COMPAL LA-4291P Schematics
5
COMPAL CONFIDENTIAL
4
3
2
1
MODEL NAME :
PCB NO :
D D
BOM P/N :
LA-4291P
46155331L01
JAZ00
MINICOOPER
C C
Intel Cantiga GS(High Performance) + ICH9M SFF
uFCBGA Mobile Penryn SFF ULV
12-07-2007
REV : 0.1(X00)
B B
@ : Nopop Component
1@ : TAA board Used only
2@ : Without TAA board Used only
A A
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
Cover sheet
LA-4291P
149Friday, Decemb er 07, 2007
1
0.1
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A
Compal confidential
Block Diagram
Model : JAZ00
1 1
DAI
USB8/USB9
SATA5
DOCK LPC BUS
E-Family
DOCKING
page 31
LVDS CONN.
RGB
On Audio/B
CRT CONN.
+5V_RUN
Vedio Switch
TS3DV520ERHUR
+3.3V_RUN
2:1 LVDS MUX
MAXIM MAX4889
+LCDVDD
On IO/B
page 20
1394 CONN.
2 2
SD/MMC CONN.
PCIE3 PCIE2 PCIE1
EXPRESS Card WWAN
+3.3V_SUS
+1.5V_RUN
+3.3V_RUN
3 3
3V/5V
page41
1.5V/1.05V
page42
1.8V/0.75V
page45
CHARGER
page46
DC IN & BATT IN
4 4
page40
WLAN
Mini Card1
+1.5V_RUN +1.5V_RUN
+3.3V_WLAN
USB[4]USB[7]
page30page35
+3.3V_RUN_BKT_PWR
Memory Card &1394
Controller
RICOH R5C833
+3.3V_RUN
Mini Card 2
+3.3V_RUN_WWAN_PWR
2:1 MUX
+3.3V_RUN_BKT_PWR
USB[5]
BKT_USBH
GPIO EXPANSION
SMSC ECE1088
+3.3V_ALW
B
RGB
RGB
page 20
DPB/DPC
LVDS
page 20
BKT_LVDS
PCI BUS
page29
PCI Express BUS
page30
WWAN_USB
SIM/UIM
page21
32M 4K section
page36
Card
W25X32VSSIG
+3.3V_LAN
BC BUS
C
INTEL
Penryn-3MB SFF ULV
+1.5V_RUN
+1.05V_VCCP
+VCC_CORE
H_A#(3..35) H_D#(0..63)
uFCBGA CPU
956pin
System Bus
FSB 800 MHz
INTEL
Cantiga GS-High Performance
+3.3V_RUN
+1.5V_MEM
+1.5V_RUN
+1.05V_M
+1.05V_VCCP
+VCC_GFXCORE
1363pin BGA
DMI*4
GFX Frequency 457/533 MHz
page 10,11,12,13,14,15
+1.5V_RUN/100MHz
INTEL
SPI
ICH9M SFF
569pin BGA
LPC BUS
BKT_USBBIO
+3.3V_RUN_BKT_PWR
page 22,23,24,25
Broadcom USH
BCM5880KFBG
+3.3V_RUN
On BIO/B
+1.5V_RUN
+RTC_CELL
+3.3V_RUN
+1.05V_VCCP
+3.3V_ALW_ICH
page30
page24
SMSC KBC
MEC5035
+RTC_CELL
+3.3V_ALW
page34
BC BUS BC BUS
SMBUS
page 7,8,9
HDA
USB[10]
USBH
2:1 MUX
BIO_USB
BIOMETRIC
page35
+5V_RUN_BKT_PWR
SILEGO SLG8LP554BV
+3.3V_M
800 MHz
Memory BUS DDR3
CHA for memory down
CHB for SO-DIMM
On BT/B
BLUETOOTH
page30
USB 2.0
USB[6] USB[0] USB[3]
HDA
GLCI/LCI
SATA0
1.8" SATA
SSD CONN.
+3.3V_RUN
page32
TERIDIAN
73S8009CN
+3.3V_RUN
page21
Touch Pad
Smart Card
+SC_VCC
page36
page35
page32
page32
D
page 6
On IO/B
USB Port
X1
Intel Boazman
+1V_LAN_M
+1.8V_LAN_M
+3.3V_LAN
LAN Switch
PI3L500-AZFEX
+3.3V_LAN
On IO/B
Transformer
+LOM_VCT
RJ45 CONN.
On BLT/B
CPU ITP PortCK505 Clock GEN
+1.05V_VCCP
page 7
1GB on Board
(128Mx8)*8pcs
DDRIII-DIMM X1
+1.5V_MEM
+V_DDR_MCH_REF
+0.75V_DDR_VTT
On Audio/B
E-SATA
page35
USB Port X1
82567LM
page28
page28
BlackTop CONN.
page 22
+FAN1_VOUT
page 16,17
page 18
SATA4
page35
Azalia Codec
IDT 92HD71B7
+VDDA
+3.3V_RUN
Dock
TI TPA6040A4
+5V_RUN_BKT_PWR
INT. Speaker
2-4W, 4OHM*1
On MIC/B
BKT SW and LED
E
FAN
GUARDIAN III
EMC4002
page 19
BKT_Audio
+3.3V_M
Inverting Buffer & Driver
TI SN74HC368PWR
+3.3V_RUN_BKT_PWR
Headphone AMP.
ADI SSM2602
page26
+3.3V_RUN_BKT_PWR
On MIC/B
Dig. MIC
On Audio/B
MIC
HeadPhone
& MIC Jack
HP
Audio AMP.
page27
page27
page 19
page26
page26
Dock
BKT_SPK
VCORE (IMVP-6)
GFX VCC CORE
page43
page44
KBD Scan extension
INT. KBD
page36
A
B
SMSC ECE1077
+3.3V_ALW
page36
SUPER I/O
SMSC ECE5028
+3.3V_ALW
page33
C
DOCK LPC BUS
Title
Size Document Number Rev
D
Date: Sheet
Compal Electronics, Inc.
Block Diagram
LA-4291P
249Friday, Decemb er 07, 2007
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DELL CONFIDENTIAL/PROPRIETARY
5
4
3
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1
POWER STATES
State
D D
C C
S0 (Full ON) / M0
S3 (Suspend to RAM) / M1
S4 (Suspend to DISK) / M1 ON ON ON ON
S5 (SOFT OFF) / M1 ON ON ON ON
S3 (Suspend to RAM) / M-OFF
S4 (Suspend to DISK) / M-OFF
S5 (SOFT OFF) / M-OFF
Signal
SLP
SLP
S3#
S4#
HIGH HIGH HIGH
HIGH
HIGH HIGH HIGH ON ON ON ON
LOW
HIGH HIGH HIGH
LOW
HIGH
LOW
HIGH HIGH HIGH
LOW
LOW LOW LOW LOW
LOW LOW LOW LOW LOW
SLP
S5#
LOW
HIGH
S4
STATE#
LOW
LOW
ALWAYS
SLP
PLANE
M#
ON
HIGH
HIGH
HIGH
ON ON
LOW
ON
ON
M
PLANE
ON
OFF
OFF
OFF
SUS
RUN
PLANE
PLANE
ON ON ON
OFF
OFF
OFF
OFF
OFF
OFFOFF
CLOCKS
OFFOFF
OFF
OFF
USB PORT#
0
1
2
3
4
5
6
7
8
9
11
JUSB (Ext Right Side)
NONE
NONE
JESATA (Ext Left Side)
WLAN
WWAN
BT
Express card
DOCKING
DOCKING
USH->BIO10
NONE
DESTINATION
PM TABLE
+15V_ALW
+5V_ALW
power
plane
State
S0
S3
B B
S5 S4/AC
S5 S4/AC don't exist
BLT mode ON OFFOFFOFF ON
+3.3V_ALW
+3.3V_ALW_ICH
+3.3V_RTC_LDO
+1.5V_ALW_HDA
ON
ON
+3.3V_SUS
+1.5V_MEM
+5V_RUN
+3.3V_RUN
+1.8V_RUN
+1.5V_RUN
+0.75V_DDR_VTT
+VCC_GFXCORE
+VCC_CORE
+1.05V_VCCP
ON ON
ON
OFF
OFFOFF
OFFON
OFF
OFF
+3.3V_M +3.3V_M
+1.05V_M +1.05V_M
ON
ON
ON
(M-OFF)
ON
OFF
OFF
OFFOFF
OFF
+3.3V_RUN_BKT_PWR +3.3V_BKT_PWR
+5V_RUN_BKT_PWR
+3.3V_RUN_WWAN_PWR
+INV_PWR_SRC
+LCDVDD
ON
OFF
OFF
OFF
OFF
OFF
OFF
OFF
ON
PCI EXPRESS
Lane 1
Lane 2
Lane 3
Lane 4
Lane 5
Lane 6
DESTINATION
MINI CARD-2 WWAN
MINI CARD-1 WLAN
None
EXPRESS CARD
None
Giga LAN
SAT A DESTINATION
SSDSATA0
PCI TABLE
REQ#/GNT#
PIRQPCI DEVICE IDSEL
SATA1
SATA4
SATA5
A A
R5C833 REQ#1 / GNT#1AD17
PIRQ[C..D]
None
ESATA
DOCKING
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
Index and Config.
LA-4291P
349Friday, Decemb er 07, 2007
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RUN_ON
ADAPTER
D D
GFX_VR_ON
ALWON
+PWR_SRC
FDS4435
Q33
ADP3209
(PU7)
SN0608098
(PU2)
+INV_PWR_SRC
(12.8V to 20V)
+VGFX_COREP
(1.05V)
+5V_ALW
BAT54SW (PD10/PD11)
+15V_ALW
BATTERY
STS11NF30L
(Q52)
CHARGER
C C
ALWON
+5V_RUN
RUN_ON
SN0608098
SI3456BDV
(Q95)
+5V_RUN_BKT_PWR
RUN_ON
BKT_GPIO4
TPA6040A (U28)
+VDDA
RUN_ON/AUD_AMP_MUTE#
+3.3V_ALW
VT351FCX
+1.5V_MEM
SI4336DY
+1.5V_RUN
1.5V_RUN_ON
(PU4)
EN_1.5VALW
(Q118)
(PU8)TPS51100
+0.75V_DDR_VTT
0.75V_VTT_ON
DDR_ON
VT351FCX
+1.05V_M
SI4336DY
+1.05V_VCCP
1.05V_RUN_ON
(PU3)
EN_1.05VALW
(Q56)
(PU2)
B B
SI345BVD
(Q55)
+3.3V_M
M_ON
SI34536BDV
SI3456BDV
(Q92)
+3.3V_RUN_BKT_PWR
3.3V_RUN_ON
BKT_GPIO3
A A
ADP3207 (PU6)
+3.3V_ALW_ICH
ICH_ALW
+VCC_CORE
STS11NF30L
+3.3V_SUS
SUS_ON
(Q51)
(Q53)
SI4336DY
+3.3V_RUN
3.3V_RUN_ON
SI4336DY (Q89)
+3.3V_RUN_WWAN_PWR
3.3V_RUN_ON
BKT_GPIO15
(Q54)
MAX8794
+1.8V_RUN
1.8V_RUN_ON
(PU9)
SI4336DY
+3.3V_WLAN
AUX_EN_WOWL
(Q48)
MAX8794
+LCDVDD
EN_VDD
BKT_GPIO2
STS11NF30L
AUX_ON
(Q31)
(Q40)
+3.3V_LAN
SI3456BDV
(PU12)
+1.5V_ALW_HDA
ICH_ALW
ADP3419 (PU5)
DELL CONFIDENTIAL/PROPRIETARY
RUNPWROK
5
4
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
Power Rails
LA-4291P
449Friday, Decemb er 07, 2007
1
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5
C18
ICH_SMBCLK
ICH_SMBDATA
C15
D D
ICH9-M
E18
A24
AMT_SMBCLK
AMT_SMBDAT
2.2K
2.2K
2.2K
2.2K
4
+3.3V_ALW_ICH
2N7002
2N7002
+3.3V_ALW_ICH
3
2.2K
2.2K
MEM_SDATA
+3.3V_ALW_M
202
MEM_SCLK 200
2
1
SMBUS Addr es s [A0]JDIMM
6
5
SMBUS Address [TBD]On board SPD ROM
9493
DOCK_SMB_CLK
6
DOCK_SMB_DAT
5
2.2K
+3.3V_ALW
127
129
SMBUS Address [TBD]DOCKING
2.2K
2.2K
2.2K
PBAT_SMBCLK 7
C C
112
111
PBAT_SMBDAT
2.2K
ALS_SMBCLK
10
ALS_SMBDAT
9
2.2K
2.2K
BKT_SMBCLK
100
99
BKT_SMBDAT
KBC
2.2K
2.2K
LCD_SMBCLK
B B
MEC 5035
8
7
LCD_SMBDATA
9897CARD_SMBCLK
2.2K
CARD_SMBDAT
+3.3V_ALW
100 ohm
100 ohm
+3.3V_ALW
2N7002
2N7002
+3.3V_ALW
+3.3V_ALW
+3.3V_ALW
6
CAPSW_ALS_SMBCLK
CAPSW_ALS_SMBDAT
27
29
24
23
SMBUS Address [TBD]JLVDS
SMBUS Address [16]BATT CONN
2.2K
2.2K
+3.3V_RUN_BKT_PWR
5
2 Ambie n t light sensor
SMBUS Address [TBD]
11
CAP Switch Controller12
SMBUS Address [TBD]
SMBUS Address [TBD]BlackTop CONN
2.2K
+3.3V_SUS
6
7
Express Card S MBUS Address [10H]
+3.3V_WLAN
30
WLAN32
SMBUS Address [TBD]
2N7002
2N7002
2N7002
2N7002
2.2K
EXP_SMBCLK
EXP_SMBDATA
2.2K
2.2K
WLAN_SMBCLK
WLAN_SMBDATA
2.2K
2.2K
2.2K
A A
CKG_SMBCLK
1213CKG_SMBDAT
10
9
CHARGER
SMBUS Address [12]
5
4
+3.3V_ALW
2N7002
2N7002
2N7002
2N7002
2.2K
CLK_SCLK
CLK_SDATA CLOCK GE N
DAI_SMBCLK
DAI_SMBDATA DAI
2.2K
3
+3.3V_M
16
17
28
27
SMBUS Address [D2]
SMBUS Address [TBD]
+3.3V_RUN_BKT_PWR
2N7002
2N7002
2
WWAN_SMBCLK
WWAN_SMBDATA
+3.3V_RUN_WWAN_PWR
30
WWAN
32
SMBUS Address [TBD]
DELL CONFIDENTIAL/PROPRIETARY
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
SMBus Topology
LA-4291P
549Friday, Decemb er 07, 2007
1
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0.1
5
4
3
2
1
+3.3V_M
+3.3V_M
6 1
Q1A
2N7002DW-7-F_SOT363-6~D
2
5
Q1B
2N7002DW-7-F_SOT363-6~D
3
4
D D
CKG_SMBDAT<26,34,46>
CKG_SMBCLK<26,34,46>
2.2K_0402_5%~D
2.2K_0402_5%~D
12
R1
12
R2
CLK_SDATA
CLK_SCLK
Place close to U1 pin 18 and 40
C16
12
CPU_MCH_BSEL0<8,10>
CPU_MCH_BSEL1<8,10>
CLK_PCI_DOCK<31>
CLK_PCI_5028<33>
CLK_PCI_R5C833<29>
CLK_PCI_5035<34>
CLK_ICH_14M<24>
CLK_SIO_14M<33>
MCH_DREFCLK<10>
MCH_DREFCLK#<10>
CLK_PCI_ICH<22>
33P_0402_50V8J~D
33P_0402_50V8J~D
CLK_ICH_48M<24>
CLK_PCI_TPM<32>
Place crystal within
500 mils of CK505
C C
CPU_MCH_BSEL2<8,10>
B B
A A
+3.3V_RUN
R45
1 2
+3.3V_RUN
R50
1 2
12
R58
10K_0402_5%~D
10K_0402_5%~D
10K_0402_5%~D
PCI_PCM
PCI_ICH
PCI_SIO
TME0PIN 32
Overclocking enable
*
ITP_EN
Overclocking disable1
PIN 37
01Pin 5/6 as SRC_10
*
Pin 5/6 as CP U_ITP
FCTSEL1 PIN43 PIN44 PIN47 PIN48
0=UMA
*
1=DIS
5
DOT96T DOT96C 96/100M_T 96/100M_C
27M_out 27M SSout SRCT0 SRCC0
12
Y6
C17
CLK_ICH_48M FSA
CPU_MCH_BSEL0
CPU_MCH_BSEL1
CPU_MCH_BSEL2
CLK_PCI_TPM
CLK_PCI_R5C833
CLK_PCI_DOCK
CLK_PCI_5035 PCI_EC
CLK_ICH_14M
CLK_SIO_14M
MCH_DREFCLK
MCH_DREFCLK#
14.31818MHZ_20PF_1Y714318CE1B~D
12
R21 33_0402_5%~D
R23 2.2K_0402_5%~D
R25 10K_0402_5%~D
R27 33_0402_5%~D
R28 33_0402_5%~D
R31 22_0402_5%~D
R33 22_0402_5%~D
R34 33_0402_5%~D
R35 22_0402_5%~D
R37 22_0402_5%~D
R40 33_0402_5%~D
R41 33_0402_5%~D
R44 33_0402_5%~D
4
+3.3V_M
R19 0_0402_5%~D
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
BLM21AG601SN1D_0805~D
0.1U_0402_16V4Z~D
1
C1
2
12
12
12
12
12
CLK_PWRGD<24>
1 2
C12
L1
C9
0.047U_0402_16V4Z~D
1
2
0.1U_0402_16V4Z~D
1
C10
2
0.047U_0402_16V4Z~D
1
C13
2
CLK_XTAL_IN
CLK_XTAL_OUT
FSC
PCI_SIOCLK_PCI_5028
PCI_TPM
PCI_PCM
CLKREF
DOT96
DOT96#
PCI_ICHCLK_PCI_ICH
CLK_PWRGD
CLK_SCLK
CLK_SDATA
+CK_VDD_MAIN
0.1U_0402_16V4Z~D
1
2
C2
49
54
65
30
36
12
18
40
20
19
41
45
23
34
33
32
27
22
43
44
37
39
16
17
15
21
31
35
42
68
73
C4
2
2
U1
1
VDD_SRC
VDD_SRC
VDD_SRC
SLG8LP554BVTR
VDD_SRC
VDD_PCI
VDD_PCI
VDD_CPU
VDD_REF
VDD_48
XTAL_IN
XTAL_OUT
USB_48MHz/FSLA
FSL_B/TEST_MODE
REF_0/FSL_C/TEST_SEL
PCICLK4/FCT_SEL
PCICLK3
PCICLK2/TME
PCICLK1
REF_1
DOT_96/27M
DOT_96#/27M_SS
PCICLK_F0/ITP_EN
CKPWRGD/PD#
9
NC
SMBCLK
SMBDAT
4
VSS_SRC
VSS_CPU
VSS_REF
VSS_PCI
VSS_PCI
VSS_48
VSS_SRC
THRM_PAD
SLG8LP554BVTR_QFN72_10X10~D
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
0.1U_0402_16V4Z~D
10U_0805_6.3V6-M~D
1
1
C3
0.1U_0402_16V4Z~D
1
1
C5
2
2
R12
1 2
2.2_0603_5%~D
0.1U_0402_16V4Z~D
C6
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
1
1
C7
2
2
+CK_VDD_A
VDD_A
VSS_A
PCI_STP#
CPU_STP#
CPU_1
CPU_1#
CPU_0
CPU_0#
CPU_ITP/SRC_10
CPU_ITP#/SRC_10#
SRC_9
SRC_9#
CLKREQ_9#
SRC_8
SRC_8#
CLKREQ_8#
SRC_7
SRC_7#
CLKREQ_7#
SRC_6
SRC_6#
CLKREQ_6#
SRC_5
SRC_5#
CLKREQ_5#
SRC_4
SRC_4#
CLKREQ_4#
SRC_3
SRC_3#
CLKREQ_3#
SRC_2
SRC_2#
CLKREQ_2#
SRC_1/SATA
SRC_1#/SATA#
CLKREQ_1#
LCD_CLK/SRC_0
LCD_CLK#/SRC_0#
0.047U_0402_16V4Z~D
4.7U_0603_6.3V4Z~D
C15
C14
1
1
2
2
7
8
25
24
11
10
14
13
6
5
3
2
72
70
69
71
66
67
38
63
64
62
60
61
29
58
59
57
55
56
28
52
53
26
50
51
46
47
48
H_STP_PCI#
H_STP_CPU#
CLK_MCH_BCLK
CLK_MCH_BCLK#
CLK_CPU_BCLK
CLK_CPU_BCLK#
CLK_CPU_ITP
CLK_CPU_ITP#
CLK_PCIE_MINI2
CLK_PCIE_MINI2#
MINI2CLK_REQ#
CLK_PCIE_MINI1
CLK_PCIE_MINI1#
MINI1CLK_REQ#
CLK_PCIE_ICH
CLK_PCIE_ICH#
CLK_PCIE_EXP
CLK_PCIE_EXP#
EXPCLK_REQ#
CLK_MCH_3GPLL
CLK_MCH_3GPLL#
CLK_3GPLLREQ#_R
CLK_PCIE_SATA
CLK_PCIE_SATA#
SATA_CLKREQ#_R
DREF_SSCLK
DREF_SSCLK#
1 2
475_0402_1%~D
1 2
475_0402_1%~D
2
H_STP_PCI# <24>
H_STP_CPU# <24>
CLK_MCH_BCLK <10>
CLK_MCH_BCLK# <10>
CLK_CPU_BCLK <7>
CLK_CPU_BCLK# <7>
CLK_CPU_ITP <7>
CLK_CPU_ITP# <7>
CLK_PCIE_MINI2 <30>
CLK_PCIE_MINI2# <30>
MINI2CLK_REQ# <30>
CLK_PCIE_MINI1 <30>
CLK_PCIE_MINI1# <30>
MINI1CLK_REQ# <30>
CLK_PCIE_ICH <24>
CLK_PCIE_ICH# <24>
CLK_PCIE_EXP <35>
CLK_PCIE_EXP# <35>
EXPCLK_REQ# <35>
CLK_MCH_3GPLL <10>
CLK_MCH_3GPLL# <10>
R51
CLK_PCIE_SATA <23>
CLK_PCIE_SATA# <23>
R55
DREF_SSCLK <10>
DREF_SSCLK# <10>
FSC
CLKSEL2
0
*
0
MINI2CLK_REQ#
MINI1CLK_REQ#
EXPCLK_REQ#
CLK_3GPLLREQ#
SATA_CLKREQ#
CLK_3GPLLREQ# <10>
SATA_CLKREQ# <24>
CLKSEL1
10
1
R6 10K_0402_5%~D
R5 10K_0402_5%~D
R10 10K_0402_5%~D
R7 10K_0402_5%~D
R8 10K_0402_5%~D
FSAFSB
CLKSEL0
00
0
1
1 2
1 2
1 2
1 2
1 2
CPU
MHz
266
200
166
DELL CONFIDENTIAL/PROPRIETARY
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
Clock GEN. with internal terminations
LA-4291P
1
SRC
MHz
100
100
100
649Friday, Decemb er 07, 2007
PCI
MHz
33.3
33.3
33.3
+3.3V_RUN
of
0.1
5
H_A#[3..35]<10>
D D
H_ADSTB#0<10>
H_REQ#0<10>
H_REQ#1<10>
H_REQ#2<10>
H_REQ#3<10>
H_REQ#4<10>
C C
H_ADSTB#1<10>
H_A20M#<23>
H_FERR#<23>
H_IGNNE#<23>
H_STPCLK#<23>
H_INTR<23>
H_NMI<23>
H_SMI#<23>
B B
H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_ADSTB#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35 H_THERMDA
H_ADSTB#1
H_A20M#
H_FERR#
H_IGNNE#
H_STPCLK#
H_INTR
H_NMI
H_SMI#
U62A
P2
A[3]#
V4
A[4]#
AG1
AM4
AM2
AG5
W1
AA1
AB4
AC5
AD2
AD4
AA5
AE5
AB2
AC1
W5
AN1
AK4
AT4
AK2
AT2
AH2
AF4
AJ5
AH4
AP4
AR5
AJ1
AL1
AU5
AP2
AR1
AN5
F10
AL5
ADDR GROUP 0
A[5]#
T4
A[6]#
A[7]#
A[8]#
T2
A[9]#
A[10]#
A[11]#
A[12]#
A[13]#
A[14]#
A[15]#
A[16]#
Y4
ADSTB[0]#
R1
REQ[0]#
R5
REQ[1]#
U1
REQ[2]#
P4
REQ[3]#
REQ[4]#
A[17]#
ADDR GROUP 1
A[18]#
A[19]#
A[20]#
A[21]#
A[22]#
A[23]#
A[24]#
A[25]#
A[26]#
A[27]#
A[28]#
A[29]#
A[30]#
A[31]#
A[32]#
THERMAL
A[33]#
A[34]#
A[35]#
ADSTB[1]#
C7
A20M#
ICH
D4
FERR#
THERMTRIP#
IGNNE#
F8
STPCLK#
C9
C5
E5
V2
Y2
J9
F4
H8
H CLK
LINT0
LINT1
SMI#
RSVD01
RSVD02
RSVD03
RSVD04
RSVD05
RSVD06
RSVD07
PENRYN SFF_UFCBGA956~D
ADS#
BNR#
BPRI#
DEFER#
DRDY#
DBSY#
BR0#
IERR#
INIT#
CONTROL
LOCK#
RESET#
RS[0]#
RS[1]#
RS[2]#
TRDY#
HIT#
HITM#
BPM[0]#
BPM[1]#
BPM[2]#
BPM[3]#
PRDY#
PREQ#
TCK
TDO
TMS
XDP/ITP SIGNALS
TRST#
DBR#
PROCHOT#
THERMDA
THERMDC
BCLK[0]
BCLK[1]
TDI
RESERVED
Layout Note: for ITP700Flex debug port with a XDP based Run Control Tools
ITP_BPM#[0..5], TCK, and TMS routings
must be a maximum of 1.5ns = 7500 mil
4
H_ADS#
M4
J5
L5
N5
F38
J1
M2
B40
D8
N1
G5
K2
H4
K4
L1
H2
F2
AY8
BA7
BA5
AY2
AV10
AV2
AV4
AW7
AU1
AW5
AV8
J7
D38
BB34
BD34
B10
A35
C35
H_BNR#
H_BPRI#
H_DEFER#
H_DRDY#
H_DBSY#
H_BR0#
H_IERR#
H_INIT#
H_LOCK#
H_RESET#
H_RS#0H_REQ#0
H_RS#1
H_RS#2
H_TRDY#
H_HIT#
H_HITM#
ITP_BPM#0
ITP_BPM#1
ITP_BPM#2
ITP_BPM#3
ITP_BPM#4
ITP_BPM#5
ITP_TCK
ITP_TDI
ITP_TDO
ITP_TMS
ITP_TRST#
ITP_DBRESET#
EC_CPU_PROCHOT#
H_THERMDC
H_THERMTRIP#
CLK_CPU_BCLK
CLK_CPU_BCLK#
+1.05V_VCCP
56_0402_5%~D
1 2
+1.05V_VCCP
51_0402_5%~D
1 2
R63
R64
H_ADS# <10>
H_BNR# <10>
H_BPRI# <10>
H_DEFER# <10>
H_DRDY# <10>
H_DBSY# <10>
H_BR0# <10>
R59 56_0402_5%~D
H_INIT# <23>
H_LOCK# <10>
H_RESET# <10>
H_RS#0 <10>
H_RS#1 <10>
H_RS#2 <10>
H_TRDY# <10>
H_HIT# <10>
H_HITM# <10>
R1077
0_0402_5%~D
1 2
1 2
R1078
0_0402_5%~D
ITP_DBRESET# <24>
2
C19
100P_0402_50V8K~D@
1
H_THERMTRIP# <19>
CLK_CPU_BCLK <6>
CLK_CPU_BCLK# <6>
H_THERMDA, H_THERMDC routing together,
Trace width / Spacing = 10 / 10 mil
H_THERMTRIP#
ITP_BPM#5
Place close to CPU within 200 mil
+1.05V_VCCP
R67
51_0402_5%~D
1 2
R69
51_0402_5%~D
1 2
ITP_TDI
ITP_TRST#
Place close to CPU within 200ps = 1000 mil
12
ITP_BPM_R#3
ITP_BPM_R#5
+1.05V_VCCP
+1.05V_VCCP
12
R61
56_0402_5%~D
H_THERMDA <19>
H_THERMDC <19>
3
+1.05V_VCCP
1
C18
0.1U_0402_16V4Z~D
2
Place close to JITP within 100 mil
H_RESET#
CLK_CPU_ITP<6>
CLK_CPU_ITP#<6>
R60
1 2
1K_0402_5%~D
2
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
JITP
VTT1
VTT0
VTAP
DBR#
DBA#
BPM0#
GND5
BPM1#
GND4
BPM2#
GND3
BPM3#
GND2
BPM4#
GND1
BPM5#
RESET#
FBO
GND0
BCLKP
BCLKN
TDO
NC2
TCK
NC1
TRST#
TMS
TDI
ITP_DBRESET#
29
30
GND6
GND7
MOLEX_52435-2891_28P~D@
+1.05V_VCCP
ITP_DBRESET#
ITP_BPM#0
ITP_BPM#1
ITP_BPM#2
ITP_BPM_R#3
ITP_BPM#4
ITP_BPM_R#5
ITP_TCK
CLK_CPU_ITP
CLK_CPU_ITP#
ITP_TDO
ITP_TCK
ITP_TRST#
ITP_TMS
ITP_TDI
+3.3V_ALW_ICH
150_0402_5%~D
1 2
R62
Place close to JITP within 1ns = 5000 mil
+1.05V_VCCP
R65
51_0402_5%~D@
1 2
51_0402_5%~D
1 2
51_0402_5%~D
1 2
51_0402_5%~D
1 2
H_RESET#
R66
ITP_TDO
R68
ITP_TMS
R70
ITP_TCK
1
U62D
B42
VSS[001]
F44
VSS[002]
D44
VSS[003]
D42
VSS[004]
F42
VSS[005]
H42
VSS[006]
K42
VSS[007]
M42
VSS[008]
P42
VSS[009]
T42
VSS[010]
V42
VSS[011]
Y42
VSS[012]
AB42
VSS[013]
AD42
VSS[014]
AF42
VSS[015]
AH42
VSS[016]
AK42
VSS[017]
AM42
VSS[018]
AP42
VSS[019]
AY44
VSS[020]
AV44
VSS[021]
AT42
VSS[022]
AV42
VSS[023]
AY42
VSS[024]
BA43
VSS[025]
BB42
VSS[026]
C39
VSS[027]
E39
VSS[028]
G37
VSS[029]
H38
VSS[030]
J39
VSS[031]
L39
VSS[032]
M38
VSS[033]
N39
VSS[034]
R39
VSS[035]
T38
VSS[036]
U39
VSS[037]
W39
VSS[038]
Y38
VSS[039]
AA39
VSS[040]
AC39
VSS[041]
AD38
VSS[042]
AE39
VSS[043]
AG39
VSS[044]
AH38
VSS[045]
AJ39
VSS[046]
AL39
VSS[047]
AM38
VSS[048]
AN39
VSS[049]
AR39
VSS[050]
AR37
VSS[051]
AT38
VSS[052]
AU39
VSS[053]
AU37
VSS[054]
AW39
VSS[055]
AW37
VSS[056]
BA39
VSS[057]
BC41
VSS[058]
BD40
VSS[059]
BD38
VSS[060]
B36
VSS[061]
H34
VSS[062]
D36
VSS[063]
K34
VSS[064]
M34
VSS[065]
M36
VSS[066]
P34
VSS[067]
T34
VSS[068]
V34
VSS[069]
T36
VSS[070]
Y34
VSS[071]
AB34
VSS[072]
AD34
VSS[073]
Y36
VSS[074]
AD36
VSS[075]
AF34
VSS[076]
AH34
VSS[077]
AH36
VSS[078]
AK34
VSS[079]
AM34
VSS[080]
AP34
VSS[081]
PENRYN SFF_UFCBGA956~D
VSS[082]
VSS[083]
VSS[084]
VSS[085]
VSS[086]
VSS[087]
VSS[088]
VSS[089]
VSS[090]
VSS[091]
VSS[092]
VSS[093]
VSS[094]
VSS[095]
VSS[096]
VSS[097]
VSS[098]
VSS[099]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
VSS[159]
VSS[160]
VSS[161]
VSS[162]
VSS[163]
AM36
AR35
AU35
AV34
AW35
AW33
AY34
AT36
AV36
BA33
BC33
BB36
BD36
C27
C29
C31
E29
E27
G29
G27
E31
G31
J29
J27
L29
L27
N29
N27
J31
L31
N31
R29
R27
U29
U27
R31
U31
W29
W27
W31
AA29
AA27
AC29
AC27
AA31
AC31
AE29
AE27
AG29
AG27
AJ29
AJ27
AE31
AG31
AJ31
AL29
AL27
AN29
AN27
AL31
AN31
AR29
AR27
AR31
AU29
AU27
AW29
AW27
AU31
AW31
BA29
BA27
BC29
BC27
BA31
BC31
C21
C23
C25
E25
E23
E21
Place close to JITP within 200ps = 1000 mil
ITP_BPM#[0..5], and TCK to FBO routings
must be length matched to within 50ps = 250 mil
Place R70 close to JITP pin 5
A A
TCK to FBO routing should refer to debug port design guide
H_RESET# should be routed from GMCH with split to ITP conn. Refer to DG page #56
Depop JITP, C18, R68, R70, R64, R67, R69
when JIP connector is depopulated
5
4
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
DELL CONFIDENTIAL/PROPRIETARY
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
Penryn SFF ULV Processor(1/3)
LA-4291P
749Friday, Decemb er 07, 2007
1
of
0.1
5
4
3
2
1
H_D#[0..63]<10>
H_D#0
H_D#1
H_D#2
D D
H_DSTBN#0<10>
H_DSTBP#0<10>
H_DINV#0<10>
C C
B B
*
H_DSTBN#1<10>
H_DSTBP#1<10>
H_DINV#1<10>
+V_CPU_GTLREF
T1
CPU_MCH_BSEL0<6,10>
CPU_MCH_BSEL1<6,10>
CPU_MCH_BSEL2<6,10>
FSB BSEL2 BSEL0
BCLK BSEL1
166
667
800 200
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_DSTBN#0
H_DSTBP#0
H_DINV#0 H_DINV#2
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_DSTBN#1
H_DSTBP#1
H_DINV#1 H_DINV#3
TEST1
TEST2
TEST3
TEST4
TEST5
TEST6
CPU_MCH_BSEL0
CPU_MCH_BSEL1
CPU_MCH_BSEL2
1
0
01
01067 266
0
U62B
F40
D[0]#
G43
D[1]#
E43
D[2]#
J43
D[3]#
H40
D[4]#
H44
D[5]#
G39
D[6]#
E41
D[7]#
L41
D[8]#
K44
D[9]#
N41
D[10]#
T40
D[11]#
M40
D[12]#
G41
D[13]#
M44
D[14]#
L43
D[15]#
K40
DSTBN[0]#
J41
DSTBP[0]#
P40
DINV[0]#
P44
D[16]#
V40
D[17]#
V44
D[18]#
AB44
D[19]#
R41
D[20]#
W41
D[21]#
N43
D[22]#
U41
D[23]#
AA41
D[24]#
AB40
D[25]#
AD40
D[26]#
AC41
D[27]#
AA43
D[28]#
Y40
D[29]#
Y44
D[30]#
T44
D[31]#
U43
DSTBN[1]#
W43
DSTBP[1]#
R43
DINV[1]#
AW43
GTLREF
E37
TEST1
D40
TEST2
C43
TEST3
AE41
TEST4
AY10
TEST5
AC43
TEST6
A37
BSEL[0]
C37
BSEL[1]
B38
BSEL[2]
PENRYN SFF_UFCBGA956~D
1
0
0
D[32]#
D[33]#
D[34]#
DATA GROUP 0
D[35]#
D[36]#
D[37]#
D[38]#
D[39]#
D[40]#
D[41]#
D[42]#
D[43]#
D[44]#
D[45]#
DATA GROUP 2DATA GROUP 3
D[46]#
D[47]#
DSTBN[2]#
DSTBP[2]#
DINV[2]#
D[48]#
D[49]#
D[50]#
D[51]#
DATA GROUP 1
D[52]#
D[53]#
D[54]#
D[55]#
D[56]#
D[57]#
D[58]#
D[59]#
D[60]#
D[61]#
D[62]#
D[63]#
DSTBN[3]#
DSTBP[3]#
DINV[3]#
COMP[0]
MISC
COMP[1]
COMP[2]
COMP[3]
DPRSTP#
DPSLP#
DPWR#
PWRGOOD
SLP#
PSI#
T2
T3
Route TEST3 and TEST5 signals
through a ground referenced Z0 = 55ohm
trace that ends in a via that is near a GND via.
AR43
AH40
AF40
AJ43
AG41
AF44
AH44
AM44
AN43
AM40
AK40
AG43
AP40
AN41
AL41
AK44
AL43
AJ41
AV38
AT44
AV40
AU41
AW41
AR41
BA37
BB38
AY36
AT40
BC35
BC39
BA41
BB40
BA35
AU43
AY40
AY38
BC37
AE43
AD44
AE1
AF2
G7
B8
C41
E7
D10
BD10
TEST3
TEST5
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_DSTBN#2
H_DSTBP#2
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
H_DSTBN#3
H_DSTBP#3
COMP0
COMP1
COMP2
COMP3
H_DPRSTP#
H_DPSLP#
H_DPWR#
H_PWRGOOD
H_CPUSLP#
H_PSI#
H_DPRSTP# <10,23,43>
H_DPSLP# <23>
H_DPWR# <10>
H_PWRGOOD <23>
H_CPUSLP# <10>
H_PSI# <43>
H_D#32
AP44
H_DSTBN#2 <10>
H_DSTBP#2 <10>
H_DINV#2 <10>
H_DSTBN#3 <10>
H_DSTBP#3 <10>
H_DINV#3 <10>
27.4_0402_1%~D
54.9_0402_1%~D
12
12
R72
R71
Resistor placed within 0.5" of CPU
pin.Trace should be at least 25
mils away fro m a n y other toggling
signal. COMP0, COMP2 trace
should be 27.4 ohm. COMP1,
COMP3 should be 55ohm.
R73
27.4_0402_1%~D
54.9_0402_1%~D
12
12
R74
+VCC_CORE +VCC_CORE
U62C
F32
VCC[001]
G33
VCC[002]
H32
VCC[003]
J33
VCC[004]
K32
VCC[005]
L33
VCC[006]
M32
VCC[007]
N33
VCC[008]
P32
VCC[009]
R33
VCC[010]
T32
VCC[011]
U33
VCC[012]
V32
VCC[013]
W33
VCC[014]
Y32
VCC[015]
AA33
VCC[016]
AB32
VCC[017]
AC33
VCC[018]
AD32
VCC[019]
AE33
VCC[020]
AF32
VCC[021]
AG33
VCC[022]
AH32
VCC[023]
AJ33
VCC[024]
AK32
VCC[025]
AL33
VCC[026]
AM32
VCC[027]
AN33
VCC[028]
AP32
VCC[029]
AR33
VCC[030]
AT34
VCC[031]
AT32
VCC[032]
AU33
VCC[033]
AV32
VCC[034]
AY32
VCC[035]
BB32
VCC[036]
BD32
VCC[037]
B28
VCC[038]
B30
VCC[039]
B26
VCC[040]
D28
VCC[041]
D30
VCC[042]
F30
VCC[043]
F28
VCC[044]
H30
VCC[045]
H28
VCC[046]
D26
VCC[047]
F26
VCC[048]
H26
VCC[049]
K30
VCC[050]
K28
VCC[051]
M30
VCC[052]
M28
VCC[053]
K26
VCC[054]
M26
VCC[055]
P30
VCC[056]
P28
VCC[057]
T30
VCC[058]
T28
VCC[059]
V30
VCC[060]
V28
VCC[061]
P26
VCC[062]
T26
VCC[063]
V26
VCC[064]
Y30
VCC[065]
Y28
VCC[066]
AB30
VCC[067]
PENRYN SFF_UFCBGA956~D
VCC[068]
VCC[069]
VCC[070]
VCC[071]
VCC[072]
VCC[073]
VCC[074]
VCC[075]
VCC[076]
VCC[077]
VCC[078]
VCC[079]
VCC[080]
VCC[081]
VCC[082]
VCC[083]
VCC[084]
VCC[085]
VCC[086]
VCC[087]
VCC[088]
VCC[089]
VCC[090]
VCC[091]
VCC[092]
VCC[093]
VCC[094]
VCC[095]
VCC[096]
VCC[097]
VCC[098]
VCC[099]
VCC[100]
VCCP_001
VCCP_002
VCCP_003
VCCP_004
VCCP_005
VCCP_006
VCCP_007
VCCP_008
VCCP_009
VCCP_010
VCCP_011
VCCP_012
VCCP_013
VCCP_014
VCCP_015
VCCP_016
VCCA[01]
VCCA[02]
VID[0]
VID[1]
VID[2]
VID[3]
VID[4]
VID[5]
VID[6]
VCCSENSE
VSSSENSE
AB28
AD30
AD28
Y26
AB26
AD26
AF30
AF28
AH30
AH28
AF26
AH26
AK30
AK28
AM30
AM28
AP30
AP28
AK26
AM26
AP26
AT30
AT28
AV30
AV28
AY30
AY28
AT26
AV26
AY26
BB30
BB28
BD30
J11
E11
G11
J37
K38
L37
N37
P38
R37
U37
V38
W37
AA37
AB38
AC37
AE37
B34
D34
BD8
BC7
BB10
BB8
BC5
BB4
AY4
BD12
BC13
VID0
VID1
VID2
VID3
VID4
VID5
VID6
VCCSENSE
VSSSENSE
C20
1
+
2
+1.05V_VCCP
220U_D2_4VY_R15M~D
VID0 <43>
VID1 <43>
VID2 <43>
VID3 <43>
VID4 <43>
VID5 <43>
VID6 <43>
VCCSENSE <43>
VSSSENSE <43>
CRB is 270uF
10U_0805_10V4Z~D
0.01U_0402_16V7K~D
C22
C21
1
1
2
2
+1.5V_RUN
Length match within 25 mils, Z0=27.4 ohm
+1.05V_VCCP
12
+V_CPU_GTLREF
Layout close CPU PIN AW43
Zo = 55 ohm, 0.5 inch (max)
A A
R75
1K_0402_1%~D
12
R80
2K_0402_1%~D
1K_0402_5%~D@
R77
R76
1 2
Place C23 close to the
CPU_TEST4 pin. Make sure
CPU_TEST4 routing is
reference to GND and away
from other n o i sy signal.
TEST1
TEST2
TEST4
0.1U_0402_10V7K~D@
1K_0402_5%~D@
2
C23
1
1 2
Place R78 and R81 close to CPU within 1000 mil
+VCC_CORE
R78
1 2
100_0402_1%~D
R81
1 2
100_0402_1%~D
VCCSENSE
VSSSENSE
1 2
27.4_0402_1%~D@
Reserve for testing only
R79
Route VCCSENSE and VSSSENSE trace at 27.4 ohms with 7 mil spacing
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
Penryn SFF ULV Processor(2/3)
LA-4291P
849Friday, Decemb er 07, 2007
1
0.1
of
5
U62F
+VCC_CORE
D D
C C
B B
A A
+1.05V_VCCP
BD28
VCC_101
BB26
VCC_102
BD26
VCC_103
B22
VCC_104
B24
VCC_105
D22
VCC_106
D24
VCC_107
F24
VCC_108
F22
VCC_109
H24
VCC_110
H22
VCC_111
K24
VCC_112
K22
VCC_113
M24
VCC_114
M22
VCC_115
P24
VCC_116
P22
VCC_117
T24
VCC_118
T22
VCC_119
V24
VCC_120
V22
VCC_121
Y24
VCC_122
Y22
VCC_123
AB24
VCC_124
AB22
VCC_125
AD24
VCC_126
AD22
VCC_127
AF24
VCC_128
AF22
VCC_129
AH24
VCC_130
AH22
VCC_131
AK24
VCC_132
AK22
VCC_133
AM24
VCC_134
AM22
VCC_135
AP24
VCC_136
AP22
VCC_137
AT24
VCC_138
AT22
VCC_139
AV24
VCC_140
AV22
VCC_141
AY24
VCC_142
AY22
VCC_143
BB24
VCC_144
BB22
VCC_145
BD24
VCC_146
BD22
VCC_147
B16
VCC_148
B18
VCC_149
B20
VCC_150
D16
VCC_151
D18
VCC_152
F18
VCC_153
F16
VCC_154
H18
VCC_155
H16
VCC_156
D20
VCC_157
F20
VCC_158
H20
VCC_159
K18
VCC_160
K16
VCC_161
M18
VCC_162
M16
VCC_163
K20
VCC_164
M20
VCC_165
P18
VCC_166
P16
VCC_167
T18
VCC_168
T16
VCC_169
V18
VCC_170
V16
VCC_171
P20
VCC_172
T20
VCC_173
V20
VCC_174
Y18
VCC_175
Y16
VCC_176
AB18
VCC_177
AB16
VCC_178
AD18
VCC_179
AD16
VCC_180
Y20
VCC_181
AB20
VCC_182
AD20
VCC_183
AF18
VCC_184
AF16
VCC_185
AH18
VCC_186
AH16
VCC_187
AF20
VCC_188
AH20
VCC_189
AK18
VCC_190
AK16
VCC_191
AM18
VCC_192
AM16
VCC_193
AP18
VCC_194
AP16
VCC_195
AK20
VCC_196
AM20
VCC_197
AP20
VCC_198
AT18
VCC_199
AT16
VCC_200
AV18
VCC_201
AV16
VCC_202
AY18
VCC_203
AY16
VCC_204
AT20
VCC_205
AV20
VCC_206
AY20
VCC_207
BB18
VCC_208
BB16
VCC_209
BD18
VCC_210
BD16
VCC_211
BB20
VCC_212
BD20
VCC_213
AM14
VCC_214
AP14
VCC_215
AT14
VCC_216
AV14
VCC_217
AY14
VCC_218
BB14
VCC_219
BD14
VCC_220
AF38
VCCP_017
AG37
VCCP_018
AJ37
VCCP_019
AK38
VCCP_020
PENRYN SFF_UFCBGA956~D
5
VCCP_021
VCCP_022
VCCP_023
VCCP_024
VCCP_025
VCCP_026
VCCP_027
VCCP_028
VCCP_029
VCCP_030
VCCP_031
VCCP_032
VCCP_033
VCCP_034
VCCP_035
VCCP_036
VCCP_037
VCCP_038
VCCP_039
VCCP_040
VCCP_041
VCCP_042
VCCP_043
VCCP_044
VCCP_045
VCCP_046
VCCP_047
VCCP_048
VCCP_049
VCCP_050
VCCP_051
VCCP_052
VCCP_053
VCCP_054
VCCP_055
VCCP_056
VCCP_057
VCCP_058
VCCP_059
VCCP_060
VCCP_061
VCCP_062
VCCP_063
VCCP_064
VCCP_065
VCCP_066
VCCP_067
VCCP_068
VCCP_069
VCCP_070
VCCP_071
VCCP_072
VCCP_073
VCCP_074
VCCP_075
VCCP_076
VCCP_077
VCCP_078
VCCP_079
VCCP_080
VCCP_081
VCCP_082
VCCP_083
VCCP_084
VCCP_085
VCCP_086
VCCP_087
VCCP_088
VCCP_089
VCCP_090
VCCP_091
VCCP_092
VCCP_093
VCCP_094
VCCP_095
VCCP_096
VCCP_097
VCCP_098
VCCP_099
VCCP_100
VCCP_101
VCCP_102
VCCP_103
VCCP_104
VCCP_105
VCCP_106
VCCP_107
VCCP_108
VCCP_109
VCCP_110
VCCP_111
VCCP_112
VCCP_113
VCCP_114
VCCP_115
VCCP_116
VCCP_117
VCCP_118
VCCP_119
VCCP_120
VCCP_121
VCCP_122
VCCP_123
VCCP_124
VCCP_125
VCCP_126
VCCP_127
VCCP_128
VCCP_129
VCCP_130
VCCP_131
VCCP_132
VCCP_133
VCCP_134
VCCP_135
VCCP_136
VCCP_137
VCCP_138
VCCP_139
VCCP_140
VCCP_141
VCCP_142
VCCP_143
VCCP_144
VCCP_145
AL37
AN37
AP38
B32
C33
D32
E35
E33
F34
G35
F36
H36
J35
L35
N35
K36
R35
U35
P36
V36
W35
AA35
AC35
AB36
AE35
AG35
AJ35
AF36
AL35
AN35
AK36
AP36
B12
B14
C13
D12
D14
E13
F14
F12
G13
H14
H12
J13
K14
K12
L13
L11
M14
N13
N11
K10
P14
P12
R13
R11
T14
U13
U11
V14
V12
W13
W11
P10
V10
Y14
AA13
AA11
AB14
AB12
AC13
AC11
AD14
AB10
AE13
AE11
AF14
AF12
AG13
AG11
AH14
AJ13
AJ11
AF10
AK14
AK12
AL13
AL11
AN13
AN11
AP12
AR13
AR11
AK10
AP10
AU13
AU11
L9
L7
N9
N7
R9
R7
U9
U7
W9
W7
AA9
AA7
AC9
AC7
AE9
AE7
AG9
AG7
AJ9
AJ7
AL9
AL7
AN9
AN7
AR9
AR7
A33
A13
+1.05V_VCCP
4
U62E
G25
VSS_164
G23
VSS_165
G21
VSS_166
J25
VSS_167
J23
VSS_168
J21
VSS_169
L25
VSS_170
L23
VSS_171
L21
VSS_172
N25
VSS_173
N23
VSS_174
N21
VSS_175
R25
VSS_176
R23
VSS_177
R21
VSS_178
U25
VSS_179
U23
VSS_180
U21
VSS_181
W25
VSS_182
W23
VSS_183
W21
VSS_184
AA25
VSS_185
AA23
VSS_186
AA21
VSS_187
AC25
VSS_188
AC23
VSS_189
AC21
VSS_190
AE25
VSS_191
AE23
VSS_192
AE21
VSS_193
AG25
VSS_194
AG23
VSS_195
AG21
VSS_196
AJ25
VSS_197
AJ23
VSS_198
AJ21
VSS_199
AL25
VSS_200
AL23
VSS_201
AL21
VSS_202
AN25
VSS_203
AN23
VSS_204
AN21
VSS_205
AR25
VSS_206
AR23
VSS_207
AR21
VSS_208
AU25
VSS_209
AU23
VSS_210
AU21
VSS_211
AW25
VSS_212
AW23
VSS_213
AW21
VSS_214
BA25
VSS_215
BA23
VSS_216
BA21
VSS_217
BC25
VSS_218
BC23
VSS_219
BC21
VSS_220
C17
VSS_221
C19
VSS_222
E19
VSS_223
E17
VSS_224
G19
VSS_225
G17
VSS_226
J19
VSS_227
J17
VSS_228
L19
VSS_229
L17
VSS_230
N19
VSS_231
N17
VSS_232
R19
VSS_233
R17
VSS_234
U19
VSS_235
U17
VSS_236
W19
VSS_237
W17
VSS_238
AA19
VSS_239
AA17
VSS_240
AC19
VSS_241
AC17
VSS_242
AE19
VSS_243
AE17
VSS_244
AG19
VSS_245
AG17
VSS_246
AJ19
VSS_247
AJ17
VSS_248
AL19
VSS_249
AL17
VSS_250
AN19
VSS_251
AN17
VSS_252
AR19
VSS_253
AR17
VSS_254
AU19
VSS_255
AU17
VSS_256
AW19
VSS_257
AW17
VSS_258
BA19
VSS_259
BA17
VSS_260
BC19
VSS_261
BC17
VSS_262
C11
VSS_263
C15
VSS_264
E15
VSS_265
G15
VSS_266
H10
VSS_267
M12
VSS_268
J15
VSS_269
L15
VSS_270
N15
VSS_271
M10
VSS_272
T12
VSS_273
R15
VSS_274
U15
VSS_275
W15
VSS_276
T10
VSS_277
Y12
VSS_278
AD12
VSS_279
PENRYN SFF_UFCBGA956~D
4
VSS_280
VSS_281
VSS_282
VSS_283
VSS_284
VSS_285
VSS_286
VSS_287
VSS_288
VSS_289
VSS_290
VSS_291
VSS_292
VSS_293
VSS_294
VSS_295
VSS_296
VSS_297
VSS_298
VSS_299
VSS_300
VSS_301
VSS_302
VSS_303
VSS_304
VSS_305
VSS_306
VSS_307
VSS_308
VSS_309
VSS_310
VSS_311
VSS_312
VSS_313
VSS_314
VSS_315
VSS_316
VSS_317
VSS_318
VSS_319
VSS_320
VSS_321
VSS_322
VSS_323
VSS_324
VSS_325
VSS_326
VSS_327
VSS_328
VSS_329
VSS_330
VSS_331
VSS_332
VSS_333
VSS_334
VSS_335
VSS_336
VSS_337
VSS_338
VSS_339
VSS_340
VSS_341
VSS_342
VSS_343
VSS_344
VSS_345
VSS_346
VSS_347
VSS_348
VSS_349
VSS_350
VSS_351
VSS_352
VSS_353
VSS_354
VSS_355
VSS_356
VSS_357
VSS_358
VSS_359
VSS_360
VSS_361
VSS_362
VSS_363
VSS_364
VSS_365
VSS_366
VSS_367
VSS_368
VSS_369
VSS_370
VSS_371
VSS_372
VSS_373
VSS_374
VSS_375
VSS_376
VSS_377
VSS_378
VSS_379
VSS_380
VSS_381
VSS_382
VSS_383
VSS_384
VSS_385
VSS_386
VSS_387
VSS_388
VSS_389
VSS_390
VSS_391
VSS_392
VSS_393
VSS_394
VSS_395
AA15
AC15
Y10
AD10
AH12
AE15
AG15
AJ15
AH10
AM12
AL15
AN15
AR15
AM10
AT12
AV12
AW13
AW11
AY12
AU15
AW15
AT10
BA13
BA11
BB12
BC11
BA15
BC15
B6
D6
E9
F6
G9
H6
K8
K6
M8
M6
P8
P6
T8
T6
V8
V6
U5
Y8
Y6
AB8
AB6
AD8
AD6
AF8
AF6
AH8
AH6
AK8
AK6
AM8
AM6
AP8
AP6
AT8
AT6
AU9
AV6
AU7
AW9
AY6
BA9
BB6
BC9
BD6
B4
C3
E3
G3
J3
L3
N3
R3
U3
W3
AA3
AC3
AE3
AG3
AJ3
AL3
AN3
AR3
AU3
AW3
BA3
BC3
D2
E1
G1
AW1
BA1
BB2
A41
A39
A29
A27
A31
A25
A23
A21
A19
A17
A11
A15
A7
A5
A9
BD4
+VCC_CORE
1
2
+VCC_CORE
1
2
+VCC_CORE
1
2
3
C1312
10U_0805_4VAM~D
C1320
10U_0805_4VAM~D
C1328
10U_0805_4VAM~D
1
C1313
10U_0805_4VAM~D
2
1
C1321
10U_0805_4VAM~D
2
1
C1329
10U_0805_4VAM~D
2
1
C1314
10U_0805_4VAM~D
2
1
C1322
10U_0805_4VAM~D
2
1
C1335
10U_0805_4VAM~D
2
1
C1315
10U_0805_4VAM~D
2
1
C1323
10U_0805_4VAM~D
2
1
C1336
10U_0805_4VAM~D
2
+VCC_CORE
1
C1330
+
2
2
1
2
1
2
1
2
470U_X_2VM_R6M~D
C1331
C1316
10U_0805_4VAM~D
C1324
10U_0805_4VAM~D
C1342
10U_0805_4VAM~D
1
+
2
Place these inside cavity on L8(North side Secondary)
+1.05V_VCCP
1
C25
0.1U_0402_10V7K~D
2
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
1
C26
0.1U_0402_10V7K~D
2
1
C27
0.1U_0402_10V7K~D
2
1
2
2
470U_X_2VM_R6M~D
470U_X_2VM_R6M~D
1
C1332
+
2
C28
0.1U_0402_10V7K~D
1
1
C1317
10U_0805_4VAM~D
2
1
C1325
10U_0805_4VAM~D
2
1
C1343
10U_0805_4VAM~D
2
1
C29
0.1U_0402_10V7K~D
2
1
C1318
10U_0805_4VAM~D
2
1
C1326
10U_0805_4VAM~D
2
1
C1344
10U_0805_4VAM~D
2
1
2
1
C1319
10U_0805_4VAM~D
2
1
C1327
10U_0805_4VAM~D
2
1
C1345
10U_0805_4VAM~D
2
C30
0.1U_0402_10V7K~D
DELL CONFIDENTIAL/PROPRIETARY
Title
Size Document Number Re v
Date: Sheet
Compal Electroni cs, Inc.
Penryn SFF ULV Processor(3/3)
LA-4291P
1
949Friday, December 07, 2007
0.1
of
5
H_D#[0..63]<8>
D D
C C
R89
1 2
24.9_0402_1%~D
H_RESET#<7>
H_CPUSLP#<8>
B B
+1.05V_VCCP
12
R97
221_0402_1%~D
H_SWNG
0.1U_0402_10V7K~D
100_0402_1%~D
12
R103
1
C35
2
A A
MCH_TSATN_EC<33>
MMST3904-7-F_SOT323-3~D
1
C34
2
H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
H_SWNG
+H_RCOMP
H_RESET#
H_CPUSLP#
+H_VREF
+1.05V_VCCP
12
+H_VREF
0.1U_0402_10V7K~D@
12
R102
+3.3V_RUN
12
R112
C
Q22
E
3 1
5
R96
1K_0402_1%~D
2K_0402_1%~D
1K_0402_5%~D
U78A
J7
H_D#_0
H6
H_D#_1
L11
H_D#_2
J3
H_D#_3
H4
H_D#_4
G3
H_D#_5
K10
H_D#_6
K12
H_D#_7
L1
H_D#_8
M10
H_D#_9
M6
H_D#_10
N11
H_D#_11
L7
H_D#_12
K6
H_D#_13
M4
H_D#_14
K4
H_D#_15
P6
H_D#_16
W9
H_D#_17
V6
H_D#_18
V2
H_D#_19
P10
H_D#_20
W7
H_D#_21
N9
H_D#_22
P4
H_D#_23
U9
H_D#_24
V4
H_D#_25
U1
H_D#_26
W3
H_D#_27
V10
H_D#_28
U7
H_D#_29
W11
H_D#_30
U11
H_D#_31
AC11
H_D#_32
AC9
H_D#_33
Y4
H_D#_34
Y10
H_D#_35
AB6
H_D#_36
AA9
H_D#_37
AB10
H_D#_38
AA1
H_D#_39
AC3
H_D#_40
AC7
H_D#_41
AD12
H_D#_42
AB4
H_D#_43
Y6
H_D#_44
AD10
H_D#_45
AA11
H_D#_46
AB2
H_D#_47
AD4
H_D#_48
AE7
H_D#_49
AD2
H_D#_50
AD6
H_D#_51
AE3
H_D#_52
AG9
H_D#_53
AG7
H_D#_54
AE11
H_D#_55
AK6
H_D#_56
AF6
H_D#_57
AJ9
H_D#_58
AH6
H_D#_59
AF12
H_D#_60
AH4
H_D#_61
AJ7
H_D#_62
AE9
H_D#_63
B6
H_SWING
D4
H_RCOMP
J11
H_CPURST#
G9
H_CPUSLP#
L17
H_AVREF
K18
H_DVREF
CANTIGA GMCH S FF _ Q R4 6 B 0_ F CBGA1363~D
SIO_SLP_S4#<24,34>
1K_0402_5%~D
12
R111
2
B
C
E
3 1
+1.05V_VCCP
R118
2
B
330_0402_5%~D
Q23
MMST3904-7-F_SOT323-3~D
1.5V_SUS_PWRGD<34,42>
12
HOST
DDR_ON<34,37,45>
12
R115
54.9_0402_1%~D
MCH_TSATN#
H_ADSTB#_0
H_ADSTB#_1
H_BREQ#
H_DEFER#
H_DBSY#
HPLL_CLK
HPLL_CLK#
H_DPWR#
H_DRDY#
H_LOCK#
H_TRDY#
H_DINV#_0
H_DINV#_1
H_DINV#_2
H_DINV#_3
H_DSTBN#_0
H_DSTBN#_1
H_DSTBN#_2
H_DSTBN#_3
H_DSTBP#_0
H_DSTBP#_1
H_DSTBP#_2
H_DSTBP#_3
H_REQ#_0
H_REQ#_1
H_REQ#_2
H_REQ#_3
H_REQ#_4
R1060
1 2
0_0402_5%~D@
Place close to pin F34,F32,B38,A37 of U78
4
H_A#3
L15
H_A#_3
H_A#_4
H_A#_5
H_A#_6
H_A#_7
H_A#_8
H_A#_9
H_A#_10
H_A#_11
H_A#_12
H_A#_13
H_A#_14
H_A#_15
H_A#_16
H_A#_17
H_A#_18
H_A#_19
H_A#_20
H_A#_21
H_A#_22
H_A#_23
H_A#_24
H_A#_25
H_A#_26
H_A#_27
H_A#_28
H_A#_29
H_A#_30
H_A#_31
H_A#_32
H_A#_33
H_A#_34
H_A#_35
H_ADS#
H_BNR#
H_BPRI#
H_HIT#
H_HITM#
H_RS#_0
H_RS#_1
H_RS#_2
+3.3V_RUN
H_A#4
B14
H_A#5
C15
H_A#6
D12
H_A#7
F14
H_A#8
G17
H_A#9
B12
H_A#10
J15
H_A#11
D16
H_A#12
C17
H_A#13
D14
H_A#14
K16
H_A#15
F16
H_A#16
B16
H_A#17
C21
H_A#18
D18
H_A#19
J19
H_A#20
J21
H_A#21
B18
H_A#22
D22
H_A#23
G19
H_A#24
J17
H_A#25
L21
H_A#26
L19
H_A#27
G21
H_A#28
D20
H_A#29
K22
H_A#30
F18
H_A#31
K20
H_A#32
F20
H_A#33
F22
H_A#34
B20
H_A#35
A19
H_ADS#
F10
H_ADSTB#0
A15
H_ADSTB#1
C19
H_BNR#
C9
H_BPRI#
B8
H_BR0#
C11
H_DEFER#
E5
H_DBSY#
D6
CLK_MCH_BCLK
AH10
CLK_MCH_BCLK#
AJ11
H_DPWR#
G11
H_DRDY#
H2
H_HIT#
C7
H_HITM#
F8
H_LOCK#
A11
H_TRDY#
D8
H_DINV#0
L9
H_DINV#1
N7
H_DINV#2
AA7
H_DINV#3
AG3
H_DSTBN#0
K2
H_DSTBN#1
N3
H_DSTBN#2
AA3
H_DSTBN#3
AF4
H_DSTBP#0
L3
H_DSTBP#1
M2
H_DSTBP#2
Y2
H_DSTBP#3
AF2
H_REQ#0
J13
H_REQ#1
L13
H_REQ#2
C13
H_REQ#3
G13
H_REQ#4
G15
H_RS#0
F4
H_RS#1
F2
H_RS#2
G7
+3.3V_M
1 2
0.1U_0402_16V4Z~D
5
1
P
A
4
Y
2
B
G
U92
3
74AHCT1G08GW SOT353~D
R94 100K_0402_5%~D
R95 100K_0402_5%~D
R99 100K_0402_5%~D
R100 100K_0402_5%~D
4
C1346
R1058
1 2
12K_0402_5%~D
12
12
12
12
H_A#[3..35] <7>
+V_DDR_MCH_REF
H_ADS# <7>
H_ADSTB#0 <7>
H_ADSTB#1 <7>
H_BNR# <7>
H_BPRI# <7>
H_BR0# <7>
H_DEFER# <7>
H_DBSY# <7>
CLK_MCH_BCLK <6>
CLK_MCH_BCLK# <6>
H_DPWR# <8>
H_DRDY# <7>
H_HIT# <7>
H_HITM# <7>
H_LOCK# <7>
H_TRDY# <7>
H_DINV#0 <8>
H_DINV#1 <8>
H_DINV#2 <8>
H_DINV#3 <8>
H_DSTBN#0 <8>
H_DSTBN#1 <8>
H_DSTBN#2 <8>
H_DSTBN#3 <8>
H_DSTBP#0 <8>
H_DSTBP#1 <8>
H_DSTBP#2 <8>
H_DSTBP#3 <8>
H_REQ#0 <7>
H_REQ#1 <7>
H_REQ#2 <7>
H_REQ#3 <7>
H_REQ#4 <7>
H_RS#0 <7>
H_RS#1 <7>
H_RS#2 <7>
SM_PWROK
12
R1059
10K_0402_5%~D
DDPC_CTRLCLK
DDPC_CTRLDATA
SDVO_CTRLCLK
SDVO_CTRLDATA
+1.5V_MEM
+3.3V_RUN
+1.05V_M
R90
R93
3
T6
T12
T15
T19
M_ODT0<16,17>
T21
GFX_VID0<44>
GFX_VID1<44>
GFX_VID2<44>
GFX_VID3<44>
GFX_VID4<44>
M_CLK_DDR0
M_CLK_DDR1
M_CLK_DDR2
M_CLK_DDR3
M_CLK_DDR#0
M_CLK_DDR#1
M_CLK_DDR#2
M_CLK_DDR#3
DDR_CKE0
DDR_CKE1
DDR_CKE2_DIMM
DDR_CKE3_DIMM
DDR_CS#0
DDR_CS#1
DDR_CS2_DIMM#
DDR_CS3_DIMM#
M_ODT0
M_ODT1
M_ODT2_DIMM
M_ODT3_DIMM
SMRCOMP
SMRCOMP#
SMRCOMP_VOH
SMRCOMP_VOL
SM_PWROK
DDR3_DRAMRST#
MCH_DREFCLK
MCH_DREFCLK#
DREF_SSCLK
DREF_SSCLK#
CLK_MCH_3GPLL
CLK_MCH_3GPLL#
DMI_MRX_ITX_N0
DMI_MRX_ITX_N1
DMI_MRX_ITX_N2
DMI_MRX_ITX_N3
DMI_MRX_ITX_P0
DMI_MRX_ITX_P1
DMI_MRX_ITX_P2
DMI_MRX_ITX_P3
DMI_MTX_IRX_N0
DMI_MTX_IRX_N1
DMI_MTX_IRX_N2
DMI_MTX_IRX_N3
DMI_MTX_IRX_P0
DMI_MTX_IRX_P1
DMI_MTX_IRX_P2
DMI_MTX_IRX_P3
GFX_VID0
GFX_VID1
GFX_VID2
GFX_VID3
GFX_VID4
GFX_VR_ON
CL_CLK0
CL_DATA0
ICH_CL_PWROK
CL_RST0#
+CL_VREF
DDPC_CTRLCLK
DDPC_CTRLDATA
SDVO_CTRLCLK
SDVO_CTRLDATA
CLK_3GPLLREQ#
MCH_ICH_SYNC#
MCH_TSATN#
R1032
1 2
33_0402_5%~D
MCH_SDIN2
M_CLK_DDR0<16,17>
M_CLK_DDR2<18>
M_CLK_DDR3<18>
M_CLK_DDR#0<16,17>
M_CLK_DDR#2<18>
M_CLK_DDR#3<18>
DDR_CKE0<16,17>
DDR_CKE2_DIMM<18>
DDR_CKE3_DIMM<18>
DDR_CS#0<16,17>
DDR_CS2_DIMM#<18>
DDR_CS3_DIMM#<18>
80.6_0402_1%~D
80.6_0402_1%~D
0.1U_0402_16V4Z~D
1
C31
2
12
R101
30K_0402_5%~D
GFX_VR_ON
12
R105
100K_0402_5%~D
1K_0402_1%~D
12
499_0402_1%~D
1 2
R82
R83
0.1U_0402_16V4Z~D
1
2
0.1U_0402_16V4Z~D
1
2
ICH_AZ_MCH_BITCLK<23>
ICH_AZ_MCH_RST#<23>
ICH_AZ_MCH_SDIN2<23>
ICH_AZ_MCH_SDOUT<23>
ICH_AZ_MCH_SYNC<23>
M_ODT2_DIMM<18>
M_ODT3_DIMM<18>
12
12
R87 499_0402_1%~D
1 2
DDR3_DRAMRST#<16,17,18>
C32
MCH_DREFCLK<6>
MCH_DREFCLK#<6>
C33
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
DREF_SSCLK<6>
DREF_SSCLK#<6>
CLK_MCH_3GPLL<6>
CLK_MCH_3GPLL#<6>
DMI_MRX_ITX_N0<24>
DMI_MRX_ITX_N1<24>
DMI_MRX_ITX_N2<24>
DMI_MRX_ITX_N3<24>
DMI_MRX_ITX_P0<24>
DMI_MRX_ITX_P1<24>
DMI_MRX_ITX_P2<24>
DMI_MRX_ITX_P3<24>
DMI_MTX_IRX_N0<24>
DMI_MTX_IRX_N1<24>
DMI_MTX_IRX_N2<24>
DMI_MTX_IRX_N3<24>
DMI_MTX_IRX_P0<24>
DMI_MTX_IRX_P1<24>
DMI_MTX_IRX_P2<24>
DMI_MTX_IRX_P3<24>
GFX_VR_ON<44>
CL_CLK0<24>
CL_DATA0<24>
ICH_CL_PWROK<24,34>
CL_RST0#<24>
DDPC_CTRLCLK<31>
DDPC_CTRLDATA<31>
SDVO_CTRLCLK<31>
SDVO_CTRLDATA<31>
CLK_3GPLLREQ#<6>
MCH_ICH_SYNC#<24>
3
U78B
BB32
SA_CK_0
BA25
SA_CK_1
BA33
SB_CK_0
BA23
SB_CK_1
BA31
SA_CK#_0
BC25
SA_CK#_1
BC33
SB_CK#_0
BB24
SB_CK#_1
BC35
SA_CKE_0
BE33
SA_CKE_1
BE37
SB_CKE_0
BC37
SB_CKE_1
BK18
SA_CS#_0
BK16
SA_CS#_1
BE23
SB_CS#_0
BC19
SB_CS#_1
BJ17
SA_ODT_0
BJ19
SA_ODT_1
BC17
SB_ODT_0
BE17
SB_ODT_1
BL25
SM_RCOMP
BK26
SM_RCOMP#
BK32
SM_RCOMP_VOH
BL31
SM_RCOMP_VOL
BC51
SM_VREF
AY37
SM_PWROK
BH20
SM_REXT
BA37
SM_DRAMRST#
B42
DPLL_REF_CLK
D42
DPLL_REF_CLK#
B50
DPLL_REF_SSCLK
D50
DPLL_REF_SSCLK#
R49
PEG_CLK
P50
PEG_CLK#
AG55
DMI_RXN_0
AL49
DMI_RXN_1
AH54
DMI_RXN_2
AL47
DMI_RXN_3
AG53
DMI_RXP_0
AK50
DMI_RXP_1
AH52
DMI_RXP_2
AL45
DMI_RXP_3
AG49
DMI_TXN_0
AJ49
DMI_TXN_1
AJ47
DMI_TXN_2
AG47
DMI_TXN_3
AF50
DMI_TXP_0
AH50
DMI_TXP_1
AJ45
DMI_TXP_2
AG45
DMI_TXP_3
G33
GFX_VID_0
G37
GFX_VID_1
F38
GFX_VID_2
F36
GFX_VID_3
G35
GFX_VID_4
G39
GFX_VR_EN
AK52
CL_CLK
AK54
CL_DATA
AW40
CL_PWROK
AL53
CL_RST#
AL55
CL_VREF
F34
DDPC_CTRLCLK
F32
DDPC_CTRLDATA
B38
SDVO_CTRLCLK
A37
SDVO_CTRLDATA
C31
CLKREQ#
K42
ICH_SYNC#
D10
TSATN#
C29
HDA_BCLK
B30
HDA_RST#
D28
HDA_SDI
A27
HDA_SDO
B28
HDA_SYNC
CANTIGA GMCH SFF_QR46 B0_FCBGA1363~D
2
TP_MCH_RSVD1
J43
RSVD1
RSVD2
RSVD3
RSVD4
RSVD5
RSVD6
RSVD7
RSVD8
RSVD9
RSVD14
RSVD15
RSVD17
RSVD20
RSVD22
RSVD23
RSVD24
RSVD25
ME_JTAG_TCK
ME_JTAG_TDI
ME_JTAG_TDO
ME_JTAG_TMS
L43
J41
L41
AN11
AM10
AK10
AL11
F12
C27
D30
J9
AW42
BB20
BE19
BF20
BF18
AN45
AP44
AT44
AN47
TP_MCH_RSVD2
TP_MCH_RSVD3
TP_MCH_RSVD4
TP_MCH_RSVD5
TP_MCH_RSVD6
TP_MCH_RSVD7
TP_MCH_RSVD8
TP_MCH_RSVD9
TP_MCH_RSVD14
TP_MCH_RSVD15
TP_MCH_RSVD17
TP_MCH_RSVD20
TP_MCH_RSVD22
TP_MCH_RSVD23
TP_MCH_RSVD24
TP_MCH_RSVD25
ME_JTAG_TCK
ME_JTAG_TDI
ME_JTAG_TDO
ME_JTAG_TMS
DDR CLK/ CONTROL/COMPENSATION
CLK
CFGRSVD
DMI
PM_SYNC#
PM_DPRSTP#
PM
PM_EXT_TS#_0
PM_EXT_TS#_1
THERMTRIP#
GRAPHICS VID
DPRSLPVR
ME
NC
MISC
CFG_0
CFG_1
CFG_2
CFG_3
CFG_4
CFG_5
CFG_6
CFG_7
CFG_8
CFG_9
CFG_10
CFG_11
CFG_12
CFG_13
CFG_14
CFG_15
CFG_16
CFG_17
CFG_18
CFG_19
CFG_20
PWROK
RSTIN#
NC_1
NC_2
NC_3
NC_4
NC_5
NC_6
NC_7
NC_8
NC_9
NC_10
NC_11
NC_12
NC_13
NC_14
NC_15
NC_16
NC_17
NC_18
NC_19
NC_20
NC_21
NC_22
K26
G23
G25
J25
L25
L27
F24
D24
D26
J23
B26
A23
C23
B24
B22
K24
C25
L23
L33
K32
K34
J35
F6
J39
L39
AY39
BB18
K28
K36
A7
A49
A52
A54
B54
D55
G55
BE55
BH55
BK55
BK54
BL54
BL52
BL49
BL7
BL4
BL2
BK2
BK1
BH1
BE1
G1
CPU_MCH_BSEL0 <6,8>
CPU_MCH_BSEL1 <6,8>
CPU_MCH_BSEL2 <6,8>
T30
T31
T90
T91
T92
T32
T93
T33
T34
T35
T36
T37
T38
T94
T39
T40
T95
T96
PM_SYNC#
H_DPRSTP#
PM_EXTTS#
RESET_OUT
PLTRST1#_R
THERMTRIP_MCH#
DPRSLPVR
HDA
DELL CONFIDEN TIAL/PROPRIETARY
Title
Size Docum e n t N u m b e r Re v
LA-4291P
2
Date: Sheet
1
T4
T5
T7
T8
T9
T10
T11
T13
T14
T16
T17
T18
T20
T22
T23
T24
T25
R84 100_0402_5%~D@
1 2
R85 100_0402_5%~D@
1 2
R86 100_0402_5%~D@
1 2
R88 100_0402_5%~D@
1 2
+3.3V_RUN
R91
PM_EXTTS#
PLTRST1#_R
THERMTRIP_MCH#
SMRCOMP_VOH
SMRCOMP_VOL
12
10K_0402_5%~D
R114
12
100_0402_5%~D
R116
1 2
56_0402_5%~D
PM_SYNC# <24>
H_DPRSTP# <8,23,43>
PM_EXTTS# <18,19>
RESET_OUT <24,34>
THERMTRIP_MCH# <19>
DPRSLPVR <24,43>
+1.5V_MEM
0.01U_0402_16V7K~D
2.2U_0603_6.3V6K~D
1
1
C36
C37
2
2
0.01U_0402_16V7K~D
2.2U_0603_6.3V6K~D
1
1
C38
C39
2
2
+1.05V_VCCP
R104
R113
Compal Electro nics, Inc.
Cantiga GS(1/6)
1
PLTRST1# <22,35>
12
R98
1K_0402_1%~D
3.01K_0402_1%~D
12
1K_0402_1%~D
12
10 49Friday, December 07, 2007
of
0.1
5
D D
4
3
2
1
DDR_A_BS0<16,17>
DDR_A_BS1<16,17>
DDR_A_BS2<16,17>
DDR_A_RAS#<16,17>
DDR_A_CAS#<16,17>
DDR_A_WE#<16,17>
DDR_A_DM[0..7]<16,17>
DDR_A_DQS[0..7]<16,17>
C C
DDR_A_DQS#[0..7]<16,17>
DDR_A_MA[0..13]<16,17>
B B
DDR_A_BS0
DDR_A_BS1
DDR_A_BS2
DDR_A_RAS#
DDR_A_CAS#
DDR_A_DM0 DDR_A_D11
DDR_A_DM1
DDR_A_DM2
DDR_A_DM3
DDR_A_DM4
DDR_A_DM5
DDR_A_DM6
DDR_A_DM7
DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7
DDR_A_DQS#0
DDR_A_DQS#1
DDR_A_DQS#2
DDR_A_DQS#3
DDR_A_DQS#4
DDR_A_DQS#5
DDR_A_DQS#6
DDR_A_DQS#7
DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA14_R
U78D
BC21
SA_BS_0
BJ21
SA_BS_1
BJ41
SA_BS_2
BH22
SA_RAS#
BK20
SA_CAS#
BL15
SA_WE#
AT50
SA_DM_0
BB50
SA_DM_1
BB46
SA_DM_2
BE39
SA_DM_3
BB12
SA_DM_4
BE7
SA_DM_5
AV10
SA_DM_6
AR9
SA_DM_7
AR47
SA_DQS_0
BA45
SA_DQS_1
BE45
SA_DQS_2
BC41
SA_DQS_3
BC13
SA_DQS_4
BB10
SA_DQS_5
BA7
SA_DQS_6
AN7
SA_DQS_7
AR49
SA_DQS#_0
AW45
SA_DQS#_1
BC45
SA_DQS#_2
BA41
SA_DQS#_3
BA13
SA_DQS#_4
BA11
SA_DQS#_5
BA9
SA_DQS#_6
AN9
SA_DQS#_7
BC23
SA_MA_0
BF22
SA_MA_1
BE31
SA_MA_2
BC31
SA_MA_3
BH26
SA_MA_4
BJ35
SA_MA_5
BB34
SA_MA_6
BH32
SA_MA_7
BB26
SA_MA_8
BF32
SA_MA_9
BA21
SA_MA_10
BG25
SA_MA_11
BH34
SA_MA_12
BH18
SA_MA_13
BE25
SA_MA_14
CANTIGA GMCH SFF_QR46 B0_FCBGA1363~D
DDR SYSTEM MEMORY A
SA_DQ_0
SA_DQ_1
SA_DQ_2
SA_DQ_3
SA_DQ_4
SA_DQ_5
SA_DQ_6
SA_DQ_7
SA_DQ_8
SA_DQ_9
SA_DQ_10
SA_DQ_11
SA_DQ_12
SA_DQ_13
SA_DQ_14
SA_DQ_15
SA_DQ_16
SA_DQ_17
SA_DQ_18
SA_DQ_19
SA_DQ_20
SA_DQ_21
SA_DQ_22
SA_DQ_23
SA_DQ_24
SA_DQ_25
SA_DQ_26
SA_DQ_27
SA_DQ_28
SA_DQ_29
SA_DQ_30
SA_DQ_31
SA_DQ_32
SA_DQ_33
SA_DQ_34
SA_DQ_35
SA_DQ_36
SA_DQ_37
SA_DQ_38
SA_DQ_39
SA_DQ_40
SA_DQ_41
SA_DQ_42
SA_DQ_43
SA_DQ_44
SA_DQ_45
SA_DQ_46
SA_DQ_47
SA_DQ_48
SA_DQ_49
SA_DQ_50
SA_DQ_51
SA_DQ_52
SA_DQ_53
SA_DQ_54
SA_DQ_55
SA_DQ_56
SA_DQ_57
SA_DQ_58
SA_DQ_59
SA_DQ_60
SA_DQ_61
SA_DQ_62
SA_DQ_63
AP46
AU47
AT46
AU49
AR45
AN49
AV50
AP50
AW47
BD50
AW49
BA49
BC49
AV46
BA47
AY50
BF46
BC47
BF50
BF48
BC43
BE49
BA43
BE47
BF42
BC39
BF44
BF40
BB40
BE43
BF38
BE41
BA15
BE11
BE15
BF14
BB14
BC15
BE13
BF16
BF10
BC11
BF8
BG7
BC7
BC9
BD6
BF12
AV6
BB6
AW7
AY6
AT10
AW11
AU11
AW9
AR11
AT6
AP6
AL7
AR7
AT12
AM6
AU7
DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6DDR_A_WE#
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63
DDR_B_BS0<18>
DDR_B_BS1<18>
DDR_B_BS2<18>
DDR_B_RAS#<18>
DDR_B_CAS#<18>
DDR_B_WE#<18>
DDR_B_DM[0..7]<18>
DDR_B_DQS[0..7]<18>
DDR_B_DQS#[0..7]<18>
DDR_B_MA[0..14]<18>
DDR_B_BS0
DDR_B_BS1
DDR_B_BS2
DDR_B_RAS#
DDR_B_CAS#
DDR_B_WE#
DDR_B_DM0
DDR_B_DM1
DDR_B_DM2
DDR_B_DM3
DDR_B_DM4
DDR_B_DM5
DDR_B_DM6
DDR_B_DM7
DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4
DDR_B_DQS5
DDR_B_DQS6
DDR_B_DQS7
DDR_B_DQS#0
DDR_B_DQS#1
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS#4
DDR_B_DQS#5
DDR_B_DQS#6
DDR_B_DQS#7
DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13
DDR_B_MA14
U78E
BJ13
SB_BS_0
BK12
SB_BS_1
BK38
SB_BS_2
BE21
SB_RAS#
BH14
SB_CAS#
BK14
SB_WE#
AP52
SB_DM_0
AY54
SB_DM_1
BJ49
SB_DM_2
BJ43
SB_DM_3
BH12
SB_DM_4
BD2
SB_DM_5
AY2
SB_DM_6
AJ3
SB_DM_7
AR53
SB_DQS_0
BA53
SB_DQS_1
BH50
SB_DQS_2
BK42
SB_DQS_3
BH8
SB_DQS_4
BB2
SB_DQS_5
AV2
SB_DQS_6
AM2
SB_DQS_7
AT54
SB_DQS#_0
BB54
SB_DQS#_1
BJ51
SB_DQS#_2
BH42
SB_DQS#_3
BK8
SB_DQS#_4
BC3
SB_DQS#_5
AW3
SB_DQS#_6
AN3
SB_DQS#_7
BJ15
SB_MA_0
BJ33
SB_MA_1
BH24
SB_MA_2
BA17
SB_MA_3
BF36
SB_MA_4
BH36
SB_MA_5
BF34
SB_MA_6
BK34
SB_MA_7
BJ37
SB_MA_8
BH40
SB_MA_9
BH16
SB_MA_10
BK36
SB_MA_11
BH38
SB_MA_12
BJ11
SB_MA_13
BL37
SB_MA_14
CANTIGA GMCH SFF_QR46 B0_FCBGA1363~D
DDR SYSTEM MEMORY B
SB_DQ_0
SB_DQ_1
SB_DQ_2
SB_DQ_3
SB_DQ_4
SB_DQ_5
SB_DQ_6
SB_DQ_7
SB_DQ_8
SB_DQ_9
SB_DQ_10
SB_DQ_11
SB_DQ_12
SB_DQ_13
SB_DQ_14
SB_DQ_15
SB_DQ_16
SB_DQ_17
SB_DQ_18
SB_DQ_19
SB_DQ_20
SB_DQ_21
SB_DQ_22
SB_DQ_23
SB_DQ_24
SB_DQ_25
SB_DQ_26
SB_DQ_27
SB_DQ_28
SB_DQ_29
SB_DQ_30
SB_DQ_31
SB_DQ_32
SB_DQ_33
SB_DQ_34
SB_DQ_35
SB_DQ_36
SB_DQ_37
SB_DQ_38
SB_DQ_39
SB_DQ_40
SB_DQ_41
SB_DQ_42
SB_DQ_43
SB_DQ_44
SB_DQ_45
SB_DQ_46
SB_DQ_47
SB_DQ_48
SB_DQ_49
SB_DQ_50
SB_DQ_51
SB_DQ_52
SB_DQ_53
SB_DQ_54
SB_DQ_55
SB_DQ_56
SB_DQ_57
SB_DQ_58
SB_DQ_59
SB_DQ_60
SB_DQ_61
SB_DQ_62
SB_DQ_63
AP54
AM52
AR55
AV54
AM54
AN53
AT52
AU53
AW53
AY52
BB52
BC53
AV52
AW55
BD52
BC55
BF54
BE51
BH48
BK48
BE53
BH52
BK46
BJ47
BL45
BJ45
BL41
BH44
BH46
BK44
BK40
BJ39
BK10
BH10
BK6
BH6
BJ9
BL11
BG5
BJ5
BG3
BF4
BD4
BA3
BE5
BF2
BB4
AY4
BA1
AP2
AU1
AT2
AT4
AV4
AU3
AR3
AN1
AP4
AL3
AJ1
AK4
AM4
AH2
AK2
DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63
DDR_B_D[0..63] <18>DDR_A_D[0..63] <16,17>
Place close to U78, reserve for 2Gb on board RAMs
DDR_A_MA14_R DDR_A_MA14
A A
R793
1 2
0_0402_5%~D@
DDR_A_MA14 <16,17>
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
Cantiga GS(2/6)
LA-4291P
11 49Friday, Decemb er 07, 2007
1
0.1
of
5
4
3
+VCC_PEG
2
1
D D
BIA_PWM<20>
PANEL_BKEN_MCH<33>
LDDC_CLK_MCH<20>
LDDC_DATA_MCH<20>
R120
1 2
2.37K_0402_1%~D
LCD_ACLK-_MCH<20>
LCD_ACLK+_MCH<20>
LCD_A0-_MCH<20>
LCD_A1-_MCH<20>
LCD_A2-_MCH<20>
LCD_A0+_MCH<20>
LCD_A1+_MCH<20>
LCD_A2+_MCH<20>
C C
B B
A A
Place close to U78
R140 100K_0402_5%~D
1 2
R135 150_0402_1%~D
1 2
1 2
1 2
R136 150_0402_1%~D
R139 150_0402_1%~D
ENVDD
CRT_BLU
CRT_GRN
CRT_RED
CRT_BLU<20>
CRT_GRN<20>
CRT_RED<20>
CRT_HSYNC<20>
1.02K_0402_1%~D
CRT_VSYNC<20>
ENVDD<20>
R126
1 2
30_0402_1%~D
R128
12
1 2
R130
30_0402_1%~D
BIA_PWM
PANEL_BKEN_MCH
LDDC_CLK_MCH
LDDC_DATA_MCH
ENVDD
L_IBG
LCD_ACLK-_MCH
LCD_ACLK+_MCH
LCD_A0-_MCH
LCD_A1-_MCH
LCD_A2-_MCH
LCD_A0+_MCH
LCD_A1+_MCH
LCD_A2+_MCH
CRT_BLU
CRT_GRN
CRT_RED
G_CLK_DDC2
G_DAT_DDC2
CRT_HSYNC_R
CRT_IREF
CRT_VSYNC_R
U78C
D38
L_BKLT_CTRL
C37
L_BKLT_EN
K38
L_CTRL_CLK
L37
L_CTRL_DATA
J37
L_DDC_CLK
L35
L_DDC_DATA
B36
L_VDD_EN
F50
LVDS_IBG
H46
LVDS_VBG
P44
LVDS_VREFH
K46
LVDS_VREFL
D46
LVDSA_CLK#
B46
LVDSA_CLK
D44
LVDSB_CLK#
B44
LVDSB_CLK
G45
LVDSA_DATA#_0
F46
LVDSA_DATA#_1
G41
LVDSA_DATA#_2
C45
LVDSA_DATA#_3
F44
LVDSA_DATA_0
G47
LVDSA_DATA_1
F40
LVDSA_DATA_2
A45
LVDSA_DATA_3
B40
LVDSB_DATA#_0
A41
LVDSB_DATA#_1
F42
LVDSB_DATA#_2
D48
LVDSB_DATA#_3
D40
LVDSB_DATA_0
C41
LVDSB_DATA_1
G43
LVDSB_DATA_2
B48
LVDSB_DATA_3
J27
TVA_DAC
E27
TVB_DAC
G27
TVC_DAC
F26
TVA_RTN
B34
TV_DCONSEL_0
D34
TV_DCONSEL_1
J29
CRT_BLUE
G29
CRT_GREEN
F30
CRT_RED
E29
CRT_IRTN
D36
CRT_DDC_CLK
C35
CRT_DDC_DATA
J33
CRT_HSYNC
D32
CRT_TVO_IREF
G31
CRT_VSYNC
CANTIGA GMCH SFF_QR46 B0_FCBGA1363~D
LVDS
TV
PEG_COMPI
PEG_COMPO
PEG_RX#_0
PEG_RX#_1
PEG_RX#_2
PEG_RX#_3
PEG_RX#_4
PEG_RX#_5
PEG_RX#_6
PEG_RX#_7
PEG_RX#_8
PEG_RX#_9
PEG_RX#_10
PEG_RX#_11
PEG_RX#_12
PEG_RX#_13
PEG_RX#_14
PEG_RX#_15
PEG_RX_0
PEG_RX_1
PEG_RX_2
PEG_RX_3
PEG_RX_4
PEG_RX_5
PEG_RX_6
PEG_RX_7
PEG_RX_8
PEG_RX_9
PEG_RX_10
PEG_RX_11
PEG_RX_12
PEG_RX_13
PEG_RX_14
PEG_RX_15
PEG_TX#_0
PEG_TX#_1
PEG_TX#_2
PEG_TX#_3
PEG_TX#_4
PEG_TX#_5
PEG_TX#_6
PEG_TX#_7
PEG_TX#_8
PEG_TX#_9
PEG_TX#_10
PEG_TX#_11
PCI-EXPRESS GRAPHICS
PEG_TX#_12
PEG_TX#_13
PEG_TX#_14
PEG_TX#_15
PEG_TX_0
PEG_TX_1
PEG_TX_2
VGA
PEG_TX_3
PEG_TX_4
PEG_TX_5
PEG_TX_6
PEG_TX_7
PEG_TX_8
PEG_TX_9
PEG_TX_10
PEG_TX_11
PEG_TX_12
PEG_TX_13
PEG_TX_14
PEG_TX_15
U45
T44
D52
G49
K54
H50
M52
N49
P54
V46
Y50
V52
W49
AB54
AD46
AC55
AE49
AF54
E51
F48
J55
J49
M54
M50
P52
U47
AA49
V54
V50
AB52
AC47
AC53
AD50
AF52
L47
F52
P46
H54
L55
T46
R53
U49
T54
Y46
AB46
W53
Y54
AC49
AF46
AD54
J47
F54
N47
H52
L53
R47
R55
T50
T52
W47
AA47
W55
Y52
AB50
AE47
AD52
PEGCOMP
R119
49.9_0402_1%~D
1 2
DPB_DOCK_AUX#
DPC_DOCK_AUX#
DPB_DOCK_AUX
DPB_DOCK_HPD#
DPC_DOCK_AUX
DPC_DOCK_HPD#
DPB_LANE_N0
DPB_LANE_N1
DPB_LANE_N2
DPB_LANE_N3
DPC_LANE_N0
DPC_LANE_N1
DPC_LANE_N2
DPC_LANE_N3
DPB_LANE_P0
DPB_LANE_P1
DPB_LANE_P2
DPB_LANE_P3
DPC_LANE_P0
DPC_LANE_P1
DPC_LANE_P2
DPC_LANE_P3
G_DAT_DDC2 DAT_DDC2
DPB_DOCK_AUX# <31>
DPC_DOCK_AUX# <31>
DPB_DOCK_AUX <31>
DPB_DOCK_HPD# <31>
DPC_DOCK_AUX <31>
DPC_DOCK_HPD# <31>
C40 0.1U_0402_10V7K~D
12
C41 0.1U_0402_10V7K~D
12
C42 0.1U_0402_10V7K~D
12
C43 0.1U_0402_10V7K~D
12
C44 0.1U_0402_10V7K~D
12
C45 0.1U_0402_10V7K~D
12
C46 0.1U_0402_10V7K~D
12
C47 0.1U_0402_10V7K~D
12
C48 0.1U_0402_10V7K~D
12
C49 0.1U_0402_10V7K~D
12
C50 0.1U_0402_10V7K~D
12
C51 0.1U_0402_10V7K~D
12
C52 0.1U_0402_10V7K~D
12
C53 0.1U_0402_10V7K~D
12
C54 0.1U_0402_10V7K~D
12
C55 0.1U_0402_10V7K~D
12
+3.3V_RUN
12
12
R1061
2.2K_0402_5%~D
R1062
2.2K_0402_5%~D
+3.3V_RUN
DPB_LANE_N0_C <31>
DPB_LANE_N1_C <31>
DPB_LANE_N2_C <31>
DPB_LANE_N3_C <31>
DPC_LANE_N0_C <31>
DPC_LANE_N1_C <31>
DPC_LANE_N2_C <31>
DPC_LANE_N3_C <31>
DPB_LANE_P0_C <31>
DPB_LANE_P1_C <31>
DPB_LANE_P2_C <31>
DPB_LANE_P3_C <31>
DPC_LANE_P0_C <31>
DPC_LANE_P1_C <31>
DPC_LANE_P2_C <31>
DPC_LANE_P3_C <31>
Q110A
2N7002DW-7-F_SOT363-6~D
2
Q110B
5
2N7002DW-7-F_SOT363-6~D
4
CLK_DDC2G_CLK_DDC2
61
3
CFG5 DMI X2 Select
iTPM Host
CFG6
Interface
Management
CFG7
Engine Crypto
Strap
PCI Express
CFG9
Graphic Lane
PCI Express
Lookpback
CFG10
enable
CFG12
ALLZ
CFG13
XOR
CFG16
FSB Dynamic
ODT
DMI Lane
CFG19
Reversal
SDVO/PCIE
CFG20
Concurrent
Operation
SDVO_CRTL_DATA
DDPC_CTRLDATA
CFG[5:16] have internal pullup
CLK_DDC2 <20>
DAT_DDC2 <20>
Strap Pin Table
Low = DMI x 2
High = DMI x 4 (Default)
Low = iTPM enable
High = iTPM disable(Defult)
Low = TLS cipher s u i t e wit h n o c onfidentiality
High = TLS cip h e r s u i t e with
confidentiality(Default)
Low = Reverse Lane
High = Normal O p e r a t i o n(Default)
Low = Enable
High = Disable ( d e f ault)
Low = ALLZ mode enable
High = Disable ( d e f ault)
Low = XOR mode enable
High = Disable ( d e f ault)
Low=Dynamic O D T Disable
High=Dynamic ODT Enable(default)
Low=Normal (default)
High=Lane Reversed
Low=Only SDVO or PCIEx1 is
operational (default)
High=SDVO and P C I E x 1 a r e o p e rating
simultaneously via PEG port
Low=No SDVO Device Present
(default)
High=SDVO Dev i ce Present
Low=DisplayPort disabled (default)
High=DisplayPort device present
CFG[19:20] have internal pulldown
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
Cantiga GS(3/6)
LA-4291P
12 49Friday, Decemb er 07, 2007
1
0.1
of
5
4
3
2
1
+1.05V_VCCP
220U_D2_4VY_R15M~D
4.7U_0603_6.3V6M~D
1
1
+
C64
C65
2
+1.05V_M
1
2
2
+3.3V_RUN
1
C78
2
R147
0_1210_5%~D
PJP1
1 2
PAD-OPEN1x1m
C109
1
2
1000P_0402_50V7K~D
C114
1
2
C66
0.1U_0402_16V4Z~D
+3.3V_RUN
0.47U_0402_10V4Z~D
22U_0805_6.3V6M~D
+1.5V_RUN_QDAC+1.5V_RUN
1
C85
2
12
CRB 270uF
0.1U_0402_16V4Z~D
1
C84
2
+1.5V_SM_CK+1.5V_MEM
1_0603_5%~D
12
R150
1
C117
10U_0805_4VAM~D
2
220U_D2_4VY_R15M~D
1
+
C71
2
0.01U_0402_16V7K~D
C116
C73
1
2
1
2
0.1U_0402_16V4Z~D
+VCC_PEG
+VCC_PEG
22U_0805_6.3V6M~D
C72
+1.5V_RUN
4.7U_0603_6.3V6M~D
1
2
118.8mA Max.
C113
D D
L4
1 2
BLM18PG181SN1_0603~D
C C
L12
+1.05V_M
12
0_1210_5%~D
R141
5
1UH_LQM21FN1R0N00D_30%_0805~D
B B
A A
2.2U_0603_6.3V6K~D
1
C68
2
0.1U_0402_16V4Z~D
1
1
C77
2
2
+1.5V_RUN_QDAC
0.1U_0402_16V4Z~D
1
C81
2
10U_0805_6.3VAM~D@
1
1
C93
2
2
+1.5V_SM_CK
+VCC_TX_LVDS
+VCC_PEG
1
C102
0.1U_0402_16V4Z~D
2
GMCH_VTTLF1
GMCH_VTTLF2
GMCH_VTTLF3
0.47U_0402_10V4Z~D
C111
1
2
L10
1 2
0.47U_0402_10V4Z~D
1
2
0.01U_0402_16V7K~D
1
C82
2
+VCC_AXF
1U_0603_10V4Z~D
4.7U_0603_6.3V6M~D
1
C67
2
C76
+1.5V_RUN
12
C92
1
C101
0.1U_0402_16V4Z~D
2
+VCC_DMI
0.47U_0402_10V4Z~D
C110
1
2
100NH_HK1608R10J-T_5%_0603~D
U78H
R13
VTT_1
T12
VTT_2
R11
VTT_3
T10
VTT_4
R9
VTT_5
T8
VTT_6
R7
VTT_7
T6
VTT_8
R5
VTT_9
T4
VTT_10
R3
VTT_11
T2
VTT_12
R1
VTT_13
VTT
K30
VCCA_TV_DAC
A31
VCC_HDA
N34
VCCD_QDAC
N32
VCCD_TVDAC
0.01U_0402_16V7K~D
POWER
M25
VCC_AXF_1
N24
VCC_AXF_2
M23
VCC_AXF_3
BK24
VCC_SM_CK_1
BL23
VCC_SM_CK_2
BJ23
VCC_SM_CK_3
BK22
VCC_SM_CK_4
T41
VCC_TX_LVDS
C33
VCC_HV_1
A33
VCC_HV_2
AB44
VCC_PEG_1
Y44
VCC_PEG_2
AC43
VCC_PEG_3
AA43
VCC_PEG_4
AM44
VCC_DMI_1
AN43
VCC_DMI_2
AL43
VCC_DMI_3
K14
VTTLF1
Y12
VTTLF2
P2
VTTLF3
CANTIGA GMCH SFF_QR46 B0_FCBGA1363~D
+1.8V_LVDS
4
AXF
HV
PEG
VTTLF
PJP38
1 2
PAD-OPEN 4x4m
PJP39
1 2
PAD-OPEN 4x4m
TVD TV/CRT
HDA
SM CK
DMI
VCCA_CRT_DAC
CRTPLLA PEGA SM
A LVDS
VCCA_PEG_PLL
VCCA_SM_NCTF_1
VCCA_SM_NCTF_2
VCCA_SM_NCTF_3
VCCA_SM_NCTF_4
VCCA_SM_NCTF_5
VCCA_SM_NCTF_6
VCCA_SM_NCTF_7
VCCA_SM_NCTF_8
VCCA_SM_NCTF_9
VCCA_SM_NCTF_10
VCCA_SM_CK_4
VCCA_SM_CK_3
VCCA_SM_CK_2
VCCA_SM_CK_1
VCCA_SM_CK_NCTF_1
VCCA_SM_CK_NCTF_2
VCCA_SM_CK_NCTF_3
VCCA_SM_CK_NCTF_4
VCCA_SM_CK_NCTF_5
VCCA_SM_CK_NCTF_6
VCCA_SM_CK_NCTF_7
VCCA_SM_CK_NCTF_8
VCCD_PEG_PLL
LVDS
+1.8V_RUN+VCC_TX_LVDS
+1.8V_RUN_LVDS
VCCA_DAC_BG
VSSA_DAC_BG
VCCA_DPLLA
VCCA_DPLLB
VCCA_HPLL
VCCA_MPLL
VCCA_LVDS1
VCCA_LVDS2
VSSA_LVDS
VCCA_PEG_BG
VCCA_SM_1
VCCA_SM_2
VCCA_SM_3
VCCA_SM_4
VCCA_SM_5
VCCA_SM_6
VCCA_SM_7
VCCA_SM_8
VCCA_SM_9
VCCA_SM_10
VCCA_SM_11
VCCA_SM_12
VCCA_SM_13
VCCA_SM_14
VCCA_SM_15
VCCA_SM_16
VCCA_SM_17
VCCD_HPLL
VCCD_LVDS_1
VCCD_LVDS_2
+3.3V_CRT_DAC
J31
L31
M33
J45
+1.05V_M_DPLLA
L49
+1.05V_M_DPLLB
AF10
+1.05V_M_HPLL
AE1
+1.05V_M_MPLL
+VCC_TX_LVDS
U43
U41
V44
VCCA_PEG_BG
AJ43
AG43
+1.05V_M_PEGPLL
AW24
AU24
AW22
AU22
AU21
AW20
AU19
AW18
AU18
AW16
AU16
AT16
AR16
AU15
AT15
AR15
AW14
AT24
AR24
AT22
AR22
AT21
AR21
AT19
AR19
AT18
AR18
AU27
AU28
AU29
AU31
AT31
AR31
AT29
AR29
AT28
AR28
AT27
AR27
AH12
AE43
M46
L45
C112
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
1U_0603_10V4Z~D
1
2
3
C88
C97
+1.8V_LVDS
1
C74
2
1
2
+1.05V_M_A_SM
1U_0603_10V4Z~D
1
1
C89
2
2
+1.05V_M_SM_CK
0.1U_0402_16V4Z~D
1
1
C99
2
2
+1.05V_M_PEGPLL
0.1U_0402_16V4Z~D
C108
1
2
+3.3V_CRT_DAC
0.01U_0402_16V7K~D
0.1U_0402_16V4Z~D
1
C75
2
R143
1 2
0_0402_5%~D
C80
0.1U_0402_16V4Z~D
4.7U_0603_6.3V6M~D
22U_0805_6.3V6M~D
1
C90
C91
2
22U_0805_6.3V6M~D
2.2U_0603_6.3V6K~D@
1
C98
2
C69
22U_0805_6.3V6M~D@
1
2
R149
1 2
0_1210_5%~D
4.7UH_LQM18FN4R7M00D_20%_0603~D
0.1U_0402_16V4Z~D
0.01U_0402_16V7K~D
1
1
C70
2
2
+VCC_TX_LVDS
1
C79
+1.05V_M
0.1U_0402_16V4Z~D
2
+1.05V_M
1
+
C87
2
+1.05V_M_PEGPLL
C86
+1.5V_RUN
R146
1 2
0_0805_5%~D
+1.05V_M
C107
1
2
1000P_0402_50V7K~D
100U_D_6.3VM_R15M~D
1
2
L3
12
BLM21PG221SN1D_0805~D
0.1U_0402_16V4Z~D
12
R145
1_0402_5%~D
1
C83
10U_0805_4VAM~D
2
2
+3.3V_RUN
L5
64.8mA Max.
+1.05V_M_DPLLA
C105
1
2
64.8mA Max.
+1.05V_M_DPLLB
C106
1
2
24mA Max.
+1.05V_M_HPLL
1
C94
2
10UH_LB2012T100MR_20%_0805~D
0.1U_0402_16V4Z~D
220U_D2_4VY_R15M~D
1
C103
+
2
10UH_LB2012T100MR_20%_0805~D
220U_D2_4VY_R15M~D
0.1U_0402_16V4Z~D
1
C104
+
2
BLM18AG121SN1D_0603~D
4.7U_0603_6.3V6M~D
0.1U_0402_16V4Z~D
1
C95
2
L8
12
L9
12
+1.05V_M
L6
12
139.2mA Max.
12
+1.05V_M
+1.05V_M_MPLL
0.1U_0402_16V4Z~D
1
C96
2
0.15UH_LQH32CNR15M33L_20%_1210~D
R148
0_0603_5%~D
1 2
1
C100
22U_0805_6.3VAM~D
2
L7
12
DELL CONFIDENTIAL/PROPRIETARY
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
Cantiga GS(4/6)
LA-4291P
1
+1.05V_M
+1.05V_M
+1.05V_M
13 49Friday, Decemb er 07, 2007
0.1
of
5
U78F
D D
Layout Note:
Place close to U78
1
C124
+
2
CRB 270uF
C C
B B
A A
220U_D2_4VY_R15M~D
Layout Note:
Inside GMCH cavity
C125
1
2
C133
1
2
22U_0805_6.3V6M~D
C126
0.22U_0402_10V4Z~D
C134
1 2
0_0402_5%~D
1
2
1
2
R763
0.22U_0402_10V4Z~D
0.1U_0402_10V7K~D
+1.05V_M
AT41
VCC_1
AR41
VCC_2
AN41
VCC_3
AJ41
VCC_4
AH41
VCC_5
AD41
VCC_6
AC41
VCC_7
Y41
VCC_8
W41
VCC_9
AT40
VCC_10
AM40
VCC_11
AL40
VCC_12
AJ40
VCC_13
AH40
VCC_14
AG40
VCC_15
AE40
VCC_16
AD40
VCC_17
AC40
VCC_18
AA40
VCC_19
Y40
VCC_20
AN35
VCC_21
AM35
VCC_22
AJ35
VCC_23
AH35
VCC_24
AD35
VCC_25
AC35
VCC_26
W35
VCC_27
AM34
VCC_28
AL34
VCC_29
AJ34
VCC_30
AH34
VCC_31
AG34
VCC_32
AE34
VCC_33
AD34
VCC_34
AC34
VCC_35
AA34
VCC_36
Y34
VCC_37
W34
VCC_38
AM32
VCC_39
AL32
VCC_40
AJ32
VCC_41
AH32
VCC_42
AE32
VCC_43
AD32
VCC_44
AA32
VCC_45
AM31
VCC_46
AL31
VCC_47
AJ31
VCC_48
AH31
VCC_49
AM29
VCC_50
AL29
VCC_51
AM28
VCC_52
AL28
VCC_53
AJ28
VCC_54
AM27
VCC_55
AL27
VCC_56
AM25
VCC_57
AL25
VCC_58
AJ25
VCC_59
AM24
VCC_60
N36
VCC_61
CANTIGA GMCH SFF_QR46 B0_FCBGA1363~D
4
VCC CORE
POWER
VCC NCTF
VCC_NCTF_1
VCC_NCTF_2
VCC_NCTF_3
VCC_NCTF_4
VCC_NCTF_5
VCC_NCTF_6
VCC_NCTF_7
VCC_NCTF_8
VCC_NCTF_9
VCC_NCTF_10
VCC_NCTF_11
VCC_NCTF_12
VCC_NCTF_13
VCC_NCTF_14
VCC_NCTF_15
VCC_NCTF_16
VCC_NCTF_17
VCC_NCTF_18
VCC_NCTF_19
VCC_NCTF_20
VCC_NCTF_21
VCC_NCTF_22
VCC_NCTF_23
VCC_NCTF_24
VCC_NCTF_25
VCC_NCTF_26
VCC_NCTF_27
VCC_NCTF_28
VCC_NCTF_29
VCC_NCTF_30
VCC_NCTF_31
VCC_NCTF_32
VCC_NCTF_33
VCC_NCTF_34
VCC_NCTF_35
VCC_NCTF_36
VCC_NCTF_37
VCC_NCTF_38
+1.5V_MEM
330U_D2_2.5VY_R15M
0.1U_0402_10V7K~D
1
C118
C121
2
+
2
1
Place close to GMCH Place on the edge
+1.05V_M
AT38
AR38
AN38
AM38
AL38
AG38
AE38
AA38
Y38
W38
U38
T38
R38
AT37
AR37
AN37
AM37
AL37
AJ37
AH37
AG37
AE37
AD37
AC37
AA37
Y37
W37
U37
T37
R37
AT35
AR35
U35
AT34
AR34
U34
T34
R34
C122
3
U78G
+VCC_SM_BB36
+VCC_SM_BE35
0.1U_0402_10V7K~D
2
1
22U_0805_6.3V6M~D
2
1
C756
C757
0.1U_0402_10V7K~D
C760
0.1U_0402_10V7K~D
2
1
+VCC_SM_BC29
0.1U_0402_10V7K~D
2
1
+VCC_SM_BF24
+VCC_SM_BL19
+VCC_SM_BB16
0.1U_0402_10V7K~D
2
1
VCC_AXG_SENSE
VSS_AXG_SENSE
+VCC_GFXCORE
C755
22U_0805_6.3V6M~D
C123
1
1
2
2
0.1U_0402_10V7K~D
C759
C758
2
1
VCC_AXG_SENSE<44>
VSS_AXG_SENSE<44>
BB36
BE35
AW34
AW32
BK30
BH30
BF30
BD30
BB30
AW30
BL29
BJ29
BG29
BE29
BC29
BA29
AY29
BK28
BH28
BF28
BD28
BB28
BL27
BJ27
BG27
BE27
BC27
BA27
AY27
AW26
BF24
BL19
BB16
W32
AG31
AE31
AD31
AC31
AA31
W31
AH29
AG29
AE29
AD29
AC29
AA29
W29
AH28
AG28
AE28
AA28
AH27
AG27
AE27
AD27
AC27
AA27
W27
AH25
AD25
AC25
W25
AJ24
AH24
AG24
AE24
AD24
AC24
AA24
W24
AM22
AL22
AJ22
AH22
AG22
AE22
AD22
AC22
AA22
AM21
AL21
AJ21
AH21
AD21
AC21
AA21
W21
AM16
AL16
AG13
AE13
Y31
Y29
Y27
Y24
Y21
VCC_SM_1
VCC_SM_2
VCC_SM_3
VCC_SM_4
VCC_SM_5
VCC_SM_6
VCC_SM_7
VCC_SM_8
VCC_SM_9
VCC_SM_10
VCC_SM_11
VCC_SM_12
VCC_SM_13
VCC_SM_14
VCC_SM_15
VCC_SM_16
VCC_SM_17
VCC_SM_18
VCC_SM_19
VCC_SM_20
VCC_SM_21
VCC_SM_22
VCC_SM_23
VCC_SM_24
VCC_SM_25
VCC_SM_26
VCC_SM_27
VCC_SM_28
VCC_SM_29
VCC_SM_30
VCC_SM_31
VCC_SM_32
VCC_SM_33
VCC_AXG_1
VCC_AXG_2
VCC_AXG_3
VCC_AXG_4
VCC_AXG_5
VCC_AXG_6
VCC_AXG_7
VCC_AXG_8
VCC_AXG_9
VCC_AXG_10
VCC_AXG_11
VCC_AXG_12
VCC_AXG_13
VCC_AXG_14
VCC_AXG_15
VCC_AXG_16
VCC_AXG_17
VCC_AXG_18
VCC_AXG_19
VCC_AXG_20
VCC_AXG_21
VCC_AXG_22
VCC_AXG_23
VCC_AXG_24
VCC_AXG_25
VCC_AXG_26
VCC_AXG_27
VCC_AXG_28
VCC_AXG_29
VCC_AXG_30
VCC_AXG_31
VCC_AXG_32
VCC_AXG_33
VCC_AXG_34
VCC_AXG_35
VCC_AXG_36
VCC_AXG_37
VCC_AXG_38
VCC_AXG_39
VCC_AXG_40
VCC_AXG_41
VCC_AXG_42
VCC_AXG_43
VCC_AXG_44
VCC_AXG_45
VCC_AXG_46
VCC_AXG_47
VCC_AXG_48
VCC_AXG_49
VCC_AXG_50
VCC_AXG_51
VCC_AXG_52
VCC_AXG_53
VCC_AXG_54
VCC_AXG_55
VCC_AXG_56
VCC_AXG_57
VCC_AXG_58
VCC_AXG_59
VCC_AXG_60
VCC_AXG_61
VCC_AXG_SENSE
VSS_AXG_SENSE
2
POWER
VCC SMVCC GFX
VCC GFX NCTF
VCC GFX
VCC_AXG_NCTF_1
VCC_AXG_NCTF_2
VCC_AXG_NCTF_3
VCC_AXG_NCTF_4
VCC_AXG_NCTF_5
VCC_AXG_NCTF_6
VCC_AXG_NCTF_7
VCC_AXG_NCTF_8
VCC_AXG_NCTF_9
VCC_AXG_NCTF_10
VCC_AXG_NCTF_11
VCC_AXG_NCTF_12
VCC_AXG_NCTF_13
VCC_AXG_NCTF_14
VCC_AXG_NCTF_15
VCC_AXG_NCTF_16
VCC_AXG_NCTF_17
VCC_AXG_NCTF_18
VCC_AXG_NCTF_19
VCC_AXG_NCTF_20
VCC_AXG_NCTF_21
VCC_AXG_NCTF_22
VCC_AXG_NCTF_23
VCC_AXG_NCTF_24
VCC_AXG_NCTF_25
VCC_AXG_NCTF_26
VCC_AXG_NCTF_27
VCC_AXG_NCTF_28
VCC_AXG_NCTF_29
VCC_AXG_NCTF_30
VCC_AXG_NCTF_31
VCC_AXG_NCTF_32
VCC_AXG_NCTF_33
VCC_AXG_NCTF_34
VCC_AXG_NCTF_35
VCC_AXG_NCTF_36
VCC_AXG_NCTF_37
VCC_AXG_NCTF_38
VCC_AXG_NCTF_39
VCC_AXG_NCTF_40
VCC_AXG_NCTF_41
VCC_AXG_NCTF_42
VCC_AXG_NCTF_43
VCC_AXG_NCTF_44
VCC_AXG_62
VCC_AXG_63
VCC_AXG_64
VCC_AXG_65
VCC_AXG_66
VCC_AXG_67
VCC_AXG_68
VCC_AXG_69
VCC_AXG_70
VCC_AXG_71
VCC_AXG_72
VCC_AXG_73
VCC_AXG_74
VCC_AXG_75
VCC_AXG_76
VCC_AXG_77
VCC_AXG_78
VCC_AXG_79
VCC_AXG_80
VCC_SM_LF1
VCC_SM_LF2
VCC_SM_LF3
VCC_SM_LF4
VCC_SM_LF5
VCC_SM_LF6
VCC_SM_LF7
VCC SM LF
+VCC_GFXCORE
T32
U31
T31
R31
U29
T29
R29
U28
U27
T27
R27
U25
T25
R25
U24
U22
T22
R22
U21
T21
R21
AM19
AL19
AH19
AG19
AE19
AD19
AC19
W19
U19
AM18
AL18
AJ18
AH18
AG18
AE18
AD18
AC18
AA18
Y18
W18
U18
T18
R18
AJ16
AH16
AD16
AC16
AA16
U16
T16
R16
AM15
AL15
AJ15
AH15
AG15
AE15
AA15
Y15
W15
U15
T15
VCCSM_LF1
AU45
VCCSM_LF2
BF52
VCCSM_LF3
BB38
VCCSM_LF4
BA19
VCCSM_LF5
BE9
VCCSM_LF6
AU9
VCCSM_LF7
AL9
Cavity Ca pacitors
0.1U_0402_10V7K~D
C129
C130
1
1
2
2
0.1U_0402_10V7K~D
C135
0.1U_0402_10V7K~D
C136
1
1
2
2
0.1U_0402_10V7K~D
C137
C127
1
1U_0603_10V4Z~D
0.47U_0402_10V4Z~D
C128
C131
1
1
2
2
0.22U_0402_10V4Z~D
0.22U_0402_10V4Z~D
C139
C138
1
1
2
2
22U_0805_6.3V6M~D
10U_0805_6.3VAM~D
C132
1
1
2
2
0.47U_0402_10V4Z~D
C140
1
2
1U_0402_6.3V4Z~D
1U_0402_6.3V4Z~D
C141
1
1
2
2
CANTIGA GMCH SFF_QR46 B0_FCBGA1363~D
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
DELL CONFIDENTIAL/PROPRIETARY
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
Cantiga GS(5/6)
LA-4291P
14 49Friday, Decemb er 07, 2007
1
of
0.1
5
4
3
2
1
U78I
BA55
VSS_1
AU55
VSS_2
AN55
VSS_3
AJ55
VSS_4
AE55
VSS_5
AA55
VSS_6
U55
VSS_7
N55
VSS_8
BD54
VSS_9
BG53
D D
C C
B B
A A
VSS_10
AJ53
VSS_11
AE53
VSS_12
AA53
VSS_13
U53
VSS_14
N53
VSS_15
J53
VSS_16
G53
VSS_17
E53
VSS_18
K52
VSS_19
BG51
VSS_20
BA51
VSS_21
AW51
VSS_22
AU51
VSS_23
AR51
VSS_24
AN51
VSS_25
AL51
VSS_26
AJ51
VSS_27
AG51
VSS_28
AE51
VSS_29
AC51
VSS_30
AA51
VSS_31
W51
VSS_32
U51
VSS_33
R51
VSS_34
N51
VSS_35
L51
VSS_36
J51
VSS_37
G51
VSS_38
C51
VSS_39
BK50
VSS_40
AM50
VSS_41
K50
VSS_42
BG49
VSS_43
E49
VSS_44
C49
VSS_45
BD48
VSS_46
BB48
VSS_47
AY48
VSS_48
AV48
VSS_49
AT48
VSS_50
AP48
VSS_51
AM48
VSS_52
AK48
VSS_53
AH48
VSS_54
AF48
VSS_55
AD48
VSS_56
AB48
VSS_57
Y48
VSS_58
V48
VSS_59
T48
VSS_60
P48
VSS_61
M48
VSS_62
K48
VSS_63
H48
VSS_64
BL47
VSS_65
BG47
VSS_66
E47
VSS_67
C47
VSS_68
A47
VSS_69
BD46
VSS_70
AY46
VSS_71
AM46
VSS_72
AK46
VSS_73
AH46
VSS_74
BG45
VSS_75
AE45
VSS_76
AC45
VSS_77
AA45
VSS_78
W45
VSS_79
R45
VSS_80
N45
VSS_81
E45
VSS_82
BD44
VSS_83
BB44
VSS_84
AV44
VSS_85
AK44
VSS_86
AH44
VSS_87
AF44
VSS_88
AD44
VSS_89
K44
VSS_90
H44
VSS_91
BL43
VSS_92
BG43
VSS_93
AY43
VSS_94
AR43
VSS_95
W43
VSS_96
R43
VSS_97
M43
VSS_98
E43
VSS_99
CANTIGA GMCH SFF_QR46 B0_FCBGA1363~D
VSS
VSS_100
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105
VSS_106
VSS_107
VSS_108
VSS_109
VSS_110
VSS_111
VSS_112
VSS_113
VSS_114
VSS_115
VSS_116
VSS_117
VSS_118
VSS_119
VSS_120
VSS_121
VSS_122
VSS_123
VSS_124
VSS_125
VSS_126
VSS_127
VSS_128
VSS_129
VSS_130
VSS_131
VSS_132
VSS_133
VSS_134
VSS_135
VSS_136
VSS_137
VSS_138
VSS_139
VSS_140
VSS_141
VSS_142
VSS_143
VSS_144
VSS_145
VSS_146
VSS_147
VSS_148
VSS_149
VSS_150
VSS_151
VSS_152
VSS_153
VSS_154
VSS_155
VSS_156
VSS_157
VSS_158
VSS_159
VSS_160
VSS_161
VSS_162
VSS_163
VSS_164
VSS_165
VSS_166
VSS_167
VSS_168
VSS_169
VSS_170
VSS_171
VSS_172
VSS_173
VSS_174
VSS_175
VSS_176
VSS_177
VSS_178
VSS_179
VSS_180
VSS_181
VSS_182
VSS_183
VSS_184
VSS_185
VSS_186
VSS_187
VSS_188
VSS_189
VSS_190
VSS_191
VSS_192
VSS_193
VSS_194
VSS_195
VSS_196
VSS_197
VSS_198
C43
A43
BD42
H42
BG41
AY41
AU41
AM41
AL41
AG41
AE41
AA41
R41
M41
E41
BD40
AU40
AR40
AN40
W40
U40
T40
R40
K40
H40
BL39
BG39
BA39
E39
C39
A39
BD38
AU38
H38
BG37
AU37
M37
E37
BD36
AW36
H36
BL35
BG35
AY35
AU35
AL35
AG35
AE35
AA35
Y35
M35
E35
A35
BD34
AU34
AN34
H34
BL33
BG33
AY33
E33
BD32
AU32
AN32
AG32
AC32
Y32
H32
B32
BJ31
BG31
AY31
AN31
M31
E31
N30
H30
AN29
AJ29
M29
A29
AW28
AN28
AD28
AC28
Y28
W28
H28
F28
AN27
AJ27
M27
BF26
BD26
N26
H26
BJ25
AY25
AU25
U78J
AN25
VSS_199
AG25
VSS_200
AE25
VSS_201
AA25
VSS_202
Y25
VSS_203
E25
VSS_204
A25
VSS_205
BD24
VSS_206
AN24
VSS_207
AL24
VSS_208
H24
VSS_209
BG23
VSS_210
AY23
VSS_211
E23
VSS_212
BD22
VSS_213
BB22
VSS_214
AN22
VSS_215
Y22
VSS_216
W22
VSS_217
H22
VSS_218
BL21
VSS_219
BG21
VSS_220
AY21
VSS_221
AN21
VSS_222
AG21
VSS_223
AE21
VSS_224
M21
VSS_225
E21
VSS_226
A21
VSS_227
BD20
VSS_228
H20
VSS_229
BG19
AY19
M19
BD18
N18
H18
BL17
BG17
AY17
M17
BD16
AN16
AG16
AE16
W16
N16
H16
BG15
AY15
AN15
AD15
AC15
R15
M15
BD14
H14
BL13
BG13
AY13
AU13
AR13
AJ13
AC13
AA13
W13
U13
M13
BD12
AV12
AP12
AM12
AK12
AB12
H12
BG11
AG11
BD10
AY10
AP10
H10
BG9
BD8
BB8
AY8
AV8
AT8
AP8
E19
E17
A17
Y16
E15
E13
A13
V12
P12
E11
BL9
E9
A9
VSS
VSS_230
VSS_231
VSS_232
VSS_233
VSS_234
VSS_235
VSS_236
VSS_237
VSS_238
VSS_239
VSS_240
VSS_241
VSS_242
VSS_243
VSS_244
VSS_245
VSS_246
VSS_247
VSS_248
VSS_249
VSS_250
VSS_251
VSS_252
VSS_253
VSS_254
VSS_255
VSS_256
VSS_257
VSS_258
VSS_259
VSS_260
VSS_261
VSS_262
VSS_263
VSS_264
VSS_265
VSS_266
VSS_267
VSS_268
VSS_269
VSS_270
VSS_271
VSS_272
VSS_273
VSS_274
VSS_275
VSS_276
VSS_277
VSS_278
VSS_279
VSS_280
VSS_281
VSS_282
VSS_283
VSS_284
VSS_285
VSS_286
VSS_287
VSS_288
VSS_289
VSS_290
VSS_291
VSS_292
VSS_293
VSS_294
VSS_295
VSS_296
VSS_297
VSS_298
VSS_299
CANTIGA GMCH SFF_QR46 B0_FCBGA1363~D
VSS_NCTF_10
VSS_NCTF_11
VSS_NCTF_12
VSS_NCTF_13
VSS NCTF
VSS_NCTF_14
VSS_NCTF_15
VSS_NCTF_16
VSS_NCTF_17
VSS_NCTF_18
VSS_NCTF_19
VSS_NCTF_20
VSS_NCTF_21
VSS_NCTF_22
VSS_NCTF_23
VSS SCB
VSS_300
VSS_301
VSS_302
VSS_303
VSS_304
VSS_305
VSS_306
VSS_307
VSS_308
VSS_309
VSS_310
VSS_311
VSS_312
VSS_313
VSS_314
VSS_315
VSS_316
VSS_317
VSS_318
VSS_319
VSS_320
VSS_321
VSS_322
VSS_323
VSS_324
VSS_325
VSS_326
VSS_327
VSS_328
VSS_329
VSS_330
VSS_331
VSS_332
VSS_333
VSS_334
VSS_335
VSS_336
VSS_337
VSS_338
VSS_339
VSS_340
VSS_341
VSS_342
VSS_343
VSS_344
VSS_345
VSS_346
VSS_347
VSS_348
VSS_349
VSS_350
VSS_351
VSS_352
VSS_353
VSS_354
VSS_355
VSS_356
VSS_357
VSS_358
VSS_359
VSS_360
VSS_361
VSS_362
VSS_NCTF_1
VSS_NCTF_2
VSS_NCTF_3
VSS_NCTF_4
VSS_NCTF_5
VSS_NCTF_6
VSS_NCTF_7
VSS_NCTF_8
VSS_NCTF_9
VSS_SCB_1
VSS_SCB_2
VSS_SCB_3
VSS_SCB_4
VSS_SCB_5
VSS_SCB_6
VSS_SCB_7
AM8
AK8
AH8
AF8
AD8
AB8
Y8
V8
P8
M8
K8
H8
BJ7
E7
BF6
BC5
BA5
AW5
AU5
AR5
AN5
AL5
AJ5
AG5
AE5
AC5
AA5
W5
U5
N5
L5
J5
G5
C5
BH4
BE3
U3
E3
BC1
AW1
AR1
AL1
AG1
AC1
W1
N1
J1
AU43
BB42
AW38
BA35
L29
N28
N22
N20
N14
AL13
B10
AN13
N42
N40
N38
M39
AJ38
AH38
AD38
AC38
T35
R35
AT32
AR32
U32
R32
T28
R28
AT25
AR25
T24
R24
AN19
AJ19
AA19
Y19
T19
R19
AN18
BL55
BL1
A55
D1
B55
B2
A4
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
Cantiga GS(6/6)
LA-4291P
15 49Friday, Decemb er 07, 2007
1
0.1
of
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