Page 1
5
COMPAL CONFIDENTIAL
4
3
2
1
MODEL NAME :
PCB NO :
D D
BOM P/N :
LA-4291P
46155331L01
JAZ00
MINICOOPER
C C
Intel Cantiga GS(High Performance) + ICH9M SFF
uFCBGA Mobile Penryn SFF ULV
12-07-2007
REV : 0.1(X00)
B B
@ : Nopop Component
1@ : TAA board Used only
2@ : Without TAA board Used only
A A
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
Cover sheet
LA-4291P
149Friday, Decemb er 07, 2007
1
0.1
of
Page 2
A
Compal confidential
Block Diagram
Model : JAZ00
1 1
DAI
USB8/USB9
SATA5
DOCK LPC BUS
E-Family
DOCKING
page 31
LVDS CONN.
RGB
On Audio/B
CRT CONN.
+5V_RUN
Vedio Switch
TS3DV520ERHUR
+3.3V_RUN
2:1 LVDS MUX
MAXIM MAX4889
+LCDVDD
On IO/B
page 20
1394 CONN.
2 2
SD/MMC CONN.
PCIE3 PCIE2 PCIE1
EXPRESS Card WWAN
+3.3V_SUS
+1.5V_RUN
+3.3V_RUN
3 3
3V/5V
page41
1.5V/1.05V
page42
1.8V/0.75V
page45
CHARGER
page46
DC IN & BATT IN
4 4
page40
WLAN
Mini Card1
+1.5V_RUN +1.5V_RUN
+3.3V_WLAN
USB[4]USB[7]
page30page35
+3.3V_RUN_BKT_PWR
Memory Card &1394
Controller
RICOH R5C833
+3.3V_RUN
Mini Card 2
+3.3V_RUN_WWAN_PWR
2:1 MUX
+3.3V_RUN_BKT_PWR
USB[5]
BKT_USBH
GPIO EXPANSION
SMSC ECE1088
+3.3V_ALW
B
RGB
RGB
page 20
DPB/DPC
LVDS
page 20
BKT_LVDS
PCI BUS
page29
PCI Express BUS
page30
WWAN_USB
SIM/UIM
page21
32M 4K section
page36
Card
W25X32VSSIG
+3.3V_LAN
BC BUS
C
INTEL
Penryn-3MB SFF ULV
+1.5V_RUN
+1.05V_VCCP
+VCC_CORE
H_A#(3..35) H_D#(0..63)
uFCBGA CPU
956pin
System Bus
FSB 800 MHz
INTEL
Cantiga GS-High Performance
+3.3V_RUN
+1.5V_MEM
+1.5V_RUN
+1.05V_M
+1.05V_VCCP
+VCC_GFXCORE
1363pin BGA
DMI*4
GFX Frequency 457/533 MHz
page 10,11,12,13,14,15
+1.5V_RUN/100MHz
INTEL
SPI
ICH9M SFF
569pin BGA
LPC BUS
BKT_USBBIO
+3.3V_RUN_BKT_PWR
page 22,23,24,25
Broadcom USH
BCM5880KFBG
+3.3V_RUN
On BIO/B
+1.5V_RUN
+RTC_CELL
+3.3V_RUN
+1.05V_VCCP
+3.3V_ALW_ICH
page30
page24
SMSC KBC
MEC5035
+RTC_CELL
+3.3V_ALW
page34
BC BUS BC BUS
SMBUS
page 7,8,9
HDA
USB[10]
USBH
2:1 MUX
BIO_USB
BIOMETRIC
page35
+5V_RUN_BKT_PWR
SILEGO SLG8LP554BV
+3.3V_M
800 MHz
Memory BUS DDR3
CHA for memory down
CHB for SO-DIMM
On BT/B
BLUETOOTH
page30
USB 2.0
USB[6] USB[0] USB[3]
HDA
GLCI/LCI
SATA0
1.8" SATA
SSD CONN.
+3.3V_RUN
page32
TERIDIAN
73S8009CN
+3.3V_RUN
page21
Touch Pad
Smart Card
+SC_VCC
page36
page35
page32
page32
D
page 6
On IO/B
USB Port
X1
Intel Boazman
+1V_LAN_M
+1.8V_LAN_M
+3.3V_LAN
LAN Switch
PI3L500-AZFEX
+3.3V_LAN
On IO/B
Transformer
+LOM_VCT
RJ45 CONN.
On BLT/B
CPU ITP PortCK505 Clock GEN
+1.05V_VCCP
page 7
1GB on Board
(128Mx8)*8pcs
DDRIII-DIMM X1
+1.5V_MEM
+V_DDR_MCH_REF
+0.75V_DDR_VTT
On Audio/B
E-SATA
page35
USB Port X1
82567LM
page28
page28
BlackTop CONN.
page 22
+FAN1_VOUT
page 16,17
page 18
SATA4
page35
Azalia Codec
IDT 92HD71B7
+VDDA
+3.3V_RUN
Dock
TI TPA6040A4
+5V_RUN_BKT_PWR
INT. Speaker
2-4W, 4OHM*1
On MIC/B
BKT SW and LED
E
FAN
GUARDIAN III
EMC4002
page 19
BKT_Audio
+3.3V_M
Inverting Buffer & Driver
TI SN74HC368PWR
+3.3V_RUN_BKT_PWR
Headphone AMP.
ADI SSM2602
page26
+3.3V_RUN_BKT_PWR
On MIC/B
Dig. MIC
On Audio/B
MIC
HeadPhone
& MIC Jack
HP
Audio AMP.
page27
page27
page 19
page26
page26
Dock
BKT_SPK
VCORE (IMVP-6)
GFX VCC CORE
page43
page44
KBD Scan extension
INT. KBD
page36
A
B
SMSC ECE1077
+3.3V_ALW
page36
SUPER I/O
SMSC ECE5028
+3.3V_ALW
page33
C
DOCK LPC BUS
Title
Size Document Number Rev
D
Date: Sheet
Compal Electronics, Inc.
Block Diagram
LA-4291P
249Friday, Decemb er 07, 2007
E
0.1
of
DELL CONFIDENTIAL/PROPRIETARY
Page 3
5
4
3
2
1
POWER STATES
State
D D
C C
S0 (Full ON) / M0
S3 (Suspend to RAM) / M1
S4 (Suspend to DISK) / M1 ON ON ON ON
S5 (SOFT OFF) / M1 ON ON ON ON
S3 (Suspend to RAM) / M-OFF
S4 (Suspend to DISK) / M-OFF
S5 (SOFT OFF) / M-OFF
Signal
SLP
SLP
S3#
S4#
HIGH HIGH HIGH
HIGH
HIGH HIGH HIGH ON ON ON ON
LOW
HIGH HIGH HIGH
LOW
HIGH
LOW
HIGH HIGH HIGH
LOW
LOW LOW LOW LOW
LOW LOW LOW LOW LOW
SLP
S5#
LOW
HIGH
S4
STATE#
LOW
LOW
ALWAYS
SLP
PLANE
M#
ON
HIGH
HIGH
HIGH
ON ON
LOW
ON
ON
M
PLANE
ON
OFF
OFF
OFF
SUS
RUN
PLANE
PLANE
ON ON ON
OFF
OFF
OFF
OFF
OFF
OFFOFF
CLOCKS
OFFOFF
OFF
OFF
USB PORT#
0
1
2
3
4
5
6
7
8
9
11
JUSB (Ext Right Side)
NONE
NONE
JESATA (Ext Left Side)
WLAN
WWAN
BT
Express card
DOCKING
DOCKING
USH->BIO10
NONE
DESTINATION
PM TABLE
+15V_ALW
+5V_ALW
power
plane
State
S0
S3
B B
S5 S4/AC
S5 S4/AC don't exist
BLT mode ON OFFOFFOFF ON
+3.3V_ALW
+3.3V_ALW_ICH
+3.3V_RTC_LDO
+1.5V_ALW_HDA
ON
ON
+3.3V_SUS
+1.5V_MEM
+5V_RUN
+3.3V_RUN
+1.8V_RUN
+1.5V_RUN
+0.75V_DDR_VTT
+VCC_GFXCORE
+VCC_CORE
+1.05V_VCCP
ON ON
ON
OFF
OFFOFF
OFFON
OFF
OFF
+3.3V_M +3.3V_M
+1.05V_M +1.05V_M
ON
ON
ON
(M-OFF)
ON
OFF
OFF
OFFOFF
OFF
+3.3V_RUN_BKT_PWR +3.3V_BKT_PWR
+5V_RUN_BKT_PWR
+3.3V_RUN_WWAN_PWR
+INV_PWR_SRC
+LCDVDD
ON
OFF
OFF
OFF
OFF
OFF
OFF
OFF
ON
PCI EXPRESS
Lane 1
Lane 2
Lane 3
Lane 4
Lane 5
Lane 6
DESTINATION
MINI CARD-2 WWAN
MINI CARD-1 WLAN
None
EXPRESS CARD
None
Giga LAN
SAT A DESTINATION
SSDSATA0
PCI TABLE
REQ#/GNT#
PIRQPCI DEVICE IDSEL
SATA1
SATA4
SATA5
A A
R5C833 REQ#1 / GNT#1AD17
PIRQ[C..D]
None
ESATA
DOCKING
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
Index and Config.
LA-4291P
349Friday, Decemb er 07, 2007
1
0.1
of
Page 4
5
4
3
2
1
RUN_ON
ADAPTER
D D
GFX_VR_ON
ALWON
+PWR_SRC
FDS4435
Q33
ADP3209
(PU7)
SN0608098
(PU2)
+INV_PWR_SRC
(12.8V to 20V)
+VGFX_COREP
(1.05V)
+5V_ALW
BAT54SW (PD10/PD11)
+15V_ALW
BATTERY
STS11NF30L
(Q52)
CHARGER
C C
ALWON
+5V_RUN
RUN_ON
SN0608098
SI3456BDV
(Q95)
+5V_RUN_BKT_PWR
RUN_ON
BKT_GPIO4
TPA6040A (U28)
+VDDA
RUN_ON/AUD_AMP_MUTE#
+3.3V_ALW
VT351FCX
+1.5V_MEM
SI4336DY
+1.5V_RUN
1.5V_RUN_ON
(PU4)
EN_1.5VALW
(Q118)
(PU8)TPS51100
+0.75V_DDR_VTT
0.75V_VTT_ON
DDR_ON
VT351FCX
+1.05V_M
SI4336DY
+1.05V_VCCP
1.05V_RUN_ON
(PU3)
EN_1.05VALW
(Q56)
(PU2)
B B
SI345BVD
(Q55)
+3.3V_M
M_ON
SI34536BDV
SI3456BDV
(Q92)
+3.3V_RUN_BKT_PWR
3.3V_RUN_ON
BKT_GPIO3
A A
ADP3207 (PU6)
+3.3V_ALW_ICH
ICH_ALW
+VCC_CORE
STS11NF30L
+3.3V_SUS
SUS_ON
(Q51)
(Q53)
SI4336DY
+3.3V_RUN
3.3V_RUN_ON
SI4336DY (Q89)
+3.3V_RUN_WWAN_PWR
3.3V_RUN_ON
BKT_GPIO15
(Q54)
MAX8794
+1.8V_RUN
1.8V_RUN_ON
(PU9)
SI4336DY
+3.3V_WLAN
AUX_EN_WOWL
(Q48)
MAX8794
+LCDVDD
EN_VDD
BKT_GPIO2
STS11NF30L
AUX_ON
(Q31)
(Q40)
+3.3V_LAN
SI3456BDV
(PU12)
+1.5V_ALW_HDA
ICH_ALW
ADP3419 (PU5)
DELL CONFIDENTIAL/PROPRIETARY
RUNPWROK
5
4
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
Power Rails
LA-4291P
449Friday, Decemb er 07, 2007
1
0.1
of
Page 5
5
C18
ICH_SMBCLK
ICH_SMBDATA
C15
D D
ICH9-M
E18
A24
AMT_SMBCLK
AMT_SMBDAT
2.2K
2.2K
2.2K
2.2K
4
+3.3V_ALW_ICH
2N7002
2N7002
+3.3V_ALW_ICH
3
2.2K
2.2K
MEM_SDATA
+3.3V_ALW_M
202
MEM_SCLK 200
2
1
SMBUS Addr es s [A0]JDIMM
6
5
SMBUS Address [TBD]On board SPD ROM
9493
DOCK_SMB_CLK
6
DOCK_SMB_DAT
5
2.2K
+3.3V_ALW
127
129
SMBUS Address [TBD]DOCKING
2.2K
2.2K
2.2K
PBAT_SMBCLK 7
C C
112
111
PBAT_SMBDAT
2.2K
ALS_SMBCLK
10
ALS_SMBDAT
9
2.2K
2.2K
BKT_SMBCLK
100
99
BKT_SMBDAT
KBC
2.2K
2.2K
LCD_SMBCLK
B B
MEC 5035
8
7
LCD_SMBDATA
9897CARD_SMBCLK
2.2K
CARD_SMBDAT
+3.3V_ALW
100 ohm
100 ohm
+3.3V_ALW
2N7002
2N7002
+3.3V_ALW
+3.3V_ALW
+3.3V_ALW
6
CAPSW_ALS_SMBCLK
CAPSW_ALS_SMBDAT
27
29
24
23
SMBUS Address [TBD]JLVDS
SMBUS Address [16]BATT CONN
2.2K
2.2K
+3.3V_RUN_BKT_PWR
5
2 Ambie n t light sensor
SMBUS Address [TBD]
11
CAP Switch Controller12
SMBUS Address [TBD]
SMBUS Address [TBD]BlackTop CONN
2.2K
+3.3V_SUS
6
7
Express Card S MBUS Address [10H]
+3.3V_WLAN
30
WLAN32
SMBUS Address [TBD]
2N7002
2N7002
2N7002
2N7002
2.2K
EXP_SMBCLK
EXP_SMBDATA
2.2K
2.2K
WLAN_SMBCLK
WLAN_SMBDATA
2.2K
2.2K
2.2K
A A
CKG_SMBCLK
1213CKG_SMBDAT
10
9
CHARGER
SMBUS Address [12]
5
4
+3.3V_ALW
2N7002
2N7002
2N7002
2N7002
2.2K
CLK_SCLK
CLK_SDATA CLOCK GE N
DAI_SMBCLK
DAI_SMBDATA DAI
2.2K
3
+3.3V_M
16
17
28
27
SMBUS Address [D2]
SMBUS Address [TBD]
+3.3V_RUN_BKT_PWR
2N7002
2N7002
2
WWAN_SMBCLK
WWAN_SMBDATA
+3.3V_RUN_WWAN_PWR
30
WWAN
32
SMBUS Address [TBD]
DELL CONFIDENTIAL/PROPRIETARY
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
SMBus Topology
LA-4291P
549Friday, Decemb er 07, 2007
1
of
0.1
Page 6
5
4
3
2
1
+3.3V_M
+3.3V_M
6 1
Q1A
2N7002DW-7-F_SOT363-6~D
2
5
Q1B
2N7002DW-7-F_SOT363-6~D
3
4
D D
CKG_SMBDAT<26,34,46>
CKG_SMBCLK<26,34,46>
2.2K_0402_5%~D
2.2K_0402_5%~D
12
R1
12
R2
CLK_SDATA
CLK_SCLK
Place close to U1 pin 18 and 40
C16
12
CPU_MCH_BSEL0<8,10>
CPU_MCH_BSEL1<8,10>
CLK_PCI_DOCK<31>
CLK_PCI_5028<33>
CLK_PCI_R5C833<29>
CLK_PCI_5035<34>
CLK_ICH_14M<24>
CLK_SIO_14M<33>
MCH_DREFCLK<10>
MCH_DREFCLK#<10>
CLK_PCI_ICH<22>
33P_0402_50V8J~D
33P_0402_50V8J~D
CLK_ICH_48M<24>
CLK_PCI_TPM<32>
Place crystal within
500 mils of CK505
C C
CPU_MCH_BSEL2<8,10>
B B
A A
+3.3V_RUN
R45
1 2
+3.3V_RUN
R50
1 2
12
R58
10K_0402_5%~D
10K_0402_5%~D
10K_0402_5%~D
PCI_PCM
PCI_ICH
PCI_SIO
TME0PIN 32
Overclocking enable
*
ITP_EN
Overclocking disable1
PIN 37
01Pin 5/6 as SRC_10
*
Pin 5/6 as CP U_ITP
FCTSEL1 PIN43 PIN44 PIN47 PIN48
0=UMA
*
1=DIS
5
DOT96T DOT96C 96/100M_T 96/100M_C
27M_out 27M SSout SRCT0 SRCC0
12
Y6
C17
CLK_ICH_48M FSA
CPU_MCH_BSEL0
CPU_MCH_BSEL1
CPU_MCH_BSEL2
CLK_PCI_TPM
CLK_PCI_R5C833
CLK_PCI_DOCK
CLK_PCI_5035 PCI_EC
CLK_ICH_14M
CLK_SIO_14M
MCH_DREFCLK
MCH_DREFCLK#
14.31818MHZ_20PF_1Y714318CE1B~D
12
R21 33_0402_5%~D
R23 2.2K_0402_5%~D
R25 10K_0402_5%~D
R27 33_0402_5%~D
R28 33_0402_5%~D
R31 22_0402_5%~D
R33 22_0402_5%~D
R34 33_0402_5%~D
R35 22_0402_5%~D
R37 22_0402_5%~D
R40 33_0402_5%~D
R41 33_0402_5%~D
R44 33_0402_5%~D
4
+3.3V_M
R19 0_0402_5%~D
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
BLM21AG601SN1D_0805~D
0.1U_0402_16V4Z~D
1
C1
2
12
12
12
12
12
CLK_PWRGD<24>
1 2
C12
L1
C9
0.047U_0402_16V4Z~D
1
2
0.1U_0402_16V4Z~D
1
C10
2
0.047U_0402_16V4Z~D
1
C13
2
CLK_XTAL_IN
CLK_XTAL_OUT
FSC
PCI_SIOCLK_PCI_5028
PCI_TPM
PCI_PCM
CLKREF
DOT96
DOT96#
PCI_ICHCLK_PCI_ICH
CLK_PWRGD
CLK_SCLK
CLK_SDATA
+CK_VDD_MAIN
0.1U_0402_16V4Z~D
1
2
C2
49
54
65
30
36
12
18
40
20
19
41
45
23
34
33
32
27
22
43
44
37
39
16
17
15
21
31
35
42
68
73
C4
2
2
U1
1
VDD_SRC
VDD_SRC
VDD_SRC
SLG8LP554BVTR
VDD_SRC
VDD_PCI
VDD_PCI
VDD_CPU
VDD_REF
VDD_48
XTAL_IN
XTAL_OUT
USB_48MHz/FSLA
FSL_B/TEST_MODE
REF_0/FSL_C/TEST_SEL
PCICLK4/FCT_SEL
PCICLK3
PCICLK2/TME
PCICLK1
REF_1
DOT_96/27M
DOT_96#/27M_SS
PCICLK_F0/ITP_EN
CKPWRGD/PD#
9
NC
SMBCLK
SMBDAT
4
VSS_SRC
VSS_CPU
VSS_REF
VSS_PCI
VSS_PCI
VSS_48
VSS_SRC
THRM_PAD
SLG8LP554BVTR_QFN72_10X10~D
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
0.1U_0402_16V4Z~D
10U_0805_6.3V6-M~D
1
1
C3
0.1U_0402_16V4Z~D
1
1
C5
2
2
R12
1 2
2.2_0603_5%~D
0.1U_0402_16V4Z~D
C6
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
1
1
C7
2
2
+CK_VDD_A
VDD_A
VSS_A
PCI_STP#
CPU_STP#
CPU_1
CPU_1#
CPU_0
CPU_0#
CPU_ITP/SRC_10
CPU_ITP#/SRC_10#
SRC_9
SRC_9#
CLKREQ_9#
SRC_8
SRC_8#
CLKREQ_8#
SRC_7
SRC_7#
CLKREQ_7#
SRC_6
SRC_6#
CLKREQ_6#
SRC_5
SRC_5#
CLKREQ_5#
SRC_4
SRC_4#
CLKREQ_4#
SRC_3
SRC_3#
CLKREQ_3#
SRC_2
SRC_2#
CLKREQ_2#
SRC_1/SATA
SRC_1#/SATA#
CLKREQ_1#
LCD_CLK/SRC_0
LCD_CLK#/SRC_0#
0.047U_0402_16V4Z~D
4.7U_0603_6.3V4Z~D
C15
C14
1
1
2
2
7
8
25
24
11
10
14
13
6
5
3
2
72
70
69
71
66
67
38
63
64
62
60
61
29
58
59
57
55
56
28
52
53
26
50
51
46
47
48
H_STP_PCI#
H_STP_CPU#
CLK_MCH_BCLK
CLK_MCH_BCLK#
CLK_CPU_BCLK
CLK_CPU_BCLK#
CLK_CPU_ITP
CLK_CPU_ITP#
CLK_PCIE_MINI2
CLK_PCIE_MINI2#
MINI2CLK_REQ#
CLK_PCIE_MINI1
CLK_PCIE_MINI1#
MINI1CLK_REQ#
CLK_PCIE_ICH
CLK_PCIE_ICH#
CLK_PCIE_EXP
CLK_PCIE_EXP#
EXPCLK_REQ#
CLK_MCH_3GPLL
CLK_MCH_3GPLL#
CLK_3GPLLREQ#_R
CLK_PCIE_SATA
CLK_PCIE_SATA#
SATA_CLKREQ#_R
DREF_SSCLK
DREF_SSCLK#
1 2
475_0402_1%~D
1 2
475_0402_1%~D
2
H_STP_PCI# <24>
H_STP_CPU# <24>
CLK_MCH_BCLK <10>
CLK_MCH_BCLK# <10>
CLK_CPU_BCLK <7>
CLK_CPU_BCLK# <7>
CLK_CPU_ITP <7>
CLK_CPU_ITP# <7>
CLK_PCIE_MINI2 <30>
CLK_PCIE_MINI2# <30>
MINI2CLK_REQ# <30>
CLK_PCIE_MINI1 <30>
CLK_PCIE_MINI1# <30>
MINI1CLK_REQ# <30>
CLK_PCIE_ICH <24>
CLK_PCIE_ICH# <24>
CLK_PCIE_EXP <35>
CLK_PCIE_EXP# <35>
EXPCLK_REQ# <35>
CLK_MCH_3GPLL <10>
CLK_MCH_3GPLL# <10>
R51
CLK_PCIE_SATA <23>
CLK_PCIE_SATA# <23>
R55
DREF_SSCLK <10>
DREF_SSCLK# <10>
FSC
CLKSEL2
0
*
0
MINI2CLK_REQ#
MINI1CLK_REQ#
EXPCLK_REQ#
CLK_3GPLLREQ#
SATA_CLKREQ#
CLK_3GPLLREQ# <10>
SATA_CLKREQ# <24>
CLKSEL1
10
1
R6 10K_0402_5%~D
R5 10K_0402_5%~D
R10 10K_0402_5%~D
R7 10K_0402_5%~D
R8 10K_0402_5%~D
FSAFSB
CLKSEL0
00
0
1
1 2
1 2
1 2
1 2
1 2
CPU
MHz
266
200
166
DELL CONFIDENTIAL/PROPRIETARY
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
Clock GEN. with internal terminations
LA-4291P
1
SRC
MHz
100
100
100
649Friday, Decemb er 07, 2007
PCI
MHz
33.3
33.3
33.3
+3.3V_RUN
of
0.1
Page 7
5
H_A#[3..35]<10>
D D
H_ADSTB#0<10>
H_REQ#0<10>
H_REQ#1<10>
H_REQ#2<10>
H_REQ#3<10>
H_REQ#4<10>
C C
H_ADSTB#1<10>
H_A20M#<23>
H_FERR#<23>
H_IGNNE#<23>
H_STPCLK#<23>
H_INTR<23>
H_NMI<23>
H_SMI#<23>
B B
H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_ADSTB#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35 H_THERMDA
H_ADSTB#1
H_A20M#
H_FERR#
H_IGNNE#
H_STPCLK#
H_INTR
H_NMI
H_SMI#
U62A
P2
A[3]#
V4
A[4]#
AG1
AM4
AM2
AG5
W1
AA1
AB4
AC5
AD2
AD4
AA5
AE5
AB2
AC1
W5
AN1
AK4
AT4
AK2
AT2
AH2
AF4
AJ5
AH4
AP4
AR5
AJ1
AL1
AU5
AP2
AR1
AN5
F10
AL5
ADDR GROUP 0
A[5]#
T4
A[6]#
A[7]#
A[8]#
T2
A[9]#
A[10]#
A[11]#
A[12]#
A[13]#
A[14]#
A[15]#
A[16]#
Y4
ADSTB[0]#
R1
REQ[0]#
R5
REQ[1]#
U1
REQ[2]#
P4
REQ[3]#
REQ[4]#
A[17]#
ADDR GROUP 1
A[18]#
A[19]#
A[20]#
A[21]#
A[22]#
A[23]#
A[24]#
A[25]#
A[26]#
A[27]#
A[28]#
A[29]#
A[30]#
A[31]#
A[32]#
THERMAL
A[33]#
A[34]#
A[35]#
ADSTB[1]#
C7
A20M#
ICH
D4
FERR#
THERMTRIP#
IGNNE#
F8
STPCLK#
C9
C5
E5
V2
Y2
J9
F4
H8
H CLK
LINT0
LINT1
SMI#
RSVD01
RSVD02
RSVD03
RSVD04
RSVD05
RSVD06
RSVD07
PENRYN SFF_UFCBGA956~D
ADS#
BNR#
BPRI#
DEFER#
DRDY#
DBSY#
BR0#
IERR#
INIT#
CONTROL
LOCK#
RESET#
RS[0]#
RS[1]#
RS[2]#
TRDY#
HIT#
HITM#
BPM[0]#
BPM[1]#
BPM[2]#
BPM[3]#
PRDY#
PREQ#
TCK
TDO
TMS
XDP/ITP SIGNALS
TRST#
DBR#
PROCHOT#
THERMDA
THERMDC
BCLK[0]
BCLK[1]
TDI
RESERVED
Layout Note: for ITP700Flex debug port with a XDP based Run Control Tools
ITP_BPM#[0..5], TCK, and TMS routings
must be a maximum of 1.5ns = 7500 mil
4
H_ADS#
M4
J5
L5
N5
F38
J1
M2
B40
D8
N1
G5
K2
H4
K4
L1
H2
F2
AY8
BA7
BA5
AY2
AV10
AV2
AV4
AW7
AU1
AW5
AV8
J7
D38
BB34
BD34
B10
A35
C35
H_BNR#
H_BPRI#
H_DEFER#
H_DRDY#
H_DBSY#
H_BR0#
H_IERR#
H_INIT#
H_LOCK#
H_RESET#
H_RS#0H_REQ#0
H_RS#1
H_RS#2
H_TRDY#
H_HIT#
H_HITM#
ITP_BPM#0
ITP_BPM#1
ITP_BPM#2
ITP_BPM#3
ITP_BPM#4
ITP_BPM#5
ITP_TCK
ITP_TDI
ITP_TDO
ITP_TMS
ITP_TRST#
ITP_DBRESET#
EC_CPU_PROCHOT#
H_THERMDC
H_THERMTRIP#
CLK_CPU_BCLK
CLK_CPU_BCLK#
+1.05V_VCCP
56_0402_5%~D
1 2
+1.05V_VCCP
51_0402_5%~D
1 2
R63
R64
H_ADS# <10>
H_BNR# <10>
H_BPRI# <10>
H_DEFER# <10>
H_DRDY# <10>
H_DBSY# <10>
H_BR0# <10>
R59 56_0402_5%~D
H_INIT# <23>
H_LOCK# <10>
H_RESET# <10>
H_RS#0 <10>
H_RS#1 <10>
H_RS#2 <10>
H_TRDY# <10>
H_HIT# <10>
H_HITM# <10>
R1077
0_0402_5%~D
1 2
1 2
R1078
0_0402_5%~D
ITP_DBRESET# <24>
2
C19
100P_0402_50V8K~D@
1
H_THERMTRIP# <19>
CLK_CPU_BCLK <6>
CLK_CPU_BCLK# <6>
H_THERMDA, H_THERMDC routing together,
Trace width / Spacing = 10 / 10 mil
H_THERMTRIP#
ITP_BPM#5
Place close to CPU within 200 mil
+1.05V_VCCP
R67
51_0402_5%~D
1 2
R69
51_0402_5%~D
1 2
ITP_TDI
ITP_TRST#
Place close to CPU within 200ps = 1000 mil
12
ITP_BPM_R#3
ITP_BPM_R#5
+1.05V_VCCP
+1.05V_VCCP
12
R61
56_0402_5%~D
H_THERMDA <19>
H_THERMDC <19>
3
+1.05V_VCCP
1
C18
0.1U_0402_16V4Z~D
2
Place close to JITP within 100 mil
H_RESET#
CLK_CPU_ITP<6>
CLK_CPU_ITP#<6>
R60
1 2
1K_0402_5%~D
2
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
JITP
VTT1
VTT0
VTAP
DBR#
DBA#
BPM0#
GND5
BPM1#
GND4
BPM2#
GND3
BPM3#
GND2
BPM4#
GND1
BPM5#
RESET#
FBO
GND0
BCLKP
BCLKN
TDO
NC2
TCK
NC1
TRST#
TMS
TDI
ITP_DBRESET#
29
30
GND6
GND7
MOLEX_52435-2891_28P~D@
+1.05V_VCCP
ITP_DBRESET#
ITP_BPM#0
ITP_BPM#1
ITP_BPM#2
ITP_BPM_R#3
ITP_BPM#4
ITP_BPM_R#5
ITP_TCK
CLK_CPU_ITP
CLK_CPU_ITP#
ITP_TDO
ITP_TCK
ITP_TRST#
ITP_TMS
ITP_TDI
+3.3V_ALW_ICH
150_0402_5%~D
1 2
R62
Place close to JITP within 1ns = 5000 mil
+1.05V_VCCP
R65
51_0402_5%~D@
1 2
51_0402_5%~D
1 2
51_0402_5%~D
1 2
51_0402_5%~D
1 2
H_RESET#
R66
ITP_TDO
R68
ITP_TMS
R70
ITP_TCK
1
U62D
B42
VSS[001]
F44
VSS[002]
D44
VSS[003]
D42
VSS[004]
F42
VSS[005]
H42
VSS[006]
K42
VSS[007]
M42
VSS[008]
P42
VSS[009]
T42
VSS[010]
V42
VSS[011]
Y42
VSS[012]
AB42
VSS[013]
AD42
VSS[014]
AF42
VSS[015]
AH42
VSS[016]
AK42
VSS[017]
AM42
VSS[018]
AP42
VSS[019]
AY44
VSS[020]
AV44
VSS[021]
AT42
VSS[022]
AV42
VSS[023]
AY42
VSS[024]
BA43
VSS[025]
BB42
VSS[026]
C39
VSS[027]
E39
VSS[028]
G37
VSS[029]
H38
VSS[030]
J39
VSS[031]
L39
VSS[032]
M38
VSS[033]
N39
VSS[034]
R39
VSS[035]
T38
VSS[036]
U39
VSS[037]
W39
VSS[038]
Y38
VSS[039]
AA39
VSS[040]
AC39
VSS[041]
AD38
VSS[042]
AE39
VSS[043]
AG39
VSS[044]
AH38
VSS[045]
AJ39
VSS[046]
AL39
VSS[047]
AM38
VSS[048]
AN39
VSS[049]
AR39
VSS[050]
AR37
VSS[051]
AT38
VSS[052]
AU39
VSS[053]
AU37
VSS[054]
AW39
VSS[055]
AW37
VSS[056]
BA39
VSS[057]
BC41
VSS[058]
BD40
VSS[059]
BD38
VSS[060]
B36
VSS[061]
H34
VSS[062]
D36
VSS[063]
K34
VSS[064]
M34
VSS[065]
M36
VSS[066]
P34
VSS[067]
T34
VSS[068]
V34
VSS[069]
T36
VSS[070]
Y34
VSS[071]
AB34
VSS[072]
AD34
VSS[073]
Y36
VSS[074]
AD36
VSS[075]
AF34
VSS[076]
AH34
VSS[077]
AH36
VSS[078]
AK34
VSS[079]
AM34
VSS[080]
AP34
VSS[081]
PENRYN SFF_UFCBGA956~D
VSS[082]
VSS[083]
VSS[084]
VSS[085]
VSS[086]
VSS[087]
VSS[088]
VSS[089]
VSS[090]
VSS[091]
VSS[092]
VSS[093]
VSS[094]
VSS[095]
VSS[096]
VSS[097]
VSS[098]
VSS[099]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
VSS[159]
VSS[160]
VSS[161]
VSS[162]
VSS[163]
AM36
AR35
AU35
AV34
AW35
AW33
AY34
AT36
AV36
BA33
BC33
BB36
BD36
C27
C29
C31
E29
E27
G29
G27
E31
G31
J29
J27
L29
L27
N29
N27
J31
L31
N31
R29
R27
U29
U27
R31
U31
W29
W27
W31
AA29
AA27
AC29
AC27
AA31
AC31
AE29
AE27
AG29
AG27
AJ29
AJ27
AE31
AG31
AJ31
AL29
AL27
AN29
AN27
AL31
AN31
AR29
AR27
AR31
AU29
AU27
AW29
AW27
AU31
AW31
BA29
BA27
BC29
BC27
BA31
BC31
C21
C23
C25
E25
E23
E21
Place close to JITP within 200ps = 1000 mil
ITP_BPM#[0..5], and TCK to FBO routings
must be length matched to within 50ps = 250 mil
Place R70 close to JITP pin 5
A A
TCK to FBO routing should refer to debug port design guide
H_RESET# should be routed from GMCH with split to ITP conn. Refer to DG page #56
Depop JITP, C18, R68, R70, R64, R67, R69
when JIP connector is depopulated
5
4
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
DELL CONFIDENTIAL/PROPRIETARY
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
Penryn SFF ULV Processor(1/3)
LA-4291P
749Friday, Decemb er 07, 2007
1
of
0.1
Page 8
5
4
3
2
1
H_D#[0..63]<10>
H_D#0
H_D#1
H_D#2
D D
H_DSTBN#0<10>
H_DSTBP#0<10>
H_DINV#0<10>
C C
B B
*
H_DSTBN#1<10>
H_DSTBP#1<10>
H_DINV#1<10>
+V_CPU_GTLREF
T1
CPU_MCH_BSEL0<6,10>
CPU_MCH_BSEL1<6,10>
CPU_MCH_BSEL2<6,10>
FSB BSEL2 BSEL0
BCLK BSEL1
166
667
800 200
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_DSTBN#0
H_DSTBP#0
H_DINV#0 H_DINV#2
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_DSTBN#1
H_DSTBP#1
H_DINV#1 H_DINV#3
TEST1
TEST2
TEST3
TEST4
TEST5
TEST6
CPU_MCH_BSEL0
CPU_MCH_BSEL1
CPU_MCH_BSEL2
1
0
01
01067 266
0
U62B
F40
D[0]#
G43
D[1]#
E43
D[2]#
J43
D[3]#
H40
D[4]#
H44
D[5]#
G39
D[6]#
E41
D[7]#
L41
D[8]#
K44
D[9]#
N41
D[10]#
T40
D[11]#
M40
D[12]#
G41
D[13]#
M44
D[14]#
L43
D[15]#
K40
DSTBN[0]#
J41
DSTBP[0]#
P40
DINV[0]#
P44
D[16]#
V40
D[17]#
V44
D[18]#
AB44
D[19]#
R41
D[20]#
W41
D[21]#
N43
D[22]#
U41
D[23]#
AA41
D[24]#
AB40
D[25]#
AD40
D[26]#
AC41
D[27]#
AA43
D[28]#
Y40
D[29]#
Y44
D[30]#
T44
D[31]#
U43
DSTBN[1]#
W43
DSTBP[1]#
R43
DINV[1]#
AW43
GTLREF
E37
TEST1
D40
TEST2
C43
TEST3
AE41
TEST4
AY10
TEST5
AC43
TEST6
A37
BSEL[0]
C37
BSEL[1]
B38
BSEL[2]
PENRYN SFF_UFCBGA956~D
1
0
0
D[32]#
D[33]#
D[34]#
DATA GROUP 0
D[35]#
D[36]#
D[37]#
D[38]#
D[39]#
D[40]#
D[41]#
D[42]#
D[43]#
D[44]#
D[45]#
DATA GROUP 2DATA GROUP 3
D[46]#
D[47]#
DSTBN[2]#
DSTBP[2]#
DINV[2]#
D[48]#
D[49]#
D[50]#
D[51]#
DATA GROUP 1
D[52]#
D[53]#
D[54]#
D[55]#
D[56]#
D[57]#
D[58]#
D[59]#
D[60]#
D[61]#
D[62]#
D[63]#
DSTBN[3]#
DSTBP[3]#
DINV[3]#
COMP[0]
MISC
COMP[1]
COMP[2]
COMP[3]
DPRSTP#
DPSLP#
DPWR#
PWRGOOD
SLP#
PSI#
T2
T3
Route TEST3 and TEST5 signals
through a ground referenced Z0 = 55ohm
trace that ends in a via that is near a GND via.
AR43
AH40
AF40
AJ43
AG41
AF44
AH44
AM44
AN43
AM40
AK40
AG43
AP40
AN41
AL41
AK44
AL43
AJ41
AV38
AT44
AV40
AU41
AW41
AR41
BA37
BB38
AY36
AT40
BC35
BC39
BA41
BB40
BA35
AU43
AY40
AY38
BC37
AE43
AD44
AE1
AF2
G7
B8
C41
E7
D10
BD10
TEST3
TEST5
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_DSTBN#2
H_DSTBP#2
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
H_DSTBN#3
H_DSTBP#3
COMP0
COMP1
COMP2
COMP3
H_DPRSTP#
H_DPSLP#
H_DPWR#
H_PWRGOOD
H_CPUSLP#
H_PSI#
H_DPRSTP# <10,23,43>
H_DPSLP# <23>
H_DPWR# <10>
H_PWRGOOD <23>
H_CPUSLP# <10>
H_PSI# <43>
H_D#32
AP44
H_DSTBN#2 <10>
H_DSTBP#2 <10>
H_DINV#2 <10>
H_DSTBN#3 <10>
H_DSTBP#3 <10>
H_DINV#3 <10>
27.4_0402_1%~D
54.9_0402_1%~D
12
12
R72
R71
Resistor placed within 0.5" of CPU
pin.Trace should be at least 25
mils away fro m a n y other toggling
signal. COMP0, COMP2 trace
should be 27.4 ohm. COMP1,
COMP3 should be 55ohm.
R73
27.4_0402_1%~D
54.9_0402_1%~D
12
12
R74
+VCC_CORE +VCC_CORE
U62C
F32
VCC[001]
G33
VCC[002]
H32
VCC[003]
J33
VCC[004]
K32
VCC[005]
L33
VCC[006]
M32
VCC[007]
N33
VCC[008]
P32
VCC[009]
R33
VCC[010]
T32
VCC[011]
U33
VCC[012]
V32
VCC[013]
W33
VCC[014]
Y32
VCC[015]
AA33
VCC[016]
AB32
VCC[017]
AC33
VCC[018]
AD32
VCC[019]
AE33
VCC[020]
AF32
VCC[021]
AG33
VCC[022]
AH32
VCC[023]
AJ33
VCC[024]
AK32
VCC[025]
AL33
VCC[026]
AM32
VCC[027]
AN33
VCC[028]
AP32
VCC[029]
AR33
VCC[030]
AT34
VCC[031]
AT32
VCC[032]
AU33
VCC[033]
AV32
VCC[034]
AY32
VCC[035]
BB32
VCC[036]
BD32
VCC[037]
B28
VCC[038]
B30
VCC[039]
B26
VCC[040]
D28
VCC[041]
D30
VCC[042]
F30
VCC[043]
F28
VCC[044]
H30
VCC[045]
H28
VCC[046]
D26
VCC[047]
F26
VCC[048]
H26
VCC[049]
K30
VCC[050]
K28
VCC[051]
M30
VCC[052]
M28
VCC[053]
K26
VCC[054]
M26
VCC[055]
P30
VCC[056]
P28
VCC[057]
T30
VCC[058]
T28
VCC[059]
V30
VCC[060]
V28
VCC[061]
P26
VCC[062]
T26
VCC[063]
V26
VCC[064]
Y30
VCC[065]
Y28
VCC[066]
AB30
VCC[067]
PENRYN SFF_UFCBGA956~D
VCC[068]
VCC[069]
VCC[070]
VCC[071]
VCC[072]
VCC[073]
VCC[074]
VCC[075]
VCC[076]
VCC[077]
VCC[078]
VCC[079]
VCC[080]
VCC[081]
VCC[082]
VCC[083]
VCC[084]
VCC[085]
VCC[086]
VCC[087]
VCC[088]
VCC[089]
VCC[090]
VCC[091]
VCC[092]
VCC[093]
VCC[094]
VCC[095]
VCC[096]
VCC[097]
VCC[098]
VCC[099]
VCC[100]
VCCP_001
VCCP_002
VCCP_003
VCCP_004
VCCP_005
VCCP_006
VCCP_007
VCCP_008
VCCP_009
VCCP_010
VCCP_011
VCCP_012
VCCP_013
VCCP_014
VCCP_015
VCCP_016
VCCA[01]
VCCA[02]
VID[0]
VID[1]
VID[2]
VID[3]
VID[4]
VID[5]
VID[6]
VCCSENSE
VSSSENSE
AB28
AD30
AD28
Y26
AB26
AD26
AF30
AF28
AH30
AH28
AF26
AH26
AK30
AK28
AM30
AM28
AP30
AP28
AK26
AM26
AP26
AT30
AT28
AV30
AV28
AY30
AY28
AT26
AV26
AY26
BB30
BB28
BD30
J11
E11
G11
J37
K38
L37
N37
P38
R37
U37
V38
W37
AA37
AB38
AC37
AE37
B34
D34
BD8
BC7
BB10
BB8
BC5
BB4
AY4
BD12
BC13
VID0
VID1
VID2
VID3
VID4
VID5
VID6
VCCSENSE
VSSSENSE
C20
1
+
2
+1.05V_VCCP
220U_D2_4VY_R15M~D
VID0 <43>
VID1 <43>
VID2 <43>
VID3 <43>
VID4 <43>
VID5 <43>
VID6 <43>
VCCSENSE <43>
VSSSENSE <43>
CRB is 270uF
10U_0805_10V4Z~D
0.01U_0402_16V7K~D
C22
C21
1
1
2
2
+1.5V_RUN
Length match within 25 mils, Z0=27.4 ohm
+1.05V_VCCP
12
+V_CPU_GTLREF
Layout close CPU PIN AW43
Zo = 55 ohm, 0.5 inch (max)
A A
R75
1K_0402_1%~D
12
R80
2K_0402_1%~D
1K_0402_5%~D@
R77
R76
1 2
Place C23 close to the
CPU_TEST4 pin. Make sure
CPU_TEST4 routing is
reference to GND and away
from other n o i sy signal.
TEST1
TEST2
TEST4
0.1U_0402_10V7K~D@
1K_0402_5%~D@
2
C23
1
1 2
Place R78 and R81 close to CPU within 1000 mil
+VCC_CORE
R78
1 2
100_0402_1%~D
R81
1 2
100_0402_1%~D
VCCSENSE
VSSSENSE
1 2
27.4_0402_1%~D@
Reserve for testing only
R79
Route VCCSENSE and VSSSENSE trace at 27.4 ohms with 7 mil spacing
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
Penryn SFF ULV Processor(2/3)
LA-4291P
849Friday, Decemb er 07, 2007
1
0.1
of
Page 9
5
U62F
+VCC_CORE
D D
C C
B B
A A
+1.05V_VCCP
BD28
VCC_101
BB26
VCC_102
BD26
VCC_103
B22
VCC_104
B24
VCC_105
D22
VCC_106
D24
VCC_107
F24
VCC_108
F22
VCC_109
H24
VCC_110
H22
VCC_111
K24
VCC_112
K22
VCC_113
M24
VCC_114
M22
VCC_115
P24
VCC_116
P22
VCC_117
T24
VCC_118
T22
VCC_119
V24
VCC_120
V22
VCC_121
Y24
VCC_122
Y22
VCC_123
AB24
VCC_124
AB22
VCC_125
AD24
VCC_126
AD22
VCC_127
AF24
VCC_128
AF22
VCC_129
AH24
VCC_130
AH22
VCC_131
AK24
VCC_132
AK22
VCC_133
AM24
VCC_134
AM22
VCC_135
AP24
VCC_136
AP22
VCC_137
AT24
VCC_138
AT22
VCC_139
AV24
VCC_140
AV22
VCC_141
AY24
VCC_142
AY22
VCC_143
BB24
VCC_144
BB22
VCC_145
BD24
VCC_146
BD22
VCC_147
B16
VCC_148
B18
VCC_149
B20
VCC_150
D16
VCC_151
D18
VCC_152
F18
VCC_153
F16
VCC_154
H18
VCC_155
H16
VCC_156
D20
VCC_157
F20
VCC_158
H20
VCC_159
K18
VCC_160
K16
VCC_161
M18
VCC_162
M16
VCC_163
K20
VCC_164
M20
VCC_165
P18
VCC_166
P16
VCC_167
T18
VCC_168
T16
VCC_169
V18
VCC_170
V16
VCC_171
P20
VCC_172
T20
VCC_173
V20
VCC_174
Y18
VCC_175
Y16
VCC_176
AB18
VCC_177
AB16
VCC_178
AD18
VCC_179
AD16
VCC_180
Y20
VCC_181
AB20
VCC_182
AD20
VCC_183
AF18
VCC_184
AF16
VCC_185
AH18
VCC_186
AH16
VCC_187
AF20
VCC_188
AH20
VCC_189
AK18
VCC_190
AK16
VCC_191
AM18
VCC_192
AM16
VCC_193
AP18
VCC_194
AP16
VCC_195
AK20
VCC_196
AM20
VCC_197
AP20
VCC_198
AT18
VCC_199
AT16
VCC_200
AV18
VCC_201
AV16
VCC_202
AY18
VCC_203
AY16
VCC_204
AT20
VCC_205
AV20
VCC_206
AY20
VCC_207
BB18
VCC_208
BB16
VCC_209
BD18
VCC_210
BD16
VCC_211
BB20
VCC_212
BD20
VCC_213
AM14
VCC_214
AP14
VCC_215
AT14
VCC_216
AV14
VCC_217
AY14
VCC_218
BB14
VCC_219
BD14
VCC_220
AF38
VCCP_017
AG37
VCCP_018
AJ37
VCCP_019
AK38
VCCP_020
PENRYN SFF_UFCBGA956~D
5
VCCP_021
VCCP_022
VCCP_023
VCCP_024
VCCP_025
VCCP_026
VCCP_027
VCCP_028
VCCP_029
VCCP_030
VCCP_031
VCCP_032
VCCP_033
VCCP_034
VCCP_035
VCCP_036
VCCP_037
VCCP_038
VCCP_039
VCCP_040
VCCP_041
VCCP_042
VCCP_043
VCCP_044
VCCP_045
VCCP_046
VCCP_047
VCCP_048
VCCP_049
VCCP_050
VCCP_051
VCCP_052
VCCP_053
VCCP_054
VCCP_055
VCCP_056
VCCP_057
VCCP_058
VCCP_059
VCCP_060
VCCP_061
VCCP_062
VCCP_063
VCCP_064
VCCP_065
VCCP_066
VCCP_067
VCCP_068
VCCP_069
VCCP_070
VCCP_071
VCCP_072
VCCP_073
VCCP_074
VCCP_075
VCCP_076
VCCP_077
VCCP_078
VCCP_079
VCCP_080
VCCP_081
VCCP_082
VCCP_083
VCCP_084
VCCP_085
VCCP_086
VCCP_087
VCCP_088
VCCP_089
VCCP_090
VCCP_091
VCCP_092
VCCP_093
VCCP_094
VCCP_095
VCCP_096
VCCP_097
VCCP_098
VCCP_099
VCCP_100
VCCP_101
VCCP_102
VCCP_103
VCCP_104
VCCP_105
VCCP_106
VCCP_107
VCCP_108
VCCP_109
VCCP_110
VCCP_111
VCCP_112
VCCP_113
VCCP_114
VCCP_115
VCCP_116
VCCP_117
VCCP_118
VCCP_119
VCCP_120
VCCP_121
VCCP_122
VCCP_123
VCCP_124
VCCP_125
VCCP_126
VCCP_127
VCCP_128
VCCP_129
VCCP_130
VCCP_131
VCCP_132
VCCP_133
VCCP_134
VCCP_135
VCCP_136
VCCP_137
VCCP_138
VCCP_139
VCCP_140
VCCP_141
VCCP_142
VCCP_143
VCCP_144
VCCP_145
AL37
AN37
AP38
B32
C33
D32
E35
E33
F34
G35
F36
H36
J35
L35
N35
K36
R35
U35
P36
V36
W35
AA35
AC35
AB36
AE35
AG35
AJ35
AF36
AL35
AN35
AK36
AP36
B12
B14
C13
D12
D14
E13
F14
F12
G13
H14
H12
J13
K14
K12
L13
L11
M14
N13
N11
K10
P14
P12
R13
R11
T14
U13
U11
V14
V12
W13
W11
P10
V10
Y14
AA13
AA11
AB14
AB12
AC13
AC11
AD14
AB10
AE13
AE11
AF14
AF12
AG13
AG11
AH14
AJ13
AJ11
AF10
AK14
AK12
AL13
AL11
AN13
AN11
AP12
AR13
AR11
AK10
AP10
AU13
AU11
L9
L7
N9
N7
R9
R7
U9
U7
W9
W7
AA9
AA7
AC9
AC7
AE9
AE7
AG9
AG7
AJ9
AJ7
AL9
AL7
AN9
AN7
AR9
AR7
A33
A13
+1.05V_VCCP
4
U62E
G25
VSS_164
G23
VSS_165
G21
VSS_166
J25
VSS_167
J23
VSS_168
J21
VSS_169
L25
VSS_170
L23
VSS_171
L21
VSS_172
N25
VSS_173
N23
VSS_174
N21
VSS_175
R25
VSS_176
R23
VSS_177
R21
VSS_178
U25
VSS_179
U23
VSS_180
U21
VSS_181
W25
VSS_182
W23
VSS_183
W21
VSS_184
AA25
VSS_185
AA23
VSS_186
AA21
VSS_187
AC25
VSS_188
AC23
VSS_189
AC21
VSS_190
AE25
VSS_191
AE23
VSS_192
AE21
VSS_193
AG25
VSS_194
AG23
VSS_195
AG21
VSS_196
AJ25
VSS_197
AJ23
VSS_198
AJ21
VSS_199
AL25
VSS_200
AL23
VSS_201
AL21
VSS_202
AN25
VSS_203
AN23
VSS_204
AN21
VSS_205
AR25
VSS_206
AR23
VSS_207
AR21
VSS_208
AU25
VSS_209
AU23
VSS_210
AU21
VSS_211
AW25
VSS_212
AW23
VSS_213
AW21
VSS_214
BA25
VSS_215
BA23
VSS_216
BA21
VSS_217
BC25
VSS_218
BC23
VSS_219
BC21
VSS_220
C17
VSS_221
C19
VSS_222
E19
VSS_223
E17
VSS_224
G19
VSS_225
G17
VSS_226
J19
VSS_227
J17
VSS_228
L19
VSS_229
L17
VSS_230
N19
VSS_231
N17
VSS_232
R19
VSS_233
R17
VSS_234
U19
VSS_235
U17
VSS_236
W19
VSS_237
W17
VSS_238
AA19
VSS_239
AA17
VSS_240
AC19
VSS_241
AC17
VSS_242
AE19
VSS_243
AE17
VSS_244
AG19
VSS_245
AG17
VSS_246
AJ19
VSS_247
AJ17
VSS_248
AL19
VSS_249
AL17
VSS_250
AN19
VSS_251
AN17
VSS_252
AR19
VSS_253
AR17
VSS_254
AU19
VSS_255
AU17
VSS_256
AW19
VSS_257
AW17
VSS_258
BA19
VSS_259
BA17
VSS_260
BC19
VSS_261
BC17
VSS_262
C11
VSS_263
C15
VSS_264
E15
VSS_265
G15
VSS_266
H10
VSS_267
M12
VSS_268
J15
VSS_269
L15
VSS_270
N15
VSS_271
M10
VSS_272
T12
VSS_273
R15
VSS_274
U15
VSS_275
W15
VSS_276
T10
VSS_277
Y12
VSS_278
AD12
VSS_279
PENRYN SFF_UFCBGA956~D
4
VSS_280
VSS_281
VSS_282
VSS_283
VSS_284
VSS_285
VSS_286
VSS_287
VSS_288
VSS_289
VSS_290
VSS_291
VSS_292
VSS_293
VSS_294
VSS_295
VSS_296
VSS_297
VSS_298
VSS_299
VSS_300
VSS_301
VSS_302
VSS_303
VSS_304
VSS_305
VSS_306
VSS_307
VSS_308
VSS_309
VSS_310
VSS_311
VSS_312
VSS_313
VSS_314
VSS_315
VSS_316
VSS_317
VSS_318
VSS_319
VSS_320
VSS_321
VSS_322
VSS_323
VSS_324
VSS_325
VSS_326
VSS_327
VSS_328
VSS_329
VSS_330
VSS_331
VSS_332
VSS_333
VSS_334
VSS_335
VSS_336
VSS_337
VSS_338
VSS_339
VSS_340
VSS_341
VSS_342
VSS_343
VSS_344
VSS_345
VSS_346
VSS_347
VSS_348
VSS_349
VSS_350
VSS_351
VSS_352
VSS_353
VSS_354
VSS_355
VSS_356
VSS_357
VSS_358
VSS_359
VSS_360
VSS_361
VSS_362
VSS_363
VSS_364
VSS_365
VSS_366
VSS_367
VSS_368
VSS_369
VSS_370
VSS_371
VSS_372
VSS_373
VSS_374
VSS_375
VSS_376
VSS_377
VSS_378
VSS_379
VSS_380
VSS_381
VSS_382
VSS_383
VSS_384
VSS_385
VSS_386
VSS_387
VSS_388
VSS_389
VSS_390
VSS_391
VSS_392
VSS_393
VSS_394
VSS_395
AA15
AC15
Y10
AD10
AH12
AE15
AG15
AJ15
AH10
AM12
AL15
AN15
AR15
AM10
AT12
AV12
AW13
AW11
AY12
AU15
AW15
AT10
BA13
BA11
BB12
BC11
BA15
BC15
B6
D6
E9
F6
G9
H6
K8
K6
M8
M6
P8
P6
T8
T6
V8
V6
U5
Y8
Y6
AB8
AB6
AD8
AD6
AF8
AF6
AH8
AH6
AK8
AK6
AM8
AM6
AP8
AP6
AT8
AT6
AU9
AV6
AU7
AW9
AY6
BA9
BB6
BC9
BD6
B4
C3
E3
G3
J3
L3
N3
R3
U3
W3
AA3
AC3
AE3
AG3
AJ3
AL3
AN3
AR3
AU3
AW3
BA3
BC3
D2
E1
G1
AW1
BA1
BB2
A41
A39
A29
A27
A31
A25
A23
A21
A19
A17
A11
A15
A7
A5
A9
BD4
+VCC_CORE
1
2
+VCC_CORE
1
2
+VCC_CORE
1
2
3
C1312
10U_0805_4VAM~D
C1320
10U_0805_4VAM~D
C1328
10U_0805_4VAM~D
1
C1313
10U_0805_4VAM~D
2
1
C1321
10U_0805_4VAM~D
2
1
C1329
10U_0805_4VAM~D
2
1
C1314
10U_0805_4VAM~D
2
1
C1322
10U_0805_4VAM~D
2
1
C1335
10U_0805_4VAM~D
2
1
C1315
10U_0805_4VAM~D
2
1
C1323
10U_0805_4VAM~D
2
1
C1336
10U_0805_4VAM~D
2
+VCC_CORE
1
C1330
+
2
2
1
2
1
2
1
2
470U_X_2VM_R6M~D
C1331
C1316
10U_0805_4VAM~D
C1324
10U_0805_4VAM~D
C1342
10U_0805_4VAM~D
1
+
2
Place these inside cavity on L8(North side Secondary)
+1.05V_VCCP
1
C25
0.1U_0402_10V7K~D
2
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
1
C26
0.1U_0402_10V7K~D
2
1
C27
0.1U_0402_10V7K~D
2
1
2
2
470U_X_2VM_R6M~D
470U_X_2VM_R6M~D
1
C1332
+
2
C28
0.1U_0402_10V7K~D
1
1
C1317
10U_0805_4VAM~D
2
1
C1325
10U_0805_4VAM~D
2
1
C1343
10U_0805_4VAM~D
2
1
C29
0.1U_0402_10V7K~D
2
1
C1318
10U_0805_4VAM~D
2
1
C1326
10U_0805_4VAM~D
2
1
C1344
10U_0805_4VAM~D
2
1
2
1
C1319
10U_0805_4VAM~D
2
1
C1327
10U_0805_4VAM~D
2
1
C1345
10U_0805_4VAM~D
2
C30
0.1U_0402_10V7K~D
DELL CONFIDENTIAL/PROPRIETARY
Title
Size Document Number Re v
Date: Sheet
Compal Electroni cs, Inc.
Penryn SFF ULV Processor(3/3)
LA-4291P
1
949Friday, December 07, 2007
0.1
of
Page 10
5
H_D#[0..63]<8>
D D
C C
R89
1 2
24.9_0402_1%~D
H_RESET#<7>
H_CPUSLP#<8>
B B
+1.05V_VCCP
12
R97
221_0402_1%~D
H_SWNG
0.1U_0402_10V7K~D
100_0402_1%~D
12
R103
1
C35
2
A A
MCH_TSATN_EC<33>
MMST3904-7-F_SOT323-3~D
1
C34
2
H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
H_SWNG
+H_RCOMP
H_RESET#
H_CPUSLP#
+H_VREF
+1.05V_VCCP
12
+H_VREF
0.1U_0402_10V7K~D@
12
R102
+3.3V_RUN
12
R112
C
Q22
E
3 1
5
R96
1K_0402_1%~D
2K_0402_1%~D
1K_0402_5%~D
U78A
J7
H_D#_0
H6
H_D#_1
L11
H_D#_2
J3
H_D#_3
H4
H_D#_4
G3
H_D#_5
K10
H_D#_6
K12
H_D#_7
L1
H_D#_8
M10
H_D#_9
M6
H_D#_10
N11
H_D#_11
L7
H_D#_12
K6
H_D#_13
M4
H_D#_14
K4
H_D#_15
P6
H_D#_16
W9
H_D#_17
V6
H_D#_18
V2
H_D#_19
P10
H_D#_20
W7
H_D#_21
N9
H_D#_22
P4
H_D#_23
U9
H_D#_24
V4
H_D#_25
U1
H_D#_26
W3
H_D#_27
V10
H_D#_28
U7
H_D#_29
W11
H_D#_30
U11
H_D#_31
AC11
H_D#_32
AC9
H_D#_33
Y4
H_D#_34
Y10
H_D#_35
AB6
H_D#_36
AA9
H_D#_37
AB10
H_D#_38
AA1
H_D#_39
AC3
H_D#_40
AC7
H_D#_41
AD12
H_D#_42
AB4
H_D#_43
Y6
H_D#_44
AD10
H_D#_45
AA11
H_D#_46
AB2
H_D#_47
AD4
H_D#_48
AE7
H_D#_49
AD2
H_D#_50
AD6
H_D#_51
AE3
H_D#_52
AG9
H_D#_53
AG7
H_D#_54
AE11
H_D#_55
AK6
H_D#_56
AF6
H_D#_57
AJ9
H_D#_58
AH6
H_D#_59
AF12
H_D#_60
AH4
H_D#_61
AJ7
H_D#_62
AE9
H_D#_63
B6
H_SWING
D4
H_RCOMP
J11
H_CPURST#
G9
H_CPUSLP#
L17
H_AVREF
K18
H_DVREF
CANTIGA GMCH S FF _ Q R4 6 B 0_ F CBGA1363~D
SIO_SLP_S4#<24,34>
1K_0402_5%~D
12
R111
2
B
C
E
3 1
+1.05V_VCCP
R118
2
B
330_0402_5%~D
Q23
MMST3904-7-F_SOT323-3~D
1.5V_SUS_PWRGD<34,42>
12
HOST
DDR_ON<34,37,45>
12
R115
54.9_0402_1%~D
MCH_TSATN#
H_ADSTB#_0
H_ADSTB#_1
H_BREQ#
H_DEFER#
H_DBSY#
HPLL_CLK
HPLL_CLK#
H_DPWR#
H_DRDY#
H_LOCK#
H_TRDY#
H_DINV#_0
H_DINV#_1
H_DINV#_2
H_DINV#_3
H_DSTBN#_0
H_DSTBN#_1
H_DSTBN#_2
H_DSTBN#_3
H_DSTBP#_0
H_DSTBP#_1
H_DSTBP#_2
H_DSTBP#_3
H_REQ#_0
H_REQ#_1
H_REQ#_2
H_REQ#_3
H_REQ#_4
R1060
1 2
0_0402_5%~D@
Place close to pin F34,F32,B38,A37 of U78
4
H_A#3
L15
H_A#_3
H_A#_4
H_A#_5
H_A#_6
H_A#_7
H_A#_8
H_A#_9
H_A#_10
H_A#_11
H_A#_12
H_A#_13
H_A#_14
H_A#_15
H_A#_16
H_A#_17
H_A#_18
H_A#_19
H_A#_20
H_A#_21
H_A#_22
H_A#_23
H_A#_24
H_A#_25
H_A#_26
H_A#_27
H_A#_28
H_A#_29
H_A#_30
H_A#_31
H_A#_32
H_A#_33
H_A#_34
H_A#_35
H_ADS#
H_BNR#
H_BPRI#
H_HIT#
H_HITM#
H_RS#_0
H_RS#_1
H_RS#_2
+3.3V_RUN
H_A#4
B14
H_A#5
C15
H_A#6
D12
H_A#7
F14
H_A#8
G17
H_A#9
B12
H_A#10
J15
H_A#11
D16
H_A#12
C17
H_A#13
D14
H_A#14
K16
H_A#15
F16
H_A#16
B16
H_A#17
C21
H_A#18
D18
H_A#19
J19
H_A#20
J21
H_A#21
B18
H_A#22
D22
H_A#23
G19
H_A#24
J17
H_A#25
L21
H_A#26
L19
H_A#27
G21
H_A#28
D20
H_A#29
K22
H_A#30
F18
H_A#31
K20
H_A#32
F20
H_A#33
F22
H_A#34
B20
H_A#35
A19
H_ADS#
F10
H_ADSTB#0
A15
H_ADSTB#1
C19
H_BNR#
C9
H_BPRI#
B8
H_BR0#
C11
H_DEFER#
E5
H_DBSY#
D6
CLK_MCH_BCLK
AH10
CLK_MCH_BCLK#
AJ11
H_DPWR#
G11
H_DRDY#
H2
H_HIT#
C7
H_HITM#
F8
H_LOCK#
A11
H_TRDY#
D8
H_DINV#0
L9
H_DINV#1
N7
H_DINV#2
AA7
H_DINV#3
AG3
H_DSTBN#0
K2
H_DSTBN#1
N3
H_DSTBN#2
AA3
H_DSTBN#3
AF4
H_DSTBP#0
L3
H_DSTBP#1
M2
H_DSTBP#2
Y2
H_DSTBP#3
AF2
H_REQ#0
J13
H_REQ#1
L13
H_REQ#2
C13
H_REQ#3
G13
H_REQ#4
G15
H_RS#0
F4
H_RS#1
F2
H_RS#2
G7
+3.3V_M
1 2
0.1U_0402_16V4Z~D
5
1
P
A
4
Y
2
B
G
U92
3
74AHCT1G08GW SOT353~D
R94 100K_0402_5%~D
R95 100K_0402_5%~D
R99 100K_0402_5%~D
R100 100K_0402_5%~D
4
C1346
R1058
1 2
12K_0402_5%~D
12
12
12
12
H_A#[3..35] <7>
+V_DDR_MCH_REF
H_ADS# <7>
H_ADSTB#0 <7>
H_ADSTB#1 <7>
H_BNR# <7>
H_BPRI# <7>
H_BR0# <7>
H_DEFER# <7>
H_DBSY# <7>
CLK_MCH_BCLK <6>
CLK_MCH_BCLK# <6>
H_DPWR# <8>
H_DRDY# <7>
H_HIT# <7>
H_HITM# <7>
H_LOCK# <7>
H_TRDY# <7>
H_DINV#0 <8>
H_DINV#1 <8>
H_DINV#2 <8>
H_DINV#3 <8>
H_DSTBN#0 <8>
H_DSTBN#1 <8>
H_DSTBN#2 <8>
H_DSTBN#3 <8>
H_DSTBP#0 <8>
H_DSTBP#1 <8>
H_DSTBP#2 <8>
H_DSTBP#3 <8>
H_REQ#0 <7>
H_REQ#1 <7>
H_REQ#2 <7>
H_REQ#3 <7>
H_REQ#4 <7>
H_RS#0 <7>
H_RS#1 <7>
H_RS#2 <7>
SM_PWROK
12
R1059
10K_0402_5%~D
DDPC_CTRLCLK
DDPC_CTRLDATA
SDVO_CTRLCLK
SDVO_CTRLDATA
+1.5V_MEM
+3.3V_RUN
+1.05V_M
R90
R93
3
T6
T12
T15
T19
M_ODT0<16,17>
T21
GFX_VID0<44>
GFX_VID1<44>
GFX_VID2<44>
GFX_VID3<44>
GFX_VID4<44>
M_CLK_DDR0
M_CLK_DDR1
M_CLK_DDR2
M_CLK_DDR3
M_CLK_DDR#0
M_CLK_DDR#1
M_CLK_DDR#2
M_CLK_DDR#3
DDR_CKE0
DDR_CKE1
DDR_CKE2_DIMM
DDR_CKE3_DIMM
DDR_CS#0
DDR_CS#1
DDR_CS2_DIMM#
DDR_CS3_DIMM#
M_ODT0
M_ODT1
M_ODT2_DIMM
M_ODT3_DIMM
SMRCOMP
SMRCOMP#
SMRCOMP_VOH
SMRCOMP_VOL
SM_PWROK
DDR3_DRAMRST#
MCH_DREFCLK
MCH_DREFCLK#
DREF_SSCLK
DREF_SSCLK#
CLK_MCH_3GPLL
CLK_MCH_3GPLL#
DMI_MRX_ITX_N0
DMI_MRX_ITX_N1
DMI_MRX_ITX_N2
DMI_MRX_ITX_N3
DMI_MRX_ITX_P0
DMI_MRX_ITX_P1
DMI_MRX_ITX_P2
DMI_MRX_ITX_P3
DMI_MTX_IRX_N0
DMI_MTX_IRX_N1
DMI_MTX_IRX_N2
DMI_MTX_IRX_N3
DMI_MTX_IRX_P0
DMI_MTX_IRX_P1
DMI_MTX_IRX_P2
DMI_MTX_IRX_P3
GFX_VID0
GFX_VID1
GFX_VID2
GFX_VID3
GFX_VID4
GFX_VR_ON
CL_CLK0
CL_DATA0
ICH_CL_PWROK
CL_RST0#
+CL_VREF
DDPC_CTRLCLK
DDPC_CTRLDATA
SDVO_CTRLCLK
SDVO_CTRLDATA
CLK_3GPLLREQ#
MCH_ICH_SYNC#
MCH_TSATN#
R1032
1 2
33_0402_5%~D
MCH_SDIN2
M_CLK_DDR0<16,17>
M_CLK_DDR2<18>
M_CLK_DDR3<18>
M_CLK_DDR#0<16,17>
M_CLK_DDR#2<18>
M_CLK_DDR#3<18>
DDR_CKE0<16,17>
DDR_CKE2_DIMM<18>
DDR_CKE3_DIMM<18>
DDR_CS#0<16,17>
DDR_CS2_DIMM#<18>
DDR_CS3_DIMM#<18>
80.6_0402_1%~D
80.6_0402_1%~D
0.1U_0402_16V4Z~D
1
C31
2
12
R101
30K_0402_5%~D
GFX_VR_ON
12
R105
100K_0402_5%~D
1K_0402_1%~D
12
499_0402_1%~D
1 2
R82
R83
0.1U_0402_16V4Z~D
1
2
0.1U_0402_16V4Z~D
1
2
ICH_AZ_MCH_BITCLK<23>
ICH_AZ_MCH_RST#<23>
ICH_AZ_MCH_SDIN2<23>
ICH_AZ_MCH_SDOUT<23>
ICH_AZ_MCH_SYNC<23>
M_ODT2_DIMM<18>
M_ODT3_DIMM<18>
12
12
R87 499_0402_1%~D
1 2
DDR3_DRAMRST#<16,17,18>
C32
MCH_DREFCLK<6>
MCH_DREFCLK#<6>
C33
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
DREF_SSCLK<6>
DREF_SSCLK#<6>
CLK_MCH_3GPLL<6>
CLK_MCH_3GPLL#<6>
DMI_MRX_ITX_N0<24>
DMI_MRX_ITX_N1<24>
DMI_MRX_ITX_N2<24>
DMI_MRX_ITX_N3<24>
DMI_MRX_ITX_P0<24>
DMI_MRX_ITX_P1<24>
DMI_MRX_ITX_P2<24>
DMI_MRX_ITX_P3<24>
DMI_MTX_IRX_N0<24>
DMI_MTX_IRX_N1<24>
DMI_MTX_IRX_N2<24>
DMI_MTX_IRX_N3<24>
DMI_MTX_IRX_P0<24>
DMI_MTX_IRX_P1<24>
DMI_MTX_IRX_P2<24>
DMI_MTX_IRX_P3<24>
GFX_VR_ON<44>
CL_CLK0<24>
CL_DATA0<24>
ICH_CL_PWROK<24,34>
CL_RST0#<24>
DDPC_CTRLCLK<31>
DDPC_CTRLDATA<31>
SDVO_CTRLCLK<31>
SDVO_CTRLDATA<31>
CLK_3GPLLREQ#<6>
MCH_ICH_SYNC#<24>
3
U78B
BB32
SA_CK_0
BA25
SA_CK_1
BA33
SB_CK_0
BA23
SB_CK_1
BA31
SA_CK#_0
BC25
SA_CK#_1
BC33
SB_CK#_0
BB24
SB_CK#_1
BC35
SA_CKE_0
BE33
SA_CKE_1
BE37
SB_CKE_0
BC37
SB_CKE_1
BK18
SA_CS#_0
BK16
SA_CS#_1
BE23
SB_CS#_0
BC19
SB_CS#_1
BJ17
SA_ODT_0
BJ19
SA_ODT_1
BC17
SB_ODT_0
BE17
SB_ODT_1
BL25
SM_RCOMP
BK26
SM_RCOMP#
BK32
SM_RCOMP_VOH
BL31
SM_RCOMP_VOL
BC51
SM_VREF
AY37
SM_PWROK
BH20
SM_REXT
BA37
SM_DRAMRST#
B42
DPLL_REF_CLK
D42
DPLL_REF_CLK#
B50
DPLL_REF_SSCLK
D50
DPLL_REF_SSCLK#
R49
PEG_CLK
P50
PEG_CLK#
AG55
DMI_RXN_0
AL49
DMI_RXN_1
AH54
DMI_RXN_2
AL47
DMI_RXN_3
AG53
DMI_RXP_0
AK50
DMI_RXP_1
AH52
DMI_RXP_2
AL45
DMI_RXP_3
AG49
DMI_TXN_0
AJ49
DMI_TXN_1
AJ47
DMI_TXN_2
AG47
DMI_TXN_3
AF50
DMI_TXP_0
AH50
DMI_TXP_1
AJ45
DMI_TXP_2
AG45
DMI_TXP_3
G33
GFX_VID_0
G37
GFX_VID_1
F38
GFX_VID_2
F36
GFX_VID_3
G35
GFX_VID_4
G39
GFX_VR_EN
AK52
CL_CLK
AK54
CL_DATA
AW40
CL_PWROK
AL53
CL_RST#
AL55
CL_VREF
F34
DDPC_CTRLCLK
F32
DDPC_CTRLDATA
B38
SDVO_CTRLCLK
A37
SDVO_CTRLDATA
C31
CLKREQ#
K42
ICH_SYNC#
D10
TSATN#
C29
HDA_BCLK
B30
HDA_RST#
D28
HDA_SDI
A27
HDA_SDO
B28
HDA_SYNC
CANTIGA GMCH SFF_QR46 B0_FCBGA1363~D
2
TP_MCH_RSVD1
J43
RSVD1
RSVD2
RSVD3
RSVD4
RSVD5
RSVD6
RSVD7
RSVD8
RSVD9
RSVD14
RSVD15
RSVD17
RSVD20
RSVD22
RSVD23
RSVD24
RSVD25
ME_JTAG_TCK
ME_JTAG_TDI
ME_JTAG_TDO
ME_JTAG_TMS
L43
J41
L41
AN11
AM10
AK10
AL11
F12
C27
D30
J9
AW42
BB20
BE19
BF20
BF18
AN45
AP44
AT44
AN47
TP_MCH_RSVD2
TP_MCH_RSVD3
TP_MCH_RSVD4
TP_MCH_RSVD5
TP_MCH_RSVD6
TP_MCH_RSVD7
TP_MCH_RSVD8
TP_MCH_RSVD9
TP_MCH_RSVD14
TP_MCH_RSVD15
TP_MCH_RSVD17
TP_MCH_RSVD20
TP_MCH_RSVD22
TP_MCH_RSVD23
TP_MCH_RSVD24
TP_MCH_RSVD25
ME_JTAG_TCK
ME_JTAG_TDI
ME_JTAG_TDO
ME_JTAG_TMS
DDR CLK/ CONTROL/COMPENSATION
CLK
CFGRSVD
DMI
PM_SYNC#
PM_DPRSTP#
PM
PM_EXT_TS#_0
PM_EXT_TS#_1
THERMTRIP#
GRAPHICS VID
DPRSLPVR
ME
NC
MISC
CFG_0
CFG_1
CFG_2
CFG_3
CFG_4
CFG_5
CFG_6
CFG_7
CFG_8
CFG_9
CFG_10
CFG_11
CFG_12
CFG_13
CFG_14
CFG_15
CFG_16
CFG_17
CFG_18
CFG_19
CFG_20
PWROK
RSTIN#
NC_1
NC_2
NC_3
NC_4
NC_5
NC_6
NC_7
NC_8
NC_9
NC_10
NC_11
NC_12
NC_13
NC_14
NC_15
NC_16
NC_17
NC_18
NC_19
NC_20
NC_21
NC_22
K26
G23
G25
J25
L25
L27
F24
D24
D26
J23
B26
A23
C23
B24
B22
K24
C25
L23
L33
K32
K34
J35
F6
J39
L39
AY39
BB18
K28
K36
A7
A49
A52
A54
B54
D55
G55
BE55
BH55
BK55
BK54
BL54
BL52
BL49
BL7
BL4
BL2
BK2
BK1
BH1
BE1
G1
CPU_MCH_BSEL0 <6,8>
CPU_MCH_BSEL1 <6,8>
CPU_MCH_BSEL2 <6,8>
T30
T31
T90
T91
T92
T32
T93
T33
T34
T35
T36
T37
T38
T94
T39
T40
T95
T96
PM_SYNC#
H_DPRSTP#
PM_EXTTS#
RESET_OUT
PLTRST1#_R
THERMTRIP_MCH#
DPRSLPVR
HDA
DELL CONFIDEN TIAL/PROPRIETARY
Title
Size Docum e n t N u m b e r Re v
LA-4291P
2
Date: Sheet
1
T4
T5
T7
T8
T9
T10
T11
T13
T14
T16
T17
T18
T20
T22
T23
T24
T25
R84 100_0402_5%~D@
1 2
R85 100_0402_5%~D@
1 2
R86 100_0402_5%~D@
1 2
R88 100_0402_5%~D@
1 2
+3.3V_RUN
R91
PM_EXTTS#
PLTRST1#_R
THERMTRIP_MCH#
SMRCOMP_VOH
SMRCOMP_VOL
12
10K_0402_5%~D
R114
12
100_0402_5%~D
R116
1 2
56_0402_5%~D
PM_SYNC# <24>
H_DPRSTP# <8,23,43>
PM_EXTTS# <18,19>
RESET_OUT <24,34>
THERMTRIP_MCH# <19>
DPRSLPVR <24,43>
+1.5V_MEM
0.01U_0402_16V7K~D
2.2U_0603_6.3V6K~D
1
1
C36
C37
2
2
0.01U_0402_16V7K~D
2.2U_0603_6.3V6K~D
1
1
C38
C39
2
2
+1.05V_VCCP
R104
R113
Compal Electro nics, Inc.
Cantiga GS(1/6)
1
PLTRST1# <22,35>
12
R98
1K_0402_1%~D
3.01K_0402_1%~D
12
1K_0402_1%~D
12
10 49Friday, December 07, 2007
of
0.1
Page 11
5
D D
4
3
2
1
DDR_A_BS0<16,17>
DDR_A_BS1<16,17>
DDR_A_BS2<16,17>
DDR_A_RAS#<16,17>
DDR_A_CAS#<16,17>
DDR_A_WE#<16,17>
DDR_A_DM[0..7]<16,17>
DDR_A_DQS[0..7]<16,17>
C C
DDR_A_DQS#[0..7]<16,17>
DDR_A_MA[0..13]<16,17>
B B
DDR_A_BS0
DDR_A_BS1
DDR_A_BS2
DDR_A_RAS#
DDR_A_CAS#
DDR_A_DM0 DDR_A_D11
DDR_A_DM1
DDR_A_DM2
DDR_A_DM3
DDR_A_DM4
DDR_A_DM5
DDR_A_DM6
DDR_A_DM7
DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7
DDR_A_DQS#0
DDR_A_DQS#1
DDR_A_DQS#2
DDR_A_DQS#3
DDR_A_DQS#4
DDR_A_DQS#5
DDR_A_DQS#6
DDR_A_DQS#7
DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA14_R
U78D
BC21
SA_BS_0
BJ21
SA_BS_1
BJ41
SA_BS_2
BH22
SA_RAS#
BK20
SA_CAS#
BL15
SA_WE#
AT50
SA_DM_0
BB50
SA_DM_1
BB46
SA_DM_2
BE39
SA_DM_3
BB12
SA_DM_4
BE7
SA_DM_5
AV10
SA_DM_6
AR9
SA_DM_7
AR47
SA_DQS_0
BA45
SA_DQS_1
BE45
SA_DQS_2
BC41
SA_DQS_3
BC13
SA_DQS_4
BB10
SA_DQS_5
BA7
SA_DQS_6
AN7
SA_DQS_7
AR49
SA_DQS#_0
AW45
SA_DQS#_1
BC45
SA_DQS#_2
BA41
SA_DQS#_3
BA13
SA_DQS#_4
BA11
SA_DQS#_5
BA9
SA_DQS#_6
AN9
SA_DQS#_7
BC23
SA_MA_0
BF22
SA_MA_1
BE31
SA_MA_2
BC31
SA_MA_3
BH26
SA_MA_4
BJ35
SA_MA_5
BB34
SA_MA_6
BH32
SA_MA_7
BB26
SA_MA_8
BF32
SA_MA_9
BA21
SA_MA_10
BG25
SA_MA_11
BH34
SA_MA_12
BH18
SA_MA_13
BE25
SA_MA_14
CANTIGA GMCH SFF_QR46 B0_FCBGA1363~D
DDR SYSTEM MEMORY A
SA_DQ_0
SA_DQ_1
SA_DQ_2
SA_DQ_3
SA_DQ_4
SA_DQ_5
SA_DQ_6
SA_DQ_7
SA_DQ_8
SA_DQ_9
SA_DQ_10
SA_DQ_11
SA_DQ_12
SA_DQ_13
SA_DQ_14
SA_DQ_15
SA_DQ_16
SA_DQ_17
SA_DQ_18
SA_DQ_19
SA_DQ_20
SA_DQ_21
SA_DQ_22
SA_DQ_23
SA_DQ_24
SA_DQ_25
SA_DQ_26
SA_DQ_27
SA_DQ_28
SA_DQ_29
SA_DQ_30
SA_DQ_31
SA_DQ_32
SA_DQ_33
SA_DQ_34
SA_DQ_35
SA_DQ_36
SA_DQ_37
SA_DQ_38
SA_DQ_39
SA_DQ_40
SA_DQ_41
SA_DQ_42
SA_DQ_43
SA_DQ_44
SA_DQ_45
SA_DQ_46
SA_DQ_47
SA_DQ_48
SA_DQ_49
SA_DQ_50
SA_DQ_51
SA_DQ_52
SA_DQ_53
SA_DQ_54
SA_DQ_55
SA_DQ_56
SA_DQ_57
SA_DQ_58
SA_DQ_59
SA_DQ_60
SA_DQ_61
SA_DQ_62
SA_DQ_63
AP46
AU47
AT46
AU49
AR45
AN49
AV50
AP50
AW47
BD50
AW49
BA49
BC49
AV46
BA47
AY50
BF46
BC47
BF50
BF48
BC43
BE49
BA43
BE47
BF42
BC39
BF44
BF40
BB40
BE43
BF38
BE41
BA15
BE11
BE15
BF14
BB14
BC15
BE13
BF16
BF10
BC11
BF8
BG7
BC7
BC9
BD6
BF12
AV6
BB6
AW7
AY6
AT10
AW11
AU11
AW9
AR11
AT6
AP6
AL7
AR7
AT12
AM6
AU7
DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6DDR_A_WE#
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63
DDR_B_BS0<18>
DDR_B_BS1<18>
DDR_B_BS2<18>
DDR_B_RAS#<18>
DDR_B_CAS#<18>
DDR_B_WE#<18>
DDR_B_DM[0..7]<18>
DDR_B_DQS[0..7]<18>
DDR_B_DQS#[0..7]<18>
DDR_B_MA[0..14]<18>
DDR_B_BS0
DDR_B_BS1
DDR_B_BS2
DDR_B_RAS#
DDR_B_CAS#
DDR_B_WE#
DDR_B_DM0
DDR_B_DM1
DDR_B_DM2
DDR_B_DM3
DDR_B_DM4
DDR_B_DM5
DDR_B_DM6
DDR_B_DM7
DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4
DDR_B_DQS5
DDR_B_DQS6
DDR_B_DQS7
DDR_B_DQS#0
DDR_B_DQS#1
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS#4
DDR_B_DQS#5
DDR_B_DQS#6
DDR_B_DQS#7
DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13
DDR_B_MA14
U78E
BJ13
SB_BS_0
BK12
SB_BS_1
BK38
SB_BS_2
BE21
SB_RAS#
BH14
SB_CAS#
BK14
SB_WE#
AP52
SB_DM_0
AY54
SB_DM_1
BJ49
SB_DM_2
BJ43
SB_DM_3
BH12
SB_DM_4
BD2
SB_DM_5
AY2
SB_DM_6
AJ3
SB_DM_7
AR53
SB_DQS_0
BA53
SB_DQS_1
BH50
SB_DQS_2
BK42
SB_DQS_3
BH8
SB_DQS_4
BB2
SB_DQS_5
AV2
SB_DQS_6
AM2
SB_DQS_7
AT54
SB_DQS#_0
BB54
SB_DQS#_1
BJ51
SB_DQS#_2
BH42
SB_DQS#_3
BK8
SB_DQS#_4
BC3
SB_DQS#_5
AW3
SB_DQS#_6
AN3
SB_DQS#_7
BJ15
SB_MA_0
BJ33
SB_MA_1
BH24
SB_MA_2
BA17
SB_MA_3
BF36
SB_MA_4
BH36
SB_MA_5
BF34
SB_MA_6
BK34
SB_MA_7
BJ37
SB_MA_8
BH40
SB_MA_9
BH16
SB_MA_10
BK36
SB_MA_11
BH38
SB_MA_12
BJ11
SB_MA_13
BL37
SB_MA_14
CANTIGA GMCH SFF_QR46 B0_FCBGA1363~D
DDR SYSTEM MEMORY B
SB_DQ_0
SB_DQ_1
SB_DQ_2
SB_DQ_3
SB_DQ_4
SB_DQ_5
SB_DQ_6
SB_DQ_7
SB_DQ_8
SB_DQ_9
SB_DQ_10
SB_DQ_11
SB_DQ_12
SB_DQ_13
SB_DQ_14
SB_DQ_15
SB_DQ_16
SB_DQ_17
SB_DQ_18
SB_DQ_19
SB_DQ_20
SB_DQ_21
SB_DQ_22
SB_DQ_23
SB_DQ_24
SB_DQ_25
SB_DQ_26
SB_DQ_27
SB_DQ_28
SB_DQ_29
SB_DQ_30
SB_DQ_31
SB_DQ_32
SB_DQ_33
SB_DQ_34
SB_DQ_35
SB_DQ_36
SB_DQ_37
SB_DQ_38
SB_DQ_39
SB_DQ_40
SB_DQ_41
SB_DQ_42
SB_DQ_43
SB_DQ_44
SB_DQ_45
SB_DQ_46
SB_DQ_47
SB_DQ_48
SB_DQ_49
SB_DQ_50
SB_DQ_51
SB_DQ_52
SB_DQ_53
SB_DQ_54
SB_DQ_55
SB_DQ_56
SB_DQ_57
SB_DQ_58
SB_DQ_59
SB_DQ_60
SB_DQ_61
SB_DQ_62
SB_DQ_63
AP54
AM52
AR55
AV54
AM54
AN53
AT52
AU53
AW53
AY52
BB52
BC53
AV52
AW55
BD52
BC55
BF54
BE51
BH48
BK48
BE53
BH52
BK46
BJ47
BL45
BJ45
BL41
BH44
BH46
BK44
BK40
BJ39
BK10
BH10
BK6
BH6
BJ9
BL11
BG5
BJ5
BG3
BF4
BD4
BA3
BE5
BF2
BB4
AY4
BA1
AP2
AU1
AT2
AT4
AV4
AU3
AR3
AN1
AP4
AL3
AJ1
AK4
AM4
AH2
AK2
DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63
DDR_B_D[0..63] <18>DDR_A_D[0..63] <16,17>
Place close to U78, reserve for 2Gb on board RAMs
DDR_A_MA14_R DDR_A_MA14
A A
R793
1 2
0_0402_5%~D@
DDR_A_MA14 <16,17>
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
Cantiga GS(2/6)
LA-4291P
11 49Friday, Decemb er 07, 2007
1
0.1
of
Page 12
5
4
3
+VCC_PEG
2
1
D D
BIA_PWM<20>
PANEL_BKEN_MCH<33>
LDDC_CLK_MCH<20>
LDDC_DATA_MCH<20>
R120
1 2
2.37K_0402_1%~D
LCD_ACLK-_MCH<20>
LCD_ACLK+_MCH<20>
LCD_A0-_MCH<20>
LCD_A1-_MCH<20>
LCD_A2-_MCH<20>
LCD_A0+_MCH<20>
LCD_A1+_MCH<20>
LCD_A2+_MCH<20>
C C
B B
A A
Place close to U78
R140 100K_0402_5%~D
1 2
R135 150_0402_1%~D
1 2
1 2
1 2
R136 150_0402_1%~D
R139 150_0402_1%~D
ENVDD
CRT_BLU
CRT_GRN
CRT_RED
CRT_BLU<20>
CRT_GRN<20>
CRT_RED<20>
CRT_HSYNC<20>
1.02K_0402_1%~D
CRT_VSYNC<20>
ENVDD<20>
R126
1 2
30_0402_1%~D
R128
12
1 2
R130
30_0402_1%~D
BIA_PWM
PANEL_BKEN_MCH
LDDC_CLK_MCH
LDDC_DATA_MCH
ENVDD
L_IBG
LCD_ACLK-_MCH
LCD_ACLK+_MCH
LCD_A0-_MCH
LCD_A1-_MCH
LCD_A2-_MCH
LCD_A0+_MCH
LCD_A1+_MCH
LCD_A2+_MCH
CRT_BLU
CRT_GRN
CRT_RED
G_CLK_DDC2
G_DAT_DDC2
CRT_HSYNC_R
CRT_IREF
CRT_VSYNC_R
U78C
D38
L_BKLT_CTRL
C37
L_BKLT_EN
K38
L_CTRL_CLK
L37
L_CTRL_DATA
J37
L_DDC_CLK
L35
L_DDC_DATA
B36
L_VDD_EN
F50
LVDS_IBG
H46
LVDS_VBG
P44
LVDS_VREFH
K46
LVDS_VREFL
D46
LVDSA_CLK#
B46
LVDSA_CLK
D44
LVDSB_CLK#
B44
LVDSB_CLK
G45
LVDSA_DATA#_0
F46
LVDSA_DATA#_1
G41
LVDSA_DATA#_2
C45
LVDSA_DATA#_3
F44
LVDSA_DATA_0
G47
LVDSA_DATA_1
F40
LVDSA_DATA_2
A45
LVDSA_DATA_3
B40
LVDSB_DATA#_0
A41
LVDSB_DATA#_1
F42
LVDSB_DATA#_2
D48
LVDSB_DATA#_3
D40
LVDSB_DATA_0
C41
LVDSB_DATA_1
G43
LVDSB_DATA_2
B48
LVDSB_DATA_3
J27
TVA_DAC
E27
TVB_DAC
G27
TVC_DAC
F26
TVA_RTN
B34
TV_DCONSEL_0
D34
TV_DCONSEL_1
J29
CRT_BLUE
G29
CRT_GREEN
F30
CRT_RED
E29
CRT_IRTN
D36
CRT_DDC_CLK
C35
CRT_DDC_DATA
J33
CRT_HSYNC
D32
CRT_TVO_IREF
G31
CRT_VSYNC
CANTIGA GMCH SFF_QR46 B0_FCBGA1363~D
LVDS
TV
PEG_COMPI
PEG_COMPO
PEG_RX#_0
PEG_RX#_1
PEG_RX#_2
PEG_RX#_3
PEG_RX#_4
PEG_RX#_5
PEG_RX#_6
PEG_RX#_7
PEG_RX#_8
PEG_RX#_9
PEG_RX#_10
PEG_RX#_11
PEG_RX#_12
PEG_RX#_13
PEG_RX#_14
PEG_RX#_15
PEG_RX_0
PEG_RX_1
PEG_RX_2
PEG_RX_3
PEG_RX_4
PEG_RX_5
PEG_RX_6
PEG_RX_7
PEG_RX_8
PEG_RX_9
PEG_RX_10
PEG_RX_11
PEG_RX_12
PEG_RX_13
PEG_RX_14
PEG_RX_15
PEG_TX#_0
PEG_TX#_1
PEG_TX#_2
PEG_TX#_3
PEG_TX#_4
PEG_TX#_5
PEG_TX#_6
PEG_TX#_7
PEG_TX#_8
PEG_TX#_9
PEG_TX#_10
PEG_TX#_11
PCI-EXPRESS GRAPHICS
PEG_TX#_12
PEG_TX#_13
PEG_TX#_14
PEG_TX#_15
PEG_TX_0
PEG_TX_1
PEG_TX_2
VGA
PEG_TX_3
PEG_TX_4
PEG_TX_5
PEG_TX_6
PEG_TX_7
PEG_TX_8
PEG_TX_9
PEG_TX_10
PEG_TX_11
PEG_TX_12
PEG_TX_13
PEG_TX_14
PEG_TX_15
U45
T44
D52
G49
K54
H50
M52
N49
P54
V46
Y50
V52
W49
AB54
AD46
AC55
AE49
AF54
E51
F48
J55
J49
M54
M50
P52
U47
AA49
V54
V50
AB52
AC47
AC53
AD50
AF52
L47
F52
P46
H54
L55
T46
R53
U49
T54
Y46
AB46
W53
Y54
AC49
AF46
AD54
J47
F54
N47
H52
L53
R47
R55
T50
T52
W47
AA47
W55
Y52
AB50
AE47
AD52
PEGCOMP
R119
49.9_0402_1%~D
1 2
DPB_DOCK_AUX#
DPC_DOCK_AUX#
DPB_DOCK_AUX
DPB_DOCK_HPD#
DPC_DOCK_AUX
DPC_DOCK_HPD#
DPB_LANE_N0
DPB_LANE_N1
DPB_LANE_N2
DPB_LANE_N3
DPC_LANE_N0
DPC_LANE_N1
DPC_LANE_N2
DPC_LANE_N3
DPB_LANE_P0
DPB_LANE_P1
DPB_LANE_P2
DPB_LANE_P3
DPC_LANE_P0
DPC_LANE_P1
DPC_LANE_P2
DPC_LANE_P3
G_DAT_DDC2 DAT_DDC2
DPB_DOCK_AUX# <31>
DPC_DOCK_AUX# <31>
DPB_DOCK_AUX <31>
DPB_DOCK_HPD# <31>
DPC_DOCK_AUX <31>
DPC_DOCK_HPD# <31>
C40 0.1U_0402_10V7K~D
12
C41 0.1U_0402_10V7K~D
12
C42 0.1U_0402_10V7K~D
12
C43 0.1U_0402_10V7K~D
12
C44 0.1U_0402_10V7K~D
12
C45 0.1U_0402_10V7K~D
12
C46 0.1U_0402_10V7K~D
12
C47 0.1U_0402_10V7K~D
12
C48 0.1U_0402_10V7K~D
12
C49 0.1U_0402_10V7K~D
12
C50 0.1U_0402_10V7K~D
12
C51 0.1U_0402_10V7K~D
12
C52 0.1U_0402_10V7K~D
12
C53 0.1U_0402_10V7K~D
12
C54 0.1U_0402_10V7K~D
12
C55 0.1U_0402_10V7K~D
12
+3.3V_RUN
12
12
R1061
2.2K_0402_5%~D
R1062
2.2K_0402_5%~D
+3.3V_RUN
DPB_LANE_N0_C <31>
DPB_LANE_N1_C <31>
DPB_LANE_N2_C <31>
DPB_LANE_N3_C <31>
DPC_LANE_N0_C <31>
DPC_LANE_N1_C <31>
DPC_LANE_N2_C <31>
DPC_LANE_N3_C <31>
DPB_LANE_P0_C <31>
DPB_LANE_P1_C <31>
DPB_LANE_P2_C <31>
DPB_LANE_P3_C <31>
DPC_LANE_P0_C <31>
DPC_LANE_P1_C <31>
DPC_LANE_P2_C <31>
DPC_LANE_P3_C <31>
Q110A
2N7002DW-7-F_SOT363-6~D
2
Q110B
5
2N7002DW-7-F_SOT363-6~D
4
CLK_DDC2G_CLK_DDC2
61
3
CFG5 DMI X2 Select
iTPM Host
CFG6
Interface
Management
CFG7
Engine Crypto
Strap
PCI Express
CFG9
Graphic Lane
PCI Express
Lookpback
CFG10
enable
CFG12
ALLZ
CFG13
XOR
CFG16
FSB Dynamic
ODT
DMI Lane
CFG19
Reversal
SDVO/PCIE
CFG20
Concurrent
Operation
SDVO_CRTL_DATA
DDPC_CTRLDATA
CFG[5:16] have internal pullup
CLK_DDC2 <20>
DAT_DDC2 <20>
Strap Pin Table
Low = DMI x 2
High = DMI x 4 (Default)
Low = iTPM enable
High = iTPM disable(Defult)
Low = TLS cipher s u i t e wit h n o c onfidentiality
High = TLS cip h e r s u i t e with
confidentiality(Default)
Low = Reverse Lane
High = Normal O p e r a t i o n(Default)
Low = Enable
High = Disable ( d e f ault)
Low = ALLZ mode enable
High = Disable ( d e f ault)
Low = XOR mode enable
High = Disable ( d e f ault)
Low=Dynamic O D T Disable
High=Dynamic ODT Enable(default)
Low=Normal (default)
High=Lane Reversed
Low=Only SDVO or PCIEx1 is
operational (default)
High=SDVO and P C I E x 1 a r e o p e rating
simultaneously via PEG port
Low=No SDVO Device Present
(default)
High=SDVO Dev i ce Present
Low=DisplayPort disabled (default)
High=DisplayPort device present
CFG[19:20] have internal pulldown
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
Cantiga GS(3/6)
LA-4291P
12 49Friday, Decemb er 07, 2007
1
0.1
of
Page 13
5
4
3
2
1
+1.05V_VCCP
220U_D2_4VY_R15M~D
4.7U_0603_6.3V6M~D
1
1
+
C64
C65
2
+1.05V_M
1
2
2
+3.3V_RUN
1
C78
2
R147
0_1210_5%~D
PJP1
1 2
PAD-OPEN1x1m
C109
1
2
1000P_0402_50V7K~D
C114
1
2
C66
0.1U_0402_16V4Z~D
+3.3V_RUN
0.47U_0402_10V4Z~D
22U_0805_6.3V6M~D
+1.5V_RUN_QDAC+1.5V_RUN
1
C85
2
12
CRB 270uF
0.1U_0402_16V4Z~D
1
C84
2
+1.5V_SM_CK+1.5V_MEM
1_0603_5%~D
12
R150
1
C117
10U_0805_4VAM~D
2
220U_D2_4VY_R15M~D
1
+
C71
2
0.01U_0402_16V7K~D
C116
C73
1
2
1
2
0.1U_0402_16V4Z~D
+VCC_PEG
+VCC_PEG
22U_0805_6.3V6M~D
C72
+1.5V_RUN
4.7U_0603_6.3V6M~D
1
2
118.8mA Max.
C113
D D
L4
1 2
BLM18PG181SN1_0603~D
C C
L12
+1.05V_M
12
0_1210_5%~D
R141
5
1UH_LQM21FN1R0N00D_30%_0805~D
B B
A A
2.2U_0603_6.3V6K~D
1
C68
2
0.1U_0402_16V4Z~D
1
1
C77
2
2
+1.5V_RUN_QDAC
0.1U_0402_16V4Z~D
1
C81
2
10U_0805_6.3VAM~D@
1
1
C93
2
2
+1.5V_SM_CK
+VCC_TX_LVDS
+VCC_PEG
1
C102
0.1U_0402_16V4Z~D
2
GMCH_VTTLF1
GMCH_VTTLF2
GMCH_VTTLF3
0.47U_0402_10V4Z~D
C111
1
2
L10
1 2
0.47U_0402_10V4Z~D
1
2
0.01U_0402_16V7K~D
1
C82
2
+VCC_AXF
1U_0603_10V4Z~D
4.7U_0603_6.3V6M~D
1
C67
2
C76
+1.5V_RUN
12
C92
1
C101
0.1U_0402_16V4Z~D
2
+VCC_DMI
0.47U_0402_10V4Z~D
C110
1
2
100NH_HK1608R10J-T_5%_0603~D
U78H
R13
VTT_1
T12
VTT_2
R11
VTT_3
T10
VTT_4
R9
VTT_5
T8
VTT_6
R7
VTT_7
T6
VTT_8
R5
VTT_9
T4
VTT_10
R3
VTT_11
T2
VTT_12
R1
VTT_13
VTT
K30
VCCA_TV_DAC
A31
VCC_HDA
N34
VCCD_QDAC
N32
VCCD_TVDAC
0.01U_0402_16V7K~D
POWER
M25
VCC_AXF_1
N24
VCC_AXF_2
M23
VCC_AXF_3
BK24
VCC_SM_CK_1
BL23
VCC_SM_CK_2
BJ23
VCC_SM_CK_3
BK22
VCC_SM_CK_4
T41
VCC_TX_LVDS
C33
VCC_HV_1
A33
VCC_HV_2
AB44
VCC_PEG_1
Y44
VCC_PEG_2
AC43
VCC_PEG_3
AA43
VCC_PEG_4
AM44
VCC_DMI_1
AN43
VCC_DMI_2
AL43
VCC_DMI_3
K14
VTTLF1
Y12
VTTLF2
P2
VTTLF3
CANTIGA GMCH SFF_QR46 B0_FCBGA1363~D
+1.8V_LVDS
4
AXF
HV
PEG
VTTLF
PJP38
1 2
PAD-OPEN 4x4m
PJP39
1 2
PAD-OPEN 4x4m
TVD TV/CRT
HDA
SM CK
DMI
VCCA_CRT_DAC
CRTPLLA PEGA SM
A LVDS
VCCA_PEG_PLL
VCCA_SM_NCTF_1
VCCA_SM_NCTF_2
VCCA_SM_NCTF_3
VCCA_SM_NCTF_4
VCCA_SM_NCTF_5
VCCA_SM_NCTF_6
VCCA_SM_NCTF_7
VCCA_SM_NCTF_8
VCCA_SM_NCTF_9
VCCA_SM_NCTF_10
VCCA_SM_CK_4
VCCA_SM_CK_3
VCCA_SM_CK_2
VCCA_SM_CK_1
VCCA_SM_CK_NCTF_1
VCCA_SM_CK_NCTF_2
VCCA_SM_CK_NCTF_3
VCCA_SM_CK_NCTF_4
VCCA_SM_CK_NCTF_5
VCCA_SM_CK_NCTF_6
VCCA_SM_CK_NCTF_7
VCCA_SM_CK_NCTF_8
VCCD_PEG_PLL
LVDS
+1.8V_RUN+VCC_TX_LVDS
+1.8V_RUN_LVDS
VCCA_DAC_BG
VSSA_DAC_BG
VCCA_DPLLA
VCCA_DPLLB
VCCA_HPLL
VCCA_MPLL
VCCA_LVDS1
VCCA_LVDS2
VSSA_LVDS
VCCA_PEG_BG
VCCA_SM_1
VCCA_SM_2
VCCA_SM_3
VCCA_SM_4
VCCA_SM_5
VCCA_SM_6
VCCA_SM_7
VCCA_SM_8
VCCA_SM_9
VCCA_SM_10
VCCA_SM_11
VCCA_SM_12
VCCA_SM_13
VCCA_SM_14
VCCA_SM_15
VCCA_SM_16
VCCA_SM_17
VCCD_HPLL
VCCD_LVDS_1
VCCD_LVDS_2
+3.3V_CRT_DAC
J31
L31
M33
J45
+1.05V_M_DPLLA
L49
+1.05V_M_DPLLB
AF10
+1.05V_M_HPLL
AE1
+1.05V_M_MPLL
+VCC_TX_LVDS
U43
U41
V44
VCCA_PEG_BG
AJ43
AG43
+1.05V_M_PEGPLL
AW24
AU24
AW22
AU22
AU21
AW20
AU19
AW18
AU18
AW16
AU16
AT16
AR16
AU15
AT15
AR15
AW14
AT24
AR24
AT22
AR22
AT21
AR21
AT19
AR19
AT18
AR18
AU27
AU28
AU29
AU31
AT31
AR31
AT29
AR29
AT28
AR28
AT27
AR27
AH12
AE43
M46
L45
C112
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
1U_0603_10V4Z~D
1
2
3
C88
C97
+1.8V_LVDS
1
C74
2
1
2
+1.05V_M_A_SM
1U_0603_10V4Z~D
1
1
C89
2
2
+1.05V_M_SM_CK
0.1U_0402_16V4Z~D
1
1
C99
2
2
+1.05V_M_PEGPLL
0.1U_0402_16V4Z~D
C108
1
2
+3.3V_CRT_DAC
0.01U_0402_16V7K~D
0.1U_0402_16V4Z~D
1
C75
2
R143
1 2
0_0402_5%~D
C80
0.1U_0402_16V4Z~D
4.7U_0603_6.3V6M~D
22U_0805_6.3V6M~D
1
C90
C91
2
22U_0805_6.3V6M~D
2.2U_0603_6.3V6K~D@
1
C98
2
C69
22U_0805_6.3V6M~D@
1
2
R149
1 2
0_1210_5%~D
4.7UH_LQM18FN4R7M00D_20%_0603~D
0.1U_0402_16V4Z~D
0.01U_0402_16V7K~D
1
1
C70
2
2
+VCC_TX_LVDS
1
C79
+1.05V_M
0.1U_0402_16V4Z~D
2
+1.05V_M
1
+
C87
2
+1.05V_M_PEGPLL
C86
+1.5V_RUN
R146
1 2
0_0805_5%~D
+1.05V_M
C107
1
2
1000P_0402_50V7K~D
100U_D_6.3VM_R15M~D
1
2
L3
12
BLM21PG221SN1D_0805~D
0.1U_0402_16V4Z~D
12
R145
1_0402_5%~D
1
C83
10U_0805_4VAM~D
2
2
+3.3V_RUN
L5
64.8mA Max.
+1.05V_M_DPLLA
C105
1
2
64.8mA Max.
+1.05V_M_DPLLB
C106
1
2
24mA Max.
+1.05V_M_HPLL
1
C94
2
10UH_LB2012T100MR_20%_0805~D
0.1U_0402_16V4Z~D
220U_D2_4VY_R15M~D
1
C103
+
2
10UH_LB2012T100MR_20%_0805~D
220U_D2_4VY_R15M~D
0.1U_0402_16V4Z~D
1
C104
+
2
BLM18AG121SN1D_0603~D
4.7U_0603_6.3V6M~D
0.1U_0402_16V4Z~D
1
C95
2
L8
12
L9
12
+1.05V_M
L6
12
139.2mA Max.
12
+1.05V_M
+1.05V_M_MPLL
0.1U_0402_16V4Z~D
1
C96
2
0.15UH_LQH32CNR15M33L_20%_1210~D
R148
0_0603_5%~D
1 2
1
C100
22U_0805_6.3VAM~D
2
L7
12
DELL CONFIDENTIAL/PROPRIETARY
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
Cantiga GS(4/6)
LA-4291P
1
+1.05V_M
+1.05V_M
+1.05V_M
13 49Friday, Decemb er 07, 2007
0.1
of
Page 14
5
U78F
D D
Layout Note:
Place close to U78
1
C124
+
2
CRB 270uF
C C
B B
A A
220U_D2_4VY_R15M~D
Layout Note:
Inside GMCH cavity
C125
1
2
C133
1
2
22U_0805_6.3V6M~D
C126
0.22U_0402_10V4Z~D
C134
1 2
0_0402_5%~D
1
2
1
2
R763
0.22U_0402_10V4Z~D
0.1U_0402_10V7K~D
+1.05V_M
AT41
VCC_1
AR41
VCC_2
AN41
VCC_3
AJ41
VCC_4
AH41
VCC_5
AD41
VCC_6
AC41
VCC_7
Y41
VCC_8
W41
VCC_9
AT40
VCC_10
AM40
VCC_11
AL40
VCC_12
AJ40
VCC_13
AH40
VCC_14
AG40
VCC_15
AE40
VCC_16
AD40
VCC_17
AC40
VCC_18
AA40
VCC_19
Y40
VCC_20
AN35
VCC_21
AM35
VCC_22
AJ35
VCC_23
AH35
VCC_24
AD35
VCC_25
AC35
VCC_26
W35
VCC_27
AM34
VCC_28
AL34
VCC_29
AJ34
VCC_30
AH34
VCC_31
AG34
VCC_32
AE34
VCC_33
AD34
VCC_34
AC34
VCC_35
AA34
VCC_36
Y34
VCC_37
W34
VCC_38
AM32
VCC_39
AL32
VCC_40
AJ32
VCC_41
AH32
VCC_42
AE32
VCC_43
AD32
VCC_44
AA32
VCC_45
AM31
VCC_46
AL31
VCC_47
AJ31
VCC_48
AH31
VCC_49
AM29
VCC_50
AL29
VCC_51
AM28
VCC_52
AL28
VCC_53
AJ28
VCC_54
AM27
VCC_55
AL27
VCC_56
AM25
VCC_57
AL25
VCC_58
AJ25
VCC_59
AM24
VCC_60
N36
VCC_61
CANTIGA GMCH SFF_QR46 B0_FCBGA1363~D
4
VCC CORE
POWER
VCC NCTF
VCC_NCTF_1
VCC_NCTF_2
VCC_NCTF_3
VCC_NCTF_4
VCC_NCTF_5
VCC_NCTF_6
VCC_NCTF_7
VCC_NCTF_8
VCC_NCTF_9
VCC_NCTF_10
VCC_NCTF_11
VCC_NCTF_12
VCC_NCTF_13
VCC_NCTF_14
VCC_NCTF_15
VCC_NCTF_16
VCC_NCTF_17
VCC_NCTF_18
VCC_NCTF_19
VCC_NCTF_20
VCC_NCTF_21
VCC_NCTF_22
VCC_NCTF_23
VCC_NCTF_24
VCC_NCTF_25
VCC_NCTF_26
VCC_NCTF_27
VCC_NCTF_28
VCC_NCTF_29
VCC_NCTF_30
VCC_NCTF_31
VCC_NCTF_32
VCC_NCTF_33
VCC_NCTF_34
VCC_NCTF_35
VCC_NCTF_36
VCC_NCTF_37
VCC_NCTF_38
+1.5V_MEM
330U_D2_2.5VY_R15M
0.1U_0402_10V7K~D
1
C118
C121
2
+
2
1
Place close to GMCH Place on the edge
+1.05V_M
AT38
AR38
AN38
AM38
AL38
AG38
AE38
AA38
Y38
W38
U38
T38
R38
AT37
AR37
AN37
AM37
AL37
AJ37
AH37
AG37
AE37
AD37
AC37
AA37
Y37
W37
U37
T37
R37
AT35
AR35
U35
AT34
AR34
U34
T34
R34
C122
3
U78G
+VCC_SM_BB36
+VCC_SM_BE35
0.1U_0402_10V7K~D
2
1
22U_0805_6.3V6M~D
2
1
C756
C757
0.1U_0402_10V7K~D
C760
0.1U_0402_10V7K~D
2
1
+VCC_SM_BC29
0.1U_0402_10V7K~D
2
1
+VCC_SM_BF24
+VCC_SM_BL19
+VCC_SM_BB16
0.1U_0402_10V7K~D
2
1
VCC_AXG_SENSE
VSS_AXG_SENSE
+VCC_GFXCORE
C755
22U_0805_6.3V6M~D
C123
1
1
2
2
0.1U_0402_10V7K~D
C759
C758
2
1
VCC_AXG_SENSE<44>
VSS_AXG_SENSE<44>
BB36
BE35
AW34
AW32
BK30
BH30
BF30
BD30
BB30
AW30
BL29
BJ29
BG29
BE29
BC29
BA29
AY29
BK28
BH28
BF28
BD28
BB28
BL27
BJ27
BG27
BE27
BC27
BA27
AY27
AW26
BF24
BL19
BB16
W32
AG31
AE31
AD31
AC31
AA31
W31
AH29
AG29
AE29
AD29
AC29
AA29
W29
AH28
AG28
AE28
AA28
AH27
AG27
AE27
AD27
AC27
AA27
W27
AH25
AD25
AC25
W25
AJ24
AH24
AG24
AE24
AD24
AC24
AA24
W24
AM22
AL22
AJ22
AH22
AG22
AE22
AD22
AC22
AA22
AM21
AL21
AJ21
AH21
AD21
AC21
AA21
W21
AM16
AL16
AG13
AE13
Y31
Y29
Y27
Y24
Y21
VCC_SM_1
VCC_SM_2
VCC_SM_3
VCC_SM_4
VCC_SM_5
VCC_SM_6
VCC_SM_7
VCC_SM_8
VCC_SM_9
VCC_SM_10
VCC_SM_11
VCC_SM_12
VCC_SM_13
VCC_SM_14
VCC_SM_15
VCC_SM_16
VCC_SM_17
VCC_SM_18
VCC_SM_19
VCC_SM_20
VCC_SM_21
VCC_SM_22
VCC_SM_23
VCC_SM_24
VCC_SM_25
VCC_SM_26
VCC_SM_27
VCC_SM_28
VCC_SM_29
VCC_SM_30
VCC_SM_31
VCC_SM_32
VCC_SM_33
VCC_AXG_1
VCC_AXG_2
VCC_AXG_3
VCC_AXG_4
VCC_AXG_5
VCC_AXG_6
VCC_AXG_7
VCC_AXG_8
VCC_AXG_9
VCC_AXG_10
VCC_AXG_11
VCC_AXG_12
VCC_AXG_13
VCC_AXG_14
VCC_AXG_15
VCC_AXG_16
VCC_AXG_17
VCC_AXG_18
VCC_AXG_19
VCC_AXG_20
VCC_AXG_21
VCC_AXG_22
VCC_AXG_23
VCC_AXG_24
VCC_AXG_25
VCC_AXG_26
VCC_AXG_27
VCC_AXG_28
VCC_AXG_29
VCC_AXG_30
VCC_AXG_31
VCC_AXG_32
VCC_AXG_33
VCC_AXG_34
VCC_AXG_35
VCC_AXG_36
VCC_AXG_37
VCC_AXG_38
VCC_AXG_39
VCC_AXG_40
VCC_AXG_41
VCC_AXG_42
VCC_AXG_43
VCC_AXG_44
VCC_AXG_45
VCC_AXG_46
VCC_AXG_47
VCC_AXG_48
VCC_AXG_49
VCC_AXG_50
VCC_AXG_51
VCC_AXG_52
VCC_AXG_53
VCC_AXG_54
VCC_AXG_55
VCC_AXG_56
VCC_AXG_57
VCC_AXG_58
VCC_AXG_59
VCC_AXG_60
VCC_AXG_61
VCC_AXG_SENSE
VSS_AXG_SENSE
2
POWER
VCC SMVCC GFX
VCC GFX NCTF
VCC GFX
VCC_AXG_NCTF_1
VCC_AXG_NCTF_2
VCC_AXG_NCTF_3
VCC_AXG_NCTF_4
VCC_AXG_NCTF_5
VCC_AXG_NCTF_6
VCC_AXG_NCTF_7
VCC_AXG_NCTF_8
VCC_AXG_NCTF_9
VCC_AXG_NCTF_10
VCC_AXG_NCTF_11
VCC_AXG_NCTF_12
VCC_AXG_NCTF_13
VCC_AXG_NCTF_14
VCC_AXG_NCTF_15
VCC_AXG_NCTF_16
VCC_AXG_NCTF_17
VCC_AXG_NCTF_18
VCC_AXG_NCTF_19
VCC_AXG_NCTF_20
VCC_AXG_NCTF_21
VCC_AXG_NCTF_22
VCC_AXG_NCTF_23
VCC_AXG_NCTF_24
VCC_AXG_NCTF_25
VCC_AXG_NCTF_26
VCC_AXG_NCTF_27
VCC_AXG_NCTF_28
VCC_AXG_NCTF_29
VCC_AXG_NCTF_30
VCC_AXG_NCTF_31
VCC_AXG_NCTF_32
VCC_AXG_NCTF_33
VCC_AXG_NCTF_34
VCC_AXG_NCTF_35
VCC_AXG_NCTF_36
VCC_AXG_NCTF_37
VCC_AXG_NCTF_38
VCC_AXG_NCTF_39
VCC_AXG_NCTF_40
VCC_AXG_NCTF_41
VCC_AXG_NCTF_42
VCC_AXG_NCTF_43
VCC_AXG_NCTF_44
VCC_AXG_62
VCC_AXG_63
VCC_AXG_64
VCC_AXG_65
VCC_AXG_66
VCC_AXG_67
VCC_AXG_68
VCC_AXG_69
VCC_AXG_70
VCC_AXG_71
VCC_AXG_72
VCC_AXG_73
VCC_AXG_74
VCC_AXG_75
VCC_AXG_76
VCC_AXG_77
VCC_AXG_78
VCC_AXG_79
VCC_AXG_80
VCC_SM_LF1
VCC_SM_LF2
VCC_SM_LF3
VCC_SM_LF4
VCC_SM_LF5
VCC_SM_LF6
VCC_SM_LF7
VCC SM LF
+VCC_GFXCORE
T32
U31
T31
R31
U29
T29
R29
U28
U27
T27
R27
U25
T25
R25
U24
U22
T22
R22
U21
T21
R21
AM19
AL19
AH19
AG19
AE19
AD19
AC19
W19
U19
AM18
AL18
AJ18
AH18
AG18
AE18
AD18
AC18
AA18
Y18
W18
U18
T18
R18
AJ16
AH16
AD16
AC16
AA16
U16
T16
R16
AM15
AL15
AJ15
AH15
AG15
AE15
AA15
Y15
W15
U15
T15
VCCSM_LF1
AU45
VCCSM_LF2
BF52
VCCSM_LF3
BB38
VCCSM_LF4
BA19
VCCSM_LF5
BE9
VCCSM_LF6
AU9
VCCSM_LF7
AL9
Cavity Ca pacitors
0.1U_0402_10V7K~D
C129
C130
1
1
2
2
0.1U_0402_10V7K~D
C135
0.1U_0402_10V7K~D
C136
1
1
2
2
0.1U_0402_10V7K~D
C137
C127
1
1U_0603_10V4Z~D
0.47U_0402_10V4Z~D
C128
C131
1
1
2
2
0.22U_0402_10V4Z~D
0.22U_0402_10V4Z~D
C139
C138
1
1
2
2
22U_0805_6.3V6M~D
10U_0805_6.3VAM~D
C132
1
1
2
2
0.47U_0402_10V4Z~D
C140
1
2
1U_0402_6.3V4Z~D
1U_0402_6.3V4Z~D
C141
1
1
2
2
CANTIGA GMCH SFF_QR46 B0_FCBGA1363~D
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
DELL CONFIDENTIAL/PROPRIETARY
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
Cantiga GS(5/6)
LA-4291P
14 49Friday, Decemb er 07, 2007
1
of
0.1
Page 15
5
4
3
2
1
U78I
BA55
VSS_1
AU55
VSS_2
AN55
VSS_3
AJ55
VSS_4
AE55
VSS_5
AA55
VSS_6
U55
VSS_7
N55
VSS_8
BD54
VSS_9
BG53
D D
C C
B B
A A
VSS_10
AJ53
VSS_11
AE53
VSS_12
AA53
VSS_13
U53
VSS_14
N53
VSS_15
J53
VSS_16
G53
VSS_17
E53
VSS_18
K52
VSS_19
BG51
VSS_20
BA51
VSS_21
AW51
VSS_22
AU51
VSS_23
AR51
VSS_24
AN51
VSS_25
AL51
VSS_26
AJ51
VSS_27
AG51
VSS_28
AE51
VSS_29
AC51
VSS_30
AA51
VSS_31
W51
VSS_32
U51
VSS_33
R51
VSS_34
N51
VSS_35
L51
VSS_36
J51
VSS_37
G51
VSS_38
C51
VSS_39
BK50
VSS_40
AM50
VSS_41
K50
VSS_42
BG49
VSS_43
E49
VSS_44
C49
VSS_45
BD48
VSS_46
BB48
VSS_47
AY48
VSS_48
AV48
VSS_49
AT48
VSS_50
AP48
VSS_51
AM48
VSS_52
AK48
VSS_53
AH48
VSS_54
AF48
VSS_55
AD48
VSS_56
AB48
VSS_57
Y48
VSS_58
V48
VSS_59
T48
VSS_60
P48
VSS_61
M48
VSS_62
K48
VSS_63
H48
VSS_64
BL47
VSS_65
BG47
VSS_66
E47
VSS_67
C47
VSS_68
A47
VSS_69
BD46
VSS_70
AY46
VSS_71
AM46
VSS_72
AK46
VSS_73
AH46
VSS_74
BG45
VSS_75
AE45
VSS_76
AC45
VSS_77
AA45
VSS_78
W45
VSS_79
R45
VSS_80
N45
VSS_81
E45
VSS_82
BD44
VSS_83
BB44
VSS_84
AV44
VSS_85
AK44
VSS_86
AH44
VSS_87
AF44
VSS_88
AD44
VSS_89
K44
VSS_90
H44
VSS_91
BL43
VSS_92
BG43
VSS_93
AY43
VSS_94
AR43
VSS_95
W43
VSS_96
R43
VSS_97
M43
VSS_98
E43
VSS_99
CANTIGA GMCH SFF_QR46 B0_FCBGA1363~D
VSS
VSS_100
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105
VSS_106
VSS_107
VSS_108
VSS_109
VSS_110
VSS_111
VSS_112
VSS_113
VSS_114
VSS_115
VSS_116
VSS_117
VSS_118
VSS_119
VSS_120
VSS_121
VSS_122
VSS_123
VSS_124
VSS_125
VSS_126
VSS_127
VSS_128
VSS_129
VSS_130
VSS_131
VSS_132
VSS_133
VSS_134
VSS_135
VSS_136
VSS_137
VSS_138
VSS_139
VSS_140
VSS_141
VSS_142
VSS_143
VSS_144
VSS_145
VSS_146
VSS_147
VSS_148
VSS_149
VSS_150
VSS_151
VSS_152
VSS_153
VSS_154
VSS_155
VSS_156
VSS_157
VSS_158
VSS_159
VSS_160
VSS_161
VSS_162
VSS_163
VSS_164
VSS_165
VSS_166
VSS_167
VSS_168
VSS_169
VSS_170
VSS_171
VSS_172
VSS_173
VSS_174
VSS_175
VSS_176
VSS_177
VSS_178
VSS_179
VSS_180
VSS_181
VSS_182
VSS_183
VSS_184
VSS_185
VSS_186
VSS_187
VSS_188
VSS_189
VSS_190
VSS_191
VSS_192
VSS_193
VSS_194
VSS_195
VSS_196
VSS_197
VSS_198
C43
A43
BD42
H42
BG41
AY41
AU41
AM41
AL41
AG41
AE41
AA41
R41
M41
E41
BD40
AU40
AR40
AN40
W40
U40
T40
R40
K40
H40
BL39
BG39
BA39
E39
C39
A39
BD38
AU38
H38
BG37
AU37
M37
E37
BD36
AW36
H36
BL35
BG35
AY35
AU35
AL35
AG35
AE35
AA35
Y35
M35
E35
A35
BD34
AU34
AN34
H34
BL33
BG33
AY33
E33
BD32
AU32
AN32
AG32
AC32
Y32
H32
B32
BJ31
BG31
AY31
AN31
M31
E31
N30
H30
AN29
AJ29
M29
A29
AW28
AN28
AD28
AC28
Y28
W28
H28
F28
AN27
AJ27
M27
BF26
BD26
N26
H26
BJ25
AY25
AU25
U78J
AN25
VSS_199
AG25
VSS_200
AE25
VSS_201
AA25
VSS_202
Y25
VSS_203
E25
VSS_204
A25
VSS_205
BD24
VSS_206
AN24
VSS_207
AL24
VSS_208
H24
VSS_209
BG23
VSS_210
AY23
VSS_211
E23
VSS_212
BD22
VSS_213
BB22
VSS_214
AN22
VSS_215
Y22
VSS_216
W22
VSS_217
H22
VSS_218
BL21
VSS_219
BG21
VSS_220
AY21
VSS_221
AN21
VSS_222
AG21
VSS_223
AE21
VSS_224
M21
VSS_225
E21
VSS_226
A21
VSS_227
BD20
VSS_228
H20
VSS_229
BG19
AY19
M19
BD18
N18
H18
BL17
BG17
AY17
M17
BD16
AN16
AG16
AE16
W16
N16
H16
BG15
AY15
AN15
AD15
AC15
R15
M15
BD14
H14
BL13
BG13
AY13
AU13
AR13
AJ13
AC13
AA13
W13
U13
M13
BD12
AV12
AP12
AM12
AK12
AB12
H12
BG11
AG11
BD10
AY10
AP10
H10
BG9
BD8
BB8
AY8
AV8
AT8
AP8
E19
E17
A17
Y16
E15
E13
A13
V12
P12
E11
BL9
E9
A9
VSS
VSS_230
VSS_231
VSS_232
VSS_233
VSS_234
VSS_235
VSS_236
VSS_237
VSS_238
VSS_239
VSS_240
VSS_241
VSS_242
VSS_243
VSS_244
VSS_245
VSS_246
VSS_247
VSS_248
VSS_249
VSS_250
VSS_251
VSS_252
VSS_253
VSS_254
VSS_255
VSS_256
VSS_257
VSS_258
VSS_259
VSS_260
VSS_261
VSS_262
VSS_263
VSS_264
VSS_265
VSS_266
VSS_267
VSS_268
VSS_269
VSS_270
VSS_271
VSS_272
VSS_273
VSS_274
VSS_275
VSS_276
VSS_277
VSS_278
VSS_279
VSS_280
VSS_281
VSS_282
VSS_283
VSS_284
VSS_285
VSS_286
VSS_287
VSS_288
VSS_289
VSS_290
VSS_291
VSS_292
VSS_293
VSS_294
VSS_295
VSS_296
VSS_297
VSS_298
VSS_299
CANTIGA GMCH SFF_QR46 B0_FCBGA1363~D
VSS_NCTF_10
VSS_NCTF_11
VSS_NCTF_12
VSS_NCTF_13
VSS NCTF
VSS_NCTF_14
VSS_NCTF_15
VSS_NCTF_16
VSS_NCTF_17
VSS_NCTF_18
VSS_NCTF_19
VSS_NCTF_20
VSS_NCTF_21
VSS_NCTF_22
VSS_NCTF_23
VSS SCB
VSS_300
VSS_301
VSS_302
VSS_303
VSS_304
VSS_305
VSS_306
VSS_307
VSS_308
VSS_309
VSS_310
VSS_311
VSS_312
VSS_313
VSS_314
VSS_315
VSS_316
VSS_317
VSS_318
VSS_319
VSS_320
VSS_321
VSS_322
VSS_323
VSS_324
VSS_325
VSS_326
VSS_327
VSS_328
VSS_329
VSS_330
VSS_331
VSS_332
VSS_333
VSS_334
VSS_335
VSS_336
VSS_337
VSS_338
VSS_339
VSS_340
VSS_341
VSS_342
VSS_343
VSS_344
VSS_345
VSS_346
VSS_347
VSS_348
VSS_349
VSS_350
VSS_351
VSS_352
VSS_353
VSS_354
VSS_355
VSS_356
VSS_357
VSS_358
VSS_359
VSS_360
VSS_361
VSS_362
VSS_NCTF_1
VSS_NCTF_2
VSS_NCTF_3
VSS_NCTF_4
VSS_NCTF_5
VSS_NCTF_6
VSS_NCTF_7
VSS_NCTF_8
VSS_NCTF_9
VSS_SCB_1
VSS_SCB_2
VSS_SCB_3
VSS_SCB_4
VSS_SCB_5
VSS_SCB_6
VSS_SCB_7
AM8
AK8
AH8
AF8
AD8
AB8
Y8
V8
P8
M8
K8
H8
BJ7
E7
BF6
BC5
BA5
AW5
AU5
AR5
AN5
AL5
AJ5
AG5
AE5
AC5
AA5
W5
U5
N5
L5
J5
G5
C5
BH4
BE3
U3
E3
BC1
AW1
AR1
AL1
AG1
AC1
W1
N1
J1
AU43
BB42
AW38
BA35
L29
N28
N22
N20
N14
AL13
B10
AN13
N42
N40
N38
M39
AJ38
AH38
AD38
AC38
T35
R35
AT32
AR32
U32
R32
T28
R28
AT25
AR25
T24
R24
AN19
AJ19
AA19
Y19
T19
R19
AN18
BL55
BL1
A55
D1
B55
B2
A4
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
Cantiga GS(6/6)
LA-4291P
15 49Friday, Decemb er 07, 2007
1
0.1
of
Page 16
5
4
3
2
1
U4
DDR_A_D1
DDR_A_D7
DDR_A_D0
DDR_A_D6
DDR_A_D4
DDR_A_D3
DDR_A_D5
DDR_A_D2
F4
DQS
G4
DQS#
E4
DQ0
F8
DQ1
F3
DQ2
F9
DQ3
H4
DQ4
H9
DQ5
G3
DQ6
H8
DQ7
D8
NU/TDQS#
E8
DM/TDQS
L9
ZQ
H2
VREFDQ
M9
VREFCA
N4
A0
P8
A1
P4
A2
N3
A3
P9
A4
P3
A5
R9
A6
R3
A7
T9
A8
R4
A9
L8
A10/AP
R8
A11
N8
A12/BC#
T4
A13
A1
NC
A2
NC
A4
NC
A8
NC
A10
NC
A11
NC
D1
NC
D4
NC
D11
NC
J2
NC
J10
NC
L2
NC
L10
NC
M8
NC
T1
NC
T8
NC
T11
NC
W1
NC
W2
NC
W4
NC
W8
NC
W10
NC
W11
NC
K4B1G0846C-ZCF7_FBGA94~D
DDR_A_DQS0<11> DDR_A_DQS2<11>
D D
1 2
R154 240_0402_5%~D
DDR_A_MA0
DDR_A_MA1 DDR_A_BS0
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5 DDR_CS#0
DDR_A_MA6
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
C C
DDR_A_MA14 DDR_A_MA14 DDR_A_MA14 DDR_A_MA14
VDDQ
VDDQ
VDDQ
VDDQ
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
ODT
CKE
RAS#
CAS#
WE#
RESET#
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
CK
CK#
BA0
BA1
BA2
CS#
+1.5V_MEM
E10
F2
H3
H10
D3
D10
G8
K3
K9
N2
N10
R2
R10
M_ODT0
K2
M_CLK_DDR0
J8
M_CLK_DDR#0
K8
DDR_CKE0
K10
M3
DDR_A_BS1
N9
DDR_A_BS2
M4
L3
DDR_A_RAS#
J4
DDR_A_CAS#DDR_A_MA7
K4
DDR_A_WE#
L4
DDR3_DRAMRST#
T3
E3
E9
F10
G2
G10
D2
D9
E2
G9
J3
J9
M2
M10
P2
P10
T2
T10
U5
F4
DQS
DDR_A_DQS#2<11>
DDR_A_D[16..23]<11>
1 2
R155 240_0402_5%~D
+V_DDR_MCH_REF+V_DDR_MCH_REF +V_DDR_MCH_REF +V_DDR_MCH_REF
DDR_A_MA0
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
G4
DDR_A_D21
DDR_A_D18
DDR_A_D17
DDR_A_D19
DDR_A_D22
DDR_A_D16 DDR_A_D33
DDR_A_D20 DDR_A_D53
DDR_A_D23
DQS#
E4
DQ0
F8
DQ1
F3
DQ2
F9
DQ3
H4
DQ4
H9
DQ5
G3
DQ6
H8
DQ7
D8
NU/TDQS#
E8
DM/TDQS
L9
ZQ
H2
VREFDQ
M9
VREFCA
N4
A0
P8
A1
P4
A2
N3
A3
P9
A4
P3
A5
R9
A6
R3
A7
T9
A8
R4
A9
L8
A10/AP
R8
A11
N8
A12/BC#
T4
A13
A1
NC
A2
NC
A4
NC
A8
NC
A10
NC
A11
NC
D1
NC
D4
NC
D11
NC
J2
NC
J10
NC
L2
NC
L10
NC
M8
NC
T1
NC
T8
NC
T11
NC
W1
NC
W2
NC
W4
NC
W8
NC
W10
NC
W11
NC
K4B1G0846C-ZCF7_FBGA94~D
+1.5V_MEM +1.5V_MEM +1.5V_MEM
VDDQ
VDDQ
VDDQ
VDDQ
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
ODT
CK#
CKE
BA0
BA1
BA2
CS#
RAS#
CAS#
WE#
RESET#
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
E10
F2
H3
H10
D3
D10
G8
K3
K9
N2
N10
R2
R10
K2
J8
CK
K8
K10
M3
N9
M4
L3
J4
K4
L4
T3
E3
E9
F10
G2
G10
D2
D9
E2
G9
J3
J9
M2
M10
P2
P10
T2
T10
DDR_A_DQS4<11>
DDR_A_DQS#4<11>
DDR_A_D[32..39]<11> DDR_A_D[48..55]<11>DDR_A_D[0..7]<11>
M_ODT0
M_CLK_DDR0
M_CLK_DDR#0
DDR_CKE0
DDR_A_BS0
DDR_A_BS1
DDR_A_BS2
DDR_CS#0
DDR_A_RAS#
DDR_A_CAS#
DDR_A_WE#
DDR3_DRAMRST#
DDR_A_D39
DDR_A_D34
DDR_A_D32
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_DM4<11> DDR_A_DM6<11>DDR_A_DM2<11>DDR_A_DM0<11>
1 2
R156 240_0402_5%~D
DDR_A_MA0
DDR_A_MA1DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
U6
F4
DQS
G4
DQS#
E4
DQ0
F8
DQ1
F3
DQ2
F9
DQ3
H4
DQ4
H9
DQ5
G3
DQ6
H8
DQ7
D8
NU/TDQS#
E8
DM/TDQS
L9
ZQ
H2
VREFDQ
M9
VREFCA
N4
A0
P8
A1
P4
A2
N3
A3
P9
A4
P3
A5
R9
A6
R3
A7
T9
A8
R4
A9
L8
A10/AP
R8
A11
N8
A12/BC#
T4
A13
A1
NC
A2
NC
A4
NC
A8
NC
A10
NC
A11
NC
D1
NC
D4
NC
D11
NC
J2
NC
J10
NC
L2
NC
L10
NC
M8
NC
T1
NC
T8
NC
T11
NC
W1
NC
W2
NC
W4
NC
W8
NC
W10
NC
W11
NC
K4B1G0846C-ZCF7_FBGA94~D
VDDQ
VDDQ
VDDQ
VDDQ
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
ODT
RAS#
CAS#
WE#
RESET#
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
CK#
CKE
BA0
BA1
BA2
CS#
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
CK
E10
F2
H3
H10
D3
D10
G8
K3
K9
N2
N10
R2
R10
M_ODT0
K2
M_CLK_DDR0
J8
M_CLK_DDR#0
K8
DDR_CKE0
K10
DDR_A_BS0
M3
DDR_A_BS1
N9
DDR_A_BS2
M4
DDR_CS#0
L3
DDR_A_RAS#
J4
DDR_A_CAS#
K4
DDR_A_WE#
L4
DDR3_DRAMRST#
T3
E3
E9
F10
G2
G10
D2
D9
E2
G9
J3
J9
M2
M10
P2
P10
T2
T10
DDR_A_DQS6<11>
DDR_A_DQS#6<11>DDR_A_DQS#0<11>
1 2
R157 240_0402_5%~D
DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_D54
DDR_A_D51
DDR_A_D49
DDR_A_D50
DDR_A_D52
DDR_A_D48
DDR_A_D55
U7
F4
DQS
G4
DQS#
E4
DQ0
F8
DQ1
F3
DQ2
F9
DQ3
H4
DQ4
H9
DQ5
G3
DQ6
H8
DQ7
D8
NU/TDQS#
E8
DM/TDQS
L9
ZQ
H2
VREFDQ
M9
VREFCA
N4
A0
P8
A1
P4
A2
N3
A3
P9
A4
P3
A5
R9
A6
R3
A7
T9
A8
R4
A9
L8
A10/AP
R8
A11
N8
A12/BC#
T4
A13
A1
NC
A2
NC
A4
NC
A8
NC
A10
NC
A11
NC
D1
NC
D4
NC
D11
NC
J2
NC
J10
NC
L2
NC
L10
NC
M8
NC
T1
NC
T8
NC
T11
NC
W1
NC
W2
NC
W4
NC
W8
NC
W10
NC
W11
NC
K4B1G0846C-ZCF7_FBGA94~D
VDDQ
VDDQ
VDDQ
VDDQ
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
ODT
CK#
CKE
BA0
BA1
BA2
CS#
RAS#
CAS#
WE#
RESET#
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
CK
E10
F2
H3
H10
D3
D10
G8
K3
K9
N2
N10
R2
R10
M_ODT0
K2
M_CLK_DDR0
J8
M_CLK_DDR#0
K8
DDR_CKE0
K10
DDR_A_BS0
M3
DDR_A_BS1
N9
DDR_A_BS2
M4
DDR_CS#0
L3
DDR_A_RAS#
J4
DDR_A_CAS#
K4
DDR_A_WE#
L4
DDR3_DRAMRST#
T3
E3
E9
F10
G2
G10
D2
D9
E2
G9
J3
J9
M2
M10
P2
P10
T2
T10
10U_0603_6.3V6M~D
0.1U_0402_16V4Z~D
C148
C155
+1.5V_MEM
10U_0603_6.3V6M~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1
C164
C165
2
2
1
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
C157
C156
1
2
1
1
2
2
1U_0402_6.3V6K~D
C166
C167
2
2
1
1
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
C158
1
2
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
C168
C169
2
2
1
1
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
C170
2
1
1U_0402_6.3V6K~D
C171
2
2
1
1
Place close to GMCH Place the end of the DDR3
M_CLK_DDR0
M_CLK_DDR#0
C142
3.3P_0402_50V8C~D
1
2
12
R152
30_0402_1%~D
M_CLK_DDR0_TERM
12
R153
30_0402_1%~D
C149
1
2
0.1U_0402_10V7K~D
B B
A A
DDR_A_MA[0..14]<11,17>
M_ODT0<10,17>
M_CLK_DDR0<10,17>
M_CLK_DDR#0<10,17>
DDR_CKE0<10,17>
DDR_A_BS0<11,17>
DDR_A_BS1<11,17>
DDR_A_BS2<11,17>
DDR_CS#0<10,17>
DDR_A_RAS#<11,17>
DDR_A_CAS#<11,17>
DDR_A_WE#<11,17>
DDR3_DRAMRST#<10,17,18>
M_ODT0
M_CLK_DDR0
M_CLK_DDR#0
DDR_CKE0
DDR_A_BS0
DDR_A_BS1
DDR_A_BS2
DDR_CS#0
DDR_A_RAS#
DDR_A_CAS#
DDR_A_WE#
DDR3_DRAMRST#
+1.5V_MEM
330U_D2_2.5VY_R15M
1
C159
C143
+
2
+V_DDR_MCH_REF
2.2U_0603_6.3V6K~D
C152
C160
1
2
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
C144
C145
1
1
2
2
2.2U_0603_6.3V6K~D
0.1U_0402_16V4Z~D
C150
C151
1
1
2
2
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
C147
C146
1
1
1
2
2
2
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
C153
C154
1
1
1
2
2
2
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
DDRIII-Memory Down (Top)
LA-4291P
1
16 49Friday, Decemb er 07, 2007
0.1
of
Page 17
5
4
3
2
1
U8
DDR_A_D10
DDR_A_D13
DDR_A_D11
DDR_A_D8
DDR_A_D9
DDR_A_D14
DDR_A_D12
DDR_A_D15
DDR_A_MA[0..14]<11,16>
M_CLK_DDR0<10,16>
M_CLK_DDR#0<10,16>
DDR_A_RAS#<11,16>
DDR_A_CAS#<11,16>
DDR3_DRAMRST#<10,16,18>
F4
DQS
G4
DQS#
E4
DQ0
F8
DQ1
F3
DQ2
F9
DQ3
H4
DQ4
H9
DQ5
G3
DQ6
H8
DQ7
D8
NU/TDQS#
E8
DM/TDQS
L9
ZQ
H2
VREFDQ
M9
VREFCA
N4
A0
P8
A1
P4
A2
N3
A3
P9
A4
P3
A5
R9
A6
R3
A7
T9
A8
R4
A9
L8
A10/AP
R8
A11
N8
A12/BC#
T4
A13
A1
NC
A2
NC
A4
NC
A8
NC
A10
NC
A11
NC
D1
NC
D4
NC
D11
NC
J2
NC
J10
NC
L2
NC
L10
NC
M8
NC
T1
NC
T8
NC
T11
NC
W1
NC
W2
NC
W4
NC
W8
NC
W10
NC
W11
NC
K4B1G0846C-ZCF7_FBGA94~D
M_ODT0<10,16>
DDR_CKE0<10,16>
DDR_A_BS0<11,16>
DDR_A_BS1<11,16>
DDR_A_BS2<11,16>
DDR_CS#0<10,16>
DDR_A_WE#<11,16>
M_ODT0
M_CLK_DDR0
M_CLK_DDR#0
DDR_CKE0
DDR_A_BS0
DDR_A_BS1
DDR_A_BS2
DDR_CS#0
DDR_A_RAS#
DDR_A_CAS#
DDR_A_WE#
DDR3_DRAMRST#
DDR_A_DQS1<11> DDR_A_DQS3<11>
D D
1 2
R158 240_0402_5%~D
DDR_A_MA0
DDR_A_MA1 DDR_A_BS0
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5 DDR_CS#0
DDR_A_MA6
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
C C
DDR_A_MA14 DDR_A_MA14 DDR_A_MA14 DDR_A_MA14
B B
A A
VDDQ
VDDQ
VDDQ
VDDQ
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
ODT
CKE
RAS#
CAS#
WE#
RESET#
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
CK
CK#
BA0
BA1
BA2
CS#
+1.5V_MEM
E10
F2
H3
H10
D3
D10
G8
K3
K9
N2
N10
R2
R10
M_ODT0
K2
M_CLK_DDR0
J8
M_CLK_DDR#0
K8
DDR_CKE0
K10
M3
DDR_A_BS1
N9
DDR_A_BS2
M4
L3
DDR_A_RAS#
J4
DDR_A_CAS#DDR_A_MA7
K4
DDR_A_WE#
L4
DDR3_DRAMRST#
T3
E3
E9
F10
G2
G10
D2
D9
E2
G9
J3
J9
M2
M10
P2
P10
T2
T10
DDR_A_DQS#3<11>
DDR_A_D[24..31]<11>
+V_DDR_MCH_REF+V_DDR_MCH_REF +V_DDR_MCH_REF +V_DDR_MCH_REF
+V_DDR_MCH_REF
2.2U_0603_6.3V6K~D
C161
C196
1
2
1K_0402_5%~D@
12
R163
R162
DDR_A_D27
DDR_A_D30
DDR_A_D26
DDR_A_D25
DDR_A_D31
DDR_A_D28
DDR_A_D24
DDR_A_D29
1 2
R159 240_0402_5%~D
DDR_A_MA0
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
2.2U_0603_6.3V6K~D
0.1U_0402_16V4Z~D
C190
C191
1
1
2
2
U2
1
A0
2
A1
3
1K_0402_5%~D@
12
A2
4
GND
AT24C02N-10SU-2.7_SO8@
F4
G4
E4
F8
F3
F9
H4
H9
G3
H8
D8
E8
L9
H2
M9
N4
P8
P4
N3
P9
P3
R9
R3
T9
R4
L8
R8
N8
T4
A1
A2
A4
A8
A10
A11
D1
D4
D11
J2
J10
L2
L10
M8
T1
T8
T11
W1
W2
W4
W8
W10
W11
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
C192
1
1
2
2
VCC
WP
SCL
SDA
U9
DQS
DQS#
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
NU/TDQS#
DM/TDQS
ZQ
VREFDQ
VREFCA
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC#
A13
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
K4B1G0846C-ZCF7_FBGA94~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
C194
1
2
+3.3V_M
C195
1
2
0.1U_0402_16V4Z~D@
MEM_SCLK
MEM_SDATA
C193
8
7
6
5
+1.5V_MEM +1.5V_MEM +1.5V_MEM
VDDQ
VDDQ
VDDQ
VDDQ
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
ODT
CK#
CKE
BA0
BA1
BA2
CS#
RAS#
CAS#
WE#
RESET#
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
E10
F2
H3
H10
D3
D10
G8
K3
K9
N2
N10
R2
R10
K2
J8
CK
K8
K10
M3
N9
M4
L3
J4
K4
L4
T3
E3
E9
F10
G2
G10
D2
D9
E2
G9
J3
J9
M2
M10
P2
P10
T2
T10
DDR_A_DQS5<11>
DDR_A_DQS#5<11>
DDR_A_D[40..47]<11> DDR_A_D[56..63]<11>DDR_A_D[8..15]<11>
M_ODT0
M_CLK_DDR0
M_CLK_DDR#0
DDR_CKE0
DDR_A_BS0
DDR_A_BS1
DDR_A_BS2
DDR_CS#0
DDR_A_RAS#
DDR_A_CAS#
DDR_A_WE#
DDR3_DRAMRST#
DDR_A_D42
DDR_A_D41
DDR_A_D43
DDR_A_D47
DDR_A_D46
DDR_A_D40
DDR_A_D44
DDR_A_D45
DDR_A_DM5<11> DDR_A_DM7<11>DDR_A_DM3<11>DDR_A_DM1<11>
1 2
R160 240_0402_5%~D
DDR_A_MA0
DDR_A_MA1DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
U10
F4
DQS
G4
DQS#
E4
DQ0
F8
DQ1
F3
DQ2
F9
DQ3
H4
DQ4
H9
DQ5
G3
DQ6
H8
DQ7
D8
NU/TDQS#
E8
DM/TDQS
L9
ZQ
H2
VREFDQ
M9
VREFCA
N4
A0
P8
A1
P4
A2
N3
A3
P9
A4
P3
A5
R9
A6
R3
A7
T9
A8
R4
A9
L8
A10/AP
R8
A11
N8
A12/BC#
T4
A13
A1
NC
A2
NC
A4
NC
A8
NC
A10
NC
A11
NC
D1
NC
D4
NC
D11
NC
J2
NC
J10
NC
L2
NC
L10
NC
M8
NC
T1
NC
T8
NC
T11
NC
W1
NC
W2
NC
W4
NC
W8
NC
W10
NC
W11
NC
K4B1G0846C-ZCF7_FBGA94~D
VDDQ
VDDQ
VDDQ
VDDQ
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
ODT
RAS#
CAS#
WE#
RESET#
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
CK#
CKE
BA0
BA1
BA2
CS#
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
CK
E10
F2
H3
H10
D3
D10
G8
K3
K9
N2
N10
R2
R10
M_ODT0
K2
M_CLK_DDR0
J8
M_CLK_DDR#0
K8
DDR_CKE0
K10
DDR_A_BS0
M3
DDR_A_BS1
N9
DDR_A_BS2
M4
DDR_CS#0
L3
DDR_A_RAS#
J4
DDR_A_CAS#
K4
DDR_A_WE#
L4
DDR3_DRAMRST#
T3
E3
E9
F10
G2
G10
D2
D9
E2
G9
J3
J9
M2
M10
P2
P10
T2
T10
DDR_A_DQS7<11>
DDR_A_DQS#7<11>DDR_A_DQS#1<11>
1 2
R161 240_0402_5%~D
DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_D58
DDR_A_D61
DDR_A_D59
DDR_A_D60
DDR_A_D63
DDR_A_D57
DDR_A_D62
DDR_A_D56
U11
F4
DQS
G4
DQS#
E4
DQ0
F8
DQ1
F3
DQ2
F9
DQ3
H4
DQ4
H9
DQ5
G3
DQ6
H8
DQ7
D8
NU/TDQS#
E8
DM/TDQS
L9
ZQ
H2
VREFDQ
M9
VREFCA
N4
A0
P8
A1
P4
A2
N3
A3
P9
A4
P3
A5
R9
A6
R3
A7
T9
A8
R4
A9
L8
A10/AP
R8
A11
N8
A12/BC#
T4
A13
A1
NC
A2
NC
A4
NC
A8
NC
A10
NC
A11
NC
D1
NC
D4
NC
D11
NC
J2
NC
J10
NC
L2
NC
L10
NC
M8
NC
T1
NC
T8
NC
T11
NC
W1
NC
W2
NC
W4
NC
W8
NC
W10
NC
W11
NC
K4B1G0846C-ZCF7_FBGA94~D
DDR3 Terminations
1
2
C199
1 2
0.1U_0402_16V4Z~D
C197
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
C198
1
1
2
2
MEM_SCLK <18,24>
MEM_SDATA <18,24>
36_0404_4P2R_5%~D
DDR_CS#0
DDR_A_WE#
36_0404_4P2R_5%~D
DDR_A_MA12
DDR_A_BS1
36_0404_4P2R_5%~D
DDR_A_MA10
DDR_A_BS2
36_0404_4P2R_5%~D
DDR_A_BS0
DDR_A_MA0
36_0404_4P2R_5%~D
DDR_A_MA4
DDR_A_MA1
36_0404_4P2R_5%~D
+0.75V_DDR_VTT
RP1
1 4
2 3
RP3
1 4
2 3
RP5
1 4
2 3
RP7
1 4
2 3
RP9
1 4
2 3
RP11
1 4
2 3
RP2
1 4
2 3
36_0404_4P2R_5%~D
RP4
1 4
2 3
36_0404_4P2R_5%~D
RP6
1 4
2 3
36_0404_4P2R_5%~D
RP8
1 4
2 3
36_0404_4P2R_5%~D
RP10
1 4
2 3
36_0404_4P2R_5%~D
RP12
1 4
2 3
36_0404_4P2R_5%~D
DDR_A_RAS#DDR_A_CAS#
M_ODT0DDR_CKE0
DDR_A_MA2
DDR_A_MA3
DDR_A_MA6
DDR_A_MA8
DDR_A_MA5
DDR_A_MA9
DDR_A_MA11
DDR_A_MA14
DDR_A_MA7
DDR_A_MA13
+0.75V_DDR_VTT
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
C183
2
1
Place decaps close end termination resistors, one decap for 4 resistors
2
2
C185
C184
1
1
E10
VDDQ
F2
VDDQ
H3
VDDQ
H10
VDDQ
D3
VDD
D10
VDD
G8
VDD
K3
VDD
K9
VDD
N2
VDD
N10
VDD
R2
VDD
R10
VDD
M_ODT0
K2
ODT
M_CLK_DDR0
J8
CK
M_CLK_DDR#0
K8
CK#
DDR_CKE0
K10
CKE
DDR_A_BS0
M3
BA0
DDR_A_BS1
N9
BA1
DDR_A_BS2
M4
BA2
DDR_CS#0
L3
CS#
DDR_A_RAS#
J4
RAS#
DDR_A_CAS#
K4
CAS#
DDR_A_WE#
L4
WE#
DDR3_DRAMRST#
T3
RESET#
E3
VSSQ
E9
VSSQ
F10
VSSQ
G2
VSSQ
G10
VSSQ
D2
VSS
D9
VSS
E2
VSS
G9
VSS
J3
VSS
J9
VSS
M2
VSS
M10
VSS
P2
VSS
P10
VSS
T2
VSS
T10
VSS
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
2
C186
1
1U_0402_6.3V6K~D
2
2
C187
C188
1
1
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
DDRIII-Memory Down (Bottom)
LA-4291P
1
17 49Friday, Decemb er 07, 2007
0.1
of
Page 18
5
DDR_B_D[0..63]<11>
DDR_B_DQS[0..7]<11>
D D
C C
B B
A A
DDR_B_DQS#[0..7]<11>
DDR_B_DM[0..7]<11>
DDR_B_MA[0..14]<11>
DDR_CKE2_DIMM<10>
DDR_B_BS2<11>
M_CLK_DDR2<10>
M_CLK_DDR#2<10>
DDR_B_BS0<11>
DDR_B_WE#<11>
DDR_B_CAS#<11>
DDR_CS3_DIMM#<10>
+3.3V_M
R164
1 2
+3.3V_M
10K_0402_5%~D
5
0.1U_0402_16V4Z~D
C217
C218
1
2
DDR_B_D0
DDR_B_D1
DDR_B_DM0
DDR_B_D2
DDR_B_D3
DDR_B_D8
DDR_B_D9
DDR_B_DQS#1
DDR_B_DQS1
DDR_B_D10
DDR_B_D11
DDR_B_D16
DDR_B_D17
DDR_B_DQS#2
DDR_B_DQS2
DDR_B_D18
DDR_B_D19
DDR_B_D24
DDR_B_D25
DDR_B_DM3
DDR_B_D26
DDR_B_D27
DDR_CKE2_DIMM
DDR_B_BS2
DDR_B_MA12
DDR_B_MA9
DDR_B_MA8
DDR_B_MA5
DDR_B_MA3
DDR_B_MA1
M_CLK_DDR#2
DDR_B_MA10
DDR_B_BS0
DDR_B_WE#
DDR_B_CAS#
DDR_B_MA13
DDR_CS3_DIMM#
T42
DDR_B_D32
DDR_B_D33
DDR_B_DQS#4
DDR_B_DQS4
DDR_B_D34
DDR_B_D35
DDR_B_D40
DDR_B_D41
DDR_B_DM5
DDR_B_D42
DDR_B_D43
DDR_B_D48
DDR_B_D49
DDR_B_DQS#6
DDR_B_DQS6
DDR_B_D50
DDR_B_D51
DDR_B_D56
DDR_B_D57
DDR_B_DM7
DDR_B_D58
DDR_B_D59
2.2U_0603_6.3V6K~D
+0.75V_DDR_VTT
10K_0402_5%~D
12
R165
1
2
4
+1.5V_MEM+1.5V_MEM +V_DDR_MCH_REF
JDIMM
1
VREF_DQ
3
VSS
5
DQ0
7
DQ1
9
VSS
11
DM0
13
VSS
15
DQ2
17
DQ3
19
VSS
21
DQ8
23
DQ9
25
VSS
27
DQS1#
29
DQS1
31
VSS
33
DQ10
35
DQ11
37
VSS
39
DQ16
41
DQ17
43
VSS
45
DQS2#
47
DQS2
49
VSS
51
DQ18
53
DQ19
55
VSS
57
DQ24
59
DQ25
61
VSS
63
DM3
65
VSS
67
DQ26
69
DQ27
71
VSS
73
CKE0
75
VDD
77
NC
79
BA2
81
VDD
83
A12/BC#
85
A9
87
VDD
89
A8
91
A5
93
VDD
95
A3
97
A1
99
VDD
101
CK0
103
CK0#
105
VDD
107
A10/AP
109
BA0
111
VDD
113
WE#
115
CAS#
117
VDD
119
A13
121
S1#
123
VDD
125
TEST
127
VSS
129
DQ32
131
DQ33
133
VSS
135
DQS4#
137
DQS4
139
VSS
141
DQ34
143
DQ35
145
VSS
147
DQ40
149
DQ41
151
VSS
153
DM5
155
VSS
157
DQ42
159
DQ43
161
VSS
163
DQ48
165
DQ49
167
VSS
169
DQS6#
171
DQS6
173
VSS
175
DQ50
177
DQ51
179
VSS
181
DQ56
183
DQ57
185
VSS
187
DM7
189
VSS
191
DQ58
193
DQ59
195
VSS
197
SA0
199
VDDSPD
201
SA1
203
VTT
205
GND1
207
GND2
TYCO_1903892-1
DDR3 SO-DIMM/Standard Type
4
VSS
DQ4
DQ5
VSS
DQS0#
DQS0
VSS
DQ6
DQ7
VSS
DQ12
DQ13
VSS
DM1
RESET#
VSS
DQ14
DQ15
VSS
DQ20
DQ21
VSS
DM2
VSS
DQ22
DQ23
VSS
DQ28
DQ29
VSS
DQS3#
DQS3
VSS
DQ30
DQ31
VSS
CKE1
VDD
VDD
VDD
VDD
VDD
CK1
CK1#
VDD
BA1
RAS#
VDD
ODT0
VDD
ODT1
VDD
VREF_CA
VSS
DQ36
DQ37
VSS
DM4
VSS
DQ38
DQ39
VSS
DQ44
DQ45
VSS
DQS5#
DQS5
VSS
DQ46
DQ47
VSS
DQ52
DQ53
VSS
DM6
VSS
DQ54
DQ55
VSS
DQ60
DQ61
VSS
DQS7#
DQS7
VSS
DQ62
DQ63
VSS
EVENT#
SDA
SCL
VTT
BOSS1
BOSS2
A15
A14
A11
A7
A6
A4
A2
A0
S0#
NC
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204
206
208
+V_DDR_MCH_REF
DDR_B_D4
DDR_B_D5
DDR_B_DQS#0
DDR_B_DQS0
DDR_B_D6
DDR_B_D7
DDR_B_D12
DDR_B_D13
DDR_B_DM1
DDR3_DRAMRST#
DDR_B_D14
DDR_B_D15
DDR_B_D20
DDR_B_D21
DDR_B_DM2
DDR_B_D22
DDR_B_D23
DDR_B_D28
DDR_B_D29
DDR_B_DQS#3
DDR_B_DQS3
DDR_B_D30
DDR_B_D31
DDR_CKE3_DIMM
DDR_B_MA14
DDR_B_MA11
DDR_B_MA7
DDR_B_MA6
DDR_B_MA4
DDR_B_MA2
DDR_B_MA0
M_CLK_DDR3M_CLK_DDR2
M_CLK_DDR#3
DDR_B_BS1
DDR_B_RAS#
DDR_CS2_DIMM#
M_ODT2_DIMM
M_ODT3_DIMM
+V_DDR_MCH_REF
DDR_B_D36
DDR_B_D37
DDR_B_DM4
DDR_B_D38
DDR_B_D39
DDR_B_D44
DDR_B_D45
DDR_B_DQS#5
DDR_B_DQS5
DDR_B_D46
DDR_B_D47
DDR_B_D52
DDR_B_D53
DDR_B_DM6
DDR_B_D54
DDR_B_D55
DDR_B_D60
DDR_B_D61
DDR_B_DQS#7
DDR_B_DQS7
DDR_B_D62
DDR_B_D63
PM_EXTTS#_R
MEM_SDATA
MEM_SCLK
+0.75V_DDR_VTT
3
0.1U_0402_16V4Z~D
2.2U_0603_6.3V6K~D
C201
C200
1
1
2
2
DDR3_DRAMRST# <10,16,17>
2
Place close to SO-DIMM
+1.5V_MEM
DDR_CKE3_DIMM <10>
T41
M_CLK_DDR3 <10>
M_CLK_DDR#3 <10>
DDR_B_BS1 <11>
DDR_B_RAS# <11>
DDR_CS2_DIMM# <10>
M_ODT2_DIMM <10>
M_ODT3_DIMM <10>
0.1U_0402_16V4Z~D
C212
C211
1
1
2
2
+V_DDR_MCH_REF
2.2U_0603_6.3V6K~D
+0.75V_DDR_VTT
Place close to JDIMM pin 203 and 204
R759
0_0402_5%~D
1 2
MEM_SDATA <17,24>
MEM_SCLK <17,24>
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
PM_EXTTS# <10,19>
2
1
330U_D2_2.5VY_R15M
1
C162
C202
+
2
0.1U_0402_16V4Z~D
C208
C163
1
2
1U_0402_6.3V6K~D
C213
C214
2
2
1
1
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
C203
1
2
0.1U_0402_16V4Z~D
C209
1
2
1U_0402_6.3V6K~D
C215
2
1
10U_0603_6.3V6M~D
C204
C205
1
1
2
2
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
C210
1
1
2
2
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
C216
2
1
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
C206
1
2
10U_0603_6.3V6M~D
C207
1
1
2
2
DELL CONFIDENTIAL/PROPRIETARY
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
DDRIII SO-DIMM SLOT
LA-4291P
18 49Friday, Decemb er 07, 2007
1
0.1
of
Page 19
5
BC_DAT_EMC4002<34>
Place Q29 under CPU
2
D D
C224
100P_0402_50V8K~D@
1
C
Q29
2
B
MMST3904-7-F_SOT323-3~D
E
3 1
BC_CLK_EMC4002<34>
2
C225
2200P_0402_50V7K~D
1
C225 close to Guardian and C224 close to Q29
Place C226 close to Guardian pin as possible
H_THERMDA<7>
H_THERMDC<7>
1
C226
470P_0402_50V7K~D
2
Place Q28 close to SO-DIMM
1
C223
100P_0402_50V8K~D@
2
C
Q28
2
B
MMST3904-7-F_SOT323-3~D
E
3 1
1
C229
2200P_0402_50V7K~D
2
C229 close to Guardian and C223 close to Q28
+3.3V_M
C C
B B
A A
1 2
0_0603_5%~D
+1.05V_VCCP
H_THERMTRIP#<7>
+1.05V_VCCP
THERMTRIP_MCH#<10>
R176
C230
1
2
Rset=953,Tp=88degree
R168
1 2
2.2K_0402_5%~D
MMST3904-7-F_SOT323-3~D
R172
1 2
2.2K_0402_5%~D
MMST3904-7-F_SOT323-3~D
5
0.1U_0402_16V4Z~D
C232
+RTC_CELL
0.1U_0402_16V4Z~D
1
2
2
B
Q26
2
B
Q27
12
R186
+3.3V_M
12
R167
8.2K_0402_5%~D
C
E
3 1
+3.3V_M
12
R171
8.2K_0402_5%~D
C
E
3 1
1 2
R178
0_0603_5%~D
953_0402_1%~D
THERMATRIP1#
1
C219
0.1U_0402_16V4Z~D
2
THERMATRIP2# THERMATRIP3#
1
C221
0.1U_0402_16V4Z~D
2
+5V_RUN
C236
1
2
C231
10U_0805_10V4Z~D
C235
1U_0603_10V4Z~D
1
2
1
2
+3V_M_THRM
0.1U_0402_16V4Z~D
+3.3V_RUN
*
+3.3V_M
ICH_PWRGD#<34>
C238
Pull-up Resistor on
ADDR_MODE/XEN
12
R191
8.2K_0402_5%~D
1
C241
0.1U_0402_16V4Z~D
2
4
BC_DAT_EMC4002
BC_CLK_EMC4002
REM_DIODE1_P
REM_DIODE1_N
REM_DIODE3_P
REM_DIODE3_N
+3V_M_THRM
+3.3V_M
R185 4.7K_0402_5%~D
10U_0805_10V4Z~D
C237
1
2
EC_32KHZ_OUT<34>
+RTC_CELL_R
R181 10K_0402_5%~D
1 2
R183 1K_0402_5%~D
1 2
THERMATRIP1#
THERMATRIP2#
THERMATRIP3#
VSET
12
0.1U_0402_16V4Z~D
+FAN1_VOUT
1
FAN1_TACH_FB
2
EC_32KHZ_OUT
For Remote1 mode
<= 4.7K +/- 5% 2F(r/w)
10K
18K
>= 33K
4
2N3904
2N3904
Thermistor
Thermistor
Must conf i r m we can get C version to solve leakage issue
Backdrive from RTC PWR to 3VSUS
B Version need external solution , check Roush I schematic
U3
10
SMDATA/BC-LINK_DATA
11
SMBCLK/BC-LINK_CLK
36
DP1/VREF_T
35
DN1/THERM
38
DP2
37
DN2
41
DP3/DN7
40
DN3/DP7
4
VCC
21
RTC_PWR3V
THERMTRIP_SIO/PWM1/GPIO5
18
VCC_PWRGD
17
3V_PWROK#
22
THERMTRIP1#
23
THERMTRIP2#
24
THERMTRIP3#
42
VSET
3
ADDR_MODE/XEN
6
VDD_5V
5
VDD_5V
9
VDD_3V
7
FAN_OUT
8
FAN_OUT
15
TACH1/GPIO3
14
CLK_IN/GPIO2
SMBus
Address
2F(r/w)
2F(r/w)
2F(r/w)
VIN1
VCP1
VCP2
DP4/DN8
DN4/DP8
DP5/DN9
DN5/DP9
DP6/VREF_T2
DN6/VIN2
ATF_INT#/BC-LINK_IRQ#
POWER_SW#
ACAVAIL_CLR
SYS_SHDN#
LDO_SHDN#
LDO_POK
LDO_SET
VDDH/VDD_5V2
VDDH/VDD_5V2
VDDL/VDD_3V2
LDO_OUT/FAN_OUT2
LDO_OUT/FAN_OUT2
TACH2/GPIO4
PWM2/GPIO1
VSS
EMC4002-HZHK C_QFN48_7X7~D
49
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
R1063
0_0402_5%~D
270K_0402_1%@
12
R1064
39
48
45
REM_DIODE4_P
44
REM_DIODE4_N
43
47
46
1
2
R175 10K_0402_5%~D
BC_INT#_EMC4002
12
POWER_SW#
26
ACAV_IN
27
20
THERM_STP#
25
1 2
R182 47K_0402_1%~D@
R184
19
10K_0402_5%~D
34
LDO_SET
33
+3V_LDOIN
32
31
+1.8V_RUN_LVDS
28
29
30
16
C240
1
13
2
R189
0_0402_5%~D
3
12
0.1U_0402_16V4Z~D
C239
2
PWR_MON_GFX <44>
1 2
R1098
4.7K_0402_5%~D
Diode circuit at DP4/DN4 is used for skin temp sensor
(placed Q28 optimally between CPU, MCH and MEM)
PWR_MON <43>
MAX8731_IINP <46>
1
C222
2200P_0402_50V7K~D
2
C
2
B
E
Q30
3 1
MMST3904-7-F_SOT323-3~D
C222 close to Guardian and C228 close to Q30
THERMISTOR OPTION:
Single-ended routing t o thermistor i s permissible
(ground return). Place R173 and C227 near EMC4002
1 2
R174
10K_0603_1%_TSM1A103F34D3RZ~D
1 2
C227
0.1U_0402_16V4Z~D
R180
10K_0402_5%~D
R187
0_1210_5%~D
74AHCT1G08GW_SOT353-5~D
12
+3.3V_M
+3.3V_RUN
12
12
12
10U_0805_10V4Z~D
1
2
12
BC_INT#_EMC4002 <34>
ACAV_IN <34,46>
THERM_STP# <41>
+RTC_CELL
+3.3V_SUS
0.1U_0402_16V4Z~D
C234
C233
1
1
2
2
PM_EXTTS# <10,18>
1 2
R173
1.2K_0402_1%~D
+3.3V_M
10U_0805_10V4Z~D
At maximum load current of 600mA,the the
voltage drop across the should be keep in
the range of 0.5V to 1V
FAN control and Tachometer
+3.3V_M
FAN1_DET#<22>
RB751S40T1_SOD523-2~D
22U_0805_6.3VAM~D
C220
D2
1
2
2 1
2
100P_0402_50V8K~D@
12
R169
10K_0402_5%~D
FAN1_DET#
+FAN1_VOUT
FAN1_TACH_FB
C228
+RTC_CELL
U95
4
Y
0_0402_5%~D@
1 2
1 2
0_0402_5%~D@
1
2
3
4
5
6
MOLEX_53780-0470
1
1
2
C1358
1 2
0.1U_0402_16V4Z~D
5
P
A
B
G
3
R1107
R179
JFAN
1
2
3
4
GND
GND
2
1
R1105
0_0402_5%~D
12
DOCK_PWR_SW# <34>
12
+1.8V_RUN_LVDS
LDO_SET
POWER_SW_IN# <34>
1.27K_0402_1%~D
12
R188
Ra
2K_0402_1%~D
12
R190
Rb
R1106
0_0402_5%~D
Voltage margining
circuit for LDO output
Adjustable fr o m 1.2V to 2.5V
Ra = ((LDO_OUT/1.1)-1) x Rb
DELL CONFIDENTIAL/PROPRIETARY
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
Thermal Sensor and FAN
LA-4291P
19 49Friday, Decemb er 07, 2007
1
0.1
of
Page 20
5
+3.3V_RUN_BKT_PWR
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
C762
C761
D D
LCD_A0+_MCH<12>
LCD_A0-_MCH<12>
BKT_LVDS_RIN0+<21>
BKT_LVDS_RIN0-<21>
LCD_A1+_MCH<12>
LCD_A1-_MCH<12>
BKT_LVDS_RIN1+<21>
BKT_LVDS_RIN1-<21>
LCD_A2+_MCH<12>
LCD_A2-_MCH<12>
BKT_LVDS_RIN2+<21>
BKT_LVDS_RIN2-<21>
LCD_ACLK+_MCH<12>
LCD_ACLK-_MCH<12>
BKT_LVDS_CLK+<21>
BKT_LVDS_CLK-<21>
C C
SEL Logic 1 Work from BKT
SEL
NC to COM NO toCOM
0ON
1
DAT_DDC2<12>
B B
CLK_DDC2<12>
CRT_VSYNC<12>
CRT_HSYNC<12>
CRT_RED<12>
CRT_GRN<12>
CRT_BLU<12>
CRT_SWITCH<33>
1
2
C763
1
1
2
2
LCD_A0+_MCH
LCD_A0-_MCH
BKT_LVDS_RIN0+
BKT_LVDS_RIN0-
LCD_A1+_MCH
LCD_A1-_MCH
BKT_LVDS_RIN1+
BKT_LVDS_RIN1-
LCD_A2+_MCH
LCD_A2-_MCH
BKT_LVDS_RIN2+
BKT_LVDS_RIN2-
LCD_ACLK+_MCH
LCD_ACLK-_MCH
BKT_LVDS_CLK+
BKT_LVDS_CLK-
OFF
ONOFF
+3.3V_RUN
DAT_DDC2
CLK_DDC2
CRT_VSYNC
CRT_HSYNC
CRT_RED
CRT_GRN
CRT_BLU
CRT_SWITCH
SEL0CRT
MB
DOCK1
A A
U84
0.1U_0402_16V4Z~D
5
V+
8
V+
13
V+
18
V+
20
V+
30
V+
40
V+
42
V+
38
NC1+
37
NC1-
34
NO1+
33
NO1-
36
NC2+
35
NC2-
32
NO2+
31
NO2-
29
NC3+
28
NC3-
25
NO3+
24
NO3-
27
NC4+
26
NC4-
23
NO4+
22
NO4-
MAX4889ETO+_TQFN42_3P5x9~D
U14
4
VCC
10
VCC
18
VCC
27
VCC
38
VCC
50
VCC
56
VCC
2
A0
3
A1
7
A2
8
A3
11
A4
12
A5
14
A6
15
A7
19
A8
20
A9
17
SEL
1
GND
6
GND
9
GND
13
GND
16
GND
21
GND
24
GND
28
GND
33
GND
39
GND
44
GND
49
GND
53
GND
55
GND
TS3DV520ERHUR_QFN56_11X5~D
MAX4889
0B1
1B1
2B1
3B1
4B1
5B1
6B1
7B1
8B1
9B1
0B2
1B2
2B2
3B2
4B2
5B2
6B2
7B2
8B2
9B2
NC
NC
NC
NC
48
47
43
42
37
36
32
31
22
23
46
45
41
40
35
34
30
29
25
26
52
5
54
51
2
COM1+
3
COM1-
6
COM2+
7
COM2-
11
COM3+
12
COM3-
15
COM4+
16
COM4-
9
SEL
1
GND
4
GND
10
GND
14
GND
17
GND
19
GND
21
GND
39
GND
41
GND
43
GND
DAT_DDC2_CRT
CLK_DDC2_CRT
VSYNC_BUF
HSYNC_BUF
RED_CRT
GREEN_CRT
BLUE_CRT
DAT_DDC2_DOCK
CLK_DDC2_DOCK
VSYNC_DOCK
HSYNC_DOCK
RED_DOCK
GREEN_DOCK
BLUE_DOCK
+3.3V_RUN
C251
0.1U_0402_16V4Z~D
1
2
SW_LVDS_A0+
SW_LVDS_A0-
SW_LVDS_A1+
SW_LVDS_A1-
SW_LVDS_A2+
SW_LVDS_A2-
SW_LVDS_ACLK+
SW_LVDS_ACLK-
C252
4
BKT_GPIO1 <36>
DAT_DDC2_CRT <35>
CLK_DDC2_CRT <35>
VSYNC_BUF <35>
HSYNC_BUF <35>
RED_CRT <35>
GREEN_CRT <35>
BLUE_CRT <35>
DAT_DDC2_DOCK <31>
CLK_DDC2_DOCK <31>
VSYNC_DOCK <31>
HSYNC_DOCK <31>
RED_DOCK <31>
GREEN_DOCK <31>
BLUE_DOCK <31>
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
C253
C254
1
1
2
2
EDID signals drive low when BlackTop mode
LDDC_DATA_MCH<12>
LDDC_CLK_MCH<12>
2N7002DW-7-F_SOT363-6~D
+3.3V_RUN
4
2N7002DW-7-F_SOT363-6~D
To MB CRT CONN
To Docking CRT CONN
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
C255
1
2
0.1U_0402_16V4Z~D
C257
C256
1
1
2
2
10U_0805_10V4Z~D
0.1U_0402_16V4Z~D
C250
1
1
2
2
3
+3.3V_RUN_BKT_PWR
R196
Q111A
61
2
5
3
Q111B
Dual layout for Q33 and Q34
LCD POWER
2
D
6
2
1
12
R197
BATT_BLUE
BATT_YELLOW
BREATH_BLUE_LED
PNL_BKLT_CBL_DET#
LCD_TST<33>
BIA_PWM<12>
0.1U_0603_50V4Z~D
+3.3V_RUN_BKT_PWR
LVDS_CBL_DET#
LDDC_CLK_MCH_LVDS
LDDC_DATA_MCH_LVDS
SW_LVDS_A0SW_LVDS_A0+
SW_LVDS_A1SW_LVDS_A1+
SW_LVDS_A2SW_LVDS_A2+
SW_LVDS_ACLKSW_LVDS_ACLK+
+INV_PWR_SRC
Q31
SI3456BDV-T1-E3_TSOP6~D
D
S
4 5
G
3
0.1U_0402_25V4Z~D
100K_0402_5%~D@
C243
1
2
LCD_TST
BIA_PWM
C244
6
2
1
+LCDVDD
BATT_BLUE<38>
BATT_YELLOW<38>
BREATH_BLUE_LED<38>
+LCDVDD
2.2K_0402_5%~D
2.2K_0402_5%~D
12
12
R194
LDDC_DATA_MCH_LVDS
0.1U_0402_16V4Z~D
C249
1
2
Place close to JLVDS.8,9,10
+3.3V_RUN_BKT_PWR
LDDC_CLK_MCH_LVDS
0.1U_0402_16V4Z~D
C248
1
2
PNL_BKLT_CBL_DET#<22>
LCD_SMBDAT<34>
LVDS_CBL_DET#<22>
+INV_PWR_SRC
LCD_SMBCLK<34>
Place close to JLVDS.25
Q33
+PWR_SRC
40mil
1000P_0402_50V7K~D
R201
C247
1
2
BKT_GPIO14<36>
RUN_ON<21,27,33,37,45>
LCD_VCC_TEST_EN<33>
3
2
BKT_GPIO2<21,36>
ENVDD<12>
FDS4435_NL_SO8~D@
1
2
3
100K_0402_5%~D
12
PWR_SRC_ON
R202
1 2
100K_0402_5%~D
EN_INVPWR
1
D51
BAT54CW_SOT323~D
D50
2 1
RB751V_SOD323-2~D
3
2
8
7
6
5
4
Q35
2N7002W-7-F_SOT323-3~D
D
S
1 3
G
2
R1119
1 2
100K_0402_5%~D@
+LCDVDD +LCDVDD
R193
2N7002DW-7-F_SOT363-6~D
Q2A
EN_LCDPWR
1
D3
BAT54CW_SOT323~D
+INV_PWR_SRC
1
C246
0.1U_0603_50V4Z~D
2
470_0402_5%~D
12
61
2
2
40mil
+PWR_SRC
PWR_SRC_ON
+15V_ALW
100K_0402_5%~D
12
R195
1
O
I
G
Q32
DDTC124EUA-7-F_SOT323-3~D
3
Q34
SI3457DV-T1_TSOP6~D
S
4 5
G
3
+15V_ALW
12
R192
100K_0402_5%~D
2N7002DW-7-F_SOT363-6~D
3
Q2B
5
4
1
JLVDS
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
0.1U_0402_16V4Z~D
+3.3V_ALW
17
17
18
18
19
19
20
20
21
21
22
22
23
23
24
24
25
25
26
26
27
27
28
28
29
29
30
30
31
31
32
32
33
33
34
34
35
35
36
36
37
37
38
38
39
39
40
40
41
41
42
42
43
GND
44
GND
45
GND
46
GND
47
GND
48
GND
49
GND
50
GND
51
GND
JAE_FI-G42SB-VF25
12
C242
1
2
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
CRT SWITCH,LVDS MUX,LVDS CONN
LA-4291P
20 49Friday, Decemb er 07, 2007
1
of
0.1
Page 21
2
+3.3V_RUN_BKT_PWR Source
Q92
SI3456BDV-T1-E3_TSOP6~D
+15V_ALW
+3.3V_ALW2
12
R789
100K_0402_5%~D
D53
BAT54CW_SOT323~D
RUN_ON
3
2
D54
BAT54CW_SOT323~D
3
2
3.3V_RUN_BKT_PWR_EN
1
100K_0402_5%~D@
5V_RUN_BKT_PWR_EN
1
100K_0402_5%~D@
R1113
1 2
R1114
1 2
RUN_ON<20,27,33,37,45>
BKT_GPIO19<36>
+5V_RUN_BKT_PWR Source, for Touch Pad and Audio Amplifier
B B
BKT_GPIO4<36>
61
Q93A
2N7002DW-7-F_SOT363-6~D
2
+3.3V_ALW2
12
R791
100K_0402_5%~D
61
Q96A
2N7002DW-7-F_SOT363-6~D
2
5
+15V_ALW
5
+3.3V_ALW
12
R787
100K_0402_5%~D
3
Q93B
2N7002DW-7-F_SOT363-6~D
4
+5V_ALW
12
R790
100K_0402_5%~D
3
Q96B
2N7002DW-7-F_SOT363-6~D
4
D
6
S
45
2
1
G
3
1
C776
470P_0402_50V7K~D
2
Q95
SI3456BDV-T1-E3_TSOP6~D
D
6
S
45
2
1
G
3
1
C778
2200P_0402_50V7K~D
2
+3.3V_RUN_BKT_PWR
20K_0402_5%~D
10U_0805_10V4Z~D
12
R788
C775
1
2
+5V_RUN_BKT_PWR
20K_0402_5%~D
10U_0805_10V4Z~D
12
R792
C777
1
2
BKT_LVDS_RIN0-<20>
BKT_LVDS_RIN0+<20>
BKT_LVDS_RIN2-<20>
BKT_LVDS_RIN2+<20>
BKT_SMBCLK<34>
BKT_SMBDAT<34>
BKT_GPIO16<36>
BKT_GPIO7<36>
BKT_GPIO8<36>
BKT_GPIO9<36>
BKT_LVDS_RIN0BKT_LVDS_RIN0+
BKT_LVDS_RIN2BKT_LVDS_RIN2+
BKT_SMBCLK
BKT_SMBDAT
BKT_GPIO16
BKT_GPIO7
BKT_GPIO8
BKT_USBHBKT_USBH+
Enable BlackTop POWER
JBKTOP
1
PAID_IN
3
Odd Rin0-
5
Odd Rin0+
7
VSS
9
Odd Rin2-
11
Odd Rin2+
13
VSS
15
Even Rin0-
17
Even Rin0+
19
VSS
21
Even Rin2-
23
Even Rin2+
25
VSS
27
SMBCLK
29
SMBDATA
31
SMBALERT
33
RST-
35
USB_SEL_BLK
37
VSS
39
VSS
41
VDD 3.3v 5%
43
VDD 3.3v 5%
45
VDD 3.3v 5%
47
VSS
49
VSS
51
USB Host Port Data-
53
USB Host Port Data+
55
VSS
57
Reserved
59
Reserved
61
VSS
63
GPIO
65
SM CLK
67
SK DAT
69
SM Alert
71
VSS
73
Radio_OFF
75
Reserved
77
Reserved
79
Reserved
81
Reserved
83
Reserved
85
Reserved
87
Reserved
89
Reserved
91
Reserved
93
Reserved
95
Reserved
97
Reserved
99
VSS
101
GND
103
GND
MOLEX_55299-1078
+3.3V_RUN_WWAN_PWR Source, for WWAN
+15V_ALW
12
+3.3V_ALW2
12
R786
100K_0402_5%~D
D52
RUN_ON
BKT_GPIO15<36>
BAT54CW_SOT323~D
3
2
3.3V_RUN_WWAN_PWR_EN
1
R1115
1 2
100K_0402_5%~D@
61
Q90A
2N7002DW-7-F_SOT363-6~D
2
R784
100K_0402_5%~D
3
Q90B
2N7002DW-7-F_SOT363-6~D
5
4
For Biometric USB signals isolation
A A
H
Disconnect
L
L
FP_USBD+
FP_USBDBKT_USBBIO+
BKT_USBBIO-
FunctionOE#
D=1D
D=2D
FP_USBD+<32>
FP_USBD-<32>
S
X
L
H Select logic 1 Work from BlackTop
U86
1
2
3
4
TS3USB221RSER_QFN10_2x1P5~D
+3.3V_RUN_BKT_PWR +3.3V_RUN_BKT_PWR
VCC
1D+
1D2D+
2DGND5OE#
S
D+
D-
0.1U_0402_16V4Z~D
10
BKT_GPIO4
9
FP_SW_USBD+
8
FP_SW_USBD-
7
BKT_GPIO3
6
C784
1 2
2
FP_SW_USBD+ <35>
FP_SW_USBD- <35>
Q89
SI4336DY-T1-E3_SO8~D
8
7
5
For WWAN USB signals isolation
+3.3V_RUN_WWAN_PWR+3.3V_ALW
1
10U_0805_10V4Z~D
1
2
H
Disconnect
L
L
20K_0402_5%~D
12
R785
USBP5+
USBP5BKT_USBH+
BKT_USBH-
FunctionOE#
D=1D
U85
1
1D+
2
1D-
3
2D+
4
2DGND5OE#
TS3USB221RSER_QFN10_2x1P5~D
VCC
10
9
S
8
D+
7
D-
6
D=2D
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
2
36
C773
4
1
C774
470P_0402_50V7K~D
2
USBP5+<24>
USBP5-<24>
S
X
L
H Select logic 1 Work from BlackTop
BKT_GPIO2<20,36>
C783
1 2
0.1U_0402_16V4Z~D
BKT_GPIO4
WWAN_SW_USBD+
WWAN_SW _USBDBKT_GPIO3
+3.3V_ALW2
100K_0402_5%~D
12
R1066
61
Q112A
2N7002DW-7-F_SOT363-6~D
2
WWAN_SW_USBD+ <30>
WWAN_SW_USBD- <30>
BKT_GPIO3 <36>
+15V_ALW
12
R1065
100K_0402_5%~D
3
Q112B
2N7002DW-7-F_SOT363-6~D
5
4
1
+3.3V_ALW
+3.3V_BKT_PWR+3.3V_BKT_PWR
2
VSS
4
Odd Rin1-
6
Odd Rin1+
8
VSS
10
Odd Clk-
12
Odd Clk+
14
VSS
16
Even Rin1-
18
Even Rin1+
20
VSS
22
Even Clk-
24
Even Clk+
26
VSS
28
I2S_LRC
30
I2S_DIN
32
I2S_DOUT
34
I2S_SCLK
36
VSS
38
M_Clk
40
VSS
42
VDD 3.3v 5%
44
VDD 3.3v 5%
46
VDD 3.3v 5%
48
VSS
50
VSS
52
BioMetric
54
BioMetric
56
VSS
58
Reserved
60
Reserved
62
VSS
64
Reserved
66
Reserved
68
Reserved
70
Reserved
72
VSS
74
LID Closed
76
Reserved
78
Reserved
80
Reserved
82
Reserved
84
Reserved
86
Reserved
88
Reserved
90
Reserved
92
Reserved
94
Reserved
96
Reserved
98
Reserved
100
PAID_Out
102
GND
104
GND
Q36
SI3456BDV-T1-E3_TSOP6~D
D
6
S
2
1
G
3
C1347
1
2
45
470P_0402_50V7K~D
BKT_LVDS_RIN1BKT_LVDS_RIN1+
BKT_LVDS_CLKBKT_LVDS_CLK+
BKT_I2S_LRC
BKT_I2S_DO
BKT_I2S_SCLK
BKT_MCLK
BKT_USBBIOBKT_USBBIO+
BKT_LED
BKT_GPIO5BKT_GPIO9
BKT_GPIO6
+3.3V_BKT_PWR
10U_0805_10V4Z~D
1
R206
C258
2
BKT_LVDS_RIN1- <20>
BKT_LVDS_RIN1+ <20>
BKT_LVDS_CLK- <20>
BKT_LVDS_CLK+ <20>
BKT_I2S_LRC <26>
BKT_I2S_DO <26>
BKT_I2S_SCLK <26>
BKT_MCLK <26>
BKT_LED <35>
BKT_GPIO5 <36>
BKT_GPIO6 <36>
20K_0402_5%~D
12
Add BlackTop to ICH9M interface by USB signals when diagnostic mode
+3.3V_RUN_BKT_PWR
+3.3V_RUN_BKT_PWR
C785
1 2
0.1U_0402_16V4Z~D
BKT_GPIO3 EN_DIAG
5
1
P
NC
4
A2Y
G
U64
74LVC1G14GV_SOT753-5
3
BKT_USBH+ USBP5+
BKT_GPIO3 Logic 1 on diagnostic mode
C1351
12
0.1U_0402_16V4Z~D
U82
8
NC
VCC
HSD-2D-
6
D+
HSD+
7
GND
OE#
FSUSB31K8X_US8~D
1
USBP5-BKT_USBH-
3
5
4
DELL CONFIDENTIAL/PROPRIETARY
Title
Size Document Number Rev
1
Date: Sheet
Compal Electronics, Inc.
BlackTop POWER and CONN
LA-4291P
21 49Friday, Decemb er 07, 2007
0.1
of
Page 22
5
4
3
2
1
D D
C C
B B
+3.3V_RUN
R219 8.2K_0402_5%~D
1 2
R220 8.2K_0402_5%~D
1 2
R764 8.2K_0402_5%~D
1 2
R212 8.2K_0402_5%~D
1 2
R207 8.2K_0402_5%~D
1 2
R214 8.2K_0402_5%~D
1 2
R211 8.2K_0402_5%~D
1 2
R213 8.2K_0402_5%~D
1 2
R208 8.2K_0402_5%~D
1 2
R209 8.2K_0402_5%~D
1 2
R210 8.2K_0402_5%~D
1 2
+3.3V_RUN
R215 8.2K_0402_5%~D
1 2
R216 8.2K_0402_5%~D
1 2
R217 8.2K_0402_5%~D
1 2
R218 8.2K_0402_5%~D
1 2
R221 100K_0402_5%~D
1 2
R222 100K_0402_5%~D
1 2
R224 100K_0402_5%~D
1 2
R223 100K_0402_5%~D
1 2
PCI_REQ0#
PCI_REQ1#
ICH_GPIO54
PCI_IRDY#
PCI_DEVSEL#
PCI_PERR#
PCI_PLOCK#
PCI_SERR#
PCI_STOP#
PCI_TRDY#
PCI_FRAME#
PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#
FAN1_DET#
LVDS_CBL_DET#
PNL_BKLT_CBL_DET#
BT_DET#
PCI_AD[0..31]<29>
PCI_PIRQC#<29>
PCI_PIRQD#<29>
PCI_AD0
PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD6
PCI_AD7
PCI_AD8
PCI_AD9
PCI_AD10
PCI_AD11
PCI_AD12
PCI_AD13
PCI_AD14
PCI_AD15
PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20
PCI_AD21
PCI_AD22
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30
PCI_AD31
PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#
A11
B12
A10
C12
A8
A12
E10
C11
B9
D8
A4
E8
A3
D9
C8
C2
D7
B3
D11
B6
D5
D3
F4
E3
E4
B2
C4
C1
D1
E2
J4
H2
F1
F5
F2
There is a w eak integrated pull-up resistor on SPI_CS#1 pin
Boot BIOS Strap
PCI_GNT0# SPI_CS1#
*
0
1
11
Boot BIOS Destination
1
0
SPI
PCI
LPC
U79B
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
Interrupt I/F
PIRQA#
PIRQB#
PIRQC#
PIRQD#C7PIRQH#/GPIO5
ICH9-M SFF ES_FCBGA569~D
PCI
REQ0#
GNT0#
REQ1#/GPIO50
GNT1#/GPIO51
REQ2#/GPIO52
GNT2#/GPIO53
REQ3#/GPIO54
GNT3#/GPIO55
C/BE0#
C/BE1#
C/BE2#
C/BE3#
IRDY#
PCIRST#
DEVSEL#
PERR#
PLOCK#
SERR#
STOP#
TRDY#
FRAME#
PLTRST#
PCICLK
PIRQE#/GPIO2
PIRQF#/GPIO3
PIRQG#/GPIO4
PAR
PME#
G4
E1
A9
E12
B11
C10
D6
C6
D10
A5
E6
C9
C3
B1
T3
A7
D4
C5
H5
A6
A2
B8
A21
B5
T1
G3
G1
F3
H4
PCI_GNT0#
PCI_REQ0#
PCI_GNT0#
PCI_REQ1#
PCI_GNT1#
PCIE_MCARD2_DET#
ICH_GPIO53
ICH_GPIO54
ICH_GPIO55
PCI_C_BE0#
PCI_C_BE1#
PCI_C_BE2#
PCI_C_BE3#
PCI_IRDY#
PCI_PAR
PCI_PCIRST#
PCI_DEVSEL#
PCI_PERR#
PCI_PLOCK#
PCI_SERR#
PCI_STOP#
PCI_TRDY#
PCI_FRAME#
PCI_PLTRST#
CLK_PCI_ICH
ICH_PME#
LVDS_CBL_DET#
PNL_BKLT_CBL_DET#
BT_DET#
FAN1_DET#
12
R225
1K_0402_5%~D
PCI_REQ1# <29>
PCI_GNT1# <29>
PCIE_MCARD2_DET# <30>
T99
T100
PCI_C_BE0# <29>
PCI_C_BE1# <29>
PCI_C_BE2# <29>
PCI_C_BE3# <29>
PCI_IRDY# <29>
PCI_PAR <29>
PCI_DEVSEL# <29>
PCI_PERR# <29>
PCI_SERR# <29>
PCI_STOP# <29>
PCI_TRDY# <29>
PCI_FRAME# <29>
CLK_PCI_ICH <6>
ICH_PME# <33>
LVDS_CBL_DET# <20>
PNL_BKLT_CBL_DET# <20>
BT_DET# <30>
FAN1_DET# <19>
PCI_PCIRST#
PCI_PLTRST#
+3.3V_ALW_ICH
+3.3V_ALW_ICH
+3.3V_ALW_ICH
10
+3.3V_ALW_ICH
13
12
C259
0.1U_0402_16V4Z~D
14
U16A
1
P
IN1
OUT
2
IN2
G
74VHC08MTCX_NL_TSSOP14~D
7
14
U16B
4
P
IN1
OUT
5
IN2
G
74VHC08MTCX_NL_TSSOP14~D
7
14
U16C
P
IN1
OUT
9
IN2
G
74VHC08MTCX_NL_TSSOP14~D
7
14
U16D
P
IN1
OUT
IN2
G
74VHC08MTCX_NL_TSSOP14~D
7
3
6
8
11
PCI_RST#
PLTRST1#
PLTRST2#
PLTRST3#
Place closely pin U79.B5
CLK_PCI_ICH
R227
10_0402_5%~D@
1 2
CLK_ICH_TERM
1
C260
8.2P_0402_50V8J~D@
2
PCI_RST# <29,31>
PLTRST1# <10,35>
PLTRST2# <33,34>
PLTRST3# <30,32>
A A
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
ICH9M SFF(1/4)
LA-4291P
22 49Friday, Decemb er 07, 2007
1
0.1
of
Page 23
5
4
3
2
1
Short
Open
D D
Short
Open
+RTC_CELL +RTC_CELL
12
C C
ICH9M Internal VR Enable Strap
(Internal VR for VccSus1.05, VccSus1.5, VccCL1.5)
ICH_INTVRMEN
ICH9M LAN100 SLP Strap
(Internal VR for VccLAN1.05 and VccCL1.05)
ICH_LAN100_SLP
B B
Place close to U79
A A
Clear CMOS
Keep CMOS
TPM settingME_CLR
Clear ME RTC Registers
Keep ME RTC Registers
12
R228
332K_0402_1%~D
ICH_INTVRMEN LAN100_SLP
ICH_AZ_CODEC_SDOUT<26>
ICH_AZ_CODEC_SYNC<26>
ICH_AZ_CODEC_RST#<26>
ICH_AZ_CODEC_BITCLK<26>
ICH_AZ_MCH_SDOUT<10>
ICH_AZ_MCH_SYNC<10>
ICH_AZ_MCH_RST#<10>
ICH_AZ_MCH_BITCLK<10>
R767
332K_0402_1%~D
Low = Internal VR Disabled
High = Internal VR Enabled(Default)
Low = Internal VR Disabled
High = Internal VR Enabled(Default)
1
2
1
2
R244 33_0402_5%~D
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
R245 33_0402_5%~D
R247 33_0402_5%~D
R248 33_0402_5%~D
C266
27P_0402_50V8J~D@
R1033 33_0402_5%~D
R1034 33_0402_5%~D
R1035 33_0402_5%~D
R1036 33_0402_5%~D
C1290
27P_0402_50V8J~D@
+RTC_CELL
1
1
C263
1 2
1U_0603_10V4Z~D
ICH_AZ_SDOUT
ICH_AZ_SYNC
ICH_AZ_RST#
ICH_AZ_BITCLK
ICH_AZ_SDOUT
ICH_AZ_SYNC
ICH_AZ_RST#
ICH_AZ_BITCLK
R234 20K_0402_5%~D
R235 20K_0402_5%~D
R237 1M_0402_5%~D
ME_CLR
2
2
PSATA_IRX_DTX_N0_C<35>
PSATA_IRX_DTX_P0_C<35>
*
There is a weak integrated pull-up resistor on ICH_RSVD_TP3 pin
There is a weak integrated pull-down resistor on HDA_SDOUT pin
C261
15P_0402_50V8J~D
12
32.768KHZ_12.5PF_1TJE125DP1~D
1 2
1 2
1 2
1
1
C264
PSATA_ITX_DRX_N0<35> CLK_PCIE_SATA# <6>
PSATA_ITX_DRX_P0<35>
C262
15P_0402_50V8J~D
CMOS_CLR
2
1 2
1U_0603_10V4Z~D
+1.5V_RUN_PCIE_ICH
12
Y1
R232
12
2
+3.3V_ALW_ICH
C271 0.01U_0402_16V7K~D
C272 0.01U_0402_16V7K~D
0_0402_5%~D
1 2
LAN_RSTSYNC<28>
LAN_TX0<28>
LAN_TX1<28>
LAN_TX2<28>
R230 10K_0402_5%~D
R243 24.9_0402_1%~D
ICH_AZ_CODEC_SDIN0<26>
ICH_AZ_MCH_SDIN2<10>
SATA_ACT#_R<38>
12
12
LAN_CLK<28>
LAN_RX0<28>
LAN_RX1<28>
LAN_RX2<28>
ME_FWP<33>
12
1 2
ICH_RTCX1
R231
10M_0402_5%~D
ICH_RTCX2
ICH_RTCRST#
SRTCRST#
INTRUDER#
ICH_INTVRMEN
LAN100_SLP
LAN_CLK
LAN_RSTSYNC
LAN_RX0
LAN_RX1
LAN_RX2
LAN_TX0
LAN_TX1
LAN_TX2
12
ICH_AZ_BITCLK
ICH_AZ_SYNC
ICH_AZ_RST#
ICH_AZ_CODEC_SDIN0
ICH_AZ_MCH_SDIN2
ICH_AZ_SDOUT
ME_FWP
RTC_BAT_DET#
SATA_ACT#_R
PSATA_IRX_DTX_N0_C
PSATA_IRX_DTX_P0_C
PSATA_ITX_DRX_N0_C
PSATA_ITX_DRX_P0_C
U79A
F25
RTCX1
G25
RTCX2
G24
RTCRST#
C24
SRTCRST#
C23
INTRUDER#
E25
INTVRMEN
D25
LAN100_SLP
G22
GLAN_CLK
D14
LAN_RSTSYNC
A14
LAN_RXD0
D12
LAN_RXD1
B14
LAN_RXD2
D13
LAN_TXD0
C13
LAN_TXD1
A13
LAN_TXD2
D15
GPIO56
H22
GLAN_COMPI
H21
GLAN_COMPO
AE7
HDA_BIT_CLK
AB7
HDA_SYNC
AA7
HDA_RST#
AB6
HDA_SDIN0
AE6
HDA_SDIN1
AC6
HDA_SDIN2
AA5
HDA_SDIN3
AC7
HDA_SDOUT
AD8
HDA_DOCK_EN#/GPIO33
AB8
HDA_DOCK_RST#/GPIO34
AC9
SATALED#
AE14
SATA0RXN
AD14
SATA0RXP
AC15
SATA0TXN
AD15
SATA0TXP
AD13
SATA1RXN
AC13
SATA1RXP
AA14
SATA1TXN
AB14
SATA1TXP
ICH9-M SFF ES_FCBGA569~D
FWH0/LAD0
FWH1/LAD1
FWH2/LAD2
FWH3/LAD3
FWH4/LFRAME#
RTCLAN / GLAN
LPCCPU
LDRQ0#
LDRQ1#/GPIO23
A20GATE
A20M#
DPRSTP#
DPSLP#
FERR#
CPUPWRGD
IGNNE#
RCIN#
STPCLK#
THRMTRIP#
SATA4RXN
SATA4RXP
IHDA
SATA4TXN
SATA4TXP
SATA5RXN
SATA5RXP
SATA5TXN
SATA5TXP
SATA_CLKN
SATA_CLKP
SATA
SATARBIAS#
SATARBIAS
INIT#
INTR
SMI#
TP11
LPC_LAD0
H3
LPC_LAD1
J3
LPC_LAD2
K5
LPC_LAD3
L3
LPC_LFRAME#
J2
LPC_LDRQ0#
H1
LPC_LDRQ1#
J1
SIO_A20GATE
N3
H_A20M#
AB23
H_DPRSTP#
AE23
H_DPSLP#
AE24
R242 56_0402_5%~D
AD25
H_PWRGOOD
AE22
H_IGNNE#
AD23
H_INIT#
AE21
H_INTR
AD24
SIO_RCIN#
L1
H_NMI
AD21
NMI
AC21
AC25
AC23
AC22
AD12
AE12
AB12
AA12
AC11
AD11
AB10
AA10
AC16
AB16
AD10
AE10
H_SMI#
H_STPCLK#
THRMTRIP_ICH#
ICH_TP11
ESATA_ITX_DRX_N4_C
ESATA_ITX_DRX_P4_C
SATA_ITX_DRX_N3_C
SATA_ITX_DRX_P3_C
CLK_PCIE_SATA#
CLK_PCIE_SATA
24.9_0402_1%~D
LPC_LAD0 <32,33,34>
LPC_LAD1 <32,33,34>
LPC_LAD2 <32,33,34>
LPC_LAD3 <32,33,34>
LPC_LFRAME# <32,33,34>
LPC_LDRQ0# <33>
LPC_LDRQ1# <33>
SIO_A20GATE <34>
H_A20M# <7>
12
H_PWRGOOD <8>
H_IGNNE# <7>
H_INIT# <7>
H_INTR <7>
SIO_RCIN# <34>
H_NMI <7>
H_SMI# <7>
H_STPCLK# <7>
R246 56_0402_5%~D
T43
C267 0.01U_0402_16V7K~D
C268 0.01U_0402_16V7K~D
C269 0.01U_0402_16V7K~D
C270 0.01U_0402_16V7K~D
CLK_PCIE_SATA <6>
12
R253
Within 500 mils
RTC BATT connector detect circuit
+3.3V_RUN
XOR Chain Entrance Strap
DESCRIPTIONICH_RSVD_TP3 HDA SDOUT
00
11
RSVD
10
Enter XOR Chain
01
Normal Operation (Default)
Set PCIE port config bit 1
12
R256
1K_0402_5%~D@
ICH_AZ_SDOUT
ICH_RSVD_TP3
12
R259
1K_0402_5%~D@
ICH_RSVD_TP3 <24>
RTC_BAT_DET#
RTC_BAT_DET_R#<40>
1 2
0_0402_5%~D@
12
12
12
12
12
R1102
+3.3V_RUN
SIO_A20GATE
SIO_RCIN#
12
R239
H_FERR# <7>
H_FERR#
+1.05V_VCCP
100K_0402_5%~D
12
+COINCELL
R1099
1 3
2N7002W-7-F_SOT323-3~D
R233
10K_0402_5%~D
R236
10K_0402_5%~D
+1.05V_VCCP
56_0402_1%~D@
56_0402_1%~D@
12
R240
H_DPRSTP# <8,10,43>
H_DPSLP# <8>
R241
56_0402_5%~D
ESATA_IRX_DTX_N4_C <35>
ESATA_IRX_DTX_P4_C <35>
ESATA_ITX_DRX_N4 <35>
ESATA_ITX_DRX_P4 <35>
SATA_SBRX_DTX_N3_C <31>
SATA_SBRX_DTX_P3_C <31>
SATA_SBTX_C_DRX_N3 <31>
SATA_SBTX_C_DRX_P3 <31>
R1100
1 2
2
G
1M_0402_5%~D
D
S
Q121
+3.3V_RUN
12
12
+1.05V_VCCP
12
12
R1101
1K_0402_5%~D
DELL CONFIDENTIAL/PROPRIETARY
CMOS settingCMOS_CLR
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
ICH9M SFF(2/4)
LA-4291P
23 49Friday, Decemb er 07, 2007
1
0.1
of
Page 24
5
+3.3V_M +3.3V_ALW_ICH
2.2K_0402_5%~D
2.2K_0402_5%~D
2.2K_0402_5%~D
12
12
R318
R319
MEM_SDATA<17,18>
D D
MEM_SCLK<17,18>
+3.3V_ALW_ICH
1 2
R289 10K_0402_5%~D
1 2
R268 10K_0402_5%~D
1 2
R271 10K_0402_5%~D
1 2
R274 10K_0402_5%~D
1 2
R293 10K_0402_5%~D
1 2
R277 10K_0402_5%~D
1 2
R287 10K_0402_5%~D
1 2
R1116 100K_0402_5%~D
1 2
R1117 100K_0402_5%~D
1 2
R278 100K_0402_5%~D
1 2
C C
B B
R295 100K_0402_5%~D
+3.3V_RUN
1 2
R267 10K_0402_5%~D
1 2
R265 8.2K_0402_5%~D
1 2
R282 10K_0402_5%~D
1 2
R794 100K_0402_5%~D
+3.3V_RUN
12
R301
8.2K_0402_5%~D
CLKRUN#
12
R303
10_0402_5%~D@
Option to "disable" CLKRUN.
Pulling it down will keep the CLK running.
+3.3V_M
ICH_GPIO60
AMT_SMBCLK
AMT_SMBDAT
SMB_ALERT#
ICH_PCIE_W AKE#
SIO_EXT_SMI#
KYBRD_BKT_DET#
IO_BD_DET#
LED_BD_DET#
BIO_DET#
IRQ_SERIRQ
RSV_THRM#
SIO_EXT_SCI#
Q3A
2N7002DW-7-F_SOT363-6~D
2
5
4
Q3B
2N7002DW-7-F_SOT363-6~D
ICH_RI#
USB_MCARD1_DET#<30>
+3.3V_RUN
TPM_ID
MINIWWAN (Mini Card 2)
MINIWLAN (Mini Card 1)
The same as MDC connector and for TAA module only
SPI_CS0#
SPI_DIN
SPI_WP#
JTAA
12
12
10
10
8
8
6
6
4
4
2
2
TYCO_1-1734054-2~D1@
+3.3V_LAN
11
11
SPI_HOLD#
9
9
7
7
SPI_CLK
5
5
3
3
SPI_DO
1
1
2.2K_0402_5%~D
12
12
R261
R264
61
3
R304
1 2
100K_0402_5%~D@
R306
1 2
1K_0402_5%~D@
SIO_EXT_WAKE#<33>
USB_MCARD2_DET#<30>
1 2
R292 100K_0402_5%~D
1 2
R272 100K_0402_5%~D
1 2
R275 100K_0402_5%~D
Express card
GIGA LAN
ICH_SMBDATA
ICH_SMBCLK
ITP_DBRESET#
DMI_TERM_SEL
47P_0402_50V8J~D@
C277
C278
1
2
SNIFFER_DET#
PCIE_IRX_WANTX_N1<30>
PCIE_IRX_WANTX_P1<30>
PCIE_ITX_WANRX_N1_C<30>
PCIE_ITX_WANRX_P1_C<30>
PCIE_IRX_WLANTX_N2<30>
PCIE_IRX_WLANTX_P2<30>
PCIE_ITX_WLANRX_N2_C<30>
PCIE_ITX_WLANRX_P2_C<30>
PCIE_IRX_GLANTX_N6<28>
PCIE_IRX_GLANTX_P6<28>
PCIE_ITX_GLANRX_N6_C<28>
PCIE_ITX_GLANRX_P6_C<28>
SPI Flash ROM: 208 mil SO8
+3.3V_LAN
5
R320
3.3K_0402_5%~D
U12
1 2
1
/CS
2
DO
3
/WP
4
GND
W25X32VSSIG_SO8~D2@
A A
SPI_CS0#
ICH_SPI_DIN
R322
1 2
15_0402_5%~D
SPI_DIN
SPI_WP#
VCC
/HOLD
CLK
+3.3V_LAN
8
7
6
5
DIO
C293
1 2
0.1U_0402_16V4Z~D
R321
3.3K_0402_5%~D
1 2
SPI_HOLD#
SPI_CLK
SPI_DO
R299
1 2
4.7K_0402_5%~D
47P_0402_50V8J~D@
C279
1
2
KB_DET#
HDD_DET#
PCIE_IRX_EXPTX_N4<35>
PCIE_IRX_EXPTX_P4<35>
PCIE_ITX_EXPRX_N4_C<35>
PCIE_ITX_EXPRX_P4_C<35>
4
ICH_SMBCLK
ICH_SMBDATA
ICH_GPIO60
T97
T46
T49
T50
SPKR<26>
T51
T52
T53
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
45
36
27
18
45
36
27
18
AMT_SMBCLK
AMT_SMBDAT
ICH_RI#
SUS_STAT#/LPCPD#
ITP_DBRESET#
PM_SYNC#
SMB_ALERT#
H_STP_PCI#
H_STP_CPU#
CLKRUN#
ICH_PCIE_W AKE#
IRQ_SERIRQ
RSV_THRM#
IMVP_PWRGD
ICH_TP12
SIO_EXT_SCI#
TPM_ID
SIO_EXT_WAKE#
SIO_EXT_SMI#
LAN_DISABLE#
KYBRD_BKT_DET#
SNIFFER_DET#
ICH_GPIO20
IO_BD_DET#
LED_BD_DET#
SATA_CLKREQ#
KB_DET#
WPAN_RADIO_DIS_MINI#
HDD_DET#
DMI_TERM_SEL
BIO_DET#
SPKR
MCH_ICH_SYNC#
ICH_RSVD_TP3
ICH_TP8
ICH_TP9
ICH_TP10
USB_OC0#<35>
ESATA_USB_OC#<35>
USB_OC0#
ESATA_USB_OC#
USB_OC4#
USB_OC5#
USB_OC6#
USB_OC7#
USB_OC8#
USB_OC9#
USB_OC10#
PCIE_IRX_WANTX_N1
PCIE_IRX_WANTX_P1
PCIE_ITX_WANRX_N1
PCIE_ITX_WANRX_P1
PCIE_IRX_WLANTX_N2
PCIE_IRX_WLANTX_P2
PCIE_ITX_WLANRX_N2
PCIE_ITX_WLANRX_P2
PCIE_IRX_EXPTX_N4
PCIE_IRX_EXPTX_P4
PCIE_ITX_EXPRX_N4
PCIE_ITX_EXPRX_P4
PCIE_IRX_GLANTX_N6
PCIE_IRX_GLANTX_P6
PCIE_ITX_GLANRX_N6
PCIE_ITX_GLANRX_P6
ICH_SPI_CLKSPI_CLK
ICH_SPI_DO
ICH_SPI_DIN
USB_OC0#
ESATA_USB_OC# USBP6+
USB_OC4#
USB_OC5#
USB_OC6#
USB_OC7#
USB_OC8#
USB_OC9#
USB_OC10#
USBRBIAS
12
Within 500 mils
AMT_SMBCLK<34>
AMT_SMBDAT<34>
ITP_DBRESET#<7>
PM_SYNC#<10>
H_STP_PCI#<6>
H_STP_CPU#<6>
CLKRUN#<29,33,34>
ICH_PCIE_WAKE#<33>
IRQ_SERIRQ<29,32,33,34>
IMVP_PWRGD<33,43,44>
SIO_EXT_SCI#<34>
SIO_EXT_SMI#<34>
LAN_DISABLE#<28>
KYBRD_BKT_DET#<36>
SNIFFER_DET#<35>
47P_0402_50V8J~D@
1
2
IO_BD_DET#<35>
LED_BD_DET#<38>
SATA_CLKREQ#<6>
KB_DET#<36>
HDD_DET#<35>
BIO_DET#<35>
MCH_ICH_SYNC#<10>
ICH_RSVD_TP3<23>
C280 0.1U_0402_10V7K~D
C282 0.1U_0402_10V7K~D
C283 0.1U_0402_10V7K~D
C284 0.1U_0402_10V7K~D
C287 0.1U_0402_10V7K~D
C288 0.1U_0402_10V7K~D
C291 0.1U_0402_10V7K~D
C292 0.1U_0402_10V7K~D
R323 15_0402_5%~D
SPI_CS0# ICH_SPI_CS0#
R316 15_0402_5%~D
SPI_DO
R324 15_0402_5%~D
+3.3V_ALW_ICH
4
RP13
10K_1206_8P4R_5%~D
RP14
10K_1206_8P4R_5%~D
1 2
R314
10K_0402_5%~D
U79C
C18
SMBCLK
C15
SMBDATA
B21
LINKALERT#/GPIO60/CLGPIO4
E18
SMLINK0
A24
SMLINK1
C20
RI#
T5
SUS_STAT#/LPCPD#
C25
SYS_RESET#
L2
PMSYNC#/GPIO0
A23
SMBALERT#/GPIO11
B15
STP_PCI#/GPIO15
A20
STP_CPU#/GPIO25
M5
CLKRUN#/GPIO32
C21
WAKE#
L4
SERIRQ
AD20
THRM#
B24
VRMPWRGD
A19
TP12
AE16
GPIO1
AE18
GPIO6
AD18
GPIO7
B25
GPIO8
C14
GPIO12
D20
GPIO13
AE17
GPIO17
K3
GPIO18
AC8
GPIO20
AC19
SCLOCK/GPIO22
D17
GPIO27
E20
GPIO28
M4
SATACLKREQ#/GPIO35
AB18
SLOAD/GPIO38
AC18
SDATAOUT0/GPIO39
AB19
SDATAOUT1/GPIO48
AC20
GPIO49
A16
GPIO57/CLGPIO5
K4
SPKR
AB20
MCH_SYNC#
C19
TP3
AB17
TP8
AC17
TP9
AD17
TP10
ICH9-M SFF ES_FCBGA569~D
22.6_0402_1%~D
R325
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
SMB
SYS GPIO
GPIO
MISC
U79D
T25
PERN1
T24
PERP1
R24
PETN1
R23
PETP1
P25
PERN2
P24
PERP2
P21
PETN2
P22
PETP2
N23
PERN3
N24
PERP3
M21
PETN3
M22
PETP3
M25
PERN4
M24
PERP4
L24
PETN4
L23
PETP4
K24
PERN5
K25
PERP5
K21
PETN5
K22
PETP5
H24
PERN6/GLAN_RXN
H25
PERP6/GLAN_RXP
J24
PETN6/GLAN_TXN
J23
PETP6/GLAN_TXP
E24
SPI_CLK
E23
SPI_CS0#
F23
SPI_CS1#/GPIO58/CLGPIO6
F22
SPI_MOSI
G23
SPI_MISO
P4
OC0#/GPIO59
N4
OC1#/GPIO40
N1
OC2#/GPIO41
P5
OC3#/GPIO42
P1
OC4#/GPIO43
P2
OC5#/GPIO29
M3
OC6#/GPIO30
M2
OC7#/GPIO31
P3
OC8#/GPIO44
R1
OC9#/GPIO45
R4
OC10#/GPIO46
R2
OC11#/GPIO47
AE5
USBRBIAS
AD5
USBRBIAS#
ICH9-M SFF ES_FCBGA569~D
3
SATA0GP/GPIO21
SATA1GP/GPIO19
SATA4GP/GPIO36
SATA5GP/GPIO37
SATA
GPIO
Clocks
S4_STATE#/GPIO26
DPRSLPVR/GPIO16
Power MGTController Link
CK_PWRGD
MEM_LED/GPIO24
GPIO10/SUS_PWR_ACK
GPIO14/AC_PRESENT
WOL_EN/GPIO9
DMI0RXN
DMI0RXP
DMI0TXN
DMI0TXP
DMI1RXN
DMI1RXP
DMI1TXN
DMI1TXP
DMI2RXN
DMI2RXP
DMI2TXN
DMI2TXP
DMI3RXN
DMI3RXP
DMI3TXN
DMI3TXP
DMI_CLKN
PCI-Express
DMI_CLKP
Direct Media Interface
DMI_ZCOMP
DMI_IRCOMP
USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4N
USBP4P
USBP5N
SPI
USBP5P
USBP6N
USB
USBP6P
USBP7N
USBP7P
USBP8N
USBP8P
USBP9N
USBP9P
USBP10N
USBP10P
USBP11N
USBP11P
CLK14
CLK48
SUSCLK
SLP_S3#
SLP_S4#
SLP_S5#
PWROK
BATLOW#
PWRBTN#
LAN_RST#
RSMRST#
CLPWROK
SLP_M#
CL_CLK0
CL_CLK1
CL_DATA0
CL_DATA1
CL_VREF0
CL_VREF1
CL_RST0#
CL_RST1#
V25
V24
U24
U23
W23
W24
V21
V22
Y24
Y25
Y21
Y22
AB24
AB25
AA23
AA24
T21
T22
AB21
AB22
AE2
AD1
AD3
AD4
AC2
AC3
AC5
AB4
AB2
AB1
AA3
AA2
Y1
Y2
W2
W3
V1
V2
Y5
Y4
U3
U2
V4
V5
AE19
AA18
AE20
AA20
K1
AB5
R3
D18
B20
D16
E14
D23
M1
C16
U4
D22
D19
U1
T4
B23
C22
A18
E22
B18
F21
A17
C17
B17
A22
E16
A15
D21
R262
1 2
8.2K_0402_5%~D
SPEAKER_DET#
AUDIO_BD_DET#
1394_DET#
CLK_ICH_14M
CLK_ICH_48M
ICH_SUSCLK
SIO_SLP_S3#
SIO_SLP_S4#
SIO_SLP_S5#
ICH_GPIO26
RESET_OUT
DPRSLPVR
ICH_BATLOW#
SIO_PWRBTN#
ICH_LAN_RST#
ICH_RSMRST#
CLK_PWRGD
ICH_CL_PWROK
SIO_SLP_M#
CL_CLK0
ICH_CL_CLK1
CL_DATA0
ICH_CL_DATA1
+CL_VREF0_ICH
+CL_VREF1_ICH
CL_RST0#
ICH_CL_RST1#
PCIE_MCARD1_DET#
ME_SUS_PWR_ACK
AC_PRESENT
ME_WOL_EN
R305
1 2
100K_0402_5%~D@
DMI_MTX_IRX_N0
DMI_MTX_IRX_P0
DMI_MRX_ITX_N0
DMI_MRX_ITX_P0
DMI_MTX_IRX_N1
DMI_MTX_IRX_P1
DMI_MRX_ITX_N1
DMI_MRX_ITX_P1
DMI_MTX_IRX_N2
DMI_MTX_IRX_P2
DMI_MRX_ITX_N2
DMI_MRX_ITX_P2
DMI_MTX_IRX_N3
DMI_MTX_IRX_P3
DMI_MRX_ITX_N3
DMI_MRX_ITX_P3
CLK_PCIE_ICH#
CLK_PCIE_ICH
DMI_IRCOMP
USBP0USBP0+
USBP3USBP3+
USBP4USBP4+
USBP5USBP5+
USBP6-
USBP7USBP7+
USBP8USBP8+
USBP9USBP9+
USBP10USBP10+
2
+3.3V_RUN
SPEAKER_DET# <27>
AUDIO_BD_DET# <35>
1394_DET# <35>
CLK_ICH_14M <6>
CLK_ICH_48M <6>
T44
SIO_SLP_S3# <33>
SIO_SLP_S4# <10,34>
SIO_SLP_S5# <34>
T45
RESET_OUT <10,34>
DPRSLPVR <10,43>
R290 8.2K_0402_5%~D
+3.3V_ALW_ICH
12
SIO_PWRBTN# <34>
ICH_LAN_RST# <34>
ICH_RSMRST# <34>
CLK_PWRGD <6>
ICH_CL_PWROK <10,34>
SIO_SLP_M# <34>
CL_CLK0 <10>
ICH_CL_CLK1 <30>
CL_DATA0 <10>
ICH_CL_DATA1 <30>
CL_RST0# <10>
ICH_CL_RST1# <30>
PCIE_MCARD1_DET# <30>
ME_SUS_PWR_ACK <34>
AC_PRESENT <34>
ME_WOL_EN <34>
CRB pop
DMI_MTX_IRX_N0 <10>
DMI_MTX_IRX_P0 <10>
DMI_MRX_ITX_N0 <10>
DMI_MRX_ITX_P0 <10>
DMI_MTX_IRX_N1 <10>
DMI_MTX_IRX_P1 <10>
DMI_MRX_ITX_N1 <10>
DMI_MRX_ITX_P1 <10>
DMI_MTX_IRX_N2 <10>
DMI_MTX_IRX_P2 <10>
DMI_MRX_ITX_N2 <10>
DMI_MRX_ITX_P2 <10>
DMI_MTX_IRX_N3 <10>
DMI_MTX_IRX_P3 <10>
DMI_MRX_ITX_N3 <10>
DMI_MRX_ITX_P3 <10>
CLK_PCIE_ICH# <6>
CLK_PCIE_ICH <6>
R313
1 2
24.9_0402_1%~D
USBP3- <35>
USBP3+ <35>
USBP4- <30>
USBP4+ <30>
USBP5- <21>
USBP5+ <21>
USBP6- <30>
USBP6+ <30>
USBP7- <35>
USBP7+ <35>
USBP8- <31>
USBP8+ <31>
USBP9- <31>
USBP9+ <31>
USBP10- <32>
USBP10+ <32>
2
+1.5V_RUN_PCIE_ICH
----->Right Side Top
----->Left Side Top
----->WLAN
----->WWAN
----->BT
----->Express Card
----->DOCK
----->DOCK
----->BIO
1
SPEAKER_DET#
AUDIO_BD_DET#
1394_DET#
ME_SUS_PWR_ACK
RESET_OUT
ICH_RSMRST#
ICH_CL_PWROK
ME_WOL_EN
+3.3V_ALW_ICH
ICH_LAN_RST#
+CL_VREF0_ICH
+CL_VREF1_ICH
C290
C289
R276 100K_0402_5%~D
1 2
R273 100K_0402_5%~D
1 2
R269 100K_0402_5%~D
1 2
R279 10K_0402_5%~D
1 2
R285 10K_0402_5%~D
1 2
R288 10K_0402_5%~D
1 2
R280 100K_0402_5%~D
1 2
R291 100K_0402_5%~D
1 2
Place closely pin U79.K1
10K_0402_5%~D
12
R297
+3.3V_M
3.24K_0402_1%~D
12
R309
Place closely pin U79.AB5
453_0402_1%~D
0.1U_0402_16V4Z~D
12
R311
1
2
+3.3V_WLAN
3.24K_0402_1%~D
12
R308
0.1U_0402_16V4Z~D
453_0402_1%~D
12
R310
1
2
CLK_ICH_14M
12
R298
1
C276
2
CLK_ICH_48M
12
R307
1
C281
2
+3.3V_RUN
+3.3V_ALW_ICH
10_0402_5%~D@
4.7P_0402_50V8C~D@
10_0402_5%~D@
4.7P_0402_50V8C~D@
Place close to ICH9M
+3.3V_SUS
C1348
1 2
0.1U_0402_16V4Z~D
USBP0USBP0+
U93
8
6
7
FSUSB31K8X_US8~D
VCC
HSD-2DHSD+
GND
OE#
1
NC
3
5
D+
4
SW_USBP0- <35>
SW_USBP0+ <35>
DELL CONFIDENTIAL/PROPRIETARY
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
ICH9M SFF(3/4)
LA-4291P
24 49Friday, Decemb er 07, 2007
1
of
0.1
Page 25
5
4
3
2
1
+RTC_CELL
0.1U_0402_16V4Z~D
+3.3V_RUN+5V_RUN
21
12
+3.3V_ALW_ICH+5V_ALW
12
D8
RB751S40T1_SOD523-2~D
ICH_V5REF_RUN
1
C300
1U_0603_10V6K~D
2
21
D9
RB751S40T1_SOD523-2~D
ICH_V5REF_SUS
1
C307
1U_0603_10V6K~D
2
R332
1
1 2
10_0805_5%~D
D7
MMBD4148-7-F_SOT23-3~D
+1.5V_RUN
1UH_GLF2012T1R0M_20%_0805~D
5
+1.5V_RUN
BLM21PG600SN1D_0805~D
+1.5V_RUN +1.5V_RUN_SATAPLL
+1.5V_RUN
+3.3V_LAN
C331
1
2
L17
1 2
R333
100_0402_5%~D
D D
R335
100_0402_5%~D
+1.05V_VCCP
C C
B B
A A
2
3
C296
+1.5V_RUN_PCIE_ICH
L13
1 2
L16
1 2
10UH_LB2012T100MR_20%_0805~D
+1.5V_RUN
C329
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
10U_0805_4VAM~D
C336
C335
1
2
C297
1
2
C301
+1.5V_RUN
0.1U_0402_16V4Z~D
C328
1
2
C334
1 2
2.2U_0603_6.3V6K~D
+1.5V_RUN_PCIE_ICH
1
2
0.1U_0402_16V4Z~D
ICH_V5REF_RUN
1
ICH_V5REF_SUS
2
220U_D2_4VY_R15M~D
10U_0603_6.3V6M~D
1
C302
C303
1
+
2
2
10U_0805_4VAM~D
C315
1
2
1
C322
0.1U_0402_16V4Z~D
2
C323
C786
0.1U_0402_16V4Z~D
1
2
VCCLAN1.05_INT_ICH
+VCCGLANPLL
10U_0805_4VAM~D
C337
1
+3.3V_RUN
2
4
10U_0603_6.3V6M~D
1
2
0.1U_0402_16V4Z~D
C316
1
2
0.1U_0402_16V4Z~D
1
2
0.1U_0402_16V4Z~D
1
2
G17
G7
U7
J19
K18
K19
L18
L19
M18
M19
N18
N19
P18
R18
T18
T19
U18
U19
W17
U13
V13
W13
U12
V12
W12
W10
U15
V15
W18
G9
H9
V11
U11
U8
T9
U9
G11
H11
G12
H13
J17
H19
J18
K16
U79F
VCCRTC
V5REF
V5REF_SUS
VCC1_5_B[01]
VCC1_5_B[02]
VCC1_5_B[03]
VCC1_5_B[04]
VCC1_5_B[05]
VCC1_5_B[06]
VCC1_5_B[07]
VCC1_5_B[08]
VCC1_5_B[09]
VCC1_5_B[10]
VCC1_5_B[11]
VCC1_5_B[12]
VCC1_5_B[13]
VCC1_5_B[14]
VCC1_5_B[15]
VCCSATAPLL
VCC1_5_A[01]
VCC1_5_A[02]
VCC1_5_A[03]
VCC1_5_A[04]
VCC1_5_A[05]
VCC1_5_A[06]
VCC1_5_A[07]
VCC1_5_A[08]
VCC1_5_A[09]
VCC1_5_A[10]
VCC1_5_A[11]
VCC1_5_A[12]
VCC1_5_A[13]
VCC1_5_A[14]
VCCUSBPLL
VCC1_5_A[15]
VCC1_5_A[16]
VCCLAN1_05[1]
VCCLAN1_05[2]
VCCLAN3_3[1]
VCCLAN3_3[2]
VCCGLANPLL
VCCGLAN1_5[1]
VCCGLAN1_5[2]
VCCGLAN3_3
ICH9-M SFF ES_FCBGA569~D
CORE
VCCA3GP ATXARX USB CORE
VCCPSUSVCCPUSB
GLAN POWER
VCC1_05[01]
VCC1_05[02]
VCC1_05[03]
VCC1_05[04]
VCC1_05[05]
VCC1_05[06]
VCC1_05[07]
VCC1_05[08]
VCC1_05[09]
VCC1_05[10]
VCC1_05[11]
VCC1_05[12]
VCC1_05[13]
VCC1_05[14]
VCC1_05[15]
VCC1_05[16]
VCCDMIPLL
VCC_DMI[1]
VCC_DMI[2]
V_CPU_IO[1]
V_CPU_IO[2]
VCC3_3[01]
VCC3_3[02]
VCC3_3[03]
VCC3_3[04]
VCC3_3[05]
VCC3_3[06]
VCC3_3[07]
VCC3_3[08]
VCCP_CORE
PCI
VCCSUSHDA
VCCSUS1_05[1]
VCCSUS1_05[2]
VCCSUS1_5[1]
VCCSUS1_5[2]
VCCSUS3_3[01]
VCCSUS3_3[02]
VCCSUS3_3[03]
VCCSUS3_3[04]
VCCSUS3_3[05]
VCCSUS3_3[06]
VCCSUS3_3[07]
VCCSUS3_3[08]
VCCSUS3_3[09]
VCCSUS3_3[10]
VCCSUS3_3[11]
VCCSUS3_3[12]
VCCSUS3_3[13]
VCCSUS3_3[14]
VCCSUS3_3[15]
VCCSUS3_3[16]
VCCCL1_05
VCCCL3_3[1]
VCCCL3_3[2]
+1.05V_VCCP
L11
L12
L13
L14
C298
L15
M11
M15
N11
N15
P11
P15
R11
R12
R13
R14
R15
+VCCDMIPLL
P19
+VCC_DMI_ICH
T17
U17
V16
U16
V18
AE9
+3.3V_RUN
AA9
0.1U_0402_16V4Z~D
V14
W14
G8
H7
H8
AD7
VCCHDA
V10
TP_VCCSUS1.05_INT_ICH1
T7
TP_VCCSUS1.05_INT_ICH2
H15
VCCSUS1_5_ICH_1
H16
VCCSUS1_5_ICH_2
V7
G14
G15
H14
W8
J7
J8
K7
K8
L7
L8
M7
C325
M8
N7
N8
P7
P8
VCCCL1_05_ICH
G18
VCCCL1_5
H17
VCCCL1_5
J14
K14
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
0.022U_0402_16V7K~D
C299
1
1
2
2
C314
1 2
0.1U_0402_16V4Z~D
C317
1
2
+3.3V_ALW_ICH
0.022U_0402_16V7K~D
C326
1
1
2
2
+3.3V_LAN
0.022U_0402_16V7K~D
0.01U_0402_16V7K~D
C306
C305
1
2
1
2
1
2
+1.5V_RUN
T56
1
C324
0.1U_0402_16V4Z~D
2
+3.3V_ALW_ICH
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
C327
1
2
0.1U_0402_16V4Z~D
1U_0603_10V4Z~D
C332
1
2
1 2
10U_0805_4VAM~D
BLM18PG181SN1_0603~D
1
2
L15
1 2
BLM18PG181SN1_0603~D
C308
4.7U_0603_6.3V6M~D
+3.3V_RUN
C313
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
C319
C318
1
1
2
2
T54
T55
C330
1 2
L14
+3.3V_RUN
C312
0.1U_0402_16V4Z~D@
C320
+1.05V_VCCP
0.1U_0402_16V4Z~D
1
2
0.1U_0402_16V4Z~D@
1
2
C309
+3.3V_RUN
+1.5V_ALW_HDA
+1.5V_RUN
+1.05V_VCCP
4.7U_0603_6.3V6M~D
C310
1
2
0.1U_0402_16V4Z~D
C321
2
1
U79E
B4
VSS[001]
B7
VSS[002]
B10
VSS[003]
B13
VSS[004]
B16
VSS[005]
B19
VSS[006]
B22
VSS[007]
D2
VSS[008]
D24
VSS[009]
E5
VSS[010]
E7
VSS[011]
E9
VSS[012]
E11
VSS[013]
E13
VSS[014]
E15
VSS[015]
E17
VSS[016]
E19
VSS[017]
E21
VSS[018]
F24
VSS[019]
G2
VSS[020]
G5
VSS[021]
G10
VSS[022]
G13
VSS[023]
G16
VSS[024]
G19
VSS[025]
G21
VSS[026]
H10
VSS[027]
H12
VSS[028]
H18
VSS[029]
H23
VSS[030]
J5
VSS[031]
0.1U_0402_16V4Z~D
1
2
J9
VSS[032]
J10
VSS[033]
J11
VSS[034]
J12
VSS[035]
J13
VSS[036]
J15
VSS[037]
J21
VSS[038]
J22
VSS[039]
J25
VSS[040]
K2
VSS[041]
K9
VSS[042]
K10
VSS[043]
K11
VSS[044]
K12
VSS[045]
K13
VSS[046]
K15
VSS[047]
K17
VSS[048]
K23
VSS[049]
L5
VSS[050]
L9
VSS[051]
L10
VSS[052]
L16
VSS[053]
L17
VSS[054]
L21
VSS[055]
L22
VSS[056]
L25
VSS[057]
M9
VSS[058]
M10
VSS[059]
M12
VSS[060]
M13
VSS[061]
M14
VSS[062]
M16
VSS[063]
M17
VSS[064]
M23
VSS[065]
N2
VSS[066]
N5
VSS[067]
N9
VSS[068]
N10
VSS[069]
N12
VSS[070]
N13
VSS[071]
N14
VSS[072]
N16
VSS[073]
N17
VSS[074]
N21
VSS[075]
N22
VSS[076]
N25
VSS[077]
P9
VSS[078]
P10
VSS[079]
P12
VSS[080]
P13
VSS[081]
P14
VSS[082]
P16
VSS[083]
P17
VSS[084]
P23
VSS[085]
R5
VSS[086]
R7
VSS[087]
R8
VSS[088]
R9
VSS[089]
R10
VSS[090]
R16
VSS[091]
R17
VSS[092]
R19
VSS[093]
R21
VSS[094]
R22
VSS[095]
R25
VSS[096]
T2
VSS[097]
T8
VSS[098]
T10
VSS[099]
T11
VSS[100]
T12
VSS[101]
T13
VSS[102]
T14
VSS[103]
T15
VSS[104]
T16
VSS[105]
T23
VSS[106]
ICH9-M SFF ES_FCBGA569~D
VSS_NCTF[01]
VSS_NCTF[02]
VSS_NCTF[03]
VSS_NCTF[04]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
VSS[159]
VSS[160]
VSS[161]
VSS[162]
VSS[163]
VSS[164]
VSS[165]
VSS[166]
VSS[167]
VSS[168]
VSS[169]
U5
U10
W11
U14
W16
U21
U22
U25
V3
V8
V19
V23
W1
W4
W5
W7
W9
W15
W19
W21
W22
W25
Y3
Y23
AA1
AA4
AA6
AA8
AA11
AA13
AA15
AA16
AA17
AA19
AA21
AA22
AA25
AB3
AB9
AB11
AB13
AB15
AC24
AC1
AC4
AC10
AC12
AC14
AD2
AD6
AD9
AD16
AD19
AD22
AE3
AE4
AE11
AE13
AE15
V17
AE8
V9
J16
A1
A25
AE1
AE25
DELL CONFIDENTIAL/PROPRIETARY
Title
Size Document Number Rev
2
Date: Sheet
Compal Electronics, Inc.
ICH9M SFF(4/4)
LA-4291P
25 49Friday, Decemb er 07, 2007
1
0.1
of
Page 26
2
1
Place close to U22 pin 13 and 34
+VDDA
R376
+3.3V_RUN
1U_0603_10V6K~D
+1.5V_RUN
C377
1
2
ICH_AZ_CODEC_SDIN0<23>
B B
ICH_AZ_CODEC_BITCLK<23>
ICH_AZ_CODEC_SDOUT<23>
ICH_AZ_CODEC_SYNC<23>
ICH_AZ_CODEC_RST#<23>
DMIC_CLK<35>
R370 0_0402_5%~D
Close to U22 pin6
ICH_AZ_CODEC_BITCLK
12
R373
10_0402_5%~D@
1
C382
10P_0402_50V8J~D@
2
CKG_SMBCLK<6,34,46>
A A
2N7002DW-7-F_SOT363-6~D
CKG_SMBDAT<6,34,46>
2N7002DW-7-F_SOT363-6~D
I2S will disconnect SMBUS a nd PU for ne x t ve rs ion.
Need to check the PU value.
C363
10U_0805_10V6K~D@
C374
C373
0.1U_0402_10V7K~D
1 2
R366 33_0402_5%~D
1 2
1
2
AUD_EAPD<27>
C375
1
2
ICH_AZ_CODEC_BITCLK
ICH_AC_SDIN0_R
ICH_AZ_CODEC_SDOUT
ICH_AZ_CODEC_SYNC
ICH_AZ_CODEC_RST#
DMIC0<35>
Close to U22 pin5
ICH_AZ_CODEC_SDOUT
12
R374
47_0402_5%~D@
1
C386
0.1U_0402_10V7K~D@
2
+3.3V_RUN_BKT_PWR
2
6 1
Q5A
5
3
4
Q5B
R359 0_0402_5%~D
1 2
Y2
1 2
27P_0402_50V8J~D
12MHZ_12PF_1Y712000CE1I~D
2
1
1000P_0402_50V7K~D
0.1U_0402_10V7K~D
C372
1
1
2
2
DMIC_CLK_R
DMIC0
AUD_EAPD
+3.3V_RUN_BKT_PWR
2.2K_0402_5%~D
12
12
R369
R368
C364
2
1
U22
1
DVDD_CORE
9
DVDD_CORE
40
NC/OTP
3
DVDD_IO
6
HDA_BITCLK
8
HDA_SDI_CODEC
5
HDA_SDO
10
HDA_SYNC
11
HDA_RST#
46
DMIC_CLK
2
DMIC0/VOL_UP/GPIO1
4
DMIC1/VOL_DN/GPIO2
47
SPDIF_OUT_0_1/EAPD/GPIO0
48
SPDIF_OUT_0
43
GPIO5
44
GPIO6
45
SPDIF_OUT_1/GPIO7
7
DVSS
49
Thermal PAD GND
92HD71B7X5NLGXB3X8_QFN48_7x7~D
2.2K_0402_5%~D
DAI_SMBCLK
DAI_SMBDATA
XTALO_12MHZ
XTALI_12MHZ
27P_0402_50V8J~D
SENSE_A
SENSE_B
PORT_A_L
PORT_A_R
PORT_B_L
PORT_B_R
VREFOUT_B
PORT_C_L
PORT_C_R
GPIO4/VREFOUT_E
1U_0402_6.3V6K~D
C368
1
2
VREFOUT_C
PORT_D_L
PORT_D_R
PORT_E_L
PORT_E_R
PORT_F_L
PORT_F_R
GPIO3
PC_BEEP
MONO_OUT
VREFFILT
+3.3V_RUN_BKT_PWR
0.1U_0402_16V7K~D
2
1
92HD71B
+3.3V_RUN_BKT_PWR +3.3V_RUN_BKT_PWR
C367
2
+VDDA
25
AVDD
38
AVDD
AUD_SENSE_A
13
AUD_SENSE_B
34
AUD_HP_OUT_L
39
AUD_HP_OUT_R
41
37
NC
AUD_EXT_MIC_L
21
AUD_EXT_MIC_R
22
28
23
24
29
AUD_LINE_OUT_L
35
AUD_LINE_OUT_R
36
14
15
31
16
17
30
18
NC
19
NC
20
NC
12
Trace>15 mil
32
CAP2
33
CAP2
AVSS
AVSS
+3.3V_RUN_BKT_PWR
VREFFILT
27
26
42
L19
BK1608LM182-T_0603~D
1U_0402_6.3V6K~D
C366
C365
2
1
1
2
R365
10K_0402_5%~D
12
0.1U_0402_10V7K~D
C369
C371
1
2
+VREFOUT
AUD_DOCK_MIC_IN_L
AUD_DOCK_MIC_IN_R
AUD_DOCK_HP_OUT_L AUD_DOCK_HP_L_C
AUD_PC_BEEP
10U_0805_10V6K~D
C384
1
2
12
C359
0.1U_0402_16V7K~D
T59
T60
1 2
10K_0402_5%~D@
10U_0805_10V6K~D@
1U_0603_10V6K~D
C370
1
1
2
2
AUD_HP_OUT_L <27>
AUD_HP_OUT_R <27>
AUD_EXT_MIC_L <35>
AUD_EXT_MIC_R <35>
AUD_LINE_OUT_L <27>
AUD_LINE_OUT_R <27>
Place close to U22
1U_0603_10V6K~D
R362
C385
1
2
+3.3V_RUN_I2S_VDD
0.1U_0402_16V7K~D
1U_0402_6.3V6K~D
C360
C361
2
1
1
2
AUD_DOCK_HP_L_R
AUD_DOCK_HP_R_R
DAI_SMBCLK
DAI_SMBDATA
XTALI_12MHZ
XTALO_12MHZ
NC_MICIN
NC_MICBIAS
R364
R367
DOCK_HP_DET<33> DOCK_MIC_DET <33>
C378 1U_0805_10V7K~D
12
C379 1U_0805_10V7K~D
12
C380 1U_0805_10V7K~D
12
C381 1U_0805_10V7K~D
12
R360
12
20K_0402_5%~D
R361
10K_0402_5%~D
12
2
1
10K_0402_5%~D
12
12
20K_0402_5%~D
0.1U_0402_16V7K~D
U21
SSM2602
3
DCVDD
18
AVDD
12
HPVDD
5
DBVDD
24
LLINEIN
23
RLINEIN
28
SCLK
27
SDIN
1
MCLK/XTI
2
XTO/ POR
22
MICIN
21
MICBIAS
25
MODE
26
CSB
20
VMID
SSM2602_LFCSP28_5X5~D
1
C376
1U_0402_6.3V6K~D
2
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
AUD_DOCK_MIC _IN_L_C
AUD_DOCK_MIC_IN_R_C
AUD_DOCK_HP_R_C
C358
12
0.1U_0402_16V4Z~D
C362
12
0.1U_0402_16V4Z~D
DVSS
AVSS
HPVSS
LOUT
ROUT
LHPOUT
RHPOUT
CLKOUT
BCLK
DACDAT
ADCDAT
DACLRC
ADCLRC
Thermal Pad
AUD_SENSE_A
12
R380
2N7002DW-7-F_SOT363-6~D
AUD_SENSE_B
12
R383
2N7002DW-7-F_SOT363-6~D
1 2
1 2
SPKR <24>
BEEP <34>
4
19
15
AUD_DOCK_MIC _IN_L_C
16
AUD_DOCK_MIC_IN_R_C
17
BKT_LSPK
13
BKT_RSPK
14
I2S_12MHZ
6
I2S_BCLK
7
I2S_DI#
8
I2S_DO
10
I2S_LRCLK
9
NC_ADCLRC
11
29
100K_0402_5%~D
R378
2
Q6A
100K_0402_5%~D
R381
2
Q7A
R371
0_0603_5%~D
R372
0_0603_5%~D
39.2K_0402_1%~D
12
12
R379
3
61
4
20K_0402_1%~D
12
12
R382
61
3
4
AUD_DOCK_HP_L_R
AUD_DOCK_HP_R_RAUD_DOCK_HP_OUT_R
EN_I2S_NB_CODEC<33>
BKT_LSPK <27>
BKT_RSPK <27>
T61
5.11K_0402_1%~D
1000P_0402_50V7K~D
20K_0402_1%~D
+3.3V_RUN+3.3V_RUN
C388
1
100K_0402_5%~D
12
R385
2
5
Q6B
2N7002DW-7-F_SOT363-6~D
39.2K_0402_1%~D
C389
5
Q7B
2N7002DW-7-F_SOT363-6~D
5.11K_0402_1%~D
1000P_0402_50V7K~D
+3.3V_RUN+3.3V_RUN
1
R384
2
+3.3V_RUN
C383
2
1
I2S_BCLK
I2S_LRCLK
I2S_DO
I2S_12MHZ
R375
1K_0402_5%~D
R377
12
100K_0402_5%~D
BKT_I2S_SCLK<21>
0.1U_0402_16V7K~D
12
12
AUD_MIC_SWITCH <35>AUD_HP_NB_SENSE<27,33,35>
+VDDA
12
BKT_GPIO11<36>
BKT_MCLK<21>
BKT_I2S_LRC<21>
U23
16
VCC
2
1A
4
2A
6
3A
10
4A
12
5A
14
6A
1
OE1#
15
OE2#
CD74HC366M96_SO16~D
+3.3V_RUN
1
5
NC
4
3
1
EN_I2S_NB_CODECBKT_GPIO11
Without BKT
BKT
Input
A
OE#
0
HL
0
L
BKT_GPIO11
I2S_12MHZ
BKT_MCLK
BKT_I2S_SCLK
I2S_BCLK
BKT_I2S_LRC
I2S_LRCLK
+3.3V_RUN
1Y
2Y
3Y
4Y
5Y
6Y
GND
C390
0.1U_0402_16V7K~D
P
A2Y
G
U20
74LVC1G14GV_SOT753-5~D
U81
1
1OE#
2
1A1
3
1Y1
4
1A2
5
1Y2
6
1A3
7
1Y3
8
GND
SN74HC368PWR_TSSOP16~D
DA204U_SOT323-3~D@
2
3
D10
1
3
5
7
9
11
13
8
12
2
3
D11
1
I2S_DI#
+3.3V_RUN
0.1U_0402_16V7K~D
1
5
P
NC
4
A2Y
G
U25
3
74LVC1G14GV_SOT753-5~D
DELL CONFIDENTIAL/PROPRIETARY
Title
Codec 92HD71B and I2C D/A A/D converters
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
LA-4291P
Output
Y
H
2OE#
DA204U_SOT323-3~D@
D12
C391
VCC
2A2
2Y2
2A1
2Y1
1A4
1Y4
3
H
L
+3.3V_RUN_BKT_PWR
0.1U_0402_16V4Z~D
16
BKT_GPIO11
15
14
13
12
11
BKT_I2S_DO
10
I2S_DI#
9
DA204U_SOT323-3~D@
2
2
3
D13
1
1
+3.3V_RUN
3
12
1
C779
1 2
2
DA204U_SOT323-3~D@
D14
DA204U_SOT323-3~D@
26 49Friday, Decemb er 07, 2007
L
H
BKT_I2S_DO <21>
DAI_BCLK# <31>
DAI_LRCK# <31>
DAI_DO# <31>
DAI_12MHZ# <31>
DAI_DI <31>
0.1
of
Page 27
5
4
3
2
1
+5V_SPK_AMP
AUD_NB_MUTE
D D
C C
AUD_HP_NB_SENSE<26,33,35>
AUD_EAPD<26>
AUD_LINE_OUT_L<26>
AUD_LINE_OUT_R<26>
AUD_HP_OUT_L<26>
AUD_HP_OUT_R<26>
AUD_EAPD
C405 0 .033U_0805_50V7K~D
12
C406 0 .033U_0805_50V7K~D
12
C407 2.2U_1206_25V7M~D
C408 2.2U_1206_25V7M~D
R387 0_0402_5%~D
1 2
R390 0_0402_5%~D
1 2
For MAX9789A, depop R399 and pop R397
+5V_SPK_AMP
12
R397
R399
1 2
B B
0_0402_5%~D
C392
1 2
5
0.1U_0402_10V7K~D
2
P
A
4
Y
1
B
G
U26
3
74AHCT1G08GW_SOT353-5~D
+5V_SPK_AMP
C393
1 2
5
0.1U_0402_10V7K~D
2
P
A
4
Y
1
B
G
U27
3
74AHCT1G08GW_SOT353-5~D
1 2
1 2
100K_0402_5%~D@
AUD_AMP_MUTE#RUN_ON
R386
1 2
0_0402_5%~D@
AUD_HP_EN
47P_0402_50V8J~D@
47P_0402_50V8J~D@
47P_0402_50V8J~D@
47P_0402_50V8J~D@
C411
C410
1
2
+5V_SPK_AMP
C413
C412
1
1
1
2
2
2
C415
1
2
Place close to Audio Chip
C398
2
1
SPKR_INL_C INT_SPK_R1
SPKR_INR_C
HP_INL_C
HP_INR_C
1 2
C409 1U_0603_10V6K~D
AUD_SPK_ENABLE#
AUD_HP_EN
AUD_AMP_MUTE#
1U_0603_10V6K~D
10U_0805_10V6K~D
C416
2
1
1M_0402_1%~D
12
R394
L20
1 2
0.1U_0402_10V7K~D
1U_0603_10V6K~D
1U_0603_10V6K~D
C400
C399
1
2
2
1
U28
3
SPKR_LIN+
2
SPKR_RIN+
27
HP_INL
26
HP_INR
24
BYPASS
23
/SPKR_EN
22
HP_EN
25
REG_EN
17
HPVDD
9
CPVDD
C1P
10
1U_0603_10V6K~D
C417
2
1
1U_0603_10V6K~D
C1N
C420
12
12
11
C1P
C1N
CPGND
+CPVSS
BLM21PG600SN1D_0805~D
30
8
18
VDD
SPVDD
SPGND21SPGND
CPVSS13HPVSS
SGND
5
14
28
33
SPVDD
ROUT+
HP_OUTL
HP_OUTR
SPKR_LIN-
REG_OUT
SPKR_RIN-
TP
TPA6040A4RHBR_QFN32_5X5~D
LOUT+
LOUT-
ROUT-
GAIN0
GAIN1
+5V_RUN_BKT_PWR
C401
2
1
6
7
20
INT_SPK_R2
19
HP_SPK_L1_R
16
HP_SPK_R1_R
15
AUD_GAIN1
31
AUD_GAIN2
32
4
29
SET
1
1U_0603_10V6K~D
W=40mils
+5V_SPK_AMP
1U_0603_10V6K~D
C403
C402
2
1
C1352 0.033U_0402_16V7K~D
1 2
R393 0_0402_5%~D@
1 2
C414 0.033U_0402_16V7K~D@
1 2
0.033U_0402_16V7K~D
10U_0805_10V6K~D
10U_0805_10V6K~D
C404
1
1
2
2
R1124 0_0402_5%~D
1 2
R1125 0_0402_5%~D
1 2
1U_0603_10V6K~D
1U_0603_10V6K~D
2
2
C418
1
1
C421
12
+VDDA
Minimam 150 mA
C419
BKT_RSPK <26>
HP_SPK_L1 <35>
HP_SPK_R1 <35>
BKT_LSPK <26>
RUN_ON <20,21,33,37,45>
*
Gain Setting for TPA6040A4
+5V_SPK_AMP
100K_0402_5%~D@
100K_0402_5%~D
12
12
R389
R388
AUD_GAIN1
AUD_GAIN2
R391
GAIN1 GAIN2 AV(inv)
12
100K_0402_5%~D@
R392
100K_0402_5%~D
12
IMPEDANCE
0
0
1
1 26K ohm
10dB
1
15.6dB
0
1
21.6dB
INPUT
82K ohm06dB
66K ohm
45K ohm
+5V_SPK_AMP
100K_0402_5%~D
R395
100K_0402_5%~D
12
AUD_SPK_ENABLE#
AUD_EAPD<26>
2N7002DW-7-F_SOT363-6~D
A A
AUD_NB_MUTE<33>
2N7002DW-7-F_SOT363-6~D
5
1 2
R396
61
2
Q8A
3
5
Q8B
4
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
4
3
2
SPEAKER_DET#<24>
SPEAKER_DET#
INT_SPK_R1
INT_SPK_R2
100P_0402_50V8J~D@
C396
100P_0402_50V8J~D@
C397
1
1
2
2
15 mils trace
DELL CONFIDENTIAL/PROPRIETARY
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
Audio amplifier and speaker CONN
LA-4291P
JSPK
1
1
2
2
3
3
4
4
5
GND
6
GND
MOLEX_53780-0470@
27 49Friday, Decemb er 07, 2007
1
0.1
of
Page 28
5
4
3
2
1
+3.3V_LAN SOURCE
C422 0.1U_0402_10V7K~D
PCIE_IRX_GLANTX_P6<24>
PCIE_IRX_GLANTX_N6<24>
D D
C C
27P_0402_50V8J~D
2
C443
1
LAN_CLK<23>
LAN_DISABLE#<24>
LAN_DISABLE#_R<33>
R410 0_0402_5%~D
1 2
Y5
1 2
25MHZ_18PF_1Y725000CE1A~D
12
C423 0.1U_0402_10V7K~D
12
PCIE_ITX_GLANRX_P6_C<24>
PCIE_ITX_GLANRX_N6_C<24>
R400 33_0402_5%~D
1 2
LAN_RSTSYNC<23>
LAN_TX0<23>
LAN_TX1<23>
LAN_TX2<23>
R404 0_0402_5%~D@
1 2
1 2
R1093
0_0402_5%~D
XTALO
XTALI
27P_0402_50V8J~D
2
C444
1
PCIE_IRX_GLANTX_P6_C
PCIE_IRX_GLANTX_N6_C
PCIE_ITX_GLANRX_P6_C
PCIE_ITX_GLANRX_N6_C
LAN_RSTSYNC
LAN_TX0
LAN_TX1
LAN_TX2
LAN_RX0
LAN_RX0<23>
LAN_RX1
LAN_RX1<23>
LAN_RX2
LAN_RX2<23>
LOM_ACTLED_YEL#
LOM_SPD100LED_ORG#
LOM_SPD10LED_GRN#
R403 4.99K_0402_1%~D
R407 1K_0402_5%~D
12
12
LAN_DISABLE#_R
10K_0402_5%~D
R409
1 2
LAN_TEST_P
LAN_TEST_N
XTALO
XTALI
U29
52
GLAN_TXP
53
GLAN_TXN
55
GLAN_RXP
56
GLAN_RXN
45
JKCLK
50
JRSTSYNC
42
JTXD_0
43
JTXD_1
44
JTXD_2
47
JRXD_0
48
JRXD_1
49
JRXD_2
4
LED_0
2
LED_1
1
LED_2
15
RSET
12
IEEE_TEST_P
13
IEEE_TEST_N
34
DIS_REG10
37
LAN_DISABLE_N
36
TEST_EN
9
XTAL2
10
XTAL1
MDI_N_0
MDI_P_0
MDI_N_1
MDI_P_1
MDI_N_2
MDI_P_2
MDI_N_3
MDI_P_3
VDDO_33_3
VDDO_33_46
AVDD_33_28
DVDD_10_5
DVDD_10_8
DVDD_10_33
DVDD_10_38
AVDD_18_11
AVDD_18_14
AVDD_18_19
AVDD_18_18
AVDD_18_24
AVDD_18_25
AVDD_18_41
AVDD_18_54
AVDD_18_32
AVDD_18_30
CTRL18
CTRL10
RESERVED_NC
GND_PAD
JTAG_TMS39JTAG_TCK40JTAG_TRST35JTAG_TDI7JTAG_TDO
WG82567LM Q036 B0~D
6
JTAG_TDO_LAN
JTAG_TDI_LAN
JTAG_TMS_LAN
JTAG_TCK_LAN
JTAG_TRST_LAN
LAN_TX0-
26
LAN_TX0+
27
LAN_TX1-
22
LAN_TX1+
23
LAN_TX2-
20
LAN_TX2+LAN_CLK_R
21
LAN_TX3-
16
LAN_TX3+
17
3
46
28
5
+1V_LAN_M
8
33
38
11
+1.8V_LAN_M
14
19
18
24
25
41
54
32
30
REGCTL_PNP18
29
31
51
57
R1103 0_0402_5%~D@
1 2
R783 200_0402_5%~D@
1 2
R411 200_0402_5%~D@
1 2
R412 200_0402_5%~D@
1 2
R414 1K_0402_5%~D@
1 2
C431
+15V_ALW
100K_0402_5%~D
12
R720
R710
2N7002DW-7-F_SOT363-6~D
3
Q18B
5
200K_0402_5%~D@
4
12
+3.3V_ALW2
+3.3V_LAN
4.7U_0603_6.3V4Z~D
0.1U_0402_16V4Z~D
C432
2
2
1
1
Place close to U29
+1V_LAN_M
4.7U_0603_6.3V6K~D
0.1U_0402_16V4Z~D
C446
C445
C448
1
2
2
1
4.7U_0603_6.3V6K~D
1
2
AUX_ON<34>
2
12
R711
100K_0402_5%~D
AUX_ON_R
2N7002DW-7-F_SOT363-6~D
61
Q18A
+1.8V_LAN_M regulator control
Place close to U29
+3.3V_LAN
C440
0.1U_0402_16V4Z~D
470P_0402_50V7K~D
C441
1
2
0.1U_0402_16V4Z~D
470P_0402_50V7K~D
C438
C437
C436
2
2
1
1
1
2
+1.8V_LAN_M
0.1U_0402_16V4Z~D
C439
2
1
10U_0805_10V4Z~D
4.7U_0603_6.3V4Z~D
C435
1
2
2
1
Make sure crystal at least 300uW max drive level
+3.3V_LAN
B B
L21 22NH_0603CS-360EJTS_5%_0603~D
LAN_TX0+
LAN_TX1-
LAN_TX2LAN_TX2+
LAN_TX3LAN_TX3+
DOCKED
A A
LOM_ACTLED_YEL#
LOM_SPD10LED_GRN#
LOM_SPD100LED_ORG#
1 2
L22 22NH_0603CS-360EJTS_5%_0603~D
1 2
L23 22NH_0603CS-360EJTS_5%_0603~D
1 2
L24 22NH_0603CS-360EJTS_5%_0603~D
1 2
L25 22NH_0603CS-360EJTS_5%_0603~D
1 2
L26 22NH_0603CS-360EJTS_5%_0603~D
1 2
L27 22NH_0603CS-360EJTS_5%_0603~D
1 2
L28 22NH_0603CS-360EJTS_5%_0603~D
1 2
1: TO DOCK
0: TO RJ45
R429
5
12
DOCKED<33>
+3.3V_LAN
10K_0402_5%~D@
10K_0402_5%~D@
R430
10K_0402_5%~D@
12
12
R431
0.1U_0402_16V4Z~D
C462
DOCKED
LOM_ACTLED_YEL#
LOM_SPD100LED_ORG#
LOM_SPD10LED_GRN#
0.1U_0402_16V4Z~D
C463
2
2
1
1
LAN_TX0-RLAN_TX0LAN_TX0+R
LAN_TX1-R
LAN_TX1+RLAN_TX1+
LAN_TX2-R
LAN_TX2+R
LAN_TX3-R
LAN_TX3+R
C464
0.1U_0402_16V4Z~D
2
1
11
12
14
15
17
19
20
54
57
56
U31
2
A0
3
A1
7
A2
8
A3
A4
A5
A6
A7
SEL
LED0
LED1
LED2
5
NC
PAD_GND
GND01GND16GND29GND313GND416GND521GND624GND728GND833GND939GND1044GND1149GND1253GND13
4
0B1
VDD04VDD110VDD218VDD327VDD438VDD550VDD6
1B1
2B1
3B1
4B1
5B1
6B1
7B1
0LED1
1LED1
2LED1
0B2
1B2
2B2
3B2
4B2
5B2
6B2
7B2
0LED2
1LED2
2LED2
PI3L500-AZFEX_TQFN56~D
55
SW_LAN_TX0-
48
SW_LAN_TX0+
47
SW_LAN_TX1-
43
SW_LAN_TX1+
42
SW_LAN_TX2-
37
SW_LAN_TX2+
36
SW_LAN_TX3-
32
SW_LAN_TX3+
31
LAN_LEDACT#
22
LINK_LED100#
23
LINK_LED10#
52
DOCK_LOM_TRD0-
46
DOCK_LOM_TRD0+
45
DOCK_LOM_TRD1-
41
DOCK_LOM_TRD1+
40
DOCK_LOM_TRD2-
35
DOCK_LOM_TRD2+
34
DOCK_LOM_TRD3-
30
DOCK_LOM_TRD3+
29
DOCK_LOM_ACTLED_YEL#
25
DOCK_LOM_SPD100LED_ORG#
26
DOCK_LOM_SPD10LED_GRN#
51
SW_LAN_TX0- <35>
SW_LAN_TX0+ <35>
SW_LAN_TX1- <35>
SW_LAN_TX1+ <35>
SW_LAN_TX2- <35>
SW_LAN_TX2+ <35>
SW_LAN_TX3- <35>
R432 150_0402_5%~D
R433 110_0402_5%~D
R434 200_0402_5%~D
SW_LAN_TX3+ <35>
1 2
1 2
1 2
DOCK_LOM_TRD0- <31>
DOCK_LOM_TRD0+ <31>
DOCK_LOM_TRD1- <31>
DOCK_LOM_TRD1+ <31>
DOCK_LOM_TRD2- <31>
DOCK_LOM_TRD2+ <31>
DOCK_LOM_TRD3- <31>
DOCK_LOM_TRD3+ <31>
DOCK_LOM_ACTLED_YEL# <31>
DOCK_LOM_SPD100LED_ORG# <31>
DOCK_LOM_SPD10LED_GRN# <31>
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
LAN_ACTLED_YEL_R# <35>
LED_100_ORG_R# <35>
LED_10_GRN_R# <35>
VOUT = 1.204 (1+R1/R2),
where R1 = R1094 + R1096, R2 = R1097
+3.3V_LAN +LOM_VCT
4.7U_0603_6.3V4Z~D
1
C1355
2
DOCK_DET#<31,33>
2
DOCK_DET#
1 2
10K_0402_5%~D
MMBT3906WT1G_SC70-3~D
+3.3V_ALW
4.7U_0603_6.3V4Z~D
C424
C425
2
2
1
1
4700P_0402_25V7K~D
12
C702
R712
1
2
REGCTL_PNP18
U94
1
IN
2
GND
3
EN
TPS73601DBVR_SOT23-5~D
R1095
2
Q120
0.1U_0402_16V4Z~D
ENAB_3VLAN
470K_0402_5%~D@
B
E
3
1
Q40
STS11NF30L_SO8~D
8
7
5
R401
R405
5.1K_0402_5%~D
5
OUT
4
NR/FB
C
4
2_1210_5%~D
12
R402
12
1
R1094
1
2
36
C428
2
1
2_1210_5%~D
12
C433
1
2
Q41
3
BCP69_SOT223~D
+1.8V_LAN_M
2
4
C442
1
2
C1356
1
2
4.64K_0402_1%
12
12
R1096
39.2K_0402_1%~D
12
R1097
36.5K_0402_1%~D
+3.3V_LAN
4.7U_0603_6.3V4Z~D
C429
+3.3V_LAN
0.1U_0402_16V4Z~D
C434
10U_0805_10V4Z~D
4.7U_0603_6.3V4Z~D
C1357
0.1U_0402_16V4Z~D
2
1
10U_0805_10V4Z~D
1
2
0.1U_0402_16V4Z~D
1
2
DELL CONFIDENTIAL/PROPRIETARY
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
Boazman 82567LM and LAN SWITCH
LA-4291P
28 49Friday, Decemb er 07, 2007
1
of
0.1
Page 29
5
4
3
2
1
Function set pin define
UDIO4UDIO3 XD E N
Pull-up
1
2
1
2
1
2
0.01U_0402_16V7K~D
C469
0.47U_0402_10V4Z~D
C480
10U_0805_6.3V6M~D
BLM21AG601SN1D_0805~D
+3.3V_RUN
0.01U_0402_16V7K~D
1
2
0.47U_0402_10V4Z~D
1
2
2
10U_0805_6.3V6M~D
C470
1
2
L29
12
+3.3V_RUN
Place close to R5C833 Chip
TPBIAS0
R457
TPA0+
TPA0TPB0+
TPB0-
R460
C498
PCI_AD[0..31]<22>
D D
+3.3V_RUN
100K_0402_5%~D
12
R436
BUS_GRST#
1U_0603_10V6K~D
C481
1
CLK_PCI_R5C833
@
10_0402_5%~D
12
R439
C C
B B
A A
@
10P_0402_50V8J~D
1
C485
2
PCI_AD17
CLKRUN#<24,33,34>
PCI_PIRQD#<22>
PCI_PIRQC#<22>
CB_HWSPND#<33>
Layout Note: Place close to
R5C833 and Shield GND
24.576MHz_16P_1BG24576CKIA~D
R5C833XO
R446 0_0402_5%~D@
+3.3V_RUN
R5C833XI
R451
220_0402_5%~D
5
2
PCI_C_BE3#<22>
PCI_C_BE2#<22>
PCI_C_BE1#<22>
PCI_C_BE0#<22>
PCI_PAR<22>
PCI_FRAME#<22>
PCI_TRDY#<22>
PCI_IRDY#<22>
PCI_STOP#<22>
PCI_DEVSEL#<22>
1 2
PCI_PERR#<22>
PCI_SERR#<22>
PCI_REQ1#<22>
PCI_GNT1#<22>
CLK_PCI_R5C833<6>
R442 0_0402_5%~D
1 2
SYS_PME#<33>
1 2
R450
1 2
10K_0402_5%~D
X2
1 2
12
PCI_RST#<22,31>
22P_0402_50V8J~D
22P_0402_50V8J~D
R440100_0402_5%~D
R443
1 2
0_0402_5%~D@
C491
12
12
C493
PCI_AD31
PCI_AD30
PCI_AD29
PCI_AD28
PCI_AD27
PCI_AD26
PCI_AD25
PCI_AD24
PCI_AD23
PCI_AD22
PCI_AD21
PCI_AD20
PCI_AD19
PCI_AD18
PCI_AD17
PCI_AD16
PCI_AD15
PCI_AD14
PCI_AD13
PCI_AD12
PCI_AD11
PCI_AD10
PCI_AD9
PCI_AD8
PCI_AD7
PCI_AD6
PCI_AD5
PCI_AD4
PCI_AD3
PCI_AD2
PCI_AD1
PCI_AD0
PCI_C_BE3#
PCI_C_BE2#
PCI_C_BE1#
PCI_C_BE0#
PCI_PAR
PCI_FRAME#
PCI_TRDY#
PCI_IRDY#
PCI_STOP#
PCI_DEVSEL#
PCI_IDSEL
PCI_PERR#
PCI_SERR#
PCI_REQ1#
PCI_GNT1#
PCI_RST#
BUS_GRST#
100K_0402_5%~D
R452
1 2
U56
125
AD31
126
AD30
127
AD29
1
AD28
2
AD27
3
AD26
5
AD25
6
AD24
9
AD23
11
AD22
12
AD21
14
AD20
15
AD19
17
AD18
18
AD17
19
AD16
36
AD15
37
AD14
38
AD13
39
AD12
40
AD11
42
AD10
43
AD9
44
AD8
46
AD7
47
AD6
48
AD5
49
AD4
50
AD3
51
AD2
52
AD1
53
AD0
7
C/BE3#
21
C/BE2#
35
C/BE1#
45
C/BE0#
33
PAR
23
FRAME#
25
TRDY#
24
IRDY#
29
STOP#
26
DEVSEL#
8
IDSEL
30
PERR#
31
SERR#
124
REQ#
123
GNT#
121
PCICLK
119
PCIRST#
71
GBRST#
117
CLKRUN#
70
PME#
115
INTA#
116
INTB#
69
HWSPND#
66
TEST
99
AGND
102
AGND
103
AGND
107
AGND
111
AGND
97
RSV
R5C833-TQFP128P_TQFP128_14X14~D
R5C833
4
VCC_PCI3V
VCC_PCI3V
VCC_PCI3V
VCC_PCI3V
VCC_PCI3V
VCC_PCI3V
VCC_RIN
VCC_ROUT
VCC_ROUT
VCC_ROUT
VCC_ROUT
VCC_ROUT
VCC_3V
VCC_MD3V
AVCC_PHY3V
AVCC_PHY3V
AVCC_PHY3V
AVCC_PHY3V
TPBIAS0
TPAP0
TPAN0
TPBP0
TPBN0
MDIO00
MDIO01
MDIO02
MDIO03
MDIO04
MDIO05
MDIO06
MDIO07
MDIO08
MDIO09
MDIO10
MDIO11
MDIO12
MDIO13
MDIO14
MDIO15
MDIO16
MDIO17
MDIO18
MDIO19
MSEN
XDEN
REXT
VREF
UDIO0/SRIRQ#
UDIO1
UDIO2
UDIO3
UDIO4
UDIO5
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
FIL0
XI
XO
10
20
27
32
41
128
61
16
34
64
114
120
67
86
+3.3V_RUN_PHY
98
106
110
112
113
109
108
105
104
80
79
78
77
76
75
74
73
88
84
82
81
93
90
91
89
92
87
85
83
58
55
94
95
96
101
100
72
60
56
65
59
57
4
13
22
28
54
62
63
68
118
122
+VCC_ROUT
+3.3V_RUN
C475
0.01U_0402_16V7K~D
1
2
TPBIAS0
TPA0+
TPA0TPB0+
TPB0SDCD#_MMCCD#
SDWP#
CARD_EN
TP_SD/MMC_LED#
SDCCMD_MMCCMD
SDCCLK_MMCCLK
SDCDAT0_MMCDAT0
SDCDAT1_MMCDAT1
SDCDAT2_MMCDAT2
SDCDAT3_MMCDAT3
MMCDAT4
MMCDAT5
MMCDAT6
MMCDAT7
R5C833XI
R5C833XO
IRQ_SERIRQ <24,32,33,34>
UDIO4
UDIO5
10K_0402_5%~D
100K_0402_5%~D
0.01U_0402_16V7K~D
0.01U_0402_16V7K~D
0.01U_0402_16V7K~D
0.1U_0402_16V4Z~D
C471
C476
10U_0805_6.3V6M~D
1
2
1 2
+3.3V_RUN
R447
1 2
1 2
R448
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
C473
C472
1
1
2
2
SDCD#_MMCCD# <35>
SDWP# <35>
CARD_EN <35>
T67
SDCCMD_MMCCMD <35>
SDCCLK_MMCCLK <35>
SDCDAT0_MMCDAT0 <35>
SDCDAT1_MMCDAT1 <35>
SDCDAT2_MMCDAT2 <35>
SDCDAT3_MMCDAT3 <35>
MMCDAT4 <35>
MMCDAT5 <35>
MMCDAT6 <35>
MMCDAT7 <35>
Layout Note:
Place C490,C492,R445 close to R5C833
C4900.01U_0402_16V7K~D
C492
3
+3.3V_RUN
0.01U_0402_16V7K~D
10U_0805_6.3V6M~D
C465
C466
1
C474
1
1
2
2
0.01U_0402_16V7K~D
10K_0402_1%~D
R445
2
1
1 2
+VCC_ROUT
+3.3V_RUN_PHY
2
C477
1000P_0402_50V7K~D
C489
C488
1
2
0.01U_0402_16V7K~D
C468
C467
1
1
2
2
0.01U_0402_16V7K~D
0.01U_0402_16V7K~D
C478
C479
1
1
2
2
0.01U_0402_16V7K~D
0.1U_0402_16V4Z~D
C487
C486
1
1
2
2
Pull-up Pull-down Pull-down
56.2_0603_1%~D
56.2_0603_1%~D
12
12
R458
56.2_0603_1%~D
56.2_0603_1%~D
12
12
R461
270P_0402_50V7K~D
5.1K_0603_1%~D
R462
2
1
1 2
DELL CONFIDENTIAL/PROPRIETARY
Title
R5C833-SD/MMC and 1394 Controller
Size Document Number Rev
LA-4291P
Date: Sheet
MSEN
SD,MMC muti-functio n pin define
Media I/F
MDIO00
SD Card
SDCD#
MDIO01
MDIO02
MDIO03
MDIO04
MDIO05
MDIO06
MDIO07
MDIO08
MDIO09
MDIO10
MDIO11
MDIO12
MDIO13
SDWP#
SDPWR0
SDPWR1
SDLED#
SDEXTCK
SDCCMD
SDCCLK
SDCDAT0
SDCDAT1
SDCDAT2
SDCDAT3
MDIO14
MDIO15
MDIO16
MDIO17
MDIO18
MDIO19
0.01U_0402_16V7K~D
0.33U_0603_10V7K~D
C494
C495
1
1
2
2
TPA0+ <35>
TPA0- <35>
TPB0+ <35>
TPB0- <35>
Compal Electronics, Inc.
1
Function
Enable
SD,MMC Card
MMC Card
MMCCD#
MMCPWR
MMCLED#
MMCCMD
MMCCLK
MMCDAT0
MMCDAT1
MMCDAT2
MMCDAT3
MMCDAT4
MMCDAT5
MMCDAT6
MMCDAT7
29 49Friday, Decemb er 07, 2007
of
0.1
Page 30
5
Mini Card 1---WLAN
4
3
2
1
+3.3V_WLAN +3.3V_WLAN
D D
1
2
+1.5V_RUN
C524
+3.3V_WLAN
C C
C527
COEX2_WLAN_ACTIVE
COEX1_BT_ACTIVE
COEX2_WLAN_ACTIVE
C521
33P_0402_50V8J~D@
0.047U_0402_16V4Z~D
0.047U_0402_16V4Z~D
C525
1
1
2
2
0.047U_0402_16V4Z~D
0.047U_0402_16V4Z~D
C529
C528
1
1
2
2
R486 0_0402_5%~D
R487 0_0402_5%~D
MINI1CLK_REQ#<6>
CLK_PCIE_MINI1#<6>
CLK_PCIE_MINI1<6>
HOST_DEBUG_RX<34>
PCIE_IRX_WLANTX_N2<24>
PCIE_IRX_WLANTX_P2<24>
PCIE_ITX_WLANRX_N2_C<24>
PCIE_ITX_WLANRX_P2_C<24>
PCIE_MCARD1_DET#<24>
ICH_CL_CLK1<24>
ICH_CL_DATA1<24>
ICH_CL_RST1#<24>
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
C526
C530
1
2
1
1
2
2
MSCLK<34>
0.1U_0402_16V4Z~D@
C531
PCIE_WAKE#
1 2
1 2
4.7U_0603_6.3V4Z~D
C523
1
2
1 2
R493
0_0402_5%~D
330U_D2E_6.3VM_R25~D@
1
+
2
USB_MCARD1_DET#
PCIE_MCARD1_DET#
PCIE_MCARD1_DET#
JMINI1
1
1
3
3
5
5
7
7
9
9
11
11
13
13
15
15
17
17
19
19
21
21
23
23
25
25
27
27
29
29
31
31
33
33
35
35
37
37
39
39
41
41
43
43
45
45
47
47
49
49
51
51
53
GND1
TYCO_1775861-1~D
R484
1 2
100K_0402_5%~D
R485
1 2
100K_0402_5%~D@
R1128
1 2
100K_0402_5%~D
GND2
2
2
4
4
6
6
8
8
10
10
12
12
14
14
16
16
18
18
20
20
22
22
24
24
26
26
28
28
30
30
32
32
34
34
36
36
38
38
40
40
42
42
44
44
46
46
48
48
50
50
52
52
54
+3.3V_RUN
+3.3V_ALW_ICH
+1.5V_RUN
WLAN_RADIO_DIS#_R
C1353
1 2
4700P_0402_25V7K~D
WLAN_RADIO_DIS#_R
PLTRST3#
12
R490
0_0402_5%~D
WLAN_SMBCLK
WLAN_SMBDATA
USBP4_DUSBP4_D+
USB_MCARD1_DET#
MSDATA_WIMAX_LED
LED_WLAN_OUT#
1 2
0_0402_5%~D@
R498 0_0402_5%~D
R499 0_0402_5%~D
BT_ACTIVE
R492
WWAN noise
USB_MCARD1_DET#
1
C522
4700P_0402_25V7K~D
2
USB_MCARD1_DET# PCIE_MCARD1_DET#
2 1
RB751S40T1_SOD523-2~D
HOST_DEBUG_TX <34>
USB_MCARD1_DET# <24>
LED_WLAN_OUT# <38>
1 2
R1085 0_0402_5%~D
1 2
R1086 0_0402_5%~D@
R488
1 2
0_0402_5%~D@
D18
12
12
AUX_EN_WOWL<34>
WLAN_RADIO_DIS# <33>
12
R477
WLAN_SMBCLK
WLAN_SMBDATA
USBP4- <24>
USBP4+ <24>
MSDATA <34>
WIMAX LEDMSDATA_WIMAX_LED
2N7002DW-7-F_SOT363-6~D
R483
2.2K_0402_5%~D
2.2K_0402_5%~D
12
R478
5
4
Q12B
2N7002DW-7-F_SOT363-6~D
+15V_ALW
100K_0402_5%~D
12
R479
61
Q11A
R481
2
100K_0402_5%~D
12
+3.3V_WLAN
2
61
Q12A
2N7002DW-7-F_SOT363-6~D
3
100K_0402_5%~D
12
R476
2N7002DW-7-F_SOT363-6~D
3
Q11B
5
200K_0402_5%~D@
12
12
R480
4
CARD_SMBCLK <34,35>
CARD_SMBDAT <34,35>
+3.3V_WLAN+3.3V_ALW
D
6
S
45
2
Q48
1
SI3456BDV-T1-E3_TSOP6~D
G
3
4700P_0402_25V7K~D
470K_0402_5%~D@
C520
1
2
BlueTooth
BT_DET#<22>
BT_RADIO_DIS#<33>
USBP6+<24>
USBP6-<24>
BT_ACTIVE<38>
COEX1_BT_ACTIVE
COEX2_WLAN_ACTIVE
33P_0402_50V8J~D
C546
R500
1
2
+3.3V_RUN
C545
1 2
0.1U_0402_16V4Z~D
JBT
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
10K_0402_5%~D
C1334
12
11
100P_0402_50V8J~D@
1
2
11
12
12
13
GND1
14
GND2
MOLEX_52893-1219
Mini Card 2---WWAN SIM Card
+3.3V_RUN_WWAN_PWR+3.3V_RUN_WWAN_PWR
JMINI2
PCIE_WAKE#<33,35>
33P_0402_50V8J~D
C537
MINI2CLK_REQ#<6>
CLK_PCIE_MINI2#<6>
CLK_PCIE_MINI2<6>
PCIE_IRX_WANTX_N1<24>
PCIE_IRX_WANTX_P1<24>
PCIE_ITX_WANRX_N1_C<24>
PCIE_ITX_WANRX_P1_C<24>
PCIE_MCARD2_DET#<22>
33P_0402_50V8J~D
0.047U_0402_16V4Z~D
0.047U_0402_16V4Z~D
C533
C534
1
2
C536
1
1
2
2
330U_D2E_6.3VM_R25~D
22U_0805_6.3VAM~D
1
C532
1
+
2
2
B B
+1.5V_RUN
+3.3V_RUN_WWAN_PWR
33P_0402_50V8J~D
0.047U_0402_16V4Z~D
C538
1
2
A A
C535
C539
1
1
2
2
1
1
3
3
5
5
7
7
9
9
11
11
13
13
15
15
17
17
19
19
21
21
23
23
25
25
27
27
29
29
31
31
33
33
35
35
37
37
39
39
41
41
43
43
45
45
47
47
49
49
51
51
53
GND1
TYCO_1775861-1~D
GND2
+1.5V_RUN
2
2
4
4
6
6
8
8
10
10
12
12
14
14
16
16
18
18
20
20
22
22
24
24
26
26
28
28
30
30
32
32
34
34
36
36
38
38
40
40
42
42
44
44
46
46
48
48
50
50
52
52
54
UIM_DATA
UIM_CLK
UIM_RESET
UIM_VPP
WWAN_RADIO_DIS#
1 2
R489
0_0402_5%~D
WWAN_SMBCLK
WWAN_SMBDATA
WWAN_USBDWW AN_USBD+
USB_MCARD2_DET#
LED_WWAN_OUT#
1 2
0_0402_5%~D@
For WIMAX LED debug
+SIM_PWR
WWAN_RADIO_DIS# <33>
PLTRST3# <22,32>
R496 0_0402_5%~D
R497 0_0402_5%~D
USB_MCARD2_DET# <24>
LED_WWAN_OUT# <38>
R491
WIMAX LED
WWAN_SMBCLK
WWAN_SMBDATA CARD_SMBDAT
12
12
USB_MCARD2_DET#
PCIE_MCARD2_DET#
USB_MCARD2_DET# PCIE_MCARD2_DET#
2.2K_0402_5%~D
12
12
R474
R475
WWAN_SW_USBD- <21>
WWAN_SW_USBD+ <21>
2N7002DW-7-F_SOT363-6~D
R494
100K_0402_5%~D
R495
1 2
100K_0402_5%~D
R482
1 2
0_0402_5%~D@
2.2K_0402_5%~D
4
+3.3V_RUN_WWAN_PWR
2
5
Q10B
12
+3.3V_RUN_WWAN_PWR
CARD_SMBCLK
61
Q10A
2N7002DW-7-F_SOT363-6~D
3
UIM_RESET
UIM_CLK
C541
1
2
33P_0402_50V8J~D
C542
+SIM_PWR
C540
1
2
1
2
33P_0402_50V8J~D
1U_0603_10V4Z~D
UIM_RESET
UIM_CLK
UIM_VPP
UIM_DATA
U39
1
2
3
SRV05-4.TCT_SOT23-6~D
1
2
3
4
5
6
7
8
9
10
MOLEX_475531001_NR
JSIM
1
2
3
4
5
6
7
8
GND
GND
C543
UIM_VPP
+SIM_PWR
UIM_DATA
33P_0402_50V8J~D
33P_0402_50V8J~D
C544
1
1
2
2
6
5
4
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
Mini WLAN/WWAN, SIM card and BT
LA-4291P
30 49Friday, Decemb er 07, 2007
1
of
0.1
Page 31
2
1
Place close to JDOCK connector HPD# inverting level shifting circuit for DisplayPort C
D19
DPB_LANE_P0_C
DPB_LANE_N0_C
DPB_LANE_P1_C
DPB_LANE_N1_C
DPB_LANE_P2_C
DPB_LANE_N2_C
DPB_LANE_P3_C
DPB_LANE_N3_C
B B
SDVO_CTRLCLK
SDVO_CTRLDATA
DPC_LANE_P0_C
DPC_LANE_N0_C
DPC_LANE_P1_C
DPC_LANE_N1_C
DPC_LANE_P2_C
DPC_LANE_N2_C DPC_LANE_N2_C
DPC_LANE_P3_C
DPC_LANE_N3_C
DDPC_CTRLCLK
DDPC_CTRLDATA
DPC_DOCK_HPD DPC_DOCK_HPD
DPC_CA_DET DPC_CA_DET
A A
@
1
2
4
5
3
8
RCLAMP0524P.TCT~D
D20
@
1
2
4
5
3
8
RCLAMP0524P.TCT~D
D21
@
1
2
4
5
3
8
RCLAMP0524P.TCT~D
D22
@
1
2
4
5
3
8
RCLAMP0524P.TCT~D
D23
@
1
2
4
5
3
8
RCLAMP0524P.TCT~D
D24
@
1
2
4
5
3
8
RCLAMP0524P.TCT~D
DPB_LANE_P0_C
10
DPB_LANE_N0_C
9
DPB_LANE_P1_C
7
DPB_LANE_N1_C
6
DPB_LANE_P2_C
10
DPB_LANE_N2_C
9
DPB_LANE_P3_C
7
DPB_LANE_N3_C
6
SDVO_CTRLCLK
10
SDVO_CTRLDATA
9
DPB_DOCK_HPDDPB_DOCK_HPD
7
DPB_CA_DETDPB_CA_DET
6
DPC_LANE_P0_C
10
DPC_LANE_N0_C
9
DPC_LANE_P1_C
7
DPC_LANE_N1_C
6
DPC_LANE_P2_C
10
9
DPC_LANE_P3_C
7
DPC_LANE_N3_C
6
DDPC_CTRLCLK
10
DDPC_CTRLDATA
9
7
6
HPD# inverting level shifting circuit for DisplayPort B
+3.3V_RUN
R510
20K_0402_5%~D
1 2
13
D
DPB_DOCK_HPD
R512
1 2
Q50
2
BSS138_SOT23~D
G
100K_0402_5%~D
S
R511
7.5K_0402_5%~D
1 2
DOCK_LOM_SPD10LED_GRN#<28>
+DOCK_PWR_BAR
DPB_DOCK_HPD# <12>
DPB_CA_DET
DAI_DI<26>
DAI_DO#<26>
C554
1
2
12
1
2
DPB_LANE_P0_C
DPB_LANE_N0_C
DPB_LANE_P1_C
DPB_LANE_N1_C
DPB_LANE_P2_C
DPB_LANE_N2_C
DPB_LANE_P3_C
DPB_LANE_N3_C
SDVO_CTRLCLK
SDVO_CTRLDATA
DPB_DOCK_HPD
BLUE_DOCK
RED_DOCK
GREEN_DOCK
HSYNC_DOCK
VSYNC_DOCK
CLK_MSE
DAI_BCLK#
DAI_LRCK#
DAI_DI
DAI_DO#
DAI_12MHZ#
D_LAD0
D_LAD1
D_LAD2
D_LAD3
D_LFRAME#
D_CLKRUN#
D_SERIRQ
D_DLDRQ1#
CLK_PCI_DOCK
DOCK_SMB_CLK
DOCK_SMB_DAT
DOCK_SMB_ALERT#
DOCK_PSID
DOCK_PWR_BTN#
SLICE_BAT_PRES#
0.1U_0603_50V4Z~D
3
D56
CLK_PCI_DOCK
R507
10_0402_5%~D@
C557
4.7P_0402_50V8C~D@
SM24.TCT_SOT23-3
2
1
DPB_LANE_P0_C<12>
DPB_LANE_N0_C<12>
DPB_LANE_P1_C<12>
DPB_LANE_N1_C<12>
DPB_LANE_P2_C<12>
DPB_LANE_N2_C<12>
DPB_LANE_P3_C<12> DPC_LANE_P3_C <12>
DPB_LANE_N3_C<12>
SDVO_CTRLCLK<10>
SDVO_CTRLDATA<10>
+NBDOCK_DC_IN_SS
BLUE_DOCK<20>
RED_DOCK<20>
GREEN_DOCK<20>
HSYNC_DOCK<20>
VSYNC_DOCK<20>
CLK_MSE<34>
DAT_MSE<34>
DAI_BCLK#<26>
DAI_LRCK#<26>
DAI_12MHZ#<26>
D_LAD0<33>
D_LAD1<33>
D_LAD2<33>
D_LAD3<33>
D_LFRAME#<33>
D_CLKRUN#<33>
D_SERIRQ<33>
D_DLDRQ1#<33>
CLK_PCI_DOCK<6>
DOCK_SMB_CLK<34>
DOCK_SMB_DAT<34>
DOCK_SMB_ALERT#<34,40>
DOCK_PSID<40>
DOCK_PWR_BTN#<34>
SLICE_BAT_PRES#<33,40,47>
2
JDOCK
1
1
3
3
5
5
7
7
9
9
11
11
13
13
15
15
17
17
19
19
21
21
23
23
25
25
27
27
29
29
31
31
33
33
35
35
37
37
39
39
41
41
43
43
45
45
47
47
49
49
51
51
53
53
55
55
57
57
59
59
61
61
63
63
65
65
67
67
69
69
71
71
73
73
75
75
77
77
79
79
81
81
83
83
85
85
87
87
89
89
91
91
93
93
95
95
97
97
99
99
101
101
103
103
105
105
107
107
109
109
111
111
113
113
115
115
117
117
119
119
121
121
123
123
125
125
127
127
129
129
131
131
133
133
135
135
137
137
139
139
141
141
143
143
145
GND1
146
PWR1
147
PWR1
148
PWR1
153
Shield_G
154
Shield_G
155
Shield_G
156
Shield_G
157
Shield_G
158
Shield_G
JAE_WD2F144WD4
DOCK_AC_OFF
2
2
4
PWR2
PWR2
PWR2
GND2
Shield_G
Shield_G
Shield_G
Shield_G
Shield_G
Shield_G
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
DPC_CA_DET
6
8
DPC_LANE_P0_C
10
DPC_LANE_N0_C
12
14
DPC_LANE_P1_C
16
DPC_LANE_N1_C
18
20
DPC_LANE_P2_C
22
DPC_LANE_N2_C
24
26
DPC_LANE_P3_C
28
DPC_LANE_N3_C
30
32
DDPC_CTRLCLK
34
DDPC_CTRLDATA
36
38
DPC_DOCK_HPD
40
ACAV_DOCK_SRC#
42
44
DAT_DDC2_DOCK
46
CLK_DDC2_DOCK
48
50
52
SATA_SBRX_DTX_P3
54
SATA_SBRX_DTX_N3
56
58
60
62
64
USBP8+
66
USBP8-
68
70
USBP9+
72
USBP9-DAT_MSE
74
76
CLK_KBD
78
DAT_KBD
80
82
84
86
88
90
92
94
96
BREATH_LED#
98
100
102
DOCK_LOM_TRD0+
104
DOCK_LOM_TRD0-
106
108
DOCK_LOM_TRD1+
110
DOCK_LOM_TRD1-
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
149
150
151
152
159
160
161
162
163
164
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
+LOM_VCT
DOCK_LOM_TRD2+
DOCK_LOM_TRD2-
DOCK_LOM_TRD3+
DOCK_LOM_TRD3-
DOCK_DCIN_IS+
DOCK_DCIN_IS-
PCI_RST#
DOCK_DET#
0.1U_0603_50V4Z~D
C553
1
2
DOCK_DET#
DOCK_AC_OFF <33>
DOCK_LOM_SPD100LED_ORG# <28>
DPC_LANE_P0_C <12>
DPC_LANE_N0_C <12>
DPC_LANE_P1_C <12>
DPC_LANE_N1_C <12>
DPC_LANE_P2_C <12>
DPC_LANE_N2_C <12>
DPC_LANE_N3_C <12>
DDPC_CTRLCLK <10>
DDPC_CTRLDATA <10>
ACAV_DOCK_SRC# <34,47>
DAT_DDC2_DOCK <20>
CLK_DDC2_DOCK <20>
C548 0.01U_0402_16V7K~D
C549 0.01U_0402_16V7K~D
SATA_SBTX_C_DRX_P3 <23>
SATA_SBTX_C_DRX_N3 <23>
USBP8+ <24>
USBP8- <24>
USBP9+ <24>
USBP9- <24>
CLK_KBD <34>
DAT_KBD <34>
BREATH_LED# <34,38>
DOCK_LOM_ACTLED_YEL# <28>
DOCK_LOM_TRD0+ <28>
DOCK_LOM_TRD0- <28>
DOCK_LOM_TRD1+ <28>
DOCK_LOM_TRD1- <28>
DOCK_LOM_TRD2+ <28>
DOCK_LOM_TRD2- <28>
DOCK_LOM_TRD3+ <28>
DOCK_LOM_TRD3- <28>
DOCK_DCIN_IS+ <46>
DOCK_DCIN_IS- <46>
PCI_RST# <22,29>
DOCK_DET# <28,33>
+DOCK_PWR_BAR
+RTC_CELL
R508
12
100K_0402_5%~D
12
12
Switch that support both DisplayPort C and DVI/HDMI
Switch that support both DisplayPort B and DVI/HDMI
DPC_DOCK_HPD
SATA_SBRX_DTX_P3_C <23>
SATA_SBRX_DTX_N3_C <23>
DDPC_CTRLCLK
DDPC_CTRLDATA
DPC_CA_DET
SDVO_CTRLCLK
SDVO_CTRLDATA
DPB_CA_DET
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
+3.3V_RUN
A2Y
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
+3.3V_RUN
A2Y
+3.3V_RUN
2
G
100K_0402_5%~D
R503
1 2
C550
DPC_F
1 2
2N7002DW-7-F_SOT363-6~D
2N7002DW-7-F_SOT363-6~D
C551
1 2
C552
1 2
0.1U_0402_16V4Z~D
1
5
P
NC
4
G
U40
NC7SZ04P5X_NL_SC70-5~D
3
C555
DPB_F
1 2
2N7002DW-7-F_SOT363-6~D
2N7002DW-7-F_SOT363-6~D
C556
1 2
C558
1 2
0.1U_0402_16V4Z~D
5
1
P
NC
4
G
U41
NC7SZ04P5X_NL_SC70-5~D
3
1
R501
20K_0402_5%~D
1 2
13
D
Q49
BSS138_SOT23~D
S
6 1
Q13A
Q13B
3
6 1
Q14A
Q14B
3
2
DPC_B
DPC#_BDPC#_F
4
5
2
DPB_B
DPB#_BDPB#_F
4
5
DPC_DOCK_HPD# <12>
R502
7.5K_0402_5%~D
1 2
R504
0_0402_5%~D
R505
0_0402_5%~D
R506
0_0402_5%~D
R509
0_0402_5%~D
12
DPC_DOCK_AUX <12>
12
DPC_DOCK_AUX# <12>
12
DPB_DOCK_AUX <12>
12
DPB_DOCK_AUX# <12>
DELL CONFIDENTIAL/PROPRIETARY
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
DOCKING CONNECTOR
LA-4291P
31 49Friday, Decemb er 07, 2007
0.1
of
Page 32
2
T82
+SC_PWR
CLK_PCI_TPM
LPC_EN_R
PLTRST3#
LPC_LFRAME#
IRQ_SERIRQ_R
LPC_LAD0
LPC_LAD1
LPC_LAD2
LPC_LAD3
LPD#
UART_RX/GPIO0
UART_TX/GPIO1
GPIO2_TER_VDDMON
SC_DET#_RSC_DET
12
SPI_CLK_USH
SPI_CS
SPI_RXD
SPI_TXD
GPIO14_TER_ON/OFF
BCM5880_GPIO15
GPIO16_TER_TRIS
USBP10-_R
USBP10+_R
FP_USBDFP_USBD+
USBH_OC0#
USBH_N1
USBH_P1
USBH_OC1#
5880_GPIO25
5880_GPIO26
BCM5880_SCVCC
BCM5880_SCRST
BCM5880_IO
AUX1UC
AUX2UC
BCM5880_SCDET
C579
2
1
1U_0402_6.3V6K~D
C580
2
1
CLK_PCI_TPM<6>
SP_TPM_LPC_EN<33>
IRQ_SERIRQ<24,29,33,34>
+3.3V_RUN
B B
+3.3V_RUN
4.7K_0402_5%~D
R537
1 2
4.7K_0402_5%~D@
R553
1 2
Pull down for 5880 Rev A0, and pull up for Rev B0
SPI_TXD
SPI_CLK_USH
SPI_RST
SP_TPM_LPC_EN<33>
4.7K_0402_5%~D
4.7K_0402_5%~D@
U34
D
C
RESET#
S#
LPC_EN_R
IRQ_SERIRQ_R
USBH_OC0#
USBH_OC1#
Q
VSS
VCC
W#
1 2
R770 47K_0402_1%~D
1 2
R771 47K_0402_1%~D@
1 2
R529 4.7K_0402_5%~D
R536
1 2
R552
1 2
1
2
3
4
M45PE16-VMP6TP_SO8~D
LPD#
USBP10-<24>
USBP10+<24>
TER_USBH_N1
TER_USBH_P1
BCM5880_SCCLK BCM5880_SCCLK_R
+3.3V_RUN
1U_0603_10V4Z~D
8
7
6
BCM5880_GPIO15SPI_CS
5
R514 0_0402_5%~D
1 2
R516
1 2
0_0402_5%~D
R517
1 2
0_0402_5%~D@
UART_RX/GPIO0
R769
@
0_0402_5%~D
1 2
UART_TX/GPIO1
R521 22_0402_5%~D
1 2
R522 22_0402_5%~D
1 2
R523 1.5K_0402_5%~D
1 2
R525 22_0402_5%~D
1 2
R526 22_0402_5%~D
1 2
R528
1 2
10_0402_5%~D
12
C620
1 2
SPI_RXD
R576
1 2
4.7K_0402_5%~D@
PCI_TPM_TERM
2
1
PLTRST3#<22,30>
LPC_LFRAME#<23,33,34>
LPC_LAD0<23,33,34>
LPC_LAD1<23,33,34>
LPC_LAD2<23,33,34>
LPC_LAD3<23,33,34>
R520
10K_0402_5%~D
FP_USBD-<21>
FP_USBD+<21>
C572
1 2
680P_0402_50V7K@
CLK_PCI_TPM
R573
10_0402_5%~D@
C621
4.7P_0402_50V8C~D@
Universal Smart Card Interface IC
C764
1
GPIO2_TER_VDDMON 8009_VDDMON
BCM5880_SCCLK
A A
GPIO16_TER_TRIS S C_USB#
5880_GPIO26
5880_GPIO25
BCM5880_SCRST
+3.3V_RUN
R545
10K_0402_5%~D
R782
1 2
47K_0402_1%~D@
R555
47K_0402_1%~D
1 2
1 2
1 2
SC_USB#
GPIO14_TER_ON/OFF
12
T83
T84
T85
12
BCM5880_SCDET
BCM5880_IO
AUX1UC
AUX2UC
R554 10K_0402_5%~D
R556 47K_0402_1%~D
R558 47K_0402_1%~D
R560 10K_0402_5%~D
12
U33
24
ON/OFF
7
CLKIN
8
RDY
9
OFF_ACK
11
OFF_REQ
12
CS
13
SC_USB#
4
CMDVCC5#
5
CMDVCC3#
6
RSTIN
32
OFF#
10
TEST1
30
TEST2
1
I/OUC
2
AUX1UC
3
AUX2UC
73S8009CN-32IMR/F_QFN32_5X5~D
Place close to JSC
+SC_VCC
0.47U_0402_6.3V4Z~D
C618
2
1
VCC
VDD
PRES
AUX1
AUX2
GND
GND
GND
VPC
CLK
RST
VP
LIN
DM
DP
I/O
+3.3V_RUN
2
2
19
26
29
15
+LIN
27
4.7U_0603_6.3V6K~D
TER_USBH_N1
23
TER_USBH_P1
25
R557 100K_0402_5%~D
14
R559 0_0402_5%~D
22
R561 0_0402_5%~D
21
R562 0_0402_5%~D
20
R563 0_0402_5%~D
16
18
17
28
31
4.7K_0402_5%~D
M7
R6
N5
P5
M6
R5
N6
N7
P6
P7
B5
B4
D6
A4
C5
B3
D5
A3
C4
A2
D4
R13
R14
P14
N11
N12
M11
N13
P13
R15
P8
R7
N15
L14
L15
K15
K14
J14
J15
M10
M15
1U_0402_6.3V6K~D
N14
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
C765
1
2
+SC_VCC
C596
12
12
1 2
1 2
1 2
1 2
2
C611
27P_0402_50V8J~D
1
R575
1 2
+SC_VCC
U32A
LCLK
LPCEN
GPIO_17/LRESET_N
GPIO_18/LFRAME_N
GPIO_19/LSERIRQ
GPIO_20/LAD[0]
GPIO_21/LAD[1]
GPIO_22/LAD[2]
GPIO_23/LAD[3]
GPIO_24/LPCPD_N
GPIO_0/UART_RX
GPIO_1/UART_TX
GPIO_2/UART_CTS
GPIO_3/UART_RTS
GPIO_6/SSP_CLK
GPIO_7/SSP_FSS
GPIO_8/SSP_RXD
GPIO_9/SSP_TXD
GPIO_14
GPIO_15
GPIO_16
USBD_DN
USBD_UP
GPIO_27/USBD_ATATCH
USBH_DN0
USBH_UP0
USBH_OC_0
USBH_DN1
USBH_UP1
USBH_OC_1
GPIO_25/SC_SEL5V
GPIO_26/SC_SEL18V
SC_CINRUSH
SC_CLK
SC_VCC
SC_RST
SC_IO
SC_FCB
SC_FCB_ENB
SC_DET
SC_PWR
SC_PWR
BCM5880KFBG B0_FBGA225~D
BCM5880
LPC
UARTSPISPISmard Card
10U_0805_10V4Z~D
C583
C584
1
2
12
L37
10UH_LQH32CN100K53L_10%~D
SC_DET
SC_C8
SC_C4
SC_IO
SC_CLK
SC_RST
SC_DET
SC_IO
SC_C4
SC_C8
SC_CLK
SC_RST
2
C612
27P_0402_50V8J~D
1
JSC
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
GND
12
GND
TYCO_1-1775784-1
SMC_ADD_0
SMC_ADD_1
SMC_ADD_2
SMC_ADD_3
SMC_ADD_4
SMC_ADD_5
SMC_ADD_6
SMC_ADD_7
SMC_ADD_8
SMC_ADD_9
SMC_ADD_10
SMC_ADD_11
SMC_ADD_12
SMC_ADD_13
SMC_ADD_15/REFCLK_FREQ_0
SMC_ADD_16/REFCLK_FREQ_1
BootStrap
+3.3V_RUN
2
1
SMC_ADD_14
SMC_ADD_17/BOOT_SRC_0
SMC_ADD_18/BOOT_SR_1
SMC_ADD_19
SMC_ADD_20
SMC_ADD_21
SMC_ADD_22
SMC_ADD_23
SMC_DATA_0
SMC_DATA_1
SMC_DATA_2
SMC_DATA_3
SMC_DATA_4
SMC_DATA_5
SMC_DATA_6
SMC_DATA_7
SMC_DATA_8
SMC_DATA_9
SMC_DATA_10
SMC_DATA_11
SMC_DATA_12
SMC_DATA_13
SMC_DATA_14
SMC_DATA_15
SMC_ADV_N
SMC_BLS_N_0
SMC_BLS_N_1
SMC_CRE
SMC_CS_N_0
SMC_CS_N_1
SMC_IO_3V
SMC_OE_N
SMC_WE_N
+3.3V_RUN
C585
0.1U_0402_16V4Z~D
C603
H1
J4
H2
H3
G1
H4
F2
G4
G2
G3
E2
F4
F1
F3
D2
E3
D1
E1
C2
D3
C1
E4
B1
C3
R2
P3
R1
P2
R3
M4
N2
N3
P1
M3
M2
L4
N1
L3
L2
K4
K2
J1
K1
J3
M1
K3
P12
J2
L1
1U_0402_6.3V6K~D
C586
2
1
1U_0402_6.3V6K~D
C604
2
1
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
+3.3V_RUN
4.7K_0402_5%~D@
R535
R534
1 2
SMC_ADD15
SMC_ADD16
SMC_ADD17
SMC_ADD18
+3.3V_RUN
1U_0402_6.3V6K~D
2
1
1U_0402_6.3V6K~D
2
1
+1.2V_VDDC_5880
C564
1 2
4.7K_0402_5%~D
R550
R551
1 2
1 2
FP_RESET# <35>
R774
0_0402_5%~D@
1 2
JTAG_TDI_USH
+3.3V_RUN
4.7K_0402_5%~D
R531
1 2
Function
Boot SRC SPI
REF CLK
C587
2
1
C605
2
1
1U_0402_6.3V6K~D
C565
2
1
SMC
AD[18:17]
AD[16:15]
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
C589
C588
2
2
1
1
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
C607
C606
2
2
1
1
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
C566
C567
2
2
1
1
+3.3V_RUN
R540
510K_0402_5%~D
1 2
POR_EXTR
4.7K_0402_5%~D
4.7K_0402_5%~D
12
R543
4.7K_0402_5%~D@
R542
JTAG_TDO_USHJTAG_CLK_USH
R775
0_0402_5%~D@
1 2
JTAG_TMS_USH
1 2
R532 4.7K_0402_5%~D
1 2
R541 4.7K_0402_5%~D
1 2
R1120 4.7K_0402_5%~D
1 2
+3.3V_RUN
4.7K_0402_5%~D
00
R548
330K_0402_5%~D
1 2
R569
4.7K_0402_5%~D
1 2
R549
1 2
JTAG_RST#_USH
JTCE_USH
FP_RESET#
01
SMC
RVD
24MHZ1027.12MHz
1U_0402_6.3V6K~D
C590
1U_0402_6.3V6K~D
C608
2
1
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
C591
C592
2
2
1
1
4.7U_0603_6.3V6M~D
4.7U_0603_6.3V6M~D
C609
1
1
2
2
+3.3V_RUN
4.7K_0402_5%~D
12
R538
1U_0402_6.3V6K~D
C569
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
C570
2
2
1
1
+1.2V_RUN_PLL
C561
C568
1 2
680P_0402_50V7K
SBOOT
4.7K_0402_5%~D@
R781
0_0402_5%~D@
1 2
OVSTB
RST_N
22_0402_5%~D@
BBCLK BB C LK_R
1 2
1 2
R773 4.7K_0402_1%~D@
AUX_XIN
R1112
0_0402_5%~D@
1 2
AUX_XOUT
1 2
R530 10K_0402_5%~D
1 2
R539 1K_0402_5%~D
USB
48MHz
1U_0402_6.3V6K~D
+1.2V_VDDC_5880
2
1
R524
C571
+3.3V_RUN
0_0402_5%~D
1 2
+3.3V_RUN
4.7U_0603_6.3V6M~D@
1
2
BBCLK
TAMPER_N
C13
J11
K11
L13
M14
K13
H14
H15
H13
H12
J13
L10
L11
1U_0603_10V4Z~D
1
2
R772
11
RVD
U32C
VDDC
E5
VDDC
F5
VDDC
VDDC
VDDC
K6
VDDC
K7
VDDC
K9
VDDC
N4
VDDC
P4
VDDC
E6
VDDO_VAR
F6
VDDO_VAR
G5
VDDO_SMC
H5
VDDO_SMC
J5
VDDO_SMC
K8
VDDO_LPC
L7
VDDO_LPC
K5
VDDO_33CORE
L5
VDDO_33CORE
L6
VDDO_33CORE
VDDO_33SC
VDDO_33SC
VDDO_SC
V3P3_BBLCLK
V3P3_PWRGOOD
V3P3_TAMPER_N
VDD_BB
VDD_BB
L8
VESD
L9
VDDO_33
VDDO_33
VDDO_33
BCM5880KFBG B0_FBGA225~D
1
C562
1U_0603_10V4Z~D
2
T71
T72
T73
JTAG_CLK_USH
JTAG_TDI_USH
JTAG_TDO_USH
JTAG_TMS_USH
JTAG_RST#_USH
JTCE_USH
BBCLK
JTAG_RST#_USH
BCM5880
1
POR_EXTR
OVSTB
SCANMOD
SBOOT
SWV
TSTMOD
IDQ_EN
REF_XIN
REF_XOUT
AUX_XIN
AUX_XOUT
RST_N
SPI_RST
1
U32B
F12
POR_AVSS
G13
POR_EXTR
G15
POR_INT12
G14
POR_MONITOR
B14
PLL_VDD_1P2I
B15
PLL_AVDD_1P2O
D12
PLL_VSS
D13
PLL_VDD_1P2I
E12
PLL_VSS
A15
NC
N9
OVSTB/ZEROB
M8
SCANACCMODE
P9
SECURE_BOOT
M12
SWV/ERROR,OSC1,OSC2,SPL
R9
TESTMODE/TST_SEC_BOOT
R10
IDDQ_EN/CM3_MODE
F15
REFCLK_XTALIN
F14
REFCLK_XTALOUT
D15
AUXCLK_XTALIN
E14
AUXCLK_XTALOUT
A1
CLKOUT
B2
CLKOUT_EN
N8
RST_N
R8
RSTOUT_N
P10
JTAG_TCK
R11
JTAG_TDI
N10
JTAG_TDO
R12
JTAG_TMS
P11
JTAG_TRSTN
M9
JTCE
BCM5880KFBG B0_FBGA225~D
R527
0_0402_5%~D@
1 2
27.12MHZ_12PF_1N227120CC0B~D
1
C581
22P_0402_50V8J~D
2
CORE_CINRUSH
CORE_PWRDN
ALDO_PWRDN
AVDD33_LDO25
AVDD_2P5I
AVDD_2P5O
AVDD25_ldo12
AVDD25_ldo12
AVDD_1P2O
AVDD_1P2I_AUX
AVDD_1P2I_REF
AVDD25_PLL
OTP_PWR
AVSS_LDO12
AVSS_ldo25
AVSS_ldo25
AVSS_AUX
AVSS_REF
AVSS_PLL
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
BCM5880
JTAG CLK
R546
1 2
10M_0402_5%~D@
Y3
1
2
R4
M5
D10
A14
G12
B13
A13
B12
E11
E13
F13
D14
P15
F11
C12
D11
C15
E15
C14
G11
G6
G7
G8
H10
H11
H6
H7
H8
H9
J10
J12
J6
J7
J8
J9
K10
K12
L12
M13
F8
3
IN
OUT
4
GND
GND
C559
1 2
680P_0402_50V7K
R513 2.2K_0402_5%~D
1 2
R515 4.7K_0402_5%~D
1 2
+2.5V_RUN_AVDD
+1.2V_RUN_PLL
+3.3V_RUN
+OTP_PWR
4.7U_0603_6.3V6M~D
C560
1
2
Place C560 close to U32.A14
+2.5V_RUN_AVDD
HF_RFIDTAG_AVDD2P5
HF_RFIDTAG_AVDD2P5
HF_RFIDTAG_DVDD1P2
HF_RX_ADC_AVDD1P2
HF_RX_AVDD1P2
HF_RX_AVDD2P5
HF_TX_AVDD1P2
HF_TX_AVDD2P5
HF_TX_AVDD3P3
HF_RFIDTAG_AVSS
HF_RFIDTAG_VREF
HF_RFIDTAG_VRX_N
HF_RFIDTAG_VRX_P
HF_RFIDTAG_VTX
HF_RX_TEST0
HF_RX_TEST1
HF_RX_TEST2
HF_RX_TEST3
HF_RX_N
HF_RX_P
RDIF
HF_TX_N
HF_TX_P
HF_RFIDTAG_AVSS
HF_RFIDTAG_AVSS
HF_RFIDTAG_DVSS
HF_RX_ADC_AVSS1
HF_RX_ADC_AVSS2
HF_RX_AVSS
HF_RX_AVSS
HF_TX_AVSS
HF_TX_AVSS
HF_TX_AVSS
R544
0_0402_5%~D
1 2
1 2
R547
0_0402_5%~D
XOXI
1
C582
22P_0402_50V8J~D
2
R518
0_0603_5%~D@
R519
0_0603_5%~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
C1291
C1293
C1292
2
2
1
1
DELL CONFIDENTIAL/PROPRIETARY
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
USH BCM5880
LA-4291P
32 49Friday, Decemb er 07, 2007
12
12
2
1
A7
F7
C6
E10
F9
G9
D8
A8
D9
B6
A6
C7
B7
E7
B10
C10
A11
A12
C11
B11
C9
B9
C8
D7
A5
E9
G10
F10
A10
A9
B8
E8
REF_XOUT
REF_XIN
1U_0402_6.3V6K~D
C1294
of
+3.3V_RUN
+SC_PWR
4.7U_0603_6.3V6M~D@
1
2
0.1
Page 33
5
4
3
2
1
+3.3V_ALW
1 2
R584 100K_0402_5%~D
1 2
R1031 10K_0402_5%~D
1 2
R577 10K_0402_5%~D
1 2
D D
C C
B B
A A
R1088 100K_0402_5%~D@
1 2
R583 100K_0402_5%~D
1 2
R579 10K_0402_5%~D
1 2
R1089 100K_0402_5%~D
1 2
R581 10K_0402_5%~D@
1 2
R1126 100K_0402_5%~D
1 2
R580 100K_0402_5%~D
1 2
R1118 100K_0402_5%~D
+3.3V_RUN
1 2
R585 100K_0402_5%~D
1 2
R604 100K_0402_5%~D
1 2
R586 100K_0402_5%~D
R587 100K_0402_5%~D
1 2
R1104 10K_0402_5%~D
R605 100K_0402_5%~D
LID_CL#<35,38>
INSTANT_ON_SW#<34,35>
R614
BID0
BID1
BID2
CHIPSET_ID0
CHIPSET_ID1
12
12
10K_0402_5%~D@
R615
1 2
1 2
5
DCIN_CBL_DET#
SYS_PME#
USB_POWERSHARE_PWR_EN#
10K_0402_5%~D@
PCIE_WAKE#
DET_PCCRD_EXPSCRD#
CAP_SW_SMB_INT#
CELL_CHARGER_DET#
ESATA_USB_PWR_EN#
INSTANT_ON_SW_D#
SLICE_BAT_PRES#
SW_BD_DET#
WIRELESS_ON#/OFF
PBATT_OFF
LCD_TST
PANEL_BKEN_MCH
SYS_LED_MASK#
VGA_IDENTIFY
R613
1 2
10_0402_5%~D
D57
RB751S40T1_SOD523-2~D
R616
1 2
1 2
R1127
0_0402_5%~D@
10K_0402_5%~D@
R617
1 2
21
10K_0402_5%~D@
R618
+3.3V_ALW
1 2
1M_0402_5%~D
12
R612
0.047U_0402_16V4Z~D
C631
1
2
+3.3V_ALW
10K_0402_5%~D
R619 10K_0402_5%~D
1 2
R620 10K_0402_5%~D
1 2
R621 10K_0402_5%~D
1 2
R622 10K_0402_5%~D
1 2
R623 10K_0402_5%~D@
1 2
U35
T87
PBAT_PRES#
SCRL_LED#
NUM_LED#
DCIN_CBL_DET#
PBATT_OFF
SYS_PME#
PCIE_WAKE#
WIRELESS_ON#/OFF
BT_RADIO_DIS#
EXPRCRD_PWREN#
EXPRCRD_STDBY#
BC_INT#_ECE5028
BC_DAT_ECE5028
BC_CLK_ECE5028
DET_PCCRD_EXPSCRD#
BIOS_RECOVERY
CAP_SW_SMB_INT#
EN_I2S_NB_CODEC
CB_HWSP ND#
EN_DOCK_PWR_BAR
ADAPT_OC
ADAPT_TRIP_SEL
LCD_TST
PSID_DISABLE#
PANEL_BKEN_MCH
DOCKED
DOCK_DET#
AUD_NB_MUTE
CELL_CHARGER_DET#
LCD_VCC_TEST_EN
AUD_HP_NB_ SENSE
ESATA_USB_PWR_EN#
LID_CL_SIO#
INSTANT_ON_SW_D#
SLICE_BAT_PRES#
SW_BD_DET#
LAN_DISABLE#_R
CAP_LED#
SYS_LED_MASK#
SIO_EXT_WAKE#
ICH_PME#
ICH_PCIE_W AKE#
WLAN_RADIO_DIS#
WWAN_RADIO_DIS#
VGA_IDENTIFY
CHIPSET_ID1
R611
10K_0402_5%~D
CHIPSET_ID0
BID2
BID1
BID0
PBAT_PRES#<40>
SCRL_LED#<38>
NUM_LED#<38>
DCIN_CBL_DET#<40>
PBATT_OFF<47>
SYS_PME#<29>
PCIE_WAKE#<30,35>
USB_POWERSHARE_PWR_EN#<35>
WIRELESS_ON#/OFF<35>
BT_RADIO_DIS#<30>
EXPRCRD_PWREN#<35>
EXPRCRD_STDBY#<35>
BC_INT#_ECE5028<34>
BC_DAT_ECE5028<34>
BC_CLK_ECE5028<34>
DET_PCCRD_EXPSCRD#<35>
CAP_SW_SMB_INT#<35>
EN_I2S_NB_CODEC<26>
CB_HWSPND#<29>
EN_DOCK_PWR_BAR<47>
ADAPT_OC<46>
ADAPT_TRIP_SEL<46>
LCD_TST<20>
PSID_DISABLE#<40>
PANEL_BKEN_MCH<12>
DOCKED<28>
DOCK_DET#<28,31>
AUD_NB_MUTE<27>
CELL_CHARGER_DET#<35>
LCD_VCC_TEST_EN<20>
AUD_HP_NB_SENSE<26,27,35>
ESATA_USB_PWR_EN#<35>
SLICE_BAT_PRES#<31,40,47>
SW_BD_DET#<35>
LAN_DISABLE#_R<28>
CAP_LED#<38>
SYS_LED_MASK#<38>
SIO_EXT_WAKE#<24>
ICH_PME#<22>
ICH_PCIE_WAKE#<24>
WLAN_RADIO_DIS#<30>
WWAN_RADIO_DIS#<30>
97
GPIOA[0]
98
GPIOA[1]
99
GPIOA[2]
100
GPIOA[3]
101
GPIOA[4]
102
GPIOA[5]
103
GPIOA[6]
104
GPIOA[7]
24
GPIOH[0]
25
GPIOH[1]
26
GPIOH[4]
27
GPIOH[5]
58
BC_INT#
59
BC_DAT
60
BC_CLK
1
GPIOE[0]/RXD
2
GPIOE[1]/TXD
3
GPIOE[2]/RTS#
4
GPIOE[3]/DSR#
5
GPIOE[4]/CTS#
84
GPIOE[5]/DTR#
83
GPIOE[6]/RI#
6
GPIOE[7]/DCD#
65
GPIOB[0]/INIT#
66
GPIOB[1]/SLCTIN#
67
GPIOC[2]/SCLT
68
GPIOC[3]/PE
69
GPIOC[4]/BUSY
70
GPIOC[5]/ACK#
71
GPIOC[6]/ERROR#
73
GPIOC[7]/ALF#
74
GPIOD[0]/STROBE#
75
GPIOC[1]/PD7
76
GPIOC[0]/PD6
77
GPIOB[7]/PD5
78
GPIOB[6]/PD4
79
GPIOB[5]/PD3
80
GPIOB[4]/PD2
81
GPIOB[3]/PD1
82
GPIOB[2]/PD0
61
GPIOD[1]
62
GPIOD[2]
63
GPIOD[3]/VBUS_DET
28
GPIOD[4]/OCS1_N
29
GPIOD[5]/OCS2_N
30
GPIOD[6]/OCS3_N
31
GPIOD[7]/OCS4_N
32
GPIOH[6]
33
GPIOH[7]
88
GPIOG[0]
89
GPIOG[1]
90
GPIOG[2]
91
GPIOG[3]
92
GPIOG[4]
93
GPIOG[5]
94
GPIOG[6]
95
GPIOG[7]
106
SYSOPT1/GPIOH[2]
107
SYSOPT0/GPIOH[3]
109
GPIOF[7]
110
GPIOF[6]
111
GPIOF[5]
112
GPIOF[4]
113
IRTX
114
12
IRRX
115
GPIOF[3]/IRMODE/IRRX3B
116
GPIOF[2]/IRTX2
117
GPIOF[1]/IRRX2
118
GPIOF[0]/IRMODE/IRRX3A
ECE5028-NU_VTQFP128_14X14~D
BID2 BID1 BID00REV
00
00
001
011
4
X00
1
X01
X02
X03
+3.3V_ALW
1
C622
0.1U_0402_16V4Z~D
2
34
57
85
108
VCC1
VCC1
VCC1
VCC1
ECE5028-NU
(ECE5018)
USB
GPIO
TEST
CLK
LPC
DLPC
GPIOK[0](USBDP2)
GPIOK[1](USBDN2)
GPIOK[3](USBDP3)
GPIOK[2](USBDN3)
GPIOK[5](USBDP4)
GPIOK[6](USBDN4)
GPIOI[6](VDDA33PLL)
GPIOI[5](VDDA18PLL)
GPIOI[4](XTAL1/CLKIN)
VCC1(VDDA33)
GPIOJ[7](VDDA33)
GPIOK[4](VDDA33)
GPIOI[1](VCC1)
GPIOJ[2](USBDP0)
GPIOJ[3](USBDN0)
GPIOJ[6](USBDP1)
GPIOJ[5](USBDN1)
GPIOI[2](VDD18)
CAP_LDO
GPIOJ[0](RBIAS)
TEST_PIN
GPIOI[7](ATEST)
GPIOI[3](XTAL2)
LAD0
LAD1
LAD2
LAD3
LFRAME#
LRESET#
PCICLK
CLKRUN#
LDRQ0#
LDRQ1#
SER_IRQ
CLKI (14.318 MHz)
DLAD0
DLAD1
DLAD2
DLAD3
DLFRAME#
DCLK_RUN#
DLDRQ1#
DSER_IRQ
PWRGD
OUT65
GPIOJ[4](VSS)
GPIOK[7](VSS)
GPIOJ[1](VSS)
1
C626
0.1U_0402_16V4Z~D
2
8
14
20
119
9
10
13
12
15
16
19
18
21
22
125
124
120
86
127
35
126
123
122
54
52
49
47
42
41
56
37
46
44
39
64
96
VSS
55
53
50
48
43
38
45
40
7
105
11
17
VSS
23
36
VSS
51
VSS
72
VSS
87
VSS
121
VSS
128
CHIPSET_ID0 CHIPSET_ID1
01
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
Small Form Factor Platform
1
C623
0.1U_0402_10V7K~D
2
DOCK_MIC_DET
MCH_TSATN_EC
1.8V_RUN_ON
SNIFFER_BLUE#
SNIFFER_YELLOW#
DOCK_HP_DET
CRT_SWITCH
ME_FWP
NB_AC_OFF
RUN_ON
IMVP_VR_ON
IMVP_PWRGD
0.75V_DDR_VTT_ON
+CAP_LDO
8mil
R600
12
1K_0402_5%~D
DOCK_AC_OFF_EC
SIO_SLP_S3#
LPC_LAD0
LPC_LAD1
LPC_LAD2
LPC_LAD3
LPC_LFRAME#
PLTRST2#
CLK_PCI_5028
CLKRUN#
LPC_LDRQ0# CLK_SIO_14M
LPC_LDRQ1#
IRQ_SERIRQ
CLK_SIO_14M
D_LAD0
D_LAD1
D_LAD2
D_LAD3
D_LFRAME#
D_CLKRUN#
D_DLDRQ1#
D_SERIRQ
RUNPWROK_R1
SP_TPM_LPC_EN
GPIO_PSID_SELECT
1
C630
4.7U_0603_6.3V4Z~D
2
TP_DET#
Note
1
C624
0.1U_0402_16V4Z~D
2
DOCK_MIC_DET <26>
MCH_TSATN_EC <10>
T109
SNIFFER_BLUE# <35>
SNIFFER_YELLOW# <35>
DOCK_HP_DET <26>
CRT_SWITCH <20>
ME_FWP <23>
NB_AC_OFF <40,46,47>
T102
T103
RUN_ON <20,21,27,37,45>
IMVP_VR_ON <43>
IMVP_PWRGD <24,43,44>
0.75V_DDR_VTT_ON <45>
SIO_SLP_S3# <24>
LPC_LAD0 <23,32,34>
LPC_LAD1 <23,32,34>
LPC_LAD2 <23,32,34>
LPC_LAD3 <23,32,34>
LPC_LFRAME# <23,32,34>
PLTRST2# <22,34>
CLK_PCI_5028 <6>
CLKRUN# <24,29,34>
LPC_LDRQ0# <23>
LPC_LDRQ1# <23>
IRQ_SERIRQ <24,29,32,34>
CLK_SIO_14M <6>
D_LAD0 <31>
D_LAD1 <31>
D_LAD2 <31>
D_LAD3 <31>
D_LFRAME# <31>
D_CLKRUN# <31>
D_DLDRQ1# <31>
D_SERIRQ <31>
R1121 10K_0402_5%~D
SP_TPM_LPC_EN <32>
GPIO_PSID_SELECT <40>
TP_DET# <36>
2
12
+3.3V_ALW
ACAV_IN_NB<34,46>
1
C625
0.1U_0402_16V4Z~D
2
C627
1
2
SNIFFER_BLUE#
SNIFFER_YELLOW#
TP_DET#
D_CLKRUN#
0.1U_0402_16V4Z~D
+3.3V_RUN
D_DLDRQ1#
D_SERIRQ
SP_TPM_LPC_EN
RUN_ON
0.75V_DDR_VTT_ON
+3.3V_ALW
0.1U_0402_16V4Z~D
5
2
P
A
Y
1
B
G
U96
3
74AHCT1G08GW_SOT353-5~D
4.7P_0402_50V8C~D@
C1359
1 2
4
CLK_PCI_5028
10_0402_5%~D@
R608
C629
R588 100K_0402_5%~D@
R589 100K_0402_5%~D@
R590 100K_0402_5%~D
12
12
12
12
R592 100K_0402_5%~D
12
R595 100K_0402_5%~D
12
R593 100K_0402_5%~D
12
R582 10K_0402_5%~D@
12
R597 100K_0402_5%~D
12
R602 100K_0402_5%~D
DOCK_AC_OFF <31>
12
10_0402_5%~D@
1
4.7P_0402_50V8C~D@
2
+3.3V_RUN
R606
10K_0402_5%~D
1 2
ME_FWP
R610
1 2
DELL CONFIDENTIAL/PROPRIETARY
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
SIO ECE5028
LA-4291P
33 49Friday, Decemb er 07, 2007
1
10K_0402_5%~D@
+3.3V_ALW
+3.3V_RUN
R607
C628
of
12
1
2
0.1
Page 34
5
+3.3V_ALW
1 2
R1081 2.2K_0402_5%~D
1 2
R1082 2.2K_0402_5%~D
1 2
R635 2.2K_0402_5%~D
1 2
R636 2.2K_0402_5%~D
D D
+5V_RUN
C C
JP1
7
G1
8
G2
ACES_85204-06001~D@
B B
JTAG
22P_0402_50V8J~D
A A
22P_0402_50V8J~D
12
R642 100K_0402_5%~D
12
R629 100K_0402_5%~D
12
R640 100K_0402_5%~D
12
R631 100K_0402_5%~D
1 2
R628 100K_0402_5%~D
12
R643 100K_0402_5%~D@
1 2
R657 4.7K_0402_5%~D
1 2
R659 4.7K_0402_5%~D
1 2
R660 4.7K_0402_5%~D
1 2
R664 4.7K_0402_5%~D
1 2
R654 100K_0402_5%~D
1 2
R656 100K_0402_5%~D
+3.3V_ALW
49.9_0402_1%~D
12
1
1
2
2
3
3
4
4
5
5
6
6
1
C646
1
1
2
2
2
1=JTAG interface Reset disabled
0=Reset JTAG interface
C650
12
C649
12
EC_FLASH_SPI_DIN
ALS_SMBDAT
ALS_SMBCLK
PBAT_SMBDAT
PBAT_SMBCLK
EC_SPI_CS#
BC_DAT_EMC4002
BC_DAT_ECE1088
BC_DAT_ECE1077
BC_DAT_ECE5028
LPC_LDRQ#_MEC5035
CLK_KBD
DAT_KBD
CLK_MSE
DAT_MSE
SUS_ON
ICH_ALW
10K_0402_5%~D
10K_0402_5%~D
10K_0402_5%~D
10K_0402_5%~D
12
12
12
R668
R670
R671
R669
+3.3V_ALW
R667
0.1U_0402_16V4Z~D
R673
MEC5035_XTAL1
Y4
32.768KHZ_12.5PF_1TJE125DP1~D
1 2
MEC5035_XTAL2
Place R678 close to U37
5
10K_0402_5%~D
12
100_0402_1%~D@
12
R678
1 2
33_0402_5%~D
1 2
JTAG_RST#
R672
JTAG_TDI
JTAG_TMS
JTAG_CLK
JTAG_TDO
BC_DAT_EMC4002<19>
BC_INT#_EMC4002<19>
BC_INT#_ECE1088<36>
BC_DAT_ECE1088<36>
BC_INT#_ECE1077<36>
BC_DAT_ECE1077<36>
BC_INT#_ECE5028<33>
BC_DAT_ECE5028<33>
BC_CLK_ECE5028<33>
MEC5035_XTAL2
EC_SPI_CS#
SPI_DIN_R3
PBAT_SMBDAT<40>
PBAT_SMBCLK<40>
ACAV_DOCK_SRC#<31,47>
KYBRD_BKLT_PWM<36>
BC_CLK_EMC4002<19>
BC_CLK_ECE1088<36>
BC_CLK_ECE1077<36>
EC_32KHZ_OUT<19>
+3.3V_ALW
ALS_SMBDAT<35>
ALS_SMBCLK<35>
CLK_TP_SIO<36>
DAT_TP_SIO<36>
CLK_KBD<31>
DAT_KBD<31>
CLK_MSE<31>
DAT_MSE<31>
SUS_ON<37>
BREATH_LED#<31,38>
ICH_ALW<37>
SIO_EXT_SMI#<24>
SIO_RCIN#<23>
IRQ_SERIRQ<24,29,32,33>
PLTRST2#<22,33>
CLK_PCI_5035<6>
LPC_LFRAME#<23,32,33>
LPC_LAD0<23,32,33>
LPC_LAD1<23,32,33>
LPC_LAD2<23,32,33>
LPC_LAD3<23,32,33>
CLKRUN#<24,29,33>
SIO_EXT_SCI#<24>
R674 0_0402_5%~D
CLK_PCI_5035
R675
10_0402_5%~D@
C651
4.7P_0402_50V8C~D@
U37
1
CS#
2
SO
3
WP#
4
GND
HOLD#
SCLK
VCC
Place close to pin 58
12
1
2
12
R676
3.3K_0402_5%~D
SST25VF016B-50-4C-S2AF_SO8~D@
4
ALS_SMBDAT
ALS_SMBCLK
CLK_TP_SIO
DAT_TP_SIO
CLK_KBD
DAT_KBD
CLK_MSE
DAT_MSE
PBAT_SMBDAT
PBAT_SMBCLK
JTAG_TDI
JTAG_TDO
JTAG_CLK
JTAG_TMS
JTAG_RST#
ACAV_DOCK_SRC#
SUS_ON
BREATH_LED#
ICH_ALW
KYBRD_BKLT_PWM
EC_SPI_CS#
BC_CLK_EMC4002
BC_DAT_EMC4002
BC_INT#_EMC4002
BC_INT#_ECE1088
BC_DAT_ECE1088
BC_CLK_ECE1088
BC_INT#_ECE1077
BC_DAT_ECE1077
BC_CLK_ECE1077
BC_INT#_ECE5028
BC_DAT_ECE5028
BC_CLK_ECE5028
SIO_EXT_SMI#
SIO_RCIN#
LPC_LDRQ#_MEC5035
IRQ_SERIRQ
PLTRST2#
CLK_PCI_5035
LPC_LFRAME#
LPC_LAD0
LPC_LAD1
LPC_LAD2
LPC_LAD3
CLKRUN#
SIO_EXT_SCI#
MEC5035_XTAL1
12
BLM18AG121SN1D_0603~D
0.1U_0402_16V4Z~D
12
R677
3.3K_0402_5%~D
8
7
SPI_CLK_R3
6
SPI_DO_R3
5
SI
4
0.1U_0402_16V4Z~D
1
2
VSS[1]26VSS[2]51VSS[3]74VSS[4]88VSS[5]
+3.3V_ALW
121
VBAT
VSS[7]
20
113
53
+RTC_CELL
C633
U36
PS/2 INTERFACE
9
GPIO007/I2C1D_DATA/PS2_CLK0B
10
GPIO010/I2C1D_CLK/PS2_DAT0B
75
GPIO110/PS2_CLK2/GPTP-IN6
76
GPIO111/PS2_DAT2/GPTP-OUT6
77
GPIO112/PS2_CLK1A
78
GPIO113/PS2_DAT1A
79
GPIO114/PS2_CLK0A
80
GPIO115/PS2_DAT0A
111
GPIO154/I2C1C_DATA/PS2_CLK1B
112
GPIO155/I2C1C_CLK/PS2_DAT1B
JTAG INTERFACE
102
GPIO145/I2C1K_DATA/JTAG_TDI
103
GPIO146/I2C1K_CLK/JTAG_TDO
105
GPIO147/I2C1J_DATA/I2C2C_DATA/JTAG_CLK
106
GPIO150/I2C1J_CLK/I2C2C_CLK/JTAG_TMS
107
JTAG_RST#
FAN PWM & TACH
41
GPIO050/FAN_TACH1
42
GPIO051/FAN_TACH2
43
GPIO052/FAN_TACH3
45
GPIO053/PWM0
46
GPIO054/PWM1
47
GPIO055/PWM2
48
GPIO056/PWM3
BC-LINK
23
GPIO022/BCM_B_CLK/V_CLK
24
GPIO023/BCM_B_DAT/V_DATA
25
GPIO024/BCM_B_INT#/V_FRAME
35
GPIO042/BCM_C_INT#
36
GPIO043/BCM_C_DAT
37
GPIO044/BCM_C_CLK
38
GPIO045/LSBCM_D_INT#
39
GPIO046/LSBCM_D_DAT
40
GPIO047/LSBCM_D_CLK
85
GPIO121/BCM_A_INT#
86
GPIO122/BCM_A_DAT
87
GPIO123/BCM_A_CLK
HOST INTERFACE
11
GPIO011/nSMI
54
GPIO061/LPCPD#
55
LDRQ#
56
SER_IRQ
57
LRESET#
58
PCI_CLK
59
LFRAME#
60
LAD0
61
LAD1
62
LAD2
63
LAD3
64
CLKRUN#
66
GPIO100/nEC_SCI
MASTER CLOCK
122
XTAL1
124
XTAL2
117
GPIO160/32KHZ_OUT
AGND
125
15 mil 8 mil 15 mil
1 2
L39
C652
33_0402_5%~D
33_0402_5%~D
+5035_AGND
12
Place R679,R680 close to U36
R679
1 2
1 2
R680
EC_FLASH_SPI_CLK
EC_FLASH_SPI_DO
116
104
52
VTR[1]21VTR[2]44VTR[3]65VTR[4]83VTR[5]
VTR[6]
VTR[7]4VTR[8]
GENERAL PURPOSE I/O
GPIO012/I2C1H_DATA/I2C2D_DATA
GPIO013/I2C1H_CLK/I2C2D_CLK
GPIO141/I2C1F_DATA/I2C2B_DATA
GPIO142/I2C1F_CLK/I2C2B_CLK
VSS[8]
VR_CAP[1]22VSS_RO
101
4.7U_0603_6.3V4Z~D
+VR_CAP
+5035_VSS
C648
1
1 2
BLM18AG121SN1D_0603~D
2
3
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
C634
C635
1
2
MISC INTERFACE
GPIO021/RC_ID
GPIO025/UART_CLK
GPIO060/KBRST
GPIO101/ECGP_SCLK
GPIO102/ECGP_SOUT
GPIO103/ECGP_SIN
GPIO104/UART_TX
GPIO105/UART_RX
GPIO106/nRESET_OUT
GPIO116/MSDATA
GPIO117/MSCLK
GPIO014/GPTP-IN7
GPIO015/GPTP-OUT7
GPIO016/GPTP-IN8
GPIO017/GPTP-OUT8
GPIO26/GPTP-IN1
GPIO27/GPTP-OUT1
GPIO30/GPTP-IN2
GPIO31/GPTP-OUT2
GPIO032/GPTP-IN3
GPIO040/GPTP-OUT3
GPIO124/GPTP-OUT5
GPIO125/GPTP-IN5
GPIO151/GPTP-IN4
GPIO152/GPTP-OUT4
SMBUS INTERFACE
GPIO003/I2C1A_DATA
GPIO004/I2C1A_CLK
GPIO005/I2C1B_DATA
GPIO006/I2C1B_CLK
GPIO130/I2C2A_DATA
GPIO131/I2C2A_CLK
GPIO132/I2C1G_DATA
GPIO140/I2C1G_CLK
GPIO143/I2C1E_DATA
GPIO144/I2C1E_CLK
DELL PWR SW INF
thermal GND
MEC5035_XVTQFP128_14X14~D
129
L38
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
C637
1
2
VCC_PRWGD
GPIO127/A20M
GPIO153/LED3
GPIO156/LED1
GPIO157/LED2
nFWP
GPIO001
GPIO002
GPIO020
GPIO041
GPIO107
GPIO120
GPIO126
BGPO0
VCI_IN2#
VCI_OUT
VCI_IN1#
VCI_IN0#
VCI_OVRD_IN
VCI_IN3#
3
0.1U_0402_16V4Z~D
C638
1
2
19
27
49
50
67
68
69
70
71
72
81
82
92
110
114
115
123
2
3
14
15
16
17
18
28
29
30
31
32
33
34
73
84
89
90
91
108
109
5
6
7
8
12
13
93
94
95
96
97
98
99
100
118
119
120
126
127
128
1
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
C639
1
1
2
2
RC_ID
DDR_ON
RUNPWROK
ICH_LAN_RST#
EC_FLASH_SPI_CLK
EC_FLASH_SPI_DO
EC_FLASH_SPI_DIN
HOST_DEBUG_TX
HOST_DEBUG_RX
RESET_OUT
MSDATA
MSCLK
SIO_A20GATE
PS_ID
BAT1_LED#
BAT2_LED#
FWP#
SIO_SLP_M#
DOCK_SMB_ALERT#
ME_WOL_EN
ME_SUS_PWR_ACK
1.5V_SUS_PWRGD
ICH_CL_PWROK
1.05V_M_PWRGD
ALW_PWRGD_3V_5V
SIO_SLP_S5#
BEEP
AUX_ON
AUX_EN_WOWL
SIO_SLP_S4#
M_ON
ICH_RSMRST#
AC_PRESENT
SIO_PWRBTN#
DOCK_SMB_DAT
DOCK_SMB_CLK
LCD_SMBDAT
LCD_SMBCLK
CKG_SMBDAT
CKG_SMBCLK
AMT_SMBDAT
AMT_SMBCLK
ACAV_IN_NB
CARD_SMBDAT
CARD_SMBCLK
BKT_SMBDAT
BKT_SMBCLK
SNIFFER/INST ANT_SW#
ALWON
POWER_SW_IN#
ACAV_IN
DOCK_PWR_SW#
C640
1
2
0.1U_0402_16V4Z~D
C641
0.1U_0402_16V4Z~D
10U_0805_10V4Z~D
C636
1
1
2
2
DDR_ON <10,37,45>
ICH_LAN_RST# <24>
HOST_DEBUG_TX <30>
HOST_DEBUG_RX <30>
RESET_OUT <10,24>
MSDATA <30>
MSCLK <30>
SIO_A20GATE <23>
PS_ID <40>
BAT1_LED# <38>
BAT2_LED# <38>
Bat2 = Amber LED
Bat1 = Blue LED
SIO_SLP_M# <24>
DOCK_SMB_ALERT# <31,40>
ME_WOL_EN <24>
ME_SUS_PWR_ACK <24>
1.5V_SUS_PWRGD <10,42>
ICH_CL_PWROK <10,24>
T106
1.05V_M_PWRGD <42>
ALW_PWRGD_3V_5V <41>
T107
SIO_SLP_S5# <24>
BEEP <26>
AUX_ON <28>
T108
AUX_EN_WOWL <30>
SIO_SLP_S4# <10,24>
M_ON <37>
ICH_RSMRST# <24>
AC_PRESENT <24>
SIO_PWRBTN# <24>
DOCK_SMB_DAT <31>
DOCK_SMB_CLK <31>
LCD_SMBDAT <20>
LCD_SMBCLK <20>
CKG_SMBDAT <6,26,46>
CKG_SMBCLK <6,26,46>
AMT_SMBDAT <24>
AMT_SMBCLK <24>
ACAV_IN_NB <33,46>
CARD_SMBDAT <30,35>
CARD_SMBCLK <30,35>
BKT_SMBDAT <21>
BKT_SMBCLK <21>
ALWON <41>
EN_CELL_CHARGER_DET# <35>
ACAV_IN <19,46>
+3.3V_M
RESET_OUT
2
G
2
RUNPWROK
12
R733
100K_0402_5%~D
ICH_PWRGD#
13
D
Q71
2N7002W-7-F_SOT323-3~D
S
2
POWER_SW_IN#<19>
R1123
10K_0402_5%~D
RC_ID
10K_0402_5%~D
12
R661
R663
HOST_DEBUG_RX
+RTC_CELL
0.1U_0402_16V4Z~D
5
P
A
4
Y
B
G
3
ICH_PWRGD# <19>
+RTC_CELL
+3.3V_RUN
12
+3.3V_ALW
C1360
100K_0402_5%~D
12
R662
C645
1 2
1
2
U47
74AHCT1G08GW SOT353~D
+RTC_CELL
R1110
1K_0402_5%~D
1 2
4700P_0402_25V7K~D
1
2
+3.3V_ALW
10K_0402_5%~D
12
MSDATA
MSCLK
Molex_53261
INSTANT_ON_SW# <33,35>
SNIFFER_PWR_SW# <35>
DELL CONFIDENTIAL/PROPRIETARY
Title
Size Document Number Rev
Date: Sheet
100K_0402_5%~D
12
R626
R630
1 2
1K_0402_5%~D
1
C642
1U_0603_10V4Z~D
2
100K_0402_5%~D
12
R638
R641
1 2
1K_0402_5%~D
1
C644
1U_0603_10V4Z~D
2
HOST_DEBUG_TX
DOCK_SMB_ALERT#
DOCK_SMB_DAT
DOCK_SMB_CLK
LCD_SMBDAT
LCD_SMBCLK
JDEG
5
5
CKG_SMBDAT
4
4
3
3
CKG_SMBCLK
2
2
1
1
CARD_SMBDAT
CARD_SMBCLK
BKT_SMBDAT
BKT_SMBCLK
INSTANT_ON_SW#
SNIFFER_PWR_SW#
SNIFFER/INST ANT_SW#
EN_CELL_CHARGER_DET#
DDR_ON
AUX_ON
M_ON
AC_PRESENT
Compal Electronics, Inc.
KBC/GPIO, MEC5035
LA-4291P
1
C632
1 2
1U_0402_6.3V6K~D@
POWER_SW#_MB <35,39>
C643
1 2
1U_0402_6.3V6K~D@
DOCK_PWR_BTN# <31>DOCK_PWR_SW#<19>
+3.3V_ALW
R652
10K_0402_5%~D
1 2
FWP#
R658
1 2
1 2
R639 10K_0402_5%~D
1 2
R632 10K_0402_5%~D
R653 2.2K_0402_5%~D
R655 2.2K_0402_5%~D
R634 2.2K_0402_5%~D
R633 2.2K_0402_5%~D
R624 2.2K_0402_5%~D
R627 2.2K_0402_5%~D
R644 2.2K_0402_5%~D
R645 2.2K_0402_5%~D
R1079 2.2K_0402_5%~D
R1080 2.2K_0402_5%~D
R647 100K_0402_5%~D
1 2
R649 100K_0402_5%~D
1 2
R1111 100K_0402_5%~D
1 2
R1090 100K_0402_5%~D
R651 100K_0402_5%~D
R650 2.7K_0402_5%~D
1 2
R648 1M_0402_5%~D
1 2
R665 10K_0402_5%~D
1
10K_0402_5%~D@
+3.3V_ALW
12
12
12
12
12
12
12
12
12
12
+RTC_CELL
12
12
12
34 49Friday, Decemb er 07, 2007
0.1
of
Page 35
5
Express Card
+1.5V_RUN
+3.3V_SUS
+3.3V_RUN
0.1U_0402_16V4Z~D
C511
C512
1
1
D D
+3.3V_SUS
R467 100K_0402_5%~D
1 2
R471 100K_0402_5%~D
1 2
R472 100K_0402_5%~D
1 2
EXPRCRD_PWREN#<33>
C C
2
2
PLTRST1#<10,22>
EXPRCRD_STDBY#<33>
0.1U_0402_16V4Z~D
C508
1
0.1U_0402_16V4Z~D
2
PLTRST1#
EXPRCRD_STDBY#
EXPRCRD_PWREN#
CPUSB#
U52
12
1.5Vin
14
1.5Vin
2
3.3Vin
4
3.3Vin
AUX_IN17AUX_OUT
6
SYSRST#
20
SHDN#
1
STBY#
10
CPPE#
9
CPUSB#
18
RCLKEN
R5538_QFN20~D
1.5Vout
1.5Vout
3.3Vout
3.3Vout
OC#
PERST#
GND
CARD_SMBDAT<30,34>
CARD_SMBCLK<30,34>
NC
AUDIO/B BTB connector, Left side
JAUDIO
2
2
4
4
6
6
8
8
10
10
12
12
14
14
16
16
18
18
20
20
22
22
24
24
26
26
28
28
30
30
32
32
34
34
36
36
38
38
40
40
42
42
44
44
46
46
48
48
50
50
FOX_QT510506-1010-7F
1
1
3
3
5
5
7
7
9
9
11
11
13
13
15
15
17
17
19
19
21
21
23
23
25
25
27
27
29
29
31
31
33
33
35
35
37
37
39
39
41
41
43
43
45
45
47
47
49
49
BKT_LED<21>
AUDIO_BD_DET#
BKT_LED
INSTANT_ON_SW#
CLK_DDC2_CRT
DAT_DDC2_CRT
+3.3V_RUN_BKT_PWR
+3.3V_RUN
+5V_RUN
ESATA_IRX_DTX_P4_C
ESATA_IRX_DTX_N4_C
ESATA_ITX_DRX_N4
ESATA_ITX_DRX_P4
+VREFOUT
AUD_HP_NB_ SENSE
HP_SPK_L1
HP_SPK_R1
AUDIO_BD_DET#<24>
INSTANT_ON_SW#<33,34>
CLK_DDC2_CRT<20>
DAT_DDC2_CRT<20>
ESATA_IRX_DTX_P4_C<23>
ESATA_IRX_DTX_N4_C<23>
ESATA_ITX_DRX_N4<23>
ESATA_ITX_DRX_P4<23>
AUD_MIC_SWITCH<26>
B B
AUD_HP_NB_SENSE<26,27,33>
HP_SPK_L1<27>
HP_SPK_R1<27>
4
+1.5V_CARD
0.1U_0402_16V4Z~D
C509
1
11
2
13
3
5
15
19
8
C517
16
7
DMIC_CLK
DMIC0
BLUE_CRT
GREEN_CRT
RED_CRT
HSYNC_BUF
VSYNC_BUF
USBP3+
USBP3-
ESATA_USB_PWR_EN#
ESATA_USB_OC#
AUD_EXT_MIC_L
AUD_EXT_MIC_R
DETECT GND
1
2
CARD_RESET#
+3.3V_SUS
+5V_ALW
+3.3V_CARD
0.1U_0402_16V4Z~D
C510
1
2
+3.3V_CARDAUX
0.1U_0402_16V4Z~D
6 1
Q9A
2N7002DW-7-F_SOT363-6~D
2
5
Q9B
2N7002DW-7-F_SOT363-6~D
3
4
DMIC_CLK <26>
DMIC0 <26>
BLUE_CRT <20>
GREEN_CRT <20>
RED_CRT <20>
HSYNC_BUF <20>
VSYNC_BUF <20>
USBP3+ <24>
USBP3- <24>
ESATA_USB_PWR_EN# <33>
ESATA_USB_OC# <24>
AUD_EXT_MIC_L <26>
AUD_EXT_MIC_R <26>
C513
0.1U_0402_16V4Z~D
1
2
+3.3V_SUS
C514
R465
3
2
1
IO/B connector, Right side
+1.5V_CARD
C503
1 2
0.1U_0402_16V4Z~D
R464
0_0402_5%~D
10U_0805_6.3V6M~D
0.1U_0402_16V4Z~D
C515
1
1
2
2
12
+3.3V_CARDAUX
C506
2.2K_0402_5%~D
2.2K_0402_5%~D
12
R466
EXP_SMBDATA
EXP_SMBCLK
1
2
EN_CELL_CHARGER_DET#<34>
+3.3V_CARD
0.1U_0402_16V4Z~D
C507
1
2
CELL_CHARGER_DET#<33>
USBP7-<24>
USBP7+<24>
0.1U_0402_16V4Z~D
1 2
1 2
0_0402_5%~D
PCIE_WAKE#<30,33>
EXPCLK_REQ#<6>
DET_PCCRD_EXPSCRD#<33>
CLK_PCIE_EXP#<6>
CLK_PCIE_EXP<6>
PCIE_IRX_EXPTX_N4<24>
PCIE_IRX_EXPTX_P4<24>
PCIE_ITX_EXPRX_N4_C<24>
PCIE_ITX_EXPRX_P4_C<24>
0_0402_5%~D
0_0402_5%~D
R463
R1091
R1092
USBP7_DUSBP7_D+
CPUSB#
EXP_SMBCLK
EXP_SMBDATA
PCIE_WAKE#
CARD_RESET#
EXPCLK_REQ#
EXPRCRD_PWREN#
CLK_PCIE_EXP#
CLK_PCIE_EXP
PCIE_IRX_EXPTX_N4
PCIE_IRX_EXPTX_P4
PCIE_ITX_EXPRX_N4_C
PCIE_ITX_EXPRX_P4_C
C1354
0.1U_0402_16V4Z~D
1 2
12
12
JEXP
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
20
21
21
22
22
23
23
24
24
25
25
26
26
27
27
28
28
29
30
MOLEX_52892-3019
CELL_CHARGER_DET_R#
31
29
GND1
32
30
GND2
JIO
GND
GND
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
MOLEX_54132-5062
52
51
IO_BD_DET#
50
POWER_SW#_MB
49
BREATH_BLUE_LED_PWR
48
LAN_ACTLED_YEL_R#
47
LED_10_GRN_R#
46
LED_100_ORG_R#
45
44
SW_LAN_TX0+
43
SW_LAN_TX0-
42
SW_LAN_TX1+
41
SW_LAN_TX1-
40
SW_LAN_TX2+
39
SW_LAN_TX2-
38
SW_LAN_TX3+
37
SW_LAN_TX3-
36
35
34
33
32
CELL_CHARGER_DET_R#
31
SW_USBP0-
30
SW_USBP0+
29
28
27
26
25
24
23
TPA0+
22
TPA0-
21
TPB0+
20
TPB0-
19
1394_DET#
18
USB_OC0#
17
16
15
CARD_EN
14
SDWP#
13
SDCD#_MMCCD#
12
SDCDAT1_MMCDAT1
11
SDCDAT0_MMCDAT0
10
SDCCLK_MMCCLK
9
MMCDAT7
8
DETECT GND
7
SDCCMD_MMCCMD
6
MMCDAT5
5
SDCDAT3_MMCDAT3
4
MMCDAT4
3
MMCDAT6
2
SDCDAT2_MMCDAT2
1
+5V_ALW
IO_BD_DET# <24>
POWER_SW#_MB <34,39>
BREATH_BLUE_LED_PWR <38>
LAN_ACTLED_YEL_R# <28>
LED_10_GRN_R# <28>
LED_100_ORG_R# <28>
SW_LAN_TX0+ <28>
SW_LAN_TX0- <28>
SW_LAN_TX1+ <28>
SW_LAN_TX1- <28>
SW_LAN_TX2+ <28>
SW_LAN_TX2- <28>
SW_LAN_TX3+ <28>
SW_LAN_TX3- <28>
+3.3V_LAN
+LOM_VCT
USB_POWERSHARE_PWR_EN# <33>
SW_USBP0- <24>
SW_USBP0+ <24>
TPA0+ <29>
TPA0- <29>
TPB0+ <29>
TPB0- <29>
1394_DET# <24>
USB_OC0# <24>
+3.3V_RUN
CARD_EN <29>
SDWP# <29>
SDCD#_MMCCD# <29>
SDCDAT1_MMCDAT1 <29>
SDCDAT0_MMCDAT0 <29>
SDCCLK_MMCCLK <29>
MMCDAT7 <29>
SDCCMD_MMCCMD <29>
MMCDAT5 <29>
SDCDAT3_MMCDAT3 <29>
MMCDAT4 <29>
MMCDAT6 <29>
SDCDAT2_MMCDAT2 <29>
SNIFFER connector and LED
+3.3V_ALW
+3.3V_ALW
SNIFFER_YELLOW#<33>
SNIFFER_BLUE#<33>
2
2
+5V_ALW
Q88
DDTA114EUA-7-F_SOT323-3~D
1 3
150_0402_5%~D
1 3
R758
1 2
220_0402_5%~D
Q86
DDTA114EUA-7-F_SOT323-3~D
R757
1 2
SNIFFER_YELLOW
SNIFFER_BLUE
SNIFFER_DET#<24>
SNIFFER_PWR_SW#<34>
WIRELESS_ON#/OFF<33>
LID_CL#<33,38>
0.1U_0402_16V4Z~D
2
1
FP_SW_USBD-<21>
FP_SW_USBD+<21>
BIO_DET#<24>
FP_RESET#<32>
+3.3V_RUN_BKT_PWR
C717
SNIFFER_DET#
SNIFFER_PWR_SW#
WIRELESS_ON#/OFF
SNIFFER_BLUE
SNIFFER_YELLOW
FP_SW_USBDFP_SW_USBD+
BIO_DET#
FP_RESET#
DETECT GND
JSNIFF
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
GND
16
GND
MOLEX_52893-1419
1.8" Micro SATA HDD connector
PJP2
+3.3V_HDD
HDD_DET#
PSATA_IRX_DTX_P0
PSATA_IRX_DTX_N0
PSATA_ITX_DRX_N0
PSATA_ITX_DRX_P0
HDD_DET#<24>
1 2
PAD-OPEN 4x4m
+3.3V_RUN
PSATA_IRX_DTX_P0_C<23>
PSATA_IRX_DTX_N0_C<23>
+3.3V_HDD
10U_0805_10V4Z~D
C770
A A
1
C340
2
C769 0.01U_0402_16V7K~D
C768 0.01U_0402_16V7K~D
0.1U_0402_16V4Z~D
1
1
C341
2
2
12
12
PSATA_ITX_DRX_N0<23>
PSATA_ITX_DRX_P0<23>
0.1U_0402_16V4Z~D
JHDD
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
GND1
14
GND2
MOLEX_52893-1219
CAP Switch and ALS connector
+3.3V_RUN_BKT_PWR
ALS_SMBDAT<34>
ALS_SMBCLK<34>
ALS_SMBDAT CAPSW_ALS_SMBDAT
2N7002DW-7-F_SOT363-6~D
6 1
Q119A
2N7002DW-7-F_SOT363-6~D
+3.3V_RUN_BKT_PWR
2
5
3
Q119B
2.2K_0402_5%~D
2.2K_0402_5%~D
12
12
R1083
R1084
CAP_SW_SMB_INT#<33>
4
CAPSW_ALS_SMBCLKALS_SMBCLK
SW_BD_DET#<33>
DETECT GND
+3.3V_RUN_BKT_PWR
CAP_SW_SMB_INT#
CAPSW_ALS_SMBDAT
CAPSW_ALS_SMBCLK
+5V_RUN_BKT_PWR
JSW
12
G2
11
G1
10
10
9
9
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
MOLEX_52746-1070
DELL CONFIDENTIAL/PROPRIETARY
Place close to JHDD
5
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
4
3
2
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
Express Card, HDD, Sniffer, IO CONN
LA-4291P
35 49Friday, Decemb er 07, 2007
1
of
0.1
Page 36
5
4
3
2
1
GPIO Expander for BlackTop
+3.3V_ALW
0.1U_0402_16V4Z~D
C664
1
2
R687
1K_0402_5%~D
+3.3V_ALW
0.1U_0402_16V4Z~D
1
2
30
10
39
37
38
34
35
36
40
12
41
U51
VCC1
VCC1
NC3
ECE1077
NC1
NC2
BC_DATA
BC_CLK
BC_INT#
TEST_PIN
GND_PAD
ECE1077-FZG_QFN40~D
KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15
KSO16/GPIO_0
KSO17/GPIO_1
KSO18/GPIO_2
KSO19/GPIO_3
KSO20/GPIO_4
KSO21/GPIO_5
KSO22/GPIO_6
KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7
KSO0
9
KSO1
11
KSO2
12
KSO3
13
KSO4
14
KSO5
15
KSO6
16
KSO7
17
KSO8
18
KSO9
19
KSO10
20
KSO11
21
KSO12
22
KSO13
23
KSO14
24
KSO15
25
KSO16
26
KSO17
27
28
29
31
32
33
KSI0
1
KSI1
2
KSI2
3
KSI3
4
KSI4
5
KSI5
6
KSI6
7
KSI7
8
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
C654
C653
1
1
2
12
12
12
2
BC_DAT_ECE1088
BC_CLK_ECE1088
BC_INT#_ECE1088
D D
BC_DAT_ECE1088<34>
BC_CLK_ECE1088<34>
BC_INT#_ECE1088<34>
+3.3V_ALW
R683 10K_0402_5%~D@
R684 10K_0402_5%~D
R685 10K_0402_5%~D
U38
VCC
21
VCC
22
BC_DAT/SMB_DATA
23
BC_CLK/SMB_CLK
24
BC_INT#/SMB_INT#
25
SMB_ADDR
28
TEST
27
RESERVE
29
THER_PAD
ECE1088-FZG_QFN28_5X5~D
ECE1088
7
GPIO00
GPIO01
GPIO02
GPIO03
GPIO07
GPIO13
GPIO14
GPIO15
GPIO16
GPIO17
GPIO20
GPIO24
GPIO25
GPIO26
GPIO27
GPIO30
GPIO31
GPIO32
GPIO36
GPIO37
17
18
19
20
26
1
2
3
4
5
6
8
9
10
11
12
13
14
15
16
BKT_GPIO1
BKT_GPIO2
BKT_GPIO3
BKT_GPIO4
BKT_GPIO5
BKT_GPIO6
BKT_GPIO7
BKT_GPIO8
BKT_GPIO9
BKT_GPIO11
BKT_GPIO14
BKT_GPIO15
BKT_GPIO16
BKT_GPIO19
BKT_GPIO1 <20>
BKT_GPIO2 <20,21>
BKT_GPIO3 <21>
BKT_GPIO4 <21>
BKT_GPIO5 <21>
BKT_GPIO6 <21>
BKT_GPIO7 <21>
BKT_GPIO8 <21>
BKT_GPIO9 <21>
BKT_GPIO11 <26>
BKT_GPIO14 <20>
BKT_GPIO15 <21>
BKT_GPIO16 <21>
BKT_GPIO19 <21>
C663
BC_DAT_ECE1077<34>
BC_CLK_ECE1077<34>
BC_INT#_ECE1077<34>
BC_DAT_ECE1077
BC_CLK_ECE1077
BC_INT#_ECE1077
Touch Pad connector
+5V_RUN_BKT_PWR
4.7K_0402_5%~D
C C
R682
CLK_TP_SIO<34>
DAT_TP_SIO<34>
CLK_TP_SIO
DAT_TP_SIO
C659
4.7K_0402_5%~D
12
12
R681
10P_0402_50V8J~D
10P_0402_50V8J~D
C658
1
1
2
2
L41
BLM18AG601SN1D_0603~D
BLM18AG601SN1D_0603~D
12
12
L40
C657
TP_DET#<33>
TP_CLK
10P_0402_50V8J~D
10P_0402_50V8J~D
1
2
C656
1
2
+5V_RUN_BKT_PWR
TP_DATA
C660
TP_DET#
0.1U_0402_16V4Z~D
SD05.TCT_SOD323-2~D@
1
D27
2
SD05.TCT_SOD323-2~D@
D28
2 1
2 1
JTP
1
1
2
2
3
3
4
4
5
5
6
6
7
GND
8
GND
TYCO_1734242-6
JKYBD
KB_DET#
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
20
21
21
22
22
23
23
24
24
25
25
26
26
27
27
GND
28
28
GND
IPEX_20413-028E
Keyboard Back l i g h t connector
KYBRD_BKLT_PWM<34>
KYBRD_BKT_DET#<24>
29
30
+5V_RUN_BKT_PWR
KYBRD_BKLT_PWM
KYBRD_BKT_DET#
JKBBKT
1
1
2
2
3
3
4
4
5
GND
6
GND
MOLEX_52745-0459
C668
KB_DET#<24>
DETECT GND
100P_0402_50V8J~D@
100P_0402_50V8J~D@
C689
1
1
2
2
B B
A A
KSI7
KSI6
KSI4
KSI2
KSI5
KSI1
KSI3
KSI0
KSO5
KSO4
KSO7
KSO6
KSO8
KSO3
KSO1
KSO2
KSO0
KSO12
KSO16
KSO15
KSO13
KSO14
KSO9
KSO11
KSO10
KSO17
100P_0402_50V8J~D@
C1333
C669
1
2
100P_0402_50V8J~D@
100P_0402_50V8J~D@
C670
1
2
100P_0402_50V8J~D@
C672
C671
1
1
2
2
100P_0402_50V8J~D@
100P_0402_50V8J~D@
C673
C674
1
1
2
2
100P_0402_50V8J~D@
100P_0402_50V8J~D@
C675
1
2
100P_0402_50V8J~D@
C676
C677
1
1
2
2
100P_0402_50V8J~D@
100P_0402_50V8J~D@
C678
C679
1
1
2
2
100P_0402_50V8J~D@
100P_0402_50V8J~D@
C680
1
2
100P_0402_50V8J~D@
C682
C681
1
1
2
2
100P_0402_50V8J~D@
100P_0402_50V8J~D@
C683
C684
1
1
2
2
100P_0402_50V8J~D@
100P_0402_50V8J~D@
C685
C686
1
1
2
2
100P_0402_50V8J~D@
100P_0402_50V8J~D@
C687
1
2
100P_0402_50V8J~D@
C688
C665
1
1
2
2
100P_0402_50V8J~D@
100P_0402_50V8J~D@
C666
1
2
100P_0402_50V8J~D@
C667
1
1
2
2
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
Keyboard,TouchPad and GPIO expander
LA-4291P
36 49Friday, Decemb er 07, 2007
1
of
0.1
Page 37
5
4
3
2
1
+5VRUN/+3.3V_RUN/+1.05V_VCCP/+1.5V_RUN Source+3.3V_ALW_ICH Source
Q51
+15V_ALW
+3.3V_ALW2
D D
ICH_ALW<34>
12
R691
100K_0402_5%~D
61
Q15A
2N7002DW-7-F_SOT363-6~D
2
ALW_ON_3.3V#
5
+3.3V_ALW
12
R688
100K_0402_5%~D
ALW_ENABLE
3
Q15B
2N7002DW-7-F_SOT363-6~D
4
SI3456BDV-T1-E3_TSOP6~D
D
6
S
45
2
1
G
3
1
C692
4700P_0402_25V7K~D
2
+3.3V_ALW_ICH
C690
1
2
10U_0805_10V4Z~D
R690
20K_0402_5%~D
12
RUN_ON<20,21,27,33,45>
+3.3V_ALW2
12
R692
100K_0402_5%~D
RUN_ON_ENABLE#
61
Q19A
2N7002DW-7-F_SOT363-6~D
2
+3.3V_SUS Source
+15V_ALW +3.3V_SUS
+3.3V_ALW2
12
R696
100K_0402_5%~D
C C
SUS_ON<34>
61
Q16A
2N7002DW-7-F_SOT363-6~D
2
SUS_ON_3.3V#
5
+3.3V_ALW
12
R694
100K_0402_5%~D
SUS_ENABLE
3
Q16B
2N7002DW-7-F_SOT363-6~D
4
Q53
STS11NF30L_SO8~D
8
7
5
1
2
36
C694
4
1
C696
4700P_0402_25V7K~D
2
10U_0805_10V4Z~D
20K_0402_5%~D
12
R695
1
2
+3.3V_M Source
Q55
+15V_ALW
+3.3V_ALW2
12
R702
100K_0402_5%~D
M_ON_3.3V#
61
B B
M_ON<34>
Q17A
2N7002DW-7-F_SOT363-6~D
2
5
+3.3V_ALW
12
R701
100K_0402_5%~D
M_ENABLE
3
Q17B
2N7002DW-7-F_SOT363-6~D
4
SI3456BDV-T1-E3_TSOP6~D
D
6
S
45
2
1
G
3
1
C700
4700P_0402_25V7K~D
2
C698
+3.3V_M
10U_0805_10V4Z~D
20K_0402_5%~D
12
R703
1
2
+15V_ALW
12
R689
100K_0402_5%~D
3
Q19B
2N7002DW-7-F_SOT363-6~D
5
4
+15V_ALW
12
R697
100K_0402_5%~D
13
D
2
G
S
+15V_ALW
12
R704
100K_0402_5%~D
13
D
2
G
S
+15V_ALW
12
R1069
100K_0402_5%~D
13
D
2
G
S
Q113
2N7002W-7-F_SOT323-3~D
Q114
2N7002W-7-F_SOT323-3~D
Q115
2N7002W-7-F_SOT323-3~D
+5V_ALW
RUN_ENABLE
R700
1 2
0_0402_5%~D
R709
1 2
0_0402_5%~D
R1071
1 2
0_0402_5%~D
Q52
STS11NF30L_SO8~D
8
7
5
8
7
5
8
7
5
8
7
5
4
1
C693
2200P_0402_50V7K~D
2
Q54
SI4336DY-T1-E3_SO8~D
4
1
C697
470P_0402_50V7K~D
2
Q56
SI4336DY-T1-E3_SO8~D
4
1
C701
470P_0402_50V7K~D
2
Q118
SI4336DY-T1-E3_SO8~D
4
1
C1350
470P_0402_50V7K~D
2
+5V_RUN
1
10U_0805_10V4Z~D
2
36
C691
1
2
36
C695
1
2
36
C699
1
2
36
C1349
20K_0402_5%~D
12
R693
1
2
+3.3V_RUN+3.3V_ALW
10U_0805_10V4Z~D
20K_0402_5%~D
12
R698
1
2
+1.05V_VCCP+1.05V_M
10U_0805_10V4Z~D
20K_0402_5%~D
12
R705
1
2
+1.5V_RUN+1.5V_MEM
10U_0805_10V4Z~D
20K_0402_5%~D
12
R1070
1
2
Level shifter for +1.05V_M and +1.5V_MEM PWM IC
+5V_ALW
+5V_ALW
R1074
1 2
61
M_ON
A A
2
R1073
4.7K_0402_5%~D
4.7K_0402_5%~D
1 2
EN_1.05VALW
3
Q116B
5
2N7002DW-7-F_SOT363-6~D
4
Q116A
2N7002DW-7-F_SOT363-6~D
EN_1.05VALW <42>
DDR_ON
DDR_ON<10,34,45>
2
+5V_ALW
+5V_ALW
4.7K_0402_5%~D
R1076
1 2
5
61
Q117A
2N7002DW-7-F_SOT363-6~D
R1075
4.7K_0402_5%~D
1 2
EN_1.5VALW
3
Q117B
2N7002DW-7-F_SOT363-6~D
4
EN_1.5VALW <42>
Discharg Circuit
+3.3V_SUS +3.3V_RUN
12
R718
1K_0402_5%~D@
13
SUS_ON_3.3V# RUN_ON_ENABLE#
D
Q64
2
2N7002W-7-F_SOT323-3~D@
G
S
12
R716
1K_0402_5%~D@
13
D
Q62
2
2N7002W-7-F_SOT323-3~D@
G
S
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
POWER CONTROL
LA-4291P
37 49Friday, Decemb er 07, 2007
1
0.1
of
Page 38
5
Keyboard Statu s, Num Lock/Caps Lock/Scroll Lock LEDs
+5V_ALW
NUM_LED#<33>
D D
CAP_LED#<33>
SCRL_LED#<33>
2
1 3
2
2
1 3
Q76
DDTA114EUA-7-F_SOT323-3~D
Q74
DDTA114EUA-7-F_SOT323-3~D
1 3
R741 150_0402_5%~D
Q75
DDTA114EUA-7-F_SOT323-3~D
1 2
R744 150_0402_5%~D
1 2
R745 150_0402_5%~D
1 2
HDD LED
+3.3V_RUN
12
R742
10K_0402_5%~D
D
S
SATA_ACT#
C C
SATA_ACT#_R<23>
MASK_BASE_LEDS#
13
Q78
G
2N7002W-7-F_SOT323-3~D
2
+5V_RUN
2
Q77
PDTA114EU_SC70-3~D
1 3
R747
1 2
150_0402_5%~D
WLAN LED
+3.3V_WLAN
12
R749
100K_0402_5%~D
D
S
LED_WLAN_OUT#<30>
MASK_BASE_LEDS#
B B
13
Q82
G
2N7002W-7-F_SOT323-3~D
2
+5V_RUN
2
Q81
PDTA114EU_SC70-3~D
1 3
R751
1 2
150_0402_5%~D
WWAN LED
+3.3V_RUN_BKT_PWR
12
R753
100K_0402_5%~D
LED_WWAN_OUT#<30>
MASK_BASE_LEDS#
D
S
13
Q84
G
2N7002W-7-F_SOT323-3~D
2
+5V_RUN_BKT_PWR
2
1 3
Q83
PDTA114EU_SC70-3~D
R754
1 2
150_0402_5%~D
BLUETOOTH LED
+3.3V_RUN
C1337
12
A2Y
10K_0402_5%~D
0.1U_0402_16V4Z~D
5
1
P
NC
BT_ACTIVE_R#
4
G
U87
74LVC1G14GV_SOT753-5
3
MASK_BASE_LEDS#
D
S
13
Q80
G
2N7002W-7-F_SOT323-3~D
2
A A
BT_ACTIVE<30>
R748
5
12
4
3
2
1
POWER/SUSPE ND breathing LED
R_NUM_LED
R_CAP_LED
R_SCRL_LED
BREATH_LED#<31,34>
NC7SZ04P5X_NL_SC70-5~D
U88
+3.3V_ALW
5
P
A2Y
G
3
C1338
0.1U_0402_16V4Z~D
1
NC
4
+3.3V_ALW
61
Q98A
2N7002DW-7-F_SOT363-6~D
2
+3.3V_ALW
61
Q99A
2N7002DW-7-F_SOT363-6~D
2
12
R1046
100K_0402_5%~D
MASK_BASE_LEDS#
12
R1048
100K_0402_5%~D
SYS_LED_MASK#
Q98B
2N7002DW-7-F_SOT363-6~D
4
5
Q99B
2N7002DW-7-F_SOT363-6~D
4
5
+5V_ALW
3
2
3
2
Q102
DDTA114EUA-7-F_SOT323-3~D
R1047
1 3
1 2
+5V_ALW
150_0402_5%~D
Q103
DDTA114EUA-7-F_SOT323-3~D
R1049
1 3
1 2
150_0402_5%~D
BREATH_BLUE_LED_PWR <35>
BREATH_BLUE_LED <20>
LED_BD_DET#<24>
SATA_LED
BATT_BLUE_LED
BATT_YELLOW_LED
WLAN_LED
BT_LED
WWAN_LED
R_NUM_LED
R_CAP_LED
R_SCRL_LED
DETECT GND
JLED
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
GND1
14
GND2
TYCO_1-1775784-2
BATTERY LED
R1050
100K_0402_5%~D@
61
3
5
Q100B
2N7002DW-7-F_SOT363-6~D
4
R1053
1 2
100K_0402_5%~D@
+3.3V_ALW
12
R1055
SYS_LED_MASK#
1 2
+5V_ALW
12
R1052
SYS_LED_MASK#
100K_0402_5%~D
2N7002W-7-F_SOT323-3~D
100K_0402_5%~D
2
S
SATA_LED
WLAN_LED
WWAN_LED
+5V_ALW
Q100A
2
MASK_BASE_LEDS#
+3.3V_ALW
C1339
0.1U_0402_16V4Z~D
5
1
P
BAT2_LED#<34>
MASK_BASE_LEDS#
+3.3V_ALW
5
BAT1_LED#<34>
P
A2Y
G
3
NC
A2Y
G
U89
NC7SZ04P5X_NL_SC70-5~D
3
C1340
0.1U_0402_16V4Z~D
1
BAT1_LED
NC
4
U90
NC7SZ04P5X_NL_SC70-5~D
2N7002DW-7-F_SOT363-6~D
BAT2_LED
4
+3.3V_ALW
61
Q101A
2
2N7002DW-7-F_SOT363-6~D
3
5
4
Q101B
2N7002DW-7-F_SOT363-6~D
LED Circuit C ontrol Table
+5V_RUN
BT_ACTIVE#BT_ACTIVE
2
4
Q79
DDTA114EUA-7-F_SOT323-3~D
1 3
R750
1 2
150_0402_5%~D
BT_LED
Mask All LEDs (Sniffer Function)
Mask Base MB LEDs (Lid Closed)
Do not Mask LEDs (Lid Opened)
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
SYS_LED_MASK#
0
1
11
+5V_ALW
2
1 3
150_0402_5%~D
Q106
2N7002W-7-F_SOT323-3~D
Q109
G
D
S
13
G
2
DDTA114EUA-7-F_SOT323-3~D
+3.3V_ALW
Q107
DDTA114EUA-7-F_SOT323-3~D
1 3
R1054
1 2
150_0402_5%~D
D
13
2
DDTA114EUA-7-F_SOT323-3~D
LID_CL#
X
0
2
Q104
DDTA114EUA-7-F_SOT323-3~D
R1051
1 2
2
SYS_LED_MASK#<33>
+3.3V_ALW
Q108
LID_CL#<33,35>
+5V_ALW
2
Q105
1 3
BATT_BLUE_LED
BATT_YELLOW_LED
1 3
R1056
1 2
150_0402_5%~D
R1057
1 2
150_0402_5%~D
SYS_LED_MASK#
LID_CL#
BATT_BLUE <20>
BATT_YELLOW <20>
+3.3V_ALW
5
2
P
A
1
B
G
3
0.1U_0402_16V4Z~D
Y
C1341
MASK_BASE_LEDS#
4
U91
74AHCT1G08GW_SOT353-5~D
DELL CONFIDENTIAL/PROPRIETARY
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
System LEDs Control
LA-4291P
1
38 49Friday, Decemb er 07, 2007
0.1
of
Page 39
5
4
3
2
1
Power button switch for debug
D D
PWR_SW1
112
PWR_SW2
112
2
2
FD1
1
FIDUCIAL MARK~D
Fiducial Mark
FD2
1
FIDUCIAL MARK~D
FD3
1
FIDUCIAL MARK~D
FD4
1
FIDUCIAL MARK~D
POWER_SW#_MB<34,35>
100P_0402_50V8J~D@
C655
1
2
Place on Top
Place on Bottom
C C
MB_PCB
BARE PCB
1
NC
Minicooper_LA-4291P REV0_M/B~D
H2
H_4P0
H12
H_2P2
H3
H_1P2
1
1
H13
H_2P2
1
1
H1
H_4P0
1
H11
H_2P2
1
B B
H4
H_1P2
H14
H_2P2
H5
H6
H7
H8
H9
H_3P25
H_2P2
H_2P3
H_2P1
1
1
1
1
H15
H_3P25
1
1
1
H_2P2
1
H10
H_2P6x2P1
1
A A
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
Standoff and EE Design Part
LA-4291P
1
39 49Friday, Decemb er 07, 2007
0.1
of
Page 40
5
4
3
2
1
+COINCELL
12
+3.3V_ALW
PD3
DA204U_SOT323~D@
12
ESD Diodes
2
3
1
PR5
100_0402_5%~D
1 2
2
3
PD4
1
DA204U_SOT323~D@
3
1
2
1
2
PD5
DA204U_SOT323~D@
3
@
PD7
SM24_SOT23
PBAT_SMBCLK <34>
PBAT_SMBDAT <34>
PR10
1 2
100K_0402_1%~D
PR12
1 2
15K_0402_1%~D
PR7
@
1 2
0_0402_5%~D
1 3
2
B
FBMA-L18-453215-900LMA90T_1812~D
1 2
1 2
12
PAD-OPEN 4x4m
PC2
<BOM Structure>
0.1U_0603_25V7K~D
PR9
33_0402_5%~D
D
S
1 2
PQ4
FDV301N_SOT23~D
G
2
C
PQ5
MMST3904-7-F_SOT323~D
E
3 1
PL1
PJP6
+3.3V_ALW
PBATT+
2
3
PD6
DA204U_SOT323~D
1
+5V_ALW
12
PR11
10K_0402_1%~D
PR13
1 2
10K_0402_5%~D@
12
PR2
10K_0402_1%~D
PBAT_PRES# <33>
PD22
RB751V_SOD323~D
21
PR334
1 2
0_0402_5%~D
DOCK_PSID<31> GPIO_PSID_SELECT <33>
NB_PSID _TS5A63157
PSID_ DISAB LE# <33>
SLICE_BAT_PRES#<31, 33,47>
+3.3V_ALW+5V_ALW
PR8
1 2
2.2K_0402_5%~D
D D
2
3
Primary Battery Connector
PD2
DA204U_SOT323~D@
PJBATT
11
GND
10
GND
9
9
8
8
7
7
6
6
12
PC3
SUYIN_2 00277MR009G 515ZR
2200P_0402_50V7K~D
C C
B B
5
5
4
4
3
3
2
2
1
1
@
1K_0402_1%~D
1 2
PR331
PD21
@
Z4304
Z4305
Z4306
NB_PSID
+3.3V_ALW
DA204U_SOT323~D
3
100_0402_5%~D
2
1
1
PR3
100_0402_5%~D
1 2
BLM18BD102SN1D_0603~D
DCIN _CBL_DET# <33>
PR4
1 2
PL2
+3.3V_RTC_LDO
BAT54CW_SOT 323~D
PQ44
NTR4502PT1G_SOT23-3~D
1
3
1 3
2
2
1
2
Z4012
3
2
PD1
1
27.4
DOCK_SMB_ALERT# <31,34>
PU1
NO
GND
NC3COM
TS5A63157DCKR_SC70-6~D
COIN RTC Battery
PR1
1K_0402_5%~D
1
2
6
IN
5
V+
4
+RTC_CELL
PC1
1U_0603_10V4Z~D
Move to power schematic
+5V_ALW
PS_I D <34>
RTC_BAT_DET_R#<23>
+COINCELL
PJRTC
1
1
2
2
3
3
4
GND
5
GND
MOLEX_53780-0370~D
1 2
PC177
@
.47U_0402_6.3V6-K~D
PL3
FBMJ4516HS720NT_1806~D
1 2
1
12
PC11
0.1U_0603_25V7K~D
12
PC9
2
0.1U_0603_25V7K~D
PL4
FBMJ4516HS720NT_1806~D
1 2
NB_AC_OFF_BJT<47>
PJDCIN
1
1
2
2
-DCIN_JACK
3
3
4
4
5
5
+DCIN_JACK
6
6
A A
MOLEX_87438-0643
5
PD9
@
12
VZ0603M260APT_0603
PC10
@
0.1U_0603_25V7K~D
IMD2AT- 108_SC74-6~D
12
PR16
0_0402_5%~D
@
5
+DC_IN
PQ1B
@
43
2
16
@
PQ1A
IMD2AT- 108_SC74-6~D
PC4
1 2
0.1U_0805_25V7K
+DC_IN
1
2
3 6
12
PR14
1M_0402_5%~D
4
PQ6
FDS6679AZ_SO8~D
4
12
PR17
1M_0402_5%~D
DC_IN+ Source
8
7
5
12
PC5
0.1U_0603_25V7K~D
12
PR18
22K_0402_5%~D
13
D
PQ7
S
RHU002N06_SOT323
2
G
100K_0402_5%~D
1 2
12
PC12
0.1U_0603_25V7K~D
PC6
PR332
+DC_IN_SS
12
PC7
0.1U_0603_25V7K~D
12
12
PC8
PR15
4.7K_0805_5%~D
10U_1206_25V6M~D
NB_AC_O F F <33,46,47>
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVIS ION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INF ORMATION IT CONT AINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WR ITT EN CO NSE NT OF COMPAL ELECTRONICS, INC.
3
DELL CONFIDENTIAL/PROPRIETARY
Title
Size Document N u mb er R e v
2
Date: Sheet
Compal Electronics, Inc.
+DCIN
LA-4291P
1
40 49Friday, De ce mb er 07, 2007
0.1
of
12
0.1U_0603_25V7K~D
Page 41
5
4
3
2
1
+3.3V_ALWP/ +5V_ALWP/ +5V_ALW2 / +15V_ALWP
D D
C C
B B
A A
+PWR_SRC
5 Volt +/-5%
Thermal Design Current:7.39A
Peck current: 10.55A
OCP min: 11A
+5V_ALWP
1
+
PC32
2
330U_D3L_6.3V_R18~D
VOUT1=5V
L=2.2uF
Fsw=400KHz
D=0.256
Output Ripple Current=4.23A
Output Ripple Voltage=4.23A*18mOhm=76.14mV
+5V_ALWP
+3.3V_ALWP
12
PC34
0.1U_0402_10V7K~D
1 2
PAD-OPE N 4x4m
1 2
PAD-OPE N 4x4m
PJP7
1 2
PAD-OPE N 4x4m
PR30
@
0_0603_5%~D
1 2
PR34
0_0603_5%~D
1 2
GNDA_3V5V
PJP11
PJP13
5
2.2UH_MPLC1040L2R2_11A_20%~D
+5V_ALW
+3.3V_ALW
+DC1_PWR_SRC
12
PR22
PR23
PC27
1 2
PR25
PR21
@
10_0603_5%~D
32
31
30
29
28
27
26
+3.3V_ALW_PHASE+5V_ALW_PHASE
25
1_0603_5%~D
1 2
1 2
PAD-OPEN1x1m
+5V_VCC1
12
12
PC26
1U_0603_10V6K~D
GNDA_3V5V
PR27
154K_0402_1%~D
1 2
PR29 0_0402_5%~D
12
POK_3.3V
EN_3V_5VEN_3V_5V
+3.3V_ALW_UGATE
12
PR33
+3.3V_ALW_LGATE
PJP9
PC31
12
PR24
0_0402_5%~D
@
0_0402_5%~D
0.1U_0603_25V7K~D
PR26
12
GNDA_3V5V
GNDA_3V5V
12
PC28
@
0.1U_0402_10V7K~D
+3.3V_ALW
PR36
1 2
100K_0402_1%~D
POK_3.3V
ALW_PWRGD_3V _5V
+3.3V_ALW
PR37
@
PR39
12
PC13
2200P_0402_50V7K~D
5
PQ9
3
241
FDMC8878_1N_POWER33-8~D
2.2UH_MPLC1040L2R2_11A_20%~D
5
3
241
1 2
100K_0402_1%~D
12
0_0402_5%~D
12
PQ11
1 2
FDMC8854_1N_POWER33-8~D
PC179
@
1000P_0603_50V7K~D
PR336
@
2.2_0805_1%~D
ALW_P WRGD_3V_5V <34>
12
12
PC15
PC14
0.1U_0805_50V7K
10U_1206_25V6M~D
PL6
12
VOUT2=3.3V
L=2.2uF
Fsw=500KHz
D=0.169
Output Ripple Current=2.49A
Output Ripple Voltage=2.49A*25mOhm=62.25mV
12
12
PC17
PC16
10U_1206_25V6M~D
10U_1206_25V6M~D
3.3 Volt +/-5%
Thermal Design Current: 6.73A
Peak current: 9.62A
OCP min: 11A
+3.3V_ALWP
1
PR31
0_0603_5%~D
PR35
@
0_0603_5%~D
GNDA_3V5V
1 2
1 2
PC35
12
+
PC33
0.1U_0402_10V7K~D
2
330U_D2E_6.3VM_R25~D
PJP8
1 2
PR20
0_0805_5%
1 2
PR354
+5V_ALWP
GNDA_3V5V
PR32
1_0603_5%~D
1 2
+5V_ALW_LGATE
PC36
0.1U_0603_25V7K~D
1 2
1
PC39
0.1U_0603_25V7K~D
1
1 2
12
PC40
0.1U_0603_25V7K~D
+5V_ALW2
12
PC25
0_0402_5%~D
1U_0603_10V6K~D
GNDA_3V5V
PU2
9
VSW
10
VOUT1
11
VFB1
12
TRIP1
13
PGOOD1
14
EN1
15
DRVH1
16
LL1
33
+5V_ALW_BOOT
3
PR42
200K_0402_1%~D
12
7
8
LDO
LDOREFIN
VBST117DRVL118V5DRV19SECFB20GND21PGND22DRVL223VBST2
PAD
PD12
1
BAT54CW_SOT323~D
2
12
PR43
39.2K_0402_1%~D
GNDA_3V5V
PAD-OPEN1x1m
5V_3V_REF
EN_3V_5V
1
5
3
4
2
6
VIN
VREF3
V5FILT
TONSEL
EN_LDO
24
GNDA_3V5V
12
PC37
+5V_ALW2
4.7U_0603_6.3V6K~D
1 2
PC23
4.7U_0805_6.3V6K
0_0402_5%~D@
1 2
0_0402_5%~D
1 2
0.1U_0603_25V7K~D
1 2
@
0_0603_5%~D
VREF2
REFIN2
TRIP2
VOUT2
SKIPSEL
PGOOD2
EN2
DRVH2
LL2
SN0608098_QFN32_5X5~D
+3.3V_ALW_BOOT
GNDA_3V5V
PR19
0_0805_5%
1 2
PC21
10U_1206_25V6M~D
12
PC22
GNDA_3V5V
PR40
1 2
200K_0402_5%
PAD-OPEN1x1m
10U_1206_25V6M~D
PC38
12
+5V_ALWP
12
0.1U_0603_25V7K~D
PJP10
+3.3V_ALW2
12
PC24
1U_0603_25V7K~D
+3.3V_RTC_LDO
GNDA_3V5V
PR28
150K_0402_1%~D
1 2
ALW_PWRGD_3V _5V
+5V_ALW_UGATE
12
PC30
0.1U_0603_25V7K~D
2
3
PD10
BAT54SW-7-F_S OT323-3~D
2
3
PD11
BAT54SW-7-F_S OT323-3~D
+15V_ALWP
12
12
PC19
0.1U_0805_50V7K
2
G
5
4
12
12
12
PC20
10U_1206_25V6M~D
12
PC29
@
0.1U_0402_10V7K~D
+15V_ALW
12
PC18
2200P_0402_50V7K~D
3
D
PQ8
S
1
PL5
12
PR335
@
2.2_0805_1%~D
ALWON<34>
THERM_STP#<19>
FDMS8692_POWER56-8~D
786
12
PC178
@
PQ10
1000P_0603_50V7K~D
123
FDS6676AS_NL_SO8~D
1 2
PR38
2K_0402_5%~D
PR41
0_0402_5%~D
(100mA,20mils ,Via NO.=1)
DELL CONFIDENTIAL/PROPRIETARY
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVIS ION OF R&D
4
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INF ORMATION IT CONT AINS
3
2
Size Document N u mb er R e v
Date: Sheet
Compal Electronics, Inc.
DC/DC +3V/ +5V
LA-4291P
1
41 49Friday, De ce mb er 07, 2007
0.1
of
Page 42
5
PR44
10_0402_1%~D
1 2
D D
AVDD2
12
12
PC44
PR45
0.22U_0402_10V7K~D
C C
PR49
10_0402_1%~D
1 2
AVDD1
BIAS1
B B
+1.05V_MP +1.05V_M
A A
+1.5V_SUS_P +1.5V_MEM
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
12
PC58
0.22U_0402_10V7K~D
PJP19
1 2
PAD-OPEN 4x4m
PJP20
1 2
PAD-OPEN 4x4m
PJP21
1 2
PAD-OPEN 4x4m
5
PR50
44.2K_0402_1%
PR51
1 2
3.74K_0402_1%~D
12
PC45
PR46
44.2K_0402_1%~D
12
PC59
2200P_0402_50V7K~D
2200P_0402_50V7K~D
3.09K_0402_1%~D
PU4
VT351FCX-ADJ_CSP25~D
PR52
56K_0402_1%
GNDA_1P5V
VSENSE1
EN1
4
PU3
VT351FCX-ADJ_CSP25~D
VSENSE2
PR47
39K_0402_1%~D
VT351_PWR1
E5
A1
BIAS
A2
R_SEL/ILOAD
A3
VDES
A4
VSENSE+
A5
OE
B1
AGND
PR53
24K_0402_1%~D
GNDA_1P5V
PJP18
12
PAD-OPEN1x1m
4
EN2
VDDE4VDD
IRIPL
B2
12
AVDD1
VT351_PWR2
A1
A2
A3
A4
A5
B1
GNDE3GNDE2GND
AVDD
B4
B3
POK1
E5
VDDE4VDD
BIAS
R_SEL/ILOAD
VDES
VSENSE+
OE
AGND
IRIPL
B2
12
PR48
31.6K_0402_1%~D
GNDA_1P05V
E1
D4
VXD5VX
STATB5TEMP
C1
GNDE3GNDE2GND
AVDD
B4
B3
AVDD2
D3
VX
D2
VX
D1
VX
C5
VDD
C4
VDD
C3
GND
GNDC2GND
EN_1.05VALW<37>
EN_1.5VALW<37>
3
2
1
+1.5V_SUS_P / +1.05V_M
PJP15
1 2
PAD-OPEN 4x4m
12
12
E1
D4
VXD5VX
D3
VX
D2
VX
D1
VX
C5
VDD
C4
VDD
C3
GND
STATB5TEMP
GNDC2GND
C1
POK2
PJP16
12
PAD-OPEN1x1m
GNDA_1P05V
PC54
PL8
PHASE1_L
@
PR58
0_0402_5%~D
1 2
PR60
0_0402_5%~D
1 2
0.2UH_ MPC0730LR20C_17.5A~D
12
PC181
@
1000P_0603_50V7K~D
PR338
1 2
2.2_0805_1%~D
EN2
EN1
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
3
22U_1206_6.3V6M~D
PC180
@
1000P_0603_50V7K~D
12
PC55
12
VSENSE1
@
PR355
1 2
100K_0402_1%~D
POK2
POK1
12
PR337
@
1 2
12
22U_1206_6.3V6M~D
PR323
0_0603_5%~D
1 2
PR324
0_0603_5%~D
1 2
+3.3V_ALW
PR356
100K_0402_1%~D
PC174
22U_1206_6.3V6M~D
0.2UH_ MPC0730LR20C_17.5A~D
PHASE2_L
2.2_0805_1%~D
12
PC56
0.1U_0603_25V7K~D
12
PC60
@
10U_0805_6.3V6K~D
PR59
1 2
0_0402_5%~D
1 2
PR57
0_0402_5%~D
1 2
PC42
PC41
22U_1206_6.3V6M~D
PL7
12
1 2
12
PC57
0.01U_0402_25V7K~D
12
PC61
22U_1206_6.3V6M~D
1.05V_M_PWRGD <34>
1.5V_SUS_PWRGD <10,34>
0.1U_0603_25V7K~D
PAD-OPEN 4x4m
PC62
12
PJP17
22U_1206_6.3V6M~D
12
PC43
0.01U_0402_25V7K~D
PR321
0_0603_5%~D
VSENSE2
PR322
@
0_0603_5%~D
+5V_ALWP
12
12
PC63
@
PC64
10U_0805_6.3V6K~D
2
+5V_ALWP
1.05 Volt +/-5%
Thermal Design Current: 4.94A
Peack current: 7.05A
OCP min:10A
12
1 2
1 2
12
PC46
@
22U_1206_6.3V6M~D
12
12
PC47
PC48
PC49
22U_1206_6.3V6M~D
22U_1206_6.3V6M~D
22U_1206_6.3V6M~D
1.5 Volt +/-5%
Thermal Design Current: 7.64A
Peak current: 10.92A
OCP min: 15A
22U_1206_6.3V6M~D
12
PC65
10U_1206_6.3V7K~D
12
12
PC66
10U_1206_6.3V7K~D
12
PC67
@
10U_0805_6.3V6K~D
DELL CONFIDENTIAL/PROPRIETARY
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
+1.5V_SUS_P / +1.05V_MP
LA-4291P
+1.05V_MP
12
12
PC50
10U_1206_6.3V7K~D
12
PC68
22U_1206_6.3V6M~D
PC51
10U_1206_6.3V7K~D
+1.5V_SUS_P
12
PC69
22U_1206_6.3V6M~D
1
PC52
0.1U_0603_25V7K~D
PC70
0.1U_0603_25V7K~D
42 49Friday, Decemb er 07, 2007
12
12
PC53
6800P_0402_25V7K~D
12
12
PC71
6800P_0402_25V7K~D
0.1
of
Page 43
8
H H
7
6
5
4
3
2
1
12
PR61
7.32K_0603_1%
@
12
IMVP_VR_ON<33>
0.1U_0402_10V7K~D
GNDA_CORE
PC85
27P_0402_50V8K
1 2
PR82
10K_0603_0.1%~D
DPRSLPVR<10,24>
PR64
0_0402_5%~D
@
12
PH1
@
GNDA_CORE
100K_0603_5%_TH11-4H104FT
H_DPRSTP#<8, 10,23>
PR79
0_0402_5%~D
PR80
10K_0402_5%~D
PC83
1 2
12
G G
Thermistor PH1 should be placed
close to the hot spot of the VR
F F
E E
D D
12
C C
B B
+3.3V_RUN
12
12
PR69
PR68
1.91K_0402_1%~D
IMVP_PWRGD<24,33,44>
12
1 2
1 2
1.91K_0402_1%~D
PWR_MON<19>
CLK_ENABLE#
PC82
1000P_0402_50V7K~D
1 2
GNDA_CORE
PC84
100P_0402_50V8K
12
PR81
1K_0402_1%
PR85
0_0402_5%~D
PR89
0_0402_5%~D
PR93
100_0402_5%~D@
PR94
100_0402_5%~D@
PC86
820P_0402_25V8K
12
1 2
1 2
12
PC87
0.015U_0402_16V7K
NOTE: ( Connection VCORE output Cap GND)
De-populate PR93 and PR94 when CPU is present
PC88
390P_0402_50V7K
GNDA_COREGNDA_CORE
VCCSense <8>
VSSSense <8>
+VCC_CORE
H_PSI#<8>
VID6<8>
VID5<8>
VID4<8>
VID3<8>
VID2<8>
VID1<8>
VID0<8>
12
499_0402_1%
1 2
12
PC80
0.01U_0402_25V7K~D
@
GNDA_CORE
PR70 0_0402_5%~D
1 2
PR71 0_0402_5%~D
1 2
PR77 0_0402_5%~D
PU6
1
EN
2
PWRGD
3
PMON
4
CLKEN
5
FBRTN
6
FB
7
COMP
8
SS
9
STSET
10
DPRSLP
PR84
GNDA_CORE
GNDA_CORE
+5V_RUN
PR63
PC81
GNDA_CORE
PR66
@
0_0402_5%~D
1 2
39
ADP3207AJCPZ-RL_LFC SP 40~D
ILIMIT11RRPM
VRPM
12
PR86
PR87
1 2
309K_0402_1%
12
PC89
1000P_0402_50V7K~D
GNDA_CORE
PC90
GNDA_CORE
12
10_0603_5%
12
1U_0805_25V4Z~D
12
12
12
PR720_0402_5%~D
PR730_0402_5%~D
RT14RAMPADJ15LLSET16CSREF17CSSUM18CSCOMP
13
1 2
1 2
ADP3207_RAMPADJ
PR88
160K_0402_1%~D
392K_0402_1%
1 2
PR91 280K_0402_1%
12
12
1000P_0402_50V7K~D
+PWR_SRC
12
12
PR740_0402_5%~D
PR750_0402_5%~D
VID634VID535VID436VID337VID238VID040VID1
ADP3207_CSREF
12
PR92 0_0402_5%~D
GNDA_CORE
12
@
33
ADP3207_CSSUM
PC91
PR760_0402_5%~D
DPRSTP
1000P_0402_50V7K~D
PR67
0_0402_5%~D
1 2
PR78
0_0402_5%~D
1 2
GNDA_CORE
32
31
PSI
VCC
TTSENSE
GND
20
19
GNDA_CORE
12
VRTT
PWM1
PWM2
PWM3
@
IMVP_VR_ON<33>
ADP3207_TTSENSE
30
ADP3207_VRTT
29
28
DCM
27
OD
26
25
24
23
SW1
22
SW2
21
SW3
71.5K_0402_1%~D
12
PC175
PC176
2200P_0402_50V7K~D
2200P_0402_50V7K~D
T110
ADP3207_#DCM
ADP3207_PWM1
PWM2, PWM3 pull high
12
PR90
165K_0402_1%~D
PR330
12
+5V_RUN
1 2
PR95
84.5K_0603_1%~D
12
PC73
PU5
4.7U_0805_10V6K
1
2
3
4
5
ADP3419JRMZ-REEL_MSOP10~D
Solution for Penryn SFF ULV: 1-phase
Icc MAX:19A
Icc dynamic:15.5A
Icc Inst time:(35us- up to 70us maximum)
Load line :4mOhm
IN
SD#
DRVLSD#
CROWBAR
VCC
PD13
RB751V-40_SOD323~D
12
BST
DRVH
GND
DRVL
SW
AD3419_BST1
PR62
1 2
0_0603_5%~D
10
AD3419_DRVH1
9
8
7
6
AD3419_DRVL1
12
PC75
0.33U_0603_10V7K
AD3419_SW1
3
D
2
G
S
1
3
D
2
G
S
1
PQ12
PQ13
12
PC76
1000P_0402_50V7K~D
SI7686DP-T1-E3_SO8~D
2
G
FDMS8670AS_POWER56-8~D
+CPU_PWR_SRC
12
12
PC77
0.1U_0805_25V7K~D
3
D
PQ14
S
1
12
PC78
PC79
10U_1206_25V6M~D
10U_1206_25V6M~D
12
PC182
@
1000P_0603_50V7K~D
FDMS8670AS_POWER56-8~D
1 2
PR339
2.2_0805_1%~D
@
PL9
@
FBMA-L11-321611-800LMA40T
ADP3207_SW1
12
PJP22
1 2
PAD-OPE N 4x4m
PL10
0.45UH_ET QP4LR45XFC_25A_20%~D
220K_0402_5%_ERTJ0EV224J~D
4
3
PH3
1 2
1
2
+PWR_SRC
1
1
+
+
PC170
PC171
2
2
@
@
68U_25V_M_R0.36
68U_25V_M_R0.36
+VCC_CORE
ADP3207_CSREF
PJP23
A A
GNDA_CORE
8
1 2
PAD-OPEN1x1m
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVIS ION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INF ORMATION IT CONT AINS
7
6
5
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WR ITT EN CO NSE NT OF COMPAL ELECTRONICS, INC.
4
3
DELL CONFIDENTIAL/PROPRIETARY
Title
Size Document N u mb er R e v
Date: Sheet
2
Compal Electronics, Inc.
+VCORE
LA-4291P
43 49Friday, De ce mb e r 07, 2007
1
of
0.1
Page 44
5
D D
VSS_AXG_SENSE<14>
C C
12
PR103
33.2K_0402_1%~D
PR105
100_0402_5%~D
1 2
VSS_AXG_SENSE
12
PC108
B B
VCC_AXG_SENSE<14>
1000P_0402_50V7K~D
GNDA_VGA
12
@
22P_0402_50V8J
1K_0402_1%~D
@
100_0402_1%~D
1 2
+VGFX_COREP
GNDA_VGA
PC98
PR107
PR109
PWR_MON_GFX<19>
PAD-OPEN1x1m
12
PJP25
22P_0402_50V8J
20K_0402_1%~D
1 2
1 2
PC101
470P_0402_50V7K
GNDA_VGA
12
PC99
12
PR108
GNDA_VGA
PR112 200K_0402_1%~D
12
PC110
2.2U_0603_6.3VAK~D
12
PC102
12
12
PC103
0.012U_0402_16V7K~D
12
PR115
3K_0402_1%
VGFX_CORE_FB
GFX_VR_ON<10>
GNDA_VGA
680P_0402_50V7K~D
4
GFX_VID4<10>
GFX_VID3<10>
GFX_VID2<10>
GFX_VID1<10>
GFX_VID0<10>
PR110
GNDA_VGA
3
PR96
0_0402_5%~D
1 2
PR97
0_0402_5%~D
1 2
PR98
0_0402_5%~D
1 2
PR99
0_0402_5%~D
1 2
PR100
0_0402_5%~D
1 2
1 2
PR101
0_0402_5%~D
+5V_ALW
+VGFX_SRC
PR102
10_0603_5%~D
GNDA_VGA
PR104
0_0603_5%~D
SW
1000P_0402_50V7K~D
PR117
76.8K_0402_1%~D
12
PC112
1200P_0402_50V7K~D
12
1 2
12
PC96
1U_0603_10V4Z~D
PD14
RB751V-40_SOD323~D
12
1 2
1 2
PC100
1U_0603_10V6K~D
12
PR123
1K_0402_1%~D
12
PC114
100P_0402_50V8J
12
PR118
169K_0402_1%~D
+VGFX_SRC
PC97
12
4.7U_0805_10V4Z
0_0402_5%~D
1 2
+VGFX_COREP
PR121
5
3
241
5
3
241
PQ16
FDMC8878_1N_POWER33-8~D
PQ17
FDMC8854_1N_POWER33-8~D
PR119
1 2
49.9K_0603_1%~D
IMVP_PWRGD<24,33,43>
32
30
31
PU7
1
FBRTN
2
FB
3
COMP
4
SS
5
ST
6
PMON
7
PMONFS
8
CLIM
PR111
1 2
1 2
187K_0402_1%
78.7K_0402_1%~D
PR116
0_0402_5%~D
@
1 2
PR120
0_0402_5%~D
1 2
EN
PWRGD
VARFREQ#
LLINE9CSCOMP10CSREF11CSFB12RAMP13VRPM14RPM15RT
12
PC113
1000P_0402_50V7K~D
GNDA_VGA GNDA_VGA
VID029VID128VID227VID326VID4
PR113
1 2
200K_0402_1%~D
12
@
2200P_0402_50V7K~D
25
24
VCC
23
BST
DRVH
22
DRVH
21
SW
20
PVCC
DRVL
19
DRVL
18
PGND
17
GND
33
AGND
ADP3209JCPZ-RL_LFCSP32_5X5~D
16
GNDA_VGA
12
12
PR114
PC109
357K_0603_1%~D
GNDA_VGAGNDA_VGA
PC111
PR122
340K_0402_1%
12
PC92
10U_1206_25V6M~D
@
12
PC107
1000P_0603_50V7K~D
PR106
2.2_0805_1%~D
1 2
PJP26
1 2
PAD-OPE N 4x4m
2
12
@
12
12
PC94
PC93
10U_1206_25V6M~D
2200P_0402_50V7K~D
PL11
0.42UH_MPC0740LR42C_20A_20%~D
1 2
PH2
220K_0402_5%_ERTJ0EV224J~D
VGFX_CORE_FB
+VCC_GFXCORE
PJP24
12
PC95
0.1U_0805_50V7K
12
1 2
PAD-OPEN 4x4m
+PWR_SRC
VGFX_CORE
Thermal Design Current: 6.09A
Peak current: 8.7A
OCP min: 11A
1
1
+
+
PC105
PC104
330U_D2_2VY_R7~D
VOUT=Vgfx_core(1.25V)
Load line:6.9mOhm
L=0.42uF
Fsw=436KHz
D=?
Output Ripple Current=?A
Output Ripple Voltage=?A*7.5mOhm=?mV
Input Ripple Current=TDC*(D*(1-D))^0.5=?A
Component select
Input CAP 10uF_1206_25V*2
Output Cap 330U 2V Y D2 LESR7M S H1.9*2
H_MOSFET SI4682DY
L_MOSFET SI4362DY(4.2/5.5mOhm@4.5V, 15A)
Inductor 0.42U_MPC0740LR42C_20A(NEC_TOKIN)
2
2
330U_D2_2VY_R7~D
12
PC106
0.1U_0402_16V7K
1
+VGFX_COREP
12
12
PC173
PC172
@
@
10U_0805_6.3V6M~D
10U_0805_6.3V6M~D
A A
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
DELL CONFIDENTIAL/PROPRIETARY
Title
Size Docu m e nt N u m be r Re v
Date: Sheet
Compal Electronics, Inc.
ADP3209_NB_core
LA-4291P
44 49Friday, D ec em be r 07, 2007
of
0.1
Page 45
5
4
3
2
1
+1.8VRUN/ +0.75V_DDR_VTT
DDR3 Termination
+5V_ALW
D D
+1.5V_SUS_P
0.75V_DDR_VTT_ON<33>
DDR_ON< 10,34,37>
+3.3V_ALWP
C C
5V_3V_REF
B B
PAD-OPE N 2x2m~D
RUN_ON<20,21,27,33,37>
PR125
10K_0402_1%
1 2
PJP27
2 1
PJP30
2 1
PAD-OPEN 2x2m ~D
PC118
10U_0805_6.3V6M~D
100K_0402_5%~D
1.8V_RUN_PWRGD
1U_0603_10V6K~D
91K_0402_1%~D
1 2
1 2
PC124
PR126
12
PC119
0.1U_0603_25V7K~D
PR124
12
PU8
10
VIN
2
VLDOIN
1
VDDQSNS
7
S3
9
S5
TPS51100DGQRG4_MSOP10~D
DC_1+1.8V_RUN_PWR_SRC
+3.3V_ALW
12
12
PC123
1U_0603_10V6K~D
+V_DDR_MCH_REF
3
VTT
5
VTTSNS
6
VTTREF
4
PGND
8
GND
11
BP
PC120
10U_0805_6.3V6M~D
12
PU9
10
IN
2
VCC
5
PGOOD
7
SHDN
4
REFIN
REFOUT
MAX8794ETB+T_TDFN10~D
+0.75V_P
0.75Volt +/-5%
Thermal Design Current: 0.7A
Peak current: 1A
12
PC115
PC116
1 2
PC117
0.1U_0603_25V7K~D
9
OUT
8
PGND
3
AGND
6
OUTS
1
11
BP
PGND and GND sholud be tied
together at one point near the GND Pin
1 2
10U_0805_6.3V6M~D
10U_0805_6.3V6M~D
1.8 Volt +/-5%
Design Current: 134mA
Peak current: 191mA
1 2
PC122
PC125
1 2
1U_0603_10V6K~D
GNDA_1P8V
10U_0805_6.3V6M~D
+0.75V_P
+1.8V_RUNP
12
PC121
10U_0805_6.3V6M~D
2 1
PAD-OPE N 2x2m~D
GNDA_1P8V
PJP28
+1.8V_RUNP
PJP33
PAD-OPEN1x1m
12
+0.75V_DDR_VTT
PJP32
2 1
PAD-OPE N 2x2m~D
+1.8V_RUN
+3.3V_ALW
A A
PJP36
12
PAD-OPEN1x1m
PU12
MAX8511EXK15+T_SC70-5~D
1
IN
3
#SHDN
1 2
PC187
1U_0603_10V6K~D
It's for layout first.
5
OUT
4
NC
GND
2
PJP37
PAD-OPEN1x1m
1 2
PC186
1U_0603_10V6K~D
+1.5V_ALW_HDA
12
1.5 Volt +/-5%
Design Current: ?mA
Peak current: ?mA
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
5
4
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
Title
Size Docu m e nt N u m be r Re v
Date: Sheet
Compal Electronics, Inc.
+1.8VRUNP/ +0.75V_DDR_VT
LA-4291P
1
45 49Friday, De ce mb er 07, 2007
of
0.1
Page 46
5
+DC_IN discharge path
+DC_IN_SS
PQ18
SI4835BDY-T1-E3_SO8~D
D D
C C
B B
A A
NB_AC_OFF <33,40,47>
5
0.01U_0402_25V7K~D
GNDA_CHG
Vin Detector
High 17.9 V
Low 17.24 V
3
PQ20B
4
2N7002DW-7-F_SOT363-6~D
+SDC_IN
PR140
49.9K_0402_1%~D
12
PC134
12
12
PR136
365K_0402_1%~D
CKG_SMBCLK<6,26,34>
CKG_SMBDAT<6,26,34>
MAX8731_IINP<19>
10K_0402_5%~D
61
PQ20A
2N7002DW-7-F_SOT363-6~D
2
PR333
200K_0402_1%~D
ACAV_IN<19,34>
5
PD23
B340A-13-F_SMA2~D
2 1
8
7
5
PR130
12
ACAV_DOCK_SRC<47>
12
MAX8731_LDO
MAX8731_REF
12
PR137
0_0402_5%~D
@
+3.3V_ALW
PC141
0.1U_0402_10V7K~D
GNDA_CHG
GNDA_CHG
ADAPT_TRIP_SEL<33>
4
100K_0402_5%~D
12
PR138
10K_0402_1%~D
12
PR143
15.8K_0402_1%~D
12
PR152
1
2
36
PR131
12
12
PC153
8.45K_0402_1%~D
0.1U_0402_10V7K~D
PJP35
1 2
PAD-OPEN1x1m
MAX8731_IINP
5
1 2
200K_0402_1%~D
12
PR147
10K_0402_5%~D
130p_0402_10V
12
12
PC152
0.01U_0402_25V7K~D
PR157
1 2
0_0402_5%~D
PR159
@
33.2K_0402_1%~D
1 2
GNDA_CHG GNDA_CHG
3
4
@
@
1 2
MAX8731_REF
PC161
4
+DC_IN
12
PR129
10K_0402_5%~D
PQ22B
2N7002DW-7-F_SOT363-6~D
12
12
PC130
PR135
@
33K_0402_5%~D
1U_0805_25V4Z~D
PR142
1 2
0_0402_5%~D
GNDA_CHG
PR145
PC146
12
0.01U_0402_25V7K~D
PC145
@
51P_0402_10V
12
PC155
PC154
0.01U_0402_25V7K~D
0.01U_0402_25V7K~D
12
PR156
57.6K_0402_1%~D
12
PR161
13K_0402_1%~D
PC162
12
0.01U_0402_25V7K~D
GNDA_CHG GNDA_CHG GNDA_CHG GNDA_CHG
PR162
105_0402_1%~D
4
3
+SDC_IN
12
12
PR132
10K_0402_5%~D
61
2
0.1U_0603_25V7K~D
PC133
12
MAX8731_IINP
PC143
@
1 2
2000P_0402_10V
12
0_0402_5%~D
12
12
PC156
1U_0603_10V6K~D
Adapter Trip current PR156 PR161 PR162 PR159
?W ?A ? ? ? N/A
12
12
PC163
100P_0402_50V8J~D
@
12
PR128
PQ22A
2N7002DW-7-F_SOT363-6~D
@
1 2
PC126
33K_0402_5%~D
NTGD4161PT1G_TSOP6~D
@
1 2
7.5K_0402_1%~D
PR149
GNDA_CHG
PC164
0.1U_0402_10V7K~D
GNDA_CHG
PR146
MAX8731_REF
PC157
0.1U_0402_10V7K~D
2
3
12
100P_0402_50V8J~D
0.1U_0603_25V7K~D
PQ19A
PC131
@
1 2
22
2
13
11
10
9
14
8
6
5
4
3
7
12
12
29
PR154
1M_0402_1%~D
1 2
GNDA_CHG
4
G
ININ+
P
8
+5V_ALW
PR127
0.01_1206_1%~D
1
2
65
D
1
G
S
PR133
10K_0402_5%~D
PC129
@
1 2
0.22U_0402_6.3V6K
1
28
PU10
DCIN
GND
CSSP
ACIN
ACOK
VDD
SCL
SDA
BATSEL
IINP
CCV
CCI
CCS
REF
DAC
GND
GND
MAX8731AETI+_TQFN28~D
Maximum charging current:1.8A
PU11A
LM393DR_SO8~D
1
O
12
PC165
PC166
0.01U_0402_25V7K~D
100P_0402_50V8J~D
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
+PWR_SRC
4
3
42
D
PQ19B
3
NTGD4161PT1G_TSOP6~D
G
S
NTGD4161PT1G_TSOP6~D
12
27
VCC
CSSN
BST
LDO
DHI
LX
DLO
PGND
CSIP
CSIN
FBSA
FBSB
12
GNDA_CHG GNDA_CHG GNDA_CHG
12
12
PR341
PR134
100K_0402_1%~D
0_0402_5%~D
26
PR141
0_0603_5%~D
25
1 2
MAX8731_LDO
21
24
PR144
23
1_0603_1%~D
1
PC142
220P_0402_50V7K~D
2
20
19
18
17
15
16
+5V_ALW +3.3V_ALW
12
PR158
100K_0402_1%~D
2
PQ28
RHU002N06_SOT323-3~D
12
PC160
@
10P_0402_50V8J~D
3
1 2
PAD-OPEN 4x4m
PQ21B
S
D
G
3
PR342
100K_0402_1%~D
1U_0603_10V6K~D
12
PD15
PC135
0.1U_0603_25V7K~D
12
1 2
PR151
100_0402_5%~D
12
PR155
100K_0402_5%~D
13
D
G
S
PJP34
42
PQ21A
NTGD4161PT1G_TSOP6~D
S
D
G
1
100K_0402_1%~D
1 2
PC132
1 2
PR139
33_0603_1%~D
1 2
PC136
1U_0603_10V6K~D
1 2
CHG_UGATE
CHG_LX
CHG_LGATE
+VCHGR
12
PR160
@
65
PR343
1K_0402_5%~D
12
RB751V_SOD323~D
2 1
DOCK_DCIN_IS+ <31>
DOCK_DCIN_IS- <31>
SW_GND <47>
GNDA_CHG
12
PC144
@
3300PF_0402_50V7K~D
PQ26
SI7230DN-T1-E3_POWERPAK1212-8
ADAPT_OC <33>
PC184
0.1U_0402_25V~D
GNDA_CHG
12
2
12
PC127
@
2200P_0402_50V7K~D
5
PQ24
3
241
SI7326DN-T1-E3_POWERPAK 1212-8
5.8UH +-30% SIL104R-5R8 5.5A~D
5
3
241
PR340
@
2.2_0805_1%~D
MAX8731_REF
+DC_IN
12
PR345
PR346
47K_0402_1%~D
232K_0402_1%~D
12
PR349
PR350
21.5K_0402_1%~D
GNDA_CHG
27.4K_0402_1%~D
GNDA_CHG GNDA_CHG
2
CHAGER_SRC
12
PC128
0.1U_0603_25V7K~D
PL12
1 2
12
PC183
@
1000P_0603_50V7K~D
1 2
12
12
PC185
100P_0402_50V8J~D
12
1
1
1
12
2
2
PC140
PC139
0.1U_0603_25V7K~D
4
3
+3.3V_ALW
PR347
10U_1206_25V6M~D
PC148
12
100K_0402_1%~D
1
2
47P_0603_50V8J~D
1 2
0_0402_5%~D
PC149
PR348
10U_1206_25V6M~D
10U_1206_25V6M~D
1
2
PC150
+VCHGR
1
2
10U_1206_25V6M~D
PC151
1
2
ACAV_IN<19,34>
10U_1206_25V6M~D
ACAV_IN_NB <33,34>
PC137
2200P_0402_50V7K~D
+VCHGR_L
12
0_0402_5%~D
PR153
12
PC159
@
GNDA_CHG
0.1U_0402_10V7K~D
PR344
1M_0402_1%~D
1 2
+5V_ALW
8
5
P
IN+
6
IN-
G
4
GNDA_CHG
12
PC138
PR148
0.01_1206_1%~D
1
2
PC158
@
0.22U_0402_6.3V6K~D
1 2
7
O
PU11B
LM393DR_SO8~D
DELL CONFIDENTIAL/PROPRIETARY
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
Charger
46 49Friday, Decemb er 07, 2007
1
PR150
1 2
1.8K_1206_5%~D
13
D
2
G
S
PQ27
0.1
of
RHU002N06_SOT323-3~D
Page 47
5
+DOCK_PWR_BAR
D D
+3.3V_ALW2
12
PR169
ACAV_DOCK_SRC#<31,34>
C C
FDS6679AZ_SO8~D
PQ25
8
+VCHGR
B B
PBATT_OFF<33>
A A
7
5
+3.3V_ALW
12
PR353
100K_0402_5%~D
2
3
PQ23B
5
2N7002DW-7-F_SOT363-6~D
4
1
2
36
4
12
PR352
47K_0402_1%~D
61
PQ23A
2N7002DW-7-F_SOT363-6~D
PBATT+
12
PR351
240K_0402_5%~D
PQ33A
2N7002DW-7-F_SOT363-6~D
100K_0402_5%~D
+3.3V_ALW2
12
3
PQ33B
5
2N7002DW-7-F_SOT363-6~D
4
PBATT_OFF<33>
2
PR173
100K_0402_5%~D
4
12
12
61
ACAV_DOCK_SRC <46>
PQ3B
IMD2AT-108_SC74-6~D
2
16
5
PQ3A
IMD2AT-108_SC74-6~D
+3.3V_ALW +3.3V_ALW
12
PR165
100K_0402_5%~D
PR171
22K_0402_5%~D
5
PR174
4 3
PR166
100K_0402_5%~D
61
PQ32A
2N7002DW-7-F_SOT363-6~D
2
SW_GND <46>
3
PQ32B
2N7002DW-7-F_SOT363-6~D
4
FDS6679AZ_SO8~D
1
2
3 6
240K_0402_5%~D
1 2
PQ35
4
PR176
47K_0402_5%~D
1 2
SLICE_BAT_PRES#<31,33,40>
8
7
5
2
+DC_IN_SS
3
12
PR167
100K_0402_5%~D
61
PQ30A
2N7002DW-7-F_SOT363-6~D
+5V_ALW
12
PR172
22K_0402_5%~D
3
PQ30B
5
2N7002DW-7-F_SOT363-6~D
4
PBATT_PSRC
PD19
RB751V_SOD323~D
2 1
+3.3V_ALW2
12
PR329
100K_0402_5%~D
3
PQ40B
5
2N7002DW-7-F_SOT363-6~D
4
NB_AC_OFF <33,40,46>
NB_AC_OFF_BJT <40>
NTGD4161PT1G_TSOP6~D
S
PR325
1 2
240K_0402_5%~D
2
PQ38B
D
42
G
3
+DOCK_PWR_BAR
PR327
1 2
61
47K_0402_5%~D
PQ40A
2N7002DW-7-F_SOT363-6~D
PD16
B540C~D
2 1
FDS6679AZ_SO8~D
PQ29
8
7
5
4
12
+NBDOCK_DC_IN_SS
2
1
2
36
12
12
PC167
0.47U_0805_25V7K~D
47K_0402_1%~D
IMD2AT-108_SC74-6~D
+DC_IN_SS
NTGD4161PT1G_TSOP6~D
PR326
1 2
240K_0402_5%~D
2
G
PR168
IMD2AT-108_SC74-6~D
PR163
240K_0402_5%~D
4 3
PQ2A
PQ38A
S
G
1
PR328
1 2
13
D
PQ42
RHU002N06_SOT323
S
D
47K_0402_5%~D
PQ2B
65
2
16
PD18
2
3
RB715F_SOT323
PD20
2 1
RB751V_SOD323~D
12
PR164
5
RHU002N06_SOT323
13
D
G
S
1 2
22K_0402_5%~D
1
22K_0402_5%~D
PQ31
2
PR170
B540C~D
2 1
FDS6679AZ_SO8~D
8
7
5
PR175
EN_DOCK_PWR_BAR <33>
PD17
PQ36
4
1 2
33K_0402_5%~D
1
1
2
36
12
PC168
2200P_0402_50V7K~D
+PWR_SRC
12
PC169
0.1U_0603_25V7K~D
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
Selector
LA-4291P
47 49Friday, Decemb er 07, 2007
1
0.1
of
Page 48
5
4
Version Change List ( P. I. R. List )
3
2
1
Item Issue DescriptionDate
D D
C C
30 R5C833 xx/xx/2007 Dell
Owner
Solution Description Rev.Page#1Title
Request
B B
A A
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
EE-Change History 1
LA-4291P
48 49Friday, Decemb er 07, 2007
1
0.1
of
Page 49
5
4
Version Change List (Power P. I. R. List )
3
2
1
Item Issue DescriptionDate
D D
C C
Owner
Solution Description Rev.Page#1Title
Request
B B
A A
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
Power-Change History 1
LA-4291P
49 49Friday, Decemb er 07, 2007
1
0.1
of
Loading...