COMPAL LA-4251P Schematics

A

ZZZ1

PCB

DA80000B000

1 1

B

C

D

E

Compal Confidential

2 2

Monday, April 28, 2008

Amazon

Schematics Document

Menlow-Silverthorne with Poulsbo

3 3

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFE RED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFE RED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFE RED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4 4

2006/08/04 2006/10/06

Compal Secret Data

Deciphered Date

REV:0.2

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

Cover Sheet

Amazon(Menlow)

1 43

of

0.2

A

B

C

D

E

A

1 1

B

C

D

E

CPU-Silverthrone

PAGE 04

H_A#(3..35)

H_D#(0..63)

LVDS

2 2

Connector

LED Driver

LVDS I/F

SCH- Poulsbo

FSB

400MHz

SingleChannel

AZALIA

SD card

WIFI-AD1111

(Port 4)

SDIO

USB2.0

PAGE 07

LPC BUS

USB2.0

ATA100

3G Minicard

3 3

Touch Screen

MC9S08QG4CFFE

PS2

EC

ENE KB926

SPI

page33

BIOS

I2C

Int.KBD

G-Sensor

MMA7450L

T-9

Joy Stick

ADBM-2100

INT KB/CMOS

4 4

PAGE 33

RTCRST#/ PWR BTN VOL_UP & DOWN/LID Shutter BTN

PAGE 33

A

B

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

C

Clock Gen.

9UMS9633

PAGE 15

DDR2 64MX16X4pcsDDR2 -400/533

K4T1G164QD

PAGE 13

AMP&Audio Jack

Audio Codec

ALC 262

PAGE 26

(Port 7)

Camera 2M

(Port 3)

Camera 0.3M(Web)

(Port 5)

BlueTooth

LBMA46LCS1

(Port 1)

GPS

NEO-4S-0-000-2

(Port 2)

USB Client X1

(Port 0)

USB Standard X1

SSD

Compal Secret Data

2006/08/04 2006/10/06

Compal Secret Data

Deciphered Date

D

3G Minicard

PCM

+1.8/+1.5/+1.05/+0.9

MAX17017

PAGE 40

+CPU_CORE

MAX8796GTJ+

PAGE 41

Compal Electronics, Inc.

Title

Size Document Number Rev

C

Amazon

Date: Sheet

DCIN/CHARGER

BQ24100

BATT Conn/OTP

+3VALW

LTC3442EDE

+5VALW

TPS61030RSAR

Block Diagram

2 43Monday, April 28, 2008

E

2 43Monday, April 28, 2008

0.2

of

Voltage Rails

power plane

State

O MEANS ON X MEANS OFF

+VBAT

+5VALW

+3VALW

+1.8V

+0.9V

+5VS

+3VS

+1.8VS

+1.5VS

+CPU_CORE

+VCCP

CLOCK

A

SKU ID Table

Vcc 3.3V +/- 5%

Board ID

0

*

1 2 3 4 5 6 7

100K +/- 5%Ra

Rb V min

0

8.2K +/- 5% 18K +/- 5% 33K +/- 5% 56K +/- 5% 100K +/- 5% 200K +/- 5%

NC

AD_BID

0 V

V typ

AD_BID

0 V 0 V

V

AD_BID

max

0.216 V 0.250 V 0.289 V

0.436 V

0.712 V

1.036 V

0.503 V

0.819 V

0.538 V

0.875 V

1.185 V 1.264 V

1.453 V 1.650 V 1.759 V

1.935 V

2.500 V

2.200 V

3.300 V

2.341 V

3.300 V

S0

S3

S5 S4/AC

S5 S4/ Battery only

S5 S4/AC & Battery don't exist

O MEANS ON

X MEANS OFF

O

X

S3 : STR S4 : STD

O

X

O

X X

X

X X X

OO

X

O

X

SKU ID

*

0 1 2 3 4 5 6 7

H L

MB ID(H)

IEL10 IDL11 IDL01 HDL10

MB ID

JAX10 JAX60

MB ID(L)

HDL00 HDL20 HDL30IDL12

TBD

S5 : SOFT OFF

1 1

BOM Structure USB PORT LIST

MARK FUNCTION

NC FOR ALL@

PORT DEVICE

0

SPR

1

Client SPR

2

CMOS3 4 5 6 7

3G, GPS

BT

EC SM Bus1 address

Device

EEPROM(24C16/02)

Address

1010 000X b

EC SM Bus2 address

Device

ADM1032

Address

1001 100X b

Address

Poulsbo SM Bus address

Device

Clock Generator ( ICS954226)

Address

1101 001Xb

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFE RED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFE RED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFE RED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

2006/08/04 2006/10/06

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

Notes List

Amazon(Menlow)

of

3 43Monday, April 28, 2008

of

3 43Monday, April 28, 2008

of

3 43Monday, April 28, 2008

0.2

5

D D

H_A#[3..16](7)

H_ADSTB#0(7)

H_REQ#0(7) H_REQ#1(7) H_REQ#2(7) H_REQ#3(7) H_REQ#4(7)

H_A#[17..31](7)

C C

H_ADSTB#1(7)

H_A20M#(30)

H_PBE#(7)

H_STPCLK#(7) H_INTR(7)

H_NMI(7) H_SMI#(7)

+1.05VS_C6

B B

+1.05VS_C6

R562

1 2

R563

1 2

R564

1 2

H_ADSTB#0

H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4

R1092

1 2

10K_0201_5%

120_0402_5%

H_PBE#

1K_0402_5%

H_A20M#

H_IGNNE#

1K_0402_5%

H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16

H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 H_ADSTB#1

H_A20M# H_PBE# H_IGNNE#

H_STPCLK# H_INTR H_NMI H_SMI#

U57A

E22

A[3]#

AE16 AF17 AD15 AD17

A22 D21 E24 B17 A18 B23 A16 E18 D15 B19 A20 D17 B15 D19

B25 D23 E20 A24 B21

B5

A12

D5

E12

B9

A6 B13 E14 A10

B7 D13

A8

C4 A14 B11 D11

G30

J28

H27

K1 H31 L28

J26

D9

D7

E8 E10 L30

J30

K29

0

A[4]# A[5]# A[6]# A[7]# A[8]# A[9]# A[10]# A[11]# A[12]# A[13]# A[14]# A[15]# A[16]# ADSTB[0]#

REQ[0]# REQ[1]# REQ[2]# REQ[3]# REQ[4]#

A[17]# A[18]#

ADDR GROUP 1

A[19]# A[20]# A[21]# A[22]# A[23]# A[24]# A[25]# A[26]# A[27]# A[28]# A[29]# A[30]# A[31]# ADSTB[1]#

A20M# FERR# IGNNE#

STPCLK# LINT0 LINT1 SMI#

RSVD7 RSVD8 RSVD9 RSVD10 RSVD0 RSVD1 RSVD2 RSVD3 RSVD4 RSVD5

RSVD13

SILVERTHORNE_FCBGA8-441

800MHz@

ADDR GROUP

CONTROL

XDP/ITP SIGNALSH CLK

PROCHOT#

THERM

THERMTRIP#

NC

ADS# BNR#

BPRI#

DEFER#

DRDY# DBSY#

BR0#

IERR#

INIT#

LOCK#

RESET#

RS[0]# RS[1]# RS[2]#

TRDY#

HIT#

HITM#

BPM[0]# BPM[1]# BPM[2]# BPM[3]#

PRDY# PREQ#

TCK

TDO TMS

TRST#

RSVD14

THRMDA

THRMDC

BCLK[0] BCLK[1]

VSS0

RSVD11

RSVD6

RSVD15

TEST4

TEST3

CMREF[1]

TDI

C26 H25 G24

B27 W28 D29

C28

H1 F31

D25

M5 D27 E28 E26 F25

E30 F29

F1 E2 F5 D3 E4 F7 L2 N2 M1 P1 J4 G26

H5 T5 U4

T1

P29 R28

K31

A26 E6

G28 U30

V27 AE26

4

H_ADS# H_BNR# H_BPRI#

H_DEFER# H_DRDY# H_DBSY#

H_BR0#

H_IERR# H_INIT#

H_LOCK#

H_RESET# H_RS#0 H_RS#1 H_RS#2 H_TRDY#

H_HIT# H_HITM#

XDP_BPM#0 XDP_BPM#1 XDP_BPM#2 XDP_BPM#3 XDP_BPM#4 XDP_BPM#5 XDP_TCK XDP_TDI XDP_TDO XDP_TMS XDP_TRST#

C624

0.1U_0402_25V4K

U57

1300MHz@

SA00002BA00

H_ADS# (7) H_BNR# (7)

H_BPRI# (7)

H_DEFER# (7) H_DRDY# (7) H_DBSY# (7)

H_BR0# (7)

H_INIT# (7,30)

H_LOCK# (7)

H_RESET# (7)

H_RS#0 (7)

H_RS#1 (7)

H_RS#2 (7)

H_TRDY# (7)

H_HIT# (7) H_HITM# (7)

R884 0_0201_5%R884 0_0201_5%

1 2

R885 0_0201_5%R885 0_0201_5%

1 2

R886 0_0201_5%R886 0_0201_5%

1 2

R887 0_0201_5%R887 0_0201_5%

1 2

R10 0_0201_5%R10 0_0201_5%

1 2

T19 PADT19 PAD

H_PROCHOT#

H_THERMDA H_THERMDC

H_THERMTRIP#

CLK_CPU_BCLK CLK_CPU_BCLK#

+CMREF

1

2

+1.05VS_C6

12

R560

56_0402_5%

R561

R561 1K_0402_1%

1K_0402_1%

3

+1.05VS_C6

R14

H_INIT#

R14

1 2

1K_0402_5%

Intel WW25 change to mount

R8

12

+1.05VS

H_PROCHOT# (41)

12

R13 56_0402_5%

H_THERMTRIP# (7)

CLK_CPU_BCLK (15) CLK_CPU_BCLK# (15)

H_THERMDA, H_THERMDC routing together, Trace width / Spacing = 10 / 10 mil

+1.05VS

H_PWRGOOD(5,7)

H_RESET#

XDP Reserve

EC_SMB_CK2(30,31)

EC_SMB_DA2(30,31)

R566

1 2

1K_0402_1%

1 2

R585 1K_0402_1%R585 1K_0402_1%

XDP_BPM#5

C2 2200P_0201_16V7KC2 2200P_0201_16V7K

1 2

2

+1.05VS

R5 56_0402_5%R5 56_0402_5%

1 2

U2

H_THERMDA

H_THERMDC

EC_SMB_DA2

U2

2

D+

3

D-

8

SCLK

7

SDATA

S IC G780P81U MSOP 8P

Address:100_1100

SA00002BO00

XDP_TDI

XDP_TMS

XDP_TDO

XDP_TRST#

XDP_TCK

C1

1 2

0.1U_0402_16V4Z

1

VDD1

6

ALERT#

4

THERM#

5

GND

R2 56_0402_5%R2 56_0402_5%

R3 56_0402_5%R3 56_0402_5%

R4 56_0402_5%

R6 56_0402_5%R6 56_0402_5%

R7 56_0402_5%R7 56_0402_5%

+3VS

THERM_SCI#

THERM#EC_SMB_CK2

1 2

R11 0_0402_5%@R11 0_0402_5%@

1

1 2

@

1 2

R9

R9 10K_0402_5%

10K_0402_5%

12

R1210K_0402_5% R1210K_0402_5%

+1.05VS

EC_THERM# (10,30)

+3VS

Check : to sb

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFE RED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFE RED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFE RED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/08/04 2006/10/06

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

Silverthorne(1/3)-AGTL+/XDP

JAX60

1

0.2

4 43Monday, April 28, 2008

0.2

of

5

4

3

2

1

H_D#[0..15](7)

D D

H_DSTBN#0(7) H_DSTBP#0(7)

H_DINV#0(7)

H_D#[16..31](7)

H_DSTBN#1(7)

C C

H_DSTBP#1(7)

H_DINV#1(7)

CPU_BSEL2(7,15)

H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 H_DSTBN#0 H_DSTBP#0 H_DINV#0

H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31 H_DSTBN#1 H_DSTBP#1 H_DINV#1

+CPU_GTLREF

CPU_BSEL2

U57B

Y27

D[0]#

AH27

D[1]#

Y31

D[2]#

AC30

D[3]#

AE30

D[4]#

AF29

D[5]#

AA26

D[6]#

AB31

D[7]#

W30

D[8]#

AC28

D[9]#

AD31

D[10]#

AF27

D[11]#

AD27

D[12]#

AG28

D[13]#

AB25

D[14]#

AC26

D[15]#

AA28

DSTBN[0]#

AA30

DSTBP[0]#

AE28

DINV[0]#

AE24

D[16]#

AC24

D[17]#

AJ20

D[18]#

AE20

D[19]#

AJ22

D[20]#

AF25

D[21]#

AH25

D[22]#

AH23

D[23]#

AH19

D[24]#

AF23

D[25]#

AE18

D[26]#

AH17

D[27]#

AD19

D[28]#

AJ24

D[29]#

AJ18

D[30]#

AF19

D[31]#

AF21

DSTBN[1]#

AH21

DSTBP[1]#

AE22

DINV[1]#

AJ26

GTLREF

MISC

P31

TEST1

T31

TEST2

R30

BSEL[0]

M31

BSEL[1]

U28

BSEL[2]

SILVERTHORNE_FCBGA8-441

800MHz@

DATA GRP 0 DATA GRP 1

D[32]# D[33]# D[34]# D[35]# D[36]# D[37]# D[38]# D[39]# D[40]# D[41]# D[42]# D[43]#

DATA GRP 2

D[44]# D[45]# D[46]#

D[47]# DSTBN[2]# DSTBP[2]#

DINV[2]#

D[48]#

D[49]#

D[50]#

D[51]#

D[52]#

D[53]#

D[54]#

D[55]#

D[56]#

D[57]#

D[58]#

D[59]#

D[60]#

DATA GRP 3

D[61]#

D[62]#

D[63]# DSTBN[3]# DSTBP[3]#

DINV[3]#

COMP[0] COMP[1] COMP[2] COMP[3]

DPRSTP#

DPSLP#

DPWR#

PWRGOOD

SLP#

RSVD12

AE8 AD7 AH15 AF9 AH9 AE10 AJ16 AF13 AF7 AF15 AH13 AJ14 AJ12 AH7 AJ8 AJ10 AH11 AF11 AE12

AH5 AB5 AJ6 Y1 AF5 AG4 AF3 AC6 AE6 AE4 W4 AC2 AE2 AD1 AA2 AC4 AB1 AA4 Y5

AE14 AD13 E16 F15

G2 G6 V31 G4 J2 K27

H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 H_DSTBN#2 H_DSTBP#2 H_DINV#2

H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63 H_DSTBN#3 H_DSTBP#3 H_DINV#3

COMP0 COMP1 COMP2 COMP3

H_DPRSTP# H_DPSLP# H_DPWR# H_PWRGOOD H_CPUSLP#

layout note: Route TEST3 & TEST5 traces on ground referenced layer to the TPs

CPU_BSEL CPU_BSEL2 CPU_BSEL1

100

133

B B

1 0

0

CPU_BSEL0

1

H_D#[32..47] (7)

H_DSTBN#2 (7) H_DSTBP#2 (7) H_DINV#2 (7) H_D#[48..63] (7)

H_DSTBN#3 (7) H_DSTBP#3 (7) H_DINV#3 (7)

H_DPRSTP# (7,41)

H_DPSLP# (7) H_DPWR# (7) H_PWRGOOD (4,7)

H_CPUSLP# (7)

12

R19

54.9_0402_1%

Resistor p laced with in

0.5" of CP U pin.Trac e should be at least 2 5 mils away from any o ther toggling s ignal. COMP[0,2] trace widt h is 18 mils. C OMP[1,3] t race width is 4 mils.

12

R22

R21

R20

27.4_0402_1%

54.9_0402_1%

27.4_0402_1%

+1.05VS_C6

12

R565

R565 1K_0402_1%

1K_0402_1%

+CPU_GTLREF

1

C817

0.1U_0402_25V4K

12

R25

2

2K_0402_1%

Close to CPU pin AD26 within 500mils.

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFE RED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFE RED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFE RED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/08/04 2006/10/06

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

Silverthorne(2/3)-AGTL+DATA

JAX60

1

0.2

5 43Monday, April 28, 2008

0.2

of

5

4

3

2

1

+1.05VS

1

C822

2

1

C794

2

1U_0402_6.3V4Z

+1.05VS_C6

U57C

AA14

VCCP35

J16

VCCP36

M27

VCCP0

H7

VCCPC61

H9

VCCPC62

J8

1

C801

2

0.1U_0402_16V7K

+1.05VS_C6

1

C795

2

0.1U_0402_16V7K

VCCPC63

AA8

VCCP1

AA10

VCCP2

AA12

VCCP3

AA16

VCCP4

AA18

VCCP5

AA20

VCCP6

AA22

VCCP7

AB7

VCCP8

AB9

VCCP9

AB11

VCCP10

AB13

VCCP11

AB15

VCCP12

AB17

VCCP13

AB19

VCCP14

AB21

VCCP15

AB23

VCCP16

H11

VCCP17

H13

VCCP18

H15

VCCP19

H17

VCCP20

H19

VCCP21

H21

VCCP22

H23

VCCP23

J10

VCCP24

J12

VCCP25

J14

VCCP26

J18

VCCP27

J20

VCCP28

J22

VCCP29

L26

VCCP30

N26

VCCP31

R26

VCCP32

U26

VCCP33

W26

VCCP34

SILVERTHORNE_FCBGA8-441

800MHz@

VCC1 VCC2 VCC3 VCC4 VCC5 VCC6 VCC7 VCC8

VCC9 VCC10 VCC11 VCC12 VCC13 VCC14 VCC15 VCC16 VCC17 VCC18 VCC19 VCC20 VCC21 VCC22 VCC23 VCC24 VCC25 VCC26 VCC27 VCC28 VCC29 VCC30 VCC31 VCC32 VCC33 VCC34 VCC35 VCC36 VCC37 VCC38 VCC39 VCC40 VCC41 VCC42 VCC43 VCC44 VCC45 VCC46 VCC47 VCC48

VCCA

VID[0]

VID[1]

VID[2]

VID[3]

VID[4]

VID[5]

VID[6]

VCCSENSE

VSSSENSE

D D

U57D

A4

VSS1

A28

VSS2

AA6

VSS4

AA24

VSS5

AB3

VSS6

AB27

VSS7

AB29

VSS8

AC8

VSS9

AC10

VSS10

AC12

VSS11

AC14

VSS12

AC16

VSS13

AC18

VSS14

AC20

VSS15

AC22

VSS16

AD3

VSS17

AD5

VSS18

AD9

VSS19

AD11

VSS20

AD21

VSS21

AD23

VSS22

AD25

VSS23

AD29

VSS24

AF1

VSS25

AF31

VSS26

AG2

VSS27

AG6

VSS28

AG8

VSS29

AG10

C C

B B

AG12 AG14 AG16 AG18 AG20 AG22 AG24 AG26 AG30

AH29

AJ28

AH3

C10 C12 C14 C16 C18 C20 C22 C24 C30

D31

G10 G12 G14 G16 G18 G20 G22

H29

VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS41 VSS42

AJ4

VSS45 VSS46

B3

VSS48

B29

VSS49

C2

VSS51

C6

VSS52

C8

VSS53 VSS54 VSS55 VSS56 VSS57 VSS58 VSS59 VSS60 VSS61 VSS62

D1

VSS63 VSS64

F3

VSS65

F9

VSS66

F11

VSS67

F13

VSS68

F17

VSS69

F19

VSS70

F21

VSS71

F23

VSS72

F27

VSS73

G8

VSS74 VSS75 VSS76 VSS77 VSS78 VSS79 VSS80 VSS81

H3

VSS82 VSS83

J6

VSS84

VSS162 VSS161 VSS160 VSS159 VSS158 VSS157 VSS156 VSS155 VSS154 VSS153 VSS152 VSS151 VSS149 VSS148 VSS147 VSS146 VSS145 VSS144 VSS143 VSS142 VSS141 VSS140 VSS139 VSS138 VSS137 VSS136 VSS135 VSS134 VSS133 VSS132 VSS131 VSS130 VSS129 VSS128 VSS127 VSS126 VSS125 VSS124 VSS123 VSS122 VSS121 VSS120 VSS119 VSS118 VSS117 VSS116 VSS115 VSS114 VSS113 VSS112 VSS111 VSS110 VSS109 VSS108 VSS107 VSS106 VSS105 VSS104 VSS103 VSS102 VSS101 VSS100

VSS99 VSS98 VSS97 VSS96 VSS95 VSS94 VSS93 VSS92 VSS91 VSS90 VSS89 VSS88 VSS87 VSS86 VSS85

Y29 Y25 Y23 Y21 Y19 Y17 Y15 Y13 Y11 Y9 Y7 Y3 W6 V29 V25 V23 V21 V19 V17 V15 V13 V11 V9 V7 V5 V3 T29 T27 T25 T23 T21 T19 T17 T15 T13 T11 T9 T7 T3 P27 P25 P23 P21 P19 P17 P15 P13 P11 P9 P7 P3 N28 M29 M25 M23 M21 M19 M17 M15 M13 M11 M9 M7 M3 L6 K25 K23 K21 K19 K17 K15 K13 K11 K9 K7 K3 J24

1

C823

2

1

C792

C793

2

1U_0402_6.3V4Z

L8 L10 L12 L14 L16 L18 L20 L22 L24 N6 N8 N10 N12 N14 N16 N18 N20 N22 N24 R6 R8 R10 R12 R14 R16 R18 R20 R22 R24 U6 U8 U10 U12 U14 U16 U18 U20 U22 U24 W8 W10 W12 W14 W16 W18 W20 W22 W24

N30

P5 R4 N4 K5 L4 R2 U2

W2

V1

+CPU_CORE

VCCSENSE

VSSSENSE

CPU_VID0 CPU_VID1 CPU_VID2 CPU_VID3 CPU_VID4 CPU_VID5 CPU_VID6

1

C781

C780

2

2.2U_0402_6.3VMZ

CPU_VID[0..6] (41)

220U_B2_2.5VM

1

C783

2

1

C784

C785

2

2.2U_0402_6.3VMZ

C782

2

2.2U_0402_6.3VMZ

1

C786

2

2.2U_0402_6.3VMZ

+1.5VS

1

C787

C788

2

2.2U_0402_6.3VMZ

1

C789

C791

2

10U_0603_6.3V6M

2.2U_0402_6.3VMZ

Length match within 25 mils. The trace width/space/other is

220U_B2_2.5VM

1

C821

2

10U_0603_6.3V6M

1

+

C45

C1012

C1012 330U_D2_2V_Y

330U_D2_2V_Y

2

20/7/25.

1

C790

0.1U_0402_16V7K

2

Near pin N30

+CPU_CORE

R24

R24 100_0402_1%

100_0402_1%

1 2

R26

R26 100_0402_1%

100_0402_1%

1 2

VCCSENSE

VSSSENSE

VCCSENSE (41)

VSSSENSE (41)

Close to CPU pin within 500mils.

SILVERTHORNE_FCBGA8-441

800MHz@

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFE RED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFE RED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFE RED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/08/04 2006/10/06

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

Silverthorne(3/3)-PWR/GND

JAX60

1

0.2

6 43Monday, April 28, 2008

0.2

of

5

H_D#[0..63](5) H_A#[3..31] (4)

D D

C C

+1.05VS

12

R569

56_0402_5%

B B

H_NMI(4) H_SMI#(4) H_PBE#(4)

H_STPCLK#(4)

H_INIT#(4,30) H_INTR(4)

H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31 H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63

R32 24_0402_5%

1 2

H_SWNG

H_TESTIN#

H_RCOMP TP_H_PLLMON1 TP_H_PLLMON1#

H_THERMTRIP_R#

U53A

V8

H_D0#

AF4

H_D1#

V2

H_D2#

AA1

H_D3#

AC1

H_D4#

AD2

H_D5#

V4

H_D6#

Y2

H_D7#

U1

H_D8#

Y8

H_D9#

AB2

H_D10#

AF2

H_D11#

AB4

H_D12#

AF8

H_D13#

AE1

H_D14#

AB8

H_D15#

AJ1

H_D16#

AH2

H_D17#

AM8

H_D18#

AN1

H_D19#

AK4

H_D20#

AG1

H_D21#

AH8

H_D22#

AK8

H_D23#

AP8

H_D24#

AK2

H_D25#

AR1

H_D26#

AT8

H_D27#

AT2

H_D28#

AH4

H_D29#

AP4

H_D30#

AP2

H_D31#

AV4

H_D32#

BB6

H_D33#

AV6

H_D34#

AY8

H_D35#

BA1

H_D36#

AU1

H_D37#

AT6

H_D38#

AV8

H_D39#

BB4

H_D40#

AT4

H_D41#

AY6

H_D42#

AV10

H_D43#

AV2

H_D44#

BC1

H_D45#

BB2

H_D46#

AY2

H_D47#

BD2

H_D48#

BH4

H_D49#

BD10

H_D50#

BK10

H_D51#

BD6

H_D52#

BD4

H_D53#

BF2

H_D54#

BE1

H_D55#

BD8

H_D56#

BF4

H_D57#

BH10

H_D58#

BK6

H_D59#

BB8

H_D60#

BF6

H_D61#

BF10

H_D62#

BH6

H_D63#

AB10

H_NMI

AB6

H_SMI#

AH6

H_PBE#

V6

H_SWING

AD10

H_STPCLK#

AK6

H_TESTIN#

T10

H_RCOMPO

AT10

RESERVED5

AP10

RESERVED4

AM6

H_THRMTRIP#

AF10

H_INIT#

AF6

H_INTR

POULSBO_FCBGA1249

layout note:

Route H_SCOMP and H_SCOMP# with trace width, spacing and impedance (55 ohm) same as FSB data traces

HOST

H_CPUPWRGD

4

H_A3# H_A4# H_A5# H_A6# H_A7# H_A8#

H_A9# H_A10# H_A11# H_A12# H_A13# H_A14# H_A15# H_A16# H_A17# H_A18# H_A19# H_A20# H_A21# H_A22# H_A23# H_A24# H_A25# H_A26# H_A27# H_A28# H_A29# H_A30# H_A31#

H_ADS# H_ADSTB0# H_ADSTB1#

H_GVREF

H_BNR#

H_BPRI#

H_BREQ0#

H_CPURST#

H_CGVREF

H_CLKINN

H_CLKINP

H_DBSY#

H_DEFER#

H_DINV0# H_DINV1# H_DINV2# H_DINV3#

H_DPWR#

H_DRDY# H_DSTBN0# H_DSTBN1# H_DSTBN2# H_DSTBN3# H_DSTBP0# H_DSTBP1# H_DSTBP2# H_DSTBP3#

H_HIT# H_HITM# H_LOCK# H_REQ0# H_REQ1# H_REQ2# H_REQ3# H_REQ4#

H_RS0# H_RS1# H_RS2#

H_CPUSLP#

H_TRDY#

H_DPSLP#

H_DPRSTP#

CFG0 CFG1

BSEL2

M2 M8 K4 P2 F4 G1 M4 F6 H6 D2 H2 J1 F2 D4 D12 H12 G11 A7 A9 A11 B6 H8 F10 B10 D6 D10 B12 B4 D8

K6 H4 B8 Y10 R1 P10 L1 M6 AD4

K10 M10 H10 AD6 AD8 AM2 AY10 BK8 P6 J9 Y4 AL1 AW1 BH8 W1 AM4 AY4 BF8

V10 T6 Y6 P4 N1 K8 P8 K2 T4 T2 T8 AH10 F12

AP6 F8 AK10

J27 B34 F28

H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16 H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31

H_ADS# H_ADSTB#0 H_ADSTB#1 H_VREF H_BNR# H_BPRI# H_BR0#

H_RESET#

CLK_MCH_BCLK# CLK_MCH_BCLK H_DBSY# H_DEFER# H_DINV#0 H_DINV#1 H_DINV#2 H_DINV#3 H_DPWR# H_DRDY# H_DSTBN#0 H_DSTBN#1 H_DSTBN#2 H_DSTBN#3 H_DSTBP#0 H_DSTBP#1 H_DSTBP#2 H_DSTBP#3

H_HIT# H_HITM# H_LOCK# H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4 H_RS#0 H_RS#1 H_RS#2 H_CPUSLP# H_TRDY#

H_ADS# (4) H_ADSTB#0 (4) H_ADSTB#1 (4)

H_BNR# (4) H_BPRI# (4) H_BR0# (4) H_RESET# (4)

CLK_MCH_BCLK# (15) CLK_MCH_BCLK (15) H_DBSY# (4) H_DEFER# (4) H_DINV#0 (5) H_DINV#1 (5) H_DINV#2 (5) H_DINV#3 (5) H_DPWR# (5) H_DRDY# (4) H_DSTBN#0 (5) H_DSTBN#1 (5) H_DSTBN#2 (5) H_DSTBN#3 (5) H_DSTBP#0 (5) H_DSTBP#1 (5) H_DSTBP#2 (5) H_DSTBP#3 (5)

H_HIT# (4) H_HITM# (4) H_LOCK# (4) H_REQ#0 (4) H_REQ#1 (4) H_REQ#2 (4) H_REQ#3 (4) H_REQ#4 (4)

H_RS#0 (4) H_RS#1 (4) H_RS#2 (4) H_CPUSLP# (5) H_TRDY# (4)

R558 10K_0402_5%

CFG0

1 2

R557 10K_0402_5%R557 10K_0402_5%

1 2

R556 10K_0402_5%R556 10K_0402_5%

1 2

CPU_BSEL2 (5,15)

3

+H_CGVREF

H_PWRGOOD (4,5) H_DPSLP# (5) H_DPRSTP# (5,41)

@

+1.05VS

12

R570

R570 1K_0402_1%

0.1U_0402_16V4Z

C51

In pre-ES R571=2k H_CGVREF=2/3VCCP In ES R571 choose 1k

+1.05VS

1K_0402_1%

12

1

R571

R571 1K_0402_1%

1K_0402_1%

2

H_THERMTRIP_R#

R767

1 2

24_0402_5%

+1.05VS

12

within 2" from R 1557

R300

R300 120_0402_5%

120_0402_5%

1

H_THERMTRIP# (4)

Layout Not e: H_RCOMP / H_VREF / H_SWNG

trace wid th and spa cing is 1 0/20

+1.05VS

12

R567

R567 1K_0402_1%

1K_0402_1%

0.1U_0402_16V4Z

R568

12

2K_0402_1%

0.1U_0402_16V4Z

1

C53

2

H_RCOMP

12

R41

24.9_0402_1%

A A

+1.05VS

12

R38

221_0603_1%

H_SWNGH_VREF

12

1

C54

R42

C54

2

100_0402_1%

0.1U_0402_16V4Z

Near B3 pinwithin 100 mils from NB

5

4

FSB BSEL2 CFG1 CFG0

100

1 0

133

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFE RED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFE RED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFE RED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

FSB

DDR

100

133

1000

Compal Secret Data

2006/08/04 2006/10/06

3

Compal Secret Data

Deciphered Date

2

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

Poulsbo(1/6)-AGTL+

JAX60

1

0.2

of

7 43Monday, April 28, 2008

5

D D

4

3

2

1

DDR_A_D[0..63](13,14)

C C

B B

DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8

DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15 DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63

U53D

BG49

SM_DQ0

BG47

SM_DQ1

BE45

SM_DQ2

BC43

SM_DQ3

BE47

SM_DQ4

BC47

SM_DQ5

BC45

SM_DQ6

BK44

SM_DQ7

BK42

SM_DQ8

BG41

SM_DQ9

BK40

SM_DQ10

BC41

SM_DQ11

BG43

SM_DQ12

BJ43

SM_DQ13

BJ39

SM_DQ14

BG39

SM_DQ15

BC39

SM_DQ16

BK38

SM_DQ17

BG37

SM_DQ18

BK36

SM_DQ19

BJ37

SM_DQ20

BG35

SM_DQ21

BJ35

SM_DQ22

BC35

SM_DQ23

BK34

SM_DQ24

BG31

SM_DQ25

BG33

SM_DQ26

BK30

SM_DQ27

BC33

SM_DQ28

BJ33

SM_DQ29

BJ31

SM_DQ30

BC31

SM_DQ31

BJ29

SM_DQ32

BG29

SM_DQ33

BK28

SM_DQ34

BC29

SM_DQ35

BE27

SM_DQ36

BK26

SM_DQ37

BG25

SM_DQ38

BJ25

SM_DQ39

BC25

SM_DQ40

BG23

SM_DQ41

BK22

SM_DQ42

BJ21

SM_DQ43

BK24

SM_DQ44

BJ23

SM_DQ45

BG21

SM_DQ46

BC21

SM_DQ47

BK20

SM_DQ48

BJ19

SM_DQ49

BG17

SM_DQ50

BJ17

SM_DQ51

BG19

SM_DQ52

BC19

SM_DQ53

BC17

SM_DQ54

BK16

SM_DQ55

BG15

SM_DQ56

BC15

SM_DQ57

BJ13

SM_DQ58

BK12

SM_DQ59

BK14

SM_DQ60

BJ15

SM_DQ61

BC13

SM_DQ62

BC11

SM_DQ63

POULSBO_FCBGA1249

SM_BS0 SM_BS1 SM_BS2

SM_CK0 SM_CK1

SM_CK0# SM_CK1#

SM_CKE0 SM_CKE1

SM_DQS0 SM_DQS1 SM_DQS2 SM_DQS3 SM_DQS4 SM_DQS5 SM_DQS6 SM_DQS7

SM_MA0 SM_MA1 SM_MA2 SM_MA3 SM_MA4 SM_MA5 SM_MA6 SM_MA7 SM_MA8

SM_MA9 SM_MA10 SM_MA11 SM_MA12 SM_MA13 SM_MA14

SM_VREF

SM_RAS# SM_CAS#

SM_WE#

SM_CS0# SM_CS1#

DDR SYSTEM MEMORY

SM_RCOMPO

SM_RCVENIN

SM_RCVENOUT

BE25 BA35

BG45 BE11

BJ45 BG11

BE39 BE37

BJ47 BJ41 BC37 BK32 BG27 BE23 BK18 BG13

BJ27 BA19 BA27 BA25 BE29 BC23 BE31 BA31 BA33 BA29 BE17 BE35 BE33 BE19 BA37

BE43

BE21 BA13

BA17

BA23 BA15

BE13

BA39 BE41

DDR_A_BS#1 DDR_A_BS#2

TP_M_CKE1

DDR_A_DQS0 DDR_A_DQS1 DDR_A_DQS2 DDR_A_DQS3 DDR_A_DQS4 DDR_A_DQS5 DDR_A_DQS6 DDR_A_DQS7

DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 TP_A_MA14

DDR_A_RAS# DDR_A_CAS#

DDR_A_WE#

TP_M_CS#1

SM_VREF

DDR_A_BS#0

BC27

DDR_A_BS#0 (13,14) DDR_A_BS#1 (13,14) DDR_A_BS#2 (13,14)

M_CLK_DDR0 (13,14) M_CLK_DDR1

M_CLK_DDR#0 (13,14) M_CLK_DDR#1

M_CKE0 (13,14)

DDR_A_DQS[0..7] (13,14)

DDR_A_MA[0..13] (13,14)

Layout Note: V_DDR_MCH_REF trace width and spacing is 20/20.

DDR_A_RAS# (13,14) DDR_A_CAS# (13,14)

DDR_A_WE# (13,14)

M_CS#0 (13,14)

R45 30.1_0402_1%R45 30.1_0402_1%

1

C55

0.1U_0402_16V4Z

2

1 2

+1.8V

1 2

R43

R43 10K_0402_1%

10K_0402_1%

R44

R44 10K_0402_1%

10K_0402_1%

+0.9VS

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFE RED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFE RED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFE RED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/08/04 2006/10/06

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

CRESTLINE((2/6)-DDR2 1CH

JAX60

8 43Monday, April 28, 2008

1

0.2

of

5

4

3

2

1

LPC_AD[0..3](30)

D D

R546 22_0402_5%R546 22_0402_5%

CLK_PCI_LPC(30)

+3VS

GMCH_BKLTCTL(22)

GMCH_ENBKL(22)

GMCH_LVDDEN(22)

MINSD_CLK(16) MINSD_CMD(16)

MINSD_DATA0 MINSD_DATA1 MINSD_DATA2 MINSD_DATA3

WIFI_DATA0 WIFI_DATA1 WIFI_DATA2 WIFI_DATA3

R818

SIRQ(30)

+3VS

MINSD_CD#(16)

MINSD_WP(16)

MINSD_PWR#(16)

WIFI_OFF(30)

WIFI_PWR#(17)

1 2

+3VS

12

R47

R48

10K_0402_5%

EDID_CLK_LCD(22) EDID_DAT_LCD(22)

C C

B B

EDID_CLK_LCD EDID_DAT_LCD

R48 10K_0402_5%

10K_0402_5%

MINSD_DATA[0..3](16)

WIFI_CLK(17) WIFI_CMD(17)

WIFI_DATA[0..3](17)

+3VS

40.2K_0402_1%

1 2

PCI_CLKRUN#(30)

R547 8.2K_0402_5%R547 8.2K_0402_5%

1 2

R548 8.2K_0402_5%R548 8.2K_0402_5%

1 2

LPC_FRAME#(30)

R49 10K_0402_5%

R49 10K_0402_5% R52 10K_0402_5%

R52 10K_0402_5%

EDID_CLK_LCD EDID_DAT_LCD

+3VS

LVDSAC+(22) LVDSAC-(22)

LVDSA0-(22) LVDSA1-(22) LVDSA2-(22)

LVDSA0+(22) LVDSA1+(22) LVDSA2+(22)

GMCH_LVDDEN

LVDSAC+ LVDSAC-

LVDSA0LVDSA1LVDSA2-

LVDSA0+ LVDSA1+ LVDSA2+

MINSD_CD#

R782

1 2

R577 10K_0402_5%R577 10K_0402_5%

1 2

R578

1 2

39K_0402_5%

1 2 1 2

0_0201_5%

R1187

R1187 0_0201_5%

0_0201_5%

GMCH_ENBKL

MINSD_CLK_R MINSD_CMD_R

MINSD_DATA0_R MINSD_DATA1_R MINSD_DATA2_R MINSD_DATA3_R

WIFI_CD# WIFI_CLK_R WIFI_CMD_R

WIFI_DATA0_R WIFI_DATA1_R WIFI_DATA2_R WIFI_DATA3_R

SD2_CMD_R

1 2

0_0201_5%

R1151

LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3

@

AF48 AF50

AG45

AK50 AH50 AG43

12

U53B

K38

LPC_AD0

J39

LPC_AD1

A35

LPC_AD2

L39

LPC_AD3

F38

LPC_CLKOUT0

B36

LPC_CLKOUT1

D38

LPC_CLKOUT2

D36

LPC_CLKRUN#

B38

LPC_SERIRQ

K40

LPC_FRAME#

A33

L_BKLTCTL

A31

L_BKLTEN

D28

L_CTLA_CLK

K26

L_CTLB_DATA

A27

L_DDCCLK

H28

L_DDCDATA

D30

L_VDDEN

LA_CLKP LA_CLKN

AJ43

LA_DATAN0

AK48

LA_DATAN1

AH48

LA_DATAN2 LA_DATAN3

AJ45

LA_DATAP0 LA_DATAP1 LA_DATAP2 LA_DATAP3

B18

SD0_CD#

D18

SD0_CLK

J15

SD0_CMD

H18

SD0_LED

F18

SD0_WP

H20

SD0_PWR#

H16

SD0_DATA0

A17

SD0_DATA1

K18

SD0_DATA2

F16

SD0_DATA3

K16

SD0_DATA4

B16

SD0_DATA5

D16

SD0_DATA6

K20

SD0_DATA7

B22

SD1_CD#

H22

SD1_CLK

F20

SD1_CMD

A21

SD1_LED

B20

SD1_WP

D20

SD1_PWR#

F22

SD1_DATA0

J19

SD1_DATA1

K22

SD1_DATA2

D22

SD1_DATA3

K24

SD2_CD#

D26

SD2_CLK

B24

SD2_CMD

D24

SD2_LED

B26

SD2_WP

A19

SD2_PWR#

J23

SD2_DATA0

A25

SD2_DATA1

F26

SD2_DATA2

A23

SD2_DATA3

F24

SD2_DATA4

H24

SD2_DATA5

H26

SD2_DATA6

E25

SD2_DATA7

G21

RESERVED18

POULSBO_FCBGA1249

LPC BUS

LVDS

MISC SIGNALSSYSTEM MGMTSDVOPCIE

LVDS

MISC SIGNALSSYSTEM MGMTSDVOPCIE

RTC

SDVO_CTRLCLK

SDIO / MMC

SDVO_CTRLDATA

SDVOB_STALL#

SDVOB_TVCLKIN

SDVOB_TVCLKIN#

SDVOB_GREEN

SDVOB_GREEN#

RESERVED8

RESERVED0 RESERVED1 RESERVED2 RESERVED3

RTC_X1 RTC_X2

INTVRMEN

RTCRST#

EXTTS

PWROK

SLPRDY#

DPRSLPVR

SLPMODE

RSMRST#

SDVOB_CLK

SDVOB_CLK#

SDVOB_INT

SDVOB_INT#

SDVOB_STALL

SDVOB_RED

SDVOB_RED#

SDVOB_BLUE

SDVOB_BLUE#

PCIE_PERn1 PCIE_PERp1 PCIE_PETn1 PCIE_PETp1

PCIE_PERn2 PCIE_PERp2 PCIE_PETn2 PCIE_PETp2

PCIE_CLKINN PCIE_CLKINP

PCIE_ICOMPI

PCIE_ICOMPO

BK50

E49 B32 BE15 BA21

F48 F50 F46 H48

D32

ICH_POK

C49 J49

D34

L45

L43

SDVO_CTRLCLK

F30

SDVO_CTRLDATA

A29

SDVOB_CLK_C

AV48

SDVOB_CLK_C#

AV50 AU47 AU49 AN45 AN43

SDVO_TVCLKIN

AP48

SDVO_TVCLKIN#

AP50

SDVOB_RED_C

AM50

SDVOB_RED_C#

AM48

SDVOB_GREEN_C

AT50

SDVOB_GREEN_C#

AT48

SDVOB_BLUE_C

AR45

SDVOB_BLUE_C#

AR43

AW45 AW43 BB48 BB50

BA43 BA45 BE49 BD50

R1089 0_0201_5%

1 2

AY48

R1088 0_0201_5%

1 2

AY50

BA47 BA49

R559

1 2

10K_0402_5%

ICH_RTCX1 ICH_RTCX2

ICH_RTCRST#

1 2

R32010K_0402_5% R32010K_0402_5%

R299

10K_0402_5%

R529 24.9_0402_1%R529 24.9_0402_1%

1 2

R318

10K_0402_5%

+RTCVCC

+3VS

ICH_POK (30) PM_SLPRDY# (30)

DPRSLPVR (41)

PM_SLPMODE (30)

EC_RSMRST# (30)

+1.5VS

R1195

20K_0201_5%

+RTCVCC

R317

R317 20K_0402_1%

20K_0402_1%

1U_0402_6.3V4Z

C350 3P_0402_50V8JC350 3P_0402_50V8J

32.768KHZ_12.5P_1TJE125DP1A000M

C351 3P_0402_50V8JC351 3P_0402_50V8J

1 2

X1

J3

1 2

JOPEN @J3JOPEN @

ICH_RTCRST#

1

C352

2

ICH_RTCX1

12

ICH_RTCX2

0_0402_5%

0_0402_5% R1091

R1091

1 2

12

R316

R316 10M_0402_5%

10M_0402_5%

RTCRST_KEY#

RP4

Issued Date

RP4

1 8 2 7 3 6 4 5

47_0804_8P4R_5%~D

RP5

1 8 2 7 3 6 4 5

47_0804_8P4R_5%~D

WIFI_DATA1_R WIFI_CMD_R

WIFI_DATA3_R WIFI_DATA0_R

WIFI_DATA2_R

Compal Secret Data

2006/08/04 2006/10/06

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Poulsbo(3/6)-LVDS/SDVO/SDIO

Size Document Number Rev

C

JAX60

Date: Sheet

1

of

9 43Monday, April 28, 2008

of

9 43Monday, April 28, 2008

of

9 43Monday, April 28, 2008

0.2

RP2

1 8

MINSD_DATA1 MINSD_DATA3 MINSD_DATA3_R

MINSD_DATA0 MINSD_DATA2 MINSD_CMD

A A

5

4

2 7 3 6 4 5

RP3

1 8 2 7 3 6 4 5

47_0804_8P4R_5%~D

MINSD_CLK_RMINSD_CLK

MINSD_DATA1_R

47_0804_8P4R_5%~D

MINSD_DATA0_R MINSD_DATA2_R MINSD_CMD_R

WIFI_DATA1

WIFI_CMD

WIFI_CLK WIFI_CLK_R

WIFI_DATA3 WIFI_DATA0

WIFI_DATA2

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

3

5

R576

10K_0402_5%

PD_A[0..3](25)

PD_D[0..15](25)

PD_IORDY

PD_IRQ

USB20_N0(28) USB20_P0(28) USB20_N1(20) USB20_P1(20) USB20_N2(28) USB20_P2(28) USB20_N3(33) USB20_P3(33) USB20_N4(19) USB20_P4(19) USB20_N5(18) USB20_P5(18) USB20_N6 USB20_P6 USB20_N7(33) USB20_P7(33)

USB_OC#0(28)

USB

GPS

CLIENT

D D

CAMARA(300K)

3G

BT

HUB

CAMARA(2.0M)

+3VALW

1 2

C C

B B

A A

4

USB20_N0 USB20_P0 USB20_N1 USB20_P1 USB20_N2 USB20_P2 USB20_N3 USB20_P3 USB20_N4 USB20_P4 USB20_N5 USB20_P5 USB20_N6 USB20_P6 USB20_N7 USB20_P7

R549

22.6_0402_1%

1 2

PD_DREQ(25) PD_IORDY(25) PD_IRQ(25) PD_DACK#(25) PD_IOW#(25) PD_IOR#(25) PD_CS#3(25) PD_CS#1(25)

R302 4.7K_0402_5% R302 4.7K_0402_5%

1 2

R1153 10K_0402_5%

1 2

PD_A2 PD_A1 PD_A0

PD_D15 PD_D14 PD_D13 PD_D12 PD_D11 PD_D10 PD_D9 PD_D8 PD_D7 PD_D6 PD_D5 PD_D4 PD_D3 PD_D2 PD_D1 PD_D0

+3VS

POULSBO_FCBGA1249

AE47 AE49 AD48 AD50 AB50 AB48 AA49 AA47

W45

AA45 AA43

W43

AC45 AC43

Y48 Y50 V50

V48 U47 U49

T50

T48

R43

R45 U43

U45

J43 D46 G45

B46

A37

F44 C47

E47

K42

J45 H40

B40

E43 H42 D42

F40

A43

A41

J41

A39

B42

F42 D44

L41

B44 G43 D40

U53C

USB_DN0 USB_DP0 USB_DN1 USB_DP1 USB_DN2 USB_DP2 USB_DN3 USB_DP3 USB_DN4 USB_DP4 USB_DN5 USB_DP5 USB_DN6 USB_DP6 USB_DN7 USB_DP7

USB_OC0# USB_OC1# USB_OC2# USB_OC3# USB_OC4# USB_OC5# USB_OC6# USB_OC7#

USB_RBIASN USB_RBIASP

PATA_DDREQ PATA_IORDY PATA_IDEIRQ PATA_DDACK# PATA_DIOW# PATA_DIOR# PATA_DCS3# PATA_DCS1#

PATA_DA2 PATA_DA1 PATA_DA0

PATA_DD15 PATA_DD14 PATA_DD13 PATA_DD12 PATA_DD11 PATA_DD10 PATA_DD9 PATA_DD8 PATA_DD7 PATA_DD6 PATA_DD5 PATA_DD4 PATA_DD3 PATA_DD2 PATA_DD1 PATA_DD0

3

USB I/F PATA/IDE

JTAG

RSTWARN GPIOSUS0 GPIOSUS1 GPIOSUS2 GPIOSUS3

SYSTEM GPIOsHD AUDIOCLOCK I/F

No-Connect

HDA_SYNC

HDA_RST#

HDA_DOCKEN#

HDA_DOCKRST#

RESERVED6 RESERVED7

DA_REFCLKINN

DA_REFCLKINP DB_REFCLKINNSSC DB_REFCLKINPSSC

USB_CLK48

SMB_ALERT#

SMB_DATA

SMB Termination Voltage

VTT_1 VTT_2 VTT_3 VTT_4 VTT_5 VTT_6 VTT_7 VTT_8

VTT_9 VTT_10 VTT_11 VTT_12 VTT_13 VTT_14 VTT_15 VTT_17 VTT_18 VTT_19 VTT_20 VTT_21 VTT_22 VTT_23 VTT_24 VTT_25 VTT_26 VTT_27 VTT_28 VTT_29 VTT_16

TRST#

TMS

TDO

STPCPU#

RSTRDY#

RESET#

WAKE#

SMI#

THRM#

GPE#

GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 GPIO8 GPIO9

SPKR

HDA_CLK

HDA_SDI0 HDA_SDI1 HDA_SDO

CLKREQ#

CLK14

SUSCLK

SMB_CLK

2

+1.05VS

AW13 AV12 AU13 AT12 AR13 AP12 AN13 AM12 AL13 AK12 AJ13 AH12 AG13 AF12 AE13 AC13 AB12 AA13 Y12 W13 V12 U13 T12 R13 P12 N13 M14 M12 AD12

N49 M50 K48

TDI

M48 N47

TCK

H30

H50 BA41 K50 U41 N43 N45 R41

N41 B30 F32 P50

G29 K30 F34 G33 K36 H36 F36 J31 H34 K28

J35 K14 E13 A13 F14 B14 D14 E15 H14

AU43 AU45 AL45 AL43 AE45 AE43 B28 H32 W41 J47

K32 G37 H38

TP_TRST# TP_TMS TP_TDI TP_TDO TP_TCK

100_0402_1%

R550

1 2

SCH_PCIE_WAKE#

EC_SMI#

R1152 1K_0402_5% @R1152 1K_0402_5% @

1 2

R1094 1K_0402_5%

1 2

512MB@

1 2

R1093

R1093 10K_0201_5%

10K_0201_5%

1

C805

2

1U_0402_6.3V4Z

EC_SMI# (30) EC_THERM# (4,30) EC_SCI# (30)

+3VS

SLPIOVR# (35)

CPU_C6

RP10 39_0804_8P4R_5%RP10 39_0804_8P4R_5%

1 8 2 7 3 6 4 5

R888

1 2

39_0402_5%

12

R765

R764

2.7K_0402_5%

1

C806

C807

2

1U_0402_6.3V4Z

T31 PADT31 PAD T14 PADT14 PAD T15 PADT15 PAD T16 PADT16 PAD

H_STP_CPU# (15)

PM_RSTRDY# (30) PLT_RST# (19,25,30) PM_RSTWARN (30)

SB_INT_FLASH_SEL (31) PBTN_OUT# (30)

CLK_MCH_DREFCLK# (15) CLK_MCH_DREFCLK (15) MCH_SSCDREFCLK# (15) MCH_SSCDREFCLK (15)

SCH_CLKREQ#

CLK_14M_SCH (15)

SUS_CLK

T11 PADT11 PAD

12

R766

2.7K_0402_5%

1

C829

C829 10U_0603_6.3V6M

10U_0603_6.3V6M

2

SCH_PCIE_WAKE#

EC_THERM#

HDA_BITCLK_AUDIO (26) HDA_SYNC_AUDIO (26) HDA_RST_AUDIO# (26,27) HDA_SDIN0 (26)

HDA_SDOUT_AUDIO (26)

1 2

R303 1K_0402_5%

@

1 2

R304 8.2K_0402_5%

SCH_GPIOSUS_3 (28)

SMB_DAT (15) SMB_CLK (15)

+3VS

+3VALW

+3VS

12

R802

R802 10K_0201_5%

10K_0201_5%

@

12

R803

R803 10K_0201_5%

10K_0201_5%

+3VS

1

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPE RTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPE RTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SE CRET INFORMATION. THIS SHEET MAY NOT B E TRANSFERED FRO M THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D

AND TRADE SE CRET INFORMATION. THIS SHEET MAY NOT B E TRANSFERED FRO M THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D

AND TRADE SE CRET INFORMATION. THIS SHEET MAY NOT B E TRANSFERED FRO M THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D DEPARTMENT EX CEPT AS AUTHORIZ ED BY COMPAL ELECTRONICS, INC . NEITHER THIS SHE ET NOR THE INFORMA TION IT CONTAINS

DEPARTMENT EX CEPT AS AUTHORIZ ED BY COMPAL ELECTRONICS, INC . NEITHER THIS SHE ET NOR THE INFORMA TION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/08/04 2006/10/06

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

CRESTLINE(4/6)-USB/PATA/HDA

JAX60

10 43Monday, April 28, 2008

of

1

of

0.2

5

+1.05VS

U53E

AG37

AF38

AF36 AE37 AD36

AT34

AT32 AR37 AP38 AP36 AN37 AU37

AT38

AT36 AM36 AV38

AK36

AJ37 AH38 AH36 AK38

AL37

+1.8V

U53E

VCCLVDS_101 VCCLVDS_100 VCCLVDS_1 VCCLVDS_2 VCCLVDS_3

VCCPCIE_4 VCCPCIE_5 VCCPCIE_6 VCCPCIE_7 VCCPCIE_8 VCCPCIE_9 VCCPCIE_1 VCCPCIE_2 VCCPCIE_3 VCCPCIE_100 VCCPCIE_101

VCCSDVO_110 VCCSDVO_100 VCCSDVO_101 VCCSDVO_103 VCCSDVO_106 VCCSDVO_105

D D

+1.5VS

1

C608

+1.5VS

1

C607

2

1U_0402_6.3V6K

1

2

1U_0402_6.3V6K

+1.5VS

C610

1U_0402_6.3V6K

C C

B B

C608

2

1U_0402_6.3V6K

4

T32

T30

T28

T26

T24

T22

T20

T18

T16

AK22

AK20

AK18

AK16

AH34

AH32

AH30

AH28

AH26

AH24

AH22

AB18

AB16

Y30

Y28

Y26

Y24

V22

V20

V18

VCC_79

VCC_80

VCCSM_100

VCCSM_101

VCCSM_43

AP16

AW35

AW33

AW31

Y22

T34

VCC_9

VCC_8

VCC_7

VCC_6

VCC_5

VCC_4

VCC_3

VCC_2

VCC_1

VCC_11

VCC_12

VCC_13

VCC_63

VCC_64

VCC_65

VCC_66

VCC_67

VCC_68

VCC_81

VCCSM_102

VCC_69

VCC_10

VCCSM_10

VCCSM_103

VCCSM_104

VCCSM_105

VCCSM_106

VCCSM_107

VCCSM_108

VCCSM_1

VCCSM_2

VCCSM_3

VCCSM_4

VCCSM_5

VCCSM_6

VCCSM_7

AV36

AV34

AV32

AV30

AV28

AW37

AW29

AW27

AW25

AW23

AW21

AW19

AV26

AW17

VCC_14

VCCSM_21

VCCSM_22

VCCSM_23

VCCSM_24

VCCSM_25

VCCSM_26

VCCSM_27

AT30

AT28

AV24

AT26

AV22

AV20

AV18

AV16

AH20

VCC_15

VCC_16

VCC_17

VCC_18

VCC_19

VCC_20

VCC_21

VCC_22

VCCSM_28

VCCSM_29

VCCSM_30

VCCSM_31

VCCSM_32

VCCSM_33

VCCSM_34

VCCSM_35

AT24

AT22

AT20

AT18

AT16

AP34

AP32

3

AM34

AM32

AM30

AM28

AM26

AM24

AM22

AM20

AH18

AH16

AF34

AF32

AF30

AF28

AF26

AF24

AF22

AF20

AF18

AF16

AD30

AD28

AD26

AD24

AD22

AD20

AD18

AD16

AB30

AB28

AB26

AB24

AB22

AB20

VCC_23

VCC_24

VCC_25

VCC_26

VCC_27

VCC_28

VCC_29

VCC_30

VCC_31

VCC_32

VCC_33

VCC_34

VCC_35

VCC_36

VCC_37

VCC_38

VCC_39

VCC_40

VCC_41

VCC_42

VCC

VCC33_15

VCC33SUS_1

VCC33SUS_2

VCC33SUS_3

VCCP33USBSUS_1

VCCP33USBSUS_2

RESERVED16

VCCSM_36

VCCSM_37

VCCSM_38

VCCSM_39

VCCSM_40

AP30

AP28

AP26

AP24

AP22

AP20

RESERVED17

VCCSM_41

VCCSM_42

RESERVED14

RESERVED15

VCCP33USBSUS_3

T38

Y38

R39

N37

N35

AP18

U37

M18

W39

AA39

AB36

AC37

VCC_49

VCC_43

VCC_44

VCC_45

VCC_46

VCC_47

VCC_48

VCC33_6

VCC33_9

VCC33_10

VCC33_11

VCC33_12

VCC33_13

VCC33_14

N19

N15

M30

M28

M26

M24

M22

M20

AM18

VCC_50

VCC_51

VCC_52

VCC_53

VCC_54

VCC_55

VCC_56

VCC_57

VCC33_1

VCC33_2

VCC33_3

VCC33_4

VCC33_5

VCC33_7

VCC33_8

VCC33_16

N29

N27

N25

N23

N21

N17

M16

2

C621

C620

1

C619

0.1U_0402_16V7K

AM16

AK34

AK32

AK30

AK28

AK26

AK24

Y18

Y16

V16

VCC_58

VCC_59

VCC_60

VCC_61

VCC_62

VCC_71

VCC_82

VCC_120

VCC_121

VCC33RTC

VCCHDA_1

VCCHDA_2

VCCAUSBPLL

VCCDHPLL

VCCAHPLL

VCCAUSBBGSUS

VSSAUSBBGSUS

J11

A45

K12

BB10

BA11

AE41

AC39

AC41

V34

VCC_72

VCC_73

V32

V30

V28

VCC_74

VCC_75

VCC_76

RESERVED10

RESERVED9

VCC15USB_1 VCC15USB_2 VCC15USB_3 VCC15USB_4 VCC15USB_5 VCC15USB_6

RESERVED12 RESERVED11 RESERVED13

VCCAPCIEBG

VSSAPCIEBG

VCCADPLLA

VCCAPCIEPLL

VCCADPLLB

AE39

AN49

AG39

Y20

V26

V24

VCC_70

VCC_77

VCC_78

VCC15_1 VCC15_2 VCC15_3 VCC15_4 VCC15_5 VCC15_6 VCC15_7 VCC15_8

VCC15_9 VCC15_10 VCC15_11 VCC15_12 VCC15_13 VCC15_14 VCC15_15 VCC15_16 VCC15_17 VCC15_18

VCC5REF_1

VCC5REFSUS

K34

AA41

+V5_5REFSUS_SCH

2

R33 R31 R29 R27 R25 R23 R21 R19 R17 R15 P34 P32 N33 N31 M38 M36 M34 M32

P38 P36

AD34 AD32 AB34 AB32 Y34 Y32

AB38 AA37 W37

AW41 AY42

21

+5VS

CH751H-40PT_SOD323-2

POULSBO_FCBGA1249

1

0.1U_0402_16V7K

2

1

C634

2

1U_0402_6.3V6K

Place under Poulsbo

+1.5VS

T9 PADT9 PAD

1 2

+5VALW+3VALW

12

D44

R889

10_0402_5%

PR119=>R889

1

C623

C622

1U_0402_6.3V6K

4.7U_0603_6.3V6K

2

Place under Poulsbo

+1.5VS

1

+

C47

2

150U_B2_6.3VM_R35M

T10 PADT10 PAD

+3VS

C633

1

R761

R761 0_0402_5%

0_0402_5%

2

0.1U_0402_16V7K

1

+

C819

2

C44

10U_0603_6.3V6M

2

150U_B2_6.3VM_R35M

C612

1

C611

2

1U_0402_6.3V6K

1

2

1

C820

C613

2

1U_0402_6.3V6K

1

Place under Poulsbo

A A

5

4

1

+

150U_B2_6.3VM_R35M

150U_B2_6.3VM_R35M C46

C46

2

10U_0603_6.3V6M

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFE RED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFE RED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFE RED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

T7

T8

PADT7PAD

PADT8PAD

C618

1

C617

2

0.1U_0402_16V7K

2006/08/04 2006/10/06

3

1

2

0.1U_0402_16V7K

+RTCVCC

+3VS

1

C615

C614

2

1U_0402_6.3V6K

Compal Secret Data

1U_0402_6.3V6K

Deciphered Date

1

+VCCAHPLL

C635

2

1U_0402_6.3V6K

0.1U_0402_16V7K

1U_0402_6.3V6K

R760

R760 0_0402_5%

0_0402_5%

1 2

+VCCAUSBPLL

R759

1 2

0_0402_5%

1

2

1

2

+1.5VS

1

C616

2

C632 0.1U_0402_16V7KC632 0.1U_0402_16V7K

C631

+3VALW+3VALW

+VCCADPLLA

+1.5VS

+VCCADPLLB

C630 0.1U_0402_16V7KC630 0.1U_0402_16V7K

0.1U_0402_16V7K

1

C629

0.1U_0402_16V7K

2

1 2

1

2

C1033

0_0402_5%

C628

1

2

R757

Title

Size Document Number Rev

Custom

Date: Sheet

1

0.1U_0402_16V7K

2

+1.5VS

Compal Electronics, Inc.

Poulsbo(5/6)-PWR

JAX60

of

11 43Monday, April 28, 2008

1

0.2

5

U53F

BH30

VSS_1

BH28

VSS_2

BH26

VSS_3

BH24

VSS_4

BH22

VSS_5

BH20

VSS_6

BH18

VSS_7

BH16

D D

C C

B B

A A

VSS_8

BH14

VSS_9

BH12

VSS_10

BH2

VSS_11

BG9

VSS_12

BG7

VSS_13

BG5

VSS_14

BG3

VSS_15

BG1

VSS_16

BF50

VSS_17

BF48

VSS_18

BF46

VSS_19

BF44

VSS_20

BF42

VSS_21

BF40

VSS_22

BF38

VSS_23

BF36

VSS_24

BF34

VSS_25

BF32

VSS_26

BF30

VSS_27

BF28

VSS_28

BF26

VSS_29

BF24

VSS_30

BF22

VSS_31

BF20

VSS_32

BF18

VSS_33

BF16

VSS_34

BF14

VSS_35

BF12

VSS_36

BE9

VSS_37

BE7

VSS_38

BE5

VSS_39

BE3

VSS_40

BD48

VSS_41

BD46

VSS_42

BD44

VSS_43

BD42

VSS_44

BD40

VSS_45

BD38

VSS_46

BD36

VSS_47

BD34

VSS_48

BD32

VSS_49

BD30

VSS_50

BD28

VSS_51

BD26

VSS_52

BD24

VSS_53

BD22

VSS_54

BD20

VSS_55

BD18

VSS_56

BD16

VSS_57

BD14

VSS_58

BD12

VSS_59

BC49

VSS_60

BC9

VSS_61

BC7

VSS_62

BC5

VSS_63

BC3

VSS_64

BB46

VSS_65

BB44

VSS_66

BB42

VSS_67

BB40

VSS_68

BB38

VSS_69

BB36

VSS_70

BB34

VSS_71

BB32

VSS_72

BB30

VSS_73

BB28

VSS_74

BB26

VSS_75

BA9

VSS_83

BB12

VSS_82

BB14

VSS_81

BB16

VSS_80

BB18

VSS_79

BB20

VSS_78

AM44

VSS_420

AM42

VSS_421

AM40

VSS_422

AM38

VSS_423

AM14

VSS_424

AM10

VSS_425

AL49

VSS_426

AL47

VSS_427

AL41

VSS_521

AL39

VSS_520

AL35

VSS_523

AL33

VSS_519

AL31

VSS_518

AL29

VSS_517

AL27

VSS_516

AL25

VSS_515

AL23

VSS_514

AL21

VSS_416

AL19

VSS_417

AL17

VSS_418

AL15

VSS_419

AL11

VSS_414

AL9

VSS_415

AK46

VSS_513

AL3

VSS_512

POULSBO_FCBGA1249

VSS

5

VSS_76 VSS_77 VSS_84 VSS_85 VSS_86 VSS_87 VSS_88 VSS_89 VSS_90 VSS_91 VSS_92 VSS_93 VSS_94 VSS_95 VSS_96 VSS_97 VSS_98

VSS_99 VSS_100 VSS_101 VSS_102 VSS_103 VSS_104 VSS_105 VSS_106 VSS_107 VSS_108 VSS_109 VSS_110 VSS_111 VSS_112 VSS_113 VSS_114 VSS_115 VSS_116 VSS_117 VSS_118 VSS_119 VSS_120 VSS_121 VSS_122 VSS_123 VSS_124 VSS_125 VSS_126 VSS_127 VSS_128 VSS_129 VSS_130 VSS_131 VSS_132 VSS_133 VSS_134 VSS_135 VSS_136 VSS_137 VSS_138 VSS_139 VSS_140 VSS_141 VSS_142 VSS_143 VSS_144 VSS_145 VSS_146 VSS_147 VSS_148 VSS_149 VSS_150 VSS_151 VSS_152 VSS_153 VSS_154 VSS_155 VSS_156 VSS_384 VSS_385 VSS_386 VSS_387 VSS_388 VSS_389 VSS_390 VSS_391 VSS_392 VSS_393 VSS_394 VSS_395 VSS_396 VSS_397 VSS_398 VSS_399 VSS_400 VSS_401 VSS_402 VSS_522 VSS_405 VSS_406 VSS_407 VSS_408 VSS_409 VSS_410 VSS_411 VSS_412 VSS_413 VSS_510 VSS_511

BB24 BB22 BA7 BA5 BA3 AY46 AY44 AY40 AY38 AY36 AY34 AY32 AY30 AY28 AY26 AY24 AY22 AY20 AY18 AY16 AY14 AY12 AW49 AW47 AW39 AW15 AW11 AW9 AW7 AW5 AW3 AV46 AV44 AV42 AV40 AV14 AU41 AU39 AU35 AU33 AU31 AU29 AU27 AU25 AU23 AU21 AU19 AU17 AU15 AU11 AU9 AU7 AU5 AU3 AT46 AT44 AT42 AT40 AT14 AR49 AR47 AR41 AR39 AR35 AR33 AR31 AR29 AR27 AR25 AR23 AR21 AR19 AR17 AR15 AR11 AR9 AR7 AR5 AR3 AP46 AP44 AP42 AP40 AP14 AN47 AN41 AN39 AN35 AN33 AN31 AN29 AN27 AN25 AN23 AN21 AN19 AN17 AN15 AN11 AN9 AN7 AN5 AN3 AM46 AL7 AL5

4

AJ3

AH46

AH44

AH42

AH40

AH14

AG49

AG47

AG41

AG35

AG33

AG31

U53G

W35

VSS_293

W33

VSS_294

W31

VSS_295

W29 W27 W25 W23 W21 W19 W17 W15 W11

W9 W7 W5

W3 V46 V44 V42

AJ41 AJ47

AJ49 AK14 AK40 AK44

AJ5 AJ7

AJ9 AJ11 AJ15 AJ17 AJ19 AJ21 AJ23 AJ25 AJ27 AJ29 AJ31 AJ33 AJ35 AJ39

L9 L7 L5

L3 K46 K44

J37 J33 J29 J25

J21 U27 U25 G47 G41 G39 G35 G31 G27 G25 G23 C19 C17 C15 C13

G3

E45

BJ1

BH50 BH48 BH46 BH44 BH42

4

VSS_296 VSS_297 VSS_298 VSS_299 VSS_300 VSS_301 VSS_302 VSS_303 VSS_304 VSS_305 VSS_306 VSS_307 VSS_308 VSS_309 VSS_310 VSS_311 VSS_163 VSS_162 VSS_161 VSS_160 VSS_159 VSS_157 VSS_179 VSS_178 VSS_177 VSS_176 VSS_175 VSS_174 VSS_173 VSS_172 VSS_171 VSS_170 VSS_169 VSS_168 VSS_167 VSS_166 VSS_165 VSS_164 VSS_323 VSS_324 VSS_325 VSS_326 VSS_327 VSS_328 VSS_329 VSS_330 VSS_331 VSS_332 VSS_333 VSS_709 VSS_710 VSS_335 VSS_336 VSS_337 VSS_338 VSS_339 VSS_340 VSS_341 VSS_342 VSS_504 VSS_503 VSS_502 VSS_501 VSS_505 VSS_506 VSS_1014 VSS_1015 VSS_1016 VSS_1017 VSS_1018 VSS_1019

VSS_1022

V38

BH36

VSS_180

VSS_181

VSS_182

VSS_183

VSS_184

VSS_701

VSS_702

VSS_703

VSS_704

VSS_705

VSS_706

VSS_707

VSS_708

V36

V14

P48

U39

U35

U33

U31

U29

AG29

VSS_185

VSS_186

VSS_187

VSS_188

VSS_189

VSS_190

VSS_191

VSS_192

VSS_736

VSS_737

VSS_738

VSS_800

VSS_801

VSS_802J7VSS_803J5VSS_804J3VSS_805

J17

J13

P46

P44

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFE RED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFE RED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFE RED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

AG27

AG25

AG23

AG21

AG19

AG17

AG15

AG11

AG9

AG7

AG5

AG3

AF46

AF44

AF42

AF40

AF14

AE35

AE33

AE31

AE29

AE27

AE25

AE23

AE21

AE19

AE17

AE15

AE11

AE9

AE7

AE5

AE3

AD46

AD44

VSS_193

VSS_194

VSS_195

VSS_196

VSS_197

VSS_198

VSS_199

VSS_200

VSS_201

VSS_202

VSS_203

VSS_204

VSS_205

VSS_206

VSS_207

VSS_208

VSS_209

VSS_210

VSS_211

VSS_212

VSS_213

VSS_214

VSS_215

VSS_216

VSS_217

VSS_218

VSS_219

VSS_220

VSS_221

VSS_222

VSS_223

VSS_224

VSS_225

VSS_226

VSS_227

VSS

VSS_711

VSS_712

VSS_713

VSS_714

VSS_715

VSS_716

VSS_717U9VSS_718U7VSS_719U5VSS_720U3VSS_721

VSS_722

VSS_723

VSS_724

VSS_725

VSS_726

VSS_727

VSS_728

VSS_729

VSS_730

VSS_731

VSS_806

VSS_807

T46

T44

T42

T40

T36

U23

U21

U19

U17

U15

H46

H44

U11

G49

3

T14

R49

R47

2006/08/04 2006/10/06

VSS_732R9VSS_733R7VSS_734R5VSS_735

R3

R37

R35

R11

Compal Secret Data

VSS_850

VSS_851

VSS_852

VSS_853E9VSS_854

E7

E19

E17

E11

N11

Deciphered Date

VSS_750

VSS_751

N39

2

AD42

AD40

AD38

AD14

AC49

AC47

AC35

AC33

AC31

AC29

AC27

AC25

AC23

AC21

AC19

AC17

AC15

AC11

AC9

AC7

AC5

AC3

AB46

AB44

AB42

AB40

AB14

AA35

AA33

AA31

AA29

AA27

AA25

AA23

AA21

VSS_228

VSS_229

VSS_230

VSS_231

VSS_232

VSS_233

VSS_234

VSS_235

VSS_236

VSS_237

VSS_238

VSS_239

VSS_240

VSS_241

VSS_242

VSS_243

VSS_244

VSS_245

VSS_246

VSS_247

VSS_248

VSS_249

VSS_250

VSS_251

VSS_252

VSS_253

VSS_254

VSS_255

VSS_256

VSS_257

VSS_258

VSS_259

VSS_260

VSS_261

VSS_700

VSS_739

VSS_740

VSS_741

VSS_742

VSS_743

VSS_744

VSS_745

VSS_746

VSS_747

VSS_748

VSS_749

P24

P22

P20

P18

P16

P14

VSS_855E5VSS_856E3VSS_857E1VSS_858

VSS_859

VSS_860

VSS_861

VSS_862

VSS_863

VSS_864

VSS_865

VSS_866

VSS_867

VSS_868

VSS_869

VSS_870

VSS_871

VSS_872

VSS_873

VSS_874C9VSS_875C7VSS_876C5VSS_877C3VSS_878C1VSS_879

V40

P42

P40

P30

P28

P26

2

D50

D48

C45

C43

C41

C39

C37

C35

C33

C31

C29

C27

C25

C23

C21

C11

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

Poulsbo(6/6)-GND

JAX60

1

BH34

VSS_1023

AA19

VSS_263

AA17

VSS_264 VSS_265 VSS_266 VSS_267 VSS_268 VSS_269 VSS_270 VSS_271 VSS_272 VSS_273 VSS_274 VSS_275 VSS_276 VSS_277 VSS_278 VSS_292 VSS_291 VSS_290 VSS_289 VSS_288 VSS_287 VSS_286 VSS_285 VSS_284 VSS_283 VSS_282 VSS_281 VSS_280 VSS_279 VSS_312 VSS_313 VSS_314 VSS_315 VSS_316 VSS_317 VSS_318 VSS_319 VSS_320 VSS_321 VSS_343 VSS_344 VSS_345 VSS_346 VSS_347 VSS_348 VSS_349 VSS_158 VSS_404 VSS_403 VSS_383 VSS_378 VSS_379 VSS_380 VSS_381 VSS_382 VSS_508 VSS_507 VSS_882

VSS_881 VSS_1003 VSS_1000 VSS_1001 VSS_1004 VSS_1005 VSS_1006 VSS_1007 VSS_1008 VSS_1009 VSS_1010 VSS_1011 VSS_1012 VSS_1013

VSS_880

VSS_883

VSS_1024

A47

BH32

VSS_1020

VSS_1021

BH40

BH38

1

AA15 AA11 AA9 AA7 AA5 AA3 Y46 Y44 Y42 Y40 Y36 Y14 W49 W47 N9 N7 N5 N3 M46 M44 M42 M40 L49 L47 L37 L35 L33 L31 L29 L27 L25 L23 L21 L19 L17 L15 L13 L11 G19 G17 G15 G13 G9 G7 G5 AK42 E21 E23 E27 E29 E31 E33 E35 E37 E39 E41 A49 B2 A15 A5 A3 BK48 BK46 BK4 BK2 BJ49 BJ11 BJ9 BJ7 BJ5 BJ3

POULSBO_FCBGA1249

of

12 43Monday, April 28, 2008

0.2

VSS_262

B50

B48

5

DDR_A_BS#[0..2](8,14)

DDR_A_D[0..63](8,14)

DDR_A_DQS[0..7](8,14)

DDR_A_MA[0..13](8,14)

D D

M_CLK_DDR#0(8,14) M_CLK_DDR0(8,14)

M_CKE0(8,14)

M_CS#0(8,14)

DDR_A_WE#(8,14)

DDR_A_RAS#(8,14)

DDR_A_CAS#(8,14)

C C

M_ODT(14)

+1.8V

R53

+VRAM_VREFA

R74

1K_0402_1%

R53

1K_0402_1%

1 2

12

1

C334

0.1U_0402_16V4Z

2

DDR_A_BS#0 DDR_A_BS#1

(SSTL-1.8) VREF = .5* VDDQ

Close to U7

DDR_A_MA12 DDR_A_MA11 DDR_A_MA10 DDR_A_MA9 DDR_A_MA8 DDR_A_MA7 DDR_A_MA6 DDR_A_MA5 DDR_A_MA4 DDR_A_MA3 DDR_A_MA2 DDR_A_MA1 DDR_A_MA0

M_CLK_DDR#0 M_CLK_DDR0

M_CKE0

M_CS#0

DDR_A_WE#

DDR_A_RAS#

DDR_A_CAS#

M_ODT

DDR_A_DQS0

DDR_A_DQS1

DDR_A_BS#2

DDR_A_MA13

4

U13

L2

BA0

L3

BA1

R2

A12

P7

A11

M2

A10/AP

P3

A9

P8

A8

P2

A7

N7

A6

N3

A5

N8

A4

N2

A3

M7

A2

M3

A1

M8

A0

K8

CK

J8

CK

K2

CKE

L8

CS

K3

WE

K7

RAS

L7

CAS

F3

LDM

B3

UDM

K9

ODT

F7

LDQS

E8

LDQS

B7

UDQS

A8

UDQS

J2

VREF

A2

NC#A2

E2

NC#E2

L1

NC#L1

R3

NC#R3

R7

NC#R7

R8

NC#R8

K4T1G164QD-ZCE6 FBGA84

512MB@

DQ15 DQ14 DQ13 DQ12 DQ11 DQ10

DQ9 DQ8 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0

VDDQ1 VDDQ2 VDDQ3 VDDQ4 VDDQ5 VDDQ6 VDDQ7 VDDQ8 VDDQ9

VDDQ10

VDD1 VDD2 VDD3 VDD4 VDD5

VDDL

VSSDL

VSSQ1 VSSQ2 VSSQ3 VSSQ4 VSSQ5 VSSQ6 VSSQ7 VSSQ8 VSSQ9

VSSQ10

VSS1 VSS2 VSS3 VSS4 VSS5

3

DDR_A_D14

B9

DDR_A_D9

B1

DDR_A_D10

D9

DDR_A_D12

D1

DDR_A_D13

D3

DDR_A_D11

D7

DDR_A_D8

C2

DDR_A_D15

C8

DDR_A_D4

F9

DDR_A_D3

F1

DDR_A_D7

H9

DDR_A_D6

H1

DDR_A_D5

H3

DDR_A_D1

H7

DDR_A_D2

G2

DDR_A_D0

G8

A9 C1 C3 C7 C9 E9 G1 G3 G7 G9

A1 E1 J9 M9 R1

J1 J7

A7 B2 B8 D2 D8 E7 F2 F8 H2 H8

A3 E3 J3 N1 P9

+1.8V

Group1

Group0

+VRAM_VREFA

1

C335

0.1U_0402_16V4Z

2

DDR_A_BS#0 DDR_A_BS#1

(SSTL-1.8) VREF = .5* VDDQ

Close to U7

DDR_A_MA12 DDR_A_MA11 DDR_A_MA10 DDR_A_MA9 DDR_A_MA8 DDR_A_MA7 DDR_A_MA6 DDR_A_MA5 DDR_A_MA4 DDR_A_MA3 DDR_A_MA2 DDR_A_MA1 DDR_A_MA0

M_CLK_DDR#0 M_CLK_DDR0

M_CKE0

M_CS#0

DDR_A_WE#

DDR_A_RAS#

DDR_A_CAS#

M_ODT

DDR_A_DQS2

DDR_A_DQS3

DDR_A_BS#2

DDR_A_MA13

2

U8

L2

BA0

L3

BA1

R2

A12

P7

A11

M2

A10/AP

P3

A9

P8

A8

P2

A7

N7

A6

N3

A5

N8

A4

N2

A3

M7

A2

M3

A1

M8

A0

K8

CK

J8

CK

K2

CKE

L8

CS

K3

WE

K7

RAS

L7

CAS

F3

LDM

B3

UDM

K9

ODT

F7

LDQS

E8

LDQS

B7

UDQS

A8

UDQS

J2

VREF

A2

NC#A2

E2

NC#E2

L1

NC#L1

R3

NC#R3

R7

NC#R7

R8

NC#R8

K4T1G164QD-ZCE6 FBGA84

512MB@

DQ15 DQ14 DQ13 DQ12 DQ11 DQ10

DQ9 DQ8 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0

VDDQ1 VDDQ2 VDDQ3 VDDQ4 VDDQ5 VDDQ6 VDDQ7 VDDQ8 VDDQ9

VDDQ10

VDD1 VDD2 VDD3 VDD4 VDD5

VDDL

VSSDL

VSSQ1 VSSQ2 VSSQ3 VSSQ4 VSSQ5 VSSQ6 VSSQ7 VSSQ8 VSSQ9

VSSQ10

VSS1 VSS2 VSS3 VSS4 VSS5

1

DDR_A_D26

B9

DDR_A_D27

B1

DDR_A_D24

D9

DDR_A_D30

D1

DDR_A_D31

D3

DDR_A_D28

D7

DDR_A_D25

C2

DDR_A_D29

C8

DDR_A_D19

F9

DDR_A_D21

F1

DDR_A_D17

H9

DDR_A_D23

H1

DDR_A_D18

H3

DDR_A_D16

H7

DDR_A_D22

G2

DDR_A_D20

G8

A9 C1 C3 C7 C9 E9 G1 G3 G7 G9

A1 E1 J9 M9 R1

J1 J7

A7 B2 B8 D2 D8 E7 F2 F8 H2 H8

A3 E3 J3 N1 P9

Group3

Group2

+1.8V

B B

A A

5

+1.8V

0.1U_0402_16V4Z

1

C267

2

0.01U_0402_16V7K

1

C266

2

1U_0402_6.3V4Z

4

0.1U_0402_16V4Z

1

C332

2

M_ODT

Issued Date

12

R575

R575 10K_0201_5%

10K_0201_5%

M_CLK_DDR0

M_CLK_DDR#0

3

12

R574

R574 100_0402_1%

100_0402_1%

Compal Secret Data

2006/08/04 2006/10/06

Compal Secret Data

1

C268

2

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFE RED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFE RED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFE RED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

0.01U_0402_16V7K

Deciphered Date

+1.8V

1

2

0.1U_0402_16V4Z

1

C259

2

1

C258

2

1U_0402_6.3V4Z

0.1U_0402_16V4Z

1

C261

2

C260

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

DDRII-DEVICE DOWN(1/2)

JAX60

1

0.2

of

13 43Monday, April 28, 2008