COMPAL LA-4241P Schematics

hexainf@hotmail.com

ZZZ1

PCB

14WDAZ@

1 1

ZZZ2

ZZZ3

LA-4241P

14WDA@

ZZZ8

ZZZ4

LS-4243P

14WDA@

ZZZ9

ZZZ5

LS-4244P

14WDA@

ZZZ10

ZZZ6

LS-4249P

14WDA@

ZZZ11

ZZZ12

PJP1

14W_DCIN

14W_45@

ZZZ13

12/21 Add PJP1 for DCIN Cable on 45 Level One for 14W DCIN , PN: DC301001Y00

PJP1

15W_DCIN

15W_45@

Another for 15W DCIN , PN: DC301001V00

LS-4242P

PCB

15WDAZ@

LA-4241P

15WDA@

LS-4242P

15WDA@

LS-4243P

15WDA@

LS-4244P

15WDA@

LS-4245P

15WDA@

LS-4246P

15WDA@

05/20 Add DAZ PCB Panel P/N

Compal Confidential

2 2

JHXXX Schematics Document

Intel Penryn Processor with Cantiga + DDRII + ICH9M

(With nVIDIA MXM/B)

2008-06-03

REV: 1.0

3 3

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2007/08/18 2008/8/18

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

Cover Page

JHXXX M/B LA-4241P Schematic

149Tuesday, June 03, 2008

0.4

Compal Confidential

Model Name : JHXXX

Fan Control

page 4

File Name : LA-4241P

1 1

LCD Conn.

page 18

LVDS

HDMI

page 25

CRT

page 19

PCI-Express

MXM II VGA/B

page 17

2 2

PCI-Express

Intel Penryn Processor

uPGA-478 Package

H_A#(3..35)

FSB

667/800MHz

Intel Cantiga

uFCBGA-1329

page 7,8,9,10,11,12,13

DMI X4 mode

Intel ICH9-M

page 4,5,6

H_D#(0..63)

3.3V 48MHz

3.3V 24.576MHz/48Mhz

Thermal Sensor

ADT7421

page 4

Memory BUS(DDRII)

Dual Channel

1.8V DDRII 533/667

USB conn x3 TO I/O/B

page 35 page 34 page 40

USB

BGA-676

New Card Socket

page 31

3 3

MINI Card x3

WLAN, TV-Tuner Robson

page 30

LAN(GbE)

RTL8111C/8102E

page 28

RJ45

page 29

Card Reader

JMB385

page 26

socket

page 26

page 20,21,22,23

LPC BUS

S-ATA

port 0

S-ATA HDD Conn.

page 24

S-ATA ODD Conn.

page 24

Clock Generator

ICS9LPRS387

page 16

200pin DDRII-SO-DIMM X2

BANK 0, 1, 2, 3

Bluetooth

page 14,15

CMOS Camera

Conn

HD Audio

GMCH HDA

page 8

MDC 1.5 Conn

page 40

Finger Print Conn

page 40

HDA Codec

ALC268

page 36

Audio AMP3 in 1

page 37

RTC CKT.

page 21

Function/B

Power On/Off CKT.

page 35

Power USB/B

page 33

Touch Pad

USB I/O Conn.

DC/DC Interface CKT.

page 41

Power Circuit DC/DC

4 4

page 41,42,43,45 46,47,48

CIR LID SW Debug port

page 35

ENE KB926

page 34

page 32

Int.KBD

page 33

BIOS

page 34

SCREW

page 39

TPM

CHARGER

page 44

LED

page 40

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2007/08/18 2008/8/18

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

Block Diagrams

JHXXX M/B LA-4241P Schematic

249Friday, April 11, 2008

0.4

hexainf@hotmail.com

Voltage Rails

Power Plane

VIN

1 1

B+ +CPU_CORE

+1.05VS +1.5VS +1.8V +1.8VS +3VALW +3VS +5VALW +5VS +VSB +RTCVCC

Description

Adapter power supply (19V) AC or battery power rail for power circuit. Core voltage for CPU

0.9V switched power rail for DDR terminator+0.9VS ( Actual +0.9V )

1.05V switched power rail

1.5V switched power rail

1.8V power rail for DDR

1.8V switched power rail

3.3V always on power rail

3.3V switched power rail 5V always on power rail 5V switched power rail VSB always on power rail RTC power

S3S1

OFF

ON OFF

OFF ON OFF

N/AN/AN/A

OFF OFF OFFOFF OFFOFF OFF OFF ON*ON OFF ON* OFF ON*ON ON

N/A N/A N/A ON ON ON ON ON ON ON ON ON ON

ONONON

EC SM Bus1 address

Device

Smart Battery EEPROM(24C16/02)

Address

1010 000X b

EC SM Bus2 address

Device

ADI ADM1032 NVIDIA NB8X

Address

1001 100X b0001 011X b

2 2

STATE

SIGNAL

Full ON

S1(Power On Suspend)

S3 (Suspend to RAM)

S4 (Suspend to Disk)

S5 (Soft OFF)

SLP_S3#SLP_S1#

SLP_S4#

HIGH HIGH HIGH

LOW

HIGH

LOW

LOW LOW LOW

LOWLOWLOW

SLP_S5#

HIGHHIGHHIGHHIGH

HIGH

LOW

+VALW

+V +VS Clock

OFF

ONON

LOW

OFF

ICH9M SM Bus address

Device

Clock Generator (ICS9LPRS325AKLFT_MLF72)

DDR DIMM0 DDR DIMM1

Address

1101 001Xb

1010 000Xb 1010 010Xb

SKU ID Table

Vcc 3.3V +/- 5%

47K +/- 5%Rb

R472

4.7K_0402_5%

H_14_C@

R472

10K_0402_5%

H_14_MP@

R472

18K_0402_5%

H_15_B@

R472

27K_0402_5%

H_15_C@

R472

39K_0402_5%

H_15_MP@

R472

Rb~ R470

PROJECT ID Table

3 3

JHT00 ( 00@ )

ID1 R361

JHT01 ( 01@ )

R360

JHL91 ( 11@ ) R360 R355

ID0 R357 R355R361 R357JHL90 ( 10@ )

MIC ID Table

R585 Single MIC R583 Array MIC

Structure

SINGLE@ DUAL@

Ra~ R472

Board ID

1 2 3 4 5 6 7 8 9 10 11 12

NA 4.7K +/- 5% 47K(RB@) 47K(RB@) 47K(RB@) 47K(RB@) 47K(RB@) 47K(RB@) 47K(RB@) 47K(RB@) 47K(RB@) 47K(RB@) 47K(RB@)

4.7K +/- 5% 10K +/- 5% 18K +/- 5% 27K +/- 5% 39K +/- 5% 56K +/- 5% 82K +/- 5% 120K +/- 5% 220K +/- 5% 470K +/- 5% NA

56K_0402_5%

L_14_B@

Ra V min

AD_BID

82K_0402_5%

L_14_C@

0 V

0.274 V 0.300 V 0.328 V

0.553V

0.849V

1.129 V

1.415 V 1.496 V 1.579 V

1.712 V

2.020V

2.303 V

2.670 V

2.972 V

3.135 V

120K_0402_5%

L_14_MP@

V typ

AD_BID

220K_0402_5%

L_15_B@

AD_BID

0 V 0 V

0.578 V

0.913V

0.628 V

0.981 V

1.204 V 1.282 V

1.794 V

2.097 V

2.371 V

2.719 V

3.000 V

3.300 V

1.876 V

2.173 V

2.437 V

2.765 V

3.026 V

3.465 V

470K_0402_5%

L_15_C@

Ra BOM Structure

max

H_14_B@ H_14_C@ H_14_MP@ H_15_B@ H_15_C@ H_15_MP@ L_14_B@ L_14_C@ L_14_MP@ L_15_B@ L_15_C@

NA for L_15_MP

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2007/08/18 2008/8/18

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

Notes List

JHXXX M/B LA-4241P Schematic

349Tuesday, June 03, 2008

0.4

EMI Recommend

+1.05VS

Which to follow?

D D

H_A#[3..35]<7> H_REQ#[0..4]<7> H_RS#[0..2]<7>

C C

B B

A A

H_A#[3..35] H_REQ#[0..4] H_RS#[0..2]

JCPU1A

H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15

H_ADSTB#0<7>

H_ADSTB#1<7> H_A20M#<21>

H_FERR#<21> H_IGNNE#<21>

H_STPCLK#<21> H_INTR<21> H_NMI<21> H_SMI#<21>

H_A#16

H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4

H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 H_A#32 H_A#33 H_A#34 H_A#35

JCPU1A

A[3]#

A[4]#

A[5]#

A[6]#

A[7]#

A[8]#

A[9]#

A[10]#

A[11]#

A[12]#

A[13]#

A[14]#

A[15]#

A[16]#

ADSTB[0]#

REQ[0]#

REQ[1]#

REQ[2]#

REQ[3]#

REQ[4]#

A[17]#

A[18]#

A[19]#

A[20]#

A[21]#

A[22]#

A[23]#

A[24]#

A[25]#

A[26]#

A[27]#

A[28]#

A[29]#

A[30]#

A[31]#

A[32]#

AA4

A[33]#

AB2

A[34]#

AA3

A[35]#

ADSTB[1]#

A20M#

FERR#

IGNNE#

STPCLK#

LINT0

LINT1

SMI#

RSVD[01]

RSVD[02]

RSVD[03]

RSVD[04]

RSVD[05]

RSVD[06]

RSVD[07]

D22

RSVD[08]

RSVD[09]

RSVD[10]

Merom Ball-out Rev 1a

CONN@

ADDR GROUP 0 ADDR GROUP 1

XDP/ITP SIGNALS

THERMAL

PROCHOT#

THERMDA THERMDC

ICH

THERMTRIP#

H CLK

RESERVED

ADS# BNR#

BPRI#

DEFER#

DRDY# DBSY#

BR0#

IERR#

INIT#

LOCK#

CONTROL

RESET#

RS[0]# RS[1]# RS[2]#

TRDY#

HIT#

HITM#

BPM[0]# BPM[1]# BPM[2]# BPM[3]#

PRDY# PREQ#

TCK

TDO TMS

TRST#

DBR#

BCLK[0] BCLK[1]

H1 E2 G5

H5 F21 E1

H_IERR#

D20 B3

H_RESET#

H_RS#0

H_RS#1

H_RS#2

G3 G2

G6 E4

AD4 AD3 AD1 AC4 AC2

EMI Recommend

AC1

ITP_TCK

AC5

ITP_TDI

AA6

TDI

AB3

ITP_TMS

AB5

ITP_TRST#

AB6

ITP_DBRESET#

C20

H_PROCHOT#

D21

THERMDA_R

A24

THERMDC_R

B25 C7

A22 A21

1 2

R705 0_0402_5%R705 0_0402_5%

Layout Note: THERMDA&THERMDC Trace / Space = 10 / 10 mil THERMDA_R&THERMDC_R Trace / Space = 10 / 10 mil

H_ADS# <7> H_BNR# <7> H_BPRI# <7>

H_DEFER# <7> H_DRDY# <7> H_DBSY# <7>

H_BR0# <7>

H_INIT# <21> H_LOCK# <7> H_RESET# <7>

H_TRDY# <7> H_HIT# <7>

H_HITM# <7>

ITP_DBRESET# <22> H_PROCHOT# <48>

R19 100_0402_5%SMSC@R19 100_0402_5%SMSC@ R20 100_0402_5%SMSC@R20 100_0402_5%SMSC@

CLK_CPU_BCLK <16> CLK_CPU_BCLK# <16>

R19

0_0402_5%

NS@

THERMDA THERMDC

H_THERMTRIP# <8,21>

R20

0_0402_5%

NS@

TCK TDI TMS TRST# PREQ#

Checklist CRB

55_5% 55_5% 55_1% 55_5% x

EMC1402

2200P_0402_50V7K

+3VS

Address:100_1100

FAN1 Conn

EN_FAN1<32>

54.9_1%

1/29 change to EMC1402 pn

THERMDA

THERMDC

1 2

R18 10K_0402_5%R18 10K_0402_5%

+5VS

+VCC_FAN1

EN_FAN1_R

R815

1 2

330_0402_5%

C769

0.047U_0402_16V7K

FAN_SPEED1<32>

+3VS

H_IERR# ITP_TMS ITP_TDI H_PROCHOT# ITP_TCK ITP_TRST#

0.1U_0402_16V4Z

1 2

VDD

D+

ALERT/THERM2

D-

THERM

ADT7421ARMZ-REEL_MSOP8

SMSC@

C3 10U_0805_10V4ZC3 10U_0805_10V4Z

1 2

VEN

2 3 4

GND

VIN

GND GND

GND

VSET

G990P11U_SOP8

+3VS

R21

R21 10K_0402_5%

10K_0402_5%

C6 1000P_0402_50V7K

1000P_0402_50V7K

R12 56_0402_5%R12 56_0402_5%

1 2

R13 54.9_0402_1%R13 54.9_0402_1%

1 2

R14 54.9_0402_1%R14 54.9_0402_1%

1 2

R15 56_0402_5%R15 56_0402_5%

1 2

R16 54.9_0402_1%R16 54.9_0402_1%

1 2

R17 54.9_0402_1%R17 54.9_0402_1%

1 2

LM95245CIMMX NOPB MSOP 8P

NS@

SCLK

SDATA

R706 10K_0402_5%R706 10K_0402_5%

GND

+5VS

8 7 6 5

D1 BAS16_SOT23-3

BAS16_SOT23-3

C4 10U_0805_10V4ZC4 10U_0805_10V4Z

1000P_0402_50V7K

40mil

+VCC_FAN1

EC_SMB_CK2 <17,32> EC_SMB_DA2 <17,32>

1 2

BAS16_SOT23-3

1 2

ACES_85205-03001

JP7

1 2 3

4 5

+3VS

1 2 3

GND GND

CONN@

Security Classification

2007/08/18 2008/08/18

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2007/08/18 2008/08/18

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

JHXXX M/B LA-4241P Schematic

Date: Sheet

Date: Sheet of

Compal Electronics, Inc.

Penryn (1/3)

449Tuesday, June 03, 2008

0.4

hexainf@hotmail.com

H_D#[0..63]

JCPU1B

H_D#0

PAD

PAD PAD

PAD

H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15

H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31

GTL_REF0

TEST1 TEST2 TEST3 TEST4 TEST5 TEST6

D D

H_DSTBN#0<7> H_DSTBP#0<7> H_DINV#0<7>

C C

Trace Close CPU < 0.5'

Width=4 mil , Spacing: 15mil (55Ohm)

B B

R22

R22 1K_0402_1%

1K_0402_1%

R28

R28 2K_0402_1%

2K_0402_1%

+1.05VS

1 2

H_DSTBN#1<7> H_DSTBP#1<7> H_DINV#1<7>

R24 1K_0402_5%@R24 1K_0402_5%@ R26 1K_0402_5%@R26 1K_0402_5%@

0.1U_0402_16V4Z

1 2

12 12

T1 PAD

T1 PAD T2

T2 T3

CPU_BSEL0<16> CPU_BSEL1<16> CPU_BSEL2<16>

JCPU1B

E22

D[0]#

F24

D[1]#

E26

D[2]#

G22

D[3]#

F23

D[4]#

G25

D[5]#

E25

D[6]#

E23

D[7]#

K24

D[8]#

G24

D[9]#

J24

D[10]#

J23

D[11]#

H22

D[12]#

F26

D[13]#

K22

D[14]#

H23

D[15]#

J26

DSTBN[0]#

H26

DSTBP[0]#

H25

DINV[0]#

N22

D[16]#

K25

D[17]#

P26

D[18]#

R23

D[19]#

L23

D[20]#

M24

D[21]#

L22

D[22]#

M23

D[23]#

P25

D[24]#

P23

D[25]#

P22

D[26]#

T24

D[27]#

R24

D[28]#

L25

D[29]#

T25

D[30]#

N25

D[31]#

L26

DSTBN[1]#

M26

DSTBP[1]#

N24

DINV[1]#

AD26

GTLREF

C23

TEST1

D25

TEST2

C24

TEST3

AF26

TEST4

AF1

TEST5

A26

TEST6

B22

BSEL[0]

B23

BSEL[1]

C21

BSEL[2]

Merom Ball-out Rev 1a

CONN@

DATA GRP 0

DATA GRP 2DATA GRP 3

DSTBN[2]#

DSTBP[2]#

DINV[2]#

DATA GRP 1

DSTBN[3]#

DSTBP[3]#

DINV[3]# COMP[0]

MISC

COMP[1] COMP[2] COMP[3]

DPRSTP#

DPSLP#

PWRGOOD

D[32]# D[33]# D[34]# D[35]# D[36]# D[37]# D[38]# D[39]# D[40]# D[41]# D[42]# D[43]# D[44]# D[45]# D[46]# D[47]#

D[48]# D[49]# D[50]# D[51]# D[52]# D[53]# D[54]# D[55]# D[56]# D[57]# D[58]# D[59]# D[60]# D[61]# D[62]# D[63]#

DPWR#

SLP#

PSI#

layout note: Route TEST3 & TEST5 traces on ground referenced layer to the TPs

CPU_BSEL CPU_BSEL2 CPU_BSEL1

CPU_BSEL0

H_D#32

Y22

H_D#33

AB24

H_D#34

V24

H_D#35

V26

H_D#36

V23

H_D#37

T22

H_D#38

U25

H_D#39

U23

H_D#40

Y25

H_D#41

W22

H_D#42

Y23

H_D#43

W24

H_D#44

W25

H_D#45

AA23

H_D#46

AA24

H_D#47

AB25 Y26 AA26 U22

AE24 AD24 AA21 AB22 AB21 AC26 AD20 AE22 AF23 AC25 AE21 AD21 AC22 AD23 AF22 AC23 AE25 AF24 AC20

R26 U26 AA1 Y1

E5 B5 D24 D6 D7 AE6

H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63

COMP0 COMP1 COMP2 COMP3

H_PWRGOOD H_CPUSLP#

R23 27.4_0402_1%R23 27.4_0402_1% R25 54.9_0402_1%R25 54.9_0402_1% R27 27.4_0402_1%R27 27.4_0402_1% R29 54.9_0402_1%R29 54.9_0402_1%

H_DSTBN#2 <7> H_DSTBP#2 <7> H_DINV#2 <7>

H_DSTBN#3 <7> H_DSTBP#3 <7> H_DINV#3 <7>

1 2 1 2 1 2 1 2

H_DPRSTP# <8,21,48> H_DPSLP# <21> H_DPWR# <7> H_PWRGOOD <21> H_CPUSLP# <7> H_PSI# <48>

TRACE CLOSELY CPU < 0.5'

COMP0, COMP2 layout : Width 18mils and Space 25mils (27.4Ohms) COMP1, COMP3 layout : Width 4mils and Space 25mils (55Ohms)

H_PSI# H_DPRSTP#

H_D#[0..63] <7>

C739 100P_0402_50V8J@C739 100P_0402_50V8J@

1 2 1 2

C762 470P_0402_50V7KC762 470P_0402_50V7K

+CPU_CORE

JCPU1C

VCC[001]

VCC[002]

A10

VCC[003]

A12

VCC[004]

A13

VCC[005]

A15

VCC[006]

A17

VCC[007]

A18

VCC[008]

A20

VCC[009]

VCC[010]

VCC[011]

B10

VCC[012]

B12

VCC[013]

B14

VCC[014]

B15

VCC[015]

B17

VCC[016]

B18

VCC[017]

B20

VCC[018]

VCC[019]

C10

VCC[020]

C12

VCC[021]

C13

VCC[022]

C15

VCC[023]

C17

VCC[024]

C18

VCC[025]

VCC[026]

D10

VCC[027]

D12

VCC[028]

D14

VCC[029]

D15

VCC[030]

D17

VCC[031]

D18

VCC[032]

VCC[033]

VCC[034]

E10

VCC[035]

E12

VCC[036]

E13

VCC[037]

E15

VCC[038]

E17

VCC[039]

E18

VCC[040]

E20

VCC[041]

VCC[042]

VCC[043]

F10

VCC[044]

F12

VCC[045]

F14

VCC[046]

F15

VCC[047]

F17

VCC[048]

F18

VCC[049]

F20

VCC[050]

AA7

VCC[051]

AA9

VCC[052]

AA10

VCC[053]

AA12

VCC[054]

AA13

VCC[055]

AA15

VCC[056]

AA17

VCC[057]

AA18

VCC[058]

AA20

VCC[059]

AB9

VCC[060]

AC10

VCC[061]

AB10

VCC[062]

AB12

VCC[063]

AB14

VCC[064]

AB15

VCC[065]

AB17

VCC[066]

AB18

VCC[067]

Merom Ball-out Rev 1a

CONN@

VCC[068] VCC[069] VCC[070] VCC[071] VCC[072] VCC[073] VCC[074] VCC[075] VCC[076] VCC[077] VCC[078] VCC[079] VCC[080] VCC[081] VCC[082] VCC[083] VCC[084] VCC[085] VCC[086] VCC[087] VCC[088] VCC[089] VCC[090] VCC[091] VCC[092] VCC[093] VCC[094] VCC[095] VCC[096] VCC[097] VCC[098] VCC[099] VCC[100]

VCCP[01] VCCP[02] VCCP[03] VCCP[04] VCCP[05] VCCP[06] VCCP[07] VCCP[08] VCCP[09] VCCP[10] VCCP[11] VCCP[12] VCCP[13] VCCP[14] VCCP[15] VCCP[16]

VCCA[01] VCCA[02]

VID[0] VID[1] VID[2] VID[3] VID[4] VID[5] VID[6]

VCCSENSE

VSSSENSE

AB20 AB7 AC7 AC9 AC12 AC13 AC15 AC17 AC18 AD7 AD9 AD10 AD12 AD14 AD15 AD17 AD18 AE9 AE10 AE12 AE13 AE15 AE17 AE18 AE20 AF9 AF10 AF12 AF14 AF15 AF17 AF18 AF20

G21 V6 J6 K6 M6 J21 K21 M21 N21 N6 R21 R6 T21 T6 V21 W21

B26 C26

AD6 AF5 AE5 AF4 AE3 AF3 AE2

AF7

AE7

20mils

VCCSENSE

VSSSENSE

+CPU_CORE

CPU_VID0 <48> CPU_VID1 <48> CPU_VID2 <48> CPU_VID3 <48> CPU_VID4 <48> CPU_VID5 <48> CPU_VID6 <48>

1 2

R30 100_0402_1%R30 100_0402_1%

1 2

R31 100_0402_1%R31 100_0402_1%

330u ESR 9m ohm Package(L*W*H)7.3*4.3*1.8 Rating 2.5V

+1.05VS

C7 330U_D2E_2.5VM_R9

330U_D2E_2.5VM_R9

0.01U_0402_16V7K

+1.5VS

C10

C10 10U_0805_10V4Z

10U_0805_10V4Z

+CPU_CORE

VCCSENSE <48>

VSSSENSE <48>

166

200

266 0 0 0

A A

For 6 layer Z=27.4 ohm VCCSENSE, VSSSENSE/ 14mils (MS),

16mils (SL) width, 7mils space, 25mils space to other signals Mismatch =25mils.

Security Classification

2007/08/18 2008/08/18

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2007/08/18 2008/08/18

Compal Secret Data

Deciphered Date

Place PU and PD within 1 inch of CPU (CRB recommend) Route VCCSENSE and VSSSENSE traces at 27.4 Ohms with 50 mils spacing.

Length matching within 25 mils (Compal Common Design) Trace width/space/other is 20/7/25 Place these 2 resisters closk to CPU pins within 500 mils

Compal Electronics, Inc.

Title

Size Document Number Rev

JHXXX M/B LA-4241P Schematic

Date: Sheet

Compal Electronics, Inc.

Penryn (2/3)

549Wednesday, May 28, 2008

0.4

JCPU1D

VSS[001]

VSS[002]

A11

VSS[003]

A14

VSS[004]

A16

VSS[005]

A19

VSS[006]

D D

C C

B B

A A

A23

VSS[007]

AF2

VSS[008]

VSS[009]

VSS[010]

B11

VSS[011]

B13

VSS[012]

B16

VSS[013]

B19

VSS[014]

B21

VSS[015]

B24

VSS[016]

VSS[017]

VSS[018]

C11

VSS[019]

C14

VSS[020]

C16

VSS[021]

C19

VSS[022]

VSS[023]

C22

VSS[024]

C25

VSS[025]

VSS[026]

VSS[027]

VSS[028]

D11

VSS[029]

D13

VSS[030]

D16

VSS[031]

D19

VSS[032]

D23

VSS[033]

D26

VSS[034]

VSS[035]

VSS[036]

VSS[037]

E11

VSS[038]

E14

VSS[039]

E16

VSS[040]

E19

VSS[041]

E21

VSS[042]

E24

VSS[043]

VSS[044]

VSS[045]

F11

VSS[046]

F13

VSS[047]

F16

VSS[048]

F19

VSS[049]

VSS[050]

F22

VSS[051]

F25

VSS[052]

VSS[053]

VSS[054]

G23

VSS[055]

G26

VSS[056]

VSS[057]

VSS[058]

H21

VSS[059]

H24

VSS[060]

VSS[061]

VSS[062]

J22

VSS[063]

J25

VSS[064]

VSS[065]

VSS[066]

K23

VSS[067]

K26

VSS[068]

VSS[069]

VSS[070]

L21

VSS[071]

L24

VSS[072]

VSS[073]

VSS[074]

M22

VSS[075]

M25

VSS[076]

VSS[077]

VSS[078]

N23

VSS[079]

N26

VSS[080] VSS[081]P3VSS[162]

Merom Ball-out Rev 1a

CONN@

VSS[082] VSS[083] VSS[084] VSS[085] VSS[086] VSS[087] VSS[088] VSS[089] VSS[090] VSS[091] VSS[092] VSS[093] VSS[094] VSS[095] VSS[096] VSS[097] VSS[098] VSS[099] VSS[100] VSS[101] VSS[102] VSS[103] VSS[104] VSS[105] VSS[106] VSS[107] VSS[108] VSS[109] VSS[110] VSS[111] VSS[112] VSS[113] VSS[114] VSS[115] VSS[116] VSS[117] VSS[118] VSS[119] VSS[120] VSS[121] VSS[122] VSS[123] VSS[124] VSS[125] VSS[126] VSS[127] VSS[128] VSS[129] VSS[130] VSS[131] VSS[132] VSS[133] VSS[134] VSS[135] VSS[136] VSS[137] VSS[138] VSS[139] VSS[140] VSS[141] VSS[142] VSS[143] VSS[144] VSS[145] VSS[146] VSS[147] VSS[148] VSS[149] VSS[150] VSS[151] VSS[152] VSS[153] VSS[154] VSS[155] VSS[156] VSS[157] VSS[158] VSS[159] VSS[160] VSS[161]

VSS[163]

P6 P21 P24 R2 R5 R22 R25 T1 T4 T23 T26 U3 U6 U21 U24 V2 V5 V22 V25 W1 W4 W23 W26 Y3 Y6 Y21 Y24 AA2 AA5 AA8 AA11 AA14 AA16 AA19 AA22 AA25 AB1 AB4 AB8 AB11 AB13 AB16 AB19 AB23 AB26 AC3 AC6 AC8 AC11 AC14 AC16 AC19 AC21 AC24 AD2 AD5 AD8 AD11 AD13 AD16 AD19 AD22 AD25 AE1 AE4 AE8 AE11 AE14 AE16 AE19 AE23 AE26 A2 AF6 AF8 AF11 AF13 AF16 AF19 AF21 A25 AF25

+CPU_CORE

C11

C11 330U_D2E_2.5VM_R9

330U_D2E_2.5VM_R9

330u ESR 9m ohm Package(L*W*H)7.3*4.3*1.8 Rating 2.5V

2 x 330uF(9mOhm/3)

C12

C13

+CPU_CORE

330U_D2E_2.5VM_R9@

C14

330U_D2E_2.5VM_R9

2 x 330uF(9mOhm/3)

C15

330U_D2E_2.5VM_R9

C16

330U_D2E_2.5VM_R9

South Side Secondary North Side Secondary

+CPU_CORE

C17

10U_0805_6.3V6M

C18

10U_0805_6.3V6M

C19

10U_0805_6.3V6M

C20

10U_0805_6.3V6M

C21

10U_0805_6.3V6M

C22

10U_0805_6.3V6M

C23

10U_0805_6.3V6M

C24

10U_0805_6.3V6M

(Place these capacitors on South side,Secondary Layer)

+CPU_CORE

C25

10U_0805_6.3V6M

C26

10U_0805_6.3V6M

C27

10U_0805_6.3V6M

C28

10U_0805_6.3V6M

C29

10U_0805_6.3V6M

C30

10U_0805_6.3V6M

C31

10U_0805_6.3V6M

C32

10U_0805_6.3V6M

(Place these capacitors on North side,Secondary Layer)

+CPU_CORE

C33

10U_0805_6.3V6M

C34

10U_0805_6.3V6M

C35

10U_0805_6.3V6M

C36

10U_0805_6.3V6M

C37

10U_0805_6.3V6M

C38

10U_0805_6.3V6M

C39

10U_0805_6.3V6M

C40

10U_0805_6.3V6M

(Place these capacitors on South side,Primary Layer)

+CPU_CORE

C41

10U_0805_6.3V6M

C42

10U_0805_6.3V6M

C43

10U_0805_6.3V6M

C44

10U_0805_6.3V6M

C45

10U_0805_6.3V6M

C46

10U_0805_6.3V6M

C47

10U_0805_6.3V6M

C48

10U_0805_6.3V6M

(Place these capacitors on North side,Primary Layer)

+CPU-CORE Decoupling SPCAP,Polymer

MLCC 0805 X5R

+1.05VS

C49

0.1U_0402_16V4Z

C,uF ESL,nH

ESR, mohm

6X330uF 9m ohm/6 1.8nH/6 32X22uF

3m ohm/32 0.6nH/32

32X10uF 3m ohm/32 0.6nH/32

C50

0.1U_0402_16V4Z

C51

0.1U_0402_16V4Z

C52

0.1U_0402_16V4Z

C53

0.1U_0402_16V4Z

C54

(Place these capacitors inside socket cavity in 2 row on North side Secondary)

Security Classification

2007/08/18 2008/8/18

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2007/08/18 2008/8/18

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

Penryn (3/3)

JHXXX M/B LA-4241P Schematic

649Friday, April 11, 2008

0.4

hexainf@hotmail.com

Change U3 from SA00001P900 to SA00001P930

3/4 Change U3 from SA00001P930 to SA00002JT10 (B0 to B2)

U3A

H_D#[0..63]<5>

D D

+1.05VS

C C

R32

R32 221_0402_1%

221_0402_1%

R33

R33 100_0402_1%

100_0402_1%

1 2

H_SWING

width=10mil

C55

0.1U_0402_16V4Z

Near C5 pin

H_RCOMP

R34

24.9_0402_1%

B B

Layout Note: H_RCOMP / H_VREF / H_SWING

trace width and spacing is 10/20

width / space =10mil / 20mil

+1.05VS

R35

R35 1K_0402_1%

1K_0402_1%

1 2 12

R36

R36 2K_0402_1%

2K_0402_1%

C56

0.1U_0402_16V4Z

H_RESET#<4> H_CPUSLP#<5>

width:spacing=10mil:20mil (<0.5")

H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31 H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63

H_SWING H_RCOMP

H_RESET# H_CPUSLP#

H_VREF

U3A

H_D#_0

H_D#_1

H_D#_2

H_D#_3

H_D#_4

H_D#_5

H_D#_6

H_D#_7

H_D#_8

H_D#_9

H_D#_10

M11

H_D#_11

H_D#_12

H_D#_13

N12

H_D#_14

H_D#_15

H_D#_16

H_D#_17

H_D#_18

H_D#_19

H_D#_20

H_D#_21

H_D#_22

H_D#_23

H_D#_24

H_D#_25

H_D#_26

P13

H_D#_27

H_D#_28

H_D#_29

N10

H_D#_30

H_D#_31

H_D#_32

AD14

H_D#_33

H_D#_34

Y10

H_D#_35

Y12

H_D#_36

Y14

H_D#_37

H_D#_38

H_D#_39

AA8

H_D#_40

H_D#_41

AA13

H_D#_42

AA9

H_D#_43

AA11

H_D#_44

AD11

H_D#_45

AD10

H_D#_46

AD13

H_D#_47

AE12

H_D#_48

AE9

H_D#_49

AA2

H_D#_50

AD8

H_D#_51

AA3

H_D#_52

AD3

H_D#_53

AD7

H_D#_54

AE14

H_D#_55

AF3

H_D#_56

AC1

H_D#_57

AE3

H_D#_58

AC3

H_D#_59

AE11

H_D#_60

AE8

H_D#_61

AG2

H_D#_62

AD6

H_D#_63

H_SWING

H_RCOMP

C12

H_CPURST#

E11

H_CPUSLP#

A11

H_AVREF

B11

H_DVREF

CANTIGA ES_FCBGA1329

GM@

H_ADSTB#_0 H_ADSTB#_1

H_BREQ#

H_DEFER#

HOST

H_DBSY#

HPLL_CLK

HPLL_CLK#

H_DPWR#

H_DRDY#

H_LOCK# H_TRDY#

H_DINV#_0 H_DINV#_1 H_DINV#_2 H_DINV#_3

H_DSTBN#_0 H_DSTBN#_1 H_DSTBN#_2 H_DSTBN#_3

H_DSTBP#_0 H_DSTBP#_1 H_DSTBP#_2 H_DSTBP#_3

H_REQ#_0 H_REQ#_1 H_REQ#_2 H_REQ#_3 H_REQ#_4

H_A#_3 H_A#_4 H_A#_5 H_A#_6 H_A#_7 H_A#_8

H_A#_9 H_A#_10 H_A#_11 H_A#_12 H_A#_13 H_A#_14 H_A#_15 H_A#_16 H_A#_17 H_A#_18 H_A#_19 H_A#_20 H_A#_21 H_A#_22 H_A#_23 H_A#_24 H_A#_25 H_A#_26 H_A#_27 H_A#_28 H_A#_29 H_A#_30 H_A#_31 H_A#_32 H_A#_33 H_A#_34 H_A#_35

H_ADS#

H_BNR#

H_BPRI#

H_HIT#

H_HITM#

H_RS#_0 H_RS#_1 H_RS#_2

A14 C15 F16 H13 C18 M16 J13 P16 R16 N17 M13 E17 P17 F17 G20 B19 J16 E20 H16 J20 L17 A17 B17 L16 C21 J17 H20 B18 K17 B20 F21 K21 L20

H12 B16 G17 A9 F11 G12 E9 B10 AH7 AH6 J11 F9 H9 E12 H11 C9

J8 L3 Y13 Y1

L10 M7 AA5 AE6

L9 M8 AA6 AE5

B15 K13 F13 B13 B14

B6 F12 C8

H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16 H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 H_A#32 H_A#33 H_A#34 H_A#35

H_ADS# H_ADSTB#0 H_ADSTB#1 H_BNR# H_BPRI# H_BR0# H_DEFER# H_DBSY# CLK_MCH_BCLK CLK_MCH_BCLK# H_DPWR# H_DRDY# H_HIT# H_HITM# H_LOCK# H_TRDY#

H_DINV#0 H_DINV#1 H_DINV#2 H_DINV#3

H_DSTBN#0 H_DSTBN#1 H_DSTBN#2 H_DSTBN#3

H_DSTBP#0 H_DSTBP#1 H_DSTBP#2 H_DSTBP#3

H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4

H_RS#0 H_RS#1 H_RS#2

H_A#[3..35] <4>

H_ADS# <4> H_ADSTB#0 <4> H_ADSTB#1 <4> H_BNR# <4> H_BPRI# <4> H_BR0# <4> H_DEFER# <4> H_DBSY# <4> CLK_MCH_BCLK <16> CLK_MCH_BCLK# <16> H_DPWR# <5> H_DRDY# <4> H_HIT# <4> H_HITM# <4> H_LOCK# <4> H_TRDY# <4>

H_DINV#0 <5> H_DINV#1 <5> H_DINV#2 <5> H_DINV#3 <5>

H_DSTBN#0 <5> H_DSTBN#1 <5> H_DSTBN#2 <5> H_DSTBN#3 <5>

H_DSTBP#0 <5> H_DSTBP#1 <5> H_DSTBP#2 <5> H_DSTBP#3 <5>

H_REQ#[0..4] <4>

H_RS#[0..2] <4>

965PM

PM@

3/4 Change U3 PM@ from SA00001ZO30 to SA00002JJ00 (B0 to B2)

A A

Security Classification

2007/08/18 2008/8/18

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2007/08/18 2008/8/18

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

Cantiga (1/7)-GTL

JHXXX M/B LA-4241P Schematic

749Tuesday, June 03, 2008

0.4

+1.8V

R38

R38 1K_0402_1%

1K_0402_1%

D D

C57

VGATE<16,22,48> ICH_PWROK<22,32>

C57

2.2U_0603_6.3V6K

C60

2.2U_0603_6.3V6K

PLT_RST_BUF#<17,20,26,28,30,40> H_THERMTRIP#<4,21> PM_DPRSLPVR_D<22,48>

+1.05VS

R76

54.9_0402_1%

1 2

330_0402_5%

PM_BMBUSY#<22> H_DPRSTP#<5,21,48> PM_EXTTS#0<14> PM_EXTTS#1<15>

R81

R43

3.01K_0402_1%

R39

R39 1K_0402_1%

1K_0402_1%

C C

B B

A A

MCH_TSATN#

SM_RCOMP_VOHSM_RCOMP_VOH

C59

0.01U_0402_16V7K

SM_RCOMP_VOL

C58

0.01U_0402_16V7K

MCH_CLKSEL0<16> MCH_CLKSEL1<16> MCH_CLKSEL2<16>

Use VGATE for GMCH_PWROK

VGATE

1 2

R52 0_0402_5%@R52 0_0402_5%@

ICH_PWROK

1 2

R53 0_0402_5%R53 0_0402_5%

+3VS +3VS

R71

R71 1K_0402_5%

1K_0402_5%

MMBT3904_SOT23-3

3 1

GMCH_PWROK

R57 0_0402_5%R57 0_0402_5%

1 2

R58 0_0402_5%R58 0_0402_5%

1 2

R61 100_0402_5%R61 100_0402_5% R63 0_0402_5%R63 0_0402_5%

1 2

R64 0_0402_5%R64 0_0402_5%

1 2

R72

R72 1K_0402_5%

1K_0402_5%

MMBT3904_SOT23-3

3 1

MCH_CLKSEL0 MCH_CLKSEL1 MCH_CLKSEL2

MCH_CFG_5 MCH_CFG_6 MCH_CFG_7

MCH_CFG_9 MCH_CFG_10

MCH_CFG_12 MCH_CFG_13

MCH_CFG_16

MCH_CFG_19 MCH_CFG_20

PM_BMBUSY#_R PM_DPRSTP#_R PM_EXTTS#0 PM_EXTTS#1 GMCH_PWROK MCH_RSTIN# THERMTRIP#_R DPRSLPVR_R

MCH_TSATN#_EC <32>

PM_DPRSLPVR_D H_DPRSTP#

U3B

M36

RSVD1

N36

RSVD2

R33

RSVD3

T33

RSVD4

AH9

RSVD5

AH10

RSVD6

AH12

RSVD7

AH13

RSVD8

K12

RSVD9

AL34

RSVD10

AK34

RSVD11

AN35

RSVD12

AM35

RSVD13

T24

RSVD14

B31

RSVD15

RSVD16

RSVD17

AY21

RSVD20

BG23

RSVD22

BF23

RSVD23

BH18

RSVD24

BF18

RSVD25

T25

CFG_0

R25

CFG_1

P25

CFG_2

P20

CFG_3

P24

CFG_4

C25

CFG_5

N24

CFG_6

M24

CFG_7

E21

CFG_8

C23

CFG_9

C24

CFG_10

N21

CFG_11

P21

CFG_12

T21

CFG_13

R20

CFG_14

M20

CFG_15

L21

CFG_16

H21

CFG_17

P29

CFG_18

R28

CFG_19

T28

CFG_20

R29

PM_SYNC#

PM_DPRSTP#

N33

PM_EXT_TS#_0

P32

PM_EXT_TS#_1

AT40

PWROK

AT11

RSTIN#

T20

THERMTRIP#

R32

DPRSLPVR

BG48

NC_1

BF48

NC_2

BD48

NC_3

BC48

NC_4

BH47

NC_5

BG47

NC_6

BE47

NC_7

BH46

NC_8

BF46

NC_9

BG45

NC_10

BH44

NC_11

BH43

NC_12

BH6

NC_13

BH5

NC_14

BG4

NC_15

BH3

NC_16

BF3

NC_17

BH2

NC_18

BG2

NC_19

BE2

NC_20

BG1

NC_21

BF1

NC_22

BD1

NC_23

BC1

NC_24

NC_25

A47

NC_26

CANTIGA ES_FCBGA1329

GM@

RSVD CFG PM NC

DDR CLK/ CONTROL/ COMPENSATIONHDA

CLKDMIGRAPHICS VIDMEMISC

1 2

C760 470P_0402_50V7KC760 470P_0402_50V7K

1 2

C761 470P_0402_50V7KC761 470P_0402_50V7K

SA_CK_0 SA_CK_1 SB_CK_0 SB_CK_1

SA_CK#_0 SA_CK#_1 SB_CK#_0 SB_CK#_1

SA_CKE_0 SA_CKE_1 SB_CKE_0 SB_CKE_1

SA_CS#_0 SA_CS#_1 SB_CS#_0 SB_CS#_1

SA_ODT_0 SA_ODT_1

SB_ODT_O

SB_ODT_1

SM_RCOMP

SM_RCOMP#

SM_RCOMP_VOH SM_RCOMP_VOL

SM_VREF

SM_PWROK

SM_REXT

SM_DRAMRST#

DPLL_REF_CLK

DPLL_REF_CLK#

DPLL_REF_SSCLK

DPLL_REF_SSCLK#

PEG_CLK

PEG_CLK#

DMI_RXN_0 DMI_RXN_1 DMI_RXN_2 DMI_RXN_3

DMI_RXP_0 DMI_RXP_1 DMI_RXP_2 DMI_RXP_3

DMI_TXN_0 DMI_TXN_1 DMI_TXN_2 DMI_TXN_3

DMI_TXP_0 DMI_TXP_1 DMI_TXP_2 DMI_TXP_3

GFX_VID_0 GFX_VID_1 GFX_VID_2 GFX_VID_3 GFX_VID_4

GFX_VR_EN

CL_CLK

CL_DATA

CL_PWROK

CL_RST# CL_VREF

DDPC_CTRLCLK

DDPC_CTRLDATA

SDVO_CTRLCLK

SDVO_CTRLDATA

CLKREQ#

ICH_SYNC#

TSATN#

HDA_BCLK HDA_RST#

HDA_SDI

HDA_SDO

HDA_SYNC

AP24 AT21 AV24 AU20

AR24 AR21 AU24 AV20

BC28 AY28 AY36 BB36

BA17 AY16 AV16 AR13

BD17 AY17 BF15 AY13

BG22 BH21

BF28 BH28

AV42 AR36 BF17 BC36

B38 A38 E41 F41

F43 E43

AE41 AE37 AE47 AH39

AE40 AE38 AE48 AH40

AE35 AE43 AE46 AH42

AD35 AE44 AF46 AH43

B33 B32 G33 F33 E33

C34

AH37 AH36 AN36 AJ35 AH34

N28 M28 G36 E36 K36 H36

B12

B28 B30 B29 C29 A28

SMRCOMP SMRCOMP#

SM_RCOMP_VOH SM_RCOMP_VOL

SM_PWROK SM_REXT

CLK_DREF_96M CLK_DREF_96M# CLK_DREF_SSC CLK_DREF_SSC#

CLK_MCH_3GPLL CLK_MCH_3GPLL#

DMI_ITX_MRX_N0 DMI_ITX_MRX_N1 DMI_ITX_MRX_N2 DMI_ITX_MRX_N3

DMI_ITX_MRX_P0 DMI_ITX_MRX_P1 DMI_ITX_MRX_P2 DMI_ITX_MRX_P3

DMI_MTX_IRX_N0 DMI_MTX_IRX_N1 DMI_MTX_IRX_N2 DMI_MTX_IRX_N3

DMI_MTX_IRX_P0 DMI_MTX_IRX_P1 DMI_MTX_IRX_P2 DMI_MTX_IRX_P3

ICH_PWROK CL_VREF

HDMICLK_NB HDMIDAT_NB MCH_CLKREQ#

MCH_TSATN#

GMCH_HDA_BITCLK GMCH_HDA_RST# MCH_HDA_SDIN GMCH_HDA_SDOUT GMCH_HDA_SYNC

R48 10K_0402_1%R48 10K_0402_1% R50 499_0402_1%R50 499_0402_1%

DDRA_CLK0 <14> DDRA_CLK1 <14> DDRB_CLK0 <15> DDRB_CLK1 <15>

DDRA_CLK0# <14> DDRA_CLK1# <14> DDRB_CLK0# <15> DDRB_CLK1# <15>

DDRA_CKE0 <14> DDRA_CKE1 <14> DDRB_CKE0 <15> DDRB_CKE1 <15>

DDRA_SCS0# <14> DDRA_SCS1# <14> DDRB_SCS0# <15> DDRB_SCS1# <15>

DDRA_ODT0 <14> DDRA_ODT1 <14> DDRB_ODT0 <15> DDRB_ODT1 <15>

SM_VREF

1 2 1 2

CLK_DREF_96M <16>

CLK_DREF_96M# <16>

CLK_DREF_SSC <16>

CLK_DREF_SSC# <16>

CLK_MCH_3GPLL <16>

CLK_MCH_3GPLL# <16>

DMI_ITX_MRX_N0 <22>

DMI_ITX_MRX_N1 <22>

DMI_ITX_MRX_N2 <22>

DMI_ITX_MRX_N3 <22>

DMI_ITX_MRX_P0 <22>

DMI_ITX_MRX_P1 <22>

DMI_ITX_MRX_P2 <22>

DMI_ITX_MRX_P3 <22>

DMI_MTX_IRX_N0 <22>

DMI_MTX_IRX_N1 <22>

DMI_MTX_IRX_N2 <22>

DMI_MTX_IRX_N3 <22>

DMI_MTX_IRX_P0 <22>

DMI_MTX_IRX_P1 <22>

DMI_MTX_IRX_P2 <22>

DMI_MTX_IRX_P3 <22>

CL_CLK0 <22>

CL_DATA0 <22>

CL_RST#0 <22>

HDMICLK_NB <25>

HDMIDAT_NB <25>

MCH_CLKREQ# <16>

MCH_ICH_SYNC# <22>

R78 33_0402_5%GM@R78 33_0402_5%GM@

1 2

SM_DRAMRST# would be needed for DDR3 only

For Cantiga 80 Ohm

R45 80.6_0402_1%R45 80.6_0402_1% R46 80.6_0402_1%R46 80.6_0402_1%

20mil

0.1U_0402_16V4Z

SM_PWROK: Pull L for DDR2 Driven by platform for DDR3

1 2

C61

R51

R51 1K_0402_1%

1K_0402_1%

1 2

Layout Note: SM_VREF trace width and spacing is 20/20.

C62

0.1U_0402_16V4Z

+1.8V

R49

+1.8V

1K_0402_1%

(Default)

10/22 intel recommend 2.21K iTPM spec use 10K

+1.05VS

R66

1K_0402_1%

1 2

R68

R68 511_0402_1%

511_0402_1%

1 2

GMCH_HDA_BITCLK <10> GMCH_HDA_RST# <10> GMCH_HDA_SDIN2 <10> GMCH_HDA_SDOUT <10> GMCH_HDA_SYNC <10>

CFG[17:3] have internal pull up CFG[19:18] have internal pull down

When ICH9M VCCHDA and VCCSUSHDA tie to 3V, don't stuff these resisters (follow CRB)

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2007/08/18 2008/8/18

Compal Secret Data

Deciphered Date

CFG[2:0] CFG5 CFG6 CFG7

CFG9 CFG10

CFG[13:12]

CFG16 CFG19 CFG20

(PCIE/SDVO select)

SDVO_CTRLDATA

Add follow CRB

CLK_DREF_96M# CLK_DREF_SSC# CLK_DREF_96M CLK_DREF_SSC

011 = 667MT/s FSB 010 = 800MT/s FSB

0 = DMI x 2 1 = DMI x 4

0 = The ITPM Host Interface is enabled 1 = The ITPM Host Interface is disabled

0 = AMT Firmware will use TLS cipher suite with no confidentiality 1 = AMT Firmware will use TLS cipher suite with confidentiality 0 = Lane Reversal Enable

1 = Normal Operation 0 = PCIE Loopback Enable

1 = Disable 00 = Reserved

01 = XOR Mode Enabled 10 = All Z Mode Enabled 11 = Normal Operation

0 = Dynamic ODT Disabled 1 = Dynamic ODT Enabled

0 = Normal Operation 1 = DMI Lane Reversal Enable

0 = Only PCIE or SDVO is operational.

(Default)

1 = PCIE/SDVO are operating simu. 0 = No SDVO Device Present 1 = SDVO Device Present

MCH_CFG_5 MCH_CFG_9 MCH_CFG_12 MCH_CFG_13 MCH_CFG_16 MCH_CFG_10 MCH_CFG_6 MCH_CFG_7

1 2

R37 0_0402_5%PM@R37 0_0402_5%PM@

1 2

R40 0_0402_5%PM@R40 0_0402_5%PM@

1 2

R41 0_0402_5%PM@R41 0_0402_5%PM@

1 2

R42 0_0402_5%PM@R42 0_0402_5%PM@

(Default)

1 2

R54 2.21K_0402_1%@R54 2.21K_0402_1%@

1 2

R55 2.21K_0402_1%@R55 2.21K_0402_1%@

1 2

R56 2.21K_0402_1%@R56 2.21K_0402_1%@

1 2

R59 2.21K_0402_1%@R59 2.21K_0402_1%@

1 2

R60 2.21K_0402_1%@R60 2.21K_0402_1%@

1 2

R62 2.21K_0402_1%@R62 2.21K_0402_1%@

1 2

R65 2.21K_0402_1%@R65 2.21K_0402_1%@

1 2

R67 2.21K_0402_1%@R67 2.21K_0402_1%@

Change R from 4.02K to 2.21K following CRB

MCH_CFG_19 MCH_CFG_20

PM_EXTTS#0 PM_EXTTS#1

HDMICLK_NB HDMIDAT_NB

Title

Size Document Number Rev

Custom

Date: Sheet

R69 4.02K_0402_1%@R69 4.02K_0402_1%@ R70 4.02K_0402_1%@R70 4.02K_0402_1%@

R73 10K_0402_5%R73 10K_0402_5% R74 10K_0402_5%R74 10K_0402_5%

1 2

R80 0_0402_5%@R80 0_0402_5%@

1 2

R83 0_0402_5%@R83 0_0402_5%@

Compal Electronics, Inc.

Cantiga (2/7)-DMI/DDR

JHXXX M/B LA-4241P Schematic

Strap Pin Table

000 = 1066MT/s FSB

(Default)

+3VS

849Tuesday, June 03, 2008

0.4

hexainf@hotmail.com

DDRB_SDQ[0..63] DDRB_SDM[0..7] DDRB_SMA[0..14]

DDRA_SBS0 <14> DDRA_SBS1 <14> DDRA_SBS2 <14>

DDRA_SRAS# <14> DDRA_SCAS# <14> DDRA_SWE# <14>

DDRA_SDQS0 <14> DDRA_SDQS1 <14> DDRA_SDQS2 <14> DDRA_SDQS3 <14> DDRA_SDQS4 <14> DDRA_SDQS5 <14> DDRA_SDQS6 <14> DDRA_SDQS7 <14>

DDRA_SDQS0# <14> DDRA_SDQS1# <14> DDRA_SDQS2# <14> DDRA_SDQS3# <14> DDRA_SDQS4# <14> DDRA_SDQS5# <14> DDRA_SDQS6# <14> DDRA_SDQS7# <14>

DDRB_SDQ0 DDRB_SDQ1 DDRB_SDQ2 DDRB_SDQ3 DDRB_SDQ4 DDRB_SDQ5 DDRB_SDQ6 DDRB_SDQ7 DDRB_SDQ8 DDRB_SDQ9 DDRB_SDQ10 DDRB_SDQ11 DDRB_SDQ12 DDRB_SDQ13 DDRB_SDQ14 DDRB_SDQ15 DDRB_SDQ16 DDRB_SDQ17 DDRB_SDQ18 DDRB_SDQ19 DDRB_SDQ20 DDRB_SDQ21 DDRB_SDQ22 DDRB_SDQ23 DDRB_SDQ24 DDRB_SDQ25 DDRB_SDQ26 DDRB_SDQ27 DDRB_SDQ28 DDRB_SDQ29 DDRB_SDQ30 DDRB_SDQ31 DDRB_SDQ32 DDRB_SDQ33 DDRB_SDQ34 DDRB_SDQ35 DDRB_SDQ36 DDRB_SDQ37 DDRB_SDQ38 DDRB_SDQ39 DDRB_SDQ40 DDRB_SDQ41 DDRB_SDQ42 DDRB_SDQ43 DDRB_SDQ44 DDRB_SDQ45 DDRB_SDQ46 DDRB_SDQ47 DDRB_SDQ48 DDRB_SDQ49 DDRB_SDQ50 DDRB_SDQ51 DDRB_SDQ52 DDRB_SDQ53 DDRB_SDQ54 DDRB_SDQ55 DDRB_SDQ56 DDRB_SDQ57 DDRB_SDQ58 DDRB_SDQ59 DDRB_SDQ60 DDRB_SDQ61 DDRB_SDQ62 DDRB_SDQ63

AK47 AH46 AP47 AP46

AJ46 AJ48

AM48

AP48 AU47 AU46 BA48 AY48 AT47 AR47 BA47 BC47 BC46 BC44

BG43

BF43 BE45 BC41 BF40 BF41

BG38

BF38 BH35

BG35

BH40 BG39 BG34

BH34

BH14 BG12

BH11

BG8 BH12 BF11

BG7

BC5

BC6

AY3 AY1 BF6 BF5 BA1

BD3

AV2 AU3 AR3 AN2

AY2

AV1

AP3 AR1

AL1

AL2

AJ1 AH1 AM2 AM3 AH3

AJ3

BF8

U3E

SB_DQ_0 SB_DQ_1 SB_DQ_2 SB_DQ_3 SB_DQ_4 SB_DQ_5 SB_DQ_6 SB_DQ_7 SB_DQ_8 SB_DQ_9 SB_DQ_10 SB_DQ_11 SB_DQ_12 SB_DQ_13 SB_DQ_14 SB_DQ_15 SB_DQ_16 SB_DQ_17 SB_DQ_18 SB_DQ_19 SB_DQ_20 SB_DQ_21 SB_DQ_22 SB_DQ_23 SB_DQ_24 SB_DQ_25 SB_DQ_26 SB_DQ_27 SB_DQ_28 SB_DQ_29 SB_DQ_30 SB_DQ_31 SB_DQ_32 SB_DQ_33 SB_DQ_34 SB_DQ_35 SB_DQ_36 SB_DQ_37 SB_DQ_38 SB_DQ_39 SB_DQ_40 SB_DQ_41 SB_DQ_42 SB_DQ_43 SB_DQ_44 SB_DQ_45 SB_DQ_46 SB_DQ_47 SB_DQ_48 SB_DQ_49 SB_DQ_50 SB_DQ_51 SB_DQ_52 SB_DQ_53 SB_DQ_54 SB_DQ_55 SB_DQ_56 SB_DQ_57 SB_DQ_58 SB_DQ_59 SB_DQ_60 SB_DQ_61 SB_DQ_62 SB_DQ_63

BC16

SB_BS_0

BB17

SB_BS_1

BB33

SB_BS_2

AU17

SB_RAS#

BG16

SB_CAS#

BF14

SB_WE#

DDRB_SDM0

AM47

SB_DM_0 SB_DM_1 SB_DM_2 SB_DM_3 SB_DM_4 SB_DM_5 SB_DM_6 SB_DM_7

SB_DQS_0 SB_DQS_1 SB_DQS_2 SB_DQS_3 SB_DQS_4 SB_DQS_5 SB_DQS_6 SB_DQS_7

SB_DQS#_0 SB_DQS#_1 SB_DQS#_2 SB_DQS#_3 SB_DQS#_4 SB_DQS#_5 SB_DQS#_6 SB_DQS#_7

SB_MA_0 SB_MA_1 SB_MA_2

DDR SYSTEM MEMORY B

SB_MA_3 SB_MA_4 SB_MA_5 SB_MA_6 SB_MA_7 SB_MA_8

SB_MA_9 SB_MA_10 SB_MA_11 SB_MA_12 SB_MA_13 SB_MA_14

CANTIGA ES_FCBGA1329GM@

AY47 BD40 BF35 BG11 BA3 AP1 AK2

AL47 AV48 BG41 BG37 BH9 BB2 AU1 AN6

AL46 AV47 BH41 BH37 BG9 BC2 AT2 AN5

AV17 BA25 BC25 AU25 AW25 BB28 AU28 AW28 AT33 BD33 BB16 AW33 AY33 BH15 AU33

DDRB_SDM1 DDRB_SDM2 DDRB_SDM3 DDRB_SDM4 DDRB_SDM5 DDRB_SDM6 DDRB_SDM7

DDRB_SDQS0 DDRB_SDQS1 DDRB_SDQS2 DDRB_SDQS3 DDRB_SDQS4 DDRB_SDQS5 DDRB_SDQS6 DDRB_SDQS7

DDRB_SDQS0# DDRB_SDQS1# DDRB_SDQS2# DDRB_SDQS3# DDRB_SDQS4# DDRB_SDQS5# DDRB_SDQS6# DDRB_SDQS7#

DDRB_SMA0 DDRB_SMA1 DDRB_SMA2 DDRB_SMA3 DDRB_SMA4 DDRB_SMA5 DDRB_SMA6 DDRB_SMA7 DDRB_SMA8 DDRB_SMA9 DDRB_SMA10 DDRB_SMA11 DDRB_SMA12 DDRB_SMA13 DDRB_SMA14

DDRB_SBS0 <15> DDRB_SBS1 <15> DDRB_SBS2 <15>

DDRB_SRAS# <15> DDRB_SCAS# <15> DDRB_SWE# <15>

DDRB_SDQS0 <15> DDRB_SDQS1 <15> DDRB_SDQS2 <15> DDRB_SDQS3 <15> DDRB_SDQS4 <15> DDRB_SDQS5 <15> DDRB_SDQS6 <15> DDRB_SDQS7 <15>

DDRB_SDQS0# <15> DDRB_SDQS1# <15> DDRB_SDQS2# <15> DDRB_SDQS3# <15> DDRB_SDQS4# <15> DDRB_SDQS5# <15> DDRB_SDQS6# <15> DDRB_SDQS7# <15>

U3D

SA_DQ_0 SA_DQ_1 SA_DQ_2 SA_DQ_3 SA_DQ_4 SA_DQ_5 SA_DQ_6 SA_DQ_7 SA_DQ_8 SA_DQ_9 SA_DQ_10 SA_DQ_11 SA_DQ_12 SA_DQ_13 SA_DQ_14 SA_DQ_15 SA_DQ_16 SA_DQ_17 SA_DQ_18 SA_DQ_19 SA_DQ_20 SA_DQ_21 SA_DQ_22 SA_DQ_23 SA_DQ_24 SA_DQ_25 SA_DQ_26 SA_DQ_27 SA_DQ_28 SA_DQ_29 SA_DQ_30 SA_DQ_31 SA_DQ_32 SA_DQ_33 SA_DQ_34 SA_DQ_35 SA_DQ_36 SA_DQ_37 SA_DQ_38 SA_DQ_39 SA_DQ_40 SA_DQ_41 SA_DQ_42 SA_DQ_43 SA_DQ_44 SA_DQ_45 SA_DQ_46 SA_DQ_47 SA_DQ_48 SA_DQ_49 SA_DQ_50 SA_DQ_51 SA_DQ_52 SA_DQ_53 SA_DQ_54 SA_DQ_55 SA_DQ_56 SA_DQ_57 SA_DQ_58 SA_DQ_59 SA_DQ_60 SA_DQ_61 SA_DQ_62 SA_DQ_63

DDRA_SDQ[0..63] DDRA_SDM[0..7] DDRA_SMA[0..14]

DDRB_SDQ[0..63]<15> DDRB_SDM[0..7]<15> DDRB_SMA[0..14]<15>

BD21

SA_BS_0

BG18

SA_BS_1

AT25

SA_BS_2

BB20

SA_RAS#

BD20

SA_CAS#

AY20

SA_WE#

DDRA_SDM0

AM37

SA_DM_0 SA_DM_1 SA_DM_2 SA_DM_3 SA_DM_4 SA_DM_5 SA_DM_6 SA_DM_7

SA_DQS_0 SA_DQS_1 SA_DQS_2 SA_DQS_3 SA_DQS_4 SA_DQS_5 SA_DQS_6 SA_DQS_7

SA_DQS#_0 SA_DQS#_1 SA_DQS#_2 SA_DQS#_3 SA_DQS#_4 SA_DQS#_5 SA_DQS#_6 SA_DQS#_7

SA_MA_0 SA_MA_1 SA_MA_2 SA_MA_3

DDR SYSTEM MEMORY A

SA_MA_4 SA_MA_5 SA_MA_6 SA_MA_7 SA_MA_8

SA_MA_9 SA_MA_10 SA_MA_11 SA_MA_12 SA_MA_13 SA_MA_14

CANTIGA ES_FCBGA1329GM@

AT41 AY41 AU39 BB12 AY6 AT7 AJ5

AJ44 AT44 BA43 BC37 AW12 BC8 AU8 AM7

AJ43 AT43 BA44 BD37 AY12 BD8 AU9 AM8

BA21 BC24 BG24 BH24 BG25 BA24 BD24 BG27 BF25 AW24 BC21 BG26 BH26 BH17 AY25

DDRA_SDM1 DDRA_SDM2 DDRA_SDM3 DDRA_SDM4 DDRA_SDM5 DDRA_SDM6 DDRA_SDM7

DDRA_SDQS0 DDRA_SDQS1 DDRA_SDQS2 DDRA_SDQS3 DDRA_SDQS4 DDRA_SDQS5 DDRA_SDQS6 DDRA_SDQS7

DDRA_SDQS0# DDRA_SDQS1# DDRA_SDQS2# DDRA_SDQS3# DDRA_SDQS4# DDRA_SDQS5# DDRA_SDQS6# DDRA_SDQS7#

DDRA_SMA0 DDRA_SMA1 DDRA_SMA2 DDRA_SMA3 DDRA_SMA4 DDRA_SMA5 DDRA_SMA6 DDRA_SMA7 DDRA_SMA8 DDRA_SMA9 DDRA_SMA10 DDRA_SMA11 DDRA_SMA12 DDRA_SMA13 DDRA_SMA14

DDRA_SDQ[0..63]<14>

D D

C C

B B

DDRA_SDM[0..7]<14> DDRA_SMA[0..14]<14>

DDRA_SDQ0 DDRA_SDQ1 DDRA_SDQ2 DDRA_SDQ3 DDRA_SDQ4 DDRA_SDQ5 DDRA_SDQ6 DDRA_SDQ7 DDRA_SDQ8 DDRA_SDQ9 DDRA_SDQ10 DDRA_SDQ11 DDRA_SDQ12 DDRA_SDQ13 DDRA_SDQ14 DDRA_SDQ15 DDRA_SDQ16 DDRA_SDQ17 DDRA_SDQ18 DDRA_SDQ19 DDRA_SDQ20 DDRA_SDQ21 DDRA_SDQ22 DDRA_SDQ23 DDRA_SDQ24 DDRA_SDQ25 DDRA_SDQ26 DDRA_SDQ27 DDRA_SDQ28 DDRA_SDQ29 DDRA_SDQ30 DDRA_SDQ31 DDRA_SDQ32 DDRA_SDQ33 DDRA_SDQ34 DDRA_SDQ35 DDRA_SDQ36 DDRA_SDQ37 DDRA_SDQ38 DDRA_SDQ39 DDRA_SDQ40 DDRA_SDQ41 DDRA_SDQ42 DDRA_SDQ43 DDRA_SDQ44 DDRA_SDQ45 DDRA_SDQ46 DDRA_SDQ47 DDRA_SDQ48 DDRA_SDQ49 DDRA_SDQ50 DDRA_SDQ51 DDRA_SDQ52 DDRA_SDQ53 DDRA_SDQ54 DDRA_SDQ55 DDRA_SDQ56 DDRA_SDQ57 DDRA_SDQ58 DDRA_SDQ59 DDRA_SDQ60 DDRA_SDQ61 DDRA_SDQ62 DDRA_SDQ63

AJ38

AJ41 AN38 AM38

AJ36

AJ40 AM44 AM42 AN43 AN44 AU40 AT38 AN41 AN39 AU44 AU42 AV39 AY44 BA40 BD43 AV41 AY43 BB41 BC40 AY37 BD38 AV37 AT36 AY38 BB38 AV36

AW36

BD13 AU11 BC11 BA12 AU13 AV13 BD12 BC12

AU10 BA11

BD9 AY8 BA6 AV5 AV7 AT9 AN8 AU5 AU6

AT5 AN10 AM11

AM5

AN12 AM13

AJ11 AJ12

BB9 BA9

AV9

AJ9 AJ8

A A

Security Classification

2007/08/18 2008/8/18

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2007/08/18 2008/8/18

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

Cantiga (3/7)-DDRII

JHXXX M/B LA-4241P Schematic

949Tuesday, June 03, 2008

0.4

GMCH_LCD_CLK<18> GMCH_LCD_DATA<18>

1 2 1 2 1 2

30_0402_5%GM@

1 2

R84 0_0402_5%GM@R84 0_0402_5%GM@

1 2

R86 2.37K_0402_1%GM@R86 2.37K_0402_1%GM@

GMCH_TZCLK-<18> GMCH_TZCLK+<18> GMCH_TXCLK-<18> GMCH_TXCLK+<18>

GMCH_TZOUT0-<18> GMCH_TZOUT1-<18> GMCH_TZOUT2-<18>

GMCH_TZOUT0+<18> GMCH_TZOUT1+<18> GMCH_TZOUT2+<18>

GMCH_TXOUT0-<18> GMCH_TXOUT1-<18> GMCH_TXOUT2-<18>

GMCH_TXOUT0+<18> GMCH_TXOUT1+<18> GMCH_TXOUT2+<18>

12 12 12

GMCH_CRT_CLK GMCH_CRT_DATA CRT_HSYNC

CRT_VSYNC

GMCH_ENBKL<18>

D D

GMCH_ENVDD<18>

1 2

C63 100P_0402_50V8J@C63 100P_0402_50V8J@

Change to @ state

C C

R88 150_0402_1%R88 150_0402_1% R89 150_0402_1%R89 150_0402_1% R90 150_0402_1%R90 150_0402_1%

GMCH_CRT_B<19> GMCH_CRT_G<19> GMCH_CRT_R<19>

GMCH_CRT_CLK<19>

B B

GMCH_CRT_DATA<19>

GMCH_CRT_HSYNC<19>

GMCH_CRT_VSYNC<19>

Conntc to 0 Ohm when use PM chip

R91 150_0402_1%GM@R91 150_0402_1%GM@ R92 150_0402_1%GM@R92 150_0402_1%GM@ R93 150_0402_1%GM@R93 150_0402_1%GM@

R94

R95

10/22 follow CRB and Checklist recommend use 30 Ohm (SD028300A80)

Common design recommend H/VSYNC width=8 mil

+3VS

R101 2.2K_0402_5%GM@R101 2.2K_0402_5%GM@

1 2

R103 2.2K_0402_5%GM@R103 2.2K_0402_5%GM@

1 2

R105 10K_0402_5%GM@R105 10K_0402_5%GM@

1 2

R107 10K_0402_5%GM@R107 10K_0402_5%GM@

1 2

A A

R91

0_0402_5%

PM@

GMCH_LCD_CLK GMCH_LCD_DATA LCTLB_DATA LCTLA_CLK

R92

0_0402_5%

PM@

R93

0_0402_5%

PM@

100P_0402_50V8J

C96

C97

LBKLT_EN LCTLA_CLK LCTLB_DATA GMCH_LCD_CLK GMCH_LCD_DATA GMCH_ENVDD

LVDS_IBG

GMCH_TZCLKGMCH_TZCLK+ GMCH_TXCLKGMCH_TXCLK+

GMCH_TZOUT0GMCH_TZOUT1GMCH_TZOUT2-

GMCH_TZOUT0+ GMCH_TZOUT1+ GMCH_TZOUT2+

GMCH_TXOUT0GMCH_TXOUT1GMCH_TXOUT2-

GMCH_TXOUT0+ GMCH_TXOUT1+ GMCH_TXOUT2+

GMCH_TV_COMPS GMCH_TV_LUMA GMCH_TV_CRMA

TV_DCONSEL_0 TV_DCONSEL_1

CRT_IREF

R98

1.02K_0402_1%

1 2

U3C

L32

L_BKLT_CTRL

G32

L_BKLT_EN

M32

L_CTRL_CLK

M33

L_CTRL_DATA

K33

L_DDC_CLK

J33

L_DDC_DATA

M29

L_VDD_EN

C44

LVDS_IBG

B43

LVDS_VBG

E37

LVDS_VREFH

E38

LVDS_VREFL

C41

LVDSA_CLK#

C40

LVDSA_CLK

B37

LVDSB_CLK#

A37

LVDSB_CLK

H47

LVDSA_DATA#_0

E46

LVDSA_DATA#_1

G40

LVDSA_DATA#_2

A40

LVDSA_DATA#_3

H48

LVDSA_DATA_0

D45

LVDSA_DATA_1

F40

LVDSA_DATA_2

B40

LVDSA_DATA_3

A41

LVDSB_DATA#_0

H38

LVDSB_DATA#_1

G37

LVDSB_DATA#_2

J37

LVDSB_DATA#_3

B42

LVDSB_DATA_0

G38

LVDSB_DATA_1

F37

LVDSB_DATA_2

K37

LVDSB_DATA_3

F25

TVA_DAC

H25

TVB_DAC

K25

TVC_DAC

H24

TV_RTN

C31

TV_DCONSEL_0

E32

TV_DCONSEL_1

E28

CRT_BLUE

G28

CRT_GREEN

J28

CRT_RED

G29

CRT_IRTN

H32

CRT_DDC_CLK

J32

CRT_DDC_DATA

J29

CRT_HSYNC

E29

CRT_TVO_IREF

L29

CRT_VSYNC

R99 0_0402_5%PM@R99 0_0402_5%PM@

1 2

R100 0_0402_5%PM@R100 0_0402_5%PM@

1 2

R102 0_0402_5%PM@R102 0_0402_5%PM@

1 2

R104 0_0402_5%PM@R104 0_0402_5%PM@

1 2

R106 0_0402_5%PM@R106 0_0402_5%PM@

1 2

R108 0_0402_5%PM@R108 0_0402_5%PM@

1 2

R109 0_0402_5%R109 0_0402_5%

1 2

R110 0_0402_5%R110 0_0402_5%

1 2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

PEG_COMP

PEG_RX_0 PEG_RX_1 PEG_RX_2 PEG_RX_3 PEG_RX_4 PEG_RX_5 PEG_RX_6 PEG_RX_7 PEG_RX_8 PEG_RX_9

PEG_TX_0 PEG_TX_1 PEG_TX_2 PEG_TX_3 PEG_TX_4 PEG_TX_5 PEG_TX_6 PEG_TX_7 PEG_TX_8 PEG_TX_9

T37 T36

PCIE_GTX_C_MRX_N0

H44

PCIE_GTX_C_MRX_N1

J46

PCIE_GTX_C_MRX_N2

L44

PCIE_GTX_C_MRX_N3

L40

PCIE_GTX_C_MRX_N4

N41

PCIE_GTX_C_MRX_N5

P48

PCIE_GTX_C_MRX_N6

N44

PCIE_GTX_C_MRX_N7

T43

PCIE_GTX_C_MRX_N8

U43

PCIE_GTX_C_MRX_N9

Y43

PCIE_GTX_C_MRX_N10

Y48

PCIE_GTX_C_MRX_N11

Y36

PCIE_GTX_C_MRX_N12

AA43

PCIE_GTX_C_MRX_N13

AD37

PCIE_GTX_C_MRX_N14

AC47

PCIE_GTX_C_MRX_N15

AD39

PCIE_GTX_C_MRX_P0

H43

PCIE_GTX_C_MRX_P1

J44

PCIE_GTX_C_MRX_P2

L43

PCIE_GTX_C_MRX_P3

L41

PCIE_GTX_C_MRX_P4

N40

PCIE_GTX_C_MRX_P5

P47

PCIE_GTX_C_MRX_P6

N43

PCIE_GTX_C_MRX_P7

T42

PCIE_GTX_C_MRX_P8

U42

PCIE_GTX_C_MRX_P9

Y42

PCIE_GTX_C_MRX_P10

W47

PCIE_GTX_C_MRX_P11

Y37

PCIE_GTX_C_MRX_P12

AA42

PCIE_GTX_C_MRX_P13

AD36

PCIE_GTX_C_MRX_P14

AC48

PCIE_GTX_C_MRX_P15

AD40

PCIE_MTX_GRX_N0

J41

PCIE_MTX_GRX_N1

M46

PCIE_MTX_GRX_N2

M47

PCIE_MTX_GRX_N3

M40

PCIE_MTX_GRX_N4

M42

PCIE_MTX_GRX_N5

R48

PCIE_MTX_GRX_N6

N38

PCIE_MTX_GRX_N7

T40

PCIE_MTX_GRX_N8

U37

PCIE_MTX_GRX_N9

U40

PCIE_MTX_GRX_N10

Y40

PCIE_MTX_GRX_N11

AA46

PCIE_MTX_GRX_N12

AA37

PCIE_MTX_GRX_N13

AA40

PCIE_MTX_GRX_N14

AD43

PCIE_MTX_GRX_N15

AC46

PCIE_MTX_GRX_P0

J42

PCIE_MTX_GRX_P1

L46

PCIE_MTX_GRX_P2

M48

PCIE_MTX_GRX_P3

M39

PCIE_MTX_GRX_P4

M43

PCIE_MTX_GRX_P5

R47

PCIE_MTX_GRX_P6

N37

PCIE_MTX_GRX_P7

T39

PCIE_MTX_GRX_P8

U36

PCIE_MTX_GRX_P9

U39

PCIE_MTX_GRX_P10

Y39

PCIE_MTX_GRX_P11

Y46

PCIE_MTX_GRX_P12

AA36

PCIE_MTX_GRX_P13

AA39

PCIE_MTX_GRX_P14

AD42

PCIE_MTX_GRX_P15

AD46

PEG_COMPI

PEG_COMPO

PEG_RX#_0 PEG_RX#_1 PEG_RX#_2 PEG_RX#_3 PEG_RX#_4 PEG_RX#_5 PEG_RX#_6 PEG_RX#_7 PEG_RX#_8 PEG_RX#_9

LVDS TV VGA

PEG_RX#_10 PEG_RX#_11 PEG_RX#_12 PEG_RX#_13 PEG_RX#_14 PEG_RX#_15

PEG_RX_10 PEG_RX_11 PEG_RX_12 PEG_RX_13 PEG_RX_14 PEG_RX_15

PEG_TX#_0 PEG_TX#_1 PEG_TX#_2 PEG_TX#_3 PEG_TX#_4 PEG_TX#_5 PEG_TX#_6 PEG_TX#_7 PEG_TX#_8

PCI-EXPRESS GRAPHICS

PEG_TX#_9 PEG_TX#_10 PEG_TX#_11 PEG_TX#_12 PEG_TX#_13 PEG_TX#_14 PEG_TX#_15

PEG_TX_10

PEG_TX_11

PEG_TX_12

PEG_TX_13

PEG_TX_14

PEG_TX_15

CANTIGA ES_FCBGA1329GM@

Reserved for 1.5V level shift circuit

GMCH_LCD_CLK GMCH_LCD_DATA LCTLB_DATA LCTLA_CLK GMCH_CRT_CLK GMCH_CRT_DATA TV_DCONSEL_0 TV_DCONSEL_1

2007/08/18 2008/8/18

HDA_BITCLK_NB<21> HDA_RST_NB#<21> HDA_SDOUT_NB<21> HDA_SYNC_NB<21> HDA_SDIN2<21>

U67 pn is SA00002CT00 for 030 used

Compal Secret Data

20/25mils R492 Close to GMCH < 0.5'

1 2

R85 49.9_0402_1%R85 49.9_0402_1%

+1.05VS_PEG

PCIE_MTX_C_GRX_N[0..15] PCIE_MTX_C_GRX_P[0..15] PCIE_GTX_C_MRX_N[0..15] PCIE_GTX_C_MRX_P[0..15]

Routing notice:

PCIE_GTX_C_MRX_P3

NB Ext VGA

C64 0.1U_0402_10V7KC64 0.1U_0402_10V7K

C65 0.1U_0402_10V7KC65 0.1U_0402_10V7K

1 2

C67 0.1U_0402_10V7KC67 0.1U_0402_10V7K

1 2

C69 0.1U_0402_10V7KPM@C69 0.1U_0402_10V7KPM@

1 2

C71 0.1U_0402_10V7KPM@C71 0.1U_0402_10V7KPM@

1 2

C73 0.1U_0402_10V7KPM@C73 0.1U_0402_10V7KPM@

1 2

C75 0.1U_0402_10V7KPM@C75 0.1U_0402_10V7KPM@

1 2

C77 0.1U_0402_10V7KPM@C77 0.1U_0402_10V7KPM@

1 2

C79 0.1U_0402_10V7KPM@C79 0.1U_0402_10V7KPM@

1 2

C81 0.1U_0402_10V7KC81 0.1U_0402_10V7K

1 2

C83 0.1U_0402_10V7KC83 0.1U_0402_10V7K

1 2

C85 0.1U_0402_10V7KPM@C85 0.1U_0402_10V7KPM@

1 2

C87 0.1U_0402_10V7KPM@C87 0.1U_0402_10V7KPM@

1 2

C89 0.1U_0402_10V7KPM@C89 0.1U_0402_10V7KPM@

1 2

C91 0.1U_0402_10V7KPM@C91 0.1U_0402_10V7KPM@

1 2

C93 0.1U_0402_10V7KPM@C93 0.1U_0402_10V7KPM@

1 2

C95 0.1U_0402_10V7KPM@C95 0.1U_0402_10V7KPM@

1 2

C748

0.1U_0402_16V4Z

Deciphered Date

HDA_SDOUT_NB HDA_SYNC_NB HDA_SDIN2

1 2

C66 0.1U_0402_10V7KC66 0.1U_0402_10V7K

1 2

C68 0.1U_0402_10V7KPM@C68 0.1U_0402_10V7KPM@ C70 0.1U_0402_10V7KPM@C70 0.1U_0402_10V7KPM@ C72 0.1U_0402_10V7KPM@C72 0.1U_0402_10V7KPM@ C74 0.1U_0402_10V7KPM@C74 0.1U_0402_10V7KPM@ C76 0.1U_0402_10V7KPM@C76 0.1U_0402_10V7KPM@ C78 0.1U_0402_10V7KPM@C78 0.1U_0402_10V7KPM@

C80 0.1U_0402_10V7KC80 0.1U_0402_10V7K

1 2

C82 0.1U_0402_10V7KC82 0.1U_0402_10V7K

1 2

C84 0.1U_0402_10V7KPM@C84 0.1U_0402_10V7KPM@ C86 0.1U_0402_10V7KPM@C86 0.1U_0402_10V7KPM@ C88 0.1U_0402_10V7KPM@C88 0.1U_0402_10V7KPM@ C90 0.1U_0402_10V7KPM@C90 0.1U_0402_10V7KPM@ C92 0.1U_0402_10V7KPM@C92 0.1U_0402_10V7KPM@ C94 0.1U_0402_10V7KPM@C94 0.1U_0402_10V7KPM@

0.1U_0402_16V4Z

U67

VCCB

CLK_OUT

CMD_B

GND

FXL2SD106BQX_DQFN16_2P5X3P5~D

PCIE_MTX_C_GRX_N[0..15] <17,25> PCIE_MTX_C_GRX_P[0..15] <17,25> PCIE_GTX_C_MRX_N[0..15] <17> PCIE_GTX_C_MRX_P[0..15] <17>

GM@

R87 0_0402_5%

1 2

PCIE_MTX_C_GRX_N0 PCIE_MTX_C_GRX_N1 PCIE_MTX_C_GRX_N2 PCIE_MTX_C_GRX_N3

1 2 1 2 1 2 1 2 1 2 1 2

+1.5VS+3.3VS

C747

R787

VCCA CLK_IN CMD_A

1 2

GMCH_HDA_BITCLKHDA_BITCLK_NB

GMCH_HDA_RST#HDA_RST_NB#

GMCH_HDA_SDOUT

GMCH_HDA_SYNC

GMCH_HDA_SDIN2

+1.5VS

Title

Size Document Number Rev

Custom

Date: Sheet

Date: Sheet of

PCIE_MTX_C_GRX_N4

PCIE_MTX_C_GRX_N5 PCIE_MTX_C_GRX_N6 PCIE_MTX_C_GRX_N7 PCIE_MTX_C_GRX_N8 PCIE_MTX_C_GRX_N9 PCIE_MTX_C_GRX_N10 PCIE_MTX_C_GRX_N11 PCIE_MTX_C_GRX_N12 PCIE_MTX_C_GRX_N13 PCIE_MTX_C_GRX_N14 PCIE_MTX_C_GRX_N15

PCIE_MTX_C_GRX_P0 PCIE_MTX_C_GRX_P1 PCIE_MTX_C_GRX_P2 PCIE_MTX_C_GRX_P3

PCIE_MTX_C_GRX_P4 PCIE_MTX_C_GRX_P5 PCIE_MTX_C_GRX_P6 PCIE_MTX_C_GRX_P7 PCIE_MTX_C_GRX_P8 PCIE_MTX_C_GRX_P9 PCIE_MTX_C_GRX_P10 PCIE_MTX_C_GRX_P11 PCIE_MTX_C_GRX_P12 PCIE_MTX_C_GRX_P13 PCIE_MTX_C_GRX_P14 PCIE_MTX_C_GRX_P15

HDA_BITCLK_NB GMCH_HDA_BITCLK HDA_RST_NB# HDA_SDOUT_NB HDA_SYNC_NB

HDA_SDIN2 GMCH_HDA_SDIN2

10K_0402_5%

Compal Electronics, Inc.

Cantiga (4/7)-VGA/LVDS/TV

JHXXX M/B LA-4241P Schematic

TMDS_B_HPD# <25>

CH7318

PCIE_MTX_C_GRX_N0 <17,25> PCIE_MTX_C_GRX_N1 <17,25> PCIE_MTX_C_GRX_N2 <17,25> PCIE_MTX_C_GRX_N3 <17,25>

PCIE_MTX_C_GRX_P0 <17,25> PCIE_MTX_C_GRX_P1 <17,25> PCIE_MTX_C_GRX_P2 <17,25> PCIE_MTX_C_GRX_P3 <17,25>

RP60

GMCH_HDA_RST#

GMCH_HDA_SDOUT

GMCH_HDA_SYNC

0_0804_8P4R_5%

0_0804_8P4R_5% R786

R786

1 2

0_0402_5%

GMCH_HDA_BITCLK <8> GMCH_HDA_RST# <8> GMCH_HDA_SDOUT <8> GMCH_HDA_SYNC <8> GMCH_HDA_SDIN2 <8>

10 49Tuesday, June 03, 2008

0.4

hexainf@hotmail.com

U3F

+1.8V

D D

C C

+VCC_AXG

B B

T22 PAD

T23 PAD

A A

U3F

AP33

VCC_SM_1

AN33

VCC_SM_2

BH32

VCC_SM_3

BG32

VCC_SM_4

BF32

VCC_SM_5

BD32

VCC_SM_6

BC32

VCC_SM_7

BB32

VCC_SM_8

BA32

VCC_SM_9

AY32

VCC_SM_10

AW32

VCC_SM_11

AV32

VCC_SM_12

AU32

VCC_SM_13

AT32

VCC_SM_14

AR32

VCC_SM_15

AP32

VCC_SM_16

AN32

VCC_SM_17

BH31

VCC_SM_18

BG31

VCC_SM_19

BF31

VCC_SM_20

BG30

VCC_SM_21

BH29

VCC_SM_22

BG29

VCC_SM_23

BF29

VCC_SM_24

BD29

VCC_SM_25

BC29

VCC_SM_26

BB29

VCC_SM_27

BA29

VCC_SM_28

AY29

VCC_SM_29

AW29

VCC_SM_30

AV29

VCC_SM_31

AU29

VCC_SM_32

AT29

VCC_SM_33

AR29

VCC_SM_34

AP29

VCC_SM_35

BA36

VCC_SM_36/NC

BB24

VCC_SM_37/NC

BD16

VCC_SM_38/NC

BB21

VCC_SM_39/NC

AW16

VCC_SM_40/NC

AW13

VCC_SM_41/NC

AT13

VCC_SM_42/NC

Y26

VCC_AXG_1

AE25

VCC_AXG_2

AB25

VCC_AXG_3

AA25

VCC_AXG_4

AE24

VCC_AXG_5

AC24

VCC_AXG_6

AA24

VCC_AXG_7

Y24

VCC_AXG_8

AE23

VCC_AXG_9

AC23

VCC_AXG_10

AB23

VCC_AXG_11

AA23

VCC_AXG_12

AJ21

VCC_AXG_13

AG21

VCC_AXG_14

AE21

VCC_AXG_15

AC21

VCC_AXG_16

AA21

VCC_AXG_17

Y21

VCC_AXG_18

AH20

VCC_AXG_19

AF20

VCC_AXG_20

AE20

VCC_AXG_21

AC20

VCC_AXG_22

AB20

VCC_AXG_23

AA20

VCC_AXG_24

T17

VCC_AXG_25

T16

VCC_AXG_26

AM15

VCC_AXG_27

AL15

VCC_AXG_28

AE15

VCC_AXG_29

AJ15

VCC_AXG_30

AH15

VCC_AXG_31

AG15

VCC_AXG_32

AF15

VCC_AXG_33

AB15

VCC_AXG_34

AA15

VCC_AXG_35

Y15

VCC_AXG_36

V15

VCC_AXG_37

U15

VCC_AXG_38

AN14

VCC_AXG_39

AM14

VCC_AXG_40

U14

VCC_AXG_41

T14

VCC_AXG_42

AJ14

VCC_AXG_SENSE

AH14

VSS_AXG_SENSE

CANTIGA ES_FCBGA1329

GM@

VCC_AXG_NTCF_1 VCC_AXG_NCTF_2 VCC_AXG_NCTF_3 VCC_AXG_NCTF_4 VCC_AXG_NCTF_5 VCC_AXG_NCTF_6 VCC_AXG_NCTF_7 VCC_AXG_NCTF_8

VCC SM

VCC_AXG_NCTF_9 VCC_AXG_NCTF_10 VCC_AXG_NCTF_11 VCC_AXG_NCTF_12 VCC_AXG_NCTF_13 VCC_AXG_NCTF_14 VCC_AXG_NCTF_15 VCC_AXG_NCTF_16 VCC_AXG_NCTF_17 VCC_AXG_NCTF_18 VCC_AXG_NCTF_19 VCC_AXG_NCTF_20 VCC_AXG_NCTF_21 VCC_AXG_NCTF_22 VCC_AXG_NCTF_23 VCC_AXG_NCTF_24 VCC_AXG_NCTF_25 VCC_AXG_NCTF_26 VCC_AXG_NCTF_27 VCC_AXG_NCTF_28 VCC_AXG_NCTF_29 VCC_AXG_NCTF_30 VCC_AXG_NCTF_31 VCC_AXG_NCTF_32 VCC_AXG_NCTF_33 VCC_AXG_NCTF_34 VCC_AXG_NCTF_35 VCC_AXG_NCTF_36 VCC_AXG_NCTF_37 VCC_AXG_NCTF_38 VCC_AXG_NCTF_39 VCC_AXG_NCTF_40 VCC_AXG_NCTF_41 VCC_AXG_NCTF_42 VCC_AXG_NCTF_43 VCC_AXG_NCTF_44

VCC GFX NCTF

VCC_AXG_NCTF_45 VCC_AXG_NCTF_46 VCC_AXG_NCTF_47 VCC_AXG_NCTF_48 VCC_AXG_NCTF_49 VCC_AXG_NCTF_50 VCC_AXG_NCTF_51 VCC_AXG_NCTF_52

POWER

VCC_AXG_NCTF_53 VCC_AXG_NCTF_54 VCC_AXG_NCTF_55 VCC_AXG_NCTF_56 VCC_AXG_NCTF_57 VCC_AXG_NCTF_58 VCC_AXG_NCTF_59 VCC_AXG_NCTF_60

VCC GFX

VCC_SM_LF1 VCC_SM_LF2 VCC_SM_LF3 VCC_SM_LF4 VCC_SM_LF5 VCC_SM_LF6 VCC_SM_LF7

VCC SM LF

W28 V28 W26 V26 W25 V25 W24 V24 W23 V23 AM21 AL21 AK21 W21 V21 U21 AM20 AK20 W20 U20 AM19 AL19 AK19 AJ19 AH19 AG19 AF19 AE19 AB19 AA19 Y19 W19 V19 U19 AM17 AK17 AH17 AG17 AF17 AE17 AC17 AB17 Y17 W17 V17 AM16 AL16 AK16 AJ16 AH16 AG16 AF16 AE16 AC16 AB16 AA16 Y16 W16 V16 U16

AV44 BA37 AM40 AV21 AY5 AM10 BB13

+VCC_AXG

VCCSM_LF1 VCCSM_LF2 VCCSM_LF3 VCCSM_LF4 VCCSM_LF5 VCCSM_LF6 VCCSM_LF7

C127

0.1U_0402_16V4Z

Checklist 220u ESR max 15m ohm 330u ESR max 12m ohm

220u ESR 15m ohm Package(L*W*H)7.3*4.3*1.9 Rating 4V

330u ESR 15m ohm Package(L*W*H)7.3*4.3*1.8 Rating 2.5V

C106

C106 220U_D2_4VM_R15

220U_D2_4VM_R15

C111

330U_D2E_2.5VM

+VCC_AXG

C118

330U_D2E_2.5VM

GM@

Add these caps around PCI-E bus of NB

C128

0.1U_0402_16V4Z

C129

0.22U_0402_6.3V6K

C130

0.22U_0402_6.3V6K

+1.05VS

VCC: 2898.52mA (220UF*1, 22UF*1, 0.22UF*2, 0.1UF*1)

10U_0805_10V4Z

VCC_SM: 3300mA

+1.8V

(330UF*1,22UF*2, 0.1UF*1)

22U_0805_6.3V6M@

VCC_AXG: 8700mA (330UF*2,22UF*1, 10UF*1, 1U*1, 0.47U*1, 0.1UF*2)

C119

GM@

330U_D2E_2.5VM

+1.05VS

C763

0.1U_0402_16V4Z

C131

0.47U_0603_16V4Z

C108

C107

0.22U_0603_16V7K

C112

10U_0805_10V4Z

C120

10U_0805_10V4Z

GM@

C764

0.1U_0402_16V4Z

C132

1U_0603_10V4Z

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

0.22U_0603_16V7K

C113

4.7U_0805_10V4Z

C121

GM@

10U_0805_10V4Z

C133

C133 1U_0603_10V4Z

1U_0603_10V4Z

Issued Date

C109

0.1U_0402_16V4Z

C114

1U_0603_10V4Z

C122

1U_0603_10V4Z

GM@

C765

0.1U_0402_16V4Z

C110

9/14 add for reservation (IFTXX)

C116

C117

C115

0.1U_0402_16V4Z@

C123

GM@

0.47U_0603_16V4Z

C766

0.1U_0402_16V4Z

C117 1U_0603_10V4Z

1U_0603_10V4Z

C124

0.1U_0402_16V4Z

GM@

C767

0.1U_0402_16V4Z

C125

GM@

0.1U_0402_16V4Z

R114

R114 0_0805_5%

0_0805_5%

PM@

10/05 This is for GM@ (IFTXX) Remember open stencil at GM@

+1.05VS +VCC_AXG

1 2

PAD-OPEN 3x3m

GM@

J5 JOPENGM@J5 JOPENGM@ J6 JOPENGM@J6 JOPENGM@ J7 JOPENGM@J7 JOPENGM@

12 12 12

1/25 Change J5, J6, J7 from 43x79 to 43x39

Compal Secret Data

2007/08/18 2008/8/18

Compal Secret Data

Deciphered Date

C126

1U_0603_10V4Z

+1.05VS

U3G

AG34

VCC_1

AC34

VCC_2

AB34

VCC_3

AA34

VCC_4

Y34

VCC_5

V34

VCC_6

U34

VCC_7

AM33

VCC_8

AK33

VCC_9

AJ33

VCC_10

AG33

VCC_11

AF33

VCC_12

AE33

VCC_13

AC33

VCC_14

AA33

VCC_15

Y33

VCC_16

W33

VCC_17

V33

VCC_18

U33

VCC_19

AH28

VCC_20

AF28

VCC_21

AC28

VCC_22

AA28

VCC_23

AJ26

VCC_24

AG26

VCC_25

AE26

VCC_26

AC26

VCC_27

AH25

VCC_28

AG25

VCC_29

AF25

VCC_30

AG24

VCC_31

AJ23

VCC_32

AH23

VCC_33

AF23

VCC_34

T32

VCC_35

CANTIGA ES_FCBGA1329

GM@

Title

Size Document Number Rev

Custom

Date: Sheet

VCC CORE

POWER

11 49Tuesday, June 03, 2008

AM32 AL32 AK32 AJ32 AH32 AG32 AE32 AC32 AA32 Y32 W32 U32 AM30 AL30 AK30 AH30 AG30 AF30 AE30 AC30 AB30 AA30 Y30 W30 V30 U30 AL29 AK29 AJ29 AH29 AG29 AE29 AC29 AA29 Y29 W29 V29 AL28 AK28 AL26 AK26 AK25 AK24 AK23

VCC_NCTF_1 VCC_NCTF_2 VCC_NCTF_3 VCC_NCTF_4 VCC_NCTF_5 VCC_NCTF_6 VCC_NCTF_7 VCC_NCTF_8

VCC_NCTF_9 VCC_NCTF_10 VCC_NCTF_11 VCC_NCTF_12 VCC_NCTF_13 VCC_NCTF_14 VCC_NCTF_15 VCC_NCTF_16 VCC_NCTF_17 VCC_NCTF_18 VCC_NCTF_19 VCC_NCTF_20 VCC_NCTF_21 VCC_NCTF_22 VCC_NCTF_23 VCC_NCTF_24 VCC_NCTF_25 VCC_NCTF_26 VCC_NCTF_27 VCC_NCTF_28

VCC NCTF

VCC_NCTF_29 VCC_NCTF_30 VCC_NCTF_31 VCC_NCTF_32 VCC_NCTF_33 VCC_NCTF_34 VCC_NCTF_35 VCC_NCTF_36 VCC_NCTF_37 VCC_NCTF_38 VCC_NCTF_39 VCC_NCTF_40 VCC_NCTF_41 VCC_NCTF_42 VCC_NCTF_43 VCC_NCTF_44

Compal Electronics, Inc.

Cantiga GMCH(5/7)-GTL

JHXXX M/B LA-4241P Schematic

+1.05VS

0.4

+1.05VS

VCCA_HPLL: 24mA

Please check Power source if want support IAMT

D D

(4.7UF*1, 0.1UF*1)

VCCA_MPLL: 139.2mA (22UF*1, 0.1UF*1)

1 2

MBK1608121YZF_0603

120Ohm@100MHz

1 2

MBK1608121YZF_0603

C134

4.7U_0805_10V4Z

R116

1_0603_1%

+1.05VS_HPLL

+1.05VS_MPLL

VCCA_CRT_DAC: 73mA (0.1UF*1, 0.01UF*1)

+3VS_TV_CRT_DAC

1 2

R120

R120 0_0603_5%

0_0603_5%

GM@

C149

GM@

0.1U_0402_16V4Z

0.01U_0402_16V7K

C135

0.1U_0402_16V4Z

Please check Power source if want support IAMT

C146

C147

C147 10U_0805_10V4Z

10U_0805_10V4Z

+3VS_CRTDAC

C150

GM@

+1.05VS

0.1U_0402_16V4Z

10U_FLC-453232-100K_0.25A_10%

10uH 10% 201005-548

GM@

L55

MBK1608121YZF_0603

VCCA_DPLLA VCCA_DPLLB: 64.8mA (220UF*1, 0.1UF*1)

GM@

L56

MBK1608121YZF_0603

10U_FLC-453232-100K_0.25A_10%

10uH 10% 201005-548

220u ESR 15m ohm Package(L*W*H)7.3*4.3*1.9 Rating 4V

+3VS

+1.5VS

Please check Power source if want support IAMT

R121

R121 0_0402_5%

0_0402_5%

PM@

Close to Ball A26, B27

C C

+3VS_TV_CRT_DAC

220u ESR 15m ohm Package(L*W*H)7.3*4.3*1.9 Rating 4V

VCCA_DAC_BG: 2.6833333mA (0.1UF*1, 0.01UF*1)

1 2

R127

R127 0_0603_5%

0_0603_5%

C164

GM@

0.1U_0402_16V4Z

C165

GM@

0.01U_0402_16V7K

Please check Power source if want support IAMT

+3VS_DACBG

C166

GM@

10U_0805_10V4Z

R128

R128 0_0402_5%

0_0402_5%

PM@

+1.05VS

C155

C155 220U_D2_4VM_R15

220U_D2_4VM_R15

Close to Ball A25

1 2

+3VS

R131

R131 0_0603_5%

0_0603_5%

B B

GM@

+3VS

A A

C707

1U_0402_6.3V4Z

VCCA_TV_DAC: 40mA (0.1UF*1,

0.01UF*1 for each DAC)

1 2

MBK1608221YZF_0603

GM@

180Ohm@100MHz

+1.5VS

copy G913CF_SOT23-5 Footprint

U36

Vin

SHDN

GND

G916T1UF

GM@

VCCD_TVDAC: 58.696mA (0.1UF*1, 0.01UF*1)

1 2

R136

R136 0_0603_5%

0_0603_5%

@U36

Vout

R679 2K_0402_1%

SET

R680 10K_0402_1%

C174

GM@

0.1U_0402_16V4Z

C183

0.1U_0402_16V4Z

0.022U_0402_16V7K

+1.5VS_LDO

1 2

+3VS_TV_CRT_DAC

C175

GM@

0.01U_0402_16V7K

+1.5VS_TVDAC

C184

Also power for internal Thermal Sensor

+1.5VS

1 2

R681 0_0402_5%R681 0_0402_5%

C710

4.7U_0805_10V4Z

R133

R133 0_0402_5%

0_0402_5%

PM@

1 2

MBK1608221YZF_0603

180Ohm@100MHz

+1.05VS_DPLLA

@L1

1 2

+1.05VS

C154

C154 10U_0805_10V4Z

10U_0805_10V4Z

C136

220U_D2_4VM_R15

+1.05VS_DPLLB

@L4

C142

220U_D2_4VM_R15

R118

R118 0_0603_5%@

0_0603_5%@

1 2

R119

R119 0_0603_5%

0_0603_5%

1 2

L5 MBK1608221YZF_0603

MBK1608221YZF_0603

1 2

R123

R123 1_0402_1%

1_0402_1%

1 2

R124

0_0603_5%

Please check Power source if want support IAMT

1 2

+1.05VS

R126

R126 0_0603_5%

0_0603_5%

+1.5VS

Please check Power source if want support IAMT

VCCD_QDAC: 48.363mA (0.1UF*1, 0.01UF*1)

C186

0.1U_0402_16V4Z

0.01U_0402_16V7K

0.1U_0402_16V4Z

C137

GM@

0.1U_0402_16V4Z

C143

GM@

+1.8V_TX_LVDS

+VCCA_PEG_BG

0.1U_0402_16V4Z

1 2

+1.05VS_A_SM

C156

C156 22U_0805_6.3V6M

22U_0805_6.3V6M

NO_STUFF

1 2

R132

R132 0_0603_5%

0_0603_5%

GM@

0_0402_5%

+1.05VS

C187

C144

GM@

1000P_0402_50V7K

VCCA_PEG_BG: 0.414mA

C148

(0.1UF*1)

C157

10U_0805_10V4Z

+1.05VS_A_SM_CK

C162

2.2U_0603_6.3V6K

R115

PM@

R117

PM@

0_0402_5%

C705

GM@

0_0402_5%

10U_0805_10V4Z

C706

GM@

+1.05VS_A_PEGPLL

C151

0.1U_0402_16V4Z

VCCA_SM: (22UF*2, 4.7UF*1, 1UF*1)

C158

4.7U_0805_10V4Z

VCCA_SM_CK: 24mA (22UF*1, 2.2UF*1,0.1UF*1)

C167

10U_0805_10V4Z

NO_STUFF

+3VS_TV_CRT_DAC

+1.5VS_HDA

R134

PM@

C176

GM@

0.1U_0402_16V4Z

VCCD_HDA: 50mA (0.1UF*1)

Close to A32

VCCD_HPLL: 157.2mA (0.1UF*1)

C178

0.1U_0402_16V4Z

Close to AF1

VCCD_PEG_PLL: 50mA (0.1UF*1)

+1.8V

+1.5VS_QDAC

Checklist 220u ESR max 15m ohm

220u ESR 15m ohm Package(L*W*H)7.3*4.3*1.9 Rating 4V

+3VS_CRTDAC

+3VS_DACBG

+1.05VS_DPLLA

+1.05VS_DPLLB

+1.05VS_HPLL +1.05VS_MPLL

VCCA_LVDS: 13.2mA (1000PF*1)

VCCA_PEG_PLL: 50mA (10UF*1,0.1UF*1)

C159

1U_0402_6.3V4Z

C163

0.1U_0402_16V4Z

+1.5VS_TVDAC

+1.5VS_QDAC

+1.05VS_A_PEGPLL

C179

Close to AA47

0.1U_0402_16V4Z

1 2

R137

R137 0_0402_5%

0_0402_5%

GM@

1U_0402_6.3V4Z

VCCD_LVDS: 60.31mA (1UF*1)

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

AD1 AE1

AD48

AA48

AR20 AP20 AN20 AR17 AP17 AN17 AT16 AR16 AP16

AP28 AN28 AP25 AN25

AN24 AM28 AM26 AM25

AL25 AM24

AL24 AM23

AL23

M25

AA47

M38

+1.8V_LVDS

C185

GM@

U3H

73mA

B27

VCCA_CRT_DAC_1

A26

VCCA_CRT_DAC_2

5mA

A25

VCCA_DAC_BG

B25

VSSA_DAC_BG

64.8mA

F47

VCCA_DPLLA

L48

VCCA_DPLLB

24mA

VCCA_HPLL

139.2mA

VCCA_MPLL

13.2mA

J48

VCCA_LVDS

J47

VSSA_LVDS

0.414mA

VCCA_PEG_BG

50mA

VCCA_PEG_PLL

720mA

VCCA_SM_1 VCCA_SM_2 VCCA_SM_3 VCCA_SM_4 VCCA_SM_5 VCCA_SM_6 VCCA_SM_7 VCCA_SM_8 VCCA_SM_9

26mA

VCCA_SM_CK_1 VCCA_SM_CK_2 VCCA_SM_CK_3 VCCA_SM_CK_4 VCCA_SM_CK_5 VCCA_SM_CK_NCTF_1 VCCA_SM_CK_NCTF_2 VCCA_SM_CK_NCTF_3 VCCA_SM_CK_NCTF_4 VCCA_SM_CK_NCTF_5 VCCA_SM_CK_NCTF_6 VCCA_SM_CK_NCTF_7 VCCA_SM_CK_NCTF_8

79mA

B24

VCCA_TV_DAC_1

A24

VCCA_TV_DAC_2

50mA

A32

VCC_HDA

35mA

VCCD_TVDAC

1mA

L28

VCCD_QDAC

157.2mA

AF1

VCCD_HPLL

50mA

VCCD_PEG_PLL

60.31mA

VCCD_LVDS_1

L37

VCCD_LVDS_2

CANTIGA ES_FCBGA1329

GM@

R138

R138 0_0402_5%

0_0402_5%

PM@

2007/08/18 2008/8/18

POWER

HDA

TV+CRT use Ivccd_qdac = 0.5u+0.5u =1mA

852mA

VTT_1 VTT_2 VTT_3 VTT_4 VTT_5 VTT_6 VTT_7

VTT

VTT_8

VTT_9 VTT_10 VTT_11 VTT_12 VTT_13 VTT_14 VTT_15 VTT_16 VTT_17 VTT_18 VTT_19 VTT_20 VTT_21 VTT_22 VTT_23 VTT_24 VTT_25

CRTPLLA LVDSA PEG

321.35mA

VCC_AXF_1 VCC_AXF_2

A SM

VCC_AXF_3

AXF

124mA

VCC_SM_CK_1 VCC_SM_CK_2 VCC_SM_CK_3 VCC_SM_CK_4

SM CK

118.8mA

VCC_TX_LVDS

105.3mA

A CK

VCC_HV_1 VCC_HV_2 VCC_HV_3

1782mA

VCC_PEG_1 VCC_PEG_2 VCC_PEG_3 VCC_PEG_4 VCC_PEG_5

456mA

VCC_DMI_1 VCC_DMI_2 VCC_DMI_3 VCC_DMI_4

DMI PEG

VTTLF1 VTTLF2 VTTLF3

VTTLF

LVDS D TV/CRT

Compal Secret Data

Deciphered Date

U13 T13 U12 T12 U11 T11 U10 T10 U9 T9 U8 T8 U7 T7 U6 T6 U5 T5 V3 U3 V2 U2 T2 V1 U1

B22 B21 A21

BF21 BH20 BG20 BF20

K47

C35 B35 A35

V48 U48 V47 U47 U46

AH48 AF48 AH47 AG47

A8 L1 AB2

0.47U_0603_16V4Z

220u ESR 15m ohm Package(L*W*H)7.3*4.3*1.9 Rating 4V

+1.05VS

C138

C138 220U_D2_4VM_R15

220U_D2_4VM_R15

+1.05VS_AXF

C152

10U_0805_6.3V6M

+1.8V_TX_LVDS: 118.8mA (22UF*1, 1000PF*1)

VCC_HV: 105.3mA (0.1UF*1)

VCC_DMI: 456mA (0.1UF*1)

VTTLF_CAP1 VTTLF_CAP2 VTTLF_CAP3

C180

C181

0.47U_0603_16V4Z

+1.05VS +3VS

VTT: 852mA (270UF*1, 4.7UF*2, 2.2UF*1, 0.47UF*1)

C139

C140

4.7U_0805_10V4Z

2.2U_0603_6.3V6K

4.7U_0805_10V4Z

VCC_AXF: 321.35mA (10UF*1, 1UF*1)

C153

C153 1U_0402_6.3V4Z

1U_0402_6.3V4Z

+1.8V_SM_CK

C160

0.1U_0402_16V4Z

R129

PM@

0_0402_5%

+3VS

C170

0.1U_0402_16V4Z

+1.05VS_PEG: 1782mA (220UF*1, 22UF*1, 4.7UF*1)

C171

4.7U_0805_10V4Z

+1.05VS_DMI

C177

0.1U_0402_16V4Z

C182

0.47U_0603_16V4Z

2 1

CH751H-40PT_SOD323-2

2.2U_0603_6.3V6K

1 2

R122

R122 0_0603_5%

0_0603_5%

VCC_SM_CK: 124mA ( 10UF*1,0.1UF*1)

1 2

R125

R125 1_0402_1%

1_0402_1%

+1.8V_TX_LVDS

C168

GM@

1000P_0402_50V7K

+1.05VS_PEG

C172

10U_0805_10V4Z

R139

1 2

10_0603_5%

Title

Size Document Number Rev

Custom

Date: Sheet

220U_V_6.3VM_R15

1 2

R135

R135 0_0805_5%

0_0805_5%

CRB have reserved another filter for +VCC_DMI separated from +1.05VS_PEG, should we?

Compal Electronics, Inc.

Cantiga GMCH(6/7)-GTL

JHXXX M/B LA-4241P Schematic

C141

C145

0.47U_0603_16V4Z

Please check Power source if want support IAMT

+1.05VS

1uH 30%

1 2

L6 MBK1608121YZF_0603

MBK1608121YZF_0603

1 2

C161

C161 10U_0805_10V4Z

10U_0805_10V4Z

0.1uH 20%

1 2

L7 MBK1608121YZF_0603GM@L7 MBK1608121YZF_0603GM@

C169

GM@

10U_0805_10V4Z

CRB use 0.1uH, should we?

1 2

R733

R733 0_0805_5%

0_0805_5%

1 2

R130

R130 0_0805_5%

0_0805_5%

C173

+1.05VS_PEG

+1.8V

Please check Power source if want support IAMT

+1.05VS

220u ESR 15m ohm Package(L*W*H)7.3*6.6*5.9 Rating 6.3V

12 49Tuesday, June 03, 2008

0.4

hexainf@hotmail.com

U3I

AU48

VSS_1

AR48

VSS_2

AL48

VSS_3

BB47

VSS_4

AW47

VSS_5

AN47

VSS_6

AJ47

VSS_7

AF47

VSS_8

AD47

VSS_9

AB47

VSS_10

Y47

VSS_11

T47

BD46 BA46 AY46 AV46 AR46

AM46

BF44 AH44 AD44 AA44

BC43 AV43 AU43

AM43

BG42 AY42 AT42 AN42

AJ42

AE42

BD41 AU41

AM41

AH41 AD41 AA41

BG40 BB40 AV40 AN40

AT39

AM39

AJ39

AE39

BH38 BC38 BA38 AU38 AH38 AD38 AA38

BF37 BB37

AW37

AT37 AN37

AJ37

BG36 BD36 AK15 AU36

VSS_12

N47

VSS_13

L47

VSS_14

G47

VSS_15 VSS_16 VSS_17 VSS_18 VSS_19 VSS_20 VSS_21

V46

VSS_22

R46

VSS_23

P46

VSS_24

H46

VSS_25

F46

VSS_26 VSS_27 VSS_28 VSS_29 VSS_30

Y44

VSS_31

U44

VSS_32

T44

VSS_33

M44

VSS_34

F44

VSS_35 VSS_36 VSS_37 VSS_38 VSS_39

J43

VSS_40

C43

VSS_41 VSS_42 VSS_43 VSS_44 VSS_45 VSS_46 VSS_47

N42

VSS_48

L42

VSS_49 VSS_50 VSS_51 VSS_52 VSS_53 VSS_54 VSS_55

Y41

VSS_56

U41

VSS_57

T41

VSS_58

M41

VSS_59

G41

VSS_60

B41

VSS_61 VSS_62 VSS_63 VSS_64 VSS_65

H40

VSS_66

E40

VSS_67 VSS_68 VSS_69 VSS_70 VSS_71

N39

VSS_72

L39

VSS_73

B39

VSS_74 VSS_75 VSS_76 VSS_77 VSS_78 VSS_79 VSS_80 VSS_81

Y38

VSS_82

U38

VSS_83

T38

VSS_84

J38

VSS_85

F38

VSS_86

C38

VSS_87 VSS_88 VSS_89 VSS_90 VSS_91 VSS_92 VSS_93

H37

VSS_94

C37

VSS_95 VSS_96 VSS_97 VSS_98 VSS_99

VSS

CANTIGA ES_FCBGA1329GM@

D D

C C

B B

A A

VSS_100 VSS_101 VSS_102 VSS_103 VSS_104 VSS_105 VSS_106 VSS_107 VSS_108 VSS_109 VSS_110 VSS_111 VSS_112 VSS_113 VSS_114 VSS_115 VSS_116 VSS_117 VSS_118 VSS_119 VSS_120 VSS_121 VSS_122 VSS_123 VSS_124 VSS_125 VSS_126 VSS_127 VSS_128 VSS_129 VSS_130 VSS_131 VSS_132 VSS_133 VSS_134 VSS_135 VSS_136 VSS_137 VSS_138 VSS_139 VSS_140 VSS_141 VSS_142 VSS_143 VSS_144 VSS_145 VSS_146 VSS_147 VSS_148 VSS_149 VSS_150 VSS_151 VSS_152 VSS_153 VSS_154 VSS_155 VSS_156 VSS_157 VSS_158 VSS_159 VSS_160 VSS_161 VSS_162 VSS_163 VSS_164 VSS_165 VSS_166 VSS_167 VSS_168 VSS_169 VSS_170 VSS_171 VSS_172 VSS_173 VSS_174 VSS_175 VSS_176 VSS_177 VSS_178 VSS_179 VSS_180 VSS_181 VSS_182 VSS_183 VSS_184 VSS_185 VSS_186 VSS_187 VSS_188 VSS_189 VSS_190 VSS_191 VSS_192 VSS_193 VSS_194 VSS_195 VSS_196 VSS_197 VSS_198 VSS_199

AM36 AE36 P36 L36 J36 F36 B36 AH35 AA35 Y35 U35 T35 BF34 AM34 AJ34 AF34 AE34 W34 B34 A34 BG33 BC33 BA33 AV33 AR33 AL33 AH33 AB33 P33 L33 H33 N32 K32 F32 C32 A31 AN29 T29 N29 K29 H29 F29 A29 BG28 BD28 BA28 AV28 AT28 AR28 AJ28 AG28 AE28 AB28 Y28 P28 K28 H28 F28 C28 BF26 AH26 AF26 AB26 AA26 C26 B26 BH25 BD25 BB25 AV25 AR25 AJ25 AC25 Y25 N25 L25 J25 G25 E25 BF24 AD12 AY24 AT24 AJ24 AH24 AF24 AB24 R24 L24 K24 J24 G24 F24 E24 BH23 AG23 Y23 B23 A23 AJ6

U3J

BG21

VSS_199

L12

VSS_200

AW21

VSS_201

AU21

VSS_202

AP21

VSS_203

AN21

VSS_204

AH21

VSS_205

AF21

VSS_206

AB21

VSS_207

R21

VSS_208

M21

VSS_209

J21

VSS_210

G21

VSS_211

BC20

VSS_212

BA20

VSS_213

AW20

VSS_214

AT20

VSS_215

AJ20

VSS_216

AG20

VSS_217

Y20

VSS_218

N20

VSS_219

K20

VSS_220

F20

VSS_221

C20

VSS_222

A20

VSS_223

BG19

VSS_224

A18

VSS_225

BG17

VSS_226

BC17

VSS_227

AW17

VSS_228

AT17

VSS_229

R17

VSS_230

M17

VSS_231

H17

VSS_232

C17 BA16 AU16

AN16

BG15 AC15

W15

BG14 AA14

BG13 BC13 BA13

AN13

AJ13

AE13

BF12 AV12 AT12

AM12

AA12

BD11 BB11 AY11 AN11 AH11

BG10 AV10 AT10

AJ10 AE10 AA10

N16 G16

C14

N13 G13

N11 G11 C11

M10 BF9 BC9 AN9 AM9 AD9

BH8 BB8 AV8 AT8

VSS_233 VSS_235 VSS_237

VSS_238 VSS_239

K16

VSS_240 VSS_241

E16

VSS_242 VSS_243 VSS_244 VSS_245

A15

VSS_246 VSS_247 VSS_248 VSS_249 VSS_250 VSS_251 VSS_252

VSS_255 VSS_256 VSS_257 VSS_258

L13

VSS_259 VSS_260

E13

VSS_261 VSS_262 VSS_263 VSS_264 VSS_265 VSS_266

J12

VSS_267

A12

VSS_268 VSS_269 VSS_270 VSS_271 VSS_272 VSS_273

Y11

VSS_275 VSS_276 VSS_277 VSS_278 VSS_279 VSS_280 VSS_281 VSS_282 VSS_283 VSS_284 VSS_285 VSS_286 VSS_287 VSS_288 VSS_289 VSS_290

VSS_291

VSS_292 VSS_293 VSS_294 VSS_295 VSS_296

VSS

CANTIGA ES_FCBGA1329GM@

VSS NCTF

VSS_NCTF_1 VSS_NCTF_2 VSS_NCTF_3 VSS_NCTF_4 VSS_NCTF_5 VSS_NCTF_6 VSS_NCTF_7 VSS_NCTF_8

VSS_NCTF_9 VSS_NCTF_10 VSS_NCTF_11 VSS_NCTF_12 VSS_NCTF_13 VSS_NCTF_14 VSS_NCTF_15 VSS_NCTF_16

VSS_SCB_1 VSS_SCB_2 VSS_SCB_3 VSS_SCB_4 VSS_SCB_5

VSS SCB

VSS_297 VSS_298 VSS_299 VSS_300 VSS_301 VSS_302 VSS_303 VSS_304 VSS_305 VSS_306 VSS_307 VSS_308 VSS_309 VSS_310 VSS_311 VSS_312 VSS_313 VSS_314 VSS_315 VSS_316 VSS_317 VSS_318 VSS_319 VSS_320 VSS_321 VSS_322 VSS_323 VSS_324 VSS_325

VSS_327 VSS_328 VSS_329 VSS_330 VSS_331 VSS_332 VSS_333 VSS_334 VSS_335 VSS_336 VSS_337 VSS_338 VSS_339 VSS_340 VSS_341 VSS_342 VSS_343 VSS_344 VSS_345 VSS_346 VSS_347 VSS_348 VSS_349 VSS_350

VSS_351 VSS_352 VSS_353 VSS_354

NC_26 NC_27 NC_28 NC_29 NC_30 NC_31 NC_32 NC_33 NC_34 NC_35 NC_36 NC_37 NC_38 NC_39 NC_40 NC_41 NC_42

AH8 Y8 L8 E8 B8 AY7 AU7 AN7 AJ7 AE7 AA7 N7 J7 BG6 BD6 AV6 AT6 AM6 M6 C6 BA5 AH5 AD5 Y5 L5 J5 H5 F5 BE4

BC3 AV3 AL3 R3 P3 F3 BA2 AW2 AU2 AR2 AP2 AJ2 AH2 AF2 AE2 AD2 AC2 Y2 M2 K2 AM1 AA1 P1 H1

U24 U28 U25 U29

AF32 AB32 V32 AJ30 AM29 AF29 AB29 U26 U23 AL20 V20 AC19 AL17 AJ17 AA17 U17

BH48 BH1 A48 C1 A3

E1 D2 C3 B4 A5 A6 A43 A44 B45 C46 D47 B47 A46 F48 E48 C48 B48

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2007/08/18 2008/8/18

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

Cantiga GMCH(7/7)-GTL

JHXXX M/B LA-4241P Schematic

13 49Tuesday, June 03, 2008

0.4

+1.8V +1.8V

JDIMM1

+DIMM_VREF

DDRA_SDQ0 DDRA_SDQ1

DDRA_SDQS0#<9> DDRA_SDQS0<9>

D D

DDRA_SDQS1#<9> DDRA_SDQS1<9>

DDRA_SDQS2#<9> DDRA_SDQS2<9>

EC_TX_P80_DATA<15,32>

C C

EC_RX_P80_CLK<15,32>

B B

EC_RX_P80_CLK

A A

DDRA_CKE0<8>

DDRA_SBS2<9>

DDRA_SBS0<9> DDRA_SWE#<9>

DDRA_SCAS#<9> DDRA_SCS1#<8>

DDRA_ODT1<8>

DDRA_SDQS4#<9> DDRA_SDQS4<9>

R144 0_0402_5%R144 0_0402_5%

1 2

EC_RX_P80_CLK_R<15>

DDRA_SDQS6#<9> DDRA_SDQS6<9>

D_CK_SDATA<15,16> D_CK_SCLK<15,16>

+3VS

DDRA_SDQS0# DDRA_SDQS0

DDRA_SDQ2 DDRA_SDQ3

DDRA_SDQ8 DDRA_SDQ9

DDRA_SDQS1# DDRA_SDQS1

DDRA_SDQ10 DDRA_SDQ11

DDRA_SDQ16 DDRA_SDQ17

DDRA_SDQS2# DDRA_SDQS2

DDRA_SDQ18 DDRA_SDQ19

DDRA_SDQ24 DDRA_SDQ25

DDRA_SDM3 EC_TX_P80_DATA

DDRA_SDQ26 DDRA_SDQ27

DDRA_CKE0 EC_RX_P80_CLK

DDRA_SBS2 DDRA_SMA12

DDRA_SMA9 DDRA_SMA8

DDRA_SMA5 DDRA_SMA3 DDRA_SMA1

DDRA_SMA10 DDRA_SBS0 DDRA_SWE#

DDRA_SCAS# DDRA_SCS1#

DDRA_ODT1 DDRA_SDQ32

DDRA_SDQ33 DDRA_SDQS4#

DDRA_SDQS4 DDRA_SDQ34

DDRA_SDQ35 DDRA_SDQ40

DDRA_SDQ41 DDRA_SDM5 DDRA_SDQ42

DDRA_SDQ43 DDRA_SDQ48

DDRA_SDQ49

EC_RX_P80_CLK_R

DDRA_SDQS6# DDRA_SDQS6

DDRA_SDQ50 DDRA_SDQ51

DDRA_SDQ56 DDRA_SDQ57

DDRA_SDM7 DDRA_SDQ58

DDRA_SDQ59 D_CK_SDATA

D_CK_SCLK

+3VS

VREF

VSS

DQ0

DQ1

VSS

DQS0#

DQS0

VSS

DQ2

DQ3

VSS

DQ8

DQ9

VSS

DQS1#

DQS1

VSS

DQ10

DQ11

VSS

DQ16

DQ17

VSS

DQS2#

DQS2

VSS

DQ18

DQ19

VSS

DQ24

DQ25

VSS

DM3

VSS

DQ26

DQ27

VSS

CKE0

VDD

BA2

VDD

A12

VDD

101

103

VDD

105

A10/AP

107

BA0

109

WE#

111

VDD

113

CAS#

115

NC/S1#

117

VDD

119

NC/ODT1

121

VSS

123

DQ32

125

DQ33

127

VSS

129

DQS4#

131

DQS4

133

VSS

135

DQ34

137

DQ35

139

VSS

141

DQ40

143

DQ41

145

VSS

147

DM5

149

VSS

151

DQ42

153

DQ43

155

VSS

157

DQ48

159

DQ49

161

VSS

163

NC,TEST

165

VSS

167

DQS6#

169

DQS6

171

VSS

173

DQ50

175

DQ51

177

VSS

179

DQ56

181

DQ57

183

VSS

185

DM7

187

VSS

189

DQ58

191

DQ59

193

VSS

195

SDA

197

SCL

199

VDDSPD

FOX_ASOA426-M2RN-7F

CONN@

DQ4 DQ5

DM0 DQ6

DQ7

DQ12 DQ13

DM1

CK0#

DQ14 DQ15

DQ20 DQ21

DM2

DQ22 DQ23

DQ28 DQ29

DQS3#

DQS3 DQ30

DQ31

NC/CKE1

VDD NC/A15 NC/A14

VDD

RAS#

VDD

ODT0

NC/A13

VDD

DQ36 DQ37

DM4

DQ38 DQ39

DQ44 DQ45

DQS5#

DQS5 DQ46

DQ47 DQ52

DQ53

CK1#

DM6

DQ54 DQ55

DQ60 DQ61

DQS7#

DQS7 DQ62

DQ63

VSS

VSS VSS

VSS

VSS VSS

CK0 VSS

VSS

BA1

VSS

VSS VSS

VSS

VSS CK1

VSS VSS

VSS

VSS SA0 SA1

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40

42 44 46 48 50

52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90

A11

96 98

100

102

104 106 108 110

S0#

112 114 116 118 120

122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200

DIMM1 STD H:5.2mm (BOT)

C215

C214

0.1U_0402_16V4Z

2.2U_0603_6.3V6K

12/22 Change from 0805 to 0603 (IFTXX)

11/12 Change to HEL80's

DDRA_SDQ4 DDRA_SDQ5

DDRA_SDM0 DDRA_SDQ6

DDRA_SDQ7 DDRA_SDQ12

DDRA_SDQ13 DDRA_SDM1

DDRA_CLK0 <8>

1 2

DDRA_CLK0# <8>

DDRA_SDQS3# <9> DDRA_SDQS3 <9>

DDRA_CKE1 <8>

DDRA_SBS1 <9> DDRA_SRAS# <9> DDRA_SCS0# <8>

DDRA_ODT0 <8>

DDRA_SDQS5# <9> DDRA_SDQS5 <9>

DDRA_CLK1 <8> DDRA_CLK1# <8>

DDRA_SDQS7# <9> DDRA_SDQS7 <9>

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

DDRA_SDQ14 DDRA_SDQ15

DDRA_SDQ20 DDRA_SDQ21

R143 0_0402_5%R143 0_0402_5%

DDRA_SDM2 DDRA_SDQ22

DDRA_SDQ23 DDRA_SDQ28

DDRA_SDQ29 DDRA_SDQS3#

DDRA_SDQS3 DDRA_SDQ30

DDRA_SDQ31 DDRA_CKE1

DDRA_SMA14 DDRA_SMA11

DDRA_SMA7 DDRA_SMA6

DDRA_SMA4 DDRA_SMA2 DDRA_SMA0

DDRA_SBS1 DDRA_SRAS# DDRA_SCS0#

DDRA_ODT0 DDRA_SMA13

DDRA_SDQ36 DDRA_SDQ37

DDRA_SDM4 DDRA_SDQ38

DDRA_SDQ39 DDRA_SDQ44

DDRA_SDQ45 DDRA_SDQS5#

DDRA_SDQS5 DDRA_SDQ46

DDRA_SDQ47 DDRA_SDQ52

DDRA_SDQ53

DDRA_SDM6 DDRA_SDQ54

DDRA_SDQ55 DDRA_SDQ60

DDRA_SDQ61 DDRA_SDQS7#

DDRA_SDQS7 DDRA_SDQ62

DDRA_SDQ63

R146 10K_0402_5%R146 10K_0402_5%

1 2

R147 10K_0402_5%R147 10K_0402_5%

1 2

PM_EXTTS#0 <8>

Issued Date

+1.8V

R141

+DIMM_VREF

20mils

C189

C188

0.1U_0402_16V4Z

2.2U_0603_6.3V6K

DDRA_SMA[0..14]<9> DDRA_SDQ[0..63]<9> DDRA_SDM[0..7]<9>

DDRA_CKE0 DDRA_SBS2

RP1 56_0404_4P2R_5%RP1 56_0404_4P2R_5%

DDRA_SMA12 DDRA_SMA9

RP2 56_0404_4P2R_5%RP2 56_0404_4P2R_5%

DDRA_SMA8 DDRA_SMA5

RP3 56_0404_4P2R_5%RP3 56_0404_4P2R_5%

DDRA_SMA3 DDRA_SMA1

RP4 56_0404_4P2R_5%RP4 56_0404_4P2R_5%

DDRA_SMA10 DDRA_SBS0

RP5 56_0404_4P2R_5%RP5 56_0404_4P2R_5%

DDRA_SWE# DDRA_SCAS#

RP6 56_0404_4P2R_5%RP6 56_0404_4P2R_5%

DDRA_SCS1# DDRA_ODT1

RP7 56_0404_4P2R_5%RP7 56_0404_4P2R_5%

DDRA_SMA11 DDRA_SMA14

RP8 56_0404_4P2R_5%RP8 56_0404_4P2R_5%

DDRA_SMA6 DDRA_SMA7

RP9 56_0404_4P2R_5%RP9 56_0404_4P2R_5%

DDRA_SMA2 DDRA_SMA4

RP10 56_0404_4P2R_5%RP10 56_0404_4P2R_5%

DDRA_SBS1 DDRA_SMA0

RP11 56_0404_4P2R_5%RP11 56_0404_4P2R_5%

DDRA_SCS0# DDRA_SRAS#

RP12 56_0404_4P2R_5%RP12 56_0404_4P2R_5%

DDRA_SMA13 DDRA_ODT0

RP13 56_0404_4P2R_5%RP13 56_0404_4P2R_5%

DDRA_CKE1

R145 56_0402_5%R145 56_0402_5%

Layout Note: Place these resistor closely JP35,all trace length Max=1.5"

2007/08/18 2008/8/18

DDRA_SMA[0..14] DDRA_SDQ[0..63] DDRA_SDM[0..7]

1 4 2 3

1 2

Compal Secret Data

Deciphered Date

R141

1K_0402_1%

R142

1K_0402_1%

+0.9VS

C190

C190 220P_0402_50V7K

220P_0402_50V7K

+1.8V

C191

2.2U_0603_6.3V6K

+1.8V

C197

0.1U_0402_16V4Z

+0.9VS

C201

0.1U_0402_16V4Z

+0.9VS

C206

0.1U_0402_16V4Z

+0.9VS

C211

0.1U_0402_16V4Z

Layout Note: Place one cap close to every 2 pullup resistors terminated to +0.9VS

+DIMM_VREF

C192

2.2U_0603_6.3V6K

C198

0.1U_0402_16V4Z

C202

0.1U_0402_16V4Z

C207

0.1U_0402_16V4Z

C212

0.1U_0402_16V4Z

Title

Size Document Number Rev

Date: Sheet

330u ESR 15m ohm Package(L*W*H)7.3*4.3*1.8 Rating 2.5V

Layout Note: Place near JP34

C195

C193

2.2U_0603_6.3V6K

C194

2.2U_0603_6.3V6K

C199

0.1U_0402_16V4Z

C203

0.1U_0402_16V4Z

C208

0.1U_0402_16V4Z

C213

0.1U_0402_16V4Z

Compal Electronics, Inc.

JHXXX M/B LA-4241P Schematic

C195

2.2U_0603_6.3V6K

C200

0.1U_0402_16V4Z

C204

0.1U_0402_16V4Z

C209

0.1U_0402_16V4Z

C702

0.1U_0402_16V4Z

DDRII-SODIMM1

C196

330U_D2E_2.5VM

C205

0.1U_0402_16V4Z

C210

0.1U_0402_16V4Z

14 49Wednesday, May 28, 2008

0.4

hexainf@hotmail.com

11/12 Change DIMM1 as HEL80's

JDIMM2

+DIMM_VREF

DDRB_SDQ0 DDRB_SDQ1

1 1

2 2

3 3

4 4

EC_TX_P80_DATA<14,32>

EC_RX_P80_CLK<14,32>

EC_RX_P80_CLK_R<14>

DDRB_SDQS0#<9> DDRB_SDQS0<9>

DDRB_SDQS1#<9> DDRB_SDQS1<9>

DDRB_SDQS2#<9> DDRB_SDQS2<9>

DDRB_CKE0<8>

DDRB_SBS2<9>

DDRB_SBS0<9> DDRB_SWE#<9>

DDRB_SCAS#<9> DDRB_SCS1#<8>

DDRB_ODT1<8>

DDRB_SDQS4#<9> DDRB_SDQS4<9>

DDRB_SDQS6#<9> DDRB_SDQS6<9>

D_CK_SDATA<14,16> D_CK_SCLK<14,16>

DDRB_SDQS0# DDRB_SDQS0

DDRB_SDQ2 DDRB_SDQ3

DDRB_SDQ8 DDRB_SDQ9

DDRB_SDQS1# DDRB_SDQS1

DDRB_SDQ10 DDRB_SDQ11

DDRB_SDQ16

DDRB_SDQS2# DDRB_SDQS2

DDRB_SDQ18 DDRB_SDQ19

DDRB_SDQ24 DDRB_SDQ25

DDRB_SDM3 EC_TX_P80_DATA

DDRB_SDQ26 DDRB_SDQ30 DDRB_SDQ27

DDRB_CKE0 EC_RX_P80_CLK

DDRB_SBS2 DDRB_SMA12

DDRB_SMA9 DDRB_SMA8

DDRB_SMA5 DDRB_SMA3 DDRB_SMA1

DDRB_SMA10 DDRB_SBS0 DDRB_SWE#

DDRB_SCAS# DDRB_SCS1#

DDRB_ODT1 DDRB_SDQ32

DDRB_SDQ33 DDRB_SDQS4#

DDRB_SDQS4 DDRB_SDQ34

DDRB_SDQ35 DDRB_SDQ40

DDRB_SDQ41 DDRB_SDM5 DDRB_SDQ42

DDRB_SDQ43 DDRB_SDQ48

DDRB_SDQ49

EC_RX_P80_CLK_R

DDRB_SDQS6# DDRB_SDQS6

DDRB_SDQ50 DDRB_SDQ51

DDRB_SDQ56

DDRB_SDM7 DDRB_SDQ58

DDRB_SDQ59 D_CK_SDATA

D_CK_SCLK

+3VS

VREF

VSS

DQ0

DQ1

VSS

DQS0#

DQS0

VSS

DQ2

DQ3

VSS

DQ8

DQ9

VSS

DQS1#

DQS1

VSS

DQ10

DQ11

VSS

DQ16

DQ17

VSS

DQS2#

DQS2

VSS

DQ18

DQ19

VSS

DQ24

DQ25

VSS

DM3

VSS

DQ26

DQ27

VSS

CKE0

VDD

BA2

VDD

A12

VDD

101

103

VDD

105

A10/AP

107

BA0

109

WE#

111

VDD

113

CAS#

115

NC/S1#

117

VDD

119

NC/ODT1

121

VSS

123

DQ32

125

DQ33

127

VSS

129

DQS4#

131

DQS4

133

VSS

135

DQ34

137

DQ35

139

VSS

141

DQ40

143

DQ41

145

VSS

147

DM5

149

VSS

151

DQ42

153

DQ43

155

VSS

157

DQ48

159

DQ49

161

VSS

163

NC,TEST

165

VSS

167

DQS6#

169

DQS6

171

VSS

173

DQ50

175

DQ51

177

VSS

179

DQ56

181

DQ57

183

VSS

185

DM7

187

VSS

189

DQ58

191

DQ59

193

VSS

195

SDA

197

SCL

199

VDDSPD

P-TWO_A5692B-A0G16-P

CONN@

Change PCB Footprint

DQS3#

NC/CKE1

NC/A15 NC/A14

NC/A13

DQS5#

DQS7#

DIMM2 STD H:9.2mm (BOT)

VSS DQ4 DQ5

VSS DM0

VSS DQ6 DQ7

VSS

DQ12 DQ13

VSS DM1

VSS

CK0

CK0#

VSS

DQ14 DQ15

VSS

DQ20 DQ21

VSS DM2

VSS

DQ22 DQ23

VSS

DQ28 DQ29

VSS

DQS3

VSS

DQ30 DQ31

VSS VDD

VDD

BA1

RAS#

VDD

ODT0

VDD

VSS

DQ36 DQ37

VSS DM4

VSS

DQ38 DQ39

VSS

DQ44 DQ45

VSS

DQS5

VSS

DQ46 DQ47

VSS

DQ52 DQ53

VSS

CK1

CK1#

VSS DM6

VSS

DQ54 DQ55

VSS

DQ60 DQ61

VSS

DQS7

VSS

DQ62 DQ63

VSS SAO

SA1

+1.8V+1.8V

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40

42 44 46 48 50

52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90

A11

96 98

100

102

104 106 108 110

S0#

112 114 116 118 120

122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200

DDRB_SDQ4 DDRB_SDQ5

DDRB_SDM0 DDRB_SDQ6

DDRB_SDQ7 DDRB_SDQ12

DDRB_SDQ13 DDRB_SDM1

DDRB_SDQ14 DDRB_SDQ15

DDRB_SDQ20 DDRB_SDQ21DDRB_SDQ17

DDRB_SDM2 DDRB_SDQ22

DDRB_SDQ23 DDRB_SDQ28

DDRB_SDQ29 DDRB_SDQS3#

DDRB_SDQS3

DDRB_SDQ31 DDRB_CKE1

DDRB_SMA14 DDRB_SMA11

DDRB_SMA7 DDRB_SMA6

DDRB_SMA4 DDRB_SMA2 DDRB_SMA0

DDRB_SBS1 DDRB_SRAS# DDRB_SCS0#

DDRB_ODT0 DDRB_SMA13

DDRB_SDQ36 DDRB_SDQ37

DDRB_SDM4 DDRB_SDQ38

DDRB_SDQ39 DDRB_SDQ44

DDRB_SDQ45 DDRB_SDQS5#

DDRB_SDQS5 DDRB_SDQ46

DDRB_SDQ47 DDRB_SDQ52

DDRB_SDQ53

DDRB_SDM6 DDRB_SDQ54

DDRB_SDQ55 DDRB_SDQ60

DDRB_SDQ61DDRB_SDQ57 DDRB_SDQS7#

DDRB_SDQS7 DDRB_SDQ62

DDRB_SDQ63

R150 10K_0402_5%R150 10K_0402_5%

1 2

R151 10K_0402_5%R151 10K_0402_5%

1 2

R148

0_0402_5%

1 2

DDRB_SMA[0..14]<9> DDRB_SDQ[0..63]<9> DDRB_SDM[0..7]<9>

DDRB_CLK0 <8> DDRB_CLK0# <8>

PM_EXTTS#1 <8>

DDRB_SDQS3# <9> DDRB_SDQS3 <9>

DDRB_CKE1 <8>

DDRB_SBS1 <9> DDRB_SRAS# <9> DDRB_SCS0# <8>

DDRB_ODT0 <8>

DDRB_SDQS5# <9> DDRB_SDQS5 <9>

DDRB_CLK1 <8> DDRB_CLK1# <8>

DDRB_SDQS7# <9> DDRB_SDQS7 <9>

+3VS

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2007/08/18 2008/8/18

DDRB_CKE0 DDRB_SBS2

DDRB_SMA12 DDRB_SMA9

DDRB_SMA8 DDRB_SMA5

DDRB_SMA3 DDRB_SMA1

DDRB_SMA10 DDRB_SBS0

DDRB_SWE# DDRB_SCAS#

DDRB_SCS1# DDRB_ODT1

DDRB_SMA11 DDRB_SMA14

DDRB_SMA6 DDRB_SMA7

DDRB_SMA2 DDRB_SMA4

DDRB_SBS1 DDRB_SMA0

DDRB_SCS0# DDRB_SRAS#

DDRB_SMA13 DDRB_ODT0

DDRB_CKE1

Layout Note: Place these resistor closely JP35,all trace length Max=1.5"

Compal Secret Data

Deciphered Date

DDRB_SMA[0..14] DDRB_SDQ[0..63] DDRB_SDM[0..7]

1 4 2 3

RP14 56_0404_4P2R_5%RP14 56_0404_4P2R_5%

1 4 2 3

RP15 56_0404_4P2R_5%RP15 56_0404_4P2R_5%

1 4 2 3

RP16 56_0404_4P2R_5%RP16 56_0404_4P2R_5%

1 4 2 3

RP17 56_0404_4P2R_5%RP17 56_0404_4P2R_5%

1 4 2 3

RP18 56_0404_4P2R_5%RP18 56_0404_4P2R_5%

1 4 2 3

RP19 56_0404_4P2R_5%RP19 56_0404_4P2R_5%

1 4 2 3

RP20 56_0404_4P2R_5%RP20 56_0404_4P2R_5%

1 4 2 3

RP21 56_0404_4P2R_5%RP21 56_0404_4P2R_5%

1 4 2 3

RP22 56_0404_4P2R_5%RP22 56_0404_4P2R_5%

1 4 2 3

RP23 56_0404_4P2R_5%RP23 56_0404_4P2R_5%

1 4 2 3

RP24 56_0404_4P2R_5%RP24 56_0404_4P2R_5%

1 4 2 3

RP25 56_0404_4P2R_5%RP25 56_0404_4P2R_5%

1 4 2 3

RP26 56_0404_4P2R_5%RP26 56_0404_4P2R_5%

1 2

R149 56_0402_5%R149 56_0402_5%

+0.9VS

+DIMM_VREF

C216

2.2U_0603_6.3V6K

+1.8V

C218

C219

2.2U_0603_6.3V6K

+1.8V

C224

C225

0.1U_0402_16V4Z

+0.9VS

C229

C228

0.1U_0402_16V4Z

+0.9VS

C233

C234

0.1U_0402_16V4Z

+0.9VS

C239

C238

0.1U_0402_16V4Z

Layout Note: Place one cap close to every 2 pullup resistors terminated to +0.9VS

Title

Size Document Number Rev

Date: Sheet

C217

0.1U_0402_16V4Z

330u ESR 15m ohm Package(L*W*H)7.3*4.3*1.8 Rating 2.5V

Layout Note: Place near JP35

C222

C221

C227

C231

C236

C222

2.2U_0603_6.3V6K

C232

0.1U_0402_16V4Z

C237

0.1U_0402_16V4Z

C220

2.2U_0603_6.3V6K

C226

0.1U_0402_16V4Z

C230

0.1U_0402_16V4Z

JHXXX M/B LA-4241P Schematic

0.1U_0402_16V4Z

C235

0.1U_0402_16V4Z

C240

0.1U_0402_16V4Z

Compal Electronics, Inc.

DDRII-SODIMM2

C223

330U_D2E_2.5VM

15 49Wednesday, May 28, 2008

0.4

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