Compal LA-4232P, Vostro 1320 Schematic

KAL80

LA-4232P

Model Name:

PCB NO:

1 1

BOM P/N:

Half Penny Bridge 13.3

2 2

Compal Confidential

Schematic Document

Cantiga + ICH9

2009 / 06 / 01

3 3

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev:1.0(A00)

Compal Secret Data

2007/1/15 2008/1/15

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, M/B LA-4232P

401593

148Saturday, June 06, 2009

Compal confidential

Half Penny Bridge 13.3

File Name : LA-4232P

ZZZ1

PCB

1 1

2 2

CRT

+CRT_VCC

LVDS Panel Interface

+LCDVDD +3VS B+

P.16

VRAM x 2

+1.8VS

Thermal Sensor ADT7421ARMZ

+3VS

Fan conn

+5VS

nVidia NB9M-GS

+1.8VS +VGA_CORE +1.1V_GFX_PCIE +3VS

P.31,32,33,34P.35

P.4

PCI-E BUS

Penryn -4MB (Socket P)

uFCPGA-478 CPU

+CPU_CORE +VCCP +1.5VS

H_A#(3..35) H_D#(0..63)

Intel Cantiga MCH

+3VS_DAC_CRT +3VS_DAC_BG

+1.05VS_DPLLA

+1.05VS_DPLLB

+VCCP

+1.8V_TXLVDS

DMI X4

1329pin BGA

P.7,8,9,10,11,12

Intel ICH9-M

+RTCVCC

+1.5VS +VCCP

+3VALW

676pin BGA

P.17,18,19,20

P.4,5,6

FSB

800/1066 MHz 1.05V

C-Link

DDR2 667/800MHz 1.8V

Dual Channel

USB2.0

Azalia

SATA 0 SATA 1

DDR2-SO-DIMM X2

BANK 0, 1, 2, 3

+1.8V

+0.9VS

P.13,14

USB conn x 4

+5VALW

FingerPrinter

+3VS

Felica Conn

+5VS

BT Conn

+3VS

Camera

+5VS +3VS

P.29

CK505

Clock Generator CS9LPRS387BKLFT

+1.05VS_CK505 +3VS_CK505

P.29

SM IC -72

P.15

10/100/1000 LAN

REALTEK RTL8111DL

3 3

+LAN_IO

P.21

Mini-Card-1 (WLAN)

+1.5VS +3VS

P.23

CardBus Controller O2MICRO OZ888

+1.8VS_CB +3VS_PHY

1394

P.30

Media Card

+3VS_CR

RJ45/11 CONN

Mini-Card-2 (WLAN)

+1.5VS +3VS

P.23

Express Card

P.26

LPC

LPC BUS

ENE KB926

+3VALW

+EC_AVCC

LPC

P.27

TPM SLB 9635

+3VS

P.28

Express Card

+3VS +1.5VS

Mini-Card-1

+1.5VS +3VS

Audio CODEC 92HD81

+3VS +5VS

P.26

P.23

Digital Mic

P.24 P.24

Audio Jack

P.24

SATA HDD Connector

Power On/Off CKT.

P.28

4 4

Touch Pad CONN. Int.KBD

+5VS

BIOS(System/EC)

+3VALW

P.27P.28P.28

+5VS

CDROM Conn.

+5VS

P.22

DC/DC Interface CKT.

+5VS

Power Circuit DC/DC

P.36

P.36~P.45

RTC CKT.

+RTCVCC

P.39

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2007/1/15 2008/1/15

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, M/B LA-4232P

401593

248Saturday, June 06, 2009

Voltage Rails

O MEANS ON X MEANS OFF

Symbol Note :

: means Digital Ground

+5VS

+3VS

power plane

State

S5 S4/AC

S5 S4/ Battery only

S5 S4/AC & Battery don't exist

1 1

+5VALW

+3VALW

XX X

USB PORT#

0 1 2 3

JUSBP1 CAMERA JUSBP3(SINGLE) Felica

+1.8V

DESTINATION

+1.5VS

+0.9V

+VCCP

+CPU_CORE

+VGA_CORE

+1.8VS

+1.1VS

+0.9VGA

PCI EXPRESS

Lane 1 Lane 2 Lane 3 Lane 4 Lane 5 Lane 6

SMBUS Control Table

SMB_EC_CK1 SMB_EC_DA1

SMB_EC_CK2 SMB_EC_DA2

SMB_CK_CLK1 SMB_CK_DAT1 ICH9

LCD_CLK LCD_DAT

DESTINATION

GLAN RTL8111DL

MINI CARD-2 WLAN EXPRESS CARD CARD READER OZ888 NA

SOURCE

KB926

Cantiga

: means Analog Ground

@ : means just reserve , no build CONN@: connect VGA@: discrete component UMA@: uma component TPM@: TPM compoent

INVERTER BATT EEPROM

X X

X XX

SERIAL SENSOR

XX X

X XX

SATA

Lane 0 Lane 1 Lane 4 Lane 5 NA

THERMAL (CPU)

SODIMM CLK CHIP

DESTINATION HDD ODD NA

MINI CARD

X X

XX X

X X

LCD

X X

ICH9-M

4 5 6 7

9 10 11

Blue Tooth Finger Printer JMINI2-WLAN Express card JUSBP3(DUEL TOP)8 JUSBP3(DUEL BOTTOM) NA NA

I2C / SMBUS ADDRESSING

DEVICE

DDR SO-DIMM 0 DDR SO-DIMM 1 CLOCK GENERATOR (EXT.)

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2005/03/10 2006/03/10

HEX

Compal Secret Data

Deciphered Date

ADDRESS

1 0 1 0 0 0 0 0 1 0 1 0 0 1 0 0A4 1 1 0 1 0 0 1 0

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, M/B LA-4232P

401593

348Saturday, June 06, 2009

XDP_TDI

D D

CONN@

H_A#[3..16]7

H_ADSTB#07 H_REQ#07

H_REQ#17 H_REQ#27 H_REQ#37 H_REQ#47

C C

B B

A A

H_A#[17..35]7

H_ADSTB#17 H_A20M#18

H_FERR#18 H_IGNNE#18

H_STPCLK#18 H_INTR18 H_NMI18 H_SMI#18

+VCCP

H_PROCHOT# OCP#

H_IERR#

3 1

MMBT3904_SOT23

+VCCP

@ R17

R17 56_0402_5%

56_0402_5%

R18

R18 56_0402_5%

56_0402_5%

1 2

H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16 H_ADSTB#0

H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4

H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 H_A#32 H_A#33 H_A#34 H_A#35 H_ADSTB#1

H_A20M# H_FERR# H_IGNNE#

H_STPCLK# H_INTR H_NMI H_SMI#

CONN@ JCPU1A

JCPU1A J4 L5 L4 K5

N2 J1 N3 P5 P2 L2 P4 P1 R1

K3 H2 K2 J3 L1

Y2 U5 R3

U4 Y5 U1 R4 T5 T3

W2 W5

Y4 U2 V4

W3 AA4 AB2 AA3

V1 A6

A5 C4

D5 C6 B4 A3

N5 T2 V3 B2 D2

D22

D3 F6

Penryn

OCP# 19

ADDR GROUP_0

A[3]# A[4]# A[5]# A[6]# A[7]# A[8]# A[9]# A[10]# A[11]# A[12]# A[13]# A[14]# A[15]# A[16]# ADSTB[0]#

REQ[0]# REQ[1]# REQ[2]# REQ[3]# REQ[4]#

A[17]# A[18]#

ADDR GROUP_1

A[19]# A[20]# A[21]# A[22]# A[23]# A[24]# A[25]# A[26]# A[27]# A[28]# A[29]# A[30]# A[31]# A[32]# A[33]# A[34]# A[35]# ADSTB[1]#

A20M# FERR# IGNNE#

STPCLK# LINT0 LINT1 SMI#

RSVD[01] RSVD[02] RSVD[03] RSVD[04] RSVD[05] RSVD[06] RSVD[07] RSVD[08] RSVD[09]

XDP/ITP SIGNALS

THERMAL

PROCHOT#

THERMDA THERMDC

ICH

THERMTRIP#

H CLK

RESERVED

ADS# BNR#

BPRI#

DEFER#

DRDY# DBSY#

BR0#

IERR#

INIT#

LOCK#

CONTROL

RESET#

RS[0]# RS[1]# RS[2]#

TRDY#

HIT#

HITM#

BPM[0]# BPM[1]# BPM[2]# BPM[3]#

PRDY# PREQ#

TCK

TDI TDO TMS

TRST#

DBR#

BCLK[0] BCLK[1]

H1 E2 G5

H5 F21 E1

F1 D20

B3 H4 C1

F3 F4 G3 G2

G6 E4

AD4 AD3 AD1 AC4 AC2 AC1 AC5 AA6 AB3 AB5 AB6 C20

D21 A24 B25

A22 A21

H_ADS# H_BNR# H_BPRI#

H_DEFER# H_DRDY# H_DBSY#

H_BR0# H_IERR#

H_INIT# H_LOCK# H_RESET#

H_RS#0 H_RS#1 H_RS#2 H_TRDY#

H_HIT# H_HITM#

XDP_TCK XDP_TDI XDP_TDO XDP_TMS XDP_TRST# XDP_DBRESET#

H_PROCHOT#

H_THERMDC_R H_THERMTRIP#

CLK_CPU_BCLK CLK_CPU_BCLK#

H_ADS# 7 H_BNR# 7 H_BPRI# 7

H_DEFER# 7 H_DRDY# 7 H_DBSY# 7

H_BR0# 7

H_INIT# 18

H_LOCK# 7 H_RESET# 7

H_RS#0 7 H_RS#1 7 H_RS#2 7 H_TRDY# 7

H_HIT# 7 H_HITM# 7

T84T84

XDP_DBRESET# 19

R146 68_0402_1%

R146 68_0402_1% R57 100_0402_5%R57 100_0402_5%

R53 100_0402_5%R53 100_0402_5%

H_THERMTRIP# 7,18

CLK_CPU_BCLK 15 CLK_CPU_BCLK# 15

1 2 1 2

H_THERMDA, H_THERMDC routing together, Trace width / Spacing = 10 / 10 mil

+3VS

C13

0.1U_0402_16V

+VCCP

H_THERMDAH_THERMDA_R H_THERMDC

+3VS

1 2

R16

1 2

10K_0402_5%

H_THERMDA H_THERMDC

2200P_0402_50V7K

L_THERM#

FAN Control circuit

C94

EN_DFAN1

+3VS

10K_0402_5%

EN_DFAN127

FAN_SPEED127

0.01U_0402_16V7K

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2006/02/13 2006/03/10

Compal Secret Data

Deciphered Date

Thermal Sensor EMC1402-1-ACZL-TR

VDD

D+

DTHERM#4GND

EMC1402-2-ACZL-TR MSOP 8P

Address:100_11000

R61

XDP_TMS

XDP_TRST# XDP_TCK

SCLK

SDATA

ALERT#

C76

10U_1206_16V4Z~N

C88

1000P_0402_50V7K~N

FAN1_POWER

FAN_SPEED1

D4 PJSOT24C_SOT23-3

PJSOT24C_SOT23-3 @

Title

Size Document Number Rev

Custom

Date: Sheet

R5 54.9_0402_1%R5 54.9_0402_1%

1 2

R4 54.9_0402_1%R4 54.9_0402_1%

1 2

R11 54.9_0402_1%R11 54.9_0402_1%

1 2

R35 54.9_0402_1%R35 54.9_0402_1%

1 2

This shall place near CPU

EC_SMB_CK2

EC_SMB_DA2

7 6 5

+5VS

1 2

C77 10U_1206_16V4Z~NC77 10U_1206_16V4Z~N U3

VEN VIN VO VSET

RT9027BPS SO 8P

JFAN1

1 2 3

GND GND

GND GND GND GND

40mil

2 3 4

1 2 3

4 5

ACES_85205-03001

ACES_85205-03001 conn@

conn@

FAN1

Compal Electronics, Inc.

SCHEMATIC, M/B LA-4232P

401593

EC_SMB_CK2 16,27,31

EC_SMB_DA2 16,27,31

8 7 6 5

+VCCP

448Saturday, June 06, 2009

H_D#[0..15]7

D D

H_DSTBN#07 H_DSTBP#07 H_DINV#07 H_D#[16..31]7

C C

H_DSTBN#17 H_DSTBP#17 H_DINV#17

T50T50 T23T23 T2T2 T3T3 T4T4 T5T5

T6T6 CPU_BSEL015 CPU_BSEL115 CPU_BSEL215

H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 H_DSTBN#0 H_DSTBP#0 H_DINV#0

H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31 H_DSTBN#1 H_DSTBP#1 H_DINV#1

+V_CPU_GTLREF

TEST1 TEST2 TEST3 TEST4 TEST5 TEST6 TEST7 CPU_BSEL0 CPU_BSEL1 CPU_BSEL2

layout note: Rout H_DPRSTP# from ICH9 to IMVP6 then to GMCH & CPU

layout note: Route TEST3 & TEST5 traces on ground referenced layer to the TPs

CPU_BSEL CPU_BSEL2 CPU_BSEL1

B B

166

200

266 0 0 0

CONN@

CONN@ JCPU1B

JCPU1B E22 F24 E26

G22

F23

G25

E25 E23 K24

G24

J24 J23 H22 F26 K22 H23 J26

H26 H25

N22 K25 P26 R23 L23

M24

L22

M23

P25 P23 P22 T24

R24

L25 T25

N25

L26

M26 N24

AD26

C23 D25 C24

AF26

AF1

A26

C3 B22 B23

C21

Penryn

CPU_BSEL0

D[0]# D[1]# D[2]# D[3]# D[4]# D[5]# D[6]# D[7]# D[8]# D[9]# D[10]# D[11]# D[12]# D[13]# D[14]# D[15]# DSTBN[0]# DSTBP[0]# DINV[0]#

D[16]# D[17]# D[18]# D[19]# D[20]# D[21]# D[22]# D[23]# D[24]# D[25]# D[26]# D[27]# D[28]# D[29]# D[30]# D[31]# DSTBN[1]# DSTBP[1]# DINV[1]#

GTLREF TEST1 TEST2 TEST3 TEST4 TEST5 TEST6 TEST7 BSEL[0] BSEL[1] BSEL[2]

DATA GRP 0

DATA GRP 1

MISC

PWRGOOD

D[32]# D[33]# D[34]# D[35]# D[36]# D[37]# D[38]# D[39]# D[40]#

DATA GRP 2DATA GRP 3

D[41]# D[42]# D[43]# D[44]# D[45]# D[46]#

D[47]# DSTBN[2]# DSTBP[2]#

DINV[2]#

D[48]#

D[49]#

D[50]#

D[51]#

D[52]#

D[53]#

D[54]#

D[55]#

D[56]#

D[57]#

D[58]#

D[59]#

D[60]#

D[61]#

D[62]#

D[63]# DSTBN[3]# DSTBP[3]#

DINV[3]# COMP[0]

COMP[1] COMP[2] COMP[3]

DPRSTP#

DPSLP# DPWR#

SLP#

PSI#

Y22 AB24 V24 V26 V23 T22 U25 U23 Y25 W22 Y23 W24 W25 AA23 AA24 AB25 Y26 AA26 U22

AE24 AD24 AA21 AB22 AB21 AC26 AD20 AE22 AF23 AC25 AE21 AD21 AC22 AD23 AF22 AC23 AE25 AF24 AC20

R26 U26 AA1 Y1

E5 B5 D24 D6 D7 AE6

+V_CPU_GTLREF

H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 H_DSTBN#2 H_DSTBP#2 H_DINV#2

H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63 H_DSTBN#3 H_DSTBP#3 H_DINV#3

COMP0 COMP1 COMP2 COMP3

H_DPRSTP# H_DPSLP# H_DPWR# H_PWRGOOD H_CPUSLP# H_PSI#

+VCCP

R27

R27 1K_0402_1%

1K_0402_1%

R29

R29 2K_0402_1%

2K_0402_1%

H_D#[32..47] 7

H_DSTBN#2 7 H_DSTBP#2 7 H_DINV#2 7 H_D#[48..63] 7

H_DSTBN#3 7 H_DSTBP#3 7 H_DINV#3 7

H_DPRSTP# 7,18,44 H_DPSLP# 18

H_DPWR# 7

H_PWRGOOD 18 H_CPUSLP# 7

H_PSI# 44

R24

R23

R23 12

54.9_0402_1%

Resistor placed within

0.5" of CPU pin.Trace should be at least 25 mils away from any other toggling signal. COMP[0,2] trace width is 21 mils. COMP[1,3] trace width is 5

27.4_0402_1%

54.9_0402_1%

R25

R25 12

27.4_0402_1%

+CPU_CORE +CPU_CORE

R26

R26 12

CONN@

CONN@ JCPU1C

JCPU1C

VCC[001]

VCC[068]

VCC[002]

VCC[069]

VCC[003]

VCC[070]

VCC[004]

VCC[071]

VCC[005]

VCC[072]

VCC[006]

VCC[073]

VCC[007]

VCC[074]

VCC[008]

VCC[075]

VCC[009]

VCC[076]

VCC[010]

VCC[077]

VCC[011]

VCC[078]

VCC[012]

VCC[079]

VCC[013]

VCC[080]

VCC[014]

VCC[081]

VCC[015]

VCC[082]

VCC[016]

VCC[083]

VCC[017]

VCC[084]

VCC[018]

VCC[085]

VCC[019]

VCC[086]

VCC[020]

VCC[087]

VCC[021]

VCC[088]

VCC[022]

VCC[089]

VCC[023]

VCC[090]

VCC[024]

VCC[091]

VCC[025]

VCC[092]

VCC[026]

VCC[093]

VCC[027]

VCC[094]

VCC[028]

VCC[095]

VCC[029]

VCC[096]

VCC[030]

VCC[097]

VCC[031]

VCC[098]

VCC[032]

VCC[099]

VCC[033]

VCC[100] VCC[034] VCC[035]

VCCP[01] VCC[036]

VCCP[02] VCC[037]

VCCP[03] VCC[038]

VCCP[04] VCC[039]

VCCP[05] VCC[040]

VCCP[06] VCC[041]

VCCP[07] VCC[042]

VCCP[08] VCC[043]

VCCP[09] VCC[044]

VCCP[10] VCC[045]

VCCP[11] VCC[046]

VCCP[12] VCC[047]

VCCP[13] VCC[048]

VCCP[14] VCC[049]

VCCP[15] VCC[050]

VCCP[16] VCC[051] VCC[052]

VCCA[01] VCC[053]

VCCA[02] VCC[054] VCC[055] VCC[056] VCC[057] VCC[058] VCC[059] VCC[060] VCC[061] VCC[062] VCC[063] VCC[064]

VCCSENSE VCC[065] VCC[066] VCC[067]

VSSSENSE

Penryn

For 8 layer condition

AA10 AA12 AA13 AA15 AA17 AA18 AA20

AC10 AB10 AB12 AB14 AB15 AB17 AB18

A9 A10 A12 A13 A15 A17 A18 A20

B9 B10 B12 B14 B15 B17 B18 B20

C9 C10 C12 C13 C15 C17 C18

D9 D10 D12 D14 D15 D17 D18

E9 E10 E12 E13 E15 E17 E18 E20

F9 F10 F12 F14 F15 F17 F18 F20 AA7 AA9

AB9

VID[0] VID[1] VID[2] VID[3] VID[4] VID[5] VID[6]

AB20 AB7 AC7 AC9 AC12 AC13 AC15 AC17 AC18 AD7 AD9 AD10 AD12 AD14 AD15 AD17 AD18 AE9 AE10 AE12 AE13 AE15 AE17 AE18 AE20 AF9 AF10 AF12 AF14 AF15 AF17 AF18 AF20

G21 V6 J6 K6 M6 J21 K21 M21 N21 N6 R21 R6 T21 T6 V21 W21

B26 C26

AD6 AF5 AE5 AF4 AE3 AF3 AE2

VCCSENSE

AF7

VSSSENSE

AE7

Length match within 25 mils.

CPU_VID0 44 CPU_VID1 44 CPU_VID2 44 CPU_VID3 44 CPU_VID4 44 CPU_VID5 44 CPU_VID6 44

VCCSENSE 44

No stuff 27.4 pull down near IMVP for testing

VSSSENSE 44

+VCCP

220U_D2_4VY_R15M

C10

0814 Change to 220uF 0819 Change to C_D2E

10U_0805_6.3V6M

C12

0.01U_0402_16V7K

Near pin B26

+1.5VS

C11

The trace width/space/other is 20/7/25.

+CPU_CORE

R28 100_0402_1%R28 100_0402_1%

1 2

R30 100_0402_1%R30 100_0402_1%

1 2

VCCSENSE

VSSSENSE

Close to CPU pin AD26 within 500mils.

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2006/02/13 2006/03/10

Compal Secret Data

Deciphered Date

Close to CPU pin within 500mils.

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, M/B LA-4232P

401593

548Saturday, June 06, 2009

High Frequence Decoupling

10uF 0805 X5R -> 85 degree.

Place these caps inside the CPU socket cavity.

( Left side on Top ).

D D

C C

B B

A A

CONN@

CONN@ JCPU1D

JCPU1D

VSS[001]

VSS[002]

A11

VSS[003]

A14

VSS[004]

A16

VSS[005]

A19

VSS[006]

A23

VSS[007]

AF2

VSS[008]

VSS[009]

VSS[010]

B11

VSS[011]

B13

VSS[012]

B16

VSS[013]

B19

VSS[014]

B21

VSS[015]

B24

VSS[016]

VSS[017]

VSS[018]

C11

VSS[019]

C14

VSS[020]

C16

VSS[021]

C19

VSS[022]

VSS[023]

C22

VSS[024]

C25

VSS[025]

VSS[026]

VSS[027]

VSS[028]

D11

VSS[029]

D13

VSS[030]

D16

VSS[031]

D19

VSS[032]

D23

VSS[033]

D26

VSS[034]

VSS[035]

VSS[036]

VSS[037]

E11

VSS[038]

E14

VSS[039]

E16

VSS[040]

E19

VSS[041]

E21

VSS[042]

E24

VSS[043]

VSS[044]

VSS[045]

F11

VSS[046]

F13

VSS[047]

F16

VSS[048]

F19

VSS[049]

VSS[050]

F22

VSS[051]

F25

VSS[052]

VSS[053]

VSS[054]

G23

VSS[055]

G26

VSS[056]

VSS[057]

VSS[058]

H21

VSS[059]

H24

VSS[060]

VSS[061]

VSS[062]

J22

VSS[063]

J25

VSS[064]

VSS[065]

VSS[066]

K23

VSS[067]

K26

VSS[068]

VSS[069]

VSS[070]

L21

VSS[071]

L24

VSS[072]

VSS[073]

VSS[074]

M22

VSS[075]

M25

VSS[076]

VSS[077]

VSS[078]

N23

VSS[079]

N26

VSS[080] VSS[081]P3VSS[162]

Penryn

VSS[082] VSS[083] VSS[084] VSS[085] VSS[086] VSS[087] VSS[088] VSS[089] VSS[090] VSS[091] VSS[092] VSS[093] VSS[094] VSS[095] VSS[096] VSS[097] VSS[098] VSS[099] VSS[100] VSS[101] VSS[102] VSS[103] VSS[104] VSS[105] VSS[106] VSS[107] VSS[108] VSS[109] VSS[110] VSS[111] VSS[112] VSS[113] VSS[114] VSS[115] VSS[116] VSS[117] VSS[118] VSS[119] VSS[120] VSS[121] VSS[122] VSS[123] VSS[124] VSS[125] VSS[126] VSS[127] VSS[128] VSS[129] VSS[130] VSS[131] VSS[132] VSS[133] VSS[134] VSS[135] VSS[136] VSS[137] VSS[138] VSS[139] VSS[140] VSS[141] VSS[142] VSS[143] VSS[144] VSS[145] VSS[146] VSS[147] VSS[148] VSS[149] VSS[150] VSS[151] VSS[152] VSS[153] VSS[154] VSS[155] VSS[156] VSS[157] VSS[158] VSS[159] VSS[160] VSS[161]

VSS[163]

P6 P21 P24 R2 R5 R22 R25 T1 T4 T23 T26 U3 U6 U21 U24 V2 V5 V22 V25 W1 W4 W23 W26 Y3 Y6 Y21 Y24 AA2 AA5 AA8 AA11 AA14 AA16 AA19 AA22 AA25 AB1 AB4 AB8 AB11 AB13 AB16 AB19 AB23 AB26 AC3 AC6 AC8 AC11 AC14 AC16 AC19 AC21 AC24 AD2 AD5 AD8 AD11 AD13 AD16 AD19 AD22 AD25 AE1 AE4 AE8 AE11 AE14 AE16 AE19 AE23 AE26 A2 AF6 AF8 AF11 AF13 AF16 AF19 AF21 A25 AF25

Place these caps inside the CPU socket cavity.

( Right side on Top side).

Place these caps inside the CPU socket cavity.

( Left side on Bottom ).

Place these caps inside the CPU socket cavity.

( Right side on Bottom ).

Place these caps inside the CPU socket.

+VCCP

C213

0.1U_0402_16V

+CPU_CORE

C202

C216

C216 10U_0805_6.3V6M

10U_0805_6.3V6M

C190

C190 10U_0805_6.3V6M

10U_0805_6.3V6M

C501

C501 10U_0805_6.3V6M

10U_0805_6.3V6M

C502

C502 10U_0805_6.3V6M

10U_0805_6.3V6M

330U_D2E_2.5VM_R9

C209

0.1U_0402_16V

C207

Place these caps inside the CPU socket.

C205

C205 10U_0805_6.3V6M

10U_0805_6.3V6M

C529

C529 10U_0805_6.3V6M

10U_0805_6.3V6M

C232

C232 10U_0805_6.3V6M

10U_0805_6.3V6M

C258

C258 10U_0805_6.3V6M

10U_0805_6.3V6M

C505

C505 10U_0805_6.3V6M

10U_0805_6.3V6M

C504

C504 10U_0805_6.3V6M

10U_0805_6.3V6M

C257

C257 10U_0805_6.3V6M

10U_0805_6.3V6M

C261

C261 10U_0805_6.3V6M

10U_0805_6.3V6M

( Left side on Top ).

C214

C214 10U_0805_6.3V6M

10U_0805_6.3V6M

Place these caps inside the CPU socket.

C210

C210 10U_0805_6.3V6M

10U_0805_6.3V6M

C508

C508 10U_0805_6.3V6M

10U_0805_6.3V6M

C510

C510 10U_0805_6.3V6M

10U_0805_6.3V6M

330U_D2E_2.5VM_R9

C259

C212

0.1U_0402_16V

C254

C254 10U_0805_6.3V6M

10U_0805_6.3V6M

C514

C514 10U_0805_6.3V6M

10U_0805_6.3V6M

C515

C515 10U_0805_6.3V6M

10U_0805_6.3V6M

330U_D2E_2.5VM_R9

Place these caps inside

C255

the CPU socket.

( Right side on Top side).( Left side on Top ).

C185

0.1U_0402_16V

C208

C208 10U_0805_6.3V6M

10U_0805_6.3V6M

C519

C519 10U_0805_6.3V6M

10U_0805_6.3V6M

C520

C520 10U_0805_6.3V6M

10U_0805_6.3V6M

C183

0.1U_0402_16V

C203

C203 10U_0805_6.3V6M

10U_0805_6.3V6M

C522

C522 10U_0805_6.3V6M

10U_0805_6.3V6M

C526

C526 10U_0805_6.3V6M

10U_0805_6.3V6M

C200

C200 10U_0805_6.3V6M

10U_0805_6.3V6M

C533

C533 10U_0805_6.3V6M

10U_0805_6.3V6M

C532

C532 10U_0805_6.3V6M

10U_0805_6.3V6M

ESR <= 1.5m ohm Capacitor > 880 uF

C184

0.1U_0402_16V

C206

C206 10U_0805_6.3V6M

10U_0805_6.3V6M

C204

C204 10U_0805_6.3V6M

10U_0805_6.3V6M

C215

C215 10U_0805_6.3V6M

10U_0805_6.3V6M

( Right side on Top ).

C226

C226 10U_0805_6.3V6M

10U_0805_6.3V6M

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2006/02/13 2006/03/10

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, M/B LA-4232P

401593

648Saturday, June 06, 2009

U4A

H_D#[0..63]5

D D

C C

H_RESET#4

H_CPUSLP#5

B B

Layout Note: H_RCOMP / H_VREF / H_SWNG

trace width and spacing is 10/20

+VCCP

R45

1K_0402_1%

A A

R46

2K_0402_1%

R46

H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31 H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63

H_SWNG H_RCOMP

H_RESET# H_CPUSLP#

+H_VREF

C391

0.1U_0402_16V

U4A

E6 G2 H6 H2

F6 D4 H3 M9

M11

N12

L2 R2 N9

L6 M5

J3 N2 R1 N5 N6

P13

N10

AD14

Y10 Y12 Y14

Y7 W2

AA8

AA13

AA9 AA11 AD11 AD10 AD13 AE12

AE9

AA2

AD8

AA3

AD3

AD7 AE14

AF3

AC1

AE3

AC3 AE11

AE8

AG2

AD6

C12

E11

A11

B11

CANTIGA_1p0

H_RCOMP

R324

24.9_0402_1%

H_D#_0 H_D#_1 H_D#_2 H_D#_3 H_D#_4 H_D#_5 H_D#_6 H_D#_7 H_D#_8 H_D#_9 H_D#_10 H_D#_11 H_D#_12 H_D#_13 H_D#_14 H_D#_15 H_D#_16 H_D#_17 H_D#_18 H_D#_19 H_D#_20 H_D#_21 H_D#_22 H_D#_23 H_D#_24 H_D#_25 H_D#_26 H_D#_27 H_D#_28 H_D#_29 H_D#_30 H_D#_31 H_D#_32 H_D#_33 H_D#_34 H_D#_35 H_D#_36 H_D#_37 H_D#_38 H_D#_39 H_D#_40 H_D#_41 H_D#_42 H_D#_43 H_D#_44 H_D#_45 H_D#_46 H_D#_47 H_D#_48 H_D#_49 H_D#_50 H_D#_51 H_D#_52 H_D#_53 H_D#_54 H_D#_55 H_D#_56 H_D#_57 H_D#_58 H_D#_59 H_D#_60 H_D#_61 H_D#_62 H_D#_63

H_SWING H_RCOMP

H_CPURST# H_CPUSLP#

H_AVREF H_DVREF

+VCCP

221_0603_1%

100_0402_1%

R322

R323

HOST

H_SWNG

C386

0.1U_0402_16V

H_ADSTB#_0 H_ADSTB#_1

H_DEFER#

HPLL_CLK

HPLL_CLK#

H_DPWR#

H_DINV#_0 H_DINV#_1 H_DINV#_2 H_DINV#_3

H_DSTBN#_0 H_DSTBN#_1 H_DSTBN#_2 H_DSTBN#_3

H_DSTBP#_0 H_DSTBP#_1 H_DSTBP#_2 H_DSTBP#_3

H_REQ#_0 H_REQ#_1 H_REQ#_2 H_REQ#_3 H_REQ#_4

Near B3 pinwithin 100 mils from NB

H_A#_3 H_A#_4 H_A#_5 H_A#_6 H_A#_7 H_A#_8

H_A#_9 H_A#_10 H_A#_11 H_A#_12 H_A#_13 H_A#_14 H_A#_15 H_A#_16 H_A#_17 H_A#_18 H_A#_19 H_A#_20 H_A#_21 H_A#_22 H_A#_23 H_A#_24 H_A#_25 H_A#_26 H_A#_27 H_A#_28 H_A#_29 H_A#_30 H_A#_31

H_A#_32 H_A#_33 H_A#_34 H_A#_35

H_ADS#

H_BNR# H_BPRI#

H_BREQ# H_DBSY#

H_DRDY#

H_HIT#

H_HITM# H_LOCK# H_TRDY#

H_RS#_0

H_RS#_1

H_RS#_2

H_A#3

A14

H_A#4

C15

H_A#5

F16

H_A#6

H13

H_A#7

C18

H_A#8

M16

H_A#9

J13

H_A#10

P16

H_A#11

R16

H_A#12

N17

H_A#13

M13

H_A#14

E17

H_A#15

P17

H_A#16

F17

H_A#17

G20

H_A#18

B19

H_A#19

J16

H_A#20

E20

H_A#21

H16

H_A#22

J20

H_A#23

L17

H_A#24

A17

H_A#25

B17

H_A#26

L16

H_A#27

C21

H_A#28

J17

H_A#29

H20

H_A#30

B18

H_A#31

K17

H_A#32

B20

H_A#33

F21

H_A#34

K21

H_A#35

L20

H_ADS#

H12

H_ADSTB#0

B16

H_ADSTB#1

G17

H_BNR#

H_BPRI#

F11

H_BR0#

G12

H_DEFER#

H_DBSY#

B10

CLK_MCH_BCLK

AH7

CLK_MCH_BCLK#

AH6

H_DPWR#

J11

H_DRDY#

H_HIT#

H_HITM#

E12

H_LOCK#

H11

H_TRDY#

H_DINV#0

H_DINV#1

H_DINV#2

Y13

H_DINV#3

H_DSTBN#0

L10

H_DSTBN#1

H_DSTBN#2

AA5

H_DSTBN#3

AE6

H_DSTBP#0

H_DSTBP#1

H_DSTBP#2

AA6

H_DSTBP#3

AE5

H_REQ#0

B15

H_REQ#1

K13

H_REQ#2

F13

H_REQ#3

B13

H_REQ#4

B14

H_RS#0

H_RS#1

F12

H_RS#2

ICH_PWROK19,27

VGATE19,27,44

Layout Note: V_DDR_MCH_REF trace width and spacing is 20/20.

+V_DDR_MCH_REF13,14

H_A#[3..35] 4

+SMRCOMP_VOH

H_ADS# 4 H_ADSTB#0 4 H_ADSTB#1 4 H_BNR# 4 H_BPRI# 4 H_BR0# 4 H_DEFER# 4 H_DBSY# 4 CLK_MCH_BCLK 15 CLK_MCH_BCLK# 15 H_DPWR# 5 H_DRDY# 4 H_HIT# 4 H_HITM# 4 H_LOCK# 4 H_TRDY# 4

H_DINV#0 5 H_DINV#1 5 H_DINV#2 5 H_DINV#3 5

H_DSTBN#0 5 H_DSTBN#1 5 H_DSTBN#2 5 H_DSTBN#3 5

H_DSTBP#0 5 H_DSTBP#1 5 H_DSTBP#2 5 H_DSTBP#3 5

H_REQ#0 4 H_REQ#1 4 H_REQ#2 4 H_REQ#3 4 H_REQ#4 4

H_RS#0 4 H_RS#1 4 H_RS#2 4

PLT_RST#17,27,30,31

H_THERMTRIP#4,18

DPRSLPVR19,44

1 2

R408 0_0402_5%R408 0_0402_5%

1 2

R407 0_0402_5%@R407 0_0402_5%@

+V_DDR_MCH_REF

C398

2.2U_0603_6.3V4Z

2.2U_0603_6.3V4Z 2

C403

2.2U_0603_6.3V4Z

C121

0.1U_0402_16V

T7T7 T11T11 T12T12

+1.8V

R331

C400

1K_0402_1%

0.01U_0402_16V7K

R332

3.01K_0402_1%

R333

1K_0402_1%

C404

0.01U_0402_16V7K

R82

PM_EXTTS#0

PM_EXTTS#1

PM_PWROK_R

+1.8V

R42

R42 1K_0402_1%

1K_0402_1%

R43

R43 1K_0402_1%

1K_0402_1%

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

1 2

10K_0402_5%

10K_0402_5% R83

R83

1 2

10K_0402_5%

MCH_CLKSEL015 MCH_CLKSEL115 MCH_CLKSEL215

CFG169

CFG199 CFG209

PM_BMBUSY#19

H_DPRSTP#5,18,44 PM_EXTTS#013 PM_EXTTS#114

1 2

R523 100_0402_5%R523 100_0402_5%

T13T13 T14T14 T15T15 T16T16 T17T17 T18T18 T19T19 T20T20 T21T21 T22T22 T24T24

T25T25 T26T26 T27T27

T28T28

T41T41 T44T44 T73T73 T74T74

+3VS

MCH_CLKSEL0 MCH_CLKSEL1 MCH_CLKSEL2

T8PAD T8PAD

T9PAD T9PAD CFG59 CFG69 CFG79

CFG99

CFG5 CFG6 CFG7

T37PAD T37PAD

CFG9

T65PAD T65PAD

T40PAD T40PAD

CFG12

T67PAD T67PAD

CFG13

T47PAD T47PAD

T10PAD T10PAD

T66PAD T66PAD

CFG16

T68PAD T68PAD

T39PAD T39PAD

CFG19 CFG20

PM_BMBUSY# H_DPRSTP# PM_EXTTS#0 PM_EXTTS#1

PM_PWROK_R

PLT_RST#_NBPLT_RST# THERMTRIP# DPRSLPVR

2006/02/13 2006/03/10

U4B

M36

RSVD1

N36

RSVD2

R33

RSVD3

T33

RSVD4

AH9

RSVD5

AH10

RSVD6

AH12

RSVD7

AH13

RSVD8

K12

RSVD9

AL34

RSVD10

AK34

RSVD11

AN35

RSVD12

AM35

RSVD13

T24

RSVD14

B31

RSVD15

RSVD16

RSVD17

AY21

RSVD20

BG23

RSVD22

BF23

RSVD23

BH18

RSVD24

BF18

RSVD25

T25

CFG_0

R25

CFG_1

P25

CFG_2

P20

CFG_3

P24

CFG_4

C25

CFG_5

N24

CFG_6

M24

CFG_7

E21

CFG_8

C23

CFG_9

C24

CFG_10

N21

CFG_11

P21

CFG_12

T21

CFG_13

R20

CFG_14

M20

CFG_15

L21

CFG_16

H21

CFG_17

P29

CFG_18

R28

CFG_19

T28

CFG_20

R29

PM_SYNC#

PM_DPRSTP#

N33

PM_EXT_TS#_0

P32

PM_EXT_TS#_1

AT40

PWROK

AT11

RSTIN#

T20

THERMTRIP#

R32

DPRSLPVR

BG48

NC_1

BF48

NC_2

BD48

NC_3

BC48

NC_4

BH47

NC_5

BG47

NC_6

BE47

NC_7

BH46

NC_8

BF46

NC_9

BG45

NC_10

BH44

NC_11

BH43

NC_12

BH6

NC_13

BH5

NC_14

BG4

NC_15

BH3

NC_16

BF3

NC_17

BH2

NC_18

BG2

NC_19

BE2

NC_20

BG1

NC_21

BF1

NC_22

BD1

NC_23

BC1

NC_24

NC_25

A47

NC_26

CANTIGA_1p0

Compal Secret Data

Deciphered Date

RSVD

SM_RCOMP_VOH SM_RCOMP_VOL

SM_DRAMRST# DPLL_REF_CLK

DDR CLK/ CONTROL/COMPENSATION

DPLL_REF_CLK#

DPLL_REF_SSCLK

DPLL_REF_SSCLK#

CLK

CFG

DMI

GRAPHICS VID

MEHDA

DDPC_CTRLCLK

DDPC_CTRLDATA

SDVO_CTRLCLK

SDVO_CTRLDATA

MISC

SA_CK_0 SA_CK_1 SB_CK_0 SB_CK_1

SA_CK#_0 SA_CK#_1 SB_CK#_0 SB_CK#_1

SA_CKE_0 SA_CKE_1 SB_CKE_0 SB_CKE_1

SA_CS#_0 SA_CS#_1 SB_CS#_0 SB_CS#_1

SA_ODT_0 SA_ODT_1 SB_ODT_0 SB_ODT_1

SM_RCOMP

SM_RCOMP#

SM_VREF

SM_PWROK

SM_REXT

PEG_CLK

PEG_CLK#

DMI_RXN_0 DMI_RXN_1 DMI_RXN_2 DMI_RXN_3

DMI_RXP_0 DMI_RXP_1 DMI_RXP_2 DMI_RXP_3

DMI_TXN_0 DMI_TXN_1 DMI_TXN_2 DMI_TXN_3

DMI_TXP_0 DMI_TXP_1 DMI_TXP_2 DMI_TXP_3

GFX_VID_0 GFX_VID_1 GFX_VID_2 GFX_VID_3 GFX_VID_4

GFX_VR_EN

CL_CLK

CL_DATA

CL_PWROK

CL_RST# CL_VREF

CLKREQ#

ICH_SYNC#

TSATN#

HDA_BCLK HDA_RST#

HDA_SDI

HDA_SDO

HDA_SYNC

M_CLK_DDR0

AP24

M_CLK_DDR1

AT21

M_CLK_DDR2

AV24

M_CLK_DDR3

AU20

M_CLK_DDR#0

AR24

M_CLK_DDR#1

AR21

M_CLK_DDR#2

AU24

M_CLK_DDR#3

AV20

DDR_CKE0_DIMMA

BC28

DDR_CKE1_DIMMA

AY28

DDR_CKE2_DIMMB

AY36

DDR_CKE3_DIMMB

BB36

DDR_CS0_DIMMA#

BA17

DDR_CS1_DIMMA#

AY16

DDR_CS2_DIMMB#

AV16

DDR_CS3_DIMMB#+SMRCOMP_VOL

AR13

M_ODT0

BD17

M_ODT1

AY17

M_ODT2

BF15

M_ODT3

AY13

SMRCOMP

BG22

SMRCOMP#

BH21

+SMRCOMP_VOH

BF28

+SMRCOMP_VOL

BH28

+V_DDR_MCH_REF

AV42 AR36

SM_REXT

BF17

TP_SM_DRAMRST#

BC36

CLK_MCH_DREFCLK

B38

CLK_MCH_DREFCLK#

A38

MCH_SSCDREFCLK

E41

MCH_SSCDREFCLK#

F41

CLK_MCH_3GPLL

F43

CLK_MCH_3GPLL#

E43

DMI_MRX_ITX_N0

AE41

DMI_MRX_ITX_N1

AE37

DMI_MRX_ITX_N2

AE47

DMI_MRX_ITX_N3

AH39

DMI_MRX_ITX_P0

AE40

DMI_MRX_ITX_P1

AE38

DMI_MRX_ITX_P2

AE48

DMI_MRX_ITX_P3

AH40

DMI_MTX_IRX_N0

AE35

DMI_MTX_IRX_N1

AE43

DMI_MTX_IRX_N2

AE46

DMI_MTX_IRX_N3

AH42

DMI_MTX_IRX_P0

AD35

DMI_MTX_IRX_P1

AE44

DMI_MTX_IRX_P2

AF46

DMI_MTX_IRX_P3

AH43

B33 B32 G33 F33 E33

C34

AH37 AH36 AN36 AJ35 AH34

N28 M28 G36 E36 K36 H36

B12

B28 B30 B29 C29 A28

T30T30 T31T31 T32T32 T33T33 T34T34

T35T35

CL_CLK0 CL_DATA0 M_PWROK CL_RST# +CL_VREF

CLKREQ#_7 MCH_ICH_SYNC#

TSATN#

T99T99 T100T100 T101T101 T102T102 T103T103

Title

SCHEMATIC, M/B LA-4232P

Size Document Number Rev

Custom

401593

Date: Sheet

M_CLK_DDR0 13 M_CLK_DDR1 13 M_CLK_DDR2 14 M_CLK_DDR3 14

M_CLK_DDR#0 13 M_CLK_DDR#1 13 M_CLK_DDR#2 14 M_CLK_DDR#3 14

DDR_CKE0_DIMMA 13 DDR_CKE1_DIMMA 13 DDR_CKE2_DIMMB 14 DDR_CKE3_DIMMB 14

DDR_CS0_DIMMA# 13 DDR_CS1_DIMMA# 13 DDR_CS2_DIMMB# 14 DDR_CS3_DIMMB# 14

M_ODT0 13 M_ODT1 13 M_ODT2 14 M_ODT3 14

R328 80.6_0402_1%

1 2

R329 80.6_0402_1%R329 80.6_0402_1%

1 2

R40 499_0402_1%R40 499_0402_1%

1 2

T29 PADT29 PAD

CLK_MCH_DREFCLK 15

CLK_MCH_DREFCLK# 15

MCH_SSCDREFCLK 15

MCH_SSCDREFCLK# 15

CLK_MCH_3GPLL 15 CLK_MCH_3GPLL# 15

DMI_MRX_ITX_N0 19 DMI_MRX_ITX_N1 19 DMI_MRX_ITX_N2 19 DMI_MRX_ITX_N3 19

DMI_MTX_IRX_N0 19 DMI_MTX_IRX_N1 19 DMI_MTX_IRX_N2 19 DMI_MTX_IRX_N3 19

DMI_MTX_IRX_P0 19 DMI_MTX_IRX_P1 19 DMI_MTX_IRX_P2 19 DMI_MTX_IRX_P3 19

CL_CLK0 19 CL_DATA0 19 M_PWROK 19 CL_RST# 19

0.1U_0402_16V

T36T36 T48T48 T63T63 T64T64

CLKREQ#_7 15 MCH_ICH_SYNC# 19

R521 56_0402_5%R521 56_0402_5%

Compal Electronics, Inc.

DMI_MRX_ITX_P0 19 DMI_MRX_ITX_P1 19 DMI_MRX_ITX_P2 19 DMI_MRX_ITX_P3 19

C181

+VCCP

748Saturday, June 06, 2009

+1.8V

R100

R100 1K_0402_1%

1K_0402_1%

R99

R99 511_0402_1%

511_0402_1%

D D

DDR_A_D[0..63]13

C C

B B

DDR_A_D0 DDR_B_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15 DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63

AJ38

AJ41 AN38 AM38

AJ36

AJ40

AM44 AM42

AN43 AN44 AU40 AT38 AN41 AN39 AU44 AU42 AV39 AY44 BA40 BD43 AV41 AY43 BB41 BC40 AY37 BD38 AV37 AT36 AY38 BB38 AV36

AW36

BD13 AU11 BC11 BA12 AU13 AV13 BD12 BC12

AU10 BA11

AN10

AM11

AM5

AN12

AM13

AJ11

AJ12

BB9 BA9

AV9 BD9

AY8 BA6 AV5 AV7 AT9 AN8 AU5 AU6 AT5

AJ9 AJ8

U4D

SA_DQ_0 SA_DQ_1 SA_DQ_2 SA_DQ_3 SA_DQ_4 SA_DQ_5 SA_DQ_6 SA_DQ_7 SA_DQ_8 SA_DQ_9 SA_DQ_10 SA_DQ_11 SA_DQ_12 SA_DQ_13 SA_DQ_14 SA_DQ_15 SA_DQ_16 SA_DQ_17 SA_DQ_18 SA_DQ_19 SA_DQ_20 SA_DQ_21 SA_DQ_22 SA_DQ_23 SA_DQ_24 SA_DQ_25 SA_DQ_26 SA_DQ_27 SA_DQ_28 SA_DQ_29 SA_DQ_30 SA_DQ_31 SA_DQ_32 SA_DQ_33 SA_DQ_34 SA_DQ_35 SA_DQ_36 SA_DQ_37 SA_DQ_38 SA_DQ_39 SA_DQ_40 SA_DQ_41 SA_DQ_42 SA_DQ_43 SA_DQ_44 SA_DQ_45 SA_DQ_46 SA_DQ_47 SA_DQ_48 SA_DQ_49 SA_DQ_50 SA_DQ_51 SA_DQ_52 SA_DQ_53 SA_DQ_54 SA_DQ_55 SA_DQ_56 SA_DQ_57 SA_DQ_58 SA_DQ_59 SA_DQ_60 SA_DQ_61 SA_DQ_62 SA_DQ_63

CANTIGA_1p0

DDR_A_BS#0

BD21

SA_BS_0 SA_BS_1 SA_BS_2

SA_RAS# SA_CAS#

SA_WE#

SA_DM_0 SA_DM_1 SA_DM_2 SA_DM_3 SA_DM_4 SA_DM_5 SA_DM_6 SA_DM_7

SA_DQS_0 SA_DQS_1 SA_DQS_2 SA_DQS_3 SA_DQS_4 SA_DQS_5 SA_DQS_6

SA_DQS_7 SA_DQS#_0 SA_DQS#_1 SA_DQS#_2 SA_DQS#_3 SA_DQS#_4 SA_DQS#_5 SA_DQS#_6 SA_DQS#_7

SA_MA_0 SA_MA_1 SA_MA_2 SA_MA_3 SA_MA_4 SA_MA_5 SA_MA_6 SA_MA_7 SA_MA_8

SA_MA_9 SA_MA_10 SA_MA_11 SA_MA_12 SA_MA_13 SA_MA_14

DDR SYSTEM MEMORY A

BG18 AT25

BB20 BD20 AY20

AM37 AT41 AY41 AU39 BB12 AY6 AT7 AJ5

AJ44 AT44 BA43 BC37 AW12 BC8 AU8 AM7 AJ43 AT43 BA44 BD37 AY12 BD8 AU9 AM8

BA21 BC24 BG24 BH24 BG25 BA24 BD24 BG27 BF25 AW24 BC21 BG26 BH26 BH17 AY25

DDR_A_BS#1 DDR_A_BS#2

DDR_A_RAS# DDR_A_CAS# DDR_A_WE#

DDR_A_DM0 DDR_A_DM1 DDR_A_DM2 DDR_A_DM3 DDR_A_DM4 DDR_A_DM5 DDR_A_DM6 DDR_A_DM7

DDR_A_DQS0 DDR_A_DQS1 DDR_A_DQS2 DDR_A_DQS3 DDR_A_DQS4 DDR_A_DQS5 DDR_A_DQS6 DDR_A_DQS7 DDR_A_DQS#0 DDR_A_DQS#1 DDR_A_DQS#2

DDR_A_DQS#3

DDR_A_DQS#4 DDR_A_DQS#5 DDR_A_DQS#6 DDR_A_DQS#7

DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 DDR_A_MA14

DDR_A_BS#0 13 DDR_A_BS#1 13 DDR_A_BS#2 13

DDR_A_RAS# 13 DDR_A_CAS# 13 DDR_A_WE# 13

DDR_A_DM[0..7] 13

DDR_A_DQS[0..7] 13

DDR_A_DQS#[0..7] 13

DDR_A_MA[0..14] 13

DDR_B_D[0..63]14

DDR_B_D1 DDR_B_D2 DDR_B_D3 DDR_B_D4 DDR_B_D5 DDR_B_D6 DDR_B_D7 DDR_B_D8 DDR_B_D9 DDR_B_D10 DDR_B_D11 DDR_B_D12 DDR_B_D13 DDR_B_D14 DDR_B_D15 DDR_B_D16 DDR_B_D17 DDR_B_D18 DDR_B_D19 DDR_B_D20 DDR_B_D21 DDR_B_D22 DDR_B_D23 DDR_B_D24 DDR_B_D25 DDR_B_D26 DDR_B_D27 DDR_B_D28 DDR_B_D29 DDR_B_D30 DDR_B_D31 DDR_B_D32 DDR_B_D33 DDR_B_D34 DDR_B_D35 DDR_B_D36 DDR_B_D37 DDR_B_D38 DDR_B_D39 DDR_B_D40 DDR_B_D41 DDR_B_D42 DDR_B_D43 DDR_B_D44 DDR_B_D45 DDR_B_D46 DDR_B_D47 DDR_B_D48 DDR_B_D49 DDR_B_D50 DDR_B_D51 DDR_B_D52 DDR_B_D53 DDR_B_D54 DDR_B_D55 DDR_B_D56 DDR_B_D57 DDR_B_D58 DDR_B_D59 DDR_B_D60 DDR_B_D61 DDR_B_D62 DDR_B_D63

AK47 AH46 AP47 AP46

AJ46

AJ48 AM48 AP48 AU47 AU46 BA48 AY48 AT47 AR47 BA47 BC47 BC46 BC44 BG43 BF43 BE45 BC41 BF40 BF41 BG38 BF38 BH35 BG35 BH40 BG39 BG34 BH34 BH14 BG12 BH11

BG8 BH12 BF11

BF8

BG7

BC5

BC6

AY3

AY1

BF6

BF5

BA1

BD3

AV2

AU3

AR3

AN2

AY2

AV1

AP3

AR1

AH1

AM2

AM3

AH3

AL1 AL2 AJ1

AJ3

U4E

SB_DQ_0 SB_DQ_1 SB_DQ_2 SB_DQ_3 SB_DQ_4 SB_DQ_5 SB_DQ_6 SB_DQ_7 SB_DQ_8 SB_DQ_9 SB_DQ_10 SB_DQ_11 SB_DQ_12 SB_DQ_13 SB_DQ_14 SB_DQ_15 SB_DQ_16 SB_DQ_17 SB_DQ_18 SB_DQ_19 SB_DQ_20 SB_DQ_21 SB_DQ_22 SB_DQ_23 SB_DQ_24 SB_DQ_25 SB_DQ_26 SB_DQ_27 SB_DQ_28 SB_DQ_29 SB_DQ_30 SB_DQ_31 SB_DQ_32 SB_DQ_33 SB_DQ_34 SB_DQ_35 SB_DQ_36 SB_DQ_37 SB_DQ_38 SB_DQ_39 SB_DQ_40 SB_DQ_41 SB_DQ_42 SB_DQ_43 SB_DQ_44 SB_DQ_45 SB_DQ_46 SB_DQ_47 SB_DQ_48 SB_DQ_49 SB_DQ_50 SB_DQ_51 SB_DQ_52 SB_DQ_53 SB_DQ_54 SB_DQ_55 SB_DQ_56 SB_DQ_57 SB_DQ_58 SB_DQ_59 SB_DQ_60 SB_DQ_61 SB_DQ_62 SB_DQ_63

CANTIGA_1p0

DDR_B_BS#0

BC16

SB_BS_0 SB_BS_1 SB_BS_2

SB_RAS#

SB_CAS#

SB_WE#

SB_DM_0 SB_DM_1 SB_DM_2 SB_DM_3 SB_DM_4 SB_DM_5 SB_DM_6 SB_DM_7

SB_DQS_0 SB_DQS_1 SB_DQS_2 SB_DQS_3 SB_DQS_4 SB_DQS_5 SB_DQS_6

SB_DQS_7 SB_DQS#_0 SB_DQS#_1 SB_DQS#_2 SB_DQS#_3 SB_DQS#_4 SB_DQS#_5 SB_DQS#_6 SB_DQS#_7

SB_MA_0 SB_MA_1 SB_MA_2 SB_MA_3 SB_MA_4 SB_MA_5 SB_MA_6 SB_MA_7 SB_MA_8

SB_MA_9 SB_MA_10 SB_MA_11 SB_MA_12 SB_MA_13 SB_MA_14

DDR SYSTEM MEMORY B

BB17 BB33

AU17 BG16 BF14

AM47 AY47 BD40 BF35 BG11 BA3 AP1 AK2

AL47 AV48 BG41 BG37 BH9 BB2 AU1 AN6 AL46 AV47 BH41 BH37 BG9 BC2 AT2 AN5

AV17 BA25 BC25 AU25 AW25 BB28 AU28 AW28 AT33 BD33 BB16 AW33 AY33 BH15 AU33

DDR_B_BS#1 DDR_B_BS#2

DDR_B_RAS# DDR_B_CAS# DDR_B_WE#

DDR_B_DM0 DDR_B_DM1 DDR_B_DM2 DDR_B_DM3 DDR_B_DM4 DDR_B_DM5 DDR_B_DM6 DDR_B_DM7

DDR_B_DQS0 DDR_B_DQS1 DDR_B_DQS2 DDR_B_DQS3 DDR_B_DQS4 DDR_B_DQS5 DDR_B_DQS6 DDR_B_DQS7 DDR_B_DQS#0 DDR_B_DQS#1 DDR_B_DQS#2 DDR_B_DQS#3 DDR_B_DQS#4 DDR_B_DQS#5 DDR_B_DQS#6 DDR_B_DQS#7

DDR_B_MA0 DDR_B_MA1 DDR_B_MA2 DDR_B_MA3 DDR_B_MA4 DDR_B_MA5 DDR_B_MA6 DDR_B_MA7 DDR_B_MA8 DDR_B_MA9 DDR_B_MA10 DDR_B_MA11 DDR_B_MA12 DDR_B_MA13 DDR_B_MA14

DDR_B_BS#0 14 DDR_B_BS#1 14 DDR_B_BS#2 14

DDR_B_RAS# 14 DDR_B_CAS# 14 DDR_B_WE# 14

DDR_B_DM[0..7] 14

DDR_B_DQS[0..7] 14

DDR_B_DQS#[0..7] 14

DDR_B_MA[0..14] 14

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2006/02/13 2006/03/10

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, M/B LA-4232P

401593

848Saturday, June 06, 2009

GMCH_ENBKL16

+3VS

D D

C C

3VDDCCL16 3VDDCDA16 CRT_HSYNC16

CRT_VSYNC16

+3VS

UMA@

UMA@ R483 2.2K_0402_5%

R483 2.2K_0402_5% UMA@

UMA@ R484 2.2K_0402_5%

R484 2.2K_0402_5%

B B

R74

0_0402_5%

VGA@

R76

0_0402_5%

VGA@

1 2

GMCH_EDID_CLK_LCD

GMCH_EDID_DAT_LCD

R75

0_0402_5%

VGA@

R81 10K_0402_5%UMA@R81 10K_0402_5% UMA@ R80 10K_0402_5%UMA@R80 10K_0402_5% UMA@

GMCH_EDID_CLK_LCD16 GMCH_EDID_DAT_LCD16

GMCH_LVDDEN16

GMCH_LVDSAC-16 GMCH_LVDSAC+16

GMCH_LVDSA0-16 GMCH_LVDSA1-16 GMCH_LVDSA2-16

GMCH_LVDSA0+16 GMCH_LVDSA1+16 GMCH_LVDSA2+16

CRT_B16 CRT_G16 CRT_R16

GMCH_ENBKL

1 2 1 2

GMCH_EDID_CLK_LCD GMCH_EDID_DAT_LCD

GMCH_LVDDEN

GMCH_LVDSACGMCH_LVDSAC+

GMCH_LVDSA0GMCH_LVDSA1GMCH_LVDSA2GMCH_LVDSA3-

T38T38

GMCH_LVDSA0+ GMCH_LVDSA1+ GMCH_LVDSA2+ GMCH_LVDSA3+

T46T46

for test point need

T45T45

CRT_B CRT_G CRT_R

R74

3VDDCCL 3VDDCDA CRT_HSYNC

CRT_VSYNC

0_0402_5%

R676

R676 VGA@

VGA@

CTRL_CLK CTRL_DATA

1 2

R94 2.4K_0402_1%~D

1 2

R6575_0402_1%

1 2

R6775_0402_1%

1 2

R6875_0402_1%

UMA@

UMA@ UMA@

UMA@

R76

UMA@

1 2

150_0402_1%

0_0402_5%

0_0402_5% R675

R675

VGA@

1 2

R65

0_0402_5%

VGA@

R68

0_0402_5%

VGA@

R75

1 2

UMA@

150_0402_1%

R334

R334 1K_0402_1%

1K_0402_1%

UMA@

1 2

L32 G32 M32

M33

K33

J33

M29

C44

B43

E37

E38

C41

C40

B37

A37

H47

E46 G40

A40

H48

D45

F40

B40

A41

H38 G37

J37

B42 G38

F37

K37

F25

H25

K25

H24

C31

E32

E28 G28

J28 G29

H32

J32

J29

E29

L29

R67

0_0402_5%

VGA@

U4C

L_BKLT_CTRL L_BKLT_EN L_CTRL_CLK

L_CTRL_DATA L_DDC_CLK L_DDC_DATA

L_VDD_EN LVDS_IBG LVDS_VBG LVDS_VREFH LVDS_VREFL LVDSA_CLK# LVDSA_CLK LVDSB_CLK# LVDSB_CLK

LVDSA_DATA#_0 LVDSA_DATA#_1 LVDSA_DATA#_2 LVDSA_DATA#_3

LVDSA_DATA_0 LVDSA_DATA_1 LVDSA_DATA_2 LVDSA_DATA_3

LVDSB_DATA#_0 LVDSB_DATA#_1 LVDSB_DATA#_2 LVDSB_DATA#_3

LVDSB_DATA_0 LVDSB_DATA_1 LVDSB_DATA_2 LVDSB_DATA_3

TVA_DAC TVB_DAC TVC_DAC

TV_RTN

TV_DCONSEL_0 TV_DCONSEL_1

CRT_BLUE CRT_GREEN CRT_RED CRT_IRTN CRT_DDC_CLK

CRT_DDC_DATA CRT_HSYNC CRT_TVO_IREF CRT_VSYNC

CANTIGA_1p0

R56 within 500 mils from pin T37,T36

T37

PEG_COMPI

T36

PEG_COMPO

PEG_RX#_0 PEG_RX#_1 PEG_RX#_2 PEG_RX#_3 PEG_RX#_4 PEG_RX#_5 PEG_RX#_6

LVDS

R334

0_0402_5%

VGA@

PEG_RX#_7 PEG_RX#_8

PEG_RX#_9 PEG_RX#_10 PEG_RX#_11 PEG_RX#_12 PEG_RX#_13 PEG_RX#_14 PEG_RX#_15

PEG_RX_0 PEG_RX_1 PEG_RX_2 PEG_RX_3 PEG_RX_4 PEG_RX_5 PEG_RX_6 PEG_RX_7 PEG_RX_8

PEG_RX_9 PEG_RX_10 PEG_RX_11 PEG_RX_12 PEG_RX_13 PEG_RX_14 PEG_RX_15

PEG_TX#_0 PEG_TX#_1 PEG_TX#_2 PEG_TX#_3 PEG_TX#_4 PEG_TX#_5 PEG_TX#_6 PEG_TX#_7 PEG_TX#_8

PEG_TX#_9 PEG_TX#_10 PEG_TX#_11 PEG_TX#_12

PCI-EXPRESS GRAPHICS

PEG_TX#_13 PEG_TX#_14 PEG_TX#_15

PEG_TX_0 PEG_TX_1 PEG_TX_2 PEG_TX_3

VGA

PEG_TX_4 PEG_TX_5 PEG_TX_6 PEG_TX_7 PEG_TX_8

PEG_TX_9 PEG_TX_10 PEG_TX_11 PEG_TX_12 PEG_TX_13 PEG_TX_14 PEG_TX_15

PEG_NRX_GTX_N0

H44

PEG_NRX_GTX_N1

J46

PEG_NRX_GTX_N2

L44

PEG_NRX_GTX_N3

L40

PEG_NRX_GTX_N4

N41

PEG_NRX_GTX_N5

P48

PEG_NRX_GTX_N6

N44

PEG_NRX_GTX_N7

T43

PEG_NRX_GTX_N8

U43

PEG_NRX_GTX_N9

Y43

PEG_NRX_GTX_N10

Y48

PEG_NRX_GTX_N11

Y36

PEG_NRX_GTX_N12

AA43

PEG_NRX_GTX_N13

AD37

PEG_NRX_GTX_N14

AC47

PEG_NRX_GTX_N15

AD39

PEG_NRX_GTX_P0

H43

PEG_NRX_GTX_P1

J44

PEG_NRX_GTX_P2

L43

PEG_NRX_GTX_P3

L41

PEG_NRX_GTX_P4

N40

PEG_NRX_GTX_P5

P47

PEG_NRX_GTX_P6

N43

PEG_NRX_GTX_P7

T42

PEG_NRX_GTX_P8

U42

PEG_NRX_GTX_P9

Y42

PEG_NRX_GTX_P10

W47

PEG_NRX_GTX_P11

Y37

PEG_NRX_GTX_P12

AA42

PEG_NRX_GTX_P13

AD36

PEG_NRX_GTX_P14

AC48

PEG_NRX_GTX_P15

AD40

PEG_TXN0

J41

PEG_TXN1

M46

PEG_TXN2

M47

PEG_TXN3

M40

PEG_TXN4

M42

PEG_TXN5 PEG_NTX_GRX_N5

R48

PEG_TXN6

N38

PEG_TXN7

T40

PEG_TXN8

U37

PEG_TXN9

U40

PEG_TXN10

Y40 AA46

PEG_TXN12

AA37

PEG_TXN13

AA40

PEG_TXN14

AD43

PEG_TXN15

AC46

PEG_TXP0

J42

PEG_TXP1

L46

PEG_TXP2

M48

PEG_TXP3

M39

PEG_TXP4

M43

PEG_TXP5

R47

PEG_TXP6

N37

PEG_TXP7

T39

PEG_TXP8

U36

PEG_TXP9

U39

PEG_TXP10

Y39

PEG_TXP11

Y46

PEG_TXP12

AA36

PEG_TXP13

AA39

PEG_TXP14

AD42

PEG_TXP15

AD46

R95

1 2

49.9_0402_1%

C568 0.1U_0402_16VVGA@C568 0.1U_0402_16VVGA@

1 2

C537 0.1U_0402_16VVGA@C537 0.1U_0402_16VVGA@

1 2

C538 0.1U_0402_16VVGA@C538 0.1U_0402_16VVGA@

1 2

C539 0.1U_0402_16VVGA@C539 0.1U_0402_16VVGA@

1 2

C540 0.1U_0402_16VVGA@C540 0.1U_0402_16VVGA@

1 2

C541 0.1U_0402_16VVGA@C541 0.1U_0402_16VVGA@

1 2

C542 0.1U_0402_16VVGA@C542 0.1U_0402_16VVGA@

1 2

C543 0.1U_0402_16VVGA@C543 0.1U_0402_16VVGA@

1 2

C544 0.1U_0402_16VVGA@C544 0.1U_0402_16VVGA@

1 2

C545 0.1U_0402_16VVGA@C545 0.1U_0402_16VVGA@

1 2

C546 0.1U_0402_16VVGA@C546 0.1U_0402_16VVGA@

1 2

C547 0.1U_0402_16VVGA@C547 0.1U_0402_16VVGA@

1 2

C548 0.1U_0402_16VVGA@C548 0.1U_0402_16VVGA@

1 2

C549 0.1U_0402_16VVGA@C549 0.1U_0402_16VVGA@

1 2

C550 0.1U_0402_16VVGA@C550 0.1U_0402_16VVGA@

1 2

C551 0.1U_0402_16VVGA@C551 0.1U_0402_16VVGA@

1 2

C552 0.1U_0402_16VVGA@C552 0.1U_0402_16VVGA@

1 2

C553 0.1U_0402_16VVGA@C553 0.1U_0402_16VVGA@

1 2

C554 0.1U_0402_16VVGA@C554 0.1U_0402_16VVGA@

1 2

C555 0.1U_0402_16VVGA@C555 0.1U_0402_16VVGA@

1 2

C556 0.1U_0402_16VVGA@C556 0.1U_0402_16VVGA@

1 2

C557 0.1U_0402_16VVGA@C557 0.1U_0402_16VVGA@

1 2

C558 0.1U_0402_16VVGA@C558 0.1U_0402_16VVGA@

1 2

C559 0.1U_0402_16VVGA@C559 0.1U_0402_16VVGA@

1 2

C560 0.1U_0402_16VVGA@C560 0.1U_0402_16VVGA@

1 2

C561 0.1U_0402_16VVGA@C561 0.1U_0402_16VVGA@

1 2

C562 0.1U_0402_16VVGA@C562 0.1U_0402_16VVGA@

1 2

C563 0.1U_0402_16VVGA@C563 0.1U_0402_16VVGA@

1 2

C564 0.1U_0402_16VVGA@C564 0.1U_0402_16VVGA@

1 2

C565 0.1U_0402_16VVGA@C565 0.1U_0402_16VVGA@

1 2

C566 0.1U_0402_16VVGA@C566 0.1U_0402_16VVGA@

1 2

C567 0.1U_0402_16VVGA@C567 0.1U_0402_16VVGA@

1 2

+VCC_PEG

PEG_NRX_GTX_N[0..15]

PEG_NRX_GTX_P[0..15]

PEGCOMP trace width and spacing is 20/25 mils.

PEG_NRX_GTX_N[0..15] 31

PEG_NRX_GTX_P[0..15] 31

PEG_NTX_GRX_N[0..15] 31

PEG_NTX_GRX_N0 PEG_NTX_GRX_N1 PEG_NTX_GRX_N2 PEG_NTX_GRX_N3 PEG_NTX_GRX_N4

PEG_NTX_GRX_N6 PEG_NTX_GRX_N7 PEG_NTX_GRX_N8

PEG_NTX_GRX_N9 PEG_NTX_GRX_N10 PEG_NTX_GRX_N11PEG_TXN11 PEG_NTX_GRX_N12 PEG_NTX_GRX_N13 PEG_NTX_GRX_N14 PEG_NTX_GRX_N15

PEG_NTX_GRX_P0 PEG_NTX_GRX_P1 PEG_NTX_GRX_P2 PEG_NTX_GRX_P3 PEG_NTX_GRX_P4 PEG_NTX_GRX_P5 PEG_NTX_GRX_P6 PEG_NTX_GRX_P7 PEG_NTX_GRX_P8

PEG_NTX_GRX_P9 PEG_NTX_GRX_P10 PEG_NTX_GRX_P11 PEG_NTX_GRX_P12 PEG_NTX_GRX_P13 PEG_NTX_GRX_P14 PEG_NTX_GRX_P15

PEG_NTX_GRX_P[0..15] 31

Strap Pin Table

CFG[2:0] FSB Freq select

CFG[4:3] Reserved

CFG5 (DMI select)

CFG6

CFG7 (Intel Management Engine Crypto strap)

CFG8

CFG9 (PCIE Graphics Lane Reversal)

CFG10 (PCIE Lookback enable)

CFG11 CFG[13:12] (XOR/ALLZ)

CFG16 (FSB Dynamic ODT)

CFG19 (DMI Lane Reversal)

CFG20 (PCIE/SDVO concurrent)

CFG57 CFG67 CFG77 CFG97 CFG167

CFG197 CFG207

CFG[19:20] have internal pulldown

000 = FSB 1066MHz 010 = FSB 800MHz 011 = FSB 667MHz Others = Reserved

0 = DMI x 2 1 = DMI x 4 0 = The iTPM Host Interface is enable

1 = The iTPM Host Interface is disable 0 =(TLS)chiper suite with no confidentiality 1 =(TLS)chiper suite with confidentiality

Reserved

0 = Reverse Lane,15->0, 14->1 1 = Normal Operation,Lane Number in order

0 = Enable 1 = Disable

Reserved 00 = Reserved

01 = XOR Mode Enabled 10 = All Z Mode Enabled

ReservedCFG[15:14]

0 = Disabled 1 = Enabled

ReservedCFG[18:17]

0 = Normal Operation

(Lane number in Order)

1 = Reverse Lane

0 = Only PCIE or SDVO is operational. 1 = PCIE/SDVO are operating simu.

R66 2.21K_0402_1%~D@R66 2.21K_0402_1%~D@

1 2

R58 2.21K_0402_1%~D@R58 2.21K_0402_1%~D@

1 2

R59 2.21K_0402_1%~D@R59 2.21K_0402_1%~D@

1 2

R55 2.21K_0402_1%~D@R55 2.21K_0402_1%~D@

1 2

R70 2.21K_0402_1%~D@R70 2.21K_0402_1%~D@

1 2

CFG[5:16] have internal pullup

R72 4.02K_0402_1%~D@R72 4.02K_0402_1%~D@ R73 4.02K_0402_1%~D@R73 4.02K_0402_1%~D@

1 2 1 2

+3VS

(Default)11 = Normal Operation

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2006/02/13 2006/03/10

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

SCHEMATIC, M/B LA-4232P

Size Document Number Rev

Custom

401593

Date: Sheet

948Saturday, June 06, 2009

+3VS_DAC_CRT

100U_D2_6.3VM_R45~D

C407

C219

UMA@C407

UMA@

D D

+3VS_DAC_BG

C405

UMA@C405

UMA@

C C

+3VS_DAC_CRT

0.01U_0402_16V7K

C401

UMA@C401

UMA@

B B

L11

1 2

BLM18PG181SN1D_0603

0.1U_0402_16V

0.01U_0402_16V7K

0.01U_0402_16V7K C411

UMA@C411

UMA@

R836 0_0402_5%~D

0.1U_0402_16V

0.01U_0402_16V7K

0.01U_0402_16V7K C408

UMA@C408

UMA@

+1.5VS

+VCCP

R50

1 2

0_0805_5%

C68

0.1U_0402_16V

C402

UMA@C402

UMA@

+3VS

UMA@L11

UMA@

1 2

COIL 2.2U +-20% IHLP-2525CZ-ER-2R2-M-01 8A

COIL 2.2U +-20% IHLP-2525CZ-ER-2R2-M-01 8A L15

@L15

+3VS_DAC_CRT

1 2

UMA@

+1.8V_TXLVDS

+1.5VS_PEG_BG

C175

0.1U_0402_16V

100U_D2E_6.3VM_R15M~D

R71

1 2

0_0603_5%

+1.05VS_PEGPLL

22U_0805_6.3V6M~D

HDMI disable connected to GND

C82

C83

4.7U_0805_10V4Z

+1.05VS_A_SM_CK

C104

C233 0.1U_0402_16VC233 0.1U_0402_16V

+1.05VS_A_SM

+3VS_DAC_BG

+1.05VS_DPLLA +1.05VS_DPLLB

+1.05VS_HPLL +1.05VS_MPLL

1000P_0402_50V7K

+1.05VS_PEGPLL

1U_0603_10V4Z

0.1U_0402_16V

C123

+3VS_DAC_CRT

+1.5VS_TVDAC +1.5VS_QDAC

+1.05VS_HPLL

+1.8V_LVDS

+3VS_DAC_CRT

C413

UMA@C413

UMA@

C72

TVA 24.15mA TVB 39.48mA TVX 24.15mA

58.67mA

48.363mA

157.2mA

60.31mA

U4H

VCC_AXF_1 VCC_AXF_2 VCC_AXF_3

AXF

VCC_SM_CK_1 VCC_SM_CK_2 VCC_SM_CK_3 VCC_SM_CK_4

SM CK

VCC_TX_LVDS

VCC_PEG_1 VCC_PEG_2 VCC_PEG_3 VCC_PEG_4 VCC_PEG_5

PEG

VCC_DMI_1 VCC_DMI_2 VCC_DMI_3 VCC_DMI_4

DMI

VTTLF

VTT_1 VTT_2 VTT_3 VTT_4 VTT_5 VTT_6 VTT_7 VTT_8

VTT_9 VTT_10 VTT_11 VTT_12 VTT_13 VTT_14 VTT_15

VTT

VTT_16 VTT_17 VTT_18 VTT_19 VTT_20 VTT_21 VTT_22 VTT_23 VTT_24 VTT_25

VCC_HV_1 VCC_HV_2 VCC_HV_3

VTTLF1 VTTLF2 VTTLF3

73mA

B27

VCCA_CRT_DAC_1

A26

VCCA_CRT_DAC_2

2.68mA

A25

VCCA_DAC_BG

B25

VSSA_DAC_BG

64.8mA

F47

64.8mA

139.2mA

13.2mA

720mA

50mA

VCCA_DPLLA

L48

VCCA_DPLLB

24mA

AD1

VCCA_HPLL

AE1

VCCA_MPLL

J48

VCCA_LVDS

J47

VSSA_LVDS

414uA

AD48

VCCA_PEG_BG

50mA

AA48

VCCA_PEG_PLL

AR20

VCCA_SM_1

AP20

VCCA_SM_2

AN20

VCCA_SM_3

AR17

VCCA_SM_4

AP17

VCCA_SM_5

AN17

VCCA_SM_6

AT16

VCCA_SM_7

AR16

VCCA_SM_8

AP16

VCCA_SM_9

26mA 321.35mA

AP28

VCCA_SM_CK_1

AN28

VCCA_SM_CK_2

AP25

VCCA_SM_CK_3

AN25

VCCA_SM_CK_4

AN24

VCCA_SM_CK_5

AM28

VCCA_SM_CK_NCTF_1

AM26

VCCA_SM_CK_NCTF_2

AM25

VCCA_SM_CK_NCTF_3

AL25

VCCA_SM_CK_NCTF_4

AM24

VCCA_SM_CK_NCTF_5

AL24

VCCA_SM_CK_NCTF_6

AM23

VCCA_SM_CK_NCTF_7

AL23

VCCA_SM_CK_NCTF_8

B24

VCCA_TV_DAC_1

A24

VCCA_TV_DAC_2

A32

VCC_HDA

M25

VCCD_TVDAC

L28

VCCD_QDAC

AF1

VCCD_HPLL

AA47

VCCD_PEG_PLL

M38

VCCD_LVDS_1

L37

VCCD_LVDS_2

CANTIGA_1p0

CRTPLLA PEGA SM

A LVDS

POWER

A CK

HDA

D TV/CRT

LVDS

852mA

U13 T13 U12 T12 U11 T11 U10 T10 U9 T9 U8 T8 U7 T7 U6 T6 U5 T5 V3 U3 V2 U2 T2 V1 U1

B22 B21 A21

124mA

BF21 BH20 BG20 BF20

118.8mA

K47 C35

B35 A35

V48 U48 V47 U47 U46

AH48 AF48 AH47 AG47

A8 L1 AB2

+VCCP

1732mA

456mA

20mils

0.47U_0603_10V7K

C382

220U_D2_4VY_R15M

+V1.05VS_AXF

+1.8V_SM_CK

+1.8V_TXLVDS

105.3mA

+VCC_PEG

+1.05VS_DMI

0.47U_0603_10V7K

C385

C370

C383

0.47U_0603_10V7K

C65

C384

C373

C410 C410

4.7U_0805_10V4Z

+3VS

0.1U_0402_16V

C56

2.2U_0805_16V4Z

220U_D2_4VY_R15M

C191

0.1U_0402_16V

+1.05VS_DPLLA

C173

UMA@

C174

C178

UMA@

0.1U_0402_16V

0.1U_0402_16V C182

C182

UMA@

L14

1 2

10U_0805_10V

UMA@

+1.05VS_HPLL

0.1U_0402_16V

C388

+1.05VS_MPLL

C63

+1.05VS_PEGPLL

0.1U_0402_16V

0.1U_0402_16V C176

C176

+VCCP

UMA@

L13

1 2

10U_0805_10V

10UH_LB2012T100MR_20%_0805~D

+VCCP+1.05VS_DPLLB

UMA@

10UH_LB2012T100MR_20%_0805~D

L29

1 2

MBK2012121YZF_0805

4.7U_0805_10V4Z

C387

1 2

LQH32CNR15M33L_1210~D

0_0603_5%

R97

1 2 1

C62

22U_0805_6.3V6M~D

L12

1 2

BLM21PG221SN1D_0805~D

R138

1_0402_5%~D

10U_0805_10V

C179

+VCCP

+V1.05VS_AXF

10U_0805_10V

+1.8V_SM_CK

1_0402_5%~D

C96

+1.5VS_TVDAC

UMA@ C115

UMA@

C115

+VCC_PEG

C95

+1.05VS_DMI

C113

R137

10U_0805_10V

UMA@ C114

UMA@

0.022U_0402_16V7K

C114

22U_0805_6.3V6M~D

220U_D2_4VY_R15M

R112

1 2

0_0603_5%

0.1U_0402_16V

C116

1U_0603_10V4Z

0.1U_0402_16V

C389

C117

+VCC_PEG

R101

1 2

0_0805_5%

C69

R102

1 2

0_0805_5%

C102

R64

1 2

0_0805_5% UMA@

PJP13

PJP13 JUMP_43X79@

JUMP_43X79@

112

4.7U_0805_10V4Z

+1.5VS

+VCCP

+1.8V

+VCCP

UMA@

+1.8V_LVDS

10U_0805_10V

C187

UMA@

R110

UMA@R110

UMA@

1 2

0_0603_5%

C186

1U_0603_10V4Z

+1.8V

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, M/B LA-4232P

401593

C413

C401

0_0402_5%

VGA@

A A

C405

0_0402_5%

VGA@

C407

0_0402_5%

VGA@

C413

0_0402_5%

VGA@

C173

0_0402_5%

VGA@

C174

0_0402_5%

VGA@

C115

0_0402_5%

VGA@

CRESTLINE_1p0

VGA@

C186

0_0603_5%

VGA@

+1.5VS_QDAC

1U_0402_6.3V6K~D

C98

C97

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

1 2

0.1U_0402_16V

2006/02/13 2006/03/10

+1.5VS

BLM18PG181SN1_0603~D

Compal Secret Data

Deciphered Date

+1.8V_TXLVDS

1000P_0402_50V7K

C414

C418

UMA@

R350

1 2

0_0603_5%

10U_0805_10V

UMA@

10 48Saturday, June 06, 2009

UMA@

+1.8V

U4F

AG34 AC34 AB34 AA34

AM33 AK33

AJ33 AG33 AF33

AE33 AC33 AA33

W33

AH28 AF28 AC28 AA28

AJ26 AG26 AE26 AC26 AH25 AG25 AF25 AG24

AJ23 AH23 AF23

Y34 V34 U34

Y33 V33

U33

T32

U4F

VCC_1 VCC_2 VCC_3 VCC_4 VCC_5 VCC_6 VCC_7 VCC_8 VCC_9 VCC_10 VCC_11 VCC_12

VCC_13 VCC_14 VCC_15 VCC_16 VCC_17 VCC_18 VCC_19 VCC_20 VCC_21 VCC_22 VCC_23 VCC_24 VCC_25 VCC_26 VCC_27 VCC_28 VCC_29 VCC_30 VCC_31 VCC_32 VCC_33 VCC_34

VCC_35

CANTIGA_1p0

+VCCP

D D

0.1U_0402_16V

0.22U_0402_10V

C143

C119

0.1U_0402_16V

C120

0.22U_0402_10V

22U_0805_6.3V6M~D

220U_D2_4VY_R15M

C118

C374

C C

B B

Extnal Graphic: 1210.34mA integrated Graphic: 1930.4mA

VCC CORE

VCC_NCTF_1 VCC_NCTF_2 VCC_NCTF_3 VCC_NCTF_4 VCC_NCTF_5 VCC_NCTF_6

POWER

VCC_NCTF_7 VCC_NCTF_8

VCC_NCTF_9 VCC_NCTF_10 VCC_NCTF_11 VCC_NCTF_12 VCC_NCTF_13 VCC_NCTF_14 VCC_NCTF_15 VCC_NCTF_16 VCC_NCTF_17 VCC_NCTF_18 VCC_NCTF_19 VCC_NCTF_20 VCC_NCTF_21 VCC_NCTF_22 VCC_NCTF_23 VCC_NCTF_24 VCC_NCTF_25 VCC_NCTF_26 VCC_NCTF_27 VCC_NCTF_28 VCC_NCTF_29 VCC_NCTF_30 VCC_NCTF_31

VCC NCTF

VCC_NCTF_32 VCC_NCTF_33 VCC_NCTF_34 VCC_NCTF_35 VCC_NCTF_36 VCC_NCTF_37 VCC_NCTF_38 VCC_NCTF_39 VCC_NCTF_40 VCC_NCTF_41 VCC_NCTF_42 VCC_NCTF_43 VCC_NCTF_44

AM32 AL32 AK32 AJ32 AH32 AG32 AE32 AC32 AA32 Y32 W32 U32 AM30 AL30 AK30 AH30 AG30 AF30 AE30 AC30 AB30 AA30 Y30 W30 V30 U30 AL29 AK29 AJ29 AH29 AG29 AE29 AC29 AA29 Y29 W29 V29 AL28 AK28 AL26 AK26 AK25 AK24 AK23

+VCCP

+1.8V

C148

330U_D2_2.5VY_R9M~D

+VCCP

C148

0.47U_0402_16V4Z~D

C99

Layout Note: Inside GMCH cavity for VCC_AXG.

0.1U_0402_10V7K~D

1U_0603_10V4Z~D

C66

C78

C165

22U_0805_6.3V6M~D

C165

22U_0805_6.3V6M~D

C147

22U_0805_6.3V6M~D

C147

22U_0805_6.3V6M~D

0317 change value

0.1U_0402_10V7K~D

10U_0805_10V

C100

C79

U4G

3000mA

AP33

VCC_SM_1

AN33

VCC_SM_2

BH32

VCC_SM_3

BG32

0.1U_0402_10V7K~D

C164

22U_0805_6.3VAM~D

C80

T42PAD T42PAD T43PAD T43PAD

BF32 BD32 BC32 BB32 BA32 AY32

AW32

AV32 AU32 AT32 AR32 AP32 AN32 BH31 BG31 BF31 BG30 BH29 BG29 BF29 BD29 BC29 BB29 BA29 AY29

AW29

AV29 AU29 AT29 AR29 AP29

BA36 BB24 BD16

BB21 AW16 AW13

AT13

AE25

AB25

AA25

AE24

AC24

AA24

AE23

AC23

AB23

AA23

AJ21

AG21

AE21

AC21

AA21

AH20

AF20

AE20

AC20

AB20

AA20

AM15

AL15

AE15

AJ15

AH15

AG15

AF15

AB15

AA15

AN14 AM14

AJ14

AH14

Y26

Y24

Y21

T17 T16

Y15 V15 U15

U14 T14

VCC_SM_4 VCC_SM_5 VCC_SM_6 VCC_SM_7 VCC_SM_8 VCC_SM_9 VCC_SM_10 VCC_SM_11 VCC_SM_12 VCC_SM_13 VCC_SM_14 VCC_SM_15 VCC_SM_16 VCC_SM_17 VCC_SM_18 VCC_SM_19 VCC_SM_20 VCC_SM_21 VCC_SM_22 VCC_SM_23 VCC_SM_24 VCC_SM_25 VCC_SM_26 VCC_SM_27 VCC_SM_28 VCC_SM_29 VCC_SM_30 VCC_SM_31 VCC_SM_32 VCC_SM_33 VCC_SM_34 VCC_SM_35

VCC_SM_36/NC VCC_SM_37/NC VCC_SM_38/NC VCC_SM_39/NC VCC_SM_40/NC VCC_SM_41/NC VCC_SM_42/NC

6326.84mA

VCC_AXG_1 VCC_AXG_2 VCC_AXG_3 VCC_AXG_4 VCC_AXG_5 VCC_AXG_6 VCC_AXG_7 VCC_AXG_8 VCC_AXG_9 VCC_AXG_10 VCC_AXG_11 VCC_AXG_12 VCC_AXG_13 VCC_AXG_14 VCC_AXG_15 VCC_AXG_16 VCC_AXG_17 VCC_AXG_18 VCC_AXG_19 VCC_AXG_20 VCC_AXG_21 VCC_AXG_22 VCC_AXG_23 VCC_AXG_24 VCC_AXG_25 VCC_AXG_26 VCC_AXG_27 VCC_AXG_28 VCC_AXG_29 VCC_AXG_30 VCC_AXG_31 VCC_AXG_32 VCC_AXG_33 VCC_AXG_34 VCC_AXG_35 VCC_AXG_36 VCC_AXG_37 VCC_AXG_38 VCC_AXG_39 VCC_AXG_40 VCC_AXG_41 VCC_AXG_42

VCC_AXG_SENSE VSS_AXG_SENSE

VCC_AXG_NCTF_10 VCC_AXG_NCTF_11 VCC_AXG_NCTF_12 VCC_AXG_NCTF_13 VCC_AXG_NCTF_14 VCC_AXG_NCTF_15 VCC_AXG_NCTF_16 VCC_AXG_NCTF_17 VCC_AXG_NCTF_18 VCC_AXG_NCTF_19 VCC_AXG_NCTF_20 VCC_AXG_NCTF_21 VCC_AXG_NCTF_22

POWER

VCC_AXG_NCTF_23 VCC_AXG_NCTF_24 VCC_AXG_NCTF_25 VCC_AXG_NCTF_26 VCC_AXG_NCTF_27 VCC_AXG_NCTF_28 VCC_AXG_NCTF_29 VCC_AXG_NCTF_30

VCC SMVCC GFX

VCC_AXG_NCTF_31 VCC_AXG_NCTF_32 VCC_AXG_NCTF_33 VCC_AXG_NCTF_34 VCC_AXG_NCTF_35 VCC_AXG_NCTF_36 VCC_AXG_NCTF_37 VCC_AXG_NCTF_38 VCC_AXG_NCTF_39 VCC_AXG_NCTF_40 VCC_AXG_NCTF_41 VCC_AXG_NCTF_42 VCC_AXG_NCTF_43 VCC_AXG_NCTF_44 VCC_AXG_NCTF_45 VCC_AXG_NCTF_46 VCC_AXG_NCTF_47 VCC_AXG_NCTF_48 VCC_AXG_NCTF_49 VCC_AXG_NCTF_50 VCC_AXG_NCTF_51 VCC_AXG_NCTF_52 VCC_AXG_NCTF_53 VCC_AXG_NCTF_54 VCC_AXG_NCTF_55 VCC_AXG_NCTF_56

VCC GFX NCTF

VCC_AXG_NCTF_57 VCC_AXG_NCTF_58 VCC_AXG_NCTF_59 VCC_AXG_NCTF_60

VCC_AXG_NCTF_1 VCC_AXG_NCTF_2 VCC_AXG_NCTF_3 VCC_AXG_NCTF_4 VCC_AXG_NCTF_5 VCC_AXG_NCTF_6 VCC_AXG_NCTF_7 VCC_AXG_NCTF_8 VCC_AXG_NCTF_9

VCC_SM_LF1 VCC_SM_LF2 VCC_SM_LF3 VCC_SM_LF4 VCC_SM_LF5 VCC_SM_LF6 VCC_SM_LF7

VCC SM LF

W28 V28 W26 V26 W25 V25 W24 V24 W23 V23 AM21 AL21 AK21 W21 V21 U21 AM20 AK20 W20 U20 AM19 AL19 AK19 AJ19 AH19 AG19 AF19 AE19 AB19 AA19 Y19 W19 V19 U19 AM17 AK17 AH17 AG17 AF17 AE17 AC17 AB17 Y17 W17 V17 AM16 AL16 AK16 AJ16 AH16 AG16 AF16 AE16 AC16 AB16 AA16 Y16 W16 V16 U16

AV44 BA37 AM40 AV21 AY5 AM10 BB13

VCCSM_LF1 VCCSM_LF2 VCCSM_LF3 VCCSM_LF4 VCCSM_LF5 VCCSM_LF6 VCCSM_LF7

+VCCP

330U_D2_2.5VY_R15M

C86

C71 0.1U_0402_16VC71 0.1U_0402_16V

C70 0.1U_0402_16VC70 0.1U_0402_16V

330U_D2_2.5VY_R15M

Layout Note:

C57

Place close to GMCH

C67 0.22U_0603_10V7KC67 0.22U_0603_10V7K

C146 0.47U_0402_6.3V6KC146 0.47U_0402_6.3V6K

C81 0.22U_0603_10V7KC81 0.22U_0603_10V7K

C163 1U_0603_10V4ZC163 1U_0603_10V4Z

C145 1U_0603_10V4ZC145 1U_0603_10V4Z

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2006/02/13 2006/03/10

Compal Secret Data

CANTIGA_1p0

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, M/B LA-4232P

401593

11 48Saturday, June 06, 2009

U4I

AU48

VSS_1

D D

C C

B B

A A

AR48

AL48

BB47

AW47

AN47

AJ47 AF47 AD47 AB47

BD46 BA46 AY46 AV46 AR46

AM46

BF44 AH44 AD44 AA44

BC43 AV43 AU43

AM43

BG42 AY42 AT42 AN42

AJ42 AE42

BD41 AU41

AM41

AH41 AD41 AA41

BG40 BB40 AV40 AN40

AT39

AM39

AJ39 AE39

BH38 BC38 BA38 AU38 AH38 AD38 AA38

BF37 BB37

AW37

AT37 AN37

AJ37

BG36 BD36 AK15 AU36

Y47 T47

N47

L47

G47

V46

R46

P46

H46

F46

Y44

U44

T44

M44

F44

J43

C43

N42

L42

Y41

U41

T41 M41 G41

B41

H40

E40

N39

L39

B39

Y38 U38

T38

J38

F38 C38

H37 C37

VSS_2 VSS_3 VSS_4 VSS_5 VSS_6 VSS_7 VSS_8 VSS_9 VSS_10 VSS_11 VSS_12 VSS_13 VSS_14 VSS_15 VSS_16 VSS_17 VSS_18 VSS_19 VSS_20 VSS_21 VSS_22 VSS_23 VSS_24 VSS_25 VSS_26 VSS_27 VSS_28 VSS_29 VSS_30 VSS_31 VSS_32 VSS_33 VSS_34 VSS_35 VSS_36 VSS_37 VSS_38 VSS_39 VSS_40 VSS_41 VSS_42 VSS_43 VSS_44 VSS_45 VSS_46 VSS_47 VSS_48 VSS_49 VSS_50 VSS_51 VSS_52 VSS_53 VSS_54 VSS_55 VSS_56 VSS_57 VSS_58 VSS_59 VSS_60 VSS_61 VSS_62 VSS_63 VSS_64 VSS_65 VSS_66 VSS_67 VSS_68 VSS_69 VSS_70 VSS_71 VSS_72 VSS_73 VSS_74 VSS_75 VSS_76 VSS_77 VSS_78 VSS_79 VSS_80 VSS_81 VSS_82 VSS_83 VSS_84 VSS_85 VSS_86 VSS_87 VSS_88 VSS_89 VSS_90 VSS_91 VSS_92 VSS_93 VSS_94 VSS_95 VSS_96 VSS_97 VSS_98 VSS_99

CANTIGA_1p0

VSS

VSS_100 VSS_101 VSS_102 VSS_103 VSS_104 VSS_105 VSS_106 VSS_107 VSS_108 VSS_109 VSS_110 VSS_111 VSS_112 VSS_113 VSS_114 VSS_115 VSS_116 VSS_117 VSS_118 VSS_119 VSS_120 VSS_121 VSS_122 VSS_123 VSS_124 VSS_125 VSS_126 VSS_127 VSS_128 VSS_129 VSS_130 VSS_131 VSS_132 VSS_133 VSS_134 VSS_135 VSS_136 VSS_137 VSS_138 VSS_139 VSS_140 VSS_141 VSS_142 VSS_143 VSS_144 VSS_145 VSS_146 VSS_147 VSS_148 VSS_149 VSS_150 VSS_151 VSS_152 VSS_153 VSS_154 VSS_155 VSS_156 VSS_157 VSS_158 VSS_159 VSS_160 VSS_161 VSS_162 VSS_163 VSS_164 VSS_165 VSS_166 VSS_167 VSS_168 VSS_169 VSS_170 VSS_171 VSS_172 VSS_173 VSS_174 VSS_175 VSS_176 VSS_177 VSS_178 VSS_179 VSS_180 VSS_181 VSS_182 VSS_183 VSS_184 VSS_185 VSS_186 VSS_187 VSS_188 VSS_189 VSS_190 VSS_191 VSS_192 VSS_193 VSS_194 VSS_195 VSS_196 VSS_197 VSS_198 VSS_199

AM36 AE36 P36 L36 J36 F36 B36 AH35 AA35 Y35 U35 T35 BF34 AM34 AJ34 AF34 AE34 W34 B34 A34 BG33 BC33 BA33 AV33 AR33 AL33 AH33 AB33 P33 L33 H33 N32 K32 F32 C32 A31 AN29 T29 N29 K29 H29 F29 A29 BG28 BD28 BA28 AV28 AT28 AR28 AJ28 AG28 AE28 AB28 Y28 P28 K28 H28 F28 C28 BF26 AH26 AF26 AB26 AA26 C26 B26 BH25 BD25 BB25 AV25 AR25 AJ25 AC25 Y25 N25 L25 J25 G25 E25 BF24 AD12 AY24 AT24 AJ24 AH24 AF24 AB24 R24 L24 K24 J24 G24 F24 E24 BH23 AG23 Y23 B23 A23 AJ6

U4J

BG21

VSS_199

L12

VSS_200

AW21

VSS_201

AU21

VSS_202

AP21

VSS_203

AN21

VSS_204

AH21

VSS_205

AF21

VSS_206

AB21

VSS_207

R21

VSS_208

M21

VSS_209

J21

VSS_210

G21

VSS_211

BC20

VSS_212

BA20

VSS_213

AW20

VSS_214

AT20

VSS_215

AJ20

VSS_216

AG20

VSS_217

Y20

VSS_218

N20

VSS_219

K20

VSS_220

F20

VSS_221

C20

VSS_222

A20

VSS_223

BG19

VSS_224

A18

VSS_225

BG17

VSS_226

BC17

VSS_227

AW17

VSS_228

AT17

VSS_229

BA16 AU16

AN16

BG15 AC15

BG14 AA14

BG13 BC13 BA13

AN13 AE13

BF12 AV12 AT12

AM12

AA12

BD11 BB11 AY11 AN11 AH11

BG10 AV10 AT10

AE10 AA10

R17

M17

H17 C17

N16 K16 G16 E16

W15

A15

C14

AJ13

N13 L13 G13 E13

A12

Y11 N11 G11 C11

AJ10

M10

BF9 BC9 AN9

AM9

AD9

BH8 BB8 AV8 AT8

J12

VSS_230 VSS_231 VSS_232 VSS_233

VSS_235 VSS_237

VSS_238 VSS_239 VSS_240 VSS_241 VSS_242 VSS_243 VSS_244 VSS_245 VSS_246 VSS_247 VSS_248 VSS_249 VSS_250 VSS_251 VSS_252

VSS_255 VSS_256 VSS_257 VSS_258 VSS_259 VSS_260 VSS_261 VSS_262 VSS_263 VSS_264 VSS_265 VSS_266 VSS_267 VSS_268 VSS_269 VSS_270 VSS_271 VSS_272 VSS_273

VSS_275 VSS_276 VSS_277 VSS_278 VSS_279 VSS_280 VSS_281 VSS_282 VSS_283 VSS_284 VSS_285 VSS_286 VSS_287 VSS_288 VSS_289 VSS_290 VSS_291 VSS_292 VSS_293 VSS_294 VSS_295 VSS_296

CANTIGA_1p0

VSS

VSS NCTF

VSS SCB

VSS_297 VSS_298 VSS_299 VSS_300 VSS_301 VSS_302 VSS_303 VSS_304 VSS_305 VSS_306 VSS_307 VSS_308 VSS_309 VSS_310 VSS_311 VSS_312 VSS_313 VSS_314 VSS_315 VSS_316 VSS_317 VSS_318 VSS_319 VSS_320 VSS_321 VSS_322 VSS_323 VSS_324 VSS_325

VSS_327 VSS_328 VSS_329 VSS_330 VSS_331 VSS_332 VSS_333 VSS_334 VSS_335 VSS_336 VSS_337 VSS_338 VSS_339 VSS_340 VSS_341 VSS_342 VSS_343 VSS_344 VSS_345 VSS_346 VSS_347 VSS_348 VSS_349 VSS_350

VSS_351 VSS_352 VSS_353 VSS_354

VSS_NCTF_1 VSS_NCTF_2 VSS_NCTF_3 VSS_NCTF_4 VSS_NCTF_5 VSS_NCTF_6 VSS_NCTF_7 VSS_NCTF_8

VSS_NCTF_9 VSS_NCTF_10 VSS_NCTF_11 VSS_NCTF_12 VSS_NCTF_13 VSS_NCTF_14 VSS_NCTF_15 VSS_NCTF_16

VSS_SCB_1 VSS_SCB_2 VSS_SCB_3 VSS_SCB_4 VSS_SCB_5

NC_26 NC_27 NC_28 NC_29 NC_30 NC_31 NC_32 NC_33 NC_34 NC_35 NC_36 NC_37 NC_38 NC_39 NC_40 NC_41 NC_42

AH8 Y8 L8 E8 B8 AY7 AU7 AN7 AJ7 AE7 AA7 N7 J7 BG6 BD6 AV6 AT6 AM6 M6 C6 BA5 AH5 AD5 Y5 L5 J5 H5 F5 BE4

BC3 AV3 AL3 R3 P3 F3 BA2 AW2 AU2 AR2 AP2 AJ2 AH2 AF2 AE2 AD2 AC2 Y2 M2 K2 AM1 AA1 P1 H1

U24 U28 U25 U29

AF32 AB32 V32 AJ30 AM29 AF29 AB29 U26 U23 AL20 V20 AC19 AL17 AJ17 AA17 U17

BH48 BH1 A48 C1 A3

E1 D2 C3 B4 A5 A6 A43 A44 B45 C46 D47 B47 A46 F48 E48 C48 B48

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2006/02/13 2006/03/10

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, M/B LA-4232P

401593

12 48Saturday, June 06, 2009

DDR_A_DQS#[0..7]8

DDR_A_D[0..63]8

DDR_A_DM[0..7]8 DDR_A_DQS[0..7]8 DDR_A_MA[0..13]8

D D

Layout Note: Place near JDIM1

+1.8V

2.2U_0603_6.3V6K

2.2U_0603_6.3V6K C105

C105

Layout Note:

C C

Place one cap close to every 2 pullup resistors terminated to +0.9V

+0.9VS

0.1U_0402_16V

C106

B B

DDR_A_MA5 DDR_A_MA8

DDR_A_MA1 DDR_A_MA3

DDR_A_RAS# DDR_CS0_DIMMA#

DDR_A_BS#0

A A

DDR_A_MA10

DDR_A_CAS# DDR_A_WE#

DDR_CS1_DIMMA# M_ODT1

DDR_CKE1_DIMMA

2.2U_0603_6.3V6K

C124

C149

0.1U_0402_16V

C125

C126

RP14

1 4 2 3

RP13

56_0404_4P2R_5%

56_0404_4P2R_5% 1 4 2 3

RP7

56_0404_4P2R_5%

56_0404_4P2R_5% 1 4 2 3

RP6

56_0404_4P2R_5%

56_0404_4P2R_5% 1 4 2 3

RP5

56_0404_4P2R_5%

56_0404_4P2R_5% 1 4 2 3

56_0404_4P2R_5%

RP1

2 3 1 4

56_0404_4P2R_5%

56_0404_4P2R_5% 1 2

R96 56_0402_5%

2.2U_0603_6.3V6K

2.2U_0603_6.3V6K 1

0.1U_0402_16V

C127

+0.9VS

2.2U_0603_6.3V6K

2.2U_0603_6.3V6K C169

C169

C166

0.1U_0402_16V

C151

C150

RP22 56_0404_4P2R_5%RP22 56_0404_4P2R_5%

14 23

RP17 56_0404_4P2R_5%RP17 56_0404_4P2R_5%

14 23

RP15 56_0404_4P2R_5%RP15 56_0404_4P2R_5%

14 23

RP16 56_0404_4P2R_5%RP16 56_0404_4P2R_5%

14 23

RP8 56_0404_4P2R_5%RP8 56_0404_4P2R_5%

14 23

RP2 56_0404_4P2R_5%RP2 56_0404_4P2R_5%

14 23

RP23 56_0404_4P2R_5%RP23 56_0404_4P2R_5%

14 23

0.1U_0402_16V

C154

0.1U_0402_16V

C167

DDR_A_MA12 DDR_CKE0_DIMMA

DDR_A_MA7 DDR_A_MA6

DDR_A_MA9 DDR_A_BS#2

DDR_A_MA4 DDR_A_MA2

DDR_A_MA0 DDR_A_BS#1

M_ODT0 DDR_A_MA13

DDR_A_MA14 DDR_A_MA11

C131

C107

0.1U_0402_16V

0.1U_0402_16V C130

C130

0.1U_0402_16V

C128

330U 2.5V Y D2

0.1U_0402_16V

0.1U_0402_16V C108

C108

0.1U_0402_16V

C152

C129

Layout Note: Place these resistor closely JP41,all trace length Max=1.5"

C84

C153

0.1U_0402_16V

C168

+1.8V

JDIM2

VREF

3 DDR_A_D4 DDR_A_D1

DDR_A_DQS#0 DDR_A_DQS0

DDR_A_D2 DDR_A_D3

DDR_A_D8 DDR_A_D9

DDR_A_DQS#1 DDR_A_DQS1

DDR_A_D14

DDR_A_D16 DDR_A_D17

DDR_A_DQS#2 DDR_A_DQS2

DDR_A_D18 DDR_A_D19

DDR_A_D29 DDR_A_D24

DDR_A_DM3

DDR_A_D26 DDR_A_D27

+3VS

0.1U_0402_16V

DDR_CKE0_DIMMA

DDR_A_BS#2 DDR_A_MA12 DDR_A_MA8 DDR_A_MA5

DDR_A_MA3 DDR_A_MA1

DDR_A_MA10 DDR_A_BS#0

DDR_A_CAS# DDR_CS1_DIMMA#

M_ODT1 DDR_A_D37

DDR_A_D36 DDR_A_DQS#4

DDR_A_DQS4 DDR_A_D35

DDR_A_D34 DDR_A_D40

DDR_A_D44 DDR_A_DM5 DDR_A_D41

DDR_A_D46 DDR_A_D49

DDR_A_D48

DDR_A_DQS#6 DDR_A_DQS6

DDR_A_D54 DDR_A_D50

DDR_A_D61 DDR_A_D60

DDR_A_DM7 DDR_A_D59

DDR_A_D58 ICH_SM_DA

ICH_SM_CLK

C58

C59

2.2U_0603_6.3V6K

DDR_CKE0_DIMMA7

DDR_A_BS#28

DDR_A_BS#08

DDR_A_WE#8

DDR_A_CAS#8

DDR_CS1_DIMMA#7

M_ODT17

ICH_SM_DA14,15,19

ICH_SM_CLK14,15,19

VSS

DQ0

DQ1

VSS

DQS0#

DQS0

VSS

DQ2

DQ3

VSS

DQ8

DQ9

VSS

DQS1#

DQS1

VSS

DQ10

DQ11

VSS

DQ16

DQ17

VSS

DQS2#

DQS2

VSS

DQ18

DQ19

VSS

DQ24

DQ25

VSS

DM3

VSS

DQ26

DQ27

VSS

CKE0

VDD

BA2

VDD

A12

VDD

101

103

VDD

105

A10/AP

107

BA0

109

WE#

111

VDD

113

CAS#

115

NC/S1#

117

VDD

119

NC/ODT1

121

VSS

123

DQ32

125

DQ33

127

VSS

129

DQS4#

131

DQS4

133

VSS

135

DQ34

137

DQ35

139

VSS

141

DQ40

143

DQ41

145

VSS

147

DM5

149

VSS

151

DQ42

153

DQ43

155

VSS

157

DQ48

159

DQ49

161

VSS

163

NC,TEST

165

VSS

167

DQS6#

169

DQS6

171

VSS

173

DQ50

175

DQ51

177

VSS

179

DQ56

181

DQ57

183

VSS

185

DM7

187

VSS

189

DQ58

191

DQ59

193

VSS

195

SDA

197

SCL

199

VDDSPD

FOX_ASOA426-M2RN-7F

SO-DIMM A

REVERSE

VSS DQ4 DQ5 VSS DM0 VSS DQ6 DQ7

VSS DQ12 DQ13

VSS

DM1

VSS

CK0

CK0#

VSS DQ14 DQ15

VSS

VSS DQ20 DQ21

VSS

DM2

VSS DQ22 DQ23

VSS DQ28 DQ29

VSS

DQS3#

DQS3

VSS DQ30 DQ31

VSS

NC/CKE1

VDD

NC/A15 NC/A14

VDD

BA1

RAS#

VDD ODT0

NC/A13

VDD

VSS DQ36 DQ37

VSS

DM4

VSS DQ38 DQ39

VSS DQ44 DQ45

VSS

DQS5#

DQS5

VSS DQ46 DQ47

VSS DQ52 DQ53

VSS

CK1

CK1#

VSS

DM6

VSS DQ54 DQ55

VSS DQ60 DQ61

VSS

DQS7#

DQS7

VSS DQ62 DQ63

VSS

SA0

SA1

DDR_A_D5

DDR_A_D0

6 8

DDR_A_DM0

10 12

DDR_A_D6

DDR_A_D7

16 18

DDR_A_D13

DDR_A_D12

22 24

DDR_A_DM1

26 28

M_CLK_DDR0

M_CLK_DDR#0

32 34

DDR_A_D11

DDR_A_D10DDR_A_D15

38 40

DDR_A_D20

DDR_A_D21

46 48 50

A11

A7 A6

A4 A2 A0

S0#

DDR_A_DM2

52 54

DDR_A_D23

DDR_A_D22

58 60

DDR_A_D28

DDR_A_D25

64 66

DDR_A_DQS#3

DDR_A_DQS3

70 72

DDR_A_D31

DDR_A_D30

76 78

DDR_CKE1_DIMMA

80 82 84

DDR_A_MA14

86 88

DDR_A_MA11

DDR_A_MA7DDR_A_MA9

DDR_A_MA6

94 96

DDR_A_MA4

DDR_A_MA2

100

DDR_A_MA0

102 104

DDR_A_BS#1

106

DDR_A_RAS#

108

DDR_CS0_DIMMA#DDR_A_WE#

110 112

M_ODT0

114

DDR_A_MA13

116 118 120 122

DDR_A_D32

124

DDR_A_D33

126 128

DDR_A_DM4

130 132

DDR_A_D39

134

DDR_A_D38

136 138

DDR_A_D45

140

DDR_A_D47

142 144

DDR_A_DQS#5

146

DDR_A_DQS5

148 150

DDR_A_D43

152

DDR_A_D42

154 156

DDR_A_D52

158

DDR_A_D53

160 162

M_CLK_DDR1

164

M_CLK_DDR#1

166 168

DDR_A_DM6

170 172

DDR_A_D51

174

DDR_A_D55

176 178

DDR_A_D57

180

DDR_A_D56

182 184

DDR_A_DQS#7

186

DDR_A_DQS7

188 190

DDR_A_D62

192

DDR_A_D63

194 196 198 200

R31

10K_0402_5%

Bottom side

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2007/1/15 2008/1/15

Compal Secret Data

Deciphered Date

Close to VREF pins of SO-DIMM

2.2U_0805_16V4Z

M_CLK_DDR0 7 M_CLK_DDR#0 7

PM_EXTTS#0 7

DDR_CKE1_DIMMA 7

DDR_A_MA14 8

DDR_A_BS#1 8 DDR_A_RAS# 8 DDR_CS0_DIMMA# 7

M_ODT0 7

M_CLK_DDR1 7 M_CLK_DDR#1 7

R32

10K_0402_5%

Custom

Date: Sheet

Date: Sheet of

0.1U_0402_16V

C201

C220

Title

Size Document Number Rev

C220

Compal Electronics, Inc.

SCHEMATIC, M/B LA-4232P

401593

+V_DDR_MCH_REF 7,14

13 48Saturday, June 06, 2009

DDR_B_DQS#[0..7]8

DDR_B_D[0..63]8 DDR_B_DM[0..7]8

DDR_B_DQS[0..7]8

DDR_B_MA[0..13]8

D D

Layout Note: Place near JDIM2

+1.8V

2.2U_0603_6.3V6K

Layout Note: Place one cap close to every 2 pullup resistors terminated to +0.9VS

C C

+0.9VS

0.1U_0402_16V

B B

DDR_B_MA3 DDR_B_MA1

DDR_B_BS#0 DDR_B_MA10

DDR_B_MA0 DDR_B_BS#1

DDR_B_RAS# DDR_CS2_DIMMB#

A A

DDR_B_CAS# DDR_B_WE#

DDR_CS3_DIMMB# M_ODT3

DDR_CKE3_DIMMB

C112

0.1U_0402_16V

C110

C139

0.1U_0402_16V

C134

RP18

RP10

RP12

RP11

RP9

RP3

R335 56_0402_5%

C160

0.1U_0402_16V

C135

1 4 2 3

56_0404_4P2R_5%

56_0404_4P2R_5% 1 4 2 3

56_0404_4P2R_5%

56_0404_4P2R_5% 1 4 2 3

56_0404_4P2R_5%

56_0404_4P2R_5% 1 4 2 3

56_0404_4P2R_5%

56_0404_4P2R_5% 1 4 2 3

56_0404_4P2R_5%

56_0404_4P2R_5% 2 3 1 4

56_0404_4P2R_5%

56_0404_4P2R_5% 1 2

2.2U_0603_6.3V6K

0.1U_0402_16V

C156

+0.9VS

2.2U_0603_6.3V6K

0.1U_0402_16V

C138

C157

0.1U_0402_16V

C177

0.1U_0402_16V

C171

C170

RP24 56_0404_4P2R_5%RP24 56_0404_4P2R_5%

DDR_B_MA12

DDR_B_MA9

RP26 56_0404_4P2R_5%RP26 56_0404_4P2R_5%

DDR_B_MA14

DDR_B_MA11

RP19 56_0404_4P2R_5%RP19 56_0404_4P2R_5%

DDR_B_MA5

DDR_B_MA8

RP21 56_0404_4P2R_5%RP21 56_0404_4P2R_5%

DDR_B_MA7

DDR_B_MA6

RP20 56_0404_4P2R_5%RP20 56_0404_4P2R_5%

DDR_B_MA4

DDR_B_MA2

RP4 56_0404_4P2R_5%RP4 56_0404_4P2R_5%

DDR_B_MA13

M_ODT2

RP25

DDR_B_BS#2

DDR_CKE2_DIMMB

56_0404_4P2R_5%

0.1U_0402_16V

C109

0.1U_0402_16V

C111

C132

0.1U_0402_16V

C136

0.1U_0402_16V

0.1U_0402_16V C133

C133

0.1U_0402_16V

C158

Layout Note: Place these resistor closely JP42,all trace length Max=1.5"

0.1U_0402_16V

0.1U_0402_16V C155

C155

0.1U_0402_16V

C137

330U 2.5V Y D2

C172

+1.8V

JDIM1

VREF

3 DDR_B_D0 DDR_B_D1

DDR_B_DQS#0 DDR_B_DQS0

DDR_B_D2 DDR_B_D3

DDR_B_D8 DDR_B_D9

DDR_B_DQS#1 DDR_B_DQS1

DDR_B_D10 DDR_B_D11

DDR_B_D17

C189

DDR_CKE2_DIMMB7

DDR_B_BS#28

DDR_B_BS#08

0.1U_0402_16V

C159

DDR_B_CAS#8

DDR_CS3_DIMMB#7

C199

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

ICH_SM_DA13,15,19

ICH_SM_CLK13,15,19

Issued Date

M_ODT37

DDR_B_D20 DDR_B_DQS#2

DDR_B_DQS2 DDR_B_D18

DDR_B_D19 DDR_B_D28

DDR_B_D25 DDR_B_DM3

DDR_B_D30 DDR_B_D31

DDR_CKE2_DIMMB

DDR_B_BS#2 DDR_B_MA12

DDR_B_MA9 DDR_B_MA8

DDR_B_MA5 DDR_B_MA3 DDR_B_MA1

DDR_B_MA10 DDR_B_BS#0 DDR_B_WE#

DDR_B_CAS# DDR_CS3_DIMMB#

M_ODT3 DDR_B_D32

DDR_B_D33 DDR_B_DQS#4

DDR_B_DQS4 DDR_B_D34

DDR_B_D35 DDR_B_D40

DDR_B_D41 DDR_B_DM5 DDR_B_D42

DDR_B_D43 DDR_B_D48

DDR_B_D49

DDR_B_DQS#6 DDR_B_DQS6

DDR_B_D51 DDR_B_D50

DDR_B_D56 DDR_B_D61

DDR_B_DM7 DDR_B_D59

DDR_B_D58 ICH_SM_DA

ICH_SM_CLK

+3VS

C60

2.2U_0603_6.3V6K

2007/1/15 2008/1/15

0.1U_0402_16V

C61

VSS

DQ0

DQ1

VSS

DQS0#

DQS0

VSS

DQ2

DQ3

VSS

DQ8

DQ9

VSS

DQS1#

DQS1

VSS

DQ10

DQ11

VSS

DQ16

DQ17

VSS

DQS2#

DQS2

VSS

DQ18

DQ19

VSS

DQ24

DQ25

VSS

DM3

VSS

DQ26

DQ27

VSS

CKE0

VDD

BA2

VDD

A12

VDD

101

103

VDD

105

A10/AP

107

BA0

109

WE#

111

VDD

113

CAS#

115

NC/S1#

117

VDD

119

NC/ODT1

121

VSS

123

DQ32

125

DQ33

127

VSS

129

DQS4#

131

DQS4

133

VSS

135

DQ34

137

DQ35

139

VSS

141

DQ40

143

DQ41

145

VSS

147

DM5

149

VSS

151

DQ42

153

DQ43

155

VSS

157

DQ48

159

DQ49

161

VSS

163

NC,TEST

165

VSS

167

DQS6#

169

DQS6

171

VSS

173

DQ50

175

DQ51

177

VSS

179

DQ56

181

DQ57

183

VSS

185

DM7

187

VSS

189

DQ58

191

DQ59

193

VSS

195

SDA

197

SCL

199

VDDSPD

FOX_AS0A426-NARN-7F~N

SO-DIMM B REVERSE

Bottom side

Compal Secret Data

Deciphered Date

NC/CKE1

VSS DQ4 DQ5 VSS DM0 VSS DQ6 DQ7

VSS DQ12 DQ13

VSS

DM1

VSS

CK0

CK0#

VSS DQ14 DQ15

VSS

VSS DQ20 DQ21

VSS

DM2

VSS DQ22 DQ23

VSS DQ28 DQ29

VSS

DQS3#

DQS3

VSS DQ30 DQ31

VSS

VDD

NC/A15 NC/A14

VDD

BA1

RAS#

VDD ODT0

NC/A13

VDD

VSS DQ36 DQ37

VSS

DM4

VSS DQ38 DQ39

VSS DQ44 DQ45

VSS

DQS5#

DQS5

VSS DQ46 DQ47

VSS DQ52 DQ53

VSS

CK1

CK1#

VSS

DM6

VSS DQ54 DQ55

VSS DQ60 DQ61

VSS

DQS7#

DQS7

VSS DQ62 DQ63

VSS

SAO

SA1

Close to VREF pins of SO-DIMM

0.1U_0402_16V

2.2U_0805_16V4Z

DDR_B_D5

DDR_B_D4

6 8

DDR_B_DM0

10 12

DDR_B_D6

DDR_B_D7

16 18

DDR_B_D12

DDR_B_D13

22 24

DDR_B_DM1

26 28

M_CLK_DDR2

M_CLK_DDR#2

32 34

DDR_B_D14

DDR_B_D15

38 40

DDR_B_D21

DDR_B_D16

46 48 50

A11

A7 A6

A4 A2 A0

S0#

DDR_B_DM2

52 54

DDR_B_D22

DDR_B_D23

58 60

DDR_B_D29

DDR_B_D24

64 66

DDR_B_DQS#3

DDR_B_DQS3

70 72

DDR_B_D26

DDR_B_D27

76 78

DDR_CKE3_DIMMB

80 82 84

DDR_B_MA14

86 88

DDR_B_MA11

DDR_B_MA7

DDR_B_MA6

94 96

DDR_B_MA4

DDR_B_MA2

100

DDR_B_MA0

102 104

DDR_B_BS#1

106

DDR_B_RAS#

108

DDR_CS2_DIMMB#

110 112

M_ODT2

114

DDR_B_MA13

116 118 120 122

DDR_B_D36

124

DDR_B_D37

126 128

DDR_B_DM4

130 132

DDR_B_D39

134

DDR_B_D38

136 138

DDR_B_D44

140

DDR_B_D45

142 144

DDR_B_DQS#5

146

DDR_B_DQS5

148 150

DDR_B_D46

152

DDR_B_D47

154 156

DDR_B_D52

158

DDR_B_D53

160 162

M_CLK_DDR3

164

M_CLK_DDR#3

166 168

DDR_B_DM6

170 172

DDR_B_D54

174

DDR_B_D55

176 178

DDR_B_D60

180

DDR_B_D57

182 184

DDR_B_DQS#7

186

DDR_B_DQS7

188 190

DDR_B_D62

192

DDR_B_D63

194 196 198 200

10K_0402_5%

R34

2.2U_0805_16V4Z 1

C222

C221

M_CLK_DDR2 7 M_CLK_DDR#2 7

PM_EXTTS#1 7

DDR_CKE3_DIMMB 7

DDR_B_MA14 8

DDR_B_BS#1 8 DDR_B_RAS# 8 DDR_CS2_DIMMB# 7DDR_B_WE#8

M_ODT2 7

M_CLK_DDR3 7 M_CLK_DDR#3 7

R33

1 2

10K_0402_5%

Title

Size Document Number Rev

Custom

Date: Sheet

+3VS

Compal Electronics, Inc.

SCHEMATIC, M/B LA-4232P

401593

+V_DDR_MCH_REF 7,13

14 48Saturday, June 06, 2009

PCI

SRC

CPU

CLKSEL1

FSA

CLKSEL0

MHz

266

MHz

1000

MHz

33.30

14.318 96.0 48.0

DOT_96 MHz

FSC FSB REF

CLKSEL2

0 1000 133 33.31 14.318 96.0 48.0

0 1001 200 33.30 14.318 96.0 48.0

D D

0 1001 166 33.31 14.318 96.0 48.0

1 1000 333 33.30 14.318 96.0 48.0

1 1000 100 33.31 14.318 96.0 48.0

1 1001 400 33.30 14.318 96.0 48.0

111

R983

FSA

1 2

2.2K_0402_5%

CPU_BSEL05

C C

CPU_BSEL1

CPU_BSEL15

1 2

R984

R984 1K_0402_5%

1K_0402_5%

1 2

R998

R998 1K_0402_5%

1K_0402_5%

Reserved

MCH_CLKSEL0 7

MCH_CLKSEL1 7

CLK_14M_ICH19

CLK_DEBUG_PORT23 CLK_PCI_EC27 CLK_PCI_TPM25 PCI_CLK17

USB MHz

NB CPU

CK_PWRGD19

ICH_SM_DA13,14,19

ICH_SM_CLK13,14,19

Routing the trace at least 10mil

14.31818MHZ_16P

R986

0_0402_5%

1 2

C1196

22P_0402_50V8J

CLK_MCH_BCLK#7 CLK_MCH_BCLK7 CLK_CPU_BCLK#4 CLK_CPU_BCLK4

R991 33_0402_1%R991 33_0402_1%

R1001 33_0402_1%R1001 33_0402_1% R1004 33_0402_1%R1004 33_0402_1% R1006 33_0402_1%

R1006 33_0402_1% R1008 33_0402_1%R1008 33_0402_1%

1 2

ICH_SM_DA ICH_SM_CLK

1 2 1 2 1 2 1 2

R976 0_0402_5%

R976 0_0402_5% R978 0_0402_5%

R978 0_0402_5% R980 0_0402_5%

R980 0_0402_5% R982 0_0402_5%

R982 0_0402_5%

T120PAD T120PAD

CLK_XTAL_OUT CLK_XTAL_IN

C1197

22P_0402_50V8J

1 2 1 2

R_CKPWRGD CPU_BSEL1

CLK_XTAL_OUT CLK_XTAL_IN

FSC

PCI2_TME R_CLK_PCI_EC 27_SEL ITP_EN

12 12

+3VS_CK505

R_MCH_BCLK# R_MCH_BCLK R_CPU_BCLK# R_CPU_BCLK

U55

CKPWRGD/PD#

FS_B/TEST_MODE

VSS_REF

XTAL_OUT

XTAL_IN

VDD_REF

REF_0/FS_C/TEST_

REF_1

SDA

SCL

VDD_PCI

PCI_1

PCI_2

PCI_3

PCI_4/SEL_LCDCL

PCIF_5/ITP_EN

VSS_PCI

+3VS

+3VS_CK505

GND

CPU_0

VDD_CPU

R971

1 2

0_0805_5%

CPU_1

CPU_0#

CPU_1#

VSS_CPU

+3VS_CK505

C1189

C1189 10U_0805_10V

10U_0805_10V

0905 Connect to +VCCP

+1.05VS_CK505

R_CLKREQ#_EXPCARD

VDD_CPU_IO

CLKREQ_7#

SRC_8/CPU_ITP

SRC_8#/CPU_ITP#

SRC_7

SRC_7#

VSS_SRC

VDD_SRC_IO

CLKREQ_6#

+VCCP

R1020 0_0402_5%

R1020 0_0402_5% R1025 0_0402_5%

R1025 0_0402_5%

R_PCIE_EXPR R_PCIE_EXPR#

+3VS_CK505

SRC_6

SRC_6#

VDD_SRC

PCI_STOP#

CPU_STOP#

VDD_SRC_IO

SRC_10#

CLKREQ_10#

SRC_11#

CLKREQ_11#

CLKREQ_9#

VSS_SRC

CLKREQ_4#

VDD_SRC_IO

CLKREQ_3#

C1190

0.1U_0402_16V

R972

1 2

0_0805_5%

10U_0805_10V

MEDIA_REQ#32

1 2 1 2

R977 0_0402_5%

1 2

R979 0_0402_5%

1 2

R981 0_0402_5%

1 2

+1.05VS_CK505

54 53 52 51 50

SRC_10

49 48

SRC_11

47 46 45

SRC_9#

SRC_9

43 42 41 40

SRC_4#

SRC_4

38 37

C1191

0.1U_0402_16V

Place close to U55

0.1U_0402_16V

C1198

H_STP_PCI# H_STP_CPU#

R_PCIE_SATA R_PCIE_SATA# R_CLKSATAREQ# R_CLK_PCIE_LAN# R_CLK_PCIE_LAN R_CLKREQ#_GLAN

R_CLK_PCIE_MCARD# R_CLK_PCIE_MCARD

C1192

0.1U_0402_16V

C1200

C1199

0.1U_0402_16V

MEDIA_REQ#32 30 CLK_PCIE_MEDIA 30 CLK_PCIE_MEDIA# 30

EXPCARD_REQ#16 26 CLK_PCIE_EXPR 26 CLK_PCIE_EXPR# 26

H_STP_PCI# 19

H_STP_CPU# 19

R992 0_0402_5%R992 0_0402_5%

1 2

R994 0_0402_5%R994 0_0402_5%

1 2

R995 475_0402_1%~DR995 475_0402_1%~D

1 2

R996 0_0402_5%R996 0_0402_5%

1 2

R997 0_0402_5%R997 0_0402_5%

1 2

R1002 0_0402_5%R1002 0_0402_5%

1 2

R1005 0_0402_5%R1005 0_0402_5%

1 2

R1007 0_0402_5%R1007 0_0402_5%

1 2

C1193

0.1U_0402_16V

10U_0805_10V

C1201

0.1U_0402_16V

Card Bus

Express Card

CPU_STP

0.1U_0402_16V

0.1U_0402_16V 1

C1202

CLK_PCIE_SATA 18 CLK_PCIE_SATA# 18 CLKSATAREQ# 19 CLK_PCIE_LAN# 21 CLK_PCIE_LAN 21 GLAN_REQ#9 21

WLAN_REQ#4 23 CLK_PCIE_MCARD# 23 CLK_PCIE_MCARD 23

C1194

0.1U_0402_16V

+1.05VS_CK505

C1203

0.1U_0402_16V

C1204

ICH_SATA

GLAN

MiniCard_WLAN

C1195

0.1U_0402_16V

VDD_4819USB_0/FS_A20USB_1/CLKREQ_A#21VSS_4822VDD_IO23SRC_0/DOT_96

SRC_0#/DOT_96#

VSS_IO26VDD_PLL327LCDCLK/27M

+3VS_CK505

R1013 33_0402_1%R1013 33_0402_1%

B B

CPU_BSEL25

FSC

R1016

1 2

10K_0402_5%

1 2

R1017

R1017 1K_0402_5%

1K_0402_5%

MCH_CLKSEL2 7

NB (UMA)

VGA (Discrete)

ITP_EN

27_SEL

PCI2_TME

A A

ITP_EN 27_SEL

R1032

R1032 10K_0402_5%

10K_0402_5%

0 = SRC8/SRC8#

1 = ITP/ITP#

0 = Enable DOT96 & SRC1(UMA)

1 = Enable SRC0 & 27MHz(DIS)

0 = Overclocking of CPU and SRC Allowed

1 = Overclocking of CPU and SRC NOT allowed

+3VS_CK505

VGA@

VGA@ R1030

R1030 10K_0402_5%

10K_0402_5%

UMA@

UMA@ R1033

R1033 10K_0402_5%

10K_0402_5%

+3VS_CK505

1 2

PCI2_TME

R1031

R1031 10K_0402_5%

10K_0402_5%

CLK_48M_ICH19 CLKREQ#_77

CLK_MCH_DREFCLK7 CLK_MCH_DREFCLK#7

CLK_PCIE_VGA31 CLK_PCIE_VGA#31

1 2 1 2

R1014 475_0402_1%~DR1014 475_0402_1%~D

R1019 0_0402_5%UMA@R1019 0_0402_5%UMA@ R1021 0_0402_5%UMA@R1021 0_0402_5%UMA@

R1024 0_0402_5%VGA@R1024 0_0402_5%VGA@ R1026 0_0402_5%VGA@R1026 0_0402_5%VGA@

12 12

FSA R_CLKREQ#_7

+1.05VS_CK505 R_MCH_DREFCLK

R_MCH_DREFCLK#

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2006/02/13 2006/03/10

LCDCLK#/27M_SS29VSS_PLL330VDD_PLL3_IO31SRC_232SRC_2#33VSS_SRC34SRC_335SRC_3#

S IC ICS9LPRS387AKLFT MLF 72P CLK GEN

R_PCIE_ICH# R_PCIE_ICH

R_MCH_3GPLL# R_MCH_3GPLL

+1.05VS_CK505

SSCDREFCLK# SSCDREFCLK

Compal Secret Data

Deciphered Date

R1010 0_0402_5%

1 2

R1012 0_0402_5%

1 2

R1015 0_0402_5%R1015 0_0402_5%

1 2

R1018 0_0402_5%R1018 0_0402_5%

1 2

R1022 0_0402_5%UMA@ R1022 0_0402_5%UMA@

1 2

R1023 0_0402_5%UMA@ R1023 0_0402_5%UMA@

1 2

R1067 33_0402_1%VGA@ R1067 33_0402_1%VGA@

1 2

R1195 33_0402_1%VGA@ R1195 33_0402_1%VGA@

1 2

CLK_PCIE_ICH# 19 CLK_PCIE_ICH 19

CLK_MCH_3GPLL# 7 CLK_MCH_3GPLL 7

MCH_SSCDREFCLK# 7 MCH_SSCDREFCLK 7

CLK_NVSS_27M 31 CLK_NV_27M 31

EXPCARD_REQ#16 MEDIA_REQ#32 CLKSATAREQ# GLAN_REQ#9 WLAN_REQ#4 CLKREQ#_7

Title

Size Document Number Rev

Date: Sheet

Date: Sheet of

ICH

NB_3GPLL

NB_SSC (UMA) VGA_27M (DIS)

+3VS

1 2

R90 10K_0402_5%R90 10K_0402_5%

1 2

R91 10K_0402_5%R91 10K_0402_5%

1 2

R88 10K_0402_5%R88 10K_0402_5%

1 2

R87 10K_0402_5%R87 10K_0402_5%

1 2

R85 10K_0402_5%R85 10K_0402_5%

1 2

R60 10K_0402_5%R60 10K_0402_5%

Compal Electronics, Inc.

SCHEMATIC, M/B LA-4232P

401593

15 48Saturday, June 06, 2009

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