Compal LA-4231P, Vostro 1310 Schematic

A

1 1

B

C

D

E

2 2

Compal Confidential

Schematic Document

Crestline + ICH8

2007 / 11 / 14

3 3

Rev:0.2

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2007/1/15 2008/1/15

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

D

Date: Sheet

Compal Electronics, Inc.

Cover Sheet

LA-4231P

E

149Thursday, January 10, 2008

0.1

of

A

B

C

D

E

Compal confidential

SMB 13.3

File Name : LA-4231P

ZZZ1

PCB

1 1

Thermal Sensor
ADM1032ARMZ

P.4

CRT

P.15

Fan conn

P.4

LVDS Panel Interface

P.15

Mobile Merom

uFCPGA-478 CPU

P.4,5,6

H_A#(3..35)
H_D#(0..63)

FSB

667/800MHz 1.05V

DDR2 667MHz 1.8V

DDR2-SO-DIMM X2

BANK 0, 1, 2, 3

P.13,14

CK505

TSSOP-64

Clock Generator
ICS 9LPRS365

P.16

Intel Crestline MCH

nVidia
NB8M-GS

VRAM x 2

P.38

2 2

CardBus Controller

PCI

DMI X4

FCBGA 1299

P.7,8,9,10,11,12P.34,35,36,37

C-Link

O2MICRO OZ129

P.40

Intel ICH8

1394

Media Card

PCI-E BUS

mBGA-676

P.17,18,19,20

Dual Channel

USB2.0

Azalia

SATA Master
SATA Slave

USB conn x 4

FingerPrinter

Felica Conn

BT Conn

Camera

P.32

P.32

P.32

P.32

P.32

Mic

10/100/1000 LAN

REALTEK
RTL8111C-GR

3 3

P.22

Mini-Card-1
(WLAN)

P.24 P.24 P.28

Mini-Card-2

Express Card

Express Card

Mini-Card-2

P.28

P.24

RJ45/11 CONN

LPC BUS

Audio CKT
ALC268

TPM CONN

P.29

Power On/Off CKT.

4 4

DC/DC Interface CKT.

Power Circuit DC/DC

A

RTC CKT.

P.18

Power OK CKT.

Touch Pad CONN. Int.KBD

B

ENE KB926

P.29

BIOS(System/EC)

P.29P.31P.31

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2007/1/15 2008/1/15

Compal Secret Data

Deciphered Date

SATA HDD Connector

CDROM Conn.

D

P.25 P.26

P.21

P.21

Title

Block diagram

Size Document Number Rev

Custom

LA-4231P

Date: Sheet

AMP & Audio Jack

Compal Electronics, Inc.

of

249Thursday, January 10, 2008

E

0.1

A

Voltage Rails

power
plane

1 1

State

O MEANS ON X MEANS OFF

+B

+5VALW
+3VALW

+3V
+1.8V

+5VS
+3VS
+1.8VS
+1.5VS
+1.25VS

+CPU_CORE
+VCCP

B

CLOCK

C

STATE

Full ON

S1(Power On Suspend)

S3 (Suspend to RAM)

S4 (Suspend to Disk)

S5 (Soft OFF)

SIGNAL

SLP_S1# SLP_S3#

HIGH HIGH HIGH HIGH

LOW

LOW

LOW LOW LOW LOW

SLP_S4# SLP_S5# +VALW +V +VS Clock

HIGH

LOW

LOWLOWLOW

HIGHHIGHHIGH

HIGH

HIGH

D

ON

ON

ON

OFF

OFF

ON ON

ON

OFF

OFF

OFF

LOW

OFF

OFF

OFF

ON

ON

ON

ON

ON

E

Board ID Table for AD channel

S0

S3

S5 S4/AC

S5 S4/ Battery only

S5 S4/AC & Battery
don't exist

2 2

O

O
O
O

X

O

O
O

X

O

XX
X

XXX

OO

X

O

O
O

X

X
X

Vcc 3.3V +/- 5%

Board ID

0
1
2
3
4
5
6

100K +/- 5%Ra / Rc

Rb / Rd V min

0

8.2K +/- 5%
18K +/- 5%
33K +/- 5%
56K +/- 5%
100K +/- 5%
200K +/- 5%

7 NC

AD_BID

0 V

V typ

AD_BID

0 V 0 V

V

AD_BID

max

0.216 V 0.250 V 0.289 V

0.436 V

0.712 V

1.036 V

0.503 V

0.819 V

0.538 V

0.875 V

1.185 V 1.264 V

1.453 V 1.650 V 1.759 V

1.935 V

2.500 V

2.200 V

3.300 V

2.341 V

3.300 V

O MEANS ON

X MEANS OFF

S3 : STR
S4 : STD
S5 : SOFT OFF

External PCI Devices

Device IDSEL# REQ#/GNT# Interrupts

CardBus

AD21

0

PIRQE/PIRQF/PIRQG

BOARD ID Table

Board ID

0
1
2
3
4
5

PCB Revision

0.1

0.2

BTO Item BOM Structure

BTO Option Table

6
7

3 3

EC SM Bus1 address

Device

Smart Battery
EEPROM(24C16/02)

(24C04)

Address Address

1010 000X b?
1011 000Xb?

EC SM Bus2 address

Device

ADM1032

4D0001 011X b?

ICH7 SM Bus address

Device

Clock Generator
(ICS ICS9LPR310)

DDRII DIMM0
DDRII DIMM2

4 4

Address

1101 001Xb?

1001 000Xb?
1001 010Xb?

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2007/1/15 2008/1/15

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

D

Date: Sheet

Compal Electronics, Inc.

Notes

LA-4231P

E

0.1

of

349Thursday, January 10, 2008

5

4

3

2

1

XDP Reserve

H_A#[3..16]7

H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10

R108

56_0402_5%@

C

H_ADSTB#0
H_REQ#0

H_REQ#1
H_REQ#2

H_REQ#4

+3VS

C424

H_THERMDA
H_THERMDC

THERM#

H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16

H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35
H_ADSTB#1

H_A20M#
H_FERR#
H_IGNNE#

H_STPCLK#
H_INTR
H_NMI
H_SMI#

OCP# 19

2

1

D D

H_ADSTB#07

H_REQ#07
H_REQ#17
H_REQ#27
H_REQ#37
H_REQ#47
H_A#[17..35]7

C C

B B

H_ADSTB#17

H_A20M#18
H_FERR#18
H_IGNNE#18

H_STPCLK#18
H_INTR18
H_NMI18
H_SMI#18

+VCCP

12

B

2

H_PROCHOT# OCP#

E

3 1

Q11

@

MMBT3904_SOT23

Thermal Sensor EMC1402-1-ACZL-TR

0.1U_0402_16V4Z~N

C423

1 2

2200P_0402_50V7K~N

A A

+3VS

R350

1 2

10K_0402_5%

JP2A

J4

ADDR GROUP 0 ADDR GROUP 1

A[3]#

L5

A[4]#

L4

A[5]#

K5

A[6]#

M3

A[7]#

N2

A[8]#

J1

A[9]#

N3

A[10]#

P5

A[11]#

P2

A[12]#

L2

A[13]#

P4

A[14]#

P1

A[15]#

R1

A[16]#

M1

ADSTB[0]#

K3

REQ[0]#

H2

REQ[1]#

K2

REQ[2]#

J3

REQ[3]#

L1

REQ[4]#

Y2

A[17]#

U5

A[18]#

R3

A[19]#

W6

A[20]#

U4

A[21]#

Y5

A[22]#

U1

A[23]#

R4

A[24]#

T5

A[25]#

T3

A[26]#

W2

A[27]#

W5

A[28]#

Y4

A[29]#

U2

A[30]#

V4

A[31]#

W3

A[32]#

AA4

A[33]#

AB2

A[34]#

AA3

A[35]#

V1

ADSTB[1]#

A6
A5
C4

D5
C6
B4
A3

M4

N5
T2
V3
B2
C3
D2

D22

D3
F6

U2

1

VDD

2

D+

3

D­THERM#4GND

EMC1402-2-ACZL-TR MSOP 8P

Address:100_1100

ICH

A20M#
FERR#
IGNNE#

STPCLK#
LINT0
LINT1
SMI#

RSVD[01]
RSVD[02]
RSVD[03]
RSVD[04]
RSVD[05]
RSVD[06]
RSVD[07]
RSVD[08]
RSVD[09]
RSVD[10]

Merom Ball-out Rev 1a

+VCCP

R41

@

54.9_0402_1%

1 2

SCLK

SDATA

ALERT#

ADS#
BNR#

BPRI#

DEFER#

DRDY#
DBSY#

BR0#

IERR#

INIT#

LOCK#

CONTROL

RESET#

RS[0]#
RS[1]#
RS[2]#

TRDY#

HIT#

HITM#

BPM[0]#
BPM[1]#
BPM[2]#
BPM[3]#

PRDY#
PREQ#

TCK

TDO
TMS

TRST#

XDP/ITP SIGNALS

DBR#

THERMAL

PROCHOT#

THERMDA
THERMDC

THERMTRIP#

H CLK

BCLK[0]
BCLK[1]

RESERVED

conn@

EC_SMB_CK2

8

EC_SMB_DA2

7

THERM_SCI#

6
5

H_ADS#H_A#3

H1

H_BNR#

E2

H_BPRI#

G5

H_DEFER#

H5

H_DRDY#

F21

H_DBSY#

E1

H_BR0#

F1

H_IERR#

D20

H_INIT#

B3

H_LOCK#

H4

H_RESET#

C1

H_RS#0

F3

H_RS#1

F4

H_RS#2

G3

H_TRDY#H_REQ#3

G2

H_HIT#

G6

H_HITM#

E4

XDP_BPM#0

AD4

XDP_BPM#1

AD3

XDP_BPM#2

AD1

XDP_BPM#3

AC4

XDP_BPM#4

AC2

XDP_BPM#5

AC1

XDP_TCK

AC5

XDP_TDI

AA6

TDI

H_RESET#

XDP_TDO

AB3

XDP_TMS

AB5

XDP_TRST#

AB6

XDP_DBRESET#

C20

H_PROCHOT#

D21

H_THERMDA

A24

H_THERMDC

B25

H_THERMTRIP#

C7

CLK_CPU_BCLK

A22

CLK_CPU_BCLK#

A21

H_THERMDA, H_THERMDC routing together,
Trace width / Spacing = 10 / 10 mil

H_THRMTRIP# should connect
to ICH8 and GMCH without
T-ing (No stub)

12

R354

10K_0402_5%@

R355

@

0_0402_5%

12

H_ADS# 7
H_BNR# 7
H_BPRI# 7

H_DEFER# 7
H_DRDY# 7
H_DBSY# 7

H_BR0# 7

H_INIT# 18
H_LOCK# 7
H_RESET# 7

H_RS#0 7
H_RS#1 7
H_RS#2 7
H_TRDY# 7

H_HIT# 7
H_HITM# 7

T28
T27
T48
T29
T47

T33

XDP_DBRESET# 19

R114 56_0402_5%

H_THERMTRIP# 7,18

CLK_CPU_BCLK 16
CLK_CPU_BCLK# 16

EC_THERM# 19,29

R89

56_0402_5%

12

Add on 1003

12

+VCCP

+VCCP

XDP_TDI
XDP_TMS

+VCCP

XDP_BPM#5

XDP_TRST#
XDP_TCK

R172 150_0402_1%

1 2

R171 39_0402_1%

1 2

R362 54.9_0402_1%

1 2

R182 560_0402_5%

1 2

R170 27_0402_5%

1 2

@

FAN1 Control and Tachometer

C76

10U_1206_16V4Z~N

12

+5VS

C69

EN_DFAN129

FAN_SPEED129

0.01U_0402_16V7K

C94

EN_DFAN1

+3VS

12

R61

10K_0402_5%

2

1

1000P_0402_50V7K~N

12

FAN1_POWER

40mil

1 2

C77 10U_1206_16V4Z~N
U3

1

VEN
VIN
VO
VSET

RT9027BPS SO 8P

JFAN1

1
2
3

GND
GND

GND
GND
GND
GND

2
3
4

1
2
3

4
5

ACES_85205-03001

conn@

FAN1

8
7
6
5

EC_SMB_CK229,31,35
EC_SMB_DA229,31,35

5

EC_SMB_CK2
EC_SMB_DA2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2007/1/15 2008/1/15

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

Compal Electronics, Inc.

Merom(1/3)-AGTL+/XDP

LA-4231P

1

0.1

of

449Thursday, January 10, 2008

5

4

3

2

1

H_D#[0..15]7

D D

H_DSTBN#07
H_DSTBP#07
H_DINV#07
H_D#[16..31]7

C C

H_DSTBN#17
H_DSTBP#17
H_DINV#17

R91 1K_0402_5%@

1 2

R90 1K_0402_5%@

1 2

CPU_BSEL016
CPU_BSEL116
CPU_BSEL216

T14
T13
T49
T15

H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_DSTBN#0
H_DSTBP#0
H_DINV#0

H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_DSTBN#1
H_DSTBP#1
H_DINV#1 H_DINV#3

V_CPU_GTLREF

TEST1
TEST2
TEST3
TEST4
TEST5
TEST6

CPU_BSEL0
CPU_BSEL1
CPU_BSEL2

JP2B

E22

D[0]#

F24

D[1]#

E26

D[2]#

G22

D[3]#

F23

D[4]#

G25

D[5]#

E25

D[6]#

E23

D[7]#

K24

D[8]#

G24

D[9]#

J24

D[10]#

J23

D[11]#

H22

D[12]#

F26

D[13]#

K22

D[14]#

H23

D[15]#

J26

DSTBN[0]#

H26

DSTBP[0]#

H25

DINV[0]#

N22

D[16]#

K25

D[17]#

P26

D[18]#

R23

D[19]#

L23

D[20]#

M24

D[21]#

L22

D[22]#

M23

D[23]#

P25

D[24]#

P23

D[25]#

P22

D[26]#

T24

D[27]#

R24

D[28]#

L25

D[29]#

T25

D[30]#

N25

D[31]#

L26

DSTBN[1]#

M26

DSTBP[1]#

N24

DINV[1]#

AD26

GTLREF

C23

TEST1

D25

TEST2

C24

TEST3

AF26

TEST4

AF1

TEST5

A26

TEST6

B22

BSEL[0]

B23

BSEL[1]

C21

BSEL[2]

Merom Ball-out Rev 1a

conn@

DATA GRP 0

DATA GRP 2DATA GRP 3

DSTBN[2]#
DSTBP[2]#

DINV[2]#

DATA GRP 1

DSTBN[3]#
DSTBP[3]#

DINV[3]#
COMP[0]

MISC

COMP[1]
COMP[2]
COMP[3]

DPRSTP#

PWRGOOD

D[32]#
D[33]#
D[34]#
D[35]#
D[36]#
D[37]#
D[38]#
D[39]#
D[40]#
D[41]#
D[42]#
D[43]#
D[44]#
D[45]#
D[46]#
D[47]#

D[48]#
D[49]#
D[50]#
D[51]#
D[52]#
D[53]#
D[54]#
D[55]#
D[56]#
D[57]#
D[58]#
D[59]#
D[60]#
D[61]#
D[62]#
D[63]#

DPSLP#

DPWR#

SLP#

PSI#

Y22
AB24
V24
V26
V23
T22
U25
U23
Y25
W22
Y23
W24
W25
AA23
AA24
AB25
Y26
AA26
U22

AE24
AD24
AA21
AB22
AB21
AC26
AD20
AE22
AF23
AC25
AE21
AD21
AC22
AD23
AF22
AC23
AE25
AF24
AC20

R26
U26
AA1
Y1

E5
B5
D24
D6
D7
AE6

H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_DSTBN#2
H_DSTBP#2
H_DINV#2

H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
H_DSTBN#3
H_DSTBP#3

COMP0
COMP1
COMP2
COMP3

H_DPRSTP#
H_DPSLP#
H_DPWR#
H_PWRGOOD
H_CPUSLP#
H_PSI#

layout note: Route TEST3 & TEST5 traces on ground referenced layer to the TPs

CPU_BSEL CPU_BSEL2 CPU_BSEL1

166

B B

200

01

0

1

CPU_BSEL0

1

0

H_D#[32..47] 7

H_DSTBN#2 7
H_DSTBP#2 7
H_DINV#2 7
H_D#[48..63] 7

H_DSTBN#3 7
H_DSTBP#3 7
H_DINV#3 7

H_DPRSTP# 7,18,49
H_DPSLP# 18

H_DPWR# 7

H_PWRGOOD 18
H_CPUSLP# 7

H_PSI# 49

12

R173

R174

27.4_0402_1%

54.9_0402_1%

Resistor placed within

0.5" of CPU pin.Trace
should be at least 25
mils away from any other
toggling signal.
COMP[0,2] trace width is
18 mils. COMP[1,3] trace
width is 4 mils.

R87

54.9_0402_1%

12

R88

27.4_0402_1%

12

12

+CPU_CORE +CPU_CORE

JP2C

A7

VCC[001]

A9

VCC[002]

A10

VCC[003]

A12

VCC[004]

A13

VCC[005]

A15

VCC[006]

A17

VCC[007]

A18

VCC[008]

A20

VCC[009]

B7

VCC[010]

B9

VCC[011]

B10

VCC[012]

B12

VCC[013]

B14

VCC[014]

B15

VCC[015]

B17

VCC[016]

B18

VCC[017]

B20

VCC[018]

C9

VCC[019]

C10

VCC[020]

C12

VCC[021]

C13

VCC[022]

C15

VCC[023]

C17

VCC[024]

C18

VCC[025]

D9

VCC[026]

D10

VCC[027]

D12

VCC[028]

D14

VCC[029]

D15

VCC[030]

D17

VCC[031]

D18

VCC[032]

E7

VCC[033]

E9

VCC[034]

E10

VCC[035]

E12

VCC[036]

E13

VCC[037]

E15

VCC[038]

E17

VCC[039]

E18

VCC[040]

E20

VCC[041]

F7

VCC[042]

F9

VCC[043]

F10

VCC[044]

F12

VCC[045]

F14

VCC[046]

F15

VCC[047]

F17

VCC[048]

F18

VCC[049]

F20

VCC[050]

AA7

VCC[051]

AA9

VCC[052]

AA10

VCC[053]

AA12

VCC[054]

AA13

VCC[055]

AA15

VCC[056]

AA17

VCC[057]

AA18

VCC[058]

AA20

VCC[059]

AB9

VCC[060]

AC10

VCC[061]

AB10

VCC[062]

AB12

VCC[063]

AB14

VCC[064]

AB15

VCC[065]

AB17

VCC[066]

AB18

VCC[067]

Merom Ball-out Rev 1a

conn@

VCC[068]
VCC[069]
VCC[070]
VCC[071]
VCC[072]
VCC[073]
VCC[074]
VCC[075]
VCC[076]
VCC[077]
VCC[078]
VCC[079]
VCC[080]
VCC[081]
VCC[082]
VCC[083]
VCC[084]
VCC[085]
VCC[086]
VCC[087]
VCC[088]
VCC[089]
VCC[090]
VCC[091]
VCC[092]
VCC[093]
VCC[094]
VCC[095]
VCC[096]
VCC[097]
VCC[098]
VCC[099]
VCC[100]

VCCP[01]
VCCP[02]
VCCP[03]
VCCP[04]
VCCP[05]
VCCP[06]
VCCP[07]
VCCP[08]
VCCP[09]
VCCP[10]
VCCP[11]
VCCP[12]
VCCP[13]
VCCP[14]
VCCP[15]
VCCP[16]

VCCA[01]
VCCA[02]

VID[0]
VID[1]
VID[2]
VID[3]
VID[4]
VID[5]
VID[6]

VCCSENSE

VSSSENSE

AB20
AB7
AC7
AC9
AC12
AC13
AC15
AC17
AC18
AD7
AD9
AD10
AD12
AD14
AD15
AD17
AD18
AE9
AE10
AE12
AE13
AE15
AE17
AE18
AE20
AF9
AF10
AF12
AF14
AF15
AF17
AF18
AF20

G21
V6
J6
K6
M6
J21
K21
M21
N21
N6
R21
R6
T21
T6
V21
W21

B26
C26

AD6
AF5
AE5
AF4
AE3
AF3
AE2

VCCSENSE

AF7

VSSSENSE

AE7

.

Length match within 25 mils.

C140

+VCCP

1

2

+

330U_V_2.5VM

CPU_VID0 49
CPU_VID1 49
CPU_VID2 49
CPU_VID3 49
CPU_VID4 49
CPU_VID5 49
CPU_VID6 49

VCCSENSE 49

VSSSENSE 49

C412

1

C409

2

10U_0805_10V4Z~N

+1.5VS

1

2

0.01U_0402_16V7K~N

Near pin B26

The trace width/space/other is
20/7/25.

+CPU_CORE

R359
100_0402_1%

1 2

R360
100_0402_1%

1 2

VCCSENSE

VSSSENSE

V_CPU_GTLREF

+VCCP

12

R86
1K_0402_1%

12

R85
2K_0402_1%

Close to CPU pin AD26
within 500mils.

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2007/1/15 2008/1/15

Compal Secret Data

Deciphered Date

2

Close to CPU pin
within 500mils.

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

Merom(2/3)-AGTL+/PWR

LA-4231P

1

of

549Thursday, January 10, 2008

0.1

5

High Frequence Decoupling

10uF 0805 X5R -> 85 degree.

Place these caps inside
the CPU socket cavity.

( Left side on Top ).

D D

C C

B B

JP2D

A4

VSS[001]

A8

VSS[002]

A11

VSS[003]

A14

VSS[004]

A16

VSS[005]

A19

VSS[006]

A23

VSS[007]

AF2

VSS[008]

B6

VSS[009]

B8

VSS[010]

B11

VSS[011]

B13

VSS[012]

B16

VSS[013]

B19

VSS[014]

B21

VSS[015]

B24

VSS[016]

C5

VSS[017]

C8

VSS[018]

C11

VSS[019]

C14

VSS[020]

C16

VSS[021]

C19

VSS[022]

C2

VSS[023]

C22

VSS[024]

C25

VSS[025]

D1

VSS[026]

D4

VSS[027]

D8

VSS[028]

D11

VSS[029]

D13

VSS[030]

D16

VSS[031]

D19

VSS[032]

D23

VSS[033]

D26

VSS[034]

E3

VSS[035]

E6

VSS[036]

E8

VSS[037]

E11

VSS[038]

E14

VSS[039]

E16

VSS[040]

E19

VSS[041]

E21

VSS[042]

E24

VSS[043]

F5

VSS[044]

F8

VSS[045]

F11

VSS[046]

F13

VSS[047]

F16

VSS[048]

F19

VSS[049]

F2

VSS[050]

F22

VSS[051]

F25

VSS[052]

G4

VSS[053]

G1

VSS[054]

G23

VSS[055]

G26

VSS[056]

H3

VSS[057]

H6

VSS[058]

H21

VSS[059]

H24

VSS[060]

J2

VSS[061]

J5

VSS[062]

J22

VSS[063]

J25

VSS[064]

K1

VSS[065]

K4

VSS[066]

K23

VSS[067]

K26

VSS[068]

L3

VSS[069]

L6

VSS[070]

L21

VSS[071]

L24

VSS[072]

M2

VSS[073]

M5

VSS[074]

M22

VSS[075]

M25

VSS[076]

N1

VSS[077]

N4

VSS[078]

N23

VSS[079]

N26

VSS[080]
VSS[081]P3VSS[162]

Merom Ball-out Rev 1a

conn@

VSS[082]
VSS[083]
VSS[084]
VSS[085]
VSS[086]
VSS[087]
VSS[088]
VSS[089]
VSS[090]
VSS[091]
VSS[092]
VSS[093]
VSS[094]
VSS[095]
VSS[096]
VSS[097]
VSS[098]
VSS[099]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
VSS[159]
VSS[160]
VSS[161]

VSS[163]

P6
P21
P24
R2
R5
R22
R25
T1
T4
T23
T26
U3
U6
U21
U24
V2
V5
V22
V25
W1
W4
W23
W26
Y3
Y6
Y21
Y24
AA2
AA5
AA8
AA11
AA14
AA16
AA19
AA22
AA25
AB1
AB4
AB8
AB11
AB13
AB16
AB19
AB23
AB26
AC3
AC6
AC8
AC11
AC14
AC16
AC19
AC21
AC24
AD2
AD5
AD8
AD11
AD13
AD16
AD19
AD22
AD25
AE1
AE4
AE8
AE11
AE14
AE16
AE19
AE23
AE26
A2
AF6
AF8
AF11
AF13
AF16
AF19
AF21
A25
AF25

.

Place these caps inside
the CPU socket cavity.

( Right side on Top side).

Place these caps inside
the CPU socket cavity.

( Left side on Bottom ).

Place these caps inside
the CPU socket cavity.

( Right side on Bottom ).

+VCCP

C212

1

+

2

220U_D2_4VY_R15M

1

C210

0.1U_0402_10V6K

2

4

+CPU_CORE

1

2

+CPU_CORE

1

2

+CPU_CORE

1

2

+CPU_CORE

1

2

1

2

C1150
10U_0805_6.3V6M

C1160
10U_0805_6.3V6M

C1170
10U_0805_6.3V6M

C1176
10U_0805_6.3V6M

1

C1151
10U_0805_6.3V6M

2

1

C1161
10U_0805_6.3V6M

2

1

C1171
10U_0805_6.3V6M

2

1

C1177
10U_0805_6.3V6M

2

Near CPU CORE regulator

+CPU_CORE

1

+

C190

C429

2

330U_V_2.5VM

330U_V_2.5VM

C209

0.1U_0402_10V6K

1

C208

0.1U_0402_10V6K

2

1

+

@

2

1

2

1

2

1

2

1

2

1

+

C207

2

330U_V_2.5VM

1

2

C1152
10U_0805_6.3V6M

C1162
10U_0805_6.3V6M

C1172
10U_0805_6.3V6M

C1178
10U_0805_6.3V6M

C426

330U_V_2.5VM

C185

0.1U_0402_10V6K

3

1

C1153
10U_0805_6.3V6M

2

1

C1163
10U_0805_6.3V6M

2

1

C1173
10U_0805_6.3V6M

2

1

C1179
10U_0805_6.3V6M

2

1

2

1

2

1

2

1

2

ESR <= 1.5m ohm
Capacitor > 1980uF

1

+

2

1

C183

0.1U_0402_10V6K

2

C1154
10U_0805_6.3V6M

C1164
10U_0805_6.3V6M

C1174
10U_0805_6.3V6M

C1180
10U_0805_6.3V6M

Place these inside
socket cavity on L8
(North side
Secondary)

1

C184

0.1U_0402_10V6K

2

1

C1155
10U_0805_6.3V6M

2

1

C1165
10U_0805_6.3V6M

2

1

C1175
10U_0805_6.3V6M

2

1

C1181
10U_0805_6.3V6M

2

2

1

C1156
10U_0805_6.3V6M

2

1

C1166
10U_0805_6.3V6M

2

1

C1157
10U_0805_6.3V6M

2

1

C1167
10U_0805_6.3V6M

2

1

C1158
10U_0805_6.3V6M

2

1

C1168
10U_0805_6.3V6M

2

1

Place these caps inside
the CPU socket.

1

( Left side on Top ).

C1159
10U_0805_6.3V6M

2

Place these caps inside
the CPU socket.

1

( Right side on Top ).

C1169
10U_0805_6.3V6M

2

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2007/1/15 2008/1/15

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

Compal Electronics, Inc.

Merom(3/3)-GND&Bypass

LA-4231P

1

0.1

of

649Thursday, January 10, 2008

5

H_D#[0..63]5

D D

C C

+VCCP

12

12

R325

R326

54.9_0402_1%

54.9_0402_1%

H_RESET#4

H_CPUSLP#5

B B

H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57

H_D#59
H_D#60
H_D#61
H_D#62
H_D#63

H_SWNG
H_RCOMP

H_SCOMP
H_SCOMP#

H_RESET#
H_CPUSLP#

H_VREF

layout note:

U4A

E2

H_D#_0

G2

H_D#_1

G7

H_D#_2

M6

H_D#_3

H7

H_D#_4

H3

H_D#_5

G4

H_D#_6

F3

H_D#_7

N8

H_D#_8

H2

H_D#_9

M10

H_D#_10

N12

H_D#_11

N9

H_D#_12

H5

H_D#_13

P13

H_D#_14

K9

H_D#_15

M2

H_D#_16

W10

H_D#_17

Y8

H_D#_18

V4

H_D#_19

M3

H_D#_20

J1

H_D#_21

N5

H_D#_22

N3

H_D#_23

W6

H_D#_24

W9

H_D#_25

N2

H_D#_26

Y7

H_D#_27

Y9

H_D#_28

P4

H_D#_29

W3

H_D#_30

N1

H_D#_31

AD12

H_D#_32

AE3

H_D#_33

AD9

H_D#_34

AC9

H_D#_35

AC7

H_D#_36

AC14

H_D#_37

AD11

H_D#_38

AC11

H_D#_39

AB2

H_D#_40

AD7

H_D#_41

AB1

H_D#_42

Y3

H_D#_43

AC6

H_D#_44

AE2

H_D#_45

AC5

H_D#_46

AG3

H_D#_47

AJ9

H_D#_48

AH8

H_D#_49

AJ14

H_D#_50

AE9

H_D#_51

AE11

H_D#_52

AH12

H_D#_53

AJ5

H_D#_54

AH5

H_D#_55

AJ6

H_D#_56

AE7

H_D#_57

AJ7

H_D#_58

AJ2

H_D#_59

AE5

H_D#_60

AJ3

H_D#_61

AH2

H_D#_62

AH13

H_D#_63

B3

H_SWING

C2

H_RCOMP

W1

H_SCOMP

W2

H_SCOMP#

B6

H_CPURST#

E5

H_CPUSLP#

B9

H_AVREF

A9

H_DVREF

CRESTLINE_1p0 UMA@

HOST

H_ADSTB#_0
H_ADSTB#_1

H_BREQ#

H_DEFER#

H_DBSY#

HPLL_CLK

HPLL_CLK#

H_DPWR#

H_DRDY#

H_LOCK#
H_TRDY#

H_DINV#_0
H_DINV#_1
H_DINV#_2
H_DINV#_3

H_DSTBN#_0
H_DSTBN#_1
H_DSTBN#_2
H_DSTBN#_3

H_DSTBP#_0
H_DSTBP#_1
H_DSTBP#_2
H_DSTBP#_3

H_REQ#_0
H_REQ#_1
H_REQ#_2
H_REQ#_3
H_REQ#_4

Route H_SCOMP and H_SCOMP# with trace width, spacing and impedance (55 ohm) same as FSB data traces

Layout Note:
H_RCOMP / H_VREF / H_SWNG

trace width and spacing is 10/20

+VCCP

R322

R323

12

221_0603_1%

12

100_0402_1%

H_SWNGH_VREF

1

C386

2

0.1U_0402_16V4Z~N

+VCCP

12

R45

1K_0402_1%

0.1U_0402_16V4Z~N

12

A A

1

R46

C391

2

2K_0402_1%

12

R324

24.9_0402_1%

H_RCOMP

Near B3 pinwithin 100 mils from NB

5

H_A#_3
H_A#_4
H_A#_5
H_A#_6
H_A#_7
H_A#_8

H_A#_9
H_A#_10
H_A#_11
H_A#_12
H_A#_13
H_A#_14
H_A#_15
H_A#_16
H_A#_17
H_A#_18
H_A#_19
H_A#_20
H_A#_21
H_A#_22
H_A#_23
H_A#_24
H_A#_25
H_A#_26
H_A#_27
H_A#_28
H_A#_29
H_A#_30
H_A#_31
H_A#_32
H_A#_33
H_A#_34
H_A#_35

H_ADS#

H_BNR#

H_BPRI#

H_HIT#
H_HITM#

H_RS#_0
H_RS#_1
H_RS#_2

close to NB

4

H_A#3

J13

H_A#4

B11

H_A#5

C11

H_A#6

M11

H_A#7

C15

H_A#8

F16

H_A#9

L13

H_A#10

G17

H_A#11

C14

H_A#12

K16

H_A#13

B13

H_A#14

L16

H_A#15

J17

H_A#16

B14

H_A#17

K19

H_A#18

P15

H_A#19

R17

H_A#20

B16

H_A#21

H20

H_A#22

L19

H_A#23

D17

H_A#24

M17

H_A#25

N16

H_A#26

J19

H_A#27

B18

H_A#28

E19

H_A#29

B17

H_A#30

B15

H_A#31

E17

H_A#32

C18

H_A#33

A19

H_A#34

B19

H_A#35

N19

H_ADS#

G12

H_ADSTB#0

H17

H_ADSTB#1

G20

H_BNR#

C8

H_BPRI#

E8

H_BR0#

F12

H_DEFER#

D6

H_DBSY#

C10

CLK_MCH_BCLK

AM5

CLK_MCH_BCLK#

AM7

H_DPWR#

H8

H_DRDY#

K7

H_HIT#

E4

H_HITM#

C6

H_LOCK#

G10

H_TRDY#

B7

H_DINV#0

K5

H_DINV#1

L2

H_DINV#2

AD13

H_DINV#3

AE13

H_DSTBN#0H_D#58

M7

H_DSTBN#1

K3

H_DSTBN#2

AD2

H_DSTBN#3

AH11

H_DSTBP#0

L7

H_DSTBP#1

K2

H_DSTBP#2

AC2

H_DSTBP#3

AJ10

H_REQ#0

M14

H_REQ#1

E13

H_REQ#2

A11

H_REQ#3

H13

H_REQ#4

B12

H_RS#0

E12

H_RS#1

D7

H_RS#2

D8

Layout Note:
+DDR_MCH_REF
trace width and
spacing is 20/20.

+DDR_MCH_REF

1

C66

2

0.1U_0402_16V4Z~N

4

H_A#[3..35] 4

H_ADS# 4
H_ADSTB#0 4
H_ADSTB#1 4
H_BNR# 4
H_BPRI# 4
H_BR0# 4
H_DEFER# 4
H_DBSY# 4
CLK_MCH_BCLK 16
CLK_MCH_BCLK# 16
H_DPWR# 5
H_DRDY# 4
H_HIT# 4
H_HITM# 4
H_LOCK# 4
H_TRDY# 4

H_DINV#0 5
H_DINV#1 5
H_DINV#2 5
H_DINV#3 5

H_DSTBN#0 5
H_DSTBN#1 5
H_DSTBN#2 5
H_DSTBN#3 5

H_DSTBP#0 5
H_DSTBP#1 5
H_DSTBP#2 5
H_DSTBP#3 5

H_REQ#0 4
H_REQ#1 4
H_REQ#2 4
H_REQ#3 4
H_REQ#4 4

H_RS#0 4
H_RS#1 4
H_RS#2 4

+1.8V

12

R42
1K_0402_1%

12

R43
1K_0402_1%

3

+1.8V

2

2

12

C400

C404

1

0.01U_0402_25V7K~N

1

2

0.01U_0402_25V7K~N

MCH_CLKSEL016
MCH_CLKSEL116
MCH_CLKSEL216

3

R331
1K_0402_1%

12

R332

3.01K_0402_1%

NA lead free

12

R333
1K_0402_1%

DDR_A_MA1413
DDR_B_MA1414

R82

10K_0402_5%

R83

10K_0402_5%

CFG129
CFG139

CFG169

CFG199
CFG209

PM_BMBUSY#19

H_DPRSTP#5,18,49
PM_EXTTS#013
PM_EXTTS#114

R56 0_0402_5%

DPRSLPVR19,49

+3VS

12

12

MCH_CLKSEL0
MCH_CLKSEL1
MCH_CLKSEL2

T8PAD
T9PAD

CFG59
CFG79

CFG89
CFG99

CFG5

T37PAD

CFG7
CFG9

T38PAD
T40PAD

CFG12
CFG13

T10PAD
T4PAD

CFG16

T5PAD
T39PAD

CFG19
CFG20

PM_BMBUSY#
H_DPRSTP#
PM_EXTTS#0
PM_EXTTS#1
PM_POK_R
PLT_RST#_R
THERMTRIP#

12

DPRSLPVR

VGATE19,29,49

PM_PWROK19,29

PLT_RST#17,19,22,24,28,29,34

2007/1/15 2008/1/15

1

2.2U_0603_106K

SMRCOMP_VOH

SMRCOMP_VOL

C398

1

2

C403

2.2U_0603_106K

PM_EXTTS#0

PM_EXTTS#1

H_THERMTRIP#4,18

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

U4B

P36

RSVD1

P37

RSVD2

R35

RSVD3

N35

RSVD4

AR12

RSVD5

AR13

RSVD6

AM12

RSVD7

AN13

RSVD8

J12

RSVD9

AR37

RSVD10

AM36

RSVD11

AL36

RSVD12

AM37

RSVD13

D20

RSVD14

H10

RSVD20

B51

RSVD21

BJ20

RSVD22

BK22

RSVD23

BF19

RSVD24

BH20

RSVD25

BK18

RSVD26

BJ18

RSVD27

BF23

RSVD28

BG23

RSVD29

BC23

RSVD30

BD24

RSVD31

BJ29

RSVD32

BE24

RSVD33

BH39

RSVD34

AW20

RSVD35

BK20

RSVD36

C48

RSVD37

D47

RSVD38

B44

RSVD39

C44

RSVD40

A35

RSVD41

B37

RSVD42

B36

RSVD43

B34

RSVD44

C34

RSVD45

P27

CFG_0

N27

CFG_1

N24

CFG_2

C21

CFG_3

C23

CFG_4

F23

CFG_5

N23

CFG_6

G23

CFG_7

J20

CFG_8

C20

CFG_9

R24

CFG_10

L23

CFG_11

J23

CFG_12

E23

CFG_13

E20

CFG_14

K23

CFG_15

M20

CFG_16

M24

CFG_17

L32

CFG_18

N33

CFG_19

L35

CFG_20

G41

PM_BM_BUSY#

L39

PM_DPRSTP#

L36

PM_EXT_TS#_0

J36

PM_EXT_TS#_1

AW49

PWROK

AV20

RSTIN#

N20

THERMTRIP#

G36

DPRSLPVR

BJ51

NC_1

BK51

NC_2

BK50

NC_3

BL50

NC_4

BL49

NC_5

BL3

NC_6

BL2

NC_7

BK1

NC_8

BJ1

NC_9

E1

NC_10

A5

NC_11

C51

NC_12

B50

NC_13

A50

NC_14

A49

NC_15

BK2

NC_16

CRESTLINE_1p0 UMA@

R101 0_0402_5%@

R102 0_0402_5%

PLT_RST# PLT_RST#_R

1 2

R111 100_0402_5%

Compal Secret Data

Deciphered Date

12

12

2

CFGRSVD

PM

NC

PM_POK_R

2

AV29

SM_CK_0

BB23

SM_CK_1

BA25

SM_CK_3

AV23

SM_CK_4

AW30

SM_CK#_0

BA23

SM_CK#_1

AW25

SM_CK#_3

AW23

SM_CK#_4

BE29

SM_CKE_0

AY32

SM_CKE_1

BD39

SM_CKE_3

BG37

SM_CKE_4

BG20

SM_CS#_0

BK16

SM_CS#_1

BG16

SM_CS#_2

BE13

SM_CS#_3

BH18

SM_ODT_0

BJ15

SM_ODT_1

BJ14

SM_ODT_2

BE16

SM_ODT_3

BL15

SM_RCOMP

SM_VREF_0
SM_VREF_1

PEG_CLK

PEG_CLK#

DMI_RXN_0
DMI_RXN_1
DMI_RXN_2
DMI_RXN_3

DMI_RXP_0
DMI_RXP_1
DMI_RXP_2
DMI_RXP_3

DMI_TXN_0
DMI_TXN_1
DMI_TXN_2
DMI_TXN_3

DMI_TXP_0
DMI_TXP_1
DMI_TXP_2
DMI_TXP_3

GFX_VID_0
GFX_VID_1
GFX_VID_2
GFX_VID_3

CL_CLK

CL_DATA

CL_PWROK

CL_RST#
CL_VREF

CLK_REQ#

ICH_SYNC#

TEST_1
TEST_2

BK14
BK31

BL31
AR49

AW4

B42
C42
H48
H47

K44
K45

AN47
AJ38
AN42
AN46

AM47
AJ39
AN41
AN45

AJ46
AJ41
AM40
AM44

AJ47
AJ42
AM39
AM43

E35
A39
C38
B39
E36

AM49
AK50
AT43
AN49
AM50

H35
K36
G39
G40

A37
R32

20K_0402_5%

Custom

SM_RCOMP#

SM_RCOMP_VOH
SM_RCOMP_VOL

DDR MUXINGCLK

DPLL_REF_CLK

DPLL_REF_CLK#

DPLL_REF_SSCLK

DPLL_REF_SSCLK#

DMI

GFX_VR_EN

GRAPHICS VID

ME

SDVO_CTRL_CLK

SDVO_CTRL_DATA

MISC

1

For Crestline: 20ohm

M_CLK_DDR0
M_CLK_DDR1
M_CLK_DDR2
M_CLK_DDR3

M_CLK_DDR#0
M_CLK_DDR#1
M_CLK_DDR#2
M_CLK_DDR#3

DDR_CKE0_DIMMA
DDR_CKE1_DIMMA
DDR_CKE2_DIMMB
DDR_CKE3_DIMMB

DDR_CS0_DIMMA#
DDR_CS1_DIMMA#
DDR_CS2_DIMMB#
DDR_CS3_DIMMB#

M_ODT0
M_ODT1
M_ODT2
M_ODT3

SMRCOMP
SMRCOMP#

SMRCOMP_VOH
SMRCOMP_VOL

+DDR_MCH_REF

CLK_MCH_DREFCLK
CLK_MCH_DREFCLK#
MCH_SSCDREFCLK
MCH_SSCDREFCLK#

CLK_MCH_3GPLL

CLK_MCH_3GPLL#

DMI_TXN0
DMI_TXN1
DMI_TXN2
DMI_TXN3

DMI_TXP0
DMI_TXP1
DMI_TXP2
DMI_TXP3

DMI_RXN0
DMI_RXN1
DMI_RXN2
DMI_RXN3

DMI_RXP0
DMI_RXP1
DMI_RXP2
DMI_RXP3

CL_CLK0
CL_DATA0
M_PWROK
CL_RST#
CL_VREF CL_VREF

CLKMCHREQ#
MCH_ICH_SYNC#

12

R77

Title

CRESTLINE(1/6)-AGTL+/DMI/DDR2

Size Document Number Rev

LA-4231P

Date: Sheet

For Calero: 80.6ohm

M_CLK_DDR0 13
M_CLK_DDR1 13
M_CLK_DDR2 14
M_CLK_DDR3 14

M_CLK_DDR#0 13
M_CLK_DDR#1 13
M_CLK_DDR#2 14
M_CLK_DDR#3 14

DDR_CKE0_DIMMA 13
DDR_CKE1_DIMMA 13
DDR_CKE2_DIMMB 14
DDR_CKE3_DIMMB 14

DDR_CS0_DIMMA# 13
DDR_CS1_DIMMA# 13
DDR_CS2_DIMMB# 14
DDR_CS3_DIMMB# 14

M_ODT0 13
M_ODT1 13
M_ODT2 14
M_ODT3 14

R328 20_0402_1%
R329 20_0402_1%

CLK_MCH_DREFCLK 16

CLK_MCH_DREFCLK# 16

MCH_SSCDREFCLK 16

MCH_SSCDREFCLK# 16

CLK_MCH_3GPLL 16
CLK_MCH_3GPLL# 16

DMI_TXN0 19
DMI_TXN1 19
DMI_TXN2 19
DMI_TXN3 19

DMI_TXP0 19
DMI_TXP1 19
DMI_TXP2 19
DMI_TXP3 19

DMI_RXN0 19
DMI_RXN1 19
DMI_RXN2 19
DMI_RXN3 19

DMI_RXP0 19
DMI_RXP1 19
DMI_RXP2 19
DMI_RXP3 19

CLK_MCH_DREFCLK
CLK_MCH_DREFCLK#
MCH_SSCDREFCLK

12

R84
0_0402_5%

MCH_SSCDREFCLK#

CL_CLK0 19
CL_DATA0 19

M_PWROK 19
CL_RST# 19

0.1U_0402_16V4Z~N

CLKMCHREQ# 16
MCH_ICH_SYNC# 19

C181

12 mil

T12 PAD
T42 PAD
T41 PAD
T16 PAD
T11 PAD

Compal Electronics, Inc.

1

+1.8V

12
12

R678 0_0402_5%VGA@
R679 0_0402_5%VGA@
R680 0_0402_5%VGA@
R681 0_0402_5%VGA@

+1.25VM_AXD

1

2

749Thursday, January 10, 2008

12
12
12
12

12

R100
1K_0402_1%

12

R99
392_0402_1%

of

0.1

5

D D

DDR_A_D[0..63]13

C C

B B

DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8

DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63

AR43

AW44

BA45
AY46
AR41
AR45
AT42

AW47

BB45
BF48
BG47

BJ45
BB47
BG50
BH49
BE45

AW43

BE44
BG42
BE40
BF44
BH45
BG40
BF40
AR40

AW40

AT39

AW36
AW41

AY41
AV38
AT38
AV13
AT13

AW11

AV11
AU15
AT11
BA13
BA11
BE10
BD10

BG10

AW9

AM8

AN10

AN9
AM9

AN11

BD8
AY9

BD7
BB9
BB5
AY7
AT5
AT7
AY6
BB7
AR5
AR8
AR9
AN3

AT9

U4D

SA_DQ_0
SA_DQ_1
SA_DQ_2
SA_DQ_3
SA_DQ_4
SA_DQ_5
SA_DQ_6
SA_DQ_7
SA_DQ_8
SA_DQ_9
SA_DQ_10
SA_DQ_11
SA_DQ_12
SA_DQ_13
SA_DQ_14
SA_DQ_15
SA_DQ_16
SA_DQ_17
SA_DQ_18
SA_DQ_19
SA_DQ_20
SA_DQ_21
SA_DQ_22
SA_DQ_23
SA_DQ_24
SA_DQ_25
SA_DQ_26
SA_DQ_27
SA_DQ_28
SA_DQ_29
SA_DQ_30
SA_DQ_31
SA_DQ_32
SA_DQ_33
SA_DQ_34
SA_DQ_35
SA_DQ_36
SA_DQ_37
SA_DQ_38
SA_DQ_39
SA_DQ_40
SA_DQ_41
SA_DQ_42
SA_DQ_43
SA_DQ_44
SA_DQ_45
SA_DQ_46
SA_DQ_47
SA_DQ_48
SA_DQ_49
SA_DQ_50
SA_DQ_51
SA_DQ_52
SA_DQ_53
SA_DQ_54
SA_DQ_55
SA_DQ_56
SA_DQ_57
SA_DQ_58
SA_DQ_59
SA_DQ_60
SA_DQ_61
SA_DQ_62
SA_DQ_63

CRESTLINE_1p0

DDR SYSTEM MEMORY A

SA_BS_0
SA_BS_1
SA_BS_2

SA_CAS#

SA_DM_0
SA_DM_1
SA_DM_2
SA_DM_3
SA_DM_4
SA_DM_5
SA_DM_6
SA_DM_7

SA_DQS_0
SA_DQS_1
SA_DQS_2
SA_DQS_3
SA_DQS_4
SA_DQS_5
SA_DQS_6

SA_DQS_7
SA_DQS#_0
SA_DQS#_1
SA_DQS#_2
SA_DQS#_3
SA_DQS#_4
SA_DQS#_5
SA_DQS#_6
SA_DQS#_7

SA_MA_0
SA_MA_1
SA_MA_2
SA_MA_3
SA_MA_4
SA_MA_5
SA_MA_6
SA_MA_7
SA_MA_8

SA_MA_9
SA_MA_10
SA_MA_11
SA_MA_12
SA_MA_13

SA_RAS#

SA_RCVEN#

SA_WE#

4

DDR_A_BS0

BB19
BK19
BF29

BL17
AT45

BD44
BD42
AW38
AW13
BG8
AY5
AN6

AT46
BE48
BB43
BC37
BB16
BH6
BB2
AP3
AT47
BD47
BC41
BA37
BA16
BH7
BC1
AP2

BJ19
BD20
BK27
BH28
BL24
BK28
BJ27
BJ25
BL28
BA28
BC19
BE28
BG30
BJ16

BE18
AY20

BA19

DDR_A_BS1
DDR_A_BS2

DDR_A_CAS#
DDR_A_DM0

DDR_A_DM1
DDR_A_DM2
DDR_A_DM3
DDR_A_DM4
DDR_A_DM5
DDR_A_DM6
DDR_A_DM7

DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2

DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7
DDR_A_DQS#0
DDR_A_DQS#1
DDR_A_DQS#2
DDR_A_DQS#3
DDR_A_DQS#4
DDR_A_DQS#5
DDR_A_DQS#6
DDR_A_DQS#7

DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13

DDR_A_RAS#
SA_RCVEN#

DDR_A_WE#

DDR_A_BS#0 13
DDR_A_BS#1 13
DDR_A_BS#2 13

DDR_A_CAS# 13 DDR_B_CAS# 14
DDR_A_DM[0..7] 13

DDR_A_DQS[0..7] 13

DDR_A_DQS#[0..7] 13

DDR_A_MA[0..13] 13

DDR_A_RAS# 13

T6

DDR_A_WE# 13

3

DDR_B_D[0..63]14

DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8

DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18DDR_A_DQS3
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41

DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63

AP49

AR51
AW50
AW51

AN51

AN50

AV50

AV49

BA50

BB50

BA49

BE50

BA51

AY49

BF50

BF49

BJ50
BJ44
BJ43

BL43
BK47
BK49
BK43
BK42

BJ41

BL41

BJ37

BJ36
BK41

BJ40

BL35
BK37
BK13
BE11
BK11
BC11
BC13
BE12
BC12
BG12

BJ10

BK10

BG1

BL9
BK5
BL5
BK9

BJ8
BJ6
BF4
BH5

BC2
BK3
BE4
BD3
BJ2
BA3
BB3
AR1
AT3
AY2
AY3
AU2
AT2

2

U4E

SB_DQ_0
SB_DQ_1
SB_DQ_2
SB_DQ_3
SB_DQ_4
SB_DQ_5
SB_DQ_6
SB_DQ_7
SB_DQ_8
SB_DQ_9
SB_DQ_10
SB_DQ_11
SB_DQ_12
SB_DQ_13
SB_DQ_14
SB_DQ_15
SB_DQ_16
SB_DQ_17
SB_DQ_18
SB_DQ_19
SB_DQ_20
SB_DQ_21
SB_DQ_22
SB_DQ_23
SB_DQ_24
SB_DQ_25
SB_DQ_26
SB_DQ_27
SB_DQ_28
SB_DQ_29
SB_DQ_30
SB_DQ_31
SB_DQ_32
SB_DQ_33
SB_DQ_34
SB_DQ_35
SB_DQ_36
SB_DQ_37
SB_DQ_38
SB_DQ_39
SB_DQ_40
SB_DQ_41
SB_DQ_42
SB_DQ_43
SB_DQ_44
SB_DQ_45
SB_DQ_46
SB_DQ_47
SB_DQ_48
SB_DQ_49
SB_DQ_50
SB_DQ_51
SB_DQ_52
SB_DQ_53
SB_DQ_54
SB_DQ_55
SB_DQ_56
SB_DQ_57
SB_DQ_58
SB_DQ_59
SB_DQ_60
SB_DQ_61
SB_DQ_62
SB_DQ_63

CRESTLINE_1p0

1

DDR_B_BS0

AY17

SB_BS_0
SB_BS_1
SB_BS_2

SB_CAS#

SB_DM_0
SB_DM_1
SB_DM_2
SB_DM_3
SB_DM_4
SB_DM_5
SB_DM_6
SB_DM_7

SB_DQS_0
SB_DQS_1
SB_DQS_2
SB_DQS_3
SB_DQS_4
SB_DQS_5
SB_DQS_6

SB_DQS_7
SB_DQS#_0
SB_DQS#_1
SB_DQS#_2
SB_DQS#_3
SB_DQS#_4
SB_DQS#_5
SB_DQS#_6
SB_DQS#_7

SB_MA_0
SB_MA_1
SB_MA_2
SB_MA_3
SB_MA_4
SB_MA_5
SB_MA_6
SB_MA_7
SB_MA_8

SB_MA_9
SB_MA_10
SB_MA_11
SB_MA_12
SB_MA_13

SB_RAS#

SB_RCVEN#

SB_WE#

DDR SYSTEM MEMORY B

BG18
BG36

BE17
AR50

BD49
BK45
BL39
BH12
BJ7
BF3
AW2

AT50
BD50
BK46
BK39
BJ12
BL7
BE2
AV2
AU50
BC50
BL45
BK38
BK12
BK7
BF2
AV3

BC18
BG28
BG25
AW17
BF25
BE25
BA29
BC28
AY28
BD37
BG17
BE37
BA39
BG13

AV16
AY18

BC17

DDR_B_BS1
DDR_B_BS2

DDR_B_CAS#
DDR_B_DM0

DDR_B_DM1
DDR_B_DM2
DDR_B_DM3
DDR_B_DM4
DDR_B_DM5
DDR_B_DM6
DDR_B_DM7

DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4
DDR_B_DQS5
DDR_B_DQS6

DDR_B_DQS7
DDR_B_DQS#0
DDR_B_DQS#1
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS#4
DDR_B_DQS#5
DDR_B_DQS#6
DDR_B_DQS#7

DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8

DDR_B_MA9
DDR_B_MA10DDR_B_D42
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13

DDR_B_RAS#

SB_RCVEN#

DDR_B_WE#

DDR_B_RAS# 14

T7

DDR_B_WE# 14

DDR_B_BS#0 14
DDR_B_BS#1 14
DDR_B_BS#2 14

DDR_B_DM[0..7] 14

DDR_B_DQS[0..7] 14

DDR_B_DQS#[0..7] 14

DDR_B_MA[0..13] 14

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2007/1/15 2008/1/15

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

Compal Electronics, Inc.

CRESTLINE((2/6)-DDR2 A/B CH

LA-4231P

1

of

849Thursday, January 10, 2008

0.1

5

For Crestline:2.4kohm
For Calero: 1.5Kohm

BIA_PWM15
GMCH_ENBKL15

+3VS

GMCH_EDID_CLK_LCD15
GMCH_EDID_DAT_LCD15

GMCH_LVDDEN15

D D

GMCH_LVDSAC-15
GMCH_LVDSAC+15

GMCH_LVDSA0-15
GMCH_LVDSA1-15
GMCH_LVDSA2-15

GMCH_LVDSA0+15
GMCH_LVDSA1+15
GMCH_LVDSA2+15

C C

CRT_B15
CRT_G15
CRT_R15

+3VS

2.2K_0402_5%

3VDDCCL
3VDDCDA
CRT_HSYNC

CRT_VSYNC

R483

UMA@

1 2

2.2K_0402_5%
R484

UMA@

1 2

3VDDCCL15
3VDDCDA15

CRT_HSYNC15
CRT_VSYNC15

B B

A A

BIA_PWM
GMCH_ENBKL

R81 10K_0402_5%UMA@

1 2

R80 10K_0402_5%UMA@

1 2

GMCH_EDID_CLK_LCD
GMCH_EDID_DAT_LCD

GMCH_LVDDEN

12

R94 2.4K_0402_1%

GMCH_LVDSAC­GMCH_LVDSAC+

GMCH_LVDSA0­GMCH_LVDSA1­GMCH_LVDSA2-

GMCH_LVDSA0+
GMCH_LVDSA1+
GMCH_LVDSA2+

1 2
1 2
1 2

CRT_B
CRT_G
CRT_R

R74

R76

UMA@

150_0402_1%

0_0402_5%
R675

VGA@

1 2

R682

VGA@

UMA@

1 2

150_0402_1%

1 2

1 2

0_0402_5%

R676

VGA@

1 2

GMCH_EDID_CLK_LCD

GMCH_EDID_DAT_LCD

0_0402_5%

CTRL_CLK
CTRL_DATA

R6575_0402_1%
R6775_0402_1%
R6875_0402_1%

R75

UMA@

1 2

150_0402_1%

1.3K_0402_1%

For Crestline:1.3kohm
For Calero: 255ohm

0_0402_5%
R677

VGA@

1 2

12

R334

U4C

J40
H39
E39
E40
C37
D35
K40

L41
L43
N41
N40
D46
C45
D44
E42

G51
E51
F49

G50
E50
F48

G44
B47
B45

E44
A47
A45

E27
G27
K27

F27
J27
L27

M35

P33

H32
G32
K29
J29
F29
E29

K33
G35
F33
C32
E33

CRESTLINE_1p0

L_BKLT_CTRL
L_BKLT_EN
L_CTRL_CLK
L_CTRL_DATA
L_DDC_CLK
L_DDC_DATA
L_VDD_EN

LVDS_IBG
LVDS_VBG
LVDS_VREFH
LVDS_VREFL
LVDSA_CLK#
LVDSA_CLK
LVDSB_CLK#
LVDSB_CLK

LVDSA_DATA#_0
LVDSA_DATA#_1
LVDSA_DATA#_2

LVDSA_DATA_0
LVDSA_DATA_1
LVDSA_DATA_2

LVDSB_DATA#_0
LVDSB_DATA#_1
LVDSB_DATA#_2

LVDSB_DATA_0
LVDSB_DATA_1
LVDSB_DATA_2

TVA_DAC
TVB_DAC
TVC_DAC

TVA_RTN
TVB_RTN
TVC_RTN

TV_DCONSEL_0
TV_DCONSEL_1

CRT_BLUE
CRT_BLUE#
CRT_GREEN
CRT_GREEN#
CRT_RED
CRT_RED#

CRT_DDC_CLK
CRT_DDC_DATA
CRT_HSYNC
CRT_TVO_IREF
CRT_VSYNC

CTRL_CLK

CTRL_DATA

4

0_0402_5%

R684

VGA@

R95

PEGCOMP

PEG_RX#_0
PEG_RX#_1
PEG_RX#_2
PEG_RX#_3
PEG_RX#_4
PEG_RX#_5
PEG_RX#_6
PEG_RX#_7
PEG_RX#_8
PEG_RX#_9

PEG_RX_0
PEG_RX_1
PEG_RX_2
PEG_RX_3
PEG_RX_4
PEG_RX_5
PEG_RX_6
PEG_RX_7
PEG_RX_8

PEG_RX_9
PEG_RX_10
PEG_RX_11
PEG_RX_12
PEG_RX_13
PEG_RX_14
PEG_RX_15

PEG_TX#_0
PEG_TX#_1
PEG_TX#_2
PEG_TX#_3
PEG_TX#_4
PEG_TX#_5
PEG_TX#_6
PEG_TX#_7
PEG_TX#_8
PEG_TX#_9

PEG_TX_0

PEG_TX_1

PEG_TX_2

PEG_TX_3

PEG_TX_4

PEG_TX_5

PEG_TX_6

PEG_TX_7

PEG_TX_8

PEG_TX_9
PEG_TX_10
PEG_TX_11
PEG_TX_12
PEG_TX_13
PEG_TX_14
PEG_TX_15

N43
M43

PEG_NRX_GTX_N0

J51

PEG_NRX_GTX_N1

L51

PEG_NRX_GTX_N2

N47

PEG_NRX_GTX_N3

T45

PEG_NRX_GTX_N4

T50

PEG_NRX_GTX_N5

U40

PEG_NRX_GTX_N6

Y44

PEG_NRX_GTX_N7

Y40

PEG_NRX_GTX_N8

AB51

PEG_NRX_GTX_N9

W49

PEG_NRX_GTX_N10

AD44

PEG_NRX_GTX_N11

AD40

PEG_NRX_GTX_N12

AG46

PEG_NRX_GTX_N13

AH49

PEG_NRX_GTX_N14

AG45

PEG_NRX_GTX_N15

AG41

PEG_NRX_GTX_P0

J50

PEG_NRX_GTX_P1

L50

PEG_NRX_GTX_P2

M47

PEG_NRX_GTX_P3

U44

PEG_NRX_GTX_P4

T49

PEG_NRX_GTX_P5

T41

PEG_NRX_GTX_P6

W45

PEG_NRX_GTX_P7

W41

PEG_NRX_GTX_P8

AB50

PEG_NRX_GTX_P9

Y48

PEG_NRX_GTX_P10

AC45

PEG_NRX_GTX_P11

AC41

PEG_NRX_GTX_P12

AH47

PEG_NRX_GTX_P13

AG49

PEG_NRX_GTX_P14

AH45

PEG_NRX_GTX_P15

AG42

PEG_TXN0

N45

PEG_TXN1

U39

PEG_TXN2

U47

PEG_TXN3

N51

PEG_TXN4

R50

PEG_TXN5

T42

PEG_TXN6

Y43

PEG_TXN7

W46

PEG_TXN8

W38

PEG_TXN9

AD39

PEG_TXN10

AC46

PEG_TXN11 PEG_NTX_GRX_N11

AC49

PEG_TXN12

AC42

PEG_TXN13

AH39

PEG_TXN14

AE49

PEG_TXN15

AH44

PEG_TXP0

M45

PEG_TXP1

T38

PEG_TXP2

T46

PEG_TXP3

N50

PEG_TXP4

R51

PEG_TXP5

U43

PEG_TXP6

W42

PEG_TXP7

Y47

PEG_TXP8

Y39

PEG_TXP9

AC38

PEG_TXP10

AD47

PEG_TXP11

AC50

PEG_TXP12

AD43

PEG_TXP13

AG39

PEG_TXP14

AE50

PEG_TXP15

AH43

PEG_COMPI

PEG_COMPO

LVDS

PEG_RX#_10
PEG_RX#_11
PEG_RX#_12
PEG_RX#_13
PEG_RX#_14
PEG_RX#_15

TV VGA

PEG_TX#_10

PCI-EXPRESS GRAPHICS

PEG_TX#_11
PEG_TX#_12
PEG_TX#_13
PEG_TX#_14
PEG_TX#_15

0_0402_5%
R683

VGA@

1 2

1 2

24.9_0402_1%

1 2

C568 0.1U_0402_16V7KVGA@
C537 0.1U_0402_16V7KVGA@
C538 0.1U_0402_16V7KVGA@
C539 0.1U_0402_16V7KVGA@
C540 0.1U_0402_16V7KVGA@
C541 0.1U_0402_16V7KVGA@
C542 0.1U_0402_16V7KVGA@
C543 0.1U_0402_16V7KVGA@
C544 0.1U_0402_16V7KVGA@
C545 0.1U_0402_16V7KVGA@
C546 0.1U_0402_16V7KVGA@
C547 0.1U_0402_16V7KVGA@
C548 0.1U_0402_16V7KVGA@
C549 0.1U_0402_16V7KVGA@
C550 0.1U_0402_16V7KVGA@
C551 0.1U_0402_16V7KVGA@

C552 0.1U_0402_16V7KVGA@
C553 0.1U_0402_16V7KVGA@
C554 0.1U_0402_16V7KVGA@
C555 0.1U_0402_16V7KVGA@
C556 0.1U_0402_16V7KVGA@
C557 0.1U_0402_16V7KVGA@
C558 0.1U_0402_16V7KVGA@
C559 0.1U_0402_16V7KVGA@
C560 0.1U_0402_16V7KVGA@
C561 0.1U_0402_16V7KVGA@
C562 0.1U_0402_16V7KVGA@
C563 0.1U_0402_16V7KVGA@
C564 0.1U_0402_16V7KVGA@
C565 0.1U_0402_16V7KVGA@
C566 0.1U_0402_16V7KVGA@
C567 0.1U_0402_16V7KVGA@

R74

0_0402_5%

VGA@

1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2

1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2

3

R76

0_0402_5%

VGA@

PEGCOMP trace width

+VCCP

and spacing is 20/25 mils.

PEG_NRX_GTX_N[0..15] 34

PEG_NRX_GTX_P[0..15] 34

PEG_NTX_GRX_N0
PEG_NTX_GRX_N1
PEG_NTX_GRX_N2
PEG_NTX_GRX_N3
PEG_NTX_GRX_N4
PEG_NTX_GRX_N5
PEG_NTX_GRX_N6
PEG_NTX_GRX_N7
PEG_NTX_GRX_N8
PEG_NTX_GRX_N9

PEG_NTX_GRX_N10
PEG_NTX_GRX_N12

PEG_NTX_GRX_N13
PEG_NTX_GRX_N14
PEG_NTX_GRX_N15

PEG_NTX_GRX_P0
PEG_NTX_GRX_P1
PEG_NTX_GRX_P2
PEG_NTX_GRX_P3
PEG_NTX_GRX_P4
PEG_NTX_GRX_P5
PEG_NTX_GRX_P6
PEG_NTX_GRX_P7
PEG_NTX_GRX_P8

PEG_NTX_GRX_P9
PEG_NTX_GRX_P10
PEG_NTX_GRX_P11
PEG_NTX_GRX_P12
PEG_NTX_GRX_P13
PEG_NTX_GRX_P14
PEG_NTX_GRX_P15

R75

0_0402_5%

VGA@

2

PEG_NTX_GRX_N[0..15] 34

PEG_NTX_GRX_P[0..15] 34

Strap Pin Table

CFG[2:0] FSB Freq select

CFG5 (DMI select)

CFG6

CFG7 (CPU Strap)

CFG8 (Low power PCIE)

CFG9

(PCIE Graphics Lane Reversal)

CFG[11:10]

CFG[13:12] (XOR/ALLZ)

CFG16 (FSB Dynamic ODT)

SDVO_CTRLDATA

CFG19 (DMI Lane Reversal)

CFG20 (PCIE/SDVO concurrent)

CFG[17:3] have internal pull up
CFG[19:18] have internal pull down

1

010 = FSB 800MHz
011 = FSB 667MHz
Others = Reserved

0 = DMI x 2
1 = DMI x 4

*

Reserved

0 = Reserved
1 = Mobile CPU

*

0 = Normal mode
1 = Low Power mode

*

0 = Reverse Lane
1 = Normal Operation

*

Reserved
00 = Reserved

01 = XOR Mode Enabled
10 = All Z Mode Enabled
11 = Normal Operation

(Default)

ReservedCFG[15:14]

0 = Disabled
1 = Enabled

*

ReservedCFG[18:17]

0 = No SDVO Device Present
1 = SDVO Device Present

0 = Normal Operation

(Lane number in Order)

*

1 = Reverse Lane

0 = Only PCIE or SDVO is operational.
1 = PCIE/SDVO are operating simu.

R66 4.02K_0402_1%@

CFG57

CFG77

CFG87

CFG97

CFG127

CFG137

CFG167

CFG197

CFG207

1 2

R58 4.02K_0402_1%@

1 2

R59 4.02K_0402_1%@

1 2

R55 4.02K_0402_1%@

1 2

R57 4.02K_0402_1%@

1 2

R63 4.02K_0402_1%@

1 2

R70 4.02K_0402_1%@

1 2

R72 4.02K_0402_1%@

1 2

R73 4.02K_0402_1%@

1 2

*

*

*

+3VS

Note: CRT / TV-out should route to JP30 first then to the JP1 & JP2 on system side.

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date

2007/1/15 2008/1/15

3

Compal Secret Data

Deciphered Date

2

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

CRESTLINE((3/6)-VGA/LVDS/TV

LA-4231P

1

of

949Thursday, January 10, 2008

0.1

5

+3VS_DAC_BG

D D

+3VS_DAC_CRT

C C

B B

A A

UMA@

0.1U_0402_16V4Z~N

0.022U_0402_16V7K~N

1

C406

2

BLM18PG181SN1D_0603

0.022U_0402_16V7K~N

UMA@

0.1U_0402_16V4Z~N

1

C407

2

+1.25VS

150U_B2_6.3VM_R45M

+3VS_TVDACA

0.022U_0402_16V7K~N

UMA@

1

C401

2

+3VS_TVDACB

0.022U_0402_16V7K~N

UMA@

1

C116

2

+3VS_TVDACC

0.022U_0402_16V7K~N

UMA@

1

C113

2

BLM18PG181SN1D_0603

UMA@

UMA@

4.7U_0805_10V4Z~N

1

1

C408

C405

2

2

UMA@

L11

1

C411

2

+3VS

R50

1 2

0_0805_5%

1

+

C68

22U_0805_6.3V4Z

2

+1.25VM_A_SM_CK

R71

12

0_0603_5%

R54

0_0603_5%

0.1U_0402_16V4Z~N

UMA@

1

C402

2

R62

0_0603_5%

0.1U_0402_16V4Z~N

UMA@

1

C96

2

R53

0_0603_5%

0.1U_0402_16V4Z~N

UMA@

1

C95

2

5

L10

UMA@

@

C103

+3VS

12

UMA@

+3VS

12

R97

1 2

0_0805_5%

C175

0.1U_0402_16V4Z~N

C82

1U_0402_6.3V4Z

C104

1

2

+3VS

12

UMA@

+3VS

12

UMA@

+3VS

12

UMA@

+3VS

+1.8V_TXLVDS

+3VS_PEG_BG

0317 change value

1

4.7U_0805_6.3V6K

2

22U_0805_6.3V4Z

1

2

+1.5VS_TVDAC

VCCSYNC

R92

UMA@

12

0_0603_5%

1

C141

UMA@

0.1U_0402_16V4Z~N

2

+3VS_DAC_CRT

+3VS_DAC_BG

+1.25VS_DPLLA
+1.25VS_DPLLB

+1.25VM_HPLL
+1.25VM_MPLL

1

C413 1000P_0402_50V7K~N

UMA@

2

1

1

2

+3VS_TVDACA
+3VS_TVDACB
+3VS_TVDACC

R674 0_0402_5%VGA@

+1.8V_LVDS

+1.5VS_QDAC

0.022U_0402_16V7K~N

1

C97

UMA@

2

+1.8V_LVDS

UMA@

10U_0805_10V4Z~N

C187

1

2

20 mils

12
12

1

C98

2

UMA@

1U_0603_10V4Z

C186

C122

+1.25VM_A_SM

C83

1U_0603_10V4Z

1

2

+1.25VS_PEGPLL

1

C72

2

1U_0603_10V4Z

0.1U_0402_16V4Z~N

C123

1

2

R673 0_0402_5% UMA@

+1.5VS_QDAC

+1.25VM_HPLL

+1.25VS_PEGPLL

2

@

J32
A33

B33

A30
B32

B49
H49
AL2

AM2

A41
B41

K50
K49

U51

AW18

AV19
AU19
AU18
AU17

AT22
AT21
AT19
AT18
AT17
AR17
AR16

BC29
BB29

C25
B25
C27
B27
B28
A28

M32

L29
N28

AN2

U48
J41

H42

R69

0_0603_5%

0.1U_0402_16V4Z~N

R109

0_0603_5%

1

UMA@

2

4

U4H

VCCSYNC
VCCA_CRT_DAC_1

VCCA_CRT_DAC_2

VCCA_DAC_BG
VSSA_DAC_BG

VCCA_DPLLA
VCCA_DPLLB
VCCA_HPLL
VCCA_MPLL

VCCA_LVDS
VSSA_LVDS

VCCA_PEG_BG
VSSA_PEG_BG

VCCA_PEG_PLL

VCCA_SM_1
VCCA_SM_2
VCCA_SM_3
VCCA_SM_4
VCCA_SM_5

VCCA_SM_7
VCCA_SM_8
VCCA_SM_9
VCCA_SM_10
VCCA_SM_11
VCCA_SM_NCTF_1
VCCA_SM_NCTF_2

VCCA_SM_CK_1
VCCA_SM_CK_2

VCCA_TVA_DAC_1
VCCA_TVA_DAC_2
VCCA_TVB_DAC_1
VCCA_TVB_DAC_2
VCCA_TVC_DAC_1
VCCA_TVC_DAC_2

VCCD_CRT
VCCD_TVDAC

VCCD_QDAC
VCCD_HPLL
VCCD_PEG_PLL
VCCD_LVDS_1

VCCD_LVDS_2

CRESTLINE_1p0 UMA@

12

UMA@

12

UMA@

4

POWER

D TV/CRTLVDS

+1.5VS

+1.8V

CRTPLLA PEGA SMTV

A CK A LVDS

VTT_1
VTT_2
VTT_3
VTT_4
VTT_5
VTT_6
VTT_7
VTT_8

VTT_9
VTT_10
VTT_11
VTT_12
VTT_13

VTT

VTT_14
VTT_15
VTT_16
VTT_17
VTT_18
VTT_19
VTT_20
VTT_21
VTT_22

VCC_AXD_1
VCC_AXD_2
VCC_AXD_3
VCC_AXD_4
VCC_AXD_5

AXD

VCC_AXD_6

VCC_AXD_NCTF

VCC_AXF_1
VCC_AXF_2
VCC_AXF_3

AXF

VCC_DMI

VCC_SM_CK_1
VCC_SM_CK_2
VCC_SM_CK_3
VCC_SM_CK_4

SM CK

VCC_TX_LVDS

VCC_HV_1
VCC_HV_2

HV

VCC_PEG_1
VCC_PEG_2
VCC_PEG_3
VCC_PEG_4

PEG

VCC_PEG_5

VCC_RXR_DMI_1
VCC_RXR_DMI_2

DMI

VTTLF1
VTTLF2
VTTLF3

VTTLF

+1.8V_TXLVDS

40 mils

1000P_0402_50V7K~N

1

C414

UMA@

2

3

+VCCP

330U_V_2.5VM

U13
U12
U11
U9
U8
U7
U5
U3
U2
U1
T13
T11
T10
T9
T7
T6
T5
T3
T2
R3
R2
R1

AT23
AU28
AU24
AT29
AT25
AT30

AR29

B23
B21
A21

AJ50

BK24
BK23
BJ24
BJ23

A43

C40
B40

AD51
W50
W51
V49
V50

AH50
AH51

A7
F2
AH1

C418

C382

0_0603_5% UMA@

1

+

220U_D2_4VY_R15M

UMA@

2

C370

+1.25VM_AXD

+1.8V_SM_CK

+1.8V_TXLVDS

0.47U_0603_10V7K
C385

1

2

R349

1

+

2

1

C383

2

1U_0603_10V4Z

1

2

+V1.25VS_AXF

+1.25VS_DMI

+VCC_PEG

20mils

0.47U_0603_10V7K
C65

1

2

12

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

4.7U_0805_10V4Z~N

1

C384

2

0.47U_0603_10V7K

C87

C88

0.47U_0603_10V7K

1

2

+1.8V

C373

1

2

+3VS_HV

C410

2.2U_0805_16V4Z

4.7U_0805_10V4Z~N

1

1

C56

2

2

R60

1 2

10U_0805_10V4Z~N

+1.25VS

0_0805_5%

0.1U_0402_16V4Z~N

1

2

2007/1/15 2008/1/15

Compal Secret Data

+1.25VS_DPLLB

0.1U_0402_16V4Z~N

UMA@

+1.25VS_DMI

+1.25VS_PEGPLL

+1.25VS_DPLLA

1

UMA@

+

C191

220U_D2_4VY_R15M

2

C406

0_0402_5%

VGA@

C407

0_0402_5%

VGA@

Deciphered Date

22U_0805_6.3VAM

C174

1

1

2

2

1 2

0.1U_0402_16V4Z~N
0_0603_5%

C180

1

2

10U_0805_10V4Z~N

0.1U_0402_16V4Z~N
C176

1

2

UMA@

C173

C182

1

2

0.1U_0402_16V4Z~N

+VCC_PEG

1

+

C417

220U_D2_4VY_R15M

2

C402

0_0402_5%

VGA@

C96

0_0402_5%

VGA@

2

UMA@

1 2

L14

10U_FLC-453232-100K_0.25A_10%

C178

UMA@

+1.25VS

R103

L12

BLM18PG121SN1D_0603

C179

1

2

L13

1 2

10U_0805_10V4Z~N

10U_FLC-453232-100K_0.25A_10%

UMA@

1

2

10U_0805_10V4Z~N

C416

1

2

C95

0_0402_5%

VGA@

C98

0_0402_5%

VGA@

2

+1.25VS

+1.25VS

12

UMA@

+1.25VS

Take off 0ohm 0805
because Layout

+VCCP

CH751H-40PT_SOD323-2

+3VS

C186

0_0603_5%

VGA@

C174

0_0402_5%

VGA@

1

+V1.25VS_AXF

10U_0805_10V4Z~N

1U_0603_10V4Z

C394

1

2

+1.8V_SM_CK

10U_0603_6.3V6M

22U_0805_6.3V4Z

0.1U_0402_16V4Z~N

+VCCP

0.1U_0402_16V4Z~N

+VCCP_D

D7

2 1

C413

0_0402_5%

VGA@

C141

0_0402_5%

VGA@

Title

CRESTLINE(4/6)-PWR

Size Document Number Rev

Custom

LA-4231P

Date: Sheet

1

1

2

C396

+1.5VS_TVDAC

+1.25VM_HPLL

C380

+1.25VM_MPLL

C63

R79

10_0402_5%

2

1

C115

2

1

2

1

2

12

C395

0.022U_0402_16V7K~N

U4

CRESTLINE_1p0

C173

0_0402_5%

VGA@

Compal Electronics, Inc.

0.1U_0402_16V4Z~N

0.1U_0402_16V4Z~N

1

C114

2

MBK2012121YZF_0805

1

C381
10U_0805_10V4Z~N

2

MBK2012121YZF_0805

1

C62
10U_0805_10V4Z~N

2

R93

0_0402_5%

VGA@

1

C397

1

2

1 2

C399

1

2

1 2

L29

L9

12

1 2

R327

0_0805_5%

R64

0_0805_5%

12

+1.25VS

12

R330

0_0603_5%

+1.25VS

+3VS_HV

of

10 49Thursday, January 10, 2008

+1.25VS

+1.8V

+1.5VS

0.1

5

4

3

2

1

+VCCP

1

2

C119

C117

+VCCP

0.1U_0402_16V4Z~N

C120

1

2

10U_0805_10V4Z~N

C121

C162

1

2

0.1U_0402_16V4Z~N
C102

1

2

U4F

AB33

VCC_NCTF_1

AB36

VCC_NCTF_2

AB37

VCC_NCTF_3

AC33

VCC_NCTF_4

AC35

VCC_NCTF_5

AC36

VCC_NCTF_6

AD35

VCC_NCTF_7

AD36

VCC_NCTF_8

AF33

VCC_NCTF_9

AF36

VCC_NCTF_10

AH33

VCC_NCTF_11

AH35

VCC_NCTF_12

AH36

VCC_NCTF_13

AH37

VCC_NCTF_14

AJ33

VCC_NCTF_15

AJ35

VCC_NCTF_16

AK33

VCC_NCTF_17

AK35

VCC_NCTF_18

AK36

VCC_NCTF_19

AK37

VCC_NCTF_20

AD33

VCC_NCTF_21

AJ36

VCC_NCTF_22

AM35

VCC_NCTF_23

AL33

VCC_NCTF_24

AL35

VCC_NCTF_25

AA33

VCC_NCTF_26

AA35

VCC_NCTF_27

AA36

VCC_NCTF_28

AP35

VCC_NCTF_29

AP36

VCC_NCTF_30

AR35

VCC_NCTF_31

AR36

VCC_NCTF_32

Y32

VCC_NCTF_33

Y33

VCC_NCTF_34

Y35

VCC_NCTF_35

Y36

VCC_NCTF_36

Y37

VCC_NCTF_37

T30

VCC_NCTF_38

T34

VCC_NCTF_39

T35

VCC_NCTF_40

U29

VCC_NCTF_41

U31

VCC_NCTF_42

U32

VCC_NCTF_43

U33

VCC_NCTF_44

U35

VCC_NCTF_45

U36

VCC_NCTF_46

V32

VCC_NCTF_47

V33

VCC_NCTF_48

V36

VCC_NCTF_49

V37

VCC_NCTF_50

AL24

VCC_AXM_NCTF_1

AL26

VCC_AXM_NCTF_2

AL28

VCC_AXM_NCTF_3

AM26

VCC_AXM_NCTF_4

AM28

VCC_AXM_NCTF_5

AM29

VCC_AXM_NCTF_6

AM31

VCC_AXM_NCTF_7

AM32

VCC_AXM_NCTF_8

AM33

VCC_AXM_NCTF_9

AP29

VCC_AXM_NCTF_10

AP31

VCC_AXM_NCTF_11

AP32

VCC_AXM_NCTF_12

AP33

VCC_AXM_NCTF_13

AL29

VCC_AXM_NCTF_14

AL31

VCC_AXM_NCTF_15

AL32

VCC_AXM_NCTF_16

AR31

VCC_AXM_NCTF_17

AR32

VCC_AXM_NCTF_18

AR33

VCC_AXM_NCTF_19

CRESTLINE_1p0 UMA@

VSS NCTF

VCC NCTF

POWER

VCC AXM NCTF

VSS_NCTF_1
VSS_NCTF_2
VSS_NCTF_3
VSS_NCTF_4
VSS_NCTF_5
VSS_NCTF_6
VSS_NCTF_7
VSS_NCTF_8

VSS_NCTF_9
VSS_NCTF_10
VSS_NCTF_11
VSS_NCTF_12
VSS_NCTF_13
VSS_NCTF_14
VSS_NCTF_15
VSS_NCTF_16
VSS_NCTF_17
VSS_NCTF_18
VSS_NCTF_19
VSS_NCTF_20
VSS_NCTF_21

VSS_SCB1
VSS_SCB2
VSS_SCB3
VSS_SCB4
VSS_SCB5
VSS_SCB6

VSS SCBVCC AXM

VCC_AXM_1
VCC_AXM_2
VCC_AXM_3
VCC_AXM_4
VCC_AXM_5
VCC_AXM_6
VCC_AXM_7

T27
T37
U24
U28
V31
V35
AA19
AB17
AB35
AD19
AD37
AF17
AF35
AK17
AM17
AM24
AP26
AP28
AR15
AR19
AR28

A3
B2
C1
BL1
BL51
A51

AT33
AT31
AK29
AK24
AK23
AJ26
AJ23

+VCCP

C78

1U_0603_10V4Z

1

C57

2

UMA@

330U_V_2.5VM

+1.8V

1

+

C148

330U_V_2.5VM

2

10U_0805_10V4Z~N

1

+

C100

2

UMA@

160mil

22U_0805_6.3V4Z

22U_0805_6.3V4Z

C165

1

2

1

1

C79

2

2

UMA@

10U_0805_10V4Z~N

1 2

0_0603_5%

0.01U_0402_16V7K~N

C147

2

1

1

2

+VCCP

0.1U_0402_16V4Z~N

1

C80

2

UMA@

UMA@

R78

C164

D D

22U_0805_6.3V4Z

0.22U_0402_10V4Z~N

1

2

0.22U_0402_10V4Z~N

C118

+VCCP

0.22U_0402_10V4Z~N

C143

12

12

10U_0805_10V4Z~N

0.1U_0402_16V4Z~N

0.1U_0402_16V4Z~N
C142

1

1

2

2

1

+

C374

220U_D2_4VY_R15M

2

C C

B B

0.22U_0402_10V4Z~N
C144

C161

12

12

AT35
AT34
AH28
AC32
AC31
AK32

AJ31

AJ28
AH32
AH31
AH29
AF32

AU32
AU33
AU35
AV33

AW33
AW35

AY35
BA32
BA33
BA35
BB33
BC32
BC33
BC35
BD32
BD35
BE32
BE33
BE35
BF33
BF34
BG32
BG33
BG35
BH32
BH34
BH35

BJ32

BJ33

BJ34
BK32
BK33
BK34
BK35

BL33
AU30

W13
W14

AA20
AA23
AA26
AA28
AB21
AB24
AB29
AC20
AC21
AC23
AC24
AC26
AC28
AC29
AD20
AD23
AD24
AD28
AF21
AF26
AA31
AH20
AH21
AH23
AH24
AH26
AD31

AJ20
AN14

R30

R20
T14

Y12

U4G

VCC_1
VCC_2
VCC_3
VCC_5
VCC_4
VCC_6
VCC_7
VCC_8
VCC_9
VCC_10
VCC_11
VCC_12

VCC_13

VCC_SM_1
VCC_SM_2
VCC_SM_3
VCC_SM_4
VCC_SM_5
VCC_SM_6
VCC_SM_7
VCC_SM_8
VCC_SM_9
VCC_SM_10
VCC_SM_11
VCC_SM_12
VCC_SM_13
VCC_SM_14
VCC_SM_15
VCC_SM_16
VCC_SM_17
VCC_SM_18
VCC_SM_19
VCC_SM_20
VCC_SM_21
VCC_SM_22
VCC_SM_23
VCC_SM_24
VCC_SM_25
VCC_SM_26
VCC_SM_27
VCC_SM_28
VCC_SM_29
VCC_SM_30
VCC_SM_31
VCC_SM_32
VCC_SM_33
VCC_SM_34
VCC_SM_35
VCC_SM_36

VCC_AXG_1
VCC_AXG_2
VCC_AXG_3
VCC_AXG_4
VCC_AXG_5
VCC_AXG_6
VCC_AXG_7
VCC_AXG_8
VCC_AXG_9
VCC_AXG_10
VCC_AXG_11
VCC_AXG_12
VCC_AXG_13
VCC_AXG_14
VCC_AXG_15
VCC_AXG_16
VCC_AXG_17
VCC_AXG_18
VCC_AXG_19
VCC_AXG_20
VCC_AXG_21
VCC_AXG_22
VCC_AXG_23
VCC_AXG_24
VCC_AXG_25
VCC_AXG_26
VCC_AXG_27
VCC_AXG_28
VCC_AXG_29
VCC_AXG_30
VCC_AXG_31
VCC_AXG_32
VCC_AXG_33
VCC_AXG_34

VCC CORE

POWER

VCC SMVCC GFX

VCC_AXG_NCTF_1
VCC_AXG_NCTF_2
VCC_AXG_NCTF_3
VCC_AXG_NCTF_4
VCC_AXG_NCTF_5
VCC_AXG_NCTF_6
VCC_AXG_NCTF_7
VCC_AXG_NCTF_8

VCC_AXG_NCTF_9
VCC_AXG_NCTF_10
VCC_AXG_NCTF_11
VCC_AXG_NCTF_12
VCC_AXG_NCTF_13
VCC_AXG_NCTF_14
VCC_AXG_NCTF_15
VCC_AXG_NCTF_16
VCC_AXG_NCTF_17
VCC_AXG_NCTF_18
VCC_AXG_NCTF_19
VCC_AXG_NCTF_20
VCC_AXG_NCTF_21
VCC_AXG_NCTF_22
VCC_AXG_NCTF_23
VCC_AXG_NCTF_24
VCC_AXG_NCTF_25
VCC_AXG_NCTF_26
VCC_AXG_NCTF_27
VCC_AXG_NCTF_28
VCC_AXG_NCTF_29
VCC_AXG_NCTF_30
VCC_AXG_NCTF_31
VCC_AXG_NCTF_32
VCC_AXG_NCTF_33
VCC_AXG_NCTF_34
VCC_AXG_NCTF_35
VCC_AXG_NCTF_36
VCC_AXG_NCTF_37
VCC_AXG_NCTF_38
VCC_AXG_NCTF_39
VCC_AXG_NCTF_40
VCC_AXG_NCTF_41
VCC_AXG_NCTF_42
VCC_AXG_NCTF_43
VCC_AXG_NCTF_44
VCC_AXG_NCTF_45
VCC_AXG_NCTF_46
VCC_AXG_NCTF_47
VCC_AXG_NCTF_48
VCC_AXG_NCTF_49
VCC_AXG_NCTF_50
VCC_AXG_NCTF_51
VCC_AXG_NCTF_52
VCC_AXG_NCTF_53
VCC_AXG_NCTF_54

VCC GFX NCTF

VCC_AXG_NCTF_55
VCC_AXG_NCTF_56
VCC_AXG_NCTF_57
VCC_AXG_NCTF_58
VCC_AXG_NCTF_59
VCC_AXG_NCTF_60
VCC_AXG_NCTF_61
VCC_AXG_NCTF_62
VCC_AXG_NCTF_63
VCC_AXG_NCTF_64
VCC_AXG_NCTF_65
VCC_AXG_NCTF_66
VCC_AXG_NCTF_67
VCC_AXG_NCTF_68
VCC_AXG_NCTF_69
VCC_AXG_NCTF_70
VCC_AXG_NCTF_71
VCC_AXG_NCTF_72
VCC_AXG_NCTF_73
VCC_AXG_NCTF_74
VCC_AXG_NCTF_75
VCC_AXG_NCTF_76
VCC_AXG_NCTF_77
VCC_AXG_NCTF_78
VCC_AXG_NCTF_79
VCC_AXG_NCTF_80
VCC_AXG_NCTF_81
VCC_AXG_NCTF_82
VCC_AXG_NCTF_83

VCC_SM_LF1
VCC_SM_LF2
VCC_SM_LF3
VCC_SM_LF4
VCC_SM_LF5
VCC_SM_LF6
VCC_SM_LF7

VCC SM LF

T17
T18
T19
T21
T22
T23
T25
U15
U16
U17
U19
U20
U21
U23
U26
V16
V17
V19
V20
V21
V23
V24
Y15
Y16
Y17
Y19
Y20
Y21
Y23
Y24
Y26
Y28
Y29
AA16
AA17
AB16
AB19
AC16
AC17
AC19
AD15
AD16
AD17
AF16
AF19
AH15
AH16
AH17
AH19
AJ16
AJ17
AJ19
AK16
AK19
AL16
AL17
AL19
AL20
AL21
AL23
AM15
AM16
AM19
AM20
AM21
AM23
AP15
AP16
AP17
AP19
AP20
AP21
AP23
AP24
AR20
AR21
AR23
AR24
AR26
V26
V28
V29
Y31

AW45
BC39
BE39
BD17
BD4
AW8
AT6

+VCCP

VCCSM_LF1
VCCSM_LF2
VCCSM_LF3
VCCSM_LF4
VCCSM_LF5
VCCSM_LF6
VCCSM_LF7

370mil

0.1U_0402_16V4Z~N

1

C99

UMA@

2

C71 0.1U_0402_16V4Z~N

C70 0.1U_0402_16V4Z~N

1

1

2

2

0.47U_0603_10V7K

12

C86

UMA@

UMA@

0.22U_0402_10V4Z~N

C146 0.47U_0402_6.3V6K

C81 0.22U_0603_10V7K~N

C67 0.22U_0603_10V7K~N

1

1

1

2

2

2

1

C101

2

C163 1U_0603_10V4Z

C145 1U_0603_10V4Z

1

1

2

2

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2007/1/15 2008/1/15

Compal Secret Data

Deciphered Date

CRESTLINE_1p0 UMA@

2

Compal Electronics, Inc.

Title

CRESTLINE((5/6)-PWR/GND

Size Document Number Rev

Custom

LA-4231P

Date: Sheet

1

of

11 49Thursday, January 10, 2008

0.1

5

U4I

A13

VSS_1

A15

VSS_2

A17

VSS_3

A24

VSS_4

AA21

VSS_5

AA24

VSS_6

AA29

VSS_7

AB20

D D

C C

B B

A A

VSS_8

AB23

VSS_9

AB26

VSS_10

AB28

VSS_11

AB31

VSS_12

AC10

VSS_13

AC13

VSS_14

AC3

VSS_15

AC39

VSS_16

AC43

VSS_17

AC47

VSS_18

AD1

VSS_19

AD21

VSS_20

AD26

VSS_21

AD29

VSS_22

AD3

VSS_23

AD41

VSS_24

AD45

VSS_25

AD49

VSS_26

AD5

VSS_27

AD50

VSS_28

AD8

VSS_29

AE10

VSS_30

AE14

VSS_31

AE6

VSS_32

AF20

VSS_33

AF23

VSS_34

AF24

VSS_35

AF31

VSS_36

AG2

VSS_37

AG38

VSS_38

AG43

VSS_39

AG47

VSS_40

AG50

VSS_41

AH3

VSS_42

AH40

VSS_43

AH41

VSS_44

AH7

VSS_45

AH9

VSS_46

AJ11

VSS_47

AJ13

VSS_48

AJ21

VSS_49

AJ24

VSS_50

AJ29

VSS_51

AJ32

VSS_52

AJ43

VSS_53

AJ45

VSS_54

AJ49

VSS_55

AK20

VSS_56

AK21

VSS_57

AK26

VSS_58

AK28

VSS_59

AK31

VSS_60

AK51

VSS_61

AL1

VSS_62

AM11

VSS_63

AM13

VSS_64

AM3

VSS_65

AM4

VSS_66

AM41

VSS_67

AM45

VSS_68

AN1

VSS_69

AN38

VSS_70

AN39

VSS_71

AN43

VSS_72

AN5

VSS_73

AN7

VSS_74

AP4

VSS_75

AP48

VSS_76

AP50

VSS_77

AR11

VSS_78

AR2

VSS_79

AR39

VSS_80

AR44

VSS_81

AR47

VSS_82

AR7

VSS_83

AT10

VSS_84

AT14

VSS_85

AT41

VSS_86

AT49

VSS_87

AU1

VSS_88

AU23

VSS_89

AU29

VSS_90

AU3

VSS_91

AU36

VSS_92

AU49

VSS_93

AU51

VSS_94

AV39

VSS_95

AV48

VSS_96

AW1

VSS_97

AW12

VSS_98

AW16

VSS_99

CRESTLINE_1p0 UMA@

VSS

VSS_100
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105
VSS_106
VSS_107
VSS_108
VSS_109
VSS_110
VSS_111
VSS_112
VSS_113
VSS_114
VSS_115
VSS_116
VSS_117
VSS_118
VSS_119
VSS_120
VSS_121
VSS_122
VSS_123
VSS_124
VSS_125
VSS_126
VSS_127
VSS_128
VSS_129
VSS_130
VSS_131
VSS_132
VSS_133
VSS_134
VSS_135
VSS_136
VSS_137
VSS_138
VSS_139
VSS_140
VSS_141
VSS_142
VSS_143
VSS_144
VSS_145
VSS_146
VSS_147
VSS_148
VSS_149
VSS_150
VSS_151
VSS_152
VSS_153
VSS_154
VSS_155
VSS_156
VSS_157
VSS_158
VSS_159
VSS_160
VSS_161
VSS_162
VSS_163
VSS_164
VSS_165
VSS_166
VSS_167
VSS_168
VSS_169
VSS_170
VSS_171
VSS_172
VSS_173
VSS_174
VSS_175
VSS_176
VSS_177
VSS_178
VSS_179
VSS_180
VSS_181
VSS_182
VSS_183
VSS_184
VSS_185
VSS_186
VSS_187
VSS_188
VSS_189
VSS_190
VSS_191
VSS_192
VSS_193
VSS_194
VSS_195
VSS_196
VSS_197
VSS_198

4

AW24
AW29
AW32
AW5
AW7
AY10
AY24
AY37
AY42
AY43
AY45
AY47
AY50
B10
B20
B24
B29
B30
B35
B38
B43
B46
B5
B8
BA1
BA17
BA18
BA2
BA24
BB12
BB25
BB40
BB44
BB49
BB8
BC16
BC24
BC25
BC36
BC40
BC51
BD13
BD2
BD28
BD45
BD48
BD5
BE1
BE19
BE23
BE30
BE42
BE51
BE8
BF12
BF16
BF36
BG19
BG2
BG24
BG29
BG39
BG48
BG5
BG51
BH17
BH30
BH44
BH46
BH8
BJ11
BJ13
BJ38
BJ4
BJ42
BJ46
BK15
BK17
BK25
BK29
BK36
BK40
BK44
BK6
BK8
BL11
BL13
BL19
BL22
BL37
BL47
C12
C16
C19
C28
C29
C33
C36
C41

3

U4J

C46

VSS_199

C50

VSS_200

C7

VSS_201

D13

VSS_202

D24

VSS_203

D3

VSS_204

D32

VSS_205

D39

VSS_206

D45

VSS_207

D49

VSS_208

E10

VSS_209

E16

VSS_210

E24

VSS_211

E28

VSS_212

E32

VSS_213

E47

VSS_214

F19

VSS_215

F36

VSS_216

F4

VSS_217

F40

VSS_218

F50

VSS_219

G1

VSS_220

G13

VSS_221

G16

VSS_222

G19

VSS_223

G24

VSS_224

G28

VSS_225

G29

VSS_226

G33

VSS_227

G42

VSS_228

G45

VSS_229

G48

VSS_230

G8

VSS_231

H24

VSS_232

H28

VSS_233

H4

VSS_234

H45

VSS_235

J11

VSS_236

J16

VSS_237

J2

VSS_238

J24

VSS_239

J28

VSS_240

J33

VSS_241

J35

VSS_242

J39

VSS_243

K12

VSS_245

K47

VSS_246

K8

VSS_247

L1

VSS_248

L17

VSS_249

L20

VSS_250

L24

VSS_251

L28

VSS_252

L3

VSS_253

L33

VSS_254

L49

VSS_255

M28

VSS_256

M42

VSS_257

M46

VSS_258

M49

VSS_259

M5

VSS_260

M50

VSS_261

M9

VSS_262

N11

VSS_263

N14

VSS_264

N17

VSS_265

N29

VSS_266

N32

VSS_267

N36

VSS_268

N39

VSS_269

N44

VSS_270

N49

VSS_271

N7

VSS_272

P19

VSS_273

P2

VSS_274

P23

VSS_275

P3

VSS_276

P50

VSS_277

R49

VSS_278

T39

VSS_279

T43

VSS_280

T47

VSS_281

U41

VSS_282

U45

VSS_283

U50

VSS_284

V2

VSS_285

V3

VSS_286

CRESTLINE_1p0 UMA@

VSS

VSS_287
VSS_288
VSS_289
VSS_290
VSS_291
VSS_292
VSS_293
VSS_294
VSS_295
VSS_296
VSS_297
VSS_298
VSS_299
VSS_300
VSS_301
VSS_302
VSS_303
VSS_304
VSS_305

VSS_306
VSS_307
VSS_308
VSS_309
VSS_310
VSS_311
VSS_312
VSS_313

W11
W39
W43
W47
W5
W7
Y13
Y2
Y41
Y45
Y49
Y5
Y50
Y11
P29
T29
T31
T33
R28

AA32
AB32
AD32
AF28
AF29
AT27
AV25
H50

2

1

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2007/1/15 2008/1/15

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

Compal Electronics, Inc.

CRESTLINE((6/6)-PWR/GND

LA-4231P

12 49Thursday, January 10, 2008

1

0.1

of

5

DDR_A_DQS#[0..7]8

DDR_A_D[0..63]8

DDR_A_DM[0..7]8
DDR_A_DQS[0..7]8
DDR_A_MA[0..13]8

D D

Layout Note:
Place near JDIM1

+DDR_MCH_REF114

close to connector

+1.8V

2.2U_0603_6.3V6K

2.2U_0603_6.3V6K

2.2U_0603_6.3V6K

C105

C124

1

1

2

2

Layout Note:

C C

Place one cap close to every 2 pullup
resistors terminated to +0.9V

+0.9VS

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

2

2

C106

C125

B B

DDR_A_MA5
DDR_A_MA8

DDR_A_MA1
DDR_A_MA3

DDR_A_RAS#
DDR_CS0_DIMMA#

DDR_A_BS#0

A A

DDR_A_MA10

DDR_A_CAS#
DDR_A_WE#

DDR_CS1_DIMMA#
M_ODT1

DDR_CKE1_DIMMA

2.2U_0603_6.3V6K

2.2U_0603_6.3V6K
C149

1

2

DDR_A_V

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

2

C126

RP14

1 4
2 3

RP13

56_0404_4P2R_5%

1 4
2 3

RP7

56_0404_4P2R_5%

1 4
2 3

RP6

56_0404_4P2R_5%

1 4
2 3

RP5

56_0404_4P2R_5%

1 4
2 3

56_0404_4P2R_5%

RP1

2 3
1 4

56_0404_4P2R_5%

1 2

R96 56_0402_5%

5

1

2

C127

C166

1

2

0.1U_0402_16V4Z

DDR_A_V

1

2

0.1U_0402_16V4Z

C169

C154

1

1

2

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

2

2

C151

DDR_A_MA12

14

DDR_CKE0_DIMMA

23

DDR_A_MA7

14

DDR_A_MA6

23

DDR_A_MA9

14

DDR_A_BS#2

23

DDR_A_MA4

14

DDR_A_MA2

23

DDR_A_MA0

14

DDR_A_BS#1

23

M_ODT0

14

DDR_A_MA13

23

DDR_A_MA14

14

DDR_A_MA11

23

C167

C150

RP22 56_0404_4P2R_5%

RP17 56_0404_4P2R_5%

RP15 56_0404_4P2R_5%

RP16 56_0404_4P2R_5%

RP8 56_0404_4P2R_5%

RP2 56_0404_4P2R_5%

RP23 56_0404_4P2R_5%

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

C130

C131

1

1

2

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

2

2

C107

C128

4

Layout Note:
+DDR_MCH_REF
trace width and
spacing is 20/20.

+DDR_MCH_REF1

1

C206

2

0.1U_0402_16V4Z~N

330U 2.5V Y D2

0.1U_0402_16V4Z

1

2

C129

1

C84

C108

1

+

2

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

2

2

C153

C152

Layout Note:
Place these resistor
closely JP41,all
trace length Max=1.5"

4

@

3

+1.8V

+1.8V

+3VS

C58

0.1U_0402_16V4Z

DDR_A_D4
DDR_A_D1

DDR_A_DQS#0
DDR_A_DQS0

DDR_A_D2
DDR_A_D3

DDR_A_D8
DDR_A_D14

DDR_A_DQS#1
DDR_A_DQS1

DDR_A_D9

DDR_A_D16
DDR_A_D17

DDR_A_DQS#2
DDR_A_DQS2

DDR_A_D18
DDR_A_D19

DDR_A_D29
DDR_A_D24

DDR_A_DM3

DDR_A_D26
DDR_A_D27

DDR_CKE0_DIMMA

DDR_A_BS#2
DDR_A_MA12
DDR_A_MA8
DDR_A_MA5

DDR_A_MA3
DDR_A_MA1

DDR_A_MA10
DDR_A_BS#0

DDR_A_CAS#
DDR_CS1_DIMMA#

M_ODT1
DDR_A_D37

DDR_A_D36
DDR_A_DQS#4

DDR_A_DQS4
DDR_A_D35

DDR_A_D34
DDR_A_D40

DDR_A_D44
DDR_A_DM5
DDR_A_D41

DDR_A_D46
DDR_A_D49

DDR_A_D48

DDR_A_DQS#6
DDR_A_DQS6

DDR_A_D54
DDR_A_D50

DDR_A_D61
DDR_A_D60

DDR_A_DM7
DDR_A_D59

DDR_A_D58
ICH_SM_DA

ICH_SM_CLK

1

1

2

2

C59

2.2U_0603_6.3V6K

12

R143
1K_0402_1%

12

R144
1K_0402_1%

DDR_CKE0_DIMMA7

DDR_A_BS#28

DDR_A_BS#08

DDR_A_WE#8

DDR_A_CAS#8

0.1U_0402_16V4Z

1

2

C168

DDR_CS1_DIMMA#7

M_ODT17

ICH_SM_DA14,16,19,24

ICH_SM_CLK14,16,19,24

JDIM2

1

VREF

3

VSS

5

DQ0

7

DQ1

9

VSS

11

DQS0#

13

DQS0

15

VSS

17

DQ2

19

DQ3

21

VSS

23

DQ8

25

DQ9

27

VSS

29

DQS1#

31

DQS1

33

VSS

35

DQ10

37

DQ11

39

VSS

41

VSS

43

DQ16

45

DQ17

47

VSS

49

DQS2#

51

DQS2

53

VSS

55

DQ18

57

DQ19

59

VSS

61

DQ24

63

DQ25

65

VSS

67

DM3

69

NC

71

VSS

73

DQ26

75

DQ27

77

VSS

79

CKE0

81

VDD

83

NC

85

BA2

87

VDD

89

A12

91

A9

93

A8

95

VDD

97

A5

99

A3

101

A1

103

VDD

105

A10/AP

107

BA0

109

WE#

111

VDD

113

CAS#

115

NC/S1#

117

VDD

119

NC/ODT1

121

VSS

123

DQ32

125

DQ33

127

VSS

129

DQS4#

131

DQS4

133

VSS

135

DQ34

137

DQ35

139

VSS

141

DQ40

143

DQ41

145

VSS

147

DM5

149

VSS

151

DQ42

153

DQ43

155

VSS

157

DQ48

159

DQ49

161

VSS

163

NC,TEST

165

VSS

167

DQS6#

169

DQS6

171

VSS

173

DQ50

175

DQ51

177

VSS

179

DQ56

181

DQ57

183

VSS

185

DM7

187

VSS

189

DQ58

191

DQ59

193

VSS

195

SDA

197

SCL

199

VDDSPD

FOX_ASOA426-M2RN-7F

SO-DIMM A

REVERSE

VSS
DQ4
DQ5
VSS
DM0
VSS
DQ6
DQ7

VSS
DQ12
DQ13

VSS

DM1

VSS

CK0

CK0#

VSS
DQ14
DQ15

VSS

VSS
DQ20
DQ21

VSS

DM2

VSS
DQ22
DQ23

VSS
DQ28
DQ29

VSS

DQS3#

DQS3

VSS
DQ30
DQ31

VSS

NC/CKE1

VDD

NC/A15
NC/A14

VDD

VDD

VDD

BA1

RAS#

VDD
ODT0

NC/A13

VDD

VSS
DQ36
DQ37

VSS

DM4

VSS
DQ38
DQ39

VSS
DQ44
DQ45

VSS

DQS5#

DQS5

VSS
DQ46
DQ47

VSS
DQ52
DQ53

VSS

CK1

CK1#

VSS

DM6

VSS
DQ54
DQ55

VSS
DQ60
DQ61

VSS

DQS7#

DQS7

VSS
DQ62
DQ63

VSS

SA0

SA1

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

42
44
46
48
50

NC

52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90

A11

92

A7

94

A6

96
98

A4

100

A2

102

A0

104
106
108
110

S0#

112
114
116
118
120

NC

122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200

2

DDR_A_D6
DDR_A_D0

DDR_A_DM0
DDR_A_D5

DDR_A_D7
DDR_A_D13

DDR_A_D12
DDR_A_DM1
M_CLK_DDR0

M_CLK_DDR#0
DDR_A_D11

DDR_A_D10DDR_A_D15

DDR_A_D20
DDR_A_D21

DDR_A_DM2
DDR_A_D23

DDR_A_D22
DDR_A_D28

DDR_A_D25
DDR_A_DQS#3

DDR_A_DQS3
DDR_A_D31

DDR_A_D30
DDR_CKE1_DIMMA

DDR_A_MA14
DDR_A_MA11

DDR_A_MA7DDR_A_MA9
DDR_A_MA6

DDR_A_MA4
DDR_A_MA2
DDR_A_MA0

DDR_A_BS#1
DDR_A_RAS#
DDR_CS0_DIMMA#DDR_A_WE#

M_ODT0
DDR_A_MA13

DDR_A_D32
DDR_A_D33

DDR_A_DM4
DDR_A_D39

DDR_A_D38
DDR_A_D45

DDR_A_D43
DDR_A_DQS#5

DDR_A_DQS5
DDR_A_D47

DDR_A_D42
DDR_A_D52

DDR_A_D53
M_CLK_DDR1

M_CLK_DDR#1
DDR_A_DM6
DDR_A_D51

DDR_A_D55
DDR_A_D57

DDR_A_D56
DDR_A_DQS#7

DDR_A_DQS7
DDR_A_D62

DDR_A_D63

12

R32

R31

10K_0402_5%

10K_0402_5%

Close to VREF pins of SO-DIMM

2.2U_0805_16V4Z
C201

1

2

M_CLK_DDR0 7
M_CLK_DDR#0 7

PM_EXTTS#0 7

DDR_CKE1_DIMMA 7

DDR_A_MA14 7

DDR_A_BS#1 8
DDR_A_RAS# 8
DDR_CS0_DIMMA# 7

M_ODT0 7

M_CLK_DDR1 7
M_CLK_DDR#1 7

12

0.1U_0402_16V4Z
C220

1

2

1

+DDR_MCH_REF1

Bottom side

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2007/1/15 2008/1/15

3

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

Compal Electronics, Inc.

DDR2 SO-DIMM I

LA-4231P

0.1

of

13 49Thursday, January 10, 2008

1

5

DDR_B_DQS#[0..7]8

DDR_B_D[0..63]8

DDR_B_DM[0..7]8

DDR_B_DQS[0..7]8

DDR_B_MA[0..13]8

D D

Layout Note:
Place near JDIM2

+1.8V

2.2U_0603_6.3V6K

2.2U_0603_6.3V6K

2.2U_0603_6.3V6K

C112

C139

1

1

2

2

Layout Note:
Place one cap close to every 2 pullup
resistors terminated to +0.9VS

C C

+0.9VS

1

2

C110

0.1U_0402_16V4Z

1

2

C134

RP18

RP10

RP12

RP11

RP9

RP3

R335 56_0402_5%

0.1U_0402_16V4Z

0.1U_0402_16V4Z

B B

DDR_B_MA3
DDR_B_MA1

DDR_B_BS#0
DDR_B_MA10

DDR_B_MA0
DDR_B_BS#1

DDR_B_RAS#
DDR_CS2_DIMMB#

A A

DDR_B_CAS#
DDR_B_WE#

DDR_CS3_DIMMB#
M_ODT3

DDR_CKE3_DIMMB

2.2U_0603_6.3V6K
C160

1

2

0.1U_0402_16V4Z

1

2

C135

1 4
2 3

56_0404_4P2R_5%

1 4
2 3

56_0404_4P2R_5%

1 4
2 3

56_0404_4P2R_5%

1 4
2 3

56_0404_4P2R_5%

1 4
2 3

56_0404_4P2R_5%

2 3
1 4

56_0404_4P2R_5%

1 2

5

1

2

C156

2.2U_0603_6.3V6K

1

2

0.1U_0402_16V4Z

DDR_B_V

DDR_B_V

1

2

0.1U_0402_16V4Z

C177

C138

1

1

2

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

2

C170

14
23

14
23

14
23

14
23

14
23

14
23

14
23

2

C171

DDR_B_MA12
DDR_B_MA9

DDR_B_MA14
DDR_B_MA11

DDR_B_MA5
DDR_B_MA8

DDR_B_MA7
DDR_B_MA6

DDR_B_MA4
DDR_B_MA2

DDR_B_MA13
M_ODT2

DDR_B_BS#2
DDR_CKE2_DIMMB

C157

RP24 56_0404_4P2R_5%

RP26 56_0404_4P2R_5%

RP19 56_0404_4P2R_5%

RP21 56_0404_4P2R_5%

RP20 56_0404_4P2R_5%

RP4 56_0404_4P2R_5%

RP25

56_0404_4P2R_5%

C109

0.1U_0402_16V4Z

0.1U_0402_16V4Z
C132

1

2

0.1U_0402_16V4Z

1

1

2

2

C136

C111

0.1U_0402_16V4Z
C133

1

2

0.1U_0402_16V4Z

1

2

C158

Layout Note:
Place these resistor
closely JP42,all
trace length Max=1.5"

4

0.1U_0402_16V4Z

330U 2.5V Y D2

1

C155

C189

1

+

2

0.1U_0402_16V4Z

1

2

C137

@

2

DDR_CKE2_DIMMB7

DDR_B_BS#28

DDR_B_BS#08

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

2

2

C172

C159

DDR_B_WE#8

DDR_B_CAS#8

DDR_CS3_DIMMB#7

M_ODT37

ICH_SM_DA13,16,19,24

ICH_SM_CLK13,16,19,24

0.1U_0402_16V4Z

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

+1.8V

JDIM1

1

VREF

3

DDR_B_D0
DDR_B_D1

DDR_B_DQS#0
DDR_B_DQS0

DDR_B_D2
DDR_B_D3

DDR_B_D8
DDR_B_D9

DDR_B_DQS#1
DDR_B_DQS1

DDR_B_D10
DDR_B_D11

DDR_B_D17
DDR_B_D20

DDR_B_DQS#2
DDR_B_DQS2

DDR_B_D18
DDR_B_D19

DDR_B_D28
DDR_B_D25

DDR_B_DM3

DDR_B_D30
DDR_B_D31

DDR_CKE2_DIMMB

DDR_B_BS#2
DDR_B_MA12

DDR_B_MA9
DDR_B_MA8

DDR_B_MA5
DDR_B_MA3
DDR_B_MA1

DDR_B_MA10
DDR_B_BS#0
DDR_B_WE#

DDR_B_CAS#
DDR_CS3_DIMMB#

M_ODT3
DDR_B_D32

DDR_B_D33
DDR_B_DQS#4

DDR_B_DQS4
DDR_B_D34

DDR_B_D35
DDR_B_D40

DDR_B_D41
DDR_B_DM5
DDR_B_D42

DDR_B_D43
DDR_B_D48

DDR_B_D49

DDR_B_DQS#6
DDR_B_DQS6

DDR_B_D51
DDR_B_D50

DDR_B_D56
DDR_B_D61

DDR_B_DM7
DDR_B_D59

DDR_B_D58
ICH_SM_DA

ICH_SM_CLK

+3VS

C61

1

2

1

C60

2.2U_0603_6.3V6K

2

2007/1/15 2008/1/15

3

VSS

5

DQ0

7

DQ1

9

VSS

11

DQS0#

13

DQS0

15

VSS

17

DQ2

19

DQ3

21

VSS

23

DQ8

25

DQ9

27

VSS

29

DQS1#

31

DQS1

33

VSS

35

DQ10

37

DQ11

39

VSS

41

VSS

43

DQ16

45

DQ17

47

VSS

49

DQS2#

51

DQS2

53

VSS

55

DQ18

57

DQ19

59

VSS

61

DQ24

63

DQ25

65

VSS

67

DM3

69

NC

71

VSS

73

DQ26

75

DQ27

77

VSS

79

CKE0

81

VDD

83

NC

85

BA2

87

VDD

89

A12

91

A9

93

A8

95

VDD

97

A5

99

A3

101

A1

103

VDD

105

A10/AP

107

BA0

109

WE#

111

VDD

113

CAS#

115

NC/S1#

117

VDD

119

NC/ODT1

121

VSS

123

DQ32

125

DQ33

127

VSS

129

DQS4#

131

DQS4

133

VSS

135

DQ34

137

DQ35

139

VSS

141

DQ40

143

DQ41

145

VSS

147

DM5

149

VSS

151

DQ42

153

DQ43

155

VSS

157

DQ48

159

DQ49

161

VSS

163

NC,TEST

165

VSS

167

DQS6#

169

DQS6

171

VSS

173

DQ50

175

DQ51

177

VSS

179

DQ56

181

DQ57

183

VSS

185

DM7

187

VSS

189

DQ58

191

DQ59

193

VSS

195

SDA

197

SCL

199

VDDSPD

FOX_AS0A426-NARN-7F~N

SO-DIMM B
REVERSE

Bottom side

Compal Secret Data

Deciphered Date

VSS
DQ4
DQ5
VSS
DM0
VSS
DQ6
DQ7

VSS
DQ12
DQ13

VSS

DM1

VSS

CK0

CK0#

VSS
DQ14
DQ15

VSS

VSS
DQ20
DQ21

VSS

DM2

VSS
DQ22
DQ23

VSS
DQ28
DQ29

VSS

DQS3#

DQS3

VSS
DQ30
DQ31

VSS

NC/CKE1

VDD

NC/A15
NC/A14

VDD

VDD

VDD

BA1

RAS#

VDD
ODT0

NC/A13

VDD

VSS
DQ36
DQ37

VSS

DM4

VSS
DQ38
DQ39

VSS
DQ44
DQ45

VSS

DQS5#

DQS5

VSS
DQ46
DQ47

VSS
DQ52
DQ53

VSS

CK1

CK1#

VSS

DM6

VSS
DQ54
DQ55

VSS
DQ60
DQ61

VSS

DQS7#

DQS7

VSS
DQ62
DQ63

VSS

SAO

SA1

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

42
44
46
48
50

NC

52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90

A11

92

A7

94

A6

96
98

A4

100

A2

102

A0

104
106
108
110

S0#

112
114
116
118
120

NC

122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200

2

+DDR_MCH_REF1

DDR_B_D5
DDR_B_D4

DDR_B_DM0
DDR_B_D6

DDR_B_D7
DDR_B_D12

DDR_B_D13
DDR_B_DM1
M_CLK_DDR2

M_CLK_DDR#2
DDR_B_D14

DDR_B_D15

DDR_B_D21
DDR_B_D16

DDR_B_DM2
DDR_B_D22

DDR_B_D23
DDR_B_D26

DDR_B_D24
DDR_B_DQS#3

DDR_B_DQS3
DDR_B_D29

DDR_B_D27
DDR_CKE3_DIMMB

DDR_B_MA14
DDR_B_MA11

DDR_B_MA7
DDR_B_MA6

DDR_B_MA4
DDR_B_MA2
DDR_B_MA0

DDR_B_BS#1
DDR_B_RAS#
DDR_CS2_DIMMB#

M_ODT2
DDR_B_MA13

DDR_B_D36
DDR_B_D37

DDR_B_DM4
DDR_B_D39

DDR_B_D38
DDR_B_D44

DDR_B_D45
DDR_B_DQS#5

DDR_B_DQS5
DDR_B_D46

DDR_B_D47
DDR_B_D52

DDR_B_D53
M_CLK_DDR3

M_CLK_DDR#3
DDR_B_DM6
DDR_B_D54

DDR_B_D55
DDR_B_D60

DDR_B_D57
DDR_B_DQS#7

DDR_B_DQS7
DDR_B_D62

DDR_B_D63

10K_0402_5%

2

1

Close to VREF pins of SO-DIMM

2.2U_0805_16V4Z

0.1U_0402_16V4Z

1

1

C221

C222

2

2

M_CLK_DDR2 7
M_CLK_DDR#2 7

PM_EXTTS#1 7

DDR_CKE3_DIMMB 7

DDR_B_MA14 7

DDR_B_BS#1 8
DDR_B_RAS# 8
DDR_CS2_DIMMB# 7

M_ODT2 7

M_CLK_DDR3 7
M_CLK_DDR#3 7

R33

1 2

12

10K_0402_5%

R34

Title

Size Document Number Rev

Custom

Date: Sheet

+3VS

Compal Electronics, Inc.

DDR2 SO-DIMM II

LA-4231P

+DDR_MCH_REF1 13

1

0.1

of

14 49Thursday, January 10, 2008

A

C R T

C R T

VGA@

VGA_CRT_R34

VGA_CRT_G34

VGA_CRT_B34

1 1

CRT_R9

CRT_G9

CRT_B9

CRT_HSYNC9

VGA_HSYNC34

VGA_VSYNC34

2 2

CRT_VSYNC9

12

R613 0_0402_5%

VGA@

12

R614 0_0402_5%

VGA@

12

R615 0_0402_5%

UMA@

12

R619 0_0402_5%

UMA@

12

R620 0_0402_5%

UMA@

12

R621 0_0402_5%

C18 0.1U_0402_16V4Z

CRT_HSYNC CRT_HSYNC_B

1 2

R336 30_0402_5%

R631 0_0402_5%

R632 0_0402_5%

1 2

R337 30_0402_5%

R2

1 2

UMA@

VGA@

VGA@

UMA@

12

R7

150_0402_1%

12

12

CRT_VSYNC_BCRT_VSYNC

12

R8

150_0402_1%

Close to GMCH Close to VGA

MSEN#29

CRT_R_C

CRT_G_C

CRT_B_C

1

12

@

C8

C9

2

150_0402_1%

22P_0402_50V8J

+CRT_VCC

5

1

P

4

OE#

A2Y

G

U5

74AHCT1G125GW_SOT353-5

3

1 2

C17 0.1U_0402_16V4Z

1

@

2

22P_0402_50V8J

@

C6

22P_0402_50V8J

+CRT_VCC

1 2

L2

BK1608LL121-T 0603

1 2

L3

BK1608LL121-T 0603

1 2

L4

BK1608LL121-T 0603

1

For EMI

2

R319 10K_0402_5%

D_CRT_HSYNC

5

1

P

4

OE#

A2Y

G

U6
74AHCT1G125GW_SOT353-5

3

CRT_R_L

CRT_G_L

CRT_B_L

4.7P_0402_50V8C

12

D_CRT_VSYNC

B

1

1

C1

C2

2

4.7P_0402_50V8C

L25 0_0603_5%

L24 0_0603_5%

2

1 2

1 2

1

C3

2

4.7P_0402_50V8C

CRT_GND

HSYNC_L

VSYNC_L

1

C348

2

15P_0402_50V8J

+5VS

F7

1.1A_6VDC_FUSE

1

C347

2

15P_0402_50V8J

C345

1

C349

2

W=40mils

D17

21

2 1

RB411DT146 SOT23

0.1U_0402_16V4Z

DDC_MD2

1

2

100P_0402_50V8J

C7

100P_0402_50V8J

C

C344

1

2

100P_0402_50V8J

C4

W=40mils

1

2

VGA_DDC_DATA_C

VGA_DDC_CLK_C

1

2

100P_0402_50V8J

CRT_GND

CRT_GND

+CRT_VCC

1

2

C346

@

0.1U_0402_16V4Z
JCRT1

6

11

1
7

12

2
8

13

3
9

14

4
10
15

5

SUYIN_070549FR015S208CR

CONN@

R6
0_0805_5%

12

R314
0_0805_5%

12

D

原本為

4.7K

R12

R9

16
17

VGA_DDC_DATA_C

VGA_DDC_CLK_C

1 2

2K_0402_5%

BSS138_NL_SOT23

1 2

2K_0402_5%

R14

R13

1 2

2.2K_0402_5%

2

G

1 3

D

S

1 3

D

Q1

BSS138_NL_SOT23

2

1 2

2.2K_0402_5%

G

S

+3VS+CRT_VCC +3VS+CRT_VCC +3VS

原本為

R10

1 2

2.2K_0402_5%

R628 0_0402_5%

R629 0_0402_5%

R624 0_0402_5%

R625 0_0402_5%

E

UMA@

UMA@

VGA@

VGA@

10K

3VDDCDA9

12

3VDDCCL9

12

VGA_DDCDATA34

Q3

12

12

VGA_DDCCLK34

LVDSAC+

D

LVDSAC­LVDSA0+

LVDSA0­LVDSA1+

LVDSA1­LVDSA2+

LVDSA2-

EDID_CLK_LCD
EDID_DAT_LCD

L C D

R655

0_0402_5%UMA@

R651

0_0402_5%VGA@

MIC_DIAG
+3VS
MIC_SIG
MIC_CLK

1 2

1 2

EC_ENBKL

BKOFF#

12

12

1
3
5
7

9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39

C195
220P_0402_50V7K

EC_ENBKL

R652

2.2K_0402_5%

VGA@

JP4

2

1

2

4

3

4

6

5

6

8

7

8

10

9

10

12

11

12

14

13

14

16

15

16

18

17

18

20

19

20

22

21

22

24

23

24

26

25

26

28

27

28

30

29

30

32

31

32

34

33

34

36

35

36

38

37

38

40

39

40

42

GND41GND

ACES_88242-4001~N

D26
CH751H-40_SC76

D25
CH751H-40_SC76@

R652

100K_0402_5%

UMA@

LCD_TSTLCD_CBL_DET#

LVDSAC+
LVDSAC-

LVDSA0+
LVDSA0-

LVDSA1+
LVDSA1-

LVDSA2+
LVDSA2-

DISPOFF#

DAC_BRIG

INVT_PWM

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

BKOFF#29

+LCDVDD

MIC_DIAG29

MIC_SIG25

MIC_CLK25

+5VS
USB20_N819
USB20_P819

220P_0402_50V7K

+3VS

+3VS

EC_ENBKL29

C251

EDID_CLK_LCD
EDID_DAT_LCD

+3VS

1

C372

0.1U_0402_16V7K~N

2

GMCH_LVDDEN9

LCD_VCC_TEST_EN

9

3 3

4 4

GMCH_LVDDEN

CH751H-40PT_SOD323-2 UMA@

VGA_LVDDEN

CH751H-40PT_SOD323-2 VGA@

LCD_VCC_TEST_EN

BIA_PWM9

2 1

2 1

BIA_PWM

A

D9

D8

R662

0_0402_5%

R20 10_0402_5%@

12

R15
10K_0402_5%

12

12

INVT_PWM

1

2

U53

IN6OUT
EN3NC

5

GND

GND

AOZ1320CI-04_SOT23-6

C36

1U_0603_10V4Z@

1
4
2

W=60milsW=60mils

1

2

+LCDVDD

+LCDVDD

1

C369

C363

2

0.1U_0402_16V7K~N

4.7U_0805_6.3V6K~N

+3VS

1

C38

0.1U_0402_16V4Z@

2

B

GMCH_ENBKL9

G7X_ENBKL34VGA_LVDDEN34

21

21

INVPWR_B+

0.1U_0603_50V4Z

Issued Date

+3VS

LCD_TST 29LCD_CBL_DET#29

C32

12

R21

4.7K_0402_5%

DISPOFF#

DAC_BRIG 29
INVT_PWM 29

2

1

1 2

L5 FBMA-L11-201209-221LMA30T_0805

2

C34

0.1U_0603_50V4Z

1

2007/1/15 2008/1/15

B+

Compal Secret Data

Deciphered Date

R508 0_0402_5%UMA@

1 2

R510 0_0402_5%UMA@

1 2

R544 0_0402_5%UMA@

1 2

R570 0_0402_5%UMA@

1 2

R595 0_0402_5%UMA@

1 2

R596 0_0402_5%UMA@

1 2

R597 0_0402_5%UMA@

1 2

R598 0_0402_5%UMA@

1 2

R599 0_0402_5%UMA@

1 2

R600 0_0402_5%UMA@

1 2

VGA_LVDSAC+35
VGA_LVDSAC-35

VGA_LVDSA0+35
VGA_LVDSA0-35

VGA_LVDSA1+35
VGA_LVDSA1-35

VGA_LVDSA2+35
VGA_LVDSA2-35

VGA_CLK_LCD34
VGA_DAT_LCD34

VGA_LVDSAC+
VGA_LVDSAC-

VGA_LVDSA0+
VGA_LVDSA0-

VGA_LVDSA1+
VGA_LVDSA1-

VGA_LVDSA2+
VGA_LVDSA2-

VGA_CLK_LCD
VGA_DAT_LCD

Title

Size Document Number Rev

Custom

Date: Sheet

GMCH_LVDSAC+
GMCH_LVDSAC-

GMCH_LVDSA0+
GMCH_LVDSA0-

GMCH_LVDSA1+
GMCH_LVDSA1-

GMCH_LVDSA2+
GMCH_LVDSA2-

GMCH_EDID_CLK_LCD
GMCH_EDID_DAT_LCD

R630 0_0402_5% VGA@

1 2

R633 0_0402_5% VGA@

1 2

R634 0_0402_5% VGA@

1 2

R635 0_0402_5% VGA@

1 2

R601 0_0402_5% VGA@

1 2

R602 0_0402_5% VGA@

1 2

R603 0_0402_5% VGA@

1 2

R604 0_0402_5% VGA@

1 2

R644 0_0402_5% VGA@

1 2

R645 0_0402_5% VGA@

1 2

Compal Electronics, Inc.

CRT CONN/LCD CONN

LA-4231P

E

GMCH_LVDSAC+ 9
GMCH_LVDSAC- 9

GMCH_LVDSA0+ 9
GMCH_LVDSA0- 9

GMCH_LVDSA1+ 9
GMCH_LVDSA1- 9

GMCH_LVDSA2+ 9
GMCH_LVDSA2- 9

GMCH_EDID_CLK_LCD 9
GMCH_EDID_DAT_LCD 9

LVDSAC+
LVDSAC-

LVDSA0+
LVDSA0-

LVDSA1+
LVDSA1-

LVDSA2+
LVDSA2-

EDID_CLK_LCD
EDID_DAT_LCD

15 49Thursday, January 10, 2008

of

0.1

5

PCI

SRC

CPU

CLKSEL1

1

1

FSLA

CLKSEL0

MHz

200

166

MHz

1000

100

MHz

33.30

33.3

1 2

+3VS

R397 0_1206_5%

FSLC1FSLB

CLKSEL2

0

FSB Frequency Selet:

D D

CPU Driven

(Default)

*

Stuff

No Stuff

Stuff

667MHz

No Stuff

Stuff

800MHz

CPU_BSEL05

C C

CPU_BSEL15

CPU_BSEL25

B B

A A

18P_0402_50V8J~N

FSC

14.31818MHZ_16P

2

C265

1

No Stuff

2.2K_0402_5%

FSA

0_0402_5%

FSB

@

0_0402_5%

10K_0402_5%

@

0_0402_5%

Y3

R402

1 2

R410

1 2

R378

R200

1 2

R184

Routing the trace at least 10mil

R1107 R1135 R1083

R1074 R1086 R1098 R1113 R1139

R1139 R1135R1135 R1139

R1083

R1107

R1128

R1098

R1113

R1135 R1139

R1083

R1086
R1107

R1098
R1113

MCH_CLKSEL0 7

MCH_CLKSEL1 7

MCH_CLKSEL2 7

R1074

12

1 2

R411

+VCCP

12

1K_0402_5%

R379
1K_0402_5%

1 2

1 2

R377

1K_0402_5%

1 2

R185

1K_0402_5%

12

R199

0_0402_5%

For ITP_EN, 0 =SRC8/SRC8#; 1 = ITP/ITP#
For 27_SEL, 0 = Enable DOT96 & SRC1,

For PCI2_EN, 0 = Overclocking of CPU and SRC Allowed

CLK_XTAL_OUT

CLK_XTAL_IN

Placed
within 500

12

mils of
CK505M

2

C257
18P_0402_50V8J~N

1

5

1 2

R1128

R1074R1086

R1128

CLKSATAREQ#19

CLKMCHREQ#7
CLK_PCI_CB40

CLK_PCI_TPM29

CLK_DEBUG_PORT24

CLK_PCI_EC29
CLK_PCI_ICH17

CLK_48M_ICH19

CLK_14M_ICH19

1 = Enable SRC0 & 27MHz

1 = Overclocking of CPU and SRC NOT allowed

+3VM_CK505

ITP_EN

R240
10K_0402_5%

+3VM_CK505

R492
10K_0402_5%

VGA@

1 2

27_SEL

R268
10K_0402_5%

UMA@

1 2

4

1

C479
10U_0805_10V4Z~N

2

+3VS
+3VS

4

1

2

1 2
1 2
1 2
1 2
1 2
1 2

1 2

1 2

+3VM_CK505

1 2

PCI2_TME

1 2

C480

0.1U_0402_16V4Z~N

+1.25VM_CK505

12

R23510K_0402_5%

12

R23410K_0402_5%

R237475_0402_1%
R233475_0402_1%
R25733_0402_5%

R23912_0402_5%

12

R25812_0402_5%
R25933_0402_5%
R26033_0402_5%

R40133_0402_5%

R20133_0402_1%

+1.25VM_CK505

R236
10K_0402_5%

R238
10K_0402_5%

@

1

C478

0.1U_0402_16V4Z~N

2

+1.25VS

+3VM_CK505

SATA_REQ
MCH_REQ
PCI2_TME
PCI_CLK3
27_SEL
ITP_EN

CLK_XTAL_IN
CLK_XTAL_OUT

FSA

FSB

FSC

3

1

C476

0.1U_0402_16V4Z~N

2

1

C464

0.1U_0402_16V4Z~N

2

1

C463

0.1U_0402_16V4Z~N

2

1

C460

0.1U_0402_16V4Z~N

2

Place close to U7

R261 0_1206_5%

1 2

C459
22U_0805_6.3V4Z

U7

2

VDDPCI

9

VDD48

16

VDDPLL3

61

VDDREF

39

VDDSRC

55

VDDCPU

12

VDD96_IO

20

VDDPLL3_IO

26

VDDSRC_IO

36

VDDSRC_IO

49

VDDCPU_IO

1

PCI0/CR#_A

3

PCI1/CR#_B

4

PCI2/TME

5

PCI3

6

PCI4/27_Select

7

PCI_F5/ITP_EN

60

X1

59

X2

10

USB_48MHZ/FSLA

57

FSLB/TEST_MODE

62

REF0/FSLC/TEST_SEL

45

VDDSRC_IO

42

GNDSRC

8

GNDPCI

11

GND48

15

GND

19

GND

52

GNDCPU

23

GNDSRC

29

GNDSRC

58

GNDREF

ICS9LPRS365BGLFT_TSSOP64

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

0.1U_0402_16V4Z~N

1

C462

2

SRC1/SE1/27MHz_NonSS

3

1

2

SRC8/CPU2_ITP

SRC8#/CPU2_ITP#

SRC11#/CR#_G

SRC1#/SE2/27MHz_SS

SRC0#/DOT96#

CK_PWRGD/PD#

2007/1/15 2008/1/15

1

C461

2

0.1U_0402_16V4Z~N

NC

SCLK

SDATA

PCI_STOP#

CPU_STOP#

CPU0

CPU0#

CPU1_F

CPU1#_F

SRC10

SRC10#

SRC11/CR#_H

SRC9

SRC9#

SRC7/CR#_F

SRC7#/CR#_E

SRC6

SRC6#

SRC4

SRC4#

SRC3/CR#_C

SRC3#/CR#_D

SRC2/SATA

SRC2#/SATA#

SRC0/DOT96

22U_0805_6.3V4Z

1

C474

2

48

64
63

38
37

R_CPU_BCLK

54

R_CPU_BCLK#

53

R_MCH_BCLK

51

R_MCH_BCLK#

50

R_PCIE_LAN

47

R_PCIE_LAN#

46

R_PCIE_EXPR

34

R_PCIE_EXPR#

35

R_CLKREQ#_H

33

R_CLKREQ#_G

32

R_CLK_PCIE_MCard

30

R_CLK_PCIE_MCard#

31

R_CLKREQ#_F

44

R_CLKREQ#_E

43

R_CLK_Rob

41

R_CLK_Rob#

40

R_MCH_3GPLL

27

R_MCH_3GPLL#

28

R_PCIE_ICH

24

R_PCIE_ICH#

25

R_PCIE_SATA

21

R_PCIE_SATA#

22

SSCDREFCLK

17

SSCDREFCLK#

18

R_MCH_DREFCLK

13

R_MCH_DREFCLK#

14

56

Compal Secret Data

0.1U_0402_16V4Z~N

1

C477

2

0.1U_0402_16V4Z~N

R202

R203
R204

R205
R208

R209
R213

R212
R396

R375
R251

R252
R398

R386

R210

R211

R247

R248

R243

R244
R241

R242
R344 0_0402_5%VGA@
R493 0_0402_5%VGA@

R376 0_0402_5%@

Deciphered Date

1

2

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2

2

+1.25VM_CK505

C475

0.1U_0402_16V4Z~N

0_0402_5%
0_0402_5%

0_0402_5%
0_0402_5%

0_0402_5%
0_0402_5%

0_0402_5%
0_0402_5%

1 2

R374 10K_0402_5%
475_0402_1%

12

475_0402_1%

12

1 2

R395 10K_0402_5%
0_0402_5%
0_0402_5%

1 2

R385 10K_0402_5%
475_0402_1%

12

475_0402_1%

12

1 2

R399 10K_0402_5%
0_0402_5%

0_0402_5%

0_0402_5%
0_0402_5%

0_0402_5%UMA@
0_0402_5%UMA@

0_0402_5%UMA@
0_0402_5%UMA@

2

1

C473

2

1

ICH_SM_CLK 13,14,19,24
ICH_SM_DA 13,14,19,24

H_STP_PCI# 19
H_STP_CPU# 19

CLK_CPU_BCLK 4
CLK_CPU_BCLK# 4

CLK_MCH_BCLK 7
CLK_MCH_BCLK# 7

CLK_PCIE_LAN 22
CLK_PCIE_LAN# 22

CLK_PCIE_EXPR 28
CLK_PCIE_EXPR# 28

+3VS

EXPR_CARD_REQ# 28
MCARD_REQ#G 24

+3VS

CLK_PCIE_MCARD 24
CLK_PCIE_MCARD# 24

+3VS

MCARD_REQ#F 22
MCARD_REQ#E 24

+3VS

CLK_PCIE_Rob 24
CLK_PCIE_Rob# 24

CLK_MCH_3GPLL 7
CLK_MCH_3GPLL# 7

CLK_PCIE_ICH 19
CLK_PCIE_ICH# 19

CLK_PCIE_SATA 18
CLK_PCIE_SATA# 18

MCH_SSCDREFCLK 7
MCH_SSCDREFCLK# 7

CLK_MCH_DREFCLK 7
CLK_MCH_DREFCLK# 7

CLK_PCIE_VGA 34
CLK_PCIE_VGA# 34

CK_PWRGD 19
CLK_EN# 49

Title

Clock generator

Size Document Number Rev

Custom

LA-4231P

Date: Sheet

Compal Electronics, Inc.

1

0.1

of

16 49Thursday, January 10, 2008

5

+3VS

1 2

R190 8.2K_0402_5%

1 2
1 2
1 2
1 2
1 2
1 2
1 2

1 2
1 2
1 2
1 2
1 2
1 2
1 2

1 2
1 2
1 2
1 2

12

R191 8.2K_0402_5%

D D

C C

R221 8.2K_0402_5%
R192 8.2K_0402_5%
R218 8.2K_0402_5%
R220 8.2K_0402_5%
R166 8.2K_0402_5%
R219 8.2K_0402_5%

+3VS

R165 8.2K_0402_5%
R217 8.2K_0402_5%
R216 8.2K_0402_5%
R389 8.2K_0402_5%
R164 8.2K_0402_5%
R167 8.2K_0402_5%
R168 8.2K_0402_5%
R214 8.2K_0402_5%

R215 8.2K_0402_5%
R178 8.2K_0402_5%
R193 8.2K_0402_5%
R388 8.2K_0402_5%

PCI_DEVSEL#
PCI_STOP#
PCI_TRDY#
PCI_FRAME#
PCI_PLOCK#
PCI_IRDY#
PCI_SERR#
PCI_PERR#

PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#
PCI_PIRQE#
PCI_PIRQF#
PCI_PIRQG#
PCI_PIRQH#

PCI_REQ0#
PCI_REQ1#
PCI_REQ2#
PCI_REQ3#

PCI_AD[0..31]40

4

PCI_AD0
PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD6
PCI_AD7
PCI_AD8
PCI_AD9
PCI_AD10
PCI_AD11
PCI_AD12
PCI_AD13
PCI_AD14
PCI_AD15
PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20
PCI_AD21
PCI_AD22
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30
PCI_AD31

PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#

U8B

D20

AD0

E19
D19
A20
D17
A21
A19
C19
A18
B16
A12
E16
A14
G16
A15

B6

C11

A9
D11
B12
C12
D10

C7
F13
E11
E13
E12

D8

A6
E8

D6

A3

F9
B5

C5
A10

PCI

AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31

Interrupt I/F

PIRQA#
PIRQB#
PIRQC#
PIRQD#

ICH8M REV 1.0

REQ0#

GNT0#
REQ1#/GPIO50
GNT1#/GPIO51
REQ2#/GPIO52
GNT2#/GPIO53
REQ3#/GPIO54
GNT3#/GPIO55

C/BE0#

C/BE1#

C/BE2#

C/BE3#

IRDY#

PAR

PCIRST#

DEVSEL#

PERR#

PLOCK#

SERR#

STOP#

TRDY#

FRAME#

PLTRST#

PCICLK

PME#

PIRQE#/GPIO2

PIRQF#/GPIO3
PIRQG#/GPIO4
PIRQH#/GPIO5

3

PCI_REQ0#

A4
D7
E18
C18
B19
F18
A11
C10

C17
E15
F16
E17

C8
D9
G6
D16
A7
B7
F10
C16
C9
A17

AG24
B10
G7

F8
G11
F12
B3

PCI_GNT0#
PCI_REQ1#

PCI_REQ2#
PCI_REQ3#

PCI_GNT3#
PCI_CBE#0

PCI_CBE#1
PCI_CBE#2
PCI_CBE#3

PCI_IRDY#
PCI_PAR
PCI_PCIRST#
PCI_DEVSEL#
PCI_PERR#
PCI_PLOCK#
PCI_SERR#
PCI_STOP#
PCI_TRDY#
PCI_FRAME#

PCI_PLTRST#
CLK_PCI_ICH
EC_PME#

PCI_PIRQE#
PCI_PIRQF#
PCI_PIRQG#
PCI_PIRQH#

PCI_REQ0# 40
PCI_GNT0# 40

PCI_CBE#0 40
PCI_CBE#1 40
PCI_CBE#2 40
PCI_CBE#3 40

PCI_IRDY# 40
PCI_PAR 40

PCI_DEVSEL# 40
PCI_PERR#

PCI_SERR#
PCI_STOP# 40
PCI_TRDY# 40
PCI_FRAME# 40

CLK_PCI_ICH 16
EC_PME# 29

PCI_PIRQF#
PCI_PIRQG# 40

2

1

PCI_GNT3#

12

R189

@

1K_0402_5%

B B

A16 swap override Strap

PCI_GNT3#

A A

Low= A16 swap override Enble
High= Default

Place closely pin B10

CLK_PCI_ICH

R390

10_0402_5% @

C470

8.2P_0402_50V@

5

*

1 2
1

2

Check if use LPC?

Boot BIOS Strap

PCI_GNT0# SPI_CS#1

0

1

1

12

R188

@

1K_0402_5%

4

R187
0_0402_5%

R122
0_0402_5%

+3VALW

5

U9

@

2

P

B

4

Y

1

A

G

MC74VHC1G08DFT2G SC70 5P

3

12

+3VALW

5

U10

@

2

P

B

4

Y

1

A

G

MC74VHC1G08DFT2G SC70 5P

3

12

PCI_RST#

PLT_RST#

Title

Size Document Number Rev

Custom

Date: Sheet

12

12

Compal Electronics, Inc.

ICH8(1/4)-PCI/INT

LA-4231P

PCI_RST# 21,40

R186
100K_0402_5%

PLT_RST# 7,19,22,24,28,29,34

R112
100K_0402_5%

of

17 49Thursday, January 10, 2008

1

0.1

Boot BIOS Location

1

0

1

SPI

PCI

LPC

*

SPI_CS1#_R19

SPI_CS1#_RPCI_GNT0#

12

R179

@

1K_0402_5%

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2007/1/15 2008/1/15

Compal Secret Data

PCI_PCIRST#

PCI_PLTRST#

Deciphered Date

2

5

+RTCVCC

D D

R139 330K_0402_1%

LAN100_SLP

1 2

R140 1M_0402_5%

SM_INTRUDER#

1 2

R141 330K_0402_1%

ICH_INTVRMEN

1 2

R341

1 2

10M_0402_5%

1

C415

10P_0402_50V8J~N

C C

PSATA_ITX_DRX_N021

PSATA_ITX_DRX_P021

2

1

IN

2

ICH_RTCX1
ICH_RTCX2

1

C419
10P_0402_50V8J~N

2

4

Y2

32.768KHZ_12.5PF_1TJS125BJ4A421P

OUT

NC3NC

+3VS

PSATA_ITX_DRX_N0

PSATA_ITX_DRX_P0

+RTCVCC

PSATA_ITX_DRX_N0_C

1 2

C193 3900P_0402_50V7K

C192 3900P_0402_50V7K

1 2

PSATA_ITX_DRX_P0_C

R124

1 2

20K_0402_5%

1U_0603_10V6K

SATA_LED#

R13510K_0402_5%

12

close ICH8

@

ODD_ITX_DRX_N0

B B

ODD_ITX_DRX_P0

ODD_ITX_DRX_N0

ODD_ITX_DRX_P0

1 2

C323 3900P_0402_50V7K

1 2

C325 3900P_0402_50V7K

@

ODD_ITX_DRX_N0_C

ODD_ITX_DRX_P0_C

close ICH8

ADC_ACZ_SDIN025

C188

4

ICH_RTCX1
ICH_RTCX2

ICH_RTCRST#
SM_INTRUDER#

HDA_BITCLK_R
HDA_SYNC_R

HDA_RST_R#
ADC_ACZ_SDIN0

HDA_SDOUT_R

SATA_LED#
PSATA_IRX_DTX_N0_C

PSATA_IRX_DTX_P0_C
PSATA_ITX_DRX_N0_C
PSATA_ITX_DRX_P0_C

ODD_IRX_DTX_N0_C
ODD_IRX_DTX_P0_C
ODD_ITX_DRX_N0_C
ODD_ITX_DRX_P0_C

CLK_PCIE_SATA#
CLK_PCIE_SATA

R358

1 2

24.9_0402_1%

Within 500 mils

ICH_INTVRMEN
LAN100_SLP

GLAN_COMP

1

JOPEN1

@

1 2

2

R181 24.9_0402_1%

R346 33_0402_5%
R353 33_0402_5%

R110 33_0402_5%

R356 33_0402_5%

PSATA_IRX_DTX_N0_C21
PSATA_IRX_DTX_P0_C21

ODD_IRX_DTX_N0_C21
ODD_IRX_DTX_P0_C21

CLK_PCIE_SATA#16
CLK_PCIE_SATA16

1 2

SATA_LED#31

1 2
1 2

1 2

1 2

T19PAD

+1.5VS

ACZ_BITCLK25

ACZ_SYNC25
ACZ_RST#25

ACZ_SDOUT25

3

U8A

AG25

RTCX1

AF24

RTCX2

AF23

RTCRST#

AD22

INTRUDER#

AF25

INTVRMEN

AD21

LAN100_SLP

B24

GLAN_CLK

D22

LAN_RSTSYNC

C21

LAN_RXD0

B21

LAN_RXD1

C22

LAN_RXD2

D21

LAN_TXD0

E20

LAN_TXD1

C20

LAN_TXD2

AH21

GLAN_DOCK#/GPIO13

D25

GLAN_COMPI

C25

GLAN_COMPO

AJ16

HDA_BIT_CLK

AJ15

HDA_SYNC

AE14

HDA_RST#

AJ17

HDA_SDIN0

AH17

HDA_SDIN1

AH15

HDA_SDIN2

AD13

HDA_SDIN3

AE13

HDA_SDOUT

AE10

HDA_DOCK_EN#/GPIO33

AG14

HDA_DOCK_RST#/GPIO34

AF10

SATALED#

AF6

SATA0RXN

AF5

SATA0RXP

AH5

SATA0TXN

AH6

SATA0TXP

AG3

SATA1RXN

AG4

SATA1RXP

AJ4

SATA1TXN

AJ3

SATA1TXP

AF2

SATA2RXN

AF1

SATA2RXP

AE4

SATA2TXN

AE3

SATA2TXP

AB7

SATA_CLKN

AC6

SATA_CLKP

AG1

SATARBIAS#

AG2

SATARBIAS

ICH8M REV 1.0

FWH0/LAD0
FWH1/LAD1
FWH2/LAD2
FWH3/LAD3

FWH4/LFRAME#

LDRQ0#

LDRQ1#/GPIO23

RTCLAN / GLAN

LPCCPU

A20GATE

A20M#

DPRSTP#

DPSLP#

FERR#

CPUPWRGD/GPIO49

IGNNE#

RCIN#

STPCLK#

THRMTRIP#

IHDA

IDE

SATA

DCS1#
DCS3#

DIOR#

DIOW#

DDACK#

IDEIRQ

IORDY

DDREQ

INIT#

INTR

SMI#

DD10
DD11
DD12
DD13
DD14
DD15

NMI

TP8
DD0

DD1
DD2
DD3
DD4
DD5
DD6
DD7
DD8
DD9

DA0
DA1
DA2

E5
F5
G8
F6

C4
G9

E6
AF13

AG26
AF26

AE26
AD24
AG29
AF27
AE24

AC20
AH14

AD23
AG28

AA24
AE27
AA23
V1

U2
V3
T1
V4
T5
AB2
T6
T3
R2
T4
V6
V5
U1
V2
U6

AA4
AA1
AB3

Y6
Y5

W4
W3
Y2
Y3
Y1
W5

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3

LPC_FRAME#
LPC_DRQ0#

GATEA20
H_A20M#

H_FERR#
H_PWRGOOD
H_IGNNE#
H_INIT#

H_INTR
KB_RST#

H_NMI
H_SMI#

H_STPCLK#
THRMTRIP_ICH#

IDE_DD0
IDE_DD1
IDE_DD2
IDE_DD3
IDE_DD4
IDE_DD5
IDE_DD6
IDE_DD7
IDE_DD8
IDE_DD9
IDE_DD10
IDE_DD11
IDE_DD12
IDE_DD13
IDE_DD14
IDE_DD15

IDE_DA0
IDE_DA1
IDE_DA2

IDE_DCS1#
IDE_DCS3#

IDE_DIOR#
IDE_DIOW#

IDE_DDACK#

IDE_IRQ

IDE_DIORDY

IDE_DDREQ

2

LPC_AD[0..3] 24,29

LPC_FRAME# 24,29

T36 PAD
T35 PAD

GATEA20 29
H_A20M# 4

12

R129 0_0402_5%

H_DPSLP# 5

H_FERR# 4
H_PWRGOOD 5
H_IGNNE# 4
H_INIT# 4

H_INTR 4

KB_RST# 29

H_NMI 4
H_SMI# 4

H_STPCLK# 4
1 2

IDE_DA0 21
IDE_DA1 21
IDE_DA2 21

IDE_DCS1# 21
IDE_DCS3# 21

IDE_DIOR# 21
IDE_DIOW# 21

IDE_DDACK# 21
IDE_IRQ 21
IDE_DIORDY 21

IDE_DDREQ 21

H_DPRSTP#H_DPRSTP_R#

R130 24_0402_1%

IDE_DD[0..15] 21

GATEA20

KB_RST#

H_FERR#

H_DPRSTP# 5,7,49

+VCCP

12

R127

10K_0402_5%

R163

10K_0402_5%

R156

56_0402_5%

within 2" from R1557

R131
56_0402_5%

H_THERMTRIP# 4,7

placed within 2" from ICH8M

IDE_DIORDY

R145 4.7K_0402_5%

IDE_IRQ

1 2

R146 8.2K_0402_5%

1 2

1

+3VS

12

12

+VCCP

12

+3VS

XOR CHAIN ENTRANCE STRAP:RSVD

+3VS

R357

@

1K_0402_5%

ACZ_SDOUT

12

ICH_RSVD

R352

@

1K_0402_5%

12

ICH_RSVD 19

XOR Chain Entrance Strap

A A

00

0

1

11

DescriptionICH RSVD HDA SDOUT

RSVD

1

Enter XOR Chain

0

Normal Operation (Default)

Set PCIE port config bit 1

5

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2007/1/15 2008/1/15

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

Compal Electronics, Inc.

ICH8(2/4)_LAN,HD,IDE,LPC

LA-4231P

18 49Thursday, January 10, 2008

1

0.1

of

5

SERIRQ

+3VS

D D

+3VALW

+3VS

1 2

R148 10K_0402_5%

1 2

R348 8.2K_0402_5%

1 2

R149 8.2K_0402_5%@

1 2

R115 8.2K_0402_5%

R138 8.2K_0402_5%

1 2

R151 1K_0402_5%

1 2

R119 10K_0402_5%

1 2

R150 10K_0402_5%

1 2

R121 10K_0402_5%

1 2

R132 10K_0402_5%@

1 2

R134 10K_0402_5% @

low-->default

PCI_CLKRUN#

EC_THERM#

OCP#

ICH_LOW_BAT#

12

ICH_PCIE_WAKE#

ICH_RI#

XDP_DBRESET#

CL_RST#1

EC_LID_OUT# VGATE

SB_SPKR

R136

10K_0402_5%

+3VALW

1 2

R137
10K_0402_5%

1 2

VGATE7,29,49

High -->No boot

C C

+3VALW

B B

RP27

USB_OC#1

45

USB_OC#2

36

USB_OC#3

27

USB_OC#4

18

10K_1206_8P4R_5%

RP28

USB_OC#5

45

USB_OC#8

36

USB_OC#9

27

USB_OC#0

18

10K_1206_8P4R_5%

USB_OC#7

12

R118 10K_0402_5%

modify follow intel check list-1003

100K_0402_5%

1 2

R120

1 2

R117 499_0402_1%@

100K_0402_5%

1 2

R342

LAN_WOL_EN

DPRSLPVR

VRMPWRGD

Express Card

Robson

WLAN

GLAN

+3VS

12

A A

ICH_SM_DA13,14,16,24
ICH_SM_CLK13,14,16,24

5

12

2.2K_0402_5%

R1042.2K_0402_5%

R105

Q9
SSM3K7002FU_SC70-3

D

S

G

+5VS

13

S

2

G

ICH_SMB_DATA

D

ICH_SMB_CLK

13

Q10

2

SSM3K7002FU_SC70-3

ICH_SMB_CLK28
ICH_SMB_DATA28

PCIE_RXN228

PCIE_RXP228
PCIE_TXN228
PCIE_TXP228

PCIE_RXN324

PCIE_RXP324
PCIE_TXN324
PCIE_TXP324

PCIE_RXN424

PCIE_RXP424
PCIE_TXN424
PCIE_TXP424

GLAN_RXN22
GLAN_RXP22

GLAN_TXN22
GLAN_TXP22

4

R106

2.2K_0402_5%

XDP_DBRESET#4
PM_BMBUSY#7
EC_LID_OUT#29
H_STP_PCI#16

H_STP_CPU#16
PCI_CLKRUN#29,40

ICH_PCIE_WAKE#24,28
SERIRQ29
EC_THERM#4,29

OCP#4

EC_SMI#29

EC_SCI#29

CLKSATAREQ#16

SB_SPKR25

MCH_ICH_SYNC#7

ICH_RSVD18

4

+3VALW

12

12

R107

2.2K_0402_5%

T30PAD

1 2

R345 0_0402_5%

T45PAD

T17PAD
T18PAD

T20PAD

0.1U_0402_16V7K~N

0.1U_0402_16V7K~N

SPI_CS1#_R17

USB_OC#032
USB_OC#132
USB_OC#232
USB_OC#332

ICH_SMB_CLK
ICH_SMB_DATA
CL_RST#1
ME_SMB_CK
ME_SMB_DA

ICH_RI#

XDP_DBRESET#
PM_BMBUSY#
EC_LID_OUT#
H_STP_PCI#

H_STP_CPU#

ICH_PCIE_WAKE#
SERIRQ
EC_THERM#

VRMPWRGD

SST_CTL

OCP#

EC_SMI#
EC_SCI#

CLKSATAREQ#

SB_SPKR
MCH_ICH_SYNC#
ICH_RSVD

EC_SWI#29

AD19
AG21
AC17
AE19

AF17

AD15
AG12
AG22
AE20

AG18
AH11
AE17

AF12
AC13

AE16
AC19

AH12
AE11
AG10
AH25
AD16
AG13

AD10

C4350.1U_0402_16V7K~N

12

C4360.1U_0402_16V7K~N

12

C4370.1U_0402_16V7K~N

12

C4500.1U_0402_16V7K~N

12

C451

12

C452

12

C4550.1U_0402_16V7K~N

12

C4540.1U_0402_16V7K~N

12

3

+3VS

R347

8.2K_0402_5%

U8C

AJ26

SMBCLK
SMBDATA
LINKALERT#
SMLINK0
SMLINK1

RI#

F4

SUS_STAT#/LPCPD#
SYS_RESET#

BMBUSY#/GPIO0
SMBALERT#/GPIO11
STP_PCI#/GPIO15

STP_CPU#/GPIO25
CLKRUN#/GPIO32
WAKE#

SERIRQ
THRM#

AJ20

VRMPWRGD

AJ22

TP7

AJ8

TACH1/GPIO1

AJ9

TACH2/GPIO6

AH9

TACH3/GPIO7
GPIO8
GPIO12

AG8

TACH0/GPIO17
GPIO18
GPIO20
SCLOCK/GPIO22
QRT_STATE0/GPIO27
QRT_STATE1/GPIO28
SATACLKREQ#/GPIO35

AF9

SLOAD/GPIO38

AJ11

SDATAOUT0/GPIO39
SDATAOUT1/GPIO48

AD9

SPKR

AJ13

MCH_SYNC#

AJ21

TP3

ICH8M REV 1.0

U8D

P27

PERN1

P26

PERP1

N29

PETN1

N28

M27
M26

AJ19
AG16
AG15
AE15
AF15
AG17
AD12

AJ18
AD14
AH18

L29
L28

K27
K26

J29
J28

H27
H26
G29
G28

F27
F26
E29
E28

D27
D26
C29
C28

C23
B23
E22

D23
F21

PETP1
PERN2

PERP2
PETN2
PETP2

PERN3
PERP3
PETN3
PETP3

PERN4
PERP4
PETN4
PETP4

PERN5
PERP5
PETN5
PETP5

PERN6/GLAN_RXN
PERP6/GLAN_RXP
PETN6/GLAN_TXN
PETP6/GLAN_TXP

SPI_CLK
SPI_CS0#
SPI_CS1#

SPI_MOSI
SPI_MISO

OC0#
OC1#/GPIO40
OC2#/GPIO41
OC3#/GPIO42
OC4#/GPIO43
OC5#/GPIO29
OC6#/GPIO30
OC7#/GPIO31
OC8#
OC9#

ICH8M REV 1.0

PCIE_RXN2
PCIE_RXP2
PCIE_C_TXN2
PCIE_C_TXP2

PCIE_RXN3
PCIE_RXP3
PCIE_C_TXN3
PCIE_C_TXP3

PCIE_RXN4
PCIE_RXP4
PCIE_C_TXN4
PCIE_C_TXP4

GLAN_RXN

GLAN_RXP
GLAN_TXN_C
GLAN_TXP_C

USB_OC#0
USB_OC#1
USB_OC#2
USB_OC#3
USB_OC#4
USB_OC#5
EC_SWI#
USB_OC#7
USB_OC#8
USB_OC#9

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

SATA0GP/GPIO21
SATA1GP/GPIO19
SATA2GP/GPIO36

SATA

GPIO

SATA3GP/GPIO37

SMB

Clocks

S4_STATE#/GPIO26

SYS

GPIO

DPRSLPVR/GPIO16

Power MGTController Link

GPIO

MEM_LED/GPIO24
ME_EC_ALERT/GPIO10
EC_ME_ALERT/GPIO14

WOL_EN/GPIO9

MISC

DMI0RXN
DMI0RXP
DMI0TXN

DMI0TXP

DMI1RXN
DMI1RXP
DMI1TXN

DMI1TXP

DMI2RXN
DMI2RXP
DMI2TXN

DMI2TXP

DMI3RXN
DMI3RXP
DMI3TXN

DMI3TXP

PCI-Express

DMI_CLKN

DMI_CLKP

DMI_ZCOMP

DMI_IRCOMP

Direct Media Interface

USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4N

SPI

USBP4P
USBP5N
USBP5P
USBP6N

USB

USBP6P
USBP7N
USBP7P
USBP8N
USBP8P
USBP9N
USBP9P

USBRBIAS#

USBRBIAS

2007/1/15 2008/1/15

3

CLK14
CLK48

SUSCLK

SLP_S3#
SLP_S4#
SLP_S5#

PWROK

BATLOW#
PWRBTN#

LAN_RST#

RSMRST#

CK_PWRGD

CLPWROK

SLP_M#

CL_CLK0
CL_CLK1

CL_DATA0
CL_DATA1

CL_VREF0
CL_VREF1

CL_RST#

V27
V26
U29
U28

Y27
Y26
W29
W28

AB26
AB25
AA29
AA28

AD27
AD26
AC29
AC28

T26
T25

Y23
Y24

G3
G2
H5
H4
H2
H1
J3
J2
K5
K4
K2
K1
L3
L2
M5
M4
M2
M1
N3
N2

F2
F3

AJ12
AJ10
AF11
AG11

AG9
G5

D3
AG23

AF21
AD18

AH27
AE23
AJ14
AE21
C2
AH20
AG27
E1
E3
AJ25
F23

AE18
F22

AF19
D24

AH23
AJ23
AJ27

AJ24
AF22
AG19

DMI_RXN0
DMI_RXP0
DMI_TXN0
DMI_TXP0

DMI_RXN1
DMI_RXP1
DMI_TXN1
DMI_TXP1

DMI_RXN2
DMI_RXP2
DMI_TXN2
DMI_TXP2

DMI_RXN3
DMI_RXP3
DMI_TXN3
DMI_TXP3

CLK_PCIE_ICH#
CLK_PCIE_ICH

DMI_IRCOMP
USB20_N0

USB20_P0
USB20_N1
USB20_P1
USB20_N2
USB20_P2
USB20_N3
USB20_P3
USB20_N4
USB20_P4
USB20_N5
USB20_P5
USB20_N6
USB20_P6
USB20_N7
USB20_P7
USB20_N8
USB20_P8
USB20_N9
USB20_P9

USBRBIAS

Compal Secret Data

1 2

CLK_14M_ICH
CLK_48M_ICH

ICH_SUSCLK
SLP_S3#

SLP_S4#
SLP_S5#

T46 PAD

PM_PWROK
DPRSLPVR
ICH_LOW_BAT#
PBTN_OUT#

PM_RSMRST#
CK_PWRGD_R CK_PWRGD
M_PWROK

CL_CLK0

CL_DATA0

CL_VREF0_ICH
CL_VREF1_ICH

CLK_14M_ICH 16
CLK_48M_ICH 16

T34 PAD

SLP_S3# 29
SLP_S4# 29
SLP_S5# 29

R123 0_0402_5%

1 2

PM_PWROK 7,29
DPRSLPVR 7,49

PBTN_OUT# 29
PLT_RST# 7,17,22,24,28,29,34

1 2

R176 0_0402_5%

M_PWROK 7

T43 PAD

T44 PAD

12

R3390_0402_5%

DMI_RXN0 7

DMI_RXP0 7
DMI_TXN0 7
DMI_TXP0 7

DMI_RXN1 7

DMI_RXP1 7
DMI_TXN1 7
DMI_TXP1 7

DMI_RXN2 7

DMI_RXP2 7
DMI_TXN2 7
DMI_TXP2 7

DMI_RXN3 7

DMI_RXP3 7
DMI_TXN3 7
DMI_TXP3 7

CLK_PCIE_ICH# 16
CLK_PCIE_ICH 16

R152 24.9_0402_1%

1 2

USB20_N0 32
USB20_P0 32
USB20_N1 32
USB20_P1 32
USB20_N2 32
USB20_P2 32
USB20_N3 32
USB20_P3 32
USB20_N4 24
USB20_P4 24
USB20_N5 28
USB20_P5 28
USB20_N6 32
USB20_P6 32
USB20_N7 32
USB20_P7 32
USB20_N8 15
USB20_P8 15
USB20_N9 32
USB20_P9 32

1 2

R177 22.6_0402_1%

Within 500 mils

Deciphered Date

2

M_PWROK

1 2

CL_CLK0 7

CL_DATA0 7

CL_RST# 7

ACIN 29,43,44

LAN_WOL_EN 29

Within 500 mils

ESATA+USB
USB0
USB1
USB2
Mini Card0
Express Card
FingerPrinter
BlueTooth
Camera

Felica

2

R128

10K_0402_5%

1 2

R158 10K_0402_5%

CK_PWRGD 16

RSMRST# -> CLPWROK -> PWROK

R195 3.24K_0402_1%

1 2

12

1

R180

+1.5VS

0.1U_0402_16V4Z~N

C234

2

453_0402_1%

EC_RSMRST#29

Title

ICH8(3/4)_PM,USB,GPIO

Size Document Number Rev

Custom

LA-4231P

Date: Sheet

1

Place closely pin AG9Place closely pin G5

CLK_14M_ICHCLK_48M_ICH

12

R175

10_0402_5%@

1

C229

4.7P_0402_50V8C@

2

+3VS

EC_RSMRST# PM_RSMRST#

12

1

2

R157 0_0402_5%

1 2

R125

10_0402_5%@

C196

4.7P_0402_50V8C@

Compal Electronics, Inc.

of

19 49Thursday, January 10, 2008

1

0.1

5

D D

+5VS +3VS

12

R159

100_0402_5%

C C

10_0402_5%

+1.5VS

B B

A A

+3VALW+5VALW

12

R361

L30

1 2

CHB1608U301_0603

+1.5VS

C230

0.1U_0402_16V4Z~N

L15

1 2

+1.5VS

CHB1608U301_0603

21

D10
CH751H-40PT_SOD323-2

20 mils

ICH_V5REF_RUN

1

C224

0.1U_0402_16V4Z~N

2

21

D18
CH751H-40PT_SOD323-2

ICH_V5REF_SUS

20 mils

1

C438

0.1U_0402_16V4Z~N

2

1

C422

2

1U_0603_10V4Z

C231

0.1U_0402_16V4Z~N

+3VS

0316 change design

1

+1.5VS

2

5

C219

1

C421

2

1

2

1 2

L17

C252

+RTCVCC

1

C205

2

0.1U_0402_16V4Z~N

40 mils

1

+

C430

220U_D2_4VY_R15M

2

10U_0805_6.3V6M

10U_0805_6.3V6M

+1.5VS

+1.5VS

0.1U_0402_16V4Z~N

CHB1608U301_0603

1

2

2.2U_0603_106K

10U_0805_6.3V6M

1

C218

2

0.1U_0402_16V4Z~N

ICH_V5REF_RUN

ICH_V5REF_SUS

10U_0805_6.3V6M

1

C200

2

+1.5VS

1U_0603_10V4Z

1U_0603_10V4Z

C226

1

+1.5VS

CHB1608U301_0603

C261

2

20 mils

1

C427

2

2.2U_0603_6.3V4Z~N

C420

C428

1

2

VCC_LAN1_05_INT_ICH_1

T31

VCC_LAN1_05_INT_ICH_2

T32

L32

@

1 2

1

2

1

2

1

2

+1.5VS

4.7U_0805_10V4Z~N

1

C457

@
2

+3VS

AD25

AA25
AA26
AA27
AB27
AB28
AB29

W25

AG7

AC10

W23

A16

T7

G4

D28
D29
E25
E26
E27

F24

F25
G24
H23
H24

J23

J24
K24
K25

L23

L24

L25
M24
M25
N23
N24
N25
P24
P25
R24
R25
R26
R27

T23

T24

T27

T28

T29
U24
U25
V23
V24
V25

Y25

AJ6
AE7

AF7
AH7

AJ7
AC1

AC2
AC3
AC4
AC5

AC9
AA5

AA6
G12

G17

H7

AC7
AD7

D1

F1
L6

L7
M6
M7

F17

G18

F19

G20
A24
A26

A27
B26
B27
B28

B25

4

U8F

VCCRTC
V5REF[1]

V5REF[2]
V5REF_SUS
VCC1_5_B[01]

VCC1_5_B[02]
VCC1_5_B[03]
VCC1_5_B[04]
VCC1_5_B[05]
VCC1_5_B[06]
VCC1_5_B[07]
VCC1_5_B[08]
VCC1_5_B[09]
VCC1_5_B[10]
VCC1_5_B[11]
VCC1_5_B[12]
VCC1_5_B[13]
VCC1_5_B[14]
VCC1_5_B[15]
VCC1_5_B[16]
VCC1_5_B[17]
VCC1_5_B[18]
VCC1_5_B[19]
VCC1_5_B[20]
VCC1_5_B[21]
VCC1_5_B[22]
VCC1_5_B[23]
VCC1_5_B[24]
VCC1_5_B[25]
VCC1_5_B[26]
VCC1_5_B[27]
VCC1_5_B[28]
VCC1_5_B[29]
VCC1_5_B[30]
VCC1_5_B[31]
VCC1_5_B[32]
VCC1_5_B[33]
VCC1_5_B[34]
VCC1_5_B[35]
VCC1_5_B[36]
VCC1_5_B[37]
VCC1_5_B[38]
VCC1_5_B[39]
VCC1_5_B[40]
VCC1_5_B[41]
VCC1_5_B[42]
VCC1_5_B[43]
VCC1_5_B[44]
VCC1_5_B[45]
VCC1_5_B[46]

VCCSATAPLL
VCC1_5_A[01]

VCC1_5_A[02]
VCC1_5_A[03]
VCC1_5_A[04]
VCC1_5_A[05]

VCC1_5_A[06]
VCC1_5_A[07]
VCC1_5_A[08]
VCC1_5_A[09]
VCC1_5_A[10]

VCC1_5_A[11]
VCC1_5_A[12]

VCC1_5_A[13]
VCC1_5_A[14]

VCC1_5_A[15]
VCC1_5_A[16]
VCC1_5_A[17]

VCC1_5_A[18]
VCC1_5_A[19]

VCCUSBPLL
VCC1_5_A[20]

VCC1_5_A[21]
VCC1_5_A[22]
VCC1_5_A[23]
VCC1_5_A[24]

VCC1_5_A[25]
VCCLAN1_05[1]

VCCLAN1_05[2]
VCCLAN3_3[1]

VCCLAN3_3[2]
VCCGLANPLL
VCCGLAN1_5[1]

VCCGLAN1_5[2]
VCCGLAN1_5[3]
VCCGLAN1_5[4]
VCCGLAN1_5[5]

VCCGLAN3_3

ICH8M REV 1.0

4

VCC1_05[01]
VCC1_05[02]
VCC1_05[03]
VCC1_05[04]
VCC1_05[05]
VCC1_05[06]
VCC1_05[07]
VCC1_05[08]
VCC1_05[09]
VCC1_05[10]
VCC1_05[11]
VCC1_05[12]
VCC1_05[13]
VCC1_05[14]
VCC1_05[15]
VCC1_05[16]

CORE

VCC1_05[17]
VCC1_05[18]
VCC1_05[19]
VCC1_05[20]
VCC1_05[21]
VCC1_05[22]
VCC1_05[23]
VCC1_05[24]
VCC1_05[25]
VCC1_05[26]
VCC1_05[27]
VCC1_05[28]

VCCA3GP ATXARX

V_CPU_IO[1]
V_CPU_IO[2]

VCCP_COREVCCPSUSVCCPUSB

IDE

PCI

VCCSUSHDA

VCCSUS1_05[1]
VCCSUS1_05[2]

VCCSUS1_5[1]

VCCSUS1_5[2]
VCCSUS3_3[01]
VCCSUS3_3[02]

VCCSUS3_3[03]
VCCSUS3_3[04]
VCCSUS3_3[05]

USB CORE

VCCSUS3_3[06]
VCCSUS3_3[07]

VCCSUS3_3[08]
VCCSUS3_3[09]
VCCSUS3_3[10]
VCCSUS3_3[11]
VCCSUS3_3[12]
VCCSUS3_3[13]
VCCSUS3_3[14]
VCCSUS3_3[15]
VCCSUS3_3[16]
VCCSUS3_3[17]
VCCSUS3_3[18]
VCCSUS3_3[19]

GLAN POWER

VCCCL3_3[1]
VCCCL3_3[2]

VCCDMIPLL
VCC_DMI[1]

VCC_DMI[2]

VCC3_3[01]
VCC3_3[02]
VCC3_3[03]

VCC3_3[04]
VCC3_3[05]
VCC3_3[06]

VCC3_3[07]
VCC3_3[08]
VCC3_3[09]
VCC3_3[10]
VCC3_3[11]
VCC3_3[12]
VCC3_3[13]

VCC3_3[14]
VCC3_3[15]
VCC3_3[16]
VCC3_3[17]
VCC3_3[18]
VCC3_3[19]
VCC3_3[20]
VCC3_3[21]
VCC3_3[22]
VCC3_3[23]
VCC3_3[24]

VCCHDA

VCCCL1_05

VCCCL1_5

3

A13
B13
C13
C14
D14
E14
F14
G14
L11
L12
L14
L16
L17
L18
M11
M18
P11
P18
T11
T18
U11
U18
V11
V12
V14
V16
V17
V18

R29
AE28

AE29
AC23

AC24
AF29
AD2
AC8

AD8
AE8
AF8

AA3
U7
V7
W1
W6
W7
Y7

A8
B15
B18
B4
B9
C15
D13
D5
E10
E7
F11

AC12
AD11

TP_VCCSUS1.05_INT_ICH1

J6

TP_VCCSUS1.05_INT_ICH2

AF20

VCCSUS1_5_ICH_1

AC16

VCCSUS1_5_ICH_2

J7
C3
AC18

AC21
AC22
AG20
AH28

P6
P7
C1
N7
P1
P2
P3
P4
P5
R1
R3
R5
R6

VCCCL1_05_ICH

G22
A22
F20

G21

0.1U_0402_16V7K~N

1

C227 0.1U_0402_16V4Z~N

C215

2

0.01U_0402_16V7K~N

C431

0.1U_0402_16V4Z~N

+3VS

+3VS

1

C213

0.1U_0402_16V4Z~N

2

0.1U_0402_16V4Z~N

+3VS

1

C202

2

C258

1

0.47U_0603_10V7K

2

T26

1

C458

@

1U_0603_10V4Z

2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

+VCCP

1

2

L16

1 2

CHB1608U301_0603

1

1

C225 10U_0805_6.3V6M

2

2

+1.25VS

22U_0805_6.3V4Z

C425

1

2

0.1U_0402_16V4Z~N

+3VS

(SATA)

1

C198

2

0.1U_0402_16V4Z~N

1

1

C214

2

2

0.1U_0402_16V4Z~N

0.1U_0402_16V4Z~N

+3VALW

1

C216

T21

2

0.1U_0402_16V4Z~N

T22
T24

1

C194

2

0.1U_0402_16V4Z~N

+3VALW

+3VALW

2007/1/15 2008/1/15

C232

1

2

+3VS

C197

1

2

+1.5VS

+3VS

(DMI)

C233

0.1U_0402_16V4Z~N

+3VS

1

C199

2T25

Compal Secret Data

4.7U_0603_6.3V6M

1

2

Deciphered Date

C217

0.1U_0402_16V4Z~N
C203

1

2

0.1U_0402_16V4Z~N

2

U8E

A23

VSS[001]

A5

VSS[002]

AA2

VSS[003]

AA7

VSS[004]

A25

VSS[005]

AB1

VSS[006]

AB24

VSS[007]

AC11

VSS[008]

AC14

VSS[009]

AC25

VSS[010]

AC26

VSS[011]

AC27

VSS[012]

AD17

VSS[013]

AD20

VSS[014]

AD28

VSS[015]

AD29

VSS[016]

AD3

VSS[017]

AD4

VSS[018]

AD6

VSS[019]

AE1

VSS[020]

AE12

VSS[021]

AE2

VSS[022]

AE22

VSS[023]

AD1

VSS[024]

AE25

VSS[025]

AE5

VSS[026]

AE6

VSS[027]

AE9

VSS[028]

AF14

VSS[029]

AF16

VSS[030]

AF18

VSS[031]

AF3

VSS[032]

AF4

VSS[033]

AG5

VSS[034]

AG6

VSS[035]

+VCCP

C204

1

2

2

AH10

VSS[036]

AH13

VSS[037]

AH16

VSS[038]

AH19

VSS[039]

AH2

VSS[040]

AF28

VSS[041]

AH22

VSS[042]

AH24

VSS[043]

AH26

VSS[044]

AH3

VSS[045]

AH4

VSS[046]

AH8

VSS[047]

AJ5

VSS[048]

B11

VSS[049]

B14

VSS[050]

B17

VSS[051]

B2

VSS[052]

B20

VSS[053]

B22

VSS[054]

B8

VSS[055]

C24

VSS[056]

C26

VSS[057]

C27

VSS[058]

C6

VSS[059]

D12

VSS[060]

D15

VSS[061]

D18

VSS[062]

D2

VSS[063]

D4

VSS[064]

E21

VSS[065]

E24

VSS[066]

E4

VSS[067]

E9

VSS[068]

F15

VSS[069]

E23

VSS[070]

F28

VSS[071]

F29

VSS[072]

F7

VSS[073]

G1

VSS[074]

E2

VSS[075]

G10

VSS[076]

G13

VSS[077]

G19

VSS[078]

G23

VSS[079]

G25

VSS[080]

G26

VSS[081]

G27

VSS[082]

H25

VSS[083]

H28

VSS[084]

H29

VSS[085]

H3

VSS[086]

H6

VSS[087]

J1

VSS[088]

J25

VSS[089]

J26

VSS[090]

J27

VSS[091]

J4

VSS[092]

J5

VSS[093]

K23

VSS[094]

K28

VSS[095]

K29

VSS[096]

K3

VSS[097]

K6

VSS[098]

ICH8M REV 1.0

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

ICH8(4/4)_POWER&GND

LA-4231P

1

VSS[099]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
VSS[159]
VSS[160]
VSS[161]
VSS[162]
VSS[163]
VSS[164]
VSS[165]
VSS[166]
VSS[167]
VSS[168]
VSS[169]
VSS[170]
VSS[171]
VSS[172]
VSS[173]
VSS[174]
VSS[175]
VSS[176]
VSS[177]
VSS[178]
VSS[179]
VSS[180]
VSS[181]
VSS[182]
VSS[183]
VSS[184]

VSS_NCTF[01]
VSS_NCTF[02]
VSS_NCTF[03]
VSS_NCTF[04]
VSS_NCTF[05]
VSS_NCTF[06]
VSS_NCTF[07]
VSS_NCTF[08]
VSS_NCTF[09]
VSS_NCTF[10]
VSS_NCTF[11]
VSS_NCTF[12]

1

K7
L1
L13
L15
L26
L27
L4
L5
M12
M13
M14
M15
M16
M17
M23
M28
M29
M3
N1
N11
N12
N13
N14
N15
N16
N17
N18
N26
N27
N4
N5
N6
P12
P13
P14
P15
P16
P17
P23
P28
P29
R11
R12
R13
R14
R15
R16
R17
R18
R28
R4
T12
T13
T14
T15
T16
T17
T2
U12
U13
U14
U15
U16
U17
U23
U26
U27
U3
U5
V13
V15
V28
V29
W2
W26
W27
Y28
Y29
Y4
AB4
AB23
AB5
AB6
AD5
U4
W24

A1
A2
A28
A29
AH1
AH29
AJ1
AJ2
AJ28
AJ29
B1
B29

0.1

of

20 49Thursday, January 10, 2008

5

CDROM CONN

C520 47P_0402_50V8J

12

D D

PCI_RST#

PCI_RST#17,40

+5VS

12

R429

100K_0402_5%

C C

ODD_ACT_LED#31

+5VS

10K_0402_5%

ODD_ACT_LED#

If CDROM is Slave
then SD_CSEL= Floating
else SD_CSEL= Low

1 2

R448 0_0402_5%

IDE_DDREQ18

IDE_DIOR#18
IDE_DIOW#18

IDE_DIORDY18
IDE_DDACK#18

IDE_IRQ18
IDE_DA118

R428

@

IDE_DA018

IDE_DA218
IDE_DCS1#18
IDE_DCS3#18

1 2

+5VS

PDIAG#

80mils

SD_CSEL

12

R286470_0402_5%

IDE_DD8
IDE_DD7
IDE_DD9
IDE_DD6
IDE_DD10
IDE_DD5
IDE_DD11
IDE_DD4
IDE_DD12
IDE_DD3
IDE_DD13
IDE_DD2
IDE_DD14
IDE_DD1
IDE_DD15
IDE_DD0

4

JODD1

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

11

11

12

12

13

13

14

14

15

15

16

16

17

17

18

18

19

19

20

20

21

21

22

22

23

23

24

24

25

25

26

26

27

27

28

28

29

29

30

30

31

31

32

32

33

33

34

34

35

35

36

36

37

37

38

38

39

39

40

40

41

41

42

42

43

43

44

44

45

45

46

GND

47

GND

ACES_88512-4541

IDE_DD[0..15] 18

3

+5VS

10U_0805_10V4Z

1

C498

2

1U_0603_10V4Z

1

C506

2

2

0.1U_0402_16V4Z

1

C503

2

1

C499

2

1000P_0402_50V7K~N

1

Close to ODD Conn

+5VS

1

+

C575

C574

150U_B2_6.3VM_R45M

2

10U_0805_10V4Z~N

1

2

C296

0.1U_0402_16V7K~N

1

2

0.1U_0402_16V7K~N

1

C377

2

1

C376

2

1000P_0402_50V7K~N

Close to SATA HDD

SATA HDD CONN

B B

PSATA_ITX_DRX_P018
PSATA_ITX_DRX_N018

PSATA_IRX_DTX_N0_C18
PSATA_IRX_DTX_P0_C18

PSATA_ITX_DRX_P0
PSATA_ITX_DRX_N0

C393 3900P_0402_50V7K

12

12

C392 3900P_0402_50V7K

+5VS

A A

5

JSATA1

1

GND

2

A+

3

A-

4

GND

5

B-

6

B+

7

GND

8

VCC3.3

9

VCC3.3

10

VCC3.3

11

GND

12

GND

13

GND

14

VCC5

15

VCC5

16

VCC5

17

GND

18

RESERVED

19

GND

20

VCC12

21

VCC12

22

VCC12

SUYIN_127043FB022G345ZR_NR

CONN@

4

GND
GND

23
24

ODD_IRX_DTX_N0_C18

ODD_IRX_DTX_P0_C18

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2007/1/15 2008/1/15

Compal Secret Data

RESERVE(SATA ODD NET)

2

ODD_ITX_DRX_P0
ODD_ITX_DRX_N0

ODD_IRX_DTX_N0
ODD_IRX_DTX_P0

ODD_ITX_DRX_P018
ODD_ITX_DRX_N018

1 2

C326 3900P_0402_50V7K

@

1 2

C327 3900P_0402_50V7K

@

close JODD1

Deciphered Date

Title

HDD/CDROM

Size Document Number Rev

Custom

LA-4231P

Date: Sheet

1

of

21 49Thursday, January 10, 2008

0.1

5

+3VALW

1

C790

1U_0603_10V6K

B+_BIAS

D D

D

SSM3K7002FU_SC70-3

C C

B B

A A

Q58

S

+LAN_VDD

C788

L92, C788, C778
close to U28(Pin 1) <200mil

C573 0.01U_0402_16V7K

1 2

C784 0.01U_0402_16V7K

1 2

C807 0.01U_0402_16V7K

1 2

C799 0.01U_0402_16V7K

1 2

R496

470K_0402_5%

1 2
13

2

G

60mil

1

2

0.1U_0402_10V7K~N

15P_0402_50V8J

1

2

2

EN_WOL

4.7UH_1098AS-4R7M_1.3A_20%

C778

22U_1206_6.3V6M

C791

Q59

D

6

S

2
1

SI3456BDV-T1-E3_TSOP6

G

3

EN_WOL# 29

L92

1 2

1 2

+3VS

Y6

1 2

2

25MHZ_12P_X8A025000FC1H-H

1

15P_0402_50V8J

L46

FBMA-L11-322513-201LMA40T_1210

1 2

45

R906

@

1.5M_0402_5%

1 2

GLAN_RXP19

GLAN_RXN19
GLAN_TXP19
GLAN_TXN19

MCARD_REQ#F16

CLK_PCIE_LAN16

CLK_PCIE_LAN#16

PLT_RST#7,17,19,24,28,29,34

60mil

R499
15K_0402_5%

1 2

C805

V_DAC
LAN_MDIN3
LAN_MDIP3

V_DAC
LAN_MDIN2
LAN_MDIP2

V_DAC
LAN_MDIN1
LAN_MDIP1

V_DAC
LAN_MDIN0
LAN_MDIP0

PCIE_PME#29

2

1

R498

1K_0402_5%

1

C812

@

2

T51

1
2
3

4
5

7
8
9

10
11
12

BOTH_GST5009-LF

4

+LAN_IO

1

1

C777

2

2

22U_1206_6.3V6M

22U_1206_6.3V6M

GLAN_RXP_C

12

C569 0.1U_0402_16V7K~N

GLAN_RXN_C

12

C570 0.1U_0402_16V7K~N

+LAN_VDD

+LAN_IO

1 2

R497 2.49K_0402_1%

ISOLATEB

LAN_XTAL1
LAN_XTAL2

MCT1
MX1+

MX1-

MCT2
MX2+

MCT3
MX3+

MX3-

MCT4
MX4+

MX4-

24
23
22

21
20
19

18
17
16

15
14
13

TCT1
TD1+
TD1-

TCT2
TD2+
TD2-6MX2-

TCT3
TD3+
TD3-

TCT4
TD4+
TD4-

1.5A

C787

0.1U_0402_10V7K~N

GLAN_TXP
GLAN_TXN

RJ45_TX3­RJ45_TX3+

RJ45_TX2­RJ45_TX2+

RJ45_RX1­RJ45_RX1+

RJ45_TX0­RJ45_TX0+

1

C781

2

0.1U_0402_10V7K~N

U28

29

HSOP

30

HSON

23

HSIP

24

HSIN

33

CLKREQB

26

REFCLK_P

27

REFCLK_N

20

PERSTB

1

SROUT12

5

FB12

62

ENSR

64

RSET

19

LANWAKEB

36

ISOLATEB

60

CKTAL1

61

CKTAL2

65

EXPOSE_PAD

25

EGND

31

EGND

15

NC

17

NC

18

NC

34

NC

35

NC

39

NC

40

NC

41

NC

42

NC

RTL8111C-GR_QFN64_9X9

RP38

75_1206_8P4R_5%

1

C802

2

18
27
36
45

0.1U_0402_10V7K~N

EEDO

EEDI/AUX

EESK
EECS

LED3
LED2
LED1
LED0

MDIP0
MDIN0
MDIP1
MDIN1
MDIP2
MDIN2
MDIP3
MDIN3

DVDD12
DVDD12
DVDD12
DVDD12
DVDD12
DVDD12

EVDD12
EVDD12

VDD33
VDD33
VDD33
VDD33

VDDSR

AVDD33
AVDD33

AVDD12
AVDD12
AVDD12
AVDD12

IGPIO

OGPIO

C794
1000P_1206_2KV7K

12

45
47
48
44

54
55
56
57

3
4
6
7
9
10
12
13

21
32
38
43
49
52

22
28

16
37
46
53

63
2

59
8

11
14
58

50
51

1

C804

2

LAN_EEDO
LAN_EEDI
LAN_EECLK
LAN_EECS

3

0.1U_0402_10V7K~N

R494

LAN_MDIP0
LAN_MDIN0
LAN_MDIP1
LAN_MDIN1
LAN_MDIP2
LAN_MDIN2
LAN_MDIP3
LAN_MDIN3

LAN_AVDD33

LAN_LED2

CH751H-40PT_SOD323-2

LAN_LED3

CH751H-40PT_SOD323-2

LAN_LED1

CH751H-40PT_SOD323-2

LAN_LED3

CH751H-40PT_SOD323-2

1 2

U43

4

DO

3

DI

2

SK

1

CS

AT93C46-10SU-2.7 SO 8P

LAN_LED3
LAN_LED2
LAN_LED1
LAN_LED0

+LAN_VDD

30mil

+LAN_IO

+LAN_IO

+LAN_VDD

D41

D42

D43

D44

+LAN_VDD

3.6K_0402_5%

GND

NC
NC

VCC

C637 0.1U_0402_16V7K~N
C793 0.1U_0402_16V7K~N

LED2_LED3

21

21

LED1_LED3

21

21

+LAN_IO

5

R495

6

1 2

0_0402_5%

7
8

@

FBML10160808121LMT_0603

1 2
1 2

FBML10160808121LMT_0603

1 2

C571 0.1U_0402_16V7K~N

1 2

C789 0.1U_0402_16V7K~N

@

L56

12

1

C8000.1U_0402_10V7K~N

2

@

+LAN_VDD

L55

12

LED2_LED3
LED1_LED3

1

1

C7980.1U_0402_10V7K~N

C8100.1U_0402_10V7K~N

2

2

1

0.1U_0402_16V7K~N

+LAN_IO

2

+LAN_IO

R968

1 2

220_0402_5%

+LAN_IO

RJ45_TX3­RJ45_TX3+
RJ45_RX1­RJ45_TX2­RJ45_TX2+
RJ45_RX1+
RJ45_TX0­RJ45_TX0+

R969

1 2

220_0402_5%

R970

1 2

220_0402_5%

+LAN_IO

2

LAN_DVDD15

1

C8030.1U_0402_10V7K~N

2

C801

LAN_ACTIVITY#LAN_LED0

LINK_10_1000#
LINK_100_1000#

1

1

C6980.1U_0402_10V7K~N

C5720.1U_0402_10V7K~N

2

2

1

C783

2

22U_1206_6.3V6M

C966,C967 close to U28(PIN63)

13
12

8
7
6
5
4
3
2
1

11

9

10

1

C7800.1U_0402_10V7K~N

C7820.1U_0402_10V7K~N

2

JLAN2

Yellow LED­Yellow LED+
PR4­PR4+
PR2­PR3­PR3+
PR2+
PR1­PR1+
Green LED­Orange LED­Green-Orange LED+

C-1775553

CONN@

1

1

C7790.1U_0402_10V7K~N

2

2

C792

1

2

0.1U_0402_10V7K~N

1

C7000.1U_0402_10V7K~N

2

+LAN_IO

GND
GND

1

R315

1 2

R316

1 2

R317

1 2

R318

1 2

15
14

0_0402_5%

0_0402_5%

0_0402_5%

0_0402_5%

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2007/1/15 2008/1/15

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

Compal Electronics, Inc.

Broadcom BCM5787M

LA-4231P

1

0.1

of

22 49Thursday, January 10, 2008

A

B

C

D

E

Mini-Express Card---WLAN

1 1

ICH_PCIE_WAKE#19,28

CH_DATA32

CH_CLK32

MCARD_REQ#G16

CLK_PCIE_MCARD#16

CLK_PCIE_MCARD16

WL_OFF#29,32

PLT_RST#7,17,19,22,28,29,34

PCIE_RXN419

2 2

3 3

+3VALW

PCIE_RXP419

+1.5VS

ICH_SM_CLK13,14,16,19

PCIE_TXN419

ICH_SM_DA13,14,16,19
PCIE_TXP419

USB20_N419
USB20_P419

+3VS

+1.5VS

+3VS

ICH_PCIE_WAKE#

CH_DATA MINI_PIN3

R380 0_0402_5%@

CH_CLK MINI_PIN4

PCIE_RXN4 PCIE_C_RXN4
PCIE_RXP4 PCIE_C_RXP4

PCIE_TXN4
PCIE_TXP4

LED_WLAN#31

1 2

R381 0_0402_5%@

1 2

MCARD_REQ#G

WL_OFF#

1 2

R403 0_0402_5%
R406 0_0402_5%

1 2

R404 0_0402_5%

R373 0_0402_5%
R343 0_0402_5%

USB20_N4
USB20_P4

T61PAD

12

12
12

LED_WWAN#

LED_WLAN#

+3VS+1.5VS

10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52

53
54

FOX_AS0B246-S50U-7F

JMINI2

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52

GND1
GND2

0.01U_0402_16V7K~N

1

C500

2

1

C489

2

0.1U_0402_16V4Z~N

1

C485

2

0.01U_0402_16V7K~N

+3VS

4.7U_0805_10V4Z~N

C456

+1.5VS

0.01U_0402_16V7K~N

C488

CLK_PCIE_Rob#16
CLK_PCIE_Rob16

CLK_DEBUG_PORT16

1

2

1

2

Roboson

0.01U_0402_16V7K~N

1

C294

2

MCARD_REQ#E16

PLT_RST#

PCIE_RXN319
PCIE_RXP319

PCIE_TXN319

PCIE_TXP319

PCIE_RXP3

+3VS +1.5VS

C321

4.7U_0805_10V4Z~N

1 2

R279 0_0402_5%

CLK_PCIE_Rob#
CLK_PCIE_Rob

1 2

R444 0_0402_5%
R288 0_0402_5%

1 2

1 2

R290 0_0402_5%

PCIE_TXN3
PCIE_TXP3

0.01U_0402_16V7K~N

1

2

ROB_REQE#

PCIE_C_RXN3PCIE_RXN3
PCIE_C_RXP3

1

C298

2

JMINI1

1

1

3

3

5

5

7

7

9

9

11

11

13

13

15

15

17

17

19

19

21

21

23

23

25

25

27

27

29

29

31

31

33

33

35

35

37

37

39

39

41

41

43

43

45

45

47

47

49

49

51

51

53

GND1

FOX_AS0B226-S52N-7F~N

GND2

Power status(Left)

PWR_BLUE_LED#29,31

BATT_LOW_LED#29
BATT_CHG_LED#29

1

C312

2

0.1U_0402_16V4Z~N

+1.5VS +3VS

2

2

4

4

6

6

8

8

10

10

12

12

14

14

16

16

18

18

20

20

22

22

24

24

26

26

28

28

30

30

32

32

34

34

36

36

38

38

40

40
42
44
46
48
50
52

DISK_BUSY

42
44
46
48
50
52

54

PWR_BLUE_LED#

BATT_LOW_LED#
BATT_CHG_LED#

12-22/Y2BHC-A30/2C_Y/B~D

4.7U_0805_10V4Z~N

1

C320

2

1 2

R280 0_0402_5%

1 2

R282 0_0402_5%

1 2

R281 0_0402_5%

1 2

R283 0_0402_5%

1 2

R287 0_0402_5%

PLT_RST# 7,17,19,22,28,29,34

T23 PAD

LED1
12-21-BHC-ZL1M2RY-2C BLUE

12

LED2

Y

3

1

2

B

LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0

R472

1 2

200_0603_5%

R471

1 2

200_0603_5%

LPC_FRAME# 18,29

LPC_AD[0..3] 18,29

+5VALW

+5VALW

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2007/1/15 2008/1/15

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

D

Date: Sheet

Compal Electronics, Inc.

Mini-Card/LED

LA-4231P

0.1

of

24 49Thursday, January 10, 2008

E

5

40mil

1

1

C862

2

2

0.1U_0402_16V4Z

1 2

C876 2.2U_0603_10V6K

1 2

C877 2.2U_0603_10V6K

ACZ_RST#18
ACZ_SYNC18
ACZ_SDOUT18

MIC_SIG

1 2

R412 0_0402_5%

R894

C_MIC1
C_MIC2
MONO_IN

SENSE_A

12

0_0402_5%

MIC_SIG_R

C860

12

EAPD26

MIC126
MIC226

0.1U_0402_16V4Z

1

C861

2

MIC_SIG15

EAPD

L94

+VDDA

D D

@

C C

SPK_SEL HIGH: HARMAN
LOW: NO-BRAND

MIC_JD26

1 2

FBM-L11-160808-800LMT_0603

10U_1206_16V4Z

MIC_SIG_R

2

C527
220P_0402_50V7K

1

39.2K _0402_1%

HP_JD

R892

1 2

R893 20K_0402_1%

R505,R504
close to PIN13

DGND

4

HD Audio Codec

+AVDD_AC97

20mil40mil

U49

14
15
16
17
23
24
18
20
19
21
22
12

11
10

5
2

3
13
34

47
48

4

7

38

AVDD125AVDD2
NC
NC
MIC2_L
MIC2_R
LINE1_L
LINE1_R
CD_L
CD_R
CD_GND
MIC1_L
MIC1_R
PCBEEP

RESET#
SYNC
SDATA_OUT
GPIO0

GPIO3
SENSE A
SENSE B

EAPD
SPDIFO
DVSS1

DVSS2

ALC268-GR_LQFP48

1

DVDD

LINE_OUT_L

LINE_OUT_R

HP_OUT_L

HP_OUT_R

DMIC_CLK

BIT_CLK

SDATA_IN

MONO_OUT

LINE1_VREFO

GPIO1
MIC1_VREFO_L
MIC1_VREFO_R

MIC2_VREFO

VREF

JDREF

AVSS1
AVSS2

9

NC

NC
NC

NC

DVDD_IO

35
36
39
41
45
46
43
44

6

8
37
29
31
28
32
30
27
40
33
26

42

0.1U_0402_16V4Z

LINEL
LINER
HP_LOUT
HP_ROUT

10mil
10mil

AGND

1

1

C863

C864

2

2

0.1U_0402_16V4Z

C867 1000P_0402_50V7K~N
C869 1000P_0402_50V7K~N

R885 0_0603_5%
R886 0_0603_5%

C872 1000P_0402_50V7K~N
C873 1000P_0402_50V7K~N

R415 0_0402_5%

1 2

C526 220P_0402_50V7K

@

1 2

R890 0_0402_5%

1 2

R891

+MIC1_VREFO_L
+MIC1_VREFO_R

AC97_VREF

10mil

For EMI

0_0603_5%

1 2

R877

1

C865
10U_1206_16V4Z

2

1 2

R881 6.8K_0603_5%

1 2

R884 6.8K_0603_5%

1 2
1 2

1 2

R889

@

10_0402_5%

0_0402_5%

12

R895
20K_0402_1%

close to CODEC

3

+3VS

HP_LEFT 26
HP_RIGHT 26

MIC_CLK

@

1 2

12

C875 10P_0402_50V8J~N

ACZ_BITCLK 18

ADC_ACZ_SDIN0 18

1

C879
10U_0805_10V4Z

2

AMP_LEFT 26
AMP_RIGHT 26

MIC_CLK 15

EC Beep

BEEP29

ICH Beep

SB_SPKR19

R369

1 2

47K_0402_5%

R363

1 2

47K_0402_5%

2

+VDDA

12

R370
10K_0402_5%

12

R367

2

B

12

10K_0402_5%

1

C

Q21

E

2SC2411K_SC59

3

D22
CH751H-40PT SOD323

2 1

C302

1 2

1U_0603_10V4Z

C305

1 2

1U_0603_10V4Z

R368

1 2

560_0402_5%

R364

1 2

560_0402_5%

10K_0402_5%

R371

1

C301

1 2

1U_0603_10V4Z

C308

1 2

1U_0603_10V4Z

1 2

R384

2.4K_0402_5%

MONO_IN

Sense Pin Impedance Codec Signals

PORT-A (PIN 39, 41)
PORT-B (PIN 21, 22)
PORT-C (PIN 23, 24)
PORT-D (PIN 35, 36)
PORT-E (PIN 14, 15)
PORT-F (PIN 16, 17)
PORT-G (PIN 43, 44)
PORT-H (PIN 45, 46)

Issued Date

3

SENSE A

SENSE B

39.2K
20K
10K

5.1K

39.2K
20K
10K

5.1K

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Compal Secret Data

Deciphered Date

Regulator for CODEC

C882

Adjustable Output

R900

1 2

10K_0603_1%

+5VS

C881

4.7U_0805_10V4Z

0.1U_0402_16V7K~N

2007/08/052006/08/05

2

U50

1

VIN

2

GND
SHDN#3BP

RT9198-4GPBG SOT-23 5P 4.75V

Title

Size Document Number Rev

Date: Sheet

5

VOUT

4

+VDDA

Compal Electronics, Inc.

HD Audio Codec_ALC268

LA-4231P

1

1

2

C883 4.7U_0805_10V4Z~N

of

25 49Thursday, January 10, 2008

1

2

C884 0.1U_0402_16V7K~N

1.0

@

+3VS

1 2

PLUG_IN#

13

D

S

100K_0402_5%

12

R897

13

D

2

G

S

Q69
SSM3K7002FU_SC70-3

@

Moat Bridge

HP_JD

Q68
SSM3K7002FU_SC70-3

@

1 2

R902 0_0603_1%

1 2

R903 0_0603_1%

1 2

R904 0_0603_1%

1 2

R905 0_0603_1%

4

B B

R898

100K_0402_5%

1 2

@

PLUG_IN26

A A

5

PLUG_IN#26

R309 0_0402_5%

2

G

A

W=40Mil

1

1

C318

0.1U_0402_16V4Z

4 4

AMP_RIGHT25

AMP_LEFT25

R298 10K_0402_5%

1 2

3 3

EC_MUTE29

Change to 100p from 0.01u for EMI

-1012

2 2

0.47U_0603_10V7K

0.47U_0603_10V7K

0.47U_0603_10V7K

+3VS

12

13

D

2

G

S

1

C519

2

C331

1 2

C521

C522

R450
100K_0402_5%

@

Q43
SSM3K7002FU_SC70-3

100P_0402_50V8J

AMP_R

1 2

AMP_L

1 2

@

C518
10U_0805_10V4Z

2

2

7

17

9

5

19

D14 CH751H-40_SC76

12

R449

1K_0402_1%

EAPD

EAPD

RIN+

RIN-

LIN+

LIN-

SHUTDOWN

GNDA

21

2 1

@

25

15

16

VDD

PVDD1

GND41GND311GND213GND1

P3017THF B0 TSSOP 20P

20

6

PVDD2

R293

0_0402_5%

GAIN0
GAIN1

ROUT+

ROUT-

LOUT+

LOUT-

NC

BYPASS

R451

B

12

+5VS

U20

2
3

18

14

4

8

12
10

1 2

2.7K_0402_5%

@

+5VS

R458 10K_0402_5%
R460 10K_0402_5%@

2

C333

0.47U_0603_16V4Z

1

PLUG_IN

1 2
1 2

SPK_1

SPK_2

R461 10K_0402_5%

1 2

R459 10K_0402_5%@

1 2

1 2

R457 0_0603_5%

1 2

R456 0_0603_5%

INTSPK_1

INTSPK_2

GAIN0 GAIN1 GAIN

00

0

*

1

0

1

1

C

1

SM05T1G_SOT23-3~D

D

D12

2
3

@

Speaker Connector

INTSPK_1
INTSPK_2

JSPK2

1

1

G1

2

2

G2

ACES_88266-0200

3
4

E

MICROPHONE IN JACK

R4633K_0402_5%
R4643K_0402_5%

12
12

12

MIC225
MIC125

R310 0_0402_5%
R311 0_0402_5%

12

1 2

L34 CHB2012U170_0805

1 2

L35 CHB2012U170_0805

220P_0402_50V7K

MIC_JD25

MIC-1

C525

2

3

D16
SM05T1G_SOT23-3~D

@

1

+MIC1_VREFO_R
+MIC1_VREFO_L

MIC-2

1

C524

2

1

2

220P_0402_50V7K

FOX_JA6333L-B3S0-7F~N

5
4
3

6 7
2
1

JMIC1

10
9
8

HEADPHONE OUT JACK

FOX_JA6333L-B3S0-7F~N

5
4
3

6 7
2
1

2

C329
470P_0402_50V7K

1

1 2

11

OUTR

9

OUTL

JHP1

HP_OUTR
HP_OUTL

10
9
8

6dB

10dB

15.6dB

21.6dB1

HP_OUTR
HP_OUTL

R301 47_0402_5%

1 2

R300 47_0402_5%

1 2

PLUG_IN#25

PLUG_IN#

EAPD

EC_MUTE HP_MUTE#

R302 0_0402_5%

PLUG_IN25

HP_R
HP_L

12

12

R299

1K_0402_5%@

SM05T1G_SOT23-3~D

+3VS

5

U21

2

P

B

Y

1

A

G

MC74VHC1G08DFT2G SC70 5P

3

@

12

PLUG_IN

1 2

L23 CHB2012U170_0805

1 2

L22 CHB2012U170_0805

D23

HP_MUTE#

470P_0402_50V7K

14
18

4

R305
1K_0402_5%@

HPR

HPL

C330

2

3

1

0_0603_5%

U22

SHDNR#
SHDNL#

2

1

@

+3VS

Reserve the 0 ohm resistor.

12

for voltage filtering

R462

C523 1U_0603_10V4Z

10

19

SVDD

PVDD

R307 2.2K_0402_5%

HP_INR HPINR

HP_RIGHT25
HP_LEFT25

1 1

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2007/1/15 2008/1/15

Compal Secret Data

1 2

C339 2.2U_0603_6.3V6K

1 2

C338 2.2U_0603_6.3V6K

Deciphered Date

1 2

HP_INL HPINL

D

1 2

R306 2.2K_0402_5%

1

2

C317
1U_0603_10V4Z

15

INR

13

INL

1

C1P

3

C1N

Title

Size Document Number Rev

Custom

Date: Sheet

PGND

PVss

SVss

2

5

7

1

C316
1U_0603_10V4Z

2

AMP/Audio Jack

LA-4231P

4

NC-4

6

NC-6

8

NC-8

12

NC-12

16

NC-16

20

NC-20

SGND

S IC TPA4411MRTJR QFN 20P

17

Compal Electronics, Inc.

E

26 49Thursday, January 10, 2008

0.1

of

5

Express card

4

3

2

1

USB20_N5_R
USB20_P5_R

JEXP1

1

GND

2

USB_D-

3

USB_D+

4

CPUSB#

5

RSV

6

RSV

7

SMB_CLK

8

SMB_DATA

9

+1.5V

10

+1.5V

11

WAKE#

12

+3.3VAUX

13

PERST#

14

+3.3V

15

+3.3V

16

CLKREQ#

17

CPPE#

18

REFCLK-

19

REFCLK+

20

GND

21

PERn0

22

PERp0

23

GND

24

PETn0

25

PETp0

26

GND

27

GND

28

GND

29

GND

30

GND

FOX_1CH4312C-TB_LB

CONN@

D D

12

C91 0.1U_0402_16V4Z~N

12

C74 0.1U_0402_16V4Z~N

12

C85 0.1U_0402_16V4Z~N

PLT_RST#7,17,19,22,24,29,34

C C

SYSON29,41,46
SUSP#29,41,46,47,48 CLK_PCIE_EXPR#16

Express Card Power Switch

+1.5VS

+3VS

+3VALW

PLT_RST#

SYSON

SUSP#
CPUSB#
EXPR_CPUSB#

+1.5V_CARD Max. 650mA, Average 500mA

U11

12

1.5Vin

14

1.5Vin

2

3.3Vin

4

3.3Vin
AUX_IN17AUX_OUT

6

SYSRST#

20

SHDN#

1

STBY#

10

CPPE#

9

CPUSB#

18

RCLKEN

P2231NF_QFN20

1.5Vout

1.5Vout

3.3Vout

3.3Vout

OC#

PERST#

GND

+1.5VS_PEC

11
13

+3VS_PEC

3
5

+3V_PEC

15
19

PERST#

8
16

NC

7

0.1U_0402_16V4Z~N

0.1U_0402_16V4Z~N

+3V_CARD Max. 1300mA, Average 1000mA

0.1U_0402_16V4Z~N

C90

C92

C75

+1.5VS_PEC

1

2

+3V_PEC

1

2

+3VS_PEC

1

2

4.7U_0805_10V4Z~N

1

C89

2

4.7U_0805_10V4Z~N

1

C93

2

4.7U_0805_10V4Z~N

1

C73

2

EXPR_CARD_REQ#16

USB20_N5
USB20_P5

ICH_SMB_CLK19
ICH_SMB_DATA19

1 2

0_0402_5%

CLK_PCIE_EXPR16

USB20_N519

USB20_P519

ICH_PCIE_WAKE#19,24

R48 0_0402_5%
R47 0_0402_5%

+1.5VS_PEC
+1.5VS_PEC

R37

+3V_PEC
+3VS_PEC

PCIE_RXN219
PCIE_RXP219

PCIE_TXN219

PCIE_TXP219

1 2
1 2

ICH_SMB_CLK
ICH_SMB_DATA

EXPR_CPUSB#

PCIE_PME#_R
PERST#

EXPR_CARD_REQ#
CPUSB#
CLK_PCIE_EXPR#
CLK_PCIE_EXPR

PCIE_RXN2
PCIE_RXP2

PCIE_TXN2
PCIE_TXP2

B B

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2007/1/15 2008/1/15

3

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

Compal Electronics, Inc.

EXPRESS CARD

LA-4231P

0.1

28 49Thursday, January 10, 2008

1

of

C281

0.1U_0402_16V4Z~N

0.1U_0402_16V4Z~N

PCI_CLKRUN#19,40

KSI[0..7]31

KSO[0..15]31

BT_OFF#

ON_OFF31

PWR_BLUE_LED#24,31

NUMLED#31

R278

1 2

20M_0603_5%@

4

1

IN

OUT

NC3NC

2

1

2

GATEA2018
KB_RST#18
SERIRQ19
LPC_FRAME#18,24
LPC_AD318,24
LPC_AD218,24
LPC_AD118,24
LPC_AD018,24

CLK_PCI_EC16
PLT_RST#7,17,19,22,24,28,34

EC_SCI#19

EC_SMB_CK150
EC_SMB_DA150
EC_SMB_CK24,31,35
EC_SMB_DA24,31,35

SLP_S3#19
SLP_S5#19
EC_SMI#19

EC_PME#17
LAN_WOL_EN19
FAN_SPEED14

C297

15P_0402_50V8J

+3VALW

R405

10K_0402_5%

1 2

R414 0_0402_5%@

CB_PME#40

PCIE_PME#22

CLK_PCI_EC PLT_RST#

12

R272
10_0402_5%@

1

C282

@

15P_0402_50V8J

2

EC_SMB_DA1
EC_SMB_CK1

EC_SMB_DA2
EC_SMB_CK2
LCD_TST
LCD_CBL_DET#
MIC_DIAG
EC_FB_SDATA_R
EC_FB_SCLK_R

TP_DATA
TP_CLK

EC_MUTE

LID_SW#

1 2
1 2

R413 0_0402_5%

R263 4.7K_0402_5%
R262 4.7K_0402_5%

R264 4.7K_0402_5%
R265 4.7K_0402_5%
R269 4.7K_0402_5%@
R276 4.7K_0402_5%
R308 10K_0402_5%

1 2

R303 4.7K_0402_5%
R304 4.7K_0402_5%

For ENE

R271

10K_0402_5%

1 2
1 2

10K_0402_5%

R270

+3VALW

1 2

10K_0402_5%

R277

3

EC_PME#

+3VALW

0.1U_0402_16V4Z

12
12

12
12
12
12

12
12

+5VS

EC_FB_SCLK31

EC_FB_SDATA31

U1
APX9132ATI-TRL_SOT23-3

VDD

VOUT

GND

1

R228

1 2

47K_0402_5%

C268

+5VALW

+3VS

2

C292

+3VALW

2

1

R416 0_0402_5%

1 2

R417 0_0402_5%

1 2

XCLKO XCLKI

15P_0402_50V8J

X2

32.768KHZ_12.5P_1TJS125BJ2A251

REED Switch

C285

0.1U_0402_16V4Z~N

1

2

KSI[0..7]
KSO[0..15]

BT_OFF#

EC_FB_SCLK_R
EC_FB_SDATA_R

EC_TX_P80_DATA

T56PAD

EC_RX_P80_CLK

T57PAD

PWR_BLUE_LED#
NUMLED#

XCLKI
XCLKO

C277

1

2

GATEA20
KB_RST#
SERIRQ
LPC_FRAME#
LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0

CLK_PCI_EC
EC_RST#

EC_SCI#
PCI_CLKRUN#

KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7
KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14

KSO15

EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2

SLP_S3#
SLP_S5#
EC_SMI#
LID_SW#

EC_PME#
LAN_WOL_EN
FAN_SPEED1

ON_OFF

C493

0.1U_0402_16V4Z~N

C269

1000P_0402_50V7K~N

1

2

U29

1

GA20/GPIO00

2

KBRST#/GPIO01

3

SERIRQ#

4

LFRAME#

5

LAD3

7

LAD2

8

LAD1

10

LAD0

12

PCICLK

13

PCIRST#/GPIO05

37

ECRST#

20

SCI#/GPIO0E

38

CLKRUN#/GPIO1D

55

KSI0/GPIO30

56

KSI1/GPIO31

57

KSI2/GPIO32

58

KSI3/GPIO33

59

KSI4/GPIO34

60

KSI5/GPIO35

61

KSI6/GPIO36

62

KSI7/GPIO37

39

KSO0/GPIO20

40

KSO1/GPIO21

41

KSO2/GPIO22

42

KSO3/GPIO23

43

KSO4/GPIO24

44

KSO5/GPIO25

45

KSO6/GPIO26

46

KSO7/GPIO27

47

KSO8/GPIO28

48

KSO9/GPIO29

49

KSO10/GPIO2A

50

KSO11/GPIO2B

51

KSO12/GPIO2C

52

KSO13/GPIO2D

53

KSO14/GPIO2E

54

KSO15/GPIO2F

81

KSO16/GPIO48

82

KSO17/GPIO49

77

SCL1/GPIO44

78

SDA1/GPIO45

79

SCL2/GPIO46

80

SDA2/GPIO47

6

PM_SLP_S3#/GPIO04

14

PM_SLP_S5#/GPIO07

15

EC_SMI#/GPIO08

16

LID_SW#/GPIO0A

17

SUSP#/GPIO0B

18

PBTN_OUT#/GPIO0C

19

EC_PME#/GPIO0D

25

EC_THERM#/GPIO11

28

FAN_SPEED1/FANFB1/GPIO14

29

FANFB2/GPIO15

30

EC_TX/GPIO16

31

EC_RX/GPIO17

32

ON_OFF/GPIO18

34

PWR_LED#/GPIO19

36

NUMLED#/GPIO1A

122

XCLK1

123

XCLK0

KB926QFA1_LQFP128

1000P_0402_50V7K~N

1

2

LPC & MISC

ICH_PWROK
VGATE

C291

Int. K/B
Matrix

+3VALW +EC_AVCC

1

2

9

22

33

96

111

125

67

VCC

VCC

VCC

VCC

VCC

VCC

INVT_PWM/PWM1/GPIO0F

ACOFF/FANPWM2/GPIO13

PWM Output

BATT_TEMP/AD0/GPIO38

BATT_OVP/AD1/GPIO39

AD Input

DAC_BRIG/DA0/GPIO3C

EN_DFAN1/DA1/GPIO3D

DA Output

PS2 Interface

TP_CLK/PSCLK3/GPIO4E

TP_DATA/PSDAT3/GPIO4F

SPI Device Interface

SPI Flash ROM

FSTCHG/SELIO#/GPIO50

BATT_CHGI_LED#/GPIO52

GPIO

GPIO

BATT_LOW_LED#/GPIO54

VR_ON/XCLK32K/GPIO57

GPO

SM Bus

GPI

GND

GND

GND

GND

GND

11

24

35

69

94

113

1 2

R408 0_0402_5%

1 2

R407 0_0402_5%@

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

1000P_0402_50V7K~N

ECAGND

AVCC

BEEP#/PWM2/GPIO10

FANPWM1/GPIO12

ADP_I/AD2/GPIO3A

AD3/GPIO3B

AD4/GPIO42

SELIO2#/AD5/GPIO43

IREF/DA2/GPIO3E

DA3/GPIO3F

PSCLK1/GPIO4A
PSDAT1/GPIO4B
PSCLK2/GPIO4C

PSDAT2/GPIO4D

SDICS#/GPXOA00
SDICLK/GPXOA01

SDIDO/GPXOA02

SDIDI/GPXID0

SPIDI/RD#

SPIDO/WR#

SPICLK/GPIO58

SPICS#

CIR_RX/GPIO40

CIR_RLC_TX/GPIO41

CAPS_LED#/GPIO53
SUSP_LED#/GPIO55

SYSON/GPIO56

AC_IN/GPIO59

EC_RSMRST#/GPXO03
EC_LID_OUT#/GPXO04

EC_ON/GPXO05

EC_SWI#/GPXO06

ICH_PWROK/GPXO06

BKOFF#/GPXO08

WL_OFF#/GPXO09

GPXO10
GPXO11

PM_SLP_S4#/GPXID1

ENBKL/GPXID2

GPXID3
GPXID4
GPXID5
GPXID6
GPXID7

V18R

AGND

ECAGND

PM_PWROK 7,19

Issued Date

L18

12

C481

1

2

21
23
26
27

63
64
65
66
75
76

68
70
71
72

83
84
85
86
87
88

97
98
99
109

119
120
126
128

73
74
89
90
91
92
93
95
121
127

100
101
102
103
104
105
106
107
108

110
112
114
115
116
117
118

124

FBM-11-160808-601-T_0603

2

C482

0.1U_0402_16V4Z~N

1

R266 0_0402_5%

1 2

BEEP
W_DISABLE#
ACOFF

C273 0.01U_0402_16V7K

1 2

BATT_TEMP
BATT_OVP
ADP_I
AD_BID
MIC_DIAG
VGA_THER

DAC_BRIG
EN_DFAN1
IREF
M_PWROK_EC

1 2

R256 0_0402_5%

EC_MUTE
LCD_TST
VGA_ON
LCD_CBL_DET#
TP_CLK
TP_DATA

SPI_PULLDOWN
EN_WOL#

VGATE

FRD#SPI_SO
FWR#SPI_SI
SPI_CLK
FSEL#SPICS#

TOUCHKEY_TINT
MSEN#
FSTCHG
BATT_CHG_LED#
CAPSLED#
BATT_LOW_LED#
SCRLED#
SYSON
VR_ON
ACIN

EC_RSMRST#
EC_LID_OUT#
EC_ON
EC_SWI#
ICH_PWROK
BKOFF#
WL_OFF#
LCD_VCC_TEST_EN
PSID_DISABLE#

SLP_S4#
EC_ENBKL
USB_EN
EC_THERM#
SUSP#

PBTN_OUT#

PS_ID

C322 4.7U_0603_6.3V

1 2

0.1U_0402_16V4Z

C270

12

2007/1/15 2008/1/15

+3VALW+EC_AVCC

12

L19FBM-11-160808-601-T_0603

INVT_PWM 15
BEEP 25

W_DISABLE# 32

ACOFF 44

BATT_TEMP 50
BATT_OVP 50
ADP_I 44

MIC_DIAG 15
VGA_THER 34

DAC_BRIG 15
EN_DFAN1 4
IREF 44

EC_MUTE 26
LCD_TST 15
VGA_ON 47

LCD_CBL_DET# 15
TP_CLK 31
TP_DATA 31

R274 4.7K_0402_5%

12

EN_WOL# 22
VGATE 7,19,49

TOUCHKEY_TINT 31

MSEN# 15

FSTCHG 44

BATT_CHG_LED# 24

CAPSLED# 31

BATT_LOW_LED# 24

SCRLED# 31
SYSON 28,41,46
VR_ON 49
ACIN 19,43,44

EC_RSMRST# 19
EC_LID_OUT# 19
EC_ON 31
EC_SWI# 19

BKOFF# 15

WL_OFF# 24,32

LCD_VCC_TEST_EN 15

PSID_DISABLE# 43

SLP_S4# 19
EC_ENBKL 15
USB_EN 32

EC_THERM# 4,19

SUSP# 28,41,46,47,48

PBTN_OUT# 19

PS_ID 43

Compal Secret Data

Deciphered Date

ECAGND

CHGVADJ 44

TPM 1.2 Conn

C314

1 2

0.1U_0402_16V4Z~N

FRD#SPI_SO SPI_SO

PLT_RST#7,17,19,22,24,28,34

+3VS

+3VALW

+3VALW

R437

SPI_CS#FSEL#SPICS#

12

R439 15_0402_5%

1 2

R27515_0402_5%

LPC_FRAME#

SERIRQ

PCI_CLKRUN#

12mA

Board ID

M/B rev:0.1; 0.2; 0.3; 1.0
Voltage:0.0; 0.4; 0.8; 1.0

+3VALW

12

10K_0402_5%

JTPM1

1

GND1

3

IAC_SDATA_OUT

5

GND2

7

IAC_SYNC

9

IAC_SDATA_IN

11

IAC_RESET#

Title

Size Document Number Rev

Custom

Date: Sheet

20mils

U37

1

CS#

VCC

2

DO

HOLD#

3

WP#

CLK

4

GND

DIO

W25X80-VSSI-G_SO8

RES0
RES1

3.3V
GND3
GND4

IAC_BITCLK

GND13GND14GND15GND16GND17GND

18

Compal Electronics, Inc.

0.5A per each pin

BIOS & EC I/O Port

LA-4231P

+3VALW

2007-09-19 change Brd ID

R232
47K_0402_5%

Ra

1 2

Rb

1 2

SPI Flash connect

SPI_CS#
SPI_SO

E&T_2941-G08N-00E~D

SPI Flash (8Mb*1)

8
7
6
5

SPI_SI

LPC_AD0

2

LPC_AD1

4

LPC_AD2

6

LPC_AD3

8
10
12

ACES_88018-124L

R231
15K_0402_5%

JBIOS1

112
334
556
778

ME@

1 2
1 2

AD_BID

1

2

2
4
6
8

C507

@

1 2

0.1U_0402_16V4Z~N

29 49Thursday, January 10, 2008

C272

0.1U_0402_16V4Z

+3VALW

SPI_CLK_R
SPI_SI

SPI_CLK_R

SPI_CLKSPI_CLK_R

R42015_0402_5%

FWR#SPI_SI

R43815_0402_5%

CLK_PCI_TPM 16

of

0.1

A

+3VALW

Power Button

R297

1 2

D15

100K_0402_5%

1 1

EC_ON29

PWR_ON-OFF_BTN#

CHN202UPT SC-70

+3VALW

R296

4.7K_0402_5%

@

1 2

EC_ON

R291
0_0402_5%

1 2

2

1

2

G

3

13

D

Q26

SSM3K7002FU_SC70-3

S

51ON#

2

1

ON_OFF 29
51ON# 43

C313
1000P_0402_50V7K~N

12

B

D13
RLZ20A_LL34

C

INT_KBD CONN.

KSI[0..7]29

KSO[0..15]29

KSI[0..7]

KSO[0..15]

KSI0

1

KSI1

2

KSI2

3

KSI3

4

KSI4

5

KSI5

6

KSI6

7

KSI7

8

KSO0

9

KSO1

10

KSO2

11

KSO3

12

KSO4

13

KSO5

14

KSO6

15

KSO7

16

KSO8

17

KSO9

18

KSO10

19

KSO11

20

KSO12

21

KSO13

22

KSO14

23

KSO15

24
25
26

27
28

ACES_88514-2601

JKB1

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26

GND1
GND2

D

KSO8

C449 100P_0402_25V8K

KSI3

C239 100P_0402_25V8K

KSO9

C249 100P_0402_25V8K

KSI2

C240 100P_0402_25V8K

KSI1

C241 100P_0402_25V8K

KSO10

C248 100P_0402_25V8K

KSO11

C247 100P_0402_25V8K

KSI0

C242 100P_0402_25V8K

KSO12

C246 100P_0402_25V8K

KSO13

C245 100P_0402_25V8K

KSO14

C244 100P_0402_25V8K

KSO15

C243 100P_0402_25V8K

E

KSI7

C235 100P_0402_25V8K

KSI6

C236 100P_0402_25V8K

KSI5

C237 100P_0402_25V8K

KSO0

C441 100P_0402_25V8K

KSO1

C442 100P_0402_25V8K

KSO2

C443 100P_0402_25V8K

KSI4

C238 100P_0402_25V8K

KSO3

C444 100P_0402_25V8K

KSO4

C445 100P_0402_25V8K

KSO5

C446 100P_0402_25V8K

KSO6

C447 100P_0402_25V8K

KSO7

C448 100P_0402_25V8K

For EMI

Function/B CONN.

2 2

Regulator for ENE sensor

1U_0402_6.3V4Z

1

2

Adjustable Output

R901

1 2

10K_0603_1%

+5VS

C250

3 3

RT9198-33PBR SOT-23 5P

SHDN#3BP

2

GND

1

VIN

VOUT

U54

4

5

+3VS_FUN

ODD_ACT_LED#21

EC_FB_SDATA29

EC_FB_SCLK29

EC_SMB_DA24,29,35

EC_SMB_CK24,29,35

SATA_LED#18

SATA_LED#
ODD_ACT_LED#

For ENE

1 2

R611 0_0402_5%

1 2

R612 0_0402_5%

0_0402_5%@

1 2

R617
R618

2
1

R622 0_0402_5%

0_0402_5%

1 2

@

For Cypress

+3VS

C55

@

0.1U_0402_16V4Z

5

U33

P

B

4

Y

A

G

MC74VHC1G08DFT2G SC70 5P

3

1 2

@

12

IDE_ACT_LED#

+3VS

0_0603_5%

@

1 2

R880

LED_WLAN#24

BLUETOOTH_LED#32
PWR_BLUE_LED#24,29

TOUCHKEY_TINT29

NUMLED#29
CAPSLED#29
SCRLED#29

+3VALW

+3VS_FUN

PWR_ON-OFF_BTN#

LED_WLAN#

FB_SDATA

FN_SCLK
BLUETOOTH_LED#
PWR_BLUE_LED#

TOUCHKEY_TINT
NUMLED#
CAPSLED#
SCRLED#

@

12

C287

680P_0603_50V8J

IDE_ACT_LED#

1 2

R606 0_0402_5%

12

C286

@

C324 4.7U_0603_6.3V

1 2

JFN1

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

11

11

12

12

13

13

14

14

15

15

16

16

17

GND

18

GND

ACES_88512-1641

680P_0603_50V8J

Touch PAD/B CONN.

+5VS

1

TP_CLK29

C300

0.01U_0402_16V7K

4 4

TP_DATA29

2

TP/B TO M/B

TP_CLK
TP_DATA

1

1

@

@

C309100P_0402_25V8K

2

2

C310100P_0402_25V8K

2

3

1

ACES_88514-0441

6

G2

5

G1

4

4

3

3

2

2

1

1

JP1

D24
SM05T1G_SOT23-3~D

@

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2007/1/15 2008/1/15

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

D

Date: Sheet

Compal Electronics, Inc.

PWR_OK/BTN/TP

LA-4231P

E

31 49Thursday, January 10, 2008

0.1

of

0.1U_0402_16V4Z

0.1U_0402_16V4Z

C64

0.1U_0402_16V4Z

+3VS

USB20_N919
USB20_P919

C228

+5VALW

1

2

+5VS

USB20_N619
USB20_P619

1

2

+5VALW

1

C253

2

TP1

C315

10U_0805_10V4Z

80 mils

USB_EN#

80 mils

80 mils

USB_EN#

Fingerprint

JFP1

1

1

2

2

3

3

4

4

5

5

6

6

7

GND

8

GND

ACES_88512-0641

Felica Conn

USB20_N9
USB20_P9

LEC

1

2

USB_EN#

ACES_88512-0641

8

GND

7

GND

6

6

5

5

4

4

3

3

2

2

1

1

JFE1

U12

1

GND

2

IN

3

IN

4

EN#

RT9711PS SO 8P

U14

1

GND

2

IN

3

IN

4

EN#

RT9711PS SO 8P

1
2
3
4

CM1293-04SO_SOT23-6

1

2

3

D21

@

CH1

Vn

CH2

CH4

CH3

USB_EN29

OUT
OUT
OUT
OC#

OUT
OUT
OUT
OC#

U13

GND

OUT

IN

OUT
OUT

IN

OC#

EN#

RT9711PS SO 8P

USB20_N6

4

5

Vp

USB20_P6

6

8
7
6
5

8
7
6
5

USB_EN

8
7
6
5

+3VS

+USB_AS+5VALW

1

+

150U_B2_6.3VM_R45M

2

+USB_CS

1 2

R44 0_0402_5%

+USB_BS

+5VALW

R222
10K_0402_5%

1 2
13

D

2

G

S

0.1U_0402_16V4Z

C434

SUSP

USB20_P719
USB20_N719

CH_CLK24

BT_OFF#

CH_DATA24

BLUETOOTH_LED#31

USB_EN#

Q4
SSM3K7002FU_SC70-3

CH4

CH3

USB20_P0

USB20_N0

USB_P0

4

5

Vp

6

C223

USB_OC#0 19

USB_OC#3 19
USB_OC#2 19

SUSP40,41,48

USB_OC#1 19

SUSP

2

G

12

R154
100K_0402_5%

@

SUSP

12

R36
30K_0402_5%

13

D

Q8
SSM3K7002FU_SC70-3

S

2

G

12

R155
30K_0402_5%

13

D

Q14
SSM3K7002FU_SC70-3

S

12

13

D

2

G

S

R38
30K_0402_5%

Q13
SSM3K7002FU_SC70-3

USB20_P019

USB20_N019

CM1293-04SO_SOT23-6

1

CH1

2

Vn

3

CH2

D19

@

Bluetooth

JBT1

1

1

2

2

3

BT_ACTIVE

T62PAD

BT_OFF#

+3VS

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

11

GND

12

GND

ACES_88460-1001

2007/1/15 2008/1/15

Compal Secret Data

Deciphered Date

+USB_AS

USB_N0

+USB_BS

L1 WCM2012F2S-900T04_0805@

1

1

4

4

R1 0_0402_5%
R3 0_0402_5%

12
12

W=60mils

2

2

3

USB_P0
USB_N0

3

W=60mils

+USB_AS

Daughter board on right side

+USB_CS

W=80mils

USB20_N119
USB20_P119

USB20_N219
USB20_P219

USB20_N319
USB20_P319

W_DISABLE#29

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

USB/BlueTooth/FP/Felcia

LA-4231P

CONN@

ACES_87213-1200G

14

GND2

13

GND1

12

12

11

11

10

10

9

9

8

8

7

7

6

6

5

5

4

4

3

3

2

2

1

1

JP3

JUSBP2

1

GND

2

D+

3

D-

4

VCC

5

GND1

6

GND2

7

GND3

8

GND4

ALLTO_C10797-10403-L

32 49Thursday, January 10, 2008

0.1

of

5

4

3

2

1

PEG_NRX_GTX_P[0..15]9
PEG_NRX_GTX_N[0..15]9

PEG_NTX_GRX_P[0..15]9
PEG_NTX_GRX_N[0..15]9

D D

PEG_NRX_GTX_P0
PEG_NRX_GTX_N0
PEG_NRX_GTX_P1
PEG_NRX_GTX_N1
PEG_NRX_GTX_P2
PEG_NRX_GTX_N2
PEG_NRX_GTX_P3
PEG_NRX_GTX_N3
PEG_NRX_GTX_P4

C C

PEG_NRX_GTX_N4
PEG_NRX_GTX_P5
PEG_NRX_GTX_N5
PEG_NRX_GTX_P6
PEG_NRX_GTX_N6

PEG_NRX_GTX_N7
PEG_NRX_GTX_P8
PEG_NRX_GTX_N8
PEG_NRX_GTX_P9

PEG_NRX_GTX_P10
PEG_NRX_GTX_N10
PEG_NRX_GTX_P11
PEG_NRX_GTX_N11
PEG_NRX_GTX_P12
PEG_NRX_GTX_N12
PEG_NRX_GTX_P13
PEG_NRX_GTX_N13
PEG_NRX_GTX_P14
PEG_NRX_GTX_N14
PEG_NRX_GTX_P15
PEG_NRX_GTX_N15

B B

18P_0402_50V8J

PEG_NRX_GTX_P[0..15]
PEG_NRX_GTX_N[0..15]

PEG_NTX_GRX_P[0..15]
PEG_NTX_GRX_N[0..15]

C581 0.1U_0402_16V7KVGA@

1 2

C582 0.1U_0402_16V7KVGA@

1 2

C583 0.1U_0402_16V7K
C584 0.1U_0402_16V7K

1 2

C585 0.1U_0402_16V7KVGA@
C586 0.1U_0402_16V7KVGA@

1 2

C587 0.1U_0402_16V7KVGA@
C588 0.1U_0402_16V7KVGA@

1 2

C589 0.1U_0402_16V7KVGA@
C590 0.1U_0402_16V7KVGA@

1 2

C591 0.1U_0402_16V7KVGA@
C592 0.1U_0402_16V7KVGA@

1 2

C593 0.1U_0402_16V7KVGA@
C594 0.1U_0402_16V7KVGA@

1 2

C595 0.1U_0402_16V7KVGA@
C596 0.1U_0402_16V7KVGA@

1 2

C598 0.1U_0402_16V7KVGA@
C599 0.1U_0402_16V7KVGA@

1 2

C600 0.1U_0402_16V7KVGA@
C601 0.1U_0402_16V7KVGA@

1 2

C602 0.1U_0402_16V7KVGA@
C603 0.1U_0402_16V7KVGA@

1 2

C604 0.1U_0402_16V7KVGA@
C605 0.1U_0402_16V7KVGA@

1 2

C606 0.1U_0402_16V7KVGA@
C607 0.1U_0402_16V7KVGA@

1 2

C608 0.1U_0402_16V7KVGA@
C609 0.1U_0402_16V7KVGA@

1 2

C610 0.1U_0402_16V7KVGA@
C611 0.1U_0402_16V7KVGA@

1 2

C612 0.1U_0402_16V7KVGA@
C613 0.1U_0402_16V7KVGA@

1 2

4
1

1

C616

2

VGA@

VGA@

1 2

VGA@

1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2

CLK_PCIE_VGA16
CLK_PCIE_VGA#16

PLT_RST#7,17,19,22,24,28,29

Y5

27MHZ_16PF_X7T027000BG1H-V~D

VGA@

GND
IN

OUT
GND

3
2

PEG_NTX_GRX_P0
PEG_NTX_GRX_N0
PEG_NTX_GRX_P1
PEG_NTX_GRX_N1
PEG_NTX_GRX_P2
PEG_NTX_GRX_N2
PEG_NTX_GRX_P3
PEG_NTX_GRX_N3
PEG_NTX_GRX_P4
PEG_NTX_GRX_N4
PEG_NTX_GRX_P5
PEG_NTX_GRX_N5
PEG_NTX_GRX_P6
PEG_NTX_GRX_N6
PEG_NTX_GRX_P7
PEG_NTX_GRX_N7
PEG_NTX_GRX_P8
PEG_NTX_GRX_N8
PEG_NTX_GRX_P9
PEG_NTX_GRX_N9
PEG_NTX_GRX_P10
PEG_NTX_GRX_N10
PEG_NTX_GRX_P11
PEG_NTX_GRX_N11
PEG_NTX_GRX_P12
PEG_NTX_GRX_N12
PEG_NTX_GRX_P13
PEG_NTX_GRX_N13
PEG_NTX_GRX_P14
PEG_NTX_GRX_N14
PEG_NTX_GRX_P15
PEG_NTX_GRX_N15

CLK_PCIE_VGA
CLK_PCIE_VGA#

PLT_RST#

XTALIN

XTALOUT

1

C617
18P_0402_50V8J

2

VGA@

PEG_NRX_C_GTX_P0
PEG_NRX_C_GTX_N0
PEG_NRX_C_GTX_P1
PEG_NRX_C_GTX_N1
PEG_NRX_C_GTX_P2
PEG_NRX_C_GTX_N2
PEG_NRX_C_GTX_P3
PEG_NRX_C_GTX_N3
PEG_NRX_C_GTX_P4
PEG_NRX_C_GTX_N4
PEG_NRX_C_GTX_P5
PEG_NRX_C_GTX_N5
PEG_NRX_C_GTX_P6
PEG_NRX_C_GTX_N6
PEG_NRX_C_GTX_P7PEG_NRX_GTX_P7
PEG_NRX_C_GTX_N7
PEG_NRX_C_GTX_P8
PEG_NRX_C_GTX_N8
PEG_NRX_C_GTX_P9
PEG_NRX_C_GTX_N9PEG_NRX_GTX_N9
PEG_NRX_C_GTX_P10
PEG_NRX_C_GTX_N10
PEG_NRX_C_GTX_P11
PEG_NRX_C_GTX_N11
PEG_NRX_C_GTX_P12
PEG_NRX_C_GTX_N12
PEG_NRX_C_GTX_P13
PEG_NRX_C_GTX_N13
PEG_NRX_C_GTX_P14
PEG_NRX_C_GTX_N14
PEG_NRX_C_GTX_P15
PEG_NRX_C_GTX_N15

R550

1 2

12

R552
10K_0402_5%

@

U38A

AF1

PEX_RX0

AG2

PEX_RX0_N

AG3

PEX_RX1

AG4

PEX_RX1_N

AF4

PEX_RX2

AF5

PEX_RX2_N

AG6

PEX_RX3

AG7

PEX_RX3_N

AF7

PEX_RX4

AF8

PEX_RX4_N

AG9

PEX_RX5

AG10

PEX_RX5_N

AF10

PEX_RX6

AF11

PEX_RX6_N

AG12

PEX_RX7

AG13

PEX_RX7_N

AG15

PEX_RX8

AG16

PEX_RX8_N

AF16

PEX_RX9

AF17

PEX_RX9_N

AG18

PEX_RX10

AG19

PEX_RX10_N

AF19

PEX_RX11

AF20

PEX_RX11_N

AG21

PEX_RX12

AG22

PEX_RX12_N

AF22

PEX_RX13

AF23

PEX_RX13_N

AG24

PEX_RX14

AG25

PEX_RX14_N

AG26

PEX_RX15

AF27

PEX_RX15_N

AD5

PEX_TX0

AD6

PEX_TX0_N

AE6

PEX_TX1

AE7

PEX_TX1_N

AD7

PEX_TX2

AC7

PEX_TX2_N

AE9

PEX_TX3

AE10

PEX_TX3_N

AD10

PEX_TX4

AC10

PEX_TX4_N

AE12

PEX_TX5

AE13

PEX_TX5_N

AD13

PEX_TX6

AC13

PEX_TX6_N

AC15

PEX_TX7

AD15

PEX_TX7_N

AE15

PEX_TX8

AE16

PEX_TX8_N

AC18

PEX_TX9

AD18

PEX_TX9_N

AE18

PEX_TX10

AE19

PEX_TX10_N

AC21

PEX_TX11

AD21

PEX_TX11_N

AE21

PEX_TX12

AE22

PEX_TX12_N

AD22

PEX_TX13

AD23

PEX_TX13_N

AF25

PEX_TX14

AE25

PEX_TX14_N

AE24

PEX_TX15

AD24

PEX_TX15_N

AE3

PEX_REFCLK

AE4

PEX_REFCLK_N

AC6

PEX_RST_N

B1

XTALIN

C2

XTALOUT

C3

XTALOUTBUFF

C1

XTALSSIN

G72M_BGA533 VGA@

VGA@

22_0402_5%

12

R553
10K_0402_5%

@

Part 1 of 5

PCI EXPRESS

CLK

PEX_TSTCLK_OUT

PEX_TSTCLK_OUT_N

OSC_SPREAD
OSC_OUT

GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8

GPIO9
GPIO10
GPIO11
GPIO12

MIOBD0
MIOBD1
MIOBD2
MIOBD3
MIOBD4
MIOBD5
MIOBD6
MIOBD7
MIOBD8

DVO / GPIO

MIOBD9
MIOBD10
MIOBD11

MIOB_HSYNC
MIOB_VSYNC

MIOB_DE

MIOB_CTL3

MIOB_CLKIN

MIOB_CLKOUT

MIOB_CLKOUT_N

MIOB_VREF

DACA_HSYNC
DACA_VSYNC

DACA_RED

DACA_BLUE

DACA_GREEN

DACA_IDUMP

DACA_RSET
DACA_VREF

DACB_HSYNC
DACB_VSYNC

DACB_RED

DACB_BLUE

DACB_GREEN

DACsI2C

DACB_IDUMP

DACB_RSET
DACB_VREF

I2CA_SCL
I2CA_SDA
I2CB_SCL
I2CB_SDA
I2CC_SCL
I2CC_SDA
I2CH_SCL
I2CH_SDA

IFPAB_VPROBE
IFPCD_VPROBE

JTAG_TCK

JTAG_TDI
JTAG_TDO
JTAG_TMS

JTAG_TRST_N

TESTMODE

TEST

HDMI

A9
D9

NV_INVTPWM

A10

VGA_LVDDEN

B10

G7X_ENBKL

C10
C12
B12
A12
A13
B13
B15
A15
B16

G2
G3
J2
J1
K4
K1
M2
M1
N1
N2
N3
R3

PEX_CFG3

G4
F1
G1
F2

R537 10K_0402_5%

R2
K2
K3

J4

VGA_HSYNC

AD4

VGA_VSYNC

AC4

VGA_CRT_R

AE1

VGA_CRT_B

AD2

VGA_CRT_G

AD1
U9

DACA_RSET

AD3

DACAVREF

AB4

E6
F5
F4
D5
E4

R656 10K_0402_5%VGA@

L9

R648 10K_0402_5%VGA@

D6

R649 10K_0402_5%VGA@

E7

VGA_DDCCLK

D10

VGA_DDCDATA

E10

I2CB_SCL

F9

I2CB_SDA

F10

VGA_CLK_LCD

E9

VGA_DAT_LCD

D8
C7
B7

HDCP

N6
M5

AE27

PAD

AD27

PAD

AE26

PAD

AD26

PAD

AD25

PAD

D7
AF13

AF14

1 2

200_0402_5%@

R534 2K_0402_5%VGA@

THER_ALERT#

VGA_THER

R542

RAM_CFG0
RAM_CFG1

PCI_DEVID2
PCI_DEVID0
PCI_DEVID1

PCI_IOBAR

R535 2.2K_0402_5%

RAM_CFG2
RAM_CFG3

PCI_DEVID3

PCI_DEVID4

12

R538 124_0603_1%

VGA@

12
12

12

IFPAB_VPROBE

0.01U_0402_16V7K @

IFPCD_VPROBE

0.01U_0402_16V7K @

TP56
TP55
TP54
TP53
TP52

R616

PAD

T52

VGA_LVDDEN 15
G7X_ENBKL 15

1 2

THER_ALERT#

VGA_THER 29

12

10K_0402_5%VGA@

RAM_CFG0 37
RAM_CFG1 37

PCI_DEVID2 37
PCI_DEVID0 37
PCI_DEVID1 37

@

1 2

RAM_CFG2 37
RAM_CFG3 37

PCI_DEVID3 37
PEX_CFG3 37

PCI_DEVID4 37

VGA@

VGA_HSYNC 15
VGA_VSYNC 15
VGA_CRT_R 15
VGA_CRT_B 15
VGA_CRT_G 15

1 2

1 2

C597 0.01U_0402_16V7K

VGA@

VGA_DDCCLK 15
VGA_DDCDATA 15

VGA_CLK_LCD 15
VGA_DAT_LCD 15

C614

12

C615

12

R54910K_0402_5% VGA@

12

+3VS

For Internal Thermal
Sensor

+3VS

<---CRT

<---LVDS

VGA termination, close chip

VGA_CRT_R
VGA_CRT_G
VGA_CRT_B

R539 150_0402_1%VGA@

1 2

R540 150_0402_1%VGA@

1 2

R541 150_0402_1%VGA@

1 2

REF

PD#

+3VS

+3VS

5

VGA@

4

1 2

R554 22_0402_5%

3

NC

6

R142

VGA_CLK_LCD

VGA_DAT_LCD

I2CB_SCL

I2CB_SDA

+3VS

OSC_OUT OSC_SPREAD

VGA@

1 2

2.2K_0402_5%
R273

VGA@

1 2

2.2K_0402_5%

R284

2.2K_0402_5% VGA@

1 2

1 2

2.2K_0402_5%
R285

VGA@

External Spread Spectrum

C618 0.1U_0402_16V4Z

1 2

VGA@

U42

7

VDD

1

MODOUT

XIN

8

XOUT

2

VSS

ASM3P1819N-SR_SO8

VGA@

PCI_IOBAR

0

1

BAR2_SIZE

0

1

NB8M

Disable

Enable(Default)

NB8M

32Mb(Default)

16Mb

If External Spread Spectrum not stuff than stuff resistor

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

2006/07/10 2007/07/10

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

Compal Electronics, Inc.

NB8M-GS Main

34 49Thursday, January 10, 2008

1

0.1

of

5

4

3

2

1

FBAD[0..63]

D D

FBAD0
FBAD1
FBAD2
FBAD3
FBAD4
FBAD5
FBAD6
FBAD7
FBAD8
FBAD9
FBAD10
FBAD11
FBAD12
FBAD13
FBAD14
FBAD15

C C

B B

FBAD16
FBAD17
FBAD18
FBAD19
FBAD20
FBAD21
FBAD22
FBAD23
FBAD24
FBAD25
FBAD26
FBAD27
FBAD28
FBAD29
FBAD30
FBAD31
FBAD32
FBAD33
FBAD34
FBAD35
FBAD36
FBAD37
FBAD38
FBAD39
FBAD40
FBAD41
FBAD42
FBAD43
FBAD44
FBAD45
FBAD46
FBAD47
FBAD48
FBAD49
FBAD50
FBAD51
FBAD52
FBAD53
FBAD54
FBAD55
FBAD56
FBAD57
FBAD58
FBAD59
FBAD60
FBAD61
FBAD62
FBAD63

U38B

A26

FBAD0

C24

FBAD1

B24

FBAD2

A24

FBAD3

C22

FBAD4

A25

FBAD5

B25

FBAD6

D23

FBAD7

G22

FBAD8

J23

FBAD9

E24

FBAD10

F23

FBAD11

J24

FBAD12

F24

FBAD13

G23

FBAD14

H24

FBAD15

D16

FBAD16

E16

FBAD17

D17

FBAD18

F18

FBAD19

E19

FBAD20

E18

FBAD21

D20

FBAD22

D19

FBAD23

A18

FBAD24

B18

FBAD25

A19

FBAD26

B19

FBAD27

D18

FBAD28

C19

FBAD29

C16

FBAD30

C18

FBAD31

N26

FBAD32

N25

FBAD33

R25

FBAD34

R26

FBAD35

R27

FBAD36

T25

FBAD37

T27

FBAD38

T26

FBAD39

AB23

FBAD40

Y24

FBAD41

AB24

FBAD42

AB22

FBAD43

AC24

FBAD44

AC22

FBAD45

AA23

FBAD46

AA22

FBAD47

T24

FBAD48

T23

FBAD49

R24

FBAD50

R23

FBAD51

R22

FBAD52

T22

FBAD53

N23

FBAD54

P24

FBAD55

AA24

FBAD56

AA27

FBAD57

AA26

FBAD58

AB25

FBAD59

AB26

FBAD60

AB27

FBAD61

AA25

FBAD62

W25

FBAD63

G72M_BGA533 VGA@

FBAA[0..11]

FBBA[2..5]

FBADQS[0..7]

FBADQS#[0..7]

FBADQM#[0..7]

Part 2 of 5

FBA_CMD0
FBA_CMD1
FBA_CMD2
FBA_CMD3
FBA_CMD4
FBA_CMD5
FBA_CMD6
FBA_CMD7
FBA_CMD8

FBA_CMD9
FBA_CMD10
FBA_CMD11
FBA_CMD12
FBA_CMD13
FBA_CMD14
FBA_CMD15
FBA_CMD16
FBA_CMD17
FBA_CMD18
FBA_CMD19
FBA_CMD20
FBA_CMD21
FBA_CMD22
FBA_CMD23
FBA_CMD24
FBA_CMD25
FBA_CMD26

FBADQM0
FBADQM1
FBADQM2
FBADQM3
FBADQM4
FBADQM5
FBADQM6
FBADQM7

FBADQS_RN0
FBADQS_RN1
FBADQS_RN2
FBADQS_RN3
FBADQS_RN4
FBADQS_RN5
FBADQS_RN6
FBADQS_RN7

FBADQS_WP0
FBADQS_WP1
FBADQS_WP2
FBADQS_WP3
FBADQS_WP4
FBADQS_WP5
FBADQS_WP6
FBADQS_WP7

FB_VREF

FBA_CLK0

FBA_CLK0_N

FBA_CLK1

FBA_CLK1_N

FBA_CMD27

FBA_DEBUG

FBAD[0..63] 38

FBAA[0..11] 38

FBBA[2..5] 38

FBADQS[0..7] 38

FBADQS#[0..7] 38

FBADQM#[0..7] 38

G27
D25
F26
F25
G25
J25
J27
M26
C27
C25
D24
N27

FBA_RST_R

G24
J26
M27
C26
M25
D26
D27
K26
K25
K24
F27
K27
G26
B27
N24

D21
F22
F20
A21
V27
W22
V22
V24

A22
E22
F21
B21
V26
W23
V23
W27

B22
D22
E21
C21
V25
W24
U24
W26

A16
L24

K23
M22
N22
M23
M24

NC

K22

FBAA3
FBAA0
FBAA2
FBAA1
FBBA3
FBBA4
FBBA5
FBA_BA2
FBACS0#
FBAWE#
FBA_BA0
FBA_CKE

R560

FBBA2
CMD14
FBARAS#
FBAA11
FBAA10
FBA_BA1
FBAA8
FBAA9
FBAA6
FBAA5
FBAA7
FBAA4
FBACAS#

FBADQM#0
FBADQM#1
FBADQM#2
FBADQM#3
FBADQM#4
FBADQM#5
FBADQM#6
FBADQM#7

FBADQS#0
FBADQS#1
FBADQS#2
FBADQS#3
FBADQS#4
FBADQS#5
FBADQS#6
FBADQS#7

FBADQS0
FBADQS1
FBADQS2
FBADQS3
FBADQS4
FBADQS5
FBADQS6
FBADQS7

FB_VREF1

FBA_DEBUG

FBACS0# 38
FBAWE# 38
FBA_BA0 38

1 2

PAD

FBARAS# 38

FBA_BA1 38

FBACAS# 38

FBACLK0 38
FBACLK0# 38
FBACLK1 38
FBACLK1# 38

R568

1 2

0_0402_5%

@

FBA_RST

0_0402_5%VGA@
T54

FBA_RST

12

R571
10K_0402_5%

VGA@

15mil

C622

@

0.1U_0402_16V4Z

FBA_CKE 38

12

FBA_RST 38

R562
10K_0402_5%

VGA@

+1.8VS

12

R566
1K_0402_1%

@

12

1

2

R567
1K_0402_1%

@

FB_VREF1=0.5 x FBVDD

VGA_LVDSAC+15

VGA_LVDSAC-15
VGA_LVDSA0+15

VGA_LVDSA0-15

VGA_LVDSA1+15

VGA_LVDSA1-15

VGA_LVDSA2+15

VGA_LVDSA2-15

R564 1K_0402_5%@

R565 1K_0402_5%@

1 2

1 2

VGA_LVDSAC+
VGA_LVDSAC­VGA_LVDSA0+
VGA_LVDSA0­VGA_LVDSA1+
VGA_LVDSA1­VGA_LVDSA2+
VGA_LVDSA2-

HDMI

U38C

T4

IFPA_TXC

U4

IFPA_TXC_N

N4

IFPA_TXD0

N5

IFPA_TXD0_N

R5

IFPA_TXD1

R4

IFPA_TXD1_N

T5

IFPA_TXD2

T6

IFPA_TXD2_N

R6

IFPA_TXD3

P6

IFPA_TXD3_N

W5

IFPB_TXC

W6

IFPB_TXC_N

W3

IFPB_TXD4

W2

IFPB_TXD4_N

AA2

IFPB_TXD5

AA3

IFPB_TXD5_N

AB1

IFPB_TXD6

AA1

IFPB_TXD6_N

AB3

IFPB_TXD7

AB2

IFPB_TXD7_N

U6

IFPAB_RSET

V1

IFPC_TXC

W1

IFPC_TXC_N

T1

IFPC_TXD0

R1

IFPC_TXD0_N

T3

IFPC_TXD1

T2

IFPC_TXD1_N

V2

IFPC_TXD2

V3

IFPC_TXD2_N

J3

IFPCD_RSET

G72M_BGA533 VGA@

Part 3 of 5

LVDS/TMDS

MIO_A_HSYNC

NC

MIO_A_VDDQ_0
MIO_A_VDDQ_1
MIO_A_VDDQ_2

GENERAL

SERIAL

MIO_A_D0
MIO_A_D1
MIO_A_D2
MIO_A_D3
MIO_A_D4
MIO_A_D5
MIO_A_D6
MIO_A_D7
MIO_A_D8
MIO_A_D9

MIO_A_D10

I2CS_SDA
I2CS_SCL

NC_2
GPIO14
GPIO13

BUFRST_N

STEREO

SWAPRDY
THERMDN
THERMDP

ROM_SCLK

ROM_SI

ROM_SO

ROMCS_N

A2
B3
A3
D4
A4
B4
B6
P4
C6
G5
V4
C4
F11
F12
D12
E12
C13

F6
G6
J6

A6

F7
A7

C9
B9

D2
F3
D3
D1

EC_SMB_DA2
EC_SMB_CK2

PEX_PLL_TERM
SUB_VENDOR

PEX_CFG0
PEX_CFG1

PEX_CFG2

SLOT_CLOCK_CFG

+3VS

1

C621

VGA@

0.1U_0402_16V4Z

2

1 2

0

1

R561 2K_0402_5%VGA@

1 2

R572

10K_0402_5%VGA@

SHARE REFERENCE CLOCKSLOT_CLOCK_CFG

Disable

Enable(Default)

PEX_PLL_TERM 37
SUB_VENDOR 37

PEX_CFG0 37FBA_BA2 38
PEX_CFG1 37

PEX_CFG2 37

EC_SMB_DA2 4,29,31

EC_SMB_CK2 4,29,31

+3VS

MEMORY INTERFACE

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/07/10 2007/07/10

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

Compal Electronics, Inc.

NB8M-GS Memory

35 49Thursday, January 10, 2008

1

0.1

of

5

4

3

2

1

+VGA_CORE

+VGA_CORE

1

C624

VGA@

2

0.1U_0402_16V4Z

1

C650

VGA@

2

1

C657

VGA@
2

0.47U_0402_6.3V6K

1

2

0.1U_0402_16V4Z

1

C625

VGA@

2

0.47U_0402_6.3V6K

1

C651

VGA@

2

0.47U_0402_6.3V6K

1

C658

VGA@
2

0.47U_0402_6.3V6K

+NV_PLLVDD

1U_0805_10V7K

D D

1U_0805_10V7KVGA@

C C

1U_0603_10V4Z

B B

0.47U_0402_6.3V6K

C656

C666

VGA@

+VGA_CORE

C623

VGA@

C649

VGA@

0.47U_0402_6.3V6K

0.47U_0402_6.3V6K

1

2

+3VS

1

C667

VGA@

2

0.1U_0402_16V4Z

R574

1 2

0_0603_5%

VGA@

1

C626

VGA@

2

0.1U_0402_16V4Z

1

C652

VGA@

2

0.47U_0402_6.3V6K

1

C659

VGA@
2

0.022U_0402_16V7K

1

C670

C669

VGA@

VGA@
2

8mA

0.1U_0402_16V4Z

1

1

C628

C627

VGA@

VGA@

2

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

C635

C636

VGA@

VGA@

2

2

0.1U_0402_16V4Z

Average to place around +VGA_CORE
plane.

1

2

1

2

1

2

+VGA_CORE

1

C660
1U_0805_10V7K

2

VGA@

+NV_PLLVDD

+3VS

+1.8VS

U38D

J9

VDD_0

J10

VDD_1

J11

VDD_2

L12

VDD_3

L13

VDD_4

L15

VDD_5

L16

VDD_6

M9

VDD_7

M11

VDD_8

M12

VDD_9

M13

VDD_10

M14

VDD_11

M15

VDD_12

M16

VDD_13

M17

VDD_14

N9

VDD_15

N11

VDD_16

N17

VDD_17

R9

VDD_18

R11

VDD_19

R17

VDD_20

T9

VDD_21

T11

VDD_22

T12

VDD_23

T13

VDD_24

T14

VDD_25

T15

VDD_26

T16

VDD_27

T17

VDD_28

U12

VDD_29

U13

VDD_30

U15

VDD_31

U16

VDD_32

W13

VDD_33

W15

VDD_34

W16

VDD_35

W9

VDD_LP_0

W10

VDD_LP_1

W11

VDD_LP_2

W12

VDD_LP_3

F13

VDD33_0

F14

VDD33_1

J12

VDD33_2

J13

VDD33_3

J15

VDD33_4

J16

VDD33_5

E15

FBVTT_0

F15

FBVTT_1

F16

FBVTT_2

J17

FBVTT_3

J18

FBVTT_4

L19

FBVTT_5

N19

FBVTT_6

R19

FBVTT_7

U19

FBVTT_8

W19

FBVTT_9

D11

NC

G72M_BGA533 VGA@

Part 4 of 5

PEX_IOVDD_0
PEX_IOVDD_1
PEX_IOVDD_2
PEX_IOVDD_3
PEX_IOVDD_4
PEX_IOVDD_5
PEX_IOVDD_6

PEX_IOVDD_7
PEX_IOVDDQ_0
PEX_IOVDDQ_1
PEX_IOVDDQ_2
PEX_IOVDDQ_3
PEX_IOVDDQ_4
PEX_IOVDDQ_5
PEX_IOVDDQ_6
PEX_IOVDDQ_7
PEX_IOVDDQ_8
PEX_IOVDDQ_9

PEX_IOVDDQ_10
PEX_IOVDDQ_11
PEX_IOVDDQ_12
PEX_IOVDDQ_13
PEX_IOVDDQ_14
PEX_IOVDDQ_15
PEX_IOVDDQ_16
PEX_IOVDDQ_17
PEX_IOVDDQ_18

PEX_PLLAVDD
PEX_PLLDVDD

POWER

MIOB_VDDQ_0
MIOB_VDDQ_1
MIOB_VDDQ_2

MIOBCAL_PD_VDDQ

IFPA_IOVDD
IFPB_IOVDD
IFPC_IOVDD

IFPAB_PLLVDD

IFPCD_PLLVDD

DACA_VDD
DACB_VDD

PLLVDD

FBA_PLLAVDD

H_PLLVDD

FBCAL_PD_VDDQ

FBVDDQ_0
FBVDDQ_1
FBVDDQ_2
FBVDDQ_3
FBVDDQ_4
FBVDDQ_5
FBVDDQ_6
FBVDDQ_7
FBVDDQ_8
FBVDDQ_9

W17
W18
AB10
AB11
AB14
AB15
AB20
AB21
AA4
AB5
AB6
AB7
AB8
AB9
AB12
AB13
AB16
AB17
AB18
AB19
AC9
AC11
AC12
AC16
AC17
AC19
AC20

+PEX_PLLAVDD

Y6

+PEX_PLLDVDD

AA5
K5

K6
L6

J5

+IFPA_IOVDD

W4
Y4
L4

+IFPAB_PLLVDD

V5
M4

+DACA_VDD

AE2
F8

R292 10K_0402_5%

40mA

H4

40mA

D13
D14
D15

4700P_0402_25V7K

F17
F19
J19
J22
L22
M19
P22
T19
U22
Y22

1400mA

VGA@

+FBA_PLLAVDD

+H_PLLVDD

1 2

45.3_0402_1%~DVGA@

1

C674

VGA@

2

4700P_0402_25V7K

C629

VGA@

0.1U_0402_16V4Z

C640

VGA@

0.1U_0402_16V4Z

R113

1 2

10K_0402_5%
R116

1 2

10K_0402_5%VGA@

12

+PLLVDD

R573

1U_0402_6.3V4Z

1

C676

C675

VGA@

VGA@

2

0.1U_0402_16V4Z

1

C630

VGA@

2

0.1U_0402_16V4Z

1

C641

VGA@

2

0.1U_0402_16V4Z

1

C662

VGA@

2

VGA@

+1.8VS

1U_0402_6.3V4Z

1

1

C677

VGA@

2

2

4700P_0402_25V7K

1

C631

VGA@

2

1U_0402_6.3V4K

1

C642

VGA@

2

1U_0402_6.3V4K

+3VS

+1.8VS

1

C678

VGA@

2

22U_0805_6.3V4Z

1U_0402_6.3V4K

1

C632

VGA@

2

1U_0402_6.3V4K

1

C643

VGA@

2

1

C679

2

VGA@

1

2

1

2

4.7U_0603_6.3V

1

C646

VGA@

2

4.7U_0603_6.3V

1

C647

VGA@

2

+PEX_PLLAVDD

1

C653

VGA@

2

0.01U_0402_16V7K

0.1U_0402_16V4Z

+PEX_PLLDVDD

C663

VGA@

0.01U_0402_16V7K

+IFPA_IOVDD

1

C680

VGA@

2

470P_0402_50V7K

+IFPAB_PLLVDD

470P_0402_50V7K

4700P_0402_25V7K

+1.2VS

1

C654

VGA@

2

1

1

2

2

0.1U_0402_16V4Z

1

C681

VGA@

2

470P_0402_50V7K

4700P_0402_25V7K

1

C687

VGA@

2

+PEX_PLLAVDD_L

1

C655

VGA@

4.7U_0805_10V4Z

2

C664

VGA@

4700P_0402_25V7K

1

C671

VGA@

2

1

C688

VGA@

2

1

C672

VGA@

2

1

4.7U_0603_6.3V
C689

2

L37

VGA@

1 2

MBK1608121YZF_0603

L39

VGA@

1 2

MBK1608121YZF_0603

1

4.7U_0603_6.3V

VGA@

C673

2

L40

1 2

MBK1608121YZF_0603

VGA@

VGA@

+1.2VS

+1.8VS

+1.8VS

L43

+PLLVDD

30mA

L47

+1.2VS

VGA@

12

C702

VGA@

4.7U_0805_10V4Z

2006/07/10 2007/07/10

0.1U_0402_16V4Z

Compal Secret Data

1

1

C701

VGA@

2

2

470P_0402_50V7K

MBK1608121YZF_0603

1

2

+H_PLLVDD

C699

VGA@

0.1U_0402_16V4Z

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

4700P_0402_25V7K

1

C693

VGA@

2

+FBA_PLLAVDD

4700P_0402_25V7K

Deciphered Date

MBK1608121YZF_0603

1

C694

VGA@

2

MBK1608121YZF_0603

1

C703

VGA@

2

2

1

4.7U_0603_6.3V

VGA@

C695

2

L48

VGA@

1

C704

VGA@

2

2.2U_0603_6.3V6K

VGA@

12

+1.2VS

+1.2VS

12

+DACA_VDD

1

C690

VGA@

2

470P_0402_50V7K

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

NB8M-GS Power

4700P_0402_25V7K

1

C691

VGA@

2

1

MBK1608121YZF_0603

1

4.7U_0603_6.3V

VGA@

C692

2

36 49Thursday, January 10, 2008

L42

VGA@

+3VS

12

0.1

of

5

4

3

2

1

STRAPS PIN DESCRIPTION

U38E

B2

GND_0

B5

GND_1

B8

GND_2

B11

GND_3

B14

GND_4

B17

D D

C C

B B

B20
B23
B26

E2
E5

E8
E11
E14
E17
E20
E23
E26

H2

H6
H23
H26

J14

K9

K19

L2

L5
L11
L14
L17
L23
L26

N12
N13
N14
N15
N16

P2

P5

P9
P11
P12
P13
P14
P15
P16
P17
P19
P23
P26

R12
R13
R14
R15
R16

U2

U5
U11
U14

GND_5
GND_6
GND_7
GND_8
GND_9
GND_10
GND_11
GND_12
GND_13
GND_14
GND_15
GND_16
GND_17

GND_19
GND_20
GND_21
GND_22
GND_23
GND_24
GND_25
GND_26
GND_27
GND_28
GND_29
GND_30
GND_31
GND_32
GND_33
GND_34
GND_35
GND_36
GND_37
GND_38
GND_39
GND_40
GND_41
GND_42
GND_43
GND_44
GND_45
GND_46
GND_47
GND_48
GND_49
GND_50
GND_51
GND_52
GND_53
GND_54
GND_55
GND_56
GND_57
GND_58
GND_59

G72M_BGA533

VGA@

Part 5 of 5

GND

MIOBCAL_PU_GND

FBCAL_TERM_GND

IFPAB_PLLGND
IFPCD_PLLGND

PEX_PLLGND

FBA_PLLGND

FBCAL_PU_GND

GND_60
GND_61
GND_62
GND_63
GND_64
GND_65
GND_66
GND_67
GND_68
GND_69
GND_70
GND_71
GND_72
GND_73
GND_74
GND_75
GND_76
GND_77
GND_78
GND_79
GND_80
GND_81
GND_82
GND_83
GND_84
GND_85
GND_86
GND_87
GND_88
GND_89
GND_90
GND_91
GND_92
GND_93
GND_94

PLLGND

U17
U23
U26
V9
V19
W14
Y2
Y5
Y23
Y26
AC2
AC8
AC14
AC23
AC26
AD8
AD9
AD11
AD12
AD14
AD16
AD17
AD19
AD20
AC5
AF2
AF3
AF6
AF9
AF12
AF15
AF18
AF21
AF24
AF26

V6
M6

M3
AA6
H5

C15

E13
H22

VGA@
VGA@

R576

24.9_0402_1%

1 2

R605

PAD

12

40.2_0402_1%

SUB_VENDOR35

SUB_VENDOR

T53

SUB_VENDOR

MIO_A_D1

PEX_PLL_TERM MIO_A_D0

PEX_CFG[3:0]

MIOAD
[9,8,6]

VBIOS on card (pull high)
VBIOS with system BIOS (pull down)

PCI-E PLL termination

0---->Enable (Default)
1---->Disable

Recommended for G8x

MIOBD_HSYNC

SUB_VENDOR

R575 2K_0402_5%

1 2

VGA@

RAM_CFG[3:0]

MIOAD0
MIOAD1

0001 ---> Qimonda 16Mx32
0010 ---> Hynix 16Mx32
0011 ---> Samsung 16Mx32

MIOAD8
MIOAD9

0

1

N0 VIDEO BIOS ROM

BIOS ROM is present(Default)

RAM_CFG034
RAM_CFG134
RAM_CFG234
RAM_CFG334
PCI_DEVID034
PCI_DEVID134
PCI_DEVID234
PCI_DEVID334
PCI_DEVID434
PEX_CFG035
PEX_CFG135
PEX_CFG235
PEX_CFG334
PEX_PLL_TERM35

RAM_CFG0
RAM_CFG1
RAM_CFG2
RAM_CFG3
PCI_DEVID0
PCI_DEVID1
PCI_DEVID2
PCI_DEVID3
PCI_DEVID4
PEX_CFG0
PEX_CFG1
PEX_CFG2
PEX_CFG3
PEX_PLL_TERM

+3VS

10K_0402_5%

12

R577

VGA@

12

R591

@

10K_0402_5%

10K_0402_5%

12

12

R578

VGA@

12

12

R592

@

VIPD[5:3]PCI_DEVID[3:0] G72M-0x01D8
MIOA_HSYNC

2K_0402_5%

10K_0402_5%

12

12

12

R580

@

R594

VGA@

R581

VGA@

R579

@

R593

VGA@

2K_0402_5%

12

R582

VGA@

G73M-xxxx8
NB8M-GS : 0X0427

NB8M-SE : 0X0428
G72MV-0x01D7

TBD/TBD

R583

VGA@

2K_0402_5%

12

R584

@

2K_0402_5%

2K_0402_5%

12

12

R585

@

2K_0402_5%

2K_0402_5%

12

R586

VGA@

12

R587

@

2K_0402_5%

2K_0402_5%

12

R588

@

2K_0402_5%

12

R589

@

12

R590

@

Value

0

0

0001

0011

0111
1000
0111

Value

10K_0402_5%

A A

5

FULL 32M

4

R17
R12HALF

RAM TypeBandwidth

16M

R11
R16

Vendor
Samsung
Hynix
Infineon

R20, R19
R18, R19

R18, R21

(10*12.5)
(11*13)
(8*13)

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Infineon GDDR2(400): SA00000S800 (HYB18T256161AFL-25)
Samsung GDDR2 (400): SA00000FG10 (K4N56163QF-ZC25)
Hynix GDDR2 (400): SA00000FF10 (HY5PS561621AFP-25) Hynix GDDR2 (350): SA00000TJ00 (HY5PS561621AFP-28)

2006/07/10 2007/07/10

3

Compal Secret Data

Package

10K_0402_5%

10K_0402_5%

Deciphered Date

10K_0402_5%

2

Infineon GDDR2(350): SA00000T700 (HYB18T256161AF-28)
Samsung GDDR2 (350): SA00000TB00 (K4N56163QF-ZC2A)

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

NB8M-GS GND & STRAP

37 49Thursday, January 10, 2008

1

of

0.1

5

+1.8VS

12

R908

1.05K_0402_1%

VGA@

12

R912

+1.8VS

12

12

2.49K_0402_1%

VGA@

R917

1.05K_0402_1%

VGA@

R918

2.49K_0402_1%

VGA@

D D

C C

B B

+VREFA2
+VREFA0

1

C886

0.01U_0402_16V7K

VGA@

2

+VREFA3
+VREFA1

1

C887

0.01U_0402_16V7K

VGA@

2

FBARAS#35
FBACAS#35
FBAWE#35
FBACS0#35

FBA_CKE35

1 2

R919 243_0402_1%

VGA@

FBA_RST35

+1.8VS

FBAA0
FBAA1
FBAA2
FBAA3
FBAA4
FBAA5
FBAA6
FBAA7
FBAA8
FBAA9
FBAA10
FBAA11
FBA_BA0
FBA_BA1

FBADQM#0
FBADQM#2
FBADQM#3
FBADQM#1

FBADQS0
FBADQS2
FBADQS3
FBADQS1

+VREFA0
+VREFA1

FBARAS#
FBACAS#
FBAWE#
FBACS0#

FBA_CKE
FBACLK0
FBACLK0#

FBADQS#0
FBADQS#2
FBADQS#3
FBADQS#1

FBA_RST
FBA_BA2

B12

U51

VSSQB1VSSQB4VSSQB9VSSQ

A0
A1
A2
A3
A4
A5
A6
A7
A8/AP
A9
A10
A11
BA0
BA1

DM0
DM1
DM2
DM3

WDQS0
WDQS1
WDQS2
WDQS3

VREF
VREF
RFU1
RFU2

RAS#
CAS#
WE#
CS#

CKE
CK
CK#

ZQ
MF

RDQS0
RDQS1
RDQS2
RDQS3

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

SEN
RESET
BA2

VSSA
VSSA

VSSQD1VSSQD4VSSQD9VSSQ

K4

H2

K3

M4

K9

H11

K10

L9

K11

M9

K2

L4
G4
G9

E3

E10

N10

N3
D2

D11

P11

P2
H1

H12

J2

J3
H3

F4
H9

F9
H4

J11
J10

A4

A9
D3

D10

P10

P3

A2

A11

F1

F12

M1

M12

V2

V11

V4

V9

H10

J1

J12

D12

VSSA3VSS

G11

VSSQG2VSSQ

VSSG1VSS

A10

L11

VSSQL2VSSQ

VSSL1VSS

G12

4

VSSQP1VSSQP4VSSQP9VSSQ

VSSV3VSS

L12

P12

T12

VSSQT1VSSQT4VSSQT9VSSQ

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8

DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

VDDA
VDDA

K4J52324QE-BC14_FBGA136~D

VGA@

V10

FBAD1

B2

FBAD3

B3

FBAD2

C2

FBAD5

C3

FBAD7

E2

FBAD4

F3

FBAD0

F2

FBAD6

G3

FBAD16

B11

FBAD17

B10

FBAD18

C11

FBAD19

C10

FBAD20

E11

FBAD21

F10

FBAD22

F11

FBAD23

G10

FBAD27

M11

FBAD25

L10

FBAD24

N11

FBAD26

M10

FBAD31

R11

FBAD28

R10

FBAD30

T11

FBAD29

T10

FBAD10

M2

FBAD12

L3

FBAD9

N2

FBAD15

M3

FBAD8

R2

FBAD13

R3

FBAD11

T2

FBAD14

T3

A1
A12
C1
C4
C9
C12
E1
E4
E9
E12
J4
J9
N1
N4
N9
N12
R1
R4
R9
R12
V1
V12

K1
K12

C889

0.1U_0402_16V4Z

VGA@

+1.8VS

+1.8VS

1

2

1

C890

0.1U_0402_16V4Z

2

VGA@

3

1 2

R920 243_0402_1%

VGA@

+1.8VS

FBAA0
FBAA1
FBBA2
FBBA3
FBBA4
FBBA5
FBAA6
FBAA7
FBAA8
FBAA9
FBAA10
FBAA11
FBA_BA0
FBA_BA1

FBADQM#5
FBADQM#4
FBADQM#6
FBADQM#7

FBADQS5
FBADQS4
FBADQS6
FBADQS7

+VREFA2
+VREFA3

FBARAS#
FBACAS#
FBAWE#
FBACS0#

FBA_CKE
FBACLK1
FBACLK1#

FBADQS#5
FBADQS#4
FBADQS#6
FBADQS#7

FBA_RST
FBA_BA2

H11
K10

K11

E10
N10

D11
P11

H12

D10
P10

A11
F12
M12
V11

H10

U52

H2
M4

M9

G4
G9

N3
D2

H1

H3
H9

H4
J11
J10

D3

M1

J12

K4
K3
K9

L9

K2
L4

E3

P2

J2
J3

F4
F9

A4
A9

P3
A2
F1

V2

V4
V9

J1

VSSQB1VSSQB4VSSQB9VSSQ

A0
A1
A2
A3
A4
A5
A6
A7
A8/AP
A9
A10
A11
BA0
BA1

DM0
DM1
DM2
DM3

WDQS0
WDQS1
WDQS2
WDQS3

VREF
VREF
RFU1
RFU2

RAS#
CAS#
WE#
CS#

CKE
CK
CK#

ZQ
MF

RDQS0
RDQS1
RDQS2
RDQS3

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

SEN
RESET
BA2

VSSA
VSSA

B12

VSSQD1VSSQD4VSSQD9VSSQ

D12

VSSA3VSS

G11

VSSQG2VSSQ

A10

VSSQL2VSSQ

VSSG1VSS

G12

L11

VSSQP1VSSQP4VSSQP9VSSQ

VSSL1VSS

L12

VSSV3VSS

2

P12

T12

VSSQT1VSSQT4VSSQT9VSSQ

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8

DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

VDDA
VDDA

K4J52324QE-BC14_FBGA136~D

VGA@

V10

FBAD40

B2

FBAD41

B3

FBAD42

C2

FBAD43

C3

FBAD44

E2

FBAD45

F3

FBAD46

F2

FBAD47

G3

FBAD35

B11

FBAD34

B10

FBAD32

C11

FBAD33

C10

FBAD39

E11

FBAD36

F10

FBAD37

F11

FBAD38

G10

FBAD51

M11

FBAD48

L10

FBAD53

N11

FBAD50

M10

FBAD52

R11

FBAD49

R10

FBAD54

T11

FBAD55

T10

FBAD59

M2

FBAD57

L3

FBAD61

N2

FBAD62

M3

FBAD60

R2

FBAD63

R3

FBAD56

T2

FBAD58

T3

A1
A12
C1
C4
C9
C12
E1
E4
E9
E12
J4
J9
N1
N4
N9
N12
R1
R4
R9
R12
V1
V12

K1
K12

C891

0.1U_0402_16V4Z

VGA@

+1.8VS

+1.8VS

1

2

1

C892

0.1U_0402_16V4Z

2

VGA@

1

FBAD[0..63]35
FBADQS#[0..7]35
FBADQS[0..7]35
FBADQM#[0..7]35

FBAA[0..11]35

FBBA[2..5]35

FBA_BA035
FBA_BA135
FBA_BA235

FBAD[0..63]
FBADQS#[0..7]
FBADQS[0..7]
DQMA#[0..7]
FBAA[0..11]
FBBA[2..5]

FBA_BA0
FBA_BA1
FBA_BA2

+1.8VS

0.01U_0402_16V7K

1

C895

VGA@

2

0.01U_0402_16V7K

FBACLK0#

1

2

1

C894

VGA@

2

1000P_0402_50V7K

FBACLK035

A A

FBACLK0#35

5

GDDR3 BGA MEMORY GDDR3 BGA MEMORY

0.1U_0402_16V4Z

1

C896

VGA@

2

FBACLK0

12

1

C898

C897

VGA@

VGA@

2

0.1U_0402_16V4Z

R607
243_0402_1%

VGA@

0.1U_0402_16V4Z

1

C899

VGA@

2

0.1U_0402_16V4Z

4

1U_0402_6.3V4Z

1

C900

VGA@

2

1

C901

VGA@

2

1U_0402_6.3V4Z

10U_0805_10V4Z

1

C902

VGA@

2

1

C903

VGA@

2

22U_0805_6.3V6M

1

C904

VGA@

2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2007/02/12

+1.8VS

0.01U_0402_16V7K

1

C905

VGA@

2

1000P_0402_50V7K

FBACLK135

FBACLK1#35

Compal Secret Data

Deciphered Date

1

C906

VGA@

2

0.01U_0402_16V7K

0.1U_0402_16V4Z

1

C907

VGA@

2

FBACLK1

FBACLK1#

1

C908

VGA@

2

0.1U_0402_16V4Z

2

1

2

12

R610
243_0402_1%

VGA@

2008/02/12

0.1U_0402_16V4Z

1

C909

C910

VGA@

VGA@

2

0.1U_0402_16V4Z

1U_0402_6.3V4Z

1

1

C911

C912

VGA@

VGA@

2

2

Title

Size Document Number Rev

Thursday, January 10, 2008

Date: Sheet

10U_0805_10V4Z

1

1

C913

VGA@

2

1U_0402_6.3V4Z

C914

VGA@

2

22U_0805_6.3V6M

1

2

C915

VGA@

Compal Electronics, Inc.

VRAM GDDR3 A

LA-4231P

1

38 49

of

0.1

5

R666

R832

C823

@

@

Q35

AO3413_SOT23

S

G

2
1

C1186

2

CLK_PCI_CB

10_0402_5%~D

12

4.7P_0402_50V8C

1

2

R691

1 2

100_0402_5%

PCI_CLKRUN#19,29

D

13

0.01U_0402_25V7K~N
C1136

PCI_AD[0..31]17

PCI_DEVSEL#17
PCI_FRAME#17

PCI_PIRQG#17

+1.8VS_CB

4.7U_0805_10V4Z

0.1U_0402_10V6K

0.1U_0402_10V6K

1

1

C1137

C1138

2

12

56.2_0402_1%

12

12

56.2_0402_1%

12

12

270P_0402_50V7K

2

1

1 2

C1141

PCI_AD31
PCI_AD30
PCI_AD29
PCI_AD28
PCI_AD27
PCI_AD26
PCI_AD25
PCI_AD24
PCI_AD23
PCI_AD22
PCI_AD21
PCI_AD20
PCI_AD19
PCI_AD18
PCI_AD17
PCI_AD16
PCI_AD15
PCI_AD14
PCI_AD13
PCI_AD12
PCI_AD11
PCI_AD10
PCI_AD9
PCI_AD8
PCI_AD7
PCI_AD6
PCI_AD5
PCI_AD4
PCI_AD3
PCI_AD2
PCI_AD1
PCI_AD0

PCI_CBE#3
PCI_CBE#2
PCI_CBE#1
PCI_CBE#0

CBS_IDSELPCI_AD21
CLK_PCI_CB
PCI_DEVSEL#
PCI_FRAME#
PCI_IRDY#
PCI_TRDY#
PCI_STOP#
PCI_PAR
PCI_REQ0#
PCI_GNT0#
PCI_RST#
PCI_PIRQG#
CB_PME#

56.2_0402_1%

R831

56.2_0402_1%

R834

5.1K_0402_1%

R835

2

PCI_CBE#317
PCI_CBE#217
PCI_CBE#117
PCI_CBE#017

CLK_PCI_CB16

PCI_IRDY#17
PCI_TRDY#17
PCI_STOP#17

PCI_PAR17

PCI_REQ0#17

PCI_GNT0#17
PCI_RST#17,21

CB_PME#29

R850 100K_0402_5%@
R693 0_0402_5%~D

1 2

LED behave:
Idel ---------> low
Accress data --> always high

IEEE1394_TPBIAS0

R830

R833

C824

+3VS

IEEE1394_TPAP0
IEEE1394_TPAN0

IEEE1394_TPBP0
IEEE1394_TPBN0

+1.8V

SUSP32,41,48

D D

C C

B B

A A

1 2

100K_0402_5%

5

4.7U_0805_10V4Z

0.1U_0402_10V6K

1

C1142

2

1U_0603_10V4Z

1

C821

2

4

125

120

91

VCC1.814VCC1.8

VCC1.8

VCC1.8

VCC1.892VCC1.8

OZ129

GND

GND

GND

GND

GND

GND

124

123

121

116

115

104

J139A1

4

TPA+

GND

3

TPA-

GND

2

TPB+

GND

1

TPB-

GND

SUYIN_020204FR004S506ZL~D

conn@

7

103

102

VCC3.3

VCC3.3

82

5
6
7
8

122

VCC3.3

VCC3.3

SD_CLK/MS_CLK

MS_D1/XD_D7

MS_BS/XD_D3
MS_D0/XD_D2
MS_D2/XD_D1
MS_D3/XD_D0

AGND

AGND

AGND

80

77

106

19
20
21
22
23
24
25
27
29
30
31
32
34
35
36
37
47
48
49
50
51
52
53
54
57
58
59
60
61
62
63
64

28
38
46
55

5
45
42
39
40
41
43
44
17
18

1
11

3

6

U46

AD31
AD30
AD29
AD28
AD27
AD26
AD25
AD24
AD23
AD22
AD21
AD20
AD19
AD18
AD17
AD16
AD15
AD14
AD13
AD12
AD11
AD10
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0

C/BE3#
C/BE2#
C/BE1#
C/BE0#

IDSEL
PCI_CLK
DEVSEL#
FRAME#
IRDY#
TRDY#
STOP#
PAR
PCI_REQ#
PCI_GNT#
PCI_RST#
INTA#
PME#
CLKRUN#

MEDIA_LED

15

26

56

PCI_VCC

PCI_VCC

GND

GND

GND

GND

GND

12

16

33

68

66

Layout Note: Place close to OZ129 Chipset.

4

+3VS_PHY

81

79

73

67

AVCC

AVCC

AVCC

AVCC

78

REF

83

XI

84

XO

76

TPBIAS

75

TPA+

74

TPA-

72

TPB+

71

TPB-

4

MC_3V#

113
111

SD_D3

112

SD_D2

107

SD_D1

108

SD_D0

110

SD_CMD

117

SD_WP

114

SD_CD#

95
93

XD_D6

89

XD_D5

87

XD_D4

88
90
94
96
119

XD_CE#

100

XD_RB#

118

XD_CLE

109

XD_ALE

105

XD_WE#

101

XD_RE#

98

XD_WPO#

99

MS_CD#

97

XD_CD#

85

PHY_TEST0

86

PHY_TEST1

2

NC

8

NC

9

NC

10

NC

13

NC

126

NC

127

NC

128

NC

AGND70AGND

AGND

OZ129TN_LQFP128_14X14

69

65

0_0603_5%

1 2

R879

3

+3VS

4.7U_0805_10V4Z

0.1U_0402_10V6K

1

C1139

C1140

2

R520 5.9K_0402_1%

1 2

OZ129XI
OZ129XO

IEEE1394_TPBIAS0
IEEE1394_TPAP0
IEEE1394_TPAN0
IEEE1394_TPBP0
IEEE1394_TPBN0

MC_3V#
SDCLK_MSCLK
SDD3
SDD2
SDD1
SDD0
SD_CMD
SD_WP
SDCD#

XDD7_MSD1
XD_D6
XD_D5
XD_D4
XDD3_MSBS
XDD2_MSD0
XDD1_MSD2
XDD0_MSD3
XDCE#
XDRB#
XDCLE
XDALE
XDWE#
XDRE#
XDWP#
MSCD#
XDCD#

MMCD4
MMCD5

MMCD6
MMCD7

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

+3VS

R942
22K_0402_5%

MC_3V#

XDD0_MSD3

R873 0_0402_5%~D

XDD1_MSD2

R874 0_0402_5%~D

XDD2_MSD0

R938 0_0402_5%~D

XDD3_MSBS

R948 0_0402_5%~D

XD_D4

R957 0_0402_5%~D

XD_D5

R964 0_0402_5%~D

XD_D6

R941 0_0402_5%~D

XDD7_MSD1

R951 0_0402_5%~D

XDWE#

R960 0_0402_5%~D

XDWP#

R967 0_0402_5%~D

XDALE

R945 0_0402_5%~D

XDCD#

R955 0_0402_5%~D

XDRB#

R952 0_0402_5%~D

XDRE#

R961 0_0402_5%~D

XDCE#

R936 0_0402_5%~D

XDCLE

R946 0_0402_5%~D

2007/09/01 2008/09/01

+3VS

Layout Note: Place close to
OZ129 and Shield GND.

15P_0402_50V8J

15P_0402_50V8J

+3VS

S

G

Q81

2

AO3413_SOT23-3

D

1 3

1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2

1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2

Compal Secret Data

Deciphered Date

C819

C822

2

0_0603_5%

1 2

R878

12

X3

24.576MHz_16P_1BG24576CKIA~D

1 2

12

+3VS_CR

1

C878

1U 10V Z Y5V 0603

2

+3VS_CR +3VS_CR

3

XDD0

32

XDD1

10

XDD2

9

XDD3

8

XDD4

7

XDD5

6

XDD6

5

XDD7

4

XDWE

34

XDWP

33

XD_ALE

35

XDCD

40

XDRB

39

XDRE

38

XDCE

37

XD_CLE

36

11
31
41
42

2

OZ129XI

OZ129XO

Q82

JSD1

XD-VCC
XD-D0

XD-D1
XD-D2
XD-D3
XD-D4
XD-D5
XD-D6
XD-D7

XD-WE
XD-WP
XD-ALE
XD-CD
XD-R/B
XD-RE
XD-CE
XD-CLE

7in1-GND
7in1-GND
7in1-GND
7in1-GND

TAITW_R015-A10-LM

0.1U_0402_10V6K

1

C922

2

12

R932
470_0402_5%

13

D

2

G

SSM3K7002FU_SC70-3

S

7 IN 1 CONN

1

+3VS_PHY

4.7U_0805_10V4Z

0.1U_0402_10V6K

1

C925

C926

2

+3VS_CR

1

1

C1187

1U 10V Z Y5V 0603

MC_3V#

SD-VCC
MS-VCC

SD_CLK
SD-DAT0
SD-DAT1
SD-DAT2
SD-DAT3
SD-DAT4
SD-DAT5
SD-DAT6
SD-DAT7

SD-CD

SD-WP

SD-CMD
MS-SCLK

MS-BS

MS-INS

MS-DATA0
MS-DATA1
MS-DATA2
MS-DATA3

Title

OZ129_Card Reader / 1394

Size Document Number Rev

Custom

LA-4131P

Date: Sheet

2

21
28

SDCLK

20

SDDAT0

14

SDDAT1

12

SDDAT2

30

SDDAT3

29

SDDAT4

27

SDDAT5

23

SDDAT6

18

SDDAT7

16

SDCD

1

SDWP

2

SDCMD

25

MSCLK

26

MSBS

13

MSINS

22

MSDATA0

17

MSDATA1

15

MSDATA2

19

MSDATA3

24

Compal Electronics, Inc.

C1188
1U 10V Z Y5V 0603

2

R713 22_0402_5%

1 2

R940 0_0402_5%~D

1 2

R950 0_0402_5%~D

1 2

R959 0_0402_5%~D

1 2

R966 0_0402_5%~D

1 2

R944 0_0402_5%~D

1 2

R953 0_0402_5%~D

1 2

R962 0_0402_5%~D

1 2

R937 0_0402_5%~D

1 2

R947 0_0402_5%~D

1 2

R956 0_0402_5%~D

1 2

R963 0_0402_5%~D

1 2

R714 22_0402_5%

1 2

R939 0_0402_5%~D

1 2

R949 0_0402_5%~D

1 2

R958 0_0402_5%~D

1 2

R965 0_0402_5%~D

1 2

R943 0_0402_5%~D

1 2

R954 0_0402_5%~D

1 2

40 40Thursday, January 10, 2008

1

SDCLK

C1146

10P_0402_50V8J

@

MSCLK

C1149

10P_0402_50V8J

@

SDCLK_MSCLK
SDD0
SDD1
SDD2
SDD3
MMCD4
MMCD5
MMCD6
MMCD7

SDCD#
SD_WP
SD_CMD

SDCLK_MSCLK
XDD3_MSBS
MSCD#

XDD2_MSD0
XDD7_MSD1
XDD1_MSD2
XDD0_MSD3

of

1

2

1

2

0.1

A

B

C

D

E

+5VALW to +5VS Transfer+3VALW to +3VS Transfer

C264

1

S

2

S

3

S

4

G

SYSON

+3VS+3VALW

10U_0805_10V4Z~N

1

C465

2

0.1U_0402_16V4Z~N

+3VALW

R409

100K_0402_5%

SYSON#

2

G

R365
10K_0402_5%

1 2

1

C256

2

12

13

D

Q42
SSM3K7002FU_SC70-3

S

U39

8

S

D

7

S

D

6

1

C278

2

10U_0805_10V4Z~N

RUNON 5VS_GATE

D

5

D

SI4800DY_SO8

1 2

R267
47K_0402_5%

+CPU_CORE

S
G

1

2

B+_BIAS

12

R198

330K_0402_5%

1 1

SUSP

2

G

2 2

1

2

RUNON 3VS_GATE

13

D

Q18

SSM3K7002FU_SC70-3

S

U40

8

D

7

D

6

D

5

D

C271

SI4800DY_SO8

10U_0805_10V4Z~N

1 2

R197
100K_0402_5%

SYSON28,29,46

1

0.01U_0402_25V7K~N

2

+5VS+5VALW

1
2
3
4

C279

0.01U_0402_25V7K~N

C211 0.1U_0402_16V4Z~N

1 2

1

C284

2

0.1U_0402_16V4Z~N

1

C283
10U_0805_10V4Z~N

2

+VCCP

+1.8V to +1.8VS Transfer

VGA_PWGOD#

SUSP

R665

1 2

0_0402_5%@

B+_BIAS

VGA@

2

G

1

R559

C727

1 2

2

10U_0805_10V4Z~N

47K_0402_5%

VGA@

1.8VS ON 1.8VS_GATE

1 2

R608
100K_0402_5%

VGA@

13

D

Q48

SSM3K7002FU_SC70-3

S

VGA@

U41

8

D

7

D

6

D

5

D

SI4800DY_SO8

VGA@

1

C696

0.01U_0402_25V7K~N

2

VGA@

1

S

2

S

3

S

4

G

+1.8VS+1.8V

10U_0805_10V4Z~N

1

C728

0.1U_0402_16V4Z~N

2

VGA@

4.7A

1

2

C697

VGA@

+5VALW

12

2

G

R338
10K_0402_5%

1 2

+3VALW

R668

2

G

VGA@

R340
100K_0402_5%

13

D

Q32
SSM3K7002FU_SC70-3

S

12

13

D

Q49
SSM3K7002FU_SC70-3

S

12

R646

2

G

+1.25VS

12

13

D

2

G

S

470_0402_5%

VGA@

13

D

Q61

S

VGA@

SSM3K7002FU_SC70-3

R372
470_0402_5%

Q34
SSM3K7002FU_SC70-3

Compal Secret Data

Deciphered Date

SUSP

+0.9VS

12

13

D

2

G

S

SUSPSUSP

R351
470_0402_5%

Q33
SSM3K7002FU_SC70-3

VGA Discharge circuit

Discharge circuit-1

+1.8VS_CB

12

R536
470_0402_5%

13

2

G

D

Q50
SSM3K7002FU_SC70-3

S

SUSP

B

+1.8V

12

R133
470_0402_5%

13

SYSON#

D

2

G

Q12

S

SSM3K7002FU_SC70-3

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

SUSP

2007/1/15 2008/1/15

C

3 3

R551

100K_0402_5%

VGA_PWGOD

SUSP

SUSP#

+5VALW

12

100K_0402_5%

VGA@

VGA_PWGOD#

SUSP32,40,48

SUSP#28,29,46,47,48

4 4

VGA_PWGOD47

SYSON -> SUSP# -> VGA_ON->VGA_PWGOD

A

12

R647
470_0402_5%

VGA@

13

D

2

G

Q62

S

VGA@

SSM3K7002FU_SC70-3

SUSP SUSPSUSP

2

D

G

+5VS

12

R391

470_0402_5%

13

D

Q39

S

SSM3K7002FU_SC70-3

VGA_PWGOD#

+3VS

12

13

D

2

G

S

Title

DC/DC Circuits

Size Document Number Rev

Custom

LA-4231P

Date: Sheet

+1.8VS+1.2VS +VGA_CORE

12

R609
470_0402_5%

VGA@

13

D

2

G

Q65

S

VGA@

SSM3K7002FU_SC70-3

+1.5VS

R383

470_0402_5%

Q38
SSM3K7002FU_SC70-3

12

13

D

2

G

S

R382
470_0402_5%

Q37
SSM3K7002FU_SC70-3

Compal Electronics, Inc.

E

0.1

of

41 49Thursday, January 10, 2008

5

D D

4

3

2

1

FD2
FIDUCAL

1

H2
HOLEA@

1

H9
HOLEA@

1

H24
HOLEA@

1

H18
HOLEA@

1

FD3
FIDUCAL

@

FD4
FIDUCAL

@

1

H3
HOLEA@

1

H11
HOLEA@

1

H19
HOLEA@

1

H16
HOLEA@

1

FD5
FIDUCAL

@

1

H25
HOLEA@

1

H14
HOLEA@

1

H17
HOLEA@

1

FD6
FIDUCAL

@

1

H5
HOLEA@

1

H8
HOLEA@

1

FD7
FIDUCAL

@

1

1

H10

H6

HOLEA@

HOLEA@

1

H23
HOLEA@

1

FD8
FIDUCAL

@

1

H21
HOLEA@

1

1

H13
HOLEA@

H26
HOLEA@

1

1

FD1
FIDUCAL

@

@

1

H7

H_2P5

H_2P8

C C

H_2P8

H_3P3

H_3P8

B B

H_4P3

HOLEA@

1

H1
HOLEA@

1

H12
HOLEA@

1

H22
HOLEA@

1

H4
HOLEA@

1

H15
HOLEA@

1

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2007/1/15 2008/1/15

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

Compal Electronics, Inc.

Screws

LA-4231P

1

42 49Thursday, January 10, 2008

0.1

of

5

4

3

2

1

ADPIN

PL17

PJPDC1

1

1

2

2

3

3

4

4

5

5

6

6

7

D D

C C

GND

8

GND

ACES_88299-0600

@

BATT+

51ON#31

PD4

2 1

CH751H-40PT_SOD323-2

CHGRTCP

12

PR205

100K_0402_5%~D

PR206

22K_0402_5%~D

1 2

PL16

FBM-L11-160808-601LMT 0603~D

PJP1
JUMP_43X118@

2

112

12

PC164

0.22U_1206_25V7K

2

12

PQ50

TP0610K-T1-E3_SOT23-3

13

32.8

12

PC286

100P_0402_50V8J~D

DOCK_PSID

VIN

PD3

RLS4148_LL34-2

1 2
12

PR203

33_1206_5%

12

PC165

0.1U_0603_25V7K~D

12

PC287

VS

12

1000P_0402_50V7K~D

FBMA-L11-322513-151LMA50T_1210

12

PC157

PC158

1000P_0402_50V7K~D

100P_0402_50V8J~D

1 2

12

PC160

100P_0402_50V8J~D

VIN

PC156

2200P_0402_50V7K~D

@

1 2

12

PC159

1000P_0402_50V7K~D

PC162

0.1U_0402_16V7K~D

VIN

12

PR190

82.5K_0402_1%~D
PR193

22K_0402_1%~D

1 2

12

PR194

19.6K_0402_1%~D

+

-

8

PU12B

P

O

G

LM393DR_SO8

4

12

7

12

5
6

N40N41
N35

PC163
1000P_0402_50V7K~D

Vin Detector

56K_0402_5%~D@

1 2

PR189
1M_0402_1%~N

1 2

VS

8

PU12A

3

P

+

2

-

G

LM393DR_SO8

4

PR198

10K_0402_5%~D

12

PR188

O

12

PC161

1

0.01U_0402_25V7K~D

RLZ4.3B_LL34

RTCVREF

3.3V

PD1

VIN

12

PR191
10K_0402_5%~D

12

PR192
1K_0402_5%~D

1 2

12

PR195
10K_0402_5%~D

ACIN 19,29,44

Max. typ. Min.

L-->H 18.234 17.841 17.449
H-->L 17.597 17.210 16.813

+3VALW+5VALW

2

PR212

3

PD5

DA204U_SOT323~D

1

+5VALW

12

Title

DCIN / Precharge

Size Document Number Rev

Custom

Date: Sheet

PR214

<Title>

10K_0402_1%~D

PR216

1 2

10K_0402_1%~D@

JAL80

PR209

@

2.2K_0402_5%~D

PD6

1 2

+5VALW

DA204U_SOT323~D

2

3

1

1

PS_ID 29

PSID_DISABLE# 29

of

43 9Thursday, January 10, 2008

0.2

PR208

2

IN

+VGA_COREP

12

PR207
200_0805_5%

12

PC167
1U_0805_25V4Z~D

+1.5VSP

+0.9VSP

+VCCPP

PJP12
JUMP_43X118@

112

PJP14
JUMP_43X118@

112

PJP4
JUMP_43X118@

112

PJP6
JUMP_43X118@

112

PJP8
JUMP_43X118@

112

PJP10
JUMP_43X118@

112

DOCK_PSID

PJP2
JUMP_43X118@

+1.2VSP

2

+1.5VS

2

+0.9VS

2

+VCCP

2

2

+VGA_CORE

2

4

112

2

+1.2VS

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

1

2006/10/1 2007/5/01

3

@

PD7
SM24_SOT23

PR213

1 2

100K_0402_1%~D

PR215

1 2

15K_0402_1%~D

Compal Secret Data

Deciphered Date

B B

+5VALWP

+3VALWP

A A

+1.8VP

+1.25VSP

RTCVREF

12

PC166

PJP3
JUMP_43X118@

112

PJP5
JUMP_43X118@

112

PJP7
JUMP_43X118@

112

PJP9
JUMP_43X118@

112

PJP11
JUMP_43X118@

112

PJP13
JUMP_43X118@

112

5

PU14G920AT24U_SOT89-3

3

OUT

4.7U_0805_6.3V6K~N

2

2

2

2

2

2

GND

1

+5VALW

+3VALW

+1.8V

+1.25VS

PQ53

@

1 2

0_0402_5%~D

D

1 3

2

B

E

2

2

C

3 1

33_0402_5%~D

S

1 2

RHU002N06_SOT323-3

G

PQ54
MMST3904-7-F_SOT323~D

A

B

C

D

E

PQ56

PQ55

VIN

12

PR339

1 1

1_1210_5%~D

12

PR272

1_1210_5%~D

PC169

2.2U_0805_25V6K

1 2

1 2

90W adapter
Icharge=(Vsrset/Vvdac)*(0.1/PR222)=3.3A
Iadapter=(Vacset/Vvdac)*(0.1/PR217)=3.65A
Input OVP : 22.3V

2 2

Input UVP : 16.98V
Fsw : 300KHz

VREF

PR229
100K_0402_1%~D

1 2

13

D

G

S

GND

CELLS

VREF

CELLS

2

PQ61
SSM3K7002F_SC59-3

3 Cell
4 Cell

ACGOOD#

3cell/4cell# 50

Cells selector

3 3

PR235

1 2

B+

100_0805_5%~D

+5VALW

PR236

1 2

12

1 2

1SS355_SOD323-2

220K_0402_5%

470K_0402_5%~D

PQ64

2

G

PD9

PR238

32.8

1 2

220K_0402_5%

4 4

12

PC194

PR239

0.1U_0603_25V7K~D

PQ63

TP0610K-T1-E3_SOT23-3

13

32.8

2

13

D

RHU002N06_SOT323-3

S

PC193

FDS4435BZ_SO8

8
7
6
5

1 2

1 2

PR226
340K_0402_1%~D

1 2

OVPSET

PR227

54.9K_0402_1%

1 2

0.1U_0603_25V7K~D

B+_BIAS

0.1U_0805_25V7M~N

PR221
340K_0402_1%~D

ACDET

PR223

54.9K_0402_1%

100K_0402_1%~D

PC170

0.01U_0603_50V7K~D

CHGVADJ29

1 2

1

S

D

2

S

D

3

S

D

4

G

D

SI2301BDS-T1-E3_SOT23-3

PR228

1 2

PC189

REGN

PR53

4.32K_0402_1%~D

1 2

PC174

1 2

0.01U_0402_25V7K~D

VREF

CP setting

2

12

ACSET

12

12

PR54
10K_0402_1%~D

RTC_VREF

12

PR219

0.01U_0402_25V7K~D

PQ60

PR51
0_0402_5%~D@

VADJ

BAT54CW_SOT323~D

FDS4435BZ_SO8

1

S

2

S

3

S

4

G

100K_0402_1%~D

PR224

56.2K_0402_1%

1 2

PC182

@

1 3

+COINCELL

2

PD2

1

27.4

8

D

7

D

6

D

5

D

12

PC178

0.1U_0603_25V7K~D

12

1U_0603_10V6K~D

12

PR1
1K_0402_5%~D

Z4012

3

1

2

PR217

0.015_2512_1%

1
2

0.1U_0402_16V7K~D

PC188

PC175

1 2

ACSET

12

PR225
100K_0402_1%~D

1 2

0.47U_0603_16V7K~N

VREF

12

/BATDRV

4
3

12

PC184

VADJ

PU15

CHGEN#

1

CHGEN

PC176

0.1U_0603_25V7K~D

@

2

ACN

3

ACP

4

ACDRV

5

ACDET

6

ACSET

7

ACOP

8

OVPSET

9

AGND

10

VREF

11

VDAC

12

VADJ

13

ACGOOD

14

BATDRV

BQ24751ARHDR_QFN28_5X5

COIN RTC Battery

+RTCVCC

PC1
1U_0603_10V4Z~D

Move to power schematic

+COINCELL

PVCC

BTST

HIDRV

PH

REGN

LODRV

PGND

LEARN

CELLS

SRP
SRN
BAT

TP

SRSET

IADAPT

ADP_I29

PJP24

1

1

2

2

3

G1

4

G2

ACES_85204-02001

28

27

26

25

24

23

22

21

20

19
18
17

29

16

15

100P_0402_50V8J~D

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

B+

PC177

0.1U_0805_25V7K

1 2

PR220

2.2_0603_5%~D

1 2

DH_CHG

LX_CHG

PD8

RLS4148_LL34-2

REGN

12

PC183
1U_0603_10V6K~D

DL_CHG

CELLS

12

PC190

0.1U_0603_25V7K~D

PJP15

2

JUMP_43X118@

FDS8884_SO8

12

0.1U_0603_25V7K~D

ACOFF 29

112

PQ57

1 2

PC179

PQ59

FDS6690AS_NL_SO8

CHG_B+

578

578

1 2

3 6

241

10UH_SIL1045RA-100PF_4.5A_30%

1 2

3 6

241

PC1714.7U_1206_25V6K~D

PL18

ICHG setting

PR231

12

12

1 2

PR233

10_0603_5%~D

PC192

2006/10/1 2007/5/01

PR234
100K_0402_1%~D

12

Compal Secret Data

49.9K_0402_1%~D

12

PC191

0.01U_0402_25V7K~D

@

IREF Current

2.968V 3A

Deciphered Date

D

12

PC2921000P_0402_50V7K~D

1 2

IREF 29

PC1724.7U_1206_25V6K~D

PC2931000P_0402_50V7K~D

12

PC180

1 2

10U_1206_25V6M~D

12

PC186

0.1U_0603_25V7K~D

12

PR218

PC168

PC1734.7U_1206_25V6K~D

1 2

/BATDRV

PR222

0.02_2512_1%

1
2

PC185

0.1U_0402_16V7K~D

1 2

ACGOOD#

FSTCHG29

Title

Size Document Number Rev

B

Date: Sheet

100K_0402_1%~D

1 2

0.01U_0402_25V7K~D

4
3

RTCVREF

12

12

PC187

0.1U_0603_25V7K~D

@

VREF

PR230
100K_0402_1%~D

1 2

13

D

2

G

S

VREF

1 2

13

D

2

G

S

4

3

G

5

12

@

PR232

100K_0402_1%~D

PQ62
SSM3K7002F_SC59-3

PR237
100K_0402_1%~D

CHGEN#

PQ65
SSM3K7002F_SC59-3

Compal Electronics, Inc.

Charger

JAL80

PQ58

S1S2S

FDS4435BZ_SO8

D8D7D6D

PC181

10U_1206_25V6M~D

@

****

E

BATT+

ACIN 19,29,43

of

44 9Thursday, January 10, 2008

0.2

5

4

3

2

1

ISL6237_B+

12

12

PC199

PC198

4.7U_1206_25V6K~D

4.7U_1206_25V6K~D

PL21

4.7UH_SIL104R-4R7PF_5.7A_30%

12

4.7_1206_5%~D

12

PC209

680P_0603_50V7K~D

12

PC200

2200P_0402_50V7K~D

12

PR246

1 2

61.9K_0402_1%~D

PR248

1 2

10K_0402_1%~D

+5VALWP

1

+

PC210
330U_D3L_6.3VM_R25M

2

12

12

12

PR251

100K_0402_1%~D

1 2

PQ79

TP0610K-T1-E3_SOT23-3

ISL6237_B+

578

AO4466_SO8

3 6

241

578

PQ68
AO4712_SO8

3 6

241

PR252

1 2

200K_0402_5%~D

PR259

0_0402_5%~D

PQ66

PC212

0.22U_0603_25V7-K

1 2

VL

PR257

12

PC205

0.1U_0603_25V7K~D

1 2

1 2

806K_0603_1%

PC213

12

PR240

0_0805_5%

1 2

0.1U_0603_25V7K~D

PR243

BST3A BST5A

12

0_0603_5%~D

LX3

DL3

FB3

VL

2VREF_ISL6237

1 2

PC211 0.22U_0603_10V7K~D

PR254

@

0_0402_5%~D

PR260

47K_0402_5%~D@

1 2

0.047U_0603_16V7K~D

1 2

12

PC214

@

0.047U_0402_16V7K~N

PC201

1 2

2VREF_ISL6237

1 2

PU16

33

TP

26

UGATE2

24

BOOT2

25

PHASE2

23

LGATE2

30

OUT2

32

REFIN2

1

REF

8

LDOREFIN

20

NC

4

EN_LDO

14

EN1

27

EN2

PR256

0_0402_5%~D

PC285

1U_0603_10V6K~D

6

5

12

VIN

NC

1 2

PC202

1U_0603_10V6K~D

3

VCC

TON

2

12

PR258

@

0_0402_5%~D

2VREF_ISL6237

VL

12

PC203

7

4.7U_0805_6.3V6K~N

19

LDO

PVCC

15

UGATE1

17

BOOT1

16

PHASE1

18

LGATE1

22

PGND

10

OUT1

11

FB1

9

BYP

29

SKIP

28

POK2

13

POK1

12

ILIM1

31

ILIM2

GND

ISL6237IRZ-T_QFN32_5X5

21

578

PQ67

AO4466_SO8

3 6

241

PC207

1U_0603_10V6K~D

1 2

DH5DH3

PR245

0_0603_5%~D

PC208

0.1U_0603_25V7K~D

LX5

DL5

FB5

PR249 0_0402_5%~D@

PR250 0_0402_5%~D

1 2

ILM1

ILIM2

12

AO4712_SO8

1 2

12

PR253

255K_0402_1%

PR255

255K_0402_1%

578

PQ69

PR242

@

3 6

241

@

VL

POK

12

12

Rds(on) = 15m ohm(max) ; Rds(on) = 12m ohm(typical)

5VALWP
Imax=6A

Iocp=9A

B+

PJP20
JUMP_43X118@

2

112

12

D D

+3VALWP

1

+

PC204

330U_D3L_6.3VM_R25M

C C

2

PR244

1 2

PR247

1 2

PC195

4.7U_1206_25V6K~D

1 2

4.7UH_SIL104R-4R7PF_5.7A_30%

0_0402_5%~D

@

10K_0402_1%~D

PC196

PL20

12

PC197

4.7U_1206_25V6K~D
2200P_0402_50V7K~D

PR241

@

PC206

@

4.7_1206_5%~D

680P_0603_50V7K~D

Rds(on) = 15m ohm(max) ; Rds(on) = 12m ohm(typical)

3.3VALWP
Imax=6A

VS

PD10

RLZ5.1B_LL34

1 2

Iocp=9A

B B

MAINPWON50

2

1 3

PD16

1 2

A A

1SS355TE-17_SOD323-2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2006/10/1 2007/05/30

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

+3VALWP, +5VALWP

Size Document Number Rev

2

Date: Sheet

JAL80

Thursday, January 10, 2008

45 9

1

of

0.2Custom

5

PR295

PQ74

AO4466_SO8

PR306

1 2

0_0603_5%~D

PC256

串1K電組 上

PR290

1K_0402_1%~D

@

1 2

VCCPP_EN

LX_VCCPP

UG_VCCPP

12

PR310

0_0603_5%~D

PGOOD1 PGOOD2

PJP21

12

1000P_0402_25V8J

PR305

4.7_1206_5%~D

JUMP_43X118@

2

112

PC290

470P_0402_50V8J~D

PC245

68K_0402_1%

12

1 2

PR308

1 2

12

ISL6228_B+

PC249

4.7U_1206_25V6K~D

12

12

12

3.3K_0402_5%~D
PR296

PR297

12

12

PC247

PC255

680P_0603_50V8J~D

ISL6228_B+

PC291

680P_0402_50K X7R~D

4.7U_1206_25V6K~D

90.9K_0402_1%~N

578

3 6

241

578

PQ75
AO4712_SO8

3 6

241

0.1U_0402_16V7K~D

D D

C C

+VCCPP

220U_D2_4VM

B+

PR298

1 2

22.6K_0402_1%

PC248

0.033U_0402_16V7K~D

1 2

22.6K_0402_1%

PL26

1 2

1.5UH_MPL73-1R5_9A_20%

1

+

PC251

2

DCR 15m ohm(max)

VCCPP
Imax=7A

Iocp=11.59A

B B

SUSP#28,29,41,47,48

PR314

0_0402_5%~D

VCCPP_EN

12

12

PC262

@

4

PC240

PC239

1U_0402_6.3V6K~D

@

+5VALWP +5VALWP

+5VALWP

BST_VCCPP

12

12

1000P_0402_50V7K~D

10

11

12

13

14

+5VALWP

1U_0402_6.3V6K~D

LG_VCCPP

0.1U_0603_25V7K~D

ISL6228_B+ ISL6228_B+

PC243

7

PGOOD1

8

FB1

9

VO1

OCSET1

EN1

PHASE1

UGATE1

BOOT1

PVCC115LGATE116PGND117PGND218LGATE219PVCC220BOOT2

PC257

1 2

2.2_0603_1%~D

PC241

PR291

12

10_0603_1%

12

PR293

22K_0402_1%~D

1 2

6

FSET1

ISL6228HRTZ-T_QFN28_4X4

PR288

12

5

VIN1

PU18

12

1U_0402_6.3V6K~D

12

3

VCC2

PR289

1 2

2.2_0603_1%~D

12

0.1U_0603_25V7K~D

PC244

1000P_0402_50V7K~D

2

VIN2

+5VALWP

PC258
1U_0402_6.3V6K~D

1 2

12

4

VCC1

PC242

PR292

10_0603_1%

12

1

GND_T

FSET2

PGOOD2

OCSET2

PHASE2

UGATE2

21

BST_1.8V

3

12

PR294

18.2K_0402_1%~D

1 2

29

28

27

FB2

26

VO2

25

24

EN2

23

22

PR313

1 2

0_0603_5%~D

LG_1.8V

PR299

1K_0402_1%~D

@

PR307

0_0402_5%~D

1 2

1 2

0.01U_0402_25V7K~D@

UG_1.8V

12

PC252

0_0603_5%~D

1 2

LX_1.8V

PC259

1 2

0.1U_0402_16V7K~D

+5VALWP

PR311

SYSON 28,29,41

578

3 6

578

3 6

241

241

ISL6228_B+

PQ76
AO4466_SO8

PQ77
AO4712_SO8

12

1 2

12

PC253

4.7U_1206_25V6K~D

12

PR312

4.7_1206_5%~D

12

PC261

680P_0603_50V8J~D

PR300
34K_0402_1%

PC250

4.7U_1206_25V6K~D

2

3.3K_0402_5%~D
1000P_0402_25V8J

PR301

PC246

12

1 2

PR302

1 2

68K_0402_1%

PR303

1 2

24K_0402_1%~D

0.022U_0402_16V7K~D
PC254

1 2

PR309

24K_0402_1%~D

1 2

PL27

1 2

1.5UH_MPL73-1R5_9A_20%

DCR 15m ohm(max)

1.8VP
Imax=9A

Iocp=12.31A

1

+1.8VP

1

+

220U_D2_4VM

PC260

2

0.01U_0402_25V7K~D

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/10/1 2007/5/01

Compal Secret Data

Deciphered Date

2

Title

Size Document Number Rev

Date: Sheet

+1.8VP/+VCCPP

JAL80

Thursday, January 10, 2008

of

1

46 9

0.2

5

4

3

2

1

12

4

VCC1

PC216

12

1U_0402_6.3V6K~D

VGA@

PR262

1 2

2.2_0603_1%~D

3

VCC2

VGA@

12

PC218

0.1U_0603_25V7K~D

VGA@

PR265

10_0603_1%

VGA@

PC220

1000P_0402_50V7K~D

12

VGA@

2

1

GND_T

VIN2

FSET2

PGOOD2

OCSET2

PHASE2

UGATE2

21

BST_VGA

+5VALWP

PC236
1U_0402_6.3V6K~D

1 2

VGA@

12

PR267

18.2K_0402_1%~D

VGA@

1 2

29

28

27

FB2

26

VO2

25

24

EN2

23

22

2.2_0603_5%~D

VGA@

LG_VGA

UG_VGA

PR286

PR280

0_0402_5%~D

1 2

VGA@

PC228

1 2

0.01U_0402_25V7K~DVGA@

PC234

12

1 2

0.1U_0402_16V7K~D

VGA@

PR284

0_0603_5%~D

1 2

LX_VGA

VGA_PWGOD 41

VGA_ON 29

578

VGA@

578

3 6

3 6

241

241

ISL6228_B++

PQ72
AO4466_SO8

VGA@

PQ73
AO4712_SO8

VGA@

PR273

3.3K_0402_5%~D

78.7K_0402_1%~D

VGA@

1 2

12

12

PC226

PC229

4.7U_1206_25V6K~D

4.7U_1206_25V6K~D

VGA@

VGA@

12

PR285

4.7_1206_5%~DVGA@

12

PC237

VGA@

680P_0603_50V8J~D

1000P_0402_25V8J

PR274

PC222

VGA@

PR275

1 2

71.5K_0402_1%~D

VGA@

1 2

PR276
24K_0402_1%~D

VGA@

1 2

PR282
24K_0402_1%~D

VGA@

1 2

1 2

1.5UH_MPL73-1R5_9A_20%

DCR 15m ohm(max)

+VGA (1.15V)
Imax=9A

12

1 2

PC230

0.022U_0402_16V7K~D

VGA@

PL24

VGA@

VGA@

Iocp=12.31A

PR277
10_0402_5%~D

VGA@

1 2

1

+

2

220U_D2_4VM

PC233

VGA@

+VGA_COREP

PC215

1U_0402_6.3V6K~D

2.2_0603_1%~D

PC217

PR264

12

10_0603_1%

12

PR266

22K_0402_1%~D

1 2

6

FSET1

ISL6228HRTZ-T_QFN28_4X4

PR261

12

12

5

VIN1

PU17

PR268

PQ70

AO4466_SO8

PR279

1 2

0_0603_5%~D

12

PC232

0.1U_0402_16V7K~D

串1K電組 上

PR263

1K_0402_1%~D

1 2

1.5V_EN

LX_1.5V

PR283

0_0603_5%~D

PGOOD1 PGOOD2

PJP22
JUMP_43X118@

PC221

112

12

68K_0402_1%

ISL6228_B++

12

PC225

12

PR281

4.7_1206_5%~D@

12

@

2

3.3K_0402_5%~D
PR269

1 2

PR270

12

12

PC223

4.7U_1206_25V6K~D

PC231

680P_0603_50V8J~D

4.7U_1206_25V6K~D

ISL6228_B++

45.3K_0402_1%~D

578

3 6

241

578

PQ71
AO4712_SO8

3 6

241

PR271

1 2

17.8K_0402_1%~D

PC224

0.033U_0402_16V7K~D

1 2

PR278

17.8K_0402_1%~D

PL23

1 2

1.5VP
Imax=5A

B+

1000P_0402_25V8J

1 2

D D

C C

+1.5VSP

220U_6.3V_M

PC227

1

+

2

1.5UH_MPL73-1R5_9A_20%

DCR 15m ohm(max)

Iocp=9.13A

B B

SUSP#28,29,41,46,48

PR287

0_0402_5%~D

1.5V_EN

12

12

PC238

@

@

+5VALWP +5VALWP

+5VALWP

12

@

1000P_0402_50V7K~D

UG_1.5V

BST_1.5V

12

1U_0402_6.3V6K~D

LG_1.5V

10

11

12

13

14

+5VALWP

0.1U_0603_25V7K~D

ISL6228_B++ ISL6228_B++

PC219

7

PGOOD1

8

FB1

9

VO1

OCSET1

EN1

PHASE1

UGATE1

BOOT1

PVCC115LGATE116PGND117PGND218LGATE219PVCC220BOOT2

PC235

1 2

0.01U_0402_25V7K~D

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/10/1 2007/5/01

Compal Secret Data

Deciphered Date

2

Title

Size Document Number Rev

Date: Sheet

+1.5VP/+VGA

JAL80

Thursday, January 10, 2008

of

1

47 9

0.2

5

VGA@

12

D D

6

PU19

7

POK

VOUT

VCNTL

PR315

SUSP#28,29,41,46,47

C C

B B

1 2

0_0402_5%~D

VGA@

12

PC269

0.1U_0402_16V7K~D

@

PR321

SUSP#28,29,41,46,47

1 2

0_0402_5%~D

12

PC277

0.1U_0402_16V7K~D

@

8

EN

7

8

VOUT

GND

1

APL5913-KAC-TRL_SO8~N

VGA@

PU21

POK

EN

PC263

5

VIN

3
4
2

FB

9

VIN

6

5

VIN

3

VOUT

VCNTL

4

VOUT

2

FB

9

VIN

GND

1

APL5913-KAC-TRL_SO8~N

4

+1.5VS+5VALW

PJP16

2

JUMP_43X118@

2

1

1

1U_0603_10V6K~D

12

PC273

1U_0603_10V6K~D

12

VGA@

PC264

1U_0603_10V6K~D

12

12

PC265

0.01U_0402_25V7K~D

12

VGA@

PR319

2K_0402_1%~D

+1.5VS+5VALW

2

2

1

1
12

12

PR322

1.15K_0402_1%

12

VGA@

JUMP_43X118@

PC274

1U_0603_10V6K~D

0.01U_0402_25V7K~D

PR323

2.05K_0402_1%~D

PR316

VGA@

1K_0402_1%~D

PJP18

12

PC275

12

PC266

1U_0603_10V6K~D

VGA@

12

+1.2VSP

PC276

1U_0603_10V6K~D

+1.25VSP

3

+1.8V

1

PJP17

1

JUMP_43X118@

2

2

12

PC267

1K_0402_1%~D

1U_0603_10V6K~D

PR318

0_0402_5%~D

SUSP32,40,41

1 2

PC272

@

0.1U_0402_16V7K~D

2

G

12

PQ78

RHU002N06_SOT323-3

13

D

S

12

PR317

12

PR320

1K_0402_1%~D

2

PC270

0.1U_0402_16V7K~D

1

PU20

VIN1VCNTL

2

GND

3

VREF

4

VOUT

APL5331KAC-TRL_SO8~N

+0.9VSP

12

12

PC271

1U_0603_10V6K~D

6
5

NC

7

NC

8

NC

9

TP

+3VALW

12

PC268

4.7U_0805_6.3V6K~N

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/10/1 2007/05/30

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

+1.25VSP / +0.9VSP/ +1.2VSP

Size Document Number Rev

2

Date: Sheet

JAL80

Thursday, January 10, 2008

1

48 9

0.2Custom

of

5

@

D D

DPRSLPVR7,19

H_DPRSTP#5,7,18

CLK_EN#16

+3VS

+3VS

PR157

499_0402_1%~D

VGATE7,19,29

H_PSI#5

POW_MON

C C

VR_TT#

PR165 4.22K_0402_1%@

1 2

100K_0603_1%_TH11-4H104FT@

1 2

PC1280.015U_0402_16V7K@

PC131

1000P_0402_50V7K~D

1 2

PC1471U_0603_10V6K~D

1 2

PR164 147K_0402_1%~D

1 2

PH2

1 2

PR166 11.5K_0402_1%~D

1 2
1 2

PR169 6.81K_0402_1%~D

1 2

12

PR156

1 2

1.91K_0402_1%~D

PR181 10K_0402_1%~D

1 2

PC1290.068U_0603_50V7K~N

PR143 499_0402_1%~D

PR144 0_0402_5%~D

PR145 0_0402_5%~D

1 2

PR154 0_0402_5%~D

1 2

12

PC121

1U_0603_10V6K~D

1
2
3
4
5
6
7
8

9
10
11
12

1 2

1 2

PGOOD
PSI#
PMON
RBIAS
VR_TT#
NTC
SOFT
OCSET
VW
COMP
FB
FB2

1 2

PC132 1000P_0402_50V7K~D

PR175 97.6K_0402_1%~D

1 2

B B

VCCSENSE5

A A

PC137 220P_0402_50V7K~D

PR177

1 2

PR179 1K_0402_1%~D

VSSSENSE5

5

PC134 470P_0402_50V7K~D

1 2

PC138 1000P_0402_50V7K~D

255_0402_1%~D

1 2

1 2

PR180 0_0402_5%~D

VCC_PRM

12

1 2

12

PR176
1K_0402_1%~D

PC140 0.022U_0603_25V7K

1 2

12

PC141

0.022U_0603_25V7K

@

1 2

PR183 0_0402_5%~D

PC143 180P_0402_50V8J~D

1 2

1 2

PR186 1K_0402_1%~D

PC145

0.22U_0603_16V7K~D

4

PC112

12

CPU_VID5

5600P_0402_25V7K

48

49

GND

46

47

3V3

CLK_EN#

DPRSTP#

CPU_VID6

VR_ON

12

12

12

12

PR153

45

PR1460_0402_5%~D

0_0402_5%~D

44

43

PR1470_0402_5%~D

VR_ON

DPRSLPVR

ISL6262ACRZ-T_QFN48_7X7

VDIFF13VSEN14RTN15DROOP16DFB17VO18VSUM19VIN20GND21VDD22ISEN223ISEN1

12

12

PC142

0.022U_0603_25V7K

1 2

PR187 3.57K_0402_1%~D

12

4

VSUM

PR185

PC144 0.068U_0603_50V7K~N

1 2

PC146 0.22U_0603_10V7K~D

12

3

+5VS

5

5

5

29

CPU_VID45CPU_VID3

CPU_VID25CPU_VID15CPU_VID0

12

12

12

PR1490_0402_5%~D

PR1480_0402_5%~D

PR1500_0402_5%~D

12

PC136
1U_0603_10V6K~D

PR178

1 2

PC139

10_0603_5%~D

0.1U_0603_25V7K~D

12

PR1510_0402_5%~D

PR1520_0402_5%~D

VID037VID138VID239VID340VID441VID542VID6

BOOT1
UGATE1
PHASE1

PGND1

LGATE1

PVCC

LGATE2

PGND2
PHASE2
UGATE2

BOOT2

NC

24

1 2

PR174 1_0603_5%~D

36
35
34
33
32
31
30
29
28
27
26
25

PU11

29.1

ISEN1
ISEN2

5

BOOT_CPU1

UGATE_CPU1
PHASE_CPU1

LGATE_CPU1

BOOT_CPU2

2.2_0603_5%~D

+5VS

+CPU_B+

2.2_0603_5%~D

LGATE_CPU2

PHASE_CPU2

UGATE_CPU2

PR167

1 2

12

12

PC118

PC117

1U_0603_10V6K~D

0.01U_0402_25V7K~D

PC122

0.22U_0603_10V7K~D

PR155

1 2

1 2

FDS6676AS_SO8

PC130

1 2

0.22U_0603_10V7K~D

1 2

12

12

PC119

0.01U_0402_25V7K~D

5

PQ44

4

PQ47

FDS6676AS_SO8

PR142
1_0603_5%~D

PC120

1U_0603_10V6K~D

D8D7D6D

S1S2S3G

5

D8D7D6D

S1S2S3G

4

3 5

241

5

D8D7D6D

S1S2S3G

4

FDS6676AS_SO8

3 5

241

5

4

FDS6676AS_SO8

12

PR182

12

2.61K_0402_1%~D

PH3
10KB_0603_ERTJ1VR103J

11K_0402_1%~D

1 2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2007/1/15 2008/1/15

3

Compal Secret Data

Deciphered Date

2

12

PC114

@

10U_1206_25V6M~D

PQ43
SI7686DP-T1-E3_SO8

12

PR158

PQ45

12

PC123

PQ46
SI7686DP-T1-E3_SO8

12

D8D7D6D

PQ48

S1S2S3G

12

2

12

PC115

PC116

10U_1206_25V6M~D

10U_1206_25V6M~D

4.7_1206_5%~D

680P_0603_50V8J~D

PR168

4.7_1206_5%~D

PC133
680P_0603_50V8J~D

PR159

PC125

10U_1206_25V6M~D

1

+CPU_B+

1

1

12

P_0.36H_ETQP4LR36WFC_24A_20%

12

3.65K_1206_1%

VSUM

12

P_0.36H_ETQP4LR36WFC_24A_20%

12

PR171

VSUM

Title

Size Document Number Rev

Custom

Date: Sheet

+

+

PC113

2

2

100U_25V_M

12

PR160

PR162 0_0402_5%~D@

1 2

10K_0402_1%~D

1 2

ISEN1

0.22U_0603_16V7K~D

12

PC126

10U_1206_25V6M~D

12

PR170

PR173 0_0402_5%~D@

10K_0402_1%~D

3.65K_1206_1%

1 2

1 2

0.22U_0603_16V7K~D

ISEN2

+CPU_CORE

LA-4121P

PL13

FBMA-L18-453215-900LMA90T_1812

1 2

PC155

100U_25V_M

12

PL14

12

PR161

1_0402_5%~D

PC124

VCC_PRM

+CPU_B+

12

PC127

@

10U_1206_25V6M~D

12

PL15

PC135

12

PR172
1_0402_5%~D

VCC_PRM

Compal Electronics, Inc.

49 9Thursday, January 10, 2008

1

B+

of

+CPU_CORE

0.1

5

D D

C C

BATT+

PL28

HCB4532KF-800T90_1812

BATT+

1 2

12

12

PJPB1 battery connector

PC288

100P_0402_50V8J~D

PC278

0.01U_0402_25V7K~D

SMART
Battery:

1.BAT+

2.BAT+

3.ID

4.B/I

5.TS

6.SMD

7.SMC

8.GND

9.GND

12

PC279
1000P_0402_50V7K~D

PJP19

10

GND

11

GND

SUYIN_200275MR009G186ZL

BATT++

@

BATT++

12

PC289

100P_0402_50V8J~D

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

3cell/4cell#

+3VALWP

1 2

1 2

PR328

100_0402_5%~D

1 2

PR329

100_0402_5%~D

4

PD12

@

PR324
47K_0402_5%~D

3cell/4cell# 44

+3VALWP

3

DA204U_SOT323~D

2

1

EC_SMB_DA1 29

EC_SMB_CK1 29

3

PD13

DA204U_SOT323~D

@

PR326

1K_0402_5%~D

12

3

2

PD14

DA204U_SOT323~D

@

3

1

2

1

PD15

DA204U_SOT323~D

2

3

1

@

2

Battery Connect/OTP

1

Place clsoe to EC pin

BATT_TEMP

1 2

PR325

1K_0402_5%~D

1 2

PR327

6.49K_0402_1%~D

PC280

0.1U_0402_16V7K~D

1 2

@

+3VALWP

BATT_TEMP 29

CPU

PH1 under CPU botten side :

CPU thermal protection at 90 +-3 degree C
Recovery at 50 +-3 degree C

BATT+

12

PR330
453K_0402_1%~D

0.01U_0402_25V7K~D

12

PR332

499K_0402_1%~D

12

PR337

86.6K_0402_1%

PC283

1000P_0402_50V7K~D

VS

0

8

LM358ADR_SO8

5

P

+

6

-

G

4

12

PC282

B B

BATT_OVP29

7

PU22B

VL VS

12

CPU

12

PR331

10.7K_0402_1%~D

PR335

61.9K_0402_1%~D

1 2

1 2

VL

12

PH4
100K_0603_1%_TH11-4H104FT

PR336

150K_0402_1%~D

150K_0402_1%~D

PR338

PR333

147K_0402_1%~D

1 2

12

12

8

3

P

+

0

2

-

G

PU22A

4

LM358ADR_SO8

PC284
1U_0603_10V6K~D

PC281

0.1U_0603_25V7K~D

1 2

1

1 2

1SS355_SOD323-2

PD11

VL

1 2

PR334
205K_0402_1%~D

MAINPWON 45

LI-3S :13.5V----BATT-OVP=1.5V

BATT-OVP=0.111*BATT+

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/10/1 2007/05/30

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

BATTERY CONN

Size Document Number Rev

2

Date: Sheet

JAL80

Thursday, January 10, 2008

1

50 9

0.2Custom

of

5

4

3

2

1

Version Change List ( P. I. R. List )

Page 1/1

Request

Item Issue DescriptionDate

1

D D

2

3

4

5

6

7

8

9

10

11

12

C C

13

14

15

16

17

18

19

20

21

22

40 P40-OZ129_Card Reader/1394 07/10/30 compal CardBus vendor change CardBus R5C833 change to OZ129 0.2

29 P29-EC KB926/REED SW/TPM1.2 07/10/30 compal Change pull up resistance Change EC pin17,18 pull up to 4.7Kohm 0.2

29 P29-EC KB926/REED SW/TPM1.2 07/10/30 compal Need pull up NET MIC_DIAG pull up R to 10Kohm 3VS 0.2

13,14 DDR2 SODIMM-I,II Socket compal Change Capacitance Change C84,C189 to SGA00002680 330U 0.2

29 P29-EC KB926/REED SW/TPM1.2 compal EC update rev EC change to 926C 0.2

28 P28-Express card compal

32 P32-USB/ BlueTooth/

FP/ Felica

42 P42-Screws 07/10/30 compal FIDUCAL no enough ADD FIDUCAL*4 0.2

41 P41-DC/DC Interface 07/10/30 compal Need pull down SYSON pull down 10K ohm 0.2

41 P41-DC/DC Interface 07/11/12 compal USB can't detect SUSP change to 5VALW(Q32) 0.2

06 P06-Merom(3/3)-GND/Bypass 07/11/12 compal Change CPU High Frequence Decoupling Capacitance C195 change to C1150~C1181 0.2

41 P41-DC/DC Interface 07/11/13 compal +1.8VS Discharge circuit Q65 net change to VGA_PWGOD# 0.2+1.8VS Discharge error

41 P41-DC/DC Interface 07/11/16 compal Delete Remove SIM card connector 0.2

42 P42-Screws 07/11/16 compal Change Holea size Change Holea size 2.5 to 2.8, change 3.5 to 3.8 0.2

31 P31-PWR_OK/ BTN/ KB /

TouchPad

15 P15-CRT Conn.& LCD Conn. 07/11/21 compal Add LCD control pin Add LCD control pin LCD_CBL_DET# & LCD_TST & LCD_VCC_TEST_EN 0.2

07/10/30

07/10/30

07/10/30

07/10/30 compal BLUETOOTH CONN USB+- change 0.2Bluetooth can't detect

07/11/21 compal Change Touch PAD/B connector Touch PAD/B connector change net 0.2

Owner

Express card can't detect POWER IC(U11) ADD PIN10 CPUSB# PIN9 EXPR_CPUSB#S 0.2

Solution Description Rev.Page# Title

0.229 P29-EC KB926/REED SW/TPM1.2 07/10/30 compal board rev update to 0.2 R231 change to 15K & R232 pop

B B

23

24

25

26

27

28

29

30

31

32

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2007/1/15 2008/1/15

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

Compal Electronics, Inc.

EE PIR-1

LA-4231P

0.1

of

51 49Thursday, January 10, 2008

1

5

4

3

2

1

Version Change List ( P. I. R. List )

Page 1/1

Request

Item Issue DescriptionDate

1

D D

2

3

4

5

6

7

8

9

10

11

12

C C

13

14

15

16

17

18

19

20

21

22

41 +3VALWP/+5VALWP 07/11/19 COMPAL When in the DC-mode , shut down the system ,5valwp output not turn off ADD PQ79 to turn off 5VALWP wehn shut down the system in the DC-mode

49 CPU_CORE 07/12/26 ADD PR163 PR184

45

+3VALWP/+5VALWP

07/12/26

Owner

COMPAL

COMPAL

change charge voltage can to adjustCOMPAL07/12/26Charge44 Change PR53 from 15K to 4.3K

Increase Resistor 0ohm on CPU_CORE high side gate for EMI request

The schematic location is wrong

DEL PL19

Solution Description Rev.Page# Title

B B

23

24

25

26

27

28

29

30

31

32

A A

4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2007/1/15 2008/1/15

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

Compal Electronics, Inc.

PW PIR-1

LA-3682P

0.1

of

52 9Thursday, January 10, 2008

1