COMPAL LA-4191 Schematics

A

1 1

B

C

D

E

2 2

Compal Confidential

Schematics Document

AMD S1/ ATI RS690MC / SB600

2007 / 1 / 10

3 3

Rev:0.3

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2008/1/3 2009/01/3

Compal Secret Data

Deciphered Date

Title

Cover Sheet

Size Document Number Rev

Custom

LA-4191P

D

Date: Sheet

E

139Monday, January 14, 2008

0.3

of

A

B

C

D

E

Compal confidential

Project Code: ANRJBL3000(JBL30)
File Name : LA-4191P

1 1

PCB P/N: DA600007000

Thermal Sensor
ADM1032ARM

page 6 page 13

Clock Generator
ICS951462

Turion64 x2 TLxx / Sempron

AMD S1g1 CPU

page 4,5,6,7

DDR2 DDR2-SO-DIMM X2

page 8,9

Dual Channel DDR2

HT 16x16 800MHZ

CRT

page 14

LCD CONN

page 14

2 2

Realtek

RTL8111C/8102E

page 22

Express Card
(New Card)

page 27

RJ45 CONN

page 22

RGB

LVDS

PCI EXPRESS

Mini Card
WLAN

page 25

PCI BUS

ATI-RS690M(C)

BGA465

page 10,11,12

A-Link Express

4 x PCIE

USB2.0

ATI-SB600

BGA548

page 15,16,17,18

HD-Interface

Media Card Controller

USB port0~3

USB port8

USB port6

USB port5

USB port7

USB port9

USB port4

Audio CKT

ALC268

USB conn x 4

Mini Card

Express Card

Finger Printer

Bluetooth

Camera

Felica Conn

page 23

page 28

page 25

page 27

page 28

page 28

page 28

page 28

AMP & Audio Jack

page 24

Mic Array

O2 OZ129

page 20

3 3

Media Card

page 20

1394
Conn.

page 28

Power On/Off CKT.

page 29

DC/DC Interface CKT.

page 30

RTC CKT.

page 15

LPC BUS

SATA

PATA

Option

TPM1.2

page 26

SATA HDD Conn.

page 19

CDROM Conn.

page 19

ENE KB926

Power Circuit DC/DC

page 31~38

4 4

Power OK CKT.

page 29

Touch Pad
CONN.

page 27

page 26

Int. KBD

page 27

SPI BIOS

page 26

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2008/1/3 2009/01/3

Compal Secret Data

Deciphered Date

Title

Block Diagrams

Size Document Number Rev

Custom

LA-4191P

D

Date: Sheet

E

239Monday, January 14, 2008

0.3

of

A

Voltage Rails

Power Plane Description

VIN

1 1

2 2

B+
+CPU_CORE
+1.2V_HT
+0.9V 0.9V switched power rail for DDR terminator
+1.2VALW 1.2V always on power rail
+1.5VS
+1.8VS 1.8V switched power rail
+1.8V
+3VALW
+3V
+3VS
+5VALW
+5VS
+RTCVCC RTC power

Adapter power supply (19V)
AC or battery power rail for power circuit.
Core voltage for CPU

1.2V switched power rail

1.5V switched power rail

1.8V power rail for DDR

3.3V always on power rail

3.3V power rail

3.3V switched power rail
5V always on power rail
5V switched power rail

B

S1 S3 S4/ S5

ON ON ON

ON OFF
ON OFF
ON OFF
ON
ON OFF OFF
ON OFF OFF
ON
ON
ON
ON
ON

ON ONON

ONONON
OFF
OFF

ON

ONON

OFF

ON
ON ON

OFF

ON

OFF

OFF
ON

ON
OFFON

OFF

C

SIGNAL

STATE

Full ON

S1(Power On Suspend)

S3 (Suspend to RAM)

SLP_S1# SLP_S3#

HIGH HIGH HIGH HIGH

LOW

LOW

LOW

S4 (Suspend to Disk)

S5 (Soft OFF)

LOW LOW LOW LOW

Board ID Table for AD channel

Vcc 3.3V +/- 5%

Board ID

0
1
2
3
4
5
6
7 NC

100K +/- 5%Ra / Rc

Rb / Rd V min

0

8.2K +/- 5%
18K +/- 5%
33K +/- 5%
56K +/- 5%
100K +/- 5%
200K +/- 5%

AD_BID

0 V

0.216 V 0.250 V 0.289 V

0.436 V

0.712 V

1.036 V

1.453 V 1.650 V 1.759 V

1.935 V

2.500 V

D

SLP_S4# SLP_S5# +VALW +V +VS Clock

ON

ON

ON

OFF

OFF

V

AD_BID

ON ON

ON

OFF

OFF

OFF

max

LOW

OFF

OFF

OFF

HIGH

LOWLOWLOW

HIGHHIGHHIGH

HIGH

HIGH

V typ

AD_BID

ON

ON

ON

ON

ON

0 V 0 V

0.503 V

0.819 V

0.538 V

0.875 V

1.185 V 1.264 V

2.200 V

3.300 V

2.341 V

3.300 V

E

External PCI Devices

Device IDSEL# REQ#/GNT# Interrupts

OZ129

AD21

0

PIRQG

BOARD ID Table

Board ID

0
1

PCB Revision

0.1 0.2

0.3

BTO Item BOM Structure

BTO Option Table

2
3
4
5
6
7

EC SM Bus1 address

3 3

Device

Smart Battery
EEPROM(24C16/02)

(24C04)

Address Address

1010 000X b?
1011 000Xb?

EC SM Bus2 address

Device

ADM1032

1001 110X b?0001 011X b?

SB600 SM Bus address

Device

Clock Generator
(ICS 951462AGT)

DDRII DIMM0
DDRII DIMM2

4 4

Address

1101 001Xb?

1001 000Xb?
1001 010Xb?

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2008/1/3 2009/01/3

Compal Secret Data

Deciphered Date

Title

Notes

Size Document Number Rev

Custom

LA-4191P

D

Date: Sheet

E

339Monday, January 14, 2008

0.3

of

5

4

3

2

1

H_CADIP[0..15]10

H_CADIP[0..15]
H_CADIN[0..15]

H_CADOP[0..15]
H_CADON[0..15]

H_CADOP[0..15] 10
H_CADON[0..15] 10H_CADIN[0..15]10

PROCESSOR HYPERTRANSPORT INTERFACE

VLDT_Ax AND VLDT_Bx ARE CONNECTED TO THE LDT_RUN POWER

D D

C C

+1.2V_HT

R236 51_0402_1%
R235 51_0402_1%

2006-10-17 Change from 49.9 1% to 51 1%

B B

A A

SUPPLY THROUGH THE PACKAGE OR ON THE DIE. IT IS ONLY CONNECTED
ON THE BOARD TO DECOUPLING NEAR THE CPU PACKAGE

+1.2V_HT

D4

1A

H_CADIP15
H_CADIN15
H_CADIP14
H_CADIN14
H_CADIP13
H_CADIN13
H_CADIP12
H_CADIN12
H_CADIP11
H_CADIN11
H_CADIP10
H_CADIN10
H_CADIP9
H_CADIN9
H_CADIP8
H_CADIN8
H_CADIP7
H_CADIN7
H_CADIP6
H_CADIN6
H_CADIP5
H_CADIN5
H_CADIP4
H_CADIN4
H_CADIP3
H_CADIN3
H_CADIP2
H_CADIN2
H_CADIP1
H_CADIN1
H_CADIP0
H_CADIN0

H_CLKIP110
H_CLKIN110
H_CLKIP010
H_CLKIN010

1 2
1 2

H_CTLIP010 H_CTLOP0 10
H_CTLIN010

H_CLKIP1
H_CLKIN1
H_CLKIP0
H_CLKIN0

H_CTLIP0
H_CTLIN0

+1.2V_HT

1

C431

2

4.7U_0603_6.3V6M~D

LAYOUT: Place bypass cap near CPU socket

NEAR HT POWER PINS THAT ARE NOT CONNECTED DIRECTLY
TO DOWNSTREAM HT DEVICE, BUT CONNECTED INTERNALLY
TO OTHER HT POWER PINS
PLACE CLOSE TO VLDT0 POWER PINS

C428

D3
D2
D1

N5
P5
M3
M4
L5
M5
K3
K4
H3
H4
G5
H5
F3
F4
E5
F5
N3
N2
L1
M1
L3
L2

K1
G1
H1
G3
G2
E1
F1
E3
E2

K5

P3
P4

N1
P1

1

2

VLDT_A3
VLDT_A2
VLDT_A1
VLDT_A0

L0_CADIN_H15
L0_CADIN_L15
L0_CADIN_H14
L0_CADIN_L14
L0_CADIN_H13
L0_CADIN_L13
L0_CADIN_H12
L0_CADIN_L12
L0_CADIN_H11
L0_CADIN_L11
L0_CADIN_H10
L0_CADIN_L10
L0_CADIN_H9
L0_CADIN_L9
L0_CADIN_H8
L0_CADIN_L8
L0_CADIN_H7
L0_CADIN_L7
L0_CADIN_H6
L0_CADIN_L6
L0_CADIN_H5
L0_CADIN_L5

J1

L0_CADIN_H4
L0_CADIN_L4
L0_CADIN_H3
L0_CADIN_L3
L0_CADIN_H2
L0_CADIN_L2
L0_CADIN_H1
L0_CADIN_L1
L0_CADIN_H0
L0_CADIN_L0

J5

L0_CLKIN_H1
L0_CLKIN_L1

J3

L0_CLKIN_H0

J2

L0_CLKIN_L0

L0_CTLIN_H1
L0_CTLIN_L1

L0_CTLIN_H0
L0_CTLIN_L0

C430

4.7U_0603_6.3V6M~D

1

2

CPU1A

L0_CADOUT_H15

L0_CADOUT_L15

L0_CADOUT_H14

L0_CADOUT_L14

L0_CADOUT_H13

L0_CADOUT_L13

L0_CADOUT_H12

L0_CADOUT_L12

L0_CADOUT_H11

L0_CADOUT_L11

L0_CADOUT_H10

L0_CADOUT_L10

L0_CADOUT_H9

L0_CADOUT_L9

L0_CADOUT_H8

L0_CADOUT_L8

L0_CADOUT_H7

L0_CADOUT_L7

L0_CADOUT_H6

L0_CADOUT_L6

L0_CADOUT_H5

L0_CADOUT_L5

L0_CADOUT_H4

L0_CADOUT_L4

L0_CADOUT_H3

L0_CADOUT_L3

L0_CADOUT_H2

L0_CADOUT_L2

L0_CADOUT_H1

L0_CADOUT_L1

L0_CADOUT_H0

HTT Interface

L0_CADOUT_L0
L0_CLKOUT_H1

L0_CLKOUT_L1
L0_CLKOUT_H0
L0_CLKOUT_L0

L0_CTLOUT_H1

L0_CTLOUT_L1

L0_CTLOUT_H0

L0_CTLOUT_L0

Athlon 64 S1
Processor Socket

1

C427

C426

2

0.22U_0603_10V7K

0.22U_0603_10V7K

VLDT_B3
VLDT_B2
VLDT_B1
VLDT_B0

1

2

C429

180P_0402_50V8J~N

1

2

AE5
AE4
AE3
AE2

T4
T3
V5
U5
V4
V3
Y5
W5
AB5
AA5
AB4
AB3
AD5
AC5
AD4
AD3
T1
R1
U2
U3
V1
U1
W2
W3
AA2
AA3
AB1
AA1
AC2
AC3
AD1
AC1

Y4
Y3
Y1
W1

T5
R5

R2
R3

180P_0402_50V8J~N

H_CADOP15
H_CADON15
H_CADOP14
H_CADON14
H_CADOP13
H_CADON13
H_CADOP12
H_CADON12
H_CADOP11
H_CADON11
H_CADOP10
H_CADON10
H_CADOP9
H_CADON9
H_CADOP8
H_CADON8
H_CADOP7
H_CADON7
H_CADOP6
H_CADON6
H_CADOP5
H_CADON5
H_CADOP4
H_CADON4
H_CADOP3
H_CADON3
H_CADOP2
H_CADON2
H_CADOP1
H_CADON1
H_CADOP0
H_CADON0

H_CLKOP1
H_CLKON1
H_CLKOP0
H_CLKON0

H_CTLOP0
H_CTLON0

1 2

C394 4.7U_0805_6.3V6K~N

H_CLKOP1 10
H_CLKON1 10
H_CLKOP0 10
H_CLKON0 10

H_CTLON0 10

FAN1 Control and Tachometer

EN_DFAN125

FAN_SPEED125

EN_DFAN1

R38

10K_0402_5%

+3VS

12

2

C114

0.01U_0402_16V7K

1

+5VS

12

D3

1SS355_SOD323 @

@

12

D14 1N4148_SOT23

C424

10U_0805_10V4Z~N

12

C113

1000P_0402_50V7K~N

12

FAN1_POWER

+5VS

40mil

1 2

C410 10U_0805_10V4Z~N
U20

1

VEN

2

VIN

3

VO

4

VSET

APL5605KI_SOP8
JFAN1

1
2
3

4

G

5

G

MOLEX_53398-0371~N

CONN@

GND
GND
GND
GND

8
7
6
5

FAN1

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2008/1/3 2009/01/3

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

Compal Electronics, Inc.

TURION64 HT I/F & FAN

LA-4191P

1

0.3

of

439Monday, January 14, 2008

A

B

C

D

E

VDD_VTT_SUS_CPU IS CONNECTED TO THE VDD_VTT_SUS POWER
SUPPLY THROUGH THE PACKAGE OR ON THE DIE. IT IS ONLY CONNECTED

ON THE BOARD TO DECOUPLING NEAR THE CPU PACKAGE

+1.8V

4 4

3 3

2 2

12

R222

39.2_0603_1%

12

R223

39.2_0603_1%

PLACE THEM CLOSE TO
CPU WITHIN 1"

DDR_CS3_DIMMA#8
DDR_CS2_DIMMA#8
DDR_CS1_DIMMA#8
DDR_CS0_DIMMA#8

DDR_CS3_DIMMB#9
DDR_CS2_DIMMB#9
DDR_CS1_DIMMB#9
DDR_CS0_DIMMB#9

DDR_CKE1_DIMMB9
DDR_CKE0_DIMMB9
DDR_CKE1_DIMMA8
DDR_CKE0_DIMMA8

DDR_A_MA[15..0]8

DDR_A_BS#28
DDR_A_BS#18
DDR_A_BS#08

DDR_A_RAS#8
DDR_A_CAS#8
DDR_A_WE#8

DDR_A_CLK2

DDR_A_CLK#2
DDR_A_CLK1

DDR_A_CLK#1

PLACE CLOSE TO PROCESSOR
WITHIN 1.5 INCH

TP1

M_ZN
M_ZP

1

C392

1.5P 50V F NPO 0402

2

1

C439

1.5P 50V F NPO 0402

2

+CPU_M_VREF

VTT_SENSE

DDR_CS3_DIMMA#
DDR_CS2_DIMMA#
DDR_CS1_DIMMA#
DDR_CS0_DIMMA#

DDR_CS3_DIMMB#
DDR_CS2_DIMMB#
DDR_CS1_DIMMB#
DDR_CS0_DIMMB#

DDR_CKE1_DIMMB
DDR_CKE0_DIMMB
DDR_CKE1_DIMMA
DDR_CKE0_DIMMA

DDR_A_MA15
DDR_A_MA14
DDR_A_MA13
DDR_A_MA12
DDR_A_MA11
DDR_A_MA10
DDR_A_MA9
DDR_A_MA8
DDR_A_MA7
DDR_A_MA6
DDR_A_MA5
DDR_A_MA4
DDR_A_MA3
DDR_A_MA2
DDR_A_MA1
DDR_A_MA0

DDR_A_BS#2
DDR_A_BS#1
DDR_A_BS#0

DDR_A_RAS#
DDR_A_CAS#
DDR_A_WE#

AE10
AF10

W17

Y10

V19
J22
V22
T19

Y26
J24

W24

U23
H26

J23
J20
J21

K19
K20
V24
K24
L20
R19
L19
L22

L21
M19
M20
M24
M22

N22

N21

R21

K22

R20

T22

T20

U20

U21

M_VREF
VTT_SENSE

M_ZN
M_ZP

MA0_CS_L3
MA0_CS_L2
MA0_CS_L1
MA0_CS_L0

MB0_CS_L3
MB0_CS_L2
MB0_CS_L1
MB0_CS_L0

MB_CKE1
MB_CKE0
MA_CKE1
MA_CKE0

MA_ADD15
MA_ADD14
MA_ADD13
MA_ADD12
MA_ADD11
MA_ADD10
MA_ADD9
MA_ADD8
MA_ADD7
MA_ADD6
MA_ADD5
MA_ADD4
MA_ADD3
MA_ADD2
MA_ADD1
MA_ADD0

MA_BANK2
MA_BANK1
MA_BANK0

MA_RAS_L
MA_CAS_L
MA_WE_L

Athlon 64 S1
Processor
Socket

CPU1B

VTT1
VTT2
VTT3
VTT4
VTT5
VTT6
VTT7
VTT8
VTT9

MA0_CLK_H2
MA0_CLK_L2
MA0_CLK_H1
MA0_CLK_L1

MB0_CLK_H2
MB0_CLK_L2
MB0_CLK_H1
MB0_CLK_L1

MB0_ODT1
MB0_ODT0
MA0_ODT1
MA0_ODT0

MB_ADD15
MB_ADD14
MB_ADD13
MB_ADD12
MB_ADD11
MB_ADD10

MB_ADD9

DDRII Cmd/Ctrl//Clk

MB_ADD8
MB_ADD7
MB_ADD6
MB_ADD5
MB_ADD4
MB_ADD3
MB_ADD2
MB_ADD1
MB_ADD0

MB_BANK2
MB_BANK1
MB_BANK0

MB_RAS_L
MB_CAS_L

MB_WE_L

DDR_B_CLK2

DDR_B_CLK#2
DDR_B_CLK1

DDR_B_CLK#1

PLACE CLOSE TO PROCESSOR
WITHIN 1.5 INCH

D10
C10
B10
AD10
W10
AC10
AB10
AA10
A10

Y16
AA16
E16
F16

AF18
AF17
A17
A18

W23
W26
V20
U19

J25
J26
W25
L23
L25
U25
L24
M26
L26
N23
N24
N25
N26
P24
P26
T24

K26
T26
U26

U24
V26
U22

+0.9V

DDR_A_CLK2
DDR_A_CLK#2
DDR_A_CLK1
DDR_A_CLK#1

DDR_B_CLK2
DDR_B_CLK#2
DDR_B_CLK1
DDR_B_CLK#1

DDR_B_ODT1
DDR_B_ODT0
DDR_A_ODT1
DDR_A_ODT0

DDR_B_MA15
DDR_B_MA14
DDR_B_MA13
DDR_B_MA12
DDR_B_MA11
DDR_B_MA10
DDR_B_MA9
DDR_B_MA8
DDR_B_MA7
DDR_B_MA6
DDR_B_MA5
DDR_B_MA4
DDR_B_MA3
DDR_B_MA2
DDR_B_MA1
DDR_B_MA0

DDR_B_BS#2
DDR_B_BS#1
DDR_B_BS#0

DDR_B_RAS#
DDR_B_CAS#
DDR_B_WE#

1

2

1

2

C393

1.5P 50V F NPO 0402

C438

1.5P 50V F NPO 0402

DDR_A_CLK2 8
DDR_A_CLK#2 8
DDR_A_CLK1 8
DDR_A_CLK#1 8

DDR_B_CLK2 9
DDR_B_CLK#2 9
DDR_B_CLK1 9
DDR_B_CLK#1 9

DDR_B_ODT1 9
DDR_B_ODT0 9
DDR_A_ODT1 8
DDR_A_ODT0 8

DDR_B_MA[15..0] 9

DDR_B_BS#2 9
DDR_B_BS#1 9
DDR_B_BS#0 9

DDR_B_RAS# 9
DDR_B_CAS# 9
DDR_B_WE# 9

Processor DDR2 Memory Interface

DDR_B_D[63..0]9

To reverse SODIMM socket

DDR_B_DM[7..0]9 DDR_A_DM[7..0] 8

DDR_B_DQS79
DDR_B_DQS#79
DDR_B_DQS69
DDR_B_DQS#69
DDR_B_DQS59
DDR_B_DQS#59
DDR_B_DQS49
DDR_B_DQS#49
DDR_B_DQS39
DDR_B_DQS#39
DDR_B_DQS29
DDR_B_DQS#29
DDR_B_DQS19
DDR_B_DQS#19
DDR_B_DQS09
DDR_B_DQS#09

DDR_B_D63
DDR_B_D62
DDR_B_D61
DDR_B_D60
DDR_B_D59
DDR_B_D58
DDR_B_D57
DDR_B_D56
DDR_B_D55
DDR_B_D54
DDR_B_D53
DDR_B_D52
DDR_B_D51
DDR_B_D50
DDR_B_D49
DDR_B_D48
DDR_B_D47
DDR_B_D46
DDR_B_D45
DDR_B_D44
DDR_B_D43
DDR_B_D42
DDR_B_D41
DDR_B_D40
DDR_B_D39
DDR_B_D38
DDR_B_D37
DDR_B_D36
DDR_B_D35
DDR_B_D34
DDR_B_D33
DDR_B_D32
DDR_B_D31
DDR_B_D30
DDR_B_D29
DDR_B_D28
DDR_B_D27
DDR_B_D26
DDR_B_D25
DDR_B_D24
DDR_B_D23
DDR_B_D22
DDR_B_D21
DDR_B_D20
DDR_B_D19
DDR_B_D18
DDR_B_D17
DDR_B_D16
DDR_B_D15
DDR_B_D14
DDR_B_D13
DDR_B_D12
DDR_B_D11
DDR_B_D10
DDR_B_D9
DDR_B_D8
DDR_B_D7
DDR_B_D6
DDR_B_D5
DDR_B_D4
DDR_B_D3
DDR_B_D2
DDR_B_D1
DDR_B_D0

DDR_B_DM7
DDR_B_DM6
DDR_B_DM5
DDR_B_DM4
DDR_B_DM3
DDR_B_DM2
DDR_B_DM1
DDR_B_DM0

DDR_B_DQS7
DDR_B_DQS#7
DDR_B_DQS6
DDR_B_DQS#6
DDR_B_DQS5
DDR_B_DQS#5
DDR_B_DQS4
DDR_B_DQS#4
DDR_B_DQS3
DDR_B_DQS#3
DDR_B_DQS2
DDR_B_DQS#2
DDR_B_DQS1
DDR_B_DQS#1
DDR_B_DQS0
DDR_B_DQS#0

AD11
AF11
AF14
AE14

AB11
AC12
AF13
AF15
AF16
AC18
AF19
AD14
AC14
AE18
AD18
AD20
AC20
AF23
AF24
AF20
AE20
AD22
AC22
AE25
AD26
AA25
AA26
AE24
AD24
AA23
AA24

AD12
AC16
AE22
AB26

AF12
AE12
AE16
AD16
AF21
AF22
AC25
AC26

Y11

G24
G23
D26
C26
G26
G25
E24
E23
C24
B24
C20
B20
C25
D24
A21
D20
D18
C18
D14
C14
A20
A19
A16
A15
A13
D12
E11
G11
B14
A14
A11
C11

E25
A22
B16
A12

F26
E26
A24
A23
D16
C16
C12
B12

MB_DATA63
MB_DATA62
MB_DATA61
MB_DATA60
MB_DATA59
MB_DATA58
MB_DATA57
MB_DATA56
MB_DATA55
MB_DATA54
MB_DATA53
MB_DATA52
MB_DATA51
MB_DATA50
MB_DATA49
MB_DATA48
MB_DATA47
MB_DATA46
MB_DATA45
MB_DATA44
MB_DATA43
MB_DATA42
MB_DATA41
MB_DATA40
MB_DATA39
MB_DATA38
MB_DATA37
MB_DATA36
MB_DATA35
MB_DATA34
MB_DATA33
MB_DATA32
MB_DATA31
MB_DATA30
MB_DATA29
MB_DATA28
MB_DATA27
MB_DATA26
MB_DATA25
MB_DATA24
MB_DATA23
MB_DATA22
MB_DATA21
MB_DATA20
MB_DATA19
MB_DATA18
MB_DATA17
MB_DATA16
MB_DATA15
MB_DATA14
MB_DATA13
MB_DATA12
MB_DATA11
MB_DATA10
MB_DATA9
MB_DATA8
MB_DATA7
MB_DATA6
MB_DATA5
MB_DATA4
MB_DATA3
MB_DATA2
MB_DATA1
MB_DATA0

MB_DM7
MB_DM6
MB_DM5
MB_DM4
MB_DM3
MB_DM2
MB_DM1
MB_DM0

MB_DQS_H7
MB_DQS_L7
MB_DQS_H6
MB_DQS_L6
MB_DQS_H5
MB_DQS_L5
MB_DQS_H4
MB_DQS_L4
MB_DQS_H3
MB_DQS_L3
MB_DQS_H2
MB_DQS_L2
MB_DQS_H1
MB_DQS_L1
MB_DQS_H0
MB_DQS_L0

CPU1C

DDRII Data

Athlon 64 S1
Processor Socket

MA_DATA63
MA_DATA62
MA_DATA61
MA_DATA60
MA_DATA59
MA_DATA58
MA_DATA57
MA_DATA56
MA_DATA55
MA_DATA54
MA_DATA53
MA_DATA52
MA_DATA51
MA_DATA50
MA_DATA49
MA_DATA48
MA_DATA47
MA_DATA46
MA_DATA45
MA_DATA44
MA_DATA43
MA_DATA42
MA_DATA41
MA_DATA40
MA_DATA39
MA_DATA38
MA_DATA37
MA_DATA36
MA_DATA35
MA_DATA34
MA_DATA33
MA_DATA32
MA_DATA31
MA_DATA30
MA_DATA29
MA_DATA28
MA_DATA27
MA_DATA26
MA_DATA25
MA_DATA24
MA_DATA23
MA_DATA22
MA_DATA21
MA_DATA20
MA_DATA19
MA_DATA18
MA_DATA17
MA_DATA16
MA_DATA15
MA_DATA14
MA_DATA13
MA_DATA12
MA_DATA11
MA_DATA10

MA_DATA9
MA_DATA8
MA_DATA7
MA_DATA6
MA_DATA5
MA_DATA4
MA_DATA3
MA_DATA2
MA_DATA1
MA_DATA0

MA_DM7
MA_DM6
MA_DM5
MA_DM4
MA_DM3
MA_DM2
MA_DM1
MA_DM0

MA_DQS_H7

MA_DQS_L7

MA_DQS_H6

MA_DQS_L6

MA_DQS_H5

MA_DQS_L5

MA_DQS_H4

MA_DQS_L4

MA_DQS_H3

MA_DQS_L3

MA_DQS_H2

MA_DQS_L2

MA_DQS_H1

MA_DQS_L1

MA_DQS_H0

MA_DQS_L0

AA12
AB12
AA14
AB14
W11
Y12
AD13
AB13
AD15
AB15
AB17
Y17
Y14
W14
W16
AD17
Y18
AD19
AD21
AB21
AB18
AA18
AA20
Y20
AA22
Y22
W21
W22
AA21
AB22
AB24
Y24
H22
H20
E22
E21
J19
H24
F22
F20
C23
B22
F18
E18
E20
D22
C19
G18
G17
C17
F14
E14
H17
E17
E15
H15
E13
C13
H12
H11
G14
H14
F12
G12

Y13
AB16
Y19
AC24
F24
E19
C15
E12

W12
W13
Y15
W15
AB19
AB20
AD23
AC23
G22
G21
C22
C21
G16
G15
G13
H13

DDR_A_D63
DDR_A_D62
DDR_A_D61
DDR_A_D60
DDR_A_D59
DDR_A_D58
DDR_A_D57
DDR_A_D56
DDR_A_D55
DDR_A_D54
DDR_A_D53
DDR_A_D52
DDR_A_D51
DDR_A_D50
DDR_A_D49
DDR_A_D48
DDR_A_D47
DDR_A_D46
DDR_A_D45
DDR_A_D44
DDR_A_D43
DDR_A_D42
DDR_A_D41
DDR_A_D40
DDR_A_D39
DDR_A_D38
DDR_A_D37
DDR_A_D36
DDR_A_D35
DDR_A_D34
DDR_A_D33
DDR_A_D32
DDR_A_D31
DDR_A_D30
DDR_A_D29
DDR_A_D28
DDR_A_D27
DDR_A_D26
DDR_A_D25
DDR_A_D24
DDR_A_D23
DDR_A_D22
DDR_A_D21
DDR_A_D20
DDR_A_D19
DDR_A_D18
DDR_A_D17
DDR_A_D16
DDR_A_D15
DDR_A_D14
DDR_A_D13
DDR_A_D12
DDR_A_D11
DDR_A_D10
DDR_A_D9
DDR_A_D8
DDR_A_D7
DDR_A_D6
DDR_A_D5
DDR_A_D4
DDR_A_D3
DDR_A_D2
DDR_A_D1
DDR_A_D0

DDR_A_DM7
DDR_A_DM6
DDR_A_DM5
DDR_A_DM4
DDR_A_DM3
DDR_A_DM2
DDR_A_DM1
DDR_A_DM0

DDR_A_DQS7
DDR_A_DQS#7
DDR_A_DQS6
DDR_A_DQS#6
DDR_A_DQS5
DDR_A_DQS#5
DDR_A_DQS4
DDR_A_DQS#4
DDR_A_DQS3
DDR_A_DQS#3
DDR_A_DQS2
DDR_A_DQS#2
DDR_A_DQS1
DDR_A_DQS#1
DDR_A_DQS0
DDR_A_DQS#0

DDR_A_D[63..0] 8

DDR_A_DQS7 8
DDR_A_DQS#7 8
DDR_A_DQS6 8
DDR_A_DQS#6 8
DDR_A_DQS5 8
DDR_A_DQS#5 8
DDR_A_DQS4 8
DDR_A_DQS#4 8
DDR_A_DQS3 8
DDR_A_DQS#3 8
DDR_A_DQS2 8
DDR_A_DQS#2 8
DDR_A_DQS1 8
DDR_A_DQS#1 8
DDR_A_DQS0 8
DDR_A_DQS#0 8

To normal SODIMM socket

+1.8V

R35

1K_0402_1%

1 2

1 1

R34

1K_0402_1%

1 2

VDD_VREF_SUS_CPU

1

C661

2

0.1U_0402_16V7K~N

1

C53

C54

2

0.1U_0402_16V7K~N

LAYOUT:PLACE CLOSE TO CPU

A

+CPU_M_VREF

1

2

1000P_0402_50V7K~N

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2008/1/3 2009/01/3

Compal Secret Data

Deciphered Date

D

Title

Size Document Number Rev

Custom

Date: Sheet

A1

Athlon 64 S1g1

uPGA638
Top View

AF1

TURION64 DDRII MEMORY I/F

LA-4191P

E

A26

539Monday, January 14, 2008

0.3

of

5

+2.5VDDA

12

U21

1

IN

OUT

2

GND
SHDN3BYP

APL5312-25BI_SOT23-5

0.01U_0402_16V7K

CPU_PWRGD

LDT_STOP#

LDT_RST#

+1.8V

C432

5

4

2

1

1

2

R255
680_0402_5%

1 2

R51
680_0402_5%

1 2

R58
680_0402_5%

1 2

150U_D2_6.3VM

C444
1U_0603_10V6K

2007-01-17 ATI recommend 680 ohm

2007-11-12 delete 0 ohm

Resistor placed close to CPU, trace reference to GND,
keep spacing 30mil to other signal.

R253

+3VS +2.5VDDA

D D

C C

B B

12

0_0805_5%

C433

1U_0603_10V6K

470_0402_5%

2

1

R241

CPU_PWRGD15

LDT_STOP#11,15

LDT_RST#15

C457

CPU_SIC

12

R228
300_0402_5%

+

4

L35
LQG21F4R7N00_0805

1 2

1

2

4.7U_0805_6.3V6K~N

CPUCLK0_H13

CPUCLK0_L13

LAYOUT: ROUTE VDDA TRACE APPROX.
50 mils WIDE (USE 2x25 mil TRACES TO
EXIT BALL FIELD) AND 500 mils LONG.

0.5A

1

1

1

C458

2

2007-11-12 delete SIC/SID

place them to CPU within 1"

C459

C460

0.22U_0603_10V7K

2

2

3300P_0402_50V7K

3900P_0402_50V7K

1 2

C446

1 2

C445 3900P_0402_50V7K

CPU_+VDDA

+1.8V

12

R29

@

300_0402_5%

R234 44.2_0402_1%

+1.2V_HT

R233 44.2_0402_1%

12

R249
169_0402_1%

THERMDC_CPU
THERMDA_CPU

3

ATHLON Control and Debug

LDT_RST#
CPU_PWRGD
LDT_STOP#

CPU_SIC
CPU_SID

1 2
1 2

CPU_VDD_FB_H35
CPU_VDD_FB_L35

TP2

CPU_CLKIN_SC_P
CPU_CLKIN_SC_N

TP26

CPU_DBRDY
CPU_TMS

CPU_TCK
CPU_TRST#
CPU_TDI

CPU_TEST25_H_BYPASSCLK_H
CPU_TEST25_L_BYPASSCLK_L
CPU_TEST19_PLLTEST0
CPU_TEST18_PLLTEST1

CPU_HTREF1
CPU_HTREF0

VDDIOFB_H
VDDIOFB_L

F8

VDDA2

F9

VDDA1

B7

RESET_L

A7

PWROK

F10

LDTSTOP_L

AF4

SIC

AF5

SID

P6

HTREF1

R6

HTREF0

F6

VDD_FB_H

E6

VDD_FB_L

W9

VDDIO_FB_H

Y9

VDDIO_FB_L

A9

CLKIN_H

A8

CLKIN_L

G10

DBRDY

AA9

TMS

AC9

TCK

AD9

TRST_L

AF9

TDI
TEST25_HE9TEST29_H

E8

TEST25_L

G9

TEST19

H10

TEST18

AA7

TEST13

C2

TEST9

D7

TEST17

E7

TEST16

F7

TEST15

C7

TEST14

AC8

TEST12

C3

TEST7

AA6

TEST6

W7

THERMDC

W8

THERMDA

Y6

TEST3

AB6

TEST2

P20

RSVD0

P19

RSVD1

N20

RSVD2

N19

RSVD3

R26

RSVD4

R25

RSVD5

P22

RSVD6

R22

RSVD7

AMD NPT S1 SOCKET
Processor Socket

CPU1D

THERMTRIP_L

PROCHOT_L

VID5
VID4
VID3
VID2
VID1
VID0

CPU_PRESENT_L

PSI_L

DBREQ_L

TDO

TEST29_L

TEST24
TEST23

MISC

TEST22
TEST21
TEST20

TEST28_H

TEST28_L

TEST27
TEST26
TEST10

TEST8

RSVD8
RSVD9

RSVD10
RSVD11

RSVD12
RSVD13
RSVD14

RSVD15
RSVD16
RSVD17
RSVD18
RSVD19
RSVD20

2

+1.8V

12

12

R227

R221

CPU_THERMTRIP#_R

AF6

CPU_PROCHOT#_1.8

AC7

VID5

A5

VID4

C6

VID3

A6

VID2

A4

VID1

C5

VID0

B5

CPU_PRESENT#

AC6

CPU_PSI#

A3

CPU_DBREQ#

E10

CPU_TDO

AE9

CPU_TEST29_H_FBCLKOUT_P

C9

CPU_TEST29_L_FBCLKOUT_N

C8

ROUTE AS 80 Ohm DIFFERENTIAL PAIR
PLACE IT CLOSE TO CPU WITHIN 1"

AE7
AD7
AE8

CPU_TEST21_SCANEN

AB8
AF7

J7
H8
AF8

CPU_TEST26_BURNIN#

AE6
K8
C4

H16
B18

B3
C1

H6
G6
D5

R24
W18
R23
AA8
H18
H19

300_0402_5%

300_0402_5%

CPU_PSI#

+1.8V +3VALW

1 2

R254

2

Q41

300_0402_5%

1 2

3 1

MMBT3904_NL_SOT23

VID5 35
VID4 35
VID3 35
VID2 35
VID1 35
VID0 35

CPU_PROCHOT#_1.8

R44

80.6_0402_1%

1 2

2006-10-02 unpop (ATI recommend)

R229

R220

@

10K_0402_5%

4.7K_0402_5%

1 2

H_THERMTRIP# 16

MMBT3904_NL_SOT23

CPU_TEST26_BURNIN#
CPU_PRESENT#
CPU_TEST25_H_BYPASSCLK_H

CPU_TEST21_SCANEN
CPU_TEST19_PLLTEST0
CPU_TEST25_L_BYPASSCLK_L
CPU_TEST18_PLLTEST1

+1.8V

1 2

CPU_PH_G

@

2

Q40

3 1

@

1

+3VALW

R219

10K_0402_5%

R218

4.7K_0402_5%

@

1 2

CPU_PROCHOT#

R225 300_0402_5%

1 2

R224 1K_0402_5%

1 2

R45 510_0402_5%

1 2

R230 300_0402_5%

1 2

R47 300_0402_5%

1 2

R46 510_0402_5%

1 2

R50 300_0402_5%

1 2

+1.8V

R20220_0402_5%

R21220_0402_5%

R24220_0402_5%

R22220_0402_5%

R18220_0402_5%

12

12

12

12

12

HDT Connector

JHDT

2

1

4

3

6

CPU_DBREQ#
CPU_DBRDY
CPU_TCK
CPU_TMS
CPU_TDI
CPU_TRST#
CPU_TDO

NOTE: HDT TERMINATION IS REQUIRED
FOR REV. Ax SILICON ONLY.

2
1

+3VALW

B
A

A A

SB_PWRGD16,25

SB_PWRGD
LDT_RST#

Close to LDT_RST# trace

5

5

8

7

10

9

12

11

14

13

16

15

18

17

20

19

22

21

2423
26

SAMTEC_ASP-68200-07

@

5

U3

P

HDT_RST#

4

Y

G

NC7SZ08P5X_NL_SC70-5

3

@

HDT_RST#

4

THERMDA_CPU

2200P_0402_50V7K

THERMDC_CPU

EC_SMB_CK225,28
EC_SMB_DA225,28

1

C396

2

EC_SMB_CK2
EC_SMB_DA2

SMBus Address: 1001110X (b)

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2008/1/3 2009/01/3

Compal Secret Data

Deciphered Date

+3VS

U19

2

D+

3

ALERT#

D-

8

THERM#

SCLK

7

SDATA

ADM1032ARMZ MSOP 8P

2

1

C395

0.1U_0402_16V7K~N

2

1

VDD1

6
4
5

GND

Thermal Sensor

12

R232

10K_0402_5%@

THERM#

R231 0_0402_5%

@

Title

Size Document Number Rev

Custom

LA-4191P

Date: Sheet of

ADM1032

CPU_PROCHOT#

12

Compal Electronics, Inc.

TURION64 CTRL & ADM1032

1

639Monday, January 14, 2008

0.3

5

4

3

2

1

Ground

Athlon 64 S1
Processor Socket

CPU1F

VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77
VSS78
VSS79
VSS80
VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS97
VSS98

VSS99
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129

J6
J8
J10
J12
J14
J16
J18
K2
K7
K9
K11
K13
K15
K17
L6
L8
L10
L12
L14
L16
L18
M7
M9
M11
M17
N4
N8
N10
N16
N18
P2
P7
P9
P11
P17
R8
R10
R16
R18
T7
T9
T11
T13
T15
T17
U4
U6
U8
U10
U12
U14
U16
U18
V2
V7
V9
V11
V13
V15
V17
W6
Y21
Y23
N6

AA4

VSS1

AA11

VSS2

AA13

VSS3

AA15

VSS4

AA17

VSS5

AA19

AB23
AB25
AC11
AC13
AC15
AC17
AC19
AC21

AD25
AE11
AE13
AE15
AE17
AE19
AE21
AE23

VSS6

AB2

VSS7

AB7

VSS8

AB9

VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17

AD6

VSS18

AD8

VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27

B4

VSS28

B6

VSS29

B8

VSS30

B9

VSS31

B11

VSS32

B13

VSS33

B15

VSS34

B17

VSS35

B19

VSS36

B21

VSS37

B23

VSS38

B25

VSS39

D6

VSS40

D8

VSS41

D9

VSS42

D11

VSS43

D13

VSS44

D15

VSS45

D17

VSS46

D19

VSS47

D21

VSS48

D23

VSS49

D25

VSS50

E4

VSS51

F2

VSS52

F11

VSS53

F13

VSS54

F15

VSS55

F17

VSS56

F19

VSS57

F21

VSS58

F23

VSS59

F25

VSS60

H7

VSS61

H9

VSS62

H21

VSS63

H23

VSS64

J4

VSS65

+CPU_CORE +CPU_CORE

AC4

VDD1

+CPU_CORE

1

+

C385

2

AD2

VDD2

G4

VDD3

H2

VDD4

J9

VDD5

J11

VDD6

J13

VDD7

K6

VDD8

K10

VDD9

K12

VDD10

K14

VDD11

L4

VDD12

L7

VDD13

L9

VDD14

L11

VDD15

L13

VDD16

M2

VDD17

M6

VDD18

M8

VDD19

M10

VDD20

N7

VDD21

N9

VDD22

N11

VDD23

P8

VDD24

P10

VDD25

R4

VDD26

R7

VDD27

R9

VDD28

R11

VDD29

T2

VDD30

T6

VDD31

T8

VDD32

T10

VDD33

T12

VDD34

T14

VDD35

U7

VDD36

U9

VDD37

U11

VDD38

U13

VDD39

V6

VDD40

V8

VDD41

V10

VDD42

C386

330U_D2E_2.5VM

35A

D D

CPU BOTTOMSIDE DECOUPLING

+1.8V

1

C69

C101

2

22U_0805_6.3V6M

C C

B B

+CPU_CORE

1

C665

2

+CPU_CORE

1

C674

2

22U_0805_6.3V6M

0.22U_0603_10V7K

C666

C675

1

1

1

C667

C668

2

2

1

2

22U_0805_6.3V6M

22U_0805_6.3V6M

1

C677

C676

2

0.22U_0603_10V7K

0.01U_0402_16V7K

1

C669

2

22U_0805_6.3V6M

1

2

180P_0402_50V8J~N

1

C670

2

2

22U_0805_6.3V6M

1

1

C403

2

22U_0805_6.3V6M

1

C671

2

22U_0805_6.3V6M

2

C672

22U_0805_6.3V6M

C398

0.22U_0603_10V7K

1

2

0.22U_0603_10V7K

1

1

C673

2

2

22U_0805_6.3V6M

22U_0805_6.3V6M

1

+

C696

2

@

330U_D2E_2.5VM

Athlon 64 S1
Processor Socket

1

+

2

330U_D2E_2.5VM

CPU1E

VDD43
VDD44
VDD45
VDD46
VDD47
VDD48
VDD49
VDD50
VDD51
VDD52
VDD53
VDD54

VDDIO1
VDDIO2
VDDIO3
VDDIO4
VDDIO5
VDDIO6
VDDIO7
VDDIO8
VDDIO9

VDDIO10

Power

VDDIO11
VDDIO12
VDDIO13
VDDIO14
VDDIO15
VDDIO16
VDDIO17
VDDIO18
VDDIO19
VDDIO20
VDDIO21
VDDIO22
VDDIO23
VDDIO24
VDDIO25
VDDIO26
VDDIO27

1

+

C678

2

V12
V14
W4
Y2
J15
K16
L15
M16
P16
T16
U15
V16

H25
J17
K18
K21
K23
K25
L17
M18
M21
M23
M25
N17
P18
P21
P23
P25
R17
T18
T21
T23
T25
U17
V18
V21
V23
V25
Y25

820U_E9_2.5V_M_R7

C679

+1.8V

6A (with DDR)

1

+

2

820U_E9_2.5V_M_R7

DECOUPLING BETWEEN PROCESSOR AND DIMMs
PLACE CLOSE TO PROCESSOR AS POSSIBLE

+1.8V

1

1

1

C49

C397

2

4.7U_0805_6.3V6K~N

A A

1

C125

C423

2

2

4.7U_0805_6.3V6K~N

4.7U_0805_6.3V6K~N

5

1

C408

2

4.7U_0805_6.3V6K~N

1

C102

C401

2

2

0.22U_0603_10V7K

0.22U_0603_10V7K

1

1

C404

2

2

0.22U_0603_10V7K

C90

C91

0.22U_0603_10V7K

0.01U_0402_16V7K

1

C70

C89

2

0.01U_0402_16V7K
180P_0402_50V8J~N

4

1

1

C662

2

180P_0402_50V8J~N

1

C663

2

2

180P_0402_50V8J~N

180P_0402_50V8J~N

+0.9V

1

C461

C447

2

4.7U_0805_6.3V6K~N

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

DECOUPLING BETWEEN PROCESSOR AND DIMMs
PLACE CLOSE TO PROCESSOR AS POSSIBLE

1

1

C52

C111

2

2

4.7U_0805_6.3V6K~N

4.7U_0805_6.3V6K~N

2008/1/3 2009/01/3

1

1

C448

2

2

4.7U_0805_6.3V6K~N

Compal Secret Data

C464

0.22U_0603_10V7K

1

C390

2

0.22U_0603_10V7K

Deciphered Date

1

1

C387

C389

2

2

0.22U_0603_10V7K

2

C435

C436

0.22U_0603_10V7K
1000P_0402_50V7K~N

1000P_0402_50V7K~N

2

C434

1000P_0402_50V7K~N

Title

Size Document Number Rev

Custom

Date: Sheet

1

180P_0402_50V8J~N

1000P_0402_50V7K~N

Compal Electronics, Inc.

LA-4191P

2

C462

C437

2

C463

1

1

180P_0402_50V8J~N

TURION64 PWR & GND

1

C388

180P_0402_50V8J~N

2

1

180P_0402_50V8J~N

of

739Monday, January 14, 2008

0.3

5

4

3

+1.8V+DIMM_VREF+1.8V+1.8V

2

1

JDIM1

1

VREF

3

DDR_A_D0

D D

C C

DDR_CKE0_DIMMA5
DDR_CS2_DIMMA#5

DDR_A_BS#25

DDR_A_BS#05
DDR_A_WE#5

DDR_A_CAS#5
DDR_CS1_DIMMA#5

DDR_A_ODT15

B B

A A

SMB_CK_DAT19,13,16,26

SMB_CK_CLK19,13,16,26

DDR_A_D1
DDR_A_DQS#0

DDR_A_DQS0
DDR_A_D2

DDR_A_D3
DDR_A_D8

DDR_A_D9
DDR_A_DQS#1

DDR_A_DQS1
DDR_A_D10

DDR_A_D11

DDR_A_D16
DDR_A_D17

DDR_A_DQS#2
DDR_A_DQS2

DDR_A_D18 DDR_A_D22
DDR_A_D19

DDR_A_D24
DDR_A_D25

DDR_A_DM3

DDR_A_D26
DDR_A_D27

DDR_CKE0_DIMMA
DDR_CS2_DIMMA#

DDR_A_BS#2
DDR_A_MA12

DDR_A_MA9

DDR_A_MA5
DDR_A_MA3
DDR_A_MA1

DDR_A_MA10
DDR_A_BS#0
DDR_A_WE#

DDR_A_CAS#
DDR_CS1_DIMMA#

DDR_A_ODT1
DDR_A_D37

DDR_A_D36
DDR_A_DQS#4

DDR_A_DQS4
DDR_A_D34

DDR_A_D35
DDR_A_D40

DDR_A_D41
DDR_A_DM5
DDR_A_D42

DDR_A_D43 DDR_A_D47
DDR_A_D48

DDR_A_D49 DDR_A_D53

DDR_A_DQS#6
DDR_A_DQS6

DDR_A_D50
DDR_A_D51 DDR_A_D55

DDR_A_D56
DDR_A_D57

DDR_A_DM7
DDR_A_D58

DDR_A_D59
SMB_CK_DAT1

SMB_CK_CLK1

+3VS

5

VSS

5

DQ0

7

DQ1

9

VSS

11

DQS0#

13

DQS0

15

VSS

17

DQ2

19

DQ3

21

VSS

23

DQ8

25

DQ9

27

VSS

29

DQS1#

31

DQS1

33

VSS

35

DQ10

37

DQ11

39

VSS

41

VSS

43

DQ16

45

DQ17

47

VSS

49

DQS2#

51

DQS2

53

VSS

55

DQ18

57

DQ19

59

VSS

61

DQ24

63

DQ25

65

VSS

67

DM3

69

NC

71

VSS

73

DQ26

75

DQ27

77

VSS

79

CKE0

81

VDD

83

NC

85

BA2

87

VDD

89

A12

91

A9

93

A8

95

VDD

97

A5

99

A3

101

A1

103

VDD

105

A10/AP

107

BA0

109

WE#

111

VDD

113

CAS#

115

NC/S1#

117

VDD

119

NC/ODT1

121

VSS

123

DQ32

125

DQ33

127

VSS

129

DQS4#

131

DQS4

133

VSS

135

DQ34

137

DQ35

139

VSS

141

DQ40

143

DQ41

145

VSS

147

DM5

149

VSS

151

DQ42

153

DQ43

155

VSS

157

DQ48

159

DQ49

161

VSS

163

NC,TEST

165

VSS

167

DQS6#

169

DQS6

171

VSS

173

DQ50

175

DQ51

177

VSS

179

DQ56

181

DQ57

183

VSS

185

DM7

187

VSS

189

DQ58

191

DQ59

193

VSS

195

SDA

197

SCL

199

VDDSPD

FOX_ASOA426-M2RN-7F

CONN@

DQ4
DQ5
VSS
DM0
VSS
DQ6
DQ7

VSS
DQ12
DQ13

VSS

DM1

VSS

CK0

CK0#

VSS
DQ14
DQ15

VSS

VSS
DQ20
DQ21

VSS

DM2

VSS
DQ22
DQ23

VSS
DQ28
DQ29

VSS

DQS3#

DQS3

VSS
DQ30
DQ31

VSS

NC/CKE1

VDD

NC/A15
NC/A14

VDD

VDD

VDD

RAS#

VDD
ODT0

NC/A13

VDD

VSS
DQ36
DQ37

VSS

DM4

VSS
DQ38
DQ39

VSS
DQ44
DQ45

VSS

DQS5#

DQS5

VSS
DQ46
DQ47

VSS
DQ52
DQ53

VSS

CK1

CK1#

VSS

DM6

VSS
DQ54
DQ55

VSS
DQ60
DQ61

VSS

DQS7#

DQS7

VSS
DQ62
DQ63

VSS

VSS

A11

BA1
S0#

SA0
SA1

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

42
44
46
48
50

NC

52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92

A7

94

A6

96
98

A4

100

A2

102

A0

104
106
108
110
112
114
116
118
120

NC

122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200

4

DDR_A_D4
DDR_A_D5

DDR_A_DM0
DDR_A_D6

DDR_A_D7
DDR_A_D12

DDR_A_D13
DDR_A_DM1
DDR_A_CLK1

DDR_A_CLK#1
DDR_A_D14

DDR_A_D15

DDR_A_D20
DDR_A_D21

DDR_A_DM2

DDR_A_D23
DDR_A_D28

DDR_A_D29
DDR_A_DQS#3

DDR_A_DQS3
DDR_A_D30

DDR_A_D31
DDR_CKE1_DIMMA
DDR_A_MA15

DDR_A_MA14
DDR_A_MA11

DDR_A_MA7
DDR_A_MA6DDR_A_MA8

DDR_A_MA4
DDR_A_MA2
DDR_A_MA0

DDR_A_BS#1
DDR_A_RAS#
DDR_CS0_DIMMA#

DDR_A_ODT0
DDR_A_MA13

DDR_CS3_DIMMA#
DDR_A_D32

DDR_A_D33
DDR_A_DM4
DDR_A_D38

DDR_A_D39
DDR_A_D44

DDR_A_D45
DDR_A_DQS#5

DDR_A_DQS5
DDR_A_D46

DDR_A_D52

DDR_A_CLK2
DDR_A_CLK#2

DDR_A_DM6
DDR_A_D54

DDR_A_D60
DDR_A_D61

DDR_A_DQS#7
DDR_A_DQS7

DDR_A_D62
DDR_A_D63

R28 0_0402_5%

12
12

R25 0_0402_5%

DDR_A_CLK1 5
DDR_A_CLK#1 5

DDR_CKE1_DIMMA 5

DDR_A_BS#1 5
DDR_A_RAS# 5
DDR_CS0_DIMMA# 5

DDR_A_ODT0 5

DDR_CS3_DIMMA# 5

KH4 JBL30
D32->D37
D33->D36
D36->D32
D37->D33

DDR_A_CLK2 5
DDR_A_CLK#2 5

C181

DDR_A_D[0..63]5

DDR_A_DM[0..7]5

DDR_A_DQS[0..7]5

DDR_A_MA[0..15]5

DDR_A_DQS#[0..7]5

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

1

C179

2

0.1U_0402_16V7K~N

1

1

C180

2

2

0.1U_0402_16V7K~N

1000P_0402_50V7K~N

R78
1K_0402_1%

1 2

R79

1K_0402_1%

1 2

DDR_A_D[0..63]
DDR_A_DM[0..7]
DDR_A_DQS[0..7]
DDR_A_MA[0..15]
DDR_A_DQS#[0..7]

+0.9V +0.9V

330U_D2E_2.5VM

1

C47

+

2

2008/1/3 2009/01/3

Compal Secret Data

Deciphered Date

2

+1.8V

330U_D2E_2.5VM

1

C166

+

2

DDR_A_MA6
DDR_A_MA4
DDR_A_MA11
DDR_A_MA14

DDR_A_MA1
DDR_A_MA10
DDR_A_BS#0
DDR_A_WE#

DDR_CS0_DIMMA#
DDR_A_MA0
DDR_A_BS#1
DDR_A_MA2

DDR_A_MA9
DDR_A_MA8
DDR_A_MA5
DDR_A_MA3

DDR_A_MA7
DDR_A_MA15
DDR_CKE1_DIMMA

DDR_A_CAS#
DDR_CS1_DIMMA#

DDR_A_ODT1

DDR_CS3_DIMMA#
DDR_A_ODT0
DDR_A_MA13
DDR_A_RAS#

DDR_CKE0_DIMMA
DDR_CS2_DIMMA#
DDR_A_BS#2
DDR_A_MA12

Layout Note:
Place one cap close to every 2 pullup
resistors terminated to +0.9V

RP14

18
27
36

47_0804_8P4R_5%

47_0804_8P4R_5%

47_0804_8P4R_5%

47_0804_8P4R_5%

47_0804_8P4R_5%

47_0804_8P4R_5%

47_0804_8P4R_5%

47_0804_8P4R_5%

Title

Size Document Number Rev

Custom

Date: Sheet

45

RP5

18
27
36
45

RP6

18
27
36
45

RP9

18
27
36
45

RP10

18
27
36
45

RP1

18
27
36
45

RP2

18
27
36
45

RP13

18
27
36
45

DDR2 SODIMM-I Socket

LA-4191P

C95 0.1U_0402_16V7K~N

12

C107 0.1U_0402_16V7K~N

1 2

C103 0.1U_0402_16V7K~N

12

C81 0.1U_0402_16V7K~N

1 2

C104 0.1U_0402_16V7K~N

12

C72 0.1U_0402_16V7K~N

1 2

C93 0.1U_0402_16V7K~N

12

C51 0.1U_0402_16V7K~N

1 2

C71 0.1U_0402_16V7K~N

12

C82 0.1U_0402_16V7K~N

1 2

C94 0.1U_0402_16V7K~N

12

C58 0.1U_0402_16V7K~N

1 2

C80 0.1U_0402_16V7K~N

12

C59 0.1U_0402_16V7K~N

1 2

C132 0.1U_0402_16V7K~N

12

C106 0.1U_0402_16V7K~N

1 2

of

1

839Monday, January 14, 2008

+1.8V

0.3

5

JDIM2

1

VREF

3

DDR_B_D0

D D

KH4 JBL30
D10->D14
D11->D15
D14->D11
D15->D10

C C

DDR_CKE0_DIMMB5
DDR_CS2_DIMMB#5

DDR_B_BS#25

DDR_B_BS#05
DDR_B_WE#5

DDR_B_CAS#5
DDR_CS1_DIMMB#5

DDR_B_ODT15

B B

A A

SMB_CK_DAT18,13,16,26

SMB_CK_CLK18,13,16,26

DDR_B_D1
DDR_B_DQS#0

DDR_B_DQS0
DDR_B_D2

DDR_B_D3
DDR_B_D8

DDR_B_D9
DDR_B_DQS#1

DDR_B_DQS1
DDR_B_D14

DDR_B_D16
DDR_B_D17

DDR_B_DQS#2
DDR_B_DQS2

DDR_B_D18 DDR_B_D22
DDR_B_D19

DDR_B_D24
DDR_B_D25

DDR_B_DM3

DDR_B_D26
DDR_B_D27

DDR_CKE0_DIMMB
DDR_CS2_DIMMB#

DDR_B_BS#2
DDR_B_MA12

DDR_B_MA9

DDR_B_MA5
DDR_B_MA3
DDR_B_MA1

DDR_B_MA10
DDR_B_BS#0
DDR_B_WE#

DDR_B_CAS#
DDR_CS1_DIMMB#

DDR_B_ODT1
DDR_B_D32

DDR_B_D33
DDR_B_DQS#4

DDR_B_DQS4
DDR_B_D34

DDR_B_D35
DDR_B_D40

DDR_B_D41
DDR_B_DM5
DDR_B_D42

DDR_B_D43 DDR_B_D47
DDR_B_D48

DDR_B_D49 DDR_B_D53

DDR_B_DQS#6
DDR_B_DQS6

DDR_B_D50
DDR_B_D51 DDR_B_D55

DDR_B_D56
DDR_B_D57

DDR_B_DM7
DDR_B_D58

DDR_B_D59
SMB_CK_DAT1

SMB_CK_CLK1

+3VS

5

VSS

5

DQ0

7

DQ1

9

VSS

11

DQS0#

13

DQS0

15

VSS

17

DQ2

19

DQ3

21

VSS

23

DQ8

25

DQ9

27

VSS

29

DQS1#

31

DQS1

33

VSS

35

DQ10

37

DQ11

39

VSS

41

VSS

43

DQ16

45

DQ17

47

VSS

49

DQS2#

51

DQS2

53

VSS

55

DQ18

57

DQ19

59

VSS

61

DQ24

63

DQ25

65

VSS

67

DM3

69

NC

71

VSS

73

DQ26

75

DQ27

77

VSS

79

CKE0

81

VDD

83

NC

85

BA2

87

VDD

89

A12

91

A9

93

A8

95

VDD

97

A5

99

A3

101

A1

103

VDD

105

A10/AP

107

BA0

109

WE#

111

VDD

113

CAS#

115

NC/S1#

117

VDD

119

NC/ODT1

121

VSS

123

DQ32

125

DQ33

127

VSS

129

DQS4#

131

DQS4

133

VSS

135

DQ34

137

DQ35

139

VSS

141

DQ40

143

DQ41

145

VSS

147

DM5

149

VSS

151

DQ42

153

DQ43

155

VSS

157

DQ48

159

DQ49

161

VSS

163

NC,TEST

165

VSS

167

DQS6#

169

DQS6

171

VSS

173

DQ50

175

DQ51

177

VSS

179

DQ56

181

DQ57

183

VSS

185

DM7

187

VSS

189

DQ58

191

DQ59

193

VSS

195

SDA

197

SCL

199

VDDSPD

FOX_AS0A426-NARN-7F~N

CONN@

VSS

DQ4

DQ5

VSS

DM0

VSS

DQ6

DQ7

VSS
DQ12
DQ13

VSS

DM1

VSS

CK0

CK0#

VSS
DQ14
DQ15

VSS

VSS
DQ20
DQ21

VSS

DM2

VSS
DQ22
DQ23

VSS
DQ28
DQ29

VSS

DQS3#

DQS3

VSS
DQ30
DQ31

VSS

NC/CKE1

VDD

NC/A15
NC/A14

VDD

VDD

VDD

RAS#

VDD
ODT0

NC/A13

VDD

VSS
DQ36
DQ37

VSS

DM4

VSS
DQ38
DQ39

VSS
DQ44
DQ45

VSS

DQS5#

DQS5

VSS
DQ46
DQ47

VSS
DQ52
DQ53

VSS

CK1

CK1#

VSS

DM6

VSS
DQ54
DQ55

VSS
DQ60
DQ61

VSS

DQS7#

DQS7

VSS
DQ62
DQ63

VSS

SAO

4

+DIMM_VREF+1.8V+1.8V

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

42
44
46
48
50

NC

52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90

A11

92

A7

94

A6

96
98

A4

100

A2

102

A0

104
106

BA1

108
110

S0#

112
114
116
118
120

NC

122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200

SA1

4

DDR_B_D4
DDR_B_D5

DDR_B_DM0
DDR_B_D6

DDR_B_D7
DDR_B_D12

DDR_B_D13
DDR_B_DM1
DDR_B_CLK1

DDR_B_CLK#1
DDR_B_D11

DDR_B_D10DDR_B_D15

DDR_B_D20
DDR_B_D21

DDR_B_DM2

DDR_B_D23
DDR_B_D28

DDR_B_D29
DDR_B_DQS#3

DDR_B_DQS3
DDR_B_D30

DDR_B_D31
DDR_CKE1_DIMMB
DDR_B_MA15

DDR_B_MA14
DDR_B_MA11

DDR_B_MA7
DDR_B_MA6DDR_B_MA8

DDR_B_MA4
DDR_B_MA2
DDR_B_MA0

DDR_B_BS#1
DDR_B_RAS#
DDR_CS0_DIMMB#

DDR_B_ODT0
DDR_B_MA13

DDR_CS3_DIMMB#
DDR_B_D37

DDR_B_D36
DDR_B_DM4
DDR_B_D38

DDR_B_D39
DDR_B_D44

DDR_B_D45
DDR_B_DQS#5

DDR_B_DQS5
DDR_B_D46

DDR_B_D52

DDR_B_CLK2
DDR_B_CLK#2

DDR_B_DM6
DDR_B_D54

DDR_B_D60
DDR_B_D61

DDR_B_DQS#7
DDR_B_DQS7

DDR_B_D62
DDR_B_D63

R26 4.7K_0402_5%

1 2

R27 0_0402_5%

12

DDR_B_CLK1 5
DDR_B_CLK#1 5

DDR_CKE1_DIMMB 5

DDR_B_BS#1 5
DDR_B_RAS# 5
DDR_CS0_DIMMB# 5

DDR_B_ODT0 5

DDR_CS3_DIMMB# 5

D36,D37 swap

DDR_B_CLK2 5
DDR_B_CLK#2 5

+3VS

3

1

C182

2

1000P_0402_50V7K~N

DDR_B_D[0..63]5
DDR_B_DM[0..7]5

DDR_B_DQS[0..7]5
DDR_B_MA[0..15]5

DDR_B_DQS#[0..7]5

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

DDR_B_D[0..63]
DDR_B_DM[0..7]
DDR_B_DQS[0..7]
DDR_B_MA[0..15]
DDR_B_DQS#[0..7]

2008/1/3 2009/01/3

+1.8V

330U_D2E_2.5VM

1

C92

+

2

Compal Secret Data

Deciphered Date

2

2

DDR_CKE1_DIMMB
DDR_B_MA14
DDR_B_MA15
DDR_B_MA11

DDR_B_MA9
DDR_B_MA12
DDR_B_MA1
DDR_B_MA3

DDR_B_MA10
DDR_B_BS#0
DDR_B_WE#
DDR_B_MA5

DDR_B_MA0
DDR_B_BS#1
DDR_B_RAS#
DDR_CS0_DIMMB#

DDR_B_MA13
DDR_B_ODT0
DDR_CS3_DIMMB#

DDR_CS1_DIMMB#
DDR_B_ODT1
DDR_B_CAS#

DDR_B_MA7
DDR_B_MA6
DDR_B_MA2
DDR_B_MA4

DDR_CS2_DIMMB#
DDR_CKE0_DIMMB
DDR_B_BS#2
DDR_B_MA8

1

Layout Note:
Place one cap close to every 2 pullup
resistors terminated to +0.9V

+0.9V

RP16

18
27
36

47_0804_8P4R_5%

47_0804_8P4R_5%

47_0804_8P4R_5%

47_0804_8P4R_5%

47_0804_8P4R_5%

47_0804_8P4R_5%

47_0804_8P4R_5%

47_0804_8P4R_5%

45

RP11

18
27
36
45

RP7

18
27
36
45

RP8

18
27
36
45

RP4

18
27
36
45

RP3

18
27
36
45

RP12

18
27
36
45

RP15

18
27
36
45

Title

Size Document Number Rev

Custom

Date: Sheet

C76 0.1U_0402_16V7K~N

12

C112 0.1U_0402_16V7K~N

1 2

C78 0.1U_0402_16V7K~N

12

C97 0.1U_0402_16V7K~N

1 2

C57 0.1U_0402_16V7K~N

12

C86 0.1U_0402_16V7K~N

1 2

C79 0.1U_0402_16V7K~N

12

C75 0.1U_0402_16V7K~N

1 2

C66 0.1U_0402_16V7K~N

12

C64 0.1U_0402_16V7K~N

1 2

C65 0.1U_0402_16V7K~N

12

C63 0.1U_0402_16V7K~N

1 2

C105 0.1U_0402_16V7K~N

12

C98 0.1U_0402_16V7K~N

1 2

C56 0.1U_0402_16V7K~N

12

C110 0.1U_0402_16V7K~N

1 2

DDR2 SODIMM-II Socket

LA-4191P

1

+1.8V

0.3

of

939Monday, January 14, 2008

5

D D

4

3

2

1

H_CADIP[0..15]4
H_CADIN[0..15]4

H_CLKOP1
H_CLKON1

H_CLKOP0
H_CLKON0

H_CTLOP0
H_CTLON0

H_CADOP[0..15]4
H_CADON[0..15]4

U690A

R19

HT_RXCAD15P

R18

HT_RXCAD15N

R21

HT_RXCAD14P

R22

HT_RXCAD14N

U22

HT_RXCAD13P

U21

HT_RXCAD13N

U18

HT_RXCAD12P

U19

HT_RXCAD12N

W19

HT_RXCAD11P

W20

HT_RXCAD11N

AC21

HT_RXCAD10P

AB22

HT_RXCAD10N

AB20

HT_RXCAD9P

AA20

HT_RXCAD9N

AA19

HT_RXCAD8P

Y19

HT_RXCAD8N

T24

HT_RXCAD7P

R25

HT_RXCAD7N

U25

HT_RXCAD6P

U24

HT_RXCAD6N

V23

HT_RXCAD5P

U23

HT_RXCAD5N

V24

HT_RXCAD4P

V25

HT_RXCAD4N

AA25

HT_RXCAD3P

AA24

HT_RXCAD3N

AB23

HT_RXCAD2P

AA23

HT_RXCAD2N

AB24

HT_RXCAD1P

AB25

HT_RXCAD1N

AC24

HT_RXCAD0P

AC25

HT_RXCAD0N

W21

HT_RXCLK1P

W22

HT_RXCLK1N

Y24

HT_RXCLK0P

W25

HT_RXCLK0N

P24

HT_RXCTLP

P25

HT_RXCTLN

A24

HT_RXCALP

C24

HT_RXCALN

216MQA6AVA11FG FCBGA 465P

U690B

G5
G4

J8
J7
J4
J5
L8
L7
L4

L5
M8
M7
M4

C C

PCIE_LAN_C_RX_P221
PCIE_LAN_C_RX_N221

PCIE_WLAN_C_RX_P124
PCIE_WLAN_C_RX_N124

SB_RX2P15
SB_RX2N15

SB_RX3P15

B B

SB_RX3N15

SB_RX0P15
SB_RX0N15

SB_RX1P15
SB_RX1N15

PCIE_LAN_C_RX_P2
PCIE_LAN_C_RX_N2

PCIE_WLAN_C_RX_P1
PCIE_WLAN_C_RX_N1

SB_RX2P
SB_RX2N

SB_RX3P
SB_RX3N

SB_RX0P
SB_RX0N

SB_RX1P
SB_RX1N

M5

P8

P7

P4

P5

R4
R5
R7
R8
U4

U5
W4
W5

Y4

Y5

V9
W9

AB7
AB6

Y7

AA7
AB9

AA9

W11
W12

AA11
AB11

W14
W15

AB12
AA12

AA14
AB14

216MQA6AVA11FG FCBGA 465P

PART 2 OF 5

GFX_RX0P
GFX_RX0N
GFX_RX1P
GFX_RX1N
GFX_RX2P
GFX_RX2N
GFX_RX3P
GFX_RX3N
GFX_RX4P
GFX_RX4N
GFX_RX5P
GFX_RX5N
GFX_RX6P
GFX_RX6N
GFX_RX7P
GFX_RX7N
GFX_RX8P
GFX_RX8N
GFX_RX9P
GFX_RX9N
GFX_RX10P
GFX_RX10N
GFX_RX11P
GFX_RX11N
GFX_RX12P
GFX_RX12N
GFX_RX13P
GFX_RX13N
GFX_RX14P
GFX_RX14N
GFX_RX15P
GFX_RX15N

GPP_RX2P
GPP_RX2N

GPP_RX3P

PCIE I/F GPP

GPP_RX3N
GPP_RX0P(SB_RX2P)

GPP_RX0N(SB_RX2N)

GPP_RX1P(SB_RX3P)
GPP_RX1N(SB_RX3N)

SB_RX0P
SB_RX0N

PCIE I/F SB

SB_RX1P
SB_RX1N

PCE_ISET(NC)
PCE_TXISET(NC)

PCIE GFX I/F

GPP_TX0P(SB_TX2P)
GPP_TX0N(SB_TX2N)

GPP_TX1P(SB_TX3P)
GPP_TX1N(SB_TX3N)

PCE_PCAL(PCE_CALRP)
PCE_NCAL(PCE_CALRN)

GFX_TX0P
GFX_TX0N
GFX_TX1P
GFX_TX1N
GFX_TX2P
GFX_TX2N
GFX_TX3P
GFX_TX3N
GFX_TX4P
GFX_TX4N
GFX_TX5P
GFX_TX5N
GFX_TX6P
GFX_TX6N
GFX_TX7P
GFX_TX7N
GFX_TX8P
GFX_TX8N
GFX_TX9P

GFX_TX9N
GFX_TX10P
GFX_TX10N
GFX_TX11P
GFX_TX11N
GFX_TX12P
GFX_TX12N
GFX_TX13P
GFX_TX13N
GFX_TX14P
GFX_TX14N
GFX_TX15P
GFX_TX15N

GPP_TX2P

GPP_TX2N

GPP_TX3P

GPP_TX3N

SB_TX0P
SB_TX0N

SB_TX1P
SB_TX1N

J1
H2
K2
K1
K3
L3
L1
L2
N2
N1
P2
P1
P3
R3
R1
R2
T2
U1
V2
V1
V3
W3
W1
W2
Y2
AA1
AA2
AB2
AB1
AC1
AE3
AE4

PCIE_LAN_TX_P2

AD4
AE5

AD5

PCIE_WLAN_TX_N1

AD6

SB_TX2P_C

AD8

SB_TX2N_C

AE8

SB_TX3P_C

AD7

SB_TX3N_C

AE7

SB_TX0P_C

AE9

SB_TX0N_C

AD10

SB_TX1P_C

AC8

SB_TX1N_C

AD9

R238 562_0402_1%

AD11

R237 2K_0402_1%

AE11

1 2
1 2

C415 0.1U_0402_16V7K~N
C416 0.1U_0402_16V7K~N

C413 0.1U_0402_16V7K~N
C414 0.1U_0402_16V7K~N

C417 0.1U_0402_16V7K~N
C418 0.1U_0402_16V7K~N

C119 0.1U_0402_16V7K~N
C120 0.1U_0402_16V7K~N

C411 0.1U_0402_16V7K~N

1 2

C412 0.1U_0402_16V7K~N

1 2

C117 0.1U_0402_16V7K~N

1 2

C118 0.1U_0402_16V7K~N

1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

+VDDA12_PKG2

PCIE_LAN_C_TX_P2
PCIE_LAN_C_TX_N2PCIE_LAN_TX_N2

PCIE_WLAN_C_TX_P1PCIE_WLAN_TX_P1
PCIE_WLAN_C_TX_N1

SB_TX2P
SB_TX2N

SB_TX3P
SB_TX3N

SB_TX0P
SB_TX0N

SB_TX1P
SB_TX1N

SB_TX2P 15
SB_TX2N 15

SB_TX3P 15
SB_TX3N 15

SB_TX0P 15
SB_TX0N 15

SB_TX1P 15
SB_TX1N 15

PCIE_LAN_C_TX_P2 21
PCIE_LAN_C_TX_N2 21

PCIE_WLAN_C_TX_P1 24
PCIE_WLAN_C_TX_N1 24

+VDDHT_PKG

H_CLKOP14

H_CLKON14

H_CLKOP04

H_CLKON04

H_CTLOP04
H_CTLON04

R282 49.9_0402_1%

1 2

R261 49.9_0402_1%

1 2

H_CADOP15
H_CADON15
H_CADOP14
H_CADON14
H_CADOP13
H_CADON13
H_CADOP12
H_CADON12
H_CADOP11
H_CADON11
H_CADOP10
H_CADON10
H_CADOP9
H_CADON9
H_CADOP8
H_CADON8

H_CADOP7
H_CADON7
H_CADOP6
H_CADON6
H_CADOP5
H_CADON5
H_CADOP4
H_CADON4
H_CADOP3
H_CADON3
H_CADOP2
H_CADON2
H_CADOP1
H_CADON1
H_CADOP0
H_CADON0

H_CADIP[0..15]
H_CADIN[0..15]

H_CADOP[0..15]

H_CADON[0..15]

PART 1 OF 5

HT_TXCAD15P
HT_TXCAD15N
HT_TXCAD14P
HT_TXCAD14N
HT_TXCAD13P
HT_TXCAD13N
HT_TXCAD12P
HT_TXCAD12N
HT_TXCAD11P
HT_TXCAD11N
HT_TXCAD10P
HT_TXCAD10N

HT_TXCAD9P
HT_TXCAD9N
HT_TXCAD8P
HT_TXCAD8N

HT_TXCAD7P
HT_TXCAD7N
HT_TXCAD6P
HT_TXCAD6N
HT_TXCAD5P
HT_TXCAD5N
HT_TXCAD4P
HT_TXCAD4N
HT_TXCAD3P
HT_TXCAD3N
HT_TXCAD2P
HT_TXCAD2N
HT_TXCAD1P
HT_TXCAD1N
HT_TXCAD0P
HT_TXCAD0N

HT_TXCLK1P
HT_TXCLK1N

HT_TXCLK0P
HT_TXCLK0N

HYPER TRANSPORT I/F

HT_TXCTLP
HT_TXCTLN

HT_TXCALP
HT_TXCALN

H_CADIP15

P21

H_CADIN15

P22

H_CADIP14

P18

H_CADIN14

P19

H_CADIP13

M22

H_CADIN13

M21

H_CADIP12

M18

H_CADIN12

M19

H_CADIP11

L18

H_CADIN11

L19

H_CADIP10

G22

H_CADIN10

G21

H_CADIP9

J20

H_CADIN9

J21

H_CADIP8

F21

H_CADIN8

F22

H_CADIP7

N24

H_CADIN7

N25

H_CADIP6

L25

H_CADIN6

M24

H_CADIP5

K25

H_CADIN5

K24

H_CADIP4

J23

H_CADIN4

K23

H_CADIP3

G25

H_CADIN3

H24

H_CADIP2

F25

H_CADIN2

F24

H_CADIP1

E23

H_CADIN1

F23

H_CADIP0

E24

H_CADIN0

E25

H_CLKIP1

L21

H_CLKIN1

L22

H_CLKIP0

J24

H_CLKIN0

J25

H_CTLIP0

N23

H_CTLIN0

P23

R260 100_0402_1%

C25

1 2

D24

H_CLKIP1 4
H_CLKIN1 4

H_CLKIP0 4
H_CLKIN0 4

H_CTLIP0 4

H_CTLIN0 4

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2008/1/3 2009/01/3

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

RS690MC HT / PCIE / DVI
LA-4191P

1

10 39Monday, January 14, 2008

0.3

of

Reserve for EMI, close to U690

NB_REFCLK

12

R63

@

33_0402_5%

2

C161

@

22P_0402_50V8J

1

HTREFCLK

12

R281

@

33_0402_5%

2

C474

@

22P_0402_50V8J

1

+3VS

+1.8VS

FBML10160808121LMT_0603

+1.8VS

FBML10160808121LMT_0603

R304

R273

1 2

1 2

4.7K_0402_5%

EDID_CLK_LCD

EDID_DAT_LCD

+3VS

12

R275
1K_0402_5%

NB_STRAP_DATA

12

R276
2K_0402_5%

@

1 2

R57 150_0402_1%

1 2

R56 150_0402_1%

1 2

R55 150_0402_1%

+1.8VS

L36

1 2

L12

1 2

+1.2V_HT

15mil

4.7K_0402_5%

VGA_CRT_R
VGA_CRT_G
VGA_CRT_B

L39

1 2

FBML10160808121LMT_0603

VGA_DDC_CLK14

1

C169

2.2U_0603_10V6K

2

15mil

1

C173
1U_0603_10V6K

2

L37

1 2

FBML10160808121LMT_0603

EDID_CLK_LCD14
EDID_DAT_LCD14

15mil

2006-12-30 Bowfin 2.1

VGA_DDC_CLK

15mil

1

C685

2.2U_0603_10V6K

2

EDID_CLK_LCD
EDID_DAT_LCD

+3VS

1 2

FBML10160808121LMT_0603

+1.8VS

15mil

1

C473

2.2U_0603_10V6K

2

VGA_CRT_R14
VGA_CRT_G14

VGA_CRT_B14
VGA_CRT_VSYNC14
VGA_CRT_HSYNC14

R277 0_0402_5%

1 2

VGA_DDC_DATA14

ALLOW_LDTSTOP15

NB_REFCLK13

NB_GFX_CLKP13

NB_GFX_CLKN13

R62 10K_0402_5%@
R54 10K_0402_5%@
R279 10K_0402_5%@
R305 10K_0402_5%@
R278 10K_0402_5%@
R306 10K_0402_5%@

R274 0_0402_5%

1 2

R303 4.7K_0402_5%@

+3VS

R302 4.7K_0402_5%

L5

+AVDD

1

C472

2.2U_0603_10V6K

2

VGA_CRT_VSYNC
VGA_CRT_HSYNC

R280 715_0402_1%

1 2

VGA_DDC_CLK_NB
VGA_DDC_DATA

NB_RST#15,19,21,24,25,26

NB_PWRGD25

HTREFCLK13

SBLINKCLK13

SBLINKCLK#13

12
12
12
12
12
12

1 2

ALLOW_LDTSTOP

12

12

SBLINKCLK#

EDID_CLK_LCD_NB

12

NB_STRAP_DATA

1

2

+AVDDQ

VGA_CRT_R
VGA_CRT_G
VGA_CRT_B

+NB_PLLVDD

+NB_HTPVDD

NB_RST#
NB_PWRGD
NB_LDTSTOP#

HTREFCLK

NB_REFCLK

NB_GFX_CLKP
NB_GFX_CLKN

SBLINKCLK

DFT_GPIO0
DFT_GPIO1
DFT_GPIO2
DFT_GPIO3
DFT_GPIO4
DFT_GPIO5

15mil

C152

2.2U_0603_10V6K
U690C

B22
C22
G17
H17
A20
B20

A21
A22

C21
C20
D19

E19

F19

G19

C6

A5

B21

B6
A6

A10
B10

B24
B25

C10
C11

C5

B5

R26210K_0402_5%

C23
B23

R25910K_0402_5%

C2

B11
A11

F2
E1

G1
G2

D6
D7
C8
C7

B8
A8

B2
A2

B4
AA15
AB15

C14

B3

C3

A3

216MQA6AVA11FG FCBGA 465P

PART 3 OF 5

AVDD1
AVDD2
AVSSN1
AVSSN2
AVDDDI
AVSSDI

AVDDQ
AVSSQ

C
Y
COMP

RED
GREEN
BLUE
DACVSYNC
DACHSYNC

RSET
DACSCL

DACSDA
PLLVDD(PLLVDD18)

PLLVSS
HTPVDD

HTPVSS
SYSRESET#

POWERGOOD
LDTSTOP#
ALLOW_LDTSTOP

HTTSTCLK
HTREFCLK

TVCLKIN
OSCIN

OSCOUT(PLLVDD12)
GFX_CLKP

GFX_CLKN
SB_CLKP

SB_CLKN
DFT_GPIO0

DFT_GPIO1
DFT_GPIO2
DFT_GPIO3
DFT_GPIO4
DFT_GPIO5

BMREQ#
I2C_CLK
I2C_DATA
THERMALDIODE_P
THERMALDIODE_N

TMDS_HPD
DDC_DATA
TESTMODE
STRP_DATA

CRT/TVOUT

LVTM

LVDDR18A_1(LVDDR33_1)
LVDDR18A_2(LVDDR33_2)

PLL PWR

PMCLOCKs

DVO_D0(GPP_TX0P)
DVO_D1(GPP_TX0N)

DVO_D2(DEBUG6)

DVO_D3(GPP_RX0P)

DVO_D4(GPP_RX0N)

DVO_D5(DEBUG9)

DVO_D6(DEBUG10)
DVO_D7(GPP_TX1N)
DVO_D8(GPP_TX1P)
DVO_D9(GPP_RX1N)

DVO_D10(GPP_RX1P)

DVO

MIS.

DVO_D11(DEBUG15)

DVO_VSYNC(DEBUG0)

DVO_DE(DEBUG2)
DVO_HSYNC(DEBUG1)
DVO_IDCKP(DEBUG14)
DVO_IDCKN(DEBUG13)

LDT_STOP#6,15

TXOUT_L0P
TXOUT_L0N
TXOUT_L1P
TXOUT_L1N
TXOUT_L2P
TXOUT_L2N
TXOUT_L3P
TXOUT_L3N

TXOUT_U0P

TXOUT_U0N

TXOUT_U1P

TXOUT_U1N

TXOUT_U2P

TXOUT_U2N

TXOUT_U3P

TXOUT_U3N

TXCLK_LP
TXCLK_LN
TXCLK_UP
TXCLK_UN

LPVDD
LPVSS

LVDDR18D_1
LVDDR18D_2

LVSSR1
LVSSR3
LVSSR5
LVSSR6
LVSSR7
LVSSR8

LVSSR12
LVSSR13

LVDS_DIGON

LVDS_BLON
LVDS_BLEN

LVDSL0+

B14

LVDSL0-

B15

LVDSL1+

B13

LVDSL1-

A13

LVDSL2+

H14

LVDSL2-

G14
D17
E17

LVDSU0+

A15

LVDSU0-

B16

LVDSU1+

C17

LVDSU1-

C18

LVDSU2+

B17

LVDSU2-

A17
A18
B18

LVDSLC+

E15

LVDSLC-

D15

LVDSUC+

H15

LVDSUC-

G15
D14

E14
A12

B12
C12
C13

A16
A14
D12
C19
C15
C16

F14
F15

ENVDD_NB

E12

ENABLT_NB

G12
F12

PCIE_CARD_TX_P1

AD14

PCIE_CARD_TX_N1

AD15
AE15

PCIE_CARD_C_RX_P1

AD16

PCIE_CARD_C_RX_N1

AE16
AC17
AD18
AE19
AD19
AE20
AD20
AE21

AD13

SUS_STAT#

AC13
AE13
AE17
AD17

R239

470K_0402_5%

+1.8VS

Q44

3 1

MMBT3904_NL_SOT23

+LVDDR18D

+LVDDR33A

@

1 2

R84

1 2

10K_0402_5%

2

LVDSL0+ 14
LVDSL0- 14
LVDSL1+ 14
LVDSL1- 14
LVDSL2+ 14
LVDSL2- 14

LVDSU0+ 14
LVDSU0- 14
LVDSU1+ 14
LVDSU1- 14
LVDSU2+ 14
LVDSU2- 14

LVDSLC+ 14
LVDSLC- 14
LVDSUC+ 14
LVDSUC- 14

+LPVDD

0.1U_0402_16V7K~N

GND_LVSSR

R69 0_0402_5%

12

R68 0_0402_5%

12

C419 0.1U_0402_16V7K~N

1 2

C420 0.1U_0402_16V7K~N

1 2

+3VS

12

R70
10K_0402_5%

NB_LDTSTOP#

C163

+3VS

1

2

C171

4.7U_0805_6.3V6K~N

PCIE_CARD_C_TX_P1
PCIE_CARD_C_TX_N1

NB_PWRGD

L11

1

C170

2.2U_0603_10V6K

2

2

G

Q17

FBML10160808121LMT_0603

1

2

SSM3K7002FU_SC70-3

12

1

C172

2

0.1U_0402_16V7K~N

4.7U_0805_6.3V6K~N

L9

1 2

FBML10160808121LMT_0603

L10

1 2

FBML10160808121LMT_0603

ENVDD

ENVDD 14

ENABLT

ENABLT 14,25

PCIE_CARD_C_RX_P1 26
PCIE_CARD_C_RX_N1 26

+5VS

ENVDD_NB

R81

@

10K_0402_5%

1 2

NB_PWRGD5V#

13

D

ENABLT_NB

@

S

AP2301GN 1P SOT23

+1.8VS

+LVDDR33A

R71
0_0805_5%

1

C162

2

GND_LVSSR

15mil

+1.8VS

15mil

PCIE_CARD_C_TX_P1 26
PCIE_CARD_C_TX_N1 26

Q19
AP2301GN 1P SOT23

S

D

ENVDD

13

@

G

2

R83

@

G

2

ENABLT

13

D

S

@

Q18

R82

12

12

1K_0402_5%

12

1K_0402_5%

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2008/1/3 2009/01/3

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

Date: Sheet

RS690MC VIDEO_IF/CLOCK GEN
LA-4191P

of

11 39Monday, January 14, 2008

0.3

5

+1.2V_HT

D D

0.3A

+3VS

C C

B B

L3

1 2

FBMA-L11-322513-201LMA40T_1210

C422

0.2A

+1.8VS

1

C151

+1.8VS

2

2.2U_0603_10V6K

C121

L4

+1.2V_HT

1 2

FBML10160808121LMT_0603

+1.2V_HT

FBMA-L11-322513-201LMA40T_1210

NB_VDDHT12

1

C122

2

22U_0805_6.3V6M

C175

15mil

1

C130

2

1U_0402_6.3V6K

C149

L7

1 2

0.8A

2

C124

1

1U_0402_6.3V6K

1

C164

2

1U_0402_6.3V6K

1

C129

2

1U_0402_6.3V6K

NB_VDDA12

1

C148

2

4.7U_0805_6.3V6K~N

1

2

1

2

40mil

2

1

1U_0402_6.3V6K

1

2

1U_0402_6.3V6K

C425

C123

1U_0402_6.3V6K

1U_0402_6.3V6K

15mil

1

2

2

1

C157

22U_0805_6.3V6M

2

C131

1

1U_0402_6.3V6K

+VDDHT_PKG
+VDDA12_PKG1
+VDDA12_PKG2

NB_VDDA12_HT

1

C146

2

1U_0402_6.3V6K

2

C421

1

1U_0402_6.3V6K

NB_VDDA12_HT

NB_VDDA12

1

C127

2

1U_0402_6.3V6K

1U_0402_6.3V6K

1

2

C145

1U_0402_6.3V6K

4

AA17
AB17
AB19
AC18
AC19
AC20
AD21
AD22
AD23
AD24
AE23
AE24
AE25

W17

Y17

J14
J15

AB3
AB4
AC3
AD2
AE1
AE2

U7

D11
E11

AC12
AD12
AE12

E7
F7
F9

G9

D22

M1

AC11

+VDDA12_PKG1

1

C116

2

1U_0402_6.3V6K

U690D

PART 4 OF 5

VDD_HT1
VDD_HT2
VDD_HT3
VDD_HT4
VDD_HT5
VDD_HT6
VDD_HT7
VDD_HT8
VDD_HT9
VDD_HT10
VDD_HT11
VDD_HT12
VDD_HT13
VDD_HT14
VDD_HT15

VDD18_1
VDD18_2

VDDA18_1(VDDA12_13)
VDDA18_2(VDDA12_14)
VDDA18_3(VDDA12_15)
VDDA18_4(VDDA12_16)
VDDA18_5(VDDA12_17)
VDDA18_6(VDDA12_18)
VDDA18_7(VDDA12_19)
VDDA18_8(VDDA12_20)W7VDDC_14

VDDR3_1
VDDR3_2

VDD_DVO1(VDDR_1)
VDD_DVO2(VDDR_2)
VDD_DVO3(VDDR_3)

VDDA12(VDDPLL_1)
VDDA12(VDDPLL_2)
VSSA12(VSSPLL_1)
VSSA12(VSSPLL_2)

VDDHT_PKG
VDDA12_PKG1
VDDA12_PKG2

216MQA6AVA11FG FCBGA 465P

1

C456

0.1U_0402_16V7K~N

2

1

2

1U_0402_6.3V6K

VDDA12_1
VDDA12_2
VDDA12_3
VDDA12_4
VDDA12_5
VDDA12_6
VDDA12_7
VDDA12_8

VDDA12_9
VDDA12_10
VDDA12_11
VDDA12_12

VDDC_1
VDDC_2
VDDC_3
VDDC_4
VDDC_5
VDDC_6
VDDC_7
VDDC_8

POWER

VDDC_9
VDDC_10
VDDC_11
VDDC_12
VDDC_13

VDDC_15
VDDC_16
VDDC_17
VDDC_18
VDDC_19
VDDC_20
VDDC_21
VDDC_22
VDDC_23
VDDC_24
VDDC_25
VDDC_26
VDDC_27
VDDC_28
VDDC_29
VDDC_30
VDDC_31
VDDC_32

3

B1
C1
D1
D2
D3
E2
E3
F4
E6
G7
L9
M9

A4
A7
A9
A19
B9
B19
C9
D9
D20
G20
H11
J11
J19
L11
L13
L15
L17
M12
M14
N11
N13
N15
P12
P14
P17
R11
R13
R15
U11
U12
U14
U15

NB_VDDA12_HT

2

C147

1

300mil

1

1

C1530.1U_0402_16V7K~N

C1350.1U_0402_16V7K~N

2

2

120mil

2

C128

C139

1

1U_0402_6.3V6K

1U_0402_6.3V6K

5A

1

1

1

C1580.1U_0402_16V7K~N

C1600.1U_0402_16V7K~N

C1340.1U_0402_16V7K~N

2

2

2

2.5A

A25

AE18

W23

AD25

W24

AC23

AC14
AC22

AE22

AE14

M17

AC15

M13

AC16

F11

D23

E9
G11
Y23
P11
R24

M15

J22

G23

J12
L12
L14
L20

L23
M11
M20
M23
M25
N12
N14

L24
P13
P20
P15
R12
R14
R20

Y25
U20

H25
Y22
D25

G24

R23

C4

T23
T25

R17
H23

A23

F17

D4

H12

B7

2

1

1

C1590.1U_0402_16V7K~N

2

C467

1U_0402_6.3V6K

+1.2V_NBCORE

1

C13322U_0805_6.3V6M

C14122U_0805_6.3V6M

2

1

2

22U_0805_6.3V6M

1

2

2

C115

1

1U_0402_6.3V6K

1

1

1

C1650.1U_0402_16V7K~N

C1400.1U_0402_16V7K~N

C1360.1U_0402_16V7K~N

2

2

2

2

U690E

VSS1

PAR 5 OF 5

VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23

VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42

VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57

VSS59
VSS60
VSS61
VSS62

216MQA6AVA11FG FCBGA 465P

GROUND

VSSA2
VSSA3
VSSA4
VSSA5
VSSA6
VSSA7
VSSA8

VSSA9
VSSA10
VSSA11

VSSA13
VSSA15

VSSA16
VSSA17
VSSA18
VSSA19
VSSA20
VSSA21
VSSA22

VSSA24
VSSA25
VSSA26
VSSA27
VSSA28

VSSA30
VSSA32

VSSA33
VSSA34
VSSA35
VSSA36
VSSA93
VSSA94
VSSA95
VSSA37
VSSA38
VSSA39
VSSA40
VSSA41
VSSA42
VSSA43
VSSA44
VSSA45
VSSA46
VSSA47
VSSA48
VSSA49
VSSA50
VSSA51

V12
V11
V14
F3
V15
A1
H1
G3
J2
H3

J6
F1

L6
M2
M6
J3
P6
T1
N3

R6
U2
T3
U3
U6

Y1
W6

AC2
Y3
Y9
Y11
Y12
Y14
AA3
R9
AD1
AC5
AC6
AC7
AD3
AC9
AC10
G6
Y15
AC4
P9
AE6
AE10
M3

1

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2008/1/3 2009/01/3

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

RS690MC Power/GND
LA-4191P

1

12 39Monday, January 14, 2008

0.3

of

A

B

C

D

E

F

G

H

12

L15

C22010U_0805_6.3V6M

1 2

C219 0.1U_0402_16V7K~N

+3VS_CLK

1 2

C49310U_0805_6.3V6M

1 2

C4920.1U_0402_16V7K~N

1 2

R319 10K_0402_5%

CPUFS1

Hi-Z
X

180.00

220.00

100.00

133.33

200.00

1 1

2 2

EXT CLK FREQUENCY SELECT TABLE(MHZ)

3 3

FS2

0 0 0
0 0 1

0 1 0
0 1 1
1 0 0
1 0 1

1 1 1

FBML10160808121LMT_0603

+3VS_CLK_VDD48

+3VS

12

L16

FBML10160808121LMT_0603

+3VS_CLK_VDDREF +3VS_CLK_VDD48

CLK_RESET

1 2

SRCCLK

HTTFS0 PCI

[2:1]

Hi-Z Hi-Z100.00 Reserved

100.00

100.00

100.00

36.56 73.12

100.00

66.66 33.33

100.00

66.66 33.33

100.00

66.66 33.33 Normal ATHLON64 operation

USB

48.00

X/6X/3

48.00

30.0060.00

48.00

48.00

48.00

48.00

48.00

+3VS

SMB_CK_CLK18,9,16,26
SMB_CK_DAT18,9,16,26

COMMENT

Reserved
Reserved
Reserved
Reserved
Reserved

L14
0_0805_5%

1

C176
10U_0805_6.3V6M

2

22P_0402_50V8J

22P_0402_50V8J

1 2

C487

14.31818MHz_20P_1BX14318BE1A

1 2

12

Y3

C481

1 2

SMB_CK_CLK1 SMB_CCK_CLK1
SMB_CK_DAT1

0.1U_0402_16V7K~N

1

C190

22U_0805_6.3V6M

R321 33_0402_5%

1 2
1 2

R320 33_0402_5%

1 2

R85 475_0603_1%

FS0
FS1
FS2

1

C193

2

2

+3VS_CLK_VDDREF

XTALIN_CLK
XTALOUT_CLK

CLK_RESET

SMB_CCK_DAT1

0.1U_0402_16V7K~N

1

C192

2

0.1U_0402_16V7K~N

CLKIREF

+3V_CLK (40 mils)

+3VS_CLK

1

C188

54
14
23
28
44

39
60
53

15
22
29
45

38
58

11
61

10

48

5
2

8
1

3
4

9

@

1

C186

2

2

0.1U_0402_16V7K~N

U25

VDDCPU
VDDSRC
VDDSRC
VDDSRC
VDDSRC
VDD48
VDDATIG
VDDREF
VDDHTT

GNDCPU
GNDSRC
GNDSRC
GNDSRC
GNDSRC
GND48
GNDATIG
GNDREF
GNDHTT

X1
X2

RESET_IN#
NC

SMBCLK
SMBDAT

IREF

ICS951462AGLFT_TSSOP64

12

12

R77

R299

2.2K_0402_5%

2.2K_0402_5%

12

12

R76

R298

@

2.2K_0402_5%

2.2K_0402_5%

0.1U_0402_16V7K~N

C189

+3VS_CLK +3VS_CLK

R295

R75

@

1

C191

2

0.1U_0402_16V7K~N

VDDA
GNDA

CPUCLK8T0
CPUCLK8C0

CPUCLK8T1

CPUCLK8C1

SRCCLKT6

SRCCLKC6
ATIGCLKT0
ATIGCLKC0
ATIGCLKT1
ATIGCLKC1
ATIGCLKT2
ATIGCLKC2
ATIGCLKT3
ATIGCLKC3

SRCCLKT5

SRCCLKC5

SRCCLKT4

SRCCLKC4

SRCCLKT3

SRCCLKC3

SRCCLKT2

SRCCLKC2

SRCCLKT0

SRCCLKC0

SRCCLKT1

SRCCLKC1

SRCCLKT7

SRCCLKC7

CLKREQA#

CLKREQB#

CLKREQC#

48MHz_1
48MHz_0

FS1/REF1
FS0/REF0
FS2/REF2

HTTCLK0

12

2.2K_0402_5%

12

2.2K_0402_5%

0.1U_0402_16V7K~N

1

1

C187

2

2

50
49

CPUCLK0H

56

CPUCLK0L

55
52
51

CLK_WCARD

16

CLK_WCARD#

17

CLK_GFX_CLKP

41

CLK_GFX_CLKN

40
37
36
35
34
30
31
18
19
20
21
24
25

CLK_CARD

26

CLK_CARD#

27

CLK_LAN

47

CLK_LAN#

46
43

SBLINKCLK#_R

42

SBSRCCLK_R

12

SBSRCCLK#_R

13

CLKREQA#

57

CLKREQB#

32

CLKREQC#

33
7

CLK_USB

6

FS1

63

FS0

64

FS2

62

CLK_HTREFCLK

59

CLKREQA#
CLKREQB#
CLKREQC#

R292 47.5_0402_1%

1 2

R291 47.5_0402_1%

1 2

R322 33_0402_5%

1 2

R296 33_0402_5%
R297 33_0402_5%

R294 33_0402_5%

1 2

12

12

R311

R293

12

R73

@

10K_0402_5%

R312

@

2.2K_0402_5%

10K_0402_5%

12

2.2K_0402_5%

R283

R284

@

1 2

+3VS_CLK_VDDA

1

2

C178

0.1U_0402_16V7K~N

R316 33_0402_5%

1 2

R315 33_0402_5%

1 2

R286 33_0402_5%

1 2

R285 33_0402_5%

1 2

R314 33_0402_5%

1 2

R313 33_0402_5%

1 2

R290 33_0402_5%

1 2

R289 33_0402_5%

1 2

R288 33_0402_5%

1 2

R287 33_0402_5%

1 2

R318 33_0402_5%

1 2

R317 33_0402_5%

1 2

12

12

10K_0402_5%

12

2.2K_0402_5%

L13

1 2

FBML10160808121LMT_0603

1

C177
22U_0805_6.3V6M

2

CLK_PCIE_WCARD
CLK_PCIE_WCARD#

NB_GFX_CLKP
NB_GFX_CLKN

CLK_PCIE_CARD
CLK_PCIE_CARD#
CLK_PCIE_LAN
CLK_PCIE_LAN#

SBLINKCLKSBLINKCLK_R

SBLINKCLK#
SBSRCCLK
SBSRCCLK#

USBCLK_EXT

R74

49.9_0402_1%

HTREFCLK 11

12

+3VS+3VS

12

R269
261_0402_1%

CLKREQA# 24
CLKREQB# 26
CLKREQC#

USBCLK_EXT 16

NB_REFCLK 11

SB_OSC_INT 16

USBCLK_EXT
NB_REFCLK
SB_OSC_INT

CLK_PCIE_WCARD
CLK_PCIE_WCARD#

CLK_PCIE_CARD
CLK_PCIE_CARD#

CLK_PCIE_LAN
CLK_PCIE_LAN#

SBSRCCLK
SBSRCCLK#

SBLINKCLK
SBLINKCLK#

NB_GFX_CLKP
NB_GFX_CLKN

CPUCLK0_H 6

CPUCLK0_L 6

CLK_PCIE_WCARD 24
CLK_PCIE_WCARD# 24
NB_GFX_CLKP 11
NB_GFX_CLKN 11

CLK_PCIE_CARD 26
CLK_PCIE_CARD# 26
CLK_PCIE_LAN 21
CLK_PCIE_LAN# 21
SBLINKCLK 11
SBLINKCLK# 11
SBSRCCLK 15
SBSRCCLK# 15

C498 10P_0402_25V8K@

1 2

C469 10P_0402_25V8K@

1 2

C470 10P_0402_25V8K@

1 2

R328 49.9_0402_1%

1 2

R327 49.9_0402_1%

1 2

R326 49.9_0402_1%

1 2

R325 49.9_0402_1%

1 2

R268 49.9_0402_1%

1 2

R267 49.9_0402_1%

1 2

R330 49.9_0402_1%

1 2

R329 49.9_0402_1%

1 2

R266 49.9_0402_1%

1 2

R265 49.9_0402_1%

1 2

R264 49.9_0402_1%

1 2

R263 49.9_0402_1%

1 2

USBCLK_EXT

@

@

12

R117
33_0402_5%

2

C255
22P_0402_50V8J

1

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

C

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

D

2008/1/3 2009/01/3

E

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

F

Date: Sheet

G

Clock Generator
LA-4191P

0.3

of

13 39Monday, January 14, 2008

H

A

1 1

VGA_CRT_R11

VGA_CRT_G11

+3VS

D11
RB751V_SOD323

21

D12
RB751V_SOD323@

21

VGA_CRT_HSYNC11

VGA_CRT_VSYNC11

BKOFF#25

ENABLT11,25

2 2

BKOFF#

VGA_CRT_B11

12

R201
1K_0402_5%

DISPOFF#

1 2

R196 39_0402_5%

VGA_CRT_VSYNC CRT_VSYNC D_CRT_VSYNC

1 2

R199 39_0402_5%

B

VGA_CRT_R

VGA_CRT_G CRT_G_L

VGA_CRT_B

1

12

R193

150_0402_1%

1 2

C4 0.1U_0402_16V7K~N

CRT_HSYNC D_CRT_HSYNCVGA_CRT_HSYNC

+CRT_VCC

1 2

C5 0.1U_0402_16V7K~N

12

12

R195

R197

150_0402_1%

150_0402_1%

+CRT_VCC

1

5

P

OE#

A2Y

G

U13

74AHCT1G125GW_SOT353-5

3

1

5

P

OE#

A2Y

G

U14
74AHCT1G125GW_SOT353-5

3

C353

4

4

1

C352

2

2

8P_0402_50V8K

8P_0402_50V8K

R200 10K_0402_5%

FCM2012C-800_0805

FCM2012C-800_0805

FCM2012C-800_0805

1

C351

2

8P_0402_50V8K

C

+3VS

L28

1 2

L29

1 2

L30

1 2

12

D24

DA204U_SOT323-3~D

CRT_R_L

CRT_B_L

1

C344

2

8P_0402_50V8K

D25

DA204U_SOT323-3~D

1

@

3

1

C345

2

8P_0402_50V8K

1 2

1 2

2

2

R191 0_0603_5%

R192 0_0603_5%

1

@

3

1

C347

2

8P_0402_50V8K

C346

10P_0402_50V8J

1

@

2

3

D26
DA204U_SOT323-3~D

MSEN#25

HSYNC_L

VSYNC_L

1

2

+5VS

+3VS+CRT_VCC +3VS+CRT_VCC +3VS

D

F2

1.1A_6VDC_FUSE

1

C348

2

100P_0402_50V8K

10P_0402_50V8J

W=40mils

21

2 1

RB411DT146 SOT23

C1

100P_0402_50V8K

E

+CRT_VCC

D1

C3

C7

1

C2

2

68P_0402_50V8K

W=40mils

1

2

0.1U_0402_16V7K~N

VGA_DDC_DATA_C

VGA_DDC_CLK_C

1

C6
68P_0402_50V8K

2

JCRT1

6

11

1
7

12

2
8

13

3
9

14

4
10
15

5

SUYIN_070549FR015S208CR

CONN@

17
16

R2

6.8K_0402_5%

BSS138_NL_SOT23

41

JLCD1

1
3

GND
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39

GND

42

R6

1 2

1 3

2

2

4

4

6

6

8

8

10

10

12

12

14

14

16

16

18

18

20

20

22

22

24

24

26

26

28

28

30

30

32

32

34

34

36

36

38

38

40

40

R5

0_0402_5%

1 2

4.7K_0402_5% 1 2

2

G

D

S

2

G

Q3

1 3

D

S

Q4

BSS138_NL_SOT23

LVDSLC+
LVDSLC-

LVDSL0+
LVDSL0-

LVDSL1+
LVDSL1-

LVDSL2+
LVDSL2-

DISPOFF#
DAC_BRIG

INVT_PWM

INVPWR_B+
INVPWR_B+

LVDSLC+ 11
LVDSLC- 11

LVDSL0+ 11
LVDSL0- 11

LVDSL1+ 11
LVDSL1- 11

LVDSL2+ 11
LVDSL2- 11

Compal Secret Data

Deciphered Date

R198

4.7K_0402_5%

1 2

DAC_BRIG 25
INVT_PWM 25

D

VGA_DDC_DATA 11

VGA_DDC_CLK 11

0.1U_0402_16V7K~N @

Close to JLCD1. Reserved for EMI

DISPOFF#
DAC_BRIG

1

C687

Custom

Date: Sheet

1

C688

2

Title

Size Document Number Rev

0.1U_0402_16V7K~N@

2

CRT Conn.& LCD Conn.
LA-4191P

E

14 39Monday, January 14, 2008

0.3

of

R695

EDID_CLK_LCD

LVDSUC+
LVDSUC-

LVDSU0+
LVDSU0-

LVDSU1+
LVDSU1-

LVDSU2+
LVDSU2-

C

R1

1 2

6.8K_0402_5%

+3VS

12

1
3
5
7

9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39

CONN@

JST_BM40B-SRDS-G-TFCLFSN~N

2008/1/3 2009/01/3

LCD POWER CIRCUIT

+3VS

1

ENVDD_PW

C372

0.1U_0402_16V7K~N

D35

2 1

RB751V_SOD323

D40

2 1

RB751V_SOD323

A

2

3 3

ENVDD11

LCD_VCC_TEST_EN25

4 4

12

R14
10K_0402_5%

U37

IN6OUT
EN3NC

5

GND

AOZ1320CI-04_SOT23-6

GND

1
4
2

1N4148_SOT23@

B+

W=60milsW=60mils

12

D13

R524
MCK2012221YZF_0805

0.1U_0603_50V4Z

1

C363

4.7U_0805_6.3V6K~N

2

12

2

1

+LCDVDD

+LCDVDD

INVT_PWM EDID_DAT_LCD

1

C360

1U_0603_10V6K

2

0.1U_0603_50V4Z

2

C359

C361

1

B

R618
0_0805_5%

1

C369

0.1U_0402_16V7K~N

2

INVPWR_B+

+LCDVDD_R

12

reserve for EMI

+3VS

1

C370

0.1U_0402_16V7K~N

2

80mil

VGA_DDC_DATA_C

VGA_DDC_CLK_C

47K_0402_5%

LCD_DET25 BIST 25

W=60mils

+LCDVDD_R

+3VS

EDID_CLK_LCD11

EDID_DAT_LCD11

LVDSUC+11

LVDSUC-11
LVDSU0+11

LVDSU0-11

LVDSU1+11

LVDSU1-11

LVDSU2+11

LVDSU2-11

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

2

1

U2
T2
U1
V2
W3
U3
V1
T1

AJ9

W7
Y1
W8
W5
AA5
Y3
AA6
AC5
AA7
AC3
AC7
AJ7
AD4
AB11
AE6
AC9
AA3
AJ4
AB1
AH4
AB2
AJ3
AB3
AH3
AC1

AD24

AH2

AD25

AC2

AD26

AH1

AD27

AD2

AD28

AG2

AD29

AD1

AD30

AG1

AD31

AB9
AF9
AJ5
AG3

CBE3#

AA2
AH6
AG5

IRDY#

AA1
AF7
Y2

STOP#

AG8

PERR#

AC11

SERR#

AJ8

REQ0#

AE2

REQ1#

AG9

REQ2#

AH8
AH5
AD11

GNT0#

AF2

GNT1#

AH7

GNT2#

AB12
AG4
AG7
AF6

LOCK#

AD3
AF1
AF4
AF3

AG24

LAD0

AG25

LAD1

AH24

LAD2

AH25

LAD3

AF24
AJ24
AH26
W22
AF23

D3
F5

E1

VBAT

D1

0.1U_0402_16V7K~N

PCI_AD[0..31]

PCICLK0_R
PCICLK1_R

PCICLK4_R
PCICLK5_R
PCICLK6_R

PCI_AD0
PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD6
PCI_AD7
PCI_AD8
PCI_AD9
PCI_AD10
PCI_AD11
PCI_AD12
PCI_AD13
PCI_AD14
PCI_AD15
PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20
PCI_AD21
PCI_AD22
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30
PCI_AD31
PCI_CBE#0
PCI_CBE#1
PCI_CBE#2
PCI_CBE#3
PCI_FRAME#
PCI_DEVSEL#
PCI_IRDY#
PCI_TRDY#
PCI_PAR
PCI_STOP#
PCI_PERR#
PCI_SERR#
PCI_REQ#0

PCI_GNT#0

PM_CLKRUN#
LOCK#

PCI_PIRQE#
PCI_PIRQF#
PCI_PIRQG#
PCI_PIRQH#

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
LPC_FRAME#
LDRQ0#
LDRQ1#

SIRQ
RTC_CLK

RTC_IRQ#

R136

A_RST#

D D

C C

B B

33_0402_5%

1 2

15mil

40mil

NB_RST# 11,19,21,24,25,26

2

C269
10P_0402_25V8K

1

@

0.1A

0.5A

SB_RX0P10

SB_RX0N10

SB_RX1P10

SB_RX1N10

SB_RX2P10

SB_RX2N10

SB_RX3P10

SB_RX3N10

SB_TX0P10
SB_TX0N10
SB_TX1P10
SB_TX1N10
SB_TX2P10
SB_TX2N10
SB_TX3P10
SB_TX3N10

+1.2V_HT

+1.2V_HT

FBM-L11-321611-260-LMT_1206

+1.8VS

BLM21A601SPT_0805

L18

1 2

C560

1 2

15P_0402_50V8J

C561

1 2

15P_0402_50V8J

R102

10K_0402_5%

SB_RX0P
SB_RX0N
SB_RX1P
SB_RX1N
SB_RX2P
SB_RX2N
SB_RX3P
SB_RX3N

L17

1 2

+PCIE_VDDR

1

C22722U_0805_6.3V6M

2

R425

12

20M_0402_5%~D

12

R426
20M_0402_5%~D

CPU_PWRGD6

ALLOW_LDTSTOP11

12

C500 0.1U_0402_16V7K~N
C499 0.1U_0402_16V7K~N
C502 0.1U_0402_16V7K~N
C501 0.1U_0402_16V7K~N
C504 0.1U_0402_16V7K~N
C503 0.1U_0402_16V7K~N
C505 0.1U_0402_16V7K~N
C506 0.1U_0402_16V7K~N

+PCIE_VDDR

+PCIE_PVDD

2

C2251U_0603_10V6K

1

2

2

C2321U_0603_10V6K

C2231U_0603_10V6K

C2331U_0603_10V6K

1

1

Y5

4

OUT

1

IN

32.768K_1TJS125BJ4A421P

LDT_STOP#6,11

LDT_RST#6

SBSRCCLK13

SBSRCCLK#13

1

C22222U_0805_6.3V6M

2

2

C5070.1U_0402_16V7K~N

1

NC
NC

ALLOW_LDTSTOP

2

C2260.1U_0402_16V7K~N

1

3
2

LDT_RST#

8.2K_0402_5%

R125

1 2

R332
R331

R333 0_0402_5%

2

1

SBSRCCLK
SBSRCCLK#

SB_RX0P_C
SB_RX0N_C
SB_RX1P_C
SB_RX1N_C
SB_RX2P_C
SB_RX2N_C
SB_RX3P_C
SB_RX3N_C

SB_TX0P
SB_TX0N
SB_TX1P
SB_TX1N
SB_TX2P
SB_TX2N
SB_TX3P
SB_TX3N

562_0402_1%

12
12

2.05K_0402_1%

12

SB_32KHI

SB_32KH0

U600A

AG10

A_RST#

J24

PCIE_RCLKP

J25

PCIE_RCLKN

P29

PCIE_TX0P

P28

PCIE_TX0N

M29

PCIE_TX1P

M28

PCIE_TX1N

K29

PCIE_TX2P

K28

PCIE_TX2N

H29

PCIE_TX3P

H28

PCIE_TX3N

T25

PCIE_RX0P

T26

PCIE_RX0N

T22

PCIE_RX1P

T23

PCIE_RX1N

M25

PCIE_RX2P

M26

PCIE_RX2N

M22

PCIE_RX3P

M23

PCIE_RX3N

E29

PCIE_CALRP

E28

PCIE_CALRN

E27

PCIE_CALI

U29

PCIE_PVDD

U28

PCIE_PVSS

F27

PCIE_VDDR_1

F28

PCIE_VDDR_2

F29

PCIE_VDDR_3

G26

PCIE_VDDR_4

G27

PCIE_VDDR_5

G28

PCIE_VDDR_6

G29

PCIE_VDDR_7

J27

PCIE_VDDR_8

J29

PCIE_VDDR_9

L25

PCIE_VDDR_10

L26

PCIE_VDDR_11

L29

PCIE_VDDR_12

N29

PCIE_VDDR_13

D2

X1

C1

X2

AC26

CPU_PG/LDT_PG

W26

INTR/LINT0

W24

NMI/LINT1

W25

INIT#

AA24

SMI#

AA23

SLP#/LDT_STP#

AA22

IGNNE#/SIC

AA26

A20M#/SID

Y27

FERR#

AA25

STPCLK#/ALLOW_LDTSTP

AH9

CPU_STP#/DPSLP_3V#

B24

DPSLP_OD#/GPIO37

W23

DPRSLPVR

AC25

LDT_RST#/DPRSTP#/PROCHOT#

218S6ECLA13FG FCBGA 548P

SB600 SB 23x23mm

Part 1 of 4

PCI CLKS

SPDIF_OUT/PCICLK7/GPIO41

PCI EXPRESS INTERFACE

CBE0#/ROMA10

CBE2#/ROMWE#

DEVSEL#/ROMA0

PCI INTERFACE

TRDY#/ROMOE#

XTAL

LDRQ1#/GNT5#/GPIO68

LPC

BMREQ#/REQ5#/GPIO65

CPU

RTC_IRQ#/GPIO69

RTC

PCICLK0
PCICLK1
PCICLK2
PCICLK3
PCICLK4
PCICLK5
PCICLK6

PCIRST#

AD0/ROMA18
AD1/ROMA17
AD2/ROMA16
AD3/ROMA15
AD4/ROMA14
AD5/ROMA13
AD6/ROMA12
AD7/ROMA11

AD8/ROMA9

AD9/ROMA8
AD10/ROMA7
AD11/ROMA6
AD12/ROMA5
AD13/ROMA4
AD14/ROMA3
AD15/ROMA2
AD16/ROMD0
AD17/ROMD1
AD18/ROMD2
AD19/ROMD3
AD20/ROMD4
AD21/ROMD5
AD22/ROMD6
AD23/ROMD7

CBE1#/ROMA1

FRAME#

PAR/ROMA19

REQ3#/GPIO70
REQ4#/GPIO71

GNT3#/GPIO72
GNT4#/GPIO73

CLKRUN#

INTE#/GPIO33
INTF#/GPIO34

INTG#/GPIO35

INTH#/GPIO36

LFRAME#

LDRQ0#

SERIRQ

RTCCLK

RTC_GND

PCI_AD[0..31] 17,20

R383 22_0402_5%

1 2

R381 22_0402_5%

1 2

R385 22_0402_5%

1 2

R384 22_0402_5%

1 2

8.2K_0402_5%

1 2

PCI_CBE#0 20
PCI_CBE#1 20
PCI_CBE#2 20
PCI_CBE#3 20
PCI_FRAME# 20
PCI_DEVSEL# 20
PCI_IRDY# 20
PCI_TRDY# 20
PCI_PAR 20
PCI_STOP# 20
PCI_PERR#
PCI_SERR#
PCI_REQ#0 20

PCI_GNT#0 20

PM_CLKRUN# 20,25

PCI_PIRQE#
PCI_PIRQF#

PCI_PIRQG# 20

LPC_AD0 24,25
LPC_AD1 24,25
LPC_AD2 24,25
LPC_AD3 24,25
LPC_FRAME# 24,25

SIRQ 25
RTC_CLK 17

RTC_IRQ# 17

+SB_VBAT

1

2

C621

C290
1U_0603_10V6K

2

1

CMOS_C @OPEN

R368

1 2

33_0402_5%

R369

1

1

2007-11-15 ATI recommend change PCI clock pin

CLK_PCI_CB 20

CLK_PCI_SIO_DB 24

PCICLK4_R 17
CLK_PCI_TPM
CLK_PCI_EC 25

PCI_RST#PCIRST#

W=20mils

2

PCI_RST# 20,24

R372
100_0402_1%

1 2

2

+RTCBATT

PCICLK0_RA_RST#
PCICLK1_R

PCICLK6_R

CLK_PCI_TPM
CLK_PCI_CB
CLK_PCI_EC

PCICLK0_R 17
PCICLK1_R 17

PCICLK6_R 17

C558 10P_0402_25V8K@

1 2

C306 10P_0402_25V8K@

1 2

C307 10P_0402_25V8K@

1 2

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2008/1/3 2009/01/3

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

SB600-PCI_EXP/PCI/LPC/RTC
LA-4191P

1

of

15 39Monday, January 14, 2008

0.3

5

4

3

2

1

Reserve for EMI, close to B23 pin

SB_OSC_INT

12

R106

@

33_0402_5%

D D

C C

B B

2

C234

@

22P_0402_50V8J

1

+3VS

R336 10K_0402_5%

1 2

R341 2.2K_0402_5%

1 2

R335 2.2K_0402_5%

1 2

R139 10K_0402_5%

1 2

@

PWM_CTRL

SMB_CK_CLK1
SMB_CK_DAT1

SB_HD_RST#

AC97_SDOUT17

EC_SWI#25

EC_SCI#25

SLP_S3#25
SLP_S5#25

PWRBTN_OUT#25

SB_PWRGD6,25

W_DISABLE#24,25

PCIE_WAKE#20,21,25,26
H_THERMTRIP#6

EC_RSMRST#25

SB_OSC_INT13

SB_SPKR23
SMB_CK_CLK18,9,13,26
SMB_CK_DAT18,9,13,26

HD_BITCLK22
HD_SDOUT22
HD_SDIN322
HD_SYNC22
HD_RST#22

TP53
TP55
TP56
TP57

EC_GA2025
KB_RST#25

2006-10-02 Configure unused GPIO to output

PCIE_WAKE#

2006-10-02 Configure unused GPIO to output

2006-10-02 Configure unused GPIO to output

R104 10K_0402_5%
R105 10K_0402_5%

2006-10-02 Configure unused GPIO to output

EC_SMI#25

NC_PWR_EN#26

OVCUR#327

EC_LID_OUT#25

OVCUR#1
OVCUR#027

1 2
1 2

1 2
1 2

SB_SUS_STAT

1 2

0_0402_5%

1 2
1 2

R42233_0402_5%
R38733_0402_5%

R13833_0402_5%
R15833_0402_5%

EC_SWI#
EC_SCI#
SLP_S3#
SLP_S5#
PWRBTN_OUT#
SB_PWRGD

SB_TEST2
SB_TEST1

SB_TEST0
EC_GA20
KB_RST#

R710

H_THERMTRIP#

EC_RSMRST#
SB_OSC_INT

PWM_CTRL

SB_SPKR
SMB_CK_CLK1
SMB_CK_DAT1

EC_SMI#

NC_PWR_EN#

OVCUR#3

EC_LID_OUT#

OVCUR#1
OVCUR#0

SB_HD_BITCLK

SB_HD_SDOUT

HD_SDIN3

SB_HD_SYNC

SB_HD_RST#

U600D

A3

PCI_PME#/GEVENT4#

B2

RI#/EXTEVNT0#

F7

SLP_S3#

A5

SLP_S5#

E3

PWR_BTN#

B5

PWR_GOOD

B3

SUS_STAT#

F9

TEST2

E9

TEST1

G9

TEST0

AF26

GA20IN

AG26

KBRST#

D7

LPC_PME#/GEVENT3#

C25

LPC_SMI#/EXTEVNT1#

D9

S3_STATE/GEVENT5#

F4

SYS_RESET#/GPM7#

E7

WAKE#/GEVENT8#

C2

BLINK/GPM6#

G7

SMBALERT#/THRMTRIP#/GEVENT2#

E2

RSMRST#

B23

14M_OSC

C28

SATA_IS0#/GPIO10

A26

ROM_CS#/GPIO1

B29

GHI#/SATA_IS1#/GPIO6

A23

WD_PWRGD/GPIO7

B27

SMARTVOLT/SATA_IS2#/GPIO4

D23

SHUTDOWN#/GPIO5

B26

SPKR/GPIO2

C27

SCL0/GPOC0#

B28

SDA0/GPOC1#

C3

SCL1/GPOC2#

F3

SDA1/GPOC3#

D26

DDC1_SCL/GPIO9

C26

DDC1_SDA/GPIO8

A27

SSMUXSEL/SATA_IS3#/GPIO0

A4

LLB#/GPIO66

C6

USB_OC9#/SLP_S2/GPM9#

C5

USB_OC8#/AZ_DOCK_RST#/GPM8#

C4

USB_OC7#/GEVENT7#

B4

USB_OC6#/GEVENT6#

B6

USB_OC5#/DDR3_RST#/GPM5#

A6

USB_OC4#/GPM4#

C8

USB_OC3#/GPM3#

C7

USB_OC2#/GPM2#

B8

USB_OC1#/GPM1#

A8

USB_OC0#/GPM0#

N2

AZ_BITCLK

M2

AZ_SDOUT

K2

AZ_SDIN3/GPIO46

L3

AZ_SYNC

K3

AZ_RST#

L1

AC_BITCLK/GPIO38

L2

AC_SDOUT/GPIO39

L4

ACZ_SDIN0/GPIO42

J2

ACZ_SDIN1/GPIO43

J4

ACZ_SDIN2/GPIO44

M3

AC_SYNC/GPIO40

L5

AC_RST#/GPIO45

E23

NC1

AC21

NC2

AD7

NC3

AE7

NC4

AA4

NC5

T4

NC6

D4

NC7

AB19

NC8

218S6ECLA13FG FCBGA 548P

SB600 SB 23x23mm

ACPI / WAKE UP EVENTS

OSC / RST

GPIO

USB OC

AC97 AZALIA

Part 4 of 4

USBCLK
USB_RCOMP
USB_ATEST1

USB_ATEST0

USB_HSDP9+

USB_HSDM9-

USB_HSDP8+

USB_HSDM8-

USB_HSDP7+

USB_HSDM7-

USB_HSDP6+

USB_HSDM6-

USB_HSDP5+

USB_HSDM5-

USB_HSDP4+

USB INTERFACE

USB_HSDM4-

USB_HSDP3+

USB_HSDM3-

USB_HSDP2+

USB_HSDM2-

USB_HSDP1+

USB_HSDM1-

USB_HSDP0+

USB_HSDM0-

AVDDTX_0
AVDDTX_1
AVDDTX_2
AVDDTX_3
AVDDTX_4
AVDDRX_0
AVDDRX_1
AVDDRX_2
AVDDRX_3
AVDDRX_4

AVDDC

AVSSC

AVSS_USB_1
AVSS_USB_2
AVSS_USB_3
AVSS_USB_4
AVSS_USB_5
AVSS_USB_6
AVSS_USB_7
AVSS_USB_8
AVSS_USB_9

AVSS_USB_10
AVSS_USB_11
AVSS_USB_12

USB PWR

AVSS_USB_13
AVSS_USB_14
AVSS_USB_15
AVSS_USB_16
AVSS_USB_17
AVSS_USB_18
AVSS_USB_19
AVSS_USB_20
AVSS_USB_21
AVSS_USB_22
AVSS_USB_23
AVSS_USB_24
AVSS_USB_25
AVSS_USB_26
AVSS_USB_27
AVSS_USB_28
AVSS_USB_29
AVSS_USB_30
AVSS_USB_31
AVSS_USB_32
AVSS_USB_33

USBCLK_EXT

A17
A14
A11

A10
H12

G12
E12

D12
E14

D14
G14

H14
D16

E16
D18

E18
G16

H16
G18

H18
D19

E19
G19

H19

+AVDDTX

B9
B11
B13
B16
B18
A9
B10
B12
B14
B17

+AVDDC

A12
A13
A16

C9
C10
C11
C12
C13
C14
C16
C17
C18
C19
C20
D11
D21
E11
E21
F11
F12
F14
F16
F18
F19
F21
G11
G21
H11
H21
J11
J12
J14
J16
J18
J19

USBCLK_EXT 13

USB20P9+ 27
USB20P9- 27

USB20P8+ 24
USB20P8- 24

USB20P7+ 27
USB20P7- 27

USB20P6+ 26
USB20P6- 26

USB20P5+ 27
USB20P5- 27

USB20P4+ 27
USB20P4- 27

USB20P3+ 27
USB20P3- 27

USB20P2+ 27
USB20P2- 27

USB20P1+ 27
USB20P1- 27

USB20P0+ 27
USB20P0- 27

R34911.8K_0402_1%

1 2

RX 20mil, TX 20mil

1

1

C2620.1U_0402_16V7K~N

C2530.1U_0402_16V7K~N

C2630.1U_0402_16V7K~N

2

2

20mil

+AVDDC

1

C534

2

2.2U_0603_10V6K

+3VS

0.5A

1

1

C2731U_0603_10V6K

2

C533

1

1

C2561U_0603_10V6K

C2741U_0603_10V6K

2

2

2

1 2

KC FBM-L11-201209-221LMAT_0805

1

2

0.1U_0402_16V7K~N

L27

1 2

1

KC FBM-L11-201209-221LMAT_0805

C25422U_0805_6.3V6M

2

+3VS

L44

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2008/1/3 2009/01/3

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

SB600 USB/ACPI/AC97/GPIO
LA-4191P

1

of

16 39Monday, January 14, 2008

0.3

5

4

3

2

1

SATA_DTX_IRX_P0
SATA_DTX_IRX_N0

SATA_ITX_DRX_N0
SATA_ITX_DRX_P0

D D

L23

12

12

L25

L24

R126
10K_0402_5%

+1.2V_AVDD_SATA

1

C240

2

22U_0805_6.3V6M

Y4

1 2

1

C258

2

1

C250

2

+3VS

SATA_LED#28

0.6A

+1.2V_HT

C C

25MHZ_12P_X8A025000FC1H-H

B B

+1.2V_HT

+3VS

A A

1 2

FBMA-L11-201209-221LMA30T

C525

10P_0402_50V8J

C520

10P_0402_50V8J

0.1A

1 2

CHB1608U301_0603

1U_0402_6.3V6K

1 2

CHB1608U301_0603

1U_0402_6.3V6K

1

2

1U_0402_6.3V6K

12

R347
10M_0402_5%

TP61
TP62

TP63
TP64

R116 1K_0402_1%

12

C238

SATA_X1

SATA_X2

+PLLVDD_ATA

1

1U_0402_6.3V6K

2

+XTLVDD_ATA

1U_0402_6.3V6K

C249

1

C229

2

12

0.1U_0402_16V7K~N

SATA_DTX_IRX_P2
SATA_DTX_IRX_N2

SATA_ITX_DRX_N2
SATA_ITX_DRX_P2

SATA_CAL
SATA_X1
SATA_X2

SATA_LED#
+PLLVDD_ATA

+XTLVDD_ATA

1

1

C248

C239

2

2

0.1U_0402_16V7K~N

U600B

AH21

SATA_TX0+

AJ21

SATA_TX0-

AH20

SATA_RX0-

AJ20

SATA_RX0+

AH18

SATA_TX1+

AJ18

SATA_TX1-

AH17

SATA_RX1-

AJ17

SATA_RX1+

AH13

SATA_TX2+

AH14

SATA_TX2-

AH16

SATA_RX2-

AJ16

SATA_RX2+

AJ11

SATA_TX3+

AH11

SATA_TX3-

AH12

SATA_RX3-

AJ13

SATA_RX3+

AF12

SATA_CAL

AD16

SATA_X1

AD18

SATA_X2

AC12

SATA_ACT#/GPIO67

AD14

PLLVDD_SATA_1

AJ10

PLLVDD_SATA_2

AC16

XTLVDD_SATA

AE14

AVDD_SATA_1

AE16

AVDD_SATA_2

AE18

AVDD_SATA_3

AE19

AVDD_SATA_4

AF19

AVDD_SATA_5

AF21

AVDD_SATA_6

AG22

AVDD_SATA_7

AG23

AVDD_SATA_8

AH22

AVDD_SATA_9

AH23

AVDD_SATA_10

AJ12

AVDD_SATA_11

AJ14

AVDD_SATA_12

AJ19

AVDD_SATA_13

AJ22

AVDD_SATA_14

AJ23

AVDD_SATA_15

AB14

AVSS_SATA_1

AB16

AVSS_SATA_2

AB18

AVSS_SATA_3

AC14

AVSS_SATA_4

AC18

AVSS_SATA_5

AC19

AVSS_SATA_6

AD12

AVSS_SATA_7

AD19

AVSS_SATA_8

AD21

AVSS_SATA_9

AE12

AVSS_SATA_10

AE21

AVSS_SATA_11

AF11

AVSS_SATA_12

AF14

AVSS_SATA_13

AF16

AVSS_SATA_14

AF18

AVSS_SATA_15

AG11

AVSS_SATA_16

AG12

AVSS_SATA_17

AG13

AVSS_SATA_18

AG14

AVSS_SATA_19

AG16

AVSS_SATA_20

AG17

AVSS_SATA_21

AG18

AVSS_SATA_22

AG19

AVSS_SATA_23

AG20

AVSS_SATA_24

AG21

AVSS_SATA_25

AH10

AVSS_SATA_26

AH19

AVSS_SATA_27

218S6ECLA13FG FCBGA 548P

SATA_DTX_IRX_N0

SATA_DTX_IRX_P0 SATA_DTX_C_IRX_P0

SATA_ITX_DRX_N0

SATA_ITX_DRX_P0 SATA_ITX_C_DRX_P0

SB600 SB 23x23mm

Part 2 of 4

SERIAL ATA

ATA 66/100

SPI_HOLD#/GPIO31

SPI ROMHW MONITOR

ROM_RST#/GPIO14

TEMPIN3/TALERT#/GPIO64

SERIAL ATA POWER

SATA_DTX_C_IRX_N0

12

C519 0.01U_0402_16V7K

12

C514 0.01U_0402_16V7K

SATA_ITX_C_DRX_N0

12

C579 0.01U_0402_16V7K

12

C578 0.01U_0402_16V7K

close to connector

IDE_D0/GPIO15
IDE_D1/GPIO16
IDE_D2/GPIO17
IDE_D3/GPIO18
IDE_D4/GPIO19
IDE_D5/GPIO20
IDE_D6/GPIO21
IDE_D7/GPIO22
IDE_D8/GPIO23

IDE_D9/GPIO24
IDE_D10/GPIO25
IDE_D11/GPIO26
IDE_D12/GPIO27
IDE_D13/GPIO28
IDE_D14/GPIO29
IDE_D15/GPIO30

SPI_DO/GPIO11
SPI_CLK/GPIO47

SPI_CS#/GPIO32

LAN_RST#/GPIO13

FANOUT0/GPIO3

FANOUT1/GPIO48
FANOUT2/GPIO49

FANIN0/GPIO50

FANIN1/GPIO51

FANIN2/GPIO52

TEMPIN0/GPIO61
TEMPIN1/GPIO62
TEMPIN2/GPIO63

IDE_IORDY

IDE_IRQ

IDE_A0
IDE_A1
IDE_A2

IDE_DACK#

IDE_DRQ

IDE_IOR#

IDE_IOW#

IDE_CS1#
IDE_CS3#

SPI_DI/GPIO12

TEMP_COMM

VIN0/GPIO53
VIN1/GPIO54
VIN2/GPIO55
VIN3/GPIO56
VIN4/GPIO57
VIN5/GPIO58
VIN6/GPIO59
VIN7/GPIO60

AVDD
AVSS

IDEIORDYA

AB29

IDEIRQA

AA28

IDESAA0

AA29

IDESAA1

AB27

IDESAA2

Y28

IDEDACK#A

AB28

IDEREQA

AC27

IDEIOR#A

AC29

IDEIOW#A

AC28

IDECS#A1

W28

IDECS#A3

W27

IDEDA0

AD28

IDEDA1

AD26

IDEDA2

AE29

IDEDA3

AF27

IDEDA4

AG29

IDEDA5

AH28

IDEDA6

AJ28

IDEDA7

AJ27

IDEDA8

AH27

IDEDA9

AG27

IDEDA10

AG28

IDEDA11

AF28

IDEDA12

AF29

IDEDA13

AE28

IDEDA14

AD25

IDEDA15

AD29

J3
J6
G3
G2
G6

C23
G5

M4
T3
V4

N3
P2
W4

P5
P7
P8
T8

EC_THERM#

T7
V5

L7
M8

2006-10-02 GPIO50-64 configure to output

V6
M6
P4
M7
V7

N1
M1

SATA_DTX_C_IRX_N0 19

SATA_DTX_C_IRX_P0 19

SATA_ITX_C_DRX_N0 19

SATA_ITX_C_DRX_P0 19

IDEIORDYA 19

IDEIRQA 19
IDESAA0 19
IDESAA1 19
IDESAA2 19
IDEDACK#A 19

IDEREQA 19
IDEIOR#A 19
IDEIOW#A 19
IDECS#A1 19
IDECS#A3 19
IDEDA[0..15] 19

AC97_SDOUT16

RTC_IRQ#15

RTC_CLK15
PCICLK4_R15
PCICLK6_R15
PCICLK0_R15
PCICLK1_R15

+3VS

R137
10K_0402_5%

1 2

EC_THERM# 25

DEBUG STRAPS

+3VS

0.1U_0402_16V7K~N

2.2U_0603_10V6K

1

1

C286

C287

2

2

SB600 HAS 15K INTERNAL PU FOR PCI_AD[28:23]

REQUIRED STRAPS

SB600 HAS 15K INTERNAL PD FOR AC_SDATA_OUT,
15K PU FOR RTC_CLK, EXTERNAL PU/PD IS
NOT REQUIRED; FOR SB460, EXTERNAL PU/PD ARE
REQUIRED

+3VS+3VS +3VS +3VS +3VS+3VALW +3VALW

12

R424

2.2K_0402_5%

PULL
HIGH

PULL
LOW

12

R140
10K_0402_5%

@

@

AC_SDOUT

USE
DEBUG
STRAPS

IGNORE
DEBUG
STRAPS

DEFAULT

PCI_AD27 PCI_AD25PCI_AD26 PCI_AD24

12

R377
10K_0402_5%

@

12

R150
10K_0402_5%

@

12

R147
10K_0402_5%

@

RTC_CLK

INTERNAL
RTC

DEFAULT

EXTERNAL
RTC

PCI_AD27 PCI_AD26

PULL
HIGH

PULL
LOW

USE PCI
PLL

DEFAULT

BYPASS
PCI PLL

USE ACPI
BCLK

DEFAULT

BYPASS
ACPI
BCLK

12

R144
10K_0402_5%

@

12

R145
10K_0402_5%

PCI_CLK4 PCI_CLK6

USE INT.
PLL48

USE EXT.
48MHZ

DEFAULT

12

R379
10K_0402_5%

@

12

R152
10K_0402_5%

@

PCI_AD25 PCI_AD24

USE IDE
PLL

DEFAULT

BYPASS IDE
PLL

PCICLK6_RPCICLK4_RAC97_SDOUT RTC_CLK PCICLK0_R

CPU IF=K8

DEFAULT

CPU IF=P4

PCI_AD[0..31]

12

R378
10K_0402_5%

@

12

R151
10K_0402_5%

@

USE DEFAULT
PCIE STRAPS

DEFAULT

USE EEPROM
PCIE STRAPS

12

R382
10K_0402_5%

12

12

PCICLK1_R

PCI_CLK1 PCI_CLK0

ROM TYPE:
H, H = PCI ROM
H, L = LPC I ROM
L, H = LPC II ROM
L, L = FWH ROM

NOTE: FOR SB460, PCICLK[8:7] ARE
CONNECTED TO SUBSTRATE
BALLS PCICLK[1:0]

+3VS+3VS+3VS+3VS

12

R380
10K_0402_5%

@

2.2K IF USED FOR SB600.
10K IF USED FOR SB460.

12

R153
10K_0402_5%

@

R154
10K_0402_5%

@

R155
10K_0402_5%

PCI_AD[0..31] 15,20

12

R157
10K_0402_5%

12

R156
10K_0402_5%

@

DEFAULT

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2008/1/3 2009/01/3

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

SB600 IDE/SATA/HW Strap
LA-4191P

1

of

17 39Monday, January 14, 2008

0.3

+1.2VALW

R160
0_0805_5%

+1.2V_HT

R109 0_0805_5%

12

12

C299

C521

2

1

2

1

0.1A

C288

0.1U_0402_16V7K~N

C244

1U_0603_10V6K

+1.2V_HT

FBM-L11-321611-260-LMT_1206

+3VALW

R375
0_0805_5%

2

2

C289

1

1

0.1U_0402_16V7K~N

0.2A

2

2

C526

1

1

1U_0603_10V6K

L26

1 2

12

2

C272

1

0.1U_0402_16V7K~N

0.1U_0402_16V7K~N

2

C245

1

1U_0603_10V6K

1U_0603_10V6K

0.1A

+5VS

+3VS

1 2

+3VS

FBML10160808121LMT_0603

+3VS

1

+

C513

2

1A

C241

0.1A

C547

R123
1K_0402_5%

1 2

D4
RB751V_SOD323

2 1

L22

C261

150U_D2_6.3VM

1

2

1

2

C522

2

1

C252

22U_0805_6.3V6M

C298

22U_0805_6.3V6M

+USBPHY

1

2

2

C243

1

1U_0603_10V6K

2

C260

1

1U_0603_10V6K

2

C271

1

1U_0603_10V6K

+1.2VALW_SB

+1.8VS

FBML10160808121LMT_0603

1U_0603_10V6K

+SB_AVDDCK

2.2U_0603_10V6K

0.6A

C284

1U_0603_10V6K

2

C242

1

1U_0603_10V6K

2

1

1U_0603_10V6K

1 2

C257

2

C285

1

1U_0603_10V6K

2

1

+3VALW_SB

L20

2

1

2

C230

1

1U_0603_10V6K

+1.2VS_SB_VDD

2

C259

1

1U_0603_10V6K

1

C231

2

U600C

A25

SB600 SB 23x23mm

VDDQ_1

A28

VDDQ_2

2

2

C235

1

1

1U_0603_10V6K

1U_0603_10V6K

1U_0603_10V6K

+SB_CPUPWR

+V5_VREF
+SB_AVDDCK
+SB_AVDDCK_1.2V

0.1U_0402_16V7K~N

C29

VDDQ_3

D24

VDDQ_4

L9

VDDQ_5

L21

VDDQ_6

M5

VDDQ_7

P3

VDDQ_8

P9

VDDQ_9

T5

VDDQ_10

V9

VDDQ_11

W2

VDDQ_12

W6

VDDQ_13

W21

VDDQ_14

W29

VDDQ_15

AA12

VDDQ_16

AA16

VDDQ_17

AA19

VDDQ_18

AC4

VDDQ_19

AC23

VDDQ_20

AD27

VDDQ_21

AE1

VDDQ_22

AE9

VDDQ_23

AE23

VDDQ_24

AH29

VDDQ_25

AJ2

VDDQ_26

AJ6

VDDQ_27

AJ26

VDDQ_28

M13

VDD_1

M17

VDD_2

N12

VDD_3

N15

VDD_4

N18

VDD_5

R13

VDD_6

R17

VDD_7

U12

VDD_8

U15

VDD_9

U18

VDD_10

V13

VDD_11

V17

VDD_12

A2

S5_3.3V_1

A7

S5_3.3V_2

F1

S5_3.3V_3

J5

S5_3.3V_4

J7

S5_3.3V_5

K1

S5_3.3V_6

G4

S5_1.2V_1

H1

S5_1.2V_2

H2

S5_1.2V_3

H3

S5_1.2V_4

A18

USB_PHY_1.2V_1

A19

USB_PHY_1.2V_2

B19

USB_PHY_1.2V_3

B20

USB_PHY_1.2V_4

B21

USB_PHY_1.2V_5

AA27

CPU_PWR

AE11

V5_VREF

A24

AVDDCK_3.3V

A22

AVDDCK_1.2V

B22

AVSSCK

V29

PCIE_VSS_42

V28

PCIE_VSS_41

V27

PCIE_VSS_40

V26

PCIE_VSS_39

V25

PCIE_VSS_38

V24

PCIE_VSS_37

V23

PCIE_VSS_36

V22

PCIE_VSS_35

U27

PCIE_VSS_34

T29

PCIE_VSS_33

T28

PCIE_VSS_32

T27

PCIE_VSS_31

T24

PCIE_VSS_30

T21

PCIE_VSS_29

P27

PCIE_VSS_28

218S6ECLA13FG FCBGA 548P

Part 3 of 4

POWER

PCIE_VSS_10
PCIE_VSS_11
PCIE_VSS_12
PCIE_VSS_13
PCIE_VSS_14
PCIE_VSS_15
PCIE_VSS_16
PCIE_VSS_17
PCIE_VSS_18
PCIE_VSS_19
PCIE_VSS_20
PCIE_VSS_21
PCIE_VSS_22
PCIE_VSS_23
PCIE_VSS_24
PCIE_VSS_25
PCIE_VSS_26
PCIE_VSS_27

VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8

VSS_9
VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47
VSS_48
VSS_49
VSS_50
VSS_51
VSS_52
VSS_53
VSS_54
VSS_55
VSS_56
VSS_57

PCIE_VSS_1
PCIE_VSS_2
PCIE_VSS_3
PCIE_VSS_4
PCIE_VSS_5
PCIE_VSS_6
PCIE_VSS_7
PCIE_VSS_8
PCIE_VSS_9

A20
A21
A29
B1
B7
B25
C21
C22
C24
D6
E24
F2
F23
G1
J1
J8
L6
L8
M9
M12
M15
M18
N13
N17
P1
P6
P21
R12
R15
R18
T6
T9
U13
U17
V3
V8
V12
V15
V18
V21
W1
W9
Y29
AA11
AA14
AA18
AC6
AC24
AD9
AD23
AE3
AE27
AG6
AJ1
AJ25
AJ29

D27
D28
D29
F26
G23
G24
G25
H27
J23
J26
J28
K27
L22
L23
L24
L27
L28
M21
M24
M27
N27
N28
P22
P23
P24
P25
P26

+1.2V_HT

FBML10160808121LMT_0603

L19

1 2

C237

+SB_AVDDCK_1.2V

1

2

2.2U_0603_10V6K

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2008/1/3 2009/01/3

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

Date: Sheet

SB600 Power/GND
LA-4191P

of

18 39Monday, January 14, 2008

0.3

5

4

3

2

1

CDROM CONN(to FPC)

C295

0.1U_0402_16V7K~N

+5VS

1

C449

2

10U_0805_10V4Z~N

Close to ODD Conn

0.1U_0402_16V7K~N

1

C294

2

1

C450

2

1U_0603_10V6K

1

2

1

C440

2

0.1U_0402_16V7K~N

1

C277

2

1000P_0402_50V7K~N

1

C441

2

1000P_0402_50V7K~N

GND
HTX+
HTX­GND
HRX­HRX+
GND

VCC3.3
VCC3.3
VCC3.3
GND
GND
GND
VCC5
VCC5
VCC5
GND
RESERVED
GND
VCC12
VCC12
VCC12

JODD1

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

11

11

12

12

13

13

14

14

15

15

16

16

17

17

18

18

19

19

20

20

21

21

22

22

23

23

24

24

25

25

26

26

27

27

28

28

29

29

30

30

31

31

32

32

33

33

34

34

35

35

36

36

37

37

38

38

39

39

40

40

41

41

42

42

43

43

44

44

45

45

46

GND

47

GND

ACES_88512-4541

27

NC

28

NC

23

GND

24

GND

25

GND

26

GND

C543

150U_D2_6.3VM

+5VS

+

1

2

1

C564

2

Close to SATA HDD

10U_0805_10V4Z~N

IDEDA[0..15] 17

D D

+5VS

12

ODD_ACT_LED#

+5VS

ODD_ACT_LED#

R257
10K_0402_5%@

12

ODD_ACT_LED#28

R256

100K_0402_5%

C C

C183 47P_0402_50V8J

12

NB_RST#11,15,21,24,25,26

IDEREQA17

IDEIOR#A17
IDEIOW#A17

IDEIORDYA17

IDEDACK#A17

IDEIRQA17

IDESAA117
IDESAA017

IDESAA217

IDECS#A117
IDECS#A317

+5VS

NB_RST#

IDEDA8
IDEDA7
IDEDA9
IDEDA6
IDEDA10
IDEDA5
IDEDA11
IDEDA4
IDEDA12
IDEDA3
IDEDA13
IDEDA2
IDEDA14
IDEDA1
IDEDA15
IDEDA0

IDEIOR#A
IDEIOW#A

IDEIORDYA
IDEDACK#A
IDEIRQA
IDESAA1
PDIAG#
IDESAA0

IDECS#A1

IDEREQA

IDESAA2
IDECS#A3

If CDROM is Slave
then SD_CSEL= Floating
else SD_CSEL= Low

SATA_DTX_C_IRX_P017

B B

SATA_DTX_C_IRX_N017
SATA_ITX_C_DRX_N017

SATA_ITX_C_DRX_P017

R242 470_0402_5%

SATA_DTX_C_IRX_P0
SATA_DTX_C_IRX_N0

SATA_ITX_C_DRX_N0
SATA_ITX_C_DRX_P0

80mils

+5VS

SD_CSEL

12

SATA HDD CONN

JSATA1

S1
S2
S3
S4
S5
S6
S7

P1
P2
P3
P4
P5
P6
P7
P8

P9
P10
P11
P12
P13
P14
P15

SUYIN_127043FR022G226ZL

CONN@

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2008/1/3 2009/01/3

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

HDD/CDROM
LA-4191P

1

0.3

of

19 39Monday, January 14, 2008

5

Q47

+1.8V

AO3413_SOT23

D

S

13

G

R701

SUSP

12

R702
470_0805_5%

DISCHG_1.8VS_OZ

13

D

Q48

S

1 2

100K_0402_5%

0.01U_0402_16V7K

IEEE1394_TPBIAS0

R543

R551

C658

C697

R527

C647

PM_CLKRUN#15,25

56.2_0402_1%

12

56.2_0402_1%

12

2

1

SUSP29,34

D D

C C

B B

A A

+1.8VS_OZ

SUSP

2

G

SSM3K7002FU_SC70-3

2

C635

1

2

CLK_PCI_CB

@

10_0402_5%

12

@

4.7P_0402_50V8C

CLK_PCI_CB_TERM

2

1

R529

1 2

100_0402_1%

56.2_0402_1%

12

R544

56.2_0402_1%

12

R552

270P_0402_50V7K

5.1K_0402_1%

R553

1 2

1

1

C634

2

4.7U_0805_6.3V6K~N

PCI_AD[0..31]15,17

CLK_PCI_CB15
PCI_DEVSEL#15
PCI_FRAME#15

PCI_IRDY#15
PCI_TRDY#15
PCI_STOP#15

PCI_PIRQG#15
PCIE_WAKE#16,21,25,26

R532 100K_0402_5%@
R531 0_0402_5%

C656

IEEE1394_TPAP0
IEEE1394_TPAN0
IEEE1394_TPBP0
IEEE1394_TPBN0

1

C633

2

2

0.1U_0402_16V7K~N

PCI_CBE#315
PCI_CBE#215
PCI_CBE#115
PCI_CBE#015

PCI_PAR15
PCI_REQ#015
PCI_GNT#015
PCI_RST#15,24

12

1 2

LED behave:
Idel ---------> low
Accress data --> always high

1

2

1U_0402_6.3V6K

C638

0.1U_0402_16V7K~N

PCI_AD31
PCI_AD30
PCI_AD29
PCI_AD28
PCI_AD27
PCI_AD26
PCI_AD25
PCI_AD24
PCI_AD23
PCI_AD22
PCI_AD21
PCI_AD20
PCI_AD19
PCI_AD18
PCI_AD17
PCI_AD16
PCI_AD15
PCI_AD14
PCI_AD13
PCI_AD12
PCI_AD11
PCI_AD10
PCI_AD9
PCI_AD8
PCI_AD7
PCI_AD6
PCI_AD5
PCI_AD4
PCI_AD3
PCI_AD2
PCI_AD1
PCI_AD0

PCI_CBE#3
PCI_CBE#2
PCI_CBE#1
PCI_CBE#0

CBS_IDSELPCI_AD21
CLK_PCI_CB
PCI_DEVSEL#
PCI_FRAME#
PCI_IRDY#
PCI_TRDY#
PCI_STOP#
PCI_PAR
PCI_REQ0#
PCI_GNT0#
PCI_RST#
PCI_PIRQG#

R694

@

1 2

0_0402_5%

IEEE1394_TPAP0 27
IEEE1394_TPAN0 27
IEEE1394_TPBP0 27
IEEE1394_TPBN0 27

Layout Note: Place close to OZ129 Chipset.

5

+3VS_OZ

1

C637

2

4.7U_0805_6.3V6K~N

CB_PME#

4

20mil 40mil

7

103

102

VCC3.3

VCC3.3

82

+3VS_PHY

73

67

122

AVCC

VCC3.3

VCC3.3

MC_3V#

SD_CLK/MS_CLK

SD_CMD

SD_CD#

MS_D1/XD_D7

MS_BS/XD_D3
MS_D0/XD_D2
MS_D2/XD_D1
MS_D3/XD_D0

XD_CE#
XD_RB#
XD_CLE
XD_ALE

XD_WE#

XD_RE#

XD_WPO#

MS_CD#

XD_CD#

PHY_TEST0
PHY_TEST1

AGND

AGND

AGND

AGND70AGND

80

77

69

65

AVCC

TPBIAS

SD_D3
SD_D2
SD_D1
SD_D0

SD_WP

XD_D6
XD_D5
XD_D4

AGND

20mil

1

2

U32

0.1U_0402_16V7K~N

19

AD31

20

AD30

21

AD29

22

AD28

23

AD27

24

AD26

25

AD25

27

AD24

29

AD23

30

AD22

31

AD21

32

AD20

34

AD19

35

AD18

36

AD17

37

AD16

47

AD15

48

AD14

49

AD13

50

AD12

51

AD11

52

AD10

53

AD9

54

AD8

57

AD7

58

AD6

59

AD5

60

AD4

61

AD3

62

AD2

63

AD1

64

AD0

28

C/BE3#

38

C/BE2#

46

C/BE1#

55

C/BE0#

5

IDSEL

45

PCI_CLK

42

DEVSEL#

39

FRAME#

40

IRDY#

41

TRDY#

43

STOP#

44

PAR

17

PCI_REQ#

18

PCI_GNT#

1

PCI_RST#

11

INTA#

3

PME#

6

CLKRUN#

106

MEDIA_LED

4

26

PCI_VCC

GND

12

56

PCI_VCC

GND

GND

16

33

15

91

VCC1.814VCC1.8

OZ129

GND

GND

GND

GND

68

66

115

104

125

120

VCC1.8

VCC1.8

VCC1.892VCC1.8

GND

GND

GND

GND

124

123

121

116

C631

20mil

81

79

AVCC

AVCC

REF

XI

XO

TPA+

TPA-

TPB+

TPB-

NC
NC
NC
NC
NC
NC
NC
NC

FBML10160808121LMT_0603

78
83

84
76

75
74
72
71

4
113
111
112
107
108
110
117
114

95
93
89
87
88
90
94
96
119
100
118
109
105
101
98
99
97

85
86

2
8
9
10
13
126
127
128

L61

1 2

R520 5.9K_0402_1%

1 2

OZ129XI
OZ129XO

IEEE1394_TPBIAS0
IEEE1394_TPAP0
IEEE1394_TPAN0
IEEE1394_TPBP0
IEEE1394_TPBN0

MC_3V#
SDCLK_MSCLK
SDD3
SDD2
SDD1
SDD0
SD_CMD
SD_WP
SDCD#

XDD7_MSD1
XD_D6
XD_D5
XD_D4
XDD3_MSBS
XDD2_MSD0
XDD1_MSD2
XDD0_MSD3
XDCE#
XDRB#
XDCLE
XDALE
XDWE#
XDRE#
XDWP#
MSCD#
XDCD#

MMCD4
MMCD5

MMCD6
MMCD7

OZ129TN_LQFP128_14X14

3

+3VS_OZ+1.8VS_OZ

1

1

C630

2

2

0.1U_0402_16V7K~N

4.7U_0805_6.3V6K~N

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

R525
0_0805_5%

12

+3VS_OZ

R536
22K_0402_5%

+3VS

+3VS_OZ

FBML10160808121LMT_0603

+3VS_OZ

MC_3V#

1

C660

2

0.1U_0402_16V7K~N

XDD0_MSD3

R572 0_0402_5%

XDD1_MSD2
XDD2_MSD0
XDD3_MSBS
XD_D4
XD_D5
XD_D6
XDD7_MSD1

XDWE#
XDWP#
XDALE
XDCD#
XDRB#
XDRE#
XDCE#
XDCLE

1 2

R573 0_0402_5%

1 2

R574 0_0402_5%

1 2

R576 0_0402_5%

1 2

R578 0_0402_5%

1 2

R580 0_0402_5%

1 2

R582 0_0402_5%

1 2

R584 0_0402_5%

1 2

R587 0_0402_5%

1 2

R589 0_0402_5%

1 2

R590 0_0402_5%

1 2

R592 0_0402_5%

1 2

R594 0_0402_5%

1 2

R596 0_0402_5%

1 2

R597 0_0402_5%

1 2

R598 0_0402_5%

1 2

2008/1/3 2009/01/3

Compal Secret Data

2

L59

1 2

1

C641

2

U10

5

IN

4

EN
GND2N.C.

RT9711DPBG_SOT23-5

1

OUT

3

C323

+3VS_CR +3VS_CR

J8IN1

3

XDD0
XDD1
XDD2
XDD3
XDD4
XDD5
XDD6
XDD7

XDWE
XDWP
XD_ALE
XDCD
XDRB
XDRE
XDCE
XD_CLE

XD-VCC

32

XD-D0

10

XD-D1

9

XD-D2

8

XD-D3

7

XD-D4

6

XD-D5

5

XD-D6

4

XD-D7

34

XD-WE

33

XD-WP

35

XD-ALE

40

XD-CD

39

XD-R/B

38

XD-RE

37

XD-CE

36

XD-CLE

11

7in1-GND

31

7in1-GND

41

7in1-GND

42

7in1-GND

TAITW_R015-A10-LM

Deciphered Date

2

+3VS_PHY

1

C639

2

0.1U_0402_16V7K~N

C648

12

C649

12

+3VS_CR

1

C659

2

1U_0402_6.3V6K

0.01U_0402_16V7K

1

2

4.7U_0805_6.3V6K~N

X1

24.576MHz_16P_3XG-24576-43E1

1 2

C655

SD-VCC
MS-VCC

SD_CLK
SD-DAT0
SD-DAT1
SD-DAT2
SD-DAT3
SD-DAT4
SD-DAT5
SD-DAT6
SD-DAT7

SD-CD

SD-WP

SD-CMD

MS-SCLK

MS-BS

MS-INS

MS-DATA0
MS-DATA1
MS-DATA2
MS-DATA3

C642

0.1U_0402_16V7K~N

Layout Note: Place close to
OZ129 and Shield GND.

22P_0402_50V8J

22P_0402_50V8J

1

2

7 IN 1 CONN

All DATA spacing=8mil, CLK spacing=15mil

1

OZ129XI

OZ129XO

SDCLK

1

C692

10P_0402_50V8J

+3VS_CR

1

1

C652

2

2

0.1U_0402_16V7K~N

4.7U_0805_6.3V6K~N

21
28

SDCLK

20
14
12
30
29
27
23
18
16

1
2
25

26
13
22

17
15
19
24

Title

Size Document Number Rev

Date: Sheet

R542 22_0402_5%

SDDAT0

R575 0_0402_5%

SDDAT1

R577 0_0402_5%

SDDAT2

R579 0_0402_5%

SDDAT3

R581 0_0402_5%

SDDAT4

R583 0_0402_5%

SDDAT5

R585 0_0402_5%

SDDAT6

R586 0_0402_5%

SDDAT7

R588 0_0402_5%

SDCD

R591 0_0402_5%

SDWP

R593 0_0402_5%

SDCMD

R595 0_0402_5%

MSCLK

R549 22_0402_5%

MSBS

R599 0_0402_5%

MSINS

R600 0_0402_5%

MSDATA0

R601 0_0402_5%

MSDATA1

R602 0_0402_5%

MSDATA2

R603 0_0402_5%

MSDATA3

R604 0_0402_5%

OZ129 Media Card/1394

Monday, January 14, 2008

1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2

1 2
1 2
1 2

1 2
1 2
1 2

1 2
1 2
1 2
1 2

LA-4191P

10P_0402_50V8J

1

@

MSCLK

C693

@

2

1

2

SDCLK_MSCLK
SDD0
SDD1
SDD2
SDD3
MMCD4
MMCD5
MMCD6
MMCD7

SDCD#
SD_WP
SD_CMD

SDCLK_MSCLK
XDD3_MSBS
MSCD#

XDD2_MSD0
XDD7_MSD1
XDD1_MSD2
XDD0_MSD3

of

20 39

0.3

5

PCIE_LAN_C_RX_P210

PCIE_LAN_C_RX_N210

D D

+LAN_AVDD12

60mil

1

C17

+3VS

12

R210

1K_0402_5%

15K_0402_5%

C C

C13 0.01U_0402_16V7K

1 2

C11 0.01U_0402_16V7K

1 2

C12 0.01U_0402_16V7K

1 2

C10 0.01U_0402_16V7K

LAN_LED2

LAN_LED3

LAN_LED1

LAN_LED3

1 2

RB751V_SOD323

8111C@

RB751V_SOD323

8111C@

RB751V_SOD323

8111C@

RB751V_SOD323

8111C@

B B

A A

R211

1 2

+LAN_IO

12

R704
1K_0402_5%

D36

LED2_LED3

21

D37

21

D38

LED1_LED3

21

D39

21

8111C@

+LAN_IO

12

R705
1K_0402_5%

8111C@

5

1

C365

2

2

0.1U_0402_16V7K~N

V_DAC
MDIN3
MDIP3

V_DAC
MDIN2
MDIP2

V_DAC
MDIN1
MDIP1

V_DAC
MDIN0
MDIP0

LAN_LED2
LAN_LED1

PCIE_LAN_C_RX_P2
PCIE_LAN_C_RX_N2

L32

1 2

4.7UH_1098AS-4R7M_1.3A_20%

8111C@

R568

1 2

0_0805_5%

22U_0805_6.3V6M

8102E@

close to RTL8111C pin1

Y2

25MHZ_12P_X8A025000FC1H-H

1 2

2

C375
15P_0402_50V8J

1

T1

1

TCT1

MCT1

2

TD1+

MX1+

3

TD1-

MX1-

4

TCT2

MCT2

5

TD2+

MX2+

TD2-6MX2-

7

TCT3

MCT3

8

TD3+

MX3+

9

TD3-

MX3-

10

TCT4

MCT4

11

TD4+

MX4+

12

TD4-

MX4-

BOTH_GST5009-LF

8102E@

10/100: TST1284(SP050001X10), NS892404(SP050003P00)
GIGALAN: GST5009(SP050005610), NS892402(SP050002I00)

LAN_LED0

R706
0_0402_5%

8102E@

LED2_LED3

1 2

LED1_LED3

1 2

R708
0_0402_5%

8102E@

C378 0.1U_0402_16V7K~N
C379 0.1U_0402_16V7K~N

PCIE_LAN_C_TX_P210
PCIE_LAN_C_TX_N210

CLK_PCIE_LAN13
CLK_PCIE_LAN#13

PCIE_WAKE#16,20,25,26

24

RJ45_TX3-

23

RJ45_TX3+

22
21

RJ45_TX2-

20

RJ45_TX2+

19
18

RJ45_RX1-

17

RJ45_RX1+

16
15

RJ45_TX0-

14

RJ45_TX0+

13

R703

1 2

220_0402_5%

+LAN_IO

R707

1 2

R709

1 2

+LAN_IO

4

1 2
1 2

NB_RST#11,15,19,24,25,26

60mil

+LAN_IO

2

C374
12P_0402_50V8J~N

1

+LAN_DVDD12

LAN_ACTIVITY#

RJ45_TX3­RJ45_TX3+
RJ45_RX1­RJ45_TX2­RJ45_TX2+
RJ45_RX1+
RJ45_TX0­RJ45_TX0+
LINK_10

220_0402_5%

LINK_100

220_0402_5%

4

RTL_LAN_TX_P2

RTL_LAN_TX_N2
PCIE_LAN_C_TX_P2
PCIE_LAN_C_TX_N2

CLK_PCIE_LAN
CLK_PCIE_LAN#
NB_RST#

+LAN_SROUT12

+LAN_AVDD12

R610 0_0402_5%

1 2

8111C@

1 2

R204 2.49K_0402_1%

ISOLATEB

R571 0_0402_5%

1 2

8102E@

RP17

75_1206_8P4R_5%

JLAN1

13

Yellow LED-

12

Yellow LED+

8

PR4-

7

PR4+

6

PR2-

5

PR3-

4

PR3+

3

PR2+

2

PR1-

1

PR1+

11

Green LED-

9

Orange LED-

10

Green-Orange LED+

C-1775553

CONN@

RSET

LAN_XTAL1
LAN_XTAL2

18
27
36
45

U15

29

HSOP

30

HSON

23

HSIP

24

HSIN

33

CLKREQB

26

REFCLK_P

27

REFCLK_N

20

PERSTB

1

SROUT12

5

FB12

62

ENSR

64

RSET

19

LANWAKEB

36

ISOLATEB

60

CKTAL1

61

CKTAL2

65

EXPOSE_PAD

25

EGND

31

EGND

15

NC

17

NC

18

NC

34

NC

35

NC

39

NC

40

NC

41

NC

42

NC

RTL8111C-GR_QFN64_9X9

8102E@

10/100: RTL8102E (SA00001YY00)

C356

GIGALAN: RTL8111C (SA00001WM00)

1000P_1206_2KV7K

12

GND
GND

EEDO

EEDI/AUX

EESK
EECS

LED3
LED2
LED1
LED0

MDIP0
MDIN0
MDIP1
MDIN1
MDIP2
MDIN2
MDIP3
MDIN3

DVDD12
DVDD12
DVDD12
DVDD12
DVDD12
DVDD12

EVDD12
EVDD12

VDD33
VDD33
VDD33
VDD33

VDDSR

AVDD33
AVDD33

AVDD12
AVDD12
AVDD12
AVDD12

IGPIO

OGPIO

15
14

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

LAN_EEDO

45

LAN_EEDI

47

LAN_EECLK

48

LAN_EECS

44

LAN_LED3

54

LAN_LED2

55

LAN_LED1

56

LAN_LED0

57

MDIP0

3

MDIN0

4

MDIP1

6

MDIN1

7

MDIP2

9

MDIN2

10

MDIP3

12

MDIN3

13

21
32
38
43
49
52

22
28

16
37
46
53

+LAN_VDDSR

63

+LAN_AVDD33

2
59

8
11
14
58

50
51

SSM3K7002FU_SC70-3

3

R209

+LAN_EVDD12

3.6K_0402_5%

1 2

U16

4

DO

3

DI

2

SK

1

CS

AT93C46-10SU-2.7 SO 8P

@

+LAN_DVDD12

+LAN_IO

GND

NC
NC

VCC

C30 0.1U_0402_16V7K~N
C33 0.1U_0402_16V7K~N

40mil

+LAN_AVDD12

Q38

2008/1/3 2009/01/3

C28 0.1U_0402_16V7K~N
C16 0.1U_0402_16V7K~N

+LAN_DVDD12

C382

1U_0603_10V6K

B+_BIAS

R213

470K_0402_5%

1 2
13

D

2

G

S

+LAN_IO

5

R212

6

1 2

0_0402_5%

7

@

8

+LAN_DVDD12

1

1

C6830.1U_0402_16V7K~N

C6840.1U_0402_16V7K~N

2

2

L31

FBML10160808121LMT_0603

1 2
1 2

L2

FBML10160808121LMT_0603

1 2
1 2

+3VALW

D

6
2

1

1

2

EN_WOL

EN_WOL# 25

Compal Secret Data

Deciphered Date

1

0.1U_0402_16V7K~N@

2

1

C210.1U_0402_16V7K~N

2

12

12

Q36

FBMA-L11-322513-201LMA40T_1210

S

45

SI3456BDV-T1-E3_TSOP6

G

3

R516

@

1.5M_0402_5%

1 2

2

C38

+LAN_IO

R567

1

C290.1U_0402_16V7K~N

2

C270.1U_0402_16V7K~N

C390.1U_0402_16V7K~N

2

C3800.1U_0402_16V7K~N

2

2

1

1

1

1 2

1

0_0805_5%

C310.1U_0402_16V7K~N

8111C@

2

close to RTL8111C each DVDD12/AVDD12 pin

+LAN_IO

+LAN_AVDD12

+LAN_IO

C371

12

R569
0_0805_5%

8111C@

+LAN_VDDSR

1

C364

2

22U_0805_6.3V6M

close to RTL8111C pin63

L34

1 2

2

1

@

C608

C381

2

22U_0805_6.3V6M

Title

Size Document Number Rev

Custom

Date: Sheet

+LAN_IO

1

C377

2

22U_0805_6.3V6M

+LAN_AVDD12

1

1

C350.1U_0402_16V7K~N

C260.1U_0402_16V7K~N

2

2

40mil

R570

1 2

1

0_0805_5%

8102E@

2

0.1U_0402_16V7K~N

60mil

1

1

C37

C34

2

2

0.1U_0402_16V7K~N

0.1U_0402_16V7K~N

Realtek RTL8111C/RJ45
LA-4191P

1

1

1

C320.1U_0402_16V7K~N

C360.1U_0402_16V7K~N

2

2

+LAN_DVDD12

1

1

C22

2

2

0.1U_0402_16V7K~N

0.1U_0402_16V7K~N

1 2

C357 0.1U_0402_16V7K~N

1 2

C355 0.1U_0402_16V7K~N

1 2

C354 0.1U_0402_16V7K~N

1 2

C358 0.1U_0402_16V7K~N

of

1

21 39Monday, January 14, 2008

0.3

A

B

C

D

E

F

G

H

U4

14
15
16
17
23
24
18
20
19
21
22
12

11
10

5
2

3
13
34

47
48

4

7

+VDDA+5VS

+AVDD_AC97

38

AVDD125AVDD2
NC
NC
MIC2_L
MIC2_R
LINE1_L
LINE1_R
CD_L
CD_R
CD_GND
MIC1_L
MIC1_R
PCBEEP

RESET#
SYNC
SDATA_OUT
GPIO0

GPIO3
SENSE A
SENSE B

EAPD
SPDIFO
DVSS1

DVSS2

1

1

2

2

C167 4.7U_0805_10V4Z~N

C168 0.1U_0402_16V7K~N

20mil

1

LINE_OUT_L

LINE_OUT_R

HP_OUT_L

HP_OUT_R

DMIC_CLK

BIT_CLK

SDATA_IN

MONO_OUT

LINE1_VREFO

GPIO1

MIC1_VREFO_L

MIC1_VREFO_R

MIC2_VREFO

JDREF

AVSS1
AVSS2

ALC268-GR_LQFP48

DVDD

VREF

9

DVDD_IO

NC

NC
NC

NC

0.1U_0402_16V7K~N

1

C485

2

0.1U_0402_16V7K~N

LINEL

35

LINER

36

HP_LOUT

39

HP_ROUT

41
45

DMIC_CLK_CODEC

46
43
44

10_0402_5% @

6

SDIN_CODEC

8
37
29
31
28

10mil

32

10mil

30
27

10mil

40
33
26

42

For EMI

0_0603_5%

1 2

R97

1

1

C491

2

C483 1000P_0402_50V7K~N
C482 1000P_0402_50V7K~N

C495 1000P_0402_50V7K~N

C496 1000P_0402_50V7K~N

R90

R80

1 2

33_0402_5%

+MIC1_VREFO_L
+MIC1_VREFO_R

12

C497
10U_0805_6.3V6M

2

0_0402_5%

C218

1 2

12

AC97_VREF

R309
20K_0402_1%

R698

+3VS

R355

+3VS

PLUG_IN23

1 2

R86 22K_0603_1%

1 2

R87 22K_0603_1%

1 2

R93 0_0603_5%

1 2

R94 0_0603_5%

12

DMIC_CLK 27

10P_0402_25V8K@

HD_BITCLK 16

HD_SDIN3 16

1

C484
10U_0805_6.3V6M

2

AMP_LEFT 23

AMP_RIGHT 23
HP_LEFT 23
HP_RIGHT 23

PLUG_IN

R354

1 2

100K_0402_5%

2

G

1 2

100K_0402_5%

PLUG_IN#

13

D

S

Q45
SSM3K7002FU_SC70-3

2

G

PLUG_IN# 23

HP_JD

13

D

Q46
SSM3K7002FU_SC70-3

S

Reserved for TEST

1 2

R374 0_0805_5%

1 2

R240 0_0805_5%

1 2

R373 0_0805_5%

1 2

R258 0_0805_5%

GND AGND

U23

VIN3VOUT

1

EN

2

C156

C155

1 1

4.7U_0805_10V4Z~N

+5VS

1 2

R67 10K_0402_5%

0.1U_0402_16V7K~N

GND

RT9198-4GPBG_SOT23-5

4

5

NC

HD Audio Codec

2 2

3 3

HD_RST#16
HD_SYNC16
HD_SDOUT16

DMIC_DATA27

4 4

MIC123
MIC223

+VDDA

@

10P_0402_25V8K

C478

2

1

10P_0402_25V8K

L40

1 2

FBM-L11-160808-800LMT_0603

1 2

MONO_IN23

HD_RST#

2

C479

1

@

C184

10U_0805_10V4Z~N

R711

R_MIC1

1 2

1K_0402_5%

R_MIC2

R712

1K_0402_5%

0_0402_5%

MIC_JD23

2

C486

1

@

10P_0402_25V8K

R699

0.1U_0402_16V7K~N

1

C185

2

1 2

C477 2.2U_0603_10V6K

1 2

C476 2.2U_0603_10V6K

DMIC_DATA_CODEC

12

39.2K _0402_1%

HP_JD

R301
R300

EAPD23

40mil

1

1

C490

2

2

0.1U_0402_16V7K~N

C_MIC1
C_MIC2

12
12

20K_0402_1%

EAPD

R96

12

0_0402_5%

DGND AGND

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

C

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

D

2008/1/3 2009/01/3

E

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

F

Date: Sheet

Compal Electronics, Inc.

Codec ALC268

LA-4191P

G

0.3

of

22 39Monday, January 14, 2008

H

A

W=40mil

1

1

2

12

2

R251
1K_0402_5%

C453
10U_0805_10V4Z~N

7

RIN+

17

RIN-

9

LIN+

5

LIN-

19

SHUTDOWN

GND

21

D15

2 1

RB751V_SOD323

@

15

16

VDD

PVDD1

GND41GND311GND213GND1

20

C137

0.1U_0402_16V7K~N

4 4

AMP_RIGHT22

AMP_LEFT22

3 3

EC_MUTE25

EC_MUTE

C451

0.47U_0603_16V7K

C443

0.47U_0603_16V7K

C452

0.47U_0603_16V7K

C442

0.47U_0603_16V7K

R605

12

10K_0402_5%

+3VS

12

R245
100K_0402_5%@

13

D

2

G

S

EAPD22

1 2

AMP_R

1 2

1 2

AMP_L

1 2

Q43
SSM3K7002FU_SC70-3

@

EAPD

Buzzer need to support ICH/PCM_SPK/Battery_low and WL_on/off

2 2

EC Beep

ICH Beep

1 1

BEEP#25

SB_SPKR16

A

R365

1 2

47K_0402_5%

R361

1 2

47K_0402_5%

C301

1 2

1U_0603_10V4Z

C305

1 2

1U_0603_10V4Z

B

6

U2

PVDD2

2

GAIN0

3

GAIN1

18

ROUT+

14

ROUT-

4

LOUT+

8

LOUT-

12

NC

10

BYPASS

P3017THF TSSOP 20P

R246

1 2

2.7K_0402_5%

@

R364

1 2

560_0402_5%

R362

1 2

560_0402_5%

10K_0402_5%

12

R367

B

PLUG_IN

+VDDA

2

B

+5VS

+5VS

2

1

12

R366
10K_0402_5%

12

R363
10K_0402_5%

1

C

Q21

E

2SC2411K_SC59

3

D20
RB751V_SOD323

2 1

R49 10K_0402_5%

1 2

R39 10K_0402_5%@

1 2

C143
1U_0603_10V6K

C300

1 2

1U_0603_10V4Z

C308

1 2

1U_0603_10V4Z

1 2

SPK_R1

SPK_R2

SPK_L1

SPK_L2

R376

2.4K_0402_5%

R244 10K_0402_5%

1 2

R250 10K_0402_5%@

1 2

1 2

R43 0_0603_5%

1 2

R42 0_0603_5%

1 2

R40 0_0603_5%

1 2

R41 0_0603_5%

INTSPK_R1

INTSPK_R2

INTSPK_L1

INTSPK_L2

GAIN0 GAIN1 GAIN

00

0

*

1

0

1

1

MONO_IN

MONO_IN 22

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

Speaker Connector

D

INTSPK_R1
INTSPK_R2
INTSPK_L1

INTSPK_L2

PACDN042_SOT23-3~D

D27

JSPK1

4

6

4

G2

3

5

3

G1

2

2

1

2

3

@

1

2

3

D28

@

1

1

ACES_88266-04001~N

CONN@

PACDN042_SOT23-3~D

E

MICROPHONE IN JACK

FOX_JA6333L-B3S0-7F~N

5
4
3

6 7
2
1

JMIC1

CONN@

10
9
8

MIC222
MIC122

PACDN042_SOT23-3~D

MIC-2
MIC-1

D29

3K_0402_5%

@

R663K_0402_5%
R59

1 2

L8 CHB2012U170_0805

1 2

L6 CHB2012U170_0805

220P_0402_50V7K

2

3

1

12
12

+MIC1_VREFO_R
+MIC1_VREFO_L

MIC-2
MIC-1

C465

MIC_JD22

1

1

C466

2

2

220P_0402_50V7K

HEADPHONE OUT JACK

FOX_JA6333L-B3S0-7F~N

HP_OUTR
HP_OUTL

R91
R89

1 2

47_0402_5%

1 2

47_0402_5%

PLUG_IN22

6dB

10dB

15.6dB

PACDN042_SOT23-3~D

HPR
HPL

21.6dB1

PLUG_IN#22

HP_RIGHT22

HP_LEFT22

2008/1/3 2009/01/3

C

Compal Secret Data

Deciphered Date

1K_0402_5%@

2

3

D30

@

1

EAPD

EC_MUTE

PLUG_IN

HP_R

1 2

L42 CHB2012U170_0805

HP_L

1 2

L41 CHB2012U170_0805

12

12

R92

R88

C524 2.2U_0603_10V6K
C523 2.2U_0603_10V6K

D

1K_0402_5%@

+3VS

5

U31

2

P

B

Y

1

A

G

NC7SZ08P5X_NL_SC70-5

3

R606 0_0402_5%

HP_INR HPINR

1 2

HP_INL HPINL

1 2

4

@

12

HPR
HPL

2

C489

470P_0402_50V7K

HP_MUTE#

HP_MUTE#

R353

1 2

6.8K_0402_5%
R352

1 2

6.8K_0402_5%

1

2

C552
1U_0603_10V6K

1

0_0603_5%

U30

14

SHDNR#

18

SHDNL#

15

INR

13

INL

1

C1P

3

C1N

Title

Size Document Number Rev

LA-4191P

Date: Sheet

5
4
3

6 7
2
1

2

C494
470P_0402_50V7K

1

+3VS

Reserve the 0 ohm resistor.

12

for voltage filtering

R371

C544 1U_0603_10V6K

10

19

SVDD

PVDD

PGND

PVss

SVss

2

5

7

1

C551
1U_0603_10V6K

2

JHP1

CONN@

1 2

11

OUTR

9

OUTL

4

NC-4

6

NC-6

8

NC-8

12

NC-12

16

NC-16

20

NC-20

SGND

TPA4411MRTJR_QFN20~N

17

HP_OUTR
HP_OUTL

Compal Electronics, Inc.

AMP/Audio Jack

E

23 39Monday, January 14, 2008

10
9
8

0.3

of

A

B

C

D

E

+1.5VS +3VALW

2

C331

0.1U_0402_16V7K~N

1

1 1

1

C338
10U_0805_10V4Z~N

2

2

C596

0.1U_0402_16V7K~N

1

2

C330

0.1U_0402_16V7K~N

1

2

C593

0.1U_0402_16V7K~N

1

1

C329
10U_0805_10V4Z~N

2

1

C328
10U_0805_10V4Z~N

2

+3VS

2

C594

0.1U_0402_16V7K~N

1

Placement Closed to JMINI2

2

C595

0.1U_0402_16V7K~N

1

Mini-Express Card (WLAN)

+3VALW

+1.5VS

JMINI2

1

CH_DATA27

CH_CLK27

CLKREQA#13

CLK_PCIE_WCARD#13

CLK_PCIE_WCARD13

PCI_RST#15,20

CLK_PCI_SIO_DB15

PCIE_WLAN_C_RX_N110
PCIE_WLAN_C_RX_P110

2 2

PCIE_WLAN_C_TX_N110

PCIE_WLAN_C_TX_P110

CH_DATA
CH_CLK

PCI_RST#
CLK_PCI_SIO_DB

R458 0_0402_5%
R457 0_0402_5%

1 2
1 2

R565 0_0402_5%@

1 2

R566 0_0402_5%@

1 2

R467 0_0402_5%@

1 2

R460 0_0402_5%

1 2

R459 0_0402_5%

1 2

PCIE_C_RXN2
PCIE_C_RXP2

1

3

3

5

5

7

7

9

9

11

11

13

13

15

15

17

17

19

19

21

21

23

23

25

25

27

27

29

29

31

31

33

33

35

35

37

37

39

39

41

41

43

43

45

45

47

47

49

49

51

51

53

GND1

FOX_AS0B226-S52N-7F~N

CONN@

GND2

2

2

4

4

6

6

8

8

10

10

12

12

14

14

16

16

18

18

20

20

22

22

24

24

26

26

28

28

30

30

32

32

34

34

36

36

38

38

40

40

42

42

44

44

46

46

48

48

50

50

52

52

54

+3VS

R4420_0402_5%

1 2

R4410_0402_5%

1 2

R4400_0402_5%

1 2

R4390_0402_5%

1 2

R4380_0402_5%

1 2

R7130_0402_5%

1 2

NB_RST#

WLAN_LED#

LPC_FRAME#
LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0

NB_RST# 11,15,19,21,25,26

USB20P8- 16
USB20P8+ 16

WLAN_LED# 28

LPC_FRAME# 15,25

LPC_AD[0..3] 15,25
WL_DISABLE# 25

Wireless_BTN

Killer switch

+3VS

3 3

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2008/1/3 2009/01/3

Compal Secret Data

Deciphered Date

12

R455
100K_0402_5%

R454

@

1.5M_0402_5%

1 2

D

SW2

1BS003-1211L_3P

11223

3

W_DISABLE#

W_DISABLE# 16,25

Title

Size Document Number Rev

Custom

Date: Sheet

MINICARD
LA-4191P

E

of

24 39Monday, January 14, 2008

0.3

5

L43

MBK1608800YZF 0603

CLK_PCI_EC

12

R113
10_0402_5%@

1

C247
15P_0402_50V8D@

2

PCIE_WAKE#16,20,21,26

LID_SW#

EC_SMB_DA1
EC_SMB_CK1

MIC_DIAG
ESB_CLK
ESB_DAT

EC_SMB_DA2
EC_SMB_CK2

1 2

1 2

L21 MBK1608800YZF 0603

3

2

C5110.1U_0402_16V7K~N

1

+3VALW

R108

1 2

0_0402_5%

U1
APX9132ATI-TRL_SOT23-3

VDD

VOUT

GND

1

REED Switch

NB_RST#

1 2

TP_DATA
TP_CLK

2

1

R119 10K_0402_5%

1 2

R118 10K_0402_5%

1 2

R343 4.7K_0402_5%
R342 4.7K_0402_5%

R619 10K_0402_5%

1 2

R615 4.7K_0402_5%

1 2

R616 4.7K_0402_5%

1 2

R110 4.7K_0402_5%
R107 4.7K_0402_5%

C246
1000P_0402_50V7K~N

@

5

ECAGND

0.1U_0402_16V7K~N

+3VALW

2

R348

100K_0402_5%@

12
12

12
12

+EC_AVCC

1

C228
1000P_0402_50V7K~N

2

R334

1 2

47K_0402_5%

C509

EC_PME#

LID_SW#

EC_MUTE

MSEN#

+5VS

+5VALW

+3VS

+3VALW

EC_RST#

2

1

R112 10K_0402_5%

1 2

R344 10K_0402_5%@

1 2

R111 10K_0402_5%

1 2

R338 10K_0402_5%

1 2

C265

15P_0402_50V8J

R141

1 2

0_0805_5%

LPC_AD[0..3]15,24

KSI[0..7]26

+3VALW

KSO[0..15]26

WL_DISABLE#24
BT_DISABLE#27

EC_SMB_CK136
EC_SMB_DA136
EC_SMB_CK26,28
EC_SMB_DA26,28

SLP_S3#16
SLP_S5#16

EC_SMI#16

ESB_CLK28

ESB_DAT28

FAN_SPEED14

NUMLED#28

1

2

Y1

32.768KHZ_1TJS125BJ4A421P

+3VALW

D D

C C

B B

A A

40mil

+3VALW_ECVCC

1

C528

2

0.1U_0402_16V7K~N

EC_GA2016

KB_RST#16

SIRQ15

CLK_PCI_EC15

NB_RST#11,15,19,21,24,26

EC_SCI#16

PM_CLKRUN#15,20

FAN_SPEED1

ON_OFF28

4

1

IN

OUT

NC3NC

2

4

0.1U_0402_16V7K~N

1

C527

2

1000P_0402_50V7K~N

LPC_FRAME#

PM_CLKRUN#

KSI[0..7]

KSO[0..15]

EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2

EC_SMI#
LID_SW#
ESB_CLK
ESB_DAT
EC_PME#

TP66

EC_TX_P80DATA
EC_RX_P80CLK

CRY2
CRY1

CRY1

CRY2

1

C264
15P_0402_50V8J

2

4

1

2

EC_GA20

KB_RST#

SIRQ
LPC_AD3

LPC_AD2
LPC_AD1
LPC_AD0

NB_RST#
EC_SCI#

0.1U_0402_16V7K~N

C529

10
12

13
37
20
38

KSI0

55

KSI1

56

KSI2

57

KSI3

58

KSI4

59

KSI5

60

KSI6

61

KSI7

62

KSO0

39

KSO1

40

KSO2

41

KSO3

42

KSO4

43

KSO5

44

KSO6

45

KSO7

46

KSO8

47

KSO9

48

KSO10

49

KSO11

50

KSO12

51

KSO13

52

KSO14

53

KSO15

54
81
82

77
78
79
80

14
15
16
17
18
19
25
28
29
30
31
32
34
36

122
123

1
2
3
4
5
7
8

6

1

2

U5

GA20/GPIO00
KBRST#/GPIO01
SERIRQ#
LFRAME#
LAD3
LAD2
LAD1
LAD0

PCICLK
PCIRST#/GPIO05
ECRST#
SCI#/GPIO0E
CLKRUN#/GPIO1D

KSI0/GPIO30
KSI1/GPIO31
KSI2/GPIO32
KSI3/GPIO33
KSI4/GPIO34
KSI5/GPIO35
KSI6/GPIO36
KSI7/GPIO37
KSO0/GPIO20
KSO1/GPIO21
KSO2/GPIO22
KSO3/GPIO23
KSO4/GPIO24
KSO5/GPIO25
KSO6/GPIO26
KSO7/GPIO27
KSO8/GPIO28
KSO9/GPIO29
KSO10/GPIO2A
KSO11/GPIO2B
KSO12/GPIO2C
KSO13/GPIO2D
KSO14/GPIO2E
KSO15/GPIO2F
KSO16/GPIO48
KSO17/GPIO49

SCL1/GPIO44
SDA1/GPIO45
SCL2/GPIO46
SDA2/GPIO47

PM_SLP_S3#/GPIO04
PM_SLP_S5#/GPIO07
EC_SMI#/GPIO08
LID_SW#/GPIO0A
SUSP#/GPIO0B
PBTN_OUT#/GPIO0C
EC_PME#/GPIO0D
EC_THERM#/GPIO11
FAN_SPEED1/FANFB1/GPIO14
FANFB2/GPIO15
EC_TX/GPIO16
EC_RX/GPIO17
ON_OFF/GPIO18
PWR_LED#/GPIO19
NUMLED#/GPIO1A

XCLK1
XCLK0

C516

LPC & MISC

2

Int. K/B
Matrix

C510

SM Bus

1000P_0402_50V7K~N

1

3

+EC_AVCC

9

22

33

96

111

125

67

VCC

VCC

VCC

VCC

VCC

VCC

AVCC

INVT_PWM/PWM1/GPIO0F

BEEP#/PWM2/GPIO10

FANPWM1/GPIO12

ACOFF/FANPWM2/GPIO13

PWM Output

BATT_TEMP/AD0/GPIO38

BATT_OVP/AD1/GPIO39

ADP_I/AD2/GPIO3A

AD Input

SELIO2#/AD5/GPIO43

DAC_BRIG/DA0/GPIO3C

EN_DFAN1/DA1/GPIO3D

DA Output

PS2 Interface

SPI Device Interface

SPI Flash ROM

GPIO

GPIO

GND

GND

GND

11

24

35

94

IREF/DA2/GPIO3E

TP_CLK/PSCLK3/GPIO4E

TP_DATA/PSDAT3/GPIO4F

SDICS#/GPXOA00
SDICLK/GPXOA01

CIR_RLC_TX/GPIO41

FSTCHG/SELIO#/GPIO50

BATT_CHGI_LED#/GPIO52

CAPS_LED#/GPIO53

BATT_LOW_LED#/GPIO54

SUSP_LED#/GPIO55

VR_ON/XCLK32K/GPIO57

EC_RSMRST#/GPXO03
EC_LID_OUT#/GPXO04

EC_SWI#/GPXO06

ICH_PWROK/GPXO06

GPO

WL_OFF#/GPXO09

PM_SLP_S4#/GPXID1

GPI

AGND

GND

GND

KB926QFA1_LQFP128_14X14

69

113

ECAGND

PSCLK1/GPIO4A
PSDAT1/GPIO4B
PSCLK2/GPIO4C

PSDAT2/GPIO4D

SDIDO/GPXOA02

SDIDI/GPXID0

SPICLK/GPIO58

CIR_RX/GPIO40

SYSON/GPIO56

AC_IN/GPIO59

EC_ON/GPXO05

BKOFF#/GPXO08

ENBKL/GPXID2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

AD3/GPIO3B

AD4/GPIO42

DA3/GPIO3F

SPIDI/RD#

SPIDO/WR#

SPICS#

GPXO10
GPXO11

GPXID3
GPXID4
GPXID5
GPXID6
GPXID7

V18R

21
23
26
27

C508 100P_0402_50V8K

1 2

63

BATT_OVP

64
65

AD_BID0

66

MIC_DIAG

75
76

68
70
71
72

EC_MUTE

83
84
85
86

TP_CLK

87

TP_DATA

88

2007-02-12 MUST PULL DOWN!!!

SPI_PD

97
98
99

VGATE

109

FRD#SPI_SO

119

FWR#SPI_SI

120

SPI_CLK

126

FSEL#SPICS#

128

73

MSEN#

74
89

BATT_CHG_LED#

90
91
92
93
95
121

ACIN

127

100
101
102
103

VLDT_EN

104
105
106

NB_PWRGD

107

PSID_DISABLE#

108

110

ENABLT

112
114

EC_THERM#

115
116
117

PS_ID

118
124

1

C686

C619

2

0.1U_0402_16V7K~N

2007-05-02 Support KB926 C0

+3VALW

EC_TX_P80DATA
EC_RX_P80CLK

2008/1/3 2009/01/3

INVT_PWM 14
BEEP# 23
W_DISABLE# 16,24
ACOFF 31LPC_FRAME#15,24

ECAGND

BATT_TEMP 36

BATT_OVP 36

TP59

R473 4.7K_0402_5%

ADP_I 31

MIC_DIAG 27

DAC_BRIG 14
EN_DFAN1 4
IREF 31
CHGVADJ 31

EC_MUTE 23

BIST 14
LCD_DET 14

TP_CLK 26
TP_DATA 26

1 2

EN_WOL# 21

VGATE 35

R351 15_0402_5%

12

R350 15_0402_5%

12

R130 15_0402_5%

12

R120 15_0402_5%

12

TS_RST# 28
MSEN# 14

FSTCHG 31

BATT_CHG_LED# 28
CAPSLED# 28
BATT_LOW_LED# 28
SCRLED# 28
SYSON 26,29,33
VR_ON 35
ACIN 30,31

EC_RSMRST# 16
EC_LID_OUT# 16
EC_ON 28
EC_SWI# 16

VLDT_EN 29
BKOFF# 14
LCD_VCC_TEST_EN 14
NB_PWRGD 11
PSID_DISABLE# 30

ENABLT 11,14

USB_EN 27PWR_GREEN_LED#28
EC_THERM# 17
SUSP# 26,29
PWRBTN_OUT# 16

PS_ID 30

1

ACIN

2

4.7U_0805_6.3V6K~N

JECDB1

1

1

2

2

3

3

4

4

ACES_85205-0400

CONN@

Compal Secret Data

Deciphered Date

2

BATT_OVP

100P_0402_50V8K

ECAGND

EC_SI_SPI_SO
EC_SO_SPI_SI
SPI_CLK_R
SPI_CS#

0.1U_0402_16V7K~N

C620

100P_0402_50V8K

2

R358

NB_PWRGD

0_0402_5%

1 2

RS690M & SB600 PowerGD

+3VALW

12

R100

Ra

Rb

100K_0402_5%

R337

8.2K_0402_5%

1 2

C488

20mil

0.1U_0402_16V7K~N

1 2

@

U26

8

VCC

7

WP

6

SCL

5

SDA

AT24C16AN-10SU-2-7 SO 8P @

C691

1

2

+5VALW

EC_SMB_CK1
EC_SMB_DA1

SPI Flash (8Mb*1)

C221

1 2

10K_0402_5%

+3VALW

20mils

R99

1 2

SPI_CS#
SPI_CLK_R
EC_SO_SPI_SI EC_SI_SPI_SO

U27

8

VCC

3

W

7

HOLD

1

S

6

C

5

D

MX25L8005M2C-15G_SO8-200mil

Title

Size Document Number Rev

Custom

Date: Sheet

1

C542

0.47U_0603_16V7K@

2

FOR Board ID

AD_BID0

1

C512

0.1U_0402_16V7K~N

2

A0
A1
A2

GND

4

VSS

2

Q

1

SB_PWRGD 6,16

12

R323

@

100K_0402_5%

1
2
3
4

12

R324

@

100K_0402_5%

Reserve for EMI, close to SPI ROM

SPI_CLK_R

12

R98

@

33_0402_5%

2

C224

@

22P_0402_50V8J

1

KB926&BIOS
LA-4191P

1

25 39Monday, January 14, 2008

0.3

of

KSO8
KSI3
KSO9
KSI2
KSI1
KSO10
KSO11
KSI0
KSO12
KSO13
KSO14
KSO15

C209 100P_0402_50V8K@
C198 100P_0402_50V8K@
C208 100P_0402_50V8K@
C199 100P_0402_50V8K@
C200 100P_0402_50V8K@
C207 100P_0402_50V8K@
C206 100P_0402_50V8K@
C201 100P_0402_50V8K@
C205 100P_0402_50V8K@
C204 100P_0402_50V8K@
C203 100P_0402_50V8K@
C202 100P_0402_50V8K@

KSI7
KSI6
KSI5
KSO0
KSO1
KSO2
KSI4
KSO3
KSO4
KSO5
KSO6
KSO7

C194 100P_0402_50V8K@
C195 100P_0402_50V8K@
C196 100P_0402_50V8K@
C217 100P_0402_50V8K@
C216 100P_0402_50V8K@
C215 100P_0402_50V8K@
C197 100P_0402_50V8K@
C214 100P_0402_50V8K@
C213 100P_0402_50V8K@
C212 100P_0402_50V8K@
C211 100P_0402_50V8K@
C210 100P_0402_50V8K@

TouchPad

KSI[0..7]
KSO[0..15]

TP/B TO M/B

INT_KBD CONN.

KSI[0..7] 25
KSO[0..15] 25

JKB1

KSI0

1

1

KSI1

2

2

KSI2

3

3

KSI3

4

4

KSI4

5

5

KSI5

6

6

KSI6

7

7

KSI7

8

8

KSO0

9

9

KSO1

10

10

KSO2

11

11

KSO3

12

12

KSO4

13

13

KSO5

14

14

KSO6

15

15

KSO7

16

16

KSO8

17

17

KSO9

18

18

KSO10

19

19

KSO11

20

20

KSO12

21

21

KSO13

22

22

KSO14

23

23

KSO15

24

24

25

25

26

26

27

G1

28

G2

ACES_88514-2601

CONN@

2007-11-15 update to 26pin

+5VS

1

C335100P_0402_50V8K

2

+3V_CARD_AUX

TP_CLK
TP_DATA

1

@

C339

2

100P_0402_50V8K

JEXP1

1

GND

2

USB_D-

3

USB_D+

4

CPUSB#

5

RSV

6

RSV

7

SMB_CLK

8

SMB_DATA

9

+1.5V

10

+1.5V

11

WAKE#

12

+3.3VAUX

13

PERST#

14

+3.3V

15

+3.3V

16

CLKREQ#

17

CPPE#

18

REFCLK-

19

REFCLK+

20

GND

21

PERn0

22

PERp0

23

GND

24

PETn0

25

PETp0

26

GND

27

GND

28

GND

29

GND
GND30GND

FOX_1CX41202-KH_26P

CONN@

1

TP_CLK25

C334

0.01U_0402_16V7K

USB20P6-16
USB20P6+16

SMB_CK_CLK18,9,13,16
SMB_CK_DAT18,9,13,16

PCIE_WAKE#16,20,21,25

CLKREQB#13

NC_PWR_EN#16

CLK_PCIE_CARD#13

CLK_PCIE_CARD13

PCIE_CARD_C_RX_N111
PCIE_CARD_C_RX_P111

PCIE_CARD_C_TX_N111
PCIE_CARD_C_TX_P111

NC_PWR_EN#

PCIE_CARD_C_RX_N1
PCIE_CARD_C_RX_P1

PCIE_CARD_C_TX_N1
PCIE_CARD_C_TX_P1

R114 0_0402_5%
R115 0_0402_5%

NC_CPUSB#

R121 0_0402_5%
R122 0_0402_5%

R133 0_0402_5%

1 2

PCIE_PERST#

R143 0_0402_5%

1 2

R510 0_0402_5%

1 2

TP_DATA25

2

12
12

12
12

@

+3V_CARD +1.5V_CARD

USB20P6-_R
USB20P6+_R

NC_CPPE#

GND

6

G2

5

G1

4

4

3

3

2

2

1

1

JTP1
ACES_88514-0441_4P

CONN@

+3VALW

31
32

C2970.1U_0402_16V7K~N

NB_RST#11,15,19,21,24,25

SYSON25,29,33
SUSP#25,29

R134 100K_0402_5%@

1 2

R135 100K_0402_5%@

1 2

+1.5V_CARD

+3VALW

1

1

C2830.1U_0402_16V7K~N

2

2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

NB_RST#

NC_PWR_EN#
NC_CPUSB#

+1.5VS+3VS

1

C2790.1U_0402_16V7K~N

2

U7

12

1.5Vin

14

1.5Vin

2

3.3Vin

4

3.3Vin
AUX_IN17AUX_OUT

6

SYSRST#

20

SHDN#

1

STBY#

10

CPPE#

9

CPUSB#

18

RCLKEN

P2231NF_QFN20

2008/1/3 2009/01/3

11

1.5Vout

13

1.5Vout

3

3.3Vout

5

3.3Vout

15
19

OC#

8

PERST#

16

NC

7

GND

Compal Secret Data

1A 1.5A

1

1

C2670.1U_0402_16V7K~N

C2780.1U_0402_16V7K~N

2

2

PCIE_PERST#

Deciphered Date

+3V_CARD

1

C26610U_0805_6.3V6M

2

C2800.1U_0402_16V7K~N

1

C268

2

10U_0805_6.3V6M

+3V_CARD_AUX

1

C2960.1U_0402_16V7K~N

2

1

1

C2810.1U_0402_16V7K~N

C2820.1U_0402_16V7K~N

2

2

0.5A

1

2

Title

Size Document Number Rev

Custom

Date: Sheet

KB / TP / Express Card
LA-4191P

26 39Monday, January 14, 2008

0.3

of

A

B

C

D

E

+USB_AS

CON-USBP0-

CON-USBP0+

4

CH4

1

+USB_AS

CON-USBP1-

CON-USBP1+

CM1293-04SO_SOT23-6

USB20P2-

USB20P2+

USB20P3-

USB20P3+

JUSB1

1

VCC

2

USB_N

3

USB_P

4

GND

5

GND

6

GND

7

GND

8

GND

TYCO 0-1775501-1 4P

CONN@

JUSB4

1

VCC

2

USB_N

3

USB_P

4

GND

5

GND

6

GND

7

GND

8

GND

TYCO 0-1775501-1 4P

CONN@

6

CH3

D42

CH23Vn2CH1

+USB_BS

5

4

Vp

CH4

1

8
7
6
5

8
7
6
5

+USB_AS

+USB_BS

+5VS

W=80mils

OVCUR#0 16

SSM3K7002FU_SC70-3

W=80mils

OVCUR#3 16

SSM3K7002FU_SC70-3

1

C343
10U_0805_10V4Z~N

2

+USB_AS

USB20P0-16

USB20P0+16

470P_0402_50V7K

USB20P1-16

USB20P1+16

USB20P7+16
USB20P7-16

CH_CLK24

CH_DATA24

+3VS

BT_LED#28

C349

+3VS

@

1

+

2

12

R715
10K_0402_5%

TP65

150U_D2_6.3VM

C9

BT_ACTIVE

1

2

C8

470P_0402_50V7K

1

2

Bluetooth

12

R4
470_0805_5%

@

DISCHG_USBAS

13

D

S

12

R217
470_0805_5%

@

DISCHG_USBBS

13

G

USB_EN#

2

G

USB_EN#

2

BT_DISABLE#25

Q1

@

D

Q39

S

@

USB20P0-

USB20P0+

2007-11-14 swap TPA<->TPB

JBT1

1
2
3
4
5
6
7
8
9

10
11
12

ACES_88460-1001

CONN@

USB20P1-

USB20P1+

1
2
3
4
5
6
7
8
9
10
GND
GND

3

2

2

3

IEEE1394_TPBN020
IEEE1394_TPBP020
IEEE1394_TPAN020
IEEE1394_TPAP020

USB20P2+16
USB20P2-16

USB20P3+16
USB20P3-16

L1

3

2

WCM-2012-670T_4P

CM1293-04SO_SOT23-6

WCM-2012-670T_4P

2

3

L60

4

4

1

1

D2

1

1

4

4

+USB_BS

IEEE1394_TPBN0
IEEE1394_TPBP0
IEEE1394_TPAN0
IEEE1394_TPAP0

USB20P2+
USB20P2-

USB20P3+
USB20P3-

6

CH3

CH23Vn2CH1

W=80mils

5

Vp

JUSB3

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

11

11

12

12

13

GND1

14

GND2

ACES_87213-1200G

CONN@

+5VALW

1 1

USB_EN25

2 2

USB_EN

2

G

+5VALW

1

0.1U_0402_16V7K~N

2

R194
10K_0402_5%

1 2

USB_EN#

13

D

Q2
SSM3K7002FU_SC70-3

S

+5VALW

1

C384

0.1U_0402_16V7K~N

2

C350

USB_EN#

U12

1

GND

2

IN

3

IN

4

EN#

RT9711PS_SO8

U18

1

GND

2

IN

3

IN

4

EN#

RT9711PS_SO8

OUT
OUT
OUT
OC#

OUT
OUT
OUT
OC#

Felica Conn

+5VS

3 3

USB20P4-16

USB20P4+16

R461 0_0402_5%

1 2

R462 0_0402_5%

1 2

TP24

1A

USBP4_R­USBP4_R+

LEC

JFE1

1

1

2

2

3

3

4

4

5

8

5

G2

7

66G1

ACES_88512-0641_6P

CONN@

UPEK

USB20P5+16
USB20P5-16

4 4

A

USB20P5+
USB20P5-

USB20P5+

+3VS

Finger Print

JFP1

1

1

2

2

3

3

4

4

5

5

G2

66G1

ACES_88512-0641_6P

CONN@

D33

1
2

GND

IO2

IO1

VIN

PJLCR05 SOT143

@

3
4

8
7

B

USB20P5-

+3VS

10-17 SWAP!!

USB20P9-

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2008/1/3 2009/01/3

D32

1

GND

IO2

2

IO1

VIN

PRTR5V0U2X_SOT143-4

@

DMIC_CLK
DMIC_DATA

Compal Secret Data

Deciphered Date

C694

USB20P9+

3
4

+5VS

C695

100P_0402_50V8K

100P_0402_50V8K

D

USB20P9+16
USB20P9-16

DMIC_DATA22

DMIC_CLK22
MIC_DIAG25

Title

Size Document Number Rev

Date: Sheet

USB20P9+
USB20P9-

+5VS
+3VS

Compal Electronics, Inc.

Monday, January 14, 2008

DMIC_DATA
DMIC_CLK

MIC_DIAG

USB Port

LA-4191P

Camera Conn

JCA1

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

11

GND

12

GND

ACES_88460-1001

CONN@

E

of

27 39

0.3

A

B

C

D

E

H7

H_3P0

1 1

H_3P2

H_3P7

H_4P2

2 2

H_1P5X1P0

H_3P1N

3 3

HOLEA@

1

H17
HOLEA@

1

H25
HOLEA@

1

H3
HOLEA@

1

H1
HOLEA@

1

H19
HOLEA@

1

H9

H8
HOLEA@

1

H5

H4

HOLEA@

HOLEA@

1

H2
HOLEA@

1

H10

HOLEA@

HOLEA@

1

1

H6
HOLEA@

1

1

H29

H14

HOLEA@

HOLEA@

1

1

H12

H11
HOLEA@

1

H27
HOLEA@

1

H26

HOLEA@

HOLEA@

1

1

H28
HOLEA@

1

H15
HOLEA@

1

FD3
FIDUCAL

@

1

Power Button

PWR_ON-OFF_BTN#

H30
HOLEA@

1

EC_ON25

EC_ON

10K_0402_5%

SATA_LED#17

ODD_ACT_LED#19

R132

12

SATA_LED#
ODD_ACT_LED#

PCB

PCB1

H16
HOLEA@

1

FD2
FIDUCAL

@

1

D6

1

DAN202U_SC70

2

G

2
1

H20

H21

HOLEA@

HOLEA@

1

1

FD1
FIDUCAL

@

1

+3VALW

R142
100K_0402_5%

1 2

2

51ON#

3

13

D

Q20
SSM3K7002FU_SC70-3

S

+5VS

5

U17

P

B

4

Y

A

G

NC7SZ08P5X_NL_SC70-5

3

FD4
FIDUCAL

@

1

2

C276
1000P_0402_50V7K~N

1

2

C383

0.1U_0402_16V7K~N

1

IDE_ACT_LED#

H18
HOLEA@

1

ON_OFF 25
51ON# 30

H22
HOLEA@

1

12

D5
RLZ20A_LL34

PWR_ON-OFF_BTN#

PACDN042_SOT23-3~D

Close to JFN1. Reserved for EMI

Regulator for ENE sensor

+5VS

1

2

FOR ENE

R559 MBK1005801YZF_0402

ESB_CLK25

ESB_DAT25

EC_SMB_CK26,25
EC_SMB_DA26,25

2

3

D31

@

1

1 2

R560 MBK1005801YZF_0402

1 2

FOR CYPRESS

R562 0_0402_5%@

1 2

R561 0_0402_5%@

1 2

L62

1 2

+3VS

FBML10160808121LMT_0603

@

BATT_LOW_LED#25
BATT_CHG_LED#25

PWR_GREEN_LED#25

1 2

C701
1U_0402_6.3V6K

+3VS_FUN

1

C700

2.2U_0603_10V6K

2

BATT_LOW_LED#
BATT_CHG_LED#

R714

10K_0402_5%

APL5151-33BC-TRL_SOT23

SHDN#3BP

2

GND

1

VIN

U691

SCRLED#25
CAPSLED#25
NUMLED#25
TS_RST#25

BT_LED#27

WLAN_LED#24

+3VALW

R471

1 2

220_0402_5%

R696

1 2

220_0402_5%

12-22/Y2BHC-A30/2C_Y/B~D

PWR_GREEN_LED#

4

5

VOUT

SCRLED#
CAPSLED#
NUMLED#
TS_RST#
PWR_GREEN_LED#

BT_LED#
FN_CK2

FN_DA2
WLAN_LED#
PWR_ON-OFF_BTN#

IDE_ACT_LED#

BATT_CHG_LED

3
2

PWR_SUS_LED

LED1
12-21-BHC-ZL1M2RY-2C BLUE

LED2

Y

B

+3VS_FUN

2

C702

0.33U_0603_10V7K~D

1

1

12

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18

R469

1 2

220_0402_5%

JFN1

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
GND

GND

ACES_88512-1641_16P

CONN@

+5VALW

LA-4191P

FN_CK2

@

@

12

R700
33_0402_5%

2

C42
22P_0402_50V8J

1

BT_LED#

SCRLED#
CAPSLED#
NUMLED#

C302 100P_0402_50V8K@
C303 100P_0402_50V8K@

C292 100P_0402_50V8K@
C698 100P_0402_50V8K@
C699 100P_0402_50V8K@

FN_DA2TS_RST#

PWR_GREEN_LED#
WLAN_LED#

IDE_ACT_LED#
PWR_ON-OFF_BTN#

C293 100P_0402_50V8K@

C43 100P_0402_50V8K@
C44 100P_0402_50V8K@

C46 100P_0402_50V8K@
C291 100P_0402_50V8K@

Close to JFN1

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2008/1/3 2009/01/3

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

D

Date: Sheet

PWR_OK/BTN
LA-4191P

E

0.3

of

28 39Monday, January 14, 2008

A

B

C

D

E

+1.2VALW TO +1.2V_NBCORE

+5VALW

8
7
6
5

1 1

1

2

+5VS

U11

1

S

D

2

S

D

3

S

D

4

G

D

AO4468 1N SO8

C336
10U_0805_10V4Z~N

C664

0.1U_0603_25V7K~N

RUN_ON

1

2

1

C340

4.7U_0805_10V4Z~N

2

R554

1 2

10K_0402_5%

SSM3K7002FU_SC70-3

1

C341
1U_0603_10V6K

2

Q32

100K_0603_5%

1 2

13

D

S

R188

G

B+_BIAS

SUSP

2

+5VALW TO +5VS

+1.2VALW +1.2V_NBCORE

U36

8
7
6
5

1

2

1

S

D

2

S

D

3

S

D

4

G

D

AO4468 1N SO8

C606
10U_0805_10V4Z~N

1.2VS_GATE

1

C604

4.7U_0805_10V4Z~N

2

1

C605
1U_0603_10V6K

2

U9

1

S

D

2

S

D

3

S

D

4

G

D

+3VALW TO +3VS

+3VS

1

C321

4.7U_0805_10V4Z~N

2

3VS_GATE

R174

1 2

0_0402_5%

1

C320

0.1U_0603_25V7K~N

2

1

C324
1U_0603_10V6K

2

RUN_ON

+3VS

1

+

C362

2

2 2

150U_D2_6.3VM

Reserved

C366

1

+

2

1

+

C367

2

150U_D2_6.3VM

150U_D2_6.3VM

+3VALW

8
7
6
5

AO4468 1N SO8

1

C325
10U_0805_10V4Z~N

2

+1.8V TO +1.8VS

+5VALW

R189
10K_0402_5%

1 2

Q30

13

D

2

G

S

+1.2V_HT

SYSON25,26,33SUSP#25,26

12

R36
470_0805_5%

SSM3K7002FU_SC70-3

SYSON

R185

10K_0402_5%

SSM3K7002FU_SC70-3

R182

10K_0402_5%

+0.9V

12

R32
470_0805_5%

SUSP

12

SUSP20,34 SYSON#34

3 3

SYSON#

12

2

G

+5VALW

1 2

13

+1.8V

12

R186
10K_0402_5%

Q31

D

S

R33
470_0805_5%

+1.8V

+1.8VS

U24

8

D

7

D

6

D

5

D

AO4468 1N SO8

1

C480
10U_0805_10V4Z~N

2

0.1U_0603_25V7K~N

12

R72
470_0805_5%

+1.8VS

1

S

2

S

3

S

4

1.8VS_GATE

1

2

@

1

C475

4.7U_0805_6.3V6K~N

2

G

C468

R65

1 2

10K_0402_5%

1

C174
1U_0603_10V6K

2

+5VS

12

R179
470_0805_5%

+1.2VALW TO +1.2V_HT

U22

8
7
6
5

1

2

+5VS+3VS

12

R37
470_0805_5%

1

S

D

2

S

D

3

S

D

4

G

D

AO4468 1N SO8

C454
10U_0805_10V4Z~N

0.1U_0603_25V7K~N

C455

1.2VS_GATE

1

2

+1.5VS

12

+1.2V_HT+1.2VALW

1

C138

4.7U_0805_10V4Z~N

2

R61

1 2

10K_0402_5%

R181
470_0805_5%

1

C144
1U_0603_10V6K

2

RUN_ON_1.2

D

Q15

S

VLDT_EN25

R564

1 2

10K_0402_5%@
R60

100K_0603_5%

1 2

13

VLDT_EN#

2

G

SSM3K7002FU_SC70-3

VLDT_EN

10K_0402_5%

R52

+5VALW

12

B+_BIAS

2

G

+5VALW

R53
10K_0402_5%

1 2

13

D

Q14

SSM3K7002FU_SC70-3

S

DISCHG_0.9V

13

SYSON#

4 4

D

Q10

2

G

S

SSM3K7002FU_SC70-3

A

SUSP

2

G

SSM3K7002FU_SC70-3

DISCHG_1.2VHT

13

D

Q12

S

SYSON#

DISCHG_1.8V

13

D

Q11

2

G

S

SSM3K7002FU_SC70-3

B

DISCHG_1.8VS

13

D

SUSP

2

G

S

SSM3K7002FU_SC70-3

DISCHG_3VS

13

D

Q16

SSM3K7002FU_SC70-3

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Q27

2

G

S

2008/1/3 2009/01/3

C

Compal Secret Data

DISCHG_5VS

13

D

SUSPSUSP

2

G

S

SSM3K7002FU_SC70-3

Deciphered Date

DISCHG_1.5VS

13

D

SUSP

Q13

SSM3K7002FU_SC70-3

D

Q28

2

G

S

Title

Size Document Number Rev

Custom

Date: Sheet of

DC Interface
LA-4191P

E

29 39Monday, January 14, 2008

0.3

5

4

3

2

1

Vin Detector

PCN1
TYCO_1566065-2~D

9

D D

C C

BATT+

CH751H-40PT_SOD323-2

51ON#28

GND_4

8

GND_3

7

GND_2

6

GND_1

MH1

PD12

2 1

CHGRTCP

PR152

100K_0402_5%~D

PR153

22K_0402_5%

1 2

MH2

Low_PWR

DC+_1
DC+_2

DC-_1
DC-_2

CONN@

@

JUMP_43X118

12

12

PC113

0.22U_1206_25V7K

1
2
3
4
5

PJP6

2

112

PQ45
TP0610K-T1-E3_SOT23-3

2

PL18

DOCK_PSID

12

1 2

PL23

FBMA-L11-322513-151LMA50T_1210~D

VIN

PD11

RLS4148_LL34-2

1 2
12

VS

PR143
33_1206_5%~N

13

12

PC114

0.1U_0603_25V7K~D

12

12

PC134

100P_0402_50V8J~N

ADPIN

PL2

FBMA-L11-322513-151LMA50T_1210~D

1 2

12

12

PC135

1000P_0402_50V7K~N

PC15

PC14

100P_0402_50V8J~N

1000P_0402_50V7K~N

12

PC30

100P_0402_50V8J~N

VIN

12

PC31

1000P_0402_50V7K~N

Max. typ. Min.

H-->L 18.234 17.841 17.449
L-->H 17.597 17.210 16.813

2200P_0402_50V7K~D

@

VIN

12

PR71

82.5K_0402_1%~D
PR72

22K_0402_1%~D

1 2

12

12

PC40

32.3

0.1U_0402_16V7K~N

12

PC34
1000P_0402_50V7K~D

PR75

19.6K_0402_1%~D

PC37

N40N41
N35

1 2

1 2

3
2

10K_0402_5%~D

56K_0402_5%~D@

1 2

PR70
1M_0402_1%~N

VS

8

P

+

-

G

4

PR65

12

PR69

12

PC35

PU4A

0.01U_0402_25V7K~D

1

0

LM393DR_SO8~N

RTCVREF

3.3V

VIN

12

PR67
10K_0402_5%~D

12

PD17

MMPZ5229BPT_SC76

PR63
1K_0402_5%~D

1 2

12

PR64
10K_0402_5%~D

ACIN 25,31

+3VALWP+5VALWP

B B

A A

3.3V

+5VALWP

+3VALWP

+1.8VP

RTCVREF

12

PC74

PJP12
JUMP_43X118@

PJP13
JUMP_43X118@

PJP11
JUMP_43X118@

PJP8
JUMP_43X118@

PJP7
JUMP_43X118@

5

4.7U_0805_6.3V6K~N

112

112

112

112

112

PU9

G920AT24U_SOT89

3

OUT

GND

1

2

2

2

2

2

+5VALW

+3VALW

+1.8V

12

PR109
200_0805_5%~N

2

IN

12

PC72
1U_0805_25V4Z~D

+1.5VSP

+0.9VP

+1.2VALWP

PJP4

1 2

PAD-OPEN1x1m

PJP1
JUMP_43X118@

112

PJP10
JUMP_43X118@

112

PJP9
JUMP_43X118@

112

DOCK_PSID

+1.5VS

2

2

2

+0.9V

+1.2VALW

2

1

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

PR260

3

PD31
SM24_SOT23

100K_0402_1%~D

@

PR262

15K_0402_1%~D

2008/1/3 2009/01/3

1 2

1 2

FDV301N_NL_SOT23-3~D

Compal Secret Data

Deciphered Date

@

0_0402_5%~D

PQ63

2

B

1 2

1 3

PR257

D

S

G

2

C

PQ64

MMST3904-7-F_SOT323-3

E

3 1

2

PR259

33_0402_5%~D

1 2

PD29

DA204U_SOT323~D

2

3

1

+5VALWP

12

PR261

10K_0402_1%~D

PR263

1 2

10K_0402_1%~D @

Title

Size Document Number Rev

Custom

Date: Sheet

PR258

1 2

2.2K_0402_5%~D

+5VALWP

2

3

PD30

@

DA204U_SOT323~D

1

<Title>

DCIN / Precharge

LA-4191P

PS_ID 25

PSID_DISABLE# 25

1

0.3

of

30 39Monday, January 14, 2008

A

B

C

D

E

2.2_0603_5%~D

1 2

DH_CHG

LX_CHG

PD27

RLS4148_LL34-2

REGN

12

PC188
1U_0603_10V6K~D

DL_CHG

CELLS

12

1 2

PR206

10_0603_5%~D

PC197

12

12

B+

PL22

FBMA-L11-322513-151LMA50T_1210~D

1 2

PC182

0.1U_0805_25V7K

1 2

PR193

12

1 2

PC184

0.1U_0603_25V7K~D

PQ50

AO4466_SO8

ACOFF 25

PC195

0.1U_0603_25V7K~D

ICHG setting

12

PR207
100K_0402_1%~D

12

PR309
0_0402_5%~D@

VADJ

PR311
10K_0402_1%~D

CHG_B+

578

578

12

1 2

PC176

4.7U_1206_25V6K~D
PQ48
AO4466_SO8

3 6

241

3 6

241

49.9K_0402_1%~D

PC196

0.01U_0402_25V7K~D

@

PL11

10UH_SIL1045RA-100PF_4.5A_30%

1 2

12

PR312

4.7_1206_5%~D

12

PC277

680P_0603_50V8J~D

PR204

12

IREF Current

3.265V 3.3A

0.49V 0.5A

1 2

IREF 25

PC175

4.7U_1206_25V6K~D

1 2

0.01U_0402_25V7K~D

1 2

PC177

4.7U_1206_25V6K~D

PC185

10U_1206_25V6M~D

12

PC191

0.1U_0603_25V7K~D

PC173

/BATDRV

PR195

0.02_2512_1%

1
2

PC190

0.1U_0402_16V7K~N

1 2

ACGOOD#

FSTCHG25

1 2

4
3

RTCVREF

12

PR189
100K_0402_1%~D

12

PC192

0.1U_0603_25V7K~D

@

12

PR203
100K_0402_1%~D

2

G

2

G

4

3

G

5

VREF

100K_0402_1%~D

1 2

13

D

PQ53
SSM3K7002F_SC59-3

@

S

VREF

PR208
100K_0402_1%~D

1 2

CHGEN#

13

D

PQ54
SSM3K7002F_SC59-3

S

PQ49

S1S2S

FDS4435BZ_SO8

D8D7D6D

@

PR205

BATT+

12

PC186

10U_1206_25V6M~D

ACIN 25,30

PQ46

VIN

12

PR190

1 1

1_1210_5%

12

PR192

1_1210_5%

PC181

2.2U_0805_25V6K

1 2

1 2

90W adapter
Icharge=(Vsrset/Vvdac)*(0.1/PR195)=3.3A
Iadapter=(Vacset/Vvdac)*(0.1/PR188)=4.26A
Input OVP : 22.3V

2 2

Input UVP : 17.26V
Fsw : 300KHz

VREF

PR202
100K_0402_1%~D

1 2

13

D

S

GND

CELLS

VREF

CELLS

2

G

PQ52
SSM3K7002F_SC59-3

3 Cell
4 Cell

ACGOOD#

3cell/4cell# 36

FDS4435BZ_SO8

8
7
6
5

1 2

1 2

PR199
340K_0402_1%~D

1 2

OVPSET

PR200

54.9K_0402_1%

1 2

0.1U_0603_25V7K~D

PR194
340K_0402_1%~D

ACDET

PR196

54.9K_0402_1%

100K_0402_1%~D

PC174

0.01U_0603_50V7K~D

1

S

D

2

S

D

3

S

D

4

G

D

SI2301BDS-T1-E3_SOT23-3

PR201

1 2

PC194

PC178

1 2

CP setting

2

12

ACSET

Cells selector

3 3

+COINCELL

12

RTCVREF

Z4012

3

2

PD33

1

BAT54CW_SOT323~D

4 4

27.4

COIN RTC Battery

PR308
390_0402_5%~D

+COINCELL

+RTCBATT

1

PC269
1U_0603_10V4Z~D

2

Move to power schematic

+COINCELL

FDS4435BZ_SO8

1
2
3
4

12

PR191

100K_0402_1%~D

0.01U_0402_25V7K~D

56.2K_0402_1%

1 2

VREF

0.01U_0402_25V7K~D

@

PQ51

1 3

PJP16

1
2

PQ47

8

S

D

7

S

D

6

S

D

5

G

D

12

PC183

0.1U_0603_25V7K~D

PR197

12

PC187

1U_0603_10V6K~D

1
2

ACES_85204-02001

PR188

0.015_2512_1%

1
2

PC179

0.1U_0402_16V7K~N

1 2

ACSET

12

PR198
100K_0402_1%~D

1 2

0.47U_0603_16V7K~N

VREF

12

PC193

VADJ

/BATDRV

4
3

CHGEN#

12

PC180

0.1U_0603_25V7K~D

@

PC189

10

11

12

13

14

PU12

1

CHGEN

2

ACN

3

ACP

4

ACDRV

5

ACDET

6

ACSET

7

ACOP

8

OVPSET

9

AGND

VREF

VDAC

VADJ

ACGOOD

BATDRV

BQ24751ARHDR_QFN28_5X5

CHGVADJ25

IADAPT

ADP_I25

4.32K_0402_1%~D

PVCC

BTST

HIDRV

PH

REGN

LODRV

PGND

LEARN

CELLS

SRP

SRN

BAT

TP

SRSET

PR310

1 2

28

27

26

25

24

23

22

21

20

19
18
17

29

16

15

100P_0402_50V8J~D

REGN

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2008/1/3 2009/01/3

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

B

D

Date: Sheet

Compal Electronics, Inc.

Charger

JBL30

****

31 39Monday, January 14, 2008

E

0.3

of

5

4

3

2

1

B+

PL12

FBMA-L11-322513-151LMA50T_1210~D

1 2

12

12

D D

+3VALWP

1

+

PC208

220U_6.3V_M

C C

2

PR214

1 2

PR216

1 2

@

0_0402_5%~D

10K_0402_1%~D

12

PC199

PC198

4.7U_1206_25V6K~D

4.7U_1206_25V6K~D

PL14

1 2

4.7UH_SIL104R-4R7PF_5.7A_30%

PC200

2200P_0402_50V7K~D

PR210

4.7_1206_5%~D

PC211

680P_0603_50V7K~D

Rds(on) = 18m ohm(max) ; Rds(on) = 15m ohm(typical)

3.3VALWP
Imax=6A

VS

PD28

RLZ5.1B_LL34

1 2

Iocp=10.133A

B B

MAINPWON36

2

1 3

PD35

1 2

A A

1SS355TE-17_SOD323-2

ISL6237_B+

PQ55

12

12

PR220

100K_0402_1%~D

1 2

PQ71

TP0610K-T1-E3_SOT23-3

578

AO4466_SO8

3 6

241

578

PQ57
AO4712_SO8

3 6

241

PR221

200K_0402_5%~D

0_0402_5%~D

1 2

PR228

PC209

0.1U_0603_25V7K~D

1 2

PC215

0.22U_0603_25V7-K

1 2

VL

PR226

1 2

806K_0603_1%

12

12

PR209

0_0805_5%

1 2

0.1U_0603_25V7K~D

PR212

BST3A BST5A

12

0_0603_5%~D

LX3

DL3

FB3

VL

2VREF_ISL6237

1 2

PC214 0.22U_0603_10V7K~D

PR224

@

0_0402_5%~D

1 2

PR229

47K_0402_5%~D@

1 2

PC216

0.047U_0603_16V7K~D

12

PC217

@

0.047U_0402_16V7K~N

PC204

33
26
24

25

23

30

32

20

14

27

PR225

1 2

2VREF_ISL6237

1 2

6

PU13

TP
UGATE2
BOOT2

PHASE2

LGATE2

OUT2

REFIN2

1

REF

8

LDOREFIN

NC

4

EN_LDO

EN1

EN2

5

0_0402_5%~D

12

PC272

1U_0603_10V6K~D

VIN

NC

1 2

PC205

1U_0603_10V6K~D

3

VCC

TON

2

12

PR227

@

0_0402_5%~D

2VREF_ISL6237

VL

12

PC206

7

4.7U_0805_6.3V6K~N

19

LDO

PVCC

15

UGATE1

17

BOOT1

16

PHASE1

18

LGATE1

22

PGND

10

OUT1

11

FB1

9

BYP

29

SKIP

28

POK2

13

POK1

12

ILIM1

31

ILIM2

GND

ISL6237IRZ-T_QFN32_5X5

21

578

PQ56

AO4466_SO8

3 6

241

PC207

1U_0603_10V6K~D

1 2

DH5DH3

PR213

0_0603_5%~D

0.1U_0603_25V7K~D

LX5

DL5

FB5

PR218 0_0402_5%~D@

PR219 0_0402_5%~D

1 2

ILM1

ILIM2

12

PC210

1 2

12

PR222

330K_0402_1%

PR223

330K_0402_1%

PQ58

AO4712_SO8

12

12

578

3 6

VL

PR211

241

POK

Rds(on) = 18m ohm(max) ; Rds(on) = 15m ohm(typical)

5VALWP
Imax=6A

Iocp=10.146A

ISL6237_B+

12

12

PC202

PC201

4.7U_1206_25V6K~D

4.7U_1206_25V6K~D

PL13

4.7UH_SIL104R-4R7PF_5.7A_30%

12

4.7_1206_5%~D

12

PC212

680P_0603_50V7K~D

12

PC203

2200P_0402_50V7K~D

12

PR215

1 2

61.9K_0402_1%~D

PR217

1 2

10K_0402_1%~D

+5VALWP

1

+

PC213
220U_6.3V_M

2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2008/1/3 2009/01/3

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

+3VALWP, +5VALWP

Size Document Number Rev

2

Date: Sheet

LA-4191P

Monday, January 14, 2008

1

32 39

of

0.3Custom

5

PR237

PR248

1 2

AO4466_SO8

0_0603_5%~D

12

PC235

0.1U_0402_16V7K~N

串1K電組 上

PR232

1K_0402_1%~D

@

1 2

+1.2V_EN

LX_+1.2V

UG_+1.2V

PR252

0_0603_5%~D

PGOOD1 PGOOD2

PL15

FBMA-L11-322513-151LMA50T_1210~D

1 2

D D

C C

+1.2VALWP

PC232

220U_6.3V_M

B+

PR240

1 2

12.1K_0402_1%

PC226

0.033U_0402_16V7K~D

1 2

PL16

1 2

1.8UH_SIL104R-1R8PF_9.5A_30%

1

+

2

DCR 7m ohm(max)

VCCPP
Imax=5A

12

PC275

470P_0402_50V8J~D

1000P_0402_25V8-J

PC224

12

68K_0402_1%

12

PR247

12.1K_0402_1%

1 2

3.3K_0402_5%~D
PR238

1 2

PR239

ISL6228_B+

12

PC227

4.7U_1206_25V6K~D

12

PR250

4.7_1206_5%~D

12

PC234

680P_0603_50V8J~D

ISL6228_B+

12

PC276

680P_0402_50K X7R~D

64.9K_0402_1%

12

578

PQ59

PC228

4.7U_1206_25V6K~D

3 6

241

578

PQ60
AO4712_SO8

3 6

241

Iocp=9A

B B

+3VALWP

PR256

47K_0402_5%~D

12

+1.2V_EN

12

PC241

0.1U_0402_16V7K~N

4

PC219

PC218

1U_0402_6.3V6K~D

@

+5VALWP +5VALWP

+5VALWP

BST_+1.2V

12

LG_+1.2V

12

1000P_0402_50V7K~D

10

11

12

13

14

+5VALW

1U_0402_6.3V6K~D

0.1U_0603_25V7K~D

ISL6228_B+ ISL6228_B+

PC222

7

PGOOD1

8

FB1

9

VO1

OCSET1

EN1

PHASE1

UGATE1

BOOT1

PVCC115LGATE116PGND117PGND218LGATE219PVCC220BOOT2

PC237

1 2

2.2_0603_1%~D

PC220

PR233

12

10_0603_1%

12

PR235

22K_0402_1%~D

1 2

6

FSET1

ISL6228HRTZ-T_QFN28_4X4

PR230

12

5

VIN1

PU14

12

1U_0402_6.3V6K~D

12

3

VCC2

PR231

1 2

2.2_0603_1%~D

12

0.1U_0603_25V7K~D

PC223

1000P_0402_50V7K~D

2

VIN2

+5VALW

PC240
1U_0402_6.3V6K~D

1 2

12

4

VCC1

PC221

PR234

10_0603_1%

12

1

GND_T

FSET2

PGOOD2

OCSET2

PHASE2

UGATE2

21

BST_1.8V

3

12

PR236

18.2K_0402_1%~D

1 2

29

28

27

FB2

26

VO2

25

24

EN2

23

22

PR255

1 2

0_0603_5%~D

LG_1.8V

PR241

1K_0402_1%~D

@

PR249

10K_0402_5%~D

1 2

PC229

1 2

0.1U_0402_16V7K~N

UG_1.8V

12

+5VALWP

PR253

0_0603_5%~D

1 2

LX_1.8V

PC238

1 2

0.1U_0402_16V7K~N

SYSON 25,26,29

578

PQ61

578

3 6

3 6

241

241

ISL6228_B+

AO4466_SO8

PQ62
AO4712_SO8

12

1 2

12

PC230

4.7U_1206_25V6K~D

12

PR254

4.7_1206_5%~D

12

PC239

680P_0603_50V8J~D

PR242
34K_0402_1%~N

PC233

4.7U_1206_25V6K~D

2

3.3K_0402_5%~D
1000P_0402_25V8-J

PR243

PC225

1 2

12

PR244

1 2

68K_0402_1%

PR245

1 2

16.5K_0402_1%~D

0.033U_0402_16V7K~D
PC231

1 2

PR251

16.5K_0402_1%~D

1 2

PL17

1 2

1.8UH_SIL104R-1R8PF_9.5A_30%

DCR 7m ohm(max)

1.8VP
Imax=9A

Iocp=12.6A

PR246
0_0402_5%~D

1 2

1

2

1

+1.8VP

+

220U_6.3V_M

PC236

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2008/1/3 2009/01/3

Compal Secret Data

Deciphered Date

2

Title

Size Document Number Rev

Date: Sheet

+1.8VP/+VCCPP

Monday, January 14, 2008

JBL30

of

1

33 39

0.3

5

4

3

2

1

+1.5VSP/+0.9VSP

+1.8V

D D

4.7U_0805_6.3V6K~N

PR88

0_0402_5%~D

SYSON#29

C C

1 2

0.1U_0402_16V7K~N@

PC49

PC54

1

PJP2

1

JUMP_43X118@

2

2

1.8V_0.9V

12

13

D

2

G

S

12

PR94

1K_0402_1%~D

PQ22

PR95

1K_0402_1%~D

SSM3K7002FU_SC70-3

12

12

12

PC50

0.1U_0402_16V7K~N

PU6

VIN1VCNTL

2

GND

3

VREF

4

VOUT

APL5331KAC-TRL_SO8~N

+0.9VP

12

PC48

4.7U_0805_6.3V6K~N

6
5

NC

7

NC

8

NC

9

TP

+3VALWP

12

PC47
1U_0603_10V6K~D

4.7U_0805_6.3V6K~N

PR132

0_0402_5%~D

0.1U_0402_16V7K~N @

1 2

SUSP20,29

PC88

PC91

+1.8V

12

PJP3
PAD-OPEN1x1m

1.8V_1.5V

12

13

D

2

G

S

12

PR133

200_0402_1%~N

PQ37

PR131

1K_0402_1%~D

SSM3K7002FU_SC70-3

12

12

12

PC89

0.1U_0402_16V7K~N

PU11

VIN1VCNTL

2

GND

3

VREF

4

VOUT

APL5331KAC-TRL_SO8~N

+1.5VSP

12

PC90

4.7U_0805_6.3V6K~N

6
5

NC

7

NC

8

NC

9

TP

+3VALWP

12

PC92
1U_0603_10V6K~D

B B

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2008/1/3 2009/01/3

Compal Secret Data

Deciphered Date

Title

<Title>

+1.5VSP/+0.9VP

Size Document Number Rev

Custom

LA-4191P

2

Date: Sheet

1

34 39Monday, January 14, 2008

0.3

of

5

4

3

2

1

+3VS

25

PSI#

PR265

D D

10K_0402_5%~D

VR_ON

1 2

6

VID4

VID56VID36VID26VID16VID0

VGATE25

+3VS

1 2

1 2

PR2670_0402_5%~D

PR2660_0402_5%~D

1 2

1 2

1 2

1 2

PR2700_0402_5%~D

PR2680_0402_5%~D

PR2690_0402_5%~D

VCC_PRM

PR276

PR275

1 2

1 2

@

10K_0402_5%~D

10K_0402_5%~D

1 2

PC248

1 2

PR279

1000P_0402_50V7K~D

1 2

PC245

1000P_0402_50V7K~D

6.81K_0603_1%

1 2

PR2805.36K_0402_1%~D

1 2

PC246

0.047U_0603_25V7M

1 2

PR281

51.1K_0402_1%

1 2

1

PR278150K_0402_1%~D

2
3
4

C C

PR288

97.6K_0402_1%~D

1 2

220P_0402_50V8J~D

1K_0402_1%~D

PR292

255_0402_1%~D

1 2

CPU_VDD_FB_H6

+CPU_CORE

B B

CPU_VDD_FB_L6

PC251

470P_0402_50V7K~D

1 2

PC253

1 2

PR290

12

PC255

1000P_0402_50V7K~D

1 2

PR293

0_0402_5%~D

PR294

100_0402_1%

PR297

0_0402_5%~D

5
6
7
8

9
10
41

PC257

0.068U_0603_16V7K

1 2

PC256

12

@

1000P_0402_50V7K~D

12

12

PR298
100_0402_1%

1 2

1 2

1 2

PC260

1000P_0402_50V7K~D

1 2

PC262

0.22U_0402_6.3V6K~D

PR295

1K_0402_1%~D

VCC_PRM

1 2

PC264

0.22U_0402_6.3V6K~D

PC261

180P_0402_50V8J~D

1 2

PR296

1.82K_0402_1%~D

1 2

12

1 2

PC263

0.022U_0402_16V7K~D

SET
RBIAS
OFS
SOFT
OCSET
VW
COMP
FB
VDIFF
VSEN
GND PAD

PR301

1 2

39

40

38

PSI_L

VR_ON

PGOOD

ISL6264CRZ-T_QFN40_6X6

DROOP

RTN

DFB

12

11

13

PH2

1 2

11K_0402_1%~D

PR307

1 2

10K_0603_5%_TSM1A103J4302RE

2.61K_0402_1%~D

VSUM

37

PU15

GND

VSUM

VIN

VO

17

15

16

14

B+

1 2

1 2

1 2

1 2

PR2710_0402_5%~D

PR2720_0402_5%~D

PR2730_0402_5%~D

VID032VID133VID234VID335VID436VID5

ISEN2

VDD

19

18

+5VALW

PR300

10_0603_5%~D

PC266

0.01U_0603_50V7K~D

6

4.7_0603_1%~D

31

BOOT1

UGATE1
PHASE1

PGND1

LGATE1

PVCC

LGATE2

PGND2
PHASE2
UGATE2

BOOT2

ISEN1

20

ISEN1

ISEN2

PR299

1 2

10_0603_5%~D

12

PC267

PR277

1U_0402_6.3V6K~D

12

0.22U_0603_10V7K~D

30
29
28
27
26
25
24
23
22
21

PR291

4.7_0603_1%~D

PC247

12

UG1-1

PR287 0_0402_5%~D

12

PC250

4.7U_0603_6.3V6K~D

UG2-1

12

12

PC254

0.22U_0603_10V7K~D

PL19

FBMA-L11-322513-151LMA50T_1210~D

1

+

PC244

2

100U_25V_M~D

10U_1206_25V6M~D

PL20

1 2

12

+CPU_CORE

B+

PHASE1

3 5

241

PQ65
SI7686DP-T1-E3_SO8

CPU_B+

1 2

1 2

PC242

PC243

10U_1206_25V6M~D

0.36UH_PCMC104T-R36MN1R17_30A_20%

5

PQ66

12

+5VALW

SI4856DY-T1-E3_SO8

4

LG1

5

D8D7D6D

PQ67

S1S2S3G

D8D7D6D

PR282

SI4856DY-T1-E3_SO8

4

1 2

S1S2S3G

4.7_1206_5%~D

12

1 2

VSUM

PR283

3.65K_0805_1%~D

PR284

PC249

10K_0402_1%~D

0.22U_0603_16V7K~D

1 2

1 2

PC252

1 2

VCC_PRMISEN1

PR285

PR286

0_0402_5%~D@

1_0402_5%~D

1 2

ISEN2

680P_0603_50V8J~D

CPU_B+

1 2

1 2

PC258

PC259

10U_1206_25V6M~D

10U_1206_25V6M~D

PL21

0.36UH_PCMC104T-R36MN1R17_30A_20%

1 2

+CPU_CORE

PHASE2

3 5

241

PQ68
SI7686DP-T1-E3_SO8

5

PQ69

LG2

D8D7D6D

S1S2S3G

SI4856DY-T1-E3_SO8

4

PQ70

5

D8D7D6D

PR302

SI4856DY-T1-E3_SO8

1 2

S1S2S3G

4

4.7_1206_5%~D

12

1 2

VSUM

PR303

3.65K_0805_1%~D

PR304

PC265

10K_0402_1%~D

0.22U_0603_16V7K~D

1 2

1 2

PC268

1 2

VCC_PRMISEN2

PR305

PR306

0_0402_5%~D@

1_0402_5%~D

1 2

ISEN1

680P_0603_50V8J~D

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2008/1/3 2009/01/3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

2

Date: Sheet

+CPU_CORE

JAWAE-Dallas 10A LA3631P

Monday, January 14, 2008

0.3

of

35 39

1

5

4

3

2

1

D D

C C

1 2

B+

+5VALW

B B

PR111

1 2

220K_0402_5%

12

PC75

0.1U_0603_25V7K~D

BATT+

PL1

HCB4532KF-800T90_1812

BATT+

1 2

12

12

PC21

0.01U_0402_25V7K~D

PC273

100P_0402_50V8J~D

PJPB1 battery connector

SMART
Battery:

1.BAT+

2.BAT+

3.ID

4.B/I

5.TS

6.SMD

7.SMC

8.GND

9.GND

PR107

100_0805_5%~D

PR108

1 2

12

1 2

220K_0402_5%

470K_0402_5%~D

PQ32

2

G

PD7

1SS355_SOD323-2

PR110

TP0610K-T1-E3_SOT23-3

2

13

D

S

32.8

SSM3K7002FU_SC70-3

BATT++

12

PC6

1000P_0402_50V7K~D

SUYIN_200275MR009G154ZL_RV

PJP5

BATT+
BATT+

B/I

TS

SMD

PC71

GND
GND

SMC
GND­GND-

1 2

0.1U_0603_25V7K~D

13

10
11

PQ29

12

1
2
3

ID

4
5
6
7
8
9

@

BATT++

PC274

100P_0402_50V8J~D

PC270

10P_0402_50V8J

@

10P_0402_50V8J

B+_BIAS

BATT_OVP25

PD34

DA204U_SOT323~D

@

1

2

PC271

@

3

1

+3VALWP

2

1 2

3cell/4cell#31

1

2

7

0

3

PD16

DA204U_SOT323~D

@

PR264
47K_0402_5%~D

1 2

PR10

100_0402_5%~D

1 2

PR9

100_0402_5%~D

8

PU3B

P

+

-

G

LM358ADT_SO8~N

4

2

2

1

PD32

DA204U_SOT323~D

@

2

3

1

EC_SMB_DA1 25

EC_SMB_CK1 25

PD18

DA204U_SOT323~D

@

PR135

1K_0402_5%~D

12

3

1

BATT+

12

PR37
453K_0402_1%~D

0.01U_0402_25V7K~D

12

PR44

499K_0402_1%~D

12

PR52

86.6K_0402_1%

VS

12

PC32

5
6

+3VALWP

Place clsoe to EC pin

BATT_TEMP

1 2

PR173

1K_0402_5%~D

1 2

1 2

PR134

6.49K_0402_1%~D

PC43

1000P_0402_50V7K~D

BATT_TEMP 25

PC130

0.1U_0402_16V7K~N

@

CPU

+3VALWP

CPU

12

PH1 under CPU botten side :

CPU thermal protection at 90 degree C
Recovery at 50 degree C

VL VS

12

PR87

10.7K_0402_1%~D

PR83

61.9K_0402_1%~D

1 2

1 2

VL

PR84

150K_0402_1%~D

12

PH1
100K_0603_1%_TH11-4H104FT

150K_0402_1%~D

PR85

PR82

442K_0402_1%~D

1 2

12

12

8

PU3A

3

P

+

0

2

-

G

LM358ADT_SO8~N

4

PC42
1U_0603_10V6K~D

Battery Connect/OTP

PC115

0.1U_0603_25V7K~D

1 2

1

1 2

PD25

1SS355_SOD323-2

VL

PR81
150K_0402_1%~D

1 2

MAINPWON 32

LI-4S :18V----BATT-OVP=1.498V

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2008/1/3 2009/01/3

Compal Secret Data

Deciphered Date

Title

BATTERY CONN

Size Document Number Rev

Custom

LA-4191P

2

Date: Sheet

1

36 39Monday, January 14, 2008

0.3

of

5

4

3

2

1

Version Change List ( P. I. R. List )

Page 1

Request

Item Issue DescriptionDate

1

D D

C C

31

2

3 08/01/04 COMPAL When in the DC-mode , shut down the system ,5valwp output not turn off ADD PD35 to turn off 5VALWP wehn shut down the system in the DC-mode+3VALWP/+5VALWP32

Charge

Charge31

08/01/04 COMPAL adjust battery charge voltage set CHANGE PR310 from 15K to 4.3K

08/01/04

Owner

DEL PR205 PQ53VIN Detector has the same functionCOMPAL

Solution Description Rev.Page# Title

B B

A A

Compal Electronics, Inc.

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

Next: PR238, PC202, PQ56, PD42, PJP21

5

4

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

EE-PIR

Size Document Number Rev

LA-4191P

Date: Sheet

Monday, January 14, 2008 3937

1

of

0.3

5

4

3

2

1

Version change list (P.I.R. List) Page 1 of 1 for HW

Reason for change Rev. PG# Modify ListFixed IssueItem

1

Fine-tune CPU_PWRGD,LDT_STOP#,LDT_RST# Fine-tune CPU_PWRGD,LDT_STOP#,LDT_RST# 0.2 6 Delete CPU testpad

D D

2

3

4

5

6

7

8

C C

9

10

panel function

also change to PWR portion
Change CLK_PCI_TPM and CLK_PCI_EC to

PCICLK5 and 6 (ATI recommend)
Modify Media card circuit to OZ129 0.2 20

Change Audio codec LDO to RT9198-4GPBG 0.2 22

USB port power control by EC 0.2 27 USB_EN(High=Enable)

touch sensor to EC
RTL8102E ver.B have E-fuse to flash

MAC address.
Change RJ45 connector to include LED type. 0.3 21

11

12

13

14Reserve LCD enable from EC for test

0.2 Add BIST and LCD_DET and LCD_VCC_TEST_EN from EC

150.2Change RTC battery to cable type,

0.2 15

Modify Media card circuit to OZ129

Change Audio codec LDO to RT9198-4GPBG

0.3 28CAPS,NUM,SCR LED control change from

0.3 U16 change to DNI (@)21

14

15

16

B B

17

18

19

20

21

22

23

24

A A

25

26

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2008/1/3 2009/01/3

Compal Secret Data

Deciphered Date

Title

PIR (HW)

Size Document Number Rev

Custom

LA-4191P

2

Date: Sheet

1

38 39Monday, January 14, 2008

0.3

of

5

4

3

2

1

ACIN

3VALW / 1.8VALW

2ms

+5/3/1.2VALW

ON/OFF#

D D

32ms

t<=10 ms

EC_ON

PWRBTN_OUT#

EC_RSMRST#

SYSON

t=560us

27.76ms

t=104 mst=134 ms

239.3ms

3V / 1.8V

<1ms

+5/3/1.8V

PWRBTN to SLP_S3#

SLP_S3/S5#

C C

T13>200ns

SUSP#

+5/3/1.8VS
VR_ON

105.1ms

143.4ms

3VS / 1.8VS

<1ms

9.472ms

+CPU_CORE

VLDT_EN

B B

+1.2V_NBCORE/+1.2V_HT

+CPU_CORE to NB_PWRGD

NB_PWRGD

T6 > 15ms

25.674ms

4.41ms

36.404ms

NB_PWRGD to SB_PWRGD

SB_PWRGD

CPU_PWRPG

A_RST#

SB_PWRGD to PCI_RST

PCI_RST#

A A

71ms < T9 < 72.1ms

LDT_RST#

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

-22ms < T7 < 500ms

SB_PWRGD to CPU_PWRGD
47ms < T8D < 66ms

SB_PWRGD to A_RST
71ms < T9A < 72ms

A_RST to PCI_RST
T8A < 80ns

PCI_RST to LDT_RST
19ms < T8C < 2.1ms

2008/1/3 2009/01/3

3

Compal Secret Data

65.2 ms

71.27 ms

78.15ns

2ms

Deciphered Date

Title

Size Document Number Rev

2

Date: Sheet

Power Sequence

Monday, January 14, 2008

LA-4191P

1

of

39 39

0.3

Compal Electronics, Inc.