COMPAL LA-4161P Schematics

1 1

JSKAA

2 2

Irving 10/10G

LA4161P

3 3

REV 1.0

Schematic

Intel Penryn/ Cantiga (GL45/GM45/PM45)/ ICH9M

2008-10-01 Rev. 1.0

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2008/10/1 2009/10/1

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

SCHEMATICS,M/B A4161

401562 G

148Monday, February 23, 2009

Compal Confidential

XDP Debug

page 4

Model Name : JSKAA File Name :

1 1

CRT

page 18

VGA Conn.

HD Audio

3.3V 24.576MHz/48Mhz

EC SMBUS

2 2

3 3

HDMI CEC Controller R5F211A4SP

page 19

PCIeMini Card -WiMAX USB port 7

PCIeMini Card -WLAN

NB9M-GS NB9P-GE/GS NB9E-GS

page 17

HDMI Conn.

Mini Slot 1 Mini Slot 2 Mini Slot 3

page 26

PCIeMini Card --

PCIe port 4

Robson/ HDDVD

PCIe port 2

Express Card

USB port 8

LCD Conn.

page 19

page 27page 26

Express Card Slot

page 26

page 17

PCIeMini Card -UWB/ TV tuner/ GPS

USB port 6

Express Card

PCIe port 1

FM Tuner

NXP--TEA5763HN

Fan Control

PCI-Express 16x

Level Shifter

page 19

page 26

page 25

page 4

USB

5V 48MHz

PCIe 1x [4..5]

USB

5V 48MHz

PCIe 1x

I2C from SB

Intel Penryn Processor

uPGA-478 Package

(Socket P)

H_A#(3..35) H_D#(0..63)

FSB

667/800/1066MHz

page 4,5,6

Intel Cantiga

PM/GM/GL

uFCBGA-1329

page 7,8,9,10,11,12,13

DMI

C-Link

Intel ICH9-M

BGA-676

page 20,21,22,23

PCI BUS

3.3V 33 MHz

5V 48MHz

SATA [0..1]

5V 1.5GHz(150MB/s)

SATA

5V 1.5GHz(150MB/s)

5V 48MHz

5V 1.5GHz(150MB/s)

HD Audio

3.3V 24.576MHz/48Mhz

Thermal Sensor

SMSC--EMC1402-1-ACZL

page 4

Memory BUS(DDRII)

Dual Channel

1.8V DDRII 533/667/800

HD Audio

3.3V 24.576MHz/48Mhz

PCIe 1x

USB

LOM(1G)

RTL8111C

PCIe port 5

TMA

USB conn x2

USB port0--Rare USB port1--Right

page 25

SATA HDD0

SATA ODD

USB

SATA

eSTAT/USB Conn

eSATA port5

page 24

LPC BUS

3.3V 33 MHz

Mini PCI

ISDB-T TV Tuner

DC I/F to HW

page37

4 4

page32

B-CAS

page32

Power Circuit DC/DC

page38~45

LPC Debug Port.

page35

LED/B Conn.

page36

VR/B Conn.

page36

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

T/P

page35

ENE KB926 C0

page34

FUN/B Conn.

page36

PWR/B Conn.

page36

2008/10/1 2009/10/1

Int.KBD

page35

SPI ROM

page35 page35

Compal Secret Data

IR/B

page33

EC Debug

Deciphered Date

Clock Generator

Seligo--SLG8SP553VTR ICS--ICS9LPRS387AKLFT

page 16

200pin DDRII-SO-DIMM X2

BANK 0, 1, 2, 3

PCIe port 3

page 28 page 28

page 27

BT2.1

USB port 5

page 25 page 25

page 24

USB port 3

RJ45

FingerPrinter

USB port 4

page 25 page 25

SATA HDD1

page 24

MDC 1.5 Conn

page29

AOCR/B LS4164P Conn.

HDAALC272

CardReader/ 1394JMB380

PCIe port 6

USB- Left Port USB Port2

page29

PCIe 1x

USB

5V 48MHz

Title

Size Document Number Rev

Date: Sheet

page 14,15

Flica

USB port 9

Int. Camera USB port 11

Int. MIC CONN

page29

SPK-L/R CONN SPK-L/R LED CONN

page29

Compal Electronics, Inc.

SCHEMATICS,M/B A4161

401562 G

248Monday, February 23, 2009

Voltage Rails

Power Plane Description

VIN

1 1

2 2

B+ +CPU_CORE +0.9V 0.9V switched power rail for DDR terminator +1.05VS +1.5VS +1.8V

+3VALW +3VL 3.3V always on power rail ONON +3V_SB 3.3V power rail for LAN ON ON +3V_LAN 3.3V power rail for LAN ON ON +3V_WLAN 3.3V power rail for LAN ON ON +3VS +5VALW +5VL 5V always on power rail ON ON

+5VS +VSB VSB always on power rail ON ON +RTCVCC RTC power

Adapter power supply (19V) AC or battery power rail for power circuit. Core voltage for CPU

1.05V switched power rail

1.5V switched power rail

1.8V power rail for DDR

3.3V always on power rail

3.3V switched power rail 5V always on power rail

5V switched power rail

S1 S3 S5

ON ON ON OFF ON ON ON ON ON OFF ON OFF ON OFF OFF ON OFF OFF ON OFF

ON ON

OFF OFF

ON ON

ON ON OFF OFF OFF

OFF

ON ON

ON ON OFF OFF+5V_SB 5V power rail for SB ON ON

OFF

OFFON

ONON

OFF OFF OFF OFF OFF

OFF

OFF OFF OFF OFF OFF

OFF OFF ON

SIGNAL

STATE

Full ON

S1(Power On Suspend)

S3 (Suspend to RAM)

SLP_S1# SLP_S3#

SLP_S4# SLP_S5#

HIGH HIGH HIGH HIGH

LOW

S4 (Suspend to Disk)

S5 (Soft OFF)

LOW LOW LOW LOW

HIGH

LOWLOWLOW

HIGHHIGHHIGH

HIGH

G3 LOWLOWLOWLOW

Reserve for AD channel define.

Vcc 3.3V +/- 5%

Board ID

0 1 2 3 4 5 6 7NC

100K +/- 5%Ra/Rc/Re

Rb / Rd / Rf V min

8.2K +/- 5% 18K +/- 5% 33K +/- 5% 56K +/- 5% 100K +/- 5% 200K +/- 5%

AD_BID

0 V

0.216 V 0.250 V 0.289 V

0.436 V

0.712 V

1.036 V

1.453 V 1.650 V 1.759 V

1.935 V

2.500 V

V typ

AD_BID

0 V 0 V

0.503 V

0.819 V

0.538 V

0.875 V

1.185 V 1.264 V

2.200 V

3.300 V

2.341 V

3.300 V

max

BTO Option Table

External PCI Devices

Device IDSEL# REQ#/GNT# Interrupts

PCI TV Tuner

AD18 (Master) AD19 (Slave)

1/1 (Master) 2/2 (Slave)

PIRQG (Master) PIRQH (Slave)

BTO Item BOM Structure

EC SM Bus1 address

Device

EC KB926 C0+5VL EC KB926 C0+3VS

3 3

Smart Battery+5VL HDMI-CEC+5VL

+5VL FUN/B (CAP Sensor)

Address Address

0001 011X b 0011 010x b

EC SM Bus2 address

Device

PowerPower

CPU THM Sen .SMSC

+3VS

EMC1402-1-ACZL-TR

VGA THM Sen. nVedia+3VS

1001 100x b

1001 1110 b

ICH9M SM Bus address

Device

Power

ICH9M

+3V_SB

Clock Generator

+3VS

(SLG8SP556V) DDR DIMM0

+3VS

DDR DIMM1

+3VS

Express

+3VS

4 4

+3VS

FM Module

Vertial I2C

Address

1101 001Xb

1001 000Xb 1001 010Xb

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2008/10/1 2009/10/1

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

SCHEMATICS,M/B A4161

401562 G

348Monday, February 23, 2009

H_A#[3..16]<7>

D D

H_ADSTB#0<7>

H_REQ#0<7> H_REQ#1<7> H_REQ#2<7> H_REQ#3<7> H_REQ#4<7>

H_A#[17..35]<7>

C C

H_ADSTB#1<7>

H_A20M#<21>

H_FERR#<21>

H_IGNNE#<21> H_STPCLK#<21>

H_INTR<21>

H_NMI<21> H_SMI#<21>

+CPU_GTLREF2

QC: POP DC: DEPOP

B B

+1.05VS

@ R984

51_0402_1%

1 2

THRMDA_2 THRMDC_2

R984

H_A20M# H_FERR# H_IGNNE#

H_STPCLK# H_INTR H_NMI H_SMI#

XDP_BPM2#1 XDP_BPM2#0

XDP_BPM2#2

TDO_M TDI_M

H_FERR#

H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16

H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 H_A#32 H_A#33 H_A#34 H_A#35

C685 180P_0402_50V8J@C685 180P_0402_50V8J@

AA4 AB2 AA3

D22

J4 L5 L4

J1 N3 P5 P2

L2 P4 P1 R1

K3 H2 K2

L1 Y2

U5 R3

U4 Y5 U1 R4 T5 T3

W2 W5

Y4 U2 V4

V1 A6

A5 C4

D5 C6 B4 A3

N5 T2 V3 B2 D2

D3 F6

@ JP1A

JP1A

A[3]# A[4]# A[5]# A[6]# A[7]# A[8]# A[9]# A[10]# A[11]# A[12]# A[13]# A[14]# A[15]# A[16]# ADSTB[0]#

REQ[0]# REQ[1]# REQ[2]# REQ[3]# REQ[4]#

A[17]# A[18]# A[19]# A[20]# A[21]# A[22]# A[23]# A[24]# A[25]# A[26]# A[27]# A[28]# A[29]# A[30]# A[31]# A[32]# A[33]# A[34]# A[35]# ADSTB[1]#

A20M# FERR# IGNNE#

STPCLK# LINT0 LINT1 SMI#

RSVD[01] RSVD[02] RSVD[03] RSVD[04] RSVD[05] RSVD[06] RSVD[07] RSVD[08] RSVD[09]

Penryn

ADDR GROUP_0

ADS# BNR# BPRI#

DEFER#

DRDY# DBSY#

BR0#

IERR#

INIT#

LOCK#

CONTROL

RESET#

RS[0]# RS[1]# RS[2]#

TRDY#

HIT#

HITM#

ADDR GROUP_1

BPM[0]# BPM[1]# BPM[2]# BPM[3]#

PRDY# PREQ#

TCK

TDI TDO TMS

TRST#

DBR#

XDP/ITP SIGNALS

THERMAL

PROCHOT#

THERMDA THERMDC

ICH

THERMTRIP#

H CLK

BCLK[0] BCLK[1]

RESERVED

H1 E2 G5

H5 F21 E1

F1 D20

B3 H4 C1

F3 F4 G3 G2

G6 E4

AD4 AD3 AD1 AC4 AC2 AC1 AC5 AA6 AB3 AB5 AB6 C20

D21 A24 B25

A22 A21

H_IERR# H_INIT#

H_RESET#

XDP_DBRESET#

H_PROCHOT# H_THERMDA H_THERMDC

Reserve for debug close to South Bridge

H_ADS# <7> H_BNR# <7>

H_BPRI# <7>

H_DEFER# <7> H_DRDY# <7> H_DBSY# <7>

1 2

H_BR0# <7>

H_INIT# <21> H_LOCK# <7>

H_RESET# <7>

H_RS#0 <7>

H_RS#1 <7>

H_RS#2 <7>

H_TRDY# <7>

H_HIT# <7> H_HITM# <7>

XDP_DBRESET# <22>

H_THERMTRIP# <8,21>

+CPU_GTLREF2

R1 49.9_0402_1%R1 49.9_0402_1%

XDP_BPM#0 XDP_BPM#1 XDP_BPM#2 XDP_BPM#3 XDP_BPM#4 XDP_BPM#5

XDP_TCK XDP_TDI XDP_TDO XDP_TMS

XDP_TRST#

CLK_CPU_BCLK <16> CLK_CPU_BCLK# <16>

QC: ES1: DePOP ALL ES2: POP ALL DC: DEPOP ALL

XDP_BPM2#3<5>

+1.05VS

XDP_TMS

R137 51_0402_1%R137 51_0402_1%

XDP_BPM#5

R985

XDP_TDI XDP_TRST# XDP_TCK

1 2

R4 51_0402_1%R4 51_0402_1%

1 2

R6 51_0402_1%R6 51_0402_1%

1 2

R136 51_0402_1%R136 51_0402_1%

Place close to CPU within 200ps = 1000 mil

Pull-High for ITP.

H_RESET#

1 2

R5 49.9_0402_1%@R5 49.9_0402_1%@

PROCHOT# PU: 68Ohm near CPU and MVP6. 56Ohm near CPU

+1.05VS

H_THERMDA, H_THERMDC routing together, Trace width / Spacing = 10 / 10 mil

+1.05VS

Quad Core support circuit

R942

@R942

1K_0402_1%

@R944

BSS138_NL_SOT23-3

R944

2K_0402_1%

Layout close CPU PIN D22

Q129

1 2

R7 56_0402_5%@R7 56_0402_5%@

1 2

R8 68_0402_5%R8 68_0402_5%

H_PROCHOT#

+3VALW

R943 100K_0402_5%

100K_0402_5%

3 1

Q20

Q20 MMBT3904_NL_SOT23-3

MMBT3904_NL_SOT23-3

50 ohm, 0.5 inch (max)

XDP_BPM2#0 XDP_BPM2#1 XDP_BPM2#2 XDP_BPM2#3

51_0402_1%

@R985

51_0402_1%

+1.05VS

@R943

R946

10K_0402_5%

R977 R979 R981 R983

+1.05VS

3 1

+3VALW

@R946

@R977

@ @R979

@ @R981

@ @R983

R945 100K_0402_5%

100K_0402_5%

+1.05VS

51_0402_1%

51_0402_1% 51_0402_1%

51_0402_1%

+1.05VS

C155 0.1U_0402_16V4ZC155 0.1U_0402_16V4Z

MMBT3904_NL_SOT23-3

@R945

QUAD_DET <5>

OCP# <22>

+3VS

XDP_BPM#2 XDP_BPM#1

XDP_BPM2#2 XDP_BPM2#1

XDP_DBRESET# XDP_TRST# XDP_TMS

0.1U_0402_16V4Z

H_THERMDA

H_THERMDC

1 2

2200P_0402_50V7K

1 2

10K_0402_5%

DVT- Change CPU Debug port.

XDP Connector

JP3

@JP3

29 GND31GND

GND33GND

P-TWO_196027-30041

+3VS

EVT2- Change U1, thermal sensor source from ADI to SMSC

CPU_THERM#

VDD

THERM#

EMC1402-1-ACZL-TR_MSOP8

2 4 6

8 10 12 14 16 18 20 22 24 26 28 30

2 4 6 8 10 12 14

H_PWRGOOD_R

16 18 20 22 24 26 28 30

32 34

XDP_BPM#4XDP_BPM#5 XDP_BPM#3

XDP_BPM#0

XDP_BPM2#3 XDP_BPM2#0

XDP_TDO XDP_TDI XDP_PRE#

SMCLK

SMDATA

ALERT#

GND

R147

1 2

XDP_TCK

1K_0402_5%

CLK_XDP# <16>CLK_XDP<16>

1 2

R78 1K_0402_5%R78 1K_0402_5%

+1.05VS

1 2

R138 51_0402_1%R138 51_0402_1% R18 10K_0402_5%R18 10K_0402_5%

Place close to JITP within 200ps = 1000 mil

8 7 6

10K_0402_5%@R310K_0402_5%@

H_PWRGOOD <5,21>

H_RESET#H_RESET#_R

XDP_TDO XDP_PRE#

EC_SMB_CK2 <17,32> EC_SMB_DA2 <17,32>

Reserve for Source control

+3VS

H_SMI# H_INIT# H_NMI H_A20M# H_INTR H_IGNNE#

H_STPCLK#

A A

C687 180P_0402_50V8J@C687 180P_0402_50V8J@ C688 180P_0402_50V8J@C688 180P_0402_50V8J@ C678 180P_0402_50V8J@C678 180P_0402_50V8J@ C691 180P_0402_50V8J@C691 180P_0402_50V8J@ C692 180P_0402_50V8J@C692 180P_0402_50V8J@ C690 180P_0402_50V8J@C690 180P_0402_50V8J@ C694 180P_0402_50V8J@C694 180P_0402_50V8J@

12 12 12 12 12 12 12

Reserve for debug close to CPU

FAN Control Circuit

+5VS

+FAN1

EN_DFAN1<32>

EN_DFAN1

C7 10U_0805_10V4Z

10U_0805_10V4Z

DVT-Change FAN Driver from SA009930010-G993P1UF to SA00002GW00-G990P11U

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2008/10/1 2009/10/1

C6 10U_0805_10V4ZC6 10U_0805_10V4Z

1 2

VEN

2 3 4

Compal Secret Data

GND

VIN

GND GND

GND

VSET

G990P11U_SOP8

Deciphered Date

8 7 6 5

C3 1000P_0402_50V7K@C31000P_0402_50V7K@

+5VS

JP2

D1 1SS355_SOD323-2

1SS355_SOD323-2

+FAN1

D2 BAS16_SOT23-3

BAS16_SOT23-3

Title

Size Document Number Rev

Date: Sheet

JP2

GND

ACES_85205-03001

R13 10K_0402_5%R13 10K_0402_5%

+3VS

0.01U_0402_25V4Z

Compal Electronics, Inc.

SCHEMATICS,M/B A4161

401562 G

FAN_SPEED1 <32>

448Monday, February 23, 2009

G22 G25

G24

H26 H25

M24 M23

R24

N25 M26

N24

AD26

C23 D25 C24

AF26

AF1

C21

E22 F24 E26

F23 E25

E23 K24

H22 F26 K22 H23

N22 K25 P26 R23 L23

L22 P25

P23 P22 T24

L25 T25

L26

A26 B22

B23

J24 J23

J26

@ JP1B

JP1B

D[0]# D[1]# D[2]# D[3]# D[4]# D[5]# D[6]# D[7]# D[8]# D[9]# D[10]# D[11]# D[12]# D[13]# D[14]# D[15]# DSTBN[0]# DSTBP[0]# DINV[0]#

D[16]# D[17]# D[18]# D[19]# D[20]# D[21]# D[22]# D[23]# D[24]# D[25]# D[26]# D[27]# D[28]# D[29]# D[30]# D[31]# DSTBN[1]# DSTBP[1]# DINV[1]#

GTLREF TEST1 TEST2 TEST3 TEST4 TEST5 TEST6 TEST7 BSEL[0] BSEL[1] BSEL[2]

Penryn

H_D#[0..15]<7>

D D

H_DSTBN#0<7> H_DSTBP#0<7> H_DINV#0<7> H_D#[16..31]<7>

+1.05VS

Close to CPU pin

C C

1K_0402_1%

2K_0402_1%

AD26 within

R15

500mils.

+CPU_GTLREF

R20

layout note: Route TEST3 & TEST5 traces on ground referenced layer to the TPs

H_DSTBN#1<7> H_DSTBP#1<7> H_DINV#1<7>

CPU_BSEL0<8,16> CPU_BSEL1<8,16> CPU_BSEL2<8,16>

CPU_BSEL CPU_BSEL2 CPU_BSEL1

B B

166

200

+CPU_GTLREF

H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15

H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31

CPU_BSEL0

266 0 0 0

DATA GRP 0

MISC

DATA GRP 1

D[32]# D[33]# D[34]# D[35]# D[36]# D[37]# D[38]# D[39]# D[40]#

DATA GRP 2DATA GRP 3

D[41]# D[42]# D[43]# D[44]# D[45]# D[46]#

D[47]# DSTBN[2]# DSTBP[2]#

DINV[2]#

D[48]#

D[49]#

D[50]#

D[51]#

D[52]#

D[53]#

D[54]#

D[55]#

D[56]#

D[57]#

D[58]#

D[59]#

D[60]#

D[61]#

D[62]#

D[63]# DSTBN[3]# DSTBP[3]#

DINV[3]# COMP[0]

COMP[1] COMP[2] COMP[3]

DPRSTP#

DPSLP#

DPWR#

PWRGOOD

SLP#

PSI#

H_CPUSLP#

H_PWRGOOD

H_DPRSTP# H_DPSLP#

Y22 AB24 V24 V26 V23 T22 U25 U23 Y25 W22 Y23 W24 W25 AA23 AA24 AB25 Y26 AA26 U22

AE24 AD24 AA21 AB22 AB21 AC26 AD20 AE22 AF23 AC25 AE21 AD21 AC22 AD23 AF22 AC23 AE25 AF24 AC20

R26 U26 AA1 Y1

E5 B5 D24 D6 D7 AE6

C693 180P_0402_50V8J@C693 180P_0402_50V8J@ C695 180P_0402_50V8J@C695 180P_0402_50V8J@ C697 180P_0402_50V8J@C697 180P_0402_50V8J@ C696 180P_0402_50V8J@C696 180P_0402_50V8J@

H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47

H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63

COMP0 COMP1 COMP2 COMP3

H_DPRSTP# H_DPSLP#

H_PWRGOOD H_CPUSLP#

12 12 12 12

H_D#[32..47] <7>

H_DSTBN#2 <7> H_DSTBP#2 <7> H_DINV#2 <7> H_D#[48..63] <7>

H_DSTBN#3 <7> H_DSTBP#3 <7> H_DINV#3 <7>

H_DPRSTP# <8,21,42> H_DPSLP# <21>

H_DPWR# <7> H_PWRGOOD <4,21> H_CPUSLP# <7>

H_PSI# <42>

Reserve for debug close to CPU

Resistor placed within

0.5" of CPU pin.Trace should be at least 25 mils away from any other toggling signal. COMP[0,2] trace width is 18 mils. COMP[1,3] trace width is 4 mils.

COMP0

1 2

R16 27.4_0402_1%R16 27.4_0402_1%

COMP1

1 2

R19 54.9_0402_1%R19 54.9_0402_1%

COMP2

1 2

R21 27.4_0402_1%R21 27.4_0402_1%

COMP3

1 2

R22 54.9_0402_1%R22 54.9_0402_1%

D8 pin Reserved for QC

QUAD_DET<4>

Pin F8 Dual Core: GND (internal) Quad Core: Floating (internal)

@ JP1D

JP1D

VSS[001]

VSS[002]

A11

VSS[003]

A14

VSS[004]

A16

VSS[005]

A19

VSS[006]

A23

VSS[007]

AF2

VSS[008]

VSS[009]

VSS[010]

B11

VSS[011]

B13

VSS[012]

B16

VSS[013]

B19

VSS[014]

B21

VSS[015]

B24

VSS[016]

VSS[017]

VSS[018]

C11

VSS[019]

C14

VSS[020]

C16

VSS[021]

C19

VSS[022]

VSS[023]

C22

VSS[024]

C25

VSS[025]

VSS[026]

VSS[027]

VSS[028]

D11

VSS[029]

D13

VSS[030]

D16

VSS[031]

D19

VSS[032]

D23

VSS[033]

D26

VSS[034]

VSS[035]

VSS[036]

VSS[037]

E11

VSS[038]

E14

VSS[039]

E16

VSS[040]

E19

VSS[041]

E21

VSS[042]

E24

VSS[043]

VSS[044]

VSS[045]

F11

VSS[046]

F13

VSS[047]

F16

VSS[048]

F19

VSS[049]

VSS[050]

F22

VSS[051]

F25

VSS[052]

VSS[053]

VSS[054]

G23

VSS[055]

G26

VSS[056]

VSS[057]

VSS[058]

H21

VSS[059]

H24

VSS[060]

VSS[061]

VSS[062]

J22

VSS[063]

J25

VSS[064]

VSS[065]

VSS[066]

K23

VSS[067]

K26

VSS[068]

VSS[069]

VSS[070]

L21

VSS[071]

L24

VSS[072]

VSS[073]

VSS[074]

M22

VSS[075]

M25

VSS[076]

VSS[077]

VSS[078]

N23

VSS[079]

N26

VSS[080] VSS[081]P3VSS[162]

Penryn

VSS[082] VSS[083] VSS[084] VSS[085] VSS[086] VSS[087] VSS[088] VSS[089] VSS[090] VSS[091] VSS[092] VSS[093] VSS[094] VSS[095] VSS[096] VSS[097] VSS[098] VSS[099] VSS[100] VSS[101] VSS[102] VSS[103] VSS[104] VSS[105] VSS[106] VSS[107] VSS[108] VSS[109] VSS[110] VSS[111] VSS[112] VSS[113] VSS[114] VSS[115] VSS[116] VSS[117] VSS[118] VSS[119] VSS[120] VSS[121] VSS[122] VSS[123] VSS[124] VSS[125] VSS[126] VSS[127] VSS[128] VSS[129] VSS[130] VSS[131] VSS[132] VSS[133] VSS[134] VSS[135] VSS[136] VSS[137] VSS[138] VSS[139] VSS[140] VSS[141] VSS[142] VSS[143] VSS[144] VSS[145] VSS[146] VSS[147] VSS[148] VSS[149] VSS[150] VSS[151] VSS[152] VSS[153] VSS[154] VSS[155] VSS[156] VSS[157] VSS[158] VSS[159] VSS[160] VSS[161]

VSS[163]

P6 P21 P24 R2 R5 R22 R25 T1 T4 T23 T26 U3 U6 U21 U24 V2 V5 V22 V25 W1 W4 W23 W26 Y3 Y6 Y21 Y24 AA2 AA5 AA8 AA11 AA14 AA16 AA19 AA22 AA25 AB1 AB4 AB8 AB11 AB13 AB16 AB19 AB23 AB26 AC3 AC6 AC8 AC11 AC14 AC16 AC19 AC21 AC24 AD2 AD5 AD8 AD11 AD13 AD16 AD19 AD22 AD25 AE1 AE4 AE8 AE11 AE14 AE16 AE19 AE23 AE26 A2 AF6 AF8 AF11 AF13 AF16 AF19 AF21 A25 AF25

AA8 pin Reserved for QC

AC8 pin Reserved for QC

XDP_BPM2#3 <4>

For QC

A A

Security Classification

2008/10/1 2009/10/1

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2008/10/1 2009/10/1

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

SCHEMATICS,M/B A4161

401562 G

548Monday, February 23, 2009

VCC[068] VCC[069] VCC[070] VCC[071] VCC[072] VCC[073] VCC[074] VCC[075] VCC[076] VCC[077] VCC[078] VCC[079] VCC[080] VCC[081] VCC[082] VCC[083] VCC[084] VCC[085] VCC[086] VCC[087] VCC[088] VCC[089] VCC[090] VCC[091] VCC[092] VCC[093] VCC[094] VCC[095] VCC[096] VCC[097] VCC[098] VCC[099] VCC[100]

VCCP[01] VCCP[02] VCCP[03] VCCP[04] VCCP[05] VCCP[06] VCCP[07] VCCP[08] VCCP[09] VCCP[10] VCCP[11] VCCP[12] VCCP[13] VCCP[14] VCCP[15] VCCP[16]

VCCA[01] VCCA[02]

VID[0] VID[1] VID[2] VID[3] VID[4] VID[5] VID[6]

VCCSENSE

VSSSENSE

+CPU_CORE

330U_D2E_2.5VM_R7

AB20 AB7 AC7 AC9 AC12 AC13 AC15 AC17 AC18 AD7 AD9 AD10 AD12 AD14 AD15 AD17 AD18 AE9 AE10 AE12 AE13 AE15 AE17 AE18 AE20 AF9 AF10 AF12 AF14 AF15 AF17 AF18 AF20

G21 V6 J6 K6 M6 J21 K21 M21 N21 N6 R21 R6 T21 T6 V21 W21

B26 C26

AD6 AF5 AE5 AF4 AE3 AF3 AE2

AF7

AE7

VCCSENSE

Near CPU CORE regulator

ESR <= 1.5m ohm Capacitor > 1980uF

D D

+CPU_CORE +CPU_CORE

C C

BR1#

B B

AA10 AA12 AA13 AA15 AA17 AA18 AA20

AC10 AB10 AB12 AB14 AB15 AB17 AB18

A10 A12 A13 A15 A17 A18 A20

B10 B12 B14 B15 B17 B18 B20

C10 C12 C13 C15 C17 C18

D10 D12 D14 D15 D17 D18

E10 E12 E13 E15 E17 E18 E20

F10 F12 F14 F15 F17 F18 F20 AA7 AA9

AB9

A7 A9

B7 B9

E7 E9

F7 F9

@ JP1C

JP1C

VCC[001] VCC[002] VCC[003] VCC[004] VCC[005] VCC[006] VCC[007] VCC[008] VCC[009] VCC[010] VCC[011] VCC[012] VCC[013] VCC[014] VCC[015] VCC[016] VCC[017] VCC[018] VCC[019] VCC[020] VCC[021] VCC[022] VCC[023] VCC[024] VCC[025] VCC[026] VCC[027] VCC[028] VCC[029] VCC[030] VCC[031] VCC[032] VCC[033] VCC[034] VCC[035] VCC[036] VCC[037] VCC[038] VCC[039] VCC[040] VCC[041] VCC[042] VCC[043] VCC[044] VCC[045] VCC[046] VCC[047] VCC[048] VCC[049] VCC[050] VCC[051] VCC[052] VCC[053] VCC[054] VCC[055] VCC[056] VCC[057] VCC[058] VCC[059] VCC[060] VCC[061] VCC[062] VCC[063] VCC[064] VCC[065] VCC[066] VCC[067]

Penryn

DVT-Delete C10 for Layout problem.

330U_D2E_2.5VM_R7

VCCSENSE

VSSSENSE

+1.05VS

VCCSENSE <42>

VSSSENSE <42>

C11

330U_D2E_2.5VM_R7

C44

C44 330U_D2E_2.5VM_R7

330U_D2E_2.5VM_R7

Near pin B26

CPU_VID0 <42> CPU_VID1 <42> CPU_VID2 <42> CPU_VID3 <42> CPU_VID4 <42> CPU_VID5 <42> CPU_VID6 <42>

+CPU_CORE

R23100_0402_1% R23100_0402_1%

Place these capacitors on L8 (North side,Secondary Layer)

Place these capacitors on L8 (Sorth side,Secondary Layer)

Mid Frequence Decoupling

Place these inside socket cavity on L8

+1.05VS

(North side Secondary)

C51

0.01U_0402_25V4Z

C45

0.1U_0402_16V4Z

C52

C52 10U_0805_10V4Z

10U_0805_10V4Z

+1.5VS

C46

0.1U_0402_16V4Z

+CPU_CORE

C12

C12 10U_0805_6.3V6M

10U_0805_6.3V6M

C20

C20 10U_0805_6.3V6M

10U_0805_6.3V6M

C28

C28 10U_0805_6.3V6M

10U_0805_6.3V6M

C36

C36 10U_0805_6.3V6M

10U_0805_6.3V6M

C47

0.1U_0402_16V4Z

C13

C13 10U_0805_6.3V6M

10U_0805_6.3V6M

C21

C21 10U_0805_6.3V6M

10U_0805_6.3V6M

C29

C29 10U_0805_6.3V6M

10U_0805_6.3V6M

C37

C37 10U_0805_6.3V6M

10U_0805_6.3V6M

C48

0.1U_0402_16V4Z

C14

C14 10U_0805_6.3V6M

10U_0805_6.3V6M

C22

C22 10U_0805_6.3V6M

10U_0805_6.3V6M

C30

C30 10U_0805_6.3V6M

10U_0805_6.3V6M

C38

C38 10U_0805_6.3V6M

10U_0805_6.3V6M

C49

0.1U_0402_16V4Z

C15

C15 10U_0805_6.3V6M

10U_0805_6.3V6M

C23

C23 10U_0805_6.3V6M

10U_0805_6.3V6M

C31

C31 10U_0805_6.3V6M

10U_0805_6.3V6M

C39

C39 10U_0805_6.3V6M

10U_0805_6.3V6M

C50

0.1U_0402_16V4Z

C16

C16 10U_0805_6.3V6M

10U_0805_6.3V6M

C24

C24 10U_0805_6.3V6M

10U_0805_6.3V6M

C32

C32 10U_0805_6.3V6M

10U_0805_6.3V6M

C40

C40 10U_0805_6.3V6M

10U_0805_6.3V6M

C17

C17 10U_0805_6.3V6M

10U_0805_6.3V6M

C25

C25 10U_0805_6.3V6M

10U_0805_6.3V6M

C33

C33 10U_0805_6.3V6M

10U_0805_6.3V6M

C41

C41 10U_0805_6.3V6M

10U_0805_6.3V6M

C18

C18 10U_0805_6.3V6M

10U_0805_6.3V6M

C26

C26 10U_0805_6.3V6M

10U_0805_6.3V6M

C34

C34 10U_0805_6.3V6M

10U_0805_6.3V6M

C42

C42 10U_0805_6.3V6M

10U_0805_6.3V6M

C19

C19 10U_0805_6.3V6M

10U_0805_6.3V6M

C27

C27 10U_0805_6.3V6M

10U_0805_6.3V6M

C35

C35 10U_0805_6.3V6M

10U_0805_6.3V6M

C43

C43 10U_0805_6.3V6M

10U_0805_6.3V6M

VSSSENSE

A A

Close to CPU pin

R24100_0402_1% R24100_0402_1%

within 500mils.

Security Classification

Length match within 25 mils. The trace width/space/other is 20/7/25.

Security Classification

2008/10/1 2009/10/1

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2008/10/1 2009/10/1

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

SCHEMATICS,M/B A4161

401562 G

648Monday, February 23, 2009

U3A

H_D#[0..63]<5>

D D

C C

Layout Note: H_RCOMP / H_VREF / H_SWNG

trace width and spacing is 10/20

within 100 mils from NB

+1.05VS+1.05VS

B B

R25

R25 1K_0402_1%

1K_0402_1%

R27

R27 2K_0402_1%

2K_0402_1%

C53

0.1U_0402_16V4Z

H_RCOMP +H_SWNG+H_VREF

R28

24.9_0402_1%

R26

R26 221_0402_1%

221_0402_1%

R29

R29 100_0402_1%

100_0402_1%

C54

0.1U_0402_16V4Z

H_RESET#<4>

H_CPUSLP#<5>

Near B3 pin

H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31 H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63

+H_SWNG H_RCOMP

+H_VREF

U3A

H_D#_0

H_D#_1

H_D#_2

H_D#_3

H_D#_4

H_D#_5

H_D#_6

H_D#_7

H_D#_8

H_D#_9

H_D#_10

M11

H_D#_11

H_D#_12

H_D#_13

N12

H_D#_14

H_D#_15

H_D#_16

H_D#_17

H_D#_18

H_D#_19

H_D#_20

H_D#_21

H_D#_22

H_D#_23

H_D#_24

H_D#_25

H_D#_26

P13

H_D#_27

H_D#_28

H_D#_29

N10

H_D#_30

H_D#_31

H_D#_32

AD14

H_D#_33

H_D#_34

Y10

H_D#_35

Y12

H_D#_36

Y14

H_D#_37

H_D#_38

H_D#_39

AA8

H_D#_40

H_D#_41

AA13

H_D#_42

AA9

H_D#_43

AA11

H_D#_44

AD11

H_D#_45

AD10

H_D#_46

AD13

H_D#_47

AE12

H_D#_48

AE9

H_D#_49

AA2

H_D#_50

AD8

H_D#_51

AA3

H_D#_52

AD3

H_D#_53

AD7

H_D#_54

AE14

H_D#_55

AF3

H_D#_56

AC1

H_D#_57

AE3

H_D#_58

AC3

H_D#_59

AE11

H_D#_60

AE8

H_D#_61

AG2

H_D#_62

AD6

H_D#_63

H_SWING

H_RCOMP

C12

H_CPURST#

E11

H_CPUSLP#

A11

H_AVREF

B11

H_DVREF

CANTIGA ES_FCBGA1329

GMR3@

H_ADSTB#_0 H_ADSTB#_1

H_BREQ#

H_DEFER#

HOST

H_DBSY#

HPLL_CLK

HPLL_CLK#

H_DPWR#

H_DRDY#

H_HITM# H_LOCK# H_TRDY#

H_DINV#_0 H_DINV#_1 H_DINV#_2 H_DINV#_3

H_DSTBN#_0 H_DSTBN#_1 H_DSTBN#_2 H_DSTBN#_3

H_DSTBP#_0 H_DSTBP#_1 H_DSTBP#_2 H_DSTBP#_3

H_REQ#_0 H_REQ#_1 H_REQ#_2 H_REQ#_3 H_REQ#_4

H_RS#_0

H_RS#_1

H_RS#_2

H_A#_3 H_A#_4 H_A#_5 H_A#_6 H_A#_7 H_A#_8

H_A#_9 H_A#_10 H_A#_11 H_A#_12 H_A#_13 H_A#_14 H_A#_15 H_A#_16 H_A#_17 H_A#_18 H_A#_19 H_A#_20 H_A#_21 H_A#_22 H_A#_23 H_A#_24 H_A#_25 H_A#_26 H_A#_27 H_A#_28 H_A#_29 H_A#_30 H_A#_31 H_A#_32 H_A#_33 H_A#_34 H_A#_35

H_ADS#

H_BNR# H_BPRI#

H_HIT#

A14 C15 F16 H13 C18 M16 J13 P16 R16 N17 M13 E17 P17 F17 G20 B19 J16 E20 H16 J20 L17 A17 B17 L16 C21 J17 H20 B18 K17 B20 F21 K21 L20

H12 B16 G17 A9 F11 G12 E9 B10 AH7 AH6 J11 F9 H9 E12 H11 C9

J8 L3 Y13 Y1

L10 M7 AA5 AE6

L9 M8 AA6 AE5

B15 K13 F13 B13 B14

B6 F12 C8

H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16 H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 H_A#32 H_A#33 H_A#34 H_A#35

CLK_MCH_BCLK CLK_MCH_BCLK#

H_A#[3..35] <4>

H_ADS# <4> H_ADSTB#0 <4> H_ADSTB#1 <4>

H_BNR# <4> H_BPRI# <4>

H_BR0# <4> H_DEFER# <4>

H_DBSY# <4> CLK_MCH_BCLK <16> CLK_MCH_BCLK# <16> H_DPWR# <5>

H_DRDY# <4> H_HIT# <4> H_HITM# <4> H_LOCK# <4> H_TRDY# <4>

H_DINV#0 <5> H_DINV#1 <5> H_DINV#2 <5> H_DINV#3 <5>

H_DSTBN#0 <5> H_DSTBN#1 <5> H_DSTBN#2 <5> H_DSTBN#3 <5>

H_DSTBP#0 <5> H_DSTBP#1 <5> H_DSTBP#2 <5> H_DSTBP#3 <5>

H_REQ#0 <4> H_REQ#1 <4> H_REQ#2 <4> H_REQ#3 <4> H_REQ#4 <4>

H_RS#0 <4> H_RS#1 <4> H_RS#2 <4>

A A

Security Classification

2008/10/1 2009/10/1

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2008/10/1 2009/10/1

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

SCHEMATICS,M/B A4161

401562 G

748Monday, February 23, 2009

Strap Pin Table

011 = FSB667

CFG[2:0]

CFG5 CFG6

D D

CFG7

CFG9 CFG10

CFG[13:12]

CFG16 CFG19

CFG20

(PCIE/SDVO select)

C C

B B

+3VS

A A

1 2

R67 10K_0402_5%R67 10K_0402_5%

010 = FSB800 000 = FSB1067

0 = DMI x 2 1 = DMI x 4

0 = iTPM Host Interface is enabled

1 = iTPM Host Interface is Disabled 0 = Intel Management Engine Crypto Transport Layer Security

(TLS) cipher suite with no confidentiality 1 = Intel Management Engine Crypto TLS cipher suite with

confidentiality 0 = Lane Reversal Enable

0 = PCIe Loopback Enable 1 = Disable

01 = All Z Mode Enabled 00 = Reserved 10 = XOR Mode Enabled 11 = Normal Operation

0 = Dynamic ODT Disabled 1 = Dynamic ODT Enabled

0 = Normal Operation 1 = DMI Lane Reversal Enable

0 = Only PCIE or SDVO is operational.

(Default)

(Default) - can support disble by SW.

(Default)1 = Normal Operation

(Default)

1 = PCIE/SDVO are operating simu.

R44 1K_0402_5%R44 1K_0402_5% R45 1K_0402_5%R45 1K_0402_5% R46 1K_0402_5%R46 1K_0402_5%

R47 2.21K_0402_1%@R47 2.21K_0402_1%@ R49 2.21K_0402_1%@R49 2.21K_0402_1%@ R51 2.21K_0402_1%@R51 2.21K_0402_1%@

R53 2.21K_0402_1%@R53 2.21K_0402_1%@ R55 2.21K_0402_1%@R55 2.21K_0402_1%@

R57 2.21K_0402_1%@R57 2.21K_0402_1%@ R59 2.21K_0402_1%@R59 2.21K_0402_1%@

R61 2.21K_0402_1%@R61 2.21K_0402_1%@

R62 4.02K_0402_1%@R62 4.02K_0402_1%@ R64 4.02K_0402_1%@R64 4.02K_0402_1%@

R66 0_0402_5%R66 0_0402_5%

R69 0_0402_5%R69 0_0402_5% R71 100_0402_5%R71 100_0402_5%

R72 0_0402_5%R72 0_0402_5% R73 0_0402_5%R73 0_0402_5%

GMCH_PWROK

1 2 1 2 1 2

1 2 1 2

1 2

1 2 1 2

1 2

1 2 1 2

PM_PWROK<22,32>

PM_EXTTS#_R

Use VGATE for GMCH_PWROK

VGATE<22,32,42>

PM_PWROK

CPU_BSEL0<5,16> CPU_BSEL1<5,16> CPU_BSEL2<5,16>

+3VS

PM_SYNC#<22>

PM_EXTTS#<14,15>

PLT_RST#<17,20,26..29,32,33> H_THERMTRIP#<4,21> PM_DPRSLPVR<22,42>

1 2

R75 0_0402_5%@R75 0_0402_5%@

1 2

R76 0_0402_5%R76 0_0402_5%

U3B

M36

RSVD1

N36

RSVD2

R33

RSVD3

T33

RSVD4

AH9

RSVD5

AH10

RSVD6

AH12

RSVD7

AH13

RSVD8

K12

RSVD9

AL34

RSVD10

AK34

RSVD11

AN35

RSVD12

AM35

RSVD13

T24

RSVD14

B31

RSVD15

RSVD16

RSVD17

AY21

RSVD20

BG23

RSVD22

BF23

RSVD23

BH18

RSVD24

BF18

RSVD25

MCH_CLKSEL0 MCH_CLKSEL1 MCH_CLKSEL2

MCH_CFG_5 MCH_CFG_6 MCH_CFG_7

MCH_CFG_9 MCH_CFG_10

MCH_CFG_12 MCH_CFG_13

MCH_CFG_16

MCH_CFG_19 MCH_CFG_20

PM_SYNC#_R

PM_EXTTS#_R GMCH_PWROK MCH_RSTIN# NB_THERMTRIP# DPRSLPVR

12 12 12

H_DPRSTP#<5,21,42>

T25

CFG_0

R25

CFG_1

P25

CFG_2

P20

CFG_3

P24

CFG_4

C25

CFG_5

N24

CFG_6

M24

CFG_7

E21

CFG_8

C23

CFG_9

C24

CFG_10

N21

CFG_11

P21

CFG_12

T21

CFG_13

R20

CFG_14

M20

CFG_15

L21

CFG_16

H21

CFG_17

P29

CFG_18

R28

CFG_19

T28

CFG_20

R29

PM_SYNC#

PM_DPRSTP#

N33

PM_EXT_TS#_0

P32

PM_EXT_TS#_1

AT40

PWROK

AT11

RSTIN#

T20

THERMTRIP#

R32

DPRSLPVR

BG48

NC_1

BF48

NC_2

BD48

NC_3

BC48

NC_4

BH47

NC_5

BG47

NC_6

BE47

NC_7

BH46

NC_8

BF46

NC_9

BG45

NC_10

BH44

NC_11

BH43

NC_12

BH6

NC_13

BH5

NC_14

BG4

NC_15

BH3

NC_16

BF3

NC_17

BH2

NC_18

BG2

NC_19

BE2

NC_20

BG1

NC_21

BF1

NC_22

BD1

NC_23

BC1

NC_24

NC_25

A47

NC_26

CANTIGA ES_FCBGA1329

CANTIGA ES_FCBGA1329 GMR3@

GMR3@

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

RSVD CFG PM NC

DDR CLK/ CONTROL/ COMPENSATIONHDA

DPLL_REF_SSCLK#

CLKDMIGRAPHICS VIDMEMISC

AP24

SA_CK_0

AT21

SA_CK_1

AV24

SB_CK_0

AU20

SB_CK_1

AR24

SA_CK#_0

AR21

SA_CK#_1

AU24

SB_CK#_0

AV20

SB_CK#_1

BC28

SA_CKE_0

AY28

SA_CKE_1

AY36

SB_CKE_0

BB36

SB_CKE_1

BA17

SA_CS#_0

AY16

SA_CS#_1

AV16

SB_CS#_0

AR13

SB_CS#_1

BD17

SA_ODT_0

AY17

SA_ODT_1

BF15

SB_ODT_O

AY13

SB_ODT_1

SM_RCOMP

SM_RCOMP#

SM_RCOMP_VOH

SM_RCOMP_VOL

SM_VREF

SM_PWROK

SM_REXT

SM_DRAMRST#

DPLL_REF_CLK

DPLL_REF_CLK#

DPLL_REF_SSCLK

PEG_CLK

PEG_CLK#

DMI_RXN_0 DMI_RXN_1 DMI_RXN_2 DMI_RXN_3

DMI_RXP_0 DMI_RXP_1 DMI_RXP_2 DMI_RXP_3

DMI_TXN_0 DMI_TXN_1 DMI_TXN_2 DMI_TXN_3

DMI_TXP_0 DMI_TXP_1 DMI_TXP_2 DMI_TXP_3

GFX_VID_0 GFX_VID_1 GFX_VID_2 GFX_VID_3 GFX_VID_4

GFX_VR_EN

CL_CLK

CL_DATA

CL_PWROK

CL_RST# CL_VREF

DDPC_CTRLCLK

DDPC_CTRLDATA

SDVO_CTRLCLK

SDVO_CTRLDATA

CLKREQ#

ICH_SYNC#

TSATN#

HDA_BCLK HDA_RST#

HDA_SDI

HDA_SDO

HDA_SYNC

2008/10/1 2009/10/1

SMRCOMP

BG22

SMRCOMP#

BH21

+SM_RCOMP_VOH

BF28

+SM_RCOMP_VOL

BH28

+SM_VREF

AV42

SM_PWROK

AR36

SM_REXT

BF17 BC36

CLK_DREF_96M

B38

CLK_DREF_96M#

A38

CLK_DREF_SSC

E41

CLK_DREF_SSC#

F41

CLK_MCH_3GPLL

F43

CLK_MCH_3GPLL#

E43

AE41 AE37 AE47 AH39

AE40 AE38 AE48 AH40

AE35 AE43 AE46 AH42

AD35 AE44 AF46 AH43

B33 B32 G33 F33 E33

C34

AH37 AH36 AN36 AJ35 AH34

N28 M28 G36 E36 K36 H36

B12

B28 B30 B29 C29 A28

+NB_CLVREF

0.1U_0402_16V4Z

PM_PWROK

+NB_CLVREF

+NB_CLVREF=0.355V

SDVO_SCLK SDVO_SDATA CLKREQ_3GPLL#

MCH_TSATN#

AZ_SDIN2_MCH_R

Compal Secret Data

DDRA_CLK0 <14> DDRA_CLK1 <14> DDRB_CLK0 <15> DDRB_CLK1 <15>

DDRA_CLK0# <14> DDRA_CLK1# <14> DDRB_CLK0# <15> DDRB_CLK1# <15>

DDRA_CKE0 <14> DDRA_CKE1 <14> DDRB_CKE0 <15> DDRB_CKE1 <15>

DDRA_SCS0# <14> DDRA_SCS1# <14> DDRB_SCS0# <15> DDRB_SCS1# <15>

DDRA_ODT0 <14> DDRA_ODT1 <14> DDRB_ODT0 <15> DDRB_ODT1 <15>

R33 80.6_0402_1%R33 80.6_0402_1%

1 2

R34 80.6_0402_1%R34 80.6_0402_1%

1 2

R37 0_0402_5%R37 0_0402_5%

1 2

R38 499_0402_1%R38 499_0402_1%

1 2

CLK_DREF_96M <16> CLK_DREF_96M# <16> CLK_DREF_SSC <16> CLK_DREF_SSC# <16>

CLK_MCH_3GPLL <16> CLK_MCH_3GPLL# <16>

DMI_ITX_MRX_N0 <20> DMI_ITX_MRX_N1 <20> DMI_ITX_MRX_N2 <20> DMI_ITX_MRX_N3 <20>

DMI_ITX_MRX_P0 <20> DMI_ITX_MRX_P1 <20> DMI_ITX_MRX_P2 <20> DMI_ITX_MRX_P3 <20>

DMI_MTX_IRX_N0 <20> DMI_MTX_IRX_N1 <20> DMI_MTX_IRX_N2 <20> DMI_MTX_IRX_N3 <20>

DMI_MTX_IRX_P0 <20> DMI_MTX_IRX_P1 <20> DMI_MTX_IRX_P2 <20> DMI_MTX_IRX_P3 <20>

CL_VREF should be

0.35 V

C60

CL_CLK0 <22> CL_DATA0 <22>

CL_RST#0 <22>

SDVO_SCLK <19> SDVO_SDATA <19>

CLKREQ_3GPLL# <16>

MCH_ICH_SYNC# <22>

AZ_BITCLK_MCH <21> AZ_RST_MCH# <21>

AZ_SDOUT_MCH <21> AZ_SYNC_MCH <21>

Deciphered Date

+1.05VS

1 2

20mil

R74

1K_0402_1%

R77

499_0402_1%

1 2

+SM_RCOMP_VOH

0.01U_0402_25V4Z

SM_DRAMRST# would be needed for DDR3 only

For Cantiga 80 Ohm

+1.8V

C59

0.1U_0402_16V4Z

CLK_DREF_96M CLK_DREF_96M# CLK_DREF_SSC CLK_DREF_SSC#

+1.8V

0.01U_0402_25V4Z

+SM_RCOMP_VOL

0.01U_0402_25V4Z

R35

R35 1K_0402_1%

1K_0402_1%

1 2

R39

R39 1K_0402_1%

1K_0402_1%

1 2

R40 0_0402_5%PM@R40 0_0402_5%PM@

1 2

R41 0_0402_5%PM@R41 0_0402_5%PM@

1 2

R42 0_0402_5%PM@R42 0_0402_5%PM@

1 2

R43 0_0402_5%PM@R43 0_0402_5%PM@

1 2

as close as possible to the related balls

Strap Pin Table

0 = No SDVO Card Present 1 = SDVO Card Present

0 = Digital DisplayPort Disable 1 = Digital DisplayPort Device Present

SDVO_SCLK

R79

SDVO_SDATA

R80

+1.05VS

R81

1K_0402_5%

3 1

MMBT3904_NL_SOT23-3

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

SCHEMATICS,M/B A4161

R84

33_0402_5%

33_0402_5% IHDMI@

IHDMI@

SDVO_CTRLDATA

54.9_0402_1%

MCH_TSATN#

AZ_SDIN2_MCH <21>

R83

+1.8V

R30

1K_0402_1%

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M C56

2.2K_0402_5%

GM@R79

GM@

2.2K_0402_5%

IHDMI@R80

IHDMI@

PM@R79

PM@

PM@R80

PM@

R82

R82 1K_0402_5%

1K_0402_5%

C56

3.01K_0402_1%

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M C58

C58

MCH_TSATN_EC# <32>

C55

C57

R79

0_0402_5%

R80

0_0402_5%

+3VS

401562 G

1K_0402_1%

R135

1 2

0_0402_5%

1 2

R134 0_0402_5%

0_0402_5%

848Monday, February 23, 2009

R31

R32

(Default)

(Default)DDPC_CTRLDATA

GM@R135

GM@

PM@R134

PM@

+3VS

D D

DDR_A_D[0..63]<14>

C C

B B

DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15 DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63

U3D

AJ38

SA_DQ_0

AJ41

SA_DQ_1

AN38

SA_DQ_2

AM38

SA_DQ_3

AJ36

SA_DQ_4

AJ40

SA_DQ_5

AM44

SA_DQ_6

AM42

SA_DQ_7

AN43

SA_DQ_8

AN44

SA_DQ_9

AU40

SA_DQ_10

AT38

SA_DQ_11

AN41

SA_DQ_12

AN39

SA_DQ_13

AU44

SA_DQ_14

AU42

SA_DQ_15

AV39

SA_DQ_16

AY44

SA_DQ_17

BA40

SA_DQ_18

BD43

SA_DQ_19

AV41

SA_DQ_20

AY43

SA_DQ_21

BB41

SA_DQ_22

BC40

SA_DQ_23

AY37

SA_DQ_24

BD38

SA_DQ_25

AV37

SA_DQ_26

AT36

SA_DQ_27

AY38

SA_DQ_28

BB38

SA_DQ_29

AV36

SA_DQ_30

AW36

SA_DQ_31

BD13

SA_DQ_32

AU11

SA_DQ_33

BC11

SA_DQ_34

BA12

SA_DQ_35

AU13

SA_DQ_36

AV13

SA_DQ_37

BD12

SA_DQ_38

BC12

SA_DQ_39

BB9

SA_DQ_40

BA9

SA_DQ_41

AU10

SA_DQ_42

AV9

SA_DQ_43

BA11

SA_DQ_44

BD9

SA_DQ_45

AY8

SA_DQ_46

BA6

SA_DQ_47

AV5

SA_DQ_48

AV7

SA_DQ_49

AT9

SA_DQ_50

AN8

SA_DQ_51

AU5

SA_DQ_52

AU6

SA_DQ_53

AT5

SA_DQ_54

AN10

SA_DQ_55

AM11

SA_DQ_56

AM5

SA_DQ_57

AJ9

SA_DQ_58

AJ8

SA_DQ_59

AN12

SA_DQ_60

AM13

SA_DQ_61

AJ11

SA_DQ_62

AJ12

SA_DQ_63

CANTIGA ES_FCBGA1329

CANTIGA ES_FCBGA1329 GMR3@

GMR3@

DDR SYSTEM MEMORY A

SA_BS_0 SA_BS_1 SA_BS_2

SA_RAS# SA_CAS#

SA_WE#

SA_DM_0 SA_DM_1 SA_DM_2 SA_DM_3 SA_DM_4 SA_DM_5 SA_DM_6 SA_DM_7

SA_DQS_0 SA_DQS_1 SA_DQS_2 SA_DQS_3 SA_DQS_4 SA_DQS_5 SA_DQS_6 SA_DQS_7

SA_DQS#_0 SA_DQS#_1 SA_DQS#_2 SA_DQS#_3 SA_DQS#_4 SA_DQS#_5 SA_DQS#_6 SA_DQS#_7

SA_MA_0 SA_MA_1 SA_MA_2 SA_MA_3 SA_MA_4 SA_MA_5 SA_MA_6 SA_MA_7 SA_MA_8

SA_MA_9 SA_MA_10 SA_MA_11 SA_MA_12 SA_MA_13 SA_MA_14

BD21 BG18 AT25

BB20 BD20 AY20

AM37 AT41 AY41 AU39 BB12 AY6 AT7 AJ5

AJ44 AT44 BA43 BC37 AW12 BC8 AU8 AM7

AJ43 AT43 BA44 BD37 AY12 BD8 AU9 AM8

BA21 BC24 BG24 BH24 BG25 BA24 BD24 BG27 BF25 AW24 BC21 BG26 BH26 BH17 AY25

DDR_A_DM0 DDR_A_DM1 DDR_A_DM2 DDR_A_DM3 DDR_A_DM4 DDR_A_DM5 DDR_A_DM6 DDR_A_DM7

DDR_A_DQS0 DDR_A_DQS1 DDR_A_DQS2 DDR_A_DQS3 DDR_A_DQS4 DDR_A_DQS5 DDR_A_DQS6 DDR_A_DQS7

DDR_A_DQS#0 DDR_A_DQS#1 DDR_A_DQS#2 DDR_A_DQS#3 DDR_A_DQS#4 DDR_A_DQS#5 DDR_A_DQS#6 DDR_A_DQS#7

DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8

DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 DDR_A_MA14

DDR_A_BS0 <14> DDR_A_BS1 <14> DDR_A_BS2 <14>

DDR_A_RAS# <14> DDR_A_CAS# <14> DDR_A_WE# <14>

DDR_A_DM[0..7] <14>

DDR_A_DQS[0..7] <14>

DDR_A_DQS#[0..7] <14>

DDR_A_MA[0..14] <14>

DDR_B_D[0..63]<15>

DDR_B_D0 DDR_B_D1 DDR_B_D2 DDR_B_D3 DDR_B_D4 DDR_B_D5 DDR_B_D6 DDR_B_D7 DDR_B_D8 DDR_B_D9 DDR_B_D10 DDR_B_D11 DDR_B_D12 DDR_B_D13 DDR_B_D14 DDR_B_D15 DDR_B_D16 DDR_B_D17 DDR_B_D18 DDR_B_D19 DDR_B_D20 DDR_B_D21 DDR_B_D22 DDR_B_D23 DDR_B_D24 DDR_B_D25 DDR_B_D26 DDR_B_D27 DDR_B_D28 DDR_B_D29 DDR_B_D30 DDR_B_D31 DDR_B_D32 DDR_B_D33 DDR_B_D34 DDR_B_D35 DDR_B_D36 DDR_B_D37 DDR_B_D38 DDR_B_D39 DDR_B_D40 DDR_B_D41 DDR_B_D42 DDR_B_D43 DDR_B_D44 DDR_B_D45 DDR_B_D46 DDR_B_D47 DDR_B_D48 DDR_B_D49 DDR_B_D50 DDR_B_D51 DDR_B_D52 DDR_B_D53 DDR_B_D54 DDR_B_D55 DDR_B_D56 DDR_B_D57 DDR_B_D58 DDR_B_D59 DDR_B_D60 DDR_B_D61 DDR_B_D62 DDR_B_D63

U3E

AK47 AH46 AP47 AP46

AJ46

AJ48 AM48 AP48 AU47 AU46 BA48 AY48 AT47 AR47 BA47 BC47 BC46 BC44 BG43

BF43 BE45 BC41

BF40

BF41 BG38

BF38 BH35 BG35 BH40 BG39 BG34 BH34 BH14 BG12 BH11

BG8

BH12

BF11

BF8 BG7 BC5 BC6

AY3

AY1

BF6

BF5

BA1 BD3

AV2 AU3 AR3 AN2

AY2

AV1

AP3 AR1

AL1

AL2

AJ1 AH1 AM2 AM3 AH3

AJ3

CANTIGA ES_FCBGA1329

CANTIGA ES_FCBGA1329 GMR3@

GMR3@

SB_DQ_0 SB_DQ_1 SB_DQ_2 SB_DQ_3 SB_DQ_4 SB_DQ_5 SB_DQ_6 SB_DQ_7 SB_DQ_8 SB_DQ_9 SB_DQ_10 SB_DQ_11 SB_DQ_12 SB_DQ_13 SB_DQ_14 SB_DQ_15 SB_DQ_16 SB_DQ_17 SB_DQ_18 SB_DQ_19 SB_DQ_20 SB_DQ_21 SB_DQ_22 SB_DQ_23 SB_DQ_24 SB_DQ_25 SB_DQ_26 SB_DQ_27 SB_DQ_28 SB_DQ_29 SB_DQ_30 SB_DQ_31 SB_DQ_32 SB_DQ_33 SB_DQ_34 SB_DQ_35 SB_DQ_36 SB_DQ_37 SB_DQ_38 SB_DQ_39 SB_DQ_40 SB_DQ_41 SB_DQ_42 SB_DQ_43 SB_DQ_44 SB_DQ_45 SB_DQ_46 SB_DQ_47 SB_DQ_48 SB_DQ_49 SB_DQ_50 SB_DQ_51 SB_DQ_52 SB_DQ_53 SB_DQ_54 SB_DQ_55 SB_DQ_56 SB_DQ_57 SB_DQ_58 SB_DQ_59 SB_DQ_60 SB_DQ_61 SB_DQ_62 SB_DQ_63

BC16

SB_BS_0

BB17

SB_BS_1

BB33

SB_BS_2

AU17

SB_RAS#

BG16

SB_CAS#

BF14

SB_WE#

DDR_B_DM0

AM47

SB_DM_0 SB_DM_1 SB_DM_2 SB_DM_3 SB_DM_4 SB_DM_5 SB_DM_6 SB_DM_7

SB_DQS_0 SB_DQS_1 SB_DQS_2 SB_DQS_3 SB_DQS_4 SB_DQS_5 SB_DQS_6 SB_DQS_7

SB_DQS#_0 SB_DQS#_1 SB_DQS#_2 SB_DQS#_3 SB_DQS#_4 SB_DQS#_5 SB_DQS#_6 SB_DQS#_7

SB_MA_0 SB_MA_1 SB_MA_2

DDR SYSTEM MEMORY B

SB_MA_3 SB_MA_4 SB_MA_5 SB_MA_6 SB_MA_7 SB_MA_8

SB_MA_9 SB_MA_10 SB_MA_11 SB_MA_12 SB_MA_13 SB_MA_14

AY47 BD40 BF35 BG11 BA3 AP1 AK2

AL47 AV48 BG41 BG37 BH9 BB2 AU1 AN6

AL46 AV47 BH41 BH37 BG9 BC2 AT2 AN5

AV17 BA25 BC25 AU25 AW25 BB28 AU28 AW28 AT33 BD33 BB16 AW33 AY33 BH15 AU33

DDR_B_DM1 DDR_B_DM2 DDR_B_DM3 DDR_B_DM4 DDR_B_DM5 DDR_B_DM6 DDR_B_DM7

DDR_B_DQS0 DDR_B_DQS1 DDR_B_DQS2 DDR_B_DQS3 DDR_B_DQS4 DDR_B_DQS5 DDR_B_DQS6 DDR_B_DQS7

DDR_B_DQS#0 DDR_B_DQS#1 DDR_B_DQS#2 DDR_B_DQS#3 DDR_B_DQS#4 DDR_B_DQS#5 DDR_B_DQS#6 DDR_B_DQS#7

DDR_B_MA0 DDR_B_MA1 DDR_B_MA2 DDR_B_MA3 DDR_B_MA4 DDR_B_MA5 DDR_B_MA6 DDR_B_MA7 DDR_B_MA8

DDR_B_MA9 DDR_B_MA10 DDR_B_MA11 DDR_B_MA12 DDR_B_MA13 DDR_B_MA14

DDR_B_BS0 <15> DDR_B_BS1 <15> DDR_B_BS2 <15>

DDR_B_RAS# <15> DDR_B_CAS# <15> DDR_B_WE# <15>

DDR_B_DM[0..7] <15>

DDR_B_DQS[0..7] <15>

DDR_B_DQS#[0..7] <15>

DDR_B_MA[0..14] <15>

A A

Security Classification

2008/10/1 2009/10/1

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2008/10/1 2009/10/1

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

SCHEMATICS,M/B A4161

401562 G

948Monday, February 23, 2009

LCTLA_CLK

GM@

+3VS

R132 0_0402_5%

0_0402_5%

R133 0_0402_5%

0_0402_5%

1 2

GM@R132

GM@

R86 10K_0402_5%

1 2

R88 10K_0402_5%

1 2

R89 2.2K_0402_5%

1 2

R90 2.2K_0402_5%

PM@R133

PM@

L_DDC_DATA

D D

1 = LFP Card Present; PCIE disable

C C

R92

PM@R92

PM@

0_0402_5%

R93

PM@R93

PM@

0_0402_5%

R94

PM@R94

PM@

0_0402_5%

R95

PM@R95

PM@

0_0402_5%

R96

PM@R96

PM@

0_0402_5%

R97

PM@R97

PM@

0_0402_5%

B B

0_0402_5%

R100

0_0402_5%

PM@R100

PM@

GM@

LCTLB_DATA

GM@

UMA_LCD_CLK

GM@

UMA_LCD_DAT

GM@

(Default)0 = LFP Disable

EVT2- Remove S-Vedio function.

1 2 1 2

UMA_TV_COMPS UMA_TV_LUMA UMA_TV_CRMA

UMA_CRT_CLK

UMA_CRT_DATA

UMA_CRT_HSYNC

UMA_CRT_VSYNC

R95 150_0402_1%GM@R95 150_0402_1%GM@ R96 150_0402_1%GM@R96 150_0402_1%GM@ R97 150_0402_1%GM@R97 150_0402_1%GM@

+3VS

1 2

R92 75_0402_1%GM@R92 75_0402_1%GM@

1 2

R93 75_0402_1%GM@R93 75_0402_1%GM@

1 2

R94 75_0402_1%GM@R94 75_0402_1%GM@

1 2 1 2 1 2

R98 4.7K_0402_5%GM@R98 4.7K_0402_5%GM@ R99 4.7K_0402_5%GM@R99 4.7K_0402_5%GM@

R101 0_0402_5%PM@R101 0_0402_5%PM@ R102 0_0402_5%PM@R102 0_0402_5%PM@

R86

PM@R86

PM@

0_0402_5%

R88

PM@R88

PM@

0_0402_5%

R89

PM@R89

PM@

0_0402_5%

R90

PM@R90

PM@

0_0402_5%

UMA_CRT_B UMA_CRT_G UMA_CRT_R

UMA_LCD_CLK<17> UMA_LCD_DAT<17>

GMCH_ENVDD<17>

UMA_TXOUT0-<17> UMA_TXOUT1-<17> UMA_TXOUT2-<17>

UMA_TXOUT0+<17> UMA_TXOUT1+<17> UMA_TXOUT2+<17>

UMA_TZOUT0-<17> UMA_TZOUT1-<17> UMA_TZOUT2-<17>

UMA_TZOUT0+<17> UMA_TZOUT1+<17> UMA_TZOUT2+<17>

Need to connect to GND if not used.

UMA_CRT_CLK<18> UMA_CRT_DATA<18>

UMA_CRT_HSYNC<18>

UMA_CRT_VSYNC<18>

UMA_ENBKL<32>

UMA_TXCLK-<17> UMA_TXCLK+<17> UMA_TZCLK-<17> UMA_TZCLK+<17>

UMA_CRT_B<18> UMA_CRT_G<18> UMA_CRT_R<18>

R91 2.37K_0402_1%GM@R91 2.37K_0402_1%GM@

R118 0_0402_5%GM@R118 0_0402_5%GM@ R126 0_0402_5%GM@R126 0_0402_5%GM@

R100 1.02K_0402_1%GM@R100 1.02K_0402_1%GM@

UMA_LCD_CLK UMA_LCD_DAT

1 2 1 2

1 2

UMA_TV_COMPS UMA_TV_LUMA UMA_TV_CRMA

UMA_CRT_B UMA_CRT_G UMA_CRT_R

UMA_CRT_CLK UMA_CRT_DATA UMA_CRT_HSYNC CRT_IREF

UMA_CRT_VSYNC

LCTLA_CLK LCTLB_DATA

LVDS_IBG

U3C

L32

L_BKLT_CTRL

G32

L_BKLT_EN

M32

L_CTRL_CLK

M33

L_CTRL_DATA

K33

L_DDC_CLK

J33

L_DDC_DATA

M29

L_VDD_EN

C44

LVDS_IBG

B43

LVDS_VBG

E37

LVDS_VREFH

E38

LVDS_VREFL

C41

LVDSA_CLK#

C40

LVDSA_CLK

B37

LVDSB_CLK#

A37

LVDSB_CLK

H47

LVDSA_DATA#_0

E46

LVDSA_DATA#_1

G40

LVDSA_DATA#_2

A40

LVDSA_DATA#_3

H48

LVDSA_DATA_0

D45

LVDSA_DATA_1

F40

LVDSA_DATA_2

B40

LVDSA_DATA_3

A41

LVDSB_DATA#_0

H38

LVDSB_DATA#_1

G37

LVDSB_DATA#_2

J37

LVDSB_DATA#_3

B42

LVDSB_DATA_0

G38

LVDSB_DATA_1

F37

LVDSB_DATA_2

K37

LVDSB_DATA_3

F25

TVA_DAC

H25

TVB_DAC

K25

TVC_DAC

H24

TV_RTN

C31

TV_DCONSEL_0

E32

TV_DCONSEL_1

E28

CRT_BLUE

G28

CRT_GREEN

J28

CRT_RED

G29

CRT_IRTN

H32

CRT_DDC_CLK

J32

CRT_DDC_DATA

J29

CRT_HSYNC

E29

CRT_TVO_IREF

L29

CRT_VSYNC

CANTIGA ES_FCBGA1329

CANTIGA ES_FCBGA1329 GMR3@

GMR3@

10mils

PEG_COMP

PEG_RX_0 PEG_RX_1 PEG_RX_2 PEG_RX_3 PEG_RX_4 PEG_RX_5 PEG_RX_6 PEG_RX_7 PEG_RX_8 PEG_RX_9

PEG_TX_0 PEG_TX_1 PEG_TX_2 PEG_TX_3 PEG_TX_4 PEG_TX_5 PEG_TX_6 PEG_TX_7 PEG_TX_8 PEG_TX_9

T37 T36

PCIE_GTX_C_MRX_N0

H44

PCIE_GTX_C_MRX_N1

J46

PCIE_GTX_C_MRX_N2

L44

PCIE_GTX_C_MRX_N3

L40

PCIE_GTX_C_MRX_N4

N41

PCIE_GTX_C_MRX_N5

P48

PCIE_GTX_C_MRX_N6

N44

PCIE_GTX_C_MRX_N7

T43

PCIE_GTX_C_MRX_N8

U43

PCIE_GTX_C_MRX_N9

Y43

PCIE_GTX_C_MRX_N10

Y48

PCIE_GTX_C_MRX_N11

Y36

PCIE_GTX_C_MRX_N12

AA43

PCIE_GTX_C_MRX_N13

AD37

PCIE_GTX_C_MRX_N14

AC47

PCIE_GTX_C_MRX_N15

AD39

PCIE_GTX_C_MRX_P0

H43

PCIE_GTX_C_MRX_P1

J44

PCIE_GTX_C_MRX_P2

L43

PCIE_GTX_C_MRX_P3

L41

PCIE_GTX_C_MRX_P4

N40

PCIE_GTX_C_MRX_P5

P47

PCIE_GTX_C_MRX_P6

N43

PCIE_GTX_C_MRX_P7

T42

PCIE_GTX_C_MRX_P8

U42

PCIE_GTX_C_MRX_P9

Y42

PCIE_GTX_C_MRX_P10

W47

PCIE_GTX_C_MRX_P11

Y37

PCIE_GTX_C_MRX_P12

AA42

PCIE_GTX_C_MRX_P13

AD36

PCIE_GTX_C_MRX_P14

AC48

PCIE_GTX_C_MRX_P15

AD40

PCIE_MTX_GRX_N0

J41

PCIE_MTX_GRX_N1

M46

PCIE_MTX_GRX_N2

M47

PCIE_MTX_GRX_N3

M40

PCIE_MTX_GRX_N4

M42

PCIE_MTX_GRX_N5

R48

PCIE_MTX_GRX_N6

N38

PCIE_MTX_GRX_N7

T40

PCIE_MTX_GRX_N8

U37

PCIE_MTX_GRX_N9

U40

PCIE_MTX_GRX_N10

Y40

PCIE_MTX_GRX_N11

AA46

PCIE_MTX_GRX_N12

AA37

PCIE_MTX_GRX_N13

AA40

PCIE_MTX_GRX_N14

AD43

PCIE_MTX_GRX_N15

AC46

PCIE_MTX_GRX_P0

J42

PCIE_MTX_GRX_P1

L46

PCIE_MTX_GRX_P2

M48

PCIE_MTX_GRX_P3

M39

PCIE_MTX_GRX_P4

M43

PCIE_MTX_GRX_P5

R47

PCIE_MTX_GRX_P6

N37

PCIE_MTX_GRX_P7

T39

PCIE_MTX_GRX_P8

U36

PCIE_MTX_GRX_P9

U39

PCIE_MTX_GRX_P10

Y39

PCIE_MTX_GRX_P11

Y46

PCIE_MTX_GRX_P12

AA36

PCIE_MTX_GRX_P13

AA39

PCIE_MTX_GRX_P14

AD42

PCIE_MTX_GRX_P15

AD46

PEG_COMPI

PEG_COMPO

PEG_RX#_0 PEG_RX#_1 PEG_RX#_2 PEG_RX#_3 PEG_RX#_4 PEG_RX#_5 PEG_RX#_6 PEG_RX#_7 PEG_RX#_8 PEG_RX#_9

LVDS TV VGA

PEG_RX#_10 PEG_RX#_11 PEG_RX#_12 PEG_RX#_13 PEG_RX#_14 PEG_RX#_15

PEG_RX_10 PEG_RX_11 PEG_RX_12 PEG_RX_13 PEG_RX_14 PEG_RX_15

PEG_TX#_0 PEG_TX#_1 PEG_TX#_2 PEG_TX#_3 PEG_TX#_4 PEG_TX#_5 PEG_TX#_6 PEG_TX#_7 PEG_TX#_8

PCI-EXPRESS GRAPHICS

PEG_TX#_9 PEG_TX#_10 PEG_TX#_11 PEG_TX#_12 PEG_TX#_13 PEG_TX#_14 PEG_TX#_15

PEG_TX_10

PEG_TX_11

PEG_TX_12

PEG_TX_13

PEG_TX_14

PEG_TX_15

1 2

R87 49.9_0402_1%R87 49.9_0402_1%

C62 0.1U_0402_16V7KPMIHD@C62 0.1U_0402_16V7KPMIHD@

1 2

C64 0.1U_0402_16V7KPMIHD@C64 0.1U_0402_16V7KPMIHD@

1 2

C66 0.1U_0402_16V7KPM@C66 0.1U_0402_16V7KPM@

1 2

C68 0.1U_0402_16V7KPM@C68 0.1U_0402_16V7KPM@

1 2

C70 0.1U_0402_16V7KPM@C70 0.1U_0402_16V7KPM@

1 2

C72 0.1U_0402_16V7KPM@C72 0.1U_0402_16V7KPM@

1 2

C74 0.1U_0402_16V7KPM@C74 0.1U_0402_16V7KPM@

1 2

C76 0.1U_0402_16V7KPM@C76 0.1U_0402_16V7KPM@

1 2

C78 0.1U_0402_16V7KPMIHD@C78 0.1U_0402_16V7KPMIHD@

1 2

C80 0.1U_0402_16V7KPMIHD@C80 0.1U_0402_16V7KPMIHD@

1 2

C82 0.1U_0402_16V7KPM@C82 0.1U_0402_16V7KPM@

1 2

C84 0.1U_0402_16V7KPM@C84 0.1U_0402_16V7KPM@

1 2

C86 0.1U_0402_16V7KPM@C86 0.1U_0402_16V7KPM@

1 2

C88 0.1U_0402_16V7KPM@C88 0.1U_0402_16V7KPM@

1 2

C90 0.1U_0402_16V7KPM@C90 0.1U_0402_16V7KPM@

1 2

C92 0.1U_0402_16V7KPM@C92 0.1U_0402_16V7KPM@

1 2

+1.05VS

PCIE_MTX_C_GRX_N[0..15] PCIE_MTX_C_GRX_P[0..15]

PCIE_GTX_C_MRX_N[0..15] PCIE_GTX_C_MRX_P[0..15]

C61 0.1U_0402_16V7KPMIHD@C61 0.1U_0402_16V7KPMIHD@

1 2

C63 0.1U_0402_16V7KPMIHD@C63 0.1U_0402_16V7KPMIHD@

1 2

C65 0.1U_0402_16V7KPM@C65 0.1U_0402_16V7KPM@

1 2

C67 0.1U_0402_16V7KPM@C67 0.1U_0402_16V7KPM@

1 2

C69 0.1U_0402_16V7KPM@C69 0.1U_0402_16V7KPM@

1 2

C71 0.1U_0402_16V7KPM@C71 0.1U_0402_16V7KPM@

1 2

C73 0.1U_0402_16V7KPM@C73 0.1U_0402_16V7KPM@

1 2

C75 0.1U_0402_16V7KPM@C75 0.1U_0402_16V7KPM@

1 2

C77 0.1U_0402_16V7KPMIHD@C77 0.1U_0402_16V7KPMIHD@

1 2

C79 0.1U_0402_16V7KPMIHD@C79 0.1U_0402_16V7KPMIHD@

1 2

C81 0.1U_0402_16V7KPM@C81 0.1U_0402_16V7KPM@

1 2

C83 0.1U_0402_16V7KPM@C83 0.1U_0402_16V7KPM@

1 2

C85 0.1U_0402_16V7KPM@C85 0.1U_0402_16V7KPM@

1 2

C87 0.1U_0402_16V7KPM@C87 0.1U_0402_16V7KPM@

1 2

C89 0.1U_0402_16V7KPM@C89 0.1U_0402_16V7KPM@

1 2

C91 0.1U_0402_16V7KPM@C91 0.1U_0402_16V7KPM@

1 2

PCIE_MTX_C_GRX_N[0..15] <17,19>

PCIE_MTX_C_GRX_P[0..15] <17,19> PCIE_GTX_C_MRX_N[0..15] <17> PCIE_GTX_C_MRX_P[0..15] <17,19>

PCIE_MTX_C_GRX_N0 PCIE_MTX_C_GRX_N1 PCIE_MTX_C_GRX_N2

PCIE_MTX_C_GRX_N3

PCIE_MTX_C_GRX_N4 PCIE_MTX_C_GRX_N5 PCIE_MTX_C_GRX_N6 PCIE_MTX_C_GRX_N7 PCIE_MTX_C_GRX_N8 PCIE_MTX_C_GRX_N9 PCIE_MTX_C_GRX_N10 PCIE_MTX_C_GRX_N11 PCIE_MTX_C_GRX_N12 PCIE_MTX_C_GRX_N13 PCIE_MTX_C_GRX_N14 PCIE_MTX_C_GRX_N15

PCIE_MTX_C_GRX_P0 PCIE_MTX_C_GRX_P1 PCIE_MTX_C_GRX_P2 PCIE_MTX_C_GRX_P3 PCIE_MTX_C_GRX_P4 PCIE_MTX_C_GRX_P5 PCIE_MTX_C_GRX_P6 PCIE_MTX_C_GRX_P7 PCIE_MTX_C_GRX_P8 PCIE_MTX_C_GRX_P9 PCIE_MTX_C_GRX_P10 PCIE_MTX_C_GRX_P11 PCIE_MTX_C_GRX_P12 PCIE_MTX_C_GRX_P13 PCIE_MTX_C_GRX_P14 PCIE_MTX_C_GRX_P15

A A

Security Classification

2008/10/1 2009/10/1

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2008/10/1 2009/10/1

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

SCHEMATICS,M/B A4161

401562 G

10 48Monday, February 23, 2009

+1.8V

DDR PWR

D D

C96

330U_4V_M

C C

10U_0805_10V4Z

0317 change value

0.1U_0402_16V4Z

10U_0805_10V4Z

C94

C93

C95

Could be NC for DDR2 Board.

+NB_VCCAXG

220U_6.3V_M@

0.1U_0402_16V4Z

0.1U_0402_16V4Z C231

C231

Int. Graphic -- 8700mA

220U_6.3V_MGM@

C105

C104

C103

GM@

GM@ 10U_0805_10V4Z

10U_0805_10V4Z

C230

0.1U_0402_16V4Z

10U_0805_10V4Z

C106

C106 GM@

GM@

0.1U_0402_16V4Z

0.1U_0402_16V4Z C228

C228

C107

C107 GM@

GM@

1U_0402_6.3V4Z

C202

0.1U_0402_16V4Z

0.47U_0402_10V4Z

C108

C108 GM@

GM@

0.1U_0402_16V4Z

0.1U_0402_16V4Z C134

C134

C109

C109 GM@

GM@

0.1U_0402_16V4Z

C110

C110 GM@

GM@

Intel:AXG and AXG_NCTF -- 220U*2, ESR 15mOhm

B B

C106

0_0805_5%

PM@C106

PM@

DVT-R707 change to J3, and R693 and R697, change to J4 for power rating issue.

+1.05VS +NB_VCCAXG

112

JUMP_43X118@J4JUMP_43X118@

112

JUMP_43X39

T3PAD T3PAD T4PAD T4PAD

A A

U3F

3000mA

AP33

VCC_SM_1

AN33

VCC_SM_2

BH32

VCC_SM_3

BG32

VCC_SM_4

BF32

VCC_SM_5

BD32

VCC_SM_6

BC32

VCC_SM_7

BB32

VCC_SM_8

BA32

VCC_SM_9

AY32

VCC_SM_10

AW32

VCC_SM_11

AV32

VCC_SM_12

AU32

VCC_SM_13

AT32

VCC_SM_14

AR32

VCC_SM_15

AP32

VCC_SM_16

AN32

VCC_SM_17

BH31

VCC_SM_18

BG31

VCC_SM_19

BF31

VCC_SM_20

BG30

VCC_SM_21

BH29

VCC_SM_22

BG29

VCC_SM_23

BF29

VCC_SM_24

BD29

VCC_SM_25

BC29

VCC_SM_26

BB29

VCC_SM_27

BA29

VCC_SM_28

AY29

VCC_SM_29

AW29

VCC_SM_30

AV29

VCC_SM_31

AU29

VCC_SM_32

AT29

VCC_SM_33

AR29

VCC_SM_34

AP29

VCC_SM_35

BA36

VCC_SM_36/NC

BB24

VCC_SM_37/NC

BD16

VCC_SM_38/NC

BB21

VCC_SM_39/NC

AW16

VCC_SM_40/NC

AW13

VCC_SM_41/NC

AT13

VCC_SM_42/NC

6326.84mA

Y26

VCC_AXG_1

AE25

VCC_AXG_2

AB25

VCC_AXG_3

AA25

VCC_AXG_4

AE24

VCC_AXG_5

AC24

VCC_AXG_6

AA24

VCC_AXG_7

Y24

VCC_AXG_8

AE23

VCC_AXG_9

AC23

VCC_AXG_10

AB23

VCC_AXG_11

AA23

VCC_AXG_12

AJ21

VCC_AXG_13

AG21

VCC_AXG_14

AE21

VCC_AXG_15

AC21

VCC_AXG_16

AA21

VCC_AXG_17

Y21

VCC_AXG_18

AH20

VCC_AXG_19

AF20

VCC_AXG_20

AE20

VCC_AXG_21

AC20

VCC_AXG_22

AB20

VCC_AXG_23

AA20

VCC_AXG_24

T17

VCC_AXG_25

T16

VCC_AXG_26

AM15

VCC_AXG_27

AL15

VCC_AXG_28

AE15

VCC_AXG_29

AJ15

VCC_AXG_30

AH15

VCC_AXG_31

AG15

VCC_AXG_32

AF15

VCC_AXG_33

AB15

VCC_AXG_34

AA15

VCC_AXG_35

Y15

VCC_AXG_36

V15

VCC_AXG_37

U15

VCC_AXG_38

AN14

VCC_AXG_39

AM14

VCC_AXG_40

U14

VCC_AXG_41

T14

VCC_AXG_42

AJ14

VCC_AXG_SENSE

AH14

VSS_AXG_SENSE

CANTIGA ES_FCBGA1329

CANTIGA ES_FCBGA1329 GMR3@

GMR3@

VCC_AXG_NTCF_1 VCC_AXG_NCTF_2 VCC_AXG_NCTF_3 VCC_AXG_NCTF_4 VCC_AXG_NCTF_5 VCC_AXG_NCTF_6 VCC_AXG_NCTF_7 VCC_AXG_NCTF_8

VCC SM

VCC_AXG_NCTF_9 VCC_AXG_NCTF_10 VCC_AXG_NCTF_11 VCC_AXG_NCTF_12 VCC_AXG_NCTF_13 VCC_AXG_NCTF_14 VCC_AXG_NCTF_15 VCC_AXG_NCTF_16 VCC_AXG_NCTF_17 VCC_AXG_NCTF_18 VCC_AXG_NCTF_19 VCC_AXG_NCTF_20 VCC_AXG_NCTF_21 VCC_AXG_NCTF_22 VCC_AXG_NCTF_23 VCC_AXG_NCTF_24 VCC_AXG_NCTF_25 VCC_AXG_NCTF_26 VCC_AXG_NCTF_27 VCC_AXG_NCTF_28 VCC_AXG_NCTF_29 VCC_AXG_NCTF_30 VCC_AXG_NCTF_31 VCC_AXG_NCTF_32 VCC_AXG_NCTF_33 VCC_AXG_NCTF_34 VCC_AXG_NCTF_35 VCC_AXG_NCTF_36 VCC_AXG_NCTF_37 VCC_AXG_NCTF_38 VCC_AXG_NCTF_39 VCC_AXG_NCTF_40 VCC_AXG_NCTF_41 VCC_AXG_NCTF_42 VCC_AXG_NCTF_43

VCC GFX NCTF

VCC_AXG_NCTF_44 VCC_AXG_NCTF_45 VCC_AXG_NCTF_46 VCC_AXG_NCTF_47 VCC_AXG_NCTF_48 VCC_AXG_NCTF_49 VCC_AXG_NCTF_50 VCC_AXG_NCTF_51 VCC_AXG_NCTF_52

POWER

VCC_AXG_NCTF_53 VCC_AXG_NCTF_54 VCC_AXG_NCTF_55 VCC_AXG_NCTF_56 VCC_AXG_NCTF_57 VCC_AXG_NCTF_58 VCC_AXG_NCTF_59 VCC_AXG_NCTF_60

VCC GFX

VCC_SM_LF1 VCC_SM_LF2 VCC_SM_LF3 VCC_SM_LF4 VCC_SM_LF5 VCC_SM_LF6 VCC_SM_LF7

VCC SM LF

+NB_VCCAXG

Int. Graphic Core -- 8700mA

W28 V28 W26 V26 W25 V25 W24 V24 W23 V23 AM21 AL21 AK21 W21 V21 U21 AM20 AK20 W20 U20 AM19 AL19 AK19 AJ19 AH19 AG19 AF19 AE19 AB19 AA19 Y19 W19 V19 U19 AM17 AK17 AH17 AG17 AF17 AE17 AC17 AB17 Y17 W17 V17 AM16 AL16 AK16 AJ16 AH16 AG16 AF16 AE16 AC16 AB16 AA16 Y16 W16 V16 U16

VCCSM_LF1

AV44

VCCSM_LF2

BA37

VCCSM_LF3

AM40

VCCSM_LF4

AV21

VCCSM_LF5

AY5

VCCSM_LF6

AM10

VCCSM_LF7

BB13

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

0.1U_0402_16V4Z

0.1U_0402_16V4Z C111

C111

Issued Date

+1.05VS

NB Core

220U_6.3V_M

C101

220U_6.3V_M@

Intel: VCC -- 220U*2, ESR 12mOhm

C113

0.1U_0402_16V4Z

0.1U_0402_16V4Z 2

0.22U_0402_10V4Z

0.22U_0402_10V4Z C112

C112

2008/10/1 2009/10/1

0.22U_0402_10V4Z

C97

C102

10U_0805_10V4Z

C114

0.22U_0402_10V4Z

0.22U_0402_10V4Z 2

Compal Secret Data

C98

0.22U_0402_10V4Z

0.47U_0402_10V4Z

0.47U_0402_10V4Z C115

C115

Deciphered Date

0.1U_0402_16V4Z

C99

C116

1U_0402_6.3V4Z

C100

1U_0402_6.3V4Z

C117

U3G

AG34

VCC_1

AC34

VCC_2

AB34

VCC_3

AA34

VCC_4

Y34

VCC_5

V34

VCC_6

U34

VCC_7

AM33

VCC_8

AK33

VCC_9

AJ33

VCC_10

AG33

VCC_11

AF33

VCC_12

AE33

VCC_13

AC33

VCC_14

AA33

VCC_15

Y33

VCC_16

W33

VCC_17

V33

VCC_18

U33

VCC_19

AH28

VCC_20

AF28

VCC_21

AC28

VCC_22

AA28

VCC_23

AJ26

VCC_24

AG26

VCC_25

AE26

VCC_26

AC26

VCC_27

AH25

VCC_28

AG25

VCC_29

AF25

VCC_30

AG24

VCC_31

AJ23

VCC_32

AH23

VCC_33

AF23

VCC_34

T32

VCC_35

CANTIGA ES_FCBGA1329

CANTIGA ES_FCBGA1329 GMR3@

GMR3@

Extnal Graphic: 1210.34mA integrated Graphic: 1930.4mA

VCC CORE

POWER

+1.05VS

VCC_NCTF_1 VCC_NCTF_2 VCC_NCTF_3 VCC_NCTF_4 VCC_NCTF_5 VCC_NCTF_6 VCC_NCTF_7 VCC_NCTF_8

VCC_NCTF_9 VCC_NCTF_10 VCC_NCTF_11 VCC_NCTF_12 VCC_NCTF_13 VCC_NCTF_14 VCC_NCTF_15 VCC_NCTF_16 VCC_NCTF_17 VCC_NCTF_18 VCC_NCTF_19 VCC_NCTF_20 VCC_NCTF_21 VCC_NCTF_22 VCC_NCTF_23 VCC_NCTF_24 VCC_NCTF_25 VCC_NCTF_26 VCC_NCTF_27 VCC_NCTF_28

VCC NCTF

VCC_NCTF_29 VCC_NCTF_30 VCC_NCTF_31 VCC_NCTF_32 VCC_NCTF_33 VCC_NCTF_34 VCC_NCTF_35 VCC_NCTF_36 VCC_NCTF_37 VCC_NCTF_38 VCC_NCTF_39 VCC_NCTF_40 VCC_NCTF_41 VCC_NCTF_42 VCC_NCTF_43 VCC_NCTF_44

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

SCHEMATICS,M/B A4161

401562 G

AM32 AL32 AK32 AJ32 AH32 AG32 AE32 AC32 AA32 Y32 W32 U32 AM30 AL30 AK30 AH30 AG30 AF30 AE30 AC30 AB30 AA30 Y30 W30 V30 U30 AL29 AK29 AJ29 AH29 AG29 AE29 AC29 AA29 Y29 W29 V29 AL28 AK28 AL26 AK26 AK25 AK24 AK23

11 48Monday, February 23, 2009

+3VS_TVCRT_DACBG

+3VS

R103

GM@R103

GM@

BLM18PG181SN1D_0603

10U_0805_10V4Z

10U_FLC-453232-100K_0.25A_10%

D D

220U_6.3V_M@

FBMA-L11-160808-121LMT_0603

10U_0805_10V4Z

+1.5VS

C C

B B

C118

GM@ C118

GM@

R105

GM@R105

GM@

C132

R107

C136

PCIe&DMI

1 2

R110 0_0603_5%R110 0_0603_5%

0.1U_0402_16V4Z

+1.5VS

R119

R119 0_0603_5%

0_0603_5%

0.1U_0402_16V4Z

+1.05VS_DPLLA+1.05VS

10U_0805_10V4Z

C133

C124

GM@

0.1U_0402_16V4Z

C126

0.1U_0402_16V4Z

Pin AD1

+1.5VS_PEG_BG

C141

0.01U_0402_25V4Z

C162

+1.5VS_QDAC

C163

Pin AD48 Pin AA48

GM@

Pin F47

C138

C138 10U_0805_10V4Z

10U_0805_10V4Z

+1.5VS +1.5VS_HDA

0.1U_0402_16V4Z

Pin L28

+3VS_TVCRT_DACBG

R104

GM@R104

GM@

0_0603_5%

C119

GM@ C119

GM@

0.1U_0402_16V4Z

C124

PM@C124

PM@

0_0805_5%

R108

C139

R117

0_0402_5%

0_0402_5% IHDMI@

IHDMI@

C157

IHDMI@

C163

0_0402_5%

R109 0.5_0805_1%R109 0.5_0805_1%

Pin AE1

0.1U_0402_16V4Z

PCIe&DMI

HDMI's HDA

Pin A32

@C163

FBMA-L11-160808-121LMT_0603

1 2

+1.05VS_PEGPLL

0.1U_0402_16V4Z

1 2

+3VS_TVCRT_DAC

0.01U_0402_25V4Z

0.01U_0402_25V4Z 1

C120

C120 GM@

GM@

R106

10U_FLC-453232-100K_0.25A_10%

+1.05VS_MPLL+1.05VS+1.05VS_AHPLL+1.05VS

C127

Intel Errata.

+1.05VS +1.05VS_DHPLL

R121

1 2

0_0402_5%

0.1U_0402_16V4Z

+1.05VS

A A

BLM18PG121SN1D_0603

R123

1_0402_1%

PCIe&DMI

10U_0805_10V4Z

C174

C170

+1.05VS_PEGPLL

0.1U_0402_16V4Z

C173

Pin AF1

Pin AA47

+1.8V

CRT TV

C120

PM@C120

PM@

0_0402_5%

GM@R106

GM@

+3VS

0.1U_0402_16V4Z

R122

R122 0_0603_5%

0_0603_5%

0_0402_5%

+1.05VS_DPLLB+1.05VS

10U_0805_10V4Z

C125

GM@

0.1U_0402_16V4Z

+1.8V_TXLVDS

C137 1000P_0402_50V7K

1000P_0402_50V7K

GND to J47

+1.05VS

10U_0805_10V4Z

+3VS_TVDAC

R127

R127 0_0603_5%

0_0603_5% GM@

GM@

+1.5VS

0.01U_0402_25V4Z

0.01U_0402_25V4Z 1

C160

1U_0402_6.3V4Z

64.8mA

C135

GM@

LVDS

GM@C137

GM@

Pin J48

R112

1 2

0_0805_5%

C143

C143 220U_6.3V_M

220U_6.3V_M

R115

1 2

0_0603_5%

C150

C156

0.01U_0402_25V4Z

Pin B24

C161

+1.8V_LVDS

C172

Pin M38

0.1U_0402_16V4Z

C125

Pin L48

C137

0_0402_5%

10U_0805_10V4Z

C156

0_0402_5%

GM@C156

GM@

Pin M25

LVDS

Pin B27

+3VS_TVCRT_DACBG

0.01U_0402_25V4Z

0.01U_0402_25V4Z 1

C121

C122

GM@

PM@C125

PM@

0_0805_5%

+3VS_TVCRT_DACBG

PM@C137

PM@

DDR2

4.7U_0603_6.3V6K

C144

C145

DDR2

+1.05VS_A_SM_CK

0.1U_0402_16V4Z

C151

C152

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M 1

PM@C156

PM@

+1.05VS_PEGPLL

+1.8V_LVDS

+1.05VS_A_SM

+3VS_TVCRT_DAC

1U_0402_6.3V4Z

C122

PM@C122

C146

+3VS_TVDAC

Issued Date

PM@

0_0402_5%

720mA

U3H

73mA

B27

VCCA_CRT_DAC_1

A26

VCCA_CRT_DAC_2

2.68mA

A25

VCCA_DAC_BG

B25

VSSA_DAC_BG

F47

VCCA_DPLLA

L48

VCCA_DPLLB

AD1

VCCA_HPLL

13.2mA

AE1

VCCA_MPLL

J48

VCCA_LVDS

414uA

J47

VSSA_LVDS

AD48

VCCA_PEG_BG

50mA

AA48

VCCA_PEG_PLL

AR20

VCCA_SM_1

AP20

VCCA_SM_2

AN20

VCCA_SM_3

AR17

VCCA_SM_4

AP17

VCCA_SM_5

AN17

VCCA_SM_6

AT16

VCCA_SM_7

AR16

VCCA_SM_8

AP16

VCCA_SM_9

AP28

VCCA_SM_CK_1

AN28

VCCA_SM_CK_2

AP25

VCCA_SM_CK_3

AN25

VCCA_SM_CK_4

AN24

VCCA_SM_CK_5

AM28

VCCA_SM_CK_NCTF_1

AM26

VCCA_SM_CK_NCTF_2

AM25

VCCA_SM_CK_NCTF_3

AL25

VCCA_SM_CK_NCTF_4

AM24

VCCA_SM_CK_NCTF_5

AL24

VCCA_SM_CK_NCTF_6

AM23

VCCA_SM_CK_NCTF_7

AL23

VCCA_SM_CK_NCTF_8

B24

VCCA_TV_DAC_1

A24

VCCA_TV_DAC_2

A32

VCC_HDA

M25

VCCD_TVDAC

L28

VCCD_QDAC

AF1

VCCD_HPLL

60.31mA

AA47

VCCD_PEG_PLL

M38

VCCD_LVDS_1

L37

VCCD_LVDS_2

CANTIGA ES_FCBGA1329

CANTIGA ES_FCBGA1329 GMR3@

GMR3@

+1.05VS +3VS

CH751H-40PT_SOD323-2

2008/10/1 2009/10/1

24mA

139.2mA

26mA 26mA

TVA 24.15mA TVB 39.48mA TVX 24.15mA

50mA

58.67mA

48.363mA

157.2mA

HDA

50mA

D21

2 1

CRTPLLA LVDSA PEG

VTT

POWER

A SM

AXF

VCC_SM_CK_1 VCC_SM_CK_2 VCC_SM_CK_3 VCC_SM_CK_4

SM CK

VCC_TX_LVDS

A CK

105.3mA

1732mA

DMI PEG

VTTLF

LVDS D TV/CRT

R1006

1 2

10_0603_5%

Compal Secret Data

852mA64.8mA

VTT_1 VTT_2 VTT_3 VTT_4 VTT_5 VTT_6 VTT_7 VTT_8

VTT_9 VTT_10 VTT_11 VTT_12 VTT_13 VTT_14 VTT_15 VTT_16 VTT_17 VTT_18 VTT_19 VTT_20 VTT_21 VTT_22 VTT_23 VTT_24 VTT_25

VCC_AXF_1 VCC_AXF_2 VCC_AXF_3

VCC_HV_1 VCC_HV_2 VCC_HV_3

VCC_PEG_1 VCC_PEG_2 VCC_PEG_3 VCC_PEG_4 VCC_PEG_5

VCC_DMI_1 VCC_DMI_2 VCC_DMI_3 VCC_DMI_4

456mA

VTTLF1 VTTLF2 VTTLF3

Deciphered Date

U13 T13 U12 T12 U11 T11 U10 T10 U9 T9 U8 T8 U7 T7 U6 T6 U5 T5 V3 U3 V2 U2 T2 V1 U1

B22 B21 A21

BF21 BH20 BG20 BF20

K47

C35 B35 A35

V48 U48 V47 U47 U46

AH48 AF48 AH47 AG47

A8 L1 AB2

+NB_VTTLF1 +NB_VTTLF2 +NB_VTTLF3

321.35mA

0.47U_0402_10V4Z

Pin A25 GNDtoB25

+1.05VS_DPLLA +1.05VS_DPLLB

+1.05VS_AHPLL

+1.05VS_MPLL

+1.8V_TXLVDS

+1.5VS_PEG_BG

+1.05VS_PEGPLL

Pin AR20

Pin AP28

+1.5VS_HDA

+1.5VS +1.5VS_QDAC

+1.05VS_DHPLL

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C128

0.47U_0402_10V4Z

0.47U_0402_10V4Z 2

+1.05VS_AXF

+1.8V_SM_CK

EVT2- Remove C153 PM@ 0Ohm.

124mA

+1.8V_TXLVDS

118.8mA

+3VS

+1.05VS_PEG_DMI

C167

C168

0.47U_0402_10V4Z

C123

2.2U_0402_6.3V6M

0.47U_0402_10V4Z

0.47U_0402_10V4Z C169

C169

+1.05VS

AGTL+

NB I/O

C140

C140 1U_0402_6.3V4Z

1U_0402_6.3V4Z

C130

4.7U_0603_6.3V6K

R111

1 2

0_0603_5%

C142

10U_0805_10V4Z

10U_0805_10V4Z 2

C129

4.7U_0603_6.3V6K

Intel: VTT 270U*1 ESR 12mOhm

+1.05VS_AXF

+1.05VS

C131

C131 220U_6.3V_M

220U_6.3V_M

Pin B22

+1.8V_SM_CK

DDR2

C147

0.1U_0402_16V4Z

Pin BF21

+1.8V_TXLVDS +1.8V

LVDS

C153

GM@C153

GM@

1000P_0402_50V7K

Pin K47

+3VS

C158

0.1U_0402_16V4Z

Pin C35

R114

R114 1_0402_1%

1_0402_1%

C149

1 2

10U_0805_10V4Z

R116 1 2

0_0603_5%

C154 10U_0805_10V4Z

10U_0805_10V4Z

GM@R116

GM@

GM@C154

GM@

R113

1 2

0_0805_5%

C148

C148 10U_0805_10V4Z

10U_0805_10V4Z

+1.8V

DVT-R120 change to J8 for power rating issue.

+1.05VS_PEG_DMI

10U_0805_10V4Z

+1.05VS_PEG_DMI

Title

Size Document Number Rev

Custom

Date: Sheet

PCIe&DMI

10U_0805_10V4Z@

C164

Pin V48

10U_0805_10V4Z@

C165

220U_6.3V_M

C166

PCIe&DMI

C171

0.1U_0402_16V4Z

Pin AH48

Compal Electronics, Inc.

SCHEMATICS,M/B A4161

401562 G

112

JUMP_43X118@J8JUMP_43X118@

12 48Monday, February 23, 2009

+1.05VS

U3I

AU48

VSS_1

AR48

VSS_2

AL48

VSS_3

BB47

VSS_4

AW47

VSS_5

AN47

VSS_6

AJ47

VSS_7

AF47

VSS_8

AD47

VSS_9

AB47

VSS_10

Y47

VSS_11

T47

BD46 BA46 AY46 AV46 AR46

AM46

BF44 AH44 AD44 AA44

M44

BC43 AV43 AU43

AM43

BG42 AY42 AT42 AN42

AJ42

AE42

BD41 AU41

AM41

AH41 AD41 AA41

M41

BG40 BB40 AV40 AN40

AT39

AM39

AJ39

AE39

BH38 BC38 BA38 AU38 AH38 AD38 AA38

BF37 BB37

AW37

AT37 AN37

AJ37

BG36 BD36 AK15 AU36

VSS_12

N47

VSS_13

L47

VSS_14

G47

VSS_15 VSS_16 VSS_17 VSS_18 VSS_19 VSS_20 VSS_21

V46

VSS_22

R46

VSS_23

P46

VSS_24

H46

VSS_25

F46

VSS_26 VSS_27 VSS_28 VSS_29 VSS_30

Y44

VSS_31

U44

VSS_32

T44

VSS_33 VSS_34

F44

VSS_35 VSS_36 VSS_37 VSS_38 VSS_39

J43

VSS_40

C43

VSS_41 VSS_42 VSS_43 VSS_44 VSS_45 VSS_46 VSS_47

N42

VSS_48

L42

VSS_49 VSS_50 VSS_51 VSS_52 VSS_53 VSS_54 VSS_55

Y41

VSS_56

U41

VSS_57

T41

VSS_58 VSS_59

G41

VSS_60

B41

VSS_61 VSS_62 VSS_63 VSS_64 VSS_65

H40

VSS_66

E40

VSS_67 VSS_68 VSS_69 VSS_70 VSS_71

N39

VSS_72

L39

VSS_73

B39

VSS_74 VSS_75 VSS_76 VSS_77 VSS_78 VSS_79 VSS_80 VSS_81

Y38

VSS_82

U38

VSS_83

T38

VSS_84

J38

VSS_85

F38

VSS_86

C38

VSS_87 VSS_88 VSS_89 VSS_90 VSS_91 VSS_92 VSS_93

H37

VSS_94

C37

VSS_95 VSS_96 VSS_97 VSS_98 VSS_99

VSS

CANTIGA ES_FCBGA1329

CANTIGA ES_FCBGA1329 GMR3@

GMR3@

D D

C C

B B

A A

VSS_100 VSS_101 VSS_102 VSS_103 VSS_104 VSS_105 VSS_106 VSS_107 VSS_108 VSS_109 VSS_110 VSS_111 VSS_112 VSS_113 VSS_114 VSS_115 VSS_116 VSS_117 VSS_118 VSS_119 VSS_120 VSS_121 VSS_122 VSS_123 VSS_124 VSS_125 VSS_126 VSS_127 VSS_128 VSS_129 VSS_130 VSS_131 VSS_132 VSS_133 VSS_134 VSS_135 VSS_136 VSS_137 VSS_138 VSS_139 VSS_140 VSS_141 VSS_142 VSS_143 VSS_144 VSS_145 VSS_146 VSS_147 VSS_148 VSS_149 VSS_150 VSS_151 VSS_152 VSS_153 VSS_154 VSS_155 VSS_156 VSS_157 VSS_158 VSS_159 VSS_160 VSS_161 VSS_162 VSS_163 VSS_164 VSS_165 VSS_166 VSS_167 VSS_168 VSS_169 VSS_170 VSS_171 VSS_172 VSS_173 VSS_174 VSS_175 VSS_176 VSS_177 VSS_178 VSS_179 VSS_180 VSS_181 VSS_182 VSS_183 VSS_184 VSS_185 VSS_186 VSS_187 VSS_188 VSS_189 VSS_190 VSS_191 VSS_192 VSS_193 VSS_194 VSS_195 VSS_196 VSS_197 VSS_198 VSS_199

AM36 AE36 P36 L36 J36 F36 B36 AH35 AA35 Y35 U35 T35 BF34 AM34 AJ34 AF34 AE34 W34 B34 A34 BG33 BC33 BA33 AV33 AR33 AL33 AH33 AB33 P33 L33 H33 N32 K32 F32 C32 A31 AN29 T29 N29 K29 H29 F29 A29 BG28 BD28 BA28 AV28 AT28 AR28 AJ28 AG28 AE28 AB28 Y28 P28 K28 H28 F28 C28 BF26 AH26 AF26 AB26 AA26 C26 B26 BH25 BD25 BB25 AV25 AR25 AJ25 AC25 Y25 N25 L25 J25 G25 E25 BF24 AD12 AY24 AT24 AJ24 AH24 AF24 AB24 R24 L24 K24 J24 G24 F24 E24 BH23 AG23 Y23 B23 A23 AJ6

U3J

BG21

VSS_199

L12

VSS_200

AW21

VSS_201

AU21

VSS_202

AP21

VSS_203

AN21

VSS_204

AH21

VSS_205

AF21

VSS_206

AB21

VSS_207

R21

VSS_208

M21

VSS_209

J21

VSS_210

G21

VSS_211

BC20

VSS_212

BA20

VSS_213

AW20

VSS_214

AT20

VSS_215

AJ20

VSS_216

AG20

VSS_217

Y20

VSS_218

N20

VSS_219

K20

VSS_220

F20

VSS_221

C20

VSS_222

A20

VSS_223

BG19

VSS_224

A18

VSS_225

BG17

VSS_226

BC17

VSS_227

AW17

VSS_228

AT17

VSS_229

R17

VSS_230

M17

VSS_231

H17

VSS_232

C17

VSS_233

BA16

VSS_235

AU16

VSS_237

AN16

VSS_238

N16

VSS_239

K16

VSS_240

G16

VSS_241

E16

VSS_242

BG15

VSS_243

AC15

VSS_244

W15

VSS_245

A15

VSS_246

BG14

VSS_247

AA14

VSS_248

C14

VSS_249

BG13

VSS_250

BC13

VSS_251

BA13

VSS_252

AN13

VSS_255

AJ13

VSS_256

AE13

VSS_257

N13

VSS_258

L13

VSS_259

G13

VSS_260

E13

VSS_261

BF12

VSS_262

AV12

VSS_263

AT12

VSS_264

AM12

VSS_265

AA12

VSS_266

J12

VSS_267

A12

VSS_268

BD11

VSS_269

BB11

VSS_270

AY11

VSS_271

AN11

VSS_272

AH11

VSS_273

Y11

VSS_275

N11

VSS_276

G11

VSS_277

C11

VSS_278

BG10

VSS_279

AV10

VSS_280

AT10

VSS_281

AJ10

VSS_282

AE10

VSS_283

AA10

VSS_284

M10

VSS_285

BF9

VSS_286

BC9

VSS_287

AN9

VSS_288

AM9

VSS_289

AD9

VSS_290

VSS_291

VSS_292

BH8

VSS_293

BB8

VSS_294

AV8

VSS_295

AT8

VSS_296

CANTIGA ES_FCBGA1329

CANTIGA ES_FCBGA1329 GMR3@

GMR3@

VSS

VSS_NCTF_10

VSS NCTF

VSS_NCTF_11 VSS_NCTF_12 VSS_NCTF_13 VSS_NCTF_14 VSS_NCTF_15 VSS_NCTF_16

VSS SCB

VSS_297 VSS_298 VSS_299 VSS_300 VSS_301 VSS_302 VSS_303 VSS_304 VSS_305 VSS_306 VSS_307 VSS_308 VSS_309 VSS_310 VSS_311 VSS_312 VSS_313 VSS_314 VSS_315 VSS_316 VSS_317 VSS_318 VSS_319 VSS_320 VSS_321 VSS_322 VSS_323 VSS_324 VSS_325

VSS_327 VSS_328 VSS_329 VSS_330 VSS_331 VSS_332 VSS_333 VSS_334 VSS_335 VSS_336 VSS_337 VSS_338 VSS_339 VSS_340 VSS_341 VSS_342 VSS_343 VSS_344 VSS_345 VSS_346 VSS_347 VSS_348 VSS_349 VSS_350

VSS_351 VSS_352 VSS_353 VSS_354

VSS_NCTF_1 VSS_NCTF_2 VSS_NCTF_3 VSS_NCTF_4 VSS_NCTF_5 VSS_NCTF_6 VSS_NCTF_7 VSS_NCTF_8 VSS_NCTF_9

VSS_SCB_1 VSS_SCB_2 VSS_SCB_3 VSS_SCB_4 VSS_SCB_5

NC_26 NC_27 NC_28 NC_29 NC_30 NC_31 NC_32 NC_33 NC_34 NC_35 NC_36 NC_37 NC_38 NC_39 NC_40 NC_41 NC_42

AH8 Y8 L8 E8 B8 AY7 AU7 AN7 AJ7 AE7 AA7 N7 J7 BG6 BD6 AV6 AT6 AM6 M6 C6 BA5 AH5 AD5 Y5 L5 J5 H5 F5 BE4

BC3 AV3 AL3 R3 P3 F3 BA2 AW2 AU2 AR2 AP2 AJ2 AH2 AF2 AE2 AD2 AC2 Y2 M2 K2 AM1 AA1 P1 H1

U24 U28 U25 U29

AF32 AB32 V32 AJ30 AM29 AF29 AB29 U26 U23 AL20 V20 AC19 AL17 AJ17 AA17 U17

BH48 BH1 A48 C1 A3

E1 D2 C3 B4 A5 A6 A43 A44 B45 C46 D47 B47 A46 F48 E48 C48 B48

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2008/10/1 2009/10/1

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

SCHEMATICS,M/B A4161

401562 G

13 48Monday, February 23, 2009

JP30

+DIMM_VREF

2.2U_0603_6.3V6K

+1.8V

D D

R124

R124 1K_0402_1%

1K_0402_1%

R125

R125 1K_0402_1%

1K_0402_1%

C C

B B

A A

C175

20mils

0.1U_0402_16V4Z

+DIMM_VREF

DDRA_CKE0<8>

DDR_A_CAS#<9>

DDRA_SCS1#<8>

DDR_A_BS2<9>

DDR_A_BS0<9>

DDR_A_WE#<9>

DDRA_ODT1<8>

C176

PM_SMBDATA<15,16,22,26> PM_SMBCLK<15,16,22,26>

+3VS

C203

0.1U_0402_16V4Z

DDR_A_D5 DDR_A_D6

DDR_A_DQS#0 DDR_A_DQS0

DDR_A_D3 DDR_A_D2

DDR_A_D8 DDR_A_D9

DDR_A_DQS#1 DDR_A_DQS1

DDR_A_D15 DDR_A_D10

DDR_A_D21 DDR_A_D20

DDR_A_DQS#2 DDR_A_DQS2

DDR_A_D23 DDR_A_D18 DDR_A_D19

DDR_A_D29 DDR_A_D24

DDR_A_DM3

DDR_A_D26 DDR_A_D27

DDRA_CKE0

DDR_A_BS2 DDR_A_MA12

DDR_A_MA9 DDR_A_MA8

DDR_A_MA5 DDR_A_MA3 DDR_A_MA1

DDR_A_MA10 DDR_A_BS0 DDR_A_WE#

DDR_A_CAS# DDRA_SCS1#

DDRA_ODT1 DDR_A_D37

DDR_A_D36 DDR_A_DQS#4

DDR_A_DQS4 DDR_A_D34

DDR_A_D39 DDR_A_D40

DDR_A_D44 DDR_A_DM5 DDR_A_D47

DDR_A_D41 DDR_A_D49

DDR_A_D48

DDR_A_DQS#6 DDR_A_DQS6

DDR_A_D54 DDR_A_D50

DDR_A_D60 DDR_A_D61

DDR_A_DM7 DDR_A_D58

DDR_A_D59

VREF

VSS

DQ0

DQ1

VSS

DQS0#

DQS0

VSS

DQ2

DQ3

VSS

DQ8

DQ9

VSS

DQS1#

DQS1

VSS

DQ10

DQ11

VSS

DQ16

DQ17

VSS

DQS2#

DQS2

VSS

DQ18

DQ19

VSS

DQ24

DQ25

VSS

DM3

VSS

DQ26

DQ27

VSS

CKE0

VDD

BA2

VDD

A12

VDD

101

103

VDD

105

A10/AP

107

BA0

109

WE#

111

VDD

113

CAS#

115

NC/S1#

117

VDD

119

NC/ODT1

121

VSS

123

DQ32

125

DQ33

127

VSS

129

DQS4#

131

DQS4

133

VSS

135

DQ34

137

DQ35

139

VSS

141

DQ40

143

DQ41

145

VSS

147

DM5

149

VSS

151

DQ42

153

DQ43

155

VSS

157

DQ48

159

DQ49

161

VSS

163

NC,TEST

165

VSS

167

DQS6#

169

DQS6

171

VSS

173

DQ50

175

DQ51

177

VSS

179

DQ56

181

DQ57

183

VSS

185

DM7

187

VSS

189

DQ58

191

DQ59

193

VSS

195

SDA

197

SCL

199

VDDSPD

VSS DQ4 DQ5 VSS DM0 VSS DQ6 DQ7

VSS DQ12 DQ13

VSS

DM1

VSS

CK0 CK0#

VSS DQ14 DQ15

VSS

VSS DQ20 DQ21

VSS

NC DM2 VSS

DQ22 DQ23

VSS

DQ28 DQ29

VSS

DQS3#

DQS3

VSS

DQ30 DQ31

VSS

NC/CKE1

VDD

NC/A15 NC/A14

VDD

A11

A7 A6

VDD

A4 A2 A0

VDD

BA1

RAS#

S0#

VDD

ODT0

NC/A13

VDD

NC VSS

DQ36 DQ37

VSS DM4 VSS

DQ38 DQ39

VSS

DQ44 DQ45

VSS

DQS5#

DQS5

VSS

DQ46 DQ47

VSS

DQ52 DQ53

VSS CK1

CK1#

VSS DM6 VSS

DQ54 DQ55

VSS

DQ60 DQ61

VSS

DQS7#

DQS7

VSS

DQ62 DQ63

VSS SAO

SA1

GND

TYCO_1775803-2~D

201

202

EVT2- Change DDR connector type, JP30 for Standard.

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40

42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200

SO-DIMM A

DDR_A_D4 DDR_A_D0

DDR_A_DM0 DDR_A_D1

DDR_A_D7 DDR_A_D13

DDR_A_D12 DDR_A_DM1

DDR_A_D14 DDR_A_D11

DDR_A_D17 DDR_A_D16

DDR_A_DM2

DDR_A_D22 DDR_A_D28

DDR_A_D25 DDR_A_DQS#3

DDR_A_DQS3 DDR_A_D31

DDR_A_D30 DDRA_CKE1

DDR_A_MA14 DDR_A_MA11

DDR_A_MA7 DDR_A_MA6

DDR_A_MA4 DDR_A_MA2 DDR_A_MA0

DDR_A_BS1 DDR_A_RAS# DDRA_SCS0#

DDRA_ODT0 DDR_A_MA13

DDR_A_D32 DDR_A_D38

DDR_A_DM4 DDR_A_D35

DDR_A_D33 DDR_A_D45

DDR_A_D43 DDR_A_DQS#5

DDR_A_DQS5 DDR_A_D46

DDR_A_D42 DDR_A_D52

DDR_A_D53

DDR_A_DM6 DDR_A_D51

DDR_A_D55 DDR_A_D57

DDR_A_D56 DDR_A_DQS#7

DDR_A_DQS7 DDR_A_D62

DDR_A_D63

Standar

BOT side

+1.8V+1.8V

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

DDRA_CLK0 <8> DDRA_CLK0# <8>

PM_EXTTS# <8,15>

DVT2- Change +0.9V to +0.9VS

DDRA_CKE1 <8>

DDR_A_BS1 <9> DDR_A_RAS# <9> DDRA_SCS0# <8>

DDRA_ODT0 <8>

DDRA_CLK1 <8> DDRA_CLK1# <8>

DVT2- Remove R406/R357 of DDR address resistors.

Compal Secret Data

2008/10/1 2009/10/1

Compal Secret Data

Layout Note:

+1.8V

Place near JP59

2.2U_0603_6.3V6K

C177

Deciphered Date

DDR_A_DQS#[0..7]<9>

DDR_A_D[0..63]<9>

DDR_A_DM[0..7]<9> DDR_A_DQS[0..7]<9> DDR_A_MA[0..14]<9>

2.2U_0603_6.3V6K

C178

C179

+0.9VS

0.1U_0402_16V4Z

C189

Layout Note: Place these resistor closely JP34,all trace length Max=1.5"

DDR_A_BS0 DDR_A_MA10 DDR_A_MA1 DDR_A_MA5

DDR_A_RAS# DDR_A_MA2 DDR_A_MA0 DDR_A_MA4

DDRA_ODT1 DDR_A_CAS# DDRA_SCS1# DDR_A_WE#

DDRA_CKE1 DDR_A_BS2 DDRA_CKE0

2.2U_0603_6.3V6K

2.2U_0603_6.3V6K C181

C181

C180

Layout Note: Place one cap close to every 2 pullup resistors terminated to +0.9V

0.1U_0402_16V4Z

C190

C191

C192

0.1U_0402_16V4Z

0.1U_0402_16V4Z C182

C182

0.1U_0402_16V4Z

C193

C183

0.1U_0402_16V4Z

C194

0.1U_0402_16V4Z

0.1U_0402_16V4Z C184

C184

0.1U_0402_16V4Z

C195

C196

0.1U_0402_16V4Z

EVT2- Swap for DDR connector change.

+0.9VS

RP2

18 27 36 45

56_0804_8P4R_5%

18 27 36 45

56_0804_8P4R_5%

RP2

1 8 2 7 3 6 4 5

DDR_A_MA3 DDR_A_MA9 DDR_A_MA8 DDR_A_MA12

RP4

DDR_A_MA6

DDR_A_MA7

DDR_A_MA11

DDR_A_MA14

RP6

DDR_A_MA13

DDRA_ODT0

DDRA_SCS0#

DDR_A_BS1

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

SCHEMATICS,M/B A4161

401562 G

RP1

56_0804_8P4R_5%

RP3

1 8 2 7 3 6 4 5

56_0804_8P4R_5%

RP5

56_0804_8P4R_5%

RP7

1 8 2 7 3 6 4 5

56_0804_8P4R_5%

C185

C186

C186 330U_4V_M

330U_4V_M

0.1U_0402_16V4Z

C197

0.1U_0402_16V4Z

C198

C199

0.1U_0402_16V4Z

C200

0.1U_0402_16V4Z

C201

14 48Monday, February 23, 2009

JP31

+DIMM_VREF

2.2U_0603_6.3V6K

1 1

2 2

3 3

4 4

C204

0.1U_0402_16V4Z

DDRB_CKE0<8>

DDR_B_BS2<9>

DDR_B_BS0<9> DDR_B_WE#<9>

DDR_B_CAS#<9>

DDRB_SCS1#<8>

DDRB_ODT1<8>

PM_SMBDATA<14,16,22,26> PM_SMBCLK<14,16,22,26>

C205

+1.8V

DDR_B_D0 DDR_B_D1

DDR_B_DQS#0 DDR_B_DQS0

DDR_B_D2 DDR_B_D3

DDR_B_D8 DDR_B_D9

DDR_B_DQS#1 DDR_B_DQS1

DDR_B_D10 DDR_B_D11

DDR_B_D17 DDR_B_D20

DDR_B_DQS#2 DDR_B_DQS2

DDR_B_D18 DDR_B_D19

DDR_B_D25 DDR_B_D28

DDR_B_DM3

DDR_B_D30 DDR_B_D31

DDRB_CKE0

DDR_B_BS2 DDR_B_MA12

DDR_B_MA9 DDR_B_MA8

DDR_B_MA5 DDR_B_MA3 DDR_B_MA1

DDR_B_MA10 DDR_B_BS0 DDR_B_WE#

DDR_B_CAS# DDRB_SCS1#

DDRB_ODT1 DDR_B_D32

DDR_B_D33 DDR_B_DQS#4

DDR_B_DQS4 DDR_B_D34

DDR_B_D35 DDR_B_D40

DDR_B_D41 DDR_B_DM5 DDR_B_D42

DDR_B_D43 DDR_B_D48

DDR_B_D49

DDR_B_DQS#6 DDR_B_DQS6

DDR_B_D50 DDR_B_D51

DDR_B_D56 DDR_B_D61

DDR_B_DM7 DDR_B_D63

DDR_B_D58

+3VS

C229

0.1U_0402_16V4Z

VREF

VSS

DQ0

DQ1

VSS

DQS0#

DQS0

VSS

DQ2

DQ3

VSS

DQ8

DQ9

VSS

DQS1#

DQS1

VSS

DQ10

DQ11

VSS

DQ16

DQ17

VSS

DQS2#

DQS2

VSS

DQ18

DQ19

VSS

DQ24

DQ25

VSS

DM3

VSS

DQ26

DQ27

VSS

CKE0

VDD

BA2

VDD

A12

VDD

101

103

VDD

105

A10/AP

107

BA0

109

WE#

111

VDD

113

CAS#

115

NC/S1#

117

VDD

119

NC/ODT1

121

VSS

123

DQ32

125

DQ33

127

VSS

129

DQS4#

131

DQS4

133

VSS

135

DQ34

137

DQ35

139

VSS

141

DQ40

143

DQ41

145

VSS

147

DM5

149

VSS

151

DQ42

153

DQ43

155

VSS

157

DQ48

159

DQ49

161

VSS

163

NC,TEST

165

VSS

167

DQS6#

169

DQS6

171

VSS

173

DQ50

175

DQ51

177

VSS

179

DQ56

181

DQ57

183

VSS

185

DM7

187

VSS

189

DQ58

191

DQ59

193

VSS

195

SDA

197

SCL

199

VDDSPD

VSS

DQ4

DQ5

VSS

DM0

VSS

DQ6

DQ7

VSS

DQ12

DQ13

VSS

DM1

VSS

CK0

CK0#

VSS

DQ14

DQ15

VSS

DQ20

DQ21

VSS

DM2

VSS

DQ22

DQ23

VSS

DQ28

DQ29

VSS

DQS3#

DQS3

VSS

DQ30

DQ31

VSS

NC/CKE1

VDD

NC/A15

NC/A14

VDD

A11

VDD

100

102

104

VDD

106

BA1

108

RAS#

110

S0#

112

VDD

114

ODT0

116

NC/A13

118

VDD

120

122

VSS

124

DQ36

126

DQ37

128

VSS

130

DM4

132

VSS

134

DQ38

136

DQ39

138

VSS

140

DQ44

142

DQ45

144

VSS

146

DQS5#

148

DQS5

150

VSS

152

DQ46

154

DQ47

156

VSS

158

DQ52

160

DQ53

162

VSS

164

CK1

166

CK1#

168

VSS

170

DM6

172

VSS

174

DQ54

176

DQ55

178

VSS

180

DQ60

182

DQ61

184

VSS

186

DQS7#

188

DQS7

190

VSS

192

DQ62

194

DQ63

196

VSS

198

SAO

200

SA1

GND

FOX_AS0A426-M6RN-7F~D

203

204

SO-DIMM B

Reserve

BOT side

EVT2- Change DDR connector type, JP31 for Reserve.

DDR_B_D5 DDR_B_D4

DDR_B_DM0 DDR_B_D6

DDR_B_D7 DDR_B_D12

DDR_B_D13 DDR_B_DM1

DDRB_CLK0 <8>

DDR_B_D14 DDR_B_D15

DDR_B_D21 DDR_B_D16

DDR_B_DM2 DDR_B_D22

DDR_B_D23 DDR_B_D26

DDR_B_D24 DDR_B_DQS#3

DDR_B_DQS3 DDR_B_D29

DDR_B_D27 DDRB_CKE1

DDR_B_MA14 DDR_B_MA11

DDR_B_MA7 DDR_B_MA6

DDR_B_MA4 DDR_B_MA2 DDR_B_MA0

DDR_B_BS1 DDR_B_RAS# DDRB_SCS0#

DDRB_ODT0 DDR_B_MA13

DDR_B_D36 DDR_B_D37

DDR_B_DM4 DDR_B_D39

DDR_B_D38 DDR_B_D44

DDR_B_D45 DDR_B_DQS#5

DDR_B_DQS5 DDR_B_D46

DDR_B_D47 DDR_B_D52

DDR_B_D53

DDR_B_DM6 DDR_B_D54

DDR_B_D55 DDR_B_D60

DDR_B_D57 DDR_B_DQS#7

DDR_B_DQS7 DDR_B_D62

DDR_B_D59

DDRB_CLK0# <8>

PM_EXTTS# <8,14>

DVT2- Change +0.9V to +0.9VS

DDRB_CKE1 <8>

+1.8V

DDR_B_BS1 <9> DDR_B_RAS# <9> DDRB_SCS0# <8>

DDRB_ODT0 <8>

DDRB_CLK1 <8> DDRB_CLK1# <8>

DVT2- Remove R407/R408 of DDR address resistors.

+3VS

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

DDR_B_DQS#[0..7]<9>

DDR_B_D[0..63]<9>

DDR_B_DM[0..7]<9> DDR_B_DQS[0..7]<9> DDR_B_MA[0..14]<9>

Layout Note:

+1.8V

Place near JP58

2.2U_0603_6.3V6K

2.2U_0603_6.3V6K C206

C206

+0.9VS

0.1U_0402_16V4Z

C215

Layout Note: Place these resistor closely JP10,all trace length Max=1.5"

DDR_B_MA5 DDR_B_MA8

DDR_B_MA9 DDR_B_MA12

DDRB_SCS0# DDR_B_MA7 DDR_B_RAS# DDR_B_MA2 DDR_B_MA4

DDR_B_BS0 DDR_B_MA10 DDR_B_MA1 DDR_B_MA3

DDRB_ODT1 DDRB_SCS1# DDR_B_CAS# DDR_B_WE#

Compal Secret Data

2008/10/1 2009/10/1

Compal Secret Data

Deciphered Date

2.2U_0603_6.3V6K

C207

C208

Layout Note: Place one cap close to every 2 pullup Resistors terminated to +0.9V

C216

C208

0.1U_0402_16V4Z

C217

C218

EVT2- Swap for DDR connector change. Add R1022 for DDRB_CKE1. Add R1023/R1024 for DDR_B_BS2/DDRB_CKE0.

RP8

1 8 2 7 3 6 4 5

56_0804_8P4R_5%

RP10

1 8 2 7 3 6 4 5

56_0804_8P4R_5%

RP12

1 8 2 7 3 6 4 5

56_0804_8P4R_5%

RP14

1 8 2 7 3 6 4 5

56_0804_8P4R_5%

2.2U_0603_6.3V6K

C209

0.1U_0402_16V4Z

C219

+0.9VS

R1023 56_0402_5%R1023 56_0402_5% R1024 56_0402_5%R1024 56_0402_5%

56_0804_8P4R_5%

R1022 56_0402_5%R1022 56_0402_5%

0.1U_0402_16V4Z

C210

0.1U_0402_16V4Z

C220

1 2 1 2

RP11

RP13

1 2

0.1U_0402_16V4Z

0.1U_0402_16V4Z C213

C213

C212

C211

0.1U_0402_16V4Z

C221

DDR_B_MA11

DDR_B_MA6

36 45

18 27

DDR_B_MA0

DDR_B_BS1

C222

C223

DDR_B_BS2 DDRB_CKE0

DDR_B_MA14

DDR_B_MA13 DDRB_ODT0

DDRB_CKE1

Title

Size Document Number Rev

Date: Sheet

0.1U_0402_16V4Z

C224

C225

Compal Electronics, Inc.

SCHEMATICS,M/B A4161

401562 G

C214

0.1U_0402_16V4Z

C226

C188

C188 330U_4V_M

330U_4V_M

0.1U_0402_16V4Z

C227

15 48Monday, February 23, 2009

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