COMPAL LA-4161P Schematics

A

1 1

B

C

D

E

JSKAA

2 2

Irving 10/10G

LA4161P

3 3

REV 1.0

Schematic

Intel Penryn/ Cantiga (GL45/GM45/PM45)/ ICH9M

2008-10-01 Rev. 1.0

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2008/10/1 2009/10/1

C

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

D

Date: Sheet

Compal Electronics, Inc.

SCHEMATICS,M/B A4161

401562 G

E

of

148Monday, February 23, 2009

of

148Monday, February 23, 2009

of

148Monday, February 23, 2009

A

B

C

D

E

Compal Confidential

XDP Debug

page 4

Model Name : JSKAA File Name :

1 1

CRT

page 18

VGA Conn.

HD Audio

3.3V 24.576MHz/48Mhz

EC SMBUS

2 2

3 3

HDMI CEC Controller R5F211A4SP

page 19

PCIeMini Card -WiMAX USB port 7

PCIeMini Card -WLAN

NB9M-GS NB9P-GE/GS NB9E-GS

page 17

HDMI Conn.

Mini Slot 1 Mini Slot 2 Mini Slot 3

page 26

PCIeMini Card --

PCIe port 4

Robson/ HDDVD

PCIe port 2

Express Card

USB port 8

LCD Conn.

page 19

page 27page 26

Express Card Slot

page 26

page 17

PCIeMini Card -UWB/ TV tuner/ GPS

USB port 6

Express Card

PCIe port 1

FM Tuner

NXP--TEA5763HN

Fan Control

PCI-Express 16x

Level Shifter

page 19

page 26

page 25

page 4

USB

5V 48MHz

PCIe 1x [4..5]

USB

5V 48MHz

PCIe 1x

I2C from SB

Intel Penryn Processor

uPGA-478 Package

(Socket P)

H_A#(3..35) H_D#(0..63)

FSB

667/800/1066MHz

page 4,5,6

Intel Cantiga

PM/GM/GL

uFCBGA-1329

page 7,8,9,10,11,12,13

DMI

C-Link

Intel ICH9-M

BGA-676

page 20,21,22,23

PCI BUS

3.3V 33 MHz

5V 48MHz

SATA [0..1]

5V 1.5GHz(150MB/s)

SATA

5V 1.5GHz(150MB/s)

5V 48MHz

5V 1.5GHz(150MB/s)

HD Audio

3.3V 24.576MHz/48Mhz

Thermal Sensor

SMSC--EMC1402-1-ACZL

page 4

Memory BUS(DDRII)

Dual Channel

1.8V DDRII 533/667/800

HD Audio

3.3V 24.576MHz/48Mhz

PCIe 1x

USB

LOM(1G)

RTL8111C

PCIe port 5

TMA

USB conn x2

USB port0--Rare USB port1--Right

page 25

SATA HDD0

SATA ODD

USB

SATA

eSTAT/USB Conn

eSATA port5

page 24

LPC BUS

3.3V 33 MHz

Mini PCI

ISDB-T TV Tuner

DC I/F to HW

page37

4 4

page32

B-CAS

page32

Power Circuit DC/DC

page38~45

A

B

LPC Debug Port.

page35

LED/B Conn.

page36

VR/B Conn.

page36

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

T/P

page35

ENE KB926 C0

page34

FUN/B Conn.

page36

PWR/B Conn.

page36

2008/10/1 2009/10/1

C

Int.KBD

page35

SPI ROM

page35 page35

Compal Secret Data

IR/B

page33

EC Debug

Deciphered Date

Clock Generator

Seligo--SLG8SP553VTR ICS--ICS9LPRS387AKLFT

page 16

200pin DDRII-SO-DIMM X2

BANK 0, 1, 2, 3

PCIe port 3

page 28 page 28

page 27

BT2.1

USB port 5

page 25 page 25

page 24

USB port 3

RJ45

FingerPrinter

USB port 4

page 25 page 25

SATA HDD1

page 24

MDC 1.5 Conn

page29

AOCR/B LS4164P Conn.

HDAALC272

CardReader/ 1394JMB380

PCIe port 6

USB- Left Port USB Port2

page29

D

PCIe 1x

USB

5V 48MHz

Title

Size Document Number Rev

B

Date: Sheet

page 14,15

Flica

USB port 9

Int. Camera USB port 11

Int. MIC CONN

page29

SPK-L/R CONN SPK-L/R LED CONN

page29

Compal Electronics, Inc.

SCHEMATICS,M/B A4161

401562 G

E

of

248Monday, February 23, 2009

of

248Monday, February 23, 2009

of

248Monday, February 23, 2009

A

Voltage Rails

Power Plane Description

VIN

1 1

2 2

B+ +CPU_CORE +0.9V 0.9V switched power rail for DDR terminator +1.05VS +1.5VS +1.8V

+3VALW +3VL 3.3V always on power rail ONON +3V_SB 3.3V power rail for LAN ON ON +3V_LAN 3.3V power rail for LAN ON ON +3V_WLAN 3.3V power rail for LAN ON ON +3VS +5VALW +5VL 5V always on power rail ON ON

+5VS +VSB VSB always on power rail ON ON +RTCVCC RTC power

Adapter power supply (19V) AC or battery power rail for power circuit. Core voltage for CPU

1.05V switched power rail

1.5V switched power rail

1.8V power rail for DDR

3.3V always on power rail

3.3V switched power rail 5V always on power rail

5V switched power rail

B

S1 S3 S5

ON ON ON OFF ON ON ON ON ON OFF ON OFF ON OFF OFF ON OFF OFF ON OFF

ON

ON ON

OFF OFF

ON

ON ON

ON ON OFF OFF OFF

OFF

ON ON

ON ON OFF OFF+5V_SB 5V power rail for SB ON ON

OFF

OFFON

ONON

OFF OFF OFF OFF OFF

OFF

OFF OFF OFF OFF OFF

OFF OFF ON

C

SIGNAL

STATE

Full ON

G3

S1(Power On Suspend)

S3 (Suspend to RAM)

SLP_S1# SLP_S3#

SLP_S4# SLP_S5#

HIGH HIGH HIGH HIGH

LOW

S4 (Suspend to Disk)

S5 (Soft OFF)

LOW LOW LOW LOW

HIGH

LOWLOWLOW

D

HIGHHIGHHIGH

HIGH

E

G3 LOWLOWLOWLOW

Reserve for AD channel define.

Vcc 3.3V +/- 5%

Board ID

0 1 2 3 4 5 6 7NC

100K +/- 5%Ra/Rc/Re

Rb / Rd / Rf V min

0

8.2K +/- 5% 18K +/- 5% 33K +/- 5% 56K +/- 5% 100K +/- 5% 200K +/- 5%

AD_BID

0 V

0.216 V 0.250 V 0.289 V

0.436 V

0.712 V

1.036 V

1.453 V 1.650 V 1.759 V

1.935 V

2.500 V

V typ

AD_BID

V

AD_BID

0 V 0 V

0.503 V

0.819 V

0.538 V

0.875 V

1.185 V 1.264 V

2.200 V

3.300 V

2.341 V

3.300 V

max

BTO Option Table

External PCI Devices

Device IDSEL# REQ#/GNT# Interrupts

PCI TV Tuner

AD18 (Master) AD19 (Slave)

1/1 (Master) 2/2 (Slave)

PIRQG (Master) PIRQH (Slave)

BTO Item BOM Structure

EC SM Bus1 address

Device

EC KB926 C0+5VL EC KB926 C0+3VS

3 3

Smart Battery+5VL HDMI-CEC+5VL

+5VL FUN/B (CAP Sensor)

Address Address

0001 011X b 0011 010x b

EC SM Bus2 address

Device

PowerPower

CPU THM Sen .SMSC

+3VS

EMC1402-1-ACZL-TR

VGA THM Sen. nVedia+3VS

1001 100x b

1001 1110 b

ICH9M SM Bus address

Device

Power

ICH9M

+3V_SB

Clock Generator

+3VS

(SLG8SP556V) DDR DIMM0

+3VS

DDR DIMM1

+3VS

Express

+3VS

4 4

+3VS

FM Module

A

Vertial I2C

Address

1101 001Xb

1001 000Xb 1001 010Xb

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2008/10/1 2009/10/1

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

B

Date: Sheet

D

Date: Sheet

Compal Electronics, Inc.

SCHEMATICS,M/B A4161

401562 G

E

of

348Monday, February 23, 2009

5

@

H_A#[3..16]<7>

D D

H_ADSTB#0<7>

H_REQ#0<7> H_REQ#1<7> H_REQ#2<7> H_REQ#3<7> H_REQ#4<7>

H_A#[17..35]<7>

C C

H_ADSTB#1<7>

H_A20M#<21>

H_FERR#<21>

H_IGNNE#<21> H_STPCLK#<21>

H_INTR<21>

H_NMI<21> H_SMI#<21>

+CPU_GTLREF2

QC: POP DC: DEPOP

B B

+1.05VS

@ R984

@

51_0402_1%

1 2

THRMDA_2 THRMDC_2

R984

H_A20M# H_FERR# H_IGNNE#

H_STPCLK# H_INTR H_NMI H_SMI#

XDP_BPM2#1 XDP_BPM2#0

XDP_BPM2#2

TDO_M TDI_M

H_FERR#

H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16

H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 H_A#32 H_A#33 H_A#34 H_A#35

C685 180P_0402_50V8J@C685 180P_0402_50V8J@

AA4 AB2 AA3

D22

J4 L5 L4

K5

M3

N2

J1 N3 P5 P2

L2 P4 P1 R1

M1

K3 H2 K2

J3

L1 Y2

U5 R3

W6

U4 Y5 U1 R4 T5 T3

W2 W5

Y4 U2 V4

W3

V1 A6

A5 C4

D5 C6 B4 A3

M4

N5 T2 V3 B2 D2

D3 F6

@ JP1A

JP1A

A[3]# A[4]# A[5]# A[6]# A[7]# A[8]# A[9]# A[10]# A[11]# A[12]# A[13]# A[14]# A[15]# A[16]# ADSTB[0]#

REQ[0]# REQ[1]# REQ[2]# REQ[3]# REQ[4]#

A[17]# A[18]# A[19]# A[20]# A[21]# A[22]# A[23]# A[24]# A[25]# A[26]# A[27]# A[28]# A[29]# A[30]# A[31]# A[32]# A[33]# A[34]# A[35]# ADSTB[1]#

A20M# FERR# IGNNE#

STPCLK# LINT0 LINT1 SMI#

RSVD[01] RSVD[02] RSVD[03] RSVD[04] RSVD[05] RSVD[06] RSVD[07] RSVD[08] RSVD[09]

Penryn

12

ADDR GROUP_0

ADS# BNR# BPRI#

DEFER#

DRDY# DBSY#

BR0#

IERR#

INIT#

LOCK#

CONTROL

RESET#

RS[0]# RS[1]# RS[2]#

TRDY#

HIT#

HITM#

ADDR GROUP_1

BPM[0]# BPM[1]# BPM[2]# BPM[3]#

PRDY# PREQ#

TCK

TDI TDO TMS

TRST#

DBR#

XDP/ITP SIGNALS

THERMAL

PROCHOT#

THERMDA THERMDC

ICH

THERMTRIP#

H CLK

BCLK[0] BCLK[1]

RESERVED

H1 E2 G5

H5 F21 E1

F1 D20

B3 H4 C1

F3 F4 G3 G2

G6 E4

AD4 AD3 AD1 AC4 AC2 AC1 AC5 AA6 AB3 AB5 AB6 C20

D21 A24 B25

C7

A22 A21

H_IERR# H_INIT#

H_RESET#

XDP_DBRESET#

H_PROCHOT# H_THERMDA H_THERMDC

Reserve for debug close to South Bridge

4

H_ADS# <7> H_BNR# <7>

H_BPRI# <7>

H_DEFER# <7> H_DRDY# <7> H_DBSY# <7>

1 2

H_BR0# <7>

H_INIT# <21> H_LOCK# <7>

H_RESET# <7>

H_RS#0 <7>

H_RS#1 <7>

H_RS#2 <7>

H_TRDY# <7>

H_HIT# <7> H_HITM# <7>

XDP_DBRESET# <22>

H_THERMTRIP# <8,21>

+CPU_GTLREF2

R1 49.9_0402_1%R1 49.9_0402_1%

XDP_BPM#0 XDP_BPM#1 XDP_BPM#2 XDP_BPM#3 XDP_BPM#4 XDP_BPM#5

XDP_TCK XDP_TDI XDP_TDO XDP_TMS

XDP_TRST#

CLK_CPU_BCLK <16> CLK_CPU_BCLK# <16>

QC: ES1: DePOP ALL ES2: POP ALL DC: DEPOP ALL

XDP_BPM2#3<5>

+1.05VS

XDP_TMS

R137 51_0402_1%R137 51_0402_1%

XDP_BPM#5

R985

XDP_TDI XDP_TRST# XDP_TCK

1 2

R4 51_0402_1%R4 51_0402_1%

1 2

R6 51_0402_1%R6 51_0402_1%

1 2

R136 51_0402_1%R136 51_0402_1%

Place close to CPU within 200ps = 1000 mil

Pull-High for ITP.

H_RESET#

1 2

R5 49.9_0402_1%@R5 49.9_0402_1%@

PROCHOT# PU: 68Ohm near CPU and MVP6. 56Ohm near CPU

+1.05VS

H_THERMDA, H_THERMDC routing together, Trace width / Spacing = 10 / 10 mil

+1.05VS

Quad Core support circuit

12

R942

@R942

@

1K_0402_1%

12

13

D

@R944

@

D

BSS138_NL_SOT23-3

S

R944

2K_0402_1%

Layout close CPU PIN D22

Q129

G

2

1 2

R7 56_0402_5%@R7 56_0402_5%@

1 2

R8 68_0402_5%R8 68_0402_5%

H_PROCHOT#

+3VALW

12

R943 100K_0402_5%

100K_0402_5%

@

C

E

3 1

Q20

Q20 MMBT3904_NL_SOT23-3

MMBT3904_NL_SOT23-3

50 ohm, 0.5 inch (max)

3

XDP_BPM2#0 XDP_BPM2#1 XDP_BPM2#2 XDP_BPM2#3

12

51_0402_1%

@R985

51_0402_1%

@

+1.05VS

@R943

@

R946

10K_0402_5%

2

B

@

R977 R979 R981 R983

+1.05VS

E

3 1

+3VALW

@R946

@

12

@R977

@ @R979

@ @R981

@ @R983

@

B

2

12

R945 100K_0402_5%

100K_0402_5%

+1.05VS

51_0402_1%

51_0402_1% 51_0402_1%

51_0402_1%

+1.05VS

C155 0.1U_0402_16V4ZC155 0.1U_0402_16V4Z

Q1

@

Q1

@

MMBT3904_NL_SOT23-3

C

@R945

@

QUAD_DET <5>

12

OCP# <22>

+3VS

2

XDP_BPM#2 XDP_BPM#1

XDP_BPM2#2 XDP_BPM2#1

XDP_DBRESET# XDP_TRST# XDP_TMS

0.1U_0402_16V4Z

H_THERMDA

C2

H_THERMDC

1 2

2200P_0402_50V7K

R2

1 2

10K_0402_5%

DVT- Change CPU Debug port.

XDP Connector

JP3

@JP3

@

1

3

5

7

9

11

13

15

17

19

21

23

25

27

29

29 GND31GND

GND33GND

P-TWO_196027-30041

+3VS

EVT2- Change U1, thermal sensor source from ADI to SMSC

1

C1

2

CPU_THERM#

U1

1

VDD

2

DP

3

DN

4

THERM#

EMC1402-1-ACZL-TR_MSOP8

2 4 6

8 10 12 14 16 18 20 22 24 26 28 30

2 4 6 8 10 12 14

H_PWRGOOD_R

16 18 20 22 24 26 28 30

32 34

1

XDP_BPM#4XDP_BPM#5 XDP_BPM#3

XDP_BPM#0

XDP_BPM2#3 XDP_BPM2#0

XDP_TDO XDP_TDI XDP_PRE#

SMCLK

SMDATA

ALERT#

GND

R147

1 2

XDP_TCK

1K_0402_5%

CLK_XDP# <16>CLK_XDP<16>

1 2

R78 1K_0402_5%R78 1K_0402_5%

+1.05VS

1 2

R138 51_0402_1%R138 51_0402_1% R18 10K_0402_5%R18 10K_0402_5%

Place close to JITP within 200ps = 1000 mil

8 7 6

10K_0402_5%@R310K_0402_5%@

5

H_PWRGOOD <5,21>

H_RESET#H_RESET#_R

XDP_TDO XDP_PRE#

12

EC_SMB_CK2 <17,32> EC_SMB_DA2 <17,32>

R3

12

Reserve for Source control

+3VS

H_SMI# H_INIT# H_NMI H_A20M# H_INTR H_IGNNE#

H_STPCLK#

A A

5

C687 180P_0402_50V8J@C687 180P_0402_50V8J@ C688 180P_0402_50V8J@C688 180P_0402_50V8J@ C678 180P_0402_50V8J@C678 180P_0402_50V8J@ C691 180P_0402_50V8J@C691 180P_0402_50V8J@ C692 180P_0402_50V8J@C692 180P_0402_50V8J@ C690 180P_0402_50V8J@C690 180P_0402_50V8J@ C694 180P_0402_50V8J@C694 180P_0402_50V8J@

12 12 12 12 12 12 12

Reserve for debug close to CPU

4

FAN Control Circuit

+5VS

+FAN1

EN_DFAN1<32>

EN_DFAN1

1

C7

C7 10U_0805_10V4Z

10U_0805_10V4Z

2

DVT-Change FAN Driver from SA009930010-G993P1UF to SA00002GW00-G990P11U

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2008/10/1 2009/10/1

3

C6 10U_0805_10V4ZC6 10U_0805_10V4Z

1 2

U2

1

VEN

2 3 4

Compal Secret Data

GND

VIN

GND GND

VO

GND

VSET

G990P11U_SOP8

Deciphered Date

8 7 6 5

2

C3 1000P_0402_50V7K@C31000P_0402_50V7K@

1

2

+5VS

JP2

12

D1

D1 1SS355_SOD323-2

1SS355_SOD323-2

+FAN1

12

D2

D2 BAS16_SOT23-3

BAS16_SOT23-3

2

1

Title

Size Document Number Rev

B

Date: Sheet

JP2

5

GND

4

GND

3

2

1

ACES_85205-03001

R13 10K_0402_5%R13 10K_0402_5%

12

+3VS

C5

0.01U_0402_25V4Z

Compal Electronics, Inc.

SCHEMATICS,M/B A4161

401562 G

1

FAN_SPEED1 <32>

of

448Monday, February 23, 2009

of

448Monday, February 23, 2009

of

448Monday, February 23, 2009

5

@

G22 G25

G24

H26 H25

M24 M23

R24

N25 M26

N24

AD26

C23 D25 C24

AF26

AF1

C21

1

0

E22 F24 E26

F23 E25

E23 K24

H22 F26 K22 H23

N22 K25 P26 R23 L23

L22 P25

P23 P22 T24

L25 T25

L26

A26 B22

B23

J24 J23

J26

C3

@ JP1B

JP1B

D[0]# D[1]# D[2]# D[3]# D[4]# D[5]# D[6]# D[7]# D[8]# D[9]# D[10]# D[11]# D[12]# D[13]# D[14]# D[15]# DSTBN[0]# DSTBP[0]# DINV[0]#

D[16]# D[17]# D[18]# D[19]# D[20]# D[21]# D[22]# D[23]# D[24]# D[25]# D[26]# D[27]# D[28]# D[29]# D[30]# D[31]# DSTBN[1]# DSTBP[1]# DINV[1]#

GTLREF TEST1 TEST2 TEST3 TEST4 TEST5 TEST6 TEST7 BSEL[0] BSEL[1] BSEL[2]

Penryn

H_D#[0..15]<7>

D D

H_DSTBN#0<7> H_DSTBP#0<7> H_DINV#0<7> H_D#[16..31]<7>

+1.05VS

Close to CPU pin

12

C C

1K_0402_1%

2K_0402_1%

AD26 within

R15

500mils.

+CPU_GTLREF

12

R20

layout note: Route TEST3 & TEST5 traces on ground referenced layer to the TPs

H_DSTBN#1<7> H_DSTBP#1<7> H_DINV#1<7>

CPU_BSEL0<8,16> CPU_BSEL1<8,16> CPU_BSEL2<8,16>

CPU_BSEL CPU_BSEL2 CPU_BSEL1

B B

166

200

01

0

+CPU_GTLREF

1

H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15

H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31

CPU_BSEL0

266 0 0 0

DATA GRP 0

MISC

DATA GRP 1

4

D[32]# D[33]# D[34]# D[35]# D[36]# D[37]# D[38]# D[39]# D[40]#

DATA GRP 2DATA GRP 3

D[41]# D[42]# D[43]# D[44]# D[45]# D[46]#

D[47]# DSTBN[2]# DSTBP[2]#

DINV[2]#

D[48]#

D[49]#

D[50]#

D[51]#

D[52]#

D[53]#

D[54]#

D[55]#

D[56]#

D[57]#

D[58]#

D[59]#

D[60]#

D[61]#

D[62]#

D[63]# DSTBN[3]# DSTBP[3]#

DINV[3]# COMP[0]

COMP[1] COMP[2] COMP[3]

DPRSTP#

DPSLP#

DPWR#

PWRGOOD

SLP#

PSI#

H_CPUSLP#

H_PWRGOOD

H_DPRSTP# H_DPSLP#

Y22 AB24 V24 V26 V23 T22 U25 U23 Y25 W22 Y23 W24 W25 AA23 AA24 AB25 Y26 AA26 U22

AE24 AD24 AA21 AB22 AB21 AC26 AD20 AE22 AF23 AC25 AE21 AD21 AC22 AD23 AF22 AC23 AE25 AF24 AC20

R26 U26 AA1 Y1

E5 B5 D24 D6 D7 AE6

C693 180P_0402_50V8J@C693 180P_0402_50V8J@ C695 180P_0402_50V8J@C695 180P_0402_50V8J@ C697 180P_0402_50V8J@C697 180P_0402_50V8J@ C696 180P_0402_50V8J@C696 180P_0402_50V8J@

H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47

H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63

COMP0 COMP1 COMP2 COMP3

H_DPRSTP# H_DPSLP#

H_PWRGOOD H_CPUSLP#

12 12 12 12

H_D#[32..47] <7>

H_DSTBN#2 <7> H_DSTBP#2 <7> H_DINV#2 <7> H_D#[48..63] <7>

H_DSTBN#3 <7> H_DSTBP#3 <7> H_DINV#3 <7>

H_DPRSTP# <8,21,42> H_DPSLP# <21>

H_DPWR# <7> H_PWRGOOD <4,21> H_CPUSLP# <7>

H_PSI# <42>

Reserve for debug close to CPU

3

Resistor placed within

0.5" of CPU pin.Trace should be at least 25 mils away from any other toggling signal. COMP[0,2] trace width is 18 mils. COMP[1,3] trace width is 4 mils.

COMP0

1 2

R16 27.4_0402_1%R16 27.4_0402_1%

COMP1

1 2

R19 54.9_0402_1%R19 54.9_0402_1%

COMP2

1 2

R21 27.4_0402_1%R21 27.4_0402_1%

COMP3

1 2

R22 54.9_0402_1%R22 54.9_0402_1%

2

D8 pin Reserved for QC

QUAD_DET<4>

Pin F8 Dual Core: GND (internal) Quad Core: Floating (internal)

@

@ JP1D

JP1D

A4

VSS[001]

A8

VSS[002]

A11

VSS[003]

A14

VSS[004]

A16

VSS[005]

A19

VSS[006]

A23

VSS[007]

AF2

VSS[008]

B6

VSS[009]

B8

VSS[010]

B11

VSS[011]

B13

VSS[012]

B16

VSS[013]

B19

VSS[014]

B21

VSS[015]

B24

VSS[016]

C5

VSS[017]

C8

VSS[018]

C11

VSS[019]

C14

VSS[020]

C16

VSS[021]

C19

VSS[022]

C2

VSS[023]

C22

VSS[024]

C25

VSS[025]

D1

VSS[026]

D4

VSS[027]

D8

VSS[028]

D11

VSS[029]

D13

VSS[030]

D16

VSS[031]

D19

VSS[032]

D23

VSS[033]

D26

VSS[034]

E3

VSS[035]

E6

VSS[036]

E8

VSS[037]

E11

VSS[038]

E14

VSS[039]

E16

VSS[040]

E19

VSS[041]

E21

VSS[042]

E24

VSS[043]

F5

VSS[044]

F8

VSS[045]

F11

VSS[046]

F13

VSS[047]

F16

VSS[048]

F19

VSS[049]

F2

VSS[050]

F22

VSS[051]

F25

VSS[052]

G4

VSS[053]

G1

VSS[054]

G23

VSS[055]

G26

VSS[056]

H3

VSS[057]

H6

VSS[058]

H21

VSS[059]

H24

VSS[060]

J2

VSS[061]

J5

VSS[062]

J22

VSS[063]

J25

VSS[064]

K1

VSS[065]

K4

VSS[066]

K23

VSS[067]

K26

VSS[068]

L3

VSS[069]

L6

VSS[070]

L21

VSS[071]

L24

VSS[072]

M2

VSS[073]

M5

VSS[074]

M22

VSS[075]

M25

VSS[076]

N1

VSS[077]

N4

VSS[078]

N23

VSS[079]

N26

VSS[080] VSS[081]P3VSS[162]

Penryn

VSS[082] VSS[083] VSS[084] VSS[085] VSS[086] VSS[087] VSS[088] VSS[089] VSS[090] VSS[091] VSS[092] VSS[093] VSS[094] VSS[095] VSS[096] VSS[097] VSS[098] VSS[099] VSS[100] VSS[101] VSS[102] VSS[103] VSS[104] VSS[105] VSS[106] VSS[107] VSS[108] VSS[109] VSS[110] VSS[111] VSS[112] VSS[113] VSS[114] VSS[115] VSS[116] VSS[117] VSS[118] VSS[119] VSS[120] VSS[121] VSS[122] VSS[123] VSS[124] VSS[125] VSS[126] VSS[127] VSS[128] VSS[129] VSS[130] VSS[131] VSS[132] VSS[133] VSS[134] VSS[135] VSS[136] VSS[137] VSS[138] VSS[139] VSS[140] VSS[141] VSS[142] VSS[143] VSS[144] VSS[145] VSS[146] VSS[147] VSS[148] VSS[149] VSS[150] VSS[151] VSS[152] VSS[153] VSS[154] VSS[155] VSS[156] VSS[157] VSS[158] VSS[159] VSS[160] VSS[161]

VSS[163]

1

P6 P21 P24 R2 R5 R22 R25 T1 T4 T23 T26 U3 U6 U21 U24 V2 V5 V22 V25 W1 W4 W23 W26 Y3 Y6 Y21 Y24 AA2 AA5 AA8 AA11 AA14 AA16 AA19 AA22 AA25 AB1 AB4 AB8 AB11 AB13 AB16 AB19 AB23 AB26 AC3 AC6 AC8 AC11 AC14 AC16 AC19 AC21 AC24 AD2 AD5 AD8 AD11 AD13 AD16 AD19 AD22 AD25 AE1 AE4 AE8 AE11 AE14 AE16 AE19 AE23 AE26 A2 AF6 AF8 AF11 AF13 AF16 AF19 AF21 A25 AF25

.

AA8 pin Reserved for QC

AC8 pin Reserved for QC

XDP_BPM2#3 <4>

For QC

A A

Security Classification

2008/10/1 2009/10/1

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2008/10/1 2009/10/1

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

B

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

SCHEMATICS,M/B A4161

401562 G

1

of

548Monday, February 23, 2009

of

548Monday, February 23, 2009

of

548Monday, February 23, 2009

5

VCC[068] VCC[069] VCC[070] VCC[071] VCC[072] VCC[073] VCC[074] VCC[075] VCC[076] VCC[077] VCC[078] VCC[079] VCC[080] VCC[081] VCC[082] VCC[083] VCC[084] VCC[085] VCC[086] VCC[087] VCC[088] VCC[089] VCC[090] VCC[091] VCC[092] VCC[093] VCC[094] VCC[095] VCC[096] VCC[097] VCC[098] VCC[099] VCC[100]

VCCP[01] VCCP[02] VCCP[03] VCCP[04] VCCP[05] VCCP[06] VCCP[07] VCCP[08] VCCP[09] VCCP[10] VCCP[11] VCCP[12] VCCP[13] VCCP[14] VCCP[15] VCCP[16]

VCCA[01] VCCA[02]

VID[0] VID[1] VID[2] VID[3] VID[4] VID[5] VID[6]

VCCSENSE

VSSSENSE

+CPU_CORE

330U_D2E_2.5VM_R7

1

C8

2

AB20 AB7 AC7 AC9 AC12 AC13 AC15 AC17 AC18 AD7 AD9 AD10 AD12 AD14 AD15 AD17 AD18 AE9 AE10 AE12 AE13 AE15 AE17 AE18 AE20 AF9 AF10 AF12 AF14 AF15 AF17 AF18 AF20

G21 V6 J6 K6 M6 J21 K21 M21 N21 N6 R21 R6 T21 T6 V21 W21

B26 C26

AD6 AF5 AE5 AF4 AE3 AF3 AE2

AF7

AE7

.

VCCSENSE

Near CPU CORE regulator

ESR <= 1.5m ohm Capacitor > 1980uF

D D

+CPU_CORE +CPU_CORE

C C

BR1#

B B

AA10 AA12 AA13 AA15 AA17 AA18 AA20

AC10 AB10 AB12 AB14 AB15 AB17 AB18

A10 A12 A13 A15 A17 A18 A20

B10 B12 B14 B15 B17 B18 B20

C10 C12 C13 C15 C17 C18

D10 D12 D14 D15 D17 D18

E10 E12 E13 E15 E17 E18 E20

F10 F12 F14 F15 F17 F18 F20 AA7 AA9

AB9

A7 A9

B7 B9

C9

D9

E7 E9

F7 F9

@

@ JP1C

JP1C

VCC[001] VCC[002] VCC[003] VCC[004] VCC[005] VCC[006] VCC[007] VCC[008] VCC[009] VCC[010] VCC[011] VCC[012] VCC[013] VCC[014] VCC[015] VCC[016] VCC[017] VCC[018] VCC[019] VCC[020] VCC[021] VCC[022] VCC[023] VCC[024] VCC[025] VCC[026] VCC[027] VCC[028] VCC[029] VCC[030] VCC[031] VCC[032] VCC[033] VCC[034] VCC[035] VCC[036] VCC[037] VCC[038] VCC[039] VCC[040] VCC[041] VCC[042] VCC[043] VCC[044] VCC[045] VCC[046] VCC[047] VCC[048] VCC[049] VCC[050] VCC[051] VCC[052] VCC[053] VCC[054] VCC[055] VCC[056] VCC[057] VCC[058] VCC[059] VCC[060] VCC[061] VCC[062] VCC[063] VCC[064] VCC[065] VCC[066] VCC[067]

Penryn

DVT-Delete C10 for Layout problem.

1

+

C9

2

330U_D2E_2.5VM_R7

VCCSENSE

VSSSENSE

+1.05VS

VCCSENSE <42>

VSSSENSE <42>

4

1

+

C11

2

330U_D2E_2.5VM_R7

1

+

C44

C44 330U_D2E_2.5VM_R7

330U_D2E_2.5VM_R7

2

Near pin B26

CPU_VID0 <42> CPU_VID1 <42> CPU_VID2 <42> CPU_VID3 <42> CPU_VID4 <42> CPU_VID5 <42> CPU_VID6 <42>

+CPU_CORE

R23100_0402_1% R23100_0402_1%

12

Place these capacitors on L8 (North side,Secondary Layer)

Place these capacitors on L8 (Sorth side,Secondary Layer)

Mid Frequence Decoupling

Place these inside socket cavity on L8

+1.05VS

(North side Secondary)

1

2

1

C51

0.01U_0402_25V4Z

2

C45

0.1U_0402_16V4Z

1

C52

C52 10U_0805_10V4Z

10U_0805_10V4Z

2

+1.5VS

1

C46

0.1U_0402_16V4Z

2

+CPU_CORE

1

2

+CPU_CORE

1

2

+CPU_CORE

1

2

+CPU_CORE

1

2

3

C12

C12 10U_0805_6.3V6M

10U_0805_6.3V6M

C20

C20 10U_0805_6.3V6M

10U_0805_6.3V6M

C28

C28 10U_0805_6.3V6M

10U_0805_6.3V6M

C36

C36 10U_0805_6.3V6M

10U_0805_6.3V6M

1

C47

0.1U_0402_16V4Z

2

1

C13

C13 10U_0805_6.3V6M

10U_0805_6.3V6M

2

1

C21

C21 10U_0805_6.3V6M

10U_0805_6.3V6M

2

1

C29

C29 10U_0805_6.3V6M

10U_0805_6.3V6M

2

1

C37

C37 10U_0805_6.3V6M

10U_0805_6.3V6M

2

1

C48

0.1U_0402_16V4Z

2

1

C14

C14 10U_0805_6.3V6M

10U_0805_6.3V6M

2

1

C22

C22 10U_0805_6.3V6M

10U_0805_6.3V6M

2

1

C30

C30 10U_0805_6.3V6M

10U_0805_6.3V6M

2

1

C38

C38 10U_0805_6.3V6M

10U_0805_6.3V6M

2

1

C49

0.1U_0402_16V4Z

2

1

C15

C15 10U_0805_6.3V6M

10U_0805_6.3V6M

2

1

C23

C23 10U_0805_6.3V6M

10U_0805_6.3V6M

2

1

C31

C31 10U_0805_6.3V6M

10U_0805_6.3V6M

2

1

C39

C39 10U_0805_6.3V6M

10U_0805_6.3V6M

2

1

C50

0.1U_0402_16V4Z

2

1

C16

C16 10U_0805_6.3V6M

10U_0805_6.3V6M

2

1

C24

C24 10U_0805_6.3V6M

10U_0805_6.3V6M

2

1

C32

C32 10U_0805_6.3V6M

10U_0805_6.3V6M

2

1

C40

C40 10U_0805_6.3V6M

10U_0805_6.3V6M

2

1

C17

C17 10U_0805_6.3V6M

10U_0805_6.3V6M

2

1

C25

C25 10U_0805_6.3V6M

10U_0805_6.3V6M

2

1

C33

C33 10U_0805_6.3V6M

10U_0805_6.3V6M

2

1

C41

C41 10U_0805_6.3V6M

10U_0805_6.3V6M

2

1

C18

C18 10U_0805_6.3V6M

10U_0805_6.3V6M

2

1

C26

C26 10U_0805_6.3V6M

10U_0805_6.3V6M

2

1

C34

C34 10U_0805_6.3V6M

10U_0805_6.3V6M

2

1

C42

C42 10U_0805_6.3V6M

10U_0805_6.3V6M

2

1

C19

C19 10U_0805_6.3V6M

10U_0805_6.3V6M

2

1

C27

C27 10U_0805_6.3V6M

10U_0805_6.3V6M

2

1

C35

C35 10U_0805_6.3V6M

10U_0805_6.3V6M

2

1

C43

C43 10U_0805_6.3V6M

10U_0805_6.3V6M

2

VSSSENSE

A A

Close to CPU pin

R24100_0402_1% R24100_0402_1%

12

within 500mils.

Security Classification

Length match within 25 mils. The trace width/space/other is 20/7/25.

5

Security Classification

2008/10/1 2009/10/1

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2008/10/1 2009/10/1

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

B

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

SCHEMATICS,M/B A4161

401562 G

1

of

648Monday, February 23, 2009

of

648Monday, February 23, 2009

of

648Monday, February 23, 2009

5

4

3

2

1

U3A

H_D#[0..63]<5>

D D

C C

Layout Note: H_RCOMP / H_VREF / H_SWNG

trace width and spacing is 10/20

within 100 mils from NB

+1.05VS+1.05VS

12

B B

R25

R25 1K_0402_1%

1K_0402_1%

12

R27

R27 2K_0402_1%

2K_0402_1%

1

C53

0.1U_0402_16V4Z

2

H_RCOMP +H_SWNG+H_VREF

12

R28

24.9_0402_1%

12

R26

R26 221_0402_1%

221_0402_1%

12

R29

R29 100_0402_1%

100_0402_1%

1

C54

0.1U_0402_16V4Z

2

H_RESET#<4>

H_CPUSLP#<5>

Near B3 pin

H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31 H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63

+H_SWNG H_RCOMP

+H_VREF

U3A

F2

H_D#_0

G8

H_D#_1

F8

H_D#_2

E6

H_D#_3

G2

H_D#_4

H6

H_D#_5

H2

H_D#_6

F6

H_D#_7

D4

H_D#_8

H3

H_D#_9

M9

H_D#_10

M11

H_D#_11

J1

H_D#_12

J2

H_D#_13

N12

H_D#_14

J6

H_D#_15

P2

H_D#_16

L2

H_D#_17

R2

H_D#_18

N9

H_D#_19

L6

H_D#_20

M5

H_D#_21

J3

H_D#_22

N2

H_D#_23

R1

H_D#_24

N5

H_D#_25

N6

H_D#_26

P13

H_D#_27

N8

H_D#_28

L7

H_D#_29

N10

H_D#_30

M3

H_D#_31

Y3

H_D#_32

AD14

H_D#_33

Y6

H_D#_34

Y10

H_D#_35

Y12

H_D#_36

Y14

H_D#_37

Y7

H_D#_38

W2

H_D#_39

AA8

H_D#_40

Y9

H_D#_41

AA13

H_D#_42

AA9

H_D#_43

AA11

H_D#_44

AD11

H_D#_45

AD10

H_D#_46

AD13

H_D#_47

AE12

H_D#_48

AE9

H_D#_49

AA2

H_D#_50

AD8

H_D#_51

AA3

H_D#_52

AD3

H_D#_53

AD7

H_D#_54

AE14

H_D#_55

AF3

H_D#_56

AC1

H_D#_57

AE3

H_D#_58

AC3

H_D#_59

AE11

H_D#_60

AE8

H_D#_61

AG2

H_D#_62

AD6

H_D#_63

C5

H_SWING

E3

H_RCOMP

C12

H_CPURST#

E11

H_CPUSLP#

A11

H_AVREF

B11

H_DVREF

CANTIGA ES_FCBGA1329

GMR3@

H_ADSTB#_0 H_ADSTB#_1

H_BREQ#

H_DEFER#

HOST

H_DBSY#

HPLL_CLK

HPLL_CLK#

H_DPWR#

H_DRDY#

H_HITM# H_LOCK# H_TRDY#

H_DINV#_0 H_DINV#_1 H_DINV#_2 H_DINV#_3

H_DSTBN#_0 H_DSTBN#_1 H_DSTBN#_2 H_DSTBN#_3

H_DSTBP#_0 H_DSTBP#_1 H_DSTBP#_2 H_DSTBP#_3

H_REQ#_0 H_REQ#_1 H_REQ#_2 H_REQ#_3 H_REQ#_4

H_RS#_0

H_RS#_1

H_RS#_2

H_A#_3 H_A#_4 H_A#_5 H_A#_6 H_A#_7 H_A#_8

H_A#_9 H_A#_10 H_A#_11 H_A#_12 H_A#_13 H_A#_14 H_A#_15 H_A#_16 H_A#_17 H_A#_18 H_A#_19 H_A#_20 H_A#_21 H_A#_22 H_A#_23 H_A#_24 H_A#_25 H_A#_26 H_A#_27 H_A#_28 H_A#_29 H_A#_30 H_A#_31 H_A#_32 H_A#_33 H_A#_34 H_A#_35

H_ADS#

H_BNR# H_BPRI#

H_HIT#

A14 C15 F16 H13 C18 M16 J13 P16 R16 N17 M13 E17 P17 F17 G20 B19 J16 E20 H16 J20 L17 A17 B17 L16 C21 J17 H20 B18 K17 B20 F21 K21 L20

H12 B16 G17 A9 F11 G12 E9 B10 AH7 AH6 J11 F9 H9 E12 H11 C9

J8 L3 Y13 Y1

L10 M7 AA5 AE6

L9 M8 AA6 AE5

B15 K13 F13 B13 B14

B6 F12 C8

H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16 H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 H_A#32 H_A#33 H_A#34 H_A#35

CLK_MCH_BCLK CLK_MCH_BCLK#

H_A#[3..35] <4>

H_ADS# <4> H_ADSTB#0 <4> H_ADSTB#1 <4>

H_BNR# <4> H_BPRI# <4>

H_BR0# <4> H_DEFER# <4>

H_DBSY# <4> CLK_MCH_BCLK <16> CLK_MCH_BCLK# <16> H_DPWR# <5>

H_DRDY# <4> H_HIT# <4> H_HITM# <4> H_LOCK# <4> H_TRDY# <4>

H_DINV#0 <5> H_DINV#1 <5> H_DINV#2 <5> H_DINV#3 <5>

H_DSTBN#0 <5> H_DSTBN#1 <5> H_DSTBN#2 <5> H_DSTBN#3 <5>

H_DSTBP#0 <5> H_DSTBP#1 <5> H_DSTBP#2 <5> H_DSTBP#3 <5>

H_REQ#0 <4> H_REQ#1 <4> H_REQ#2 <4> H_REQ#3 <4> H_REQ#4 <4>

H_RS#0 <4> H_RS#1 <4> H_RS#2 <4>

A A

Security Classification

2008/10/1 2009/10/1

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2008/10/1 2009/10/1

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

B

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

SCHEMATICS,M/B A4161

401562 G

1

of

748Monday, February 23, 2009

of

748Monday, February 23, 2009

of

748Monday, February 23, 2009

Strap Pin Table

5

011 = FSB667

CFG[2:0]

CFG5 CFG6

D D

CFG7

CFG9 CFG10

CFG[13:12]

CFG16 CFG19

CFG20

(PCIE/SDVO select)

C C

B B

+3VS

A A

1 2

R67 10K_0402_5%R67 10K_0402_5%

010 = FSB800 000 = FSB1067

0 = DMI x 2 1 = DMI x 4

0 = iTPM Host Interface is enabled

1 = iTPM Host Interface is Disabled 0 = Intel Management Engine Crypto Transport Layer Security

(TLS) cipher suite with no confidentiality 1 = Intel Management Engine Crypto TLS cipher suite with

confidentiality 0 = Lane Reversal Enable

0 = PCIe Loopback Enable 1 = Disable

01 = All Z Mode Enabled 00 = Reserved 10 = XOR Mode Enabled 11 = Normal Operation

0 = Dynamic ODT Disabled 1 = Dynamic ODT Enabled

0 = Normal Operation 1 = DMI Lane Reversal Enable

0 = Only PCIE or SDVO is operational.

(Default)

*

(Default)

(Default) - can support disble by SW.

*

(Default)1 = Normal Operation

(Default)

*

(Default)

*

(Default)

*

(Default)

*

1 = PCIE/SDVO are operating simu.

R44 1K_0402_5%R44 1K_0402_5% R45 1K_0402_5%R45 1K_0402_5% R46 1K_0402_5%R46 1K_0402_5%

R47 2.21K_0402_1%@R47 2.21K_0402_1%@ R49 2.21K_0402_1%@R49 2.21K_0402_1%@ R51 2.21K_0402_1%@R51 2.21K_0402_1%@

R53 2.21K_0402_1%@R53 2.21K_0402_1%@ R55 2.21K_0402_1%@R55 2.21K_0402_1%@

R57 2.21K_0402_1%@R57 2.21K_0402_1%@ R59 2.21K_0402_1%@R59 2.21K_0402_1%@

R61 2.21K_0402_1%@R61 2.21K_0402_1%@

R62 4.02K_0402_1%@R62 4.02K_0402_1%@ R64 4.02K_0402_1%@R64 4.02K_0402_1%@

R66 0_0402_5%R66 0_0402_5%

R69 0_0402_5%R69 0_0402_5% R71 100_0402_5%R71 100_0402_5%

R72 0_0402_5%R72 0_0402_5% R73 0_0402_5%R73 0_0402_5%

GMCH_PWROK

1 2 1 2 1 2

1 2 1 2

1 2

1 2 1 2

1 2

1 2 1 2

PM_PWROK<22,32>

PM_EXTTS#_R

Use VGATE for GMCH_PWROK

VGATE<22,32,42>

PM_PWROK

5

CPU_BSEL0<5,16> CPU_BSEL1<5,16> CPU_BSEL2<5,16>

+3VS

PM_SYNC#<22>

PM_EXTTS#<14,15>

PLT_RST#<17,20,26..29,32,33> H_THERMTRIP#<4,21> PM_DPRSLPVR<22,42>

1 2

R75 0_0402_5%@R75 0_0402_5%@

1 2

R76 0_0402_5%R76 0_0402_5%

4

U3B

M36

RSVD1

N36

RSVD2

R33

RSVD3

T33

RSVD4

AH9

RSVD5

AH10

RSVD6

AH12

RSVD7

AH13

RSVD8

K12

RSVD9

AL34

RSVD10

AK34

RSVD11

AN35

RSVD12

AM35

RSVD13

T24

RSVD14

B31

RSVD15

B2

RSVD16

M1

RSVD17

AY21

RSVD20

BG23

RSVD22

BF23

RSVD23

BH18

RSVD24

BF18

RSVD25

4

MCH_CLKSEL0 MCH_CLKSEL1 MCH_CLKSEL2

MCH_CFG_5 MCH_CFG_6 MCH_CFG_7

MCH_CFG_9 MCH_CFG_10

MCH_CFG_12 MCH_CFG_13

MCH_CFG_16

MCH_CFG_19 MCH_CFG_20

PM_SYNC#_R

PM_EXTTS#_R GMCH_PWROK MCH_RSTIN# NB_THERMTRIP# DPRSLPVR

12 12 12

H_DPRSTP#<5,21,42>

T25

CFG_0

R25

CFG_1

P25

CFG_2

P20

CFG_3

P24

CFG_4

C25

CFG_5

N24

CFG_6

M24

CFG_7

E21

CFG_8

C23

CFG_9

C24

CFG_10

N21

CFG_11

P21

CFG_12

T21

CFG_13

R20

CFG_14

M20

CFG_15

L21

CFG_16

H21

CFG_17

P29

CFG_18

R28

CFG_19

T28

CFG_20

R29

PM_SYNC#

B7

PM_DPRSTP#

N33

PM_EXT_TS#_0

P32

PM_EXT_TS#_1

AT40

PWROK

AT11

RSTIN#

T20

THERMTRIP#

R32

DPRSLPVR

BG48

NC_1

BF48

NC_2

BD48

NC_3

BC48

NC_4

BH47

NC_5

BG47

NC_6

BE47

NC_7

BH46

NC_8

BF46

NC_9

BG45

NC_10

BH44

NC_11

BH43

NC_12

BH6

NC_13

BH5

NC_14

BG4

NC_15

BH3

NC_16

BF3

NC_17

BH2

NC_18

BG2

NC_19

BE2

NC_20

BG1

NC_21

BF1

NC_22

BD1

NC_23

BC1

NC_24

F1

NC_25

A47

NC_26

CANTIGA ES_FCBGA1329

CANTIGA ES_FCBGA1329 GMR3@

GMR3@

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

RSVD CFG PM NC

3

DDR CLK/ CONTROL/ COMPENSATIONHDA

DPLL_REF_SSCLK#

CLKDMIGRAPHICS VIDMEMISC

3

AP24

SA_CK_0

AT21

SA_CK_1

AV24

SB_CK_0

AU20

SB_CK_1

AR24

SA_CK#_0

AR21

SA_CK#_1

AU24

SB_CK#_0

AV20

SB_CK#_1

BC28

SA_CKE_0

AY28

SA_CKE_1

AY36

SB_CKE_0

BB36

SB_CKE_1

BA17

SA_CS#_0

AY16

SA_CS#_1

AV16

SB_CS#_0

AR13

SB_CS#_1

BD17

SA_ODT_0

AY17

SA_ODT_1

BF15

SB_ODT_O

AY13

SB_ODT_1

SM_RCOMP

SM_RCOMP#

SM_RCOMP_VOH

SM_RCOMP_VOL

SM_VREF

SM_PWROK

SM_REXT

SM_DRAMRST#

DPLL_REF_CLK

DPLL_REF_CLK#

DPLL_REF_SSCLK

PEG_CLK

PEG_CLK#

DMI_RXN_0 DMI_RXN_1 DMI_RXN_2 DMI_RXN_3

DMI_RXP_0 DMI_RXP_1 DMI_RXP_2 DMI_RXP_3

DMI_TXN_0 DMI_TXN_1 DMI_TXN_2 DMI_TXN_3

DMI_TXP_0 DMI_TXP_1 DMI_TXP_2 DMI_TXP_3

GFX_VID_0 GFX_VID_1 GFX_VID_2 GFX_VID_3 GFX_VID_4

GFX_VR_EN

CL_CLK

CL_DATA

CL_PWROK

CL_RST# CL_VREF

DDPC_CTRLCLK

DDPC_CTRLDATA

SDVO_CTRLCLK

SDVO_CTRLDATA

CLKREQ#

ICH_SYNC#

TSATN#

HDA_BCLK HDA_RST#

HDA_SDI

HDA_SDO

HDA_SYNC

2008/10/1 2009/10/1

SMRCOMP

BG22

SMRCOMP#

BH21

+SM_RCOMP_VOH

BF28

+SM_RCOMP_VOL

BH28

+SM_VREF

AV42

SM_PWROK

AR36

SM_REXT

BF17 BC36

CLK_DREF_96M

B38

CLK_DREF_96M#

A38

CLK_DREF_SSC

E41

CLK_DREF_SSC#

F41

CLK_MCH_3GPLL

F43

CLK_MCH_3GPLL#

E43

AE41 AE37 AE47 AH39

AE40 AE38 AE48 AH40

AE35 AE43 AE46 AH42

AD35 AE44 AF46 AH43

B33 B32 G33 F33 E33

C34

AH37 AH36 AN36 AJ35 AH34

N28 M28 G36 E36 K36 H36

B12

B28 B30 B29 C29 A28

+NB_CLVREF

0.1U_0402_16V4Z

PM_PWROK

+NB_CLVREF

+NB_CLVREF=0.355V

SDVO_SCLK SDVO_SDATA CLKREQ_3GPLL#

MCH_TSATN#

AZ_SDIN2_MCH_R

Compal Secret Data

DDRA_CLK0 <14> DDRA_CLK1 <14> DDRB_CLK0 <15> DDRB_CLK1 <15>

DDRA_CLK0# <14> DDRA_CLK1# <14> DDRB_CLK0# <15> DDRB_CLK1# <15>

DDRA_CKE0 <14> DDRA_CKE1 <14> DDRB_CKE0 <15> DDRB_CKE1 <15>

DDRA_SCS0# <14> DDRA_SCS1# <14> DDRB_SCS0# <15> DDRB_SCS1# <15>

DDRA_ODT0 <14> DDRA_ODT1 <14> DDRB_ODT0 <15> DDRB_ODT1 <15>

R33 80.6_0402_1%R33 80.6_0402_1%

1 2

R34 80.6_0402_1%R34 80.6_0402_1%

1 2

R37 0_0402_5%R37 0_0402_5%

1 2

R38 499_0402_1%R38 499_0402_1%

1 2

CLK_DREF_96M <16> CLK_DREF_96M# <16> CLK_DREF_SSC <16> CLK_DREF_SSC# <16>

CLK_MCH_3GPLL <16> CLK_MCH_3GPLL# <16>

DMI_ITX_MRX_N0 <20> DMI_ITX_MRX_N1 <20> DMI_ITX_MRX_N2 <20> DMI_ITX_MRX_N3 <20>

DMI_ITX_MRX_P0 <20> DMI_ITX_MRX_P1 <20> DMI_ITX_MRX_P2 <20> DMI_ITX_MRX_P3 <20>

DMI_MTX_IRX_N0 <20> DMI_MTX_IRX_N1 <20> DMI_MTX_IRX_N2 <20> DMI_MTX_IRX_N3 <20>

DMI_MTX_IRX_P0 <20> DMI_MTX_IRX_P1 <20> DMI_MTX_IRX_P2 <20> DMI_MTX_IRX_P3 <20>

CL_VREF should be

0.35 V

1

C60

2

CL_CLK0 <22> CL_DATA0 <22>

CL_RST#0 <22>

SDVO_SCLK <19> SDVO_SDATA <19>

CLKREQ_3GPLL# <16>

MCH_ICH_SYNC# <22>

AZ_BITCLK_MCH <21> AZ_RST_MCH# <21>

AZ_SDOUT_MCH <21> AZ_SYNC_MCH <21>

Deciphered Date

+1.05VS

1 2

2

20mil

R74

1K_0402_1%

R77

499_0402_1%

1 2

2

+SM_RCOMP_VOH

0.01U_0402_25V4Z

SM_DRAMRST# would be needed for DDR3 only

For Cantiga 80 Ohm

+1.8V

1

C59

0.1U_0402_16V4Z

2

CLK_DREF_96M CLK_DREF_96M# CLK_DREF_SSC CLK_DREF_SSC#

+1.8V

0.01U_0402_25V4Z

+SM_RCOMP_VOL

0.01U_0402_25V4Z

R35

R35 1K_0402_1%

1K_0402_1%

1 2

R39

R39 1K_0402_1%

1K_0402_1%

1 2

R40 0_0402_5%PM@R40 0_0402_5%PM@

1 2

R41 0_0402_5%PM@R41 0_0402_5%PM@

1 2

R42 0_0402_5%PM@R42 0_0402_5%PM@

1 2

R43 0_0402_5%PM@R43 0_0402_5%PM@

1 2

as close as possible to the related balls

Strap Pin Table

0 = No SDVO Card Present 1 = SDVO Card Present

0 = Digital DisplayPort Disable 1 = Digital DisplayPort Device Present

SDVO_SCLK

R79

SDVO_SDATA

R80

+1.05VS

12

R81

1K_0402_5%

12

B

2

Q4

E

3 1

MMBT3904_NL_SOT23-3

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

SCHEMATICS,M/B A4161

R84

33_0402_5%

33_0402_5% IHDMI@

IHDMI@

SDVO_CTRLDATA

54.9_0402_1%

MCH_TSATN#

AZ_SDIN2_MCH <21>

R83

1

+1.8V

12

R30

1K_0402_1%

2

1

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M C56

2

1

2

2.2K_0402_5%

12

GM@R79

GM@

2.2K_0402_5%

12

IHDMI@R80

IHDMI@

PM@R79

PM@

PM@R80

PM@

R82

R82 1K_0402_5%

1K_0402_5%

C56

1

3.01K_0402_1%

2

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M C58

C58

1

MCH_TSATN_EC# <32>

1

C55

C57

R79

0_0402_5%

R80

0_0402_5%

+3VS

12

C

401562 G

1K_0402_1%

R135

1 2

0_0402_5%

1 2

R134 0_0402_5%

0_0402_5%

848Monday, February 23, 2009

R31

R32

(Default)

*

(Default)DDPC_CTRLDATA

*

GM@R135

GM@

PM@R134

PM@

of

12

+3VS

5

D D

DDR_A_D[0..63]<14>

C C

B B

DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15 DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63

U3D

AJ38

SA_DQ_0

AJ41

SA_DQ_1

AN38

SA_DQ_2

AM38

SA_DQ_3

AJ36

SA_DQ_4

AJ40

SA_DQ_5

AM44

SA_DQ_6

AM42

SA_DQ_7

AN43

SA_DQ_8

AN44

SA_DQ_9

AU40

SA_DQ_10

AT38

SA_DQ_11

AN41

SA_DQ_12

AN39

SA_DQ_13

AU44

SA_DQ_14

AU42

SA_DQ_15

AV39

SA_DQ_16

AY44

SA_DQ_17

BA40

SA_DQ_18

BD43

SA_DQ_19

AV41

SA_DQ_20

AY43

SA_DQ_21

BB41

SA_DQ_22

BC40

SA_DQ_23

AY37

SA_DQ_24

BD38

SA_DQ_25

AV37

SA_DQ_26

AT36

SA_DQ_27

AY38

SA_DQ_28

BB38

SA_DQ_29

AV36

SA_DQ_30

AW36

SA_DQ_31

BD13

SA_DQ_32

AU11

SA_DQ_33

BC11

SA_DQ_34

BA12

SA_DQ_35

AU13

SA_DQ_36

AV13

SA_DQ_37

BD12

SA_DQ_38

BC12

SA_DQ_39

BB9

SA_DQ_40

BA9

SA_DQ_41

AU10

SA_DQ_42

AV9

SA_DQ_43

BA11

SA_DQ_44

BD9

SA_DQ_45

AY8

SA_DQ_46

BA6

SA_DQ_47

AV5

SA_DQ_48

AV7

SA_DQ_49

AT9

SA_DQ_50

AN8

SA_DQ_51

AU5

SA_DQ_52

AU6

SA_DQ_53

AT5

SA_DQ_54

AN10

SA_DQ_55

AM11

SA_DQ_56

AM5

SA_DQ_57

AJ9

SA_DQ_58

AJ8

SA_DQ_59

AN12

SA_DQ_60

AM13

SA_DQ_61

AJ11

SA_DQ_62

AJ12

SA_DQ_63

CANTIGA ES_FCBGA1329

CANTIGA ES_FCBGA1329 GMR3@

GMR3@

DDR SYSTEM MEMORY A

4

SA_BS_0 SA_BS_1 SA_BS_2

SA_RAS# SA_CAS#

SA_WE#

SA_DM_0 SA_DM_1 SA_DM_2 SA_DM_3 SA_DM_4 SA_DM_5 SA_DM_6 SA_DM_7

SA_DQS_0 SA_DQS_1 SA_DQS_2 SA_DQS_3 SA_DQS_4 SA_DQS_5 SA_DQS_6 SA_DQS_7

SA_DQS#_0 SA_DQS#_1 SA_DQS#_2 SA_DQS#_3 SA_DQS#_4 SA_DQS#_5 SA_DQS#_6 SA_DQS#_7

SA_MA_0 SA_MA_1 SA_MA_2 SA_MA_3 SA_MA_4 SA_MA_5 SA_MA_6 SA_MA_7 SA_MA_8

SA_MA_9 SA_MA_10 SA_MA_11 SA_MA_12 SA_MA_13 SA_MA_14

BD21 BG18 AT25

BB20 BD20 AY20

AM37 AT41 AY41 AU39 BB12 AY6 AT7 AJ5

AJ44 AT44 BA43 BC37 AW12 BC8 AU8 AM7

AJ43 AT43 BA44 BD37 AY12 BD8 AU9 AM8

BA21 BC24 BG24 BH24 BG25 BA24 BD24 BG27 BF25 AW24 BC21 BG26 BH26 BH17 AY25

DDR_A_DM0 DDR_A_DM1 DDR_A_DM2 DDR_A_DM3 DDR_A_DM4 DDR_A_DM5 DDR_A_DM6 DDR_A_DM7

DDR_A_DQS0 DDR_A_DQS1 DDR_A_DQS2 DDR_A_DQS3 DDR_A_DQS4 DDR_A_DQS5 DDR_A_DQS6 DDR_A_DQS7

DDR_A_DQS#0 DDR_A_DQS#1 DDR_A_DQS#2 DDR_A_DQS#3 DDR_A_DQS#4 DDR_A_DQS#5 DDR_A_DQS#6 DDR_A_DQS#7

DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8

DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 DDR_A_MA14

DDR_A_BS0 <14> DDR_A_BS1 <14> DDR_A_BS2 <14>

DDR_A_RAS# <14> DDR_A_CAS# <14> DDR_A_WE# <14>

DDR_A_DM[0..7] <14>

DDR_A_DQS[0..7] <14>

DDR_A_DQS#[0..7] <14>

DDR_A_MA[0..14] <14>

3

DDR_B_D[0..63]<15>

DDR_B_D0 DDR_B_D1 DDR_B_D2 DDR_B_D3 DDR_B_D4 DDR_B_D5 DDR_B_D6 DDR_B_D7 DDR_B_D8 DDR_B_D9 DDR_B_D10 DDR_B_D11 DDR_B_D12 DDR_B_D13 DDR_B_D14 DDR_B_D15 DDR_B_D16 DDR_B_D17 DDR_B_D18 DDR_B_D19 DDR_B_D20 DDR_B_D21 DDR_B_D22 DDR_B_D23 DDR_B_D24 DDR_B_D25 DDR_B_D26 DDR_B_D27 DDR_B_D28 DDR_B_D29 DDR_B_D30 DDR_B_D31 DDR_B_D32 DDR_B_D33 DDR_B_D34 DDR_B_D35 DDR_B_D36 DDR_B_D37 DDR_B_D38 DDR_B_D39 DDR_B_D40 DDR_B_D41 DDR_B_D42 DDR_B_D43 DDR_B_D44 DDR_B_D45 DDR_B_D46 DDR_B_D47 DDR_B_D48 DDR_B_D49 DDR_B_D50 DDR_B_D51 DDR_B_D52 DDR_B_D53 DDR_B_D54 DDR_B_D55 DDR_B_D56 DDR_B_D57 DDR_B_D58 DDR_B_D59 DDR_B_D60 DDR_B_D61 DDR_B_D62 DDR_B_D63

U3E

AK47 AH46 AP47 AP46

AJ46

AJ48 AM48 AP48 AU47 AU46 BA48 AY48 AT47 AR47 BA47 BC47 BC46 BC44 BG43

BF43 BE45 BC41

BF40

BF41 BG38

BF38 BH35 BG35 BH40 BG39 BG34 BH34 BH14 BG12 BH11

BG8

BH12

BF11

BF8 BG7 BC5 BC6

AY3

AY1

BF6

BF5

BA1 BD3

AV2 AU3 AR3 AN2

AY2

AV1

AP3 AR1

AL1

AL2

AJ1 AH1 AM2 AM3 AH3

AJ3

CANTIGA ES_FCBGA1329

CANTIGA ES_FCBGA1329 GMR3@

GMR3@

SB_DQ_0 SB_DQ_1 SB_DQ_2 SB_DQ_3 SB_DQ_4 SB_DQ_5 SB_DQ_6 SB_DQ_7 SB_DQ_8 SB_DQ_9 SB_DQ_10 SB_DQ_11 SB_DQ_12 SB_DQ_13 SB_DQ_14 SB_DQ_15 SB_DQ_16 SB_DQ_17 SB_DQ_18 SB_DQ_19 SB_DQ_20 SB_DQ_21 SB_DQ_22 SB_DQ_23 SB_DQ_24 SB_DQ_25 SB_DQ_26 SB_DQ_27 SB_DQ_28 SB_DQ_29 SB_DQ_30 SB_DQ_31 SB_DQ_32 SB_DQ_33 SB_DQ_34 SB_DQ_35 SB_DQ_36 SB_DQ_37 SB_DQ_38 SB_DQ_39 SB_DQ_40 SB_DQ_41 SB_DQ_42 SB_DQ_43 SB_DQ_44 SB_DQ_45 SB_DQ_46 SB_DQ_47 SB_DQ_48 SB_DQ_49 SB_DQ_50 SB_DQ_51 SB_DQ_52 SB_DQ_53 SB_DQ_54 SB_DQ_55 SB_DQ_56 SB_DQ_57 SB_DQ_58 SB_DQ_59 SB_DQ_60 SB_DQ_61 SB_DQ_62 SB_DQ_63

2

BC16

SB_BS_0

BB17

SB_BS_1

BB33

SB_BS_2

AU17

SB_RAS#

BG16

SB_CAS#

BF14

SB_WE#

DDR_B_DM0

AM47

SB_DM_0 SB_DM_1 SB_DM_2 SB_DM_3 SB_DM_4 SB_DM_5 SB_DM_6 SB_DM_7

SB_DQS_0 SB_DQS_1 SB_DQS_2 SB_DQS_3 SB_DQS_4 SB_DQS_5 SB_DQS_6 SB_DQS_7

SB_DQS#_0 SB_DQS#_1 SB_DQS#_2 SB_DQS#_3 SB_DQS#_4 SB_DQS#_5 SB_DQS#_6 SB_DQS#_7

SB_MA_0 SB_MA_1 SB_MA_2

DDR SYSTEM MEMORY B

SB_MA_3 SB_MA_4 SB_MA_5 SB_MA_6 SB_MA_7 SB_MA_8

SB_MA_9 SB_MA_10 SB_MA_11 SB_MA_12 SB_MA_13 SB_MA_14

AY47 BD40 BF35 BG11 BA3 AP1 AK2

AL47 AV48 BG41 BG37 BH9 BB2 AU1 AN6

AL46 AV47 BH41 BH37 BG9 BC2 AT2 AN5

AV17 BA25 BC25 AU25 AW25 BB28 AU28 AW28 AT33 BD33 BB16 AW33 AY33 BH15 AU33

DDR_B_DM1 DDR_B_DM2 DDR_B_DM3 DDR_B_DM4 DDR_B_DM5 DDR_B_DM6 DDR_B_DM7

DDR_B_DQS0 DDR_B_DQS1 DDR_B_DQS2 DDR_B_DQS3 DDR_B_DQS4 DDR_B_DQS5 DDR_B_DQS6 DDR_B_DQS7

DDR_B_DQS#0 DDR_B_DQS#1 DDR_B_DQS#2 DDR_B_DQS#3 DDR_B_DQS#4 DDR_B_DQS#5 DDR_B_DQS#6 DDR_B_DQS#7

DDR_B_MA0 DDR_B_MA1 DDR_B_MA2 DDR_B_MA3 DDR_B_MA4 DDR_B_MA5 DDR_B_MA6 DDR_B_MA7 DDR_B_MA8

DDR_B_MA9 DDR_B_MA10 DDR_B_MA11 DDR_B_MA12 DDR_B_MA13 DDR_B_MA14

1

DDR_B_BS0 <15> DDR_B_BS1 <15> DDR_B_BS2 <15>

DDR_B_RAS# <15> DDR_B_CAS# <15> DDR_B_WE# <15>

DDR_B_DM[0..7] <15>

DDR_B_DQS[0..7] <15>

DDR_B_DQS#[0..7] <15>

DDR_B_MA[0..14] <15>

A A

Security Classification

2008/10/1 2009/10/1

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2008/10/1 2009/10/1

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

B

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

SCHEMATICS,M/B A4161

401562 G

1

of

948Monday, February 23, 2009

of

948Monday, February 23, 2009

of

948Monday, February 23, 2009

5

LCTLA_CLK

GM@

12

+3VS

R132 0_0402_5%

0_0402_5%

R133 0_0402_5%

0_0402_5%

1 2

GM@R132

GM@

R86 10K_0402_5%

1 2

R88 10K_0402_5%

1 2

R89 2.2K_0402_5%

1 2

12

R90 2.2K_0402_5%

PM@R133

PM@

L_DDC_DATA

D D

1 = LFP Card Present; PCIE disable

C C

R92

PM@R92

PM@

0_0402_5%

R93

PM@R93

PM@

0_0402_5%

R94

PM@R94

PM@

0_0402_5%

R95

PM@R95

PM@

0_0402_5%

R96

PM@R96

PM@

0_0402_5%

R97

PM@R97

PM@

0_0402_5%

B B

0_0402_5%

R100

0_0402_5%

PM@R100

PM@

GM@

LCTLB_DATA

GM@

UMA_LCD_CLK

GM@

UMA_LCD_DAT

GM@

(Default)0 = LFP Disable

*

EVT2- Remove S-Vedio function.

1 2 1 2

UMA_TV_COMPS UMA_TV_LUMA UMA_TV_CRMA

UMA_CRT_CLK

UMA_CRT_DATA

UMA_CRT_HSYNC

12

UMA_CRT_VSYNC

12

R95 150_0402_1%GM@R95 150_0402_1%GM@ R96 150_0402_1%GM@R96 150_0402_1%GM@ R97 150_0402_1%GM@R97 150_0402_1%GM@

+3VS

1 2

R92 75_0402_1%GM@R92 75_0402_1%GM@

1 2

R93 75_0402_1%GM@R93 75_0402_1%GM@

1 2

R94 75_0402_1%GM@R94 75_0402_1%GM@

1 2 1 2 1 2

R98 4.7K_0402_5%GM@R98 4.7K_0402_5%GM@ R99 4.7K_0402_5%GM@R99 4.7K_0402_5%GM@

R101 0_0402_5%PM@R101 0_0402_5%PM@ R102 0_0402_5%PM@R102 0_0402_5%PM@

R86

PM@R86

PM@

0_0402_5%

R88

PM@R88

PM@

0_0402_5%

R89

PM@R89

PM@

0_0402_5%

R90

PM@R90

PM@

0_0402_5%

UMA_CRT_B UMA_CRT_G UMA_CRT_R

UMA_LCD_CLK<17> UMA_LCD_DAT<17>

GMCH_ENVDD<17>

UMA_TXOUT0-<17> UMA_TXOUT1-<17> UMA_TXOUT2-<17>

UMA_TXOUT0+<17> UMA_TXOUT1+<17> UMA_TXOUT2+<17>

UMA_TZOUT0-<17> UMA_TZOUT1-<17> UMA_TZOUT2-<17>

UMA_TZOUT0+<17> UMA_TZOUT1+<17> UMA_TZOUT2+<17>

Need to connect to GND if not used.

UMA_CRT_CLK<18> UMA_CRT_DATA<18>

UMA_CRT_HSYNC<18>

UMA_CRT_VSYNC<18>

UMA_ENBKL<32>

UMA_TXCLK-<17> UMA_TXCLK+<17> UMA_TZCLK-<17> UMA_TZCLK+<17>

UMA_CRT_B<18> UMA_CRT_G<18> UMA_CRT_R<18>

4

R91 2.37K_0402_1%GM@R91 2.37K_0402_1%GM@

R118 0_0402_5%GM@R118 0_0402_5%GM@ R126 0_0402_5%GM@R126 0_0402_5%GM@

R100 1.02K_0402_1%GM@R100 1.02K_0402_1%GM@

UMA_LCD_CLK UMA_LCD_DAT

1 2 1 2

1 2

UMA_TV_COMPS UMA_TV_LUMA UMA_TV_CRMA

UMA_CRT_B UMA_CRT_G UMA_CRT_R

UMA_CRT_CLK UMA_CRT_DATA UMA_CRT_HSYNC CRT_IREF

12

UMA_CRT_VSYNC

LCTLA_CLK LCTLB_DATA

LVDS_IBG

U3C

L32

L_BKLT_CTRL

G32

L_BKLT_EN

M32

L_CTRL_CLK

M33

L_CTRL_DATA

K33

L_DDC_CLK

J33

L_DDC_DATA

M29

L_VDD_EN

C44

LVDS_IBG

B43

LVDS_VBG

E37

LVDS_VREFH

E38

LVDS_VREFL

C41

LVDSA_CLK#

C40

LVDSA_CLK

B37

LVDSB_CLK#

A37

LVDSB_CLK

H47

LVDSA_DATA#_0

E46

LVDSA_DATA#_1

G40

LVDSA_DATA#_2

A40

LVDSA_DATA#_3

H48

LVDSA_DATA_0

D45

LVDSA_DATA_1

F40

LVDSA_DATA_2

B40

LVDSA_DATA_3

A41

LVDSB_DATA#_0

H38

LVDSB_DATA#_1

G37

LVDSB_DATA#_2

J37

LVDSB_DATA#_3

B42

LVDSB_DATA_0

G38

LVDSB_DATA_1

F37

LVDSB_DATA_2

K37

LVDSB_DATA_3

F25

TVA_DAC

H25

TVB_DAC

K25

TVC_DAC

H24

TV_RTN

C31

TV_DCONSEL_0

E32

TV_DCONSEL_1

E28

CRT_BLUE

G28

CRT_GREEN

J28

CRT_RED

G29

CRT_IRTN

H32

CRT_DDC_CLK

J32

CRT_DDC_DATA

J29

CRT_HSYNC

E29

CRT_TVO_IREF

L29

CRT_VSYNC

CANTIGA ES_FCBGA1329

CANTIGA ES_FCBGA1329 GMR3@

GMR3@

3

10mils

PEG_COMP

PEG_RX_0 PEG_RX_1 PEG_RX_2 PEG_RX_3 PEG_RX_4 PEG_RX_5 PEG_RX_6 PEG_RX_7 PEG_RX_8 PEG_RX_9

PEG_TX_0 PEG_TX_1 PEG_TX_2 PEG_TX_3 PEG_TX_4 PEG_TX_5 PEG_TX_6 PEG_TX_7 PEG_TX_8 PEG_TX_9

T37 T36

PCIE_GTX_C_MRX_N0

H44

PCIE_GTX_C_MRX_N1

J46

PCIE_GTX_C_MRX_N2

L44

PCIE_GTX_C_MRX_N3

L40

PCIE_GTX_C_MRX_N4

N41

PCIE_GTX_C_MRX_N5

P48

PCIE_GTX_C_MRX_N6

N44

PCIE_GTX_C_MRX_N7

T43

PCIE_GTX_C_MRX_N8

U43

PCIE_GTX_C_MRX_N9

Y43

PCIE_GTX_C_MRX_N10

Y48

PCIE_GTX_C_MRX_N11

Y36

PCIE_GTX_C_MRX_N12

AA43

PCIE_GTX_C_MRX_N13

AD37

PCIE_GTX_C_MRX_N14

AC47

PCIE_GTX_C_MRX_N15

AD39

PCIE_GTX_C_MRX_P0

H43

PCIE_GTX_C_MRX_P1

J44

PCIE_GTX_C_MRX_P2

L43

PCIE_GTX_C_MRX_P3

L41

PCIE_GTX_C_MRX_P4

N40

PCIE_GTX_C_MRX_P5

P47

PCIE_GTX_C_MRX_P6

N43

PCIE_GTX_C_MRX_P7

T42

PCIE_GTX_C_MRX_P8

U42

PCIE_GTX_C_MRX_P9

Y42

PCIE_GTX_C_MRX_P10

W47

PCIE_GTX_C_MRX_P11

Y37

PCIE_GTX_C_MRX_P12

AA42

PCIE_GTX_C_MRX_P13

AD36

PCIE_GTX_C_MRX_P14

AC48

PCIE_GTX_C_MRX_P15

AD40

PCIE_MTX_GRX_N0

J41

PCIE_MTX_GRX_N1

M46

PCIE_MTX_GRX_N2

M47

PCIE_MTX_GRX_N3

M40

PCIE_MTX_GRX_N4

M42

PCIE_MTX_GRX_N5

R48

PCIE_MTX_GRX_N6

N38

PCIE_MTX_GRX_N7

T40

PCIE_MTX_GRX_N8

U37

PCIE_MTX_GRX_N9

U40

PCIE_MTX_GRX_N10

Y40

PCIE_MTX_GRX_N11

AA46

PCIE_MTX_GRX_N12

AA37

PCIE_MTX_GRX_N13

AA40

PCIE_MTX_GRX_N14

AD43

PCIE_MTX_GRX_N15

AC46

PCIE_MTX_GRX_P0

J42

PCIE_MTX_GRX_P1

L46

PCIE_MTX_GRX_P2

M48

PCIE_MTX_GRX_P3

M39

PCIE_MTX_GRX_P4

M43

PCIE_MTX_GRX_P5

R47

PCIE_MTX_GRX_P6

N37

PCIE_MTX_GRX_P7

T39

PCIE_MTX_GRX_P8

U36

PCIE_MTX_GRX_P9

U39

PCIE_MTX_GRX_P10

Y39

PCIE_MTX_GRX_P11

Y46

PCIE_MTX_GRX_P12

AA36

PCIE_MTX_GRX_P13

AA39

PCIE_MTX_GRX_P14

AD42

PCIE_MTX_GRX_P15

AD46

PEG_COMPI

PEG_COMPO

PEG_RX#_0 PEG_RX#_1 PEG_RX#_2 PEG_RX#_3 PEG_RX#_4 PEG_RX#_5 PEG_RX#_6 PEG_RX#_7 PEG_RX#_8 PEG_RX#_9

LVDS TV VGA

PEG_RX#_10 PEG_RX#_11 PEG_RX#_12 PEG_RX#_13 PEG_RX#_14 PEG_RX#_15

PEG_RX_10 PEG_RX_11 PEG_RX_12 PEG_RX_13 PEG_RX_14 PEG_RX_15

PEG_TX#_0 PEG_TX#_1 PEG_TX#_2 PEG_TX#_3 PEG_TX#_4 PEG_TX#_5 PEG_TX#_6 PEG_TX#_7 PEG_TX#_8

PCI-EXPRESS GRAPHICS

PEG_TX#_9 PEG_TX#_10 PEG_TX#_11 PEG_TX#_12 PEG_TX#_13 PEG_TX#_14 PEG_TX#_15

PEG_TX_10

PEG_TX_11

PEG_TX_12

PEG_TX_13

PEG_TX_14

PEG_TX_15

1 2

R87 49.9_0402_1%R87 49.9_0402_1%

C62 0.1U_0402_16V7KPMIHD@C62 0.1U_0402_16V7KPMIHD@

1 2

C64 0.1U_0402_16V7KPMIHD@C64 0.1U_0402_16V7KPMIHD@

1 2

C66 0.1U_0402_16V7KPM@C66 0.1U_0402_16V7KPM@

1 2

C68 0.1U_0402_16V7KPM@C68 0.1U_0402_16V7KPM@

1 2

C70 0.1U_0402_16V7KPM@C70 0.1U_0402_16V7KPM@

1 2

C72 0.1U_0402_16V7KPM@C72 0.1U_0402_16V7KPM@

1 2

C74 0.1U_0402_16V7KPM@C74 0.1U_0402_16V7KPM@

1 2

C76 0.1U_0402_16V7KPM@C76 0.1U_0402_16V7KPM@

1 2

C78 0.1U_0402_16V7KPMIHD@C78 0.1U_0402_16V7KPMIHD@

1 2

C80 0.1U_0402_16V7KPMIHD@C80 0.1U_0402_16V7KPMIHD@

1 2

C82 0.1U_0402_16V7KPM@C82 0.1U_0402_16V7KPM@

1 2

C84 0.1U_0402_16V7KPM@C84 0.1U_0402_16V7KPM@

1 2

C86 0.1U_0402_16V7KPM@C86 0.1U_0402_16V7KPM@

1 2

C88 0.1U_0402_16V7KPM@C88 0.1U_0402_16V7KPM@

1 2

C90 0.1U_0402_16V7KPM@C90 0.1U_0402_16V7KPM@

1 2

C92 0.1U_0402_16V7KPM@C92 0.1U_0402_16V7KPM@

1 2

+1.05VS

2

PCIE_MTX_C_GRX_N[0..15] PCIE_MTX_C_GRX_P[0..15]

PCIE_GTX_C_MRX_N[0..15] PCIE_GTX_C_MRX_P[0..15]

C61 0.1U_0402_16V7KPMIHD@C61 0.1U_0402_16V7KPMIHD@

1 2

C63 0.1U_0402_16V7KPMIHD@C63 0.1U_0402_16V7KPMIHD@

1 2

C65 0.1U_0402_16V7KPM@C65 0.1U_0402_16V7KPM@

1 2

C67 0.1U_0402_16V7KPM@C67 0.1U_0402_16V7KPM@

1 2

C69 0.1U_0402_16V7KPM@C69 0.1U_0402_16V7KPM@

1 2

C71 0.1U_0402_16V7KPM@C71 0.1U_0402_16V7KPM@

1 2

C73 0.1U_0402_16V7KPM@C73 0.1U_0402_16V7KPM@

1 2

C75 0.1U_0402_16V7KPM@C75 0.1U_0402_16V7KPM@

1 2

C77 0.1U_0402_16V7KPMIHD@C77 0.1U_0402_16V7KPMIHD@

1 2

C79 0.1U_0402_16V7KPMIHD@C79 0.1U_0402_16V7KPMIHD@

1 2

C81 0.1U_0402_16V7KPM@C81 0.1U_0402_16V7KPM@

1 2

C83 0.1U_0402_16V7KPM@C83 0.1U_0402_16V7KPM@

1 2

C85 0.1U_0402_16V7KPM@C85 0.1U_0402_16V7KPM@

1 2

C87 0.1U_0402_16V7KPM@C87 0.1U_0402_16V7KPM@

1 2

C89 0.1U_0402_16V7KPM@C89 0.1U_0402_16V7KPM@

1 2

C91 0.1U_0402_16V7KPM@C91 0.1U_0402_16V7KPM@

1 2

1

PCIE_MTX_C_GRX_N[0..15] <17,19>

PCIE_MTX_C_GRX_P[0..15] <17,19> PCIE_GTX_C_MRX_N[0..15] <17> PCIE_GTX_C_MRX_P[0..15] <17,19>

PCIE_MTX_C_GRX_N0 PCIE_MTX_C_GRX_N1 PCIE_MTX_C_GRX_N2

PCIE_MTX_C_GRX_N3

PCIE_MTX_C_GRX_N4 PCIE_MTX_C_GRX_N5 PCIE_MTX_C_GRX_N6 PCIE_MTX_C_GRX_N7 PCIE_MTX_C_GRX_N8 PCIE_MTX_C_GRX_N9 PCIE_MTX_C_GRX_N10 PCIE_MTX_C_GRX_N11 PCIE_MTX_C_GRX_N12 PCIE_MTX_C_GRX_N13 PCIE_MTX_C_GRX_N14 PCIE_MTX_C_GRX_N15

PCIE_MTX_C_GRX_P0 PCIE_MTX_C_GRX_P1 PCIE_MTX_C_GRX_P2 PCIE_MTX_C_GRX_P3 PCIE_MTX_C_GRX_P4 PCIE_MTX_C_GRX_P5 PCIE_MTX_C_GRX_P6 PCIE_MTX_C_GRX_P7 PCIE_MTX_C_GRX_P8 PCIE_MTX_C_GRX_P9 PCIE_MTX_C_GRX_P10 PCIE_MTX_C_GRX_P11 PCIE_MTX_C_GRX_P12 PCIE_MTX_C_GRX_P13 PCIE_MTX_C_GRX_P14 PCIE_MTX_C_GRX_P15

A A

Security Classification

2008/10/1 2009/10/1

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2008/10/1 2009/10/1

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

SCHEMATICS,M/B A4161

401562 G

1

of

10 48Monday, February 23, 2009

of

10 48Monday, February 23, 2009

of

10 48Monday, February 23, 2009

5

+1.8V

DDR PWR

D D

C96

330U_4V_M

C C

10U_0805_10V4Z

1

+

2

0317 change value

0.1U_0402_16V4Z

10U_0805_10V4Z

C94

C93

1

2

C95

1

2

1

Could be NC for DDR2 Board.

1

+NB_VCCAXG

1

+

2

220U_6.3V_M@

0.1U_0402_16V4Z

0.1U_0402_16V4Z C231

C231

@

Int. Graphic -- 8700mA

220U_6.3V_MGM@

1

+

C105

C104

C103

2

GM@

GM@ 10U_0805_10V4Z

10U_0805_10V4Z

1

C230

@

2

0.1U_0402_16V4Z

10U_0805_10V4Z

1

C106

C106 GM@

GM@

2

1

0.1U_0402_16V4Z

0.1U_0402_16V4Z C228

C228

@

2

1

C107

C107 GM@

GM@

2

1U_0402_6.3V4Z

C202

@

2

0.1U_0402_16V4Z

0.47U_0402_10V4Z

1

C108

C108 GM@

GM@

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z C134

C134

@

2

1

C109

C109 GM@

GM@

2

0.1U_0402_16V4Z

1

2

0.1U_0402_16V4Z

1

C110

C110 GM@

GM@

2

1

2

Intel:AXG and AXG_NCTF -- 220U*2, ESR 15mOhm

B B

C106

0_0805_5%

PM@C106

PM@

DVT-R707 change to J3, and R693 and R697, change to J4 for power rating issue.

+1.05VS +NB_VCCAXG

J4

2

112

JUMP_43X118@J4JUMP_43X118@

J3

2

112

@

JUMP_43X39

T3PAD T3PAD T4PAD T4PAD

A A

5

4

U3F

3000mA

AP33

VCC_SM_1

AN33

VCC_SM_2

BH32

VCC_SM_3

BG32

VCC_SM_4

BF32

VCC_SM_5

BD32

VCC_SM_6

BC32

VCC_SM_7

BB32

VCC_SM_8

BA32

VCC_SM_9

AY32

VCC_SM_10

AW32

VCC_SM_11

AV32

VCC_SM_12

AU32

VCC_SM_13

AT32

VCC_SM_14

AR32

VCC_SM_15

AP32

VCC_SM_16

AN32

VCC_SM_17

BH31

VCC_SM_18

BG31

VCC_SM_19

BF31

VCC_SM_20

BG30

VCC_SM_21

BH29

VCC_SM_22

BG29

VCC_SM_23

BF29

VCC_SM_24

BD29

VCC_SM_25

BC29

VCC_SM_26

BB29

VCC_SM_27

BA29

VCC_SM_28

AY29

VCC_SM_29

AW29

VCC_SM_30

AV29

VCC_SM_31

AU29

VCC_SM_32

AT29

VCC_SM_33

AR29

VCC_SM_34

AP29

VCC_SM_35

BA36

VCC_SM_36/NC

BB24

VCC_SM_37/NC

BD16

VCC_SM_38/NC

BB21

VCC_SM_39/NC

AW16

VCC_SM_40/NC

AW13

VCC_SM_41/NC

AT13

VCC_SM_42/NC

6326.84mA

Y26

VCC_AXG_1

AE25

VCC_AXG_2

AB25

VCC_AXG_3

AA25

VCC_AXG_4

AE24

VCC_AXG_5

AC24

VCC_AXG_6

AA24

VCC_AXG_7

Y24

VCC_AXG_8

AE23

VCC_AXG_9

AC23

VCC_AXG_10

AB23

VCC_AXG_11

AA23

VCC_AXG_12

AJ21

VCC_AXG_13

AG21

VCC_AXG_14

AE21

VCC_AXG_15

AC21

VCC_AXG_16

AA21

VCC_AXG_17

Y21

VCC_AXG_18

AH20

VCC_AXG_19

AF20

VCC_AXG_20

AE20

VCC_AXG_21

AC20

VCC_AXG_22

AB20

VCC_AXG_23

AA20

VCC_AXG_24

T17

VCC_AXG_25

T16

VCC_AXG_26

AM15

VCC_AXG_27

AL15

VCC_AXG_28

AE15

VCC_AXG_29

AJ15

VCC_AXG_30

AH15

VCC_AXG_31

AG15

VCC_AXG_32

AF15

VCC_AXG_33

AB15

VCC_AXG_34

AA15

VCC_AXG_35

Y15

VCC_AXG_36

V15

VCC_AXG_37

U15

VCC_AXG_38

AN14

VCC_AXG_39

AM14

VCC_AXG_40

U14

VCC_AXG_41

T14

VCC_AXG_42

AJ14

VCC_AXG_SENSE

AH14

VSS_AXG_SENSE

CANTIGA ES_FCBGA1329

CANTIGA ES_FCBGA1329 GMR3@

GMR3@

4

VCC_AXG_NTCF_1 VCC_AXG_NCTF_2 VCC_AXG_NCTF_3 VCC_AXG_NCTF_4 VCC_AXG_NCTF_5 VCC_AXG_NCTF_6 VCC_AXG_NCTF_7 VCC_AXG_NCTF_8

VCC SM

VCC_AXG_NCTF_9 VCC_AXG_NCTF_10 VCC_AXG_NCTF_11 VCC_AXG_NCTF_12 VCC_AXG_NCTF_13 VCC_AXG_NCTF_14 VCC_AXG_NCTF_15 VCC_AXG_NCTF_16 VCC_AXG_NCTF_17 VCC_AXG_NCTF_18 VCC_AXG_NCTF_19 VCC_AXG_NCTF_20 VCC_AXG_NCTF_21 VCC_AXG_NCTF_22 VCC_AXG_NCTF_23 VCC_AXG_NCTF_24 VCC_AXG_NCTF_25 VCC_AXG_NCTF_26 VCC_AXG_NCTF_27 VCC_AXG_NCTF_28 VCC_AXG_NCTF_29 VCC_AXG_NCTF_30 VCC_AXG_NCTF_31 VCC_AXG_NCTF_32 VCC_AXG_NCTF_33 VCC_AXG_NCTF_34 VCC_AXG_NCTF_35 VCC_AXG_NCTF_36 VCC_AXG_NCTF_37 VCC_AXG_NCTF_38 VCC_AXG_NCTF_39 VCC_AXG_NCTF_40 VCC_AXG_NCTF_41 VCC_AXG_NCTF_42 VCC_AXG_NCTF_43

VCC GFX NCTF

VCC_AXG_NCTF_44 VCC_AXG_NCTF_45 VCC_AXG_NCTF_46 VCC_AXG_NCTF_47 VCC_AXG_NCTF_48 VCC_AXG_NCTF_49 VCC_AXG_NCTF_50 VCC_AXG_NCTF_51 VCC_AXG_NCTF_52

POWER

VCC_AXG_NCTF_53 VCC_AXG_NCTF_54 VCC_AXG_NCTF_55 VCC_AXG_NCTF_56 VCC_AXG_NCTF_57 VCC_AXG_NCTF_58 VCC_AXG_NCTF_59 VCC_AXG_NCTF_60

VCC GFX

VCC_SM_LF1 VCC_SM_LF2 VCC_SM_LF3 VCC_SM_LF4 VCC_SM_LF5 VCC_SM_LF6 VCC_SM_LF7

VCC SM LF

3

+NB_VCCAXG

Int. Graphic Core -- 8700mA

W28 V28 W26 V26 W25 V25 W24 V24 W23 V23 AM21 AL21 AK21 W21 V21 U21 AM20 AK20 W20 U20 AM19 AL19 AK19 AJ19 AH19 AG19 AF19 AE19 AB19 AA19 Y19 W19 V19 U19 AM17 AK17 AH17 AG17 AF17 AE17 AC17 AB17 Y17 W17 V17 AM16 AL16 AK16 AJ16 AH16 AG16 AF16 AE16 AC16 AB16 AA16 Y16 W16 V16 U16

VCCSM_LF1

AV44

VCCSM_LF2

BA37

VCCSM_LF3

AM40

VCCSM_LF4

AV21

VCCSM_LF5

AY5

VCCSM_LF6

AM10

VCCSM_LF7

BB13

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

0.1U_0402_16V4Z

0.1U_0402_16V4Z C111

C111

Issued Date

1

2

3

+1.05VS

NB Core

220U_6.3V_M

1

+

C101

2

220U_6.3V_M@

Intel: VCC -- 220U*2, ESR 12mOhm

1

C113

0.1U_0402_16V4Z

0.1U_0402_16V4Z 2

1

0.22U_0402_10V4Z

0.22U_0402_10V4Z C112

C112

2

2008/10/1 2009/10/1

0.22U_0402_10V4Z

1

+

C97

C102

2

10U_0805_10V4Z

1

C114

0.22U_0402_10V4Z

0.22U_0402_10V4Z 2

Compal Secret Data

1

C98

2

0.22U_0402_10V4Z

1

0.47U_0402_10V4Z

0.47U_0402_10V4Z C115

C115

2

Deciphered Date

0.1U_0402_16V4Z

1

C99

2

1

C116

1U_0402_6.3V4Z

2

1

C100

2

1

1U_0402_6.3V4Z

C117

2

U3G

AG34

VCC_1

AC34

VCC_2

AB34

VCC_3

AA34

VCC_4

Y34

VCC_5

V34

VCC_6

U34

VCC_7

AM33

VCC_8

AK33

VCC_9

AJ33

VCC_10

AG33

VCC_11

AF33

VCC_12

AE33

VCC_13

AC33

VCC_14

AA33

VCC_15

Y33

VCC_16

W33

VCC_17

V33

VCC_18

U33

VCC_19

AH28

VCC_20

AF28

VCC_21

AC28

VCC_22

AA28

VCC_23

AJ26

VCC_24

AG26

VCC_25

AE26

VCC_26

AC26

VCC_27

AH25

VCC_28

AG25

VCC_29

AF25

VCC_30

AG24

VCC_31

AJ23

VCC_32

AH23

VCC_33

AF23

VCC_34

T32

VCC_35

CANTIGA ES_FCBGA1329

CANTIGA ES_FCBGA1329 GMR3@

GMR3@

1

Extnal Graphic: 1210.34mA integrated Graphic: 1930.4mA

VCC CORE

POWER

+1.05VS

VCC_NCTF_1 VCC_NCTF_2 VCC_NCTF_3 VCC_NCTF_4 VCC_NCTF_5 VCC_NCTF_6 VCC_NCTF_7 VCC_NCTF_8

VCC_NCTF_9 VCC_NCTF_10 VCC_NCTF_11 VCC_NCTF_12 VCC_NCTF_13 VCC_NCTF_14 VCC_NCTF_15 VCC_NCTF_16 VCC_NCTF_17 VCC_NCTF_18 VCC_NCTF_19 VCC_NCTF_20 VCC_NCTF_21 VCC_NCTF_22 VCC_NCTF_23 VCC_NCTF_24 VCC_NCTF_25 VCC_NCTF_26 VCC_NCTF_27 VCC_NCTF_28

VCC NCTF

VCC_NCTF_29 VCC_NCTF_30 VCC_NCTF_31 VCC_NCTF_32 VCC_NCTF_33 VCC_NCTF_34 VCC_NCTF_35 VCC_NCTF_36 VCC_NCTF_37 VCC_NCTF_38 VCC_NCTF_39 VCC_NCTF_40 VCC_NCTF_41 VCC_NCTF_42 VCC_NCTF_43 VCC_NCTF_44

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

SCHEMATICS,M/B A4161

401562 G

AM32 AL32 AK32 AJ32 AH32 AG32 AE32 AC32 AA32 Y32 W32 U32 AM30 AL30 AK30 AH30 AG30 AF30 AE30 AC30 AB30 AA30 Y30 W30 V30 U30 AL29 AK29 AJ29 AH29 AG29 AE29 AC29 AA29 Y29 W29 V29 AL28 AK28 AL26 AK26 AK25 AK24 AK23

of

11 48Monday, February 23, 2009

1

5

+3VS_TVCRT_DACBG

+3VS

R103

GM@R103

GM@

BLM18PG181SN1D_0603

10U_0805_10V4Z

10U_FLC-453232-100K_0.25A_10%

D D

220U_6.3V_M@

FBMA-L11-160808-121LMT_0603

10U_0805_10V4Z

+1.5VS

C C

B B

12

1

C118

GM@ C118

GM@

2

R105

GM@R105

GM@

C132

R107

12

C136

PCIe&DMI

1 2

R110 0_0603_5%R110 0_0603_5%

0.1U_0402_16V4Z

+1.5VS

R119

R119 0_0603_5%

0_0603_5%

0.1U_0402_16V4Z

+1.05VS_DPLLA+1.05VS

10U_0805_10V4Z

12

1

+

C133

C124

GM@

2

0.1U_0402_16V4Z

1

C126

2

0.1U_0402_16V4Z

Pin AD1

+1.5VS_PEG_BG

1

C141

0.01U_0402_25V4Z

12

1

C162

2

+1.5VS_QDAC

C163

Pin AD48 Pin AA48

1

GM@

Pin F47

2

C138

C138 10U_0805_10V4Z

10U_0805_10V4Z

+1.5VS +1.5VS_HDA

0.1U_0402_16V4Z

TV

1

Pin L28

2

+3VS_TVCRT_DACBG

R104

GM@R104

GM@

12

0_0603_5%

C119

GM@ C119

GM@

0.1U_0402_16V4Z

C124

PM@C124

PM@

0_0805_5%

R108

1

C139

2

R117

0_0402_5%

0_0402_5% IHDMI@

IHDMI@

C157

IHDMI@

C163

0_0402_5%

12

R109 0.5_0805_1%R109 0.5_0805_1%

Pin AE1

0.1U_0402_16V4Z

PCIe&DMI

HDMI's HDA

1

Pin A32

2

@C163

@

FBMA-L11-160808-121LMT_0603

1 2

+1.05VS_PEGPLL

0.1U_0402_16V4Z

1 2

+3VS_TVCRT_DAC

0.01U_0402_25V4Z

0.01U_0402_25V4Z 1

1

C120

C120 GM@

GM@

2

R106

10U_FLC-453232-100K_0.25A_10%

+1.05VS_MPLL+1.05VS+1.05VS_AHPLL+1.05VS

1

C127

2

Intel Errata.

+1.05VS +1.05VS_DHPLL

R121

1 2

0_0402_5%

0.1U_0402_16V4Z

+1.05VS

A A

BLM18PG121SN1D_0603

R123

1_0402_1%

PCIe&DMI

L1

12

10U_0805_10V4Z

C174

12

C170

+1.05VS_PEGPLL

0.1U_0402_16V4Z

C173

5

2

Pin AF1

1

2

Pin AA47

+1.8V

4

CRT TV

C120

PM@C120

PM@

0_0402_5%

GM@R106

GM@

12

+3VS

0.1U_0402_16V4Z

R122

R122 0_0603_5%

0_0603_5%

0_0402_5%

+1.05VS_DPLLB+1.05VS

10U_0805_10V4Z

1

C125

GM@

2

0.1U_0402_16V4Z

+1.8V_TXLVDS

1

C137 1000P_0402_50V7K

1000P_0402_50V7K

2

GND to J47

+1.05VS

+

+1.05VS

10U_0805_10V4Z

+3VS_TVDAC

R127

R127 0_0603_5%

0_0603_5% GM@

GM@

+1.5VS

0.01U_0402_25V4Z

0.01U_0402_25V4Z 1

C160

2

12

1U_0402_6.3V4Z

4

64.8mA

C135

GM@

LVDS

GM@C137

GM@

Pin J48

R112

1 2

0_0805_5%

1

C143

C143 220U_6.3V_M

220U_6.3V_M

2

R115

1 2

0_0603_5%

C150

12

1

C156

0.01U_0402_25V4Z

Pin B24

2

C161

+1.8V_LVDS

1

C172

2

Pin M38

0.1U_0402_16V4Z

C125

1

Pin L48

2

C137

0_0402_5%

10U_0805_10V4Z

1

2

C156

0_0402_5%

GM@C156

GM@

1

Pin M25

2

LVDS

Pin B27

+3VS_TVCRT_DACBG

0.01U_0402_25V4Z

0.01U_0402_25V4Z 1

C121

C122

GM@

2

PM@C125

PM@

0_0805_5%

+3VS_TVCRT_DACBG

PM@C137

PM@

DDR2

4.7U_0603_6.3V6K

1

C144

C145

2

DDR2

+1.05VS_A_SM_CK

0.1U_0402_16V4Z

2

C151

C152

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M 1

PM@C156

PM@

+1.05VS_PEGPLL

+1.8V_LVDS

+1.05VS_A_SM

3

1

2

+3VS_TVCRT_DAC

1U_0402_6.3V4Z

C122

PM@C122

C146

+3VS_TVDAC

Issued Date

PM@

0_0402_5%

720mA

U3H

73mA

B27

VCCA_CRT_DAC_1

A26

VCCA_CRT_DAC_2

2.68mA

A25

VCCA_DAC_BG

B25

VSSA_DAC_BG

F47

VCCA_DPLLA

L48

VCCA_DPLLB

AD1

VCCA_HPLL

13.2mA

AE1

VCCA_MPLL

J48

VCCA_LVDS

414uA

J47

VSSA_LVDS

AD48

VCCA_PEG_BG

50mA

AA48

VCCA_PEG_PLL

AR20

VCCA_SM_1

AP20

VCCA_SM_2

AN20

VCCA_SM_3

AR17

VCCA_SM_4

AP17

VCCA_SM_5

AN17

VCCA_SM_6

AT16

VCCA_SM_7

AR16

VCCA_SM_8

AP16

VCCA_SM_9

AP28

VCCA_SM_CK_1

AN28

VCCA_SM_CK_2

AP25

VCCA_SM_CK_3

AN25

VCCA_SM_CK_4

AN24

VCCA_SM_CK_5

AM28

VCCA_SM_CK_NCTF_1

AM26

VCCA_SM_CK_NCTF_2

AM25

VCCA_SM_CK_NCTF_3

AL25

VCCA_SM_CK_NCTF_4

AM24

VCCA_SM_CK_NCTF_5

AL24

VCCA_SM_CK_NCTF_6

AM23

VCCA_SM_CK_NCTF_7

AL23

VCCA_SM_CK_NCTF_8

B24

VCCA_TV_DAC_1

A24

VCCA_TV_DAC_2

A32

VCC_HDA

M25

VCCD_TVDAC

L28

VCCD_QDAC

AF1

VCCD_HPLL

60.31mA

AA47

VCCD_PEG_PLL

M38

VCCD_LVDS_1

L37

VCCD_LVDS_2

CANTIGA ES_FCBGA1329

CANTIGA ES_FCBGA1329 GMR3@

GMR3@

+1.05VS +3VS

CH751H-40PT_SOD323-2

2008/10/1 2009/10/1

3

24mA

139.2mA

26mA 26mA

TVA 24.15mA TVB 39.48mA TVX 24.15mA

50mA

58.67mA

48.363mA

157.2mA

HDA

50mA

D21

2 1

CRTPLLA LVDSA PEG

VTT

POWER

A SM

AXF

VCC_SM_CK_1 VCC_SM_CK_2 VCC_SM_CK_3 VCC_SM_CK_4

SM CK

VCC_TX_LVDS

A CK

HV

105.3mA

1732mA

TV

DMI PEG

VTTLF

LVDS D TV/CRT

R1006

1 2

10_0603_5%

Compal Secret Data

852mA64.8mA

VTT_1 VTT_2 VTT_3 VTT_4 VTT_5 VTT_6 VTT_7 VTT_8

VTT_9 VTT_10 VTT_11 VTT_12 VTT_13 VTT_14 VTT_15 VTT_16 VTT_17 VTT_18 VTT_19 VTT_20 VTT_21 VTT_22 VTT_23 VTT_24 VTT_25

VCC_AXF_1 VCC_AXF_2 VCC_AXF_3

VCC_HV_1 VCC_HV_2 VCC_HV_3

VCC_PEG_1 VCC_PEG_2 VCC_PEG_3 VCC_PEG_4 VCC_PEG_5

VCC_DMI_1 VCC_DMI_2 VCC_DMI_3 VCC_DMI_4

456mA

VTTLF1 VTTLF2 VTTLF3

Deciphered Date

U13 T13 U12 T12 U11 T11 U10 T10 U9 T9 U8 T8 U7 T7 U6 T6 U5 T5 V3 U3 V2 U2 T2 V1 U1

B22 B21 A21

BF21 BH20 BG20 BF20

K47

C35 B35 A35

V48 U48 V47 U47 U46

AH48 AF48 AH47 AG47

A8 L1 AB2

+NB_VTTLF1 +NB_VTTLF2 +NB_VTTLF3

321.35mA

0.47U_0402_10V4Z

Pin A25 GNDtoB25

+1.05VS_DPLLA +1.05VS_DPLLB

+1.05VS_AHPLL

+1.05VS_MPLL

+1.8V_TXLVDS

+1.5VS_PEG_BG

+1.05VS_PEGPLL

1

2

Pin AR20

1

2

Pin AP28

+1.5VS_HDA

+1.5VS +1.5VS_QDAC

+1.05VS_DHPLL

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2

1

C128

0.47U_0402_10V4Z

0.47U_0402_10V4Z 2

+1.05VS_AXF

+1.8V_SM_CK

EVT2- Remove C153 PM@ 0Ohm.

124mA

+1.8V_TXLVDS

118.8mA

+3VS

+1.05VS_PEG_DMI

1

C167

C168

0.47U_0402_10V4Z

2

C123

2.2U_0402_6.3V6M

1

0.47U_0402_10V4Z

0.47U_0402_10V4Z C169

C169

2

1

+1.05VS

AGTL+

NB I/O

C140

C140 1U_0402_6.3V4Z

1U_0402_6.3V4Z

1

C130

4.7U_0603_6.3V6K

2

R111

1 2

0_0603_5%

1

C142

10U_0805_10V4Z

10U_0805_10V4Z 2

1

C129

4.7U_0603_6.3V6K

2

Intel: VTT 270U*1 ESR 12mOhm

+1.05VS_AXF

2

1

+1.05VS

1

+

2

C131

C131 220U_6.3V_M

220U_6.3V_M

Pin B22

+1.8V_SM_CK

DDR2

1

C147

0.1U_0402_16V4Z

2

Pin BF21

+1.8V_TXLVDS +1.8V

LVDS

1

C153

GM@C153

GM@

1000P_0402_50V7K

2

Pin K47

+3VS

1

C158

0.1U_0402_16V4Z

Pin C35

2

R114

R114 1_0402_1%

1_0402_1%

C149

1 2

10U_0805_10V4Z

R116 1 2

0_0603_5%

1

C154 10U_0805_10V4Z

10U_0805_10V4Z

2

GM@R116

GM@

GM@C154

GM@

R113

1 2

0_0805_5%

1

C148

C148 10U_0805_10V4Z

10U_0805_10V4Z

2

+1.8V

DVT-R120 change to J8 for power rating issue.

+1.05VS_PEG_DMI

10U_0805_10V4Z

1

+1.05VS_PEG_DMI

2

Title

Size Document Number Rev

Custom

Date: Sheet

PCIe&DMI

10U_0805_10V4Z@

1

C164

2

Pin V48

10U_0805_10V4Z@

1

C165

220U_6.3V_M

2

C166

1

+

2

PCIe&DMI

1

C171

0.1U_0402_16V4Z

2

Pin AH48

Compal Electronics, Inc.

SCHEMATICS,M/B A4161

401562 G

1

J8

2

112

JUMP_43X118@J8JUMP_43X118@

of

12 48Monday, February 23, 2009

+1.05VS

5

U3I

AU48

VSS_1

AR48

VSS_2

AL48

VSS_3

BB47

VSS_4

AW47

VSS_5

AN47

VSS_6

AJ47

VSS_7

AF47

VSS_8

AD47

VSS_9

AB47

VSS_10

Y47

VSS_11

T47

BD46 BA46 AY46 AV46 AR46

AM46

BF44 AH44 AD44 AA44

M44

BC43 AV43 AU43

AM43

BG42 AY42 AT42 AN42

AJ42

AE42

BD41 AU41

AM41

AH41 AD41 AA41

M41

BG40 BB40 AV40 AN40

AT39

AM39

AJ39

AE39

BH38 BC38 BA38 AU38 AH38 AD38 AA38

BF37 BB37

AW37

AT37 AN37

AJ37

BG36 BD36 AK15 AU36

VSS_12

N47

VSS_13

L47

VSS_14

G47

VSS_15 VSS_16 VSS_17 VSS_18 VSS_19 VSS_20 VSS_21

V46

VSS_22

R46

VSS_23

P46

VSS_24

H46

VSS_25

F46

VSS_26 VSS_27 VSS_28 VSS_29 VSS_30

Y44

VSS_31

U44

VSS_32

T44

VSS_33 VSS_34

F44

VSS_35 VSS_36 VSS_37 VSS_38 VSS_39

J43

VSS_40

C43

VSS_41 VSS_42 VSS_43 VSS_44 VSS_45 VSS_46 VSS_47

N42

VSS_48

L42

VSS_49 VSS_50 VSS_51 VSS_52 VSS_53 VSS_54 VSS_55

Y41

VSS_56

U41

VSS_57

T41

VSS_58 VSS_59

G41

VSS_60

B41

VSS_61 VSS_62 VSS_63 VSS_64 VSS_65

H40

VSS_66

E40

VSS_67 VSS_68 VSS_69 VSS_70 VSS_71

N39

VSS_72

L39

VSS_73

B39

VSS_74 VSS_75 VSS_76 VSS_77 VSS_78 VSS_79 VSS_80 VSS_81

Y38

VSS_82

U38

VSS_83

T38

VSS_84

J38

VSS_85

F38

VSS_86

C38

VSS_87 VSS_88 VSS_89 VSS_90 VSS_91 VSS_92 VSS_93

H37

VSS_94

C37

VSS_95 VSS_96 VSS_97 VSS_98 VSS_99

VSS

CANTIGA ES_FCBGA1329

CANTIGA ES_FCBGA1329 GMR3@

GMR3@

D D

C C

B B

A A

VSS_100 VSS_101 VSS_102 VSS_103 VSS_104 VSS_105 VSS_106 VSS_107 VSS_108 VSS_109 VSS_110 VSS_111 VSS_112 VSS_113 VSS_114 VSS_115 VSS_116 VSS_117 VSS_118 VSS_119 VSS_120 VSS_121 VSS_122 VSS_123 VSS_124 VSS_125 VSS_126 VSS_127 VSS_128 VSS_129 VSS_130 VSS_131 VSS_132 VSS_133 VSS_134 VSS_135 VSS_136 VSS_137 VSS_138 VSS_139 VSS_140 VSS_141 VSS_142 VSS_143 VSS_144 VSS_145 VSS_146 VSS_147 VSS_148 VSS_149 VSS_150 VSS_151 VSS_152 VSS_153 VSS_154 VSS_155 VSS_156 VSS_157 VSS_158 VSS_159 VSS_160 VSS_161 VSS_162 VSS_163 VSS_164 VSS_165 VSS_166 VSS_167 VSS_168 VSS_169 VSS_170 VSS_171 VSS_172 VSS_173 VSS_174 VSS_175 VSS_176 VSS_177 VSS_178 VSS_179 VSS_180 VSS_181 VSS_182 VSS_183 VSS_184 VSS_185 VSS_186 VSS_187 VSS_188 VSS_189 VSS_190 VSS_191 VSS_192 VSS_193 VSS_194 VSS_195 VSS_196 VSS_197 VSS_198 VSS_199

AM36 AE36 P36 L36 J36 F36 B36 AH35 AA35 Y35 U35 T35 BF34 AM34 AJ34 AF34 AE34 W34 B34 A34 BG33 BC33 BA33 AV33 AR33 AL33 AH33 AB33 P33 L33 H33 N32 K32 F32 C32 A31 AN29 T29 N29 K29 H29 F29 A29 BG28 BD28 BA28 AV28 AT28 AR28 AJ28 AG28 AE28 AB28 Y28 P28 K28 H28 F28 C28 BF26 AH26 AF26 AB26 AA26 C26 B26 BH25 BD25 BB25 AV25 AR25 AJ25 AC25 Y25 N25 L25 J25 G25 E25 BF24 AD12 AY24 AT24 AJ24 AH24 AF24 AB24 R24 L24 K24 J24 G24 F24 E24 BH23 AG23 Y23 B23 A23 AJ6

4

3

U3J

BG21

VSS_199

L12

VSS_200

AW21

VSS_201

AU21

VSS_202

AP21

VSS_203

AN21

VSS_204

AH21

VSS_205

AF21

VSS_206

AB21

VSS_207

R21

VSS_208

M21

VSS_209

J21

VSS_210

G21

VSS_211

BC20

VSS_212

BA20

VSS_213

AW20

VSS_214

AT20

VSS_215

AJ20

VSS_216

AG20

VSS_217

Y20

VSS_218

N20

VSS_219

K20

VSS_220

F20

VSS_221

C20

VSS_222

A20

VSS_223

BG19

VSS_224

A18

VSS_225

BG17

VSS_226

BC17

VSS_227

AW17

VSS_228

AT17

VSS_229

R17

VSS_230

M17

VSS_231

H17

VSS_232

C17

VSS_233

BA16

VSS_235

AU16

VSS_237

AN16

VSS_238

N16

VSS_239

K16

VSS_240

G16

VSS_241

E16

VSS_242

BG15

VSS_243

AC15

VSS_244

W15

VSS_245

A15

VSS_246

BG14

VSS_247

AA14

VSS_248

C14

VSS_249

BG13

VSS_250

BC13

VSS_251

BA13

VSS_252

AN13

VSS_255

AJ13

VSS_256

AE13

VSS_257

N13

VSS_258

L13

VSS_259

G13

VSS_260

E13

VSS_261

BF12

VSS_262

AV12

VSS_263

AT12

VSS_264

AM12

VSS_265

AA12

VSS_266

J12

VSS_267

A12

VSS_268

BD11

VSS_269

BB11

VSS_270

AY11

VSS_271

AN11

VSS_272

AH11

VSS_273

Y11

VSS_275

N11

VSS_276

G11

VSS_277

C11

VSS_278

BG10

VSS_279

AV10

VSS_280

AT10

VSS_281

AJ10

VSS_282

AE10

VSS_283

AA10

VSS_284

M10

VSS_285

BF9

VSS_286

BC9

VSS_287

AN9

VSS_288

AM9

VSS_289

AD9

VSS_290

G9

VSS_291

B9

VSS_292

BH8

VSS_293

BB8

VSS_294

AV8

VSS_295

AT8

VSS_296

CANTIGA ES_FCBGA1329

CANTIGA ES_FCBGA1329 GMR3@

GMR3@

VSS

VSS_NCTF_10

VSS NCTF

VSS_NCTF_11 VSS_NCTF_12 VSS_NCTF_13 VSS_NCTF_14 VSS_NCTF_15 VSS_NCTF_16

VSS SCB

NC

VSS_297 VSS_298 VSS_299 VSS_300 VSS_301 VSS_302 VSS_303 VSS_304 VSS_305 VSS_306 VSS_307 VSS_308 VSS_309 VSS_310 VSS_311 VSS_312 VSS_313 VSS_314 VSS_315 VSS_316 VSS_317 VSS_318 VSS_319 VSS_320 VSS_321 VSS_322 VSS_323 VSS_324 VSS_325

VSS_327 VSS_328 VSS_329 VSS_330 VSS_331 VSS_332 VSS_333 VSS_334 VSS_335 VSS_336 VSS_337 VSS_338 VSS_339 VSS_340 VSS_341 VSS_342 VSS_343 VSS_344 VSS_345 VSS_346 VSS_347 VSS_348 VSS_349 VSS_350

VSS_351 VSS_352 VSS_353 VSS_354

VSS_NCTF_1 VSS_NCTF_2 VSS_NCTF_3 VSS_NCTF_4 VSS_NCTF_5 VSS_NCTF_6 VSS_NCTF_7 VSS_NCTF_8 VSS_NCTF_9

VSS_SCB_1 VSS_SCB_2 VSS_SCB_3 VSS_SCB_4 VSS_SCB_5

NC_26 NC_27 NC_28 NC_29 NC_30 NC_31 NC_32 NC_33 NC_34 NC_35 NC_36 NC_37 NC_38 NC_39 NC_40 NC_41 NC_42

AH8 Y8 L8 E8 B8 AY7 AU7 AN7 AJ7 AE7 AA7 N7 J7 BG6 BD6 AV6 AT6 AM6 M6 C6 BA5 AH5 AD5 Y5 L5 J5 H5 F5 BE4

BC3 AV3 AL3 R3 P3 F3 BA2 AW2 AU2 AR2 AP2 AJ2 AH2 AF2 AE2 AD2 AC2 Y2 M2 K2 AM1 AA1 P1 H1

U24 U28 U25 U29

AF32 AB32 V32 AJ30 AM29 AF29 AB29 U26 U23 AL20 V20 AC19 AL17 AJ17 AA17 U17

BH48 BH1 A48 C1 A3

E1 D2 C3 B4 A5 A6 A43 A44 B45 C46 D47 B47 A46 F48 E48 C48 B48

2

1

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2008/10/1 2009/10/1

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

SCHEMATICS,M/B A4161

401562 G

13 48Monday, February 23, 2009

1

of

5

JP30

+DIMM_VREF

2.2U_0603_6.3V6K

+1.8V

D D

12

R124

R124 1K_0402_1%

1K_0402_1%

12

R125

R125 1K_0402_1%

1K_0402_1%

C C

B B

A A

C175

20mils

2

0.1U_0402_16V4Z

1

+DIMM_VREF

DDRA_CKE0<8>

DDR_A_CAS#<9>

DDRA_SCS1#<8>

DDR_A_BS2<9>

DDR_A_BS0<9>

DDR_A_WE#<9>

DDRA_ODT1<8>

5

C176

PM_SMBDATA<15,16,22,26> PM_SMBCLK<15,16,22,26>

1

2

+3VS

C203

0.1U_0402_16V4Z

DDR_A_D5 DDR_A_D6

DDR_A_DQS#0 DDR_A_DQS0

DDR_A_D3 DDR_A_D2

DDR_A_D8 DDR_A_D9

DDR_A_DQS#1 DDR_A_DQS1

DDR_A_D15 DDR_A_D10

DDR_A_D21 DDR_A_D20

DDR_A_DQS#2 DDR_A_DQS2

DDR_A_D23 DDR_A_D18 DDR_A_D19

DDR_A_D29 DDR_A_D24

DDR_A_DM3

DDR_A_D26 DDR_A_D27

DDRA_CKE0

DDR_A_BS2 DDR_A_MA12

DDR_A_MA9 DDR_A_MA8

DDR_A_MA5 DDR_A_MA3 DDR_A_MA1

DDR_A_MA10 DDR_A_BS0 DDR_A_WE#

DDR_A_CAS# DDRA_SCS1#

DDRA_ODT1 DDR_A_D37

DDR_A_D36 DDR_A_DQS#4

DDR_A_DQS4 DDR_A_D34

DDR_A_D39 DDR_A_D40

DDR_A_D44 DDR_A_DM5 DDR_A_D47

DDR_A_D41 DDR_A_D49

DDR_A_D48

DDR_A_DQS#6 DDR_A_DQS6

DDR_A_D54 DDR_A_D50

DDR_A_D60 DDR_A_D61

DDR_A_DM7 DDR_A_D58

DDR_A_D59

1

2

1

VREF

3

VSS

5

DQ0

7

DQ1

9

VSS

11

DQS0#

13

DQS0

15

VSS

17

DQ2

19

DQ3

21

VSS

23

DQ8

25

DQ9

27

VSS

29

DQS1#

31

DQS1

33

VSS

35

DQ10

37

DQ11

39

VSS

41

VSS

43

DQ16

45

DQ17

47

VSS

49

DQS2#

51

DQS2

53

VSS

55

DQ18

57

DQ19

59

VSS

61

DQ24

63

DQ25

65

VSS

67

DM3

69

NC

71

VSS

73

DQ26

75

DQ27

77

VSS

79

CKE0

81

VDD

83

NC

85

BA2

87

VDD

89

A12

91

A9

93

A8

95

VDD

97

A5

99

A3

101

A1

103

VDD

105

A10/AP

107

BA0

109

WE#

111

VDD

113

CAS#

115

NC/S1#

117

VDD

119

NC/ODT1

121

VSS

123

DQ32

125

DQ33

127

VSS

129

DQS4#

131

DQS4

133

VSS

135

DQ34

137

DQ35

139

VSS

141

DQ40

143

DQ41

145

VSS

147

DM5

149

VSS

151

DQ42

153

DQ43

155

VSS

157

DQ48

159

DQ49

161

VSS

163

NC,TEST

165

VSS

167

DQS6#

169

DQS6

171

VSS

173

DQ50

175

DQ51

177

VSS

179

DQ56

181

DQ57

183

VSS

185

DM7

187

VSS

189

DQ58

191

DQ59

193

VSS

195

SDA

197

SCL

199

VDDSPD

4

VSS DQ4 DQ5 VSS DM0 VSS DQ6 DQ7

VSS DQ12 DQ13

VSS

DM1

VSS

CK0 CK0#

VSS DQ14 DQ15

VSS

VSS DQ20 DQ21

VSS

NC DM2 VSS

DQ22 DQ23

VSS

DQ28 DQ29

VSS

DQS3#

DQS3

VSS

DQ30 DQ31

VSS

NC/CKE1

VDD

NC/A15 NC/A14

VDD

A11

A7 A6

VDD

A4 A2 A0

VDD

BA1

RAS#

S0#

VDD

ODT0

NC/A13

VDD

NC VSS

DQ36 DQ37

VSS DM4 VSS

DQ38 DQ39

VSS

DQ44 DQ45

VSS

DQS5#

DQS5

VSS

DQ46 DQ47

VSS

DQ52 DQ53

VSS CK1

CK1#

VSS DM6 VSS

DQ54 DQ55

VSS

DQ60 DQ61

VSS

DQS7#

DQS7

VSS

DQ62 DQ63

VSS SAO

SA1

GND

TYCO_1775803-2~D

201

202

4

EVT2- Change DDR connector type, JP30 for Standard.

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40

42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200

SO-DIMM A

DDR_A_D4 DDR_A_D0

DDR_A_DM0 DDR_A_D1

DDR_A_D7 DDR_A_D13

DDR_A_D12 DDR_A_DM1

DDR_A_D14 DDR_A_D11

DDR_A_D17 DDR_A_D16

DDR_A_DM2

DDR_A_D22 DDR_A_D28

DDR_A_D25 DDR_A_DQS#3

DDR_A_DQS3 DDR_A_D31

DDR_A_D30 DDRA_CKE1

DDR_A_MA14 DDR_A_MA11

DDR_A_MA7 DDR_A_MA6

DDR_A_MA4 DDR_A_MA2 DDR_A_MA0

DDR_A_BS1 DDR_A_RAS# DDRA_SCS0#

DDRA_ODT0 DDR_A_MA13

DDR_A_D32 DDR_A_D38

DDR_A_DM4 DDR_A_D35

DDR_A_D33 DDR_A_D45

DDR_A_D43 DDR_A_DQS#5

DDR_A_DQS5 DDR_A_D46

DDR_A_D42 DDR_A_D52

DDR_A_D53

DDR_A_DM6 DDR_A_D51

DDR_A_D55 DDR_A_D57

DDR_A_D56 DDR_A_DQS#7

DDR_A_DQS7 DDR_A_D62

DDR_A_D63

Standar

BOT side

+1.8V+1.8V

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

DDRA_CLK0 <8> DDRA_CLK0# <8>

PM_EXTTS# <8,15>

DVT2- Change +0.9V to +0.9VS

DDRA_CKE1 <8>

DDR_A_BS1 <9> DDR_A_RAS# <9> DDRA_SCS0# <8>

DDRA_ODT0 <8>

DDRA_CLK1 <8> DDRA_CLK1# <8>

DVT2- Remove R406/R357 of DDR address resistors.

Compal Secret Data

2008/10/1 2009/10/1

3

Compal Secret Data

Layout Note:

+1.8V

Place near JP59

2.2U_0603_6.3V6K

C177

1

2

Deciphered Date

DDR_A_DQS#[0..7]<9>

DDR_A_D[0..63]<9>

DDR_A_DM[0..7]<9> DDR_A_DQS[0..7]<9> DDR_A_MA[0..14]<9>

2.2U_0603_6.3V6K

C178

C179

1

2

C179

1

2

+0.9VS

0.1U_0402_16V4Z

1

2

C189

Layout Note: Place these resistor closely JP34,all trace length Max=1.5"

DDR_A_BS0 DDR_A_MA10 DDR_A_MA1 DDR_A_MA5

DDR_A_RAS# DDR_A_MA2 DDR_A_MA0 DDR_A_MA4

DDRA_ODT1 DDR_A_CAS# DDRA_SCS1# DDR_A_WE#

DDRA_CKE1 DDR_A_BS2 DDRA_CKE0

2

2.2U_0603_6.3V6K

2.2U_0603_6.3V6K C181

C181

C180

1

2

Layout Note: Place one cap close to every 2 pullup resistors terminated to +0.9V

0.1U_0402_16V4Z

1

2

C190

1

2

C191

C192

0.1U_0402_16V4Z

0.1U_0402_16V4Z C182

C182

1

2

0.1U_0402_16V4Z

1

2

C193

C183

1

2

0.1U_0402_16V4Z

1

2

C194

0.1U_0402_16V4Z

0.1U_0402_16V4Z C184

C184

1

2

0.1U_0402_16V4Z

1

2

C195

C196

1

2

0.1U_0402_16V4Z

1

2

EVT2- Swap for DDR connector change.

+0.9VS

RP2

18 27 36 45

56_0804_8P4R_5%

18 27 36 45

56_0804_8P4R_5%

RP2

1 8 2 7 3 6 4 5

DDR_A_MA3 DDR_A_MA9 DDR_A_MA8 DDR_A_MA12

RP4

DDR_A_MA6

18

DDR_A_MA7

27

DDR_A_MA11

36

DDR_A_MA14

45

RP6

DDR_A_MA13

18

DDRA_ODT0

27

DDRA_SCS0#

36

DDR_A_BS1

45

Compal Electronics, Inc.

Title

Size Document Number Rev

B

Date: Sheet

Compal Electronics, Inc.

SCHEMATICS,M/B A4161

401562 G

RP1

56_0804_8P4R_5%

RP3

1 8 2 7 3 6 4 5

56_0804_8P4R_5%

RP5

56_0804_8P4R_5%

RP7

1 8 2 7 3 6 4 5

56_0804_8P4R_5%

2

1

C185

+

C186

C186 330U_4V_M

330U_4V_M

2

@

0.1U_0402_16V4Z

1

2

C197

0.1U_0402_16V4Z

1

2

C198

C199

1

0.1U_0402_16V4Z

1

2

C200

1

0.1U_0402_16V4Z

1

2

C201

of

14 48Monday, February 23, 2009

of

14 48Monday, February 23, 2009

of

14 48Monday, February 23, 2009

A

JP31

+DIMM_VREF

2.2U_0603_6.3V6K

1 1

2 2

3 3

4 4

C204

1

0.1U_0402_16V4Z

2

DDRB_CKE0<8>

DDR_B_BS2<9>

DDR_B_BS0<9> DDR_B_WE#<9>

DDR_B_CAS#<9>

DDRB_SCS1#<8>

DDRB_ODT1<8>

PM_SMBDATA<14,16,22,26> PM_SMBCLK<14,16,22,26>

C205

A

1

2

+1.8V

DDR_B_D0 DDR_B_D1

DDR_B_DQS#0 DDR_B_DQS0

DDR_B_D2 DDR_B_D3

DDR_B_D8 DDR_B_D9

DDR_B_DQS#1 DDR_B_DQS1

DDR_B_D10 DDR_B_D11

DDR_B_D17 DDR_B_D20

DDR_B_DQS#2 DDR_B_DQS2

DDR_B_D18 DDR_B_D19

DDR_B_D25 DDR_B_D28

DDR_B_DM3

DDR_B_D30 DDR_B_D31

DDRB_CKE0

DDR_B_BS2 DDR_B_MA12

DDR_B_MA9 DDR_B_MA8

DDR_B_MA5 DDR_B_MA3 DDR_B_MA1

DDR_B_MA10 DDR_B_BS0 DDR_B_WE#

DDR_B_CAS# DDRB_SCS1#

DDRB_ODT1 DDR_B_D32

DDR_B_D33 DDR_B_DQS#4

DDR_B_DQS4 DDR_B_D34

DDR_B_D35 DDR_B_D40

DDR_B_D41 DDR_B_DM5 DDR_B_D42

DDR_B_D43 DDR_B_D48

DDR_B_D49

DDR_B_DQS#6 DDR_B_DQS6

DDR_B_D50 DDR_B_D51

DDR_B_D56 DDR_B_D61

DDR_B_DM7 DDR_B_D63

DDR_B_D58

+3VS

C229

0.1U_0402_16V4Z

1

2

1

VREF

3

VSS

5

DQ0

7

DQ1

9

VSS

11

DQS0#

13

DQS0

15

VSS

17

DQ2

19

DQ3

21

VSS

23

DQ8

25

DQ9

27

VSS

29

DQS1#

31

DQS1

33

VSS

35

DQ10

37

DQ11

39

VSS

41

VSS

43

DQ16

45

DQ17

47

VSS

49

DQS2#

51

DQS2

53

VSS

55

DQ18

57

DQ19

59

VSS

61

DQ24

63

DQ25

65

VSS

67

DM3

69

NC

71

VSS

73

DQ26

75

DQ27

77

VSS

79

CKE0

81

VDD

83

NC

85

BA2

87

VDD

89

A12

91

A9

93

A8

95

VDD

97

A5

99

A3

101

A1

103

VDD

105

A10/AP

107

BA0

109

WE#

111

VDD

113

CAS#

115

NC/S1#

117

VDD

119

NC/ODT1

121

VSS

123

DQ32

125

DQ33

127

VSS

129

DQS4#

131

DQS4

133

VSS

135

DQ34

137

DQ35

139

VSS

141

DQ40

143

DQ41

145

VSS

147

DM5

149

VSS

151

DQ42

153

DQ43

155

VSS

157

DQ48

159

DQ49

161

VSS

163

NC,TEST

165

VSS

167

DQS6#

169

DQS6

171

VSS

173

DQ50

175

DQ51

177

VSS

179

DQ56

181

DQ57

183

VSS

185

DM7

187

VSS

189

DQ58

191

DQ59

193

VSS

195

SDA

197

SCL

199

VDDSPD

B

2

VSS

4

DQ4

6

DQ5

8

VSS

10

DM0

12

VSS

14

DQ6

16

DQ7

18

VSS

20

DQ12

22

DQ13

24

VSS

26

DM1

28

VSS

30

CK0

32

CK0#

34

VSS

36

DQ14

38

DQ15

40

VSS

42

VSS

44

DQ20

46

DQ21

48

VSS

50

NC

52

DM2

54

VSS

56

DQ22

58

DQ23

60

VSS

62

DQ28

64

DQ29

66

VSS

68

DQS3#

70

DQS3

72

VSS

74

DQ30

76

DQ31

78

VSS

80

NC/CKE1

82

VDD

84

NC/A15

86

NC/A14

88

VDD

90

A11

92

A7

94

A6

96

VDD

98

A4

100

A2

102

A0

104

VDD

106

BA1

108

RAS#

110

S0#

112

VDD

114

ODT0

116

NC/A13

118

VDD

120

NC

122

VSS

124

DQ36

126

DQ37

128

VSS

130

DM4

132

VSS

134

DQ38

136

DQ39

138

VSS

140

DQ44

142

DQ45

144

VSS

146

DQS5#

148

DQS5

150

VSS

152

DQ46

154

DQ47

156

VSS

158

DQ52

160

DQ53

162

VSS

164

CK1

166

CK1#

168

VSS

170

DM6

172

VSS

174

DQ54

176

DQ55

178

VSS

180

DQ60

182

DQ61

184

VSS

186

DQS7#

188

DQS7

190

VSS

192

DQ62

194

DQ63

196

VSS

198

SAO

200

SA1

GND

FOX_AS0A426-M6RN-7F~D

203

204

SO-DIMM B

Reserve

BOT side

B

EVT2- Change DDR connector type, JP31 for Reserve.

DDR_B_D5 DDR_B_D4

DDR_B_DM0 DDR_B_D6

DDR_B_D7 DDR_B_D12

DDR_B_D13 DDR_B_DM1

DDRB_CLK0 <8>

DDR_B_D14 DDR_B_D15

DDR_B_D21 DDR_B_D16

DDR_B_DM2 DDR_B_D22

DDR_B_D23 DDR_B_D26

DDR_B_D24 DDR_B_DQS#3

DDR_B_DQS3 DDR_B_D29

DDR_B_D27 DDRB_CKE1

DDR_B_MA14 DDR_B_MA11

DDR_B_MA7 DDR_B_MA6

DDR_B_MA4 DDR_B_MA2 DDR_B_MA0

DDR_B_BS1 DDR_B_RAS# DDRB_SCS0#

DDRB_ODT0 DDR_B_MA13

DDR_B_D36 DDR_B_D37

DDR_B_DM4 DDR_B_D39

DDR_B_D38 DDR_B_D44

DDR_B_D45 DDR_B_DQS#5

DDR_B_DQS5 DDR_B_D46

DDR_B_D47 DDR_B_D52

DDR_B_D53

DDR_B_DM6 DDR_B_D54

DDR_B_D55 DDR_B_D60

DDR_B_D57 DDR_B_DQS#7

DDR_B_DQS7 DDR_B_D62

DDR_B_D59

DDRB_CLK0# <8>

PM_EXTTS# <8,14>

DVT2- Change +0.9V to +0.9VS

DDRB_CKE1 <8>

+1.8V

DDR_B_BS1 <9> DDR_B_RAS# <9> DDRB_SCS0# <8>

DDRB_ODT0 <8>

DDRB_CLK1 <8> DDRB_CLK1# <8>

DVT2- Remove R407/R408 of DDR address resistors.

+3VS

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

DDR_B_DQS#[0..7]<9>

DDR_B_D[0..63]<9>

DDR_B_DM[0..7]<9> DDR_B_DQS[0..7]<9> DDR_B_MA[0..14]<9>

Layout Note:

+1.8V

Place near JP58

2.2U_0603_6.3V6K

2.2U_0603_6.3V6K C206

C206

1

2

+0.9VS

0.1U_0402_16V4Z

1

2

C215

Layout Note: Place these resistor closely JP10,all trace length Max=1.5"

DDR_B_MA5 DDR_B_MA8

DDR_B_MA9 DDR_B_MA12

DDRB_SCS0# DDR_B_MA7 DDR_B_RAS# DDR_B_MA2 DDR_B_MA4

DDR_B_BS0 DDR_B_MA10 DDR_B_MA1 DDR_B_MA3

DDRB_ODT1 DDRB_SCS1# DDR_B_CAS# DDR_B_WE#

Compal Secret Data

2008/10/1 2009/10/1

C

Compal Secret Data

Deciphered Date

2.2U_0603_6.3V6K

C207

C208

1

2

Layout Note: Place one cap close to every 2 pullup Resistors terminated to +0.9V

1

2

C216

C208

1

2

0.1U_0402_16V4Z

1

2

C217

C218

EVT2- Swap for DDR connector change. Add R1022 for DDRB_CKE1. Add R1023/R1024 for DDR_B_BS2/DDRB_CKE0.

RP8

1 8 2 7 3 6 4 5

56_0804_8P4R_5%

RP10

1 8 2 7 3 6 4 5

56_0804_8P4R_5%

RP12

1 8 2 7 3 6 4 5

56_0804_8P4R_5%

RP14

1 8 2 7 3 6 4 5

56_0804_8P4R_5%

D

2.2U_0603_6.3V6K

C209

1

2

0.1U_0402_16V4Z

1

2

C219

+0.9VS

R1023 56_0402_5%R1023 56_0402_5% R1024 56_0402_5%R1024 56_0402_5%

56_0804_8P4R_5%

R1022 56_0402_5%R1022 56_0402_5%

D

0.1U_0402_16V4Z

C210

1

2

0.1U_0402_16V4Z

1

2

C220

1 2 1 2

RP11

RP13

1 2

E

0.1U_0402_16V4Z

0.1U_0402_16V4Z C213

C213

C212

C211

1

2

0.1U_0402_16V4Z

1

2

C221

18

DDR_B_MA11

27

DDR_B_MA6

36 45

18 27

DDR_B_MA0

36

DDR_B_BS1

45

2

C222

C223

DDR_B_BS2 DDRB_CKE0

DDR_B_MA14

DDR_B_MA13 DDRB_ODT0

DDRB_CKE1

Title

Size Document Number Rev

B

Date: Sheet

1

2

0.1U_0402_16V4Z

1

2

C224

C225

Compal Electronics, Inc.

SCHEMATICS,M/B A4161

401562 G

C214

+

0.1U_0402_16V4Z

1

2

C226

1

C188

C188 330U_4V_M

330U_4V_M

2

@

0.1U_0402_16V4Z

1

2

C227

15 48Monday, February 23, 2009

E

of

A

FSC FSB REF

CLKSEL2

CLKSEL1

FSA

CLKSEL0

0

CPU MHz

266

0 1000 133 33.31 14.318 96.0 48.0

0 1001 200 33.30 14.318 96.0 48.0

1 1

0 1001 166 33.31 14.318 96.0 48.0

1 1000 333 33.30 14.318 96.0 48.0

1 1000 100 33.31 14.318 96.0 48.0

1 1001 400 33.30 14.318 96.0 48.0

111

CLK_XTAL_OUT

Y3

2 2

18P_0402_50V8J

PVT-Remove CLK_14M_IR and R734, because remove SMSC IR Bluster solution.

CLK_PCI_TV1<30> CLK_PCI_TV2<30>

3 3

CLK_ICH

CLK_EC

2

C838

1

CPU_BSEL0<5,8>

0 = SRC8/SRC8# 1 = ITP/ITP# 0 = Enable DOT96 & SRC1(UMA) 1 = Enable SRC0 & 27MHz(DIS)

PVT-modify R719/R724 signal from CLK_SIO to CLK ICH.

+3VS +3VS

12

R719

R719 10K_0402_5%@

4 4

10K_0402_5%@

CLK_ICH CLK_EC

12

R724

R724 10K_0402_5%

10K_0402_5%

A

Y3

14.31818MHz_20P_1BX14318BE1A

R701 22_0402_5%

1 2

TV@

R702 22_0402_5%

1 2

TV@

B

PCI

SRC

MHz

1000

33.30

CLK_XTAL_IN

12

2

1

R708 2.2K_0402_5%R708 2.2K_0402_5%

12

R720 10K_0402_5%

10K_0402_5%

12

R726 10K_0402_5%

10K_0402_5%

B

MHz

14.318 96.0 48.0

Reserved

Routing the trace at least 10mil

C839

18P_0402_50V8J

CLK_TV

CLK_FSA

12

CLK_FSC

12

R52

R52 10K_0402_5%

10K_0402_5%

PM@R720

PM@

GM@R726

GM@

C

R680

1 2

DOT_96 MHz

+3VS +3VS_CK505 +1.05VS +1.05VS_CK505

USB MHz

+3VS_CK505

+1.05VS_CK505

H_STP_CPU#<22>

H_STP_PCI#<22>

0_0805_5%

C824

10U_0805_10V4Z

1

2

EVT2- ICH PCI CLK need to be used PCI_F5

CLK_PCI_DDR<33>

PVT-Delete CLK_PCI_IR/ CLK_IR, because remove SMSC IR Bluster solution.

CLK_PCI_EC<32> CLK_PCI_ICH<20>

EVT2- ICH PCI CLK need to be used PCI_F5

CK_PWRGD<22>

CLK_48M_ICH<22>

CPU_BSEL1<5,8> CPU_BSEL2<5,8>

CLK_14M_ICH<22>

C

1 2

R728 33_0402_5%R728 33_0402_5%

CLK_TV

1 2

R705 33_0402_5%R705 33_0402_5%

1 2

R700 33_0402_5%R700 33_0402_5%

CLK_XTAL_IN CLK_XTAL_OUT

1 2

R709 33_0402_5%R709 33_0402_5%

R689 10K_0402_5%@R689 10K_0402_5%@

1 2

R694 33_0402_5%R694 33_0402_5%

D

0.1U_0402_16V4Z

1

C825

2

12

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

1

C826

0.1U_0402_16V4Z

2

19 72 12 27 55

52 38 62 31 66 23

53 54

CLK_SIO

13 14 15

CLK_EC

16

CLK_ICH

17

11

CLK_FSA

20

CLK_FSC CLK_14ICH

69

18 22 30 26 34 59 42

D

0.1U_0402_16V4Z

1

C827

C828

0.1U_0402_16V4Z

2

U18

6

VDDREF VDD48 VDDCPU VDDPCI VDDPLL3 VDDSRC

VDDSRC_IO VDDSRC_IO VDDSRC_IO VDDPLL3_IO VDDCPU_IO VDD96_IO

CPU_STOP# PCI_STOP#

PCI1 PCI2/TME PCI3 PCI4/27_SELECT PCI_F5/ITP_EN

1

CK_PWRGD/PD#

5

X1

4

X2

NC

USB_48MHz/FSLA

2

FSLB/TEST_MODE

7

FSLC/TEST_SEL/REF0

8

REF1

GNDCPU

3

GNDREF GNDPCI GND48 GND GND GNDSRC GNDSRC GNDSRC

SLG8SP556VTR

2008/10/1 2009/10/1

1

2

E

0.1U_0402_16V4Z

1

C829

0.1U_0402_16V4Z

2

Compal Secret Data

E

1

C830

2

CPUT0_LPR_F

CPUC0_LPR_F

CPUT1_LPR_F

CPUC1_LPR_F

SRCT0_LPR/DOTT_96_LPR

SRCC0_LPR/DOTC_96_LPR

27MHz_NonSS/SRCT1_LPR/SE1

27MHz_SS/SRCC1_LPR/SE2

SRCT2_LPR/SATAT_LPR

SRCC2_LPR/SATAC_LPR

SRCT3_LPR SRCC3_LPR

SRCT4_LPR SRCC4_LPR

SRCT6_LPR SRCC6_LPR

SRCT7_LPR SRCC7_LPR

CPUT2_ITP_LPR/SRCT8_LPR CPUC2_ITP_LPR/SRCC8_LPR

SRCT9_LPR SRCC9_LPR

SRCT10_LPR SRCC10_LPR

SRCT11_LPR SRCC11_LPR

GND-PAD

73

Deciphered Date

SDATA

SCLK

CR#3 CR#4 CR#6 CR7#

CR#9 CR10# CR#11

CR#A

F

9 10

71 70

68 67

CLK_DISPLY

24

CLK_DISPLY#

25

CLK_SSC

28

CLK_SSC#

29

32 33

35 36

39 40

57 56

61 60

64 63

44 45

50 51

48 47

37 41 58 65 43

CLKREQ_5IN1#

49 46 21

F

R681

1 2

0_0805_5%

CLKREQ_SATA# CLKREQ_WLAN# CLKREQ_NEW# CLKREQ_3GPLL# CLKREQ_NAND#

CLKREQ_TMA#

C831

10U_0805_10V4Z

1 2

R713 0_0402_5%GM@R713 0_0402_5%GM@

1 2

R711 0_0402_5%GM@R711 0_0402_5%GM@

SRC8 SRC8#

0.1U_0402_16V4Z

1

C833

C832

2

0.1U_0402_16V4Z

CLK_DISPLY CLK_DISPLY#

SRC8 SRC8#

12

R730 10K_0402_5%R730 10K_0402_5%

Title

Size Document Number Rev

Custom

Date: Sheet

G

10U_0805_10V4Z

1

C834

2

PM_SMBDATA <14,15,22,26> PM_SMBCLK <14,15,22,26>

CLK_CPU_BCLK <4> CLK_CPU_BCLK# <4>

CLK_MCH_BCLK <7> CLK_MCH_BCLK# <7>

R714 0_0402_5%PM@R714 0_0402_5%PM@ R715 0_0402_5%PM@R715 0_0402_5%PM@

R710 0_0402_5%GM@R710 0_0402_5%GM@ R712 0_0402_5%GM@R712 0_0402_5%GM@

CLK_DREF_SSC <8> CLK_DREF_SSC# <8>

CLK_PCIE_ICH <20> CLK_PCIE_ICH# <20>

CLK_PCIE_SATA <21> CLK_PCIE_SATA# <21>

CLK_WLAN <26> CLK_WLAN# <26>

CLK_NEW <26> CLK_NEW# <26>

CLK_MCH_3GPLL <8> CLK_MCH_3GPLL# <8>

R729 0_0402_5%@R729 0_0402_5%@

1 2

R743 0_0402_5%@R743 0_0402_5%@

1 2

R682 0_0402_5%R682 0_0402_5%

1 2

R683 0_0402_5%R683 0_0402_5%

1 2

CLK_NAND <27> CLK_NAND# <27>

CLK_5IN1 <29> CLK_5IN1# <29>

CLK_TMA <27> CLK_TMA# <27>

CLKREQ_SATA# <22> CLKREQ_WLAN# <26> CLKREQ_NEW# <26> CLKREQ_3GPLL# <8> CLKREQ_NAND# <27>

CLKREQ_TMA# <27>

Compal Electronics, Inc.

SCHEMATICS,M/B A4161

G

0.1U_0402_16V4Z

1

C835

C836

2

0.1U_0402_16V4Z

CPU

NB

12 12

NB_SSC (UMA)

ICH-DMI

SATA

WLAN

ExpressCard

3G_PLL

ROBSON/HDDVD

CardReader

TMA

CLKREQ_SATA# CLKREQ_WLAN# CLKREQ_NEW# CLKREQ_3GPLL# CLKREQ_NAND#

CLKREQ_TMA#

401562 G

1

C837

2

0.1U_0402_16V4Z

CLK_PCIE_VGA <17> CLK_PCIE_VGA# <17>

CLK_DREF_96M <8> CLK_DREF_96M# <8>

CLK_XDP <4> CLK_XDP# <4>

CLK_LAN <28> CLK_LAN# <28>

R725 10K_0402_5%R725 10K_0402_5% R723 10K_0402_5%R723 10K_0402_5% R717 10K_0402_5%R717 10K_0402_5% R716 10K_0402_5%R716 10K_0402_5% R722 10K_0402_5%R722 10K_0402_5%

R721 10K_0402_5%R721 10K_0402_5%

H

1

2

VGA

NB (UMA)

12 12 12 12 12

12

of

16 48Monday, February 23, 2009

of

16 48Monday, February 23, 2009

of

16 48Monday, February 23, 2009

H

XDP LOM

+3VS

5

VGA BOARD Conn.

PCEI_GTX_C_MRX_N[0..15] PCIE_MTX_C_GRX_N[0..15] PCEI_GTX_C_MRX_P[0..15] PCIE_MTX_C_GRX_P[0..15]

D D

VGA_CRT_VSYNC<18>

VGA_CRT_HSYNC<18>

VGA_CRT_B<18> VGA_CRT_G<18> VGA_CRT_R<18>

C C

B B

A A

VGA_HPD<19>

VGA_DVI_SCLK<19>

VGA_DVI_SDATA<19>

VGA_DVI_TXD2+<19> VGA_DVI_TXD2-<19>

VGA_DVI_TXD1+<19> VGA_DVI_TXD1-<19>

VGA_DVI_TXD0+<19> VGA_DVI_TXD0-<19>

VGA_DVI_TXC+<19> VGA_DVI_TXC-<19>

CLK_PCIE_VGA<16> CLK_PCIE_VGA#<16>

5

PCIE_GTX_C_MRX_P[0..15] <10,19>

B+

VGA_TZOUT2VGA_TZOUT2+

VGA_TZCLKVGA_TZCLK+

VGA_TZOUT1VGA_TZOUT1+

VGA_TZOUT0- DAC_BRIG VGA_TZOUT0+

PCEI_GTX_C_MRX_P0 PCEI_GTX_C_MRX_N0

PCEI_GTX_C_MRX_P1 PCEI_GTX_C_MRX_N1

PCEI_GTX_C_MRX_P2 PCEI_GTX_C_MRX_N2

PCEI_GTX_C_MRX_P3 PCEI_GTX_C_MRX_N3

PCEI_GTX_C_MRX_P4 PCEI_GTX_C_MRX_N4

PCEI_GTX_C_MRX_P5 PCEI_GTX_C_MRX_N5

PCEI_GTX_C_MRX_P6 PCEI_GTX_C_MRX_N6

PCEI_GTX_C_MRX_P7 PCEI_GTX_C_MRX_N7

PCEI_GTX_C_MRX_P8 PCEI_GTX_C_MRX_N8

PCEI_GTX_C_MRX_P9 PCEI_GTX_C_MRX_N9

PCEI_GTX_C_MRX_P10 PCEI_GTX_C_MRX_N10

PCEI_GTX_C_MRX_P11 PCEI_GTX_C_MRX_N11

PCEI_GTX_C_MRX_P12 PCEI_GTX_C_MRX_N12

PCEI_GTX_C_MRX_P13 PCEI_GTX_C_MRX_N13

PCEI_GTX_C_MRX_P14 PCEI_GTX_C_MRX_N14

PCEI_GTX_C_MRX_P15 PCEI_GTX_C_MRX_N15

JPV1

1

3

5

7

9

11

13

15

17

19

21

23

25

27

29

31

33

35

37

39

41

43

45

47

49

51

53

55

57

59

61

63

65

67

69

71

73

75

77

79

81

83

85

87

89

91

93

95

97

99

101

103

105

107

109

111

113

115

117

119

121

123

125

127

129

131

133

135

137

139

141

143

145

147

149

151

153

155

157

159

161

163

165

167

169

171

173

175

177

179

181

183

185

187

189

191

193

195

197

199

201

GND

ACES_88394-2A71@

GND

2 4 6

8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98

100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202

4

PCIE_MTX_C_GRX_N[0..15] <10,19>PCIE_GTX_C_MRX_N[0..15] <10> PCIE_MTX_C_GRX_P[0..15] <10,19>

B+

PVT- VGA connector burned issue, re-assign power pin define, delete 2 B+ pin.

+1.5VS+1.5VS

VGA_TXCLK-

VGA_TXCLK+

VGA_TXOUT2-

VGA_TXOUT2+

VGA_TXOUT0-

VGA_TXOUT0+

VGA_TXOUT1-

VGA_TXOUT1+

VGA_EDID_DATA

VGA_EDID_CLK

VGA_ENVDD

PCIE_MTX_C_GRX_P0 PCIE_MTX_C_GRX_N0

PCIE_MTX_C_GRX_P1 PCIE_MTX_C_GRX_N1

PCIE_MTX_C_GRX_P2

PCIE_MTX_C_GRX_N2

PCIE_MTX_C_GRX_P3

PCIE_MTX_C_GRX_N3

PCIE_MTX_C_GRX_P4

PCIE_MTX_C_GRX_N4

PCIE_MTX_C_GRX_P5

PCIE_MTX_C_GRX_N5

PCIE_MTX_C_GRX_P6

PCIE_MTX_C_GRX_N6

PCIE_MTX_C_GRX_P7

PCIE_MTX_C_GRX_N7

PCIE_MTX_C_GRX_P8

PCIE_MTX_C_GRX_N8

PCIE_MTX_C_GRX_P9

PCIE_MTX_C_GRX_N9

PCIE_MTX_C_GRX_P10 PCIE_MTX_C_GRX_N10

PCIE_MTX_C_GRX_P11 PCIE_MTX_C_GRX_N11

PCIE_MTX_C_GRX_P12 PCIE_MTX_C_GRX_N12

PCIE_MTX_C_GRX_P13 PCIE_MTX_C_GRX_N13

PCIE_MTX_C_GRX_P14

PCIE_MTX_C_GRX_N14 PCIE_MTX_C_GRX_P15

PCIE_MTX_C_GRX_N15

4

+5VALW

+3VS

AZ_RST_VGA# <21> AZ_SDIN3_VGA <21> AZ_SDOUT_VGA <21> AZ_SYNC_VGA <21>

AZ_BITCLK_VGA <21>VGA_ENBKL<32>

EC_SMB_CK2 <4,32> EC_SMB_DA2 <4,32>

PLT_RST# <8,20,26..29,32,33> SUSP# <26,29,32,35,40> ACIN <22,32,34,36,38>

VGA_DDC_CLK <18>

VGA_DDC_DATA <18>

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

LCD/PANEL BD. Conn.

DVT- Modify R170 from 1M_0603 to 470_0805 Modify R171 from 300 to 1M_0402

R173 0_0402_5%

GMCH_ENVDD<10>

1 2

VGA_ENVDD

2N7002DW-T/R7_SOT363-6

+LCD_VDD

12

61

GM@

100K_0402_5%

DVT2-Change JP6, LVDS connector type.

LCD_TZOUT0LCD_TZOUT0+ LCD_TZOUT2LCD_TZOUT2+ LCD_TZOUT1+ LCD_TZOUT1-

LCD_TXOUT0+

LCD_TXOUT0-

LCD_TXOUT1+

LCD_TXOUT1LCD_TXOUT2-

LCD_TXOUT2+

LCD_EDID_CLK

L2

+LCD_VDD

0.1U_0402_16V4Z

VGA_EDID_CLK VGA_EDID_DATA

VGA_TXCLKVGA_TXCLK+

VGA_TXOUT0-

VGA_TXOUT0+

VGA_TXOUT1VGA_TXOUT1+

VGA_TXOUT2VGA_TXOUT2+

VGA_TZOUT0VGA_TZOUT0+

VGA_TZOUT1VGA_TZOUT1+

VGA_TZOUT2VGA_TZOUT2+

VGA_TZCLKVGA_TZCLK+

2008/10/1 2009/10/1

3

1 2

0_0805_5%

1

C242

2

Compal Secret Data

LCD_EDID_DATA

1

C396

4.7U_0603_6.3V6K

2

R1770_0402_5% PM@ R1770_0402_5% PM@

12

R1790_0402_5% PM@ R1790_0402_5% PM@

12

R1810_0402_5% PM@ R1810_0402_5% PM@

12

R1830_0402_5% PM@ R1830_0402_5% PM@

12

R1850_0402_5% PM@ R1850_0402_5% PM@

12

R1870_0402_5% PM@ R1870_0402_5% PM@

12

R1890_0402_5% PM@ R1890_0402_5% PM@

12

R1910_0402_5% PM@ R1910_0402_5% PM@

12

R1930_0402_5% PM@ R1930_0402_5% PM@

12

R1950_0402_5% PM@ R1950_0402_5% PM@

12

R1970_0402_5% PM@ R1970_0402_5% PM@

12

R1990_0402_5% PM@ R1990_0402_5% PM@

12

R2010_0402_5% PM@ R2010_0402_5% PM@

12

R2030_0402_5% PM@ R2030_0402_5% PM@

12

R2050_0402_5% PM@ R2050_0402_5% PM@

12

R2070_0402_5% PM@ R2070_0402_5% PM@

12

R2090_0402_5% PM@ R2090_0402_5% PM@

12

R2110_0402_5% PM@ R2110_0402_5% PM@

12

Deciphered Date

+LCDVDD_R

LCD_EDID_CLK LCD_EDID_DATA

LCD_TXCLK-

LCD_TXCLK+

LCD_TXOUT0-

LCD_TXOUT0+

LCD_TXOUT1-

LCD_TXOUT1+

LCD_TXOUT2-

LCD_TXOUT2+

LCD_TZOUT0-

LCD_TZOUT0+

LCD_TZOUT1-

LCD_TZOUT1+ LCD_TZOUT2-

LCD_TZOUT2+

LCD_TZCLK-

LCD_TZCLK+

2

+3V_SB

R170

R170 470_0805_5%

470_0805_5%

Q5A

2

Q5B

5

12

2N7002DW-T/R7_SOT363-6

R175

JP6

GND41GND

39

37

35

33

31

29

27

25

23

21

19

17

15

13

11

9

7

5

3

1

ACES_87142-4041_40P-T

R178 0_0402_5%GM@R178 0_0402_5%GM@ R180 0_0402_5%GM@R180 0_0402_5%GM@

R182 0_0402_5%GM@R182 0_0402_5%GM@ R184 0_0402_5%GM@R184 0_0402_5%GM@

R186 0_0402_5%GM@R186 0_0402_5%GM@ R188 0_0402_5%GM@R188 0_0402_5%GM@

R190 0_0402_5%GM@R190 0_0402_5%GM@ R192 0_0402_5%GM@R192 0_0402_5%GM@

R194 0_0402_5%GM@R194 0_0402_5%GM@ R196 0_0402_5%GM@R196 0_0402_5%GM@

R198 0_0402_5%GM@R198 0_0402_5%GM@ R200 0_0402_5%GM@R200 0_0402_5%GM@

R202 0_0402_5%GM@R202 0_0402_5%GM@ R204 0_0402_5%GM@R204 0_0402_5%GM@

R206 0_0402_5%GM@R206 0_0402_5%GM@ R208 0_0402_5%GM@R208 0_0402_5%GM@

R210 0_0402_5%GM@R210 0_0402_5%GM@ R212 0_0402_5%GM@R212 0_0402_5%GM@

2

12

R171

R171 1M_0402_5%

1M_0402_5%

12

R172 100K_0402_5%R172 100K_0402_5%

3

1000P_0402_50V7K

4

@JP6

@

42

LCD_TZCLK+

40

40 38 36 34 32 30 28 26 24 22 20 18 16 14 12 10

8 6 4 2

38 36 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2

1 2 1 2

LCD_TZCLK-

BKOFF#

DAC_BRIG INVT_PWM

LCD_TXCLKLCD_TXCLK+

Title

Size Document Number Rev

Date: Sheet

Date: Sheet of

C238

+3VS

W=60mils

1

S

G

Q6

2

AO3413_SOT23-3

D

1

2

D

1 3

1

C239

4.7U_0603_6.3V6K

2

BKOFF#

100P_0402_25V8K

BKOFF# <32> DAC_BRIG <32>

INVT_PWM <32>

+LCD_INV

C244

@ C244

@

68P_0402_50V8J

UMA_LCD_CLK UMA_LCD_DAT

Compal Electronics, Inc.

SCHEMATICS,M/B A4161

401562

2

+LCD_VDD

1

@C239

@

2

12

R6364.7K_0402_5% @ R6364.7K_0402_5% @

C264

@ C264

@

+3VS

1

C241

0.1U_0402_16V4Z

2

FBMA-L11-201209-221LMA30T_0805

1

C245

0.1U_0402_25V4K

2

UMA_LCD_CLK <10> UMA_LCD_DAT <10>

UMA_TXCLK- <10> UMA_TXCLK+ <10>

UMA_TXOUT0- <10> UMA_TXOUT0+ <10>

UMA_TXOUT1- <10> UMA_TXOUT1+ <10>

UMA_TXOUT2- <10> UMA_TXOUT2+ <10>

UMA_TZOUT0- <10>

UMA_TZOUT0+ <10>

UMA_TZOUT1- <10>

UMA_TZOUT1+ <10>

UMA_TZOUT2- <10>

UMA_TZOUT2+ <10>

UMA_TZCLK- <10>

UMA_TZCLK+ <10>

1

C237

4.7U_0603_6.3V6K

W=60mils

C240

0.1U_0402_16V4Z

+3VS

DVT- Add C264 for EMI.

1

2

L3

17 48Monday, February 23, 2009

1

B++LCD_INV

12

G

of

G

A

B

C

D

E

CRT CONNECTOR

DVT- Update F1 (SP04301P000) symbol for Layout.

C253

D3

@

1

2

1

3

1

C254

2

10P_0402_50V8J

HSYNC

VSYNCD_CRT_VSYNC

10P_0402_50V8J

C250

PM@C250

PM@C247

R222

PM@R222

1 1

VGA_CRT_R<17> UMA_CRT_R<10> VGA_CRT_G<17> UMA_CRT_G<10> VGA_CRT_B<17> UMA_CRT_B<10>

2 2

VGA_CRT_HSYNC<17> UMA_CRT_HSYNC<10>

VGA_CRT_VSYNC<17> UMA_CRT_VSYNC<10>

1 2

R213 0_0402_5%PM@R213 0_0402_5%PM@

1 2

R215 0_0402_5%GM@R215 0_0402_5%GM@

1 2

R216 0_0402_5%PM@R216 0_0402_5%PM@

1 2

R218 0_0402_5%GM@R218 0_0402_5%GM@

1 2

R219 0_0402_5%PM@R219 0_0402_5%PM@

1 2

R221 0_0402_5%GM@R221 0_0402_5%GM@

1 2

R228 0_0402_5%PM@R228 0_0402_5%PM@

1 2

R230 0_0402_5%GM@R230 0_0402_5%GM@

1 2

R234 0_0402_5%PM@R234 0_0402_5%PM@

1 2

R235 0_0402_5%GM@R235 0_0402_5%GM@

12

R222

R222 GM@

GM@

1 2

C256 0.1U_0402_16V4ZC256 0.1U_0402_16V4Z

CRT_VSYNC

75_0402_1%

R223

75_0402_1%

R224

75_0402_1%

12

R223

R223 GM@

GM@

150_0402_1%

PM@

PM@R223

PM@

PM@R224

PM@

CRT_R

CRT_G

CRT_B

R224

R224 GM@

GM@

150_0402_1%

12

C247

GM@

150_0402_1%

+CRT_VCC

5

P

A2Y

G

74AHCT1G125GW_SOT353-5

3

+CRT_VCC

1 2

C261

0.1U_0402_16V4Z

1

OE#

PM@

12P_0402_50V8J

C248

PM@C248

PM@

12P_0402_50V8J

C249

PM@C249

PM@

12P_0402_50V8J

1

C248

C248 GM@

GM@

2

22P_0402_50V8J

R225 10K_0402_5%R225 10K_0402_5%

U6

4

1

5

U7

P

OE#

A2Y

G

74AHCT1G125GW_SOT353-5

3

L4

1 2

BLM15BB121SN1D_0402

L5

1 2

BLM15BB121SN1D_0402

L6

1 2

BLM15BB121SN1D_0402

1

C249

C249 GM@

GM@

2

22P_0402_50V8J

12

D_CRT_HSYNCCRT_HSYNC

4

1

C250

GM@

2

L7 10_0402_5%L7 10_0402_5%

L8 10_0402_5%L8 10_0402_5%

6P_0402_50V8D

C251

6P_0402_50V8D

C252

6P_0402_50V8D

1

C251

C251 GM@

GM@

2

6P_0402_50V8D

1 2

PM@C247

PM@C251

PM@

PM@C252

PM@

C252

GM@

CRT_R_L

CRT_G_L

CRT_B_L

1

2

PJDLC05_SOT23-3

1 2

R214

R214 0_0402_5%

0_0402_5%

1 2

R217

R217 0_0402_5%

0_0402_5%

1 2

R220

R220 0_0402_5%

0_0402_5%

6P_0402_50V8D

1

C257

2

@ D3

@

C258

10P_0402_50V8J

2

@

1

2

1

C255

@

2

10P_0402_50V8J

D4

@D4

@

PJDLC05_SOT23-3

3

CRT_R_L2

CRT_G_L2 CRT_G_L2

CRT_B_L2

1

2

10P_0402_50V8J

VGA_DDC_DATA<17> UMA_CRT_DATA<10> VGA_DDC_CLK<17> UMA_CRT_CLK<10>

+CRT_VCC

1 2

R229 0_0402_5%PM@R229 0_0402_5%PM@

1 2

R231 0_0402_5%GM@R231 0_0402_5%GM@

1 2

R232 0_0402_5%PM@R232 0_0402_5%PM@

1 2

R233 0_0402_5%GM@R233 0_0402_5%GM@

+5VS +CRT_VCC_R +CRT_VCC

D6

2 1

RB491D_SC59-3

CRT_R_L2 CRT_DDC_DAT

HSYNC CRT_B_L2

VSYNC

CRT_DDC_CLK

Q67A

2N7002DW-T/R7_SOT363-6

F1

21

1.1A_6V_MINISMDC110F-2

JP7

6

11

1 7

12

2 8

13

3 9

14

4 10 15

5

SUYIN_070549FR015S208CR

+3VS

4.7K_0402_5%

5

Q67B

3

4

2

2N7002DW-T/R7_SOT363-6

61

470P_0402_50V8J

0.1U_0402_16V4Z@

16 17

R226

C259

@ C259

@

C246

1

2

+CRT_VCC

1 2

CRT_DDC_CLK

1

2

R227

4.7K_0402_5%

CRT_DDC_DAT

C260

@C260

@

470P_0402_50V8J

3 3

4 4

Security Classification

2008/10/1 2009/10/1

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2008/10/1 2009/10/1

C

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

D

Date: Sheet

Compal Electronics, Inc.

SCHEMATICS,M/B A4161

401562 G

E

of

18 48Monday, February 23, 2009

of

18 48Monday, February 23, 2009

of

18 48Monday, February 23, 2009

5

@

1 2

R1035 0_0402_5%

PCIE_GTX_C_MRX_P3<10,17>

12

D

Q11

R244

7.5K_0402_1%

7.5K_0402_1% IHDMI@

IHDMI@

D D

DVT-Add R1035 for B version Level shift and DVT use this solution.

DVT-Change Level Shifter from SA00001U910 (CHRONTEL_CH7318B) to SA00002D700 ( PARADE _PS8101T) PVT-Change Level Shifter from SA00002D700 to SA00001U920

PVT-R249 change to 910_1% (SD00000B880).

C C

PVT-R253/R255/R257/R258 change to 200 Ohm, and C276/C277/C278/C279 change to 0 Ohm.

VGA_DVI_TXC-

VGA_DVI_TXD0- VGA_DVI_TXD0+

B B

@

R145 0_0402_5%

R145 0_0402_5% R146 0_0402_5%

R146 0_0402_5% R144 0_0402_5%IHDMI@R144 0_0402_5%IHDMI@

R143

R253 240_0402_1%

240_0402_1%

R255 270_0402_1%

270_0402_1%

R257 270_0402_1%

270_0402_1%

R258 270_0402_1%

270_0402_1%

@

IHDMI@R253

IHDMI@

1 2

IHDMI@R255

IHDMI@

1 2

IHDMI@R257

IHDMI@

1 2

IHDMI@R258

IHDMI@

1 2

12 12

0_0402_5%IHDMI@

1 2

C276 0_0402_5%

1 2

C277 0_0402_5%

1 2

C278 0_0402_5%

1 2

C279 0_0402_5%

HDMI CEC Controller

EC_SMB_CK1<32,34,37>

+5VL

CEC_RST#

CEC@C445

CEC@

12

CEC_XOUT

12

CEC_XIN

12

HDMI_CECIN

HDMI_CECOUT

22P_0402_50V8J

5

R998 4.7K_0402_5%CEC@R998 4.7K_0402_5%CEC@

R997 4.7K_0402_5%CEC@R997 4.7K_0402_5%CEC@

R996 47K_0402_5%CEC@R996 47K_0402_5%CEC@

R1000 4.7K_0402_5%CEC@R1000 4.7K_0402_5%CEC@

A A

1

C445

2

0.1U_0402_16V4Z

2N7002_SOT23-3

2N7002_SOT23-3 IHDMI@

IHDMI@

SDVO_SDATA<8>

SDVO_SCLK<8>

IHDMI@

@ C841

@

S

VGA_DVI_TXC+

VGA_DVI_TXD2+VGA_DVI_TXD2-

VGA_DVI_TXD1+VGA_DVI_TXD1-

U4

1

2

3

4

5

6

7

8

9

10

C841

@

R242

12

20K_0402_5%

IHDMI@

13

2

G

12

R245

IHDMI@R245

IHDMI@

20K_0402_5%

+3VS

R249

IHDMI@R249

IHDMI@

976_0402_1%

12

HPD_7318

VGA_DVI_TXCVGA_DVI_TXC+

VGA_DVI_TXD0VGA_DVI_TXD0+

VGA_DVI_TXD1VGA_DVI_TXD1+

VGA_DVI_TXD2VGA_DVI_TXD2+

CEC@U4

CEC@

P3_5/SSCK/SCL/CMP1_2

P3_7/CNTR0#/SSO/TXD1

RESET#

XOUT/P4_7

VSS/AVSS

XIN/P4_6

VCC/AVCC

MODE

P4_5/INT0#/RXD1

P1_7/CNTR00/INT10#

Y5

@Y5

@

1 2

2

8MHZ_20PF_X8A008000IK1H

1

+3VS

HPD_7318

U8

2

VCC3V

11

VCC3V

15

VCC3V

21

VCC3V

26

VCC3V

33

VCC3V

40

VCC3V

46

VCC3V

3

FUNCTION1

4

FUCNTION2

6

ANALOG1(REXT)

7

HPD_SOURCE

8

SDA_SOURCE

9

SCL_SOURCE

10

ANALOG2

13

OUT_D4+

14

OUT_D4-

16

OUT_D3+

17

OUT_D3-

19

OUT_D2+

20

OUT_D2-

22

OUT_D1+

23

OUT_D1-

1

GND

5

GND

12

GND

18

GND

24

GND

27

GND

31

GND

36

GND

37

GND

43

GND

PS8101T_QFN48_7X7

PS8101T_QFN48_7X7 IHDMI@

IHDMI@

DVT- Change U4 with C32 code.

P3_3/TCIN/INT3#/SSI00/CMP1_0

CEC_XOUTCEC_XIN

2

C840 22P_0402_50V8J

22P_0402_50V8J

1

4

+3VS

10U_0805_10V4Z

P1_6/CLK0/SSI01

P1_5/RXD0/CNTR01/INT11#

P1_4/TXD0

P1_3/KI3#/AN11/TZOUT

P1_2/KI2#/AN10/CMP0_2

P4_2/VREF

P1_1/KI1#/AN9/CMP0_1

P1_0/KI0#/AN8/CMP0_0

P3_4/SCS#/SDA/CMP1_1

R5F211A4C32SP#W4_LSSOP20

@C840

@

4

0.1U_0402_16V4Z

1

2

1

C268

C268 IHDMI@

IHDMI@

C269

C269 IHDMI@

IHDMI@

2

11

CEC_TEST

12

CEC_FSHUPD

13

CEC_FSHUPD (Pin13)

14

Low= Force to update flash.

15

16

HDMI_SCLK

17

HDMI_SDATA

18

HDMI_HPD_R

19

20

3

0.1U_0402_16V4Z

1

2

0.1U_0402_16V4Z

SCL_SINK SDA_SINK

HPD_SINK

DDC_EN

FUNCTION3 FUNCTION4

R994

1 2

R995

1 2

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

1

C271

C270

C270 IHDMI@

IHDMI@

IN_D4+

IN_D4-

IN_D3+

IN_D3-

IN_D2+

IN_D2-

IN_D1+

IN_D1-

4.7K_0402_5%CEC@

0.1U_0402_16V4Z

EC_SMB_DA1 <32,34,37>

Issued Date

C271 IHDMI@

IHDMI@

2

0.1U_0402_16V4Z

25

OE*

CEC_INT# <32>

10K_0402_5%

28 29

DVT- Change U8.30 from HDMI_HPD to HDMI_HPD_R

30 32

34 35

48 47

45 44

42 41

39 38

C281

HDMI@

0.1U_0402_16V4Z

1

C446

C446 CEC@

CEC@

1U_0402_6.3V4Z

2

0.1U_0402_16V4Z

1

2

R243

R247 4.7K_0402_5%

IHDMI@

R139 10K_0402_5%IHDMI@R139 10K_0402_5%IHDMI@ R140 10K_0402_5%IHDMI@R140 10K_0402_5%IHDMI@ R141 0_0402_5%@R141 0_0402_5%@ R142 10K_0402_5%@R142 10K_0402_5%@

+HDMI_5V_OUT

2

1

+5VL

1

C187

2

DVT- Change U4.19 from HDMI_HPD to HDMI_HPD_R

1

C273

12

HDMI_HPD_R

1 2 1 2 1 2 1 2

C273 IHDMI@

IHDMI@

2

0.1U_0402_16V4Z

HDMI_SCLK HDMI_SDATA

12

R369

HDMI@R369

HDMI@

2.2K_0402_5%

2.2K_0402_5% HDMI_HPD_R

PCIE_MTX_C_GRX_N3 <10,17> PCIE_MTX_C_GRX_P3 <10,17>

PCIE_MTX_C_GRX_N2 <10,17> PCIE_MTX_C_GRX_P2 <10,17>

PCIE_MTX_C_GRX_N1 <10,17> PCIE_MTX_C_GRX_P1 <10,17>

PCIE_MTX_C_GRX_N0 <10,17> PCIE_MTX_C_GRX_P0 <10,17>

C272

C272 IHDMI@

IHDMI@

@R243

@

HDMI detece level shift for GPU.

1

5

U9

P

4

OE#

A2Y

G

74AHCT1G125GW_SOT353-5

3

EVT2- Add HDP to EC

+5VL

C232

C232 @

@

1U_0402_6.3V4Z

10K_0402_5%

HDMI_CECIN

HDMI_CECOUT

+5VL

CEC@

2008/10/1 2009/10/1

3

0.1U_0402_16V4Z

1

2

12

HDMI_HPD_R

1

2

R1001

R1001 CEC@

CEC@

1

C275

C274

C274 IHDMI@

IHDMI@

DVT2-Set R139/R140 as @ to follow PARADE design. PVT-R139/R142 change to 10K Ohm.

100K_0402_5%

HDMI_CECIN

Compal Secret Data

C275 IHDMI@

IHDMI@

2

HDMI_SCLK HDMI_SDATA

+3VS

+3VS+3VS

EVT2- Add HDP to EC DVT-Set D16 as HDMI@

21

D16

HDMI@D16

HDMI@

CH751H-40PT_SOD323-2

HDMI_HPD

2

R261

HDMI@

+5VL

12

R1002

R1002 27K_0402_5%

27K_0402_5% CEC@

CEC@

1

0.1U_0402_16V4Z

1 2

U61

5

Vcc

4

Y

TC7SET14FU_SOT353-5

2

G

CEC@

Q29

1 3

D

2N7002_SOT23-3

12

CEC_RST#

2

G691L308T72UF_SOT23-3

Deciphered Date

VGA_DVI_SCLK<17>

VGA_DVI_SDATA<17>

R48 0_0402_5%HDMI@R48 0_0402_5%HDMI@ R50 0_0402_5%HDMI@R50 0_0402_5%HDMI@

R260

HDMI@R260

HDMI@

2.2K_0402_5%

C280

C280 HDMI@

HDMI@

@U61

@

1

NC

2

A

3

GND

R1005 27K_0402_5%

R1005 27K_0402_5% CEC@

CEC@

2N7002_SOT23-3

S

U60

@U60

@

VCC

RESET#

GND

12

+3VS+5VL

VGA_HPD

HDMI_CEC

12

CH751H-40PT_SOD323-2

D

S

D

S

13

Q31

Q31 CEC@

CEC@

G

2

1 2

R1003

R1003 100K_0402_5%

100K_0402_5% CEC@

CEC@

+5VL

3

1

2

1

2

4.7K_0402_5%

VGA_DVI_SCLK

VGA_DVI_SDATA

VGA_DVI_TXC-<17>

VGA_HDMI_SCLK VGA_HDMI_SDATA

VGA_DVI_TXC+<17>

VGA_DVI_TXD0-<17>

VGA_HPD <17>HDMI_HPD_R<32>

VGA_DVI_TXD0+<17>

VGA_DVI_TXD1-<17>

VGA_DVI_TXD1+<17>

VGA_DVI_TXD2-<17>

VGA_DVI_TXD2+<17>

D15

CEC@D15

CEC@

21

HDMI_CEC

C486

C486 @

@

0.1U_0402_16V4Z

1

+3VS +HDMI_5V_OUT+3VS

12

R238

+3VL

R238 PM@

PM@

R239

4.7K_0402_5%

4.7K_0402_5% PM@

PM@

Q10

Q10 PM@

PM@

VGA_DVI_TXC- HDMI_R_CK-

VGA_DVI_TXC+

VGA_DVI_TXD0-

VGA_DVI_TXD0+

VGA_DVI_TXD1-

VGA_DVI_TXD1+

VGA_DVI_TXD2-

VGA_DVI_TXD2+

DVT- Update F2 (SP04301P000) symbol for Layout. Add D18 for +5VL Add R1036 to change D9.

1 2

R1036 0_0805_5%

0_0805_5%

2 1

+5VL

D9 RB491D_SC59-3HDMI@ D9 RB491D_SC59-3HDMI@

2 1

+5VS

D18 RB491D_SC59-3HDMI@ D18 RB491D_SC59-3HDMI@

Q32

Q32 PM@

PM@

2 3

SGD

1

2 3

SGD

@R1036

@

1

BSH111_SOT23-3

1

L11

4

1

L12

4

R252 0_0402_5%

1

L13

4

R254 0_0402_5%

R256 0_0402_5%

1

L14

4

R259 0_0402_5%

HDMI Connector

+HDMI_5V_OUT

DVT2- JP9, change to Dip type connector.

Title

Size Document Number Rev

Custom

Date: Sheet

HDMI_HPD

HDMI_SDATA HDMI_SCLK

HDMI_CEC HDMI_R_CK-

HDMI_R_CK+

HDMI_R_D0-

HDMI_R_D0+

HDMI_R_D1-

HDMI_R_D1+

HDMI_R_D2-

HDMI_R_D2+

Compal Electronics, Inc.

SCHEMATICS,M/B A4161

401562

12

R240

4.7K_0402_5%

4.7K_0402_5% HDMI@

HDMI@

BSH111_SOT23-3

1 2

R246 0_0402_5%

@

1

4

1 2

R248 0_0402_5%

1 2

R250 0_0402_5%

1

4

1 2

R251 0_0402_5%

1 2

1

4

1 2

1

4

1 2

+5VS_HDMI

1.1A_6V_MINISMDC110F-2

2

3

OCE2012120YZF_0805HDMI@

@

2

3

OCE2012120YZF_0805HDMI@

@

2

3

OCE2012120YZF_0805HDMI@

@

2

3

OCE2012120YZF_0805HDMI@

@

F2

2 1

19 18 17 16 15 14 13 12 11 10

9 8 7 6 5 4 3 2 1

TAITW_PDVBR5-19FLBS4NN4N

1

12

R241

4.7K_0402_5%

4.7K_0402_5% HDMI@

HDMI@

VGA_HDMI_SCLK

VGA_HDMI_SDATA

2

3

2

3

2

3

2

3

HDMI@F2

HDMI@

JP9

HP_DET +5V DDC/CEC_GND SDA SCL Reserved CEC CKCK_shield CK+ D0D0_shield D0+ D1D1_shield D1+ D2D2_shield D2+

HDMI_R_CK+

HDMI_R_D0-

HDMI_R_D0+

HDMI_R_D1-

HDMI_R_D1+

HDMI_R_D2-

HDMI_R_D2+

+HDMI_5V_OUT

1

C282

C282 HDMI@

HDMI@

0.1U_0402_16V4Z

2

@JP9

@

GND GND GND GND

of

19 48Monday, February 23, 2009

of

19 48Monday, February 23, 2009

of

19 48Monday, February 23, 2009

20 21 22 23

G

5

4

3

2

1

U10B

PCI_AD[0..31]<30>

D D

+3VS

R275 8.2K_0402_5%R275 8.2K_0402_5%

1 2

R277 8.2K_0402_5%R277 8.2K_0402_5%

1 2

R279 8.2K_0402_5%R279 8.2K_0402_5%

C C

B B

A A

1 2

R281 8.2K_0402_5%R281 8.2K_0402_5%

1 2

DVT-Remove USB_OC#3 and short USB_OC#0 and USB_OC#3 for USB protect.

PVT-Remove ICH ROM Part, becasue HDCP code build in EC system ROM part.

PCI_PIRQA# PCI_PIRQB# PCI_PIRQC# PCI_PIRQD#

For Express Card

For Robson/ HDDVD

For LAN

For WLAN

For TMA

For CardReader

5

PCIE_IRX_C_NEWTX_N1<26> PCIE_IRX_C_NEWTX_P1<26> PCIE_ITX_C_NEWRX_N1<26> PCIE_ITX_C_NEWRX_P1<26>

PCIE_IRX_C_NANDTX_N2<27> PCIE_IRX_C_NANDTX_P2<27>

PCIE_ITX_C_NANDRX_N2<27> PCIE_ITX_C_NANDRX_P2<27>

PCIE_IRX_C_LANTX_N3<28> PCIE_IRX_C_LANTX_P3<28> PCIE_ITX_C_LANRX_N3<28> PCIE_ITX_C_LANRX_P3<28>

PCIE_IRX_C_WLANTX_N4<26> PCIE_IRX_C_WLANTX_P4<26> PCIE_ITX_C_WLANRX_N4<26> PCIE_ITX_C_WLANRX_P4<26>

PCIE_IRX_C_TMATX_N5<27> PCIE_IRX_C_TMATX_P5<27> PCIE_ITX_C_TMARX_N5<27> PCIE_ITX_C_TMARX_P5<27>

PCIE_IRX_C_5IN1TX_N6<29> PCIE_IRX_C_5IN1TX_P6<29>

PCIE_ITX_C_5IN1RX_N6<29> PCIE_ITX_C_5IN1RX_P6<29>

+3V_SB

C284 0.1U_0402_16V7KNEW@C284 0.1U_0402_16V7KNEW@ C286 0.1U_0402_16V7KNEW@C286 0.1U_0402_16V7KNEW@

C292 0.1U_0402_16V7KSLOT2@C292 0.1U_0402_16V7KSLOT2@ C293 0.1U_0402_16V7KSLOT2@C293 0.1U_0402_16V7KSLOT2@

C289 0.1U_0402_16V7KC289 0.1U_0402_16V7K C285 0.1U_0402_16V7KC285 0.1U_0402_16V7K

C290 0.1U_0402_16V7KSLOT1@C290 0.1U_0402_16V7KSLOT1@ C291 0.1U_0402_16V7KSLOT1@C291 0.1U_0402_16V7KSLOT1@

C287 0.1U_0402_16V7KTMA@C287 0.1U_0402_16V7KTMA@ C288 0.1U_0402_16V7KTMA@C288 0.1U_0402_16V7KTMA@

C294 0.1U_0402_16V7KC294 0.1U_0402_16V7K C295 0.1U_0402_16V7KC295 0.1U_0402_16V7K

RP15

USB_OC#4

45

USB_OC#6

36 27

USB_OC#10

18

10K_0804_8P4R_5%

RP16

USB_OC#1

45

USB_OC#0

36

USB_OC#8

27

USB_OC#2

18

10K_0804_8P4R_5%

RP17

USB_OC#9

45

USB_OC#5

36

USB_OC#11

27 18

10K_0804_8P4R_5%

PCI_AD0 PCI_AD1 PCI_AD2 PCI_AD3 PCI_AD4 PCI_AD5 PCI_AD6 PCI_AD7 PCI_AD8 PCI_AD9 PCI_AD10 PCI_AD11 PCI_AD12 PCI_AD13 PCI_AD14 PCI_AD15 PCI_AD16 PCI_AD17 PCI_AD18 PCI_AD19 PCI_AD20 PCI_AD21 PCI_AD22 PCI_AD23 PCI_AD24 PCI_AD25 PCI_AD26 PCI_AD27 PCI_AD28 PCI_AD29 PCI_AD30 PCI_AD31

PCI_PIRQA#

PCI_PIRQB# PCI_PIRQC# PCI_PIRQD#

12 12

4

U10B

D11

AD0

C8

AD1

D9

AD2

E12

AD3

E9

AD4

C9

AD5

E10

AD6

B7

AD7

C7

AD8

C5

AD9

G11

AD10

F8

AD11

F11

AD12

E7

AD13

A3

AD14

D2

AD15

F10

AD16

D5

AD17

D10

AD18

B3

AD19

F7

AD20

C3

AD21

F3

AD22

F4

AD23

C1

AD24

G7

AD25

H7

AD26

D1

AD27

G5

AD28

H6

AD29

G1

AD30

H3

AD31

J5

PIRQA#

E1

PIRQB#

J6

PIRQC#

C4

PIRQD#

ICH9-M ES_FCBGA676

ICH9-M ES_FCBGA676 SBR3@

SBR3@

SPI_CS#1<22>

ICH_R_SPI_MOSI<22>

USB_OC#0<25> USB_OC#1<25> USB_OC#2<29>

EXP_CPPE#<26>

Within 500 mils

PCI

REQ0#

GNT0# REQ1#/GPIO50 GNT1#/GPIO51 REQ2#/GPIO52 GNT2#/GPIO53 REQ3#/GPIO54 GNT3#/GPIO55

C/BE0# C/BE1# C/BE2# C/BE3#

IRDY#

PAR PCIRST# DEVSEL#

PERR#

PLOCK#

SERR#

STOP# TRDY#

FRAME#

PLTRST#

PCICLK

PME#

F1 G4 B6 A7 F13 F12 E6 F6

D8 B4 D6 A5

D3 E3 R1 C6 E4 C2 J4 A4 F5 D7

C14 D4 R2

PCI_REQ#0 PCI_REQ#1 PCI_REQ#2 PCI_REQ#3

PCI_IRDY#

PCI_DEVSEL# PCI_PERR# PCI_PLOCK# PCI_SERR# PCI_STOP# PCI_TRDY#

PCI_FRAME#

CLK_PCI_ICH

PCI_GNT#0 <22> PCI_REQ#1 <30> PCI_GNT#1 <30> PCI_REQ#2 <30> PCI_GNT#2 <30>

STRAP_A16 <22> PCI_CBE#0 <30>

PCI_CBE#1 <30> PCI_CBE#2 <30> PCI_CBE#3 <30>

PCI_IRDY# <30> PCI_PAR <30> PCI_RST# <30> PCI_DEVSEL# <30> PCI_PERR# <30>

PCI_SERR# <30> PCI_STOP# <30> PCI_TRDY# <30> PCI_FRAME# <30>

PLT_RST# <8,17,26..29,32,33> CLK_PCI_ICH <16>

PCI_REQ#0 PCI_REQ#1 PCI_REQ#2 PCI_REQ#3

PCI_IRDY#

PCI_DEVSEL#

PCI_PERR#

PCI_PLOCK#

PCI_SERR#

PCI_STOP#

PCI_TRDY#

PCI_FRAME#

CLK_PCI_ICH

PVT-Modify EC_BD0/EC_BD1 to EC_BD0#/EC_BD1#

Interrupt I/F

1 2

R290

22.6_0402_1%

PIRQE#/GPIO2

PIRQF#/GPIO3 PIRQG#/GPIO4 PIRQH#/GPIO5

PCIE_ITX_NEWRX_N1 PCIE_ITX_NEWRX_P1

PCIE_ITX_NANDRX_N2 PCIE_ITX_NANDRX_P2

PCIE_ITX_LANRX_N3 PCIE_ITX_LANRX_P3

PCIE_ITX_WLANRX_N4 PCIE_ITX_WLANRX_P4

PCIE_ITX_TMARX_N5 PCIE_ITX_TMARX_P5

PCIE_ITX_5IN1RX_N6 PCIE_ITX_5IN1RX_P6

USB_OC#0 USB_OC#1 USB_OC#2 USB_OC#0 USB_OC#4 USB_OC#5 USB_OC#6

USB_OC#8 USB_OC#9 USB_OC#10 USB_OC#11

USBBIAS

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

PCI_PIRQE#

H4

PCI_PIRQF#

K6

PCI_PIRQG#

F2

PCI_PIRQH#

G2

U10D

N29

PERN1

N28

PERP1

P27

PETN1

P26

PETP1

L29

PERN2

L28

PERP2

M27

PETN2

M26

PETP2

J29

PERN3

J28

PERP3

K27

PETN3

K26

PETP3

G29

PERN4

G28

PERP4

H27

PETN4

H26

PETP4

E29

PERN5

E28

PERP5

F27

PETN5

F26

PETP5

C29

PERN6/GLAN_RXN

C28

PERP6/GLAN_RXP

D27

PETN6/GLAN_TXN

D26

PETP6/GLAN_TXP

D23

SPI_CLK

D24

SPI_CS0#

F23

SPI_CS1#GPIO58/CLGPIO6

D25

SPI_MOSI

E23

SPI_MISO

N4

OC0#/GPIO59

N5

OC1#/GPIO40

N6

OC2#/GPIO41

P6

OC3#/GPIO42

M1

OC4#/GPIO43

N2

OC5#/GPIO29

M4

OC6#/GPIO30

M3

OC7#/GPIO31

N3

OC8#/GPIO44

N1

OC9#/GPIO45

P5

OC10#/GPIO46

P3

OC11#/GPIO47

AG2

USBRBIAS

AG1

USBRBIAS#

ICH9-M ES_FCBGA676

ICH9-M ES_FCBGA676 SBR3@

SBR3@

3

SPI

USB

2008/10/1 2009/10/1

EC_BD0# <31> EC_BD1# <31> PCI_PIRQG# <30> PCI_PIRQH# <30>

V27

DMI0RXN

V26

DMI0RXP

U29

DMI0TXN

U28

DMI0TXP

Y27

DMI1RXN

Y26

DMI1RXP

W29

DMI1TXN

W28

DMI1TXP

AB27

DMI2RXN

AB26

DMI2RXP

AA29

DMI2TXN

AA28

DMI2TXP

AD27

DMI3RXN

AD26

DMI3RXP

AC29

DMI3TXN

AC28

DMI3TXP

T26

DMI_CLKN

T25

DMI_CLKP

PCI - Express

DMI_ZCOMP

Direct Media Interface

DMI_IRCOMP

Compal Secret Data

USBP0N

USBP0P

USBP1N

USBP1P

USBP2N

USBP2P

USBP3N

USBP3P

USBP4N

USBP4P

USBP5N

USBP5P

USBP6N

USBP6P

USBP7N

USBP7P

USBP8N

USBP8P

USBP9N

USBP9P USBP10N USBP10P USBP11N USBP11P

Deciphered Date

AF29 AF28

AC5 AC4 AD3 AD2 AC1 AC2 AA5 AA4 AB2 AB3 AA1 AA2 W5 W4 Y3 Y2 W1 W2 V2 V3 U5 U4 U1 U2

PCI_PIRQE# PCI_PIRQF# PCI_PIRQG# PCI_PIRQH#

Within 500 mils

DMI_IRCOMP

1 2

R283 24.9_0402_1%R283 24.9_0402_1%

EVT2- Remove USB20_N10/P10 for FM tuner change NXP, I2C solution.

R262 8.2K_0402_5%R262 8.2K_0402_5% R263 8.2K_0402_5%R263 8.2K_0402_5% R264 8.2K_0402_5%R264 8.2K_0402_5% R265 8.2K_0402_5%R265 8.2K_0402_5% R266 8.2K_0402_5%R266 8.2K_0402_5% R267 8.2K_0402_5%R267 8.2K_0402_5% R268 8.2K_0402_5%R268 8.2K_0402_5% R269 8.2K_0402_5%R269 8.2K_0402_5% R270 8.2K_0402_5%R270 8.2K_0402_5% R271 8.2K_0402_5%R271 8.2K_0402_5% R272 8.2K_0402_5%R272 8.2K_0402_5% R273 8.2K_0402_5%R273 8.2K_0402_5%

R276 8.2K_0402_5%R276 8.2K_0402_5% R278 8.2K_0402_5%R278 8.2K_0402_5% R280 8.2K_0402_5%R280 8.2K_0402_5% R282 8.2K_0402_5%R282 8.2K_0402_5%

DMI_MTX_IRX_N0 <8> DMI_MTX_IRX_P0 <8> DMI_ITX_MRX_N0 <8> DMI_ITX_MRX_P0 <8>

DMI_MTX_IRX_N1 <8> DMI_MTX_IRX_P1 <8> DMI_ITX_MRX_N1 <8> DMI_ITX_MRX_P1 <8>

DMI_MTX_IRX_N2 <8> DMI_MTX_IRX_P2 <8> DMI_ITX_MRX_N2 <8> DMI_ITX_MRX_P2 <8>

DMI_MTX_IRX_N3 <8> DMI_MTX_IRX_P3 <8> DMI_ITX_MRX_N3 <8> DMI_ITX_MRX_P3 <8>

CLK_PCIE_ICH# <16> CLK_PCIE_ICH <16>

USB20_N0 <25> USB20_P0 <25> USB20_N1 <25> USB20_P1 <25> USB20_N2 <29> USB20_P2 <29> USB20_N3 <24> USB20_P3 <24> USB20_N4 <25> USB20_P4 <25> USB20_N5 <25> USB20_P5 <25> USB20_N6 <26> USB20_P6 <26> USB20_N7 <26> USB20_P7 <26> USB20_N8 <26> USB20_P8 <26> USB20_N9 <25> USB20_P9 <25>

USB20_N11 <25> USB20_P11 <25>

2

R274

10_0402_5%@

12 12 12 12 12 12 12 12 12 12 12 12

12

1 2

12 12 12 12

+1.5VS

USB-Rare USB-Right USB-Left eSATA-USB FP BT UWB/ TV Tuner WiMax(WLAN) ExpressCard Felica

Int. Camera

+3VS

C283

10P_0402_50V8J@

+3VS

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

SCHEMATICS,M/B A4161

401562 G

1

of

20 48Monday, February 23, 2009

of

20 48Monday, February 23, 2009

of

20 48Monday, February 23, 2009

5

18P_0402_50V8J

1

+RTCVCC

1

C297

0.1U_0402_16V4Z

D D

0.1U_0402_16V4Z

2

3

+RTCBATT

D10

D10 BAS40-04_SOT23-3

BAS40-04_SOT23-3

+CHGRTC

32.768KHZ_12.5PF_1TJS125BJ4A421P

CMOS Setting, near DDR Door

R292

+RTCVCC

1 2

20K_0402_5%

iME Setting.

R296

1 2

20K_0402_5%

R298

1 2

1M_0402_5%

AZ_BITCLK_MD<29> AZ_BITCLK_MCH<8> AZ_BITCLK_VGA<17>

AZ_SYNC_HD<29>

AZ_SYNC_MD<29> AZ_SYNC_MCH<8> AZ_SYNC_VGA<17>

C C

AZ_RST_HD#<29>

AZ_RST_MD#<29>

AZ_RST_MCH#<8>

AZ_RST_VGA#<17>

AZ_SDOUT_HD<29>

AZ_SDOUT_MD<29> AZ_SDOUT_MCH<8> AZ_SDOUT_VGA<17>

R304 33_0402_5%MDC@R304 33_0402_5%MDC@ R305 33_0402_5%IHDMI@R305 33_0402_5%IHDMI@ R637 33_0402_5%PM@R637 33_0402_5%PM@

R306 33_0402_5%R306 33_0402_5% R307 33_0402_5%MDC@R307 33_0402_5%MDC@ R308 33_0402_5%IHDMI@R308 33_0402_5%IHDMI@ R638 33_0402_5%PM@R638 33_0402_5%PM@

R310 33_0402_5%R310 33_0402_5%

R311 33_0402_5%MDC@R311 33_0402_5%MDC@ R312 33_0402_5%IHDMI@R312 33_0402_5%IHDMI@ R639 33_0402_5%PM@R639 33_0402_5%PM@

R313 33_0402_5%R313 33_0402_5% R314 33_0402_5%MDC@R314 33_0402_5%MDC@ R315 33_0402_5%IHDMI@R315 33_0402_5%IHDMI@ R640 33_0402_5%PM@R640 33_0402_5%PM@

+3VS

ICH_RTCRST#

ICH_SRTCRST#

SM_INTRUDER#

1 2 1 2 1 2

1 2 1 2 1 2 1 2

R316 10K_0402_5%R316 10K_0402_5%

1 2

SHORT PADS

C299

1U_0402_6.3V4Z

SHORT PADS

C300

1U_0402_6.3V4Z

SATA_LED#

1 2 1 2

AZ_BITCLK

AZ_SYNC

AZ_RST#

AZ_SDOUT

18P_0402_50V8J

Y4

3 2

J1

J2

1ST HDD

2ND HDD

B B

+SSC_VDD

R1038

R1039

12

0_0603_5%NIHDMI@

12

0_0603_5%IHDMI@

+3VS

+1.5VS

AZ_BITCLK_HD<29>

C778

0.1U_0402_16V4Z

1M_0402_5%

4

C296

12

4

OUT

NC NC

1

IN

12

C298 18P_0402_50V8JC298 18P_0402_50V8J

ICH_INTVRMEN<22>

LAN100_SLP<22>

1 2

R54 100K_0402_5%

TV@

REC_LED<34>

R300

1 2

+1.5VS

24.9_0402_1%

AZ_SDIN0_HD<29>

AZ_SDIN1_MD<29> AZ_SDIN2_MCH<8> AZ_SDIN3_VGA<17>

AZ_SDOUT<22>

SATA_LED#<34>

SATA_IRX_C_DTX_N0<24> SATA_IRX_C_DTX_P0<24>

SATA_ITX_DRX_N0<24> SATA_ITX_DRX_P0<24>

SATA_IRX_C_DTX_N1<24> SATA_IRX_C_DTX_P1<24>

SATA_ITX_DRX_N1<24> SATA_ITX_DRX_P1<24>

1 2

R322

33_0402_5%

R386

R386 @

@

1 2

R386

NIHDMI@R386

NIHDMI@

1.5M_0402_5%

12

R291

10M_0402_5%

ICH_RTCX1 ICH_RTCX2

ICH_RTCRST# ICH_SRTCRST# SM_INTRUDER#

AZ_BITCLK AZ_SYNC

AZ_RST#

AZ_SDOUT

SATA_LED#

R302

MBK1005470YZF_0402

8

VDD SSEXTR7PD#/OE

6

DLY_CTRL

5

ModOUT

PCS3P73Z11BXG-08-CR_TDFN8_2X2

C777

@C777

@

0.1U_0402_16V4Z

EMI

DVT-Change to SSC solution for EMI. DVT2-Change demping resistor to add R322 for EMI PVT-Change SSC to PCS3P73Z11BXG-08CR, Add R357/R386/R1038/R1039 and add SSC@ and NSSC@

U10A

C23

RTCX1

C24

RTCX2

A25

RTCRST#

F20

SRTCRST#

C22

INTRUDER#

B22

INTVRMEN

A22

LAN100_SLP

E25

GLAN_CLK

C13

LAN_RSTSYNC

F14

LAN_RXD0

G13

LAN_RXD1

D14

LAN_RXD2

D13

LAN_TXD_0

D12

LAN_TXD_1

E13

LAN_TXD_2

B10

GPIO56

B28

GLAN_COMPI

B27

GLAN_COMPO

AF6

HDA_BIT_CLK

AH4

HDA_SYNC

AE7

HDA_RST#

AF4

HDA_SDIN0

AG4

HDA_SDIN1

AH3

HDA_SDIN2

AE5

HDA_SDIN3

AG5

HDA_SDOUT

AG7

HDA_DOCK_EN#/GPIO33

AE8

HDA_DOCK_RST#/GPIO34

AG8

SATALED#

AJ16

SATA0RXN

AH16

SATA0RXP

AF17

SATA0TXN

AG17

SATA0TXP

AH13

SATA1RXN

AJ13

SATA1RXP

AG14

SATA1TXN

AF14

SATA1TXP

ICH9-M ES_FCBGA676

ICH9-M ES_FCBGA676 SBR3@

SBR3@

1 2

IHDMI@R302

IHDMI@

U5

CLKIN

FS

GND

NIHDMI@

1 2

10K_0402_5%

3 4

AZ_BITCLK

R357

3

12

RTC

LPCCPU

LAN / GLAN

IHDA

SATA

@ R354

@

10K_0402_5%

+SSC_VDD

10K_0402_5%

FWH0/LAD0 FWH1/LAD1 FWH2/LAD2 FWH3/LAD3

FWH4/LFRAME#

LDRQ0#

LDRQ1#/GPIO23

A20GATE

A20M#

DPRSTP#

DPSLP#

FERR#

CPUPWRGD

IGNNE#

INIT#

INTR

RCIN#

NMI

SMI#

STPCLK#

THRMTRIP#

TP12

SATA4RXN

SATA4RXP SATA4TXN SATA4TXP

SATA5RXN

SATA5RXP SATA5TXN SATA5TXP

SATA_CLKN SATA_CLKP

SATARBIAS#

SATARBIAS

+SSC_VDD

R354

1 2

R355

1 2

K5 K4 L6 K2

K3 J3

J1 N7

AJ27 AJ25

AE23 AJ26 AD22 AF25 AE22

AG25 L3

AF23 AF24

AH27

THRMTRIP_ICH#

AG26 AG27

AH11 AJ11 AG12 AF12

AH9 AJ9 AE10 AF10

AH18 AJ18 AJ7 AH7

2

EC_GA20

R297 49.9_0402_1%R297 49.9_0402_1%

1 2

EC_KBRST#GLAN_COMP

1 2

R309 49.9_0402_1%R309 49.9_0402_1%

TP12

SATARBIAS

24.9_0402_1%

R317

PADT5PAD

10mils width less than 500mils

1 2

LPC_AD0 <32,33> LPC_AD1 <32,33> LPC_AD2 <32,33> LPC_AD3 <32,33>

LPC_FRAME# <32,33>

FELICA_PWR <25> EC_GA20 <32>

H_A20M# <4> H_DPRSTP# <5,8,42>

H_DPSLP# <5>

H_PWRGOOD <4,5> H_IGNNE# <4> H_INIT# <4>

H_INTR <4> EC_KBRST# <32>

H_NMI <4> H_SMI# <4>

H_STPCLK# <4>

T5

SATA_IRX_C_DTX_N4 <24>

SATA_IRX_C_DTX_P4 <24> SATA_ITX_DRX_N4 <24> SATA_ITX_DRX_P4 <24>

SATA_IRX_C_DTX_N5 <24>

SATA_IRX_C_DTX_P5 <24> SATA_ITX_DRX_N5 <24> SATA_ITX_DRX_P5 <24>

CLK_PCIE_SATA# <16>

CLK_PCIE_SATA <16>

H_FERR#FERR#

H_THERMTRIP#

EC_GA20 H_DPRSTP# H_FERR#

EC_KBRST#

H_FERR# <4>

+1.05VS

49.9_0402_1%

H_THERMTRIP#

H_THERMTRIP# <4,8>

SATA ODD

eSATA

R293 10K_0402_5%@R293 10K_0402_5%@ R294 56_0402_5%@R294 56_0402_5%@ R295 49.9_0402_1%R295 49.9_0402_1%

R299

R303

10K_0402_5%@

12

2

3

1

12 12 12

12

R301

R301 330_0402_5%

330_0402_5% @

@

Q12 2SC2411KT146_SOT23-3@

CBE

1

2

3

+3VS +1.05VS

+3VS

D46

@D46

@

DAN202UT106_SC70-3

ENTRIP1 <37,39> ENTRIP2 <37,39>

A A

Security Classification

2008/10/1 2009/10/1

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2008/10/1 2009/10/1

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

SCHEMATICS,M/B A4161

401562 G

21 48Monday, February 23, 2009

1

of

5

4

3

2

1

+3VS

PM_SMBDATA<14..16,26>

PM_SMBCLK<14..16,26>

D D

+3V_SB

C C

R325 10K_0402_5%R325 10K_0402_5%

1 2

R328 10K_0402_5%R328 10K_0402_5%

1 2

R330 10K_0402_5%R330 10K_0402_5%

1 2

R326 10K_0402_5%R326 10K_0402_5%

1 2

R332 10K_0402_5%R332 10K_0402_5%

1 2

Place close to JITP within 1ns = 5000 mil

R333 10K_0402_5%R333 10K_0402_5%

1 2

R335 8.2K_0402_5%R335 8.2K_0402_5%

+3VS

+3V_SB

+3VS

DMI Termination Voltage

GPIO49

1 2 1 2

R338 1K_0402_5%R338 1K_0402_5%

R340 10K_0402_5%R340 10K_0402_5%

1 2

R341 8.2K_0402_5%@R341 8.2K_0402_5%@

1 2

R343 10K_0402_5%R343 10K_0402_5%

1 2

DVT- R346 change to 332K for leakage issue.

1 2

R346 332K_0402_1%R346 332K_0402_1%

ACIN<17,32,34,36,38>

R348 8.2K_0402_5%R348 8.2K_0402_5%

1 2

R349 10K_0402_5%R349 10K_0402_5%

1 2

R350 100K_0402_5%R350 100K_0402_5%

1 2 1 2

R351 1K_0402_5%2HDD@R351 1K_0402_5%2HDD@

R353 8.2K_0402_5%R353 8.2K_0402_5%

1 2

R356 100K_0402_5%R356 100K_0402_5%

1 2

Low= Desktop used High= Mobile* (Internal pull-up)

R3194.7K_0402_5% R3194.7K_0402_5%

R3214.7K_0402_5% R3214.7K_0402_5%

2N7002DW-T/R7_SOT363-6

D11 CH751H-40PT_SOD323-2D11 CH751H-40PT_SOD323-2

4

LINKALERT#

ME_EC_CLK1

ME_EC_DATA1 XDP_DBRESET#

EC_LID_OUT#

PM_CLKRUN#

EC_SWI#

EC_THERM#

ICH_ACIN

21

2HDD_DET#

5

Q13B

2N7002DW-T/R7_SOT363-6

ICH_RI#

SERIRQ

OCP#

EC_SMI#

EC_SCI#

BT_DET#

CIR_EN#

3

THRM# not used, 8.2K to 10K PU to +3VS.

EVT2- New add FM_I2CDAT and I2CINT on GPIO27/28.

iTPM Physical Presence

CLGPIO5 Mobil Platform

GPIO57

B B

Assert = iTPM Physical Presence Enable De-assert = iTPM disable **Only used in iAMT w/ME Firmware Desktop Platform used only

ICH9M Strap Pin

1 2

+3VS

R363 1K_0402_5%@R363 1K_0402_5%@

1 2

R366 1K_0402_5%@R366 1K_0402_5%@

1 2

R368 1K_0402_5%@R368 1K_0402_5%@

ICH_R_SPI_MOSI <20>

PCI_GNT#0 <20>

SPI_CS#1 <20>

R318 4.7K_0402_5%R318 4.7K_0402_5%

1 2

R320 4.7K_0402_5%R320 4.7K_0402_5%

1 2

Q13A

ICH_SMBDATA

ICH_SMBCLK

61

XDP_DBRESET#<4>

PM_SYNC#<8>

EC_LID_OUT#<32>

H_STP_PCI#<16> H_STP_CPU#<16>

EC_SWI#<26,32>

SERIRQ<32>

EC_THERM#<32>

VGATE<8,32,42>

PADT6PAD

T6

OCP#<4>

FM_I2CCLK<25>

EC_SMI#<32> EC_SCI#<32>

CAM_PWR<25>

FELICA_PWR_R<25>

BT_DET#<25>

FM_I2CDAT<25>

FM_I2CINT#<25>

CLKREQ_SATA#<16>

CIR_EN#<34>

SB_SPKR<29>

MCH_ICH_SYNC#<8>

T7 T8 T9

High= iTPM enable by MCH strap

ICH_SMBCLK ICH_SMBDATA LINKALERT# ME_EC_CLK1 ME_EC_DATA1

ICH_RI#

XDP_DBRESET#

EC_LID_OUT#

PM_CLKRUN# EC_SWI#

SERIRQ EC_THERM#

VGATE

TP11

OCP# ICH_ACIN

EC_SMI# EC_SCI#

2HDD_DET# BT_DET#

CIR_EN#

1 2

R367 10K_0402_5%R367 10K_0402_5%

SB_SPKR ICH_TP3

PADT7PAD PADT8PAD PADT9PAD

2

EVT2- New add FM_I2CCLK on GPIO24.

Internal TPM Strap SPI_MOSI Low= Disable*

Boot BIOS Strap PCI_GNT#0 SPI_CS#1 Boot BIOS Loaction

0

1

0

1

SPI PCI

LPC*

(Default)

TP8 TP9 TP10

+3V_SB

GPIO57

U10C

G16

SMBCLK

A13

SMBDATA

E17

LINKALERT#/GPIO60/CLGPIO4

C17

SMLINK0

B18

SMLINK1

F19

RI#

R4

SUS_STAT#/LPCPD#

G19

SYS_RESET#

M6

PMSYNC#/GPIO0

A17

SMBALERT#/GPIO11

A14

STP_PCI#

E19

STP_CPU#

L4

CLKRUN#

E20

WAKE#

M5

SERIRQ

AJ23

THRM#

D21

VRMPWRGD

A20

TP11

AG19

GPIO1

AH21

GPIO6

AG21

GPIO7

A21

GPIO8

C12

GPIO12

C21

GPIO13

AE18

GPIO17

K1

GPIO18

AF8

GPIO20

AJ22

SCLOCK/GPIO22

A9

GPIO27

D19

GPIO28

L1

SATACLKREQ#/GPIO35

AE19

SLOAD/GPIO38

AG22

SDATAOUT0/GPIO39

AF21

SDATAOUT1/GPIO48

AH24

GPIO49

A8

GPIO57/CLGPIO5

M7

SPKR

AJ24

MCH_SYNC#

B21

TP3

AH20

TP8

AJ20

TP9

AJ21

TP10

ICH9-M ES_FCBGA676

ICH9-M ES_FCBGA676 SBR3@

SBR3@

+RTCVCC

1 2

R364 330K_0402_5%R364 330K_0402_5%

1 2

R365 0_0402_5%@R365 0_0402_5%@

SMB

SATA0GP/GPIO21 SATA1GP/GPIO19 SATA4GP/GPIO36 SATA5GP/GPIO37

SATA

GPIO

SATA

GPIO

clocks

SYS / GPIOGPIOMISC

Power MGT

GPIO10/SUS_PWR_ACK

GPIO14/AC_PRESENT

Controller Link

CLK14 CLK48

SUSCLK

SLP_S3# SLP_S4# SLP_S5#

S4_STATE#/GPIO26

PWROK

DPRSLPVR/GPIO16

BATLOW# PWRBTN#

LAN_RST#

RSMRST#

CK_PWRGD

CLPWROK

SLP_M#

CL_CLK0 CL_CLK1

CL_DATA0 CL_DATA1

CL_VREF0 CL_VREF1

CL_RST0# CL_RST1#

MEM_LED/GPIO24

WOL_EN/GPIO9

ICH_INTVRMEN <21> LAN100_SLP <21>

EVT2- Remove R322/R323/R324/R327 and set these four signal as GPIOs. DVT- Change BT_PWR and BT_RST# from EC to SB.

Default: De-POP PU/PD Resistors, BIOS set GPIO

SPK_SEL

AH23

SUBWOOFER

AF19 AE21 AD20

CLK_14M_ICH

H1

CLK_48M_ICH

AF3 P1 C16

E16 G17

S4_STATE#

C10

PM_PWROK

G20 M2

ICH_LOW_BAT#

B13 R3

1 2

D20

R344 0_0402_5%R344 0_0402_5%

SB_RSMRST#

D22 R5

PM_PWROK

R6 B16 F24

B19 F22

C19

+ICH9_CLVREF

C25 A19

F21 D18

EVT2- SB_INT_FLASH_SEL# chage to GPIO24.

A16

SUS_PWR_ACK

C18 C11 C20

SUS_PWR_ACK

GPIO10

Internal VR Enable Strap (Internal VR for VccSus1.05, VccSus1.5, VccCL1.5)

ICH_INTVRMEN

ICH9M LAN100 SLP Strap (Internal VR for VccLAN1.05 and VccCL1.05)

ICH_LAN100_SLP

SPK_SEL <29> SUBWOOFER <29> BT_PWR <25> BT_RST# <25>

CLK_14M_ICH <16> CLK_48M_ICH <16>

PM_SLP_S3# <32> PM_SLP_S4# <32> PM_SLP_S5# <32>

PM_PWROK <8,32> PM_DPRSLPVR <8,42>PM_CLKRUN#<30>

PBTN_OUT# <32>

CK_PWRGD <16>

CL_CLK0 <8>

CL_DATA0 <8>

CL_RST#0 <8>

SB_INT_FLASH_SEL# <33>

SB_TVLED <34>

1 2

R359 10K_0402_5%R359 10K_0402_5%

Mobile Platform used only

Desktop Platform used only

Low = Internal VR Disabled High = Internal VR Enabled(Default)

DVT- R347 pull-up source from +3VS to +3V_SB

BAV99DW-7_SOT363

SB_RSMRST#

1 2

R345

R345 10K_0402_5%

10K_0402_5%

D12B

R352

2.2K_0402_5%

+3V_SB

+3VS

CLK_14M_ICH

CLK_48M_ICH

PM_PWROK

S4_STATE# ICH_LOW_BAT#

R342 0_0402_5%@R342 0_0402_5%@

4

5

3

12

+ICH9_CLVREF

0.1U_0402_16V4Z

1 2

R362 1K_0402_5%@R362 1K_0402_5%@

No Reboot Strap SB_SPKR Low= Default*

1 2

R329

10_0402_5%@

1 2

R331

10_0402_5%@

1 2

R334 10K_0402_5%R334 10K_0402_5%

1 2

R336 10K_0402_5%@R336 10K_0402_5%@ R337 8.2K_0402_5%R337 8.2K_0402_5%

12

Q14

123

C

E

MMBT3906_SOT23-3

B

1 2

R347

1

2

4.7K_0402_5%

D12A

D12A BAV99DW-7_SOT363

BAV99DW-7_SOT363

6

RSMRST# circuit

CL_VREF should be

0.35 V

C311

High= "No Reboot"

1

2

4.7P_0402_50V8C@

12

+3VS

R641

3.24K_0402_1%

1 2

R642

R642 453_0402_1%

453_0402_1%

1 2

SB_SPKR

1 2

C309

1 2

C310

EC_RSMRST# <32>

+3V_SB

XOR Chain Entrance Strap

1 2

R370 1K_0402_5%@R370 1K_0402_5%@

A A

5

STRAP_A16 <20>

A16 Swap Override Strap

PCI_GNT#3

Low= A16 swap override Enable High= Default* (Internal pull-up)

Flash Descriptor Security Override Strap

GPIO33

Low= Descriptor Security override High= Default* (Internal pull-up)

4

1 2

+3VS

R371 1K_0402_5%@R371 1K_0402_5%@

ICH_TP3

12

R372 1K_0402_5%@R372 1K_0402_5%@

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2008/10/1 2009/10/1

3

AZ_SDOUT <21>

Compal Secret Data

0 1

Deciphered Date

0

HDA_SDOUTICH_TP3

0 1 0 11

Description RSVD Enter XOR Chain Normal Operation Set PCIE port config bit 1

2

(Default)

Compal Electronics, Inc.

Title

Size Document Number Rev

B

Date: Sheet

Compal Electronics, Inc.

SCHEMATICS,M/B A4161

401562 G

22 48Monday, February 23, 2009

1

of

5

+RTCVCC

1U_0402_6.3V4Z

DVT- Set C322 as @ for leakage issue.

D D

SBPWR_EN#<35>

C322

0.1U_0402_16V4Z

PJ20

2

JUMP_43X79@

+1.5VS

C C

B B

1

C312

0.1U_0402_16V4Z

2

+5VALW

Q15

STAR@

Q15

STAR@

AO3413_SOT23-3

@C322

@

112

L16

FBMA-L11-201209-221LMA30T_0805

G

2

1

2

+5V_SB

+5V_SB+5VALW

S

D

1 3

220U_D2_4VM_R15

L17

L17 MBK1608121YZF_0603

MBK1608121YZF_0603

+1.5VS

1

C314

0.1U_0402_16V4Z

2

+3VS +5VS

+3V_SB +5V_SB

DVT- R374 change from 10 to 100, C313 change from 0.1U to 1U

+1.5VS_PCIE_ICH

12

C326

+1.5VS_SATAPLL_ICH+1.5VS

1 2

10U_0805_10V4Z

1

C340

C340 1U_0402_6.3V4Z

1U_0402_6.3V4Z

2

close to AE15 close to AF11

1

C315

2

D13

D13 CH751H-40PT_SOD323-2

CH751H-40PT_SOD323-2

2 1 1 2

R373

2

100_0402_5%

1

D14

D14 CH751H-40PT_SOD323-2

CH751H-40PT_SOD323-2

2 1

12

R374

R374 100_0402_5%

100_0402_5%

1

2

C337

10U_0805_10V4Z

+

C327

1

2

1

C328

2

10U_0805_10V4Z

C338

+ICH_V5REF

C318

C318 1U_0402_6.3V6K

1U_0402_6.3V6K

+ICH_V5REF_SUS

C313

C313 1U_0402_6.3V6K

1U_0402_6.3V6K

2.2U_0402_6.3V6M

1

C329

2

1

1U_0402_6.3V4Z

2

1

C341

C341 1U_0402_6.3V4Z

1U_0402_6.3V4Z

2

close to AC9

+1.5VS

1

C347

0.1U_0402_16V4Z

2

1

C348

2

0.1U_0402_16V4Z

+ICH_V5REF

+ICH_V5REF_SUS

2

1

close to AC14

+1.5VS

1

2

close to AJ5close to AC7

1

C350

0.1U_0402_16V4Z

2

+1.5VS

1

C356

0.1U_0402_16V4Z

2

+1.5VS

1

C349

0.1U_0402_16V4Z

2

+VCCLAN1_05_INT_ICH

0.1U_0402_16V4Z

A A

C351

1

+3VS

2

5

1

C354

0.1U_0402_16V4Z

2

0.1U_0402_16V4Z

C357

+3VS

4

U10F

A23

VCCRTC

A6

V5REF

AE1

V5REF_SUS

AA24

VCC1_5_B[01]

AA25

VCC1_5_B[02]

AB24

VCC1_5_B[03]

AB25

VCC1_5_B[04]

AC24

VCC1_5_B[05]

AC25

VCC1_5_B[06]

AD24

VCC1_5_B[07]

AD25

VCC1_5_B[08]

AE25

VCC1_5_B[09]

AE26

VCC1_5_B[10]

AE27

VCC1_5_B[11]

AE28

VCC1_5_B[12]

AE29

VCC1_5_B[13]

F25

VCC1_5_B[14]

G25

VCC1_5_B[15]

H24

VCC1_5_B[16]

H25

VCC1_5_B[17]

J24

VCC1_5_B[18]

J25

VCC1_5_B[19]

K24

VCC1_5_B[20]

K25

VCC1_5_B[21]

L23

VCC1_5_B[22]

L24

VCC1_5_B[23]

L25

VCC1_5_B[24]

M24

VCC1_5_B[25]

M25

VCC1_5_B[26]

N23

VCC1_5_B[27]

N24

VCC1_5_B[28]

N25

VCC1_5_B[29]

P24

VCC1_5_B[30]

P25

VCC1_5_B[31]

R24

VCC1_5_B[32]

R25

VCC1_5_B[33]

R26

VCC1_5_B[34]

R27

VCC1_5_B[35]

T24

VCC1_5_B[36]

T27

VCC1_5_B[37]

T28

VCC1_5_B[38]

T29

VCC1_5_B[39]

U24

VCC1_5_B[40]

U25

VCC1_5_B[41]

V24

VCC1_5_B[42]

V25

VCC1_5_B[43]

U23

VCC1_5_B[44]

W24

VCC1_5_B[45]

W25

VCC1_5_B[46]

K23

VCC1_5_B[47]

Y24

VCC1_5_B[48]

Y25

VCC1_5_B[49]

AJ19

VCCSATAPLL

AC16

VCC1_5_A[01]

AD15

VCC1_5_A[02]

AD16

VCC1_5_A[03]

AE15

VCC1_5_A[04]

AF15

VCC1_5_A[05]

AG15

VCC1_5_A[06]

AH15

VCC1_5_A[07]

AJ15

VCC1_5_A[08]

AC11

VCC1_5_A[09]

AD11

VCC1_5_A[10]

AE11

VCC1_5_A[11]

AF11

VCC1_5_A[12]

AG10

VCC1_5_A[13]

AG11

VCC1_5_A[14]

AH10

VCC1_5_A[15]

AJ10

VCC1_5_A[16]

AC9

VCC1_5_A[17]

AC18

VCC1_5_A[18]

AC19

VCC1_5_A[19]

AC21

VCC1_5_A[20]

G10

VCC1_5_A[21]

G9

VCC1_5_A[22]

AC12

VCC1_5_A[23]

AC13

VCC1_5_A[24]

AC14

VCC1_5_A[25]

AJ5

VCCUSBPLL

AA7

VCC1_5_A[26]

AB6

VCC1_5_A[27]

AB7

VCC1_5_A[28]

AC6

VCC1_5_A[29]

AC7

VCC1_5_A[30]

A10

VCCLAN1_05[1]

A11

VCCLAN1_05[2]

A12

VCCLAN3_3[1]

B12

VCCLAN3_3[2]

A27

VCCGLANPLL

D28

VCCGLAN1_5[1]

D29

VCCGLAN1_5[2]

E26

VCCGLAN1_5[3]

E27

VCCGLAN1_5[4]

A26

VCCGLAN3_3

ICH9-M ES_FCBGA676

ICH9-M ES_FCBGA676 SBR3@

SBR3@

4

VCCA3GP

VCCP_CORE

ARX

ATX

VCCPSUS

USB CORE

GLAN POWER

VCC1_05[01] VCC1_05[02] VCC1_05[03] VCC1_05[04] VCC1_05[05] VCC1_05[06] VCC1_05[07] VCC1_05[08] VCC1_05[09] VCC1_05[10] VCC1_05[11] VCC1_05[12] VCC1_05[13] VCC1_05[14] VCC1_05[15] VCC1_05[16]

CORE

VCC1_05[17] VCC1_05[18] VCC1_05[19] VCC1_05[20] VCC1_05[21] VCC1_05[22] VCC1_05[23] VCC1_05[24] VCC1_05[25] VCC1_05[26]

VCCDMIPLL

VCC_DMI[1] VCC_DMI[2]

V_CPU_IO[1] V_CPU_IO[2]

VCC3_3[01] VCC3_3[02] VCC3_3[07]

VCC3_3[03] VCC3_3[04] VCC3_3[05] VCC3_3[06]

VCC3_3[08] VCC3_3[09] VCC3_3[10] VCC3_3[11] VCC3_3[12]

PCI

VCC3_3[13] VCC3_3[14]

VCCSUSHDA

VCCSUS1_05[1] VCCSUS1_05[2]

VCCSUS1_5[1] VCCSUS1_5[2]

VCCSUS3_3[01] VCCSUS3_3[02] VCCSUS3_3[03] VCCSUS3_3[04]

VCCSUS3_3[05]

VCCSUS3_3[06] VCCSUS3_3[07] VCCSUS3_3[08] VCCSUS3_3[09] VCCSUS3_3[10] VCCSUS3_3[11] VCCSUS3_3[12] VCCSUS3_3[13] VCCSUS3_3[14] VCCSUS3_3[15] VCCSUS3_3[16]

VCCPUSB

VCCSUS3_3[17] VCCSUS3_3[18] VCCSUS3_3[19] VCCSUS3_3[20]

VCCCL1_05

VCCCL3_3[1] VCCCL3_3[2]

3

A15 B15 C15 D15 E15 F15 L11 L12 L14 L16 L17 L18 M11 M18 P11 P18 T11 T18 U11 U18 V11 V12 V14 V16 V17 V18

R29 W23

Y23 AB23

AC23 AG29

AJ6 AC10

AD19 AF20 AG24 AC20

B9 F9 G3 G6 J2 J7 K7

AJ4

VCCHDA

AJ3

TP_VCCSUS1_05_ICH_1

AC8

TP_VCCSUS1_05_ICH_2

F17

AD8 F18

A18 D16 D17 E22

AF1

T1 T2 T3 T4 T5 T6 U6 U7 V6 V7 W6 W7 Y6 Y7 T7

G22 G23

VCCCL1_5

A24 B24

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

1

C316

0.1U_0402_16V4Z

2

0.01U_0402_25V4Z

C323

0.1U_0402_16V4Z

close to AG29

1

C330

0.1U_0402_16V4Z

2

+VCCSUS1_5_ICH_INT

1

C342

0.1U_0402_16V4Z

2

0.022U_0402_16V7K

0.022U_0402_16V7K C344

C344

1

C352

+3VS

1U_0402_6.3V4Z

2

close to G23

3

+1.5VS_DMIPLL_ICH +1.5VS

C319

1

0.1U_0402_16V4Z

2

0.1U_0402_16V4Z

close to AD19

@

PAD

@

PAD

C345

0.022U_0402_16V7K

2008/10/1 2009/10/1

1

C317

0.1U_0402_16V4Z

2

L15

L15 MBK1608121YZF_0603

MBK1608121YZF_0603

1

C320

C320 10U_0805_10V4Z

10U_0805_10V4Z

2

+1.05VS

1

C321

4.7U_0603_6.3V6K

2

C324

1

C331

2

T10

T10 T11

T11

1

2

+VCCCL1_5_INT_ICH

1

C355

0.1U_0402_16V4Z

2

+1.05VS

1 2

1

C325

4.7U_0603_6.3V6K

2

close to AG24

1

C332

0.1U_0402_16V4Z

2

+ICH_HDA

1

2

+ICH_SUSHDA

R377 0_0603_5%

1

R378 0_0603_5%

C343

0.1U_0402_16V4Z

2

1

0.1U_0402_16V4Z

0.1U_0402_16V4Z C346

C346

2

close to AF1close to T1

Compal Secret Data

Deciphered Date

+1.05VS

0.1U_0402_16V4Z

1

C333

2

close to B9, G6, K7

C339

0.1U_0402_16V4Z

NIHDMI@

IHDMI@

+3V_SB

1

2

0.1U_0402_16V4Z

1

C335

C334

0.1U_0402_16V4Z

2

NIHDMI@

R375 0_0603_5%

R375 0_0603_5% R376 0_0603_5%

R376 0_0603_5%

IHDMI@

+3V_SB +VCCSUS1_5_ICH_INT

1K_0402_5%

+ICH_SUSHDA

1K_0402_5%

+VCCCL1_05_INT_ICH

C353

0.1U_0402_16V4Z

close to G22

2

1

2

R1007

@ R1007

@

R1008

@ R1008

@

+3VS

1

C336

0.1U_0402_16V4Z

2

close to AJ6

+3VS +1.5VS

+3V_SB

12

1

U10E

AA26

VSS[001]

AA27

VSS[002]

AA3

VSS[003]

AA6

VSS[004]

AB1

VSS[005]

AA23

VSS[006]

AB28

VSS[007]

AB29

VSS[008]

AB4

VSS[009]

AB5

VSS[010]

AC17

VSS[011]

AC26

VSS[012]

AC27

VSS[013]

AC3

VSS[014]

AD1

VSS[015]

AD10

VSS[016]

AD12

VSS[017]

AD13

VSS[018]

AD14

VSS[019]

AD17

VSS[020]

AD18

VSS[021]

AD21

VSS[022]

AD28

VSS[023]

AD29

VSS[024]

AD4

VSS[025]

AD5

VSS[026]

AD6

VSS[027]

AD7

VSS[028]

AD9

VSS[029]

AE12

VSS[030]

AE13

VSS[031]

AE14

VSS[032]

AE16

VSS[033]

AE17

VSS[034]

AE2

VSS[035]

AE20

VSS[036]

AE24

VSS[037]

AE3

VSS[038]

AE4

VSS[039]

AE6

VSS[040]

AE9

VSS[041]

AF13

VSS[042]

AF16

VSS[043]

AF18

VSS[044]

AF22

VSS[045]

AH26

VSS[046]

AF26

VSS[047]

AF27

VSS[048]

AF5

VSS[049]

AF7

VSS[050]

AF9

VSS[051]

AG13

VSS[052]

AG16

VSS[053]

AG18

VSS[054]

AG20

VSS[055]

AG23

VSS[056]

AG3

VSS[057]

AG6

VSS[058]

AG9

VSS[059]

AH12

VSS[060]

AH14

VSS[061]

AH17

VSS[062]

AH19

VSS[063]

AH2

VSS[064]

AH22

VSS[065]

AH25

VSS[066]

AH28

VSS[067]

AH5

VSS[068]

AH8

VSS[069]

AJ12

VSS[070]

AJ14

VSS[071]

AJ17

VSS[072]

AJ8

VSS[073]

B11

VSS[074]

B14

VSS[075]

B17

VSS[076]

B2

VSS[077]

B20

VSS[078]

B23

VSS[079]

B5

VSS[080]

B8

VSS[081]

C26

VSS[082]

C27

VSS[083]

E11

VSS[084]

E14

VSS[085]

E18

VSS[086]

E2

VSS[087]

E21

VSS[088]

E24

VSS[089]

E5

VSS[090]

E8

VSS[091]

F16

VSS[092]

F28

VSS[093]

F29

VSS[094]

G12

VSS[095]

G14

VSS[096]

G18

VSS[097]

G21

VSS[098]

G24

VSS[099]

G26

VSS[100]

G27

VSS[101]

G8

VSS[102]

H2

VSS[103]

H23

VSS[104]

H28

VSS[105]

H29

VSS[106]

ICH9-M ES_FCBGA676

ICH9-M ES_FCBGA676 SBR3@

SBR3@

Title

Size Document Number Rev

Custom

Date: Sheet

VSS_NCTF[01] VSS_NCTF[02] VSS_NCTF[03] VSS_NCTF[04] VSS_NCTF[05] VSS_NCTF[06] VSS_NCTF[07] VSS_NCTF[08] VSS_NCTF[09] VSS_NCTF[10] VSS_NCTF[11] VSS_NCTF[12]

Compal Electronics, Inc.

SCHEMATICS,M/B A4161

401562 G

VSS[107] VSS[108] VSS[109] VSS[110] VSS[111] VSS[112] VSS[113] VSS[114] VSS[115] VSS[116] VSS[117] VSS[118] VSS[119] VSS[120] VSS[121] VSS[122] VSS[123] VSS[124] VSS[125] VSS[126] VSS[127] VSS[128] VSS[129] VSS[130] VSS[131] VSS[132] VSS[133] VSS[134] VSS[135] VSS[136] VSS[137] VSS[138] VSS[139] VSS[140] VSS[141] VSS[142] VSS[143] VSS[144] VSS[145] VSS[146] VSS[147] VSS[148] VSS[149] VSS[150] VSS[151] VSS[152] VSS[153] VSS[154] VSS[155] VSS[156] VSS[157] VSS[158] VSS[159] VSS[160] VSS[161] VSS[162] VSS[163] VSS[164] VSS[165] VSS[166] VSS[167] VSS[168] VSS[169] VSS[170] VSS[171] VSS[172] VSS[173] VSS[174] VSS[175] VSS[176] VSS[177] VSS[178] VSS[179] VSS[180] VSS[181] VSS[182] VSS[183] VSS[184] VSS[185] VSS[186] VSS[187] VSS[188] VSS[189] VSS[190] VSS[191] VSS[192] VSS[193] VSS[194] VSS[195] VSS[196] VSS[197] VSS[198]

H5 J23 J26 J27 AC22 K28 K29 L13 L15 L2 L26 L27 L5 L7 M12 M13 M14 M15 M16 M17 M23 M28 M29 N11 N12 N13 N14 N15 N16 N17 N18 N26 N27 P12 P13 P14 P15 P16 P17 P2 P23 P28 P29 P4 P7 R11 R12 R13 R14 R15 R16 R17 R18 R28 T12 T13 T14 T15 T16 T17 T23 B26 U12 U13 U14 U15 U16 U17 AD23 U26 U27 U3 V1 V13 V15 V23 V28 V29 V4 V5 W26 W27 W3 Y1 Y28 Y29 Y4 Y5 AG28 AH6 AF2 B25

A1 A2 A28 A29 AH1 AH29 AJ1 AJ2 AJ28 AJ29 B1 B29

of

23 48Monday, February 23, 2009

1

5

1st SATA HDD Conn.

+5VS

Place closely JP25 SATA CONN.

1

C359

C359 10U_0805_10V4Z

10U_0805_10V4Z

2

D D

C C

+3VS +3VS

+3VS rail reserve for SSD

1

C368

C368 10U_0805_10V4Z

10U_0805_10V4Z

2

SSD@

JP10

24

GND

23

GND

OCTEK_tSAT-0801001_NR

@JP10

@

GND HTX+ HTX-

GND HRX-

HRX+

GND

VCC3.3 VCC3.3 VCC3.3

GND

VCC5 VCC5 VCC5

GND

RESERVED

GND

VCC12 VCC12 VCC12

1

C360

0.1U_0402_16V4Z

2

1

C370

0.1U_0402_16V4Z

2

SSD@

1 2 3 4 5 6 7

8 9 10 11 12 13 14 15 16 17 18 19 20 21 22

1

C361

0.1U_0402_16V4Z

2

1

C371

0.1U_0402_16V4Z

2

SSD@

SATA_ITX_C_DRX_P0 SATA_ITX_C_DRX_N0

SATA_IRX_DTX_N0 SATA_IRX_DTX_P0

C303 0.01U_0402_16V7KC303 0.01U_0402_16V7K C304 0.01U_0402_16V7KC304 0.01U_0402_16V7K

C379 0.01U_0402_16V7KC379 0.01U_0402_16V7K C378 0.01U_0402_16V7KC378 0.01U_0402_16V7K

+3VS

+5VS

4

1

C362

0.1U_0402_16V4Z

2

1 2 1 2

3

EVT2- For HDD change issue, remove C374/C369/C377/C372 Delete C358/C363

SATA_ITX_DRX_P0 <21> SATA_ITX_DRX_N0 <21>

SATA_IRX_C_DTX_N0 <21> SATA_IRX_C_DTX_P0 <21>

2nd SATA HDD Conn.

+5VS

Place closely JP55 SATA CONN.

1

C364

2HDD@C364

2HDD@

10U_0805_10V4Z

2

+3VS rail reserve for SSD

1

C373

C373 10U_0805_10V4Z

10U_0805_10V4Z

2

2SSD@

EVT2- Change JP11, HDD connector type for screw issue.EVT2- Change JP10, HDD connector type to DIP component.

JP11

@ JP11

@

1

GND

2

A+

3

A-

4

GND

5

B-

6

B+

7

GND

8

V33

9

V33

10

V33

11

GND

12

GND

13

GND

14

V5

15

V5

16

V5

17

GND

18

Reserved

19

GND

20

V12

24

GND

23

GND

SANTA_198202-1_NR

V12 V12

21 22

1

C365

2HDD@C365

2HDD@

0.1U_0402_16V4Z

2

1

C375

0.1U_0402_16V4Z

2

2SSD@

SATA_ITX_C_DRX_P1 SATA_ITX_C_DRX_N1

SATA_IRX_DTX_N1 SATA_IRX_DTX_P1

2

1

C366

2HDD@C366

2HDD@

0.1U_0402_16V4Z

2

1

C376

0.1U_0402_16V4Z

2

2SSD@

C307 0.01U_0402_16V7K2HDD@C307 0.01U_0402_16V7K2HDD@

1 2

C308 0.01U_0402_16V7K2HDD@C308 0.01U_0402_16V7K2HDD@

1 2

C380 0.01U_0402_16V7K2HDD@C380 0.01U_0402_16V7K2HDD@

1 2

C381 0.01U_0402_16V7K2HDD@C381 0.01U_0402_16V7K2HDD@

1 2

+3VS

+5VS

1

C367

2HDD@C367

2HDD@

0.1U_0402_16V4Z

2

1

SATA_ITX_DRX_P1 <21> SATA_ITX_DRX_N1 <21>

SATA_IRX_C_DTX_N1 <21> SATA_IRX_C_DTX_P1 <21>

SATA ODD Conn

+5VS

1

C384

0.1U_0402_16V4Z

2

C301 0.01U_0402_16V7KC301 0.01U_0402_16V7K C302 0.01U_0402_16V7KC302 0.01U_0402_16V7K

C388 0.01U_0402_16V7KC388 0.01U_0402_16V7K C389 0.01U_0402_16V7KC389 0.01U_0402_16V7K

+5VS

1 2 3 4 5 6 7

8 9 10 11 12 13

1

C383

2

1U_0402_6.3V4Z

SATA_ITX_C_DRX_P4 SATA_ITX_C_DRX_N4

SATA_IRX_DTX_N4 SATA_IRX_DTX_P4

1

C386

C386 10U_0805_10V4Z

10U_0805_10V4Z

B B

2

1

C382

C382 10U_0805_10V4Z

10U_0805_10V4Z

2

Place component's closely ODD CONN.

JP12

GND

A+ A-

GND

BB+

GND

DP

V5 V5

GND GND

MD

5

14

A A

15

OCTEK_tSLS-0711037@

0.1U_0402_16V4Z

1 2 1 2

1

C385

2

USBP20_N3 USBP20_P3

SATA_ITX_DRX_P4 <21>

SATA_ITX_DRX_N4 <21>

SATA_IRX_C_DTX_N4 <21> SATA_IRX_C_DTX_P4 <21>

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

eSATA w/ USB port

+USB_VCCA

W=60mils

1

+

C779

150U_Y_6.3VM

@

D40

2 3

PJDLC05_SOT23-3

@

SATA_ITX_DRX_P5<21> SATA_ITX_DRX_N5<21>

SATA_IRX_C_DTX_N5<21> SATA_IRX_C_DTX_P5<21>

2008/10/1 2009/10/1

3

1

C306 0.01U_0402_25V7KESATA@C306 0.01U_0402_25V7KESATA@

1 2

C305 0.01U_0402_25V7KESATA@C305 0.01U_0402_25V7KESATA@

1 2

C390 0.01U_0402_25V7KESATA@C390 0.01U_0402_25V7KESATA@ C391 0.01U_0402_25V7KESATA@C391 0.01U_0402_25V7KESATA@

Compal Secret Data

Deciphered Date

@

12 12

2

USB20_N3<20>

USB20_P3<20>

ESATA@

1000P_0402_50V7K

1

C780

2

0.1U_0402_16V4Z

SATA_ITX_C_DRX_P5 SATA_ITX_C_DRX_N5

SATA_IRX_DTX_N5

SATA_IRX_DTX_P5

2

1

C781

C781 ESATA@

ESATA@

2

USBP20_N3 USBP20_P3

PVT- Update ESATA connector footprint for latche hole size.

JP13

USB

1

B_VCC

2

B_D-

3

B_D+

4

B_GND

5

GND

6

A+

ESATA

7

A-

8

GND

SHIELD

9

B-

SHIELD

10

B+

SHIELD

11

GND

SHIELD

FOX_3Q318111-RB133A-8F

@

Title

Size Document Number Rev

Custom

Date: Sheet

Compal,Electronics,Lnc.

SCHEMATICS,M/B A4161

12 13 14 15

401562 G

1

of

24 48Monday, February 23, 2009

of

24 48Monday, February 23, 2009

of

24 48Monday, February 23, 2009

5

BlueTooth Interface

D D

BT_PWR<22>

BT@

2N7002_SOT23-3

BT_RST#<22>

C C

1 2

R382

+5VS

BT@

2

G

Q17

BT_RESET#

BT@

0_0402_5%

C398

C398 BT@

BT@

0.1U_0402_16V4Z

R379

R379 1M_0402_5%

1M_0402_5% R380

1 2

100K_0402_5%

13

D

1000P_0402_50V7K

S

WLAN_BT_CLK<26> BT_DET#<22>

WLAN_BT_DATA<26>

BT@R380

BT@

AO3413_SOT23-3

C395

BT@ C395

BT@

USB20_P5<20> USB20_N5<20>

+BT_VCC

4.7U_0603_6.3V6K

+3VS

Q16

BT@

Q16

BT@

2

1

(MAX=200mA)

1

C399

C399 BT@

BT@

2

+3VS

C392

0.1U_0402_16V4Z

S

G

D

1 3

1 2

R381 0_0402_5%BT@R381 0_0402_5%BT@

1 2

R383 4.7K_0402_5%@R383 4.7K_0402_5%@

C400

C400 BT@

BT@

0.1U_0402_16V4Z

+BT_VCC

BT@C392

BT@

4

Bluetooth Connector

R384

R384 BT@

BT@

4.7K_0402_5%

1 2

JP15

@JP15

@

1

2

3

4

5

6

7

8

9

G11

9

10

G12

10

ACES_87212-10G0

3

2

1

USB CONN. 1 -- Rear USB CONN.2 -- Right

+USB_VCCB

+USB_VCCA

1

+

C784

150U_Y_6.3VM

USB20_N0 USB20_P0

11 12

2

D41

2 3

PJDLC05_SOT23-3@

+5VALW +5VALW

USB_OC#0<20>

DVT-R1020 and R1021 set as mount and add F3 and F4 for USB protect solution. Delete F3 and F4, just reserve space for layout.

W=60mils

1

C786

2

0.1U_0402_16V4Z

USB20_N0<20> USB20_P0<20>

1

U15

1

GND

2

IN

3

IN

4

EN#

G528P1UF_SO8

1

C787

C787 1000P_0402_50V7K

1000P_0402_50V7K

2

USB20_N0 USB20_P0

P-TWO_CU304G-A0G1G-P

8

OUT

7

OUT

6

OUT

5

FLG

1 2

R1020 0_0402_5%R1020 0_0402_5%

JP48

1

VCC

2

D-

3

D+

4

GND

5

GND

6

GND

7

GND

8

GND

1

C492

0.1U_0402_16V4Z

2

150U_Y_6.3VM

USB20_N1 USB20_P1

USB_EN#<29,32>

C782

1

+

2

0.1U_0402_16V4Z

2 3

C783

USB20_N1<20>

USB20_P1<20>

D42

PJDLC05_SOT23-3@

USB_EN#USB_EN#

1

2

USB_OC#1<20>

W=60mils

1

2

USB20_N1 USB20_P1

1

U14

1 2 3 4

G528P1UF_SO8

C785

C785 1000P_0402_50V7K

1000P_0402_50V7K

GND

OUT

IN

OUT OUT

IN

FLG

EN#

1 2

R1021 0_0402_5%R1021 0_0402_5%

EVT2- Change JP47, USB connector type, from SMD to DIP.

JP47

@JP47

@

GND GND GND GND

+USB_VCCB+USB_VCCA

0.1U_0402_16V4Z

5 6 7 8

1

2

1

VCC

2

D-

3

D+

4

GND

ALLTO_SK-C107B8

8 7 6 5

C394

Finger printer

+3VS

1

C401

0.1U_0402_16V4Z

FP@

2

USB20_N4<20> USB20_P4<20>

B B

FM Module

EVT2- Change FM tuner from USB I/F to I2C linked to SB DVT- Add R1032 reserve for FM_I2CINT# DVT2- Change JP5 Layout location, and pin9 connector to GND

JP5

@ JP5

@

1

2

FM_I2CCLK

3

FM_I2CDAT

4

FM_I2CINT_R#

5

6

7

8

GND

9

1010GND

11 12

ACES_88514-1041

A A

DVT2- Change JP16 Layout location.

JP16

USB20_N4 USB20_P4

7 5

ACES_85203-04021

+3VS

FM_I2CCLK <22>

FM_I2CDAT <22>

FM_LINE_R <29> FM_LINE_L <29>

334 112

887 665

4 2

R1032 0_0402_5%@R1032 0_0402_5%@

1 2

USB20_N4 USB20_P4

FM_I2CCLK

R1017 4.7K_0402_5%R1017 4.7K_0402_5%

FM_I2CDAT

R1018 4.7K_0402_5%R1018 4.7K_0402_5%

FM_I2CINT#

R1019 100K_0402_5%R1019 100K_0402_5%

FM_I2CINT#

2 3

1 2 1 2 1 2

D45

PJDLC05_SOT23-3@

FM_I2CINT# <22>

1

+3VS

Felica

+FLICA_VCC

1

2

Int. Camera

EVT2- Change JP17, Felica connector, new conn. DVT2- Change JP17 Layout location.

Reserve R151 for Felica PWR controlled signal.

USB20_N9<20>

FLICA@C402

FLICA@

USB20_P9<20>

C402

0.1U_0402_16V4Z

W=20mils

R385

GND GND

+CAM_VDD

1

2

3

4

5

6 7

+5VALW

0_0603_5%

0_0603_5% CAM@

CAM@

JP18

ACES_87212-05G0

FELICA_PWR_R<22>

1

C405

0.1U_0402_16V4Z

2

CAM@

JP17

@JP17

@

2

112

4

334

5

665

7

887

ACES_85203-04021

FELICA_PWR<21>

USB20_N11 <20> USB20_P11 <20>

1 2

R151 0_0402_5%@R151 0_0402_5%@

1 2

R152 0_0402_5%

R152 0_0402_5% FLICA@

FLICA@

CAM_PWR<22>

2N7002_SOT23-3

Q25

Q25 FLICA@

FLICA@

2

G

2N7002_SOT23-3

+5VS

Q30

@

Q30

@

2

G

+5VS

R414 1M_0402_5%

1M_0402_5%

1 2 13

D

C397

1000P_0402_50V7K

S

R415

@R415

@

1M_0402_5%

R413

1 2

100K_0402_5%

13

D

C406

1000P_0402_50V7K

S

FLICA@R414

FLICA@

R388

FLICA@R388

FLICA@

1 2

100K_0402_5%

FLICA@C397

FLICA@

@R413

@

@C406

@

2

1

Q26

G

2

AO3413_SOT23-3

1

+5VS

S

Q19

G

2

D

1 3

AO3413_SOT23-3

FLICA@

+5VS

S

D

1 3

@

+CAM_VDD

C403

0.1U_0402_16V4Z

+FLICA_VCC

C404

0.1U_0402_16V4Z

FLICA@C403

FLICA@

@C404

@

Security Classification

2008/10/1 2009/10/1

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2008/10/1 2009/10/1

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

SCHEMATICS,M/B A4161

401562 G

1

of

25 48Monday, February 23, 2009

of

25 48Monday, February 23, 2009

of

25 48Monday, February 23, 2009

Slot1 - PCIe Mini Card for Wi-Fi/WiMax

+3V_WLAN

0.1U_0402_16V4Z

PCIE_IRX_C_WLANTX_N4<20> PCIE_IRX_C_WLANTX_P4<20>

PCIE_ITX_C_WLANRX_N4<20> PCIE_ITX_C_WLANRX_P4<20>

0.1U_0402_16V4Z

1

C409

SLOT1@

2

+3V_WLAN

WLAN_WAKE#<32>

WLAN_BT_DATA<25>

WLAN_BT_CLK<25>

CLKREQ_WLAN#<16>

CLK_WLAN#<16> CLK_WLAN<16>

SLOT1@

0.01U_0402_25V4Z

0.1U_0402_16V4Z

1

C410

2

R387

R387 100K_0402_5%

100K_0402_5%

1 2

SLOT1@

C412

C411

SLOT1@

2

4.7U_0603_6.3V6K

WLAN_BT_DATA WLAN_BT_DATA WLAN_BT_CLK WLAN_BT_CLK CLKREQ_WLAN# CLKREQ_WLAN#

CLK_WLAN# CLK_WLAN# CLK_WLAN CLK_WLAN

PCIE_IRX_C_WLANTX_N4 PCIE_IRX_C_WLANTX_N4 PCIE_IRX_C_WLANTX_P4 PCIE_IRX_C_WLANTX_P4

PCIE_ITX_C_WLANRX_N4 PCIE_ITX_C_WLANRX_N4 PCIE_ITX_C_WLANRX_P4 PCIE_ITX_C_WLANRX_P4

ShirleyPeak : Intel

3.3VALW

WLAN_WAKE#WLAN_WAKE#

EchoPeak : Intel

3.3VALW

Slot3 - PCIe Mini Card for UWB/ DVB-T analog/digital Hybrid TV Tuner

+3VS +1.5VS

0.1U_0402_16V4Z

1

C422

SLOT3@

2

0.01U_0402_25V4Z

C423

SLOT3@

1

C424

C424 SLOT3@

SLOT3@

2

4.7U_0603_6.3V6K

C427

SLOT3@

0.1U_0402_16V4Z

JP20B

B1

WAKE#

B3

COEX1

B5

COEX1

B7

CLKREQ#

GND

B11

REFCLK-

B13

REFCLK+

GND

B17

Reserved

B19

Reserved

GND

B23

PERn0

B25

PERp0

GND

GND GND

GND

B31

PETn0

B33

PETp0

GND

B37

GND

B39

+3.3Vaux

B41

+3.3Vaux

B43

GND

B45

Reserved

B47

Reserved

B49

Reserved

B51

Reserved

QUASA_CA0416-092N21

1

2

@

WL_OFF#<32>

KILL_SW#<32,34>

+3V_WLAN

W_DISABLE#

LED_WWAN#

LED_WPAN#

KS@ U17

KS@

NC7SZ08P5X_NL_SC70-5

KILL_SW#

EVT2- Update connector pin assigment.

A1 A3 A5 A7

A9 A11 A13 A15 A17 A19 A21 A23 A25 A27 A29 A31 A33 A35 A37 A39 A41 A43 A45 A47 A49 A51

A53

UWB_OFF#<32>

B2

+3.3Vaux

B4

GND

B6

+1.5V

B8

UIM_PWR

B10

UIM_DATA

B12

UIM_CLK

UIM_VPP

GND

PERST#

+3.3Vaux

GND

+1.5V

SMB_CLK

GND

USB_D-

USB_D+

GND

+1.5V

GND

+3.3Vaux

B14 B16 B18 B20 B22 B24 B26 B28 B30 B32 B34 B36 B38 B40 B42 B44 B46 B48 B50 B52

UIM_RESET

SMB_DATA

LED_WLAN#

+3V_WLAN

KS@

C428 0.1U_0402_16V4Z

1 2

U17

5

2

P

B

4

Y

1

A

G

3

JP20A

@

JP20A

@

WAKE# COEX1 COEX2 CLKREQ# GND REFCLKREFCLK+ GND Reserved Reserved GND PERn0 PERp0 GND GND PETn0 PETp0 GND GND +3.3Vaux +3.3Vaux GND Reserved Reserved Reserved Reserved

GND

QUASA_CA0416-092N21

+3VS+1.5VS

UWB_DISABLE#

UWB : Askey

3.3V/1.5V

EVT2- Separate XMIT_OFF# to XMIT_OFF# and XMIT_OFF_R#. Add R420 for XMT_OFF_R# pull-high

XMIT_OFF#

DVT-Add R421 for floating issue and rotate and swap Q24.3 and Q24.1. DVT2-Add R12 and R323 reserve for WiMax LED controlled circuit.

R12

SLOT1@R12

SLOT1@

+3V_WLAN

W_DISABLE#

LED_WWAN#

NC7SZ08P5X_NL_SC70-5

PLT_RST#

USB20_N6 USB20_N6 USB20_N6 USB20_P6 USB20_P6 USB20_P6

1 2

10K_0402_5%

LED_WWAN_R#

A2

+3.3Vaux

GND

A6

+1.5V

A8

UIM_PWR

A10

UIM_DATA

A12

UIM_CLK

UIM_RESET

SMB_DATA

LED_WLAN# LED_WPAN#

A14 A16

UIM_VPP

GND

A20 A22

PERST#

A24

+3.3Vaux

GND

A28

+1.5V

A30

SMB_CLK

A32

GND

A36

USB_D-

A38

USB_D+

GND

A42 A44 A46 A48

+1.5V

GND

A52

+3.3Vaux

A54

GND

+3VS

U22

KS@ U22

KS@

2 1

1 2

R128 0_0402_5%@R128 0_0402_5%@

TV : YUAN

3.3V only

Issued Date

B A

KILL_SW#

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

XMIT_OFF#

Q24

Q24 SLOT1@

SLOT1@

+3V_WLAN

2N7002_SOT23-3

1 2

R323 0_0402_5%@R323 0_0402_5%@

XMIT_OFF# XMIT_OFF# PLT_RST# PLT_RST#

USB20_N7 USB20_P7

LED_WWAN_R#

LED_WLAN# LED_WLAN#

EchoPeak : Intel

3.3VALW

C430

KS@C430

KS@

0.1U_0402_16V4Z

1 2

5

P

4

Y

G

3

LED_GPS_STATE

GPS : UBlox

3.3V only

R421

SLOT1@R421

SLOT1@

100K_0402_5%

G

2

1 2

13

D

S

D

S

ShirleyPeak : Intel

3.3VALW

UWB_DISABLE#

USB20_N6 <20> USB20_P6 <20>

2008/10/1 2009/10/1

+3V_WLAN

LED_WWAN# <34>

USB20_N7 <20> USB20_P7 <20>

UWB_DISABLE# <27>

Compal Secret Data

Deciphered Date

+3VALW_CARD +3VS_CARD +1.5VS_CARD

1

C435

NEW@

10U_0805_6.3V6M

2

EVT2- Change U59 partnumber from SA00001ZM10 to SA000029E00 and add R416 to pull low PLT_RST# DVT-Change C435 and C439 for ME High-Limit issue. DVT2-Remove NEW@ from R416.

1 2

R416

R416 100K_0402_5%

100K_0402_5%

+3V_SB

10K_0402_5%

RCLKEN

+3VALW_CARD

PCIE_IRX_C_NEWTX_N1<20> PCIE_IRX_C_NEWTX_P1<20>

PCIE_ITX_C_NEWRX_N1<20> PCIE_ITX_C_NEWRX_P1<20>

1

C436

NEW@

0.1U_0402_16V4Z

2

PLT_RST#

+3VS

+3V_SB

PLT_RST#<8,17,20,27..29,32,33>

SYSON<32,34,35,41>

SUSP#<17,29,32,35,40>

CP_USB#

1 2

R390 100K_0402_5%NEW@R390 100K_0402_5%NEW@ R391 100K_0402_5%R391 100K_0402_5%

R393

NEW@

2

G

PM_SMBCLK<14..16,22> PM_SMBDATA<14..16,22>

+1.5VS_CARD

EC_SWI#<22,32>

+3VS_CARD

EXP_CPPE#<20> CLK_NEW#<16> CLK_NEW<16>

1 2

+3VS

12

13

D

S

USB20_N8<20> USB20_P8<20>

EXP_CPPE#

10K_0402_5%

CLKREQ#

Q18

Q18 2N7002_SOT23-3

2N7002_SOT23-3 NEW@

NEW@

1

C437

NEW@

NEW@ 10U_0805_10V4Z

10U_0805_10V4Z

2

+1.5VS

PLT_RST#

EXP_CPPE# CP_USB#

RCLKEN

+3VS +3VS

12

R392

NEW@

2 1

CP_USB#

PM_SMBCLK PM_SMBDATA

PERST#

CLKREQ# EXP_CPPE#

Title

Size Document Number Rev

B

Monday, February 23, 2009

Date: Sheet

1

C438

NEW@

0.1U_0402_16V4Z

2

U59

12

1.5Vin

14

1.5Vin

2

3.3Vin

4

3.3Vin AUX_IN17AUX_OUT

6

SYSRST#

20

SHDN#

1

STBY#

10

CPPE#

9

CPUSB#

18

B A

Thermal_Pad

RCLKEN

G577BSR91U_TQFN20_4x4

NEW@

1

C441

C441 NEW@

NEW@

0.1U_0402_16V4Z

5

3

0.1U_0402_16V4Z

2

U19

4

Vcc

Y

G

NC7SZ32P5X_NL_SC70-5

NC7SZ32P5X_NL_SC70-5 NEW@

NEW@

JP23

@JP23

@

1

GND

2

USB_D-

3

USB_D+

4

CPUSB#

5

RSV

6

RSV

7

SMB_CLK

8

SMB_DATA

9

+1.5V

10

+1.5V

11

WAKE#

12

+3.3VAUX

13

PERST#

14

+3.3V

15

+3.3V

16

CLKREQ#

17

CPPE#

18

REFCLK-

19

REFCLK+

20

GND

21

PERn0

22

PERp0

23

GND

24

PETn0

25

PETp0

26

GND

27

GND

28

GND

29

GND

30

GND

TYCO_1759100-1

1.5Vout

3.3Vout

PERST#

C439

NEW@

NEW@ 10U_0805_6.3V6M

10U_0805_6.3V6M

11 13

3 5

15 19

OC#

8 16

NC

7

GND

21

1

2

PERST#

CLKREQ_NEW# <16>

EVT2- Reserve JP19 for ME connector 2nd source

Compal,Electronics,Lnc.

SCHEMATICS,M/B A4161

401562 G

26 48

+1.5VS_CARD

+3VS_CARD

+3VALW_CARD

1

C440

NEW@

0.1U_0402_16V4Z

2

of

A

PCIe Mini Card for TMA

EVT2- Change JP24, TMA connector from 34pin to 24pin type.

1 1

2 2

DVT- Change JP24, TMA connector from 24pin to 26pin type. To add TMA_TMP and ECAGND. PVT- Change JP24 pin24 as NC because near power pin to prevent assembly issue.

CLKREQ_TMA#<16>

+3VS

+1.5VS CLK_TMA#<16> CLK_TMA<16>

PCIE_IRX_C_TMATX_N5<20> PCIE_IRX_C_TMATX_P5<20>

PCIE_ITX_C_TMARX_N5<20> PCIE_ITX_C_TMARX_P5<20>

PLT_RST#<8,17,20,26,28,29,32,33>

+1.5VS

+3VS

ECAGND<30,32> TMA_TMP<32>

TMA_CLKDWN#<32>

TMA_ALERT#<32>

+3VS

1

C442

0.01U_0402_25V4Z

2

TMA@

UWB_DISABLE#

PLT_RST#

LED_WLON#

B

1

C443

0.1U_0402_16V4Z

2

TMA@

26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

9 8 7 6 5 4 3 2 1

P-TWO_196090-26041

C444

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K TMA@

TMA@

JP24

@JP24

@

26

GND

25

GND 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1

C

+5VS

1

C788

C788 10U_0805_10V4Z

10U_0805_10V4Z

2

TMA@

+1.5VS

1

C793

28 27

C793 10U_0805_10V4Z

10U_0805_10V4Z

2

TMA@

1

C789

C789 10U_0805_10V4Z

10U_0805_10V4Z

2

TMA@

1

C794

0.1U_0402_16V4Z

2

TMA@

1

C790

0.1U_0402_16V4Z

2

TMA@

1

C795

0.1U_0402_16V4Z

2

TMA@

D

1

C791

0.1U_0402_16V4Z

2

TMA@

1

C792

0.1U_0402_16V4Z

2

TMA@

EVT2- Change JP25, TMA power connector type, from righ-angle to Harizantial.

JP25

@JP25

@

+5VS

+1.5VS

ACES_87216-2016

112 334 556 778 9910 111112 131314 151516 171718 191920

G121G2

2 4 6 8 10 12 14 16 18 20

22

E

+5VS

Slot2 - PCIe Mini Card for Robson/ HDDVD

+3VS

SLOT2@ C417

SLOT2@

1

0.1U_0402_16V4Z

C416

SLOT2@C416

SLOT2@

2

0.01U_0402_25V4Z

C417

1

2

SLOT2@

4.7U_0603_6.3V6K

C418

+1.5VS

1

0.1U_0402_16V4Z

C419

2

0.01U_0402_25V4Z

C420

SLOT2@ C420

SLOT2@

SLOT2@C419

SLOT2@

1

SLOT2@ C421

SLOT2@

4.7U_0603_6.3V6K

2

C421

3 3

CLKREQ_NAND#<16>

CLK_NAND#<16> CLK_NAND<16>

PCIE_IRX_C_NANDTX_N2<20> PCIE_IRX_C_NANDTX_P2<20>

PCIE_ITX_C_NANDRX_N2<20> PCIE_ITX_C_NANDRX_P2<20>

4 4

A

CLKREQ_NAND# CLKREQ_NAND# CLK_NAND# CLK_NAND#

CLK_NAND CLK_NAND

PCIE_IRX_C_NANDTX_N2 PCIE_IRX_C_NANDTX_N2 PCIE_IRX_C_NANDTX_P2 PCIE_IRX_C_NANDTX_P2

PCIE_ITX_C_NANDRX_N2 PCIE_ITX_C_NANDRX_N2 PCIE_ITX_C_NANDRX_P2 PCIE_ITX_C_NANDRX_P2

HDDVDIntel Turbo MEM.

B

JP22

@JP22

@

1

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51

GND1

GND2

2 4 6

8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52

3 5 7

9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51

53

FOX_AS0B226-S40N-7F

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

+1.5VS +3VS

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52

54

2008/10/1 2009/10/1

C

For PCIE UWB

PLT_RST#

Compal Secret Data

UWB_DISABLE# <26>

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

D

Date: Sheet

Compal Electronics, Inc.

SCHEMATICS,M/B A4161

401562

E

G

of

27 48Monday, February 23, 2009

of

27 48Monday, February 23, 2009

of

27 48Monday, February 23, 2009

G

5

4

3

2

1

EVT2- SA093461070 shortage, change source to SA000019910.

1 2

U20

LED3 LED2 LED1 LED0

45 47 48 44

54 55 56 57

3 4 6 7 9 10 12 13

21 32 38 43 49 52

22 28

16 37 46 53

63 2

59 8

11 14 58

50 51

LAN_DO LAN_DI LAN_SK LAN_CS

LAN_LINK# LAN_ACTIVITY#

LAN_MDI0+ LAN_MDI0LAN_MDI1+ LAN_MDI1LAN_MDI2+ LAN_MDI2LAN_MDI3+ LAN_MDI3-

+LAN_VDD12

+LAN_EVDD12

+3V_LAN

+VDDSR +AVDD33

1 2

R402 75_0402_1%R402 75_0402_1%

1 2

R404 75_0402_1%R404 75_0402_1%

1 2

R405 75_0402_1%R405 75_0402_1%

RJ45_GND

C448 0.1U_0402_16V7KC448 0.1U_0402_16V7K

PCIE_IRX_C_LANTX_P3<20>

PCIE_IRX_C_LANTX_N3<20>

D D

+3V_LAN

1 2

R395 100K_0402_5%R395 100K_0402_5%

+3VS

12

R397

R397 1K_0402_1%

1K_0402_1%

ISOLATEB

R399

R399 15K_0402_5%

C C

B B

A A

15K_0402_5%

C472

27P_0402_50V8J

0.01U_0402_25V4Z

25MHz_20pF_6X25000017

1

2

1 2

C449 0.1U_0402_16V7KC449 0.1U_0402_16V7K

1 2

PCIE_ITX_C_LANRX_P3<20> PCIE_ITX_C_LANRX_N3<20>

CLK_LAN<16> CLK_LAN#<16>

PLT_RST#<8,17,20,26,27,29,32,33>

LOM_WAKE#

+LAN_VDD12

Y1

0.01U_0402_16V7K

2

C10

1

LOM_WAKE#<32>

LAN_X2LAN_X1

12

1

2

1

C481

2

+3V_LAN

C473

C473 27P_0402_50V8J

27P_0402_50V8J

1

2

Place these components colsed to LAN chip

PCIE_IRX_LANTX_P3 PCIE_IRX_LANTX_N3

+LAN_CTRL18

R396

R396 0_0402_5%

0_0402_5%

1 2

R398 2.49K_0402_1%R398 2.49K_0402_1%

LOM_WAKE#

ISOLATEB

LAN_X1 LAN_X2

LAN_MDI3LAN_MDI3+

LAN_MDI2LAN_MDI2+

LAN_MDI1LAN_MDI1+

LAN_MDI0LAN_MDI0+

C482

0.01U_0402_16V7K

29

HSOP

30

HSON

23

HSIP

24

HSIN

33

CLKREQB

26

REFCLK_P

27

REFCLK_N

20

PERSTB

1

SROUT12

5

FB12

62

ENSR

64

RSET

19

LANWAKEB

36

ISOLATEB

60

CKTAL1

61

CKTAL2

65

EXPOSE_PAD

25

EGND

31

EGND

15

NC

17

NC

18

NC

34

NC

35

NC

39

NC

40

NC

41

NC

42

NC

RTL8111C-GR_QFN64_9X9

EEDO

EEDI/AUX

EESK EECS

MDIP0 MDIN0 MDIP1 MDIN1 MDIP2 MDIN2 MDIP3 MDIN3

DVDD12 DVDD12 DVDD12 DVDD12 DVDD12 DVDD12

EVDD12 EVDD12

VDD33 VDD33 VDD33 VDD33

VDDSR

AVDD33 AVDD33

AVDD12 AVDD12 AVDD12 AVDD12

IGPIO

OGPIO

DVT-Change transformer vendor from Bothand to Superworld

T1

C483

1

2

1

TCT1

2

TD1+

3

TD1-

4

TCT2

5

TD2+ TD2-6MX2-

7

TCT3

8

TD3+

9

TD3-

10

TCT4

11

TD4+

12

TD4-

SUPERWORLD_SWG150401

C484

0.01U_0402_16V7K

MCT1

MX1+

MX1-

MCT2

MX2+

MCT3

MX3+

MX3-

MCT4

MX4+

MX4-

24 23 22

21 20 19

18 17 16

15 14 13

R394 3.6K_0402_5%R394 3.6K_0402_5% U21

U21

4

DO

3

DI

2

SK

1

CS

CAT93C46VI-GT3_SO8

CAT93C46VI-GT3_SO8 @

@

+LAN_VDD12

R401 75_0402_1%R401 75_0402_1%

5

GND

6

ORG

7

NC

8

VCC

+AVDD33

0.1U_0402_16V4Z

PVT-C475 and C455, change to MLCC for cost problem.

RJ45_MIDI3RJ45_MIDI3+

RJ45_MIDI2RJ45_MIDI2+

RJ45_MIDI1RJ45_MIDI1+

RJ45_MIDI0RJ45_MIDI0+

+3V_LAN

2

1

0.1U_0402_16V4Z

+LAN_CTRL18

C465

0.1U_0402_16V4Z

Close to Pin2 & pin59

+VDDSR

C474

C454

C454 @

@

1

2

+3V_LAN

4.7uH choke

4.7UH_1008HC-472EJFS-A_5%_1008

4.7UH_1008HC-472EJFS-A_5%_1008 L18

L18

1 2

Close to Pin1

C455

22U_0805_6.3V6M

+3V_LAN

2

C466

0.1U_0402_16V4Z

1

+3V_LAN

L21

L21 0_0603_5%

0_0603_5%

1

C475

C475 22U_0805_6.3V6M

22U_0805_6.3V6M

2

1

C457

2

0.1U_0402_16V4Z

LAN_ACTIVITY#

68P_0402_50V8J

LAN_LINK#

68P_0402_50V8J

2

0.1U_0402_16V4Z

1

2

C469

0.1U_0402_16V4Z

1

+3V_LAN

2

C453

0.1U_0402_16V4Z

1

C462

2

0.1U_0402_16V4Z

1

2

C470

0.1U_0402_16V4Z

1

C463

Close to Pin16,37,46,53

2

C450

0.1U_0402_16V4Z

1

+LAN_VDD12

0.1U_0402_16V4Z

2

1

C459

0.1U_0402_16V4Z

2

1

Bead for 8111C 300mA

L19 0_0805_5%L19 0_0805_5%

0.1U_0402_16V4Z

2

0.1U_0402_16V4Z

1

2

C467

0.1U_0402_16V4Z

1

C451

0.1U_0402_16V4Z

+LAN_EVDD12

C456

2

C460

0.1U_0402_16V4Z

1

2

C468

0.1U_0402_16V4Z

1

2

1

2

1

C461

C452

0.1U_0402_16V4Z

C458

0.1U_0402_16V4Z

LAN Conn.

EVT2- Change JP26, RJ45 connector type. DVT2- Re-Layout JP26 for LAN signal for wrong symbol.

JP26

@JP26

R400

12

300_0402_5%

+3V_LAN

1000P_1808_3KV7K

300_0402_5%

RJ45_MIDI3RJ45_MIDI3+ RJ45_MIDI1RJ45_MIDI2RJ45_MIDI2+

RJ45_MIDI1+

RJ45_MIDI0-

RJ45_MIDI0+

R403

12

300_0402_5%

1

C476

2

1

C477

2

RJ45_GND LANGND

C478

1 2

@

14

YELLOW LED-

13

YELLOW LED+

8

PR4-

7

PR4+

6

PR2-

5

PR3-

4

PR3+

3

PR2+

2

PR1-

1

PR1+

12

GREEN LED-

11

GREEN LED+

10

DETECT PIN

9

DETECT PIN

FOX_JM3611A-R1125-7F

1

C479

0.1U_0402_16V4Z

2

1

C480

4.7U_0603_6.3V6K

2

0.1U_0402_16V4Z

1

2

C471

1

15

GND

16

GND

+LAN_VDD12

C464

2

1

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2008/10/1

3

Compal Secret Data

Deciphered Date

2009/10/1

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

SCHEMATICS,M/B A4161

401562

Monday, February 23, 2009

1

of

28 48

of

28 48

of

28 48

G

A

DVT2-ME shift left 1mm.

AOCR/B LS-4164P

PCIE_ITX_C_5IN1RX_N6<20>

4 4

EVT2- Move Audio Codec VDDI/O power from AOCR/B to M/B.

+3VS

+1.5VS

3 3

20mil

FBMA-L11-160808-800LMT_0603

MDC 1.5 Conn.

CLK_5IN1<16>

PCIE_IRX_C_5IN1TX_P6<20>

AZ_SYNC_HD<21>

AZ_SDIN0_HD<21>

SPK_SEL<22>

EAPD<32>

LID_SW#<32> 5IN1_LED <34>

PLT_RST#<8,17,20,26..28,32,33>

R1016

0_0603_5%

NIHDMI@

L44

12

IHDMI@

+3VALW

+5VS

+3VS

+5VALW

12

SPKR+

+1.5VS_HD

+MDC

1

C796

0.1U_0402_16V4Z

2

MDC@

PVT-Remove Pin1 GND for shortage issue.

P-TWO_196027-50041

54

GND

52

GND

50

48

46

44

42

40

38

36

34

32

30

28

26

24

22

20

18

16

14

12

10

8

6

4

2

@ JP14

@

+3V_SB

1

C756

C756 1000P_0402_50V7K

1000P_0402_50V7K

2

MDC@

53

GND

51

GND

49

47

45

43

41

39

37

35

33

31

29

27

25

23

21

19

17

15

13

11

9

7

5

3

1

JP14

1

C755

0.1U_0402_16V4Z

2

MDC@

B

INT_MIC

SPKR-

SPKL-SPKL+

1

C757

4.7U_0603_6.3V6K

2

MDC@

CLK_5IN1# <16>

PCIE_ITX_C_5IN1RX_P6 <20>

PCIE_IRX_C_5IN1TX_N6 <20>

USB20_N2 <20>USB20_P2<20> AZ_BITCLK_HD <21> AZ_RST_HD# <21> AZ_SDOUT_HD <21>

USB_OC#2 <20>USB_EN#<25,32>

SB_SPKR <22>BEEP#<32>

SUBWOOFER <22>

EC_EAPD <32>

SUSP# <17,26,32,35,40>

FM_LINE_L <25>FM_LINE_R<25> +1.5VS_HD

+5VS

+3VS +5VALW

C

D

Right Main Speaker & SPKR-LED/B Connector

SPK_LED#

13

D

Q28

VR_LED<32,34>

2

G

2N7002_SOT23-3

S

Left Main Speaker & SPKR-LED/B Connector

EVT2- JP28, JP29 chage footprint to meet ME. Remove SPK ALC269 circuit.

JP28

@JP28

@

3

ACES_85205-0400

D19

D19 PJDLC05_SOT23-3

PJDLC05_SOT23-3

1

2

3

1

2

3

4

JP29

@JP29

@

1

2

3

4

ACES_85205-0400

D20

D20 PJDLC05_SOT23-3

PJDLC05_SOT23-3

+5VS

SPK_LED# SPKR+ SPKR-

2

EVT2- JP28, JP29 chage footprint to meet ME. Remove SPK ALC269 circuit.

+5VS

SPK_LED# SPKL+ SPKL-

E

DVT2-Change JP57 Layout location

JP57

@JP57

@

1

AZ_SDOUT_MD<21>

2 2

AZ_SYNC_MD<21>

AZ_SDIN1_MD<21>

AZ_SDIN1_MD_R

12

R625 33_0402_5% MDC@R625 33_0402_5% MDC@

3

5

7

9

11

13

GND

15

GND

17

GND

SANTA_210812-1

GND GND GND

2

4

6

8

10

12

14 16 18

+MDC

R466 0_0603_5%NIHDMI@R466 0_0603_5%NIHDMI@

1 2

R465 0_0603_5%IHDMI@R465 0_0603_5%IHDMI@

R624

R624 10_0402_5%

10_0402_5% @

@

1 2 1

C754

C754 10P_0402_50V8J

10P_0402_50V8J @

@

2

AZ_BITCLK_MD <21>AZ_RST_MD#<21>

1 2

+3V_SB +VCCSUS1_5_ICH_INT +3V_SB

DVT2-Change JP33 Layout footprint.

JP33

@ JP33

@

1

2

3

GND

4

GND

ACES_85204-0200L

1 1

EMI

A

INT_MIC

2

3

D5

PJDLC05_SOT23-3

1

@D5

@

Security Classification

2008/10/1 2009/10/1

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2008/10/1 2009/10/1

C

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

B

Date: Sheet

D

Date: Sheet

SCHEMATICS,M/B A4161

401562 G

Monday, February 23, 2009

E

29 48

of

A

+3VS +3VS_TM

L35

TV@L35

TV@

22U_0805_6.3V6M

L36

TV@L36

TV@

22U_0805_6.3V6M

1 2

R448 0_0603_5%TV@R448 0_0603_5%TV@

1 2

R449 0_0603_5%TV@R449 0_0603_5%TV@

12

1

C556

C556 TV@

TV@

2

12

C564

C564 TV@

TV@

FBMA-L11-201209-221LMA30T_0805

1 1

+5VS +5VS_TMA

FBMA-L11-201209-221LMA30T_0805

P-3V=1200mA

22U_0805_6.3V6M

1

C557

C558

TV@

2

0.1U_0402_16V4Z

22U_0805_6.3V6M

1

C565

C565 TV@

TV@

2

0.1U_0402_16V4Z

1

C559

C559 TV@

TV@

2

P-5V=1003mA

0.1U_0402_16V4Z

1

C566

C567

TV@

2

1

C560

C560 TV@

TV@

2

0.1U_0402_16V4Z

1

C568

C568 TV@

TV@

2

0.1U_0402_16V4Z

1

C561

C561 TV@

TV@

2

1

2

DGND TVGND

2 2

+5VALW

12

R452

R452 10K_0402_5%

10K_0402_5%

TV@

Q22A

BCPWON

12

2N7002DW-T/R7_SOT363-6

3 3

TV@ R475

TV@ 10K_0402_5%

10K_0402_5%

4 4

2N7002DW-T/R7_SOT363-6

R475

+5VS_L_BCAS

BCRSTM

XBCLKM

+5VS_L_BCAS

CPLGP1

61

TV@Q22A

TV@

2

DVT-Change U27, U28 from SA741080000 to SA007080380.

5

U27

TV@U27

1 2

10K_0402_5%

TV@

P

A

4

O

B

G

NC7ST08P5X_NL _SC70

3

5

U28

TV@U28

TV@

P

A

4

O

B

G

NC7ST08P5X_NL _SC70

3

R460

TV@R460

TV@

1 2

5

2N7002DW-T/R7_SOT363-6

A

R455

TV@R455

TV@

33K_0402_5%

C570

0.047U_0402_16V7K

B_R_BCRST

B_R_XBCCLK

R462

3

10K_0402_5%

Q22B

Q22B TV@

TV@

4

12

TV@C570

TV@

TV@ R456

TV@

2.2K_0402_5%

+5VS

G

2

1

2

12

R456

1 2

R457 100_0402_5%

TV@

1 2

R458 100_0402_5%

TV@

+5VS_L_BCAS

12

2

B

TV@R462

TV@

C

B-CAS Circuit

S

Q21

TV@

Q21

TV@

AO3413_SOT23-3

D

1 3

1

C571

TV@C571

TV@

4.7U_0603_6.3V6K

2

B_BCRST

B_XBCCLK

1 2

R461

TV@R461

31

E

TV@

10K_0402_5%

Q23

TV@

Q23

TV@

2SB1197K_SOT23-3

1 2

R463

TV@R463

TV@

1.5K_0402_5%

B

1

C562

C562 TV@

TV@

2

0.1U_0402_16V4Z

1

C569

TV@C569

TV@

4.7U_0603_6.3V6K

2

+5VS_L_BCAS

0.1U_0402_16V4Z

B

0.1U_0402_16V4Z

1

C563

C563 TV@

TV@

2

+5VS_BCAS

1

C572

TV@

2

JP35

@ JP35

@

11

GND

12

GND

ACES_85201-10051

BCIO

TU2 (Slave)

PCI_PIRQH#<20>

CLK_PCI_TV2<16>

PCI_REQ#2<20>

PCI_GNT#2<20>

C447

4.7P_0402_50V8C

C485

4.7P_0402_50V8C

EMI

CPLGP3

12

R474 10K_0402_5%TV@R474 10K_0402_5%TV@ R451 10K_0402_5%TV@R451 10K_0402_5%TV@ R453 10K_0402_5%TV@R453 10K_0402_5%TV@ R454 10K_0402_5%TV@R454 10K_0402_5%TV@

FBMA-L11-201209-221LMA30T_0805

1

C573 1U_0402_6.3V4Z

1U_0402_6.3V4Z

2

1

2

3

4

5

6

7

8

9

10

CPLGP2

12

CPLGP1

12

CPLGP0

12

L37

1 2

TV@C573

TV@

B_XBCCLK B_BCRST

R459 470_0402_5%TV@R459 470_0402_5%TV@

BCIO

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

12

@C447

@

12

@C485

@

+5VS_L_BCAS

TV@L37

TV@

12

Issued Date

C

PCI_AD[0..31]<20>

PCI_PIRQH#

CLK_PCI_TV2

PCI_REQ#2 PCI_PIRQG#

PCI_GNT#2

IDSL_TV2PCI_AD19

12

R450 100_0402_5%TV@R450 100_0402_5%TV@

CLK_PCI_TV1

12

R360

@R360

@

10_0402_5%

10_0402_5% R361

10_0402_5%

BCCDET

CLK_PCI_TV2

12

@R361

@

PCI_CBE#3<20>

PCI_CBE#2<20> PCI_IRDY#<20>

PM_CLKRUN#<22>

PCI_SERR#<20> PCI_PERR#<20>

PCI_CBE#1<20>

BCRSTM PCI_AD2

BCIO CPLGP1 BCCDET XBCLKM

BCPWON

+5VS_BCAS

2008/10/1 2009/10/1

C

+5VS

+3VS_TM +3VS_TM

+5VS_TMA +5VS_TMA

PCI_PIRQH# CLK_PCI_TV2 CLK_PCI_TV1 PCI_REQ#1 PCI_GNT#1 PCI_AD31

PCI_AD29 PCI_GNT#2 PCI_AD27

PCI_AD25 PCI_AD28 PCI_REQ#2 PCI_AD26

PCI_AD23 IDSL_TV1 PCI_AD21 PCI_AD22

PCI_AD19 PCI_AD20 PCI_AD17 PCI_AD18

PCI_AD14 PCI_AD15 PCI_AD12 PCI_AD11

PCI_AD10 PCI_AD8

PCI_AD7 PCI_AD5 PCI_AD4 PCI_AD3 PCI_AD0 PCI_AD1

CPLGP2 CPLGP0

Compal Secret Data

Deciphered Date

101 103 105 107 109 111 113 115 117 119 121 123

FOX_AS0B126-S60N-7F@

JP34

KEY KEY

112 334

556 778 9910 111112 131314 151516 171718 191920 212122 232324 252526 272728 292930 313132 333334 353536 373738 393940 414142 434344 454546 474748 494950 515152 535354 555556 575758 595960 616162 636364 656566 676768 696970 717172 737374 757576 777778 797980 818182 838384 858586 878788 898990 919192 939394 959596 979798 9999100 101 103 105 107 109 111 113 115 117 119 121 123

D

2 4

6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102

102

104

106

108

110

112

114

116

118

120

122

124

D

ECAGND

E

+5VS

TU1 Configration

12

R447 100_0402_5%TV@R447 100_0402_5%TV@ CLK_PCI_TV1 PCI_REQ#1

PCI_GNT#1

PCI_PIRQG#

IDSL_TV2

PCI_RST# <20>

PCI_AD30

PCI_AD24

PCI_AD16

PCI_AD13

PCI_AD9

PCI_AD6

CPLGP3

Title

Size Document Number Rev

Date: Sheet

PCI_PAR <20>

PCI_FRAME# <20> PCI_TRDY# <20> PCI_STOP# <20>

PCI_DEVSEL# <20>

PCI_CBE#0 <20>

ECAGND <27,32> TV_TMPTM1 <32> TV_TMPTM2 <32>

Compal Electronics, Inc.

SCHEMATICS,M/B A4161

401562 G

CLK_PCI_TV1 <16> PCI_PIRQG# <20> PCI_REQ#1 <20> PCI_GNT#1 <20>

E

PCI_AD18IDSL_TV1

of

30 48Monday, February 23, 2009

of

30 48Monday, February 23, 2009

of

30 48Monday, February 23, 2009

A

DVT- Modify IRTX circuit for votage drop problem. Add C601 for U35, for Layout placement update for DFB

B

C

D

E

EVT2- LEARNIR change to LEARNIR#

+3VS

R68

@ R68

@

2 1

R85

@ R85

@

C601

2 1

+5VS

12

R70

IRBL@R70

IRBL@

0_0402_5%

12

5

U33

IRBL@U33

IRBL@

P

B A

+3VS

12

B A

IRTX0

4

Y

G

3

PVT-Modify EC_BD0/EC_BD1 to EC_BD0#/EC_BD1#

+5VS

12

R120

IRBL@R120

IRBL@

0_0402_5%

5

U35

IRBL@U35

IRBL@

P

IRTX1

4

Y

G

3

Modify BD0/BD1 to BD0#/BD1#

DVT2- Reserve Q3/Q8/Q136/R1013/R1037 for IR Blaster test

DVT- Delete R508 and R510, duplicate with R276 and R278. R736 and R737, change from 100 to 33.

IRTX1

R736 100_0402_5%IRBL@R736 100_0402_5%IRBL@

IRTX0

R737 100_0402_5%IRBL@R737 100_0402_5%IRBL@

12 12

EC_BD0#<20> EC_BD1#<20>

IR_R_TX1 IR_R_TX0

JP27

1 3 5 7 9

11

ACES_85203-06021@

2

1

2

4

3

4

6

5

6

8

7

8

10

9

10

12

11

12

PVT-Delete SMSC IR Bluster solution Delete R738,R739, R748,R749

1 1

EC_IRTX0<32>

IRBL@ R503

IRBL@ 10K_0402_5%

10K_0402_5%

2 2

EC_IRTX1<32>

IRBL@ R507

IRBL@ 10K_0402_5%

10K_0402_5%

+3VS

IRBL@

IRBL@ R129

R129

10K_0402_5%

IRBL@

IRBL@ Q131A

Q131A

2N7002DW-T/R7_SOT363-6

1 2

R503

IRBL@

IRBL@ R131

R131

10K_0402_5%

Q131B

IRBL@Q131B

IRBL@

4

2N7002DW-T/R7_SOT363-6

1 2

R507

12

2

R150

@R150

@

0_0402_5%

12

5

R149

@R149

@

0_0402_5%

61

3

+5VS

+5VS+3VS

12

R130

12

R148

IRBL@R130

IRBL@

10K_0402_5%

IRBL@ R60

IRBL@ 10K_0402_5%

10K_0402_5%

IRBL@R148

IRBL@

10K_0402_5%

IRBL@ R65

IRBL@ 10K_0402_5%

10K_0402_5%

R65

R60

+5VS

12

+3VS

12

R58 10K_0402_5%

10K_0402_5%

12

R63 10K_0402_5%

10K_0402_5%

@R63

@

@R58

@

0_0402_5%

C600

IRBL@C600

IRBL@

0.1U_0402_16V4Z

NC7SZ08P5X_NL_SC70-5

0_0402_5%

IRBL@ C601

IRBL@

0.1U_0402_16V4Z

NC7SZ08P5X_NL_SC70-5

3 3

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2008/10/1

C

Compal Secret Data

Deciphered Date

2009/10/1

D

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

SCHEMATICS,M/B A4161

401562

Monday, February 23, 2009

E

of

31 48

of

31 48

of

31 48

G

5

0.1U_0402_16V4Z

0.1U_0402_16V4Z C604

C603

MCH_TSATN_EC#<8>

PWR_SUSP_LED<34>

NUM_LED#<33>

WLAN_WAKE#<26> FAN_SPEED1<4>

TMA_CLKDWN#<27>

EC_SMB_CK1<19,34,37> EC_SMB_DA1<19,34,37> EC_SMB_CK2<4,17> EC_SMB_DA2<4,17>

TMA_ALERT#<27>

PM_SLP_S3#<22>

ON/OFFBTN#<34>

LPC_FRAME#<21,33>

EC_SMI#<22>

LEARNIR#<34>

CEC_INT#<19>

EC_IRTX1<31>

UWB_OFF#<26>

C604

1

2

EC_GA20<21>

EC_KBRST#<21>

LPC_AD3<21,33> LPC_AD2<21,33> LPC_AD1<21,33> LPC_AD0<21,33>

CLK_PCI_EC<16>

PLT_RST#<8,17,20,26..29,33>

EC_SCI#<22>

WL_BT_LED#<34>

KSI[0..7] KSO[0..15]

T12PAD T12PAD

E51_TXD<34>

SERIRQ<22>

0.1U_0402_16V4Z

1

2

0.1U_0402_16V4Z

D D

@

10_0402_5%

@

22P_0402_50V8J

+3VL

+5VL

C C

B B

+3VS

PM_SLP_S5#<22> PM_SLP_S4#<22>

PVT-Remove IR_WAKE#/EC_IR# and R745/R744 for delete SMSC solution.

DVT- Change MCH_TSATN_EC# from pin76 to pin18

EVT2- LEARNIR change to LEARNIR# EC_IR change to EC_IR#

+5VS

EVT2- EC input signal pull high. CEC_INT# add by A51.

CLK_PCI_EC

12

R509

1

C612

2

R512

R512 47K_0402_5%

47K_0402_5%

C613 0.1U_0402_16V4ZC613 0.1U_0402_16V4Z

1 2

R1025 4.7K_0402_5%R1025 4.7K_0402_5%

1 2

R1026 4.7K_0402_5%R1026 4.7K_0402_5%

1 2

R1027 4.7K_0402_5%R1027 4.7K_0402_5%

1 2

R1028 4.7K_0402_5%R1028 4.7K_0402_5%

EVT2- EC input signal pull high. PVT-Remove R1014 TMA@ for input pin.

1 2

R1014 100K_0402_5%R1014 100K_0402_5%

0.1U_0402_16V4Z

1 2

R1015 100K_0402_5%R1015 100K_0402_5%

12

C429

1 2

EC_SMB_CK1 EC_SMB_DA1 EC_SMB_CK2 EC_SMB_DA2

+3VALW

2

B

1

A

ECRST#

TMA_ALERT#

5

P

Y

G

U23NC7SZ08P5X_NL_SC70-5 U23NC7SZ08P5X_NL_SC70-5

3

LEARNIR#

4

SLP_S5#

KSI[0..7]<33>

KSO[0..15]<33>

DVT- Change CEC_INT# from pin31 to pin17

C614

DVT- Change CEC_INT# from pin31 to pin17

A A

and add R1033 for INT#

1 2

+5VL

R1033 100K_0402_5%R1033 100K_0402_5%

CEC_INT#

5

15P_0402_50V8J

32.768KHZ_12.5PF_1TJS125BJ4A421P

1

C605

2

1

Y2

2

4

0.1U_0402_16V4Z

1

C606

2

1000P_0402_50V7K

CLK_PCI_EC ECRST#

KSI0 KSI1 KSI2 KSI3 KSI4 KSI5 KSI6

KSI7 KSO0 KSO1 KSO2 KSO3 KSO4 KSO5 KSO6 KSO7 KSO8 KSO9

KSO10 KSO11 KSO12 KSO13 KSO14 KSO15

TMA_ALERT#

EC_SMB_CK1 EC_SMB_DA1 EC_SMB_CK2 EC_SMB_DA2

SLP_S5#

LEARNIR#

CEC_INT#

CIR_IN E51_TXD

E51_TXD

CRY1 CRY2

R519

1 2

20M_0603_5%@

4

1

IN

OUT

NC3NC

2

4

1000P_0402_50V7K

2

C607

1

U37

1

GA20/GPIO00

2

KBRST#/GPIO01

3

SERIRQ#

4

LFRAME#

5

LAD3

7

LAD2

8

LAD1

10

LAD0

12

PCICLK

13

PCIRST#/GPIO05

37

ECRST#

20

SCI#/GPIO0E

38

CLKRUN#/GPIO1D

55

KSI0/GPIO30

56

KSI1/GPIO31

57

KSI2/GPIO32

58

KSI3/GPIO33

59

KSI4/GPIO34

60

KSI5/GPIO35

61

KSI6/GPIO36

62

KSI7/GPIO37

39

KSO0/GPIO20

40

KSO1/GPIO21

41

KSO2/GPIO22

42

KSO3/GPIO23

43

KSO4/GPIO24

44

KSO5/GPIO25

45

KSO6/GPIO26

46

KSO7/GPIO27

47

KSO8/GPIO28

48

KSO9/GPIO29

49

KSO10/GPIO2A

50

KSO11/GPIO2B

51

KSO12/GPIO2C

52

KSO13/GPIO2D

53

KSO14/GPIO2E

54

KSO15/GPIO2F

81

KSO16/GPIO48

82

KSO17/GPIO49

77

SCL1/GPIO44

78

SDA1/GPIO45

79

SCL2/GPIO46

80

SDA2/GPIO47

6

PM_SLP_S3#/GPIO04

14

PM_SLP_S5#/GPIO07

15

EC_SMI#/GPIO08

16

LID_SW#/GPIO0A

17

SUSP#/GPIO0B

18

PBTN_OUT#/GPIO0C

19

EC_PME#/GPIO0D

25

EC_THERM#/GPIO11

28

FAN_SPEED1/FANFB1/GPIO14

29

FANFB2/GPIO15

30

EC_TX/GPIO16

31

EC_RX/GPIO17

32

ON_OFF/GPIO18

34

PWR_LED#/GPIO19

36

NUMLED#/GPIO1A

122

XCLK1

123

XCLK0

CRY2CRY1

1

C615

2

15P_0402_50V8J

+3VL

2

C608

1

LPC & MISC

9

22

33

96

111

125

VCC

PWM Output

AD Input

DA Output

PS2 Interface

Int. K/B

Int. K/B Matrix

Matrix

SPI Device Interface

SPI Flash ROM

GPIO

SM Bus

GPO

GPIO

GPI

GND

11

24

35

94

113

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

+3VL

C609

ECAGND

1 2

0.1U_0402_16V4Z

67

AVCC

INVT_PWM/PWM1/GPIO0F

BEEP#/PWM2/GPIO10

FANPWM1/GPIO12

ACOFF/FANPWM2/GPIO13

BATT_TEMP/AD0/GPIO38

BATT_OVP/AD1/GPIO39

ADP_I/AD2/GPIO3A

AD3/GPIO3B

AD4/GPIO42

SELIO2#/AD5/GPIO43

DAC_BRIG/DA0/GPIO3C

EN_DFAN1/DA1/GPIO3D

IREF/DA2/GPIO3E

DA3/GPIO3F

PSCLK1/GPIO4A PSDAT1/GPIO4B PSCLK2/GPIO4C

PSDAT2/GPIO4D

TP_CLK/PSCLK3/GPIO4E

TP_DATA/PSDAT3/GPIO4F

SDICS#/GPXOA00 SDICLK/GPXOA01

SDIDO/GPXOA02

SDIDI/GPXID0

SPIDI/RD#

SPIDO/WR#

SPICLK/GPIO58

SPICS#

CIR_RX/GPIO40

CIR_RLC_TX/GPIO41

FSTCHG/SELIO#/GPIO50

BATT_CHGI_LED#/GPIO52

CAPS_LED#/GPIO53

BATT_LOW_LED#/GPIO54

SUSP_LED#/GPIO55

SYSON/GPIO56

VR_ON/XCLK32K/GPIO57

AC_IN/GPIO59

EC_RSMRST#/GPXO03 EC_LID_OUT#/GPXO04

EC_ON/GPXO05

EC_SWI#/GPXO06

ICH_PWROK/GPXO06

BKOFF#/GPXO08

WL_OFF#/GPXO09

GPXO10 GPXO11

PM_SLP_S4#/GPXID1

ENBKL/GPXID2

GPXID3 GPXID4 GPXID5 GPXID6 GPXID7

V18R

AGND

KB926QFA1_LQFP128_14X14

69

ECAGND

2008/10/1 2009/10/1

3

L38

12

0_0603_5%

21 23 26 27

BATT_TEMPA

63

BATT_OVP

64

TV_TMPTM2

65

TV_TMPTM1

66

KILL_SW#

75

TMA_TMP

76

68 70 71 72

83 84

CAP_INT#

85 86

TP_CLK

87

TP_DATA

88

VGATE

97 98 99

LID_SW#

109

119 120

CLK_ECSPI_R

126 128

CIR_IN

73 74 89 90 91 92 93 95 121 127

100 101 102 103 104 105 106 107 108

110 112 114 115 116 117 118

124

EC_ACIN

+EC_V18R

New add for KB926 C0

Compal Secret Data

Deciphered Date

ENBKL

C689

4.7U_0603_6.3V6K

INVT_PWM <17> BEEP# <29>

VR_LED <29,34> ACOFF <38>

BATT_TEMPA <37>

BATT_OVP <38> TV_TMPTM2 <30> TV_TMPTM1 <30> KILL_SW# <26,34> TMA_TMP <27>

DAC_BRIG <17>

EN_DFAN1 <4>

IREF <38> CHGVADJ <38>

EC_EAPD <29> USB_EN# <25,29> CAP_INT# <34>

ENCODER_PULSE <34>

TP_CLK <34>

TP_DATA <34>

VGATE <8,22,42>

WOL_EN <35>

SBPWR_EN <35> LID_SW# <29>

EC_SI_SPI_SO <33>

EC_SO_SPI_SI <33>

SPI_CS# <33>

CIR_IN <34>

EC_IRTX0 <31>

FSTCHG <38> BATT_FULL_LED# <34> CAPS_LED# <33> BATT_CHG_LOW_LED# <34>

CURS_LED# <33>

SYSON <26,34,35,41>

VR_ON <42>

EC_RSMRST# <22> EC_LID_OUT# <22>

EC_ON <34>

EC_SWI# <22,26> PM_PWROK <8,22> BKOFF# <17>

WL_OFF# <26>

HDMI_HPD_R <19>

STB_WLAN <35>

ENCODER_DIR <34>

EAPD <29> EC_THERM# <22> SUSP# <17,26,29,35,40> PBTN_OUT# <22> LOM_WAKE# <28>

2

EVT2- Add R1029 and R1030 for A51 PCI TV request.

TV_TMPTM2

R1029 10K_0402_1%R1029 10K_0402_1%

TV_TMPTM1

R1030 10K_0402_1%R1030 10K_0402_1%

1 2 1 2

+3VS

DVT- Add TMA_TMP in U37.76 for TMA Thermistor and add R1034 for pull-up.

TMA_TMP

1 2

R1034 10K_0402_1%R1034 10K_0402_1%

EVT2- Move PU from LS4168P to MB

KILL_SW#

BATT_OVP EC_ACIN

TP_CLK TP_DATA

12

R11 100K_0402_5%R11 100K_0402_5%

1 2

C610 100P_0402_25V8KC610 100P_0402_25V8K

1 2

C575 100P_0402_25V8KC575 100P_0402_25V8K

1 2

C576 100P_0402_25V8KC576 100P_0402_25V8K

1 2

R5144.7K_0402_5% R5144.7K_0402_5%

1 2

R5154.7K_0402_5% R5154.7K_0402_5%

+3VS

+3VALW

ECAGNDBATT_TEMPA

+5VS

EVT2- Move PU from LS430CP to MB

CAP_INT#

EVT2- Move PU from LS4164P to MB

LID_SW#

VGATE

EVT2- Add R740 for EMI DVT-Change R470 as 15 Ohm for EMI solution.

1 2

R740 15_0402_5%R740 15_0402_5%

CLK_ECSPI <33>

STRAP: Reserve for KB926 B0

CIR_IN

PVT-Remove R735/R741/R744/R745/R742, for SMSC IR Bluster remove.

+3VALW

R517

12

100K_0402_5%

EC_ACIN

2 1

D22

CH751H-40PT_SOD323-2

DVT-Add D22 for AC-IN leakage issue

EVT2- Add HDP to EC

R520 0_0402_5%PM@R520 0_0402_5%PM@

ENBKL

Title

Size Document Number Rev

Custom

Date: Sheet

2

Date: Sheet

R521 0_0402_5%GM@R521 0_0402_5%GM@

SCHEMATICS,M/B A4161

Monday, February 23, 2009

12

1 2

R522 100K_0402_5%R522 100K_0402_5%

Compal,Electronics,Lnc.

401562 G

1

ECAGND <27,30>

R516 4.7K_0402_5%@R516 4.7K_0402_5%@

R511 100K_0402_5%R511 100K_0402_5%

ACIN <17,22,34,36,38>

VGA_ENBKL <17>

UMA_ENBKL <10>

1

12

R10100K_0402_5% R10100K_0402_5%

12

R9100K_0402_5% R9100K_0402_5%

12

of

32 48

of

32 48

of

32 48

+5VL

+3VALW

+5VL

SPI Flash (16Mb*1)

R525

MP@R525

MP@

0_0402_5%

EC_SI_SPI_SO<32>

1 2

External Flash ROM

SPI_CS#<32>

SB_INT_FLASH_SEL#<22>

SPI_CS# EC_SI_SPI_SO

SI/O Debug

LPC Debug Port

CLK_PCI_DDR

R539

22_0402_5%

22_0402_5% @

@

1 2 2

C647

C647 22P_0402_50V8J

22P_0402_50V8J

1

@

INT_SPI_CS#SPI_CS# EC_SI_SPI_SO

+3VL

JP38

112 334 556 778

E&T_2941-G08N-00E~D

TEST@

U38

1

CS#

2 3 4

VCC

SO

HOLD#

WP#

SCLK

GND

MX25L1605AM2C-12G_SO8

2 4 6 8

SI

INT_FLASH_EN# CLK_ECSPI EC_SO_SPI_SI

EVT2- Delete EC debug port to reduce space for Layout. Change Debug PAD to 10pin connector.

8 7 6 5

CLK_PCI_DDR<16>

LPC_FRAME#<21,32>

+3VL

C617

1 2

0.1U_0402_16V4Z

CLK_ECSPI EC_SO_SPI_SI

+3VL

+3VS

LPC_AD0<21,32> LPC_AD1<21,32> LPC_AD2<21,32> LPC_AD3<21,32>

PLT_RST#<8,17,20,26..29,32>

EVT2- Remove 24C16 circuits, U39/C616/R523/R524 DVT-Add R410 w/33Ohm and R489 w/22P in BOM for EMI.

CLK_ECSPI

EMI

+3VL

5

U40

B

4

Vcc

Y

A

G

NC7SZ32P5X_NL_SC70-5

3

TEST@

INT_SPI_CS#

CLK_ECSPI <32> EC_SO_SPI_SI <32>

R529

1 2

22_0402_5%

22_0402_5% TEST@

TEST@

TP CONN.

DVT2- Remove JP39, TP/B connector, and C621, becasue combined in LED/B connector

JP4

1

CLK_PCI_DDR LPC_AD0

LPC_AD1 LPC_AD2 LPC_AD3 LPC_FRAME#

PLT_RST#

1

2

3

4

5

6

7

8

9

10

11

GND

12

GND

ACES_85201-1005N

1 2

R410 33_0402_5%R410 33_0402_5%

TEST@

C618 0.1U_0402_16V4Z

12

INT_FLASH_EN#

2

SPI_CS#

1

C489 22P_0402_50V8JC489 22P_0402_50V8J

TEST@

R530 100K_0402_5%

1 2

SB_INT_FLASH_SEL

JP40

GND69GND

67

65 63 61 59 57 55 53 51 49 47 45 43 41 39 37 35 33 31 29 27 25 23 21 19 17 15 13 11

QUASA_CA0323-034B00

QUASA_CA0323-034B00 @

@

68

65

66

63

64

61

62

59

60

57

58

55

56

53

54

51

52

49

50

47

48

45

46

43

44

41

42

39

40

37

38

35

36

33

34

31

32

29

30

27

28

25

26

23

24

21

22

19

20

17

18

15

16

13

14

11

12

9

10

7

5 3 1

8

5

6

3

4

1

2

H

L

SPI#

EXT_CS#

External Flash ROM

STOP RUN

L

H

L

KEYBOARD CONN.

70

68

66

64

62

60

58

56

54

52

50

48

46

44

42

40

38

36

34

32

30

28

26

24

22

20

18

16

14

12

10

8

6

4

2

R389

R409

R409 KSO2 KSO1 KSO0 KSO4 KSO3 KSO5

KSO14

KSO6 KSO7

KSO13

KSO8 KSO9

KSO10 KSO11 KSO12 KSO15

KSI7 KSI2 KSI3 KSI4 KSI0 KSI5 KSI6 KSI1

CAPS_LED# CURS_LED# NUM_LED#

KSI[0..7]

KSO[0..15]

1 2

R417 300_0402_5%R417 300_0402_5%

KSI[0..7] <32> KSO[0..15] <32>

300_0402_5%

12

+3VS

+3VS CAPS_LED# <32> CURS_LED# <32> NUM_LED# <32>

SB_INT_FLASH_SEL

L

H

STOP

SPI#

INT_SPI_CS#

External Flash ROM

RUN

H

L

STOP

DVT- Change Keyboard capacitors to mount components for EMI.

KSO2 KSO1 KSO0 KSO4 KSO3 KSO5 KSO14 KSO6 KSO7 KSO13 KSO8 KSO9 KSO10 KSO11 KSO12 KSO15

KSI7 KSI2 KSI3 KSI4 KSI0 KSI5 KSI6 KSI1

CAPS_LED#

CURS_LED#

NUM_LED#

1 2

C619 100P_0402_25V8KC619 100P_0402_25V8K

1 2

C620 100P_0402_25V8KC620 100P_0402_25V8K

1 2

C622 100P_0402_25V8KC622 100P_0402_25V8K

1 2

C623 100P_0402_25V8KC623 100P_0402_25V8K

1 2

C624 100P_0402_25V8KC624 100P_0402_25V8K

1 2

C625 100P_0402_25V8KC625 100P_0402_25V8K

1 2

C626 100P_0402_25V8KC626 100P_0402_25V8K

1 2

C627 100P_0402_25V8KC627 100P_0402_25V8K

1 2

C628 100P_0402_25V8KC628 100P_0402_25V8K

1 2

C629 100P_0402_25V8KC629 100P_0402_25V8K

1 2

C630 100P_0402_25V8KC630 100P_0402_25V8K

1 2

C631 100P_0402_25V8KC631 100P_0402_25V8K

1 2

C632 100P_0402_25V8KC632 100P_0402_25V8K

1 2

C633 100P_0402_25V8KC633 100P_0402_25V8K

1 2

C634 100P_0402_25V8KC634 100P_0402_25V8K

1 2

C635 100P_0402_25V8KC635 100P_0402_25V8K

1 2

C636 100P_0402_25V8KC636 100P_0402_25V8K

1 2

C637 100P_0402_25V8KC637 100P_0402_25V8K

1 2

C638 100P_0402_25V8KC638 100P_0402_25V8K

1 2

C639 100P_0402_25V8KC639 100P_0402_25V8K

1 2

C640 100P_0402_25V8KC640 100P_0402_25V8K

1 2

C641 100P_0402_25V8KC641 100P_0402_25V8K

1 2

C642 100P_0402_25V8KC642 100P_0402_25V8K

1 2

C643 100P_0402_25V8KC643 100P_0402_25V8K

1 2

C644 100P_0402_25V8KC644 100P_0402_25V8K

1 2

C645 100P_0402_25V8KC645 100P_0402_25V8K

1 2

C646 100P_0402_25V8KC646 100P_0402_25V8K

L

HINT_FLASH_EN#

H

L

H

STOP

Security Classification

2008/10/1 2009/10/1

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2008/10/1 2009/10/1

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

B

Date: Sheet

SCHEMATICS,M/B A4161

401562 G

Monday, February 23, 2009

of

33 48

of

33 48

of

33 48

5

FUN/B Connector

JP53

@JP53

@

+5VALW

+5VL

@C262

@

CAP_INT#<32>

1

10P_0402_50V8J

2

C263

@ C263

@

D D

C C

EC_SMB_DA1<19,32,37> EC_SMB_CK1<19,32,37>

C262

10P_0402_50V8J

EVT2- EMI request to add C262/C263 near FUN/B side. Pin1 change power rail from +5VL to +5VALW

1 3 5 7 9

11

ACES_85203-06021

2

1

2

4

3

4

6

5

6

8

7

8

10

9

10

12

11

12

VR/B Control

DVT2- Remove JP51, VR/B connector, becasue combined in LED/B connector.

4

LED/B LS4168P Connector Power Button/ PWR/B

EVT2- LEARNIR change to LEARNIR# DVT2- Change JP52, LED/B connector from 24pin to 30pin, to combined VR/B and TP/B connector in LED/B.

+5VL +5VS

KILL_SW#<26,32>

ACIN<17,22,32,36,38>

SYSON<26,32,35,41>

PWR_SUSP_LED<32>

BATT_CHG_LOW_LED#<32>

BATT_FULL_LED#<32>

SATA_LED#<21> WL_BT_LED#<32>

5IN1_LED<29>

VR_LED<29,32>

LED_WWAN#<26>

CIR_IN<32>

LEARNIR#<32>

REC_LED<21> ENCODER_DIR<32> ENCODER_PULSE<32>

CIR_EN#<22>

TP_CLK<32>

TP_DATA<32>

E51_TXD<32> SB_TVLED<22>

EVT2- Add R12/D7/Q3 for test checking. DVT- Remove DC-IN test circuits, delete R12, D7 and Q3.

1 2

R153 0_0402_5%@R153 0_0402_5%@

1 2

R154 0_0402_5%TV@R154 0_0402_5%TV@

+3VS

+5VALW

PWR_SUSP_LED

VR_LED

TV_LED

1 2

R56

TV@R56

TV@

100K_0402_5%

DVT2-VR/B Add +3VS/ ENCODER_DIR/ ENCORDER_PULSE Share w/ LED/B +5VS/ VR_LED

DVT2-TP/B Add +5VS/ TP_CLK/ TP_DATA Share w/ LED/B SW_L/SW_R

TV_LED

3

JP52

@JP52

@

1

3

5

7

9

11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59

ACES_85203-3002L

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

2

4

6

8

10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60

2

DVT2-Remove SW4 becasue no place for it.

+3VL

R540

R540 100K_0402_5%

100K_0402_5%

1 2

ON/OFFBTN#

+5VALW

47K

Q2

10K

2

DTA114YKAT146_SOT23-3

1 3

+5VS

PVT-add J9 to make PWR LED behavior without Fade-In/Fade-Out.

47K

Q9

10K

2

DTA114YKAT146_SOT23-3

1 3

1 2

JUMP_43X39

SW5

SMT1-05-A_4P

5

6

TEST@

SW1

SMT1-05-A_4P

5

6

TEST@

J9

@

3 4

2

1

DVT2-Change JP55 Layout location

ACES_85203-04021

EC_ON<32>

R542

10K_0402_5%

2

Q7A

6 1

2N7002DW-T/R7_SOT363-6

R1012 22_0402_5%R1012 22_0402_5%

Q7B

3

2N7002DW-T/R7_SOT363-6

1 2

R1011 22_0402_5%R1011 22_0402_5%

PWR_SUSP_LED

1 2

5

4

PWR_LED_R

1

JP55

@JP55

@

2

112

4

334

5

665

7

887

13

D

2

G

Q27

S

2N7002_SOT23-3

1 2

SYSON

PWR_SUSP_LED_R

VR_LED

PWR_LED_R

ON/OFFBTN#

PWR_SUSP_LED_R

51_ON# <36>ON/OFFBTN# <32>

PCB Fedical Mark PAD

B B

FD1@FD1

FD2@FD2

@

1

FD4@FD4

FD3@FD3

@

1

EMI Shielding Clip PADs

EVT2- Delete EMI clip PAD M2.

M1

EMI_80X100

@

1

A A

5

Screw Hole

DVT- Change H2, H3, H4, H30.

CPU support screw

H30

H_4P3

@

H30

H2

H_4P3

@

1

VGA support screw

DVT- Change screw size from 3.75 to 3.8

H23

H24

1

H_3P8

@

H24

H_3P8

@

FAN module screw

DVT- New add in EVT2 for FAN Module.

H31

H_2P8

@

1

4

H3

H_4P2

@

H_3P8

@

1

H8

1

Slot2 Full

EVT2- Separate Slot2&Slot3 screw hole. DVT- Change screw size from 1.15 to 1.2 DVT2- Change H9 and H10 from 1.2 to 3.3

H4

H_4P2X4P3

@

1

H_3P3

@

H5

H9

H_3P3

@

1

Slot1 Full/ Slot3 Full support screw

H_3P8

@

H7

DVT- Change screw size from 3.25 to 3.3

H11

H12

H_3P3

@

Issued Date

@

1

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

H11

H_3P3

@

1

2008/10/1 2009/10/1

3

Slot3 Helf support screw

EVT2- Add H5/H6 for Slot3 helf-module for movement issue. DVT- Change screw size from 1.15 to 1.2 DVT2- Change H5 and H6 from 1.2 to 3.3

H_3P3

@

H6

H_3P3

@

1

MDC/FM Module support Other screw hole

DVT- Change screw size from 1.15 to 1.2 DVT2- Change H13 and H14 from 1.2 to 3.3

H14

H_3P3

@

Compal Secret Data

Deciphered Date

H13

H_3P3

@

1

H10

2

NPDH holes

H28

H_3P0N

1

H_4P0X3P0N

@

1

EVT2- Add H32 and H33 for 2nd HDD breaket hole.

H29

@

1

H_2P3N

@

H32

H33

H_2P3N

@

1

EVT2- Change H21 to H_2P8

H17

H16

H15

H_3P0

@

H22

H_3P0

@

Title

Size Document Number Rev

Custom

Date: Sheet

H16

H_3P1

@

H_3P0

@

H25

1

@

H_5P2

@

H26

1

H_3P0

@

H_3P0

@

Compal,Electronics,Lnc.

SCHEMATICS,M/B A4161

401562 G

Monday, February 23, 2009

H18

H27

1

H_3P0

@

1

H19

H_3P0

@

1

34 48

H20

of

1

H_2P8

@

H21

1

A

B

C

D

E

+3VALW TO +3VS

+3VALW +3VS

Q37

8

S

D

7

S

D

6

S

D

5

G

1 1

D

AO4422_SO8

1

C663

2

4.7U_0603_6.3V6K

+3VALW TO +3V_SB

+1.5VS +0.9VS

1 2 13

D

2 2

3 3

4 4

S

DVT2- Change +0.9V to +0.9VS

R563

470_0805_5%

SUSP SUSP

2

G

Q46

Q46 2N7002_SOT23-3@

2N7002_SOT23-3@

SYSON<26,32,34,41>

10K_0402_5%

SUSP<41>

SUSP#<17,26,29,32,40>

10K_0402_5%

1 2 13

D

S

R572

R579

R564

470_0805_5%

2

G

Q47

Q47 2N7002_SOT23-3@

2N7002_SOT23-3@

1 2

2

G

SUSP

2

G

+5VL

R570

R570 10K_0402_5%

10K_0402_5% @

@

1 2 13

D

Q54

Q54 2N7002_SOT23-3

2N7002_SOT23-3

S

@

+5VL

R576

R576 10K_0402_5%

10K_0402_5%

1 2 13

D

Q59

Q59 2N7002_SOT23-3

2N7002_SOT23-3

S

1

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K C667

C667 STAR@

STAR@

2

+VSB

STAR@

R568 47K_0402_5%

12

2N7002DW-T/R7_SOT363-6

STAR@

+3VALW TO +3V_LAN

1

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K C677

C677 STAR@

STAR@

2

+VSB

R573

STAR@R573

STAR@ 47K_0402_5%

47K_0402_5%

2N7002DW-T/R7_SOT363-6

STAR@

+3VALW TO +3V_WLAN

1

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K C684

C684 STAR@

STAR@

2

+VSB

R582

STAR@R582

STAR@ 47K_0402_5%

47K_0402_5%

STB_WLAN#

2N7002DW-T/R7_SOT363-6

1

C657

1 2

2

3 4

1U_0402_6.3V4Z

1

C665

2

Q71B

2N7002DW-T/R7_SOT363-6

0.01U_0402_25V7K

+3VALW

Q45

D

6 2

1

STAR@

STAR@ SI3456BDV-T1-E3_TSOP6

SI3456BDV-T1-E3_TSOP6

3

STAR@R14

STAR@ 120K_0402_5%

120K_0402_5%

5

Q72B

4

+3VALW

Q53

6 2

1

STAR@

STAR@ SI3456BDV-T1-E3_TSOP6

SI3456BDV-T1-E3_TSOP6

12

3

120K_0402_5%

5

Q73B

4

+3VALW

Q60

6 2

1

STAR@

STAR@ SI3456BDV-T1-E3_TSOP6

SI3456BDV-T1-E3_TSOP6

12

3

120K_0402_5%

5

4

STAR@

3

4

J5

2

JUMP_43X79@J5JUMP_43X79@

G

3

D

STAR@ R17

STAR@

D

STAR@ R36

STAR@

Q74B

1

C658 4.7U_0603_6.3V6KC658 4.7U_0603_6.3V6K

2

R560

1 2

330K_0402_5%

5

+3V_SB

112

S

45

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K C670

C670 STAR@

STAR@

1

R14

C675

0.1U_0402_25V4K

0.1U_0402_25V4K STAR@

STAR@

2

+3V_LAN

J6

2

112

JUMP_43X79@J6JUMP_43X79@

S

45

4.7U_0603_6.3V6K

G

3

1

R17

2

J7

2

112

JUMP_43X79@J7JUMP_43X79@

S

45

4.7U_0603_6.3V6K

G

3

1

R36

2

R558

+VSB

SUSP 2N7002DW-T/R7_SOT363-6

2N7002DW-T/R7_SOT363-6

1

1U_0402_6.3V4Z

2

C679

STAR@

C681

0.1U_0402_25V4K

0.1U_0402_25V4K STAR@

STAR@

+3V_WLAN

C682

STAR@

C686

C686 STAR@

STAR@

0.1U_0402_25V4K

1 2 61

2

Q71A

1

C669

STAR@

2

Q72A

2N7002DW-T/R7_SOT363-6

STAR@

1

C680

STAR@

1U_0402_6.3V4Z

2

1

C683

STAR@

1U_0402_6.3V4Z

2

470_0805_5%

R566

R566 STAR@

STAR@ 470_0805_5%

470_0805_5%

1 2 61

SBPWR_EN#SBPWR_EN#

2

R571

R571 STAR@

STAR@ 470_0805_5%

470_0805_5%

1 2 61

Q73A

2N7002DW-T/R7_SOT363-6

STAR@

Q74A

2N7002DW-T/R7_SOT363-6

STAR@

2

R580

R580 STAR@

STAR@ 470_0805_5%

470_0805_5%

1 2 61

2

WOL_EN#WOL_EN#

STB_WLAN#

+5VALW TO +5VS

+5VALW

Q38

8

S

D

7

S

D

6

S

D

5

G

D

AO4422_SO8

1

C664

2

4.7U_0603_6.3V6K

100K_0402_5%

WOL_EN<32> SBPWR_EN<32>

R577

STAR@

100K_0402_5%

C659

1 2 3 4

1

C666

2

0.1U_0402_25V4K

R574

STAR@

WOL_EN#

2

G

12

+5VS

4.7U_0603_6.3V6K

1

C660

2

1U_0402_6.3V4Z

Q75B

2N7002DW-T/R7_SOT363-6

+5VALW

1 2

13

3

4

D

Q57

Q57 STAR@

STAR@ 2N7002_SOT23-3

2N7002_SOT23-3

S

R561

1 2

10K_0402_5%

5

1

2

SUSP

2N7002DW-T/R7_SOT363-6

+VSB

STB_WLAN<32>

R559

2

SBPWR_EN#<23>

470_0805_5%

1 2 61

Q75A

R578

STAR@

100K_0402_5%

R583

STAR@

100K_0402_5%

SBPWR_EN#

2

G

12

R581

STAR@

100K_0402_5%

STB_WLAN#

2

G

12

+5VALW

1 2

13

+5VALW

1 2

13

R575

R575 STAR@

STAR@ 100K_0402_5%

100K_0402_5%

D

Q58

Q58 STAR@

STAR@ 2N7002_SOT23-3

2N7002_SOT23-3

S

D

Q63

Q63 STAR@

STAR@ 2N7002_SOT23-3

2N7002_SOT23-3

S

Security Classification

2008/10/1 2009/10/1

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2008/10/1 2009/10/1

C

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

SCHEMATICS,M/B A4161

Size Document Number Rev

B

Monday, February 23, 2009

Date: Sheet

D

Date: Sheet

401562 G

E

of

35 48

of

35 48

of

35 48

A

PF1

12A_65V_451012MRL

BATT+

CHGRTCP

PR8

560_0603_5%

1 2

12A_65V_451012MRL

21

12

PD2

RLS4148_LL34-2

PR3

200_0603_5%

1 2

PR4

100K_0402_1%

1 2

PR5

22K_0402_1%

RTCVREF

3.3V

12

PC7

PC7 10U_0805_10V4Z

10U_0805_10V4Z

DC_IN_S2

12

PC1

PC1 1000P_0402_50V7K

1000P_0402_50V7K

12

PU1 G920AT24U_SOT89-3PU1 G920AT24U_SOT89-3

3

OUT

DC301001N00

PJP1

1

+

SINGA_2DW-0005-B03@

+CHGRTC

2

+

3

4

-

1 1

2 2

PR7

560_0603_5%

1 2

DC_IN_S1

51_ON#<34>

12

TP0610K-T1-E3_SOT23-3

N1

12

PC5

0.22U_1206_25V7K

2

IN

GND

1

SMB3025500YA_2P

1 2

PC2

100P_0402_50V8J

PQ1

12

N2

12

1U_0805_25V4Z

PL1

68_1206_5%

2

PR6

PR6 200_0603_5%

200_0603_5%

PC8

B

12

PC3

PC3 1000P_0402_50V7K

1000P_0402_50V7K

VIN

1 2 12

PR1

13

12

PD1

PD1 RLS4148_LL34-2

RLS4148_LL34-2

12

PR2

PR2 68_1206_5%

68_1206_5%

PC6

0.1U_0603_25V7K

VIN

12

PC4

PC4 100P_0402_50V8J

100P_0402_50V8J

VS

ACIN<17,22,32,34,38>

RTC Battery

PBJ1

-+

MAXEL_ML1220T10@

SP093MX0000

12

+RTCBATT

C

1 2

+RTCBATT

PR153

10K_0402_1%

PR154

10K_0402_1%

12

PD7

PD7 GLZ4.3B_LL34-2

GLZ4.3B_LL34-2

PR150

1 2

10K_0402_1%

PR149

1M_0402_1%

1 2

7

0

VS

8

PU5B

5

P

+

6

-

G

LM358DT_SO8

4

PR152

22K_0402_1%

1 2

PR156

10K_0402_1%

D

VIN

12

PC125

0.1U_0603_25V7K

12

PR151

84.5K_0402_1%

12

PR155

20K_0402_1%

RTCVREF

12

PC126

PC126 1000P_0402_50V7K

1000P_0402_50V7K

3 3

PJ2

PJ1

+3VALWP +3VALW

+5VALWP

+VSBP +VSB

2

112

JUMP_43X118@

(8A,320mils ,Via NO.= 16)

(12A,48mils ,Via NO.= 24)

JUMP_43X118@

PJ3

2

112

JUMP_43X118@

JUMP_43X118@ PJ5

PJ5

2

112

JUMP_43X118@

PJ7

2

112

JUMP_43X39@

+5VALW

+1.8VP +1.8V

(11A,440mils ,Via NO.=22)

+1.05VSP +1.05VS

(10A,400mils ,Via NO.=20)

PJ2

2

112

JUMP_43X118@

PJ4

2

112

JUMP_43X118@

PJ6

2

112

JUMP_43X118@

JUMP_43X118@ PJ8

PJ8

2

112

JUMP_43X118@

PJ16

2

112

@

JUMP_43X39

(1A,40mils ,Via NO.= 2)

PJ17

2

112

@

JUMP_43X39

(1A,40mils ,Via NO.= 2)

+3VL+3VLP

+5VLVL

(120mA,40mils ,Via NO.= 2)

PJ10

PJ9

4 4

PJ9

2

112

JUMP_43X118@

+1.5VS+1.5VSP

PJ10

2

112

@

JUMP_43X39

(1A,40mils ,Via NO.= 2)

+0.9VS+0.9VSP

(8.0A,320mils ,Via NO.=16)

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Compal Secret Data

Deciphered Date

C

Compal Electronics, Inc.

Title

2009/10/12008/10/1

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

SCHEMATICS,M/B A4161

401562

D

36 45Monday, February 23, 2009

G

of

A

B

C

D

PH1 under CPU botten side :

PF2

@PF2

@ 20A_24V_TR/3216FF20-R

1 2

20A_24V_TR/3216FF20-R

21

PF3

15A_65V_451015MRL

21

PR16

PR16 100_0402_1%

100_0402_1%

12

PR20

PR20 1K_0402_1%

1K_0402_1%

1 2

12

PR13

PR13 1K_0402_1%

1K_0402_1%

PR9

1K_0402_1%

6.49K_0402_1%

PR17

1 2

PR10

47K_0402_1%

12

VMB

SMB3025500YA_2P

+3VL

12

PC9

PC9 1000P_0402_50V7K

1000P_0402_50V7K

+3VL

BATT_TEMPA <32>

EC_SMB_DA1 <19,32,34> EC_SMB_CK1 <19,32,34>

PL2

1 2

ALI/MH# <38>

BATT+

12

PC10

0.01U_0402_25V7K

100K_0603_1%_TH11-4H104FT

PH2 near main Battery CONN :

90W,120w PF2=15A

1 1

2 2

180W, PF2=20A

PJP3

10

GND

11

GND

12

GND

13

GND

OCTEK_BTJ-09HA1G

1

2

3

4

5

6

7

8

9

BATT_S1

EC_SMDA EC_SMCA

PR15

100_0402_1%

CPU thermal protection at 92 degree C Recovery at 56 degree C

PH1

12

PC12

0.22U_0805_16V7K

VL

12

0.1U_0603_25V7K

12

PR18

PR14

13.7K_0402_1%

13.7K_0402_1% 1 2

15.4K_0402_1%

PC11

TM_REF1

12

PC13

1000P_0402_50V7K

12

3 2

12

PR21

PR21 100K_0402_1%

100K_0402_1%

VL

47K_0402_1%

1 2

8

PU2A

P

+

-

G

LM393DG_SO8

4

12

PR19

100K_0402_1%

PR12

O

1

VL

PR11

PR11 47K_0402_1%

47K_0402_1%

1 2

RLS4148_LL34-2

PD3

ENTRIP1 <21,39>

13

D

PQ2

2

SSM3K7002FU_SC70-3

G

S

12

13

D

2

G

S

ENTRIP2 <21,39>

PQ3

PQ3 SSM3K7002FU_SC70-3

SSM3K7002FU_SC70-3

BAT. thermal protection at 92 degree C Recovery at 56 degree C

VLVL

PQ4

TP0610K-T1-E3_SOT23-3

B+

3 3

VL

PR28

100K_0402_1%

POK<39>

4 4

A

1 2

PR29

PR29 0_0402_5%

0_0402_5%

12

13

2

G

PC17

0.1U_0402_16V7K

@

22K_0402_1%

D

PQ5

PQ5 SSM3K7002FU_SC70-3

SSM3K7002FU_SC70-3

S

PR26

PR26 1 2

12

PR24

100K_0402_1%

12

PC14

@

0.22U_1206_25V7K

B

13

2

+VSBP

12

PC15

0.1U_0603_25V7K

@

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

100K_0603_1%_TH11-4H104FT

PC16

0.22U_0805_16V7K

Compal Secret Data

12

PH2

12

PR27

15.4K_0402_1%

Deciphered Date

C

PR25

13.7K_0402_1%

13.7K_0402_1% 1 2

TM_REF1

PR22

PR22 47K_0402_1%

PR23

47K_0402_1%

1 2

8

5

P

+

6

-

G

4

2009/10/12008/10/1

47K_0402_1%

1 2

PU2B

7

O

LM393DG_SO8

RLS4148_LL34-2

Title

Size Document Number Rev

Date: Sheet

12

PD4

Compal Electronics, Inc.

SCHEMATICS,M/B A4161

401562

D

37 45Monday, February 23, 2009

G

of

A

VIN

PR31

3.3_1210_5%

1 2

PR32

3.3_1210_5%

1 1

PC25

2.2U_0805_25V6K

1 2

PC21

12

0.01U_0603_50V7K

1 2

8 7

5

8 7

5

PR35

PR35 340K_0402_1%

340K_0402_1%

PQ6 AO4407_SO8@PQ6 AO4407_SO8@

4

PQ9 AO4407_SO8PQ9 AO4407_SO8

4

1 2 36

PC26

1 2

PQ7 AO4407_SO8@PQ7 AO4407_SO8@

1 2 3 6

PQ10 AO4407_SO8PQ10 AO4407_SO8

1 2 3 6

12

PR34

100K_0402_1%

0.01U_0402_25V7K

4

Input OVP : 22.3V Input UVP : 17.26V Fsw : 300KHz

2 2

VREF

CELLS

PR45

PR45 47K_0402_1%

47K_0402_1%

1 2

CELLS

13

D

2

G

PQ15

S

SSM3K7002FU_SC70-3

3 3

Cells selector

GND VREF

3 Cell 4 Cell

ALI/MH# <37>

1 2

PR41

PR41 340K_0402_1%

340K_0402_1%

1 2

PR42

54.9K_0402_1%

1 2

ACOFF

0.1U_0402_16V7K

PR39

54.9K_0402_1%

100K_0402_1%

1 2

PC129

PR158

100K_0402_1%

0.1U_0603_25V7K

VREF

12

PR159

PR159 340K_0402_1%

340K_0402_1%

SI2301BDS-T1-E3_SOT23-3

PR43

ACGOOD#

VREF

PC39

12

13

D

S

GATE

PR157

PR157 200K_0402_1%

200K_0402_1%

PQ39

PQ39 SSM3K7002FU_SC70-3

SSM3K7002FU_SC70-3

1 2

2

G

VREF

CP setting

2

12

ACSET

13

D

2

G

S

PR38

71.5K_0402_1%

71.5K_0402_1% 1 2

0.01U_0402_25V7K@

PQ14

1 3

GATE

PQ38

PQ38 SSM3K7002FU_SC70-3

SSM3K7002FU_SC70-3

VMB

PC43

0.01U_0402_25V7K

12

PR53

340K_0402_1%

12

PR55

499K_0402_1%

12

PR57

105K_0402_1%

12

PC44

0.01U_0402_25V7K

VS

12

4 4

BATT_OVP<32>

PR56

10K_0402_1%

1 2

A

8

PU5A

3

P

+

1

0

2

-

G

LM358DT_SO8

4

8 7

5

8 7

5

PC32

1U_0603_10V6K

B

1 2

0.01_2512_1%

0.1U_0402_16V7K

0.1U_0402_16V7K 1 2

12

PC27

0.1U_0603_25V7K

12

PC38

CHGVADJ<32>

B

C

PJ11

2

112

JUMP_43X118@

1 2

PC29

0.1U_0603_25V7K

ACOFF <32>

ICHG setting

12

PR47

PR47 100K_0402_1%

100K_0402_1%

PR30

PC23

ACSET

PR40

PR40 100K_0402_1%

100K_0402_1%

1 2

0.47U_0603_16V7K

VREF

12

VADJ

/BATDRV

210K_0402_1%

1 2

PR51

4 3

12

PC35

@

PC28

0.1U_0603_25V7K

10

11

12

13

14

REGN

CHGEN#

PU4

1

CHGEN

2

ACN

3

ACP

4

ACDRV

5

ACDET

6

ACSET

7

ACOP

8

OVPSET

9

AGND

VREF

VDAC

VADJ

ACGOOD

BATDRV

BQ24751ARHDR_QFN28_5X5

12

PR50

PR50 0_0402_5%@

0_0402_5%@

VADJ

12

PR52

PR52 499K_0402_1%

499K_0402_1%

LODRV

IADAPT

28

PVCC

0_0603_1%

1 2

27

BTST

26

HIDRV

25

PH

REGN

24

REGN

PGND

LEARN

CELLS

SRN

SRSET

SRP

BAT

TP

12

23

22

21

CELLS

20

19 18 17

29

16

1 2

15

10_0603_5%

100P_0402_50V8J

CHGVADJ Pre Cell

3.3V 4.35V

0V 4V

CHGVADJ

B+

PC24

0.1U_0805_25V7K

1 2

PR36

PD5

12

RLS4148_LL34-2

PC34

PC34 1U_0603_10V6K

1U_0603_10V6K

12

PC40

0.1U_0603_25V7K

PR49

12

PC42

要接到

EC DA pin

LI-3S :13.5V----BATT-OVP=1.5V BATT-OVP=0.111*BATT+

90W,Iadapter=4.736A,PR30=0.015ohm,PR38=54.9K,PR40=100K,CP=4.357A 120W,Iadapter=6.315A,PR30=0.010ohm,PR38=71.5K,PR40=100K,CP=5.810A 180W,Iadapter=7.890A,PR30=0.010ohm,PR38=50K,PR40=133K,CP=7.421A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Compal Secret Data

Deciphered Date

C

CHG_B+

578

12

1 2

PC18

4.7U_1206_25V6K

PQ12

PQ12 AO4466_SO8

AO4466_SO8

3 6

241

3 6

241

49.9K_0402_1%

PC41

0.01U_0402_25V7K

@

PL3

10UH_SIL1045RA-100PF_4.5A_30%

1 2

PQ13

PQ13 AO4466_SO8

AO4466_SO8

PR46

12

IREF Current

2.968V 3A

2009/10/12008/10/1

1 2

PC19

IREF <32>

1 2

PC22

4.7U_1206_25V6K

12

PC36

0.1U_0603_25V7K

D

PQ8 AO4407_SO8PQ8 AO4407_SO8

4

12

PC30

10U_1206_25V6M

8 7

5

8 7

5

PC31

10U_1206_25V6M

ACIN <17,22,32,34,36>

of

38 45Monday, February 23, 2009

of

38 45Monday, February 23, 2009

of

38 45Monday, February 23, 2009

1 2 3 6

12

1 2

PC20

0.01U_0402_25V7K

PR33

100K_0402_1%

PQ11 AO4407_SO8PQ11 AO4407_SO8

1 2 3 6

/BATDRV

PR37

0.02_2512_1%

0.02_2512_1% 1 2

0.1U_0402_16V7K

100K_0402_1%

ACGOOD#

FSTCHG<32>

Date: Sheet

4 3

PC33

1 2

12

RTCVREF

12

PR44

Title

Size Document Number Rev

PR48

@PR48

@

100K_0402_1%

Compal Electronics, Inc.

SCHEMATICS,M/B A4161

401562

PC37

0.1U_0603_25V7K

@

VREF

1 2

13

D

2

G

S

VREF

1 2

13

D

2

G

S

D

12

PQ16

@

PQ16

@ SSM3K7002FU_SC70-3

SSM3K7002FU_SC70-3

PR54

PR54 100K_0402_1%

100K_0402_1%

CHGEN#

PQ17

PQ17 SSM3K7002FU_SC70-3

SSM3K7002FU_SC70-3

BATT+

G

5

4

3

2

1

2VREF_51125

D D

PR58

13K_0402_1%

1 2

PR60

B++

PJ12

2

B+

C C

B B

JUMP_43X118@

112

PC46

2200P_0402_50V7K

+3VALWP

12

PC47

10U_1206_25V6M

4.7UH_PLC1045-4R7_5.5A_30%

1

2

PQ22

SSM3K7002FU_SC70-3

PQ22

+

PC53

PL4

1 2

220U_6.3VM_R15

13

D

2

G

S

PQ18

PQ18 AO4466_SO8

AO4466_SO8

12

PR67 @ PR67

@

4.7_1206_5%

12

PC127

@

680P_0603_50V7K

13

D

2

G

S

578

3 6

241

578

PQ20

PQ20 AO4712_SO8

AO4712_SO8

3 6

241

ENTRIP2 <21,37>ENTRIP1 <21,37>

PQ23

PQ23 SSM3K7002FU_SC70-3

SSM3K7002FU_SC70-3

12

PC50

4.7U_0805_10V6K

1 2

PC51

0.1U_0402_16V7K

LX_3V

B+

+3VLP

1 2

@ PR160

@ 499K_0402_1%

499K_0402_1%

1 2

PR64

0_0603_1%

LG_3V

PR160

PR60

20K_0402_1%

1 2

PR62

150K_0402_1%

1 2

PU6

25

P PAD

7

VO2

8

12

@

VREG3

9

VBST2

10

DRVH2

11

LL2

12

DRVL2

PR68

100K_0402_5%

BST_3V UG_3V UG_5V

2VREF_51125

12

PC45

0.22U_0603_10V7K

ENTRIP2

6

5

VFB2

ENTRIP2

SKIPSEL

EN0

14

13

1 2

PR69

0_0402_5%@

B++

3

4

TONSEL

GND

15

16

12

1

2

VFB1

VREF

ENTRIP1

PGOOD

VBST1 DRVH1

DRVL1

VREG5

VIN

VCLK

17

18

12

PC55

4.7U_0805_10V6K

PC56

0.1U_0603_25V7K

PR59

30K_0402_1%

1 2

PR61

20K_0402_1%

1 2

PR63

150K_0402_1%

ENTRIP1

1 2

24

VO1

23 22 21 20

LL1

19

TPS51125RGER_QFN24_4X4

BST_5V

LX_5V LG_5V

0_0603_1%

1 2

VL

PR65

B++

12

PC48

2200P_0402_50V7K

POK <37>

PC52

0.1U_0402_16V7K

1 2

12

PC49

PC124

4.7U_1206_25V6K

PQ21

FDS6670AS_NL_SO8

578

4.7U_1206_25V6K

3 6

241

D6D5D7D

4

G

S

3

2

8

S

1

PQ19

AO4466_SO8

3.3UH_SIL1045R-3R3PF_8.2A_30%

1 2

12

PR66 @ PR66

@

4.7_1206_5%

12

PC128

@

680P_0603_50V7K

PL5

+5VALWP

1

+

PC54

2

220U_6.3VM_R15

VL

100K_0402_1%

1 2

VS

PR71

100K_0402_1%

A A

5

PR70

12

PR72

49.9K_0402_1%

12

2

G

12

PC57

@

0.01U_0402_16V7K

13

D

PQ24

PQ24 SSM3K7002FU_SC70-3

SSM3K7002FU_SC70-3

S

Security Classification

2008/10/1 2009/10/1

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2008/10/1 2009/10/1

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

2

Date: Sheet

SCHEMATICS,M/B A4161

401562

Monday, February 23, 2009

1

of

39 45

of

39 45

of

39 45

G

A

PR73

75K_0402_1%

+1.5VSP

75K_0402_1%

1 2

B

PR74

75K_0402_1%

75K_0402_1% 1 2

PR75

75K_0402_1%

12

PR76

29.4K_0402_1%

29.4K_0402_1% 12

+1.05VSP

C

D

1 1

+1.5VSP

2 2

51124_B+

PC58

4.7U_1206_25V6K

1.8U_D104C-919AS-1R8N_9.5A_30%

1

12

+

PC66

2

220U_6.3VM_R15

12

1 2

PC67

12

PC59

4.7U_1206_25V6K

PL6

4.7U_0805_6.3V6K

12

PC60

2200P_0402_50V7K

12

PR82 @ PR82

@

4.7_1206_5%

4.7_1206_5% 12

PC70

@

680P_0603_50V7K

241

578

3 6

578

3 6

PQ25

AO4466_SO8

0.1U_0402_16V7K

PQ27

PQ27 AO4712_SO8

AO4712_SO8

SUSP#

PC64

0_0402_5%

0.1U_0402_16V7K@

PR86

0_0603_1%

12

PC74

12

PR78

12

BST_1.5V UG_1.5V

LX_1.5V

1U_0603_10V6K

PU7

25

7 8

9 10 11 12

18.2K_0402_1%

18.2K_0402_1% 1 2

PC72

0_0402_5%

P PAD

PGOOD2 EN2 VBST2 DR VH2 LL2 DR VL2

PR85

12

PR77

5

6

VO2

VFB2

TRIP2

PGND2

14

13

1 2

PR87

3.3_0402_5%

1 2

4

TONSEL

V5FILT

15

3

GND

V5IN

16

12

2

17

12

PC73

4.7U_0805_10V6K

1

VO1

VFB1

24

PGOOD1

23

EN1

BST_1.05V

22

VBST1

DR VH1

DR VL1

TRIP1

PGND1

TPS51124RGER_QFN24_4x4

TPS51124RGER_QFN24_4x4 18

PR84

14.7K_0402_1%

+5VALW

UG_1.05V

21 20

LL1

LG_1.05VLG_1.5V

19

LX_1.05V

12

PR79

0_0603_1%

PR88

0_0402_5%

1 2

PC75

0.1U_0402_16V7K@

0.1U_0402_16V7K

12

AO4466_SO8

PC65

1 2

PQ28

FDS6670AS_NL_SO8

SUSP# <17,26,29,32,35>

PQ26

51124_B+

578

3 6

241

D6D5D7D

4

G

S

3

2

PJ13

112

JUMP_43X118@

12

PC62

PC61

4.7U_1206_25V6K

PL7

1.8U_D104C-919AS-1R8N_9.5A_30%

1.8U_D104C-919AS-1R8N_9.5A_30% 1 2

8

12

PR83 @ PR83

@

4.7_1206_5%

12

S

1

PC71

@

680P_0603_50V7K

2

B+

12

PC63

2200P_0402_50V7K

+1.05VSP+1.5VSP

+1.05VSP

1

+

PC69

1 2

PC68

2

220U_6.3VM_R15

4.7U_0805_6.3V6K

220U_6.3VM_R15

3 3

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Compal Secret Data

Deciphered Date

C

Compal Electronics, Inc.

Title

2009/10/12008/10/1

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

SCHEMATICS,M/B A4161

401562

D

40 45Monday, February 23, 2009

G

of

5

4

3

2

1

D D

578

PR89

300K_0402_5%

2 3 4 5 6

PU8

TON VOUT V5FILT VFB PGOOD

1 2

1

EN_PSV

GND7PGND

0_0402_5%

1 2

0.1U_0402_16V7K@

BST_1.8V_1

14

15

TP

VBST

V5DRV

TPS51117RGYR_QFN14_3.5x3.5

8

4.7U_0805_6.3V6K

PR98

PC88

PR90

0_0402_5%

PR93

422_0603_1%

1 2

PC81

1U_0603_10V6K

1 2

12

PC78

@PC78

@

0.1U_0402_16V7K

PC83

47P_0402_50V8J@

1 2

PR95

28.7K_0402_1%

28.7K_0402_1% 1 2

12

PR96

20.5K_0402_1%

SUSP<35>

SYSON<26,32,34,35>

+5VALW

C C

B B

DRVH

TRIP

DRVL

PR91

PR91 0_0603_1%

0_0603_1%

1 2

PC79

PR97

PC79

1 2

0.1U_0603_25V7K

+5VALW

12

PC84

4.7U_0805_10V6K

12

PR99

PC87

1K_0402_1%

12

0.1U_0402_16V7K

BST_1.8V

DH_1.8V

13

LX_1.8V

12

LL

1 2

11

PR94

16.9K_0402_1%

10

DL_1.8V

9

+1.8V

1

PJ15

1

JUMP_43X79@

2

12

PC85

1K_0402_1%

13

D

2

G

PQ31

S

PQ31

SSM3K7002FU_SC70-3

12

PQ29

PQ29 AO4466_SO8

AO4466_SO8

3 6

241

578

PQ30

PQ30 AO4712_SO8

AO4712_SO8

3 6

241

PU9

VIN1VCNTL

2

GND

3

VREF

4

VOUT

APL5331KAC-TRL_SO8

+0.9VSP

12

PC89

PC89 10U_0805_6.3V6M

10U_0805_6.3V6M

51117_B+

12

PC76

4.7U_1206_25V6K

PL8

1.8U_D104C-919AS-1R8N_9.5A_30%

1.8U_D104C-919AS-1R8N_9.5A_30% 1 2

12

PR92

4.7_1206_5%@

12

PC82

680P_0603_50V7K@

6 5

NC

7

NC

8

NC

9

TP

2

JUMP_43X118@

PC77

4.7U_1206_25V6K

+3VALWP

12

PC86

PC86 1U_0603_6.3V6M

1U_0603_6.3V6M

PJ14

112

1

+

PC80

PC80 220U_6.3VM_R15

220U_6.3VM_R15

2

B+

+1.8VP

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

2009/10/12008/10/1

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

SCHEMATICS,M/B A4161

401562

41 48Monday, February 23, 2009

1

1.0

of

5

D D

PR101 0_0402_5%PR101 0_0402_5%

PM_DPRSLPVR<8,22>

H_DPRSTP#<5,8,21>

CLK_ENABLE#

12

1 2

12

PR109 0_0402_5%PR109 0_0402_5%

12

PR115

PC117 0.018U_0603_50V7JPC117 0.018U_0603_50V7J

12

PC118

0.018U_0603_50V7J

PR147 1K_0402_1%PR147 1K_0402_1%

0.22U_0603_10V7K

+3VS

PR114

499_0402_1%

1 2

VGATE<8,22,32>

H_PSI#<5>

PGD_IN

C C

B B

PR124 4.22K_0402_1%@PR124 4.22K_0402_1%@

VCCSENSE<6>

+CPU_CORE

VR_TT#

PR142 20_0402_5%PR142 20_0402_5%

PR121 147K_0402_1%PR121 147K_0402_1%

1 2

100K_0603_1%_TH11-4H104FT@

1 2

PC1050.015U_0402_16V7K@ PC1050.015U_0402_16V7K@

PR126 13K_0402_1%PR126 13K_0402_1%

PR135 97.6K_0402_1%PR135 97.6K_0402_1%

1 2

PC114 220P_0402_50V7KPC114 220P_0402_50V7K

1 2

255_0402_1%

PR140 1K_0402_1%PR140 1K_0402_1%

1 2

VSSSENSE<6>

PH3

PC109 1000P_0402_50V7KPC109 1000P_0402_50V7K

1 2

PR138

1 2

PR123 0_0402_5%@PR123 0_0402_5%@

1 2

PC1060.022U_0603_25V7K PC1060.022U_0603_25V7K

1 2

1 2 1 2

PC1081000P_0402_50V7K PC1081000P_0402_50V7K

PR128 6.81K_0402_1%PR128 6.81K_0402_1%

1 2

PC111 470P_0402_50V7KPC111 470P_0402_50V7K

PC115 1000P_0402_50V7KPC115 1000P_0402_50V7K

1 2

PR141 0_0402_5%PR141 0_0402_5%

PR145

20_0402_5%

VCC_PRM

PR102 0_0402_5%PR102 0_0402_5%

PR103 0_0402_5%PR103 0_0402_5%

1 2

12

PC99

1U_0603_6.3V6M

1.91K_0402_1%

1 2 3 4 5 6 7 8

9 10 11 12

PR136

@

0_0402_5%

1 2

PR144 0_0402_5%PR144 0_0402_5%

PC120 180P_0402_50V8JPC120 180P_0402_50V8J

1 2

PC122

1 2

48

49

3V3

GND

PGOOD PSI# PMON RBIAS VR_TT# NTC SOFT OCSET VW COMP FB FB2

VDIFF13VSEN14RTN15DROOP16DFB17VO18VSUM19VIN20GND21VDD22ISEN223ISEN1

12

PR137

PR137 1K_0402_5%

1K_0402_5%

1 2

PR148 4.42K_0402_1%PR148 4.42K_0402_1%

4

VR_ON

45

44

46

47

VR_ON

CLK_EN#

DPRSTP#

DPRSLPVR

ISL6262ACRZ-T_QFN48_7X7

12

PC119

0.018U_0603_50V7J

PC121 0.1U_0402_16V7KPC121 0.1U_0402_16V7K

1 2

PC123 0.22U_0402_6.3V6KPC1230.22U_0402_6.3V6K

12

CPU_VID6

43

12

<32>

CPU_VID5

12

PR146

<6>

CPU_VID4

CPU_VID3

CPU_VID2

12

1 2

PC116

0.1U_0603_25V7K

PR143

12

11K_0402_1%

<6>

PC112

PC112 1U_0402_6.3V6K

1U_0402_6.3V6K

10_0603_5%

12

1 2

<6>

CPU_VID1

CPU_VID0

VID037VID138VID239VID340VID441VID542VID6

BOOT1 UGATE1 PHASE1

PGND1 LGATE1

PVCC

LGATE2

PGND2 PHASE2 UGATE2

BOOT2

24

1 2

PR134 1_0603_5%PR134 1_0603_5%

PR139

VSUM

2.61K_0402_1%

PH4

PH4 10KB_0603_5%_ERTJ1VR103J

10KB_0603_5%_ERTJ1VR103J

BOOT_CPU1

36 35 34 33 32 31 30 29 28 27

BOOT_CPU2

26

PR127

2.2_0603_1%

25

NC

PU10

ISEN1 ISEN2

+5VS

+CPU_B+

2.2_0603_1%

2.2_0603_1% PR113

PR113

1 2

UGATE_CPU1 PHASE_CPU1

LGATE_CPU1

LGATE_CPU2

PHASE_CPU2 UGATE_CPU2

1 2

3

+5VS

12

PC92

PC91

0.022U_0402_16V7K

2.2U_0603_6.3V6K

0.22U_0603_10V7K

0.22U_0603_10V7K PC100

PC100

1 2

SI4856DY-T1-E3_SO8

1 2

PC107

0.22U_0603_10V7K

SI4856DY-T1-E3_SO8

PR100

PR100 1_0603_5%

1_0603_5%

1 2

12

PQ33

PQ36

2

+CPU_B+

@

PL10

1 2

PC102

1 2

PL11

1 2

PC113

1 2

1

+

PC96

2

220U_25V_M

12

1_0402_5%

VCC_PRM

+CPU_B+

12

VCC_PRM

PC90

PR120

PR132

1_0402_5%

12

PC93

PC94

10U_1206_25V6M

12

PR117

4.7_1206_5%

12

PC101

680P_0603_50V8J

12

PR129

4.7_1206_5%

12

PC110

PC110 680P_0603_50V8J

680P_0603_50V8J

10U_1206_25V6M

12

PR118

VSUM

12

PC103

10U_1206_25V6M

12

PR130

VSUM

0.36UH_MPC1040LR36_24A_20%

12

PR119

PR122 0_0603_5%@PR122 0_0603_5%@

10K_0402_1%

3.65K_0805_1%

ISEN1

0.22U_0603_10V7K

12

PC104

10U_1206_25V6M

0.36UH_MPC1040LR36_24A_20%

12

PR131

10K_0402_1%

PR133 0_0603_5%@PR133 0_0603_5%@

3.65K_0805_1%

0.22U_0603_10V7K

0.22U_0603_10V7K ISEN2

PQ32

PQ32 SI7686DP-T1-E3_SO8

SI7686DP-T1-E3_SO8

3 5

241

5

4

5

D8D7D6D

S1S2S3G

5

4

D8D7D6D

S1S2S3G

D8D7D6D

S1S2S3G

PQ34

4

SI4856DY-T1-E3_SO8

3 5

241

5

D8D7D6D

S1S2S3G

4

SI4856DY-T1-E3_SO8

PQ35

PQ35 SI7686DP-T1-E3_SO8

SI7686DP-T1-E3_SO8

PQ37

PL9

HCB4532KF-800T90_1812

1 2

1

+

0.01U_0402_25V7K

2

220U_25V_M

PC95

+CPU_CORE

1

12

PC97

680P_0603_50V8J

12

PC98

3300P_0402_50V7K

B+

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2008/10/1 2009/10/1

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

SCHEMATICS,M/B A4161

401562

Monday, February 23, 2009

1

of

42 48

G

NO DATE PAGE MODIFICATION LIST PURPOSE

-------------------------------------------------------------------------------------------------------------

11/01'071

2 12/25'07 Add AC-IN detect functionAdd AC-IN schematic

2/13'083 P.38

4 3/5'08 P.38 Add PQ38,PQ39,PR159,PC129,PR157,PR158 Add wrong adapter protection function

3/23'085 Add PR160 Add TPS51125/RT8205A p2p

4/28'08 Delete PD6,change PR150 and PR1536 For ACIN detect to meet wrong adapter function

6/219'08 Change PR45 from 100K_0402_1% to 47K_0402_1%( SD034470280)6 P.38 For ACIN detect to meet wrong adapter function

P.36 P.38 P.39 PR66,PR67,PC127,PC128 Add 3VALWP and 5VALWP snubber

P.42

P.39

P.36

P.39 P.40 P.41

Release

Add AC-IN pull-higher resistormove PR44

Change CHGVADJ voltagechange PR51, PR52

Change PQ33,PQ34,PQ36,PQ37 Change low side Mosfet

Change +3VALW->+3VL on Battery portP.37

Change +3VL->B+ in PU6 pin13P.39 Add PR67,PC127,PR66,PC128 Add PR82,PR83,PC70,PC71 Add PR92,PC82

Add CPU boost and snubber for EMI requestChange PR113,PR127,PR117,PC101,PR129,PC110

Change battery temperature action

Add 2nd source RT8205A P2P GPS noise GPS noise GPS noise

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2008/10/1 2009/10/1

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

SCHEMATICS,M/B A4161

401562 G

of

43 48Monday, February 23, 2009

of

43 48Monday, February 23, 2009

of

43 48Monday, February 23, 2009

45@ Part

PJP1

DC-JACK

45@PJP1

45@

5

4

3

2

1

PCB

D D

ZZZ

LA-4161P DAZ BOM--DAZ04G00101

CHIPSET(R1)

U3

PMR1@U3

PMR1@

NB-R1

U3

PMR3@U3

PMR3@

NB-R3

C C

NB-R1

U3 NB-R3

NB-R3

GMLR1@U3

GMLR1@

GMLR3@U3

GMLR3@

U3 NB-R1

NB-R1

GMR1@U3

U10 SB-R1

SB-R1

SBR1@U10

SBR1@

B B

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

2009/10/12008/10/1

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

SCHEMATICS,M/B A4161

401562

44 48Monday, February 23, 2009

1

G

of

5

Item Phase-Description

Date

D D

C C

P.

PreMP-Remove TMA SMBus, becase TMA remvoe thermal sensor.

P.031 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30

32 33 34 35 36 37 38 39 40 41 42 43 44 45

48 50 P.31 PreMP-Changef R736 and R737 from 33 to 100Ohm

51 52

PreMP-Change VGA Thermal sensor IC PreMP-Set Q20 as @

P.04

PreMP-D2 part number change from SC100000Y10 to SC100001M00 for cost. PreMP-Delete R727, becasue remove S I/O debug port.

P.16

PreMP-Delete R696, becasue remove S I/O debug port. PreMP-Add R52, reserve for GPS test. PreMP-R249 change to 976_1% (SD000003280).

P.19

PreMP-R253 change to 240_1%, and R255/R257/R258 change to 270_1%. PreMP-Modify JP9, to increase hole size to 0.5mm PreMP-Add R48 and R50 for HDMI DDC. PreMP-Delete Q10A/B dual 2N7002 and add Q10 and Q32 with ow cp, SB501110010. PreMP-Delete Q130A/B dual 2N7002 and add Q29 and Q31 with ow cp, SB501110010. PreMP-Change from LPC_DRQ1# to FELICA_PWR becasue remove S I/O debug port and Felica enable power not enough.

P.21

PreMP-Remove FELICA_PWR becasue voltage not enough issue. PreMP-Add R54 for REC_LED PreMP-Change SSC@ to NIHDMI@ and IHDMI@ PreMP-Remove R358, and place to LED/B

P.22

PreMP-Add TV_LED for JPN TV model PreMP-Change HDD connector type to increase two screw hole size.

P.24

PreMP-Change HDD type. PreMP-Change Felica FFC to FPC and decrease pin to 4pins, and change pin define.

P.25

PreMP-Delete R420/D17, request separate disable pin.

P.26

PreMP-Reserve U22/C430 for UWB_OFF#. Add R128 for pass, controlled by EC. PreMP-Delete R419/R418/Q135 and remove TMA_THERM#, becasue TMA remove Thermal sensor, don't need SMBUS again.

P.27

PreMP-Change JP24 pin13 to USB_DISABLE# PreMP-Change JP22 pin20 to USB_DISABLE# PreMP-L19 change to 0_0805_5%P.28 PreMP-Delete L20. PreMP-Add C10 near U20 pin5. PreMP-Remove U21 and C545 for cost down plane for new BIOS code.31 PreMP- Remove Q3/Q8/Q136/R1013/R1037 for IR Blaster testP.31 PreMP-Delete R499 and R506, and add R58, R60, R63, R65, R68, R70, R85, R120, R129, R130, R131, R148.

Add Q131, R149 and R150. PreMP-Delete R1031, becasue TMA remove Thermal Sensor.P.32

PreMP-Delete TMA_THERM# from EC pin31, becasue TMA remove Thermal Sensor. PreMP-Add UWB_OFF# on U37 pin31 to separate UWB disable controlled.. PreMP- Remove JP42, S I/O debug connector.P.33 PreMP-remove J9 and Pop Q9 for LED behavior.P.34 PreMP-Add TV_LED on JP52 pin43 for REC Amber LED. PreMP-Add SW1 at BTN for Debug. PreMP-Remove R358, and place to LED/B PreMP-Add R56 for TV_LED PreMP-Add R14/R17/R36 near C675/C681/C686 for MOS burned issue. And set all part as STAR@P.35

P.16 PreMP-R689 set as @ and POP R52.46

PreMP-For RTC delay, modify C838 and C839 to 18P. P.1847PreMP-Modify L4/L5/L6, to SM010005X00. P.19 PreMP-Set HDMI power R1036 as @ and POP D9.49

P.21 PreMP-Change R386 to 1.5M Ohm (SD028150480) for Discrete; and 1M Ohm (SD028100480) for UMA P.16 PreMP-Chang R728 from 22 to 33Ohm

4

3

2

1

62 MP-For EMI L11~L14 set as "HDMI@" add and set pass resistor as "@"P.19 63 P.35 MP-For cost to set SYSON circuit Q54/R570 as "@"

P.2164 MP-Modify U5 VDD circuit (+SSC_VDD) for EMI report.

65 MP-R302 change to 47-Ohm@100M Bead in JSKAA UMA. 66 MP- Replace SB00000AR00 (2N7002KDW) by SB00000EO00 (2N7002KDW)

67 MP- R80, change GM@ to IHDMI@ for Intel display straping define.

B B

2009/2/6 P.16

68 MP- 2nd Source problem, L15,L17 change to SM010016720 69 MP- Y3: SJ114P3M700 is AP code=X1, change to SJ114P3M210/SJ100001700/SJ114P3MG00

A A

Security Classification

2008/10/1 2009/10/1

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2008/10/1 2009/10/1

3

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

SCHEMATICS,M/B A4161

401562 G

Monday, February 23, 2009

401562 G

1

of

45 48

of

45 48

of

45 48

5

4

3

2

1

4.7K

G16

D D

A13

ICH_SMBCLK ICH_SMBDATA

+3V_SB

2N7002 2N7002

PM_SMCLK

PM_SMDATA

10K

ICH9-M

C17 B18

ME_EC_CLK1

10K

ME_EC_DAT1

+3V_SB

4.7K

HDMI-CEC Control

Feather Touch

100

+5VL

SMBUS Address [0011 010Xb]

SMBUS Address [TBD]

BATTERY

2N7002 2N7002

SMBUS Address [0001 011Xb]

C C

SCL1

SDA1

EC_SMB_CK1

EC_SMB_DA1

4.7K

EC

KB926C

B B

4.7K

197

195

197 195

10 9

7 8

DIMM-0

DIMM-1

CLOCK

EXPRESS CARD

4.7K

TMA

+3VS

SMBUS Address [1001 000Xb]

SMBUS Address [1001 010Xb]

SMBUS Address [1101 001Xb]

SMBUS Address [TBD]

+3VS

SMBUS Address [TBD]

4.7K

SCL2

SDA2

A A

5

EC_SMB_CK2

EC_SMB_DA2

4

+3VS

GPU Thermal

CPU Thermal

SMBUS Address [TBD]

SMBUS Address [1001 100Xb]

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2008/10/1 2009/10/1

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

B

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

SCHEMATICS,M/B A4161

401562

46 48Monday, February 23, 2009

1

G

of

G

5

4

3

2

1

System support S5(DC) Turn On

+3VL

D D

4.7K

+5VL

EC_SMB_CK1

78 EC_SMB_DA1

177

20

+5VL

CEC

9

HDMI_CECIN HDMI_CECOUT

10

+5VL

HDMI_CEC 13

Circuit

+5VL

HDMI

HDMI-CEC By TV

+5VL

C C

EC

KB926C

LPC

TBD TBD

Feather Touch

+3VS

**SMSC SIO1049 solution.

Feather Touch

+3VL

+5VL

B B

38

73

A A

5

IR_WAKE#

EC_CIRIN

100K

**ENE KB926 solution.

4

+5VL

IR Blaster

6

0

BOM Control

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2008/10/1 2009/10/1

3

Compal Secret Data

CIR_IN

Deciphered Date

2

CIR

IR

Compal Electronics, Inc.

Title

Size Document Number Rev

B

Date: Sheet

Compal Electronics, Inc.

SCHEMATICS,M/B A4161

401562

1

of

47 48Monday, February 23, 2009

of

47 48Monday, February 23, 2009

of

47 48Monday, February 23, 2009

G

5

4

3

2

1

B+

Battery

AC

D D

adapter

Charger

B+

PWM 3V/5V TPS51125

+3VALWP

+5VALWP

Single PWM VGA core TPS51117

VGA Core VGA Core

B+

PWM VGA core ISL6264

BQ24751A

B+

Single PWM

1.8V TPS51117

+1.8VSP

Battery

PWM

1.05V/1.5V TPS51124

+1.05VSP

+1.5VSP

+1.5VS

Single PWM

C C

1.8V TPS51117

PWM

+1.8VP

+CPU_CORE

LDO

1.2V or1.1V APL5913

CPU core ISL6262A

+1.2VSP or +1.1VSP

B+

+1.5VS

Single PWM

1.8V TPS51117

LDO

1.1V APL5913

+1.8VSP

+1.2VSP or +1.1VSP

LDO

B B

A A

5

0.9V APL5331

4

+0.9VP+1.8V

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2008/10/1 2009/10/1

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

B

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

SCHEMATICS,M/B A4161

401562

48 48Monday, February 23, 2009

1

G

of

COMPAL LA-4161P Schematics

Specifications and Main Features

Frequently Asked Questions

User Manual