COMPAL LA-4151P Schematics

A

B

COMPAL CONFIDENTIAL

C

D

E

1 1

PCB NO :

LA4151P(DAA00000Q1L)

MODEL NAME :

JAL10

BOM P/N :

M09 Lola UMA

uFCBGA Mobile Penryn

2 2

3 3

Intel Cantiga GM + ICH9M

2008-07-4

REV : 1.0

@ : Nopop Component
1@ : Use TCM only
2@ : Use TAA only
3@ : Use BROADCOM TPM only
4@ : Use without TAA only
5@ : Use with BKT only
6@ : Use without BKT only
7@ : Use disable TPM only
8@ : Use with TCM depop
9@ : Use with ZTE TCM

4 4

MB PCB

Part Number Description

DAA00000Q1L

PCB 03S LA-4151P REV0 M/B

A

10@ : Use with Jetway TCM

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

B

C

DELL CONFIDENTIAL/PROPRIETARY

Title

Size Document Number Rev

D

Date: Sheet

Compal Electronics, Inc.

Cover Sheet

LA-4151P

157Friday, July 04, 2008

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of

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C

D

E

Block Diagram
Compal confidential
Model : JAL10

FAN

1 1

+FAN1_VOUT

page 18 page6page 7

On daughter board

CRT CONN

+5V_RUN

RGB

page 29

SVID

RGB

DPB

SD/MMC/MMC+

CONN

+3.3V_RUN

2 2

DOCKING

page 27

PORT

page 31

DAI

USB[8,9]

SATA3

DOCK LPC BUS

PCIE2 PCIE1

Mini Card2

WLAN

+3.3V_WLAN
+1.5V_RUN +1.5V_RUN

3 3

BKT CONN

+3.3V_BKT_PWR

4 4

USB[4] USB[5] USB[6]

On daughter board

Trough BTB

page 39

1.8V/0.75V

page 44

VCORE (IMVP-6)

page 45

CHARGER

page 46 page 41

ExpressCard

+3.3V_RUN
+1.5V_RUN

Mini Card 1

WWAN

+3.3V_RUN

BKT_USBH

Trough FPC

LVDS CONN

+PWR_SRC
+5V_ALW
+3.3V_RUN

Camera Card

Trough FPC

USB[11]

1.5V/1.05V

A

page 28

PCIE4

Smart Card

PCI Express BUS

page 21page 21

page 32

RFID

Trough FPC

page 19

page 19

page 43

Trough FFC

page 32

Biometric

+3.3V_RUN

BATT IN3V/5V

DC IN

Thermal

GUARDIAN III
EMC4002

+3.3V_SUS

Vedio Switch
TS3DV520ERHUR

+3.3V_RUN

PCI BUS

IDSEL:AD17
(PIRQC#,PIRQD#,GNT#1,REQ#1)

R5C833

+3.3V_RUN

BlueTooth

+3.3V_RUN

73S8009CN

+5V_RUN
+3.3V_RUN

BKT_USBBIO

page 29

page 27

USB[7]

+3.3V_RUN/ +1.5V_RUN 100MHz

page 30

page 32

USBH

Touch Pad

page 41page 42

page 18

LVDS

RGB

page 20

SVID

DPC

+3VRUN 33MHz

IEEE1394

Trough BTB

Option

TPM1.2

For China

page 30

USH

TPM1.2
SSX35BCB
BCM5880

+3.3V_RUN
+2.5V_RUN
+1.2V_RUN

USB[10]

SMBUS

Trough Cable

page 35

Stick

Power Sequence

Power On/Off
SW & LED

B

page 21

page 32

page 37

page 38

Pentium-M

+1.5V_RUN
+1.05V_VCCP
+VCC_CORE

H_A#(3..35) H_D#(0..63)

+3.3V_RUN
+1.8V_RUN
+1.5V_MEM
+1.5V_RUN
+VCC_GFXCORE
+1.05V_M
+1.05V_VCCP

Penryn -4MB
uFCBGA SFF CPU

956pin

System Bus

FSB 800/1066 MHz

INTEL

Cantiga SFF

1363pin BGA

page 10,11,12,13,14,15

DMI

+1.5V_RUN
100MHz

+RTC_CELL
+3.3V_ALW_ICH
+3.3V_RUN
+1.5V_RUN
+1.05V_VCCP

LPC BUS

+3V_RUN
33MHz

INTEL

ICH9-M SFF

569pin BGA

page 22,23,24,25

SMSC KBC
MEC5035

+RTC_CELL
+3.3V_ALW

ECE1077

+3.3V_ALW

page 35

page 34

ECE1088

+3.3V_ALW

Int.KBD &

page 35

Stick

22X22mm

page 7,8,9

25X27mm

16X16mm

SPI

W25X32VSSIG

+3.3V_LAN

W25X32VSSIG

+3.3V_LAN

page 24

16M 4K section

page 24

SPI

DOCK LPC BUS

BC BUS

BC BUSBC BUS

page 35

C

CPU ITP Port

+1.05V_VCCP

Memory BUS
(DDR3)

48MHz

+1.5V_MEM 800 / 1066MHz

USB[3] L SIDE

USB[0] R SIDE

GLCI/LCI

Azalia I/F

S-ATA 0/1

SATA1 SATA0

ODD

+5V_MOD

page 26

SST25VF016B

+3.3V_ALW

page 34

SMSC SIO

ECE5028

+3.3V_ALW

page 33

SATA4

+3V_RUN/ +1.5V_RUN 100MHz

S-HDD

+5V_HDD
+3.3V_RUN

page 26

D

E-SATA

USB Ports X1

+5V_ALW

USB Ports X1

+5V_ALW

Azalia Codec

92HD71B

+3.3V_RUN
+VDDA

Clock Generator
CK505
SLG8LP554

+3.3V_M

DDRII-DIMM X2

BANK 0, 1, 2, 3, 4 ,5 ,6 ,7 ,8

+1.5V_MEM
+0.75V_DDR_VTT

page 29

page 29

page 21

page 16,17

On daughter board

Trough BTB

Intel Boaz
82567LM

+3.3V_ALW
+1.8V_LAN_M

page 21

AMP & INT.
Speaker

+5V_RUN

page 21

HeadPhone &
MIC Jack

+3.3V_RUN

page 21

+1V_LAN_M

page 21

LAN SWITCH
PI3L500-AZFEX

+3.3V_ALW

RJ45

SNIFFER

DAI

+3.3V_RUN

page 21

DOCKSSM2602

Dig. MIC

page 19

Trough cable

DELL CONFIDENTIAL/PROPRIETARY

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

Block Diagram
LA-4151P

257Friday, July 04, 2008

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4

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2

1

POWER STATES

State

D D

S0 (Full ON) / M0

S3 (Suspend to RAM) / M1

S4 (Suspend to DISK) / M1 ON ON ON ONOFF

S5 (SOFT OFF) / M1 ON ON ON ONOFFLOW HIGH LOW HIGHLOW

S3 (Suspend to RAM) / M-OFF

S4 (Suspend to DISK) / M-OFF

S5 (SOFT OFF) / M-OFF

Signal

SLP

SLP

S3#

S4#

HIGH HIGH H IGH

HIGH

LOW HIGH HIGH HIGH ON ON ON ONOFF

LOW HIGH HIGH HIGHLOW

LOW HIGH HIGH HIGH LOW ON ONOFF OFF OFF

LOW LOW LOW LOW ON OFF OFF OFF OFF

LOW LOW LOW LOW LOW ON OFF OFF OFF OFF

SLP
S5#

HIGH

S4
STATE#

SLP
M#

HIGH

HIGH

ALWAYS
PLANE

ON

M
PLANE

ON

SUS

RUN

PLANE

PLANE

ON ON ON

CLOCKS

ICH9-M

USB PORT#

0
1
2
3
4
5
6
7

DESTINATION
JUSB1 (Ext Right Side Top)
BLT mode
None
JESATA1 (Ext Left Side Bottom)
WLAN
WWAN
BT
Express card
DOCKING8

C C

B B

PM TABLE

State

S0

S3

S5 S4/AC

S5 S4/AC don't exist

power
plane

+15V_ALW
+5V_ALW
+3.3V_ALW_ICH
+3.3V_RTC_LDO

ON

ON

+3.3V_SUS
+1.5V_MEM

ON ON

ON

OFF

OFFOFF

+5V_RUN
+3.3V_RUN
+2.5V_RUN
+1.5V_RUN
+1.8V_RUN
+0.75V_DDR_VTT
+VCC_GFXCORE
+VCC_CORE
+1.05V_VCCP

OFFON

OFF

OFF

ON

ON

ON

+3.3V_M

(M-OFF)

ON

OFF

OFF

OFFOFF

+3.3V_M
+1.05V_M +1.05V_M

+3.3V_RUN_
WWAN_PWR

+3.3V_RUN_
BKT_PWR

+3.3V_BKT
_PWR

+INV_PWR_SRC
+LCDVDD

ON

OFF

OFF

OFF

ONON OFF OFF OFF OFFBlackTop mode

PCI EXPRESS

Lane 1
Lane 2
Lane 3
Lane 4
Lane 5
Lane 6

9

11

DESTINATION
MINI CARD-1 WWAN
MINI CARD-2 WLAN
None
EXPRESS CARD
None

None
10/100/1G LAN

DOCKING
USH->BIO10
Camera

PCI TABLE

REQ#/GNT#

R5C833 REQ#1 / GNT#1AD17

A A

PIRQPCI DEVICE IDSEL

PIRQ[C..D]

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

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Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

Index and Config.

LA-4151P

357Friday, July 04, 2008

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RUN_ON

FDS4435

Q16

+INV_PWR_SRC

ADAPTER

D D

GFX_CORE_ON

ADP3209

(PU15)

+VGFX_COREP

BlackTop function

BATTERY

+PWR_SRC

RUN_ON&BKT_GPIO4

STS11NF30L

(Q145)

+5V_RUN_
BKT_PWR

+15V_ALW

CHARGER

C C

ALW_ON

3.3V_SUS_ON

ISL6236

(PU2)

SI3456BDV

(Q60)

(PU7) (PU14)

IMVP_VR_ON

+VCC_CORE +0.75V_DDR_VTT +1.5V_MEM

MAX8794ISL6260

(PU12)

1.8V_RUN_ON

+1.8V_RUN +1.05V_M

TPS51100D
GQRG4

0.75V_DDR_VTT_ON

VT351FC

(PU25,PU26)

ISL6236

(PU2)

1.5V_RUN_ON

DDR_ON

SI4336DY

(Q128)

ALWON

ALWON

+5V_ALW

+3.3V_ALW

ENAB_3VLAN

STS11NF30L

RUN_ON

3.3V_RUN_ON&BKT_GPIO3

3.3V_RUN_ON

(Q44)

STS11NF30L

BKT_GPIO2

SI4336DY

(Q61)

(Q55)

MAX8511(LDO)

(U103)

BlackTop function

SI4336DY

+5V_RUN

+1.5V_ALW_HDA

(Q140)

+5V_ALW

B B

HDDC_EN

MODC_EN

+3.3V_SUS

RUN_ON

1.05V_RUN_ON M_ON

SI4336DY
Q67

+1.5V_RUN

On I/O board

+3.3V_LAN

REGCTL_PNP1

REGCTL_PNP18

+3.3V_RUN

+3.3V_RUN_
BKT_PWR

BCP69BCP69

SI3456BDVSI3456BDV

(Q29)(Q32)

A A

+5V_HDD

+5V_MOD

TPA6040

(U9)

+VDDA

+1.05V_VCCP

(Q4) SI3456BDV

(Q3)

(Q143)

+3.3V_BKT_PWR

+1V_LAN_M

+1.8V_LAN_M

SI4336DY

(Q137)

+3.3V_RUN_
WWAN_PWR

DELL CONFIDENTIAL/PROPRIETARY

on I/O board

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

Power Rail
LA-4151P

457Friday, July 04, 2008

1

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G16

ICH_SMBCLK
ICH_SMBDATA

A13

ICH9-M

D D

E18
A24

AMT_SMBCLK
AMT_SMBDAT

2.2K

2.2K

10K

10K

4

+3.3V_ALW

+3.3V_ALW_ICH

2N7002
2N7002

MEM_SCLK

MEM_SDATA

3

2.2K

2.2K

+3.3V_M

197
195

DIMMA

197
195

DIMMB

SMBUS Address[A0h]

SMBUS Address[A4h]

2

1

8.2K

9493

2A 2A

6

5

DOCK_SMB_CLK
DOCK_SMB_DAT

1A

1A

8.2K

8.2K

8.2K

8
7

LCD_SMBCLK
LCD_SMDATA

C C

1B
1B

+5V_ALW

+3.3V_ALW

6

5

6

5

DOCKING

INVERTER
(JLVDS)

SMBUS Address[48h]Dock_APR
SMBUS Address[70h]DOCK_SPR

SMBUS Address[58h]

2.2K

PBAT_SMBCLK

112

10
9

100
99

98
97

PBAT_SMBDAT

BKT_SMBCLK
BKT_SMBDAT

CARD_SMBCLK
CARD_SMBDAT

KBC

B B

1C1C111

1D
1D

1E
1E

1F
1F

2.2K

2.2K

2.2K

MEC 5035

96

1G

95

1H

2.2K

12

1H

1H

A A

1J
1J

1K
1K

5

CKG_SMBDAT

13

CKG_SMBCLK

106
105

Dedicated JTAG

103
102

Dedicated JTAG

2.2K

9

Charger

10

SMBUS Address[12h]

+3.3V_ALW

+3.3V_ALW

+3.3V_ALW

4

100 ohm
100 ohm

3
4

27
29

BATTERY
CONN

BKT
CONN

2N7002
2N7002

2N7002
2N7002

SMBUS Address[16h]

SMBUS Address[TBD]

2.2K

2.2K
CLK_SDATA

CLK_SCLK

DAI

SMBUS Address[35h]

3

+3.3V_M

17

16

CLK GEN

2N7002
2N7002

2N7002
2N7002

2N7002
2N7002

SMBUS Addr ess[a2h]

2.2K

2.2K

EXP_SMBCLK
EXP_SMBDATA

2.2K

2.2K

WLAN_SMBCLK
WLAN_SMBDATA

2.2K

2.2K

MINI_SMBCLK
MINI_SMBDATA

2

+3.3V_SUS

7
8

Express card

+3.3V_WLAN

30
32

WLAN

+3.3V_RUN

30
32

WWAN

Title

Size Document Number Rev

Date: Sheet

SMBUS Address[TBD]

SMBUS Address[TBD]

SMBUS Address[TBD]

Compal Electronics, Inc.

SMBUS TOPOLOGY
LA-4151P

1

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+3.3V_M

CKG_SMBDAT<21,34,46>

D D

CKG_SMBCLK<21,34,46>

FSC FSB FSA CPU

CLKSEL2 CLKSEL0CLKSEL1

000

*

00

1

0

11

C C

0

1

1

0

11

+3.3V_M

12

R51

@

10K_0402_5%~D

FSA

12

R55

@

10K_0402_5%~D

B B

+3.3V_RUN

+3.3V_M

10K_0402_5%~D

@

12

R43

R1112

10K_0402_5%~D

1 2

PCI_DOCKING

+3.3V_RUN

10K_0402_5%~D

R46

1 2

A A

PCI_SIO

10K_0402_5%~D

12

R54

PCI_ICH

*

*

*

0=UMA

6 1

Q1A
2N7002DW-T/R7_SOT363-6~D

+3.3V_M

1

0

00

1

0

TME

ITP_EN

2
5

Q1B
2N7002DW-T/R7_SOT363-6~D

3

4

SRC

MHz

MHz

100

266

100

133

100

200

100

166

100

333

100

100

100

400

PIN 32

0

overclocking enabled

1

overclocling disabled

PIN 37

0

Pin 5/6 as SRC_10

PCI
MHz

33.3

33.3

33.3

33.3

33.3

33.3

33.3

1 Pin 5/6 as CPU_ITP

FCTSEL1 PIN43 PIN44 PIN47 PIN48

0=UMA

1=DIS

DOT96T DOT96C 96/100M_T 96/100M_C

27M_out 27M SSout SRCT0 SRCC0

2.2K_0402_5%~D

12

R1

Place crystal within
500 mils of CK505

12

2.2K_0402_5%~D

R2

CLK_SDATA

CLK_SCLK

CPU_MCH_BSEL0<8,10>
CPU_MCH_BSEL1<8,10>

CPU_MCH_BSEL2<8,10>

CLK_PCI_TPM_CHA<30>

CLK_ICH_48M<24>

CLK_PCI_5028<33>

CLK_PCI_PCM<27>
CLK_PCI_TPM<32>

CLK_PCI_DOCK<31>

CLK_PCI_5035<34>

CLK_ICH_14M<24>
CLK_TCM_14M<30>
CLK_SIO_14M<33>

MCH_DREFCLK<10>
MCH_DREFCLK#<10>

CLK_PCI_ICH<22>

CLK_PWRGD<24>

1=Disc. GRFX down

5

4

4.7U_0603_6.3V4Z~D

1

@

2

C16

33P_0402_50V8J~D

C17

33P_0402_50V8J~D

MINI1CLK_REQ#
MINI2CLK_REQ#
CLK_3GPLLREQ#
SATA_CLKREQ#
EXPCLK_REQ#

4

1 2

R12 0_0603_5%~D

1 2

R14 0_0603_5%~D

+CK_VDD_MAIN+3.3V_M

+CK_VDD_REF
+CK_VDD_48

CLK_XTAL_IN

CLK_XTAL_OUT

FSC

PCI_SIOCLK_PCI_5028
PCI_TPMCLK_PCI_TPM
PCI_DOCKING

CLKREF

DOT96
DOT96#

PCI_ICHCLK_PCI_ICH

CLK_SCLK

CLK_SDATA

1 2

0.1U_0402_16V4Z~D

C1

0.047U_0402_16V7K~D

C13

1

2

1 2

1 2

1 2

1 2
1 2
1 2

1 2
1 2
1 2

1 2
1 2

+3.3V_RUN

0.1U_0402_16V4Z~D

C10

L1 BK2125HS601-T 0805~D

12

12
12

12

33_0402_5%~D
22_0402_5%~D

22_0402_5%~D
22_0402_5%~D

12

1

2

0.047U_0402_16V4Z~D

1

C12

C11

2

12

12

CLK_ICH_48M FSA
CPU_MCH_BSEL0
CPU_MCH_BSEL1

CPU_MCH_BSEL2

CLK_PCI_PCM

CLK_PCI_DOCK
CLK_PCI_5035 PCI_EC
CLK_ICH_14M

CLK_TCM_14M
CLK_SIO_14M

MCH_DREFCLK
MCH_DREFCLK#

CLK_PWRGD

1 2

R4 10K_0402_5%~D

1 2

R5 10K_0402_5%~D

1 2

R6 10K_0402_5%~D

1 2

R7 10K_0402_5%~D

1 2

R356 10K_0402_5%~D

+CK_VDD_REF+CK_VDD_48

1

2

0.1U_0402_16V4Z~D

1

C9

2

X1

14.31818MHz_20P_1BX14318CC1A~D

12

R17 0_0402_5%~D

R19 33_0402_5%~D
R22 2.2K_0402_5%~D

R24 10K_0402_5%~D
R26 33_0402_5%~D

R30 22_0402_5%~D
R29 22_0402_5%~D
R986 22_0402_5%~D1@
R27 33_0402_5%~D

R32
R33

R1114

1@

R35

R37 33_0402_5%~D
R38 33_0402_5%~D

R41 33_0402_5%~D

3

+CK_VDD_MAIN

1

2

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

0.1U_0402_16V4Z~D

10U_0805_10V4Z~D

1

C3

C2

2

1 2

R10 2.2_0603_5%~D

U1

1

VDD_SRC

49

VDD_SRC

54

VDD_SRC

65

VDD_SRC

30

VDD_PCI

36

VDD_PCI

12

VDD_CPU

18

VDD_REF

40

VDD_48

20

XTAL_IN

19

XTAL_OUT

41

USB_48MHz/FSLA

45

FSL_B/TEST_MODE

23

REF_0/FSL_C/TEST_SEL

34

PCICLK4/FCT_SEL

33

PCICLK3

32

PCICLK2/TME

27

PCICLK1

22

REF_1

43

DOT_96/27M

44

DOT_96#/27M_SS

37

PCICLK_F0/ITP_EN

39

CKPWRGD/PD#

9

NC

16

SMBCLK

17

SMBDAT

4

VSS_SRC

15

VSS_CPU

21

VSS_REF

31

VSS_PCI

35

VSS_PCI

42

VSS_48

68

VSS_SRC

73

THRM_PAD

SLG8LP554VTR_QFN72_10X10~D

1

2

SLG8LP554VTR

0.1U_0402_16V4Z~D

C4

0.1U_0402_16V4Z~D

1

C5

2

+CK_VDD_A

PCI_STP#

CPU_STP#

CPU_ITP/SRC_10

CPU_ITP#/SRC_10#

CLKREQ_9#

CLKREQ_8#

CLKREQ_7#

CLKREQ_6#

CLKREQ_5#

CLKREQ_4#

CLKREQ_3#

CLKREQ_2#

SRC_1/SATA

SRC_1#/SATA#

CLKREQ_1#

LCD_CLK/SRC_0

LCD_CLK#/SRC_0#

1

2

VDD_A
VSS_A

CPU_1

CPU_1#

CPU_0

CPU_0#

SRC_9

SRC_9#

SRC_8

SRC_8#

SRC_7

SRC_7#

SRC_6

SRC_6#

SRC_5

SRC_5#

SRC_4

SRC_4#

SRC_3

SRC_3#

SRC_2

SRC_2#

0.1U_0402_16V4Z~D

C6

7
8

25
24

11
10

14
13

6
5

3
2
72
70
69
71
66
67
38
63
64
62
60
61
29
58
59
57
55
56
28
52
53
26
50
51
46
47
48

2

0.1U_0402_16V4Z~D

1

C7

2

4.7U_0603_6.3V4Z~D

1

C14

2

H_STP_PCI#
H_STP_CPU#

MCH_BCLK CLK_MCH_BCLK
MCH_BCLK#

CPU_BCLK
CPU_BCLK#

CPU_ITP
CPU_ITP#

PCIE_MINI1
PCIE_MINI1#
MINI1CLK_REQ#
PCIE_MINI2
PCIE_MINI2#
MINI2CLK_REQ#
PCIE_ICH
PCIE_ICH#

PCIE_EXP#
EXPCLK_REQ#
MCH_3GPLL

CLK_3GPLLREQ#_R

PCIE_SATA CLK_PCIE_SATA
PCIE_SATA#
SATA_CLKREQ#_R
DOT96_SSC DREF_SSCLK

1 2

R11 33_0402_5%~D

1 2

R13 33_0402_5%~D

1 2

R15 33_0402_5%~D

1 2

R16 33_0402_5%~D

1 2

R18 33_0402_5%~D@

1 2

R21 33_0402_5%~D@

1 2

R23 33_0402_5%~D

1 2

R25 33_0402_5%~D

1 2

R28 33_0402_5%~D

1 2

R31 33_0402_5%~D

1 2

R34 33_0402_5%~D

1 2

R36 33_0402_5%~D

1 2

R408 33_0402_5%~D

1 2

R415 33_0402_5%~D

1 2

R45 33_0402_5%~D

1 2

R47 33_0402_5%~D

1 2

R48 475_0402_1%~D

1 2

R49 33_0402_5%~D

1 2

R52 33_0402_5%~D

1 2

R53 475_0402_1%~D

1 2

R523 33_0402_5%~D

1 2

R670 33_0402_5%~D

2

0.047U_0402_16V4Z~D

1

C15

2

CLK_3GPLLREQ#

1

H_STP_PCI# <24>

H_STP_CPU# <24>

CLK_MCH_BCLK#

CLK_CPU_BCLK
CLK_CPU_BCLK#

CLK_CPU_ITP
CLK_CPU_ITP#

CLK_PCIE_MINI1
CLK_PCIE_MINI1#

CLK_PCIE_MINI2
CLK_PCIE_MINI2#

CLK_PCIE_ICH
CLK_PCIE_ICH#

CLK_PCIE_EXPPCIE_EXP
CLK_PCIE_EXP#

CLK_MCH_3GPLL
CLK_MCH_3GPLL#MCH_3GPLL#

CLK_PCIE_SATA#
SATA_CLKREQ#

DREF_SSCLK#DOT96_SSC#

CLK_MCH_BCLK <10>
CLK_MCH_BCLK# <10>

CLK_CPU_BCLK <7>
CLK_CPU_BCLK# <7>

CLK_CPU_ITP <7>
CLK_CPU_ITP# <7>

CLK_PCIE_MINI1 <21>

CLK_PCIE_MINI1# <21>

MINI1CLK_REQ# <21>

CLK_PCIE_MINI2 <21>
CLK_PCIE_MINI2# <21>

MINI2CLK_REQ# <21>

CLK_PCIE_ICH <24>
CLK_PCIE_ICH# <24>

CLK_PCIE_EXP <28>
CLK_PCIE_EXP# <28>

EXPCLK_REQ# <28>
CLK_MCH_3GPLL <10>

CLK_MCH_3GPLL# <10>

CLK_3GPLLREQ# <10>

CLK_PCIE_SATA <23>

CLK_PCIE_SATA# <23>

SATA_CLKREQ# <24>
DREF_SSCLK <10>
DREF_SSCLK# <10>

DELL CONFIDENTIAL/PROPRIETARY

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

Clock Generator
LA-4151P

657Friday, July 04, 2008

1

1.0

of

5

4

3

2

1

0_0402_5%~D
0_0402_5%~D
0_0402_5%~D
0_0402_5%~D
0_0402_5%~D
0_0402_5%~D

+1.05V_VCCP

ITP_DBRESET#

ITP_BPM_R#1
ITP_BPM_R#2
ITP_BPM_R#3
ITP_BPM_R#4
ITP_BPM_R#5

H_RESET_R#
ITP_TCK

CLK_CPU_ITP
CLK_CPU_ITP#

ITP_TCK
ITP_TRST#

ITP_TMS
ITP_TDI

+1.05V_VCCP

1

2

Place near JITP within 100mil

+3.3V_ALW_ICH

R60 150_0402_5%~D

Place close to JITP within 1ns = 5000 mil

+1.05V_VCCP

R977

@

Place close to CPU within 200 mil

+1.05V_VCCP

1 2

R65 150_0402_5%~D

1 2

R66 649_0402_1%~D

H_A#[3..35]<10>

D D

H_ADSTB#0<10>

H_REQ#0<10>
H_REQ#1<10>
H_REQ#2<10>
H_REQ#3<10>
H_REQ#4<10>

C C

H_ADSTB#1<10>

H_A20M#<23>

H_FERR#<23>

H_IGNNE#<23>
H_STPCLK#<23>

H_INTR<23>
H_NMI<23>
H_SMI#<23>

B B

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_ADSTB#0

H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35 H_THERMDA
H_ADSTB#1

H_A20M#
H_FERR#
H_IGNNE#

H_STPCLK#
H_INTR
H_NMI
H_SMI#

U62A

P2

A[3]#

V4

A[4]#

W1

ADDR GROUP 0

A[5]#

T4

A[6]#

AA1

A[7]#

AB4

A[8]#

T2

A[9]#

AC5

A[10]#

AD2

A[11]#

AD4

A[12]#

AA5

A[13]#

AE5

A[14]#

AB2

A[15]#

AC1

A[16]#

Y4

ADSTB[0]#

R1

REQ[0]#

R5

REQ[1]#

U1

REQ[2]#

P4

REQ[3]#

W5

REQ[4]#

AN1

A[17]#

AM4
AR5

AM2
AU5

AR1
AN5

AG5

AK4
AG1
AT4
AK2
AT2
AH2
AF4
AJ5
AH4

AP4
AJ1

AL1

AP2

F10

AL5

ADDR GROUP 1

A[18]#
A[19]#
A[20]#
A[21]#
A[22]#
A[23]#
A[24]#
A[25]#
A[26]#
A[27]#
A[28]#
A[29]#
A[30]#
A[31]#
A[32]#

THERMAL

A[33]#
A[34]#
A[35]#
ADSTB[1]#

C7

A20M#

ICH

D4

FERR#

THERMTRIP#

IGNNE#

F8

STPCLK#

C9
C5

E5
V2

Y2

J9
F4

H8

H CLK

LINT0
LINT1
SMI#

RSVD01
RSVD02
RSVD03
RSVD04
RSVD05
RSVD06
RSVD07

PENRYN SFF_UFCBGA956~D

ADS#
BNR#

BPRI#

DEFER#

DRDY#
DBSY#

BR0#

IERR#

INIT#

CONTROL

LOCK#

RESET#

RS[0]#
RS[1]#
RS[2]#

TRDY#

HIT#

HITM#

BPM[0]#
BPM[1]#
BPM[2]#
BPM[3]#

PRDY#
PREQ#

XDP/ITP SIGNALS

TRST#

DBR#

PROCHOT#

THERMDA
THERMDC

BCLK[0]
BCLK[1]

TCK
TDO

TMS

H_ADS#

M4

H_BNR#

J5

H_BPRI#

L5

H_DEFER#

N5

H_DRDY#

F38

H_DBSY#

J1

H_BR0#

M2

H_IERR#

B40

H_INIT#

D8

H_LOCK#

N1

H_RESET#

G5

H_RS#0H_REQ#0

K2

H_RS#1

H4

H_RS#2

K4

H_TRDY#

L1

H_HIT#

H2

H_HITM#

F2

ITP_BPM#0

AY8

ITP_BPM#1

BA7

ITP_BPM#2

BA5

ITP_BPM#3

AY2

ITP_BPM#4

AV10

ITP_BPM#5

AV2

ITP_TCK

AV4

ITP_TDI

AW7

TDI

RESERVED

AU1
AW5
AV8
J7

D38
BB34
BD34

B10

A35
C35

ITP_TDO
ITP_TMS
ITP_TRST#
ITP_DBRESET#

EC_CPU_PROCHOT#

H_THERMDC
H_THERMTRIP#
CLK_CPU_BCLK

CLK_CPU_BCLK#

+1.05V_VCCP

1 2

R61 56_0402_5%~D

H_INIT# <23>

H_LOCK# <10>

H_RESET# <10>
H_RS#0 <10>
H_RS#1 <10>
H_RS#2 <10>
H_TRDY# <10>

ITP_DBRESET# <24>

2

C18

@

100P_0402_50V8K~D

1

H_THERMTRIP# <18>

CLK_CPU_BCLK <6>

CLK_CPU_BCLK# <6>

H_ADS# <10>

H_BNR# <10>
H_BPRI# <10>

H_DEFER# <10>

H_DRDY# <10>
H_DBSY# <10>

H_BR0# <10>

H_HIT# <10>

H_HITM# <10>

H_THERMTRIP#

R997

ITP_BPM#0 ITP_BPM_R#0

R998

ITP_BPM#1

R999

12

R56 56_0402_5%~D

+1.05V_VCCP

12

R59
56_0402_5%~D

H_THERMDA <18>

H_THERMDC <18>

H_THERMDA, H_THERMDC routing together,
Trace width / Spacing = 10 / 10 mil

H_THERMTRIP# should connect
to ICH9 and G MCH without
T-ing(no stub )

+1.05V_VCCP

ITP_BPM#2

R1000

ITP_BPM#3

R1001

ITP_BPM#4

R1002

ITP_BPM#5
H_RESET#

R57 124_0402_1%~D

ITP_TDO

1 2
1 2
1 2
1 2
1 2
1 2

1 2

CLK_CPU_ITP<6>
CLK_CPU_ITP#<6>

1 2

R58 22.6_0402_1%~D

Layout Note: for ITP700Flex debug port with a XDP based Run Control Tools

ITP_BPM#[0..5], TCK, and TMS routings
must be a maximum of 1.5ns = 7500 mil

ITP_BPM#[0..5], and TCK to FBO routings
must be length matched to within 50ps = 250 mil

Place R67 close to JITP pin 5
TCK to FBO routing should refer to debug port design guide
H_RESET# should be routed from GMCH with split to ITP conn. Refer to DG page #56

Depop JITP, C19,C20,R62, R64, R67, R977, R65, R66

JITP1

28

VTT1

27

VTT0

26

VTAP

25

DBR#

24

DBA#

23

BPM0#

22

GND5

21

BPM1#

20

GND4

19

BPM2#

18

GND3

17

BPM3#

16

GND2

15

BPM4#

14

GND1

13

BPM5#

12

RESET#

11

FBO

10

GND0

9

BCLKP

8

BCLKN

7

TDO

6

NC2

5

TCK

4

NC1

3

TRST#

2

TMS

1

TDI

0.1U_0402_16V4Z~D

C19

1 2

29

GND6

GND7

MOLEX_52435-2891_28P~D@

30

0.1U_0402_16V4Z~D

1

C20

2

ITP_DBRESET#

ITP_BPM#5

51_0402_1%~D

ITP_TDI

ITP_TRST#

+1.05V_VCCP

1 2

1 2

1 2

H_RESET#

51_0402_1%~D

ITP_TDO

ITP_TMS

ITP_TCK

R1059

@

R62 56_0402_5%~D

R64 39_0402_5%~D

R67 27_0402_5%

Place close to JITP within 200ps = 1000 mil

when JIP connector is depopulated

Place close to CPU within 200ps = 1000 mil

A A

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

Penryn Processor(1/2)
LA-4151P

757Friday, July 04, 2008

1

1.0

of

5

4

3

2

1

+VCC_CORE +VCC_CORE

D D

C C

B B

1 2

Place CAP close to the TEST4 pin

A A

Make sure TEST4 routing is reference
to GND and away from other noisy signals.

1K_0402_5%~D

@

R72

+V_CPU_GTLREF

CPU_MCH_BSEL0<6,10>
CPU_MCH_BSEL1<6,10>
CPU_MCH_BSEL2<6,10>

1K_0402_5%~D

@

R73

1 2

0.1U_0402_16V4Z~D

@

1

C1101

2

H_D#[0..63]<10>

H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15

H_DSTBN#0< 10>
H_DSTBP#0<10>

H_DINV#0<10>

H_DSTBN#1< 10>
H_DSTBP#1<10>

H_DINV#1<10>

T138PAD~D

H_DSTBN#0
H_DSTBP#0
H_DINV#0 H_DINV#2

H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_DSTBN#1
H_DSTBP#1
H_DINV#1 H_DINV#3

TEST1
TEST2
TEST3
TEST4
TEST5
TEST6

CPU_MCH_BSEL0
CPU_MCH_BSEL1
CPU_MCH_BSEL2

TEST1
TEST2

For the purpose of testability, route these signals
through a ground referenced Z0 = 55ohm trace that
ends in a via that is near a GND via and is
accessible through an oscilloscope connection.

TEST4

U62B

F40

D[0]#

G43

D[1]#

E43

D[2]#

J43

D[3]#

H40

D[4]#

H44

D[5]#

G39

D[6]#

E41

D[7]#

L41

D[8]#

K44

D[9]#

N41

D[10]#

T40

D[11]#

M40

D[12]#

G41

D[13]#

M44

D[14]#

L43

D[15]#

K40

DSTBN[0]#

J41

DSTBP[0]#

P40

DINV[0]#

P44

D[16]#

V40

D[17]#

V44

D[18]#

AB44

D[19]#

R41

D[20]#

W41

D[21]#

N43

D[22]#

U41

D[23]#

AA41

D[24]#

AB40

D[25]#

AD40

D[26]#

AC41

D[27]#

AA43

D[28]#

Y40

D[29]#

Y44

D[30]#

T44

D[31]#

U43

DSTBN[1]#

W43

DSTBP[1]#

R43

DINV[1]#

AW43

GTLREF

E37

TEST1

D40

TEST2

C43

TEST3

AE41

TEST4

AY10

TEST5

AC43

TEST6

A37

BSEL[0]

C37

BSEL[1]

B38

BSEL[2]

PENRYN SFF_UFCBGA956~D

T2PAD~D
T3PAD~D

TEST3
TEST5

BCLK BSEL2 BSEL1 BSEL0FSB
133
166

667

200

800 00
1067 266

D[32]#
D[33]#
D[34]#

DATA GROUP 0

D[35]#
D[36]#
D[37]#
D[38]#
D[39]#
D[40]#
D[41]#
D[42]#
D[43]#
D[44]#
D[45]#

DATA GROUP 2DATA GROUP 3

D[46]#

D[47]#
DSTBN[2]#
DSTBP[2]#

DINV[2]#

D[48]#

D[49]#

D[50]#

D[51]#

DATA GROUP 1

D[52]#

D[53]#

D[54]#

D[55]#

D[56]#

D[57]#

D[58]#

D[59]#

D[60]#

D[61]#

D[62]#

D[63]#
DSTBN[3]#
DSTBP[3]#

DINV[3]#
COMP[0]

MISC

COMP[1]
COMP[2]
COMP[3]

DPRSTP#

DPSLP#

DPWR#

PWRGOOD

SLP#

PSI#

AR43
AH40
AF40
AJ43
AG41
AF44
AH44
AM44
AN43
AM40
AK40
AG43
AP40
AN41
AL41
AK44
AL43
AJ41

AV38
AT44
AV40
AU41
AW41
AR41
BA37
BB38
AY36
AT40
BC35
BC39
BA41
BB40
BA35
AU43
AY40
AY38
BC37

AE43
AD44
AE1
AF2

G7
B8
C41
E7
D10
BD10

H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_DSTBN#2
H_DSTBP#2

H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
H_DSTBN#3
H_DSTBP#3

COMP0
COMP1
COMP2
COMP3

H_DPRSTP#
H_DPSLP#
H_DPWR#
H_PWRGOOD
H_CPUSLP#
H_PSI#

H_D#32

AP44

0533 0 1

110

1

000

+V_CPU_GTLREF

H_DSTBN#2 <10>
H_DSTBP#2 <10>

H_DINV#2 <10>

H_DSTBN#3 <10>
H_DSTBP#3 <10>

H_DINV#3 <10>

H_DPRSTP# <10,23,45>

H_DPSLP# <23>

H_DPWR# <10>

H_PWRGOOD <23>

H_CPUSLP# <10>

H_PSI# <45>

+1.05V_VCCP

12

R77
1K_0402_1%~D

12

R78
2K_0402_1%~D

27.4_0402_1%~D

54.9_0402_1%~D

12

R68

Resistor placed within 0.5" of
CPU pin.Trace should be at least
25 mils away from any other
toggling signal. COMP0, COMP2
trace should be 27.4 ohm.
COMP1, COMP3 should be 55
ohm.

54.9_0402_1%~D

12

12

R69

12

R70

27.4_0402_1%~D
R71

U62C

F32

VCC[001]

G33

VCC[002]

H32

VCC[003]

J33

VCC[004]

K32

VCC[005]

L33

VCC[006]

M32

VCC[007]

N33

VCC[008]

P32

VCC[009]

R33

VCC[010]

T32

VCC[011]

U33

VCC[012]

V32

VCC[013]

W33

VCC[014]

Y32

VCC[015]

AA33

VCC[016]

AB32

VCC[017]

AC33

VCC[018]

AD32

VCC[019]

AE33

VCC[020]

AF32

VCC[021]

AG33

VCC[022]

AH32

VCC[023]

AJ33

VCC[024]

AK32

VCC[025]

AL33

VCC[026]

AM32

VCC[027]

AN33

VCC[028]

AP32

VCC[029]

AR33

VCC[030]

AT34

VCC[031]

AT32

VCC[032]

AU33

VCC[033]

AV32

VCC[034]

AY32

VCC[035]

BB32

VCC[036]

BD32

VCC[037]

B28

VCC[038]

B30

VCC[039]

B26

VCC[040]

D28

VCC[041]

D30

VCC[042]

F30

VCC[043]

F28

VCC[044]

H30

VCC[045]

H28

VCC[046]

D26

VCC[047]

F26

VCC[048]

H26

VCC[049]

K30

VCC[050]

K28

VCC[051]

M30

VCC[052]

M28

VCC[053]

K26

VCC[054]

M26

VCC[055]

P30

VCC[056]

P28

VCC[057]

T30

VCC[058]

T28

VCC[059]

V30

VCC[060]

V28

VCC[061]

P26

VCC[062]

T26

VCC[063]

V26

VCC[064]

Y30

VCC[065]

Y28

VCC[066]

AB30

VCC[067]

PENRYN SFF_UFCBGA956~D

AB28

VCC[068]

AD30

VCC[069]

AD28

VCC[070]

Y26

VCC[071]

AB26

VCC[072]

AD26

VCC[073]

AF30

VCC[074]

AF28

VCC[075]

AH30

VCC[076]

AH28

VCC[077]

AF26

VCC[078]

AH26

VCC[079]

AK30

VCC[080]

AK28

VCC[081]

AM30

VCC[082]

AM28

VCC[083]

AP30

VCC[084]

AP28

VCC[085]

AK26

VCC[086]

AM26

VCC[087]

AP26

VCC[088]

AT30

VCC[089]

AT28

VCC[090]

AV30

VCC[091]

AV28

VCC[092]

AY30

VCC[093]

AY28

VCC[094]

AT26

VCC[095]

AV26

VCC[096]

AY26

VCC[097]

BB30

VCC[098]

BB28

VCC[099]

BD30

VCC[100]

J11

VCCP_001
VCCP_002
VCCP_003
VCCP_004
VCCP_005
VCCP_006
VCCP_007
VCCP_008
VCCP_009
VCCP_010
VCCP_011
VCCP_012
VCCP_013
VCCP_014
VCCP_015
VCCP_016

VCCA[01]
VCCA[02]

VID[0]
VID[1]
VID[2]
VID[3]
VID[4]
VID[5]
VID[6]

VCCSENSE

VSSSENSE

E11
G11
J37
K38
L37
N37
P38
R37
U37
V38
W37
AA37
AB38
AC37
AE37

B34
D34

BD8
BC7
BB10
BB8
BC5
BB4
AY4

BD12

BC13

VID0
VID1
VID2
VID3
VID4
VID5
VID6

VCCSENSE

VSSSENSE

1

+

2

Length match within 25 mils, Z0=27.4 ohm

Place R75 and R76 near CPU

+VCC_CORE

1 2

R75 100_0402_1%~D

1 2

R76 100_0402_1%~D

Route VCCSENSE and VSSSENSE trace at

27.4 ohms, 7 mils spacing and R75&R76
keep to pad max 1 inch

+1.05V_VCCP

220U_D2_4VY_R15M~D

C21

CRB was 270uF

VID0 <45>
VID1 <45>
VID2 <45>
VID3 <45>
VID4 <45>
VID5 <45>
VID6 <45>

VCCSENSE <45>

VSSSENSE <45>

VCCSENSE

VSSSENSE

10U_0805_10V4Z~D

0.01U_0402_16V7K~D

+1.5V_RUN

1

1

C23

C22

2

2

VCCSENSE=18mils

1 2

R833 27.4_0402_1%~D@

Reserve for testing
only

DELL CONFIDENTIAL/PROPRIETARY

Layout close CPU PIN AD26
55 ohm, 0.5 inch (max)

5

4

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

Penryn Processor(2/2)
LA-4151P

857Friday, July 04, 2008

1

1.0

of

5

U62E

G25

VSS_164

G23

VSS_165

G21

VSS_166

J25

VSS_167

J23

VSS_168

J21

VSS_169

L25

VSS_170

L23

VSS_171

L21

VSS_172

N25

VSS_173

N23

D D

C C

B B

A A

VSS_174

N21

VSS_175

R25

VSS_176

R23

VSS_177

R21

VSS_178

U25

VSS_179

U23

VSS_180

U21

VSS_181

W25

VSS_182

W23

VSS_183

W21

VSS_184

AA25

VSS_185

AA23

VSS_186

AA21

VSS_187

AC25

VSS_188

AC23

VSS_189

AC21

VSS_190

AE25

VSS_191

AE23

VSS_192

AE21

VSS_193

AG25

VSS_194

AG23

VSS_195

AG21

VSS_196

AJ25

VSS_197

AJ23

VSS_198

AJ21

VSS_199

AL25

VSS_200

AL23

VSS_201

AL21

VSS_202

AN25

VSS_203

AN23

VSS_204

AN21

VSS_205

AR25

VSS_206

AR23

VSS_207

AR21

VSS_208

AU25

VSS_209

AU23

VSS_210

AU21

VSS_211

AW25

VSS_212

AW23

VSS_213

AW21

VSS_214

BA25

VSS_215

BA23

VSS_216

BA21

VSS_217

BC25

VSS_218

BC23

VSS_219

BC21

VSS_220

C17

VSS_221

C19

VSS_222

E19

VSS_223

E17

VSS_224

G19

VSS_225

G17

VSS_226

J19

VSS_227

J17

VSS_228

L19

VSS_229

L17

VSS_230

N19

VSS_231

N17

VSS_232

R19

VSS_233

R17

VSS_234

U19

VSS_235

U17

VSS_236

W19

VSS_237

W17

VSS_238

AA19

VSS_239

AA17

VSS_240

AC19

VSS_241

AC17

VSS_242

AE19

VSS_243

AE17

VSS_244

AG19

VSS_245

AG17

VSS_246

AJ19

VSS_247

AJ17

VSS_248

AL19

VSS_249

AL17

VSS_250

AN19

VSS_251

AN17

VSS_252

AR19

VSS_253

AR17

VSS_254

AU19

VSS_255

AU17

VSS_256

AW19

VSS_257

AW17

VSS_258

BA19

VSS_259

BA17

VSS_260

BC19

VSS_261

BC17

VSS_262

C11

VSS_263

C15

VSS_264

E15

VSS_265

G15

VSS_266

H10

VSS_267

M12

VSS_268

J15

VSS_269

L15

VSS_270

N15

VSS_271

M10

VSS_272

T12

VSS_273

R15

VSS_274

U15

VSS_275

W15

VSS_276

T10

VSS_277

Y12

VSS_278

AD12

VSS_279

PENRYN SFF_UFCBGA956~D

VSS_280
VSS_281
VSS_282
VSS_283
VSS_284
VSS_285
VSS_286
VSS_287
VSS_288
VSS_289
VSS_290
VSS_291
VSS_292
VSS_293
VSS_294
VSS_295
VSS_296
VSS_297
VSS_298
VSS_299
VSS_300
VSS_301
VSS_302
VSS_303
VSS_304
VSS_305
VSS_306
VSS_307
VSS_308
VSS_309
VSS_310
VSS_311
VSS_312
VSS_313
VSS_314
VSS_315
VSS_316
VSS_317
VSS_318
VSS_319
VSS_320
VSS_321
VSS_322
VSS_323
VSS_324
VSS_325
VSS_326
VSS_327
VSS_328
VSS_329
VSS_330
VSS_331
VSS_332
VSS_333
VSS_334
VSS_335
VSS_336
VSS_337
VSS_338
VSS_339
VSS_340
VSS_341
VSS_342
VSS_343
VSS_344
VSS_345
VSS_346
VSS_347
VSS_348
VSS_349
VSS_350
VSS_351
VSS_352
VSS_353
VSS_354
VSS_355
VSS_356
VSS_357
VSS_358
VSS_359
VSS_360
VSS_361
VSS_362
VSS_363
VSS_364
VSS_365
VSS_366
VSS_367
VSS_368
VSS_369
VSS_370
VSS_371
VSS_372
VSS_373
VSS_374
VSS_375
VSS_376
VSS_377
VSS_378
VSS_379
VSS_380
VSS_381
VSS_382
VSS_383
VSS_384
VSS_385
VSS_386
VSS_387
VSS_388
VSS_389
VSS_390
VSS_391
VSS_392
VSS_393
VSS_394
VSS_395

AA15
AC15
Y10
AD10
AH12
AE15
AG15
AJ15
AH10
AM12
AL15
AN15
AR15
AM10
AT12
AV12
AW13
AW11
AY12
AU15
AW15
AT10
BA13
BA11
BB12
BC11
BA15
BC15
B6
D6
E9
F6
G9
H6
K8
K6
M8
M6
P8
P6
T8
T6
V8
V6
U5
Y8
Y6
AB8
AB6
AD8
AD6
AF8
AF6
AH8
AH6
AK8
AK6
AM8
AM6
AP8
AP6
AT8
AT6
AU9
AV6
AU7
AW9
AY6
BA9
BB6
BC9
BD6
B4
C3
E3
G3
J3
L3
N3
R3
U3
W3
AA3
AC3
AE3
AG3
AJ3
AL3
AN3
AR3
AU3
AW3
BA3
BC3
D2
E1
G1
AW1
BA1
BB2
A41
A39
A29
A27
A31
A25
A23
A21
A19
A17
A11
A15
A7
A5
A9
BD4

5

+VCC_CORE

+1.05V_VCCP

U62F

BD28

VCC_101

BB26

VCC_102

BD26

VCC_103

B22

VCC_104

B24

VCC_105

D22

VCC_106

D24

VCC_107

F24

VCC_108

F22

VCC_109

H24

VCC_110

H22

VCC_111

K24

VCC_112

K22

VCC_113

M24

VCC_114

M22

VCC_115

P24

VCC_116

P22

VCC_117

T24

VCC_118

T22

VCC_119

V24

VCC_120

V22

VCC_121

Y24

VCC_122

Y22

VCC_123

AB24

VCC_124

AB22

VCC_125

AD24

VCC_126

AD22

VCC_127

AF24

VCC_128

AF22

VCC_129

AH24

VCC_130

AH22

VCC_131

AK24

VCC_132

AK22

VCC_133

AM24

VCC_134

AM22

VCC_135

AP24

VCC_136

AP22

VCC_137

AT24

VCC_138

AT22

VCC_139

AV24

VCC_140

AV22

VCC_141

AY24

VCC_142

AY22

VCC_143

BB24

VCC_144

BB22

VCC_145

BD24

VCC_146

BD22

VCC_147

B16

VCC_148

B18

VCC_149

B20

VCC_150

D16

VCC_151

D18

VCC_152

F18

VCC_153

F16

VCC_154

H18

VCC_155

H16

VCC_156

D20

VCC_157

F20

VCC_158

H20

VCC_159

K18

VCC_160

K16

VCC_161

M18

VCC_162

M16

VCC_163

K20

VCC_164

M20

VCC_165

P18

VCC_166

P16

VCC_167

T18

VCC_168

T16

VCC_169

V18

VCC_170

V16

VCC_171

P20

VCC_172

T20

VCC_173

V20

VCC_174

Y18

VCC_175

Y16

VCC_176

AB18

VCC_177

AB16

VCC_178

AD18

VCC_179

AD16

VCC_180

Y20

VCC_181

AB20

VCC_182

AD20

VCC_183

AF18

VCC_184

AF16

VCC_185

AH18

VCC_186

AH16

VCC_187

AF20

VCC_188

AH20

VCC_189

AK18

VCC_190

AK16

VCC_191

AM18

VCC_192

AM16

VCC_193

AP18

VCC_194

AP16

VCC_195

AK20

VCC_196

AM20

VCC_197

AP20

VCC_198

AT18

VCC_199

AT16

VCC_200

AV18

VCC_201

AV16

VCC_202

AY18

VCC_203

AY16

VCC_204

AT20

VCC_205

AV20

VCC_206

AY20

VCC_207

BB18

VCC_208

BB16

VCC_209

BD18

VCC_210

BD16

VCC_211

BB20

VCC_212

BD20

VCC_213

AM14

VCC_214

AP14

VCC_215

AT14

VCC_216

AV14

VCC_217

AY14

VCC_218

BB14

VCC_219

BD14

VCC_220

AF38

VCCP_017

AG37

VCCP_018

AJ37

VCCP_019

AK38

VCCP_020

PENRYN S FF _U FC BG A 956~D

VCCP_021
VCCP_022
VCCP_023
VCCP_024
VCCP_025
VCCP_026
VCCP_027
VCCP_028
VCCP_029
VCCP_030
VCCP_031
VCCP_032
VCCP_033
VCCP_034
VCCP_035
VCCP_036
VCCP_037
VCCP_038
VCCP_039
VCCP_040
VCCP_041
VCCP_042
VCCP_043
VCCP_044
VCCP_045
VCCP_046
VCCP_047
VCCP_048
VCCP_049
VCCP_050
VCCP_051
VCCP_052
VCCP_053
VCCP_054
VCCP_055
VCCP_056
VCCP_057
VCCP_058
VCCP_059
VCCP_060
VCCP_061
VCCP_062
VCCP_063
VCCP_064
VCCP_065
VCCP_066
VCCP_067
VCCP_068
VCCP_069
VCCP_070
VCCP_071
VCCP_072
VCCP_073
VCCP_074
VCCP_075
VCCP_076
VCCP_077
VCCP_078
VCCP_079
VCCP_080
VCCP_081
VCCP_082
VCCP_083
VCCP_084
VCCP_085
VCCP_086
VCCP_087
VCCP_088
VCCP_089
VCCP_090
VCCP_091
VCCP_092
VCCP_093
VCCP_094
VCCP_095
VCCP_096
VCCP_097
VCCP_098
VCCP_099
VCCP_100
VCCP_101
VCCP_102
VCCP_103
VCCP_104
VCCP_105
VCCP_106
VCCP_107
VCCP_108
VCCP_109
VCCP_110
VCCP_111
VCCP_112
VCCP_113
VCCP_114
VCCP_115
VCCP_116
VCCP_117
VCCP_118
VCCP_119
VCCP_120
VCCP_121
VCCP_122
VCCP_123
VCCP_124
VCCP_125
VCCP_126
VCCP_127
VCCP_128
VCCP_129
VCCP_130
VCCP_131
VCCP_132
VCCP_133
VCCP_134
VCCP_135
VCCP_136
VCCP_137
VCCP_138
VCCP_139
VCCP_140
VCCP_141
VCCP_142
VCCP_143
VCCP_144
VCCP_145

AL37
AN37
AP38
B32
C33
D32
E35
E33
F34
G35
F36
H36
J35
L35
N35
K36
R35
U35
P36
V36
W35
AA35
AC35
AB36
AE35
AG35
AJ35
AF36
AL35
AN35
AK36
AP36
B12
B14
C13
D12
D14
E13
F14
F12
G13
H14
H12
J13
K14
K12
L13
L11
M14
N13
N11
K10
P14
P12
R13
R11
T14
U13
U11
V14
V12
W13
W11
P10
V10
Y14
AA13
AA11
AB14
AB12
AC13
AC11
AD14
AB10
AE13
AE11
AF14
AF12
AG13
AG11
AH14
AJ13
AJ11
AF10
AK14
AK12
AL13
AL11
AN13
AN11
AP12
AR13
AR11
AK10
AP10
AU13
AU11
L9
L7
N9
N7
R9
R7
U9
U7
W9
W7
AA9
AA7
AC9
AC7
AE9
AE7
AG9
AG7
AJ9
AJ7
AL9
AL7
AN9
AN7
AR9
AR7
A33
A13

+1.05V_VCCP

4

U62D

B42

VSS[001]

F44

VSS[002]

D44

VSS[003]

D42

VSS[004]

F42

VSS[005]

H42

VSS[006]

K42

VSS[007]

M42

VSS[008]

P42

VSS[009]

T42

VSS[010]

V42

VSS[011]

Y42

VSS[012]

AB42

VSS[013]

AD42

VSS[014]

AF42

VSS[015]

AH42

VSS[016]

AK42

VSS[017]

AM42

VSS[018]

AP42

VSS[019]

AY44

VSS[020]

AV44

VSS[021]

AT42

VSS[022]

AV42

VSS[023]

AY42

VSS[024]

BA43

VSS[025]

BB42

VSS[026]

C39

VSS[027]

E39

VSS[028]

G37

VSS[029]

H38

VSS[030]

J39

VSS[031]

L39

VSS[032]

M38

VSS[033]

N39

VSS[034]

R39

VSS[035]

T38

VSS[036]

U39

VSS[037]

W39

VSS[038]

Y38

VSS[039]

AA39

VSS[040]

AC39

VSS[041]

AD38

VSS[042]

AE39

VSS[043]

AG39

VSS[044]

AH38

VSS[045]

AJ39

VSS[046]

AL39

VSS[047]

AM38

VSS[048]

AN39

VSS[049]

AR39

VSS[050]

AR37

VSS[051]

AT38

VSS[052]

AU39

VSS[053]

AU37

VSS[054]

AW39

VSS[055]

AW37

VSS[056]

BA39

VSS[057]

BC41

VSS[058]

BD40

VSS[059]

BD38

VSS[060]

B36

VSS[061]

H34

VSS[062]

D36

VSS[063]

K34

VSS[064]

M34

VSS[065]

M36

VSS[066]

P34

VSS[067]

T34

VSS[068]

V34

VSS[069]

T36

VSS[070]

Y34

VSS[071]

AB34

VSS[072]

AD34

VSS[073]

Y36

VSS[074]

AD36

VSS[075]

AF34

VSS[076]

AH34

VSS[077]

AH36

VSS[078]

AK34

VSS[079]

AM34

VSS[080]

AP34

VSS[081]

PENRYN SFF_UFCBGA956~D

4

VSS[082]
VSS[083]
VSS[084]
VSS[085]
VSS[086]
VSS[087]
VSS[088]
VSS[089]
VSS[090]
VSS[091]
VSS[092]
VSS[093]
VSS[094]
VSS[095]
VSS[096]
VSS[097]
VSS[098]
VSS[099]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
VSS[159]
VSS[160]
VSS[161]
VSS[162]
VSS[163]

AM36
AR35
AU35
AV34
AW35
AW33
AY34
AT36
AV36
BA33
BC33
BB36
BD36
C27
C29
C31
E29
E27
G29
G27
E31
G31
J29
J27
L29
L27
N29
N27
J31
L31
N31
R29
R27
U29
U27
R31
U31
W29
W27
W31
AA29
AA27
AC29
AC27
AA31
AC31
AE29
AE27
AG29
AG27
AJ29
AJ27
AE31
AG31
AJ31
AL29
AL27
AN29
AN27
AL31
AN31
AR29
AR27
AR31
AU29
AU27
AW29
AW27
AU31
AW31
BA29
BA27
BC29
BC27
BA31
BC31
C21
C23
C25
E25
E23
E21

+VCC_CORE

Place these inside
socket cavity on L8
(North side
Secondary)

+VCC_CORE

Place these inside
socket cavity on L8
(Sorth side
Secondary)

+VCC_CORE

Place these inside
socket cavity on L8
(North side
Primary)

Place these inside
socket cavity on L8
(Sorth side
Primary)

1

C24
10U_0805_4VAM~D

2

1

C34
10U_0805_4VAM~D

2

1

C44
10U_0805_4VAM~D

2

+VCC_CORE

1

@

C50
10U_0805_4VAM~D

2

South Side Secondary

+1.05V_VCCP

1

2

+VCC_CORE

2

1

+VCC_CORE

2

1

3

1

C25
10U_0805_4VAM~D

2

1

C35
10U_0805_4VAM~D

2

1

C45
10U_0805_4VAM~D

2

1

@

C51
10U_0805_4VAM~D

2

+VCC_CORE

C62

0.1U_0402_10V7K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

2

@

@

C1177

C1176

1

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

2

@

@

C1190

C1191

1

3

2

1

C26
10U_0805_4VAM~D

2

1

C36
10U_0805_4VAM~D

2

1

C46
10U_0805_4VAM~D

2

1

C52
10U_0805_4VAM~D

2

270U_D_2VM_R4.5M~D

270U_D_2VM_R4.5M~D

1

1

+

2

C57

C56

+

2

1

C63

0.1U_0402_10V7K~D

2

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

2

2

@

@

C1178

C1179

1

1

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

2

2

@

@

C1192

C1193

1

1

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

270U_D_2VM_R4.5M~D

1

+

2

1

2

1U_0402_6.3V6K~D

2

@

C1180

1

1U_0402_6.3V6K~D

2

@

C1194

1

1

C27
10U_0805_4VAM~D

2

1

C37
10U_0805_4VAM~D

2

1

@

C48
10U_0805_4VAM~D

2

1

@

C53
10U_0805_4VAM~D

2

C58

C64

0.1U_0402_10V7K~D

1U_0402_6.3V6K~D

2

@

C1181

1

1U_0402_6.3V6K~D

2

@

C1195

1

1U_0402_6.3V6K~D

2

@

1

1U_0402_6.3V6K~D

2

@

1

1

2

1

2

1

2

1

C65

0.1U_0402_10V7K~D

2

1U_0402_6.3V6K~D

2

C1182

1

1U_0402_6.3V6K~D

2

C1196

1

C28
10U_0805_4VAM~D

C38
10U_0805_4VAM~D

@

C49
10U_0805_4VAM~D

1

@

C54
10U_0805_4VAM~D

2

2

@

C1183

1

2

@

C1197

1

1

C29
10U_0805_4VAM~D

2

1

C39
10U_0805_4VAM~D

2

1

@

C55
10U_0805_4VAM~D

2

High Frequence Decoupling

10uF 0805 X6S -> 85 degree C

1

C66

0.1U_0402_10V7K~D

2

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

2

@

@

C1184

C1185

+VCC_CORE

1

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

2

@

@

C1199

C1198

1

2

1

C30
10U_0805_4VAM~D

2

1

C40
10U_0805_4VAM~D

2

1

C67

0.1U_0402_10V7K~D

2

1

C31
10U_0805_4VAM~D

2

1

C41
10U_0805_4VAM~D

2

Place these inside
socket cavity on L8
(North side
Secondary)

1

2

1

2

High Frequence CAP for ULV CPU

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

2

2

@

@

C1187

C1186

1

1

1U_0402_6.3V6K~D

2

2

@

@

C1188

C1189

1

1

DELL CONFIDENTIAL/PROPRIETARY

Title

Size Doc um e n t N u mb er Re v

Date: Sheet

Compal Electronics, Inc.

CPU Bypass

LA-4151P

1

C32
10U_0805_4VAM~D

C42
10U_0805_4VAM~D

1

1

C33
10U_0805_4VAM~D

2

1

C43
10U_0805_4VAM~D

2

957Friday, July 04, 2008

of

1.0

5

H_D#[0..63]<8>

D D

C C

1 2

B B

A A

R82 24.9_0402_1%~D

+1.05V_VCCP

+H_VREF

R94

2K_0402_1%~D

+1.05V_VCCP

H_SWNG

100_0402_1%~D

R95

H_RESET#<7>

H_CPUSLP#<8>

12

R90
1K_0402_1%~D

12

1

2

12

R91
221_0402_1%~D

12

1

2

H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20

H_D#21

H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29

H_D#30

H_D#31
H_D#32

H_D#33

H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44

H_D#45
H_D#46
H_D#47

H_D#48
H_D#49

H_D#50

H_D#51

H_D#52

H_D#53

H_D#54

H_D#55

H_D#56

H_D#57

H_D#58

H_D#59

H_D#60

H_D#61

H_D#62

H_D#63

H_SWNG
+H_RCOMP

H_RESET#
H_CPUSLP#

+H_VREF

0.1U_0402_16V4Z~D

@

C73

+1.05V_VCCP

0.1U_0402_16V4Z~D

C74

MCH_TSATN#

5

U78A

J7

H_D#_0

H6

H_D#_1

L11

H_D#_2

J3

H_D#_3

H4

H_D#_4

G3

H_D#_5

K10

H_D#_6

K12

H_D#_7

L1

H_D#_8

M10

H_D#_9

M6

H_D#_10

N11

H_D#_11

L7

H_D#_12

K6

H_D#_13

M4

H_D#_14

K4

H_D#_15

P6

H_D#_16

W9

H_D#_17

V6

H_D#_18

V2

H_D#_19

P10

H_D#_20

W7

H_D#_21

N9

H_D#_22

P4

H_D#_23

U9

H_D#_24

V4

H_D#_25

U1

H_D#_26

W3

H_D#_27

V10

H_D#_28

U7

H_D#_29

W11

H_D#_30

U11

H_D#_31

AC11

H_D#_32

AC9

H_D#_33

Y4

H_D#_34

Y10

H_D#_35

AB6

H_D#_36

AA9

H_D#_37

AB10

H_D#_38

AA1

H_D#_39

AC3

H_D#_40

AC7

H_D#_41

AD12

H_D#_42

AB4

H_D#_43

Y6

H_D#_44

AD10

H_D#_45

AA11

H_D#_46

AB2

H_D#_47

AD4

H_D#_48

AE7

H_D#_49

AD2

H_D#_50

AD6

H_D#_51

AE3

H_D#_52

AG9

H_D#_53

AG7

H_D#_54

AE11

H_D#_55

AK6

H_D#_56

AF6

H_D#_57

AJ9

H_D#_58

AH6

H_D#_59

AF12

H_D#_60

AH4

H_D#_61

AJ7

H_D#_62

AE9

H_D#_63

B6

H_SWING

D4

H_RCOMP

J11

H_CPURST#

G9

H_CPUSLP#

L17

H_AVREF

K18

H_DVREF

CANTIGA GMCH SFF_ FCBG A1363~D

+3.3V_RUN

12

R101

54.9_0402_1%~D

1 2

2

B

R104
330_0402_5%~D

MMST3904-7-F_SOT323-3~D

Q4

+3.3V_RUN

HOST

1K_0402_5%~D

12

1K_0402_5%~D

12

R98

C

2

B

E

C

3 1

Q3

E

MMST3904-7-F_SOT323-3~D

3 1

R180 2.2K_0402_5%~D
R181 2.2K_0402_5%~D
R182 2.2K_0402_5%~D
R183 2.2K_0402_5%~D

Place close to U78.
F34,F32,B38,A37

R99

MCH_TSATN_EC <33>

12
12
12
12

H_A#_3
H_A#_4
H_A#_5
H_A#_6
H_A#_7
H_A#_8

H_A#_9
H_A#_10
H_A#_11
H_A#_12
H_A#_13
H_A#_14
H_A#_15
H_A#_16
H_A#_17
H_A#_18
H_A#_19
H_A#_20
H_A#_21
H_A#_22
H_A#_23
H_A#_24
H_A#_25
H_A#_26
H_A#_27
H_A#_28
H_A#_29
H_A#_30
H_A#_31
H_A#_32
H_A#_33
H_A#_34
H_A#_35

H_ADS#
H_ADSTB#_0
H_ADSTB#_1

H_BNR#

H_BPRI#

H_BREQ#

H_DEFER#

H_DBSY#

HPLL_CLK

HPLL_CLK#

H_DPWR#

H_DRDY#

H_HIT#

H_HITM#
H_LOCK#
H_TRDY#

H_DINV#_0
H_DINV#_1
H_DINV#_2
H_DINV#_3

H_DSTBN#_0
H_DSTBN#_1
H_DSTBN#_2
H_DSTBN#_3

H_DSTBP#_0
H_DSTBP#_1
H_DSTBP#_2
H_DSTBP#_3

H_REQ#_0
H_REQ#_1
H_REQ#_2
H_REQ#_3
H_REQ#_4

H_RS#_0

H_RS#_1

H_RS#_2

4

SDVO_CTRLCLK
SDVO_CTRLDATA
DDPC_CTRLCLK
DDPC_CTRLDATA

L15
B14
C15
D12
F14
G17
B12
J15
D16
C17
D14
K16
F16
B16
C21
D18
J19
J21
B18
D22
G19
J17
L21
L19
G21
D20
K22
F18
K20
F20
F22
B20
A19

F10
A15
C19
C9
B8
C11
E5
D6
AH10
AJ11
G11
H2
C7
F8
A11
D8

L9
N7
AA7
AG3

K2
N3
AA3
AF4

L3
M2
Y2
AF2

J13
L13
C13
G13
G15

F4
F2
G7

4

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35

H_ADS#
H_ADSTB#0
H_ADSTB#1
H_BNR#
H_BPRI#
H_BR0#
H_DEFER#
H_DBSY#
CLK_MCH_BCLK
CLK_MCH_BCLK#
H_DPWR#
H_DRDY#
H_HIT#
H_HITM#
H_LOCK#
H_TRDY#

H_DINV#0
H_DINV#1
H_DINV#2
H_DINV#3

H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3

H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

H_RS#0
H_RS#1
H_RS#2

ICH_AZ_MCH_BITCLK<23>
ICH_AZ_MCH_RST#<23>

ICH_AZ_MCH_SDIN2<23>
ICH_AZ_MCH_SDOUT<23>
ICH_AZ_MCH_SYNC<23>

H_A#[3..35] <7>

+1.5V_MEM

R79 80.6_0402_1%~D
R80 80.6_0402_1%~D

+V_DDR_MCH_REF

H_ADS# <7>

H_ADSTB#0 <7>

H_ADSTB#1 <7>
H_BNR# <7>
H_BPRI# <7>
H_BR0# <7>
H_DEFER# <7>
H_DBSY# <7>

CLK_MCH_BCLK <6>

CLK_MCH_BCL K# <6>
H_DPWR# <8>
H_DRDY# <7>

H_HIT# <7>
H_HITM# <7>
H_LOCK# <7>

H_TRDY# <7>

H_DINV#0 <8>
H_DINV#1 <8>
H_DINV#2 <8>
H_DINV#3 <8>

H_DSTBN#0 <8>
H_DSTBN#1 <8>
H_DSTBN#2 <8>
H_DSTBN#3 <8>

H_DSTBP#0 <8>
H_DSTBP#1 <8>
H_DSTBP#2 <8>
H_DSTBP#3 <8>

H_REQ#0 <7>
H_REQ#1 <7>
H_REQ#2 <7>
H_REQ#3 <7>
H_REQ#4 <7>

H_RS#0 <7>
H_RS#1 <7>
H_RS#2 <7>

ICH_AZ_MCH_BITCLK
ICH_AZ_MCH_RST#
ICH_AZ_MCH_SDIN2
ICH_AZ_MCH_SDOUT
ICH_AZ_MCH_SYNC

+1.05V_M

510_0402_5%~D

R87

1

2

12

12

3

12
12

0.1U_0402_16V4Z~D

C68

1K_0402_1%~D

R83

1

2

M_CLK_DDR0<16>
M_CLK_DDR1<16>
M_CLK_DDR2<17>
M_CLK_DDR3<17>

M_CLK_DDR#0<16>
M_CLK_DDR#1<16>
M_CLK_DDR#2<17>
M_CLK_DDR#3<17>

DDR_CKE0_DIMMA<16>
DDR_CKE1_DIMMA<16>
DDR_CKE2_DIMMB<17>
DDR_CKE3_DIMMB<17>

DDR_CS0_DIMMA#<16>
DDR_CS1_DIMMA#<16>
DDR_CS2_DIMMB#<17>
DDR_CS3_DIMMB#<17>

SMRCOMP
SMRCOMP#

0.1U_0402_16V4Z~D
R81 499_0402_1%~D

1 2

1

2

0.1U_0402_16V4Z~D
C70

R685 33_0402_5%~D

C69

1 2

SM_DRAMRST#<16,17>

MCH_DREFCLK<6>

MCH_DREFCLK#<6>

DREF_SSCLK<6>

DREF_SSCLK#<6>

CLK_MCH_3GPLL<6>
CLK_MCH_3GPLL#<6>

DMI_MRX_ITX_N0<24>
DMI_MRX_ITX_N1<24>
DMI_MRX_ITX_N2<24>
DMI_MRX_ITX_N3<24>

DMI_MRX_ITX_P0<24>
DMI_MRX_ITX_P1<24>
DMI_MRX_ITX_P2<24>
DMI_MRX_ITX_P3<24>

DMI_MTX_IRX_N0<24>
DMI_MTX_IRX_N1<24>
DMI_MTX_IRX_N2<24>
DMI_MTX_IRX_N3<24>

DMI_MTX_IRX_P0<24>
DMI_MTX_IRX_P1<24>
DMI_MTX_IRX_P2<24>
DMI_MTX_IRX_P3<24>

GFX_VR_ON<47>

CL_CLK0<24>
CL_DATA0<24>

ICH_CL_PWROK<24,34>

CL_RST0#<24>

DDPC_CTRLCLK<21>
DDPC_CTRLDATA<21>
SDVO_CTRLCLK<21>
SDVO_CTRLDATA<21>

CLK_3GPLLREQ#<6>
MCH_ICH_SYNC#<24>

M_ODT0<16>
M_ODT1<16>
M_ODT2<17>
M_ODT3<17>

GFX_VID0<47>
GFX_VID1<47>
GFX_VID2<47>
GFX_VID3<47>
GFX_VID4<47>

M_CLK_DDR0
M_CLK_DDR1
M_CLK_DDR2
M_CLK_DDR3

M_CLK_DDR#0
M_CLK_DDR#1
M_CLK_DDR#2
M_CLK_DDR#3

DDR_CKE0_DIMMA
DDR_CKE1_DIMMA
DDR_CKE2_DIMMB
DDR_CKE3_DIMMB

DDR_CS0_DIMMA#
DDR_CS1_DIMMA#
DDR_CS2_DIMMB#
DDR_CS3_DIMMB#

M_ODT0
M_ODT1
M_ODT2
M_ODT3

SMRCOMP
SMRCOMP#

SMRCOMP_VOH
SMRCOMP_VOL

+V_DDR_MCH_REF

SM_PWROK
SM_DRAMRST#
MCH_DREFCLK

MCH_DREFCLK#
DREF_SSCLK
DREF_SSCLK#

CLK_MCH_3GPLL
CLK_MCH_3GPLL#

DMI_MRX_ITX_N0
DMI_MRX_ITX_N1
DMI_MRX_ITX_N2
DMI_MRX_ITX_N3

DMI_MRX_ITX_P0
DMI_MRX_ITX_P1
DMI_MRX_ITX_P2
DMI_MRX_ITX_P3

DMI_MTX_IRX_N0
DMI_MTX_IRX_N1
DMI_MTX_IRX_N2
DMI_MTX_IRX_N3

DMI_MTX_IRX_P0
DMI_MTX_IRX_P1
DMI_MTX_IRX_P2
DMI_MTX_IRX_P3

GFX_VID0
GFX_VID1
GFX_VID2
GFX_VID3
GFX_VID4

GFX_VR_ON

CL_CLK0
CL_DATA0
ICH_CL_PWROK
CL_RST0#
+CL_VREF

DDPC_CTRLCLK
DDPC_CTRLDATA
SDVO_CTRLCLK
SDVO_CTRLDATA
CLK_3GPLLREQ#
MCH_ICH_SYNC#

MCH_TSATN#

ICH_AZ_MCH_SDIN2_R

BB32
BA25
BA33

BA23

BA31
BC25
BC33

BB24

BC35
BE33
BE37
BC37

BK18
BK16
BE23
BC19

BJ17
BJ19
BC17
BE17

BL25
BK26

BK32

BL31

BC51
AY37
BH20
BA37

AG55

AL49
AH54

AL47
AG53

AK50
AH52

AL45
AG49

AJ49

AJ47
AG47

AF50
AH50

AJ45
AG45

AK52
AK54

AW40

AL53

AL55

B42
D42
B50
D50

R49
P50

G33
G37
F38
F36
G35

G39

F34
F32
B38
A37
C31
K42

D10

C29
B30
D28
A27
B28

SA_CK_0
SA_CK_1
SB_CK_0
SB_CK_1

SA_CK#_0
SA_CK#_1
SB_CK#_0
SB_CK#_1

SA_CKE_0
SA_CKE_1
SB_CKE_0
SB_CKE_1

SA_CS#_0
SA_CS#_1
SB_CS#_0
SB_CS#_1

SA_ODT_0
SA_ODT_1
SB_ODT_0
SB_ODT_1

SM_RCOMP
SM_RCOMP#

SM_RCOMP_VOH
SM_RCOMP_VOL

SM_VREF
SM_PWROK
SM_REXT
SM_DRAMRST#

DPLL_REF_CLK
DPLL_REF_CLK#
DPLL_REF_SSCLK
DPLL_REF_SSCLK#

PEG_CLK
PEG_CLK#

DMI_RXN_0
DMI_RXN_1
DMI_RXN_2
DMI_RXN_3

DMI_RXP_0
DMI_RXP_1
DMI_RXP_2
DMI_RXP_3

DMI_TXN_0
DMI_TXN_1
DMI_TXN_2
DMI_TXN_3

DMI_TXP_0
DMI_TXP_1
DMI_TXP_2
DMI_TXP_3

GFX_VID_0
GFX_VID_1
GFX_VID_2
GFX_VID_3
GFX_VID_4

GFX_VR_EN

CL_CLK
CL_DATA
CL_PWROK
CL_RST#
CL_VREF

DDPC_CTRLCLK
DDPC_CTRLDATA
SDVO_CTRLCLK
SDVO_CTRLDATA
CLKREQ#
ICH_SYNC#

TSATN#

HDA_BCLK
HDA_RST#
HDA_SDI
HDA_SDO
HDA_SYNC

HD support 1.5V

THERMTRIP_MCH#

PLTRST1#_R

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

1 2

R102 56_0402_5%~D

12

R100 100_0402_5%~D

+1.05V_VCCP

PLTRST1# <22,28>

2

DDR CLK/ CONTROL/COMPENSATION

CLK

CFGRSVD

DMI

PM

GRAPHICS VID

ME

NC

MISC

HDA

CANTIGA GMCH SFF_ FCBG A1363~D

RSVD1
RSVD2
RSVD3
RSVD4
RSVD5
RSVD6
RSVD7
RSVD8
RSVD9

RSVD14
RSVD15

RSVD17

RSVD20

RSVD22
RSVD23
RSVD24
RSVD25

ME_JTAG_TCK

ME_JTAG_TDI
ME_JTAG_TDO
ME_JTAG_TMS

CFG_0
CFG_1
CFG_2
CFG_3
CFG_4
CFG_5
CFG_6
CFG_7
CFG_8

CFG_9
CFG_10
CFG_11
CFG_12
CFG_13
CFG_14
CFG_15
CFG_16
CFG_17
CFG_18
CFG_19
CFG_20

PM_SYNC#

PM_DPRSTP#
PM_EXT_TS#_0
PM_EXT_TS#_1

PWROK

RSTIN#

THERMTRIP#

DPRSLPVR

NC_1
NC_2
NC_3
NC_4
NC_5
NC_6
NC_7
NC_8

NC_9
NC_10
NC_11
NC_12
NC_13
NC_14
NC_15
NC_16
NC_17
NC_18
NC_19
NC_20
NC_21
NC_22

U78B

J43
L43
J41
L41
AN11
AM10
AK10
AL11
F12

C27
D30

J9

AW42

BB20
BE19
BF20
BF18

AN45
AP44
AT44
AN47

SM_PWROK

K26
G23
G25
J25
L25
L27
F24
D24
D26
J23
B26
A23
C23
B24
B22
K24
C25
L23
L33
K32
K34

J35
F6
J39
L39
AY39
BB18
K28
K36

A7
A49
A52
A54
B54
D55
G55
BE55
BH55
BK55
BK54
BL54
BL52
BL49
BL7
BL4
BL2
BK2
BK1
BH1
BE1
G1

GFX_VR_ON

TP_MCH_RSVD1
TP_MCH_RSVD2
TP_MCH_RSVD3
TP_MCH_RSVD4
TP_MCH_RSVD5
TP_MCH_RSVD6
TP_MCH_RSVD7
TP_MCH_RSVD8
TP_MCH_RSVD9

TP_MCH_RSVD14
TP_MCH_RSVD15

TP_MCH_RSVD17

TP_MCH_RSVD20

TP_MCH_RSVD22
TP_MCH_RSVD23
TP_MCH_RSVD24
TP_MCH_RSVD25

ME_JTAG_TCK
ME_JTAG_TDI
ME_JTAG_TDO
ME_JTAG_TMS

R946 12K_0402_5%~D

1 2

12

R947
10K_0402_5%~D

CPU_MCH_BSEL0
CPU_MCH_BSEL1
CPU_MCH_BSEL2

CFG5
CFG6
CFG7

CFG9
CFG10

CFG12
CFG13

CFG16

CFG19
CFG20

PM_SYNC#
H_DPRSTP#
PM_EXTTS#0

ICH_PWRGD
PLTRST1#_R
THERMTRIP_MCH#
DPRSLPVR

+3.3V_RUN

12

R156
30K_0402_5%~D

12

R157
100K_0402_5%~D

R804 100_0402_5%~D@
R805 100_0402_5%~D@
R806 100_0402_5%~D@
R807 100_0402_5%~D@

4

1 2
1 2
1 2
1 2

+3.3V_ALW_ICH

O

DELL CONFIDENTIAL/PROPRIETARY

Title

Size Document Number Rev

2

Date: Sheet

Compal Electronics, Inc.

LA-4151P

1

PAD~D

T150

PAD~D

T151

PAD~D

T152

PAD~D

T153

PAD~D

T154

PAD~D

T155

PAD~D

T156

PAD~D

T157

PAD~D

T5

PAD~D

T158

PAD~D

T6

PAD~D

T8

T9 PAD~D

PAD~D

T10

PAD~D

T11

PAD~D

T12

PAD~D

T159

SIO_SLP_S4#<24,34>

C1108 0.1U_0402_16V4Z~D

1 2

5

DDR_ON

1

P

IN1

2

IN2

G

3

U80
74AHC1G08GW_SOT353-5~D

CPU_MCH_BSEL0 <6,8>
CPU_MCH_BSEL1 <6,8>

CPU_MCH_BSEL2 <6,8>

T14 PAD~D
T15 PAD~D

CFG5 <12>
CFG6 <12>
CFG7 <12>

T16 PAD~D

CFG9 <12>

CFG10 <12>

T18 PAD~D

CFG12 <12>

CFG13 <12>

T21 PAD~D
T22 PAD~D

CFG16 <12>

T23 PAD~D
T24 PAD~D

CFG19 <12>

CFG20 <12>

PM_SYNC# <24>
H_DPRSTP# <8,23,45>

PM_EXTTS#0 <16,17,18>

ICH_PWRG D <24,37>

THERMTRIP_MCH# <18>

DPRSLPVR <24,45>

PM_EXTTS#0

3.01K_0402_1%~D

1K_0402_1%~D

DDR_ON <34,36,44>

R1007 0_0402_5%~D@

1 2

1.5V_POK1

1.5V_POK1 <34,43>

12

R84 10K_0402_5%~D

+1.5V_MEM

12

R88

1K_0402_1%~D

SMRCOMP_VOH

1

12

2

R93

SMRCOMP_VOL

12

1

R97

2

Cantiga(1 of 6)

10 57Friday, Jul y 04, 2008

1

T123
T124
T125 PAD~D
T126 PAD~D

SIO_SLP_S4#

Notes refer
page 12

+3.3V_RUN

0.01U_0402_16V7K~D

1

C71

2

0.01U_0402_16V7K~D

1

C75

2

of

PAD~D
PAD~D

2.2U_0603_6.3V6K~D

C72

2.2U_0603_6.3V6K~D

C76

1.0

5

4

3

2

1

D D

C C

B B

DDR_A_BS1<16>
DDR_A_BS2<16>

DDR_A_RAS#<16>
DDR_A_CAS#<16>
DDR_A_WE#<16>

DDR_A_DM[0..7]<16>

DDR_A_DQS[0..7]<16>

DDR_A_DQS#[0..7]<16>

DDR_A_MA[0..14]<16>

DDR_A_BS0 DDR_B_BS1
DDR_A_BS1
DDR_A_BS2

DDR_A_RAS#
DDR_A_CAS#
DDR_A_WE#

DDR_A_DM0
DDR_A_DM1
DDR_A_DM2
DDR_A_DM3
DDR_A_DM4
DDR_A_DM5
DDR_A_DM6
DDR_A_DM7

DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7
DDR_A_DQS#0
DDR_A_DQS#1
DDR_A_DQS#2
DDR_A_DQS#3
DDR_A_DQS#4
DDR_A_DQS#5
DDR_A_DQS#6
DDR_A_DQS#7

DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA14

BC21

BJ21
BJ41

BH22
BK20

BL15

AT50
BB50
BB46
BE39
BB12

AV10

AR47
BA45
BE45
BC41
BC13
BB10

AR49

AW45

BC45
BA41
BA13
BA11

BC23
BF22
BE31
BC31
BH26

BJ35
BB34
BH32
BB26
BF32
BA21
BG25
BH34
BH18
BE25

BE7
AR9

BA7
AN7

BA9
AN9

SA_BS_0
SA_BS_1
SA_BS_2

SA_RAS#
SA_CAS#
SA_WE#

SA_DM_0
SA_DM_1
SA_DM_2
SA_DM_3
SA_DM_4
SA_DM_5
SA_DM_6
SA_DM_7

SA_DQS_0
SA_DQS_1
SA_DQS_2
SA_DQS_3
SA_DQS_4
SA_DQS_5
SA_DQS_6
SA_DQS_7
SA_DQS#_0
SA_DQS#_1
SA_DQS#_2
SA_DQS#_3
SA_DQS#_4
SA_DQS#_5
SA_DQS#_6
SA_DQS#_7

SA_MA_0
SA_MA_1
SA_MA_2
SA_MA_3
SA_MA_4
SA_MA_5
SA_MA_6
SA_MA_7
SA_MA_8
SA_MA_9
SA_MA_10
SA_MA_11
SA_MA_12
SA_MA_13
SA_MA_14

CANTIGA GMCH SFF_FCBGA1363~D

DDR SYSTEM MEMORY A

U78D

SA_DQ_0
SA_DQ_1
SA_DQ_2
SA_DQ_3
SA_DQ_4
SA_DQ_5
SA_DQ_6
SA_DQ_7
SA_DQ_8

SA_DQ_9
SA_DQ_10
SA_DQ_11
SA_DQ_12
SA_DQ_13
SA_DQ_14
SA_DQ_15
SA_DQ_16
SA_DQ_17
SA_DQ_18
SA_DQ_19
SA_DQ_20
SA_DQ_21
SA_DQ_22
SA_DQ_23
SA_DQ_24
SA_DQ_25
SA_DQ_26
SA_DQ_27
SA_DQ_28
SA_DQ_29
SA_DQ_30
SA_DQ_31
SA_DQ_32
SA_DQ_33
SA_DQ_34
SA_DQ_35
SA_DQ_36
SA_DQ_37
SA_DQ_38
SA_DQ_39
SA_DQ_40
SA_DQ_41
SA_DQ_42
SA_DQ_43
SA_DQ_44
SA_DQ_45
SA_DQ_46
SA_DQ_47
SA_DQ_48
SA_DQ_49
SA_DQ_50
SA_DQ_51
SA_DQ_52
SA_DQ_53
SA_DQ_54
SA_DQ_55
SA_DQ_56
SA_DQ_57
SA_DQ_58
SA_DQ_59
SA_DQ_60
SA_DQ_61
SA_DQ_62
SA_DQ_63

DDR_A_D0

AP46

DDR_A_D1

AU47

DDR_A_D2

AT46

DDR_A_D3

AU49

DDR_A_D4

AR45

DDR_A_D5

AN49

DDR_A_D6

AV50

DDR_A_D7

AP50

DDR_A_D8

AW47

DDR_A_D9

BD50

DDR_A_D10

AW49

DDR_A_D11

BA49

DDR_A_D12

BC49

DDR_A_D13

AV46

DDR_A_D14

BA47

DDR_A_D15

AY50

DDR_A_D16

BF46

DDR_A_D17

BC47

DDR_A_D18

BF50

DDR_A_D19

BF48

DDR_A_D20

BC43

DDR_A_D21

BE49

DDR_A_D22

BA43

DDR_A_D23

BE47

DDR_A_D24

BF42

DDR_A_D25

BC39

DDR_A_D26

BF44

DDR_A_D27

BF40

DDR_A_D28

BB40

DDR_A_D29

BE43

DDR_A_D30

BF38

DDR_A_D31

BE41

DDR_A_D32

BA15

DDR_A_D33

BE11

DDR_A_D34

BE15

DDR_A_D35

BF14

DDR_A_D36

BB14

DDR_A_D37

BC15

DDR_A_D38

BE13

DDR_A_D39

BF16

DDR_A_D40

BF10

DDR_A_D41

BC11

DDR_A_D42

BF8

DDR_A_D43

BG7

DDR_A_D44

BC7

DDR_A_D45

BC9

DDR_A_D46

BD6

DDR_A_D47

BF12

DDR_A_D48

AV6

DDR_A_D49

BB6

DDR_A_D50

AW7

DDR_A_D51

AY6

DDR_A_D52

AT10

DDR_A_D53

AW11

DDR_A_D54

AU11

DDR_A_D55

AW9

DDR_A_D56

AR11

DDR_A_D57

AT6

DDR_A_D58

AP6

DDR_A_D59

AL7

DDR_A_D60

AR7

DDR_A_D61

AT12

DDR_A_D62

AM6

DDR_A_D63

AU7

DDR_A_D[0..63] <16>

DDR_B_BS0<17>
DDR_B_BS1<17>DDR_A_BS0<16>
DDR_B_BS2<17>

DDR_B_RAS#<17>
DDR_B_CAS#<17>
DDR_B_WE#<17>

DDR_B_DM[0..7]<17>

DDR_B_DQS[0..7]<17>

DDR_B_DQS#[0..7]<17>

DDR_B_MA[0..14]<17>

DDR_B_BS0
DDR_B_BS2

DDR_B_RAS#
DDR_B_CAS#
DDR_B_WE#

DDR_B_DM0
DDR_B_DM1
DDR_B_DM2
DDR_B_DM3
DDR_B_DM4
DDR_B_DM5
DDR_B_DM6
DDR_B_DM7

DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4
DDR_B_DQS5
DDR_B_DQS6
DDR_B_DQS7
DDR_B_DQS#0
DDR_B_DQS#1
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS#4
DDR_B_DQS#5
DDR_B_DQS#6
DDR_B_DQS#7

DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13
DDR_B_MA14

BJ13
BK12
BK38

BE21
BH14
BK14

AP52
AY54

BJ49

BJ43
BH12

AR53
BA53
BH50
BK42

AM2
AT54
BB54

BJ51

BH42

AW3

BJ15

BJ33
BH24
BA17
BF36
BH36
BF34
BK34

BJ37
BH40
BH16
BK36
BH38

BJ11

BL37

BD2
AY2

AJ3

BH8
BB2
AV2

BK8
BC3

AN3

SB_BS_0
SB_BS_1
SB_BS_2

SB_RAS#
SB_CAS#
SB_WE#

SB_DM_0
SB_DM_1
SB_DM_2
SB_DM_3
SB_DM_4
SB_DM_5
SB_DM_6
SB_DM_7

SB_DQS_0
SB_DQS_1
SB_DQS_2
SB_DQS_3
SB_DQS_4
SB_DQS_5
SB_DQS_6
SB_DQS_7
SB_DQS#_0
SB_DQS#_1
SB_DQS#_2
SB_DQS#_3
SB_DQS#_4
SB_DQS#_5
SB_DQS#_6
SB_DQS#_7

SB_MA_0
SB_MA_1
SB_MA_2
SB_MA_3
SB_MA_4
SB_MA_5
SB_MA_6
SB_MA_7
SB_MA_8
SB_MA_9
SB_MA_10
SB_MA_11
SB_MA_12
SB_MA_13
SB_MA_14

CANTIGA GMCH SFF_FCBGA1363~D

DDR SYSTEM MEMORY B

SB_DQ_0
SB_DQ_1
SB_DQ_2
SB_DQ_3
SB_DQ_4
SB_DQ_5
SB_DQ_6
SB_DQ_7
SB_DQ_8

SB_DQ_9
SB_DQ_10
SB_DQ_11
SB_DQ_12
SB_DQ_13
SB_DQ_14
SB_DQ_15
SB_DQ_16
SB_DQ_17
SB_DQ_18
SB_DQ_19
SB_DQ_20
SB_DQ_21
SB_DQ_22
SB_DQ_23
SB_DQ_24
SB_DQ_25
SB_DQ_26
SB_DQ_27
SB_DQ_28
SB_DQ_29
SB_DQ_30
SB_DQ_31
SB_DQ_32
SB_DQ_33
SB_DQ_34
SB_DQ_35
SB_DQ_36
SB_DQ_37
SB_DQ_38
SB_DQ_39
SB_DQ_40
SB_DQ_41
SB_DQ_42
SB_DQ_43
SB_DQ_44
SB_DQ_45
SB_DQ_46
SB_DQ_47
SB_DQ_48
SB_DQ_49
SB_DQ_50
SB_DQ_51
SB_DQ_52
SB_DQ_53
SB_DQ_54
SB_DQ_55
SB_DQ_56
SB_DQ_57
SB_DQ_58
SB_DQ_59
SB_DQ_60
SB_DQ_61
SB_DQ_62
SB_DQ_63

U78E

DDR_B_D0

AP54

DDR_B_D1

AM52

DDR_B_D2

AR55

DDR_B_D3

AV54

DDR_B_D4

AM54

DDR_B_D5

AN53

DDR_B_D6

AT52

DDR_B_D7

AU53

DDR_B_D8

AW53

DDR_B_D9

AY52

DDR_B_D10

BB52

DDR_B_D11

BC53

DDR_B_D12

AV52

DDR_B_D13

AW55

DDR_B_D14

BD52

DDR_B_D15

BC55

DDR_B_D16

BF54

DDR_B_D17

BE51

DDR_B_D18

BH48

DDR_B_D19

BK48

DDR_B_D20

BE53

DDR_B_D21

BH52

DDR_B_D22

BK46

DDR_B_D23

BJ47

DDR_B_D24

BL45

DDR_B_D25

BJ45

DDR_B_D26

BL41

DDR_B_D27

BH44

DDR_B_D28

BH46

DDR_B_D29

BK44

DDR_B_D30

BK40

DDR_B_D31

BJ39

DDR_B_D32

BK10

DDR_B_D33

BH10

DDR_B_D34

BK6

DDR_B_D35

BH6

DDR_B_D36

BJ9

DDR_B_D37

BL11

DDR_B_D38

BG5

DDR_B_D39

BJ5

DDR_B_D40

BG3

DDR_B_D41

BF4

DDR_B_D42

BD4

DDR_B_D43

BA3

DDR_B_D44

BE5

DDR_B_D45

BF2

DDR_B_D46

BB4

DDR_B_D47

AY4

DDR_B_D48

BA1

DDR_B_D49

AP2

DDR_B_D50

AU1

DDR_B_D51

AT2

DDR_B_D52

AT4

DDR_B_D53

AV4

DDR_B_D54

AU3

DDR_B_D55

AR3

DDR_B_D56

AN1

DDR_B_D57

AP4

DDR_B_D58

AL3

DDR_B_D59

AJ1

DDR_B_D60

AK4

DDR_B_D61

AM4

DDR_B_D62

AH2

DDR_B_D63

AK2

DDR_B_D[0..63] <17>

A A

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

Cantiga(2 of 6)

LA-4151P

11 57Fr id ay, July 04, 2008

1

1.0

of

5

4

+VCC_PEG

3

2

1

Strap Pin Table

U78C

+3.3V_RUN

R1010 10K_0402_5%~D @

D D

Apply CIS

C C

B B

A A

1 2
1 2

R1011

@

1 2

The value is recommended per Intel

R688 2.4K_0402_1%~D

CRT_HSYNC<20>

Apply CIS

CRT_VSYNC<20>

BIA_PWM<19>

PANEL_BKEN_MCH<33>

10K_0402_5%~D

LDDC_CLK_MCH<39>
LDDC_DATA_MCH<39>

LCD_ACLK-_MCH<40>
LCD_ACLK+_MCH<40>

LCD_A0-_MCH<40>
LCD_A1-_MCH<40>
LCD_A2-_MCH<40>

LCD_A0+_MCH<40>
LCD_A1+_MCH<40>
LCD_A2+_MCH<40>

CRT_BLU<20>
CRT_GRN<20>
CRT_RED<20>

CRT_HSYNC CRT_HSYNC_R

CRT_VSYNC CRT_VSYNC_R

1 2

R679 150_0402_1%~D

1 2

R680 150_0402_1%~D

1 2

R681 150_0402_1%~D

1 2

R682 100K_0402_5%~D

5

BIA_PWM
PANEL_BKEN_MCH
L_CTRL_CLK

L_CTRL_DATA
LDDC_CLK_MCH
LDDC_DATA_MCH

ENVDD<19>

CRT_BLU
CRT_GRN
CRT_RED
ENVDD

ENVDD
L_IBG

LCD_ACLK-_MCH
LCD_ACLK+_MCH

LCD_A0-_MCH
LCD_A1-_MCH
LCD_A2-_MCH

LCD_A0+_MCH
LCD_A1+_MCH
LCD_A2+_MCH

R1107 75_0402_5%~D

R1106 75_0402_5%~D

12

12

CRT_BLU
CRT_GRN
CRT_RED

G_CLK_DDC2

1 2

R480 30_0402_1%~D
R672 976_0402_1%~D
R673 30_0402_1%~D

1 2

12

CRT_IREF

D38

L_BKLT_CTRL

C37

L_BKLT_EN

K38

L_CTRL_CLK

L37

L_CTRL_DATA

J37

L_DDC_CLK

L35

L_DDC_DATA

B36

L_VDD_EN

F50

LVDS_IBG

H46

LVDS_VBG

P44

LVDS_VREFH

K46

LVDS_VREFL

D46

LVDSA_CLK#

B46

LVDSA_CLK

D44

LVDSB_CLK#

B44

LVDSB_CLK

G45

LVDSA_DATA#_0

F46

LVDSA_DATA#_1

G41

LVDSA_DATA#_2

C45

LVDSA_DATA#_3

F44

LVDSA_DATA_0

G47

LVDSA_DATA_1

F40

LVDSA_DATA_2

A45

LVDSA_DATA_3

B40

LVDSB_DATA#_0

A41

LVDSB_DATA#_1

F42

LVDSB_DATA#_2

D48

LVDSB_DATA#_3

D40

LVDSB_DATA_0

C41

LVDSB_DATA_1

G43

LVDSB_DATA_2

B48

LVDSB_DATA_3

J27

TVA_DAC

E27

TVB_DAC

G27

R1105 75_0402_5%~D

12

TVC_DAC

F26

TVA_RTN

B34

TV_DCONSEL_0

D34

TV_DCONSEL_1

J29

CRT_BLUE

G29

CRT_GREEN

F30

CRT_RED

E29

CRT_IRTN

D36

CRT_DDC_CLK

C35

CRT_DDC_DATA

J33

CRT_HSYNC

D32

CRT_TVO_IREF

G31

CRT_VSYNC

CANTIGA GMCH SFF_FCBGA1363~D

2.2K_0402_5%~D

G_DAT_DDC2 DAT_DDC2

+3.3V_RUN

R675

12

12

+3.3V_RUN

4

LVDS

TV

R676

2.2K_0402_5%~D

PEG_COMPI

PEG_COMPO

PEG_RX#_0
PEG_RX#_1
PEG_RX#_2
PEG_RX#_3
PEG_RX#_4
PEG_RX#_5
PEG_RX#_6
PEG_RX#_7
PEG_RX#_8

PEG_RX#_9
PEG_RX#_10
PEG_RX#_11
PEG_RX#_12
PEG_RX#_13
PEG_RX#_14
PEG_RX#_15

PEG_RX_0
PEG_RX_1
PEG_RX_2
PEG_RX_3
PEG_RX_4
PEG_RX_5
PEG_RX_6
PEG_RX_7
PEG_RX_8

PEG_RX_9
PEG_RX_10
PEG_RX_11
PEG_RX_12
PEG_RX_13
PEG_RX_14
PEG_RX_15

PEG_TX#_0
PEG_TX#_1
PEG_TX#_2
PEG_TX#_3
PEG_TX#_4
PEG_TX#_5
PEG_TX#_6
PEG_TX#_7
PEG_TX#_8
PEG_TX#_9

PEG_TX#_10
PEG_TX#_11

PCI-EXPRESS GRAPHICS

PEG_TX#_12
PEG_TX#_13
PEG_TX#_14
PEG_TX#_15

PEG_TX_0
PEG_TX_1
PEG_TX_2

1 2

R860 0_0402_5%~D@

4

1 2

R861 0_0402_5%~D@

2
5

PEG_TX_3
PEG_TX_4
PEG_TX_5
PEG_TX_6
PEG_TX_7
PEG_TX_8

PEG_TX_9
PEG_TX_10
PEG_TX_11
PEG_TX_12
PEG_TX_13
PEG_TX_14
PEG_TX_15

61

Q123A

2N7002DW-T/R7_SOT363-6~D

Q123B

2N7002DW-T/R7_SOT363-6~D

3

VGA

CLK_DDC2G_ C LK_DDC2

U45
T44

D52
G49
K54
H50
M52
N49
P54
V46
Y50
V52
W49
AB54
AD46
AC55
AE49
AF54

E51
F48
J55
J49
M54
M50
P52
U47
AA49
V54
V50
AB52
AC47
AC53
AD50
AF52

L47
F52
P46
H54
L55
T46
R53
U49
T54
Y46
AB46
W53
Y54
AC49
AF46
AD54

J47
F54
N47
H52
L53
R47
R55
T50
T52
W47
AA47
W55
Y52
AB50
AE47
AD52

PEGCOMP

DPB_AUX#

DPC_DOCK_AUX#

DPB_AUX
DPB_HPD#

DPC_DOCK_AUX
DPC_DOCK_HPD#

DPB_LANE_N0
DPB_LANE_N1
DPB_LANE_N2
DPB_LANE_N3
DPC_LANE_N0
DPC_LANE_N1
DPC_LANE_N2
DPC_LANE_N3

DPB_LANE_P0
DPB_LANE_P1
DPB_LANE_P2
DPB_LANE_P3
DPC_LANE_P0
DPC_LANE_P1
DPC_LANE_P2
DPC_LANE_P3

R105

49.9_0402_1%~D

1 2

DPB_AUX# <21>

DPC_DOCK_AUX# <21>

DPB_AUX <21>

DPB_HPD# <21>

DPC_DOCK_AUX <21>

DPC_DOCK_HPD# <21>

C716 0.1U_0402_10V7K~D

12

C717 0.1U_0402_10V7K~D

12

C718 0.1U_0402_10V7K~D

12

C719 0.1U_0402_10V7K~D

12

C720 0.1U_0402_10V7K~D

12

C721 0.1U_0402_10V7K~D

12

C722 0.1U_0402_10V7K~D

12

C723 0.1U_0402_10V7K~D

12

C724 0.1U_0402_10V7K~D

12

C725 0.1U_0402_10V7K~D

12

C726 0.1U_0402_10V7K~D

12

C727 0.1U_0402_10V7K~D

12

C728 0.1U_0402_10V7K~D

12

C729 0.1U_0402_10V7K~D

12

C730 0.1U_0402_10V7K~D

12

C731 0.1U_0402_10V7K~D

12

CLK_DDC2 <20>

DAT_DDC2 <20>

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

CFG5

DMI X2 Select

iTPM Host

CFG6

Interface
Management

Engine Crypto

CFG7

Strap
PCI Express

CFG9

Graphic Lane

FSB Dynamic

CFG16

ODT
DMI Lane

CFG19

Reversal

SDVO/PCIE

CFG20

Concurrent
Operation

SDVO_CRTL_DATA

DDPC_CTRLDATA

DPB_LANE_N0_C <31>
DPB_LANE_N1_C <31>
DPB_LANE_N2_C <31>
DPB_LANE_N3_C <31>
DPC_LANE_N0_C <31>
DPC_LANE_N1_C <31>
DPC_LANE_N2_C <31>
DPC_LANE_N3_C <31>

CG13 CG12 configuration

00
1
0

0
1

11

CG10(PCIE Loopback enable)

DPB_LANE_P0_C <31>
DPB_LANE_P1_C <31>
DPB_LANE_P2_C <31>
DPB_LANE_P3_C <31>
DPC_LANE_P0_C <31>
DPC_LANE_P1_C <31>
DPC_LANE_P2_C <31>
DPC_LANE_P3_C <31>

3

2

Low = DMI x 2
High = DMI x 4 (Default)
Low = iTPM enable
High = iTPM disable(Defult)
Low = TLS cipher s u i t e wit h n o c onfidentiality
High = TLS cip h e r s u i t e with

confidentiality(Default)
Low = Reverse Lane

High = Normal O p e r a t i o n(Default)

Low=Dynamic O D T Disable
High=Dynamic ODT Enable(default)
Low=Normal (default)
High=Lane Reversed

Low=Only SDVO or PCIEx1 is
operational (default)
High=SDVO and P C I E x 1 a r e o p e rating
simultaneously via PEG port
Low=No SDVO Device Present
(default)
High=SDVO Dev i ce Present

Low=DisplayPort disabled (default)
High=DisplayPort device present

XOR/ALLZ/Clock Un-gating

Reserved
XOR Mode Enabled
All-Z Mode Enabled
Normal Operation(default)

Low= Enables
High= Disable ( d e fault)

CFG5

CFG5<10>
CFG6<10>
CFG7<10>
CFG9<10>
CFG16<10>

CFG10<10>
CFG12<10>
CFG13<10>

CFG19<10>
CFG20<10>

R106

@

CFG6

R107

@

CFG7G_DAT_DDC2

R108

@

CFG9

R109

@

CFG16

R110

@

CFG[5:16] have internal pullup

CFG10

R979

@

CFG12

R980

@

CFG13

R981

@

CFG19

R111

@

CFG20

R112

@

1 2
1 2
1 2
1 2
1 2

1 2
1 2
1 2

1 2
1 2

2.21K_0402_1%~D

2.21K_0402_1%~D

2.21K_0402_1%~D

2.21K_0402_1%~D

2.21K_0402_1%~D

2.21K_0402_1%~D

2.21K_0402_1%~D

2.21K_0402_1%~D

4.02K_0402_1%~D

4.02K_0402_1%~D

CFG[19:20] have internal pulldown

DELL CONFIDENTIAL/PROPRIETARY

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

Cantiga(3 of 6)

LA-4151P

+3.3V_RUN

1

12 57Fr id ay, July 04, 2008

1.0

of

5

CRB 270uF

220U_D2_4VY_R15M~D

1

+

2

D D

C114

4.7U_0603_6.3V6M~D

C115

4.7U_0603_6.3V6M~D

1

2

+1.5V_RUN_QDAC

C C

+1.05V_M

R118 0_1210_5%~D

+3.3V_RUN

0.1U_0402_16V4Z~D
C136

1

B B

A A

2

0.47U_0402_10V4Z~D
C142

1

2

+1.05V_VCCP

0.47U_0402_10V4Z~D

1

C109

2

C116

2.2U_0603_6.3V6K~D

1

1

+1.5V_RUN

0.1U_0402_16V4Z~D

2

2

+VCC_AXF

12

10U_0805_4VAM~D

@

1

C125

2

+1.5V_SM_CK

118.8mA Max.

+VCC_TX_LVDS

+VCC_PEG

+VCC_DMI

0.1U_0402_16V4Z~D

1

2

GMCH_VTTLF1
GMCH_VTTLF2
GMCH_VTTLF3

0.47U_0402_10V4Z~D
C143

1

1

2

2

C110

C137

0.47U_0402_10V4Z~D

1

2

1

2

C144

C998

1U_0603_10V4Z~D

C126

BK24

BL23
BJ23

BK22

AB44
AC43

AA43

AM44
AN43

AL43

R13
T12
R11
T10

R9
T8
R7
T6
R5
T4
R3

R1

K30

A31

N34
N32

M25
N24
M23

T41
C33

A33

Y44

K14
Y12

P2

VTT_1
VTT_2
VTT_3
VTT_4
VTT_5
VTT_6
VTT_7
VTT_8
VTT_9
VTT_10
VTT_11

T2

VTT_12
VTT_13

VCCA_TV_DAC

VCC_HDA

VCCD_QDAC
VCCD_TVDAC

VCC_AXF_1
VCC_AXF_2
VCC_AXF_3

VCC_SM_CK_1
VCC_SM_CK_2
VCC_SM_CK_3
VCC_SM_CK_4

VCC_TX_LVDS
VCC_HV_1

VCC_HV_2

VCC_PEG_1
VCC_PEG_2
VCC_PEG_3
VCC_PEG_4

VCC_DMI_1
VCC_DMI_2
VCC_DMI_3

VTTLF1
VTTLF2
VTTLF3

VTT

TVD TV/CRT

HDA

POWER

AXF

SM CK

HV

PEG

DMI

VTTLF

CANTIGA GMCH SFF_FCBGA1363~D

VCCA_CRT_DAC

VCCA_DAC_BG
VSSA_DAC_BG

CRTPLLA PEGA SM

VCCA_DPLLA
VCCA_DPLLB

VCCA_HPLL
VCCA_MPLL

VCCA_LVDS1
VCCA_LVDS2

VSSA_LVDS

A LVDS

VCCA_PEG_BG

VCCA_PEG_PLL

VCCA_SM_1
VCCA_SM_2
VCCA_SM_3
VCCA_SM_4
VCCA_SM_5
VCCA_SM_6
VCCA_SM_7
VCCA_SM_8

VCCA_SM_9
VCCA_SM_10
VCCA_SM_11
VCCA_SM_12
VCCA_SM_13
VCCA_SM_14
VCCA_SM_15
VCCA_SM_16
VCCA_SM_17

VCCA_SM_NCTF_1
VCCA_SM_NCTF_2
VCCA_SM_NCTF_3
VCCA_SM_NCTF_4
VCCA_SM_NCTF_5
VCCA_SM_NCTF_6
VCCA_SM_NCTF_7
VCCA_SM_NCTF_8
VCCA_SM_NCTF_9

VCCA_SM_NCTF_10

VCCA_SM_CK_4
VCCA_SM_CK_3
VCCA_SM_CK_2

VCCA_SM_CK_1
VCCA_SM_CK_NCTF_1
VCCA_SM_CK_NCTF_2
VCCA_SM_CK_NCTF_3
VCCA_SM_CK_NCTF_4
VCCA_SM_CK_NCTF_5
VCCA_SM_CK_NCTF_6
VCCA_SM_CK_NCTF_7
VCCA_SM_CK_NCTF_8

VCCD_HPLL

VCCD_PEG_PLL

VCCD_LVDS_1
VCCD_LVDS_2

LVDS

60.31mA Max.

U78H

J31

L31
M33

J45
L49
AF10
AE1

U43
U41

V44

AJ43

AG43

AW24
AU24
AW22
AU22
AU21
AW20
AU19
AW18
AU18
AW16
AU16
AT16
AR16
AU15
AT15
AR15
AW14

AT24
AR24
AT22
AR22
AT21
AR21
AT19
AR19
AT18
AR18

AU27
AU28
AU29
AU31
AT31
AR31
AT29
AR29
AT28
AR28
AT27
AR27

AH12
AE43

M46
L45

4

+3.3V_CRT_DAC

+1.05V_M_DPLLA
+1.05V_M_DPLLB
+1.05V_M_HPLL
+1.05V_M_MPLL

+VCC_TX_LVDS

+VCCA_PEG_BG

+1.05V_M_PEGPLL

+1.05V_M_SM_CK

1

2

+1.05V_M_PEGPLL

0.1U_0402_16V4Z~D

1

2

+1.8V_RUN

1U_0603_10V4Z~D

1

C743

2

1

2

0.1U_0402_16V4Z~D

C127

+1.05V_M

C141

1

2

13.2mA Max.

1

C117

0.1U_0402_16V4Z~D

2

+1.05V_M_A_SM

4.7U_0603_6.3V6M~D

1U_0603_10V4Z~D

1

C122

C121

2

2.2U_0603_6.3V6K~D

22U_0805_6.3V6M~D

1

1

C128

2

2

0.1U_0402_16V4Z~D

1

C140

2

+3.3V_CRT_DAC

0.01U_0402_25V7K~D

0.1U_0402_16V4Z~D

1

C734

C735

2

1 2

R778 0_0402_5%~D

1 2

R779 0_0402_5%~D@

R116

1 2

22U_0805_6.3V6M~D

22U_0805_6.3V6M~D

0_0805_5%~D

@

1

1

C123

C124

2

2

1 2

R119 0_1210_5%~D

@

C129

+1.05V_M

3

0.01U_0402_25V7K~D

0.1U_0402_16V4Z~D
10UH_LB2012T100MR_20%_0805~D

1

1

C732

C733

2

2

+VCC_TX_LVDS

+1.5V_RUN
+3.3V_RUN

+1.05V_M

100U_D2E_6.3VM_R15M~D

1

+

C120

2

+3.3V_RUN+3 .3 V_CRT_DAC

L43

1 2

Rating current 125mA

1000P_0402_50V7K~D

1

C736

2

+1.5V_MEM +1.5V_SM_CK

+VCC_PEG

220U_D2_4VY_R15M~D

4.7U_0603_6.3V6M~D

1

1

+

+1.05V_M

C118

10U_0805_4VAM~D

12

+1.05V_M_HPLL

24mA Max. 139.2mA Max.

+1.05V_M_DPLLA +1.05V_M_DPLLB

L7
LQM21FN1R0 N 0 0 _0805~D

Rdc=0.1~0.2,rated
current=220mA(MAX)

C147

10U_0805_4VAM~D

+1.5V_SM_CKG

12

C112

C111

2

2

BLM21PG221SN1D_0805~D

1 2

+1.05V_MPEG

R117

0.1U_0402_16V4Z~D

4.7U_0603_6.3V6M~D

1

1

C130

2

2

10UH_LB2012T100MR_20%_0805~D

220U_D2_4VY_R15M~D

0.1U_0402_16V4Z~D

1

1

+

C741

2

2

12

12

2

+VCC_DMI

1 2

R114

22U_0805_6.3V6M~D

0_1210_5%~D

1

2

L3

BLM18AG121SN1D_0603~D

C131

1 2

1 2

R115

@

C113

0_1210_5%~D

+1.05V_M_PEGPLL

1_0402_5%~D

+1.05V_M +1.05V_M

L4

12

+1.05V_M

L45

Rating current 125mA Rating current 125mA

C739

0.1U_0402_16V4Z~D

1_0603_5%~D

R121

1

C146

2

2 1

D1

@

RB751V_SOD323-2~D

Follow CRB to
VCC_HV(C33,A33)

+1.05V_M

+1.05V_VCCP

Follow ERB,CRB option
to select +1.05V_M or
+1.05V_VCCP

0.1U_0402_16V4Z~D

1

C119

2

+VCCPRUN

220U_D2_4VY_R15M~D

+1.5V_RUN_QDAC

1

2

64.8mA Max.64.8mA Max.

+1.8V_RUN_LVDS

+3.3V_RUN+1.05V_VCCP

1 2

R122

@

10_0603_5%~D

C145

@

0.1U_0402_16V4Z~D

0.01U_0402_25V7K~D

1

C738

C737

2

+1.05V_M_MPLL

0.1U_0402_16V4Z~D

1

2

0.1U_0402_16V4Z~D

1

2

@

PJP61

1 2

PAD-OPEN 1x1m

L44
BLM18PG181SN1_0603~D

C132

1 2
1

2

10UH_LB2012T100MR_20%_0805~D

1

+

C742

2

1

12

PJP1
PAD-OPEN1x1m

12

L6

@

1

LBC2518T91NM_1210~D

+

2

+1.5V_RUN

12

L5
LQH32CNR15M33L_1210~D
R120
0_0603_5%~D

C133
22U_0805_6.3VAM~D

220U_D2_4VY_R15M~D

12

+1.05V_MPLL

+1.05V_M

L46

1 2

C740

12

L47
HK1608R10J-T_0603~D

+VCC_PEG

+1.05V_M

+VCC_TX_LVDS+1.8V_RUN

22U_0805_6.3V6M~D

1000P_0402_50V7K~D

C745

1

1

C744

2

2

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

Cantiga(4 of 6)

LA-4151P

13 57Fr id ay, July 04, 2008

1

1.0

of

5

4

3

2

1

U78G

POWER

VCC SMVCC GFX

VCC GFX NCTF

VCC GFX

VCC_AXG_NCTF_1
VCC_AXG_NCTF_2
VCC_AXG_NCTF_3
VCC_AXG_NCTF_4
VCC_AXG_NCTF_5
VCC_AXG_NCTF_6
VCC_AXG_NCTF_7
VCC_AXG_NCTF_8

VCC_AXG_NCTF_9
VCC_AXG_NCTF_10
VCC_AXG_NCTF_11
VCC_AXG_NCTF_12
VCC_AXG_NCTF_13
VCC_AXG_NCTF_14
VCC_AXG_NCTF_15
VCC_AXG_NCTF_16
VCC_AXG_NCTF_17
VCC_AXG_NCTF_18
VCC_AXG_NCTF_19
VCC_AXG_NCTF_20
VCC_AXG_NCTF_21
VCC_AXG_NCTF_22
VCC_AXG_NCTF_23
VCC_AXG_NCTF_24
VCC_AXG_NCTF_25
VCC_AXG_NCTF_26
VCC_AXG_NCTF_27
VCC_AXG_NCTF_28
VCC_AXG_NCTF_29
VCC_AXG_NCTF_30
VCC_AXG_NCTF_31
VCC_AXG_NCTF_32
VCC_AXG_NCTF_33
VCC_AXG_NCTF_34
VCC_AXG_NCTF_35
VCC_AXG_NCTF_36
VCC_AXG_NCTF_37
VCC_AXG_NCTF_38
VCC_AXG_NCTF_39
VCC_AXG_NCTF_40
VCC_AXG_NCTF_41
VCC_AXG_NCTF_42
VCC_AXG_NCTF_43
VCC_AXG_NCTF_44

VCC_AXG_62
VCC_AXG_63
VCC_AXG_64
VCC_AXG_65
VCC_AXG_66
VCC_AXG_67
VCC_AXG_68
VCC_AXG_69
VCC_AXG_70
VCC_AXG_71
VCC_AXG_72
VCC_AXG_73
VCC_AXG_74
VCC_AXG_75
VCC_AXG_76
VCC_AXG_77
VCC_AXG_78
VCC_AXG_79
VCC_AXG_80

VCC_SM_LF1
VCC_SM_LF2
VCC_SM_LF3
VCC_SM_LF4
VCC_SM_LF5
VCC_SM_LF6
VCC_SM_LF7

VCC SM LF

+1.5V_MEM

330U_D2_2.5VY_R15M

C1103

1

2

C1105

1

2

0.1U_0402_10V7K~D

2

C149

1

+VCC_CM_BB36
+VCC_CM_BE35

0.1U_0402_10V7K~D
C1104

1

2

+VCC_CM_BF24
+VCC_CM_BL19

0.1U_0402_10V7K~D
C1106

1

2

1

C148

+

2

Layout Note:
Place on the edge

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D
C1102

1

1

2

2

CRB use

VCC_AXG_SENSE<47>
VSS_AXG_SENSE<47>

+VCC_CM_BB16
+VCC_CM_BC29

C1110

D D

Layout Note:
Place close to GMCH

0.1U_0402_10V7K~D

C C

0.1U_0402_10V7K~D

B B

A A

22U_0805_6.3V6M~D

1

1

C150

2

2

+VCC_GFXCORE

+VCC_CM_BB36
+VCC_CM_BE35

22U_0805_6.3V6M~D

C151

+VCC_CM_BC29

+VCC_CM_BF24
+VCC_CM_BL19
+VCC_CM_BB16

BB36

BE35
AW34
AW32

BK30

BH30

BF30

BD30

BB30
AW30

BL29

BJ29
BG29
BE29
BC29
BA29
AY29
BK28
BH28
BF28
BD28
BB28

BL27

BJ27
BG27
BE27
BC27
BA27
AY27

AW26

BF24

BL19
BB16

W32
AG31
AE31
AD31
AC31
AA31

W31
AH29
AG29
AE29
AD29
AC29
AA29

W29
AH28
AG28
AE28
AA28
AH27
AG27
AE27
AD27
AC27
AA27

W27
AH25
AD25
AC25

W25

AJ24
AH24
AG24
AE24
AD24
AC24
AA24

W24

AM22

AL22

AJ22
AH22
AG22
AE22
AD22
AC22
AA22

AM21

AL21

AJ21
AH21
AD21
AC21
AA21

W21

AM16

AL16

AG13
AE13

Y31

Y29

Y27

Y24

Y21

VCC_SM_1
VCC_SM_2
VCC_SM_3
VCC_SM_4
VCC_SM_5
VCC_SM_6
VCC_SM_7
VCC_SM_8
VCC_SM_9
VCC_SM_10
VCC_SM_11
VCC_SM_12
VCC_SM_13
VCC_SM_14
VCC_SM_15
VCC_SM_16
VCC_SM_17
VCC_SM_18
VCC_SM_19
VCC_SM_20
VCC_SM_21
VCC_SM_22
VCC_SM_23
VCC_SM_24
VCC_SM_25
VCC_SM_26
VCC_SM_27
VCC_SM_28
VCC_SM_29
VCC_SM_30
VCC_SM_31
VCC_SM_32
VCC_SM_33

VCC_AXG_1
VCC_AXG_2
VCC_AXG_3
VCC_AXG_4
VCC_AXG_5
VCC_AXG_6
VCC_AXG_7
VCC_AXG_8
VCC_AXG_9
VCC_AXG_10
VCC_AXG_11
VCC_AXG_12
VCC_AXG_13
VCC_AXG_14
VCC_AXG_15
VCC_AXG_16
VCC_AXG_17
VCC_AXG_18
VCC_AXG_19
VCC_AXG_20
VCC_AXG_21
VCC_AXG_22
VCC_AXG_23
VCC_AXG_24
VCC_AXG_25
VCC_AXG_26
VCC_AXG_27
VCC_AXG_28
VCC_AXG_29
VCC_AXG_30
VCC_AXG_31
VCC_AXG_32
VCC_AXG_33
VCC_AXG_34
VCC_AXG_35
VCC_AXG_36
VCC_AXG_37
VCC_AXG_38
VCC_AXG_39
VCC_AXG_40
VCC_AXG_41
VCC_AXG_42
VCC_AXG_43
VCC_AXG_44
VCC_AXG_45
VCC_AXG_46
VCC_AXG_47
VCC_AXG_48
VCC_AXG_49
VCC_AXG_50
VCC_AXG_51
VCC_AXG_52
VCC_AXG_53
VCC_AXG_54
VCC_AXG_55
VCC_AXG_56
VCC_AXG_57
VCC_AXG_58
VCC_AXG_59
VCC_AXG_60
VCC_AXG_61

VCC_AXG_SENSE
VSS_AXG_SENSE

+VCC_GFXCORE

T32
U31
T31
R31
U29
T29
R29
U28
U27
T27
R27
U25
T25
R25
U24
U22
T22
R22
U21
T21
R21
AM19
AL19
AH19
AG19
AE19
AD19
AC19
W19
U19
AM18
AL18
AJ18
AH18
AG18
AE18
AD18
AC18
AA18
Y18
W18
U18
T18
R18

AJ16
AH16
AD16
AC16
AA16
U16
T16
R16
AM15
AL15
AJ15
AH15
AG15
AE15
AA15
Y15
W15
U15
T15

AU45
BF52
BB38
BA19
BE9
AU9
AL9

VCCSM_LF1
VCCSM_LF2
VCCSM_LF3
VCCSM_LF4
VCCSM_LF5
VCCSM_LF6
VCCSM_LF7

0.47U_0402_10V4Z~D

1U_0603_10V4Z~D

0.1U_0402_10V7K~D

C748

1

1

1

2

2

Layout Note: Inside GMCH
cavity for VCC_AXG.

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

C158

C157

1

1

2

2

1

C749

C750

2

2

0.22U_0402_10V4Z~D

0.22U_0402_10V4Z~D

C159

1

1

2

2

C160

U78F

+1.05V_M

AT41

VCC_1

AR41

VCC_2

AN41

VCC_3

AJ41

VCC_4

AH41

VCC_5

AD41

VCC_6

AC41

VCC_7

Y41

VCC_8

1 2

R123
0_0402_5%~D

W41

VCC_9

AT40

VCC_10

AM40

VCC_11

AL40

VCC_12

AJ40

VCC_13

AH40

VCC_14

AG40

VCC_15

AE40

VCC_16

AD40

VCC_17

AC40

VCC_18

AA40

VCC_19

Y40

VCC_20

AN35

VCC_21

AM35

VCC_22

AJ35

VCC_23

AH35

VCC_24

AD35

VCC_25

AC35

VCC_26

W35

VCC_27

AM34

VCC_28

AL34

VCC_29

AJ34

VCC_30

AH34

VCC_31

AG34

VCC_32

AE34

VCC_33

AD34

VCC_34

AC34

VCC_35

AA34

VCC_36

Y34

VCC_37

W34

VCC_38

AM32

VCC_39

AL32

VCC_40

AJ32

VCC_41

AH32

VCC_42

AE32

VCC_43

AD32

VCC_44

AA32

VCC_45

AM31

VCC_46

AL31

VCC_47

AJ31

VCC_48

AH31

VCC_49

AM29

VCC_50

AL29

VCC_51

AM28

VCC_52

AL28

VCC_53

AJ28

VCC_54

AM27

VCC_55

AL27

VCC_56

AM25

VCC_57

AL25

VCC_58

AJ25

VCC_59

AM24

VCC_60

N36

VCC_61

CANTIGA GMCH SFF_FCBGA1363~D

VCC CORE

VCC_NCTF_1
VCC_NCTF_2
VCC_NCTF_3
VCC_NCTF_4
VCC_NCTF_5
VCC_NCTF_6
VCC_NCTF_7
VCC_NCTF_8

POWER

VCC_NCTF_9
VCC_NCTF_10
VCC_NCTF_11
VCC_NCTF_12
VCC_NCTF_13
VCC_NCTF_14
VCC_NCTF_15
VCC_NCTF_16
VCC_NCTF_17
VCC_NCTF_18
VCC_NCTF_19
VCC_NCTF_20
VCC_NCTF_21
VCC_NCTF_22
VCC_NCTF_23
VCC_NCTF_24
VCC_NCTF_25
VCC_NCTF_26
VCC_NCTF_27
VCC_NCTF_28
VCC_NCTF_29
VCC_NCTF_30
VCC_NCTF_31
VCC_NCTF_32

VCC NCTF

VCC_NCTF_33
VCC_NCTF_34
VCC_NCTF_35
VCC_NCTF_36
VCC_NCTF_37
VCC_NCTF_38

AT38
AR38
AN38
AM38
AL38
AG38
AE38
AA38
Y38
W38
U38
T38
R38
AT37
AR37
AN37
AM37
AL37
AJ37
AH37
AG37
AE37
AD37
AC37
AA37
Y37
W37
U37
T37
R37
AT35
AR35
U35
AT34
AR34
U34
T34
R34

+1.05V_M

CRB 270uF

22U_0805_6.3VAM~D

10U_0805_10V4Z~D

0.1U_0402_10V7K~D

1

1

C753

C752

C751

2

2

1

2

1U_0402_6.3V4Z~D

0.47U_0402_10V4Z~D

C162

C161

1

2

1U_0402_6.3V4Z~D

C163

1

2

Layout Note:
Place close to GMCH

220U_D2_4VY_R15M~D

1

+

2

22U_0805_6.3VAM~D

C152

C153

1

2

0.22U_0402_10V4Z~D

C155

1

2

Layout Note:
Inside GMCH cavity.

0.22U_0402_10V4Z~D

1

C154

2

0.1U_0402_10V7K~D

C156

1

2

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL

CANTIGA GMCH SFF_FCBGA1363~D

5

4

TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

Cantiga(5 of 6)

LA-4151P

14 57Fr id ay, July 04, 2008

1

1.0

of

5

4

3

2

1

U78I

BA55

VSS_1

AU55

VSS_2

AN55

VSS_3

AJ55

VSS_4

AE55

VSS_5

AA55

VSS_6

U55

VSS_7

N55

D D

C C

B B

A A

VSS_8

BD54

VSS_9

BG53

VSS_10

AJ53

VSS_11

AE53

VSS_12

AA53

VSS_13

U53

VSS_14

N53

VSS_15

J53

VSS_16

G53

VSS_17

E53

VSS_18

K52

VSS_19

BG51

VSS_20

BA51

VSS_21

AW51

VSS_22

AU51

VSS_23

AR51

VSS_24

AN51

VSS_25

AL51

VSS_26

AJ51

VSS_27

AG51

VSS_28

AE51

VSS_29

AC51

VSS_30

AA51

VSS_31

W51

VSS_32

U51

VSS_33

R51
N51

L51

J51
G51
C51

BK50

AM50

K50

BG49

E49
C49

BD48
BB48
AY48
AV48
AT48
AP48

AM48

AK48
AH48
AF48
AD48
AB48

Y48
V48
T48
P48

M48

K48
H48

BL47

BG47

E47
C47
A47

BD46
AY46

AM46

AK46
AH46
BG45
AE45
AC45
AA45

W45

R45
N45
E45

BD44
BB44
AV44
AK44
AH44
AF44
AD44

K44
H44

BL43
BG43
AY43
AR43

W43

R43

M43

E43

CANTIGA GMCH SFF_FCBGA1363~D

VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47
VSS_48
VSS_49
VSS_50
VSS_51
VSS_52
VSS_53
VSS_54
VSS_55
VSS_56
VSS_57
VSS_58
VSS_59
VSS_60
VSS_61
VSS_62
VSS_63
VSS_64
VSS_65
VSS_66
VSS_67
VSS_68
VSS_69
VSS_70
VSS_71
VSS_72
VSS_73
VSS_74
VSS_75
VSS_76
VSS_77
VSS_78
VSS_79
VSS_80
VSS_81
VSS_82
VSS_83
VSS_84
VSS_85
VSS_86
VSS_87
VSS_88
VSS_89
VSS_90
VSS_91
VSS_92
VSS_93
VSS_94
VSS_95
VSS_96
VSS_97
VSS_98
VSS_99

VSS

VSS_100
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105
VSS_106
VSS_107
VSS_108
VSS_109
VSS_110
VSS_111
VSS_112
VSS_113
VSS_114
VSS_115
VSS_116
VSS_117
VSS_118
VSS_119
VSS_120
VSS_121
VSS_122
VSS_123
VSS_124
VSS_125
VSS_126
VSS_127
VSS_128
VSS_129
VSS_130
VSS_131
VSS_132
VSS_133
VSS_134
VSS_135
VSS_136
VSS_137
VSS_138
VSS_139
VSS_140
VSS_141
VSS_142
VSS_143
VSS_144
VSS_145
VSS_146
VSS_147
VSS_148
VSS_149
VSS_150
VSS_151
VSS_152
VSS_153
VSS_154
VSS_155
VSS_156
VSS_157
VSS_158
VSS_159
VSS_160
VSS_161
VSS_162
VSS_163
VSS_164
VSS_165
VSS_166
VSS_167
VSS_168
VSS_169
VSS_170
VSS_171
VSS_172
VSS_173
VSS_174
VSS_175
VSS_176
VSS_177
VSS_178
VSS_179
VSS_180
VSS_181
VSS_182
VSS_183
VSS_184
VSS_185
VSS_186
VSS_187
VSS_188
VSS_189
VSS_190
VSS_191
VSS_192
VSS_193
VSS_194
VSS_195
VSS_196
VSS_197
VSS_198

C43
A43
BD42
H42
BG41
AY41
AU41
AM41
AL41
AG41
AE41
AA41
R41
M41
E41
BD40
AU40
AR40
AN40
W40
U40
T40
R40
K40
H40
BL39
BG39
BA39
E39
C39
A39
BD38
AU38
H38
BG37
AU37
M37
E37
BD36
AW36
H36
BL35
BG35
AY35
AU35
AL35
AG35
AE35
AA35
Y35
M35
E35
A35
BD34
AU34
AN34
H34
BL33
BG33
AY33
E33
BD32
AU32
AN32
AG32
AC32
Y32
H32
B32
BJ31
BG31
AY31
AN31
M31
E31
N30
H30
AN29
AJ29
M29
A29
AW28
AN28
AD28
AC28
Y28
W28
H28
F28
AN27
AJ27
M27
BF26
BD26
N26
H26
BJ25
AY25
AU25

U78J

AN25

VSS_199

AG25

VSS_200

AE25

VSS_201

AA25

VSS_202

Y25

VSS_203

E25

VSS_204

A25

VSS_205

BD24

VSS_206

AN24

VSS_207

AL24

VSS_208

H24

VSS_209

BG23

VSS_210

AY23

VSS_211

E23

VSS_212

BD22

VSS_213

BB22

VSS_214

AN22

VSS_215

Y22

VSS_216

W22

VSS_217

H22

VSS_218

BL21

VSS_219

BG21

VSS_220

AY21

VSS_221

AN21

VSS_222

AG21

VSS_223

AE21

VSS_224

M21

VSS_225

E21

VSS_226

A21

VSS_227

BD20

VSS_228

H20

VSS_229

BG19
AY19

M19

BD18

N18
H18

BL17
BG17
AY17

M17

BD16
AN16
AG16
AE16

W16

N16

H16
BG15
AY15
AN15
AD15
AC15

R15

M15
BD14

H14

BL13
BG13
AY13
AU13
AR13

AJ13
AC13
AA13

W13

U13
M13

BD12
AV12
AP12
AM12
AK12
AB12

H12
BG11
AG11

BD10
AY10
AP10

H10

BG9

BD8

BB8

AY8

AV8

AT8

AP8

E19

E17
A17

Y16

E15

E13
A13

V12
P12

E11

BL9

E9
A9

VSS

VSS_230
VSS_231
VSS_232
VSS_233
VSS_234
VSS_235
VSS_236
VSS_237
VSS_238
VSS_239
VSS_240
VSS_241
VSS_242
VSS_243
VSS_244
VSS_245
VSS_246
VSS_247
VSS_248
VSS_249
VSS_250
VSS_251
VSS_252
VSS_253
VSS_254
VSS_255
VSS_256
VSS_257
VSS_258
VSS_259
VSS_260
VSS_261
VSS_262
VSS_263
VSS_264
VSS_265
VSS_266
VSS_267
VSS_268
VSS_269
VSS_270
VSS_271
VSS_272
VSS_273
VSS_274
VSS_275
VSS_276
VSS_277
VSS_278
VSS_279
VSS_280
VSS_281
VSS_282
VSS_283
VSS_284
VSS_285
VSS_286
VSS_287
VSS_288
VSS_289
VSS_290
VSS_291
VSS_292
VSS_293
VSS_294
VSS_295
VSS_296
VSS_297
VSS_298
VSS_299

CANTIGA GMCH SFF_FCBGA1363~D

VSS_300
VSS_301
VSS_302
VSS_303
VSS_304
VSS_305
VSS_306
VSS_307
VSS_308
VSS_309
VSS_310
VSS_311
VSS_312
VSS_313
VSS_314
VSS_315
VSS_316
VSS_317
VSS_318
VSS_319
VSS_320
VSS_321
VSS_322
VSS_323
VSS_324
VSS_325
VSS_326
VSS_327
VSS_328
VSS_329
VSS_330
VSS_331
VSS_332
VSS_333
VSS_334
VSS_335
VSS_336
VSS_337
VSS_338
VSS_339
VSS_340
VSS_341
VSS_342
VSS_343
VSS_344
VSS_345
VSS_346
VSS_347
VSS_348
VSS_349
VSS_350
VSS_351
VSS_352
VSS_353
VSS_354
VSS_355
VSS_356
VSS_357
VSS_358

VSS_359
VSS_360
VSS_361
VSS_362

VSS_NCTF_1
VSS_NCTF_2
VSS_NCTF_3
VSS_NCTF_4
VSS_NCTF_5
VSS_NCTF_6
VSS_NCTF_7
VSS_NCTF_8

VSS_NCTF_9
VSS_NCTF_10
VSS_NCTF_11
VSS_NCTF_12
VSS_NCTF_13

VSS NCTF

VSS_NCTF_14
VSS_NCTF_15
VSS_NCTF_16
VSS_NCTF_17
VSS_NCTF_18
VSS_NCTF_19
VSS_NCTF_20
VSS_NCTF_21
VSS_NCTF_22
VSS_NCTF_23

VSS_SCB_1
VSS_SCB_2
VSS_SCB_3
VSS_SCB_4
VSS_SCB_5
VSS_SCB_6
VSS_SCB_7

VSS SCB

AM8
AK8
AH8
AF8
AD8
AB8
Y8
V8
P8
M8
K8
H8
BJ7
E7
BF6
BC5
BA5
AW5
AU5
AR5
AN5
AL5
AJ5
AG5
AE5
AC5
AA5
W5
U5
N5
L5
J5
G5
C5
BH4
BE3
U3
E3
BC1
AW1
AR1
AL1
AG1
AC1
W1
N1
J1
AU43
BB42
AW38
BA35
L29
N28
N22
N20
N14
AL13
B10
AN13

N42
N40
N38
M39

AJ38
AH38
AD38
AC38
T35
R35
AT32
AR32
U32
R32
T28
R28
AT25
AR25
T24
R24
AN19
AJ19
AA19
Y19
T19
R19
AN18

BL55
BL1
A55
D1
B55
B2
A4

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

Cantiga(6 of 6)

LA-4151P

15 57Fr id ay, July 04, 2008

1

1.0

of

5

DDR_A_DQS#[0..7]<11>

DDR_A_D[0..63]<11>
DDR_A_DM[0..7]<11>
DDR_A_DQS[0..7]<11>

DDR_A_MA[0..14]<11>

D D

Layout Note:
Place near JDIMMA

+1.5V_MEM

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

C171

C172

1

1

2

2

+1.5V_MEM

C C

+0.75V_DDR_VTT

B B

A A

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

C1114

C1113

1

1

2

2

Layout Note:
Place near JDIMMA.203,204

1U_0603_10V4Z~D

1U_0603_10V4Z~D

1

1

C1120

2

2

0.1U_0402_16V4Z~D

C173

C174

1

1

2

2

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

C1116

C1115

1

2

1

C1121

2

C1117

1

1

2

2

1U_0603_10V4Z~D

1U_0603_10V4Z~D

1

C1123

C1122

2

1

2

10U_0603_6.3V6M~D

C1118

1

2

330U_D2_2.5VY_R15M

1

C1119

+

2

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

1

C1154

C1153

2

4

1

C1155

2

+V_DDR_MCH_REF +1.5V_MEM+1.5V_MEM

2.2U_0603_6.3V6K~D

0.1U_0402_16V4Z~D

1

1

+3.3V_M

C164

2

DDR_CKE0_DIMMA<10>

DDR_CS1_DIMMA#<10>

0.1U_0402_16V4Z~D

C165

2

DDR_A_BS2<11>

M_CLK_DDR0<10>

DDR_A_BS0<11>
DDR_A_WE#<11>

DDR_A_CAS#<11>

2.2U_0603_6.3V6K~D
C190

C189

1

1

2

2

DDR_A_D0
DDR_A_D1

DDR_A_DM0
DDR_A_D2

DDR_A_D3
DDR_A_D8

DDR_A_D13
DDR_A_DQS#1

DDR_A_DQS1
DDR_A_D10

DDR_A_D11
DDR_A_D20 DDR_A_D22

DDR_A_D17
DDR_A_DQS#2

DDR_A_DQS2
DDR_A_D18

DDR_A_D19
DDR_A_D25

DDR_A_D30
DDR_A_DM3
DDR_A_D26

DDR_A_D27

DDR_CKE0_DIMMA DDR_CKE1_DIMMA

DDR_A_BS2

DDR_A_MA3

M_CLK_DDR0
M_CLK_DDR#0

DDR_A_MA10
DDR_A_BS0

DDR_A_WE#
DDR_A_CAS#

DDR_A_MA13

DDR_CS1_DIMMA#

DDR_A_D32
DDR_A_D39

DDR_A_DQS#4
DDR_A_DQS4

DDR_A_D34
DDR_A_D35

DDR_A_D40
DDR_A_D41

DDR_A_DM5
DDR_A_D42

DDR_A_D43
DDR_A_D54

DDR_A_D49
DDR_A_DQS#6

DDR_A_DQS6
DDR_A_D50

DDR_A_D51
DDR_A_D56

DDR_A_D57
DDR_A_DM7
DDR_A_D58

DDR_A_D59

1 2

R128 10K_0402_5%~D

1 2

R129 10K_0402_5%~D

+0.75V_DDR_VTT

3

JDIMMA

1

VREF_DQ

3

VSS

5

DQ0

7

DQ1

9

VSS

11

DM0

13

VSS

15

DQ2

17

DQ3

19

VSS

21

DQ8

23

DQ9

25

VSS

27

DQS1#

29

DQS1

31

VSS

33

DQ10

35

DQ11

37

VSS

39

DQ16

41

DQ17

43

VSS

45

DQS2#

47

DQS2

49

VSS

51

DQ18

53

DQ19

55

VSS

57

DQ24

59

DQ25

61

VSS

63

DM3

65

VSS

67

DQ26

69

DQ27

71

VSS

73

CKE0

75

VDD

77

NC

79

BA2

81

VDD

83

A12/BC#

85

A9

87

VDD

89

A8

91

A5

93

VDD

95

A3

97

A1

99

VDD

101

CK0

103

CK0#

105

VDD

107

A10/AP

109

BA0

111

VDD

113

WE#

115

CAS#

117

VDD

119

A13

121

S1#

123

VDD

125

TEST

127

VSS

129

DQ32

131

DQ33

133

VSS

135

DQS4#

137

DQS4

139

VSS

141

DQ34

143

DQ35

145

VSS

147

DQ40

149

DQ41

151

VSS

153

DM5

155

VSS

157

DQ42

159

DQ43

161

VSS

163

DQ48

165

DQ49

167

VSS

169

DQS6#

171

DQS6

173

VSS

175

DQ50

177

DQ51

179

VSS

181

DQ56

183

DQ57

185

VSS

187

DM7

189

VSS

191

DQ58

193

DQ59

195

VSS

197

SA0

199

VDDSPD

201

SA1

203

VTT

205

GND1

FOX_AS0A626-U4SN-7F

VSS
DQ4
DQ5

VSS

DQS0#

DQS0

VSS
DQ6
DQ7

VSS

DQ12
DQ13

VSS
DM1

RESET#

VSS

DQ14
DQ15

VSS

DQ20
DQ21

VSS
DM2

VSS

DQ22
DQ23

VSS

DQ28
DQ29

VSS

DQS3#

DQS3

VSS

DQ30
DQ31

VSS

CKE1

VDD

A15

A14
VDD

A11
VDD

VDD

VDD

CK1

CK1#

VDD

BA1

RAS#

VDD

S0#

ODT0

VDD

ODT1

VDD

VREF_CA

VSS

DQ36
DQ37

VSS
DM4

VSS

DQ38
DQ39

VSS

DQ44
DQ45

VSS

DQS5#

DQS5

VSS

DQ46
DQ47

VSS

DQ52
DQ53

VSS
DM6

VSS

DQ54
DQ55

VSS

DQ60
DQ61

VSS

DQS7#

DQS7

VSS

DQ62
DQ63

VSS

EVENT#

SDA

SCL

VTT

GND2

2

2

DDR_A_D4

4

DDR_A_D5

6
8

DDR_A_DQS#0

10

DDR_A_DQS0

12
14

DDR_A_D6

16

DDR_A_D7

18
20

DDR_A_D14

22

DDR_A_D15

24
26

DDR_A_DM1

28

SM_DRAMRST#

30
32

DDR_A_D9

34

DDR_A_D12

36
38
40

DDR_A_D21

42
44

DDR_A_DM2

46
48

DDR_A_D16

50

DDR_A_D23

52
54

DDR_A_D28

56

DDR_A_D29

58
60

DDR_A_DQS#3

62

DDR_A_DQS3

64
66

DDR_A_D24

68

DDR_A_D31

70
72

74
76
78

DDR_A_MA14

80
82

DDR_A_MA11DDR_A_MA12

84

DDR_A_MA7DDR_A_MA9

86

A7

88

DDR_A_MA6DDR_A_MA8

90

A6
A4

A2
A0

NC

92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204

206

DDR_A_MA4DDR_A_MA5
DDR_A_MA2

DDR_A_MA0DDR_A_MA1
M_CLK_DDR1

M_CLK_DDR#1
DDR_A_BS1

DDR_A_RAS#
DDR_CS0_DIMMA#

M_ODT0
M_ODT1

DDR_A_D36
DDR_A_D37

DDR_A_DM4
DDR_A_D33

DDR_A_D38
DDR_A_D47

DDR_A_D45
DDR_A_DQS#5

DDR_A_DQS5
DDR_A_D46

DDR_A_D44
DDR_A_D52

DDR_A_D53
DDR_A_DM6
DDR_A_D48

DDR_A_D55
DDR_A_D60

DDR_A_D61
DDR_A_DQS#7

DDR_A_DQS7
DDR_A_D62

DDR_A_D63
PM_EXTTS#0

MEM_SDATA
MEM_SCLK

+0.75V_DDR_VTT

SM_DRAMRST# <10,17>

DDR_CKE1_DIMMA <10>

T161PAD~D

M_CLK_DDR1 <10>

M_CLK_DDR#1 <10>M_CLK_DDR#0<10>

DDR_A_BS1 <11>

DDR_A_RAS# <11>

DDR_CS0_DIMMA# <10>

M_ODT0 <10>
M_ODT1 <10>

2.2U_0603_6.3V6K~D

PM_EXTTS#0 <10,17,18>
MEM_SDATA <17,24>

MEM_SCLK <17,24>

1

C1089

2

+V_DDR_MCH_REF

0.1U_0402_16V4Z~D

1

C1088

2

1

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

DDRIII-SODIMM SLOT1

LA-4151P

16 57Fr id ay, July 04, 2008

1

1.0

of

5

4

3

2

1

+1.5V_MEM

DDR_B_D0
DDR_B_D1

DDR_B_DM0
DDR_B_D2

DDR_B_D3
DDR_B_D8

DDR_B_D9
DDR_B_DQS#1

DDR_B_DQS1
DDR_B_D10

DDR_B_D11
DDR_B_D16

DDR_B_D17
DDR_B_DQS#2

DDR_B_DQS2
DDR_B_D18

DDR_B_D19
DDR_B_D24

DDR_B_D25
DDR_B_DM3
DDR_B_D26

DDR_B_D27

DDR_CKE2_DIMMB

DDR_B_BS2
DDR_B_MA12

DDR_B_MA9
DDR_B_MA8

DDR_B_MA5
DDR_B_MA3

DDR_B_MA1
M_CLK_DDR2

M_CLK_DDR#2
DDR_B_MA10

DDR_B_BS0
DDR_B_WE#

DDR_B_CAS#
DDR_B_MA13

DDR_CS3_DIMMB#

DDR_B_D32
DDR_B_D33

DDR_B_DQS#4
DDR_B_DQS4

DDR_B_D34
DDR_B_D35

DDR_B_D40
DDR_B_D41

DDR_B_DM5
DDR_B_D42

DDR_B_D43
DDR_B_D48

DDR_B_D49

DDR_B_DQS6
DDR_B_D50

DDR_B_D51
DDR_B_D56

DDR_B_D57
DDR_B_DM7
DDR_B_D58

DDR_B_D59

2.2U_0603_6.3V6K~D

+0.75V_DDR_VTT

C216

C215

1

1

2

2

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

2.2U_0603_6.3V6K~D

DDR_B_DQS#[0..7]<11>

DDR_B_D[0..63]<11>
DDR_B_DM[0..7]<11>

D D

C C

B B

A A

DDR_B_DQS[0..7]<11>

DDR_B_MA[0..14]<11>

+1.5V_MEM

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

+1.5V_MEM

10U_0603_6.3V6M~D

Layout Note:
Place near JDIMMB.203,204

+0.75V_DDR_VTT

C199

C198

1

1

2

2

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

C1124

1

2

1U_0603_10V4Z~D

1

C1131

2

C1126

C1125

1

1

2

2

1U_0603_10V4Z~D

1

C1132

2

5

Layout Note:
Place near JDIMMB

0.1U_0402_16V4Z~D

C200

C201

1

1

2

2

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

1

2

1U_0603_10V4Z~D

1

2

C1133

C1127

10U_0603_6.3V6M~D

C1128

C1129

1

1

2

2

1U_0603_10V4Z~D

1

C1134

2

330U_D2_2.5VY_R15M

1

C1130

+

2

4

1

2

+3.3V_M

C191

DDR_CKE2_DIMMB<10>

DDR_CS3_DIMMB#<10>

+3.3V_M

R131

10K_0402_5%~D

0.1U_0402_16V4Z~D

M_CLK_DDR2<10>
M_CLK_DDR#2<10>

DDR_B_CAS#<11>

12

DDR_B_BS2<11>

DDR_B_BS0<11>
DDR_B_WE#<11>

10K_0402_5%~D

+V_DDR_MCH_REF

1

C192

2

0.1U_0402_16V4Z~D

12

R132

JDIMMB

1

VREF_DQ

3

VSS

5

DQ0

7

DQ1

9

VSS

11

DM0

13

VSS

15

DQ2

17

DQ3

19

VSS

21

DQ8

23

DQ9

25

VSS

27

DQS1#

29

DQS1

31

VSS

33

DQ10

35

DQ11

37

VSS

39

DQ16

41

DQ17

43

VSS

45

DQS2#

47

DQS2

49

VSS

51

DQ18

53

DQ19

55

VSS

57

DQ24

59

DQ25

61

VSS

63

DM3

65

VSS

67

DQ26

69

DQ27

71

VSS

73

CKE0

75

VDD

77

NC

79

BA2

81

VDD

83

A12/BC#

85

A9

87

VDD

89

A8

91

A5

93

VDD

95

A3

97

A1

99

VDD

101

CK0

103

CK0#

105

VDD

107

A10/AP

109

BA0

111

VDD

113

WE#

115

CAS#

117

VDD

119

A13

121

S1#

123

VDD

125

TEST

127

VSS

129

DQ32

131

DQ33

133

VSS

135

DQS4#

137

DQS4

139

VSS

141

DQ34

143

DQ35

145

VSS

147

DQ40

149

DQ41

151

VSS

153

DM5

155

VSS

157

DQ42

159

DQ43

161

VSS

163

DQ48

165

DQ49

167

VSS

169

DQS6#

171

DQS6

173

VSS

175

DQ50

177

DQ51

179

VSS

181

DQ56

183

DQ57

185

VSS

187

DM7

189

VSS

191

DQ58

193

DQ59

195

VSS

197

SA0

199

VDDSPD

201

SA1

203

VTT

205

GND1

FOX_AS0A626-U8SN-7F

VREF_CA

VSS
DQ4
DQ5
VSS

DQS0#

DQS0

VSS
DQ6
DQ7

VSS
DQ12
DQ13

VSS

DM1

RESET#

VSS
DQ14
DQ15

VSS
DQ20
DQ21

VSS

DM2

VSS
DQ22
DQ23

VSS
DQ28
DQ29

VSS

DQS3#

DQS3

VSS
DQ30
DQ31

VSS

CKE1

VDD

VDD

VDD

VDD

VDD

CK1

CK1#

VDD

BA1
RAS#

VDD
ODT0

VDD
ODT1

VDD

VSS
DQ36
DQ37

VSS

DM4

VSS
DQ38
DQ39

VSS
DQ44
DQ45

VSS

DQS5#

DQS5

VSS
DQ46
DQ47

VSS
DQ52
DQ53

VSS

DM6

VSS
DQ54
DQ55

VSS
DQ60
DQ61

VSS

DQS7#

DQS7

VSS
DQ62
DQ63

VSS

EVENT#

SDA

SCL

VTT

GND2

A15
A14

A11

A7
A6

A4
A2

A0

S0#

NC

+1.5V_MEM+V_DDR_MCH_REF

2

DDR_B_D4

4

DDR_B_D5

6
8

DDR_B_DQS#0

10

DDR_B_DQS0

12
14

DDR_B_D6

16

DDR_B_D7

18
20

DDR_B_D12

22

DDR_B_D13

24
26

DDR_B_DM1

28

SM_DRAMRST#

30
32

DDR_B_D14

34

DDR_B_D15

36
38

DDR_B_D20

40

DDR_B_D21

42
44

DDR_B_DM2

46
48

DDR_B_D22

50

DDR_B_D23

52
54

DDR_B_D28

56

DDR_B_D29

58
60

DDR_B_DQS#3

62

DDR_B_DQS3

64
66

DDR_B_D30

68

DDR_B_D31

70
72

DDR_CKE3_DIMMB

74
76
78

DDR_B_MA14

80
82

DDR_B_MA11

84

DDR_B_MA7

86
88

DDR_B_MA6

90

DDR_B_MA4

92
94

DDR_B_MA2

96

DDR_B_MA0

98
100

M_CLK_DDR3

102

M_CLK_DDR#3

104
106

DDR_B_BS1

108

DDR_B_RAS#

110
112

DDR_CS2_DIMMB#

114

M_ODT2

116
118

M_ODT3

120
122
124
126
128

DDR_B_D36

130

DDR_B_D37

132
134

DDR_B_DM4

136
138

DDR_B_D38

140

DDR_B_D39

142
144

DDR_B_D44

146

DDR_B_D45

148
150

DDR_B_DQS#5

152

DDR_B_DQS5

154
156

DDR_B_D46

158

DDR_B_D47

160
162

DDR_B_D52

164

DDR_B_D53

166
168

DDR_B_DM6DDR_B_DQS#6

170
172

DDR_B_D54

174

DDR_B_D55

176
178

DDR_B_D60

180

DDR_B_D61

182
184

DDR_B_DQS#7

186

DDR_B_DQS7

188
190

DDR_B_D62

192

DDR_B_D63

194
196

PM_EXTTS#0

198

MEM_SDATA

200

MEM_SCLK

202
204

206

+0.75V_DDR_VTT

2

SM_DRAMRST# <10,16>

DDR_CKE3_DIMMB <10>

T162

PAD~D

M_CLK_DDR3 <10>

M_CLK_DDR#3 <10>

DDR_B_BS1 <11>

DDR_B_RAS# <11>
DDR_CS2_DIMMB# <10>

M_ODT2 <10>
M_ODT3 <10>

2.2U_0603_6.3V6K~D

1

2

PM_EXTTS#0 <10,16,18>
MEM_SDATA <16,24>
MEM_SCLK <16,24>

+V_DDR_MCH_REF

0.1U_0402_16V4Z~D

1

C1090

C1091

2

DELL CONFIDENTIAL/PROPRIETARY

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

DDRIII-SODIMM SLOT2

LA-4151P

17 57Fr id ay, July 04, 2008

1

1.0

of

5

+3.3V_M

12

R134

8.2K_0402_5%~D

+1.05V_VCCP

R135

D D

H_THERMTRIP#<7>

THERMTRIP_MCH#<10>

2.2K_0402_5%~D

1 2

MMST3904-7-F_SOT323-3~D

+1.05V_VCCP

R138

2.2K_0402_5%~D

1 2

MMST3904-7-F_SOT323-3~D

THERMATRIP1#

C

E

3 1

12

C

E

3 1

1

C218

0.1U_0402_16V4Z~D

2

R137

8.2K_0402_5%~D

THERMATRIP2#

1

C220

0.1U_0402_16V4Z~D

2

RB751S40T1_SOD523-2~D

2

B

Q5

+3.3V_M

2

B

Q6

Place under CPU

C225

1

+RTC_CELL

C229

0.1U_0402_16V4Z~D

2

1

C231

2

12

R155

8.2K_0402_5%~D

THERMATRIP3#

1

C240

0.1U_0402_16V4Z~D

2

C

E

3 1

1

2

C

E

3 1

100P_0402_50V8K~D

C C

H_THERMDA<7>

H_THERMDC<7>

Q9 Place near DIMM
Place C227 close

to Q9

+3.3V_M

B B

1

Place C223 close to the Q8 as possible
Place C224, C225 close to the Guardian pins as possible

470P_0402_50V7K~D

Place C228 close to the Guardian pins as possible

1

C227

@

100P_0402_50V8K~D

2

1 2

R142 0_0603_5%~D

0.1U_0402_16V4Z~D

2

C223

@

Rset=1.5K,Tp=95degree

+3.3V_M

A A

5

4

D2

2 1

2

B

Q8
MMST3904-7-F_SOT323-3~D

2

B

Q9

MMST3904-7-F_SOT323-3~D

12

R151

1.5K_0402_1%~D

2200P_0402_50V7K~D

+5V_RUN

4

C219

1U_0603_10V4Z~D

1

2

0.1U_0402_16V4Z~D

1

C234

2

1

2

22U_0805_6.3VAM~D

BC_DAT_EMC4002<34>

BC_CLK_EMC4002<34>

2

C224
2200P_0402_50V7K~D

1

C228

C230

3.3V_M_PWRGD<34,37>
ICH_PWRGD#<37>

10U_0805_10V4Z~D

+3.3V_RUN

C235

1

2

3

+3.3V_M

12

R136
10K_0402_5%~D

FAN1_DET#<22>

1

2

R146 1K_0402_5%~D
R148 1K_0402_5%~D

+3V_M_THRM

10U_0805_10V4Z~D

0.1U_0402_16V4Z~D

1

1

C237

C236

2

2

EC_32KHZ_OUT<34>

Pull-up Resistor
on ADDR_MODE/XEN

<= 4.7K +/- 5% 2F(r/w)

*

10K
18K

>= 33K

+FAN1_VOUT

FAN1_TACH_FB

REM_DIODE1_N

REM_DIODE3_P
REM_DIODE3_N

+3V_M_THRM
+RTC_CELL_R

1 2
1 2

THERMATRIP1#
THERMATRIP2#
THERMATRIP3#

VSET

12

R150 4.7K_0402_5%~D

+FAN1_VOUT

FAN1_TACH_FB

EC_32KHZ_OUT

For Remote1
mode

2N3904

2N3904
Thermistor
Thermistor

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

JFAN1

1

1

2

2

3

3

4

4

5

GND

6

GND

MOLEX_53780-0470

U3
EMC4002

10

SMDATA/BC-LINK_DATA

11

SMBCLK/BC-LINK_CLK

36

DP1/VREF_T

35

DN1/THERM

38

DP2

37

DN2

41

DP3/DN7

40

DN3/DP7

4

VCC

21

RTC_PWR3V

THERMTRIP_SIO/PWM1/GPIO5

18

VCC_PWRGD

17

3V_PWROK#

22

THERMTRIP1#

23

THERMTRIP2#

24

THERMTRIP3#

42

VSET

3

ADDR_MODE/XEN

6

VDD_5V

5

VDD_5V

9

VDD_3V

7

FAN_OUT

8

FAN_OUT

15

TACH1/GPIO3

14

CLK_IN/GPIO2

SMBUS
Address

2E(r/w)
2F(r/w)
2E(r/w)

200K_0402_1%~D

DP6/VREF_T2

ATF_INT#/BC-LINK_IRQ#

POWER_SW#
ACAVAIL_CLR

VDDH/VDD_5V2
VDDH/VDD_5V2

VDDL/VDD_3V2

LDO_OUT/FAN_OUT2
LDO_OUT/FAN_OUT2

TACH2/GPIO4

PWM2/GPIO1

VSS

49

0_0402_5%~D

R1033

VIN1
VCP1
VCP2

DP4/DN8
DN4/DP8

DP5/DN9
DN5/DP9

DN6/VIN2

SYS_SHDN#

LDO_SHDN#

LDO_POK

LDO_SET

POWER_SW#

12

R1032

12

39
48
45

REM_DIODE4_PREM_DIODE1_P

44

REM_DIODE4_N

43
47

46
1

2

R141 10K_0402_5%~D

12

POWER_SW#

26
27
20
25

R1081

@

19

R149 10K_0402_5%~D

34

LDO_SET

33

+3V_LDOIN

32
31

28
29

30
16

13

+RTC_CELL

5

IN1

4

O

IN2

3

12

R1063 0_0402_5%~D@

12

R1064 0_0402_5%~D@

2

1 2

R1061 4.7K_0402_5%~D

Place C221 close to the
Guardian pins as possible.

12

C1158 0.1U_0402_16V4Z~D

1 2

P

G

U93
74AHC1G08GW_SOT353-5~D

BC_INT#_EMC4002 <34>
ACAV_IN <34,46>

12

10K_0402_5%~D

12

2.5V_RUN_PWRGD <33,37>

+1.8V_RUN_LVDS

10U_0805_10V6K~D

1

2

1

R143 0_0402_5%~D

2

R144 0_0402_5%~D

2

1

PWR_MON_GFX <47>

PWR_MON <45>

MAX8731_IINP

1

C221

2

2200P_0402_50V7K~D

THERMISTOR OPTION:
Single-ended ro ut in g t o thermistor is permissible
(ground retu r n ) . Pl a c e R139 and C226 near EMC4002

+3.3V_M

0.1U_0402_16V4Z~D

1

C239

C238

2

12
12

MAX8731_IINP <46>

1 2

R139

1.2K_0402_1%~D

R145 10K_0402_5%~D

1 2

R147 47K_0402_1%~D@

+3.3V_SUS

10U_0805_10V4Z~D

1

1

@

C232

2

2

PM_EXTTS#0 <10,16,17>

DOCK_PWR_SW# <34>
POWER_SW_IN# <34>

Diode circui t a t DP 4 /DN4 is used for skin
temp sensor (p la ce d o ptimally between CPU,
MCH and MEM).

C

Q7

2

B

MMST3904-7-F_SOT323-3~D

E

3 1

1 2

R140
10KB_0603_1%_TSM1A103F34D3R~D

1 2

C226

0.1U_0402_16V4Z~D

12

At maximum loa d c ur rent of 600mA,the the
voltage drop a c r o ss the should be keep
in the range of 0.5V to 1V

0.1U_0402_16V4Z~D
R152
0_1210_5%~D

C233

+3.3V_M

THERM_STP# <42>

+RTC_CELL

+3.3V_RUN

12

1

C222

@

100P_0402_50V8K~D

2

Place C222 close to Q7 as
possible.

LDO_SET

Voltage margi ning circuit
for LDO output. Adjustable
from 1.2 to 2.5V.
Ra=((LDO_OUT /1.2)-1)*Rb.

DELL CONFIDENTIAL/PROPRIETARY

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

FAN & Thermal Sensor

LA-4151P

1

+1.8V_RUN_LVDS

3.16K_0402_1%~D

12

R153

5.1K_0402_1%~D

12

R154

18 57Fr id ay, July 04, 2008

Ra

Rb

1.0

of