A
B
COMPAL CONFIDENTIAL
C
D
E
1 1
PCB NO :
LA4151P(DAA00000Q1L)
MODEL NAME :
JAL10
BOM P/N :
M09 Lola UMA
uFCBGA Mobile Penryn
2 2
3 3
Intel Cantiga GM + ICH9M
2008-07-4
REV : 1.0
@ : Nopop Component
1@ : Use TCM only
2@ : Use TAA only
3@ : Use BROADCOM TPM only
4@ : Use without TAA only
5@ : Use with BKT only
6@ : Use without BKT only
7@ : Use disable TPM only
8@ : Use with TCM depop
9@ : Use with ZTE TCM
4 4
MB PCB
Part Number Description
DAA00000Q1L
PCB 03S LA-4151P REV0 M/B
A
10@ : Use with Jetway TCM
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
B
C
DELL CONFIDENTIAL/PROPRIETARY
Title
Size Document Number Rev
D
Date: Sheet
Compal Electronics, Inc.
Cover Sheet
LA-4151P
157Friday, July 04, 2008
E
1.0
of
A
B
C
D
E
Block Diagram
Compal confidential
Model : JAL10
FAN
1 1
+FAN1_VOUT
page 18 page6page 7
On daughter board
CRT CONN
+5V_RUN
RGB
page 29
SVID
RGB
DPB
SD/MMC/MMC+
CONN
+3.3V_RUN
2 2
DOCKING
page 27
PORT
page 31
DAI
USB[8,9]
SATA3
DOCK LPC BUS
PCIE2 PCIE1
Mini Card2
WLAN
+3.3V_WLAN
+1.5V_RUN +1.5V_RUN
3 3
BKT CONN
+3.3V_BKT_PWR
4 4
USB[4] USB[5] USB[6]
On daughter board
Trough BTB
page 39
1.8V/0.75V
page 44
VCORE (IMVP-6)
page 45
CHARGER
page 46 page 41
ExpressCard
+3.3V_RUN
+1.5V_RUN
Mini Card 1
WWAN
+3.3V_RUN
BKT_USBH
Trough FPC
LVDS CONN
+PWR_SRC
+5V_ALW
+3.3V_RUN
Camera Card
Trough FPC
USB[11]
1.5V/1.05V
A
page 28
PCIE4
Smart Card
PCI Express BUS
page 21page 21
page 32
RFID
Trough FPC
page 19
page 19
page 43
Trough FFC
page 32
Biometric
+3.3V_RUN
BATT IN3V/5V
DC IN
Thermal
GUARDIAN III
EMC4002
+3.3V_SUS
Vedio Switch
TS3DV520ERHUR
+3.3V_RUN
PCI BUS
IDSEL:AD17
(PIRQC#,PIRQD#,GNT#1,REQ#1)
R5C833
+3.3V_RUN
BlueTooth
+3.3V_RUN
73S8009CN
+5V_RUN
+3.3V_RUN
BKT_USBBIO
page 29
page 27
USB[7]
+3.3V_RUN/ +1.5V_RUN 100MHz
page 30
page 32
USBH
Touch Pad
page 41page 42
page 18
LVDS
RGB
page 20
SVID
DPC
+3VRUN 33MHz
IEEE1394
Trough BTB
Option
TPM1.2
For China
page 30
USH
TPM1.2
SSX35BCB
BCM5880
+3.3V_RUN
+2.5V_RUN
+1.2V_RUN
USB[10]
SMBUS
Trough Cable
page 35
Stick
Power Sequence
Power On/Off
SW & LED
B
page 21
page 32
page 37
page 38
Pentium-M
+1.5V_RUN
+1.05V_VCCP
+VCC_CORE
H_A#(3..35) H_D#(0..63)
+3.3V_RUN
+1.8V_RUN
+1.5V_MEM
+1.5V_RUN
+VCC_GFXCORE
+1.05V_M
+1.05V_VCCP
Penryn -4MB
uFCBGA SFF CPU
956pin
System Bus
FSB 800/1066 MHz
INTEL
Cantiga SFF
1363pin BGA
page 10,11,12,13,14,15
DMI
+1.5V_RUN
100MHz
+RTC_CELL
+3.3V_ALW_ICH
+3.3V_RUN
+1.5V_RUN
+1.05V_VCCP
LPC BUS
+3V_RUN
33MHz
INTEL
ICH9-M SFF
569pin BGA
page 22,23,24,25
SMSC KBC
MEC5035
+RTC_CELL
+3.3V_ALW
ECE1077
+3.3V_ALW
page 35
page 34
ECE1088
+3.3V_ALW
Int.KBD &
page 35
Stick
22X22mm
page 7,8,9
25X27mm
16X16mm
SPI
W25X32VSSIG
+3.3V_LAN
W25X32VSSIG
+3.3V_LAN
page 24
16M 4K section
page 24
SPI
DOCK LPC BUS
BC BUS
BC BUSBC BUS
page 35
C
CPU ITP Port
+1.05V_VCCP
Memory BUS
(DDR3)
48MHz
+1.5V_MEM 800 / 1066MHz
USB[3] L SIDE
USB[0] R SIDE
GLCI/LCI
Azalia I/F
S-ATA 0/1
SATA1 SATA0
ODD
+5V_MOD
page 26
SST25VF016B
+3.3V_ALW
page 34
SMSC SIO
ECE5028
+3.3V_ALW
page 33
SATA4
+3V_RUN/ +1.5V_RUN 100MHz
S-HDD
+5V_HDD
+3.3V_RUN
page 26
D
E-SATA
USB Ports X1
+5V_ALW
USB Ports X1
+5V_ALW
Azalia Codec
92HD71B
+3.3V_RUN
+VDDA
Clock Generator
CK505
SLG8LP554
+3.3V_M
DDRII-DIMM X2
BANK 0, 1, 2, 3, 4 ,5 ,6 ,7 ,8
+1.5V_MEM
+0.75V_DDR_VTT
page 29
page 29
page 21
page 16,17
On daughter board
Trough BTB
Intel Boaz
82567LM
+3.3V_ALW
+1.8V_LAN_M
page 21
AMP & INT.
Speaker
+5V_RUN
page 21
HeadPhone &
MIC Jack
+3.3V_RUN
page 21
+1V_LAN_M
page 21
LAN SWITCH
PI3L500-AZFEX
+3.3V_ALW
RJ45
SNIFFER
DAI
+3.3V_RUN
page 21
DOCKSSM2602
Dig. MIC
page 19
Trough cable
DELL CONFIDENTIAL/PROPRIETARY
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
Block Diagram
LA-4151P
257Friday, July 04, 2008
E
pg 21
1.0
of
5
4
3
2
1
POWER STATES
State
D D
S0 (Full ON) / M0
S3 (Suspend to RAM) / M1
S4 (Suspend to DISK) / M1 ON ON ON ONOFF
S5 (SOFT OFF) / M1 ON ON ON ONOFFLOW HIGH LOW HIGHLOW
S3 (Suspend to RAM) / M-OFF
S4 (Suspend to DISK) / M-OFF
S5 (SOFT OFF) / M-OFF
Signal
SLP
SLP
S3#
S4#
HIGH HIGH H IGH
HIGH
LOW HIGH HIGH HIGH ON ON ON ONOFF
LOW HIGH HIGH HIGHLOW
LOW HIGH HIGH HIGH LOW ON ONOFF OFF OFF
LOW LOW LOW LOW ON OFF OFF OFF OFF
LOW LOW LOW LOW LOW ON OFF OFF OFF OFF
SLP
S5#
HIGH
S4
STATE#
SLP
M#
HIGH
HIGH
ALWAYS
PLANE
ON
M
PLANE
ON
SUS
RUN
PLANE
PLANE
ON ON ON
CLOCKS
ICH9-M
USB PORT#
0
1
2
3
4
5
6
7
DESTINATION
JUSB1 (Ext Right Side Top)
BLT mode
None
JESATA1 (Ext Left Side Bottom)
WLAN
WWAN
BT
Express card
DOCKING8
C C
B B
PM TABLE
State
S0
S3
S5 S4/AC
S5 S4/AC don't exist
power
plane
+15V_ALW
+5V_ALW
+3.3V_ALW_ICH
+3.3V_RTC_LDO
ON
ON
+3.3V_SUS
+1.5V_MEM
ON ON
ON
OFF
OFFOFF
+5V_RUN
+3.3V_RUN
+2.5V_RUN
+1.5V_RUN
+1.8V_RUN
+0.75V_DDR_VTT
+VCC_GFXCORE
+VCC_CORE
+1.05V_VCCP
OFFON
OFF
OFF
ON
ON
ON
+3.3V_M
(M-OFF)
ON
OFF
OFF
OFFOFF
+3.3V_M
+1.05V_M +1.05V_M
+3.3V_RUN_
WWAN_PWR
+3.3V_RUN_
BKT_PWR
+3.3V_BKT
_PWR
+INV_PWR_SRC
+LCDVDD
ON
OFF
OFF
OFF
ONON OFF OFF OFF OFFBlackTop mode
PCI EXPRESS
Lane 1
Lane 2
Lane 3
Lane 4
Lane 5
Lane 6
9
11
DESTINATION
MINI CARD-1 WWAN
MINI CARD-2 WLAN
None
EXPRESS CARD
None
None
10/100/1G LAN
DOCKING
USH->BIO10
Camera
PCI TABLE
REQ#/GNT#
R5C833 REQ#1 / GNT#1AD17
A A
PIRQPCI DEVICE IDSEL
PIRQ[C..D]
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
Index and Config.
LA-4151P
357Friday, July 04, 2008
1
1.0
of
5
4
3
2
1
RUN_ON
FDS4435
Q16
+INV_PWR_SRC
ADAPTER
D D
GFX_CORE_ON
ADP3209
(PU15)
+VGFX_COREP
BlackTop function
BATTERY
+PWR_SRC
RUN_ON&BKT_GPIO4
STS11NF30L
(Q145)
+5V_RUN_
BKT_PWR
+15V_ALW
CHARGER
C C
ALW_ON
3.3V_SUS_ON
ISL6236
(PU2)
SI3456BDV
(Q60)
(PU7) (PU14)
IMVP_VR_ON
+VCC_CORE +0.75V_DDR_VTT +1.5V_MEM
MAX8794ISL6260
(PU12)
1.8V_RUN_ON
+1.8V_RUN +1.05V_M
TPS51100D
GQRG4
0.75V_DDR_VTT_ON
VT351FC
(PU25,PU26)
ISL6236
(PU2)
1.5V_RUN_ON
DDR_ON
SI4336DY
(Q128)
ALWON
ALWON
+5V_ALW
+3.3V_ALW
ENAB_3VLAN
STS11NF30L
RUN_ON
3.3V_RUN_ON&BKT_GPIO3
3.3V_RUN_ON
(Q44)
STS11NF30L
BKT_GPIO2
SI4336DY
(Q61)
(Q55)
MAX8511(LDO)
(U103)
BlackTop function
SI4336DY
+5V_RUN
+1.5V_ALW_HDA
(Q140)
+5V_ALW
B B
HDDC_EN
MODC_EN
+3.3V_SUS
RUN_ON
1.05V_RUN_ON M_ON
SI4336DY
Q67
+1.5V_RUN
On I/O board
+3.3V_LAN
REGCTL_PNP1
REGCTL_PNP18
+3.3V_RUN
+3.3V_RUN_
BKT_PWR
BCP69BCP69
SI3456BDVSI3456BDV
(Q29)(Q32)
A A
+5V_HDD
+5V_MOD
TPA6040
(U9)
+VDDA
+1.05V_VCCP
(Q4) SI3456BDV
(Q3)
(Q143)
+3.3V_BKT_PWR
+1V_LAN_M
+1.8V_LAN_M
SI4336DY
(Q137)
+3.3V_RUN_
WWAN_PWR
DELL CONFIDENTIAL/PROPRIETARY
on I/O board
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
Power Rail
LA-4151P
457Friday, July 04, 2008
1
1.0
of
5
G16
ICH_SMBCLK
ICH_SMBDATA
A13
ICH9-M
D D
E18
A24
AMT_SMBCLK
AMT_SMBDAT
2.2K
2.2K
10K
10K
4
+3.3V_ALW
+3.3V_ALW_ICH
2N7002
2N7002
MEM_SCLK
MEM_SDATA
3
2.2K
2.2K
+3.3V_M
197
195
DIMMA
197
195
DIMMB
SMBUS Address[A0h]
SMBUS Address[A4h]
2
1
8.2K
9493
2A 2A
6
5
DOCK_SMB_CLK
DOCK_SMB_DAT
1A
1A
8.2K
8.2K
8.2K
8
7
LCD_SMBCLK
LCD_SMDATA
C C
1B
1B
+5V_ALW
+3.3V_ALW
6
5
6
5
DOCKING
INVERTER
(JLVDS)
SMBUS Address[48h]Dock_APR
SMBUS Address[70h]DOCK_SPR
SMBUS Address[58h]
2.2K
PBAT_SMBCLK
112
10
9
100
99
98
97
PBAT_SMBDAT
BKT_SMBCLK
BKT_SMBDAT
CARD_SMBCLK
CARD_SMBDAT
KBC
B B
1C1C111
1D
1D
1E
1E
1F
1F
2.2K
2.2K
2.2K
MEC 5035
96
1G
95
1H
2.2K
12
1H
1H
A A
1J
1J
1K
1K
5
CKG_SMBDAT
13
CKG_SMBCLK
106
105
Dedicated JTAG
103
102
Dedicated JTAG
2.2K
9
Charger
10
SMBUS Address[12h]
+3.3V_ALW
+3.3V_ALW
+3.3V_ALW
4
100 ohm
100 ohm
3
4
27
29
BATTERY
CONN
BKT
CONN
2N7002
2N7002
2N7002
2N7002
SMBUS Address[16h]
SMBUS Address[TBD]
2.2K
2.2K
CLK_SDATA
CLK_SCLK
DAI
SMBUS Address[35h]
3
+3.3V_M
17
16
CLK GEN
2N7002
2N7002
2N7002
2N7002
2N7002
2N7002
SMBUS Addr ess[a2h]
2.2K
2.2K
EXP_SMBCLK
EXP_SMBDATA
2.2K
2.2K
WLAN_SMBCLK
WLAN_SMBDATA
2.2K
2.2K
MINI_SMBCLK
MINI_SMBDATA
2
+3.3V_SUS
7
8
Express card
+3.3V_WLAN
30
32
WLAN
+3.3V_RUN
30
32
WWAN
Title
Size Document Number Rev
Date: Sheet
SMBUS Address[TBD]
SMBUS Address[TBD]
SMBUS Address[TBD]
Compal Electronics, Inc.
SMBUS TOPOLOGY
LA-4151P
1
557Friday, July 04, 2008
1.0
of
5
+3.3V_M
CKG_SMBDAT<21,34,46>
D D
CKG_SMBCLK<21,34,46>
FSC FSB FSA CPU
CLKSEL2 CLKSEL0CLKSEL1
000
*
00
1
0
11
C C
0
1
1
0
11
+3.3V_M
12
R51
@
10K_0402_5%~D
FSA
12
R55
@
10K_0402_5%~D
B B
+3.3V_RUN
+3.3V_M
10K_0402_5%~D
@
12
R43
R1112
10K_0402_5%~D
1 2
PCI_DOCKING
+3.3V_RUN
10K_0402_5%~D
R46
1 2
A A
PCI_SIO
10K_0402_5%~D
12
R54
PCI_ICH
*
*
*
0=UMA
6 1
Q1A
2N7002DW-T/R7_SOT363-6~D
+3.3V_M
1
0
00
1
0
TME
ITP_EN
2
5
Q1B
2N7002DW-T/R7_SOT363-6~D
3
4
SRC
MHz
MHz
100
266
100
133
100
200
100
166
100
333
100
100
100
400
PIN 32
0
overclocking enabled
1
overclocling disabled
PIN 37
0
Pin 5/6 as SRC_10
PCI
MHz
33.3
33.3
33.3
33.3
33.3
33.3
33.3
1 Pin 5/6 as CPU_ITP
FCTSEL1 PIN43 PIN44 PIN47 PIN48
0=UMA
1=DIS
DOT96T DOT96C 96/100M_T 96/100M_C
27M_out 27M SSout SRCT0 SRCC0
2.2K_0402_5%~D
12
R1
Place crystal within
500 mils of CK505
12
2.2K_0402_5%~D
R2
CLK_SDATA
CLK_SCLK
CPU_MCH_BSEL0<8,10>
CPU_MCH_BSEL1<8,10>
CPU_MCH_BSEL2<8,10>
CLK_PCI_TPM_CHA<30>
CLK_ICH_48M<24>
CLK_PCI_5028<33>
CLK_PCI_PCM<27>
CLK_PCI_TPM<32>
CLK_PCI_DOCK<31>
CLK_PCI_5035<34>
CLK_ICH_14M<24>
CLK_TCM_14M<30>
CLK_SIO_14M<33>
MCH_DREFCLK<10>
MCH_DREFCLK#<10>
CLK_PCI_ICH<22>
CLK_PWRGD<24>
1=Disc. GRFX down
5
4
4.7U_0603_6.3V4Z~D
1
@
2
C16
33P_0402_50V8J~D
C17
33P_0402_50V8J~D
MINI1CLK_REQ#
MINI2CLK_REQ#
CLK_3GPLLREQ#
SATA_CLKREQ#
EXPCLK_REQ#
4
1 2
R12 0_0603_5%~D
1 2
R14 0_0603_5%~D
+CK_VDD_MAIN+3.3V_M
+CK_VDD_REF
+CK_VDD_48
CLK_XTAL_IN
CLK_XTAL_OUT
FSC
PCI_SIOCLK_PCI_5028
PCI_TPMCLK_PCI_TPM
PCI_DOCKING
CLKREF
DOT96
DOT96#
PCI_ICHCLK_PCI_ICH
CLK_SCLK
CLK_SDATA
1 2
0.1U_0402_16V4Z~D
C1
0.047U_0402_16V7K~D
C13
1
2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
+3.3V_RUN
0.1U_0402_16V4Z~D
C10
L1 BK2125HS601-T 0805~D
12
12
12
12
33_0402_5%~D
22_0402_5%~D
22_0402_5%~D
22_0402_5%~D
12
1
2
0.047U_0402_16V4Z~D
1
C12
C11
2
12
12
CLK_ICH_48M FSA
CPU_MCH_BSEL0
CPU_MCH_BSEL1
CPU_MCH_BSEL2
CLK_PCI_PCM
CLK_PCI_DOCK
CLK_PCI_5035 PCI_EC
CLK_ICH_14M
CLK_TCM_14M
CLK_SIO_14M
MCH_DREFCLK
MCH_DREFCLK#
CLK_PWRGD
1 2
R4 10K_0402_5%~D
1 2
R5 10K_0402_5%~D
1 2
R6 10K_0402_5%~D
1 2
R7 10K_0402_5%~D
1 2
R356 10K_0402_5%~D
+CK_VDD_REF+CK_VDD_48
1
2
0.1U_0402_16V4Z~D
1
C9
2
X1
14.31818MHz_20P_1BX14318CC1A~D
12
R17 0_0402_5%~D
R19 33_0402_5%~D
R22 2.2K_0402_5%~D
R24 10K_0402_5%~D
R26 33_0402_5%~D
R30 22_0402_5%~D
R29 22_0402_5%~D
R986 22_0402_5%~D1@
R27 33_0402_5%~D
R32
R33
R1114
1@
R35
R37 33_0402_5%~D
R38 33_0402_5%~D
R41 33_0402_5%~D
3
+CK_VDD_MAIN
1
2
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
0.1U_0402_16V4Z~D
10U_0805_10V4Z~D
1
C3
C2
2
1 2
R10 2.2_0603_5%~D
U1
1
VDD_SRC
49
VDD_SRC
54
VDD_SRC
65
VDD_SRC
30
VDD_PCI
36
VDD_PCI
12
VDD_CPU
18
VDD_REF
40
VDD_48
20
XTAL_IN
19
XTAL_OUT
41
USB_48MHz/FSLA
45
FSL_B/TEST_MODE
23
REF_0/FSL_C/TEST_SEL
34
PCICLK4/FCT_SEL
33
PCICLK3
32
PCICLK2/TME
27
PCICLK1
22
REF_1
43
DOT_96/27M
44
DOT_96#/27M_SS
37
PCICLK_F0/ITP_EN
39
CKPWRGD/PD#
9
NC
16
SMBCLK
17
SMBDAT
4
VSS_SRC
15
VSS_CPU
21
VSS_REF
31
VSS_PCI
35
VSS_PCI
42
VSS_48
68
VSS_SRC
73
THRM_PAD
SLG8LP554VTR_QFN72_10X10~D
1
2
SLG8LP554VTR
0.1U_0402_16V4Z~D
C4
0.1U_0402_16V4Z~D
1
C5
2
+CK_VDD_A
PCI_STP#
CPU_STP#
CPU_ITP/SRC_10
CPU_ITP#/SRC_10#
CLKREQ_9#
CLKREQ_8#
CLKREQ_7#
CLKREQ_6#
CLKREQ_5#
CLKREQ_4#
CLKREQ_3#
CLKREQ_2#
SRC_1/SATA
SRC_1#/SATA#
CLKREQ_1#
LCD_CLK/SRC_0
LCD_CLK#/SRC_0#
1
2
VDD_A
VSS_A
CPU_1
CPU_1#
CPU_0
CPU_0#
SRC_9
SRC_9#
SRC_8
SRC_8#
SRC_7
SRC_7#
SRC_6
SRC_6#
SRC_5
SRC_5#
SRC_4
SRC_4#
SRC_3
SRC_3#
SRC_2
SRC_2#
0.1U_0402_16V4Z~D
C6
7
8
25
24
11
10
14
13
6
5
3
2
72
70
69
71
66
67
38
63
64
62
60
61
29
58
59
57
55
56
28
52
53
26
50
51
46
47
48
2
0.1U_0402_16V4Z~D
1
C7
2
4.7U_0603_6.3V4Z~D
1
C14
2
H_STP_PCI#
H_STP_CPU#
MCH_BCLK CLK_MCH_BCLK
MCH_BCLK#
CPU_BCLK
CPU_BCLK#
CPU_ITP
CPU_ITP#
PCIE_MINI1
PCIE_MINI1#
MINI1CLK_REQ#
PCIE_MINI2
PCIE_MINI2#
MINI2CLK_REQ#
PCIE_ICH
PCIE_ICH#
PCIE_EXP#
EXPCLK_REQ#
MCH_3GPLL
CLK_3GPLLREQ#_R
PCIE_SATA CLK_PCIE_SATA
PCIE_SATA#
SATA_CLKREQ#_R
DOT96_SSC DREF_SSCLK
1 2
R11 33_0402_5%~D
1 2
R13 33_0402_5%~D
1 2
R15 33_0402_5%~D
1 2
R16 33_0402_5%~D
1 2
R18 33_0402_5%~D@
1 2
R21 33_0402_5%~D@
1 2
R23 33_0402_5%~D
1 2
R25 33_0402_5%~D
1 2
R28 33_0402_5%~D
1 2
R31 33_0402_5%~D
1 2
R34 33_0402_5%~D
1 2
R36 33_0402_5%~D
1 2
R408 33_0402_5%~D
1 2
R415 33_0402_5%~D
1 2
R45 33_0402_5%~D
1 2
R47 33_0402_5%~D
1 2
R48 475_0402_1%~D
1 2
R49 33_0402_5%~D
1 2
R52 33_0402_5%~D
1 2
R53 475_0402_1%~D
1 2
R523 33_0402_5%~D
1 2
R670 33_0402_5%~D
2
0.047U_0402_16V4Z~D
1
C15
2
CLK_3GPLLREQ#
1
H_STP_PCI# <24>
H_STP_CPU# <24>
CLK_MCH_BCLK#
CLK_CPU_BCLK
CLK_CPU_BCLK#
CLK_CPU_ITP
CLK_CPU_ITP#
CLK_PCIE_MINI1
CLK_PCIE_MINI1#
CLK_PCIE_MINI2
CLK_PCIE_MINI2#
CLK_PCIE_ICH
CLK_PCIE_ICH#
CLK_PCIE_EXPPCIE_EXP
CLK_PCIE_EXP#
CLK_MCH_3GPLL
CLK_MCH_3GPLL#MCH_3GPLL#
CLK_PCIE_SATA#
SATA_CLKREQ#
DREF_SSCLK#DOT96_SSC#
CLK_MCH_BCLK <10>
CLK_MCH_BCLK# <10>
CLK_CPU_BCLK <7>
CLK_CPU_BCLK# <7>
CLK_CPU_ITP <7>
CLK_CPU_ITP# <7>
CLK_PCIE_MINI1 <21>
CLK_PCIE_MINI1# <21>
MINI1CLK_REQ# <21>
CLK_PCIE_MINI2 <21>
CLK_PCIE_MINI2# <21>
MINI2CLK_REQ# <21>
CLK_PCIE_ICH <24>
CLK_PCIE_ICH# <24>
CLK_PCIE_EXP <28>
CLK_PCIE_EXP# <28>
EXPCLK_REQ# <28>
CLK_MCH_3GPLL <10>
CLK_MCH_3GPLL# <10>
CLK_3GPLLREQ# <10>
CLK_PCIE_SATA <23>
CLK_PCIE_SATA# <23>
SATA_CLKREQ# <24>
DREF_SSCLK <10>
DREF_SSCLK# <10>
DELL CONFIDENTIAL/PROPRIETARY
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
Clock Generator
LA-4151P
657Friday, July 04, 2008
1
1.0
of
5
4
3
2
1
0_0402_5%~D
0_0402_5%~D
0_0402_5%~D
0_0402_5%~D
0_0402_5%~D
0_0402_5%~D
+1.05V_VCCP
ITP_DBRESET#
ITP_BPM_R#1
ITP_BPM_R#2
ITP_BPM_R#3
ITP_BPM_R#4
ITP_BPM_R#5
H_RESET_R#
ITP_TCK
CLK_CPU_ITP
CLK_CPU_ITP#
ITP_TCK
ITP_TRST#
ITP_TMS
ITP_TDI
+1.05V_VCCP
1
2
Place near JITP within 100mil
+3.3V_ALW_ICH
R60 150_0402_5%~D
Place close to JITP within 1ns = 5000 mil
+1.05V_VCCP
R977
@
Place close to CPU within 200 mil
+1.05V_VCCP
1 2
R65 150_0402_5%~D
1 2
R66 649_0402_1%~D
H_A#[3..35]<10>
D D
H_ADSTB#0<10>
H_REQ#0<10>
H_REQ#1<10>
H_REQ#2<10>
H_REQ#3<10>
H_REQ#4<10>
C C
H_ADSTB#1<10>
H_A20M#<23>
H_FERR#<23>
H_IGNNE#<23>
H_STPCLK#<23>
H_INTR<23>
H_NMI<23>
H_SMI#<23>
B B
H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_ADSTB#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35 H_THERMDA
H_ADSTB#1
H_A20M#
H_FERR#
H_IGNNE#
H_STPCLK#
H_INTR
H_NMI
H_SMI#
U62A
P2
A[3]#
V4
A[4]#
W1
ADDR GROUP 0
A[5]#
T4
A[6]#
AA1
A[7]#
AB4
A[8]#
T2
A[9]#
AC5
A[10]#
AD2
A[11]#
AD4
A[12]#
AA5
A[13]#
AE5
A[14]#
AB2
A[15]#
AC1
A[16]#
Y4
ADSTB[0]#
R1
REQ[0]#
R5
REQ[1]#
U1
REQ[2]#
P4
REQ[3]#
W5
REQ[4]#
AN1
A[17]#
AM4
AR5
AM2
AU5
AR1
AN5
AG5
AK4
AG1
AT4
AK2
AT2
AH2
AF4
AJ5
AH4
AP4
AJ1
AL1
AP2
F10
AL5
ADDR GROUP 1
A[18]#
A[19]#
A[20]#
A[21]#
A[22]#
A[23]#
A[24]#
A[25]#
A[26]#
A[27]#
A[28]#
A[29]#
A[30]#
A[31]#
A[32]#
THERMAL
A[33]#
A[34]#
A[35]#
ADSTB[1]#
C7
A20M#
ICH
D4
FERR#
THERMTRIP#
IGNNE#
F8
STPCLK#
C9
C5
E5
V2
Y2
J9
F4
H8
H CLK
LINT0
LINT1
SMI#
RSVD01
RSVD02
RSVD03
RSVD04
RSVD05
RSVD06
RSVD07
PENRYN SFF_UFCBGA956~D
ADS#
BNR#
BPRI#
DEFER#
DRDY#
DBSY#
BR0#
IERR#
INIT#
CONTROL
LOCK#
RESET#
RS[0]#
RS[1]#
RS[2]#
TRDY#
HIT#
HITM#
BPM[0]#
BPM[1]#
BPM[2]#
BPM[3]#
PRDY#
PREQ#
XDP/ITP SIGNALS
TRST#
DBR#
PROCHOT#
THERMDA
THERMDC
BCLK[0]
BCLK[1]
TCK
TDO
TMS
H_ADS#
M4
H_BNR#
J5
H_BPRI#
L5
H_DEFER#
N5
H_DRDY#
F38
H_DBSY#
J1
H_BR0#
M2
H_IERR#
B40
H_INIT#
D8
H_LOCK#
N1
H_RESET#
G5
H_RS#0H_REQ#0
K2
H_RS#1
H4
H_RS#2
K4
H_TRDY#
L1
H_HIT#
H2
H_HITM#
F2
ITP_BPM#0
AY8
ITP_BPM#1
BA7
ITP_BPM#2
BA5
ITP_BPM#3
AY2
ITP_BPM#4
AV10
ITP_BPM#5
AV2
ITP_TCK
AV4
ITP_TDI
AW7
TDI
RESERVED
AU1
AW5
AV8
J7
D38
BB34
BD34
B10
A35
C35
ITP_TDO
ITP_TMS
ITP_TRST#
ITP_DBRESET#
EC_CPU_PROCHOT#
H_THERMDC
H_THERMTRIP#
CLK_CPU_BCLK
CLK_CPU_BCLK#
+1.05V_VCCP
1 2
R61 56_0402_5%~D
H_INIT# <23>
H_LOCK# <10>
H_RESET# <10>
H_RS#0 <10>
H_RS#1 <10>
H_RS#2 <10>
H_TRDY# <10>
ITP_DBRESET# <24>
2
C18
@
100P_0402_50V8K~D
1
H_THERMTRIP# <18>
CLK_CPU_BCLK <6>
CLK_CPU_BCLK# <6>
H_ADS# <10>
H_BNR# <10>
H_BPRI# <10>
H_DEFER# <10>
H_DRDY# <10>
H_DBSY# <10>
H_BR0# <10>
H_HIT# <10>
H_HITM# <10>
H_THERMTRIP#
R997
ITP_BPM#0 ITP_BPM_R#0
R998
ITP_BPM#1
R999
12
R56 56_0402_5%~D
+1.05V_VCCP
12
R59
56_0402_5%~D
H_THERMDA <18>
H_THERMDC <18>
H_THERMDA, H_THERMDC routing together,
Trace width / Spacing = 10 / 10 mil
H_THERMTRIP# should connect
to ICH9 and G MCH without
T-ing(no stub )
+1.05V_VCCP
ITP_BPM#2
R1000
ITP_BPM#3
R1001
ITP_BPM#4
R1002
ITP_BPM#5
H_RESET#
R57 124_0402_1%~D
ITP_TDO
1 2
1 2
1 2
1 2
1 2
1 2
1 2
CLK_CPU_ITP<6>
CLK_CPU_ITP#<6>
1 2
R58 22.6_0402_1%~D
Layout Note: for ITP700Flex debug port with a XDP based Run Control Tools
ITP_BPM#[0..5], TCK, and TMS routings
must be a maximum of 1.5ns = 7500 mil
ITP_BPM#[0..5], and TCK to FBO routings
must be length matched to within 50ps = 250 mil
Place R67 close to JITP pin 5
TCK to FBO routing should refer to debug port design guide
H_RESET# should be routed from GMCH with split to ITP conn. Refer to DG page #56
Depop JITP, C19,C20,R62, R64, R67, R977, R65, R66
JITP1
28
VTT1
27
VTT0
26
VTAP
25
DBR#
24
DBA#
23
BPM0#
22
GND5
21
BPM1#
20
GND4
19
BPM2#
18
GND3
17
BPM3#
16
GND2
15
BPM4#
14
GND1
13
BPM5#
12
RESET#
11
FBO
10
GND0
9
BCLKP
8
BCLKN
7
TDO
6
NC2
5
TCK
4
NC1
3
TRST#
2
TMS
1
TDI
0.1U_0402_16V4Z~D
C19
1 2
29
GND6
GND7
MOLEX_52435-2891_28P~D@
30
0.1U_0402_16V4Z~D
1
C20
2
ITP_DBRESET#
ITP_BPM#5
51_0402_1%~D
ITP_TDI
ITP_TRST#
+1.05V_VCCP
1 2
1 2
1 2
H_RESET#
51_0402_1%~D
ITP_TDO
ITP_TMS
ITP_TCK
R1059
@
R62 56_0402_5%~D
R64 39_0402_5%~D
R67 27_0402_5%
Place close to JITP within 200ps = 1000 mil
when JIP connector is depopulated
Place close to CPU within 200ps = 1000 mil
A A
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
Penryn Processor(1/2)
LA-4151P
757Friday, July 04, 2008
1
1.0
of
5
4
3
2
1
+VCC_CORE +VCC_CORE
D D
C C
B B
1 2
Place CAP close to the TEST4 pin
A A
Make sure TEST4 routing is reference
to GND and away from other noisy signals.
1K_0402_5%~D
@
R72
+V_CPU_GTLREF
CPU_MCH_BSEL0<6,10>
CPU_MCH_BSEL1<6,10>
CPU_MCH_BSEL2<6,10>
1K_0402_5%~D
@
R73
1 2
0.1U_0402_16V4Z~D
@
1
C1101
2
H_D#[0..63]<10>
H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_DSTBN#0< 10>
H_DSTBP#0<10>
H_DINV#0<10>
H_DSTBN#1< 10>
H_DSTBP#1<10>
H_DINV#1<10>
T138PAD~D
H_DSTBN#0
H_DSTBP#0
H_DINV#0 H_DINV#2
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_DSTBN#1
H_DSTBP#1
H_DINV#1 H_DINV#3
TEST1
TEST2
TEST3
TEST4
TEST5
TEST6
CPU_MCH_BSEL0
CPU_MCH_BSEL1
CPU_MCH_BSEL2
TEST1
TEST2
For the purpose of testability, route these signals
through a ground referenced Z0 = 55ohm trace that
ends in a via that is near a GND via and is
accessible through an oscilloscope connection.
TEST4
U62B
F40
D[0]#
G43
D[1]#
E43
D[2]#
J43
D[3]#
H40
D[4]#
H44
D[5]#
G39
D[6]#
E41
D[7]#
L41
D[8]#
K44
D[9]#
N41
D[10]#
T40
D[11]#
M40
D[12]#
G41
D[13]#
M44
D[14]#
L43
D[15]#
K40
DSTBN[0]#
J41
DSTBP[0]#
P40
DINV[0]#
P44
D[16]#
V40
D[17]#
V44
D[18]#
AB44
D[19]#
R41
D[20]#
W41
D[21]#
N43
D[22]#
U41
D[23]#
AA41
D[24]#
AB40
D[25]#
AD40
D[26]#
AC41
D[27]#
AA43
D[28]#
Y40
D[29]#
Y44
D[30]#
T44
D[31]#
U43
DSTBN[1]#
W43
DSTBP[1]#
R43
DINV[1]#
AW43
GTLREF
E37
TEST1
D40
TEST2
C43
TEST3
AE41
TEST4
AY10
TEST5
AC43
TEST6
A37
BSEL[0]
C37
BSEL[1]
B38
BSEL[2]
PENRYN SFF_UFCBGA956~D
T2PAD~D
T3PAD~D
TEST3
TEST5
BCLK BSEL2 BSEL1 BSEL0FSB
133
166
667
200
800 00
1067 266
D[32]#
D[33]#
D[34]#
DATA GROUP 0
D[35]#
D[36]#
D[37]#
D[38]#
D[39]#
D[40]#
D[41]#
D[42]#
D[43]#
D[44]#
D[45]#
DATA GROUP 2DATA GROUP 3
D[46]#
D[47]#
DSTBN[2]#
DSTBP[2]#
DINV[2]#
D[48]#
D[49]#
D[50]#
D[51]#
DATA GROUP 1
D[52]#
D[53]#
D[54]#
D[55]#
D[56]#
D[57]#
D[58]#
D[59]#
D[60]#
D[61]#
D[62]#
D[63]#
DSTBN[3]#
DSTBP[3]#
DINV[3]#
COMP[0]
MISC
COMP[1]
COMP[2]
COMP[3]
DPRSTP#
DPSLP#
DPWR#
PWRGOOD
SLP#
PSI#
AR43
AH40
AF40
AJ43
AG41
AF44
AH44
AM44
AN43
AM40
AK40
AG43
AP40
AN41
AL41
AK44
AL43
AJ41
AV38
AT44
AV40
AU41
AW41
AR41
BA37
BB38
AY36
AT40
BC35
BC39
BA41
BB40
BA35
AU43
AY40
AY38
BC37
AE43
AD44
AE1
AF2
G7
B8
C41
E7
D10
BD10
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_DSTBN#2
H_DSTBP#2
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
H_DSTBN#3
H_DSTBP#3
COMP0
COMP1
COMP2
COMP3
H_DPRSTP#
H_DPSLP#
H_DPWR#
H_PWRGOOD
H_CPUSLP#
H_PSI#
H_D#32
AP44
0533 0 1
110
1
000
+V_CPU_GTLREF
H_DSTBN#2 <10>
H_DSTBP#2 <10>
H_DINV#2 <10>
H_DSTBN#3 <10>
H_DSTBP#3 <10>
H_DINV#3 <10>
H_DPRSTP# <10,23,45>
H_DPSLP# <23>
H_DPWR# <10>
H_PWRGOOD <23>
H_CPUSLP# <10>
H_PSI# <45>
+1.05V_VCCP
12
R77
1K_0402_1%~D
12
R78
2K_0402_1%~D
27.4_0402_1%~D
54.9_0402_1%~D
12
R68
Resistor placed within 0.5" of
CPU pin.Trace should be at least
25 mils away from any other
toggling signal. COMP0, COMP2
trace should be 27.4 ohm.
COMP1, COMP3 should be 55
ohm.
54.9_0402_1%~D
12
12
R69
12
R70
27.4_0402_1%~D
R71
U62C
F32
VCC[001]
G33
VCC[002]
H32
VCC[003]
J33
VCC[004]
K32
VCC[005]
L33
VCC[006]
M32
VCC[007]
N33
VCC[008]
P32
VCC[009]
R33
VCC[010]
T32
VCC[011]
U33
VCC[012]
V32
VCC[013]
W33
VCC[014]
Y32
VCC[015]
AA33
VCC[016]
AB32
VCC[017]
AC33
VCC[018]
AD32
VCC[019]
AE33
VCC[020]
AF32
VCC[021]
AG33
VCC[022]
AH32
VCC[023]
AJ33
VCC[024]
AK32
VCC[025]
AL33
VCC[026]
AM32
VCC[027]
AN33
VCC[028]
AP32
VCC[029]
AR33
VCC[030]
AT34
VCC[031]
AT32
VCC[032]
AU33
VCC[033]
AV32
VCC[034]
AY32
VCC[035]
BB32
VCC[036]
BD32
VCC[037]
B28
VCC[038]
B30
VCC[039]
B26
VCC[040]
D28
VCC[041]
D30
VCC[042]
F30
VCC[043]
F28
VCC[044]
H30
VCC[045]
H28
VCC[046]
D26
VCC[047]
F26
VCC[048]
H26
VCC[049]
K30
VCC[050]
K28
VCC[051]
M30
VCC[052]
M28
VCC[053]
K26
VCC[054]
M26
VCC[055]
P30
VCC[056]
P28
VCC[057]
T30
VCC[058]
T28
VCC[059]
V30
VCC[060]
V28
VCC[061]
P26
VCC[062]
T26
VCC[063]
V26
VCC[064]
Y30
VCC[065]
Y28
VCC[066]
AB30
VCC[067]
PENRYN SFF_UFCBGA956~D
AB28
VCC[068]
AD30
VCC[069]
AD28
VCC[070]
Y26
VCC[071]
AB26
VCC[072]
AD26
VCC[073]
AF30
VCC[074]
AF28
VCC[075]
AH30
VCC[076]
AH28
VCC[077]
AF26
VCC[078]
AH26
VCC[079]
AK30
VCC[080]
AK28
VCC[081]
AM30
VCC[082]
AM28
VCC[083]
AP30
VCC[084]
AP28
VCC[085]
AK26
VCC[086]
AM26
VCC[087]
AP26
VCC[088]
AT30
VCC[089]
AT28
VCC[090]
AV30
VCC[091]
AV28
VCC[092]
AY30
VCC[093]
AY28
VCC[094]
AT26
VCC[095]
AV26
VCC[096]
AY26
VCC[097]
BB30
VCC[098]
BB28
VCC[099]
BD30
VCC[100]
J11
VCCP_001
VCCP_002
VCCP_003
VCCP_004
VCCP_005
VCCP_006
VCCP_007
VCCP_008
VCCP_009
VCCP_010
VCCP_011
VCCP_012
VCCP_013
VCCP_014
VCCP_015
VCCP_016
VCCA[01]
VCCA[02]
VID[0]
VID[1]
VID[2]
VID[3]
VID[4]
VID[5]
VID[6]
VCCSENSE
VSSSENSE
E11
G11
J37
K38
L37
N37
P38
R37
U37
V38
W37
AA37
AB38
AC37
AE37
B34
D34
BD8
BC7
BB10
BB8
BC5
BB4
AY4
BD12
BC13
VID0
VID1
VID2
VID3
VID4
VID5
VID6
VCCSENSE
VSSSENSE
1
+
2
Length match within 25 mils, Z0=27.4 ohm
Place R75 and R76 near CPU
+VCC_CORE
1 2
R75 100_0402_1%~D
1 2
R76 100_0402_1%~D
Route VCCSENSE and VSSSENSE trace at
27.4 ohms, 7 mils spacing and R75&R76
keep to pad max 1 inch
+1.05V_VCCP
220U_D2_4VY_R15M~D
C21
CRB was 270uF
VID0 <45>
VID1 <45>
VID2 <45>
VID3 <45>
VID4 <45>
VID5 <45>
VID6 <45>
VCCSENSE <45>
VSSSENSE <45>
VCCSENSE
VSSSENSE
10U_0805_10V4Z~D
0.01U_0402_16V7K~D
+1.5V_RUN
1
1
C23
C22
2
2
VCCSENSE=18mils
1 2
R833 27.4_0402_1%~D@
Reserve for testing
only
DELL CONFIDENTIAL/PROPRIETARY
Layout close CPU PIN AD26
55 ohm, 0.5 inch (max)
5
4
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
Penryn Processor(2/2)
LA-4151P
857Friday, July 04, 2008
1
1.0
of
5
U62E
G25
VSS_164
G23
VSS_165
G21
VSS_166
J25
VSS_167
J23
VSS_168
J21
VSS_169
L25
VSS_170
L23
VSS_171
L21
VSS_172
N25
VSS_173
N23
D D
C C
B B
A A
VSS_174
N21
VSS_175
R25
VSS_176
R23
VSS_177
R21
VSS_178
U25
VSS_179
U23
VSS_180
U21
VSS_181
W25
VSS_182
W23
VSS_183
W21
VSS_184
AA25
VSS_185
AA23
VSS_186
AA21
VSS_187
AC25
VSS_188
AC23
VSS_189
AC21
VSS_190
AE25
VSS_191
AE23
VSS_192
AE21
VSS_193
AG25
VSS_194
AG23
VSS_195
AG21
VSS_196
AJ25
VSS_197
AJ23
VSS_198
AJ21
VSS_199
AL25
VSS_200
AL23
VSS_201
AL21
VSS_202
AN25
VSS_203
AN23
VSS_204
AN21
VSS_205
AR25
VSS_206
AR23
VSS_207
AR21
VSS_208
AU25
VSS_209
AU23
VSS_210
AU21
VSS_211
AW25
VSS_212
AW23
VSS_213
AW21
VSS_214
BA25
VSS_215
BA23
VSS_216
BA21
VSS_217
BC25
VSS_218
BC23
VSS_219
BC21
VSS_220
C17
VSS_221
C19
VSS_222
E19
VSS_223
E17
VSS_224
G19
VSS_225
G17
VSS_226
J19
VSS_227
J17
VSS_228
L19
VSS_229
L17
VSS_230
N19
VSS_231
N17
VSS_232
R19
VSS_233
R17
VSS_234
U19
VSS_235
U17
VSS_236
W19
VSS_237
W17
VSS_238
AA19
VSS_239
AA17
VSS_240
AC19
VSS_241
AC17
VSS_242
AE19
VSS_243
AE17
VSS_244
AG19
VSS_245
AG17
VSS_246
AJ19
VSS_247
AJ17
VSS_248
AL19
VSS_249
AL17
VSS_250
AN19
VSS_251
AN17
VSS_252
AR19
VSS_253
AR17
VSS_254
AU19
VSS_255
AU17
VSS_256
AW19
VSS_257
AW17
VSS_258
BA19
VSS_259
BA17
VSS_260
BC19
VSS_261
BC17
VSS_262
C11
VSS_263
C15
VSS_264
E15
VSS_265
G15
VSS_266
H10
VSS_267
M12
VSS_268
J15
VSS_269
L15
VSS_270
N15
VSS_271
M10
VSS_272
T12
VSS_273
R15
VSS_274
U15
VSS_275
W15
VSS_276
T10
VSS_277
Y12
VSS_278
AD12
VSS_279
PENRYN SFF_UFCBGA956~D
VSS_280
VSS_281
VSS_282
VSS_283
VSS_284
VSS_285
VSS_286
VSS_287
VSS_288
VSS_289
VSS_290
VSS_291
VSS_292
VSS_293
VSS_294
VSS_295
VSS_296
VSS_297
VSS_298
VSS_299
VSS_300
VSS_301
VSS_302
VSS_303
VSS_304
VSS_305
VSS_306
VSS_307
VSS_308
VSS_309
VSS_310
VSS_311
VSS_312
VSS_313
VSS_314
VSS_315
VSS_316
VSS_317
VSS_318
VSS_319
VSS_320
VSS_321
VSS_322
VSS_323
VSS_324
VSS_325
VSS_326
VSS_327
VSS_328
VSS_329
VSS_330
VSS_331
VSS_332
VSS_333
VSS_334
VSS_335
VSS_336
VSS_337
VSS_338
VSS_339
VSS_340
VSS_341
VSS_342
VSS_343
VSS_344
VSS_345
VSS_346
VSS_347
VSS_348
VSS_349
VSS_350
VSS_351
VSS_352
VSS_353
VSS_354
VSS_355
VSS_356
VSS_357
VSS_358
VSS_359
VSS_360
VSS_361
VSS_362
VSS_363
VSS_364
VSS_365
VSS_366
VSS_367
VSS_368
VSS_369
VSS_370
VSS_371
VSS_372
VSS_373
VSS_374
VSS_375
VSS_376
VSS_377
VSS_378
VSS_379
VSS_380
VSS_381
VSS_382
VSS_383
VSS_384
VSS_385
VSS_386
VSS_387
VSS_388
VSS_389
VSS_390
VSS_391
VSS_392
VSS_393
VSS_394
VSS_395
AA15
AC15
Y10
AD10
AH12
AE15
AG15
AJ15
AH10
AM12
AL15
AN15
AR15
AM10
AT12
AV12
AW13
AW11
AY12
AU15
AW15
AT10
BA13
BA11
BB12
BC11
BA15
BC15
B6
D6
E9
F6
G9
H6
K8
K6
M8
M6
P8
P6
T8
T6
V8
V6
U5
Y8
Y6
AB8
AB6
AD8
AD6
AF8
AF6
AH8
AH6
AK8
AK6
AM8
AM6
AP8
AP6
AT8
AT6
AU9
AV6
AU7
AW9
AY6
BA9
BB6
BC9
BD6
B4
C3
E3
G3
J3
L3
N3
R3
U3
W3
AA3
AC3
AE3
AG3
AJ3
AL3
AN3
AR3
AU3
AW3
BA3
BC3
D2
E1
G1
AW1
BA1
BB2
A41
A39
A29
A27
A31
A25
A23
A21
A19
A17
A11
A15
A7
A5
A9
BD4
5
+VCC_CORE
+1.05V_VCCP
U62F
BD28
VCC_101
BB26
VCC_102
BD26
VCC_103
B22
VCC_104
B24
VCC_105
D22
VCC_106
D24
VCC_107
F24
VCC_108
F22
VCC_109
H24
VCC_110
H22
VCC_111
K24
VCC_112
K22
VCC_113
M24
VCC_114
M22
VCC_115
P24
VCC_116
P22
VCC_117
T24
VCC_118
T22
VCC_119
V24
VCC_120
V22
VCC_121
Y24
VCC_122
Y22
VCC_123
AB24
VCC_124
AB22
VCC_125
AD24
VCC_126
AD22
VCC_127
AF24
VCC_128
AF22
VCC_129
AH24
VCC_130
AH22
VCC_131
AK24
VCC_132
AK22
VCC_133
AM24
VCC_134
AM22
VCC_135
AP24
VCC_136
AP22
VCC_137
AT24
VCC_138
AT22
VCC_139
AV24
VCC_140
AV22
VCC_141
AY24
VCC_142
AY22
VCC_143
BB24
VCC_144
BB22
VCC_145
BD24
VCC_146
BD22
VCC_147
B16
VCC_148
B18
VCC_149
B20
VCC_150
D16
VCC_151
D18
VCC_152
F18
VCC_153
F16
VCC_154
H18
VCC_155
H16
VCC_156
D20
VCC_157
F20
VCC_158
H20
VCC_159
K18
VCC_160
K16
VCC_161
M18
VCC_162
M16
VCC_163
K20
VCC_164
M20
VCC_165
P18
VCC_166
P16
VCC_167
T18
VCC_168
T16
VCC_169
V18
VCC_170
V16
VCC_171
P20
VCC_172
T20
VCC_173
V20
VCC_174
Y18
VCC_175
Y16
VCC_176
AB18
VCC_177
AB16
VCC_178
AD18
VCC_179
AD16
VCC_180
Y20
VCC_181
AB20
VCC_182
AD20
VCC_183
AF18
VCC_184
AF16
VCC_185
AH18
VCC_186
AH16
VCC_187
AF20
VCC_188
AH20
VCC_189
AK18
VCC_190
AK16
VCC_191
AM18
VCC_192
AM16
VCC_193
AP18
VCC_194
AP16
VCC_195
AK20
VCC_196
AM20
VCC_197
AP20
VCC_198
AT18
VCC_199
AT16
VCC_200
AV18
VCC_201
AV16
VCC_202
AY18
VCC_203
AY16
VCC_204
AT20
VCC_205
AV20
VCC_206
AY20
VCC_207
BB18
VCC_208
BB16
VCC_209
BD18
VCC_210
BD16
VCC_211
BB20
VCC_212
BD20
VCC_213
AM14
VCC_214
AP14
VCC_215
AT14
VCC_216
AV14
VCC_217
AY14
VCC_218
BB14
VCC_219
BD14
VCC_220
AF38
VCCP_017
AG37
VCCP_018
AJ37
VCCP_019
AK38
VCCP_020
PENRYN S FF _U FC BG A 956~D
VCCP_021
VCCP_022
VCCP_023
VCCP_024
VCCP_025
VCCP_026
VCCP_027
VCCP_028
VCCP_029
VCCP_030
VCCP_031
VCCP_032
VCCP_033
VCCP_034
VCCP_035
VCCP_036
VCCP_037
VCCP_038
VCCP_039
VCCP_040
VCCP_041
VCCP_042
VCCP_043
VCCP_044
VCCP_045
VCCP_046
VCCP_047
VCCP_048
VCCP_049
VCCP_050
VCCP_051
VCCP_052
VCCP_053
VCCP_054
VCCP_055
VCCP_056
VCCP_057
VCCP_058
VCCP_059
VCCP_060
VCCP_061
VCCP_062
VCCP_063
VCCP_064
VCCP_065
VCCP_066
VCCP_067
VCCP_068
VCCP_069
VCCP_070
VCCP_071
VCCP_072
VCCP_073
VCCP_074
VCCP_075
VCCP_076
VCCP_077
VCCP_078
VCCP_079
VCCP_080
VCCP_081
VCCP_082
VCCP_083
VCCP_084
VCCP_085
VCCP_086
VCCP_087
VCCP_088
VCCP_089
VCCP_090
VCCP_091
VCCP_092
VCCP_093
VCCP_094
VCCP_095
VCCP_096
VCCP_097
VCCP_098
VCCP_099
VCCP_100
VCCP_101
VCCP_102
VCCP_103
VCCP_104
VCCP_105
VCCP_106
VCCP_107
VCCP_108
VCCP_109
VCCP_110
VCCP_111
VCCP_112
VCCP_113
VCCP_114
VCCP_115
VCCP_116
VCCP_117
VCCP_118
VCCP_119
VCCP_120
VCCP_121
VCCP_122
VCCP_123
VCCP_124
VCCP_125
VCCP_126
VCCP_127
VCCP_128
VCCP_129
VCCP_130
VCCP_131
VCCP_132
VCCP_133
VCCP_134
VCCP_135
VCCP_136
VCCP_137
VCCP_138
VCCP_139
VCCP_140
VCCP_141
VCCP_142
VCCP_143
VCCP_144
VCCP_145
AL37
AN37
AP38
B32
C33
D32
E35
E33
F34
G35
F36
H36
J35
L35
N35
K36
R35
U35
P36
V36
W35
AA35
AC35
AB36
AE35
AG35
AJ35
AF36
AL35
AN35
AK36
AP36
B12
B14
C13
D12
D14
E13
F14
F12
G13
H14
H12
J13
K14
K12
L13
L11
M14
N13
N11
K10
P14
P12
R13
R11
T14
U13
U11
V14
V12
W13
W11
P10
V10
Y14
AA13
AA11
AB14
AB12
AC13
AC11
AD14
AB10
AE13
AE11
AF14
AF12
AG13
AG11
AH14
AJ13
AJ11
AF10
AK14
AK12
AL13
AL11
AN13
AN11
AP12
AR13
AR11
AK10
AP10
AU13
AU11
L9
L7
N9
N7
R9
R7
U9
U7
W9
W7
AA9
AA7
AC9
AC7
AE9
AE7
AG9
AG7
AJ9
AJ7
AL9
AL7
AN9
AN7
AR9
AR7
A33
A13
+1.05V_VCCP
4
U62D
B42
VSS[001]
F44
VSS[002]
D44
VSS[003]
D42
VSS[004]
F42
VSS[005]
H42
VSS[006]
K42
VSS[007]
M42
VSS[008]
P42
VSS[009]
T42
VSS[010]
V42
VSS[011]
Y42
VSS[012]
AB42
VSS[013]
AD42
VSS[014]
AF42
VSS[015]
AH42
VSS[016]
AK42
VSS[017]
AM42
VSS[018]
AP42
VSS[019]
AY44
VSS[020]
AV44
VSS[021]
AT42
VSS[022]
AV42
VSS[023]
AY42
VSS[024]
BA43
VSS[025]
BB42
VSS[026]
C39
VSS[027]
E39
VSS[028]
G37
VSS[029]
H38
VSS[030]
J39
VSS[031]
L39
VSS[032]
M38
VSS[033]
N39
VSS[034]
R39
VSS[035]
T38
VSS[036]
U39
VSS[037]
W39
VSS[038]
Y38
VSS[039]
AA39
VSS[040]
AC39
VSS[041]
AD38
VSS[042]
AE39
VSS[043]
AG39
VSS[044]
AH38
VSS[045]
AJ39
VSS[046]
AL39
VSS[047]
AM38
VSS[048]
AN39
VSS[049]
AR39
VSS[050]
AR37
VSS[051]
AT38
VSS[052]
AU39
VSS[053]
AU37
VSS[054]
AW39
VSS[055]
AW37
VSS[056]
BA39
VSS[057]
BC41
VSS[058]
BD40
VSS[059]
BD38
VSS[060]
B36
VSS[061]
H34
VSS[062]
D36
VSS[063]
K34
VSS[064]
M34
VSS[065]
M36
VSS[066]
P34
VSS[067]
T34
VSS[068]
V34
VSS[069]
T36
VSS[070]
Y34
VSS[071]
AB34
VSS[072]
AD34
VSS[073]
Y36
VSS[074]
AD36
VSS[075]
AF34
VSS[076]
AH34
VSS[077]
AH36
VSS[078]
AK34
VSS[079]
AM34
VSS[080]
AP34
VSS[081]
PENRYN SFF_UFCBGA956~D
4
VSS[082]
VSS[083]
VSS[084]
VSS[085]
VSS[086]
VSS[087]
VSS[088]
VSS[089]
VSS[090]
VSS[091]
VSS[092]
VSS[093]
VSS[094]
VSS[095]
VSS[096]
VSS[097]
VSS[098]
VSS[099]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
VSS[159]
VSS[160]
VSS[161]
VSS[162]
VSS[163]
AM36
AR35
AU35
AV34
AW35
AW33
AY34
AT36
AV36
BA33
BC33
BB36
BD36
C27
C29
C31
E29
E27
G29
G27
E31
G31
J29
J27
L29
L27
N29
N27
J31
L31
N31
R29
R27
U29
U27
R31
U31
W29
W27
W31
AA29
AA27
AC29
AC27
AA31
AC31
AE29
AE27
AG29
AG27
AJ29
AJ27
AE31
AG31
AJ31
AL29
AL27
AN29
AN27
AL31
AN31
AR29
AR27
AR31
AU29
AU27
AW29
AW27
AU31
AW31
BA29
BA27
BC29
BC27
BA31
BC31
C21
C23
C25
E25
E23
E21
+VCC_CORE
Place these inside
socket cavity on L8
(North side
Secondary)
+VCC_CORE
Place these inside
socket cavity on L8
(Sorth side
Secondary)
+VCC_CORE
Place these inside
socket cavity on L8
(North side
Primary)
Place these inside
socket cavity on L8
(Sorth side
Primary)
1
C24
10U_0805_4VAM~D
2
1
C34
10U_0805_4VAM~D
2
1
C44
10U_0805_4VAM~D
2
+VCC_CORE
1
@
C50
10U_0805_4VAM~D
2
South Side Secondary
+1.05V_VCCP
1
2
+VCC_CORE
2
1
+VCC_CORE
2
1
3
1
C25
10U_0805_4VAM~D
2
1
C35
10U_0805_4VAM~D
2
1
C45
10U_0805_4VAM~D
2
1
@
C51
10U_0805_4VAM~D
2
+VCC_CORE
C62
0.1U_0402_10V7K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
2
@
@
C1177
C1176
1
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
2
@
@
C1190
C1191
1
3
2
1
C26
10U_0805_4VAM~D
2
1
C36
10U_0805_4VAM~D
2
1
C46
10U_0805_4VAM~D
2
1
C52
10U_0805_4VAM~D
2
270U_D_2VM_R4.5M~D
270U_D_2VM_R4.5M~D
1
1
+
2
C57
C56
+
2
1
C63
0.1U_0402_10V7K~D
2
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
2
2
@
@
C1178
C1179
1
1
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
2
2
@
@
C1192
C1193
1
1
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
270U_D_2VM_R4.5M~D
1
+
2
1
2
1U_0402_6.3V6K~D
2
@
C1180
1
1U_0402_6.3V6K~D
2
@
C1194
1
1
C27
10U_0805_4VAM~D
2
1
C37
10U_0805_4VAM~D
2
1
@
C48
10U_0805_4VAM~D
2
1
@
C53
10U_0805_4VAM~D
2
C58
C64
0.1U_0402_10V7K~D
1U_0402_6.3V6K~D
2
@
C1181
1
1U_0402_6.3V6K~D
2
@
C1195
1
1U_0402_6.3V6K~D
2
@
1
1U_0402_6.3V6K~D
2
@
1
1
2
1
2
1
2
1
C65
0.1U_0402_10V7K~D
2
1U_0402_6.3V6K~D
2
C1182
1
1U_0402_6.3V6K~D
2
C1196
1
C28
10U_0805_4VAM~D
C38
10U_0805_4VAM~D
@
C49
10U_0805_4VAM~D
1
@
C54
10U_0805_4VAM~D
2
2
@
C1183
1
2
@
C1197
1
1
C29
10U_0805_4VAM~D
2
1
C39
10U_0805_4VAM~D
2
1
@
C55
10U_0805_4VAM~D
2
High Frequence Decoupling
10uF 0805 X6S -> 85 degree C
1
C66
0.1U_0402_10V7K~D
2
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
2
@
@
C1184
C1185
+VCC_CORE
1
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
2
@
@
C1199
C1198
1
2
1
C30
10U_0805_4VAM~D
2
1
C40
10U_0805_4VAM~D
2
1
C67
0.1U_0402_10V7K~D
2
1
C31
10U_0805_4VAM~D
2
1
C41
10U_0805_4VAM~D
2
Place these inside
socket cavity on L8
(North side
Secondary)
1
2
1
2
High Frequence CAP for ULV CPU
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
2
2
@
@
C1187
C1186
1
1
1U_0402_6.3V6K~D
2
2
@
@
C1188
C1189
1
1
DELL CONFIDENTIAL/PROPRIETARY
Title
Size Doc um e n t N u mb er Re v
Date: Sheet
Compal Electronics, Inc.
CPU Bypass
LA-4151P
1
C32
10U_0805_4VAM~D
C42
10U_0805_4VAM~D
1
1
C33
10U_0805_4VAM~D
2
1
C43
10U_0805_4VAM~D
2
957Friday, July 04, 2008
of
1.0
5
H_D#[0..63]<8>
D D
C C
1 2
B B
A A
R82 24.9_0402_1%~D
+1.05V_VCCP
+H_VREF
R94
2K_0402_1%~D
+1.05V_VCCP
H_SWNG
100_0402_1%~D
R95
H_RESET#<7>
H_CPUSLP#<8>
12
R90
1K_0402_1%~D
12
1
2
12
R91
221_0402_1%~D
12
1
2
H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
H_SWNG
+H_RCOMP
H_RESET#
H_CPUSLP#
+H_VREF
0.1U_0402_16V4Z~D
@
C73
+1.05V_VCCP
0.1U_0402_16V4Z~D
C74
MCH_TSATN#
5
U78A
J7
H_D#_0
H6
H_D#_1
L11
H_D#_2
J3
H_D#_3
H4
H_D#_4
G3
H_D#_5
K10
H_D#_6
K12
H_D#_7
L1
H_D#_8
M10
H_D#_9
M6
H_D#_10
N11
H_D#_11
L7
H_D#_12
K6
H_D#_13
M4
H_D#_14
K4
H_D#_15
P6
H_D#_16
W9
H_D#_17
V6
H_D#_18
V2
H_D#_19
P10
H_D#_20
W7
H_D#_21
N9
H_D#_22
P4
H_D#_23
U9
H_D#_24
V4
H_D#_25
U1
H_D#_26
W3
H_D#_27
V10
H_D#_28
U7
H_D#_29
W11
H_D#_30
U11
H_D#_31
AC11
H_D#_32
AC9
H_D#_33
Y4
H_D#_34
Y10
H_D#_35
AB6
H_D#_36
AA9
H_D#_37
AB10
H_D#_38
AA1
H_D#_39
AC3
H_D#_40
AC7
H_D#_41
AD12
H_D#_42
AB4
H_D#_43
Y6
H_D#_44
AD10
H_D#_45
AA11
H_D#_46
AB2
H_D#_47
AD4
H_D#_48
AE7
H_D#_49
AD2
H_D#_50
AD6
H_D#_51
AE3
H_D#_52
AG9
H_D#_53
AG7
H_D#_54
AE11
H_D#_55
AK6
H_D#_56
AF6
H_D#_57
AJ9
H_D#_58
AH6
H_D#_59
AF12
H_D#_60
AH4
H_D#_61
AJ7
H_D#_62
AE9
H_D#_63
B6
H_SWING
D4
H_RCOMP
J11
H_CPURST#
G9
H_CPUSLP#
L17
H_AVREF
K18
H_DVREF
CANTIGA GMCH SFF_ FCBG A1363~D
+3.3V_RUN
12
R101
54.9_0402_1%~D
1 2
2
B
R104
330_0402_5%~D
MMST3904-7-F_SOT323-3~D
Q4
+3.3V_RUN
HOST
1K_0402_5%~D
12
1K_0402_5%~D
12
R98
C
2
B
E
C
3 1
Q3
E
MMST3904-7-F_SOT323-3~D
3 1
R180 2.2K_0402_5%~D
R181 2.2K_0402_5%~D
R182 2.2K_0402_5%~D
R183 2.2K_0402_5%~D
Place close to U78.
F34,F32,B38,A37
R99
MCH_TSATN_EC <33>
12
12
12
12
H_A#_3
H_A#_4
H_A#_5
H_A#_6
H_A#_7
H_A#_8
H_A#_9
H_A#_10
H_A#_11
H_A#_12
H_A#_13
H_A#_14
H_A#_15
H_A#_16
H_A#_17
H_A#_18
H_A#_19
H_A#_20
H_A#_21
H_A#_22
H_A#_23
H_A#_24
H_A#_25
H_A#_26
H_A#_27
H_A#_28
H_A#_29
H_A#_30
H_A#_31
H_A#_32
H_A#_33
H_A#_34
H_A#_35
H_ADS#
H_ADSTB#_0
H_ADSTB#_1
H_BNR#
H_BPRI#
H_BREQ#
H_DEFER#
H_DBSY#
HPLL_CLK
HPLL_CLK#
H_DPWR#
H_DRDY#
H_HIT#
H_HITM#
H_LOCK#
H_TRDY#
H_DINV#_0
H_DINV#_1
H_DINV#_2
H_DINV#_3
H_DSTBN#_0
H_DSTBN#_1
H_DSTBN#_2
H_DSTBN#_3
H_DSTBP#_0
H_DSTBP#_1
H_DSTBP#_2
H_DSTBP#_3
H_REQ#_0
H_REQ#_1
H_REQ#_2
H_REQ#_3
H_REQ#_4
H_RS#_0
H_RS#_1
H_RS#_2
4
SDVO_CTRLCLK
SDVO_CTRLDATA
DDPC_CTRLCLK
DDPC_CTRLDATA
L15
B14
C15
D12
F14
G17
B12
J15
D16
C17
D14
K16
F16
B16
C21
D18
J19
J21
B18
D22
G19
J17
L21
L19
G21
D20
K22
F18
K20
F20
F22
B20
A19
F10
A15
C19
C9
B8
C11
E5
D6
AH10
AJ11
G11
H2
C7
F8
A11
D8
L9
N7
AA7
AG3
K2
N3
AA3
AF4
L3
M2
Y2
AF2
J13
L13
C13
G13
G15
F4
F2
G7
4
H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35
H_ADS#
H_ADSTB#0
H_ADSTB#1
H_BNR#
H_BPRI#
H_BR0#
H_DEFER#
H_DBSY#
CLK_MCH_BCLK
CLK_MCH_BCLK#
H_DPWR#
H_DRDY#
H_HIT#
H_HITM#
H_LOCK#
H_TRDY#
H_DINV#0
H_DINV#1
H_DINV#2
H_DINV#3
H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3
H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
H_RS#0
H_RS#1
H_RS#2
ICH_AZ_MCH_BITCLK<23>
ICH_AZ_MCH_RST#<23>
ICH_AZ_MCH_SDIN2<23>
ICH_AZ_MCH_SDOUT<23>
ICH_AZ_MCH_SYNC<23>
H_A#[3..35] <7>
+1.5V_MEM
R79 80.6_0402_1%~D
R80 80.6_0402_1%~D
+V_DDR_MCH_REF
H_ADS# <7>
H_ADSTB#0 <7>
H_ADSTB#1 <7>
H_BNR# <7>
H_BPRI# <7>
H_BR0# <7>
H_DEFER# <7>
H_DBSY# <7>
CLK_MCH_BCLK <6>
CLK_MCH_BCL K# <6>
H_DPWR# <8>
H_DRDY# <7>
H_HIT# <7>
H_HITM# <7>
H_LOCK# <7>
H_TRDY# <7>
H_DINV#0 <8>
H_DINV#1 <8>
H_DINV#2 <8>
H_DINV#3 <8>
H_DSTBN#0 <8>
H_DSTBN#1 <8>
H_DSTBN#2 <8>
H_DSTBN#3 <8>
H_DSTBP#0 <8>
H_DSTBP#1 <8>
H_DSTBP#2 <8>
H_DSTBP#3 <8>
H_REQ#0 <7>
H_REQ#1 <7>
H_REQ#2 <7>
H_REQ#3 <7>
H_REQ#4 <7>
H_RS#0 <7>
H_RS#1 <7>
H_RS#2 <7>
ICH_AZ_MCH_BITCLK
ICH_AZ_MCH_RST#
ICH_AZ_MCH_SDIN2
ICH_AZ_MCH_SDOUT
ICH_AZ_MCH_SYNC
+1.05V_M
510_0402_5%~D
R87
1
2
12
12
3
12
12
0.1U_0402_16V4Z~D
C68
1K_0402_1%~D
R83
1
2
M_CLK_DDR0<16>
M_CLK_DDR1<16>
M_CLK_DDR2<17>
M_CLK_DDR3<17>
M_CLK_DDR#0<16>
M_CLK_DDR#1<16>
M_CLK_DDR#2<17>
M_CLK_DDR#3<17>
DDR_CKE0_DIMMA<16>
DDR_CKE1_DIMMA<16>
DDR_CKE2_DIMMB<17>
DDR_CKE3_DIMMB<17>
DDR_CS0_DIMMA#<16>
DDR_CS1_DIMMA#<16>
DDR_CS2_DIMMB#<17>
DDR_CS3_DIMMB#<17>
SMRCOMP
SMRCOMP#
0.1U_0402_16V4Z~D
R81 499_0402_1%~D
1 2
1
2
0.1U_0402_16V4Z~D
C70
R685 33_0402_5%~D
C69
1 2
SM_DRAMRST#<16,17>
MCH_DREFCLK<6>
MCH_DREFCLK#<6>
DREF_SSCLK<6>
DREF_SSCLK#<6>
CLK_MCH_3GPLL<6>
CLK_MCH_3GPLL#<6>
DMI_MRX_ITX_N0<24>
DMI_MRX_ITX_N1<24>
DMI_MRX_ITX_N2<24>
DMI_MRX_ITX_N3<24>
DMI_MRX_ITX_P0<24>
DMI_MRX_ITX_P1<24>
DMI_MRX_ITX_P2<24>
DMI_MRX_ITX_P3<24>
DMI_MTX_IRX_N0<24>
DMI_MTX_IRX_N1<24>
DMI_MTX_IRX_N2<24>
DMI_MTX_IRX_N3<24>
DMI_MTX_IRX_P0<24>
DMI_MTX_IRX_P1<24>
DMI_MTX_IRX_P2<24>
DMI_MTX_IRX_P3<24>
GFX_VR_ON<47>
CL_CLK0<24>
CL_DATA0<24>
ICH_CL_PWROK<24,34>
CL_RST0#<24>
DDPC_CTRLCLK<21>
DDPC_CTRLDATA<21>
SDVO_CTRLCLK<21>
SDVO_CTRLDATA<21>
CLK_3GPLLREQ#<6>
MCH_ICH_SYNC#<24>
M_ODT0<16>
M_ODT1<16>
M_ODT2<17>
M_ODT3<17>
GFX_VID0<47>
GFX_VID1<47>
GFX_VID2<47>
GFX_VID3<47>
GFX_VID4<47>
M_CLK_DDR0
M_CLK_DDR1
M_CLK_DDR2
M_CLK_DDR3
M_CLK_DDR#0
M_CLK_DDR#1
M_CLK_DDR#2
M_CLK_DDR#3
DDR_CKE0_DIMMA
DDR_CKE1_DIMMA
DDR_CKE2_DIMMB
DDR_CKE3_DIMMB
DDR_CS0_DIMMA#
DDR_CS1_DIMMA#
DDR_CS2_DIMMB#
DDR_CS3_DIMMB#
M_ODT0
M_ODT1
M_ODT2
M_ODT3
SMRCOMP
SMRCOMP#
SMRCOMP_VOH
SMRCOMP_VOL
+V_DDR_MCH_REF
SM_PWROK
SM_DRAMRST#
MCH_DREFCLK
MCH_DREFCLK#
DREF_SSCLK
DREF_SSCLK#
CLK_MCH_3GPLL
CLK_MCH_3GPLL#
DMI_MRX_ITX_N0
DMI_MRX_ITX_N1
DMI_MRX_ITX_N2
DMI_MRX_ITX_N3
DMI_MRX_ITX_P0
DMI_MRX_ITX_P1
DMI_MRX_ITX_P2
DMI_MRX_ITX_P3
DMI_MTX_IRX_N0
DMI_MTX_IRX_N1
DMI_MTX_IRX_N2
DMI_MTX_IRX_N3
DMI_MTX_IRX_P0
DMI_MTX_IRX_P1
DMI_MTX_IRX_P2
DMI_MTX_IRX_P3
GFX_VID0
GFX_VID1
GFX_VID2
GFX_VID3
GFX_VID4
GFX_VR_ON
CL_CLK0
CL_DATA0
ICH_CL_PWROK
CL_RST0#
+CL_VREF
DDPC_CTRLCLK
DDPC_CTRLDATA
SDVO_CTRLCLK
SDVO_CTRLDATA
CLK_3GPLLREQ#
MCH_ICH_SYNC#
MCH_TSATN#
ICH_AZ_MCH_SDIN2_R
BB32
BA25
BA33
BA23
BA31
BC25
BC33
BB24
BC35
BE33
BE37
BC37
BK18
BK16
BE23
BC19
BJ17
BJ19
BC17
BE17
BL25
BK26
BK32
BL31
BC51
AY37
BH20
BA37
AG55
AL49
AH54
AL47
AG53
AK50
AH52
AL45
AG49
AJ49
AJ47
AG47
AF50
AH50
AJ45
AG45
AK52
AK54
AW40
AL53
AL55
B42
D42
B50
D50
R49
P50
G33
G37
F38
F36
G35
G39
F34
F32
B38
A37
C31
K42
D10
C29
B30
D28
A27
B28
SA_CK_0
SA_CK_1
SB_CK_0
SB_CK_1
SA_CK#_0
SA_CK#_1
SB_CK#_0
SB_CK#_1
SA_CKE_0
SA_CKE_1
SB_CKE_0
SB_CKE_1
SA_CS#_0
SA_CS#_1
SB_CS#_0
SB_CS#_1
SA_ODT_0
SA_ODT_1
SB_ODT_0
SB_ODT_1
SM_RCOMP
SM_RCOMP#
SM_RCOMP_VOH
SM_RCOMP_VOL
SM_VREF
SM_PWROK
SM_REXT
SM_DRAMRST#
DPLL_REF_CLK
DPLL_REF_CLK#
DPLL_REF_SSCLK
DPLL_REF_SSCLK#
PEG_CLK
PEG_CLK#
DMI_RXN_0
DMI_RXN_1
DMI_RXN_2
DMI_RXN_3
DMI_RXP_0
DMI_RXP_1
DMI_RXP_2
DMI_RXP_3
DMI_TXN_0
DMI_TXN_1
DMI_TXN_2
DMI_TXN_3
DMI_TXP_0
DMI_TXP_1
DMI_TXP_2
DMI_TXP_3
GFX_VID_0
GFX_VID_1
GFX_VID_2
GFX_VID_3
GFX_VID_4
GFX_VR_EN
CL_CLK
CL_DATA
CL_PWROK
CL_RST#
CL_VREF
DDPC_CTRLCLK
DDPC_CTRLDATA
SDVO_CTRLCLK
SDVO_CTRLDATA
CLKREQ#
ICH_SYNC#
TSATN#
HDA_BCLK
HDA_RST#
HDA_SDI
HDA_SDO
HDA_SYNC
HD support 1.5V
THERMTRIP_MCH#
PLTRST1#_R
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
1 2
R102 56_0402_5%~D
12
R100 100_0402_5%~D
+1.05V_VCCP
PLTRST1# <22,28>
2
DDR CLK/ CONTROL/COMPENSATION
CLK
CFGRSVD
DMI
PM
GRAPHICS VID
ME
NC
MISC
HDA
CANTIGA GMCH SFF_ FCBG A1363~D
RSVD1
RSVD2
RSVD3
RSVD4
RSVD5
RSVD6
RSVD7
RSVD8
RSVD9
RSVD14
RSVD15
RSVD17
RSVD20
RSVD22
RSVD23
RSVD24
RSVD25
ME_JTAG_TCK
ME_JTAG_TDI
ME_JTAG_TDO
ME_JTAG_TMS
CFG_0
CFG_1
CFG_2
CFG_3
CFG_4
CFG_5
CFG_6
CFG_7
CFG_8
CFG_9
CFG_10
CFG_11
CFG_12
CFG_13
CFG_14
CFG_15
CFG_16
CFG_17
CFG_18
CFG_19
CFG_20
PM_SYNC#
PM_DPRSTP#
PM_EXT_TS#_0
PM_EXT_TS#_1
PWROK
RSTIN#
THERMTRIP#
DPRSLPVR
NC_1
NC_2
NC_3
NC_4
NC_5
NC_6
NC_7
NC_8
NC_9
NC_10
NC_11
NC_12
NC_13
NC_14
NC_15
NC_16
NC_17
NC_18
NC_19
NC_20
NC_21
NC_22
U78B
J43
L43
J41
L41
AN11
AM10
AK10
AL11
F12
C27
D30
J9
AW42
BB20
BE19
BF20
BF18
AN45
AP44
AT44
AN47
SM_PWROK
K26
G23
G25
J25
L25
L27
F24
D24
D26
J23
B26
A23
C23
B24
B22
K24
C25
L23
L33
K32
K34
J35
F6
J39
L39
AY39
BB18
K28
K36
A7
A49
A52
A54
B54
D55
G55
BE55
BH55
BK55
BK54
BL54
BL52
BL49
BL7
BL4
BL2
BK2
BK1
BH1
BE1
G1
GFX_VR_ON
TP_MCH_RSVD1
TP_MCH_RSVD2
TP_MCH_RSVD3
TP_MCH_RSVD4
TP_MCH_RSVD5
TP_MCH_RSVD6
TP_MCH_RSVD7
TP_MCH_RSVD8
TP_MCH_RSVD9
TP_MCH_RSVD14
TP_MCH_RSVD15
TP_MCH_RSVD17
TP_MCH_RSVD20
TP_MCH_RSVD22
TP_MCH_RSVD23
TP_MCH_RSVD24
TP_MCH_RSVD25
ME_JTAG_TCK
ME_JTAG_TDI
ME_JTAG_TDO
ME_JTAG_TMS
R946 12K_0402_5%~D
1 2
12
R947
10K_0402_5%~D
CPU_MCH_BSEL0
CPU_MCH_BSEL1
CPU_MCH_BSEL2
CFG5
CFG6
CFG7
CFG9
CFG10
CFG12
CFG13
CFG16
CFG19
CFG20
PM_SYNC#
H_DPRSTP#
PM_EXTTS#0
ICH_PWRGD
PLTRST1#_R
THERMTRIP_MCH#
DPRSLPVR
+3.3V_RUN
12
R156
30K_0402_5%~D
12
R157
100K_0402_5%~D
R804 100_0402_5%~D@
R805 100_0402_5%~D@
R806 100_0402_5%~D@
R807 100_0402_5%~D@
4
1 2
1 2
1 2
1 2
+3.3V_ALW_ICH
O
DELL CONFIDENTIAL/PROPRIETARY
Title
Size Document Number Rev
2
Date: Sheet
Compal Electronics, Inc.
LA-4151P
1
PAD~D
T150
PAD~D
T151
PAD~D
T152
PAD~D
T153
PAD~D
T154
PAD~D
T155
PAD~D
T156
PAD~D
T157
PAD~D
T5
PAD~D
T158
PAD~D
T6
PAD~D
T8
T9 PAD~D
PAD~D
T10
PAD~D
T11
PAD~D
T12
PAD~D
T159
SIO_SLP_S4#<24,34>
C1108 0.1U_0402_16V4Z~D
1 2
5
DDR_ON
1
P
IN1
2
IN2
G
3
U80
74AHC1G08GW_SOT353-5~D
CPU_MCH_BSEL0 <6,8>
CPU_MCH_BSEL1 <6,8>
CPU_MCH_BSEL2 <6,8>
T14 PAD~D
T15 PAD~D
CFG5 <12>
CFG6 <12>
CFG7 <12>
T16 PAD~D
CFG9 <12>
CFG10 <12>
T18 PAD~D
CFG12 <12>
CFG13 <12>
T21 PAD~D
T22 PAD~D
CFG16 <12>
T23 PAD~D
T24 PAD~D
CFG19 <12>
CFG20 <12>
PM_SYNC# <24>
H_DPRSTP# <8,23,45>
PM_EXTTS#0 <16,17,18>
ICH_PWRG D <24,37>
THERMTRIP_MCH# <18>
DPRSLPVR <24,45>
PM_EXTTS#0
3.01K_0402_1%~D
1K_0402_1%~D
DDR_ON <34,36,44>
R1007 0_0402_5%~D@
1 2
1.5V_POK1
1.5V_POK1 <34,43>
12
R84 10K_0402_5%~D
+1.5V_MEM
12
R88
1K_0402_1%~D
SMRCOMP_VOH
1
12
2
R93
SMRCOMP_VOL
12
1
R97
2
Cantiga(1 of 6)
10 57Friday, Jul y 04, 2008
1
T123
T124
T125 PAD~D
T126 PAD~D
SIO_SLP_S4#
Notes refer
page 12
+3.3V_RUN
0.01U_0402_16V7K~D
1
C71
2
0.01U_0402_16V7K~D
1
C75
2
of
PAD~D
PAD~D
2.2U_0603_6.3V6K~D
C72
2.2U_0603_6.3V6K~D
C76
1.0
5
4
3
2
1
D D
C C
B B
DDR_A_BS1<16>
DDR_A_BS2<16>
DDR_A_RAS#<16>
DDR_A_CAS#<16>
DDR_A_WE#<16>
DDR_A_DM[0..7]<16>
DDR_A_DQS[0..7]<16>
DDR_A_DQS#[0..7]<16>
DDR_A_MA[0..14]<16>
DDR_A_BS0 DDR_B_BS1
DDR_A_BS1
DDR_A_BS2
DDR_A_RAS#
DDR_A_CAS#
DDR_A_WE#
DDR_A_DM0
DDR_A_DM1
DDR_A_DM2
DDR_A_DM3
DDR_A_DM4
DDR_A_DM5
DDR_A_DM6
DDR_A_DM7
DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7
DDR_A_DQS#0
DDR_A_DQS#1
DDR_A_DQS#2
DDR_A_DQS#3
DDR_A_DQS#4
DDR_A_DQS#5
DDR_A_DQS#6
DDR_A_DQS#7
DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA14
BC21
BJ21
BJ41
BH22
BK20
BL15
AT50
BB50
BB46
BE39
BB12
AV10
AR47
BA45
BE45
BC41
BC13
BB10
AR49
AW45
BC45
BA41
BA13
BA11
BC23
BF22
BE31
BC31
BH26
BJ35
BB34
BH32
BB26
BF32
BA21
BG25
BH34
BH18
BE25
BE7
AR9
BA7
AN7
BA9
AN9
SA_BS_0
SA_BS_1
SA_BS_2
SA_RAS#
SA_CAS#
SA_WE#
SA_DM_0
SA_DM_1
SA_DM_2
SA_DM_3
SA_DM_4
SA_DM_5
SA_DM_6
SA_DM_7
SA_DQS_0
SA_DQS_1
SA_DQS_2
SA_DQS_3
SA_DQS_4
SA_DQS_5
SA_DQS_6
SA_DQS_7
SA_DQS#_0
SA_DQS#_1
SA_DQS#_2
SA_DQS#_3
SA_DQS#_4
SA_DQS#_5
SA_DQS#_6
SA_DQS#_7
SA_MA_0
SA_MA_1
SA_MA_2
SA_MA_3
SA_MA_4
SA_MA_5
SA_MA_6
SA_MA_7
SA_MA_8
SA_MA_9
SA_MA_10
SA_MA_11
SA_MA_12
SA_MA_13
SA_MA_14
CANTIGA GMCH SFF_FCBGA1363~D
DDR SYSTEM MEMORY A
U78D
SA_DQ_0
SA_DQ_1
SA_DQ_2
SA_DQ_3
SA_DQ_4
SA_DQ_5
SA_DQ_6
SA_DQ_7
SA_DQ_8
SA_DQ_9
SA_DQ_10
SA_DQ_11
SA_DQ_12
SA_DQ_13
SA_DQ_14
SA_DQ_15
SA_DQ_16
SA_DQ_17
SA_DQ_18
SA_DQ_19
SA_DQ_20
SA_DQ_21
SA_DQ_22
SA_DQ_23
SA_DQ_24
SA_DQ_25
SA_DQ_26
SA_DQ_27
SA_DQ_28
SA_DQ_29
SA_DQ_30
SA_DQ_31
SA_DQ_32
SA_DQ_33
SA_DQ_34
SA_DQ_35
SA_DQ_36
SA_DQ_37
SA_DQ_38
SA_DQ_39
SA_DQ_40
SA_DQ_41
SA_DQ_42
SA_DQ_43
SA_DQ_44
SA_DQ_45
SA_DQ_46
SA_DQ_47
SA_DQ_48
SA_DQ_49
SA_DQ_50
SA_DQ_51
SA_DQ_52
SA_DQ_53
SA_DQ_54
SA_DQ_55
SA_DQ_56
SA_DQ_57
SA_DQ_58
SA_DQ_59
SA_DQ_60
SA_DQ_61
SA_DQ_62
SA_DQ_63
DDR_A_D0
AP46
DDR_A_D1
AU47
DDR_A_D2
AT46
DDR_A_D3
AU49
DDR_A_D4
AR45
DDR_A_D5
AN49
DDR_A_D6
AV50
DDR_A_D7
AP50
DDR_A_D8
AW47
DDR_A_D9
BD50
DDR_A_D10
AW49
DDR_A_D11
BA49
DDR_A_D12
BC49
DDR_A_D13
AV46
DDR_A_D14
BA47
DDR_A_D15
AY50
DDR_A_D16
BF46
DDR_A_D17
BC47
DDR_A_D18
BF50
DDR_A_D19
BF48
DDR_A_D20
BC43
DDR_A_D21
BE49
DDR_A_D22
BA43
DDR_A_D23
BE47
DDR_A_D24
BF42
DDR_A_D25
BC39
DDR_A_D26
BF44
DDR_A_D27
BF40
DDR_A_D28
BB40
DDR_A_D29
BE43
DDR_A_D30
BF38
DDR_A_D31
BE41
DDR_A_D32
BA15
DDR_A_D33
BE11
DDR_A_D34
BE15
DDR_A_D35
BF14
DDR_A_D36
BB14
DDR_A_D37
BC15
DDR_A_D38
BE13
DDR_A_D39
BF16
DDR_A_D40
BF10
DDR_A_D41
BC11
DDR_A_D42
BF8
DDR_A_D43
BG7
DDR_A_D44
BC7
DDR_A_D45
BC9
DDR_A_D46
BD6
DDR_A_D47
BF12
DDR_A_D48
AV6
DDR_A_D49
BB6
DDR_A_D50
AW7
DDR_A_D51
AY6
DDR_A_D52
AT10
DDR_A_D53
AW11
DDR_A_D54
AU11
DDR_A_D55
AW9
DDR_A_D56
AR11
DDR_A_D57
AT6
DDR_A_D58
AP6
DDR_A_D59
AL7
DDR_A_D60
AR7
DDR_A_D61
AT12
DDR_A_D62
AM6
DDR_A_D63
AU7
DDR_A_D[0..63] <16>
DDR_B_BS0<17>
DDR_B_BS1<17>DDR_A_BS0<16>
DDR_B_BS2<17>
DDR_B_RAS#<17>
DDR_B_CAS#<17>
DDR_B_WE#<17>
DDR_B_DM[0..7]<17>
DDR_B_DQS[0..7]<17>
DDR_B_DQS#[0..7]<17>
DDR_B_MA[0..14]<17>
DDR_B_BS0
DDR_B_BS2
DDR_B_RAS#
DDR_B_CAS#
DDR_B_WE#
DDR_B_DM0
DDR_B_DM1
DDR_B_DM2
DDR_B_DM3
DDR_B_DM4
DDR_B_DM5
DDR_B_DM6
DDR_B_DM7
DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4
DDR_B_DQS5
DDR_B_DQS6
DDR_B_DQS7
DDR_B_DQS#0
DDR_B_DQS#1
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS#4
DDR_B_DQS#5
DDR_B_DQS#6
DDR_B_DQS#7
DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13
DDR_B_MA14
BJ13
BK12
BK38
BE21
BH14
BK14
AP52
AY54
BJ49
BJ43
BH12
AR53
BA53
BH50
BK42
AM2
AT54
BB54
BJ51
BH42
AW3
BJ15
BJ33
BH24
BA17
BF36
BH36
BF34
BK34
BJ37
BH40
BH16
BK36
BH38
BJ11
BL37
BD2
AY2
AJ3
BH8
BB2
AV2
BK8
BC3
AN3
SB_BS_0
SB_BS_1
SB_BS_2
SB_RAS#
SB_CAS#
SB_WE#
SB_DM_0
SB_DM_1
SB_DM_2
SB_DM_3
SB_DM_4
SB_DM_5
SB_DM_6
SB_DM_7
SB_DQS_0
SB_DQS_1
SB_DQS_2
SB_DQS_3
SB_DQS_4
SB_DQS_5
SB_DQS_6
SB_DQS_7
SB_DQS#_0
SB_DQS#_1
SB_DQS#_2
SB_DQS#_3
SB_DQS#_4
SB_DQS#_5
SB_DQS#_6
SB_DQS#_7
SB_MA_0
SB_MA_1
SB_MA_2
SB_MA_3
SB_MA_4
SB_MA_5
SB_MA_6
SB_MA_7
SB_MA_8
SB_MA_9
SB_MA_10
SB_MA_11
SB_MA_12
SB_MA_13
SB_MA_14
CANTIGA GMCH SFF_FCBGA1363~D
DDR SYSTEM MEMORY B
SB_DQ_0
SB_DQ_1
SB_DQ_2
SB_DQ_3
SB_DQ_4
SB_DQ_5
SB_DQ_6
SB_DQ_7
SB_DQ_8
SB_DQ_9
SB_DQ_10
SB_DQ_11
SB_DQ_12
SB_DQ_13
SB_DQ_14
SB_DQ_15
SB_DQ_16
SB_DQ_17
SB_DQ_18
SB_DQ_19
SB_DQ_20
SB_DQ_21
SB_DQ_22
SB_DQ_23
SB_DQ_24
SB_DQ_25
SB_DQ_26
SB_DQ_27
SB_DQ_28
SB_DQ_29
SB_DQ_30
SB_DQ_31
SB_DQ_32
SB_DQ_33
SB_DQ_34
SB_DQ_35
SB_DQ_36
SB_DQ_37
SB_DQ_38
SB_DQ_39
SB_DQ_40
SB_DQ_41
SB_DQ_42
SB_DQ_43
SB_DQ_44
SB_DQ_45
SB_DQ_46
SB_DQ_47
SB_DQ_48
SB_DQ_49
SB_DQ_50
SB_DQ_51
SB_DQ_52
SB_DQ_53
SB_DQ_54
SB_DQ_55
SB_DQ_56
SB_DQ_57
SB_DQ_58
SB_DQ_59
SB_DQ_60
SB_DQ_61
SB_DQ_62
SB_DQ_63
U78E
DDR_B_D0
AP54
DDR_B_D1
AM52
DDR_B_D2
AR55
DDR_B_D3
AV54
DDR_B_D4
AM54
DDR_B_D5
AN53
DDR_B_D6
AT52
DDR_B_D7
AU53
DDR_B_D8
AW53
DDR_B_D9
AY52
DDR_B_D10
BB52
DDR_B_D11
BC53
DDR_B_D12
AV52
DDR_B_D13
AW55
DDR_B_D14
BD52
DDR_B_D15
BC55
DDR_B_D16
BF54
DDR_B_D17
BE51
DDR_B_D18
BH48
DDR_B_D19
BK48
DDR_B_D20
BE53
DDR_B_D21
BH52
DDR_B_D22
BK46
DDR_B_D23
BJ47
DDR_B_D24
BL45
DDR_B_D25
BJ45
DDR_B_D26
BL41
DDR_B_D27
BH44
DDR_B_D28
BH46
DDR_B_D29
BK44
DDR_B_D30
BK40
DDR_B_D31
BJ39
DDR_B_D32
BK10
DDR_B_D33
BH10
DDR_B_D34
BK6
DDR_B_D35
BH6
DDR_B_D36
BJ9
DDR_B_D37
BL11
DDR_B_D38
BG5
DDR_B_D39
BJ5
DDR_B_D40
BG3
DDR_B_D41
BF4
DDR_B_D42
BD4
DDR_B_D43
BA3
DDR_B_D44
BE5
DDR_B_D45
BF2
DDR_B_D46
BB4
DDR_B_D47
AY4
DDR_B_D48
BA1
DDR_B_D49
AP2
DDR_B_D50
AU1
DDR_B_D51
AT2
DDR_B_D52
AT4
DDR_B_D53
AV4
DDR_B_D54
AU3
DDR_B_D55
AR3
DDR_B_D56
AN1
DDR_B_D57
AP4
DDR_B_D58
AL3
DDR_B_D59
AJ1
DDR_B_D60
AK4
DDR_B_D61
AM4
DDR_B_D62
AH2
DDR_B_D63
AK2
DDR_B_D[0..63] <17>
A A
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
Cantiga(2 of 6)
LA-4151P
11 57Fr id ay, July 04, 2008
1
1.0
of
5
4
+VCC_PEG
3
2
1
Strap Pin Table
U78C
+3.3V_RUN
R1010 10K_0402_5%~D @
D D
Apply CIS
C C
B B
A A
1 2
1 2
R1011
@
1 2
The value is recommended per Intel
R688 2.4K_0402_1%~D
CRT_HSYNC<20>
Apply CIS
CRT_VSYNC<20>
BIA_PWM<19>
PANEL_BKEN_MCH<33>
10K_0402_5%~D
LDDC_CLK_MCH<39>
LDDC_DATA_MCH<39>
LCD_ACLK-_MCH<40>
LCD_ACLK+_MCH<40>
LCD_A0-_MCH<40>
LCD_A1-_MCH<40>
LCD_A2-_MCH<40>
LCD_A0+_MCH<40>
LCD_A1+_MCH<40>
LCD_A2+_MCH<40>
CRT_BLU<20>
CRT_GRN<20>
CRT_RED<20>
CRT_HSYNC CRT_HSYNC_R
CRT_VSYNC CRT_VSYNC_R
1 2
R679 150_0402_1%~D
1 2
R680 150_0402_1%~D
1 2
R681 150_0402_1%~D
1 2
R682 100K_0402_5%~D
5
BIA_PWM
PANEL_BKEN_MCH
L_CTRL_CLK
L_CTRL_DATA
LDDC_CLK_MCH
LDDC_DATA_MCH
ENVDD<19>
CRT_BLU
CRT_GRN
CRT_RED
ENVDD
ENVDD
L_IBG
LCD_ACLK-_MCH
LCD_ACLK+_MCH
LCD_A0-_MCH
LCD_A1-_MCH
LCD_A2-_MCH
LCD_A0+_MCH
LCD_A1+_MCH
LCD_A2+_MCH
R1107 75_0402_5%~D
R1106 75_0402_5%~D
12
12
CRT_BLU
CRT_GRN
CRT_RED
G_CLK_DDC2
1 2
R480 30_0402_1%~D
R672 976_0402_1%~D
R673 30_0402_1%~D
1 2
12
CRT_IREF
D38
L_BKLT_CTRL
C37
L_BKLT_EN
K38
L_CTRL_CLK
L37
L_CTRL_DATA
J37
L_DDC_CLK
L35
L_DDC_DATA
B36
L_VDD_EN
F50
LVDS_IBG
H46
LVDS_VBG
P44
LVDS_VREFH
K46
LVDS_VREFL
D46
LVDSA_CLK#
B46
LVDSA_CLK
D44
LVDSB_CLK#
B44
LVDSB_CLK
G45
LVDSA_DATA#_0
F46
LVDSA_DATA#_1
G41
LVDSA_DATA#_2
C45
LVDSA_DATA#_3
F44
LVDSA_DATA_0
G47
LVDSA_DATA_1
F40
LVDSA_DATA_2
A45
LVDSA_DATA_3
B40
LVDSB_DATA#_0
A41
LVDSB_DATA#_1
F42
LVDSB_DATA#_2
D48
LVDSB_DATA#_3
D40
LVDSB_DATA_0
C41
LVDSB_DATA_1
G43
LVDSB_DATA_2
B48
LVDSB_DATA_3
J27
TVA_DAC
E27
TVB_DAC
G27
R1105 75_0402_5%~D
12
TVC_DAC
F26
TVA_RTN
B34
TV_DCONSEL_0
D34
TV_DCONSEL_1
J29
CRT_BLUE
G29
CRT_GREEN
F30
CRT_RED
E29
CRT_IRTN
D36
CRT_DDC_CLK
C35
CRT_DDC_DATA
J33
CRT_HSYNC
D32
CRT_TVO_IREF
G31
CRT_VSYNC
CANTIGA GMCH SFF_FCBGA1363~D
2.2K_0402_5%~D
G_DAT_DDC2 DAT_DDC2
+3.3V_RUN
R675
12
12
+3.3V_RUN
4
LVDS
TV
R676
2.2K_0402_5%~D
PEG_COMPI
PEG_COMPO
PEG_RX#_0
PEG_RX#_1
PEG_RX#_2
PEG_RX#_3
PEG_RX#_4
PEG_RX#_5
PEG_RX#_6
PEG_RX#_7
PEG_RX#_8
PEG_RX#_9
PEG_RX#_10
PEG_RX#_11
PEG_RX#_12
PEG_RX#_13
PEG_RX#_14
PEG_RX#_15
PEG_RX_0
PEG_RX_1
PEG_RX_2
PEG_RX_3
PEG_RX_4
PEG_RX_5
PEG_RX_6
PEG_RX_7
PEG_RX_8
PEG_RX_9
PEG_RX_10
PEG_RX_11
PEG_RX_12
PEG_RX_13
PEG_RX_14
PEG_RX_15
PEG_TX#_0
PEG_TX#_1
PEG_TX#_2
PEG_TX#_3
PEG_TX#_4
PEG_TX#_5
PEG_TX#_6
PEG_TX#_7
PEG_TX#_8
PEG_TX#_9
PEG_TX#_10
PEG_TX#_11
PCI-EXPRESS GRAPHICS
PEG_TX#_12
PEG_TX#_13
PEG_TX#_14
PEG_TX#_15
PEG_TX_0
PEG_TX_1
PEG_TX_2
1 2
R860 0_0402_5%~D@
4
1 2
R861 0_0402_5%~D@
2
5
PEG_TX_3
PEG_TX_4
PEG_TX_5
PEG_TX_6
PEG_TX_7
PEG_TX_8
PEG_TX_9
PEG_TX_10
PEG_TX_11
PEG_TX_12
PEG_TX_13
PEG_TX_14
PEG_TX_15
61
Q123A
2N7002DW-T/R7_SOT363-6~D
Q123B
2N7002DW-T/R7_SOT363-6~D
3
VGA
CLK_DDC2G_ C LK_DDC2
U45
T44
D52
G49
K54
H50
M52
N49
P54
V46
Y50
V52
W49
AB54
AD46
AC55
AE49
AF54
E51
F48
J55
J49
M54
M50
P52
U47
AA49
V54
V50
AB52
AC47
AC53
AD50
AF52
L47
F52
P46
H54
L55
T46
R53
U49
T54
Y46
AB46
W53
Y54
AC49
AF46
AD54
J47
F54
N47
H52
L53
R47
R55
T50
T52
W47
AA47
W55
Y52
AB50
AE47
AD52
PEGCOMP
DPB_AUX#
DPC_DOCK_AUX#
DPB_AUX
DPB_HPD#
DPC_DOCK_AUX
DPC_DOCK_HPD#
DPB_LANE_N0
DPB_LANE_N1
DPB_LANE_N2
DPB_LANE_N3
DPC_LANE_N0
DPC_LANE_N1
DPC_LANE_N2
DPC_LANE_N3
DPB_LANE_P0
DPB_LANE_P1
DPB_LANE_P2
DPB_LANE_P3
DPC_LANE_P0
DPC_LANE_P1
DPC_LANE_P2
DPC_LANE_P3
R105
49.9_0402_1%~D
1 2
DPB_AUX# <21>
DPC_DOCK_AUX# <21>
DPB_AUX <21>
DPB_HPD# <21>
DPC_DOCK_AUX <21>
DPC_DOCK_HPD# <21>
C716 0.1U_0402_10V7K~D
12
C717 0.1U_0402_10V7K~D
12
C718 0.1U_0402_10V7K~D
12
C719 0.1U_0402_10V7K~D
12
C720 0.1U_0402_10V7K~D
12
C721 0.1U_0402_10V7K~D
12
C722 0.1U_0402_10V7K~D
12
C723 0.1U_0402_10V7K~D
12
C724 0.1U_0402_10V7K~D
12
C725 0.1U_0402_10V7K~D
12
C726 0.1U_0402_10V7K~D
12
C727 0.1U_0402_10V7K~D
12
C728 0.1U_0402_10V7K~D
12
C729 0.1U_0402_10V7K~D
12
C730 0.1U_0402_10V7K~D
12
C731 0.1U_0402_10V7K~D
12
CLK_DDC2 <20>
DAT_DDC2 <20>
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
CFG5
DMI X2 Select
iTPM Host
CFG6
Interface
Management
Engine Crypto
CFG7
Strap
PCI Express
CFG9
Graphic Lane
FSB Dynamic
CFG16
ODT
DMI Lane
CFG19
Reversal
SDVO/PCIE
CFG20
Concurrent
Operation
SDVO_CRTL_DATA
DDPC_CTRLDATA
DPB_LANE_N0_C <31>
DPB_LANE_N1_C <31>
DPB_LANE_N2_C <31>
DPB_LANE_N3_C <31>
DPC_LANE_N0_C <31>
DPC_LANE_N1_C <31>
DPC_LANE_N2_C <31>
DPC_LANE_N3_C <31>
CG13 CG12 configuration
00
1
0
0
1
11
CG10(PCIE Loopback enable)
DPB_LANE_P0_C <31>
DPB_LANE_P1_C <31>
DPB_LANE_P2_C <31>
DPB_LANE_P3_C <31>
DPC_LANE_P0_C <31>
DPC_LANE_P1_C <31>
DPC_LANE_P2_C <31>
DPC_LANE_P3_C <31>
3
2
Low = DMI x 2
High = DMI x 4 (Default)
Low = iTPM enable
High = iTPM disable(Defult)
Low = TLS cipher s u i t e wit h n o c onfidentiality
High = TLS cip h e r s u i t e with
confidentiality(Default)
Low = Reverse Lane
High = Normal O p e r a t i o n(Default)
Low=Dynamic O D T Disable
High=Dynamic ODT Enable(default)
Low=Normal (default)
High=Lane Reversed
Low=Only SDVO or PCIEx1 is
operational (default)
High=SDVO and P C I E x 1 a r e o p e rating
simultaneously via PEG port
Low=No SDVO Device Present
(default)
High=SDVO Dev i ce Present
Low=DisplayPort disabled (default)
High=DisplayPort device present
XOR/ALLZ/Clock Un-gating
Reserved
XOR Mode Enabled
All-Z Mode Enabled
Normal Operation(default)
Low= Enables
High= Disable ( d e fault)
CFG5
CFG5<10>
CFG6<10>
CFG7<10>
CFG9<10>
CFG16<10>
CFG10<10>
CFG12<10>
CFG13<10>
CFG19<10>
CFG20<10>
R106
@
CFG6
R107
@
CFG7G_DAT_DDC2
R108
@
CFG9
R109
@
CFG16
R110
@
CFG[5:16] have internal pullup
CFG10
R979
@
CFG12
R980
@
CFG13
R981
@
CFG19
R111
@
CFG20
R112
@
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
2.21K_0402_1%~D
2.21K_0402_1%~D
2.21K_0402_1%~D
2.21K_0402_1%~D
2.21K_0402_1%~D
2.21K_0402_1%~D
2.21K_0402_1%~D
2.21K_0402_1%~D
4.02K_0402_1%~D
4.02K_0402_1%~D
CFG[19:20] have internal pulldown
DELL CONFIDENTIAL/PROPRIETARY
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
Cantiga(3 of 6)
LA-4151P
+3.3V_RUN
1
12 57Fr id ay, July 04, 2008
1.0
of
5
CRB 270uF
220U_D2_4VY_R15M~D
1
+
2
D D
C114
4.7U_0603_6.3V6M~D
C115
4.7U_0603_6.3V6M~D
1
2
+1.5V_RUN_QDAC
C C
+1.05V_M
R118 0_1210_5%~D
+3.3V_RUN
0.1U_0402_16V4Z~D
C136
1
B B
A A
2
0.47U_0402_10V4Z~D
C142
1
2
+1.05V_VCCP
0.47U_0402_10V4Z~D
1
C109
2
C116
2.2U_0603_6.3V6K~D
1
1
+1.5V_RUN
0.1U_0402_16V4Z~D
2
2
+VCC_AXF
12
10U_0805_4VAM~D
@
1
C125
2
+1.5V_SM_CK
118.8mA Max.
+VCC_TX_LVDS
+VCC_PEG
+VCC_DMI
0.1U_0402_16V4Z~D
1
2
GMCH_VTTLF1
GMCH_VTTLF2
GMCH_VTTLF3
0.47U_0402_10V4Z~D
C143
1
1
2
2
C110
C137
0.47U_0402_10V4Z~D
1
2
1
2
C144
C998
1U_0603_10V4Z~D
C126
BK24
BL23
BJ23
BK22
AB44
AC43
AA43
AM44
AN43
AL43
R13
T12
R11
T10
R9
T8
R7
T6
R5
T4
R3
R1
K30
A31
N34
N32
M25
N24
M23
T41
C33
A33
Y44
K14
Y12
P2
VTT_1
VTT_2
VTT_3
VTT_4
VTT_5
VTT_6
VTT_7
VTT_8
VTT_9
VTT_10
VTT_11
T2
VTT_12
VTT_13
VCCA_TV_DAC
VCC_HDA
VCCD_QDAC
VCCD_TVDAC
VCC_AXF_1
VCC_AXF_2
VCC_AXF_3
VCC_SM_CK_1
VCC_SM_CK_2
VCC_SM_CK_3
VCC_SM_CK_4
VCC_TX_LVDS
VCC_HV_1
VCC_HV_2
VCC_PEG_1
VCC_PEG_2
VCC_PEG_3
VCC_PEG_4
VCC_DMI_1
VCC_DMI_2
VCC_DMI_3
VTTLF1
VTTLF2
VTTLF3
VTT
TVD TV/CRT
HDA
POWER
AXF
SM CK
HV
PEG
DMI
VTTLF
CANTIGA GMCH SFF_FCBGA1363~D
VCCA_CRT_DAC
VCCA_DAC_BG
VSSA_DAC_BG
CRTPLLA PEGA SM
VCCA_DPLLA
VCCA_DPLLB
VCCA_HPLL
VCCA_MPLL
VCCA_LVDS1
VCCA_LVDS2
VSSA_LVDS
A LVDS
VCCA_PEG_BG
VCCA_PEG_PLL
VCCA_SM_1
VCCA_SM_2
VCCA_SM_3
VCCA_SM_4
VCCA_SM_5
VCCA_SM_6
VCCA_SM_7
VCCA_SM_8
VCCA_SM_9
VCCA_SM_10
VCCA_SM_11
VCCA_SM_12
VCCA_SM_13
VCCA_SM_14
VCCA_SM_15
VCCA_SM_16
VCCA_SM_17
VCCA_SM_NCTF_1
VCCA_SM_NCTF_2
VCCA_SM_NCTF_3
VCCA_SM_NCTF_4
VCCA_SM_NCTF_5
VCCA_SM_NCTF_6
VCCA_SM_NCTF_7
VCCA_SM_NCTF_8
VCCA_SM_NCTF_9
VCCA_SM_NCTF_10
VCCA_SM_CK_4
VCCA_SM_CK_3
VCCA_SM_CK_2
VCCA_SM_CK_1
VCCA_SM_CK_NCTF_1
VCCA_SM_CK_NCTF_2
VCCA_SM_CK_NCTF_3
VCCA_SM_CK_NCTF_4
VCCA_SM_CK_NCTF_5
VCCA_SM_CK_NCTF_6
VCCA_SM_CK_NCTF_7
VCCA_SM_CK_NCTF_8
VCCD_HPLL
VCCD_PEG_PLL
VCCD_LVDS_1
VCCD_LVDS_2
LVDS
60.31mA Max.
U78H
J31
L31
M33
J45
L49
AF10
AE1
U43
U41
V44
AJ43
AG43
AW24
AU24
AW22
AU22
AU21
AW20
AU19
AW18
AU18
AW16
AU16
AT16
AR16
AU15
AT15
AR15
AW14
AT24
AR24
AT22
AR22
AT21
AR21
AT19
AR19
AT18
AR18
AU27
AU28
AU29
AU31
AT31
AR31
AT29
AR29
AT28
AR28
AT27
AR27
AH12
AE43
M46
L45
4
+3.3V_CRT_DAC
+1.05V_M_DPLLA
+1.05V_M_DPLLB
+1.05V_M_HPLL
+1.05V_M_MPLL
+VCC_TX_LVDS
+VCCA_PEG_BG
+1.05V_M_PEGPLL
+1.05V_M_SM_CK
1
2
+1.05V_M_PEGPLL
0.1U_0402_16V4Z~D
1
2
+1.8V_RUN
1U_0603_10V4Z~D
1
C743
2
1
2
0.1U_0402_16V4Z~D
C127
+1.05V_M
C141
1
2
13.2mA Max.
1
C117
0.1U_0402_16V4Z~D
2
+1.05V_M_A_SM
4.7U_0603_6.3V6M~D
1U_0603_10V4Z~D
1
C122
C121
2
2.2U_0603_6.3V6K~D
22U_0805_6.3V6M~D
1
1
C128
2
2
0.1U_0402_16V4Z~D
1
C140
2
+3.3V_CRT_DAC
0.01U_0402_25V7K~D
0.1U_0402_16V4Z~D
1
C734
C735
2
1 2
R778 0_0402_5%~D
1 2
R779 0_0402_5%~D@
R116
1 2
22U_0805_6.3V6M~D
22U_0805_6.3V6M~D
0_0805_5%~D
@
1
1
C123
C124
2
2
1 2
R119 0_1210_5%~D
@
C129
+1.05V_M
3
0.01U_0402_25V7K~D
0.1U_0402_16V4Z~D
10UH_LB2012T100MR_20%_0805~D
1
1
C732
C733
2
2
+VCC_TX_LVDS
+1.5V_RUN
+3.3V_RUN
+1.05V_M
100U_D2E_6.3VM_R15M~D
1
+
C120
2
+3.3V_RUN+3 .3 V_CRT_DAC
L43
1 2
Rating current 125mA
1000P_0402_50V7K~D
1
C736
2
+1.5V_MEM +1.5V_SM_CK
+VCC_PEG
220U_D2_4VY_R15M~D
4.7U_0603_6.3V6M~D
1
1
+
+1.05V_M
C118
10U_0805_4VAM~D
12
+1.05V_M_HPLL
24mA Max. 139.2mA Max.
+1.05V_M_DPLLA +1.05V_M_DPLLB
L7
LQM21FN1R0 N 0 0 _0805~D
Rdc=0.1~0.2,rated
current=220mA(MAX)
C147
10U_0805_4VAM~D
+1.5V_SM_CKG
12
C112
C111
2
2
BLM21PG221SN1D_0805~D
1 2
+1.05V_MPEG
R117
0.1U_0402_16V4Z~D
4.7U_0603_6.3V6M~D
1
1
C130
2
2
10UH_LB2012T100MR_20%_0805~D
220U_D2_4VY_R15M~D
0.1U_0402_16V4Z~D
1
1
+
C741
2
2
12
12
2
+VCC_DMI
1 2
R114
22U_0805_6.3V6M~D
0_1210_5%~D
1
2
L3
BLM18AG121SN1D_0603~D
C131
1 2
1 2
R115
@
C113
0_1210_5%~D
+1.05V_M_PEGPLL
1_0402_5%~D
+1.05V_M +1.05V_M
L4
12
+1.05V_M
L45
Rating current 125mA Rating current 125mA
C739
0.1U_0402_16V4Z~D
1_0603_5%~D
R121
1
C146
2
2 1
D1
@
RB751V_SOD323-2~D
Follow CRB to
VCC_HV(C33,A33)
+1.05V_M
+1.05V_VCCP
Follow ERB,CRB option
to select +1.05V_M or
+1.05V_VCCP
0.1U_0402_16V4Z~D
1
C119
2
+VCCPRUN
220U_D2_4VY_R15M~D
+1.5V_RUN_QDAC
1
2
64.8mA Max.64.8mA Max.
+1.8V_RUN_LVDS
+3.3V_RUN+1.05V_VCCP
1 2
R122
@
10_0603_5%~D
C145
@
0.1U_0402_16V4Z~D
0.01U_0402_25V7K~D
1
C738
C737
2
+1.05V_M_MPLL
0.1U_0402_16V4Z~D
1
2
0.1U_0402_16V4Z~D
1
2
@
PJP61
1 2
PAD-OPEN 1x1m
L44
BLM18PG181SN1_0603~D
C132
1 2
1
2
10UH_LB2012T100MR_20%_0805~D
1
+
C742
2
1
12
PJP1
PAD-OPEN1x1m
12
L6
@
1
LBC2518T91NM_1210~D
+
2
+1.5V_RUN
12
L5
LQH32CNR15M33L_1210~D
R120
0_0603_5%~D
C133
22U_0805_6.3VAM~D
220U_D2_4VY_R15M~D
12
+1.05V_MPLL
+1.05V_M
L46
1 2
C740
12
L47
HK1608R10J-T_0603~D
+VCC_PEG
+1.05V_M
+VCC_TX_LVDS+1.8V_RUN
22U_0805_6.3V6M~D
1000P_0402_50V7K~D
C745
1
1
C744
2
2
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
Cantiga(4 of 6)
LA-4151P
13 57Fr id ay, July 04, 2008
1
1.0
of
5
4
3
2
1
U78G
POWER
VCC SMVCC GFX
VCC GFX NCTF
VCC GFX
VCC_AXG_NCTF_1
VCC_AXG_NCTF_2
VCC_AXG_NCTF_3
VCC_AXG_NCTF_4
VCC_AXG_NCTF_5
VCC_AXG_NCTF_6
VCC_AXG_NCTF_7
VCC_AXG_NCTF_8
VCC_AXG_NCTF_9
VCC_AXG_NCTF_10
VCC_AXG_NCTF_11
VCC_AXG_NCTF_12
VCC_AXG_NCTF_13
VCC_AXG_NCTF_14
VCC_AXG_NCTF_15
VCC_AXG_NCTF_16
VCC_AXG_NCTF_17
VCC_AXG_NCTF_18
VCC_AXG_NCTF_19
VCC_AXG_NCTF_20
VCC_AXG_NCTF_21
VCC_AXG_NCTF_22
VCC_AXG_NCTF_23
VCC_AXG_NCTF_24
VCC_AXG_NCTF_25
VCC_AXG_NCTF_26
VCC_AXG_NCTF_27
VCC_AXG_NCTF_28
VCC_AXG_NCTF_29
VCC_AXG_NCTF_30
VCC_AXG_NCTF_31
VCC_AXG_NCTF_32
VCC_AXG_NCTF_33
VCC_AXG_NCTF_34
VCC_AXG_NCTF_35
VCC_AXG_NCTF_36
VCC_AXG_NCTF_37
VCC_AXG_NCTF_38
VCC_AXG_NCTF_39
VCC_AXG_NCTF_40
VCC_AXG_NCTF_41
VCC_AXG_NCTF_42
VCC_AXG_NCTF_43
VCC_AXG_NCTF_44
VCC_AXG_62
VCC_AXG_63
VCC_AXG_64
VCC_AXG_65
VCC_AXG_66
VCC_AXG_67
VCC_AXG_68
VCC_AXG_69
VCC_AXG_70
VCC_AXG_71
VCC_AXG_72
VCC_AXG_73
VCC_AXG_74
VCC_AXG_75
VCC_AXG_76
VCC_AXG_77
VCC_AXG_78
VCC_AXG_79
VCC_AXG_80
VCC_SM_LF1
VCC_SM_LF2
VCC_SM_LF3
VCC_SM_LF4
VCC_SM_LF5
VCC_SM_LF6
VCC_SM_LF7
VCC SM LF
+1.5V_MEM
330U_D2_2.5VY_R15M
C1103
1
2
C1105
1
2
0.1U_0402_10V7K~D
2
C149
1
+VCC_CM_BB36
+VCC_CM_BE35
0.1U_0402_10V7K~D
C1104
1
2
+VCC_CM_BF24
+VCC_CM_BL19
0.1U_0402_10V7K~D
C1106
1
2
1
C148
+
2
Layout Note:
Place on the edge
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
C1102
1
1
2
2
CRB use
VCC_AXG_SENSE<47>
VSS_AXG_SENSE<47>
+VCC_CM_BB16
+VCC_CM_BC29
C1110
D D
Layout Note:
Place close to GMCH
0.1U_0402_10V7K~D
C C
0.1U_0402_10V7K~D
B B
A A
22U_0805_6.3V6M~D
1
1
C150
2
2
+VCC_GFXCORE
+VCC_CM_BB36
+VCC_CM_BE35
22U_0805_6.3V6M~D
C151
+VCC_CM_BC29
+VCC_CM_BF24
+VCC_CM_BL19
+VCC_CM_BB16
BB36
BE35
AW34
AW32
BK30
BH30
BF30
BD30
BB30
AW30
BL29
BJ29
BG29
BE29
BC29
BA29
AY29
BK28
BH28
BF28
BD28
BB28
BL27
BJ27
BG27
BE27
BC27
BA27
AY27
AW26
BF24
BL19
BB16
W32
AG31
AE31
AD31
AC31
AA31
W31
AH29
AG29
AE29
AD29
AC29
AA29
W29
AH28
AG28
AE28
AA28
AH27
AG27
AE27
AD27
AC27
AA27
W27
AH25
AD25
AC25
W25
AJ24
AH24
AG24
AE24
AD24
AC24
AA24
W24
AM22
AL22
AJ22
AH22
AG22
AE22
AD22
AC22
AA22
AM21
AL21
AJ21
AH21
AD21
AC21
AA21
W21
AM16
AL16
AG13
AE13
Y31
Y29
Y27
Y24
Y21
VCC_SM_1
VCC_SM_2
VCC_SM_3
VCC_SM_4
VCC_SM_5
VCC_SM_6
VCC_SM_7
VCC_SM_8
VCC_SM_9
VCC_SM_10
VCC_SM_11
VCC_SM_12
VCC_SM_13
VCC_SM_14
VCC_SM_15
VCC_SM_16
VCC_SM_17
VCC_SM_18
VCC_SM_19
VCC_SM_20
VCC_SM_21
VCC_SM_22
VCC_SM_23
VCC_SM_24
VCC_SM_25
VCC_SM_26
VCC_SM_27
VCC_SM_28
VCC_SM_29
VCC_SM_30
VCC_SM_31
VCC_SM_32
VCC_SM_33
VCC_AXG_1
VCC_AXG_2
VCC_AXG_3
VCC_AXG_4
VCC_AXG_5
VCC_AXG_6
VCC_AXG_7
VCC_AXG_8
VCC_AXG_9
VCC_AXG_10
VCC_AXG_11
VCC_AXG_12
VCC_AXG_13
VCC_AXG_14
VCC_AXG_15
VCC_AXG_16
VCC_AXG_17
VCC_AXG_18
VCC_AXG_19
VCC_AXG_20
VCC_AXG_21
VCC_AXG_22
VCC_AXG_23
VCC_AXG_24
VCC_AXG_25
VCC_AXG_26
VCC_AXG_27
VCC_AXG_28
VCC_AXG_29
VCC_AXG_30
VCC_AXG_31
VCC_AXG_32
VCC_AXG_33
VCC_AXG_34
VCC_AXG_35
VCC_AXG_36
VCC_AXG_37
VCC_AXG_38
VCC_AXG_39
VCC_AXG_40
VCC_AXG_41
VCC_AXG_42
VCC_AXG_43
VCC_AXG_44
VCC_AXG_45
VCC_AXG_46
VCC_AXG_47
VCC_AXG_48
VCC_AXG_49
VCC_AXG_50
VCC_AXG_51
VCC_AXG_52
VCC_AXG_53
VCC_AXG_54
VCC_AXG_55
VCC_AXG_56
VCC_AXG_57
VCC_AXG_58
VCC_AXG_59
VCC_AXG_60
VCC_AXG_61
VCC_AXG_SENSE
VSS_AXG_SENSE
+VCC_GFXCORE
T32
U31
T31
R31
U29
T29
R29
U28
U27
T27
R27
U25
T25
R25
U24
U22
T22
R22
U21
T21
R21
AM19
AL19
AH19
AG19
AE19
AD19
AC19
W19
U19
AM18
AL18
AJ18
AH18
AG18
AE18
AD18
AC18
AA18
Y18
W18
U18
T18
R18
AJ16
AH16
AD16
AC16
AA16
U16
T16
R16
AM15
AL15
AJ15
AH15
AG15
AE15
AA15
Y15
W15
U15
T15
AU45
BF52
BB38
BA19
BE9
AU9
AL9
VCCSM_LF1
VCCSM_LF2
VCCSM_LF3
VCCSM_LF4
VCCSM_LF5
VCCSM_LF6
VCCSM_LF7
0.47U_0402_10V4Z~D
1U_0603_10V4Z~D
0.1U_0402_10V7K~D
C748
1
1
1
2
2
Layout Note: Inside GMCH
cavity for VCC_AXG.
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
C158
C157
1
1
2
2
1
C749
C750
2
2
0.22U_0402_10V4Z~D
0.22U_0402_10V4Z~D
C159
1
1
2
2
C160
U78F
+1.05V_M
AT41
VCC_1
AR41
VCC_2
AN41
VCC_3
AJ41
VCC_4
AH41
VCC_5
AD41
VCC_6
AC41
VCC_7
Y41
VCC_8
1 2
R123
0_0402_5%~D
W41
VCC_9
AT40
VCC_10
AM40
VCC_11
AL40
VCC_12
AJ40
VCC_13
AH40
VCC_14
AG40
VCC_15
AE40
VCC_16
AD40
VCC_17
AC40
VCC_18
AA40
VCC_19
Y40
VCC_20
AN35
VCC_21
AM35
VCC_22
AJ35
VCC_23
AH35
VCC_24
AD35
VCC_25
AC35
VCC_26
W35
VCC_27
AM34
VCC_28
AL34
VCC_29
AJ34
VCC_30
AH34
VCC_31
AG34
VCC_32
AE34
VCC_33
AD34
VCC_34
AC34
VCC_35
AA34
VCC_36
Y34
VCC_37
W34
VCC_38
AM32
VCC_39
AL32
VCC_40
AJ32
VCC_41
AH32
VCC_42
AE32
VCC_43
AD32
VCC_44
AA32
VCC_45
AM31
VCC_46
AL31
VCC_47
AJ31
VCC_48
AH31
VCC_49
AM29
VCC_50
AL29
VCC_51
AM28
VCC_52
AL28
VCC_53
AJ28
VCC_54
AM27
VCC_55
AL27
VCC_56
AM25
VCC_57
AL25
VCC_58
AJ25
VCC_59
AM24
VCC_60
N36
VCC_61
CANTIGA GMCH SFF_FCBGA1363~D
VCC CORE
VCC_NCTF_1
VCC_NCTF_2
VCC_NCTF_3
VCC_NCTF_4
VCC_NCTF_5
VCC_NCTF_6
VCC_NCTF_7
VCC_NCTF_8
POWER
VCC_NCTF_9
VCC_NCTF_10
VCC_NCTF_11
VCC_NCTF_12
VCC_NCTF_13
VCC_NCTF_14
VCC_NCTF_15
VCC_NCTF_16
VCC_NCTF_17
VCC_NCTF_18
VCC_NCTF_19
VCC_NCTF_20
VCC_NCTF_21
VCC_NCTF_22
VCC_NCTF_23
VCC_NCTF_24
VCC_NCTF_25
VCC_NCTF_26
VCC_NCTF_27
VCC_NCTF_28
VCC_NCTF_29
VCC_NCTF_30
VCC_NCTF_31
VCC_NCTF_32
VCC NCTF
VCC_NCTF_33
VCC_NCTF_34
VCC_NCTF_35
VCC_NCTF_36
VCC_NCTF_37
VCC_NCTF_38
AT38
AR38
AN38
AM38
AL38
AG38
AE38
AA38
Y38
W38
U38
T38
R38
AT37
AR37
AN37
AM37
AL37
AJ37
AH37
AG37
AE37
AD37
AC37
AA37
Y37
W37
U37
T37
R37
AT35
AR35
U35
AT34
AR34
U34
T34
R34
+1.05V_M
CRB 270uF
22U_0805_6.3VAM~D
10U_0805_10V4Z~D
0.1U_0402_10V7K~D
1
1
C753
C752
C751
2
2
1
2
1U_0402_6.3V4Z~D
0.47U_0402_10V4Z~D
C162
C161
1
2
1U_0402_6.3V4Z~D
C163
1
2
Layout Note:
Place close to GMCH
220U_D2_4VY_R15M~D
1
+
2
22U_0805_6.3VAM~D
C152
C153
1
2
0.22U_0402_10V4Z~D
C155
1
2
Layout Note:
Inside GMCH cavity.
0.22U_0402_10V4Z~D
1
C154
2
0.1U_0402_10V7K~D
C156
1
2
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
CANTIGA GMCH SFF_FCBGA1363~D
5
4
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
Cantiga(5 of 6)
LA-4151P
14 57Fr id ay, July 04, 2008
1
1.0
of
5
4
3
2
1
U78I
BA55
VSS_1
AU55
VSS_2
AN55
VSS_3
AJ55
VSS_4
AE55
VSS_5
AA55
VSS_6
U55
VSS_7
N55
D D
C C
B B
A A
VSS_8
BD54
VSS_9
BG53
VSS_10
AJ53
VSS_11
AE53
VSS_12
AA53
VSS_13
U53
VSS_14
N53
VSS_15
J53
VSS_16
G53
VSS_17
E53
VSS_18
K52
VSS_19
BG51
VSS_20
BA51
VSS_21
AW51
VSS_22
AU51
VSS_23
AR51
VSS_24
AN51
VSS_25
AL51
VSS_26
AJ51
VSS_27
AG51
VSS_28
AE51
VSS_29
AC51
VSS_30
AA51
VSS_31
W51
VSS_32
U51
VSS_33
R51
N51
L51
J51
G51
C51
BK50
AM50
K50
BG49
E49
C49
BD48
BB48
AY48
AV48
AT48
AP48
AM48
AK48
AH48
AF48
AD48
AB48
Y48
V48
T48
P48
M48
K48
H48
BL47
BG47
E47
C47
A47
BD46
AY46
AM46
AK46
AH46
BG45
AE45
AC45
AA45
W45
R45
N45
E45
BD44
BB44
AV44
AK44
AH44
AF44
AD44
K44
H44
BL43
BG43
AY43
AR43
W43
R43
M43
E43
CANTIGA GMCH SFF_FCBGA1363~D
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47
VSS_48
VSS_49
VSS_50
VSS_51
VSS_52
VSS_53
VSS_54
VSS_55
VSS_56
VSS_57
VSS_58
VSS_59
VSS_60
VSS_61
VSS_62
VSS_63
VSS_64
VSS_65
VSS_66
VSS_67
VSS_68
VSS_69
VSS_70
VSS_71
VSS_72
VSS_73
VSS_74
VSS_75
VSS_76
VSS_77
VSS_78
VSS_79
VSS_80
VSS_81
VSS_82
VSS_83
VSS_84
VSS_85
VSS_86
VSS_87
VSS_88
VSS_89
VSS_90
VSS_91
VSS_92
VSS_93
VSS_94
VSS_95
VSS_96
VSS_97
VSS_98
VSS_99
VSS
VSS_100
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105
VSS_106
VSS_107
VSS_108
VSS_109
VSS_110
VSS_111
VSS_112
VSS_113
VSS_114
VSS_115
VSS_116
VSS_117
VSS_118
VSS_119
VSS_120
VSS_121
VSS_122
VSS_123
VSS_124
VSS_125
VSS_126
VSS_127
VSS_128
VSS_129
VSS_130
VSS_131
VSS_132
VSS_133
VSS_134
VSS_135
VSS_136
VSS_137
VSS_138
VSS_139
VSS_140
VSS_141
VSS_142
VSS_143
VSS_144
VSS_145
VSS_146
VSS_147
VSS_148
VSS_149
VSS_150
VSS_151
VSS_152
VSS_153
VSS_154
VSS_155
VSS_156
VSS_157
VSS_158
VSS_159
VSS_160
VSS_161
VSS_162
VSS_163
VSS_164
VSS_165
VSS_166
VSS_167
VSS_168
VSS_169
VSS_170
VSS_171
VSS_172
VSS_173
VSS_174
VSS_175
VSS_176
VSS_177
VSS_178
VSS_179
VSS_180
VSS_181
VSS_182
VSS_183
VSS_184
VSS_185
VSS_186
VSS_187
VSS_188
VSS_189
VSS_190
VSS_191
VSS_192
VSS_193
VSS_194
VSS_195
VSS_196
VSS_197
VSS_198
C43
A43
BD42
H42
BG41
AY41
AU41
AM41
AL41
AG41
AE41
AA41
R41
M41
E41
BD40
AU40
AR40
AN40
W40
U40
T40
R40
K40
H40
BL39
BG39
BA39
E39
C39
A39
BD38
AU38
H38
BG37
AU37
M37
E37
BD36
AW36
H36
BL35
BG35
AY35
AU35
AL35
AG35
AE35
AA35
Y35
M35
E35
A35
BD34
AU34
AN34
H34
BL33
BG33
AY33
E33
BD32
AU32
AN32
AG32
AC32
Y32
H32
B32
BJ31
BG31
AY31
AN31
M31
E31
N30
H30
AN29
AJ29
M29
A29
AW28
AN28
AD28
AC28
Y28
W28
H28
F28
AN27
AJ27
M27
BF26
BD26
N26
H26
BJ25
AY25
AU25
U78J
AN25
VSS_199
AG25
VSS_200
AE25
VSS_201
AA25
VSS_202
Y25
VSS_203
E25
VSS_204
A25
VSS_205
BD24
VSS_206
AN24
VSS_207
AL24
VSS_208
H24
VSS_209
BG23
VSS_210
AY23
VSS_211
E23
VSS_212
BD22
VSS_213
BB22
VSS_214
AN22
VSS_215
Y22
VSS_216
W22
VSS_217
H22
VSS_218
BL21
VSS_219
BG21
VSS_220
AY21
VSS_221
AN21
VSS_222
AG21
VSS_223
AE21
VSS_224
M21
VSS_225
E21
VSS_226
A21
VSS_227
BD20
VSS_228
H20
VSS_229
BG19
AY19
M19
BD18
N18
H18
BL17
BG17
AY17
M17
BD16
AN16
AG16
AE16
W16
N16
H16
BG15
AY15
AN15
AD15
AC15
R15
M15
BD14
H14
BL13
BG13
AY13
AU13
AR13
AJ13
AC13
AA13
W13
U13
M13
BD12
AV12
AP12
AM12
AK12
AB12
H12
BG11
AG11
BD10
AY10
AP10
H10
BG9
BD8
BB8
AY8
AV8
AT8
AP8
E19
E17
A17
Y16
E15
E13
A13
V12
P12
E11
BL9
E9
A9
VSS
VSS_230
VSS_231
VSS_232
VSS_233
VSS_234
VSS_235
VSS_236
VSS_237
VSS_238
VSS_239
VSS_240
VSS_241
VSS_242
VSS_243
VSS_244
VSS_245
VSS_246
VSS_247
VSS_248
VSS_249
VSS_250
VSS_251
VSS_252
VSS_253
VSS_254
VSS_255
VSS_256
VSS_257
VSS_258
VSS_259
VSS_260
VSS_261
VSS_262
VSS_263
VSS_264
VSS_265
VSS_266
VSS_267
VSS_268
VSS_269
VSS_270
VSS_271
VSS_272
VSS_273
VSS_274
VSS_275
VSS_276
VSS_277
VSS_278
VSS_279
VSS_280
VSS_281
VSS_282
VSS_283
VSS_284
VSS_285
VSS_286
VSS_287
VSS_288
VSS_289
VSS_290
VSS_291
VSS_292
VSS_293
VSS_294
VSS_295
VSS_296
VSS_297
VSS_298
VSS_299
CANTIGA GMCH SFF_FCBGA1363~D
VSS_300
VSS_301
VSS_302
VSS_303
VSS_304
VSS_305
VSS_306
VSS_307
VSS_308
VSS_309
VSS_310
VSS_311
VSS_312
VSS_313
VSS_314
VSS_315
VSS_316
VSS_317
VSS_318
VSS_319
VSS_320
VSS_321
VSS_322
VSS_323
VSS_324
VSS_325
VSS_326
VSS_327
VSS_328
VSS_329
VSS_330
VSS_331
VSS_332
VSS_333
VSS_334
VSS_335
VSS_336
VSS_337
VSS_338
VSS_339
VSS_340
VSS_341
VSS_342
VSS_343
VSS_344
VSS_345
VSS_346
VSS_347
VSS_348
VSS_349
VSS_350
VSS_351
VSS_352
VSS_353
VSS_354
VSS_355
VSS_356
VSS_357
VSS_358
VSS_359
VSS_360
VSS_361
VSS_362
VSS_NCTF_1
VSS_NCTF_2
VSS_NCTF_3
VSS_NCTF_4
VSS_NCTF_5
VSS_NCTF_6
VSS_NCTF_7
VSS_NCTF_8
VSS_NCTF_9
VSS_NCTF_10
VSS_NCTF_11
VSS_NCTF_12
VSS_NCTF_13
VSS NCTF
VSS_NCTF_14
VSS_NCTF_15
VSS_NCTF_16
VSS_NCTF_17
VSS_NCTF_18
VSS_NCTF_19
VSS_NCTF_20
VSS_NCTF_21
VSS_NCTF_22
VSS_NCTF_23
VSS_SCB_1
VSS_SCB_2
VSS_SCB_3
VSS_SCB_4
VSS_SCB_5
VSS_SCB_6
VSS_SCB_7
VSS SCB
AM8
AK8
AH8
AF8
AD8
AB8
Y8
V8
P8
M8
K8
H8
BJ7
E7
BF6
BC5
BA5
AW5
AU5
AR5
AN5
AL5
AJ5
AG5
AE5
AC5
AA5
W5
U5
N5
L5
J5
G5
C5
BH4
BE3
U3
E3
BC1
AW1
AR1
AL1
AG1
AC1
W1
N1
J1
AU43
BB42
AW38
BA35
L29
N28
N22
N20
N14
AL13
B10
AN13
N42
N40
N38
M39
AJ38
AH38
AD38
AC38
T35
R35
AT32
AR32
U32
R32
T28
R28
AT25
AR25
T24
R24
AN19
AJ19
AA19
Y19
T19
R19
AN18
BL55
BL1
A55
D1
B55
B2
A4
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
Cantiga(6 of 6)
LA-4151P
15 57Fr id ay, July 04, 2008
1
1.0
of
5
DDR_A_DQS#[0..7]<11>
DDR_A_D[0..63]<11>
DDR_A_DM[0..7]<11>
DDR_A_DQS[0..7]<11>
DDR_A_MA[0..14]<11>
D D
Layout Note:
Place near JDIMMA
+1.5V_MEM
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
C171
C172
1
1
2
2
+1.5V_MEM
C C
+0.75V_DDR_VTT
B B
A A
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
C1114
C1113
1
1
2
2
Layout Note:
Place near JDIMMA.203,204
1U_0603_10V4Z~D
1U_0603_10V4Z~D
1
1
C1120
2
2
0.1U_0402_16V4Z~D
C173
C174
1
1
2
2
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
C1116
C1115
1
2
1
C1121
2
C1117
1
1
2
2
1U_0603_10V4Z~D
1U_0603_10V4Z~D
1
C1123
C1122
2
1
2
10U_0603_6.3V6M~D
C1118
1
2
330U_D2_2.5VY_R15M
1
C1119
+
2
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
1
C1154
C1153
2
4
1
C1155
2
+V_DDR_MCH_REF +1.5V_MEM+1.5V_MEM
2.2U_0603_6.3V6K~D
0.1U_0402_16V4Z~D
1
1
+3.3V_M
C164
2
DDR_CKE0_DIMMA<10>
DDR_CS1_DIMMA#<10>
0.1U_0402_16V4Z~D
C165
2
DDR_A_BS2<11>
M_CLK_DDR0<10>
DDR_A_BS0<11>
DDR_A_WE#<11>
DDR_A_CAS#<11>
2.2U_0603_6.3V6K~D
C190
C189
1
1
2
2
DDR_A_D0
DDR_A_D1
DDR_A_DM0
DDR_A_D2
DDR_A_D3
DDR_A_D8
DDR_A_D13
DDR_A_DQS#1
DDR_A_DQS1
DDR_A_D10
DDR_A_D11
DDR_A_D20 DDR_A_D22
DDR_A_D17
DDR_A_DQS#2
DDR_A_DQS2
DDR_A_D18
DDR_A_D19
DDR_A_D25
DDR_A_D30
DDR_A_DM3
DDR_A_D26
DDR_A_D27
DDR_CKE0_DIMMA DDR_CKE1_DIMMA
DDR_A_BS2
DDR_A_MA3
M_CLK_DDR0
M_CLK_DDR#0
DDR_A_MA10
DDR_A_BS0
DDR_A_WE#
DDR_A_CAS#
DDR_A_MA13
DDR_CS1_DIMMA#
DDR_A_D32
DDR_A_D39
DDR_A_DQS#4
DDR_A_DQS4
DDR_A_D34
DDR_A_D35
DDR_A_D40
DDR_A_D41
DDR_A_DM5
DDR_A_D42
DDR_A_D43
DDR_A_D54
DDR_A_D49
DDR_A_DQS#6
DDR_A_DQS6
DDR_A_D50
DDR_A_D51
DDR_A_D56
DDR_A_D57
DDR_A_DM7
DDR_A_D58
DDR_A_D59
1 2
R128 10K_0402_5%~D
1 2
R129 10K_0402_5%~D
+0.75V_DDR_VTT
3
JDIMMA
1
VREF_DQ
3
VSS
5
DQ0
7
DQ1
9
VSS
11
DM0
13
VSS
15
DQ2
17
DQ3
19
VSS
21
DQ8
23
DQ9
25
VSS
27
DQS1#
29
DQS1
31
VSS
33
DQ10
35
DQ11
37
VSS
39
DQ16
41
DQ17
43
VSS
45
DQS2#
47
DQS2
49
VSS
51
DQ18
53
DQ19
55
VSS
57
DQ24
59
DQ25
61
VSS
63
DM3
65
VSS
67
DQ26
69
DQ27
71
VSS
73
CKE0
75
VDD
77
NC
79
BA2
81
VDD
83
A12/BC#
85
A9
87
VDD
89
A8
91
A5
93
VDD
95
A3
97
A1
99
VDD
101
CK0
103
CK0#
105
VDD
107
A10/AP
109
BA0
111
VDD
113
WE#
115
CAS#
117
VDD
119
A13
121
S1#
123
VDD
125
TEST
127
VSS
129
DQ32
131
DQ33
133
VSS
135
DQS4#
137
DQS4
139
VSS
141
DQ34
143
DQ35
145
VSS
147
DQ40
149
DQ41
151
VSS
153
DM5
155
VSS
157
DQ42
159
DQ43
161
VSS
163
DQ48
165
DQ49
167
VSS
169
DQS6#
171
DQS6
173
VSS
175
DQ50
177
DQ51
179
VSS
181
DQ56
183
DQ57
185
VSS
187
DM7
189
VSS
191
DQ58
193
DQ59
195
VSS
197
SA0
199
VDDSPD
201
SA1
203
VTT
205
GND1
FOX_AS0A626-U4SN-7F
VSS
DQ4
DQ5
VSS
DQS0#
DQS0
VSS
DQ6
DQ7
VSS
DQ12
DQ13
VSS
DM1
RESET#
VSS
DQ14
DQ15
VSS
DQ20
DQ21
VSS
DM2
VSS
DQ22
DQ23
VSS
DQ28
DQ29
VSS
DQS3#
DQS3
VSS
DQ30
DQ31
VSS
CKE1
VDD
A15
A14
VDD
A11
VDD
VDD
VDD
CK1
CK1#
VDD
BA1
RAS#
VDD
S0#
ODT0
VDD
ODT1
VDD
VREF_CA
VSS
DQ36
DQ37
VSS
DM4
VSS
DQ38
DQ39
VSS
DQ44
DQ45
VSS
DQS5#
DQS5
VSS
DQ46
DQ47
VSS
DQ52
DQ53
VSS
DM6
VSS
DQ54
DQ55
VSS
DQ60
DQ61
VSS
DQS7#
DQS7
VSS
DQ62
DQ63
VSS
EVENT#
SDA
SCL
VTT
GND2
2
2
DDR_A_D4
4
DDR_A_D5
6
8
DDR_A_DQS#0
10
DDR_A_DQS0
12
14
DDR_A_D6
16
DDR_A_D7
18
20
DDR_A_D14
22
DDR_A_D15
24
26
DDR_A_DM1
28
SM_DRAMRST#
30
32
DDR_A_D9
34
DDR_A_D12
36
38
40
DDR_A_D21
42
44
DDR_A_DM2
46
48
DDR_A_D16
50
DDR_A_D23
52
54
DDR_A_D28
56
DDR_A_D29
58
60
DDR_A_DQS#3
62
DDR_A_DQS3
64
66
DDR_A_D24
68
DDR_A_D31
70
72
74
76
78
DDR_A_MA14
80
82
DDR_A_MA11DDR_A_MA12
84
DDR_A_MA7DDR_A_MA9
86
A7
88
DDR_A_MA6DDR_A_MA8
90
A6
A4
A2
A0
NC
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204
206
DDR_A_MA4DDR_A_MA5
DDR_A_MA2
DDR_A_MA0DDR_A_MA1
M_CLK_DDR1
M_CLK_DDR#1
DDR_A_BS1
DDR_A_RAS#
DDR_CS0_DIMMA#
M_ODT0
M_ODT1
DDR_A_D36
DDR_A_D37
DDR_A_DM4
DDR_A_D33
DDR_A_D38
DDR_A_D47
DDR_A_D45
DDR_A_DQS#5
DDR_A_DQS5
DDR_A_D46
DDR_A_D44
DDR_A_D52
DDR_A_D53
DDR_A_DM6
DDR_A_D48
DDR_A_D55
DDR_A_D60
DDR_A_D61
DDR_A_DQS#7
DDR_A_DQS7
DDR_A_D62
DDR_A_D63
PM_EXTTS#0
MEM_SDATA
MEM_SCLK
+0.75V_DDR_VTT
SM_DRAMRST# <10,17>
DDR_CKE1_DIMMA <10>
T161PAD~D
M_CLK_DDR1 <10>
M_CLK_DDR#1 <10>M_CLK_DDR#0<10>
DDR_A_BS1 <11>
DDR_A_RAS# <11>
DDR_CS0_DIMMA# <10>
M_ODT0 <10>
M_ODT1 <10>
2.2U_0603_6.3V6K~D
PM_EXTTS#0 <10,17,18>
MEM_SDATA <17,24>
MEM_SCLK <17,24>
1
C1089
2
+V_DDR_MCH_REF
0.1U_0402_16V4Z~D
1
C1088
2
1
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
DDRIII-SODIMM SLOT1
LA-4151P
16 57Fr id ay, July 04, 2008
1
1.0
of
5
4
3
2
1
+1.5V_MEM
DDR_B_D0
DDR_B_D1
DDR_B_DM0
DDR_B_D2
DDR_B_D3
DDR_B_D8
DDR_B_D9
DDR_B_DQS#1
DDR_B_DQS1
DDR_B_D10
DDR_B_D11
DDR_B_D16
DDR_B_D17
DDR_B_DQS#2
DDR_B_DQS2
DDR_B_D18
DDR_B_D19
DDR_B_D24
DDR_B_D25
DDR_B_DM3
DDR_B_D26
DDR_B_D27
DDR_CKE2_DIMMB
DDR_B_BS2
DDR_B_MA12
DDR_B_MA9
DDR_B_MA8
DDR_B_MA5
DDR_B_MA3
DDR_B_MA1
M_CLK_DDR2
M_CLK_DDR#2
DDR_B_MA10
DDR_B_BS0
DDR_B_WE#
DDR_B_CAS#
DDR_B_MA13
DDR_CS3_DIMMB#
DDR_B_D32
DDR_B_D33
DDR_B_DQS#4
DDR_B_DQS4
DDR_B_D34
DDR_B_D35
DDR_B_D40
DDR_B_D41
DDR_B_DM5
DDR_B_D42
DDR_B_D43
DDR_B_D48
DDR_B_D49
DDR_B_DQS6
DDR_B_D50
DDR_B_D51
DDR_B_D56
DDR_B_D57
DDR_B_DM7
DDR_B_D58
DDR_B_D59
2.2U_0603_6.3V6K~D
+0.75V_DDR_VTT
C216
C215
1
1
2
2
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2.2U_0603_6.3V6K~D
DDR_B_DQS#[0..7]<11>
DDR_B_D[0..63]<11>
DDR_B_DM[0..7]<11>
D D
C C
B B
A A
DDR_B_DQS[0..7]<11>
DDR_B_MA[0..14]<11>
+1.5V_MEM
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
+1.5V_MEM
10U_0603_6.3V6M~D
Layout Note:
Place near JDIMMB.203,204
+0.75V_DDR_VTT
C199
C198
1
1
2
2
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
C1124
1
2
1U_0603_10V4Z~D
1
C1131
2
C1126
C1125
1
1
2
2
1U_0603_10V4Z~D
1
C1132
2
5
Layout Note:
Place near JDIMMB
0.1U_0402_16V4Z~D
C200
C201
1
1
2
2
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
1
2
1U_0603_10V4Z~D
1
2
C1133
C1127
10U_0603_6.3V6M~D
C1128
C1129
1
1
2
2
1U_0603_10V4Z~D
1
C1134
2
330U_D2_2.5VY_R15M
1
C1130
+
2
4
1
2
+3.3V_M
C191
DDR_CKE2_DIMMB<10>
DDR_CS3_DIMMB#<10>
+3.3V_M
R131
10K_0402_5%~D
0.1U_0402_16V4Z~D
M_CLK_DDR2<10>
M_CLK_DDR#2<10>
DDR_B_CAS#<11>
12
DDR_B_BS2<11>
DDR_B_BS0<11>
DDR_B_WE#<11>
10K_0402_5%~D
+V_DDR_MCH_REF
1
C192
2
0.1U_0402_16V4Z~D
12
R132
JDIMMB
1
VREF_DQ
3
VSS
5
DQ0
7
DQ1
9
VSS
11
DM0
13
VSS
15
DQ2
17
DQ3
19
VSS
21
DQ8
23
DQ9
25
VSS
27
DQS1#
29
DQS1
31
VSS
33
DQ10
35
DQ11
37
VSS
39
DQ16
41
DQ17
43
VSS
45
DQS2#
47
DQS2
49
VSS
51
DQ18
53
DQ19
55
VSS
57
DQ24
59
DQ25
61
VSS
63
DM3
65
VSS
67
DQ26
69
DQ27
71
VSS
73
CKE0
75
VDD
77
NC
79
BA2
81
VDD
83
A12/BC#
85
A9
87
VDD
89
A8
91
A5
93
VDD
95
A3
97
A1
99
VDD
101
CK0
103
CK0#
105
VDD
107
A10/AP
109
BA0
111
VDD
113
WE#
115
CAS#
117
VDD
119
A13
121
S1#
123
VDD
125
TEST
127
VSS
129
DQ32
131
DQ33
133
VSS
135
DQS4#
137
DQS4
139
VSS
141
DQ34
143
DQ35
145
VSS
147
DQ40
149
DQ41
151
VSS
153
DM5
155
VSS
157
DQ42
159
DQ43
161
VSS
163
DQ48
165
DQ49
167
VSS
169
DQS6#
171
DQS6
173
VSS
175
DQ50
177
DQ51
179
VSS
181
DQ56
183
DQ57
185
VSS
187
DM7
189
VSS
191
DQ58
193
DQ59
195
VSS
197
SA0
199
VDDSPD
201
SA1
203
VTT
205
GND1
FOX_AS0A626-U8SN-7F
VREF_CA
VSS
DQ4
DQ5
VSS
DQS0#
DQS0
VSS
DQ6
DQ7
VSS
DQ12
DQ13
VSS
DM1
RESET#
VSS
DQ14
DQ15
VSS
DQ20
DQ21
VSS
DM2
VSS
DQ22
DQ23
VSS
DQ28
DQ29
VSS
DQS3#
DQS3
VSS
DQ30
DQ31
VSS
CKE1
VDD
VDD
VDD
VDD
VDD
CK1
CK1#
VDD
BA1
RAS#
VDD
ODT0
VDD
ODT1
VDD
VSS
DQ36
DQ37
VSS
DM4
VSS
DQ38
DQ39
VSS
DQ44
DQ45
VSS
DQS5#
DQS5
VSS
DQ46
DQ47
VSS
DQ52
DQ53
VSS
DM6
VSS
DQ54
DQ55
VSS
DQ60
DQ61
VSS
DQS7#
DQS7
VSS
DQ62
DQ63
VSS
EVENT#
SDA
SCL
VTT
GND2
A15
A14
A11
A7
A6
A4
A2
A0
S0#
NC
+1.5V_MEM+V_DDR_MCH_REF
2
DDR_B_D4
4
DDR_B_D5
6
8
DDR_B_DQS#0
10
DDR_B_DQS0
12
14
DDR_B_D6
16
DDR_B_D7
18
20
DDR_B_D12
22
DDR_B_D13
24
26
DDR_B_DM1
28
SM_DRAMRST#
30
32
DDR_B_D14
34
DDR_B_D15
36
38
DDR_B_D20
40
DDR_B_D21
42
44
DDR_B_DM2
46
48
DDR_B_D22
50
DDR_B_D23
52
54
DDR_B_D28
56
DDR_B_D29
58
60
DDR_B_DQS#3
62
DDR_B_DQS3
64
66
DDR_B_D30
68
DDR_B_D31
70
72
DDR_CKE3_DIMMB
74
76
78
DDR_B_MA14
80
82
DDR_B_MA11
84
DDR_B_MA7
86
88
DDR_B_MA6
90
DDR_B_MA4
92
94
DDR_B_MA2
96
DDR_B_MA0
98
100
M_CLK_DDR3
102
M_CLK_DDR#3
104
106
DDR_B_BS1
108
DDR_B_RAS#
110
112
DDR_CS2_DIMMB#
114
M_ODT2
116
118
M_ODT3
120
122
124
126
128
DDR_B_D36
130
DDR_B_D37
132
134
DDR_B_DM4
136
138
DDR_B_D38
140
DDR_B_D39
142
144
DDR_B_D44
146
DDR_B_D45
148
150
DDR_B_DQS#5
152
DDR_B_DQS5
154
156
DDR_B_D46
158
DDR_B_D47
160
162
DDR_B_D52
164
DDR_B_D53
166
168
DDR_B_DM6DDR_B_DQS#6
170
172
DDR_B_D54
174
DDR_B_D55
176
178
DDR_B_D60
180
DDR_B_D61
182
184
DDR_B_DQS#7
186
DDR_B_DQS7
188
190
DDR_B_D62
192
DDR_B_D63
194
196
PM_EXTTS#0
198
MEM_SDATA
200
MEM_SCLK
202
204
206
+0.75V_DDR_VTT
2
SM_DRAMRST# <10,16>
DDR_CKE3_DIMMB <10>
T162
PAD~D
M_CLK_DDR3 <10>
M_CLK_DDR#3 <10>
DDR_B_BS1 <11>
DDR_B_RAS# <11>
DDR_CS2_DIMMB# <10>
M_ODT2 <10>
M_ODT3 <10>
2.2U_0603_6.3V6K~D
1
2
PM_EXTTS#0 <10,16,18>
MEM_SDATA <16,24>
MEM_SCLK <16,24>
+V_DDR_MCH_REF
0.1U_0402_16V4Z~D
1
C1090
C1091
2
DELL CONFIDENTIAL/PROPRIETARY
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
DDRIII-SODIMM SLOT2
LA-4151P
17 57Fr id ay, July 04, 2008
1
1.0
of
5
+3.3V_M
12
R134
8.2K_0402_5%~D
+1.05V_VCCP
R135
D D
H_THERMTRIP#<7>
THERMTRIP_MCH#<10>
2.2K_0402_5%~D
1 2
MMST3904-7-F_SOT323-3~D
+1.05V_VCCP
R138
2.2K_0402_5%~D
1 2
MMST3904-7-F_SOT323-3~D
THERMATRIP1#
C
E
3 1
12
C
E
3 1
1
C218
0.1U_0402_16V4Z~D
2
R137
8.2K_0402_5%~D
THERMATRIP2#
1
C220
0.1U_0402_16V4Z~D
2
RB751S40T1_SOD523-2~D
2
B
Q5
+3.3V_M
2
B
Q6
Place under CPU
C225
1
+RTC_CELL
C229
0.1U_0402_16V4Z~D
2
1
C231
2
12
R155
8.2K_0402_5%~D
THERMATRIP3#
1
C240
0.1U_0402_16V4Z~D
2
C
E
3 1
1
2
C
E
3 1
100P_0402_50V8K~D
C C
H_THERMDA<7>
H_THERMDC<7>
Q9 Place near DIMM
Place C227 close
to Q9
+3.3V_M
B B
1
Place C223 close to the Q8 as possible
Place C224, C225 close to the Guardian pins as possible
470P_0402_50V7K~D
Place C228 close to the Guardian pins as possible
1
C227
@
100P_0402_50V8K~D
2
1 2
R142 0_0603_5%~D
0.1U_0402_16V4Z~D
2
C223
@
Rset=1.5K,Tp=95degree
+3.3V_M
A A
5
4
D2
2 1
2
B
Q8
MMST3904-7-F_SOT323-3~D
2
B
Q9
MMST3904-7-F_SOT323-3~D
12
R151
1.5K_0402_1%~D
2200P_0402_50V7K~D
+5V_RUN
4
C219
1U_0603_10V4Z~D
1
2
0.1U_0402_16V4Z~D
1
C234
2
1
2
22U_0805_6.3VAM~D
BC_DAT_EMC4002<34>
BC_CLK_EMC4002<34>
2
C224
2200P_0402_50V7K~D
1
C228
C230
3.3V_M_PWRGD<34,37>
ICH_PWRGD#<37>
10U_0805_10V4Z~D
+3.3V_RUN
C235
1
2
3
+3.3V_M
12
R136
10K_0402_5%~D
FAN1_DET#<22>
1
2
R146 1K_0402_5%~D
R148 1K_0402_5%~D
+3V_M_THRM
10U_0805_10V4Z~D
0.1U_0402_16V4Z~D
1
1
C237
C236
2
2
EC_32KHZ_OUT<34>
Pull-up Resistor
on ADDR_MODE/XEN
<= 4.7K +/- 5% 2F(r/w)
*
10K
18K
>= 33K
+FAN1_VOUT
FAN1_TACH_FB
REM_DIODE1_N
REM_DIODE3_P
REM_DIODE3_N
+3V_M_THRM
+RTC_CELL_R
1 2
1 2
THERMATRIP1#
THERMATRIP2#
THERMATRIP3#
VSET
12
R150 4.7K_0402_5%~D
+FAN1_VOUT
FAN1_TACH_FB
EC_32KHZ_OUT
For Remote1
mode
2N3904
2N3904
Thermistor
Thermistor
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
JFAN1
1
1
2
2
3
3
4
4
5
GND
6
GND
MOLEX_53780-0470
U3
EMC4002
10
SMDATA/BC-LINK_DATA
11
SMBCLK/BC-LINK_CLK
36
DP1/VREF_T
35
DN1/THERM
38
DP2
37
DN2
41
DP3/DN7
40
DN3/DP7
4
VCC
21
RTC_PWR3V
THERMTRIP_SIO/PWM1/GPIO5
18
VCC_PWRGD
17
3V_PWROK#
22
THERMTRIP1#
23
THERMTRIP2#
24
THERMTRIP3#
42
VSET
3
ADDR_MODE/XEN
6
VDD_5V
5
VDD_5V
9
VDD_3V
7
FAN_OUT
8
FAN_OUT
15
TACH1/GPIO3
14
CLK_IN/GPIO2
SMBUS
Address
2E(r/w)
2F(r/w)
2E(r/w)
200K_0402_1%~D
DP6/VREF_T2
ATF_INT#/BC-LINK_IRQ#
POWER_SW#
ACAVAIL_CLR
VDDH/VDD_5V2
VDDH/VDD_5V2
VDDL/VDD_3V2
LDO_OUT/FAN_OUT2
LDO_OUT/FAN_OUT2
TACH2/GPIO4
PWM2/GPIO1
VSS
49
0_0402_5%~D
R1033
VIN1
VCP1
VCP2
DP4/DN8
DN4/DP8
DP5/DN9
DN5/DP9
DN6/VIN2
SYS_SHDN#
LDO_SHDN#
LDO_POK
LDO_SET
POWER_SW#
12
R1032
12
39
48
45
REM_DIODE4_PREM_DIODE1_P
44
REM_DIODE4_N
43
47
46
1
2
R141 10K_0402_5%~D
12
POWER_SW#
26
27
20
25
R1081
@
19
R149 10K_0402_5%~D
34
LDO_SET
33
+3V_LDOIN
32
31
28
29
30
16
13
+RTC_CELL
5
IN1
4
O
IN2
3
12
R1063 0_0402_5%~D@
12
R1064 0_0402_5%~D@
2
1 2
R1061 4.7K_0402_5%~D
Place C221 close to the
Guardian pins as possible.
12
C1158 0.1U_0402_16V4Z~D
1 2
P
G
U93
74AHC1G08GW_SOT353-5~D
BC_INT#_EMC4002 <34>
ACAV_IN <34,46>
12
10K_0402_5%~D
12
2.5V_RUN_PWRGD <33,37>
+1.8V_RUN_LVDS
10U_0805_10V6K~D
1
2
1
R143 0_0402_5%~D
2
R144 0_0402_5%~D
2
1
PWR_MON_GFX <47>
PWR_MON <45>
MAX8731_IINP
1
C221
2
2200P_0402_50V7K~D
THERMISTOR OPTION:
Single-ended ro ut in g t o thermistor is permissible
(ground retu r n ) . Pl a c e R139 and C226 near EMC4002
+3.3V_M
0.1U_0402_16V4Z~D
1
C239
C238
2
12
12
MAX8731_IINP <46>
1 2
R139
1.2K_0402_1%~D
R145 10K_0402_5%~D
1 2
R147 47K_0402_1%~D@
+3.3V_SUS
10U_0805_10V4Z~D
1
1
@
C232
2
2
PM_EXTTS#0 <10,16,17>
DOCK_PWR_SW# <34>
POWER_SW_IN# <34>
Diode circui t a t DP 4 /DN4 is used for skin
temp sensor (p la ce d o ptimally between CPU,
MCH and MEM).
C
Q7
2
B
MMST3904-7-F_SOT323-3~D
E
3 1
1 2
R140
10KB_0603_1%_TSM1A103F34D3R~D
1 2
C226
0.1U_0402_16V4Z~D
12
At maximum loa d c ur rent of 600mA,the the
voltage drop a c r o ss the should be keep
in the range of 0.5V to 1V
0.1U_0402_16V4Z~D
R152
0_1210_5%~D
C233
+3.3V_M
THERM_STP# <42>
+RTC_CELL
+3.3V_RUN
12
1
C222
@
100P_0402_50V8K~D
2
Place C222 close to Q7 as
possible.
LDO_SET
Voltage margi ning circuit
for LDO output. Adjustable
from 1.2 to 2.5V.
Ra=((LDO_OUT /1.2)-1)*Rb.
DELL CONFIDENTIAL/PROPRIETARY
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
FAN & Thermal Sensor
LA-4151P
1
+1.8V_RUN_LVDS
3.16K_0402_1%~D
12
R153
5.1K_0402_1%~D
12
R154
18 57Fr id ay, July 04, 2008
Ra
Rb
1.0
of
5
4
3
2
1
LCD Power
+3.3V_RUN_LVDS
R159 2.2K_0402_5%~D
R160 2.2K_0402_5%~D
D D
C C
+3.3V_RUN_LVDS
B B
Close to JLVD1.25
+LCDVDD
0.1U_0402_16V4Z~D
1
2
0.1U_0402_16V4Z~D
1
2
JLVDS1
51
G9
50
G8
49
G7
48
G6
47
G5
46
G4
45
G3
44
G2
43
G1
JAE_SP07-12942-03
C243
C244
42
42
41
41
40
40
39
39
38
38
37
37
36
36
35
35
34
34
33
33
32
32
31
31
30
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
9
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
LDDC_DATA_MCH_LVDS
LDDC_CLK_MCH_LVDS
LVDS_CBL_DET#
LCD_SMBCLK
LCD_SMBDAT
BIA_PWM_LCD
LCD_TST
+LCDVDD
BREATH_BLUE_LED
BATT_YELLOW_LED
BATT_BLUE_LED
SW_LVDS_ACLK+ <40>
SW_LVDS_ACLK- <40>
SW_LVDS_A2+ <40>
SW_LVDS_A2- <40>
SW_LVDS_A1+ <40>
SW_LVDS_A1- <40>
SW_LVDS_A0+ <40>
SW_LVDS_A0- <40>
LDDC_DATA_MCH_LVDS <39>
LDDC_CLK_MCH_LVDS <39>
LVDS_CBL_DET# <22>
LCD_SMBCLK <34>
LCD_SMBDAT <34>
C246
0.1U_0603_50V4Z~D
LCD_TST <33>
C245
0.1U_0402_16V4Z~D
+3.3V_RUN
BREATH_BLUE_LED <38>
BATT_YELLOW_LED <38>
BATT_BLUE_LED <38>
1 2
1
2
For Webcam
+CAMERA_VDD
100K_0402_5%~D
0.1U_0402_16V4Z~D
1
C1168
2
+15V_ALW
R1098
PMV45EN_SOT23-3~D
10U_1206_16V4Z~D
1
C1169
2
12
Place near to JLVDS1
+3.3V_RUN_LVDS
+INV_PWR_SRC
DMIC_CLK <21>
DMIC0 <21>
+5V_ALW
Q165
D
S
+CMOS_VDD
13
G
2
1 2
1 2
1
2
LDDC_CLK_MCH_LVDS
LDDC_DATA_MCH_LVDS
+3.3V_RUN_LVDS
12
R1091
10K_0402_5%~D
R1094
@
0_0603_5%~D
12
R1096
0_0603_5%~D
12
C1170
0.1U_0402_16V4Z~D
+3.3V_RUN_LVDS
D81
RB751S40T1_SOD523-2~D
+3.3V_RUN
+5V_RUN
21
PJP51 PAD-OPEN 4x4m6@
1 2
PJP52 PAD-OPEN 4x4m5@
1 2
BIA_PWM <12>
USBP11+<24>
USBP11-<24>
USBP11-
USBP11_D+
BKT_GPIO18<35>
LCD_VCC_TEST_EN<33>
ENVDD<12>
+3.3V_RUN
+3.3V_RUN_BKT_PWR
L70
@
DLW21SN121SQ2L_4P~D
1
1
4
4
1 2
R1095 0_0402_5%~D
1 2
R1097 0_0402_5%~D
U98
@
1
GND
IO2
2
IO1
VIN
PRTR5V0U2X_SOT143-4~D
2N7002DW-T/R7_SOT363-6~D
BKT_GPIO18
2 1
D68 RB751V_SOD323-2~D5@
3
2
D3 BAT54CW_SOT323~D
2
2
3
3
USBP11_D-
3
4
Close to JLVD1.8,9,10
Webcam PWR CTRL
CCD_OFF<33>
A A
CCD_OFF
13
D
2
G
S
Q166
2N7002W-7-F_SOT323-3~D
1
C1171
0.1U_0402_25V4K~D
2
CAM_CBL_DET#<22>
+CAMERA_VDD
USBP11_DUSBP11_D+
CAM_CBL_DET#
Q13A
EN_LCDPWR
1
USBP11_D+USBP11+
USBP11_D-
+CAMERA_VDD
TYCO_2041070-6
+LCDVDD
12
61
BKT_GPIO14<35>
JCAM
1
1
2
2
3
3
4
4
5
5
6
6
7
GND
8
GND
470_0402_5%~D
R161
2
2
I
40mil
1
2
RUN_ON<21,33,36,37,39>
+15V_ALW +3.3V_ALW
+15V_ALW
100K_0402_5%~D
12
R162
5
1
O
Q15
G
DDTC124EUA-7-F_SOT323-3~D
3
+PWR_SRC
1000P_0402_50V7K~D
12
C248
R168 100K_0402_5%~D
BKT_GPIO14
RUN_ON
+LCDVDD
12
R158
100K_0402_5%~D
2N7002DW-T/R7_SOT363-6~D
12
3
Q13B
4
R167
100K_0402_5%~D
PWR_SRC_ON
+PWR_SRC_ON_F
1 2
D69
3
2
BAT54CW_SOT323~D
D
S
6
4 5
2
1
G
Q12
SI3456DV-T1-E3_TSOP6~D
3
100K_0402_5%~D
0.1U_0402_25V4Z~D
@
R163
1
C242
2
Q16
@
FDS4435_NL_SO8~D
8
7
1
6
2
5
3
4
D
1 3
EN_INVPWR
1
Dual layout for Q17
Overlap on Q 1 6 for pop option
+PWR_SRC
Q17
SI3457DV-T1_TSOP6~D
S
4 5
G
3
PWR_SRC_ON
1
C241
0.1U_0402_16V4Z~D
2
40mil
1
C247
0.1U_0603_50V4Z~D
2
Q18
2N7002W-7-F_SOT323-3~D
S
G
2
R1058
1 2
100K_0402_5%~D@
FDS4435: P CHANNAL
D
6
2
1
+INV_PWR_SRC
+INV_PWR_SRC
SI3457DV : P CHANNAL
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
LVDS Conn
LA-4151P
19 57Fr id ay, July 04, 2008
1
1.0
of
2
1
+3.3V_RUN
DAT_DDC2<12>
CLK_DDC2<12>
CRT_VSYNC<12>
CRT_HSYNC<12>
CRT_RED<12>
CRT_GRN<12>
B B
CRT_BLU<12>
CRT_SWITCH<33>
DAT_DDC2
CLK_DDC2
CRT_VSYNC
CRT_HSYNC
CRT_RED
CRT_GRN
CRT_BLU
CRT_SWITCH
SEL CRT TV
0 MB Dock
1 Dock NA
U4
4
VCC
10
VCC
18
VCC
27
VCC
38
VCC
50
VCC
56
VCC
2
A0
3
A1
7
A2
8
A3
11
A4
12
A5
14
A6
15
A7
19
A8
20
A9
17
SEL
1
GND
6
GND
9
GND
13
GND
16
GND
21
GND
24
GND
28
GND
33
GND
39
GND
44
GND
49
GND
53
GND
55
GND
TS3DV520ERHUR_QFN56_11X5~D
0B1
1B1
2B1
3B1
4B1
5B1
6B1
7B1
8B1
9B1
0B2
1B2
2B2
3B2
4B2
5B2
6B2
7B2
8B2
9B2
NC
NC
NC
NC
48
47
43
42
37
36
32
31
22
23
46
45
41
40
35
34
30
29
25
26
52
5
54
51
DAT_DDC2_CRT
CLK_DDC2_CRT
VSYNC_CRT
HSYNC_CRT
RED_CRT
GREEN_CRT
BLUE_CRT
DAT_DDC2_DOCK
CLK_DDC2_DOCK
VSYNC_DOCK
HSYNC_DOCK
RED_DOCK
GREEN_DOCK
BLUE_DOCK
10U_0805_10V4Z~D
1
2
DAT_DDC2_CRT <29>
CLK_DDC2_CRT <29>
VSYNC_CRT <29>
HSYNC_CRT <29>
RED_CRT <29>
GREEN_CRT <29>
BLUE_CRT <29>
DAT_DDC2_DOCK <31>
CLK_DDC2_DOCK <31>
VSYNC_DOCK <31>
HSYNC_DOCK <31>
RED_DOCK <31>
GREEN_DOCK <31>
BLUE_DOCK <31>
0.1U_0402_16V4Z~D
1
1
C259
C260
2
2
To MB CRT Conn.
To Dock Conn.
+3.3V_RUN
0.1U_0402_16V4Z~D
C261
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
1
1
C263
C262
2
2
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
1
C264
2
0.1U_0402_16V4Z~D
1
1
C265
C266
2
2
A A
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
2
1
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
CRT/Video switch
LA-4151P
20 57Fr id ay, July 04, 2008
1.0
of
2
SW for eDOCK side
C271 0.1U_0402_10V7K~D
DPB_AUX_C
DPB_AUX<12>
DPB_AUX#<12>
SDVO_CTRLCLK<10>
SDVO_CTRLDATA<10>
B B
12
DPB_AUX#_C
12
C273 0.1U_0402_10V7K~D
DPB_DOCK_CA_DET
SDVO_CTRLDATA
2
1A
2A51B
1
1OE#
7
2OE#
SN74CBTD3306CPWR_TSSOP8~D
2
1A
2A51B
1
1OE#
7
2OE#
SN74CBTD3306CPWR_TSSOP8~D
DPB_DOCK_CA_DET#
SW for eDOCK side
+5V_RUN
C272 0.1U_0402_10V7K~D
DPC_DOCK_AUX_C
DPC_DOCK_AUX<12>
DPC_DOCK_AUX#<12>
DDPC_CTRLCLK<10>
DDPC_CTRLDATA<10>
12
DPC_DOCK_AUX#_C
12
C274 0.1U_0402_10V7K~D
DPC_DOCK_CA_DET
U101
2
1A
2A51B
1
1OE#
7
2OE#
SN74CBTD3306CPWR_TSSOP8~D
+5V_RUN
U102
2
1A
2A51B
1
1OE#
7
2OE#
SN74CBTD3306CPWR_TSSOP8~D
DPC_DOCK_CA_DET#
C1159 0.1U_0402_16V4Z~D
+5V_RUN
U99
+5V_RUN
U100
VCC
GND
VCC
GND
NC7SZ04P5X_NL_SC70-5~D
1 2
8
VCC
3
6
2B
4
GND
C1174
1 2
8
VCC
3
6
2B
4
GND
+3.3V_RUN
C1160 0.1U_0402_16V4Z~D
1 2
8
3
6
2B
4
C1175
1 2
8
3
6
2B
4
0.1U_0402_16V4Z~D
C277 0.1U_0402_16V4Z~D
1 2
1
5
P
DPB_DOCK_CA_DET
NC
4
A2Y
G
U8 NC7SZ04P5X_NL_SC70-5~D
0.1U_0402_16V4Z~D
+3.3V_RUN
U7
4
1 2
3
R1052 1M_0402_5%~D
C276 0.1U_0402_16V4Z~D
1 2
1
5
P
DPC_DOCK_CA_DET
NC
A2Y
G
3
R1053 1M_0402_5%~D
DPB_DOCK_AUX <31>
DPB_DOCK_AUX# <31>
DPB_DOCK_AUX#
DPB_DOCK_AUXSDVO_CTRLCLK
DPC_DOCK_AUX_SW <31>
DPC_DOCK_AUX#_SW <31>
DPC_DOCK_AUX#_SW
DPC_DOCK_AUX_SW
1 2
1 2
R1086 100K_0402_5%~D@
1 2
R1085 100K_0402_5%~D@
DPB_DOCK_CA_DET <31>
DPC_DOCK_CA_DET <31>
1 2
R1088 100K_0402_5%~D@
1 2
R1087 100K_0402_5%~D@
+3.3V_RUN
+3.3V_RUN
AUD_NB_MUTE<33>
DOCK_LOM_TRD0-<31>
DOCK_LOM_TRD0+<31>
DOCK_LOM_TRD1-<31>
DOCK_LOM_TRD1+<31>
DOCK_LOM_TRD2-<31>
DOCK_LOM_TRD2+<31>
DOCK_LOM_TRD3-<31>
DOCK_LOM_TRD3+<31>
PLTRST3#<22,32>
PCIE_IRX_WLANTX_N2<24>
PCIE_IRX_WLANTX_P2<24>
PCIE_ITX_WLANRX_N2_C<24>
PCIE_ITX_WLANRX_P2_C<24>
PCIE_MCARD1_DET#<24>
CARD_SMBCLK<28,34>
CARD_SMBDAT<28,34>
MSCLK<34>
MSDATA<34>
LED_WLAN_OUT#<38>
PCIE_WAKE#<28,33>
PCIE_IRX_WANTX_N1<24>
PCIE_IRX_WANTX_P1<24>
PCIE_ITX_WANRX_N1_C<24>
PCIE_ITX_WANRX_P1_C<24>
PCIE_MCARD2_DET#<22>
WWAN_RADIO_DIS#<33>
PCIE_IRX_GLANTX_P6<24>
PCIE_IRX_GLANTX_N6<24>
USB_MCARD2_DET#<24>
PCIE_ITX_GLANRX_P6_C<24>
PCIE_ITX_GLANRX_N6_C<24>
BKT_GPIO12<35>
LAN_RSTSYNC<23>
LAN_CLK<23>
LAN_TX0<23>
LAN_TX1<23>
LAN_TX2<23>
ICH_AZ_CODEC_BITCLK<23>
ICH_AZ_CODEC_SDIN0<23>
ICH_AZ_CODEC_SDOUT<23>
ICH_AZ_CODEC_SYNC<23>
ICH_AZ_CODEC_RST#<23>
+3.3V_RUN_BKT_PWR
+3.3V_RUN
+5V_RUN_AMP
+3.3V_WLAN
+3.3V_LAN
+3.3V_RUN_WWAN
+5V_ALW
+LOM_VCT
LAN_RX0<23>
LAN_RX1<23>
LAN_RX2<23>
AUD_NB_MUTE
DOCK_LOM_TRD0DOCK_LOM_TRD0+
DOCK_LOM_TRD1DOCK_LOM_TRD1+
DOCK_LOM_TRD2DOCK_LOM_TRD2+
DOCK_LOM_TRD3DOCK_LOM_TRD3+
LAN_DISABLE#_R
PLTRST3#
PCIE_IRX_WLANTX_N2
PCIE_IRX_WLANTX_P2
PCIE_ITX_WLANRX_N2_C
PCIE_ITX_WLANRX_P2_C
PCIE_MCARD1_DET#
CARD_SMBCLK
CARD_SMBDAT
MSCLK
MSDATA
LED_WLAN_OUT#
PCIE_WAKE#
PCIE_IRX_WANTX_N1
PCIE_IRX_WANTX_P1
PCIE_ITX_WANRX_N1_C
PCIE_ITX_WANRX_P1_C
PCIE_MCARD2_DET#
WWAN_RADIO_DIS#
PCIE_IRX_GLANTX_P6
PCIE_IRX_GLANTX_N6
USB_MCARD2_DET#
PCIE_ITX_GLANRX_P6_C
PCIE_ITX_GLANRX_N6_C
BKT_GPIO12
LAN_RSTSYNC
LAN_CLK
LAN_TX0
LAN_TX1
LAN_TX2
LAN_RX0
LAN_RX1
LAN_RX2
ICH_AZ_CODEC_BITCLK
ICH_AZ_CODEC_SDIN0
ICH_AZ_CODEC_SDOUT
ICH_AZ_CODEC_SYNC
ICH_AZ_CODEC_RST#
JBIO1
1
1
3
3
5
5
7
7
9
9
11
GND
13
13
15
15
17
17
19
19
21
21
23
23
25
25
27
27
29
29
31
31
33
33
35
GND
37
37
39
39
41
41
43
43
45
45
47
47
49
49
51
51
53
53
55
55
57
57
59
GND
61
61
63
63
65
65
67
67
69
69
71
71
73
73
75
75
77
77
79
79
81
GND
83
83
85
85
87
87
89
89
91
91
93
93
95
95
97
97
99
99
101
101
103
103
105
GND
107
107
109
109
111
111
113
113
115
115
117
117
119
119
121
121
123
123
125
125
127
127
129
GND
131
131
133
133
135
135
137
137
139
139
1
USBP0+
GND
GND
GND
GND
GND
GND
2
2
4
4
6
6
8
8
10
10
12
14
14
16
16
18
18
20
20
22
22
24
24
26
26
28
28
30
30
32
32
34
34
36
38
38
40
40
42
42
44
44
46
46
48
48
50
50
52
52
54
54
56
56
58
58
60
62
62
64
64
66
66
68
68
70
70
72
72
74
74
76
76
78
78
80
80
82
84
84
86
86
88
88
90
90
92
92
94
94
96
96
98
98
100
100
102
102
104
104
106
108
108
110
110
112
112
114
114
116
116
118
118
120
120
122
122
124
124
126
126
128
128
130
132
132
134
134
136
136
138
138
140
140
USBP0DOCK_LOM_ACTLED_YEL#
DOCK_LOM_SPD10LED_GRN#
DOCK_LOM_SPD100LED_ORG#
TPA0+
TPA0-
TPB0+
TPB0WLAN_RADIO_DIS#
BT_ACTIVE
COEX1_BT_ACTIVE
COEX2_WLAN_ACTIVE
USB_MCARD1_DET#
ICH_CL_CLK1
ICH_CL_DATA1
ICH_CL_RST1#
HOST_DEBUG_RX
HOST_DEBUG_TX
MINI2CLK_REQ#
CLK_PCIE_MINI2#
CLK_PCIE_MINI2
CLK_PCIE_MINI1#
CLK_PCIE_MINI1
MINI1CLK_REQ#
USBP4+
USBP4-
LED_WWAN_OUT#
USB_OC0_1#
USB_POWERSHARE_PWR_EN#
USB_SW_USBD+
USB_SW_USBDCELL_CHARGER_DET_R#
CKG_SMBCLK
CKG_SMBDAT
AUD_PC_BEEP
DOCKED
DMIC0
DMIC_CLK
DOCK_MIC_DET
DOCK_HP_DET
AUD_HP_NB_SENSE
RUN_ON
DAI_DO#
DAI_DI
DAI_LRCK#
DAI_BCLK#
EN_I2S_NB_CODEC
DAI_12MHZ#
INT_SPK_L1
INT_SPK_L2
INT_SPK_R1
INT_SPK_R2
WIRELESS_ON#/OFF
BKT_GPIO13
BKT_I2S_DO
BKT_I2S_LRC
BKT_I2S_SCLK
BKT_MCLK
SNIFFER_PWR_SW#
SNIFFER_YELLOW
SNIFFER_BLUE
USBP0+ <24>
USBP0- <24>
DOCK_LOM_ACTLED_YEL# <31>
DOCK_LOM_SPD10LED_GRN# <31>
DOCK_LOM_SPD100LED_ORG# <31>
TPA0+ <27>
TPA0- <27>
TPB0+ <27>
TPB0- <27>
WLAN_RADIO_DIS# <33>
BT_ACTIVE <30,38>
COEX1_BT_ACTIVE <30>
COEX2_WLAN_ACTIVE <30>
USB_MCARD1_DET# <24>
ICH_CL_CLK1 <24>
ICH_CL_DATA1 <24>
ICH_CL_RST1# <24>
HOST_DEBUG_RX <34>
HOST_DEBUG_TX <34>
MINI2CLK_REQ# <6>
CLK_PCIE_MINI2# <6>
CLK_PCIE_MINI2 <6>
CLK_PCIE_MINI1# <6>
CLK_PCIE_MINI1 <6>
MINI1CLK_REQ# <6>
USBP4+ <24>
USBP4- <24>
LED_WWAN_OUT# <38>
USB_OC0_1# <24>
USB_POWERSHARE_PWR_EN# <33>
USB_SW_USBD+ <40>
USB_SW_USBD- <40>
CKG_SMBCLK <6,34,46>
CKG_SMBDAT <6,34,46>
DOCKED <33>
DMIC0 <19>
DMIC_CLK <19>
DOCK_MIC_DET <33>
DOCK_HP_DET <33>
AUD_HP_NB_SENSE <33>
RUN_ON <19,33,36,37,39>
DAI_DO# <31>
DAI_DI <31>
DAI_LRCK# <31>
DAI_BCLK# <31>
EN_I2S_NB_CODEC <33>
DAI_12MHZ# <31>
INT_SPK_L1 <29>
INT_SPK_L2 <29>
INT_SPK_R1 <29>
INT_SPK_R2 <29>
WIRELESS_ON#/OFF <33>
BKT_GPIO13 <35>
BKT_I2S_DO <39>
BKT_I2S_LRC <39>
BKT_I2S_SCLK <39>
BKT_MCLK <39>
SNIFFER_PWR_SW# <34>
SNIFFER_YELLOW <38>
SNIFFER_BLUE <38>
+1.5V_RUN
FOX_QT00140A-1120-9F
+3.3V_RUN
R798
20K_0402_5%~D
1 2
13
D
Q10
DPB_DOCK_HPD<31>
A A
DPC_DOCK_HPD_R<31>
DPB_DOCK_HPD
100K_0402_5%~D
R191
1 2
DPC_DOCK_HPD_R
100K_0402_5%~D
1 2
2
R796
G
S
+3.3V_RUN
2
G
BSS138_SOT23~D
R795
20K_0402_5%~D
1 2
13
D
BSS138_SOT23~D
S
1 2
Q114
DPB_HPD# <12>
R824
7.5K_0402_5%~D
R825
7.5K_0402_5%~D
1 2
DPC_DOCK_HPD# <12>
2
SPKR<24>
BEEP<34>
2
1
+5V_RUN_BKT_PWR
+3.3V_RUN_WWAN_PWR
C389 0.1U_0402_16V4Z~D
C394 0.1U_0402_16V4Z~D
+3.3V_ALW
0.1U_0402_16V4Z~D
4.7U_0603_6.3V4Z~D
2
C454
C453
1
+5V_RUN
PAD-OPEN 2x2m~D
PAD-OPEN 2x2m~D
R327 499K_0402_1%~D
1 2
R828 499K_0402_1%~D
1 2
Q44
STS11NF30L_SO8~D
8
7
5
ENAB_3VLAN<36>
PAD-OPEN 2x2m~D
PJP53
6@
21
PJP54
5@
21
PJP56
21
1 2
1 2
4
+3.3V_RUN_WWAN
1
2
36
+5V_RUN_AMP
TRACE>15 mil
AUD_PC_BEEP USB_MCARD1_DET#
12
@
R328
10K_0402_5%~D
+3.3V_LAN
10U_0805_10V4Z~D
4.7U_0603_6.3V4Z~D
1
2
C455
C456
2
1
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
0.1U_0402_16V4Z~D
4.7U_0603_6.3V4Z~D
2
C457
1
0.1U_0402_16V4Z~D
2
2
C458
1
1
PCIE_MCARD1_DET#
USB_MCARD1_DET# PCIE_MCARD1_DET#
C459
1 2
R438 100K_0402_5%~D
1 2
R439 100K_0402_5%~D@
1 2
R1090 100K_0402_5%~D
1 2
R741 0_0402_5%~D@
EN_CELL_CHARGER_DET#<34>
+3.3V_RUN
CELL_CHARGER_DET#<33>
+3.3V_ALW_ICH
LAN_DISABLE#<24>
LAN_DISABLE#_R<33>
USB_MCARD2_DET#
PCIE_MCARD2_DET#
USB_MCARD2_DET# PCIE_MCARD2_DET#
R996 0_0402_5%~D@
LAN_DISABLE#
LAN_DISABLE#_R
R447 100K_0402_5%~D
R449 100K_0402_5%~D
1 2
R740 0_0402_5%~D@
C1135 1U_0402_6.3V6K~D
12
12
R1028 0_0402_5%~D
DELL CONFIDENTIAL/PROPRIETARY
Title
Size Document Number Rev
1
Date: Sheet
Display port
+3.3V_RUN
12
12
1 2
D80
2 1
RB751S40T1_SOD523-2~D
CELL_CHARGER_DET_R#
R1083 100K_0402_5%~D
Compal Electronics, Inc.
LA-4151P
21 57Fr id ay, July 04, 2008
+3.3V_ALW2
12
1.0
of
5
+3.3V_RUN
PCI_DEVSEL#
PCI_STOP#
PCI_TRDY#
PCI_FRAME#
PCI_PLOCK#
PCI_IRDY#
PCI_SERR#
PCI_PERR#
PCI_REQ3#
PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#
PCI_REQ0#
PCI_REQ1#
LVDS_CBL_DET#
CAM_CBL_DET#
PNL_BKLT_CBL_DET#
FAN1_DET#
PCI_AD[0..31]<27>
PCI_GNT3#
1 2
R194 8.2K_0402_5%~D
1 2
R195 8.2K_0402_5%~D
1 2
D D
C C
B B
R196 8.2K_0402_5%~D
1 2
R197 8.2K_0402_5%~D
1 2
R198 8.2K_0402_5%~D
1 2
R199 8.2K_0402_5%~D
1 2
R200 8.2K_0402_5%~D
1 2
R201 8.2K_0402_5%~D
1 2
R925 8.2K_0402_5%~D
1 2
R202 8.2K_0402_5%~D
1 2
R203 8.2K_0402_5%~D
1 2
R204 8.2K_0402_5%~D
1 2
R205 8.2K_0402_5%~D
1 2
R207 8.2K_0402_5%~D
1 2
R208 8.2K_0402_5%~D
+3.3V_RUN
1 2
R755 100K_0402_5%~D
1 2
R212 100K_0402_5%~D
1 2
R817 100K_0402_5%~D
1 2
R926 100K_0402_5%~D
4
PCI_PIRQC#<27>
PCI_PIRQD#<27>
12
R215
@
1K_0402_5%~D
PCI_AD0
PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD6
PCI_AD7
PCI_AD8
PCI_AD9
PCI_AD10
PCI_AD11
PCI_AD12
PCI_AD13
PCI_AD14
PCI_AD15
PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20
PCI_AD21
PCI_AD22
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30
PCI_AD31
PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#
U79B
A11
AD0
B12
A10
C12
A8
A12
E10
C11
B9
D8
A4
E8
A3
D9
C8
C2
D7
B3
D11
B6
D5
D3
F4
E3
E4
B2
C4
C1
D1
E2
J4
H2
F1
F5
F2
C7
PCI
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
Interrupt I/F
PIRQA#
PIRQB#
PIRQC#
PIRQD#
ICH9-M SFF ES_FCBGA569~D
PCI_GNT0#
REQ0#
GNT0#
REQ1#/GPIO50
GNT1#/GPIO51
REQ2#/GPIO52
GNT2#/GPIO53
REQ3#/GPIO54
GNT3#/GPIO55
C/BE0#
C/BE1#
C/BE2#
C/BE3#
IRDY#
PCIRST#
DEVSEL#
PERR#
PLOCK#
SERR#
STOP#
TRDY#
FRAME#
PLTRST#
PCICLK
PME#
PIRQE#/GPIO2
PIRQF#/GPIO3
PIRQG#/GPIO4
PIRQH#/GPIO5
12
G4
E1
A9
E12
B11
C10
D6
C6
D10
A5
E6
C9
C3
B1
PAR
T3
A7
D4
C5
H5
A6
A2
B8
A21
B5
T1
G3
G1
F3
H4
R213
1K_0402_5%~D
3
PCI_REQ0#
PCI_GNT0#
PCI_REQ1#
PCI_GNT1#
PCIE_MCARD2_DET#
ICH_GPIO53
PCI_REQ3#
PCI_GNT3#
PCI_C_BE0#
PCI_C_BE1#
PCI_C_BE2#
PCI_C_BE3#
PCI_IRDY#
PCI_PAR
PCI_PCIRST#
PCI_DEVSEL#
PCI_PERR#
PCI_PLOCK#
PCI_SERR#
PCI_STOP#
PCI_TRDY#
PCI_FRAME#
PCI_PLTRST#
CLK_PCI_ICH
ICH_PME#
LVDS_CBL_DET#
PNL_BKLT_CBL_DET#
CAM_CBL_DET#
FAN1_DET#
ICH_SPI_CS1#<24>
PCI_REQ1# <27>
PCI_GNT1# <27>
PCIE_MCARD2_DET# <21>
ICH_GPIO53 <23>
PCI_C_BE0# <27>
PCI_C_BE1# <27>
PCI_C_BE2# <27>
PCI_C_BE3# <27>
PCI_IRDY# <27>
PCI_PAR <27>
PCI_DEVSEL# <27>
PCI_PERR# <27>
PCI_SERR# <27>
PCI_STOP# <27>
PCI_TRDY# <27>
PCI_FRAME# <27>
CLK_PCI_ICH <6>
ICH_PME# <33>
LVDS_CBL_DET# <19>
CAM_CBL_DET# <19>
FAN1_DET# <18>
ICH_SPI_CS1#
12
R214
@
1K_0402_5%~D
2
PCI_PCIRST#
PCI_PLTRST#
+3.3V_ALW_ICH
14
1
P
IN1
OUT
2
IN2
G
U11A
7
74VHC08MTCX_NL_TSSOP14~D
+3.3V_ALW_ICH
14
4
P
IN1
OUT
5
IN2
G
U11B
7
74VHC08MTCX_NL_TSSOP14~D
+3.3V_ALW_ICH
14
10
P
IN1
OUT
9
IN2
G
U11C
7
74VHC08MTCX_NL_TSSOP14~D
+3.3V_ALW_ICH
14
13
P
IN1
OUT
12
IN2
G
U11D
7
74VHC08MTCX_NL_TSSOP14~D
C294
0.1U_0402_16V4Z~D
PCI_RST#
3
PLTRST1#
6
PLTRST2#
8
PLTRST3#
11
1
PCI_RST# <27,30>
PLTRST1# <10,28>
PLTRST2# <33,34>
PLTRST3# <21,32>
Place closely pin U79.B5
CLK_PCI_ICH
A16 away override strap.
PCI_GNT3#/(MDC_RST_DIS#)
A A
Low = A16 swap override enabled.
High = Default.
Boot BIOS Strap
PCI_GNT0# SPI_CS1#
*
0
1
1
R216
@
10_0402_5%~D
Boot BIOS Location
1
0
1
SPI
PCI
LPC
1 2
CLK_ICH_TERM
1
C295
@
8.2P_0402_50V8J~D
2
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
ICH9-M(1/4)
LA-4151P
22 57Fr id ay, July 04, 2008
1
1.0
of
5
D D
+3.3V_ALW_ICH
GLAN_DOCK#
12
R221 10K_0402_5%~D
CMOS settingCMOS_CLR1
Shunt
Open
Shunt
Open
C C
ICH_AZ_MCH_SDOUT<10>
ICH_AZ_MCH_SYNC<10>
ICH_AZ_MCH_RST#<10>
ICH_AZ_MCH_BITCLK<10>
B B
Clear CMOS
Keep CMOS
TPM settingME_CLR1
Clear ME RTC Registers
Keep ME RTC Registers
1
1
@
ME_CLR1 @SHORT PA DS ~ D
1 2
C298 1U_0603_10V4Z~D
1
C309
@
27P_0402_50V8J~D
2
2
1 2
R243 33_0402_5%~D
1 2
R244 33_0402_5%~D
1 2
R245 33_0402_5%~D
1 2
R246 33_0402_5%~D
2
+RTC_CELL
ICH_AZ_SDOUT
ICH_AZ_SYNC
ICH_AZ_RST#
ICH_AZ_BITCLK
32.768K_12.5P_1TJS125DJ4A420P~D
1 2
R224 20K_0402_5%~D
1 2
R225 20K_0402_5%~D
1 2
R226 1M_0402_5%~D
1
1
@
CMOS_CLR1 @SHORT PADS~D
1 2
C299 1U_0603_10V4Z~D
ICH_AZ_CODEC_BITCLK<21>
ICH_AZ_CODEC_SDOUT<21>
SATA_ODD_IRX_DTX_N1_C<26>
SATA_ODD_IRX_DTX_P1_C<26>
SATA_ODD_ITX_DRX_N1<26>
SATA_ODD_ITX_DRX_P1<26>
2
2
ICH_AZ_CO D EC_SYNC<21>
ICH_AZ_CODEC_RST#<21>
ICH_AZ_CODEC_SDIN0<21>
ICH_AZ_MCH_SDIN2<10>
ME_FWP<33>
RTC_BAT_DET#<41>
SATA_ACT#_R<38>
PSATA_IRX_DTX_N0_C<26>
PSATA_IRX_DTX_P0_C<26>
PSATA_ITX_DRX_N0<26>
PSATA_ITX_DRX_P0<26>
XOR Chain Entrance Strap
DescriptionICH_RSVD_TP3 HDA SDOUT
00
0
A A
1
11
1
0
RSVD
Enter XOR Chain
Normal Operation (Default)
Set PCIE port config bit 1
4
Package
9.6X4.06 mm
12
C296
12P_0402_50V8J~D
12
C297 12P_0402_50V8J~D
C302
@
27P_0402_50V8J~D
C307 0.01U_0402_16V7K~D
C308 0.01U_0402_16V7K~D
C310 0.01U_0402_16V7K~D
C311 0.01U_0402_16V7K~D
+3.3V_RUN
12
R248
@
1K_0402_5%~D
ICH_AZ_SDOUT
12
R249
@
1K_0402_5%~D
Y1
1 4
LAN_CLK<21>
LAN_RSTSYNC<21>
LAN_RX0<21>
LAN_RX1<21>
LAN_RX2<21>
LAN_TX0<21>
LAN_TX1<21>
LAN_TX2<21>
1
+1.5V_RUN_PCIE_ICH
2
R241 33_0402_5%~D
R235 33_0402_5%~D
R239 33_0402_5%~D
12
12
12
12
2 3
R223
0_0402_5%~D
1 2
1 2
1 2
1 2
1 2
R234 33_0402_5%~D
ICH_RSVD_TP3 <24>
ICH_RTCX1
12
R222
10M_0402_5%~D
ICH_RTCX2
ICH_RTCRST#
SRTCRST#
INTRUDER#
ICH_INTVRMEN
LAN100_SLP
LAN_CLK
LAN_RSTSYNC
LAN_RX0
LAN_RX1
LAN_RX2
LAN_TX0
LAN_TX1
LAN_TX2
GLAN_DOCK#
1 2
R232
24.9_0402_1%~D
ICH_AZ_BITCLK
ICH_AZ_SYNC
ICH_AZ_RST#
ICH_AZ_CODEC_SDIN0
ICH_AZ_MCH_SDIN2
ICH_AZ_SDOUT
ME_FWP
RTC_BAT_DET#
SATA_ACT#_R
PSATA_IRX_DTX_N0_C
PSATA_IRX_DTX_P0_C
PSATA_ITX_DRX_N0_C
PSATA_ITX_DRX_P0_C
SATA_ODD_ITX_DRX_N1_C
SATA_ODD_ITX_DRX_P1_C
3
+RTC_CELL +RTC_CELL
12
R217
332K_0402_1%~D
ICH_INTVRMEN
R219
@
0_0402_5%~D
1 2
ICH9M Internal VR Enable Strap
(Internal VR f or Vc cS us 1.05, VccSus1.5, VccCL1.5)
ICH_INTVRMEN
U79A
F25
RTCX1
G25
RTCX2
G24
RTCRST#
C24
SRTCRST#
C23
INTRUDER#
E25
INTVRMEN
D25
LAN100_SLP
G22
GLAN_CLK
D14
LAN_RSTSYNC
A14
LAN_RXD0
D12
LAN_RXD1
B14
LAN_RXD2
D13
LAN_TXD0
C13
LAN_TXD1
A13
LAN_TXD2
D15
GPIO56
H22
GLAN_COMPI
H21
GLAN_COMPO
AE7
HDA_BIT_CLK
AB7
HDA_SYNC
AA7
HDA_RST#
AB6
HDA_SDIN0
AE6
HDA_SDIN1
AC6
HDA_SDIN2
AA5
HDA_SDIN3
AC7
HDA_SDOUT
AD8
HDA_DOCK_EN#/GPIO33
AB8
HDA_DOCK_RST#/GPIO34
AC9
SATALED#
AE14
SATA0RXN
AD14
SATA0RXP
AC15
SATA0TXN
AD15
SATA0TXP
AD13
SATA1RXN
AC13
SATA1RXP
AA14
SATA1TXN
AB14
SATA1TXP
ICH9-M SFF ES_FCBGA569~D
+3.3V_RUN
12
12
Low = Internal VR Disabled
High = Internal VR Enabled(Default)
FWH0/LAD0
FWH1/LAD1
FWH2/LAD2
FWH3/LAD3
FWH4/LFRAME#
RTCLAN / GLAN
LPCCPU
LDRQ0#
LDRQ1#/GPIO23
A20GATE
A20M#
DPRSTP#
DPSLP#
FERR#
CPUPWRGD
IGNNE#
INIT#
INTR
RCIN#
NMI
SMI#
STPCLK#
THRMTRIP#
TP11
SATA4RXN
SATA4RXP
IHDA
SATA4TXN
SATA4TXP
SATA5RXN
SATA5RXP
SATA5TXN
SATA5TXP
SATA_CLKN
SATA_CLKP
SATA
SATARBIAS#
SATARBIAS
R928
@
1K_0402_5%~D
ICH_AZ_SYNC
ICH_GPIO53
R929
@
1K_0402_5%~D
ICH_GPIO53 <22>
LPC_LAD0
H3
LPC_LAD1
J3
LPC_LAD2
K5
LPC_LAD3
L3
LPC_LFRAME#
J2
LPC_LDRQ0#
H1
LPC_LDRQ1#
J1
SIO_A20GATE
N3
H_A20M#
AB23
H_DPRSTP#
AE23
H_DPSLP#
AE24
R229
AD25
AE22
AD23
AE21
AD24
L1
AD21
AC21
AC25
AC23
AC22
AD12
AE12
AB12
AA12
AC11
AD11
AB10
AA10
AC16
AB16
AD10
AE10
H_FERR#
12
56_0402_5%~D
H_PWRGOOD
H_IGNNE#
H_INIT#
H_INTR
SIO_RCIN#
H_NMI
H_SMI#
H_STPCLK#
THRMTRIP_ICH#
ICH_TP12
ESATA_IRX_DTX_N4_C
ESATA_IRX_DTX_P4_C
ESATA_ITX_DRX_N4_C
ESATA_ITX_DRX_P4_C
SATA_SBRX_DTX_N3_C
SATA_SBRX_DTX_P3_C
SATA_ITX_DRX_N3_C
SATA_ITX_DRX_P3_C
CLK_PCIE_SATA#
CLK_PCIE_SATA
R247 24.9_0402_1%~D
Within 500 mils
PCIe Port Conf ig ur ation 1 (Ports 1-4)
00
PCIe Port Conf ig ur ation 2 (Ports 1-4)
ICH_GPIO531Ports Routing
2
ICH9M LAN100 SLP Strap
(Internal VR f or Vc cL AN1.05 and VccCL1.05)
ICH_LAN100_SLP Low = In t e r n al VR Disabled
LPC_LAD0 <30,32,33,34>
LPC_LAD1 <30,32,33,34>
LPC_LAD2 <30,32,33,34>
LPC_LAD3 <30,32,33,34>
LPC_LFRAME# <30,32,33,34>
LPC_LDRQ0# <33>
LPC_LDRQ1# <33>
SIO_A20GATE <34>
H_A20M# <7>
H_FERR# <7>
H_PWRGOOD <8>
H_IGNNE# <7>
H_INIT# <7>
H_INTR <7>
SIO_RCIN# <34>
H_NMI <7>
H_SMI# <7>
H_STPCLK# <7>
T41PAD~D
C303 0.01U_0402_16V7K~D
C304 0.01U_0402_16V7K~D
C305 0.01U_0402_16V7K~D
C306 0.01U_0402_16V7K~D
12
LPC_LAD[0..3] <30,32,33,34>
12
12
12
12
+1.05V_VCCP
56_0402_1%~D
@
12
R227
Ports RoutingHDA_SYNC HDA SDOUT
Port 1(X1),Po rt 2( X1 ), Po rt 3(X1), Port 4(X1) default
11
Port 5(X1), Port 6(X1) default
1
12
R218
332K_0402_1%~D
LAN100_SLP
R220
@
0_0402_5%~D
1 2
High = Interna l V R Enabled(Default)
SIO_A20GATE
SIO_RCIN#
56_0402_1%~D
RTC_BAT_DET#
@
12
R228
H_FERR#
H_DPRSTP# <8,10,45>
H_DPSLP# <8>
+1.05V_VCCP
12
R237
56_0402_5%~D
1 2
C301
0.1U_0402_16V4Z~D
ESATA_IRX_DTX_N4_C <29>
ESATA_IRX_DTX_P4_C <29>
ESATA_ITX_DRX_N4 <29>
ESATA_ITX_DRX_P4 <29>
SATA_SBRX_DTX_N3_C <31>
SATA_SBRX_DTX_P3_C <31>
SATA_SBTX_C_DRX_N3 <31>
SATA_SBTX_C_DRX_P3 <31>
CLK_PCIE_SATA# <6>
CLK_PCIE_SATA <6>
12
R230 10K_0402_5%~D
12
R231 10K_0402_5%~D
R757 100K_0402_5%~D
1 2
12
R233 56_0402_5%~D
ICH9MSFF Straps
Port 1(X4)
+3.3V_RUN
+1.05V_VCCP
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
ICH9-M(2/4)
LA-4151P
23 57Fr id ay, July 04, 2008
1
1.0
of
+3.3V_RUN
1 2
R251 2.2K_0402_5%~D@
1 2
R254 10K_0402_5%~D@
1 2
R258 8.2K_0402_5%~D
12
R261 10K_0402_5%~D
1 2
R264 1K_0402_5%~D@
1 2
R834 100K_0402_5%~D
1 2
D D
+3.3V_LAN
+3.3V_ALW_ICH
R754 100K_0402_5%~D@
1 2
R272 10K_0402_5%~D
1 2
R270 1K_0402_5%~D@
1 2
R822 100K_0402_5%~D
5
IMVP_PWRGD
MCH_ICH_SYNC#
RSV_THRM#
IRQ_SERIRQ
SPKR
SPEAKER_DET#
SNIFFER_DET#
SIO_EXT_SCI#
ICH_EC_SPI_DO
CONTACTLESS_DET#
+3.3V_ALW_ICH
R252 2.2K_0402_5%~D
R255 2.2K_0402_5%~D
R259 10K_0402_5%~D@
R262 10K_0402_5%~D
R265 10K_0402_5%~D
R267 10K_0402_5%~D
R268 10K_0402_5%~D
R269 10K_0402_5%~D
R274 10K_0402_5%~D
R787 10K_0402_5%~D8@
R192 10K_0402_5%~D
R1065 10K_0402_5%~D@
R1111 10K_0402_5%~D1@
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
ICH_SMBDATA
ICH_CL_RST1#
AMT_SMBCLK
AMT_SMBDAT
ICH_RI#
ICH_PCIE_W AKE#
12
ME_SUS_PWR_ACK
12
SIO_EXT_SMI#
ICH_GPIO60
SMB_ALERT#
LAN_DISABLE#
ICH_GPIO60
ICH_SMBCLK
1 2
iTPM function
No stuff = Disable
R270
Stuff = Enable
SIO_EXT_WAKE#<33>
No Reboot Strap
Low = Default
SPKR
High = No Reboot
C C
+3.3V_RUN
12
R282
8.2K_0402_5%~D
CLKRUN#
12
R283
@
10_0402_5%~D
Option to " Disable "
clkrun. Pulling it
down
will keep the clks
running.
MiniWWAN (Mini Card 1)--->
+3.3V_ALW_ICH
RP1
10K_1206_8P4R_5%~D
B B
A A
RP2
10K_1206_8P4R_5%~D
1 2
R288 10K_0402_5%~D
1 2
R291 10K_0402_5%~D
1 2
R293 10K_0402_5%~D
ICH_SPI_CS0#
ICH_EC_SPI_DIN
1 2
R1108 0_0402_5%~D
SPI_WP#_SEL
For iAMT
ICH_SPI_CS1#
1 2
R1109 0_0402_5%~D@
SPI_WP#_SEL
MiniWLAN (Mini Card 2)--->
USB_OC0_1#
45
USB_OC2#
36
ESATA_USB_OC#
27
USB_OC4#
18
USB_OC5#
45
USB_OC6#
36
USB_OC7#
27
USB_OC11#
18
USB_OC9#
USB_OC10#
USB_OC8#
+3.3V_LAN
12
R298
3.3K_0402_5%~D
SPI_DIN_R1
1 2
R300
33_0402_5%~D
SPI_WP#_SEL <33>
+3.3V_LAN
12
@
R304
3.3K_0402_5%~D
R306
@
1 2
SPI_WE#
33_0402_5%~D
SPI_DIN_R2 SPI_AMT_HOLD#ICH_SPI_DIN_R
SPI_AMT_WE#
GPIO6
GPIO60
00
001
1
11
Express card--->
10/100/1G LAN --->
200 MIL SO8
Flash ROM
SA00001OZ0L
U12
4@
1
/CS
2
DO
3
/WP
GND4DIO
W25X32VSSIG_SO8~D
U13
@
1
CS#
2
SO
3
WP#
4
GND
W25X16-VSSIG_SO8~D
5
Function
TCM
RSVD
No TPM or TCM
TPM
1 2
R811 100K_0402_5%~D@
1 2
R789 1K_0402_5%~D@
8
VCC
SPI_HOLD#
7
/HOLD
SPI_CLK_R1
6
CLK
SPI_DO_R1
5
8
VCC
7
HOLD#
6
SCLK
5
SI
PCIE_IRX_WANTX_N1<21>
PCIE_IRX_WANTX_P1<21>
PCIE_ITX_WANRX_N1_C<21>
PCIE_ITX_WANRX_P1_C<21>
PCIE_IRX_WLANTX_N2<21>
PCIE_IRX_WLANTX_P2<21>
PCIE_ITX_WLANRX_N2_C<21>
PCIE_ITX_WLANRX_P2_C<21>
PCIE_IRX_EXPTX_N4<28>
PCIE_IRX_EXPTX_P4<28>
PCIE_ITX_EXPRX_N4_C<28>
PCIE_ITX_EXPRX_P4_C<28>
PCIE_IRX_GLANTX_N6<21>
PCIE_IRX_GLANTX_P6<21>
PCIE_ITX_GLANRX_N6_C<21>
PCIE_ITX_GLANRX_P6_C<21>
R309 33_0402_5%~D @
ITP_DBRESET#
DMI_TERM_SEL
4@
12
R299
3.3K_0402_5%~D
R301 33_0402_5%~D
1 2
1 2
R302 33_0402_5%~D
12
@
R305
3.3K_0402_5%~D
R308
@
1 2
1 2
+3.3V_RUN
100K_0402_5%~D
1 2
TPM_ID
100K_0402_5%~D
1 2
1
2
ICH_SPI_CS1#<22>
C328
1 2
0.1U_0402_16V4Z~D
ICH_EC_SPI_CLK
ICH_EC_SPI_DO
C329 0.1U_0402_16V4Z~D@
1 2
33_0402_5%~D
ICH_EC_SPI_CLKSPI_CLK_R2
ICH_EC_SPI_DOSPI_DO_R2
4
3@
R987
AMT_SMBCLK<34>
AMT_SMBDAT<34>
7@
R988
47P_0402_50V8J~D
4
@
C313
USB_MCARD1_DET#<21>
T163PAD~D
ITP_DBRESET#<7>
PM_SYNC#<10>
H_STP_PCI#<6>
H_STP_CPU#<6>
CLKRUN#<27,30,33,34>
ICH_PCIE_WAKE#<33>
IRQ_SERIRQ<27,30,32,33,34>
IMVP_PWRGD<33,37,45,47>
SIO_EXT_SCI#<34>
SIO_EXT_SMI#<34>
LAN_DISABLE#<21>
CONTACTLESS_DET#<32>
USB_MCARD2_DET#<21>
SATA_CLKREQ#<6>
ODD_DET#<26>
HDD_DET#<26>
SPKR<21>
MCH_ICH_SYNC#<10>
ICH_RSVD_TP3<23>
C317 0.1U_0402_10V7K~D
1 2
C319 0.1U_0402_10V7K~D
1 2
C320 0.1U_0402_10V7K~D
1 2
C321 0.1U_0402_10V7K~D
1 2
C1008 0.1U_0402_10V7K~D
1 2
C1009 0.1U_0402_10V7K~D
1 2
C326 0.1U_0402_10V7K~D
1 2
C327 0.1U_0402_10V7K~D
1 2
ICH_SPI_CS0# ICH_ SP I_ C S 0#_R
ESATA_USB_OC#<29>
Follow Daisy Chain and Star
Topology. Place close to U10
pinE23 within 500mils
T45PAD~D
CONTACTLESS_DET#
T132PAD~D
T48PAD~D
T50PAD~D
T51PAD~D
T52PAD~D
R294
33_0402_5%~D
1 2
1 2
R295
33_0402_5%~D
USB_OC0_1#<21>
1 2
R307 0_0402_5%~D
ICH_SMBCLK
ICH_SMBDATA
ICH_GPIO60
AMT_SMBCLK
AMT_SMBDAT
ICH_RI#
SUS_STAT#/LPCPD#
ITP_DBRESET#
PM_SYNC#
SMB_ALERT#
H_STP_PCI#
H_STP_CPU#
CLKRUN#
ICH_PCIE_W AKE#
IRQ_SERIRQ
RSV_THRM#
IMVP_PWRGD
ICH_TP11
SIO_EXT_SCI#
TPM_ID
SIO_EXT_SMI#
LAN_DISABLE#
SNIFFER_DET#
ICH_GPIO20
SATA_CLKREQ#
ODD_DET#
WPAN_RADIO_DIS_MINI#
HDD_DET#
DMI_TERM_SEL
SPKR
MCH_ICH_SYNC#
ICH_RSVD_TP3
ICH_TP8
ICH_TP9
ICH_TP10
PCIE_IRX_WANTX_N1
PCIE_IRX_WANTX_P1
PCIE_ITX_WANRX_N1
PCIE_ITX_WANRX_P1
PCIE_IRX_WLANTX_N2
PCIE_IRX_WLANTX_P2
PCIE_ITX_WLANRX_N2
PCIE_ITX_WLANRX_P2
PCIE_IRX_EXPTX_N4
PCIE_IRX_EXPTX_P4
PCIE_ITX_EXPRX_N4
PCIE_ITX_EXPRX_P4
PCIE_IRX_GLANTX_N6
PCIE_IRX_GLANTX_P6
PCIE_ITX_GLANRX_N6
PCIE_ITX_GLANRX_P6
ICH_EC_SPI_CLK
ICH_SPI_CS1#_RICH_SPI_CS1#
ICH_EC_SPI_DO
USB_OC0_1#
USB_OC2#
ESATA_USB_OC#
USB_OC4#
USB_OC5#
USB_OC6#
USB_OC7#
USB_OC8#
USB_OC9#
USB_OC10#
USB_OC11#
R303
22.6_0402_1%~D
Within 500 mils
12
ICH_SPI_DIN_RICH_EC_SPI_DIN
U79C
C18
SMBCLK
C15
SMBDATA
B21
LINKALERT#/GPIO60/CLGPIO4
E18
SMLINK0
A24
SMLINK1
C20
RI#
T5
SUS_STAT#/LPCPD#
C25
SYS_RESET#
L2
PMSYNC#/GPIO0
A23
SMBALERT#/GPIO11
B15
STP_PCI#/GPIO15
A20
STP_CPU#/GPIO25
M5
CLKRUN#/GPIO32
C21
WAKE#
L4
SERIRQ
AD20
THRM#
B24
VRMPWRGD
A19
TP12
AE16
GPIO1
AE18
GPIO6
AD18
GPIO7
B25
GPIO8
C14
GPIO12
D20
GPIO13
AE17
GPIO17
K3
GPIO18
AC8
GPIO20
AC19
SCLOCK/GPIO22
D17
GPIO27
E20
GPIO28
M4
SATACLKREQ#/GPIO35
AB18
SLOAD/GPIO38
AC18
SDATAOUT0/GPIO39
AB19
SDATAOUT1/GPIO48
AC20
GPIO49
A16
GPIO57/CLGPIO5
K4
SPKR
AB20
MCH_SYNC#
C19
TP3
AB17
TP8
AC17
TP9
AD17
TP10
ICH9-M SFF ES_FCBGA569~D
USBRBIAS
3
1 2
R256 8.2K_0402_5%~D
CLK14
CLK48
SUSCLK
SLP_S3#
SLP_S4#
SLP_S5#
PWROK
BATLOW#
PWRBTN#
LAN_RST#
RSMRST#
CK_PWRGD
CLPWROK
SLP_M#
CL_CLK0
CL_CLK1
CL_DATA0
CL_DATA1
CL_VREF0
CL_VREF1
CL_RST0#
CL_RST1#
V25
V24
U24
U23
W23
W24
V21
V22
Y24
Y25
Y21
Y22
AB24
AB25
AA23
AA24
T21
T22
AB21
AB22
AE2
AD1
AD3
AD4
AC2
AC3
AC5
AB4
AB2
AB1
AA3
AA2
Y1
Y2
W2
W3
V1
V2
Y5
Y4
U3
U2
V4
V5
AE19
AA18
AE20
AA20
K1
AB5
R3
D18
B20
D16
E14
D23
M1
C16
U4
D22
D19
U1
T4
B23
C22
A18
E22
B18
F21
A17
C17
B17
A22
E16
A15
D21
R284
@
10K_0402_5%~D
DMI_MTX_IRX_N0
DMI_MTX_IRX_P0
DMI_MRX_ITX_N0
DMI_MRX_ITX_P0
DMI_MTX_IRX_N1
DMI_MTX_IRX_P1
DMI_MRX_ITX_N1
DMI_MRX_ITX_P1
DMI_MTX_IRX_N2
DMI_MTX_IRX_P2
DMI_MRX_ITX_N2
DMI_MRX_ITX_P2
DMI_MTX_IRX_N3
DMI_MTX_IRX_P3
DMI_MRX_ITX_N3
DMI_MRX_ITX_P3
CLK_PCIE_ICH#
CLK_PCIE_ICH
DMI_IRCOMP
USBP0-
USBP0+
USBP1USBP1+
USBP3USBP3+
USBP4USBP4+ICH_EC_SPI_DIN
USBP5USBP5+
USBP6USBP6+
USBP7USBP7+
USBP8USBP8+
USBP9USBP9+
USBP10USBP10+
USBP11USBP11+
SPEAKER_DET#
BT_DET#
CLK_ICH_14M
CLK_ICH_48M
ICH_SUSCLK
SIO_SLP_S3#
SIO_SLP_S4#
SIO_SLP_S5#
ICH_GPIO26
ICH_PWRGD
DPRSLPVR
ICH_BATLOW#
SIO_PWRBTN#
ICH_LAN_RST#
ICH_RSMRST#
CLK_PWRGD
ICH_CL_PWROK
SIO_SLP_M#
CL_CLK0
ICH_CL_CLK1
CL_DATA0
ICH_CL_DATA1
+CL_VREF0_ICH
+CL_VREF1_ICH
CL_RST0#
ICH_CL_RST1#
PCIE_MCARD1_DET#
ME_SUS_PWR_ACK
AC_PRESENT
ME_WOL_EN
1 2
SATA0GP/GPIO21
SATA1GP/GPIO19
SATA4GP/GPIO36
SATA5GP/GPIO37
SATA
GPIO
SMB
Clocks
S4_STATE#/GPIO26
DPRSLPVR/GPIO16
SYS GPIO
Power MGTController Link
GPIO
MEM_LED/GPIO24
GPIO10/SUS_PWR_ACK
GPIO14/AC_PRESENT
WOL_EN/GPIO9
MISC
U79D
T25
PERN1
T24
PERP1
R24
PETN1
R23
PETP1
P25
PERN2
P24
PERP2
P21
PETN2
P22
PETP2
N23
PERN3
N24
PERP3
M21
PETN3
M22
PETP3
M25
PERN4
M24
PERP4
L24
PETN4
L23
PETP4
K24
PERN5
K25
PERP5
K21
PETN5
K22
PETP5
H24
PERN6/GLAN_RXN
H25
PERP6/GLAN_RXP
J24
PETN6/GLAN_TXN
J23
PETP6/GLAN_TXP
E24
SPI_CLK
E23
SPI_CS0#
F23
SPI_CS1#/GPIO58/CLGPIO6
F22
SPI_MOSI
G23
SPI_MISO
P4
OC0#/GPIO59
N4
OC1#/GPIO40
N1
OC2#/GPIO41
P5
OC3#/GPIO42
P1
OC4#/GPIO43
P2
OC5#/GPIO29
M3
OC6#/GPIO30
M2
OC7#/GPIO31
P3
OC8#/GPIO44
R1
OC9#/GPIO45
R4
OC10#/GPIO46
R2
OC11#/GPIO47
AE5
USBRBIAS
AD5
USBRBIAS#
ICH9-M SFF ES_FCBGA569~D
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
PCI-Express
USB
DMI0RXN
DMI0RXP
DMI0TXN
DMI0TXP
DMI1RXN
DMI1RXP
DMI1TXN
DMI1TXP
DMI2RXN
DMI2RXP
DMI2TXN
DMI2TXP
DMI3RXN
DMI3RXP
DMI3TXN
DMI3TXP
DMI_CLKN
DMI_CLKP
Direct Media Interface
DMI_ZCOMP
DMI_IRCOMP
USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4N
USBP4P
USBP5N
SPI
USBP5P
USBP6N
USBP6P
USBP7N
USBP7P
USBP8N
USBP8P
USBP9N
USBP9P
USBP10N
USBP10P
USBP11N
USBP11P
2
+3.3V_RUN
R275 8.2K_0402_5%~D
DMI_MTX_IRX_N0 <10>
DMI_MTX_IRX_P0 <10>
DMI_MRX_ITX_N0 <10>
DMI_MRX_ITX_P0 <10>
DMI_MTX_IRX_N1 <10>
DMI_MTX_IRX_P1 <10>
DMI_MRX_ITX_N1 <10>
DMI_MRX_ITX_P1 <10>
DMI_MTX_IRX_N2 <10>
DMI_MTX_IRX_P2 <10>
DMI_MRX_ITX_N2 <10>
DMI_MRX_ITX_P2 <10>
DMI_MTX_IRX_N3 <10>
DMI_MTX_IRX_P3 <10>
DMI_MRX_ITX_N3 <10>
DMI_MRX_ITX_P3 <10>
CLK_PCIE_ICH# <6>
CLK_PCIE_ICH <6>
Within 500 mils
1 2
R292 24.9_0402_1%~D
USBP0- <21>
USBP0+ <21>
USBP1- <40>
USBP1+ <40>
USBP3- <29>
USBP3+ <29>
USBP4- <21>
USBP4+ <21>
USBP5- <40>
USBP5+ <40>
USBP6- <30>
USBP6+ <30>
USBP7- <28>
USBP7+ <28>
USBP8- <31>
USBP8+ <31>
USBP9- <31>
USBP9+ <31>
USBP10- <32>
USBP10+ <32>
USBP11- <19>
USBP11+ <19>
2
SPEAKER_DET# <29>
BT_DET# <30>
CLK_ICH_14M <6>
CLK_ICH_48M <6>
T44 PAD~D
SIO_SLP_S3# <33>
SIO_SLP_S4# <10,34>
SIO_SLP_S5# <34>
T130
ICH_PWRGD <10,37>
DPRSLPVR <10,45>
SIO_PWRBTN# <34>
ICH_LAN_RST# <34>
ICH_RSMRST# <34>
CLK_PWRGD <6>
ICH_CL_PWROK <10,34>
SIO_SLP_M# <34>
CL_CLK0 <10>
ICH_CL_CLK1 <21>
CL_DATA0 <10>
ICH_CL_DATA1 <21>
CL_RST0# <10>
ICH_CL_RST1# <21>
PCIE_MCARD1_DET# <21>
ME_SUS_PWR_ACK <34>
AC_PRESENT <34>
ME_WOL_EN <34>
+3.3V_ALW_ICH
+1.5V_RUN_PCIE_ICH
CLK_ICH_48M
12
R285
10_0402_5%~D
1
C318
4.7P_0402_50V8C~D
2
PAD~D
12
+3.3V_ALW_ICH
----->Right Side Top
----->BLT mode
----->Left Side Top
----->WLAN
----->WWAN
----->BT
----->Express Card
ICH_SMBDATA
----->DOCK
----->DOCK
----->BIO
+3.3V_M
ICH_SMBCLK
-----Camera
DELL CONFIDENTIAL/PROPRIETARY
Title
Size Document Number Rev
Date: Sheet
ICH_LAN_RST#
SPI_WE#
SPI_DIN_R1
ICH_SPI_CS0#
+3.3V_M
6 1
3
LA-4151P
1
BT_DET#
ODD_DET#
HDD_DET#
ICH_CL_PWROK
DPRSLPVR
ICH_PWRGD
ICH_RSMRST#
Place closely pin U79.AB5
ME_WOL_EN
+3.3V_ALW_ICH
10K_0402_5%~D
@
R271
1 2
10K_0402_5%~D
R276
1 2
2@
2
4
6
8
10
12
14
16
18
TYCO_5-1775013-4~D
+CL_VREF1_ICH
1
C324
2
2.2K_0402_5%~D
12
Q27A
2N7002DW-T/R7_SOT363-6~D
2
5
4
Q27B
2N7002DW-T/R7_SOT363-6~D
1 2
R836 100K_0402_5%~D
R760 100K_0402_5%~D
1 2
R759 100K_0402_5%~D
1 2
R250 100K_0402_5%~D
1 2
R253 100K_0402_5%~D@
1 2
R257 10K_0402_5%~D
1 2
R260 10K_0402_5%~D
1 2
R263 100K_0402_5%~D
Place closely pin U79.K1
CLK_ICH_14M
12
R279
10_0402_5%~D
1
C312
4.7P_0402_50V8C~D
2
JP6
112
334
556
778
9910
111112
G113G2
G315G4
G517G6
The same MDC connector
for TAA module
TYCO_1-179373-2
+3.3V_WLAN
12
R286
+CL_VREF0_ICH
3.24K_0402_1%~D
12
R289
453_0402_1%~D
0.1U_0402_16V4Z~D
2.2K_0402_5%~D
12
R296
R297
MEM_SDATA
MEM_SCLK
Compal Electronics, Inc.
ICH9-M(3/4)
1
+3.3V_RUN
12
SPI_DO_R1
SPI_CLK_R1
SPI_HOLD#
+3.3V_LAN
+3.3V_M
12
12
1
C325
2
0.1U_0402_16V4Z~D
MEM_SDATA <16,17>
MEM_SCLK <16,17>
24 57Fr id ay, July 04, 2008
of
R287
R290
3.24K_0402_1%~D
453_0402_1%~D
1.0
5
4
3
2
1
+RTC_CELL
+1.5V_RUN_PCI E _I CH
L13
1 2
1
C330
2
+1.5V_RUN_ PCI E _I CH
220U_D2_4VY_R15M~D
1
+
C336
2
+1.5V_RUN_SATAPLL
10U_0805_4VAM~D
+3.3V_RUN+5V_RUN
12
21
R311
100_0402_5%~D
D D
R313
100_0402_5%~D
C C
+3.3V_ALW_ICH+5V_ALW
12
+1.5V_RUN
D15
RB751S40T1_SOD523-2~D
ICH_V5REF_RUN
1
C335
1U_0603_10V6K~D
2
21
D16
RB751S40T1_SOD523-2~D
ICH_V5REF_SUS
1
C342
1U_0603_10V6K~D
2
+1.5V_RUN
BLM21PG600SN1D_0805~D
L16
10UH_LB2012T100MR_20%_0805~D
1 2
1
2
B B
0.1U_0402_16V4Z~D
1
C365
+3.3V_LAN
A A
0.1U_0402_16V4Z~D
1
C367
2
1 2
L17
1UH_20%_0805~D
5
2
C370
0.1U_0402_16V4Z~D
+VCCGLANPLL+1.5V_RUN
2.2U_0603_6.3V6K~D
10U_0805_4VAM~D
1
1
2
C372
C371
2
1
2
C350
1 2
@
1
C332
C331
2
ICH_V5REF_RUN
ICH_V5REF_SUS
2.2U_0603_6.3V6K~D
22U_0805_6.3V6M~D
22U_0805_6.3V6M~D
1
C337
2
1
1
C338
2
2
U79F
G17
VCCRTC
G7
V5REF
U7
V5REF_SUS
J19
VCC1_5_B[01]
K18
VCC1_5_B[02]
K19
VCC1_5_B[03]
L18
VCC1_5_B[04]
L19
VCC1_5_B[05]
M18
C339
M19
N18
N19
P18
R18
T18
T19
U18
U19
VCC1_5_B[06]
VCC1_5_B[07]
VCC1_5_B[08]
VCC1_5_B[09]
VCC1_5_B[10]
VCC1_5_B[11]
VCC1_5_B[12]
VCC1_5_B[13]
VCC1_5_B[14]
VCC1_5_B[15]
CORE
VCC1_05[01]
VCC1_05[02]
VCC1_05[03]
VCC1_05[04]
VCC1_05[05]
VCC1_05[06]
VCC1_05[07]
VCC1_05[08]
VCC1_05[09]
VCC1_05[10]
VCC1_05[11]
VCC1_05[12]
VCC1_05[13]
VCC1_05[14]
VCC1_05[15]
VCC1_05[16]
VCCDMIPLL
VCC_DMI[1]
VCC_DMI[2]
V_CPU_IO[1]
V_CPU_IO[2]
VCC3_3[01]
VCCA3GP ATXARX USB CORE
VCC3_3[02]
1U_0603_10V4Z~D
1
C351
2
W17
VCCSATAPLL
1U_0603_10V4Z~D
1
C358
2
1
2
0.1U_0402_16V4Z~D
1
C364
2
+1.5V_RUN
1U_0603_10V4Z~D
1
2
VCCLAN1.05_INT_ICH
4.7U_0603_6.3V6M~D
1
+3.3V_RUN
C373
2
4
U13
VCC1_5_A[01]
V13
VCC1_5_A[02]
W13
VCC1_5_A[03]
U12
1U_0603_10V4Z~D
C359
C1111
VCC1_5_A[04]
V12
VCC1_5_A[05]
W12
VCC1_5_A[06]
W10
VCC1_5_A[07]
U15
VCC1_5_A[08]
V15
VCC1_5_A[09]
W18
VCC1_5_A[10]
G9
VCC1_5_A[11]
H9
VCC1_5_A[12]
V11
VCC1_5_A[13]
U11
VCC1_5_A[14]
U8
VCCUSBPLL
T9
VCC1_5_A[15]
U9
VCC1_5_A[16]
G11
VCCLAN1_05[1]
H11
VCCLAN1_05[2]
G12
VCCLAN3_3[1]
H13
VCCLAN3_3[2]
J17
VCCGLANPLL
H19
VCCGLAN1_5[1]
J18
VCCGLAN1_5[2]
K16
VCCGLAN3_3
ICH9-M SFF ES_FC BGA 569~D
VCCPSUSVCCPUSB
GLAN POWER
VCC3_3[03]
VCC3_3[04]
VCC3_3[05]
VCC3_3[06]
VCC3_3[07]
VCC3_3[08]
VCCP_CORE
PCI
VCCSUSHDA
VCCSUS1_05[1]
VCCSUS1_05[2]
VCCSUS1_5[1]
VCCSUS1_5[2]
VCCSUS3_3[01]
VCCSUS3_3[02]
VCCSUS3_3[03]
VCCSUS3_3[04]
VCCSUS3_3[05]
VCCSUS3_3[06]
VCCSUS3_3[07]
VCCSUS3_3[08]
VCCSUS3_3[09]
VCCSUS3_3[10]
VCCSUS3_3[11]
VCCSUS3_3[12]
VCCSUS3_3[13]
VCCSUS3_3[14]
VCCSUS3_3[15]
VCCSUS3_3[16]
VCCCL1_05
VCCCL1_5
VCCCL3_3[1]
VCCCL3_3[2]
+1.05V_VCCP
L11
L12
L13
L14
L15
M11
M15
N11
N15
P11
P15
R11
R12
R13
R14
R15
P19
T17
U17
V16
U16
0.1U_0402_16V4Z~D
1
2
+VCCDMIPLL
+VCC_DMI_ICH
0.1U_0402_16V4Z~D
1
C333
C334
2
0.01U_0402_16V7K~D
10U_0805_4VAM~D
1
1
C340
2
2
4.7U_0603_6.3V6M~D
1
C343
2
V18
AE9
AA9
V14
W14
G8
H7
H8
+1.5V_RUN
AD7
VCCHDA
V10
T7
H15
H16
V7
G14
G15
H14
W8
J7
J8
K7
K8
L7
L8
M7
M8
N7
N8
P7
P8
G18
H17
J14
K14
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
+3.3V_RUN
C349
1 2
0.1U_0402_16V4Z~D
C352
0.1U_0402_16V4Z~D
1 2
TP_VCCSUS1.05_INT_ICH1
TP_VCCSUS1.05_INT_ICH2
VCCSUS1_5_ICH_1
VCCSUS1_5_ICH_2
0.022U_0402_16V7K~D
1
C361
2
VCCCL1_05_ICH
C366 0.1U_0402_16V4Z~D
VCCCL1_5
+3.3V_LAN
1
2
1 2
0.1U_0402_16V4Z~D
1
2
T91
+3.3V_ALW_ICH
0.1U_0402_16V4Z~D
0.022U_0402_16V7K~D
1
C362
2
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
1U_0603_10V4Z~D
+1.05V_VCCP
L14
BLM18PG181SN1_0603~D
1 2
C341
5ohm@100MHz
1 2
L15
BLM18PG181SN1_0603~D
+3.3V_RUN
0.1U_0402_16V4Z~D
+3.3V_RUN
1
C348
2
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
1
1
C354
C353
2
2
T53
T122
+3.3V_ALW_ICH
C363
0.1U_0402_16V4Z~D
1U_0603_10V4Z~D
1
1
C369
C368
2
2
D14
2
3
MMBD4148-7-F_SOT23-3~D
R312
1_0603_1%~D
+1.05V_VCCP
0.1U_0402_16V4Z~D
1
C347
2
+3.3V_RUN
C355
+1.5V_ALW_HDA
PAD~D
PAD~D
1
C360
0.1U_0402_16V4Z~D
2
1
+1.5V_RUN
12
4.7U_0603_6.3V6M~D
1
C344
2
2
C357
0.1U_0402_16V4Z~D
1
2
+1.05V_1.5V_PSEQ
+1.05V_VCCP
0.1U_0402_16V4Z~D
1
1
C345
2
2
0.1U_0402_16V4Z~D
C346
+1.5V_RUN
R310
1 2
10_0805_5%~D
DELL CONFIDENTIAL/PROPRIETARY
Title
Size Document Number Rev
LA-4151P
Date: Sheet
U79E
B4
VSS[001]
B7
VSS[002]
B10
VSS[003]
B13
VSS[004]
B16
VSS[005]
B19
VSS[006]
B22
VSS[007]
D2
VSS[008]
D24
VSS[009]
E5
VSS[010]
E7
VSS[011]
E9
VSS[012]
E11
VSS[013]
E13
VSS[014]
E15
VSS[015]
E17
VSS[016]
E19
VSS[017]
E21
VSS[018]
F24
VSS[019]
G2
VSS[020]
G5
VSS[021]
G10
VSS[022]
G13
VSS[023]
G16
VSS[024]
G19
VSS[025]
G21
VSS[026]
H10
VSS[027]
H12
VSS[028]
H18
VSS[029]
H23
VSS[030]
J5
VSS[031]
J9
VSS[032]
J10
VSS[033]
J11
VSS[034]
J12
VSS[035]
J13
VSS[036]
J15
VSS[037]
J21
VSS[038]
J22
VSS[039]
J25
VSS[040]
K2
VSS[041]
K9
VSS[042]
K10
VSS[043]
K11
VSS[044]
K12
VSS[045]
K13
VSS[046]
K15
VSS[047]
K17
VSS[048]
K23
VSS[049]
L5
VSS[050]
L9
VSS[051]
L10
VSS[052]
L16
VSS[053]
L17
VSS[054]
L21
VSS[055]
L22
VSS[056]
L25
VSS[057]
M9
VSS[058]
M10
VSS[059]
M12
VSS[060]
M13
VSS[061]
M14
VSS[062]
M16
VSS[063]
M17
VSS[064]
M23
VSS[065]
N2
VSS[066]
N5
VSS[067]
N9
VSS[068]
N10
VSS[069]
N12
VSS[070]
N13
VSS[071]
N14
VSS[072]
N16
VSS[073]
N17
VSS[074]
N21
VSS[075]
N22
VSS[076]
N25
VSS[077]
P9
VSS[078]
P10
VSS[079]
P12
VSS[080]
P13
VSS[081]
P14
VSS[082]
P16
VSS[083]
P17
VSS[084]
P23
VSS[085]
R5
VSS[086]
R7
VSS[087]
R8
VSS[088]
R9
VSS[089]
R10
VSS[090]
R16
VSS[091]
R17
VSS[092]
R19
VSS[093]
R21
VSS[094]
R22
VSS[095]
R25
VSS[096]
T2
VSS[097]
T8
VSS[098]
T10
VSS[099]
T11
VSS[100]
T12
VSS[101]
T13
VSS[102]
T14
VSS[103]
T15
VSS[104]
T16
VSS[105]
T23
VSS[106]
ICH9-M SFF ES_FC BGA 569~D
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
VSS[159]
VSS[160]
VSS[161]
VSS[162]
VSS[163]
VSS[164]
VSS[165]
VSS[166]
VSS[167]
VSS[168]
VSS[169]
VSS_NCTF[01]
VSS_NCTF[02]
VSS_NCTF[03]
VSS_NCTF[04]
Compal Electronics, Inc.
ICH9-M(4/4)
25 57Friday, Jul y 04, 2008
1
U5
U10
W11
U14
W16
U21
U22
U25
V3
V8
V19
V23
W1
W4
W5
W7
W9
W15
W19
W21
W22
W25
Y3
Y23
AA1
AA4
AA6
AA8
AA11
AA13
AA15
AA16
AA17
AA19
AA21
AA22
AA25
AB3
AB9
AB11
AB13
AB15
AC24
AC1
AC4
AC10
AC12
AC14
AD2
AD6
AD9
AD16
AD19
AD22
AE3
AE4
AE11
AE13
AE15
V17
AE8
V9
J16
A1
A25
AE1
AE25
of
1.0
5
4
3
2
1
D D
C374 0.01U_0402_16V7K~D
C375 0.01U_0402_16V7K~D
SATA_ODD_ITX_DRX_P1
SATA_ODD_ITX_DRX_N1
SATA_ODD_IRX_DTX_N1
12
SATA_ODD_IRX_DTX_P1
12
ODD_DET#<24>
+5V_MOD
ODD_DET#
+5V_MOD
1
2
SATA_ODD_ITX_DRX_P1<23>
1000P_0402_50V7K~D
0.1U_0402_16V4Z~D
1
C376
C377
2
SATA_ODD_ITX_DRX_N1<23>
SATA_ODD_IRX_DTX_N1_C<23>
SATA_ODD_IRX_DTX_P1_C<23>
close SATA connector
Pleace near ODD CONN
PSATA_ITX_DRX_P0<23>
PSATA_ITX_DRX_N0<23>
PSATA_IRX_DTX_N0_C<23>
C C
+5V_HDD +3.3V_HDD
0.1U_0402_16V4Z~D
1000P_0402_50V7K~D
1
1
C385
C384
2
2
PSATA_IRX_DTX_P0_C<23>
0.1U_0402_16V4Z~D
10U_0805_10V4Z~D
@
@
1
1
C387
C386
2
2
PSATA_ITX_DRX_P0
PSATA_ITX_DRX_N0
C380 0.01U_0402_16V7K~D
C381 0.01U_0402_16V7K~D
close SATA connector
0.1U_0402_10V7K~D
@
1
C388
2
12
12
HDD_DET#<24>
PSATA_IRX_DTX_N0
PSATA_IRX_DTX_P0
+3.3V_HDD
HDD_DET#
+5V_HDD
Pleace near HDD CONN
For ODD
JSATA1
1
GND
2
RX+
3
RX-
4
GND
5
TX-
6
TX+
7
GND
8
DP
9
+5V
10
+5V
11
MD
12
GND
13
GND
TYCO_2-1759838-5_NR~D
Main SATA +5V Default
For HDD
JSATA2
1
GND
2
RX+
3
RX-
4
GND
5
TX-
6
TX+
7
GND
8
3.3V
9
3.3V
10
3.3V
11
GND
12
GND
13
GND
14
5V
15
5V
16
5V
17
GND
18
Reserved
19
GND
20
12V
21
12V
22
12V
TYCO_1775770-1_RV
Main SATA +5V Default
GND1
GND2
GND1
GND2
14
15
23
24
MODC_EN<33>
100K_0402_5%~D
HDDC_EN<33>
100K_0402_5%~D
100K_0402_5%~D
12
R319
100K_0402_5%~D
12
R323
R317
2
+3.3V_ALW2
R321
2
+3.3V_ALW2
12
61
+5VMOD Source
12
5
2N7002DW-T/R7_SOT363-6
61
Q31A
+15V_ALW
12
Q34A
5
HDD_EN_5V
3
4
2N7002DW-T/R7_SOT363-6
12
R316
100K_0402_5%~D
2
MOD_EN
2N7002DW-T/R7_SOT363-6
3
Q31B
4
HDD PWR
R320
100K_0402_5%~D
2N7002DW-T/R7_SOT363-6
Q34B
1
2
+5V_ALW+15V_ALW
2
1
G
3
0.1U_0603_50V4Z~D
4 5
1
C378
1
2
2
+5V_ALW
6
2
1
D
Q32
G
SI3456BDV-T1-E3_TSOP6~D
3
S
+5V_HDD
4 5
0.1U_0603_50V4Z~D
10U_0805_10V4Z~D
1
C382
C383
2
+5V_HDD Source
+3.3V_ALW
6
D
Q29
SI3456BDV-T1-E3_TSOP6~D
S
+5V_MOD
1 2
100K_0402_5%~D
10U_0805_10V4Z~D
12
R318
C379
PJP3
1 2
100K_0402_5%~D
PAD-OPEN 4x4m@
12
R322
Open
PJP2
PAD-OPEN 4x4m@
Open
+5V_RUN
+5V_RUN
6
2
1
D
Q117
B B
3
G
4 5
1
2
SI3456BDV-T1-E3_TSOP6~D
S
+3.3V_HDD
1 2
10U_0805_10V4Z~D
100K_0402_5%~D
12
R477
C79
PJP47
PAD-OPEN 4x4m@
Open
+3.3V_RUN
+3.3V_HDD Source
A A
DELL CONFIDENTIAL/PROPRIETA RY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
5
4
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
ODD/HDD CONNECTOR
LA-4151P
26 57Friday, July 04, 2008
1
1.0
of
5
PCI_AD[0..31]<22>
+3.3V_R5C833
D D
CLK_PCI_PCM
R803
C1057
PCI_AD17
CLKRUN#<24,30,33,34>
+3.3V_R5C833
1 2
0_0402_5%~D@
PCI_PIRQD#<22>
PCI_PIRQC#<22>
R808 0_0402_5%~D
CBUS_GRST#<33>
10_0402_5%~D
12
10P_0402_50V8J~D
1
C C
B B
2
CB_HWSPND#<33>
R802
C1026
PCI_PAR<22>
PCI_FRAME#<22>
PCI_TRDY#<22>
PCI_IRDY#<22>
PCI_STOP#<22>
PCI_DEVSEL#<22>
1 2
CLK_PCI_PCM<6>
R885 0_0402_5%~D
1 2
SYS_PME#<33>
1 2
R812
1 2
10K_0402_5%~D
12
R801
47K_0402_1%~D
BUS_GRST#
1U_0603_10V6K~D
1
2
PCI_C_BE3#<22>
PCI_C_BE2#<22>
PCI_C_BE1#<22>
PCI_C_BE0#<22>
PCI_PERR#<22>
PCI_SERR#<22>
PCI_REQ1#<22>
PCI_GNT1#<22>
PCI_RST#<22,30>
R895100_0402_5%~D
R886
1 2
0_0402_5%~D@
PCI_AD31
PCI_AD30
PCI_AD29
PCI_AD28
PCI_AD27
PCI_AD26
PCI_AD25
PCI_AD24
PCI_AD23
PCI_AD22
PCI_AD21
PCI_AD20
PCI_AD19
PCI_AD18
PCI_AD17
PCI_AD16
PCI_AD15
PCI_AD14
PCI_AD13
PCI_AD12
PCI_AD11
PCI_AD10
PCI_AD9
PCI_AD8
PCI_AD7
PCI_AD6
PCI_AD5
PCI_AD4
PCI_AD3
PCI_AD2
PCI_AD1
PCI_AD0
PCI_C_BE3#
PCI_C_BE2#
PCI_C_BE1#
PCI_C_BE0#
PCI_PAR
PCI_FRAME#
PCI_TRDY#
PCI_IRDY#
PCI_STOP#
PCI_DEVSEL#
PCI_IDSEL
PCI_PERR#
PCI_SERR#
PCI_REQ1#
PCI_GNT1#
CLK_PCI_PCM
PCI_RST#
BUS_GRST#
100K_0402_5%~D
R813
1 2
Layout Note: Place close to R5C833 Chip
TPBIAS0
TPA0+
TPA0TPB0+
TPB0-
A A
R814
R890
C1052
56.2_0402_1%~D
56.2_0402_1%~D
12
12
R815
C1044
56.2_0402_1%~D
56.2_0402_1%~D
12
12
R891
270P_0402_50V7K~D
5.1K_0402_1%~D
R985
2
1
1 2
5
0.33U_0603_10V7K~D
0.01U_0402_16V7K~D
C1045
1
1
2
2
U56
125
AD31
126
AD30
127
AD29
1
AD28
2
AD27
3
AD26
5
AD25
6
AD24
9
AD23
11
AD22
12
AD21
14
AD20
15
AD19
17
AD18
18
AD17
19
AD16
36
AD15
37
AD14
38
AD13
39
AD12
40
AD11
42
AD10
43
AD9
44
AD8
46
AD7
47
AD6
48
AD5
49
AD4
50
AD3
51
AD2
52
AD1
53
AD0
7
C/BE3#
21
C/BE2#
35
C/BE1#
45
C/BE0#
33
PAR
23
FRAME#
25
TRDY#
24
IRDY#
29
STOP#
26
DEVSEL#
8
IDSEL
30
PERR#
31
SERR#
124
REQ#
123
GNT#
121
PCICLK
119
PCIRST#
71
GBRST#
117
CLKRUN#
70
PME#
115
INTA#
116
INTB#
69
HWSPND#
66
TEST
99
AGND
102
AGND
103
AGND
107
AGND
111
AGND
97
RSV
R5C833-TQFP128P_TQFP128_14X14~D
4
10
VCC_PCI3V
20
VCC_PCI3V
27
VCC_PCI3V
32
VCC_PCI3V
R5C833
AVCC_PHY3V
AVCC_PHY3V
AVCC_PHY3V
AVCC_PHY3V
UDIO0/SRIRQ#
VCC_PCI3V
VCC_PCI3V
VCC_RIN
VCC_ROUT
VCC_ROUT
VCC_ROUT
VCC_ROUT
VCC_ROUT
VCC_3V
VCC_MD3V
TPBIAS0
TPAP0
TPAN0
TPBP0
TPBN0
MDIO00
MDIO01
MDIO02
MDIO03
MDIO04
MDIO05
MDIO06
MDIO07
MDIO08
MDIO09
MDIO10
MDIO11
MDIO12
MDIO13
MDIO14
MDIO15
MDIO16
MDIO17
MDIO18
MDIO19
MSEN
XDEN
REXT
VREF
UDIO1
UDIO2
UDIO3
UDIO4
UDIO5
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
FIL0
XI
XO
41
128
61
16
34
64
114
120
67
86
+3.3V_RUN_PHY
98
106
110
112
113
109
108
105
104
80
79
78
77
76
75
74
73
88
84
82
81
93
90
91
89
92
87
85
83
58
55
94
95
96
101
100
72
60
56
65
59
57
4
13
22
28
54
62
63
68
118
122
+VCC_ROUT
C1040
TPBIAS0
TPA0+
TPA0TPB0+
TPB0SDCD#_MMCDC#
SDWP#
CARD_EN
TP_SD/MMC/MS
SDCMD_MSBS
SDCLK_MSCLK
SDDATA0_MSDATA0
SDDATA1_MSDATA1
SDDATA2_MSDATA2
SDDATA3_MSDATA3
MMCDAT4
MMCDAT5
MMCDAT6
MMCDAT7
MSEN
XDEN
R5C833XI
R5C833XO
UDIO4
UDIO5
MSEN Pull-Up : MS Enabled
MSEN Pull-Down: MS Disabled
R975 10K_0402_5%~D
MSEN
1 2
R976 10K_0402_5%~D
XDEN
1 2
XDEN Pull-Up : xD Enabled
XDEN Pull-Down: xD Disabled
4
0.01U_0402_16V7K~D
C1049
C1050
1
2
+3.3V_R5C833
0.01U_0402_16V7K~D
C1051
10U_0805_6.3V6M~D
1
1
2
2
TPA0+ <21>
TPA0- <21>
TPB0+ <21>
TPB0- <21>
T94 PAD~D
R1110
1 2
Layout Note:
Place close to R5C833
@
C10560.01U_0402_16V7K~D
1 2
IRQ_SERIRQ <24,30,32,33,34>
+3.3V_R5C833
R889
10K_0402_5%~D
1 2
1 2
R984
100K_0402_5%~D
SDDATA1_MSDATA1
SDDATA2_MSDATA2
+15V_ALW
0.1U_0402_16V4Z~D
C1042
1
2
+3.3V_R5C833
SDCLK_MSCLK_R
0_0402_5%~D
3
+3.3V_R5C833
0.01U_0402_16V7K~D
C1043
1
2
BLM21AG601SN1D_0805~D
C1055
2
1
10U_0805_6.3V6M~D
1
2
L65
1 2
+3.3V_RUN
0.01U_0402_16V7K~D
R887
1 2
C1010
1
2
CARD_EN
10K_0402_1%~D
0.01U_0402_16V7K~D
C1041
1
2
10U_0805_6.3V6M~D
C1027
1
2
R1029
0_0805_5%~D
1 2
0.01U_0402_16V7K~D
C1059
C1028
1
2
0.01U_0402_16V7K~D
0.01U_0402_16V7K~D
C1046
1
1
2
2
+3.3V_RUN_PHY
0.1U_0402_16V4Z~D
0.01U_0402_16V7K~D
C1030
C1029
1
1
2
2
U28
5
IN
4
0.1U_0402_16V4Z~D
EN
TPS2051BDBVR_SOT23-5~D
C509
Layout Note: Place close to
R5C833 and Shield GND
C1032
15P_0402_50V8J~D
1 2
1 2
C1058
15P_0402_50V8J~D
+3.3V_R5C833
0.01U_0402_16V7K~D
C1047
C1048
1
1
2
2
1000P_0402_50V7K~D
1
2
1
OUT
2
GND
3
OC#
Y2
24.576MHZ_12PF_1YG24576CE1C~D
1 2
1 2
220_0402_5%~D
10U_0805_6.3V6M~D
+3.3V_R5C833
+VCC_ROUT
C1053
1
2
R809
2
0.01U_0402_16V7K~D
C1054
1
2
+3.3V_RUN_CARD
1
2
R5C833XI
R5C833XO
Solve MS Duo Adaptor short problem
Q132
D
S
2N7002W-7-F_SOT323-3~D
1 3
G
2
R923
1 2
10K_0402_5%~D
13
SDCD#_MMCDC#
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
D
2
G
Q134
S
2N7002W-7-F_SOT323-3~D
D
1 3
2
S
G
Q133
2N7002W-7-F_SOT323-3~D
SDDATA1
SDDATA2
2
R888
1 2
0_0805_5%~D
0.01U_0402_16V7K~D
C1024
1
2
1
C505
2
0.1U_0402_16V4Z~D
+3.3V_RUN
0.47U_0402_10V4Z~D
0.47U_0402_10V4Z~D
C1025
1
2
R413
C506
1 2
150K_0402_5%~D
1U_0603_10V4Z~D
Function set pin define
Pull-up
SDDATA3_MSDATA3
SDCMD_MSBS
+3.3V_RUN_CARD
SDCLK_MSCLK_R
SDDATA0_MSDATA0
SDDATA1
SDDATA2
MMCDAT4
MMCDAT5
MMCDAT6
MMCDAT7
SDCD#_MMCDC#
SDWP#
SDCD#_MMCDC#
SDWP#
1
SD,MMC muti-functio n pin define
Media I/F
MDIO00
SD Card
SDCD#
MMC Card
MMCCD#
MDIO01
MDIO02
MDIO03
MDIO04
MDIO05
MDIO06
MDIO07
MDIO08
MDIO09
MDIO10
MDIO11
MDIO12
MDIO13
MDIO14
MDIO15
MDIO16
MDIO17
SDWP#
SDPWR0
SDPWR1
SDLED#
SDEXTCK
SDCCMD
SDCCLK
SDCDAT0
SDCDAT1
SDCDAT2
SDCDAT3
MMCPWR
MMCLED#
MMCCMD
MMCCLK
MMCDAT0
MMCDAT1
MMCDAT2
MMCDAT3
MMCDAT4
MMCDAT5
MMCDAT6
MMCDAT7
MDIO18
MDIO19
UDIO4UDIO3 XDEN
Pull-up Pull-up Pull-up
MSEN
Function
Enable
SD,XD,MS,MMC Card
JSD1
14
DAT3/SD1
12
CMD/SD2
10
VSS1/SD3
9
VCC/SD4
8
CLK/SD5
6
GND/VSSS2/SD6
4
DAT0/SD7
3
DAT1/SD8
15
DAT2/SD9
13
DAT4/MMC10
11
DAT5/MMC11
7
DAT6/MMC12
5
DAT7/MMC13
16
CD_WP_SW/GND
17
CD_WP_SW/GND
19
CD_SW/SD
20
WP_SW/SD
2
CD_SW_TAISOL/SD
1
WP/SW_TAISOL/SD
18
GND_SW
T-SOL_156-4000000901_NR
only for MMC/SD
DELL CONFIDENTIAL/PROPRIETARY
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
CardBus Controller(R5C833)
LA-4151P
1
27 57Fr id ay, July 04, 2008
of
1.0
5
4
3
2
1
1.5Vout
1.5Vout
3.3Vout
3.3Vout
OC#
PERST#
GND
NC
+1.5V_CARD
11
13
3
5
15
19
8
16
7
0.1U_0402_16V4Z~D
1
C999
2
1
2
CARD_RESET#
0.1U_0402_16V4Z~D
1
C1000
2
+3.3V_CARDAUX
0.1U_0402_16V4Z~D
C1006
+3.3V_CARD
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
1
C1001
2
10U_0805_6.3V6M~D
1
1
C1002
C1003
2
2
C135
1
2
+1.5V_RUN
0.1U_0402_16V4Z~D
C997
U52
12
1.5Vin
14
1.5Vin
2
3.3Vin
4
3.3Vin
AUX_IN17AUX_OUT
6
SYSRST#
20
SHDN#
1
STBY#
10
CPPE#
9
CPUSB#
18
RCLKEN
R5538_QFN20~D
D D
+3.3V_SUS
1 2
R657 100K_0402_5%~D
EXPRCRD_STDBY#<33>
+3.3V_SUS
C C
1 2
R683 0_0402_5%~D
1 2
R684 100K_0402_5%~D
1 2
R790 100K_0402_5%~D
EXPRCRD_PWREN#<33>
+3.3V_SUS
0.1U_0402_16V4Z~D
1
2
PLTRST1#<10,22>
C134
+3.3V_RUN
0.1U_0402_16V4Z~D
1
2
PLTRST1#
EXPRCRD_STBY_R#
EXPRCRD_PWREN#
CPUSB#
Express Card
+1.5V_CARD: Max. 650mA, A verage 500mA
+3.3V_CA R D: Max. 1300mA, Average 1000mA
DET_PCCRD_EXPSCRD#<33>
1 2
R791 0_0402_5%~D@
1 2
R792 0_0402_5%~D @
+3.3V_CARDAUX
2.2K_0402_5%~D
2.2K_0402_5%~D
12
R126
4
4
1
1
L64
DLW21SN900SQ2_0805~D
R127
EXP_SMBDATA
EXP_SMBCLK
USBP7-<24>
USBP7+<24>
B B
+3.3V_SUS
12
+3.3V_SUS
6 1
2
5
3
Q112A
2N7002DW-T/R7_SOT363-6
Q112B
2N7002DW-T/R7_SOT363-6
4
CARD_SMBDAT<21,34>
CARD_SMBCLK<21,34>
A A
1
2
0.1U_0402_16V4Z~D
C1004
3
3
2
2
+3.3V_CARD
0.1U_0402_16V4Z~D
1
2
USBP7_D-
USBP7_D+
PCIE_WAKE#<21,33>
EXPCLK_REQ#<6>
CLK_PCIE_EXP#<6>
C1005
CLK_PCIE_EXP<6>
PCIE_IRX_EXPTX_N4<24>
PCIE_IRX_EXPTX_P4<24>
PCIE_ITX_EXPRX_N4_C<24>
PCIE_ITX_EXPRX_P4_C<24>
+1.5V_CARD
DET_PCCRD_EXPSCRD#
CPUSB#
EXP_SMBCLK
EXP_SMBDATA
PCIE_WAKE#
CARD_RESET#
EXPRCRD_PWREN#
CLK_PCIE_EXP#
CLK_PCIE_EXP
PCIE_IRX_EXPTX_N4
PCIE_IRX_EXPTX_P4
PCIE_ITX_EXPRX_N4_C
PCIE_ITX_EXPRX_P4_C
0.1U_0402_16V4Z~D
1
C1007
2
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
JEXP1
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
GND
GND
TYCO_2-2041070-6
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
CardBus/SD card Socket
LA-4151P
28 57Fr id ay, July 04, 2008
1
1.0
of
5
4
3
2
1
IO connector II
D D
DAT_DDC2_CRT<20>
CLK_DDC2_CRT<20>
C C
TYCO_2041070-6
FP_SW_USBD+<40>
FP_SW_USBD-<40>
JBIO3
1
1
2
2
3
3
4
4
5
5
6
6
7
GND
8
GND
R422 0_0402_5%~D
R423 0_0402_5%~D
USBP3-<24>
USBP3+<24>
+5V_FP
1 2
1 2
+5V_RUN
+3.3V_RUN
DAT_DDC2_CRT
CLK_DDC2_CRT
USBP3USBP3+
+5V_ALW
FP_USB_DFP_USB_D+
1 2
R873
@
0_0402_5%~D
FPRESET#
FP_USB_D+
FP_USB_D-
JBIO2
112
334
556
778
9910
11
11
13
13
151516
171718
191920
212122
232324
252526
27
27
29
29
31
GND
GND
32
GND
GND
33
GND
GND
TYCO_3-1775014-0~D
+3.3V_TP_PWR
+5V_TP_PWR
BAT54CW_SOT323~D
FP_USB_D-
2
4
6
8
10
12
12
14
14
16
18
20
22
24
26
28
28
30
30
34
35
36
1
RED_CRT
GREEN_CRT
BLUE_CRT
HSYNC_CRT
VSYNC_CRT
ESATA_USB_OC#
ESATA_USB_PWR_EN#
ESATA_IRX_DTX_N4_C
ESATA_IRX_DTX_P4_C
ESATA_ITX_DRX_P4
ESATA_ITX_DRX_N4
D82
3
2
U51
1
GND
IO2
2
IO1
VIN
PRTR5V0U2X_SOT143-4~D
RED_CRT <20>
GREEN_CRT <20>
BLUE_CRT <20>
HSYNC_CRT <20>
VSYNC_CRT <20>
ESATA_USB_OC# <24>
ESATA_IRX_DTX_N4_C <23>
ESATA_IRX_DTX_P4_C <23>
ESATA_ITX_DRX_P4 <23>
ESATA_ITX_DRX_N4 <23>
FP_RESET# <32>
BKT_GPIO17 <35>
FP_USB_D+
3
4
ESATA_USB_PWR_EN# <33>
+3.3V_TP_PWR
Place close to
JBIO1.1
+3.3V_TP_PWR
+5V_TP_PWR
0.1U_0402_16V4Z~D
1
1
C770
2
2
0.1U_0402_16V4Z~D
@
C1035
USB PORT#
0
1
2
3
4
5
6
7
9
11
JUSB1 (Ext Right Side Top)
BLT mode
NC
JESATA1 (Ext Left Side Bottom)
WLAN
WWAN
BT
Card Bus/Express card
DOCKING8
DOCKING
USH->BIO10
Camera
DESTINATION
B B
JSPK1
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
GND
11
GND
MOLEX_53780-0919
Speaker Connector
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
DELL CONFIDENTIAL/PROPRIETARY
Title
Size Document Number Rev
2
Date: Sheet
Compal Electronics, Inc.
FingerFrint
LA-4151P
29 57Fr id ay, July 04, 2008
1
1.0
of
100P_0402_50V8J~D
@
C423
LID_CL#
100P_0402_50V8J~D
@
1
C424
2
4
15 mils trace
INT_SPK_L1<21>
INT_SPK_L2<21>
INT_SPK_R1<21>
INT_SPK_R2<21>
SPEAKER_DET#<24>
A A
5
INT_SPK_L1
INT_SPK_L2
INT_SPK_R1
INT_SPK_R2
LID_CL#<33,38>
1
2
LID_CL#
2
1
100P_0402_50V8J~D
@
C425
0.1U_0402_16V4Z~D
C685
1
2
+3.3V_ALW
100P_0402_50V8J~D
@
C426
1
2
5
4
3
2
1
China TPM
VDD_0
VDD_1
VDD_2
NC_3
NC_5
NC_12
NC_13
NC_14
+3.3V_RUN
10
19
24
11
18
25
4
3
5
12
13
14
RUNMODE
PIN9
X
0
1
1
2
TPM_PIN3
TPM_PIN5
TPM_PIN12
TPM_PIN13
TPM_PIN14
1
2
Jetway
Base Address
EE/EF
7E/7F
2E/2F
4E/4F
C_TPM_LPC_EN
C1203
0.1U_0402_10V7K~D
10@
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
2
2
1@
1@
C484
C485
1
1
R1115 0_0402_5%~D10@
1 2
C1202
0.1U_0402_10V7K~D
9@
CLK_TCM_14M<6>
BA1
PIN3
0
0
1
11
12
1@
4.7K_0402_5%~D
2
1
R892
Lola USH and China TPM BOM Option
10U_0603_6.3V6M~D
0.1U_0402_16V4Z~D
1
1@
C486
2
Pull-up on LPC_EN_R
Pull-down on LPC_EN_R
9@
C487
Series from EC to LPC_EN_R
Series from EC to LPD#
Pull-up on LPD#
Pull-up on EC
Pull-down on China TPM
Series from EC to China PD#
Broadcom USH
China TPM
LPCBus Series Resistors
TPM_ID(Strap Low) ICH9M GP I O6 Pin AH21 POP
PART/PINDESCRIPTION B0 USHA0 USHRef Des
USH pin R6 LPCEN
USH pin R6 LPCEN
EC to USH Pin R6 LPCEN
EC to USH Pin P7 LPCPD_N
USH pin P7 LPCPD_N
SIO pin 105 OUT65
To China TPM U24 pin 28
SIO to China Pin 28 LPCPD#
U32 USH
U24 China TPM
R705,R723,R7 24,R732,R733
R841
R483
3@ R464
R466
R474
R788
1@ R892
1@ R893
U32
1@ U24
3@
1@ R988
POP POP
@
@
@
@
@
@
POP
@@
POP POP
3@ R987@POP@POP
BA0
PIN9
0
1
0
1@ is for TCM
3@ is for Broadcom TPM only
9@ is for ZTE TCM
10@ is for Jetway TCM
A0 w/CHINAB0 w/CHINA
@
POP
POP
@
@
POP
@
@
POPPOP POP POP
POP
POP
POP
@
POP
POP
POP
@
@
@
POP
POP POP
@@
POP
@
@
@
@
@
@TPM_ID (Strap High) ICH 9 M GP I O 6 Pin AH21
D D
C C
LOW:Power Down Mode
High:Working Mode
SP_TPM_LPC_EN<32,33>
LPC_LAD0<23,32,33,34>
LPC_LAD1<23,32,33,34>
LPC_LAD2<23,32,33,34>
LPC_LAD3<23,32,33,34>
CLK_PCI_TPM_CHA<6>
LPC_LFRAME#<23,32,33,34>
PCI_RST#<22,27>
IRQ_SERIRQ<24,27,32,33,34>
CLKRUN#<24,27,33,34>
T167PAD~D
9@
R884
1K_0402_5%~D
+3.3V_RUN +3.3V_RUN
12
@
R1116
10K_0402_5%~D
TPM_PIN3
9@
R1118
1K_0402_5%~D
1 2
R893 0_0402_5%~D1@
1 2
1 2
BSEL
PIN12
T166PAD~D
1 2
1(default)
FLASH
TPM_PIN7
TPM_PIN9
TESTI
@
T164PAD~D
T165PAD~D
TPM_PIN6
C_TPM_LPC_EN
R383
10K_0402_5%~D
12
@
R1117
10K_0402_5%~D
SRAM
28
26
23
20
17
21
22
16
27
15
TPM_PIN12TPM_PIN9
0
U24
1@
1
GPIO1
2
GPIO2
6
GPIO_EXPRESS_00
LPCPD#
LAD0
LAD1
LAD2
LAD3
LCLK
LFRAME#
LRESET#
SERIRQ
CLKRUN#
7
PP
9
TESTBI/BADD
8
TESTI
SSX35BCB_TSSOP28~D
ZTE
STATUS
Normal mode
JTAG mode
Normal mode
@
R1119
1K_0402_5%~D
1 2
TESTEN
PIN8
0
1
1
GND_11
GND_18
GND_25
GND_4
TPM_PIN5
B B
100K_0402_5%~D
D
100K_0402_5%~D
12
R431
5
200K_0402_5%~D
61
R437
Q53A
12
2
2N7002DW-T/R7_SOT363-6~D
AUX_EN_WOWL<34>
100K_0402_5%~D
A A
12
@
6
12
R432
2
1
2N7002DW-T/R7_SOT363-6~D
3
Q53B
4
R436
+3.3V_WLAN+3.3V_ALW+15V_ALW
S
45
Q47
SI3456BDV-T1-E3_TSOP6~D
G
3
4700P_0402_25V7K~D
470K_0402_5%~D
1
12
@
R435
2
C551
Blue tooth
+3.3V_RUN
C1085 0.1U_0402_16V4Z~D
1 2
C1086
1
2
COEX1_BT_ACTIVE
COEX2_WLAN_ACTIVE
BT_RADIO_DIS#
USBP6+
USBP6BT_ACTIVE
BT_DET#
33P_0402_50V8J~D
10K_0402_5%~D
12
R920
100P_0402_50V8J~D@
C1087
1
2
COEX1_BT_ACTIVE<21>
COEX2_WLAN_ACTIVE<21>
BT_RADIO_DIS#<33>
USBP6+<24>
USBP6-<24>
BT_ACTIVE<21,38>
BT_DET#<24>
JBT
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
GND
12
12
GND
TYCO_1-2041070-2
13
14
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
Blue Tooth
LA-4151P
30 57Fr id ay, July 04, 2008
1
1.0
of
5
4
3
2
1
SM24.TCT_SOT23-3~D
JDOCK1
1
1
3
3
5
5
7
7
9
9
11
11
13
13
15
15
17
17
19
19
21
21
23
23
25
25
27
27
29
29
31
31
33
33
35
35
37
37
39
39
41
41
43
43
45
45
47
47
49
49
51
51
53
53
55
55
57
57
59
59
61
61
63
63
65
65
67
67
69
69
71
71
73
73
75
75
77
77
79
79
81
81
83
83
85
85
87
87
89
89
91
91
93
93
95
95
97
97
99
99
101
101
103
103
105
105
107
107
109
109
111
111
113
113
115
115
117
117
119
119
121
121
123
123
125
125
127
127
129
129
131
131
133
133
135
135
137
137
139
139
141
141
143
143
145
GND1
146
PWR1
147
PWR1
148
PWR1
153
Shield_G
154
Shield_G
155
Shield_G
156
Shield_G
157
Shield_G
158
Shield_G
JAE_WD2F144WD3
PWR2
PWR2
PWR2
GND2
Shield_G
Shield_G
Shield_G
Shield_G
Shield_G
Shield_G
DOCK_AC_OFF
2
2
4
4
6
6
8
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
DPC_LANE_P0_C
10
DPC_LANE_N0_C
12
14
DPC_LANE_P1_C
16
DPC_LANE_N1_C
18
20
DPC_LANE_P2_C
22
DPC_LANE_N2_C
24
26
DPC_LANE_P3_C
28
DPC_LANE_N3_C
30
32
DPC_DOCK_AUX_SW
34
DPC_DOCK_AUX#_SW
36
38
DPC_DOCK_HPD_R
40
42
44
46
48
50
52
SATA_SBRX_DTX_P3
54
SATA_SBRX_DTX_N3
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
TR0/1CT
116
TR2/3CT
118
120
122
124
126
128
130
132
134
136
138
140
142
DOCK_DET#_R DOCK_DET#
144
149
150
151
152
159
160
161
162
163
164
C586 0.01U_0402_16V7K~D
C587 0.01U_0402_16V7K~D
+DOCK_PWR_BAR
1
C1033
0.1U_0603_50V4Z~D
2
DOCK_AC_OFF <33,48>
DOCK_LOM_SPD100LED_ORG# <21>
DPC_DOCK_CA_DET <21>
DPC_LANE_P0_C <12>
DPC_LANE_N0_C <12>
DPC_LANE_P1_C <12>
DPC_LANE_N1_C <12>
DPC_LANE_P2_C <12>
DPC_LANE_N2_C <12>
DPC_LANE_P3_C <12>
DPC_LANE_N3_C <12>
DPC_DOCK_AUX_SW <21>
DPC_DOCK_AUX#_SW <21>
DPC_DOCK_HPD_R <21>
ACAV_DOCK_SRC# <48>
DAT_DDC2_DOCK <20>
CLK_DDC2_DOCK <20>
12
12
SATA_SBTX_C_DRX_P3 <23>
SATA_SBTX_C_DRX_N3 <23>
USBP8+ <24>
USBP8- <24>
USBP9+ <24>
USBP9- <24>
CLK_KBD <34>
DAT_KBD <34>
BREATH_LED# <34,38>
DOCK_LOM_ACTLED_YEL# <21>
DOCK_LOM_TRD0+ <21>
DOCK_LOM_TRD0- <21>
DOCK_LOM_TRD1+ <21>
DOCK_LOM_TRD1- <21>
+LOM_VCT
DOCK_LOM_TRD2+ <21>
DOCK_LOM_TRD2- <21>
DOCK_LOM_TRD3+ <21>
DOCK_LOM_TRD3- <21>
DOCK_DCIN_IS+ <46>
DOCK_DCIN_IS- <46>
DOCK_POR_RST# <34>
12
@
SATA_SBRX_DTX_P3_C <23>
SATA_SBRX_DTX_N3_C <23>
D77
RB751S40T1_SOD523-2~D
21
R1076
910K_0402_5%~D
DPC_LANE_P0_C
DPC_LANE_N0_C
DPC_LANE_P1_C
DPC_LANE_N1_C
DPC_LANE_P2_C
DPC_LANE_N2_C DPC_LANE_N2_C
DPC_LANE_P3_C
DPC_LANE_N3_C
DPC_DOCK_AUX_SW
DPC_DOCK_AUX#_SW
DPC_DOCK_HPD_R DPC_DOCK_HPD_R
DPC_DOCK_CA_DET DPC_DOCK_CA_DET
DOCK_DET# <33>
D22
@
1
2
4
5
3
8
RCLAMP0524P.TCT~D
D24
@
1
2
4
5
3
8
RCLAMP0524P.TCT~D
D26
@
1
2
4
5
3
8
RCLAMP0524P.TCT~D
DOCK_DET#
DPC_LANE_P0_C
10
DPC_LANE_N0_C
9
DPC_LANE_P1_C
7
DPC_LANE_N1_C
6
DPC_LANE_P2_C
10
9
DPC_LANE_P3_C
7
DPC_LANE_N3_C
6
DPC_DOCK_AUX_SW
10
DPC_DOCK_AUX#_SW
9
7
6
+RTC_CELL
R124 100K_0402_5%~D@
R1075 100K_0402_5%~D
12
+3.3V_ALW
12
CLK_PCI_DOCK
12
R462
@
10_0402_5%~D
1
C590
@
4.7P_0402_50V8C~D
2
D23
DPB_LANE_P0_C
DPB_LANE_N0_C
DPB_LANE_P1_C
DPB_LANE_N1_C
D D
DPB_LANE_P2_C
DPB_LANE_N2_C
DPB_LANE_P3_C
DPB_LANE_N3_C
DPB_DOCK_AUX
DPB_DOCK_AUX#
C C
@
1
2
4
5
3
8
RCLAMP0524P.TCT~D
D25
@
1
2
4
5
3
8
RCLAMP0524P.TCT~D
D27
@
1
2
4
5
3
8
RCLAMP0524P.TCT~D
Place close to JDOCK1 connector Place close to JDOCK1 connector
B B
DPB_LANE_P0_C
10
DPB_LANE_N0_C
9
DPB_LANE_P1_C
7
DPB_LANE_N1_C
6
DPB_LANE_P2_C
10
DPB_LANE_N2_C
9
DPB_LANE_P3_C
7
DPB_LANE_N3_C
6
DPB_DOCK_AUX
10
DPB_DOCK_AUX#
9
DPB_DOCK_HPDDPB_DOCK_HPD
7
DPB_DOCK_CA_DETDPB_DOCK_CA_DET
6
DOCK_LOM_SPD10LED_GRN#<21>
DPB_DOCK_CA_DET<21>
DPB_LANE_P0_C<12>
DPB_LANE_N0_C<12>
DPB_LANE_P1_C<12>
DPB_LANE_N1_C<12>
DPB_LANE_P2_C<12>
DPB_LANE_N2_C<12>
DPB_LANE_P3_C<12>
DPB_LANE_N3_C<12>
+NBDOCK_DC_IN_SS
DOCK_SMB_DAT<34>
DOCK_PWR_BTN#<34>
DPB_DOCK_AUX<21>
DPB_DOCK_AUX#<21>
DPB_DOCK_HPD<21>
BLUE_DOCK<20>
RED_DOCK<20>
GREEN_DOCK<20>
HSYNC_DOCK<20>
VSYNC_DOCK<20>
CLK_MSE<34>
DAT_MSE<34>
DAI_BCLK#<21>
DAI_LRCK#<21>
DAI_12MHZ#<21>
D_LAD0<33>
D_LAD1<33>
D_LAD2<33>
D_LAD3<33>
D_LFRAME#<33>
D_CLKRUN#<33>
D_SERIRQ<33>
D_DLDRQ1#<33>
CLK_PCI_DOCK<6>
DOCK_SMB_CLK<34>
DOCK_SMB_ALERT#<34,41>
DOCK_PSID<41>
SLICE_BAT_PRES#<33,41,48>
+DOCK_PWR_BAR
0.1U_0603_50V4Z~D
DOCK_DET_1
DPB_LANE_P0_C
DPB_LANE_N0_C
DPB_LANE_P1_C
DPB_LANE_N1_C
DPB_LANE_P2_C
DPB_LANE_N2_C
DPB_LANE_P3_C
DPB_LANE_N3_C
DPB_DOCK_AUX
DPB_DOCK_AUX#
DPB_DOCK_HPD
BLUE_DOCK
RED_DOCK
GREEN_DOCK
DAI_DI<21>
DAI_DO#<21>
SLICE_BAT_PRES#
2
3
1
C1034
2
D73
1
A A
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
DOCKING CONN
LA-4151P
31 57Fr id ay, July 04, 2008
1
1.0
of
2
BCM5880
LPC
UARTSPISPISmard Card
SMC_ADD_15/REFCLK_FREQ_0
SMC_ADD_16/REFCLK_FREQ_1
SMC_ADD_17/BOOT_SRC_0
SMC_ADD_18/BOOT_SR_1
BootStrap
LPC_LFRAME#<23,30,33,34>
LPC_LAD0<23,30,33,34>
LPC_LAD1<23,30,33,34>
LPC_LAD2<23,30,33,34>
LPC_LAD3<23,30,33,34>
C1014
L69 10UH_LQH32CN100K53L_10%~D
R773 100K_0402_5%~D
R491 0_0402_5%~D
R493 0_0402_5%~D
R492 0_0402_5%~D
R772 0_0402_5%~D
27P_0402_50V8J~D
2
1
BCM5880KFBG_FBGA225~D
+SC_VCC
12
12
1 2
1 2
1 2
1 2
C633
U34
1
D
2
C
VSS
3
RESET#
VCC
4
S#
W#
M45PE16-VMP6TP_SO8~D
BCM5880_GPIO15
SC_DET
2
R705 0_0402_5%~D
R723 0_0402_5%~D
R724 0_0402_5%~D
R732 0_0402_5%~D
R733 0_0402_5%~D
+3.3V_RUN
8
Q
7
6
5
2
1
R341 4.7K_0402_5%~D@
USH:B0-->SA00001SJ1L
H1
SMC_ADD_0
J4
SMC_ADD_1
H2
SMC_ADD_2
H3
SMC_ADD_3
G1
SMC_ADD_4
H4
SMC_ADD_5
F2
SMC_ADD_6
G4
SMC_ADD_7
G2
SMC_ADD_8
G3
SMC_ADD_9
E2
SMC_ADD_10
F4
SMC_ADD_11
F1
SMC_ADD_12
F3
SMC_ADD_13
D2
SMC_ADD_14
E3
D1
E1
C2
D3
SMC_ADD_19
C1
SMC_ADD_20
E4
SMC_ADD_21
B1
SMC_ADD_22
C3
SMC_ADD_23
R2
SMC_DATA_0
P3
SMC_DATA_1
R1
SMC_DATA_2
P2
SMC_DATA_3
R3
SMC_DATA_4
M4
SMC_DATA_5
N2
SMC_DATA_6
N3
SMC_DATA_7
P1
SMC_DATA_8
M3
SMC_DATA_9
SMC_DATA_10
SMC_DATA_11
SMC_DATA_12
SMC_DATA_13
SMC_DATA_14
SMC_DATA_15
SMC_BLS_N_0
SMC_BLS_N_1
1 2
1 2
1 2
1 2
1 2
0.1U_0402_16V4Z~D
1 2
R1068 100K_0402_5%~D@
M2
L4
N1
L3
L2
K4
K2
SMC_ADV_N
J1
K1
J3
SMC_CRE
M1
SMC_CS_N_0
K3
SMC_CS_N_1
P12
SMC_IO_3V
J2
SMC_OE_N
L1
SMC_WE_N
+3.3V_RUN
10U_0805_10V4Z~D
1
C706
C620
2
Routing impedance is 90ohm
C621
4.7U_0603_6.3V6K~D
12
SC_RST
27P_0402_50V8J~D
2
C1015
1
+3.3V_RUN
1U_0603_10V4Z~D
1
C644
2
SPI_RXD
BCM5880_GPIO15SPI_CS
12
+1.2V_RUN_PLL
SMC_ADD15
SMC_ADD16
SMC_ADD17
SMC_ADD18
FP_RESET#
FP_RESET# <29>
R1057
@
1 2
BBCLK
R555 22_0402_5%~D@
R848 4.7K_0402_1%~D@
PLTRST3#
1 2
R1077 0_0402_5%~D@
R940 0_0402_5%~D @
1 2
R941 0_0402_5%~D @
1 2
R942 0_0402_5%~D @
1 2
1 2
R949 0_0402_5%~D@
+3.3V_RUN
1 2
R339
4.7K_0402_5%~D
LPC_LFRAME#_R
LPC_LAD0_R
LPC_LAD1_R
LPC_LAD2_R
LPC_LAD3_R
R1067
1@
1 2
1 2
CLK_PCI_TPM
10_0402_5%~D
12
@
4.7P_0402_50V8C~D
PCI_TPM_TERM
2
@
1
12
R744
C589
R1089 10K_0402_5%~D@
3@
R841 3K_0402_5%~D
R843 47K_0402_1%~D@
12
100K_0402_5%~D
U32B
F12
G13
G15
G14
B14
B15
D12
D13
E12
A15
N9
M8
P9
M12
R9
R10
F15
F14
D15
E14
A1
B2
N8
R8
P10
R11
N10
R12
P11
M9
SWV
+3.3V_RUN
+2.5V_RUN_AVDD
BLM18BB100SN1D_0603~D
1U_0402_6.3V6K~D
L36
2
C624
1
1 2
R494 3K_0402_1%~D
1 2
R498 3K_0402_1%~D
POR_AVSS
POR_EXTR
POR_INT12
POR_MONITOR
PLL_VDD_1P2I
PLL_AVDD_1P2O
PLL_VSS
PLL_VDD_1P2I
PLL_VSS
NC
OVSTB/ZEROB
SCANACCMODE
SECURE_BOOT
SWV/ERROR,OSC1,OSC2,SPL
TESTMODE/TST_SEC_BOOT
IDDQ_EN/CM3_MODE
REFCLK_XTALIN
REFCLK_XTALOUT
AUXCLK_XTALIN
AUXCLK_XTALOUT
CLKOUT
CLKOUT_EN
RST_N
RSTOUT_N
JTAG_TCK
JTAG_TDI
JTAG_TDO
JTAG_TMS
JTAG_TRSTN
JTCE
1 2
R474 4.7K_0402_5%~D
1 2
R484 4.7K_0402_5%~D
1 2
R485 4.7K_0402_5%~D
1 2
R736 4.7K_0402_5%~D
1 2
R810 4.7K_0402_5%~D
1 2
R478 4.7K_0402_5%~D
R850 10K_0402_5%~D
1 2
R1066 4.7K_0402_5%~D
SSMC
AD[18:17]
SMC SPI RVDUSB
AD[16:15]
RVD
+RFID_AVDD2P5
12
2
1
POR_EXTR
1U_0603_10V4Z~D
1U_0603_10V4Z~D
1
1
C593
C592
2
2
OVSTB
SCANMOD
T66PAD~D
SBOOT
SWV
TSTMOD
T68PAD~D
IDQ_EN
T69PAD~D
REF_XIN
REF_XOUT
0_0402_5%~D
AUX_XIN
AUX_XOUT
BBCLK_R
1 2
1 2
JTAG_CLK_USH
JTAG_TDI_USH
JTAG_TDO_USH
JTAG_TMS_USH
JTAG_RST#_USH
@
+3.3V_RUN
1 2
POR_EXTR
1 2
RST_N
SPI_RST
JTCE_USH
1 2
C594
680P_0402_50V7K
R476
5.1M_0402_5%~D
R488
3.3M_0402_5%~D
Function
Boot SRC
REF CLK
PLTRST3#_R
LPC_EN_R
IRQ_SERIRQ_R
RFREADER_RXN RXN_F
RFREADER_RXP RFREADER_RXP_F
BCM5880
HF_RFIDTAG_AVDD2P5
HF_RFIDTAG_AVDD2P5
HF_RFIDTAG_DVDD1P2
HF_RX_ADC_AVDD1P2
HF_RX_AVDD1P2
HF_RX_AVDD2P5
HF_TX_AVDD1P2
HF_TX_AVDD2P5
HF_TX_AVDD3P3
HF_RFIDTAG_AVSS
HF_RFIDTAG_VREF
HF_RFIDTAG_VRX_N
HF_RFIDTAG_VRX_P
HF_RFIDTAG_VTX
HF_RX_TEST0
HF_RX_TEST1
HF_RX_TEST2
HF_RX_TEST3
HF_RX_N
RDIF
HF_RX_P
HF_TX_N
HF_TX_P
HF_RFIDTAG_AVSS
HF_RFIDTAG_AVSS
HF_RFIDTAG_DVSS
HF_RX_ADC_AVSS1
HF_RX_ADC_AVSS2
HF_RX_AVSS
HF_RX_AVSS
HF_TX_AVSS
HF_TX_AVSS
JTAG CLK
HF_TX_AVSS
BCM5880KFBG_FBGA225~D
LPD#
OVSTB
SBOOT
TAMPER_N
RST_N
SMC_ADD16
SC_USB#
12
FP_RESET#
00 01 10 11
24MHZ 27.12MHz 48MHz
1U_0402_6.3V6K~D
0.1U_0402_16V4Z~D
1
C625
2
1 2
C639 1U_0603_10V6K~D
1 2
C643 1U_0603_10V6K~D
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
1 2
R473 1K_0402_5%~D
1 2
R483 4.7K_0402_5%~D7@
1 2
R737 1K_0402_5%~D
1 2
R479 4.7K_0402_5%~D
1 2
R950 4.7K_0402_5%~D@
Pull-downs for 5880
Rev A0, and pull-ups
for Rev B0
+1.2V_RUN_AVDD +3.3V_RUN
BLM18BB100SN1D_0603~D
12
L37
1U_0603_10V4Z~D
C626
1
C627
2
RFREADER_TXN1
RFREADER_TXP1
1 2
150P_0402_50V8J~D
1
2
1 2
150P_0402_50V8J~D
1
2
+RFID_AVDD2P5
A7
F7
+RFID_AVDD1P2
C6
E10
F9
G9
D8
A8
+RFID_AVDD3P3
D9
B6
A6
C7
B7
E7
B10
C10
A11
A12
C11
B11
C9
B9
C8
D7
A5
E9
G10
F10
A10
A9
B8
E8
BBCLK
LPC_EN_R
JTAG_RST#_USH
SMC_ADD15
SBOOT
+RFID_AVDD1P2 +RFID_AVDD3P3
1U_0402_6.3V6K~D
2
C628
1
L71 150NH_LLQ1608-FR15G_2%~D
C641
L72 150NH_LLQ1608-FR15G_2%~D
C647
C595
+RF_VREF
0.01U_0402_25V7K~D
RFTAG_VRXN
RFTAG_VRXP
RFREADER_RXN
RFREADER_RXP
RFREADER_TXN1
RFREADER_TXP1
SMC_ADD18
SMC_ADD17
USBH_OC0#
USBH_OC1#
1
2
68P_0402_50V8J~D
1
2
68P_0402_50V8J~D
1
2
1 2
+3.3V_RUN
0.1U_0402_16V4Z~D
C1172
C1173
C1022
2
1
PRES
U32A
M7
LCLK
R6
LPCEN
N5
GPIO_17/LRESET_N
P5
GPIO_18/LFRAME_N
M6
GPIO_19/LSERIRQ
R5
GPIO_20/LAD[0]
N6
GPIO_21/LAD[1]
N7
GPIO_22/LAD[2]
P6
GPIO_23/LAD[3]
P7
GPIO_24/LPCPD_N
B5
GPIO_0/UART_RX
B4
GPIO_1/UART_TX
D6
GPIO_2/UART_CTS
A4
GPIO_3/UART_RTS
C5
GPIO_6/SSP_CLK
B3
GPIO_7/SSP_FSS
D5
GPIO_8/SSP_RXD
A3
GPIO_9/SSP_TXD
C4
GPIO_14
A2
GPIO_15
D4
GPIO_16
R13
USBD_DN
R14
USBD_UP
P14
GPIO_27/USBD_ATATCH
N11
USBH_DN0
N12
USBH_UP0
M11
USBH_OC_0
N13
USBH_DN1
P13
USBH_UP1
R15
USBH_OC_1
P8
GPIO_25/SC_SEL5V
R7
GPIO_26/SC_SEL18V
N15
SC_CINRUSH
L14
SC_CLK
L15
SC_VCC
K15
SC_RST
K14
SC_IO
J14
SC_FCB
J15
SC_FCB_ENB
M10
SC_DET
M15
SC_PWR
N14
1U_0402_6.3V6K~D
SC_PWR
C1023
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
2
2
C1013
1
1
19
VCC
26
VPC
29
VDD
15
VP
+LIN
27
LIN
TER_USBH_N1
23
DM
TER_USBH_P1
25
DP
SC_DET_PR SC_DET
14
SC_IO_R SC_IO
22
I/O
SC_C4_R SC_C4
21
AUX1
SC_C8_R SC_C8
20
AUX2
SC_CLK_R SC_CLK
16
CLK
18
RST
17
GND
28
GND
31
GND
SPI_TXD
SPI_CLK
SPI_RST
D76
CLK_PCI_TPM<6>
SP_TPM_LPC_EN<30,33>
PLTRST3#<21,22>
IRQ_SERIRQ<24,27,30,33,34>
SP_TPM_LPC_EN<30,33>
UART_RX/GPIO1
R948 0_0402_5%~D@
USBP10-<24>
B B
USBP10+<24>
TER_USBH_N1
TER_USBH_P1
BCM5880_SCCLK
T142PAD~D
1 2
R486 10M_0402_5%~D
@
Y5
1
IN
2
1
GND
C608
12P_0402_50V8J~D
2
27.12MHZ_12PF_1N227120CC0B~D
GPIO1_TER_ON/OFF
BCM5880_SCCLK
GPIO16_TER_TRIS
5880_GPIO26
5880_GPIO25
BCM5880_SCRST
BCM5880_SCDET
A A
+SC_VCC
0.47U_0402_10V4Z~D
10U_0805_10V4Z~D
2
1
@
C646
C1031
1
2
R973 300_0402_5%~D
1 2
+3.3V_RUN
3@
RB751S40T1_SOD523-2~D
21
R464 0_0402_5%~D@
1 2
R1072
1 2
0_0402_5%~D
1 2
R842 0_0402_5%~D
1 2
R466 0_0402_5%~D@
SC_DET
UART_RX/GPIO0
1 2
R468 22_0402_5%~D
R469 22_0402_5%~D
R470 1.5K_0402_5%~D
R768 22_0402_5%~D
R769 22_0402_5%~D
3
OUT
4
GND
GPIO2_TER_VDDMON
1 2
R771 1K_0402_5%~D
T139PAD~D
T63PAD~D
T64PAD~D
1 2
R490 47K_0402_1%~D@
1 2
R766 47K_0402_1%~D
1 2
R767 47K_0402_1%~D
R770 10K_0402_5%~D
BCM5880_IO
AUX1UC
AUX2UC
+3.3V_SC
SC_DET
SC_C8
SC_C4
SC_IO
SC_CLK
SC_RST
+SC_VCC
12
R849 1.5K_0402_5%~D
1 2
1 2
1 2
FP_USBD-<40>
FP_USBD+<40>
1 2
1 2
C600
@
680P_0402_50V7K
1 2
1 2
R472 10_0402_5%~D
1 2
R481 0_0402_5%~D
1 2
R487
0_0402_5%~D
XOXI
1
C609
15P_0402_50V8J~D
2
R20 47K_0402_1%~D@
SC_USB#
12
When using the 73S8009C,no-stuff R768,R769,R490
When using the 73S8009CN,stuff R768,R769,R490
12
GND
11
GND
10
10
9
9
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
TYCO_1-1775784-0
CLK_PCI_TPM
LPC_EN_R
PLTRST3#_R
LPC_LFRAME#_R
IRQ_SERIRQ_R
LPC_LAD0_R
LPC_LAD1_R
LPC_LAD2_R
LPC_LAD3_R
LPD#
UART_RX/GPIO0
UART_RX/GPIO1
GPIO2_TER_VDDMON
SC_DET_R
SPI_CLK
SPI_CS
SPI_RXD
SPI_TXD
GPIO1_TER_ON/OFF
BCM5880_GPIO15
GPIO16_TER_TRIS
USBP10-_R
USBP10+_R
FP_USBDFP_USBD+
USBH_OC0#
USBH_N1
USBH_P1
USBH_OC1#
5880_GPIO25
5880_GPIO26
BCM5880_SCCLK_R
BCM5880_SCVCC
BCM5880_SCRST
BCM5880_IO
AUX1UC
AUX2UC
BCM5880_SCDET
+SC_PWR
REF_XOUT
REF_XIN
1 2
24
7
8
9
11
12
13
4
5
6
32
10
30
1
2
3
JSC1
1U_0402_6.3V6K~D
2
1
+8009_VDDMON
U33
ON/OFF
CLKIN
RDY
OFF_ACK
OFF_REQ
CS
SC_USB#
CMDVCC5#
CMDVCC3#
RSTIN
OFF#
TEST1
TEST2
I/OUC
AUX1UC
AUX2UC
73S8009CN-32IMR/F_QFN32_5X5~D
+3.3V_RUN
1
C629
2
RFTAG_VRXN
+1.2V_VDDC_5880
+3.3V_RUN
BBCLK
12
R471 0_0402_5%~D
TAMPER_N
+3.3V_RUN
4.7K_0402_5%~D
4.7K_0402_5%~D
@
R819
R475
1 2
1 2
4.7K_0402_5%~D
4.7K_0402_5%~D
R820
@
R482
1 2
1 2
BLM18BB100SN1D_0603~D
12
L38
3.3U_0603_10V4Z~D
2
C630
1
2 3
1 2
R496 4.12K_0402_1%~D
1 2
R497 4.12K_0402_1%~D
2 3
1 2
1 2
1U_0402_6.3V6K~D
BAS40-04_SOT23-3~DD29
C13
E5
F5
J11
K11
K6
K7
K9
N4
P4
E6
F6
G5
H5
J5
K8
L7
K5
L5
L6
L13
M14
K13
H14
H15
H13
H12
J13
L8
L9
L10
L11
4.7K_0402_5%~D
R844
@
4.7K_0402_5%~D
R846
C631
BAS40-04_SOT23-3~DD28
1
1
1
U32C
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDO_VAR
VDDO_VAR
VDDO_SMC
VDDO_SMC
VDDO_SMC
VDDO_LPC
VDDO_LPC
VDDO_33CORE
VDDO_33CORE
VDDO_33CORE
VDDO_33SC
VDDO_33SC
VDDO_SC
V3P3_BBLCLK
V3P3_PWRGOOD
V3P3_TAMPER_N
VDD_BB
VDD_BB
VESD
VDDO_33
VDDO_33
VDDO_33
4.7K_0402_5%~D
R845
1 2
4.7K_0402_5%~D
@
R847
1 2
1
2
RFTAG_VRXP_FRFTAG_VRXP
1
BCM5880
CONTACTLESS_DET#<24>
@
1 2
CORE_CINRUSH
CORE_PWRDN
ALDO_PWRDN
AVDD33_LDO25
AVDD_2P5I
AVDD_2P5O
AVDD25_ldo12
AVDD25_ldo12
AVDD_1P2O
AVDD_1P2I_AUX
AVDD_1P2I_REF
AVDD25_PLL
OTP_PWR
AVSS_LDO12
AVSS_ldo25
AVSS_ldo25
AVSS_AUX
AVSS_REF
AVSS_PLL
BCM5880KFBG_FBGA225~D
+3.3V_RUN
0.1U_0402_16V4Z~D
C632
+3.3V_RUN
RFREADER_TXN1_P1
C640 1U_1206_100V4Z~D
C642 1U_1206_100V4Z~D
RFREADER_TXP1_P1
+3.3V_RUN
+2.5V_RUN_AVDD
0.1U_0402_16V4Z~D
1
1
C612
2
2
0.1U_0402_16V4Z~D
1
1
C635
2
2
Hardware enable for USH TPM:Populate D70 & R841,
No Stuff R483.
Hardware disable for USH TPM:No Stuff D70 &
R841, Populate R483
ANT_RFTAG_VRXN_RRFTAG_VRXN_F
1 2
ANT_RFTAG_VRXP_R
1 2
CONTACTLESS_DET#
R4
M5
D10
A14
G12
B13
A13
B12
E11
E13
F13
D14
P15
F11
C12
D11
C15
E15
C14
G11
VSS
G6
VSS
G7
VSS
G8
VSS
H10
VSS
H11
VSS
H6
VSS
H7
VSS
H8
VSS
H9
VSS
J10
VSS
J12
VSS
J6
VSS
J7
VSS
J8
VSS
J9
VSS
K10
VSS
K12
VSS
L12
VSS
M13
VSS
F8
VSS
0.1U_0402_16V4Z~D
1
2
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
1
C614
C613
2
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
1
C636
C637
2
C591 680P_0402_50V7K
1 2
R463 2.2K_0402_5%~D
1 2
R465 4.7K_0402_5%~D
+2.5V_RUN_AVDD
+3.3V_RUN
+1.2V_RUN_AVDD
+1.2V_RUN_PLL
+OTP_PWR
@
R467 0_0603_5%~D
R829 0_0603_5%~D
+1.2V_VDDC_5880
0.1U_0402_16V4Z~D
1
2
0.1U_0402_16V4Z~D
1
2
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
1
1
C605
1
2
1
2
2
0.1U_0402_16V4Z~D
C615
0.1U_0402_16V4Z~D
C638
C606
2
0.1U_0402_16V4Z~D
1
C616
2
0.1U_0402_16V4Z~D
1
C875
2
1
2
3
4
5
6
7
8
TYCO_2041070-6
C607
JCS1
1
2
3
4
5
6
GND
GND
1
2
1
2
C596
C873
DELL CONFIDENTIAL/PROPRIETARY
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
USH I/F
LA-4151P
4.7U_0603_6.3V6M~D
Place
1
C1019
close
to
pinA14
2
12
+3.3V_RUN
12
+SC_PWR
0.1U_0402_16V4Z~D
1
C597
2
1
C877
2
0.1U_0402_16V4Z~D
1
C618
2
10U_0603_6.3V6M~D
1
C1018
2
0.1U_0402_16V4Z~D
1
C598
C599
2
10U_0603_6.3V6M~D
C1020
+1.2V_RUN_AVDD
0.1U_0402_16V4Z~D
1
C601
2
0.1U_0402_16V4Z~D
1
C619
2
32 57Friday, July 04, 2008
0.1U_0402_16V4Z~D
1
C602
2
1.0
of
0.1U_0402_16V4Z~D
1
2
0.1U_0402_16V4Z~D
1
2
4.7U_0603_6.3V6M~D
1
C1021
2
0.1U_0402_16V4Z~D
C617
4.7U_0603_6.3V6M~D
C1017
5
+3.3V_ALW
1 2
R501 10K_0402_5%~D
1 2
R503 4.7K_0402_5%~D
1 2
R862 100K_0402_5%~D
1 2
R991 100K_0402_5%~D
1 2
D D
C C
B B
A A
R1099 100K_0402_5%~D
+3.3V_RUN
1 2
R874 100K_0402_5%~D@
1 2
R788 10K_0402_5%~D@
1 2
R816 100K_0402_5%~D
R505 100K_0402_5%~D
R1069 10K_0402_5%~D
+3.3V_ALW2
1 2
R502 10K_0402_5%~D
1 2
R504 10K_0402_5%~D
1 2
R1013 100K_0402_5%~D
INSTANT_ON_SW#<34,38>
12
12
BID0
BID1
BID2
CHIPSET_ID0
CHIPSET_ID1
PCIE_WAKE#
SLICE_BAT_PRES#
DCIN_CBL_DET#
CELL_CHARGER_DET#
PWR_BTN_BD_DET#
WIRELESS_ON#/OFF
SP_TPM_LPC_EN
LCD_TST
PANEL_BKEN_MCH
SYS_LED_MASK#
USB_SIDE_EN#
ESATA_USB_PWR_EN#
USB_POWERSHARE_PWR_EN#
RB751S40T1_SOD523-2~D
1 2
R1070 0_0402_5%~D@
10K_0402_5%~D
10K_0402_5%~D
@
@
R530
R529
1 2
1 2
5
1 2
+3.3V_RUN
R882
100K_0402_5%~D
1 2
DET_PCCRD_EXPSCRD#
PBAT_PRES#<41>
SCRL_LED#<38>
NUM_LED#<38>
DCIN_CBL_DET#<41>
PBATT_OFF<48>
SYS_PME#<27>
USB_POWERSHARE_PWR_EN#<21>
D74
10K_0402_5%~D
R531
PCIE_WAKE#<21,28>
WIRELESS_ON#/OFF<21>
BT_RADIO_DIS#<30>
EXPRCRD_PWREN#<28>
EXPRCRD_STDBY#<28>
BC_INT#_ECE5028<34>
BC_DAT_ECE5028<34>
BC_CLK_ECE5028<34>
DET_PCCRD_EXPSCRD#<28>
EN_I2S_NB_CODEC<21>
CB_HWSPND#<27>
EN_DOCK_PWR_BAR<48>
ADAPT_OC<46>
ADAPT_TRIP_SET<46>
LCD_TST<19>
PSID_DISABLE#<41>
PANEL_BKEN_MCH<12>
DOCKED<21>
DOCK_DET#<31>
AUD_NB_MUTE<21>
CELL_CHARGER_DET#<21>
LCD_VCC_TEST_EN<19>
CCD_OFF<19>
AUD_HP_NB_SENSE<21>
ESATA_USB_PWR_EN#<29>
1.05V_RUN_ON<36>
HDDC_EN<26>
MODC_EN<26>
SLICE_BAT_PRES#<31,41,48>
PWR_BTN_BD_DET#<38>
LAN_DISABLE#_R<21>
CAP_LED#<38>
SYS_LED_MASK#<38>
CBUS_GRST#<27>
SIO_EXT_WAKE#<24>
ICH_PME#<22>
ICH_PCIE_W AKE#<24>
WLAN_RADIO_DIS#<21>
WWAN_RADIO_DIS#<21>
INSTANT_ON_SW_D#INSTANT_ON_SW#
21
10K_0402_5%~D
10K_0402_5%~D
@
R533
R532
1 2
1 2
R534 10K_0402_5%~D
R535 10K_0402_5%~D
R536 10K_0402_5%~D @
R537 10K_0402_5%~D
R538 10K_0402_5%~D @
R526 0_0402_5%~D
+3.3V_ALW
1 2
1 2
1 2
1 2
1 2
4
PBAT_PRES#
SCRL_LED#
NUM_LED#
DCIN_CBL_DET#
PBATT_OFF
SYS_PME#
PCIE_WAKE#
USB_POWERSHARE_PWR_EN#
BT_RADIO_DIS#
EXPRCRD_PWREN#
EXPRCRD_STDBY#
BC_INT#_ECE5028
BC_DAT_ECE5028
BC_CLK_ECE5028
DET_PCCRD_EXPSCRD#
USB_SIDE_EN#
EN_I2S_NB_CODEC
CB_HWSP ND#
EN_DOCK_PWR_BAR
ADAPT_OC
ADAPT_TRIP_SET
LCD_TST
PSID_DISABLE#
PANEL_BKEN_MCH
DOCKED
DOCK_DET#
AUD_NB_MUTE
CELL_CHARGER_DET#
LCD_VCC_TEST_EN
CCD_OFF
AUD_HP_NB_ SENSE
ESATA_USB_PWR_EN#
LID_CL_SIO#
1.05V_RUN_ON
INSTANT_ON_SW_D#
HDDC_EN
MODC_EN
SLICE_BAT_PRES#
PWR_BTN_BD_DET#
LAN_DISABLE#_R
CAP_LED#
SYS_LED_MASK#
CBUS_GRST#
1 2
ICH_PME#
ICH_PCIE_W AKE#
WLAN_RADIO_DIS#
WWAN_RADIO_DIS#
VGA_IDENTIFY
CHIPSET_ID1
R528
10K_0402_5%~D
CHIPSET_ID0
BID2
BID1
BID0
12
00
0
0
1X04
1
110
111
4
U35
97
GPIOA[0]
98
GPIOA[1]
99
GPIOA[2]
100
GPIOA[3]
101
GPIOA[4]
102
GPIOA[5]
103
GPIOA[6]
104
GPIOA[7]
24
GPIOH[0]
25
GPIOH[1]
26
GPIOH[4]
27
GPIOH[5]
58
BC_INT#
59
BC_DAT
60
BC_CLK
1
GPIOE[0]/RXD
2
GPIOE[1]/TXD
3
GPIOE[2]/RTS#
4
GPIOE[3]/DSR#
5
GPIOE[4]/CTS#
84
GPIOE[5]/DTR#
83
GPIOE[6]/RI#
6
GPIOE[7]/DCD#
65
GPIOB[0]/INIT#
66
GPIOB[1]/SLCTIN#
67
GPIOC[2]/SCLT
68
GPIOC[3]/PE
69
GPIOC[4]/BUSY
70
GPIOC[5]/ACK#
71
GPIOC[6]/ERROR#
73
GPIOC[7]/ALF#
74
GPIOD[0]/STROBE#
75
GPIOC[1]/PD7
76
GPIOC[0]/PD6
77
GPIOB[7]/PD5
78
GPIOB[6]/PD4
79
GPIOB[5]/PD3
80
GPIOB[4]/PD2
81
GPIOB[3]/PD1
82
GPIOB[2]/PD0
61
GPIOD[1]
62
GPIOD[2]
63
GPIOD[3]/VBUS_DET
28
GPIOD[4]/OCS1_N
29
GPIOD[5]/OCS2_N
30
GPIOD[6]/OCS3_N
31
GPIOD[7]/OCS4_N
32
GPIOH[6]
33
GPIOH[7]
88
GPIOG[0]
89
GPIOG[1]
90
GPIOG[2]
91
GPIOG[3]
92
GPIOG[4]
93
GPIOG[5]
94
GPIOG[6]
95
GPIOG[7]
106
SYSOPT1/GPIOH[2]
107
SYSOPT0/GPIOH[3]
109
GPIOF[7]
110
GPIOF[6]
111
GPIOF[5]
112
GPIOF[4]
113
IRTX
114
IRRX
115
GPIOF[3]/IRMODE/IRRX3B
116
GPIOF[2]/IRTX2
117
GPIOF[1]/IRRX2
118
GPIOF[0]/IRMODE/IRRX3A
ECE5028-NU_VTQFP128_14X14~D
0
0
ECE5028-NU
BID0BID1BID2
REV
X00
000
X01
1
X021
0
11
X03
0
1 X05
X06
X07
+3.3V_ALW
34
57
85
108
VCC1
VCC1
VCC1
VCC1
(ECE5018)
USB
GPIO
TEST
CLK
LPC
DLPC
CHIPSET_ID0 CHIPSET_ID1
01
3
VCC1(VDDA33)
GPIOJ[7](VDDA33)
GPIOK[4](VDDA33)
GPIOI[1](VCC1)
GPIOJ[2](USBDP0)
GPIOJ[3](USBDN0)
GPIOJ[6](USBDP1)
GPIOJ[5](USBDN1)
GPIOK[0](USBDP2)
GPIOK[1](USBDN2)
GPIOK[3](USBDP3)
GPIOK[2](USBDN3)
GPIOK[5](USBDP4)
GPIOK[6](USBDN4)
GPIOI[6](VDDA33PLL)
GPIOI[5](VDDA18PLL)
GPIOI[2](VDD18)
CAP_LDO
GPIOJ[0](RBIAS)
TEST_PIN
GPIOI[7](ATEST)
GPIOI[4](XTAL1/CLKIN)
GPIOI[3](XTAL2)
LAD0
LAD1
LAD2
LAD3
LFRAME#
LRESET#
PCICLK
CLKRUN#
LDRQ0#
LDRQ1#
SER_IRQ
CLKI (14.318 MHz)
VSS
DLAD0
DLAD1
DLAD2
DLAD3
DLFRAME#
DCLK_RUN#
DLDRQ1#
DSER_IRQ
PWRGD
OUT65
GPIOJ[4](VSS)
VSS
GPIOK[7](VSS)
VSS
VSS
VSS
VSS
VSS
GPIOJ[1](VSS)
1
C648
0.1U_0402_16V4Z~D
2
8
14
20
119
9
10
13
12
15
16
19
18
21
22
125
124
120
+CAP_LDO
86
127
35
126
123
122
54
52
49
47
42
41
56
37
46
44
39
64
96
55
53
50
48
43
38
45
40
7
105
11
17
23
36
51
72
87
121
128
DOCK_MIC_DET
MCH_TSATN_EC
1.8V_RUN_ON
SNIFFER_BLUE#
SNIFFER_YELLOW#WIRELESS_ON#/OFF
DOCK_HP_DET
CRT_SWITCH
ME_FWP
NB_AC_OFF
2.5V_RUN_PWRGD
RUN_ON
1.5V_RUN_ON
R509 0_0402_5%~D
1 2
IMVP_PWRGD
0.75V_DDR_VTT_ON
8mil
12
R514
1K_0402_5%~D
DOCK_AC_OFF_EC
SIO_SLP_S3#
3.3V_RUN_ON
LPC_LAD0
LPC_LAD1
LPC_LAD2
LPC_LAD3
LPC_LFRAME#
PLTRST2#
CLK_PCI_5028
CLKRUN#
LPC_LDRQ0#
LPC_LDRQ1#
IRQ_SERIRQ
CLK_SIO_14M
D_LAD0
D_LAD1
D_LAD2
D_LAD3
D_LFRAME#
D_CLKRUN#
D_DLDRQ1#
D_SERIRQ
RUNPWROK
SP_TPM_LPC_EN
GPIO_PSID_SELECT
1
SPI_WP#_SEL
C657
4.7U_0603_6.3V4Z~D
2
TP_DET#
1
C652
0.1U_0402_16V4Z~D
2
2
1
C649
0.1U_0402_10V7K~D
2
DOCK_MIC_DET <21>
MCH_TSATN_EC <10>
1.8V_RUN_ON <44>
SNIFFER_BLUE# <38>
SNIFFER_YELLOW# <38>
DOCK_HP_DET <21>
CRT_SWITCH <20>
ME_FWP <23>
NB_AC_OFF <41,46,48>
2.5V_RUN_PWRGD <18,37>
RUN_ON <19,21,36,37,39>
1.5V_RUN_ON <36>
IMVP_VR_ON <45>
IMVP_PWRGD <24,37,45,47>
0.75V_DDR_VTT_ON <44>
ACAV_IN_NB <34,46>
ACAV_IN_NB
SIO_SLP_S3# <24>
3.3V_RUN_ON <36,39>
LPC_LFRAME# <23,30,32,34>
PLTRST2# <22,34>
CLK_PCI_5028 <6>
CLKRUN# <24,27,30,34>
LPC_LDRQ0# <23>
LPC_LDRQ1# <23>
IRQ_SERIRQ <24,27,30,32,34>
CLK_SIO_14M <6>
D_LAD0 <31>
D_LAD1 <31>
D_LAD2 <31>
D_LAD3 <31>
D_LFRAME# <31>
D_CLKRUN# <31>
D_DLDRQ1# <31>
D_SERIRQ <31>
RUNPW ROK <34,37,45>
SP_TPM_LPC_EN <30,32>
GPIO_PSID_SELECT <41>
SPI_WP#_SEL <24>
TP_DET# <35>
+3.3V_ALW
1
2
LPC_LAD[0..3] <23,30,32,34>
Note
SFF
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
+3.3V_ALW
0.1U_0402_16V4Z~D
1
C653
2
C1161 0.1U_0402_16V4Z~D
1 2
5
P
IN1
DOCK_AC_OFF_R
4
O
IN2
G
U96
74AHC1G08GW_SOT353-5~D
3
ME_FWP
1
1
C650
0.1U_0402_16V4Z~D
2
R1078 0_0402_5%~D@
1 2
2 1
D78 RB751S40T1_SOD523-2~D
+3.3V_RUN
R648
10K_0402_5%~D
1 2
R649
@
10K_0402_5%~D
1 2
+3.3V_ALW
12
LID_CL_SIO# LID_CL#
1
2
1
C651
0.1U_0402_16V4Z~D
2
SNIFFER_BLUE#
SNIFFER_YELLOW#
TP_DET#
INSTANT_ON_SW_D#
D_CLKRUN#
D_SERIRQ
D_DLDRQ1#
RUN_ON
1.5V_RUN_ON
1.05V_RUN_ON
3.3V_RUN_ON
0.75V_DDR_VTT_ON
PBATT_OFF
VGA_IDENTIFY
1.8V_RUN_ON
DOCK_AC_OFF <31,48>
R1079
33K_0402_1%~D
1 2
10_0402_5%~D
4.7P_0402_50V8C~D
R524
1M_0402_5%~D
R525
10_0402_5%~D
C655
0.047U_0402_16V4Z~D
R507 100K_0402_5%~D@
R508 100K_0402_5%~D@
R756 100K_0402_5%~D
R1080 100K_0402_5%~D
R510 100K_0402_5%~D
R511 100K_0402_5%~D
R512 100K_0402_5%~D
R515 100K_0402_5%~D
R516 100K_0402_5%~D
R518 100K_0402_5%~D
R519 100K_0402_5%~D
R520 100K_0402_5%~D
R521 100K_0402_5%~D
R522 100K_0402_5%~D
R951 100K_0402_5%~D
R506
@
C654
@
12
12
12
12
12
12
12
12
12
12
12
12
12
12
1 2
1 2
CLK_PCI_5028CLK_SIO_14M
12
10_0402_5%~D
1
4.7P_0402_50V8C~D
2
@
@
LID_CL# <29,38>
DELL CONFIDENTIAL/PROPRIETARY
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
ECE5028
LA-4151P
33 57Fr id ay, July 04, 2008
1
+3.3V_ALW
R527
C656
of
+3.3V_RUN
12
1
2
1.0
5
+3.3V_ALW
R540 2.2K_0402_5%~D
R542 2.2K_0402_5%~D
D D
C C
B B
A A
R543 100K_0402_5%~D
R545 100K_0402_5%~D
R546 100K_0402_5%~D
R547 10K_0402_5%~D
R548 8.2K_0402_5%~D
R549 8.2K_0402_5%~D
R551 2.2K_0402_5%~D
R552 2.2K_0402_5%~D
R557 100K_0402_5%~D5@
R837 100K_0402_5%~D@
R838 2.2K_0402_5%~D
R839 2.2K_0402_5%~D
R974 10K_0402_5%~D
R1026 2.2K_0402_5%~D 5@
R1027 2.2K_0402_5%~D5@
R1082 1M_0402_5%~D
R561 1M_0402_5%~D
1 2
R563 2.7K_0402_5%~D
1 2
R564 100K_0402_5%~D
1 2
R566 100K_0402_5%~D
1 2
R568 100K_0402_5%~D
JDEG1
@
5
5
4
4
3
3
2
2
1
1
Molex_53261
JP2
@
1
2
7
3
G1
8
4
G2
5
6
ACES_85204-06001~D
32 KHz Clock
Same as Laguna
MEC5035_XTAL1
32.768K_12.5P_1TJS125DJ4A420P~D
MEC5035_XTAL2
CKG_SMBDAT
1 2
CKG_SMBCLK
1 2
BC_DAT_ECE5028
1 2
BC_DAT_EMC4002
12
BC_DAT_ECE1077
12
DOCK_SMB_ALERT#
12
LCD_SMBCLK
1 2
LCD_SMBDAT
1 2
PBAT_SMBDAT
1 2
PBAT_SMBCLK
1 2
BC_DAT_ECE1088
12
LPC_LDRQ#_MEC5035
12
CARD_SMBDAT
1 2
CARD_SMBCLK
1 2
HOST_DEBUG_TX
12
BKT_SMBDAT
1 2
BKT_SMBCLK
1 2
DOCK_POR_RST#
12
M_ON
12
AUX_ON
DDR_ON
SUS_ON
ICH_ALW
+3.3V_ALW
100K_0402_5%~D
R574
1 2
MSDATA
MSCLK
1 2
R577 0_0402_5%~D
+3.3V_ALW
10K_0402_5%~D
49.9_0402_1%~D
12
12
R581
R580
1
2
3
4
5
6
Y4
27P_0402_50V8J~D
1
C674
2
10K_0402_5%~D
12
R575
10K_0402_5%~D
12
R582
14
23
1
2
10K_0402_5%~D
12
R576
HOST_DEBUG_RX
10K_0402_5%~D
10K_0402_5%~D
12
R583
R584
1 2
JTAG_TDI
JTAG_TMS
JTAG_CLK
JTAG_TDO
22P_0402_50V8J~D
C675
BC_CLK_ECE5028<33>
Place closely pin 58
CLK_PCI_5035
R588
@
10_0402_5%~D
C673
@
4.7P_0402_50V8C~D
PBAT_SMBDAT<41>
PBAT_SMBCLK<41>
DOCK_POR_RST#<31>
KYBRD_BKLT_PWM<35>
BC_CLK_EMC4002<18>
BC_DAT_EMC4002<18>
BC_INT#_EMC4002<18>
BC_INT#_ECE1088<35>
BC_DAT_ECE1088<35>
BC_CLK_ECE1088<35>
BC_INT#_ECE1077<35>
BC_DAT_ECE1077<35>
BC_CLK_ECE1077<35>
BC_INT#_ECE5028<33>
BC_DAT_ECE5028<33>
IRQ_SERIRQ<24,27,30,32,33>
LPC_LFRAME#<23,30,32,33>
MEC5035_XTAL2
EC_32KHZ_OUT<18>
12
1
2
CLK_TP_SIO<35>
DAT_TP_SIO<35>
CLK_KBD<31>
DAT_KBD<31>
CLK_MSE<31>
DAT_MSE<31>
SUS_ON<36,37>
BREATH_LED#<31,38>
ICH_ALW<36>
SIO_EXT_SMI#<24>
SIO_RCIN#<23>
PLTRST2#<22,33>
CLK_PCI_5035<6>
LPC_LAD0<23,30,32,33>
LPC_LAD1<23,30,32,33>
LPC_LAD2<23,30,32,33>
LPC_LAD3<23,30,32,33>
CLKRUN#<24,27,30,33>
SIO_EXT_SCI#<24>
4
+RTC_CELL
CLK_TP_SIO
DAT_TP_SIO
CLK_KBD
DAT_KBD
CLK_MSE
DAT_MSE
PBAT_SMBDAT
PBAT_SMBCLK
JTAG_TDI
JTAG_TDO
JTAG_CLK
JTAG_TMS
JTAG_RST#
C1167
0.1U_0402_16V4Z~D
1 2
DOCK_POR_RST#
SUS_ON
BREATH_LED#
ICH_ALW
KYBRD_BKLT_PWM
BC_CLK_EMC4002
BC_DAT_EMC4002
BC_INT#_EMC4002
BC_INT#_ECE1088
BC_DAT_ECE1088
BC_CLK_ECE1088
BC_INT#_ECE1077
BC_DAT_ECE1077
BC_CLK_ECE1077
BC_INT#_ECE5028
BC_DAT_ECE5028
BC_CLK_ECE5028
SIO_EXT_SMI#
SIO_RCIN#
LPC_LDRQ#_MEC5035
IRQ_SERIRQ
PLTRST2#
CLK_PCI_5035
LPC_LFRAME#
LPC_LAD0
LPC_LAD1
LPC_LAD2
LPC_LAD3
CLKRUN#
SIO_EXT_SCI#
MEC5035_XTAL1
12
R587 0_0402_5%~D
1 2
R544
0_0402_5%~D
U36
PS/2 INTERFACE
9
GPIO007/I2C1D_DATA/PS2_CLK0B
10
GPIO010/I2C1D_CLK/PS2_DAT0B
75
GPIO110/PS2_CLK2/GPTP-IN6
76
GPIO111/PS2_DAT2/GPTP-OUT6
77
GPIO112/PS2_CLK1A
78
GPIO113/PS2_DAT1A
79
GPIO114/PS2_CLK0A
80
GPIO115/PS2_DAT0A
111
GPIO154/I2C1C_DATA/PS2_CLK1B
112
GPIO155/I2C1C_CLK/PS2_DAT1B
JTAG INTERFACE
102
GPIO145/I2C1K_DATA/JTAG_TDI
103
GPIO146/I2C1K_CLK/JTAG_TDO
105
GPIO147/I2C1J_DATA/I2C2C_DATA/JTAG_CLK
106
GPIO150/I2C1J_CLK/I2C2C_CLK/JTAG_TMS
107
JTAG_RST#
FAN PWM & TACH
41
GPIO050/FAN_TACH1
42
GPIO051/FAN_TACH2
43
GPIO052/FAN_TACH3
45
GPIO053/PWM0
46
GPIO054/PWM1
47
GPIO055/PWM2
48
GPIO056/PWM3
BC-LINK
23
GPIO022/BCM_B_CLK/V_CLK
24
GPIO023/BCM_B_DAT/V_DATA
25
GPIO024/BCM_B_INT#/V_FRAME
35
GPIO042/BCM_C_INT#
36
GPIO043/BCM_C_DAT
37
GPIO044/BCM_C_CLK
38
GPIO045/LSBCM_D_INT#
39
GPIO046/LSBCM_D_DAT
40
GPIO047/LSBCM_D_CLK
85
GPIO121/BCM_A_INT#
86
GPIO122/BCM_A_DAT
87
GPIO123/BCM_A_CLK
HOST INTERFACE
11
GPIO011/nSMI
54
GPIO061/LPCPD#
55
LDRQ#
56
SER_IRQ
57
LRESET#
58
PCI_CLK
59
LFRAME#
60
LAD0
61
LAD1
62
LAD2
63
LAD3
64
CLKRUN#
66
GPIO100/nEC_SCI
MASTER CLOCK
122
XTAL1
124
XTAL2
117
GPIO160/32KHZ_OUT
BLM18AG121SN1D_0603~D
L39
+RTC_CELL_VBAT
1
C660
0.1U_0402_16V4Z~D
2
AGND
VSS[1]26VSS[2]51VSS[3]74VSS[4]88VSS[5]
125
15mil
+5035_AGND
12
+3.3V_ALW
121
VBAT
20
113
116
104
VTR[1]21VTR[2]44VTR[3]65VTR[4]83VTR[5]
VTR[6]
GPIO012/I2C1H_DATA/I2C2D_DATA
GPIO141/I2C1F_DATA/I2C2B_DATA
VSS[7]
VSS[8]
VR_CAP[1]22VSS_RO
53
101
+VR_CAP
+5035_VSS
1
8mil
C671
2
4.7U_0603_6.3V4Z~D
3
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
C661
1
1
C662
2
2
52
VTR[7]4VTR[8]
MISC INTERFACE
GPIO021/RC_ID
GPIO025/UART_CLK
VCC_PRWGD
GPIO060/KBRST
GPIO101/ECGP_SCLK
GPIO102/ECGP_SOUT
GPIO103/ECGP_SIN
GPIO104/UART_TX
GPIO105/UART_RX
GPIO106/nRESET_OUT
GPIO116/MSDATA
GPIO117/MSCLK
GPIO127/A20M
GPIO153/LED3
GPIO156/LED1
GPIO157/LED2
nFWP
GENERAL PURPOSE I/O
SMBUS INTERFACE
GPIO013/I2C1H_CLK/I2C2D_CLK
GPIO142/I2C1F_CLK/I2C2B_CLK
DELL PWR SW INF
129
15mil
GPIO001
GPIO002
GPIO014/GPTP-IN7
GPIO015/GPTP-OUT7
GPIO016/GPTP-IN8
GPIO017/GPTP-OUT8
GPIO020
GPIO26/GPTP-IN1
GPIO27/GPTP-OUT1
GPIO30/GPTP-IN2
GPIO31/GPTP-OUT2
GPIO032/GPTP-IN3
GPIO040/GPTP-OUT3
GPIO041
GPIO107
GPIO120
GPIO124/GPTP-OUT5
GPIO125/GPTP-IN5
GPIO126
GPIO151/GPTP-IN4
GPIO152/GPTP-OUT4
GPIO003/I2C1A_DATA
GPIO004/I2C1A_CLK
GPIO005/I2C1B_DATA
GPIO006/I2C1B_CLK
GPIO130/I2C2A_DATA
GPIO131/I2C2A_CLK
GPIO132/I2C1G_DATA
GPIO140/I2C1G_CLK
GPIO143/I2C1E_DATA
GPIO144/I2C1E_CLK
BGPO0
VCI_IN2#
VCI_OUT
VCI_IN1#
VCI_IN0#
VCI_OVRD_IN
VCI_IN3#
thermal GND
MEC5035_XVTQFP128_14X14~D
1 2
L40
BLM18AG121SN1D_0603~D
10U_0805_10V4Z~D
1
C663
2
19
27
49
50
67
68
69
70
71
72
81
82
92
110
114
115
123
2
3
14
15
16
17
18
28
29
30
31
32
33
34
73
84
89
90
91
108
109
5
6
7
8
12
13
93
94
95
96
97
98
99
100
118
119
120
126
127
128
1
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
1
1
C665
C664
2
2
RC_ID
DDR_ON
RUNPWROK
ICH_LAN_RST#
HOST_DEBUG_TX
HOST_DEBUG_RX
RESET_OUT#
MSDATA
MSCLK
SIO_A20GATE
PS_ID
BAT1_LED#
BAT2_LED#
FWP#
SIO_SLP_M#
DOCK_SMB_ALERT#
ME_WOL_EN
ME_SUS_PWR_ACK
1.5V_SUS_PWRGD
ICH_CL_PWROK
3.3V_LAN_PWRGD
1.05V_M_PWRGD
ALW_PWRGD_3V_5V
SUSPWROK
SIO_SLP_S5#
BEEP
AUX_ON
3.3V_M_PWRGD
AUX_EN_WOWL
SIO_SLP_S4#
M_ON
ICH_RSMRST#
AC_PRESENT
SIO_PWRBTN#
DOCK_SMB_DAT
DOCK_SMB_CLK
LCD_SMBDAT
LCD_SMBCLK
CKG_SMBDAT
CKG_SMBCLK
AMT_SMBDAT
AMT_SMBCLK
ACAV_IN_NB
CARD_SMBDAT
CARD_SMBCLK
BKT_SMBDAT
BKT_SMBCLK
SNIFFER/INSTANT_SW#
ALWON
EN_CELL_CHARGER_DET#
POWER_SW_IN#
ACAV_IN
DOCK_PWR_SW#
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
1
1
C667
C666
2
2
DDR_ON <10,36,44>
RUNPWROK <33,37,45>
ICH_LAN_RST# <24>
HOST_DEBUG_TX <21>
HOST_DEBUG_RX <21>
RESET_OUT# <37>
MSDATA <21>
MSCLK <21>
SIO_A20GATE <23>
PS_ID <41>
BAT1_LED# <38>
BAT2_LED# <38>
SIO_SLP_M# <24>
DOCK_SMB_ALERT# <31,41>
ME_WOL_EN <24>
ME_SUS_PWR_ACK <24>
1.5V_SUS_PWRGD <10,43>
ICH_CL _PWROK <10,24>
3.3V_LAN_PWRGD <37>
1.05V_M_PW RGD <43>
ALW_PWRGD_3V_5V <42>
SUSPWROK <37>
SIO_SLP_S5# <24>
BEEP <21>
AUX_ON <36>
3.3V_M_PWRGD <18,37>
AUX_EN_WOWL <30>
SIO_SLP_S4# <10,24>
M_ON <36>
ICH_RSMRST# <24>
AC_PRESENT <24>
SIO_PWRBTN# <24>
DOCK_SMB_DAT <31>
DOCK_SMB_CLK <31>
LCD_SMBDAT <19>
LCD_SMBCLK <19>
CKG_SMBDAT <6,21,46>
CKG_SMBCLK <6,21,46>
AMT_SMBDAT <24>
AMT_SMBCLK <24>
ACAV_IN _NB <33,46>
CARD_SMBDAT <21,28>
CARD_SMBCLK <21,28>
BKT_SMBDAT <39>
BKT_SMBCLK <39>
ALWON <42>
EN_CELL_CHARGER_DET# <21>
ACAV_IN <18,46>
0.1U_0402_16V4Z~D
1
C668
2
Bat2 = Amber LED
Bat1 = Blue LED
20mA drive pins
2
+RTC_CELL
12
R539
100K_0402_5%~D
+3.3V_ALW
FWP#
R1050
33K_0402_1%~D
1 2
4700P_0402_25V7K~D
1
C1151
2
1 2
C1011 0.1U_0402_16V4Z~D
INSTANT_ON_SW#
SNIFFER_PWR_SW#
POWER_SW_IN#
DOCK_PWR_SW#
R578
10K_0402_5%~D
1 2
R586
@
10K_0402_5%~D
1 2
JTAG_RST#
R541 1K_0402_5%~D
1
C659
1U_0603_10V4Z~D
2
+RTC_CELL
12
R550
100K_0402_5%~D
1 2
R554 1K_0402_5%~D
1
2
C670
1U_0603_10V4Z~D
EN_CELL_CHARGER_DET#
SNIFFER/INSTANT_SW#
+3.3V_ALW
R579
10K_0402_5%~D
1 2
R585
100_0402_1%~D
@
1 2
INSTANT_ON_SW# <33,38>
SNIFFER _PWR _SW# <21>
POWER_SW_IN#<18> POWER_SW#_MB <38>
+3.3V_ALW
RC_ID
+RTC_CELL
5
U57
P
IN1
4
O
IN2
G
74AHC1G08GW_SOT353-5~D
3
1 2
R1071 0_0402_5%~D@
1
2
1 2
INSTANT_ON_SW#
SNIFFER_PWR_SW#
DOCK_SMB_DAT
DOCK_SMB_CLK
CLK_KBD
DAT_KBD
CLK_MSE
DAT_MSE
AC_PRESENT
2
C1109
0.1U_0402_16V4Z~D
1
@SHORT PADS~D
1 2
C658
@
1U_0402_6.3V6K~D
1 2
C669
@
1U_0402_6.3V6K~D
R560 100K_0402_5%~D
R562 100K_0402_5%~D
R877 200K_0402_5%~D
D79 RB751S40T1_SOD523-2~D
R968 100K_0402_5%~D
R565 2.2K_0402_5%~D
R567 2.2K_0402_5%~D
R569 4.7K_0402_5%~D
R570 4.7K_0402_5%~D
R571 4.7K_0402_5%~D
R572 4.7K_0402_5%~D
R573 10K_0402_5%~D
JTAG1
1=JTAG interface Reset disabled
0=Reset JTAG interface
1
1 2
2 1
1 2
@
DOCK_PWR_BTN# <31>DOCK_PWR_SW#<18>
+RTC_CELL
12
12
12
+3.3V_ALW
12
12
+5V_RUN
12
12
12
12
1
1
2
2
DELL CONFIDENTIAL/PROPRIETA RY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
EMC5035
LA-4151P
1
34 57Friday, July 04, 2008
1.0
of
5
+3.3V_ALW
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
5@
1
2
D D
BC_DAT_ECE1088<34>
BC_CLK_ECE1088<34>
BC_INT#_ECE1088<34>
+3.3V_ALW
C C
BC_DAT_ECE1077<34>
BC_CLK_ECE1077<34>
BC_INT#_ECE1077<34>
+3.3V_ALW
+5V_TP_PWR
+5V_ALW
+3.3V_TP_PWR
KYBRD_BKLT_PWM<34>
B B
+5V_RUN_BKT_PWR
A A
+3.3V_RUN_BKT_PWR
TP_DET#<33>
+5V_RUN
+3.3V_RUN
R747 10K_0402_5%~D @
R650 10K_0402_5%~D5@
R826 10K_0402_5%~D 5@
TP_CLK
TP_DATA
KYBRD_BKLT_PWM
TP_DET#
PJP57 PAD-OPEN 4x4m6@
1 2
PJP58 PAD-OPEN 4x4m 5@
1 2
PJP59 PAD-OPEN 4x4m6@
1 2
PJP60 PAD-OPEN 4x4m5@
1 2
5@
1
C676
C677
2
BC_DAT_ECE1088
BC_CLK_ECE1088
BC_INT#_ECE1088
12
12
12
U38
5@
7
VCC
21
VCC
22
BC_DAT/SMB_DATA
23
BC_CLK/SMB_CLK
24
BC_INT#/SMB_INT#
25
SMB_ADDR
28
TEST
27
RESERVE
29
THER_PAD
JTP1
18
GND
17
GND
16
16
15
15
14
14
13
13
12
12
11
11
10
10
9
9
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
TYCO_1-2041070-6
+5V_TP_PWR
+3.3V_TP_PWR
ECE1088
ECE1088-FZG_QFN28_5X5~D
BKT_GPIO12
TP_CLK
TP_DATA
Place close to JTP1 connector
5
4
17
GPIO00
18
GPIO01
19
GPIO02
20
GPIO03
26
GPIO07
1
GPIO13
2
GPIO14
3
GPIO15
4
GPIO16
5
GPIO17
6
GPIO20
8
GPIO24
9
GPIO25
10
GPIO26
11
GPIO27
12
GPIO30
13
GPIO31
14
GPIO32
15
GPIO36
16
GPIO37
BKT_GPIO17
R1104 10K_0402_5%~D@
Normal mode BKT mode
+5V_TP_PWR
0.1U_0402_16V4Z~D
1
2
Place close to
JTP1.11
+3.3V_ALW
0.1U_0402_16V4Z~D
1
2
Place close to
JTP1.5,6
SD05.TCT_SOD323-2~D
@
D53
2 1
4
BKT_GPIO1
BKT_GPIO2
BKT_GPIO3
BKT_GPIO4
BKT_GPIO5
BKT_GPIO6
BKT_GPIO7
BKT_GPIO8
BKT_GPIO9
BKT_GPIO11
BKT_GPIO12
BKT_GPIO13
BKT_GPIO14
BKT_GPIO15
BKT_GPIO16
BKT_GPIO17
BKT_GPIO18
BKT_GPIO19
12
BKT_GPIO1 <40>
BKT_GPIO2 <39>
BKT_GPIO3 <40>
BKT_GPIO4 <39,40>
BKT_GPIO5 <39>
BKT_GPIO6 <39>
BKT_GPIO7 <39>
BKT_GPIO8 <39>
BKT_GPIO9 <39>
BKT_GPIO11 <40>
BKT_GPIO12 <21>
BKT_GPIO13 <21>
BKT_GPIO14 <19>
BKT_GPIO15 <39>
BKT_GPIO16 <39>
BKT_GPIO17 <29>
BKT_GPIO18 <19>
BKT_GPIO19 <39>
01
+5V_ALW
C678
1
2
Place close to
JTP1.12
+3.3V_TP_PWR
1
C771
2
Place close to
JTP1.13
SD05.TCT_SOD323-2~D
@
D54
2 1
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
+3.3V_ALW
0.1U_0402_16V4Z~D
C1112
0.1U_0402_16V4Z~D
C679
3
BKT_GPIO1
BKT_GPIO2
BKT_GPIO3
BKT_GPIO4
BKT_GPIO5
BKT_GPIO6
BKT_GPIO7
BKT_GPIO8
BKT_GPIO9
BKT_GPIO11
BKT_GPIO12
For LVDS signals switch
For BKT power switch
For TP power swich&USB signal switch
For AMP/TP power source&USB signal switch
For LID_Closed
For PAD_Out
For BKT Reset
For USB_SEL_BLK
For Radio_OFF
Biometric mux switch
For WLAN antenna mux control
RSB_DET#BKT_GPIO13
BKT_GPIO14
BKT_GPIO15
For Inverter Power
For WWAN Power
BKT_GPIO16 For SMBALERT
For Biometic reset signalBKT_GPIO17
BKT_GPIO18
BKT_GPIO19
TP_DATA
TP_CLK
1
2
3
10P_0402_50V8J~D
C680
For LVDS Power switch
For TP Power
L41
1 2
BLM18AG601SN1D_0603~D
1 2
L42
10P_0402_50V8J~D
BLM18AG601SN1D_0603~D
1
C681
2
2
RTC BATT@
Part Number Description
GC20323MX00
FAN@
Part Number Description
DC28A000800
Speak@
Part Number Description
PK230003Q0L
SM CARD BODY
Part Number Description
SP070007V0L
PCMCIA BODY
Part Number Description
DC000001Q0L
PWR cable@
Part Number Description
NBX00009O0L
LCD-LED cable@
Part Number Description
DC02000KC0L
LED cable@
Part Number Description
DA300003O0L
TOUCH PAD cable@
Part Number Description
NBX0000BA0L
Bluetooth cable@
+5V_ALW
R594
C682
4.7K_0402_5%~D
12
10P_0402_50V8J~D
1
2
R595
DAT_TP_SIO
CLK_TP_SIO
C683
DAT_TP_SIO <34>
CLK_TP_SIO <34>
4.7K_0402_5%~D
12
10P_0402_50V8J~D
1
2
Part Number Description
NBX00009L0L
SW cable@
Part Number Description
NBX0000BF0L
Finger print cable@
Part Number Description
NBX00009M0L
1
BATT CR2032 3V
220MAH MAXELL
FAN SET DAQ20 DC5V AB7405HB-HB3 ADDA
SPK PACK ZJX 2.0W 4 OHM FG
S SOCKET TYCO 1770551-1
10P H5.9 SMART
PCMCIA TYCO
1759096-1
FFC 4P G P.5
PAD=.3 79MM
MB-PWR_SW/B 03S
H-CONN SET 03S MB-LCD
FPC 03S LF-4151P REV0
M/B-LED/B
FFC 16P G P0.5
PAD=0.3 117MM
MB-TP 03S
FFC 12P F P0.5
PAD=0.3
76MM MB-BT/B 03S
FFC 12P A P1
PAD=0.6 L=83MM
03I
FFC 6P F P0.5
PAD=0.3 257.2MM
MB-FP 03S
DELL CONFIDENTIAL/PROPRIETARY
Title
Size Document Number Rev
2
Date: Sheet
Compal Electronics, Inc.
Touch PAD/Int KB/LID
LA-4151P
35 57Friday, July 04, 2008
1
1.0
of
5
DC/DC Interface
+15V_ALW
+3.3V_ALW2
12
R602
100K_0402_5%~D
D D
ICH_ALW<34>
C C
B B
A A
SUS_ON<34,37>
AUX_ON<34>
+3.3V_ALW
+5V_ALW
1 2
R1034 4.7K_0402_5%~D
1 2
R1004 4.7K_0402_5%~D
M_ON<34>
1 2
R1103 100K_0402_5%~D@
Q136B
Q136A
+3.3V_ALW2
2
+3.3V_ALW2
2
EN_1.05VALW
2N7002DW-7-F_SOT363-6~D
3
2N7002DW-7-F_SOT363-6~D
6 1
M_ON
ALW_ON_3.3V#
61
Q57A
2N7002DW-T/R7_SOT363-6~D
2
+3.3V_ALW2
12
R604
100K_0402_5%~D
SUS_ON_3.3V#
61
Q62A
2N7002DW-T/R7_SOT363-6~D
2
12
R611
100K_0402_5%~D
M_ON_3.3V#
61
Q68A
2N7002DW-T/R7_SOT363-6~D
12
R620
100K_0402_5%~D
AUX_ON_R
2N7002DW-T/R7_SOT363-6~D
61
Q74A
4
5
2
1 2
R1100 0_0402_5%~D@
5
+15V_ALW
12
3
5
4
+15V_ALW
5
200K_0402_5%~D
12
@
R629
EN_1.05VALW <43>
12
R598
100K_0402_5%~D
ALW_ENABLE
3
5
4
+15V_ALW
12
R603
100K_0402_5%~D
SUS_ENABLE
3
5
4
100K_0402_5%~D
R610
M_ENABLE
Q68B
2N7002DW-T/R7_SOT363-6~D
12
R619
100K_0402_5%~D
2N7002DW-T/R7_SOT363-6~D
3
Q74B
4
+5V_ALW
+3.3V_ALW +3.3V_ALW_I CH
Q57B
2N7002DW-T/R7_SOT363-6~D
+3.3V_ALW
Q62B
2N7002DW-T/R7_SOT363-6~D
+3.3VM Source
+3.3V_ALW
1
2
R1035 4.7K_0402_5%~D
1 2
R1003 4.7K_0402_5%~D
DDR_ON<10,34,44>
Q66
SI3456BDV-T1-E3_TSOP6~D
6
2
1
C698
4700P_0402_25V7K~D
+3.3V_ALW
1 2
4
+3.3V_ALW_ICH Source
Q54
SI3456BDV-T1-E3_TSOP6~D
D
6
S
45
2
1
G
3
1
2
+3.3V_SUS Source
Q60
SI3456BDV-T1-E3_TSOP6~D
D
6
S
2
1
G
3
1
C692
4700P_0402_25V7K~D
2
D
S
45
G
3
1
C696
4700P_0402_25V7K~D
2
12
R621
@
470K_0402_5%~D
1 2
R1102 100K_0402_5%~D@
EN_1.5VALW
2N7002DW-T/R7_SOT363-6~D
3
4
Q150B
5
2N7002DW-T/R7_SOT363-6~D
6 1
Q150A
2
1 2
R1101 0_0402_5%~D@
4
1
C687
2
10U_0805_10V4Z~D
C688
4700P_0402_25V7K~D
+3.3V_SUS
45
10U_0805_10V4Z~D
1
C690
2
+3.3V_M
10U_0805_10V4Z~D
12
1
C694
2
ENAB_3VLAN <21>
EN_1.5VALW <43>
R601
20K_0402_5%~D
20K_0402_5%~D
R612
3
2
1
Discharg Circuit
+3.3V_M+1.05V_M
2
G
2
G
@
R623
2N7002W-7-F_SOT323-3~D
@
Q77
+3.3V_ALW_ICH
2
G
OUT
NC
GND
2
1K_0402_5%~D
@
12
R616
2N7002W-7-F_SOT323-3~D
13
D
S
+1.05V_VCCP
1K_0402_5%~D
12
13
D
S
12
13
D
2
G
S
1K_0402_5%~D
12
13
D
S
5
4
@
Q72
@
R626
2N7002W-7-F_SOT323-3~D
@
Q80
1K_0402_5%~D
@
R624
2N7002W-7-F_SOT323-3~D
@
Q78
@
R628
2N7002W-7-F_SOT323-3~D
@
Q82
2
C1200
1U_0603_10V6K~D
1
RUN_ON<19,21,33,37,39>
3.3V_RUN_ON<33,39>
1.05V_RUN_ON<33>
+1.5V_ALW_HDA
1.5V_RUN_ON<33>
12
R599
100K_0402_5%~D
RUN_ON_5V#
61
Q56A
2N7002DW-T/R7_SOT363-6~D
2
12
R608
100K_0402_5%~D
RUN_ON_3V#
61
Q64A
2N7002DW-T/R7_SOT363-6~D
2
12
R617
100K_0402_5%~D
RUN_ON_1.05V#
61
Q70A
2N7002DW-T/R7_SOT363-6~D
2
12
R910
100K_0402_5%~D
61
Q129A
2N7002DW-T/R7_SOT363-6~D
2
RUN_ON_1.5V#
+15V_ALW+3.3V_ALW2 +5V_ALW
12
R597
100K_0402_5%~D
RUN_ENABLEM_ON_3.3V#
3
Q56B
2N7002DW-T/R7_SOT363-6~D
5
4
12
R606
100K_0402_5%~D
3
5
Q64B
2N7002DW-T/R7_SOT363-6~D
4
12
R613
100K_0402_5%~D
3
5
Q70B
2N7002DW-T/R7_SOT363-6~D
4
12
R911
100K_0402_5%~D
3
5
Q129B
2N7002DW-T/R7_SOT363-6~D
4
75_0603_5%~D
12
@
R615
12
+3.3V_RUN
12
20K_0402_5%~D
12
R605
RUN_ON_3V#
RUN_ON_5V#
SUS_ON_3.3V# ALW_ON_3.3V#
2
G
2
G
2
G
+3.3V_ALW
13
D
S
+5V_RUN
1K_0402_5%~D
12
13
D
S
+3.3V_SUS
12
13
D
S
2
1
2N7002W-7-F_SOT323-3~D
13
D
2
39_0402_5%~D
@
R622
2N7002W-7-F_SOT323-3~D
1K_0402_5%~D
C1201
1U_0603_10V6K~D
@
Q71
G
S
R625
2N7002W-7-F_SOT323-3~D
RUN_ON_1.05V#
Q79
+1.5V_RUN +0.75V_DDR_VTT
1K_0402_5%~D
12
13
D
@
2
Q76
G
S
@
R627
2N7002W-7-F_SOT323-3~D
@
Q81
U103
MAX8511EXK15+T_SC70-5~D
1
IN
3
#SHDN
1.5 Volt +/-5%
Design Current:11mA
Peak current: 11mA
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
DELL CONFIDENTIAL/PROPRIETARY
Title
Size Document Number Rev
Date: Sheet
+5VRUN Source
Q55
STS11NF30L_SO8~D
8
7
5
4
1
2
+3.3V_RUN Source
Q61
+3.3V_ALW+3.3V_ALW2 +15V_ALW
D30
@
RB751V_SOD323-2~D
R609
0_0402_5%~D
+1.05V_M+3.3V_ALW2 +15V_ALW
D31
@
RB751V_SOD323-2~D
R618
0_0402_5%~D
@
RB751V_SOD323-2~D
SI4336DY-T1-E3_SO8~D
8
7
5
21
1 2
+1.05V_VCCP Source
Q67
SI4336DY-T1-E3_SO8~D
8
7
5
21
1 2
+1.5V_RUN Source
Q128
SI4336DY-T1-E3_SO8~D
+1.5V_MEM+3.3V_ALW2 +15V_ALW
8
7
5
21
D65
1 2
R913
0_0402_5%~D
Compal Electronics, Inc.
POWER CONTROL
LA-4151P
1
2
36
2200P_0402_50V7K~D
C689
1
2
36
4
1
C693
470P_0402_50V7K~D
2
1
2
36
4
1
C697
470P_0402_50V7K~D
2
1
2
36
4
1
C1081
470P_0402_50V7K~D
2
1
1
2
C691
10U_0805_10V4Z~D
C695
10U_0805_10V4Z~D
C1080
+5V_RUN
10U_0805_10V4Z~D
C686
+3.3V_RUN
1
2
+1.05V_VCCP
1
2
1
2
10U_0805_10V4Z~D
12
R600
20K_0402_5%~D
12
12
+1.5V_RUN
36 57Fr id ay, July 04, 2008
R607
20K_0402_5%~D
R614
20K_0402_5%~D
12
R912
20K_0402_5%~D
1.0
of
5
4
3
2
1
@
2.5V_RUN_PWRGD<18,33>
+5V_RUN
D D
1
2
+3.3V_RUN
1
2
C C
B B
+1.5V_RUN
1
2
+3.3V_SUS
2 1
D32
RB751V_SOD323-2~D
C702
0.1U_0402_16V4Z~D
2 1
D33
RB751V_SOD323-2~D
C704
0.1U_0402_16V4Z~D
2 1
D66
RB751V_SOD323-2~D
C1082
0.1U_0402_16V4Z~D
D34
RB751V_SOD323-2~D
2 1
1
C707
0.1U_0402_16V4Z~D
2
12
12
12
200K_0402_5%~D
12
R642
200K_0402_5%~D
R634
200K_0402_5%~D
R638
200K_0402_5%~D
R916
10K_0402_5%~D
2200P_0402_50V7K~D
1
2
R633
10K_0402_5%~D
1 2
1
C703
2200P_0402_50V7K~D
2
1 2
R637
10K_0402_5%~D
1
C705
2200P_0402_50V7K~D
2
1 2
R915
10K_0402_5%~D
1
C1083
2200P_0402_50V7K~D
2
R641
1 2
C708
+5V_ALW
B
2
+3.3V_ALW
B
2
+1.5V_MEM
B
2
+3.3V_ALW
E
3
B
Q88
2
MMBT3906WT1G_SC70-3~D
C
1
200K_0402_5%~D
12
R643
E
3
Q83
MMBT3906WT1G_SC70-3~D
C
1
R635
4.7K_0402_5%~D
1 2
E
3
Q85
MMBT3906WT1G_SC70-3~D
C
1
R639
4.7K_0402_5%~D
1 2
E
3
Q130
MMBT3906WT1G_SC70-3~D
C
1
R917
4.7K_0402_5%~D
1 2
D35
RB751V_SOD323-2~D
2 1
1.8V_RUN_PWRGD<44>
C
Q84
2
B
MMST3904-7-F_SOT323-3~D
E
3 1
C
Q86
2
B
MMST3904-7-F_SOT323-3~D
E
3 1
C
Q131
2
B
MMST3904-7-F_SOT323-3~D
E
3 1
+3.3V_ALW
8
P
A3Y
G
U39C
74LVC3G14DC_VSSOP8~D
4
5
R630 0_0402_5%~D
R879 0_0402_5%~D
12
12
+3.3V_SUS
12
1
2
100K_0402_5%~D
0.1U_0402_16V4Z~D
R632
C701
+3.3V_M
+3.3V_ALW
1 2
8
P
A1Y
G
U39A
74LVC3G14DC_VSSOP8~D
4
IMVP_PWRGD<24,33,45,47>
RESET_OUT#<34>
D36
RB751V_SOD323-2~D
2 1
1
C709
0.1U_0402_16V4Z~D
2
C699
0.1U_0402_16V4Z~D
7
12
SUS_ON<34,36>
IMVP_PWRGD
RESET_OUT#
200K_0402_5%~D
R645
+3.3V_ALW
A6Y
RUN_ON<19,21,33,36,39>
10K_0402_5%~D
1 2
2200P_0402_50V7K~D
1
C710
2
8
P
G
4
R644
2
U39B
74LVC3G14DC_VSSOP8~D
1 2
R636
0_0402_5%~D
3.3V_5V_SUS_PWRGD
+3.3V_ALW
14
13
P
IN1
11
OUT
12
IN2
G
U40D
74VHC08MTCX_NL_TSSOP14~D
7
E
3
B
Q89
2
MMBT3906WT1G_SC70-3~D
C
1
200K_0402_5%~D
12
+3.3V_ALW
14
1
IN1
2
IN2
7
+3.3V_ALW
14
10
IN1
9
IN2
7
ICH_PWRGD
2 1
D37
RB751V_SOD323-2~D
R646
C700
0.1U_0402_16V4Z~D
1 2
U40A
74VHC08MTCX_NL_TSSOP14~D
P
3
OUT
G
4
5
P
8
OUT
G
U40C
74VHC08MTCX_NL_TSSOP14~D
+3.3V_M
R640
100K_0402_5%~D
2
G
+3.3V_ALW+3.3V_ALW
8
A1Y
4
+3.3V_ALW
14
U40B
74VHC08MTCX_NL_TSSOP14~D
P
IN1
6
OUT
IN2
G
7
12
ICH_PWRGD#
13
D
Q87
2N7002W-7-F_SOT323-3~D
S
P
7
G
U41A
74LVC3G14DC_VSSOP8~D
RUNPWROK
ICH_PWRGD# <18>
ICH_PWRGD <10,24>
3.3V_M_PWRGD <18,34>
RUNPW ROK <33,34,45>
SUSPWROK <34>
+3.3V_LAN
D40
RB751V_SOD323-2~D
2 1
1
C714
0.1U_0402_16V4Z~D
2
A A
200K_0402_5%~D
12
R652
10K_0402_5%~D
1 2
2200P_0402_50V7K~D
1
C715
2
R651
E
3
B
Q91
2
MMBT3906WT1G_SC70-3~D
C
1
200K_0402_5%~D
12
R653
2 1
D41
RB751V_SOD323-2~D
+3.3V_ALW+3.3V_ALW
C713
0.1U_0402_16V4Z~D
1 2
8
P
2
A6Y
G
U41B
74LVC3G14DC_VSSOP8~D
4
3.3V_LAN_PWRGD <34>
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
Power Good
LA-4151P
37 57Fr id ay, July 04, 2008
1
1.0
of
5
+5V_RUN+3.3V_RUN
12
R654
10K_0402_5%~D
D
SATA_ACT#_R<23>
MASK_BASE_LEDS#
D D
S
G
2
SATA_ACT#
13
Q93
2N7002W-7-F_SOT323-3~D
2
1 3
HDD LED solution for Blue LED
+3.3V_WLAN +5V_RUN
12
R662
100K_0402_5%~D
D
S
LED_WLAN# LED_W#
LED_WLAN_OUT#<21>
MASK_BASE_LEDS#
BKT_LED<39>
BKT_LED BATT_YELLOW_LED_R
13
Q98
G
2
2N7002W-7-F_SOT323-3~D
D
S
13
Q168
5@
G
2
2N7002W-7-F_SOT323-3~D
21
D75 SDM10U45-7_SOD523-2~D
+5V_RUN_BKT_PWR
2
2
1 3
WLAN_LED_RMASK_BASE_LEDS#
1 3
Q167
PDTA114EU_SC70-3~D
WLAN&BKT LED solution for Blue LED
C C
+3.3V_RUN_BKT_PWR
12
R206
LED_WWAN_OUT#<21>
100K_0402_5%~D
MASK_BASE_LEDS#
D
S
13
G
Q116
2
2N7002W-7-F_SOT323-3~D
LED_WWAN#
+5V_TP_PWR
2
1 3
WWAN LED solution for Blue LED
+3.3V_RUN
C1152 0.1U_0402_16V4Z~D
1 2
5
1
P
BT_ACTIVE_R BT_ACTIVE#
NC
BT_ACTIVE<2 1,30>
B B
SNIFFER_YELLOW#<33>
A A
SNIFFER_BLUE#<33>
10K_0402_5%~D
12
74LVC1G14GV_SOT753-5
R1051
A2Y
U91
2
2
G
3
+3.3V_ALW
+5V_ALW
5
4
MASK_BASE_LEDS#
@
Q100
DDTA114EUA-7-F_SOT323-3~D
1 3
Q102
DDTA114EUA-7-F_SOT323-3~D
1 3
D
S
13
G
Q95
2
2N7002W-7-F_SOT323-3~D
Mask All LEDs (Sn iffer Function)
Mask Base MB LEDs (Lid Closed)
Do not Mask LEDs (Lid Opened) 11
1 2
R667 220_0402_5%~D@
1 2
R668 150_0402_5%~D
+5V_RUN
2
1 3
LED Circuit Control Table
SNIFFER_YELLOW
SNIFFER_BLUE
4
Q92
DDTA114EUA-7-F_SOT323-3~D
SATA_LED
1 2
R659 1K_0402_5%~D
Q97
PDTA114EU_SC70-3~D
D83 SDM10U45-7_SOD523-2~D
2 1
R663 1K_0402_5%~D
5@
Q115
PDTA114EU_SC70-3~D
R125 1K_0402_5%~D
Q94
DDTA114EUA-7-F_SOT323-3~D
R661 1K_0402_5%~D
1 2
1 2
1 2
WLAN_LED
WWAN_LED
BT_LED
BT LED
SYS_LED_MASK# LID_CL#
0
10
SNI FFER_YE LLOW <21>
SNIF FER_BLUE <21>
4
LID_CL#<29,33>
SYS_LED_MASK#<33>
X
LID_CL#
SYS_LED_MASK#
H1
@H_3P4N
@
BAT2_LED#<34>
BAT1_LED#<34>
BREATH_LED#<31,34>
+3.3V_ALW
C1165 0.1U_0402_16V4Z~D
1 2
5
U90
1
P
IN1
O
2
IN2
G
74AHC1G08GW_SOT353-5~D
3
H2
@H_3P4N
1
@
CAP_LED#<33>
NUM_LED#<33>
SCRL_LED#<33>
BAT2_LED#
BAT1_LED#
MASK_BASE_LEDS#
4
3
H3
@H_2P3
1
1
@
+3.3V_ALW
A2Y
MASK_BASE_LEDS#
+3.3V_ALW
C1163 0.1U_0402_16V4Z~D
1 2
5
1
P
NC
A2Y
G
NC7SZ04P5X_NL_SC70-5~D
3
12
R1113
47K_0402_1%~D
3
2
H4
H5
@H_2P3
1
@
2
MASK_BASE_LEDS#
C1162 0.1U_0402_16V4Z~D
1 2
5
1
P
NC
4
G
U87
NC7SZ04P5X_NL_SC70-5~D
3
4
U88
2N7002DW-7-F_SOT363-6~D
+3.3V_ALW
5
A2Y
3
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
H6
@H_2P3
@H_2P7
1
1
@
@
2
1 3
Q122
DDTA114EUA-7-F_SOT323-3~D
1 3
61
Q152A
2
2N7002DW-7-F_SOT363-6~D
BAT2_LED
2N7002DW-7-F_SOT363-6~D
@
100K_0402_5%~D
1 2
+3.3V_ALW
61
Q157A
2
2N7002DW-7-F_SOT363-6~D
BAT1_LED
5
Q157B
C1164 0.1U_0402_16V4Z~D
1 2
1
P
BREATH_LED#_R
NC
4
G
U89
NC7SZ04P5X_NL_SC70-5~D
H10
H7
@H_2P8
@H_2P7
1
1
@
@
+5V_ALW
2
Q121
DDTA114EUA-7-F_SOT323-3~D
+5V_ALW
Q152B
R1039
3
4
5
@
100K_0402_5%~D
1 2
3
4
+3.3V_ALW
2
2
Q120
DDTA114EUA-7-F_SOT323-3~D
1 3
R1036
2
12
R1041
100K_0402_5%~D
2N7002W-7-F_SOT323-3~D
SYS_LED_MASK#
61
Q161A
61
Q162A
H11
@H_2P8
1
@
1 2
R556 1K_0402_5%~D
1 2
R596 1K_0402_5%~D
1 2
R655 1K_0402_5%~D
+5V_ALW
SYS_LED_MASK#
+3.3V_ALW
S
+3.3V_ALW
12
+3.3V_ALW
12
2N7002DW-7-F_SOT363-6~D
2N7002DW-7-F_SOT363-6~D
H12
@H_2P8
@H_2P8
1
@
R_CAP_LED
R_NUM_LED
R_SCRL_LED
+5V_ALW
2
1 3
12
R1038
100K_0402_5%~D
Q154
2N7002W-7-F_SOT323-3~D
S
G
2
Q155
1 3
DDTA114EUA-7-F_SOT323-3~D
Q156
D
2
13
G
2
R1044
100K_0402_5%~D
SYS_LED_MASK#
R1046
100K_0402_5%~D
MASK_BASE_LEDS#
2
H13
1
@
Keyboard Status LED
Q151
DDTA114EUA-7-F_SOT323-3~D
R1037 1K_0402_5%~D
D
13
150_0402_5%~D
1 2
+3.3V_ALW
2N7002DW-7-F_SOT363-6~D
2N7002DW-7-F_SOT363-6~D
H8
@H_2P8
1
@
1 2
2
R1040
1 3
4
5
4
5
Q161B
Q162B
@H_2P8
+5V_ALW
Q158
DDTA114EUA-7-F_SOT323-3~D
H9
1
@
H18
@H_2P5
1
@
Q153
1 3
DDTA114EUA-7-F_SOT323-3~D
+5V_ALW
2
3
+5V_ALW
2
3
1
Fiducial Mark
FD1
1
FIDUCIAL MARK~D
@
H14
@H_2P5
1
@
PWR_BTN_BD_DET#<33>
POWER_SW#_MB<34>
INSTANT_ON_SW#< 33,34>
BATT_BLUE_LED_R
BATT_YELLOW_LED_R
1 2
R1042 1K_0402_5%~D
R1043
150_0402_5%~D
1 2
DDTA114EUA-7-F_SOT323-3~D
Q159
1 3
DDTA114EUA-7-F_SOT323-3~D
Q160
1 3
FD2
1
FIDUCIAL MARK~D
@
H16
H15
@H_3P2X4P2N
@H_2P5
1
1
@
@
PWR_BTN_BD_DET#
POWER_SW#_MB
BREATH_BLUE_LE D_PW R
INSTANT_ON_SW#
R_SCRL_LED
R_NUM_LED
R_CAP_LED
WWAN_LED
BATT_BLUE_LED_R
SATA_LED
WLAN_LED
BT_LED
MASK_BASE_LEDS#
BATT_BLUE_LED <19>
BATT_Y ELLOW_LED <19>
BREATH_BLUE_LED
1 2
R1045 1K_0402_5%~D
1 2
R1047 150_0402_5%~D
BREATH_BLUE_LE D_P WR
FD3
1
FIDUCIAL MARK~D
@
H17
@H_2P2N
1
@
JBIO4
1
1
2
2
3
3
4
4
5
5
6
6
7
GND
8
GND
TYCO_2041070-6
JBIO5
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
GND
12
12
GND
TYCO_1-2041070-2
DELL CONFIDENTIAL/PROPRIETARY
Title
Size Doc um e n t N u mb er Re v
Date: Sheet
Compal Electronics, Inc.
PAD and Standoff
LA-4151P
1
FD4
1
FIDUCIAL MARK~D
@
13
14
BREATH_BLUE_LED <19>
38 57Friday, July 04, 2008
1.0
of
5
+3.3V_RUN_WWAN_PWR Source
D D
12
R1018
100K_0402_5%~D
3.3V_RUN_ON<33,36>
BKT_GPIO15<35>
C C
3.3V_RUN_ON
BKT_GPIO15
D70
3
3.3V_RUN_WWAN_PWR_EN
1
2
BAT54CW_SOT323~D
R1054
1 2
100K_0402_5%~D@
13
D
2
G
S
Q139
2N7002W-7-F_SOT323-3~D
+3.3V_RUN_BKT_PWR Source
12
R1021
100K_0402_5%~D
3.3V_RUN_ON<33,36>
BKT_GPIO19<35>
B B
3.3V_RUN_ON
BKT_GPIO19
D71
3
3.3V_RUN_BKT_PWR_EN
1
2
BAT54CW_SOT323~D
R1055
1 2
100K_0402_5%~D@
13
D
2
G
S
Q142
2N7002W-7-F_SOT323-3~D
+5V_RUN_BKT_PWR Source
12
5@
R1024
100K_0402_5%~D
A A
BKT_GPIO4<35,40>
RUN_ON<19,21,33,36,37>
BKT_GPIO4
RUN_ON
5@
D72
3
2
BAT54CW_SOT323~D
5
5V_RUN_BKT_PWR_EN
1
1 2
R1056
13
D
Q147
2
G
2N7002W-7-F_SOT323-3~D
100K_0402_5%~D @
S
4
Q137
SI3456BDV-T1-E3_TSOP6~D
D
6
2
1
S
G
3
1
C1137
470P_0402_50V7K~D
2
12
13
D
2
G
S
+3.3V_ALW+3.3V_ALW2 +15V_ALW
R1016
100K_0402_5%~D
Q138
2N7002W-7-F_SOT323-3~D
For WWAN power source
Q140
SI3456BDV-T1-E3_TSOP6~D
D
6
S
2
1
G
3
1
C1139
470P_0402_50V7K~D
2
12
13
D
2
G
S
+3.3V_ALW+3.3V_ALW2 +15V_ALW
R1019
100K_0402_5%~D
Q141
2N7002W-7-F_SOT323-3~D
For TP power source
Q145
5@
+15V_ALW+3.3V_ALW2 +5V_ALW
12
5@
R1023
100K_0402_5%~D
13
D
5@
Q146
2
G
2N7002W-7-F_SOT323-3~D
S
5@
SI3456BDV-T1-E3_TSOP6~D
D
6
S
2
1
G
3
1
2
For AMP/TP power source
4
3
+3.3V_BKT_PWR +3.3V_BKT_PWR
BKT_LVDS_RIN0-<40>
BKT_LVDS_RIN0+<40>
BKT_LVDS_RIN2-<40>
BKT_LVDS_RIN2+<40>
+3.3V_RUN_WWAN_PWR
45
45
45
2200P_0402_50V7K~D
5@
C1142
1
2
C1136
10U_0805_10V4Z~D
+3.3V_RUN_BKT_PWR
1
2
C1138
10U_0805_10V4Z~D
+5V_RUN_BKT_PWR
1
C1141
2
5@
10U_0805_10V4Z~D
12
R1017
20K_0402_5%~D
12
R1020
20K_0402_5%~D
20K_0402_5%~D
12
5@
R1025
3
BKT_SMBCLK<34>
BKT_SMBDAT<34>
BKT_GPIO16<35>
BKT_GPIO7<35>
BKT_GPIO8<35>
BKT_USBH-<40>
BKT_USBH+<40>
BKT_GPIO9<35> BKT_GPIO5 <35>
BKT_GPIO2<35>
BKT_LVDS_RIN0BKT_LVDS_RIN0+
BKT_LVDS_RIN2BKT_LVDS_RIN2+
BKT_SMBCLK
BKT_SMBDAT
BKT_GPIO16
BKT_GPIO7
BKT_GPIO8
BKT_USBHBKT_USBH+
BKT_GPIO9
+3.3V_ALW2 +15V_ALW
BKT_GPIO2
2
G
LDDC_DATA_MCH<12>
LDDC_CLK_MCH<12>
2
5@
JBKT1
1
PAID_IN
3
Odd Rin0-
5
Odd Rlin0+
7
VSS
9
Odd Rin2-
11
Odd Rin2+
13
VSS
15
Even Rin0-
17
Even Rlin0+
19
VSS
21
Even Rin2-
23
Even Rin2+
25
VSS
27
SMBCLK
29
SMBDATA
31
SMBALERT
33
RST-
35
USB_SEL_BLK
37
VSS
39
VSS
41
VDD 3.3v 5%
43
VDD 3.3v 5%
45
VDD 3.3v 5%
47
VSS
49
VSS
51
USB Host Port Data-
53
USB Host Port Data+
55
VSS
57
Reserved
59
Reserved
61
VSS
63
GPIO
65
SM CLK
67
SK DAT
69
SM Alert
71
VSS
73
Radio_OFF
75
Reserved
77
Reserved
79
Reserved
81
Reserved
83
Reserved
85
Reserved
87
Reserved
89
Reserved
91
Reserved
93
Reserved
95
Reserved
97
Reserved
99
VSS
101
GND
103
GND
12
5@
R1031
100K_0402_5%~D
Q148
13
D
S
2N7002W-7-F_SOT323-3~D
5@
Q149
2N7002W-7-F_SOT323-3~D
2
MOLEX_55299-1071
+3.3V_ALW
2
5@
G
2N7002DW-7-F_SOT363-6~D
LDDC_DATA_MCH
+3.3V_RUN
LDDC_CLK_MCH
Q143
5@
SI3456BDV-T1-E3_TSOP6~D
D
6
2
1
G
12
5@
R1030
100K_0402_5%~D
13
D
S
Q144A
2
5
4
Q144B
2N7002DW-7-F_SOT363-6~D
1
2
VSS
BKT_LVDS_RIN1-
Odd Rin1-
Odd Rin1+
VSS
Odd Clk-
Odd Clk+
VSS
Even Rin1-
Even Rin1+
VSS
Even Clk-
Even Clk+
VSS
I2S_LRC
I2S_DIN
I2S_DOUT
I2S_SCLK
VSS
M_Clk
VSS
VDD 3.3v 5%
VDD 3.3v 5%
VDD 3.3v 5%
VSS
VSS
BioMetric
BioMetric
VSS
Reserved
Reserved
VSS
Reserved
Reserved
Reserved
Reserved
VSS
LID Closed
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
PAID_Out
GND
GND
+3.3V_BKT_PWR
S
45
3
C1140
5@
1
5@
C1150
470P_0402_50V7K~D
2
LDDC_DATA_MCH_LVDS
61
4
BKT_LVDS_RIN1+
6
8
BKT_LVDS_CLK-
10
BKT_LVDS_CLK+
12
14
16
18
20
22
24
26
BKT_I2S_LRC
28
30
BKT_I2S_DO
32
BKT_I2S_SCLK
34
36
BKT_MCLK
38
40
42
44
46
48
50
BKT_USBBIO-
52
BKT_USBBIO+
54
56
58
60
62
BKT_LEDBKT_GPIO5
64
66
68
70
72
BKT_GPIO5
74
76
78
80
82
84
86
88
90
92
94
96
98
BKT_GPIO6
100
102
104
5@
1
12
2
10U_0805_10V4Z~D
R1022
BKT_LVDS_RIN1- <40>
BKT_LVDS_RIN1+ <40>
BKT_LVDS_CLK- <40>
BKT_LVDS_CLK+ <40>
BKT_I2S_LRC <21>
BKT_I2S_DO <21>
BKT_I2S_SCLK <21>
BKT_MCLK <21>
BKT_USBBIO- <40>
BKT_USBBIO+ <40>
BKT_LED <38>
BKT_GPIO6 <35>
Enable BKT power
20K_0402_5%~D
LDDC_DATA_MCH_LVDS <19>
LVDS connector side
LDDC_CLK_MCH_LVDS
3
LDDC_CLK_MCH_LVDS <19>
EDID signals drive low
when BlackTop mode
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
BlackTopI
LA-4151P
39 57Fr id ay, July 04, 2008
1
of
1.0
5
4
3
2
1
Normal mode BKT mode
BKT_GPIO1
BKT_GPIO4
BKT_GPIO11
D D
BKT_GPIO3
01
01
01
Normal mode BKT mode1Diag mode
10
5@
U84
SW_LVDS_A0+<19>
SW_LVDS_A0-<19>
SW_LVDS_A1+<19>
SW_LVDS_A1-<19>
+3.3V_RUN_BKT_PWR
5@
C C
BKT_GPIO3<35>
BKT_USBHBKT_USBH+
BKT_GPIO3
U97
8
2
1
7
NC
VCC
HSD-6DHSD+
GND
OE#
TS3USB31RSER_QFN8_1P5X1P5~D
USBP1-
5
USBP1+
3
D+
4
USBP1- <24>
USBP1+ <24>
SW_LVDS_A2+<19>
SW_LVDS_A2-<19>
SW_LVDS_ACLK+<19>
SW_LVDS_ACLK-<19>
BKT_GPIO3 Logic"0" on Diag mode
Add SB<-->BKT by USB interface when diagnostic mode
For WWAN
5@
From SB signals
USBP5+<24>
B B
USBP5-<24>
BKT_USBH+<39>
BKT_USBH-<39>
USBP5+
USBP5BKT_USBH+
BKT_USBH-
S Logic"1" Work from BKT
U85
1
1D+
2
1D-
3
2D+
4
2DGND5OE#
TS3USB221RSER_QFN10_2x1P5~D
For Biometric
5@
From USH signals
FP_USBD+<32>
FP_USBD-<32>
BKT_USBBIO+<39>
BKT_USBBIO-<39>
A A
FP_USBD+
FP_USBDBKT_USBBIO+
BKT_USBBIO-
S Logic"1" Work from BKT
U86
1
1D+
2
1D-
3
2D+
4
2DGND5OE#
TS3USB221RSER_QFN10_2x1P5~D
5
VCC
VCC
10
9
S
8
D+
7
D-
6
10
9
S
8
D+
7
D-
6
5@
C1148 0.1U_0402_16V4Z~D
1 2
BKT_GPIO4
USB_SW_USBD+
USB_SW_USBD-
+3.3V_RUN_BKT_PWR
BKT_GPIO4 <35,39>
USB_SW_USBD+ <21>
USB_SW_USBD- <21>
S
X
L
H
5@
C1149 0.1U_0402_16V4Z~D
1 2
BKT_GPIO11
FP_SW_USBD+
FP_SW_USBD-
+3.3V_RUN_BKT_PWR
BKT_GPIO11 <35>
FP_SW_USBD+ <29>
FP_SW_USBD- <29>
To Fingerpri nt signals
S
X
L
H
OE#
OE#
H
L
L
H
L
L
Function
Disconnect
D=1D
D=2D
Function
Disconnect
D=1D
D=2D
4
USBP5USBP5+
To WWAN signals
Bypass BKT function
FP_USBD+
FP_USBD-
Bypass BKT function
6@
RN1
1 4
2 3
0_0404_4P2R_5%~D
6@
RN6
FP_SW_USBD+
1 4
FP_SW_USBD-
2 3
0_0404_4P2R_5%~D
USB_SW_USBDUSB_SW_USBD+
3
SW_LVDS_A0+
SW_LVDS_A0-
SW_LVDS_A1+
SW_LVDS_A1-
SW_LVDS_A2+
SW_LVDS_A2-
SW_LVDS_ACLK+
SW_LVDS_ACLK-
SEL
0
1
BKT_GPIO1
Com_to
_NC
ON
OFF
Com_to
_NO
OFF
ON
BKT_GPIO1<35>
SEL Logic"1" Work from BKT
LVDS switch when system
on powe r mode or BKT mode
SW_LVDS_A0+
SW_LVDS_A1SW_LVDS_A1+
11
12
15
16
10
14
17
19
21
39
41
43
6@
1 4
2 3
0_0404_4P2R_5%~D
6@
1 4
2 3
0_0404_4P2R_5%~D
MAX4889
2
COM1+
3
COM1-
6
COM2+
7
COM2-
COM3+
COM3-
COM4+
COM4-
9
SEL
1
GND
4
GND
GND
GND
GND
GND
GND
GND
GND
GND
MAX4889ETO+_TQFN42_3P5x9~D
RN2
LCD_A0-_MCHSW_LVDS_A0LCD_A0+_MCH
RN5
LCD_A1-_MCH
LCD_A1+_MCH
Bypass BKT function
2
5
V+
8
V+
13
V+
18
V+
20
V+
30
V+
40
V+
42
V+
38
NC1+
37
NC1-
34
NO1+
33
NO1-
36
NC2+
35
NC2-
32
NO2+
31
NO2-
29
NC3+
28
NC3-
25
NO3+
24
NO3-
27
NC4+
26
NC4-
23
NO4+
22
NO4-
SW_LVDS_A2SW_LVDS_A2+
SW_LVDS_ACLKSW_LVDS_ACLK+
+3.3V_RUN_BKT_PWR
5@
5@
1
C1145
2
0.1U_0402_16V4Z~D
LCD_A0+_MCH
LCD_A0-_MCH
BKT_LVDS_RIN0+
BKT_LVDS_RIN0-
LCD_A1+_MCH
LCD_A1-_MCH
BKT_LVDS_RIN1+
BKT_LVDS_RIN1-
LCD_A2+_MCH
LCD_A2-_MCH
BKT_LVDS_RIN2+
BKT_LVDS_RIN2-
LCD_ACLK+_MCH
LCD_ACLK-_MCH
BKT_LVDS_CLK+
BKT_LVDS_CLK-
6@
RN3
1 4
2 3
0_0404_4P2R_5%~D
6@
RN4
1 4
2 3
0_0404_4P2R_5%~D
C1146
5@
1
1
C1147
2
2
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
LCD_A0+_MCH <12>
LCD_A0-_MCH <12>
BKT_LVDS_RIN0+ <39>
BKT_LVDS_RIN0- <39>
LCD_A1+_MCH <12>
LCD_A1-_MCH <12>
BKT_LVDS_RIN1+ <39>
BKT_LVDS_RIN1- <39>
LCD_A2+_MCH <12>
LCD_A2-_MCH <12>
BKT_LVDS_RIN2+ <39>
BKT_LVDS_RIN2- <39>
LCD_ACLK+_MCH <12>
LCD_ACLK-_MCH <12>
BKT_LVDS_CLK+ <39>
BKT_LVDS_CLK- <39>
LCD_A2-_MCH
LCD_A2+_MCH
LCD_ACLK-_MCH
LCD_ACLK+_MCH
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
BlackTopII
LA-4151P
40 57Fr id ay, July 04, 2008
1
of
1.0
5
4
3
2
1
+COINCELL
12
+3.3V_RTC_LDO
D D
+3.3V_ALW
ESD Diodes
2
2
3
Primary Battery Connector
FOX_BP02093-P5652-7F~D
11
10
12
PC4
2200P_0402_50V7K~D
C C
B B
PJPDC1
1
1
2
2
-DCIN_JACK
3
3
4
4
+DCIN_JACK
5
5
6
6
7
7
MOLEX_87438-0743
A A
GND
GND
PBATT1
12
PC414
0.1U_0603_25V7K~D
9
9
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
0_0402_5%~D
PC412
Z4304
Z4305
Z4306
GND
NB_PSID
+5V_ALW
2
3
PD12
@
DA204U_SOT323~D
1
PR20
1 2
1 2
PC183
@
PL20
.47U_0402_6.3V6-K~D
FBMJ4516HS720NT_1806~D
1 2
1
PD29
12
@
2
VZ0603M260APT_0603
PC413
0.1U_0603_25V7K~D
FBMJ4516HS720NT_1806~D
@
PL21
1 2
NB_AC_OFF_BJT<48> NB_AC_OF F <33,46,48>
DA204U_SOT323~D@
100_0402_5%~D
GND
DCIN _CBL_DET# <33>
IMD2AT- 108_SC74-6~D
12
12
PR272
0.1U_0603_25V7K~D
0_0402_5%~D
@
5
PD5
PR7
1 2
PQ4B
2
16
BLM18BD102SN1D_0603~D
PQ4A
IMD2AT- 108_SC74-6~D
1
PR8
100_0402_5%~D
1 2
PL3
+DC_IN
PC5
1 2
43
0.022U_0603_50V7K~D
PD6
DA204U_SOT323~D@
3
12
+DC_IN
12
PR16
3
2
PD7
1
PR9
100_0402_5%~D
1 2
100_0402_5%~D
PQ2
FDS6679AZ_SO8~D
1
2
3 6
4
1M_0402_5%~D
12
PR21
1M_0402_5%~D
2
3
1
DA204U_SOT323~D@
1 2
PR10
1
@
2
1
DC_IN+ Source
8
7
5
12
PR22
22K_0402_1%~D
13
D
2
G
PQ5
S
RHU002N06_SOT323
PD8
DA204U_SOT323~D@
PBAT_ALARM#
3
@
PD10
SM24_SOT23
PC6
0.1U_0603_25V7K~D
PR285
100K_0402_5%~D
1 2
12
PBAT_SMBCLK <34>
PBAT_SMBDAT <34>
PR14
1 2
100K_0402_1%~D
PR18
1 2
15K_0402_1%~D
12
12
PC7
0.1U_0603_25V7K~D
PC11
0.1U_0603_25V7K~D
PBATT+_C
PC8
0.1U_0603_25V7K~D
FBMA-L18-453215-900LMA90T_1812~D
PC3
0.1U_0603_25V7K~D
PR12
@
1 2
0_0402_5%~D
D
S
1 3
PQ1
FDV301N_SOT23~D
G
2
C
PQ3
2
B
MMST3904-7-F_SOT323~D
E
3 1
+DC_IN_SS
12
12
PC9
PR19
4.7K_0805_5%~D
12
10U_1206_25V6M~D
1 2
1 2
PAD-OPE N 4x4m
PR13
33_0402_5%~D
1 2
12
PL2
PJP12
PD9
DA204U_SOT323~D
+5V_ALW
3
+5V_ALW
+3.3V_ALW
PR17
10K_0402_5%~D@
SLICE_BAT_PRES#<31, 33,48>
PD11
@
PR6
10K_0402_1%~D
+3.3V_ALW
PR11
1 2
2.2K_0402_5%~D
+5V_ALW
3
DA204U_SOT323~D
12
RB751V_SOD323~D
2
1
PBAT_PRES# <33>
PD22
NB_PSID _TS5A63157
PQ47
FDN338P_NL_SOT23-3~D
1
3
1 3
21
2
2
PR334
1 2
0_0402_5%~D
PSID_ DISAB LE# <33>
12
PC38
1500P_0402_50V7K~D
DOCK_PSID<31> GPIO_P SID_SELECT <33>
PBATT+
2
GND
1
12
PR15
10K_0402_1%~D
1 2
Z4012
3
2
PD28
1
BAT54CW_SOT323~D
<BOM Structure>
27.4
DOCK_SMB_ALERT# <31,34>
PU1
1
NO
2
GND
NC3COM
TS5A63157DCKR_SC70-6~D
COIN RTC Battery
PR271
1K_0402_5%~D
1
2
IN
V+
RTC_BAT_DET#<23>
+RTC_CELL
PC244
1U_0603_10V4Z~D
Move to power schematic
6
5
+5V_ALW
4
PS_I D <34>
+COINCELL
JRTC2
1
1
2
2
3
3
4
GND
5
GND
MOLEX_53780-0370~D
DELL CONFIDENTIAL/PROPRIETARY
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONT AINS CONFIDE NTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVIS ION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INF ORMATION IT CONT AINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WR ITT EN CO NSE NT OF COMPAL ELECTRONICS, INC.
5
4
3
2
Title
Size Doc um e n t N u mb er Re v
Date: Sheet
Compal Electronics, Inc.
+DCIN
LA-4151P
41 57Friday, July 04, 2008
1
0.2
of
5
4
3
2
1
+3.3V_ALWP/ +5V_ALWP/ +5V_ALW2 / +15V_ALWP/ +3.3V_RTC_LDO
THERM_STP#<18>
12
1 2
ALWON<34>
+DC1_PWR_SRC
3
2
G
1
3
2
G
1
+5V_ALW
+3.3V_ALW
12
PR26
PR27
PC24
1 2
PR29
32
31
30
29
28
27
26
25
+5V_VCC1
PR25
10_0603_5%~D
12
PC23
GNDA_3V5V
REFIN2
PR31
200K_0402_1%~D
1 2
+3.3V_OUT2
PR33 0_0402_5%~D
POK2
EN_3V_5VEN_3V_5V
+3.3V_ALW_UGATE
+3.3V_ALW_PHASE
PR37
4.7_0603_5%~D
1 2
+3.3V_ALW_LGATE
PJP16
1 2
PAD-OPEN1x1m
12
12
12
PC12
PC13
PC14
0.1U_0805_50V7K
2200P_0402_50V7K~D
12
1U_0603_10V6K~D
12
0_0402_5%~D
PR28
PR30
12
12
PC28
0.1U_0603_25V7K~D
@
1 2
0_0402_5%~D
GNDA_3V5V
GNDA_3V5V
POK2
POK1
@
PC25
0.1U_0402_10V7K~D
+3.3V_ALWP
PR40
12
+3.3V_ALWP
PR41
@
1 2
1 2
100K_0402_1%~D
100K_0402_1%~D
12
PR43
0_0402_5%~D
2
G
2
G
PC222
470P_0402_50V7K
1 2
3
D
PQ7
S
1
FDMS8692_POWERPAK
3
D
PQ9
S
1
FDS6676AS_NL_SO8~D
ALW_PWRGD_ 3V_5V <34>
10U_1206_25V6M~D
PL7
HMP1350-2R8 16A
2 1
PC191
12
1000P_0603_50V7K~D
PR290
2.2_1206_5%~D
1 2
VOUT2=3.3V
L=3.3uF
Fsw=300KHz
D=0.173
Input Ripple Current=TDC*(D*(1-D))^0.5=2.98A
Output ripple current=(19-3.3)*0.173/2.8u/300K=3.23A
Output ripple Voltage=3.23*25=58.14mV
Component select
Input CAP 10uF_1206_25V *2
Output Cap 330uF_D3L_6.3VM_R18
Sanyo_6TPE330ML)*1
H_MOSFET FDMC8878
L_MOSFET FDS6676AS(5.9/7.25mOhm@4.5V, 14.5A)
Inductor 2.8U_SSC-1350F3-2R8-R_16A(TNP)
12
12
PC64
PC15
10U_1206_25V6M~D
10U_1206_25V6M~D
3.3 Volt +/-5%
Thermal Design Current: 8.4A
Peak current: 12A
OCP_min:12.4A
+3.3V_ALWP
+3.3V_ALWP+5V_ALWP
12
PC30
1
+
2
330U_D3L_6.3VM_R18~D
PR35
0_0402_5%~D
12
@
PR39
0_0402_5%~D
GNDA_3V5V
PC32
12
0.1U_0402_10V7K~D
PJP15
1 2
+5V_ALW2
PR23
12
12
12
12
12
PC63
PC19
PC18
PC17
PC16
0.1U_0805_50V7K
2200P_0402_50V7K~D
D
PQ6
S
FDMS8692_POWERPAK
D
PQ8
S
FDS6676AS_NL_SO8~D
PR42
2K_0402_5%~D
PR45
0_0402_5%~D
10U_1206_25V6M~D
PC26
@
0.1U_0402_10V7K~D
12
12
+15V_ALW
10U_1206_25V6M~D
10U_1206_25V6M~D
PC21
12
187K_0402_1%~D
GNDA_3V5V
+5V_ALW_UGATE
+5V_ALW_PHASE
+5V_ALWP
12
PC35
0.1U_0603_25V7K~D
PR44
1 2
200K_0402_5%
PJP17
PAD-OPEN1x1m
(100mA,20mils ,Via NO.=1)
PR24
1 2
+3.3V_ALW2
12
+3.3V_RTC_LDO
PR32
1 2
12
PC27
0.1U_0603_25V7K~D
2
3
PD14
2
3
PD15
+15V_ALWP
0_0805_5%
1 2
+5V_ALWP
+5V_OUT1
+5V_FB1
POK1
PR36
1_0603_5%~D
1 2
+5V_ALW_LGATE
PC33
0.1U_0603_25V7K~D
1 2
1
PC36
0.1U_0603_25V7K~D
1
1 2
PC37
0.1U_0603_25V7K~D
0_0805_5%
0.1U_0603_25V7K~D
GNDA_3V5V
BAT54SW-7-F_SOT 323-3~D
BAT54SW-7-F_SOT 323-3~D
12
12
PR284
0_0402_5%~D
LDOREFIN
BYP
9
10
11
12
13
14
15
16
GNDA_3V5V
+5V_ALW_BOOT
200K_0402_1%~D
12
12
PC22
0.1U_0603_25V7K~D
GNDA_3V5V
BYP
OUT1
FB1
ILIM1
POK1
MAX8778_QFN32~D
EN1
UGATE1
PHASE1
PAD
33
3
PR46
PAD-OPEN1x1m
5V_3V_REF
VIN
+5V_ALW2P
+3.3V_ALW2SECFB
EN_3V_5V
5
7
4
8
3
6
VIN
LDO
VREF3
EN_LDO
LDOREFIN
PU2
BOOT117LGATE118PVCC19SECFB20GND21PGND22LGATE223BOOT2
GNDA_3V5V
PC34
+5V_ALW2
PD16
1
BAT54CW_SOT323~D
2
12
PR49
39K_0402_1%~D
1 2
GNDA_3V5V
PC20
4.7U_0805_6.3V6K
0_0402_5%~D
1 2
@
0_0402_5%~D
1 2
0.1U_0603_25V7K~D
1 2
TON
@
0_0603_5%~D
1
REF
TON2VCC
REFIN2
ILIM2
OUT2
SKIP#
POK2
EN2
UGATE2
PHASE2
24
+3.3V_ALW_BOOT
12
GNDA_3V5V
1U_0603_10V6K~D
PL15
FBMJ4516HS720NT_1806~D
PC31
12
0.1U_0402_10V7K~D
1 2
HMP1350-2R8 16A
12
12
GNDA_3V5V
+5V_ALWP
+3.3V_ALWP
@
0_0402_5%~D
PR34
0_0402_5%~D
PR38
PL6
2 1
PC189
1000P_0603_50V7K~D
PR288
2.2_1206_5%~D
PJP26
1 2
PAD-OPE N 4x4m
PJP18
1 2
PAD-OPE N 4x4m
PJP19
1 2
PAD-OPE N 4x4m
PJP29
1 2
PAD-OPE N 4x4m
+PWR_SRC
D D
5 Volt +/-5%
Thermal Design Current:8.33A
Peck current: 11.97A
OCP_min:13A
+5V_ALWP
C C
1
+
PC29
2
330U_D3L_6.3VM_R18~D
VOUT2=5V
L=3.3uF
Fsw=200KHz
D=0.263
Input Ripple Current=TDC*(D*(1-D))^0.5=4.63A
Output Ripple Current=(19-5)*0.263/2.8u/200K=6.57A
Output Ripple Voltage=6.57*18m=118mV
B B
Component select
Input CAP 10uF_1206_25V *2
Output Cap 330uF_D3L_6.3VM_R18(Sanyo_6TPE330ML)*1
H_MOSFET FDMC8878
L_MOSFET FDS6676AS(5.9/7.25mOhm@4.5V, 14.5A)
Inductor 2.8U_SSC-1350F3-2R8-R_16A(TNP)
A A
DELL CONFIDENTIAL/PROPRIETARY
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVIS ION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INF ORMATION IT CONT AINS
5
4
3
2
Title
Size Doc um e n t N u mb er Re v
Date: Sheet
Compal Electronics, Inc.
DC/DC +3V/ +5V
LA-4151P
1
42 57Friday, July 04, 2008
0.2
of
5
4
3
2
1
+1.5V_SUS_P / +1.05V_M
PC418
PC425
22U_1206_6.3V6M~D
12
PC435
0.1U_0603_25V7K~D
12
PJP49
1 2
PAD-OPEN 4x4m
12
0.1U_0603_25V7K~D
12
PC426
@
22U_1206_6.3V6M~D
1 2
PC436
0.1U_0603_25V7K~D
PC443
22U_1206_6.3V6M~D
PJP23
1 2
PAD-OPEN 4x4m
2
12
PC427
@
22U_1206_6.3V6M~D
PJP50
PAD-OPEN 4x4m
12
12
PC444
22U_1206_6.3V6M~D
12
12
+5V_ALW
PC428
+1.05V_M+1.05V_MP
1.05 Volt +/-5%
Thermal Design Current: 4.6A
Peack current: 6.5A
OCP_MIN: 10A
+1.05V_MP
12
12
PC429
22U_1206_6.3V6M~D
+5V_ALW
22U_1206_6.3V6M~D
12
12
PC431
PC430
@
0.1U_0603_25V7K~D
22U_1206_6.3V6M~D
PC432
6800P_0402_25V7K~D
1.5 Volt +/-5%
Thermal Design Current: 7.56A
Peak current: 10.7A
OCP_MIN:15A
+1.5V_SUS_P
12
PC445
PC446
@
22U_1206_6.3V6M~D
22U_1206_6.3V6M~D
12
12
PC447
0.1U_0603_25V7K~D
PC448
25V,X7R,10%
6800P_0402_25V7K~D
DELL CONFIDENTIAL/PROPRIETARY
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
+1.5V_RUN / +1.05V_VCCP
LA-4151P
1
43 57Fr id ay, July 04, 2008
0.2
of
DC_5V_ALW2
12
PR273
D D
C C
B B
+1.5V_SUS_P
A A
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
AVDD2
PJP25
1 2
PAD-OPEN 4x4m
PJP24
1 2
PAD-OPEN 4x4m
EN2
5
PR64
0_0402_5%~D
1 2
1 2
12
PC419
0.22U_0402_10V7K~D
GNDA_1.05V
AVDD1
10_0402_1%~D
PR278
10_0402_1%~D
1 2
12
PC437
0.22U_0402_10V7K~D
GNDA_1.5V
+1.5V_MEM
EN_1.05VALW <36>
PR277
38.3K_0402_1%
PC420
PC438
2200P_0402_50V7K~D
+1.05V_R_SEL/LOAD
12
2200P_0402_50V7K~D
PR53
1 2
0_0402_5%~D
PR282
12
PR54
0_0402_5%~D
1 2
+1.05V_VDES
VSENSE2
PR275
3.09K_0402_1%
+1.5V_R_SEL/LOAD
3.74K_0402_1%~D
PR280
56K_0402_1%
1 2
4
A1
A2
A3
A4
EN2
A5
B1
PR276
44.2K_0402_1%
GNDA_1.05V
DC_5V_ALW1
BIAS
+1.5V_VDES
VSENSE1
EN1
PR281
PR65
1.05V_POK2
1.5V_POK1
1.5V_POK1 <10,34>
E5
BIAS
R_SEL/ILOAD
VDES
VSENSE+
OE
AGND
B2
PR274
31.6K_0402_1%~D
A1
A2
A3
A4
A5
B1
44.2K_0402_1%
12
100K_0402_1%~D
GND
VDDE4VDD
GNDE3GNDE2GND
PU25
VT351AFCX-ADJ
IRIPL
AVDD
B4
B3
AVDD2
PJP22
1 2
PAD-OPEN1x1m
E5
VDDE4VDD
BIAS
R_SEL/ILOAD
VDES
VSENSE+
OE
AGND
IRIPL
B2
B3
AVDD1
PR279
PJP20
1 2
24K_0402_1%~D
PAD-OPEN1x1m
GNDA_1.5V
+3.3V_ALW+3.3V_ALW
PR66
PC449
@
1 2
100K_0402_1%~D
12
PR283
@
0_0402_5%~D
E1
D4
VXD5VX
VX
VX
VX
VDD
VDD
GND
STATB5TEMP
GNDC2GND
C1
1.05V_POK2
GND
E1
GNDE3GNDE2GND
PU26
VT351AFCX-ADJ
STATB5TEMP
AVDD
1.5V_POK1
B4
C1
12
0.1U_0402_10V7K~D
1.05V_M_PWRGD <34>
1.5V_SUS_PWRGD <10,34>
D3
VXD5VX
D2
D1
C5
C4
C3
D4
VX
VX
VX
VDD
VDD
GND
GNDC2GND
+1.05V_VX
12
PC187
1000P_0603_50V7K~D
1_0805_5%~D
PR286
PR47
0_0402_5%~D
1 2
VSENSE2
PR48
@
0_0402_5%~D
D3
D2
D1
C5
C4
C3
THIS SHEET OF EN GINEE RING D RAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
+1.5V_VX
+1.5V_VX
12
PC188
1000P_0603_50V7K~D
1_0805_5%~D
PR287
0_0402_5%~D
1 2
PR50
VSENSE1
PR51
@
0_0402_5%~D
EN_1.5VALW<36>
3
12
PC65
PC415
@
10U_1206_25V6M~D
10U_1206_25V6M~D
PL22
0.2UH +-25%_ MPC0730LR20C_17.5A
12
12
PC421
12
10U_1206_25V6M~D
PL23
0.2UH +-25%_ MPC0730LR20C_17.5A
12
12
EN1
12
PC416
10U_1206_25V6M~D
12
12
PC423
PC422
10U_1206_25V6M~D
22U_1206_6.3V6M~D
12
PC433
10U_1206_25V6M~D
12
12
12
PC439
PC440
10U_1206_25V6M~D
10U_1206_25V6M~D
12
PC417
0.1U_0603_25V7K~D
12
12
PC424
22U_1206_6.3V6M~D
12
PC434
10U_1206_25V6M~D
12
PC441
PC442
22U_1206_6.3V6M~D
22U_1206_6.3V6M~D
5
4
3
2
1
+1.8VRUN/ +0.75V_DDR_VTT
DDR3 Termination
D D
OUT
PGND
AGND
OUTS
+0.75V_P
0.75Volt +/-5%
Thermal Design Current: 1.4A
Peak current: 2A
PC343
PC342
1 2
1 2
PC345
1 2
1U_0603_10V6K~D
10U_0805_6.3V6M~D
10U_0805_6.3V6M~D
+0.75V_P
PJP45
2 1
PAD-OPEN 2x2m~D
+0.75V_DDR_VTT
1.8 Volt +/-5%
Design Current: 221.3mA
Max current: 316.3mA
+1.8V_RUN
1 2
PJP27
2 1
PAD-OPEN 2x2m~D
12
PC179
10U_0805_6.3V6M~D
9
8
3
6
1
11
BP
1.8V_OUT
PC180
1 2
PC178
1U_0603_10V6K~D
10U_0805_6.3V6M~D
+5V_ALW
PU24
10
PJP48
+1.5V_SUS_P
0.75V_DDR_VTT_ON<33>
C C
B B
5V_3V_REF
DDR_ON<10,34,36>
+3.3V_ALWP
1.8V_RUN_PWRGD<37>
PAD-OPEN 2x2m~D
1.8V_RUN_ON<33>
PR270
10K_0402_1%
1 2
2 1
PJP28
2 1
PAD-OPEN 2x2m~D
DC_1+0.75V_VTT_PWR_SRC
PC348
1 2
10U_0805_6.3V6M~D
100K_0402_5%~D@
1U_0603_10V6K~D
91K_0402_1%~D
1 2
2
1
7
9
12
PC410
0.1U_0603_25V7K~D
PR134
12
PC181
12
PR135
VIN
VLDOIN
VDDQSNS
S3
S5
TPS51100DGQRG4_MSOP10~D
DC_1+1.8V_RUN_PWR_SRC
+3.3V_ALW
12
PC182
1U_0603_10V6K~D
+V_DDR_MCH_REF
3
VTT
5
VTTSNS
6
VTTREF
4
PGND
8
GND
11
BP
PC184
10U_0805_6.3V6M~D
12
PU12
MAX8794
10
IN
2
VCC
5
PGOOD
7
SHDN#
4
REFIN
REFOUT
PGND and GND sholud be tied
together at one point near the GND Pin
A A
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
+1.8VSUSP/ +0.75V_DDR_VT
LA-4151P
44 57Fr id ay, July 04, 2008
1
of
0.2
8
H H
G G
F F
E E
GNDA_VCORE
H_DPRSTP#<8,10,23>
DPRSLPVR<10,24>
D D
C C
B B
A A
H_PSI#<8>
PWR_MON<18>
PC111
@
1U_0603_10V6K~D
GNDA_VCORE
RUNPWROK<33,34,37>
IMVP_VR_ON<33>
10KB_0603_1%_ERTJ1VG103FA~D
GNDA_VCORE
0_0402_5%~D
2200P_0402_50V7K~D
VID0<8>
VID1<8>
VID2<8>
VID3<8>
VID4<8>
VID5<8>
VID6<8>
PR110
@
10K_0402_5%~D
1 2
PH2
PR118
6.34K_0402_1%
VSSSENSE<8>
PR123
@
332_0402_1%~D
0.47U_0402_10V7KD
12
PR138
0_0402_5%~D
8
PR94
143K_0402_1%~D
12
@
PR96
12
PC101
@
12
PC107
1000P_0402_50V7K~D
1 2
PR100
0_0402_5%~D
PR102
0_0402_5%~D
PR104
0_0402_5%~D
0_0402_5%~D
12
0_0402_5%~D
PR115 0_0402_5%~D@
12
12
GNDA_VCORE
12
1 2
PC121
@
680P_0402_50V7K~D
1500P_0402_50V7K~D
1 2
PC124
@
PC127
1 2
@
470KB_0402_5%_NCP15WM474J03RB~D
PR99
0_0402_5%~D
12
PR101
0_0402_5%~D
12
PR103
0_0402_5%~D
12
PR105
0_0402_5%~D
PR108
499_0402_1%~D
12
PR113
12
12
VCCSENSE<8>
PC112 1000P_0402_50V7K~D
PC117 1000P_0402_50V7K~D
PR126
@
1.69K_0402_1%~D
82.5K_0402_1%~D
@
1000P_0402_50V7K~D
732_0402_1%~D
PR89
PC100
GNDA_VCORE
PAD~D
IMVP6_PROCHOT#
T92
PH1
12
12
12
12
12
PR107
12
T55PAD~D
PR114 10_0402_1%~D
12
12
PR120
12
0_0402_5%~D
PR124
14.3K_0603_1%~D
12
PR127
71.5K_0402_1%~D
12
PR129
@
PC128
12
12
PR136
7
+5V_ALW
1 2
10_0603_5%~D
12
12
1U_0603_10V6K~D
@
DPRSLPRV
CLK_ENABLE#
@
12
12
12
@
@
GNDA_VCORE
7
PR95
THRM
PGD_IN
PR137
1K_0402_1%~D
PC134
0.01U_0402_16V7K~D
12
0_0402_5%~D
0_0603_5%~D
OSC
CCV
D0
D1
D2
D3
D4
D5
D6
PSI
SHDN
CNDS
VPS
TIME
REF
GNDA_VCORE
12
12
1
2
+CPU_PWR_SRC
12
PC97
0.01U_0402_25V7K~D
@
GNDA_VCORE
MAX8786_VCC
PR97
19
20
PU7
VCC
GND
4
VRHOT
3
OSC
5
THRM
6
CCV
28
D0
29
D1
30
D2
31
D3
32
D4
33
D5
34
D6
37
DPRSTP
36
DPRSLPVR
1
PSI
2
PGD_IN
38
CLKEN
35
SHDN
12
FBS
13
GNDS
11
VPS
10
TIME
9
REF
8
TRC
MAX8786GTL+_TQFN40_6X6~D
41
TP
CSN3
14
PR131
@
10.5K_0402_1%
12
PC129
@
12
330P_0402_50V7K~D
PC131
@
1000P_0402_50V7K~D
PR86
@
10_0603_5%~D
1 2
+3.3V_RUN
18
39
N.C.
V3P3
PWM1
CSP1
PWM2
CSP2
DRSKP
PWM3
CSP3
ILIMPK
CSN215CSN1
CSN2
@
1K_0402_1%~D
12
PC132
@
PR93
10K_0603_1%~D
1 2
40
IMVPOK
PWR
16
@
VO
PR132
1000P_0402_50V7K~D
GNDA_VCORE
6
IMVP_PWRGD <24,33,37,47>
PWM1
27
CSP1
23
PWM2
26
CSP2
22
DRSKP
24
25
MAX8786_VCC
VSUM
PC120
@
1
2
PC123
@
0.01U_0402_16V7K~D
PR116
154K_0402_1%~D
PR117
@
11.5K_0402_1%~D
PR119
@
1 2
0.033U_0402_16V7K~D
12
PH3
@
12
12
12
2.43K_0402_1%~D
12
6.8KB_0603_5%_ERTJ1VR682J~D
21
7
17
12
PR122
2
4.53K_0402_1%~D
1
PC122
@
0.33U_0603_10V7K
12
12
PC133
@
1000P_0402_50V7K~D
6
PR130
@
GNDA_VCORE
12
PR125
17.8K_0402_1%~D
15K_0402_1%~D
1
2
5
+5V_ALW
12
PC95
1U_0603_10V6K~D
12
PR139
PC130
0.1U_0402_16V7K~D
5
PU6
5
VCC
6
FCCM
UGATE
2
PWM
12
PR128
12
PR133
33K_0402_1%~D
22.1K_0402_1%~D
PHASE
3
LGATE
GND
MAX8791_QFN8~D
33K_0402_1%~D
+5V_ALW
PC106
PU8
1U_0603_10V6K~D
5
VCC
6
FCCM
2
PWM
3
12
GND
MAX8791_QFN8~D
PWR_ MON <18>
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVIS ION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INF ORMATION IT CONT AINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WR ITT EN CO NSE NT OF COMPAL ELECTRONICS, INC.
BOOT1 BOOT1_1
1
BOOT
8
7
4
BOOT
UGATE
PHASE
LGATE
4
PR87
2.2_0603_5%~D
LGATE1
PR98
2.2_0603_5%~D
BOOT2
1
8
7
LGATE2
4
4
UGATE1
UGATE2
0.22U_0603_10V7K~D
12
1 2
2
BOOT2_2
12
2
PC96
3
D
G
S
1
FDMS8670AS_ POWER56-8
PC108
0.22U_0603_10V7K~D
1 2
3
D
G
S
1
FDMS8670AS_ POWER56-8
PQ17
PQ21
PQ22
2
PQ19
SI4686DY-T1-E3~D
2
G
SI4686DY-T1-E3~D
G
8
1
3
D
S
1
8
1
3
D
S
1
3
12
PC113
@
D5D6D7D
1500P_0603_25V7K~D
G4S3S2S
@
4.7_1206_5%~D
1 2
PHASE1
PQ18
FDMS8670AS_ POWER56-8
1500P_0603_25V7K~D
PC114
@
D5D6D7D
G4S3S2S
PR268
@
4.7_1206_5%~D
PQ20
FDMS8670AS_ POWER56-8
3
PR269
12
1 2
+CPU_PWR_SRC
12
PC91
0.1U_0603_25V7K~D
12
PC99
1000P_0603_50V7K~D
PR266
4.7_1206_5%~D
1 2
12
PC102
0.1U_0603_25V7K~D
PHASE2
12
PC110
1000P_0603_50V7K~D
PR267
4.7_1206_5%~D
1 2
12
12
PC93
PC92
2200P_0402_50V7K~D
1 2
PC103
PC94
10U_1206_25V6M~D
PL13
0.45UH_ETQP4LR45XFC_25A_20%~D
4
3
PR90
430_0402_1%~D
1 2
PR91
7.68K_0805_1%~D
@
VSUM
12
12
PC104
2200P_0402_50V7K~D
10U_1206_25V6M~D
0.45UH_ETQP4LR45XFC_25A_20%~D
PR109
430_0402_1%~D
1 2
PR111
7.68K_0805_1%~D
@
1 2
VSUMFBS
2
12
10U_1206_25V6M~D
1
2
PC98
1UU_0603_25V5K~D
+CPU_PWR_SRC
12
PC105
10U_1206_25V6M~D
PL14
4
3
1UU_0603_25V5K~D
FBMJ4516HS720NT_1806~D
1 2
@
1
1
+
+
PC88
2
100U_25V_M~D
Iccmax=TDB
I_TDC=TDB
OCP=TDBA, Intel spec=TDBA
12
1
2
PC109
12
PR121
0_0402_5%~D
PC89
2
100U_25V_M~D
12
PR88
0_0402_5%~D
12
PR92
0_0402_5%~D
VO
12
CSN2
PAD-OPE N 4x4m
12
PR106
0_0402_5%~D
12
PR112
0_0402_5%~D
@
VO
PL12
PJP32
1 2
+VCC_CORE
+VCC_CORE
1
DELL CONFIDENTIAL/PROPRIETARY
Title
Size Doc um e n t N u mb er Re v
Date: Sheet
2
Compal Electronics, Inc.
+VCORE
LA-4151P
45 57Friday, July 04, 2008
1
of
+PWR_SRC
0.2
5
PD30
B540C~D
2 1
PQ34
SI4835BDY-T1-E3_SO8~D
8
+DC_IN_SS
D D
C C
B B
A A
NB_AC_OFF <33,41,48>
NB_AC_OFF#
3
PQ68B
2N7002DW-T/R7_SOT363-6~D
5
4
365K_0402_1%
PR154
49.9K_0402_1%~D
PC146
0.01U_0402_25V7K~D
GNDA_CHG
0.1U_0402_10V7K~D
CKG_SMBCLK<6,21,34>
CKG_SMBDAT<6,21,34>
2
PR145
12
12
+5V_ALW
PC153
MAX8731_IINP<18>
ADAPT_TRIP_SET<33>
7
5
PR174
10K_0402_5%~D
PR52
12
MAX8731A_LDO
ACAV_IN<18,34>
12
MAX8731_IINP
5
12
PR152
10K_0402_1%~D
33.2K_0402_1%~D
61
PQ68A
2N7002DW-T/R7_SOT363-6~D
200K_0402_1%~D
+SDC_IN
1 2
GNDA_CHG
4
24K_0402_1%~D
+DOCK_PWR_BAR
+DC_IN_SS
MAX8731_REF
12
PR157
15.8K_0402_1%~D
PR162
MAX8731_REF
PR167
@
1 2
0_0402_5%~D
PR169
@
1 2
GNDA_CHG
@
12
8.45K_0402_1%~D
PC168
@
1
2
36
PR175
PR173
12
0.01U_0402_25V7K~D
12
0_0402_5%~D
PC164
12
GNDA_CHG
12
PR184
@
12
2
3
0.1U_0402_10V7K~D
ACAV_DOCK_SRC<48>
12
PR166
@
PR171
@
PR172
@
51.1K_0402_1%~D
17.8K_0402_1%
348_0402_1%~D
0_0402_5%~D
PD52
BAT54CW_SOT323~D
1
PR156
1 2
0_0402_5%~D
1 2
PR176
@
200K_0402_5%~D
12
PR159
PC241
@
10K_0402_5%~D
130P_0402_10V7K~D
1 2
12
PC165
0.01U_0402_25V7K~D
12
12
12
PC169
PC170
@
@
12
GNDA_CHG
0.01U_0402_25V7K~D
GNDA_CHG
100P_0402_50V8J
New Create Part Number
5
12
4
+SDC_IN
+DC_IN
12
PR143
10K_0402_5%~D
3
PQ67B
2N7002DW-T/R7_SOT363-6~D
4
12
PR150
33K_0402_5%~D
2000P_0402_10V7K~D
PC242
1 2
@
130P_0402_10V7K~D
12
12
PC156
PC157
0.01U_0402_25V7K~D
0.01U_0402_25V7K~D
1M_0402_1%~D
1 2
2
IN-
3
IN+
12
PC171
@
100P_0402_50V8J
GNDA_CHG GNDA_CHG G N DA_CHG
+5V_ALW
4
PQ67A
2
12
PC142
0.047U_0603_25V7K~D
1U_0805_25V4Z~D
GNDA_CHG
12
PC243
@
12
PC158
1U_0603_10V6K~D
PR164
@
GNDA_CHG
4
G
O
P
8
PC172
@
12
PR141
33K_0402_5%~D
12
PR146
10K_0402_5%~D
61
2N7002DW-T/R7_SOT363-6~D
PC145
12
MAX8731_IINP
1 2
PR262
@
7.5K_0402_5%~D
MAX8731_REF
PR263
@
1 2
0_0402_5%~D
GNDA_CHG
PU11A
LM393DR_SO8~D
1
12
PC173
@
100P_0402_50V8J
0.01U_0402_25V7K~D
PC163
0.1U_0402_10V7K~D
12
@
12
PC135
0.1U_0603_25V7K~D
13
1
2
2
3
PC138
@
0.1U_0603_25V7K~D
1 2
GNDA_CHG
DCIN
12
@
GNDA_CHG GNDA_CHG
PR168
@
100K_0402_1%~D
PC167
10P_0402_50V8J~D
PU10
22
DCIN
2
ACIN
13
ACOK
11
VDD
10
SCL
9
SDA
14
BATSEL
8
IINP
6
CCV
5
CCI
4
CCS
3
REF
7
DAC
12
GND
29
GND
12
12
0.22U_0402_6.3V6K
PQ33
@
RHU002N06_SOT323
3
PR140
0.01_1206_1%~D
1
2
@
10K_0402_5%~D
1
MAX8731AETI+_TQFN28~D
2
G
THIS SHEET OF EN GINEE RING D RAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
GND
PR165
@
PQ26
@
1 2
+3.3V_ALW+5V_ALW
100K_0402_5%~D
NTR4502PT1G_SOT23-3~D
PR177
PC143
28
CSSP
12
13
D
S
4
3
2
2
12
27
VCC
CSSN
BST
LDO
DLO
PGND
CSIP
CSIN
FBSA
FBSB
GNDA_CHG
13
1
3
12
PR149
DHI
LX
3
PQ25
NTGD4161PT1G_TSOP6~D
PR341
100K_0402_1%~D
26
0_0402_1%~D
BOOT
25
MAX8731A_LDO
21
24
23
20
19
18
17
VFB
15
16
12
PR170
+PWR_SRC
NTR4502PT1G_SOT23-3~D
PQ63B
S
D
42
G
3
NTGD4161PT1G_TSOP6~D
S
12
G
12
PR342
100K_0402_1%~D
VCC
PR155
4.7_0603_5%~D
1 2
PC147
PR158
12
0_0603_1%~D
12
PC154
220P_0402_50V7K~D
PR161
1 2
100_0402_5%~D
GNDA_CHG
ADAPT_OC <33>
1K_0402_5%~D
PQ63A
D
65
1
PR343
100K_0402_1%~D
1 2
1U_0603_10V6K~D
BOOT_D
12
PD17
RB751V_SOD323~D
CHG_UGATE
0.1U_0603_25V7K~D
CHG_LGATE
PJP34
1 2
PAD-OPEN1x1m
PC185
100P_0402_50V8J~D
GNDA_CHG
PJP33
1 2
PAD-OPEN 4x4m
DOCK_DCIN_IS+ <31>
DOCK_DCIN_IS- <31>
PC144
1 2
PR153
33_0603_1%~D
1 2
PC148
1U_0603_10V6K~D
2 1
1 2
PBATT+
MAX8731_REF
+DC_IN
12
PR345
232K_0402_1%~D
12
12
PR349
21.5K_0402_1%~D
GNDA_CHG
PC136
47P_0402_50V7K~D
SW_GND <48>
GNDA_CHG
PQ30
FDMC8878_POWERPAK 1212-8
PC155
@
3300PF_0402_50V7K~D
PQ32
FDMC8854_POWERPAK 1212-8
12
PR346
47K_0402_1%~D
12
PC186
PR350
27.4K_0402_1%~D
GNDA_CHG GNDA_CHG
2
CHAGER_SRC
12
12
PC137
@
0.1U_0603_25V7K~D
PQ31
FDMC8878_POWERPAK 1212-8
5
3
241
12
5
3
241
+VCHGR_B +VCHGR_L
5
3
241
GNDA_CHG
Maximum charging current is 4.7A
PR344
1M_0402_1%~D
1 2
+5V_ALW
8
5
P
IN+
7
O
6
IN-
G
PU11B
LM393DR_SO8~D
4
12
GNDA_CHG
100P_0402_50V8J~D
2
12
PC149
2200P_0402_50V7K~D
PL16
5.6UH +-25%_ MPLCH1040L5R6_7.6A
PC190
12
1000P_0603_50V7K~D
PR289
2.2_1206_5%~D
PC139
@
0.1U_0603_25V7K~D
1 2
1 2
+3.3V_ALW
MAX8731_REF
12
PR347
@
100K_0402_1%~D
12
PR163
PR354
PR355
@
GNDA_CHG
0_0402_1%~D
100K_0402_1%~D
TBD_0402_1%~D
0.01_1206_1%~D
1
2
12
0.22U_0402_6.3V6K
12
12
NB_AC_OFF#
DELL CONFIDENTIAL/PROPRIETARY
Title
Size Document Number Rev
Date: Sheet
12
12
PC150
0.1U_0603_25V7K~D
PR160
PC166
@
1 2
PR348
1 2
0_0402_5%~D
RB751S40T1_SOD523-2~D
PC151
10U_1206_25V6M~D
4
3
PC159
PD35
2 1
PC152
10U_1206_25V6M~D
12
PC160
0.1U_0603_25V7K~D
Compal Electronics, Inc.
Charger
LA-4151P
1
12
+VCHGR
12
12
PC161
PC162
10U_1206_25V6M~D
10U_1206_25V6M~D
ACAV_IN
ACAV_IN_NB <33,34>
1
46 57Fr id ay, July 04, 2008
10U_1206_25V6M~D
12
12
PR264
1.8K_1206_5%~D
13
D
PQ36
2
G
S
RHU002N06_SOT323
0.2
of
5
A
D D
4
PR216
0_0402_5%~D
GFX_VID4<10>
GFX_VID3<10>
GFX_VID2<10>
GFX_VID1<10>
GFX_VID0<10>
GFX_VR_ON<10>
1 2
PR217
0_0402_5%~D
1 2
PR218
0_0402_5%~D
1 2
PR219
0_0402_5%~D
1 2
PR220
0_0402_5%~D
1 2
1 2
PR221
0_0402_5%~D
3
2
1
24
BST
23
22
SW
21
20
DRVL
19
PGND
18
17
33
GNDA_VGA
12
PC216
+5V_ALW
1 2
12
GNDA_VGA
PR225
0_0603_5%~D
12
1000P_0402_50V7K~D
76.8K_0402_1%
PR237
12
PC219
1200P_0402_50V7K~D
PR223
10_0603_5%~D
PC204
1U_0603_10V4Z~D
PD25
RB751V-40_SOD323~D
BST_D
1 2
1 2
PC211
1U_0603_10V6K~D
12
12
PC205
4.7U_0805_10V4Z
169K_0402_1%~D
12
PR238
PQ50
FDMC8878_POWERPAK 1212-8
5
3
241
DRVH
PQ51
FDMC8854_POWERPAK 1212-8
5
1000P_0603_50V7K~D
2.2_1206_5%~D
3
241
PR239
1 2
69.8K_0603_1%~D
PR241
0_0402_5%~D
1 2
+VGFX_SRC
PC140
PR265
PJP38
1 2
PAD-OPE N 4x4m
12
12
12
PC203
10U_1206_25V6M~D
10U_1206_25V6M~D
PC62
2200P_0402_50V7K~D
PL19
0.42UH_MPCG0740LR42 _20A_20%~D
PH4
1 2
220K_0402_5%_ERTJ0EV224J~D
VGFX_CORE_FB
PC202
12
1 2
VGFX_NB
12
Thermal Design Current: 6.1A
Peak current: 8.7A
PC61
0.1U_0805_50V7K
OCP min: 10A
12
+PWR_SRC
+VGFX_COREP
PC214
1
1
+
+
PC213
PC212
2
2
330U_D2E_2.5VM_R7~D
VOUT=Vgfx_NB(1.25V)
L=0.42uF
Load line:6.9 mohm
Fsw=436K
D=0.0658
Output Ripple Current=5.88A
Output Ripple Voltage=5.88A*3.5mOhm=20.58mV
Input Ripple Current=TDC*(D*(1-D))^0.5=1.52A
Component select
Input CAP 10uF_1206_25V*2
Output Cap 330U_D2E_2VM_R7*2
H_MOSFET FDMC8878
L_MOSFET FDMC8854(5.6/7.6mOhm@4.5V, 13A)
Inductor 0.42U_MPCG0740LR42_20A(NEC_TOKIN)
330U_D2E_2.5VM_R7~D
12
0.1U_0402_16V7K
12
12
PC176
PC177
@
@
10U_0805_6.3V6M~D
10U_0805_6.3V6M~D
+3.3V_RUN
12
PR222
10K_0603_5%
PR362
0_0402_5%~D
PMONFS
PR230
1 2
187K_0402_1%
GNDA_VGA
1 2
FB
COMP
SS
ST
PMON
CLIM
1 2
1 2
1 2
PU15
1
FBRTN
2
FB
3
COMP
4
SS
5
ST
6
PMON
7
PMONFS
8
CLIM
PR231
78.7K_0402_1%~D
PR236
0_0402_5%~D
@
PR240
0_0402_5%~D
EN
32
30
31
PWRGD
VARFREQ#
LLINE9CSCOMP10CSREF11CSFB12RAMP13VRPM14RPM15RT
LLINE
CSREF
CSCOMP
VDD1
VDD0
EN
VID029VID128VID227VID326VID4
RAMP
CSFB
PR233
VDD3
VDD2
RPM
VRPM
1 2
200K_0402_1%~D
12
@
2200P_0402_50V7K~D
VDD4
25
VCC
BST
DRVH
SW
PVCC
DRVL
PGND
GND
AGND
ADP3209JCPZ-RL_LFCSP32_5X5~D
16
RT
12
PR234
357K_0603_0.5%
GNDA_VGAGNDA_VGA
PC218
IMVP_PWRGD<24,33,37,45>
VSS_AXG_SENSE<14>
C C
PR226
100_0402_5%~D
1 2
PC215
1000P_0402_50V7K~D
GNDA_VGA
VCC_AXG_SENSE<14>
B B
33.2K_0402_1%
VSS_AXG_SENSE
12
12
PR224
12
PC206
@
22P_0402_50V8J
PR227
12
1K_0402_1%~D
PR229
@
100_0402_1%~D
1 2
PR364
1 2
0_0402_5%~D
PWR_MON_GFX<18>
+VGFX_COREP
22P_0402_50V8J
20K_0402_1%~D
1 2
1 2
PC208
470P_0402_50V7K
GNDA_VGA
PC207
12
PR228
GNDA_VGA
PR232 200K_0402_1%~D
12
PC217
2.2U_0603_6.3VAK~D
12
12
12
PC209
0.012U_0402_16V7K~D
12
PR235
3K_0402_1%
VGFX_CORE_FB
GNDA_VGA
PC210
680P_0402_50V7K~D
GNDA_VGA
PJP39
PAD-OPEN1x1m
PR242
12
12
PC220
1000P_0402_50V7K~D
GNDA_VGA GNDA_VGA
340K_0402_1%
12
1K_0402_1%~D
12
PC221
100P_0402_50V8J
PR243
+VGFX_SRC
12
PJP40
+VGFX_COREP
1 2
PAD-OPEN 4x4m
+VCC_GFXCORE
A
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
Title
ADP3209 Power Up both Intel GMCH and ATI M54
Size Doc um e n t N u mb er Re v
Date: Sheet
Compal Electronics, Inc.
LA-4151P
47 57Friday, July 04, 2008
0.2
of
5
+DOCK_PWR_BAR
D D
+3.3V_ALW2
12
PR182
100K_0402_5%~D
ACAV_DOCK_SRC#<31>
C C
SI4835BDY_SO8~D
PQ45
8
+VCHGR
B B
PBATT_OFF<33>
A A
7
5
+3.3V_ALW
12
PR353
3
PQ62B
2N7002DW-T/R7_SOT363-6~D
5
4
PBATT_OFF<33>
DOCK_AC_OFF<31,33>
5
4
12
61
100K_0402_5%~D
2
PR352
47K_0402_1%~D
2N7002DW-T/R7_SOT363-6~D
21
+3.3V_ALW2
12
3
5
4
1
2
36
PR291
12
PR351
240K_0402_5%~D
PQ62A
PBATT_OFF<33>
PD34
RB751S40T1_SOD523-2~D
PR292
PR183
100K_0402_5%~D
PQ64B
2N7002DW-T/R7_SOT363-6~D
390K_0402_5%~D
1 2
PR293
2
390K_0402_5%~D
1 2
3
PQ55B
2N7002DW-T/R7_SOT363-6~D
5
4
21
PD36
RB751S40T1_SOD523-2~D
4
61
PQ64A
2
2N7002DW-T/R7_SOT363-6~D
PBATT+
PR294
620K_0402_5%~D
1 2
61
33_0402_5%~D
2N7002DW-T/R7_SOT363-6~D
PQ55A
4
12
PR147
100K_0402_5%~D
12
PR179
22K_0402_5%~D
2N7002DW-T/R7_SOT363-6~D
PQ69B
FDS6679AZ_SO8~D
1
2
3 6
4
12
12
SLICE_BAT_PRES#<31,33,41>
+3.3V_ALW +3.3V_ALW
12
13
D
2
G
S
3
5
4
PQ41
8
7
5
+DC_IN_SS
PC193
1U_0805_25V4Z~D
12
PR357
330K_0402_5%~D
PR178
100K_0402_5%~D
PQ65
RHU002N06_SOT323
SW_GND <46>
61
2
PQ69A
2N7002DW-T/R7_SOT363-6~D
PR360
0_0402_5%~D
PBATT_IN_SS
PD19
12
RB751V-40_SOD323~D
+3.3V_ALW2
12
PR329
100K_0402_5%~D
SLICE_BAT_PRES
3
PQ56B
2N7002DW-T/R7_SOT363-6~D
5
4
3
PD27
B540C~D
2 1
FDS6679AZ_SO8~D
PQ23
8
7
5
12
PR180
100K_0402_5%~D
NB_AC_OFF <33,41,46>
61
PQ66A
2N7002DW-T/R7_SOT363-6~D
2
+5V_ALW
12
PR181
22K_0402_5%~D
NB_AC_OFF_BJT <41>ACAV_DOCK_SRC <46>
3
PQ66B
2N7002DW-T/R7_SOT363-6~D
5
4
SLICE_BAT_PRES
12
D
42
47K_0402_5%~D
PR363
1K_1206_5%
PC192
1U_0603_25V6-K~D
12
12
+NBDOCK_DC_IN_SS
+DOCK_PWR_BAR
PQ59B
NTGD4161PT1G_TSOP6~D
S
G
3
PR325
1 2
240K_0402_5%~D
PR327
1 2
61
PQ56A
2N7002DW-T/R7_SOT363-6~D
2
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
1
2
36
4
12
PR148
47K_0402_1%~D
PR361
@
330K_0402_5%~D
1 2
PR326
1 2
240K_0402_5%~D
12
12
PR142
PC141
240K_0402_5%~D
0.47U_0805_25V7K~D
IMD2AT-108_SC74-6~D
+DC_IN_SS
PQ59A
NTGD4161PT1G_TSOP6~D
S
D
65
G
1
PR328
1 2
47K_0402_5%~D
13
D
PQ61
2
RHU002N06_SOT323
G
S
PQ24B
IMD2AT-108_SC74-6~D
4 3
PQ24A
PD20
RB751V-40_SOD323~D
2
2
16
PD51
3
2
RB715F_SOT323~D
12
D
S
2
12
PR144
22K_0402_5%~D
EN_DOCK_PWR_BAR#
5
PQ28
RHU002N06_SOT323
13
D
2
G
S
1 2
PR151
22K_0402_5%~D
2
3
PQ42
FDS6679AZ_SO8~D
8
7
5
1
PR186
47K_0402_5%~D
PQ70
RHU002N06_SOT323
13
2
G
PR358
0_0402_5%~D
PR359
@
0_0402_5%~D
1
EN_DOCK_PWR_BAR <33>
PD31
PDS5100H-13_POWERDI5-3~D
1
1
2
36
4
1 2
12
12
12
PC174
2200P_0402_50V7K~D
EN_DOCK_PWR_BAR#
ACAV_DOCK_SRC
+PWR_SRC
12
PC175
0.1U_0603_25V7K~D
DELL CONFIDENTIAL/PROPRIETARY
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
Selector
LA-4151P
1
48 57Fr id ay, July 04, 2008
0.2
of
5
4
Version Change List ( P. I. R. List )
3
2
1
Item Issue DescriptionDate
D D
2
3
4
5
6
7 CPU 12/14/2007 HW Add R1059 H_RESET# pull up +1.05V_VCCP and Depop R1059 Depop R1059
9 CPU 12/14/2007 HW For Intel CPU power transient Change C56,C57and C58 to 470UF
10 MCH 12/14/2007 HW For Intel request for DP function Change R180,R181,R182 and R183 to 4.02K
10,34 MCH 12/14/2007 HW For design issue Change U80 and U57 to 74AHC1G08GW
13 MCH 12/14/2007 HW For disable TV-OUT function
Owner
For Intel request power seqHW12/14/2007MCH13
Depop D1 and R122
Modify U78.K30 to GND plane
-Disconnect PWR_MON_GFX from U3.45
7
18 EMC4002 12/14/2007 Dell For Dell request
-Connect U3.45 to MAX8731_IINP with a 4.7k series resistor
-Identify the values of R1033 and R1061
8
C C
9
10
11
12
13
14
15
18 EMC4002 12/14/2007 Dell For U3 POWER_SW# Input-Add AND Gate
21 DP 12/14/2007 Intel Follow Intel proposal for DP interoperability Add U94,U95,Q163,Q164,C1159,R1073,R1074 and C1160
31 Docking 12/14/2007 Compal For Docking ESD concern Add D73
32 USH 12/14/2007 Broadcom Follow Broadcom request to modify schematics for USH
33 SIO 12/14/2007 Dell GPIO Map update
33 SIO 12/14/2007 Dell
The LCD/LED will keep had power with USB
device when unplug AC & Battery
33 SIO 12/14/2007 Dell On Battery Mode U35 have +3.3V backdrive
33 SIO 12/14/2007 Dell Add PD on SYS_LED_MASK# Add R1069
-Add U93,C1158,R1063,and R1064
-Change R142 to 0ohm
-Add R1066,R1067,R1068 and del R495,R499 and change R771 to 1K
-Depop R1067,R490,C594,C591,R467 and pop R829,add R1072
-Changed pin 82 from USB_CHARGER_PWR_EN# to ESATA_USB_PWR_EN#
-Change pin 104 from ESATA_USB_PWR_EN# to USB_POWERSHARE_PWR_EN#
-Add 100k no pop pull-ups to +3.3V_ALW2 on:
USB_SIDE_EN#,ESATA_USB_PWR_EN#,USB_POWERSHARE_PWR_EN#
-No stuff R502, R504, R1013.
-Add diode on signal INSTANT_ON_SW# to 5028 pin 28
-Add D74 and R1070
Solution Description Rev.Page#1Title
X01
X01
X01
X01
X01
X01
X01
X01
X01
X01
X01
X01
X01
X01
X01
Request
16
B B
17
18
19
20
21
22
23
24
A A
33 SIO 12/14/2007 Compal Change BID to X01(001) Pop R529 and depop R534
33 SIO 12/14/2007 Dell GPIO Map update Add U96 and C1161 X01
34 EC 12/14/2007 Dell GPIO Map update
-Del U59,C1012,R553,R558 and add R1071,Change R1050 from 1K to 33K
-Change ACAV_IN_DOCK# to ACAC_DOCK_SRC# ACAV_IN_MB/DOCK to ACAV_IN
35 EC 12/14/2007 Dell GPIO Map update -For BKT add U38.15 to BKT_GPIO17 connect to D71.2
38 LED 12/14/2007 Compal Backdrive from +3.3V_WLAN to +5V_RUN on S3 mode Add D75 between Q97 and Q98
38 LED 12/31/2007 Compal Add Bypass Capacitor for TTL Gate Add C1162~C1165
USH32 12/31/2007 Broadcom Follow Broadcom request to modify schematics for USH
-Change R476 to 5.1M ohms and R488 to 3.3M ohms to lower
-Pop D70, C641, C647,add R1077 and Depop R464,R1077
Docking 12/31/200731 Dell Roush + Docking AC protect issue(crowbar) Add D77, R1075,R1076,and Depop R124.
33 SIO 12/31/2007 Dell For Power change Media Slice issue Add D78, R1079 and Depop R1078.
X01
X01
X01
X01
X01
X01
X01
X01
25 21,40 USB 01/03/2008 Compal For power leakage for USB switch Change U97,P/N from FSUSB31K8X_US8 to TS3USB31RSER_QFN8
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
Changed-List History1
LA-4151P
49 57Fr id ay, July 04, 2008
1
0.5
of
5
4
Version Change List ( P. I. R. List )
3
2
1
Item Issue DescriptionDate
D D
16,17 DIMM 01/03/2008 ME For ME team change foxconn to main source
Owner
-Change DIMMA P/N from TYCO_2013022-1 to FOX_AS0A620_U4SN-7F
-Change DIMMB P/N from TYCO_2013297-1 to FOX_AS0A620_U8SN-7F
27 34 SIO 01/03/2008 HW Update Cell charger detect circuit Add D79
28 29 Fingerprint 01/03/2008 HW Follow Broadcom request to modify schematics for USH Modify JBIO3.5 from U19.A16 to U32.C3(FP_RESET#)
29 24 SB 01/03/2008 HW For LOM Disable concern Add R1065 and Depop R1065 and del R935
30 40 BKT 01/03/2008 HW
For BKT function concern and bypass BKT function
31 34 SIO 01/04/2008 HW For GPIO update
32 19 LVDS 01/07/2008 X01
HW/ME
For ME team change LVDS connector and cost down action
for BKT function
For HW concern2133 01/08/2008BTB HW
C C
34 21,33 BTB 01/08/2008 HW For HW concern
-Del U81 and U86.6 connect to GND
-Add RN1~RN6 and depop
-Modify U36.41 to DOCK_POR_RST# connect to JDOCK1.140
-Add C1167,R1082
-Modify LVDS connector to SP02081020
-Modify LVDS1.4 from PNL_BKLT_CBL_DET# to +3.3V_RUN
-Swap netname LCD_VCC_TEST_EN and BKT_GPIO2
Modify pin-name from JBIO1.109,111,113~123 to JBIO1.107,109,
111~121 and change JBIO1.139 from +1.8V_LAN_M to +LOM_VCT
-Add D80 and R1083 to pull up +3V_ALW2
-Add R1084 pull up to +3V_ALW and depop
35 35 ECE1088 01/08/2008 HW For GPIO update Modify U38.15 from BKT_GPIO17 to BKT_GPIO19
36 21,33 BTB 01/08/2008 HW For GPIO update
-Modify from WIRELESS_ON/OFF# to WIRELESS_ON#/OFF
-Del R489,R830 and netname SC_DET from U35.84
37 21 DP 01/09/2008 HW For Intel DP solution update Add R1085,R1086,R1087,R1088 X01
38
23,27,32,34 Crystal
39
35 TouchPAD
01/09/2008
01/09/2008
HW For EA test result for crystal
ME For ME team change connector Change JTP1 to SP070801070
-Change Y3 to SJ100005X0L,C674 to 27PF
-Change C608,C296,C297 to 12PF,C609,C1032,C1058 to 15PF
Solution Description Rev.Page#26Title
X01
X01
X01
X01
X01
X01
X01
X01
X01
X01
X01
X01
Request
40 38 LED 01/09/2008 ME For ME team change LED board to FPC Change JBIO5 pin-define
41 21,35 WLAN 01/10/2008 HW For GPIO update for WLAN switch
B B
Add BKT_GPIO12(U38.8) and BKT_GPIO13(U38.9) connect to JBIO1.75
and JBIO1.120
42 07 ITP 01/10/2008 HW For Intel ITP solution update Change R62,R64,R65,R66,R67 from 51ohm to 56ohm and R977 depop
43 32 USH 01/11/2008 HW Follow Broadcom request to modify schematics for USH Add R1089
UMA display TV solution implementHW01/14/2008MCH1044
HW01/14/2008MCH1045
Follow Roush UMA implement (CRT/LVDS)
UMA display TV solution implementHW01/14/2008MCH1146
ICH9M2347 Follow Roush UMA implement
HW01/14/2008
Follow Roush UMA implementHW01/14/2008DP/Card1 IO2148
A A
ICH9M24,3549
HW01/14/2008
HW01/15/2008LVDS19 Add D81 between LVDS and MCH, ADD 1091 pullup.
CIS Symbol update
BIA_PWM signal seems to be floating in " BKT mode ".50
Remove TV_CVBS/TV_Y/TV_C signals with pull down resistors
(R674,R677 and R678). Connect pin J27,E27 and G27 to GND
Remove R1048,R1049(CRT_H/VSYNC)pull up. Change R688 from
2.37K_1% to 2.4K_1%; Change R672 from 1.02K_1% to 976_1%
Change pin N32 of U78(VCCD_TVDAC) from +1.5V_RUN to GND. Remove
C138 and C139
Remove R952, connect pin AC23 of U79 to pin2 of R237
Remove BIO_DET# net(Del. R823,R932; pin A16 of U79), depop R754
Add R1090(100K)pull up to +3.3V_ALW_ICH on PCIE_MCARD1_DET# net,
make R439 depop; change C1135 from .1uf to 1uf
Link JP3(Change to JP6) and JTP1
X01
X01
X01
X01
X01
X01
X01
X01
X01
X01
X01
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
Changed-List History2
LA-4151P
50 57Fr id ay, July 04, 2008
1
0.5
of
5
4
Version Change List ( P. I. R. List )
3
2
1
Item Issue DescriptionDate
51 6 CLKGEN For component derating 03/04/2008 HW L1 change to SM01002480L
D D
52
7 CPU 03/04/2008 HW For ITP modify solution
Owner
R57 change to 124ohm, R64 change to 39ohm, R65 change to 150ohm,
R66 change to 649ohm, R67 change to 27ohm
53 9 CPU 03/04/2008 HW For CPU power loadline solution C52 change to pop and C56,C57,C58 change to 270UF(SGA00003H0L) X02
54 10 MCH 03/04/2008 HW For DP modify solution R180,R181,R182,R183 change to 2.2K ohm X02
55 19 PFG 03/04/2008 HW Add Camera solution for PFG
Add Q165,Q166,R1094(unpop),R1095,R1096,R1097,R1098,C1168,C1169
C1170,C1171,U98(unpop),L70(unpop),JCAM and net CAM_MIC_CBL_DET#
56 19 LVDS,JBIO1 03/04/2008 HW For BKT table updated Modify D68.2 to BKT_GPIO18 for +LCDVDD power and X02
57 21 Audio 03/04/2008 HW For audio vendor solution R327,R828 change to 499K ohm and R328 unpop X02
58 27 R5C833 03/04/2008 HW For R5C833 crystal solution by test result Modify X2(SJ124P5M53L)-->Y2(SJ10000690L) X02
59 29 FP 03/04/2008 ME For FP connector change Modify JBIO3(Tyco_1734820-6)-->(TYCO_1734242-6) X02
C C
60 32 BCM5880 03/04/2008 HW For EMI solution by BCM5880
61 33 ECE5028 03/04/2008 HW For ECE5028 and board ID updated
62 34 ECE5035 03/04/2008 HW For ECE5035 updated
Add L71,L72,C1172,C1173
R841 change to 3K and R473 change to 1K,R849 pop
Del R1084, add PWR_BTN_BD_DET#
R529(unpop),R534(pop),R530(pop),R535(unpop) for X02
Modify R560 to pop,R877 change to 200K and
R565,R567 change to 2.2K ohm
63 38 LED 03/04/2008 HW Add WLAN LED share to BKT LED Add Q167,Q168
64 38 PWR board 03/04/2008 ME For PWR board connector change
65
39 BKT function 03/04/2008 HW For BKT function updated
JBIO4 change from Tyco_1734242-4 to Tyco_1734242-6
add PWR_BTN_BD_DET# for PWR board
Modify +3.3V_RUN_BKT_PWR source to alway pop
Add net BKT_LED to control LED
66 40 BKT function 03/04/2008 HW For BKT table updated Modify U86.9 to BKT_GPIO11(U38.14)
Solution Description Rev.Page# Titl e
X02
X02
X02
X02
X02
X02
X02
X02
X02
X02
Request
67 24 SPI 03/04/2008 HW For del recovery bios function Del U13,R295,R303,R304,R305,R306,R308,R309,C329 X 0 2
B B
68 31 Dock 03/04/2008 HW For Docking ESD concern Modify D73 from SC10T24C010 and SC600000N0L X02
69 36 Power 03/04/2008 HW For power control concern Reserve R1100,R1101 to bypass level shift X02
70 29,35 BKT function 03/05/2008 HW For BKT table updated Add net BKT_GPIO17 and R1104(unpop),D82 for Biometic reset signal X02
71 35 TP 03/06/2008 HW For backdrive from Touch PAD Modify R594,R595 pull-up to +5V_ALW X02
72 32 USH 03/06/2008 HW For smart card concern Modify R849 to 1.5K and R973 to 300ohm X02
73 38 03/07/2008 HW For keyboard LED modify
74 19,22
A A
LED
Camera 03/10/2008 HW For Camera function Modify net name from CAM_MIC_CBL_DET# to CAM_CBL_DET# X02
-Modify JBIO5 to TYCO_1-1734242-2 and add net MASK_BASE_LEDS#
-Q120.3,Q121.3,Q122.3 modify to +5V_ALW
X02
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
Changed-List History3
LA-4151P
51 57Fr id ay, July 04, 2008
1
0.5
of
5
4
Version Change List ( P. I. R. List )
3
2
1
Item Issue DescriptionDate
75
D D
76 04/07/2008
77
78
79
80
81
33
38
33
18
34
24
Docking Slice battery issue04/07/2008 HW change R1076 from 1K to 910K X0331
EC5028
LED
EC5028
EMC4002
EC5035
SPI ROM
04/07/2008
04/07/2008
04/07/2008
04/07/2008
04/07/2008
Owner
HW
HW
HW
HW
HW
HW
Support wireless on#/off switch on BLT mode
Blue LED brightness concern
Roush MB side have backdrive when plug some USB device
which have extra-power source
Vendor recommend value
Remove reserved SPI ROM at EC side.
Reserved 2nd SPI ROM for code size over 4M byte.
change R874 to depop
R659, R663, R125, R661, R556, R596, R655, R1037, R1042, R1045
change from 150 ohm to 1K ohm
R504 change to 10K and made pop.R502 and R1013 change to pop
R1033 change to 200K
Remove U37,C672,R589,R590,R591,R592,R593 and R558
Add U13,C329,R295,R304,R305,R306,R308,,R307 and R309
D28 and D29 change connect to RFREADER_TXN1_P1 and RFREADER_TXP1_P1
82
C C
32
USH
04/07/2008
HW
Vendor recommend schematics for EMI
R494 and C639 change connect to RFREADER_TXN1
R498 and C643 change connect to RFREADER_TXP1
Add U99~U101(SN74CBTD3306) and C1174~C1175(0.1UF)
83
21
DP
04/07/2008
HW
Vendor recommend schematics for DP switch
R1053 change from 100K ohm to 1M ohm
Del Q19,Q20,Q163,Q164,R958,R960,R964,R966,R1073,R1074
84
85
86
87
88
B B
12
24,33
35
06
40
TV
EC5028,
SPI ROM
TouchPAD
Clock
BlackTop
89 19 Camera 04/07/2008
90
91
92
38 LED 04/09/2008 HW Add WWAN LED control on BLT mode X03
27 R5C833 04/09/2008 HW
29 PWR SW 04/09/2008 HW Remove PWR SW for debug Remove PWRSW1,PWRSW2 and C684 X03
04/07/2008
04/07/2008
04/07/2008
04/07/2008
04/07/2008
HW
HW
ME
Vendor recommend schematics for TV disable
GPIO table update
ME concern need to shorten TouchPAD FFC length
Isolate CLK_PCI_DOCK signal that has risk for docking
HW
HW
scenarios.
USB interface change for BKT to ICH
HW Camera pinout modify for vendor
Add SC CLK impedance control between chip(20~30 ohm)
and connector
Add R1105~R1107 to 75 ohm
Add net name SPI_WP#_SEL and R1108~R1109(0 ohm)
Swap JTP1 Pin1~Pin16 net name
change CLK_PCI_PCM to U1.33
Del U83 and C1144,Modify U97.5 to USB1-,U97.3 to USB1+ and U85.6
from BKT_GPIO3 to GND and change U97.1to BKT_GPIO3
USBP11_D- change to JCAM.2,USBP11_D+ change to JCAM.3
CAM_CBL_DET# change to JCAM.5
Modify R206.1 to +3.3V_RUN_BKT_PWR and Q115.3 to +5V_TP_PWR
Add R1110 X03
Solution Description Rev.Page# Titl e
X03
X03
X03
X03
X03
X03
X03
X03
X03
X03
X03
X03
X03
X03
Request
93
94
95
96
A A
97 10 S3 04/21/2008 HW Modify U80 power to +3.3V_ALW_ICHFixed S3 resume
21 I/O 04/10/2008 HW Vendor I/O connector update Remove JBIO1.141~144 X03
06 Clock 04/14/2008 HW
29,32 Hall sensor 04/16/2008 ME
Vendor recommend schematics modify to damping resistor
for share CLK signals
Modify Hall sensor from smart card connector to
SPK connector
Modify R27 to 33ohm X03
Modify JSC1 to 10pin and JSPK1 to 9pin connector X03
24,27 RF issue 04/21/2008 HW Add 14M/33M/48MHz terminator for RF issue POP R279,C312,R285,C318,R803 and C1057 X03
X03
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
Changed-List History4
LA-4151P
52 57Fr id ay, July 04, 2008
1
0.5
of
5
4
Version Change List ( P. I. R. List )
3
2
1
Request
Date Issue DescriptionItem TitlePage#
D D
98
Owner
HW04/21/2008 Reserve 24 pcs high frequence for ULV CPUCPU Add C1176~C1199 X039
Thermal 04/22/200899 HW X0318 Modidy thermal protect on 95 degree change R151 to 1.5K
100 21 DP 04/23/2008 HW Update new DP swith schematics Depop R1085~R1088 X03
101 36
102 39 BLT 04/25/2008 HW
backdrive 04/24/2008 HW Fix +3.3V_RUN backdrive from North bridge Modify R625 to 33ohm 0603 and pop Q79 X03
Update BLT GPIO table Add BKT_GPIO5 connect to JBKT1.63 X03
Add U103,C1200,C1201 and del U92,C1156,C1157,R1060 ,U79.V10
103 10,36 Audio 05/22/2008 HW Fix WLAN card intermittent can't detect
change to +1.5V_ALW_HDA R153 change to 3.16K R154 change to
5.1K, del R314,R315 and U79.AD7 change to +1.5V_RUN
104 38 LED 05/22/2008 HW Fix +5V_RUN backdrive on BLT mode Add D83
105
C C
33
106 27
107
24
108 36
109 30,38
110 29,38
111 28
112 35 connector
113 32 USH 06/13/2008 HW Modify USH component tolerance
B B
Slice Battery
1394
ICH
06/10/2008 HW Fix slice battery concern on power Change R503 from 100K to 4.7K
06/10/2008 HW Fix 1394 reset timing Modify R801 to 47K
06/10/2008 HW Update GPIO table for TPM and TCM Add R1111
06/10/2008 HWbackdrive Fix +3.3V_RUN backdrive from North bridge Modify R625 to 39ohm 0402
connector 06/11/2008 ME Fix ME concern for factory build Modify JBT and JBIO5 to SP070805091(TYCO_1-2041070-2)
connector 06/11/2008 ME Fix ME concern for factory build Modify JBIO3,JCAM,JCS1 and JBIO4 to SP070805092(TYCO_2041070-6)
connector 06/11/2008 ME Fix ME concern for factory build Modify JEXP1 to SP070805271(TYCO_2-2041070-6)
06/11/2008 ME Fix ME concern for factory build
Modify JEXP1 to SP070805270(TYCO_1-2041070-6)
JSATA1 to SP01000SE0L(TYCO 2-1759838-5)
Modify L71,L72 change to SHI00005Y0L
and C639,C643 change to +-10%
114 12 NB 06/13/2008 HW Update NB reference schematics Add C1202
115 29 SPK
06/16/2008 ME
Modify SPK connector pin define to improve cable
routing for ME concern
Re-define SPK connector pin-out
116 6 CLKGEN 06/20/2008 HW Fix setup ME power package5 issue when power on Add R1112
Rev.Solution Description
X04
X04
X05
X05
X05
X05
X05
X05
X05
X05
X05
X05
X05
X05
117 38 LED 06/20/2008 HW Fix LED flash bright when unplug AC Add R1113
118
119 30 BT 06/20/2008 HW Fix BT cable for factory assemble
120 30 TCM 06/20/2008 HW Update TCM reference schematics
A A
21 USB Charge 06/20/2008 HW Follow Roush reduce USB charge schematics Delete R995
Modify BT_DET# from JBT.1 to JBT.12
Add R1115~R1119,C1202,C1203 and R383 change to 10K,R884 change to
1K and delete R381,R382
X05
X05
X05
X05
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
Changed-List History5
LA-4151P
53 57Fr id ay, July 04, 2008
1
0.5
of
5
4
Version Change List ( P. I. R. List )
3
2
1
Item Issue DescriptionDate
D D
2
Battery slice
41
application
Charger 12/13 Dell
46/48
46
Charger
3
4
46 Charger 12/13
12/13 Dell for Slice battery to detect NB battery is
12/13
Owner
Dell
insert or not.
To block +PWR_SRC (19.5V) from
Docking connector DOCK_DCIN_S +/- pins when NB is not docked
Charger of ISL88731 will turn off
When ACIN is no power
This change to allow charging when AC adapter only in Dock.
Note TI and Intersil version of charger will disable
charging when AC OK goes low.
Add PQ47(FDN338P_NL), PD22(RB751V) and PR234 (0 ohm)
Add PQ63 A/B(NTGD4161PT1G),P341(100K),PR342(100K),
PR343(100K).
Add PQ46 RHU002N06 to control PQ62 on/off
Add LM393 to replace ISL88731 ACOK function(PU11B)
Add PR345(232K),PR346(47K),PR349(21.5K),PR350(27.4K)
Add PR344(1M),PR347(100K), PR348(0)
Add PC185(0.1U),PC186(100P)
Remove PR188 and PR187,
Change PR145 from +DC_IN to +SDC_IN.
change PR157 net name from ACAV_IN_NB to ACAV_IN.
Maxim charger function was fine.
The added comparator circuit is used to give BIOS
indication when AC adapter is inserted or removed from
C C
5
6
46 Charger 12/13 Dell Change PQ36.2 connection
Charger
12/1346/48
Dell
48 Selector 12/13 Dell PBATT back drive to Battery Slice
7
notebook.
Replaces charger AC OK function.
Change all notebook signal
name's "ACAV_IN_DOCK" and "ACAV_IN_DOCK#" to
"ACAV_DOCK_SRC" and "ACAV_DOCK_SRC#" respectfully.
Change PQ36.2 connection
from ACAV_IN_NB to "ACAV_IN"
vias charger high side MOSFET
Change PQ40_Pin1 from "ACAV_IN_DOCK#" to "ACAV_DOCK_SRC#"
Change PQ40_Pin2 from "ACAV_IN_DOCK" to "ACAV_DOCK_SRC"
Change PQ43_Pin2 from "ACAV_IN_DOCK" to "ACAV_DOCK_SRC"
from ACAV_IN_NB to "ACAV_IN"
Add PQ45 between PBATT+ and +VCHGR
Use PBATT_OFF control PQ62 to switch PQ45
Add PR351(240K), PR352(47K) and PR353(100K)
8
48
Selector 12/13 Compal PBATT_OFF connect to DOCK_AC_OFF Add PD34 RB751V-40 X01
Solution Description Rev.Page#1Title
X01
X01
X01
X01Dell
X01
X01
X01
Request
9
B B
10
11
41 DC_IN 12/13 Dell Add PC183 and non-stuff
42 +3.3V/+5V 12/13 Dell EE work item
48 Selector 12/14 Compal
For save the placement space, use one dule MOS chip to
replace 2pcs MOS chip
Add PC183 and non-stuff X01
Change PL6 and PL7 from HMP1350-3R3LD-R to SSC-1350F3-2R8
Change PQ6 and PQ7 from FDMC8878 to FDMS8692
X01
Add PQ64 A/B (2N7002DW-T/R7) to replace PQ29 and
PQ40 (RHU002N06)
X01
Add PQ65 A/B (2N7002DW-T/R7) to replace PQ37 and
PQ46 (RHU002N06)
Add PQ66A/B (2N7002DW-T/R7) to replace PQ 38and
PQ39 (RHU002N06)
12
46 Charger 12/14 Compal
For save the placement space, use one dule MOS chip to
replace 2pcs MOS chip
Add PQ67 A/B (2N7002DW-T/R7) to replace PQ27 and
PQ43 (RHU002N06)
X01
Add PQ68 A/B (2N7002DW-T/R7) to replace PQ35 and
PQ44 (RHU002N06)
13
14 45 CPU_VCORE 12/14 Compal Connect MAX8786_VCC to PU7_Pin3 to disable third phase Connect MAX8786_VCC to PU7_Pin3 X01
A A
42 +3.3V/+5V 12/14 Compal
ME highet limit issue
Change PL16 from HMU1356-5R6 to MPLCH1040L5R6
X01
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
Changed-List History
LA-4151P
54 57Fr id ay, July 04, 2008
1
1.0
of
5
4
Version Change List ( P. I. R. List )
3
2
1
Item Issue DescriptionDate
D D
2
3
48 Selector 1/7
46 Charger 1/7
48 Selector Hot dock issue, adapter crowber1/7
Owner
AJ
Compal
Merle
DELL
Merle
DELL
Charger for Battery Slice
Change PQ63 to 2N7002DW
Add PR360 0_0402_5% between PQ63 and SLICE_BAT_PRES
Charger Isense MOSFET timing change PC142 change to 0.047u_0603_25V
Add PR357 330K_0402 form +DOCK_PWR_BAR to GND.
Add PQ70 RHU002N06 parallel PQ61, series PR358 0_0402
to EN_DOCK_PWR_BAR#,serial PR359 0_0402 to ACAV_DOCK_SRC
4
5
41 +DC_IN 1/7
PWR
Snubber
1/9
Doug
DELL
Guangyong
DELL
PJPDC1 change to 7pin connector
DELL request add a snubber circuit
on every regulator
PJPDC1 change to MOLEX_87438-0743_7P-T
Change PR20 to 0_0402_5% and populate
Add below location of regulator switching node
+3.3V_ALW: PR290, PC191 +5V_ALW: PR288, PC189
+1.5V_RUN:PR287, PC188 +1.05V_M:PR286, PC187
+VCHGR:PR289, PC190
6
C C
41
+DC_IN
1/9
Battery
Team
DELL
Change Battery Pin from 9 to 7pin Change Battery Pin from 9 to 7pin
Populate PR224
7
47 ADP3209
NB_CORE
8
45 CPU_CORE 1/10 Compal The load line SPEC is 4 mohm for SFF SV CPU
1/10 Guangyong
DELL
Modify ADP3209 schematic
Follow ADI suggestion
Change PR239 from220K_0603_1% to 49.9K_0603_1%
Change PR238 from 140K_0402_1% to 169K_0402_1%
Change PC219 from 2200p_0402_50V to 1200p_0402_50V
Change PR124 from 6.49K_0603_1% to 14.3K_0603_1%
Change PR118 from 4.99K_0402_1% to 6.34K_0402_1%
Change PR136 from 1.43K_0402_1% to 732_0402_1%
Change PR90 and PR109 fro, 2K_0402_1% to 430_0402_1%
Change P98 and PC109 from 0.22U_0603_10V to 1U_0603_25V
No stuff PC131, PC132 and PC133
46 Charger 2/19
BO
DELL
Maxim Charger from powering on while in S5 and battery only
9
B B
1. Un-pop PR184, PR347.
2.Add PD52 BAT54CW_SOT323,
+DOCK_PWR_BAR/+DC_IN_SS
Reserve PR184 0_0402_5% form +SDC_IN to PU10 PIN22
3. Add PR354 (10K), MAX8731A_REF/PR348_Pin1
ADD PR355 (41.2K) PR348_Pin1/GND
Solution Description Rev.Page#1Title
X01
X01
X01
X01
X01
X01
X01
X01
X02
Request
10
11
12
48 Selector 3/4
47 +VGFX_CORE 3/4
Merle
DELL
AJ
Compal
Kenny
Compal
Fix BITS CR196131 and CR19613046 Charger 3/4
for reducing leakage current.
for VGFX-CORE test
Add PR363 1K_1206 and PC192 1U_0603_25V from
+NBDOCK_DC_IN_SS to ground.
Add PD35 RB751S40T1_SOD523-2 from NB_AC_OFF# to
ACAV_IN_NB.
Change PD31 from SCSB540C08L(S SCH DIO B540C-13-F SMC) to
SCS00002M0L(S SCH DIO PDS5100H-13 POWERDI5).
Add PR364 SD02800008L(S RES 1/16W 0 +-5% 0402 between
VCC_AXG_SENSE and PR227.2
X02
X02
X02
Add PR362:SD02800008L(S RES 1/16W 0 +-5% 0402) between
IMVP_PWRGD and pin31 of PU15.
13
PWR Snubber
3/5 Compal
EMI
In order to meet the derating requirement,
change the resister component size
Change component sixe from 0805 t0 1206 below location of
regulator switching node
X02
+3.3V_ALW: PR290 +5V_ALW: PR288,
A A
+VCHGR:PR289, Vcore: PR266,PR267,PR268 and PR269
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
Changed-List History
LA-4151P
55 57Fr id ay, July 04, 2008
1
1.0
of
5
4
Version Change List ( P. I. R. List )
3
2
1
Item Issue DescriptionDate
D D
2
3
4
5
C C
48 Selector 3/6 MERLE
46 Charger
3/6 Compal Material smooth control
41 DC_IN 4/8 AJ
45 VCORE
43 +1.5V/1.05V
42,43,
45,46,
EMC&Noise 4/8
4/8 James
4/8 Compal Chenge logic high level voltage for OE pin
47
Owner
DELL
Compal
Compal
EMI and
Key Part
DELL
Application for Battery Slice
SPACE limitation
PWM circuitry DH/DL still switch a few cycles in all
3 phase after power off resulted in a voltage pulse
observed at output Vcore with a negative voltage
( -0.24V approximately).
from 5V to 3.3V
To solve the EMI and system noisde issue
Delete PR260 and PR261
Change PQ55 from IMD2AT to 2N7002DW
Add PR291, PR292, PR293, PR294, PC193 and PD36
Change PQ30 and PQ31 from SI7326DN-T1-E3 to FDMC8878
Change PQ32 from SI7230DN-T1-E3 to FDMC8854
Change PC5 to SE00000GG8L(22U_0603) from SE002223K8L(22U_0806)
Add PR128 (10K_0402) between PWM1 to GND
Add PR133 (10K_0402) Between PWM2 to GND
Change PU25 and PU26 from SA000022Y0L(S IC VT351FCX-ADJ CSP 25P)
to SA00002GE0L (S IC VT351AFCX-ADJ CSP 25P
1.Boost resister.
a.CPU Vocre
Change PR87 and PR98 from 0ohm_0603 to 2.2ohm_0603
2 Snubber
a.CPU Vcore
Change PC99 and PC110 from 1500PF_0603 to 1000PF_0603
Stuff PR266 (4.7ohm_1206), PR267(4.7ohm_1206), PC99
and PC110.
b.5V/3.3V/Charger/GPU_Core
Change PC191, PC140, PC190 and PC189 from 1500PF_0603
to 1000PF_0603.
Change PR288, PR265, PR289 and PR290 from 4.7ohm_1206
to 2.2ohm_1206.
Stuff PC189, PC191, PC190, PC140, PR265, PR289,
PR288 and PR290.
C.1.5V/1.05V
Change PC187 and PC188 from 1500PF_0603 to 1000PF_0603.
Change PR286 and PR287 from 4.7ohm_1206 to 1ohm_1206.
Stuff PC187, PC188, PR286 and PR287.
B B
6
42 +3.3V/+5V 4/22
7
45 VCORE 4/22
8
4/8 Change PQ41 and PQ42 from SI4835 to FDS6679Z
Kenny
Compal
Kenny
Compal
LES
DELL
Current Derating issue48 Selector
Material PSL issue
PWM circuitry DH/DL still switch a few cycles in all
3 phase after power off resulted in a voltage pulse
Change PL6 and PL7 from SSC-1350F3-2R8 (TMP) to HMP1350-2R8
(Delta)
Change PR128 and PR138 from 10K_0402 to 33K_0402
observed at output Vcore with a negative voltage
( -0.24V approximately).
46 Charger M09 NB_AC_IN design change for sequence issue
9
10
46
Charger
6/2
6/2
AJ
Compal
AJ
Compal
Change UL setting from 65W to 90W
Change PC185 from 1000p to 100p.
Change PR175 from 100K to 24K
Change PR166 from 57.6K to 51.1K
Cgange PR171 from 13K to 17.8K
Change PR172 from 105 to 348
Pop Pr169
41 DC_IN 6/3
11
A A
46 Charger 6/20
12
5
AJ
Compal
AJ
Compal
SLICE_BAT_PRES# glitch issue
Follow the common design
4
Add PC38 (1500n) between PQ47 to GND
Change PR354 from 10K to 100K
De-POP PR355
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
Solution Description Rev.Page#1Title
X02
X02
X03
X03
X03
X03
X03
X03
X03
X05
X05
X05
X05
DELL CONFIDENTIAL/PROPRIETARY
Title
Size Document Number Rev
2
Date: Sheet
Compal Electronics, Inc.
Changed-List History
LA-4151P
56 57Fr id ay, July 04, 2008
1
1.0
of
Request
5
4
Version Change List ( P. I. R. List )
3
2
1
Item Issue DescriptionDate
D D
43 6/20 Henry
Owner
Change PR65 pull high voltage from +3.3V_SUS to +3.3V_ALW +1.5V/1.05V Change PR65 pull high voltage from +3.3V_SUS to +3.3V_ALW
Compal
2
3
4
47
+Vgfx_Core
45 +Vcore 6/20
42/45/46
EMI ISN 6/25
6/20 Kenny
Compal
Kenny
Compal
EMI
Compal
Load lide 6.9mohm to follow HW North Bridge setting
Change PR239 from 49.9K to 69.8K
on performance mode
Modify the CPU power monitor error on thermal control panel Change PR139 from 22.1K to 14.3K
EMI ISN issue Add PL15(FBMJ4516HS720NT) and PC222(470P_0402)
Change PR155 from 0 ohm to 4.7 ohm.
Change PR37 from 1ohm to 4.7 ohm.
POP PL12 and de-POP PJP32
C C
46
5
Charger
7/4
Merle
Dell
Because the the average current is not over 3A(65W adapter).Depop UL circuit, pop PR170
Solution Description Rev.Page#1Title
X05
X05
X05
X05
X05
Request
B B
A A
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
Changed-List History
LA-4151P
57 57Fr id ay, July 04, 2008
1
1.0
of
Loading...