COMPAL LA-4131P Schematics

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1 1

B

C

D

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Compal Confidential

Schematic Document

Crestline + ICH8M

2008 / 02 / 18

3 3

Rev:0.3

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2007/12/28 2007/12/28

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

D

Date: Sheet

Compal Electronics, Inc.

Cover Sheet

LA-4131P

E

153Monday, February 18, 2008

0.2

of

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B

C

D

E

Compal Confidential

Project Code: ANRJAL6000 (JAL60)
File Name : LA-4131P

ZZZ1

1 1

PCB

CRT

P15

LVDS Panel Interface

P15

nVidia

GDDR3 x 4

2 2

NB8P-SE

CardBus Controller

O2 OZ129

P25

Media Card

PCIE4 PCIE3PCIE5

10/100/1000 LAN

REALTEK
RTL8111C-GR

3 3

P22

Mini Card-1
(WLAN)

1394

Mini Card-2

P27 P27

(Robson)

RJ45 CONN

P22

JAL60 UMA / Discrete

Thermal Sensor
ADM1032ARMZ

P4

Fan conn

PCI-E x16

P34 ~ 38P39 , 40

PCI

Express Card

P26

PCI-E x1

P4

Intel Crestline MCH

DMI x4

PCIE2

Mobile Merom

uFCPGA-478 CPU

H_A#(3..35)
H_D#(0..63)

FCBGA 1299

P7, 8, 9, 10, 11, 12

Intel ICH8M

mBGA-676

P17, 18, 19, 20

LPC BUS

P4, 5, 6

FSB

667/800MHz 1.05V

C-Link

USB2.0

Azalia

SATA0
SATA1
PATA

Option

TPM1.2

DDR2 667MHz 1.8V

Dual Channel

P28

CK505

TSSOP-64

Clock Generator
ICS 9LPRS365

P16

DDR2-SO-DIMM X2

BANK 0, 1, 2, 3

USB0

P13, 14

Finger Printer

USB1

Blue Tooth

USB2,3

JUSBP5 Conn.

USB4

JUSBP1 Conn.

USB5

USB Hub

USB6

JUSBP4 Conn.

USB7

Express Card

USB8

JUSBP3 Conn.

USB9

JUSBP2 Conn.

P31

P31

P30

P30

P31

P30

P26

P30

P30

Camera

Felica

P31

P31

Audio CKT
ALC268

P23

AMP & Audio Jack

P24

ENE KB926

P28

Power On/Off CKT.

P29

4 4

DC/DC Interface CKT.

Power Circuit DC/DC

P41~48

A

RTC CKT.

P18P32

Power OK CKT.

P29

B

Touch Pad Conn Int.KBD

P29 P29

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

BIOS (System/EC)

2007/12/28 2007/12/28

C

P28

Compal Secret Data

Deciphered Date

D

SATA HDD1 Conn.

SATA HDD2 Conn.

ODD Conn.

Custom

Date: Sheet

P21

P21

P21

Title

Block Diagram

Size Document Number Rev

LA-4131P

Compal Electronics, Inc.

of

253Monday, February 18, 2008

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0.2

A

Voltage Rails

1 1

2 2

State

S0

S3

S5 S4/AC

S5 S4/ Battery only

S5 S4/AC & Battery
don't exist

O MEANS ON X MEANS OFF

Power
plane

+B

O

O
O
O

X

+5VALW
+3VALW

+1.8V

O

O
O

X

O

XX
X

XXX

+5VS
+3VS
+1.8VS
+1.5VS
+1.25VS
+1.2VS
+0.9VS
+CPU_CORE
+VGA_CORE
+VCCP

OO

X

X

B

CLOCK

C

STATE

Full ON

S1(Power On Suspend)

S3 (Suspend to RAM)

S4 (Suspend to Disk)

S5 (Soft OFF)

SIGNAL

SLP_S1# SLP_S3#

HIGH HIGH HIGH HIGH

LOW

LOW

LOW LOW LOW LOW

SLP_S4# SLP_S5# +VALW +V +VS Clock

HIGH

LOW

LOWLOWLOW

HIGHHIGHHIGH

HIGH

HIGH

D

ON

ON

ON

OFF

OFF

ON ON

ON

OFF

OFF

OFF

LOW

OFF

OFF

OFF

ON

ON

ON

ON

ON

E

Board ID Table for AD channel

O

O
O

X
X

Vcc 3.3V +/- 5%

Board ID

0
1
2
3
4
5
6

100K +/- 5%Ra / Rc

Rb / Rd V min

0

8.2K +/- 5%
18K +/- 5%
33K +/- 5%
56K +/- 5%
100K +/- 5%
200K +/- 5%

7 NC

AD_BID

0 V

V typ

AD_BID

0 V 0 V

V

AD_BID

max

0.216 V 0.250 V 0.289 V

0.436 V

0.712 V

1.036 V

0.503 V

0.819 V

0.538 V

0.875 V

1.185 V 1.264 V

1.453 V 1.650 V 1.759 V

1.935 V

2.500 V

2.200 V

3.300 V

2.341 V

3.300 V

O MEANS ON

X MEANS OFF

S3 : STR
S4 : STD
S5 : SOFT OFF

External PCI Devices

Device IDSEL# REQ#/GNT# Interrupts

CardBus

AD21

0

PIRQG

BOARD ID Table

Board ID

0
1
2
3
4
5

PCB Revision

0.1

BTO Item BOM Structure

BTO Option Table

6
7

3 3

EC SM Bus1 address

Device

Smart Battery
EEPROM(24C16/02)

(24C04)

Address Address

1010 000X b?
1011 000Xb?

EC SM Bus2 address

Device

EMC1402-1-ACZL-TR_MSOP8

4C0001 011X b?

for CPU Thermal Sensor

ICH8 SM Bus address

Device

Clock Generator
(ICS ICS9LPR365)

DDRII DIMM1
DDRII DIMM2

4 4

Address

1101 001Xb?

1001 000Xb?
1001 010Xb?

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2007/12/28 2007/12/28

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

D

Date: Sheet

Compal Electronics, Inc.

Notes

LA-4131P

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1

XDP Reserve

H_A#[3..16]7

H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10

H_ADSTB#0
H_REQ#0

H_REQ#1
H_REQ#2

H_REQ#4

R70
56_0402_5%

@

C

H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16

H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35
H_ADSTB#1

H_A20M#
H_FERR#
H_IGNNE#

H_STPCLK#
H_INTR
H_NMI
H_SMI#

OCP# 19

D D

H_ADSTB#07

H_REQ#07
H_REQ#17
H_REQ#27
H_REQ#37
H_REQ#47
H_A#[17..35]7

C C

B B

H_ADSTB#17
H_A20M#18

H_FERR#18
H_IGNNE#18

H_STPCLK#18
H_INTR18
H_NMI18
H_SMI#18

+VCCP

12

B

2

H_PROCHOT# OCP#

E

3 1

Q10
MMBT3904_SOT23

@

Thermal Sensor ADM1032ARMZ

+3VS

1

C113

0.1U_0402_10V6K

A A

2200P_0402_50V7K

+3VS

C123

1 2

R69

1 2

10K_0402_5%

5

2

H_THERMDA
H_THERMDC

THERM#

JP1A

J4

ADDR GROUP 0 ADDR GROUP 1

A[3]#

L5

A[4]#

L4

A[5]#

K5

A[6]#

M3

A[7]#

N2

A[8]#

J1

A[9]#

N3

A[10]#

P5

A[11]#

P2

A[12]#

L2

A[13]#

P4

A[14]#

P1

A[15]#

R1

A[16]#

M1

ADSTB[0]#

K3

REQ[0]#

H2

REQ[1]#

K2

REQ[2]#

J3

REQ[3]#

L1

REQ[4]#

Y2

A[17]#

U5

A[18]#

R3

A[19]#

W6

A[20]#

U4

A[21]#

Y5

A[22]#

U1

A[23]#

R4

A[24]#

T5

A[25]#

T3

A[26]#

W2

A[27]#

W5

A[28]#

Y4

A[29]#
A[30]#
A[31]#
A[32]#
A[33]#
A[34]#
A[35]#
ADSTB[1]#

A20M#
FERR#
IGNNE#

STPCLK#
LINT0
LINT1
SMI#

RSVD[01]
RSVD[02]
RSVD[03]
RSVD[04]
RSVD[05]
RSVD[06]
RSVD[07]
RSVD[08]
RSVD[09]
RSVD[10]

ALERT#

ICH

SCLK

SDATA

XDP/ITP SIGNALS

THERMAL

PROCHOT#

THERMDA
THERMDC

THERMTRIP#

H CLK

RESERVED

EC_SMB_CK228,29,34
EC_SMB_DA228,29,34

U2
V4

W3
AA4
AB2
AA3

V1
A6

A5
C4

D5
C6
B4
A3

M4

N5
T2
V3
B2
C3
D2

D22

D3
F6

Merom Ball-out Rev 1a

U2

1

VDD

2

D+

3

D­THERM#4GND

EMC1402-1-ACZL-TR_MSOP8

Address:100_1100 (4C)

ADS#
BNR#
BPRI#

DEFER#

DRDY#
DBSY#

BR0#

IERR#

INIT#

LOCK#

CONTROL

RESET#

RS[0]#
RS[1]#
RS[2]#

TRDY#

HIT#

HITM#

BPM[0]#
BPM[1]#
BPM[2]#
BPM[3]#

PRDY#
PREQ#

TCK

TDI
TDO
TMS

TRST#

DBR#

BCLK[0]
BCLK[1]

CONN@

EC_SMB_CK2

8

EC_SMB_DA2

7

THERM_SCI#

6
5

H_ADS#H_A#3

H1

H_BNR#

E2

H_BPRI#

G5

H_DEFER#

H5

H_DRDY#

F21

H_DBSY#

E1

H_BR0#

F1

H_IERR#

D20

H_INIT#

B3

H_LOCK#

H4

H_RESET#

C1

H_RS#0

F3

H_RS#1

F4

H_RS#2

G3

H_TRDY#H_REQ#3

G2

H_HIT#

G6

H_HITM#

E4
AD4

AD3
AD1
AC4
AC2
AC1

XDP_TCK

AC5

XDP_TDI

AA6
AB3

XDP_TMS

AB5

XDP_TRST#

AB6

XDP_DBRESET#

C20

H_PROCHOT#

D21

H_THERMDA

A24

H_THERMDC

B25

H_THERMTRIP#

C7

CLK_CPU_BCLK

A22

CLK_CPU_BCLK#

A21

H_THERMDA, H_THERMDC routing together,
Trace width / Spacing = 10 / 10 mil

H_THRMTRIP# should connect
to ICH8 and GMCH without
T-ing (No stub)

12

R64
10K_0402_5%

@

12

R65
0_0402_5%

@

EC_SMB_CK2
EC_SMB_DA2

4

H_ADS# 7
H_BNR# 7
H_BPRI# 7

H_DEFER# 7
H_DRDY# 7
H_DBSY# 7

H_BR0# 7

H_INIT# 18
H_LOCK# 7
H_RESET# 7

H_RS#0 7
H_RS#1 7
H_RS#2 7
H_TRDY# 7

H_HIT# 7
H_HITM# 7

XDP_DBRESET# 19

1 2

R79 56_0402_1%

H_THERMTRIP# 7,18

CLK_CPU_BCLK 16
CLK_CPU_BCLK# 16

EC_THERM# 19,28

R78

56_0402_5%

Add on 1003

12

+VCCP

PROCHOT# is not used ---> 56 ohms pull-up
CRB uses 1K ohms pull-up resistor to fix

+VCCP

PROCHOT# failure when driven by a thermal sensor.

Fan Control and Tachometer

EN_DFAN128

FAN_SPEED128

0.01U_0402_16V7K

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2007/12/28 2007/12/28

Compal Secret Data

Deciphered Date

+VCCP

XDP_TDI
XDP_TMS

XDP_TRST#
XDP_TCK

C75

10U_1206_16V4Z~N

C77

1000P_0402_50V7K~N

EN_DFAN1

+3VS

12

R381

10K_0402_5%

2

C529

1

2

FAN1_POWER

Title

Merom(1/3)_AGTL+ / XDP

Size Document Number Rev

Custom

LA-4131P

Date: Sheet

R442 150_0402_1%

1 2

R446 39_0402_1%

1 2

R443 560_0402_5%

1 2

R447 27_0402_1%

1 2

12

+5VS

12

40mil

1 2

C88 10U_1206_16V4Z~N
U1

1

VEN

2
3
4

1
2
3

4
5

ACES_85205-03001

CONN@

GND

VIN

GND
GND

VO

GND

VSET

APL5605KI-TRL SOP 8P

JFAN1

1
2
3

GND
GND

Compal Electronics, Inc.

1

8
7
6
5

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453Monday, February 18, 2008

5

4

3

2

1

H_D#[0..15]7

D D

H_DSTBN#07
H_DSTBP#07
H_DINV#07
H_D#[16..31]7

C C

H_DSTBN#17
H_DSTBP#17
H_DINV#17

R80 1K_0402_5%@

1 2

R77 1K_0402_5%@

1 2

CPU_BSEL016
CPU_BSEL116
CPU_BSEL216

T2
T4
T47
T3

H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_DSTBN#0
H_DSTBP#0
H_DINV#0

H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_DSTBN#1
H_DSTBP#1
H_DINV#1 H_DINV#3

V_CPU_GTLREF

TEST1
TEST2
TEST3
TEST4
TEST5
TEST6

CPU_BSEL0
CPU_BSEL1
CPU_BSEL2

JP1B

E22

D[0]#

F24

D[1]#

E26

D[2]#

G22

D[3]#

F23

D[4]#

G25

D[5]#

E25

D[6]#

E23

D[7]#

K24

D[8]#

G24

D[9]#

J24

D[10]#

J23

D[11]#

H22

D[12]#

F26

D[13]#

K22

D[14]#

H23

D[15]#

J26

DSTBN[0]#

H26

DSTBP[0]#

H25

DINV[0]#

N22

D[16]#

K25

D[17]#

P26

D[18]#

R23

D[19]#

L23

D[20]#

M24

D[21]#

L22

D[22]#

M23

D[23]#

P25

D[24]#

P23

D[25]#

P22

D[26]#

T24

D[27]#

R24

D[28]#

L25

D[29]#

T25

D[30]#

N25

D[31]#

L26

DSTBN[1]#

M26

DSTBP[1]#

N24

DINV[1]#

AD26

GTLREF

C23

TEST1

D25

TEST2

C24

TEST3

AF26

TEST4

AF1

TEST5

A26

TEST6

B22

BSEL[0]

B23

BSEL[1]

C21

BSEL[2]

Merom Ball-out Rev 1a

CONN@

DATA GRP 0

DATA GRP 2DATA GRP 3

DSTBN[2]#
DSTBP[2]#

DINV[2]#

DATA GRP 1

DSTBN[3]#
DSTBP[3]#

DINV[3]#
COMP[0]

MISC

COMP[1]
COMP[2]
COMP[3]

DPRSTP#

PWRGOOD

D[32]#
D[33]#
D[34]#
D[35]#
D[36]#
D[37]#
D[38]#
D[39]#
D[40]#
D[41]#
D[42]#
D[43]#
D[44]#
D[45]#
D[46]#
D[47]#

D[48]#
D[49]#
D[50]#
D[51]#
D[52]#
D[53]#
D[54]#
D[55]#
D[56]#
D[57]#
D[58]#
D[59]#
D[60]#
D[61]#
D[62]#
D[63]#

DPSLP#

DPWR#

SLP#

PSI#

Y22
AB24
V24
V26
V23
T22
U25
U23
Y25
W22
Y23
W24
W25
AA23
AA24
AB25
Y26
AA26
U22

AE24
AD24
AA21
AB22
AB21
AC26
AD20
AE22
AF23
AC25
AE21
AD21
AC22
AD23
AF22
AC23
AE25
AF24
AC20

R26
U26
AA1
Y1

E5
B5
D24
D6
D7
AE6

H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_DSTBN#2
H_DSTBP#2
H_DINV#2

H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
H_DSTBN#3
H_DSTBP#3

COMP0
COMP1
COMP2
COMP3

H_DPRSTP#
H_DPSLP#
H_DPWR#
H_PWRGOOD
H_CPUSLP#
H_PSI#

layout note: Route TEST3 & TEST5 traces on ground referenced layer to the TPs

CPU_BSEL CPU_BSEL2 CPU_BSEL1

166

B B

200

01

0

1

CPU_BSEL0

1

0

H_D#[32..47] 7

H_DSTBN#2 7
H_DSTBP#2 7
H_DINV#2 7
H_D#[48..63] 7

H_DSTBN#3 7
H_DSTBP#3 7
H_DINV#3 7

H_DPRSTP# 7,18,48
H_DPSLP# 18

H_DPWR# 7

H_PWRGOOD 18
H_CPUSLP# 7

H_PSI# 48

12

R445

27.4_0402_1%

12

R75

54.9_0402_1%

12

R76

27.4_0402_1%

12

R444

54.9_0402_1%

Resistor placed within

0.5" of CPU pin.Trace
should be at least 25
mils away from any other
toggling signal.
COMP[0,2] trace width is
18 mils. COMP[1,3] trace
width is 4 mils.

+CPU_CORE +CPU_CORE

JP1C

A7

VCC[001]

A9

VCC[002]

A10

VCC[003]

A12

VCC[004]

A13

VCC[005]

A15

VCC[006]

A17

VCC[007]

A18

VCC[008]

A20

VCC[009]

B7

VCC[010]

B9

VCC[011]

B10

VCC[012]

B12

VCC[013]

B14

VCC[014]

B15

VCC[015]

B17

VCC[016]

B18

VCC[017]

B20

VCC[018]

C9

VCC[019]

C10

VCC[020]

C12

VCC[021]

C13

VCC[022]

C15

VCC[023]

C17

VCC[024]

C18

VCC[025]

D9

VCC[026]

D10

VCC[027]

D12

VCC[028]

D14

VCC[029]

D15

VCC[030]

D17

VCC[031]

D18

VCC[032]

E7

VCC[033]

E9

VCC[034]

E10

VCC[035]

E12

VCC[036]

E13

VCC[037]

E15

VCC[038]

E17

VCC[039]

E18

VCC[040]

E20

VCC[041]

F7

VCC[042]

F9

VCC[043]

F10

VCC[044]

F12

VCC[045]

F14

VCC[046]

F15

VCC[047]

F17

VCC[048]

F18

VCC[049]

F20

VCC[050]

AA7

VCC[051]

AA9

VCC[052]

AA10

VCC[053]

AA12

VCC[054]

AA13

VCC[055]

AA15

VCC[056]

AA17

VCC[057]

AA18

VCC[058]

AA20

VCC[059]

AB9

VCC[060]

AC10

VCC[061]

AB10

VCC[062]

AB12

VCC[063]

AB14

VCC[064]

AB15

VCC[065]

AB17

VCC[066]

AB18

VCC[067]

Merom Ball-out Rev 1a

CONN@

VCC[068]
VCC[069]
VCC[070]
VCC[071]
VCC[072]
VCC[073]
VCC[074]
VCC[075]
VCC[076]
VCC[077]
VCC[078]
VCC[079]
VCC[080]
VCC[081]
VCC[082]
VCC[083]
VCC[084]
VCC[085]
VCC[086]
VCC[087]
VCC[088]
VCC[089]
VCC[090]
VCC[091]
VCC[092]
VCC[093]
VCC[094]
VCC[095]
VCC[096]
VCC[097]
VCC[098]
VCC[099]
VCC[100]

VCCP[01]
VCCP[02]
VCCP[03]
VCCP[04]
VCCP[05]
VCCP[06]
VCCP[07]
VCCP[08]
VCCP[09]
VCCP[10]
VCCP[11]
VCCP[12]
VCCP[13]
VCCP[14]
VCCP[15]
VCCP[16]

VCCA[01]
VCCA[02]

VID[0]
VID[1]
VID[2]
VID[3]
VID[4]
VID[5]
VID[6]

VCCSENSE

VSSSENSE

AB20
AB7
AC7
AC9
AC12
AC13
AC15
AC17
AC18
AD7
AD9
AD10
AD12
AD14
AD15
AD17
AD18
AE9
AE10
AE12
AE13
AE15
AE17
AE18
AE20
AF9
AF10
AF12
AF14
AF15
AF17
AF18
AF20

G21
V6
J6
K6
M6
J21
K21
M21
N21
N6
R21
R6
T21
T6
V21
W21

B26
C26

AD6
AF5
AE5
AF4
AE3
AF3
AE2

VCCSENSE

AF7

VSSSENSE

AE7

.

Length match within 25 mils.

+VCCP

1

+

C312
330U_D2_2.5VY_R9M

@

2

CPU_VID0 48
CPU_VID1 48
CPU_VID2 48
CPU_VID3 48
CPU_VID4 48
CPU_VID5 48
CPU_VID6 48

VCCSENSE 48

VSSSENSE 48

C118

1

C121

2

10U_0805_10V4Z~N

+1.5VS

1

2

0.01U_0402_16V7K

Near pin B26

The trace width/space/other is
20/7/25.

+CPU_CORE

R98
100_0402_1%

1 2

R101
100_0402_1%

1 2

VCCSENSE

VSSSENSE

V_CPU_GTLREF

+VCCP

12

R73
1K_0402_1%

12

R74
2K_0402_1%

Close to CPU pin AD26
within 500mils.

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2007/12/28 2007/12/28

Compal Secret Data

Deciphered Date

2

Close to CPU pin
within 500mils.

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

Merom(2/3)_AGTL+ / PWR

LA-4131P

1

of

553Monday, February 18, 2008

0.2

5

High Frequence Decoupling

D D

C C

B B

JP1D

A4

VSS[001]

A8

VSS[002]

A11

VSS[003]

A14

VSS[004]

A16

VSS[005]

A19

VSS[006]

A23

VSS[007]

AF2

VSS[008]

B6

VSS[009]

B8

VSS[010]

B11

VSS[011]

B13

VSS[012]

B16

VSS[013]

B19

VSS[014]

B21

VSS[015]

B24

VSS[016]

C5

VSS[017]

C8

VSS[018]

C11

VSS[019]

C14

VSS[020]

C16

VSS[021]

C19

VSS[022]

C2

VSS[023]

C22

VSS[024]

C25

VSS[025]

D1

VSS[026]

D4

VSS[027]

D8

VSS[028]

D11

VSS[029]

D13

VSS[030]

D16

VSS[031]

D19

VSS[032]

D23

VSS[033]

D26

VSS[034]

E3

VSS[035]

E6

VSS[036]

E8

VSS[037]

E11

VSS[038]

E14

VSS[039]

E16

VSS[040]

E19

VSS[041]

E21

VSS[042]

E24

VSS[043]

F5

VSS[044]

F8

VSS[045]

F11

VSS[046]

F13

VSS[047]

F16

VSS[048]

F19

VSS[049]

F2

VSS[050]

F22

VSS[051]

F25

VSS[052]

G4

VSS[053]

G1

VSS[054]

G23

VSS[055]

G26

VSS[056]

H3

VSS[057]

H6

VSS[058]

H21

VSS[059]

H24

VSS[060]

J2

VSS[061]

J5

VSS[062]

J22

VSS[063]

J25

VSS[064]

K1

VSS[065]

K4

VSS[066]

K23

VSS[067]

K26

VSS[068]

L3

VSS[069]

L6

VSS[070]

L21

VSS[071]

L24

VSS[072]

M2

VSS[073]

M5

VSS[074]

M22

VSS[075]

M25

VSS[076]

N1

VSS[077]

N4

VSS[078]

N23

VSS[079]

N26

VSS[080]
VSS[081]P3VSS[162]

Merom Ball-out Rev 1a

CONN@

VSS[082]
VSS[083]
VSS[084]
VSS[085]
VSS[086]
VSS[087]
VSS[088]
VSS[089]
VSS[090]
VSS[091]
VSS[092]
VSS[093]
VSS[094]
VSS[095]
VSS[096]
VSS[097]
VSS[098]
VSS[099]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
VSS[159]
VSS[160]
VSS[161]

VSS[163]

P6
P21
P24
R2
R5
R22
R25
T1
T4
T23
T26
U3
U6
U21
U24
V2
V5
V22
V25
W1
W4
W23
W26
Y3
Y6
Y21
Y24
AA2
AA5
AA8
AA11
AA14
AA16
AA19
AA22
AA25
AB1
AB4
AB8
AB11
AB13
AB16
AB19
AB23
AB26
AC3
AC6
AC8
AC11
AC14
AC16
AC19
AC21
AC24
AD2
AD5
AD8
AD11
AD13
AD16
AD19
AD22
AD25
AE1
AE4
AE8
AE11
AE14
AE16
AE19
AE23
AE26
A2
AF6
AF8
AF11
AF13
AF16
AF19
AF21
A25
AF25

.

10uF 0805 X5R -> 85 degree.

Place these caps inside
the CPU socket cavity.

( Left side on Top ).

Place these caps inside
the CPU socket cavity.

( Right side on Top side).

Place these caps inside
the CPU socket cavity.

( Left side on Bottom ).

Place these caps inside
the CPU socket cavity.

( Right side on Bottom ).

Place these caps inside
the CPU socket.

( Left side on Top ). ( Right side on Top side).

220U_D2_4VY_R15M

4

+CPU_CORE

1

2

+CPU_CORE

1

2

+CPU_CORE

1

2

+CPU_CORE

1

2

+CPU_CORE

1

C193

+

2

+VCCP

1

+

C109

2

C182
10U_0805_4VAM~D

C238
10U_0805_4VAM~D

C601
10U_0805_4VAM~D

C604
10U_0805_4VAM~D

330U_D2E_2.5VM_R9

1

C219

+

2

1

2

1

C181
10U_0805_4VAM~D

2

1

C237
10U_0805_4VAM~D

2

1

C239
10U_0805_4VAM~D

2

1

C574
10U_0805_4VAM~D

2

330U_D2E_2.5VM_R9

C164

0.1U_0402_10V6K

1

C598
10U_0805_4VAM~D

2

1

C217
10U_0805_4VAM~D

2

1

C572
10U_0805_4VAM~D

2

1

C577
10U_0805_4VAM~D

2

330U_D2E_2.5VM_R9

Place these caps inside

1

C579

the CPU socket.

+

2

1

C260

0.1U_0402_10V6K

2

3

1

2

1

2

1

2

1

2

1

C259

0.1U_0402_10V6K

2

C180
10U_0805_4VAM~D

C208
10U_0805_4VAM~D

C602
10U_0805_4VAM~D

C573
10U_0805_4VAM~D

1

2

1

C185
10U_0805_4VAM~D

2

1

C218
10U_0805_4VAM~D

2

1

C179
10U_0805_4VAM~D

2

1

C575
10U_0805_4VAM~D

2

1

C599
10U_0805_4VAM~D

2

1

C207
10U_0805_4VAM~D

2

1

C576
10U_0805_4VAM~D

2

1

C571
10U_0805_4VAM~D

2

ESR <= 1.5m ohm
Capacitor > 880 uF

C115

0.1U_0402_10V6K

1

C120

0.1U_0402_10V6K

2

2

1

C184
10U_0805_4VAM~D

2

1

C600
10U_0805_4VAM~D

2

1

C165

0.1U_0402_10V6K

2

1

C183
10U_0805_4VAM~D

2

1

C236
10U_0805_4VAM~D

2

Place these inside
socket cavity on L8
(North side
Secondary)

1

C233
10U_0805_4VAM~D

2

1

C234
10U_0805_4VAM~D

2

1

Place these caps inside
the CPU socket.

1

( Left side on Top ).

C235
10U_0805_4VAM~D

2

Place these caps inside
the CPU socket.

1

( Right side on Top ).

C603
10U_0805_4VAM~D

2

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2007/12/28 2007/12/28

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

Compal Electronics, Inc.

Merom(3/3)_GND / Bypass

LA-4131P

1

0.2

of

653Monday, February 18, 2008

5

H_D#[0..63]5

D D

C C

+VCCP

12

12

R93

R92

54.9_0402_1%

54.9_0402_1%

H_RESET#4
H_CPUSLP#5

B B

H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57

H_D#59
H_D#60
H_D#61
H_D#62
H_D#63

H_SWNG
H_RCOMP

H_SCOMP
H_SCOMP#

H_RESET#
H_CPUSLP#

H_VREF

U3A

E2

H_D#_0

G2

H_D#_1

G7

H_D#_2

M6

H_D#_3

H7

H_D#_4

H3

H_D#_5

G4

H_D#_6

F3

H_D#_7

N8

H_D#_8

H2

H_D#_9

M10

H_D#_10

N12

H_D#_11

N9

H_D#_12

H5

H_D#_13

P13

H_D#_14

K9

H_D#_15

M2

H_D#_16

W10

H_D#_17

Y8

H_D#_18

V4

H_D#_19

M3

H_D#_20

J1

H_D#_21

N5

H_D#_22

N3

H_D#_23

W6

H_D#_24

W9

H_D#_25

N2

H_D#_26

Y7

H_D#_27

Y9

H_D#_28

P4

H_D#_29

W3

H_D#_30

N1

H_D#_31

AD12

H_D#_32

AE3

H_D#_33

AD9

H_D#_34

AC9

H_D#_35

AC7

H_D#_36

AC14

H_D#_37

AD11

H_D#_38

AC11

H_D#_39

AB2

H_D#_40

AD7

H_D#_41

AB1

H_D#_42

Y3

H_D#_43

AC6

H_D#_44

AE2

H_D#_45

AC5

H_D#_46

AG3

H_D#_47

AJ9

H_D#_48

AH8

H_D#_49

AJ14

H_D#_50

AE9

H_D#_51

AE11

H_D#_52

AH12

H_D#_53

AJ5

H_D#_54

AH5

H_D#_55

AJ6

H_D#_56

AE7

H_D#_57

AJ7

H_D#_58

AJ2

H_D#_59

AE5

H_D#_60

AJ3

H_D#_61

AH2

H_D#_62

AH13

H_D#_63

B3

H_SWING

C2

H_RCOMP

W1

H_SCOMP

W2

H_SCOMP#

B6

H_CPURST#

E5

H_CPUSLP#

B9

H_AVREF

A9

H_DVREF

CRESTLINE_1p0 UMA@

HOST

H_ADSTB#_0
H_ADSTB#_1

H_BREQ#

H_DEFER#

H_DBSY#

HPLL_CLK

HPLL_CLK#

H_DPWR#

H_DRDY#

H_LOCK#
H_TRDY#

H_DINV#_0
H_DINV#_1
H_DINV#_2
H_DINV#_3

H_DSTBN#_0
H_DSTBN#_1
H_DSTBN#_2
H_DSTBN#_3

H_DSTBP#_0
H_DSTBP#_1
H_DSTBP#_2
H_DSTBP#_3

H_REQ#_0
H_REQ#_1
H_REQ#_2
H_REQ#_3
H_REQ#_4

layout note:
Route H_SCOMP and H_SCOMP# with trace width, spacing and impedance (55 ohm) same as FSB data traces.

Layout Note:
H_RCOMP / H_VREF / H_SWNG

trace width and spacing is 10/20

+VCCP

R441

12

R464
221_0402_1%

12

100_0402_1%

H_SWNGH_VREF

1

C622

2

0.1U_0402_16V4Z~N

+VCCP

12

R450

1K_0402_1%

0.1U_0402_16V4Z~N

12

A A

R440

C620

2K_0402_1%

1

2

12

R424

24.9_0402_1%

H_RCOMP

Near B3 pinwithin 100 mils from NB

5

H_A#_3
H_A#_4
H_A#_5
H_A#_6
H_A#_7
H_A#_8

H_A#_9
H_A#_10
H_A#_11
H_A#_12
H_A#_13
H_A#_14
H_A#_15
H_A#_16
H_A#_17
H_A#_18
H_A#_19
H_A#_20
H_A#_21
H_A#_22
H_A#_23
H_A#_24
H_A#_25
H_A#_26
H_A#_27
H_A#_28
H_A#_29
H_A#_30
H_A#_31
H_A#_32
H_A#_33
H_A#_34
H_A#_35

H_ADS#

H_BNR#

H_BPRI#

H_HIT#
H_HITM#

H_RS#_0
H_RS#_1
H_RS#_2

J13
B11
C11
M11
C15
F16
L13
G17
C14
K16
B13
L16
J17
B14
K19
P15
R17
B16
H20
L19
D17
M17
N16
J19
B18
E19
B17
B15
E17
C18
A19
B19
N19

G12
H17
G20
C8
E8
F12
D6
C10
AM5
AM7
H8
K7
E4
C6
G10
B7

K5
L2
AD13
AE13

M7
K3
AD2
AH11

L7
K2
AC2
AJ10

M14
E13
A11
H13
B12

E12
D7
D8

4

4

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35

H_ADS#
H_ADSTB#0
H_ADSTB#1
H_BNR#
H_BPRI#
H_BR0#
H_DEFER#
H_DBSY#
CLK_MCH_BCLK
CLK_MCH_BCLK#
H_DPWR#
H_DRDY#
H_HIT#
H_HITM#
H_LOCK#
H_TRDY#

H_DINV#0
H_DINV#1
H_DINV#2
H_DINV#3

H_DSTBN#0H_D#58
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3

H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

H_RS#0
H_RS#1
H_RS#2

H_A#[3..35] 4

H_ADS# 4
H_ADSTB#0 4
H_ADSTB#1 4
H_BNR# 4
H_BPRI# 4
H_BR0# 4
H_DEFER# 4
H_DBSY# 4
CLK_MCH_BCLK 16
CLK_MCH_BCLK# 16
H_DPWR# 5
H_DRDY# 4
H_HIT# 4
H_HITM# 4
H_LOCK# 4
H_TRDY# 4

H_DINV#0 5
H_DINV#1 5
H_DINV#2 5
H_DINV#3 5

H_DSTBN#0 5
H_DSTBN#1 5
H_DSTBN#2 5
H_DSTBN#3 5

H_DSTBP#0 5
H_DSTBP#1 5
H_DSTBP#2 5
H_DSTBP#3 5

H_REQ#0 4
H_REQ#1 4
H_REQ#2 4
H_REQ#3 4
H_REQ#4 4

H_RS#0 4
H_RS#1 4
H_RS#2 4

PM_PWROK19,28

PLT_RST#17,19,21,22,26,27,28,31,34

3

+1.8V

2

2

12

C543

C544

1

0.01U_0402_25V7K~D

1

2

0.01U_0402_25V7K~D

MCH_CLKSEL016
MCH_CLKSEL116
MCH_CLKSEL216

12

3

R399
1K_0402_1%

12

R397

3.01K_0402_1%

NA lead free

12

R400
1K_0402_1%

DDR_A_MA1413
DDR_B_MA1414

R111

10K_0402_5%

R39

10K_0402_5%

CFG129
CFG139

CFG169

PM_BMBUSY#19

H_DPRSTP#5,18,48
PM_EXTTS#013
PM_EXTTS#114

R108 0_0402_5%

DPRSLPVR19,48

PM_POK_R

+3VS

12

12

MCH_CLKSEL0
MCH_CLKSEL1
MCH_CLKSEL2

T14PAD
T15PAD

T7PAD
T12PAD

CFG99

CFG9

T10PAD
T8PAD

CFG12
CFG13

T13PAD
T9PAD

CFG16

T6PAD
T11PAD

PM_BMBUSY#
H_DPRSTP#
PM_EXTTS#0
PM_EXTTS#1
PM_POK_R
PLT_RST#_R
THERMTRIP#

12

DPRSLPVR

2007/12/28 2007/12/28

1

2.2U_0603_106K

SMRCOMP_VOH

SMRCOMP_VOL

C540

1

2

C541

2.2U_0603_106K

PM_EXTTS#0

PM_EXTTS#1

H_THERMTRIP#4,18

R83 0_0402_5%

PLT_RST# PLT_RST#_R

1 2

R85 100_0402_5%

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

U3B

P36

RSVD1

P37

RSVD2

R35

RSVD3

N35

RSVD4

AR12

RSVD5

AR13

RSVD6

AM12

RSVD7

AN13

RSVD8

J12

RSVD9

AR37

RSVD10

AM36

RSVD11

AL36

RSVD12

AM37

RSVD13

D20

RSVD14

H10

RSVD20

B51

RSVD21

BJ20

RSVD22

BK22

RSVD23

BF19

RSVD24

BH20

RSVD25

BK18

RSVD26

BJ18

RSVD27

BF23

RSVD28

BG23

RSVD29

BC23

RSVD30

BD24

RSVD31

BJ29

RSVD32

BE24

RSVD33

BH39

RSVD34

AW20

RSVD35

BK20

RSVD36

C48

RSVD37

D47

RSVD38

B44

RSVD39

C44

RSVD40

A35

RSVD41

B37

RSVD42

B36

RSVD43

B34

RSVD44

C34

RSVD45

P27

CFG_0

N27

CFG_1

N24

CFG_2

C21

CFG_3

C23

CFG_4

F23

CFG_5

N23

CFG_6

G23

CFG_7

J20

CFG_8

C20

CFG_9

R24

CFG_10

L23

CFG_11

J23

CFG_12

E23

CFG_13

E20

CFG_14

K23

CFG_15

M20

CFG_16

M24

CFG_17

L32

CFG_18

N33

CFG_19

L35

CFG_20

G41

PM_BM_BUSY#

L39

PM_DPRSTP#

L36

PM_EXT_TS#_0

J36

PM_EXT_TS#_1

AW49

PWROK

AV20

RSTIN#

N20

THERMTRIP#

G36

DPRSLPVR

BJ51

NC_1

BK51

NC_2

BK50

NC_3

BL50

NC_4

BL49

NC_5

BL3

NC_6

BL2

NC_7

BK1

NC_8

BJ1

NC_9

E1

NC_10

A5

NC_11

C51

NC_12

B50

NC_13

A50

NC_14

A49

NC_15

BK2

NC_16

CRESTLINE_1p0 UMA@

Compal Secret Data

Deciphered Date

2

CFGRSVD

PM

NC

2

AV29

SM_CK_0

BB23

SM_CK_1

BA25

SM_CK_3

AV23

SM_CK_4

AW30

SM_CK#_0

BA23

SM_CK#_1

AW25

SM_CK#_3

AW23

SM_CK#_4

BE29

SM_CKE_0

AY32

SM_CKE_1

BD39

SM_CKE_3

BG37

SM_CKE_4

BG20

SM_CS#_0

BK16

SM_CS#_1

BG16

SM_CS#_2

BE13

SM_CS#_3

BH18

SM_ODT_0

BJ15

SM_ODT_1

BJ14

SM_ODT_2

BE16

SM_ODT_3

BL15

SM_RCOMP

SM_VREF_0
SM_VREF_1

PEG_CLK

PEG_CLK#

DMI_RXN_0
DMI_RXN_1
DMI_RXN_2
DMI_RXN_3

DMI_RXP_0
DMI_RXP_1
DMI_RXP_2
DMI_RXP_3

DMI_TXN_0
DMI_TXN_1
DMI_TXN_2
DMI_TXN_3

DMI_TXP_0
DMI_TXP_1
DMI_TXP_2
DMI_TXP_3

GFX_VID_0
GFX_VID_1
GFX_VID_2
GFX_VID_3

CL_CLK

CL_DATA

CL_PWROK

CL_RST#
CL_VREF

CLK_REQ#

ICH_SYNC#

TEST_1
TEST_2

BK14
BK31

BL31
AR49

AW4

B42
C42
H48
H47

K44
K45

AN47
AJ38
AN42
AN46

AM47
AJ39
AN41
AN45

AJ46
AJ41
AM40
AM44

AJ47
AJ42
AM39
AM43

E35
A39
C38
B39
E36

AM49
AK50
AT43
AN49
AM50

H35
K36
G39
G40

A37
R32

20K_0402_5%

Custom

SM_RCOMP#

SM_RCOMP_VOH
SM_RCOMP_VOL

DDR MUXINGCLK

DPLL_REF_CLK

DPLL_REF_CLK#

DPLL_REF_SSCLK

DPLL_REF_SSCLK#

DMI

GFX_VR_EN

GRAPHICS VID

ME

SDVO_CTRL_CLK

SDVO_CTRL_DATA

MISC

1

For Crestline: 20ohm

M_CLK_DDR0
M_CLK_DDR1
M_CLK_DDR2
M_CLK_DDR3

M_CLK_DDR#0
M_CLK_DDR#1
M_CLK_DDR#2
M_CLK_DDR#3

DDR_CKE0_DIMMA
DDR_CKE1_DIMMA
DDR_CKE2_DIMMB
DDR_CKE3_DIMMB

DDR_CS0_DIMMA#
DDR_CS1_DIMMA#
DDR_CS2_DIMMB#
DDR_CS3_DIMMB#

M_ODT0
M_ODT1
M_ODT2
M_ODT3

SMRCOMP
SMRCOMP#

SMRCOMP_VOH
SMRCOMP_VOL

+DDR_MCH_REF1

1 2

C171 0.1U_0402_16V4Z~N

CLK_MCH_DREFCLK
CLK_MCH_DREFCLK#
MCH_SSCDREFCLK
MCH_SSCDREFCLK#

CLK_MCH_3GPLL

CLK_MCH_3GPLL#

DMI_TXN0
DMI_TXN1
DMI_TXN2
DMI_TXN3

DMI_TXP0
DMI_TXP1
DMI_TXP2
DMI_TXP3

DMI_RXN0
DMI_RXN1
DMI_RXN2
DMI_RXN3

DMI_RXP0
DMI_RXP1
DMI_RXP2
DMI_RXP3

CL_CLK0
CL_DATA0
M_PWROK
CL_RST#
CL_VREF CL_VREF

CLKMCHREQ#
MCH_ICH_SYNC#

12

R96

Title

Crestline(1/6)_AGTL+/DDR2/DMI

Size Document Number Rev

LA-4131P

Date: Sheet

For Calero: 80.6ohm

M_CLK_DDR0 13
M_CLK_DDR1 13
M_CLK_DDR2 14
M_CLK_DDR3 14

M_CLK_DDR#0 13
M_CLK_DDR#1 13
M_CLK_DDR#2 14
M_CLK_DDR#3 14

DDR_CKE0_DIMMA 13
DDR_CKE1_DIMMA 13
DDR_CKE2_DIMMB 14
DDR_CKE3_DIMMB 14

DDR_CS0_DIMMA# 13
DDR_CS1_DIMMA# 13
DDR_CS2_DIMMB# 14
DDR_CS3_DIMMB# 14

M_ODT0 13
M_ODT1 13
M_ODT2 14
M_ODT3 14

R402 20_0402_1%
R403 20_0402_1%

+DDR_MCH_REF1 13,14

SMVREF = 20 uA

CLK_MCH_DREFCLK 16

CLK_MCH_DREFCLK# 16

MCH_SSCDREFCLK 16

MCH_SSCDREFCLK# 16

CLK_MCH_3GPLL 16
CLK_MCH_3GPLL# 16

DMI_TXN0 19
DMI_TXN1 19
DMI_TXN2 19
DMI_TXN3 19

DMI_TXP0 19
DMI_TXP1 19
DMI_TXP2 19
DMI_TXP3 19

DMI_RXN0 19
DMI_RXN1 19
DMI_RXN2 19
DMI_RXN3 19

DMI_RXP0 19
DMI_RXP1 19
DMI_RXP2 19
DMI_RXP3 19

CLK_MCH_DREFCLK
CLK_MCH_DREFCLK#
MCH_SSCDREFCLK
MCH_SSCDREFCLK#

0.1U_0402_16V4Z~N

R149 0_0402_5%VGA@
R145 0_0402_5%VGA@
R122 0_0402_5%VGA@
R114 0_0402_5%VGA@

CL_CLK0 19
CL_DATA0 19

M_PWROK 19
CL_RST# 19

C568

12 mil

CLKMCHREQ# 16
MCH_ICH_SYNC# 19

Layout Note:
+DDR_MCH_REF1
trace width and
spacing is 20/20.

1

2

Compal Electronics, Inc.

1

12
12

+1.25VM_AXD

12

12

753Monday, February 18, 2008

TTRC= 30 mA

+1.8V

12
12
12
12

R410
1K_0402_1%

R409
392_0402_1%

of

0.2

5

D D

DDR_A_D[0..63]13

C C

B B

DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8

DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63

U3D

AR43

SA_DQ_0

AW44

SA_DQ_1

BA45

SA_DQ_2

AY46

SA_DQ_3

AR41

SA_DQ_4

AR45

SA_DQ_5

AT42

SA_DQ_6

AW47

SA_DQ_7

BB45

SA_DQ_8

BF48

SA_DQ_9

BG47

SA_DQ_10

BJ45

SA_DQ_11

BB47

SA_DQ_12

BG50

SA_DQ_13

BH49

SA_DQ_14

BE45

SA_DQ_15

AW43

SA_DQ_16

BE44

SA_DQ_17

BG42

SA_DQ_18

BE40

SA_DQ_19

BF44

SA_DQ_20

BH45

SA_DQ_21

BG40

SA_DQ_22

BF40

SA_DQ_23

AR40

SA_DQ_24

AW40

SA_DQ_25

AT39

SA_DQ_26

AW36

SA_DQ_27

AW41

SA_DQ_28

AY41

SA_DQ_29

AV38

SA_DQ_30

AT38

SA_DQ_31

AV13

SA_DQ_32

AT13

SA_DQ_33

AW11

SA_DQ_34

AV11

SA_DQ_35

AU15

SA_DQ_36

AT11

SA_DQ_37

BA13

SA_DQ_38

BA11

SA_DQ_39

BE10

SA_DQ_40

BD10

SA_DQ_41

BD8

SA_DQ_42

AY9

SA_DQ_43

BG10

SA_DQ_44

AW9

SA_DQ_45

BD7

SA_DQ_46

BB9

SA_DQ_47

BB5

SA_DQ_48

AY7

SA_DQ_49

AT5

SA_DQ_50

AT7

SA_DQ_51

AY6

SA_DQ_52

BB7

SA_DQ_53

AR5

SA_DQ_54

AR8

SA_DQ_55

AR9

SA_DQ_56

AN3

SA_DQ_57

AM8

SA_DQ_58

AN10

SA_DQ_59

AT9

SA_DQ_60

AN9

SA_DQ_61

AM9

SA_DQ_62

AN11

SA_DQ_63

CRESTLINE_1p0 UMA@

DDR SYSTEM MEMORY A

SA_BS_0
SA_BS_1
SA_BS_2

SA_CAS#

SA_DM_0
SA_DM_1
SA_DM_2
SA_DM_3
SA_DM_4
SA_DM_5
SA_DM_6
SA_DM_7

SA_DQS_0
SA_DQS_1
SA_DQS_2
SA_DQS_3
SA_DQS_4
SA_DQS_5
SA_DQS_6

SA_DQS_7
SA_DQS#_0
SA_DQS#_1
SA_DQS#_2
SA_DQS#_3
SA_DQS#_4
SA_DQS#_5
SA_DQS#_6
SA_DQS#_7

SA_MA_0
SA_MA_1
SA_MA_2
SA_MA_3
SA_MA_4
SA_MA_5
SA_MA_6
SA_MA_7
SA_MA_8

SA_MA_9
SA_MA_10
SA_MA_11
SA_MA_12
SA_MA_13

SA_RAS#

SA_RCVEN#

SA_WE#

4

DDR_A_BS#0

BB19
BK19
BF29

BL17
AT45

BD44
BD42
AW38
AW13
BG8
AY5
AN6

AT46
BE48
BB43
BC37
BB16
BH6
BB2
AP3
AT47
BD47
BC41
BA37
BA16
BH7
BC1
AP2

BJ19
BD20
BK27
BH28
BL24
BK28
BJ27
BJ25
BL28
BA28
BC19
BE28
BG30
BJ16

BE18
AY20

BA19

DDR_A_BS#1
DDR_A_BS#2

DDR_A_CAS#
DDR_A_DM0

DDR_A_DM1
DDR_A_DM2
DDR_A_DM3
DDR_A_DM4
DDR_A_DM5
DDR_A_DM6
DDR_A_DM7

DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2

DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7
DDR_A_DQS#0
DDR_A_DQS#1
DDR_A_DQS#2
DDR_A_DQS#3
DDR_A_DQS#4
DDR_A_DQS#5
DDR_A_DQS#6
DDR_A_DQS#7

DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13

DDR_A_RAS#

DDR_A_WE#

DDR_A_BS#0 13
DDR_A_BS#1 13
DDR_A_BS#2 13

DDR_A_CAS# 13 DDR_B_CAS# 14
DDR_A_DM[0..7] 13

DDR_A_DQS[0..7] 13

DDR_A_DQS#[0..7] 13

DDR_A_MA[0..13] 13

DDR_A_RAS# 13

DDR_A_WE# 13

3

DDR_B_D[0..63]14

DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8

DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18DDR_A_DQS3
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41

DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63

AP49

AR51
AW50
AW51

AN51

AN50

AV50

AV49

BA50

BB50

BA49

BE50

BA51

AY49

BF50

BF49

BJ50
BJ44
BJ43

BL43
BK47
BK49
BK43
BK42

BJ41

BL41

BJ37

BJ36
BK41

BJ40

BL35
BK37
BK13
BE11
BK11
BC11
BC13
BE12
BC12
BG12

BJ10

BK10

BG1

BL9
BK5
BL5
BK9

BJ8
BJ6
BF4
BH5

BC2
BK3
BE4
BD3
BJ2
BA3
BB3
AR1
AT3
AY2
AY3
AU2
AT2

2

U3E

SB_DQ_0
SB_DQ_1
SB_DQ_2
SB_DQ_3
SB_DQ_4
SB_DQ_5
SB_DQ_6
SB_DQ_7
SB_DQ_8
SB_DQ_9
SB_DQ_10
SB_DQ_11
SB_DQ_12
SB_DQ_13
SB_DQ_14
SB_DQ_15
SB_DQ_16
SB_DQ_17
SB_DQ_18
SB_DQ_19
SB_DQ_20
SB_DQ_21
SB_DQ_22
SB_DQ_23
SB_DQ_24
SB_DQ_25
SB_DQ_26
SB_DQ_27
SB_DQ_28
SB_DQ_29
SB_DQ_30
SB_DQ_31
SB_DQ_32
SB_DQ_33
SB_DQ_34
SB_DQ_35
SB_DQ_36
SB_DQ_37
SB_DQ_38
SB_DQ_39
SB_DQ_40
SB_DQ_41
SB_DQ_42
SB_DQ_43
SB_DQ_44
SB_DQ_45
SB_DQ_46
SB_DQ_47
SB_DQ_48
SB_DQ_49
SB_DQ_50
SB_DQ_51
SB_DQ_52
SB_DQ_53
SB_DQ_54
SB_DQ_55
SB_DQ_56
SB_DQ_57
SB_DQ_58
SB_DQ_59
SB_DQ_60
SB_DQ_61
SB_DQ_62
SB_DQ_63

CRESTLINE_1p0 UMA@

1

DDR_B_BS#0

AY17

SB_BS_0
SB_BS_1
SB_BS_2

SB_CAS#

SB_DM_0
SB_DM_1
SB_DM_2
SB_DM_3
SB_DM_4
SB_DM_5
SB_DM_6
SB_DM_7

SB_DQS_0
SB_DQS_1
SB_DQS_2
SB_DQS_3
SB_DQS_4
SB_DQS_5
SB_DQS_6

SB_DQS_7
SB_DQS#_0
SB_DQS#_1
SB_DQS#_2
SB_DQS#_3
SB_DQS#_4
SB_DQS#_5
SB_DQS#_6
SB_DQS#_7

SB_MA_0
SB_MA_1
SB_MA_2
SB_MA_3
SB_MA_4
SB_MA_5
SB_MA_6
SB_MA_7
SB_MA_8

SB_MA_9
SB_MA_10
SB_MA_11
SB_MA_12
SB_MA_13

SB_RAS#

SB_RCVEN#

SB_WE#

DDR SYSTEM MEMORY B

BG18
BG36

BE17
AR50

BD49
BK45
BL39
BH12
BJ7
BF3
AW2

AT50
BD50
BK46
BK39
BJ12
BL7
BE2
AV2
AU50
BC50
BL45
BK38
BK12
BK7
BF2
AV3

BC18
BG28
BG25
AW17
BF25
BE25
BA29
BC28
AY28
BD37
BG17
BE37
BA39
BG13

AV16
AY18

BC17

DDR_B_BS#1
DDR_B_BS#2

DDR_B_CAS#
DDR_B_DM0

DDR_B_DM1
DDR_B_DM2
DDR_B_DM3
DDR_B_DM4
DDR_B_DM5
DDR_B_DM6
DDR_B_DM7

DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4
DDR_B_DQS5
DDR_B_DQS6

DDR_B_DQS7
DDR_B_DQS#0
DDR_B_DQS#1
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS#4
DDR_B_DQS#5
DDR_B_DQS#6
DDR_B_DQS#7

DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8

DDR_B_MA9
DDR_B_MA10DDR_B_D42
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13

DDR_B_RAS#

DDR_B_WE#

DDR_B_BS#0 14
DDR_B_BS#1 14
DDR_B_BS#2 14

DDR_B_DM[0..7] 14

DDR_B_DQS[0..7] 14

DDR_B_DQS#[0..7] 14

DDR_B_MA[0..13] 14

DDR_B_RAS# 14

DDR_B_WE# 14

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2007/12/28 2007/12/28

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

Compal Electronics, Inc.

Crestline(2/6)_DDR2 Channel A/B

LA-4131P

1

of

853Monday, February 18, 2008

0.2

5

For Crestline:2.4kohm
For Calero: 1.5Kohm

BIA_PWM15
GMCH_ENBKL28

+3VS

D D

C C

3VDDCCL15
3VDDCDA15

CRT_HSYNC15
CRT_VSYNC15

B B

+3VS

R131

2.2K_0402_5%
R143

2.2K_0402_5%

A A

R124 10K_0402_5%
R120 10K_0402_5%

GMCH_EDID_CLK_LCD15
GMCH_EDID_DAT_LCD15

GMCH_LVDDEN15,28

GMCH_LVDSAC-15
GMCH_LVDSAC+15
GMCH_LVDSBC-15
GMCH_LVDSBC+15

GMCH_LVDSA0-15
GMCH_LVDSA1-15
GMCH_LVDSA2-15

GMCH_LVDSA0+15
GMCH_LVDSA1+15
GMCH_LVDSA2+15

GMCH_LVDSB0-15
GMCH_LVDSB1-15
GMCH_LVDSB2-15

GMCH_LVDSB0+15
GMCH_LVDSB1+15
GMCH_LVDSB2+15

CRT_B15
CRT_G15
CRT_R15

UMA@

GMCH_EDID_CLK_LCD CTRL_CLK

1 2

UMA@

GMCH_EDID_DAT_LCD

1 2

BIA_PWM

GMCH_ENBKL

1 2
1 2

GMCH_EDID_CLK_LCD
GMCH_EDID_DAT_LCD

GMCH_LVDDEN

12

R103 2.4K_0402_1% UMA@

GMCH_LVDSAC-

GMCH_LVDSAC+

GMCH_LVDSBC-

GMCH_LVDSBC+

GMCH_LVDSA0-

GMCH_LVDSA1-

GMCH_LVDSA2-

GMCH_LVDSA0+

GMCH_LVDSA1+

GMCH_LVDSA2+

GMCH_LVDSB0-

GMCH_LVDSB1-

GMCH_LVDSB2-

GMCH_LVDSB0+

GMCH_LVDSB1+

GMCH_LVDSB2+

CRT_B
CRT_G
CRT_R

R127

1 2

150_0402_1%

UMA@

3VDDCCL
3VDDCDA

CRT_HSYNC
CRT_VSYNC

0_0402_5%

R121

VGA@

1 2

1 2

0_0402_5%

R147

VGA@

1 2

UMA@
UMA@

1 2
1 2
1 2

R116

1 2

0_0402_5%
R117

VGA@

VGA@

1 2

CTRL_CLK
CTRL_DATA

R13675_0402_1%UMA@
R13075_0402_1%UMA@
R10775_0402_1%UMA@

R128

1 2

150_0402_1%

150_0402_1%

UMA@

For Crestline:1.3kohm
For Calero: 255ohm

0_0402_5%
R138

UMA@

12

1.3K_0402_1%

R148

UMA@

U3C

J40
H39
E39
E40
C37
D35
K40

L41
L43
N41
N40
D46
C45
D44
E42

G51
E51
F49

G50
E50
F48

G44
B47
B45

E44
A47
A45

E27
G27
K27

F27
J27
L27

M35

P33

H32
G32
K29
J29
F29
E29

K33
G35
F33
C32
E33

CRESTLINE_1p0

UMA@

L_BKLT_CTRL
L_BKLT_EN
L_CTRL_CLK
L_CTRL_DATA
L_DDC_CLK
L_DDC_DATA
L_VDD_EN

LVDS_IBG
LVDS_VBG
LVDS_VREFH
LVDS_VREFL
LVDSA_CLK#
LVDSA_CLK
LVDSB_CLK#
LVDSB_CLK

LVDSA_DATA#_0
LVDSA_DATA#_1
LVDSA_DATA#_2

LVDSA_DATA_0
LVDSA_DATA_1
LVDSA_DATA_2

LVDSB_DATA#_0
LVDSB_DATA#_1
LVDSB_DATA#_2

LVDSB_DATA_0
LVDSB_DATA_1
LVDSB_DATA_2

TVA_DAC
TVB_DAC
TVC_DAC

TVA_RTN
TVB_RTN
TVC_RTN

TV_DCONSEL_0
TV_DCONSEL_1

CRT_BLUE
CRT_BLUE#
CRT_GREEN
CRT_GREEN#
CRT_RED
CRT_RED#

CRT_DDC_CLK
CRT_DDC_DATA
CRT_HSYNC
CRT_TVO_IREF
CRT_VSYNC

4

CTRL_DATA

0_0402_5%

PEGCOMP

N43

PEG_COMPI

PEG_RX#_0
PEG_RX#_1
PEG_RX#_2
PEG_RX#_3
PEG_RX#_4
PEG_RX#_5
PEG_RX#_6
PEG_RX#_7
PEG_RX#_8
PEG_RX#_9

PEG_RX_0
PEG_RX_1
PEG_RX_2
PEG_RX_3
PEG_RX_4
PEG_RX_5
PEG_RX_6
PEG_RX_7
PEG_RX_8

PEG_RX_9
PEG_RX_10
PEG_RX_11
PEG_RX_12
PEG_RX_13
PEG_RX_14
PEG_RX_15

PEG_TX#_0
PEG_TX#_1
PEG_TX#_2
PEG_TX#_3
PEG_TX#_4
PEG_TX#_5
PEG_TX#_6
PEG_TX#_7
PEG_TX#_8
PEG_TX#_9

PEG_TX_0

PEG_TX_1

PEG_TX_2

PEG_TX_3

PEG_TX_4

PEG_TX_5

PEG_TX_6

PEG_TX_7

PEG_TX_8

PEG_TX_9
PEG_TX_10
PEG_TX_11
PEG_TX_12
PEG_TX_13
PEG_TX_14
PEG_TX_15

M43

PEG_NRX_GTX_N0

J51

PEG_NRX_GTX_N1

L51

PEG_NRX_GTX_N2

N47

PEG_NRX_GTX_N3

T45

PEG_NRX_GTX_N4

T50

PEG_NRX_GTX_N5

U40

PEG_NRX_GTX_N6

Y44

PEG_NRX_GTX_N7

Y40

PEG_NRX_GTX_N8

AB51

PEG_NRX_GTX_N9

W49

PEG_NRX_GTX_N10

AD44

PEG_NRX_GTX_N11

AD40

PEG_NRX_GTX_N12

AG46

PEG_NRX_GTX_N13

AH49

PEG_NRX_GTX_N14

AG45

PEG_NRX_GTX_N15

AG41

PEG_NRX_GTX_P0

J50

PEG_NRX_GTX_P1

L50

PEG_NRX_GTX_P2

M47

PEG_NRX_GTX_P3

U44

PEG_NRX_GTX_P4

T49

PEG_NRX_GTX_P5

T41

PEG_NRX_GTX_P6

W45

PEG_NRX_GTX_P7

W41

PEG_NRX_GTX_P8

AB50

PEG_NRX_GTX_P9

Y48

PEG_NRX_GTX_P10

AC45

PEG_NRX_GTX_P11

AC41

PEG_NRX_GTX_P12

AH47

PEG_NRX_GTX_P13

AG49

PEG_NRX_GTX_P14

AH45

PEG_NRX_GTX_P15

AG42

PEG_TXN0

N45

PEG_TXN1

U39

PEG_TXN2

U47

PEG_TXN3

N51

PEG_TXN4

R50

PEG_TXN5

T42

PEG_TXN6

Y43

PEG_TXN7

W46

PEG_TXN8

W38

PEG_TXN9

AD39

PEG_TXN10

AC46

PEG_TXN11

AC49

PEG_TXN12

AC42

PEG_TXN13

AH39

PEG_TXN14

AE49

PEG_TXN15

AH44

PEG_TXP0

M45

PEG_TXP1

T38

PEG_TXP2

T46

PEG_TXP3

N50

PEG_TXP4

R51

PEG_TXP5

U43

PEG_TXP6

W42

PEG_TXP7

Y47

PEG_TXP8

Y39

PEG_TXP9

AC38

PEG_TXP10

AD47

PEG_TXP11

AC50

PEG_TXP12

AD43

PEG_TXP13

AG39

PEG_TXP14

AE50

PEG_TXP15

AH43

R136

0_0402_5%

VGA@

PEG_COMPO

LVDS

PEG_RX#_10
PEG_RX#_11
PEG_RX#_12
PEG_RX#_13
PEG_RX#_14
PEG_RX#_15

TV VGA

PEG_TX#_10

PCI-EXPRESS GRAPHICS

PEG_TX#_11
PEG_TX#_12
PEG_TX#_13
PEG_TX#_14
PEG_TX#_15

0_0402_5%

R119

VGA@

R112

VGA@

1 2

1 2

3

R104

24.9_0402_1%

1 2

C612 0.1U_0402_16V7KVGA@

1 2

C609 0.1U_0402_16V7KVGA@

1 2

C605 0.1U_0402_16V7KVGA@

1 2

C592 0.1U_0402_16V7KVGA@

1 2

C590 0.1U_0402_16V7KVGA@

1 2

C588 0.1U_0402_16V7KVGA@

1 2

C581 0.1U_0402_16V7KVGA@

1 2

C582 0.1U_0402_16V7KVGA@

1 2

C567 0.1U_0402_16V7KVGA@

1 2

C566 0.1U_0402_16V7KVGA@

1 2

C561 0.1U_0402_16V7KVGA@

1 2

C560 0.1U_0402_16V7KVGA@

1 2

C557 0.1U_0402_16V7KVGA@

1 2

C555 0.1U_0402_16V7KVGA@

1 2

C552 0.1U_0402_16V7KVGA@

1 2

C549 0.1U_0402_16V7KVGA@

1 2

C614 0.1U_0402_16V7KVGA@

1 2

C611 0.1U_0402_16V7KVGA@

1 2

C608 0.1U_0402_16V7KVGA@

1 2

C594 0.1U_0402_16V7KVGA@

1 2

C593 0.1U_0402_16V7KVGA@

1 2

C591 0.1U_0402_16V7KVGA@

1 2

C585 0.1U_0402_16V7KVGA@

1 2

C586 0.1U_0402_16V7KVGA@

1 2

C578 0.1U_0402_16V7KVGA@

1 2

C570 0.1U_0402_16V7KVGA@

1 2

C563 0.1U_0402_16V7KVGA@

1 2

C562 0.1U_0402_16V7KVGA@

1 2

C559 0.1U_0402_16V7KVGA@

1 2

C558 0.1U_0402_16V7KVGA@

1 2

C554 0.1U_0402_16V7KVGA@

1 2

C551 0.1U_0402_16V7KVGA@

1 2

R130

0_0402_5%

VGA@

PEGCOMP trace width

+VCCP

R107

0_0402_5%

VGA@

and spacing is 20/25 mils.

PEG_NRX_GTX_N[0..15] 34

PEG_NRX_GTX_P[0..15] 34

PEG_NTX_GRX_N0
PEG_NTX_GRX_N1
PEG_NTX_GRX_N2
PEG_NTX_GRX_N3
PEG_NTX_GRX_N4
PEG_NTX_GRX_N5
PEG_NTX_GRX_N6
PEG_NTX_GRX_N7
PEG_NTX_GRX_N8

PEG_NTX_GRX_N9
PEG_NTX_GRX_N10
PEG_NTX_GRX_N11
PEG_NTX_GRX_N12
PEG_NTX_GRX_N13
PEG_NTX_GRX_N14
PEG_NTX_GRX_N15

PEG_NTX_GRX_P0

PEG_NTX_GRX_P1

PEG_NTX_GRX_P2

PEG_NTX_GRX_P3

PEG_NTX_GRX_P4

PEG_NTX_GRX_P5

PEG_NTX_GRX_P6

PEG_NTX_GRX_P7

PEG_NTX_GRX_P8

PEG_NTX_GRX_P9

PEG_NTX_GRX_P10
PEG_NTX_GRX_P11
PEG_NTX_GRX_P12
PEG_NTX_GRX_P13
PEG_NTX_GRX_P14
PEG_NTX_GRX_P15

R127

0_0402_5%

VGA@

PEG_NTX_GRX_N[0..15] 34

PEG_NTX_GRX_P[0..15] 34

R116

0_0402_5%

VGA@

2

R128

0_0402_5%

VGA@

Strap Pin Table

CFG[2:0] FSB Freq select

CFG5 (DMI select)

CFG6

CFG7 (CPU Strap)

CFG8 (Low power PCIE)

(PCIE Graphics Lane Reversal)

CFG20 (PCIE/SDVO concurrent)

CFG9

CFG[11:10]

CFG[13:12] (XOR/ALLZ)

CFG16 (FSB Dynamic ODT)

SDVO_CTRLDATA

CFG19 (DMI Lane Reversal)

R148

0_0402_5%

VGA@

1

010 = FSB 800MHz
011 = FSB 667MHz
Others = Reserved

0 = DMI x 2
1 = DMI x 4

*

Reserved

0 = Reserved
1 = Mobile CPU

*

0 = Normal mode
1 = Low Power mode

*

0 = Reverse Lane
1 = Normal Operation

*

Reserved
00 = Reserved

01 = XOR Mode Enabled
10 = All Z Mode Enabled
11 = Normal Operation

(Default)

*

ReservedCFG[15:14]

0 = Disabled
1 = Enabled

*

ReservedCFG[18:17]

0 = No SDVO Device Present
1 = SDVO Device Present

0 = Normal Operation

(Lane number in Order)

*

*

1 = Reverse Lane

0 = Only PCIE or SDVO is operational.
1 = PCIE/SDVO are operating simu.

CFG[17:3] have internal pull up
CFG[19:18] have internal pull down

R135 4.02K_0402_1%@

CFG97

CFG127

CFG137

CFG167

1 2

R118 4.02K_0402_1%@

1 2

R125 4.02K_0402_1%@

1 2

R100 4.02K_0402_1%@

1 2

*

Note: CRT / TV-out should route to JP30 first then to the JP1 & JP2 on system side.

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date

2007/12/28 2007/12/28

3

Compal Secret Data

Deciphered Date

2

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

Crestline(3/6)_LVDS / CRT/ PCIE

LA-4131P

1

of

953Monday, February 18, 2008

0.2

5

+3VS_DAC_CRT

C635

0.1U_0402_16V4Z~N

C632

0.022U_0402_16V7K~N

1

1

2

2

UMA@

UMA@

D D

+3VS_DAC_BG

C C

0.1U_0402_16V4Z~N

C633

0.022U_0402_16V7K~N

1

2

UMA@

+1.25VS

BLM18PG181SN1D_0603

C636

1

2

UMA@

+3VS

R469

10_0603_5%

UMA@

L31

UMA@

C638

4.7U_0805_10V4Z~N

1

2

UMA@

R416

1 2

0_0805_5%

0.1U_0402_16V4Z~N

R87

1 2

0_0805_5%

R84

0_0603_5%

VCCD_CRT = 60 mA
VCCD_TVDAC = 60 mA

+3VS

+3VS

12

+3VS_PEG_BG

C615

+1.25VM_A_SM

150U_Y_6.3VM

+1.25VM_A_SM_CK

12

1U_0402_6.3V4Z

+3VS

VCCA_PEG_BG = 0.4 mA

1

2

VCCA_SM = 735 mA

22U_0805_6.3V4Z

1

C196

C539

1

+

2

2

VCCA_SM_CK = 35 mA

22U_0805_6.3V4Z

@

C142

C159

1

1

2

2

+1.5VS_TVDAC

VCCD_QTVDAC = 0.5 mA

VCCD_HPLL = 250 mA

VCCD_PEG_PLL = 90 mA

VCCD_LVDS = 150 mA

B B

+3VS_TVDACA

0.022U_0402_16V7K~N

1

2

C630

0.1U_0402_16V4Z~N

1

UMA@

2

+3VS

R467

12

0_0603_5%

C627

UMA@

VCCA_TVA_DAC = 40 mA

UMA@

VCCSYNC

R97

12

0_0603_5%

UMA@

+3VS_DAC_CRT

VCC_CRT_DAC = 70 mA

+3VS_DAC_BG

VCCA_DAC_BG = 5 mA

+1.25VS_DPLLA

VCCA_DPLLA = 100 mA

+1.25VS_DPLLB

VCCA_DPLLB = 100 mA

+1.25VM_HPLL

VCCA_HPLL = 50 mA

+1.25VM_MPLL

VCCA_MPLL = 150 mA

+1.8V_TXLVDS

VCCA_LVDS = 10 mA

1000P_0402_50V7K~N

+1.25VS_PEGPLL

VCCA_PEG_PLL = 90 mA

4.7U_0805_6.3V6K

1U_0603_10V4Z

C176

1

2

0.1U_0402_16V4Z~N

1U_0603_10V4Z

@

C162

1

2

VCC_SYNC = 10 mA

1

C250

0.1U_0402_16V4Z~N

UMA@

2

1

C294

UMA@

2

C155

1

2

C149

1

+3VS_TVDACA
+3VS_TVDACB

2

+3VS_TVDACC

R109 0_0402_5% VGA@

R106 0_0402_5% UMA@

+1.5VS_QDAC

+1.25VM_HPLL

+1.25VS_PEGPLL

+1.8V_LVDS

12
12

20 mils

4

U3H

J32

VCCSYNC

A33

VCCA_CRT_DAC_1

B33

VCCA_CRT_DAC_2

A30

VCCA_DAC_BG

B32

VSSA_DAC_BG

B49

VCCA_DPLLA

H49

VCCA_DPLLB

AL2

VCCA_HPLL

AM2

VCCA_MPLL

A41

VCCA_LVDS

B41

VSSA_LVDS

K50

VCCA_PEG_BG

K49

VSSA_PEG_BG

U51

VCCA_PEG_PLL

AW18

VCCA_SM_1

AV19

VCCA_SM_2

AU19

VCCA_SM_3

AU18

VCCA_SM_4

AU17

VCCA_SM_5

AT22

VCCA_SM_7

AT21

VCCA_SM_8

AT19

VCCA_SM_9

AT18

VCCA_SM_10

AT17

VCCA_SM_11

AR17

VCCA_SM_NCTF_1

AR16

VCCA_SM_NCTF_2

BC29

VCCA_SM_CK_1

BB29

VCCA_SM_CK_2

C25

VCCA_TVA_DAC_1

B25

VCCA_TVA_DAC_2

C27

VCCA_TVB_DAC_1

B27

VCCA_TVB_DAC_2

B28

VCCA_TVC_DAC_1

A28

VCCA_TVC_DAC_2

M32

VCCD_CRT

L29

VCCD_TVDAC

N28

VCCD_QDAC

AN2

VCCD_HPLL

U48

VCCD_PEG_PLL

J41

VCCD_LVDS_1

H42

VCCD_LVDS_2

CRESTLINE_1p0 UMA@

CRTPLLA PEGA SMTV

POWER

A CK A LVDS

D TV/CRTLVDS

VTT_10
VTT_11
VTT_12
VTT_13

VTT

VTT_14
VTT_15
VTT_16
VTT_17
VTT_18
VTT_19
VTT_20
VTT_21
VTT_22

VCC_AXD_1

VCC_AXD_2
VCC_AXD_3

VCC_AXD_4

VCC_AXD_5

AXD

VCC_AXD_6

VCC_AXD_NCTF

VCC_AXF_1
VCC_AXF_2
VCC_AXF_3

AXF

VCC_DMI

VCC_SM_CK_1
VCC_SM_CK_2
VCC_SM_CK_3
VCC_SM_CK_4

SM CK

VCC_TX_LVDS

VCC_HV_1
VCC_HV_2

HV

VCC_PEG_1
VCC_PEG_2
VCC_PEG_3
VCC_PEG_4

PEG

VCC_PEG_5

VCC_RXR_DMI_1
VCC_RXR_DMI_2

DMI

VTTLF1
VTTLF2
VTTLF3

VTTLF

U13

VTT_1

U12

VTT_2

U11

VTT_3

U9

VTT_4

U8

VTT_5

U7

VTT_6

U5

VTT_7

U3

VTT_8

U2

VTT_9

U1
T13
T11
T10
T9
T7
T6
T5
T3
T2
R3
R2
R1

AT23
AU28
AU24
AT29
AT25
AT30

AR29

B23
B21
A21

AJ50

BK24
BK23
BJ24
BJ23

A43

C40
B40

VCC_PEG = 1310 mA

AD51
W50
W51
V49
V50

AH50
AH51

VCCR_RX_DMI = 260 mA

A7
F2
AH1

3

+VCCP

VTT = 850 mA

330U_D2_2.5VY_R9M

4.7U_0805_10V4Z~N

1

C313

+

2

0.47U_0603_10V7K

4.7U_0805_10V4Z~N

C197

1

2

+1.25VM_AXD

10U_0805_10V4Z~N

1U_0603_10V4Z

C174

1

2

+V1.25VS_AXF

VCC_AXF = 495 mA

VCC_DMI = 100 mA

+1.25VS_DMI

VCC_SM_CK = 200 mA

+1.8V_SM_CK

VCC_TX_LVDS = 100 mA

+1.8V_TXLVDS

VCC_HV = 100 mA

+VCC_PEG

1

2

0.47U_0603_10V7K

C210

1

2

0.47U_0603_10V7K

C279

0.47U_0603_10V7K

C225

1

2

2.2U_0805_16V4Z

C596

1

2

R88

1 2

0_0805_5%

VCC_AXD = 515 mA

C199

1

2

+3VS_HV

0.1U_0402_16V4Z~N
C288

1

2

20mils

C624

1

2

2

+1.25VS_DPLLA

220U_D2_4VY_R15M

0.1U_0402_16V4Z~N

10U_0805_10V4Z~N

C327

C317

1

1

+

UMA@

2

C595

1

2

+1.25VS

+1.25VS_DPLLB +1.25VS

0.1U_0402_16V4Z~N

C619

1

UMA@

2

0.1U_0402_16V4Z~N

C178

1

2

+1.25VM_MPLL

0.1U_0402_16V4Z~N
C201

1

2

1

UMA@

2

2

L30

UMA@

1 2

22U_0805_6.3VAM

10U_FLC-453232-100K_0.25A_10%

C618

1

UMA@

2

L9

MBK2012121YZF_0805

10U_0805_10V4Z~N

C187

1

2

L10

MBK2012121YZF_0805

10U_0805_10V4Z~N

C204

1

2

+1.25VS

L14

UMA@

1 2

10U_FLC-453232-100K_0.25A_10%

C321

UMA@

+1.25VS+1.25VM_HPLL

12

+1.25VS

12

+VCCP_D

D12

2 1

+VCCP

CH751H-40PT_SOD323-2

+3VS

22U_0805_6.3V4Z

+V1.25VS_AXF

+1.25VS_DMI

+1.8V_SM_CK

C117

1

2

+1.8V_TXLVDS

+VCC_PEG

R140

10_0402_5%

1

10U_0805_10V4Z~N

1U_0603_10V4Z

C628

1

2

1 2

0.1U_0402_16V4Z~N
0_0603_5%

C583

1

2

10U_0805_10V4Z~N

0.1U_0402_16V4Z~N

C542

1

2

40 mils

C309

1000P_0402_50V7K~N

220U_D2_4VY_R15M

1

UMA@

2

10U_0805_10V4Z~N

220U_D2_4VY_R15M

1

C569

+

2

R137

12

0_0402_5%

C623

1

2

R411

C538

1

2

C326

1

+

UMA@

2

C589

1

2

R466

1 2

0_0603_5%

+1.25VS

R393

1 2

0_0805_5%

R153

UMA@

0_0603_5%

R415

0_0805_5%

12

+1.25VS

+1.8V

+1.8V

12

+VCCP

12

+3VS_HV

+3VS_TVDACB

C626

0.022U_0402_16V7K~N

0.1U_0402_16V4Z~N

1

1

UMA@

2

2

A A

+3VS_TVDACC

0.1U_0402_16V4Z~N

C625

0.022U_0402_16V7K~N

1

1

UMA@

2

2

+3VS

R468

12

0_0603_5%

C629

UMA@

VCCA_TVB_DAC = 40 mA

UMA@

+3VS

R465

12

0_0603_5%

C621

UMA@

VCCA_TVC_DAC = 40 mA

UMA@

5

+1.5VS_TVDAC

0.022U_0402_16V7K~N

1

2

+1.5VS_QDAC

1U_0402_6.3V4Z

1

2

+1.5VS

R91

1 2

0_0805_5%

0.1U_0402_16V4Z~N

C251

C240

1

2

R95

100_0603_1%

C249

C232

0.1U_0402_16V4Z~N

UMA@

1

UMA@

UMA@

2

+1.25VS_PEGPLL

0.1U_0402_16V4Z~N

+1.5VS

12

4

1

2

+1.8V_LVDS

10U_0805_10V4Z~N

1

2

C607

C280

UMA@

10U_0805_10V4Z~N

1

2

1U_0603_10V4Z

1

2

+1.25VS

L29

R141

0_0603_5%

UMA@

12

+1.8V

12

BLM18PG121SN1D_0603

C597

C273

UMA@

C633

0_0402_5%

VGA@

C632

0_0402_5%

VGA@

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2007/12/28 2007/12/28

Compal Secret Data

Deciphered Date

C627

0_0402_5%

VGA@

C629

0_0402_5%

VGA@

2

For Discrete BOM

C621

0_0402_5%

VGA@

C232

0_0402_5%

VGA@

C273

0_0603_5%

VGA@

C309

0_0402_5%

VGA@

Title

Crestline(4/6)_PWR

Size Document Number Rev

Custom

LA-4131P

Date: Sheet

C619

0_0402_5%

VGA@

C250

0_0402_5%

VGA@

U3

PM965_C0

VGA@

C317

0_0402_5%

VGA@

Compal Electronics, Inc.

10 53Monday, February 18, 2008

1

0.2

of

5

4

3

2

1

+VCCP

VCC = 1573 mA

1

2

C215

C202

+VCCP

0.1U_0402_16V4Z~N

C188

1

2

10U_0805_10V4Z~N

C200

C205

1

2

0.1U_0402_16V4Z~N
C191

1

2

U3F

AB33

VCC_NCTF_1

AB36

VCC_NCTF_2

AB37

VCC_NCTF_3

AC33

VCC_NCTF_4

AC35

VCC_NCTF_5

AC36

VCC_NCTF_6

AD35

VCC_NCTF_7

AD36

VCC_NCTF_8

AF33

VCC_NCTF_9

AF36

VCC_NCTF_10

AH33

VCC_NCTF_11

AH35

VCC_NCTF_12

AH36

VCC_NCTF_13

AH37

VCC_NCTF_14

AJ33

VCC_NCTF_15

AJ35

VCC_NCTF_16

AK33

VCC_NCTF_17

AK35

VCC_NCTF_18

AK36

VCC_NCTF_19

AK37

VCC_NCTF_20

AD33

VCC_NCTF_21

AJ36

VCC_NCTF_22

AM35

VCC_NCTF_23

AL33

VCC_NCTF_24

AL35

VCC_NCTF_25

AA33

VCC_NCTF_26

AA35

VCC_NCTF_27

AA36

VCC_NCTF_28

AP35

VCC_NCTF_29

AP36

VCC_NCTF_30

AR35

VCC_NCTF_31

AR36

VCC_NCTF_32

Y32

VCC_NCTF_33

Y33

VCC_NCTF_34

Y35

VCC_NCTF_35

Y36

VCC_NCTF_36

Y37

VCC_NCTF_37

T30

VCC_NCTF_38

T34

VCC_NCTF_39

T35

VCC_NCTF_40

U29

VCC_NCTF_41

U31

VCC_NCTF_42

U32

VCC_NCTF_43

U33

VCC_NCTF_44

U35

VCC_NCTF_45

U36

VCC_NCTF_46

V32

VCC_NCTF_47

V33

VCC_NCTF_48

V36

VCC_NCTF_49

V37

VCC_NCTF_50

AL24

VCC_AXM_NCTF_1

AL26

VCC_AXM_NCTF_2

AL28

VCC_AXM_NCTF_3

AM26

VCC_AXM_NCTF_4

AM28

VCC_AXM_NCTF_5

AM29

VCC_AXM_NCTF_6

AM31

VCC_AXM_NCTF_7

AM32

VCC_AXM_NCTF_8

AM33

VCC_AXM_NCTF_9

AP29

VCC_AXM_NCTF_10

AP31

VCC_AXM_NCTF_11

AP32

VCC_AXM_NCTF_12

AP33

VCC_AXM_NCTF_13

AL29

VCC_AXM_NCTF_14

AL31

VCC_AXM_NCTF_15

AL32

VCC_AXM_NCTF_16

AR31

VCC_AXM_NCTF_17

AR32

VCC_AXM_NCTF_18

AR33

VCC_AXM_NCTF_19

CRESTLINE_1p0 UMA@

VSS NCTF

VCC NCTF

POWER

VCC AXM NCTF

VSS_NCTF_1
VSS_NCTF_2
VSS_NCTF_3
VSS_NCTF_4
VSS_NCTF_5
VSS_NCTF_6
VSS_NCTF_7
VSS_NCTF_8

VSS_NCTF_9
VSS_NCTF_10
VSS_NCTF_11
VSS_NCTF_12
VSS_NCTF_13
VSS_NCTF_14
VSS_NCTF_15
VSS_NCTF_16
VSS_NCTF_17
VSS_NCTF_18
VSS_NCTF_19
VSS_NCTF_20
VSS_NCTF_21

VSS_SCB1
VSS_SCB2
VSS_SCB3
VSS_SCB4
VSS_SCB5
VSS_SCB6

VSS SCBVCC AXM

VCC_AXM_1
VCC_AXM_2
VCC_AXM_3
VCC_AXM_4
VCC_AXM_5
VCC_AXM_6
VCC_AXM_7

T27
T37
U24
U28
V31
V35
AA19
AB17
AB35
AD19
AD37
AF17
AF35
AK17
AM17
AM24
AP26
AP28
AR15
AR19
AR28

A3
B2
C1
BL1
BL51
A51

AT33
AT31
AK29
AK24
AK23
AJ26
AJ23

+VCCP

VCC_AXM = 540 mA

1

C211

UMA@

1U_0603_10V4Z

2

330U_D2_2.5VY_R9MUMA@

C324

1

+

2

+1.8V

VCC_SM = 3300 mA

160mil

330U_D2_2.5VY_R9M

22U_0805_6.3V4Z

1

C99

C122

1

+

2

2

VCC_AXG = 7700 mA

10U_0805_10V4Z~NUMA@

1

C252

1

C223

2

2

10U_0805_10V4Z~NUMA@

0.01U_0402_16V7K

22U_0805_6.3V4Z

C129

1

2

+VCCP

0.1U_0402_16V4Z~N

1

C221

2

R94

1 2

0_0603_5%

C143

2

1

UMA@

D D

220U_D2_4VY_R15M

22U_0805_6.3V4Z

1

C325

+

2

C C

B B

0.22U_0402_10V4Z~N

C173

C189

12

12

1

2

0.22U_0402_10V4Z~N

C224

+VCCP

0.22U_0402_10V4Z~N

0.22U_0402_10V4Z~N

C214

12

12

10U_0805_10V4Z~N

0.1U_0402_16V4Z~N

0.1U_0402_16V4Z~N

C172

1

1

2

2

AT35
AT34
AH28
AC32
AC31
AK32

AJ31

AJ28
AH32
AH31
AH29
AF32

AU32
AU33
AU35
AV33

AW33
AW35

AY35
BA32
BA33
BA35
BB33
BC32
BC33
BC35
BD32
BD35
BE32
BE33
BE35
BF33
BF34
BG32
BG33
BG35
BH32
BH34
BH35

BJ32

BJ33

BJ34
BK32
BK33
BK34
BK35

BL33
AU30

W13
W14

AA20
AA23
AA26
AA28
AB21
AB24
AB29
AC20
AC21
AC23
AC24
AC26
AC28
AC29
AD20
AD23
AD24
AD28
AF21
AF26
AA31
AH20
AH21
AH23
AH24
AH26
AD31

AJ20
AN14

R30

R20
T14

Y12

U3G

VCC_1
VCC_2
VCC_3
VCC_5
VCC_4
VCC_6
VCC_7
VCC_8
VCC_9
VCC_10
VCC_11
VCC_12

VCC_13

VCC_SM_1
VCC_SM_2
VCC_SM_3
VCC_SM_4
VCC_SM_5
VCC_SM_6
VCC_SM_7
VCC_SM_8
VCC_SM_9
VCC_SM_10
VCC_SM_11
VCC_SM_12
VCC_SM_13
VCC_SM_14
VCC_SM_15
VCC_SM_16
VCC_SM_17
VCC_SM_18
VCC_SM_19
VCC_SM_20
VCC_SM_21
VCC_SM_22
VCC_SM_23
VCC_SM_24
VCC_SM_25
VCC_SM_26
VCC_SM_27
VCC_SM_28
VCC_SM_29
VCC_SM_30
VCC_SM_31
VCC_SM_32
VCC_SM_33
VCC_SM_34
VCC_SM_35
VCC_SM_36

VCC_AXG_1
VCC_AXG_2
VCC_AXG_3
VCC_AXG_4
VCC_AXG_5
VCC_AXG_6
VCC_AXG_7
VCC_AXG_8
VCC_AXG_9
VCC_AXG_10
VCC_AXG_11
VCC_AXG_12
VCC_AXG_13
VCC_AXG_14
VCC_AXG_15
VCC_AXG_16
VCC_AXG_17
VCC_AXG_18
VCC_AXG_19
VCC_AXG_20
VCC_AXG_21
VCC_AXG_22
VCC_AXG_23
VCC_AXG_24
VCC_AXG_25
VCC_AXG_26
VCC_AXG_27
VCC_AXG_28
VCC_AXG_29
VCC_AXG_30
VCC_AXG_31
VCC_AXG_32
VCC_AXG_33
VCC_AXG_34

VCC CORE

POWER

VCC SMVCC GFX

VCC_AXG_NCTF_1
VCC_AXG_NCTF_2
VCC_AXG_NCTF_3
VCC_AXG_NCTF_4
VCC_AXG_NCTF_5
VCC_AXG_NCTF_6
VCC_AXG_NCTF_7
VCC_AXG_NCTF_8

VCC_AXG_NCTF_9
VCC_AXG_NCTF_10
VCC_AXG_NCTF_11
VCC_AXG_NCTF_12
VCC_AXG_NCTF_13
VCC_AXG_NCTF_14
VCC_AXG_NCTF_15
VCC_AXG_NCTF_16
VCC_AXG_NCTF_17
VCC_AXG_NCTF_18
VCC_AXG_NCTF_19
VCC_AXG_NCTF_20
VCC_AXG_NCTF_21
VCC_AXG_NCTF_22
VCC_AXG_NCTF_23
VCC_AXG_NCTF_24
VCC_AXG_NCTF_25
VCC_AXG_NCTF_26
VCC_AXG_NCTF_27
VCC_AXG_NCTF_28
VCC_AXG_NCTF_29
VCC_AXG_NCTF_30
VCC_AXG_NCTF_31
VCC_AXG_NCTF_32
VCC_AXG_NCTF_33
VCC_AXG_NCTF_34
VCC_AXG_NCTF_35
VCC_AXG_NCTF_36
VCC_AXG_NCTF_37
VCC_AXG_NCTF_38
VCC_AXG_NCTF_39
VCC_AXG_NCTF_40
VCC_AXG_NCTF_41
VCC_AXG_NCTF_42
VCC_AXG_NCTF_43
VCC_AXG_NCTF_44
VCC_AXG_NCTF_45
VCC_AXG_NCTF_46
VCC_AXG_NCTF_47
VCC_AXG_NCTF_48
VCC_AXG_NCTF_49
VCC_AXG_NCTF_50
VCC_AXG_NCTF_51
VCC_AXG_NCTF_52
VCC_AXG_NCTF_53
VCC_AXG_NCTF_54

VCC GFX NCTF

VCC_AXG_NCTF_55
VCC_AXG_NCTF_56
VCC_AXG_NCTF_57
VCC_AXG_NCTF_58
VCC_AXG_NCTF_59
VCC_AXG_NCTF_60
VCC_AXG_NCTF_61
VCC_AXG_NCTF_62
VCC_AXG_NCTF_63
VCC_AXG_NCTF_64
VCC_AXG_NCTF_65
VCC_AXG_NCTF_66
VCC_AXG_NCTF_67
VCC_AXG_NCTF_68
VCC_AXG_NCTF_69
VCC_AXG_NCTF_70
VCC_AXG_NCTF_71
VCC_AXG_NCTF_72
VCC_AXG_NCTF_73
VCC_AXG_NCTF_74
VCC_AXG_NCTF_75
VCC_AXG_NCTF_76
VCC_AXG_NCTF_77
VCC_AXG_NCTF_78
VCC_AXG_NCTF_79
VCC_AXG_NCTF_80
VCC_AXG_NCTF_81
VCC_AXG_NCTF_82
VCC_AXG_NCTF_83

VCC_SM_LF1
VCC_SM_LF2
VCC_SM_LF3
VCC_SM_LF4
VCC_SM_LF5
VCC_SM_LF6
VCC_SM_LF7

VCC SM LF

T17
T18
T19
T21
T22
T23
T25
U15
U16
U17
U19
U20
U21
U23
U26
V16
V17
V19
V20
V21
V23
V24
Y15
Y16
Y17
Y19
Y20
Y21
Y23
Y24
Y26
Y28
Y29
AA16
AA17
AB16
AB19
AC16
AC17
AC19
AD15
AD16
AD17
AF16
AF19
AH15
AH16
AH17
AH19
AJ16
AJ17
AJ19
AK16
AK19
AL16
AL17
AL19
AL20
AL21
AL23
AM15
AM16
AM19
AM20
AM21
AM23
AP15
AP16
AP17
AP19
AP20
AP21
AP23
AP24
AR20
AR21
AR23
AR24
AR26
V26
V28
V29
Y31

AW45
BC39
BE39
BD17
BD4
AW8
AT6

+VCCP

VCCSM_LF1
VCCSM_LF2
VCCSM_LF3
VCCSM_LF4
VCCSM_LF5
VCCSM_LF6
VCCSM_LF7

370mil

0.1U_0402_16V4Z~N

UMA@

1

C226

2

0.22U_0402_10V4Z~N UMA@

C170 0.1U_0402_16V4Z~N

C154 0.1U_0402_16V4Z~N

1

1

2

2

C153 0.22U_0603_10V7K~D

1

2

12

C229

C141 0.22U_0603_10V7K~D

1

2

0.47U_0603_10V7K

UMA@

1

C231

2

C135 0.47U_0402_6.3V6K

C148 1U_0603_10V4Z

1

1

2

2

C156 1U_0603_10V4Z

1

2

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2007/12/28 2007/12/28

Compal Secret Data

Deciphered Date

CRESTLINE_1p0 UMA@

2

Compal Electronics, Inc.

Title

Crestline(5/6)_PWR / GND

Size Document Number Rev

Custom

LA-4131P

Date: Sheet of

11 53Monday, February 18, 2008

1

0.2

5

U3I

A13

VSS_1

A15

VSS_2

A17

VSS_3

A24

VSS_4

AA21

VSS_5

AA24

VSS_6

AA29

VSS_7

AB20

D D

C C

B B

A A

VSS_8

AB23

VSS_9

AB26

VSS_10

AB28

VSS_11

AB31

VSS_12

AC10

VSS_13

AC13

VSS_14

AC3

VSS_15

AC39

VSS_16

AC43

VSS_17

AC47

VSS_18

AD1

VSS_19

AD21

VSS_20

AD26

VSS_21

AD29

VSS_22

AD3

VSS_23

AD41

VSS_24

AD45

VSS_25

AD49

VSS_26

AD5

VSS_27

AD50

VSS_28

AD8

VSS_29

AE10

VSS_30

AE14

VSS_31

AE6

VSS_32

AF20

VSS_33

AF23

VSS_34

AF24

VSS_35

AF31

VSS_36

AG2

VSS_37

AG38

VSS_38

AG43

VSS_39

AG47

VSS_40

AG50

VSS_41

AH3

VSS_42

AH40

VSS_43

AH41

VSS_44

AH7

VSS_45

AH9

VSS_46

AJ11

VSS_47

AJ13

VSS_48

AJ21

VSS_49

AJ24

VSS_50

AJ29

VSS_51

AJ32

VSS_52

AJ43

VSS_53

AJ45

VSS_54

AJ49

VSS_55

AK20

VSS_56

AK21

VSS_57

AK26

VSS_58

AK28

VSS_59

AK31

VSS_60

AK51

VSS_61

AL1

VSS_62

AM11

VSS_63

AM13

VSS_64

AM3

VSS_65

AM4

VSS_66

AM41

VSS_67

AM45

VSS_68

AN1

VSS_69

AN38

VSS_70

AN39

VSS_71

AN43

VSS_72

AN5

VSS_73

AN7

VSS_74

AP4

VSS_75

AP48

VSS_76

AP50

VSS_77

AR11

VSS_78

AR2

VSS_79

AR39

VSS_80

AR44

VSS_81

AR47

VSS_82

AR7

VSS_83

AT10

VSS_84

AT14

VSS_85

AT41

VSS_86

AT49

VSS_87

AU1

VSS_88

AU23

VSS_89

AU29

VSS_90

AU3

VSS_91

AU36

VSS_92

AU49

VSS_93

AU51

VSS_94

AV39

VSS_95

AV48

VSS_96

AW1

VSS_97

AW12

VSS_98

AW16

VSS_99

CRESTLINE_1p0 UMA@

VSS

VSS_100
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105
VSS_106
VSS_107
VSS_108
VSS_109
VSS_110
VSS_111
VSS_112
VSS_113
VSS_114
VSS_115
VSS_116
VSS_117
VSS_118
VSS_119
VSS_120
VSS_121
VSS_122
VSS_123
VSS_124
VSS_125
VSS_126
VSS_127
VSS_128
VSS_129
VSS_130
VSS_131
VSS_132
VSS_133
VSS_134
VSS_135
VSS_136
VSS_137
VSS_138
VSS_139
VSS_140
VSS_141
VSS_142
VSS_143
VSS_144
VSS_145
VSS_146
VSS_147
VSS_148
VSS_149
VSS_150
VSS_151
VSS_152
VSS_153
VSS_154
VSS_155
VSS_156
VSS_157
VSS_158
VSS_159
VSS_160
VSS_161
VSS_162
VSS_163
VSS_164
VSS_165
VSS_166
VSS_167
VSS_168
VSS_169
VSS_170
VSS_171
VSS_172
VSS_173
VSS_174
VSS_175
VSS_176
VSS_177
VSS_178
VSS_179
VSS_180
VSS_181
VSS_182
VSS_183
VSS_184
VSS_185
VSS_186
VSS_187
VSS_188
VSS_189
VSS_190
VSS_191
VSS_192
VSS_193
VSS_194
VSS_195
VSS_196
VSS_197
VSS_198

4

AW24
AW29
AW32
AW5
AW7
AY10
AY24
AY37
AY42
AY43
AY45
AY47
AY50
B10
B20
B24
B29
B30
B35
B38
B43
B46
B5
B8
BA1
BA17
BA18
BA2
BA24
BB12
BB25
BB40
BB44
BB49
BB8
BC16
BC24
BC25
BC36
BC40
BC51
BD13
BD2
BD28
BD45
BD48
BD5
BE1
BE19
BE23
BE30
BE42
BE51
BE8
BF12
BF16
BF36
BG19
BG2
BG24
BG29
BG39
BG48
BG5
BG51
BH17
BH30
BH44
BH46
BH8
BJ11
BJ13
BJ38
BJ4
BJ42
BJ46
BK15
BK17
BK25
BK29
BK36
BK40
BK44
BK6
BK8
BL11
BL13
BL19
BL22
BL37
BL47
C12
C16
C19
C28
C29
C33
C36
C41

3

U3J

C46

VSS_199

C50

VSS_200

C7

VSS_201

D13

VSS_202

D24

VSS_203

D3

VSS_204

D32

VSS_205

D39

VSS_206

D45

VSS_207

D49

VSS_208

E10

VSS_209

E16

VSS_210

E24

VSS_211

E28

VSS_212

E32

VSS_213

E47

VSS_214

F19

VSS_215

F36

VSS_216

F4

VSS_217

F40

VSS_218

F50

VSS_219

G1

VSS_220

G13

VSS_221

G16

VSS_222

G19

VSS_223

G24

VSS_224

G28

VSS_225

G29

VSS_226

G33

VSS_227

G42

VSS_228

G45

VSS_229

G48

VSS_230

G8

VSS_231

H24

VSS_232

H28

VSS_233

H4

VSS_234

H45

VSS_235

J11

VSS_236

J16

VSS_237

J2

VSS_238

J24

VSS_239

J28

VSS_240

J33

VSS_241

J35

VSS_242

J39

VSS_243

K12

VSS_245

K47

VSS_246

K8

VSS_247

L1

VSS_248

L17

VSS_249

L20

VSS_250

L24

VSS_251

L28

VSS_252

L3

VSS_253

L33

VSS_254

L49

VSS_255

M28

VSS_256

M42

VSS_257

M46

VSS_258

M49

VSS_259

M5

VSS_260

M50

VSS_261

M9

VSS_262

N11

VSS_263

N14

VSS_264

N17

VSS_265

N29

VSS_266

N32

VSS_267

N36

VSS_268

N39

VSS_269

N44

VSS_270

N49

VSS_271

N7

VSS_272

P19

VSS_273

P2

VSS_274

P23

VSS_275

P3

VSS_276

P50

VSS_277

R49

VSS_278

T39

VSS_279

T43

VSS_280

T47

VSS_281

U41

VSS_282

U45

VSS_283

U50

VSS_284

V2

VSS_285

V3

VSS_286

CRESTLINE_1p0 UMA@

VSS

VSS_287
VSS_288
VSS_289
VSS_290
VSS_291
VSS_292
VSS_293
VSS_294
VSS_295
VSS_296
VSS_297
VSS_298
VSS_299
VSS_300
VSS_301
VSS_302
VSS_303
VSS_304
VSS_305

VSS_306
VSS_307
VSS_308
VSS_309
VSS_310
VSS_311
VSS_312
VSS_313

W11
W39
W43
W47
W5
W7
Y13
Y2
Y41
Y45
Y49
Y5
Y50
Y11
P29
T29
T31
T33
R28

AA32
AB32
AD32
AF28
AF29
AT27
AV25
H50

2

1

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2007/12/28 2007/12/28

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

Compal Electronics, Inc.

Crestline(6/6)_GND

LA-4131P

1

0.2

of

12 53Monday, February 18, 2008

5

DDR_A_DQS#[0..7]8

DDR_A_D[0..63]8

DDR_A_DM[0..7]8
DDR_A_DQS[0..7]8
DDR_A_MA[0..13]8

D D

Layout Note:
Place near JDIM1

+DDR_MCH_REF17,14

close to connector

+1.8V

2.2U_0603_6.3V6K

0.1U_0402_16V4Z

1

2

C57

2.2U_0603_6.3V6K

C65

1

1

2

2

DDR_A_V

0.1U_0402_16V4Z

1

1

2

2

C74

C58

RP24

RP26

56_0404_4P2R_5%

1 4
2 3

RP18

56_0404_4P2R_5%

1 4
2 3

RP22

56_0404_4P2R_5%

RP23

56_0404_4P2R_5%

1 4
2 3

RP21

56_0404_4P2R_5%

56_0404_4P2R_5%

1 2

R47 56_0402_5%

C530

2.2U_0603_6.3V6K

1

2

0.1U_0402_16V4Z

1

2

C73

DDR_A_V

23
14

23
14

14
23

5

0.1U_0402_16V4Z

2.2U_0603_6.3V6K
C93

C531

1

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

2

2

C72

C69

56_0404_4P2R_5%

RP27

DDR_CKE0_DIMMA

2 3

DDR_A_MA12

1 4

RP20 56_0404_4P2R_5%

DDR_A_MA7

14

DDR_A_MA6

23

RP25 56_0404_4P2R_5%

DDR_A_BS#2

2 3

DDR_A_MA9

1 4

RP19 56_0404_4P2R_5%

DDR_A_MA2

14

DDR_A_MA4

23

RP15 56_0404_4P2R_5%

DDR_A_BS#1

14

DDR_A_MA0

23

RP17 56_0404_4P2R_5%

M_ODT0

14

DDR_A_MA13

23

RP16 56_0404_4P2R_5%

DDR_A_MA11

14

DDR_A_MA14

23

0.1U_0402_16V4Z

C520

1

2

0.1U_0402_16V4Z

1

2

C85

0.1U_0402_16V4Z

C522

C521

1

1

2

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

2

2

C71

C70

2.2U_0603_6.3V6K
C94

1

2

Layout Note:

C C

Place one cap close to every 2 pullup
resistors terminated to +0.9V

+0.9VS

0.1U_0402_16V4Z

B B

DDR_A_MA8
DDR_A_MA5

DDR_A_MA1
DDR_A_MA3

DDR_A_RAS#
DDR_CS0_DIMMA#

DDR_A_BS#0
DDR_A_MA10

DDR_A_CAS#
DDR_A_WE#

DDR_CS1_DIMMA#

A A

M_ODT1

DDR_CKE1_DIMMA

4

Layout Note:
+DDR_MCH_REF1
trace width and
spacing is 20/20.

+DDR_MCH_REF1

1

C64

2

0.1U_0402_16V4Z~N

330U_D2_2.5VY_R9M

0.1U_0402_16V4Z

1

2

C44

1

C101

C517

1

+

2

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

2

2

C45

C56

Layout Note:
Place these resistor
closely JDIM1,
all trace length Max=1.5"

4

3

+1.8V

+1.8V

+3VS

C79

0.1U_0402_16V4Z

DDR_A_D4
DDR_A_D1

DDR_A_DQS#0
DDR_A_DQS0

DDR_A_D2
DDR_A_D3

DDR_A_D8
DDR_A_D14

DDR_A_DQS#1
DDR_A_DQS1

DDR_A_D9

DDR_A_D16
DDR_A_D17

DDR_A_DQS#2
DDR_A_DQS2

DDR_A_D18
DDR_A_D19

DDR_A_D29
DDR_A_D24

DDR_A_DM3

DDR_A_D26
DDR_A_D27

DDR_CKE0_DIMMA

DDR_A_BS#2
DDR_A_MA12
DDR_A_MA8
DDR_A_MA5

DDR_A_MA3
DDR_A_MA1

DDR_A_MA10
DDR_A_BS#0

DDR_A_CAS#
DDR_CS1_DIMMA#

M_ODT1
DDR_A_D37

DDR_A_D36
DDR_A_DQS#4

DDR_A_DQS4
DDR_A_D35

DDR_A_D34
DDR_A_D40

DDR_A_D44
DDR_A_DM5
DDR_A_D41

DDR_A_D46
DDR_A_D49

DDR_A_D48

DDR_A_DQS#6
DDR_A_DQS6

DDR_A_D54
DDR_A_D50

DDR_A_D61
DDR_A_D60

DDR_A_DM7
DDR_A_D59

DDR_A_D58
ICH_SM_DA

ICH_SM_CLK

1

1

2

2

C80

2.2U_0603_6.3V6K

12

R43
1K_0402_1%

12

R42
1K_0402_1%

DDR_CKE0_DIMMA7

DDR_A_BS#28

DDR_A_BS#08

DDR_A_WE#8

DDR_A_CAS#8

0.1U_0402_16V4Z

1

2

C63

DDR_CS1_DIMMA#7

M_ODT17

ICH_SM_DA14,16,19

ICH_SM_CLK14,16,19

JDIM1

1

VREF

3

VSS

5

DQ0

7

DQ1

9

VSS

11

DQS0#

13

DQS0

15

VSS

17

DQ2

19

DQ3

21

VSS

23

DQ8

25

DQ9

27

VSS

29

DQS1#

31

DQS1

33

VSS

35

DQ10

37

DQ11

39

VSS

41

VSS

43

DQ16

45

DQ17

47

VSS

49

DQS2#

51

DQS2

53

VSS

55

DQ18

57

DQ19

59

VSS

61

DQ24

63

DQ25

65

VSS

67

DM3

69

NC

71

VSS

73

DQ26

75

DQ27

77

VSS

79

CKE0

81

VDD

83

NC

85

BA2

87

VDD

89

A12

91

A9

93

A8

95

VDD

97

A5

99

A3

101

A1

103

VDD

105

A10/AP

107

BA0

109

WE#

111

VDD

113

CAS#

115

NC/S1#

117

VDD

119

NC/ODT1

121

VSS

123

DQ32

125

DQ33

127

VSS

129

DQS4#

131

DQS4

133

VSS

135

DQ34

137

DQ35

139

VSS

141

DQ40

143

DQ41

145

VSS

147

DM5

149

VSS

151

DQ42

153

DQ43

155

VSS

157

DQ48

159

DQ49

161

VSS

163

NC,TEST

165

VSS

167

DQS6#

169

DQS6

171

VSS

173

DQ50

175

DQ51

177

VSS

179

DQ56

181

DQ57

183

VSS

185

DM7

187

VSS

189

DQ58

191

DQ59

193

VSS

195

SDA

197

SCL

199

VDDSPD

FOX_ASOA426-M2RN-7F

CONN@

SO-DIMM A

VSS
DQ4
DQ5

VSS
DM0

VSS
DQ6
DQ7

VSS

DQ12
DQ13

VSS
DM1

VSS

CK0

CK0#

VSS

DQ14
DQ15

VSS

VSS

DQ20
DQ21

VSS
DM2

VSS

DQ22
DQ23

VSS

DQ28
DQ29

VSS

DQS3#

DQS3

VSS

DQ30
DQ31

VSS

NC/CKE1

VDD

NC/A15
NC/A14

VDD

VDD

VDD

BA1

RAS#

VDD

ODT0

NC/A13

VDD

VSS

DQ36
DQ37

VSS
DM4

VSS

DQ38
DQ39

VSS

DQ44
DQ45

VSS

DQS5#

DQS5

VSS

DQ46
DQ47

VSS

DQ52
DQ53

VSS

CK1

CK1#

VSS
DM6

VSS

DQ54
DQ55

VSS

DQ60
DQ61

VSS

DQS7#

DQS7

VSS

DQ62
DQ63

VSS

SA0

SA1

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

42
44
46
48
50

NC

52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90

A11

92

A7

94

A6

96
98

A4

100

A2

102

A0

104
106
108
110

S0#

112
114
116
118
120

NC

122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200

2

DDR_A_D6
DDR_A_D0

DDR_A_DM0
DDR_A_D5

DDR_A_D7
DDR_A_D13

DDR_A_D12
DDR_A_DM1
M_CLK_DDR0

M_CLK_DDR#0
DDR_A_D11

DDR_A_D10DDR_A_D15

DDR_A_D20
DDR_A_D21

DDR_A_DM2
DDR_A_D23

DDR_A_D22
DDR_A_D28

DDR_A_D25
DDR_A_DQS#3

DDR_A_DQS3
DDR_A_D31

DDR_A_D30
DDR_CKE1_DIMMA

DDR_A_MA14
DDR_A_MA11

DDR_A_MA7DDR_A_MA9
DDR_A_MA6

DDR_A_MA4
DDR_A_MA2
DDR_A_MA0

DDR_A_BS#1
DDR_A_RAS#
DDR_CS0_DIMMA#DDR_A_WE#

M_ODT0
DDR_A_MA13

DDR_A_D32
DDR_A_D33

DDR_A_DM4
DDR_A_D39

DDR_A_D38
DDR_A_D45

DDR_A_D43
DDR_A_DQS#5

DDR_A_DQS5
DDR_A_D47

DDR_A_D42
DDR_A_D52

DDR_A_D53
M_CLK_DDR1

M_CLK_DDR#1
DDR_A_DM6
DDR_A_D51

DDR_A_D55
DDR_A_D57

DDR_A_D56
DDR_A_DQS#7

DDR_A_DQS7
DDR_A_D62

DDR_A_D63

12

R49

R48

10K_0402_5%

10K_0402_5%

Close to VREF pins of SO-DIMM

2.2U_0805_16V4Z
C53

1

2

M_CLK_DDR0 7
M_CLK_DDR#0 7

PM_EXTTS#0 7

DDR_CKE1_DIMMA 7

DDR_A_MA14 7

DDR_A_BS#1 8
DDR_A_RAS# 8
DDR_CS0_DIMMA# 7

M_ODT0 7

M_CLK_DDR1 7
M_CLK_DDR#1 7

12

1

+DDR_MCH_REF1

0.1U_0402_16V4Z
C51

1

2

Bottom side

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2007/12/28 2007/12/28

3

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

Compal Electronics, Inc.

DDR2 SO-DIMM I

LA-4131P

0.2

of

13 53Monday, February 18, 2008

1

5

DDR_B_DQS#[0..7]8

DDR_B_D[0..63]8

DDR_B_DM[0..7]8

DDR_B_DQS[0..7]8

DDR_B_MA[0..13]8

D D

Layout Note:
Place near JDIM2

+1.8V

2.2U_0603_6.3V6K

2.2U_0603_6.3V6K
C67

1

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

2

C81

RP14

RP10

RP6

RP12

RP9

RP8

R36 56_0402_5%

2.2U_0603_6.3V6K
C66

1

2

0.1U_0402_16V4Z

1

2

C62

56_0404_4P2R_5%

56_0404_4P2R_5%

1 4
2 3

56_0404_4P2R_5%

56_0404_4P2R_5%

56_0404_4P2R_5%

56_0404_4P2R_5%

1 2

5

C49

1

2

Layout Note:
Place one cap close to every 2 pullup
resistors terminated to +0.9VS

C C

+0.9VS

0.1U_0402_16V4Z

1

2

C83

B B

DDR_CKE2_DIMMB
DDR_B_BS#2

DDR_B_MA8
DDR_B_MA5

DDR_CS2_DIMMB#
DDR_B_BS#1

DDR_B_WE#
DDR_B_CAS#

A A

DDR_B_MA10
DDR_B_BS#0

M_ODT3
DDR_CS3_DIMMB# M_ODT2

DDR_CKE3_DIMMB

1

2

23
14

23
14

23
14

23
14

14
23

C82

2.2U_0603_6.3V6K

1

2

0.1U_0402_16V4Z

DDR_B_V

2 3
1 4

2 3
1 4

2.2U_0603_6.3V6K

0.1U_0402_16V4Z

C78

C76

1

2

DDR_B_V

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

2

C84

RP4 56_0404_4P2R_5%

RP3 56_0404_4P2R_5%

RP11

RP7 56_0404_4P2R_5%

RP13 56_0404_4P2R_5%

RP2 56_0404_4P2R_5%

RP5

56_0404_4P2R_5%

1

2

2

C86

DDR_B_MA7

14

DDR_B_MA6

23

DDR_B_MA4

14

DDR_B_MA2

23

56_0404_4P2R_5%

DDR_B_MA12
DDR_B_MA9

DDR_B_MA0

14

DDR_B_RAS#

23

DDR_B_MA3
DDR_B_MA1

DDR_B_MA13

14
23

DDR_B_MA14

14

DDR_B_MA11

23

0.1U_0402_16V4Z

0.1U_0402_16V4Z

C518

C523

1

1

2

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

2

2

C61

C59

C87

4

0.1U_0402_16V4Z

C519

1

1

2

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

2

2

C60

C47

Layout Note:
Place these resistor
closely JDIM2,
all trace length Max=1.5"

4

3

+1.8V

JDIM2

1

VREF

3

DDR_B_D0
DDR_B_D1

DDR_B_DQS#0
DDR_B_DQS0

DDR_B_D2
DDR_B_D3

DDR_B_D8
DDR_B_D9

DDR_B_DQS#1
DDR_B_DQS1

DDR_B_D10
DDR_B_D11

330U_D2_2.5VY_R9M

1

C100

C68

+

@

2

DDR_CKE2_DIMMB7

DDR_B_BS#08

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

2

2

C48

C46

DDR_B_WE#8

DDR_B_CAS#8

DDR_CS3_DIMMB#7

M_ODT37

ICH_SM_DA13,16,19

ICH_SM_CLK13,16,19

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

DDR_B_D17
DDR_B_D20

DDR_B_DQS#2
DDR_B_DQS2

DDR_B_D18
DDR_B_D19

DDR_B_D28
DDR_B_D25

DDR_B_DM3

DDR_B_D30
DDR_B_D31

DDR_CKE2_DIMMB

DDR_B_BS#2
DDR_B_MA12

DDR_B_MA9
DDR_B_MA8

DDR_B_MA5
DDR_B_MA3
DDR_B_MA1

DDR_B_MA10
DDR_B_BS#0
DDR_B_WE#

DDR_B_CAS#
DDR_CS3_DIMMB#

M_ODT3
DDR_B_D32

DDR_B_D33
DDR_B_DQS#4

DDR_B_DQS4
DDR_B_D34

DDR_B_D35
DDR_B_D40

DDR_B_D41
DDR_B_DM5
DDR_B_D42

DDR_B_D43
DDR_B_D48

DDR_B_D49

DDR_B_DQS#6
DDR_B_DQS6

DDR_B_D51
DDR_B_D50

DDR_B_D56
DDR_B_D61

DDR_B_DM7
DDR_B_D59

DDR_B_D58
ICH_SM_DA

ICH_SM_CLK

+3VS

1

2

1

C55

2.2U_0603_6.3V6K

2

C54

0.1U_0402_16V4Z

2007/12/28 2007/12/28

3

VSS

5

DQ0

7

DQ1

9

VSS

11

DQS0#

13

DQS0

15

VSS

17

DQ2

19

DQ3

21

VSS

23

DQ8

25

DQ9

27

VSS

29

DQS1#

31

DQS1

33

VSS

35

DQ10

37

DQ11

39

VSS

41

VSS

43

DQ16

45

DQ17

47

VSS

49

DQS2#

51

DQS2

53

VSS

55

DQ18

57

DQ19

59

VSS

61

DQ24

63

DQ25

65

VSS

67

DM3

69

NC

71

VSS

73

DQ26

75

DQ27

77

VSS

79

CKE0

81

VDD

83

NC

85

BA2

87

VDD

89

A12

91

A9

93

A8

95

VDD

97

A5

99

A3

101

A1

103

VDD

105

A10/AP

107

BA0

109

WE#

111

VDD

113

CAS#

115

NC/S1#

117

VDD

119

NC/ODT1

121

VSS

123

DQ32

125

DQ33

127

VSS

129

DQS4#

131

DQS4

133

VSS

135

DQ34

137

DQ35

139

VSS

141

DQ40

143

DQ41

145

VSS

147

DM5

149

VSS

151

DQ42

153

DQ43

155

VSS

157

DQ48

159

DQ49

161

VSS

163

NC,TEST

165

VSS

167

DQS6#

169

DQS6

171

VSS

173

DQ50

175

DQ51

177

VSS

179

DQ56

181

DQ57

183

VSS

185

DM7

187

VSS

189

DQ58

191

DQ59

193

VSS

195

SDA

197

SCL

199

VDDSPD

FOX_AS0A426-NARN-7F~N

CONN@

SO-DIMM B

Bottom side

Compal Secret Data

Deciphered Date

VSS
DQ4
DQ5

VSS
DM0

VSS
DQ6
DQ7

VSS

DQ12
DQ13

VSS
DM1

VSS

CK0

CK0#

VSS

DQ14
DQ15

VSS

VSS

DQ20
DQ21

VSS
DM2

VSS

DQ22
DQ23

VSS

DQ28
DQ29

VSS

DQS3#

DQS3

VSS

DQ30
DQ31

VSS

NC/CKE1

VDD

NC/A15
NC/A14

VDD

VDD

VDD

BA1

RAS#

VDD

ODT0

NC/A13

VDD

VSS

DQ36
DQ37

VSS
DM4

VSS

DQ38
DQ39

VSS

DQ44
DQ45

VSS

DQS5#

DQS5

VSS

DQ46
DQ47

VSS

DQ52
DQ53

VSS

CK1

CK1#

VSS
DM6

VSS

DQ54
DQ55

VSS

DQ60
DQ61

VSS

DQS7#

DQS7

VSS

DQ62
DQ63

VSS
SAO

SA1

NC

A11

A7
A6

A4
A2
A0

S0#

NC

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200

2

+DDR_MCH_REF1

DDR_B_D5
DDR_B_D4

DDR_B_DM0
DDR_B_D6

DDR_B_D7
DDR_B_D12

DDR_B_D13
DDR_B_DM1
M_CLK_DDR2

M_CLK_DDR#2
DDR_B_D14

DDR_B_D15

DDR_B_D21
DDR_B_D16

DDR_B_DM2
DDR_B_D22

DDR_B_D23
DDR_B_D26

DDR_B_D24
DDR_B_DQS#3

DDR_B_DQS3
DDR_B_D29

DDR_B_D27
DDR_CKE3_DIMMB

DDR_B_MA14
DDR_B_MA11

DDR_B_MA7
DDR_B_MA6

DDR_B_MA4
DDR_B_MA2
DDR_B_MA0

DDR_B_BS#1
DDR_B_RAS#
DDR_CS2_DIMMB#

M_ODT2
DDR_B_MA13

DDR_B_D36
DDR_B_D37

DDR_B_DM4
DDR_B_D39

DDR_B_D38
DDR_B_D44

DDR_B_D45
DDR_B_DQS#5

DDR_B_DQS5
DDR_B_D46

DDR_B_D47
DDR_B_D52

DDR_B_D53
M_CLK_DDR3

M_CLK_DDR#3
DDR_B_DM6
DDR_B_D54

DDR_B_D55
DDR_B_D60

DDR_B_D57
DDR_B_DQS#7

DDR_B_DQS7
DDR_B_D62

DDR_B_D63

10K_0402_5%

2

1

Close to VREF pins of SO-DIMM

0.1U_0402_16V4Z

2.2U_0805_16V4Z

M_CLK_DDR2 7
M_CLK_DDR#2 7

PM_EXTTS#1 7

DDR_CKE3_DIMMB 7

DDR_B_MA14 7DDR_B_BS#28

DDR_B_BS#1 8
DDR_B_RAS# 8
DDR_CS2_DIMMB# 7

M_ODT2 7

M_CLK_DDR3 7
M_CLK_DDR#3 7

R37

1 2

12

10K_0402_5%

R38

Title

DDR2 SO-DIMM II

Size Document Number Rev

Custom

LA-4131P

Date: Sheet

1

1

C50

C52

2

2

+3VS

Compal Electronics, Inc.

+DDR_MCH_REF1 7,13

1

0.2

of

14 53Monday, February 18, 2008

A

C R T

VGA@

VGA_CRT_B34

VGA_CRT_G34

VGA_CRT_R34

1 1

CRT_R9

CRT_G9

CRT_B9

CRT_HSYNC9

VGA_HSYNC34

2 2

VGA_VSYNC34

CRT_VSYNC9

12

R336 0_0402_5%

VGA@

12

R341 0_0402_5%

VGA@

12

R338 0_0402_5%

UMA@

12

R339 0_0402_5%

UMA@

12

R342 0_0402_5%

UMA@

12

R335 0_0402_5%

C9 0.1U_0402_16V4Z

CRT_HSYNC

CRT_VSYNC

UMA@

1 2

R406 30_0402_1%

VGA@

R405 0_0402_5%

VGA@

R401 0_0402_5%

UMA@

1 2

R404 30_0402_1%

Close to GMCH

12

R340

150_0402_1%

1 2

12

12

12

R337

R334

150_0402_1%

CRT_HSYNC_B

CRT_VSYNC_B

Close to VGA

CRT_R_C

CRT_G_C

CRT_B_C

12

150_0402_1%

+CRT_VCC

C13 0.1U_0402_16V4Z

D22

DAN217_SC59-3

1

+3VS

2

3

VGA@

1

C455

C456

@

5

P

A2Y

G

3

1 2

@

2

22P_0402_50V8J

1

4

OE#

U4

74AHCT1G125GW_SOT353-5

D23

DAN217_SC59-3

2

VGA@

1

2

22P_0402_50V8J

+CRT_VCC

D24

DAN217_SC59-3

1

2

3

VGA@

1 2

BK1608LL121-T 0603

1 2

BK1608LL121-T 0603

1 2

BK1608LL121-T 0603

1

C457

For EMI

@

2

22P_0402_50V8J

R15 10K_0402_5%

1

5

P

4

OE#

A2Y

G

U574AHCT1G125GW_SOT353-5

3

B

1

For nVIDIA

3

L25

L24

L23

12

D_CRT_HSYNC

D_CRT_VSYNC

CRT_R_L

CRT_G_L

CRT_B_L

C452

1

1

C451

2

2

4.7P_0402_50V8C

1 2

R16 0_0603_5%

1 2

R6 0_0603_5%

4.7P_0402_50V8C

C450

C

+5VS

C5

1

2

100P_0402_50V8J

D21

2 1

RB411DT146 SOT23

C6

0.1U_0402_16V4Z

C7

C1

1

1

2

2

100P_0402_50V8J

100P_0402_50V8J

1 2

R8
0_1206_5%~D

MSEN#28

1

2

4.7P_0402_50V8C

HSYNC_L

C3

C2

1

2

C4

1

1

2

2

15P_0402_50V8J

15P_0402_50V8J

+CRT_VCC

1

2

100P_0402_50V8J

W=40milsW=40mils

@

1

C448

2

0.1U_0402_16V4Z
JCRT1

6

11

1
7

12

2
8

13

3
9

14

4
10
15

5

SUYIN_070549FR015S208CR

VGA_DDC_DATA_C

VGA_DDC_CLK_CVSYNC_L

16
17

CONN@

D

原本為

4.7K

R7

1 2

2K_0402_5%

R2

2K_0402_5%

1 2

R3

1 2
2

G

2.2K_0402_5%

1 3

D

Q2BSS138_NL_SOT23

BSS138_NL_SOT23

+3VS

S

2

1 3

D

Q1

D18

@

DAN217_SC59-3

2

CRT_B_L

原本為

R20

1 2

2.2K_0402_5%

G

S

1

3

10K

+3VS+CRT_VCC +3VS+CRT_VCC +3VS

1 2

E

D19

@

DAN217_SC59-3

CRT_G_L

R11

2.2K_0402_5%

R14 0_0402_5%

R12 0_0402_5%

R13 0_0402_5%

R21 0_0402_5%

2

UMA@

UMA@

VGA@

VGA@

1

3

DAN217_SC59-3

CRT_R_L

12

12

12

12

D20

@

1

For ESD.

2

3

Close to JCRT1.

3VDDCDA 9

3VDDCCL 9

VGA_DDCCLK 34

VGA_DDCDATA 34

EDID_CLK_LCD
EDID_DAT_LCD

C461

LVDSBC+
LVDSBC-

LVDSB0+
LVDSB0-

LVDSB1+
LVDSB1-

LVDSB2+
LVDSB2-

BIA_PWM9

+3VALW

47K_0402_5%

12

R17

JP4

1
3
5
7
9

11
13
15
17
19
21
23
25
27
29
31
33
35
37
39

87242-4001-09 40P

CONN@

@

BIA_PWM INVT_PWM

10_0402_5%

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
GND41GND

R343

1N4148_SOT23@

2

2

4

4

6

6

8

8

10

10

12

12

14

14

16

16

18

18

20

20

22

22

24

24

26

26

28

28

30

30

32

32

34

34

36

36

38

38

40

40

42

12

D25

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

BISTLCD_DET#
LVDSAC+

LVDSAC­LVDSA0+

LVDSA0­LVDSA1+

LVDSA1­LVDSA2+

LVDSA2­EC_SMB_CK1

EC_SMB_DA1
INVT_PWM

INVPWR_B+
INVPWR_B+

12

1

2

BIST 28

EC_SMB_CK1 28,49
EC_SMB_DA1 28,49
INVT_PWM 28

INVPWR_B+

C453

1U_0603_10V4Z@

2007/12/28 2007/12/28

Compal Secret Data

Deciphered Date

GMCH_LVDSAC+9

GMCH_LVDSAC-9
GMCH_LVDSA0+9

GMCH_LVDSA0-9
GMCH_LVDSA1+9

GMCH_LVDSA1-9
GMCH_LVDSA2+9

GMCH_LVDSA2-9

GMCH_LVDSBC+9

GMCH_LVDSBC-9
GMCH_LVDSB0+9

GMCH_LVDSB0-9
GMCH_LVDSB1+9

GMCH_LVDSB1-9
GMCH_LVDSB2+9

GMCH_LVDSB2-9

GMCH_EDID_CLK_LCD9
GMCH_EDID_DAT_LCD9

VGA_LVDSAC+36
VGA_LVDSAC-36

VGA_LVDSA0+36
VGA_LVDSA0-36

VGA_LVDSA1+36
VGA_LVDSA1-36

VGA_LVDSA2+36
VGA_LVDSA2-36

VGA_LVDSBC+36
VGA_LVDSBC-36

VGA_LVDSB0+36
VGA_LVDSB0-36

VGA_LVDSB1+36
VGA_LVDSB1-36

VGA_LVDSB2+36
VGA_LVDSB2-36

VGA_CLK_LCD34
VGA_DAT_LCD34

D

LCD_TEST_EN

1

C466

2

0.1U_0603_50V4Z~D
2200P_0402_50V7K~D

A

+3VALW

0.1U_0402_16V7K~N

C469

1

2

2 1

D27 CH751H-40PT_SOD323-2@

2 1

D28 CH751H-40PT_SOD323-2@

R358

1 2

0_0402_5%

W=60mils

B+

1

C465

2

1000P_0402_50V7K~D

W=60mils

12

R356
200K_0402_5%~D

100K_0402_5%~D

SUSP#26,28,32,44,47

U54

IN6OUT
EN3NC

5

GND

GND

AOZ1320CI-04_SOT23-6

R357
10K_0402_5%

1 2

FDS4435: P Channel MOS

Q29

FDS4435BZ_SO8~D

R22

8
7

1

6

2

5

3

4

Q3

2N7002W-7-F_SOT323-3~D

D

S

12

1 3

G

2

W=60mils

1
4
2

INVPWR_B+

1

2

+LCDVDD

+LCDVDD

C463 4.7U_0805_6.3V6K~N

1

2

W=60mils

C460

0.1U_0603_50V4Z~D

C462 0.1U_0402_16V7K~N

1

LCD_DET#28
+5VALW

2

+LCDVDD

+3VS

0.1U_0402_16V4Z

1

2

B

L C D

GMCH_LVDDEN9,28

VGA_LVDDEN28,34

3 3

LCD_TEST_EN28

1

C467

2

4 4

GMCH_LVDSAC+

GMCH_LVDSAC­GMCH_LVDSA0+

GMCH_LVDSA0-

GMCH_LVDSA1+ LVDSA1+

GMCH_LVDSA1-

GMCH_LVDSA2+

GMCH_LVDSA2-

GMCH_LVDSBC+

GMCH_LVDSBC­GMCH_LVDSB0+

GMCH_LVDSB0-

GMCH_LVDSB1+

GMCH_LVDSB1-

GMCH_LVDSB2+

GMCH_LVDSB2-

GMCH_EDID_CLK_LCD
GMCH_EDID_DAT_LCD

VGA_LVDSAC+
VGA_LVDSAC-

VGA_LVDSA0+
VGA_LVDSA0-

VGA_LVDSA1+
VGA_LVDSA1-

VGA_LVDSA2+
VGA_LVDSA2-

VGA_LVDSBC+
VGA_LVDSBC-

VGA_LVDSB0+
VGA_LVDSB0-

VGA_LVDSB1+
VGA_LVDSB1-

VGA_LVDSB2+
VGA_LVDSB2-

VGA_DAT_LCD EDID_DAT_LCD

R418 0_0402_5% VGA@

1 2

R417 0_0402_5% VGA@

1 2

R461 0_0402_5% VGA@

1 2

R460 0_0402_5% VGA@

1 2

R463 0_0402_5% VGA@

1 2

R462 0_0402_5% VGA@

1 2

R449 0_0402_5% VGA@

1 2

R439 0_0402_5% VGA@

1 2

R459 0_0402_5% VGA@

1 2

R458 0_0402_5% VGA@

1 2

R454 0_0402_5% VGA@

1 2

R455 0_0402_5% VGA@

1 2

R452 0_0402_5% VGA@

1 2

R453 0_0402_5% VGA@

1 2

R456 0_0402_5% VGA@

1 2

R457 0_0402_5% VGA@

1 2

R353 0_0402_5% VGA@

1 2

R350 0_0402_5% VGA@

1 2

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

CRT Conn / LCD Conn

LA-4131P

12
12

12
12

12
12

12
12

12
12

12
12

12
12

12
12

12
12

E

R4220_0402_5% UMA@
R4210_0402_5% UMA@

R4350_0402_5% UMA@
R4340_0402_5% UMA@

R4370_0402_5% UMA@
R4360_0402_5% UMA@

R4480_0402_5% UMA@
R4380_0402_5% UMA@

R4330_0402_5% UMA@
R4320_0402_5% UMA@

R4280_0402_5% UMA@
R4290_0402_5% UMA@

R4260_0402_5% UMA@
R4270_0402_5% UMA@

R4300_0402_5% UMA@
R4310_0402_5% UMA@

R3520_0402_5% UMA@
R3490_0402_5% UMA@

LVDSAC+

LVDSAC­LVDSA0+

LVDSA0-

LVDSA1-

LVDSA2+

LVDSA2-

LVDSBC+

LVDSBC­LVDSB0+

LVDSB0-

LVDSB1+

LVDSB1-

LVDSB2+

LVDSB2-

EDID_CLK_LCD
EDID_DAT_LCD

LVDSAC+
LVDSAC-

LVDSA0+
LVDSA0-

LVDSA1+
LVDSA1-

LVDSA2+
LVDSA2-

LVDSBC+
LVDSBC-

LVDSB0+
LVDSB0-

LVDSB1+
LVDSB1-

LVDSB2+
LVDSB2-

EDID_CLK_LCDVGA_CLK_LCD

15 53Monday, February 18, 2008

0.2

of

5

PCI

SRC

CPU

CLKSEL1

1

1

FSLA

CLKSEL0

MHz

200

166

MHz

1000

100

MHz

33.30

33.3

FSLC1FSLB

CLKSEL2

0

FSB Frequency Selet:

D D

CPU Driven

(Default)

*

Stuff

No Stuff

Stuff

667MHz

No Stuff

Stuff

800MHz

CPU_BSEL05

C C

CPU_BSEL15

CPU_BSEL25

B B

A A

18P_0402_50V8J~N

No Stuff

R548

2.2K_0402_5%

FSA

1 2

R550

0_0402_5%

FSB

1 2

R501

0_0402_5%

R516

10K_0402_5%

FSC

1 2

R519

@

0_0402_5%

Y4

14.31818MHz_20P_1BX14318BE1A

2

C667

1

Routing the trace at least 10mil

R1107 R1135 R1083

R1074 R1086 R1098 R1113 R1139

R1139 R1135R1135 R1139

R1083

R1107

R1128

R1098

R1113

R1135 R1139

R1083

R1086
R1107

@

R1098
R1113

MCH_CLKSEL0 7

MCH_CLKSEL1 7

MCH_CLKSEL2 7

R1074

12

1 2

R556

+VCCP

12

1K_0402_5%

R502
1K_0402_5%

1 2

1 2

R499

1K_0402_5%

1 2

R517

1K_0402_5%

12

R514

0_0402_5%

For ITP_EN, 0 =SRC8/SRC8#; 1 = ITP/ITP#
For 27_SEL, 0 = Enable DOT96 & SRC1,

For PCI2_EN, 0 = Overclocking of CPU and SRC Allowed

CLK_XTAL_OUT

CLK_XTAL_IN

Placed
within 500
mils of
CK505M

12

2

C666
18P_0402_50V8J~N

1

5

1 2

R1128

R1074R1086

R1128

CLKSATAREQ#19

CLKMCHREQ#7

CLK_PCI_CB25,28
CLK_PCI_TPM28

CLK_DEBUG_PORT27

CLK_PCI_EC28
CLK_PCI_ICH17

CLK_48M_ICH19

CLK_14M_ICH19
CLK_14M_SIO

1 = Enable SRC0 & 27MHz

1 = Overclocking of CPU and SRC NOT allowed

+3VM_CK505

ITP_EN

R534
10K_0402_5%

R549
10K_0402_5%

VGA@

1 2

27_SEL

R545
10K_0402_5%

UMA@

1 2

4

3

2

1

Place these caps close to U6

+3VM_CK505

R521

1 2

+3VS

0_0805_5%

+1.25VM_CK505

R520

1 2

+1.25VS

0_0805_5%

+3VM_CK505

+1.25VM_CK505

+3VS
+3VS

+3VM_CK505

4

R52410K_0402_5%

R53010K_0402_5%

1 2
1 2
1 2

1 2
1 2

1 2
1 2

1 2

1 2
1 2

R535

10K_0402_5%

1 2

PCI2_TME

R531

10K_0402_5%

@

1 2

12
12

R525475_0402_1%
R529475_0402_1%
R52733_0402_5%

R52833_0402_5%
R53233_0402_5%

R53633_0402_5%
R52633_0402_5%

R53333_0402_5%

R51533_0402_5%
R50933_0402_5%

+1.25VM_CK505

SATA_REQ
MCH_REQ
PCI2_TME
PCI_CLK3
27_SEL
ITP_EN

CLK_XTAL_IN
CLK_XTAL_OUT

FSA

FSB

FSC

+3VM_CK505 = 250 mA

1

C684
10U_0805_10V4Z~N

2

1

C687

0.1U_0402_16V4Z~N

2

1

C678

0.1U_0402_16V4Z~N

2

1

C685

0.1U_0402_16V4Z~N

2

1

C677

0.1U_0402_16V4Z~N

2

1

2

+1.25VM_CK505 = 80 mA

1

C682
22U_0805_6.3V4Z

2

U6

2

VDDPCI

9

VDD48

16

VDDPLL3

61

VDDREF

39

VDDSRC

55

VDDCPU

12

VDD96_IO

20

VDDPLL3_IO

26

VDDSRC_IO

36

VDDSRC_IO

49

VDDCPU_IO

1

PCI0/CR#_A

3

PCI1/CR#_B

4

PCI2/TME

5

PCI3

6

PCI4/27_Select

7

PCI_F5/ITP_EN

60

X1

59

X2

10

USB_48MHZ/FSLA

57

FSLB/TEST_MODE

62

REF0/FSLC/TEST_SEL

45

VDDSRC_IO

42

GNDSRC

8

GNDPCI

11

GND48

15

GND

19

GND

52

GNDCPU

23

GNDSRC

29

GNDSRC

58

GNDREF

ICS9LPRS365BGLFT_TSSOP64

1

C686

0.1U_0402_16V4Z~N

2

SRC1/SE1/27MHz_NonSS

SRC1#/SE2/27MHz_SS

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

1

C688

0.1U_0402_16V4Z~N

2

NC

SCLK

SDATA

PCI_STOP#

CPU_STOP#

CPU0

CPU0#

CPU1_F

CPU1#_F

SRC8/CPU2_ITP

SRC8#/CPU2_ITP#

SRC10

SRC10#

SRC11/CR#_H

SRC11#/CR#_G

SRC9

SRC9#

SRC7/CR#_F

SRC7#/CR#_E

SRC6

SRC6#

SRC4

SRC4#

SRC3/CR#_C

SRC3#/CR#_D

SRC2/SATA

SRC2#/SATA#

SRC0/DOT96

SRC0#/DOT96#

CK_PWRGD/PD#

2007/12/28 2007/12/28

1

C681
22U_0805_6.3V4Z

2

48

64
63

38
37

R_CPU_BCLK

54

R_CPU_BCLK#

53

R_MCH_BCLK

51

R_MCH_BCLK#

50

R_PCIE_LAN

47

R_PCIE_LAN#

46

R_PCIE_EXPR

34

R_PCIE_EXPR#

35

R_CLKREQ#_H

33

R_CLKREQ#_G

32

R_CLK_PCIE_MCard

30

R_CLK_PCIE_MCard#

31

R_PCIE_LAN_REQ#

44

R_ROBSON_REQ#

43

R_CLK_ROB

41

R_CLK_ROB#

40

R_MCH_3GPLL

27

R_MCH_3GPLL#

28

R_PCIE_ICH

24

R_PCIE_ICH#

25

R_PCIE_SATA

21

R_PCIE_SATA#

22

R_SSCDREFCLK

17

R_SSCDREFCLK#

18

R_MCH_DREFCLK

13

R_MCH_DREFCLK#

14

56

R553 0_0402_5%VGA@
R554 0_0402_5%VGA@

Compal Secret Data

Deciphered Date

1

C689

0.1U_0402_16V4Z~N

2

R493

1 2
1 2

R494
R495

1 2

1 2

R496
R503

1 2

1 2

R504
R513

1 2

1 2

R512
R522

R510
R537

1 2

1 2

R538
R497

1 2

1 2

R498 475_0402_1%

R505

1 2

1 2

R506
R541

1 2

1 2

R542
R539

1 2

1 2

R540
R543

1 2

1 2

R544

R555 0_0402_5%UMA@

1 2

R552 0_0402_5%UMA@

1 2

R546

1 2

1 2

R547

1 2

1 2

1 2

R507 0_0402_5%@

12
12

0_0402_5%
0_0402_5%

0_0402_5%
0_0402_5%

0_0402_5%
0_0402_5%

0_0402_5%
0_0402_5%

1 2

R511 10K_0402_5%
475_0402_1%
475_0402_1%

1 2

R523 10K_0402_5%
0_0402_5%
0_0402_5%

1 2

R484 10K_0402_5%
475_0402_1%

1 2

R485 10K_0402_5%
0_0402_5%

0_0402_5%

0_0402_5%
0_0402_5%

0_0402_5%
0_0402_5%

0_0402_5%
0_0402_5%

0_0402_5%UMA@
0_0402_5%UMA@

CK_PWRGD

2

1

2

CLK_EN#

C683

0.1U_0402_16V4Z~N

C680

0.1U_0402_16V4Z~N

ICH_SM_CLK 13,14,19
ICH_SM_DA 13,14,19

H_STP_PCI# 19
H_STP_CPU# 19

CLK_CPU_BCLK 4
CLK_CPU_BCLK# 4

CLK_MCH_BCLK 7
CLK_MCH_BCLK# 7

CLK_PCIE_LAN 22
CLK_PCIE_LAN# 22

CLK_PCIE_EXPR 26
CLK_PCIE_EXPR# 26

+3VS

EXPR_CARD_REQ# 26
MCARD_REQ# 27

+3VS

CLK_PCIE_MCARD 27
CLK_PCIE_MCARD# 27

+3VS

PCIE_LAN_REQ# 22
ROBSON_REQ# 27

+3VS

CLK_PCIE_ROB 27
CLK_PCIE_ROB# 27

CLK_MCH_3GPLL 7
CLK_MCH_3GPLL# 7

CLK_PCIE_ICH 19
CLK_PCIE_ICH# 19

CLK_PCIE_SATA 18
CLK_PCIE_SATA# 18

MCH_SSCDREFCLK 7
MCH_SSCDREFCLK# 7

CLK_MCH_DREFCLK 7
CLK_MCH_DREFCLK# 7

CLK_PCIE_VGA 34
CLK_PCIE_VGA# 34

CK_PWRGD 19
CLK_EN# 48

1

C676

0.1U_0402_16V4Z~N

2

1

C679

0.1U_0402_16V4Z~N

2

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

Clock Generator

LA-4131P

1

of

16 53Monday, February 18, 2008

0.2