COMPAL LA-4131P Schematics

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1 1

B

C

D

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Compal Confidential

Schematic Document

Crestline + ICH8M

2008 / 02 / 18

3 3

Rev:0.3

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2007/12/28 2007/12/28

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

D

Date: Sheet

Compal Electronics, Inc.

Cover Sheet

LA-4131P

E

153Monday, February 18, 2008

0.2

of

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B

C

D

E

Compal Confidential

Project Code: ANRJAL6000 (JAL60)
File Name : LA-4131P

ZZZ1

1 1

PCB

CRT

P15

LVDS Panel Interface

P15

nVidia

GDDR3 x 4

2 2

NB8P-SE

CardBus Controller

O2 OZ129

P25

Media Card

PCIE4 PCIE3PCIE5

10/100/1000 LAN

REALTEK
RTL8111C-GR

3 3

P22

Mini Card-1
(WLAN)

1394

Mini Card-2

P27 P27

(Robson)

RJ45 CONN

P22

JAL60 UMA / Discrete

Thermal Sensor
ADM1032ARMZ

P4

Fan conn

PCI-E x16

P34 ~ 38P39 , 40

PCI

Express Card

P26

PCI-E x1

P4

Intel Crestline MCH

DMI x4

PCIE2

Mobile Merom

uFCPGA-478 CPU

H_A#(3..35)
H_D#(0..63)

FCBGA 1299

P7, 8, 9, 10, 11, 12

Intel ICH8M

mBGA-676

P17, 18, 19, 20

LPC BUS

P4, 5, 6

FSB

667/800MHz 1.05V

C-Link

USB2.0

Azalia

SATA0
SATA1
PATA

Option

TPM1.2

DDR2 667MHz 1.8V

Dual Channel

P28

CK505

TSSOP-64

Clock Generator
ICS 9LPRS365

P16

DDR2-SO-DIMM X2

BANK 0, 1, 2, 3

USB0

P13, 14

Finger Printer

USB1

Blue Tooth

USB2,3

JUSBP5 Conn.

USB4

JUSBP1 Conn.

USB5

USB Hub

USB6

JUSBP4 Conn.

USB7

Express Card

USB8

JUSBP3 Conn.

USB9

JUSBP2 Conn.

P31

P31

P30

P30

P31

P30

P26

P30

P30

Camera

Felica

P31

P31

Audio CKT
ALC268

P23

AMP & Audio Jack

P24

ENE KB926

P28

Power On/Off CKT.

P29

4 4

DC/DC Interface CKT.

Power Circuit DC/DC

P41~48

A

RTC CKT.

P18P32

Power OK CKT.

P29

B

Touch Pad Conn Int.KBD

P29 P29

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

BIOS (System/EC)

2007/12/28 2007/12/28

C

P28

Compal Secret Data

Deciphered Date

D

SATA HDD1 Conn.

SATA HDD2 Conn.

ODD Conn.

Custom

Date: Sheet

P21

P21

P21

Title

Block Diagram

Size Document Number Rev

LA-4131P

Compal Electronics, Inc.

of

253Monday, February 18, 2008

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0.2

A

Voltage Rails

1 1

2 2

State

S0

S3

S5 S4/AC

S5 S4/ Battery only

S5 S4/AC & Battery
don't exist

O MEANS ON X MEANS OFF

Power
plane

+B

O

O
O
O

X

+5VALW
+3VALW

+1.8V

O

O
O

X

O

XX
X

XXX

+5VS
+3VS
+1.8VS
+1.5VS
+1.25VS
+1.2VS
+0.9VS
+CPU_CORE
+VGA_CORE
+VCCP

OO

X

X

B

CLOCK

C

STATE

Full ON

S1(Power On Suspend)

S3 (Suspend to RAM)

S4 (Suspend to Disk)

S5 (Soft OFF)

SIGNAL

SLP_S1# SLP_S3#

HIGH HIGH HIGH HIGH

LOW

LOW

LOW LOW LOW LOW

SLP_S4# SLP_S5# +VALW +V +VS Clock

HIGH

LOW

LOWLOWLOW

HIGHHIGHHIGH

HIGH

HIGH

D

ON

ON

ON

OFF

OFF

ON ON

ON

OFF

OFF

OFF

LOW

OFF

OFF

OFF

ON

ON

ON

ON

ON

E

Board ID Table for AD channel

O

O
O

X
X

Vcc 3.3V +/- 5%

Board ID

0
1
2
3
4
5
6

100K +/- 5%Ra / Rc

Rb / Rd V min

0

8.2K +/- 5%
18K +/- 5%
33K +/- 5%
56K +/- 5%
100K +/- 5%
200K +/- 5%

7 NC

AD_BID

0 V

V typ

AD_BID

0 V 0 V

V

AD_BID

max

0.216 V 0.250 V 0.289 V

0.436 V

0.712 V

1.036 V

0.503 V

0.819 V

0.538 V

0.875 V

1.185 V 1.264 V

1.453 V 1.650 V 1.759 V

1.935 V

2.500 V

2.200 V

3.300 V

2.341 V

3.300 V

O MEANS ON

X MEANS OFF

S3 : STR
S4 : STD
S5 : SOFT OFF

External PCI Devices

Device IDSEL# REQ#/GNT# Interrupts

CardBus

AD21

0

PIRQG

BOARD ID Table

Board ID

0
1
2
3
4
5

PCB Revision

0.1

BTO Item BOM Structure

BTO Option Table

6
7

3 3

EC SM Bus1 address

Device

Smart Battery
EEPROM(24C16/02)

(24C04)

Address Address

1010 000X b?
1011 000Xb?

EC SM Bus2 address

Device

EMC1402-1-ACZL-TR_MSOP8

4C0001 011X b?

for CPU Thermal Sensor

ICH8 SM Bus address

Device

Clock Generator
(ICS ICS9LPR365)

DDRII DIMM1
DDRII DIMM2

4 4

Address

1101 001Xb?

1001 000Xb?
1001 010Xb?

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2007/12/28 2007/12/28

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

D

Date: Sheet

Compal Electronics, Inc.

Notes

LA-4131P

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1

XDP Reserve

H_A#[3..16]7

H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10

H_ADSTB#0
H_REQ#0

H_REQ#1
H_REQ#2

H_REQ#4

R70
56_0402_5%

@

C

H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16

H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35
H_ADSTB#1

H_A20M#
H_FERR#
H_IGNNE#

H_STPCLK#
H_INTR
H_NMI
H_SMI#

OCP# 19

D D

H_ADSTB#07

H_REQ#07
H_REQ#17
H_REQ#27
H_REQ#37
H_REQ#47
H_A#[17..35]7

C C

B B

H_ADSTB#17
H_A20M#18

H_FERR#18
H_IGNNE#18

H_STPCLK#18
H_INTR18
H_NMI18
H_SMI#18

+VCCP

12

B

2

H_PROCHOT# OCP#

E

3 1

Q10
MMBT3904_SOT23

@

Thermal Sensor ADM1032ARMZ

+3VS

1

C113

0.1U_0402_10V6K

A A

2200P_0402_50V7K

+3VS

C123

1 2

R69

1 2

10K_0402_5%

5

2

H_THERMDA
H_THERMDC

THERM#

JP1A

J4

ADDR GROUP 0 ADDR GROUP 1

A[3]#

L5

A[4]#

L4

A[5]#

K5

A[6]#

M3

A[7]#

N2

A[8]#

J1

A[9]#

N3

A[10]#

P5

A[11]#

P2

A[12]#

L2

A[13]#

P4

A[14]#

P1

A[15]#

R1

A[16]#

M1

ADSTB[0]#

K3

REQ[0]#

H2

REQ[1]#

K2

REQ[2]#

J3

REQ[3]#

L1

REQ[4]#

Y2

A[17]#

U5

A[18]#

R3

A[19]#

W6

A[20]#

U4

A[21]#

Y5

A[22]#

U1

A[23]#

R4

A[24]#

T5

A[25]#

T3

A[26]#

W2

A[27]#

W5

A[28]#

Y4

A[29]#
A[30]#
A[31]#
A[32]#
A[33]#
A[34]#
A[35]#
ADSTB[1]#

A20M#
FERR#
IGNNE#

STPCLK#
LINT0
LINT1
SMI#

RSVD[01]
RSVD[02]
RSVD[03]
RSVD[04]
RSVD[05]
RSVD[06]
RSVD[07]
RSVD[08]
RSVD[09]
RSVD[10]

ALERT#

ICH

SCLK

SDATA

XDP/ITP SIGNALS

THERMAL

PROCHOT#

THERMDA
THERMDC

THERMTRIP#

H CLK

RESERVED

EC_SMB_CK228,29,34
EC_SMB_DA228,29,34

U2
V4

W3
AA4
AB2
AA3

V1
A6

A5
C4

D5
C6
B4
A3

M4

N5
T2
V3
B2
C3
D2

D22

D3
F6

Merom Ball-out Rev 1a

U2

1

VDD

2

D+

3

D­THERM#4GND

EMC1402-1-ACZL-TR_MSOP8

Address:100_1100 (4C)

ADS#
BNR#
BPRI#

DEFER#

DRDY#
DBSY#

BR0#

IERR#

INIT#

LOCK#

CONTROL

RESET#

RS[0]#
RS[1]#
RS[2]#

TRDY#

HIT#

HITM#

BPM[0]#
BPM[1]#
BPM[2]#
BPM[3]#

PRDY#
PREQ#

TCK

TDI
TDO
TMS

TRST#

DBR#

BCLK[0]
BCLK[1]

CONN@

EC_SMB_CK2

8

EC_SMB_DA2

7

THERM_SCI#

6
5

H_ADS#H_A#3

H1

H_BNR#

E2

H_BPRI#

G5

H_DEFER#

H5

H_DRDY#

F21

H_DBSY#

E1

H_BR0#

F1

H_IERR#

D20

H_INIT#

B3

H_LOCK#

H4

H_RESET#

C1

H_RS#0

F3

H_RS#1

F4

H_RS#2

G3

H_TRDY#H_REQ#3

G2

H_HIT#

G6

H_HITM#

E4
AD4

AD3
AD1
AC4
AC2
AC1

XDP_TCK

AC5

XDP_TDI

AA6
AB3

XDP_TMS

AB5

XDP_TRST#

AB6

XDP_DBRESET#

C20

H_PROCHOT#

D21

H_THERMDA

A24

H_THERMDC

B25

H_THERMTRIP#

C7

CLK_CPU_BCLK

A22

CLK_CPU_BCLK#

A21

H_THERMDA, H_THERMDC routing together,
Trace width / Spacing = 10 / 10 mil

H_THRMTRIP# should connect
to ICH8 and GMCH without
T-ing (No stub)

12

R64
10K_0402_5%

@

12

R65
0_0402_5%

@

EC_SMB_CK2
EC_SMB_DA2

4

H_ADS# 7
H_BNR# 7
H_BPRI# 7

H_DEFER# 7
H_DRDY# 7
H_DBSY# 7

H_BR0# 7

H_INIT# 18
H_LOCK# 7
H_RESET# 7

H_RS#0 7
H_RS#1 7
H_RS#2 7
H_TRDY# 7

H_HIT# 7
H_HITM# 7

XDP_DBRESET# 19

1 2

R79 56_0402_1%

H_THERMTRIP# 7,18

CLK_CPU_BCLK 16
CLK_CPU_BCLK# 16

EC_THERM# 19,28

R78

56_0402_5%

Add on 1003

12

+VCCP

PROCHOT# is not used ---> 56 ohms pull-up
CRB uses 1K ohms pull-up resistor to fix

+VCCP

PROCHOT# failure when driven by a thermal sensor.

Fan Control and Tachometer

EN_DFAN128

FAN_SPEED128

0.01U_0402_16V7K

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2007/12/28 2007/12/28

Compal Secret Data

Deciphered Date

+VCCP

XDP_TDI
XDP_TMS

XDP_TRST#
XDP_TCK

C75

10U_1206_16V4Z~N

C77

1000P_0402_50V7K~N

EN_DFAN1

+3VS

12

R381

10K_0402_5%

2

C529

1

2

FAN1_POWER

Title

Merom(1/3)_AGTL+ / XDP

Size Document Number Rev

Custom

LA-4131P

Date: Sheet

R442 150_0402_1%

1 2

R446 39_0402_1%

1 2

R443 560_0402_5%

1 2

R447 27_0402_1%

1 2

12

+5VS

12

40mil

1 2

C88 10U_1206_16V4Z~N
U1

1

VEN

2
3
4

1
2
3

4
5

ACES_85205-03001

CONN@

GND

VIN

GND
GND

VO

GND

VSET

APL5605KI-TRL SOP 8P

JFAN1

1
2
3

GND
GND

Compal Electronics, Inc.

1

8
7
6
5

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453Monday, February 18, 2008

5

4

3

2

1

H_D#[0..15]7

D D

H_DSTBN#07
H_DSTBP#07
H_DINV#07
H_D#[16..31]7

C C

H_DSTBN#17
H_DSTBP#17
H_DINV#17

R80 1K_0402_5%@

1 2

R77 1K_0402_5%@

1 2

CPU_BSEL016
CPU_BSEL116
CPU_BSEL216

T2
T4
T47
T3

H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_DSTBN#0
H_DSTBP#0
H_DINV#0

H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_DSTBN#1
H_DSTBP#1
H_DINV#1 H_DINV#3

V_CPU_GTLREF

TEST1
TEST2
TEST3
TEST4
TEST5
TEST6

CPU_BSEL0
CPU_BSEL1
CPU_BSEL2

JP1B

E22

D[0]#

F24

D[1]#

E26

D[2]#

G22

D[3]#

F23

D[4]#

G25

D[5]#

E25

D[6]#

E23

D[7]#

K24

D[8]#

G24

D[9]#

J24

D[10]#

J23

D[11]#

H22

D[12]#

F26

D[13]#

K22

D[14]#

H23

D[15]#

J26

DSTBN[0]#

H26

DSTBP[0]#

H25

DINV[0]#

N22

D[16]#

K25

D[17]#

P26

D[18]#

R23

D[19]#

L23

D[20]#

M24

D[21]#

L22

D[22]#

M23

D[23]#

P25

D[24]#

P23

D[25]#

P22

D[26]#

T24

D[27]#

R24

D[28]#

L25

D[29]#

T25

D[30]#

N25

D[31]#

L26

DSTBN[1]#

M26

DSTBP[1]#

N24

DINV[1]#

AD26

GTLREF

C23

TEST1

D25

TEST2

C24

TEST3

AF26

TEST4

AF1

TEST5

A26

TEST6

B22

BSEL[0]

B23

BSEL[1]

C21

BSEL[2]

Merom Ball-out Rev 1a

CONN@

DATA GRP 0

DATA GRP 2DATA GRP 3

DSTBN[2]#
DSTBP[2]#

DINV[2]#

DATA GRP 1

DSTBN[3]#
DSTBP[3]#

DINV[3]#
COMP[0]

MISC

COMP[1]
COMP[2]
COMP[3]

DPRSTP#

PWRGOOD

D[32]#
D[33]#
D[34]#
D[35]#
D[36]#
D[37]#
D[38]#
D[39]#
D[40]#
D[41]#
D[42]#
D[43]#
D[44]#
D[45]#
D[46]#
D[47]#

D[48]#
D[49]#
D[50]#
D[51]#
D[52]#
D[53]#
D[54]#
D[55]#
D[56]#
D[57]#
D[58]#
D[59]#
D[60]#
D[61]#
D[62]#
D[63]#

DPSLP#

DPWR#

SLP#

PSI#

Y22
AB24
V24
V26
V23
T22
U25
U23
Y25
W22
Y23
W24
W25
AA23
AA24
AB25
Y26
AA26
U22

AE24
AD24
AA21
AB22
AB21
AC26
AD20
AE22
AF23
AC25
AE21
AD21
AC22
AD23
AF22
AC23
AE25
AF24
AC20

R26
U26
AA1
Y1

E5
B5
D24
D6
D7
AE6

H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_DSTBN#2
H_DSTBP#2
H_DINV#2

H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
H_DSTBN#3
H_DSTBP#3

COMP0
COMP1
COMP2
COMP3

H_DPRSTP#
H_DPSLP#
H_DPWR#
H_PWRGOOD
H_CPUSLP#
H_PSI#

layout note: Route TEST3 & TEST5 traces on ground referenced layer to the TPs

CPU_BSEL CPU_BSEL2 CPU_BSEL1

166

B B

200

01

0

1

CPU_BSEL0

1

0

H_D#[32..47] 7

H_DSTBN#2 7
H_DSTBP#2 7
H_DINV#2 7
H_D#[48..63] 7

H_DSTBN#3 7
H_DSTBP#3 7
H_DINV#3 7

H_DPRSTP# 7,18,48
H_DPSLP# 18

H_DPWR# 7

H_PWRGOOD 18
H_CPUSLP# 7

H_PSI# 48

12

R445

27.4_0402_1%

12

R75

54.9_0402_1%

12

R76

27.4_0402_1%

12

R444

54.9_0402_1%

Resistor placed within

0.5" of CPU pin.Trace
should be at least 25
mils away from any other
toggling signal.
COMP[0,2] trace width is
18 mils. COMP[1,3] trace
width is 4 mils.

+CPU_CORE +CPU_CORE

JP1C

A7

VCC[001]

A9

VCC[002]

A10

VCC[003]

A12

VCC[004]

A13

VCC[005]

A15

VCC[006]

A17

VCC[007]

A18

VCC[008]

A20

VCC[009]

B7

VCC[010]

B9

VCC[011]

B10

VCC[012]

B12

VCC[013]

B14

VCC[014]

B15

VCC[015]

B17

VCC[016]

B18

VCC[017]

B20

VCC[018]

C9

VCC[019]

C10

VCC[020]

C12

VCC[021]

C13

VCC[022]

C15

VCC[023]

C17

VCC[024]

C18

VCC[025]

D9

VCC[026]

D10

VCC[027]

D12

VCC[028]

D14

VCC[029]

D15

VCC[030]

D17

VCC[031]

D18

VCC[032]

E7

VCC[033]

E9

VCC[034]

E10

VCC[035]

E12

VCC[036]

E13

VCC[037]

E15

VCC[038]

E17

VCC[039]

E18

VCC[040]

E20

VCC[041]

F7

VCC[042]

F9

VCC[043]

F10

VCC[044]

F12

VCC[045]

F14

VCC[046]

F15

VCC[047]

F17

VCC[048]

F18

VCC[049]

F20

VCC[050]

AA7

VCC[051]

AA9

VCC[052]

AA10

VCC[053]

AA12

VCC[054]

AA13

VCC[055]

AA15

VCC[056]

AA17

VCC[057]

AA18

VCC[058]

AA20

VCC[059]

AB9

VCC[060]

AC10

VCC[061]

AB10

VCC[062]

AB12

VCC[063]

AB14

VCC[064]

AB15

VCC[065]

AB17

VCC[066]

AB18

VCC[067]

Merom Ball-out Rev 1a

CONN@

VCC[068]
VCC[069]
VCC[070]
VCC[071]
VCC[072]
VCC[073]
VCC[074]
VCC[075]
VCC[076]
VCC[077]
VCC[078]
VCC[079]
VCC[080]
VCC[081]
VCC[082]
VCC[083]
VCC[084]
VCC[085]
VCC[086]
VCC[087]
VCC[088]
VCC[089]
VCC[090]
VCC[091]
VCC[092]
VCC[093]
VCC[094]
VCC[095]
VCC[096]
VCC[097]
VCC[098]
VCC[099]
VCC[100]

VCCP[01]
VCCP[02]
VCCP[03]
VCCP[04]
VCCP[05]
VCCP[06]
VCCP[07]
VCCP[08]
VCCP[09]
VCCP[10]
VCCP[11]
VCCP[12]
VCCP[13]
VCCP[14]
VCCP[15]
VCCP[16]

VCCA[01]
VCCA[02]

VID[0]
VID[1]
VID[2]
VID[3]
VID[4]
VID[5]
VID[6]

VCCSENSE

VSSSENSE

AB20
AB7
AC7
AC9
AC12
AC13
AC15
AC17
AC18
AD7
AD9
AD10
AD12
AD14
AD15
AD17
AD18
AE9
AE10
AE12
AE13
AE15
AE17
AE18
AE20
AF9
AF10
AF12
AF14
AF15
AF17
AF18
AF20

G21
V6
J6
K6
M6
J21
K21
M21
N21
N6
R21
R6
T21
T6
V21
W21

B26
C26

AD6
AF5
AE5
AF4
AE3
AF3
AE2

VCCSENSE

AF7

VSSSENSE

AE7

.

Length match within 25 mils.

+VCCP

1

+

C312
330U_D2_2.5VY_R9M

@

2

CPU_VID0 48
CPU_VID1 48
CPU_VID2 48
CPU_VID3 48
CPU_VID4 48
CPU_VID5 48
CPU_VID6 48

VCCSENSE 48

VSSSENSE 48

C118

1

C121

2

10U_0805_10V4Z~N

+1.5VS

1

2

0.01U_0402_16V7K

Near pin B26

The trace width/space/other is
20/7/25.

+CPU_CORE

R98
100_0402_1%

1 2

R101
100_0402_1%

1 2

VCCSENSE

VSSSENSE

V_CPU_GTLREF

+VCCP

12

R73
1K_0402_1%

12

R74
2K_0402_1%

Close to CPU pin AD26
within 500mils.

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2007/12/28 2007/12/28

Compal Secret Data

Deciphered Date

2

Close to CPU pin
within 500mils.

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

Merom(2/3)_AGTL+ / PWR

LA-4131P

1

of

553Monday, February 18, 2008

0.2

5

High Frequence Decoupling

D D

C C

B B

JP1D

A4

VSS[001]

A8

VSS[002]

A11

VSS[003]

A14

VSS[004]

A16

VSS[005]

A19

VSS[006]

A23

VSS[007]

AF2

VSS[008]

B6

VSS[009]

B8

VSS[010]

B11

VSS[011]

B13

VSS[012]

B16

VSS[013]

B19

VSS[014]

B21

VSS[015]

B24

VSS[016]

C5

VSS[017]

C8

VSS[018]

C11

VSS[019]

C14

VSS[020]

C16

VSS[021]

C19

VSS[022]

C2

VSS[023]

C22

VSS[024]

C25

VSS[025]

D1

VSS[026]

D4

VSS[027]

D8

VSS[028]

D11

VSS[029]

D13

VSS[030]

D16

VSS[031]

D19

VSS[032]

D23

VSS[033]

D26

VSS[034]

E3

VSS[035]

E6

VSS[036]

E8

VSS[037]

E11

VSS[038]

E14

VSS[039]

E16

VSS[040]

E19

VSS[041]

E21

VSS[042]

E24

VSS[043]

F5

VSS[044]

F8

VSS[045]

F11

VSS[046]

F13

VSS[047]

F16

VSS[048]

F19

VSS[049]

F2

VSS[050]

F22

VSS[051]

F25

VSS[052]

G4

VSS[053]

G1

VSS[054]

G23

VSS[055]

G26

VSS[056]

H3

VSS[057]

H6

VSS[058]

H21

VSS[059]

H24

VSS[060]

J2

VSS[061]

J5

VSS[062]

J22

VSS[063]

J25

VSS[064]

K1

VSS[065]

K4

VSS[066]

K23

VSS[067]

K26

VSS[068]

L3

VSS[069]

L6

VSS[070]

L21

VSS[071]

L24

VSS[072]

M2

VSS[073]

M5

VSS[074]

M22

VSS[075]

M25

VSS[076]

N1

VSS[077]

N4

VSS[078]

N23

VSS[079]

N26

VSS[080]
VSS[081]P3VSS[162]

Merom Ball-out Rev 1a

CONN@

VSS[082]
VSS[083]
VSS[084]
VSS[085]
VSS[086]
VSS[087]
VSS[088]
VSS[089]
VSS[090]
VSS[091]
VSS[092]
VSS[093]
VSS[094]
VSS[095]
VSS[096]
VSS[097]
VSS[098]
VSS[099]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
VSS[159]
VSS[160]
VSS[161]

VSS[163]

P6
P21
P24
R2
R5
R22
R25
T1
T4
T23
T26
U3
U6
U21
U24
V2
V5
V22
V25
W1
W4
W23
W26
Y3
Y6
Y21
Y24
AA2
AA5
AA8
AA11
AA14
AA16
AA19
AA22
AA25
AB1
AB4
AB8
AB11
AB13
AB16
AB19
AB23
AB26
AC3
AC6
AC8
AC11
AC14
AC16
AC19
AC21
AC24
AD2
AD5
AD8
AD11
AD13
AD16
AD19
AD22
AD25
AE1
AE4
AE8
AE11
AE14
AE16
AE19
AE23
AE26
A2
AF6
AF8
AF11
AF13
AF16
AF19
AF21
A25
AF25

.

10uF 0805 X5R -> 85 degree.

Place these caps inside
the CPU socket cavity.

( Left side on Top ).

Place these caps inside
the CPU socket cavity.

( Right side on Top side).

Place these caps inside
the CPU socket cavity.

( Left side on Bottom ).

Place these caps inside
the CPU socket cavity.

( Right side on Bottom ).

Place these caps inside
the CPU socket.

( Left side on Top ). ( Right side on Top side).

220U_D2_4VY_R15M

4

+CPU_CORE

1

2

+CPU_CORE

1

2

+CPU_CORE

1

2

+CPU_CORE

1

2

+CPU_CORE

1

C193

+

2

+VCCP

1

+

C109

2

C182
10U_0805_4VAM~D

C238
10U_0805_4VAM~D

C601
10U_0805_4VAM~D

C604
10U_0805_4VAM~D

330U_D2E_2.5VM_R9

1

C219

+

2

1

2

1

C181
10U_0805_4VAM~D

2

1

C237
10U_0805_4VAM~D

2

1

C239
10U_0805_4VAM~D

2

1

C574
10U_0805_4VAM~D

2

330U_D2E_2.5VM_R9

C164

0.1U_0402_10V6K

1

C598
10U_0805_4VAM~D

2

1

C217
10U_0805_4VAM~D

2

1

C572
10U_0805_4VAM~D

2

1

C577
10U_0805_4VAM~D

2

330U_D2E_2.5VM_R9

Place these caps inside

1

C579

the CPU socket.

+

2

1

C260

0.1U_0402_10V6K

2

3

1

2

1

2

1

2

1

2

1

C259

0.1U_0402_10V6K

2

C180
10U_0805_4VAM~D

C208
10U_0805_4VAM~D

C602
10U_0805_4VAM~D

C573
10U_0805_4VAM~D

1

2

1

C185
10U_0805_4VAM~D

2

1

C218
10U_0805_4VAM~D

2

1

C179
10U_0805_4VAM~D

2

1

C575
10U_0805_4VAM~D

2

1

C599
10U_0805_4VAM~D

2

1

C207
10U_0805_4VAM~D

2

1

C576
10U_0805_4VAM~D

2

1

C571
10U_0805_4VAM~D

2

ESR <= 1.5m ohm
Capacitor > 880 uF

C115

0.1U_0402_10V6K

1

C120

0.1U_0402_10V6K

2

2

1

C184
10U_0805_4VAM~D

2

1

C600
10U_0805_4VAM~D

2

1

C165

0.1U_0402_10V6K

2

1

C183
10U_0805_4VAM~D

2

1

C236
10U_0805_4VAM~D

2

Place these inside
socket cavity on L8
(North side
Secondary)

1

C233
10U_0805_4VAM~D

2

1

C234
10U_0805_4VAM~D

2

1

Place these caps inside
the CPU socket.

1

( Left side on Top ).

C235
10U_0805_4VAM~D

2

Place these caps inside
the CPU socket.

1

( Right side on Top ).

C603
10U_0805_4VAM~D

2

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2007/12/28 2007/12/28

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

Compal Electronics, Inc.

Merom(3/3)_GND / Bypass

LA-4131P

1

0.2

of

653Monday, February 18, 2008

5

H_D#[0..63]5

D D

C C

+VCCP

12

12

R93

R92

54.9_0402_1%

54.9_0402_1%

H_RESET#4
H_CPUSLP#5

B B

H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57

H_D#59
H_D#60
H_D#61
H_D#62
H_D#63

H_SWNG
H_RCOMP

H_SCOMP
H_SCOMP#

H_RESET#
H_CPUSLP#

H_VREF

U3A

E2

H_D#_0

G2

H_D#_1

G7

H_D#_2

M6

H_D#_3

H7

H_D#_4

H3

H_D#_5

G4

H_D#_6

F3

H_D#_7

N8

H_D#_8

H2

H_D#_9

M10

H_D#_10

N12

H_D#_11

N9

H_D#_12

H5

H_D#_13

P13

H_D#_14

K9

H_D#_15

M2

H_D#_16

W10

H_D#_17

Y8

H_D#_18

V4

H_D#_19

M3

H_D#_20

J1

H_D#_21

N5

H_D#_22

N3

H_D#_23

W6

H_D#_24

W9

H_D#_25

N2

H_D#_26

Y7

H_D#_27

Y9

H_D#_28

P4

H_D#_29

W3

H_D#_30

N1

H_D#_31

AD12

H_D#_32

AE3

H_D#_33

AD9

H_D#_34

AC9

H_D#_35

AC7

H_D#_36

AC14

H_D#_37

AD11

H_D#_38

AC11

H_D#_39

AB2

H_D#_40

AD7

H_D#_41

AB1

H_D#_42

Y3

H_D#_43

AC6

H_D#_44

AE2

H_D#_45

AC5

H_D#_46

AG3

H_D#_47

AJ9

H_D#_48

AH8

H_D#_49

AJ14

H_D#_50

AE9

H_D#_51

AE11

H_D#_52

AH12

H_D#_53

AJ5

H_D#_54

AH5

H_D#_55

AJ6

H_D#_56

AE7

H_D#_57

AJ7

H_D#_58

AJ2

H_D#_59

AE5

H_D#_60

AJ3

H_D#_61

AH2

H_D#_62

AH13

H_D#_63

B3

H_SWING

C2

H_RCOMP

W1

H_SCOMP

W2

H_SCOMP#

B6

H_CPURST#

E5

H_CPUSLP#

B9

H_AVREF

A9

H_DVREF

CRESTLINE_1p0 UMA@

HOST

H_ADSTB#_0
H_ADSTB#_1

H_BREQ#

H_DEFER#

H_DBSY#

HPLL_CLK

HPLL_CLK#

H_DPWR#

H_DRDY#

H_LOCK#
H_TRDY#

H_DINV#_0
H_DINV#_1
H_DINV#_2
H_DINV#_3

H_DSTBN#_0
H_DSTBN#_1
H_DSTBN#_2
H_DSTBN#_3

H_DSTBP#_0
H_DSTBP#_1
H_DSTBP#_2
H_DSTBP#_3

H_REQ#_0
H_REQ#_1
H_REQ#_2
H_REQ#_3
H_REQ#_4

layout note:
Route H_SCOMP and H_SCOMP# with trace width, spacing and impedance (55 ohm) same as FSB data traces.

Layout Note:
H_RCOMP / H_VREF / H_SWNG

trace width and spacing is 10/20

+VCCP

R441

12

R464
221_0402_1%

12

100_0402_1%

H_SWNGH_VREF

1

C622

2

0.1U_0402_16V4Z~N

+VCCP

12

R450

1K_0402_1%

0.1U_0402_16V4Z~N

12

A A

R440

C620

2K_0402_1%

1

2

12

R424

24.9_0402_1%

H_RCOMP

Near B3 pinwithin 100 mils from NB

5

H_A#_3
H_A#_4
H_A#_5
H_A#_6
H_A#_7
H_A#_8

H_A#_9
H_A#_10
H_A#_11
H_A#_12
H_A#_13
H_A#_14
H_A#_15
H_A#_16
H_A#_17
H_A#_18
H_A#_19
H_A#_20
H_A#_21
H_A#_22
H_A#_23
H_A#_24
H_A#_25
H_A#_26
H_A#_27
H_A#_28
H_A#_29
H_A#_30
H_A#_31
H_A#_32
H_A#_33
H_A#_34
H_A#_35

H_ADS#

H_BNR#

H_BPRI#

H_HIT#
H_HITM#

H_RS#_0
H_RS#_1
H_RS#_2

J13
B11
C11
M11
C15
F16
L13
G17
C14
K16
B13
L16
J17
B14
K19
P15
R17
B16
H20
L19
D17
M17
N16
J19
B18
E19
B17
B15
E17
C18
A19
B19
N19

G12
H17
G20
C8
E8
F12
D6
C10
AM5
AM7
H8
K7
E4
C6
G10
B7

K5
L2
AD13
AE13

M7
K3
AD2
AH11

L7
K2
AC2
AJ10

M14
E13
A11
H13
B12

E12
D7
D8

4

4

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35

H_ADS#
H_ADSTB#0
H_ADSTB#1
H_BNR#
H_BPRI#
H_BR0#
H_DEFER#
H_DBSY#
CLK_MCH_BCLK
CLK_MCH_BCLK#
H_DPWR#
H_DRDY#
H_HIT#
H_HITM#
H_LOCK#
H_TRDY#

H_DINV#0
H_DINV#1
H_DINV#2
H_DINV#3

H_DSTBN#0H_D#58
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3

H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

H_RS#0
H_RS#1
H_RS#2

H_A#[3..35] 4

H_ADS# 4
H_ADSTB#0 4
H_ADSTB#1 4
H_BNR# 4
H_BPRI# 4
H_BR0# 4
H_DEFER# 4
H_DBSY# 4
CLK_MCH_BCLK 16
CLK_MCH_BCLK# 16
H_DPWR# 5
H_DRDY# 4
H_HIT# 4
H_HITM# 4
H_LOCK# 4
H_TRDY# 4

H_DINV#0 5
H_DINV#1 5
H_DINV#2 5
H_DINV#3 5

H_DSTBN#0 5
H_DSTBN#1 5
H_DSTBN#2 5
H_DSTBN#3 5

H_DSTBP#0 5
H_DSTBP#1 5
H_DSTBP#2 5
H_DSTBP#3 5

H_REQ#0 4
H_REQ#1 4
H_REQ#2 4
H_REQ#3 4
H_REQ#4 4

H_RS#0 4
H_RS#1 4
H_RS#2 4

PM_PWROK19,28

PLT_RST#17,19,21,22,26,27,28,31,34

3

+1.8V

2

2

12

C543

C544

1

0.01U_0402_25V7K~D

1

2

0.01U_0402_25V7K~D

MCH_CLKSEL016
MCH_CLKSEL116
MCH_CLKSEL216

12

3

R399
1K_0402_1%

12

R397

3.01K_0402_1%

NA lead free

12

R400
1K_0402_1%

DDR_A_MA1413
DDR_B_MA1414

R111

10K_0402_5%

R39

10K_0402_5%

CFG129
CFG139

CFG169

PM_BMBUSY#19

H_DPRSTP#5,18,48
PM_EXTTS#013
PM_EXTTS#114

R108 0_0402_5%

DPRSLPVR19,48

PM_POK_R

+3VS

12

12

MCH_CLKSEL0
MCH_CLKSEL1
MCH_CLKSEL2

T14PAD
T15PAD

T7PAD
T12PAD

CFG99

CFG9

T10PAD
T8PAD

CFG12
CFG13

T13PAD
T9PAD

CFG16

T6PAD
T11PAD

PM_BMBUSY#
H_DPRSTP#
PM_EXTTS#0
PM_EXTTS#1
PM_POK_R
PLT_RST#_R
THERMTRIP#

12

DPRSLPVR

2007/12/28 2007/12/28

1

2.2U_0603_106K

SMRCOMP_VOH

SMRCOMP_VOL

C540

1

2

C541

2.2U_0603_106K

PM_EXTTS#0

PM_EXTTS#1

H_THERMTRIP#4,18

R83 0_0402_5%

PLT_RST# PLT_RST#_R

1 2

R85 100_0402_5%

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

U3B

P36

RSVD1

P37

RSVD2

R35

RSVD3

N35

RSVD4

AR12

RSVD5

AR13

RSVD6

AM12

RSVD7

AN13

RSVD8

J12

RSVD9

AR37

RSVD10

AM36

RSVD11

AL36

RSVD12

AM37

RSVD13

D20

RSVD14

H10

RSVD20

B51

RSVD21

BJ20

RSVD22

BK22

RSVD23

BF19

RSVD24

BH20

RSVD25

BK18

RSVD26

BJ18

RSVD27

BF23

RSVD28

BG23

RSVD29

BC23

RSVD30

BD24

RSVD31

BJ29

RSVD32

BE24

RSVD33

BH39

RSVD34

AW20

RSVD35

BK20

RSVD36

C48

RSVD37

D47

RSVD38

B44

RSVD39

C44

RSVD40

A35

RSVD41

B37

RSVD42

B36

RSVD43

B34

RSVD44

C34

RSVD45

P27

CFG_0

N27

CFG_1

N24

CFG_2

C21

CFG_3

C23

CFG_4

F23

CFG_5

N23

CFG_6

G23

CFG_7

J20

CFG_8

C20

CFG_9

R24

CFG_10

L23

CFG_11

J23

CFG_12

E23

CFG_13

E20

CFG_14

K23

CFG_15

M20

CFG_16

M24

CFG_17

L32

CFG_18

N33

CFG_19

L35

CFG_20

G41

PM_BM_BUSY#

L39

PM_DPRSTP#

L36

PM_EXT_TS#_0

J36

PM_EXT_TS#_1

AW49

PWROK

AV20

RSTIN#

N20

THERMTRIP#

G36

DPRSLPVR

BJ51

NC_1

BK51

NC_2

BK50

NC_3

BL50

NC_4

BL49

NC_5

BL3

NC_6

BL2

NC_7

BK1

NC_8

BJ1

NC_9

E1

NC_10

A5

NC_11

C51

NC_12

B50

NC_13

A50

NC_14

A49

NC_15

BK2

NC_16

CRESTLINE_1p0 UMA@

Compal Secret Data

Deciphered Date

2

CFGRSVD

PM

NC

2

AV29

SM_CK_0

BB23

SM_CK_1

BA25

SM_CK_3

AV23

SM_CK_4

AW30

SM_CK#_0

BA23

SM_CK#_1

AW25

SM_CK#_3

AW23

SM_CK#_4

BE29

SM_CKE_0

AY32

SM_CKE_1

BD39

SM_CKE_3

BG37

SM_CKE_4

BG20

SM_CS#_0

BK16

SM_CS#_1

BG16

SM_CS#_2

BE13

SM_CS#_3

BH18

SM_ODT_0

BJ15

SM_ODT_1

BJ14

SM_ODT_2

BE16

SM_ODT_3

BL15

SM_RCOMP

SM_VREF_0
SM_VREF_1

PEG_CLK

PEG_CLK#

DMI_RXN_0
DMI_RXN_1
DMI_RXN_2
DMI_RXN_3

DMI_RXP_0
DMI_RXP_1
DMI_RXP_2
DMI_RXP_3

DMI_TXN_0
DMI_TXN_1
DMI_TXN_2
DMI_TXN_3

DMI_TXP_0
DMI_TXP_1
DMI_TXP_2
DMI_TXP_3

GFX_VID_0
GFX_VID_1
GFX_VID_2
GFX_VID_3

CL_CLK

CL_DATA

CL_PWROK

CL_RST#
CL_VREF

CLK_REQ#

ICH_SYNC#

TEST_1
TEST_2

BK14
BK31

BL31
AR49

AW4

B42
C42
H48
H47

K44
K45

AN47
AJ38
AN42
AN46

AM47
AJ39
AN41
AN45

AJ46
AJ41
AM40
AM44

AJ47
AJ42
AM39
AM43

E35
A39
C38
B39
E36

AM49
AK50
AT43
AN49
AM50

H35
K36
G39
G40

A37
R32

20K_0402_5%

Custom

SM_RCOMP#

SM_RCOMP_VOH
SM_RCOMP_VOL

DDR MUXINGCLK

DPLL_REF_CLK

DPLL_REF_CLK#

DPLL_REF_SSCLK

DPLL_REF_SSCLK#

DMI

GFX_VR_EN

GRAPHICS VID

ME

SDVO_CTRL_CLK

SDVO_CTRL_DATA

MISC

1

For Crestline: 20ohm

M_CLK_DDR0
M_CLK_DDR1
M_CLK_DDR2
M_CLK_DDR3

M_CLK_DDR#0
M_CLK_DDR#1
M_CLK_DDR#2
M_CLK_DDR#3

DDR_CKE0_DIMMA
DDR_CKE1_DIMMA
DDR_CKE2_DIMMB
DDR_CKE3_DIMMB

DDR_CS0_DIMMA#
DDR_CS1_DIMMA#
DDR_CS2_DIMMB#
DDR_CS3_DIMMB#

M_ODT0
M_ODT1
M_ODT2
M_ODT3

SMRCOMP
SMRCOMP#

SMRCOMP_VOH
SMRCOMP_VOL

+DDR_MCH_REF1

1 2

C171 0.1U_0402_16V4Z~N

CLK_MCH_DREFCLK
CLK_MCH_DREFCLK#
MCH_SSCDREFCLK
MCH_SSCDREFCLK#

CLK_MCH_3GPLL

CLK_MCH_3GPLL#

DMI_TXN0
DMI_TXN1
DMI_TXN2
DMI_TXN3

DMI_TXP0
DMI_TXP1
DMI_TXP2
DMI_TXP3

DMI_RXN0
DMI_RXN1
DMI_RXN2
DMI_RXN3

DMI_RXP0
DMI_RXP1
DMI_RXP2
DMI_RXP3

CL_CLK0
CL_DATA0
M_PWROK
CL_RST#
CL_VREF CL_VREF

CLKMCHREQ#
MCH_ICH_SYNC#

12

R96

Title

Crestline(1/6)_AGTL+/DDR2/DMI

Size Document Number Rev

LA-4131P

Date: Sheet

For Calero: 80.6ohm

M_CLK_DDR0 13
M_CLK_DDR1 13
M_CLK_DDR2 14
M_CLK_DDR3 14

M_CLK_DDR#0 13
M_CLK_DDR#1 13
M_CLK_DDR#2 14
M_CLK_DDR#3 14

DDR_CKE0_DIMMA 13
DDR_CKE1_DIMMA 13
DDR_CKE2_DIMMB 14
DDR_CKE3_DIMMB 14

DDR_CS0_DIMMA# 13
DDR_CS1_DIMMA# 13
DDR_CS2_DIMMB# 14
DDR_CS3_DIMMB# 14

M_ODT0 13
M_ODT1 13
M_ODT2 14
M_ODT3 14

R402 20_0402_1%
R403 20_0402_1%

+DDR_MCH_REF1 13,14

SMVREF = 20 uA

CLK_MCH_DREFCLK 16

CLK_MCH_DREFCLK# 16

MCH_SSCDREFCLK 16

MCH_SSCDREFCLK# 16

CLK_MCH_3GPLL 16
CLK_MCH_3GPLL# 16

DMI_TXN0 19
DMI_TXN1 19
DMI_TXN2 19
DMI_TXN3 19

DMI_TXP0 19
DMI_TXP1 19
DMI_TXP2 19
DMI_TXP3 19

DMI_RXN0 19
DMI_RXN1 19
DMI_RXN2 19
DMI_RXN3 19

DMI_RXP0 19
DMI_RXP1 19
DMI_RXP2 19
DMI_RXP3 19

CLK_MCH_DREFCLK
CLK_MCH_DREFCLK#
MCH_SSCDREFCLK
MCH_SSCDREFCLK#

0.1U_0402_16V4Z~N

R149 0_0402_5%VGA@
R145 0_0402_5%VGA@
R122 0_0402_5%VGA@
R114 0_0402_5%VGA@

CL_CLK0 19
CL_DATA0 19

M_PWROK 19
CL_RST# 19

C568

12 mil

CLKMCHREQ# 16
MCH_ICH_SYNC# 19

Layout Note:
+DDR_MCH_REF1
trace width and
spacing is 20/20.

1

2

Compal Electronics, Inc.

1

12
12

+1.25VM_AXD

12

12

753Monday, February 18, 2008

TTRC= 30 mA

+1.8V

12
12
12
12

R410
1K_0402_1%

R409
392_0402_1%

of

0.2

5

D D

DDR_A_D[0..63]13

C C

B B

DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8

DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63

U3D

AR43

SA_DQ_0

AW44

SA_DQ_1

BA45

SA_DQ_2

AY46

SA_DQ_3

AR41

SA_DQ_4

AR45

SA_DQ_5

AT42

SA_DQ_6

AW47

SA_DQ_7

BB45

SA_DQ_8

BF48

SA_DQ_9

BG47

SA_DQ_10

BJ45

SA_DQ_11

BB47

SA_DQ_12

BG50

SA_DQ_13

BH49

SA_DQ_14

BE45

SA_DQ_15

AW43

SA_DQ_16

BE44

SA_DQ_17

BG42

SA_DQ_18

BE40

SA_DQ_19

BF44

SA_DQ_20

BH45

SA_DQ_21

BG40

SA_DQ_22

BF40

SA_DQ_23

AR40

SA_DQ_24

AW40

SA_DQ_25

AT39

SA_DQ_26

AW36

SA_DQ_27

AW41

SA_DQ_28

AY41

SA_DQ_29

AV38

SA_DQ_30

AT38

SA_DQ_31

AV13

SA_DQ_32

AT13

SA_DQ_33

AW11

SA_DQ_34

AV11

SA_DQ_35

AU15

SA_DQ_36

AT11

SA_DQ_37

BA13

SA_DQ_38

BA11

SA_DQ_39

BE10

SA_DQ_40

BD10

SA_DQ_41

BD8

SA_DQ_42

AY9

SA_DQ_43

BG10

SA_DQ_44

AW9

SA_DQ_45

BD7

SA_DQ_46

BB9

SA_DQ_47

BB5

SA_DQ_48

AY7

SA_DQ_49

AT5

SA_DQ_50

AT7

SA_DQ_51

AY6

SA_DQ_52

BB7

SA_DQ_53

AR5

SA_DQ_54

AR8

SA_DQ_55

AR9

SA_DQ_56

AN3

SA_DQ_57

AM8

SA_DQ_58

AN10

SA_DQ_59

AT9

SA_DQ_60

AN9

SA_DQ_61

AM9

SA_DQ_62

AN11

SA_DQ_63

CRESTLINE_1p0 UMA@

DDR SYSTEM MEMORY A

SA_BS_0
SA_BS_1
SA_BS_2

SA_CAS#

SA_DM_0
SA_DM_1
SA_DM_2
SA_DM_3
SA_DM_4
SA_DM_5
SA_DM_6
SA_DM_7

SA_DQS_0
SA_DQS_1
SA_DQS_2
SA_DQS_3
SA_DQS_4
SA_DQS_5
SA_DQS_6

SA_DQS_7
SA_DQS#_0
SA_DQS#_1
SA_DQS#_2
SA_DQS#_3
SA_DQS#_4
SA_DQS#_5
SA_DQS#_6
SA_DQS#_7

SA_MA_0
SA_MA_1
SA_MA_2
SA_MA_3
SA_MA_4
SA_MA_5
SA_MA_6
SA_MA_7
SA_MA_8

SA_MA_9
SA_MA_10
SA_MA_11
SA_MA_12
SA_MA_13

SA_RAS#

SA_RCVEN#

SA_WE#

4

DDR_A_BS#0

BB19
BK19
BF29

BL17
AT45

BD44
BD42
AW38
AW13
BG8
AY5
AN6

AT46
BE48
BB43
BC37
BB16
BH6
BB2
AP3
AT47
BD47
BC41
BA37
BA16
BH7
BC1
AP2

BJ19
BD20
BK27
BH28
BL24
BK28
BJ27
BJ25
BL28
BA28
BC19
BE28
BG30
BJ16

BE18
AY20

BA19

DDR_A_BS#1
DDR_A_BS#2

DDR_A_CAS#
DDR_A_DM0

DDR_A_DM1
DDR_A_DM2
DDR_A_DM3
DDR_A_DM4
DDR_A_DM5
DDR_A_DM6
DDR_A_DM7

DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2

DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7
DDR_A_DQS#0
DDR_A_DQS#1
DDR_A_DQS#2
DDR_A_DQS#3
DDR_A_DQS#4
DDR_A_DQS#5
DDR_A_DQS#6
DDR_A_DQS#7

DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13

DDR_A_RAS#

DDR_A_WE#

DDR_A_BS#0 13
DDR_A_BS#1 13
DDR_A_BS#2 13

DDR_A_CAS# 13 DDR_B_CAS# 14
DDR_A_DM[0..7] 13

DDR_A_DQS[0..7] 13

DDR_A_DQS#[0..7] 13

DDR_A_MA[0..13] 13

DDR_A_RAS# 13

DDR_A_WE# 13

3

DDR_B_D[0..63]14

DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8

DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18DDR_A_DQS3
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41

DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63

AP49

AR51
AW50
AW51

AN51

AN50

AV50

AV49

BA50

BB50

BA49

BE50

BA51

AY49

BF50

BF49

BJ50
BJ44
BJ43

BL43
BK47
BK49
BK43
BK42

BJ41

BL41

BJ37

BJ36
BK41

BJ40

BL35
BK37
BK13
BE11
BK11
BC11
BC13
BE12
BC12
BG12

BJ10

BK10

BG1

BL9
BK5
BL5
BK9

BJ8
BJ6
BF4
BH5

BC2
BK3
BE4
BD3
BJ2
BA3
BB3
AR1
AT3
AY2
AY3
AU2
AT2

2

U3E

SB_DQ_0
SB_DQ_1
SB_DQ_2
SB_DQ_3
SB_DQ_4
SB_DQ_5
SB_DQ_6
SB_DQ_7
SB_DQ_8
SB_DQ_9
SB_DQ_10
SB_DQ_11
SB_DQ_12
SB_DQ_13
SB_DQ_14
SB_DQ_15
SB_DQ_16
SB_DQ_17
SB_DQ_18
SB_DQ_19
SB_DQ_20
SB_DQ_21
SB_DQ_22
SB_DQ_23
SB_DQ_24
SB_DQ_25
SB_DQ_26
SB_DQ_27
SB_DQ_28
SB_DQ_29
SB_DQ_30
SB_DQ_31
SB_DQ_32
SB_DQ_33
SB_DQ_34
SB_DQ_35
SB_DQ_36
SB_DQ_37
SB_DQ_38
SB_DQ_39
SB_DQ_40
SB_DQ_41
SB_DQ_42
SB_DQ_43
SB_DQ_44
SB_DQ_45
SB_DQ_46
SB_DQ_47
SB_DQ_48
SB_DQ_49
SB_DQ_50
SB_DQ_51
SB_DQ_52
SB_DQ_53
SB_DQ_54
SB_DQ_55
SB_DQ_56
SB_DQ_57
SB_DQ_58
SB_DQ_59
SB_DQ_60
SB_DQ_61
SB_DQ_62
SB_DQ_63

CRESTLINE_1p0 UMA@

1

DDR_B_BS#0

AY17

SB_BS_0
SB_BS_1
SB_BS_2

SB_CAS#

SB_DM_0
SB_DM_1
SB_DM_2
SB_DM_3
SB_DM_4
SB_DM_5
SB_DM_6
SB_DM_7

SB_DQS_0
SB_DQS_1
SB_DQS_2
SB_DQS_3
SB_DQS_4
SB_DQS_5
SB_DQS_6

SB_DQS_7
SB_DQS#_0
SB_DQS#_1
SB_DQS#_2
SB_DQS#_3
SB_DQS#_4
SB_DQS#_5
SB_DQS#_6
SB_DQS#_7

SB_MA_0
SB_MA_1
SB_MA_2
SB_MA_3
SB_MA_4
SB_MA_5
SB_MA_6
SB_MA_7
SB_MA_8

SB_MA_9
SB_MA_10
SB_MA_11
SB_MA_12
SB_MA_13

SB_RAS#

SB_RCVEN#

SB_WE#

DDR SYSTEM MEMORY B

BG18
BG36

BE17
AR50

BD49
BK45
BL39
BH12
BJ7
BF3
AW2

AT50
BD50
BK46
BK39
BJ12
BL7
BE2
AV2
AU50
BC50
BL45
BK38
BK12
BK7
BF2
AV3

BC18
BG28
BG25
AW17
BF25
BE25
BA29
BC28
AY28
BD37
BG17
BE37
BA39
BG13

AV16
AY18

BC17

DDR_B_BS#1
DDR_B_BS#2

DDR_B_CAS#
DDR_B_DM0

DDR_B_DM1
DDR_B_DM2
DDR_B_DM3
DDR_B_DM4
DDR_B_DM5
DDR_B_DM6
DDR_B_DM7

DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4
DDR_B_DQS5
DDR_B_DQS6

DDR_B_DQS7
DDR_B_DQS#0
DDR_B_DQS#1
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS#4
DDR_B_DQS#5
DDR_B_DQS#6
DDR_B_DQS#7

DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8

DDR_B_MA9
DDR_B_MA10DDR_B_D42
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13

DDR_B_RAS#

DDR_B_WE#

DDR_B_BS#0 14
DDR_B_BS#1 14
DDR_B_BS#2 14

DDR_B_DM[0..7] 14

DDR_B_DQS[0..7] 14

DDR_B_DQS#[0..7] 14

DDR_B_MA[0..13] 14

DDR_B_RAS# 14

DDR_B_WE# 14

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2007/12/28 2007/12/28

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

Compal Electronics, Inc.

Crestline(2/6)_DDR2 Channel A/B

LA-4131P

1

of

853Monday, February 18, 2008

0.2

5

For Crestline:2.4kohm
For Calero: 1.5Kohm

BIA_PWM15
GMCH_ENBKL28

+3VS

D D

C C

3VDDCCL15
3VDDCDA15

CRT_HSYNC15
CRT_VSYNC15

B B

+3VS

R131

2.2K_0402_5%
R143

2.2K_0402_5%

A A

R124 10K_0402_5%
R120 10K_0402_5%

GMCH_EDID_CLK_LCD15
GMCH_EDID_DAT_LCD15

GMCH_LVDDEN15,28

GMCH_LVDSAC-15
GMCH_LVDSAC+15
GMCH_LVDSBC-15
GMCH_LVDSBC+15

GMCH_LVDSA0-15
GMCH_LVDSA1-15
GMCH_LVDSA2-15

GMCH_LVDSA0+15
GMCH_LVDSA1+15
GMCH_LVDSA2+15

GMCH_LVDSB0-15
GMCH_LVDSB1-15
GMCH_LVDSB2-15

GMCH_LVDSB0+15
GMCH_LVDSB1+15
GMCH_LVDSB2+15

CRT_B15
CRT_G15
CRT_R15

UMA@

GMCH_EDID_CLK_LCD CTRL_CLK

1 2

UMA@

GMCH_EDID_DAT_LCD

1 2

BIA_PWM

GMCH_ENBKL

1 2
1 2

GMCH_EDID_CLK_LCD
GMCH_EDID_DAT_LCD

GMCH_LVDDEN

12

R103 2.4K_0402_1% UMA@

GMCH_LVDSAC-

GMCH_LVDSAC+

GMCH_LVDSBC-

GMCH_LVDSBC+

GMCH_LVDSA0-

GMCH_LVDSA1-

GMCH_LVDSA2-

GMCH_LVDSA0+

GMCH_LVDSA1+

GMCH_LVDSA2+

GMCH_LVDSB0-

GMCH_LVDSB1-

GMCH_LVDSB2-

GMCH_LVDSB0+

GMCH_LVDSB1+

GMCH_LVDSB2+

CRT_B
CRT_G
CRT_R

R127

1 2

150_0402_1%

UMA@

3VDDCCL
3VDDCDA

CRT_HSYNC
CRT_VSYNC

0_0402_5%

R121

VGA@

1 2

1 2

0_0402_5%

R147

VGA@

1 2

UMA@
UMA@

1 2
1 2
1 2

R116

1 2

0_0402_5%
R117

VGA@

VGA@

1 2

CTRL_CLK
CTRL_DATA

R13675_0402_1%UMA@
R13075_0402_1%UMA@
R10775_0402_1%UMA@

R128

1 2

150_0402_1%

150_0402_1%

UMA@

For Crestline:1.3kohm
For Calero: 255ohm

0_0402_5%
R138

UMA@

12

1.3K_0402_1%

R148

UMA@

U3C

J40
H39
E39
E40
C37
D35
K40

L41
L43
N41
N40
D46
C45
D44
E42

G51
E51
F49

G50
E50
F48

G44
B47
B45

E44
A47
A45

E27
G27
K27

F27
J27
L27

M35

P33

H32
G32
K29
J29
F29
E29

K33
G35
F33
C32
E33

CRESTLINE_1p0

UMA@

L_BKLT_CTRL
L_BKLT_EN
L_CTRL_CLK
L_CTRL_DATA
L_DDC_CLK
L_DDC_DATA
L_VDD_EN

LVDS_IBG
LVDS_VBG
LVDS_VREFH
LVDS_VREFL
LVDSA_CLK#
LVDSA_CLK
LVDSB_CLK#
LVDSB_CLK

LVDSA_DATA#_0
LVDSA_DATA#_1
LVDSA_DATA#_2

LVDSA_DATA_0
LVDSA_DATA_1
LVDSA_DATA_2

LVDSB_DATA#_0
LVDSB_DATA#_1
LVDSB_DATA#_2

LVDSB_DATA_0
LVDSB_DATA_1
LVDSB_DATA_2

TVA_DAC
TVB_DAC
TVC_DAC

TVA_RTN
TVB_RTN
TVC_RTN

TV_DCONSEL_0
TV_DCONSEL_1

CRT_BLUE
CRT_BLUE#
CRT_GREEN
CRT_GREEN#
CRT_RED
CRT_RED#

CRT_DDC_CLK
CRT_DDC_DATA
CRT_HSYNC
CRT_TVO_IREF
CRT_VSYNC

4

CTRL_DATA

0_0402_5%

PEGCOMP

N43

PEG_COMPI

PEG_RX#_0
PEG_RX#_1
PEG_RX#_2
PEG_RX#_3
PEG_RX#_4
PEG_RX#_5
PEG_RX#_6
PEG_RX#_7
PEG_RX#_8
PEG_RX#_9

PEG_RX_0
PEG_RX_1
PEG_RX_2
PEG_RX_3
PEG_RX_4
PEG_RX_5
PEG_RX_6
PEG_RX_7
PEG_RX_8

PEG_RX_9
PEG_RX_10
PEG_RX_11
PEG_RX_12
PEG_RX_13
PEG_RX_14
PEG_RX_15

PEG_TX#_0
PEG_TX#_1
PEG_TX#_2
PEG_TX#_3
PEG_TX#_4
PEG_TX#_5
PEG_TX#_6
PEG_TX#_7
PEG_TX#_8
PEG_TX#_9

PEG_TX_0

PEG_TX_1

PEG_TX_2

PEG_TX_3

PEG_TX_4

PEG_TX_5

PEG_TX_6

PEG_TX_7

PEG_TX_8

PEG_TX_9
PEG_TX_10
PEG_TX_11
PEG_TX_12
PEG_TX_13
PEG_TX_14
PEG_TX_15

M43

PEG_NRX_GTX_N0

J51

PEG_NRX_GTX_N1

L51

PEG_NRX_GTX_N2

N47

PEG_NRX_GTX_N3

T45

PEG_NRX_GTX_N4

T50

PEG_NRX_GTX_N5

U40

PEG_NRX_GTX_N6

Y44

PEG_NRX_GTX_N7

Y40

PEG_NRX_GTX_N8

AB51

PEG_NRX_GTX_N9

W49

PEG_NRX_GTX_N10

AD44

PEG_NRX_GTX_N11

AD40

PEG_NRX_GTX_N12

AG46

PEG_NRX_GTX_N13

AH49

PEG_NRX_GTX_N14

AG45

PEG_NRX_GTX_N15

AG41

PEG_NRX_GTX_P0

J50

PEG_NRX_GTX_P1

L50

PEG_NRX_GTX_P2

M47

PEG_NRX_GTX_P3

U44

PEG_NRX_GTX_P4

T49

PEG_NRX_GTX_P5

T41

PEG_NRX_GTX_P6

W45

PEG_NRX_GTX_P7

W41

PEG_NRX_GTX_P8

AB50

PEG_NRX_GTX_P9

Y48

PEG_NRX_GTX_P10

AC45

PEG_NRX_GTX_P11

AC41

PEG_NRX_GTX_P12

AH47

PEG_NRX_GTX_P13

AG49

PEG_NRX_GTX_P14

AH45

PEG_NRX_GTX_P15

AG42

PEG_TXN0

N45

PEG_TXN1

U39

PEG_TXN2

U47

PEG_TXN3

N51

PEG_TXN4

R50

PEG_TXN5

T42

PEG_TXN6

Y43

PEG_TXN7

W46

PEG_TXN8

W38

PEG_TXN9

AD39

PEG_TXN10

AC46

PEG_TXN11

AC49

PEG_TXN12

AC42

PEG_TXN13

AH39

PEG_TXN14

AE49

PEG_TXN15

AH44

PEG_TXP0

M45

PEG_TXP1

T38

PEG_TXP2

T46

PEG_TXP3

N50

PEG_TXP4

R51

PEG_TXP5

U43

PEG_TXP6

W42

PEG_TXP7

Y47

PEG_TXP8

Y39

PEG_TXP9

AC38

PEG_TXP10

AD47

PEG_TXP11

AC50

PEG_TXP12

AD43

PEG_TXP13

AG39

PEG_TXP14

AE50

PEG_TXP15

AH43

R136

0_0402_5%

VGA@

PEG_COMPO

LVDS

PEG_RX#_10
PEG_RX#_11
PEG_RX#_12
PEG_RX#_13
PEG_RX#_14
PEG_RX#_15

TV VGA

PEG_TX#_10

PCI-EXPRESS GRAPHICS

PEG_TX#_11
PEG_TX#_12
PEG_TX#_13
PEG_TX#_14
PEG_TX#_15

0_0402_5%

R119

VGA@

R112

VGA@

1 2

1 2

3

R104

24.9_0402_1%

1 2

C612 0.1U_0402_16V7KVGA@

1 2

C609 0.1U_0402_16V7KVGA@

1 2

C605 0.1U_0402_16V7KVGA@

1 2

C592 0.1U_0402_16V7KVGA@

1 2

C590 0.1U_0402_16V7KVGA@

1 2

C588 0.1U_0402_16V7KVGA@

1 2

C581 0.1U_0402_16V7KVGA@

1 2

C582 0.1U_0402_16V7KVGA@

1 2

C567 0.1U_0402_16V7KVGA@

1 2

C566 0.1U_0402_16V7KVGA@

1 2

C561 0.1U_0402_16V7KVGA@

1 2

C560 0.1U_0402_16V7KVGA@

1 2

C557 0.1U_0402_16V7KVGA@

1 2

C555 0.1U_0402_16V7KVGA@

1 2

C552 0.1U_0402_16V7KVGA@

1 2

C549 0.1U_0402_16V7KVGA@

1 2

C614 0.1U_0402_16V7KVGA@

1 2

C611 0.1U_0402_16V7KVGA@

1 2

C608 0.1U_0402_16V7KVGA@

1 2

C594 0.1U_0402_16V7KVGA@

1 2

C593 0.1U_0402_16V7KVGA@

1 2

C591 0.1U_0402_16V7KVGA@

1 2

C585 0.1U_0402_16V7KVGA@

1 2

C586 0.1U_0402_16V7KVGA@

1 2

C578 0.1U_0402_16V7KVGA@

1 2

C570 0.1U_0402_16V7KVGA@

1 2

C563 0.1U_0402_16V7KVGA@

1 2

C562 0.1U_0402_16V7KVGA@

1 2

C559 0.1U_0402_16V7KVGA@

1 2

C558 0.1U_0402_16V7KVGA@

1 2

C554 0.1U_0402_16V7KVGA@

1 2

C551 0.1U_0402_16V7KVGA@

1 2

R130

0_0402_5%

VGA@

PEGCOMP trace width

+VCCP

R107

0_0402_5%

VGA@

and spacing is 20/25 mils.

PEG_NRX_GTX_N[0..15] 34

PEG_NRX_GTX_P[0..15] 34

PEG_NTX_GRX_N0
PEG_NTX_GRX_N1
PEG_NTX_GRX_N2
PEG_NTX_GRX_N3
PEG_NTX_GRX_N4
PEG_NTX_GRX_N5
PEG_NTX_GRX_N6
PEG_NTX_GRX_N7
PEG_NTX_GRX_N8

PEG_NTX_GRX_N9
PEG_NTX_GRX_N10
PEG_NTX_GRX_N11
PEG_NTX_GRX_N12
PEG_NTX_GRX_N13
PEG_NTX_GRX_N14
PEG_NTX_GRX_N15

PEG_NTX_GRX_P0

PEG_NTX_GRX_P1

PEG_NTX_GRX_P2

PEG_NTX_GRX_P3

PEG_NTX_GRX_P4

PEG_NTX_GRX_P5

PEG_NTX_GRX_P6

PEG_NTX_GRX_P7

PEG_NTX_GRX_P8

PEG_NTX_GRX_P9

PEG_NTX_GRX_P10
PEG_NTX_GRX_P11
PEG_NTX_GRX_P12
PEG_NTX_GRX_P13
PEG_NTX_GRX_P14
PEG_NTX_GRX_P15

R127

0_0402_5%

VGA@

PEG_NTX_GRX_N[0..15] 34

PEG_NTX_GRX_P[0..15] 34

R116

0_0402_5%

VGA@

2

R128

0_0402_5%

VGA@

Strap Pin Table

CFG[2:0] FSB Freq select

CFG5 (DMI select)

CFG6

CFG7 (CPU Strap)

CFG8 (Low power PCIE)

(PCIE Graphics Lane Reversal)

CFG20 (PCIE/SDVO concurrent)

CFG9

CFG[11:10]

CFG[13:12] (XOR/ALLZ)

CFG16 (FSB Dynamic ODT)

SDVO_CTRLDATA

CFG19 (DMI Lane Reversal)

R148

0_0402_5%

VGA@

1

010 = FSB 800MHz
011 = FSB 667MHz
Others = Reserved

0 = DMI x 2
1 = DMI x 4

*

Reserved

0 = Reserved
1 = Mobile CPU

*

0 = Normal mode
1 = Low Power mode

*

0 = Reverse Lane
1 = Normal Operation

*

Reserved
00 = Reserved

01 = XOR Mode Enabled
10 = All Z Mode Enabled
11 = Normal Operation

(Default)

*

ReservedCFG[15:14]

0 = Disabled
1 = Enabled

*

ReservedCFG[18:17]

0 = No SDVO Device Present
1 = SDVO Device Present

0 = Normal Operation

(Lane number in Order)

*

*

1 = Reverse Lane

0 = Only PCIE or SDVO is operational.
1 = PCIE/SDVO are operating simu.

CFG[17:3] have internal pull up
CFG[19:18] have internal pull down

R135 4.02K_0402_1%@

CFG97

CFG127

CFG137

CFG167

1 2

R118 4.02K_0402_1%@

1 2

R125 4.02K_0402_1%@

1 2

R100 4.02K_0402_1%@

1 2

*

Note: CRT / TV-out should route to JP30 first then to the JP1 & JP2 on system side.

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date

2007/12/28 2007/12/28

3

Compal Secret Data

Deciphered Date

2

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

Crestline(3/6)_LVDS / CRT/ PCIE

LA-4131P

1

of

953Monday, February 18, 2008

0.2

5

+3VS_DAC_CRT

C635

0.1U_0402_16V4Z~N

C632

0.022U_0402_16V7K~N

1

1

2

2

UMA@

UMA@

D D

+3VS_DAC_BG

C C

0.1U_0402_16V4Z~N

C633

0.022U_0402_16V7K~N

1

2

UMA@

+1.25VS

BLM18PG181SN1D_0603

C636

1

2

UMA@

+3VS

R469

10_0603_5%

UMA@

L31

UMA@

C638

4.7U_0805_10V4Z~N

1

2

UMA@

R416

1 2

0_0805_5%

0.1U_0402_16V4Z~N

R87

1 2

0_0805_5%

R84

0_0603_5%

VCCD_CRT = 60 mA
VCCD_TVDAC = 60 mA

+3VS

+3VS

12

+3VS_PEG_BG

C615

+1.25VM_A_SM

150U_Y_6.3VM

+1.25VM_A_SM_CK

12

1U_0402_6.3V4Z

+3VS

VCCA_PEG_BG = 0.4 mA

1

2

VCCA_SM = 735 mA

22U_0805_6.3V4Z

1

C196

C539

1

+

2

2

VCCA_SM_CK = 35 mA

22U_0805_6.3V4Z

@

C142

C159

1

1

2

2

+1.5VS_TVDAC

VCCD_QTVDAC = 0.5 mA

VCCD_HPLL = 250 mA

VCCD_PEG_PLL = 90 mA

VCCD_LVDS = 150 mA

B B

+3VS_TVDACA

0.022U_0402_16V7K~N

1

2

C630

0.1U_0402_16V4Z~N

1

UMA@

2

+3VS

R467

12

0_0603_5%

C627

UMA@

VCCA_TVA_DAC = 40 mA

UMA@

VCCSYNC

R97

12

0_0603_5%

UMA@

+3VS_DAC_CRT

VCC_CRT_DAC = 70 mA

+3VS_DAC_BG

VCCA_DAC_BG = 5 mA

+1.25VS_DPLLA

VCCA_DPLLA = 100 mA

+1.25VS_DPLLB

VCCA_DPLLB = 100 mA

+1.25VM_HPLL

VCCA_HPLL = 50 mA

+1.25VM_MPLL

VCCA_MPLL = 150 mA

+1.8V_TXLVDS

VCCA_LVDS = 10 mA

1000P_0402_50V7K~N

+1.25VS_PEGPLL

VCCA_PEG_PLL = 90 mA

4.7U_0805_6.3V6K

1U_0603_10V4Z

C176

1

2

0.1U_0402_16V4Z~N

1U_0603_10V4Z

@

C162

1

2

VCC_SYNC = 10 mA

1

C250

0.1U_0402_16V4Z~N

UMA@

2

1

C294

UMA@

2

C155

1

2

C149

1

+3VS_TVDACA
+3VS_TVDACB

2

+3VS_TVDACC

R109 0_0402_5% VGA@

R106 0_0402_5% UMA@

+1.5VS_QDAC

+1.25VM_HPLL

+1.25VS_PEGPLL

+1.8V_LVDS

12
12

20 mils

4

U3H

J32

VCCSYNC

A33

VCCA_CRT_DAC_1

B33

VCCA_CRT_DAC_2

A30

VCCA_DAC_BG

B32

VSSA_DAC_BG

B49

VCCA_DPLLA

H49

VCCA_DPLLB

AL2

VCCA_HPLL

AM2

VCCA_MPLL

A41

VCCA_LVDS

B41

VSSA_LVDS

K50

VCCA_PEG_BG

K49

VSSA_PEG_BG

U51

VCCA_PEG_PLL

AW18

VCCA_SM_1

AV19

VCCA_SM_2

AU19

VCCA_SM_3

AU18

VCCA_SM_4

AU17

VCCA_SM_5

AT22

VCCA_SM_7

AT21

VCCA_SM_8

AT19

VCCA_SM_9

AT18

VCCA_SM_10

AT17

VCCA_SM_11

AR17

VCCA_SM_NCTF_1

AR16

VCCA_SM_NCTF_2

BC29

VCCA_SM_CK_1

BB29

VCCA_SM_CK_2

C25

VCCA_TVA_DAC_1

B25

VCCA_TVA_DAC_2

C27

VCCA_TVB_DAC_1

B27

VCCA_TVB_DAC_2

B28

VCCA_TVC_DAC_1

A28

VCCA_TVC_DAC_2

M32

VCCD_CRT

L29

VCCD_TVDAC

N28

VCCD_QDAC

AN2

VCCD_HPLL

U48

VCCD_PEG_PLL

J41

VCCD_LVDS_1

H42

VCCD_LVDS_2

CRESTLINE_1p0 UMA@

CRTPLLA PEGA SMTV

POWER

A CK A LVDS

D TV/CRTLVDS

VTT_10
VTT_11
VTT_12
VTT_13

VTT

VTT_14
VTT_15
VTT_16
VTT_17
VTT_18
VTT_19
VTT_20
VTT_21
VTT_22

VCC_AXD_1

VCC_AXD_2
VCC_AXD_3

VCC_AXD_4

VCC_AXD_5

AXD

VCC_AXD_6

VCC_AXD_NCTF

VCC_AXF_1
VCC_AXF_2
VCC_AXF_3

AXF

VCC_DMI

VCC_SM_CK_1
VCC_SM_CK_2
VCC_SM_CK_3
VCC_SM_CK_4

SM CK

VCC_TX_LVDS

VCC_HV_1
VCC_HV_2

HV

VCC_PEG_1
VCC_PEG_2
VCC_PEG_3
VCC_PEG_4

PEG

VCC_PEG_5

VCC_RXR_DMI_1
VCC_RXR_DMI_2

DMI

VTTLF1
VTTLF2
VTTLF3

VTTLF

U13

VTT_1

U12

VTT_2

U11

VTT_3

U9

VTT_4

U8

VTT_5

U7

VTT_6

U5

VTT_7

U3

VTT_8

U2

VTT_9

U1
T13
T11
T10
T9
T7
T6
T5
T3
T2
R3
R2
R1

AT23
AU28
AU24
AT29
AT25
AT30

AR29

B23
B21
A21

AJ50

BK24
BK23
BJ24
BJ23

A43

C40
B40

VCC_PEG = 1310 mA

AD51
W50
W51
V49
V50

AH50
AH51

VCCR_RX_DMI = 260 mA

A7
F2
AH1

3

+VCCP

VTT = 850 mA

330U_D2_2.5VY_R9M

4.7U_0805_10V4Z~N

1

C313

+

2

0.47U_0603_10V7K

4.7U_0805_10V4Z~N

C197

1

2

+1.25VM_AXD

10U_0805_10V4Z~N

1U_0603_10V4Z

C174

1

2

+V1.25VS_AXF

VCC_AXF = 495 mA

VCC_DMI = 100 mA

+1.25VS_DMI

VCC_SM_CK = 200 mA

+1.8V_SM_CK

VCC_TX_LVDS = 100 mA

+1.8V_TXLVDS

VCC_HV = 100 mA

+VCC_PEG

1

2

0.47U_0603_10V7K

C210

1

2

0.47U_0603_10V7K

C279

0.47U_0603_10V7K

C225

1

2

2.2U_0805_16V4Z

C596

1

2

R88

1 2

0_0805_5%

VCC_AXD = 515 mA

C199

1

2

+3VS_HV

0.1U_0402_16V4Z~N
C288

1

2

20mils

C624

1

2

2

+1.25VS_DPLLA

220U_D2_4VY_R15M

0.1U_0402_16V4Z~N

10U_0805_10V4Z~N

C327

C317

1

1

+

UMA@

2

C595

1

2

+1.25VS

+1.25VS_DPLLB +1.25VS

0.1U_0402_16V4Z~N

C619

1

UMA@

2

0.1U_0402_16V4Z~N

C178

1

2

+1.25VM_MPLL

0.1U_0402_16V4Z~N
C201

1

2

1

UMA@

2

2

L30

UMA@

1 2

22U_0805_6.3VAM

10U_FLC-453232-100K_0.25A_10%

C618

1

UMA@

2

L9

MBK2012121YZF_0805

10U_0805_10V4Z~N

C187

1

2

L10

MBK2012121YZF_0805

10U_0805_10V4Z~N

C204

1

2

+1.25VS

L14

UMA@

1 2

10U_FLC-453232-100K_0.25A_10%

C321

UMA@

+1.25VS+1.25VM_HPLL

12

+1.25VS

12

+VCCP_D

D12

2 1

+VCCP

CH751H-40PT_SOD323-2

+3VS

22U_0805_6.3V4Z

+V1.25VS_AXF

+1.25VS_DMI

+1.8V_SM_CK

C117

1

2

+1.8V_TXLVDS

+VCC_PEG

R140

10_0402_5%

1

10U_0805_10V4Z~N

1U_0603_10V4Z

C628

1

2

1 2

0.1U_0402_16V4Z~N
0_0603_5%

C583

1

2

10U_0805_10V4Z~N

0.1U_0402_16V4Z~N

C542

1

2

40 mils

C309

1000P_0402_50V7K~N

220U_D2_4VY_R15M

1

UMA@

2

10U_0805_10V4Z~N

220U_D2_4VY_R15M

1

C569

+

2

R137

12

0_0402_5%

C623

1

2

R411

C538

1

2

C326

1

+

UMA@

2

C589

1

2

R466

1 2

0_0603_5%

+1.25VS

R393

1 2

0_0805_5%

R153

UMA@

0_0603_5%

R415

0_0805_5%

12

+1.25VS

+1.8V

+1.8V

12

+VCCP

12

+3VS_HV

+3VS_TVDACB

C626

0.022U_0402_16V7K~N

0.1U_0402_16V4Z~N

1

1

UMA@

2

2

A A

+3VS_TVDACC

0.1U_0402_16V4Z~N

C625

0.022U_0402_16V7K~N

1

1

UMA@

2

2

+3VS

R468

12

0_0603_5%

C629

UMA@

VCCA_TVB_DAC = 40 mA

UMA@

+3VS

R465

12

0_0603_5%

C621

UMA@

VCCA_TVC_DAC = 40 mA

UMA@

5

+1.5VS_TVDAC

0.022U_0402_16V7K~N

1

2

+1.5VS_QDAC

1U_0402_6.3V4Z

1

2

+1.5VS

R91

1 2

0_0805_5%

0.1U_0402_16V4Z~N

C251

C240

1

2

R95

100_0603_1%

C249

C232

0.1U_0402_16V4Z~N

UMA@

1

UMA@

UMA@

2

+1.25VS_PEGPLL

0.1U_0402_16V4Z~N

+1.5VS

12

4

1

2

+1.8V_LVDS

10U_0805_10V4Z~N

1

2

C607

C280

UMA@

10U_0805_10V4Z~N

1

2

1U_0603_10V4Z

1

2

+1.25VS

L29

R141

0_0603_5%

UMA@

12

+1.8V

12

BLM18PG121SN1D_0603

C597

C273

UMA@

C633

0_0402_5%

VGA@

C632

0_0402_5%

VGA@

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2007/12/28 2007/12/28

Compal Secret Data

Deciphered Date

C627

0_0402_5%

VGA@

C629

0_0402_5%

VGA@

2

For Discrete BOM

C621

0_0402_5%

VGA@

C232

0_0402_5%

VGA@

C273

0_0603_5%

VGA@

C309

0_0402_5%

VGA@

Title

Crestline(4/6)_PWR

Size Document Number Rev

Custom

LA-4131P

Date: Sheet

C619

0_0402_5%

VGA@

C250

0_0402_5%

VGA@

U3

PM965_C0

VGA@

C317

0_0402_5%

VGA@

Compal Electronics, Inc.

10 53Monday, February 18, 2008

1

0.2

of

5

4

3

2

1

+VCCP

VCC = 1573 mA

1

2

C215

C202

+VCCP

0.1U_0402_16V4Z~N

C188

1

2

10U_0805_10V4Z~N

C200

C205

1

2

0.1U_0402_16V4Z~N
C191

1

2

U3F

AB33

VCC_NCTF_1

AB36

VCC_NCTF_2

AB37

VCC_NCTF_3

AC33

VCC_NCTF_4

AC35

VCC_NCTF_5

AC36

VCC_NCTF_6

AD35

VCC_NCTF_7

AD36

VCC_NCTF_8

AF33

VCC_NCTF_9

AF36

VCC_NCTF_10

AH33

VCC_NCTF_11

AH35

VCC_NCTF_12

AH36

VCC_NCTF_13

AH37

VCC_NCTF_14

AJ33

VCC_NCTF_15

AJ35

VCC_NCTF_16

AK33

VCC_NCTF_17

AK35

VCC_NCTF_18

AK36

VCC_NCTF_19

AK37

VCC_NCTF_20

AD33

VCC_NCTF_21

AJ36

VCC_NCTF_22

AM35

VCC_NCTF_23

AL33

VCC_NCTF_24

AL35

VCC_NCTF_25

AA33

VCC_NCTF_26

AA35

VCC_NCTF_27

AA36

VCC_NCTF_28

AP35

VCC_NCTF_29

AP36

VCC_NCTF_30

AR35

VCC_NCTF_31

AR36

VCC_NCTF_32

Y32

VCC_NCTF_33

Y33

VCC_NCTF_34

Y35

VCC_NCTF_35

Y36

VCC_NCTF_36

Y37

VCC_NCTF_37

T30

VCC_NCTF_38

T34

VCC_NCTF_39

T35

VCC_NCTF_40

U29

VCC_NCTF_41

U31

VCC_NCTF_42

U32

VCC_NCTF_43

U33

VCC_NCTF_44

U35

VCC_NCTF_45

U36

VCC_NCTF_46

V32

VCC_NCTF_47

V33

VCC_NCTF_48

V36

VCC_NCTF_49

V37

VCC_NCTF_50

AL24

VCC_AXM_NCTF_1

AL26

VCC_AXM_NCTF_2

AL28

VCC_AXM_NCTF_3

AM26

VCC_AXM_NCTF_4

AM28

VCC_AXM_NCTF_5

AM29

VCC_AXM_NCTF_6

AM31

VCC_AXM_NCTF_7

AM32

VCC_AXM_NCTF_8

AM33

VCC_AXM_NCTF_9

AP29

VCC_AXM_NCTF_10

AP31

VCC_AXM_NCTF_11

AP32

VCC_AXM_NCTF_12

AP33

VCC_AXM_NCTF_13

AL29

VCC_AXM_NCTF_14

AL31

VCC_AXM_NCTF_15

AL32

VCC_AXM_NCTF_16

AR31

VCC_AXM_NCTF_17

AR32

VCC_AXM_NCTF_18

AR33

VCC_AXM_NCTF_19

CRESTLINE_1p0 UMA@

VSS NCTF

VCC NCTF

POWER

VCC AXM NCTF

VSS_NCTF_1
VSS_NCTF_2
VSS_NCTF_3
VSS_NCTF_4
VSS_NCTF_5
VSS_NCTF_6
VSS_NCTF_7
VSS_NCTF_8

VSS_NCTF_9
VSS_NCTF_10
VSS_NCTF_11
VSS_NCTF_12
VSS_NCTF_13
VSS_NCTF_14
VSS_NCTF_15
VSS_NCTF_16
VSS_NCTF_17
VSS_NCTF_18
VSS_NCTF_19
VSS_NCTF_20
VSS_NCTF_21

VSS_SCB1
VSS_SCB2
VSS_SCB3
VSS_SCB4
VSS_SCB5
VSS_SCB6

VSS SCBVCC AXM

VCC_AXM_1
VCC_AXM_2
VCC_AXM_3
VCC_AXM_4
VCC_AXM_5
VCC_AXM_6
VCC_AXM_7

T27
T37
U24
U28
V31
V35
AA19
AB17
AB35
AD19
AD37
AF17
AF35
AK17
AM17
AM24
AP26
AP28
AR15
AR19
AR28

A3
B2
C1
BL1
BL51
A51

AT33
AT31
AK29
AK24
AK23
AJ26
AJ23

+VCCP

VCC_AXM = 540 mA

1

C211

UMA@

1U_0603_10V4Z

2

330U_D2_2.5VY_R9MUMA@

C324

1

+

2

+1.8V

VCC_SM = 3300 mA

160mil

330U_D2_2.5VY_R9M

22U_0805_6.3V4Z

1

C99

C122

1

+

2

2

VCC_AXG = 7700 mA

10U_0805_10V4Z~NUMA@

1

C252

1

C223

2

2

10U_0805_10V4Z~NUMA@

0.01U_0402_16V7K

22U_0805_6.3V4Z

C129

1

2

+VCCP

0.1U_0402_16V4Z~N

1

C221

2

R94

1 2

0_0603_5%

C143

2

1

UMA@

D D

220U_D2_4VY_R15M

22U_0805_6.3V4Z

1

C325

+

2

C C

B B

0.22U_0402_10V4Z~N

C173

C189

12

12

1

2

0.22U_0402_10V4Z~N

C224

+VCCP

0.22U_0402_10V4Z~N

0.22U_0402_10V4Z~N

C214

12

12

10U_0805_10V4Z~N

0.1U_0402_16V4Z~N

0.1U_0402_16V4Z~N

C172

1

1

2

2

AT35
AT34
AH28
AC32
AC31
AK32

AJ31

AJ28
AH32
AH31
AH29
AF32

AU32
AU33
AU35
AV33

AW33
AW35

AY35
BA32
BA33
BA35
BB33
BC32
BC33
BC35
BD32
BD35
BE32
BE33
BE35
BF33
BF34
BG32
BG33
BG35
BH32
BH34
BH35

BJ32

BJ33

BJ34
BK32
BK33
BK34
BK35

BL33
AU30

W13
W14

AA20
AA23
AA26
AA28
AB21
AB24
AB29
AC20
AC21
AC23
AC24
AC26
AC28
AC29
AD20
AD23
AD24
AD28
AF21
AF26
AA31
AH20
AH21
AH23
AH24
AH26
AD31

AJ20
AN14

R30

R20
T14

Y12

U3G

VCC_1
VCC_2
VCC_3
VCC_5
VCC_4
VCC_6
VCC_7
VCC_8
VCC_9
VCC_10
VCC_11
VCC_12

VCC_13

VCC_SM_1
VCC_SM_2
VCC_SM_3
VCC_SM_4
VCC_SM_5
VCC_SM_6
VCC_SM_7
VCC_SM_8
VCC_SM_9
VCC_SM_10
VCC_SM_11
VCC_SM_12
VCC_SM_13
VCC_SM_14
VCC_SM_15
VCC_SM_16
VCC_SM_17
VCC_SM_18
VCC_SM_19
VCC_SM_20
VCC_SM_21
VCC_SM_22
VCC_SM_23
VCC_SM_24
VCC_SM_25
VCC_SM_26
VCC_SM_27
VCC_SM_28
VCC_SM_29
VCC_SM_30
VCC_SM_31
VCC_SM_32
VCC_SM_33
VCC_SM_34
VCC_SM_35
VCC_SM_36

VCC_AXG_1
VCC_AXG_2
VCC_AXG_3
VCC_AXG_4
VCC_AXG_5
VCC_AXG_6
VCC_AXG_7
VCC_AXG_8
VCC_AXG_9
VCC_AXG_10
VCC_AXG_11
VCC_AXG_12
VCC_AXG_13
VCC_AXG_14
VCC_AXG_15
VCC_AXG_16
VCC_AXG_17
VCC_AXG_18
VCC_AXG_19
VCC_AXG_20
VCC_AXG_21
VCC_AXG_22
VCC_AXG_23
VCC_AXG_24
VCC_AXG_25
VCC_AXG_26
VCC_AXG_27
VCC_AXG_28
VCC_AXG_29
VCC_AXG_30
VCC_AXG_31
VCC_AXG_32
VCC_AXG_33
VCC_AXG_34

VCC CORE

POWER

VCC SMVCC GFX

VCC_AXG_NCTF_1
VCC_AXG_NCTF_2
VCC_AXG_NCTF_3
VCC_AXG_NCTF_4
VCC_AXG_NCTF_5
VCC_AXG_NCTF_6
VCC_AXG_NCTF_7
VCC_AXG_NCTF_8

VCC_AXG_NCTF_9
VCC_AXG_NCTF_10
VCC_AXG_NCTF_11
VCC_AXG_NCTF_12
VCC_AXG_NCTF_13
VCC_AXG_NCTF_14
VCC_AXG_NCTF_15
VCC_AXG_NCTF_16
VCC_AXG_NCTF_17
VCC_AXG_NCTF_18
VCC_AXG_NCTF_19
VCC_AXG_NCTF_20
VCC_AXG_NCTF_21
VCC_AXG_NCTF_22
VCC_AXG_NCTF_23
VCC_AXG_NCTF_24
VCC_AXG_NCTF_25
VCC_AXG_NCTF_26
VCC_AXG_NCTF_27
VCC_AXG_NCTF_28
VCC_AXG_NCTF_29
VCC_AXG_NCTF_30
VCC_AXG_NCTF_31
VCC_AXG_NCTF_32
VCC_AXG_NCTF_33
VCC_AXG_NCTF_34
VCC_AXG_NCTF_35
VCC_AXG_NCTF_36
VCC_AXG_NCTF_37
VCC_AXG_NCTF_38
VCC_AXG_NCTF_39
VCC_AXG_NCTF_40
VCC_AXG_NCTF_41
VCC_AXG_NCTF_42
VCC_AXG_NCTF_43
VCC_AXG_NCTF_44
VCC_AXG_NCTF_45
VCC_AXG_NCTF_46
VCC_AXG_NCTF_47
VCC_AXG_NCTF_48
VCC_AXG_NCTF_49
VCC_AXG_NCTF_50
VCC_AXG_NCTF_51
VCC_AXG_NCTF_52
VCC_AXG_NCTF_53
VCC_AXG_NCTF_54

VCC GFX NCTF

VCC_AXG_NCTF_55
VCC_AXG_NCTF_56
VCC_AXG_NCTF_57
VCC_AXG_NCTF_58
VCC_AXG_NCTF_59
VCC_AXG_NCTF_60
VCC_AXG_NCTF_61
VCC_AXG_NCTF_62
VCC_AXG_NCTF_63
VCC_AXG_NCTF_64
VCC_AXG_NCTF_65
VCC_AXG_NCTF_66
VCC_AXG_NCTF_67
VCC_AXG_NCTF_68
VCC_AXG_NCTF_69
VCC_AXG_NCTF_70
VCC_AXG_NCTF_71
VCC_AXG_NCTF_72
VCC_AXG_NCTF_73
VCC_AXG_NCTF_74
VCC_AXG_NCTF_75
VCC_AXG_NCTF_76
VCC_AXG_NCTF_77
VCC_AXG_NCTF_78
VCC_AXG_NCTF_79
VCC_AXG_NCTF_80
VCC_AXG_NCTF_81
VCC_AXG_NCTF_82
VCC_AXG_NCTF_83

VCC_SM_LF1
VCC_SM_LF2
VCC_SM_LF3
VCC_SM_LF4
VCC_SM_LF5
VCC_SM_LF6
VCC_SM_LF7

VCC SM LF

T17
T18
T19
T21
T22
T23
T25
U15
U16
U17
U19
U20
U21
U23
U26
V16
V17
V19
V20
V21
V23
V24
Y15
Y16
Y17
Y19
Y20
Y21
Y23
Y24
Y26
Y28
Y29
AA16
AA17
AB16
AB19
AC16
AC17
AC19
AD15
AD16
AD17
AF16
AF19
AH15
AH16
AH17
AH19
AJ16
AJ17
AJ19
AK16
AK19
AL16
AL17
AL19
AL20
AL21
AL23
AM15
AM16
AM19
AM20
AM21
AM23
AP15
AP16
AP17
AP19
AP20
AP21
AP23
AP24
AR20
AR21
AR23
AR24
AR26
V26
V28
V29
Y31

AW45
BC39
BE39
BD17
BD4
AW8
AT6

+VCCP

VCCSM_LF1
VCCSM_LF2
VCCSM_LF3
VCCSM_LF4
VCCSM_LF5
VCCSM_LF6
VCCSM_LF7

370mil

0.1U_0402_16V4Z~N

UMA@

1

C226

2

0.22U_0402_10V4Z~N UMA@

C170 0.1U_0402_16V4Z~N

C154 0.1U_0402_16V4Z~N

1

1

2

2

C153 0.22U_0603_10V7K~D

1

2

12

C229

C141 0.22U_0603_10V7K~D

1

2

0.47U_0603_10V7K

UMA@

1

C231

2

C135 0.47U_0402_6.3V6K

C148 1U_0603_10V4Z

1

1

2

2

C156 1U_0603_10V4Z

1

2

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2007/12/28 2007/12/28

Compal Secret Data

Deciphered Date

CRESTLINE_1p0 UMA@

2

Compal Electronics, Inc.

Title

Crestline(5/6)_PWR / GND

Size Document Number Rev

Custom

LA-4131P

Date: Sheet of

11 53Monday, February 18, 2008

1

0.2

5

U3I

A13

VSS_1

A15

VSS_2

A17

VSS_3

A24

VSS_4

AA21

VSS_5

AA24

VSS_6

AA29

VSS_7

AB20

D D

C C

B B

A A

VSS_8

AB23

VSS_9

AB26

VSS_10

AB28

VSS_11

AB31

VSS_12

AC10

VSS_13

AC13

VSS_14

AC3

VSS_15

AC39

VSS_16

AC43

VSS_17

AC47

VSS_18

AD1

VSS_19

AD21

VSS_20

AD26

VSS_21

AD29

VSS_22

AD3

VSS_23

AD41

VSS_24

AD45

VSS_25

AD49

VSS_26

AD5

VSS_27

AD50

VSS_28

AD8

VSS_29

AE10

VSS_30

AE14

VSS_31

AE6

VSS_32

AF20

VSS_33

AF23

VSS_34

AF24

VSS_35

AF31

VSS_36

AG2

VSS_37

AG38

VSS_38

AG43

VSS_39

AG47

VSS_40

AG50

VSS_41

AH3

VSS_42

AH40

VSS_43

AH41

VSS_44

AH7

VSS_45

AH9

VSS_46

AJ11

VSS_47

AJ13

VSS_48

AJ21

VSS_49

AJ24

VSS_50

AJ29

VSS_51

AJ32

VSS_52

AJ43

VSS_53

AJ45

VSS_54

AJ49

VSS_55

AK20

VSS_56

AK21

VSS_57

AK26

VSS_58

AK28

VSS_59

AK31

VSS_60

AK51

VSS_61

AL1

VSS_62

AM11

VSS_63

AM13

VSS_64

AM3

VSS_65

AM4

VSS_66

AM41

VSS_67

AM45

VSS_68

AN1

VSS_69

AN38

VSS_70

AN39

VSS_71

AN43

VSS_72

AN5

VSS_73

AN7

VSS_74

AP4

VSS_75

AP48

VSS_76

AP50

VSS_77

AR11

VSS_78

AR2

VSS_79

AR39

VSS_80

AR44

VSS_81

AR47

VSS_82

AR7

VSS_83

AT10

VSS_84

AT14

VSS_85

AT41

VSS_86

AT49

VSS_87

AU1

VSS_88

AU23

VSS_89

AU29

VSS_90

AU3

VSS_91

AU36

VSS_92

AU49

VSS_93

AU51

VSS_94

AV39

VSS_95

AV48

VSS_96

AW1

VSS_97

AW12

VSS_98

AW16

VSS_99

CRESTLINE_1p0 UMA@

VSS

VSS_100
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105
VSS_106
VSS_107
VSS_108
VSS_109
VSS_110
VSS_111
VSS_112
VSS_113
VSS_114
VSS_115
VSS_116
VSS_117
VSS_118
VSS_119
VSS_120
VSS_121
VSS_122
VSS_123
VSS_124
VSS_125
VSS_126
VSS_127
VSS_128
VSS_129
VSS_130
VSS_131
VSS_132
VSS_133
VSS_134
VSS_135
VSS_136
VSS_137
VSS_138
VSS_139
VSS_140
VSS_141
VSS_142
VSS_143
VSS_144
VSS_145
VSS_146
VSS_147
VSS_148
VSS_149
VSS_150
VSS_151
VSS_152
VSS_153
VSS_154
VSS_155
VSS_156
VSS_157
VSS_158
VSS_159
VSS_160
VSS_161
VSS_162
VSS_163
VSS_164
VSS_165
VSS_166
VSS_167
VSS_168
VSS_169
VSS_170
VSS_171
VSS_172
VSS_173
VSS_174
VSS_175
VSS_176
VSS_177
VSS_178
VSS_179
VSS_180
VSS_181
VSS_182
VSS_183
VSS_184
VSS_185
VSS_186
VSS_187
VSS_188
VSS_189
VSS_190
VSS_191
VSS_192
VSS_193
VSS_194
VSS_195
VSS_196
VSS_197
VSS_198

4

AW24
AW29
AW32
AW5
AW7
AY10
AY24
AY37
AY42
AY43
AY45
AY47
AY50
B10
B20
B24
B29
B30
B35
B38
B43
B46
B5
B8
BA1
BA17
BA18
BA2
BA24
BB12
BB25
BB40
BB44
BB49
BB8
BC16
BC24
BC25
BC36
BC40
BC51
BD13
BD2
BD28
BD45
BD48
BD5
BE1
BE19
BE23
BE30
BE42
BE51
BE8
BF12
BF16
BF36
BG19
BG2
BG24
BG29
BG39
BG48
BG5
BG51
BH17
BH30
BH44
BH46
BH8
BJ11
BJ13
BJ38
BJ4
BJ42
BJ46
BK15
BK17
BK25
BK29
BK36
BK40
BK44
BK6
BK8
BL11
BL13
BL19
BL22
BL37
BL47
C12
C16
C19
C28
C29
C33
C36
C41

3

U3J

C46

VSS_199

C50

VSS_200

C7

VSS_201

D13

VSS_202

D24

VSS_203

D3

VSS_204

D32

VSS_205

D39

VSS_206

D45

VSS_207

D49

VSS_208

E10

VSS_209

E16

VSS_210

E24

VSS_211

E28

VSS_212

E32

VSS_213

E47

VSS_214

F19

VSS_215

F36

VSS_216

F4

VSS_217

F40

VSS_218

F50

VSS_219

G1

VSS_220

G13

VSS_221

G16

VSS_222

G19

VSS_223

G24

VSS_224

G28

VSS_225

G29

VSS_226

G33

VSS_227

G42

VSS_228

G45

VSS_229

G48

VSS_230

G8

VSS_231

H24

VSS_232

H28

VSS_233

H4

VSS_234

H45

VSS_235

J11

VSS_236

J16

VSS_237

J2

VSS_238

J24

VSS_239

J28

VSS_240

J33

VSS_241

J35

VSS_242

J39

VSS_243

K12

VSS_245

K47

VSS_246

K8

VSS_247

L1

VSS_248

L17

VSS_249

L20

VSS_250

L24

VSS_251

L28

VSS_252

L3

VSS_253

L33

VSS_254

L49

VSS_255

M28

VSS_256

M42

VSS_257

M46

VSS_258

M49

VSS_259

M5

VSS_260

M50

VSS_261

M9

VSS_262

N11

VSS_263

N14

VSS_264

N17

VSS_265

N29

VSS_266

N32

VSS_267

N36

VSS_268

N39

VSS_269

N44

VSS_270

N49

VSS_271

N7

VSS_272

P19

VSS_273

P2

VSS_274

P23

VSS_275

P3

VSS_276

P50

VSS_277

R49

VSS_278

T39

VSS_279

T43

VSS_280

T47

VSS_281

U41

VSS_282

U45

VSS_283

U50

VSS_284

V2

VSS_285

V3

VSS_286

CRESTLINE_1p0 UMA@

VSS

VSS_287
VSS_288
VSS_289
VSS_290
VSS_291
VSS_292
VSS_293
VSS_294
VSS_295
VSS_296
VSS_297
VSS_298
VSS_299
VSS_300
VSS_301
VSS_302
VSS_303
VSS_304
VSS_305

VSS_306
VSS_307
VSS_308
VSS_309
VSS_310
VSS_311
VSS_312
VSS_313

W11
W39
W43
W47
W5
W7
Y13
Y2
Y41
Y45
Y49
Y5
Y50
Y11
P29
T29
T31
T33
R28

AA32
AB32
AD32
AF28
AF29
AT27
AV25
H50

2

1

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2007/12/28 2007/12/28

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

Compal Electronics, Inc.

Crestline(6/6)_GND

LA-4131P

1

0.2

of

12 53Monday, February 18, 2008

5

DDR_A_DQS#[0..7]8

DDR_A_D[0..63]8

DDR_A_DM[0..7]8
DDR_A_DQS[0..7]8
DDR_A_MA[0..13]8

D D

Layout Note:
Place near JDIM1

+DDR_MCH_REF17,14

close to connector

+1.8V

2.2U_0603_6.3V6K

0.1U_0402_16V4Z

1

2

C57

2.2U_0603_6.3V6K

C65

1

1

2

2

DDR_A_V

0.1U_0402_16V4Z

1

1

2

2

C74

C58

RP24

RP26

56_0404_4P2R_5%

1 4
2 3

RP18

56_0404_4P2R_5%

1 4
2 3

RP22

56_0404_4P2R_5%

RP23

56_0404_4P2R_5%

1 4
2 3

RP21

56_0404_4P2R_5%

56_0404_4P2R_5%

1 2

R47 56_0402_5%

C530

2.2U_0603_6.3V6K

1

2

0.1U_0402_16V4Z

1

2

C73

DDR_A_V

23
14

23
14

14
23

5

0.1U_0402_16V4Z

2.2U_0603_6.3V6K
C93

C531

1

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

2

2

C72

C69

56_0404_4P2R_5%

RP27

DDR_CKE0_DIMMA

2 3

DDR_A_MA12

1 4

RP20 56_0404_4P2R_5%

DDR_A_MA7

14

DDR_A_MA6

23

RP25 56_0404_4P2R_5%

DDR_A_BS#2

2 3

DDR_A_MA9

1 4

RP19 56_0404_4P2R_5%

DDR_A_MA2

14

DDR_A_MA4

23

RP15 56_0404_4P2R_5%

DDR_A_BS#1

14

DDR_A_MA0

23

RP17 56_0404_4P2R_5%

M_ODT0

14

DDR_A_MA13

23

RP16 56_0404_4P2R_5%

DDR_A_MA11

14

DDR_A_MA14

23

0.1U_0402_16V4Z

C520

1

2

0.1U_0402_16V4Z

1

2

C85

0.1U_0402_16V4Z

C522

C521

1

1

2

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

2

2

C71

C70

2.2U_0603_6.3V6K
C94

1

2

Layout Note:

C C

Place one cap close to every 2 pullup
resistors terminated to +0.9V

+0.9VS

0.1U_0402_16V4Z

B B

DDR_A_MA8
DDR_A_MA5

DDR_A_MA1
DDR_A_MA3

DDR_A_RAS#
DDR_CS0_DIMMA#

DDR_A_BS#0
DDR_A_MA10

DDR_A_CAS#
DDR_A_WE#

DDR_CS1_DIMMA#

A A

M_ODT1

DDR_CKE1_DIMMA

4

Layout Note:
+DDR_MCH_REF1
trace width and
spacing is 20/20.

+DDR_MCH_REF1

1

C64

2

0.1U_0402_16V4Z~N

330U_D2_2.5VY_R9M

0.1U_0402_16V4Z

1

2

C44

1

C101

C517

1

+

2

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

2

2

C45

C56

Layout Note:
Place these resistor
closely JDIM1,
all trace length Max=1.5"

4

3

+1.8V

+1.8V

+3VS

C79

0.1U_0402_16V4Z

DDR_A_D4
DDR_A_D1

DDR_A_DQS#0
DDR_A_DQS0

DDR_A_D2
DDR_A_D3

DDR_A_D8
DDR_A_D14

DDR_A_DQS#1
DDR_A_DQS1

DDR_A_D9

DDR_A_D16
DDR_A_D17

DDR_A_DQS#2
DDR_A_DQS2

DDR_A_D18
DDR_A_D19

DDR_A_D29
DDR_A_D24

DDR_A_DM3

DDR_A_D26
DDR_A_D27

DDR_CKE0_DIMMA

DDR_A_BS#2
DDR_A_MA12
DDR_A_MA8
DDR_A_MA5

DDR_A_MA3
DDR_A_MA1

DDR_A_MA10
DDR_A_BS#0

DDR_A_CAS#
DDR_CS1_DIMMA#

M_ODT1
DDR_A_D37

DDR_A_D36
DDR_A_DQS#4

DDR_A_DQS4
DDR_A_D35

DDR_A_D34
DDR_A_D40

DDR_A_D44
DDR_A_DM5
DDR_A_D41

DDR_A_D46
DDR_A_D49

DDR_A_D48

DDR_A_DQS#6
DDR_A_DQS6

DDR_A_D54
DDR_A_D50

DDR_A_D61
DDR_A_D60

DDR_A_DM7
DDR_A_D59

DDR_A_D58
ICH_SM_DA

ICH_SM_CLK

1

1

2

2

C80

2.2U_0603_6.3V6K

12

R43
1K_0402_1%

12

R42
1K_0402_1%

DDR_CKE0_DIMMA7

DDR_A_BS#28

DDR_A_BS#08

DDR_A_WE#8

DDR_A_CAS#8

0.1U_0402_16V4Z

1

2

C63

DDR_CS1_DIMMA#7

M_ODT17

ICH_SM_DA14,16,19

ICH_SM_CLK14,16,19

JDIM1

1

VREF

3

VSS

5

DQ0

7

DQ1

9

VSS

11

DQS0#

13

DQS0

15

VSS

17

DQ2

19

DQ3

21

VSS

23

DQ8

25

DQ9

27

VSS

29

DQS1#

31

DQS1

33

VSS

35

DQ10

37

DQ11

39

VSS

41

VSS

43

DQ16

45

DQ17

47

VSS

49

DQS2#

51

DQS2

53

VSS

55

DQ18

57

DQ19

59

VSS

61

DQ24

63

DQ25

65

VSS

67

DM3

69

NC

71

VSS

73

DQ26

75

DQ27

77

VSS

79

CKE0

81

VDD

83

NC

85

BA2

87

VDD

89

A12

91

A9

93

A8

95

VDD

97

A5

99

A3

101

A1

103

VDD

105

A10/AP

107

BA0

109

WE#

111

VDD

113

CAS#

115

NC/S1#

117

VDD

119

NC/ODT1

121

VSS

123

DQ32

125

DQ33

127

VSS

129

DQS4#

131

DQS4

133

VSS

135

DQ34

137

DQ35

139

VSS

141

DQ40

143

DQ41

145

VSS

147

DM5

149

VSS

151

DQ42

153

DQ43

155

VSS

157

DQ48

159

DQ49

161

VSS

163

NC,TEST

165

VSS

167

DQS6#

169

DQS6

171

VSS

173

DQ50

175

DQ51

177

VSS

179

DQ56

181

DQ57

183

VSS

185

DM7

187

VSS

189

DQ58

191

DQ59

193

VSS

195

SDA

197

SCL

199

VDDSPD

FOX_ASOA426-M2RN-7F

CONN@

SO-DIMM A

VSS
DQ4
DQ5

VSS
DM0

VSS
DQ6
DQ7

VSS

DQ12
DQ13

VSS
DM1

VSS

CK0

CK0#

VSS

DQ14
DQ15

VSS

VSS

DQ20
DQ21

VSS
DM2

VSS

DQ22
DQ23

VSS

DQ28
DQ29

VSS

DQS3#

DQS3

VSS

DQ30
DQ31

VSS

NC/CKE1

VDD

NC/A15
NC/A14

VDD

VDD

VDD

BA1

RAS#

VDD

ODT0

NC/A13

VDD

VSS

DQ36
DQ37

VSS
DM4

VSS

DQ38
DQ39

VSS

DQ44
DQ45

VSS

DQS5#

DQS5

VSS

DQ46
DQ47

VSS

DQ52
DQ53

VSS

CK1

CK1#

VSS
DM6

VSS

DQ54
DQ55

VSS

DQ60
DQ61

VSS

DQS7#

DQS7

VSS

DQ62
DQ63

VSS

SA0

SA1

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

42
44
46
48
50

NC

52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90

A11

92

A7

94

A6

96
98

A4

100

A2

102

A0

104
106
108
110

S0#

112
114
116
118
120

NC

122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200

2

DDR_A_D6
DDR_A_D0

DDR_A_DM0
DDR_A_D5

DDR_A_D7
DDR_A_D13

DDR_A_D12
DDR_A_DM1
M_CLK_DDR0

M_CLK_DDR#0
DDR_A_D11

DDR_A_D10DDR_A_D15

DDR_A_D20
DDR_A_D21

DDR_A_DM2
DDR_A_D23

DDR_A_D22
DDR_A_D28

DDR_A_D25
DDR_A_DQS#3

DDR_A_DQS3
DDR_A_D31

DDR_A_D30
DDR_CKE1_DIMMA

DDR_A_MA14
DDR_A_MA11

DDR_A_MA7DDR_A_MA9
DDR_A_MA6

DDR_A_MA4
DDR_A_MA2
DDR_A_MA0

DDR_A_BS#1
DDR_A_RAS#
DDR_CS0_DIMMA#DDR_A_WE#

M_ODT0
DDR_A_MA13

DDR_A_D32
DDR_A_D33

DDR_A_DM4
DDR_A_D39

DDR_A_D38
DDR_A_D45

DDR_A_D43
DDR_A_DQS#5

DDR_A_DQS5
DDR_A_D47

DDR_A_D42
DDR_A_D52

DDR_A_D53
M_CLK_DDR1

M_CLK_DDR#1
DDR_A_DM6
DDR_A_D51

DDR_A_D55
DDR_A_D57

DDR_A_D56
DDR_A_DQS#7

DDR_A_DQS7
DDR_A_D62

DDR_A_D63

12

R49

R48

10K_0402_5%

10K_0402_5%

Close to VREF pins of SO-DIMM

2.2U_0805_16V4Z
C53

1

2

M_CLK_DDR0 7
M_CLK_DDR#0 7

PM_EXTTS#0 7

DDR_CKE1_DIMMA 7

DDR_A_MA14 7

DDR_A_BS#1 8
DDR_A_RAS# 8
DDR_CS0_DIMMA# 7

M_ODT0 7

M_CLK_DDR1 7
M_CLK_DDR#1 7

12

1

+DDR_MCH_REF1

0.1U_0402_16V4Z
C51

1

2

Bottom side

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2007/12/28 2007/12/28

3

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

Compal Electronics, Inc.

DDR2 SO-DIMM I

LA-4131P

0.2

of

13 53Monday, February 18, 2008

1

5

DDR_B_DQS#[0..7]8

DDR_B_D[0..63]8

DDR_B_DM[0..7]8

DDR_B_DQS[0..7]8

DDR_B_MA[0..13]8

D D

Layout Note:
Place near JDIM2

+1.8V

2.2U_0603_6.3V6K

2.2U_0603_6.3V6K
C67

1

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

2

C81

RP14

RP10

RP6

RP12

RP9

RP8

R36 56_0402_5%

2.2U_0603_6.3V6K
C66

1

2

0.1U_0402_16V4Z

1

2

C62

56_0404_4P2R_5%

56_0404_4P2R_5%

1 4
2 3

56_0404_4P2R_5%

56_0404_4P2R_5%

56_0404_4P2R_5%

56_0404_4P2R_5%

1 2

5

C49

1

2

Layout Note:
Place one cap close to every 2 pullup
resistors terminated to +0.9VS

C C

+0.9VS

0.1U_0402_16V4Z

1

2

C83

B B

DDR_CKE2_DIMMB
DDR_B_BS#2

DDR_B_MA8
DDR_B_MA5

DDR_CS2_DIMMB#
DDR_B_BS#1

DDR_B_WE#
DDR_B_CAS#

A A

DDR_B_MA10
DDR_B_BS#0

M_ODT3
DDR_CS3_DIMMB# M_ODT2

DDR_CKE3_DIMMB

1

2

23
14

23
14

23
14

23
14

14
23

C82

2.2U_0603_6.3V6K

1

2

0.1U_0402_16V4Z

DDR_B_V

2 3
1 4

2 3
1 4

2.2U_0603_6.3V6K

0.1U_0402_16V4Z

C78

C76

1

2

DDR_B_V

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

2

C84

RP4 56_0404_4P2R_5%

RP3 56_0404_4P2R_5%

RP11

RP7 56_0404_4P2R_5%

RP13 56_0404_4P2R_5%

RP2 56_0404_4P2R_5%

RP5

56_0404_4P2R_5%

1

2

2

C86

DDR_B_MA7

14

DDR_B_MA6

23

DDR_B_MA4

14

DDR_B_MA2

23

56_0404_4P2R_5%

DDR_B_MA12
DDR_B_MA9

DDR_B_MA0

14

DDR_B_RAS#

23

DDR_B_MA3
DDR_B_MA1

DDR_B_MA13

14
23

DDR_B_MA14

14

DDR_B_MA11

23

0.1U_0402_16V4Z

0.1U_0402_16V4Z

C518

C523

1

1

2

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

2

2

C61

C59

C87

4

0.1U_0402_16V4Z

C519

1

1

2

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

2

2

C60

C47

Layout Note:
Place these resistor
closely JDIM2,
all trace length Max=1.5"

4

3

+1.8V

JDIM2

1

VREF

3

DDR_B_D0
DDR_B_D1

DDR_B_DQS#0
DDR_B_DQS0

DDR_B_D2
DDR_B_D3

DDR_B_D8
DDR_B_D9

DDR_B_DQS#1
DDR_B_DQS1

DDR_B_D10
DDR_B_D11

330U_D2_2.5VY_R9M

1

C100

C68

+

@

2

DDR_CKE2_DIMMB7

DDR_B_BS#08

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

2

2

C48

C46

DDR_B_WE#8

DDR_B_CAS#8

DDR_CS3_DIMMB#7

M_ODT37

ICH_SM_DA13,16,19

ICH_SM_CLK13,16,19

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

DDR_B_D17
DDR_B_D20

DDR_B_DQS#2
DDR_B_DQS2

DDR_B_D18
DDR_B_D19

DDR_B_D28
DDR_B_D25

DDR_B_DM3

DDR_B_D30
DDR_B_D31

DDR_CKE2_DIMMB

DDR_B_BS#2
DDR_B_MA12

DDR_B_MA9
DDR_B_MA8

DDR_B_MA5
DDR_B_MA3
DDR_B_MA1

DDR_B_MA10
DDR_B_BS#0
DDR_B_WE#

DDR_B_CAS#
DDR_CS3_DIMMB#

M_ODT3
DDR_B_D32

DDR_B_D33
DDR_B_DQS#4

DDR_B_DQS4
DDR_B_D34

DDR_B_D35
DDR_B_D40

DDR_B_D41
DDR_B_DM5
DDR_B_D42

DDR_B_D43
DDR_B_D48

DDR_B_D49

DDR_B_DQS#6
DDR_B_DQS6

DDR_B_D51
DDR_B_D50

DDR_B_D56
DDR_B_D61

DDR_B_DM7
DDR_B_D59

DDR_B_D58
ICH_SM_DA

ICH_SM_CLK

+3VS

1

2

1

C55

2.2U_0603_6.3V6K

2

C54

0.1U_0402_16V4Z

2007/12/28 2007/12/28

3

VSS

5

DQ0

7

DQ1

9

VSS

11

DQS0#

13

DQS0

15

VSS

17

DQ2

19

DQ3

21

VSS

23

DQ8

25

DQ9

27

VSS

29

DQS1#

31

DQS1

33

VSS

35

DQ10

37

DQ11

39

VSS

41

VSS

43

DQ16

45

DQ17

47

VSS

49

DQS2#

51

DQS2

53

VSS

55

DQ18

57

DQ19

59

VSS

61

DQ24

63

DQ25

65

VSS

67

DM3

69

NC

71

VSS

73

DQ26

75

DQ27

77

VSS

79

CKE0

81

VDD

83

NC

85

BA2

87

VDD

89

A12

91

A9

93

A8

95

VDD

97

A5

99

A3

101

A1

103

VDD

105

A10/AP

107

BA0

109

WE#

111

VDD

113

CAS#

115

NC/S1#

117

VDD

119

NC/ODT1

121

VSS

123

DQ32

125

DQ33

127

VSS

129

DQS4#

131

DQS4

133

VSS

135

DQ34

137

DQ35

139

VSS

141

DQ40

143

DQ41

145

VSS

147

DM5

149

VSS

151

DQ42

153

DQ43

155

VSS

157

DQ48

159

DQ49

161

VSS

163

NC,TEST

165

VSS

167

DQS6#

169

DQS6

171

VSS

173

DQ50

175

DQ51

177

VSS

179

DQ56

181

DQ57

183

VSS

185

DM7

187

VSS

189

DQ58

191

DQ59

193

VSS

195

SDA

197

SCL

199

VDDSPD

FOX_AS0A426-NARN-7F~N

CONN@

SO-DIMM B

Bottom side

Compal Secret Data

Deciphered Date

VSS
DQ4
DQ5

VSS
DM0

VSS
DQ6
DQ7

VSS

DQ12
DQ13

VSS
DM1

VSS

CK0

CK0#

VSS

DQ14
DQ15

VSS

VSS

DQ20
DQ21

VSS
DM2

VSS

DQ22
DQ23

VSS

DQ28
DQ29

VSS

DQS3#

DQS3

VSS

DQ30
DQ31

VSS

NC/CKE1

VDD

NC/A15
NC/A14

VDD

VDD

VDD

BA1

RAS#

VDD

ODT0

NC/A13

VDD

VSS

DQ36
DQ37

VSS
DM4

VSS

DQ38
DQ39

VSS

DQ44
DQ45

VSS

DQS5#

DQS5

VSS

DQ46
DQ47

VSS

DQ52
DQ53

VSS

CK1

CK1#

VSS
DM6

VSS

DQ54
DQ55

VSS

DQ60
DQ61

VSS

DQS7#

DQS7

VSS

DQ62
DQ63

VSS
SAO

SA1

NC

A11

A7
A6

A4
A2
A0

S0#

NC

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200

2

+DDR_MCH_REF1

DDR_B_D5
DDR_B_D4

DDR_B_DM0
DDR_B_D6

DDR_B_D7
DDR_B_D12

DDR_B_D13
DDR_B_DM1
M_CLK_DDR2

M_CLK_DDR#2
DDR_B_D14

DDR_B_D15

DDR_B_D21
DDR_B_D16

DDR_B_DM2
DDR_B_D22

DDR_B_D23
DDR_B_D26

DDR_B_D24
DDR_B_DQS#3

DDR_B_DQS3
DDR_B_D29

DDR_B_D27
DDR_CKE3_DIMMB

DDR_B_MA14
DDR_B_MA11

DDR_B_MA7
DDR_B_MA6

DDR_B_MA4
DDR_B_MA2
DDR_B_MA0

DDR_B_BS#1
DDR_B_RAS#
DDR_CS2_DIMMB#

M_ODT2
DDR_B_MA13

DDR_B_D36
DDR_B_D37

DDR_B_DM4
DDR_B_D39

DDR_B_D38
DDR_B_D44

DDR_B_D45
DDR_B_DQS#5

DDR_B_DQS5
DDR_B_D46

DDR_B_D47
DDR_B_D52

DDR_B_D53
M_CLK_DDR3

M_CLK_DDR#3
DDR_B_DM6
DDR_B_D54

DDR_B_D55
DDR_B_D60

DDR_B_D57
DDR_B_DQS#7

DDR_B_DQS7
DDR_B_D62

DDR_B_D63

10K_0402_5%

2

1

Close to VREF pins of SO-DIMM

0.1U_0402_16V4Z

2.2U_0805_16V4Z

M_CLK_DDR2 7
M_CLK_DDR#2 7

PM_EXTTS#1 7

DDR_CKE3_DIMMB 7

DDR_B_MA14 7DDR_B_BS#28

DDR_B_BS#1 8
DDR_B_RAS# 8
DDR_CS2_DIMMB# 7

M_ODT2 7

M_CLK_DDR3 7
M_CLK_DDR#3 7

R37

1 2

12

10K_0402_5%

R38

Title

DDR2 SO-DIMM II

Size Document Number Rev

Custom

LA-4131P

Date: Sheet

1

1

C50

C52

2

2

+3VS

Compal Electronics, Inc.

+DDR_MCH_REF1 7,13

1

0.2

of

14 53Monday, February 18, 2008

A

C R T

VGA@

VGA_CRT_B34

VGA_CRT_G34

VGA_CRT_R34

1 1

CRT_R9

CRT_G9

CRT_B9

CRT_HSYNC9

VGA_HSYNC34

2 2

VGA_VSYNC34

CRT_VSYNC9

12

R336 0_0402_5%

VGA@

12

R341 0_0402_5%

VGA@

12

R338 0_0402_5%

UMA@

12

R339 0_0402_5%

UMA@

12

R342 0_0402_5%

UMA@

12

R335 0_0402_5%

C9 0.1U_0402_16V4Z

CRT_HSYNC

CRT_VSYNC

UMA@

1 2

R406 30_0402_1%

VGA@

R405 0_0402_5%

VGA@

R401 0_0402_5%

UMA@

1 2

R404 30_0402_1%

Close to GMCH

12

R340

150_0402_1%

1 2

12

12

12

R337

R334

150_0402_1%

CRT_HSYNC_B

CRT_VSYNC_B

Close to VGA

CRT_R_C

CRT_G_C

CRT_B_C

12

150_0402_1%

+CRT_VCC

C13 0.1U_0402_16V4Z

D22

DAN217_SC59-3

1

+3VS

2

3

VGA@

1

C455

C456

@

5

P

A2Y

G

3

1 2

@

2

22P_0402_50V8J

1

4

OE#

U4

74AHCT1G125GW_SOT353-5

D23

DAN217_SC59-3

2

VGA@

1

2

22P_0402_50V8J

+CRT_VCC

D24

DAN217_SC59-3

1

2

3

VGA@

1 2

BK1608LL121-T 0603

1 2

BK1608LL121-T 0603

1 2

BK1608LL121-T 0603

1

C457

For EMI

@

2

22P_0402_50V8J

R15 10K_0402_5%

1

5

P

4

OE#

A2Y

G

U574AHCT1G125GW_SOT353-5

3

B

1

For nVIDIA

3

L25

L24

L23

12

D_CRT_HSYNC

D_CRT_VSYNC

CRT_R_L

CRT_G_L

CRT_B_L

C452

1

1

C451

2

2

4.7P_0402_50V8C

1 2

R16 0_0603_5%

1 2

R6 0_0603_5%

4.7P_0402_50V8C

C450

C

+5VS

C5

1

2

100P_0402_50V8J

D21

2 1

RB411DT146 SOT23

C6

0.1U_0402_16V4Z

C7

C1

1

1

2

2

100P_0402_50V8J

100P_0402_50V8J

1 2

R8
0_1206_5%~D

MSEN#28

1

2

4.7P_0402_50V8C

HSYNC_L

C3

C2

1

2

C4

1

1

2

2

15P_0402_50V8J

15P_0402_50V8J

+CRT_VCC

1

2

100P_0402_50V8J

W=40milsW=40mils

@

1

C448

2

0.1U_0402_16V4Z
JCRT1

6

11

1
7

12

2
8

13

3
9

14

4
10
15

5

SUYIN_070549FR015S208CR

VGA_DDC_DATA_C

VGA_DDC_CLK_CVSYNC_L

16
17

CONN@

D

原本為

4.7K

R7

1 2

2K_0402_5%

R2

2K_0402_5%

1 2

R3

1 2
2

G

2.2K_0402_5%

1 3

D

Q2BSS138_NL_SOT23

BSS138_NL_SOT23

+3VS

S

2

1 3

D

Q1

D18

@

DAN217_SC59-3

2

CRT_B_L

原本為

R20

1 2

2.2K_0402_5%

G

S

1

3

10K

+3VS+CRT_VCC +3VS+CRT_VCC +3VS

1 2

E

D19

@

DAN217_SC59-3

CRT_G_L

R11

2.2K_0402_5%

R14 0_0402_5%

R12 0_0402_5%

R13 0_0402_5%

R21 0_0402_5%

2

UMA@

UMA@

VGA@

VGA@

1

3

DAN217_SC59-3

CRT_R_L

12

12

12

12

D20

@

1

For ESD.

2

3

Close to JCRT1.

3VDDCDA 9

3VDDCCL 9

VGA_DDCCLK 34

VGA_DDCDATA 34

EDID_CLK_LCD
EDID_DAT_LCD

C461

LVDSBC+
LVDSBC-

LVDSB0+
LVDSB0-

LVDSB1+
LVDSB1-

LVDSB2+
LVDSB2-

BIA_PWM9

+3VALW

47K_0402_5%

12

R17

JP4

1
3
5
7
9

11
13
15
17
19
21
23
25
27
29
31
33
35
37
39

87242-4001-09 40P

CONN@

@

BIA_PWM INVT_PWM

10_0402_5%

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
GND41GND

R343

1N4148_SOT23@

2

2

4

4

6

6

8

8

10

10

12

12

14

14

16

16

18

18

20

20

22

22

24

24

26

26

28

28

30

30

32

32

34

34

36

36

38

38

40

40

42

12

D25

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

BISTLCD_DET#
LVDSAC+

LVDSAC­LVDSA0+

LVDSA0­LVDSA1+

LVDSA1­LVDSA2+

LVDSA2­EC_SMB_CK1

EC_SMB_DA1
INVT_PWM

INVPWR_B+
INVPWR_B+

12

1

2

BIST 28

EC_SMB_CK1 28,49
EC_SMB_DA1 28,49
INVT_PWM 28

INVPWR_B+

C453

1U_0603_10V4Z@

2007/12/28 2007/12/28

Compal Secret Data

Deciphered Date

GMCH_LVDSAC+9

GMCH_LVDSAC-9
GMCH_LVDSA0+9

GMCH_LVDSA0-9
GMCH_LVDSA1+9

GMCH_LVDSA1-9
GMCH_LVDSA2+9

GMCH_LVDSA2-9

GMCH_LVDSBC+9

GMCH_LVDSBC-9
GMCH_LVDSB0+9

GMCH_LVDSB0-9
GMCH_LVDSB1+9

GMCH_LVDSB1-9
GMCH_LVDSB2+9

GMCH_LVDSB2-9

GMCH_EDID_CLK_LCD9
GMCH_EDID_DAT_LCD9

VGA_LVDSAC+36
VGA_LVDSAC-36

VGA_LVDSA0+36
VGA_LVDSA0-36

VGA_LVDSA1+36
VGA_LVDSA1-36

VGA_LVDSA2+36
VGA_LVDSA2-36

VGA_LVDSBC+36
VGA_LVDSBC-36

VGA_LVDSB0+36
VGA_LVDSB0-36

VGA_LVDSB1+36
VGA_LVDSB1-36

VGA_LVDSB2+36
VGA_LVDSB2-36

VGA_CLK_LCD34
VGA_DAT_LCD34

D

LCD_TEST_EN

1

C466

2

0.1U_0603_50V4Z~D
2200P_0402_50V7K~D

A

+3VALW

0.1U_0402_16V7K~N

C469

1

2

2 1

D27 CH751H-40PT_SOD323-2@

2 1

D28 CH751H-40PT_SOD323-2@

R358

1 2

0_0402_5%

W=60mils

B+

1

C465

2

1000P_0402_50V7K~D

W=60mils

12

R356
200K_0402_5%~D

100K_0402_5%~D

SUSP#26,28,32,44,47

U54

IN6OUT
EN3NC

5

GND

GND

AOZ1320CI-04_SOT23-6

R357
10K_0402_5%

1 2

FDS4435: P Channel MOS

Q29

FDS4435BZ_SO8~D

R22

8
7

1

6

2

5

3

4

Q3

2N7002W-7-F_SOT323-3~D

D

S

12

1 3

G

2

W=60mils

1
4
2

INVPWR_B+

1

2

+LCDVDD

+LCDVDD

C463 4.7U_0805_6.3V6K~N

1

2

W=60mils

C460

0.1U_0603_50V4Z~D

C462 0.1U_0402_16V7K~N

1

LCD_DET#28
+5VALW

2

+LCDVDD

+3VS

0.1U_0402_16V4Z

1

2

B

L C D

GMCH_LVDDEN9,28

VGA_LVDDEN28,34

3 3

LCD_TEST_EN28

1

C467

2

4 4

GMCH_LVDSAC+

GMCH_LVDSAC­GMCH_LVDSA0+

GMCH_LVDSA0-

GMCH_LVDSA1+ LVDSA1+

GMCH_LVDSA1-

GMCH_LVDSA2+

GMCH_LVDSA2-

GMCH_LVDSBC+

GMCH_LVDSBC­GMCH_LVDSB0+

GMCH_LVDSB0-

GMCH_LVDSB1+

GMCH_LVDSB1-

GMCH_LVDSB2+

GMCH_LVDSB2-

GMCH_EDID_CLK_LCD
GMCH_EDID_DAT_LCD

VGA_LVDSAC+
VGA_LVDSAC-

VGA_LVDSA0+
VGA_LVDSA0-

VGA_LVDSA1+
VGA_LVDSA1-

VGA_LVDSA2+
VGA_LVDSA2-

VGA_LVDSBC+
VGA_LVDSBC-

VGA_LVDSB0+
VGA_LVDSB0-

VGA_LVDSB1+
VGA_LVDSB1-

VGA_LVDSB2+
VGA_LVDSB2-

VGA_DAT_LCD EDID_DAT_LCD

R418 0_0402_5% VGA@

1 2

R417 0_0402_5% VGA@

1 2

R461 0_0402_5% VGA@

1 2

R460 0_0402_5% VGA@

1 2

R463 0_0402_5% VGA@

1 2

R462 0_0402_5% VGA@

1 2

R449 0_0402_5% VGA@

1 2

R439 0_0402_5% VGA@

1 2

R459 0_0402_5% VGA@

1 2

R458 0_0402_5% VGA@

1 2

R454 0_0402_5% VGA@

1 2

R455 0_0402_5% VGA@

1 2

R452 0_0402_5% VGA@

1 2

R453 0_0402_5% VGA@

1 2

R456 0_0402_5% VGA@

1 2

R457 0_0402_5% VGA@

1 2

R353 0_0402_5% VGA@

1 2

R350 0_0402_5% VGA@

1 2

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

CRT Conn / LCD Conn

LA-4131P

12
12

12
12

12
12

12
12

12
12

12
12

12
12

12
12

12
12

E

R4220_0402_5% UMA@
R4210_0402_5% UMA@

R4350_0402_5% UMA@
R4340_0402_5% UMA@

R4370_0402_5% UMA@
R4360_0402_5% UMA@

R4480_0402_5% UMA@
R4380_0402_5% UMA@

R4330_0402_5% UMA@
R4320_0402_5% UMA@

R4280_0402_5% UMA@
R4290_0402_5% UMA@

R4260_0402_5% UMA@
R4270_0402_5% UMA@

R4300_0402_5% UMA@
R4310_0402_5% UMA@

R3520_0402_5% UMA@
R3490_0402_5% UMA@

LVDSAC+

LVDSAC­LVDSA0+

LVDSA0-

LVDSA1-

LVDSA2+

LVDSA2-

LVDSBC+

LVDSBC­LVDSB0+

LVDSB0-

LVDSB1+

LVDSB1-

LVDSB2+

LVDSB2-

EDID_CLK_LCD
EDID_DAT_LCD

LVDSAC+
LVDSAC-

LVDSA0+
LVDSA0-

LVDSA1+
LVDSA1-

LVDSA2+
LVDSA2-

LVDSBC+
LVDSBC-

LVDSB0+
LVDSB0-

LVDSB1+
LVDSB1-

LVDSB2+
LVDSB2-

EDID_CLK_LCDVGA_CLK_LCD

15 53Monday, February 18, 2008

0.2

of

5

PCI

SRC

CPU

CLKSEL1

1

1

FSLA

CLKSEL0

MHz

200

166

MHz

1000

100

MHz

33.30

33.3

FSLC1FSLB

CLKSEL2

0

FSB Frequency Selet:

D D

CPU Driven

(Default)

*

Stuff

No Stuff

Stuff

667MHz

No Stuff

Stuff

800MHz

CPU_BSEL05

C C

CPU_BSEL15

CPU_BSEL25

B B

A A

18P_0402_50V8J~N

No Stuff

R548

2.2K_0402_5%

FSA

1 2

R550

0_0402_5%

FSB

1 2

R501

0_0402_5%

R516

10K_0402_5%

FSC

1 2

R519

@

0_0402_5%

Y4

14.31818MHz_20P_1BX14318BE1A

2

C667

1

Routing the trace at least 10mil

R1107 R1135 R1083

R1074 R1086 R1098 R1113 R1139

R1139 R1135R1135 R1139

R1083

R1107

R1128

R1098

R1113

R1135 R1139

R1083

R1086
R1107

@

R1098
R1113

MCH_CLKSEL0 7

MCH_CLKSEL1 7

MCH_CLKSEL2 7

R1074

12

1 2

R556

+VCCP

12

1K_0402_5%

R502
1K_0402_5%

1 2

1 2

R499

1K_0402_5%

1 2

R517

1K_0402_5%

12

R514

0_0402_5%

For ITP_EN, 0 =SRC8/SRC8#; 1 = ITP/ITP#
For 27_SEL, 0 = Enable DOT96 & SRC1,

For PCI2_EN, 0 = Overclocking of CPU and SRC Allowed

CLK_XTAL_OUT

CLK_XTAL_IN

Placed
within 500
mils of
CK505M

12

2

C666
18P_0402_50V8J~N

1

5

1 2

R1128

R1074R1086

R1128

CLKSATAREQ#19

CLKMCHREQ#7

CLK_PCI_CB25,28
CLK_PCI_TPM28

CLK_DEBUG_PORT27

CLK_PCI_EC28
CLK_PCI_ICH17

CLK_48M_ICH19

CLK_14M_ICH19
CLK_14M_SIO

1 = Enable SRC0 & 27MHz

1 = Overclocking of CPU and SRC NOT allowed

+3VM_CK505

ITP_EN

R534
10K_0402_5%

R549
10K_0402_5%

VGA@

1 2

27_SEL

R545
10K_0402_5%

UMA@

1 2

4

3

2

1

Place these caps close to U6

+3VM_CK505

R521

1 2

+3VS

0_0805_5%

+1.25VM_CK505

R520

1 2

+1.25VS

0_0805_5%

+3VM_CK505

+1.25VM_CK505

+3VS
+3VS

+3VM_CK505

4

R52410K_0402_5%

R53010K_0402_5%

1 2
1 2
1 2

1 2
1 2

1 2
1 2

1 2

1 2
1 2

R535

10K_0402_5%

1 2

PCI2_TME

R531

10K_0402_5%

@

1 2

12
12

R525475_0402_1%
R529475_0402_1%
R52733_0402_5%

R52833_0402_5%
R53233_0402_5%

R53633_0402_5%
R52633_0402_5%

R53333_0402_5%

R51533_0402_5%
R50933_0402_5%

+1.25VM_CK505

SATA_REQ
MCH_REQ
PCI2_TME
PCI_CLK3
27_SEL
ITP_EN

CLK_XTAL_IN
CLK_XTAL_OUT

FSA

FSB

FSC

+3VM_CK505 = 250 mA

1

C684
10U_0805_10V4Z~N

2

1

C687

0.1U_0402_16V4Z~N

2

1

C678

0.1U_0402_16V4Z~N

2

1

C685

0.1U_0402_16V4Z~N

2

1

C677

0.1U_0402_16V4Z~N

2

1

2

+1.25VM_CK505 = 80 mA

1

C682
22U_0805_6.3V4Z

2

U6

2

VDDPCI

9

VDD48

16

VDDPLL3

61

VDDREF

39

VDDSRC

55

VDDCPU

12

VDD96_IO

20

VDDPLL3_IO

26

VDDSRC_IO

36

VDDSRC_IO

49

VDDCPU_IO

1

PCI0/CR#_A

3

PCI1/CR#_B

4

PCI2/TME

5

PCI3

6

PCI4/27_Select

7

PCI_F5/ITP_EN

60

X1

59

X2

10

USB_48MHZ/FSLA

57

FSLB/TEST_MODE

62

REF0/FSLC/TEST_SEL

45

VDDSRC_IO

42

GNDSRC

8

GNDPCI

11

GND48

15

GND

19

GND

52

GNDCPU

23

GNDSRC

29

GNDSRC

58

GNDREF

ICS9LPRS365BGLFT_TSSOP64

1

C686

0.1U_0402_16V4Z~N

2

SRC1/SE1/27MHz_NonSS

SRC1#/SE2/27MHz_SS

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

1

C688

0.1U_0402_16V4Z~N

2

NC

SCLK

SDATA

PCI_STOP#

CPU_STOP#

CPU0

CPU0#

CPU1_F

CPU1#_F

SRC8/CPU2_ITP

SRC8#/CPU2_ITP#

SRC10

SRC10#

SRC11/CR#_H

SRC11#/CR#_G

SRC9

SRC9#

SRC7/CR#_F

SRC7#/CR#_E

SRC6

SRC6#

SRC4

SRC4#

SRC3/CR#_C

SRC3#/CR#_D

SRC2/SATA

SRC2#/SATA#

SRC0/DOT96

SRC0#/DOT96#

CK_PWRGD/PD#

2007/12/28 2007/12/28

1

C681
22U_0805_6.3V4Z

2

48

64
63

38
37

R_CPU_BCLK

54

R_CPU_BCLK#

53

R_MCH_BCLK

51

R_MCH_BCLK#

50

R_PCIE_LAN

47

R_PCIE_LAN#

46

R_PCIE_EXPR

34

R_PCIE_EXPR#

35

R_CLKREQ#_H

33

R_CLKREQ#_G

32

R_CLK_PCIE_MCard

30

R_CLK_PCIE_MCard#

31

R_PCIE_LAN_REQ#

44

R_ROBSON_REQ#

43

R_CLK_ROB

41

R_CLK_ROB#

40

R_MCH_3GPLL

27

R_MCH_3GPLL#

28

R_PCIE_ICH

24

R_PCIE_ICH#

25

R_PCIE_SATA

21

R_PCIE_SATA#

22

R_SSCDREFCLK

17

R_SSCDREFCLK#

18

R_MCH_DREFCLK

13

R_MCH_DREFCLK#

14

56

R553 0_0402_5%VGA@
R554 0_0402_5%VGA@

Compal Secret Data

Deciphered Date

1

C689

0.1U_0402_16V4Z~N

2

R493

1 2
1 2

R494
R495

1 2

1 2

R496
R503

1 2

1 2

R504
R513

1 2

1 2

R512
R522

R510
R537

1 2

1 2

R538
R497

1 2

1 2

R498 475_0402_1%

R505

1 2

1 2

R506
R541

1 2

1 2

R542
R539

1 2

1 2

R540
R543

1 2

1 2

R544

R555 0_0402_5%UMA@

1 2

R552 0_0402_5%UMA@

1 2

R546

1 2

1 2

R547

1 2

1 2

1 2

R507 0_0402_5%@

12
12

0_0402_5%
0_0402_5%

0_0402_5%
0_0402_5%

0_0402_5%
0_0402_5%

0_0402_5%
0_0402_5%

1 2

R511 10K_0402_5%
475_0402_1%
475_0402_1%

1 2

R523 10K_0402_5%
0_0402_5%
0_0402_5%

1 2

R484 10K_0402_5%
475_0402_1%

1 2

R485 10K_0402_5%
0_0402_5%

0_0402_5%

0_0402_5%
0_0402_5%

0_0402_5%
0_0402_5%

0_0402_5%
0_0402_5%

0_0402_5%UMA@
0_0402_5%UMA@

CK_PWRGD

2

1

2

CLK_EN#

C683

0.1U_0402_16V4Z~N

C680

0.1U_0402_16V4Z~N

ICH_SM_CLK 13,14,19
ICH_SM_DA 13,14,19

H_STP_PCI# 19
H_STP_CPU# 19

CLK_CPU_BCLK 4
CLK_CPU_BCLK# 4

CLK_MCH_BCLK 7
CLK_MCH_BCLK# 7

CLK_PCIE_LAN 22
CLK_PCIE_LAN# 22

CLK_PCIE_EXPR 26
CLK_PCIE_EXPR# 26

+3VS

EXPR_CARD_REQ# 26
MCARD_REQ# 27

+3VS

CLK_PCIE_MCARD 27
CLK_PCIE_MCARD# 27

+3VS

PCIE_LAN_REQ# 22
ROBSON_REQ# 27

+3VS

CLK_PCIE_ROB 27
CLK_PCIE_ROB# 27

CLK_MCH_3GPLL 7
CLK_MCH_3GPLL# 7

CLK_PCIE_ICH 19
CLK_PCIE_ICH# 19

CLK_PCIE_SATA 18
CLK_PCIE_SATA# 18

MCH_SSCDREFCLK 7
MCH_SSCDREFCLK# 7

CLK_MCH_DREFCLK 7
CLK_MCH_DREFCLK# 7

CLK_PCIE_VGA 34
CLK_PCIE_VGA# 34

CK_PWRGD 19
CLK_EN# 48

1

C676

0.1U_0402_16V4Z~N

2

1

C679

0.1U_0402_16V4Z~N

2

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

Clock Generator

LA-4131P

1

of

16 53Monday, February 18, 2008

0.2

5

+3VS

1 2

R241 8.2K_0402_5%

1 2
1 2
1 2
1 2
1 2
1 2
1 2

1 2
1 2
1 2
1 2
1 2
1 2
1 2

1 2
1 2
1 2
1 2

12

R242 8.2K_0402_5%

D D

C C

R261 8.2K_0402_5%
R235 8.2K_0402_5%
R276 8.2K_0402_5%
R270 8.2K_0402_5%
R258 8.2K_0402_5%
R274 8.2K_0402_5%

+3VS

R262 8.2K_0402_5%
R283 8.2K_0402_5%
R279 8.2K_0402_5%
R254 8.2K_0402_5%
R272 8.2K_0402_5%
R255 8.2K_0402_5%
R251 8.2K_0402_5%
R287 8.2K_0402_5%

R285 8.2K_0402_5%
R231 8.2K_0402_5%
R222 8.2K_0402_5%
R250 8.2K_0402_5%

PCI_DEVSEL#
PCI_STOP#
PCI_TRDY#
PCI_FRAME#
PCI_PLOCK#
PCI_IRDY#
PCI_SERR#
PCI_PERR#

PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#
PCI_PIRQE#
PCI_PIRQF#
PCI_PIRQG#
PCI_PIRQH#

PCI_REQ0#
PCI_REQ1#
PCI_REQ2#
PCI_REQ3#

PCI_AD[0..31]25,28

4

PCI_AD0
PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD6
PCI_AD7
PCI_AD8
PCI_AD9
PCI_AD10
PCI_AD11
PCI_AD12
PCI_AD13
PCI_AD14
PCI_AD15
PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20
PCI_AD21
PCI_AD22
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30
PCI_AD31

PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#

U7B

D20

AD0

E19

AD1

D19

AD2

A20

AD3

D17

AD4

A21

AD5

A19

AD6

C19

AD7

A18

AD8

B16

AD9

A12

AD10

E16

AD11

A14

AD12

G16

AD13

A15

AD14

B6

AD15

C11

AD16

A9

AD17

D11

AD18

B12

AD19

C12

AD20

D10

AD21

C7

AD22

F13

AD23

E11

AD24

E13

AD25

E12

AD26

D8

AD27

A6

AD28

E8

AD29

D6

AD30

A3

AD31

Interrupt I/F

F9

PIRQA#

B5

PIRQB#

C5

PIRQC#

A10

PIRQD#

ICH8M REV 1.0

PCI

REQ0#

GNT0#
REQ1#/GPIO50
GNT1#/GPIO51
REQ2#/GPIO52
GNT2#/GPIO53
REQ3#/GPIO54
GNT3#/GPIO55

C/BE0#

C/BE1#

C/BE2#

C/BE3#

IRDY#

PAR

PCIRST#

DEVSEL#

PERR#

PLOCK#

SERR#

STOP#

TRDY#

FRAME#

PLTRST#

PCICLK

PME#

PIRQE#/GPIO2

PIRQF#/GPIO3
PIRQG#/GPIO4
PIRQH#/GPIO5

3

PCI_REQ0#

A4
D7
E18
C18
B19
F18
A11
C10

C17
E15
F16
E17

C8
D9
G6
D16
A7
B7
F10
C16
C9
A17

AG24
B10
G7

F8
G11
F12
B3

PCI_GNT0#
PCI_REQ1#

PCI_REQ2#
PCI_REQ3#

PCI_GNT3#
PCI_CBE#0

PCI_CBE#1
PCI_CBE#2
PCI_CBE#3

PCI_IRDY#
PCI_PAR
PCI_PCIRST#
PCI_DEVSEL#
PCI_PERR#
PCI_PLOCK#
PCI_SERR#
PCI_STOP#
PCI_TRDY#
PCI_FRAME#

PCI_PLTRST#
CLK_PCI_ICH
EC_PME#

PCI_PIRQE#
PCI_PIRQF#
PCI_PIRQG#
PCI_PIRQH#

PCI_REQ0# 25
PCI_GNT0# 25

PCI_CBE#0 25,28
PCI_CBE#1 25,28
PCI_CBE#2 25,28
PCI_CBE#3 25,28

PCI_IRDY# 25
PCI_PAR 25

PCI_DEVSEL# 25
PCI_PERR#

PCI_SERR#
PCI_STOP# 25
PCI_TRDY# 25,28
PCI_FRAME# 25,28

CLK_PCI_ICH 16
EC_PME# 28

PCI_PIRQG# 25

2

1

PCI_GNT3#

12

R257

@

1K_0402_5%

B B

A16 swap override Strap

PCI_GNT3#

A A

Low= A16 swap override Enble
High= Default

Place closely pin B10

CLK_PCI_ICH

R269

10_0402_5% @

C382

8.2P_0402_50V@

5

*

1 2
1

2

Check if use LPC

Boot BIOS Strap

PCI_GNT0# SPI_CS#1

0

1

1

PCI_GNT0#

12

R275

@

1K_0402_5%

4

R277
0_0402_5%

R212
0_0402_5%

+3V_SB

5

@

2

P

B

1

A

G

NC7SZ08P5X_NL_SC70-5

3

12

+3V_SB

5

@

2

P

B

1

A

G

NC7SZ08P5X_NL_SC70-5

3

12

U8

PCI_RST#

4

Y

U9

PLT_RST#

4

Y

Title

Size Document Number Rev

Custom

Date: Sheet

12

12

Compal Electronics, Inc.

ICH8M(1/4)_PCI / INT

LA-4131P

PCI_RST# 21,25,28

R278
100K_0402_5%

PLT_RST# 7,19,21,22,26,27,28,31,34

R211
100K_0402_5%

1

0.2

of

17 53Monday, February 18, 2008

Boot BIOS Location

1

0

1

SPI

PCI

LPC

*

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2007/12/28 2007/12/28

Compal Secret Data

PCI_PCIRST#

PCI_PLTRST#

Deciphered Date

2

5

4

3

2

1

+RTC_CELL

R204 330K_0402_1%

LAN100_SLP

1 2

R201 1M_0402_5%

SM_INTRUDER#

1 2

R160 330K_0402_1%

ICH_INTVRMEN

1 2

D D

C C

B B

15P_0402_50V8J

+3VS

R260 10K_0402_5%

SATA_ITX_DRX_N021

SATA_ITX_DRX_P021

SATA_ITX_DRX_N121

SATA_ITX_DRX_P121

C351

R200

1 2

10M_0402_5%

1

1

2

IN

2

SATA_LED#

12

SATA_ITX_DRX_N0

SATA_ITX_DRX_P0

ICH_RTCX1
ICH_RTCX2

1

15P_0402_50V8J

4

2

OUT

Y1

32.768KHZ QTFM28-32768K125P10L

NC3NC

C403 3900P_0402_50V7K

C400 3900P_0402_50V7K

Close ICH8

SATA_ITX_DRX_N1 SATA_ITX_DRX_N1_C

C692 3900P_0402_50V7K

C697 3900P_0402_50V7K

C355

1 2

1 2

1 2

1 2

SATA_ITX_DRX_N0_C

SATA_ITX_DRX_P0_C

SATA_IRX_DTX_N1_C

SATA_IRX_DTX_P1_C

SATA_ITX_DRX_P1_CSATA_ITX_DRX_P1

Close ICH8

12

R284

0_0402_5%

@

ACZ_BITCLK23
ACZ_SYNC23

ACZ_RST#23

ADC_ACZ_SDIN023

ACZ_SDOUT23

12

R282

0_0402_5%

@

+RTC_CELL

R173

1 2

20K_0402_5%

C343

1U_0603_10V6K

R189 24.9_0402_1%

+1.5VS

R273 33_0402_5%
R268 33_0402_5%

R244 33_0402_5%

R224 33_0402_5%

SATA_IRX_DTX_N0_C21
SATA_IRX_DTX_P0_C21

SATA_IRX_DTX_N1_C21
SATA_IRX_DTX_P1_C21

CLK_PCIE_SATA#16
CLK_PCIE_SATA16

1

2

1 2

SATA_LED#29

12

JCMOS1

@

NO SHORT PAD

1 2
1 2

1 2

1 2

Within 500 mils

ICH_RTCX1
ICH_RTCX2

ICH_RTCRST#
SM_INTRUDER#
ICH_INTVRMEN

LAN100_SLP

GLAN_COMP

HDA_BITCLK_R
HDA_SYNC_R

HDA_RST_R#
ADC_ACZ_SDIN0

HDA_SDOUT_R

SATA_LED#
SATA_IRX_DTX_N0_C

SATA_IRX_DTX_P0_C
SATA_ITX_DRX_N0_C
SATA_ITX_DRX_P0_C

SATA_IRX_DTX_N1_C
SATA_IRX_DTX_P1_C
SATA_ITX_DRX_N1_C
SATA_ITX_DRX_P1_C

SATA_IRX_DTX_N2_C
SATA_IRX_DTX_P2_C
SATA_ITX_DRX_N2_C
SATA_ITX_DRX_P2_C

CLK_PCIE_SATA#
CLK_PCIE_SATA

R290

1 2

24.9_0402_1%

U7A

AG25

RTCX1

AF24

RTCX2

AF23

RTCRST#

AD22

INTRUDER#

AF25

INTVRMEN

AD21

LAN100_SLP

B24

GLAN_CLK

D22

LAN_RSTSYNC

C21

LAN_RXD0

B21

LAN_RXD1

C22

LAN_RXD2

D21

LAN_TXD0

E20

LAN_TXD1

C20

LAN_TXD2

AH21

GLAN_DOCK#/GPIO13

D25

GLAN_COMPI

C25

GLAN_COMPO

AJ16

HDA_BIT_CLK

AJ15

HDA_SYNC

AE14

HDA_RST#

AJ17

HDA_SDIN0

AH17

HDA_SDIN1

AH15

HDA_SDIN2

AD13

HDA_SDIN3

AE13

HDA_SDOUT

AE10

HDA_DOCK_EN#/GPIO33

AG14

HDA_DOCK_RST#/GPIO34

AF10

SATALED#

AF6

SATA0RXN

AF5

SATA0RXP

AH5

SATA0TXN

AH6

SATA0TXP

AG3

SATA1RXN

AG4

SATA1RXP

AJ4

SATA1TXN

AJ3

SATA1TXP

AF2

SATA2RXN

AF1

SATA2RXP

AE4

SATA2TXN

AE3

SATA2TXP

AB7

SATA_CLKN

AC6

SATA_CLKP

AG1

SATARBIAS#

AG2

SATARBIAS

ICH8M REV 1.0

FWH0/LAD0
FWH1/LAD1
FWH2/LAD2
FWH3/LAD3

FWH4/LFRAME#

LDRQ0#

LDRQ1#/GPIO23

RTCLAN / GLAN

LPCCPU

A20GATE

A20M#

DPRSTP#

DPSLP#

FERR#

CPUPWRGD/GPIO49

IGNNE#

RCIN#

STPCLK#

THRMTRIP#

IHDA

IDE

SATA

DCS1#
DCS3#

DIOR#

DIOW#

DDACK#

IDEIRQ

IORDY

DDREQ

INIT#

INTR

SMI#

DD10
DD11
DD12
DD13
DD14
DD15

NMI

TP8
DD0

DD1
DD2
DD3
DD4
DD5
DD6
DD7
DD8
DD9

DA0
DA1
DA2

E5
F5
G8
F6

C4
G9

E6
AF13

AG26
AF26

AE26
AD24
AG29
AF27
AE24

AC20
AH14

AD23
AG28

AA24
AE27
AA23
V1

U2
V3
T1
V4
T5
AB2
T6
T3
R2
T4
V6
V5
U1
V2
U6

AA4
AA1
AB3

Y6
Y5

W4
W3
Y2
Y3
Y1
W5

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3

LPC_FRAME#
LPC_DRQ0#

LPC_DRQ1#

GATEA20
H_A20M#

H_FERR#
H_PWRGOOD
H_IGNNE#
H_INIT#

H_INTR
KB_RST#

H_NMI
H_SMI#

H_STPCLK#
THRMTRIP_ICH#

IDE_DD0
IDE_DD1
IDE_DD2
IDE_DD3
IDE_DD4
IDE_DD5
IDE_DD6
IDE_DD7
IDE_DD8
IDE_DD9
IDE_DD10
IDE_DD11
IDE_DD12
IDE_DD13
IDE_DD14
IDE_DD15

IDE_DA0
IDE_DA1
IDE_DA2

IDE_DCS1#
IDE_DCS3#

IDE_DIOR#
IDE_DIOW#

IDE_DDACK#

IDE_IRQ

IDE_DIORDY

IDE_DDREQ

LPC_AD[0..3] 27,28

LPC_FRAME# 27,28
LPC_DRQ0#

T39 PAD

GATEA20 28
H_A20M# 4

12

R175 0_0402_5%

H_DPSLP# 5

H_FERR# 4
H_PWRGOOD 5
H_IGNNE# 4
H_INIT# 4

H_INTR 4

KB_RST# 28

H_NMI 4
H_SMI# 4

H_STPCLK# 4
1 2

IDE_DD[0..15] 21

IDE_DA0 21
IDE_DA1 21
IDE_DA2 21

IDE_DCS1# 21
IDE_DCS3# 21

IDE_DIOR# 21
IDE_DIOW# 21

IDE_DDACK# 21
IDE_IRQ 21
IDE_DIORDY 21

IDE_DDREQ 21

H_DPRSTP#H_DPRSTP_R#

R185 24_0402_1%

placed within 2" from ICH8M

XOR CHAIN ENTRANCE STRAP:RSVD

GATEA20

KB_RST#

H_FERR#

H_DPRSTP# 5,7,48

+VCCP

IDE_DIORDY

R292 4.7K_0402_5%

IDE_IRQ

R288 8.2K_0402_5%

10K_0402_5%

10K_0402_5%

within 2" from R1557

12

R172
56_0402_5%

1 2
1 2

+3VS

R227

12

R248

12

+VCCP

R203

12

56_0402_5%

H_THERMTRIP# 4,7

+3VS

XOR Chain Entrance Strap

SATA_IRX_DTX_N2_C

T42PAD

SATA_IRX_DTX_P2_C

T43PAD

SATA_ITX_DRX_N2_CSATA_ITX_DRX_N2

A A

T45PAD

T44PAD

5

1 2

C415 3900P_0402_50V7K

@

SATA_ITX_DRX_P2_CSATA_ITX_DRX_P2

1 2

C414 3900P_0402_50V7K

@

Close ICH8

12

R296

0_0402_5%

12

R295

0_0402_5%

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2007/12/28 2007/12/28

+3VS

R223

@

1K_0402_5%

12
12

R218

@

1K_0402_5%

Compal Secret Data

Deciphered Date

ACZ_SDOUT
ICH_RSVD

ICH_RSVD 19

2

ICH RSVD

HDA SDOUT

0

0

1

1

Title

ICH8M(2/4)_LAN / HD / IDE / LPC

Size Document Number Rev

Custom

LA-4131P

Date: Sheet

Description

0

RSVD

Enter XOR Chain

1

Normal Operation (Default)

0

1

Set PCIE port config bit 1

Compal Electronics, Inc.

1

0.2

of

18 53Monday, February 18, 2008

5

SERIRQ

+3VS

D D

1 2

R256 10K_0402_5%

R259 8.2K_0402_5%

R249 8.2K_0402_5%@

R264 8.2K_0402_5%

R610 10K_0402_5% @

1 2

1 2

1 2

1 2

PCI_CLKRUN#

EC_THERM#

OCP#

SB_SPKR

Low--> Default

R215

10K_0402_5%

+3V_SB

1 2

R225
10K_0402_5%

1 2

High --> No Reboot Mode

ICH_LOW_BAT#

+3V_SB

C C

+3V_SB

B B

R216 8.2K_0402_5%

R234 1K_0402_5%

R230 10K_0402_5%

R236 10K_0402_5%

R213 10K_0402_5%

R214 10K_0402_5%@

10K_1206_8P4R_5%

R233 10K_0402_5%

Modify follow intel check list-1003

R221 100K_0402_5%@

R228 100K_0402_5%

R245 499_0402_1%@

R217 10K_0402_5% @

1 2

1 2

1 2

1 2

1 2

RP28

45
36
27
18

RP29

45
36
27
18

12

1 2

1 2

1 2

12

ICH_PCIE_WAKE#

ICH_RI#

XDP_DBRESET#

CL_RST#1

EC_LID_OUT#

USB_OC#1
USB_OC#2
USB_OC#3
USB_OC#4

USB_OC#5
USB_OC#8
USB_OC#9
USB_OC#0

10K_1206_8P4R_5%

USB_OC#7

LAN_WOL_EN

VRMPWRGD

DPRSLPVR

PLT_RST#

12

VGATE28,48

Reserve

Express Card

Robson

WLAN

GLAN

+3VS

12

A A

ICH_SM_DA13,14,16
ICH_SM_CLK13,14,16

For(DDR/CLKGEN/G-sensor/WWAN)

5

12

2.2K_0402_5%
R483

R2202.2K_0402_5%

+5VS

Q17A
2N7002DW-T/R7_SOT363-6~D

61

3

4

2

Q17B

2N7002DW-T/R7_SOT363-6~D

5

ICH_SMB_DATA
ICH_SMB_CLK

For(WLAN/EXP-Card/LAN)

ICH_SMB_CLK26
ICH_SMB_DATA26

PCIE_RXN226

PCIE_RXP226
PCIE_TXN226
PCIE_TXP226

PCIE_RXN327

PCIE_RXP327
PCIE_TXN327
PCIE_TXP327

PCIE_RXN427

PCIE_RXP427
PCIE_TXN427
PCIE_TXP427

GLAN_RXN22

GLAN_RXP22
GLAN_TXN22
GLAN_TXP22

4

R491

2.2K_0402_5%

XDP_DBRESET#4
PM_BMBUSY#7
EC_LID_OUT#28
H_STP_PCI#16

H_STP_CPU#16
PCI_CLKRUN#25,28

ICH_PCIE_WAKE#26,27
SERIRQ28
EC_THERM#4,28

VGATE

OCP#4

EC_SMI#28

EC_SCI#28

CLKSATAREQ#16

SB_SPKR24

MCH_ICH_SYNC#7

ICH_RSVD18

4

+3V_SB

12

12

R487

2.2K_0402_5%

T41PAD

1 2

R219 0_0402_5%

T28PAD

T35PAD

T36PAD
T34PAD

T33PAD

0.1U_0402_16V7K~N

0.1U_0402_16V7K~N

USB_OC#030
USB_OC#130
USB_OC#230
USB_OC#330
USB_OC#430

ICH_SMB_CLK
ICH_SMB_DATA
CL_RST#1
ME_SMB_CK
ME_SMB_DA

ICH_RI#

XDP_DBRESET#
PM_BMBUSY#
EC_LID_OUT#
H_STP_PCI#

H_STP_CPU#

ICH_PCIE_WAKE#
SERIRQ
EC_THERM#

VRMPWRGD

SST_CTL

OCP#
WWAN_REQ#

EC_SMI#
EC_SCI#

CLKSATAREQ#

SB_SPKR
MCH_ICH_SYNC#
ICH_RSVD

T23PAD
T20PAD

T22PAD
T21PAD
T18PAD
T17PAD

EC_SWI#28

AD19
AG21
AC17
AE19

AF17

AD15
AG12
AG22
AE20

AG18
AH11
AE17

AF12
AC13

AE16
AC19

AH12
AE11
AG10
AH25
AD16
AG13

AD10

C6580.1U_0402_16V7K~N@

12

C6570.1U_0402_16V7K~N@

12

C6560.1U_0402_16V7K~N

12

C6550.1U_0402_16V7K~N

12

C6540.1U_0402_16V7K~N

12

C6530.1U_0402_16V7K~N

12

C651

12

C652

12

C6490.1U_0402_16V7K~N

12

C6500.1U_0402_16V7K~N

12

3

+3VS

R551

8.2K_0402_5%

U7C

AJ26

SMBCLK
SMBDATA
LINKALERT#
SMLINK0
SMLINK1

RI#

F4

SUS_STAT#/LPCPD#
SYS_RESET#

BMBUSY#/GPIO0
SMBALERT#/GPIO11
STP_PCI#/GPIO15

STP_CPU#/GPIO25
CLKRUN#/GPIO32
WAKE#

SERIRQ
THRM#

AJ20

VRMPWRGD

AJ22

TP7

AJ8

TACH1/GPIO1

AJ9

TACH2/GPIO6

AH9

TACH3/GPIO7
GPIO8
GPIO12

AG8

TACH0/GPIO17
GPIO18
GPIO20
SCLOCK/GPIO22
QRT_STATE0/GPIO27
QRT_STATE1/GPIO28
SATACLKREQ#/GPIO35

AF9

SLOAD/GPIO38

AJ11

SDATAOUT0/GPIO39
SDATAOUT1/GPIO48

AD9

SPKR

AJ13

MCH_SYNC#

AJ21

TP3

ICH8M REV 1.0

AJ19
AG16
AG15
AE15
AF15
AG17
AD12

AJ18
AD14
AH18

P27
P26
N29
N28

M27
M26

L29
L28

K27
K26

J29
J28

H27
H26
G29
G28

F27
F26
E29
E28

D27
D26
C29
C28

C23
B23
E22

D23
F21

U7D

PERN1
PERP1
PETN1
PETP1

PERN2
PERP2
PETN2
PETP2

PERN3
PERP3
PETN3
PETP3

PERN4
PERP4
PETN4
PETP4

PERN5
PERP5
PETN5
PETP5

PERN6/GLAN_RXN
PERP6/GLAN_RXP
PETN6/GLAN_TXN
PETP6/GLAN_TXP

SPI_CLK
SPI_CS0#
SPI_CS1#

SPI_MOSI
SPI_MISO

OC0#
OC1#/GPIO40
OC2#/GPIO41
OC3#/GPIO42
OC4#/GPIO43
OC5#/GPIO29
OC6#/GPIO30
OC7#/GPIO31
OC8#
OC9#

ICH8M REV 1.0

PCIE_RXN1
PCIE_RXP1
PCIE_C_TXN1
PCIE_C_TXP1

PCIE_RXN2
PCIE_RXP2
PCIE_C_TXN2
PCIE_C_TXP2

PCIE_RXN3
PCIE_RXP3
PCIE_C_TXN3
PCIE_C_TXP3

PCIE_RXN4
PCIE_RXP4
PCIE_C_TXN4
PCIE_C_TXP4

GLAN_RXN

GLAN_RXP
GLAN_TXN_C
GLAN_TXP_C

PCIE_RXN6

PCIE_RXP6
PCIE_C_TXN6
PCIE_C_TXP6

USB_OC#0
USB_OC#1
USB_OC#2
USB_OC#3
USB_OC#4
USB_OC#5
EC_SWI#
USB_OC#7
USB_OC#8
USB_OC#9

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

SATA0GP/GPIO21
SATA1GP/GPIO19
SATA2GP/GPIO36

SATA

GPIO

SATA3GP/GPIO37

SMB

Clocks

S4_STATE#/GPIO26

SYS

GPIO

DPRSLPVR/GPIO16

Power MGTController Link

GPIO

MEM_LED/GPIO24
ME_EC_ALERT/GPIO10
EC_ME_ALERT/GPIO14

WOL_EN/GPIO9

MISC

DMI0RXN
DMI0RXP
DMI0TXN

DMI0TXP

DMI1RXN
DMI1RXP
DMI1TXN

DMI1TXP

DMI2RXN
DMI2RXP
DMI2TXN

DMI2TXP

DMI3RXN
DMI3RXP
DMI3TXN

DMI3TXP

PCI-Express

DMI_CLKN

DMI_CLKP

DMI_ZCOMP

DMI_IRCOMP

Direct Media Interface

USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4N

SPI

USBP4P
USBP5N
USBP5P
USBP6N

USB

USBP6P
USBP7N
USBP7P
USBP8N
USBP8P
USBP9N
USBP9P

USBRBIAS#

USBRBIAS

2007/12/28 2007/12/28

3

CLK14
CLK48

SUSCLK

SLP_S3#
SLP_S4#
SLP_S5#

PWROK

BATLOW#
PWRBTN#

LAN_RST#

RSMRST#

CK_PWRGD

CLPWROK

SLP_M#

CL_CLK0
CL_CLK1

CL_DATA0
CL_DATA1

CL_VREF0
CL_VREF1

CL_RST#

V27
V26
U29
U28

Y27
Y26
W29
W28

AB26
AB25
AA29
AA28

AD27
AD26
AC29
AC28

T26
T25

Y23
Y24

G3
G2
H5
H4
H2
H1
J3
J2
K5
K4
K2
K1
L3
L2
M5
M4
M2
M1
N3
N2

F2
F3

AJ12
AJ10
AF11
AG11

AG9
G5

D3
AG23

AF21
AD18

AH27
AE23
AJ14
AE21
C2
AH20
AG27
E1
E3
AJ25
F23

AE18
F22

AF19
D24

AH23
AJ23
AJ27

AJ24
AF22
AG19

DMI_RXN0
DMI_RXP0
DMI_TXN0
DMI_TXP0

DMI_RXN1
DMI_RXP1
DMI_TXN1
DMI_TXP1

DMI_RXN2
DMI_RXP2
DMI_TXN2
DMI_TXP2

DMI_RXN3
DMI_RXP3
DMI_TXN3
DMI_TXP3

CLK_PCIE_ICH#
CLK_PCIE_ICH

DMI_IRCOMP
USB20_N0

USB20_P0
USB20_N1
USB20_P1
USB20_N2
USB20_P2
USB20_N3
USB20_P3
USB20_N4
USB20_P4
USB20_N5
USB20_P5
USB20_N6
USB20_P6
USB20_N7
USB20_P7
USB20_N8
USB20_P8
USB20_N9
USB20_P9

USBRBIAS

Compal Secret Data

1 2

CLK_14M_ICH
CLK_48M_ICH

ICH_SUSCLK
SLP_S3#

SLP_S4#
SLP_S5#

T19 PAD

PM_PWROK
DPRSLPVR
ICH_LOW_BAT#
PBTN_OUT#

PLT_RST#
PM_RSMRST#
CK_PWRGD_R CK_PWRGD
M_PWROK
PM_SLP_M#
CL_CLK0

CL_DATA0

CL_VREF0_ICH
CL_VREF1_ICH

CLK_14M_ICH 16
CLK_48M_ICH 16

T40 PAD

SLP_S3# 28
SLP_S4# 28
SLP_S5# 28

R243 0_0402_5%

1 2

PM_PWROK 7,28
DPRSLPVR 7,48

PBTN_OUT# 28
PLT_RST# 7,17,21,22,26,27,28,31,34

1 2

R289 0_0402_5%

M_PWROK 7

T25 PAD

T27 PAD

T50 PAD

12

R2090_0402_5%

DMI_RXN0 7

DMI_RXP0 7
DMI_TXN0 7
DMI_TXP0 7

DMI_RXN1 7

DMI_RXP1 7
DMI_TXN1 7
DMI_TXP1 7

DMI_RXN2 7

DMI_RXP2 7
DMI_TXN2 7
DMI_TXP2 7

DMI_RXN3 7

DMI_RXP3 7
DMI_TXN3 7
DMI_TXP3 7

CLK_PCIE_ICH# 16
CLK_PCIE_ICH 16

R210 24.9_0402_1%

1 2

USB20_N0 31
USB20_P0 31
USB20_N1 31
USB20_P1 31
USB20_N2 30
USB20_P2 30
USB20_N3 30
USB20_P3 30
USB20_N4 30
USB20_P4 30
USB20_N5 31
USB20_P5 31
USB20_N6 30
USB20_P6 30
USB20_N7 26
USB20_P7 26
USB20_N8 30
USB20_P8 30
USB20_N9 30
USB20_P9 30

1 2

R286 22.6_0402_1%

Within 500 mils

Deciphered Date

2

M_PWROK

1 2

CL_CLK0 7

CL_DATA0 7

CL_RST# 7

ACIN 28,41,42

LAN_WOL_EN

Within 500 mils

Finger Printer
Blue Tooth
JUSBP5
JUSBP5
JUSBP1
USB Hub
JUSBP4
Express Card
JUSBP3
JUSBP2

2

R240

10K_0402_5%

1 2

R168 10K_0402_5%

CK_PWRGD 16

RSMRST# -> CLPWROK -> PWROK

R198 3.24K_0402_1%

1 2

12

1

C358

R202

453_0402_1%

2

0.1U_0402_16V4Z~N

+1.5VS

RSMRST circuit

EC_RSMRST#28

@

2.2K_0402_5%

Title

ICH8M(3/4)_PM/USB/GPIO

Size Document Number Rev

Custom

LA-4131P

Date: Sheet

1

Place closely pin AG9Place closely pin G5

12

R294

10_0402_5%@

1

C413

4.7P_0402_50V8C@

2

+3VS

R176 0_0402_5%

1 2

Q12

EC_RSMRST# PM_RSMRST#

BAV99DW-7_SOT363

D13B

@

R174

1 2

@

R171

1 2

2.2K_0402_5%

@

3

E

B

2
1

2

4

5

@

6

3

Compal Electronics, Inc.

1

CLK_14M_ICHCLK_48M_ICH

12

R265

10_0402_5%@

1

C380

4.7P_0402_50V8C@

2

C

1

MMBT3906_SOT23

D13A
BAV99DW-7_SOT363

of

19 53Monday, February 18, 2008

0.2

5

D D

+5VS +3VS

12

R263

100_0402_5%

C C

10_0402_5%

+1.5VS

B B

A A

+3V_SB+5VALW

12

R291

L21

1 2

CHB1608U301_0603

+1.5VS

C369

0.1U_0402_16V4Z~N

L18

1 2

+1.5VS

CHB1608U301_0603

220U_D2_4VY_R15M

21

D14
CH751H-40PT_SOD323-2

20 mils

ICH_V5REF_RUN

1

C383

0.1U_0402_16V4Z~N

2

21

D15
CH751H-40PT_SOD323-2

ICH_V5REF_SUS

20 mils

1

C409

0.1U_0402_16V4Z~N

2

1

C393

2

1U_0603_10V4Z

C384

0.1U_0402_16V4Z~N

+3VS

0316 change design

1

+1.5VS

2

5

C341

1

C402

2

1

2

1 2

L20

C361

+RTC_CELL

1

C354

2

0.1U_0402_16V4Z~N

40 mils

1

1

+

C648

2

2

10U_0805_4VAM~D

+1.5VS

10U_0805_4VAM~D

+1.5VS

+1.5VS

0.1U_0402_16V4Z~N

CHB1608U301_0603

1

2

2.2U_0603_106K

10U_0805_4VAM~D

20 mils

1

C350

2

0.1U_0402_16V4Z~N

ICH_V5REF_RUN

ICH_V5REF_SUS

10U_0805_4VAM~D

1

C647

2

2.2U_0603_6.3V4Z~N

1U_0603_10V4Z

1U_0603_10V4Z

1

C412

2

T31
T30

1 2

1

+1.5VS

CHB1608U301_0603

C360

2

1

C661

2

1

C416

2

1

C388

2

+1.5VS

VCC_LAN1_05_INT_ICH_1
VCC_LAN1_05_INT_ICH_2

4.7U_0805_10V4Z~N

L32

@

1

C671

@
2

+3VS

AD25

AA25
AA26
AA27
AB27
AB28
AB29

W25

AG7

AC10

W23

A16

T7

G4

D28
D29
E25
E26
E27
F24
F25
G24
H23
H24

J23

J24
K24
K25
L23
L24
L25
M24
M25
N23
N24
N25
P24
P25
R24
R25
R26
R27
T23
T24
T27
T28
T29
U24
U25
V23
V24
V25

Y25
AJ6
AE7

AF7
AH7

AJ7
AC1

AC2
AC3
AC4
AC5

AC9
AA5

AA6
G12

G17

H7

AC7
AD7

D1

F1
L6

L7
M6
M7

F17
G18

F19
G20

A24
A26

A27
B26
B27
B28

B25

4

U7F

VCCRTC
V5REF[1]

V5REF[2]
V5REF_SUS
VCC1_5_B[01]

VCC1_5_B[02]
VCC1_5_B[03]
VCC1_5_B[04]
VCC1_5_B[05]
VCC1_5_B[06]
VCC1_5_B[07]
VCC1_5_B[08]
VCC1_5_B[09]
VCC1_5_B[10]
VCC1_5_B[11]
VCC1_5_B[12]
VCC1_5_B[13]
VCC1_5_B[14]
VCC1_5_B[15]
VCC1_5_B[16]
VCC1_5_B[17]
VCC1_5_B[18]
VCC1_5_B[19]
VCC1_5_B[20]
VCC1_5_B[21]
VCC1_5_B[22]
VCC1_5_B[23]
VCC1_5_B[24]
VCC1_5_B[25]
VCC1_5_B[26]
VCC1_5_B[27]
VCC1_5_B[28]
VCC1_5_B[29]
VCC1_5_B[30]
VCC1_5_B[31]
VCC1_5_B[32]
VCC1_5_B[33]
VCC1_5_B[34]
VCC1_5_B[35]
VCC1_5_B[36]
VCC1_5_B[37]
VCC1_5_B[38]
VCC1_5_B[39]
VCC1_5_B[40]
VCC1_5_B[41]
VCC1_5_B[42]
VCC1_5_B[43]
VCC1_5_B[44]
VCC1_5_B[45]
VCC1_5_B[46]

VCCSATAPLL
VCC1_5_A[01]

VCC1_5_A[02]
VCC1_5_A[03]
VCC1_5_A[04]
VCC1_5_A[05]

VCC1_5_A[06]
VCC1_5_A[07]
VCC1_5_A[08]
VCC1_5_A[09]
VCC1_5_A[10]

VCC1_5_A[11]
VCC1_5_A[12]

VCC1_5_A[13]
VCC1_5_A[14]

VCC1_5_A[15]
VCC1_5_A[16]
VCC1_5_A[17]

VCC1_5_A[18]
VCC1_5_A[19]

VCCUSBPLL
VCC1_5_A[20]

VCC1_5_A[21]
VCC1_5_A[22]
VCC1_5_A[23]
VCC1_5_A[24]

VCC1_5_A[25]
VCCLAN1_05[1]

VCCLAN1_05[2]
VCCLAN3_3[1]

VCCLAN3_3[2]
VCCGLANPLL
VCCGLAN1_5[1]

VCCGLAN1_5[2]
VCCGLAN1_5[3]
VCCGLAN1_5[4]
VCCGLAN1_5[5]

VCCGLAN3_3

ICH8M REV 1.0

4

CORE

VCCA3GP ATXARX

VCCP_COREVCCPSUSVCCPUSB

IDE

PCI

VCCSUS1_05[1]
VCCSUS1_05[2]

VCCSUS1_5[1]

VCCSUS1_5[2]
VCCSUS3_3[01]
VCCSUS3_3[02]

VCCSUS3_3[03]
VCCSUS3_3[04]
VCCSUS3_3[05]

USB CORE

VCCSUS3_3[06]
VCCSUS3_3[07]

VCCSUS3_3[08]
VCCSUS3_3[09]
VCCSUS3_3[10]
VCCSUS3_3[11]
VCCSUS3_3[12]
VCCSUS3_3[13]
VCCSUS3_3[14]
VCCSUS3_3[15]
VCCSUS3_3[16]
VCCSUS3_3[17]
VCCSUS3_3[18]
VCCSUS3_3[19]

GLAN POWER

VCC1_05[01]
VCC1_05[02]
VCC1_05[03]
VCC1_05[04]
VCC1_05[05]
VCC1_05[06]
VCC1_05[07]
VCC1_05[08]
VCC1_05[09]
VCC1_05[10]
VCC1_05[11]
VCC1_05[12]
VCC1_05[13]
VCC1_05[14]
VCC1_05[15]
VCC1_05[16]
VCC1_05[17]
VCC1_05[18]
VCC1_05[19]
VCC1_05[20]
VCC1_05[21]
VCC1_05[22]
VCC1_05[23]
VCC1_05[24]
VCC1_05[25]
VCC1_05[26]
VCC1_05[27]
VCC1_05[28]

VCCDMIPLL
VCC_DMI[1]

VCC_DMI[2]

V_CPU_IO[1]
V_CPU_IO[2]

VCC3_3[01]
VCC3_3[02]
VCC3_3[03]

VCC3_3[04]
VCC3_3[05]
VCC3_3[06]

VCC3_3[07]
VCC3_3[08]
VCC3_3[09]
VCC3_3[10]
VCC3_3[11]
VCC3_3[12]
VCC3_3[13]

VCC3_3[14]
VCC3_3[15]
VCC3_3[16]
VCC3_3[17]
VCC3_3[18]
VCC3_3[19]
VCC3_3[20]
VCC3_3[21]
VCC3_3[22]
VCC3_3[23]
VCC3_3[24]

VCCHDA

VCCSUSHDA

VCCCL1_05

VCCCL1_5

VCCCL3_3[1]
VCCCL3_3[2]

3

A13
B13
C13
C14
D14
E14
F14
G14
L11
L12
L14
L16
L17
L18
M11
M18
P11
P18
T11
T18
U11
U18
V11
V12
V14
V16
V17
V18

R29
AE28

AE29
AC23

AC24
AF29
AD2
AC8

AD8
AE8
AF8

AA3
U7
V7
W1
W6
W7
Y7

A8
B15
B18
B4
B9
C15
D13
D5
E10
E7
F11

AC12
AD11

TP_VCCSUS1.05_INT_ICH1

J6

TP_VCCSUS1.05_INT_ICH2

AF20

VCCSUS1_5_ICH_1

AC16

VCCSUS1_5_ICH_2

J7
C3
AC18

AC21
AC22
AG20
AH28

P6
P7
C1
N7
P1
P2
P3
P4
P5
R1
R3
R5
R6

VCCCL1_05_ICH

G22
A22
F20

G21

0.1U_0402_16V7K~N

1

C228

C242 0.1U_0402_16V4Z~N

2

0.01U_0402_16V7K

C348

0.1U_0402_16V4Z~N

+3VS

+3VS

1

C390

0.1U_0402_16V4Z~N

2

0.1U_0402_16V4Z~N

+3VS

1

C346

2

C716

1

0.47U_0603_10V7K

2

T26

1

C366

@

1U_0603_10V4Z

2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

+VCCP

1

2

L19

1 2

CHB1608U301_0603

1

1

C345 10U_0805_4VAM~D

2

2

+1.25VS

22U_0805_6.3V4Z

C660

1

2

0.1U_0402_16V4Z~N

+3VS

(SATA)

1

C405

2

0.1U_0402_16V4Z~N

1

1

C391

2

2

0.1U_0402_16V4Z~N

0.1U_0402_16V4Z~N

+3V_SB

1

T38

C714

T29

2

0.1U_0402_16V4Z~N

T32
T37

1

C359

2

0.1U_0402_16V4Z~N

+3V_SB

+3V_SB

2007/12/28 2007/12/28

C364

1

2

+3VS

C387

1

2

+1.5VS

+3VS

(DMI)

C408

0.1U_0402_16V4Z~N

+3VS

1

C362

2

Compal Secret Data

4.7U_0603_6.3V6M
C248

1

2

Deciphered Date

0.1U_0402_16V4Z~N
C243

1

2

0.1U_0402_16V4Z~N

2

U7E

A23

VSS[001]

A5

VSS[002]

AA2

VSS[003]

AA7

VSS[004]

A25

VSS[005]

AB1

VSS[006]

AB24

VSS[007]

AC11

VSS[008]

AC14

VSS[009]

AC25

VSS[010]

AC26

VSS[011]

AC27

VSS[012]

AD17

VSS[013]

AD20

VSS[014]

AD28

VSS[015]

AD29

VSS[016]

AD3

VSS[017]

AD4

VSS[018]

AD6

VSS[019]

AE1

VSS[020]

AE12

VSS[021]

AE2

VSS[022]

AE22

VSS[023]

AD1

VSS[024]

AE25

VSS[025]

AE5

VSS[026]

AE6

VSS[027]

AE9

VSS[028]

AF14

VSS[029]

AF16

VSS[030]

AF18

VSS[031]

AF3

VSS[032]

AF4

VSS[033]

AG5

VSS[034]

AG6

VSS[035]

+VCCP

C244

1

2

2

AH10

VSS[036]

AH13

VSS[037]

AH16

VSS[038]

AH19

VSS[039]

AH2

VSS[040]

AF28

VSS[041]

AH22

VSS[042]

AH24

VSS[043]

AH26

VSS[044]

AH3

VSS[045]

AH4

VSS[046]

AH8

VSS[047]

AJ5

VSS[048]

B11

VSS[049]

B14

VSS[050]

B17

VSS[051]

B2

VSS[052]

B20

VSS[053]

B22

VSS[054]

B8

VSS[055]

C24

VSS[056]

C26

VSS[057]

C27

VSS[058]

C6

VSS[059]

D12

VSS[060]

D15

VSS[061]

D18

VSS[062]

D2

VSS[063]

D4

VSS[064]

E21

VSS[065]

E24

VSS[066]

E4

VSS[067]

E9

VSS[068]

F15

VSS[069]

E23

VSS[070]

F28

VSS[071]

F29

VSS[072]

F7

VSS[073]

G1

VSS[074]

E2

VSS[075]

G10

VSS[076]

G13

VSS[077]

G19

VSS[078]

G23

VSS[079]

G25

VSS[080]

G26

VSS[081]

G27

VSS[082]

H25

VSS[083]

H28

VSS[084]

H29

VSS[085]

H3

VSS[086]

H6

VSS[087]

J1

VSS[088]

J25

VSS[089]

J26

VSS[090]

J27

VSS[091]

J4

VSS[092]

J5

VSS[093]

K23

VSS[094]

K28

VSS[095]

K29

VSS[096]

K3

VSS[097]

K6

VSS[098]

ICH8M REV 1.0

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

ICH8M(4/4)_Power / GND

LA-4131P

1

VSS[099]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
VSS[159]
VSS[160]
VSS[161]
VSS[162]
VSS[163]
VSS[164]
VSS[165]
VSS[166]
VSS[167]
VSS[168]
VSS[169]
VSS[170]
VSS[171]
VSS[172]
VSS[173]
VSS[174]
VSS[175]
VSS[176]
VSS[177]
VSS[178]
VSS[179]
VSS[180]
VSS[181]
VSS[182]
VSS[183]
VSS[184]

VSS_NCTF[01]
VSS_NCTF[02]
VSS_NCTF[03]
VSS_NCTF[04]
VSS_NCTF[05]
VSS_NCTF[06]
VSS_NCTF[07]
VSS_NCTF[08]
VSS_NCTF[09]
VSS_NCTF[10]
VSS_NCTF[11]
VSS_NCTF[12]

1

K7
L1
L13
L15
L26
L27
L4
L5
M12
M13
M14
M15
M16
M17
M23
M28
M29
M3
N1
N11
N12
N13
N14
N15
N16
N17
N18
N26
N27
N4
N5
N6
P12
P13
P14
P15
P16
P17
P23
P28
P29
R11
R12
R13
R14
R15
R16
R17
R18
R28
R4
T12
T13
T14
T15
T16
T17
T2
U12
U13
U14
U15
U16
U17
U23
U26
U27
U3
U5
V13
V15
V28
V29
W2
W26
W27
Y28
Y29
Y4
AB4
AB23
AB5
AB6
AD5
U4
W24

A1
A2
A28
A29
AH1
AH29
AJ1
AJ2
AJ28
AJ29
B1
B29

0.2

of

20 53Monday, February 18, 2008

5

4

3

2

1

ODD Conn

ODD_ACT_LED# 29

12

PLT_RST#

12

IDE_DD[0..15] 18

PCI_RST# 17,25,28

PLT_RST# 7,17,19,22,26,27,28,31,34

+5VS

10U_0805_10V4Z

1

C407

2

1U_0603_10V4Z

Close to ODD Conn

1

C406

2

0.1U_0402_16V4Z

1

C411

2

1

C410

2

1000P_0402_50V7K~N

+5VS

If CDROM is Slave

then SD_CSEL= Floating

D D

else SD_CSEL= Low

IDE_DCS3#18
IDE_DA218

IDE_DDACK#18
IDE_DIOR#18
IDE_DDREQ18

R293

10K_0402_5%

R557470_0402_5%

47P_0402_50V8J

@

1 2

SD_CSEL

12

PDIAG#

IDE_DD15
IDE_DD14
IDE_DD13
IDE_DD12
IDE_DD11
IDE_DD10
IDE_DD9
IDE_DD8

1

C730

2

80mils

+5VS +5VS

JODD1

1
3
5
7
9

11
13
15
17
19
21
23
25
27
29
31
33
35
37
39

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

GND41GND

87242-4001-09 40P

CONN@

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42

ODD_ACT_LED#

IDE_DD0
IDE_DD1
IDE_DD2
IDE_DD3
IDE_DD4
IDE_DD5
IDE_DD6
IDE_DD7
ODD_RST# PCI_RST#

+5VS

12

R560
100K_0402_5%

IDE_DCS1# 18
IDE_DA0 18
IDE_DA1 18
IDE_IRQ 18
IDE_DIORDY 18
IDE_DIOW# 18

R614

@

0_0402_5%

R611

33_0402_5%

SATA HDD1 Conn

JSATA1

24

C C

SATA_ITX_DRX_P018
SATA_ITX_DRX_N018

SATA_IRX_DTX_N0_C18
SATA_IRX_DTX_P0_C18

W=80mils

SATA_ITX_DRX_P0
SATA_ITX_DRX_N0

C758 3900P_0402_50V7K

12
12

C756 3900P_0402_50V7K

+3VS

+5VS

Ground4

23

Ground3

22

Ground2

21

Ground1

20

20

19

19

18

18

17

17

16

16

15

15

14

14

13

13

12

12

11

11

10

10

9

9

8

8

7

7

6

6

5

5

4

4

3

3

2

2

1

1

HONDA_LVC-D20SFYG3~D

CONN@

@

150U_Y_6.3VM

C738

+5VS

1

+

2

10U_0805_10V4Z

1

C736

2

Close to JSATA1

1

C742

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

C745

2

1

C749

2

1000P_0402_50V7K~N

B B

SATA HDD2 Conn

JSATA2

24

Ground4

23

Ground3

22

Ground2

21

Ground1

20

SATA_ITX_DRX_P118
SATA_ITX_DRX_N118

SATA_IRX_DTX_N1_C18
SATA_IRX_DTX_P1_C18

W=80mils

A A

5

SATA_ITX_DRX_P1
SATA_ITX_DRX_N1

C713 3900P_0402_50V7K

12
12

C711 3900P_0402_50V7K

+3VS

+5VS

4

20

19

19

18

18

17

17

16

16

15

15

14

14

13

13

12

12

11

11

10

10

9

9

8

8

7

7

6

6

5

5

4

4

3

3

2

2

1

1

HONDA_LVC-D20SFYG3~D

CONN@

150U_Y_6.3VM

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2007/12/28 2007/12/28

+5VS

1

+

C694

@

2

Compal Secret Data

Deciphered Date

10U_0805_10V4Z

1

C691

2

Close to JSATA2

1

C702

2

0.1U_0402_16V4Z

2

0.1U_0402_16V4Z

1

C700

2

1

C693

2

1000P_0402_50V7K~N

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

HDD / ODD

LA-4131P

1

21 53Monday, February 18, 2008

0.2

5

Q30

FBMA-L11-322513-201LMA40T_1210

D

6

S

2
1

G

PCIE_LAN_REQ#16

CLK_PCIE_LAN16

CLK_PCIE_LAN#16

R362

1 2

1K_0402_5%

Y2

1 2

T46

1

TCT1

2

TD1+

3

TD1-

4

TCT2

5

TD2+
TD2-6MX2-

7

TCT3

8

TD3+

9

TD3-

10

TCT4

11

TD4+

12

TD4-

BOTH_GST5009-LF

45

AO6402A 1N TSOP-6

3

R364

1.5M_0402_5%

@

1 2

GLAN_RXP19

GLAN_RXN19
GLAN_TXP19
GLAN_TXN19

PLT_RST#7,17,19,21,26,27,28,31,34

1 2

MCT1
MX1+

MX1-

MCT2
MX2+

MCT3
MX3+

MX3-

MCT4
MX4+

MX4-

1U_0603_10V6K

2

+LAN_VDD

C19

0.1U_0402_10V7K~N

B+_BIAS

G

1

2

D D

EN_WOL#28

C C

W=60mils

2

R359
470K_0402_5%

1 2

EN_WOL

13

D

Q31
SSM3K7002FU_SC70-3

S

L2

1 2

4.7UH_1008HC-472EJFS-A_5%_1008

1

C16

2

+3VS

22U_1206_6.3V6M

1

C473

These components close to U30: Pin 1

( Should be place within 200 mils )

B B

1

C459

@

0.1U_0402_10V6K

2

49.9_0402_1%

1 2

1 2

12

12

49.9_0402_1%

2

C454

0.1U_0402_10V6K

1

@

R351

@

49.9_0402_1%

R332

@

49.9_0402_1%

5

R354

@

C12 0.01U_0402_16V7K

1 2

C10 0.01U_0402_16V7K

1 2

C11 0.01U_0402_16V7K

1 2

C14 0.01U_0402_16V7K

1 2

A A

R333

@

@

R346

@

49.9_0402_1%

R330

@

49.9_0402_1%

C458

1 2

12

1

0.1U_0402_10V6K

2

2

1

2

25MHZ_20P_1BX25000CK1A

C470

1

27P_0402_50V8J

R344

@

49.9_0402_1%

1 2

V_DAC
LAN_MDIN3
LAN_MDIP3

V_DAC
LAN_MDIN2
LAN_MDIP2

V_DAC
LAN_MDIN1
LAN_MDIP1

V_DAC

LAN_MDIN0
LAN_MDIP0

12

R329

@

49.9_0402_1%

C449

0.1U_0402_10V6K

@

These components close to T47.

for EMI

L26

1 2

PCIE_PME#28

R363
15K_0402_5%

2

C468

1

27P_0402_50V8J

24

RJ45_TX3-

23

RJ45_TX3+

22
21

RJ45_TX2-

20

RJ45_TX2+

19
18

RJ45_RX1-

17

RJ45_RX1+

16
15

RJ45_TX0-

14

RJ45_TX0+

13

4

1

1

C29

C482

@

2

2

22U_1206_6.3V6M

22U_1206_6.3V6M

GLAN_RXP_C

12

C476 0.1U_0402_16V7K~N

GLAN_RXN_C

12

C474 0.1U_0402_16V7K~N

GLAN_TXP
GLAN_TXN

W=60mils

+LAN_VDD

+LAN_IO

1 2

R355 2.49K_0402_1%

LAN_XTAL1
LAN_XTAL2

RP1

75_1206_8P4R_5%

4

W=60milsW=60mils

ISOLATEB

45
36
27
18

+LAN_IO+3VALW

1.5A

1

C33

2

0.1U_0402_10V7K~N

2

C8
1000P_1206_2KV7K

1

3

+LAN_VDD

1

C31

2

0.1U_0402_10V7K~N

1

C26

2

0.1U_0402_10V7K~N

1

C35

2

0.1U_0402_10V7K~N

1

C17

2

0.1U_0402_10V7K~N

These caps close to U30: Pin 16, 37, 46, 53

R361 3.6K_0402_5%

U30

29

HSOP

30

HSON

23

HSIP

24

HSIN

33

CLKREQB

26

REFCLK_P

27

REFCLK_N

20

PERSTB

1

SROUT12

5

FB12

62

ENSR

64

RSET

19

LANWAKEB

36

ISOLATEB

60

CKTAL1

61

CKTAL2

65

EXPOSE_PAD

25

EGND

31

EGND

15

NC

17

NC

18

NC

34

NC

35

NC

39

NC

40

NC

41

NC

42

NC

RTL8111C-GR_QFN64_9X9

R331 0_0402_5%

R1 0_0402_5%

R4 0_0402_5% @

R328 0_0402_5%@

EEDI/AUX

DVDD12
DVDD12
DVDD12
DVDD12
DVDD12
DVDD12

EVDD12
EVDD12

AVDD33
AVDD33

AVDD12
AVDD12
AVDD12
AVDD12

1 2

1 2

1 2

1 2

MDIP0
MDIN0
MDIP1
MDIN1
MDIP2
MDIN2
MDIP3
MDIN3

VDD33
VDD33
VDD33
VDD33

VDDSR

OGPIO

EEDO

EESK
EECS

LED3
LED2
LED1
LED0

IGPIO

45
47
48
44

54
55
56
57

3
4
6
7
9
10
12
13

21
32
38
43
49
52

22
28

16
37
46
53

63
2

59
8

11
14
58

50
51

LAN_EEDO
LAN_EEDI
LAN_EECLK
LAN_EECS

LAN_LED3
LAN_LED2
LAN_LED1
LAN_LED0

LAN_MDIP0
LAN_MDIN0
LAN_MDIP1
LAN_MDIN1
LAN_MDIP2
LAN_MDIN2
LAN_MDIP3
LAN_MDIN3

LAN_AVDD33

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

1 2

U43

@

4

DO

GND

3

DI

NC

2

SK

NC

1

CS

VCC

AT93C46-10SU-2.7 SO 8P

LAN_DVDD12

+LAN_IO

C27 0.1U_0402_16V7K~N
C30 0.1U_0402_16V7K~N

These caps close to U30: Pin 22, 28

+LAN_IO

LAN_AVDD12

These caps close to U30: Pin 2, 59

LAN_LED2

CH751H-40PT_SOD323-2

LAN_LED3

CH751H-40PT_SOD323-2

LAN_LED1

CH751H-40PT_SOD323-2

LAN_LED3

CH751H-40PT_SOD323-2

2007/12/28 2007/12/28

Compal Secret Data

+LAN_IO

5

R360

@

6

1 2

0_0402_5%

7
8

FBML10160808121LMT_0603

1 2
1 2

C28 0.1U_0402_16V7K~N
C18 0.1U_0402_16V7K~N

L1

12

FBML10160808121LMT_0603

1 2
1 2

D4

LED2_LED3

21

D3

21

D1

LED1_LED3

21

D2

21

Deciphered Date

L3

12

2

1 2

R19

0_0603_5%

1

C483

0.1U_0402_16V7K~N

2

W=30milsW=30mils

+LAN_VDD

+LAN_IO

2

@

LAN_DVDD12

1

C4790.1U_0402_10V7K~N

2

1

1

C4770.1U_0402_10V7K~N

C4810.1U_0402_10V7K~N

2

2

1

1

C320.1U_0402_10V7K~N

2

1

C340.1U_0402_10V7K~N

C4710.1U_0402_10V7K~N

2

2

These caps close to U30: Pin 21, 32, 38, 43, 49, 52

1

C36

2

+LAN_IO

22U_1206_6.3V6M

These caps close to U30: Pin 63

( Should be place within 200 mils )

+LAN_VDD

R18

1 2

0_0603_5%

These caps close to U30: Pin 8, 11, 14, 58

LAN_LED0

LED2_LED3
LED1_LED3

LAN_ACTIVITY#

R5

1 2

220_0402_5%

+LAN_IO

RJ45_TX3­RJ45_TX3+
RJ45_RX1­RJ45_TX2­RJ45_TX2+
RJ45_RX1+
RJ45_TX0­RJ45_TX0+
LINK_10_1000#

R10

1 2

220_0402_5%

LINK_100_1000#

R9

1 2

220_0402_5%

+LAN_IO

Title

Realtek RTL8111C-GR

Size Document Number Rev

Custom

LA-4131P

Date: Sheet

13
12

8
7
6
5
4
3
2
1

11

9

10

Compal Electronics, Inc.

1

1

C250.1U_0402_10V7K~N

2

1

2

LAN_AVDD12

1

C210.1U_0402_10V7K~N

2

JLAN1

Yellow LED­Yellow LED+
PR4­PR4+
PR2­PR3­PR3+
PR2+
PR1­PR1+
Green LED­Orange LED­Green-Orange LED+

C-1775553

CONN@

1

C4780.1U_0402_10V7K~N

C4720.1U_0402_10V7K~N

1

2

C464

1

2

1

1

C4750.1U_0402_10V7K~N

C4800.1U_0402_10V7K~N

2

2

+LAN_IO

0.1U_0402_10V7K~N

1

1

C220.1U_0402_10V7K~N

C200.1U_0402_10V7K~N

2

2

15

GND

14

GND

0.2

of

22 53Monday, February 18, 2008

5

4

3

2

1

Regulator for Codec

HD Audio Codec

+AVDD_AC97

12

40mil

1

C764

2

40mil

U15

14
15
16
17
23
24
18
20
19
21
22
12

11
10

5
2

3
13
34

47
48

4

7

38

AVDD125AVDD2
NC
NC
MIC2_L
MIC2_R
LINE1_L
LINE1_R
CD_L
CD_R
CD_GND
MIC1_L
MIC1_R
PCBEEP

RESET#
SYNC
SDATA_OUT
GPIO0

GPIO3
SENSE A
SENSE B

EAPD
SPDIFO
DVSS1

DVSS2

D D

L41

+VDDA

C C

SPK_SEL HIGH: HARMAN
LOW: NO-BRAND

1 2

FBM-L11-160808-800LMT_0603

10U_1206_16V4Z

MIC124
MIC224

MONO_IN24

DMIC_DATA31

for EMI

12

R645 39.2K _0402_1%

MIC_JD24

B B

1 2

R648 20K_0402_1%

EAPD24

0.1U_0402_16V4Z

1

C768

C741 220P_0402_50V7K

1 2

SENSE_AHP_JD

EAPD

1

C769

2

2

0.1U_0402_16V4Z

C_MIC1

1 2

C761 2.2U_0603_10V6K
C763 2.2U_0603_10V6K

R639 0_0402_5%

R650
0_0402_5%

1 2

ACZ_RST#18
ACZ_SYNC18
ACZ_SDOUT18

1 2

C_MIC2
MONO_IN

DGND

20mil

1

LINE_OUT_L

LINE_OUT_R

HP_OUT_L

HP_OUT_R

DMIC_CLK

BIT_CLK

SDATA_IN

MONO_OUT

LINE1_VREFO

GPIO1
MIC1_VREFO_L
MIC1_VREFO_R

MIC2_VREFO

JDREF

AVSS1

ALC268-GR_LQFP48

AVSS2

DVDD

VREF

9

NC

NC
NC

NC

DVDD_IO

35
36
39
41
45
46
43
44

6

8
37
29
31
28
32
30
27
40
33
26

42

0.1U_0402_16V4Z

1

1

C748

2

2

0.1U_0402_16V4Z

C766 1000P_0402_50V7K~N

LINEL
LINER
HP_LOUT
HP_ROUT

C765 1000P_0402_50V7K~N
R666 22K_0603_1%
R667 22K_0603_1%
R319 0_0603_5%
R312 0_0603_5%
C762 1000P_0402_50V7K~N @
C442 1000P_0402_50V7K~N@

R653 0_0402_5%

for EMI

1 2

R638 0_0402_5%

R637 0_0402_5%

+MIC1_VREFO_L
+MIC1_VREFO_R

AC97_VREF

12

AGND

C746

1 2
1 2
1 2
1 2

1 2

1 2

R658
20K_0402_1%

For EMI

0_0603_5%

1 2

R635

1

C744
10U_1206_16V4Z

2

C757 220P_0402_50V7K

@

10_0402_5%

12

1 2

1 2

R630

10mil
10mil

10mil

1

C770
10U_0805_10V4Z

2

C740

+3VS

AMP_LEFT 24
AMP_RIGHT 24
HP_LEFT 24
HP_RIGHT 24

DMIC_CLK 31

ACZ_BITCLK 18

@

10P_0402_50V8J

ADC_ACZ_SDIN0 18

C441

100K_0402_5%

PLUG_IN24

+5VS

C436

4.7U_0805_10V4Z

0.1U_0402_16V7K~N

R620

1 2

1 2

10K_0603_1%

Adjustable Output

R321

PLUG_IN#24

U53

1

EN

2

GND

3

VIN

RT9198-4GPBG SOT-23 5P 4.75V

+3VS

2

G

5

NC

4

VOUT

4.7U_0805_10V4Z~N

R613

100K_0402_5%

1 2

PLUG_IN#

2

G

13

D

Q39
SSM3K7002FU_SC70-3

S

+VDDA

1

C443

2

13

D

Q38
SSM3K7002FU_SC70-3

S

HP_JD

1

C444

0.1U_0402_16V7K~N

2

Sense Pin Impedance Codec Signals

39.2K

SENSE A

20K
10K

A A

5.1K

39.2K

SENSE B

20K
10K

5.1K

5

PORT-A (PIN 39, 41)
PORT-B (PIN 21, 22)
PORT-C (PIN 23, 24)
PORT-D (PIN 35, 36)
PORT-E (PIN 14, 15)
PORT-F (PIN 16, 17)
PORT-G (PIN 43, 44)
PORT-H (PIN 45, 46)

Moat Bridge

1 2

R668 0_0603_1%

1 2

R664 0_0603_1%

1 2

R317 0_0603_1%

1 2

R305 0_0603_1%

DGND AGND

4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2007/12/28 2007/12/28

3

Compal Secret Data

Deciphered Date

2

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

Audio Codec_ALC268

LA-4131P

1

of

23 53Monday, February 18, 2008

0.2

A

W=40Mil

1

1

2

R619
1K_0402_5%

1 2

EAPD23

R599

1 2

47K_0402_5%

R612

1 2

47K_0402_5%

C754
10U_0805_10V4Z

2

7

RIN+

17

RIN-

9

LIN+

5

LIN-

19

SHUTDOWN

D30 CH751H-40_SC76@

2 1

GND

21

15

16

VDD

PVDD1

GND41GND311GND213GND1

20

C715

1 2

1U_0603_10V4Z

C725

1 2

1U_0603_10V4Z

C755

0.1U_0402_16V4Z

4 4

AMP_RIGHT23

AMP_LEFT23

R634 0_0402_5%

3 3

EC_MUTE28

Change to 100p from 0.01u for EMI

-1012

C751

0.47U_0603_10V7K

C771

0.47U_0603_10V7K

C747

0.47U_0603_10V7K

C767

0.47U_0603_10V7K

@

12

+3VS

12

13

D

2

G

S

1

C737

2

1 2

AMP_R

1 2

1 2

AMP_L

1 2

R618
100K_0402_5%

Q40
SSM3K7002FU_SC70-3

0_0402_5%

Buzzer need to support ICH/PCM_SPK/Battery_low and WL_on/off

2 2

EC Beep

1 1

ICH Beep

A

BEEP#28

SB_SPKR19

B

R646

12

+5VS

0_0402_5%

6

U18

PVDD2

2

GAIN0

3

GAIN1

18

ROUT+

14

ROUT-

4

LOUT+

8

LOUT-

12

NC

10

BYPASS

P3017THF TSSOP 20P

R624

@

1 2

2.7K_0402_5%

R601

1 2

560_0402_5%

R600

1 2

560_0402_5%

10K_0402_5%

B

R602

+5VS

R643 10K_0402_5%
R641 10K_0402_5%@

1

C743

2

1U_0603_10V4Z

PLUG_IN

+VDDA

12

R629
10K_0402_5%

12

R625
10K_0402_5%

1

C

2

B

E

3

12

D29
CH751H-40PT_SOD323-2

2 1

1 2
1 2

SPK_R1

SPK_R2

SPK_L1

SPK_L2

*

C739

1 2

1U_0603_10V4Z

C735 1U_0603_10V4Z

1 2

1 2

R623 2.4K_0402_5%

Q36
2SC2411KT146_SOT23-3

R640 10K_0402_5%

1 2

R642 10K_0402_5%@

1 2

1 2

R661 0_0603_5%

1 2

R662 0_0603_5%

1 2

R663 0_0603_5%

1 2

R665 0_0603_5%

INTSPK_R1

INTSPK_R2

INTSPK_L1

INTSPK_L2

GAIN0 GAIN1 GAIN

00

0

1

0

1

1

MONO_IN

MONO_IN 23

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

Speaker Connector

D

PACDN042_SOT23-3~D

INTSPK_R1
INTSPK_R2
INTSPK_L1
INTSPK_L2

D35

@

E

JSPK1

1

1

2

2

3

5

3

G1

4

6

4

G2

2

3

1

2

3

D34
PACDN042_SOT23-3~D

@

1

ACES_88266-04001~N

CONN@

Microphone In Jack

R6473K_0402_5%

R644

1K_0402_5%

MIC223
MIC123

1 2
1 2

R656

1K_0402_5%

1 2

L38 CHB2012U170_0805

1 2

L40 CHB2012U170_0805

12
12

R6543K_0402_5%

MIC-2
MIC-1

C760

1

2

220P_0402_50V7K

+MIC1_VREFO_R
+MIC1_VREFO_L

MIC_JD23

1

C753

2

220P_0402_50V7K

2

3

D32
PACDN042_SOT23-3~D

@

1

FOX_JA6333L-B3S0-7F~N

5
4
3

6 7
2
1

JMIC1

CONN@

10
9
8

Headphone Out Jack

FOX_JA6333L-B3S0-7F~N

5
4
3

6 7
2
1

JHP1

2

PGND

CONN@

D31
PACDN042_SOT23-3~D

@

1 2

11

OUTR

9

OUTL

4

NC-4

6

NC-6

8

NC-8

12

NC-12

16

NC-16

20

NC-20

SGND

TPA4411MRTJR QFN 20P

17

HP_OUTR
HP_OUTL

Compal Electronics, Inc.

E

24 53Monday, February 18, 2008

10
9
8

0.2

of

6dB

R652 47_0402_5%

HP_OUTL

R657 47_0402_5%

1 2
1 2

PLUG_IN23

HP_R

1 2

L37 CHB2012U170_0805

HP_L

1 2

L39 CHB2012U170_0805

12

12

R655

1K_0402_5%@

R649

1K_0402_5%@

C759

PLUG_IN
HPRHP_OUTR
HPL

2

C752

1

2

3

1

10dB

HP_MUTE#

470P_0402_50V7K

0_0603_5%

U20

14

SHDNR#

18

SHDNL#

15

INR

13

INL

1

C1P

3

C1N

Custom

Date: Sheet

15.6dB

21.6dB1

PLUG_IN#23

HP_RIGHT23
HP_LEFT23

2007/12/28 2007/12/28

C

Compal Secret Data

PLUG_IN#

EAPD

EC_MUTE

1 2

C433 2.2U_0603_6.3V6K

1 2

C438 2.2U_0603_6.3V6K

Deciphered Date

+3VS

5

U19

2

P

B

4

Y

1

A

G

NC7SZ08P5X_NL_SC70-5

3

@

HP_MUTE#

12

R636 0_0402_5%

R314 2.2K_0402_5%

HP_INR HPINR

1 2

HP_INL HPINL

D

1 2

R318 2.2K_0402_5%

1

C434
1U_0603_10V4Z

2

1

470P_0402_50V7K

+3VS

Reserve the 0 ohm resistor.

12

for voltage filtering

R304

C430 1U_0603_10V4Z

10

19

SVDD

PVDD

PVss

SVss

2

5

7

1

C440
1U_0603_10V4Z

2

Title

AMP / Audio Jack

Size Document Number Rev

LA-4131P

5

4

3

2

1

Layout Note: Place close to OZ129 Chipset.

R298

1 2

+3VS_CR

0_0603_5%

D D

100_0402_5%

PCI_CLKRUN#19,28

Q22

AO3413_SOT23

S

G

2
1

C419

2

R324

1 2

D

13

4.7U_0805_10V4Z

0.01U_0402_25V7K~D
C421

PCI_AD[0..31]17,28

PCI_CBE#317,28
PCI_CBE#217,28
PCI_CBE#117,28
PCI_CBE#017,28

CLK_PCI_CB16,28
PCI_DEVSEL#17
PCI_FRAME#17,28

PCI_IRDY#17
PCI_TRDY#17,28
PCI_STOP#17

PCI_PAR17

PCI_REQ0#17

PCI_GNT0#17
PCI_RST#17,21,28

PCI_PIRQG#17

CB_PME#28

R323 100K_0402_5%@
R326 0_0402_5%

0.1U_0402_10V6K

0.1U_0402_10V6K

1

C439

1

2

C445

+3VS_CR

C447

4.7U_0805_10V4Z

1

C426

2

2

PCI_AD31
PCI_AD30
PCI_AD29
PCI_AD28
PCI_AD27
PCI_AD26
PCI_AD25
PCI_AD24
PCI_AD23
PCI_AD22
PCI_AD21
PCI_AD20
PCI_AD19
PCI_AD18
PCI_AD17
PCI_AD16
PCI_AD15
PCI_AD14
PCI_AD13
PCI_AD12
PCI_AD11
PCI_AD10
PCI_AD9
PCI_AD8
PCI_AD7
PCI_AD6
PCI_AD5
PCI_AD4
PCI_AD3
PCI_AD2
PCI_AD1
PCI_AD0

PCI_CBE#3
PCI_CBE#2
PCI_CBE#1
PCI_CBE#0

CBS_IDSELPCI_AD21
CLK_PCI_CB
PCI_DEVSEL#
PCI_FRAME#
PCI_IRDY#
PCI_TRDY#
PCI_STOP#
PCI_PAR
PCI_REQ0#
PCI_GNT0#
PCI_RST#
PCI_PIRQG#
CB_PME#

12

1 2

LED behave:
Idel ---------> low
Accress data --> always high

0.1U_0402_10V6K

U44

19

AD31

20

AD30

21

AD29

22

AD28

23

AD27

24

AD26

25

AD25

27

AD24

29

AD23

30

AD22

31

AD21

32

AD20

34

AD19

35

AD18

36

AD17

37

AD16

47

AD15

48

AD14

49

AD13

50

AD12

51

AD11

52

AD10

53

AD9

54

AD8

57

AD7

58

AD6

59

AD5

60

AD4

61

AD3

62

AD2

63

AD1

64

AD0

28

C/BE3#

38

C/BE2#

46

C/BE1#

55

C/BE0#

5

IDSEL

45

PCI_CLK

42

DEVSEL#

39

FRAME#

40

IRDY#

41

TRDY#

43

STOP#

44

PAR

17

PCI_REQ#

18

PCI_GNT#

1

PCI_RST#

11

INTA#

3

PME#

6

CLKRUN#

106

MEDIA_LED

26

12

56

PCI_VCC

GND

16

PCI_VCC

GND

GND

33

66

15

91

VCC1.814VCC1.8

OZ129

GND

GND

GND

GND

68

115

104

+3VS_CR+1.8VS_CR

1 2

0_0603_5%

4.7U_0805_10V4Z

0.1U_0402_10V6K

1

C446

R299 5.9K_0402_1%

1 2

OZ129XI
OZ129XO

IEEE1394_TPBIAS0
IEEE1394_TPAP0
IEEE1394_TPAN0
IEEE1394_TPBP0
IEEE1394_TPBN0

MC_3V#
SDCLK_MSCLK
SDD3
SDD2
SDD1
SDD0
SD_CMD
SD_WP
SDCD#

XDD7_MSD1
XD_D6
XD_D5
XD_D4
XDD3_MSBS
XDD2_MSD0
XDD1_MSD2
XDD0_MSD3
XDCE#
XDRB#
XDCLE
XDALE
XDWE#
XDRE#
XDWP#
MSCD#
XDCD#

MMCD4
MMCD5

MMCD6
MMCD7

C425

2

+3VS_PHY

7

125

122

120

103

102

VCC3.3

VCC1.8

VCC1.8

VCC3.3

VCC1.892VCC1.8

GND

GND

GND

GND

124

123

121

116

67

VCC3.3

VCC3.3

SD_CLK/MS_CLK

MS_D1/XD_D7

MS_BS/XD_D3
MS_D0/XD_D2
MS_D2/XD_D1
MS_D3/XD_D0

XD_WPO#

PHY_TEST0
PHY_TEST1

AGND

AGND

AGND

AGND70AGND

82

80

77

69

81

79

73

AVCC

AVCC

AVCC

AVCC

78

REF

83

XI

84

XO

76

TPBIAS

75

TPA+

74

TPA-

72

TPB+

71

TPB-

4

MC_3V#

113
111

SD_D3

112

SD_D2

107

SD_D1

108

SD_D0

110

SD_CMD

117

SD_WP

114

SD_CD#

95
93

XD_D6

89

XD_D5

87

XD_D4

88
90
94
96
119

XD_CE#

100

XD_RB#

118

XD_CLE

109

XD_ALE

105

XD_WE#

101

XD_RE#

98
99

MS_CD#

97

XD_CD#

85
86

2

NC

8

NC

9

NC

10

NC

13

NC

126

NC

127

NC

128

NC

AGND

OZH24TN LQFP 128P

65

R621

0_0603_5%

12

+3VS

R306

+3VS_CR

R325
22K_0402_5%

+3VS_CR

G

MC_3V#

2

Layout Note: Place close to J8IN1 pin3.

XDD0_MSD3

R575 0_0402_5%

XDD1_MSD2
XDD2_MSD0
XDD3_MSBS
XD_D4
XD_D5
XD_D6
XDD7_MSD1

XDWE#
XDWP#
XDALE
XDCD#
XDRB#
XDRE#
XDCE#
XDCLE

1 2

R594 0_0402_5%

1 2

R576 0_0402_5%

1 2

R595 0_0402_5%

1 2

R577 0_0402_5%

1 2

R596 0_0402_5%

1 2

R578 0_0402_5%

1 2

R597 0_0402_5%

1 2

R574 0_0402_5%

1 2

R593 0_0402_5%

1 2

R592 0_0402_5%

1 2

R571 0_0402_5%

1 2

R590 0_0402_5%

1 2

R572 0_0402_5%

1 2

R591 0_0402_5%

1 2

R573 0_0402_5%

1 2

+1.8V

R300

+1.8VS_CR

12

R301
470_0402_5%

13

D

Q23
SSM3K7002FU_SC70-3

S

1 2

100K_0402_5%

SUSP32,47

SUSP

2

R315

C435

12

@

1

@

2

G

CLK_PCI_CB

10_0402_5%~D

4.7P_0402_50V8C

C C

B B

A A

C424

Layout Note: Place close to
OZ129 and Shield GND.

C423

12

15P_0402_50V8J

15P_0402_50V8J

S

Q20
AO3413_SOT23-3

D

1 3

1 2

C422

12

C394

1U 10V Z Y5V 0603

X1

24.576MHz_16P_3XG-24576-43E1

+3VS_SD

XDD0
XDD1
XDD2
XDD3
XDD4
XDD5
XDD6
XDD7

XDWE
XDWP
XD_ALE
XDCD
XDRB
XDRE
XDCE
XD_CLE

+3VS_PHY

0.1U_0402_10V6K

1

C418

2

Q21

J8IN1

3

XD-VCC

32

XD-D0

10

XD-D1

9

XD-D2

8

XD-D3

7

XD-D4

6

XD-D5

5

XD-D6

4

XD-D7

34

XD-WE

33

XD-WP

35

XD-ALE

40

XD-CD

39

XD-R/B

38

XD-RE

37

XD-CE

36

XD-CLE

11

7in1-GND

31

7in1-GND

41

7in1-GND

42

7in1-GND

TAITW_R015-A10-LM

4.7U_0805_10V4Z

12

R297
470_0402_5%

13

D

MC_3V#

2

G

SSM3K7002FU_SC70-3

S

7 IN 1 CONN

0.1U_0402_10V6K

1

C420

2

OZ129XI

OZ129XO

1

2

+3VS_SD +3VS_SD

IEEE1394_TPBIAS0

R606

R605

C723

56.2_0402_1%

56.2_0402_1%

12

12

56.2_0402_1%

56.2_0402_1%

12

12

270P_0402_50V7K

5.1K_0402_1%

2

1

1 2

R609

R608

R604

1

C724

2

IEEE1394_TPAP0
IEEE1394_TPAN0
IEEE1394_TPBP0
IEEE1394_TPBN0

1U_0603_10V4Z

Layout Note: Place close to J8IN1 pin21 ,28.

+3VS_SD

1

1

C398

2

1U 10V Z Y5V 0603

2

R565 22_0402_5%

1 2

R568 0_0402_5%

1 2

R569 0_0402_5%

1 2

R580 0_0402_5%

1 2

R561 0_0402_5%

1 2

R562 0_0402_5%

1 2

R564 0_0402_5%

1 2

R566 0_0402_5%

1 2

R567 0_0402_5%

1 2

R588 0_0402_5%

1 2

R570 0_0402_5%

1 2

R563 0_0402_5%

1 2

R581 22_0402_5%

1 2

R587 0_0402_5%

1 2

R583 0_0402_5%

1 2

R585 0_0402_5%

1 2

R586 0_0402_5%

1 2

R584 0_0402_5%

1 2

R582 0_0402_5%

1 2

1U 10V Z Y5V 0603

SD-VCC

MS-VCC

SD_CLK
SD-DAT0
SD-DAT1
SD-DAT2
SD-DAT3
SD-DAT4
SD-DAT5
SD-DAT6
SD-DAT7

SD-CD
SD-WP

SD-CMD

MS-SCLK

MS-BS

MS-INS

MS-DATA0
MS-DATA1
MS-DATA2
MS-DATA3

21
28

20
14
12
30
29
27
23
18
16

1
2
25

26
13
22

17
15
19
24

C397

SDCLK
SDDAT0
SDDAT1
SDDAT2
SDDAT3
SDDAT4
SDDAT5
SDDAT6
SDDAT7

SDCD
SDWP
SDCMD

MSCLK
MSBS
MSINS

MSDATA0
MSDATA1
MSDATA2
MSDATA3

IEEE1394_TPAP0 30
IEEE1394_TPAN0 30
IEEE1394_TPBP0 30
IEEE1394_TPBN0 30

SDCLK

C395

10P_0402_50V8J

@

MSCLK

C396

10P_0402_50V8J

@

SDCLK_MSCLK
SDD0
SDD1
SDD2
SDD3
MMCD4
MMCD5
MMCD6
MMCD7

SDCD#
SD_WP
SD_CMD

SDCLK_MSCLK
XDD3_MSBS
MSCD#

XDD2_MSD0
XDD7_MSD1
XDD1_MSD2
XDD0_MSD3

1

2

1

2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2007/12/28 2007/12/28

Compal Secret Data

Deciphered Date

2

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

OZH24_Card Reader / 1394

LA-4131P

1

25 53Monday, February 18, 2008

of

0.2

5

D D

4

3

2

1

Express Card Power Switch Express Card

+1.5VS_CARD

(1A) (1.5A)

1

1

C6960.1U_0402_16V7K~N

C6990.1U_0402_16V7K~N

+3VALW

C C

1

C7120.1U_0402_16V7K~N

2

PLT_RST#7,17,19,21,22,27,28,31,34

SYSON28,32,45
SUSP#15,28,32,44,47

R579 100K_0402_5%@

+3VALW

B B

1 2

R598 100K_0402_5%@

1 2

1

C7200.1U_0402_16V7K~N

2

1

C6950.1U_0402_16V7K~N

2

PLT_RST#

CPUSB#
EXPR_CPUSB#

+1.5VS+3VS

U46

12

1.5Vin

14

1.5Vin

2

3.3Vin

4

3.3Vin
AUX_IN17AUX_OUT

6

SYSRST#

20

SHDN#

1

STBY#

10

CPPE#

9

CPUSB#

18

RCLKEN

P2231NF_QFN20

1.5Vout

1.5Vout

3.3Vout

3.3Vout

OC#

PERST#

GND

2

2

11
13

3
5

15
19

PERST#

8
16

NC

7

C69810U_0805_4VAM~D

1

2

+3VS_CARD

1

C718

2

10U_0805_4VAM~D

+3VS_CARD_AUX

1

1

C7030.1U_0402_16V7K~N

C7010.1U_0402_16V7K~N

2

2

1

C7210.1U_0402_16V7K~N

2

(0.5A)

1

C7190.1U_0402_16V7K~N

2

ICH_SMB_CLK19
ICH_SMB_DATA19

+1.5VS_CARD

ICH_PCIE_WAKE#19,27

+3VS_CARD_AUX

+3VS_CARD

EXPR_CARD_REQ#16

CPUSB#

CLK_PCIE_EXPR#16

CLK_PCIE_EXPR16

PCIE_RXN219
PCIE_RXP219

PCIE_TXN219
PCIE_TXP219

JEXP1

1

USB20_N7

USB20_N719
USB20_P719

R156 0_0402_5%

USB20_P7

R157 0_0402_5%

EXPR_CPUSB#

R158 0_0402_5%
R159 0_0402_5%

R167 0_0402_5%

PERST#

R186 0_0402_5%

CPUSB#

R199 0_0402_5%

PCIE_RXN2
PCIE_RXP2

PCIE_TXN2
PCIE_TXP2

1 2

1 2
1 2

12
12

12
12

USB20_N7_R
USB20_P7_R

GND

2

USB_D-

3

USB_D+

4

CPUSB#

5

RSV

6

RSV

7

SMB_CLK

8

SMB_DATA

9

+1.5V

10

+1.5V

11

WAKE#

12

+3.3VAUX

13

PERST#

14

+3.3V

15

+3.3V

16

CLKREQ#

17

CPPE#

18

REFCLK-

19

REFCLK+

20

GND

21

PERn0

22

PERp0

23

GND

24

PETn0

25

PETp0

26

GND

27

GND

28

GND

29

GND
GND30GND

FOX_1CX41202-KH_26P

CONN@

GND

31
32

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2007/12/28 2007/12/28

3

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

Compal Electronics, Inc.

Express Card

LA-4131P

0.2

26 53Monday, February 18, 2008

1

of

A

Mini-Express Card---WLAN

ICH_PCIE_WAKE#19,26

CH_DATA

R382 0_0402_5%@

CH_DATA31
CH_CLK31

1 1

2 2

PCIE_RXN419
PCIE_RXP419

PCIE_TXN419

PCIE_TXP419

1

C525

2

0.01U_0402_16V7K

CH_CLK

MCARD_REQ#16

CLK_PCIE_MCARD#16

CLK_PCIE_MCARD16

0.01U_0402_16V7K

R383 0_0402_5%@

PCIE_RXN4
PCIE_RXP4

PCIE_TXN4
PCIE_TXP4

+1.5VS

C528

1

2

1 2
1 2

R50 0_0402_5%

R51 0_0402_5%

1 2
1 2

PCIE_C_RXN4
PCIE_C_RXP4

JMINI1

1

1

3

3

5

5

7

7

9

9

11

11

13

13

15

15

17

17

19

19

21

21

23

23

25

25

27

27

29

29

31

31

33

33

35

35

37

37

39

39

41

41

43

43

45

45

47

47

49

49

51

51

53

GND1

ACES_88911-5204

CONN@

GND2

2

2

4

4

6

6

8

8

10

10

12

12

14

14

16

16

18

18

20

20

22

22

24

24

26

26

28

28

30

30

32

32

34

34

36

36

38

38

40

40

42

42

WLAN_LED#

44

44

46

46

48

48

50

50

52

52

54

+1.5VS

B

+3VS

C527

+3VS

1 2

R380 0_0402_5%

0.01U_0402_16V7K

1

2

R379

@

10K_0402_5%

WL_DIS#

1 2

WLAN_LED# 29

+3VS

4.7U_0805_10V4Z~N

1

C526

0.1U_0402_16V4Z~N

WL_DIS# 28
PLT_RST# 7,17,19,21,22,26,28,31,34

+3VALW

C524

2

C

1

2

Mini-Express Card---Robson

ROBSON_REQ#16

CLK_PCIE_ROB#16
CLK_PCIE_ROB16

CLK_DEBUG_PORT16

PCIE_RXN319
PCIE_RXP319

PCIE_TXN319
PCIE_TXP319

0.01U_0402_16V7K

1

C484

2

4.7U_0805_10V4Z~N

1 2

R376 0_0402_5%

CLK_PCIE_ROB

PLT_RST#

1 2

R367 0_0402_5%
R366 0_0402_5%

PCIE_RXN3

1 2

PCIE_RXP3

1 2

R365 0_0402_5%

PCIE_TXN3
PCIE_TXP3

+3VS

1

C516

2

D

ROB_REQE#

PCIE_C_RXN3
PCIE_C_RXP3

JMINI2

1

1

3

3

5

5

7

7

9

9

11

11

13

13

15

15

17

17

19

19

21

21

23

23

25

25

27

27

29

29

31

31

33

33

35

35

37

37

39

39

41

41

43

43

45

45

47

47

49

49

51

51

53

GND1

ACES_88911-5204

CONN@

+1.5VS +3VS

2

2

4

4

6

6

8

8

10

10

12

12

14

14

16

16

18

18

20

20

22

22

24

24

26

26

28

28

30

30

32

32

34

34

36

36

38

38

40

40

42

42

44

44

46

46

48

48

50

50

52

52

54

GND2

1 2

R375 0_0402_5%

1 2

R373 0_0402_5%

1 2

R370 0_0402_5%

1 2

R369 0_0402_5%

1 2

R368 0_0402_5%

PLT_RST# 7,17,19,21,22,26,28,31,34

DISK_BUSY

T1 PAD

0.01U_0402_16V7K

1

C486

2

LPC_AD3
LPC_AD2CLK_PCIE_ROB#
LPC_AD1
LPC_AD0

E

1

C485

2

0.1U_0402_16V4Z~N

LPC_FRAME# 18,28

LPC_AD[0..3] 18,28

+1.5VS

4.7U_0805_10V4Z~N

C515

1

2

3 3

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2007/12/28 2007/12/28

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Mini Card

Size Document Number Rev

Custom

LA-4131P

D

Date: Sheet

E

27 53Monday, February 18, 2008

0.2

of

CB_PME#25

PCIE_PME#22

EC_SMB_DA1
EC_SMB_CK1
USB_EN#

Low Enable

EC_MUTE

ESB_CLK
ESB_DAT
EC_SMB_DA2
EC_SMB_CK2
MIC_DIAG
BT_DIS#

TP_DATA
TP_CLK

GMCH_ENBKL9

G8X_ENBKL34

CLK_PCI_EC

12

R63
10_0402_5%@

1

C102

@

15P_0402_50V8J

2

+3VALW

+3VALW

R57
10K_0402_5%

R387 0_0402_5% @

R389 0_0402_5%

R55 4.7K_0402_5%
R385 4.7K_0402_5%
R72 4.7K_0402_5%

R390 10K_0402_5%

1 2

R60 4.7K_0402_5%
R388 4.7K_0402_5%
R59 4.7K_0402_5%
R58 4.7K_0402_5%
R391 10K_0402_5%

1 2

R384 10K_0402_5%@

R392 10K_0402_5%

1 2

R62 10K_0402_5%

1 2

1 2
1 2
1 2

12
12
12

12
12
12
12

12

R348 0_0402_5%UMA@

R347 0_0402_5%VGA@

1 2

R52 47K_0402_5%

0.1U_0402_16V4Z

EC_PME#

+5VALW

+3VALW

+3VS

+5VS

12
12

2

C90

1

EC_ENBKL

R345

2.2K_0402_5%

VGA@

R345

100K_0402_5%

UMA@

+3VALW +EC_AVCC

L8

C95

1000P_0402_50V7K~N

C110

0.1U_0402_16V4Z~N

C103

0.1U_0402_16V4Z~N

C534

0.1U_0402_16V4Z~N

1

2

GATEA2018
KB_RST#18
SERIRQ19

LPC_FRAME#18,27

LPC_AD318,27
LPC_AD218,27
LPC_AD118,27
LPC_AD018,27

CLK_PCI_EC16
PLT_RST#7,17,19,21,22,26,27,31,34

EC_SCI#19

PCI_CLKRUN#19,25

KSI[0..7]29

KSO[0..17]29

EC_SMB_CK115,49
EC_SMB_DA115,49
EC_SMB_CK24,29,34
EC_SMB_DA24,29,34

SLP_S3#19
SLP_S5#19
EC_SMI#19

ESB_CLK29

ESB_DAT29

EC_PME#17
VGA_LVDDEN15,34
FAN_SPEED14

GMCH_LVDDEN9,15

VGA_THER#34
ON_OFF29

PWR_SUS_LED#29

NUMLED#29

1

1

2

2

GATEA20
KB_RST#
SERIRQ
LPC_FRAME#
LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0

CLK_PCI_EC
PLT_RST#
EC_RST#
EC_SCI#
PCI_CLKRUN#

KSI[0..7]
KSO[0..17]

EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2

SLP_S3#
SLP_S5#
EC_SMI#
LID_SW#
ESB_CLK
ESB_DAT
EC_PME#
VGA_LVDDEN
FAN_SPEED1
GMCH_LVDDEN

E51_TXD

VGA_THER#
ON_OFF
PWR_SUS_LED#

NUMLED#

XCLKI
XCLKO

XCLKO XCLKI

R71

1 2

20M_0603_5%@

1

C112

IN

2

15P_0402_50V8J

C533

1000P_0402_50V7K~N

C89

0.1U_0402_16V4Z~N

1

2

10
12

13
37
20
38

KSI0

55

KSI1

56

KSI2

57

KSI3

58

KSI4

59

KSI5

60

KSI6

61

KSI7

62

KSO0

39

KSO1

40

KSO2

41

KSO3

42

KSO4

43

KSO5

44

KSO6

45

KSO7

46

KSO8

47

KSO9

48

KSO10

49

KSO11

50

KSO12

51

KSO13

52

KSO14

53

KSO15

54

KSO16

81

KSO17

82

77
78
79
80

14
15
16
17
18
19
25
28
29
30
31
32
34
36

122
123

4

OUT

NC3NC

X2

32.768KHZ QTFM28-32768K125P20L

1

2

U28

1

GA20/GPIO00

2

KBRST#/GPIO01

3

SERIRQ#

4

LFRAME#

5

LAD3

7

LAD2

8

LAD1

LPC & MISC

LAD0
PCICLK

PCIRST#/GPIO05
ECRST#
SCI#/GPIO0E
CLKRUN#/GPIO1D

KSI0/GPIO30
KSI1/GPIO31
KSI2/GPIO32
KSI3/GPIO33
KSI4/GPIO34
KSI5/GPIO35
KSI6/GPIO36
KSI7/GPIO37
KSO0/GPIO20
KSO1/GPIO21
KSO2/GPIO22
KSO3/GPIO23
KSO4/GPIO24
KSO5/GPIO25
KSO6/GPIO26
KSO7/GPIO27
KSO8/GPIO28
KSO9/GPIO29
KSO10/GPIO2A
KSO11/GPIO2B
KSO12/GPIO2C
KSO13/GPIO2D
KSO14/GPIO2E
KSO15/GPIO2F
KSO16/GPIO48
KSO17/GPIO49

SCL1/GPIO44
SDA1/GPIO45
SCL2/GPIO46
SDA2/GPIO47

6

PM_SLP_S3#/GPIO04
PM_SLP_S5#/GPIO07
EC_SMI#/GPIO08
LID_SW#/GPIO0A
SUSP#/GPIO0B
PBTN_OUT#/GPIO0C
EC_PME#/GPIO0D
EC_THERM#/GPIO11
FAN_SPEED1/FANFB1/GPIO14
FANFB2/GPIO15
EC_TX/GPIO16
EC_RX/GPIO17
ON_OFF/GPIO18
PWR_LED#/GPIO19
NUMLED#/GPIO1A

XCLK1
XCLK0

KB926QFC0 LQFP 128P

C111

15P_0402_50V8J

1

2

Int. K/B
Matrix

SM Bus

C98

ECAGND

FANPWM1/GPIO12

ADP_I/AD2/GPIO3A

AD3/GPIO3B

AD4/GPIO42

IREF/DA2/GPIO3E

DA3/GPIO3F

PSCLK1/GPIO4A
PSDAT1/GPIO4B
PSCLK2/GPIO4C

PSDAT2/GPIO4D

SDICS#/GPXOA00
SDICLK/GPXOA01

SDIDO/GPXOA02

SDIDI/GPXID0

SPIDI/RD#

SPIDO/WR#

SPICLK/GPIO58

SPICS#

CIR_RX/GPIO40

SYSON/GPIO56

AC_IN/GPIO59

EC_ON/GPXO05

EC_SWI#/GPXO06

BKOFF#/GPXO08

WL_OFF#/GPXO09

GPXO10
GPXO11

ENBKL/GPXID2

GPXID3
GPXID4
GPXID5
GPXID6
GPXID7

V18R

0.1U_0402_10V7K~N

ICH_PWROK

1 2

R396 0_0402_5%

VGATE

1 2

R395 0_0402_5%@

21
23
26
27

63
64
65
66
75
76

68
70
71
72

83
84
85
86
87
88

97
98
99
109

119
120
126
128

73
74
89
90
91
92
93
95
121
127

100
101
102
103
104
105
106
107
108

110
112
114
115
116
117
118

124

9

22

33

96

111

125

VCC

VCC

VCC

VCC

VCC

VCC

INVT_PWM/PWM1/GPIO0F

ACOFF/FANPWM2/GPIO13

PWM Output

AD Input

DA Output

PS2 Interface

TP_DATA/PSDAT3/GPIO4F

SPI Device Interface

SPI Flash ROM

GPIO

GPO

GPIO

GPI

GND

GND

GND

GND

GND

11

24

35

94

113

1000P_0402_50V7K~N

67

AVCC

BEEP#/PWM2/GPIO10

BATT_TEMP/AD0/GPIO38

BATT_OVP/AD1/GPIO39

SELIO2#/AD5/GPIO43

DAC_BRIG/DA0/GPIO3C

EN_DFAN1/DA1/GPIO3D

TP_CLK/PSCLK3/GPIO4E

CIR_RLC_TX/GPIO41

FSTCHG/SELIO#/GPIO50

BATT_CHGI_LED#/GPIO52

CAPS_LED#/GPIO53

BATT_LOW_LED#/GPIO54

SUSP_LED#/GPIO55

VR_ON/XCLK32K/GPIO57

EC_RSMRST#/GPXO03
EC_LID_OUT#/GPXO04

ICH_PWROK/GPXO06

PM_SLP_S4#/GPXID1

AGND

69

ECAGND BATT_TEMP

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C532

1

2

R56 0_0402_5%

1 2

BEEP#
ADP_C
ACOFF

BATT_TEMP
BATT_OVP
ADP_I
AD_BID
MIC_DIAG
POW_MON

BT_DIS#

EN_DFAN1
IREF

1 2

R386 0_0402_5%

EC_MUTE
BIST
VGA_ON
LCD_DET#
TP_CLK
TP_DATA

SPI_PULLDOWN
EN_WOL#
STB_SB
VGATE

FRD#SPI_SO
FWR#SPI_SI
SPI_CLK
FSEL#SPICS#

MSEN#
FSTCHG
BATT_CHG_LED#
CAPSLED#
BATT_LOW_LED#
USB_EN#
SYSON
VR_ON
ACIN

EC_RSMRST#
EC_LID_OUT#
EC_ON
EC_SWI#
ICH_PWROK

WL_DIS#

LCD_TEST_EN

SCRLED#

PSID_DISABLE#

SLP_S4#
EC_ENBKL
W_DISABLE#
EC_THERM#
SUSP#
PBTN_OUT#
PS_ID

1

C536

2

C92100P 25V K NPO 0402

12

C91100P 25V K NPO 0402

12

2007/12/28 2007/12/28

2

1

12

FBM-11-160808-601-T_0603

0.1U_0402_16V4Z~N

C119 100P 25V K NPO 0402

1 2

1

2

BATT_OVP

PM_PWROK 7,19

+3VALW

12

L27FBM-11-160808-601-T_0603

INVT_PWM 15
BEEP# 24
ADP_C 42
ACOFF 42

BATT_TEMP 49
BATT_OVP 49
ADP_I 42

MIC_DIAG 31
POW_MON 48

BT_DIS# 31
EN_DFAN1 4
IREF 42
CHGVADJ 42

EC_MUTE 24
BIST 15
VGA_ON 46
LCD_DET# 15
TP_CLK 29
TP_DATA 29

R67 4.7K_0402_5%

12
EN_WOL# 22
STB_SB 32

VGATE 19,48

TS_RST# 29
MSEN# 15
FSTCHG 42

BATT_CHG_LED# 29

CAPSLED# 29

BATT_LOW_LED# 29
USB_EN# 30

SYSON 26,32,45
VR_ON 48
ACIN 19,41,42

EC_RSMRST# 19
EC_LID_OUT# 19
EC_ON 29
EC_SWI# 19

WL_DIS# 27

LCD_TEST_EN 15

SCRLED# 29

PSID_DISABLE# 41

SLP_S4# 19
W_DISABLE# 30

EC_THERM# 4,19

SUSP# 15,26,32,44,47
PBTN_OUT# 19
PS_ID 41

C535

4.7U_0603_6.3V X5R

Compal Secret Data

Deciphered Date

+3VALW

E51_TXD

REED Switch

Q28
APX9132ATI-TRL_SOT23-3

LID_SW#

3

C488

1 2

0.1U_0402_16V4Z~N

10K_0402_5%

FSEL#SPICS#

R377 15_0402_5%

SPI_CLK

R371 15_0402_5%
R372 15_0402_5%

JBIOS1

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20

ACES_85201-2005

CONN@

PLT_RST#7,17,19,21,22,26,27,31,34

+3VS

+3VALW

VOUT

R374

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

1
2
3
4

JECDB1

1
2
3

4

ACES_85205-0400

CONN@

2

VDD

GND

1

+3VALW

Board ID

+3VALW

12

R53

100K_0402_5%

18K_0402_5%

M/B rev:0.1; 0.2; 0.3; 1.0
Voltage:0.0; 0.4; 0.8; 1.0

Ra

12

R54

Rb

SPI Flash (8Mb*1)

+3VALW

1 2

20mils

12
12
12

SPI_CS#
SPI_CLK_R
SPI_SI FRD#SPI_SOFWR#SPI_SI

U29

8

VCC

VSS

3

W

7

HOLD

1

S

6

C

5

SST25LF080A_SO8-200mil

Q

D

4

2

SPI_SO

R378 15_0402_5%

For BIOS_PCI DeBug Port

PCI_AD9
PCI_TRDY#
PCI_FRAME#
PCI_RST#

PCI_CBE#3
PCI_CBE#2
PCI_CBE#1
PCI_AD8
PCI_AD7
PCI_AD5
PCI_AD3
PCI_AD1
PCI_AD0
PCI_AD2
PCI_AD4
PCI_AD6
PCI_CBE#0

PCI_AD9 17,25
PCI_TRDY# 17,25
PCI_FRAME# 17,25
PCI_RST# 17,21,25

+5VS

R651

1 2

0_0402_5%

PCI_CBE#3 17,25
PCI_CBE#2 17,25
PCI_CBE#1 17,25
PCI_AD8 17,25
PCI_AD7 17,25
PCI_AD5 17,25
PCI_AD3 17,25
PCI_AD1 17,25
PCI_AD0 17,25
PCI_AD2 17,25
PCI_AD4 17,25
PCI_AD6 17,25
PCI_CBE#0 17,25

CLK_PCI_CBL_CLK_PCI_CB

TPM 1.2 Conn

LPC_FRAME#
PLT_RST#
SERIRQ
PCI_CLKRUN#

12mA

JTPM1

1

GND1

3

IAC_SDATA_OUT

5

GND2

7

IAC_SYNC

9

IAC_SDATA_IN

11

IAC_RESET#

GND13GND14GND15GND16GND17GND

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

EC_KB926/Reed Switch/BIOS/TPM

LA-4131P

RES0
RES1

GND3
GND4

IAC_BITCLK

18

2
4
6

3.3V

8
10
12

ACES_88018-124L

2007-11-22 change Brd ID

AD_BID

1

C96

0.1U_0402_16V4Z

2

C487

@

SPI_CLK_R

1 2

0.1U_0402_16V4Z~N

12

CLK_PCI_CB 16,25

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3

CLK_PCI_TPM 16

of

28 53Monday, February 18, 2008

0.2

A

Power Button

Power Switch

SW1

@

SW_1BT002-0121L_4P

1 1

2 2

BATT_LOW_LED#28
BATT_CHG_LED#28

3 3

3
4

EC_ON28

BATT_LOW_LED#
BATT_CHG_LED#

1
2

5

6

PWR_ON-OFF_BTN#

1 2
1 2

PWR_SUS_LED#28

+3VALW

R29

D5

2

1

3

DAN202U_SC70

2

G

12

R33
10K_0402_5%

R659 220_0402_5%
R660 220_0402_5%

PWR_SUS_LED#

B

1 2

100K_0402_5%

51ON#

2

C42
1000P_0402_50V7K~N

1

13

D

Q5
SSM3K7002FU_SC70-3

S

D16

Y

3
2

B

12-22/Y2BHC-A30/2C_Y/B~D

D17

12-21-BHC-ZL1M2RY-2C BLUE

C

INT_KBD Conn.

KSI[0..7]

KSO[0..17]

KSO10
KSO11
KSO12
KSO13
KSO14
KSO15
KSO16
KSO17

ON_OFF 28
51ON# 41

12

D8
RLZ20A_LL34

KSI[0..7]28

KSO[0..17]28

Function/B Conn.

For Cypress

EC_SMB_DA24,28,34

EC_SMB_CK24,28,34

ESB_CLK28

+5VALW

1

R327

1 2

12

220_0402_5%

ESB_DAT28

For ENE ( Close to JFN1 ).

SATA_LED#18

ODD_ACT_LED#21

R31 0_0402_5%@

1 2

R30 0_0402_5%@

1 2

MBK1005801YZF 0402

1 2
1 2

MBK1005801YZF 0402

100P_0402_25V8K

SATA_LED# PWR_ON-OFF_BTN#
ODD_ACT_LED#

KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9

10
11
12
13
14
15
16
17
18

KSI0

19

KSI1

20

KSI2

21

KSI3

22

KSI4

23

KSI5

24

KSI6

25

KSI7

26
27
28

ACES_88514-2601_26P

L6
L7

C37

+3VS

5

2

P

B

1

A

G

3

D

JKB1

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
G1
G2

CONN@

TS_RST#28

1

1

C38
100P_0402_25V8K

@

@

2

2

C376

12

0.1U_0402_16V4Z

U31

IDE_ACT_LED#

4

Y

NC7SZ08P5X_NL_SC70-5

KSO8

C506 100P_0402_25V8K

KSI3

C493 100P_0402_25V8K

KSO9

C505 100P_0402_25V8K

KSI2

C494 100P_0402_25V8K

KSI1

C495 100P_0402_25V8K

KSO10

C504 100P_0402_25V8K

KSO11

C503 100P_0402_25V8K

KSI0

C496 100P_0402_25V8K

KSO12

C502 100P_0402_25V8K

KSO13

C501 100P_0402_25V8K

KSO14

C500 100P_0402_25V8K

KSO15

C499 100P_0402_25V8K

KSO16

C498 100P_0402_25V8K

KSO17

C497 100P_0402_25V8K

WLAN_LED#27

PWR_SUS_LED#28

+3VS

BT_LED#31

TS_RST#

CAPSLED#28

SCRLED#28

NUMLED#28

@

1 2

L5

BK1608LL121-T 0603

+3VALW

IDE_ACT_LED#
PWR_ON-OFF_BTN#

WLAN_LED#
FN_SDATA
FN_SCLK

BT_LED#

PWR_SUS_LED#

R28 0_0402_5%

1 2

NUMLED#
CAPSLED#
SCRLED#

E

KSI7

C490 100P_0402_25V8K

KSI6

C489 100P_0402_25V8K

KSI5

C491 100P_0402_25V8K

KSO0

C514 100P_0402_25V8K

KSO1

C513 100P_0402_25V8K

KSO2

C512 100P_0402_25V8K

KSI4

C492 100P_0402_25V8K

KSO3

C511 100P_0402_25V8K

KSO4

C510 100P_0402_25V8K

KSO5

C509 100P_0402_25V8K

KSO6

C508 100P_0402_25V8K

KSO7

C507 100P_0402_25V8K

+3VS_FUN

+3VALW

D7

1

DAN217_SC59

@

For EMI

JFN1

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

11

11

12

12

13

13

14

14

15

15

16

16

17

GND

18

GND

ACES_88512-1641_16P

CONN@

3
2

Regulator for ENE sensor

1U_0402_6.3V4Z

1

2

Adjustable Output

R32

1 2

10K_0603_1%

+5VS

C43

4 4

A

APL5151-33BC-TRL SOT23 5P 3.3V

SHDN#3BP

2

GND

1

VIN

U55

VOUT

4

5

B

+3VS_FUN

2

C41

.33U 10V +-10% X7R 0603

1

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Touch Pad/B Conn.

2007/12/28 2007/12/28

C

C147

0.01U_0402_16V7K

Compal Secret Data

Deciphered Date

+5VS

1

2

TP/B to M/B

TP_DATA28
TP_CLK28

D

JP2

1

TP_DATA
TP_CLK

2

1

1

@

@

C139100P_0402_25V8K

C136100P_0402_25V8K

2

2

1

Title

Size Document Number Rev

Custom

Date: Sheet

1

2

2

3

3

4

4

5

G1

6

G2

ACES_88514-0441_4P

3

CONN@

D9
SM05T1G_SOT23-3~D

@

Compal Electronics, Inc.

PWR_OK / BTN / KB / TP

LA-4131P

E

0.2

of

29 53Monday, February 18, 2008

A

B

C

D

E

+5VALW

W=40mils

R27

1

C15

0.1U_0402_16V4Z

1 1

USB_EN#28

2

1 2

0_0402_5%

USB_OC#019

W=80mils

0.1U_0402_16V4Z

2 2

2

1

C631

USB_EN#

R451

1 2

0_0402_5%

USB_OC#119
USB_OC#219

W=40mils

0.1U_0402_16V4Z

3 3

2

1

C731

USB_EN#

R617

1 2

0_0402_5%

USB_OC#319

U32

1

GND

2

IN

3

IN

4

EN#

RT9711PS SO 8P

USB_EN#

U33

1

GND

2

IN

3

IN

4

EN#

RT9711PS SO 8P

R425 0_0402_5%
R420 0_0402_5%

USB_EN#

U34

1

GND

2

IN

3

IN

4

EN#

RT9711PS SO 8P

R615 0_0402_5%

USB_EN#

OUT
OUT
OUT
OC#

OUT
OUT
OUT
OC#

OUT
OUT
OUT
OC#

+USB_AS

8
7
6
5

12

R26
100K_0402_5%

+USB_BS+5VALW

8
7
6
5

12
12

12

R423
100K_0402_5%

+USB_CS+5VALW

8
7
6
5

12

12

R616
100K_0402_5%

W=40mils

12

R23

13

D

2

G

S

W=80mils

12

R419

13

D

2

G

S

W=40mils

12

R622

13

D

2

G

S

Close to USB Connector.

1

C23

+

2

470_0402_5%

Q4
SSM3K7002FU_SC70-3

150U_Y_6.3VM

Close to USB Connector.

1

C606

+

2

470_0402_5%

Q33
SSM3K7002FU_SC70-3

150U_Y_6.3VM

Close to USB Connector.

1

C750

+

2

470_0402_5%

Q37
SSM3K7002FU_SC70-3

220U_6.3V_M

C24

C267

C437

+USB_AS

W=40mils

USB20_N419

USB20_P419

0.1U_0402_16V4Z

USB20_N919

USB20_P919

0.1U_0402_16V4Z

0.1U_0402_16V4Z

USB20_N819

USB20_P819

USB20_N619

USB20_P619

USB20_N4

USB20_P4

USB20_N9

USB20_P9

USB20_N8

USB20_P8

USB20_N6

USB20_P6

L4

@

4

4

1

1

R24 0_0402_5%
R25 0_0402_5%

1

1

4

4

R102 0_0402_5%
R99 0_0402_5%

4

4

1

1

R110 0_0402_5%
R115 0_0402_5%

4

4

1

1

R320 0_0402_5%
R322 0_0402_5%

3

2

WCM-2012-900T_4P

12
12

L11

@

2

3

WCM-2012-900T_4P

12
12

L13

@

3

2

WCM-2012-900T_4P

12
12

L22

@

3

2

WCM-2012-900T_4P

12
12

3

USB_P4­USB_P4+

2

+USB_BS

2

USB_P9-

3

USB_P9+

+USB_BS

3

USB_P8­USB_P8+

2

+USB_CS

3

USB_P6­USB_P6+

2

JUSBP1

1

VCC

2

USB_N

3

USB_P

4

GND

5

GND

6

GND

7

GND

8

GND

TYCO_0-1775501-1_4P-T

CONN@

W=40mils

JUSBP2

1

VCC

2

USB_N

3

USB_P

4

GND

5

GND

6

GND

7

GND

8

GND

TYCO_0-1775501-1_4P-T

CONN@

W=40mils

JUSBP3

1

VCC

2

USB_N

3

USB_P

4

GND

5

GND

6

GND

7

GND

8

GND

TYCO_0-1775501-1_4P-T

CONN@

W=40mils

JUSBP4

1

VCC

2

USB_N

3

USB_P

4

GND

5

GND

6

GND

7

GND

8

GND

TYCO_0-1775501-1_4P-T

CONN@

+USB_BS

USB_P8-

USB_P8+

+USB_CS

CM1293A-04SO SOT23-6

1

2

3

D26

CH4

CH1

Vn

CH3

CH2

D11

6

CH23CH3

5

Vn

Vp

4

CH1

CH4

NUP4301MR6T1_TSOP6

D33

6

CH23CH3

5

Vn

Vp

4

CH1

CH4

NUP4301MR6T1_TSOP6

USB_P4+

4

5

+USB_AS

Vp

USB_P4-

6

USB_P9+

2

USB_P9-

1

USB_P6-

2

USB_P6+

1

+3VS +USB_DS

Deciphered Date

D

W=80mils

JUSBP5

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

11

11

12

12

13

13

14

14

ACES_87213-1400G

CONN@

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

USB / 1394 Conn

LA-4131P

of

E

30 53Monday, February 18, 2008

0.2

+5VALW +USB_DS

W=80mils

0.1U_0402_16V4Z

4 4

2

A

1

C427

USB_EN#

R310

1 2

0_0402_5%

USB_OC#419

U51

1

GND

2

IN

3

IN

4

EN#

RT9711PS SO 8P

R313 0_0402_5%

USB_EN#

B

OUT
OUT
OUT
OC#

8
7
6
5

12

12

R309
100K_0402_5%

W=80mils

R316

2

G

12

470_0402_5%

13

D

Q27
SSM3K7002FU_SC70-3

S

IEEE1394_TPBN025
IEEE1394_TPBP025
IEEE1394_TPAN025
IEEE1394_TPAP025

USB20_P219
USB20_N219
USB20_P319
USB20_N319

W_DISABLE#28

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2007/12/28 2007/12/28

Compal Secret Data

C727
18P_0402_50V8J~N

@

BLM21AG601SN1D_0805~D

PLT_RST#7,17,19,21,22,26,27,28,34

Y5

1 2

12MHZ_16PF_6X12000012

2

2

@

1

1

+1.8VD +VDD +3VS +AVDD

C729
18P_0402_50V8J~N

@

PLT_RST#

R628
1K_0402_5%

@

1 2

L36

@

1 2

+3VS

1 2

0_0402_5%

1 2

@

0_0402_5%

@

R633

R589

C722

@

1

2

+1.8VD

C708

@

U_XTAL1
U_XTAL2U_XTAL2U_XTAL1

1

C705

@

2

4.7U_0805_10V4Z~N
1000P_0402_50V7K~N

1

1

2

AU6254_LQFP48_7x7

2

C728 0.1U_0402_10V7K~N

@

U49

0.1U_0402_10V7K~N

18

BUS_PWREDN

19

EEPENABLE

20

E2PCLK

21

E2PDAT

34

SUSPEND

37

ChipReset#

48

UP_RREF

26

DP4_LEDAM

27

DP4_LEDGR

28

DP3_LEDAM

29

DP3_LEDGR

30

DP2_LEDAM

31

DP2_LEDGR

32

DP1_LEDAM

33

DP1_LEDGR

3

XSCI

2

XSCO

@

1

C726

@

2

0.1U_0402_10V7K~N

+VDD

1

2

C706 0.1U_0402_10V7K~N

@

16

38

15

V18

VSS

22

1

35

23

VDD

VDD

VDDH

VDDH

PVSS4AVSS

VSSH

VSS

VSSH

5

17

36

39

L35

@

1 2

BLM21AG601SN1D_0805~D

1

2

C732

@

+AVDD

14

43

47

AVDD

AVDD

AVDD

AVDD

USB_DM
USB_DP

USB1_DM

USB1_DP

DP2_DM

DP2_DP

DP3_DM

DP3_DP

DP4_DM

DP4_DP

DP1_PWRUP

DP1_OVRCUR

AVSS

AVSS

AVSS

40

44

@

41
42

45
46

6
7

10
11

12
13

24
25

8

PVDD

9

C717

1

C704

@

2

4.7U_0805_10V4Z~N

+3VS

1

2

C707

@

0.1U_0402_10V7K~N

0.1U_0402_10V7K~N

1

1

C710

C709

2

2

@

@

0.1U_0402_10V7K~N

0.1U_0402_10V7K~N
R626 0_0402_5%@

1 2

R627 0_0402_5%@

1 2

U_USBP1­U_USBP1+

U_USBP2­U_USBP2+

C734

@

1

2

1

2

0.1U_0402_10V7K~N

R631 0_0402_5%@
R632 0_0402_5%@

R607 0_0402_5%@
R603 0_0402_5%@

C733

@

1000P_0402_50V7K~N

1 2
1 2

1 2
1 2

D6

1

CH1

2

Vn

1

2

0.1U_0402_10V7K~N

DMIC_DATA

3

CH2

CM1293A-04SO SOT23-6

@

Reserve for ESD.

(Close to JCA1)

CH4

CH3

USB20_N5DMIC_CLK

4

5

6

+5VS

USB20_P5

Vp

Camera Conn

JCA1

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

11

GND

12

GND

ACES_88460-1001

CONN@

100P_0402_25V8K

USB20_N5 19
USB20_P5 19

W=20mils
W=20mils

USB20_P5

TP1

USB20_N5

DMIC_DATA23

DMIC_CLK23

MIC_DIAG28

+5VS
+3VS

1

1

C39

C40

2

2

100P_0402_25V8K

Felica Conn

JFE1

1

LEC

TP2

USB20_P0
USB20_N0

+5VS

C417

10U_0805_10V4Z

1

2

2
3
4
5

ACES_88512-0641_6P

1
2
3
4
5

G2

66G1

CONN@

8
7

D10

1

2

3

CH4

CH1

Vn

CH2

CM1293A-04SO SOT23-6

Vp

CH3

(Close to JFP1)

4

5

6

USB20_P0

USB20_N0

Finger Printer

JFP1

1

1

2

2

+3VS

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

+3VS

USB20_P019
USB20_N019

USB20_P0
USB20_N0

2007/12/28 2007/12/28

3

3

4

4

5

8

5

G2

7

66G1

ACES_88512-0641_6P

CONN@

Compal Secret Data

Deciphered Date

Blue Tooth

JBT1

1

1

USB20_P119
USB20_N119

CH_CLK27

BT_DIS#28
CH_DATA27

BT_LED#29

BT_ACTIVE

TP4

BT_DIS#

+3VS

Title

Size Document Number Rev

Custom

Date: Sheet

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

11

GND

12

GND

ACES_88460-1001

CONN@

Compal Electronics, Inc.

USB Hub / Camera / Felcia / FP/ BT

LA-4131P

of

31 53Monday, February 18, 2008

0.2

A

B

C

D

E

+3VALW to +3VS Transfer +5VALW to +5VS Transfer

C675

1

S

2

S

3

S

4

G

+3VS+3VALW

10U_0805_10V4Z~N

1

C668

2

0.1U_0402_16V4Z~N

U36

D
D
D
D

AO4466 1N SO8

R476
47K_0402_5%

R303

12

VGA_PWGOD

1

S

2

S

3

S

4

G

5VS_GATERUNON

1

C643

0.01U_0402_25V7K~D

2

STB_SB#

2

G

12

+3VALW

R45

100K_0402_5%

VGA@

VGA_PWGOD#

2

G

+5VALW

1 2

13

12

13

D

S

D

S

8
7
6

1

C659

2

STB_SB28

1

C642

5

2

10U_0805_10V4Z~N

1 2

STB_SB STB_SB_R

R302

1 2

0_0402_5%

100K_0402_5%

+5VALW

R41

100K_0402_5%

@

VGA_PWGOD46

B+_BIAS +5VALW +5VS

12

13

D

Q35

SSM3K7002FU_SC70-3

S

100K_0402_5%

SYSON#

SYSON

R40

10K_0402_5%

SUSP

SUSP#

R188

10K_0402_5%

1

2

1 2

1 2

R518

1 1

2 2

3 3

330K_0402_5%

RUNON

SUSP

SYSON26,28,45

SUSP25,47

SUSP#15,26,28,44,47

2

G

U35

8

D

7

D

6

D

C645

5

D

AO4466 1N SO8

10U_0805_10V4Z~N

1 2

R508
100K_0402_5%

+3VALW

12

R44

61

Q8A

2

2N7002DW-T/R7_SOT363-6~D

+5VALW

12

R165
100K_0402_5%

13

D

Q13

2

SSM3K7002FU_SC70-3

G

S

3VS_GATERUNON

1

0.01U_0402_25V7K~D

2

6.5A4.5A

1

1

C634

C641
10U_0805_10V4Z~N

2

2

0.1U_0402_16V4Z~N

R308
100K_0402_5%

Q24
SSM3K7002FU_SC70-3

Q7
SSM3K7002FU_SC70-3

VGA@

B+_BIAS

+1.8V to +1.8VS Transfer ( For Discrete )

VGA Discharge Circuit

SUSP VGA_PWGOD#

+VGA_CORE +1.8VS

12

13

D

2

G

S

+3VALW to +3V_SB

+3VALW

2

U37

10U_0805_10V4Z~N

1

C432

2

R307

1 2

330K_0402_5%

STB_SB#

VGA_PWGOD#

R238
470_0402_5%

VGA@

Q15
SSM3K7002FU_SC70-3

VGA@

8

D

7

D

6

D

5

D

AO4466 1N SO8

13

D

2

G

S

SSM3K7002FU_SC70-3

R68

1 2

100K_0402_5%

VGA@

3VSB_GATE

Q25

JP3

112

JUMP_43X79@

1

S

2

S

3

S

4

G

R61

47K_0402_5%

VGA@

2

1

C114

VGA@

2

0.1U_0402_16V4Z~N

SUSP

2

+3V_SB

10U_0805_10V4Z~N

1

C431

0.1U_0402_16V4Z~N

2

SSM3K7002FU_SC70-3

1

C428

0.01U_0402_25V7K~D

2

B+_BIAS

10U_0805_10V4Z~N

1

C97

VGA@

1 2

2

R66

1.8VS ON 1.8VS_GATE

1 2

100K_0402_5%

13

D

G

S

+1.2VS

12

13

D

G

S

VGA@

Q9

SSM3K7002FU_SC70-3

VGA@

R253
470_0402_5%

VGA@

Q18
SSM3K7002FU_SC70-3

VGA@

1

C429

2

Q26

U41

8

D

7

D

6

D

5

D

AO4466 1N SO8

VGA@

1

2

12

R311
470_0402_5%

13

D

STB_SB#

2

G

S

1

S

2

S

3

S

4

G

C105

0.01U_0402_25V7K~D

VGA@

2

G

+1.8VS+1.8V

C104

0.1U_0402_16V4Z~N

1

VGA@

2

12

R239
470_0402_5%

VGA@

13

D

Q14
SSM3K7002FU_SC70-3

VGA@

S

4.7A

10U_0805_10V4Z~N

1

2

C106

VGA@

Discharge Circuit

+5VS +3VS

12

R46
470_0402_5%

3

4 4

Q8B

5

2N7002DW-T/R7_SOT363-6~D

4

12

R34
470_0402_5%

61

Q6A

2

2N7002DW-T/R7_SOT363-6~D

SUSP

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

12

R492
470_0402_5%

13

D

Q34

2

SSM3K7002FU_SC70-3

G

S

2007/12/28 2007/12/28

C

Compal Secret Data

+1.5VS +1.25VS +0.9VS+1.8V

12

R166
470_0402_5%

13

2

G

D

Q11
SSM3K7002FU_SC70-3

S

SUSP SUSP

Deciphered Date

D

12

R252
470_0402_5%

13

D

Q19

2

SSM3K7002FU_SC70-3

G

S

Title

DC/DC Interface

Size Document Number Rev

Custom

LA-4131P

Date: Sheet

SUSPSYSON# SUSP

Compal Electronics, Inc.

12

R35
470_0402_5%

3

Q6B

5

2N7002DW-T/R7_SOT363-6~D

4

E

0.2

of

32 53Monday, February 18, 2008

5

D D

4

3

2

1

FD5

FD1

FD2

FD3

FIDUCAL

@

H_4P2

C C

H_3P2

H_3P7

B B

H_3P2

FIDUCAL

@

@

1

1

H6

H11

HOLEA@

HOLEA@

1

1

H1
HOLEA@

1

H9

H3

HOLEA@

HOLEA@

1

1

H2

H4

HOLEA@

HOLEA@

1

1

H23

H22

HOLEA@

HOLEA@

1

1

FIDUCAL

1

H7
HOLEA@

1

H17
HOLEA@

1

H5
HOLEA@

1

H24
HOLEA@

1

FD4
FIDUCAL

@

@

1

H10
HOLEA@

1

H8
HOLEA@

1

H25
HOLEA@

1

FIDUCAL

1

H18
HOLEA@

1

H12
HOLEA@

1

H26
HOLEA@

1

FD8
FIDUCAL

@

@

1

H19
HOLEA@

1

H13
HOLEA@

1

H27
HOLEA@

1

FD6
FIDUCAL

1

H21
HOLEA@

1

H14
HOLEA@

1

H33
HOLEA@

1

@

FD7
FIDUCAL

1

H15
HOLEA@

1

H20

H16

H_2P5

A A

NPTH

HOLEA@

1

H29
HOLEA@

1

H31
HOLEA@

1

5

H28

HOLEA@

HOLEA@

1

1

H30
HOLEA@

1

H32
HOLEA@

1

4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2007/12/28 2007/12/28

Compal Secret Data

Deciphered Date

2

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

Screws

LA-4131P

of

1

33 53Monday, February 18, 2008

0.2

5

4

3

2

1

PEG_NRX_GTX_P[0..15]9
PEG_NRX_GTX_N[0..15]9

PEG_NTX_GRX_P[0..15]9
PEG_NTX_GRX_N[0..15]9

D D

PEG_NRX_GTX_P0
PEG_NRX_GTX_N0
PEG_NRX_GTX_P1
PEG_NRX_GTX_N1
PEG_NRX_GTX_P2
PEG_NRX_GTX_N2
PEG_NRX_GTX_P3
PEG_NRX_GTX_N3
PEG_NRX_GTX_P4

C C

PEG_NRX_GTX_N4
PEG_NRX_GTX_P5
PEG_NRX_GTX_N5
PEG_NRX_GTX_P6
PEG_NRX_GTX_N6

PEG_NRX_GTX_N7
PEG_NRX_GTX_P8
PEG_NRX_GTX_N8
PEG_NRX_GTX_P9

PEG_NRX_GTX_P10
PEG_NRX_GTX_N10
PEG_NRX_GTX_P11
PEG_NRX_GTX_N11
PEG_NRX_GTX_P12
PEG_NRX_GTX_N12
PEG_NRX_GTX_P13
PEG_NRX_GTX_N13
PEG_NRX_GTX_P14
PEG_NRX_GTX_N14
PEG_NRX_GTX_P15
PEG_NRX_GTX_N15

B B

C640

A A

18P_0402_50V8J

VGA@

PEG_NRX_GTX_P[0..15]
PEG_NRX_GTX_N[0..15]

PEG_NTX_GRX_P[0..15]
PEG_NTX_GRX_N[0..15]

C255 0.1U_0402_16V7KVGA@

1 2

C261 0.1U_0402_16V7KVGA@

1 2

C262 0.1U_0402_16V7K
C269 0.1U_0402_16V7K

1 2

C253 0.1U_0402_16V7KVGA@
C246 0.1U_0402_16V7KVGA@

1 2

C222 0.1U_0402_16V7KVGA@
C227 0.1U_0402_16V7KVGA@

1 2

C230 0.1U_0402_16V7KVGA@
C241 0.1U_0402_16V7KVGA@

1 2

C220 0.1U_0402_16V7KVGA@
C213 0.1U_0402_16V7KVGA@

1 2

C206 0.1U_0402_16V7KVGA@
C209 0.1U_0402_16V7KVGA@

1 2

C177 0.1U_0402_16V7KVGA@
C192 0.1U_0402_16V7KVGA@

1 2

C195 0.1U_0402_16V7KVGA@
C203 0.1U_0402_16V7KVGA@

1 2

C175 0.1U_0402_16V7KVGA@
C169 0.1U_0402_16V7KVGA@

1 2

C158 0.1U_0402_16V7KVGA@
C168 0.1U_0402_16V7KVGA@

1 2

C160 0.1U_0402_16V7KVGA@
C151 0.1U_0402_16V7KVGA@

1 2

C146 0.1U_0402_16V7KVGA@
C140 0.1U_0402_16V7KVGA@

1 2

C150 0.1U_0402_16V7KVGA@
C145 0.1U_0402_16V7KVGA@

1 2

C138 0.1U_0402_16V7KVGA@
C131 0.1U_0402_16V7KVGA@

1 2

C128 0.1U_0402_16V7KVGA@
C130 0.1U_0402_16V7KVGA@

1 2

+3VS

4
1

27MHZ_16PF_X7S027000BG1H-U

1

2

5

Y3

GND
IN

VGA@

VGA@

1 2

VGA@

1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2

CLK_PCIE_VGA16
CLK_PCIE_VGA#16

PLT_RST#7,17,19,21,22,26,27,28,31

R477 10K_0402_5%VGA@

1 2

R146 10K_0402_5%@

1 2

R133 10K_0402_5%@

1 2

R139 10K_0402_5%@

1 2

R132 10K_0402_5%VGA@

1 2

C289

1 2

C298

1 2

3

OUT

2

GND

XTALIN
XTALOUT

1

C639
18P_0402_50V8J

2

VGA@

PEG_NTX_GRX_P0
PEG_NTX_GRX_N0
PEG_NTX_GRX_P1
PEG_NTX_GRX_N1
PEG_NTX_GRX_P2
PEG_NTX_GRX_N2
PEG_NTX_GRX_P3
PEG_NTX_GRX_N3
PEG_NTX_GRX_P4
PEG_NTX_GRX_N4
PEG_NTX_GRX_P5
PEG_NTX_GRX_N5
PEG_NTX_GRX_P6
PEG_NTX_GRX_N6
PEG_NTX_GRX_P7
PEG_NTX_GRX_N7
PEG_NTX_GRX_P8
PEG_NTX_GRX_N8
PEG_NTX_GRX_P9
PEG_NTX_GRX_N9
PEG_NTX_GRX_P10
PEG_NTX_GRX_N10
PEG_NTX_GRX_P11
PEG_NTX_GRX_N11
PEG_NTX_GRX_P12
PEG_NTX_GRX_N12
PEG_NTX_GRX_P13
PEG_NTX_GRX_N13
PEG_NTX_GRX_P14
PEG_NTX_GRX_N14
PEG_NTX_GRX_P15
PEG_NTX_GRX_N15

PEG_NRX_C_GTX_P0
PEG_NRX_C_GTX_N0
PEG_NRX_C_GTX_P1
PEG_NRX_C_GTX_N1
PEG_NRX_C_GTX_P2
PEG_NRX_C_GTX_N2
PEG_NRX_C_GTX_P3
PEG_NRX_C_GTX_N3
PEG_NRX_C_GTX_P4
PEG_NRX_C_GTX_N4
PEG_NRX_C_GTX_P5
PEG_NRX_C_GTX_N5
PEG_NRX_C_GTX_P6
PEG_NRX_C_GTX_N6
PEG_NRX_C_GTX_P7PEG_NRX_GTX_P7
PEG_NRX_C_GTX_N7
PEG_NRX_C_GTX_P8
PEG_NRX_C_GTX_N8
PEG_NRX_C_GTX_P9
PEG_NRX_C_GTX_N9PEG_NRX_GTX_N9
PEG_NRX_C_GTX_P10
PEG_NRX_C_GTX_N10
PEG_NRX_C_GTX_P11
PEG_NRX_C_GTX_N11
PEG_NRX_C_GTX_P12
PEG_NRX_C_GTX_N12
PEG_NRX_C_GTX_P13
PEG_NRX_C_GTX_N13
PEG_NRX_C_GTX_P14
PEG_NRX_C_GTX_N14
PEG_NRX_C_GTX_P15
PEG_NRX_C_GTX_N15

CLK_PCIE_VGA
CLK_PCIE_VGA#

PLT_RST#

R126 200_0402_5%@

1 2

IFPAB_VPROBE

0.01U_0402_16V7K@

IFPCD_VPROBE

0.01U_0402_16V7K@

If External Spread Spectrum not stuff than stuff resistor.

TP3

R480

1 2

12

R472
10K_0402_5%

@

AK13

AK14
AM14
AM15

AK16

AK17

AM18
AM19

AK19

AK20

AM21
AM22

AK22

AK23

AM24
AM25

AK25

AK26

AM27
AM28

AK15

AH16

AG16

AG17

AH17

AG18

AH18

AK18

AH19

AG20

AH20

AG21

AH21

AK21

AH22

AG23

AH23

AK24

AH25

AH26

AG26

AK27

AH27

AH14

AH15

AM12
AM11

AK12

AK11

VGA@

AL15
AL16

AL17
AL18

AL20
AL21

AL23
AL24

AL26
AL27

AL28
AL29

AJ15

AJ18
AJ19

AJ21
AJ22

AJ24
AJ25

AJ27
AJ28

AJ14

AJ11
AL12
AL13

AM4

H2

AK3

U1
U2

T2

T1

22_0402_5%

U38A

PEX_RX0
PEX_RX0_N
PEX_RX1
PEX_RX1_N
PEX_RX2
PEX_RX2_N
PEX_RX3
PEX_RX3_N
PEX_RX4
PEX_RX4_N
PEX_RX5
PEX_RX5_N
PEX_RX6
PEX_RX6_N
PEX_RX7
PEX_RX7_N
PEX_RX8
PEX_RX8_N
PEX_RX9
PEX_RX9_N
PEX_RX10
PEX_RX10_N
PEX_RX11
PEX_RX11_N
PEX_RX12
PEX_RX12_N
PEX_RX13
PEX_RX13_N
PEX_RX14
PEX_RX14_N
PEX_RX15
PEX_RX15_N

PEX_TX0
PEX_TX0_N
PEX_TX1
PEX_TX1_N
PEX_TX2
PEX_TX2_N
PEX_TX3
PEX_TX3_N
PEX_TX4
PEX_TX4_N
PEX_TX5
PEX_TX5_N
PEX_TX6
PEX_TX6_N
PEX_TX7
PEX_TX7_N
PEX_TX8
PEX_TX8_N
PEX_TX9
PEX_TX9_N
PEX_TX10
PEX_TX10_N
PEX_TX11
PEX_TX11_N
PEX_TX12
PEX_TX12_N
PEX_TX13
PEX_TX13_N
PEX_TX14
PEX_TX14_N
PEX_TX15
PEX_TX15_N

PEX_REFCLK
PEX_REFCLK_N

PEX_RST_N

PEX_TSTCLK_OUT
PEX_TSTCLK_OUT_N

TESTMODE
JTAG_TCK

JTAG_TDI
JTAG_TDO
JTAG_TMS
JTAG_N

IFPAB_VPROBE
IFPCD_VPROBE

XTALIN
XTALOUT

XTALOUTBUFF

XTALSSIN

NB8P-SE-A2 BGA 820P VGA@

12

R471
10K_0402_5%

@

4

Part 1 of 6

OSC_SPREAD
OSC_OUT

MIOA_HSYNC
MIOA_VSYNC

MIOA_CTL3

DVO / GPIO

MIOA_CLKOUT

MIOA_CLKOUT_N

MIOA_VREF

DACsI2C

MIOB_HSYNC
MIOB_VSYNC

MIOB_CTL3

MIOB_CLKIN

MIOB_CLKOUT

MIOB_CLKOUT_N

MIOB_VREF

DACA_HSYNC
DACA_VSYNC

DACA_RED

DACA_BLUE

DACA_GREEN

DACA_IDUMP

DACA_RSET

DACA_VREF
DACC_HSYNC
DACC_VSYNC

DACC_RED

DACC_BLUE
DACC_GREEN

DACC_IDUMP

DACC_RSET

DACC_VREF

DACB_RED

DACB_BLUE

DACB_GREEN

DACB_IDUMP

DACB_RSET
DACB_CSYNC

DACB_VREF

PCI EXPRESS

TEST

CLK

GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8

GPIO9
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14

MIOAD0
MIOAD1
MIOAD2
MIOAD3
MIOAD4
MIOAD5
MIOAD6
MIOAD7
MIOAD8

MIOAD9
MIOAD10
MIOAD11

MIOA_DE

MIOBD0

MIOBD1

MIOBD2

MIOBD3

MIOBD4

MIOBD5

MIOBD6

MIOBD7

MIOBD8

MIOBD9
MIOBD10
MIOBD11

MIOB_DE

I2CA_SCL
I2CA_SDA
I2CB_SCL
I2CB_SDA
I2CC_SCL
I2CC_SDA
I2CH_SCL
I2CH_SDA
ISCS_SCL
ISCS_SDA

K3
H1

NV_INVTPWM

K5

VGA_LVDDEN

G5

G8X_ENBKL

E2
J5
G6
K6

G_THERM#

E1

G_ALERT#

D2
H5
F4
E3
U3
U4

P2
N2
N1
N3
M1
M3
P5
N6
N5
M4
L4
L5

R3
R1
P1
P3

R4
P4

L2
AC3

AC1
AC2
AB2
AB1
AA1
AB3
AA3
AC5
AB5
AB4
AA5

AF3
AE3
AD1
AD3

AE4
AD4
AD5

Y2
AF10

AK10
AH11
AH12
AJ12
AG9
AH9
AH10
AG7
AG5
AF6
AE5
AG6
AG4
AF5

AH4
R6

T6
T5
V7

R194 10K_0402_5%VGA@

R7
U5

R206 10K_0402_5%VGA@

R5
K2

J3
H4
J4
G2
G1
G3
H3
C1
B1

R489 0_0402_5% VGA@

AC_DET

PEX_PLL_TERM
SUB_VENDOR

PEX_CFG0
PEX_CFG1

PEX_CFG2

SLOT_CLOCK_CFG

RAM_CFG0
RAM_CFG1

PCI_DEVID2
PCI_DEVID0
PCI_DEVID1

PCI_IOBAR
RAM_CFG2
RAM_CFG3

PCI_DEVID3
PEX_CFG3

PCI_DEVID4

R154 10K_0402_5%

VGA_HSYNC
VGA_VSYNC
VGA_CRT_R
VGA_CRT_B
VGA_CRT_G

DACA_RSET
DACAVREF

VGA_DDCCLK
VGA_DDCDATA
I2CB_SCL
I2CB_SDA
VGA_CLK_LCD
VGA_DAT_LCD
I2CH_SCL
I2CH_SDA

I2CS_SCL
I2CS_SDA

R193 2.2K_0402_5%

12

R150 124_0603_1%VGA@
C293 0.01U_0402_16V7KVGA@

12
12

R486 0_0402_5% VGA@

R490 0_0402_5% VGA@

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

PAD

T48

VGA_LVDDEN 15,28
G8X_ENBKL 28

For Internal Thermal Sensor

PAD

T49

12

FB_VREFCTL 39,40

PAD

T24

PEX_PLL_TERM 38
SUB_VENDOR 38

PEX_CFG0 38
PEX_CFG1 38

PEX_CFG2 38

SLOT_CLOCK_CFG 38

RAM_CFG0 38
RAM_CFG1 38

PCI_DEVID2 38
PCI_DEVID0 38
PCI_DEVID1 38

@

1 2

RAM_CFG2 38
RAM_CFG3 38

PCI_DEVID3 38
PEX_CFG3 38

PCI_DEVID4 38

VGA@

VGA_HSYNC 15
VGA_VSYNC 15
VGA_CRT_R 15
VGA_CRT_B 15
VGA_CRT_G 15

1 2
1 2

VGA_DDCCLK 15
VGA_DDCDATA 15

VGA_CLK_LCD 15
VGA_DAT_LCD 15

EC_SMB_CK2

12

EC_SMB_DA2

12

2007/12/28 2007/12/28

VGA_THER# 28

<---CRT

<---LVDS
<---HDCP

EC_SMB_CK2 4,28,29
EC_SMB_DA2 4,28,29

Compal Secret Data

Deciphered Date

HDCP

R559

2.2K_0402_5%

@

VGA_CRT_R
VGA_CRT_G
VGA_CRT_B

VGA_CLK_LCD

VGA_DAT_LCD

2

1 2

OSC_OUT OSC_SPREAD

U56

1

NC

2

NC

3

NC

4

GND

AT88SC0808C-SU-2.7_SO8

@

VGA termination, close chip

R134 150_0402_1%VGA@

1 2

R129 150_0402_1%VGA@

1 2

R142 150_0402_1%VGA@

1 2

R482

VGA@

1 2

2.2K_0402_5%
R479

VGA@

1 2

2.2K_0402_5%

External Spread Spectrum

+3VS

C342 0.1U_0402_16V4Z

1 2

VGA@

U40

7

VDD

1

XIN

8

XOUT

2

VSS

ASM3P1819N-SR_SO8

VGA@

I2CB_SCL

R195 2K_0402_5%

I2CB_SDA

R183 2K_0402_5%

I2CS_SCL

R488 2K_0402_5%

I2CS_SDA

R500 2K_0402_5%

Title

Size Document Number Rev

Custom

Date: Sheet

8

VCC

7

SCL
SDA

NC

6
5

I2CH_SDA

I2CH_SCL

R558

10K_0402_5%

@

12

PCI_IOBAR

REF

MODOUT

NC

PD#

VGA@

1 2

VGA@

1 2

VGA@

1 2

VGA@

1 2

+3VS

5
4
3
6

BAR2_SIZE

VGA@

1 2

R178 22_0402_5%

+3VS

Compal Electronics, Inc.

NB8P-SE_Main

LA-4131P

+3VS+3VS

0

1

0

1

1

C690

0.1U_0402_16V4Z

@

NB8P

Disable

Enable(Default)

NB8P

32Mb(Default)

16Mb

of

34 53Monday, February 18, 2008

0.2

5

4

3

2

1

FBAD[0..63]

D D

FBAD0

N27

FBAD1

M27

FBAD2

N28

FBAD3

L29

FBAD4

K27

FBAD5

K28

FBAD6

J29

FBAD7

J28

FBAD8

P30

FBAD9

N31

FBAD10

C C

B B

FBAD11
FBAD12
FBAD13
FBAD14
FBAD15
FBAD16
FBAD17
FBAD18
FBAD19
FBAD20
FBAD21
FBAD22
FBAD23
FBAD24
FBAD25
FBAD26
FBAD27
FBAD28
FBAD29
FBAD30
FBAD31
FBAD32
FBAD33
FBAD34
FBAD35
FBAD36
FBAD37
FBAD38
FBAD39
FBAD40
FBAD41
FBAD42
FBAD43
FBAD44
FBAD45
FBAD46
FBAD47
FBAD48
FBAD49
FBAD50
FBAD51
FBAD52
FBAD53
FBAD54
FBAD55
FBAD56
FBAD57
FBAD58
FBAD59
FBAD60
FBAD61
FBAD62
FBAD63

N30
N32

H30
H31
H32
D30
H28

H29

AD29
AE29
AD28
AC28
AB29
AA30

AB30
AM30
AF30

AJ31
AJ30

AJ32
AK29
AM31

AL30
AE32
AE30
AE31
AD30
AC31
AC32
AB32
AB31
AG27
AF28
AH28
AG28
AG29
AD27
AF27
AE28

L31
L30
J30
L32

K30
F30
E31
E30

E29
J27
F27
E27
E28
F28

Y28

FBAA[0..11]

FBBA[2..5]

RDQSA[0..7]

WDQSA[0..7]

DQMA#[0..7]

FBA_BA[0..2]

U38B

FBAD0
FBAD1
FBAD2
FBAD3
FBAD4
FBAD5
FBAD6
FBAD7
FBAD8
FBAD9
FBAD10
FBAD11
FBAD12
FBAD13
FBAD14
FBAD15
FBAD16
FBAD17
FBAD18
FBAD19
FBAD20
FBAD21
FBAD22
FBAD23
FBAD24
FBAD25
FBAD26
FBAD27
FBAD28
FBAD29
FBAD30
FBAD31
FBAD32
FBAD33
FBAD34
FBAD35
FBAD36
FBAD37
FBAD38
FBAD39
FBAD40
FBAD41
FBAD42
FBAD43
FBAD44
FBAD45
FBAD46
FBAD47
FBAD48
FBAD49
FBAD50
FBAD51
FBAD52
FBAD53
FBAD54
FBAD55
FBAD56
FBAD57
FBAD58
FBAD59
FBAD60
FBAD61
FBAD62
FBAD63

NB8P-SE-A2 BGA 820P VGA@

Part 2 of 6

MEMORY INTERFACE A

FBAD[0..63] 39

FBAA[0..11] 39

FBBA[2..5] 39

RDQSA[0..7] 39

WDQSA[0..7] 39

DQMA#[0..7] 39

FBA_BA[0..2] 39

FBA_CMD0
FBA_CMD1
FBA_CMD2
FBA_CMD3
FBA_CMD4
FBA_CMD5
FBA_CMD6
FBA_CMD7
FBA_CMD8

FBA_CMD9
FBA_CMD10
FBA_CMD11
FBA_CMD12
FBA_CMD13
FBA_CMD14
FBA_CMD15
FBA_CMD16
FBA_CMD17
FBA_CMD18
FBA_CMD19
FBA_CMD20
FBA_CMD21
FBA_CMD22
FBA_CMD23
FBA_CMD24
FBA_CMD25
FBA_CMD26
FBA_CMD27
FBA_CMD28

FBADQM0
FBADQM1
FBADQM2
FBADQM3
FBADQM4
FBADQM5
FBADQM6
FBADQM7

FBADQS_RN0
FBADQS_RN1
FBADQS_RN2
FBADQS_RN3
FBADQS_RN4
FBADQS_RN5
FBADQS_RN6
FBADQS_RN7

FBADQS_WP0
FBADQS_WP1
FBADQS_WP2
FBADQS_WP3
FBADQS_WP4
FBADQS_WP5
FBADQS_WP6
FBADQS_WP7

FB_VREF

FBA_CLK0

FBA_CLK0_N

FBA_CLK1

FBA_CLK1_N

FBA_DEBUG

P32
U27
P31
U30
Y31
W32
W31
T32
V27
T28
T31
U32
W29
W30
T27
V28
V30
U31
R27
V29
T30
W28
R29
R30
P29
U28
Y32
Y30
V32

M29
M30
G30
F29
AA29
AK30
AC30
AG30

M28
K32
G31
G27
AA28
AL31
AF31
AH29

L28
K31
G32
G28
AB28
AL32
AF32
AH30

E32
P28

R28
Y27
AA27
AC27

FBAA4
FBAA5

FBA_BA1
FBBA2
FBBA4
FBBA3

FBAA11

FBA_BA0
FBBA5

FBAA7
FBAA10

FBAA0
FBAA9
FBAA6
FBAA2
FBAA8
FBAA3
FBAA1

DQMA#0
DQMA#1
DQMA#2
DQMA#3
DQMA#4
DQMA#5
DQMA#6
DQMA#7

RDQSA0
RDQSA1
RDQSA2
RDQSA3
RDQSA4
RDQSA5
RDQSA6
RDQSA7

WDQSA0
WDQSA1
WDQSA2
WDQSA3
WDQSA4
WDQSA5
WDQSA6
WDQSA7

PAD

T5

FBARAS# 39

FBACS0# 39
FBACAS# 39

FBAWE# 39

12

R90
10K_0402_5%

VGA@

CLKA0 39
CLKA0# 39
CLKA1 39
CLKA1# 39

FBA_CKE 39

12

R89
10K_0402_5%

VGA@

FBA_RST# 39

FBCD0
FBCD1
FBCD2
FBCD3
FBCD4
FBCD5
FBCD6
FBCD7
FBCD8
FBCD9
FBCD10
FBCD11
FBCD12
FBCD13
FBCD14
FBCD15
FBCD16
FBCD17
FBCD18
FBCD19
FBCD20
FBCD21
FBCD22
FBCD23
FBCD24
FBCD25
FBCD26
FBCD27
FBCD28
FBCD29
FBCD30
FBCD31
FBCD32
FBCD33
FBCD34
FBCD35
FBCD36
FBCD37
FBCD38
FBCD39
FBCD40
FBCD41
FBCD42
FBCD43
FBCD44
FBCD45
FBCD46
FBCD47
FBCD48
FBCD49
FBCD50
FBCD51
FBCD52
FBCD53
FBCD54
FBCD55
FBCD56
FBCD57
FBCD58
FBCD59
FBCD60
FBCD61
FBCD62
FBCD63

U38C

B7

FBCD0

A7

FBCD1

C7

FBCD2

A2

FBCD3

B2

FBCD4

C4

FBCD5

A5

FBCD6

B5

FBCD7

F9

FBCD8

F10

FBCD9

D12

FBCD10

D9

FBCD11

E12

FBCD12

D11

FBCD13

E8

FBCD14

D8

FBCD15

E7

FBCD16

F7

FBCD17

D6

FBCD18

D5

FBCD19

D3

FBCD20

E4

FBCD21

C3

FBCD22

B4

FBCD23

C10

FBCD24

B10

FBCD25

C8

FBCD26

A10

FBCD27

C11

FBCD28

C12

FBCD29

A11

FBCD30

B11

FBCD31

B28

FBCD32

C27

FBCD33

C26

FBCD34

B26

FBCD35

C30

FBCD36

B31

FBCD37

C29

FBCD38

A31

FBCD39

D28

FBCD40

D27

FBCD41

F26

FBCD42

D24

FBCD43

E23

FBCD44

E26

FBCD45

E24

FBCD46

F23

FBCD47

B23

FBCD48

A23

FBCD49

C25

FBCD50

C23

FBCD51

A22

FBCD52

C22

FBCD53

C21

FBCD54

B22

FBCD55

E22

FBCD56

D22

FBCD57

D21

FBCD58

E21

FBCD59

E18

FBCD60

D19

FBCD61

D18

FBCD62

E19

FBCD63

NB8P-SE-A2 BGA 820P VGA@

FBCD[0..63]

FBCA[0..11]

FBDA[2..5]

RDQSC[0..7]

WDQSC[0..7]

DQMC#[0..7]

FBC_BA[0..2]

FBC_CMD0

Part 3 of 6

FBC_CMD1
FBC_CMD2
FBC_CMD3
FBC_CMD4
FBC_CMD5
FBC_CMD6
FBC_CMD7
FBC_CMD8

FBC_CMD9
FBC_CMD10
FBC_CMD11
FBC_CMD12
FBC_CMD13
FBC_CMD14
FBC_CMD15
FBC_CMD16
FBC_CMD17
FBC_CMD18
FBC_CMD19
FBC_CMD20
FBC_CMD21
FBC_CMD22
FBC_CMD23
FBC_CMD24
FBC_CMD25
FBC_CMD26
FBC_CMD27
FBC_CMD28

FBCDQM0
FBCDQM1
FBCDQM2
FBCDQM3
FBCDQM4
FBCDQM5
FBCDQM6
FBCDQM7

FBCDQS_RN0
FBCDQS_RN1
FBCDQS_RN2
FBCDQS_RN3
FBCDQS_RN4
FBCDQS_RN5
FBCDQS_RN6
FBCDQS_RN7

FBCDQS_WP0

MEMORY INTERFACE B

FBCDQS_WP1
FBCDQS_WP2
FBCDQS_WP3
FBCDQS_WP4
FBCDQS_WP5
FBCDQS_WP6
FBCDQS_WP7

FBC_CLK0

FBC_CLK0_N

FBC_CLK1

FBC_CLK1_N

FBC_DEBUG

FBCD[0..63] 40

FBCA[0..11] 40

FBDA[2..5] 40

RDQSC[0..7] 40

WDQSC[0..7] 40

DQMC#[0..7] 40

FBC_BA[0..2] 40

C13
A16
A13
B17
B20
A19
B19
B14
E16
A14
C15
B16
F17
C19
D15
C17
A17
C16
D14
F16
C14
C18
E14
B13
E15
F15
A20
C20
A15

A4
E11
F5
C9
C28
F24
C24
E20

C6
E9
E6
A8
B29
E25
A25
F21

C5
E10
E5
B8
A29
D25
B25
F20

E13
F13
F18
E17
F12

FBCA4
FBCA5

FBC_BA1
FBDA2
FBDA4
FBDA3
FBC_BA2FBA_BA2

FBCA11

FBC_BA0
FBDA5

FBCA7
FBCA10

FBCA0
FBCA9
FBCA6
FBCA2
FBCA8
FBCA3
FBCA1

DQMC#0
DQMC#1
DQMC#2
DQMC#3
DQMC#4
DQMC#5
DQMC#6
DQMC#7

RDQSC0
RDQSC1
RDQSC2
RDQSC3
RDQSC4
RDQSC5
RDQSC6
RDQSC7

WDQSC0
WDQSC1
WDQSC2
WDQSC3
WDQSC4
WDQSC5
WDQSC6
WDQSC7

PAD

T16

FBCRAS# 40

FBCCS0# 40
FBCCAS# 40

FBCWE# 40

12

R266
10K_0402_5%

VGA@

CLKC0 40
CLKC0# 40
CLKC1 40
CLKC1# 40

FBC_CKE 40

12

R267
10K_0402_5%

VGA@

FBC_RST# 40

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2007/12/28 2007/12/28

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

Compal Electronics, Inc.

NB8P-SE_Memory Interface

LA-4131P

1

0.2

of

35 53Monday, February 18, 2008

5

4

3

2

1

U38D

AK9

AM6
AM5
AM7

AM2
AM3

AG1
AH1
AG3
AH2

AH3

AJ9
AH6
AJ6
AH8
AH7
AJ8
AK8
AJ5
AH5
AK4
AL4

AL7
AK6
AK5
AK7
AL8

AL5

AE2
AE1
AF1
AF2

AK1
AJ1
AL2
AL1
AJ2
AJ3

IFPA_TXC
IFPA_TXC_N
IFPA_TXD0
IFPA_TXD0_N
IFPA_TXD1
IFPA_TXD1_N
IFPA_TXD2
IFPA_TXD2_N
IFPA_TXD3
IFPA_TXD3_N
IFPB_TXC
IFPB_TXC_N
IFPB_TXD4
IFPB_TXD4_N
IFPB_TXD5
IFPB_TXD5_N
IFPB_TXD6
IFPB_TXD6_N
IFPB_TXD7
IFPB_TXD7_N

IFPAB_RSET
IFPC_TXC

IFPC_TXC_N
IFPC_TXD0
IFPC_TXD0_N
IFPC_TXD1
IFPC_TXD1_N
IFPC_TXD2
IFPC_TXD2_N
IFPD_TXC
IFPD_TXC_N
IFPD_TXD4
IFPD_TXD4_N
IFPD_TXD5
IFPD_TXD5_N
IFPD_TXD6
IFPD_TXD6_N

IFPCD_RSET

Part 4 of 6

NC

LVDS/TMDS

GENERAL

SERIAL

NB8P-SE-A2 BGA 820P VGA@

NC_0
NC_1
NC_2
NC_3
NC_4
NC_5
NC_6
NC_7
NC_8

NC_9
NC_10
NC_11
NC_12
NC_13
NC_14
NC_15
NC_16
NC_17
NC_18
NC_19
NC_20
NC_21
NC_22
NC_23
NC_24
NC_25
NC_26
NC_27
NC_28
NC_29
NC_30
NC_31
NC_32

SPDIF

BUFRST_N

STEREO

SWAPRDY_A

THERMDN
THERMDP

ROM_SCLK

ROM_SI

ROM_SO

ROMCS_N

B32
D1
D31
F1
D32
G9
G10
U6
V1
V3
V4
V5
V6
W1
W3
W4
W5
Y5
Y6
G8
AC26
AG12
AH13
AM8
AM9
AH32
M5
A26
AD26
AH31
AE26
F6
A28

J6
F3

T3

R208 10K_0402_5%VGA@

M6

1 2
J1
K1

AA7
W2
AA6
AA4

+3VS

1 2

1 2

VGA_LVDSAC+
VGA_LVDSAC­VGA_LVDSA0+
VGA_LVDSA0­VGA_LVDSA1+
VGA_LVDSA1­VGA_LVDSA2+
VGA_LVDSA2-

VGA_LVDSBC+
VGA_LVDSBC­VGA_LVDSB0+
VGA_LVDSB0­VGA_LVDSB1+
VGA_LVDSB1­VGA_LVDSB2+
VGA_LVDSB2-

VGA@

VGA@

D D

C C

B B

VGA_LVDSAC+15

VGA_LVDSAC-15
VGA_LVDSA0+15

VGA_LVDSA0-15

VGA_LVDSA1+15

VGA_LVDSA1-15

VGA_LVDSA2+15

VGA_LVDSA2-15

VGA_LVDSBC+15

VGA_LVDSBC-15
VGA_LVDSB0+15

VGA_LVDSB0-15

VGA_LVDSB1+15

VGA_LVDSB1-15

VGA_LVDSB2+15

VGA_LVDSB2-15

R152 1K_0402_5%

R151 1K_0402_5%

U38F

B3

GND_0

B6

GND_1

B9

GND_2

B12

GND_3

B15

GND_4

B18

GND_5

B21

GND_6

B24

GND_7

B27

GND_8

B30

GND_9

C2

GND_10

C31

GND_11

D4

GND_12

D7

GND_13

D10

GND_14

D13

GND_15

D17

GND_16

D20

GND_17

D23

GND_18

D26

GND_19

D29

GND_20

F2

GND_21

F8

GND_22

F11

GND_23

F14

GND_24

F19

GND_25

F22

GND_26

F25

GND_27

F31

GND_28

G4

GND_29

G7

GND_30

G26

GND_31

G29

GND_32

H27

GND_33

H6

GND_34

J2

GND_35

J16

GND_36

J17

GND_37

J31

GND_38

K10

GND_39

K23

GND_40

K29

GND_41

K4

GND_42

L6

GND_43

L27

GND_44

M2

GND_45

M12

GND_46

AM10

GND_47

M31

GND_48

N4

GND_49

N15

GND_50

N18

GND_51

N29

GND_52

P6

GND_53

P15

GND_54

P18

GND_55

P27

GND_56

R2

GND_57

R13

GND_58

R14

GND_59

R15

GND_60

R18

GND_61

R19

GND_62

R20

GND_63

R31

GND_64

T4

GND_65

T16

GND_66

T17

GND_67

T24

GND_68

T29

GND_69

U8

GND_70

U16

GND_71

U17

GND_72

U24

GND_73

U29

GND_74

V2

GND_75

V13

GND_76

V14

GND_77

V15

GND_78

V18

GND_79

V19

GND_80

V20

GND_81

V31

GND_82

W6

GND_83

NB8P-SE-A2 BGA 820P VGA@

Part 6 of 6

GND

MIOACAL_PU_GND
MIOBCAL_PU_GND

FBCAL_TERM_GND

GND_85
GND_86
GND_87
GND_88
GND_89
GND_90
GND_91
GND_92
GND_93
GND_94
GND_95
GND_96
GND_97
GND_98

GND_99
GND_100
GND_101
GND_102
GND_103
GND_104
GND_105
GND_106
GND_107
GND_108
GND_109
GND_110
GND_111
GND_112
GND_113
GND_114
GND_115
GND_116
GND_117
GND_118
GND_119
GND_120
GND_121
GND_122
GND_123
GND_124
GND_125
GND_126
GND_127
GND_128
GND_129
GND_130
GND_131
GND_132
GND_133
GND_134
GND_135
GND_136
GND_137
GND_138
GND_139
GND_140
GND_141
GND_142
GND_143
GND_144
GND_145
GND_146
GND_147
GND_148
GND_149
GND_150
GND_151
GND_152
GND_153
GND_154

GND_SENSE

IFPAB_PLLGND

IFPCD_PLLGND

PEX_PLLGND

PLLGND

FB_PLLGND

FBCAL_PU_GND

W18
Y4
Y15
Y18
Y29
AA2
AA12
AA21
AA31
AB6
AB27
AC4
AC10
AC23
AC29
AD2
AD16
AD17
AD31
AE6
AE17
AE27
AF4
AF7
AF11
AF26
AF29
AG2
AG8
AG10
AG11
AG13
AG14
AG15
AG19
AG22
AG31
AH24
AJ4
AJ7
AJ10
AJ13
AJ16
AJ17
AJ20
AJ23
AJ26
AJ29
AK2
AL3
AL6
AL9
AL10
AK28
AK31
AL11
AL14
AL19
AL22
AL25
AM13
AM16
AM17
AM20
AM23
AM26
AM29
D16
W27
W15

M21
AD9
AB10

L3
Y3

AE16
U10
G24
H26

J26

R123 24.9_0402_1%VGA@
R113 40.2_0402_1%VGA@

1 2
1 2

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2007/12/28 2007/12/28

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

Compal Electronics, Inc.

NB8P-SE_LVDS / TMDS / GND

LA-4131P

1

of

36 53Monday, February 18, 2008

0.2

5

4

3

2

+1.2VS

1

+1.2VS

+3VS

VGA@

10K_0402_5%

VGA@

10K_0402_5%

VGA@

10K_0402_5%

VGA@

10K_0402_5%

VGA@

10K_0402_5%

C274 0.1U_0402_16V4ZVGA@

1 2

C268 0.1U_0402_16V4ZVGA@

1 2

+VGA_PEX_PLL_VDD = 85mA

+VGA_PEX_PLL_VDD

L28

1 2

INDUC_ 10NH +-5% LL1005-FHL10NJ

C547 4.7U_0603_6.3V X5RVGA@

1 2

C553 0.01U_0402_16V7KVGA@

1 2

C556 0.01U_0402_16V7KVGA@

1 2

C548 0.1U_0402_16V4ZVGA@

1 2

C550 0.1U_0402_16V4ZVGA@

1 2

+IFPA_IOVDD = 90mA

+IFPA_IOVDD

1 2

C338 4.7U_0603_6.3V X5RVGA@

1 2

C334 4700P_0402_25V7KVGA@

1 2

C335 4700P_0402_25V7KVGA@

1 2

C330 470P_0402_50V7KVGA@

1 2

C331 470P_0402_50V7KVGA@

1 2

+IFPAB_PLLVDD = 75mA

+IFPAB_PLLVDD

C340 4.7U_0603_6.3V X5RVGA@

1 2

C333 4700P_0402_25V7KVGA@

1 2

C337 470P_0402_50V7KVGA@

1 2

+DACA_VDD = 130mA

+DACA_VDD

C339 4.7U_0603_6.3V X5RVGA@

1 2

C332 4700P_0402_25V7KVGA@

1 2

C336 470P_0402_50V7KVGA@

1 2

VGA@

L15

VGA@

MBK1608121YZF_0603

L17

VGA@

1 2

MBK1608121YZF_0603

4.7U_0603_6.3V6M

L16

VGA@

1 2

MBK1608121YZF_0603

C564

+1.2VS

+1.8VS

+1.8VS

+3VS

1

2

VGA@

C271 4.7U_0603_6.3V X5RVGA@

1 2

C257 1U_0402_6.3V4KVGA@

+VGA_CORE

C311 1U_0402_6.3V4K

1 2

D D

C C

+3VS

+1.2VS

L34

VGA@

1 2

MBK1608121YZF_0603

B B

+1.2VS

L33

VGA@

1 2

MBK1608121YZF_0603

1

C291

4.7U_0603_6.3V X5R

2

VGA@

+1.2VS

L12

1 2

MBK1608121YZF_0603

VGA@

+VGA_VIDPLL = 35mA

C674 4.7U_0603_6.3V X5RVGA@

1 2

C670 0.1U_0402_16V4ZVGA@

1 2

C665 4700P_0402_25V7KVGA@

1 2

+VGA_PLLVDD = 35mA

C673 4.7U_0603_6.3V X5RVGA@

1 2

C669 0.1U_0402_16V4ZVGA@

1 2

C664 4700P_0402_25V7KVGA@

1 2

+VGA_HPLL = 30mA

C265 4.7U_0603_6.3V X5RVGA@

1 2

C272 0.1U_0402_16V4ZVGA@

1 2

C277 0.01U_0402_16V7KVGA@

1 2

VGA@

C270 0.47U_0402_6.3V6K

1 2

VGA@

C316 0.47U_0402_6.3V6K

1 2

VGA@

C310 0.47U_0402_6.3V6K

1 2

VGA@

C319 0.47U_0402_6.3V6K

1 2

VGA@

C290 0.47U_0402_6.3V6K

1 2

VGA@

C308 0.47U_0402_6.3V6K

1 2

VGA@

C318 0.47U_0402_6.3V6K

1 2

VGA@

C278 0.47U_0402_6.3V6K

1 2

VGA@

C300 0.47U_0402_6.3V6K

1 2

VGA@

C281 0.47U_0402_6.3V6K

1 2

VGA@

C329 1U_0402_6.3V4K

1 2

VGA@

C305 0.47U_0402_6.3V6K

1 2

VGA@

C320 0.47U_0402_6.3V6K

1 2

VGA@

C254 0.1U_0402_16V4Z

1 2

VGA@

C306 0.1U_0402_16V4Z

1 2

VGA@

+VGA_VIDPLL

+VGA_PLLVDD

+VGA_HPLL

+1.8VS

NVVDD = 18430 mA

C286 1U_0402_6.3V4K

1 2

VGA@

C299 1U_0402_6.3V4K

1 2

VGA@

C275 0.1U_0402_16V4Z

1 2

VGA@

C295 0.1U_0402_16V4Z

1 2

VGA@

C285 0.1U_0402_16V4Z

1 2

VGA@

C304 0.1U_0402_16V4Z

1 2

VGA@

C307 0.1U_0402_16V4Z

1 2

VGA@

C276 0.1U_0402_16V4Z

1 2

VGA@

C314 0.1U_0402_16V4Z

1 2

VGA@

C292 0.1U_0402_16V4Z

1 2

VGA@

C303 0.1U_0402_16V4Z

1 2

VGA@

C283 0.1U_0402_16V4Z

1 2

VGA@

VDD33 = 50mA

C322

1 2

0.022U_0402_16V7K~NVGA@

C296

1 2

0.022U_0402_16V7K~NVGA@

C323

1 2

0.022U_0402_16V7K~NVGA@

C256

1 2

0.022U_0402_16V7K~NVGA@

VID_PLLVDD = 35mA

+VGA_VIDPLL

+VGA_PLLVDD

PLLVDD = 35mA
FBA_PLLVDD = 15 mA
H_PLLVDD = 15 mA

+VGA_HPLL

1 2

45.3_0402_1%~DVGA@

+1.8VS

+FBCAL_PD_VDDQ

R105

VDD_SENSE

10mil

1 2

R144
100_0402_1%

VGA@

U38E

K16

VDD_0
VDD_1
VDD_2
VDD_3
VDD_4
VDD_5
VDD_6
VDD_7
VDD_8
VDD_9
VDD_10
VDD_11
VDD_12
VDD_13
VDD_14
VDD_15
VDD_16
VDD_17
VDD_18
VDD_19
VDD_20
VDD_21
VDD_22
VDD_23
VDD_24
VDD_25
VDD_26
VDD_27
VDD_28
VDD_29
VDD_30
VDD_31
VDD_32
VDD_33
VDD_34
VDD_35
VDD_36

VDD_LP_0
VDD_LP_1
VDD_LP_2
VDD_LP_3
VDD_LP_4
VDD_LP_5

VDD33_0
VDD33_1
VDD33_2
VDD33_3
VDD33_4
VDD33_5
VDD33_6
VDD33_7
VDD33_8
VDD33_9
VDD33_10
VDD33_11
VDD33_12

VID_PLLVDD
PLLVDD

FB_PLLAVDD
H_PLLVDD
FBCAL_PD_VDDQ
FBVTT_0

FBVTT_1
FBVTT_2
FBVTT_3
FBVTT_4
FBVTT_5
FBVTT_6
FBVTT_7
FBVTT_8
FBVTT_9
FBVTT_10
FBVTT_11
FBVTT_12
FBVTT_13
FBVTT_14
FBVTT_15
FBVTT_16
FBVTT_17

VDD_SENSE

Part 5 of 6

POWER

MIOACAL_PD_VDDQ
MIOBCAL_PD_VDDQ

K17
N13
N14
N16
N17
N19
U18

P13

P14

P16

P17

P19
R16
R17

T13

T14

T15

T18

T19
U13
U14
U15
U19

V16

V17
W13
W14
W16
W17
W19

Y13

Y14

Y16

Y17

Y19

Y20

P20

T20

T23
U20
U23
W20

H7

J7
K7
L7
L8

L10
M10

AC11
AC12
AC24
AD24

AE11
AE12

T10

T9

G25
G23

K26
H16

H17

J9
J10
J23
J24

K9
K11
K12
K21
K22
K24
L23

M23

T25

U25
AA23
AB23

N20

NB8P-SE-A2 BGA 820P VGA@

PEX_IOVDD_0
PEX_IOVDD_1
PEX_IOVDD_2
PEX_IOVDD_3
PEX_IOVDD_4
PEX_IOVDD_5

PEX_IOVDDQ_0
PEX_IOVDDQ_1
PEX_IOVDDQ_2
PEX_IOVDDQ_3
PEX_IOVDDQ_4
PEX_IOVDDQ_5
PEX_IOVDDQ_6
PEX_IOVDDQ_7
PEX_IOVDDQ_8
PEX_IOVDDQ_9

PEX_IOVDDQ_10

PEX_PLLAVDD

PEX_PLLDVDD
MIOA_VDDQ_0

MIOA_VDDQ_1
MIOA_VDDQ_2
MIOA_VDDQ_3
MIOA_VDDQ_4
MIOB_VDDQ_0
MIOB_VDDQ_1
MIOB_VDDQ_2
MIOB_VDDQ_3
MIOB_VDDQ_4

IFPA_IOVDD

IFPB_IOVDD
IFPC_IOVDD
IFPD_IOVDD

IFPAB_PLLVDD
IFPCD_PLLVDD

DACA_VDD
DACB_VDD

DACC_VDD

FBVDD_0
FBVDD_1
FBVDD_2
FBVDD_3
FBVDD_4
FBVDD_5
FBVDD_6
FBVDD_7
FBVDD_8

FBVDD_9
FBVDD_10
FBVDD_11
FBVDD_12
FBVDD_13
FBVDD_14
FBVDD_15
FBVDD_16
FBVDD_17

FBVDDQ_0
FBVDDQ_1
FBVDDQ_2
FBVDDQ_3
FBVDDQ_4
FBVDDQ_5
FBVDDQ_6
FBVDDQ_7
FBVDDQ_8

FBVDDQ_9
FBVDDQ_10
FBVDDQ_11
FBVDDQ_12
FBVDDQ_13
FBVDDQ_14
FBVDDQ_15
FBVDDQ_16
FBVDDQ_17
FBVDDQ_18
FBVDDQ_19
FBVDDQ_20
FBVDDQ_21
FBVDDQ_22
FBVDDQ_23

AD23
AF23
AF24
AF25
AG24
AG25

AC16
AC17
AC21
AC22
AE18
AE21
AE22
AF12
AF18
AF21
AF22

AF15
AE15

M7
M8
R8
T8
U9
AA8
AB7
AB8
AC6
AC7
L1
Y1

AF9
AF8
AD6
AE7

AC9
AA10

AD10
V8
AD7

A3
A6
A9
A12
AG32
A18
A21
A24
A27
A30
C32
F32
J32
M32
R32
AK32
AA32
AD32

G11
G12
G15
G18
G21
G22
H11
H12
H15
H18
H21
L25
L26
M25
M26
R25
R26
V25
V26
AA25
AA26
AB25
AB26
H22

75mA
10mA

45mA
45mA
50mA
50mA

75mA
75mA

130mA
130mA
130mA

1 2

C247 1U_0402_6.3V4KVGA@

1 2

PEX_IOVDD/Q = 1500mA

C315 4.7U_0603_6.3V X5RVGA@

1 2

C287 1U_0402_6.3V4KVGA@

1 2

C266 1U_0402_6.3V4KVGA@

1 2

C258 0.1U_0402_16V4ZVGA@

1 2

C245 0.1U_0402_16V4ZVGA@

1 2

+VGA_PEX_PLL_VDD

MIOA_VDDQ = 10mA

C301 0.1U_0402_16V4ZVGA@

1 2

MIOB_VDDQ = 10mA

+IFPA_IOVDD

+IFPAB_PLLVDD

+DACA_VDD
+DACB_VDD

+DACC_VDD

+1.8VS

1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2

1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2

+

1 2

FBVDD/Q = 5420mA

C644 4700P_0402_25V7KVGA@
C637 4700P_0402_25V7KVGA@
C646 0.022U_0402_16V7K~NVGA@
C580 0.022U_0402_16V7K~NVGA@
C584 0.1U_0402_16V4ZVGA@
C662 0.1U_0402_16V4ZVGA@
C610 0.1U_0402_16V4ZVGA@
C672 4.7U_0603_6.3V X5RVGA@

C302 4700P_0402_25V7KVGA@
C284 4700P_0402_25V7KVGA@
C565 4700P_0402_25V7KVGA@
C616 0.022U_0402_16V7K~NVGA@
C617 0.022U_0402_16V7K~NVGA@
C328 0.022U_0402_16V7K~NVGA@
C663 0.1U_0402_16V4ZVGA@
C263 0.1U_0402_16V4ZVGA@
C264 0.1U_0402_16V4ZVGA@
C613 0.1U_0402_16V4ZVGA@
C282 4.7U_0603_6.3V X5RVGA@

C297 220U_D2_4VY_R15MVGA@

R196
R190

R207

R197
R184

1 2
1 2

1 2

1 2
1 2

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2007/12/28 2007/12/28

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

2

Date: Sheet

Compal Electronics, Inc.

NB8P-SE_Power

LA-4131P

1

37 53Monday, February 18, 2008

0.2

of

5

4

+3VS

3

2

1

D D

SUB_VENDOR34
PCI_DEVID434
PCI_DEVID334
PCI_DEVID234
PCI_DEVID134
PCI_DEVID034
PEX_CFG334
PEX_CFG234
PEX_CFG134
PEX_CFG034
PEX_PLL_TERM34
SLOT_CLOCK_CFG34

C C

Description

Setting

12

12

R475
2K_0402_5%

VGA@

0: BIOS not present
1: BIOS present

0: BIOS not present

R161
2K_0402_5%

@

SUB_VENDOR SLOT_CLK_CFGStraps

12

12

R181
2K_0402_5%

@

PCI_DEVID [4:0]

NB8P-GS: 0x0407
NB8P-GT: 0x0408
NB8P-SE: 0x0425

NB8P-SE: 0x0425 (00101)

R169
2K_0402_5%

VGA@

12

12

R470
2K_0402_5%

@

PEX_CFG[3:0] PEX_PLL_TERM

0001: 0X1 (0001)

Internal Pull downInternal Pull down

R162
2K_0402_5%

VGA@

0X1

12

R155
2K_0402_5%

@

12

0: Enable
1: Disable

1: Disable

R481
2K_0402_5%

@

12

12

R182
2K_0402_5%

@

0: GPU&MCH do not share a common ref. CLK.
1: GPU&MCH share a common ref. CLK.

1: GPU & MCH share a common ref. CLK.

R205
2K_0402_5%

VGA@

12

R474
2K_0402_5%

VGA@

12

R478
2K_0402_5%

VGA@

12

R473
2K_0402_5%

@

RAM_CFG[3:0]

RAM_CFG3 RAM_CFG[1:0]

0 = Single Rank
1 = Dual Rank

R163
2K_0402_5%

VGA@

R164
2K_0402_5%

@

+3VS

12

R177
2K_0402_5%

@

12

R170
2K_0402_5%

@

B B

RAM_CFG334
RAM_CFG234
RAM_CFG134
RAM_CFG034

A A

ZZZ

12

R192
2K_0402_5%

@

12

R180
2K_0402_5%

VGA@

12

R191
2K_0402_5%

@

12

R179
2K_0402_5%

VGA@

12

12

Place together at the same side

RAM_CFG2

RAM Size Vendor
0=16Mx32
1= 8Mx32

0
0
0

0
0
0
0
1
1
1
1
1
1
1
1

0
0
0

1
1
1
1
0
0
0
0
1
1
1
1

0
0
1

0
0
1
1
0
0
1
1
0
0
1
1

10 = Hynix
11 = Samsung

0
1
0

1001

0
1
0
1
0
1
0
1
0
1
0
1

Description

NB8P-GS

Hynix ( 16M*32 4pcs = 256MB )

Samsung ( 16M*32 4pcs = 256MB )

VRAM

5

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2007/12/28 2007/12/28

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

Compal Electronics, Inc.

NB8P-SE_Straps

LA-4131P

1

0.2

of

38 53Monday, February 18, 2008

5

+1.8VS

12

R408

1.05K_0402_1%

VGA@

12

R407

+1.8VS

12

12

2.49K_0402_1%

VGA@

R413

1.05K_0402_1%

VGA@

R412

2.49K_0402_1%

VGA@

D D

C C

B B

CLKA0

CLKA0#

+VREFA0

1

C546

0.01U_0402_16V7K

VGA@

2

+VREFA1

1

C587

0.01U_0402_16V7K

VGA@

2

12

R86
243_0402_1%

VGA@

FBARAS#35
FBACAS#35
FBAWE#35
FBACS0#35

FBA_CKE35
CLKA035
CLKA0#35

1 2

R414 243_0402_1%

VGA@

FBA_RST#35

+1.8VS

FBAA0
FBAA1
FBAA2
FBAA3
FBAA4

FBAA6
FBAA7
FBAA8
FBAA9
FBAA10
FBAA11
FBA_BA0
FBA_BA1

DQMA#0
DQMA#2
DQMA#3
DQMA#1

WDQSA0
WDQSA2
WDQSA3
WDQSA1

+VREFA0
+VREFA1

FBARAS#
FBACAS#
FBAWE#
FBACS0#

FBA_CKE
CLKA0
CLKA0#

RDQSA0
RDQSA2
RDQSA3
RDQSA1

FBA_RST#
FBA_BA2

B12

UA1

VSSQB1VSSQB4VSSQB9VSSQ

A0
A1
A2
A3
A4
A5
A6
A7
A8/AP
A9
A10
A11
BA0
BA1

DM0
DM1
DM2
DM3

WDQS0
WDQS1
WDQS2
WDQS3

VREF
VREF
RFU1
RFU2

RAS#
CAS#
WE#
CS#

CKE
CK
CK#

ZQ
MF

RDQS0
RDQS1
RDQS2
RDQS3

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

SEN
RESET
BA2

VSSA
VSSA

VSSQD1VSSQD4VSSQD9VSSQ

K4

H2

K3

M4

K9

H11

K10

L9

K11

M9

K2

L4
G4
G9

E3

E10

N10

N3
D2

D11

P11

P2
H1

H12

J2

J3
H3

F4
H9

F9
H4

J11
J10

A4

A9
D3

D10

P10

P3

A2

A11

F1

F12

M1

M12

V2

V11

V4

V9

H10

J1

J12

D12

VSSA3VSS

G11

VSSQG2VSSQ

VSSG1VSS

A10

L11

VSSQL2VSSQ

G12

4

VSSQP1VSSQP4VSSQP9VSSQ

VSSL1VSS

VSSV3VSS

L12

P12

T12

VSSQT1VSSQT4VSSQT9VSSQ

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8

DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

VDDA
VDDA

K4J52324QE-BC14_FBGA136~D

@

V10

FBAD1

B2

FBAD3

B3

FBAD2

C2

FBAD5

C3

FBAD7FBAA5

E2

FBAD4

F3

FBAD0

F2

FBAD6

G3

FBAD16

B11

FBAD17

B10

FBAD18

C11

FBAD19

C10

FBAD20

E11

FBAD21

F10

FBAD22

F11

FBAD23

G10

FBAD27

M11

FBAD25

L10

FBAD24

N11

FBAD26

M10

FBAD31

R11

FBAD28

R10

FBAD30

T11

FBAD29

T10

FBAD10

M2

FBAD12

L3

FBAD9

N2

FBAD15

M3

FBAD8

R2

FBAD13

R3

FBAD11

T2

FBAD14

T3

A1
A12
C1
C4
C9
C12
E1
E4
E9
E12
J4
J9
N1
N4
N9
N12
R1
R4
R9
R12
V1
V12

K1
K12

0.1U_0402_16V4Z

3

B12

D12

G11

VSSQD1VSSQD4VSSQD9VSSQ

VSSA3VSS

A10

VSSQG2VSSQ

VSSG1VSS

G12

L11

VSSQL2VSSQ

VSSL1VSS

UA2

FBAA0
FBAA1
FBBA2
FBBA3
FBBA4
FBBA5
FBAA6
FBAA7
FBAA8
FBAA9
FBAA10
FBAA11
FBA_BA0
FBA_BA1

DQMA#5
DQMA#4
DQMA#6
DQMA#7

WDQSA5
WDQSA4
WDQSA6
WDQSA7

+VREFA0
+VREFA1

FBARAS#
FBACAS#
FBAWE#
FBACS0#

+1.8VS

FBA_CKE
CLKA1
CLKA1#

RDQSA5
RDQSA4
RDQSA6
RDQSA7

FBA_RST#
FBA_BA2

+1.8VS

+1.8VS +1.8VS

1

1

2

2

C166

0.1U_0402_16V4Z

VGA@

C134

VGA@

CLKA135
CLKA1#35

1 2

R82 243_0402_1%

VGA@

VSSQB1VSSQB4VSSQB9VSSQ

K4

A0

H2

A1

K3

A2

M4

A3

K9

A4

H11

A5

K10

A6

L9

A7

K11

A8/AP

M9

A9

K2

A10

L4

A11

G4

BA0

G9

BA1

E3

DM0

E10

DM1

N10

DM2

N3

DM3

D2

WDQS0

D11

WDQS1

P11

WDQS2

P2

WDQS3

H1

VREF

H12

VREF

J2

RFU1

J3

RFU2

H3

RAS#

F4

CAS#

H9

WE#

F9

CS#

H4

CKE

J11

CK

J10

CK#

A4

ZQ

A9

MF

D3

RDQS0

D10

RDQS1

P10

RDQS2

P3

RDQS3

A2

VDD

A11

VDD

F1

VDD

F12

VDD

M1

VDD

M12

VDD

V2

VDD

V11

VDD

V4

SEN

V9

RESET

H10

BA2

J1

VSSA

J12

VSSA

2

P12

T12

VSSQP1VSSQP4VSSQP9VSSQ

VSSQT1VSSQT4VSSQT9VSSQ

B2

DQ0

B3

DQ1

C2

DQ2

C3

DQ3

E2

DQ4

F3

DQ5

F2

DQ6

G3

DQ7

B11

DQ8

B10

DQ9

C11

DQ10

C10

DQ11

E11

DQ12

F10

DQ13

F11

DQ14

G10

DQ15

M11

DQ16

L10

DQ17

N11

DQ18

M10

DQ19

R11

DQ20

R10

DQ21

T11

DQ22

T10

DQ23

M2

DQ24

L3

DQ25

N2

DQ26

M3

DQ27

R2

DQ28

R3

DQ29

T2

DQ30

T3

DQ31

A1

VDDQ

A12

VDDQ

C1

VDDQ

C4

VDDQ

C9

VDDQ

C12

VDDQ

E1

VDDQ

E4

VDDQ

E9

VDDQ

E12

VDDQ

J4

VDDQ

J9

VDDQ

N1

VDDQ

N4

VDDQ

N9

VDDQ

N12

VDDQ

R1

VDDQ

R4

VDDQ

R9

VDDQ

R12

VDDQ

V1

VDDQ

V12

VDDQ

K1

VDDA

K12

VDDA

VSSV3VSS

K4J52324QE-BC14_FBGA136~D

L12

V10

0.1U_0402_16V4Z

@

FBAD40
FBAD41
FBAD42
FBAD43
FBAD44
FBAD45
FBAD46
FBAD47
FBAD35
FBAD34
FBAD32
FBAD33
FBAD39
FBAD36
FBAD37
FBAD38
FBAD51
FBAD48
FBAD53
FBAD50
FBAD52
FBAD49
FBAD54
FBAD55
FBAD59
FBAD57
FBAD61
FBAD62
FBAD60
FBAD63
FBAD56
FBAD58

C124

VGA@

+1.8VS

1

2

1

2

+VREFA0
+VREFA1

C125

0.1U_0402_16V4Z

VGA@

FBAD[0..63]35
RDQSA[0..7]35
WDQSA[0..7]35
DQMA#[0..7]35
FBAA[0..11]35
FBA_BA[0..2]35
FBBA[2..5]35

1 2

R398 976_0402_1%

1 2

R394 976_0402_1%

2N7002W-7-F_SOT323-3~D

Q32

VGA@

VREF setting:
70% for normal.
40% for power saving when mosfet short.
(976*2.49K)/(976+2.49)=701.16

701.16/(1.05K+701.16)=0.40039

VGA@
VGA@

1

FBAD[0..63]
RDQSA[0..7]
WDQSA[0..7]
DQMA#[0..7]
FBAA[0..11]
FBA_BA[0..2]
FBBA[2..5]

13

D

G

S

CLKA1

CLKA1#

2

FB_VREFCTL 34,40

12

R81
243_0402_1%

VGA@

+1.8VS +1.8VS

0.01U_0402_16V7K

1

1

C132

C163

VGA@

2

1000P_0402_50V7K~N

A A

5

VGA@

2

0.01U_0402_16V7K

GDDR3 BGA Memory GDDR3 BGA Memory

1

2

C194

VGA@

0.1U_0402_16V4Z

1

C152

VGA@

2

1

C186

VGA@

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

C190

VGA@

2

4

1

C212

VGA@

2

0.1U_0402_16V4Z

1U_0402_6.3V4K

1

C216

VGA@

2

1

C161

VGA@

2

1U_0402_6.3V4K

10U_0805_10V4Z

1

C198

VGA@

2

1

C133

VGA@

2

22U_0805_6.3V4Z

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2007/12/28 2007/12/28

0.01U_0402_16V7K

1

C127

VGA@

2

1000P_0402_50V7K~N

1

C545

VGA@

2

0.01U_0402_16V7K

Compal Secret Data

1

C116

VGA@

2

Deciphered Date

0.1U_0402_16V4Z

1

2

C107

VGA@

0.1U_0402_16V4Z

2

1

2

C144

VGA@

0.1U_0402_16V4Z

1

C137

VGA@

2

1U_0402_6.3V4K

1

1

2

0.1U_0402_16V4Z

C537

C126

VGA@

VGA@

2

Title

GDDR3_A

Size Document Number Rev

Custom

LA-4131P

Date: Sheet

10U_0805_10V4Z

1

1

C167

VGA@

2

1U_0402_6.3V4K

2

C108

VGA@

1

C157

VGA@

2

22U_0805_6.3V4Z

Compal Electronics, Inc.

1

0.2

of

39 53Monday, February 18, 2008

5

+1.8VS

12

R246

1.05K_0402_1%

VGA@

12

R247

2.49K_0402_1%

D D

VGA@

+1.8VS

12

R281

1.05K_0402_1%

VGA@

12

R280

2.49K_0402_1%

VGA@

C C

B B

CLKC0

CLKC0#

+VREFC0

1

C372

0.01U_0402_16V7K

VGA@

2

+VREFC1

1

C399

0.01U_0402_16V7K

VGA@

2

12

R271
243_0402_1%

VGA@

FBCA0
FBCA1
FBCA2
FBCA3
FBCA4
FBCA5
FBCA6
FBCA7
FBCA8
FBCA9
FBCA10
FBCA11
FBC_BA0
FBC_BA1

DQMC#1
DQMC#0
DQMC#2
DQMC#3

WDQSC1
WDQSC0
WDQSC2
WDQSC3

+VREFC0
+VREFC1

FBCRAS#35
FBCCAS#35
FBCWE#35
FBCCS0#35

FBC_CKE35
CLKC035
CLKC0#35

1 2

R232 243_0402_1%

VGA@

FBC_RST#35

+1.8VS +1.8VS

1

2

1000P_0402_50V7K~N

FBCRAS#
FBCCAS#
FBCWE#
FBCCS0#

FBC_CKE
CLKC0
CLKC0#

RDQSC1
RDQSC0
RDQSC2
RDQSC3

+1.8VS

FBC_RST#
FBC_BA2 FBC_BA2

0.01U_0402_16V7K

1

C379

VGA@

2

0.01U_0402_16V7K

1

2

C401

VGA@

C385

VGA@

B12

UB1

VSSQB1VSSQB4VSSQB9VSSQ

A0
A1
A2
A3
A4
A5
A6
A7
A8/AP
A9
A10
A11
BA0
BA1

DM0
DM1
DM2
DM3

WDQS0
WDQS1
WDQS2
WDQS3

VREF
VREF
RFU1
RFU2

RAS#
CAS#
WE#
CS#

CKE
CK
CK#

ZQ
MF

RDQS0
RDQS1
RDQS2
RDQS3

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

SEN
RESET
BA2

VSSA
VSSA

VSSQD1VSSQD4VSSQD9VSSQ

K4
H2
K3

M4

K9

H11

K10

L9

K11

M9

K2
L4

G4
G9

E3

E10

N10

N3
D2

D11

P11

P2
H1

H12

J2
J3

H3
F4
H9
F9

H4

J11
J10

A4
A9

D3

D10

P10

P3
A2

A11

F1

F12

M1

M12

V2

V11

V4
V9

H10

J1

J12

GDDR3 BGA Memory GDDR3 BGA Memory

0.1U_0402_16V4Z

1

C386

VGA@

2

0.1U_0402_16V4Z

D12

VSSA3VSS

1

2

G11

VSSQG2VSSQ

VSSG1VSS

A10

C373

VGA@

4

L11

P12

VSSQL2VSSQ

VSSQP1VSSQP4VSSQP9VSSQ

VSSQT1VSSQT4VSSQT9VSSQ

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8

DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

VDDA
VDDA

VSSL1VSS

VSSV3VSS

K4J52324QE-BC14_FBGA136~D

L12

V10

G12

0.1U_0402_16V4Z

1

C377

VGA@

2

0.1U_0402_16V4Z

T12

B2
B3
C2
C3
E2
F3
F2
G3
B11
B10
C11
C10
E11
F10
F11
G10
M11
L10
N11
M10
R11
R10
T11
T10
M2
L3
N2
M3
R2
R3
T2
T3

A1
A12
C1
C4
C9
C12
E1
E4
E9
E12
J4
J9
N1
N4
N9
N12
R1
R4
R9
R12
V1
V12

K1
K12

@

1

C378

VGA@

2

FBCD11
FBCD15
FBCD14
FBCD9
FBCD13
FBCD8
FBCD12
FBCD10
FBCD0
FBCD1
FBCD2
FBCD3
FBCD4
FBCD5
FBCD6
FBCD7
FBCD19
FBCD17
FBCD23
FBCD16
FBCD21
FBCD22
FBCD20
FBCD18
FBCD25
FBCD27
FBCD24
FBCD31
FBCD30
FBCD29
FBCD28
FBCD26

C374

0.1U_0402_16V4Z

VGA@

1U_0402_6.3V4K

1

C389

VGA@

2

3

B12

UB2

FBCA0
FBCA1
FBDA2
FBDA3
FBDA4
FBDA5
FBCA6
FBCA7
FBCA8
FBCA9
FBCA10
FBCA11
FBC_BA0
FBC_BA1

DQMC#4
DQMC#7
DQMC#6
DQMC#5

WDQSC4
WDQSC7
WDQSC6
WDQSC5

+VREFC0
+VREFC1

FBCRAS#
FBCCAS#
FBCWE#
FBCCS0#

+1.8VS

FBC_CKE
CLKC1
CLKC1#

RDQSC4
RDQSC7
RDQSC6
RDQSC5

FBC_RST#

+1.8VS

+1.8VS +1.8VS

1

1

C370

0.1U_0402_16V4Z

VGA@

2

2

10U_0805_10V4Z

1

1

2

1U_0402_6.3V4K

C381

VGA@

2

C404

VGA@

22U_0805_6.3V4Z

R187 243_0402_1%

1

C392

VGA@

2

CLKC135
CLKC1#35

1 2

VGA@

VSSQB1VSSQB4VSSQB9VSSQ

K4

A0

H2

A1

K3

A2

M4

A3

K9

A4

H11

A5

K10

A6

L9

A7

K11

A8/AP

M9

A9

K2

A10

L4

A11

G4

BA0

G9

BA1

E3

DM0

E10

DM1

N10

DM2

N3

DM3

D2

WDQS0

D11

WDQS1

P11

WDQS2

P2

WDQS3

H1

VREF

H12

VREF

J2

RFU1

J3

RFU2

H3

RAS#

F4

CAS#

H9

WE#

F9

CS#

H4

CKE

J11

CK

J10

CK#

A4

ZQ

A9

MF

D3

RDQS0

D10

RDQS1

P10

RDQS2

P3

RDQS3

A2

VDD

A11

VDD

F1

VDD

F12

VDD

M1

VDD

M12

VDD

V2

VDD

V11

VDD

V4

SEN

V9

RESET

H10

BA2

J1

VSSA

J12

VSSA

1

C353

VGA@

2

1000P_0402_50V7K~N

D12

VSSQD1VSSQD4VSSQD9VSSQ

0.01U_0402_16V7K

1

C365

VGA@

2

0.01U_0402_16V7K

VSSQG2VSSQ

VSSA3VSS

A10

2

G11

L11

P12

VSSQL2VSSQ

VSSQP1VSSQP4VSSQP9VSSQ

VSSG1VSS

VSSL1VSS

VSSV3VSS

K4J52324QE-BC14_FBGA136~D

L12

V10

G12

0.1U_0402_16V4Z

1

C357

VGA@

2

T12

VSSQT1VSSQT4VSSQT9VSSQ

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8

DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

VDDA
VDDA

@

1

C356

VGA@

2

0.1U_0402_16V4Z

FBCD32

B2

FBCD33

B3

FBCD34

C2

FBCD35

C3

FBCD36

E2

FBCD37

F3

FBCD38

F2

FBCD39

G3

FBCD58

B11

FBCD57

B10

FBCD59

C11

FBCD56

C10

FBCD63

E11

FBCD60

F10

FBCD61

F11

FBCD62

G10

FBCD53

M11

FBCD49

L10

FBCD55

N11

FBCD48

M10

FBCD52

R11

FBCD51

R10

FBCD54

T11

FBCD50

T10

FBCD43

M2

FBCD47

L3

FBCD44

N2

FBCD46

M3

FBCD45

R2

FBCD42

R3

FBCD41

T2

FBCD40

T3

A1
A12
C1
C4
C9
C12
E1
E4
E9
E12
J4
J9
N1
N4
N9
N12
R1
R4
R9
R12
V1
V12

K1
K12

0.1U_0402_16V4Z

1

C367

VGA@

2

C344

VGA@

0.1U_0402_16V4Z

1

2

+1.8VS

1

2

C371

VGA@

+VREFC0

R229 976_0402_1%

+VREFC1

R237 976_0402_1%

2N7002W-7-F_SOT323-3~D

1

C347

0.1U_0402_16V4Z

VGA@

2

1

C368

VGA@

2

0.1U_0402_16V4Z

1

VGA@
VGA@

1

C349

VGA@

2

D

S

FBCD[0..63]
RDQSC[0..7]
WDQSC[0..7]
DQMC#[0..7]
FBCA[0..11]
FBC_BA[0..2]
FBDA[2..5]

13

G

CLKC1

CLKC1#

10U_0805_10V4Z

FBCD[0..63]35
RDQSC[0..7]35
WDQSC[0..7]35
DQMC#[0..7]35
FBCA[0..11]35
FBC_BA[0..2]35
FBDA[2..5]35

1 2
1 2

Q16

VGA@

VREF setting:
70% for normal.
40% for power saving when mosfet short.
(976*2.49K)/(976+2.49)=701.16

701.16/(1.05K+701.16)=0.40039

1U_0402_6.3V4K

1

C363

VGA@

2

1U_0402_6.3V4K

2

12

1

C375

VGA@

2

FB_VREFCTL 34,39

R226
243_0402_1%

VGA@

1

C352

VGA@

2

22U_0805_6.3V4Z

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2007/12/28 2007/12/28

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

Compal Electronics, Inc.

GRRD3_B

LA-4131P

1

0.2

of

40 53Monday, February 18, 2008

5

4

3

2

1

ADPIN

PJPDC1

1

1

2

2

3

3

4

4

5

5

6

6

D D

C C

7

GND

8

GND

ACES_88299-0600

@

BATT+

51ON#29

PL16

FBM-L11-160808-601LMT 0603~D

PD4

12

RLS4148_LL34-2

CHGRTCP

12

PR205

100K_0402_5%~D

PR206

22K_0402_5%

1 2

DOCK_PSID

12

12

PC164

12

12

PC158

100P_0402_50V8J~D

VIN

13

PQ50

PD3

RLS4148_LL34-2

1 2
12

PR203

33_1206_5%

12

PC165

0.1U_0603_25V7K~D

PJP1
JUMP_43X118@

2

112

TP0610K-T1-E3_SOT23-3

32.8

0.22U_1206_25V7K

2

PL17

FBMA-L18-453215-900LMA90T_1812

1 2

12

PC157

1000P_0402_50V7K~D

VS

PC160

100P_0402_50V8J~D

VIN

PC156

2200P_0402_50V7K~D

@

1 2

12

PC159

1000P_0402_50V7K~D

PC162

.1U_0402_16V7K~D

VIN

12

PR190

82.5K_0402_1%~D
PR193

22K_0402_1%~D

1 2

12

PR194

19.6K_0402_1%~D

+

-

8

PU12B

P

O

G

LM393DR_SO8

4

12

7

12

5
6

N40N41
N35

PC163
1000P_0402_50V7K~D

Vin Detector

56K_0402_5%~D@

1 2

PR189
1M_0402_1%~N

1 2

VS

8

PU12A

3

P

+

2

-

G

LM393DR_SO8

4

PR198

10K_0402_5%~D

12

PR188

O

12

PC161

1

0.01U_0402_25V7K~D

RLZ4.3B_LL34

RTCVREF

3.3V

PD1

VIN

12

PR191
10K_0402_5%~D

12

PR192
1K_0402_5%~D

1 2

12

PR195
10K_0402_5%~D

ACIN 19,28,40

Max. typ. Min.

L-->H 18.234 17.841 17.449
H-->L 17.597 17.210 16.813

+3VALWP+5VALWP

PR209

1 2

2.2K_0402_5%~D

+5VALWP

2

3

PD6

@

PR214

Title

Size Document Number Rev

Custom

Date: Sheet

DA204U_SOT323~D

10K_0402_1%~D

PR216

1 2

10K_0402_1%~D@

DCIN / Precharge

1

JAL60

PS_ID 28

PSID_DISABLE# 28

1

of

41 50Monday, February 18, 2008

0.2

2

IN

+VGA_COREP

12

PR207
200_0805_5%

12

PC167
1U_0805_25V4Z~D

+1.5VSP

+0.9VSP

+VCCPP

PJP12
JUMP_43X118@

112

PJP14
JUMP_43X118@

112

JUMP_43X118@

112

PJP4
JUMP_43X118@

112

PJP6
JUMP_43X118@

112

PJP8
JUMP_43X118@

112

PJP10
JUMP_43X118@

112

2

PR212

PD5

DA204U_SOT323~D

3

1

+5VALWP

12

PR208

@

1 2

0_0402_5%~D

PJP2
JUMP_43X118@

+1.2VSP

2

+1.5VS

2

+0.9VS

2

+VCCP

2

+VGA_CORE

2

2

PJP25

2

4

112

2

+1.2VS

DOCK_PSID

2

1

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

PR213

3

PD7
SM24_SOT23

100K_0402_1%~D

@

PR215

15K_0402_1%~D

2006/10/1 2007/5/01

FDV301N_NL_SOT23-3~D

1 2

1 2

Compal Secret Data

PQ53

2

Deciphered Date

D

1 3

B

E

33_0402_5%~D

S

1 2

G

2

C

PQ54

MMST3904-7-F_SOT323-3

3 1

2

B B

+5VALWP

+3VALWP

A A

+1.8VP

+1.25VSP

3.3V

RTCVREF

12

PC166

PJP3
JUMP_43X118@

112

PJP5
JUMP_43X118@

112

PJP7
JUMP_43X118@

112

PJP9
JUMP_43X118@

112

PJP11
JUMP_43X118@

112

PJP13
JUMP_43X118@

112

5

PU14G920AT24U_SOT89-3

3

OUT

4.7U_0805_6.3V6K~N

2

2

2

2

2

2

GND

1

+5VALW

+3VALW

+1.8V

+1.25VS

A

B

C

D

E

PQ55

VIN

12

PR339

1 1

1_1210_5%

12

PR272

1_1210_5%

PC169

2.2U_0805_25V6K

1 2

1 2

90W adapter
Icharge=(Vsrset/Vvdac)*(0.1/PR34)=3A

Iadapter=(Vacset/Vvdac)*(0.1/PR23)=3.65A

Input OVP : 22.3V

2 2

Input UVP : 17.26V
Fsw : 300KHz

VREF

PR229
100K_0402_1%~D

1 2

13

D

G

S

GND

CELLS

VREF

CELLS

2

PQ61
SSM3K7002F_SC59-3

3 Cell
4 Cell

ACGOOD#

3cell/4cell#

Cells selector

3 3

PR235

1 2

B+

100_0805_5%~D

+5VALW

PR236

1 2

12

1 2

1SS355_SOD323-2

220K_0402_5%

470K_0402_5%~D

PQ64

2

G

PD9

PR238

1 2

32.8

220K_0402_5%

4 4

12

PC194

PR239

0.1U_0603_25V7K~D

TP0610K-T1-E3_SOT23-3

13

32.8

2

13

D

RHU002N06_SOT323

S

PQ63

PC193

FDS4435BZ_SO8

8
7
6
5

PC170

0.01U_0603_50V7K~D

PR221
340K_0402_1%~D

1 2

ACDET

PR223

54.9K_0402_1%

1 2

PR226
340K_0402_1%~D

1 2

OVPSET

PR227

54.9K_0402_1%

1 2

100K_0402_1%~D

0.1U_0603_25V7K~D

CHGVADJ29

B+_BIAS

1 2

0.1U_0805_25V7K

1

S

D

2

S

D

3

S

D

4

G

D

SI2301BDS-T1-E3_SOT23-3

PR228

1 2

PC189

210K_0402_1%~D

1 2

1 2

2

12

REGN

PR53

PC174

CP setting

ACSET

FDS4435BZ_SO8

1
2
3
4

12

PR219

100K_0402_1%~D

0.01U_0402_25V7K~D

56.2K_0402_1%

1 2

VREF

0.01U_0402_25V7K~D

@

PQ60

1 3

12

12

PR54
499K_0402_1%~D

RTCVREF

PQ56

8

S

D

7

S

D

6

S

D

5

G

D

12

PC178

0.1U_0603_25V7K~D

PR224

12

PC182

1U_0603_10V6K~D

12

PR230
100K_0402_1%~D

PR51
0_0402_5%@

VADJ

+COINCELL

12

Z4012

3

2

PD2

1

BAT54CW_SOT323~D

27.4

PR217

0.015_2512_1%

1
2

.1U_0402_16V7K~D

PC188

PC175

1 2

ACSET

12

PR225
100K_0402_1%~D

1 2

0.47U_0603_16V7K~N

VREF

12

4
3

12

@

PC184

VADJ

CHGEN#

PC176

0.1U_0603_25V7K~D

/BATDRV

COIN RTC Battery

PR1
1K_0402_5%~D

+RTC_CELL

12

PC1
1U_0603_10V6K~D

Move to power schematic

PU15

1

CHGEN

2

ACN

3

ACP

4

ACDRV

5

ACDET

6

ACSET

7

ACOP

8

OVPSET

9

AGND

10

VREF

11

VDAC

12

VADJ

13

ACGOOD

14

BATDRV

BQ24751ARHDR_QFN28_5X5

ADP_I28

+COINCELL

IREF Current

3.265V 3.3A

0.49V 0.5A

Security Classification

PVCC

BTST

HIDRV

PH

REGN

LODRV

PGND

LEARN

CELLS

SRP
SRN
BAT

TP

SRSET

IADAPT

PJP20

1

1

2

2

3

G1

4

G2

ACES_85204-02001

@

28

27

26

25

24

23

22

21

20

19
18
17

29

16

15

100P_0402_50V8J~D

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

B+

PJP15

2

112

JUMP_43X118@

PC177

0.1U_0805_25V7K

1 2

PR220

0_0603_5%~D

1 2

DH_CHG

LX_CHG

PD8

RLS4148_LL34-2

REGN

1U_0603_10V6K~D

12

PC183

DL_CHG

CELLS

12

PC190

0.1U_0603_25V7K~D

12

0.1U_0603_25V7K~D

ACOFF 28,39

1 2

PC179

ICHG setting

12

1 2

PR233

10_0603_5%~D

PC192

2006/10/1 2007/5/01

PR234
100K_0402_1%~D

12

Compal Secret Data

ADP_C28

CHG_B+

578

PQ57

3 6

241

578

3 6

241

49.9K_0402_1%~D

12

PC191

0.01U_0402_25V7K~D

@

Deciphered Date

1 2

PC171

AO4466_SO8

PL18

10UH_SIL1045RA-100PF_4.5A_30%

1 2

PQ59
AO4712_SO8

PR231

12

ADP_C

2

G

D

1 2

4.7U_1206_25V6K~D

IREF 28

ACSET

12

PR364
10K_0402_5%~D

@

13

D

S

0.01U_0402_25V7K~D

1 2

PC172

PC173

4.7U_1206_25V6K~D

4.7U_1206_25V6K~D

PC180

1 2

10U_1206_25V6M~D

12

PC186

0.1U_0603_25V7K~D

PQ83
SSM3K7002F_SC59-3

@

12

PR218

PC168

/BATDRV

PR222

0.02_2512_1%

1
2

PC185

.1U_0402_16V7K~D

1 2

ACGOOD#

FSTCHG28

Title

Size Document Number Rev

B

Date: Sheet

100K_0402_1%~D

1 2

4

3

G

5

4
3

12

PC187

0.1U_0603_25V7K~D

@

VREF

PR232

100K_0402_1%~D

2

G

@

2

G

1 2

@

13

D

S

VREF

PR237
100K_0402_1%~D

1 2

13

D

S

PQ62
SSM3K7002F_SC59-3

CHGEN#

PQ65
SSM3K7002F_SC59-3

Compal Electronics, Inc.

Charger

JAL60

PQ58

S1S2S

FDS4435BZ_SO8

D8D7D6D

12

****

E

BATT+

PC181

10U_1206_25V6M~D

ACIN 19,28,39

42 50Monday, February 18, 2008

0.2

of

5

4

3

2

1

ISL6237_B+

12

12

PC199

PC198

4.7U_1206_25V6K~D

4.7U_1206_25V6K~D

PL21

4.7UH_SIL104R-4R7PF_5.7A_30%

12

4.7_1206_5%~D

12

PC209

680P_0603_50V8J~D

12

PC200

2200P_0402_50V7K~D

12

PR246

1 2

61.9K_0402_1%~D

PR248

1 2

10K_0402_1%~D

+5VALWP

1

+

PC210
220U_6.3V_M

2

PQ66

12

12

1 2

ISL6237_B+

578

3 6

241

578

3 6

241

PR251

100K_0402_1%~D

PR252

200K_0402_5%~D

0.047U_0603_16V7K~D

AO4466_SO8

PQ68
AO4712_SO8

1 2

1 2

PR259

0_0402_5%~D

PC213

PC205

0.1U_0603_25V7K~D

1 2

PC212

0.22U_0603_25V7-K

VL

PR257

12

1 2

806K_0603_1%

47K_0402_5%~D@

1 2

12

PR240

0_0805_5%

1 2

PC201

0.1U_0603_25V7K~D

PR243

BST3A BST5A

12

0_0603_5%~D

LX3

DL3

FB3

VL

1 2

PU16

33

TP

26

UGATE2

24

BOOT2

25

PHASE2

23

LGATE2

30

OUT2

32

REFIN2

1 2

PC202

6

3

VIN

VCC

2VREF_ISL6237

1 2

PC211 0.22U_0603_10V7K~D

PR254

@

0_0402_5%~D

PR260

PC214

@

.047U_0402_16V7K~D

1 2

12

20

14

27

PR256

1 2

2VREF_ISL6237

1

REF

8

LDOREFIN

NC

4

EN_LDO

EN1

EN2

5

0_0402_5%~D

12

PC239

1U_0603_10V6K~D

NC

TON

2

12

PR258

0_0402_5%~D

2VREF_ISL6237

VL

PC203

1U_0603_10V6K~D

7

LDO

PVCC

UGATE1

BOOT1

PHASE1

LGATE1

PGND

OUT1

FB1

BYP

SKIP

POK2

POK1

ILIM1

ILIM2

GND

ISL6237IRZ-T_QFN32_5X5

21

@

12

4.7U_0805_6.3V6K~N

19
15
17

16

18

22

10

11

9

29

28

13

12

31

PC207

1U_0603_10V6K~D

1 2

DH5DH3

PR245

0_0603_5%~D

0.1U_0603_25V7K~D

LX5

DL5

FB5

PR249 0_0402_5%~D@

PR250 0_0402_5%~D

1 2

ILM1

ILIM2

Rds(on) = 18m ohm(max) ; Rds(on) = 15m ohm(typical)

12

PC208

1 2

12

PR253

330K_0402_1%

PR255

330K_0402_1%

PQ67

PQ69

AO4712_SO8

12

12

578

3 6

241

578

3 6

241

VL

AO4466_SO8

POK

PR242

@

@

5VALWP
Imax=6A

Iocp=10.146A

B+

PL19

HCB4532KF-800T90_1812

1 2

PJP21

1 2

D D

PAD-OPEN 4x4m

+3VALWP

1

+

PC204

220U_6.3V_M

2

C C

PR244

0_0402_5%~D

1 2

PR247

1 2

@

10K_0402_1%~D

12

PC195

PC196

4.7U_1206_25V6K~D

4.7U_1206_25V6K~D

PL20

1 2

4.7UH_SIL104R-4R7PF_5.7A_30%

12

PC197

2200P_0402_50V7K~D

PR241

@

PC206

@

12

4.7_1206_5%~D

680P_0603_50V8J~D

Rds(on) = 18m ohm(max) ; Rds(on) = 15m ohm(typical)

3.3VALWP
Imax=6A

VS

PD10

RLZ5.1B_LL34

1 2

Iocp=10.133A

B B

12

RB751V_SOD323-2

PD16

TP0610K-T1-E3_SOT23-3

A A

PQ76

32.8

2

MAINPWON46

1 3

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2006/10/1 2007/05/30

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

+3VALWP, +5VALWP

Size Document Number Rev

2

Date: Sheet

JAL60

Monday, February 18, 2008

1

43 50

of

0.2Custom

5

4

3

2

1

PC215

1U_0402_6.3V6K~D

2.2_0603_1%~D

PC217

PR264

12

10_0603_1%

12

PR266

22K_0402_1%~D

1 2

6

FSET1

ISL6228HRTZ-T_QFN28_4X4

PR261

12

12

5

VIN1

PU17

PR268

1 2

AO4466_SO8

0_0603_5%~D

PC232

串1K電組 上

1K_0402_1%~D

1 2

1.5V_EN

PR279

12

PR283

0_0603_5%~D

PR263

LX_1.5V

PGOOD1 PGOOD2

PL22

HCB4532KF-800T90_1812

1 2

PR271

1 2

12.1K_0402_1%

PC224

0.033U_0402_16V7K~D

1 2

PL23

1 2

1.5VP
Imax=5A

B+

1 2

PAD-OPEN 4x4m

1000P_0402_50V7K~D

PC221

PR278

12.1K_0402_1%

1 2

PJP22

1 2

12

PR270

68K_0402_1%

ISL6228_B+

12

PC225

4.7U_1206_25V6K~D

12

PR281

4.7_1206_5%~D@

12

3.3K_0402_5%~D
PR269

12

12

PQ70

PC223

4.7U_1206_25V6K~D

PC231

680P_0603_50V8J~D

@

ISL6228_B+

578

3 6

241

578

PQ71
AO4712_SO8

3 6

241

.1U_0402_16V7K~D

45.3K_0402_1%~D

D D

C C

+1.5VSP

1.8UH_SIL104R-1R8PF_9.5A_30%

1

+

PC227

2

220U_6.3V_M

DCR 7m ohm(max)

Iocp=9A

B B

SUSP#26,28,31,44

PR287

0_0402_5%~D

1.5V_EN

12

12

PC238

@

@

+5VALWP +5VALWP

+5VALWP

12

@

1000P_0402_50V7K~D

UG_1.5V

BST_1.5V

12

1U_0402_6.3V6K~D

LG_1.5V

+5VALWP

0.1U_0603_25V7K~D

ISL6228_B+ ISL6228_B+

PC219

7

PGOOD1

8

FB1

9

VO1

10

OCSET1

11

EN1

12

PHASE1

13

UGATE1

14

BOOT1

PVCC115LGATE116PGND117PGND218LGATE219PVCC220BOOT2

PC235

1 2

12

4

VCC1

PC216

12

1U_0402_6.3V6K~D

PR262

1 2

2.2_0603_1%~D

12

1000P_0402_50V7K~D

3

2

VCC2

1 2

PC218

0.1U_0603_25V7K~D

PR265

10_0603_1%

PC220

12

1

VIN2

FSET2

21

+5VALWP

PC236
1U_0402_6.3V6K~D

1 2

GND_T

PGOOD2

FB2

VO2

OCSET2

EN2

PHASE2

UGATE2

BST_VCCPP

12

PR267

18.2K_0402_1%~D

29

28

27

26

25

24

23

UG_VCCPP

22

PR286

1 2

0_0603_5%~D

LG_VCCPP

PR290

12

1K_0402_1%~D

@

PR280

0_0402_5%~D

1 2

PC228

1 2

0.01U_0402_25V7K~D

@

0_0603_5%~D

1 2

LX_VCCPP

PC234

1 2

.1U_0402_16V7K~D

SUSP# 26,28,31,44

PR284

+5VALWP 39,41,43

578

PQ72

AO4466_SO8

3 6

241

578

PQ73
AO4712_SO8

3 6

241

ISL6228_B+

12

PC229

4.7U_1206_25V6K~D

12

PR285

4.7_1206_5%~D@

12

PR273

90.9K_0402_1%~N

1 2

12

PC226

PC237

@

680P_0603_50V8J~D

3.3K_0402_5%~D

4.7U_1206_25V6K~D

1 2

1.8UH_SIL104R-1R8PF_9.5A_30%

DCR 7m ohm(max)

1000P_0402_50V7K~D

PR274

12

1 2

PR275

1 2

68K_0402_1%

PR276

1 2

15.4K_0402_1%~D

0.033U_0402_16V7K~D
PC230

1 2

PR282

15.4K_0402_1%~D

PL24

1 2

+VCCPP
Imax=5A

Iocp=9A

PC222

+VCCPP

1

+

220U_6.3V_M

PC233

2

0.01U_0402_25V7K~D

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/10/1 2007/5/01

Compal Secret Data

Deciphered Date

2

Title

Size Document Number Rev

Date: Sheet

+1.5VP/VCCPP

Monday, February 18, 2008

JAL60

of

1

44 50

0.2

5

4

3

2

1

D D

B+

C C

SYSON13,28,32

B B

PL29

HCB4532KF-800T90_1812

1 2

PJP23

1 2

PAD-OPEN 4x4m

PR344

22K_0402_1%~D

1 2

PC285

@

12

10U_1206_25V6M~D

12

PC291
.1U_0402_16V7K~D

12

PC286

10U_1206_25V6M~D

6269_1.8V

12

PC289

2.2U_0603_6.3V6K~D

6269_B+

PR362

0_0402_5%~D

1 2

12

PC293

68P_0402_50V8J~N

6269_1.8V

PR341

10K_0402_1%~D

17

PU23

GND

1

VIN

2

VCC

3

FCCM

4

EN

COMP5FB6FSET

12

PR348

33K_0402_1%~D

12

PC295

2200P_0402_25V7K~N

12

16

15

PHASE

PGOOD

PR349

57.6K_0402_1%

PHASE_1.8V

14

UG

7

12

PR340

1 2

2.2_0603_5%~D

+5VS

BOOT_1.8V

13

BOOT

PVCC

PGND

ISEN

VO

8

12

PC294

0.01U_0402_25V7K~D

12

12

2.2U_0603_6.3V6K~D

11

LG

10

ISEN_1.8V

9

16.5K_0402_1%~D

ISL6269CRZ-T_QFN16_4X4~N

PC287

PR342

@

0_0603_5%~D

PR343

4.7_0603_5%

1 2

PC288

1 2

LG_1.8V

1 2

PR345

UG_1.8V

1 2

0.1U_0603_25V7K~D

6269_1.8V

PQ80

AO4712_SO8

578

3 6

578

3 6

AO4712
Rds(on)=15mohm~18mohm

PQ79
AO4466_SO8

241

1.8UH_SIL104R-1R8PF_9.5A_30%

PR346

4.7_1206_5%~D@

1 2

PC292
680P_0603_50V8J~D@

1 2

241

PL30

1 2

1.8VP
Imax=9A

Iocp=12.6A

PR350

1.5K_0402_1%

PR347
3K_0402_1%

1 2

12

1

+

PC290
220U_6.3V_M

2

+1.8VP

+1.8VP

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2006/10/1 2007/05/30

3

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

2

Date: Sheet

Compal Electronics, Inc.

NB_CORE

Monday, February 18, 2008

JAL70

1

of

45 10

0.11

5

VGA@

D D

B+

C C

VGA_ON13,28,32

B B

PL31

HCB4532KF-800T90_1812

1 2

PJP24

1 2

PAD-OPEN 4x4m

PR356

22K_0402_1%~D

1 2

VGA@

PC296

@

12

10U_1206_25V6M~D

12

PC303
.1U_0402_16V7K~D

VGA@

12

PC297

VGA@

6269_VGA

12

PC300

2.2U_0603_6.3V6K~D

VGA@

4

6269_B++

6269_VGA

PR352

10K_0402_1%~D

17

GND

COMP5FB6FSET

12

PR359

33K_0402_1%~D

VGA@

12

57.6K_0402_1%

VGA@

12

16

VGA@

1 2

PC304

VGA_PWGOD32

PR363

0_0402_5%~D

VGA@

12

VGA@

68P_0402_50V8J~N

PU24

1

VIN

2

VCC

3

FCCM

4

EN

PC306

2200P_0402_25V7K~N

10U_1206_25V6M~D

PGOOD

15

PR360

PHASE_VGA

14

UG

PHASE

7

12

VGA@

3

PR351

1 2

0_0603_5%~D

VGA@

BOOT_VGA

13

BOOT

PVCC

PGND

ISEN

VO

8

12

+5VS

12

@

12

2.2U_0603_6.3V6K~D

11

LG

10

ISEN_VGA

9

6.49K_0402_1%~D

ISL6269CRZ-T_QFN16_4X4~N

VGA@

PC305

0.01U_0402_25V7K~D

VGA@

UG_VGA

1 2

PC298 0.1U_0603_25V7K~D

PR353
0_0603_5%~D

PR354

4.7_0603_5%

1 2

VGA@

PC299

1 2

LG_VGA

1 2

PR357

VGA@

VGA@

6269_VGA

VGA@

AO4456_SO8

VGA@

VGA@

PQ82

2

1

AO4456
Rds(on)=4.5mohm~5.6mohm

8

D6D5D7D

PQ81

G

3

578

3 6

FDS6294_NL_SO8~D

S

S

S

2

1

1UH_FDUE1040D-1R0M-P3_21.3A_20%

1 2

PR355

4.7_1206_5%~D@

1 2

PC302
680P_0603_50V8J~D@

1 2

241

PL32

VGA@

4

+VGA_COREP
Imax=15A

Iocp=19.5A

1 2

12

PR361

1.87K_0402_1%~D

PR358

2.26K_0402_1%

VGA@

VGA@

1

+

PC301
220U_D2_4VM

VGA@

2

+1.32V

+VGA_COREP

1

+

PC307
220U_D2_4VM

VGA@

2

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2006/10/1 2007/05/30

3

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

2

Date: Sheet

Compal Electronics, Inc.

+VGA_COREP

Monday, February 18, 2008

JAL60

1

of

46 10

0.11

5

4

3

2

1

+1.5VSP+5VALW

VGA@

12

D D

6

PU19

7

POK

VOUT

VCNTL

PR315

SUSP#26,28,31,42

C C

B B

1 2

0_0402_5%~D

VGA@

12

PC269
.1U_0402_16V7K~D

@

PR321

SUSP#26,28,31,42

1 2

0_0402_5%~D

12

PC277
.1U_0402_16V7K~D

@

8

EN

7

8

VOUT

GND

1

APL5913-KAC-TRL_SO8~N

VGA@

PU21

POK

EN

PC263

1U_0603_10V6K~D

5

VIN

3
4
2

FB

9

VIN

12

6

5

VIN

3

VOUT

VCNTL

4

VOUT

2

FB

9

VIN

GND

1

APL5913-KAC-TRL_SO8~N

PR316

VGA@

PC273

1U_0603_10V6K~D

2

2

1

1
12

PC264

12

1K_0402_1%~D

12

PR319

+1.5VSP+5VALW

PR322

1.15K_0402_1%

PJP16

JUMP_43X118@

VGA@

1U_0603_10V6K~D

12

PC265

VGA@

0.01U_0402_25V7K~D

VGA@

2K_0402_1%~D

PJP18

2

JUMP_43X118@

2

1

1
12

PC274

1U_0603_10V6K~D

12

12

PC275

0.01U_0402_25V7K~D

12

PR323

2.05K_0402_1%~D

+1.8V

1

PJP17

1

JUMP_43X118@

2

+1.2VSP

12

PC266

1U_0603_10V6K~D

VGA@

PR318

0_0402_5%~D

SUSP30,31

+1.25VSP

12

PC276

1U_0603_10V6K~D

1 2

PC272

@

.1U_0402_16V7K~D

2

12

PC267

1U_0603_10V6K~D

2

G

12

PQ78

RHU002N06_SOT323

1K_0402_1%~D

13

D

S

PR317

PR320

1K_0402_1%~D

12

12

12

PC270

.1U_0402_16V7K~D

PU20

VIN1VCNTL

2

GND

3

VREF

4

VOUT

APL5331KAC-TRL_SO8~N

+0.9VSP

12

PC271

1U_0603_10V6K~D

6
5

NC

7

NC

8

NC

9

TP

+3VALW

12

PC268

4.7U_0805_6.3V6K~N

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/10/1 2007/05/30

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

+1.25VSP / +0.9VSP/ +1.2VSP

Size Document Number Rev

2

Date: Sheet

JAL60

Monday, February 18, 2008

1

47 50

0.2Custom

of

5

@

D D

DPRSLPVR7,19

H_DPRSTP#5,7,18

CLK_EN#16

+3VS

+3VS

PR157

499_0402_1%~D

VGATE7,19,28

H_PSI#5

POW_MON7,19,28

C C

PR165 4.22K_0402_1%@

VR_TT#

1 2

1U_0603_10V6K~D

100K_0603_1%_TH11-4H104FT@

1 2

PC1280.015U_0402_16V7K@

PC131

1000P_0402_50V7K~D

1 2

PC147

1 2

PR164 147K_0402_1%~D

1 2

PH2

1 2

PR166 11.5K_0402_1%~D

1 2
1 2

PR169 6.81K_0402_1%~D

1 2

12

PR156

1.91K_0402_1%~D

PR181 10K_0402_1%~D

1 2

PC1290.068U_0603_50V7K~N

1 2

PR143 499_0402_1%~D

PR144 0_0402_5%~D

PR145 0_0402_5%~D

1 2

PR154 0_0402_5%~D

1 2

12

PC121

1U_0603_10V6K~D

1
2
3
4
5
6
7
8

9
10
11
12

1 2

1 2

PGOOD
PSI#
PMON
RBIAS
VR_TT#
NTC
SOFT
OCSET
VW
COMP
FB
FB2

1 2

PC132 1000P_0402_50V7K~D

PR175 97.6K_0402_1%~D

1 2

B B

PC137 220P_0402_50V7K~D

PR177

1 2

PR179 1K_0402_1%~D

VCCSENSE5

VSSSENSE5

PC134 470P_0402_50V7K~D

1 2

PC138 1000P_0402_50V7K~D

255_0402_1%~D

1 2

1 2

PR180 0_0402_5%~D

12

1 2

12

PR176
1K_0402_1%~D

PC140 0.022U_0603_25V7K

1 2

12

PC141

0.022U_0603_25V7K

@

1 2

PR183 0_0402_5%~D

PC143 180P_0402_50V8J~D

1 2

1 2

PR186 1K_0402_1%~D

VCC_PRM

A A

PC145

0.22U_0603_16V7K~D

4

PC112

12

5600P_0402_25V7K

48

49

46

47

3V3

GND

CLK_EN#

DPRSTP#

VR_ON

12

PR153

0_0402_5%~D

45

44

VR_ON

DPRSLPVR

ISL6262ACRZ-T_QFN48_7X7

CPU_VID5

CPU_VID6

12

12

PR1460_0402_5%~D

PR1470_0402_5%~D

43

28

CPU_VID45CPU_VID3

12

12

PR1480_0402_5%~D

VDIFF13VSEN14RTN15DROOP16DFB17VO18VSUM19VIN20GND21VDD22ISEN223ISEN1

12

PC139

0.1U_0603_25V7K~D

12

PC142

0.022U_0603_25V7K

VSUM

12

1 2

PR187 3.57K_0402_1%~D

PC144 0.068U_0603_50V7K~N

PC146 0.22U_0603_10V7K~D

12

1 2

PR185

12

5

5

CPU_VID25CPU_VID15CPU_VID0

12

12

12

PR1510_0402_5%~D

PR1490_0402_5%~D

PR1500_0402_5%~D

PR1520_0402_5%~D

VID037VID138VID239VID340VID441VID542VID6

BOOT1
UGATE1
PHASE1

PGND1

LGATE1

PVCC

LGATE2

PGND2
PHASE2
UGATE2

BOOT2

NC

24

1 2

12

PR174 1_0603_5%~D
PC136
1U_0603_10V6K~D

PR178

1 2

10_0603_5%~D

12

PR182

2.61K_0402_1%~D

PH3
10KB_0603_ERTJ1VR103J

11K_0402_1%~D

1 2

3

+5VS

5

5

PR142
1_0603_5%~D

1 2

12

12

36
35
34

BOOT_CPU1

UGATE_CPU1
PHASE_CPU1

12

PC117

0.01U_0402_25V7K~D

PR155

1 2

2.2_0603_5%~D

1 2

2.2_0603_5%~D
PR163

PC118

1U_0603_10V6K~D

PC122

0.22U_0603_10V7K~D

1 2

FDS6676AS_SO8

PC119

PQ44

12

PC120

1U_0603_10V6K~D

0.01U_0402_25V7K~D

5

D8D7D6D

S1S2S3G

4

3 5

241

5

4

33

LGATE_CPU1

32
31
30
29
28
27
26
25

PU11

29.1

ISEN1
ISEN2

BOOT_CPU2

2.2_0603_5%~D

+5VS

+CPU_B+

LGATE_CPU2

PHASE_CPU2

UGATE_CPU2

PR167

1 2

PC130

1 2

0.22U_0603_10V7K~D

PR184

2.2_0603_5%~D

1 2

PQ47

FDS6676AS_SO8

5

4

FDS6676AS_SO8

D8D7D6D

S1S2S3G

3 5

241

5

4

FDS6676AS_SO8

2

12

PC114

10U_1206_25V6M~D

PQ43
SI7686DP-T1-E3_SO8

12

PR158

D8D7D6D

12

PQ45

S1S2S3G

PC123

@

PQ46
SI7686DP-T1-E3_SO8

12

@

D8D7D6D

12

PQ48

S1S2S3G

@

12

PC115

PC116

@

10U_1206_25V6M~D

4.7_1206_5%~D

@

680P_0603_50V8J~D

PC125

PR168

4.7_1206_5%~D

PC133
680P_0603_50V8J~D

+CPU_B+

1

+

PC113

2

100U_25V_M~D

12

PR160

PR162 0_0402_5%~D@

1 2

10K_0402_1%~D

ISEN1

0.22U_0603_16V7K~D

12

PC126

10U_1206_25V6M~D

12

PR170

PR173 0_0402_5%~D@

10K_0402_1%~D

3.65K_1206_1%

0.22U_0603_16V7K~D

ISEN2

1

+

2

12

10U_1206_25V6M~D

P_0.36H_ETQP4LR36WFC_24A_20%

12

PR159

3.65K_1206_1%

VSUM

12

10U_1206_25V6M~D

P_0.36H_ETQP4LR36WFC_24A_20%

12

PR171

VSUM

1

FBMA-L18-453215-900LMA90T_1812

PL13

1 2

PC155

100U_25V_M~D

12

PL14

PC124

1 2

12

PR161

1_0402_5%~D

VCC_PRM

+CPU_B+

12

PC127

@

10U_1206_25V6M~D

12

PL15

12

PR172
1_0402_5%~D

1 2

PC135

1 2

VCC_PRM

B+

+CPU_CORE

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2007/1/15 2008/1/15

3

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

Compal Electronics, Inc.

+CPU_CORE

JAL60

0.1

48 50Monday, February 18, 2008

1

of

5

D D

BATT+

PL28

FBMA-L18-453215-900LMA90T_1812

BATT+

1 2

12

PC278

0.01U_0402_25V7K~D

BATT++

12

PC279
1000P_0402_50V7K~D

BATT++

PJPB1 battery connector

SMART
Battery:

1.BAT+

2.BAT+

3.ID

4.B/I

C C

5.TS

6.SMD

7.SMC

8.GND

9.GND

PJP19

10
11

SUYIN_200275MR009G186ZL

@

GND
GND

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

3cell/4cell#

+3VALWP

1 2

1 2

PR328

100_0402_5%~D

1 2

PR329

100_0402_5%~D

4

@

PD12

DA204U_SOT323~D

PR324
47K_0402_5%~D

3

2

1

PD13

@

3cell/4cell#

EC_SMB_DA1 28

EC_SMB_CK1 28

3

DA204U_SOT323~D

1

PR326

1K_0402_5%~D

3

+3VALWP

2

2

PD14

DA204U_SOT323~D

2

3

1

@

PD15

DA204U_SOT323~D

@

3

1

2

Battery Connect/OTP

1

Place clsoe to EC pin

BATT_TEMP

1 2

PR325

1K_0402_5%~D

12

1 2

PR327

6.49K_0402_1%~D

PC280
.1U_0402_16V7K~D

1 2

@

+3VALWP

BATT_TEMP 28

CPU

PH1 under CPU botten side :

CPU thermal protection at 90 +-3 degree C
Recovery at 50 +-3 degree C

BATT+

12

PR330
453K_0402_1%~D

VS

12

PR332

499K_0402_1%~D

PC282

0.01U_0402_25V7K~D

12

PR337

86.6K_0402_1%

PC283

1000P_0402_50V7K~D

0

8

LM358ADR_SO8

5

P

+

6

-

G

4

12

B B

BATT_OVP28

7

PU22B

VL VS

12

CPU

12

PR331

10.7K_0402_1%~D

PR335

61.9K_0402_1%~D

1 2

1 2

VL

12

PH4
100K_0603_1%_TH11-4H104FT

PR336

150K_0402_1%~D

150K_0402_1%~D

PR338

PR333

147K_0402_1%~D

1 2

12

12

8

3

P

+

0

2

-

G

PU22A

4

LM358ADR_SO8

PC284
1U_0603_10V6K~D

PC281

0.1U_0603_25V7K~D

1 2

1

1 2

1SS355_SOD323-2

PD11

VL

1 2

PR334
205K_0402_1%~D

MAINPWON 41

LI-3S :13.5V----BATT-OVP=1.5V

BATT-OVP=0.111*BATT+

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/10/1 2007/05/30

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

BATTERY CONN

Size Document Number Rev

2

Date: Sheet

JAL60

Monday, February 18, 2008

1

49 50

0.2Custom

of

5

4

3

2

1

Version Change List ( P. I. R. List )

Page 1/1

Request

Item Issue DescriptionDate

1

D D

2

3

4

5

6

7

8
9

10

11

C C

12

ALL ALL Page 07/11/30 DELL base on customer request change SD SE to *L part

P41 +3VALWP/+5VALWP 07/12/11 COMPAL When battery only and 4s shut down the system can not turn off the 3valwp

P41 +3VALWP/+5VALWP 07/12/11 COMPAL in order to trial run ISL6237 2'nd source,reserve PC239 in ISL6237 PIN5. ADD PC239 (1U 0603 10V)

P44 +VGA_CORE 07/12/11 COMPAL Base on HW power budger,change the VGA_CORE high low side MOS and choke. change PQ81 from AO4466 to FDS6294,PQ82 from AO4712 to AO4456,PL32

P39 DC-IN / Precharge 07/12/11 COMPAL base on customer spec no need CHARGE RTC, delete CHARGE RTC limit resister Del PR210,PR211

P46 CPU_CORE 07/12/14 COMPAL EMI request to increase resister in CPU_CORE low side mos gate pin ADD PR163(2.2 ohm),PR184(2.2ohm)

P43 1.8VP 07/12/14 COMPAL EMI request to increase resister in 1.8VP BOOT pin Change PR340 from 0 ohm to 2.2 ohm

P40 CHARGER 08/01/04 COMPAL disable BQ24751 VIN detecte function CHANGE PQ62 to @ and PR232 to @

P40 CHARGER 08/02/12 COMPAL EC have drop volotage in CHGVADJ,it will make the charge voltage not correct CHANGE PR53 from 4.3k to 210k and PR54 from 10k to 499k

P44 +VGA_CORE COMPAL Base on HW power budger,change the VGA_CORE output capacity change PC301,PC307 from

08/02/12

Owner

and 5valwp

ADD PD16 (RB751V),PQ76(TP0610K)

from 1.8uH 9.5A to 1uH 21.3A

SF22001M300 S ELE CAP 220U 6.3V M F60(6.3X5.7) PXC to
SGA20221150 S POLY C 220U 4V M D2 PSL LESR15M H1.9

Solution Description Rev.Page# Title

ALL SD* SE*

ADD PR53(4.3K) PR54 PR51P40 CHARGER 07/12/11 COMPAL in order to meet the JETA rule,the charge voltage will be auto adjust by EC

B B

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2007/1/15 2008/1/15

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

Compal Electronics, Inc.

PW PIR-1

JAL60

0.1

of

50 50Monday, February 18, 2008

1

5

4

3

2

1

Version Change List ( P. I. R. List )

Page 1/1

Request

Item Issue DescriptionDate

1

D D

2

3

4

5

6

7

8

9

10

11

12

C C

13

14

15

16

17

18

19

20

21

22

28 EC_KB926/Reed Switch/BIOS/TPM 2007/11/14 Compal_HW Change Board ID. Change R459 to 8.2K ohm. 0.2

38 NB8P-SE_Straps 2007/11/14 There is display issue on Discrete platform. Not stuff R784. 0.2

32 DC/DC Interface Sometime system can't detect USB device.2007/11/19 Change R522 pull high to +5VALW. ( for SUSP ) 0.2

CRT Conn/LCD Conn

25 OZ129_Card Reader/1394 OZ129 has power sequence and leakage issue. 2007/12/03 Compal_HW Update the circuit of OZ129 on Page 25.

28 Can't Wake up on LAN. Change R464 pull high to +3VALW for WOL.2007/12/03 Compal_HWEC_KB926/Reed Switch/BIOS/TPM

28 Support Wake up from USB Port and replace USB HUB port arrangement. Add USB_EN# to enable USB power swith.Compal_HWEC_KB926/Reed Switch/BIOS/TPM 2007/12/03

29 51ON# shout down issue. Change R493 pull down to GND and del R494.Compal_HWPWR_OK/BTN/KB/TP 2007/12/13

29 Int. Keyboard can't work. Modify the pin definition of JKB1.2007/12/03 Compal_HWPWR_OK/BTN/KB/TP

30 2007/12/03USB/1394 Conn Compal_HW Support Wake up from USB Port.

32 VGA_PWGOD sequence issue. 1.Change R551 pull high to +5VALW and don't stuff R551.DC/DC Interface 2007/12/03 Compal_HW

15 Dell 17" LCD Panel gray color issue. Add Q83, Q84, R942, R943, C1191~C1194 for Dell 17" panel.2007/12/13 Compal_HWCRT Conn/LCD Conn

22 These is EMI issue on Transformer.

22

31 USB Hub/Camera/Felcia/FP/BT

Realtek RTL8111C-GR

Realtek RTL8111C-GR

CRT Conn/LCD Conn

2007/12/03 Compal_HW15 Support BIST and LCD detect function for LCD panel. Add nets: LCD_DET# , BIST and Modify the pin definition of JP4.

2007/12/0323 There are EMI issue on DMIC_DATA and DMIC_CLK. Add R933, R934, C1189, C1190 for EMI.Audio Codec_ALC268 Compal_EMI

2007/12/13

2007/12/18

2007/12/19

2007/12/24 Compal_HW Modify the definition of JFP1.Finfer Print assermble FFC.

Owner

Compal_HW

Compal_HW

Compal_EMI

Compal_HW

Compal_EMI15

RJ-45: LED support "link" and "activity" status.

EMI' request.

1.U32, U33, U34, U51 change input voltage to +5VALW.

2.JUSBP1~5 change USB differential pair from ICH8M.

2.Change VGA_PWGOD to PR352 pin2.

Add R945~R952 and C1195~C1198 for EMI.

1.Change the connector of JLAN1.

2.Add D41, D42, D43, D44, R953, R954, R955.
Del CRT_GND, R105, R107 for EMI.

Solution Description Rev.Page# Title

0.2

0.2

0.2

0.2

0.2

0.2

0.2

0.2

0.2

0.2

0.2

0.2

0.2

B B

23

24

25

26

27

28

29

30

31

32

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2007/12/28 2007/12/28

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

EE_PIR-1

Size Document Number Rev

Custom

LA-4131P

2

Date: Sheet

51 53Monday, February 18, 2008

1

0.2

of

5

4

3

2

1

JAL60 Power Block

RTC Charger

D D

Battery OVP

Vin Detector

Page 41

Input

DC IN

C C

CHARGER

Switch

Turn Off

Page 41

Page 49

+CHGRTC

B+

CC:
CV:
( BQ24751ARHDR )

Page 42

Battery

Page 42

CPU OTP

Page 49

Turn Off

+3VALWP: OCP: 10.133A OVP: 107%~115%
+5VALWP: OCP: 10.146A OVP: 107%~115%
( ISL6237IRZ-T )

+VCCPP: OCP: 9A OVP: 110%~115%
+1.5VSP: OCP: 9A OVP: 110%~115%
( ISL6228HRTZ-T )

+1.5VSP

+1.2VSP
Thermal protection: 160 degree C
( APL5913-KAC-TRL )

+1.5VSP

+1.25VSP
Thermal protection: 160 degree C
( APL5913-KAC-TRL )

Page 43

Page 44

Page 47

Page 47

+3VALWP: 2VREF_ISL6237

+5VALWP: MAINPWON

+VCCPP: SUSP#

+1.5VSP: 1.5V_EN ( SUSP# )

SUSP#

SUSP#

B B

CPU CORE

VR_ON

OCP:54A
OVP:2V
( ISL6262ACRZ-T )

A A

5

Page 48

4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

+1.8VP: OCP: 12.6A OVP: 110%~115%
( ISL6269CRZ-T )

+1.8V

+0.9VSP
Thermal protection: 160 degree C
( APL5331KAC-TRL )

+VGA_COREP: OCP: 19.5A OVP: 110%~115%
( ISL6269CRZ-T )

2007/12/28 2007/12/28

3

Compal Secret Data

Deciphered Date

2

SYSON

Page 45

SUSP

Page 47

VGA_ON

Page 46

Compal Electronics, Inc.

Title

Power Block

Size Document Number Rev

Custom

LA-4131P

Date: Sheet

1

52 53Monday, February 18, 2008

0.2

of

5

4

3

2

1

ACIN/BATT-IN

+5VALW/+3VALW

EC_ON

D D

ON/OFF

STB_SB (Control +3V_SB)

+3V_SB

RSMRST#

T1>20ms

WOL_EN(Control +3VLAN)

+3VLAN

SYSON(Control +3V/+1.8V)

C C

+3V/1.8V

T2=40ms

PWRBTN_OUT#

SLP_S5#

T3<110ms

SLP_S4#

SLP_S3#

SUSP#

T4=20ms

+5VS>3VS>1.5VS>1.25VS>+1.2VS>VCCP>0.9VS

VR_ON#/VGA_ON

B B

+CPU_CORE

VGATE(IMVP to SB for VRMPWRGD/to EC for CPUCORE PWRGD)

CK_PWRGD(SB to CLK-GEN; Local AND of VRMPWRGD and S3 )

PM_PWROK(EC to SB/NB)

T5>30ms

T8>99ms

T9>3ms

T6= ~7ms

100ns>T7>0ns

T10>70ms

H_PWRGOOD(SB to CPU; Local AND of VRMPWRGD and PWROK)

PLTRST#(SB to NB/Device)

H_RESET#(NB to CPU)

A A

VGA_ON

T13>30ms

41RTCCLK>T11>34RTCCLK

T12>1ms

+VGA_CORE

VGA_PWGOD(Turn on 1.8VS for VRAM/VGA)

T14= ~7ms

+1.8VS

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Compal Secret Data

2007/12/28 2007/12/28

2

Deciphered Date

Compal Electronics, Inc.

Title

Power On Sequence

Size Document Number Rev

Custom

LA-4131P

Date: Sheet

1

53 53Monday, February 18, 2008

of

0.2