COMPAL LA-4105P Schematics

A
1 1
B
C
D
E
Compal confidential
2 2
Schematics Document
Mobile Penryn uFCPGA with Intel Cantiga_GM+ICH9-M core logic
2009-07-15
3 3
Blade 1.4 MV
4 4
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2007/08/28 2006/03/10
2007/08/28 2006/03/10
2007/08/28 2006/03/10
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
D
Date: Sheet
Compal Electronics, Inc.
Cover Sheet
Cover Sheet
Cover Sheet
Montevina Blade UMA LA4105P
Montevina Blade UMA LA4105P
Montevina Blade UMA LA4105P
E
1.0
1.0
1 45Saturday, July 18, 2009
1 45Saturday, July 18, 2009
1 45Saturday, July 18, 2009
1.0
of
of
of
A
B
C
D
E
Compal confidential
1 1
LVDS Panel Interface
CRT
Support V1.3
2 2
PCIE CardReader JMB385
P27
RTL8103EL (10/100M)
HDMI
P25
P19
P18
P35
Mini-Card
WLAN
Thermal Sensor EMC1402
Fan conn
Mini-Card
TV-tuner or Robson
Montevina Consumer 14" UMA
Mobile Penryn
P06
P06
PCI-E BUS*5
New Card
P26P26
DMI X4
P26
uFCPGA-478 CPU
P6, 7, 8
H_A#(3..35)
H_D#(0..63)
FSB
667/800/1066 MHz 1.05V
Intel Cantiga MCH
FCBGA 1329
P9,10, 11, 12, 13, 14
Intel ICH9-M
mBGA-676
P20,21,22,23
DDR3 800/1066MHz
1.5V
Dual Channel
USB2.0 X12
C-Link
Azalia
SATA Master-1
SATA Slave
SATA Slave
CK505
72QFN
Clock Generator SLG8SP553V
DDR3 SO-DIMM X2
BANK 0, 1, 2, 3
USB conn x1
BT Conn
USB Camera
Finger print
Codec_IDT9271B7
P17
P15, 16
P30
P30
P19
P30
Audio CKT AMP & Audio Jack
P28 P29
TPA6017A2
5 in1 Slot
3 3
RJ45/11 CONN
P33
P25
LPC BUS
MDC
P29
SATA HDD Connector
P24
ENE
RTC CKT.
ACCELEROMETER-1 ST
ACCELEROMETER-2 BOSCH
4 4
K/B backlight Conn
P21
LED
P33
P24
P24
P33
Dock
USB2.0*1
RGB
RJ45
SPDIF
MIC*1
LINE-OUT*1
Touch Pad CONN.
P33
DC/DC Interface CKT.
P36
A
P34
B
KB926
SPI ROM SST25VF080
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
P31
C
SPI
P32
Int.KBD
P32
2006/02/13 2006/03/10
2006/02/13 2006/03/10
2006/02/13 2006/03/10
Deciphered Date
Deciphered Date
Deciphered Date
SATA ODD Connector
e-SATA Connector
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
D
Date: Sheet
P24
P30
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Block Diagram
Block Diagram
Block Diagram
Montevina Blade UMA LA4105P
Montevina Blade UMA LA4105P
Montevina Blade UMA LA4105P
USB Board Conn USB conn x2
P30
Audio board
CIR Conn
Capsense switch Conn
2 45Saturday, July 18, 2009
2 45Saturday, July 18, 2009
2 45Saturday, July 18, 2009
E
P29
P33
of
of
of
1.0
1.0
1.0
A
Symbol Note :
Voltage Rails
power plane
State
S0
S1
S3
S5 S4/AC
S5 S4/ Battery only
S5 S4/AC & Battery don't exist
1 1
O MEANS ON X MEANS OFF
+B
O
O
O
O
O
+5VALW
+3VALW
O
O
O
O
X
XX
+1.8V
: means Digital Ground
: means Analog Ground
+5VS
+3VS
+1.5VS
+0.9V
+VCCP
+CPU_CORE
+2.5VS
+1.8VS
O
O
O
X
X
X
O
O
X
X
X
X
@ : means just reserve , no build
45@ : means need be mounted when 45 level assy or rework stage.
DEBUG@ : means just reserve for debug.
BATT @ : means need be mounted when 45 level assy or rework stage.
CONN@ : means ME part
ESATA @ : means just reserve for ESATA
GS @ : means just reserve for G sensor
FP @ : means just reserve for Finger Print
Multi @ : means just reserve for Multi Bay
NewC@ : means just reserve for New card
DOCK@ : means just reserve for Docking
Main@ : means just reserve for Main stream
OPP@ : means just reserve for OPP
2MiniC@ : means just reserve for 2nd Mini card slot
PA @ : means just reserve for PA
PR @ : means just reserve for PR
USB assignment:
USB-0 Right side
USB-1 Right side
USB-2 Left side(with ESATA)
USB-3 Dock
USB-4 Camera
USB-5 WLAN
USB-6 Bluetooth
USB-7 Finger Printer
USB-8 MiniCard(WWAN/TV)
USB-9 Express card
USB-10 X
USB-11 X
PCIe assignment:
PCIe-1 TV /WWAN/Robeson
PCIe-2 X
PCIe-3 WLAN
PCIe-4 GLAN (Realtek)
PCIe-5 Card reader
PCIe-6 New Card
I2C / SMBUS ADDRESSING
HEX
A0
D2
ADDRESS
1 0 1 0 0 0 0 0
1 0 1 0 0 1 0 0A4
1 1 0 1 0 0 1 0
DEVICE
DDR SO-DIMM 0
DDR SO-DIMM 1
CLOCK GENERATOR (EXT.)
SMBUS Control Table
SMB_EC_CK1
SMB_EC_DA1
SMB_EC_CK2
SMB_EC_DA2
SMB_CK_CLK1
SMB_CK_DAT1
LCD_CLK
LCD_DAT
SOURCE
KB926
KB926
ICH9
Cantiga
INVERTER BATT
X V
X
X
X
X
X
X
SERIAL EEPROM
V
X
X
X
Thermal Sensor
X
V
X
X
SODIMM CLK CHIP
X
X
X
X
V V V
X
X
MINI CARD
X
X
X
LCD
X
X
X
V
Cap sensor board
V
X
X
X
NEW CARD G sensor
X X
X
X
V V
X
X
43154432L01 43154432L02 43154432L03 43154432L04 43154432L05
Cantiga GM45 B0(QR32) ICH9M A2 ES2 Base Cantiga GM45 B-2 QS QT62 Cantiga GM45 B-3 QS QU36 ICH9M A-3 QS - BASE QT09 Cantiga GM45 B-3 QS SLB97 ICH9M A-3 QS -BASE SLB8Q
::::
UMA GM PA FF (V)
::::
UMA GM PR FF (V)
::::
UMA GL PR FF-
::::
UMA GM OPP (V)
::::
UMA GL OPP
::::
::::
SA00001P930 (SI-1
SA00002AN10 (SI-1
:::: :::: ::::
::::
::::
、、、、
SI-2)
、、、、
SI-2) SA00002JT10 (PV-1) SA00002JT50 (PV-2) SA00002JH00 (PV-1
SA00002JJE0 (MV-1
SA00002JHB0 (MV-1
、、、、
、、、、
、、、、
PV-2)
MV-2)
MV-2)
43154432L01 43154432L02 43154432L03 43154432L04 43154432L05
::::
Main@/DEBUG@/DOCK@/NewC@/FP@/ESATA@/GS@/Multi@/2MiniC@/PA@
::::
Main@/DEBUG@/DOCK@/NewC@/FP@/ESATA@/GS@/PR@
::::
Main@/DEBUG@/DOCK@/NewC@/FP@/PR@
::::
OPP@/DEBUG@/PR@
::::
OPP@/DEBUG@/PR@
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
::::
DA600007110 --->M/B
PCB DAZ03V00200 --->Main DAZ03V00101 --->OPP
2007/08/28 2006/03/10
2007/08/28 2006/03/10
2007/08/28 2006/03/10
A
Deciphered Date
Deciphered Date
Deciphered Date
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
Date: Sheet
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Notes List
Notes List
Notes List
Montevina Blade UMA LA4105P
Montevina Blade UMA LA4105P
Montevina Blade UMA LA4105P
1.0
1.0
3 45Saturday, July 18, 2009
3 45Saturday, July 18, 2009
3 45Saturday, July 18, 2009
1.0
of
of
of
5
4
3
2
60mA
+3VAUX_BT
1
50mA
1A
D D
VIN
AC
+V_BATTERY Dock con
0.3A
INVPWR_B+
2A
B++
LVDS CON
1.7A
+3VALW
35mA
177mA
300mA
550mA
MDC 1.5
ICH9
LAN
JMB385
3.39A5.89A
+3VS
25mA
20mA
10mA
1A
278mA
1.5A
250mA
C C
+1.5VS
B+
+5VALW
2.2A0.3A
1.3A0.58A
657mA
1.56A
7A
ICH_VCC1_5 ICH9
ICH9
+5VS
35mA
10mA
1A
1A
+VDDA IDT 9271B7
+5VAMP
Finger printer
+3VS_DVDD ALC268
+3VALW_EC
SPI ROM
New card
ICH9
+LCDVDD
LVDS CON
+3VS_CK505
Mini card (WLAN)
Mini card (TV tu/WWAN/Robeson)
1.8A
700mA
B B
3.7 X 3=11.1V
BATT
DC
B+++
A A
5
CPU_B+ +VCC_CORE
12.11A1.9A
4.7A
10mA2A
+1.8V
1.05V_B+
34A/1.025V
4
3.7A
8 A
50mA
+VCCP
CPU
MCH
DDR2 800Mhz 4G x2
1.8A
50mA
+0.9V
1.17A
1.26A
2.3A
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
ICH9
MCH
CPU
Compal Secret Data
Compal Secret Data
2007/08/28 2006/03/10
2007/08/28 2006/03/10
2007/08/28 2006/03/10
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
ODD
SATA
Muti Bay
PC Camera(4.75V)
2
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
C
C
C
Montevina Blade UMA LA4105P
Montevina Blade UMA LA4105P
Montevina Blade UMA LA4105P
Date: Sheet
Date: Sheet
Date: Sheet
Power delevry
Power delevry
Power delevry
1
4 45Saturday, July 18, 2009
4 45Saturday, July 18, 2009
4 45Saturday, July 18, 2009
of
of
of
1.0
1.0
1.0
A
1 1
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
2007/08/28 2006/03/10
2007/08/28 2006/03/10
2007/08/28 2006/03/10
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
Date: Sheet
Compal Electronics, Inc.
Notes List
Notes List
Notes List
Montevina Blade UMA LA4105P
Montevina Blade UMA LA4105P
Montevina Blade UMA LA4105P
5 45Saturday, July 18, 2009
5 45Saturday, July 18, 2009
5 45Saturday, July 18, 2009
of
of
of
1.0
1.0
1.0
5
D D
4
3
ITP-XDP Connector
PV::: follow check list ver:1.5 change to 51 ohm
04/29 MV1 R2~R8 change to 54.9 Ohm, follow checklist 2.0
2
XDP_DBRESET#
Change value in 5/02
XDP_TDI
XDP_TMS
XDP_TDO
R2 54.9_0402_1%R2 54.9_0402_1%
R3 54.9_0402_1%R3 54.9_0402_1%
R4 54.9_0402_1%R4 54.9_0402_1%
R1
@R1
@
1 2
1 2
1 2
1 2
1
1K_0402_5%
1K_0402_5%
+3VS
+VCCP
H_A#[3..16]<9>
H_ADSTB#0<9>
H_REQ#0<9> H_REQ#1<9> H_REQ#2<9> H_REQ#3<9> H_REQ#4<9>
C C
B B
A A
H_A#[17..35]<9>
H_ADSTB#1<9>
H_A20M#<21>
H_FERR#<21>
H_IGNNE#<21>
H_STPCLK#<21> H_INTR<21> H_NMI<21> H_SMI#<21>
+VCCP
B
B
E
H_PROCHOT# OCP#
H_IERR#
E
3 1
Q1
@
Q1
@
MMBT3904_NL_SOT23-3
MMBT3904_NL_SOT23-3
+VCCP
12
@
@
R17
R17 56_0402_5%
56_0402_5%
2
C
C
R18
R18 56_0402_5%
56_0402_5%
1 2
5
H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16 H_ADSTB#0
H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4
H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 H_A#32 H_A#33 H_A#34 H_A#35 H_ADSTB#1
H_A20M# H_FERR# H_IGNNE#
H_STPCLK# H_INTR H_NMI H_SMI#
JCPU1A
JCPU1A
J4
A[3]#
L5
A[4]#
L4
A[5]#
K5
A[6]#
M3
A[7]#
N2
A[8]#
J1
A[9]#
N3
A[10]#
P5
A[11]#
P2
A[12]#
L2
A[13]#
P4
A[14]#
P1
A[15]#
R1
A[16]#
M1
ADSTB[0]#
K3
REQ[0]#
H2
REQ[1]#
K2
REQ[2]#
J3
REQ[3]#
L1
REQ[4]#
Y2
A[17]#
U5
A[18]#
R3
A[19]#
W6
A[20]#
U4
A[21]#
Y5
A[22]#
U1
A[23]#
R4
A[24]#
T5
A[25]#
T3
A[26]#
W2
A[27]#
W5
A[28]#
Y4
A[29]#
U2
A[30]#
V4
A[31]#
W3
A[32]#
AA4
A[33]#
AB2
A[34]#
AA3
A[35]#
V1
ADSTB[1]#
A6
A20M#
A5
FERR#
C4
IGNNE#
D5
STPCLK#
C6
LINT0
B4
LINT1
A3
SMI#
M4
RSVD[01]
N5
RSVD[02]
T2
RSVD[03]
V3
RSVD[04]
B2
RSVD[05]
D2
RSVD[06]
D22
RSVD[07]
D3
RSVD[08]
F6
RSVD[09]
Penryn
Penryn
OCP# <22>
ADDR GROUP_0
ADDR GROUP_0
ADDR GROUP_1
ADDR GROUP_1
THERMAL
THERMAL
ICH
ICH
THERMTRIP#
RESERVED
RESERVED
ADS# BNR# BPRI#
DEFER#
DRDY# DBSY#
BR0#
IERR#
INIT#
LOCK#
CONTROL
CONTROL
RESET#
RS[0]# RS[1]# RS[2]#
TRDY#
HIT#
HITM#
BPM[0]# BPM[1]# BPM[2]# BPM[3]#
PRDY# PREQ#
TCK
TDO TMS
TRST#
DBR#
XDP/ITP SIGNALS
XDP/ITP SIGNALS
PROCHOT#
THERMDA THERMDC
H CLK
H CLK
BCLK[0] BCLK[1]
H_ADS#
H1
H_BNR#
E2
H_BPRI#
G5
H_DEFER#
H5
H_DRDY#
F21
H_DBSY#
E1
H_BR0#
F1
H_IERR#
D20
H_INIT#
B3
H_LOCK#
H4
H_RESET#
C1
H_RS#0
F3
H_RS#1
F4
H_RS#2
G3
H_TRDY#
G2
H_HIT#
G6
H_HITM#
E4
AD4 AD3 AD1 AC4 AC2 AC1
XDP_TCK
AC5
XDP_TDI
AA6
TDI
XDP_TDO
AB3
XDP_TMS
AB5
XDP_TRST#
AB6
XDP_DBRESET#
C20
H_PROCHOT#
D21 A24
H_THERMDC_R
B25
H_THERMTRIP#
C7
CLK_CPU_BCLK
A22
CLK_CPU_BCLK#
A21
For Merom, R14 and R15 are 0ohm For Penryn, R14 and R15 are 100ohm.
04/29 MV1 change R14、、、R15 to 0 ohm
4
H_ADS# <9> H_BNR# <9>
H_BPRI# <9>
H_DEFER# <9> H_DRDY# <9> H_DBSY# <9>
H_BR0# <9>
H_INIT# <21>
H_LOCK# <9>
H_RESET# <9>
H_RS#0 <9>
H_RS#1 <9>
H_RS#2 <9>
H_TRDY# <9>
H_HIT# <9> H_HITM# <9>
T1T1
Place TP with a GND 0.1" away
PV:::Checklist Ver 1.5 change to 56 ohm
XDP_DBRESET# <22>
R13 56_0402_1%R13 56_0402_1%
1 2
R14 0_0402_5%R14 0_0402_5%
1 2
R15 0_0402_5%R15 0_0402_5%
1 2
H_THERMTRIP# <9,21>
CLK_CPU_BCLK <17> CLK_CPU_BCLK# <17>
H_THERMDA, H_THERMDC routing together, Trace width / Spacing = 10 / 10 mil
+VCCP
03/18 PV:::Delete XDP connector
+3VS
1
C2
2
+5VS
D1
D1
2
1
G
G
4 5
1
2
3
4
2 1
6
D
D
Q2
Q2
S
S
SI3456BDV-T1-E3_TSOP6
SI3456BDV-T1-E3_TSOP6
H_THERMDAH_THERMDA_R H_THERMDC
+3VS
0.1U_0402_16V4ZC20.1U_0402_16V4Z
C3
C3
1 2
2200P_0402_50V7K
2200P_0402_50V7K
R16
R16
1 2
10K_0402_5%
10K_0402_5%
H_THERMDA
H_THERMDC
THERM#
PWM Fan Control circuit
RB751V_SOD323
RB751V_SOD323
FAN_PWM<32>
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2007/08/28 2006/03/10
2007/08/28 2006/03/10
2007/08/28 2006/03/10
Deciphered Date
Deciphered Date
Deciphered Date
3
2
U1
U1
VDD
DP
DN
THERM#
EMC1402-1-ACZL-TR_MSOP8
EMC1402-1-ACZL-TR_MSOP8
Address:100_1100
1
C4
C4
4.7U_0805_10V4Z
4.7U_0805_10V4Z
2
XDP_TRST#
XDP_TCK
SMCLK
SMDATA
ALERT#
GND
+FAN
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
Date: Sheet
R7 54.9_0402_1%R7 54.9_0402_1%
1 2
R8 54.9_0402_1%R8 54.9_0402_1%
1 2
This shall place near CPU
SMB_EC_CK2
8
SMB_EC_DA2
7
R6 10K_0402_5%
R6 10K_0402_5%
6
1 2
5
04/29 MV1 reserve 10K for 2nd source
11/01 update
1
1
C5
C5
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
12
D2
@D2
@
RLZ5.1B_LL34
RLZ5.1B_LL34
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Penryn(1/3)-AGTL+/ITP-XDP
Penryn(1/3)-AGTL+/ITP-XDP
Penryn(1/3)-AGTL+/ITP-XDP
Montevina Blade UMA LA4105P
Montevina Blade UMA LA4105P
Montevina Blade UMA LA4105P
2
3 4
Change PCB Footprint from ACES_85204-02001_2P to ACES_88231-02001_2P
1
SMB_EC_CK2 <32>
SMB_EC_DA2 <32>
+3VS
JP2
JP2
1 2
GND GND
ACES_88231-02001
ACES_88231-02001
CONN@
CONN@
6 45Saturday, July 18, 2009
6 45Saturday, July 18, 2009
6 45Saturday, July 18, 2009
of
of
of
1.0
1.0
1.0
5
4
3
2
1
H_D#[0..15]<9>
D D
H_DSTBN#0<9> H_DSTBP#0<9> H_DINV#0<9> H_D#[16..31]<9>
C C
* Route the TEST3 and TEST5 signals through a ground referenced Zo = 55-ohm trace that ends in a via that is near a GND via and is accessible through an oscilloscope connection.
B B
CPU_BSEL CPU_BSEL2 CPU_BSEL1
R21 1K_0402_5%@R21 1K_0402_5%@ R22 1K_0402_5%@R22 1K_0402_5%@
166
H_DSTBN#1<9> H_DSTBP#1<9> H_DINV#1<9>
1 2 1 2
CPU_BSEL0<17> CPU_BSEL1<17>
T2T2 T3T3 T4T4 T5T5 T6T6
0 1
200
266
0 0
H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 H_DSTBN#0 H_DSTBP#0 H_DINV#0
H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31 H_DSTBN#1 H_DSTBP#1 H_DINV#1
+V_CPU_GTLREF
TEST1 TEST2 TEST3 TEST4 TEST5 TEST6 TEST7 CPU_BSEL0 CPU_BSEL1 CPU_BSEL2
10
JCPU1B
JCPU1B
E22
D[0]#
F24
D[1]#
E26
D[2]#
G22
D[3]#
F23
D[4]#
G25
D[5]#
E25
D[6]#
E23
D[7]#
K24
D[8]#
G24
D[9]#
J24
D[10]#
J23
D[11]#
H22
D[12]#
F26
D[13]#
K22
D[14]#
H23
D[15]#
J26
DSTBN[0]#
H26
DSTBP[0]#
H25
DINV[0]#
N22
D[16]#
K25
D[17]#
P26
D[18]#
R23
D[19]#
L23
D[20]#
M24
D[21]#
L22
D[22]#
M23
D[23]#
P25
D[24]#
P23
D[25]#
P22
D[26]#
T24
D[27]#
R24
D[28]#
L25
D[29]#
T25
D[30]#
N25
D[31]#
L26
DSTBN[1]#
M26
DSTBP[1]#
N24
DINV[1]#
AD26
GTLREF
C23
TEST1
D25
TEST2
C24
TEST3
AF26
TEST4
AF1
TEST5
A26
TEST6
C3
TEST7
B22
BSEL[0]
B23
BSEL[1]
C21
BSEL[2]
Penryn
Penryn
CPU_BSEL0
H_D#32
Y22
MISC
MISC
DATA GRP 0
DATA GRP 0
DATA GRP 1
DATA GRP 1
D[32]# D[33]# D[34]# D[35]# D[36]# D[37]# D[38]# D[39]# D[40]#
DATA GRP 2DATA GRP 3
DATA GRP 2DATA GRP 3
D[41]# D[42]# D[43]# D[44]# D[45]# D[46]#
D[47]# DSTBN[2]# DSTBP[2]#
DINV[2]#
D[48]#
D[49]#
D[50]#
D[51]#
D[52]#
D[53]#
D[54]#
D[55]#
D[56]#
D[57]#
D[58]#
D[59]#
D[60]#
D[61]#
D[62]#
D[63]# DSTBN[3]# DSTBP[3]#
DINV[3]#
COMP[0] COMP[1] COMP[2] COMP[3]
DPRSTP#
DPSLP#
DPWR#
PWRGOOD
SLP# PSI#
AB24 V24 V26 V23 T22 U25 U23 Y25 W22 Y23 W24 W25 AA23 AA24 AB25 Y26 AA26 U22
AE24 AD24 AA21 AB22 AB21 AC26 AD20 AE22 AF23 AC25 AE21 AD21 AC22 AD23 AF22 AC23 AE25 AF24 AC20
R26 U26 AA1 Y1
E5 B5 D24 D6 D7 AE6
H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 H_DSTBN#2 H_DSTBP#2 H_DINV#2
H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63 H_DSTBN#3 H_DSTBP#3 H_DINV#3
COMP0 COMP1 COMP2 COMP3
H_DPRSTP# H_DPSLP# H_DPWR# H_PWRGOOD H_CPUSLP# H_PSI#
1
0
0
H_D#[32..47] <9>
H_DSTBN#2 <9> H_DSTBP#2 <9> H_DINV#2 <9> H_D#[48..63] <9>
H_DSTBN#3 <9> H_DSTBP#3 <9> H_DINV#3 <9>
H_DPRSTP# <9,21,43>
H_DPSLP# <21> H_DPWR# <9> H_PWRGOOD <21>
H_CPUSLP# <9> H_PSI# <43>CPU_BSEL2<17>
R24
R24
R23
R23
12
54.9_0402_1%
54.9_0402_1%
Resistor placed within 0.5" of CPU pin.Trace should be at least 25 mils away from any other toggling signal. COMP[0,2] trace width is 18 mils. COMP[1,3] trace width is 4 mils.
+V_CPU_GTLREF
27.4_0402_1%
27.4_0402_1%
12
+VCCP
R25
R25
12
54.9_0402_1%
54.9_0402_1%
12
R27
R27 1K_0402_1%
1K_0402_1%
12
R29
R29 2K_0402_1%
2K_0402_1%
27.4_0402_1%
27.4_0402_1%
+VCC_CORE +VCC_CORE
R26
R26
12
AA10 AA12 AA13 AA15 AA17 AA18 AA20
AC10 AB10 AB12 AB14 AB15 AB17 AB18
JCPU1C
JCPU1C
A7
VCC[001] VCC[002] VCC[003] VCC[004] VCC[005] VCC[006] VCC[007] VCC[008] VCC[009] VCC[010] VCC[011] VCC[012] VCC[013] VCC[014] VCC[015] VCC[016] VCC[017] VCC[018] VCC[019] VCC[020] VCC[021] VCC[022] VCC[023] VCC[024] VCC[025] VCC[026] VCC[027] VCC[028] VCC[029] VCC[030] VCC[031] VCC[032] VCC[033] VCC[034] VCC[035] VCC[036] VCC[037] VCC[038] VCC[039] VCC[040] VCC[041] VCC[042] VCC[043] VCC[044] VCC[045] VCC[046] VCC[047] VCC[048] VCC[049] VCC[050] VCC[051] VCC[052] VCC[053] VCC[054] VCC[055] VCC[056] VCC[057] VCC[058] VCC[059] VCC[060] VCC[061] VCC[062] VCC[063] VCC[064] VCC[065] VCC[066] VCC[067]
Penryn
Penryn
VCC[068] VCC[069] VCC[070] VCC[071] VCC[072] VCC[073] VCC[074] VCC[075] VCC[076] VCC[077] VCC[078] VCC[079] VCC[080] VCC[081] VCC[082] VCC[083] VCC[084] VCC[085] VCC[086] VCC[087] VCC[088] VCC[089] VCC[090] VCC[091] VCC[092] VCC[093] VCC[094] VCC[095] VCC[096] VCC[097] VCC[098] VCC[099] VCC[100]
VCCP[01] VCCP[02] VCCP[03] VCCP[04] VCCP[05] VCCP[06] VCCP[07] VCCP[08] VCCP[09] VCCP[10] VCCP[11] VCCP[12] VCCP[13] VCCP[14] VCCP[15] VCCP[16]
VCCA[01] VCCA[02]
VCCSENSE
VSSSENSE
A9 A10 A12 A13 A15 A17 A18 A20
B7
B9 B10 B12 B14 B15 B17 B18 B20
C9 C10 C12 C13 C15 C17 C18
D9 D10 D12 D14 D15 D17 D18
E7
E9 E10 E12 E13 E15 E17 E18 E20
F7
F9 F10 F12 F14 F15 F17 F18 F20 AA7 AA9
AB9
AB20 AB7 AC7 AC9 AC12 AC13 AC15 AC17 AC18 AD7 AD9 AD10 AD12 AD14 AD15 AD17 AD18 AE9 AE10 AE12 AE13 AE15 AE17 AE18 AE20 AF9 AF10 AF12 AF14 AF15 AF17 AF18
VID[0] VID[1] VID[2] VID[3] VID[4] VID[5] VID[6]
AF20
+VCCPA
G21
+VCCPB
V6 J6 K6 M6 J21 K21 M21 N21 N6 R21 R6 T21 T6 V21 W21
B26 C26
AD6 AF5 AE5 AF4 AE3 AF3 AE2
AF7
AE7
.
.
VCCSENSE
VSSSENSE
R19
R19
1 2 1 2
R20
R20
0_0402_5%
0_0402_5% 0_0402_5%
0_0402_5%
CPU_VID0 <43> CPU_VID1 <43> CPU_VID2 <43> CPU_VID3 <43> CPU_VID4 <43> CPU_VID5 <43> CPU_VID6 <43>
VCCSENSE <43>
VSSSENSE <43>
Length match within 25 mils. The trace width/space/other is 20/7/25.
+VCC_CORE
R28 100_0402_1%R28 100_0402_1%
1 2
R30 100_0402_1%R30 100_0402_1%
1 2
+VCCP
10U_0805_6.3V6M
10U_0805_6.3V6M
VCCSENSE
VSSSENSE
1
+
+
C6
C6 330U_D2E_2.5VM_R7
330U_D2E_2.5VM_R7
2
1
C7
C7
2
0.01U_0402_16V7K
0.01U_0402_16V7K
+1.5VS
1
C8
C8
2
Near pin B26
Close to CPU pin within
A A
Close to CPU pin AD26 within 500mils.
500mils.
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2007/08/28 2006/03/10
2007/08/28 2006/03/10
2007/08/28 2006/03/10
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
2
Date: Sheet
Compal Electronics, Inc.
Penryn(2/3)-AGTL+/ITP-XDP
Penryn(2/3)-AGTL+/ITP-XDP
Penryn(2/3)-AGTL+/ITP-XDP
Montevina Blade UMA LA4105P
Montevina Blade UMA LA4105P
Montevina Blade UMA LA4105P
1
1.0
1.0
7 45Saturday, July 18, 2009
7 45Saturday, July 18, 2009
7 45Saturday, July 18, 2009
1.0
of
of
of
5
D D
JCPU1D
JCPU1D
A4
VSS[001]
A8
VSS[002]
A11
VSS[003]
A14
VSS[004]
A16
VSS[005]
A19
VSS[006]
A23
VSS[007]
AF2
VSS[008]
B6
VSS[009]
B8
VSS[010]
B11
VSS[011]
B13
VSS[012]
B16
VSS[013]
B19
VSS[014]
B21
VSS[015]
B24
VSS[016]
C5
VSS[017]
C8
VSS[018]
C11
VSS[019]
C14
VSS[020]
C16
VSS[021]
C19
VSS[022]
C2
VSS[023]
C22
VSS[024]
C25
VSS[025]
D1
VSS[026]
D4
VSS[027]
D8
VSS[028]
D11
C C
B B
VSS[029]
D13
VSS[030]
D16
VSS[031]
D19
VSS[032]
D23
VSS[033]
D26
VSS[034]
E3
VSS[035]
E6
VSS[036]
E8
VSS[037]
E11
VSS[038]
E14
VSS[039]
E16
VSS[040]
E19
VSS[041]
E21
VSS[042]
E24
VSS[043]
F5
VSS[044]
F8
VSS[045]
F11
VSS[046]
F13
VSS[047]
F16
VSS[048]
F19
VSS[049]
F2
VSS[050]
F22
VSS[051]
F25
VSS[052]
G4
VSS[053]
G1
VSS[054]
G23
VSS[055]
G26
VSS[056]
H3
VSS[057]
H6
VSS[058]
H21
VSS[059]
H24
VSS[060]
J2
VSS[061]
J5
VSS[062]
J22
VSS[063]
J25
VSS[064]
K1
VSS[065]
K4
VSS[066]
K23
VSS[067]
K26
VSS[068]
L3
VSS[069]
L6
VSS[070]
L21
VSS[071]
L24
VSS[072]
M2
VSS[073]
M5
VSS[074]
M22
VSS[075]
M25
VSS[076]
N1
VSS[077]
N4
VSS[078]
N23
VSS[079]
N26
VSS[080] VSS[081]P3VSS[162]
Penryn
Penryn
VSS[082] VSS[083] VSS[084] VSS[085] VSS[086] VSS[087] VSS[088] VSS[089] VSS[090] VSS[091] VSS[092] VSS[093] VSS[094] VSS[095] VSS[096] VSS[097] VSS[098] VSS[099] VSS[100] VSS[101] VSS[102] VSS[103] VSS[104] VSS[105] VSS[106] VSS[107] VSS[108] VSS[109] VSS[110] VSS[111] VSS[112] VSS[113] VSS[114] VSS[115] VSS[116] VSS[117] VSS[118] VSS[119] VSS[120] VSS[121] VSS[122] VSS[123] VSS[124] VSS[125] VSS[126] VSS[127] VSS[128] VSS[129] VSS[130] VSS[131] VSS[132] VSS[133] VSS[134] VSS[135] VSS[136] VSS[137] VSS[138] VSS[139] VSS[140] VSS[141] VSS[142] VSS[143] VSS[144] VSS[145] VSS[146] VSS[147] VSS[148] VSS[149] VSS[150] VSS[151] VSS[152] VSS[153] VSS[154] VSS[155] VSS[156] VSS[157] VSS[158] VSS[159] VSS[160] VSS[161]
VSS[163]
P6 P21 P24 R2 R5 R22 R25 T1 T4 T23 T26 U3 U6 U21 U24 V2 V5 V22 V25 W1 W4 W23 W26 Y3 Y6 Y21 Y24 AA2 AA5 AA8 AA11 AA14 AA16 AA19 AA22 AA25 AB1 AB4 AB8 AB11 AB13 AB16 AB19 AB23 AB26 AC3 AC6 AC8 AC11 AC14 AC16 AC19 AC21 AC24 AD2 AD5 AD8 AD11 AD13 AD16 AD19 AD22 AD25 AE1 AE4 AE8 AE11 AE14 AE16 AE19 AE23 AE26 A2 AF6 AF8 AF11 AF13 AF16 AF19 AF21 A25 AF25
.
.
4
Place these capacitors on L8 (North side,Secondary Layer)
Place these capacitors on L8 (North side,Secondary Layer)
Place these capacitors on L8 (North side,Secondary Layer)
Place these capacitors on L8 (North side,Secondary Layer)
Mid Frequence Decoupling
Near CPU CORE regulator
+VCC_CORE
C41
C41
11/21 Change ESR=7m ohm
+VCCP
1
C45
C45
0.1U_0402_10V6K
0.1U_0402_10V6K
2
3
+VCC_CORE
1
2
+VCC_CORE
1
2
+VCC_CORE
1
2
+VCC_CORE
1
2
C9
C9
10U_0805_6.3V6M
10U_0805_6.3V6M
C17
C17
10U_0805_6.3V6M
10U_0805_6.3V6M
C25
C25
10U_0805_6.3V6M
10U_0805_6.3V6M
C33
C33
10U_0805_6.3V6M
10U_0805_6.3V6M
1
C10
C10
10U_0805_6.3V6M
10U_0805_6.3V6M
2
1
C18
C18
10U_0805_6.3V6M
10U_0805_6.3V6M
2
1
C26
C26
10U_0805_6.3V6M
10U_0805_6.3V6M
2
1
C34
C34
10U_0805_6.3V6M
10U_0805_6.3V6M
2
ESR <= 1.5m ohm Capacitor > 1980uF
1
1
1
@
@
+
+
+
+
C43
C42
C42
2
330U_D2_2VY_R7M
330U_D2_2VY_R7M
C43
2
330U_D2_2VY_R7M
330U_D2_2VY_R7M
Inside CPU center cavity in 2 rows
1
C46
C46
0.1U_0402_10V6K
0.1U_0402_10V6K
2
1
2
+
+
C44
C44
2
330U_D2_2VY_R7M
330U_D2_2VY_R7M
C47
C47
0.1U_0402_10V6K
0.1U_0402_10V6K
1
+
+
2
330U_D2_2VY_R7M
330U_D2_2VY_R7M
1
2
1
C11
C11
10U_0805_6.3V6M
10U_0805_6.3V6M
2
1
C19
C19
10U_0805_6.3V6M
10U_0805_6.3V6M
2
1
C27
C27
10U_0805_6.3V6M
10U_0805_6.3V6M
2
1
C35
C35
10U_0805_6.3V6M
10U_0805_6.3V6M
2
C48
C48
0.1U_0402_10V6K
0.1U_0402_10V6K
1
C12
C12
10U_0805_6.3V6M
10U_0805_6.3V6M
2
1
C20
C20
10U_0805_6.3V6M
10U_0805_6.3V6M
2
1
C28
C28
10U_0805_6.3V6M
10U_0805_6.3V6M
2
1
C36
C36
10U_0805_6.3V6M
10U_0805_6.3V6M
2
1
C49
C49
0.1U_0402_10V6K
0.1U_0402_10V6K
2
1
C13
C13
10U_0805_6.3V6M
10U_0805_6.3V6M
2
1
C21
C21
10U_0805_6.3V6M
10U_0805_6.3V6M
2
1
C29
C29
10U_0805_6.3V6M
10U_0805_6.3V6M
2
1
C37
C37
10U_0805_6.3V6M
10U_0805_6.3V6M
2
1
C50
C50
0.1U_0402_10V6K
0.1U_0402_10V6K
2
2
1
C14
C14
10U_0805_6.3V6M
10U_0805_6.3V6M
2
1
C22
C22
10U_0805_6.3V6M
10U_0805_6.3V6M
2
1
C30
C30
10U_0805_6.3V6M
10U_0805_6.3V6M
2
1
C38
C38
10U_0805_6.3V6M
10U_0805_6.3V6M
2
1
C15
C15
10U_0805_6.3V6M
10U_0805_6.3V6M
2
1
C23
C23
10U_0805_6.3V6M
10U_0805_6.3V6M
2
1
C31
C31
10U_0805_6.3V6M
10U_0805_6.3V6M
2
1
C39
C39
10U_0805_6.3V6M
10U_0805_6.3V6M
2
1
2
1
2
1
2
1
2
1
C16
C16
10U_0805_6.3V6M
10U_0805_6.3V6M
C24
C24
10U_0805_6.3V6M
10U_0805_6.3V6M
C32
C32
10U_0805_6.3V6M
10U_0805_6.3V6M
C40
C40
10U_0805_6.3V6M
10U_0805_6.3V6M
A A
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2007/08/28 2006/03/10
2007/08/28 2006/03/10
2007/08/28 2006/03/10
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
2
Date: Sheet
Compal Electronics, Inc.
Penryn(3/3)-AGTL+/ITP-XDP
Penryn(3/3)-AGTL+/ITP-XDP
Penryn(3/3)-AGTL+/ITP-XDP
Montevina Blade UMA LA4105P
Montevina Blade UMA LA4105P
Montevina Blade UMA LA4105P
1
1.0
1.0
8 45Saturday, July 18, 2009
8 45Saturday, July 18, 2009
8 45Saturday, July 18, 2009
1.0
of
of
of
5
U2A
H_D#[0..63]<7>
D D
C C
+H_SWNG H_RCOMP
0.1U_0402_16V4Z
0.1U_0402_16V4Z
+H_VREF
1
C58
C58
2
H_RESET# H_CPUSLP#
+H_VREF
H_RESET#<6>
H_CPUSLP#<7>
B B
Layout note:
Route H_SCOMP and H_SCOMP# with trace width, spacing and impedance (55 ohm) same as FSB data traces
Layout Note: H_RCOMP / H_VREF / H_SWNG trace width and spacing is 10/20
+VCCP
12
R46
R46
1K_0402_1%
1K_0402_1%
A A
12
R52
R52
2K_0402_1%
2K_0402_1%
H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8
H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31 H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63
12
24.9_0402_1%
24.9_0402_1%
H_RCOMP
R54
R54
U2A
F2
H_D#_0
G8
H_D#_1
F8
H_D#_2
E6
H_D#_3
G2
H_D#_4
H6
H_D#_5
H2
H_D#_6
F6
H_D#_7
D4
H_D#_8
H3
H_D#_9
M9
H_D#_10
M11
H_D#_11
J1
H_D#_12
J2
H_D#_13
N12
H_D#_14
J6
H_D#_15
P2
H_D#_16
L2
H_D#_17
R2
H_D#_18
N9
H_D#_19
L6
H_D#_20
M5
H_D#_21
J3
H_D#_22
N2
H_D#_23
R1
H_D#_24
N5
H_D#_25
N6
H_D#_26
P13
H_D#_27
N8
H_D#_28
L7
H_D#_29
N10
H_D#_30
M3
H_D#_31
Y3
H_D#_32
AD14
H_D#_33
Y6
H_D#_34
Y10
H_D#_35
Y12
H_D#_36
Y14
H_D#_37
Y7
H_D#_38
W2
H_D#_39
AA8
H_D#_40
Y9
H_D#_41
AA13
H_D#_42
AA9
H_D#_43
AA11
H_D#_44
AD11
H_D#_45
AD10
H_D#_46
AD13
H_D#_47
AE12
H_D#_48
AE9
H_D#_49
AA2
H_D#_50
AD8
H_D#_51
AA3
H_D#_52
AD3
H_D#_53
AD7
H_D#_54
AE14
H_D#_55
AF3
H_D#_56
AC1
H_D#_57
AE3
H_D#_58
AC3
H_D#_59
AE11
H_D#_60
AE8
H_D#_61
AG2
H_D#_62
AD6
H_D#_63
C5
H_SWING
E3
H_RCOMP
C12
H_CPURST#
E11
H_CPUSLP#
A11
H_AVREF
B11
H_DVREF
CANTIGA ES_FCBGA1329
CANTIGA ES_FCBGA1329
+VCCP
221_0603_1%
221_0603_1%
100_0402_1%
100_0402_1%
H_A#_3 H_A#_4 H_A#_5 H_A#_6 H_A#_7 H_A#_8
H_A#_9 H_A#_10 H_A#_11 H_A#_12 H_A#_13 H_A#_14 H_A#_15 H_A#_16 H_A#_17 H_A#_18 H_A#_19 H_A#_20 H_A#_21 H_A#_22 H_A#_23 H_A#_24 H_A#_25 H_A#_26 H_A#_27 H_A#_28 H_A#_29 H_A#_30 H_A#_31 H_A#_32 H_A#_33 H_A#_34 H_A#_35
H_ADS# H_ADSTB#_0 H_ADSTB#_1
H_BNR#
H_BPRI#
H_BREQ#
H_DEFER#
H_DBSY#
HPLL_CLK
HPLL_CLK#
H_DPWR#
HOST
HOST
H_DRDY#
H_HIT#
H_HITM# H_LOCK# H_TRDY#
H_DINV#_0 H_DINV#_1 H_DINV#_2 H_DINV#_3
H_DSTBN#_0 H_DSTBN#_1 H_DSTBN#_2 H_DSTBN#_3
H_DSTBP#_0 H_DSTBP#_1 H_DSTBP#_2 H_DSTBP#_3
H_REQ#_0 H_REQ#_1 H_REQ#_2 H_REQ#_3 H_REQ#_4
H_RS#_0
H_RS#_1
H_RS#_2
Layout Note: V_DDR_MCH_REF trace width and spacing is 20/20.
+V_DDR_MCH_REF generated by DC-DC
12
R47
R47
+H_SWNG
12
1
C59
C59
R55
R55
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
PV
::::
follow check list ver:1.5 change to 10K ohm
Near B3 pinwithin 100 mils from NB
5
A14 C15 F16 H13 C18 M16 J13 P16 R16 N17 M13 E17 P17 F17 G20 B19 J16 E20 H16 J20 L17 A17 B17 L16 C21 J17 H20 B18 K17 B20 F21 K21 L20
H12 B16 G17 A9 F11 G12 E9 B10 AH7 AH6 J11 F9 H9 E12 H11 C9
J8 L3 Y13 Y1
L10 M7 AA5 AE6
L9 M8 AA6 AE5
B15 K13 F13 B13 B14
B6 F12 C8
4
H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16 H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 H_A#32 H_A#33 H_A#34 H_A#35
H_ADS# H_ADSTB#0 H_ADSTB#1 H_BNR# H_BPRI# H_BR0# H_DEFER# H_DBSY# CLK_MCH_BCLK CLK_MCH_BCLK# H_DPWR# H_DRDY# H_HIT# H_HITM# H_LOCK# H_TRDY#
H_DINV#0 H_DINV#1 H_DINV#2 H_DINV#3
H_DSTBN#0 H_DSTBN#1 H_DSTBN#2 H_DSTBN#3
H_DSTBP#0 H_DSTBP#1 H_DSTBP#2 H_DSTBP#3
H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4
H_RS#0 H_RS#1 H_RS#2
4
H_A#[3..35] <6>
SMRCOMP_VOH
80% of 1.5V VCC_SM
20% of 1.5V VCC_SM
SMRCOMP_VOL
H_ADS# <6> H_ADSTB#0 <6> H_ADSTB#1 <6> H_BNR# <6> H_BPRI# <6> H_BR0# <6> H_DEFER# <6> H_DBSY# <6> CLK_MCH_BCLK <17> CLK_MCH_BCLK# <17> H_DPWR# <7> H_DRDY# <6> H_HIT# <6> H_HITM# <6> H_LOCK# <6> H_TRDY# <6>
H_DINV#0 <7> H_DINV#1 <7> H_DINV#2 <7> H_DINV#3 <7>
H_DSTBN#0 <7> H_DSTBN#1 <7> H_DSTBN#2 <7> H_DSTBN#3 <7>
H_DSTBP#0 <7> H_DSTBP#1 <7> H_DSTBP#2 <7> H_DSTBP#3 <7>
H_REQ#0 <6> H_REQ#1 <6> H_REQ#2 <6> H_REQ#3 <6> H_REQ#4 <6>
H_RS#0 <6> H_RS#1 <6> H_RS#2 <6>
PLT_RST#<20,25,26,27>
H_THERMTRIP#<6,21>
DPRSLPVR<22,43>
V_DDR_MCH_REF
1
C57
C57
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
+1.5V
1
1
C51
C51
2.2U_0603_6.3V4Z
2.2U_0603_6.3V4Z
2
1
C53
C53
2
2.2U_0603_6.3V4Z
2.2U_0603_6.3V4Z
R41 100_0402_5%R41 100_0402_5% R42 0_0402_5%R42 0_0402_5%
C52
C52
0.01U_0402_25V7K
0.01U_0402_25V7K
2
1
C54
C54
2
0.01U_0402_25V7K
0.01U_0402_25V7K
PM_EXTTS#0
PM_EXTTS#1
CLKREQ#_7
PM_BMBUSY#<22>
1 2 1 2
+1.5V
12
R45
R45 10K_0402_1%
10K_0402_1%
12
R48
R48 10K_0402_1%
10K_0402_1%
12
R31
R31 1K_0402_1%
1K_0402_1%
12
R32
R32
3.01K_0402_1%
3.01K_0402_1%
12
R33
R33 1K_0402_1%
1K_0402_1%
R38 10K_0402_5%
R38 10K_0402_5%
R39 10K_0402_5%R39 10K_0402_5%
R40 10K_0402_5%R40 10K_0402_5%
MCH_CLKSEL0<17> MCH_CLKSEL1<17> MCH_CLKSEL2<17>
H_DPRSTP#<7,21,43> PM_EXTTS#0<15> PM_EXTTS#1<16> PM_PWROK<22,32>
Security Classification
Security Classification
Security Classification
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
1 2
1 2
1 2
CFG5<11> CFG6<11> CFG7<11> CFG8<11>
CFG9<11> CFG10<11> CFG11<11> CFG12<11> CFG13<11> CFG14<11> CFG15<11> CFG16<11> CFG17<11> CFG18<11> CFG19<11> CFG20<11>
Issued Date
Issued Date
Issued Date
3
PM_BMBUSY# H_DPRSTP# PM_EXTTS#0 PM_EXTTS#1 PM_PWROK
THERMTRIP# DPRSLPVR
@
@
1
C55
C55
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
3
U2B
U2B
M36
T7T7 T8T8 T9T9 T10T10 T11T11 T12T12 T13T13 T14T14 T15T15 T16T16 T17T17 T18T18 T19T19 T20T20
T21T21 T22T22 T23T23
T24T24
T25T25 T26T26 T27T27 T28T28
MCH_CLKSEL0 MCH_CLKSEL1 MCH_CLKSEL2
CFG5 CFG6 CFG7 CFG8 CFG9 CFG10 CFG11 CFG12 CFG13 CFG14 CFG15 CFG16 CFG17 CFG18 CFG19 CFG20
RESERVED
N36
RESERVED
R33
RESERVED
T33
RESERVED
AH9
RESERVED
AH10
RESERVED
AH12
RESERVED
AH13
RESERVED
K12
RESERVED
AL34
RESERVED
AK34
RESERVED
AN35
RESERVED
AM35
RESERVED
T24
RESERVED
B31
RESERVED
B2
RESERVED
M1
RESERVED
AY21
RESERVED
BG23
RESERVED
BF23
RESERVED
BH18
RESERVED
BF18
RESERVED
+3VS
T25
CFG_0
R25
CFG_1
P25
CFG_2
P20
CFG_3
P24
CFG_4
C25
CFG_5
N24
CFG_6
M24
CFG_7
E21
CFG_8
C23
CFG_9
C24
CFG_10
N21
CFG_11
P21
CFG_12
T21
CFG_13
R20
CFG_14
M20
CFG_15
L21
CFG_16
H21
CFG_17
P29
CFG_18
R28
CFG_19
T28
CFG_20
R29
PM_SYNC#
B7
PM_DPRSTP#
N33
PM_EXT_TS#_0
P32
PM_EXT_TS#_1
AT40
PWROK
AT11
RSTIN#
T20
THERMTRIP#
R32
DPRSLPVR
BG48
NC
BF48
NC
BD48
NC
BC48
NC
BH47
NC
BG47
NC
BE47
NC
BH46
NC
BF46
NC
BG45
NC
BH44
NC
BH43
NC
BH6
NC
BH5
NC
BG4
NC
BH3
NC
BF3
NC
BH2
NC
BG2
NC
BE2
NC
BG1
NC
BF1
NC
BD1
NC
BC1
NC
F1
NC
A47
NC
CANTIGA ES_FCBGA1329
CANTIGA ES_FCBGA1329
2007/08/28 2006/03/10
2007/08/28 2006/03/10
2007/08/28 2006/03/10
RSVD
RSVD
SM_RCOMP_VOH
SM_RCOMP_VOL
DDR CLK/ CONTROL/COMPENSATION
DDR CLK/ CONTROL/COMPENSATION
DPLL_REF_CLK#
DPLL_REF_SSCLK
DPLL_REF_SSCLK#
CLK
CLK
CFG
CFG
DMI
DMI
PM
PM
GRAPHICS VID
GRAPHICS VID
MEHDA
MEHDA
DDPC_CTRLCLK
DDPC_CTRLDATA
NC
NC
SDVO_CTRLCLK
SDVO_CTRLDATA
MISC
MISC
Deciphered Date
Deciphered Date
Deciphered Date
SA_CK_0 SA_CK_1 SB_CK_0 SB_CK_1
SA_CK#_0 SA_CK#_1 SB_CK#_0 SB_CK#_1
SA_CKE_0 SA_CKE_1 SB_CKE_0 SB_CKE_1
SA_CS#_0 SA_CS#_1 SB_CS#_0 SB_CS#_1
SA_ODT_0 SA_ODT_1 SB_ODT_0 SB_ODT_1
SM_RCOMP
SM_RCOMP#
SM_VREF
SM_PWROK
SM_REXT
SM_DRAMRST#
DPLL_REF_CLK
PEG_CLK
PEG_CLK#
DMI_RXN_0 DMI_RXN_1 DMI_RXN_2 DMI_RXN_3
DMI_RXP_0 DMI_RXP_1 DMI_RXP_2 DMI_RXP_3
DMI_TXN_0 DMI_TXN_1 DMI_TXN_2 DMI_TXN_3
DMI_TXP_0 DMI_TXP_1 DMI_TXP_2 DMI_TXP_3
GFX_VID_0 GFX_VID_1 GFX_VID_2 GFX_VID_3 GFX_VID_4
GFX_VR_EN
CL_CLK
CL_DATA
CL_PWROK
CL_RST# CL_VREF
CLKREQ#
ICH_SYNC#
TSATN#
HDA_BCLK
HDA_RST#
HDA_SDI
HDA_SDO
HDA_SYNC
2
M_CLK_DDR0
AP24
M_CLK_DDR1
AT21
M_CLK_DDR2
AV24
M_CLK_DDR3
AU20
M_CLK_DDR#0
AR24
M_CLK_DDR#1
AR21
M_CLK_DDR#2
AU24
M_CLK_DDR#3
AV20
DDR_CKE0_DIMMA
BC28
DDR_CKE1_DIMMA
AY28
DDR_CKE2_DIMMB
AY36
DDR_CKE3_DIMMB
BB36
DDR_CS0_DIMMA#
BA17
DDR_CS1_DIMMA#
AY16
DDR_CS2_DIMMB#
AV16
DDR_CS3_DIMMB#
AR13
M_ODT0
BD17
M_ODT1
AY17
M_ODT2
BF15
M_ODT3
AY13
SMRCOMP
BG22
SMRCOMP#
BH21
SMRCOMP_VOH
BF28
SMRCOMP_VOL
BH28
V_DDR_MCH_REF
AV42
SM_PWROK
AR36
SM_REXT
BF17
TP_SM_DRAMRST#
BC36
CLK_MCH_DREFCLK
B38
CLK_MCH_DREFCLK#
A38
MCH_SSCDREFCLK
E41
MCH_SSCDREFCLK#
F41
CLK_MCH_3GPLL
F43
CLK_MCH_3GPLL#
E43
DMI_TXN0
AE41
DMI_TXN1
AE37
DMI_TXN2
AE47
DMI_TXN3
AH39
DMI_TXP0
AE40
DMI_TXP1
AE38
DMI_TXP2
AE48
DMI_TXP3
AH40
DMI_RXN0
AE35
DMI_RXN1
AE43
DMI_RXN2
AE46
DMI_RXN3
AH42
DMI_RXP0
AD35
DMI_RXP1
AE44
DMI_RXP2
AF46
DMI_RXP3
AH43
B33 B32 G33 F33 E33
C34
AH37 AH36 AN36 AJ35 AH34
CL_CLK0 CL_DATA0 M_PWROK CL_RST# +CL_VREF
T30T30 T31T31 T32T32 T33T33 T34T34
T35T35
0621 add CLK and DAT for DVI
N28 M28
HDMICLK_NB
G36
HDMIDAT_NB
E36
CLKREQ#_7
K36
MCH_ICH_SYNC#
H36
TSATN#
B12
B28 B30
HDA_SDIN2_NB
B29 C29 A28
R737 56_0402_5%R737 56_0402_5%
1 2
M_CLK_DDR0 <15> M_CLK_DDR1 <15> M_CLK_DDR2 <16> M_CLK_DDR3 <16>
M_CLK_DDR#0 <15> M_CLK_DDR#1 <15> M_CLK_DDR#2 <16> M_CLK_DDR#3 <16>
DDR_CKE0_DIMMA <15> DDR_CKE1_DIMMA <15> DDR_CKE2_DIMMB <16> DDR_CKE3_DIMMB <16>
DDR_CS0_DIMMA# <15> DDR_CS1_DIMMA# <15> DDR_CS2_DIMMB# <16> DDR_CS3_DIMMB# <16>
M_ODT0 <15> M_ODT1 <15> M_ODT2 <16> M_ODT3 <16>
R34 80.6_0402_1%
R34 80.6_0402_1%
1 2
R35 80.6_0402_1%R35 80.6_0402_1%
1 2
Follow Design Guide For Cantiga: 80.6ohm
R36 0_0402_5%@R36 0_0402_5%@
1 2
R37 499_0402_1%R37 499_0402_1%
1 2
SM_DRAMRST# <15,16>
CLK_MCH_DREFCLK <17>
CLK_MCH_DREFCLK# <17>
MCH_SSCDREFCLK <17>
MCH_SSCDREFCLK# <17>
CLK_MCH_3GPLL <17> CLK_MCH_3GPLL# <17>
DMI_TXN0 <22> DMI_TXN1 <22> DMI_TXN2 <22> DMI_TXN3 <22>
DMI_TXP0 <22> DMI_TXP1 <22> DMI_TXP2 <22> DMI_TXP3 <22>
DMI_RXN0 <22> DMI_RXN1 <22> DMI_RXN2 <22> DMI_RXN3 <22>
DMI_RXP0 <22> DMI_RXP1 <22> DMI_RXP2 <22> DMI_RXP3 <22>
SM_PWROK
CL_CLK0 <22> CL_DATA0 <22> M_PWROK <22,32> CL_RST# <22>
0.1U_0402_16V4Z
0.1U_0402_16V4Z
T36T36 T37T37
HDMICLK_NB <35> HDMIDAT_NB <35>
CLKREQ#_7 <17> MCH_ICH_SYNC# <22>
+VCCP
TSATN# <32>
HDA_BITCLK_NB <21> HDA_RST#_NB <21>
HDA_SDOUT_NB <21> HDA_SYNC_NB <21>
1 2
33_0402_5%
33_0402_5%
CH751H-40PT_SOD323-2
CH751H-40PT_SOD323-2
C56
C56
R210
R210
0830 Add pull-up and pull-down resistor.
Title
Title
Title
Cantiga(1/6)-AGTL/DMI/DDR
Cantiga(1/6)-AGTL/DMI/DDR
Cantiga(1/6)-AGTL/DMI/DDR
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Montevina Blade UMA LA4105P
Montevina Blade UMA LA4105P
Montevina Blade UMA LA4105P
Date: Sheet
Date: Sheet
2
Date: Sheet
1
+1.5V
12
12
R43
R43 1K_0402_1%
1K_0402_1%
12
R44
R44 499_0402_1%
499_0402_1%
HDA_SDIN2 <21>
+1.5V
SYSON <26,32,33,36,41>
DDR3_SM_PWROK <41>
9 45Saturday, July 18, 2009
9 45Saturday, July 18, 2009
9 45Saturday, July 18, 2009
1
R1120
R1120 10K_0402_5%~D
10K_0402_5%~D
D25
D25
2 1
+VCCP
1
2
*R44*Follow Intel feedback
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
1.0
1.0
1.0
of
of
of
5
D D
DDR_A_D[0..63]<15>
C C
B B
DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15 DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63
U2D
U2D
AJ38
SA_DQ_0
AJ41
SA_DQ_1
AN38
SA_DQ_2
AM38
SA_DQ_3
AJ36
SA_DQ_4
AJ40
SA_DQ_5
AM44
SA_DQ_6
AM42
SA_DQ_7
AN43
SA_DQ_8
AN44
SA_DQ_9
AU40
SA_DQ_10
AT38
SA_DQ_11
AN41
SA_DQ_12
AN39
SA_DQ_13
AU44
SA_DQ_14
AU42
SA_DQ_15
AV39
SA_DQ_16
AY44
SA_DQ_17
BA40
SA_DQ_18
BD43
SA_DQ_19
AV41
SA_DQ_20
AY43
SA_DQ_21
BB41
SA_DQ_22
BC40
SA_DQ_23
AY37
SA_DQ_24
BD38
SA_DQ_25
AV37
SA_DQ_26
AT36
SA_DQ_27
AY38
SA_DQ_28
BB38
SA_DQ_29
AV36
SA_DQ_30
AW36
SA_DQ_31
BD13
SA_DQ_32
AU11
SA_DQ_33
BC11
SA_DQ_34
BA12
SA_DQ_35
AU13
SA_DQ_36
AV13
SA_DQ_37
BD12
SA_DQ_38
BC12
SA_DQ_39
BB9
SA_DQ_40
BA9
SA_DQ_41
AU10
SA_DQ_42
AV9
SA_DQ_43
BA11
SA_DQ_44
BD9
SA_DQ_45
AY8
SA_DQ_46
BA6
SA_DQ_47
AV5
SA_DQ_48
AV7
SA_DQ_49
AT9
SA_DQ_50
AN8
SA_DQ_51
AU5
SA_DQ_52
AU6
SA_DQ_53
AT5
SA_DQ_54
AN10
SA_DQ_55
AM11
SA_DQ_56
AM5
SA_DQ_57
AJ9
SA_DQ_58
AJ8
SA_DQ_59
AN12
SA_DQ_60
AM13
SA_DQ_61
AJ11
SA_DQ_62
AJ12
SA_DQ_63
CANTIGA ES_FCBGA1329
CANTIGA ES_FCBGA1329
DDR SYSTEM MEMORY A
DDR SYSTEM MEMORY A
SA_BS_0 SA_BS_1 SA_BS_2
SA_RAS# SA_CAS#
SA_WE#
SA_DM_0 SA_DM_1 SA_DM_2 SA_DM_3 SA_DM_4 SA_DM_5 SA_DM_6 SA_DM_7
SA_DQS_0 SA_DQS_1 SA_DQS_2 SA_DQS_3 SA_DQS_4 SA_DQS_5 SA_DQS_6
SA_DQS_7 SA_DQS#_0 SA_DQS#_1 SA_DQS#_2 SA_DQS#_3 SA_DQS#_4 SA_DQS#_5 SA_DQS#_6 SA_DQS#_7
SA_MA_0 SA_MA_1 SA_MA_2 SA_MA_3 SA_MA_4 SA_MA_5 SA_MA_6 SA_MA_7 SA_MA_8
SA_MA_9 SA_MA_10 SA_MA_11 SA_MA_12 SA_MA_13 SA_MA_14
4
DDR_A_BS0
BD21 BG18 AT25
BB20 BD20 AY20
AM37 AT41 AY41 AU39 BB12 AY6 AT7 AJ5
AJ44 AT44 BA43 BC37 AW12 BC8 AU8 AM7 AJ43 AT43 BA44 BD37 AY12 BD8 AU9 AM8
BA21 BC24 BG24 BH24 BG25 BA24 BD24 BG27 BF25 AW24 BC21 BG26 BH26 BH17 AY25
DDR_A_BS1 DDR_A_BS2
DDR_A_RAS# DDR_A_CAS# DDR_A_WE#
DDR_A_DM0 DDR_A_DM1 DDR_A_DM2 DDR_A_DM3 DDR_A_DM4 DDR_A_DM5 DDR_A_DM6 DDR_A_DM7
DDR_A_DQS0 DDR_A_DQS1 DDR_A_DQS2 DDR_A_DQS3 DDR_A_DQS4 DDR_A_DQS5 DDR_A_DQS6 DDR_A_DQS7 DDR_A_DQS#0 DDR_A_DQS#1 DDR_A_DQS#2
DDR_A_DQS#3
DDR_A_DQS#4 DDR_A_DQS#5 DDR_A_DQS#6 DDR_A_DQS#7
DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 DDR_A_MA14
DDR_A_BS0 <15> DDR_A_BS1 <15> DDR_A_BS2 <15>
DDR_A_RAS# <15> DDR_A_CAS# <15> DDR_A_WE# <15>
DDR_A_DM[0..7] <15>
DDR_A_DQS[0..7] <15>
DDR_A_DQS#[0..7] <15>
DDR_A_MA[0..14] <15>
3
DDR_B_D[0..63]<16>
DDR_B_D0 DDR_B_D1 DDR_B_D2 DDR_B_D3 DDR_B_D4 DDR_B_D5 DDR_B_D6 DDR_B_D7 DDR_B_D8 DDR_B_D9 DDR_B_D10 DDR_B_D11 DDR_B_D12 DDR_B_D13 DDR_B_D14 DDR_B_D15 DDR_B_D16 DDR_B_D17 DDR_B_D18 DDR_B_D19 DDR_B_D20 DDR_B_D21 DDR_B_D22 DDR_B_D23 DDR_B_D24 DDR_B_D25 DDR_B_D26 DDR_B_D27 DDR_B_D28 DDR_B_D29 DDR_B_D30 DDR_B_D31 DDR_B_D32 DDR_B_D33 DDR_B_D34 DDR_B_D35 DDR_B_D36 DDR_B_D37 DDR_B_D38 DDR_B_D39 DDR_B_D40 DDR_B_D41 DDR_B_D42 DDR_B_D43 DDR_B_D44 DDR_B_D45 DDR_B_D46 DDR_B_D47 DDR_B_D48 DDR_B_D49 DDR_B_D50 DDR_B_D51 DDR_B_D52 DDR_B_D53 DDR_B_D54 DDR_B_D55 DDR_B_D56 DDR_B_D57 DDR_B_D58 DDR_B_D59 DDR_B_D60 DDR_B_D61 DDR_B_D62 DDR_B_D63
U2E
U2E
AK47
SB_DQ_0
AH46
SB_DQ_1
AP47
SB_DQ_2
AP46
SB_DQ_3
AJ46
SB_DQ_4
AJ48
SB_DQ_5
AM48
SB_DQ_6
AP48
SB_DQ_7
AU47
SB_DQ_8
AU46
SB_DQ_9
BA48
SB_DQ_10
AY48
SB_DQ_11
AT47
SB_DQ_12
AR47
SB_DQ_13
BA47
SB_DQ_14
BC47
SB_DQ_15
BC46
SB_DQ_16
BC44
SB_DQ_17
BG43
SB_DQ_18
BF43
SB_DQ_19
BE45
SB_DQ_20
BC41
SB_DQ_21
BF40
SB_DQ_22
BF41
SB_DQ_23
BG38
SB_DQ_24
BF38
SB_DQ_25
BH35
SB_DQ_26
BG35
SB_DQ_27
BH40
SB_DQ_28
BG39
SB_DQ_29
BG34
SB_DQ_30
BH34
SB_DQ_31
BH14
SB_DQ_32
BG12
SB_DQ_33
BH11
SB_DQ_34
BG8
SB_DQ_35
BH12
SB_DQ_36
BF11
SB_DQ_37
BF8
SB_DQ_38
BG7
SB_DQ_39
BC5
SB_DQ_40
BC6
SB_DQ_41
AY3
SB_DQ_42
AY1
SB_DQ_43
BF6
SB_DQ_44
BF5
SB_DQ_45
BA1
SB_DQ_46
BD3
SB_DQ_47
AV2
SB_DQ_48
AU3
SB_DQ_49
AR3
SB_DQ_50
AN2
SB_DQ_51
AY2
SB_DQ_52
AV1
SB_DQ_53
AP3
SB_DQ_54
AR1
SB_DQ_55
AL1
SB_DQ_56
AL2
SB_DQ_57
AJ1
SB_DQ_58
AH1
SB_DQ_59
AM2
SB_DQ_60
AM3
SB_DQ_61
AH3
SB_DQ_62
AJ3
SB_DQ_63
CANTIGA ES_FCBGA1329
CANTIGA ES_FCBGA1329
2
DDR_B_BS0
BC16
SB_BS_0 SB_BS_1 SB_BS_2
SB_RAS#
SB_CAS#
SB_WE#
SB_DM_0 SB_DM_1 SB_DM_2 SB_DM_3 SB_DM_4 SB_DM_5 SB_DM_6 SB_DM_7
SB_DQS_0 SB_DQS_1 SB_DQS_2 SB_DQS_3 SB_DQS_4 SB_DQS_5 SB_DQS_6
SB_DQS_7 SB_DQS#_0 SB_DQS#_1 SB_DQS#_2 SB_DQS#_3 SB_DQS#_4 SB_DQS#_5 SB_DQS#_6 SB_DQS#_7
SB_MA_0 SB_MA_1 SB_MA_2 SB_MA_3 SB_MA_4 SB_MA_5 SB_MA_6 SB_MA_7 SB_MA_8
SB_MA_9 SB_MA_10 SB_MA_11 SB_MA_12 SB_MA_13 SB_MA_14
DDR SYSTEM MEMORY B
DDR SYSTEM MEMORY B
BB17 BB33
AU17 BG16 BF14
AM47 AY47 BD40 BF35 BG11 BA3 AP1 AK2
AL47 AV48 BG41 BG37 BH9 BB2 AU1 AN6 AL46 AV47 BH41 BH37 BG9 BC2 AT2 AN5
AV17 BA25 BC25 AU25 AW25 BB28 AU28 AW28 AT33 BD33 BB16 AW33 AY33 BH15 AU33
DDR_B_BS1 DDR_B_BS2
DDR_B_RAS# DDR_B_CAS# DDR_B_WE#
DDR_B_DM0 DDR_B_DM1 DDR_B_DM2 DDR_B_DM3 DDR_B_DM4 DDR_B_DM5 DDR_B_DM6 DDR_B_DM7
DDR_B_DQS0 DDR_B_DQS1 DDR_B_DQS2 DDR_B_DQS3 DDR_B_DQS4 DDR_B_DQS5 DDR_B_DQS6 DDR_B_DQS7 DDR_B_DQS#0 DDR_B_DQS#1 DDR_B_DQS#2 DDR_B_DQS#3 DDR_B_DQS#4 DDR_B_DQS#5 DDR_B_DQS#6 DDR_B_DQS#7
DDR_B_MA0 DDR_B_MA1 DDR_B_MA2 DDR_B_MA3 DDR_B_MA4 DDR_B_MA5 DDR_B_MA6 DDR_B_MA7 DDR_B_MA8 DDR_B_MA9 DDR_B_MA10 DDR_B_MA11 DDR_B_MA12 DDR_B_MA13 DDR_B_MA14
1
DDR_B_BS0 <16> DDR_B_BS1 <16> DDR_B_BS2 <16>
DDR_B_RAS# <16> DDR_B_CAS# <16> DDR_B_WE# <16>
DDR_B_DM[0..7] <16>
DDR_B_DQS[0..7] <16>
DDR_B_DQS#[0..7] <16>
DDR_B_MA[0..14] <16>
A A
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2007/08/28 2006/03/10
2007/08/28 2006/03/10
2007/08/28 2006/03/10
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
2
Date: Sheet
Compal Electronics, Inc.
Cantiga(2/6)-DDR2 A/B CH
Cantiga(2/6)-DDR2 A/B CH
Cantiga(2/6)-DDR2 A/B CH
Montevina Blade UMA LA4105P
Montevina Blade UMA LA4105P
Montevina Blade UMA LA4105P
1
1.0
1.0
10 45Saturday, July 18, 2009
10 45Saturday, July 18, 2009
10 45Saturday, July 18, 2009
1.0
of
of
of
5
R148
R148
1 2
100K_0402_5%
100K_0402_5%
D D
C C
11/10 Disable TV out
B B
ENBKL
ENBKL<32>
+3VS
DDC2_CLK<19> DDC2_DATA<19>
Follow Intel DG & Checklist
ENAVDD<19>
T48T48 T49T49 T50T50
Follow Intel DG & Checklist
+3VS
M_BLUE<18> M_GREEN<18> M_RED<18>
Follow Intel DG & Checklist
3VDDCCL<18> 3VDDCDA<18>
CRT_HSYNC<18>
CRT_VSYNC<18>
ENBKL
R58 10K_0402_5%R58 10K_0402_5%
1 2
R59 10K_0402_5%R59 10K_0402_5%
1 2
DDC2_CLK DDC2_DATA
ENAVDD
R60 4.75K_0402_1%R60 4.75K_0402_1%
1 2
LVDS_ACLK­LVDS_ACLK+ LVDS_BCLK-
T80T80
LVDS_BCLK+
T81T81
LVDS_A0­LVDS_A1­LVDS_A2­LVDS_A3-
T38T38
LVDS_A0+ LVDS_A1+ LVDS_A2+ LVDS_A3+
T39T39
LVDS_B0-
T72T72
LVDS_B1-
T73T73
LVDS_B2-
T74T74
LVDS_B3-
T40T40
LVDS_B0+
T75T75
LVDS_B1+
T77T77
LVDS_B2+
T79T79
LVDS_B3+
T41T41
TV_COMPS TV_LUMA TV_CRMA
12
75_0402_1%
75_0402_1%
R62
R62
R61
R61
R64 2.2K_0402_5%@R64 2.2K_0402_5%@
1 2
R406 0_0402_5%R406 0_0402_5%
1 2
M_BLUE M_GREEN M_RED
3VDDCCL 3VDDCDA CRT_HSYNC
R65
R65
R68
R68
30.1_0402_1%
30.1_0402_1%
R69
R69
30.1_0402_1%
30.1_0402_1%
150_0402_1%
150_0402_1%
12
1 2
1 2
R66
R66
12
75_0402_1%
75_0402_1%
R63
R63
150_0402_1%
150_0402_1%
12
R67
R67
HSYNC
VSYNCCRT_VSYNC
1.02K_0402_1%
1.02K_0402_1%
12
12
R70
R70
4
U2C
U2C
L32
L_BKLT_CTRL
G32
L_BKLT_EN
M32
L_CTRL_CLK
M33
L_CTRL_DATA
K33
L_DDC_CLK
J33
L_DDC_DATA
M29
L_VDD_EN
C44
LVDS_IBG
B43
LVDS_VBG
E37
LVDS_VREFH
E38
LVDS_VREFL
C41
LVDSA_CLK#
C40
LVDSA_CLK
B37
LVDSB_CLK#
A37
LVDSB_CLK
H47
LVDSA_DATA#_0
E46
LVDSA_DATA#_1
G40
LVDSA_DATA#_2
A40
LVDSA_DATA#_3
H48
LVDSA_DATA_0
D45
LVDSA_DATA_1
F40
LVDSA_DATA_2
B40
LVDSA_DATA_3
A41
LVDSB_DATA#_0
H38
LVDSB_DATA#_1
G37
LVDSB_DATA#_2
J37
LVDSB_DATA#_3
B42
LVDSB_DATA_0
G38
LVDSB_DATA_1
F37
LVDSB_DATA_2
K37
LVDSB_DATA_3
F25
TVA_DAC
H25
75_0402_1%
75_0402_1%
150_0402_1%
150_0402_1%
12
TVB_DAC
K25
TVC_DAC
H24
TV_RTN
C31
TV_DCONSEL_0
E32
TV_DCONSEL_1
E28
CRT_BLUE
G28
CRT_GREEN
J28
CRT_RED
G29
CRT_IRTN
H32
CRT_DDC_CLK
J32
CRT_DDC_DATA
J29
CRT_HSYNC
E29
CRT_TVO_IREF
L29
CRT_VSYNC
CANTIGA ES_FCBGA1329
CANTIGA ES_FCBGA1329
LVDS
LVDS
TV VGA
TV VGA
PCI-EXPRESS GRAPHICS
PCI-EXPRESS GRAPHICS
PEG_COMPI
PEG_COMPO
PEG_RX#_0 PEG_RX#_1 PEG_RX#_2 PEG_RX#_3 PEG_RX#_4 PEG_RX#_5 PEG_RX#_6 PEG_RX#_7 PEG_RX#_8
PEG_RX#_9 PEG_RX#_10 PEG_RX#_11 PEG_RX#_12 PEG_RX#_13 PEG_RX#_14 PEG_RX#_15
PEG_RX_0 PEG_RX_1 PEG_RX_2 PEG_RX_3 PEG_RX_4 PEG_RX_5 PEG_RX_6 PEG_RX_7 PEG_RX_8
PEG_RX_9 PEG_RX_10 PEG_RX_11 PEG_RX_12 PEG_RX_13 PEG_RX_14 PEG_RX_15
PEG_TX#_0 PEG_TX#_1 PEG_TX#_2 PEG_TX#_3 PEG_TX#_4 PEG_TX#_5 PEG_TX#_6 PEG_TX#_7 PEG_TX#_8 PEG_TX#_9
PEG_TX#_10 PEG_TX#_11 PEG_TX#_12 PEG_TX#_13 PEG_TX#_14 PEG_TX#_15
PEG_TX_0 PEG_TX_1 PEG_TX_2 PEG_TX_3 PEG_TX_4 PEG_TX_5 PEG_TX_6 PEG_TX_7 PEG_TX_8
PEG_TX_9 PEG_TX_10 PEG_TX_11 PEG_TX_12 PEG_TX_13 PEG_TX_14 PEG_TX_15
T37 T36
H44 J46 L44 L40 N41 P48 N44 T43 U43 Y43 Y48 Y36 AA43 AD37 AC47 AD39
H43 J44 L43 L41 N40 P47 N43 T42 U42 Y42 W47 Y37 AA42 AD36 AC48 AD40
J41 M46 M47 M40 M42 R48 N38 T40 U37 U40 Y40 AA46 AA37 AA40 AD43 AC46
J42 L46 M48 M39 M43 R47 N37 T39 U36 U39 Y39 Y46 AA36 AA39 AD42 AD46
3
R57
R57
1 2
49.9_0402_1%
49.9_0402_1%
PEGCOMP trace width and spacing is 20/25 mils.
TMDS_B_HPD#
TMDS_BDATA2# TMDS_BDATA1# TMDS_BDATA0# TMDS_BCLK#
TMDS_BDATA2 TMDS_BDATA1 TMDS_BDATA0 TMDS_BCLK
C274 0.1U_0402_10V7KC274 0.1U_0402_10V7K C275 0.1U_0402_10V7KC275 0.1U_0402_10V7K C276 0.1U_0402_10V7KC276 0.1U_0402_10V7K C277 0.1U_0402_10V7KC277 0.1U_0402_10V7K
C278 0.1U_0402_10V7KC278 0.1U_0402_10V7K C279 0.1U_0402_10V7KC279 0.1U_0402_10V7K C280 0.1U_0402_10V7KC280 0.1U_0402_10V7K C281 0.1U_0402_10V7KC281 0.1U_0402_10V7K
1 2 1 2 1 2 1 2
1 2 1 2 1 2 1 2
+VCC_PEG
TMDS_B_HPD# <35>
2
TMDS_B_DATA2# <35> TMDS_B_DATA1# <35> TMDS_B_DATA0# <35> TMDS_B_CLK# <35>
TMDS_B_DATA2 <35> TMDS_B_DATA1 <35> TMDS_B_DATA0 <35> TMDS_B_CLK <35>
Strap Pin Table
CFG[2:0] FSB Freq select
CFG[4:3]
CFG5 (DMI select)
CFG6
(Intel Management
CFG7
Engine Crypto strap)
CFG8
CFG9 (PCIE Graphics
Lane Reversal)
(PCIE
CFG10
Lookback enable)
CFG11
CFG[13:12] (XOR/ALLZ)
CFG[15:14]
CFG16 (FSB Dynamic ODT)
CFG[18:17]
CFG19 (DMI Lane Reversal)
(PCIE/SDVO
CFG20
concurrent)
+3VS
R71
@R71
@
4.02K_0402_1%
4.02K_0402_1%
CFG5<9>
CFG5
R74
@R74
@
2.21K_0402_1%
2.21K_0402_1%
1
000 = FSB 1066MHz 010 = FSB 800MHz 011 = FSB 667MHz Others = Reserved
Reserved
0 = DMI x 2 1 = DMI x 4
0 = The iTPM Host Interface is enable
*
1 = The iTPM Host Interface is disable
0 =(TLS)chiper suite with no confidentiality
1 =(TLS)chiper suite with confidentiality
Reserved
0 = Reverse Lane,15->0, 14->1
1 = Normal Operation,Lane Number in order
0 = Enable
1 = Disable
Reserved
00 = Reserved 01 = XOR Mode Enabled 10 = All Z Mode Enabled
*
Reserved
0 = Disabled 1 = Enabled
*
Reserved
0 = Normal Operation
(Lane number in Order)
1 = Reverse Lane
0 = Only PCIE or SDVO is operational.
1 = PCIE/SDVO are operating simu.
12
R72
@R72
12
CFG16<9>
CFG19<9>
CFG20<9>
@
@ R73
@
@R75
@
R73
R75
(Default)11 = Normal Operation
*
*
1 2
4.02K_0402_1%
4.02K_0402_1%
1 2
4.02K_0402_1%
4.02K_0402_1%
1 2
4.02K_0402_1%
4.02K_0402_1%
*
*
*
*
+3VS
R76
@R76
@
@R77
@
@R78
@
@R80
@
@R82
@
@R85
@
@R87
@
R77
R78
R80
R82
R85
R87
1 2
2.21K_0402_1%
2.21K_0402_1%
1 2
2.21K_0402_1%
2.21K_0402_1%
1 2
2.21K_0402_1%
2.21K_0402_1%
1 2
2.21K_0402_1%
2.21K_0402_1%
1 2
2.21K_0402_1%
2.21K_0402_1%
1 2
2.21K_0402_1%
2.21K_0402_1%
1 2
2.21K_0402_1%
2.21K_0402_1%
11 45Saturday, July 18, 2009
11 45Saturday, July 18, 2009
11 45Saturday, July 18, 2009
of
of
of
1.0
1.0
1.0
Solve 3G WWAN issue
LVDS_ACLK+<19>
LVDS_ACLK-<19> LVDS_A0+<19>
LVDS_A0-<19> LVDS_A1+<19>
LVDS_A1-<19> LVDS_A2+<19>
A A
LVDS_A2-<19>
LVDS_ACLK+
LVDS_ACLK­LVDS_A0+
LVDS_A0­LVDS_A1+
LVDS_A1­LVDS_A2+
LVDS_A2-
5
1
@
@
C60
C60
0.1U_0402_10V6K
0.1U_0402_10V6K
2 1
@
@
C61
C61
0.1U_0402_10V6K
0.1U_0402_10V6K
2 1
@
@
C62
C62
0.1U_0402_10V6K
0.1U_0402_10V6K
2 1
@
@
C63
C63
0.1U_0402_10V6K
0.1U_0402_10V6K
2
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2007/08/28 2006/03/10
2007/08/28 2006/03/10
2007/08/28 2006/03/10
Deciphered Date
Deciphered Date
Deciphered Date
04/29 MV-1 Delete CFG5 CFG7
、、、、
CFG12
CFG6<9>
CFG7<9>
CFG8<9>
CFG9<9>
CFG10<9>
2
、、、、
、、、、
CFG13
、、、、
CFG16
R79
@R79
@
1 2
2.21K_0402_1%
2.21K_0402_1%
R81
@R81
@
1 2
2.21K_0402_1%
2.21K_0402_1%
R83
@R83
@
1 2
2.21K_0402_1%
2.21K_0402_1%
R84
@R84
@
1 2
2.21K_0402_1%
2.21K_0402_1%
R86
@R86
@
1 2
2.21K_0402_1%
2.21K_0402_1%
Title
Title
Title
Cantiga(3/6)-VGA/LVDS/TV
Cantiga(3/6)-VGA/LVDS/TV
Cantiga(3/6)-VGA/LVDS/TV
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Montevina Blade UMA LA4105P
Montevina Blade UMA LA4105P
Montevina Blade UMA LA4105P
Date: Sheet
Date: Sheet
Date: Sheet
CFG11<9>
CFG12<9>
CFG13<9>
CFG14<9>
CFG15<9>
CFG17<9>
CFG18<9>
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
1
5
+3VS_DAC_BG
0.022U_0402_16V7K
0.022U_0402_16V7K
0.1U_0402_16V4Z
12
@
@
0_0603_5%
0_0603_5%
C68
C68
R89
R89
D D
C C
B B
12
@ R92
@
R92
+3VS_DAC_CRT
C75
C75
0_0603_5%
0_0603_5%
+1.5VS
+VCCP
C69
C69
1
2
0.022U_0402_16V7K
0.022U_0402_16V7K
C76
C76
1
2
+3VS
220U_D2_4VM
220U_D2_4VM
R103
R103
1 2
0_0603_5%
0_0603_5%
1U_0603_10V4Z
1U_0603_10V4Z
0.1U_0402_16V4Z
C70
C70
1
1
2
2
R91
R91
1 2
BLM18PG181SN1D_0603
BLM18PG181SN1D_0603
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
2
R96
@ R96
@
1 2
0_0603_5%
0_0603_5%
R97
R97
1 2
0_0603_5%
0_0603_5%
1
C94
C94
+
+
2
C102
C102
+3VS
R88
R88
1 2
BLM18PG181SN1D_0603
BLM18PG181SN1D_0603
10U_0805_10V4Z
10U_0805_10V4Z
+3VS
1
C89
C89
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
R100
R100
1 2
0_0805_5%
0_0805_5%
1
2
C95
C95
1
2
+1.05VS_A_SM_CK
C103
C103
1
2
10U_0805_10V4Z
10U_0805_10V4Z
10U_0805_10V4Z
10U_0805_10V4Z
Check Again!!!
**RED Mark: Means UMA & dis@ Power select** ~It check by INTEL Graphics Disable Guidelines~
+3VS_DAC_CRT
+3VS_DAC_BG
+1.05VS_DPLLA
+1.05VS_DPLLB
+1.05VS_HPLL
+1.05VS_MPLL
+1.8V_TXLVDS
+1.5VS_PEG_BG
4.7U_0805_10V4Z
4.7U_0805_10V4Z
C104
C104
+1.05VS_A_SM
C96
C96
1U_0603_10V4Z
1U_0603_10V4Z
1
2
1
C88
C88
1000P_0402_50V7K
1000P_0402_50V7K
2
+1.05VS_PEGPLL
1
2
1U_0603_10V4Z
1U_0603_10V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
C105
C105
1
2
+3VS_TVDAC
+1.5VS
+1.5VS_TVDAC
+1.5VS_QDAC
+1.05VS_HPLL
+1.05VS_PEGPLL
+1.8V_LVDS
1
C97
C97
2
4
U2H
U2H
73mA
B27
VCCA_CRT_DAC
A26
VCCA_CRT_DAC
2.68mA
A25
VCCA_DAC_BG
B25
VSSA_DAC_BG
F47
VCCA_DPLLA
L48
VCCA_DPLLB
AD1
VCCA_HPLL
AE1
VCCA_MPLL
13.2mA
J48
VCCA_LVDS
J47
VSSA_LVDS
414uA
AD48
VCCA_PEG_BG
50mA
AA48
VCCA_PEG_PLL
AR20
VCCA_SM
AP20
VCCA_SM
AN20
VCCA_SM
AR17
VCCA_SM
AP17
VCCA_SM
AN17
VCCA_SM
AT16
VCCA_SM
AR16
VCCA_SM
AP16
VCCA_SM
AP28
VCCA_SM_CK
AN28
VCCA_SM_CK
AP25
VCCA_SM_CK
AN25
VCCA_SM_CK
AN24
VCCA_SM_CK
AM28
VCCA_SM_CK_NCTF
AM26
VCCA_SM_CK_NCTF
AM25
VCCA_SM_CK_NCTF
AL25
VCCA_SM_CK_NCTF
AM24
VCCA_SM_CK_NCTF
AL24
VCCA_SM_CK_NCTF
AM23
VCCA_SM_CK_NCTF
AL23
VCCA_SM_CK_NCTF
B24
VCCA_TV_DAC
A24
VCCA_TV_DAC
A32
VCC_HDA
M25
VCCD_TVDAC
L28
VCCD_QDAC
AF1
VCCD_HPLL
AA47
VCCD_PEG_PLL
M38
VCCD_LVDS
L37
VCCD_LVDS
60.31mA
CANTIGA ES_FCBGA1329
CANTIGA ES_FCBGA1329
64.8mA
64.8mA
24mA
139.2mA
720mA
26mA
26mA
TVA 24.15mA TVB 39.48mA TVX 24.15mA
50mA
58.67mA
48.363mA
157.2mA
50mA
CRTPLLA PEGA SMTV
CRTPLLA PEGA SMTV
A LVDS
A LVDS
POWER
POWER
A CK
A CK
105.3mA
1732mA
HDA
HDA
D TV/CRT
D TV/CRT
LVDS
LVDS
852mA
SM CK
SM CK
118.8mA
VCC_TX_LVDS
DMI
DMI
456mA
VTT
VTT
321.35mA
VCC_AXF VCC_AXF VCC_AXF
AXF
AXF
124mA
VCC_SM_CK VCC_SM_CK VCC_SM_CK VCC_SM_CK
VCC_HV VCC_HV VCC_HV
HV
HV
VCC_PEG VCC_PEG VCC_PEG VCC_PEG VCC_PEG
PEG
PEG
VCC_DMI VCC_DMI VCC_DMI VCC_DMI
VTTLF
VTTLF
VTTLF VTTLF VTTLF
3
+VCCP
U13
VTT
T13
VTT
U12
VTT
T12
VTT
U11
VTT
T11
VTT
U10
VTT
T10
VTT
U9
VTT
T9
VTT
U8
VTT
T8
VTT
U7
VTT
T7
VTT
U6
VTT
T6
VTT
U5
VTT
T5
VTT
V3
VTT
U3
VTT
V2
VTT
U2
VTT
T2
VTT
V1
VTT
U1
VTT
B22 B21 A21
BF21 BH20 BG20 BF20
K47
C35 B35 A35
V48 U48 V47 U47 U46
AH48 AF48 AH47 AG47
A8 L1 AB2
C71
C71
+
+
C80
C80
+V1.05VS_AXF
+1.5V_SM_CK
+1.8V_TXLVDS
+VCC_PEG
+1.05VS_DMI
0.47U_0603_10V7K
0.47U_0603_10V7K
0.47U_0603_10V7K
0.47U_0603_10V7K
C111
C111
C110
C110
1
1
2
2
4.7U_0805_10V4Z
4.7U_0805_10V4Z
220U_6.3V_M
220U_6.3V_M
1
C72
C72
1
2
2
0.47U_0603_10V7K
0.47U_0603_10V7K
4.7U_0805_10V4Z
4.7U_0805_10V4Z
2.2U_0805_16V4Z
1
C81
C81
2
+3VS_HV
0.47U_0603_10V7K
0.47U_0603_10V7K
C112
C112
1
2
2.2U_0805_16V4Z
1
1
C82
C82
2
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
C107
C107
1
2
+1.05VS_DPLLA
@
@
220U_D2_4VM
220U_D2_4VM
1
C77
C77
+
+
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z C86
C86
1
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
C73
C73
C87
C87
+1.05VS_PEGPLL
2
1 2
10U_0805_10V4Z
10U_0805_10V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z C74
C74
1
1
2
2
R94
R94
1 2
10U_FLC-453232-100K_0.25A_10%
10U_FLC-453232-100K_0.25A_10%
10U_0805_10V4Z
10U_0805_10V4Z
1
2
+1.05VS_HPLL
0.1U_0402_16V4Z
0.1U_0402_16V4Z C91
C91
C90
C90
1
2
+1.05VS_MPLL
1
C99
C99
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
10U_0805_10V4Z
10U_0805_10V4Z
C106
C106
1
2
+VCCP
R90
R90 10U_FLC-453232-100K_0.25A_10%
10U_FLC-453232-100K_0.25A_10%
+VCCP+1.05VS_DPLLB
D3
D3
2 1
CH751H-40PT_SOD323-2
CH751H-40PT_SOD323-2
+3VS
+VCCP
+VCCP
+VCCP
R98
R98
1 2
MBK2012121YZF_0805
MBK2012121YZF_0805
10U_0805_10V4Z
10U_0805_10V4Z
1
2
R101
R101
1 2
MBK2012121YZF_0805
MBK2012121YZF_0805
1
C100
C100
10U_0805_10V4Z
10U_0805_10V4Z
2
L1
L1
1 2
BLM18PG121SN1D_0603
BLM18PG121SN1D_0603
C108
C108
1
2
+VCCP
+VCCP_D
R105
R105
1 2
10_0402_5%
10_0402_5%
+V1.05VS_AXF
+1.5V_SM_CK
10U_0805_10V4Z
10U_0805_10V4Z
@
@
C83
C83
1
2
+1.5VS_TVDAC
+VCC_PEG
C98
C98
+1.05VS_DMI
10U_0805_10V4Z
10U_0805_10V4Z
1
2
1
2
1
C92
C92
2
1
+
+
2
1
2
R106
R106
1 2
0_0402_5%
0_0402_5%
C78
C78
10U_0805_10V4Z
10U_0805_10V4Z
0.022U_0402_16V7K
0.022U_0402_16V7K
220U_D2_4VM
220U_D2_4VM
C109
C109
1
C84
C84
C93
C93
C101
C101
R104
R104
1 2
0_0603_5%
0_0603_5%
0.1U_0402_16V4Z
0.1U_0402_16V4Z
+VCCP
R93
R93
1 2
1U_0603_10V4Z
1U_0603_10V4Z
0_0603_5%
0_0603_5%
C79
C79
1
2
+1.5V
R95
R95
1 2
0.1U_0402_16V4Z
0.1U_0402_16V4Z 0_0805_5%
0_0805_5%
R99
R99
1 2
0_0805_5%
0_0805_5%
R102
R102
1 2
0_0805_5%
0_0805_5%
+VCCP
+3VS_HV
+VCCP
+1.5VS
C85
C85
1
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
2
10U_0805_10V4Z
10U_0805_10V4Z
1
2
+1.8V_LVDS
R107
R107
@R109
@
10U_0805_10V4Z
10U_0805_10V4Z
R109
12
0_0603_5%
0_0603_5%
+3VS_TVDAC
0.022U_0402_16V7K
@R113
@
A A
R113
0.022U_0402_16V7K
12
0_0603_5%
0_0603_5%
C117
C117
1
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
C118
C118
1
2
R111
R111
1 2
BLM18PG181SN1D_0603
BLM18PG181SN1D_0603
5
+3VS
+1.5VS_QDAC
0.022U_0402_16V7K
0.022U_0402_16V7K
0.1U_0402_16V4Z
0.1U_0402_16V4Z
@
@R114
@
12
R114
C120
C120
C119
C119
0_0603_5%
0_0603_5%
1
2
@
220U_D2_4VM
220U_D2_4VM
1
C121
1
2
C121
+
+
2
4
R112
R112
1 2
100_0603_1%
100_0603_1%
+1.5VS
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2007/08/28 2006/03/10
2007/08/28 2006/03/10
2007/08/28 2006/03/10
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
1
2
2
1 2
1U_0603_10V4Z
1U_0603_10V4Z
0_0603_5%
0_0603_5%
C113
C113
C114
C114
1
2
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
Date: Sheet
@R110
@
+1.8V
R110
12
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Cantiga(4/6)-PWR
Cantiga(4/6)-PWR
Cantiga(4/6)-PWR
Montevina Blade UMA LA4105P
Montevina Blade UMA LA4105P
Montevina Blade UMA LA4105P
40 mils
0_0603_5%
0_0603_5%
1000P_0402_50V7K
1000P_0402_50V7K
+1.8V_TXLVDS
C116
C116
1
2
R108
R108
1 2
0_0603_5%
0_0603_5%
@
@
220U_D2_4VM
220U_D2_4VM
1
C115
C115
+
+
2
12 45Saturday, July 18, 2009
12 45Saturday, July 18, 2009
12 45Saturday, July 18, 2009
1
+1.8V
1.0
1.0
1.0
of
of
of
5
4
3
2
1
W28 V28 W26 V26 W25 V25 W24 V24 W23 V23 AM21 AL21 AK21 W21 V21 U21 AM20 AK20 W20 U20 AM19 AL19 AK19 AJ19 AH19 AG19 AF19 AE19 AB19 AA19 Y19 W19 V19 U19 AM17 AK17 AH17 AG17 AF17 AE17 AC17 AB17 Y17 W17 V17 AM16 AL16 AK16 AJ16 AH16 AG16 AF16 AE16 AC16 AB16 AA16 Y16 W16 V16 U16
AV44 BA37 AM40 AV21 AY5 AM10 BB13
+VCCP
VCCSM_LF1 VCCSM_LF2 VCCSM_LF3 VCCSM_LF4 VCCSM_LF5 VCCSM_LF6 VCCSM_LF7
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
C127
C127
2
0.22U_0402_10V4Z
0.22U_0402_10V4Z
C139 0.1U_0402_16V 4ZC139 0.1U_0402_16V4Z
1
2
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
1
1
2
C140 0.1U_0402_16V 4ZC140 0.1U_0402_16V4Z
1
1
2
2
C129
C129
C128
C128
2
C144 1U_0603_10V4ZC144 1U_0603_10V 4Z
C142 0.22U_0603_10V7KC142 0.22U_0603_10V7K
C141 0.22U_0603_10V7KC141 0.22U_0603_10V7K
1
1
2
2
C145 1U_0603_10V4ZC145 1U_0603_10V 4Z
C143 0.47U_0402_6.3V6KC143 0.47U_0402_6.3V6K
1
1
2
2
U2G
U2G
0421 Change size to B2 for DFX
Extnal Graphic: 1210.34mA integrated Graphic: 1930.4mA
U2F
+VCCP
D D
0.22U_0402_10V4Z
0.22U_0402_10V4Z
0.22U_0402_10V4Z
220U_D2_4VM
220U_D2_4VM
C C
B B
0.22U_0402_10V4Z
10U_0805_10V4Z
10U_0805_10V4Z
1
C131
C131
C124
C124
1
+
+
2
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
C133
C133
C132
C132
1
2
C125
C125
1
1
2
2
U2F
AG34
VCC
AC34
VCC
AB34
VCC
AA34
VCC
Y34
VCC
V34
VCC
U34
VCC
AM33
VCC
AK33
VCC
AJ33
VCC
AG33
VCC
AF33
VCC
AE33
VCC
AC33
VCC
AA33
VCC
Y33
VCC
W33
VCC
V33
VCC
U33
VCC
AH28
VCC
AF28
VCC
AC28
VCC
AA28
VCC
AJ26
VCC
AG26
VCC
AE26
VCC
AC26
VCC
AH25
VCC
AG25
VCC
AF25
VCC
AG24
VCC
AJ23
VCC
AH23
VCC
AF23
VCC
T32
VCC
CANTIGA ES_FCBGA1329
CANTIGA ES_FCBGA1329
VCC CORE
VCC CORE
POWER
POWER
VCC NCTF
VCC NCTF
VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF
AM32 AL32 AK32 AJ32 AH32 AG32 AE32 AC32 AA32 Y32 W32 U32 AM30 AL30 AK30 AH30 AG30 AF30 AE30 AC30 AB30 AA30 Y30 W30 V30 U30 AL29 AK29 AJ29 AH29 AG29 AE29 AC29 AA29 Y29 W29 V29 AL28 AK28 AL26 AK26 AK25 AK24 AK23
+VCCP
request
1U_0603_10V4Z
1U_0603_10V4Z
+1.5V
1
C134
C134
2
330U_B2_2.5VM_R15M
330U_B2_2.5VM_R15M
1
@ +C126
@
+
2
10U_0805_10V4Z
10U_0805_10V4Z
330U_D2E_2.5VM_R7
330U_D2E_2.5VM_R7
1
+
+
C135
C135
2
10U_0805_10V4Z
10U_0805_10V4Z
10U_0805_10V4Z
10U_0805_10V4Z
C122
C122
C126
1
2
0317 change value
1
1
C137
C137
C136
C136
2
2
10U_0805_10V4Z
10U_0805_10V4Z
0.01U_0402_16V7K
0.01U_0402_16V7K
C130
C130
C123
C123
1
2
2
1
+VCCP
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
C138
C138
2
T42PAD T42PAD T43PAD T43PAD
AP33 AN33 BH32 BG32 BF32 BD32 BC32 BB32 BA32 AY32
AW32
AV32 AU32 AT32 AR32 AP32 AN32 BH31 BG31 BF31 BG30 BH29 BG29 BF29 BD29 BC29 BB29 BA29 AY29
AW29
AV29 AU29 AT29 AR29 AP29
BA36 BB24
BD16
BB21 AW16 AW13
AT13
AE25
AB25
AA25
AE24
AC24
AA24
AE23
AC23
AB23
AA23
AJ21 AG21 AE21 AC21 AA21
AH20 AF20 AE20 AC20 AB20 AA20
AM15
AL15 AE15
AJ15
AH15 AG15
AF15 AB15 AA15
AN14 AM14
AJ14
AH14
Y26
Y24
Y21
T17 T16
Y15 V15 U15
U14 T14
3000mA
VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM
VCC_SM/NC VCC_SM/NC VCC_SM/NC VCC_SM/NC VCC_SM/NC VCC_SM/NC VCC_SM/NC
6326.84mA
VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG
VCC_AXG_SENSE VSS_AXG_SENSE
POWER
POWER
VCC SMVCC GFX
VCC SMVCC GFX
VCC GFX NCTF
VCC GFX NCTF
VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF
VCC_SM_LF VCC_SM_LF VCC_SM_LF VCC_SM_LF VCC_SM_LF VCC_SM_LF VCC_SM_LF
VCC SM LF
VCC SM LF
A A
CANTIGA ES_FCBGA1329
CANTIGA ES_FCBGA1329
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2007/08/28 2006/03/10
2007/08/28 2006/03/10
2007/08/28 2006/03/10
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
2
Date: Sheet
Compal Electronics, Inc.
Cantiga(5/6)-PWR/GND
Cantiga(5/6)-PWR/GND
Cantiga(5/6)-PWR/GND
Montevina Blade UMA LA4105P
Montevina Blade UMA LA4105P
Montevina Blade UMA LA4105P
1
1.0
1.0
13 45Saturday, July 18, 2009
13 45Saturday, July 18, 2009
13 45Saturday, July 18, 2009
1.0
of
of
of
5
U2I
U2I
AU48
VSS
AR48
VSS
AL48
VSS
BB47
VSS
AW47
VSS
AN47
VSS
AJ47
VSS
AF47
D D
C C
B B
A A
VSS
AD47
VSS
AB47
VSS
Y47
VSS
T47
VSS
N47
VSS
L47
VSS
G47
VSS
BD46
VSS
BA46
VSS
AY46
VSS
AV46
VSS
AR46
VSS
AM46
VSS
V46
VSS
R46
VSS
P46
VSS
H46
VSS
F46
VSS
BF44
VSS
AH44
VSS
AD44
VSS
AA44
VSS
Y44
VSS
U44
VSS
T44
VSS
M44
VSS
F44
VSS
BC43
VSS
AV43
VSS
AU43
VSS
AM43
VSS
J43
VSS
C43
VSS
BG42
VSS
AY42
VSS
AT42
VSS
AN42
VSS
AJ42
VSS
AE42
VSS
N42
VSS
L42
VSS
BD41
VSS
AU41
VSS
AM41
VSS
AH41
VSS
AD41
VSS
AA41
VSS
Y41
VSS
U41
VSS
T41
VSS
M41
VSS
G41
VSS
B41
VSS
BG40
VSS
BB40
VSS
AV40
VSS
AN40
VSS
H40
VSS
E40
VSS
AT39
VSS
AM39
VSS
AJ39
VSS
AE39
VSS
N39
VSS
L39
VSS
B39
VSS
BH38
VSS
BC38
VSS
BA38
VSS
AU38
VSS
AH38
VSS
AD38
VSS
AA38
VSS
Y38
VSS
U38
VSS
T38
VSS
J38
VSS
F38
VSS
C38
VSS
BF37
VSS
BB37
VSS
AW37
VSS
AT37
VSS
AN37
VSS
AJ37
VSS
H37
VSS
C37
VSS
BG36
VSS
BD36
VSS
AK15
VSS
AU36
VSS
CANTIGA ES_FCBGA1329
CANTIGA ES_FCBGA1329
VSS
VSS
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
4
AM36 AE36 P36 L36 J36 F36 B36 AH35 AA35 Y35 U35 T35 BF34 AM34 AJ34 AF34 AE34 W34 B34 A34 BG33 BC33 BA33 AV33 AR33 AL33 AH33 AB33 P33 L33 H33 N32 K32 F32 C32 A31 AN29 T29 N29 K29 H29 F29 A29 BG28 BD28 BA28 AV28 AT28 AR28 AJ28 AG28 AE28 AB28 Y28 P28 K28 H28 F28 C28 BF26 AH26 AF26 AB26 AA26 C26 B26 BH25 BD25 BB25 AV25 AR25 AJ25 AC25 Y25 N25 L25 J25 G25 E25 BF24 AD12 AY24 AT24 AJ24 AH24 AF24 AB24 R24 L24 K24 J24 G24 F24 E24 BH23 AG23 Y23 B23 A23 AJ6
3
U2J
U2J
BG21
VSS
L12
VSS
AW21
VSS
AU21
VSS
AP21
VSS
AN21
VSS
AH21
VSS
AF21
VSS
AB21
VSS
R21
VSS
M21
VSS
J21
VSS
G21
VSS
BC20
VSS
BA20
VSS
AW20
VSS
AT20
VSS
AJ20
VSS
AG20
VSS
Y20
VSS
N20
VSS
K20
VSS
F20
VSS
C20
VSS
A20
VSS
BG19
VSS
A18
VSS
BG17
VSS
BC17
VSS
AW17
VSS
AT17
VSS
BA16
AU16 AN16
BG15 AC15
W15
BG14
AA14
BG13 BC13
BA13
AN13
AJ13 AE13
BF12 AV12 AT12
AM12
AA12
BD11
BB11
AY11 AN11 AH11
BG10
AV10
AT10
AJ10
AE10
AA10
AM9
R17 M17 H17 C17
N16
K16
G16
E16
A15
C14
N13
L13
G13
E13
J12
A12
Y11 N11 G11 C11
M10 BF9 BC9 AN9
AD9
G9
B9 BH8 BB8 AV8 AT8
VSS
VSS
VSS VSS VSS VSS
VSS
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
CANTIGA ES_FCBGA1329
CANTIGA ES_FCBGA1329
VSS NCTF
VSS NCTF
VSS SCB
VSS SCB
NC
NC
VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF
VSS_SCB VSS_SCB VSS_SCB VSS_SCB VSS_SCB
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
VSS VSS VSS VSS
2
AH8 Y8 L8 E8 B8 AY7 AU7 AN7 AJ7 AE7 AA7 N7 J7 BG6 BD6 AV6 AT6 AM6 M6 C6 BA5 AH5 AD5 Y5 L5 J5 H5 F5 BE4
BC3 AV3 AL3 R3 P3 F3 BA2 AW2 AU2 AR2 AP2 AJ2 AH2 AF2 AE2 AD2 AC2 Y2 M2 K2 AM1 AA1 P1 H1
U24 U28 U25 U29
AF32 AB32 V32 AJ30 AM29 AF29 AB29 U26 U23 AL20 V20 AC19 AL17 AJ17 AA17 U17
BH48 BH1 A48 C1 A3
E1
NC
D2
NC
C3
NC
B4
NC
A5
NC
A6
NC
A43
NC
A44
NC
B45
NC
C46
NC
D47
NC
B47
NC
A46
NC
F48
NC
E48
NC
C48
NC
B48
NC
1
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2007/08/28 2006/03/10
2007/08/28 2006/03/10
2007/08/28 2006/03/10
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
2
Date: Sheet
Compal Electronics, Inc.
Cantiga(6/6)-PWR/GND
Cantiga(6/6)-PWR/GND
Cantiga(6/6)-PWR/GND
Montevina Blade UMA LA4105P
Montevina Blade UMA LA4105P
Montevina Blade UMA LA4105P
1
1.0
1.0
14 45Saturday, July 18, 2009
14 45Saturday, July 18, 2009
14 45Saturday, July 18, 2009
1.0
of
of
of
5
DDR_A_DQS#[0..7]<10>
DDR_A_D[0..63]<10>
DDR_A_DM[0..7]<10>
DDR_A_DQS[0..7]<10>
DDR_A_MA[0..14]<10>
D D
C C
B B
A A
Layout Note: Place near JDIMM1
+1.5V
2.2U_0805_16V4Z
2.2U_0805_16V4Z
C152
C152
1
2
Layout Note: Place near JDIMM1.203 & JDIMM1.204
+0.75V
1U_0603_10V4Z
1U_0603_10V4Z
C159
C159
1
2
2.2U_0805_16V4Z
2.2U_0805_16V4Z
2.2U_0805_16V4Z
2.2U_0805_16V4Z
2.2U_0805_16V4Z
C147
C147
1
2
1U_0603_10V4Z
1U_0603_10V4Z
1U_0603_10V4Z
1U_0603_10V4Z
C160
C160
1
2
+V_DDR3_DIMM_REF<16>
2.2U_0805_16V4Z
C153
C153
C154
C154
1
1
2
2
1U_0603_10V4Z
1U_0603_10V4Z
10U_0805_6.3V6M
10U_0805_6.3V6M
C161
C161
C162
C162
C163
1
2
C163
1
1
2
2
2.2U_0805_16V4Z
2.2U_0805_16V4Z
1
2
+V_DDR3_DIMM_REF
2.2U_0805_16V4Z
2.2U_0805_16V4Z
Layout Note: Place these 4 caps near Command and Control signals of DIMMA
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2.2U_0805_16V4Z
2.2U_0805_16V4Z
C155
C155
C158
C158
1
1
2
2
+1.5V
12
R1108
R1108
1K_0402_1%
1K_0402_1%
0.1U_0402_16V4Z
0.1U_0402_16V4Z
12
C165
C165
C164
C164
1
1
2
R1109
R1109 1K_0402_1%
1K_0402_1%
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
C148
C148
C156
C156
1
2
+V_DDR3_DIMM_REF
4
+V_DDR3_DIMM_REF
330U_D2E_2.5VM_R7
330U_D2E_2.5VM_R7
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
C149
C149
1
2
1
C150
C150
C157
C157
1
+
+
2
2
0.1U_0402_10V6K
0.1U_0402_10V6K C166
C166
1
2
DDR_CKE0_DIMMA<9>
DDR_A_BS2<10>
M_CLK_DDR0<9>
M_CLK_DDR#0<9>
DDR_A_BS0<10>
DDR_A_WE#<10>
DDR_A_CAS#<10>
DDR_CS1_DIMMA#<9>
3
2.2U_0603_6.3V4Z
2.2U_0603_6.3V4Z
1
2
DDR_A_D0
C167
C167
DDR_A_D1
DDR_A_DM0
DDR_A_D2 DDR_A_D3
DDR_A_D8 DDR_A_D9
DDR_A_DQS#1 DDR_A_DQS1
DDR_A_D10 DDR_A_D11
DDR_A_D16 DDR_A_D17
DDR_A_DQS#2 DDR_A_DQS2
DDR_A_D18 DDR_A_D19
DDR_A_D24 DDR_A_D25
DDR_A_DM3
DDR_A_D26 DDR_A_D27
DDR_CKE0_DIMMA
+1.5V
DDR_A_BS2
DDR_A_MA12 DDR_A_MA9
DDR_A_MA8 DDR_A_MA5
DDR_A_MA3 DDR_A_MA1
M_CLK_DDR0 M_CLK_DDR1 M_CLK_DDR#0 M_CLK_DDR#1
DDR_A_MA10 DDR_A_BS0
DDR_A_WE# DDR_A_CAS#
DDR_A_MA13 DDR_CS1_DIMMA#
DDR_A_D32 DDR_A_D33
DDR_A_DQS#4 DDR_A_DQS4
DDR_A_D34 DDR_A_D35
DDR_A_D40 DDR_A_D41
DDR_A_DM5
DDR_A_D42 DDR_A_D43
DDR_A_D48 DDR_A_D49
DDR_A_DQS#6 DDR_A_DQS6
DDR_A_D51
DDR_A_D56 DDR_A_D57
DDR_A_DM7
DDR_A_D59
R116 10K_0402_5%
R116 10K_0402_5%
1 2
+3VS
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2.2U_0603_6.3V4Z
2.2U_0603_6.3V4Z
1
1
C171
C171
2
2
2
JDIMM1
JDIMM1
VREF_DQ1VSS1
3
VSS2
5
DQ0
7
DQ1
9
VSS4
11
DM0
13
VSS5
15
DQ2
17
DQ3
19
VSS7
21
DQ8
23
DQ9
25
VSS9
27
DQS#1 DQS129RESET# VSS1131VSS12
33
DQ10
35
DQ11 VSS1337VSS14
39
DQ16
41
DQ17 VSS1543VSS16
45
DQS#2
47
DQS2
49
VSS18
51
DQ18
53
DQ19
55
VSS20
57
DQ24
59
DQ25 VSS2261DQS#3
63
DM3 VSS2365VSS24
67
DQ26
69
DQ27 VSS2571VSS26
73
CKE0
75
VDD1
77
NC1
79
BA2
81
VDD3
83
A12/BC#
85
A9
87
VDD5
89
A8
91
A5
93
VDD7
95
A3
97
A1
99
VDD9
101
CK0
103
CK0#
105
VDD11
107
A10/AP
109
BA0
111
VDD13
113
WE#
115
CAS#
117
VDD15
119
A13
121
S1#
123
VDD17
125
NCTEST
127
VSS27
129
DQ32
131
DQ33
133
VSS29
135
DQS#4
137
DQS4
139
VSS32
141
DQ34
143
DQ35
145
VSS34
147
DQ40
149
DQ41
151
VSS36
153
DM5
155
VSS37
157
DQ42
159
DQ43
161
VSS39
163
DQ48
165
DQ49
167
VSS41
169
DQS#6
171
DQS6
173
VSS44
175
DQ50
177
DQ51
179
VSS46
181
DQ56
183
DQ57
185
VSS48
187
DM7
189
VSS49
191
DQ58
193
DQ59
195
VSS51
197
SA0
199
VDDSPD
201
SA1
203
10K_0402_5%
10K_0402_5%
12
R115
R115
C172
C172
VTT1
205
G1
TYCO_C-2013289
TYCO_C-2013289
CONN@
CONN@
DQ4 DQ5
VSS3
DQS#0
DQS0
VSS6
DQ6
DQ7 VSS8 DQ12 DQ13
VSS10
DM1
DQ14 DQ15
DQ20 DQ21
DM2
VSS17
DQ22 DQ23
VSS19
DQ28 DQ29
VSS21
DQS3
DQ30 DQ31
CKE1 VDD2
VDD4
VDD6
VDD8
VDD10
CK1 CK1#
VDD12
RAS#
VDD14
ODT0
VDD16
ODT1
NC2
VDD18
VREF_CA
VSS28
DQ36 DQ37
VSS30
DM4
VSS31
DQ38 DQ39
VSS33
DQ44 DQ45
VSS35
DQS#5
DQS5
VSS38
DQ46 DQ47
VSS40
DQ52 DQ53
VSS42
DM6
VSS43
DQ54 DQ55
VSS45
DQ60 DQ61
VSS47
DQS#7
DQS7
VSS50
DQ62 DQ63
VSS52
EVENT#
SDA
SCL
VTT2
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72
74 76 78
A15
80
A14
82 84
A11
86
A7
88 90
A6
92
A4
94 96
A2
98
A0
100 102 104 106 108
BA1
110 112 114
S0#
116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204
206
G2
DDR_A_D4 DDR_A_D5
DDR_A_DQS#0 DDR_A_DQS0
DDR_A_D6 DDR_A_D7
DDR_A_D12 DDR_A_D13
DDR_A_DM1 SM_DRAMRST#
DDR_A_D14 DDR_A_D15
DDR_A_D20 DDR_A_D21
DDR_A_DM2
DDR_A_D22 DDR_A_D23
DDR_A_D28 DDR_A_D29
DDR_A_DQS#3 DDR_A_DQS3
DDR_A_D30 DDR_A_D31
DDR_CKE1_DIMMA
R1107 0_0402_5%@R1107 0_0402_5%@
1 2
DDR_A_MA14
DDR_A_MA11 DDR_A_MA7
DDR_A_MA6 DDR_A_MA4
DDR_A_MA2 DDR_A_MA0
DDR_A_BS1 DDR_A_RAS#
DDR_CS0_DIMMA# M_ODT0
M_ODT1
DDR_A_D36 DDR_A_D37
DDR_A_DM4
DDR_A_D38 DDR_A_D39
DDR_A_D44 DDR_A_D45
DDR_A_DQS#5 DDR_A_DQS5
DDR_A_D46 DDR_A_D47
DDR_A_D52 DDR_A_D53
DDR_A_DM6
DDR_A_D54 DDR_A_D55DDR_A_D50
DDR_A_D60 DDR_A_D61
DDR_A_DQS#7 DDR_A_DQS7
DDR_A_D62DDR_A_D58 DDR_A_D63
PM_EXTTS#0 CLK_SMBDATA CLK_SMBCLK
+0.75V
SM_DRAMRST# <9,16>
DDR_CKE1_DIMMA <9>
M_CLK_DDR1 <9> M_CLK_DDR#1 <9>
DDR_A_BS1 <10> DDR_A_RAS# <10>
DDR_CS0_DIMMA# <9> M_ODT0 <9>
M_ODT1 <9>
+V_DDR3_DIMM_REF
2.2U_0805_16V4Z
2.2U_0805_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
C146
C146
2
PM_EXTTS#0 <9>
CLK_SMBDATA <16,17,24>
CLK_SMBCLK <16,17,24>
+1.5V
1
C151
C151
2
1
SO-DIMM A
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2006/02/13 2006/03/10
2006/02/13 2006/03/10
2006/02/13 2006/03/10
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
2
Date: Sheet
Compal Electronics, Inc.
DDRIII-SODIMM SLOT1
DDRIII-SODIMM SLOT1
DDRIII-SODIMM SLOT1
Montevina Blade UMA LA4105P
Montevina Blade UMA LA4105P
Montevina Blade UMA LA4105P
1
1.0
1.0
15 45Saturday, July 18, 2009
15 45Saturday, July 18, 2009
15 45Saturday, July 18, 2009
1.0
of
of
of
5
DDR_B_DQS#[0..7]<10>
DDR_B_D[0..63]<10>
DDR_B_DM[0..7]<10>
DDR_B_DQS[0..7]<10>
DDR_B_MA[0..14]<10>
D D
Layout Note: Place near JDIMM2
+1.5V
2.2U_0805_16V4Z
2.2U_0805_16V4Z
2.2U_0805_16V4Z
2.2U_0805_16V4Z
2.2U_0805_16V4Z
C C
B B
A A
Layout Note: Place near JDIMM2.203 & JDIMM2.204
+0.75V
1U_0603_10V4Z
1U_0603_10V4Z
C175
C175
C174
C174
1
1
2
2
1U_0603_10V4Z
1U_0603_10V4Z
1U_0603_10V4Z
1U_0603_10V4Z
C186
C186
C185
C185
1
1
2
2
5
2.2U_0805_16V4Z
2.2U_0805_16V4Z
2.2U_0805_16V4Z
C176
C176
1
2
1U_0603_10V4Z
1U_0603_10V4Z
C187
C187
1
2
2.2U_0805_16V4Z
2.2U_0805_16V4Z
C183
C183
C177
C177
1
1
2
2
10U_0805_6.3V6M
10U_0805_6.3V6M
C189
C189
C188
C188
1
1
2
2
Layout Note: Place these 4 caps near Command and Control signals of DIMMB
2.2U_0805_16V4Z
2.2U_0805_16V4Z
C184
C184
1
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
C178
C178
1
2
4
+V_DDR3_DIMM_REF<15>
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
C180
C180
C179
C179
1
2
C181
C181
1
1
2
2
+1.5V
+3VS
C192
C192
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
+V_DDR3_DIMM_REF
JDIMM2
JDIMM2
VREF_DQ1VSS1
3
DDR_B_D0
2.2U_0805_16V4Z
2.2U_0805_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
C173
C173
1
1
2
2
DDR_CKE2_DIMMB<9> DDR_CKE3_DIMMB <9>
DDR_B_BS2<10>
M_CLK_DDR2<9>
M_CLK_DDR#2<9>
DDR_B_BS0<10>
DDR_B_WE#<10>
DDR_B_CAS#<10>
DDR_CS3_DIMMB#<9>
+3VS
1
1
2
2
C1403
C1403
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2.2U_0603_6.3V4Z
2.2U_0603_6.3V4Z
3
DDR_B_D1
DDR_B_DM0
C182
C182
DDR_B_D2 DDR_B_D3
DDR_B_D8 DDR_B_D9
DDR_B_DQS#1 DDR_B_DQS1
DDR_B_D10 DDR_B_D11
DDR_B_D16 DDR_B_D17
DDR_B_DQS#2 DDR_B_DQS2
DDR_B_D18 DDR_B_D19
DDR_B_D24 DDR_B_D25
DDR_B_DM3
DDR_B_D26 DDR_B_D27
DDR_CKE2_DIMMB
DDR_B_BS2
DDR_B_MA12 DDR_B_MA9
DDR_B_MA8 DDR_B_MA6 DDR_B_MA5
DDR_B_MA3 DDR_B_MA1
M_CLK_DDR2 M_CLK_DDR#2
DDR_B_MA10 DDR_B_BS0
DDR_B_WE# DDR_B_CAS#
DDR_B_MA13 DDR_CS3_DIMMB#
DDR_B_D32 DDR_B_D33
DDR_B_DQS#4 DDR_B_DQS4
DDR_B_D34 DDR_B_D35
DDR_B_D40 DDR_B_D41
DDR_B_DM5
DDR_B_D42 DDR_B_D43
DDR_B_D48 DDR_B_D49
DDR_B_DQS#6 DDR_B_DQS6
DDR_B_D50 DDR_B_D51
DDR_B_D56 DDR_B_D57
DDR_B_DM7
DDR_B_D58 DDR_B_D59
R1111 10K_0402_5%
R1111 10K_0402_5%
R1112 10K_0402_5%
R1112 10K_0402_5%
12
12
2006/02/13 2006/03/10
2006/02/13 2006/03/10
2006/02/13 2006/03/10
VSS2
5
DQ0
7
DQ1
9
VSS4
11
DM0
13
VSS5
15
DQ2
17
DQ3
19
VSS7
21
DQ8
23
DQ9
25
VSS9
27
DQS#1 DQS129RESET#
31
VSS11
33
DQ10
35
DQ11
37
VSS13
39
DQ16
41
DQ17
43
VSS15
45
DQS#2
47
DQS2
49
VSS18
51
DQ18
53
DQ19
55
VSS20
57
DQ24
59
DQ25 VSS2261DQS#3
63
DM3
65
VSS23
67
DQ26
69
DQ27
71
VSS25
73
CKE0
75
VDD1
77
NC1
79
BA2
81
VDD3
83
A12/BC#
85
A9
87
VDD5
89
A8
91
A5
93
VDD7
95
A3
97
A1
99
VDD9
101
CK0
103
CK0#
105
VDD11
107
A10/AP
109
BA0
111
VDD13
113
WE#
115
CAS#
117
VDD15
119
A13
121
S1#
123
VDD17
125
NCTEST
127
VSS27
129
DQ32
131
DQ33
133
VSS29
135
DQS#4
137
DQS4
139
VSS32
141
DQ34
143
DQ35
145
VSS34
147
DQ40
149
DQ41
151
VSS36
153
DM5
155
VSS37
157
DQ42
159
DQ43
161
VSS39
163
DQ48
165
DQ49
167
VSS41
169
DQS#6
171
DQS6
173
VSS44
175
DQ50
177
DQ51
179
VSS46
181
DQ56
183
DQ57
185
VSS48
187
DM7
189
VSS49
191
DQ58
193
DQ59
195
VSS51
197
SA0
199
VDDSPD
201
SA1
203
VTT1
205
G1
TYCO_C-2013310
TYCO_C-2013310
CONN@
CONN@
SO-DIMM B
Deciphered Date
Deciphered Date
Deciphered Date
VSS3
DQS#0
DQS0
VSS6
VSS8 DQ12 DQ13
VSS10
VSS12
DQ14 DQ15
VSS14
DQ20 DQ21
VSS16
VSS17
DQ22 DQ23
VSS19
DQ28 DQ29
VSS21
DQS3
VSS24
DQ30 DQ31
VSS26
CKE1 VDD2
VDD4
VDD6
VDD8
VDD10
CK1#
VDD12
RAS#
VDD14
ODT0
VDD16
ODT1
VDD18
VREF_CA
VSS28
DQ36 DQ37
VSS30
VSS31
DQ38 DQ39
VSS33
DQ44 DQ45
VSS35
DQS#5
DQS5
VSS38
DQ46 DQ47
VSS40
DQ52 DQ53
VSS42
VSS43
DQ54 DQ55
VSS45
DQ60 DQ61
VSS47
DQS#7
DQS7
VSS50
DQ62 DQ63
VSS52
EVENT#
VTT2
DQ4 DQ5
DQ6 DQ7
DM1
DM2
NC2
DM4
DM6
SDA
2
2
DDR_B_D4
4
DDR_B_D5
6 8
DDR_B_DQS#0
10
DDR_B_DQS0
12 14
DDR_B_D6
16
DDR_B_D7
18 20
DDR_B_D12
22
DDR_B_D13
24 26
DDR_B_DM1
28
SM_DRAMRST#
30 32
DDR_B_D14
34
DDR_B_D15
36 38
DDR_B_D20
40
DDR_B_D21
42 44
DDR_B_DM2
46 48
DDR_B_D22
50
DDR_B_D23
52 54
DDR_B_D28
56
DDR_B_D29
58 60
DDR_B_DQS#3
62
DDR_B_DQS3
64 66
DDR_B_D30
68
DDR_B_D31
70 72
DDR_CKE3_DIMMB
74 76 78
A15
80
A14
82 84
A11
86
A7
88 90
A6
92
A4
94 96
A2
98
A0
100 102
CK1
104 106 108
BA1
110 112 114
S0#
116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202
SCL
204
206
G2
2
R1110 0_0402_5%@R1110 0_0402_5%@
DDR_B_MA14
DDR_B_MA11 DDR_B_MA7
DDR_B_MA4
DDR_B_MA2 DDR_B_MA0
M_CLK_DDR3 M_CLK_DDR#3
DDR_B_BS1 DDR_B_RAS#
DDR_CS2_DIMMB# M_ODT2
M_ODT3
DDR_B_D36 DDR_B_D37
DDR_B_DM4
DDR_B_D38 DDR_B_D39
DDR_B_D44 DDR_B_D45
DDR_B_DQS#5 DDR_B_DQS5
DDR_B_D46 DDR_B_D47
DDR_B_D52 DDR_B_D53
DDR_B_DM6
DDR_B_D54 DDR_B_D55
DDR_B_D60 DDR_B_D61
DDR_B_DQS#7 DDR_B_DQS7
DDR_B_D62 DDR_B_D63
PM_EXTTS#1 CLK_SMBDATA CLK_SMBCLK
+0.75V
SM_DRAMRST# <9,15>
1 2
M_CLK_DDR3 <9> M_CLK_DDR#3 <9>
DDR_B_BS1 <10> DDR_B_RAS# <10>
DDR_CS2_DIMMB# <9> M_ODT2 <9>
M_ODT3 <9>
+V_DDR3_DIMM_REF
PM_EXTTS#1 <9>
CLK_SMBDATA <15,17,24>
CLK_SMBCLK <15,17,24>
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet
Date: Sheet
1
+1.5V
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2.2U_0805_16V4Z
2.2U_0805_16V4Z
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
DDRIII-SODIMM SLOT2
DDRIII-SODIMM SLOT2
DDRIII-SODIMM SLOT2
Montevina Blade UMA LA4105P
Montevina Blade UMA LA4105P
Montevina Blade UMA LA4105P
1
1
C191
C191
C190
C190
2
2
16 45Saturday, July 18, 2009
16 45Saturday, July 18, 2009
16 45Saturday, July 18, 2009
1
1.0
1.0
1.0
of
of
5
PCI
FSC
FSB
CLKSEL2
CLKSEL1
00
00
0
1
D D
0
1
0
1
0
1
1
1
1
1
FSA
CPU_BSEL0<7>
C C
FSB
CPU_BSEL1<7>
B B
FSC
CPU_BSEL2<7>
FSA
CLKSEL0
0
1
0
1
0
1
0
1
R128
R128
1 2
2.2K_0402_5%
2.2K_0402_5% R138
R138
1 2
0_0402_5%
0_0402_5%
R154
R154
1 2
0_0402_5%
0_0402_5%
R164
R164
1 2
10K_0402_5%
10K_0402_5% R171
R171
1 2
0_0402_5%
0_0402_5%
CPU MHz
266
133
200
166
333
100
400
+VCCP
+VCCP
12
1 2
12
1 2
1 2
12
12
1 2
12
MHz
100
100
100
100
100
100
100
R123
R123
1 2
56_0402_5%
56_0402_5%
CLRP1
CLRP1 NO SHORT PADS
NO SHORT PADS
R129
R129 1K_0402_5%
1K_0402_5%
@
@
R139
R139 1K_0402_5%
1K_0402_5%
@
@
R143
R143 1K_0402_5%
1K_0402_5%
R150
R150 1K_0402_5%
1K_0402_5%
@
@
R157
R157 0_0402_5%
0_0402_5%
@
@
R163
R163 1K_0402_5%
1K_0402_5%
R165
R165 1K_0402_5%
1K_0402_5%
@
@
R174
R174 0_0402_5%
0_0402_5%
SRC
REF
MHz
MHz
33.3
14.318 96.0 48.0
14.318
33.3
14.318
33.3
14.318
33.3
14.318
33.3
14.318
33.3
14.318
33.3
Reserved
+VCCP
MCH_CLKSEL0 <9>
MCH_CLKSEL1 <9>
MCH_CLKSEL2 <9>
DOT_96 MHz
96.0
96.0
96.0
96.0
96.0
96.0
NB
CPU
CLK_ENABLE#<43>
CK_PWRGD<22>
CLK_14M_ICH<22>
CLK_DEBUG_PORT_1<26>
CLK_DEBUG_PORT_0
CLK_PCI_EC<32>
CLK_PCI_ICH<20>
Change 33M and 48M damping to 39M by EMI request
NB (UMA)
4
USB MHz
48.0
48.0
48.0
48.0
48.0
48.0
CLKREQ#_7<9>
CLK_MCH_BCLK<9> CLK_CPU_BCLK#<6> CLK_CPU_BCLK<6>
VGATE<22,43>
R141 0_0402_5%@R141 0_0402_5%@ R142 0_0402_5%@R142 0_0402_5%@ R140 0_0402_5%R140 0_0402_5%
No Debug port anymore
R147 33_0402_1%R147 33_0402_1%
CLK_SMBDATA<15,16,24>
CLK_SMBCLK<15,16,24>
R393 39_0402_1%
R393 39_0402_1% R155 39_0402_1%
R155 39_0402_1%
R158 33_0402_1%R158 33_0402_1%
R161 33_0402_1%R161 33_0402_1%
CLK_48M_ICH<22>
CLK_MCH_DREFCLK<9> CLK_MCH_DREFCLK#<9>
+3VS
Routing the trace at least 10mil
Y1
Y1
1 2
2
C213
C213
18P_0402_50V8J
18P_0402_50V8J
1
Vendor suggests 22pF
R126 475_0402_1%R126 475_0402_1%
1 2
R130 0_0402_5%R130 0_0402_5%
1 2
R132 0_0402_5%R132 0_0402_5%
1 2
R134 0_0402_5%R134 0_0402_5%
1 2
R136 0_0402_5%R136 0_0402_5%
1 2
1 2 1 2 1 2
1 2
T44T44
1 2 1 2 1 2
1 2
R167 39_0402_1%
R167 39_0402_1%
1 2
T76T76
R173 0_0402_5%R173 0_0402_5%
1 2
R175 0_0402_5%R175 0_0402_5%
1 2
+3VS_CK505
R121
R121
1 2
0_0805_5%
0_0805_5%
CLK_XTAL_OUT
CLK_XTAL_IN
14.318MHZ_16PF_7A14300083
14.318MHZ_16PF_7A14300083
2
C214
C214 18P_0402_50V8J
18P_0402_50V8J
1
+3VS_CK505
R_CKPWRGD FSB
CLK_XTAL_OUT CLK_XTAL_IN
FSC REF1 CLK_SMBDATA CLK_SMBCLK
PCI2_1 PCI2_TME 27_SEL PCI_CLK3 ITP_EN
3
1
C199
C199
10U_0805_10V4Z
10U_0805_10V4Z
2
R_CLKREQ#_7 R_MCH_BCLK# R_MCH_BCLK R_CPU_BCLK# R_CPU_BCLK
U3
U3
1
CKPWRGD/PD#
2
FS_B/TEST_MODE
3
VSS_REF
4
XTAL_OUT
5
XTAL_IN
6
VDD_REF
7
REF_0/FS_C/TEST_
8
REF_1
9
SDA
10
SCL
11
NC
12
VDD_PCI
13
PCI_1
14
PCI_2
15
PCI_3
16
PCI_4/SEL_LCDCL
17
PCIF_5/ITP_EN
18
VSS_PCI
+3VS_CK505
FSA R_CLK_48M_CRUSB
+1.05VS_CK505
R_MCH_DREFCLK R_MCH_DREFCLK# SSCDREFCLK#
1
C200
C200
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
+VCCP
+3VS_CK505
72
71
70
69
68
67
66
CPU_0
CPU_1
CPU_0#
CPU_1#
VSS_CPU
VDD_CPU
VDD_CPU_IO
VDD_4819USB_0/FS_A20USB_1/CLKREQ_A#21VSS_4822VDD_IO23SRC_0/DOT_9624SRC_0#/DOT_96#25VSS_IO26VDD_PLL327LCDCLK/27M28LCDCLK#/27M_SS29VSS_PLL330VDD_PLL3_IO31SRC_232SRC_2#33VSS_SRC34SRC_335SRC_3#
R122
R122
1 2
0_0805_5%
0_0805_5%
+1.05VS_CK505
65
64
63
62
CLKREQ_7#
VDD_SRC_IO
SRC_8/CPU_ITP
SRC_8#/CPU_ITP#
1
C201
C201
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
+1.05VS_CK505
1
C206
C206
2
10U_0805_10V4Z
10U_0805_10V4Z
61
60
59
58
57
56
SRC_7
SRC_6
SRC_7#
SRC_6#
VSS_SRC
CLKREQ_6#
+1.05VS_CK505
Place close to U51
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
C207
C207
2
R_MCH_3GPLL R_MCH_3GPLL# R_CLKREQ#_6 R_CLK_PCIE_MCARD2 R_CLK_PCIE_MCARD2#
+3VS_CK505
55
VDD_SRC
PCI_STOP#
CPU_STOP#
VDD_SRC_IO
SRC_10#
SRC_10
CLKREQ_10#
SRC_11
SRC_11#
CLKREQ_11#
SRC_9#
SRC_9
CLKREQ_9#
VSS_SRC
CLKREQ_4#
SRC_4#
SRC_4
VDD_SRC_IO
CLKREQ_3#
SLG8SP553VTR_QFN72_10x10
SLG8SP553VTR_QFN72_10x10
36
R_PCIE_SATA# R_PCIE_SATA
R_PCIE_ICH# R_PCIE_ICH
SSCDREFCLK
1
C202
C202
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
1
C208
C208
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
+1.05VS_CK505
54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37
2
1
C203
C203
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
10U_0805_10V4Z
10U_0805_10V4Z
1
C209
C209
2
R127 0_0402_5%R127 0_0402_5% R131 0_0402_5%R131 0_0402_5% R133 475_0402_1%R133 475_0402_1% R135 0_0402_5%R135 0_0402_5% R137 0_0402_5%R137 0_0402_5%
H_STP_PCI# H_STP_CPU#
R_CLK_PCIE_MCARD0# R_CLK_PCIE_MCARD0 R_CLKREQ#_10 R_CLK_SRC11 R_CLK_SRC11#
R_CLK_PCIE_LAN# R_CLK_PCIE_LAN R_CLKREQ#_9
R_CLKREQ#_4 R_CLK_PCIE_NCARD# R_CLK_PCIE_NCARD
R_CLKREQ#_C
R166 0_0402_5%R166 0_0402_5% R168 0_0402_5%R168 0_0402_5%
R170 0_0402_5%R170 0_0402_5% R172 0_0402_5%R172 0_0402_5%
R176 0_0402_5%R176 0_0402_5% R177 0_0402_5%R177 0_0402_5%
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
C210
C210
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1 2 1 2 1 2 1 2 1 2
R725 0_0402_5%R725 0_0402_5%
1 2
R726 0_0402_5%R726 0_0402_5%
1 2
1 2 1 2
1 2 1 2
1 2 1 2
1
C204
C204
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
1
C211
C211
2
R144 0_0402_5%
R144 0_0402_5% R145 0_0402_5%
R145 0_0402_5% R146 475_0402_1%R146 475_0402_1%
R152 0_0402_5%R152 0_0402_5% R153 0_0402_5%R153 0_0402_5% R738 475_0402_1%R738 475_0402_1%
R156 475_0402_1%R156 475_0402_1% R159 0_0402_5%
R159 0_0402_5% R160 0_0402_5%
R160 0_0402_5%
R162 475_0402_1%R162 475_0402_1%
1
2
1
C212
C212
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
CLK_MCH_3GPLL <9> CLK_MCH_3GPLL# <9>CLK_MCH_BCLK#<9>
CLKREQ#_6 <26>
CLK_PCIE_MCARD2 <26> CLK_PCIE_MCARD2# <26>
H_STP_PCI# <22> H_STP_CPU# <22>
1 2 1 2 1 2
1 2 1 2 1 2
1 2 1 2 1 2
1 2
NewC@
NewC@ NewC@
NewC@
CLK_PCIE_SATA# <21> CLK_PCIE_SATA <21>
CLK_PCIE_ICH# <22> CLK_PCIE_ICH <22>
MCH_SSCDREFCLK# <9> MCH_SSCDREFCLK <9>
C205
C205
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2MiniC@
2MiniC@ 2MiniC@
2MiniC@
CLK_PCIE_MCARD0# <26> CLK_PCIE_MCARD0 <26>
CLKREQ#_10 <26> CLK_SRC11 <27> CLK_SRC11# <27>
CLK_PCIE_LAN# <25> CLK_PCIE_LAN <25>
CLKREQ#_9 <25>
CLKREQ#_4 <26>
CLK_PCIE_NCARD# <26> CLK_PCIE_NCARD <26>
CLKREQ#_C <22>
1
XDP/ITP
3G_PLL
MiniCard_2(WLAN)
MiniCard_0
Cardreader
LAN
New Card
SATA
ICH
NB_SSC (UMA)
+3VS
R179
R178
R178
2.2K_0402_5%
2.2K_0402_5%
2007/08/28 2006/03/10
2007/08/28 2006/03/10
2007/08/28 2006/03/10
R179
2.2K_0402_5%
2.2K_0402_5%
CLK_SMBDATA
CLK_SMBCLK
Deciphered Date
Deciphered Date
Deciphered Date
02/13 Add 12P on CLK_14M_ICH for WWAN noise
C215
@C215
@
5P_0402_50V8C
5P_0402_50V8C
C216
C216
12P_0402_50V8J
12P_0402_50V8J
C217
@C217
@
4.7P_0402_50V8C
4.7P_0402_50V8C C218
@C218
@
4.7P_0402_50V8C
4.7P_0402_50V8C C219
@C219
@
5P_0402_50V8C
5P_0402_50V8C
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
2
Date: Sheet
Compal Electronics, Inc.
Clock Generator CK505
Clock Generator CK505
Clock Generator CK505
Montevina Blade UMA LA4105P
Montevina Blade UMA LA4105P
Montevina Blade UMA LA4105P
CLK_48M_ICH
12
CLK_14M_ICH
12
CLK_PCI_ICH
12
CLK_PCI_EC
12
CLK_DEBUG_PORT_0
12
1
1.0
1.0
1.0
of
17 45Saturday, July 18, 2009
of
17 45Saturday, July 18, 2009
of
17 45Saturday, July 18, 2009
Q3A
Q3A
6 1
5
2N7002DW-7-F_SOT363-6
2N7002DW-7-F_SOT363-6
4
<BOM Structure>
<BOM Structure>
+3VS
3
2
ITP_EN
PCI_CLK3
A A
0 = SRC8/SRC8# 1 = ITP/ITP# 0 = Enable DOT96 & SRC1(UMA) 1 = Enable SRC0 & 27MHz(DIS)
+3VS +3VS
12
R180
R180 10K_0402_5%
10K_0402_5%
ITP_EN PCI_CLK3
12
@
@
R182
R182 10K_0402_5%
10K_0402_5%
5
12
@
@
R181
R181 10K_0402_5%
10K_0402_5%
12
R183
R183 10K_0402_5%
10K_0402_5%
+3VS
ICH_SMBDATA<22,26>
SB, MINI PCI
ICH_SMBCLK<22,26>
4
Q3B
Q3B
3
2N7002DW-7-F_SOT363-6
2N7002DW-7-F_SOT363-6
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
1 1
CRT Connector
+5VS +5VS
C221
C221
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1 2
1
5
U4
U4 SN74AHCT1G125GW_SOT353-5
SN74AHCT1G125GW_SOT353-5
2 2
CRT_HSYNC<11>
CRT_VSYNC<11>
CRT_HSYNC
CRT_VSYNC
P
A2Y
G
3
4
OE#
B
C222
C222
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1 2
HSYNC_G_A
1
5
P
A2Y
G
3
VSYNC_G_A D_VSYNC
4
OE#
U5
U5 SN74AHCT1G125GW_SOT353-5
SN74AHCT1G125GW_SOT353-5
R184
R184
1 2
R189
R189
1 2
GREEN<34>
D_HSYNC<34>
D_VSYNC<34>
0_0603_5%
0_0603_5%
0_0603_5%
0_0603_5%
C
D4
D4
2 1
RB491D_SC59-3
RB491D_SC59-3
RED<34>
BLUE<34>
RED
GREEN
BLUE
D_HSYNC
@
@
1
C223
C223
5P_0402_50V8C
5P_0402_50V8C
2
@
@
1
C224
C224
5P_0402_50V8C
5P_0402_50V8C
2
F1
F1
1.1A_6VDC_FUSE
1.1A_6VDC_FUSE
2.2K_0402_5%
2.2K_0402_5%
D_DDCDATA
D_DDCCLK
21
6
11
1 7
12
2 8
13
3 9
14
4 10 15
5
SUYIN_070546FR015S263ZR
SUYIN_070546FR015S263ZR
CONN@
CONN@
12
R185
R185
2.2K_0402_5%
2.2K_0402_5%
D_DDCDATA <34> D_DDCCLK <34>
W=40mils
0.1U_0402_16V4Z
0.1U_0402_16V4Z C220
C220
JCRT1
JCRT1
R186
R186
D
+CRTVDD+RCRT_VCC+5VS
1
2
16 17
12
6 1
Q5A
Q5A
2N7002DW-7-F_SOT363-6
2N7002DW-7-F_SOT363-6
+3VS+CRTVDD +CRTVDD
2
2N7002DW-7-F_SOT363-6
2N7002DW-7-F_SOT363-6
E
BLUE GREEN RED
D5
@D5
@
+3VS
12
12
R187
R187
2.2K_0402_5%
2.2K_0402_5%
5
3
4
Q5B
Q5B
1
2
3
DAN217T146_SC59-3
DAN217T146_SC59-3
R188
R188
2.2K_0402_5%
2.2K_0402_5%
3VDDCDA
3VDDCCL
@D6
@
D6
1
2
3
D7
@D7
@
2
DAN217T146_SC59-3
DAN217T146_SC59-3
3VDDCDA <11>
3VDDCCL <11>
Place close to JCRT1
1
3
+CRTVDD
DAN217T146_SC59-3
DAN217T146_SC59-3
CRT Termination/EMI Filter
3 3
M_RED<11>
M_GREEN<11>
M_BLUE<11>
4 4
A
B
12
12
R195
R195
R196
R196
150_0402_1%
150_0402_1%
C_RED
C_GRN
22P_0402_50V8J
22P_0402_50V8J
22P_0402_50V8J
12
R197
R197
150_0402_1%
150_0402_1%
150_0402_1%
150_0402_1%
22P_0402_50V8J
1
1
1
2
2
2
C227
@C227
@
C226
@C226
@
C225
@C225
@
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
11/07 Change CRT lounting NB-->Docking-->CRT connector
L2
L2
1 2
HLC0603CSCCR11JT_0603
HLC0603CSCCR11JT_0603
L3
L3
1 2
HLC0603CSCCR11JT_0603
HLC0603CSCCR11JT_0603
L4
L4
1 2
HLC0603CSCCR11JT_0603
HLC0603CSCCR11JT_0603
22P_0402_50V8J
22P_0402_50V8J
2007/08/28 2006/07/26
2007/08/28 2006/07/26
2007/08/28 2006/07/26
10P_0402_50V8J
10P_0402_50V8J
1
1
2
2
C228
C228
C229
C229
Deciphered Date
Deciphered Date
Deciphered Date
RED
GREEN
BLUEC_BLU
10P_0402_50V8J
10P_0402_50V8J
10P_0402_50V8J
10P_0402_50V8J
1
2
C230
C230
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
D
Date: Sheet
Compal Electronics, Inc.
CRT Connector
CRT Connector
CRT Connector
Montevina Blade UMA LA4105P
Montevina Blade UMA LA4105P
Montevina Blade UMA LA4105P
18 45Saturday, July 18, 2009
18 45Saturday, July 18, 2009
18 45Saturday, July 18, 2009
E
1.0
1.0
1.0
of
of
of
5
INVPWR_B++LCDVDD+3VS
C236
C236
C235
D D
C C
C235
12
680P_0402_50V7K
680P_0402_50V7K
USB20_P4<22> USB20_N4<22>
C237
C237
1
12
2
680P_0402_50V7K
680P_0402_50V7K
680P_0402_50V7K
680P_0402_50V7K
USB20_P4 USB20_N4
11/17 Delete LVDS B
LVDS CONN & USB Camera + Dig Mic
JLVDS1
JLVDS1
+3VS
1 3 5 7
9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
GND41GND
ACES_88242-4001
ACES_88242-4001
CONN@
CONN@
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42
4
LVDS_A2­LVDS_A2+ LVDS_A1­LVDS_A1+ LVDS_A0­LVDS_A0+ LVDS_ACLK­LVDS_ACLK+
11/07 Change R727 to 0805 size
DMIC_DAT DMIC_CLK +3V_LOGO
R727
R727
INV_PWM BKOFF# DAC_BRIG
DDC2_CLK DDC2_DATA
680P_0402_50V7K
680P_0402_50V7K
1 2
100_0805_5%
100_0805_5%
+USB_CAM
C435
C435
1
2
1
C434
C434 680P_0402_50V7K
680P_0402_50V7K
2
LVDS_A2- <11> LVDS_A2+ <11> LVDS_A1- <11> LVDS_A1+ <11> LVDS_A0- <11> LVDS_A0+ <11> LVDS_ACLK- <11> LVDS_ACLK+ <11>
DMIC_DAT <28>
DMIC_CLK <28>
+5VS
INV_PWM <32>
BKOFF# <32>
DAC_BRIG <32>
DDC2_CLK <11> DDC2_DATA <11>
3
1
C231
C231
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
02/13 Reserve
BKOFF#
10K_0402_5%
10K_0402_5%
1 2
R245
@R245
@
1
2
C232
C232
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
02/20 Change to 0805 size
12
R198
R198
470_0805_5%
470_0805_5%
61
1M_0402_5%
1M_0402_5%
2
2N7002DW-7-F_SOT363-6
2N7002DW-7-F_SOT363-6 Q8A
Q8A
Limited Current < 1A
ENAVDD<11>
100K_0402_5%
100K_0402_5%
R201
R201
12
Avoid Panel display garbage after power on.
+5VALW+LCDVDD+LCDVDD
12
R199
R199
3
Q8B
Q8B 2N7002DW-7-F_SOT363-6
2N7002DW-7-F_SOT363-6
5
4
R200
R200
100K_0402_5%
100K_0402_5%
C233
C233
4.7U_0805_10V4Z
4.7U_0805_10V4Z
12
1
+LCDVDD
Q7
Q7
SI2301BDS-T1-E3_SOT23-3
SI2301BDS-T1-E3_SOT23-3
1 3
D
1
2
D
C238
C238
0.047U_0402_16V7K
0.047U_0402_16V7K
01/03 Change to 0.047u to meet T1 timing
+3VS
S
S
G
G
C234
C234
1
2
2
4.7U_0805_10V4Z
4.7U_0805_10V4Z
0308_Install all cap for EMI request.
INVPWR_B+B+
LVDS_ACLK+ LVDS_ACLK­DDC2_CLK DDC2_DATA
C1399 100P_0402_50V8J@ C1399 100P_0402_50V8J@
1 2
C1400 100P_0402_50V8J@ C1400 100P_0402_50V8J@
1 2
C1401 100P_0402_50V8J@ C1401 100P_0402_50V8J@
1 2
C1402 100P_0402_50V8J@ C1402 100P_0402_50V8J@
1 2
0831 EMI request
R202
R202
2.2K_0402_5%
2.2K_0402_5%
DDC2_CLK DDC2_DATA
+3VS
1 2
R203
R203
2.2K_0402_5%
2.2K_0402_5%
1 2
Must close JLVDS1pin 24、、、26
DMIC_CLK
DMIC_DAT
1
1
C302
@ C302
@
220P_0402_25V8J
220P_0402_25V8J
2
C303
@C303
@
220P_0402_25V8J
220P_0402_25V8J
2
@
@
L5 0_0805_5%
L5 0_0805_5%
1 2
L6
L6
1 2
FBMA-L11-201209-221LMA30T_0805
FBMA-L11-201209-221LMA30T_0805
0308_Reserve L10 and install L11.
11/09 EMI reserver
B B
USB Camera
+5VALW +USB_CAM
PJP6
@PJP6
@
PAD-OPEN 2x2m
PAD-OPEN 2x2m
10U_0805_6.3V6M
10U_0805_6.3V6M
GPIO20<22>
A A
11/07 Change U42 to 3.9V LDO(Adjustable)
11/07 Change R1091 to 215K,,,R1093 to 100K
C1392
C1392
R441 0_0402_5% @ R441 0_0402_5% @
PAD-OPEN 2x2m
PAD-OPEN 2x2m
2 1
1
2
1 2
11/08 Change C1391、、、C1392 to 0805 size
+USB_CAM is +3.9VS, R1091:215K; R1093:100Kohm
5
PJP5
PJP5
R440
R440
0_0402_5%
0_0402_5%
+5VS
U42
U42
1
IN
2
2 1
1 2
GND
3
SHDN
G916-390T1UF_SOT23-5
G916-390T1UF_SOT23-5
OUT
BYP
5
4
+USB_CAM=1.25(1+R1091/R1093)
12
R1091
R1091 215K_0603_1%
215K_0603_1%
1
C1391
R1093
R1093 100K_0402_1%
100K_0402_1%
C1391
10U_0805_6.3V6M
10U_0805_6.3V6M
2
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2007/08/28 2006/07/26
2007/08/28 2006/07/26
2007/08/28 2006/07/26
Deciphered Date
Deciphered Date
Deciphered Date
2
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
Compal Electronics, Inc.
LCD CONN.
LCD CONN.
LCD CONN.
Montevina Blade UMA LA4105P
Montevina Blade UMA LA4105P
Montevina Blade UMA LA4105P
19 45Saturday, July 18, 2009
19 45Saturday, July 18, 2009
19 45Saturday, July 18, 2009
1
of
of
of
1.0
1.0
1.0
12
4
5
+3VS
R272 8.2K_0402_5%
R272 8.2K_0402_5%
1 2
R273 8.2K_0402_5%
R273 8.2K_0402_5%
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
12
R274 8.2K_0402_5%
R274 8.2K_0402_5%
R275 8.2K_0402_5%
R275 8.2K_0402_5%
R276 8.2K_0402_5%
D D
C C
R276 8.2K_0402_5%
R277 8.2K_0402_5%
R277 8.2K_0402_5%
R278 8.2K_0402_5%
R278 8.2K_0402_5%
R279 8.2K_0402_5%
R279 8.2K_0402_5%
+3VS
R281 8.2K_0402_5%R281 8.2K_0402_5%
R282 8.2K_0402_5%
R282 8.2K_0402_5%
R283 8.2K_0402_5%
R283 8.2K_0402_5%
R284 8.2K_0402_5%
R284 8.2K_0402_5%
R285 8.2K_0402_5%
R285 8.2K_0402_5%
R286 8.2K_0402_5%
R286 8.2K_0402_5%
R287 8.2K_0402_5%
R287 8.2K_0402_5%
R288 8.2K_0402_5%
R288 8.2K_0402_5%
R289 8.2K_0402_5%R289 8.2K_0402_5%
R290 8.2K_0402_5%R290 8.2K_0402_5%
R292 8.2K_0402_5%R292 8.2K_0402_5%
R293 8.2K_0402_5%R293 8.2K_0402_5%
PCI_DEVSEL#
PCI_STOP#
PCI_TRDY#
PCI_FRAME#
PCI_PLOCK#
PCI_IRDY#
PCI_SERR#
PCI_PERR#
PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#
PCI_PIRQE#
PCI_PIRQF#
PCI_PIRQG#
PCI_PIRQH#
PCI_REQ0#
PCI_REQ1#
PCI_REQ2#
PCI_REQ3#
4
U12B
U12B
D11
AD0
C8
AD1
PCI_PIRQA# PCI_PIRQB# PCI_PIRQC# PCI_PIRQD#
D9
E12
E9 C9
E10
B7 C7 C5
G11
F8
F11
E7 A3 D2
F10
D5
D10
B3 F7 C3 F3 F4 C1
G7
H7 D1
G5
H6
G1
H3
J5
E1
J6
C4
ICH9-M ES_FCBGA676
ICH9-M ES_FCBGA676
PCI
PCI
AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31
Interrupt I/F
Interrupt I/F
PIRQA# PIRQB# PIRQC# PIRQD#
REQ0#
GNT0# REQ1#/GPIO50 GNT1#/GPIO51 REQ2#/GPIO52 GNT2#/GPIO53 REQ3#/GPIO54 GNT3#/GPIO55
C/BE0# C/BE1# C/BE2# C/BE3#
IRDY#
PAR
PCIRST#
DEVSEL#
PERR#
PLOCK#
SERR#
STOP#
TRDY#
FRAME#
PLTRST#
PCICLK
PME#
PIRQE#/GPIO2 PIRQF#/GPIO3
PIRQG#/GPIO4
PIRQH#/GPIO5
3
PCI_REQ0#
F1
PCI_GNT0#
G4
PCI_REQ1#
B6 A7
PCI_REQ2#
F13 F12
PCI_REQ3#
E6
PCI_GNT3#
F6
D8 B4 D6 A5
PCI_IRDY#
D3 E3
PCI_RST#
R1
PCI_DEVSEL#
C6
PCI_PERR#
E4
PCI_PLOCK#
C2
PCI_SERR#
J4
PCI_STOP#
A4
PCI_TRDY#
F5
PCI_FRAME#
D7
PLT_RST#
C14
CLK_PCI_ICH
D4
PCI_PME#
R2
3/28 PCI_PME# Remvoe 8.2k pull high +3VALW resistance.
PCI_PIRQE#
H4
PCI_PIRQF#
K6
PCI_PIRQG#
F2
PCI_PIRQH#
G2
PCI_RST# <32>
PCI_SERR# <32>
PLT_RST# <9,25,26,27> CLK_PCI_ICH <17> PCI_PME# <32>
1 2
R291 0_0402_5%
R291 0_0402_5%
GS@
GS@
ACCEL_INT <24>
2
Place closely pin D4
CLK_PCI_ICH
12
@
@
R280
R280 10_0402_5%
10_0402_5%
1
@
@
C425
C425
8.2P_0402_50V
8.2P_0402_50V
2
1
B B
PCI_GNT3#
PCI_GNT3#
A A
Low= A16 swap override Enble High= Default
R294
@R294
@
1 2
5
1K_0402_5%
1K_0402_5%
*
A16 swap override Strap
Boot BIOS Strap
PCI_GNT0# SPI_CS#1
0
1
SPI_CS1#_R<22>
4
1
01
1
SPI_CS1#_R
PCI_GNT0#
Boot BIOS Location
SPI
PCI
LPC
*
@
@
R295
R295
1 2
R296
R296
@
@
1 2
1K_0402_5%
1K_0402_5%
1K_0402_5%
1K_0402_5%
+3VALW
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2007/08/28 2006/03/10
2007/08/28 2006/03/10
2007/08/28 2006/03/10
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
2
Date: Sheet
Compal Electronics, Inc.
ICH9(1/4)-PCI/INT
ICH9(1/4)-PCI/INT
ICH9(1/4)-PCI/INT
Montevina Blade UMA LA4105P
Montevina Blade UMA LA4105P
Montevina Blade UMA LA4105P
20 45Saturday, July 18, 2009
20 45Saturday, July 18, 2009
20 45Saturday, July 18, 2009
1
1.0
1.0
1.0
of
of
of
5
+RTCVCC
HDA_SYNC_CODEC<28> HDA_SYNC_MDC<29>
HDA_SYNC_NB<9> HDA_RST#_CODEC<28,32> HDA_RST#_MDC<29> HDA_RST#_NB<9>
1 2
1 2
1 2
5
SM_INTRUDER#
LAN100_SLP
ICH_INTVRMEN
ICH_SRTCRST#
C426
C426
0.1U_0402_16V4Z
0.1U_0402_16V4Z
+RTCVCC
12P_0402_50V8J
12P_0402_50V8J
C331
C331
1 2
R312 33_0402_5%
R312 33_0402_5% R313 33_0402_5%
R313 33_0402_5% R207 33_0402_5%
R207 33_0402_5%
HDA_SDIN0<28> HDA_SDIN1<29> HDA_SDIN2<9>
R307
R307
1 2
20K_0402_5%
20K_0402_5%
HDA_SDOUT_MDC<29> HDA_SDOUT_CODEC<28> HDA_SDOUT_NB<9>
12
1
@
@
R303
R303
2
0_0402_5%
0_0402_5%
1U_0603_10V4Z
1U_0603_10V4Z
HDA_BITCLK
R316 33_0402_5%
R316 33_0402_5% R314 33_0402_5%
R314 33_0402_5% R208 33_0402_5%
R208 33_0402_5% R317 33_0402_5%
R317 33_0402_5% R318 33_0402_5%
R318 33_0402_5% R209 33_0402_5%
R209 33_0402_5%
SATA_LED#<33>
SATA_RXN0_C<24>
SATA_RXP0_C<24> SATA_TXN0<24> SATA_TXP0<24>
SATA_RXP1_C<24> SATA_TXN1<24> SATA_TXP1<24>
ICH_RSVD <22>
12
@
@
R304
R304
0_0402_5%
0_0402_5%
1
2
1 2 1 2 1 2 1 2 1 2 1 2
R320 33_0402_5%
R320 33_0402_5% R321 33_0402_5%
R321 33_0402_5% R204 33_0402_5%
R204 33_0402_5%
SATA_TXN0 SATA_TXP0
SATA_TXN1 SATA_TXP1
1
C436
C436
2
12
CLRP2
CLRP2 SHORT PADS
SHORT PADS
HDABITCLK
HDABITCLK
C427
C427
1 2 1 2 1 2
15P_0402_50V8J
15P_0402_50V8J
0821 Change C436 and C437 to 15PF
1 2
R297 1M_0402_5%R297 1M_0402_5%
1 2
R299 330K_0402_5%R299 330K_0402_5%
1 2
R300 330K_0402_5%R300 330K_0402_5%
1 2
D D
C C
R302 180K_0402_5%R302 180K_0402_5%
HDA_BITCLK_CODEC<28> HDA_BITCLK_MDC<29> HDA_BITCLK_NB<9>
P- HDD
B B
Add 12p on HDA_SDOUT and HDA_SDOUT
HDA_SDOUT_MDC
HDA_SDOUT_CODEC
HDA_SDOUT_NB
XOR CHAIN ENTRANCE STRAP:RSVD
+3VS
R325
@R325
@
1 2
R326
@R326
@
1 2
A A
ICH_RSVD HDA_SDOUT_CODEC
0
0
1
1K_0402_5%
1K_0402_5%
1K_0402_5%
1K_0402_5%
C311 12P_0402_50V8J@C311 12P_0402_50V8J@
C312 12P_0402_50V8J@C312 12P_0402_50V8J@
C66 12P_0402_50V8J@C66 12P_0402_50V8J@
HDA_SDOUT_CODEC
ICH_RSVD
0
1
0
1 1
4
ICH8M Internal VR Enable Strap (Internal VR for VccSus1.05, VccSus1.5, VccCL1.5)
ICH_INTVRMEN
ICH8M LAN100 SLP Strap (Internal VR for VccLAN1.05 and VccCL1.05)
ICH_LAN100_SLP Low = Internal VR Disabled
+1.5VS
R311
R311
24.9_0402_1%
24.9_0402_1%
1 2
R259
R259
1 2
0_0402_5%
0_0402_5%
1 2 1 2 1 2
T55PAD T55PAD T56PAD T56PAD
0.01U_0402_16V7K
0.01U_0402_16V7K
C431
C431
1 2 1 2
0.01U_0402_16V7K
0.01U_0402_16V7K
0.01U_0402_16V7K
0.01U_0402_16V7K
1 2 1 2
0.01U_0402_16V7K
0.01U_0402_16V7K
R260 10K_0402_5%@R260 10K_0402_5%@
C327 12P_0402_50V8J@C327 12P_0402_50V8J@
1 2
1 2
R264 33_0402_5%@R264 33_0402_5%@
4
Multi@C820
Multi@ Multi@C821
Multi@
12
ICH_RTCX1
ICH_RTCX2
1
C437
C437
15P_0402_50V8J
15P_0402_50V8J
2
C433
C433
C820 C821
R328
R328
1 2
10M_0402_5%
10M_0402_5%
Y2
Y2
1 4
2 3
32.768KHZ_12.5P_MC-146
32.768KHZ_12.5P_MC-146
Low = Internal VR Disabled High = Internal VR Enabled(Default)
High = Internal VR Enabled(Default)
ICH_RTCX1 ICH_RTCX2
ICH_RTCRST# ICH_SRTCRST# SM_INTRUDER#
ICH_INTVRMEN LAN100_SLP
GLAN_COMP
HDA_BITCLK HDA_SYNC
HDARST#
HDA_SDIN0 HDA_SDIN1 HDA_SDIN2
HDA_SDOUT
SATA_LED#
SATA_TXN0_C SATA_TXP0_C
SATA_TXN1_C SATA_TXP1_C
AJ16
AH16
AF17
AG17
AH13
AJ13
AG14
AF14
U8
@U8
@
7
VDD
6
CLKOUT
5
SSON
4
GND
ASM3P623S00BF-08TR_TSSOP8
ASM3P623S00BF-08TR_TSSOP8
HDA_BITCLK
12
@
@
R327
R327 10_0402_5%
10_0402_5%
1
@
@
C439
C439 10P_0402_25V8K
10P_0402_25V8K
2
U12A
U12A
C23
RTCX1
C24
RTCX2
A25
RTCRST#
F20
SRTCRST#
C22
INTRUDER#
B22
INTVRMEN
A22
LAN100_SLP
E25
GLAN_CLK
C13
LAN_RSTSYNC
F14
LAN_RXD0
G13
LAN_RXD1
D14
LAN_RXD2
D13
LAN_TXD_0
D12
LAN_TXD_1
E13
LAN_TXD_2
B10
GPIO56
B28
GLAN_COMPI
B27
GLAN_COMPO
AF6
HDA_BIT_CLK
AH4
HDA_SYNC
AE7
HDA_RST#
AF4
HDA_SDIN0
AG4
HDA_SDIN1
AH3
HDA_SDIN2
AE5
HDA_SDIN3
AG5
HDA_SDOUT
AG7
HDA_DOCK_EN#/GPIO33
AE8
HDA_DOCK_RST#/GPIO34
AG8
SATALED#
SATA0RXN SATA0RXP SATA0TXN SATA0TXP
SATA1RXN SATA1RXP SATA1TXN SATA1TXP
ICH9-M ES_FCBGA676
ICH9-M ES_FCBGA676
1
CLKIN
2
NC
8
NC
3
SS
3
LPC_AD0
K5
HDA_BITCLK
R263
@R263
@
1 2
10K_0402_5%
10K_0402_5%
0.1U_0402_16V4Z
0.1U_0402_16V4Z
+1.5VS
C328
@C328
@
RTC
RTC
LAN / GLAN
LAN / GLAN
IHDA
IHDA
+1.5VS
LPCCPU
LPCCPU
SATA
SATA
1
2
+1.5VS
12
1 2
FWH0/LAD0 FWH1/LAD1 FWH2/LAD2 FWH3/LAD3
FWH4/LFRAME#
LDRQ1#/GPIO23
CPUPWRGD
THRMTRIP#
SATA4RXN SATA4RXP SATA4TXN SATA4TXP
SATA5RXN SATA5RXP SATA5TXN SATA5TXP
SATA_CLKN SATA_CLKP
SATARBIAS#
SATARBIAS
R261
@R261
@
10K_0402_5%
10K_0402_5%
R262
@R262
@
10K_0402_5%
10K_0402_5%
LDRQ0#
A20GATE
A20M#
DPRSTP#
DPSLP#
FERR#
IGNNE#
INIT# INTR
RCIN#
SMI#
STPCLK#
TP12
LPC_AD1
K4
LPC_AD2
L6
LPC_AD3
K2
LPC_FRAME#
K3
J3 J1
GATEA20
N7
H_A20M#
AJ27
AJ25
H_DPSLP#
AE23
R_H_FERR#
AJ26
H_PWRGOOD
AD22
H_IGNNE#
AF25
H_INIT#
AE22
H_INTR
AG25
KB_RST#
L3
H_NMI
AF23
NMI
H_SMI#
AF24
H_STPCLK#
AH27
THRMTRIP_ICH#
AG26
AG27
AH11 AJ11 AG12 AF12
AH9 AJ9 AE10 AF10
AH18 AJ18 AJ7 AH7
SATA_TXN4_C SATA_TXP4_C
SATA_TXN5_C SATA_TXP5_C
CLK_PCIE_SATA# CLK_PCIE_SATA
PR@ C428
PR@ PR@ C429
PR@
R322
R322
1 2
24.9_0402_1%
24.9_0402_1%
Within 500 mils
03/18 Reserve SSC for EMI
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2007/08/28 2006/03/10
2007/08/28 2006/03/10
2007/08/28 2006/03/10
Deciphered Date
Deciphered Date
Deciphered Date
2
PV
::::
follow check list ver:1.5 change to 8.2K ohm
LPC_AD[0..3] <26,32>
LPC_FRAME# <26,32>
T54 PADT54 PAD
GATEA20 <32> H_A20M# <6>
R309
R309
1 2
0_0402_5%
R310
R310
R319 54.9_0402_1%R319 54.9_0402_1%
0.01U_0402_16V7K
0.01U_0402_16V7K
0.01U_0402_16V7K
0.01U_0402_16V7K
ESATA@
ESATA@ ESATA@
ESATA@
0_0402_5%
1 2
56_0402_5%
56_0402_5%
H_PWRGOOD <7>
H_IGNNE# <6>
H_INIT# <6> H_INTR <6>
KB_RST# <32>
H_NMI <6> H_SMI# <6>
H_STPCLK# <6>
1 2
C428
12
C429
12
0.01U_0402_16V7K
0.01U_0402_16V7K C430
C430
12
C432
C432
12
0.01U_0402_16V7K
0.01U_0402_16V7K
02/13 Reserve cap on HDA_BITCLK for WWAN noise issue
HDA_BITCLK_CODEC
HDA_BITCLK_MDC
HDA_BITCLK_NB
R329
R329
1 2
W=20mils
0_0402_5%
1
C438
C438
2.2U_0603_6.3V4Z
2.2U_0603_6.3V4Z
2
0_0402_5%
Place near ICH9
2
GATEA20
KB_RST#
H_DPRSTP#
H_DPSLP#
H_DPRSTP#H_DPRSTP_R#
H_FERR#
H_DPRSTP# <7,9,43> H_DPSLP# <7>
3/28 add 56ohm
+VCCP
12
R315
R315 56_0402_5%
56_0402_5%
placed within 2" from ICH9M
SATA_RXN4_C <24>
SATA_TXN4 SATA_TXP4
SATA_TXN5 SATA_TXP5
W=20mils
SATA_RXP4_C <24>
SATA_RXN5_C <30> SATA_RXP5_C <30>
CLK_PCIE_SATA# <17> CLK_PCIE_SATA <17>SATA_RXN1_C<24>
C67 33P_0402_50V8K
C67 33P_0402_50V8K
1 2
C239 33P_0402_50V8K
C239 33P_0402_50V8K
1 2
C242 33P_0402_50V8K
C242 33P_0402_50V8K
1 2
D8
D8
1
DAN202U_SC70
DAN202U_SC70
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
Date: Sheet
+3VS
R298
R298
1 2
8.2K_0402_5%
8.2K_0402_5%
R301
R301
1 2
10K_0402_5%
10K_0402_5%
+VCCP
R305
@R305
@
1 2
56_0402_5%
56_0402_5%
R306
@R306
@
1 2
56_0402_5%
56_0402_5%
+VCCP
R308
R308 56_0402_5%
56_0402_5%
1 2
within 2" from R379
H_THERMTRIP# <6,9>
SATA_TXN4 <24>
SATA_TXP4 <24>
SATA_TXN5 <30>
SATA_TXP5 <30>
+3VL+RTCVCC
2
3
W=20mils
Montevina Blade UMA LA4105P
Montevina Blade UMA LA4105P
Montevina Blade UMA LA4105P
ODD
e-SATA
De-feature disable
BATT1.1
R330
R330
1 2
1K_0402_5%
1K_0402_5%
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
ICH9(2/4)_LAN,HD,IDE,LPC
ICH9(2/4)_LAN,HD,IDE,LPC
ICH9(2/4)_LAN,HD,IDE,LPC
W=20mils
1
H_FERR# <6>
BATT1
BATT1
@
@
CR2032 RTC BATTERY
CR2032 RTC BATTERY
1
JBATT1
JBATT1
1
1
2
2
3
GND
4
GND
ACES_85205-02001
ACES_85205-02001
CONN@
CONN@
21 45Saturday, July 18, 2009
21 45Saturday, July 18, 2009
21 45Saturday, July 18, 2009
of
of
of
1.0
1.0
1.0
5
04/29 MV-1 add R337 clock REQ pull high
+3VS
1 2
R333 10K_0402_5%R333 10K_0402_5%
1 2
R334 8.2K_0402_5%R334 8.2K_0402_5%
1 2
R335 10K_0402_5%R335 10K_0402_5%
1 2
R336 8.2K_0402_5%@ R336 8.2K_0402_5%@
1 2
D D
C C
B B
A A
R337 10K_0402_5%R337 10K_0402_5%
1 2
R338 8.2K_0402_5%@R338 8.2K_0402_5%@
1 2
R341 8.2K_0402_5%R341 8.2K_0402_5%
1 2
R344 8.2K_0402_5%R344 8.2K_0402_5%
1 2
R356 8.2K_0402_5%R356 8.2K_0402_5%
1 2
R349 8.2K_0402_5%R349 8.2K_0402_5%
1 2
R350 8.2K_0402_5%R350 8.2K_0402_5%
1 2
R351 8.2K_0402_5%R351 8.2K_0402_5%
1 2
R352 8.2K_0402_5%R352 8.2K_0402_5%
1 2
R357 8.2K_0402_5%R357 8.2K_0402_5%
1 2
R358 8.2K_0402_5%R358 8.2K_0402_5%
1 2
R359 10K_0402_5%R359 10K_0402_5%
1 2
R361 8.2K_0402_5%@R361 8.2K_0402_5%@
1 2
R362 8.2K_0402_5%R362 8.2K_0402_5%
1 2
R365 10K_0402_5%@R365 10K_0402_5%@
+3VALW
1 2
R369 10K_0402_5%R369 10K_0402_5%
1 2
R371 8.2K_0402_5%R371 8.2K_0402_5%
1 2
R372 1K_0402_5%R372 1K_0402_5%
1 2
R374 10K_0402_5%R374 10K_0402_5%
1 2
R375 10K_0402_5%R375 10K_0402_5%
1 2
R376 10K_0402_5%R376 10K_0402_5%
1 2
R377 10K_0402_5%R377 10K_0402_5%
1 2
R378 10K_0402_5%R378 10K_0402_5%
1 2
R379 10K_0402_5%R379 10K_0402_5%
1 2
R373 10K_0402_5%R373 10K_0402_5%
1 2
R380 8.2K_0402_5%R380 8.2K_0402_5%
1 2
R381 8.2K_0402_5%R381 8.2K_0402_5%
+3VS +3VS
R745
@R745
@
10K_0402_5%
10K_0402_5%
1 2
DIS/UMA
R746
R746 10K_0402_5%
10K_0402_5%
1 2
USB_OC#6 USB_OC#1 USB_OC#2 USB_OC#4
USB_OC#7 USB_OC#8 USB_OC#9 USB_OC#0
WXMIT_OFF# USB_OC#5 USB_OC#10 USB_OC#11
SIRQ
PM_CLKRUN#
OCP#
THERM_SCI#
CLKREQ#_C
PM_BMBUSY#
EC_SCI#
CR_CPPE#
CR_WAKE#
GPIO18
HDDHALT_LED#
GPIO20
GPIO21
GPIO36
GPIO37
GPIO39
GPIO48
GPIO57
GPIO49
LINKALERT#
ICH_LOW_BAT#
ICH_PCIE_WAKE#
ICH_RI#
XDP_DBRESET#
S4_STATE#
ME_EC_CLK1
ME_EC_DATA1
GPIO10
EC_LID_OUT#
EC_SMI#
GPIO14
@R747
@
10K_0402_5%
10K_0402_5%
1 2
R748
R748 10K_0402_5%
10K_0402_5%
1 2
RP27
RP27
4 5 3 6 2 7 1 8
10K_1206_8P4R_5%
10K_1206_8P4R_5%
RP28
RP28
4 5 3 6 2 7 1 8
10K_1206_8P4R_5%
10K_1206_8P4R_5%
RP29
RP29
4 5 3 6 2 7 1 8
10K_1206_8P4R_5%
10K_1206_8P4R_5%
5
Board ID
R747
17/14 SPI_CLK_SB
+3VALW
+3VS
01/03 Change HDCP ROM to +3VS
+3VALW
10K_0402_5%
10K_0402_5%
H_STP_PCI#<17> H_STP_CPU#<17>
CR_CPPE#<27>
EC_SCI#<32> EC_SMI#<32>
+3VS
TV Tuner
11/17 Swap PCIE LAN and New card
WLAN
LAN
Card Reader
New Card
11/20 Add HDCP ROM for ICH9M
SPI_SB_CS#
1 2
R399 10K_0402_5%@R399 10K_0402_5%@
1 2
R429 10K_0402_5%@R429 10K_0402_5%@
1 2
R430 10K_0402_5%@R430 10K_0402_5%@
R331 2.2K_0402_5%R331 2.2K_0402_5% R332 2.2K_0402_5%R332 2.2K_0402_5%
ICH_SMBCLK<17,26>
ICH_SMBDATA<17,26>
+3VS
12
12
R340
@R340
@
R339
@R339
@
VGATE<17,43>
R366 Low High -->No
-->default boot
SPI_SI
SPI_SO_R
10K_0402_5%
10K_0402_5%
R345 0_0402_5%R345 0_0402_5%
R353
R353
100K_0402_5%
100K_0402_5%
CR_WAKE#<27>
1 2
R364 8.2K_0402_5%R364 8.2K_0402_5%
EXP_CPPE#<26>
+3VS
SB_SPKR<28>
SPI_CLK_SB<31> SPI_SB_CS#<31>
SPI_CS1#_R<20>
SPI_SI<31>
SPI_SO_R<31>
4
1 2 1 2
T57PAD T57PAD
XDP_DBRESET#<6>
PM_BMBUSY#<9>
EC_LID_OUT#<32>
1 2
ICH_PCIE_WAKE#<25,26> SIRQ<32> THERM_SCI#<32>
1 2
R225 0_0402_5%R225 0_0402_5%
1 2
R226 0_0402_5%@R226 0_0402_5%@
1 2
R366 1K_0402_5% @ R366 1K_0402_5% @
CLKREQ#_C<17>
R739
@R739
@
1 2
MCH_ICH_SYNC#<9>
ICH_RSVD<21>
T59PAD T59PAD
OCP#<6>
GPIO20<19>
1 2
0_0402_5%
0_0402_5%
05/08 MV-1 Delete R739
PCIE_RXN1<26> PCIE_RXP1<26> PCIE_TXN1<26> PCIE_TXP1<26>
PCIE_RXN3<26> PCIE_RXP3<26> PCIE_TXN3<26> PCIE_TXP3<26>
GLAN_RXN<25> GLAN_RXP<25> GLAN_TXN<25> GLAN_TXP<25>
PCIE_RXN5<27> PCIE_RXP5<27> PCIE_TXN5<27> PCIE_TXP5<27>
PCIE_RXN4<26> PCIE_RXP4<26> PCIE_TXN4<26> PCIE_TXP4<26>
BT_OFF<30>
WXMIT_OFF#<26>
C445 0.1U_0402_16V4Z
C445 0.1U_0402_16V4Z C444 0.1U_0402_16V4Z
C444 0.1U_0402_16V4Z
2MiniC@
2MiniC@ 2MiniC@
2MiniC@
C448 0.1U_0402_16V4Z
C448 0.1U_0402_16V4Z C449 0.1U_0402_16V4Z
C449 0.1U_0402_16V4Z
C452 0.1U_0402_16V4Z C452 0.1U_0402_16V4Z C453 0.1U_0402_16V4Z C453 0.1U_0402_16V4Z
C816 0.1U_0402_16V4Z
C816 0.1U_0402_16V4Z C817 0.1U_0402_16V4Z
C817 0.1U_0402_16V4Z
C450 0.1U_0402_16V4Z
C450 0.1U_0402_16V4Z C451 0.1U_0402_16V4Z
C451 0.1U_0402_16V4Z
NewC@
NewC@ NewC@
NewC@
SPI_SB_CS#
SPI_SI SPI_SO_R
R383 0_0402_5%R383 0_0402_5%
4
1 2 1 2
1 2 1 2
1 2 1 2
1 2 1 2
1 2 1 2
R417 15_0402_5%@R417 15_0402_5%@
R416 15_0402_5%@R416 15_0402_5%@
1 2
ICH_SMBCLK ICH_SMBDATA LINKALERT# ME_EC_CLK1 ME_EC_DATA1
ICH_RI#
SUS_STAT# XDP_DBRESET#
PM_BMBUSY#
EC_LID_OUT#
H_STP_PCI# R_STP_CPU#
PM_CLKRUN#
ICH_PCIE_WAKE# SIRQ THERM_SCI#
VGATE
OCP# CR_CPPE# EC_SCI#_SB EC_SMI# EC_SCI#_GPIO12
T46PAD T46PAD
17/14 GPIO18 GPIO20 CR_WAKE# DIS/UMA
T47PAD T47PAD
CLKREQ#_C GPIO38 GPIO39 GPIO48 GPIO49 GPIO57
SB_SPKR MCH_ICH_SYNC# ICH_RSVD
1 2
1 2
12
Within 500 mils
R384
R384
22.6_0402_1%
22.6_0402_1%
3
U12C
U12C
G16
SMBCLK
A13
SMBDATA
E17
LINKALERT#/GPIO60/CLGPIO4
C17
SMLINK0
B18
SMLINK1
F19
RI#
R4
SUS_STAT#/LPCPD#
G19
SYS_RESET#
M6
PMSYNC#/GPIO0
A17
SMBALERT#/GPIO11
A14
STP_PCI#
E19
STP_CPU#
L4
CLKRUN#
E20
WAKE#
M5
SERIRQ
AJ23
THRM#
D21
VRMPWRGD
A20
TP11
AG19
GPIO1
AH21
GPIO6
AG21
GPIO7
A21
GPIO8
C12
GPIO12
C21
GPIO13
AE18
GPIO17
K1
GPIO18
AF8
GPIO20
AJ22
SCLOCK/GPIO22
A9
GPIO27
D19
GPIO28
L1
SATACLKREQ#/GPIO35
AE19
SLOAD/GPIO38
AG22
SDATAOUT0/GPIO39
AF21
SDATAOUT1/GPIO48
AH24
GPIO49
A8
GPIO57/CLGPIO5
M7
SPKR
AJ24
MCH_SYNC#
B21
TP3
AH20
TP8
AJ20
TP9
AJ21
TP10
ICH9-M ES_FCBGA676
ICH9-M ES_FCBGA676
PCIE_RXN1 PCIE_RXP1 PCIE_C_TXN1 PCIE_C_TXP1
PCIE_RXN3 PCIE_RXP3 PCIE_C_TXN3 PCIE_C_TXP3
GLAN_RXN GLAN_RXP GLAN_TXN_C GLAN_TXP_C
PCIE_RXN5 PCIE_RXP5 PCIE_C_TXN5 PCIE_C_TXP5
PCIE_RXN4 PCIE_RXP4 PCIE_C_TXN4 PCIE_C_TXP4
SPI_CS1#_R
USB_OC#0 USB_OC#1 USB_OC#2 WXMIT_OFF# USB_OC#4 USB_OC#5 USB_OC#6 USB_OC#7 USB_OC#8 USB_OC#9 USB_OC#10 USB_OC#11
USBRBIAS
SMB
SMB
U12D
U12D
N29
PERN1
N28
PERP1
P27
PETN1
P26
PETP1
L29
PERN2
L28
PERP2
M27
PETN2
M26
PETP2
J29
PERN3
J28
PERP3
K27
PETN3
K26
PETP3
G29
PERN4
G28
PERP4
H27
PETN4
H26
PETP4
E29
PERN5
E28
PERP5
F27
PETN5
F26
PETP5
C29
PERN6/GLAN_RXN
C28
PERP6/GLAN_RXP
D27
PETN6/GLAN_TXN
D26
PETP6/GLAN_TXP
D23
SPI_CLK
D24
SPI_CS0#
F23
SPI_CS1#GPIO58/CLGPIO6
D25
SPI_MOSI
E23
SPI_MISO
N4
OC0#/GPIO59
N5
OC1#/GPIO40
N6
OC2#/GPIO41
P6
OC3#/GPIO42
M1
OC4#/GPIO43
N2
OC5#/GPIO29
M4
OC6#/GPIO30
M3
OC7#/GPIO31
N3
OC8#/GPIO44
N1
OC9#/GPIO45
P5
OC10#/GPIO46
P3
OC11#/GPIO47
AG2
USBRBIAS
AG1
USBRBIAS#
ICH9-M ES_FCBGA676
ICH9-M ES_FCBGA676
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
SATA0GP/GPIO21 SATA1GP/GPIO19 SATA4GP/GPIO36 SATA5GP/GPIO37
SATA
GPIO
SATA
GPIO
clocks
clocks
SYS / GPIOGPIOMISC
SYS / GPIOGPIOMISC
Power MGT
Power MGT
GPIO10/SUS_PWR_ACK
GPIO14/AC_PRESENT
Controller Link
Controller Link
PCI - Express
PCI - Express
SPI
SPI
USB
USB
CLK14 CLK48
SUSCLK
SLP_S3# SLP_S4# SLP_S5#
S4_STATE#/GPIO26
PWROK
DPRSLPVR/GPIO16
BATLOW#
PWRBTN#
LAN_RST#
RSMRST#
CK_PWRGD
CLPWROK
SLP_M#
CL_CLK0 CL_CLK1
CL_DATA0 CL_DATA1
CL_VREF0 CL_VREF1
CL_RST0# CL_RST1#
MEM_LED/GPIO24
WOL_EN/GPIO9
DMI0RXN DMI0RXP
DMI0TXN DMI0TXP
DMI1RXN DMI1RXP
DMI1TXN DMI1TXP
DMI2RXN DMI2RXP
DMI2TXN DMI2TXP
DMI3RXN DMI3RXP
DMI3TXN DMI3TXP
DMI_CLKN DMI_CLKP
DMI_ZCOMP
Direct Media Interface
Direct Media Interface
DMI_IRCOMP
USBP0N USBP0P USBP1N USBP1P USBP2N USBP2P USBP3N USBP3P USBP4N USBP4P USBP5N USBP5P USBP6N USBP6P USBP7N USBP7P USBP8N USBP8P USBP9N
USBP9P USBP10N USBP10P USBP11N USBP11P
2007/08/28 2006/03/10
2007/08/28 2006/03/10
2007/08/28 2006/03/10
GPIO21
AH23
HDDHALT_LED#
AF19
GPIO36
AE21
GPIO37
AD20
CLK_14M_ICH
H1
CLK_48M_ICH
AF3
ICH_SUSCLK
P1
SLP_S3#
C16
SLP_S4#
E16
SLP_S5#
G17
S4_STATE#
C10
PM_PWROK
G20
R348 0_0402_5%R348 0_0402_5%
M2
ICH_LOW_BAT#
B13
PWRBTN_OUT#
R3
D20
R_EC_RSMRST#
D22
CK_PWRGD
R5
M_PWROK
R6
B16
CL_CLK0
F24 B19
CL_DATA0
F22 C19
CL_VREF0_ICH
C25
CL_VREF1_ICH
A19
CL_RST#
F21 D18
XMIT_OFF
A16
GPIO10
C18
GPIO14
C11
LAN_WOL_EN
C20
DMI_RXN0
V27
DMI_RXP0
V26
DMI_TXN0
U29
DMI_TXP0
U28
DMI_RXN1
Y27
DMI_RXP1
Y26
DMI_TXN1
W29
DMI_TXP1
W28
DMI_RXN2
AB27
DMI_RXP2
AB26
DMI_TXN2
AA29
DMI_TXP2
AA28
DMI_RXN3
AD27
DMI_RXP3
AD26
DMI_TXN3
AC29
DMI_TXP3
AC28
CLK_PCIE_ICH#
T26
CLK_PCIE_ICH
T25
AF29
DMI_IRCOMP
AF28
USB20_N0
AC5
USB20_P0
AC4
USB20_N1
AD3
USB20_P1
AD2
USB20_N2
AC1
USB20_P2
AC2
USB20_N3
AA5
USB20_P3
AA4
USB20_N4
AB2
USB20_P4
AB3
USB20_N5
AA1
USB20_P5
AA2
USB20_N6
W5
USB20_P6
W4
USB20_N7
Y3
USB20_P7
Y2
USB20_N8
W1
USB20_P8
W2
USB20_N9
V2
USB20_P9
V3 U5 U4 U1 U2
1 2
Deciphered Date
Deciphered Date
Deciphered Date
11/09 Change Gsensor control from SB
T58 PADT58 PAD
CL_CLK0 <9>
CL_DATA0 <9>
CL_RST# <9>
R370
R370
12
100K_0402_5%
100K_0402_5%
DMI_RXN0 <9> DMI_RXP0 <9> DMI_TXN0 <9> DMI_TXP0 <9>
DMI_RXN1 <9> DMI_RXP1 <9> DMI_TXN1 <9> DMI_TXP1 <9>
DMI_RXN2 <9> DMI_RXP2 <9> DMI_TXN2 <9> DMI_TXP2 <9>
DMI_RXN3 <9> DMI_RXP3 <9> DMI_TXN3 <9> DMI_TXP3 <9>
CLK_PCIE_ICH# <17> CLK_PCIE_ICH <17>
R382 24.9_0402_1%R382 24.9_0402_1%
1 2
USB20_N0 <30> USB20_P0 <30> USB20_N1 <30> USB20_P1 <30> USB20_N2 <30> USB20_P2 <30> USB20_N3 <34> USB20_P3 <34> USB20_N4 <19> USB20_P4 <19> USB20_N5 <26> USB20_P5 <26> USB20_N6 <30> USB20_P6 <30> USB20_N7 <30> USB20_P7 <30> USB20_N8 <26> USB20_P8 <26> USB20_N9 <26> USB20_P9 <26>
2
HDDHALT_LED# <33>
CLK_14M_ICH <17> CLK_48M_ICH <17>
SLP_S3# <32> SLP_S4# <32,36> SLP_S5# <32>
PM_PWROK <9,32>
PWRBTN_OUT# <32>
CK_PWRGD <17>
M_PWROK <9,32>
XMIT_OFF <26>
DPRSLPVR <9,43>
R_EC_RSMRST# <39>
R354 100_0402_5% R354 100_0402_5%
1 2
R355 10K_0402_5%R355 10K_0402_5%
1 2
+3VALW
USB-0 Right side
USB-1 Right side
USB-2 Left side(with ESATA)
USB-3 Dock
USB-4 Camera
USB-5 WLAN
USB-6 Bluetooth
USB-7 Finger Printer
USB-8 MiniCard(WWAN/TV)
USB-9 Express card
2
R346 10K_0402_5%R346 10K_0402_5%
1 2
C442
C442
C443
C443
Within 500 mils
+1.5VS
1
+3VS
+3VALW
Place closely pin H1
CLK_14M_ICH
12
R343
@R343
@
10_0402_5%
10_0402_5%
1
C441
@C441
@
4.7P_0402_50V8C
4.7P_0402_50V8C
2
Place closely pin AF3
CLK_48M_ICH
12
R342
@ R342
@
10_0402_5%
10_0402_5%
1
C440
@ C440
@
4.7P_0402_50V8C
4.7P_0402_50V8C
2
11/17 Add +3VALW GD to EC_RSMRST# to fix Battery mode can't boot issue
EC_RSMRST# <32>
R360
R360
1 2
12
3.24K_0402_1%
R363
R363 453_0402_1%
453_0402_1%
NA lead free
12
R368
R368 453_0402_1%
453_0402_1%
D22
D22
2 1
3.24K_0402_1%
R367
R367
1 2
3.24K_0402_1%
3.24K_0402_1%
1
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
PM_PWROK R_EC_RSMRST#
CH751H-40PT_SOD323-2
CH751H-40PT_SOD323-2
#PV PWROK sequence issue
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
Date: Sheet
Compal Electronics, Inc.
ICH9(3/4)_DMI,USB,GPIO,PCIE
ICH9(3/4)_DMI,USB,GPIO,PCIE
ICH9(3/4)_DMI,USB,GPIO,PCIE
Montevina Blade UMA LA4105P
Montevina Blade UMA LA4105P
Montevina Blade UMA LA4105P
22 45Saturday, July 18, 2009
22 45Saturday, July 18, 2009
22 45Saturday, July 18, 2009
of
of
1
of
1.0
1.0
1.0
5
+RTCVCC
20 mils
1
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
40 mils
1
+
+
C459
C459
2
10U_0805_10V4Z
10U_0805_10V4Z
220U_D2_4VM
220U_D2_4VM
1
C477
C477
2
1U_0603_10V4Z
1U_0603_10V4Z
1
C483
C483
2
1
C487
C487
2
10U_0805_10V4Z
10U_0805_10V4Z
1
C454
C454
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
2
10U_0805_10V4Z
10U_0805_10V4Z
+1.5VS
1
C488
C488
2
2.2U_0603_6.3V4Z
2.2U_0603_6.3V4Z
C462
C462
R387
R387
1 2
+5VS +3VS
12
R386
R386
100_0402_5%
100_0402_5%
12
R388
R388
10_0402_5%
10_0402_5%
+1.5VS
0316 change design
+1.5VS
+3VALW+5VALW
R389
R389
1 2
CHB1608U301_0603
CHB1608U301_0603
+3VS
C485
C485
0.1U_0402_16V4Z
0.1U_0402_16V4Z
CHB1608U301_0603
CHB1608U301_0603
21
D9
D9
CH751H-40_SC76
CH751H-40_SC76
ICH_V5REF_RUN
20 mils
1
C465
C465
0.1U_0402_10V6K
0.1U_0402_10V6K
2
21
D10
D10
CH751H-40_SC76
CH751H-40_SC76
ICH_V5REF_SUS
20 mils
1
C472
C472
0.1U_0402_10V6K
0.1U_0402_10V6K
2
+1.5VS
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
R390 CHB1608U301_0603R390 CHB1608U301_0603
1 2
+1.5VS
2
5
C458
C458
1
C476
C476
2
D D
C C
B B
A A
ICH_V5REF_RUN
ICH_V5REF_SUS
10U_0805_10V4Z
10U_0805_10V4Z
1
C456
C456
C460
C460
2
2.2U_0603_6.3V4Z
2.2U_0603_6.3V4Z
+1.5VS
C478
C478
1U_0603_10V4Z
1U_0603_10V4Z
+1.5VS
C481
C481
1U_0603_10V4Z
1U_0603_10V4Z
C484
C484
0.1U_0402_16V4Z
0.1U_0402_16V4Z
VCC_LAN1_05_INT_ICH_1
T69T69
VCC_LAN1_05_INT_ICH_2
T70T70
R391
R391
1 2
+1.5VS
CHB1608U301_0603
CHB1608U301_0603
0316 change design
1
2
1
2
1
2
1
2
C489
C489
4.7U_0805_10V4Z
4.7U_0805_10V4Z
1
+3VS
2
4
U12F
U12F
A23
VCCRTC
A6
V5REF
AE1
V5REF_SUS
AA24
VCC1_5_B[01]
AA25
VCC1_5_B[02]
AB24
VCC1_5_B[03]
AB25
VCC1_5_B[04]
AC24
VCC1_5_B[05]
AC25
VCC1_5_B[06]
AD24
VCC1_5_B[07]
AD25
VCC1_5_B[08]
AE25
VCC1_5_B[09]
AE26
VCC1_5_B[10]
AE27
VCC1_5_B[11]
AE28
VCC1_5_B[12]
AE29
VCC1_5_B[13]
F25
VCC1_5_B[14]
G25
VCC1_5_B[15]
H24
VCC1_5_B[16]
H25
VCC1_5_B[17]
J24
VCC1_5_B[18]
J25
VCC1_5_B[19]
K24
VCC1_5_B[20]
K25
VCC1_5_B[21]
L23
VCC1_5_B[22]
L24
VCC1_5_B[23]
L25
VCC1_5_B[24]
M24
VCC1_5_B[25]
M25
VCC1_5_B[26]
N23
VCC1_5_B[27]
N24
VCC1_5_B[28]
N25
VCC1_5_B[29]
P24
VCC1_5_B[30]
P25
VCC1_5_B[31]
R24
VCC1_5_B[32]
R25
VCC1_5_B[33]
R26
VCC1_5_B[34]
R27
VCC1_5_B[35]
T24
VCC1_5_B[36]
T27
VCC1_5_B[37]
T28
VCC1_5_B[38]
T29
VCC1_5_B[39]
U24
VCC1_5_B[40]
U25
VCC1_5_B[41]
V24
VCC1_5_B[42]
V25
VCC1_5_B[43]
U23
VCC1_5_B[44]
W24
VCC1_5_B[45]
W25
VCC1_5_B[46]
K23
VCC1_5_B[47]
Y24
VCC1_5_B[48]
Y25
VCC1_5_B[49]
AJ19
VCCSATAPLL
AC16
VCC1_5_A[01]
AD15
VCC1_5_A[02]
AD16
VCC1_5_A[03]
AE15
VCC1_5_A[04]
AF15
VCC1_5_A[05]
AG15
VCC1_5_A[06]
AH15
VCC1_5_A[07]
AJ15
VCC1_5_A[08]
AC11
VCC1_5_A[09]
AD11
VCC1_5_A[10]
AE11
VCC1_5_A[11]
AF11
VCC1_5_A[12]
AG10
VCC1_5_A[13]
AG11
VCC1_5_A[14]
AH10
VCC1_5_A[15]
AJ10
VCC1_5_A[16]
AC9
VCC1_5_A[17]
AC18
VCC1_5_A[18]
AC19
VCC1_5_A[19]
AC21
VCC1_5_A[20]
G10
VCC1_5_A[21]
G9
VCC1_5_A[22]
11mA
AC12
VCC1_5_A[23]
AC13
VCC1_5_A[24]
AC14
VCC1_5_A[25]
AJ5
VCCUSBPLL
AA7
VCC1_5_A[26]
AB6
VCC1_5_A[27]
AB7
VCC1_5_A[28]
AC6
VCC1_5_A[29]
AC7
VCC1_5_A[30]
A10
VCCLAN1_05[1]
A11
VCCLAN1_05[2]
A12
VCCLAN3_3[1]
B12
VCCLAN3_3[2]
23mA
A27
VCCGLANPLL
80mA
D28
VCCGLAN1_5[1]
D29
VCCGLAN1_5[2]
E26
VCCGLAN1_5[3]
E27
VCCGLAN1_5[4]
1mA
A26
VCCGLAN3_3
ICH9-M ES_FCBGA676
ICH9-M ES_FCBGA676
4
11mA
G3: 6uA
2mA
2mA
646mA
47mA
1342mA
VCCA3GP
VCCA3GP
ARX
212mA
ATX
ATXARX
USB CORE
USB CORE
1634mA
11mA
GLAN POWER
GLAN POWER
VCC1_05[01] VCC1_05[02] VCC1_05[03] VCC1_05[04] VCC1_05[05] VCC1_05[06] VCC1_05[07] VCC1_05[08] VCC1_05[09] VCC1_05[10] VCC1_05[11] VCC1_05[12] VCC1_05[13] VCC1_05[14] VCC1_05[15] VCC1_05[16]
CORE
CORE
VCC1_05[17] VCC1_05[18] VCC1_05[19] VCC1_05[20] VCC1_05[21] VCC1_05[22] VCC1_05[23] VCC1_05[24] VCC1_05[25] VCC1_05[26]
23mA
V_CPU_IO[1]
48mA
V_CPU_IO[2]
2mA
VCCP_CORE
VCCP_CORE
308mA
PCI
PCI
11mA
VCCSUSHDA
VCCSUS1_05[1] VCCSUS1_05[2]
VCCSUS1_5[1]
VCCSUS1_5[2]
VCCSUS3_3[01] VCCSUS3_3[02] VCCSUS3_3[03] VCCSUS3_3[04]
VCCPSUS
VCCPSUS
VCCSUS3_3[05]
VCCSUS3_3[06] VCCSUS3_3[07] VCCSUS3_3[08] VCCSUS3_3[09] VCCSUS3_3[10] VCCSUS3_3[11] VCCSUS3_3[12] VCCSUS3_3[13] VCCSUS3_3[14] VCCSUS3_3[15] VCCSUS3_3[16]
VCCPUSB
VCCPUSB
VCCSUS3_3[17] VCCSUS3_3[18] VCCSUS3_3[19] VCCSUS3_3[20]
19/73/73mA19/78/78mA
VCCCL3_3[1] VCCCL3_3[2]
VCCDMIPLL
VCC_DMI[1] VCC_DMI[2]
VCC3_3[01] VCC3_3[02] VCC3_3[07]
VCC3_3[03] VCC3_3[04] VCC3_3[05] VCC3_3[06]
VCC3_3[08] VCC3_3[09] VCC3_3[10] VCC3_3[11] VCC3_3[12] VCC3_3[13] VCC3_3[14]
VCCHDA
VCCCL1_05
VCCCL1_5
3
A15 B15 C15 D15 E15 F15 L11 L12 L14 L16 L17 L18 M11 M18 P11 P18 T11 T18 U11 U18 V11 V12 V14 V16 V17 V18
R29
W23 Y23
AB23 AC23
AG29 AJ6 AC10
AD19 AF20 AG24 AC20
B9 F9 G3 G6 J2 J7 K7
AJ4
AJ3
AC8 F17
AD8
F18
A18 D16 D17 E22
AF1
T1 T2 T3 T4 T5 T6 U6 U7 V6 V7 W6 W7 Y6 Y7 T7
G22 G23
A24 B24
+VCCP
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
VCCSUS1_5_ICH_1
VCCSUS1_5_ICH_2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
VCCCL1_05_ICH
+3VS
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
1
C457
C457
C455
C455
2
2
R385
1
C464
C464
2
+3VS
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1 2
12
0.1U_0402_16V4Z
0.1U_0402_16V4Z
R385
1 2
CHB1608U301_0603
CHB1608U301_0603
1
C463
C463
10U_0805_10V4Z
10U_0805_10V4Z
2
+VCCP
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
C470
C470
2
R212
@R212
@
0_0402_5%
0_0402_5%
1 2
R741
R741 150_0402_1%
150_0402_1%
1
C471
C471
2
R740
R740 180_0402_1%
180_0402_1%
+1.5VALW
+1.5VS
+3VALW
Deciphered Date
Deciphered Date
Deciphered Date
0.01U_0402_16V7K
0.01U_0402_16V7K
1
C461
C461
2
22U_0805_6.3VAM
22U_0805_6.3VAM
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
C469
C469
2
+3VS
1
2
1
2
1
2
+1.5VS
C473
C473
1
C475
C475
T65T65
2
T66T66
T67T67
T68T68
+3VALW
1
C480
C480
C479
C479
2
+3VALW
1
C482
C482
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
2
T71T71
@
@
C486
C486 1U_0603_10V4Z
1U_0603_10V4Z
2007/08/28 2006/03/10
2007/08/28 2006/03/10
2007/08/28 2006/03/10
+VCCP
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
C466
C466
1
2
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
C467
C467
1
2
(DMI)
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
C468
C468
1
2
1
C474
C474
2
U12E
U12E
AA26
VSS[001]
AA27
VSS[002]
AA3
VSS[003]
AA6
VSS[004]
AB1
VSS[005]
AA23
VSS[006]
AB28
VSS[007]
AB29
VSS[008]
AB4
VSS[009]
AB5
VSS[010]
AC17
VSS[011]
AC26
VSS[012]
AC27
VSS[013]
AC3
VSS[014]
AD1
VSS[015]
AD10
VSS[016]
AD12
VSS[017]
AD13
VSS[018]
AD14
VSS[019]
AD17
VSS[020]
AD18
VSS[021]
AD21
VSS[022]
AD28
VSS[023]
AD29
VSS[024]
AD4
VSS[025]
AD5
VSS[026]
AD6
VSS[027]
AD7
VSS[028]
AD9
VSS[029]
AE12
VSS[030]
AE13
VSS[031]
AE14
VSS[032]
AE16
VSS[033]
AE17
VSS[034]
AE2
VSS[035]
AE20
VSS[036]
AE24
VSS[037]
AE3
VSS[038]
AE4
VSS[039]
AE6
VSS[040]
AE9
VSS[041]
AF13
VSS[042]
AF16
VSS[043]
AF18
VSS[044]
AF22
VSS[045]
AH26
VSS[046]
AF26
VSS[047]
AF27
VSS[048]
AF5
VSS[049]
AF7
VSS[050]
AF9
VSS[051]
AG13
VSS[052]
AG16
VSS[053]
AG18
VSS[054]
AG20
VSS[055]
AG23
VSS[056]
AG3
VSS[057]
+1.5VS
Custom
Custom
Custom
AG6
VSS[058]
AG9
VSS[059]
AH12
VSS[060]
AH14
VSS[061]
AH17
VSS[062]
AH19
VSS[063]
AH2
VSS[064]
AH22
VSS[065]
AH25
VSS[066]
AH28
VSS[067]
AH5
VSS[068]
AH8
VSS[069]
AJ12
VSS[070]
AJ14
VSS[071]
AJ17
VSS[072]
AJ8
VSS[073]
B11
VSS[074]
B14
VSS[075]
B17
VSS[076]
B2
VSS[077]
B20
VSS[078]
B23
VSS[079]
B5
VSS[080]
B8
VSS[081]
C26
VSS[082]
C27
VSS[083]
E11
VSS[084]
E14
VSS[085]
E18
VSS[086]
E2
VSS[087]
E21
VSS[088]
E24
VSS[089]
E5
VSS[090]
E8
VSS[091]
F16
VSS[092]
F28
VSS[093]
F29
VSS[094]
G12
VSS[095]
G14
VSS[096]
G18
VSS[097]
G21
VSS[098]
G24
VSS[099]
G26
VSS[100]
G27
VSS[101]
G8
VSS[102]
H2
VSS[103]
H23
VSS[104]
H28
VSS[105]
H29
VSS[106]
ICH9-M ES_FCBGA676
ICH9-M ES_FCBGA676
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
Compal Electronics, Inc.
ICH9(4/4)_POWER&GND
ICH9(4/4)_POWER&GND
ICH9(4/4)_POWER&GND
Montevina Blade UMA LA4105P
Montevina Blade UMA LA4105P
Montevina Blade UMA LA4105P
1
VSS_NCTF[01] VSS_NCTF[02] VSS_NCTF[03] VSS_NCTF[04] VSS_NCTF[05] VSS_NCTF[06] VSS_NCTF[07] VSS_NCTF[08] VSS_NCTF[09] VSS_NCTF[10] VSS_NCTF[11] VSS_NCTF[12]
1
VSS[107] VSS[108] VSS[109] VSS[110] VSS[111] VSS[112] VSS[113] VSS[114] VSS[115] VSS[116] VSS[117] VSS[118] VSS[119] VSS[120] VSS[121] VSS[122] VSS[123] VSS[124] VSS[125] VSS[126] VSS[127] VSS[128] VSS[129] VSS[130] VSS[131] VSS[132] VSS[133] VSS[134] VSS[135] VSS[136] VSS[137] VSS[138] VSS[139] VSS[140] VSS[141] VSS[142] VSS[143] VSS[144] VSS[145] VSS[146] VSS[147] VSS[148] VSS[149] VSS[150] VSS[151] VSS[152] VSS[153] VSS[154] VSS[155] VSS[156] VSS[157] VSS[158] VSS[159] VSS[160] VSS[161] VSS[162] VSS[163] VSS[164] VSS[165] VSS[166] VSS[167] VSS[168] VSS[169] VSS[170] VSS[171] VSS[172] VSS[173] VSS[174] VSS[175] VSS[176] VSS[177] VSS[178] VSS[179] VSS[180] VSS[181] VSS[182] VSS[183] VSS[184] VSS[185] VSS[186] VSS[187] VSS[188] VSS[189] VSS[190] VSS[191] VSS[192] VSS[193] VSS[194] VSS[195] VSS[196] VSS[197] VSS[198]
H5 J23 J26 J27 AC22 K28 K29 L13 L15 L2 L26 L27 L5 L7 M12 M13 M14 M15 M16 M17 M23 M28 M29 N11 N12 N13 N14 N15 N16 N17 N18 N26 N27 P12 P13 P14 P15 P16 P17 P2 P23 P28 P29 P4 P7 R11 R12 R13 R14 R15 R16 R17 R18 R28 T12 T13 T14 T15 T16 T17 T23 B26 U12 U13 U14 U15 U16 U17 AD23 U26 U27 U3 V1 V13 V15 V23 V28 V29 V4 V5 W26 W27 W3 Y1 Y28 Y29 Y4 Y5 AG28 AH6 AF2 B25
A1 A2 A28 A29 AH1 AH29 AJ1 AJ2 AJ28 AJ29 B1 B29
1.0
1.0
23 45Saturday, July 18, 2009
23 45Saturday, July 18, 2009
23 45Saturday, July 18, 2009
1.0
of
of
of
5
4
3
2
1
1
C713
2
GS@ C713
GS@
CLK_SMBDATA
R570
GS@R570
GS@
0_0402_5%
0_0402_5%
1 2
+3VS_ACL
1
C714
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
10U_0805_6.3V6M
10U_0805_6.3V6M
GS@ C714
GS@
CLK_SMBCLK <15,16,17>
0011101b
CLK_SMBDATA <15,16,17>
ACCEL_INT <20>
Pleace near HDD CONN (JP3)
HDD Connector
JP3
JP3
1
GND
2
A+
3
A-
D D
C C
GND
B-
B+
GND
V33 V33
V33 GND GND GND
V5 V5 V5
GND
Reserved
GND
V12
V12
V12
SUYIN_127072FR022G523_RV
SUYIN_127072FR022G523_RV
CONN@
CONN@
CD-ROM Connector
JP5
JP5
GND
A+
A-
GND
B-
B+
GND
DP V5 V5
MD GND GND
SUYIN_127382FR013GX09ZR
SUYIN_127382FR013GX09ZR
CONN@
CONN@
0.01U_0402_16V7K
0.01U_0402_16V7K
4
SATA_RXN0
5
SATA_RXP0 SATA_RXP0_C
6
0.01U_0402_16V7K
0.01U_0402_16V7K
7
8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
13 12 11 10 9 8 7
6 5 4 3 2 1
+3VS_HDD1
+5VS
0.01U_0402_16V7K
0.01U_0402_16V7K
SATA_RXN4 SATA_RXP4
0.01U_0402_16V7K
0.01U_0402_16V7K
+5VS
SATA_TXP0 SATA_TXN0
SATA_RXN0_C
C494
C494
12
C495
C495
12
Near CONN side.
SATA_TXP4 SATA_TXN4
SATA_RXN4_C
C510
C510
12
SATA_RXP4_C
C511
C511
12
Near CONN side.
PR@
PR@ PR@
PR@
SATA_TXP0 <21>
SATA_TXN0 <21>
SATA_RXN0_C <21>
SATA_RXP0_C <21>
SATA_TXP4 <21>
SATA_TXN4 <21>
SATA_RXN4_C <21> SATA_RXP4_C <21>
+5VS
1
C490
C490
2
Pleace near HDD CONN
R392
@R392
@
1 2
+3VS
0_0805_5%
0_0805_5%
+5VS
1
C512
C512
PR@
PR@
2
1
1
C492
C492
C491
C491
2
2
10U_0805_10V4Z
10U_0805_10V4Z
1
C496
@C496
@
2
Placea caps. near ODD CONN.
1
C513
C513
PR@
PR@
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
@C497
@
1000P_0402_50V7K
1000P_0402_50V7K
1U_0603_10V4Z
1U_0603_10V4Z
C497
C514
C514
PR@
PR@
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
@C498
@
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
2
10U_0805_10V4Z
10U_0805_10V4Z
C493
C493
+3VS_HDD1
C498
C515
C515
PR@
PR@
ACCELEROMETER (ST)
1
D23
GS@ D23
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
2
1U_0603_10V4Z
1U_0603_10V4Z
1
2
10U_0805_10V4Z
10U_0805_10V4Z
VDDIO absolute man rating is VDD+0.1
+3VS_ACL_IO
GS@
2 1
CH751H-40PT_SOD323-2
CH751H-40PT_SOD323-2
GS@ R568
GS@
+3VS_ACL
+3VS_ACL+3VS +3VS_ACL_IO
1 2
GS@
GS@
U29
U29
1
R568
0_0402_5%
0_0402_5%
1 2
Vdd_IO
2
GND
3
Reserved
4
GND
5
GND
6
Vdd
R569 10K_0402_5%GS@ R569 10K_0402_5%GS@
Must be placed in the center of the system.
02/12 Change SM bus to VS
04/23 Change part number from SA00001U600 to SA00002B600
R564
GS@ R564
GS@
0_0603_5%
0_0603_5%
12
CLK_SMBCLK
14
SCL / SPC
SDA / SDI / SDO
Reserved
CS
7
13
12
SDO
11
10
GND
9
INT 2
8
INT 1
LIS302DLTR_LGA14_3x5
LIS302DLTR_LGA14_3x5
ACCELEROMETER (Bosch)
B B
U14
@
U14
@
BMA150
Multi Bay
+5VS
+5VS
A A
2
VCC5
4
VCC5
6
VCC5
8
VCC3
10
VCC3
12
VCC3
14
GND
16
GND
18
GND
TYCO_2023087-3
TYCO_2023087-3
CONN@
CONN@
GND
TX+
GND
RX+ GND GND
GND
JP12
JP12
TX-
RX-
1
SATA_TXP1
3
SATA_TXN1
5 7
SATA_RXN1 SATA_RXN1_C
C822
9 11 13 15
17
5
C822
SATA_RXP1 SATA_RXP1_C
C823
C823
0.01U_0402_16V7K
0.01U_0402_16V7K
0.01U_0402_16V7K
0.01U_0402_16V7K
SATA_TXP1 <21> SATA_TXN1 <21>
12 12
Multi@
Multi@ Multi@
Multi@
SATA_RXN1_C <21> SATA_RXP1_C <21>
4
Placea caps. near Multi Bay CONN.
C297
C297
Multi@
Multi@
1
2
1
C298
C298
Multi@
Multi@
2
1U_0603_10V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1U_0603_10V4Z
04/29 MV1 add C330 , avoid multibay hot plug shut down
C299
C299
Multi@
Multi@
ZZZ2
ZZZ2
PCB-MB
PCB-MB
1
C330
C330
Multi@
Multi@
2
10U_0805_10V4Z
10U_0805_10V4Z
Issued Date
Issued Date
Issued Date
1
+
+
2
150U_B_6.3VM_R40M
150U_B_6.3VM_R40M
2007/08/28 2006/03/10
2007/08/28 2006/03/10
2007/08/28 2006/03/10
3
1
C300
C300
Multi@
Multi@
2
10U_0805_10V4Z
10U_0805_10V4Z
Security Classification
Security Classification
Security Classification
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
+3VS_ACL
02/12 Correct SM bus
Deciphered Date
Deciphered Date
Deciphered Date
R571 10K_0402_5%@ R571 10K_0402_5%@
1 2
CLK_SMBCLK
CLK_SMBDATA
ACCEL_INT
G_CS#
2
BMA150
4
INT
5
CSB
6
SCK
7
SDO
8
SDI
BMA150_LGA12
BMA150_LGA12
9
VDDIO
VDD
GND
RSVD RSVD
RSVD RSVD
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
Date: Sheet
+3VS_ACL_IO
2
+3VS_ACL
3
1 10
11 12
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
HDD & CDROM
HDD & CDROM
HDD & CDROM
Montevina Blade UMA LA4105P
Montevina Blade UMA LA4105P
Montevina Blade UMA LA4105P
24 45Saturday, July 18, 2009
24 45Saturday, July 18, 2009
24 45Saturday, July 18, 2009
1
1.0
1.0
1.0
of
of
of
5
4
3
2
1
LAN Conn.
JRJ45
R697
Place Close to Chip
C240 0.1U_0402_16V7K C240 0.1U_0402_16V7K
12
C241 0.1U_0402_16V7K C241 0.1U_0402_16V7K
12
GLAN_TXP<22>
GLAN_TXN<22>
CLK_PCIE_LAN<17>
CLK_PCIE_LAN#<17>
CLKREQ#_9<17>
PLT_RST#<9,20,26,27>
R688 2.49K_0402_1%R688 2.49K_0402_1%
ICH_PCIE_WAKE#<22,26>
+LAN_VDD12
2
2
C251
C251
C252
C252
1
1
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
+3VS
12
R215
R215 1K_0402_1%
1K_0402_1%
R216
R216 15K_0402_5%
15K_0402_5%
GLAN_RXP<22>
GLAN_RXN<22>
ISOLATEB
LAN_POWER_OFF<32>
D D
C C
B B
Close to Pin10,13,30,36
2
C249
C249
C250
C250
1
0.1U_0402_16V4Z
0.1U_0402_16V4Z
PCIE_PTX_IRX_P2
PCIE_PTX_IRX_N2
1 2
ISOLATEB
LAN_X1 LAN_X2
1 2
R218 10K_0402_5%
R218 10K_0402_5%
2
1
0.1U_0402_16V4Z
0.1U_0402_16V4Z
U44
U44
20
HSOP
21
HSON
15
HSIP
16
HSIN
17
REFCLK_P
18
REFCLK_M
25
CLKREQB
27
PERSTB
46
RSET
26
LANWAKEB
28
ISOLATEB
41
CKXTAL1
42
CKXTAL2
23
NC
24
NC
7
GND
14
GND
31
GND
47
GND
22
GNDTX
RTL8103EL-GR_LQFP48_7X7
RTL8103EL-GR_LQFP48_7X7
PJP4
PJP4
C255
C255
1 2
PAD-OPEN 4x4m
PAD-OPEN 4x4m
S
S
2
G
G
@
@
2
1
+3VALW
0.1U_0402_16V4Z
0.1U_0402_16V4Z
Close to Pin1,37,29
2
C253
C253
1
RTL8103EL
RTL8103EL
D
D
Q19
Q19 SI2301BDS-T1-E3_SOT23-3
SI2301BDS-T1-E3_SOT23-3
C254
C254
0.1U_0402_16V4Z
0.1U_0402_16V4Z
40 mils
13
+3V_LAN
2
C261
C261
1
0.1U_0402_16V4Z
0.1U_0402_16V4Z
LED3/EEDO
LED2/EEDI/AUX
LED1/EESK
EECS
LED0
MDIP0 MDIN0 MDIP1 MDIN1
VCTRL12A
VDDTX DVDD12 DVDD12 DVDD12 DVDD12
VCTRL12D
VDD33
VDD33
AVDD33
+3V_LAN
2
1
0.1U_0402_16V4Z
0.1U_0402_16V4Z
NC NC NC NC
NC
NC
NC
NC NC
LAN_DO
33
LAN_DI
34
LAN_SK_LAN_LINK#
35
LAN_CS
32
LAN_ACTIVITY#
38
LAN_MDI0+
2
LAN_MDI0-
3
LAN_MDI1+
5
LAN_MDI1-
6 8 9 11 12
4
VCTRL12
48
19 30 36 13 10
39
44 45
29 37
1 40 43
+EVDD12 +LAN_VDD12
+LAN_VDD12
+3V_LAN
10/29 update
C247 0.01U_0402_16V7K
C247 0.01U_0402_16V7K
1 2
C248 0.01U_0402_16V7K
C248 0.01U_0402_16V7K
1 2
LAN_ACTIVITY#
LAN_SK_LAN_LINK#
2
3
D20
D20
PACDN042_SOT23~D
PACDN042_SOT23~D
@
@
1
02/12 Reserve to prevent ESD issue as other project.
LAN_MDI0+ LAN_MDI0­LAN_CT0
LAN_CT1 LAN_MDI1+ LAN_MDI1-
LANLED_ACT#
LANLED_LINK#
LAN_DO LAN_DI LAN_SK_LAN_LINK# LAN_CS
R697 300_0402_5%
300_0402_5%
1
C268
C268
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
02/25 EMI request
2
C269
C269
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
R698
R698 300_0402_5%
300_0402_5%
U46
U46
1
RD+
2
RD-
3
CT
4
NC
5
NC
6
CT
7
TD+ TD-8TX-
LEF8423A-R
LEF8423A-R
16
RX+
15
RX-
14
CT
13
NC
12
NC
11
CT
10
TX+
9
1 2
R695 3.6K_0402_5%R695 3.6K_0402_5%
U45
4
DO
3
DI
2
SK
1
CS
AT93C46-10SI-2.7_SO8
AT93C46-10SI-2.7_SO8
R696 10K_0402_5%R696 10K_0402_5%
12
12
RJ45_MIDI0+ RJ45_MIDI0­RJ45_CT0
RJ45_CT1 RJ45_MIDI1+ RJ45_MIDI1-
@U45
@
12
+3V_LAN
LANLED_ACT#
RJ45_MIDI1-
RJ45_MIDI1+
RJ45_MIDI0-
RJ45_MIDI0+
+3V_LAN
LANLED_LINK#
C257 0.01U_0603_100V7-M
C257 0.01U_0603_100V7-M C258 0.01U_0603_100V7-M
C258 0.01U_0603_100V7-M
+3V_LAN
5
GND
6
NC
7
NC
8
VCC
JRJ45
13
14
8
7
6
5
4
3
2
1
11
12
FOX_JM36113-P1122-7F
FOX_JM36113-P1122-7F
CONN@
CONN@
1
C271
C271
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
1 2 1 2
2
C256
C256
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
C Delete
Yellow LED+
Yellow LED-
PR4-
DETECT PIN1
PR4+
PR2-
PR3-
PR3+
PR2+
PR1-
DETCET PIN2
PR1+
Green LED+
Green LED-
1
2
RJ45_MIDI0+ <34> RJ45_MIDI0- <34>
RJ45_MIDI1+ <34> RJ45_MIDI1- <34>
+3V_LAN
16
SHLD1
9
10
15
SHLD1
C272
C272
4.7U_0805_10V4Z
4.7U_0805_10V4Z
RJ45_CT0_C RJ45_CT1_C
LANGND
R693
R693 75_0402_1%
75_0402_1%
1 2 1 2
R694
R694
75_0402_1%
75_0402_1%
RJ45_GND
C259
C259
1000P_1206_2KV7K
1000P_1206_2KV7K
1
2
Y3
Y3
Close to Pin19 Close to Pin45
A A
C266
C266
+EVDD12
2
2
C267
C267
1
1
1U_0402_6.3V4Z
1U_0402_6.3V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
5
C264
C264
2
1
+LAN_VDD12
@
@
C265
C265
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
2
10U_0805_10V4Z
10U_0805_10V4Z
Close to Pin48
4
VCTRL12
C262
C262
@
@
1
2
C263
C263
2
1
10U_0805_10V4Z
10U_0805_10V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2007/08/28
2007/08/28
2007/08/28
LAN_X1
25MHz_20pF_6X25000017
25MHz_20pF_6X25000017
1
C244
C244
2
27P_0402_50V8J
27P_0402_50V8J
Deciphered Date
Deciphered Date
Deciphered Date
LAN_X2
12
27P_0402_50V8J
27P_0402_50V8J
2
10/09 update
1
C245
C245
Change the PCB Footprint from Y_KDS_1BX25000CK1A_2P to
2
Y_6X25000017_2P
2007/06/30
2007/06/30
2007/06/30
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
RTL8103EL LAN
RTL8103EL LAN
RTL8103EL LAN
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Montevina Blade UMA LA4105P 1.0
Custom
Montevina Blade UMA LA4105P 1.0
Custom
Montevina Blade UMA LA4105P 1.0
Custom
Saturday, July 18, 2009
Saturday, July 18, 2009
Saturday, July 18, 2009
Date: Sheet
Date: Sheet
Date: Sheet
25 45
25 45
25 45
of
of
1
of
A
B
C
D
E
Mini Card 0--TV tuner/WWAN/Robson
1 1
2 2
04/29 MV-1 add clock REQ pull high
+3VS
0821 Change +3VS to +3VS_WWAN
0811 Pins 37 and 43 connect to GND and remove +1.5VS
WXMIT_OFF#<22>
+3VALW +3VS_WWAN
0.01U_0402_16V7K
0.01U_0402_16V7K
1
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
CLKREQ#_10<17>
CLK_PCIE_MCARD0#<17> CLK_PCIE_MCARD0<17>
PCIE_RXN1<22> PCIE_RXP1<22>
PCIE_TXN1<22>
PCIE_TXP1<22>
+3VS_WWAN
R10
R10
1 2
10K_0402_5%
10K_0402_5%
1
C573
2
2MiniC@
2MiniC@ 2MiniC@
2MiniC@ 1 2 1 2
1 2 1 2
2MiniC@
2MiniC@ 2MiniC@
2MiniC@
CLKREQ#_10
D11
D11
21
CH751H-40_SC76
CH751H-40_SC76
2MiniC@
2MiniC@
C573
2MiniC@
2MiniC@
0.1U_0402_16V4Z
0.1U_0402_16V4Z
ICH_PCIE_WAKE# CH_DATA CH_CLK CLKREQ#_10
0_0402_5%
0_0402_5%
PCIE_TXN1 PCIE_TXP1
R427 0_0603_5%
R427 0_0603_5%
R428 0_0603_5%
R428 0_0603_5%
C572
C572
2MiniC@
2MiniC@
R419
R419
R421 0_0402_5%
R421 0_0402_5%
UTX<32>
4.7U_0805_10V4Z
4.7U_0805_10V4Z
1
C574
C574
2MiniC@
2MiniC@
2
PCIE_C_RXN1 PCIE_C_RXP1
R1129
R1129
1 2
33_0402_1%
33_0402_1%
M_WXMIT_OFF#
1
C575
C575
2MiniC@
2MiniC@
2
1 3 5 7
9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51
53
WWAN_POWER_OFF<32>
JP6
JP6
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51
GND1
FOX_AS0B226-S40N-7F
FOX_AS0B226-S40N-7F
CONN@
CONN@
+3VALW
GND2
2
2
4
4
6
6
8
8
10
10
12
12
14
14
16
16
18
18
20
20
22
22
24
24
26
26
28
28
30
30
32
32
34
34
36
36
38
38
40
40
42
42
44
44
46
46
48
48
50
50
52
52
54
+3VS_WWAN
R400
@ R400
@
1 2
0_0603_5%
0_0603_5%
S
S
G
G
2
SIM card Connector
UIM_PWR UIM_DATA UIM_CLK UIM_RST UIM_VPP
+1.5VS_WLAN
UIM_PWR
UIM_DATA_R
UIM_CLK UIM_RST UIM_VPP
M_WXMIT_OFF# PLT_RST#
R420 0_0805_5%@R420 0_0805_5%@
1 2
R422 0_0805_5%
R422 0_0805_5%
1 2
2MiniC@
2MiniC@
ICH_SMBCLK ICH_SMBDATA
+1.5VS_WLAN
+3VS_WWAN
+3VS_WWAN
D
D
13
Q52
@
Q52
@
SI2301BDS_SOT23
SI2301BDS_SOT23
+1.5VS_WLAN
USB20_N8 <22>
WW_LED# <33>
20090616 Gobi2 solution
UIM_DATA_R
2MiniC@
2MiniC@
R418
R418
1 2
0_1206_5%
0_1206_5%
+3VS
JP4
JP4
1
1
2
2
3
3
4
4
5
5
6
6
G1
7
7
G2
ACES_88266-07001
ACES_88266-07001
CONN@
CONN@
+3VALW +3VS_WWAN
R750
R750 22_0402_5%
22_0402_5%
1 2
UIM_CLK
1
C824 18P_0402_50V8J
18P_0402_50V8J
2
8 9
@C824
@
UIM_DATA
Mini Card
1
C566
C566
2
CLK_PCIE_MCARD2#<17> CLK_PCIE_MCARD2<17>
1 2
10K_0402_5%
10K_0402_5%
+3VS_WLAN
CLK_DEBUG_PORT_1<17>
R11
R11
2---WLAN
0.1U_0402_16V4Z
0.1U_0402_16V4Z
4.7U_0805_10V4Z
4.7U_0805_10V4Z
PCIE_RXN3<22> PCIE_RXP3<22>
04/29 MV-1 add clock REQ pull high
+3VS
+3VALW
1
C568
1 2 1 2
C568
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
C567
C567
2
CH_DATA<30>
CH_CLK<30>
CLKREQ#_6<17>
R423 0_0402_5%R423 0_0402_5% R425 0_0402_5%R425 0_0402_5%
PCIE_TXN3<22>
PCIE_TXP3<22>
CLKREQ#_6
0.01U_0402_16V7K
0.01U_0402_16V7K
1
2
ICH_PCIE_WAKE# CH_DATA CH_CLK CLKREQ#_6
CLK_PCIE_MCARD2# CLK_PCIE_MCARD2
PLT_RST#
PCIE_C_RXN3 PCIE_C_RXP3
PCIE_TXN3 PCIE_TXP3
+3VS_WLAN
+1.5VS_WLAN
4.7U_0805_10V4Z
4.7U_0805_10V4Z
1
C570
C570
2
XMIT_OFF<22>
1
C571
C571
2
JP7
JP7
1
1
3
3
5
5
7
7
9
9
11
11
13
13
15
15
17
17
19
19
21
21
23
23
25
25
27
27
29
29
31
31
33
33
35
35
37
37
39
39
41
41
43
43
45
45
47
47
49
49
51
51
53
GND1
GND2
FOX_AS0B226-S40N-7F
FOX_AS0B226-S40N-7F
CONN@
CONN@
C569
C569
0.1U_0402_16V4Z
0.1U_0402_16V4Z
01/03 Prevent WLAN leakage
R431 0_0805_5%R431 0_0805_5%
+1.5VS
+3VS +3VS_WLAN
02/13 Change WLAN and WWAN 0402 resistor to 0805, and WLAN change to +3VS power plane
2
2
4
4
6
6
8
8
10
10
12
12
14
14
16
16
18
18
20
20
22
22
24
24
26
26
28
28
30
30
32
32
34
34
36
36
38
38
40
40
42
42
44
44
46
46
48
48
50
50
52
52
54
D19
D19
CH751H-40_SC76
CH751H-40_SC76
+3VS_WLAN
+1.5VS_WLAN
R699 0_0402_5% DEBUG@R699 0_0402_5% DEBUG@ R700 0_0402_5% DEBUG@R700 0_0402_5% DEBUG@ R701 0_0402_5% DEBUG@R701 0_0402_5% DEBUG@ R702 0_0402_5% DEBUG@R702 0_0402_5% DEBUG@ R703 0_0402_5% DEBUG@R703 0_0402_5% DEBUG@
XMIT_OFF#
PLT_RST#
R424 0_0805_5%@R424 0_0805_5%@ R426 0_0805_5%
R426 0_0805_5%
ICH_SMBCLK
ICH_SMBDATA
R433
@R433
@
10K_0402_5%
10K_0402_5%
21
1 2
R432 0_0805_5%R432 0_0805_5%
1 2
1 2 1 2 1 2 1 2 1 2
1 2 1 2
USB20_N5 <22>USB20_P8 <22> USB20_P5 <22>
WL_LED# <33>
+1.5VS_WLAN
+3VS_WLAN
+3VALW
12
12
@
@
R434
R434 100K_0402_5%
100K_0402_5%
13
D
D
@
@
Q10
Q10
2
G
G
2N7002_SOT23-3
2N7002_SOT23-3
S
S
R435
R435
1 2
0_0402_5%
0_0402_5%
+3VALW +3VS_WLAN +1.5VS_WLAN
XMIT_OFF#
+1.5VS_WLAN
LPC_FRAME# <21,32> LPC_AD3 <21,32> LPC_AD2 <21,32> LPC_AD1 <21,32> LPC_AD0 <21,32>
Close to JEXP
NewC@
NewC@
R436 0_0402_5%
R436 0_0402_5%
1 2
R437 0_0402_5%
R437 0_0402_5%
1 2
NewC@
NewC@
R438
R438
1 2
0_0402_5%
0_0402_5%
NewC@
NewC@
+1.5VS_PEC +1.5VS_PEC
+3V_PEC
+3VS_PEC
Deciphered Date
Deciphered Date
Deciphered Date
USB9­USB9+ EXP_CPPE#
ICH_SMBCLK ICH_SMBDATA
PCIE_PME#_R
PERST#
CLKREQ#_4 EXP_CPPE#
D
JEXP1
JEXP1
1
GND
2
USB_D-
3
USB_D+
4
CPUSB#
5
RSV
6
RSV
7
SMB_CLK
8
SMB_DATA
9
+1.5V
10
+1.5V
11
WAKE#
12
+3.3VAUX
13
PERST#
14
+3.3V
15
+3.3V
16
CLKREQ#
17
CPPE#
18
REFCLK-
19
REFCLK+
20
GND
21
PERn0
22
PERp0
23
GND
24
PETn0
25
PETp0
26
GND
27
GND
28
GND
SANTA_130801-5_LT
SANTA_130801-5_LT
CONN@
CONN@
01/03 New card PTH connector GND
29
GND
30
GND
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
NewC@C576
NewC@
0.1U_0402_16V4Z
0.1U_0402_16V4Z
NewC@
NewC@
NewC@
NewC@
New Card
Express Card Power
+1.5VS
Switch
U16
12
+3VS
1.5Vin
14
1.5Vin
2
3.3Vin
4
3.3Vin
AUX_IN17AUX_OUT
6
SYSRST#
20
SHDN#
1
STBY#
10
CPPE#
9
CPUSB#
18
RCLKEN
R5538D001-TR-F_QFN20_4X4~D
R5538D001-TR-F_QFN20_4X4~D
B
NewC@U16
NewC@
1.5Vout
1.5Vout
3.3Vout
3.3Vout
OC#
PERST#
GND
USB20_N9<22>
11 13
3 5
15
19
8
16
NC
7
+1.5VS_PEC
+3VS_PEC
+3V_PEC
PERST#
04/29 MV-1 add clock REQ pull high
+3VS
R12
R12
10K_0402_5%
10K_0402_5%
Issued Date
Issued Date
Issued Date
CLKREQ#_4
C
1 2
Security Classification
Security Classification
Security Classification
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
USB20_P9<22>
ICH_SMBCLK<17,22>
ICH_SMBDATA<17,22>
ICH_PCIE_WAKE#<22,25>
CLKREQ#_4<17>
CLK_PCIE_NCARD#<17> CLK_PCIE_NCARD<17>
PCIE_RXN4<22> PCIE_RXP4<22>
PCIE_TXN4<22>
PCIE_TXP4<22>
2007/08/28 2006/07/26
2007/08/28 2006/07/26
2007/08/28 2006/07/26
3 3
C576
1 2
C579 0.1U_0402_16V4Z
C579 0.1U_0402_16V4Z
1 2
C580 0.1U_0402_16V4Z
C580 0.1U_0402_16V4Z
+3VALW
PLT_RST#<9,20,25,27>
SYSON<9,32,33,36,41>
SUSP#<28,32,36,38,40>
+3VALW
EXP_CPPE#<22>
1 2
PLT_RST#
SYSON
SUSP#
R439 100K_0402_5%@R439 100K_0402_5%@
EXP_CPPE#
1 2
05/08 MV-1 Delete R439
4 4
internal pull high to 3.3Vaux-in EC need setting at Hi-Z & output Low
A
Near to Express Card slot.
+3VS_PEC
1
1
C577
C577
0.1U_0402_16V4Z
0.1U_0402_16V4Z
NewC@
NewC@
+1.5VS_PEC
C581
C581
0.1U_0402_16V4Z
0.1U_0402_16V4Z
NewC@
NewC@
C583
C583
0.1U_0402_16V4Z
0.1U_0402_16V4Z
NewC@
NewC@
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
WLAN, WWAN, New Card
WLAN, WWAN, New Card
WLAN, WWAN, New Card
Montevina Blade UMA LA4105P
Montevina Blade UMA LA4105P
Montevina Blade UMA LA4105P
2
1
2
+3V_PEC
1
2
E
2
1
2
1
2
26 45Saturday, July 18, 2009
26 45Saturday, July 18, 2009
26 45Saturday, July 18, 2009
C578
C578
4.7U_0805_10V4Z
4.7U_0805_10V4Z
NewC@
NewC@
C582
C582
4.7U_0805_10V4Z
4.7U_0805_10V4Z
NewC@
NewC@
C584
C584
4.7U_0805_10V4Z
4.7U_0805_10V4Z
NewC@
NewC@
of
of
of
1.0
1.0
1.0
5
4
3
2
1
09/26 (JMicron)recommend C1328/1000pF close to U36 pin5
09/26 (JMicron)recommend place C1329/0.1uF near by C1328
09/26 (JMicron)recommend (APVDD, 20 mil width, less than 120mil long)
DV33 DV33 DV33 DV18 DV18
GND GND GND GND
NC NC NC
+1.8VS_CR
10U_0805_10V4Z
10U_0805_10V4Z
5 10 30
19 20 44 18 37
XD_SD_MS_D0
48
XD_SD_MS_D1
47
XD_SD_MS_D2
46
XD_SD_MS_D3
45
SDCMD_MSBS_XDWE#
43
SDCLK_MSCLK_XDCE#
42
XDWP#_SDWP#
41
XD_CLE
40
XD_D4
29
XD_D5
28
XD_D6
27
XD_D7
26
XD_RE#
25
XD_RB#
23
XD_ALE
22
34 35 36
6
24 31 32 33
C1326
C1326
+3VS
1
2
1
C1336
C1336
2
1
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
C1327
C1327
+3VS
0.1U_0402_16V4Z
0.1U_0402_16V4Z
+1.8VS_CR
1
C1332
C1332
2
1
1
2
2
C1328
C1328 1000P_0402_50V7K
1000P_0402_50V7K
1
C1334
C1334
2
C1329
C1329
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
C1335
C1335
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
1
C1333
C1333
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
11/07 Stuff for JMB385 internal LDO
R704
R704
0_0603_5%
0_0603_5%
1 2
C1324
C1324
10U_0805_10V4Z
10U_0805_10V4Z
Use 0603 type and over 20 mils trace width on both side
+VCC_4IN1+VCC_OUT
1
12
C1325
C1325
0.1U_0805_50V7M
0.1U_0805_50V7M
2
09/26 (JMicron)recommend change to 0805 Size
09/26 (JMicron)recommend +VCC_OUT >30mil
+VCC_4IN1+VCC_OUT
C1331
C1331
1
2
40mil
12
@R1050
@
150K_0402_5%
150K_0402_5%
C1330
C1330
0.1U_0402_16V4Z
0.1U_0402_16V4Z
+3VS
1
2
U37
@U37
@
3
IN
OUT
4
EN
OUT
2
GND
G5250C2T1U_SOT23-5
G5250C2T1U_SOT23-5
1U_0603_10V4Z
1U_0603_10V4Z
1 5
reserved power circuit
11/07 Change U37 correct PCBFootprint SOT23
11/07 BOM delete for JMB385 internal LDO
R1050
+3VS
R706
R707
R708
1 2 1 2 1 2
XDCD0#_SDCD# XDCD1#_MSCD#
12
@C788
@
100P_0402_25V8K
100P_0402_25V8K
1 2
@C789
@
100P_0402_25V8K
100P_0402_25V8K
1 2
@C790
@
100P_0402_25V8K
100P_0402_25V8K
D41
D41
2
3
DAN202U_SC70
DAN202U_SC70
09/26 (JMicron)recommend width/length: 12mil / <250mil for PREXT signal
XDWP#_SDWP#
XD_RB#
XD_CLE
XD_ALE
XD_ALE
C788
C789
C790
11/07 Change to 8.2K(vender)
11/09 Reserve D18 for cardreader wake up
(pin 7)
PCIE_RXN5<22>
PCIE_RXP5<22>
09/26 (JMicron)recommend add a test point for pin 13
CR_CPPE#<22>
CR_WAKE#<22>
02/13 Add D18
SDCLKSDCLK_MSCLK_XDCE# MSCLK XDCE#
XD_CD#
1
1
C1047
C1047 270P_0402_50V7K
270P_0402_50V7K
2
PCIE_TXN5<22> PCIE_TXP5<22>
CLK_SRC11#<17> CLK_SRC11<17>
C1321 0.1U_0402_16V4ZC1321 0.1U_0402_16V4Z
12
C1322 0.1U_0402_16V4ZC1322 0.1U_0402_16V4Z
12
R402 8.2K_0402_5%R402 8.2K_0402_5%
1 2
R972 10K_0402_5%R972 10K_0402_5%
1 2
+3VS
、、、、
14
PLT_RST#<9,20,25,26>
R404 0_0402_5%@ R404 0_0402_5%@
1 2
D18
D18
21
CH751H-40PT_SOD323-2
CH751H-40PT_SOD323-2
PCIE_C_RXN5 PCIE_C_RXP5
T78T78
XDCD1#_MSCD# XDCD0#_SDCD#
+VCC_OUT
use for PWR_EN#
CR_LED#
8mA sink current
PREXT
3 4
9 8
11 12
7
XIN
38 39
1 2
13 14
15 16
17
21
U36
U36
APCLKN APCLKP
APRXN APRXP
APTXN APTXP
APREXT
PCIES_EN PCIES
JMB385
JMB385
XRSTN XTEST
SEEDAT SEECLK
CR1_CD1N CR1_CD0N
CR1_PCTLN
CR1_LEDN
JMB385-LGEZ0A_LQFP48_7X7
JMB385-LGEZ0A_LQFP48_7X7
APVDD
APV18
TAV33
MDIO0 MDIO1 MDIO2 MDIO3 MDIO4 MDIO5 MDIO6 MDIO7 MDIO8
MDIO9 MDIO10 MDIO11 MDIO12 MDIO13 MDIO14
APGND
R1042 4.7K_0402_5%
R1042 4.7K_0402_5%
1 2
R1041 4.7K_0402_5%
R1041 4.7K_0402_5%
1 2
D D
+VCC_4IN1
R1044 10K_0402_5%
R1044 10K_0402_5% R1043 10K_0402_5%
R1043 10K_0402_5%
+3VS
R709 10K_0603_5%R709 10K_0603_5%
+3VS
@
@
R1048 10K_0603_5%
R1048 10K_0603_5%
R248 10K_0603_5%R248 10K_0603_5%
12 12
11/07 Change to 10K(vender)
1 2
1 2
1 2
01/03 Change Cardreader LED control
02/13 XD_ALE Change to LED low active
XD_RE#
R1046 200K_0402_5%
R1046 200K_0402_5%
1 2
XDCE#
C C
SDCLK
MSCLK
12
@R706
@
100_0402_5%
100_0402_5%
1 2
@R707
@
100_0402_5%
100_0402_5%
1 2
@R708
@
100_0402_5%
100_0402_5%
R710 22_0402_5%R710 22_0402_5% R711 22_0402_5%R711 22_0402_5% R712 22_0402_5%R712 22_0402_5%
XDCD1#_MSCD#
XDCD0#_SDCD#
Card Reader Connector
JREAD1
JREAD1
B B
A A
White LED: VF=3V, IF = 5mA, Res = 56ohm
11/09 don't support DIM function
+5VS
12
R719
R719 470_0402_5%
470_0402_5%
21
D15
D15
White
HT-F196BP5_WHITE
HT-F196BP5_WHITE
R249
R249
0_0402_5%
0_0402_5%
1 2
13
D
D
Q101
@
Q101
@
2N7002_SOT23-3
2N7002_SOT23-3
2
G
G
S
S
CR_LED#
R194
4.7K_0402_5%
4.7K_0402_5%
1 2
@R194
@
+VCC_4IN1
XD_SD_MS_D0 XD_SD_MS_D1 XD_SD_MS_D2 XD_SD_MS_D3 XD_D4 XD_D5 XD_D6 XD_D7
SDCMD_MSBS_XDWE# XDWP#_SDWP# XD_ALE XD_CD# XD_RB# XD_RE# XDCE# XD_CLE
3
XD-VCC
32
XD-D0
10
9 8 7 6 5 4
34 33 35 40 39 38 37 36
11 31
41 42
7 IN 1 CONN
7 IN 1 CONN
XD-D1 XD-D2 XD-D3 XD-D4 XD-D5 XD-D6 XD-D7
XD-WE XD-WP XD-ALE XD-CD XD-R/B XD-RE XD-CE XD-CLE
7IN1 GND 7IN1 GND
7IN1 GND 7IN1 GND
TAITW_R015-B10-LM
TAITW_R015-B10-LM
CONN@
CONN@
11/17 Update CIS library
SD-VCC
MS-VCC
SD_CLK SD-DAT0 SD-DAT1 SD-DAT2 SD-DAT3 SD-DAT4 SD-DAT5 SD-DAT6 SD-DAT7
SD-CMD
SD-CD-SW
SD-WP-SW
MS-SCLK
MS-DATA0 MS-DATA1 MS-DATA2 MS-DATA3
MS-INS
MS-BS
21 28
SDCLK
20
XD_SD_MS_D0
14
XD_SD_MS_D1
12
XD_SD_MS_D2
30
XD_SD_MS_D3
29
XD_D4
27
XD_D5
23
XD_D6
18
XD_D7
16
SDCMD_MSBS_XDWE#
25
XDCD0#_SDCD#
1
XDWP#_SDWP#
2
MSCLK
26
XD_SD_MS_D0
17
XD_SD_MS_D1
15
XD_SD_MS_D2
19
XD_SD_MS_D3
24
XDCD1#_MSCD#
22
SDCMD_MSBS_XDWE#
13
+VCC_4IN1
01/03 Change Cardreader LED control
02/13 Direct driver LED
5
4
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2007/08/28 2006/10/06
2007/08/28 2006/10/06
2007/08/28 2006/10/06
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2
delete +1.8VS_CR R
Title
Title
Title
USB CardReader&CONN
USB CardReader&CONN
USB CardReader&CONN
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
Date: Sheet
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Montevina Blade UMA LA4105P
Montevina Blade UMA LA4105P
Montevina Blade UMA LA4105P
1
27 45Saturday, July 18, 2009
27 45Saturday, July 18, 2009
27 45Saturday, July 18, 2009
1.0
1.0
1.0
of
of
of
A
B
C
D
E
CODEC POWER
+1.5VS_HDA
R1051
R1051
1 2
BLM18BD601SN1D_0603
BLM18BD601SN1D_0603
0.1U_0402_16V4Z
0.1U_0402_16V4Z
C1342
C1342
1 1
HDA_BITCLK_CODEC
12
@
@
R1054
R1054
47_0402_5%
47_0402_5%
2 2
33P_0402_50V8K
33P_0402_50V8K
3 3
@
@
C1345
C1345
C1358
@C1358
@
1 2
C1359
@C1359
@
1 2
C1360
@C1360
@
1 2
C1361
@C1361
@
1 2
C1362
C1362
R1065
R1065
R596
R596
1 2
1 2
1 2
1
2
11/09 reserve EC_BEEP
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0_0402_5%
0_0402_5%
0_1206_5%
0_1206_5%
0_1206_5%
0_1206_5%
R445
@R445
@
47K_0402_5%
47K_0402_5%
EC_BEEP
EC_BEEP<32>
1 2
SB_SPKR<22>
GNDA <29,34>
1
2
HDA_BITCLK_CODEC<21>
HDA_SDOUT_CODEC<21>
HDA_SDIN0<21>
HDA_SYNC_CODEC<21>
HDA_RST#_CODEC<21,32>
DMIC_CLK<19>
R1060 47K_0402_5%R1060 47K_0402_5%
1 2
R1061 10K_0402_5%R1061 10K_0402_5%
1 2
C1349 0.1U_0402_16V4ZC1349 0.1U_0402_16V4Z
1 2
+VDDA_CODEC_R
SENSE_B#<34>
R1062 5.1K_0402_1%R1062 5.1K_0402_1% R1063 39.2K_0402_1%R1063 39.2K_0402_1%
+1.5VS
+3VDD_CODEC
+VDDA_CODEC_R
+1.5VS_HDA
HDA_BITCLK_CODEC
HDA_SDOUT_CODEC
R1055
1 2
HDA_SYNC_CODEC
HDA_RST#_CODEC
R1058 22_0402_5%
R1058 22_0402_5%
1 2 1 2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
C1355
C1355 10U_0805_10V4Z
10U_0805_10V4Z
R1052
R1052
1 2
+3VS +VDDA_CODEC
BLM18BD601SN1D_0603
BLM18BD601SN1D_0603
HDA_SDIN0_CODEC
R1055
33_0402_5%
33_0402_5%
1 2
C1347
C1347
12
1U_0603_10V4Z
1U_0603_10V4Z
MONO_INR
1 2
C1348 0.1U_0402_16V4ZC1348 0.1U_0402_16V4Z
SENSEB#
1
C1353
C1353
2
VC_REFA
1 2
+3VDD_CODEC +5VALW
1
2
C1337
C1337
1U_0603_10V4Z
1U_0603_10V4Z
U38
U38
9
DVDD_CORE*
1
DVDD_CORE
25
AVDD1*
38
AVDD2**
3
DVDD_IO
32
MONO_OUT
6
BITCLK
5
SDO
8
SDI_CODEC
10
SYNC
11
RESET#
46
DMIC_CLK
33
CAP2
12
PCBEEP
40
NC / OTP
34
SENSE_B / NC
37
NC
18
NC
19
NC
20
NC
27
VREFFILT
26
AVSS1*
42
AVSS2**
7
DVSS**
92HD71B7X5NLGXA1X8_QFN48_7X7
92HD71B7X5NLGXA1X8_QFN48_7X7
+VDDA_CODEC_R
1
2
C1338
0.1U_0402_16V4Z
C1338
0.1U_0402_16V4Z
C1339
0.1U_0402_16V4Z
C1339
0.1U_0402_16V4Z
EAPD/ SPDIF OUT 0 or 1 / GPIO 0
VOL_UP/DMIC_0/GPIO 1
VOL_DN/DMIC_1/GPIO 2
SPDIF OUT1 / GPIO 7
1 2
1
1
2
2
1U_0603_10V4Z
1U_0603_10V4Z
C1340
C1340
GPIO 3
VREFOUT-E / GPIO 4
GPIO 5
GPIO 6
SPDIF OUT0
VREFOUT-B
VREFOUT-C
SENSE_A
PORTA_R
PORTA_L
PORTB_R
PORTB_L
PORTC_R
PORTC_L
PORTD_R
PORTD_L
PORTE_R
PORTE_L
PORTF_R
PORTF_L
R1053
R1053
0_0603_5%
0_0603_5%
EAPD_CODEC
47
2
4
30
31
43
44
SPDIF_OUT
45
48
VREFOUT_B
28
29
SENSE
13
HP_OUTR
41
HP_OUTL
39
MIC_EXTR
22
21
24
23
36
35
15
14
17
16
C1350 1U_0603_10V6K
C1350 1U_0603_10V6K
MIC_EXTL
C1351 1U_0603_10V6K
C1351 1U_0603_10V6K
MIC_INR
MIC_INL
LINE_OUT_R
LINE_OUT_L
DOCK_MICR DOCK_MICR_C
DOCK_MICL
C1356 1U_0603_10V6K
C1356 1U_0603_10V6K
C1357 1U_0603_10V6K
C1357 1U_0603_10V6K
C1341
C1341
EAPD_CODEC <32>
DMIC_DAT <19>
SPDIF_OUT <34>
01/03 Change SPDIF to SPDIF1
VREFOUT_B <29>
R1056 5.1K_0402_1%R1056 5.1K_0402_1%
1 2
R1057 20K_0402_1%R1057 20K_0402_1%
1 2
R1059 39.2K_0402_1%R1059 39.2K_0402_1%
1 2
R683 10K_0402_1%
R683 10K_0402_1%
1 2
C1346 0.1U_0402_16V4ZC1346 0.1U_0402_16V4Z
1 2
HP_OUTR <29>
HP_OUTL <29>
1 2
1 2
LINE_OUT_R <29>
LINE_OUT_L <29>
1 2
1 2
DOCK_MICL_C
R735
R735
1.21K_0402_1%
1.21K_0402_1%
Internal SPKR.
W=40Mil
1 2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
SUSP#<26,32,36,38,40>
11/07 Change to 4.75V LDO
+VDDA_CODEC_R
HP Jack & Dock
MIC_EXT_R <29>
MIC_EXT_L <29>
C1352 0.022U_0402_16V7KC1352 0.022U_0402_16V7K
12
@R1064
@
0_0603_5%
0_0603_5%
C1354 0.022U_0402_16V7KC1354 0.022U_0402_16V7K
12
Jack MIC
1 2
R1064
1 2
R733 10K_0402_5%R733 10K_0402_5%
1 2
R734 10K_0402_5%R734 10K_0402_5%
1 2
12
R736
R736
1.21K_0402_1%
1.21K_0402_1%
1/10*Vin need close to Codec
U39
U39
1
IN
OUT
2
GND
3
SHDN
BYP
G9191-475T1U_SOT23-5
G9191-475T1U_SOT23-5
EXTMIC_DET# <29> JACK_DET# <29,34> INTMIC_DET# <29>
11/08 Change C1352、、、C1354 (recommend)
11/07 Change R1059
39.2K
MIC_IN_R <29>
Internal MIC
MIC_IN_L <29>
5
4
DOCK_MIC_R <34>
DOCK_MIC_L <34>
GNDAGND
11/07 Stuff 0 Ohm for AGND and GND
SENSE A SENSE B
Port Resistor Port Resistor
(4.75V(4.56~4.94V))
+VDDA_CODEC
2.2U_0805_16V4Z
2.2U_0805_16V4Z
1
2
C1343
C1343
1
C1344
C1344
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
DOCK MIC
300mA
A 39.2K
4 4
B 20K
C 10K
D 5.11K
A
E
F
G
H
39.2K
20K
10K
5.11K
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2007/08/28 2006/07/26
2007/08/28 2006/07/26
2007/08/28 2006/07/26
Deciphered Date
Deciphered Date
Deciphered Date
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
D
Date: Sheet
Codec_IDT9271B7
Codec_IDT9271B7
Codec_IDT9271B7
Montevina Blade UMA LA4105P
Montevina Blade UMA LA4105P
Montevina Blade UMA LA4105P
28 45Saturday, July 18, 2009
28 45Saturday, July 18, 2009
28 45Saturday, July 18, 2009
E
1.0
1.0
1.0
of
of
of
A
B
C
D
E
GAIN0 GAIN1 Av(inv)
+3VALW
R676
R676
10K_0402_5%
10K_0402_5%
DOCK@
DOCK@
Q16A
Q16A
DOCK@
DOCK@
2
+1.5VS
1
C620
C620
2
1000P_0402_50V7K
1000P_0402_50V7K
0
1
0
1
JACK_DET#<28,34>
1 2
61
2N7002DW-7-F_SOT363-6
2N7002DW-7-F_SOT363-6
1
C621
@C621
@
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
4.7U_0805_10V4Z
4.7U_0805_10V4Z
+5VS+5VAMP
R394
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
C282
1 1
U40
U40
C285 0.022U_0603_25V7KC285 0.022U_0603_25V7K
1 2 1 2
C286 47P_0402_50V8JC286 47P_0402_50V8J
C287 0.022U_0603_25V7KC287 0.022U_0603_25V7K
LINE_OUT_R<28>
LINE_OUT_L<28>
2 2
3 3
EC_MUTE#<32>
1 2 1 2
C288 47P_0402_50V8JC288 47P_0402_50V8J
C289 0.022U_0603_25V7KC289 0.022U_0603_25V7K
1 2 1 2
C290 47P_0402_50V8JC290 47P_0402_50V8J
C291 0.022U_0603_25V7KC291 0.022U_0603_25V7K
1 2 1 2
C292 47P_0402_50V8JC292 47P_0402_50V8J
EC_MUTE#
VREFOUT_B<28>
MIC_EXT_R<28>
7
RIN+
17
RIN-
9
LIN+
5
LIN-
19
SHUTDOWN
20
R684
R684
0_0402_5%
0_0402_5%
4.7K_0402_5%
4.7K_0402_5%
MIC_EXT_R
MIC_EXT_L<28>
MIC_EXT_L
10U_0805_10V4Z
10U_0805_10V4Z
16
15
6
VDD
PVDD1
PVDD2
GAIN0
GAIN1
ROUT+
ROUT-
LOUT+
LOUT-
BYPASS
GND41GND311GND213GND1
THERMAL PAD
21
TPA6017A2_TSSOP20
TPA6017A2_TSSOP20
12
12
R685
R685
C282
C787
C787
12
1
C283
C283
2
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
3
SPKR+
18
SPKR-
14
SPKL+
4
SPKL-
8
12
NC
10
12/18 Shut down pop noise
1 2
1U_0603_10V4Z
1U_0603_10V4Z
R686
R686
4.7K_0402_5%
4.7K_0402_5%
EXTMIC IN
R394
1 2
0_1206_5%
0_1206_5%
1
C284
C284
2
R395
@R395
@
100K_0402_5%
100K_0402_5%
R397
R397
100K_0402_5%
100K_0402_5%
Keep 10 mil width
1
C293
C293 1U_0805_25V6K
1U_0805_25V6K
2
15.6 dB
12
12
+5VS
12
12
1 2
0_0402_5%
0_0402_5%
0
0
1
1
11/17 Change to15.6 dB
R396
R396 100K_0402_5%
100K_0402_5%
R398
@R398
@
100K_0402_5%
100K_0402_5%
+3VALW
R401
R401
10K_0402_5%
10K_0402_5%
1 2
HP_DET#
11/07 Add 10K PU
HP_OUTR<28>
HP_OUTL<28>
OPP@
OPP@
R192
R192
HP_DET#JACK_DET#
MDC 1.5 Conn.
JP8
JP8
1
GND1
3
IAC_SDATA_OUT
5
GND2
7
IAC_SYNC
9
IAC_SDATA_IN
11
IAC_RESET#
GND13GND14GND15GND16GND17GND
Connector for MDC Rev1.5
Connector for MDC Rev1.5
CONN@
CONN@
1 2
HDA_SDOUT_MDC
HDA_SYNC_MDC HDA_SDIN1_MDC
HDA_SDOUT_MDC<21>
HDA_SYNC_MDC<21> MIC_IN_R<28>
HDA_SDIN1<21>
HDA_RST#_MDC<21>
H12
H12
H14
H14
HOLEA
HOLEA
HOLEA
HOLEA
4 4
1
1
R477 33_0402_5%R477 33_0402_5%
RES0 RES1
GND3 GND4
IAC_BITCLK
18
2 4 6
3.3V
8 10 12
ACES_88018-124G
ACES_88018-124G
R475 0_0603_5%R475 0_0603_5%
R476 0_0603_5%@ R476 0_0603_5%@
+3VS
R478
@R478
@
10_0402_5%
10_0402_5%
1 2
1 2
12
@C618
@
+1.5VS
+3VS
HDA_BITCLK_MDC <21>
1 2
C618 10P_0402_25V8K
10P_0402_25V8K
1
C619
C619
2
Q16B
Q16B
DOCK@
DOCK@
5
2
G
G
6dB
10dB
15.6dB
21.6dB
3
4
2N7002DW-7-F_SOT363-6
2N7002DW-7-F_SOT363-6
Q46
Q46
13
D
D
2N7002_SOT23-3
2N7002_SOT23-3
DOCK@
DOCK@
S
S
Q17B
Q17B
DOCK@
DOCK@
3
2N7002DW-7-F_SOT363-6
2N7002DW-7-F_SOT363-6
Q17A
Q17A
2
DOCK@
DOCK@
6 1
2N7002DW-7-F_SOT363-6
2N7002DW-7-F_SOT363-6
SPKR­SPKR+ SPKL­SPKL+
B+
C1378
C1378
12
R678
R678 330K_0402_5%
330K_0402_5%
DOCK@
DOCK@
5
4
R1105 0_0603_5%R1105 0_0603_5%
1 2
R1104 0_0603_5%R1104 0_0603_5%
1 2
R1103 0_0603_5%R1103 0_0603_5%
1 2
R1102 0_0603_5%R1102 0_0603_5%
1
1
2
100P_0402_50V8J
100P_0402_50V8J
1
2
2
C1377
C1377
C1376
C1376
100P_0402_50V8J
100P_0402_50V8J
100P_0402_50V8J
100P_0402_50V8J
1 2
1
2
C1375
C1375
100P_0402_50V8J
100P_0402_50V8J
PSOT24C_SOT23-3
PSOT24C_SOT23-3
8/31EMI request
04/29 MV-1 add 2 2N7002 for Docking issue
1
C270
C270
0.01U_0402_25V7K
0.01U_0402_25V7K
2
DOCK@
DOCK@
Q14B
Q14B
5
DOCK@
DOCK@
4
2N7002DW-7-F_SOT363-6
2N7002DW-7-F_SOT363-6
Q14A
Q14A
2
DOCK@
DOCK@
2N7002DW-7-F_SOT363-6
2N7002DW-7-F_SOT363-6
61
11/07 Add Capacitor avoid DC lever to Docking audio
+VDDA_CODEC
MIC_IN_L<28>
ANA_MIC_DET<32>
INTMIC_DET#<28>
HP OUT
1 2
3
150U_B_6.3VM_R40M
150U_B_6.3VM_R40M
1 2
150U_B_6.3VM_R40M
150U_B_6.3VM_R40M
C785
C785
1 2
C786
C786
1 2
R1077
R1077
1K_0402_5%
1K_0402_5%
4.7K_0402_5%
4.7K_0402_5%
+3VS
R681 10K_0402_5%R681 10K_0402_5%
61
Q18A
Q18A
2
DOCK@
DOCK@
C295
C295
+
+
DOCK@
DOCK@
C296
C296
+
+
+
+
+
+
R1078
R1078
12
D55
@D55
@
PSOT24C_SOT23-3
PSOT24C_SOT23-3
EXTMIC_DET#<28>
CIR_IN<32,34>
1 2
1 2
150U_B_6.3VM_R40M
150U_B_6.3VM_R40M
150U_B_6.3VM_R40M
150U_B_6.3VM_R40M
C1379
C1379
1U_0603_10V4Z
1U_0603_10V4Z
1 2
12
12
R1079
R1079
4.7K_0402_5%
4.7K_0402_5%
12
3
4
2
3
1
R409
R409
DOCK@
DOCK@
R410
R410
DOCK@
DOCK@
+VDDA_CODEC
Q18B
Q18B
5
2
3
11/07Change JP60 PCB Footprint from
1
ACES_85204-04001_4P to ACES_88231-04001_4P
D56
@D56
@
Audio/B & CIR
MIC_EXT_R MIC_EXT_L
HP_OUT_R HP_OUT_L
EXTMIC_DET# HP_DET#
CIR_IN
+5VL
47_0402_5%
47_0402_5%
HP OUT For Docking
47_0402_5%
47_0402_5%
HP_OUT_R
HP OUT For M/B
HP_OUT_L
R951
R951 10K_0402_5%
10K_0402_5%
1 2
JP51
JP51
1 2 3 4
5 6
ACES_88231-04001
ACES_88231-04001
CONN@
CONN@
6 5
4 3 2 1
INTMIC IN
1 2 3 4
GND1 GND2
SPEAKER
JP60
JP60
GND2 GND1
4 3 2 1
ACES_88231-04001
ACES_88231-04001
CONN@
CONN@
JP49
JP49
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
ACES_87213-1400G
ACES_87213-1400G
CONN@
CONN@
DOCK_LOUT_R <34>
DOCK_LOUT_L <34>
MDC Standoff
2N7002DW-7-F_SOT363-6
2N7002DW-7-F_SOT363-6
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2007/08/28 2006/07/26
2007/08/28 2006/07/26
2007/08/28 2006/07/26
Deciphered Date
Deciphered Date
Deciphered Date
D
2N7002DW-7-F_SOT363-6
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
Date: Sheet
2N7002DW-7-F_SOT363-6
AMP & Audio Jack
AMP & Audio Jack
AMP & Audio Jack
Montevina Blade UMA LA4105P
Montevina Blade UMA LA4105P
Montevina Blade UMA LA4105P
E
1.0
1.0
29 45Saturday, July 18, 2009
29 45Saturday, July 18, 2009
29 45Saturday, July 18, 2009
1.0
of
of
of
5
4
3
2
1
Left side USB Power Switch Left side ESATA/USB combination Connector
+5VALW
U41
U41
1
GND
2
D D
C1381
C1381
4.7U_0805_10V4Z
4.7U_0805_10V4Z
C C
USB_EN#
1
2
IN
3
IN
4
EN#
TPS2061IDGNR_MSOP8
TPS2061IDGNR_MSOP8
OUT OUT OUT OC#
8
W=100mils
7 6 5
1
+
+
C1380
C1380
2
150U_D_6.3VM
150U_D_6.3VM
R1083 10K_0402_5%R1083 10K_0402_5%
+5VALW
USB20_P2
1
C1382
C1382
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1 2
D45
D45
4
VIN
3
IO2
@
@
PRTR5V0U2X_SOT143-4
PRTR5V0U2X_SOT143-4
USB_VCCC
1
C1383
C1383
2
1000P_0402_50V7K
1000P_0402_50V7K
IO1
GND
USB_VCCC
R1080 0_0402_5%R1080 0_0402_5%
USB20_N2<22> USB20_P2<22>
SATA_TXP5<21> SATA_TXN5<21>
SATA_RXN5_C<21>
+5VALW
USB20_N2
2
1
SATA_RXP5_C<21>
1 2
R1081 0_0402_5%R1081 0_0402_5%
1 2
C1385 0.01U_0402_16V7K
C1385 0.01U_0402_16V7K
12
C1384 0.01U_0402_16V7K
C1384 0.01U_0402_16V7K
12
ESATA@
ESATA@ ESATA@
ESATA@
USB20_N2_R USB20_P2_R
SATA_TXP5 SATA_TXN5
SATA_RXN5 SATA_RXP5
+5VALW
SATA_TXN5
JP53
JP53
USB
USB
1
VBUS
2
D-
3
D+
4
GND
5
GND
6
A+
ESATA
ESATA
7
A-
8
GND
9
B-
10
B+
11
GND
12
GND
13
GND
14
GND
15
GND
TYCO_1759576-1
TYCO_1759576-1
CONN@
CONN@
D46
D46
4
IO1
VIN
3
GND
IO2
@
@
PRTR5V0U2X_SOT143-4
PRTR5V0U2X_SOT143-4
2
1
SATA_TXP5
Finger printer
@
@
R627 0_0603_5%
R627 0_0603_5%
1 2
S
+3VALW
USB20_N7<22> USB20_P7<22>
B B
S
G
G
2
USB_EN#
R634 0_0402_5%
R634 0_0402_5%
1 2
R635 0_0402_5%
R635 0_0402_5%
1 2
FP@
FP@ FP@
FP@
PACDN042_SOT23-3~D
PACDN042_SOT23-3~D
20070209 Add for FPR
D
D
13
Q31
@
Q31
@
SI2301BDS_SOT23
SI2301BDS_SOT23
D30
@D30
@
3
2
1
1
C756
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
USB20_N7_R USB20_P7_R
FP@C756
FP@
R405
@R405
@
1 2
0_0402_5%
0_0402_5%
04/28 MV1 Change to +3VS
1 2 3 4 5 6 GND GND
FP@R628
FP@
0_0603_5%
0_0603_5%
+3VS
R628
1 2
JP24
JP24
1 2 3 4 5 6 7 8
ACES_85201-06051
ACES_85201-06051
CONN@
CONN@
11/07 Change PCB Footprint to ACES_85201-06051_6P
USB cable connector for Right side
JP55
JP55
+5VALW
USB_EN#<32>
USB20_N0<22> USB20_P0<22>
USB20_N1<22> USB20_P1<22>
A A
USB_EN#
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
GND1
12
GND2
ACES_87213-1000G
ACES_87213-1000G
CONN@
CONN@
BT Connector
JP57
JP57
8
10
8
GND
7
7
USB20_P6_R
6
6
USB20_N6_R
5
5
4
4
3
3
2
2
1
9
1
GND
ACES_87213-0800G
ACES_87213-0800G
CONN@
CONN@
+3VS
R235
R235
1 2
+3VALW +3VAUX_BT
0_0603_5%
0_0603_5%
R236
@ R236
@
1 2
0_0603_5%
0_0603_5%
1
C1386
@C1386
@
1U_0603_10V4Z
1U_0603_10V4Z
2
R1092 10K_0402_5%
R1092 10K_0402_5%
BT_OFF<22>
01/03 Change BT power to +3VS
02/12 Change to 10K
1 2
02/12 Change BT connector type
R1084 0_0402_5%R1084 0_0402_5% R1085 0_0402_5%R1085 0_0402_5%
R1086 1K_0402_5%@ R1086 1K_0402_5%@
1 2
R1087 1K_0402_5%@ R1087 1K_0402_5%@
1 2
Need change to New version
12 12
0612 no install
+5VALW
USB20_N6_R
Q105 SI2301BDS_SOT23
Q105 SI2301BDS_SOT23
S
S
D
D
13
12
G
R1090
R1090 100K_0402_5%
100K_0402_5%
G
2
1
C1387
C1387
2
0.01U_0402_16V7K
0.01U_0402_16V7K
C1390
C1390
1 2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
+3VAUX_BT
4
3
PRTR5V0U2X_SOT143-4
PRTR5V0U2X_SOT143-4
@
@
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
C1388
C1388
2
4.7U_0805_10V4Z
4.7U_0805_10V4Z
D47
D47
VIN
IO2
IO1
GND
1
C1389
C1389
2
USB20_P6 <22> USB20_N6 <22> BT_LED <33> CH_DATA <26>
CH_CLK <26>
USB20_P6_R
2
1
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2007/08/28 2006/07/26
2007/08/28 2006/07/26
2007/08/28 2006/07/26
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
2
Date: Sheet
Compal Electronics, Inc.
USB, BT, eSATA
USB, BT, eSATA
USB, BT, eSATA
Montevina Blade UMA LA4105P
Montevina Blade UMA LA4105P
Montevina Blade UMA LA4105P
30 45Saturday, July 18, 2009
30 45Saturday, July 18, 2009
30 45Saturday, July 18, 2009
1
1.0
1.0
1.0
of
of
of
5
4
3
2
1
D D
0.1U_0402_16V4Z
0.1U_0402_16V4Z
FSEL#<32>
SPI_CLK<32>
C307
12
12
12
C307
12
22P_0402_50V8J
22P_0402_50V8J
C308
C308
12
22P_0402_50V8J
22P_0402_50V8J
C309
C309
12
22P_0402_50V8J
22P_0402_50V8J
R230
R230
SPI_FSEL#
33_0402_5%
33_0402_5%
R231
R231
SPI_CLK_R
33_0402_5%
33_0402_5%
R232
R232
C C
SPI_FWR#
12/27EMI request
33_0402_5%
33_0402_5%
+3VL
20mils
1
C712
C712
2
1 2
R553 10_0402_5%R553 10_0402_5%
1 2
R554 10_0402_5%R554 10_0402_5%
1 2
R556 10_0402_5%R556 10_0402_5%
SP07000F500 S SOCKET WIESON G6179-100000 8P SPIFLASH WIESO_G6179-100000_8P
C711
@ C711
@
0.1U_0402_16V4Z
0.1U_0402_16V4Z
SMB_EC_CK1<32,33,37> SMB_EC_DA1<32,33,37>
SPI_FSEL#
SPI_CLK_R
1
2
SPI ROM
U27
U27
8
VCC
VSS
3
W
7
HOLD
1
S
6
C
5
U28
8 7 6 5
AT24C16AN-10SI-2.7_SO8
AT24C16AN-10SI-2.7_SO8
Q
D
WIESON G6179 8P SPI
WIESON G6179 8P SPI
@U28
@
A0
VCC
A1
WP SCL
A2
SDA
GND
4
SPI_SOSPI_FWR#
2
+3VL+3VL
12
1 2 3 4
12
1 2
R555 0_0402_5%
R555 0_0402_5%
R552 100K_0402_5%
100K_0402_5%
R557 100K_0402_5%
100K_0402_5%
FRD#
@R552
@
11/16 Change TO +3VALW
02/18 Change TO +3VL
02/18 Delete KBC EEPROM
@R557
@
FRD# <32>FWR#<32>
Remove LPC Debug Port 20090618
HDCP ROM
C304
@C304
@
1
2
SPI_WP#
SPI_HOLD#
+3VS
8
3
7
1
6
5
U6
@U6
@
VSS
4
2
Q
VCC
W
HOLD
S
C
D
SST25LF080A_SO8-200mil
SST25LF080A_SO8-200mil
R415
@R415
@
1 2
15_0402_5%
15_0402_5%
SPI_SO_RSPI_SO_L
SPI_SO_R <22>
+3VS
B B
R411
@R411
@
R412
@R412
@
SPI_SB_CS#<22>
SPI_CLK_SB<22>
11/17 Add SB HDCP ROM
01/03 Change HDCP ROM to +3VS
02/13 Sparate SPI_CLK between SB and EC
1 2
1 2
SPI_SI<22>
SPI_WP#
3.3K_0402_5%
3.3K_0402_5%
SPI_HOLD#
3.3K_0402_5%
3.3K_0402_5%
SPI_SB_CS#
SPI_CLK_SB
SPI_SI
@R414
@
1 2
15_0402_5%
15_0402_5%
R414
+3VS
1 2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
R413
@ R413
@
1K_0402_5%
1K_0402_5%
A A
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2007/08/28 2006/07/26
2007/08/28 2006/07/26
2007/08/28 2006/07/26
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
2
Date: Sheet
Compal Electronics, Inc.
BIOS ROM
BIOS ROM
BIOS ROM
Montevina Blade UMA LA4105P
Montevina Blade UMA LA4105P
Montevina Blade UMA LA4105P
1
1.0
1.0
1.0
of
31 45Saturday, July 18, 2009
of
31 45Saturday, July 18, 2009
of
31 45Saturday, July 18, 2009
+3VL_EC
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
1
C715
C715
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
SMB_EC_DA1 SMB_EC_CK1 SMB_EC_DA2 SMB_EC_CK2
1
C716
C716
2
2
1000P_0402_50V7K
1000P_0402_50V7K
R573 4.7K_0402_5%R573 4.7K_0402_5%
1 2
R577 4.7K_0402_5%R577 4.7K_0402_5%
1 2
R574 4.7K_0402_5%R574 4.7K_0402_5%
1 2
R575 4.7K_0402_5%R575 4.7K_0402_5%
1 2
03/28 PV2 Change SM bus power to +3VL
CLK_PCI_EC<17>
1 2
+3VL
R578 47K_0402_5% R578 47K_0402_5%
C721 0.1U_0402_16V4ZC721 0.1U_0402_16V4Z
SYSON
R213
R213
8.2K_0402_5%
8.2K_0402_5%
1 2
SUSP#
12
R581
R581
8.2K_0402_5%
8.2K_0402_5%
11/07 Add SYSON and SUSP# PD
11/15 Delete PCI_PME#
R589
@R589
@
PCI_PME#<20>
WL_BLUE_BTN<33>
DOCK_SLP_BTN#<34>
11/07 Connect DOCK_SLP_BTN# to ON/OFFBTN
EC_PME# PCI_RST#
1
C324
C324
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
03/13 PV2 Add EMI solution
1 2
R190
R190
1 2
OPP@
OPP@
R592
R592
1 2
1
C325
C325
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
EC DEBUG
UTX
R233
@R233
@
port
LAN_POWER_OFF<25>
1 2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
C717
C717
12
12
12
R443
R443
0_0402_5%
0_0402_5%
1
C718
C718
2
C722
@C722
@
1 2
15P_0402_50V8J
15P_0402_50V8J
PCI_RST#
R713
R713 100K_0402_5%
100K_0402_5%
+3VL
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0805_5%
0_0805_5%
LAN_POWER_OFF_R
1000P_0402_50V7K
1000P_0402_50V7K
1
C719
C719
2
04/22 MV1 Change SMbus1 power to +3VL
+3VL +3VS
R576
@R576
@
1 2
33_0402_5%
33_0402_5%
EC_SCI#<22>
12
J1
11/09 Delete CLKRUN#
JOPENJ1JOPEN
11/09 Add HDA_RST# to EC
11/17 Change to +3VALW
04/29 MV1 Change to +3VL
+3VL
+3VALW
12
12
R124
@R124
@
R583
10K_0402_5%
10K_0402_5%
@R585
@
10K_0402_5%
10K_0402_5%
1 2
EC_PME#
EC_PME#
ON/OFFBTN
ESB_CLK<33>
ESB_DAT<33>
R583 10K_0402_5%
10K_0402_5%
+3VALW
12
R585
R191
R191 10K_0402_5%
10K_0402_5%
+3VL
ON/OFFBTN<33>
32.768KHZ_12.5P_1TJS125DJ2A073
32.768KHZ_12.5P_1TJS125DJ2A073
4.7K_0402_5%
4.7K_0402_5%
LID_SW#
WWAN_POWER_OFF<26>
R593
R593
R1100
R1100
TSATN#<9>
1 2
4.7K_0402_5%
4.7K_0402_5%
Y5
Y5
3
2
+3VL +3VL
LPC_FRAME#<21,26>
HDA_RST#_EC
+3VS
12
R721
R721 10K_0402_5%
10K_0402_5%
TP_BTN#
01/03 Change to +3VS
SMB_EC_CK1<31,33,37> SMB_EC_DA1<31,33,37> SMB_EC_CK2<6> SMB_EC_DA2<6>
CONA#<34>
UTX<26>
C723
C723 15P_0402_50V8J
15P_0402_50V8J
1 2
4
OUT
NC
1
IN
NC
1 2
C725
C725 15P_0402_50V8J
15P_0402_50V8J
12
R1099
R1099
4.7K_0402_5%
4.7K_0402_5%
1 2
SLP_S3#<22> SLP_S5#<22> EC_SMI#<22> LID_SW#<33>
1 2
DIM_LED<36> NUM_LED#<33>
R731 33_0402_5%R731 33_0402_5% R732 33_0402_5%R732 33_0402_5%
1 2
WWAN_POWER_OFF UTX LAN_POWER_OFF_R
ON/OFFBTN
CRY2
12
@
@
R595
R595 20M_0402_5%
20M_0402_5%
CRY1
1 2 1 2
GATEA20 KB_RST# SIRQ LPC_FRAME# LPC_AD3 LPC_AD2 LPC_AD1 LPC_AD0
CLK_PCI_EC
PCI_RST# ECRST#
KSI0 KSI1 KSI2 KSI3 KSI4 KSI5 KSI6 KSI7 KSO0 KSO1 KSO2 KSO3 KSO4 KSO5 KSO6 KSO7 KSO8 KSO9 KSO10 KSO11 KSO12 KSO13 KSO14 KSO15
SMB_EC_CK1 SMB_EC_DA1 SMB_EC_CK2 SMB_EC_DA2
SLP_S3# SLP_S5# EC_SMI# LID_SW# ESB_CLK_R ESB_DAT_R EC_PME#
CONA#
DIM_LED NUM_LED#
GATEA20<21> KB_RST#<21> SIRQ<22>
LPC_AD3<21,26> LPC_AD2<21,26> LPC_AD1<21,26> LPC_AD0<21,26>
PCI_RST#<20>
R403 0_0402_5%R403 0_0402_5%
R591 0_0603_5% @ R591 0_0603_5% @
+3VL +3VL_EC
R572
R572
1 2
0_0805_5%
0_0805_5%
U30
U30
1
GA20/GPIO00
2
KBRST#/GPIO01
3
SERIRQ#
4
LFRAME#
5
LAD3
7
LAD2
8
LAD1
10
LPC & MISC
LPC & MISC
LAD0
12
PCICLK
13
PCIRST#/GPIO05
37
ECRST#
20
SCI#/GPIO0E
38
CLKRUN#/GPIO1D
55
KSI0/GPIO30
56
KSI1/GPIO31
57
KSI2/GPIO32
58
KSI3/GPIO33
59
KSI4/GPIO34
60
KSI5/GPIO35
61
KSI6/GPIO36
62
KSI7/GPIO37
39
KSO0/GPIO20
40
KSO1/GPIO21
41
KSO2/GPIO22
42
KSO3/GPIO23
43
KSO4/GPIO24
44 45 46 47 48 49 50 51 52 53 54 81 82
77 78 79 80
6 14 15 16 17 18 19 25 28 29 30 31 32 34 36
122 123
+EC_AVCC
1
C315 10P_0402_25V8K
10P_0402_25V8K
2
ESB_CLK_R ESB_DAT_R
02/20 PV EMI reserve C315 near EC
Int. K/B
Int. K/B
KSO5/GPIO25
Matrix
Matrix
KSO6/GPIO26 KSO7/GPIO27 KSO8/GPIO28 KSO9/GPIO29 KSO10/GPIO2A KSO11/GPIO2B KSO12/GPIO2C KSO13/GPIO2D KSO14/GPIO2E KSO15/GPIO2F KSO16/GPIO48 KSO17/GPIO49
SCL1/GPIO44 SDA1/GPIO45 SCL2/GPIO46 SDA2/GPIO47
PM_SLP_S3#/GPIO04 PM_SLP_S5#/GPIO07 EC_SMI#/GPIO08 LID_SW#/GPIO0A SUSP#/GPIO0B PBTN_OUT#/GPIO0C EC_PME#/GPIO0D EC_THERM#/GPIO11 FAN_SPEED1/FANFB1/GPIO14 FANFB2/GPIO15 EC_TX/GPIO16 EC_RX/GPIO17 ON_OFF/GPIO18 PWR_LED#/GPIO19 NUMLED#/GPIO1A
XCLK1 XCLK0
+3VL_EC
12
@C315
@
+1.5VS
+EC_AVCC
9
22
33
67
96
111
125
VCC
VCC
VCC
VCC
VCC
VCC
AVCC
INVT_PWM/PWM1/GPIO0F
BEEP#/PWM2/GPIO10
FANPWM1/GPIO12
ACOFF/FANPWM2/GPIO13
PWM Output
PWM Output
BATT_TEMP/AD0/GPIO38
BATT_OVP/AD1/GPIO39
ADP_I/AD2/GPIO3A
AD Input
AD Input
SELIO2#/AD5/GPIO43
DAC_BRIG/DA0/GPIO3C
EN_DFAN1/DA1/GPIO3D
DA Output
DA Output
PS2 Interface
PS2 Interface
SPI Device Interface
SPI Device Interface
SPI Flash ROM
SPI Flash ROM
GPIO
GPIO
SM Bus
SM Bus
GPIO
GPIO
GND
GND
GND
11
24
35
94
L30
L30 0_0603_5%
0_0603_5%
1 2
C726 0.1U_0402_16V4Z
C726 0.1U_0402_16V4Z
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
IREF/DA2/GPIO3E
PSDAT1/GPIO4B PSCLK2/GPIO4C PSDAT2/GPIO4D
TP_CLK/PSCLK3/GPIO4E
TP_DATA/PSDAT3/GPIO4F
SDICS#/GPXOA00 SDICLK/GPXOA01
SDIDO/GPXOA02
CIR_RLC_TX/GPIO41
FSTCHG/SELIO#/GPIO50
BATT_CHGI_LED#/GPIO52
CAPS_LED#/GPIO53
BATT_LOW_LED#/GPIO54
SUSP_LED#/GPIO55
VR_ON/XCLK32K/GPIO57
EC_RSMRST#/GPXO03 EC_LID_OUT#/GPXO04
EC_SWI#/GPXO06
ICH_PWROK/GPXO06
GPO
GPO
BKOFF#/GPXO08
WL_OFF#/GPXO09
PM_SLP_S4#/GPXID1
GPI
GPI
GND
GND
AGND
KB926QFB0_LQFP128_14X14
KB926QFB0_LQFP128_14X14
69
113
ECAGND
L31
L31
1 2
PSCLK1/GPIO4A
SDIDI/GPXID0
SPICLK/GPIO58
CIR_RX/GPIO40
SYSON/GPIO56
AC_IN/GPIO59
EC_ON/GPXO05
ENBKL/GPXID2
21 23 26 27
63 64 65 66
AD3/GPIO3B
75
AD4/GPIO42
76
68 70 71 72
DA3/GPIO3F
83 84 85 86 87 88
97 98 99 109
119
SPIDI/RD#
120
SPIDO/WR#
126 128
SPICS#
73 74 89 90 91 92 93 95 121 127
100 101 102 103 104 105 106 107
GPXO10
108
GPXO11
110 112 114
GPXID3
115
GPXID4
116
GPXID5
117
GPXID6
118
GPXID7
124
V18R
For C Revision
0_0603_5%
0_0603_5%
2007/08/28 2006/07/26
2007/08/28 2006/07/26
2007/08/28 2006/07/26
HDA_RST#_CODEC<21,28>
Current limit
R1130 22_0402_5%R1130 22_0402_5%
1 2
FAN_PWM EC_BEEP ACOFF
BATT_TEMP BATT_OVP ADP_I ADP_ID TP_BTN# ANA_MIC_DET
DAC_BRIG VCTRL IREF AC_SET
EC_MUTE# USB_EN# I2C_INT MUTE_LED TP_CLK TP_DATA
DOCK_VOL_UP# DOCK_VOL_DWN#
R227 33_0402_5%
R227 33_0402_5%
1 2
R228 47_0402_5%
R228 47_0402_5%
1 2
R229 33_0402_5%
R229 33_0402_5%
1 2
CIR_IN
FSTCHG STD_ADP CAPS_LED# BAT_LED# ON/OFFBTN_LED#
VR_ON AC_IN
EC_RSMRST#
R588
R588
1 2
EC_ON
0_0402_5%
0_0402_5%
WL_BLUE_LED# PM_PWROK_R
M_PWROK TP_LED#
SLP_S4# ENBKL EAPD_CODEC THERM_SCI# SUSP# PWRBTN_OUT# NMI_DBG#
1
C724
C724
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
2
NMI_DBG# PCI_SERR#
AC_IN ACIN
1 2
C791 100P_0402_50V8JC791 100P_0402_50V8J
Vendor Recommend
FAN_PWM <6> EC_BEEP <28> ACOFF <38>
BATT_TEMP <37> BATT_OVP <37> ADP_I <38> ADP_ID <37>
DAC_BRIG <19>
VCTRL <38> IREF <38> AC_SET <38>
EC_MUTE# <29>
USB_EN# <30> I2C_INT <33> MUTE_LED <34>
R582 0_0402_5%R582 0_0402_5%
1 2
DOCK_VOL_UP# <34> DOCK_VOL_DWN# <34>
R720 10K_0402_5%R720 10K_0402_5%
1 2
FSTCHG <38>
CAPS_LED# <33>
BAT_LED# <33>
ON/OFFBTN_LED# <33>
VR_ON <43>
R586 10K_0402_5%
R586 10K_0402_5%
EC_RSMRST# <22>
EC_LID_OUT# <22>
EC_ON <39>
M_PWROK <9,22> TP_LED# <33>
SLP_S4# <22,36>
THERM_SCI# <22> SUSP# <26,28,36,38,40>
PWRBTN_OUT# <22>
+3VL
12
R714
R714
+3VL
12
Deciphered Date
Deciphered Date
Deciphered Date
12
R250
R250 56_0402_5%
56_0402_5%
B
B
2
E
E
3 1
C
C
Q21
Q21
MMBT3904_NL_SOT23-3
MMBT3904_NL_SOT23-3
INV_PWM <19>
0.01U_0402_16V7K
0.01U_0402_16V7K
C720
C720
TP_BTN# <33> ANA_MIC_DET <29>
ECAGND
1 2
R579 10K_0402_5%R579 10K_0402_5% R580 10K_0402_5%R580 10K_0402_5%
02/13 Correct AC_LED control by EC
11/09 don't stuff when use C0
FRD# FWR# SPI_CLK FSEL#
CIR_IN <29,34>
STD_ADP <38>
12
WL_BLUE_LED# <33>
11/09 PU +5VL move to M/B
1 2
1 2
R1131
R1131
1 2
PV PWROK sequence issue
11/07 Add SLP_S4# to South bridge
ENBKL <11> EAPD_CODEC <28>
10K_0402_5%
10K_0402_5%
D14
D14
21
CH751H-40PT_SOD323-2
CH751H-40PT_SOD323-2
11/07 Correct direction pretect leakage
R715
R715 150K_0402_5%
150K_0402_5%
2 1
04/29 MV1 Change to 150K
D13
D13
CH751H-40PT_SOD323-2
CH751H-40PT_SOD323-2
+3VS
12
R251
R251 10K_0402_5%
10K_0402_5%
HDA_RST#_EC
02/13 Add HDA level shift
1 2 1 2
TP_CLK <33> TP_DATA <33>
AC_LED# <37>
FRD# <31> FWR# <31> SPI_CLK <31> FSEL# <31>
+5VL
10K_0402_5%
10K_0402_5%
R1132
R1132
12
C1408
C1408
R1133
R1133
100K_0402_5%
100K_0402_5%
R254
R254
100_0402_5%
100_0402_5%
22_0402_5%
22_0402_5%
Current limit
ADP_ID
2 1
CH751H-40PT_SOD323-2
CH751H-40PT_SOD323-2
PCI_SERR# <20>
ACIN <38>
C301
BATT_OVP
11/09 EC recommend
C301
12
100P_0402_50V8J
100P_0402_50V8J
For EMI
KSO15
C792 100P_0402_50V8J@C792 100P_0402_50V8J@
C793 100P_0402_50V8J@C793 100P_0402_50V8J@
C794 100P_0402_50V8J@C794 100P_0402_50V8J@
C795 100P_0402_50V8J@C795 100P_0402_50V8J@
C796 100P_0402_50V8J@C796 100P_0402_50V8J@
C797 100P_0402_50V8J@C797 100P_0402_50V8J@
C798 100P_0402_50V8J@C798 100P_0402_50V8J@
C799 100P_0402_50V8J@C799 100P_0402_50V8J@
C800 100P_0402_50V8J@C800 100P_0402_50V8J@
C801 100P_0402_50V8J@C801 100P_0402_50V8J@
C802 100P_0402_50V8J@C802 100P_0402_50V8J@
C803 100P_0402_50V8J@C803 100P_0402_50V8J@
C804 100P_0402_50V8J@C804 100P_0402_50V8J@
C805 100P_0402_50V8J@C805 100P_0402_50V8J@
C806 100P_0402_50V8J@C806 100P_0402_50V8J@
C807 100P_0402_50V8J@C807 100P_0402_50V8J@
C808 100P_0402_50V8J@C808 100P_0402_50V8J@
C809 100P_0402_50V8J@C809 100P_0402_50V8J@
C810 100P_0402_50V8J@C810 100P_0402_50V8J@
C811 100P_0402_50V8J@C811 100P_0402_50V8J@
C812 100P_0402_50V8J@C812 100P_0402_50V8J@
C813 100P_0402_50V8J@C813 100P_0402_50V8J@
C814 100P_0402_50V8J@C814 100P_0402_50V8J@
C815 100P_0402_50V8J@C815 100P_0402_50V8J@
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
R407
R407 10K_0402_5%
10K_0402_5%
R408
R408 10K_0402_5%
10K_0402_5%
+3VS
12
12
+5V_TP
SPI_CLK
1
SYSON
2
<9,26,33,36,41>
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
PM_PWROK <9,22> BKOFF# <19>
KSO10
KSO11
KSO14
KSO13
KSO12
KSO3
KSO6
KSO8
KSO7
KSO4
KSO2
KSI0
KSO1
KSO5
KSI3
KSI2
KSO0
KSI5
KSI4
KSO9
KSI6
KSI7
KSI1
2
C818
C818 22P_0402_50V8J
22P_0402_50V8J
1
DOCK_VOL_UP#
DOCK_VOL_DWN#
14" INT_KBD CONN.( TYPE "D" KB)
JP19
JP19
KSO15
1
KSO10
2
KSO11
3
KSO14
4
KSO13
+3VL
D16
D16
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
Compal Electronics, Inc.
EC KB926/KB Conn.
EC KB926/KB Conn.
EC KB926/KB Conn.
Montevina Blade UMA LA4105P
Montevina Blade UMA LA4105P
Montevina Blade UMA LA4105P
KSO12 KSO3 KSO6 KSO8 KSO7 KSO4 KSO2 KSI0 KSO1 KSO5 KSI3 KSI2
KSO0 KSI5 KSI4 KSO9 KSI6 KSI7 KSI1
5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
ACES_85201-2405
ACES_85201-2405
CONN@
CONN@
32 45Saturday, July 18, 2009
32 45Saturday, July 18, 2009
32 45Saturday, July 18, 2009
of
of
of
1.0
1.0
1.0
A
B
C
D
E
System LED
CAPS_LED#<32>
1 1
HDDHALT_LED#<22>
SATA_LED#<21>
BAT_LED#<32>
White
AMBER
ON/OFFBTN_LED#
White
D50
D50
HT-F196BP5_WHITE
HT-F196BP5_WHITE
White
D52
D52
HT-F196BP5_WHITE
HT-F196BP5_WHITE
D53
D53
White
White
Amber
Amber
QSMF-C16E_AMBER-WHITE
QSMF-C16E_AMBER-WHITE
White
D17
D17
HT-F196BP5_WHITE
HT-F196BP5_WHITE
21
21
21
43
21
R1095
R1095
1 2
470_0402_5%
470_0402_5%
R1097
R1097
1 2
200_0402_5%
200_0402_5%
R1098
R1098 200_0402_5%
200_0402_5%
1 2
GS@
GS@
1 2
R728
R728 200_0402_5%
200_0402_5%
R980
R980
1 2
200_0402_5%
200_0402_5%
+5VS_LED
+5VALW_LED
+5VS_LED
+3VS
+5VALW_LED
Cap lock
Battery Charge LED
HDD LED
System Power LED
21
+3VL_CAP+3VL
4
5
VOUT
@C317
@
0.33U_0603_10V7K
0.33U_0603_10V7K
+5VL
1
@ C316
@
1U_0603_10V4Z
1U_0603_10V4Z
2
C316
@
@
R253
R253
1 2
10K_0603_1%
10K_0603_1%
APL5151-33BC-TRL SOT23 5P 3.3V
APL5151-33BC-TRL SOT23 5P 3.3V
PJP703
PJP703 PAD-OPEN 2x2m
PAD-OPEN 2x2m
U7
@U7
@
SHDN#3BP
2
GND
1
VIN
#PV reserve LDO for capacitor sensor board
03/28 PV2 Delete LDO
C317
1 2
02/22 Add C on +3VL
+5VS_LED
2 2
WL_BLUE_BTN<32>
ON/OFFBTN_LED#<32>
ENE
Cypress
3 3
Capacitor
02/13 Add ON/OFFBTN_LED# and ON/OFFBTN
Sensor Conn
on Cap board connector for OPP
R151 0_0402_5%OPP@ R151 0_0402_5%OPP@ R169 0_0402_5%OPP@ R169 0_0402_5%OPP@
R237 0_0402_5%OPP@ R237 0_0402_5%OPP@ R729 0_0402_5%Main@ R729 0_0402_5%Main@ R56 33_0402_5%Main@ R56 33_0402_5%Main@ R149 33_0402_5%Main@ R149 33_0402_5%Main@
1 2 1 2
12
1 2 1 2
1 2 1 2 1 2 1 2
SMB_EC_CK1<31,32,37>
ESB_CLK<32> ESB_DAT<32>
NUM_LED#<32> SMB_EC_DA1<31,32,37> ON/OFFBTN<32>
I2C_INT<32>
ESB_CLK
01/03 EMI request
WL_BLUE_LED#
SMB_EC_CK1 ESB_CLK ESB_DAT
SMB_EC_DA1
R234
R234
33_0402_5%
33_0402_5%
Main@
Main@
R730 0_0402_5%
R730 0_0402_5% R238 0_0402_5%OPP@ R238 0_0402_5%OPP@
C310
C310
12
15P_0402_50V8J
15P_0402_50V8J
@
@
C323
C323
15P_0402_50V8J
15P_0402_50V8J
02/25 EMI request
ON/OFF Button Connector
+3VL_CAP +5VALW_LED
12
12
R51
R51
R53
R53
0_0805_5%
0_0805_5%
0_0805_5%
0_0805_5%
Main@
Main@
OPP@
OPP@
JP59
JP59
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
1
2
1
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
C313
C313
2
11
GND
12
GND
ACES_85201-1005N
ACES_85201-1005N
CONN@
CONN@
Keyboard backlight
04/29 MV1 Delete C322
+3VL
1
+
C322 22U_A_4VM
22U_A_4VM
2
1
@
@
C329
C329
2
15P_0402_50V8J
15P_0402_50V8J
03/13 PV2 Add EMI solution
@+C322
@
I2C_INTNUM_LED#
1
C326
C326
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
T/P Board (Inculde T/P_ON/OFF)
+3VL_CAP
TouchPAD ON/OFF LED
PA PR
+5VS
12
AMBER White
R718
R718
10K_0402_5%
10K_0402_5%
2N7002_SOT23-3
2N7002_SOT23-3
SYSON<9,26,32,36,41>
+5VS_LED
12
12
R610
200_0402_5%
200_0402_5%
D12
D12
PA@
PA@
R610
Amber
Amber
QSMF-C16E_AMBER-WHITE
QSMF-C16E_AMBER-WHITE
2
G
G
Q4
Q4
10K_0402_5%
10K_0402_5%
SYSON
R609
R609 200_0402_5%
200_0402_5%
21
43
White
White
TP_LED#
13
D
D
S
S
On (TP_LED#=L)-> White Off (TP_LED#=H)-> Amber
+5VALW +5V_TP
R691 0_0603_5%
R691 0_0603_5%
1 2
S
S
G
G
12
13
D
D
Q24
@
Q24
@
2N7002_SOT23-3
2N7002_SOT23-3
S
S
2
R612
@R612
@
2
G
G
AMBER White
SI2301BDS-T1-E3_SOT23-3
SI2301BDS-T1-E3_SOT23-3
Mini card LED
21
43
Amber
Amber
D21
D21
PR@
PR@
QSMF-C16E_AMBER-WHITE
QSMF-C16E_AMBER-WHITE
TP_LED# <32>
T/P Board Conn
D
D
13
Q23
@
Q23
@
5 6
White
White
02/13 Add PR TP LED
JP23
JP23
1 2 3
G1
4
G2
ACES_85201-04051
ACES_85201-04051
CONN@
CONN@
Conn
+5VALW_LED
JP10
JP10
1
ON/OFFBTN ON/OFFBTN_LED#
1
2
2
3
3
G1
4
4
G2
ACES_85201-04051
ACES_85201-04051
CONN@
CONN@
5 6
Lid Switch
4 4
Connector
LID_SW#<32>
+3VL
1
1
C246
C246
2
2
C243
C243
10P_0402_25V8K
10P_0402_25V8K
0.1U_0402_16V4Z
0.1U_0402_16V4Z
A
JP11
JP11
1
1
2
2
3
3
G1
4
4
G2
ACES_85201-04051
ACES_85201-04051
CONN@
CONN@
5 6
+5VS_LED
01/03 Keyboard backlight reserve a 0805 size resistor
ESB_DAT
02/20 EMI
01/03 Change Lid switch connector type
request 02/18 Support Hall sensor module, move
C243、、、C246 to M/B
03/18 Delete Lid switch pin 1
04/29 MV1 Change LID switch power to +3VL
@R205
@
1 2
0_0805_5%
0_0805_5%
R252
@R252
@
33_0402_5%
33_0402_5%
B
R205
@
@
12
C260
C260
12
15P_0402_50V8J
15P_0402_50V8J
JP9
JP9
1
1
2
2
3
3
G1
4
4
G2
ACES_85201-04051
ACES_85201-04051
CONN@
CONN@
5 6
WL_LED#<26>
WW_LED#<26>
11/20 Reserve WW_LED function
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2007/08/28 2006/07/26
2007/08/28 2006/07/26
2007/08/28 2006/07/26
Deciphered Date
Deciphered Date
Deciphered Date
D24 CH751H-40PT_SOD323-2D24 CH751H-40PT_SOD323-2
21
21
D58 CH751H-40PT_SOD323-2D58 CH751H-40PT_SOD323-2
D
BT_LED<30>
100K_0402_5%
100K_0402_5%
R257
R257
1 2
02/20 PV change to doide
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
TP ON/OFF
+5V_TP
12
R611 10K_0402_5%
SW1
SW1 TJG-533-V-T/R_6P
TJG-533-V-T/R_6P
3
4
5
6
+5V_TP
1
C729
C729
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
1
TP_CLK
2
TP_DATA
3 4
C730
@C730
@
100P_0402_50V8J
100P_0402_50V8J
Q11
Q11
2N7002_SOT23-3
2N7002_SOT23-3
R716
R716
0_0402_5%
0_0402_5%
13
D
D
2
G
G
12
S
S
WL_LED
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
KBD, ON/OFF, SW, CIR
KBD, ON/OFF, SW, CIR
KBD, ON/OFF, SW, CIR
Montevina Blade UMA LA4105P
Montevina Blade UMA LA4105P
Montevina Blade UMA LA4105P
10K_0402_5%
1
2
11/07 Change part number
TP_DATA TP_CLK
3
02/25 EMI request Add D28 and C729
1
1
C731
@C731
@
100P_0402_50V8J
100P_0402_50V8J
2
2
+3VS
12
R193
R193 10K_0402_5%
10K_0402_5%
E
@R611
@
TP_BTN# <32>
2
D28
D28 PSOT24C_SOT23-3
PSOT24C_SOT23-3
1
EMI request
TP_CLK <32> TP_DATA <32>
WL_BLUE_LED# <32>
of
33 45Saturday, July 18, 2009
of
33 45Saturday, July 18, 2009
of
33 45Saturday, July 18, 2009
1.0
1.0
1.0
DOCK_PWR_ON Spec 0V = Notebook S4/S5, Dock off
2.5V = Notebook S3, Dock on 4V = Notebook S0, Dock on
R974 1K_0402_5%
R974 1K_0402_5%
+5VS
R975 1K_0402_5%
R975 1K_0402_5%
+3VALW
SYSON#<36,42>
1 2
1 2
2N7002_SOT23-3
2N7002_SOT23-3
DOCK@
DOCK@
Q58
Q58
DOCK@
DOCK@
DOCK@
DOCK@
2
G
G
Dock PRESENT
CONA#<32>
R979
DOCK_PRESENT
R979
1 2
22_0402_5%
22_0402_5%
DOCK@
DOCK@
13
D
D
S
S
12
12
R976
R976 10K_0402_5%
10K_0402_5%
DOCK@
DOCK@
R623
R623 2K_0402_5%
2K_0402_5%
DOCK@
DOCK@
D57
D57
2
3
DAN202U_SC70
DAN202U_SC70
DOCK@
DOCK@
11/12 Change to +3VL
+3VL
1 2
13
2
G
G
1
R621
R621 10K_0402_5%
10K_0402_5%
D
D
Q27
Q27 2N7002_SOT23-3
2N7002_SOT23-3
S
S
DOCK@
DOCK@
DOCK_PWRON
Atlas/ Saturn Dock
RED<18> GREEN<18> BLUE<18> D_DDCDATA<18> D_DDCCLK<18> D_HSYNC<18> D_VSYNC<18>
USB20_N3<22> USB20_P3<22>
RJ45_MIDI1-<25> RJ45_MIDI1+<25> RJ45_MIDI0-<25> RJ45_MIDI0+<25>
B+
PJP3
PJP3
PAD-OPEN 2x2m
PAD-OPEN 2x2m
RED GREEN BLUE D_DDCDATA D_DDCCLK D_HSYNC D_VSYNC USB20_N3 USB20_P3
12/18 Correct GND
RJ45_MIDI1­RJ45_MIDI1+ RJ45_MIDI0­RJ45_MIDI0+
+V_BATTERY
21
MIC_Dock
DOCK_MIC_R<28>
DOCK_MIC_L<28>
38 40 34 36 30 32 26 28 22 24 18 20 14 16 10 12
6 8 2 4
45 46
Need 600 Ohm 500 mA
L36
DOCK@L36
DOCK@
FBM-11-160808-601-T_0603
FBM-11-160808-601-T_0603
1 2
1 2
L37
DOCK@L37
DOCK@
FBM-11-160808-601-T_0603
FBM-11-160808-601-T_0603
220P_0402_50V7K
220P_0402_50V7K
+3VS
JDOCK1
JDOCK1
CRT_Red CRT_Green CRT_Blue DDC_DATA DDC_Clock Hsync Vsync USB­USB+ Digital gnd MDI3­MDI3+ MD2I­MDI2+ MDI1­MDI1+ MDI0­MDI0+ Battery out Battery out
GND GND
CONN@
CONN@
C754
C754
DOCK@
DOCK@
GNDA GNDA
Digital gnd
TV Luma
TV chroma
TV composite
TV ground
CIR input
PWR_ON
Mute_LED
Sleep Botton
Jack Detect
VOL_up
VOL_down
SPDIF Audio Output gnd Right headphone
Left headphone
Mic_Right
Mic_Left
Mic gnd
Dock_present
FOX_QL1122L-H212AR-7F
FOX_QL1122L-H212AR-7F
DOCK_MIC_R_C
DOCK_MIC_L_C
1
1
C755
C755 220P_0402_50V7K
220P_0402_50V7K
2
2
DOCK@
DOCK@
GND GND GND GND
39 37 35 33 31 29 27 25 23 21 19 17 15 13 11 9 7 5 3 1
41 42 43 44
12/18 Correct GND
11/07 Delete TVout function from Docking
VGA_GND CIR_IN DOCK_PWRON D_MUTE_LED D_DOCK_SLP_BTN# JACK_DET# R_VOL_UP# R_VOL_DWN# SPDIFO_L AUDIO_OGND DOCK_LOUT_R DOCK_LOUT_L DOCK_MIC_R_C DOCK_MIC_L_C AUDIO_IGND DOCK_PRESENT
CIR_IN <29,32>
R246 33_0402_5%R246 33_0402_5% R247 33_0402_5%R247 33_0402_5%
R617 200_0402_5%
R617 200_0402_5% R618 200_0402_5%
R618 200_0402_5%
GNDA
DOCK_LOUT_R <29> DOCK_LOUT_L <29>
GNDA
R620 2K_0402_5%R620 2K_0402_5%
1 2
+DOCKVIN
11/17 Reserve
C744
C744
DOCK@
DOCK@
1 2 1 2
1 2 1 2
DOCK@
DOCK@ DOCK@
DOCK@
C305
C305
@
@
C306
C306
@
@
1
2
1000P_0402_50V7K
1000P_0402_50V7K
1 2
1000P_0402_50V7K
1000P_0402_50V7K
1 2
1000P_0402_50V7K
1000P_0402_50V7K
1
2
1000P_0402_50V7K
1000P_0402_50V7K
C745
C745
DOCK@
DOCK@
02/13 Add 33 ohm for isolate
MUTE_LED <32>
DOCK_SLP_BTN# <32>
JACK_DET# <28,29>
DOCK_VOL_UP# <32> DOCK_VOL_DWN# <32>
GNDA
C740
C740
DOCK@
DOCK@
11/17 Recommend
+DOCKVIN
1
C734
C734 1000P_0402_50V7K
1000P_0402_50V7K
2
DOCK@
DOCK@
1
2
0.01U_0402_16V7K
0.01U_0402_16V7K
GNDA GNDA
DOCK_LOUT_RR_VOL_UP#
DOCK_LOUT_LR_VOL_DWN#
1
C741
C741
2
DOCK@
DOCK@
0.01U_0402_16V7K
0.01U_0402_16V7K
DOCK_MIC_L_C
R632
R632
1 2
10K_0402_5%
10K_0402_5%
DOCK@
DOCK@
47K_0402_5%
47K_0402_5%
10K_0402_5%
10K_0402_5%
MMBT3904_NL_SOT23-3
MMBT3904_NL_SOT23-3
R633
R633
1 2
DOCK@
DOCK@
13
D
D
Q29
Q29 2N7002_SOT23-3
2N7002_SOT23-3
DOCK@
DOCK@
S
S
SENSE_B# <28>
Deciphered Date
Deciphered Date
Deciphered Date
R625
R625 10K_0402_5%
R626
R626
DOCK@
DOCK@
1 2
Q32
Q32
C
C
DOCK@
DOCK@
2
B
B
E
E
2
3 1
C757
C757
1
1U_0603_10V6K
1U_0603_10V6K
DOCK@
DOCK@
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
10K_0402_5%
DOCK@
DOCK@
1 2
C
C
2
B
B
E
E
3 1
Q30
Q30 MMBT3904_NL_SOT23-3
MMBT3904_NL_SOT23-3
DOCK@
DOCK@
2
G
G
2007/08/28 2006/03/10
2007/08/28 2006/03/10
2007/08/28 2006/03/10
Q55
@
Q55
@
2N7002_SOT23-3
2N7002_SOT23-3
SPDIFO_L
+1.5VS_HDA
1 2 13
D
D
S
S
R722 33_0402_5%
33_0402_5%
2
G
G
R723
R723
DOCK@
DOCK@
1 2
0_0603_5%
0_0603_5%
@R722
@
C64
C64
DOCK@
DOCK@
1 2
0.1U_0402_16V7K
0.1U_0402_16V7K
12
1
C819
C819
220P_0402_25V8J
220P_0402_25V8J
DOCK@
DOCK@
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
Date: Sheet
R978
R978 110_0402_5%
110_0402_5%
2
DOCK@
DOCK@
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
DOCK CONN.
DOCK CONN.
DOCK CONN.
Montevina Blade UMA LA4105P
Montevina Blade UMA LA4105P
Montevina Blade UMA LA4105P
R977
R977
DOCK@
DOCK@
1 2
220_0402_5%
220_0402_5%
SPDIF_OUT <28>
34 45Saturday, July 18, 2009
34 45Saturday, July 18, 2009
34 45Saturday, July 18, 2009
1.0
1.0
1.0
of
of
of
5
4
3
2
1
+3VS_LS +3VS_LS
36
35
34
33
32
31
30
29
28
27
26
25
0.5P_0402_50V8B
0.5P_0402_50V8B
0.5P_0402_50V8B
0.5P_0402_50V8B
TMDS_B_DATA1 <11> TMDS_B_DATA1# <11>
TMDS_B_DATA0 <11> TMDS_B_DATA0# <11>
11/07 Enable DDC_EN pin
+3VS_LS
HDMI_DETECT
HDMIDAT
HDMICLK
@C770
@
@C772
@
R651 0_0402_5%R651 0_0402_5%
R652 0_0402_5%@R652 0_0402_5%@
R654 0_0402_5% @ R654 0_0402_5% @
R655 0_0402_5%R655 0_0402_5%
C770
C772
HDMI_TX_0-
HDMI_TX_0+HDMICLK+
HDMI_TX_1-
HDMI_TX_1+
12
12
12
12
+3VS_LS
+3VS_LS+3VS_LS
TMDS_B_DATA2#<11>
1 2
1 2
R653
R653
TMDS_B_DATA2<11>
TMDS_B_CLK#<11> TMDS_B_CLK<11>
+3VS_LS
475_0402_1%
475_0402_1%
12
TMDS_B_HPD
+3VS_LS
C769
@C769
@
0.5P_0402_50V8B
0.5P_0402_50V8B
C771
@C771
@
0.5P_0402_50V8B
0.5P_0402_50V8B
U43
U43
1
2
3
4
5
6
7
8
9
10
11
12
R656
@R656
@
1 2
68_0402_5%
68_0402_5%
R658
@R658
@
1 2
68_0402_5%
68_0402_5%
48
47
46
45
44
43
IN_D4-
IN_D4+
GND
VCC3V
PC0
FUNCTION1
PC1
FUCNTION2
GND
ANALOG1(REXT)
HPD_SOURCE
SDA_SOURCE
SCL_SOURCE
ANALOG2
VCC3V
GND
OUT_D4+13OUT_D4-14VCC3V15OUT_D3+16OUT_D3-17GND18OUT_D2+19OUT_D2-20VCC3V21OUT_D1+22OUT_D1-23GND
GND
IN_D3-
VCC3V
IN_D3+
42
41
40
39
38
37
IN_D2-
IN_D2+
+3VS_LS+3VS_LS
GND
IN_D1-
VCC3V
IN_D1+
GND
FUNCTION4
FUNCTION3
VCC3V
DDC_EN
GND
HPD_SINK
SDA_SINK
SCL_SINK
GND
VCC3V
OE*
24
CH7318A-BF-TR_QFN48_7X7
CH7318A-BF-TR_QFN48_7X7
R657
@R657
@
1 2
68_0402_5%
68_0402_5%
R659
@R659
@
1 2
68_0402_5%
68_0402_5%
EQUALIZATION SETTING: [PC1,PC0]=00,8dB [PC1,PC0]=01,4dB (Recommanded) [PC1,PC0]=10,12dB [PC1,PC0]=11,0dB
D D
PV 02/20 follow datasheet
+3VS_LS
Follow Intel Feedback putting
2.2K ohm
+3VS_LS
12
R742
@R742
@
20K_0402_5%
12
2
G
G
20K_0402_5%
TMDS_B_HPD#
13
D
D
@
@
S
S
2N7002_SOT23-3
2N7002_SOT23-3
C C
TMDS_B_HPD
R743
@R743
@
20K_0402_5%
20K_0402_5%
11/07 correct TMDS_B_HPD# connection to North
2.2K_0402_5%
2.2K_0402_5%
HDMIDAT_NB<9>
HDMICLK_NB<9>
TMDS_B_HPD TMDS_B_HPD#
Q28
Q28
@
@
Follow Vendor Feedback
R649
R649
R9
R9
1 2
0_0402_5%
0_0402_5%
12
R744
R744
7.5K_0402_1%
7.5K_0402_1%
12
12
R650
R650
2.2K_0402_5%
2.2K_0402_5%
TMDS_B_HPD# <11>
+3VS_LS
R255 4.7K_0402_5%R255 4.7K_0402_5%
R256 4.7K_0402_5%@R256 4.7K_0402_5%@
HDMICLK-
HDMI_TX_2+
HDMI_TX_2-
bridge
R648
R648
1 2
0_0603_5%
0_0603_5%
1
2
C320
C320
C321
C321
2
1
0.1U_0402_10V6K
0.1U_0402_10V6K
0.01U_0402_16V7K
0.01U_0402_16V7K
PV 02/20 follow datasheet
02/20 PV EMI request add C273、、、C314
+3VS_LS+3VS
1
1
C319
C319
2
2
C318
C318
0.1U_0402_10V6K
0.1U_0402_10V6K
10U_0805_6.3V6M
10U_0805_6.3V6M
R1121 0_0402_5%R1121 0_0402_5%
1 2
L38
HDMICLK-
B B
A A
HDMICLK+
HDMI_TX_0-
HDMI_TX_0+
HDMI_TX_1-
HDMI_TX_1+
HDMI_TX_2-
HDMI_TX_2+
L38
1
1
4
4
R1122 0_0402_5%R1122 0_0402_5%
1 2
R1123 0_0402_5%R1123 0_0402_5%
1 2
L39
L39
1
1
4
4
R1124 0_0402_5%R1124 0_0402_5%
1 2
R1125 0_0402_5%R1125 0_0402_5%
1 2
L41
L41
1
1
4
4
R1126 0_0402_5%R1126 0_0402_5%
1 2
R1127 0_0402_5%R1127 0_0402_5%
1 2
L42
L42
1
1
4
4
R1128 0_0402_5%R1128 0_0402_5%
1 2
2
2
WCM-2012-670T_0805
WCM-2012-670T_0805
3
3
2
2
WCM-2012-670T_0805
WCM-2012-670T_0805
3
3
2
2
WCM-2012-670T_0805
WCM-2012-670T_0805
3
3
2
2
WCM-2012-670T_0805
WCM-2012-670T_0805
3
3
HDMI_CLK-
HDMI_CLK+
HDMI_TX0-
HDMI_TX0+
HDMI_TX1-
HDMI_TX1+
HDMI_TX2-
HDMI_TX2+
01/03 Reserver 0 ohm co lay with common choke
5
4
HDMI Connector
Vendor suggests 4K
11/07 Follow recommend change to 3.9K
R665
2 1
R665
1 2
1K_0402_1%
1K_0402_1%
12
R666
R666 10K_0402_1%
10K_0402_1%
Deciphered Date
Deciphered Date
Deciphered Date
HDMI_DETECT
D32
D32
SKS10-04AT_TSMA
SKS10-04AT_TSMA
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2007/08/28 2006/03/10
2007/08/28 2006/03/10
2007/08/28 2006/03/10
PU
L40
L40
1 2
FBML10160808121LMT_0603
FBML10160808121LMT_0603
C774
C774
330P_0402_50V7K
330P_0402_50V7K
2
1
2
HDMIDAT HDMICLK
HDMI_CLK­HDMI_CLK+ HDMI_TX0­HDMI_TX0+ HDMI_TX1­HDMI_TX1+ HDMI_TX2­HDMI_TX2+
+5VS
C273
C273
@
@
1 2
21
2200P_0402_25V7K
2200P_0402_25V7K
RB411D T146 _SOT23-3
RB411D T146 _SOT23-3 D31
D31
+5VS_HDMI
1
0.1U_0402_16V4Z
12
12
R49
R49
R50
R50
3.9K_0402_1%
3.9K_0402_1%
3.9K_0402_1%
3.9K_0402_1%
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Montevina Blade UMA LA4105P
Montevina Blade UMA LA4105P
Montevina Blade UMA LA4105P
Date: Sheet
Date: Sheet
Date: Sheet
0.1U_0402_16V4Z C773
C773
2
JHDMI1
JHDMI1
18
+5V
16
SDA
15
SCL
19
HP_DET
12
CK-
10
CK+
9
D0-
7
D0+
6
D1-
4
D1+
3
D2-
1
D2+
SUYIN_100042MR019S153ZL
SUYIN_100042MR019S153ZL
CONN@
CONN@
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
HDMI LS & Conn.
HDMI LS & Conn.
HDMI LS & Conn.
Reserved
GND GND GND GND GND GND GND GND
DDC/CEC_GND
1
CEC
1
2
13 14
2 5 8 11 20 21 22 23 17
C314
@C314
@
2200P_0402_25V7K
2200P_0402_25V7K
35 45Saturday, July 18, 2009
35 45Saturday, July 18, 2009
35 45Saturday, July 18, 2009
of
of
of
1.0
1.0
1.0
5
4
3
2
1
10U_0805_10V4Z
10U_0805_10V4Z
DIM LED
DIM_LED<32>
R637
R637
10K_0402_5%
10K_0402_5%
2
G
G
+5VALW +5VALW_LEDB+
12
13
D
D
S
S
Q33
Q33
SI2301BDS-T1-E3_SOT23-3
SI2301BDS-T1-E3_SOT23-3
S
S
D
D
13
G
G
2
DIM_LED#
Q35
Q35 2N7002_SOT23-3
2N7002_SOT23-3
SYSON#<34,42> SUSP <42>
SYSON<9,26,32,33,41>
1
C758
C758
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
100K_0402_5%
100K_0402_5%
SYSON#
Q13A
Q13A
R639
R639
2
+3VL
Q15
Q15
SI2301BDS-T1-E3_SOT23-3
SI2301BDS-T1-E3_SOT23-3
S
S
G
G
DIM_LED#
+3VL
12
12
R640
R640
100K_0402_5%
100K_0402_5%
SUSP
61
3
Q13B
Q13B
SUSP#
2N7002DW-7-F_SOT363-6
2N7002DW-7-F_SOT363-6
5
4
2N7002DW-7-F_SOT363-6
2N7002DW-7-F_SOT363-6
2
+5VS_LED+5VS
D
D
13
1
2
SUSP# <26,28,32,38,40>
C294
C294
0.1U_0402_16V4Z
0.1U_0402_16V4Z
+5VALW to +5VS Transfer +3VALW to +3VS Transfer
U32
U32
8
D
7
D
6
D
5
D
AO4466_SO8
AO4466_SO8
10U_0805_10V4Z
10U_0805_10V4Z
RUNON
61
12
1
2
Q34A
Q34A
C760
C760
1
2
2
D D
12
R223
R223
330K_0402_5%
330K_0402_5%
SUSP
2N7002DW-7-F_SOT363-6
2N7002DW-7-F_SOT363-6
+5VS+5VALW +3VS+3VALWB+
1
S
2
S
3
S
4
G
C761
C761
R224
R224
470_0402_5%
470_0402_5%
C65
C65
4700P_0402_25V7K
4700P_0402_25V7K
1
2
1
C762
C762
2
10U_0805_10V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
10U_0805_10V4Z
01/03 Sparate+5VS and +3VS power timing
12
R636
R636
330K_0402_5%
330K_0402_5%
SUSP
5
Q34B
Q34B
2N7002DW-7-F_SOT363-6
2N7002DW-7-F_SOT363-6
1
C759
C759
10U_0805_10V4Z
10U_0805_10V4Z
2
RUNON_3VS
3
4
+1.5V to +1.5VS Transfer
B+
2
G
G
1
C766
C766
10U_0805_10V4Z
10U_0805_10V4Z
2
RUNON_1.5VS
13
D
D
Q44
Q44
S
S
2N7002_SOT23-3
2N7002_SOT23-3
C C
12
R647
R647
330K_0402_5%
330K_0402_5%
SUSP
U34
U34
8
D
7
D
6
D
5
D
AO4466_SO8
AO4466_SO8
12
R1113
R1113 1K_0402_5%
1K_0402_5%
1
C1406
C1406
0.1U_0402_25V4K
0.1U_0402_25V4K
2
+1.5VS+1.5V
1
S
2
S
3
S
4
1
G
2
2
C1405
C1405
1
C1404
C1404
0.1U_0402_16V4Z
0.1U_0402_16V4Z
10U_0805_10V4Z
10U_0805_10V4Z
SLP_S4#<22,32>
1 2
R1115
@ R1115
@
0_0201_5%
0_0201_5%
R1116
R1116 0_0402_5%
0_0402_5%
12
VOUT=1.25(1+R912/R913)
VOUT=1.25(1+100k/215k)=1.83V
U33
U33
8
S
D
7
S
D
6
S
D
5
G
D
AO4466_SO8
AO4466_SO8
12
R638
R638
470_0402_5%
470_0402_5%
1
C765
C765
0.01U_0402_16V7K
0.01U_0402_16V7K
2
U47
U47
1
IN
OUT
2
GND
3
SHDN
BYP
G916-390T1UF_SOT23-5
G916-390T1UF_SOT23-5
1 2 3 4
1
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
5
4
10U_0805_10V4Z
10U_0805_10V4Z
1
C764
C764
C763
C763
2
12
R1114
R1114
47K_0402_1%
47K_0402_1%
12
R1117
R1117
100K_0402_1%
100K_0402_1%
+1.8V+3VALW
1
2
C1407
C1407
H9
H10
H2
H1
1
HOLEAH1HOLEA
1
H15
H15 HOLEA
HOLEA
1
FM1FM1
Discharge circuit
+VCCP +0.75V
12
R645
R645
470_0402_5%
470_0402_5%
3
Q9B
Q9B
5
4
2N7002DW-7-F_SOT363-6
2N7002DW-7-F_SOT363-6
470_0402_5%
470_0402_5%
Q9A
Q9A
SUSP
2
R644
R644
+1.5VS
4
12
61
2N7002DW-7-F_SOT363-6
2N7002DW-7-F_SOT363-6
B B
A A
5
+5VS +3VS
12
R641
R641
470_0402_5%
470_0402_5%
61
Q6A
Q6A
SUSP SYSON#SUSP
2
SUSP SUSP
2N7002DW-7-F_SOT363-6
2N7002DW-7-F_SOT363-6
R642
R642
470_0402_5%
470_0402_5%
Q6B
Q6B
5
12
3
4
2N7002DW-7-F_SOT363-6
2N7002DW-7-F_SOT363-6
+1.5V
12
R643
R643
470_0402_5%
470_0402_5%
61
Q12A
Q12A
2
2N7002DW-7-F_SOT363-6
2N7002DW-7-F_SOT363-6
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
12
R646
R646
470_0402_5%
470_0402_5%
3
Q12B
Q12B
5
4
2N7002DW-7-F_SOT363-6
2N7002DW-7-F_SOT363-6
2007/08/28 2006/07/26
2007/08/28 2006/07/26
2007/08/28 2006/07/26
Deciphered Date
Deciphered Date
Deciphered Date
2
H3
HOLEAH2HOLEA
HOLEAH3HOLEA
1
1
H16
H16
H17
H17
HOLEA
HOLEA
HOLEA
HOLEA
1
1
FM3FM3
FM2FM2
1
1
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
H5
H4
HOLEAH5HOLEA
HOLEAH4HOLEA
1
1
H19
H19
H18
H18
HOLEC
HOLEC
HOLEA
HOLEA
1
1
FM4FM4
1
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
H7 HOLEAH7HOLEA
1
H11
H11 HOLEA
HOLEA
1
H8 HOLEAH8HOLEA
1
1
H6 HOLEAH6HOLEA
1
H20
H20 HOLEC
HOLEC
1
DC/DC Interface
DC/DC Interface
DC/DC Interface
Montevina Blade UMA LA4105P
Montevina Blade UMA LA4105P
Montevina Blade UMA LA4105P
HOLEAH9HOLEA
1
36 45Saturday, July 18, 2009
36 45Saturday, July 18, 2009
36 45Saturday, July 18, 2009
of
of
of
H10 HOLEA
HOLEA
1
1.0
1.0
1.0
A
B
C
D
+3VALW
PQ3
PQ3 TP0610K-T1-E3_SOT23-3
TP0610K-T1-E3_SOT23-3
1 2
100K_0402_5%
1 1
1 3
PR8
PR8 2K_0402_5%
2K_0402_5%
ACES_88334-057N
ACES_88334-057N
PJP1
PJP1
2 2
1 2
ADP_SIGNAL
5
5
4
4
3
3
2
2
1
1
ADPINADPIN
PD1
PD1
100K_0402_5%
2
1 2
PR3
PR3 10K_0402_5%
10K_0402_5%
2
3
@PJSOT24C_SOT23-3
@PJSOT24C_SOT23-3
1
PR9
PR9
+3VL
12
100P_0402_50V8J
100P_0402_50V8J
PC2
PC2
connect to KBC pin97
AC_LED# <32>
12
PR2
PR2 10K_0402_5%
10K_0402_5%
12
RLZ3.6B_LL34
RLZ3.6B_LL34
PL1
PL1
SMB3025500YA_2P
SMB3025500YA_2P
1 2
12
PC3
PC3 1000P_0402_50V7K
1000P_0402_50V7K
PD4
PD4
12
12
PC4
PC4
100P_0402_50V8J
100P_0402_50V8J
ADP_ID <32>
PC12
PC12
@1000P_0402_50V7K
@1000P_0402_50V7K
VIN +DOCKVIN
PL2
PL2
SMB3025500YA_2P
PC5
PC5
12
1000P_0402_50V7K
1000P_0402_50V7K
SMB3025500YA_2P
12
BATT
12
+5VALW
PR1
PR1
340K_0402_1%
340K_0402_1%
12
PR4
PR4
499K_0402_1%
499K_0402_1%
12
PC6
PC6
0.01U_0402_25V7K
0.01U_0402_25V7K
12
PR6
PR6
105K_0402_1%
105K_0402_1%
12
PC1
PC1
0.01U_0402_25V7K
0.01U_0402_25V7K
3
2
PU1A
PU1A
LM358ADT_SO8
LM358ADT_SO8
8
P
+
1
0
-
G
4
PR5
PR5
10K_0402_5%
10K_0402_5%
12
BATT_OVP <32>
VMB
PL3
PL3
HCB2012KF-121T50_0805
PJP2
PJP2
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
9
GND
10
GND
SUYIN_200275MR008GXOLZR
SUYIN_200275MR008GXOLZR
3 3
PR16
PR16
6.49K_0402_1%
6.49K_0402_1%
1 2
12
PR17
PR17 1K_0402_5%
1K_0402_5%
4 4
EC_SMD EC_SMC
12
PR13
PR13
100_0402_5%
100_0402_5%
BAT_ID <38>
+3VL
A
PD2
PD2 @SM05_SOT23
@SM05_SOT23
3
2
12
PR14
PR14 100_0402_5%
100_0402_5%
BATT_TEMP <32>
1
2
3
1
PD3
PD3 @SM24.TC_SOT23-3
@SM24.TC_SOT23-3
SMB_EC_DA1
SMB_EC_CK1
HCB2012KF-121T50_0805
1 2
PL4
PL4
HCB2012KF-121T50_0805
HCB2012KF-121T50_0805
1 2
12
PC8
PC8 1000P_0402_50V7K
1000P_0402_50V7K
12
B
BATT
PH1 under CPU botten side :
CPU thermal protection at 90 +-3 degree C
PC9
PC9
0.01U_0402_50V4Z
0.01U_0402_50V4Z
+5VS
CPU
12
PH1
PH1
10K_TH11-3H103FT_0603_1%
10K_TH11-3H103FT_0603_1%
PR10
SMB_EC_DA1 <31,32,33>
SMB_EC_CK1 <31,32,33>
12
PC10
PC10
0.22U_0603_10V7K
0.22U_0603_10V7K
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2007/05/29 2008/05/29
2007/05/29 2008/05/29
2007/05/29 2008/05/29
+5VALW
12
PR12
PR12
2.49K_0402_1%
2.49K_0402_1%
PR10
200K_0402_1%
200K_0402_1%
1 2
1 2
PR11
PR11
150K_0402_1%
150K_0402_1%
PR15
PR15
150K_0402_1%
150K_0402_1%
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
C
12
PR7
PR7
604K_0402_1%
604K_0402_1%
1 2
8
5
+
6
-
12
4
PC11
PC11 1000P_0402_50V7K
1000P_0402_50V7K
P
G
LM358ADT_SO8
LM358ADT_SO8
0
PU1B
PU1B
EN0_TRIP <39>
13
D
D
PQ1
7
2
G
G
PQ1 SSM3K7002FU_SC70-3
SSM3K7002FU_SC70-3
S
S
ENTRIP2 <39>
13
D
D
PQ2
2
G
G
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
Compal Electronics, Inc.
DC Connector/CPU_OTP
DC Connector/CPU_OTP
DC Connector/CPU_OTP
PQ2 @SSM3K7002FU_SC70-3
@SSM3K7002FU_SC70-3
S
S
Montevina Blade UMA LA4105P
Montevina Blade UMA LA4105P
Montevina Blade UMA LA4105P
D
37 45Saturday, July 18, 2009
37 45Saturday, July 18, 2009
37 45Saturday, July 18, 2009
1.0
1.0
1.0
of
of
of
A
VIN
PQ101
1 1
PR101
PR101
47K_0402_5%
47K_0402_5%
1 2
12
PC101
PR107
PR107 47K_0402_1%
47K_0402_1%
1 2
SSM3K7002FU_SC70-3
SSM3K7002FU_SC70-3
PQ107
PQ107
PC101
47P_0402_50V8J
47P_0402_50V8J
2
13
D
D
2
G
G
S
S
2
13
PQ105
PQ105 DTC115EUA_SC70-3
DTC115EUA_SC70-3
PQ101 SI4835DDY-T1-E3_SO8
SI4835DDY-T1-E3_SO8
8 7
5
PQ104
PQ104
DTA144EUA_SC70-3
DTA144EUA_SC70-3
1 3
PACIN_1 <39>
PQ109
PR111
PR111
3K_0402_1%
3K_0402_1%
PACIN
1 2
PD101
2 2
ACOFF#
PD101
1 2
1SS355_SOD323-2
1SS355_SOD323-2
2
G
G
PQ109
13
D
D
SSM3K7002FU_SC70-3
SSM3K7002FU_SC70-3
S
S
VCTRL<32>
4
1 2
1U_0603_10V6K
1U_0603_10V6K
1 2 36
12
PC106
PC106
0.1U_0603_25V7K
0.1U_0603_25V7K
PR114
PR114 @0_0402_5%
@0_0402_5%
PC117
PC117
P2
12
12
PR109
PR109 150K_0402_5%
150K_0402_5%
12
PR106
PR106
143K_0402_1%
143K_0402_1%
PQ103
PQ103
SI4459ADY
SI4459ADY
1 2 3 6
4
AC_SET<32>
200K_0402_5%
200K_0402_5%
SUSP#<26,28,32,36,40>
12
PR113
PR113
12
PR115
PR115 100K_0402_1%
100K_0402_1%
8 7
5
@0.01U_0402_16V7K
@0.01U_0402_16V7K
PC128
PC128
1 2
@180P_0402_50V8J
@180P_0402_50V8J
PC112
PC112
1 2
1U_0603_6.3V6M
1U_0603_6.3V6M
Charge Detector
ADP_I<32>
VIN
PD104
PD104 1SS355_SOD323-2
1SS355_SOD323-2
PR123
PR123
1 2
1M_0402_5%
3
2
VIN_1
12
8
+
-
4
1M_0402_5%
1 2
PR125
PR125 47_1206_5%
47_1206_5%
P
1
O
G
PU102A
PU102A LM393DG_SO8
LM393DG_SO8
12
PC125
PC125
0.1U_0603_25V7K
0.1U_0603_25V7K
+3VL
12
PR129
PR129
10K_0402_1%
10K_0402_1%
STD_ADP <32>
PR128
PR128
2
G
G
+3VL
12
10K_0402_5%
10K_0402_5%
13
D
D
S
S
FSTCHG<32>
CHGEN#
PQ112
PQ112 SSM3K7002FU_SC70-3
SSM3K7002FU_SC70-3
FSTCHG#
1 2
PR137
PR137 20K_0402_1%
20K_0402_1%
+3VL
PR132
PR132
100K_0402_5%
100K_0402_5%
2
G
G
ACDET
12
3 3
VIN
12
PR131
PR131 133K_0402_1%
133K_0402_1%
12
PR135
PR135 10K_0603_0.1%
10K_0603_0.1%
1.24VREF
4 4
PR104
PR104 0_0402_5%
0_0402_5%
1 2
PC107
PC107
PR110
PR110 0_0402_5%
0_0402_5%
1 2
BQ24740VREF
PR116
PR116
15K_0402_1%
15K_0402_1%
12
PC120
PC120
0.22U_0603_10V7K
0.22U_0603_10V7K
12
13
D
D
PQ113
PQ113 SSM3K7002FU_SC70-3
SSM3K7002FU_SC70-3
S
S
PR138
PR138
100K_0402_1%
100K_0402_1%
B
12
+3VL
12
PR118
PR118
10K_0402_5%
10K_0402_5%
1 2
0.1U_0402_10V7K
0.1U_0402_10V7K
470P_0402_50V7K
470P_0402_50V7K
ACSET
ACSET
12
PR140
PR140 100K_0402_5%
100K_0402_5%
8
IADSLP
9
AGND
10
VREF
11
VDAC
12
VADJ
13
EXTPWR
14
ISYNSET
PC121
PC121
100P_0402_50V8J
100P_0402_50V8J
PC123
PC123
PC133
PC133
ACDET
6
7
LPREF
ACSET
PU101
PU101 BQ24740RHDR_QFN28_5X5
BQ24740RHDR_QFN28_5X5
IADAPT
SRSET
15
16
IADAPT
12
12
5
ACDET
BAT
17
BATT
12
PC108
PC108
0.1U_0603_25V7K
0.1U_0603_25V7K
P4
PR102
PR102
0.012_2512_1%
0.012_2512_1%
1 2
1 2
PC102
PC102
1U_0603_6.3V6M
1U_0603_6.3V6M
12
3
4
ACP
LPMD
SRP
SRN
19
18
133K_0402_1%
133K_0402_1%
12
PR121
PR121 200K_0402_1%
200K_0402_1%
B+
1 2
12
PC109
PC109 @0.1U_0603_25V7K
@0.1U_0603_25V7K
CHGEN#
1
2
ACN
CHGEN
PVCC
BTST
HIDRV
REGN
LODRV
PGND
DPMDET
CELLS
21
20
SSM3K7002FU_SC70-3
SSM3K7002FU_SC70-3
PR120
PR120
12
PL101
PL101 HCB2012KF-121T50_0805
HCB2012KF-121T50_0805
29
TP
PH
28
BST_CHG
27
DH_CHG
26
LX_CHG
25
REGNVADJ
24
DL_CHG
23
22
PQ111
PQ111
IREF <32>
PC110
PC110 1U_0805_25V6K
1U_0805_25V6K
1 2
12
PC119
PC119
1U_0603_10V6K
1U_0603_10V6K
D
D
S
S
12
PC103
PC103
4.7U_0805_25V6-K
4.7U_0805_25V6-K
PR108
PR108 10_1206_5%
10_1206_5%
1 2
PD102
PD102
RLS4148_LL34-2
RLS4148_LL34-2
PR117
PR117
100K_0402_5%
100K_0402_5%
1 2
13
2
G
G
12
12
PC104
PC104
4.7U_0805_25V6-K
4.7U_0805_25V6-K
12
12
1000P_0402_50V7K
1000P_0402_50V7K
PC134
PC134
PC111
PC111
1 2
0.1U_0402_10V7K
0.1U_0402_10V7K
12
FDS6690AS_NL_SO8
FDS6690AS_NL_SO8
BQ24740VREF
12
PC124
PC124
PC105
PC105
4.7U_0805_25V6-K
4.7U_0805_25V6-K
PC129
PC129
PC130
PC130
12
470P_0402_50V7K
470P_0402_50V7K
PQ110
PQ110
47K_0402_5%
47K_0402_5% PR119
PR119
12
0.1U_0603_25V7K
0.1U_0603_25V7K
C
270P_0402_50V7K
270P_0402_50V7K
CHG_B+
578
3 6
578
3 6
CHG_B+
PQ108
PQ108 AO4466_SO8
AO4466_SO8
241
241
BAT_ID <37>
12
PC122
PC122
0.047U_0402_16V7K
0.047U_0402_16V7K
PL102
PL102 10U_LF919AS-100M-P3_4.5A_20%
10U_LF919AS-100M-P3_4.5A_20%
1 2
12
PR141
PR141
4.7_1206_5%
4.7_1206_5%
PC135
PC135 470P_0603_50V8J
470P_0603_50V8J
1 2
@0.1U_0603_25V7K
@0.1U_0603_25V7K
PR126
PR126
100K_0402_1%
100K_0402_1%
12
PC126
PC126
12
PC113
PC113
4.7U_0805_25V6-K
4.7U_0805_25V6-K
VIN
12
12
PR133
PR133 10K_0603_0.1%
10K_0603_0.1%
22P_0402_50V8J
22P_0402_50V8J
12
PC114
PC114
4.7U_0805_25V6-K
4.7U_0805_25V6-K
PR130
PR130
2.15K_0402_1%
2.15K_0402_1%
1 2
PC127
PC127
PQ102
PQ102 FDS6675BZ_SO8
FDS6675BZ_SO8
1 2 3 6
PR112
PR112
0.015_1206_1%
0.015_1206_1%
1 2
1 2
PC118
PC118
0.1U_0402_10V7K
0.1U_0402_10V7K
12
4
PR122
PR122 681K_0402_1%
681K_0402_1%
1 2
5
+
6
-
8 7
5
ACOFF#
BATT
12
12
PC115
PC115
4.7U_0805_25V6-K
4.7U_0805_25V6-K
8
PU102B
PU102B
P
7
O
G
LM393DG_SO8
LM393DG_SO8
4
RLZ4.3B_LL34
RLZ4.3B_LL34
PR136
PR136
60.4K_0402_1%
60.4K_0402_1%
1 2
4
REF
5
ANODE
LMV431ACM5X_SOT23-5
LMV431ACM5X_SOT23-5
PC116
PC116
4.7U_0805_25V6-K
4.7U_0805_25V6-K
PD103
PD103
CATHODE
12
VIN_1
PU104
PU104
NC
NC
12
BATT
PC136
PC136
VIN
D
PC132
PC132
@1000P_0402_50V7K
@1000P_0402_50V7K
12
PC131
PC131
4.7U_0805_25V6-K
4.7U_0805_25V6-K
12
PR127
PR127
10K_0402_1%
10K_0402_1%
12
3
2
1
12
PR105
PR105 10K_0402_5%
10K_0402_5%
13
PQ106
PQ106 DTC115EUA_SC70-3
DTC115EUA_SC70-3
@1000P_0402_50V7K
@1000P_0402_50V7K
12
PR134
PR134 10K_0402_5%
10K_0402_5%
PR103
PR103
47K_0402_5%
47K_0402_5%
1 2
2
PR124
PR124 1K_0402_5%
1K_0402_5%
1 2
PACIN
1.24VREF
VIN
ACOFF <32>
ACIN <32>
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2007/05/29 2008/05/29
2007/05/29 2008/05/29
2007/05/29 2008/05/29
C
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
Charger
Charger
Charger
Montevina Blade UMA LA4105P
Montevina Blade UMA LA4105P
Montevina Blade UMA LA4105P
D
of
38 45Saturday, July 18, 2009
of
38 45Saturday, July 18, 2009
of
38 45Saturday, July 18, 2009
1.0
1.0
1.0
A
B
C
D
E
2VREF_51125
1 1
PR301
PR301
13.7K_0402_1%
13.7K_0402_1%
1 2
PR303
B+
2 2
3 3
PL301
PL301
HCB2012KF-121T50_0805
HCB2012KF-121T50_0805
1 2
PC316
PC316
PACIN_1<38>
4 4
B++
12
PC301
PC301
0.1U_0402_25V6
0.1U_0402_25V6 2200P_0402_50V7K
2200P_0402_50V7K
+3VALWP
SSM3K7002FU_SC70-3
SSM3K7002FU_SC70-3
12
12
PC303
PC303
4.7U_0805_25V6-K
4.7U_0805_25V6-K
3.3UH_SIQB74B-4R7PF_5.9A_20%
3.3UH_SIQB74B-4R7PF_5.9A_20%
1
+
+
2
ENTRIP1
13
D
D
PQ305
PQ305
S
S
PQ308
PR317
PR317
12
PQ308
PC318
PC318
@SSM3K7002FU_SC70-3
@SSM3K7002FU_SC70-3
1 2
@604K_0402_1%
@604K_0402_1%
PL302
PL302
PC309
PC309
2
G
G
+3VLP
PQ301
PQ301
1
D1
2
D1
3
G2
4
S2
AO4932_2N_SO8
AO4932_2N_SO8
12
220U_6.3VM_R15
220U_6.3VM_R15
ENTRIP2<37>
13
2
G
G
13
D
D
S
S
2
G
G
1 2
100K_0402_5%
100K_0402_5%
13
D
D
PQ307
PQ307
2
G
G
SSM3K7002FU_SC70-3
SSM3K7002FU_SC70-3
S
S
PR313
PR313
8
1G
7
1S/2D
6
1S/2D
5
1S/2D
LG_3V
D
D
PQ306
PQ306 SSM3K7002FU_SC70-3
SSM3K7002FU_SC70-3
S
S
12
UG1_3V
VL
100K_0402_5%
100K_0402_5% PR314
PR314
PR315
PR315
@4.7_1206_5%
@4.7_1206_5%
12
PC306
PC306
10U_0805_6.3V6M
10U_0805_6.3V6M
1 2
PC307
PC307
0.1U_0402_10V7K
0.1U_0402_10V7K
LX_3V
12
12
PC314
PC314
@680P_0603_50V7K
@680P_0603_50V7K
+5VALWP
+3VALWP
EC_ON <32>
1 2
0_0402_5%
0_0402_5%
B++
EN0_TRIP<37>
PR307
PR307
PR309
PR309
1 2
1M_0402_1%
1M_0402_1%
1 2
1 2
PR303
20K_0402_1%
20K_0402_1%
1 2
PR305
PR305
100K_0402_1%
100K_0402_1%
1 2
PU301
PU301
25
P PAD
7
VO2
8
BST_3V BST_5V
UG_3V
VREG3
9
VBST2
10
DRVH2
11
LL2
12
DRVL2
12
PR311
PR311
191K_0402_1%
191K_0402_1%
2VREF_51125
PJP302
PJP302
PAD-OPEN 4x4m
PAD-OPEN 4x4m PJP303
PJP303
PAD-OPEN 4x4m
PAD-OPEN 4x4m
12
PC302
PC302
0.22U_0603_10V7K
0.22U_0603_10V7K
PR302
PR302
30.9K_0402_1%
30.9K_0402_1%
1 2
PR304
PR304
20K_0402_1%
20K_0402_1%
1 2
140K_0402_1%
ENTRIP2
3
4
5
6
VFB2
VREF
TONSEL
ENTRIP2
GND
VIN
SKIPSEL
EN0
15
16
14
13
140K_0402_1%
ENTRIP1
1 2
1
2
VFB1
ENTRIP1
VO1
PGOOD
VBST1
DRVH1
LL1
DRVL1
VREG5
VCLK
17
18
VL
12
PC311
PC311
12
10U_0805_10V6K
B++
(4.5A,180mils ,Via NO.= 9)
+5VALW
(3A,120mils ,Via NO.= 6)
+3VALW
10U_0805_10V6K
PC312
PC312
0.1U_0603_25V7K
0.1U_0603_25V7K
PR306
PR306
24
23
22
21
20
19
TPS51125RGER_QFN24_4X4
TPS51125RGER_QFN24_4X4
UG_5V
LX_5V
LG_5V
1 2
0_0805_5%
0_0805_5%
PR308
PR308
2.2_0402_5%
2.2_0402_5%
1 2
PR318
PR318
B++
12
PC304
PC304
2200P_0402_50V7K
2200P_0402_50V7K
PC308
PC308
0.1U_0402_10V7K
0.1U_0402_10V7K
1 2
VL
+3VLP
12
12
PC317
PC317
PC305
PC305
0.1U_0402_25V6
0.1U_0402_25V6
10U_1206_25V6M
10U_1206_25V6M
UG1_5V
12
4.7_1206_5%
4.7_1206_5%
PR316
PR316
12
PC315
PC315
680P_0603_50V7K
680P_0603_50V7K
R_EC_RSMRST# <22>
PJP304
PJP304
2 1
PAD-OPEN 2x2m
PAD-OPEN 2x2m
PJP301
PJP301
2 1
PAD-OPEN 2x2m
PAD-OPEN 2x2m
+5VL
+3VL
578
PQ302
PQ302
AO4466_SO8
AO4466_SO8
3 6
241
PL303
PL303 10U_LF919AS-100M-P3_4.5A_20%
10U_LF919AS-100M-P3_4.5A_20%
1 2
578
3 6
241
PQ304
PQ304
FDS6690AS_NL_SO8
FDS6690AS_NL_SO8
+5VALWP
1
+
+
PC310
PC310
150U_D_6.3VM
150U_D_6.3VM
2
Security Classification
Security Classification
@0.047U_0402_16V7K
@0.047U_0402_16V7K
A
B
Security Classification
2007/05/29 2008/05/29
2007/05/29 2008/05/29
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2007/05/29 2008/05/29
C
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
D
Date: Sheet
Compal Electronics, Inc.
3.3VALWP/5VALWP
3.3VALWP/5VALWP
3.3VALWP/5VALWP
Montevina Blade UMA LA4105P
Montevina Blade UMA LA4105P
Montevina Blade UMA LA4105P
39 45Saturday, July 18, 2009
39 45Saturday, July 18, 2009
39 45Saturday, July 18, 2009
E
1.0
1.0
1.0
of
of
of
A
1 1
PR401
PR401
0_0402_5%
0_0402_5%
SUSP#
PR410
PR410
@10K_0402_5%
@10K_0402_5%
2 2
1 2
12
@1000P_0402_50V7K
@1000P_0402_50V7K
+1.05V_VCCP
PC401
PC401
12
PR405
PR405
0_0402_5%
0_0402_5%
+5VALW
PR403
PR403
316_0402_1%
316_0402_1%
12
12
12
PC409
PC409 1U_0603_10V6K
1U_0603_10V6K
+1.05V_VCCP
PR408
PR408
1 2
10.5K_0402_1%
10.5K_0402_1%
PR404
PR404 255K_0402_1%
255K_0402_1%
1 2
PU401
PU401
2
TON
3
VOUT
4
V5FILT
5
VFB
6
PGOOD
B
1
EN_PSV
GND7PGND
8
PR402
PR402
13
12
11
10
9
BST1_1.05VBST_1.05V
DH_1.05V
LX_1.05V
+5VALW
1 2
0_0402_5%
0_0402_5%
14TP15
VBST
DRVH
LL
TRIP
V5DRV
DRVL
TPS51117RGYR_QFN14_3.5x3.5
TPS51117RGYR_QFN14_3.5x3.5
1 2
PC402
PC402
0.1U_0402_10V7K
0.1U_0402_10V7K
1 2
PR406
PR406
15.4K_0402_1%
15.4K_0402_1%
PC415
PC415
12
4.7U_0805_10V6K
4.7U_0805_10V6K
PR411
PR411
1 2
0_0402_5%
0_0402_5%
DL_1.05V
578
3 6
578
3 6
241
241
C
12
PC414
PC414
0.1U_0402_25V6
0.1U_0402_25V6
PQ401
PQ401 AO4466_SO8
AO4466_SO8
PQ402
PQ402 FDS6690AS_NL_SO8
FDS6690AS_NL_SO8
HCB1608KF-121T30_0603
12
12
PC404
PC404
4.7U_0805_25V6-K
4.7U_0805_25V6-K
PL402
PL402
1 2
HCB1608KF-121T30_0603
PC405
PC405
2200P_0402_50V7K
2200P_0402_50V7K
1.05V_B+
12
PC403
PC403
4.7U_0805_25V6-K
4.7U_0805_25V6-K
2.2UH_PCMC063T-2R2MN_8A_20%
2.2UH_PCMC063T-2R2MN_8A_20%
12
PR407
PR407
4.7_1206_5%
4.7_1206_5%
PC412
PC412 220P_0603_50V8J
220P_0603_50V8J
1 2
PL401
PL401
1 2
1
+
+
2
D
B+
12
PC406
PC406 @680P_0402_50V7K
@680P_0402_50V7K
+1.05V_VCCP
PC408
PC408
220U_6.3VM_R15
220U_6.3VM_R15
12
PR409
PR409
25.5K_0402_1%
25.5K_0402_1%
3 3
PJP401
PJP401
+1.05V_VCCP
4 4
A
1 2
PAD-OPEN 4x4m
PAD-OPEN 4x4m
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
B
(6A,240mils ,Via NO.=12)
+VCCP
Compal Secret Data
Compal Secret Data
2007/05/29 2008/05/29
2007/05/29 2008/05/29
2007/05/29 2008/05/29
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
C
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
Compal Electronics, Inc.
1.05V_VCCP
1.05V_VCCP
1.05V_VCCP
Montevina Blade UMA LA4105P
Montevina Blade UMA LA4105P
Montevina Blade UMA LA4105P
D
40 45Saturday, July 18, 2009
40 45Saturday, July 18, 2009
40 45Saturday, July 18, 2009
of
of
of
1.0
1.0
1.0
5
D D
4
3
2
1
PR521
PR521
SYSON<9,26,32,33,36>
C C
+5VALW
+5VALW
B B
1 2
PR522
PR522
316_0402_1%
316_0402_1%
PC522
PC522
1U_0603_10V6K
1U_0603_10V6K
0_0402_5%
0_0402_5%
+1.5VP
+1.5VP
12
12
PC524
PC524
12
@1000P_0402_50V7K
@1000P_0402_50V7K
1 2
PR520 0_0402_5%PR520 0_0402_5%
PR501
PR501
1 2
10.2K_0603_0.1%
10.2K_0603_0.1%
10K_0603_0.1%
10K_0603_0.1%
PR523
PR523 255K_0402_1%
255K_0402_1%
1 2
PR502
PR502
PR510
PR510
0_0402_5%
0_0402_5%
BST_1.5V
1 2
1
PU502
PU502
2
TON
3
VOUT
4
V5FILT
5
VFB
6
PGOOD
12
PR503
PR503
@10K_0402_5%
@10K_0402_5%
14TP15
VBST
EN_PSV
DRVH
TRIP
V5DRV
DRVL
GND7PGND
8
TPS51117RGYR_QFN14_3.5x3.5
TPS51117RGYR_QFN14_3.5x3.5
+1.5V
12
13
12
LL
11
10
9
PC511
PC511
0.1U_0402_10V7K
0.1U_0402_10V7K
1 2
UG_1.5V
LX_1.5V
PR515
PR515
13.7K_0402_1%
+5VALW
13.7K_0402_1%
12
PC523
PC523
4.7U_0805_10V6K
4.7U_0805_10V6K
1 2
LG_1.5V
DDR3_SM_PWROK <9>
+5VALW
PR508
PR508
0_0402_5%
0_0402_5%
1 2
AO4466_SO8
AO4466_SO8
UG1_1.5V
12
PR516
PR516 @4.7_1206_5%
@4.7_1206_5%
12
PC519
PC519
@680P_0603_50V7K
@680P_0603_50V7K
PQ501
PQ501
B+++
578
3 6
241
2.2UH +-20% PCMC063T-2R2MN 8A
2.2UH +-20% PCMC063T-2R2MN 8A
578
3 6
241
PL502
PL502
HCB1608KF-121T30_0603
HCB1608KF-121T30_0603
12
12
PC516
PC516
PC504
PC504
4.7U_0805_25V6-K
4.7U_0805_25V6-K
4.7U_0805_25V6-K
4.7U_0805_25V6-K
PL501
PL501
1 2
PC510
PC510
4.7U_0805_6.3V6K
4.7U_0805_6.3V6K
PQ503
PQ503
FDS6690AS_SO8
FDS6690AS_SO8
B+
12
12
12
PC521
PC521
PC505
PC505
2200P_0402_50V7K
2200P_0402_50V7K
0.1U_0402_25V6
0.1U_0402_25V6
+1.5VP
1
+
+
PC508
PC508
1 2
2
330U_2V_M_R15M
330U_2V_M_R15M
PJP501
PJP501
1 2
PAD-OPEN 4x4m
PAD-OPEN 4x4m
PJP502
PJP502
5
1 2
PAD-OPEN 4x4m
PAD-OPEN 4x4m
+1.5VP
A A
(8A,320mils ,Via NO.= 16)
+1.5V
Security Classification
Security Classification
Security Classification
2007/05/29 2008/05/29
2007/05/29 2008/05/29
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2007/05/29 2008/05/29
3
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
2
Date: Sheet
Compal Electronics, Inc.
1.5VP
1.5VP
1.5VP
Montevina Blade UMA LA4105P
Montevina Blade UMA LA4105P
Montevina Blade UMA LA4105P
41 45Saturday, July 18, 2009
41 45Saturday, July 18, 2009
41 45Saturday, July 18, 2009
1
1.0
1.0
1.0
of
of
of
5
D D
C C
PJP601
PJP601
+0.75VP
1 2
PAD-OPEN 3x3m
PAD-OPEN 3x3m
(2A,80mils ,Via NO.= 4)
+0.75V
4
+1.5V
12
12
PC601
PC601
10U_0805_10V4Z
10U_0805_10V4Z
SYSON#<34,36>
SUSP<36>
1 2
PR602
PR602
@0_0402_5%
@0_0402_5%
SSM3K7002FU_SC70-3
SSM3K7002FU_SC70-3
1 2
PR604
PR604
0_0402_5%
0_0402_5%
PQ601
PQ601
2
12
PC606
PC606 @0.1U_0402_16V7K
@0.1U_0402_16V7K
12
PC602
PC602
PR601
PR601
1K_0402_1%
1K_0402_1%
@10U_0805_10V4Z
@10U_0805_10V4Z
12
PR603
PR603
13
D
D
1K_0402_1%
G
G
1K_0402_1%
S
S
3
PU601
PU601
VIN1VCNTL
2
GND
3
VREF
4
VOUT
G2992F1U_SO8
G2992F1U_SO8
6
5
NC
7
NC
8
NC
9
TP
12
PC603
PC603 1U_0603_16V6K
1U_0603_16V6K
+5VALW
2
1
+0.75VP
12
12
PC605
PC605 10U_0805_6.3V6M
10U_0805_6.3V6M
0.1U_0402_16V7K
0.1U_0402_16V7K
PC604
PC604
B B
A A
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2006/11/23 2007/11/23
2006/11/23 2007/11/23
2006/11/23 2007/11/23
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
Compal Electronics, Inc.
0.75VP
0.75VP
0.75VP
Montevina Blade UMA LA4105P
Montevina Blade UMA LA4105P
Montevina Blade UMA LA4105P
1
of
42 45Saturday, July 18, 2009
of
42 45Saturday, July 18, 2009
of
42 45Saturday, July 18, 2009
1.0
1.0
1.0
5
4
3
2
1
+5VS
PC205
PC205
4.7U_0805_25V6-K
4.7U_0805_25V6-K
PR220
PR220
10K_0402_1%
10K_0402_1%
12
PC214
PC214
PR231
PR231
CPU_B+
12
12
PC206
PC206
4.7U_0805_25V6-K
4.7U_0805_25V6-K
PL202
PL202
12
PR224
PR224
@0_0603_5%
@0_0603_5%
1 2
PC211
PC211
1 2
ISEN1
0.22U_0603_10V7K
0.22U_0603_10V7K
12
12
PC235
PC235
PC236
PC236
2200P_0402_50V7K
2200P_0402_50V7K
4.7U_0805_25V6-K
4.7U_0805_25V6-K
PL203
PL203
12
10K_0402_1%
10K_0402_1%
PR233 @0_0603_5%PR233 @0_0603_5%
1 2
PC223
PC223
1 2
0.22U_0603_10V7K
0.22U_0603_10V7K
ISEN2
PC207
PC207
12
4.7U_0805_25V6-K
4.7U_0805_25V6-K
PR202
12
0.22U_0603_10V7K
0.22U_0603_10V7K PC209
PC209
1 2
1 2
0_0603_5%
0_0603_5%
PR217
PR217
1 2
PC217
PC217
PR202 1_0603_5%
1_0603_5%
1 2
12
PC203
PC203
2.2U_0603_6.3V6K
2.2U_0603_6.3V6K
RQW130N03_PSO8
RQW130N03_PSO8
PQ202
PQ202
FDS8672S_SO8
FDS8672S_SO8
PQ205
PQ205
FDS8672S_SO8
FDS8672S_SO8
PQ201
PQ201
UGATE_CPU1-2
578
3 6
241
PQ204
PQ204
RQW130N03_PSO8
RQW130N03_PSO8
UGATE_CPU2-2
578
3 6
241
3 5
578
3 6
578
PC242
PC242
241
241
PQ203
PQ203
FDS8672S_SO8
FDS8672S_SO8
3 5
241
PQ206
PQ206
3 6
241
FDS8672S_SO8
FDS8672S_SO8
1
12
12
+
+
PC204
PC204
2
470P_0402_50V7K
470P_0402_50V7K
68U_25V_M_R0.44
68U_25V_M_R0.44
12
12
PR245
PR245
PR218
PR218
4.7_1206_5%
4.7_1206_5%
4.7_1206_5%
4.7_1206_5%
12
PC210
PC210
2200P_0603_50V7K
2200P_0603_50V7K
12
PC233
PC233
PC234
PC234
4.7U_0805_25V6-K
4.7U_0805_25V6-K
4.7U_0805_25V6-K
4.7U_0805_25V6-K
0.36UH_PCMC104T-R36MN1R17_30A_20%
0.36UH_PCMC104T-R36MN1R17_30A_20%
12
PR219
PR219
3.65K_0805_1%
3.65K_0805_1%
VSUM
12
PC213
PC213
PC212
PC212
4.7U_0805_25V6-K
4.7U_0805_25V6-K
4.7U_0805_25V6-K
4.7U_0805_25V6-K
0.36UH_PCMC104T-R36MN1R17_30A_20%
0.36UH_PCMC104T-R36MN1R17_30A_20%
12
12
PR229
PR229
PR246
PR246
4.7_1206_5%
4.7_1206_5%
12
12
4.7_1206_5%
4.7_1206_5%
PR230
PR230
3.65K_0805_1%
3.65K_0805_1%
PC219
PC219
VSUM
2200P_0603_50V7K
2200P_0603_50V7K
<7>
<7>
<7>
<7>
<32>
CPU_VID5
CPU_VID3
CPU_VID4
CPU_VID6
VR_ON
D D
PR215
PR215
@499_0402_1%
@499_0402_1%
+3VS
DPRSLPVR<9,22>
H_DPRSTP#<7,9,21>
CLK_ENABLE#<17>
+3VS
1 2
VGATE<17,22>
H_PSI#<7>
PR221
PR221
1 2
@0_0402_5%
@0_0402_5%
PR222 147K_0402_1%PR222 147K_0402_1%
1 2
C C
PR226 13K_0402_1%PR226 13K_0402_1%
VR_TT#
PC2150.022U_0603_25V7K PC2150.022U_0603_25V7K
1 2
1 2
1 2
PC2161000P_0402_50V7K PC2161000P_0402_50V7K
PR228 13K_0402_1%
PR228 13K_0402_1%
1 2
1 2
PC218 1000P_0402_50V7KPC218 1000P_0402_50V7K
PR235 97.6K_0402_1%PR235 97.6K_0402_1%
1 2
PC222 100P_0402_50V8J
PC222 100P_0402_50V8J
100_0402_1%
B B
VCCSENSE<7>
100_0402_1%
PC220
PC220
270P_0402_50V7K
270P_0402_50V7K
1 2
1 2
PR238
PR238
1 2
PR240 1K_0402_1%PR240 1K_0402_1%
VSSSENSE<7>
12
PC224 2200P_0402_50V7K
PC224 2200P_0402_50V7K
1 2
VCC_PRM
PR201 499_0402_1%PR201 499_0402_1%
PR204 0_0402_5%PR204 0_0402_5%
PR206 0_0402_5%PR206 0_0402_5%
1 2
12
PC201
PC201
PR216
PR216
1U_0603_6.3V6M
1U_0603_6.3V6M
1.91K_0402_1%
1.91K_0402_1%
10
11
12
PR236
PR236
1 2
@0_0402_5%
@0_0402_5%
PC226 330P_0603_50V8PC226 330P_0603_50V8
1 2
12
PC227
PC227 330P_0603_50V8
330P_0603_50V8
PC229 180P_0402_50V8JPC229 180P_0402_50V8J
1 2
PR243 1K_0402_1%PR243 1K_0402_1%
PC231
PC231
0.22U_0603_10V7K
0.22U_0603_10V7K
1 2
PR203 0_0402_5%PR203 0_0402_5%
1 2
1 2
12
49
GND
1
PGOOD
2
PSI#
3
PMON
4
RBIAS
5
VR_TT#
6
NTC
7
SOFT
8
OCSET
9
VW
47
48
3V3
CLK_EN#
PR208
PR208
PR207
PR207
12
12
0_0402_5%
0_0402_5%
43
44
45
46
VR_ON
DPRSTP#
DPRSLPVR
ISL6266ACRZ-T_QFN48_7X7
ISL6266ACRZ-T_QFN48_7X7
COMP
FB
FB2
VDIFF13VSEN14RTN15DROOP16DFB17VO18VSUM19VIN20GND21VDD22ISEN223ISEN1
12
PR237
PR237
1K_0402_1%
1K_0402_1%
12
PC228
PC228
0.01U_0603_50V7K
0.01U_0603_50V7K
1 2
1 2
PR244 3.57K_0402_1%PR244 3.57K_0402_1%
PC230 0.1U_0402_16V7KPC230 0.1U_0402_16V7K
1 2
PC232 0.22U_0402_6.3V6KPC232 0.22U_0402_6.3V6K
12
PR210
PR210
PR209
PR209
PR211
PR211
12
12
12
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
12
12
PR242
PR242
12
CPU_VID1
CPU_VID2
PR213
PR213
PR212
PR212
PR205
PR205
12
12
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
BOOT1
UGATE1
PHASE1
PGND1
LGATE1
LGATE2
PGND2
PHASE2
UGATE2
BOOT2
1 2
12
PC221
PC221 1U_0402_6.3V6K
1U_0402_6.3V6K
PR239
PR239
10_0603_5%
10_0603_5%
1 2
PC225
PC225
0.1U_0603_25V7K
0.1U_0603_25V7K
VSUM
12
PR241
PR241
2.61K_0402_1%
2.61K_0402_1%
PH201
PH201
11K_0402_1%
11K_0402_1%
1 2
CPU_VID0
12
0_0402_5%
0_0402_5%
VID037VID138VID239VID340VID441VID542VID6
PVCC
NC
24
PR234 1_0603_5%PR234 1_0603_5%
10KB_0603_5%_ERTJ1VR103J
10KB_0603_5%_ERTJ1VR103J
36
35
34
33
32
31
30
29
28
27
26
25
PU201
PU201
ISEN1 ISEN2
<7>
<7>
<7>
0.022U_0402_16V7K
0.022U_0402_16V7K
BOOT_CPU1
UGATE_CPU1-1
PHASE_CPU1
LGATE_CPU1
LGATE_CPU2
PHASE_CPU2
UGATE_CPU2-1
BOOT_CPU2
1 2
PR227
PR227
2.2_0603_5%
2.2_0603_5%
+5VS
CPU_B+
PC202
PC202
2.2_0603_5%
2.2_0603_5% PR214
PR214
1 2
PR225
PR225
1 2
0_0603_5%
0_0603_5%
0.22U_0603_10V7K
0.22U_0603_10V7K
SMB3025500YA_2P
SMB3025500YA_2P
12
2200P_0402_50V7K
2200P_0402_50V7K
12
PR223
PR223
1_0402_5%
1_0402_5%
VCC_PRM
12
12
12
12
PR232
PR232
1_0402_5%
1_0402_5%
VCC_PRM
PL201
PL201
12
12
PC237
PC237
470P_0402_50V7K
470P_0402_50V7K
1
1
PC24168U_25V_M_R0.44+PC24168U_25V_M_R0.44
12
PC243
PC243
47P_0402_50V8J
47P_0402_50V8J
+
PC239
PC239
2
68U_25V_M_R0.44
68U_25V_M_R0.44
+VCC_CORE
+
+
2
12
PC244
PC244
47P_0402_50V8J
47P_0402_50V8J
CPU_B+
PC238
PC238
47P_0402_50V8J
47P_0402_50V8J
12
PC245
PC245
47P_0402_50V8J
47P_0402_50V8J
B+
12
12
PC208
PC208
PC240
PC240
1000P_0402_50V7K
1000P_0402_50V7K
2200P_0402_50V7K
2200P_0402_50V7K
A A
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
+CPU_CORE
+CPU_CORE
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2
+CPU_CORE
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
Date: Sheet
1
of
of
of
43 45Saturday, July 18, 2009
43 45Saturday, July 18, 2009
43 45Saturday, July 18, 2009
1.0
1.0
1.0
A
Version Change List ( P. I. R. List ) for Power Circuit
Version Change List ( P. I. R. List ) for Power Circuit
Version Change List ( P. I. R. List ) for Power CircuitVersion Change List ( P. I. R. List ) for Power Circuit
Request
Request
Page#
Page#
Item
Page#Page#
ItemItem
1 1
1
37
Title
Title
TitleTitle
3.3VALWP/5VALWP
Date
Date
DateDate
5/4
RequestRequest Owner
Owner
OwnerOwner
Compal
B
Issue DescriptionItem
Issue DescriptionIssue Description
RF solution
C
Add PC316, PC317
Solution Description
Solution Description
Solution DescriptionSolution Description
D
E
Rev.
Rev.Issue Description
Rev.Rev.
2
41 +1.5VP 5/4 Compal RF solution Add PC521
3
2 2
3 3
+1.05V_VCCP Compal
5/440 Add PC414
RF solution
4 4
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2007/08/02 2008/08/02
2007/08/02 2008/08/02
2007/08/02 2008/08/02
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
D
Date: Sheet
Compal Electronics, Inc.
Power Changed-List History-1
Power Changed-List History-1
Power Changed-List History-1
Montevina Blade UMA LA4105P
Montevina Blade UMA LA4105P
Montevina Blade UMA LA4105P
44 45Saturday, July 18, 2009
44 45Saturday, July 18, 2009
44 45Saturday, July 18, 2009
of
of
E
of
1.0
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Item (Reason for change)Fixed Issue PAGE Modify List Date
85 03/31V_DDR_MCH_REF change to +1.5VDDR2 change to DDR3 09
86
DDR2 change to DDR3 09 SMRCOMP_VOH change to +1.5V
87
D D
C C
DDR2 change to DDR3 SMRCOMP change to +1.5V
88
DDR2 change to DDR3 0941 Add AND gate (U48) and R1119~R1120, C1408 for SM_RWOK
89
DDR2 change to DDR3 12 VCC_SM_CK change to +1.5V
90
DDR2 change to DDR3 13 VCC_SM change to +1.5V
DDR2 change to DDR3
91
92
DDR2 change to DDR3
DDR2 change to DDR3
93
DDR2 change to DDR3
94
09
1516 Change to DDR3 SODIMM
36 Delete reserve +1.8V DC-DC, and add +1.5V DC-DC
3627Add LDO for +1.8V_LVDS
delete +1.8VS_CR, card reader internal LDO can provide +1.8VS
03/31
03/31
03/31
03/31
03/31
03/31
03/31
03/31
03/31
modify R750 netname trace, add R1129 for UTX.Gobi RF test and UTX for debug card.
EMI solution for ENE cap. board.
EMI solution for ENE cap. board. modify R234 ,R56 and R149 to 33 ohm , C310 to 15pF. BOM change.
32
modify R731 and R732 to 33 ohm. BOM change.
33
06/19 1.4PVR
06/19 1.4PVR
Phase
1.4DB
1.4DB
1.4DB
1.4DB
1.4DB
1.4DB
1.4DB
1.4DB
1.4DB
1.4DB
1.4PVR06/1926
B B
A A
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2007/08/28 2006/07/26
2007/08/28 2006/07/26
2007/08/28 2006/07/26
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
2
Date: Sheet
Compal Electronics, Inc.
HW PIR 3
HW PIR 3
HW PIR 3
Montevina Blade UMA LA4105P
Montevina Blade UMA LA4105P
Montevina Blade UMA LA4105P
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45 45Saturday, July 18, 2009
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45 45Saturday, July 18, 2009
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45 45Saturday, July 18, 2009
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