COMPAL LA-4092P Schematics

1 1

2 2

Compal confidential

JBK00 LA-4092P Schematics Document

Mobile AMD S1G2 CPU with ATI RX781 & SB700 core logic with M82-S

3 3

2008-02-20

REV:0.4

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2007/08/02 2008/08/02

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

Cover Sheet

LA-4092P

153Thursday, February 21, 2008

0.4

Compal

Consumer AMD UMA/DISCRETE 17"

confidential

1 1

VRAM 256MB

page 19, 20

Discrete

ATI M82-S

P15,16,17,18,21

Thermal Sensor ADM1032ARMZ

Fan conn

PCI-E Lane*16

AMD S1G2 CPU

638-PIN uFCPGA 638

P4, 5, 6, 7

Hyper Transport Link

16X16

ATI RX781M

LVDS Panel Interface

2 2

CRT

HDMI

P24

P10, 11, 12, 13, 14

P23

A-Link Express II 4X PCI-E

P25

PCI-E BUS*5

ATI SB700

LED

P42

RTL8111C

10/100/1000

Mini-Card*2

WLAN & TV Tunner

P32

P33

Express Card

P33

P26, 27, 28, 29, 30

DDR2 667MHz 1.8V DDR2 800MHz 1.8V

Dual Channel

USB2.0 X12

Azalia SATA Master-1 SATA Master-2 SATA Slave SATA Slave

DDR2-SO-DIMM X2

BANK 0, 1, 2, 3

P8, 9

Finger Print

USB Camera with Digital MIC

USB conn x4

BT Conn

Touch Screen

Dock

Clock Generator SLG8SP626

P39

P43

72QFN

P22

3 3

RTC CKT.

P26

Power OK CKT.

Docking CKT.

P43

RJ45 Conn.

P32

CardReader

JMB380

P34

1394 Conn.

P34 P34

SPI ROM

SPI

P40

Touch Pad CONN.

P42

ENE

KB926

CIR

P37

LPC BUS

P41

Int.KBD

P41

DC/DC Interface CKT.

4 4

ACCELEROMETER.

LIS302DLTR

P44

P35

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2007/08/02 2008/08/02

Compal Secret Data

Deciphered Date

Audio CKT AMP & Audio Jack

Codec_92HD71B7

MDC V1.5

SATA HDD Connector

SATA ODD Connector

SATA 2nd HDD Option Connector

e-SATA Connector

P36

P42

P31

P39

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

Subwoofer

P31

Block Diagram

LA-4092P

TPA6020A2

SUBAMP

TPA3007D1

P37

P38

0.4

253Thursday, February 21, 2008

Voltage Rails

Symbol Note :

+5VS

1 1

State

power plane

+B +3VL

+5VALW +3VALW +1.2VALW +3V_LAN+5VL

+1.8V +0.9V

+3VS +2.5VS +1.8VS +1.5VS +1.1VS +VGA_CORE +1.2V_HT +CPU_CORE_NB +CPU_CORE_0 +CPU_CORE_1

: means Digital Ground

: means Analog Ground

@ : means just reserve , no build DEBUG@ : means just reserve for debug.

Layout Notes

2 2

S5 S4/AC

S5 S4/ Battery only

S5 S4/AC & Battery don't exist

O O O O O

O MEANS ON X MEANS OFF

I2C / SMBUS ADDRESSING

DEVICE

3 3

DDR SO-DIMM 0 DDR SO-DIMM 1 CLOCK GENERATOR (EXT.)

HEX

D2 3AACCELEROMETER 0 0 1 1 1 0 1 0

EC SM Bus1 address

Device

Smart Battery

24C16

CPU SIC interface

4 4

HEX HEX

Address Address

0001 011X b

16H

1010 000X b

A0H

1001 100X b

98H

O O O O

XX X

OO OO

XX X

ADDRESS

1 0 1 0 0 0 0 0 1 0 1 0 0 1 0 0A4 1 1 0 1 0 0 1 0

EC SM Bus2 address

Device ADI1032-2 CPU ADI1032-1 VGA

9AH 98H

1001 101X b 1001 100X b

SMBUS Control Table

SOURCE

SMB_EC_CK1 SMB_EC_DA1 SMB_EC_CK2 SMB_EC_DA2 I2C_CLK I2C_DATA DDC_CLK0 DDC_DATA0 DDC_CLK1 DDC_DATA1 SCL0 SDA0 SCL1 SDA1 SCL2 SDA2 SCL3 SDA3

KB926

RS780M

SB700

THERMAL SENSORSERIAL

CPU & ADM1032

I / II

XXXXXX

X X

EEPROMBATTINVERTER

XX XX

XX XXX

XX XXXX

XXX

XXXX XX

CLK CHIPSODIMM

X X

XXXX

MINI CARD

Slot 2

LCD

X XXXXX XXX

XXX

XXXX XX

XXX

X X

HDMI

X X X

G-Sensor

X X X X X

X X X

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2007/08/02 2008/08/02

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

Notes List

LA-4092P

353Thursday, February 21, 2008

0.4

1 1

+1.2V_HT

250 mil

H_CADIP[0..15]10

H_CADIP[0..15] H_CADIN[0..15]

H_CADOP[0..15] H_CADON[0..15]

H_CADOP[0..15] 10 H_CADON[0..15] 10H_CADIN[0..15]10

4.7U_0805_10V4Z

VLDT CAP.

0.22U_0603_16V4Z

C5 180P_0402_50V8J

180P_0402_50V8J

C6 180P_0402_50V8J

180P_0402_50V8J

Near CPU Socket

+1.2V_HT

2 2

3 3

VLDT=500mA

H_CADIP0 H_CADIN0 H_CADIP1 H_CADIN1 H_CADIP2 H_CADIN2 H_CADIP3 H_CADIN3 H_CADIP4 H_CADIN4 H_CADIP5 H_CADIN5 H_CADIP6 H_CADIN6 H_CADIP7 H_CADIN7 H_CADIP8 H_CADIN8 H_CADIP9 H_CADIN9 H_CADIP10 H_CADIN10 H_CADIP11 H_CADIN11 H_CADIP12 H_CADIN12 H_CADIP13 H_CADIN13 H_CADIP14 H_CADIN14 H_CADIP15 H_CADIN15

H_CLKIP010 H_CLKIN010 H_CLKIP110 H_CLKIN110

H_CTLIP010 H_CTLIP110 H_CTLOP1 10

H_CTLIN110

D1 D2 D3 D4

E3 E2 E1

F1 G3 G2 G1

J1 K1 L3 L2 L1

N3 N2 E5 F5 F3 F4

H5 H3 H4 K3 K4 L5

M5 M3 M4

N5 P5

J5 K5

N1 P1 P3 P4

VLDT_A0 VLDT_A1 VLDT_A2 VLDT_A3

L0_CADIN_H0 L0_CADIN_L0 L0_CADIN_H1 L0_CADIN_L1 L0_CADIN_H2 L0_CADIN_L2 L0_CADIN_H3 L0_CADIN_L3 L0_CADIN_H4 L0_CADIN_L4 L0_CADIN_H5 L0_CADIN_L5 L0_CADIN_H6 L0_CADIN_L6 L0_CADIN_H7 L0_CADIN_L7 L0_CADIN_H8 L0_CADIN_L8 L0_CADIN_H9 L0_CADIN_L9 L0_CADIN_H10 L0_CADIN_L10 L0_CADIN_H11 L0_CADIN_L11 L0_CADIN_H12 L0_CADIN_L12 L0_CADIN_H13 L0_CADIN_L13 L0_CADIN_H14 L0_CADIN_L14 L0_CADIN_H15 L0_CADIN_L15

L0_CLKIN_H0 L0_CLKIN_L0 L0_CLKIN_H1 L0_CLKIN_L1

L0_CTLIN_H0 L0_CTLIN_L0 L0_CTLIN_H1 L0_CTLIN_L1

6090022100G_B

JP1A

HT LINK

VLDT_B0 VLDT_B1 VLDT_B2 VLDT_B3

L0_CADOUT_H0 L0_CADOUT_L0 L0_CADOUT_H1 L0_CADOUT_L1 L0_CADOUT_H2 L0_CADOUT_L2 L0_CADOUT_H3 L0_CADOUT_L3 L0_CADOUT_H4 L0_CADOUT_L4 L0_CADOUT_H5 L0_CADOUT_L5 L0_CADOUT_H6 L0_CADOUT_L6 L0_CADOUT_H7 L0_CADOUT_L7 L0_CADOUT_H8 L0_CADOUT_L8 L0_CADOUT_H9

L0_CADOUT_L9 L0_CADOUT_H10 L0_CADOUT_L10 L0_CADOUT_H11 L0_CADOUT_L11 L0_CADOUT_H12 L0_CADOUT_L12 L0_CADOUT_H13 L0_CADOUT_L13 L0_CADOUT_H14 L0_CADOUT_L14 L0_CADOUT_H15 L0_CADOUT_L15

L0_CLKOUT_H0

L0_CLKOUT_L0

L0_CLKOUT_H1

L0_CLKOUT_L1 L0_CTLOUT_H0

L0_CTLOUT_L0 L0_CTLOUT_H1 L0_CTLOUT_L1

+VLDT_B

AE2 AE3 AE4 AE5

AD1 AC1 AC2 AC3 AB1 AA1 AA2 AA3 W2 W3 V1 U1 U2 U3 T1 R1 AD4 AD3 AD5 AC5 AB4 AB3 AB5 AA5 Y5 W5 V4 V3 V5 U5 T4 T3

Y1 W1 Y4 Y3

R2 R3 T5 R5

1 2

C7 4.7U_0805_10V4ZC7 4.7U_0805_10V4Z

H_CADOP0 H_CADON0 H_CADOP1 H_CADON1 H_CADOP2 H_CADON2 H_CADOP3 H_CADON3 H_CADOP4 H_CADON4 H_CADOP5 H_CADON5 H_CADOP6 H_CADON6 H_CADOP7 H_CADON7 H_CADOP8 H_CADON8 H_CADOP9 H_CADON9 H_CADOP10 H_CADON10 H_CADOP11 H_CADON11 H_CADOP12 H_CADON12 H_CADOP13 H_CADON13 H_CADOP14 H_CADON14 H_CADOP15 H_CADON15

H_CLKOP0 10 H_CLKON0 10 H_CLKOP1 10 H_CLKON1 10

H_CTLOP0 10 H_CTLON0 10H_CTLIN010

H_CTLON1 10

PWM Fan Control circuit

CH751H-40PT_SOD323-2

FAN_PWM41

+5VS

JP2

2 1

SI3456BDV-T1-E3_TSOP6

4 5

4.7U_0805_10V4Z

+VCC_FAN

0.1U_0402_16V4Z@C90.1U_0402_16V4Z@

@D2

RLZ5.1B_LL34

GND

ACES_88231-02001

CONN@

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2007/08/02 2008/08/02

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

AMD CPU S1G2 HT I/F

LA-4092P

453Thursday, February 21, 2008

0.4

Processor DDR2 Memory Interface

PLACE CLOSE TO PROCESSOR WITHIN 1.5 INCH

AD10 AF10

AE10

AA16

D10 C10 B10

H16 T19

V22 U21 V19

T20 U19 U20 V20

J22 J20

N19 N20 E16 F16 Y16

P19 P20

N21 M20 N22 M19 M22 L20 M24 L21 L19 K22 R21 L22 K20 V24 K24 K19

R20 R23

J21

R19 T22 T24

DDR_A_CLK0

DDR_A_CLK#0 DDR_A_CLK1

DDR_A_CLK#1

DDR_B_CLK0

DDR_B_CLK#0 DDR_B_CLK1

DDR_B_CLK#1

VTT1

MEM:CMD/CTRL/CLK

VTT2 VTT3 VTT4

MEMZP MEMZN

RSVD_M1 MA0_ODT0

MA0_ODT1 MA1_ODT0 MA1_ODT1

MA0_CS_L0 MA0_CS_L1 MA1_CS_L0 MA1_CS_L1

MA_CKE0 MA_CKE1

MA_CLK_H0 MA_CLK_L0 MA_CLK_H1 MA_CLK_L1 MA_CLK_H2 MA_CLK_L2 MA_CLK_H3 MA_CLK_L3

MA_ADD0 MA_ADD1 MA_ADD2 MA_ADD3 MA_ADD4 MA_ADD5 MA_ADD6 MA_ADD7 MA_ADD8 MA_ADD9 MA_ADD10 MA_ADD11 MA_ADD12 MA_ADD13 MA_ADD14 MA_ADD15

MA_BANK0 MA_BANK1 MA_BANK2

MA_RAS_L MA_CAS_L MA_WE_L

JP1B

VTT5 VTT6 VTT7 VTT8 VTT9

VTT_SENSE

MEMVREF

RSVD_M2

MB0_ODT0 MB0_ODT1 MB1_ODT0

MB0_CS_L0 MB0_CS_L1 MB1_CS_L0

MB_CKE0 MB_CKE1

MB_CLK_H0

MB_CLK_L0

MB_CLK_H1

MB_CLK_L1

MB_CLK_H2

MB_CLK_L2

MB_CLK_H3

MB_CLK_L3

MB_ADD0 MB_ADD1 MB_ADD2 MB_ADD3 MB_ADD4 MB_ADD5 MB_ADD6 MB_ADD7 MB_ADD8

MB_ADD9 MB_ADD10 MB_ADD11 MB_ADD12 MB_ADD13 MB_ADD14 MB_ADD15

MB_BANK0 MB_BANK1 MB_BANK2

MB_RAS_L MB_CAS_L

MB_WE_L

C10

1.5P_0402_50V9C

C11

1.5P_0402_50V9C

C14

1.5P_0402_50V9C

C15

1.5P_0402_50V9C

W10 AC10 AB10 AA10 A10

Y10 W17 B18 W26

W23 Y26

V26 W25 U22

J25 H26

P22 R22 A17 A18 AF18 AF17 R26 R25

P24 N24 P26 N23 N26 L23 N25 L24 M26 K26 T26 L26 L25 W24 J23 J24

R24 U26 J26

U25 U24 U23

+0.9V+0.9V

VTT_SENSE

+MCH_REF

DDR_B_ODT0 DDR_B_ODT1

DDR_CS1_DIMMB#

DDR_CKE0_DIMMB DDR_CKE1_DIMMB

DDR_B_CLK0 DDR_B_CLK#0 DDR_B_CLK1 DDR_B_CLK#1DDR_A_CLK#1

DDR_B_MA0 DDR_B_MA1 DDR_B_MA2 DDR_B_MA3 DDR_B_MA4 DDR_B_MA5 DDR_B_MA6 DDR_B_MA7 DDR_B_MA8 DDR_B_MA9 DDR_B_MA10 DDR_B_MA11 DDR_B_MA12 DDR_B_MA13 DDR_B_MA14 DDR_B_MA15

DDR_B_BS#0 DDR_B_BS#1 DDR_B_BS#2

DDR_B_RAS# DDR_B_CAS# DDR_B_WE#

T1PAD T1PAD

T3PAD T3PAD

DDR_B_ODT0 9 DDR_B_ODT1 9

DDR_CS1_DIMMB# 9

DDR_CKE0_DIMMB 9 DDR_CKE1_DIMMB 9

DDR_B_CLK0 9 DDR_B_CLK#0 9 DDR_B_CLK1 9 DDR_B_CLK#1 9

DDR_B_BS#0 9 DDR_B_BS#1 9 DDR_B_BS#2 9

DDR_B_RAS# 9 DDR_B_CAS# 9 DDR_B_WE# 9

1 1

2 2

+1.8V

1K_0402_1% R11K_0402_1%

1 2

+MCH_REF

1K_0402_1% R21K_0402_1%

1 2

C12

C13

0.1U_0402_16V4Z

0.1U_0402_16V4Z 1000P_0402_25V8J

1000P_0402_25V8J

Place them close to CPU within 1"

R4 39.2_0402_1%

1 2

+1.8V

DDR_A_ODT08 DDR_A_ODT18

DDR_CS0_DIMMA#8 DDR_CS1_DIMMA#8 DDR_CS0_DIMMB# 9

DDR_CKE0_DIMMA8 DDR_CKE1_DIMMA8

DDR_A_CLK08

DDR_A_CLK#08

DDR_A_CLK18

DDR_A_CLK#18

3 3

DDR_A_MA[15..0]8 DDR_B_MA[15..0] 9

DDR_A_BS#08 DDR_A_BS#18 DDR_A_BS#28

DDR_A_RAS#8 DDR_A_CAS#8 DDR_A_WE#8

1 2

R3 39.2_0402_1%

T2 PADT2 PAD

DDR_A_ODT0 DDR_A_ODT1

DDR_CS0_DIMMA# DDR_CS1_DIMMA# DDR_CS0_DIMMB#

DDR_CKE0_DIMMA DDR_CKE1_DIMMA

DDR_A_CLK0 DDR_A_CLK#0 DDR_A_CLK1

DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 DDR_A_MA14 DDR_A_MA15

DDR_A_BS#0 DDR_A_BS#1 DDR_A_BS#2

DDR_A_RAS# DDR_A_CAS# DDR_A_WE#

DDR_B_D[63..0]9

DDR_B_DM[7..0]9 DDR_A_DM[7..0] 8

DDR_B_DQS09 DDR_B_DQS#09 DDR_B_DQS19 DDR_B_DQS#19 DDR_B_DQS29 DDR_B_DQS#29 DDR_B_DQS39 DDR_B_DQS#39 DDR_B_DQS49 DDR_B_DQS#49 DDR_B_DQS59 DDR_B_DQS#59 DDR_B_DQS69 DDR_B_DQS#69 DDR_B_DQS79 DDR_B_DQS#79

DDR_B_D0 DDR_B_D1 DDR_B_D2 DDR_B_D3 DDR_B_D4 DDR_B_D5 DDR_B_D6 DDR_B_D7 DDR_B_D8 DDR_B_D9 DDR_B_D10 DDR_B_D11 DDR_B_D12 DDR_B_D13 DDR_B_D14 DDR_B_D15 DDR_B_D16 DDR_B_D17 DDR_B_D18 DDR_B_D19 DDR_B_D20 DDR_B_D21 DDR_B_D22 DDR_B_D23 DDR_B_D24 DDR_B_D25 DDR_B_D26 DDR_B_D27 DDR_B_D28 DDR_B_D29 DDR_B_D30 DDR_B_D31 DDR_B_D32 DDR_B_D33 DDR_B_D34 DDR_B_D35 DDR_B_D36 DDR_B_D37 DDR_B_D38 DDR_B_D39 DDR_B_D40 DDR_B_D41 DDR_B_D42 DDR_B_D43 DDR_B_D44 DDR_B_D45 DDR_B_D46 DDR_B_D47 DDR_B_D48 DDR_B_D49 DDR_B_D50 DDR_B_D51 DDR_B_D52 DDR_B_D53 DDR_B_D54 DDR_B_D55 DDR_B_D56 DDR_B_D57 DDR_B_D58 DDR_B_D59 DDR_B_D60 DDR_B_D61 DDR_B_D62 DDR_B_D63

DDR_B_DM0 DDR_B_DM1 DDR_B_DM2 DDR_B_DM3 DDR_B_DM4 DDR_B_DM5 DDR_B_DM6 DDR_B_DM7

DDR_B_DQS0 DDR_B_DQS#0 DDR_B_DQS1 DDR_B_DQS#1 DDR_B_DQS2 DDR_B_DQS#2 DDR_B_DQS3 DDR_B_DQS#3 DDR_B_DQS4 DDR_B_DQS#4 DDR_B_DQS5 DDR_B_DQS#5 DDR_B_DQS6 DDR_B_DQS#6 DDR_B_DQS7 DDR_B_DQS#7

AA24 AA23 AD24 AE24 AA26 AA25 AD26 AE25 AC22 AD22 AE20 AF20 AF24 AF23 AC20 AD20 AD18 AE18 AC14 AD14 AF19 AC18 AF16 AF15 AF13 AC12 AB11

AE14 AF14 AF11 AD11

AB26 AE22 AC16 AD12

AC25 AC26 AF21 AF22 AE16 AD16 AF12 AE12

C11 A11 A14 B14 G11 E11 D12 A13 A15 A16 A19 A20 C14 D14 C18 D18 D20 A21 D24 C25 B20 C20 B24 C24 E23 E24 G25 G26 C26 D26 G23 G24

Y11

A12 B16 A22 E25

C12 B12 D16 C16 A24 A23 F26 E26

JP1C

MB_DATA0 MB_DATA1 MB_DATA2 MB_DATA3 MB_DATA4 MB_DATA5 MB_DATA6 MB_DATA7 MB_DATA8 MB_DATA9 MB_DATA10 MB_DATA11 MB_DATA12 MB_DATA13 MB_DATA14 MB_DATA15 MB_DATA16 MB_DATA17 MB_DATA18 MB_DATA19 MB_DATA20 MB_DATA21 MB_DATA22 MB_DATA23 MB_DATA24 MB_DATA25 MB_DATA26 MB_DATA27 MB_DATA28 MB_DATA29 MB_DATA30 MB_DATA31 MB_DATA32 MB_DATA33 MB_DATA34 MB_DATA35 MB_DATA36 MB_DATA37 MB_DATA38 MB_DATA39 MB_DATA40 MB_DATA41 MB_DATA42 MB_DATA43 MB_DATA44 MB_DATA45 MB_DATA46 MB_DATA47 MB_DATA48 MB_DATA49 MB_DATA50 MB_DATA51 MB_DATA52 MB_DATA53 MB_DATA54 MB_DATA55 MB_DATA56 MB_DATA57 MB_DATA58 MB_DATA59 MB_DATA60 MB_DATA61 MB_DATA62 MB_DATA63

MB_DM0 MB_DM1 MB_DM2 MB_DM3 MB_DM4 MB_DM5 MB_DM6 MB_DM7

MB_DQS_H0 MB_DQS_L0 MB_DQS_H1 MB_DQS_L1 MB_DQS_H2 MB_DQS_L2 MB_DQS_H3 MB_DQS_L3 MB_DQS_H4 MB_DQS_L4 MB_DQS_H5 MB_DQS_L5 MB_DQS_H6 MB_DQS_L6 MB_DQS_H7 MB_DQS_L7

6090022100G_B

MEM:DATA

MA_DATA0 MA_DATA1 MA_DATA2 MA_DATA3 MA_DATA4 MA_DATA5 MA_DATA6 MA_DATA7 MA_DATA8

MA_DATA9 MA_DATA10 MA_DATA11 MA_DATA12 MA_DATA13 MA_DATA14 MA_DATA15 MA_DATA16 MA_DATA17 MA_DATA18 MA_DATA19 MA_DATA20 MA_DATA21 MA_DATA22 MA_DATA23 MA_DATA24 MA_DATA25 MA_DATA26 MA_DATA27 MA_DATA28 MA_DATA29 MA_DATA30 MA_DATA31 MA_DATA32 MA_DATA33 MA_DATA34 MA_DATA35 MA_DATA36 MA_DATA37 MA_DATA38 MA_DATA39 MA_DATA40 MA_DATA41 MA_DATA42 MA_DATA43 MA_DATA44 MA_DATA45 MA_DATA46 MA_DATA47 MA_DATA48 MA_DATA49 MA_DATA50 MA_DATA51 MA_DATA52 MA_DATA53 MA_DATA54 MA_DATA55 MA_DATA56 MA_DATA57 MA_DATA58 MA_DATA59 MA_DATA60 MA_DATA61 MA_DATA62 MA_DATA63

MA_DM0 MA_DM1 MA_DM2 MA_DM3 MA_DM4 MA_DM5 MA_DM6 MA_DM7

MA_DQS_H0 MA_DQS_L0 MA_DQS_H1 MA_DQS_L1 MA_DQS_H2 MA_DQS_L2 MA_DQS_H3 MA_DQS_L3 MA_DQS_H4 MA_DQS_L4 MA_DQS_H5 MA_DQS_L5 MA_DQS_H6 MA_DQS_L6 MA_DQS_H7 MA_DQS_L7

G12 F12 H14 G14 H11 H12 C13 E13 H15 E15 E17 H17 E14 F14 C17 G17 G18 C19 D22 E20 E18 F18 B22 C23 F20 F22 H24 J19 E21 E22 H20 H22 Y24 AB24 AB22 AA21 W22 W21 Y22 AA22 Y20 AA20 AA18 AB18 AB21 AD21 AD19 Y18 AD17 W16 W14 Y14 Y17 AB17 AB15 AD15 AB13 AD13 Y12 W11 AB14 AA14 AB12 AA12

E12 C15 E19 F24 AC24 Y19 AB16 Y13

G13 H13 G16 G15 C22 C21 G22 G21 AD23 AC23 AB19 AB20 Y15 W15 W12 W13

DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15 DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63

DDR_A_DM0 DDR_A_DM1 DDR_A_DM2 DDR_A_DM3 DDR_A_DM4 DDR_A_DM5 DDR_A_DM6 DDR_A_DM7

DDR_A_DQS0 DDR_A_DQS#0 DDR_A_DQS1 DDR_A_DQS#1 DDR_A_DQS2 DDR_A_DQS#2 DDR_A_DQS3 DDR_A_DQS#3 DDR_A_DQS4 DDR_A_DQS#4 DDR_A_DQS5 DDR_A_DQS#5 DDR_A_DQS6 DDR_A_DQS#6 DDR_A_DQS7 DDR_A_DQS#7

DDR_A_D[63..0] 8

DDR_A_DQS0 8 DDR_A_DQS#0 8 DDR_A_DQS1 8 DDR_A_DQS#1 8 DDR_A_DQS2 8 DDR_A_DQS#2 8 DDR_A_DQS3 8 DDR_A_DQS#3 8 DDR_A_DQS4 8 DDR_A_DQS#4 8 DDR_A_DQS5 8 DDR_A_DQS#5 8 DDR_A_DQS6 8 DDR_A_DQS#6 8 DDR_A_DQS7 8 DDR_A_DQS#7 8

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2007/08/02 2008/08/02

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

AMD CPU S1G2 DDRII I/F

LA-4092P

553Thursday, February 21, 2008

0.4

+2.5VS

C16

100U_D2_10VM@

1 1

CLK_CPU_BCLK22

CLK_CPU_BCLK#22

+1.8VS

R15

R15 300_0402_5%

300_0402_5%

1 2

LDT_RST#26

2 2

H_PWRGD26

LDT_STOP#11,26

3 3

LDT_RST#

C22

0.01U_0402_25V4Z

+1.8VS

R21

R21 300_0402_5%

300_0402_5%

1 2

H_PWRGD

C23

+1.8VS

R36

R36 300_0402_5%

300_0402_5%

1 2

LDT_STOP#

C25

0.01U_0402_25V4Z

0.1U_0402_16V4Z@

SI2: remove 100uF

1 2

C20

1 2

C21 3900P_0402_50V7KC21 3900P_0402_50V7K

Place close to CPU wihtin 1.5"

+CPU_CORE_0

R487 10_0402_5%R487 10_0402_5%

R486 10_0402_5%R486 10_0402_5%

+CPU_CORE_1

R489 10_0402_5%R489 10_0402_5%

R488 10_0402_5%R488 10_0402_5%

+1.8VS

R30

300_0402_5%@

1 2

CPU_LDT_REQ#

C24

0.01U_0402_25V4Z

+3VS

+1.8V

CPU_SID

1 2

FBM_L11_201209_300L_0805

3900P_0402_50V7K

R8 169_0402_1%

169_0402_1%

Address:100_1100

CPU_VDD0_FB_H

1 2

CPU_VDD0_FB_L

1 2

Close to CPU

CPU_VDD1_FB_H

1 2

CPU_VDD1_FB_L

1 2

PV:unmount R30 per AMD 4.1 change

R175

20K_0402_5%@

R18

2.2K_0402_5%

PV:change to 2.2K

R19

2.2K_0402_5%

CPU_SIC

8 7 6 5

SMB_EC_CK2 SMB_EC_DA2

+3VS

C26

4 4

2200p change to 1000p for ADT7421

0.1U_0402_16V4Z

C27

1 2

2200P_0402_50V7K

THERMDA_CPU THERMDC_CPU

+1.8V

VDD

2 3

ADM1032ARMZ-2REEL_MSOP8

SCLK

D+

SDATA

ALERT#

DTHERM#4GND

Address:100_1101

+2.5VDDA

+1.2V_HT

CPU_LDT_REQ# 11,26

1 2

C939 0.1U_0402_16V4Z@C939 0.1U_0402_16V4Z@

R814

34.8K_0402_1%~N@

Q127 FDV301N_NL_SOT23-3@

Q129 FDV301N_NL_SOT23-3@

SMB_EC_CK2 21,41

VDDA=300mA

3300P_0402_50V7K

C174.7U_0805_10V4Z C174.7U_0805_10V4Z

C18

CPU_CLKIN_SC_P CPU_CLKIN_SC_N

R13 44.2_0402_1%R13 44.2_0402_1%

1 2

R14 44.2_0402_1%R14 44.2_0402_1%

1 2

CPU_VDD0_FB_H51 CPU_VDD0_FB_L51

CPU_VDD1_FB_H51 CPU_VDD1_FB_L51

+1.8V

R493 510_0402_5%@R493 510_0402_5%@

1 2 1 2

R492 510_0402_5%@R492 510_0402_5%@

2.09V for Gate

SMB_EC_DA1 40,41,42,45

EC is PU to 5VALW

SMB_EC_CK1 40,41,42,45

SMB_EC_DA2 21,41

C19

0.22U_0603_16V4Z

LDT_RST# H_PWRGD LDT_STOP# CPU_LDT_REQ#

CPU_SIC CPU_SID

CPU_HTREF0 CPU_HTREF1

CPU_VDD0_FB_H CPU_VDD0_FB_L

CPU_VDD1_FB_H CPU_VDD1_FB_L

CPU_DBRDY CPU_TMS CPU_TCK CPU_TRST#

CPU_TDI CPU_TEST23_TSTUPD CPU_TEST19_PLLTEST0

CPU_TEST18_PLLTEST1 CPU_TEST25_H_BYPASSCLK_H

CPU_TEST25_L_BYPASSCLK_L CPU_TEST21_SCANEN

CPU_TEST20_SCANCLK2 CPU_TEST24_SCANCLK1 CPU_TEST22_SCANSHIFTEN CPU_TEST12_SCANSHIFTENB CPU_TEST27_SINGLECHAIN

R25 0_0402_5%R25 0_0402_5%

1 2

FDV301N, the Vgs is: min = 0.65V Typ = 0.85V Max = 1.5V

JP1D

VDDA1

VDDA2

CLKIN_H

CLKIN_L

RESET_L

PWROK

F10

LDTSTOP_L

LDTREQ_L

AF4

SIC

AF5

SID

AE6

ALERT_L

HT_REF0

HT_REF1

VDD0_FB_H

VDD0_FB_L

VDD1_FB_H

AB6

VDD1_FB_L

G10

DBRDY

AA9

TMS

AC9

TCK

AD9

TRST_L

AF9

TDI

AD7

TEST23

H10

TEST18

TEST19

TEST25_H

TEST25_L

AB8

TEST21

AF7

TEST20

AE7

TEST24

AE8

TEST22

AC8

TEST12

AF8

TEST27

TEST9

AA6

TEST6

RSVD1

RSVD2

RSVD3

RSVD4

RSVD5

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

6090022100G_B

THERMTRIP_L

PROCHOT_L

VDDIO_FB_H VDDIO_FB_L

VDDNB_FB_H VDDNB_FB_L

M11

KEY1

W18

KEY2

CPU_SVC

SVC

CPU_SVD

SVD

AF6 AC7 AA8

MEMHOT_L

THERMDC_CPU

THERMDC THERMDA

DBREQ_L

TEST28_H

TEST28_L

TEST17 TEST16 TEST15 TEST14

TEST10

TEST29_H

TEST29_L

RSVD10

RSVD9 RSVD8 RSVD7 RSVD6

THERMDA_CPU

W9 Y9

VDD_NB_FB_H

VDD_NB_FB_L

CPU_DBREQ#

E10

CPU_TDO

AE9

TDO

CPU_TEST28_H_PLLCHRZ_P

CPU_TEST28_L_PLLCHRZ_N

CPU_TEST17_BP3

CPU_TEST16_BP2

CPU_TEST15_BP1

CPU_TEST14_BP0

C7 C3

TEST7

K8 C4

TEST8

CPU_TEST29_H_FBCLKOUT_P

CPU_TEST29_L_FBCLKOUT_N

H18 H19 AA7 D5 C5

CPU_DBREQ# CPU_DBRDY CPU_TCK CPU_TMS CPU_TDI CPU_TRST# CPU_TDO

NOTE: HDT TERMINATION IS REQUIRED FOR REV. Ax SILICON ONLY.

2007/08/02 2008/08/02

CPU_SVC 51 CPU_SVD 51

CPU_THERMTRIP#_R CPU_PROCHOT#_1.8

R48 300_0402_5%R48 300_0402_5%

+1.8V sense no support

T22PAD T22PAD T21PAD T21PAD

VDD_NB_FB_H 51 VDD_NB_FB_L 51

+1.8V

R38220_0402_5%@ R38220_0402_5%@

R40220_0402_5%@ R40220_0402_5%@

R39220_0402_5%@ R39220_0402_5%@

R37220_0402_5%@ R37220_0402_5%@

Compal Secret Data

Deciphered Date

1 2

R10 10K_0402_5%R10 10K_0402_5%

1 2

R5 300_0402_5%R5 300_0402_5%

CPU_THERMTRIP#_R

+1.8V

route as differential

T5PAD T5PAD

as short as possible

T6PAD T6PAD

testpoint under package

T13PAD T13PAD T14PAD T14PAD

+1.8V

T7PAD T7PAD T8PAD T8PAD T10PAD T10PAD T12PAD T12PAD

PV:AMD 4.1 recommend

HDT Connector

R41300_0402_5% R41300_0402_5%

JP3

1 3 5 7 9 11 13 15 17 19 21

SAMTEC_ASP-68200-07

CONN@ SAMTEC_ASP-68200-07

CONN@

Close to CPU

CPU_SVC CPU_SVD

CPU_TEST27_SINGLECHAIN

CPU_TEST21_SCANEN CPU_TEST20_SCANCLK2 CPU_TEST24_SCANCLK1 CPU_TEST22_SCANSHIFTEN CPU_TEST12_SCANSHIFTENB CPU_TEST15_BP1 CPU_TEST14_BP0 CPU_TEST19_PLLTEST0 CPU_TEST18_PLLTEST1 CPU_TEST23_TSTUPD

10 12 14 16 18 20 22 2423 26

3 1

MMBT3904_NL_SOT23-3

1 2

R9 300_0402_5%R9 300_0402_5%

CPU_PROCHOT#_1.8

VDD_NB_FB_H VDD_NB_FB_L

2 4 6 8

R484 10_0402_5%R484 10_0402_5%

1 2 1 2

R485 10_0402_5%R485 10_0402_5%

Title

Size Document Number Rev

Custom

Date: Sheet

R11

1 2

0_0402_5%@

1 2

0_0402_5%@R60_0402_5%@ 0_0402_5%

0_0402_5%

PV:change PROCHOT# & delete Q2

+CPU_CORE_NB

0718 AMD --> 1K ohm

1 2

R22 1K_0402_5%R22 1K_0402_5%

1 2

R23 1K_0402_5%R23 1K_0402_5%

1 2

R24 300_0402_5%R24 300_0402_5%

1 2

R26 300_0402_5%R26 300_0402_5% R27 300_0402_5%R27 300_0402_5% R28 300_0402_5%R28 300_0402_5% R29 300_0402_5%R29 300_0402_5% R31 300_0402_5%R31 300_0402_5% R32 300_0402_5%R32 300_0402_5% R33 300_0402_5%R33 300_0402_5% R34 300_0402_5%R34 300_0402_5% R35 300_0402_5%R35 300_0402_5% R49 300_0402_5%R49 300_0402_5%

HDT_RST#

12 12 12 12 12 12 12 12 12

+3VS

Compal Electronics, Inc.

AMD CPU S1G2 CTRL

LA-4092P

NC7SZ08P5X_NL_SC70-5@U1NC7SZ08P5X_NL_SC70-5@

+1.8V

LDT_RST#

ENTRIP2 47 H_THERMTRIP# 27,41

H_PROCHOT# 26

SB_PWRGD 27,41,51

653Thursday, February 21, 2008

0.4

VDD(+CPU_CORE) decoupling.

+CPU_CORE_0

C30

1 1

C30 330U_X_2VM_R6M

330U_X_2VM_R6M

C28

C28 330U_X_2VM_R6M

330U_X_2VM_R6M

Near CPU Socket

+CPU_CORE_0

C32

C32 22U_0805_6.3V6M

22U_0805_6.3V6M

+CPU_CORE_0

C40

0.22U_0603_16V4Z

2 2

C33

C33 22U_0805_6.3V6M

22U_0805_6.3V6M

C41

0.01U_0402_25V4Z

C34

C34 22U_0805_6.3V6M

22U_0805_6.3V6M

C42

C42 180P_0402_50V8J

180P_0402_50V8J

C35

C35 22U_0805_6.3V6M

22U_0805_6.3V6M

Under CPU Socket

VDDIO decoupling.

+1.8V

C46

C46 22U_0805_6.3V6M

22U_0805_6.3V6M

C47

C47 22U_0805_6.3V6M

22U_0805_6.3V6M

C48

0.22U_0603_16V4Z

Under CPU Socket

C49

0.22U_0603_16V4Z

+CPU_CORE_1

C36

C36 22U_0805_6.3V6M

22U_0805_6.3V6M

C50

180P_0402_50V8J

C31

C31 330U_X_2VM_R6M

330U_X_2VM_R6M

+CPU_CORE_1

C51

C51 180P_0402_50V8J

180P_0402_50V8J

C37

C37 22U_0805_6.3V6M

22U_0805_6.3V6M

C43

0.22U_0603_16V4Z

JP1E

G4 H2

J9 J11 J13 J15

K6 K10 K12 K14

L4 L7

L9 L11 L13 L15

M2 M6 M8

M10

N7 N9

N11

K16

M16

P16 T16 V16

H25

J17 K18 K21 K23 K25 L17

M18 M21 M23 M25 N17

6090022100G_B

Athlon 64 S1 Processor Socket

JP1E

VDD0_1 VDD0_2 VDD0_3 VDD0_4 VDD0_5 VDD0_6 VDD0_7 VDD0_8 VDD0_9 VDD0_10 VDD0_11 VDD0_12 VDD0_13 VDD0_14 VDD0_15 VDD0_16 VDD0_17 VDD0_18 VDD0_19 VDD0_20 VDD0_21 VDD0_22 VDD0_23

VDDNB_1 VDDNB_2 VDDNB_3 VDDNB_4 VDDNB_5

VDDIO1 VDDIO2 VDDIO3 VDDIO4 VDDIO5 VDDIO6 VDDIO7 VDDIO8 VDDIO9 VDDIO10 VDDIO11 VDDIO12

C29

C29 330U_X_2VM_R6M

330U_X_2VM_R6M

C38

C38 22U_0805_6.3V6M

22U_0805_6.3V6M

C44

0.01U_0402_25V4Z

C39

C39 22U_0805_6.3V6M

22U_0805_6.3V6M

C45

C45 180P_0402_50V8J

180P_0402_50V8J

+CPU_CORE_0

+CPU_CORE_NB

+1.8V

+CPU_CORE_NB decoupling.

+CPU_CORE_NB

C52

C52 22U_0805_6.3V6M

22U_0805_6.3V6M

C53

C53 22U_0805_6.3V6M

22U_0805_6.3V6M

SI2: reserve 22u

C54

C54 22U_0805_6.3V6M@

22U_0805_6.3V6M@

VDD1_1 VDD1_2 VDD1_3 VDD1_4 VDD1_5 VDD1_6 VDD1_7 VDD1_8

VDD1_9 VDD1_10 VDD1_11 VDD1_12 VDD1_13 VDD1_14 VDD1_15 VDD1_16 VDD1_17 VDD1_18 VDD1_19 VDD1_20 VDD1_21 VDD1_22 VDD1_23 VDD1_24 VDD1_25 VDD1_26

VDDIO27 VDDIO26 VDDIO25 VDDIO24 VDDIO23 VDDIO22 VDDIO21 VDDIO20 VDDIO19 VDDIO18 VDDIO17 VDDIO16 VDDIO15 VDDIO14 VDDIO13

JP1F

AA4

P8 P10 R4 R7 R9 R11 T2 T6 T8 T10 T12 T14 U7 U9 U11 U13 U15 V6 V8 V10 V12 V14 W4 Y2 AC4 AD2

Y25 V25 V23 V21 V18 U17 T25 T23 T21 T18 R17 P25 P23 P21 P18

+CPU_CORE_1

+1.8V

AA11 AA13 AA15 AA17 AA19

AB23 AB25 AC11 AC13 AC15 AC17 AC19 AC21

AD25 AE11 AE13 AE15 AE17 AE19 AE21 AE23

AB2 AB7 AB9

AD6 AD8

B4 B6 B8

B9 B11 B13 B15 B17 B19 B21 B23 B25

D6 D8

D9 D11 D13 D15 D17 D19 D21 D23 D25

F2 F11 F13 F15 F17 F19 F21 F23 F25

H9 H21 H23

VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 VSS42 VSS43 VSS44 VSS45 VSS46 VSS47 VSS48 VSS49 VSS50 VSS51 VSS52 VSS53 VSS54 VSS55 VSS56 VSS57 VSS58 VSS59 VSS60 VSS61 VSS62 VSS63 VSS64 VSS65

6090022100G_B

Athlon 64 S1 Processor Socket

VSS66 VSS67 VSS68 VSS69 VSS70 VSS71 VSS72 VSS73 VSS74 VSS75 VSS76 VSS77 VSS78 VSS79 VSS80 VSS81 VSS82 VSS83 VSS84 VSS85 VSS86 VSS87 VSS88 VSS89 VSS90 VSS91 VSS92 VSS93 VSS94 VSS95 VSS96 VSS97 VSS98

VSS99 VSS100 VSS101 VSS102 VSS103 VSS104 VSS105 VSS106 VSS107 VSS108 VSS109 VSS110 VSS111 VSS112 VSS113 VSS114 VSS115 VSS116 VSS117 VSS118 VSS119 VSS120 VSS121 VSS122 VSS123 VSS124 VSS125 VSS126 VSS127 VSS128 VSS129

J6 J8 J10 J12 J14 J16 J18 K2 K7 K9 K11 K13 K15 K17 L6 L8 L10 L12 L14 L16 L18 M7 M9 AC6 M17 N4 N8 N10 N16 N18 P2 P7 P9 P11 P17 R8 R10 R16 R18 T7 T9 T11 T13 T15 T17 U4 U6 U8 U10 U12 U14 U16 U18 V2 V7 V9 V11 V13 V15 V17 W6 Y21 Y23 N6

3 3

4 4

+1.8V

C55

0.22U_0603_16V4Z

+1.8V +1.8V

C60

0.01U_0402_25V4Z

+1.8V

Between CPU Socket and DIMM

C57

0.22U_0603_16V4Z

180PF Qt'y follow the distance between CPU socket and DIMM0. <2.5inch>

C62

C62 180P_0402_50V8J

180P_0402_50V8J

C76

4.7U_0805_10V4Z

C74

4.7U_0805_10V4Z

C56

0.22U_0603_16V4Z

C61

0.01U_0402_25V4Z

C75

4.7U_0805_10V4Z

C58

0.22U_0603_16V4Z

C63

C63 180P_0402_50V8J

180P_0402_50V8J

A: Add C165 and C176 to follow AMD Layout review recommand for EMI

C77

4.7U_0805_10V4Z

C64

C64 180P_0402_50V8J

180P_0402_50V8J

C: Change to NBO CAP

C78

C78 220U_Y_4VM

220U_Y_4VM

C65

C65 180P_0402_50V8J

180P_0402_50V8J

VTT decoupling.

+0.9V

C66

4.7U_0805_10V4Z

+0.9V

C79

4.7U_0805_10V4Z

C67

4.7U_0805_10V4Z

C68

0.22U_0603_16V4Z

Near CPU Socket Right side.

C80

4.7U_0805_10V4Z

C81

0.22U_0603_16V4Z

+0.9V

Near Power Supply

C: Change to NBO CAP

C59

C59 220U_Y_4VM

220U_Y_4VM

C69

0.22U_0603_16V4Z

C82

0.22U_0603_16V4Z

C70

C70 1000P_0402_25V8J

1000P_0402_25V8J

C83

C83 1000P_0402_25V8J

1000P_0402_25V8J

C71

C71 1000P_0402_25V8J

1000P_0402_25V8J

C84

C84 1000P_0402_25V8J

1000P_0402_25V8J

C72

C72 180P_0402_50V8J

180P_0402_50V8J

C85

C85 180P_0402_50V8J

180P_0402_50V8J

C73

C73 180P_0402_50V8J

180P_0402_50V8J

C86

C86 180P_0402_50V8J

180P_0402_50V8J

Near CPU Socket Left side.

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2007/08/02 2008/08/02

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

AMD CPU S1G2 PWR & GND

LA-4092P

753Thursday, February 21, 2008

0.4

+V_DDR_MCH_REF

JP4

VREF

DDR_A_D0 DDR_A_D1

DDR_A_DQS#0

1 1

2 2

3 3

4 4

DDR_CKE0_DIMMA5

DDR_A_BS#25

DDR_A_BS#05 DDR_A_WE#5

DDR_A_CAS#5 DDR_CS1_DIMMA#5

DDR_A_ODT15

SMB_CK_DAT09,22,27,35 SMB_CK_CLK09,22,27,35

+3VS

DDR_A_DQS0 DDR_A_D2

DDR_A_D3 DDR_A_D8

DDR_A_D9 DDR_A_DQS#1

DDR_A_DQS1 DDR_A_D10

DDR_A_D11

DDR_A_D16 DDR_A_D20 DDR_A_D17

DDR_A_DQS#2 DDR_A_DQS2

DDR_A_D18 DDR_A_D19

DDR_A_D24 DDR_A_D25

DDR_A_DM3

DDR_A_D26 DDR_A_D27

DDR_CKE0_DIMMA

DDR_A_BS#2 DDR_A_MA12

DDR_A_MA9 DDR_A_MA8

DDR_A_MA5 DDR_A_MA3 DDR_A_MA1 DDR_A_MA0

DDR_A_MA10 DDR_A_BS#0 DDR_A_WE#

DDR_A_CAS# DDR_A_ODT0 DDR_CS1_DIMMA#

DDR_A_ODT1 DDR_A_D32

DDR_A_D33 DDR_A_DQS#4

DDR_A_DQS4 DDR_A_D34

DDR_A_D35 DDR_A_D40

DDR_A_D41 DDR_A_DM5 DDR_A_D42

DDR_A_D43 DDR_A_D48

DDR_A_D49

DDR_A_DQS#6 DDR_A_DQS6

DDR_A_D50 DDR_A_D51

DDR_A_D56 DDR_A_D57

DDR_A_DM7 DDR_A_D58

DDR_A_D59

C103

0.1U_0402_16V4Z

VSS

DQ0

DQ1

VSS

DQS0#

DQS0

VSS

DQ2

DQ3

VSS

DQ8

DQ9

VSS

DQS1#

DQS1

VSS

DQ10

DQ11

VSS

DQ16

DQ17

VSS

DQS2#

DQS2

VSS

DQ18

DQ19

VSS

DQ24

DQ25

VSS

DM3

VSS

DQ26

DQ27

VSS

CKE0

VDD

BA2

VDD

A12

VDD

101

103

VDD

105

A10/AP

107

BA0

109

WE#

111

VDD

113

CAS#

115

NC/S1#

117

VDD

119

NC/ODT1

121

VSS

123

DQ32

125

DQ33

127

VSS

129

DQS4#

131

DQS4

133

VSS

135

DQ34

137

DQ35

139

VSS

141

DQ40

143

DQ41

145

VSS

147

DM5

149

VSS

151

DQ42

153

DQ43

155

VSS

157

DQ48

159

DQ49

161

VSS

163

NC,TEST

165

VSS

167

DQS6#

169

DQS6

171

VSS

173

DQ50

175

DQ51

177

VSS

179

DQ56

181

DQ57

183

VSS

185

DM7

187

VSS

189

DQ58

191

DQ59

193

VSS

195

SDA

197

SCL

199

VDDSPD

P-TWO_A5692B-A0G16-P

CONN@

DQ12 DQ13

CK0#

DQ14 DQ15

DQ20 DQ21

DQ22 DQ23

DQ28 DQ29

DQS3#

DQS3 DQ30

DQ31

NC/CKE1

NC/A15 NC/A14

RAS#

ODT0

NC/A13

DQ36 DQ37

DQ38 DQ39

DQ44 DQ45

DQS5#

DQS5 DQ46

DQ47 DQ52

DQ53

CK1#

DQ54 DQ55

DQ60 DQ61

DQS7#

DQS7 DQ62

DQ63

DQ4 DQ5

DM0 DQ6

DQ7

DM1

DM2

VDD

DM4

DM6

SAO

VSS

VSS VSS

VSS

VSS VSS

CK0 VSS

VSS

A11

BA1 S0#

VSS

VSS VSS

VSS

VSS CK1

VSS VSS

VSS

VSS SA1

+1.8V+1.8V

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40

42 44 46 48 50

52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92

96 98

100

102

104 106 108 110 112 114 116 118 120

122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200

DDR_A_D4 DDR_A_D5

DDR_A_DM0 DDR_A_D6

DDR_A_D7 DDR_A_D12

DDR_A_D13 DDR_A_DM1

DDR_A_D14 DDR_A_D15

DDR_A_D21

DDR_A_DM2 DDR_A_D22

DDR_A_D23 DDR_A_D28

DDR_A_D29 DDR_A_DQS#3

DDR_A_DQS3 DDR_A_D30

DDR_A_D31 DDR_CKE1_DIMMA DDR_A_MA15

DDR_A_MA14 DDR_A_MA11

DDR_A_MA7 DDR_A_MA6

DDR_A_MA4 DDR_A_MA2

DDR_A_BS#1 DDR_A_RAS# DDR_CS0_DIMMA#

DDR_A_MA13

DDR_A_D36 DDR_A_D37

DDR_A_DM4 DDR_A_D38

DDR_A_D39 DDR_A_D44

DDR_A_D45 DDR_A_DQS#5

DDR_A_DQS5 DDR_A_D46

DDR_A_D47 DDR_A_D52

DDR_A_D53

DDR_A_DM6 DDR_A_D54

DDR_A_D55 DDR_A_D60

DDR_A_D61 DDR_A_DQS#7

DDR_A_DQS7 DDR_A_D62

DDR_A_D63

DDR_A_D[0..63]

DDR_A_DM[0..7] DDR_A_DQS[0..7] DDR_A_MA[0..15]

DDR_A_DQS#[0..7]

DDR_A_CLK0 5 DDR_A_CLK#0 5

+V_DDR_MCH_REF

C95

DDR_CKE1_DIMMA 5

DDR_A_BS#1 5 DDR_A_RAS# 5 DDR_CS0_DIMMA# 5

DDR_A_ODT0 5

DDR_A_CLK1 5 DDR_A_CLK#1 5

DDR_A_D[0..63] 5

DDR_A_DM[0..7] 5

DDR_A_DQS[0..7] 5

DDR_A_MA[0..15] 5

DDR_A_DQS#[0..7] 5

+1.8V

R43

R43 1K_0402_1%

1K_0402_1%

1 2

C96

1 2

0.1U_0402_16V4Z

1000P_0402_25V8J

R44

R44 1K_0402_1%

1K_0402_1%

+V_DDR_MCH_REF 9

DDR_A_MA6 DDR_A_MA7 DDR_A_MA11 DDR_A_MA14

DDR_CKE0_DIMMA DDR_A_BS#2 DDR_A_MA15 DDR_CKE1_DIMMA

DDR_A_MA0 DDR_A_BS#1 DDR_A_MA2 DDR_A_MA4

DDR_A_MA5 DDR_A_MA8 DDR_A_MA9 DDR_A_MA12

DDR_A_BS#0 DDR_A_MA1 DDR_A_MA10 DDR_A_MA3

DDR_CS1_DIMMA# DDR_A_ODT1 DDR_A_WE# DDR_A_CAS#

DDR_A_ODT0 DDR_A_MA13 DDR_A_RAS# DDR_CS0_DIMMA#

RP1

1 8 2 7 3 6 4 5

47_0804_8P4R_5%

RP2

47_0804_8P4R_5%

RP3

1 8 2 7 3 6 4 5

47_0804_8P4R_5%

RP4

47_0804_8P4R_5%

RP5

47_0804_8P4R_5%

RP6

47_0804_8P4R_5%

RP7

1 8 2 7 3 6 4 5

47_0804_8P4R_5%

+0.9V

1 2

C87 0.1U_0402_16V4Z

1 2

C88 0.1U_0402_16V4Z

1 2

C90 0.1U_0402_16V4Z

1 2

C89 0.1U_0402_16V4Z

1 2

C91 0.1U_0402_16V4Z

1 2

C92 0.1U_0402_16V4Z

1 2

C93 0.1U_0402_16V4Z

1 2

C94 0.1U_0402_16V4Z

1 2

C98 0.1U_0402_16V4Z

1 2

C97 0.1U_0402_16V4Z

1 2

C100 0.1U_0402_16V4Z

1 2

C99 0.1U_0402_16V4Z

1 2

C102 0.1U_0402_16V4Z

1 2

C101 0.1U_0402_16V4Z

+1.8V

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2007/08/02 2008/08/02

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

DDRII SO-DIMM 0

LA-4092P

853Thursday, February 21, 2008

0.4

+1.8V

+V_DDR_MCH_REF8

1 1

2 2

3 3

4 4

DDR_CKE0_DIMMB5

DDR_B_BS#25

DDR_B_BS#05 DDR_B_WE#5

DDR_B_CAS#5 DDR_CS1_DIMMB#5

DDR_B_ODT15

SMB_CK_DAT08,22,27,35 SMB_CK_CLK08,22,27,35

DDR_B_D0 DDR_B_D1

DDR_B_DQS#0 DDR_B_DQS0

C104

DDR_B_D2 DDR_B_D3

DDR_B_D8

1000P_0402_25V8J

DDR_B_D9 DDR_B_DQS#1

DDR_B_DQS1 DDR_B_D10

DDR_B_D11

DDR_B_D16 DDR_B_D17

DDR_B_DQS#2 DDR_B_DQS2

DDR_B_D18 DDR_B_D22 DDR_B_D19

DDR_B_D24 DDR_B_D25

DDR_B_DM3

DDR_B_D26 DDR_B_D27

DDR_CKE0_DIMMB

DDR_B_BS#2 DDR_B_MA12

DDR_B_MA9

DDR_B_MA5 DDR_B_MA3 DDR_B_MA1

DDR_B_MA10 DDR_B_BS#0 DDR_B_WE#

DDR_B_CAS# DDR_B_ODT0 DDR_CS1_DIMMB#

DDR_B_ODT1 DDR_B_D32

DDR_B_D33 DDR_B_DQS#4

DDR_B_DQS4 DDR_B_D34

DDR_B_D35 DDR_B_D40

DDR_B_D41 DDR_B_DM5 DDR_B_D42

DDR_B_D43 DDR_B_D47 DDR_B_D48

DDR_B_D49 DDR_B_D53

DDR_B_DQS#6 DDR_B_DQS6

DDR_B_D50 DDR_B_D51 DDR_B_D55

DDR_B_D56 DDR_B_D57

DDR_B_DM7 DDR_B_D58

DDR_B_D59

+3VS

0.1U_0402_16V4Z

C119

JP5

VREF

VSS

DQ0

DQ1

VSS

DQS0#

DQS0

VSS

DQ2

DQ3

VSS

DQ8

DQ9

VSS

DQS1#

DQS1

VSS

DQ10

DQ11

VSS

DQ16

DQ17

VSS

DQS2#

DQS2

VSS

DQ18

DQ19

VSS

DQ24

DQ25

VSS

DM3

VSS

DQ26

DQ27

VSS

CKE0

VDD

BA2

VDD

A12

VDD

101

103

VDD

105

A10/AP

107

BA0

109

WE#

111

VDD

113

CAS#

115

NC/S1#

117

VDD

119

NC/ODT1

121

VSS

123

DQ32

125

DQ33

127

VSS

129

DQS4#

131

DQS4

133

VSS

135

DQ34

137

DQ35

139

VSS

141

DQ40

143

DQ41

145

VSS

147

DM5

149

VSS

151

DQ42

153

DQ43

155

VSS

157

DQ48

159

DQ49

161

VSS

163

NC,TEST

165

VSS

167

DQS6#

169

DQS6

171

VSS

173

DQ50

175

DQ51

177

VSS

179

DQ56

181

DQ57

183

VSS

185

DM7

187

VSS

189

DQ58

191

DQ59

193

VSS

195

SDA

197

SCL

199

VDDSPD

PTI_A5652D-A0G16-P

CONN@

DQ4 DQ5 VSS DM0 VSS DQ6 DQ7

VSS DQ12 DQ13

VSS

DM1

VSS

CK0

CK0#

VSS DQ14 DQ15

VSS

VSS DQ20 DQ21

VSS

DM2

VSS DQ22 DQ23

VSS DQ28 DQ29

VSS

DQS3#

DQS3

VSS DQ30 DQ31

VSS

NC/CKE1

VDD

NC/A15 NC/A14

VDD

RAS#

VDD ODT0

NC/A13

VDD

VSS DQ36 DQ37

VSS

DM4

VSS DQ38 DQ39

VSS DQ44 DQ45

VSS

DQS5#

DQS5

VSS DQ46 DQ47

VSS DQ52 DQ53

VSS

CK1

CK1#

VSS

DM6

VSS DQ54 DQ55

VSS DQ60 DQ61

VSS

DQS7#

DQS7

VSS DQ62 DQ63

VSS

SAO

VSS

A11

BA1 S0#

SA1

A7 A6

A4 A2 A0

+1.8V

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40

42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200

DDR_B_D4 DDR_B_D5

DDR_B_DM0 DDR_B_D6

DDR_B_D7 DDR_B_D12

DDR_B_D13 DDR_B_DM1

DDR_B_D14 DDR_B_D15

DDR_B_D20 DDR_B_D21

DDR_B_DM2

DDR_B_D23 DDR_B_D28

DDR_B_D29 DDR_B_DQS#3

DDR_B_DQS3 DDR_B_D30

DDR_B_D31 DDR_CKE1_DIMMB DDR_B_MA15

DDR_B_MA14 DDR_B_MA11

DDR_B_MA7 DDR_B_MA6DDR_B_MA8

DDR_B_MA4 DDR_B_MA2 DDR_B_MA0

DDR_B_BS#1 DDR_B_RAS# DDR_CS0_DIMMB#

DDR_B_MA13

DDR_B_D36 DDR_B_D37

DDR_B_DM4 DDR_B_D38

DDR_B_D39 DDR_B_D44

DDR_B_D45 DDR_B_DQS#5

DDR_B_DQS5 DDR_B_D46

DDR_B_D52

DDR_B_DM6 DDR_B_D54

DDR_B_D60 DDR_B_D61

DDR_B_DQS#7 DDR_B_DQS7

DDR_B_D62 DDR_B_D63

+3VS

DDR_B_D[0..63]

DDR_B_DM[0..7] DDR_B_DQS[0..7] DDR_B_MA[0..15]

DDR_B_DQS#[0..7]

DDR_B_CLK0 5 DDR_B_CLK#0 5

DDR_CKE1_DIMMB 5

DDR_B_BS#1 5 DDR_B_RAS# 5 DDR_CS0_DIMMB# 5

DDR_B_ODT0 5

DDR_B_CLK1 5 DDR_B_CLK#1 5

DDR_B_D[0..63] 5

DDR_B_DM[0..7] 5

DDR_B_DQS[0..7] 5

DDR_B_MA[0..15] 5

DDR_B_DQS#[0..7] 5

DDR_B_BS#1 DDR_B_MA2 DDR_B_MA0 DDR_B_MA6

DDR_B_MA4 DDR_B_MA14 DDR_B_MA7 DDR_B_MA11

DDR_B_BS#2 DDR_CKE0_DIMMB DDR_CKE1_DIMMB DDR_B_MA15

DDR_B_MA5 DDR_B_MA8 DDR_B_MA9 DDR_B_MA12

DDR_B_BS#0 DDR_B_MA10 DDR_B_MA3 DDR_B_MA1

DDR_B_ODT1 DDR_CS1_DIMMB# DDR_B_CAS# DDR_B_WE#

DDR_B_MA13 DDR_B_ODT0 DDR_B_RAS# DDR_CS0_DIMMB#

1 8 2 7 3 6 4 5

47_0804_8P4R_5%

1 8 2 7 3 6 4 5

47_0804_8P4R_5%

1 8 2 7 3 6 4 5

47_0804_8P4R_5%

RP10

RP11

RP12

RP13

RP8

RP9

RP14

+0.9V

C105 0.1U_0402_16V4Z

1 2

C106 0.1U_0402_16V4Z

C108 0.1U_0402_16V4Z

1 2

C107 0.1U_0402_16V4Z

C109 0.1U_0402_16V4Z

1 2

C110 0.1U_0402_16V4Z

C111 0.1U_0402_16V4Z

1 2

C112 0.1U_0402_16V4Z

C114 0.1U_0402_16V4Z

1 2

C113 0.1U_0402_16V4Z

C116 0.1U_0402_16V4Z

27 36

1 2

C115 0.1U_0402_16V4Z

C118 0.1U_0402_16V4Z

1 2

C117 0.1U_0402_16V4Z

+1.8V

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2007/08/02 2008/08/02

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

DDRII SO-DIMM 1

LA-4092P

953Thursday, February 21, 2008

0.4

1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2

SB_TX0P 26 SB_TX0N 26 SB_TX1P 26 SB_TX1N 26 SB_TX2P 26 SB_TX2N 26 SB_TX3P 26 SB_TX3N 26

PCIE_MTX_C_GRX_P[0..15]

PCIE_MTX_C_GRX_N[0..15]

PCIE_ITX_C_PRX_P0 33 PCIE_ITX_C_PRX_N0 33 PCIE_ITX_C_PRX_P1 34 PCIE_ITX_C_PRX_N1 34 PCIE_ITX_C_PRX_P2 33 PCIE_ITX_C_PRX_N2 33 PCIE_ITX_C_PRX_P3 32 PCIE_ITX_C_PRX_N3 32

PCIE_ITX_C_PRX_P5 33 PCIE_ITX_C_PRX_N5 33

PCIE_MTX_C_GRX_P[0..15] 15 PCIE_MTX_C_GRX_N[0..15] 15

PCIE_MTX_C_GRX_P0PCIE_MTX_GRX_P0 PCIE_MTX_C_GRX_N0 PCIE_MTX_C_GRX_P1 PCIE_MTX_C_GRX_N1PCIE_MTX_GRX_N1 PCIE_MTX_C_GRX_P2 PCIE_MTX_C_GRX_N2 PCIE_MTX_C_GRX_N3 PCIE_MTX_C_GRX_P3PCIE_MTX_GRX_N3 PCIE_MTX_C_GRX_P4 PCIE_MTX_C_GRX_N4 PCIE_MTX_C_GRX_P5 PCIE_MTX_C_GRX_N5PCIE_MTX_GRX_N5 PCIE_MTX_C_GRX_N6 PCIE_MTX_C_GRX_P6PCIE_MTX_GRX_N6 PCIE_MTX_C_GRX_N7 PCIE_MTX_C_GRX_P7PCIE_MTX_GRX_N7 PCIE_MTX_C_GRX_P8 PCIE_MTX_C_GRX_N8PCIE_MTX_GRX_N8 PCIE_MTX_C_GRX_P9 PCIE_MTX_C_GRX_N9 PCIE_MTX_C_GRX_P10PCIE_MTX_GRX_P10 PCIE_MTX_C_GRX_N10 PCIE_MTX_C_GRX_P11 PCIE_MTX_C_GRX_N11 PCIE_MTX_C_GRX_N12 PCIE_MTX_C_GRX_P12 PCIE_MTX_C_GRX_P13 PCIE_MTX_C_GRX_N13PCIE_MTX_GRX_N13 PCIE_MTX_C_GRX_P14 PCIE_MTX_C_GRX_N14 PCIE_MTX_C_GRX_P15 PCIE_MTX_C_GRX_N15PCIE_MTX_GRX_N15

New Card Cardreader

WLAN GLAN

TV Tuner

H_CLKOP04 H_CLKON04 H_CLKOP14 H_CLKON14

H_CTLOP04

H_CTLON04 H_CTLON14

R57 301_0402_1%R57 301_0402_1%

1 2

0718 Place within 1" layout 1:2

Polarity inversion

H_CADOP[0..15]4 H_CADON[0..15]4 H_CADIN[0..15] 4

H_CADOP0 H_CADON0 H_CADOP1 H_CADON1 H_CADOP2 H_CADON2 H_CADOP3 H_CADON3 H_CADOP4 H_CADON4 H_CADOP5 H_CADON5 H_CADOP6 H_CADON6 H_CADOP7 H_CADON7

H_CADOP8 H_CADON8 H_CADOP9

H_CADON9 H_CADOP10 H_CADON10 H_CADOP11 H_CADON11 H_CADOP12 H_CADON12 H_CADOP13 H_CADON13 H_CADOP14 H_CADON14 H_CADOP15 H_CADON15

H_CTLOP0 H_CTLON0 H_CTLOP1 H_CTLON1

H_CADON[0..15]

U3A

Y25

HT_RXCAD0P

Y24

HT_RXCAD0N

V22

HT_RXCAD1P

V23

HT_RXCAD1N

V25

HT_RXCAD2P

V24

HT_RXCAD2N

U24

HT_RXCAD3P

U25

HT_RXCAD3N

T25

HT_RXCAD4P

T24

HT_RXCAD4N

P22

HT_RXCAD5P

P23

HT_RXCAD5N

P25

HT_RXCAD6P

P24

HT_RXCAD6N

N24

HT_RXCAD7P

N25

HT_RXCAD7N

AC24

HT_RXCAD8P

AC25

HT_RXCAD8N

AB25

HT_RXCAD9P

AB24

HT_RXCAD9N

AA24

HT_RXCAD10P

AA25

HT_RXCAD10N

Y22

HT_RXCAD11P

Y23

HT_RXCAD11N

W21

HT_RXCAD12P

W20

HT_RXCAD12N

V21

HT_RXCAD13P

V20

HT_RXCAD13N

U20

HT_RXCAD14P

U21

HT_RXCAD14N

U19

HT_RXCAD15P

U18

HT_RXCAD15N

T22

HT_RXCLK0P

T23

HT_RXCLK0N

AB23

HT_RXCLK1P

AA22

HT_RXCLK1N

M22

HT_RXCTL0P

M23

HT_RXCTL0N

R21

HT_RXCTL1P

R20

HT_RXCTL1N

C23

HT_RXCALP

A24

HT_RXCALN

RS780M_FCBGA528

H_CADIP[0..15]H_CADOP[0..15] H_CADIN[0..15]

PART 1 OF 6

HT_TXCAD0P HT_TXCAD0N HT_TXCAD1P HT_TXCAD1N HT_TXCAD2P HT_TXCAD2N HT_TXCAD3P HT_TXCAD3N HT_TXCAD4P HT_TXCAD4N HT_TXCAD5P HT_TXCAD5N HT_TXCAD6P HT_TXCAD6N HT_TXCAD7P HT_TXCAD7N

HT_TXCAD8P HT_TXCAD8N HT_TXCAD9P

HT_TXCAD9N HT_TXCAD10P HT_TXCAD10N HT_TXCAD11P HT_TXCAD11N HT_TXCAD12P HT_TXCAD12N HT_TXCAD13P HT_TXCAD13N HT_TXCAD14P HT_TXCAD14N HT_TXCAD15P HT_TXCAD15N

HT_TXCLK0P

HT_TXCLK0N

HT_TXCLK1P

HT_TXCLK1N

HYPER TRANSPORT CPU I/F

HT_TXCTL0P

HT_TXCTL0N

HT_TXCTL1P

HT_TXCTL1N

HT_TXCALP HT_TXCALN

H_CADIP[0..15] 4

H_CADIP0

D24

H_CADIN0

D25

H_CADIP1

E24

H_CADIN1

E25

H_CADIP2

F24

H_CADIN2

F25

H_CADIP3

F23

H_CADIN3

F22

H_CADIP4

H23

H_CADIN4

H22

H_CADIP5

J25

H_CADIN5

J24

H_CADIP6

K24

H_CADIN6

K25

H_CADIP7

K23

H_CADIN7

K22

H_CADIP8

F21

H_CADIN8

G21

H_CADIP9

G20

H_CADIN9

H21

H_CADIP10

J20

H_CADIN10

J21

H_CADIP11

J18

H_CADIN11

K17

H_CADIP12

L19

H_CADIN12

J19

H_CADIP13

M19

H_CADIN13

L18

H_CADIP14

M21

H_CADIN14

P21

H_CADIP15

P18

H_CADIN15

M18 H24

H25 L21 L20

H_CTLIP0

M24

H_CTLIN0

M25

H_CTLIP1

P19

H_CTLIN1

R18 B24

B25

0718 Place within 1" layout 1:2

H_CLKIP0 4 H_CLKIN0 4 H_CLKIP1 4 H_CLKIN1 4

H_CTLIP0 4

H_CTLIN0 4

H_CTLIP1 4H_CTLOP14

H_CTLIN1 4

R58 301_0402_1%R58 301_0402_1%

1 2

PCIE_GTX_C_MRX_P[0..15]15 PCIE_GTX_C_MRX_N[0..15]15

U3B

PCIE_GTX_C_MRX_P0 PCIE_GTX_C_MRX_N0 PCIE_GTX_C_MRX_N1

1 1

PCIE_PTX_C_IRX_P033 PCIE_PTX_C_IRX_N033

2 2

PCIE_PTX_C_IRX_P134 PCIE_PTX_C_IRX_N134 PCIE_PTX_C_IRX_P233 PCIE_PTX_C_IRX_N233 PCIE_PTX_C_IRX_P332 PCIE_PTX_C_IRX_N332

PCIE_PTX_C_IRX_P533 PCIE_PTX_C_IRX_N533

PCIE_GTX_C_MRX_P1 PCIE_GTX_C_MRX_P2 PCIE_GTX_C_MRX_N2 PCIE_GTX_C_MRX_P3 PCIE_GTX_C_MRX_N3 PCIE_GTX_C_MRX_P4 PCIE_GTX_C_MRX_N4 PCIE_GTX_C_MRX_P5 PCIE_GTX_C_MRX_N5 PCIE_GTX_C_MRX_N6 PCIE_GTX_C_MRX_P6 PCIE_GTX_C_MRX_P7 PCIE_GTX_C_MRX_N7 PCIE_GTX_C_MRX_P8 PCIE_GTX_C_MRX_N8 PCIE_GTX_C_MRX_P9 PCIE_GTX_C_MRX_N9 PCIE_GTX_C_MRX_P10 PCIE_GTX_C_MRX_N10 PCIE_GTX_C_MRX_P11 PCIE_GTX_C_MRX_N11 PCIE_GTX_C_MRX_P12 PCIE_GTX_C_MRX_N12 PCIE_GTX_C_MRX_P13 PCIE_GTX_C_MRX_N13 PCIE_GTX_C_MRX_P14 PCIE_GTX_C_MRX_N14 PCIE_GTX_C_MRX_P15 PCIE_GTX_C_MRX_N15

SB_RX0P26 SB_RX0N26 SB_RX1P26 SB_RX1N26 SB_RX2P26 SB_RX2N26 SB_RX3P26 SB_RX3N26

U3B

GFX_RX0P

GFX_RX0N

GFX_RX1P

GFX_RX1N

GFX_RX2P

GFX_RX2N

GFX_RX3P

GFX_RX3N

GFX_RX4P

GFX_RX4N

GFX_RX5P

GFX_RX5N

GFX_RX6P

GFX_RX6N

GFX_RX7P

GFX_RX7N

GFX_RX8P

GFX_RX8N

GFX_RX9P

GFX_RX9N

GFX_RX10P

GFX_RX10N

GFX_RX11P

GFX_RX11N

GFX_RX12P

GFX_RX12N

GFX_RX13P

GFX_RX13N

GFX_RX14P

GFX_RX14N

GFX_RX15P

GFX_RX15N

AE3

GPP_RX0P

AD4

GPP_RX0N

AE2

GPP_RX1P

AD3

GPP_RX1N

AD1

GPP_RX2P

AD2

GPP_RX2N

GPP_RX3P

GPP_RX3N

GPP_RX4P

GPP_RX4N

GPP_RX5P

GPP_RX5N

AA8

SB_RX0P

SB_RX0N

AA7

SB_RX1P

SB_RX1N

AA5

SB_RX2P

AA6

SB_RX2N

SB_RX3P

SB_RX3N

RS780M_FCBGA528

PCIE_GTX_C_MRX_P[0..15] PCIE_GTX_C_MRX_N[0..15]

PART 2 OF 6

PCIE I/F GPP

PCIE I/F SB

PCE_CALRP(PCE_BCALRP) PCE_CALRN(PCE_BCALRN)

GFX_TX0P GFX_TX0N GFX_TX1P GFX_TX1N GFX_TX2P GFX_TX2N GFX_TX3P GFX_TX3N GFX_TX4P GFX_TX4N GFX_TX5P GFX_TX5N GFX_TX6P GFX_TX6N GFX_TX7P GFX_TX7N GFX_TX8P GFX_TX8N GFX_TX9P

GFX_TX9N GFX_TX10P GFX_TX10N GFX_TX11P GFX_TX11N GFX_TX12P GFX_TX12N GFX_TX13P GFX_TX13N GFX_TX14P GFX_TX14N GFX_TX15P GFX_TX15N

PCIE I/F GFX

GPP_TX0P

GPP_TX0N

GPP_TX1P

GPP_TX1N

GPP_TX2P

GPP_TX2N

GPP_TX3P

GPP_TX3N

GPP_TX4P

GPP_TX4N

GPP_TX5P

GPP_TX5N

SB_TX0P SB_TX0N SB_TX1P SB_TX1N SB_TX2P SB_TX2N SB_TX3P SB_TX3N

PCIE_MTX_GRX_N0

PCIE_MTX_GRX_P1

A4 B4

PCIE_MTX_GRX_P2

PCIE_MTX_GRX_N2

PCIE_MTX_GRX_P3

D1 D2

PCIE_MTX_GRX_P4

PCIE_MTX_GRX_N4

PCIE_MTX_GRX_P5

F4 F3

PCIE_MTX_GRX_P6

F1 F2

PCIE_MTX_GRX_P7

H4 H3

PCIE_MTX_GRX_P8

H1 H2

PCIE_MTX_GRX_P9

PCIE_MTX_GRX_N9

J1 K4

PCIE_MTX_GRX_N10

PCIE_MTX_GRX_P11

PCIE_MTX_GRX_N11

PCIE_MTX_GRX_P12

PCIE_MTX_GRX_N12

PCIE_MTX_GRX_P13

M1 M2

PCIE_MTX_GRX_P14

PCIE_MTX_GRX_N14

PCIE_MTX_GRX_P15

P1 P2

PCIE_ITX_PRX_P0

AC1

PCIE_ITX_PRX_N0

AC2

PCIE_ITX_PRX_P1

AB4

PCIE_ITX_PRX_N1

AB3

PCIE_ITX_PRX_P2

AA2

PCIE_ITX_PRX_N2

AA1

PCIE_ITX_PRX_P3

PCIE_ITX_PRX_N3

Y2 Y4 Y3

PCIE_ITX_PRX_P5

PCIE_ITX_PRX_N5

SB_TX0P_C

AD7

SB_TX0N_C

AE7

SB_TX1P_C

AE6

SB_TX1N_C

AD6

SB_TX2P_C

AB6

SB_TX2N_C

AC6

SB_TX3P_C

AD5

SB_TX3N_C

AE5 AC8

AB8

C121 0.1U_0402_16V7KC121 0.1U_0402_16V7K

1 2

C123 0.1U_0402_16V7KC123 0.1U_0402_16V7K

1 2

C125 0.1U_0402_16V7KC125 0.1U_0402_16V7K

1 2

C127 0.1U_0402_16V7KC127 0.1U_0402_16V7K

1 2

C129 0.1U_0402_16V7KC129 0.1U_0402_16V7K

1 2

C131 0.1U_0402_16V7KC131 0.1U_0402_16V7K

1 2

C133 0.1U_0402_16V7KC133 0.1U_0402_16V7K

1 2

C135 0.1U_0402_16V7KC135 0.1U_0402_16V7K

1 2

C137 0.1U_0402_16V7KC137 0.1U_0402_16V7K

1 2

C139 0.1U_0402_16V7KC139 0.1U_0402_16V7K

1 2

C141 0.1U_0402_16V7KC141 0.1U_0402_16V7K

1 2

C143 0.1U_0402_16V7KC143 0.1U_0402_16V7K

1 2

C145 0.1U_0402_16V7KC145 0.1U_0402_16V7K

1 2

C147 0.1U_0402_16V7KC147 0.1U_0402_16V7K

1 2

C149 0.1U_0402_16V7KC149 0.1U_0402_16V7K

1 2

C151 0.1U_0402_16V7KC151 0.1U_0402_16V7K

1 2

C152 0.1U_0402_16V7KC152 0.1U_0402_16V7K

1 2

C153 0.1U_0402_16V7KC153 0.1U_0402_16V7K

1 2

C154 0.1U_0402_16V7KC154 0.1U_0402_16V7K

1 2

C155 0.1U_0402_16V7KC155 0.1U_0402_16V7K

1 2

C156 0.1U_0402_16V7KC156 0.1U_0402_16V7K

1 2

C157 0.1U_0402_16V7KC157 0.1U_0402_16V7K

1 2

C158 0.1U_0402_16V7KC158 0.1U_0402_16V7K

1 2

C159 0.1U_0402_16V7KC159 0.1U_0402_16V7K

1 2

C160 0.1U_0402_16V7KC160 0.1U_0402_16V7K

1 2

C161 0.1U_0402_16V7KC161 0.1U_0402_16V7K

1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2

1 2

C162 0.1U_0402_16V7KC162 0.1U_0402_16V7K C163 0.1U_0402_16V7KC163 0.1U_0402_16V7K C164 0.1U_0402_16V7KC164 0.1U_0402_16V7K C165 0.1U_0402_16V7KC165 0.1U_0402_16V7K C166 0.1U_0402_16V7KC166 0.1U_0402_16V7K C168 0.1U_0402_16V7KC168 0.1U_0402_16V7K C169 0.1U_0402_16V7KC169 0.1U_0402_16V7K C167 0.1U_0402_16V7KC167 0.1U_0402_16V7K

R55 1.27K_0402_1%R55 1.27K_0402_1%

1 2

R56 2K_0402_1%R56 2K_0402_1%

1 2

C120 0.1U_0402_16V7KC120 0.1U_0402_16V7K C122 0.1U_0402_16V7KC122 0.1U_0402_16V7K C124 0.1U_0402_16V7KC124 0.1U_0402_16V7K C126 0.1U_0402_16V7KC126 0.1U_0402_16V7K C128 0.1U_0402_16V7KC128 0.1U_0402_16V7K C130 0.1U_0402_16V7KC130 0.1U_0402_16V7K C132 0.1U_0402_16V7KC132 0.1U_0402_16V7K C134 0.1U_0402_16V7KC134 0.1U_0402_16V7K C136 0.1U_0402_16V7KC136 0.1U_0402_16V7K C138 0.1U_0402_16V7KC138 0.1U_0402_16V7K C140 0.1U_0402_16V7KC140 0.1U_0402_16V7K C142 0.1U_0402_16V7KC142 0.1U_0402_16V7K C144 0.1U_0402_16V7KC144 0.1U_0402_16V7K C146 0.1U_0402_16V7KC146 0.1U_0402_16V7K C148 0.1U_0402_16V7KC148 0.1U_0402_16V7K C150 0.1U_0402_16V7KC150 0.1U_0402_16V7K

+1.1VS

RS780M Display Port Support (muxed on GFX)

DP0

3 3

4 4

DP1

GFX_TX0,TX1,TX2 and TX3 AUX0 and HPD0

GFX_TX4,TX5,TX6 and TX7 AUX1 and HPD1

NEED CHECK R68 & R69 WITH AMD

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2007/08/02 2008/08/02

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

RS780-HT/PCIE

LA-4092P

10 53Thursday, February 21, 2008

0.4

1 1

PV: follow check list connect to GND

U3C

RX781GND

R250 0_0402_5%R250 0_0402_5%

RX781GND RX781GND

R249 0_0402_5%R249 0_0402_5%

PV: follow check list connect to GND

+1.8VS

BLM18PG121SN1D_0603

2.2U_0603_6.3V4Z

2 2

+1.8VS

BLM18PG121SN1D_0603

2.2U_0603_6.3V4Z

+1.8VS

1 2

R371 300_0402_5%R371 300_0402_5%

2.2U_0603_6.3V4Z

NB_PWRGD

For SB700 A12 use

3 3

L10

1 2

L11

1 2

+1.1VS

4.7K_0402_5%

+VDDA18HTPLL

C179

+VDDA18PCIEPLL

C180

1 2

R71

1 2

R72

4.7K_0402_5%

UMA_HSYNC14 UMA_VSYNC14

RX781GND

+VDDA18HTPLL

R67 0_0402_5%R67 0_0402_5%

PLT_RST#14,15,26,32,33,34,40,41

NB_OSC_14.318M22

1 2

CLK_SBLINK_BCLK22 CLK_SBLINK_BCLK#22

+VDDA18PCIEPLL

NB_PWRGD27

LDT_STOP#6,26

CPU_LDT_REQ#6,26

CLK_NBHT22 CLK_NBHT#22

NBGFX_CLK22 NBGFX_CLK#22

+3VS

R251 0_0402_5%R251 0_0402_5%

NB_RESET#

NB_PWRGD

R88 10K_0402_5%R88 10K_0402_5%

AUX_CAL14

Strap pin

F12

AVDD1(NC)

E12

AVDD2(NC)

F14

AVDDDI(NC)

G15

AVSSDI(NC)

H15

AVDDQ(NC)

H14

AVSSQ(NC)

E17

C_Pr(DFT_GPIO5)

F17

Y(DFT_GPIO2)

F15

COMP_Pb(DFT_GPIO4)

G18

RED(DFT_GPIO0)

G17

REDb(NC)

E18

GREEN(DFT_GPIO1)

F18

GREENb(NC)

E19

BLUE(DFT_GPIO3)

F19

BLUEb(NC)

A11

DAC_HSYNC(PWM_GPIO4)

B11

DAC_VSYNC(PWM_GPIO6)

DAC_SCL(PCE_RCALRN)

DAC_SDA(PCE_TCALRN)

G14

DAC_RSET(PWM_GPIO1)

A12

PLLVDD(NC)

D14

PLLVDD18(NC)

B12

PLLVSS(NC)

H17

VDDA18HTPLL

VDDA18PCIEPLL1

VDDA18PCIEPLL2

SYSRESETb

A10

POWERGOOD

C10

LDTSTOPb

C12

ALLOW_LDTSTOP

C25

HT_REFCLKP

C24

HT_REFCLKN

E11

REFCLK_P/OSCIN(OSCIN)

F11

REFCLK_N(PWM_GPIO3)

GFX_REFCLKP

GFX_REFCLKN

GPP_REFCLKP

GPP_REFCLKN

GPPSB_REFCLKP(SB_REFCLKP)

GPPSB_REFCLKN(SB_REFCLKN)

I2C_CLK

I2C_DATA

DDC_DATA0/AUX0N(NC)

DDC_CLK0/AUX0P(NC)

DDC_CLK1/AUX1P(NC)

DDC_DATA1/AUX1N(NC)

B10

STRP_DATA

G11

RSVD

AUX_CAL(NC)

RS780M_FCBGA528

PART 3 OF 6

TXOUT_U1P(PCIE_RESET_GPIO3) TXOUT_U1N(PCIE_RESET_GPIO2)

TXOUT_U3P(PCIE_RESET_GPIO5)

CRT/TVOUT

TXCLK_UP(PCIE_RESET_GPIO4)

TXCLK_UN(PCIE_RESET_GPIO1)

LVTM

LVDS_DIGON(PCE_TCALRP)

LVDS_BLON(PCE_RCALRP)

LVDS_ENA_BL(PWM_GPIO2)

CLOCKs PLL PWR

MIS.

SUS_STAT#(PWM_GPIO5)

TXOUT_L0P(NC)

TXOUT_L0N(NC)

TXOUT_L1P(NC)

TXOUT_L1N(NC)

TXOUT_L2P(NC)

TXOUT_L2N(DBG_GPIO0)

TXOUT_L3P(NC)

TXOUT_L3N(DBG_GPIO2)

TXOUT_U0P(NC) TXOUT_U0N(NC)

TXOUT_U2P(NC) TXOUT_U2N(NC)

TXOUT_U3N(NC)

TXCLK_LP(DBG_GPIO1)

TXCLK_LN(DBG_GPIO3)

VDDLTP18(NC) VSSLTP18(NC)

VDDLT18_1(NC) VDDLT18_2(NC) VDDLT33_1(NC) VDDLT33_2(NC)

VSSLT1(VSS) VSSLT2(VSS) VSSLT3(VSS) VSSLT4(VSS) VSSLT5(VSS) VSSLT6(VSS) VSSLT7(VSS)

TMDS_HPD(NC)

THERMALDIODE_P THERMALDIODE_N

HPD(NC)

TESTMODE

A22 B22 A21 B21 B20 A20 A19 B19

B18 A18 A17 B17 D20 D21 D18 D19

B16 A16 D16 D17

PV: follow check list connect to GND

RX781GND

A13 B13

RX781GND

A15 B15 A14 B14

C14 D15 C16 C18 C20 E20 C22

E9 F7 G12

D9 D10

D12 AE8

AD8 D13

1 2

R77 0_0402_5%R77 0_0402_5%

1 2

R80

1.8K_0402_5%

SUS_STAT# 27 SUS_STAT_R# 14

Strap pin

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2007/08/02 2008/08/02

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

RS780 VEDIO/CLK GEN

LA-4092P

11 53Thursday, February 21, 2008

0.4

U3D

PAR 4 OF 6

MEM_A0(NC) MEM_A1(NC) MEM_A2(NC) MEM_A3(NC) MEM_A4(NC) MEM_A5(NC) MEM_A6(NC) MEM_A7(NC) MEM_A8(NC) MEM_A9(NC) MEM_A10(NC) MEM_A11(NC) MEM_A12(NC) MEM_A13(NC)

MEM_BA0(NC) MEM_BA1(NC) MEM_BA2(NC)

MEM_RASb(NC) MEM_CASb(NC) MEM_WEb(NC) MEM_CSb(NC) MEM_CKE(NC) MEM_ODT(NC)

MEM_CKP(NC) MEM_CKN(NC)

MEM_COMPP(NC) MEM_COMPN(NC)

PAR 4 OF 6

MEM_DQ0/DVO_VSYNC(NC) MEM_DQ1/DVO_HSYNC(NC)

MEM_DQ2/DVO_DE(NC) MEM_DQ3/DVO_D0(NC)

MEM_DQ4(NC) MEM_DQ5/DVO_D1(NC) MEM_DQ6/DVO_D2(NC) MEM_DQ7/DVO_D4(NC) MEM_DQ8/DVO_D3(NC) MEM_DQ9/DVO_D5(NC)

MEM_DQ10/DVO_D6(NC) MEM_DQ11/DVO_D7(NC)

MEM_DQ12(NC)

MEM_DQ13/DVO_D9(NC) MEM_DQ14/DVO_D10(NC) MEM_DQ15/DVO_D11(NC)

MEM_DQS0P/DVO_IDCKP(NC) MEM_DQS0N/DVO_IDCKN(NC)

MEM_DQS1P(NC)

MEM_DQS1N(NC)

MEM_DM0(NC)

MEM_DM1/DVO_D8(NC)

SBD_MEM/DVO_I/F

IOPLLVDD18(NC)

IOPLLVDD(NC) IOPLLVSS(NC)

MEM_VREF(NC)

AA18 AA20 AA19 Y19 V17 AA17 AA15 Y15 AC20 AD19 AE22 AC18 AB20 AD22 AC22 AD21

Y17 W18 AD20 AE21

W17 AE19

AE23 AE24

AD23 AE18

+1.8VS +1.1VS

AB12 AE16

V11 AE15 AA12 AB16 AB14 AD14 AD13 AD15 AC16 AE13 AC14

Y14 AD16

AE17 AD17

B B

W12

Y12 AD18 AB13 AB18

V14

V15

W14

AE12 AD12

RS780M_FCBGA528

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2007/08/02 2008/08/02

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Custom Date: Sheet

Date: Sheet

Compal Electronics, Inc.

RS780 SIDE PORT

LA-4092P

12 53Thursday, February 21, 2008

0.4

1 1

+1.1VS

PV:Change C215 from 4.7u to 10u

+1.2V_HT

+1.35VS

FBMA-L11-201209-221LMA30T_0805@

2 2

+1.8VS

3 3

L16

0_0805_5%

L18

0_0805_5%

L19

0_0805_5%

L43

L22

0_0805_5%

4.7U_0805_10V4Z

C209

4.7U_0805_10V4Z

C215

10U_0805_10V4Z

C225

4.7U_0805_10V4Z

C235

C246

4.7U_0805_10V4Z

C206

0.1U_0402_16V4Z

C214

C216

0.1U_0402_16V4Z

C226

0.1U_0402_16V4Z

C236

0.1U_0402_16V4Z

C207

0.1U_0402_16V4Z

C217

0.1U_0402_16V4Z

C227

0.1U_0402_16V4Z

C237

0.1U_0402_16V4Z

1U_0402_6.3V4Z

C208

C228

C238

C218

+1.8VS

C210

0.1U_0402_16V4Z

+VDDHTRX

0.1U_0402_16V4Z

C229

0.1U_0402_16V4Z

C239

0.1U_0402_16V4Z

C251

+VDDHT

+VDDHTTX

+VDDA18PCIE

U3E

J17

K16 L16

M16

P16

R16

T16

H18 G19

F20 E21

D22

B23 A23

AE25 AD24 AC23 AB22 AA21

Y20

W19

V18

U17

T17

R17

P17

M17

J10 P10 K10

M10

L10 W9

T10

R10

Y9 AA9 AB9 AD9 AE9 U10

G9 AE11 AD11

R252

R252 0_0402_5%

0_0402_5%

VDDHT_1

PART 5/6

VDDHT_2 VDDHT_3 VDDHT_4 VDDHT_5 VDDHT_6 VDDHT_7

VDDHTRX_1 VDDHTRX_2 VDDHTRX_3 VDDHTRX_4 VDDHTRX_5 VDDHTRX_6 VDDHTRX_7

VDDHTTX_1 VDDHTTX_2 VDDHTTX_3 VDDHTTX_4 VDDHTTX_5 VDDHTTX_6 VDDHTTX_7 VDDHTTX_8 VDDHTTX_9 VDDHTTX_10 VDDHTTX_11 VDDHTTX_12 VDDHTTX_13

VDDA18PCIE_1 VDDA18PCIE_2 VDDA18PCIE_3 VDDA18PCIE_4 VDDA18PCIE_5 VDDA18PCIE_6 VDDA18PCIE_7 VDDA18PCIE_8 VDDA18PCIE_9 VDDA18PCIE_10 VDDA18PCIE_11 VDDA18PCIE_12 VDDA18PCIE_13 VDDA18PCIE_14 VDDA18PCIE_15

VDD18_1 VDD18_2 VDD18_MEM1(NC) VDD18_MEM2(NC)

RS780M_FCBGA528

VDDPCIE_1 VDDPCIE_2 VDDPCIE_3 VDDPCIE_4 VDDPCIE_5 VDDPCIE_6 VDDPCIE_7 VDDPCIE_8

VDDPCIE_9 VDDPCIE_10 VDDPCIE_11 VDDPCIE_12 VDDPCIE_13 VDDPCIE_14 VDDPCIE_15 VDDPCIE_16 VDDPCIE_17

VDDC_1 VDDC_2 VDDC_3 VDDC_4 VDDC_5 VDDC_6 VDDC_7 VDDC_8

VDDC_9 VDDC_10 VDDC_11 VDDC_12

POWER

VDDC_13 VDDC_14 VDDC_15 VDDC_16 VDDC_17 VDDC_18 VDDC_19 VDDC_20 VDDC_21 VDDC_22

VDD_MEM1(NC) VDD_MEM2(NC) VDD_MEM3(NC) VDD_MEM4(NC) VDD_MEM5(NC) VDD_MEM6(NC)

VDD33_1(NC) VDD33_2(NC)

VDDA_12=2.5A

A6 B6 C6 D6 E6 F6 G7 H8 J9 K9 M9 L9 P9 R9 T9 V9 U9

K12 J14 U16 J11 K15 M12 L14 L11 M13 M15 N12 N14 P11 P13 P14 R12 R15 T11 T15 U12 T14 J16

AE10 AA11 Y11 AD10 AB10 AC10

H11 H12

L17

1 2

FBMA-L11-201209-221LMA30T_0805

+VDDA11PCIE

FBMA-L11-201209-221LMA30T_0805

10U_0805_10V4Z

1 2 1 2 1 2 1 2

12 12

PJP3

1 2

PAD-OPEN 4x4m

10U_0805_10V4Z 10U_0805_10V4Z

10U_0805_10V4Z

C211

C211 C212

C212

C220 1U_0402_6.3V4ZC220 1U_0402_6.3V4Z C219 1U_0402_6.3V4ZC219 1U_0402_6.3V4Z C222 1U_0402_6.3V4ZC222 1U_0402_6.3V4Z C221 1U_0402_6.3V4ZC221 1U_0402_6.3V4Z C224 0.1U_0402_16V4ZC224 0.1U_0402_16V4Z C223 0.1U_0402_16V4ZC223 0.1U_0402_16V4Z

+1.1VS +NB_VDDC

VDD_CORE=10A

C2300.1U_0402_16V4Z C2300.1U_0402_16V4Z

C2410.1U_0402_16V4Z C2410.1U_0402_16V4Z

C2420.1U_0402_16V4Z C2420.1U_0402_16V4Z

C2430.1U_0402_16V4Z C2430.1U_0402_16V4Z

C2310.1U_0402_16V4Z C2310.1U_0402_16V4Z

C2440.1U_0402_16V4Z C2440.1U_0402_16V4Z

C23310U_0805_10V4Z C23310U_0805_10V4Z

C2320.1U_0402_16V4Z C2320.1U_0402_16V4Z

+3VS

C2400.1U_0402_16V4Z C2400.1U_0402_16V4Z

C2470.1U_0402_16V4Z C2470.1U_0402_16V4Z

U3F

A25

VSSAHT1

D23

VSSAHT2

E22

VSSAHT3

G22

VSSAHT4

G24

VSSAHT5

G25

VSSAHT6

H19

VSSAHT7

J22

VSSAHT8

L17

VSSAHT9

L22

VSSAHT10

L24

VSSAHT11

+1.1VS

330U_D2E_2.5VM

C234

C24510U_0805_10V4Z C24510U_0805_10V4Z

L25

VSSAHT12

M20

VSSAHT13

N22

VSSAHT14

P20

VSSAHT15

R19

VSSAHT16

R22

VSSAHT17

R24

VSSAHT18

R25

VSSAHT19

H20

VSSAHT20

U22

VSSAHT21

V19

VSSAHT22

W22

VSSAHT23

W24

VSSAHT24

W25

VSSAHT25

Y21

VSSAHT26

AD25

VSSAHT27

L12

VSS11

M14

VSS12

N13

VSS13

P12

VSS14

P15

VSS15

R11

VSS16

R14

VSS17

T12

VSS18

U14

VSS19

U11

VSS20

U15

VSS21

V12

VSS22

W11

VSS23

W15

VSS24

AC12

VSS25

AA14

VSS26

Y18

VSS27

AB11

VSS28

AB15

VSS29

AB17

VSS30

AB19

VSS31

AE20

VSS32

AB21

VSS33

K11

VSS34

RS780M_FCBGA528

PART 6/6

GROUND

VSSAPCIE1 VSSAPCIE2 VSSAPCIE3 VSSAPCIE4 VSSAPCIE5 VSSAPCIE6 VSSAPCIE7 VSSAPCIE8

VSSAPCIE9 VSSAPCIE10 VSSAPCIE11 VSSAPCIE12 VSSAPCIE13 VSSAPCIE14 VSSAPCIE15 VSSAPCIE16 VSSAPCIE17 VSSAPCIE18 VSSAPCIE19 VSSAPCIE20 VSSAPCIE21 VSSAPCIE22 VSSAPCIE23 VSSAPCIE24 VSSAPCIE25 VSSAPCIE26 VSSAPCIE27 VSSAPCIE28 VSSAPCIE29 VSSAPCIE30 VSSAPCIE31 VSSAPCIE32 VSSAPCIE33 VSSAPCIE34 VSSAPCIE35 VSSAPCIE36 VSSAPCIE37 VSSAPCIE38 VSSAPCIE39 VSSAPCIE40

VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9

VSS10

A2 B1 D3 D5 E4 G1 G2 G4 H7 J4 R7 L1 L2 L4 L7 M6 N4 P6 R1 R2 R4 V7 U4 V8 V6 W1 W2 W4 W7 W8 Y6 AA4 AB5 AB1 AB7 AC3 AC4 AE1 AE4 AB2

AE14 D11 G8 E14 E15 J15 J12 K14 M11 L15

PV: follow check list connect to GND

+1.8VS

U67

VIN1VCNTL

C903

C903 10U_0805_10V4Z@

10U_0805_10V4Z@

Q56

2N7002_SOT23-3@

4 4

VLDT_EN#44

R601 0_0402_5%@R601 0_0402_5%@

1 2

2N7002_SOT23-3@

C703

0.1U_0402_16V7K@

R599

R599 1K_0402_1%

1K_0402_1%

+VREF1.35V

R600

3K_0402_5%@

GND

VREF

VOUT

G2992F1U_SO8@

C702

C905

10U_0805_10V4Z@

0.1U_0402_16V7K@

+1.35VS

6 5

+3VS

C489

1U_0603_10V6K@

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2007/08/02 2008/08/02

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

RS780 PWR/GND

LA-4092P

13 53Thursday, February 21, 2008

0.4

RS780 DFT_GPIO5 mux at CRT_VSYNC pull high to 3K

SI2: Change to 3K pull high

1 1

UMA_VSYNC11

R101 3K_0402_5%R101 3K_0402_5%

R102 3K_0402_5%@R102 3K_0402_5%@

+3VS

DFT_GPIO5:STRAP_DEBUG_BUS_GPIO_ENABLEb

Enables the Test Debug Bus using GPIO. 1 : Enable (RX780, RS780) 0 : Disable (RX780, RS780) PIN: RS740-->RS780_AUX_CAL; RX780-->NB_TV_C; RS780--> VSYNC#

DFT_GPIO[4:2]: STRAP_PCIE_GPP_CFG[2:0]

These pin straps are used to configure PCI-E GPP mode. 000 : 00001 001 : 00010

RS780 use register to control PCI-E configure

2 2

010 : 01011 011 : 00100 100 : 01010 101 : 01100 111 : 01011

DFT_GPIO1: LOAD_EEPROM_STRAPS

Selects Loading of STRAPS from EPROM 1 : Bypass the loading of EEPROM straps and use Hardware Default Values 0 : I2C Master can load strap values from EEPROM if connected, or use default values if not connected RS740/RX780: DFT_GPIO1 RS780:SUS_STAT

RS780 DFT_GPIO1

AUX_CAL11

SUS_STAT_R#11 PLT_RST# 11,15,26,32,33,34,40,41

1 2

R104 150_0402_1%@R104 150_0402_1%@ D4 CH751H-40PT_SOD323-2@D4 CH751H-40PT_SOD323-2@

2 1

RX780 DFT_GPIO1 mux at GREEN(Ball E18) and change pull low form 150 to 3K.

3 3

4 4

RS780 use HSYNC to enable SIDE PORT (internal pull high)

UMA_HSYNC11

R107 3K_0402_5%@R107 3K_0402_5%@

R125 3K_0402_5%R125 3K_0402_5%

+3VS

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

DFT_GPIO0: STRAP_DEBUG_BUS_PCIE_ENABLEb

RX780: Enables the Test Debug Bus using PCIE bus 1 : Disable ( Can still be enabled using nbcfg register access ) 0 : Enable

RS780: Enables Side port memory ( RS780 use HSYNC#)

1. Disable (RS780) 0 : Enable (RS780)

Compal Secret Data

2007/08/02 2008/08/02

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

RS780 STRAPS

LA-4092P

14 53Thursday, February 21, 2008

0.4

PCIE_GTX_C_MRX_P[0..15]10 PCIE_GTX_C_MRX_N[0..15]10 PCIE_MTX_C_GRX_P[0..15]10 PCIE_MTX_C_GRX_N[0..15]10

D D

PCIE_MTX_C_GRX_P15 PCIE_MTX_C_GRX_N15

PCIE_MTX_C_GRX_P14 PCIE_MTX_C_GRX_N14

PCIE_MTX_C_GRX_P13 PCIE_MTX_C_GRX_N13

PCIE_MTX_C_GRX_P12 PCIE_MTX_C_GRX_N12

PCIE_MTX_C_GRX_P11 PCIE_MTX_C_GRX_N11

PCIE_MTX_C_GRX_P10 PCIE_MTX_C_GRX_N10

PCIE_MTX_C_GRX_P9

C C

B B

CLK_PCIE_VGA22 CLK_PCIE_VGA#22

PCIE_MTX_C_GRX_N9

PCIE_MTX_C_GRX_P8 PCIE_MTX_C_GRX_N8

PCIE_MTX_C_GRX_P7 PCIE_MTX_C_GRX_N7

PCIE_MTX_C_GRX_P6 PCIE_MTX_C_GRX_N6

PCIE_MTX_C_GRX_P5 PCIE_MTX_C_GRX_N5

PCIE_MTX_C_GRX_P4 PCIE_MTX_C_GRX_N4

PCIE_MTX_C_GRX_P3 PCIE_MTX_C_GRX_N3

PCIE_MTX_C_GRX_P2 PCIE_MTX_C_GRX_N2

PCIE_MTX_C_GRX_P1 PCIE_MTX_C_GRX_N1

PCIE_MTX_C_GRX_P0 PCIE_MTX_C_GRX_N0 PEG_M_RXN0

PLT_RST#11,14,26,32,33,34,40,41

U5A

AC30

PCIE_RX0P

AC31

PCIE_RX0N

AC29

PCIE_RX1P

AB29

PCIE_RX1N

AB31

PCIE_RX2P

AB30

PCIE_RX2N

AA31

PCIE_RX3P

AA30

PCIE_RX3N

W30

PCIE_RX4P

W31

PCIE_RX4N

W29

PCIE_RX5P

V29

PCIE_RX5N

V31

PCIE_RX6P

V30

PCIE_RX6N

U31

PCIE_RX7P

U30

PCIE_RX7N

P30

PCIE_RX8P

P31

PCIE_RX8N

P29

PCIE_RX9P

N29

PCIE_RX9N

N31

PCIE_RX10P

N30

PCIE_RX10N

M31

PCIE_RX11P

M30

PCIE_RX11N

K30

PCIE_RX12P

K31

PCIE_RX12N

K29

PCIE_RX13P

J29

PCIE_RX13N

J31

PCIE_RX14P

J30

PCIE_RX14N

H31

PCIE_RX15P

H30

PCIE_RX15N

Clock

AD29

PCIE_REFCLKP

AD30

PCIE_REFCLKN

SM BUS

AC28

NC_SMBCLK

AC27

NC_SMBDATA

AG25

PERSTB

216-0707001-00/M82-S_BGA632

PCIE_GTX_C_MRX_P[0..15] PCIE_GTX_C_MRX_N[0..15] PCIE_MTX_C_GRX_P[0..15] PCIE_MTX_C_GRX_N[0..15]

PART 1 OF 6

P C

C I

E X

X P

P R

R E

E S

S S

I N

N T

T E

E R

R F

F A

A C

C E

PCIE_TX0P PCIE_TX0N

PCIE_TX1P PCIE_TX1N

PCIE_TX2P PCIE_TX2N

PCIE_TX3P PCIE_TX3N

PCIE_TX4P PCIE_TX4N

PCIE_TX5P PCIE_TX5N

PCIE_TX6P PCIE_TX6N

PCIE_TX7P PCIE_TX7N

PCIE_TX8P PCIE_TX8N

PCIE_TX9P PCIE_TX9N

PCIE_TX10P PCIE_TX10N

PCIE_TX11P PCIE_TX11N

PCIE_TX12P PCIE_TX12N

PCIE_TX13P PCIE_TX13N

PCIE_TX14P PCIE_TX14N

PCIE_TX15P PCIE_TX15N

Calibration

PCIE_CALRN PCIE_CALRP

PEG_M_RXP15

AA28

PEG_M_RXN15

AA27

PEG_M_RXP14

AA25

PEG_M_RXN14

AA24

PEG_M_RXP13

Y28

PEG_M_RXN13

Y27

PEG_M_RXP12

Y25

PEG_M_RXN12

Y24

PEG_M_RXP11

V28

PEG_M_RXN11

V27

PEG_M_RXP10

V25

PEG_M_RXN10

V24

PEG_M_RXP9

T28

PEG_M_RXN9 PCIE_GTX_C_MRX_N9

T27

PEG_M_RXP8

T25

PEG_M_RXN8 PCIE_GTX_C_MRX_N8

T24

PEG_M_RXP7

P28

PEG_M_RXN7

P27

PEG_M_RXP6

P25

PEG_M_RXN6

P24

PEG_M_RXP5

M28

PEG_M_RXN5

M27

PEG_M_RXP4 PCIE_GTX_C_MRX_P4

M25

PEG_M_RXN4

M24

PEG_M_RXP3

L28

PEG_M_RXN3

L27

PEG_M_RXP2 PCIE_GTX_C_MRX_P2

L25

PEG_M_RXN2

L24

PEG_M_RXP1 PCIE_GTX_C_MRX_P1

J28

PEG_M_RXN1

J27

PEG_M_RXP0

G28 G27

R108 2K_0402_1%R108 2K_0402_1%

AF25

1 2

R109 1.27K_0402_1%R109 1.27K_0402_1%

AE25

1 2

AE23

AH30

C284 0.1U_0402_16V7KC284 0.1U_0402_16V7K

1 2

C285 0.1U_0402_16V7KC285 0.1U_0402_16V7K

1 2

C282 0.1U_0402_16V7KC282 0.1U_0402_16V7K

1 2

C283 0.1U_0402_16V7KC283 0.1U_0402_16V7K

1 2

C280 0.1U_0402_16V7KC280 0.1U_0402_16V7K

1 2

C281 0.1U_0402_16V7KC281 0.1U_0402_16V7K

1 2

C278 0.1U_0402_16V7KC278 0.1U_0402_16V7K

1 2

C279 0.1U_0402_16V7KC279 0.1U_0402_16V7K

1 2

C276 0.1U_0402_16V7KC276 0.1U_0402_16V7K

1 2

C277 0.1U_0402_16V7KC277 0.1U_0402_16V7K

1 2

C274 0.1U_0402_16V7KC274 0.1U_0402_16V7K

1 2

C275 0.1U_0402_16V7KC275 0.1U_0402_16V7K

1 2

C272 0.1U_0402_16V7KC272 0.1U_0402_16V7K

1 2

C273 0.1U_0402_16V7KC273 0.1U_0402_16V7K

1 2

C270 0.1U_0402_16V7KC270 0.1U_0402_16V7K

1 2

C271 0.1U_0402_16V7KC271 0.1U_0402_16V7K

1 2

C268 0.1U_0402_16V7KC268 0.1U_0402_16V7K

1 2

C269 0.1U_0402_16V7KC269 0.1U_0402_16V7K

1 2

C266 0.1U_0402_16V7KC266 0.1U_0402_16V7K

1 2

C267 0.1U_0402_16V7KC267 0.1U_0402_16V7K

1 2

C264 0.1U_0402_16V7KC264 0.1U_0402_16V7K

1 2

C265 0.1U_0402_16V7KC265 0.1U_0402_16V7K

1 2

C262 0.1U_0402_16V7KC262 0.1U_0402_16V7K

1 2

C263 0.1U_0402_16V7KC263 0.1U_0402_16V7K

1 2

C260 0.1U_0402_16V7KC260 0.1U_0402_16V7K

1 2

C261 0.1U_0402_16V7KC261 0.1U_0402_16V7K

1 2

C258 0.1U_0402_16V7KC258 0.1U_0402_16V7K

1 2

C259 0.1U_0402_16V7KC259 0.1U_0402_16V7K

1 2

C256 0.1U_0402_16V7KC256 0.1U_0402_16V7K

1 2

C257 0.1U_0402_16V7KC257 0.1U_0402_16V7K

1 2

C254 0.1U_0402_16V7KC254 0.1U_0402_16V7K

1 2

C255 0.1U_0402_16V7KC255 0.1U_0402_16V7K

1 2

+1.1VS

PCIE_GTX_C_MRX_P15 PCIE_GTX_C_MRX_N15

PCIE_GTX_C_MRX_P14 PCIE_GTX_C_MRX_N14

PCIE_GTX_C_MRX_P13 PCIE_GTX_C_MRX_N13

PCIE_GTX_C_MRX_P12 PCIE_GTX_C_MRX_N12

PCIE_GTX_C_MRX_P11 PCIE_GTX_C_MRX_N11

PCIE_GTX_C_MRX_P10 PCIE_GTX_C_MRX_N10

PCIE_GTX_C_MRX_P9

PCIE_GTX_C_MRX_P8

PCIE_GTX_C_MRX_P7 PCIE_GTX_C_MRX_N7

PCIE_GTX_C_MRX_P6 PCIE_GTX_C_MRX_N6

PCIE_GTX_C_MRX_P5 PCIE_GTX_C_MRX_N5

PCIE_GTX_C_MRX_N4

PCIE_GTX_C_MRX_P3 PCIE_GTX_C_MRX_N3

PCIE_GTX_C_MRX_N2

PCIE_GTX_C_MRX_N1

PCIE_GTX_C_MRX_P0 PCIE_GTX_C_MRX_N0

PCIE LANE REVERSALPCIE LANE REVERSAL

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2006/09/25 2006/09/25

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

M82-S PCIE interface

LA-4092P

15 53Thursday, February 21, 2008

0.4

BLM18PG121SN1D_0603

+VGA_CORE

D D

+1.8VS

+1.1VS

C C

+1.8VS

R132

R132 499_0402_1%

499_0402_1%

R136

R136 249_0402_1%

249_0402_1%

B B

L23

BLM18PG121SN1D_0603

L26

10U_0603_6.3V6M

BLM18PG121SN1D_0603

+1.8VS

10U_0603_6.3V6M

BLM18PG121SN1D_0603

R115

10U_0603_6.3V6M

+VGA_VREF

R110

C325

0.1U_0402_16V4Z

SI: Per EMI request add SSC chip

Spread spectrum

27M_OUT

R630

0_0402_5%

1 2

27M_CLK 22

A A

1U_0402_6.3V4Z

C294

10U_0603_6.3V6M

0.1U_0402_16V4Z

C299

0.1U_0402_16V4Z

C307

0.1U_0402_16V4Z

C310

ENBKL41

+3.3V_DELAY

VGA_PWRSEL52

27M_SSC22 THM_ALERT#21

SCS#_GPIO2221

REFOUT

XOUT XIN3VDD

ASM3P2872A

0.1U_0402_16V4Z@

VGA input level is 1.8V

22P_0402_50V8J

+MPVDD

C286

C290

C308

C311

0.1U_0402_16V4Z

+DPLL_PVDD

C291

C291 1U_0402_6.3V4Z

1U_0402_6.3V4Z

+PCIE_PVDD

C309

C309 1U_0402_6.3V4Z

1U_0402_6.3V4Z

+DPLL_VDDC

C312

C312 1U_0402_6.3V4Z

1U_0402_6.3V4Z

SI2:unmount R188

R188

+3.3V_DELAY

VSS

27MCLK

@ Y6

GND IN

CV2

R178 33_0402_5%@R178 33_0402_5%@

C462

OUT

GND

1 2

MODOUT

4 1

27MHz_16PF_6P27000126

@ CV2

C287

R120

10K_0402_5%

10K_0402_5%@

1 2

R625 0_0402_5%R625 0_0402_5%

R12710K_0402_5%@ R12710K_0402_5%@

R130 10K_0402_5%R130 10K_0402_5% R131 1K_0402_5%R131 1K_0402_5%

27M_SSC_R

+3VS

C463

C463 1U_0402_6.3V4Z

1U_0402_6.3V4Z

75_0402_1%

27M_OUT

1 2

R177

XTALOUT

3 2

@ CV1

22P_0402_50V8J

VRAM_ID021 VRAM_ID121 VRAM_ID221 VRAM_ID321

SOUT_GPIO821

SIN_GPIO921

SCLK21 GPIO1121 GPIO1221 GPIO1321

VGA_CLKREQ#

12 12

120mA

40mA

230mA

300mA

CV1

PSYNC21

GPIO021 GPIO121

GPIO421 GPIO521 GPIO621

R189

R189 100_0402_5%

100_0402_5%

1 2

1K_0402_5%

27M_SSC_R

VGA_CTF

T35 PADT35 PAD T36 PADT36 PAD T37 PADT37 PAD T38 PADT38 PAD

TMDS_SSCOUT TMDS_CLKIN

+DPLL_PVDD

+PCIE_PVDD

+MPVDD

+DPLL_VDDC

+VGA_VREF

27MCLK

XTALOUT

R142

U5B

AJ4

TXCM_DPA0P

AJ5

TXCP_DPA0N

AL5

TX0M_DPA1P

AK5

TX0P_DPA1N

AL6

TX1M_DPA2P

AK6

TX1P_DPA2N

AK8

TX2M_DPA3P

AL8

TX2P_DPA3N

AD9

DVALID

AE7

PSYNC_NEW

AK4

DVPCNTL_MVP_0

AL3

DVPCNTL_MVP_1

DVPCNTL_0

DVPCNTL_1

DVPCNTL_2

DVPCLK

DVPDATA_0

DVPDATA_1

DVPDATA_2

AA2

DVPDATA_3

AA3

DVPDATA_4

AB1

DVPDATA_5

AB2

DVPDATA_6

AB3

DVPDATA_7

AC1

DVPDATA_8

AC3

DVPDATA_9

AD1

DVPDATA_10

AD2

DVPDATA_11

AD3

DVPDATA_12

AF3

DVPDATA_13

AG3

DVPDATA_14

AH3

DVPDATA_15

AG1

DVPDATA_16

AH2

DVPDATA_17

AH1

DVPDATA_18

AJ3

DVPDATA_19

AJ1

DVPDATA_20

AJ2

DVPDATA_21

AK2

DVPDATA_22

AK3

DVPDATA_23

GPIO_0

GPIO_1

GPIO_2

GPIO_3

GPIO_4

GPIO_5

GPIO_6

GPIO_7_BLON

GPIO_8_ROMSO

GPIO_9_ROMSI

GPIO_10_ROMSCK

GPIO_11

GPIO_12

GPIO_13

GPIO_14_HPD2

GPIO_15_PWRCNTL_0

GPIO_16_SSIN

GPIO_17_THERMAL_INT

GPIO_18_HPD3

GPIO_19_CTF

GPIO_20_PWRCNTL_1

GPIO_21_BB_EN

GPIO_22_ROMCSB

GPIO_23_CLKREQB

GPIO_24_JMODE

GPIO_25_TDI

GPIO_26_TCK

GPIO_27_TMS

GPIO_28_TDO

GEN_A

GEN_B

GEN_C

AH6

GEN_D_HPD4

AG6

GEN_E

AC11

VREFG

AH12

DPLL_PVDD

AG12

DPLL_PVSS

AH31

PCIE_PVDD

MPVDD

MPVSS

AE12

DPLL_VDDC

AJ31

XTALIN

AJ30

XTALOUT

AH26

TESTEN

AD12

PLLTEST

216-0707001-00/M82-S_BGA632

PART 2 OF 6

INTEGRATED

INTEGRATED TMDS/DP PORT

TMDS/DP PORT

EXT TMDS

EXT TMDS DVO

DVO

GENERAL

GENERAL PURPOSE

PURPOSE I/O

I/O

PLL &

PLL & XTAL

XTAL

TEST

polarity swap for ATI commond

DPA_PVDD

DPA_PVSS

DPB_PVDD

DPB_PVSS

DPA_VDDR DPA_VDDR

DPB_VDDR DPB_VDDR

DPB_VSSR DPB_VSSR DPB_VSSR DPB_VSSR DPB_VSSR

DPA_VSSR DPA_VSSR DPA_VSSR DPA_VSSR DPA_VSSR

DP_CALR

HPD1

HSYNC VSYNC

RSET

AVDD AVSSQ VDD1DI VSS1DI

R2B

G2B

B2B

COMP

V2SYNC H2SYNC

A2VDD

A2VDDQ

A2VSSQ

VDD2DI VSS2DI

R2SET

SCL SDA

DDC1DATA

DDC1CLK

DDC2DATA

DDC2CLK

TS_FDO

DPLUS

DMINUS

AK9 AL9

AJ9 AJ10

AL10 AK10

AL11 AK11

40mA

AL7 AK7

AE11 AF11

AJ12 AJ13

AK13 AL13

AL12 AK12 AJ11 AH9 AH11

AJ8 AF7 AG7 AJ7 AH7

AG11 AA8 AL28

AK28

AL27

AK27

AL26

AK26

AK29 AK30

AJ28 AL29 AH28 AJ27 AJ26 AL17

AK17 AL15

AK15 AL14

AK14 AJ17

AJ15

AJ14 AE16

AF16 AH14 AH16 AG16 AF18 AE18 AG14

AA5 AA4

AJ29 AH29

AC5 AC4

AF4 AH4

AF9 AG9

AE14 AE5

AE4

+DPA_PVDD

+DPB_PVDD

R112 150_0402_1%R112 150_0402_1%

1 2

RED

GREEN

BLUE

CRT_HSYNC 21,23

+A2VDD +A2VDDQ

CRT_VSYNC 23

D+ 21 D- 21

1 2

R119 499_0402_1%R119 499_0402_1%

1 2

R135 715_0402_1%R135 715_0402_1%

LCD_DDC_CLK LCD_DDC_DAT

VGA_DDC_DAT VGA_DDC_CLK

HDMIDAT_VGA HDMICLK_VGA

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

TXCM_DPB0P TXCP_DPB0N

TX0M_DPB1P

TX0P_DPB1N

TX1M_DPB2P

TX1P_DPB2N

TX2M_DPB3P

TX2P_DPB3N

DAC1 / CRT

DAC2 (TV/CRT2)

SERIAL

SERIAL BUSES

BUSES

DDC3DATA_DP3_AUXN

DDC3CLK_DP3_AUXP

DDC4DATA_DP4_AUXN

DDC4CLK_DP4_AUXP

THERMAL

+1.8VS

1 2

L40

BLM18PG121SN1D_0603

HDMI_CLK-_VGA 25 HDMI_CLK+_VGA 25

HDMI_TX0-_VGA 25 HDMI_TX0+_VGA 25

HDMI_TX1-_VGA 25 HDMI_TX1+_VGA 25

HDMI_TX2-_VGA 25 HDMI_TX2+_VGA 25

1U_0402_6.3V4Z

C297

0.1U_0402_16V4Z

HPD 25 RED 23

GREEN 23

BLUE 23

C289

+DPA_VDDR

+DPB_VDDR

+AVDD

+VDD1DI

1U_0402_6.3V4Z

BLM18PG121SN1D_0603

10U_0603_6.3V6M

+1.8VS

BLM18PG121SN1D_0603

BLM18PG121SN1D_0603 C298

C298 10U_0603_6.3V6M

10U_0603_6.3V6M

1U_0402_6.3V4Z

RED GREEN BLUE

1 2

L24

BLM18PG121SN1D_0603

10U_0603_6.3V6M

L25

SI2: Add C598,C597,C599,L41 for AMD request

+DPB_PVDD

C3000.1U_0402_16V4Z C3000.1U_0402_16V4Z

C2920.1U_0402_16V4Z C2920.1U_0402_16V4Z

+1.8VS

1U_0402_6.3V4Z

C598

0.1U_0402_16V4Z

200mA

C301

C302

10U_0603_6.3V6M

200mA

C303

C293

10U_0603_6.3V6M

1 2

R116 150_0402_1%R116 150_0402_1%

1 2

R117 150_0402_1%R117 150_0402_1%

1 2

R118 150_0402_1%R118 150_0402_1%

100mA

C316

C317

0.1U_0402_16V4Z

TMDS_CLKIN

SI: Per EMI request add SSC chip

135mA

C323

0.1U_0402_16V4Z

L33 0_0603_5%L33 0_0603_5%

C324

1U_0402_6.3V4Z

LCD_DDC_CLK LCD_DDC_DAT VGA_DDC_DAT VGA_DDC_CLK HDMIDAT_VGA HDMICLK_VGA

2mA

10U_0603_6.3V6M

LCD_DDC_CLK 24

LCD_DDC_DAT 24

VGA_DDC_DAT 23 VGA_DDC_CLK 23

HDMIDAT_VGA 25 HDMICLK_VGA 25

C322

LCD

CRT HDMI

thermal

Compal Secret Data

2006/09/25 2006/09/25

Compal Secret Data

Deciphered Date

1U_0402_6.3V4Z

C390

1U_0402_6.3V4Z

C295

BLM18PG121SN1D_0603

C597

C599

10U_0603_6.3V6M

L27

BLM18PG121SN1D_0603

L28

BLM18PG121SN1D_0603

C318

C318 10U_0603_6.3V6M

10U_0603_6.3V6M

R182 33_0402_5%@R182 33_0402_5%@ R626 0_0402_5%@R626 0_0402_5%@ R627 0_0402_5%@R627 0_0402_5%@

+1.8VS

L41

1 2 1 2 1 2

+LVDDR

C389

C391

0.1U_0402_16V4Z

+LVDDC

C288

C296

0.1U_0402_16V4Z

+1.8VS

+1.1VS

L31

BLM18PG121SN1D_0603

10U_0603_6.3V6M

0.1U_0402_16V4Z

Pin 5 have internal pull low

C320

C319

40mA

+1.8VS

320mA

80mA

1U_0402_6.3V4Z

1 2 3 4

P2040CF-08TR_TSSOP8@

SI: Per AMD request cahnge to +3.3V_DELAY

+3.3V_DELAY

1 2

R241 4.7K_0402_5%R241 4.7K_0402_5%

1 2

R242 4.7K_0402_5%R242 4.7K_0402_5%

1 2

R243 10K_0402_5%R243 10K_0402_5%

1 2

R244 10K_0402_5%R244 10K_0402_5%

1 2

R245 10K_0402_5%R245 10K_0402_5%

1 2

R246 10K_0402_5%R246 10K_0402_5%

SI2: change from 4.7K to 10K

U5F

PART 6 OF 6

AF20

LVDDR

AG20

LVDDR

AJ18

LVDDC

AH20

LVDDC

AF23

LVSSR

AF21

LVSSR

AL18

LVSSR

AJ22

LVSSR

AJ25

LVSSR

AK18

LVSSR

AK23

LVSSR

AK25

LVSSR

AJ21

LVSSR

AL23

LVSSR

AL25

LVSSR

AG18

LPVDD

AH18

LPVSS

216-0707001-00/M82-S_BGA632

10U_0603_6.3V6M

C304

1U_0402_6.3V4Z

U70

CLKIN

VDD

MRA

SR0

SR1

ModOUT

VSS

SSON#

L32 0_0603_5%L32 0_0603_5%

C321

1U_0402_6.3V4Z

Title

M82-S CRT/LVDS/TV-OUT

Size Document Number Rev

Date: Sheet

VARY_BL

Control

DIGON

LVDS channel

TXCLK_UP TXCLK_UN

TXOUT_U0P

TXOUT_U0N

TXOUT_U1P

TXOUT_U1N

TXOUT_U2P

TXOUT_U2N

TXOUT_U3P

TXOUT_U3N

TXCLK_LP

TXCLK_LN TXOUT_L0P TXOUT_L0N TXOUT_L1P TXOUT_L1N TXOUT_L2P TXOUT_L2N TXOUT_L3P TXOUT_L3N

C305

8 7 6 5

Compal Electronics, Inc.

+LPVDD

C306

0.1U_0402_16V4Z

C313

C314

0.1U_0402_16V4Z

+3VS

1 2

C500 0.1U_0402_16V4Z@C500 0.1U_0402_16V4Z@

R629 0_0402_5%@R629 0_0402_5%@

1 2

R183 33_0402_5%@R183 33_0402_5%@

1 2

+3.3V_DELAY

LA-4092P

10U_0603_6.3V6M

T44 PADT44 PAD

AA7 AC6

AD21 AE21 AJ24 AJ23 AK24 AL24 AG21 AH21 AG23 AH23

AL19 AK19 AJ20 AJ19 AK20 AL20 AK21 AL21 AK22 AL22

L29

BLM18PG121SN1D_0603

C315

L30

TMDS_SSCOUT

16 53Thursday, February 21, 2008

VGA_ENVDD 24

LVDS_BCLK+ 24 LVDS_BCLK- 24 LVDS_B0+ 24 LVDS_B0- 24 LVDS_B1+ 24 LVDS_B1- 24 LVDS_B2+ 24 LVDS_B2- 24

LVDS_ACLK+ 24 LVDS_ACLK- 24 LVDS_A0+ 24 LVDS_A0- 24 LVDS_A1+ 24 LVDS_A1- 24 LVDS_A2+ 24 LVDS_A2- 24

+1.8VS

0.4

MDA[63..32]20 MDA[31..0]19

D D

C C

+1.8VS

R143

100_0402_1%

C328

0.1U_0402_16V4Z

R144

100_0402_1%

B B

0.1U_0402_16V4Z

100_0402_1%

R148

+1.8VS

MDA[63..32] MDA[31..0]

+VDD_MEM18_REFD +VDD_MEM18_REFS

4.7K_0402_5%

R145

R146

4.7K_0402_5%

MDA0 MDA1 MDA2 MDA3 MDA4 MDA5 MDA6 MDA7 MDA8 MDA9 MDA10 MDA11 MDA12 MDA13 MDA14 MDA15 MDA16 MDA17 MDA18 MDA19 MDA20 MDA21 MDA22 MDA23 MDA24 MDA25 MDA26 MDA27 MDA28 MDA29 MDA30 MDA31 MDA32 MDA33 MDA34 MDA35 MDA36 MDA37 MDA38 MDA39 MDA40 MDA41 MDA42 MDA43 MDA44 MDA45 MDA46 MDA47 MDA48 MDA49 MDA50 MDA51 MDA52 MDA53 MDA54 MDA55 MDA56 MDA57 MDA58 MDA59 MDA60 MDA61 MDA62 MDA63

U5C

E29

DQ_0

E30

DQ_1

E31

DQ_2

D31

DQ_3

C29

DQ_4

B29

DQ_5

B30

DQ_6

A29

DQ_7

E26

DQ_8

D26

DQ_9

E25

DQ_10

D25

DQ_11

G23

DQ_12

G21

DQ_13

E21

DQ_14

D21

DQ_15

C28

DQ_16

B28

DQ_17

B27

DQ_18

A27

DQ_19

C25

DQ_20

A25

DQ_21

C24

DQ_22

B24

DQ_23

C23

DQ_24

B23

DQ_25

A23

DQ_26

B22

DQ_27

C20

DQ_28

B20

DQ_29

A20

DQ_30

C19

DQ_31

DQ_32

DQ_33

DQ_34

DQ_35

DQ_36

DQ_37

DQ_38

DQ_39

DQ_40

DQ_41

DQ_42

DQ_43

DQ_44

DQ_45

DQ_46

DQ_47

DQ_48

DQ_49

DQ_50

DQ_51

DQ_52

DQ_53

DQ_54

DQ_55

DQ_56

DQ_57

DQ_58

DQ_59

DQ_60

DQ_61

DQ_62

DQ_63

F30

MVREFD

F31

MVREFS

TEST_MCLK

TEST_YCLK

MEMTEST

216-0707001-00/M82-S_BGA632

R149

R149 240_0402_1%

240_0402_1%

Part 3 of 6

MEMORY

MEMORY INTERFACE

INTERFACE

write strobe read strobe

MA_0 MA_1 MA_2 MA_3 MA_4 MA_5 MA_6 MA_7 MA_8

MA_9 MA_10 MA_11

MA_BA0 MA_BA1 MA_A12 MA_BA2

DQMB_0 DQMB_1 DQMB_2 DQMB_3 DQMB_4 DQMB_5 DQMB_6 DQMB_7

QS_0 QS_1 QS_2 QS_3 QS_4 QS_5 QS_6 QS_7

QS_0B QS_1B QS_2B QS_3B QS_4B QS_5B QS_6B QS_7B

ODT0

ODT1

CLK0 CLK1

CLK0B CLK1B

RAS0B RAS1B

CAS0B CAS1B

CS0B_0 CS0B_1

CS1B_0 CS1B_1

CKE0 CKE1

WE0B WE1B

DRAM_RST

B14 A14 B13 E14 B17 A17 C15 G16 E16 C14 A12 B12 C12 D14 B15 G14

D30 G25 C26 C21 C5 D6 D2 K3

C30 D23 B26 B21 B6 E7 E2 J2

C31 E23 A26 A21 A6 D7 E1 J1

E20 C11

A18 A11

B18 B11

G20 D12

D20 E12

E18 G18

G11 E11

D18 G12

D16 C10

R147

4.7K_0402_5%

MAA0 MAA1 MAA2 MAA3 MAA4 MAA5 MAA6 MAA7 MAA8 MAA9 MAA10 MAA11 BA0 BA1 MAA12 BA2

DQMA#0 DQMA#1 DQMA#2 DQMA#3 DQMA#4 DQMA#5 DQMA#6 DQMA#7

QSA0 QSA1 QSA2 QSA3 QSA4 QSA5 QSA6 QSA7

QSA#0 QSA#1 QSA#2 QSA#3 QSA#4 QSA#5 QSA#6 QSA#7

ODTA0 ODTA1

CLKA0 CLKA1

CLKA0# CLKA1#

RASA#0 RASA#1

CASA#0 CASA#1

CSA0#

CSA1#

CKEA0 CKEA1

WEA#0 WEA#1

MAA[12..0] BA[2..0]

ODTA0 19 ODTA1 20

CLKA0 19 CLKA1 20

CLKA0# 19 CLKA1# 20

RASA#0 19 RASA#1 20

CASA#0 19 CASA#1 20

CSA0# 19

CSA1# 20

CKEA0 19 CKEA1 20

WEA#0 19 WEA#1 20

DQMA#[3..0] 19

DQMA#[7..4] 20

QSA[3..0] 19

QSA[7..4] 20

QSA#[3..0] 19

QSA#[7..4] 20

MAA[12..0] 19,20 BA[2..0] 19,20

R150

100_0402_1%

A A

C329

0.1U_0402_16V4Z

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2006/09/25 2006/09/25

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

M82-S MEM

LA-4092P

17 53Thursday, February 21, 2008

0.4

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