COMPAL LA-4042P Schematics

A

B

C

D

E

COMPAL CONFIDENTIAL

MODEL NAME :

1 1

PCB NO :
BOM P/N :

JAL21

LA-4042P (DAA00000T0L)

43153331L01

M09 Maybach DIS

2 2

uFCPGA Mobile Penryn

Intel Cantiga PM + ICH9M

2007-10-30

REV : 0.1

3 3

4 4

MB PCB

MB PCB

Part Number Description

Part Number Description

PCB 03P LA-4051P REV0 M/B

PCB 03P LA-4051P REV0 M/B

DAA00000R0L

DAA00000R0L

A

B

@ : Nopop Component

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

C

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

D

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, MB A4042

SCHEMATIC, MB A4042

SCHEMATIC, MB A4042

401533

401533

401533

156Monday, December 17, 2007

156Monday, December 17, 2007

156Monday, December 17, 2007

E

A

A

A

of

of

of

A

Block Diagram
Compal confidential
Model : JAL22

1 1

CRT CONN

+5V_RUN

page 20

VGA/SVID

Video Switch

+3.3V_RUN

LVDS CONN

+5V_ALW
+3.3V_RUN
+PWR_SRC

2 2

DOCKING
PORT

+PWR_SRC
+1.8V_LAN_M

USB[8,9]

Mini Card 3

WPAN/BT/Robson

3 3

+3.3V_RUN

SCREW HOLE
LED

GPUCORE / 1.1V

4 4

Selector

page 35

DAI

SATA5

page 42

page 41

page 40

on M/B Board

page 19

DP Switch

+5V_RUN

DP CONN

+5V_RUN

SD CONN

+3.3V_RUN

Through FPC to SD Board

DC IN
BATT IN

1.5V/1.05V

1.8V/0.9V

VCORE (IMVP-6)CHARGER

A

FAN

+FAN1_VOUT

TS3DV520

page 20

TS2DP512

page 21

page 21

page 31

Mini Card 2

+3.3V_WLAN
+1.5V_RUN+1.5V_RUN

page 43

3V/5V

page 44

page 45

page 46

page 47page 48

page 18

DPC

WLAN

USB[4]

VGA

SVID

+FBVDDQ
+3.3V_RUN

LVDS

+1.1V_GFX_PCIE
+GPU_CORE

CardBus

R5C847

+3.3V_RUN

PCI Express BUS

page 34page 34

RFID

page 36

73S8009CN

+3.3V_RUN

page 36

Smart Card

page 36

+3.3V_SUS

NV G98

IDSEL:AD17
(GNT#1,REQ#1)
(PIRQD#,PIRQB#,PIRQC#)

USB[7]

+3.3V_RUN

Trough Cable

B

Thermal

GUARDIAN III
EMC4002

page 51,52,53,54,55,56

DPB

PCI BUS

page 31,32

+3VRUN 33MHz

Through FPC to IO Board

PCIE1PCIE2PCIE3

Mini Card 1

WWAN

+3.3V_RUN
+1.5V_RUN

page 34

USB[5]USB[6]

USH I/F
BCM5880

+3.3V_RUN
+2.5V_AVDD_5880
+1.2V_AVDD_5880

USBH

Biometric

TPM 1.2

ME & LED

B

page 18

PCIE-E 16X

SNIFFER

IEEE1394

page 31

SIM card

USB[10]

page 36

page 42

ECE1077

+3.3V_ALW

Int.KBD &
Stick

C

Pentium-M

+1.5V_RUN
+1.05V_VCCP
+VCC_CORE

H_A#(3..35) H_D#(0..63)

Penryn -4MB (Socket P)

uFCPGA CPU

478pin

page 7,8,9

System Bus

FSB 1066 MHz

INTEL

Cantiga

+1.5V_RUN
+1.8V_MEM
+1.05V_VCCP
+3.3V_RUN
+1.05V_M

1329pin BGA

page 10,11,12,13,14,15

DMI

+1.5V_RUN
100MHz

+5V_ALW
+5V_RUN
+RTC_CELL
+3.3V_RUN
+3.3V_ALW_ICH
+1.5V_RUN
+1.05V_VCCP

INTEL

ICH9-M

676pin BGA

page 22,23,24,25

LPC BUS

+3V_RUN

page 34

33MHz

LPC BUS

SMSC KBC

+RTC_CELL
+3.3V_ALW

BC

MEC5035

page 38

SMBus

Touch Pad

page 39

page 39page 33

Stick

BC BUS

C

E-Module

+5V_MOD

SPI

SPI

BC BUS

SMSC SIO

ECE5028

+3.3V_ALW

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

D

CPU ITP Port

+1.05V_VCCP

Memory BUS (DDR2)

+1.8V_MEM 667/800 MHz

48MHz

GLCI/LCI

Azalia I/F

S-ATA(4)

SATA0SATA1

S-HDD

+3.3V_RUN

page 26 page 26

+5V_HDD

W25X32VSSIG

+3.3V_LAN

page 24

32Mbit

W25X32VSSIG

+3.3V_LAN

+3.3V_ALW

page 24

SST25VF

16Mbit

page 38

Expend GPIO

ECE1088

+3.3V_ALW

page 39

DOCK LPC BUS

page 37

D

Clock Generator

SLG8LP554

+3.3V_M

DDRII-DIMM X2

BANK 0, 1, 2, 3, 4 ,5 ,6 ,7 ,8

+0.9V_DDR_VTT
+1.8V_MEM

USB[11]

USB[2,3]

LEFT SIDE

USB[0,1] RIGHT SIDE

Intel Boazman

+3.3V_ALW
+1.8V_LAN_M
+1V_LAN_M

Azalia Codec

92HD71B

+3.3V_RUN
+VDDA

MDC

+3V_SUS

RJ11

page 27

HeadPhone &
MIC Jack

+3.3V_RUN

Through Cable

DELL CONFIDENTIAL/PROPRIETARY

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

Date: Sheet

E

CK505

page6page 7

page 16,17

USB Port
Camera

E-SATA

USB Port1 X1

Charger USB Port X1

+5V_ALW

USB Ports X2

+5V_ALW

82567LF

page 29

AMP & INT.
Speaker

+5V_RUN

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

SCHEMATIC, MB A4042

SCHEMATIC, MB A4042

SCHEMATIC, MB A4042

401533

401533

401533

page 28

On IO/B

E

Trough LVDS Cable

page 19

SATA4

page 33

On IO/B

LAN Switch

P13L500

+3.3V_LAN

page 30

RJ45

On IO/B

Trough LVDS Cable

Dig. MIC

+VDDA

DAI

SSM2602

+3.3V_RUN

256Monday, December 17, 2007

256Monday, December 17, 2007

256Monday, December 17, 2007

page 27

DOCKING

of

of

of

A

A

A

5

4

3

2

1

POWER STATES

State

D D

S0 (Full ON) / M0

S3 (Suspend to RAM) / M1

S4 (Suspend to DISK) / M1 ON ON ON ONOFF

S5 (SOFT OFF) / M1 ON ON ON ONOFFLOW HIGH LOW HIGHLOW

S3 (Suspend to RAM) / M-OFF

S4 (Suspend to DISK) / M-OFF

S5 (SOFT OFF) / M-OFF

Signal

SLP

SLP

S3#

S4#

HIGH HIGH HIGH

HIGH

LOW HIGH HIGH HIGH ON ON ON ONOFF

LOW HIGH HIGH HIGHLOW

LOW HIGH HIGH HIGH LOW ON ONOFF OFF OFF

LOW LOW LOW LOW ON OFF OFF OFF OFF

LOW LOW LOW LOW LOW ON OFF OFF OFF OFF

SLP
S5#

HIGH

S4
STATE#

SLP
M#

HIGH

HIGH

ALWAYS
PLANE

ON

M
PLANE

ON

SUS

RUN

PLANE

PLANE

ON ON ON

CLOCKS

ICH9-M

USB PORT#

0
1
2
3
4
5
6
7

DESTINATION
JUSB1 (Ext Right Side Top)
JUSB1 (Ext Right Side Bottom)
JESA1 (Ext Left Side Bottom)
JESA1 (Ext Left Side TOP)
WLAN
WWAN
WPAN
Card Bus/Express card
DOCKING8

C C

B B

PM TABLE

State

S0

S3

S5 S4/AC

S5 S4/AC don't exist

power
plane

+15V_ALW
+5V_ALW
+3.3V_ALW_ICH
+3.3V_RTC_LDO

ON

ON

+3.3V_SUS
+1.8V_MEM

ON ON

ON

OFF

OFFOFF

+5V_RUN
+3.3V_RUN
+2.5V_RUN
+1.5V_RUN
+0.9V_DDR_VTT
+GPU_CORE
+VCC_CORE
+1.05V_VCCP
+FBVDDQ
+1.1V_GFX_PCIE

OFFON

OFF

OFF

ON

ON

ON

+3.3V_M

(M-OFF)

ON

OFF

OFF

OFFOFF

+3.3V_M
+1.05V_M +1.05V_M

9

11

PCI EXPRESS

Lane 1
Lane 2
Lane 3
Lane 4
Lane 5

DOCKING
USH->BIO10
Camera

DESTINATION
MINI CARD-1 WWAN
MINI CARD-2 WLAN
MINI CARD-3 BT/UWB
EXPRESS CARD
None

Lane 6

10/100/1G LAN

PCI TABLE

PCI DEVICE IDSEL

REQ#/GNT#

PIRQ

R5C847 REQ#1 / GNT#1AD17 PIRQ[B..D]

A A

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

Date: Sheet

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

SCHEMATIC, MB A4042

SCHEMATIC, MB A4042

SCHEMATIC, MB A4042

401533

401533

401533

356Monday, December 17, 2007

356Monday, December 17, 2007

356Monday, December 17, 2007

1

A

A

A

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of

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5

4

3

2

1

RUN_ON

SI3457

( Q17 )

+INV_PWR_SRC

ADAPTER

D D

GFX_CORE_CNTRL

MAX17007
(PU13)

+GPU_COREP

RUN_ON

+PWR_SRC

+15V_ALW

(Q55)

ISL6260

(PU7)

IMVP_VR_ON

+VCC_CORE

+5V_RUNSTS11NF30L

DDR_ON

+1.8V_MEM

GFX_CORE_PWRGD

TPS51116

(PU4)

+0.9V_DDR_VTT

SN0608098

0.9V_DDR_VTT_ON

(PU3)

M_ON

(PU2)

1.5V_RUN_ON

+1.05V_M +1.5V_RUN

1.05V_RUN_ON

SN0608098

ALWON

+3.3V_ALW

ENAB_3VLAN

STS11NF30L

(Q44)

+3.3V_LAN

3.3V_RUN_ON

SI4336DY

+3.3V_RUN

(Q61)

SUS_ON

STS11NF30L

(Q60)

+3.3V_SUS

ICH_ALW_ON

SI3456BDV

(Q54)

+3.3V_ALW_ICH

M_ON

SI3456BDV

(Q54)

+3.3V_M

BATTERY

CHARGER

C C

ALW_ON

SN0608098

(PU2)

+5V_ALW

B B

HDDC_EN

MODC_EN

STS11NF30L

(Q116)

RUN_ON

SI4336DY

(Q67)

REGCTL_PNP18

BCP69

SI3456BDVSI3456BDV

(Q29)(Q32)

A A

+5V_HDD

+5V_MOD

MAX9789A

(U22)

+VDDA

+FBVDDQ

(Q45)

+1.05V_VCCP

+1.8V_LAN_M

DELL CONFIDENTIAL/PROPRIETARY

Title

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

Date: Sheet

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

SCHEMATIC, MB A4042

SCHEMATIC, MB A4042

SCHEMATIC, MB A4042

401533

401533

401533

456Monday, December 17, 2007

456Monday, December 17, 2007

456Monday, December 17, 2007

1

A

A

A

of

of

of

5

G16
A13

ICH_SMBCLK
ICH_SMBDATA

ICH9-M

D D

C17
B18

AMT_SMBCLK
AMT_SMBDAT

2.2K

2.2K

10K

10K

4

+3.3V_ALW_ICH

+3.3V_ALW_ICH

2N7002
2N7002

MEM_SCLK

MEM_SDATA

3

2.2K

2.2K

+3.3V_M

197
195

197
195

DIMMA

DIMMB

SMBUS Address [TBD]

SMBUS Address [TBD]

2

1

8.2K

9493

2A 2A

6

5

DOCK_SMB_CLK
DOCK_SMB_DAT

1A

1A

8.2K

8.2K

8.2K

8
7

LCD_SMBCLK
LCD_SMDATA

C C

1B
1B

+5V_ALW

+3.3V_ALW

6

5

6

5

DOCKING

INVERTER
(JLVDS)

SMBUS Address [TBD]

SMBUS Address [TBD]

2.2K

PBAT_SMBCLK

112

10
9

100
99

97

PBAT_SMBDAT

CARD_SMBCLK
CARD_SMBDAT

SIO

B B

1C1C111

1D
1D

1E
1E

1F1F98

2.2K

MEC 5035

96

1G

95

1H

2.2K

12

1H

1H

A A

1J
1J

CKG_SMBDAT

13

CKG_SMBCLK

106
105

Dedicated JTAG

2.2K

9

Charger

10

SMBUS Address [TBD]

103

1K

102

1K

5

Dedicated JTAG

+3.3V_ALW

+3.3V_ALW

4

100 ohm
100 ohm

3

BATTERY

4

CONN

2N7002
2N7002

2N7002
2N7002

SMBUS Address [TBD]

2.2K

2.2K
CLK_SDATA

CLK_SCLK

DAI

SMBUS Address [TBD]

3

+3.3V_M

17

16

CLK GEN

2.2K

2.2K

2N7002
2N7002

2N7002
2N7002

2N7002
2N7002

3032

WWAN

SMBUS Address [TBD]

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD

USH

PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

SMBUS Address [TBD]

+3.3V_RUN

2.2K

2.2K

EXP_SMBCLK
EXP_SMBDATA

2.2K

2.2K

WLAN_SMBCLK
WLAN_SMBDATA

2.2K

2.2K

MINI_SMBCLK
MINI_SMBDATA

SMBUS Address [TBD]

2

+3.3V_SUS

7
8

Express card

+3.3V_WLAN

30
32

WLAN

+3.3V_RUN

30
32

BT/UWB

SMBUS Address [TBD]

SMBUS Address [TBD]

SMBUS Address [TBD]

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, MB A4042

SCHEMATIC, MB A4042

SCHEMATIC, MB A4042
401533

401533

401533

556Monday, December 17, 2007

556Monday, December 17, 2007

556Monday, December 17, 2007

1

of

of

of

A

A

A

5

+3.3V_M

1 2

R3

@R3

@

0_0402_5%~D

0_0402_5%~D

CKG_SMBDAT<27,38,48>

D D

CKG_SMBCLK<27,38,48>

FSC FSB FSA CPU

CLKSEL2 CLKSEL0CLKSEL1

000

*

00

1

0

11

C C

0

1

1

0

11

+3.3V_M

12

R51

@R51

@

10K_0402_5%~D

10K_0402_5%~D

FSA

12

R55

@R55

@

10K_0402_5%~D

10K_0402_5%~D

B B

+3.3V_RUN

10K_0402_5%~D

10K_0402_5%~D

R43

R43

1 2

PCI_PCM

R46

R46

PCI_ICH

R50

R50

R54

R54

*

*

+3.3V_RUN

10K_0402_5%~D

10K_0402_5%~D

1 2

+3.3V_RUN

10K_0402_5%~D

10K_0402_5%~D

1 2

A A

PCI_SIO

10K_0402_5%~D

10K_0402_5%~D

12

@

@

*

6 1

Q1A

Q1A
2N7002DW-T/R7_SOT363-6~D

2N7002DW-T/R7_SOT363-6~D

+3.3V_M

2
5

Q1B

Q1B
2N7002DW-T/R7_SOT363-6~D

2N7002DW-T/R7_SOT363-6~D

3

1 2

R9

@R9

@

0_0402_5%~D

0_0402_5%~D

4

SRC

MHz

MHz

100

266

1

0

00

1

0

TME PIN 32

0
1

ITP_EN

0
1 Pin 5/6 as CPU_ITP

0=UMA

1=DIS

100

133

100

200

100

166

100

333

100

100

100

400

overclocking enabled
overclocling disabled

PIN 37
Pin 5/6 as SRC_10

PIN43FCTSEL1 PIN48PIN47PIN44

27M_out

2.2K_0402_5%~D

2.2K_0402_5%~D

2.2K_0402_5%~D

2.2K_0402_5%~D

12

12

R1

R1

R2

R2

CLK_SDATA

CLK_SCLK

PCI
MHz

33.3

33.3

33.3

33.3

Place crystal within

33.3

500 mils of CK505

33.3

33.3

CLK_ICH_48M<24>
CPU_MCH_BSEL0<8,10>
CPU_MCH_BSEL1<8,10>

CPU_MCH_BSEL2<8,10>

CLK_PCI_5028<37>

CLK_PCI_TPM<36>
CLK_PCI_PCM<31>

CLK_PCI_DOCK<35>

CLK_PCI_5035<38>

CLK_ICH_14M<24>
CLK_SIO_14M<37>

CLK_NV_27M<51>

CLK_NVSS_27M<51>

CLK_PCI_ICH<22>

CLK_PWRGD<24>

96/100M_TDOT96CDOT96T

0=UMA
1=Disc. GRFX down

5

4

1 2

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D
L1

L1
BLM21AG601SN1D_0805~D

BLM21AG601SN1D_0805~D

1

C1

C1

2

4.7U_0603_6.3V4Z~D

4.7U_0603_6.3V4Z~D

0.047U_0402_16V4Z~D

0.047U_0402_16V4Z~D

1

1

@

@

C11

C11

C12

C12

2

2

X1

X1

14.31818MHz_20P_1BX14318CC1A~D

33P_0402_50V8J~D

33P_0402_50V8J~D

33P_0402_50V8J~D

33P_0402_50V8J~D

14.31818MHz_20P_1BX14318CC1A~D

12

C16

C16

C17

C17

12

CLK_ICH_48M FSA
CPU_MCH_BSEL0
CPU_MCH_BSEL1

CPU_MCH_BSEL2

CLK_PCI_5028
CLK_PCI_TPM PCI_TPM
CLK_PCI_PCM PCI_PCM

CLK_PCI_DOCK
CLK_PCI_5035 PCI_EC

CLK_ICH_14M
CLK_SIO_14M

CLK_NV_27M
CLK_NVSS_27M

CLK_PWRGD

12

R17 0_0402_5%~DR17 0_0402_5%~D
R19 33_0402_5%~D

R19 33_0402_5%~D
R22 2.2K_0402_5%~D

R22 2.2K_0402_5%~D

R24 10K_0402_5%~D

R24 10K_0402_5%~D

R26 33_0402_5%~D

R26 33_0402_5%~D
R29 22_0402_5%~D

R29 22_0402_5%~D
R30 22_0402_5%~D

R30 22_0402_5%~D
R27 22_0402_5%~D

R27 22_0402_5%~D
R32 33_0402_5%~D

R32 33_0402_5%~D

R33 22_0402_5%~D

R33 22_0402_5%~D
R35 22_0402_5%~D

R35 22_0402_5%~D
R37 33_0402_5%~DR37 33_0402_5%~D
R38 33_0402_5%~DR38 33_0402_5%~D

R41 33_0402_5%~D

R41 33_0402_5%~D

+CK_VDD_MAIN2

1 2

L2

@L2

@

BLM21PG600SN1D_0805~D

BLM21PG600SN1D_0805~D

+CK_VDD_REF+CK_VDD_48

0.047U_0402_16V7K~D

0.047U_0402_16V7K~D

1

C13

C13

2

1 2

1 2

1 2

1 2

1 2

1 2
1 2

1 2

12

12

12
12

12

12

96/100M_C

SRCC0SRCT027M SSout

4

+CK_VDD_MAIN+3.3V_M

0_0805_5%~D

0_0805_5%~D

R851

R851

1 2

1 2

R12 0_0603_5%~D R12 0_0603_5%~D

1 2

R14 0_0603_5%~D R14 0_0603_5%~D

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

+CK_VDD_MAIN

1

2

1

2

+CK_VDD_REF
+CK_VDD_48

CLK_XTAL_IN

CLK_XTAL_OUT

FSC

PCI_SIO

CLKREF

CLK_NV
CLK_NVSS

PCI_ICHCLK_PCI_ICH

CLK_SCLK

CLK_SDATA

3

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

10U_0805_10V4Z~D

10U_0805_10V4Z~D

1

C3

C3

C2

C2

2

10U_0805_10V4Z~D

10U_0805_10V4Z~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

1

@

@

C8

C8

C9

C9

2

1 2

R10 2.2_0603_5%~D

R10 2.2_0603_5%~D

U1

U1

1

VDD_SRC

49

VDD_SRC

54

VDD_SRC

65

VDD_SRC

30

VDD_PCI

36

VDD_PCI

12

VDD_CPU

18

VDD_REF

40

VDD_48

20

XTAL_IN

19

XTAL_OUT

41

USB_48MHz/FSLA

45

FSL_B/TEST_MODE

23

REF_0/FSL_C/TEST_SEL

34

PCICLK4/FCT_SEL

33

PCICLK3

32

PCICLK2/TME

27

PCICLK1

22

REF_1

43

DOT_96/27M

44

DOT_96#/27M_SS

37

PCICLK_F0/ITP_EN

39

CKPWRGD/PD#

9

NC

16

SMBCLK

17

SMBDAT

4

VSS_SRC

15

VSS_CPU

21

VSS_REF

31

VSS_PCI

35

VSS_PCI

42

VSS_48

68

VSS_SRC

73

THRM_PAD

SLG8LP554VTR_QFN72_10X10~D

SLG8LP554VTR_QFN72_10X10~D

1

2

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

1

2

SLG8LP554VTR

SLG8LP554VTR

C4

C4

C10

C10

C5

C5

2

CPU_STP#

CPU_ITP/SRC_10

CPU_ITP#/SRC_10#

CLKREQ_9#

CLKREQ_8#

CLKREQ_7#

CLKREQ_6#

CLKREQ_5#

CLKREQ_4#

CLKREQ_3#

CLKREQ_2#

SRC_1/SATA

SRC_1#/SATA#

CLKREQ_1#

LCD_CLK/SRC_0

LCD_CLK#/SRC_0#

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

1

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

1

2

+CK_VDD_A

VDD_A
VSS_A

PCI_STP#

CPU_1

CPU_1#

CPU_0

CPU_0#

SRC_9

SRC_9#

SRC_8

SRC_8#

SRC_7

SRC_7#

SRC_6

SRC_6#

SRC_5

SRC_5#

SRC_4

SRC_4#

SRC_3

SRC_3#

SRC_2

SRC_2#

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

1

C7

C7

C6

C6

2

7
8

H_STP_PCI#

25

H_STP_CPU#

24

MCH_BCLK CLK_MCH_BCLK

11

MCH_BCLK#

10

CPU_BCLK

14

CPU_BCLK#

13

CPU_ITP

6

CPU_ITP#

5

PCIE_MINI1

3

PCIE_MINI1#

2

MINI1CLK_REQ#

72

PCIE_MINI2

70

PCIE_MINI2#

69

MINI2CLK_REQ#

71

PCIE_ICH

66

PCIE_ICH#

67
38
63
64

MINI3CLK_REQ#

62

PCIE_VGA CLK_PCIE_VGA

60

PCIE_VGA# CLK_PCIE_VGA#

61
29

PCIE_EXP CLK_PCIE_EXP

58

PCIE_EXP# CLK_PCIE_EXP#

59

EXPCLK_REQ#

57

MCH_3GPLL

55
56

CLK_3GPLLREQ#_R

28
52
53
26

PCIE_SATA CLK_PCIE_SATA

50

PCIE_SATA#

51

SATA_CLKREQ#_R

46
47
48

2

4.7U_0603_6.3V4Z~D

4.7U_0603_6.3V4Z~D

1

C14

C14

2

1 2

R11 33_0402_5%~D

R11 33_0402_5%~D

1 2

R13 33_0402_5%~D

R13 33_0402_5%~D

1 2

R15 33_0402_5%~D

R15 33_0402_5%~D

1 2

R16 33_0402_5%~D

R16 33_0402_5%~D

1 2

R18 33_0402_5%~D

R18 33_0402_5%~D

1 2

R21 33_0402_5%~D

R21 33_0402_5%~D

1 2

R23 33_0402_5%~D

R23 33_0402_5%~D

1 2

R25 33_0402_5%~D

R25 33_0402_5%~D

1 2

R28 33_0402_5%~D

R28 33_0402_5%~D

1 2

R31 33_0402_5%~D

R31 33_0402_5%~D

1 2

R34 33_0402_5%~D

R34 33_0402_5%~D

1 2

R36 33_0402_5%~D

R36 33_0402_5%~D

1 2

R39 33_0402_5%~D

R39 33_0402_5%~D

1 2

R40 33_0402_5%~D

R40 33_0402_5%~D

1 2

R42 33_0402_5%~DR42 33_0402_5%~D

1 2

R44 33_0402_5%~DR44 33_0402_5%~D

1 2

R408 33_0402_5%~DR408 33_0402_5%~D

1 2

R415 33_0402_5%~DR415 33_0402_5%~D

1 2

R45 33_0402_5%~D

R45 33_0402_5%~D

1 2

R47 33_0402_5%~D

R47 33_0402_5%~D

1 2

R48 475_0402_1%~D

R48 475_0402_1%~D

1 2

R49 33_0402_5%~D

R49 33_0402_5%~D

1 2

R52 33_0402_5%~D

R52 33_0402_5%~D

1 2

R53 475_0402_1%~D

R53 475_0402_1%~D

2

1

+3.3V_RUN

MINI1CLK_REQ#
MINI2CLK_REQ#
CLK_3GPLLREQ#
SATA_CLKREQ#
MINI3CLK_REQ#
EXPCLK_REQ#

0.047U_0402_16V4Z~D

0.047U_0402_16V4Z~D

1

C15

C15

2

H_STP_PCI# <24>

H_STP_CPU# <24>

CLK_MCH_BCLK#

CLK_CPU_BCLK
CLK_CPU_BCLK#

CLK_CPU_ITP
CLK_CPU_ITP#

CLK_PCIE_MINI1
CLK_PCIE_MINI1#

CLK_PCIE_MINI2
CLK_PCIE_MINI2#

CLK_PCIE_ICH
CLK_PCIE_ICH#

CLK_PCIE_MINI3PCIE_MINI3
CLK_PCIE_MINI3#PCIE_MINI3#

CLK_MCH_3GPLL
CLK_MCH_3GPLL#MCH_3GPLL#
CLK_3GPLLREQ#

CLK_PCIE_SATA#

CLK_MCH_BCLK <10>
CLK_MCH_BCLK# <10>

CLK_CPU_BCLK <7>
CLK_CPU_BCLK# <7>

CLK_CPU_ITP <7>
CLK_CPU_ITP# <7>

CLK_PCIE_MINI1# <34>

MINI1CLK_REQ# <34>

CLK_PCIE_MINI2 <34>
CLK_PCIE_MINI2# <34>

MINI2CLK_REQ# <34>

CLK_PCIE_ICH <24>
CLK_PCIE_ICH# <24>

CLK_PCIE_MINI3 <34>
CLK_PCIE_MINI3# <34>

MINI3CLK_REQ# <34>

CLK_PCIE_VGA <51>
CLK_PCIE_VGA# <51>

CLK_PCIE_EXP <32>
CLK_PCIE_EXP# <32>

EXPCLK_REQ# <32>
CLK_MCH_3GPLL <10>

CLK_MCH_3GPLL# <10>

CLK_3GPLLREQ# <10>

CLK_PCIE_SATA <23>

CLK_PCIE_SATA# <23>

SATA_CLKREQ# <24>

1 2

R4 10K_0402_5%~D

R4 10K_0402_5%~D

1 2

R5 10K_0402_5%~D

R5 10K_0402_5%~D

1 2

R6 10K_0402_5%~D

R6 10K_0402_5%~D

1 2

R7 10K_0402_5%~D

R7 10K_0402_5%~D

1 2

R8 10K_0402_5%~D

R8 10K_0402_5%~D

1 2

R356 10K_0402_5%~D

R356 10K_0402_5%~D

CLK_PCIE_MINI1 <34>

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, MB A4042

SCHEMATIC, MB A4042

SCHEMATIC, MB A4042
401533

401533

401533

656Tuesday, December 18, 2007

656Tuesday, December 18, 2007

656Tuesday, December 18, 2007

1

A

A

A

of

of

of

5

H_A#[3..35]<10>

D D

H_ADSTB#0<10>

H_REQ#0<10>
H_REQ#1<10>
H_REQ#2<10>
H_REQ#3<10>
H_REQ#4<10>

C C

H_ADSTB#1<10>

H_A20M#<23>

H_FERR#<23>

H_IGNNE#<23>
H_STPCLK#<23>

H_INTR<23>
H_NMI<23>

H_THERMDA1<18>

width / Spacing = 10 / 10 mil

H_THERMDC1<18>

+1.05V_VCCP

B B

Pin D22
Dual Core: 0 V
Quad Core: 2/3 VTT

+V_CPU_GTLREF_2

H_SMI#<23>

C227

C227

100P_0402_50V8K~D

100P_0402_50V8K~D

+V_CPU_GTLREF_2

51_0402_5%~D

51_0402_5%~D

QC: POP
DC: DEPOP

+1.05V_VCCP

12

@

@

R942

R942
1K_0402_1%~D

1K_0402_1%~D

12

@

@

R944

R944
2K_0402_1%~D

2K_0402_1%~D

@

@

1 2

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_ADSTB#0

H_REQ#0
H_REQ#1
H_REQ#2

H_REQ#4
H_A#17

H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25 ITP_TCK
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35
H_ADSTB#1

H_A20M#
H_FERR#
H_IGNNE#

H_STPCLK#
H_INTR
H_NMI
H_SMI#

ITP_BPM2#1
ITP_BPM2#0

2

@

@

ITP_BPM2#2

1

R984

R984

13

D

D

S

S

Layout close CPU PIN D22
50 ohm, 0.5 inch (max)

A A

JCPU1A

JCPU1A

J4

A[3]#

L5

A[4]#

L4

A[5]#

K5

A[6]#

M3

A[7]#

N2

A[8]#

J1

A[9]#

N3

A[10]#

P5

A[11]#

P2

A[12]#

L2

A[13]#

P4

A[14]#

P1

A[15]#

R1

A[16]#

M1

ADSTB[0]#

K3

REQ[0]#

H2

REQ[1]#

K2

REQ[2]#

J3

REQ[3]#

L1

REQ[4]#

Y2

A[17]#

U5

A[18]#

R3

A[19]#

W6

A[20]#

U4

A[21]#

Y5

A[22]#

U1

A[23]#

R4

A[24]#

T5

A[25]#

T3

A[26]#

W2

A[27]#

W5

A[28]#

Y4

A[29]#

U2

A[30]#

V4

A[31]#

W3

A[32]#

AA4

A[33]#

AB2

A[34]#

AA3

A[35]#

V1

ADSTB[1]#

A6

A20M#

A5

FERR#

C4

IGNNE#

D5

STPCLK#

C6

LINT0

B4

LINT1

A3

SMI#

M4

RSVD[01]

N5

RSVD[02]

T2

RSVD[03]

V3

RSVD[04]

B2

RSVD[05]

D2

RSVD[06]

D22

RSVD[07]

D3

RSVD[08]

F6

RSVD[09]

TYCO_1-1674770-2_Penryn~D

TYCO_1-1674770-2_Penryn~D

Q129

Q129
BSS138_SOT23~D

BSS138_SOT23~D

@

@

2

G

G

ADDR GROUP_0

ADDR GROUP_0

ADS#
BNR#
BPRI#

DEFER#

DRDY#
DBSY#

BR0#

IERR#

INIT#

LOCK#

CONTROL

CONTROL

RESET#

RS[0]#
RS[1]#
RS[2]#
TRDY#

HIT#

HITM#

ADDR GROUP_1

ADDR GROUP_1

BPM[0]#
BPM[1]#
BPM[2]#
BPM[3]#

PRDY#
PREQ#

TCK

TDI
TDO
TMS

TRST#

DBR#

XDP/ITP SIGNALS

XDP/ITP SIGNALS

THERMAL

THERMAL

PROCHOT#

THERMDA
THERMDC

ICH

ICH

THERMTRIP#

H CLK

H CLK

BCLK[0]
BCLK[1]

RESERVED

RESERVED

+3.3V_ALW

12

R943

R943
100K_0402_5%~D

100K_0402_5%~D

@

@

C

C

2

B

B

E

E

MMST3904-7-F_SOT323-3~D

MMST3904-7-F_SOT323-3~D

3 1

@

@

Q14

Q14

H1
E2
G5

H5
F21
E1

F1
D20

B3
H4
C1

F3
F4
G3
G2

G6
E4

AD4
AD3
AD1
AC4
AC2
AC1
AC5
AA6
AB3
AB5
AB6
C20

D21
A24
B25

C7

A22
A21

4

H_ADS#
H_BNR#
H_BPRI#

H_DEFER#
H_DRDY#
H_DBSY#

H_BR0#
H_IERR#

H_INIT#
H_LOCK#
H_RESET#

H_RS#0
H_RS#1
H_RS#2
H_TRDY#H_REQ#3

H_HIT#
H_HITM#

ITP_BPM#0
ITP_BPM#1
ITP_BPM#2
ITP_BPM#3
ITP_BPM#4
ITP_BPM#5

ITP_TDI
ITP_TDO
ITP_TMS
ITP_TRST#
ITP_DBRESET#

EC_CPU_PROCHOT#
H_THERMDA

H_THERMDC
H_THERMTRIP#
CLK_CPU_BCLK

CLK_CPU_BCLK#

+1.05V_VCCP

R973

R973

1 2

R61 56_0402_5%~D

R61 56_0402_5%~D

+1.05V_VCCP

51_0402_5%~D

51_0402_5%~D

1 2

@

@

H_ADS# <10>

H_BNR# <10>
H_BPRI# <10>

H_DEFER# <10>
H_DRDY# <10>

H_DBSY# <10>

H_BR0# <10>

H_INIT# <23>

H_LOCK# <10>

H_RESET# <10>
H_RS#0 <10>
H_RS#1 <10>
H_RS#2 <10>
H_TRDY# <10>

H_HIT# <10>

H_HITM# <10>

ITP_DBRESET# <24,37>

2

C18

@C18

@

100P_0402_50V8K~D

100P_0402_50V8K~D

1

H_THERMTRIP# <18>

CLK_CPU_BCLK <6>

CLK_CPU_BCLK# <6>

H_RESET#

51_0402_1%~D

51_0402_1%~D

H_THERMTRIP#

R785

R785

ITP_BPM#5

Place close to CPU within 200 mil

+3.3V_ALW

12

R945

R945
100K_0402_5%~D

100K_0402_5%~D

@

R946

R946

10K_0402_5%~D

10K_0402_5%~D

@

@

12

@

QUAD_REF_EN <37>

+1.05V_VCCP

Place near JITP

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

1

1

2

12

R56 56_0402_5%~D

R56 56_0402_5%~D

+1.05V_VCCP

12

H_THERMDA <18>

R59

R59
56_0402_5%~D

56_0402_5%~D

C19

C19

C20

C20

2

+1.05V_VCCP

H_RESET#

ITP_TDO

width / Spacing = 10 / 10 mil

H_THERMDC <18>

ITP_BPM#0 ITP_BPM2#0

ITP_BPM#1 ITP_BPM2#1

ITP_BPM#2 ITP_BPM2#2

ITP_BPM#3 ITP_BPM2#3

QC:
ES1: POP ALL
ES2: POP 0 ohm ONLY
DC: DEPOP ALL

+3.3V_ALW_ICH

R60 10K_0402_5%~D

R60 10K_0402_5%~D

Place close to JITP within 1ns = 5000 mil

+1.05V_VCCP

51_0402_5%~D

51_0402_5%~D

1 2

51_0402_5%~D

51_0402_5%~D

1 2

Place close to CPU within 200ps = 1000 mil

Depop JITP1,C19,C20,R64,R67,R785,R65,R66 when not supported for cost saving.

3

1 2

R57 1K_0402_5%~DR57 1K_0402_5%~D

1 2

R989 22.6_0402_1%~DR989 22.6_0402_1%~D

R976

R976

0_0402_5%~D

0_0402_5%~D

1 2

R978

R978

0_0402_5%~D

0_0402_5%~D

1 2

R980

R980

0_0402_5%~D

0_0402_5%~D

1 2

R982

R982

0_0402_5%~D

0_0402_5%~D

1 2

1 2

R65

R65

R66

R66

ITP_BPM#0
ITP_BPM#1
ITP_BPM#2
ITP_BPM#3
ITP_BPM#4
ITP_BPM#5

@

@

@

@

@

@

@

@

ITP_DBRESET#

ITP_TDI

ITP_TRST#

CLK_CPU_ITP<6>
CLK_CPU_ITP#<6>

2

R977

R977
51_0402_1%~D

51_0402_1%~D

@

@

R979

R979
51_0402_1%~D

51_0402_1%~D

@

@

R981

R981
51_0402_1%~D

51_0402_1%~D

@

@

R983

R983
51_0402_1%~D

51_0402_1%~D

@

@

+1.05V_VCCP

ITP_DBRESET#

ITP_TCK
CLK_CPU_ITP

CLK_CPU_ITP#

ITP_TCK
ITP_TRST#

ITP_TMS
ITP_TDI

+1.05V_VCCP

+1.05V_VCCP

28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10

9
8
7
6
5
4
3
2
1

R62

R62

51_0402_5%~D

51_0402_5%~D

1 2

R64

R64

51_0402_5%~D

51_0402_5%~D

1 2

R67

R67

51_0402_5%~D

51_0402_5%~D

1 2

JITP1

JITP1

VTT1
VTT0
VTAP
DBR#
DBA#
BPM0#
GND5
BPM1#
GND4
BPM2#
GND3
BPM3#
GND2
BPM4#
GND1
BPM5#
RESET#
FBO
GND0
BCLKP
BCLKN
TDO
NC2
TCK
NC1
TRST#
TMS
TDI

Place close to JITP within 200ps = 1000 mil

29

GND6

GND7

MOLEX_52435-2891_28P~D

MOLEX_52435-2891_28P~D

30

100K_0402_5%~D

100K_0402_5%~D

QUAD_DET<37>

Pin F8
Dual Core: GND (internal)
Quad Core: Floating (internal)

ITP_TDO

ITP_TMS

ITP_TCK

+3.3V_ALW

R941

R941

@

@

1

JCPU1D

JCPU1D

A4

VSS[001]

A8

VSS[002]

A11

VSS[003]

A14

VSS[004]

A16

VSS[005]

A19

VSS[006]

A23

VSS[007]

AF2

VSS[008]

B6

VSS[009]

B8

VSS[010]

B11

VSS[011]

B13

VSS[012]

B16

VSS[013]

B19

VSS[014]

B21

VSS[015]

B24

VSS[016]

C5

VSS[017]

C8

VSS[018]

C11

VSS[019]

C14

VSS[020]

C16

VSS[021]

C19

VSS[022]

C2

VSS[023]

C22

VSS[024]

C25

VSS[025]

D1

VSS[026]

D4

VSS[027]

D8

VSS[028]

D11

VSS[029]

D13

VSS[030]

D16

VSS[031]

D19

VSS[032]

D23

VSS[033]

D26

VSS[034]

E3

VSS[035]

E6

VSS[036]

E8

VSS[037]

12

E11

VSS[038]

E14

VSS[039]

E16

VSS[040]

E19

VSS[041]

E21

VSS[042]

E24

VSS[043]

F5

VSS[044]

F8

VSS[045]

F11

VSS[046]

F13

VSS[047]

F16

VSS[048]

F19

VSS[049]

F2

VSS[050]

F22

VSS[051]

F25

VSS[052]

G4

VSS[053]

G1

VSS[054]

G23

VSS[055]

G26

VSS[056]

H3

VSS[057]

H6

VSS[058]

H21

VSS[059]

H24

VSS[060]

J2

VSS[061]

J5

VSS[062]

J22

VSS[063]

J25

VSS[064]

K1

VSS[065]

K4

VSS[066]

K23

VSS[067]

K26

VSS[068]

L3

VSS[069]

L6

VSS[070]

L21

VSS[071]

L24

VSS[072]

M2

VSS[073]

M5

VSS[074]

M22

VSS[075]

M25

VSS[076]

N1

VSS[077]

N4

VSS[078]

N23

VSS[079]

N26

VSS[080]
VSS[081]P3VSS[162]

TYCO_1-1674770-2_Penryn~D

TYCO_1-1674770-2_Penryn~D

VSS[082]
VSS[083]
VSS[084]
VSS[085]
VSS[086]
VSS[087]
VSS[088]
VSS[089]
VSS[090]
VSS[091]
VSS[092]
VSS[093]
VSS[094]
VSS[095]
VSS[096]
VSS[097]
VSS[098]
VSS[099]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
VSS[159]
VSS[160]
VSS[161]

VSS[163]

P6
P21
P24
R2
R5
R22
R25
T1
T4
T23
T26
U3
U6
U21
U24
V2
V5
V22
V25
W1
W4
W23
W26
Y3
Y6
Y21
Y24
AA2
AA5
AA8
AA11
AA14
AA16
AA19
AA22
AA25
AB1
AB4
AB8
AB11
AB13
AB16
AB19
AB23
AB26
AC3
AC6
AC8
AC11
AC14
AC16
AC19
AC21
AC24
AD2
AD5
AD8
AD11
AD13
AD16
AD19
AD22
AD25
AE1
AE4
AE8
AE11
AE14
AE16
AE19
AE23
AE26
A2
AF6
AF8
AF11
AF13
AF16
AF19
AF21
A25
AF25

ITP_BPM2#3

Quad Core support circuit

5

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

4

3

2

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, MB A4042

SCHEMATIC, MB A4042

SCHEMATIC, MB A4042
401533

401533

401533

756Monday, December 17, 2007

756Monday, December 17, 2007

756Monday, December 17, 2007

1

A

A

A

of

of

of

5

4

3

2

1

+VCC_CORE +VCC_CORE

D D

C C

B B

1 2

A A

1K_0402_5%~D

1K_0402_5%~D

@R72

@

R72

+V_CPU_GTLREF

CPU_MCH_BSEL0<6,10>
CPU_MCH_BSEL1<6,10>
CPU_MCH_BSEL2<6,10>

1K_0402_5%~D

1K_0402_5%~D

@R73

@

R73

1 2

H_D#[0..63]<10>

JCPU1B

JCPU1B

E22

D[0]#

F24

D[1]#

E26

D[2]#

G22

D[3]#

F23

D[4]#

G25

D[5]#

E25

D[6]#

E23

D[7]#

K24

D[8]#

G24

D[9]#

J24

D[10]#

J23

D[11]#

H22

D[12]#

F26

D[13]#

K22

D[14]#

H23

D[15]#

J26

DSTBN[0]#

H26

DSTBP[0]#

H25

DINV[0]#

N22

D[16]#

K25

D[17]#

P26

D[18]#

R23

D[19]#

L23

D[20]#

M24

D[21]#

L22

D[22]#

M23

D[23]#

P25

D[24]#

P23

D[25]#

P22

D[26]#

T24

D[27]#

R24

D[28]#

L25

D[29]#

T25

D[30]#

N25

D[31]#

L26

DSTBN[1]#

M26

DSTBP[1]#

N24

DINV[1]#

AD26

GTLREF

C23

TEST1

D25

TEST2

C24

TEST3

AF26

TEST4

AF1

TEST5

A26

TEST6

C3

TEST7

B22

BSEL[0]

B23

BSEL[1]

C21

BSEL[2]

TYCO_1-1674770-2_Penryn~D

TYCO_1-1674770-2_Penryn~D

T154PAD~D T154PAD~D
T3PAD~D T3PAD~D

TEST3
TEST5

DATA GRP 0

DATA GRP 0

DATA GRP 1

DATA GRP 1

MISC

MISC

PWRGOOD

D[32]#
D[33]#
D[34]#
D[35]#
D[36]#
D[37]#
D[38]#
D[39]#
D[40]#
D[41]#

DATA GRP 2DATA GRP 3

DATA GRP 2DATA GRP 3

D[42]#
D[43]#
D[44]#
D[45]#
D[46]#
D[47]#

DSTBN[2]#

DSTBP[2]#

DINV[2]#

D[48]#
D[49]#
D[50]#
D[51]#
D[52]#
D[53]#
D[54]#
D[55]#
D[56]#
D[57]#
D[58]#
D[59]#
D[60]#
D[61]#
D[62]#
D[63]#

DSTBN[3]#

DSTBP[3]#

DINV[3]#
COMP[0]

COMP[1]
COMP[2]
COMP[3]

DPRSTP#

DPSLP#

DPWR#

SLP#

PSI#

BCLK BSEL2 BSEL1 BSEL0
133

001
166
200

100

TEST1
TEST2

H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_DSTBN#0
H_DSTBP#0
H_DINV#0

H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21

H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_DSTBN#1
H_DSTBP#1
H_DINV#1

TEST1
TEST2
TEST3
TEST4
TEST5
TEST6
TEST7
CPU_MCH_BSEL0
CPU_MCH_BSEL1
CPU_MCH_BSEL2

For the purpose of testability, route these signals
through a ground referenced Z0 = 50ohm trace that
ends in a via that is near a GND via and is
accessible through an oscilloscope connection.

H_DSTBN#0<10>

H_DSTBP#0<10>

H_DINV#0<10>

H_DSTBN#1<10>

H_DSTBP#1<10>

H_DINV#1<10>

T153PAD~D T153PAD~D
T138PAD~D T138PAD~D

T4PAD~D T4PAD~D

FSB
533
667
800
1067 266 0 0 0

5

4

Y22
AB24
V24
V26
V23
T22
U25
U23
Y25
W22
Y23
W24
W25
AA23
AA24
AB25
Y26
AA26
U22

AE24
AD24
AA21
AB22
AB21
AC26
AD20
AE22
AF23
AC25
AE21
AD21
AC22
AD23
AF22
AC23
AE25
AF24
AC20

R26
U26
AA1
Y1

E5
B5
D24
D6
D7
AE6

110

H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_DSTBN#2
H_DSTBP#2
H_DINV#2

H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54H_D#22
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
H_DSTBN#3
H_DSTBP#3
H_DINV#3

COMP0
COMP1
COMP2
COMP3

H_DPRSTP#
H_DPSLP#
H_DPWR#
H_PWRGOOD
H_CPUSLP#
H_PSI#

+V_CPU_GTLREF

H_DPRSTP# <10,23,47>

H_DPWR# <10>

H_PWRGOOD <23>

H_CPUSLP# <10>

+1.05V_VCCP

12

R77

R77
1K_0402_1%~D

1K_0402_1%~D

12

R78

R78
2K_0402_1%~D

2K_0402_1%~D

H_PSI# <47>

Layout close CPU PIN AD26
50 ohm, 0.5 inch (max)

H_DSTBN#2 <10>
H_DSTBP#2 <10>

H_DINV#2 <10>

H_DSTBN#3 <10>
H_DSTBP#3 <10>

H_DINV#3 <10>

H_DPSLP# <23>

24.9_0402_1%~D

24.9_0402_1%~D

49.9_0402_1%~D

49.9_0402_1%~D

12

12

Resistor placed within 0.5" of
CPU pin.Trace should be at least
25 mils away from any other
toggling signal. COMP0, COMP2
trace should be 25 ohm. COMP1,
COMP3 should be 50 ohm.
(Quad Core design)

R69

R69

R68

R68

24.9_0402_1%~D

24.9_0402_1%~D

49.9_0402_1%~D

49.9_0402_1%~D

12

12

R71

R71

R70

R70

Dual Core Should follow Quad Core value
Avia should support Quad / Dual Core CPU

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

JCPU1C

JCPU1C

A7

VCC[001]

A9

VCC[002]

A10

VCC[003]

A12

VCC[004]

A13

VCC[005]

A15

VCC[006]

A17

VCC[007]

A18

VCC[008]

A20

VCC[009]

B7

VCC[010]

B9

VCC[011]

B10

VCC[012]

B12

VCC[013]

B14

VCC[014]

B15

VCC[015]

B17

VCC[016]

B18

VCC[017]

B20

VCC[018]

C9

VCC[019]

C10

VCC[020]

C12

VCC[021]

C13

VCC[022]

C15

VCC[023]

C17

VCC[024]

C18

VCC[025]

D9

VCC[026]

D10

VCC[027]

D12

VCC[028]

D14

VCC[029]

D15

VCC[030]

D17

VCC[031]

D18

VCC[032]

E7

VCC[033]

E9

VCC[034]

E10

VCC[035]

E12

VCC[036]

E13

VCC[037]

E15

VCC[038]

E17

VCC[039]

E18

VCC[040]

E20

VCC[041]

F7

VCC[042]

F9

VCC[043]

F10

VCC[044]

F12

VCC[045]

F14

VCC[046]

F15

VCC[047]

F17

VCC[048]

F18

VCC[049]

F20

VCC[050]

AA7

VCC[051]

AA9

VCC[052]

AA10

VCC[053]

AA12

VCC[054]

AA13

VCC[055]

AA15

VCC[056]

AA17

VCC[057]

AA18

VCC[058]

AA20

VCC[059]

AB9

VCC[060]

AC10

VCC[061]

AB10

VCC[062]

AB12

VCC[063]

AB14

VCC[064]

AB15

VCC[065]

AB17

VCC[066]

AB18

VCC[067]

TYCO_1-1674770-2_Penryn~D

TYCO_1-1674770-2_Penryn~D

AB20

VCC[068]

AB7

VCC[069]

AC7

VCC[070]

AC9

VCC[071]

AC12

VCC[072]

AC13

VCC[073]

AC15

VCC[074]

AC17

VCC[075]

AC18

VCC[076]

AD7

VCC[077]

AD9

VCC[078]

AD10

VCC[079]

AD12

VCC[080]

AD14

VCC[081]

AD15

VCC[082]

AD17

VCC[083]

AD18

VCC[084]

AE9

VCC[085]

AE10

VCC[086]

AE12

VCC[087]

AE13

VCC[088]

AE15

VCC[089]

AE17

VCC[090]

AE18

VCC[091]

AE20

VCC[092]

AF9

VCC[093]

AF10

VCC[094]

AF12

VCC[095]

AF14

VCC[096]

AF15

VCC[097]

AF17

VCC[098]

AF18

VCC[099]

AF20

VCC[100]
VCCP[01]

VCCP[02]
VCCP[03]
VCCP[04]
VCCP[05]
VCCP[06]
VCCP[07]
VCCP[08]
VCCP[09]
VCCP[10]
VCCP[11]
VCCP[12]
VCCP[13]
VCCP[14]
VCCP[15]
VCCP[16]

VCCA[01]
VCCA[02]

VID[0]
VID[1]
VID[2]
VID[3]
VID[4]
VID[5]
VID[6]

VCCSENSE

VSSSENSE

G21
V6
J6
K6
M6
J21
K21
M21
N21
N6
R21
R6
T21
T6
V21
W21

B26
C26

AD6
AF5
AE5
AF4
AE3
AF3
AE2

AF7

AE7

VID0
VID1
VID2
VID3
VID4
VID5
VID6

VCCSENSE

VSSSENSE

+1.05V_VCCP

220U_D2_4VY_R15M~D

220U_D2_4VY_R15M~D

1

+

+

C21

C21

2

CRB was 270uF

VID0 <47>
VID1 <47>
VID2 <47>
VID3 <47>
VID4 <47>
VID5 <47>
VID6 <47>

VCCSENSE <47>

VSSSENSE <47>

0.01U_0402_16V7K~D

0.01U_0402_16V7K~D

10U_0805_10V4Z~D

10U_0805_10V4Z~D

1

1

C22

C22

C23

C23

2

2

Length match within 25 mils, Z0=27.4 ohm

Place R75 and R76 near CPU

+VCC_CORE

1 2

R75 100_0402_1%~D

R75 100_0402_1%~D

1 2

R76 100_0402_1%~D

R76 100_0402_1%~D

Route VCCSENSE and VSSSENSE trace at

27.4 ohms, 7 mils spacing and the placement should be within 1 inch (max)

VCCSENSE

VSSSENSE

1 2

R833 27.4_0402_1%~D@R833 27.4_0402_1%~D@

Reserve for testing
only

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, MB A4042

SCHEMATIC, MB A4042

SCHEMATIC, MB A4042
401533

401533

401533

1

+1.5V_RUN

A

A

856Monday, December 17, 2007

856Monday, December 17, 2007

856Monday, December 17, 2007

A

of

of

of

5

4

3

2

1

+VCC_CORE

Place these inside
socket cavity on L8
(North side
Secondary)

D D

+VCC_CORE

Place these inside
socket cavity on L8
(Sorth side
Secondary)

+VCC_CORE

Place these inside
socket cavity on L8
(North side
Primary)

+VCC_CORE

Place these inside
socket cavity on L8
(Sorth side

C C

Primary)

1

C24

C24
10U_0805_4VAM~D

10U_0805_4VAM~D

2

1

C34

C34
10U_0805_4VAM~D

10U_0805_4VAM~D

2

1

C44

C44
10U_0805_4VAM~D

10U_0805_4VAM~D

2

1

C50

C50
10U_0805_4VAM~D

10U_0805_4VAM~D

2

1

C25

C25
10U_0805_4VAM~D

10U_0805_4VAM~D

2

1

C35

C35
10U_0805_4VAM~D

10U_0805_4VAM~D

2

1

C45

C45
10U_0805_4VAM~D

10U_0805_4VAM~D

2

1

C51

C51
10U_0805_4VAM~D

10U_0805_4VAM~D

2

1

C26

C26
10U_0805_4VAM~D

10U_0805_4VAM~D

2

1

C36

C36
10U_0805_4VAM~D

10U_0805_4VAM~D

2

1

C46

C46
10U_0805_4VAM~D

10U_0805_4VAM~D

2

1

C52

C52
10U_0805_4VAM~D

10U_0805_4VAM~D

2

1

C27

C27
10U_0805_4VAM~D

10U_0805_4VAM~D

2

1

C37

C37
10U_0805_4VAM~D

10U_0805_4VAM~D

2

1

C47

C47
10U_0805_4VAM~D

10U_0805_4VAM~D

2

1

C53

C53
10U_0805_4VAM~D

10U_0805_4VAM~D

2

1

C28

C28
10U_0805_4VAM~D

10U_0805_4VAM~D

2

1

C38

C38
10U_0805_4VAM~D

10U_0805_4VAM~D

2

1

C48

C48
10U_0805_4VAM~D

10U_0805_4VAM~D

2

1

C54

C54
10U_0805_4VAM~D

10U_0805_4VAM~D

2

1

C29

C29
10U_0805_4VAM~D

10U_0805_4VAM~D

2

1

C39

C39
10U_0805_4VAM~D

10U_0805_4VAM~D

2

1

C49

C49
10U_0805_4VAM~D

10U_0805_4VAM~D

2

1

C55

C55
10U_0805_4VAM~D

10U_0805_4VAM~D

2

1

C30

C30
10U_0805_4VAM~D

10U_0805_4VAM~D

2

1

C40

C40
10U_0805_4VAM~D

10U_0805_4VAM~D

2

10uF 0805 X6S -> 85 degree C

1

C31

C31
10U_0805_4VAM~D

10U_0805_4VAM~D

2

1

C41

C41
10U_0805_4VAM~D

10U_0805_4VAM~D

2

1

C32

C32
10U_0805_4VAM~D

10U_0805_4VAM~D

2

1

C42

C42
10U_0805_4VAM~D

10U_0805_4VAM~D

2

1

C33

C33
10U_0805_4VAM~D

10U_0805_4VAM~D

2

1

C43

C43
10U_0805_4VAM~D

10U_0805_4VAM~D

2

High Frequence Decoupling

Near VCORE regulator.

+VCC_CORE

220U_X_2VM_R7M~D

1

+

+

2

220U_X_2VM_R7M~D

@

@

C58

C58

1

+

+

2

220U_X_2VM_R7M~D

220U_X_2VM_R7M~D

@

@

C61

C61

220U_X_2VM_R7M~D

220U_X_2VM_R7M~D

1

+

+

2

220U_X_2VM_R7M~D

220U_X_2VM_R7M~D

1

1

+

+

+

C56

C56

+

C59

C59

2

2

220U_X_2VM_R7M~D

220U_X_2VM_R7M~D

C60

C60

1

+

+

2

220U_X_2VM_R7M~D

220U_X_2VM_R7M~D

C57

C57

ESR <= 1.5m ohm
Capacitor > 1320uF

B B

+1.05V_VCCP

1

C62

C62

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

2

A A

Board Bottom Side Board Top Side

1

C63

C63

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

2

1

C64

C64

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

2

5

1

C65

C65

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

2

1

C66

C66

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

2

4

1

C67

C67

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

2

Place these inside
socket cavity on L8
(North side
Secondary)

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, MB A4042

SCHEMATIC, MB A4042

SCHEMATIC, MB A4042

401533

401533

401533

956Tuesday, December 18, 2007

956Tuesday, December 18, 2007

956Tuesday, December 18, 2007

1

A

A

A

of

of

of

5

U2A

M11

N12

P13

N10

AD14

Y10
Y12
Y14

W2

AA8

AA13

AA9
AA11
AD11
AD10
AD13
AE12

AE9

AA2

AD8

AA3

AD3

AD7
AE14

AF3

AC1

AE3

AC3
AE11

AE8

AG2

AD6

C12

E11

A11

B11

12

R91

R91
221_0402_1%~D

221_0402_1%~D

12

1

2

F2
G8
F8
E6
G2
H6
H2
F6
D4
H3
M9

P2
R2

N9
M5
N2

R1
N5
N6

N8

M3
Y3

Y6

Y7

Y9

C5
E3

U2A

H_D#_0
H_D#_1
H_D#_2
H_D#_3
H_D#_4
H_D#_5
H_D#_6
H_D#_7
H_D#_8
H_D#_9
H_D#_10
H_D#_11

J1

H_D#_12

J2

H_D#_13
H_D#_14

J6

H_D#_15
H_D#_16

L2

H_D#_17
H_D#_18
H_D#_19

L6

H_D#_20
H_D#_21

J3

H_D#_22
H_D#_23
H_D#_24
H_D#_25
H_D#_26
H_D#_27
H_D#_28

L7

H_D#_29
H_D#_30
H_D#_31
H_D#_32
H_D#_33
H_D#_34
H_D#_35
H_D#_36
H_D#_37
H_D#_38
H_D#_39
H_D#_40
H_D#_41
H_D#_42
H_D#_43
H_D#_44
H_D#_45
H_D#_46
H_D#_47
H_D#_48
H_D#_49
H_D#_50
H_D#_51
H_D#_52
H_D#_53
H_D#_54
H_D#_55
H_D#_56
H_D#_57
H_D#_58
H_D#_59
H_D#_60
H_D#_61
H_D#_62
H_D#_63

H_SWING
H_RCOMP

H_CPURST#
H_CPUSLP#

H_AVREF
H_DVREF

CANTIGA ES_FCBGA1329~D

CANTIGA ES_FCBGA1329~D

3.01K_0402_1%~D

3.01K_0402_1%~D

0.1U_0402_16V7K~D

0.1U_0402_16V7K~D

C74

C74

1K_0402_1%~D

1K_0402_1%~D

+1.8V_MEM

R93

R93

R97

R97

HOST

HOST

12

R88

R88
1K_0402_1%~D

1K_0402_1%~D

12

12

H_ADSTB#_0
H_ADSTB#_1

H_DSTBN#_0
H_DSTBN#_1
H_DSTBN#_2
H_DSTBN#_3

H_DSTBP#_0
H_DSTBP#_1
H_DSTBP#_2
H_DSTBP#_3

1

2

1

2

H_D#[0..63]<8>

D D

C C

1 2

R82 24.9_0402_1%~D

R82 24.9_0402_1%~D

B B

A A

+H_VREF

R94

2K_0402_1%~D

2K_0402_1%~D

R94

H_RESET#<7>

H_CPUSLP#<8>

12

R90

R90
1K_0402_1%~D

1K_0402_1%~D

12

0.1U_0402_16V7K~D

0.1U_0402_16V7K~D

@C73

@

1

C73

2

H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63

H_SWNG
+H_RCOMP

H_RESET#
H_CPUSLP#

+H_VREF

+1.05V_VCCP+1.05V_VCCP

H_SWNG

100_0402_1%~D

100_0402_1%~D

R95

R95

5

H_A#_3
H_A#_4
H_A#_5
H_A#_6
H_A#_7
H_A#_8

H_A#_9
H_A#_10
H_A#_11
H_A#_12
H_A#_13
H_A#_14
H_A#_15
H_A#_16
H_A#_17
H_A#_18
H_A#_19
H_A#_20
H_A#_21
H_A#_22
H_A#_23
H_A#_24
H_A#_25
H_A#_26
H_A#_27
H_A#_28
H_A#_29
H_A#_30
H_A#_31
H_A#_32
H_A#_33
H_A#_34
H_A#_35

H_ADS#

H_BNR#

H_BPRI#

H_BREQ#

H_DEFER#

H_DBSY#

HPLL_CLK

HPLL_CLK#

H_DPWR#

H_DRDY#

H_HIT#

H_HITM#

H_LOCK#
H_TRDY#

H_DINV#_0
H_DINV#_1
H_DINV#_2
H_DINV#_3

H_REQ#_0
H_REQ#_1
H_REQ#_2
H_REQ#_3
H_REQ#_4

H_RS#_0
H_RS#_1
H_RS#_2

SMRCOMP_VOH

0.01U_0402_16V7K~D

0.01U_0402_16V7K~D

C71

C71

SMRCOMP_VOL

0.01U_0402_16V7K~D

0.01U_0402_16V7K~D

C75

C75

MCH_TSATN#

4

A14
C15
F16
H13
C18
M16
J13
P16
R16
N17
M13
E17
P17
F17
G20
B19
J16
E20
H16
J20
L17
A17
B17
L16
C21
J17
H20
B18
K17
B20
F21
K21
L20

H12
B16
G17
A9
F11
G12
E9
B10
AH7
AH6
J11
F9
H9
E12
H11
C9

J8
L3
Y13
Y1

L10
M7
AA5
AE6

L9
M8
AA6
AE5

B15
K13
F13
B13
B14

B6
F12
C8

2.2U_0603_6.3V6K~D

2.2U_0603_6.3V6K~D

1

C72

C72

2

2.2U_0603_6.3V6K~D

2.2U_0603_6.3V6K~D

1

C76

C76

2

R103

R103
0_0402_5%~D

0_0402_5%~D

4

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35

H_ADS#
H_ADSTB#0
H_ADSTB#1
H_BNR#
H_BPRI#
H_BR0#
H_DEFER#
H_DBSY#
CLK_MCH_BCLK
CLK_MCH_BCLK#
H_DPWR#
H_DRDY#
H_HIT#
H_HITM#
H_LOCK#
H_TRDY#

H_DINV#0
H_DINV#1
H_DINV#2
H_DINV#3

H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3

H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

H_RS#0
H_RS#1
H_RS#2

+1.05V_VCCP

12

R101

R101

54.9_0402_1%~D

54.9_0402_1%~D

1 2

12

R104

R104

330_0402_5%~D

330_0402_5%~D

MMST3904-7-F_SOT323-3~D

MMST3904-7-F_SOT323-3~D

H_A#[3..35] <7>

+1.8V_MEM

R79 80.6_0402_1%~DR79 80.6_0402_1%~D
R80 80.6_0402_1%~DR80 80.6_0402_1%~D

+V_DDR_MCH_REF

H_ADS# <7>

H_ADSTB#0 <7>

H_ADSTB#1 <7>
H_BNR# <7>
H_BPRI# <7>
H_BR0# <7>
H_DEFER# <7>
H_DBSY# <7>

CLK_MCH_BCLK <6>

CLK_MCH_BCLK# <6>
H_DPWR# <8>
H_DRDY# <7>

H_HIT# <7>
H_HITM# <7>
H_LOCK# <7>

H_TRDY# <7>

H_DINV#0 <8>
H_DINV#1 <8>
H_DINV#2 <8>
H_DINV#3 <8>

H_DSTBN#0 <8>
H_DSTBN#1 <8>
H_DSTBN#2 <8>
H_DSTBN#3 <8>

H_DSTBP#0 <8>
H_DSTBP#1 <8>
H_DSTBP#2 <8>
H_DSTBP#3 <8>

H_REQ#0 <7>
H_REQ#1 <7>
H_REQ#2 <7>
H_REQ#3 <7>
H_REQ#4 <7>

H_RS#0 <7>
H_RS#1 <7>
H_RS#2 <7>

499_0402_1%~D

499_0402_1%~D

+3.3V_RUN

1K_0402_5%~D

1K_0402_5%~D

12

R98

R98

2

B

B

C

C

2

B

B

Q3

Q3

E

E

MMST3904-7-F_SOT323-3~D

MMST3904-7-F_SOT323-3~D

3 1

Q4

Q4

E

E

+1.05V_M

R87

R87

12

C

C

3 1

1

2

12

1 2

1K_0402_5%~D

1K_0402_5%~D

R99

R99

3

M_ODT0<16>
M_ODT1<16>
M_ODT2<17>
M_ODT3<17>

T13PAD~D T13PAD~D

T25PAD~D T25PAD~D
T26PAD~D T26PAD~D
T27PAD~D T27PAD~D
T28PAD~D T28PAD~D
T29PAD~D T29PAD~D

T30PAD~D T30PAD~D

T31PAD~D T31PAD~D

T32PAD~D T32PAD~D
T33PAD~D T33PAD~D
T34PAD~D T34PAD~D
T35PAD~D T35PAD~D
T36PAD~D T36PAD~D

M_CLK_DDR0
M_CLK_DDR1
M_CLK_DDR2
M_CLK_DDR3

M_CLK_DDR#0
M_CLK_DDR#1
M_CLK_DDR#2
M_CLK_DDR#3

DDR_CKE0_DIMMA
DDR_CKE1_DIMMA
DDR_CKE2_DIMMB
DDR_CKE3_DIMMB

DDR_CS0_DIMMA#
DDR_CS1_DIMMA#
DDR_CS2_DIMMB#
DDR_CS3_DIMMB#

M_ODT0
M_ODT1
M_ODT2
M_ODT3

SMRCOMP
SMRCOMP#

SMRCOMP_VOH
SMRCOMP_VOL

+V_DDR_MCH_REF

SM_PWROK
TP_SM_DRAMRST#

CLK_MCH_3GPLL
CLK_MCH_3GPLL#

DMI_MRX_ITX_N0
DMI_MRX_ITX_N1
DMI_MRX_ITX_N2
DMI_MRX_ITX_N3

DMI_MRX_ITX_P0
DMI_MRX_ITX_P1
DMI_MRX_ITX_P2
DMI_MRX_ITX_P3

DMI_MTX_IRX_N0
DMI_MTX_IRX_N1
DMI_MTX_IRX_N2
DMI_MTX_IRX_N3

DMI_MTX_IRX_P0
DMI_MTX_IRX_P1
DMI_MTX_IRX_P2
DMI_MTX_IRX_P3

GFX_VID0
GFX_VID1
GFX_VID2
GFX_VID3
GFX_VID4

GFX_VR_ON

CL_CLK0
CL_DATA0
ICH_CL_PWROK
CL_RST0#
+CL_VREF

DDPC_CTRLCLK
DDPC_CTRLDATA

CLK_3GPLLREQ#
MCH_ICH_SYNC#

MCH_TSATN#

ICH_AZ_MCH_BITCLK
ICH_AZ_MCH_RST#
ICH_AZ_MCH_SDIN2
ICH_AZ_MCH_SDOUT
ICH_AZ_MCH_SYNC

1 2

R102 56_0402_5%~D R102 56_0402_5%~D

M_CLK_DDR0<16>
M_CLK_DDR1<16>
M_CLK_DDR2<17>
M_CLK_DDR3<17>

M_CLK_DDR#0<16>
M_CLK_DDR#1<16>
M_CLK_DDR#2<17>
M_CLK_DDR#3<17>

DDR_CKE0_DIMMA<16>
DDR_CKE1_DIMMA<16>
DDR_CKE2_DIMMB<17>
DDR_CKE3_DIMMB<17>

DDR_CS0_DIMMA#<16>
DDR_CS1_DIMMA#<16>
DDR_CS2_DIMMB#<17>
DDR_CS3_DIMMB#<17>

SMRCOMP

12

SMRCOMP#

12

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

MCH_TSATN_EC <37>

R81 499_0402_1%~D

R81 499_0402_1%~D

1 2

1

C69

C69

C68

C68

2

CLK_MCH_3GPLL<6>
CLK_MCH_3GPLL#<6>

DMI_MRX_ITX_N0<24>
DMI_MRX_ITX_N1<24>
DMI_MRX_ITX_N2<24>
DMI_MRX_ITX_N3<24>

DMI_MRX_ITX_P0<24>
DMI_MRX_ITX_P1<24>
DMI_MRX_ITX_P2<24>
DMI_MRX_ITX_P3<24>

DMI_MTX_IRX_N0<24>
DMI_MTX_IRX_N1<24>
DMI_MTX_IRX_N2<24>
DMI_MTX_IRX_N3<24>

DMI_MTX_IRX_P0<24>
DMI_MTX_IRX_P1<24>
DMI_MTX_IRX_P2<24>
DMI_MTX_IRX_P3<24>

1K_0402_1%~D

1K_0402_1%~D

R83

R83

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

1

2

CL_CLK0<24>
CL_DATA0<24>

ICH_CL_PWROK<24,38>

CL_RST0#<24>

C70

C70

DDPC_CTRLDATA<12>

CLK_3GPLLREQ#<6>
MCH_ICH_SYNC#<24>

THERMTRIP_MCH#

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

AP24
AT21
AV24
AU20

AR24
AR21
AU24
AV20

BC28
AY28
AY36
BB36

BA17
AY16
AV16
AR13

BD17
AY17

BF15

AY13
BG22

BH21

BF28

BH28
AV42

AR36

BF17

BC36

AE41
AE37
AE47
AH39

AE40
AE38
AE48
AH40

AE35
AE43
AE46
AH42

AD35
AE44

AF46

AH43

AH37
AH36
AN36

AJ35

AH34

U2B

U2B

B38
A38
E41
F41

F43
E43

B33
B32

G33

F33
E33

C34

N28
M28
G36

E36

K36

H36

B12

B28

B30

B29

C29

A28

SA_CK_0
SA_CK_1
SB_CK_0
SB_CK_1

SA_CK#_0
SA_CK#_1
SB_CK#_0
SB_CK#_1

SA_CKE_0
SA_CKE_1
SB_CKE_0
SB_CKE_1

SA_CS#_0
SA_CS#_1
SB_CS#_0
SB_CS#_1

SA_ODT_0
SA_ODT_1
SB_ODT_0
SB_ODT_1

SM_RCOMP
SM_RCOMP#

SM_RCOMP_VOH
SM_RCOMP_VOL

SM_VREF
SM_PWROK
SM_REXT
SM_DRAMRST#

DPLL_REF_CLK
DPLL_REF_CLK#
DPLL_REF_SSCLK
DPLL_REF_SSCLK#

PEG_CLK
PEG_CLK#

DMI_RXN_0
DMI_RXN_1
DMI_RXN_2
DMI_RXN_3

DMI_RXP_0
DMI_RXP_1
DMI_RXP_2
DMI_RXP_3

DMI_TXN_0
DMI_TXN_1
DMI_TXN_2
DMI_TXN_3

DMI_TXP_0
DMI_TXP_1
DMI_TXP_2
DMI_TXP_3

GFX_VID_0
GFX_VID_1
GFX_VID_2
GFX_VID_3
GFX_VID_4

GFX_VR_EN

CL_CLK
CL_DATA
CL_PWROK
CL_RST#
CL_VREF

DDPC_CTRLCLK
DDPC_CTRLDATA
SDVO_CTRLCLK
SDVO_CTRLDATA
CLKREQ#
ICH_SYNC#

TSATN#

HDA_BCLK
HDA_RST#
HDA_SDI
HDA_SDO
HDA_SYNC

+1.05V_VCCP

2

TP_MCH_RSVD1

M36

RSVD1
RSVD2
RSVD3
RSVD4
RSVD5
RSVD6
RSVD7
RSVD8

RSVD9
RSVD10
RSVD11
RSVD12
RSVD13

RSVD

RSVD

DDR CLK/ CONTROL/COMPENSATION

DDR CLK/ CONTROL/COMPENSATION

CLK

CLK

CFG

CFG

DMI

DMI

PM

PM

GRAPHICS VID

GRAPHICS VID

MEHDA

MEHDA

NC

NC

MISC

MISC

CANTIGA ES_FCBGA1329~D

CANTIGA ES_FCBGA1329~D

RSVD14
RSVD15

RSVD16
RSVD17

RSVD20

RSVD22
RSVD23
RSVD24
RSVD25

CFG_0

CFG_1

CFG_2

CFG_3

CFG_4

CFG_5

CFG_6

CFG_7

CFG_8

CFG_9
CFG_10
CFG_11
CFG_12
CFG_13
CFG_14
CFG_15
CFG_16
CFG_17
CFG_18
CFG_19
CFG_20

PM_SYNC#

PM_DPRSTP#
PM_EXT_TS#_0
PM_EXT_TS#_1

PWROK

RSTIN#

THERMTRIP#

DPRSLPVR

NC_1
NC_2
NC_3
NC_4
NC_5
NC_6
NC_7
NC_8

NC_9
NC_10
NC_11
NC_12
NC_13
NC_14
NC_15
NC_16
NC_17
NC_18
NC_19
NC_20
NC_21
NC_22
NC_23
NC_24
NC_25
NC_26

N36
R33
T33
AH9
AH10
AH12
AH13
K12
AL34
AK34
AN35
AM35
T24

B31
B2
M1

AY21

BG23
BF23
BH18
BF18

T25
R25
P25
P20
P24
C25
N24
M24
E21
C23
C24
N21
P21
T21
R20
M20
L21
H21
P29
R28
T28

R29
B7
N33
P32
AT40
AT11
T20
R32

BG48
BF48
BD48
BC48
BH47
BG47
BE47
BH46
BF46
BG45
BH44
BH43
BH6
BH5
BG4
BH3
BF3
BH2
BG2
BE2
BG1
BF1
BD1
BC1
F1
A47

TP_MCH_RSVD2
TP_MCH_RSVD3
TP_MCH_RSVD4
TP_MCH_RSVD5
TP_MCH_RSVD6
TP_MCH_RSVD7
TP_MCH_RSVD8
TP_MCH_RSVD9
ME_JTAG_TCK
ME_JTAG_TDI
ME_JTAG_TDO
ME_JTAG_TMS

TP_MCH_RSVD15
TP_MCH_RSVD16
TP_MCH_RSVD17

TP_MCH_RSVD20

TP_MCH_RSVD22
TP_MCH_RSVD23
TP_MCH_RSVD24
TP_MCH_RSVD25

CFG5
CFG6
CFG7

CFG9

CFG16

CFG19
CFG20

PM_SYNC#
H_DPRSTP#

PM_EXTTS#
ICH_PWRGD
PLTRST1#_R
THERMTRIP_MCH#
DPRSLPVR

PLTRST1#_R

PM_EXTTS#

SM_PWROK

T172PAD~DT172PAD~D
T173PAD~DT173PAD~D
T174PAD~DT174PAD~D
T175PAD~DT175PAD~D
T176PAD~DT176PAD~D
T177PAD~DT177PAD~D
T178PAD~DT178PAD~D
T179PAD~DT179PAD~D

R804 100_0402_5%~D@R804 100_0402_5%~D@

1 2

R805 100_0402_5%~D@R805 100_0402_5%~D@

1 2

R806 100_0402_5%~D@R806 100_0402_5%~D@

1 2

R807 100_0402_5%~D@R807 100_0402_5%~D@

1 2

T6 PAD~DT6 PAD~D
T7 PAD~DT7 PAD~D
T8 PAD~DT8 PAD~D

T9 PAD~DT9 PAD~D

T10 PAD~DT10 PAD~D
T11 PAD~DT11 PAD~D
T12 PAD~DT12 PAD~D
T182PAD~DT182PAD~D

CPU_MCH_BSEL0 <6,8>
CPU_MCH_BSEL1 <6,8>

CPU_MCH_BSEL2 <6,8>

T14 PAD~DT14 PAD~D
T15 PAD~DT15 PAD~D

CFG5 <12>
CFG6 <12>
CFG7 <12>

T16 PAD~DT16 PAD~D

CFG9 <12>

T17 PAD~DT17 PAD~D
T18 PAD~DT18 PAD~D
T19 PAD~DT19 PAD~D
T20 PAD~DT20 PAD~D
T21 PAD~DT21 PAD~D
T22 PAD~DT22 PAD~D

CFG16 <12>

T23 PAD~DT23 PAD~D
T24 PAD~DT24 PAD~D

CFG19 <12>

CFG20 <12>

PM_SYNC# <24>
H_DPRSTP# <8,23,47>

PM_EXTTS# <18>

ICH_PWRGD <24,41>

THERMTRIP_MCH# <18>

DPRSLPVR <24,47>

12

R85 10K_0402_5%~D

R85 10K_0402_5%~D

12

R86 0_0402_5%~DR86 0_0402_5%~D

Use for DDR3 signls,
if support DDR2 need
connect to GND

12

R100 100_0402_5%~DR100 100_0402_5%~D

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, MB A4042

SCHEMATIC, MB A4042

SCHEMATIC, MB A4042

401533

401533

401533

1

T5 PAD~DT5 PAD~D
T123PAD~DT123PAD~D
T124PAD~DT124PAD~D
T125PAD~DT125PAD~D
T126PAD~DT126PAD~D

Reserve 100ohm and Test
point for ME JTAG debug

+3.3V_RUN

PLTRST1# <22,32,51>

10 56Tuesday, December 18, 2007

10 56Tuesday, December 18, 2007

10 56Tuesday, December 18, 2007

of

of

1

of

A

A

A

5

4

3

2

1

D D

U2E

U2D

DDR_A_BS0<16>
DDR_A_BS1<16>
DDR_A_BS2<16>

DDR_A_RAS#<16>
DDR_A_CAS#<16>
DDR_A_WE#<16>

DDR_A_DM[0..7]<16>

C C

B B

DDR_A_DQS[0..7]<16>

DDR_A_DQS#[0..7]<16>

DDR_A_MA[0..14]<16>

DDR_A_BS0
DDR_A_BS1
DDR_A_BS2

DDR_A_RAS#
DDR_A_CAS#

DDR_A_DM0 DDR_A_D11
DDR_A_DM1
DDR_A_DM2
DDR_A_DM3
DDR_A_DM4
DDR_A_DM5
DDR_A_DM6
DDR_A_DM7

DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7
DDR_A_DQS#0
DDR_A_DQS#1
DDR_A_DQS#2
DDR_A_DQS#3
DDR_A_DQS#4
DDR_A_DQS#5
DDR_A_DQS#6
DDR_A_DQS#7

DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA14

BD21
BG18
AT25

BB20
BD20
AY20

AM37
AT41
AY41
AU39
BB12

AJ44
AT44
BA43
BC37

AW12

AM7

AJ43
AT43
BA44
BD37
AY12

AM8
BA21

BC24
BG24
BH24
BG25
BA24
BD24
BG27
BF25

AW24

BC21
BG26
BH26
BH17
AY25

AY6
AT7
AJ5

BC8
AU8

BD8
AU9

U2D

SA_BS_0
SA_BS_1
SA_BS_2

SA_RAS#
SA_CAS#
SA_WE#

SA_DM_0
SA_DM_1
SA_DM_2
SA_DM_3
SA_DM_4
SA_DM_5
SA_DM_6
SA_DM_7

SA_DQS_0
SA_DQS_1
SA_DQS_2
SA_DQS_3
SA_DQS_4
SA_DQS_5
SA_DQS_6
SA_DQS_7
SA_DQS#_0
SA_DQS#_1
SA_DQS#_2
SA_DQS#_3
SA_DQS#_4
SA_DQS#_5
SA_DQS#_6
SA_DQS#_7

SA_MA_0
SA_MA_1
SA_MA_2
SA_MA_3
SA_MA_4
SA_MA_5
SA_MA_6
SA_MA_7
SA_MA_8
SA_MA_9
SA_MA_10
SA_MA_11
SA_MA_12
SA_MA_13
SA_MA_14

SA_DQ_0
SA_DQ_1
SA_DQ_2
SA_DQ_3
SA_DQ_4
SA_DQ_5
SA_DQ_6
SA_DQ_7
SA_DQ_8

SA_DQ_9
SA_DQ_10
SA_DQ_11
SA_DQ_12
SA_DQ_13
SA_DQ_14
SA_DQ_15
SA_DQ_16
SA_DQ_17
SA_DQ_18
SA_DQ_19
SA_DQ_20
SA_DQ_21
SA_DQ_22
SA_DQ_23
SA_DQ_24
SA_DQ_25
SA_DQ_26
SA_DQ_27
SA_DQ_28
SA_DQ_29
SA_DQ_30
SA_DQ_31
SA_DQ_32
SA_DQ_33
SA_DQ_34
SA_DQ_35
SA_DQ_36
SA_DQ_37
SA_DQ_38
SA_DQ_39
SA_DQ_40
SA_DQ_41
SA_DQ_42
SA_DQ_43
SA_DQ_44
SA_DQ_45
SA_DQ_46
SA_DQ_47
SA_DQ_48
SA_DQ_49
SA_DQ_50
SA_DQ_51

DDR SYSTEM MEMORY A

DDR SYSTEM MEMORY A

SA_DQ_52
SA_DQ_53
SA_DQ_54
SA_DQ_55
SA_DQ_56
SA_DQ_57
SA_DQ_58
SA_DQ_59
SA_DQ_60
SA_DQ_61
SA_DQ_62

CANTIGA ES_FCBGA1329~D

CANTIGA ES_FCBGA1329~D

SA_DQ_63

AJ38
AJ41
AN38
AM38
AJ36
AJ40
AM44
AM42
AN43
AN44
AU40
AT38
AN41
AN39
AU44
AU42
AV39
AY44
BA40
BD43
AV41
AY43
BB41
BC40
AY37
BD38
AV37
AT36
AY38
BB38
AV36
AW36
BD13
AU11
BC11
BA12
AU13
AV13
BD12
BC12
BB9
BA9
AU10
AV9
BA11
BD9
AY8
BA6
AV5
AV7
AT9
AN8
AU5
AU6
AT5
AN10
AM11
AM5
AJ9
AJ8
AN12
AM13
AJ11
AJ12

DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6DDR_A_WE#
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10

DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63

DDR_B_BS0<17>
DDR_B_BS1<17>
DDR_B_BS2<17>

DDR_B_RAS#<17>
DDR_B_CAS#<17>
DDR_B_WE#<17>

DDR_B_DM[0..7]<17>

DDR_B_DQS[0..7]<17>

DDR_B_DQS#[0..7]<17>

DDR_B_MA[0..14]<17>

DDR_B_BS0
DDR_B_BS1
DDR_B_BS2

DDR_B_RAS#
DDR_B_CAS#
DDR_B_WE#

DDR_B_DM0
DDR_B_DM1
DDR_B_DM2
DDR_B_DM3
DDR_B_DM4
DDR_B_DM5
DDR_B_DM6
DDR_B_DM7

DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4
DDR_B_DQS5
DDR_B_DQS6
DDR_B_DQS7
DDR_B_DQS#0
DDR_B_DQS#1
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS#4
DDR_B_DQS#5
DDR_B_DQS#6
DDR_B_DQS#7

DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13
DDR_B_MA14

BC16
BB17
BB33

AU17
BG16
BF14

AM47
AY47
BD40
BF35
BG11

AL47
AV48
BG41
BG37

AL46
AV47
BH41
BH37

BG9

AV17
BA25
BC25
AU25

AW25

BB28
AU28

AW28

AT33
BD33
BB16

AW33

AY33
BH15
AU33

BA3
AP1
AK2

BH9
BB2
AU1
AN6

BC2
AT2
AN5

U2E

SB_BS_0
SB_BS_1
SB_BS_2

SB_RAS#
SB_CAS#
SB_WE#

SB_DM_0
SB_DM_1
SB_DM_2
SB_DM_3
SB_DM_4
SB_DM_5
SB_DM_6
SB_DM_7

SB_DQS_0
SB_DQS_1
SB_DQS_2
SB_DQS_3
SB_DQS_4
SB_DQS_5
SB_DQS_6
SB_DQS_7
SB_DQS#_0
SB_DQS#_1
SB_DQS#_2
SB_DQS#_3
SB_DQS#_4
SB_DQS#_5
SB_DQS#_6
SB_DQS#_7

SB_MA_0
SB_MA_1
SB_MA_2
SB_MA_3
SB_MA_4
SB_MA_5
SB_MA_6
SB_MA_7
SB_MA_8
SB_MA_9
SB_MA_10
SB_MA_11
SB_MA_12
SB_MA_13
SB_MA_14

SB_DQ_0
SB_DQ_1
SB_DQ_2
SB_DQ_3
SB_DQ_4
SB_DQ_5
SB_DQ_6
SB_DQ_7
SB_DQ_8

SB_DQ_9
SB_DQ_10
SB_DQ_11
SB_DQ_12
SB_DQ_13
SB_DQ_14
SB_DQ_15
SB_DQ_16
SB_DQ_17
SB_DQ_18
SB_DQ_19
SB_DQ_20
SB_DQ_21
SB_DQ_22
SB_DQ_23
SB_DQ_24
SB_DQ_25
SB_DQ_26
SB_DQ_27
SB_DQ_28
SB_DQ_29
SB_DQ_30
SB_DQ_31
SB_DQ_32
SB_DQ_33
SB_DQ_34
SB_DQ_35
SB_DQ_36
SB_DQ_37
SB_DQ_38
SB_DQ_39
SB_DQ_40
SB_DQ_41
SB_DQ_42
SB_DQ_43
SB_DQ_44
SB_DQ_45
SB_DQ_46
SB_DQ_47
SB_DQ_48
SB_DQ_49
SB_DQ_50
SB_DQ_51
SB_DQ_52

DDR SYSTEM MEMORY B

DDR SYSTEM MEMORY B

SB_DQ_53
SB_DQ_54
SB_DQ_55
SB_DQ_56
SB_DQ_57
SB_DQ_58
SB_DQ_59
SB_DQ_60
SB_DQ_61
SB_DQ_62

CANTIGA ES_FCBGA1329~D

CANTIGA ES_FCBGA1329~D

SB_DQ_63

AH46
AP47
AP46
AJ46
AJ48
AM48
AP48
AU47
AU46
BA48
AY48
AT47
AR47
BA47
BC47
BC46
BC44
BG43
BF43
BE45
BC41
BF40
BF41
BG38
BF38
BH35
BG35
BH40
BG39
BG34
BH34
BH14
BG12
BH11
BG8
BH12
BF11
BF8
BG7
BC5
BC6
AY3
AY1
BF6
BF5
BA1
BD3
AV2
AU3
AR3
AN2
AY2
AV1
AP3
AR1
AL1
AL2
AJ1
AH1
AM2
AM3
AH3
AJ3

DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63

DDR_B_D0

AK47

DDR_B_D[0..63] <17>DDR_A_D[0..63] <16>

A A

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, MB A4042

SCHEMATIC, MB A4042

SCHEMATIC, MB A4042

401533

401533

401533

11 56Tuesday, December 18, 2007

11 56Tuesday, December 18, 2007

11 56Tuesday, December 18, 2007

of

of

1

of

A

A

A

5

4

3

2

1

+VCC_PEG

U2C

D D

C C

B B

U2C

L32
G32
M32

M33

K33

J33

M29
C44

B43

E37

E38
C41
C40

B37

A37
H47

E46
G40

A40
H48

D45

F40

B40

A41
H38
G37

J37

B42
G38

F37

K37

F25
H25

K25
H24

C31

E32

E28
G28

J28
G29
H32

J32

J29

E29

L29

L_BKLT_CTRL
L_BKLT_EN
L_CTRL_CLK

L_CTRL_DATA
L_DDC_CLK
L_DDC_DATA

L_VDD_EN
LVDS_IBG
LVDS_VBG
LVDS_VREFH
LVDS_VREFL
LVDSA_CLK#
LVDSA_CLK
LVDSB_CLK#
LVDSB_CLK

LVDSA_DATA#_0
LVDSA_DATA#_1
LVDSA_DATA#_2
LVDSA_DATA#_3

LVDSA_DATA_0
LVDSA_DATA_1
LVDSA_DATA_2
LVDSA_DATA_3

LVDSB_DATA#_0
LVDSB_DATA#_1
LVDSB_DATA#_2
LVDSB_DATA#_3

LVDSB_DATA_0
LVDSB_DATA_1
LVDSB_DATA_2
LVDSB_DATA_3

TVA_DAC
TVB_DAC
TVC_DAC

TV_RTN

TV_DCONSEL_0
TV_DCONSEL_1

CRT_BLUE
CRT_GREEN
CRT_RED
CRT_IRTN
CRT_DDC_CLK

CRT_DDC_DATA
CRT_HSYNC
CRT_TVO_IREF
CRT_VSYNC

PEGCOMP

PEG_RX#_0
PEG_RX#_1
PEG_RX#_2
PEG_RX#_3
PEG_RX#_4
PEG_RX#_5
PEG_RX#_6
PEG_RX#_7
PEG_RX#_8
PEG_RX#_9

PEG_RX_0
PEG_RX_1
PEG_RX_2
PEG_RX_3
PEG_RX_4
PEG_RX_5
PEG_RX_6
PEG_RX_7
PEG_RX_8

PEG_RX_9
PEG_RX_10
PEG_RX_11
PEG_RX_12
PEG_RX_13
PEG_RX_14
PEG_RX_15

PEG_TX#_0
PEG_TX#_1
PEG_TX#_2
PEG_TX#_3
PEG_TX#_4
PEG_TX#_5
PEG_TX#_6
PEG_TX#_7
PEG_TX#_8
PEG_TX#_9

PEG_TX_0

PEG_TX_1

PEG_TX_2

PEG_TX_3

PEG_TX_4

PEG_TX_5

PEG_TX_6

PEG_TX_7

PEG_TX_8

PEG_TX_9
PEG_TX_10
PEG_TX_11
PEG_TX_12
PEG_TX_13
PEG_TX_14
PEG_TX_15

T37
T36

PEG_MRX_GTX_N0

H44

PEG_MRX_GTX_N1

J46

PEG_MRX_GTX_N2

L44

PEG_MRX_GTX_N3

L40

PEG_MRX_GTX_N4

N41

PEG_MRX_GTX_N5

P48

PEG_MRX_GTX_N6

N44

PEG_MRX_GTX_N7

T43

PEG_MRX_GTX_N8

U43

PEG_MRX_GTX_N9

Y43

PEG_MRX_GTX_N10

Y48

PEG_MRX_GTX_N11

Y36

PEG_MRX_GTX_N12

AA43

PEG_MRX_GTX_N13

AD37

PEG_MRX_GTX_N14

AC47

PEG_MRX_GTX_N15

AD39

PEG_MRX_GTX_P0

H43

PEG_MRX_GTX_P1

J44

PEG_MRX_GTX_P2

L43

PEG_MRX_GTX_P3

L41

PEG_MRX_GTX_P4

N40

PEG_MRX_GTX_P5

P47

PEG_MRX_GTX_P6

N43

PEG_MRX_GTX_P7

T42

PEG_MRX_GTX_P8

U42

PEG_MRX_GTX_P9

Y42

PEG_MRX_GTX_P10

W47

PEG_MRX_GTX_P11

Y37

PEG_MRX_GTX_P12

AA42

PEG_MRX_GTX_P13

AD36

PEG_MRX_GTX_P14

AC48

PEG_MRX_GTX_P15

AD40

PEG_MTX_GRX_C_N0

J41

PEG_MTX_GRX_C_N1

M46

PEG_MTX_GRX_C_N2

M47

PEG_MTX_GRX_C_N3

M40

PEG_MTX_GRX_C_N4

M42

PEG_MTX_GRX_C_N5

R48

PEG_MTX_GRX_C_N6

N38

PEG_MTX_GRX_C_N7

T40

PEG_MTX_GRX_C_N8

U37

PEG_MTX_GRX_C_N9

U40

PEG_MTX_GRX_C_N10

Y40

PEG_MTX_GRX_C_N11

AA46

PEG_MTX_GRX_C_N12

AA37

PEG_MTX_GRX_C_N13

AA40

PEG_MTX_GRX_C_N14

AD43

PEG_MTX_GRX_C_N15

AC46

PEG_MTX_GRX_C_P0

J42

PEG_MTX_GRX_C_P1

L46

PEG_MTX_GRX_C_P2

M48

PEG_MTX_GRX_C_P3

M39

PEG_MTX_GRX_C_P4

M43

PEG_MTX_GRX_C_P5

R47

PEG_MTX_GRX_C_P6

N37

PEG_MTX_GRX_C_P7

T39

PEG_MTX_GRX_C_P8

U36

PEG_MTX_GRX_C_P9

U39

PEG_MTX_GRX_C_P10

Y39

PEG_MTX_GRX_C_P11

Y46

PEG_MTX_GRX_C_P12

AA36

PEG_MTX_GRX_C_P13

AA39

PEG_MTX_GRX_C_P14

AD42

PEG_MTX_GRX_C_P15

AD46

PEG_COMPI

PEG_COMPO

LVDS

LVDS

PEG_RX#_10
PEG_RX#_11
PEG_RX#_12
PEG_RX#_13
PEG_RX#_14
PEG_RX#_15

TV

TV

PEG_TX#_10
PEG_TX#_11
PEG_TX#_12

PCI-EXPRESS GRAPHICS

PCI-EXPRESS GRAPHICS

PEG_TX#_13
PEG_TX#_14
PEG_TX#_15

VGA

VGA

CANTIGA ES_FCBGA1329~D

CANTIGA ES_FCBGA1329~D

12

R105

R105

49.9_0402_1%~D

49.9_0402_1%~D

PEG_MRX_GTX_N[0..15] <51>

PEG_MRX_GTX_P[0..15] <51>

PEG_MTX_GRX_P[0..15]
PEG_MTX_GRX_N[0..15]

PEG_MTX_GRX_C_P0
PEG_MTX_GRX_C_N0 PEG_MTX_GRX_N0

PEG_MTX_GRX_C_P1
PEG_MTX_GRX_C_N1

PEG_MTX_GRX_C_P2
PEG_MTX_GRX_C_N2

PEG_MTX_GRX_C_P3
PEG_MTX_GRX_C_N3

PEG_MTX_GRX_C_P4
PEG_MTX_GRX_C_N4

PEG_MTX_GRX_C_P5
PEG_MTX_GRX_C_N5

PEG_MTX_GRX_C_P6
PEG_MTX_GRX_C_N6

PEG_MTX_GRX_C_P7
PEG_MTX_GRX_C_N7

PEG_MTX_GRX_C_P8
PEG_MTX_GRX_C_N8

PEG_MTX_GRX_C_P9
PEG_MTX_GRX_C_N9

PEG_MTX_GRX_C_P10
PEG_MTX_GRX_C_N10

PEG_MTX_GRX_C_P11
PEG_MTX_GRX_C_N11

PEG_MTX_GRX_C_P12
PEG_MTX_GRX_C_N12

PEG_MTX_GRX_C_P13
PEG_MTX_GRX_C_N13

PEG_MTX_GRX_C_P14
PEG_MTX_GRX_C_N14

PEG_MTX_GRX_C_P15
PEG_MTX_GRX_C_N15

PEG_MTX_GRX_P[0..15] <51>
PEG_MTX_GRX_N[0..15] <51>

CFG5 DMI X2 Select

iTPM Host

CFG6

Interface
Management

CFG7

Engine Crypto
Strap

PCI Express

CFG9

Graphic Lane

FSB Dynamic

CFG16

ODT

CFG19

DMI Lane
Reversal

Digital Display

CFG20

Port
Concurrent
Operation

SDVO_CRTL_DATA Low=No SDVO Device Present

DDPC_CTRLDATA

C77 0.1U_0402_10V7K~DC77 0.1U_0402_10V7K~D

12

C78 0.1U_0402_10V7K~DC78 0.1U_0402_10V7K~D

C79 0.1U_0402_10V7K~DC79 0.1U_0402_10V7K~D

12

C81 0.1U_0402_10V7K~DC81 0.1U_0402_10V7K~D

12

C83 0.1U_0402_10V7K~DC83 0.1U_0402_10V7K~D

12

C85 0.1U_0402_10V7K~DC85 0.1U_0402_10V7K~D

12

C87 0.1U_0402_10V7K~DC87 0.1U_0402_10V7K~D

12

C89 0.1U_0402_10V7K~DC89 0.1U_0402_10V7K~D

12

C91 0.1U_0402_10V7K~DC91 0.1U_0402_10V7K~D

12

C93 0.1U_0402_10V7K~D C93 0.1U_0402_10V7K~D

1 2

C95 0.1U_0402_10V7K~D C95 0.1U_0402_10V7K~D

1 2

C97 0.1U_0402_10V7K~D C97 0.1U_0402_10V7K~D

1 2

C99 0.1U_0402_10V7K~D C99 0.1U_0402_10V7K~D

1 2

C101 0.1U_0402_10V7K~D C101 0.1U_0402_10V7K~D

1 2

C103 0.1U_0402_10V7K~D C103 0.1U_0402_10V7K~D

1 2

C105 0.1U_0402_10V7K~D C105 0.1U_0402_10V7K~D

1 2

C107 0.1U_0402_10V7K~D C107 0.1U_0402_10V7K~D

1 2

12

C80 0.1U_0402_10V7K~DC80 0.1U_0402_10V7K~D

12

C82 0.1U_0402_10V7K~DC82 0.1U_0402_10V7K~D

12

C84 0.1U_0402_10V7K~DC84 0.1U_0402_10V7K~D

12

C86 0.1U_0402_10V7K~DC86 0.1U_0402_10V7K~D

12

C88 0.1U_0402_10V7K~DC88 0.1U_0402_10V7K~D

12

C90 0.1U_0402_10V7K~DC90 0.1U_0402_10V7K~D

12

C92 0.1U_0402_10V7K~DC92 0.1U_0402_10V7K~D

12

C94 0.1U_0402_10V7K~D C94 0.1U_0402_10V7K~D

1 2

C96 0.1U_0402_10V7K~D C96 0.1U_0402_10V7K~D

1 2

C98 0.1U_0402_10V7K~D C98 0.1U_0402_10V7K~D

1 2

C100 0.1U_0402_10V7K~D C100 0.1U_0402_10V7K~D

1 2

C102 0.1U_0402_10V7K~D C102 0.1U_0402_10V7K~D

1 2

C104 0.1U_0402_10V7K~D C104 0.1U_0402_10V7K~D

1 2

C106 0.1U_0402_10V7K~D C106 0.1U_0402_10V7K~D

1 2

C108 0.1U_0402_10V7K~D C108 0.1U_0402_10V7K~D

1 2

Strap Pin Table

Low = DMI x 2
High = DMI x 4 (Default)
Low = iTPM enable
High = iTPM disable(Defult)
Low = TLS cipher suite with no confidentiality
High = TLS cipher suite with

confidentiality(Default)
Low = Reverse Lane

High = Normal Operation(Default)

Low=Dynamic ODT Disable
High=Dynamic ODT Enable(default)
Low=Normal (default)
High=Lane Reversed
Low=Only digital display port (SDVO/DP/iHDMI) or

PCIe is operational (default)
High = Digital display port (SDVO/DP/iHDMI) and
PCIe are operating simultaneously via the PEG
port

(default)
High=SDVO Device Present

Low=DisplayPort disabled (default)
High=DisplayPort device present

PEG_MTX_GRX_P0

PEG_MTX_GRX_P1
PEG_MTX_GRX_N1

PEG_MTX_GRX_P2
PEG_MTX_GRX_N2

PEG_MTX_GRX_P3
PEG_MTX_GRX_N3

PEG_MTX_GRX_P4
PEG_MTX_GRX_N4

PEG_MTX_GRX_P5
PEG_MTX_GRX_N5

PEG_MTX_GRX_P6
PEG_MTX_GRX_N6

PEG_MTX_GRX_P7
PEG_MTX_GRX_N7

PEG_MTX_GRX_P8
PEG_MTX_GRX_N8

PEG_MTX_GRX_P9
PEG_MTX_GRX_N9

PEG_MTX_GRX_P10
PEG_MTX_GRX_N10

PEG_MTX_GRX_P11
PEG_MTX_GRX_N11

PEG_MTX_GRX_P12
PEG_MTX_GRX_N12

PEG_MTX_GRX_P13
PEG_MTX_GRX_N13

PEG_MTX_GRX_P14
PEG_MTX_GRX_N14

PEG_MTX_GRX_P15
PEG_MTX_GRX_N15

DDPC_CTRLDATA<10>

R106 2.21K_0402_1%~D@R106 2.21K_0402_1%~D@
R107 2.21K_0402_1%~D@R107 2.21K_0402_1%~D@
R108 2.21K_0402_1%~D@R108 2.21K_0402_1%~D@
R109 2.21K_0402_1%~D@R109 2.21K_0402_1%~D@
R110 2.21K_0402_1%~D@R110 2.21K_0402_1%~D@

1 2
1 2
1 2
1 2
1 2

CFG5<10>
CFG6<10>
CFG7<10>
CFG9<10>
CFG16<10>

CFG[5:16] have internal pullup

R111 4.02K_0402_1%~D@R111 4.02K_0402_1%~D@
R112 4.02K_0402_1%~D@R112 4.02K_0402_1%~D@
R113 4.02K_0402_1%~D@R113 4.02K_0402_1%~D@

1 2
1 2
1 2

CFG19<10>
CFG20<10>

CFG[19:20] have internal pulldown

+3.3V_RUN

A A

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, MB A4042

SCHEMATIC, MB A4042

SCHEMATIC, MB A4042

401533

401533

401533

12 56Tuesday, December 18, 2007

12 56Tuesday, December 18, 2007

12 56Tuesday, December 18, 2007

of

of

1

of

A

A

A

5

220U_D2_4VY_R15M~D

220U_D2_4VY_R15M~D

C109

C109

4.7U_0603_6.3V6M~D

4.7U_0603_6.3V6M~D

1

2

12

C136

C136

+VCC_PEG

+VCC_DMI

C142

C142

1

2

C115

C115

+VCC_AXF

1

2

0.47U_0402_10V4Z~D

0.47U_0402_10V4Z~D
C143

C143

0.47U_0402_10V4Z~D

0.47U_0402_10V4Z~D

1

2

2.2U_0603_10V7K~D

2.2U_0603_10V7K~D

1

2

10U_0805_4VAM~D

10U_0805_4VAM~D

@C125

@

C125

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

1

2

1

2

+1.05V_VCCP

C110

C110

C116

C116

1U_0603_10V4Z~D

1U_0603_10V4Z~D

1

2

+1.8V_SM_CK

C137

C137

GMCH_VTTLF1
GMCH_VTTLF2
GMCH_VTTLF3

0.47U_0402_10V4Z~D

0.47U_0402_10V4Z~D
C144

C144

CRB 270uF

1

+

+

2

D D

4.7U_0603_6.3V6M~D

4.7U_0603_6.3V6M~D

1

C114

C114

2

+1.05V_M

C C

R118

R118
0_1210_5%~D

0_1210_5%~D

+3.3V_RUN

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

1

B B

2

0.47U_0402_10V4Z~D

0.47U_0402_10V4Z~D

1

2

C126

C126

BF21
BH20
BG20
BF20

AH48
AF48
AH47
AG47

AB2

U13
T13
U12
T12
U11
T11
U10
T10

U9

T9

U8

T8

U7

T7

U6

T6

U5

T5
V3

U3

V2

U2

T2
V1

U1

B22
B21
A21

K47
C35

B35
A35

V48
U48
V47
U47
U46

A8
L1

U2H

U2H

VTT_1
VTT_2
VTT_3
VTT_4
VTT_5
VTT_6
VTT_7
VTT_8
VTT_9
VTT_10
VTT_11
VTT_12
VTT_13
VTT_14
VTT_15
VTT_16
VTT_17
VTT_18
VTT_19
VTT_20
VTT_21
VTT_22
VTT_23
VTT_24
VTT_25

VCC_AXF_1
VCC_AXF_2
VCC_AXF_3

VCC_SM_CK_1
VCC_SM_CK_2
VCC_SM_CK_3
VCC_SM_CK_4

VCC_TX_LVDS
VCC_HV_1

VCC_HV_2
VCC_HV_3

VCC_PEG_1
VCC_PEG_2
VCC_PEG_3
VCC_PEG_4
VCC_PEG_5

VCC_DMI_1
VCC_DMI_2
VCC_DMI_3
VCC_DMI_4

VTTLF1
VTTLF2
VTTLF3

VTT

VTT

POWER

POWER

AXF

AXF

SM CK

SM CK

HV

HV

PEG

PEG

DMI

DMI

VTTLF

VTTLF

VCCA_CRT_DAC_1
VCCA_CRT_DAC_2

VCCA_DAC_BG
VSSA_DAC_BG

CRTPLLA PEGA SM

CRTPLLA PEGA SM

VCCA_DPLLA
VCCA_DPLLB

VCCA_HPLL
VCCA_MPLL

VCCA_LVDS
VSSA_LVDS

VCCA_PEG_BG

A LVDS

A LVDS

VCCA_PEG_PLL

VCCA_SM_1
VCCA_SM_2
VCCA_SM_3
VCCA_SM_4
VCCA_SM_5
VCCA_SM_6
VCCA_SM_7
VCCA_SM_8
VCCA_SM_9

VCCA_SM_CK_1
VCCA_SM_CK_2
VCCA_SM_CK_3
VCCA_SM_CK_4

VCCA_SM_CK_5
VCCA_SM_CK_NCTF_1
VCCA_SM_CK_NCTF_2
VCCA_SM_CK_NCTF_3
VCCA_SM_CK_NCTF_4
VCCA_SM_CK_NCTF_5

A CK

A CK

VCCA_SM_CK_NCTF_6
VCCA_SM_CK_NCTF_7
VCCA_SM_CK_NCTF_8

VCCA_TV_DAC_1
VCCA_TV_DAC_2

TV

TV

VCC_HDA

HDA

HDA

VCCD_TVDAC

VCCD_QDAC

VCCD_HPLL

VCCD_PEG_PLL

D TV/CRT

D TV/CRT

VCCD_LVDS_1
VCCD_LVDS_2

LVDS

LVDS

CANTIGA ES_FCBGA1329~D

CANTIGA ES_FCBGA1329~D

B27
A26

A25
B25

F47
L48
AD1
AE1

J48
J47

AD48

AA48

AR20
AP20
AN20
AR17
AP17
AN17
AT16
AR16
AP16

AP28
AN28
AP25
AN25
AN24
AM28
AM26
AM25
AL25
AM24
AL24
AM23
AL23

B24
A24

A32

M25
L28
AF1
AA47

M38
L37

4

+1.05V_M_HPLL
+1.05V_M_MPLL

+VCCA_PEG_BG

+1.05V_M_PEGPLL

+1.05V_M_SM_CK

1U_0603_10V4Z~D

1U_0603_10V4Z~D

1

2

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

1

2

+1.5V_RUN

C121

C121

C127

C127

1 2

R778 0_0402_5%~DR778 0_0402_5%~D

1 2

R779 0_0402_5%~D@R779 0_0402_5%~D@

1

C117

C117

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

2

+1.05V_M_A_SM

22U_0805_6.3V6M~D

22U_0805_6.3V6M~D

4.7U_0603_6.3V6M~D

4.7U_0603_6.3V6M~D

1

1

C123

C123

C122

C122

2

2

22U_0805_6.3V6M~D

22U_0805_6.3V6M~D

2.2U_0603_6.3V6K~D

2.2U_0603_6.3V6K~D
R119 0_1210_5%~D

R119 0_1210_5%~D

@C129

@

1

1

C128

C128

C129

2

2

1

C998

C998

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

2

+1.05V_M_PEGPLL

1

2

1 2

22U_0805_6.3V6M~D

22U_0805_6.3V6M~D

@C124

@

1

C124

2

1 2

+1.05V_M

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

C141

C141

R116

R116

0_0805_5%~D

0_0805_5%~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

1

C140

C140

2

+1.05V_M

1

+

+

2

+1.05V_M

3

+1.5V_RUN
+3.3V_RUN

100U_D2E_6.3VM_R15M~D

100U_D2E_6.3VM_R15M~D

C120

C120

+1.5V_RUN

0.01U_0402_25V7K~D

0.01U_0402_25V7K~D

2

1

C138

C138

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

1

2

C139

C139

220U_D2_4VY_R15M~D

220U_D2_4VY_R15M~D

+VCC_PEG

220U_D2_4VY_R15M~D

220U_D2_4VY_R15M~D

1

+

+

C111

C111

2

+1.05V_M

C118

C118

10U_0805_4VAM~D

10U_0805_4VAM~D

+1.05V_M_HPLL

+VCC_DMI

1

+

C145

@+C145

@

2

4.7U_0603_6.3V6M~D

4.7U_0603_6.3V6M~D

22U_0805_6.3V6M~D

22U_0805_6.3V6M~D

1

1

C112

C112

2

2

L3

BLM21PG221SN1D_0805~D L3BLM21PG221SN1D_0805~D

1 2

12

R117

R117

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

4.7U_0603_6.3V6M~D

4.7U_0603_6.3V6M~D

1

1

C131

C131

C130

C130

2

2

L6

@L6

@

LBC2518T91NM_1210~D

LBC2518T91NM_1210~D

2

1 2

R114

R114
0_1210_5%~D

0_1210_5%~D

1 2

R115

@R115

@

C113

C113

0_1210_5%~D

0_1210_5%~D

+1.05V_M_PEGPLL

1_0402_5%~D

1_0402_5%~D

+1.05V_M +1.05V_M

L4

12

BLM18AG121SN1D_0603~D L4BLM18AG121SN1D_0603~D

12

PJP21

PJP21
PAD-OPEN1x1m

PAD-OPEN1x1m

12

+VCC_PEG

+1.05V_M

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

1

2

+1.05V_M

+1.05V_VCCP

Follow ERB,CRB option
to select +1.05V_M or
+1.05V_VCCP

C119

C119

139.2mA Max.24mA Max.

+1.05V_M_MPLL

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

1

2

C132

C132

1

L5

L5
LQH32CNR15M33L_1210~D

LQH32CNR15M33L_1210~D
R120

R120
0_0603_5%~D

0_0603_5%~D

1 2
1

C133

C133
22U_0805_6.3VAM~D

22U_0805_6.3VAM~D

2

12

+1.8V_MEM +1.8V_SM_CK

A A

L7

L7
LQM21FN1R0N00 _0805~D

LQM21FN1R0N00 _0805~D

Rdc=0.1~0.2,rated
current=220mA(MAX)

12

C147

C147

10U_0805_4VAM~D

10U_0805_4VAM~D

12

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

1_0603_5%~D

1_0603_5%~D

12

R121

R121

1

C146

C146

2

5

D1

D1

RB751V_SOD323-2~D

RB751V_SOD323-2~D

2 1

4

+1.05V_VCCP/+3.3V_RUN

Follow CRB to
VCC_HV(C35,B35,A35)

1 2

R122

R122

10_0603_5%~D

10_0603_5%~D

+3.3V_RUN+1.05V_VCCP

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, MB A4042

SCHEMATIC, MB A4042

SCHEMATIC, MB A4042

401533

401533

401533

A

A

13 56Tuesday, December 18, 2007

13 56Tuesday, December 18, 2007

13 56Tuesday, December 18, 2007

1

A

of

of

of

5

+1.05V_M

D D

CRB 270uF

Layout Note:
Place close to GMCH

C C

B B

A A

22U_0805_6.3VAM~D

22U_0805_6.3VAM~D

220U_D2_4VY_R15M~D

220U_D2_4VY_R15M~D

1

+

+

2

C153

C153

C152

C152

1

2

0.22U_0402_10V4Z~D

0.22U_0402_10V4Z~D

C155

C155

1

2

Layout Note:
Inside GMCH cavity.

0.22U_0402_10V4Z~D

0.22U_0402_10V4Z~D

1

C154

C154

2

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

C156

C156

1

2

1 2

R123

R123
0_0402_5%~D

0_0402_5%~D

AG34
AC34
AB34
AA34

AM33

AK33

AJ33
AG33
AF33

AE33
AC33
AA33

W33

AH28
AF28
AC28
AA28

AJ26
AG26
AE26
AC26
AH25
AG25
AF25
AG24

AJ23
AH23
AF23

U2F

U2F

VCC_1
VCC_2
VCC_3
VCC_4

Y34

VCC_5

V34

VCC_6

U34

VCC_7
VCC_8
VCC_9
VCC_10
VCC_11
VCC_12

VCC_13
VCC_14
VCC_15

Y33

VCC_16
VCC_17

V33

VCC_18

U33

VCC_19
VCC_20
VCC_21
VCC_22
VCC_23
VCC_24
VCC_25
VCC_26
VCC_27
VCC_28
VCC_29
VCC_30
VCC_31
VCC_32
VCC_33
VCC_34

T32

VCC_35

VCC CORE

VCC CORE

4

VCC_NCTF_1
VCC_NCTF_2
VCC_NCTF_3
VCC_NCTF_4
VCC_NCTF_5
VCC_NCTF_6

POWER

POWER

VCC_NCTF_7
VCC_NCTF_8

VCC_NCTF_9
VCC_NCTF_10
VCC_NCTF_11
VCC_NCTF_12
VCC_NCTF_13
VCC_NCTF_14
VCC_NCTF_15
VCC_NCTF_16
VCC_NCTF_17
VCC_NCTF_18
VCC_NCTF_19
VCC_NCTF_20
VCC_NCTF_21
VCC_NCTF_22
VCC_NCTF_23
VCC_NCTF_24
VCC_NCTF_25
VCC_NCTF_26
VCC_NCTF_27
VCC_NCTF_28
VCC_NCTF_29
VCC_NCTF_30
VCC_NCTF_31

VCC NCTF

VCC NCTF

VCC_NCTF_32
VCC_NCTF_33
VCC_NCTF_34
VCC_NCTF_35
VCC_NCTF_36
VCC_NCTF_37
VCC_NCTF_38
VCC_NCTF_39
VCC_NCTF_40
VCC_NCTF_41
VCC_NCTF_42
VCC_NCTF_43
VCC_NCTF_44

CANTIGA ES_FCBGA1329~D

CANTIGA ES_FCBGA1329~D

AM32
AL32
AK32
AJ32
AH32
AG32
AE32
AC32
AA32
Y32
W32
U32
AM30
AL30
AK30
AH30
AG30
AF30
AE30
AC30
AB30
AA30
Y30
W30
V30
U30
AL29
AK29
AJ29
AH29
AG29
AE29
AC29
AA29
Y29
W29
V29
AL28
AK28
AL26
AK26
AK25
AK24
AK23

+1.05V_M

+1.8V_MEM

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

2

C149

C149

1

Layout Note:
Place close to GMCH

3

U2G

U2G

C151

C151

AP33
AN33
BH32
BG32

BF32
BD32
BC32
BB32
BA32
AY32

AW32

AV32
AU32
AT32
AR32
AP32
AN32
BH31
BG31

BF31
BG30
BH29
BG29

BF29
BD29
BC29
BB29
BA29
AY29

AW29

AV29
AU29
AT29
AR29
AP29

BA36
BB24
BD16
BB21

AW16
AW13

AT13

AE25
AB25
AA25
AE24
AC24
AA24

AE23
AC23
AB23
AA23

AJ21
AG21
AE21
AC21
AA21

AH20

AF20
AE20
AC20
AB20
AA20

AM15

AL15
AE15

AJ15
AH15
AG15

AF15
AB15
AA15

AN14
AM14

AJ14
AH14

Y26

Y24

Y21

T17
T16

Y15
V15
U15

U14
T14

VCC_SM_1
VCC_SM_2
VCC_SM_3
VCC_SM_4
VCC_SM_5
VCC_SM_6
VCC_SM_7
VCC_SM_8
VCC_SM_9
VCC_SM_10
VCC_SM_11
VCC_SM_12
VCC_SM_13
VCC_SM_14
VCC_SM_15
VCC_SM_16
VCC_SM_17
VCC_SM_18
VCC_SM_19
VCC_SM_20
VCC_SM_21
VCC_SM_22
VCC_SM_23
VCC_SM_24
VCC_SM_25
VCC_SM_26
VCC_SM_27
VCC_SM_28
VCC_SM_29
VCC_SM_30
VCC_SM_31
VCC_SM_32
VCC_SM_33
VCC_SM_34
VCC_SM_35

VCC_SM_36/NC
VCC_SM_37/NC
VCC_SM_38/NC
VCC_SM_39/NC
VCC_SM_40/NC
VCC_SM_41/NC
VCC_SM_42/NC

VCC_AXG_1
VCC_AXG_2
VCC_AXG_3
VCC_AXG_4
VCC_AXG_5
VCC_AXG_6
VCC_AXG_7
VCC_AXG_8
VCC_AXG_9
VCC_AXG_10
VCC_AXG_11
VCC_AXG_12
VCC_AXG_13
VCC_AXG_14
VCC_AXG_15
VCC_AXG_16
VCC_AXG_17
VCC_AXG_18
VCC_AXG_19
VCC_AXG_20
VCC_AXG_21
VCC_AXG_22
VCC_AXG_23
VCC_AXG_24
VCC_AXG_25
VCC_AXG_26
VCC_AXG_27
VCC_AXG_28
VCC_AXG_29
VCC_AXG_30
VCC_AXG_31
VCC_AXG_32
VCC_AXG_33
VCC_AXG_34
VCC_AXG_35
VCC_AXG_36
VCC_AXG_37
VCC_AXG_38
VCC_AXG_39
VCC_AXG_40
VCC_AXG_41
VCC_AXG_42

VCC_AXG_SENSE
VSS_AXG_SENSE

330U_D2_2.5VY_R15M

330U_D2_2.5VY_R15M

1

C148

C148

+

+

2

Layout Note:
Place on the edge

T37PAD~D T37PAD~D
T38PAD~D T38PAD~D

1

2

22U_0805_6.3V6M~D

22U_0805_6.3V6M~D

C150

C150

22U_0805_6.3V6M~D

22U_0805_6.3V6M~D

1

2

VCC_AXG_SENSE
VSS_AXG_SENSE

2

POWER

POWER

VCC SMVCC GFX

VCC SMVCC GFX

VCC GFX NCTF

VCC GFX NCTF

VCC_AXG_NCTF_1
VCC_AXG_NCTF_2
VCC_AXG_NCTF_3
VCC_AXG_NCTF_4
VCC_AXG_NCTF_5
VCC_AXG_NCTF_6
VCC_AXG_NCTF_7
VCC_AXG_NCTF_8

VCC_AXG_NCTF_9
VCC_AXG_NCTF_10
VCC_AXG_NCTF_11
VCC_AXG_NCTF_12
VCC_AXG_NCTF_13
VCC_AXG_NCTF_14
VCC_AXG_NCTF_15
VCC_AXG_NCTF_16
VCC_AXG_NCTF_17
VCC_AXG_NCTF_18
VCC_AXG_NCTF_19
VCC_AXG_NCTF_20
VCC_AXG_NCTF_21
VCC_AXG_NCTF_22
VCC_AXG_NCTF_23
VCC_AXG_NCTF_24
VCC_AXG_NCTF_25
VCC_AXG_NCTF_26
VCC_AXG_NCTF_27
VCC_AXG_NCTF_28
VCC_AXG_NCTF_29
VCC_AXG_NCTF_30
VCC_AXG_NCTF_31
VCC_AXG_NCTF_32
VCC_AXG_NCTF_33
VCC_AXG_NCTF_34
VCC_AXG_NCTF_35
VCC_AXG_NCTF_36
VCC_AXG_NCTF_37
VCC_AXG_NCTF_38
VCC_AXG_NCTF_39
VCC_AXG_NCTF_40
VCC_AXG_NCTF_41
VCC_AXG_NCTF_42
VCC_AXG_NCTF_43
VCC_AXG_NCTF_44
VCC_AXG_NCTF_45
VCC_AXG_NCTF_46
VCC_AXG_NCTF_47
VCC_AXG_NCTF_48
VCC_AXG_NCTF_49
VCC_AXG_NCTF_50
VCC_AXG_NCTF_51
VCC_AXG_NCTF_52
VCC_AXG_NCTF_53
VCC_AXG_NCTF_54
VCC_AXG_NCTF_55
VCC_AXG_NCTF_56
VCC_AXG_NCTF_57
VCC_AXG_NCTF_58
VCC_AXG_NCTF_59
VCC_AXG_NCTF_60

VCC_SM_LF1
VCC_SM_LF2
VCC_SM_LF3
VCC_SM_LF4
VCC_SM_LF5
VCC_SM_LF6
VCC_SM_LF7

VCC SM LF

VCC SM LF

W28
V28
W26
V26
W25
V25
W24
V24
W23
V23
AM21
AL21
AK21
W21
V21
U21
AM20
AK20
W20
U20
AM19
AL19
AK19
AJ19
AH19
AG19
AF19
AE19
AB19
AA19
Y19
W19
V19
U19
AM17
AK17
AH17
AG17
AF17
AE17
AC17
AB17
Y17
W17
V17
AM16
AL16
AK16
AJ16
AH16
AG16
AF16
AE16
AC16
AB16
AA16
Y16
W16
V16
U16

AV44
BA37
AM40
AV21
AY5
AM10
BB13

VCCSM_LF1
VCCSM_LF2
VCCSM_LF3
VCCSM_LF4
VCCSM_LF5
VCCSM_LF6
VCCSM_LF7

1

0.22U_0402_10V4Z~D

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

C157

C157

C158

C158

1

1

2

2

0.22U_0402_10V4Z~D

0.22U_0402_10V4Z~D

0.22U_0402_10V4Z~D

C160

C160

C159

C159

1

1

2

1

2

2

0.47U_0402_10V4Z~D

0.47U_0402_10V4Z~D

1U_0402_6.3V4Z~D

1U_0402_6.3V4Z~D

1U_0402_6.3V4Z~D

1U_0402_6.3V4Z~D

C161

C161

C162

C162

C163

C163

1

1

2

2

CANTIGA ES_FCBGA1329~D

CANTIGA ES_FCBGA1329~D

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, MB A4042

SCHEMATIC, MB A4042

SCHEMATIC, MB A4042

401533

401533

401533

14 56Tuesday, December 18, 2007

14 56Tuesday, December 18, 2007

14 56Tuesday, December 18, 2007

of

of

1

of

A

A

A

5

U2I

U2I

AU48

VSS_1

AR48

VSS_2

AL48

D D

C C

B B

A A

BB47

AW47

AN47

AJ47
AF47
AD47
AB47

BD46
BA46
AY46
AV46
AR46

AM46

BF44
AH44
AD44
AA44

BC43
AV43
AU43

AM43

BG42
AY42
AT42
AN42

AJ42
AE42

BD41
AU41

AM41

AH41
AD41
AA41

BG40
BB40
AV40
AN40

AT39

AM39

AJ39
AE39

BH38
BC38
BA38
AU38
AH38
AD38
AA38

BF37
BB37

AW37

AT37
AN37

AJ37

BG36
BD36
AK15
AU36

VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
VSS_10

Y47

VSS_11

T47

VSS_12

N47

VSS_13

L47

VSS_14

G47

VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21

V46

VSS_22

R46

VSS_23

P46

VSS_24

H46

VSS_25

F46

VSS_26
VSS_27
VSS_28
VSS_29
VSS_30

Y44

VSS_31

U44

VSS_32

T44

VSS_33

M44
F44

J43

C43

N42

L42

Y41
U41
T41
M41
G41
B41

H40
E40

N39

L39

B39

Y38
U38
T38

J38
F38
C38

H37
C37

VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47
VSS_48
VSS_49
VSS_50
VSS_51
VSS_52
VSS_53
VSS_54
VSS_55
VSS_56
VSS_57
VSS_58
VSS_59
VSS_60
VSS_61
VSS_62
VSS_63
VSS_64
VSS_65
VSS_66
VSS_67
VSS_68
VSS_69
VSS_70
VSS_71
VSS_72
VSS_73
VSS_74
VSS_75
VSS_76
VSS_77
VSS_78
VSS_79
VSS_80
VSS_81
VSS_82
VSS_83
VSS_84
VSS_85
VSS_86
VSS_87
VSS_88
VSS_89
VSS_90
VSS_91
VSS_92
VSS_93
VSS_94
VSS_95
VSS_96
VSS_97
VSS_98
VSS_99

VSS

VSS

CANTIGA ES_FCBGA1329~D

CANTIGA ES_FCBGA1329~D

VSS_100
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105
VSS_106
VSS_107
VSS_108
VSS_109
VSS_110
VSS_111
VSS_112
VSS_113
VSS_114
VSS_115
VSS_116
VSS_117
VSS_118
VSS_119
VSS_120
VSS_121
VSS_122
VSS_123
VSS_124
VSS_125
VSS_126
VSS_127
VSS_128
VSS_129
VSS_130
VSS_131
VSS_132
VSS_133
VSS_134
VSS_135
VSS_136
VSS_137
VSS_138
VSS_139
VSS_140
VSS_141
VSS_142
VSS_143
VSS_144
VSS_145
VSS_146
VSS_147
VSS_148
VSS_149
VSS_150
VSS_151
VSS_152
VSS_153
VSS_154
VSS_155
VSS_156
VSS_157
VSS_158
VSS_159
VSS_160
VSS_161
VSS_162
VSS_163
VSS_164
VSS_165
VSS_166
VSS_167
VSS_168
VSS_169
VSS_170
VSS_171
VSS_172
VSS_173
VSS_174
VSS_175
VSS_176
VSS_177
VSS_178
VSS_179
VSS_180
VSS_181
VSS_182
VSS_183
VSS_184
VSS_185
VSS_186
VSS_187
VSS_188
VSS_189
VSS_190
VSS_191
VSS_192
VSS_193
VSS_194
VSS_195
VSS_196
VSS_197
VSS_198
VSS_199

AM36
AE36
P36
L36
J36
F36
B36
AH35
AA35
Y35
U35
T35
BF34
AM34
AJ34
AF34
AE34
W34
B34
A34
BG33
BC33
BA33
AV33
AR33
AL33
AH33
AB33
P33
L33
H33
N32
K32
F32
C32
A31
AN29
T29
N29
K29
H29
F29
A29
BG28
BD28
BA28
AV28
AT28
AR28
AJ28
AG28
AE28
AB28
Y28
P28
K28
H28
F28
C28
BF26
AH26
AF26
AB26
AA26
C26
B26
BH25
BD25
BB25
AV25
AR25
AJ25
AC25
Y25
N25
L25
J25
G25
E25
BF24
AD12
AY24
AT24
AJ24
AH24
AF24
AB24
R24
L24
K24
J24
G24
F24
E24
BH23
AG23
Y23
B23
A23
AJ6

4

U2J

U2J

BG21

VSS_199

L12

VSS_200

AW21

VSS_201

AU21

VSS_202

AP21

VSS_203

AN21

VSS_204

AH21

VSS_205

AF21

VSS_206

AB21

VSS_207

R21

VSS_208

M21

VSS_209

J21

VSS_210

G21

VSS_211

BC20

VSS_212

BA20

VSS_213

AW20

VSS_214

AT20

VSS_215

AJ20

VSS_216

AG20

VSS_217

Y20

VSS_218

N20

VSS_219

K20

VSS_220

F20

VSS_221

C20

VSS_222

A20

VSS_223

BG19

VSS_224

A18

VSS_225

BG17

VSS_226

BC17

VSS_227

AW17

VSS_228

AT17

VSS_229

BA16
AU16

AN16

BG15
AC15

W15

BG14
AA14

BG13
BC13
BA13

AN13

AJ13

AE13

BF12
AV12
AT12

AM12

AA12

BD11
BB11
AY11
AN11
AH11

BG10
AV10
AT10

AJ10
AE10
AA10

AM9

R17
M17
H17
C17

N16

K16

G16

E16

A15

C14

N13

L13

G13

E13

J12
A12

Y11
N11
G11
C11

M10
BF9
BC9
AN9

AD9

G9

B9
BH8
BB8
AV8
AT8

VSS_230
VSS_231
VSS_232
VSS_233

VSS_235
VSS_237

VSS_238
VSS_239
VSS_240
VSS_241
VSS_242
VSS_243
VSS_244
VSS_245
VSS_246
VSS_247
VSS_248
VSS_249
VSS_250
VSS_251
VSS_252

VSS_255
VSS_256
VSS_257
VSS_258
VSS_259
VSS_260
VSS_261
VSS_262
VSS_263
VSS_264
VSS_265
VSS_266
VSS_267
VSS_268
VSS_269
VSS_270
VSS_271
VSS_272
VSS_273

VSS_275
VSS_276
VSS_277
VSS_278
VSS_279
VSS_280
VSS_281
VSS_282
VSS_283
VSS_284
VSS_285
VSS_286
VSS_287
VSS_288
VSS_289
VSS_290
VSS_291
VSS_292
VSS_293
VSS_294
VSS_295
VSS_296

VSS

VSS

VSS SCB

VSS SCB

CANTIGA ES_FCBGA1329~D

CANTIGA ES_FCBGA1329~D

3

VSS_297
VSS_298
VSS_299
VSS_300
VSS_301
VSS_302
VSS_303
VSS_304
VSS_305
VSS_306
VSS_307
VSS_308
VSS_309
VSS_310
VSS_311
VSS_312
VSS_313
VSS_314
VSS_315
VSS_316
VSS_317
VSS_318
VSS_319
VSS_320
VSS_321
VSS_322
VSS_323
VSS_324
VSS_325

VSS_327
VSS_328
VSS_329
VSS_330
VSS_331
VSS_332
VSS_333
VSS_334
VSS_335
VSS_336
VSS_337
VSS_338
VSS_339
VSS_340
VSS_341
VSS_342
VSS_343
VSS_344
VSS_345
VSS_346
VSS_347
VSS_348
VSS_349
VSS_350

VSS_351
VSS_352
VSS_353
VSS_354

VSS_NCTF_1
VSS_NCTF_2
VSS_NCTF_3
VSS_NCTF_4
VSS_NCTF_5
VSS_NCTF_6
VSS_NCTF_7
VSS_NCTF_8

VSS_NCTF_9
VSS_NCTF_10
VSS_NCTF_11
VSS_NCTF_12
VSS_NCTF_13
VSS_NCTF_14

VSS NCTF

VSS NCTF

VSS_NCTF_15
VSS_NCTF_16

VSS_SCB_1
VSS_SCB_2
VSS_SCB_3
VSS_SCB_4
VSS_SCB_5

NC_26
NC_27
NC_28
NC_29
NC_30
NC_31
NC_32
NC_33
NC_34
NC_35

NC

NC

NC_36
NC_37
NC_38
NC_39
NC_40
NC_41
NC_42

AH8
Y8
L8
E8
B8
AY7
AU7
AN7
AJ7
AE7
AA7
N7
J7
BG6
BD6
AV6
AT6
AM6
M6
C6
BA5
AH5
AD5
Y5
L5
J5
H5
F5
BE4

BC3
AV3
AL3
R3
P3
F3
BA2
AW2
AU2
AR2
AP2
AJ2
AH2
AF2
AE2
AD2
AC2
Y2
M2
K2
AM1
AA1
P1
H1

U24
U28
U25
U29

AF32
AB32
V32
AJ30
AM29
AF29
AB29
U26
U23
AL20
V20
AC19
AL17
AJ17
AA17
U17

BH48
BH1
A48
C1
A3

E1
D2
C3
B4
A5
A6
A43
A44
B45
C46
D47
B47
A46
F48
E48
C48
B48

2

1

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, MB A4042

SCHEMATIC, MB A4042

SCHEMATIC, MB A4042

401533

401533

401533

15 56Tuesday, December 18, 2007

15 56Tuesday, December 18, 2007

15 56Tuesday, December 18, 2007

of

of

1

of

A

A

A

5

DDR_A_DQS#[0..7]<11>

DDR_A_D[0..63]<11>
DDR_A_DM[0..7]<11>
DDR_A_DQS[0..7]<11>

DDR_A_MA[0..14]<11>

D D

+1.8V_MEM

2.2U_0603_6.3V6K~D

2.2U_0603_6.3V6K~D

2.2U_0603_6.3V6K~D

2.2U_0603_6.3V6K~D

2.2U_0603_6.3V6K~D
C166

C166

1

2

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

C C

+0.9V_DDR_VTT

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

B B

A A

1

1

2

2

C176

C176

C175

C175

DDR_A_MA3
DDR_A_MA1

56_0404_4P2R_5%~D

56_0404_4P2R_5%~D

DDR_A_BS0
DDR_A_MA10

56_0404_4P2R_5%~D

56_0404_4P2R_5%~D

DDR_CS0_DIMMA#
DDR_A_RAS#

56_0404_4P2R_5%~D

56_0404_4P2R_5%~D

DDR_A_CAS#
DDR_A_WE#

56_0404_4P2R_5%~D

56_0404_4P2R_5%~D

DDR_CS1_DIMMA#
M_ODT1

56_0404_4P2R_5%~D

56_0404_4P2R_5%~D

DDR_CKE1_DIMMA

DDR_CKE0_DIMMA
DDR_A_BS2

56_0404_4P2R_5%~D

56_0404_4P2R_5%~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

1

2

C177

C177

5

2.2U_0603_6.3V6K~D

C167

C167

C168

C168

1

1

2

2

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

C172

C172

C171

C171

1

1

2

2

Layout Note:
Place one cap close to every 2 pullup
resistors terminated to +0.9V_DDR_VTT

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

1 4
2 3

1 4
2 3

1 4
2 3

1 4
2 3

1 4
2 3

R130

R130

56_0402_5%~D

56_0402_5%~D

2 3
1 4

1

2

C178

C178

RN1

RN1

RN3

RN3

RN5

RN5

RN7

RN7

RN9

RN9

RN12

RN12

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

1

2

C179

C179

+0.9V_DDR_VTT

12

2.2U_0603_6.3V6K~D

2.2U_0603_6.3V6K~D

1

2

1

2

C180

C180

C173

C173

RN6

RN6

RN8

RN8

RN10

RN10

RN11

RN11

RN13

RN13

RN2

RN2

RN4

RN4

1

2

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

C169

C169

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

1

2

C181

C181

2.2U_0603_6.3V6K~D

2.2U_0603_6.3V6K~D

1

2

14
23

56_0404_4P2R_5%~D

56_0404_4P2R_5%~D

14
23

56_0404_4P2R_5%~D

56_0404_4P2R_5%~D

14
23

56_0404_4P2R_5%~D

56_0404_4P2R_5%~D

14
23

56_0404_4P2R_5%~D

56_0404_4P2R_5%~D

14
23

56_0404_4P2R_5%~D

56_0404_4P2R_5%~D

14
23

56_0404_4P2R_5%~D

56_0404_4P2R_5%~D

14
23

56_0404_4P2R_5%~D

56_0404_4P2R_5%~D

C170

C170

1

2

C174

C174

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

1

2

C182

C182

DDR_A_MA12
DDR_A_MA8

DDR_A_MA6
DDR_A_MA7

DDR_A_MA5
DDR_A_MA9

DDR_A_MA2
DDR_A_MA4

DDR_A_BS1
DDR_A_MA0

DDR_A_MA13
M_ODT0

DDR_A_MA11
DDR_A_MA14

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

Layout Note:
Place near JDIMMA

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

1

1

2

2

C183

C183

C184

C184

4

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

1

1

2

2

C185

C185

C186

C186

Layout Note:
Place these resistor
closely JDIMMA,all
trace length<750 mil

Layout Note:
Place these resistor
closely JDIMMA,all
trace length
Max=1.3"

4

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

3

+1.8V_MEM +1.8V_MEM +V_DDR_MCH_REF

JDIMMA

JDIMMA

1

VREF

3

DDR_A_D0
DDR_A_D1

DDR_A_DQS#0
DDR_A_DQS0

DDR_A_D2
DDR_A_D3

DDR_A_D8
DDR_A_D9

DDR_A_DQS#1
DDR_A_DQS1

DDR_A_D11

DDR_A_D16

DDR_A_DQS#2
DDR_A_DQS2

DDR_A_D18

DDR_A_D24
DDR_A_D25

DDR_A_DM3

DDR_A_D26 DDR_A_D30
DDR_A_D27

DDR_CKE0_DIMMA<10>

DDR_A_BS2<11>

DDR_A_BS0<11>
DDR_A_WE#<11>

DDR_A_CAS#<11>

DDR_CS1_DIMMA#<10>

M_ODT1<10>

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

1

1

2

2

C187

C187

C188

C188

MEM_SDATA<17,24>
MEM_SCLK<17,24>

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

DDR_CKE0_DIMMA

DDR_A_BS2
DDR_A_MA12

DDR_A_MA9 DDR_A_MA7
DDR_A_MA8

DDR_A_MA5
DDR_A_MA3
DDR_A_MA1

DDR_A_MA10
DDR_A_BS0
DDR_A_WE#

DDR_A_CAS#
DDR_CS1_DIMMA#

M_ODT1
DDR_A_D32

DDR_A_D33
DDR_A_DQS#4

DDR_A_DQS4
DDR_A_D34

DDR_A_D35
DDR_A_D40

DDR_A_D41
DDR_A_DM5
DDR_A_D42

DDR_A_D43

DDR_A_D49

DDR_A_DQS#6
DDR_A_DQS6

DDR_A_D50
DDR_A_D51 DDR_A_D55

DDR_A_D57
DDR_A_DM7
DDR_A_D58

DDR_A_D59
MEM_SDATA

MEM_SCLK

+3.3V_M

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

2.2U_0603_6.3V6K~D

2.2U_0603_6.3V6K~D

C189

C189

C190

C190

1

1

2

2

VSS

5

DQ0

7

DQ1

9

VSS

11

DQS0#

13

DQS0

15

VSS

17

DQ2

19

DQ3

21

VSS

23

DQ8

25

DQ9

27

VSS

29

DQS1#

31

DQS1

33

VSS

35

DQ10

37

DQ11

39

VSS

41

VSS

43

DQ16

45

DQ17

47

VSS

49

DQS2#

51

DQS2

53

VSS

55

DQ18

57

DQ19

59

VSS

61

DQ24

63

DQ25

65

VSS

67

DM3

69

NC

71

VSS

73

DQ26

75

DQ27

77

VSS

79

CKE0

81

VDD

83

NC

85

BA2

87

VDD

89

A12

91

A9

93

A8

95

VDD

97

A5

99

A3

101

A1

103

VDD

105

A10/AP

107

BA0

109

WE#

111

VDD

113

CAS#

115

NC/S1#

117

VDD

119

NC/ODT1

121

VSS

123

DQ32

125

DQ33

127

VSS

129

DQS4#

131

DQS4

133

VSS

135

DQ34

137

DQ35

139

VSS

141

DQ40

143

DQ41

145

VSS

147

DM5

149

VSS

151

DQ42

153

DQ43

155

VSS

157

DQ48

159

DQ49

161

VSS

163

NC,TEST

165

VSS

167

DQS6#

169

DQS6

171

VSS

173

DQ50

175

DQ51

177

VSS

179

DQ56

181

DQ57

183

VSS

185

DM7

187

VSS

189

DQ58

191

DQ59

193

VSS

195

SDA

197

SCL

199

VDDSPD

201

G1

FOX_AS0A426-N4RN-7F~D

FOX_AS0A426-N4RN-7F~D

REVERSE

NC/CKE1

DIMMA

2

VSS
DQ4
DQ5
VSS
DM0
VSS
DQ6
DQ7

VSS
DQ12
DQ13

VSS

DM1

VSS

CK0#

VSS
DQ14
DQ15

VSS

VSS
DQ20
DQ21

VSS

DM2

VSS
DQ22
DQ23

VSS
DQ28
DQ29

VSS

DQS3#

DQS3

VSS
DQ30
DQ31

VSS

VDD

NC/A15
NC/A14

VDD

VDD

VDD

RAS#

VDD
ODT0

NC/A13

VDD

VSS
DQ36
DQ37

VSS

DM4

VSS
DQ38
DQ39

VSS
DQ44
DQ45

VSS

DQS5#

DQS5

VSS
DQ46
DQ47

VSS
DQ52
DQ53

VSS

CK1#

VSS

DM6

VSS
DQ54
DQ55

VSS
DQ60
DQ61

VSS

DQS7#

DQS7

VSS
DQ62
DQ63

VSS

SAO

2

1

+V_DDR_MCH_REF

2

DDR_A_D4

4

DDR_A_D5

6
8

DDR_A_DM0

10
12

DDR_A_D6

14

DDR_A_D7

16
18

DDR_A_D12

20

DDR_A_D13

22
24

DDR_A_DM1

26
28

M_CLK_DDR0

30

CK0

NC

A11

A7
A6

A4
A2

A0
BA1
S0#

NC

CK1

SA1

G2

M_CLK_DDR#0

32
34

DDR_A_D14DDR_A_D10

36

DDR_A_D15

38
40

42

DDR_A_D20

44

DDR_A_D21DDR_A_D17

46
48
50

DDR_A_DM2

52
54

DDR_A_D22

56

DDR_A_D23DDR_A_D19

58
60

DDR_A_D28

62

DDR_A_D29

64
66

DDR_A_DQS#3

68

DDR_A_DQS3

70
72
74

DDR_A_D31

76
78

DDR_CKE1_DIMMA

80
82
84

DDR_A_MA14

86
88

DDR_A_MA11

90
92

DDR_A_MA6

94
96

DDR_A_MA4

98

DDR_A_MA2

100

DDR_A_MA0

102
104

DDR_A_BS1

106

DDR_A_RAS#

108

DDR_CS0_DIMMA#

110
112

M_ODT0

114

DDR_A_MA13

116
118
120
122

DDR_A_D36

124

DDR_A_D37

126
128

DDR_A_DM4

130
132

DDR_A_D38

134

DDR_A_D39

136
138

DDR_A_D44

140

DDR_A_D45

142
144

DDR_A_DQS#5

146

DDR_A_DQS5

148
150

DDR_A_D46

152

DDR_A_D47

154
156

DDR_A_D52DDR_A_D48

158

DDR_A_D53

160
162

M_CLK_DDR1

164

M_CLK_DDR#1

166
168

DDR_A_DM6

170
172

DDR_A_D54

174
176
178

DDR_A_D60DDR_A_D56

180

DDR_A_D61

182
184

DDR_A_DQS#7

186

DDR_A_DQS7

188
190

DDR_A_D62

192

DDR_A_D63

194
196

R128 10K_0402_5%~D

R128 10K_0402_5%~D

198
200
202

1 2

R129 10K_0402_5%~D

R129 10K_0402_5%~D

1 2

M_CLK_DDR0 <10>

M_CLK_DDR#0 <10>

DDR_CKE1_DIMMA <10>

DDR_A_BS1 <11>
DDR_A_RAS# <11>

DDR_CS0_DIMMA# <10>

M_ODT0 <10>

M_CLK_DDR1 <10>

M_CLK_DDR#1 <10>

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

2.2U_0603_6.3V6K~D

2.2U_0603_6.3V6K~D

1

1

C164

C164

2

C165

C165

2

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, MB A4042

SCHEMATIC, MB A4042

SCHEMATIC, MB A4042

401533

401533

401533

16 56Tuesday, December 18, 2007

16 56Tuesday, December 18, 2007

16 56Tuesday, December 18, 2007

1

A

A

A

of

of

of

5

DDR_B_DQS#[0..7]<11>

DDR_B_D[0..63]<11>
DDR_B_DM[0..7]<11>
DDR_B_DQS[0..7]<11>

DDR_B_MA[0..14]<11>

D D

C C

B B

A A

+1.8V_MEM

+0.9V_DDR_VTT

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

1

2

C202

C202

DDR_B_MA3
DDR_B_MA1

56_0404_4P2R_5%~D

56_0404_4P2R_5%~D

DDR_B_BS0
DDR_B_MA10

56_0404_4P2R_5%~D

56_0404_4P2R_5%~D

DDR_B_MA0
DDR_B_BS1

56_0404_4P2R_5%~D

56_0404_4P2R_5%~D

DDR_B_RAS#
DDR_CS2_DIMMB#

56_0404_4P2R_5%~D

56_0404_4P2R_5%~D

DDR_B_WE#
DDR_B_CAS#

56_0404_4P2R_5%~D

56_0404_4P2R_5%~D

DDR_CKE3_DIMMB

DDR_CS3_DIMMB#
M_ODT3

R133

56_0404_4P2R_5%~D

56_0404_4P2R_5%~D

2.2U_0603_6.3V6K~D

2.2U_0603_6.3V6K~D

2.2U_0603_6.3V6K~D

1

2

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

C199

C199

RN15

RN15

RN17

RN17

RN19

RN19

RN21

RN21

RN23

RN23

RN24

RN24

RN26

RN26

1

2

1

2

C206

C206

C195

C195

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

2.2U_0603_6.3V6K~D
C196

C196

1

2

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

C200

C200

1

2

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

1

2

C207

C207

DDR_B_MA12

14

DDR_B_BS2

23

56_0404_4P2R_5%~D

56_0404_4P2R_5%~D

DDR_B_MA14

14

DDR_B_MA11

23

56_0404_4P2R_5%~D

56_0404_4P2R_5%~D

DDR_B_MA5

14

DDR_B_MA8

23

56_0404_4P2R_5%~D

56_0404_4P2R_5%~D

DDR_B_MA7

14

DDR_B_MA6

23

56_0404_4P2R_5%~D

56_0404_4P2R_5%~D

DDR_B_MA4

14

DDR_B_MA2

23

56_0404_4P2R_5%~D

56_0404_4P2R_5%~D

M_ODT2

14

DDR_B_MA13

23

56_0404_4P2R_5%~D

56_0404_4P2R_5%~D

DDR_B_MA9

14

DDR_CKE2_DIMMB

23

56_0404_4P2R_5%~D

56_0404_4P2R_5%~D

2.2U_0603_6.3V6K~D

2.2U_0603_6.3V6K~D

2.2U_0603_6.3V6K~D

2.2U_0603_6.3V6K~D

1

2

C203

C203

1 4
2 3

1 4
2 3

1 4
2 3

1 4
2 3

1 4
2 3

R133
56_0402_5%~D

56_0402_5%~D

2 3
1 4

C194

C194

C193

C193

1

1

2

2

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D
C198

C198

1

2

Layout Note:
Place one cap close to every 2 pullup
resistors terminated to +0.9V_DDR_VTT

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

1

1

2

2

C205

C205

C204

C204

+0.9V_DDR_VTT

RN14

RN14

RN16

RN16

RN18

RN18

RN20

RN20

RN22

RN22

12

RN25

RN25

5

2.2U_0603_6.3V6K~D

2.2U_0603_6.3V6K~D
C197

C197

1

2

C201

C201

1

2

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

1

1

2

2

C209

C209

C208

C208

Layout Note:
Place near JDIMMB

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

1

2

C210

C210

4

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

1

2

C211

C211

Layout Note:
Place these resistor
closely JDIMMB,all
trace length<750 mil

Layout Note:
Place these resistor
closely JDIMMB,all
trace length
Max=1.3"

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

1

1

2

2

C212

C212

C213

C213

4

3

JDIMMB

JDIMMB

1

VREF

3

C216

C216

5
7

9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39

41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99

101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201

VSS
DQ0
DQ1
VSS
DQS0#
DQS0
VSS
DQ2
DQ3
VSS
DQ8
DQ9
VSS
DQS1#
DQS1
VSS
DQ10
DQ11
VSS

VSS
DQ16
DQ17
VSS
DQS2#
DQS2
VSS
DQ18
DQ19
VSS
DQ24
DQ25
VSS
DM3
NC
VSS
DQ26
DQ27
VSS
CKE0
VDD
NC
BA2
VDD
A12
A9
A8
VDD
A5
A3
A1
VDD
A10/AP
BA0
WE#
VDD
CAS#
NC/S1#
VDD
NC/ODT1
VSS
DQ32
DQ33
VSS
DQS4#
DQS4
VSS
DQ34
DQ35
VSS
DQ40
DQ41
VSS
DM5
VSS
DQ42
DQ43
VSS
DQ48
DQ49
VSS
NC,TEST
VSS
DQS6#
DQS6
VSS
DQ50
DQ51
VSS
DQ56
DQ57
VSS
DM7
VSS
DQ58
DQ59
VSS
SDA
SCL
VDDSPD
GND

FOX_AS0A426-N8RN-7F_RV

FOX_AS0A426-N8RN-7F_RV

DIMMB

REVERSE

DDR_B_D0 DDR_B_D5
DDR_B_D1

DDR_B_DQS#0
DDR_B_DQS0

DDR_B_D2
DDR_B_D3

DDR_B_D8
DDR_B_D9

DDR_B_DQS#1
DDR_B_DQS1

DDR_B_D10
DDR_B_D11

DDR_B_D16 DDR_B_D20
DDR_B_D17

DDR_B_DQS#2
DDR_B_DQS2

DDR_B_D18
DDR_B_D19

DDR_B_D24
DDR_B_D25

DDR_B_DM3

DDR_B_D26
DDR_B_D27

DDR_CKE2_DIMMB<10>

DDR_B_BS2<11>

DDR_B_BS0<11>
DDR_B_WE#<11>

DDR_B_CAS#<11>

DDR_CS3_DIMMB#<10>

MEM_SDATA<16,24>
MEM_SCLK<16,24>

M_ODT3<10>

+3.3V_M

1

2

C214

C214

DDR_CKE2_DIMMB

DDR_B_BS2
DDR_B_MA12

DDR_B_MA9
DDR_B_MA8

DDR_B_MA5
DDR_B_MA3
DDR_B_MA1

DDR_B_MA10
DDR_B_BS0 DDR_B_RAS#
DDR_B_WE#

DDR_B_CAS#
DDR_CS3_DIMMB#

M_ODT3
DDR_B_D32

DDR_B_D33
DDR_B_DQS#4

DDR_B_DQS4
DDR_B_D34

DDR_B_D35
DDR_B_D40

DDR_B_D41
DDR_B_DM5
DDR_B_D42

DDR_B_D43
DDR_B_D48

DDR_B_D49

DDR_B_DQS#6
DDR_B_DQS6

DDR_B_D50
DDR_B_D51

DDR_B_D56
DDR_B_D57

DDR_B_DM7
DDR_B_D58

DDR_B_D59
MEM_SDATA

MEM_SCLK

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

2.2U_0603_6.3V6K~D

2.2U_0603_6.3V6K~D

C215

C215

1

1

2

2

VSS
DQ4
DQ5
VSS
DM0
VSS
DQ6
DQ7

VSS
DQ12
DQ13

VSS

DM1

VSS

CK0

CK0#

VSS
DQ14
DQ15

VSS

VSS
DQ20
DQ21

VSS

DM2

VSS
DQ22
DQ23

VSS
DQ28
DQ29

VSS

DQS3#

DQS3

VSS
DQ30
DQ31

VSS

NC/CKE1

VDD

NC/A15
NC/A14

VDD

VDD

VDD
RAS#

VDD
ODT0

NC/A13

VDD

VSS
DQ36
DQ37

VSS

DM4

VSS
DQ38
DQ39

VSS
DQ44
DQ45

VSS

DQS5#

DQS5

VSS
DQ46
DQ47

VSS
DQ52
DQ53

VSS

CK1

CK1#

VSS

DM6

VSS
DQ54
DQ55

VSS
DQ60
DQ61

VSS

DQS7#

DQS7

VSS
DQ62
DQ63

VSS

SAO

GND

NC

A11

A7
A6

A4
A2

A0
BA1
S0#

NC

SA1

2

+1.8V_MEM+1.8V_MEM +V_DDR_MCH_REF

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202

+V_DDR_MCH_REF

DDR_B_D4

DDR_B_DM0
DDR_B_D6

DDR_B_D7
DDR_B_D12

DDR_B_D13
DDR_B_DM1
M_CLK_DDR2

M_CLK_DDR#2
DDR_B_D14

DDR_B_D15

DDR_B_D21

DDR_B_DM2
DDR_B_D22

DDR_B_D23
DDR_B_D28

DDR_B_D29
DDR_B_DQS#3

DDR_B_DQS3
DDR_B_D30

DDR_B_D31
DDR_CKE3_DIMMB

DDR_B_MA14
DDR_B_MA11

DDR_B_MA7
DDR_B_MA6

DDR_B_MA4
DDR_B_MA2
DDR_B_MA0

DDR_B_BS1
DDR_CS2_DIMMB#
M_ODT2

DDR_B_MA13

DDR_B_D36
DDR_B_D37

DDR_B_DM4
DDR_B_D38

DDR_B_D39
DDR_B_D44

DDR_B_D45
DDR_B_DQS#5

DDR_B_DQS5
DDR_B_D46

DDR_B_D47
DDR_B_D52

DDR_B_D53
M_CLK_DDR3

M_CLK_DDR#3
DDR_B_DM6
DDR_B_D54

DDR_B_D55
DDR_B_D60

DDR_B_D61
DDR_B_DQS#7

DDR_B_DQS7
DDR_B_D62

DDR_B_D63

10K_0402_5%~D

10K_0402_5%~D

12

M_CLK_DDR2 <10>

M_CLK_DDR#2 <10>

DDR_CKE3_DIMMB <10>

DDR_B_BS1 <11>

DDR_B_RAS# <11>
DDR_CS2_DIMMB# <10>

M_ODT2 <10>

M_CLK_DDR3 <10>

M_CLK_DDR#3 <10>

R131

R131

10K_0402_5%~D

10K_0402_5%~D

R132

R132

2.2U_0603_6.3V6K~D

2.2U_0603_6.3V6K~D

1

2

+3.3V_M

12

C191

C191

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

1

1

C192

C192

2

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

2

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, MB A4042

SCHEMATIC, MB A4042

SCHEMATIC, MB A4042

401533

401533

401533

17 56Tuesday, December 18, 2007

17 56Tuesday, December 18, 2007

17 56Tuesday, December 18, 2007

1

A

A

A

of

of

of

5

+3.3V_M

12

R134

+1.05V_VCCP

R135

R135

2.2K_0402_5%~D

D D

H_THERMTRIP#<7>

THERMTRIP_MCH#<10>

2.2K_0402_5%~D

1 2

MMST3904-7-F_SOT323-3~D

MMST3904-7-F_SOT323-3~D

+1.05V_VCCP

R138

R138

2.2K_0402_5%~D

2.2K_0402_5%~D

1 2

MMST3904-7-F_SOT323-3~D

MMST3904-7-F_SOT323-3~D

R134

8.2K_0402_5%~D

8.2K_0402_5%~D

THERMATRIP1#

C

C

E

E

3 1

12

C

C

E

E

3 1

1

C218

C218

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

2

R137

R137

8.2K_0402_5%~D

8.2K_0402_5%~D

THERMATRIP2#

1

C220

C220

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

2

RB751S40T1_SOD523-2~D

RB751S40T1_SOD523-2~D

2

B

B

Q5

Q5

+3.3V_M

2

B

B

Q6

Q6

Place under CPU

C

100P_0402_50V8K~D

C C

H_THERMDA<7>

H_THERMDC<7>

+3.3V_M

B B

1

Place C223 close to the Q8 as possible
Place C224,C225 close to the Guardian pins as possible

470P_0402_50V7K~D

470P_0402_50V7K~D

1 2

R142

R142
22_0603_1%~D

22_0603_1%~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

2

C223

@C223

@

100P_0402_50V8K~D

Rset=953,Tp=88degree

R157

R157

THERM_B3

+3.3V_M

2

B

B

E

E

+3.3V_RUN

2.2K_0402_5%~D

2.2K_0402_5%~D

8.2K_0402_5%~D

8.2K_0402_5%~D

12

12

R156

R156

A A

THERMTRIP_VGA#<51>

5

C

E

E

3 1

1

C225

C225

2

H_THERMDA1<7>

Place C228 close to U3

H_THERMDC1<7>

1

+RTC_CELL

C229

C229

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

2

12

1

R151

R151
953_0402_1%~D

2

R155

R155

8.2K_0402_5%~D

8.2K_0402_5%~D

THERMATRIP3#

953_0402_1%~D

C231

C231

12

C

C

Q11

Q11
MMST3904-7-F_SOT323-3~D

MMST3904-7-F_SOT323-3~D

3 1

4

D2

D2

2 1

2

B

B

Q8

Q8
MMST3904-7-F_SOT323-3~D

MMST3904-7-F_SOT323-3~D

Place C225 close to U3

+5V_RUN

1

C240

C240

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

2

4

1

C219

C219

2

22U_0805_6.3VAM~D

22U_0805_6.3VAM~D

BC_DAT_EMC4002<38>

BC_CLK_EMC4002<38>

2

C224

C224
2200P_0402_50V7K~D

2200P_0402_50V7K~D

1

C228

C228

470P_0402_50V7K~D

470P_0402_50V7K~D

1U_0603_10V4Z~D

1U_0603_10V4Z~D

C230

C230

1

2

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

10U_0805_10V4Z~D

10U_0805_10V4Z~D

+3.3V_RUN

1

1

C234

C234

C235

C235

2

2

+3.3V_M

12

R136

R136
10K_0402_5%~D

10K_0402_5%~D

FAN1_DET#<22>

1

2

3.3V_M_PWRGD<38,41>
ICH_PWRGD#<41>

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

1

2

*

R146 1K_0402_5%~D

R146 1K_0402_5%~D
R148 1K_0402_5%~D

R148 1K_0402_5%~D

+3VSUS_THRM

10U_0805_10V4Z~D

10U_0805_10V4Z~D

1

C236

C236

C237

C237

2

EC_32KHZ_OUT<38>

Pull-up Resistor
on ADDR_MODE/XEN

<= 4.7K +/- 5% 2F(r/w)

10K
18K

>= 33K

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

+FAN1_VOUT

FAN1_TACH_FB

REM_DIODE1_P
REM_DIODE1_N

+3VSUS_THRM

1 2
1 2

THERMATRIP1#
THERMATRIP2#
THERMATRIP3#

VSET

12

R150 4.7K_0402_5%~D

R150 4.7K_0402_5%~D

+FAN1_VOUT

FAN1_TACH_FB

EC_32KHZ_OUT

For Remote1
mode

2N3904

2N3904
Thermistor
Thermistor

3

U3
EMC4002U3EMC4002

10
11

36
35

38
37

41
40

4

21

18
17

22
23
24

42

3

6
5

9
7

8

15
14

3

JFAN1

JFAN1

1

1

2

2

3

5

3

G1

4

6

4

G2

MOLEX_53398-0471~D

MOLEX_53398-0471~D

SMDATA/BC-LINK_DATA
SMBCLK/BC-LINK_CLK

DP1/VREF_T
DN1/THERM

DP2
DN2

DP3/DN7
DN3/DP7

VCC

ATF_INT#/BC-LINK_IRQ#

RTC_PWR3V

THERMTRIP_SIO/PWM1/GPIO5

VCC_PWRGD
3V_PWROK#

THERMTRIP1#
THERMTRIP2#
THERMTRIP3#

VSET
ADDR_MODE/XEN

VDD_5V
VDD_5V

VDD_3V
FAN_OUT

FAN_OUT
TACH1/GPIO3

CLK_IN/GPIO2

SMBUS
Address

LDO_OUT/FAN_OUT2
LDO_OUT/FAN_OUT2

VSS

49

2E(r/w)
2F(r/w)
2E(r/w)

@ R1005

@

4.7K_0402_5%~D

4.7K_0402_5%~D

VIN1
VCP1
VCP2

DP4/DN8
DN4/DP8

DP5/DN9
DN5/DP9

DP6/VREF_T2

DN6/VIN2

POWER_SW#

ACAVAIL_CLR

SYS_SHDN#

LDO_SHDN#

LDO_POK

LDO_SET

VDDH/VDD_5V2
VDDH/VDD_5V2

VDDL/VDD_3V2

TACH2/GPIO4

PWM2/GPIO1

R1005

PWR_MON_GFX

12

39
48
45

REM_DIODE4_P

44

REM_DIODE4_N

43

VGA_THERMDP

47

VGA_THERMDN

46
1

2

R141 10K_0402_5%~D

R141 10K_0402_5%~D

12
26
27
20
25

R149

R149

19
34

LDO_SET

33

+3V_LDOIN

32
31

28
29

30
16

13

2

Discrete

VGA_THERMDP

1

C217

C217
470P_0402_50V7K~D

470P_0402_50V7K~D

VGA_THERMDN

2

Place Capacitor close to Guardian Chip

T186PAD~DT186PAD~D

ISL88731_ICM_R

Place C221 close to the
Guardian pins as possible.

12

12

10K_0402_5%~D

10K_0402_5%~D

R985 0_0402_5%~DR985 0_0402_5%~D

PWR_MON <47>

1 2

R992

R992

0_0402_5%~D

0_0402_5%~D

1

2

BC_INT#_EMC4002 <38>
ACAV_IN_MB/DOCK <38>

2.5V_RUN_PWRGD <37,41>

+2.5V_RUN

10U_0805_10V4Z~D

10U_0805_10V4Z~D

1

1

C238

C238

2

2

12

ISL88731_ICM <48>

2

B

C221

C221
2200P_0402_50V7K~D

2200P_0402_50V7K~D

THERMISTOR OPTION:
Single-ended routing to thermistor is permissible
(ground return). Place R139 and C226 near EMC4002

1 2

R139

R139

1.2K_0402_1%~D

1.2K_0402_1%~D

+3.3V_M

+3.3V_SUS

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

C239

C239

PM_EXTTS# <10>

B

E

E

1 2

1 2

C226

C226

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

R143 0_0402_5%~D

R143 0_0402_5%~D
R144 0_0402_5%~D

R144 0_0402_5%~D

12

R145 10K_0402_5%~D

R145 10K_0402_5%~D

1 2

R147 47K_0402_1%~D@R147 47K_0402_1%~D@

At maximum load current of 600mA,the the
voltage drop across the should be keep
in the range of 0.5V to 1V

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

10U_0805_10V4Z~D

10U_0805_10V4Z~D

1

2

C232

C232

1

2

R152

R152
0_1210_5%~D

0_1210_5%~D

C233

C233

DELL CONFIDENTIAL/PROPRIETARY

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

2

Date: Sheet

1

VGA_THERMDP <51>

VGA_THERMDN <51>

Diode circuit at DP4/DN4 is used for skin
temp sensor (placed optimally between CPU,
MCH and MEM).

E

E

Q7

Q7

12
12

2

MMST3904-7-F_SOT323-3~D

MMST3904-7-F_SOT323-3~D

12

31

B

B

Q9

Q9

C

C

+3.3V_M

THERM_STP# <44>

+RTC_CELL

+3.3V_RUN

1

C222

@C222

@

100P_0402_50V8K~D

100P_0402_50V8K~D

2

Place C222 close to Q7 as
possible.

MMST3904-7-F_SOT323-3~D

MMST3904-7-F_SOT323-3~D

DOCK_PWR_SW# <38>
POWER_SW_IN# <38>

+2.5V_RUN

0_0402_5%~D

0_0402_5%~D

12

@

@

R153

R153

C

C

3 1

R140

R140
10KB_0603_1%_TSM1A103F34D3R~D

10KB_0603_1%_TSM1A103F34D3R~D

Ra

LDO_SET

1K_0402_1%~D

1K_0402_1%~D

12

R154

R154

Rb

Voltage margining circuit
for LDO output. Adjustable
from 1.2 to 2.5V.
Ra=((LDO_OUT/1.2)-1)*Rb.

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

SCHEMATIC, MB A4042

SCHEMATIC, MB A4042

SCHEMATIC, MB A4042

401533

401533

401533

18 56Tuesday, December 18, 2007

18 56Tuesday, December 18, 2007

18 56Tuesday, December 18, 2007

of

of

1

of

A

A

A

5

JLVDS1

JLVDS1

59

MGND1

60

MGND2

61

MGND3

62

MGND4

63

MGND5

64

MGND6

65

MGND7

66

MGND8

67

MGND9

68

MGND10

69

MGND11

70

D D

C C

B B

MGND12

DATA EEDID

Diag_Loop_CAM

JAE_FI-DP58SB-VF100

JAE_FI-DP58SB-VF100

Even_ClkIN+
Even_ClkIN-

VSS

Even_Rin2+

Even_Rin2-

VSS

Even_Rin1+

Even_Rin1-

VSS

Even_Rin0+

Even_Rin0-

VSS

Odd_ClkIN+

Odd_ClkIN-

VSS
Odd_Rin2+
Odd_Rin2-

VSS
Odd_Rin1+
Odd_Rin1-

VSS
Odd_Rin0+
Odd_Rin0-

VSS

CLK EEDID

VSS

VEEDID

MIC_CLK

3.3V

MIC_SIG

USB-

USB+

GND

CONNTST

SMB_CLK

SMB_DATA

INV_SRC
INV_SRC
INV_SRC
INV_SRC

VBL­VBL­VBL­VBL-

INV_PWM

+5V_ALW

TEST

VDD
VDD

VDD
CONNTST
PWR_LED

BATT2_LED
BATT1_LED

VSS

+CMOS_VDD

58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26

5V

25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

1

C249

C249

2

1

2

+15V_ALW

12

LDDC_DATA_GPU
LDDC_CLK_GPU
LVDS_CBL_DET#

CAM_MIC_CBL_DET#
DMIC_CLK

DMIC0
+CMOS_VDD
USBP11_D­USBP11_D+

LCD_SMBCLK
LCD_SMBDAT

LCD_TST

BREATH_BLUE_LED_LCD
BATT_YELLOW_LED_LCD
BATT_BLUE_LED_LCD

PMV45EN_SOT23-3~D

PMV45EN_SOT23-3~D
Q132

Q132

S

S

10U_1206_16V4Z~D

10U_1206_16V4Z~D

G

G

C250

C250

100K_0402_5%~D

100K_0402_5%~D

R994

R994

2

LCD_SMBCLK <38>
LCD_SMBDAT <38>

1 2

C246

C246

0.1U_0603_50V4Z~D

0.1U_0603_50V4Z~D

LCD_TST <37>

+LCDVDD

D

D

+CMOS_VDD_R

13

LCD_BCLK+_GPU <51>
LCD_BCLK-_GPU <51>

LCD_B2+_GPU <51>

LCD_B2-_GPU <51>

LCD_B1+_GPU <51>

LCD_B1-_GPU <51>

LCD_B0+_GPU <51>

LCD_B0-_GPU <51>

LCD_ACLK+_GPU <51>
LCD_ACLK-_GPU <51>

LCD_A2+_GPU <51>

LCD_A2-_GPU <51>

LCD_A1+_GPU <51>

LCD_A1-_GPU <51>

LCD_A0+_GPU <51>

LCD_A0-_GPU <51>

LDDC_DATA_GPU <51>
LDDC_CLK_GPU <51>
LVDS_CBL_DET# <22>

CAM_MIC_CBL_DET# <22>

+INV_PWR_SRC

PNL_BKLT_CBL_DET# <22>
BREATH_BLUE_LED_LCD <42>
BATT_YELLOW_LED_LCD <42>
BATT_BLUE_LED_LCD <42>

@

@

12

R170

R170
0_0603_5%~D

0_0603_5%~D

12

R169

R169

0_0603_5%~D

0_0603_5%~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

1

C1026

C1026

2

+3.3V_RUN

+3.3V_RUN

12

R165

R165

10K_0402_5%~D

10K_0402_5%~D

1 2

R166 0_0402_5%~D@ R166 0_0402_5%~D@

+3.3V_RUN

+5V_RUN

4

+3.3V_RUN

1 2

R159 2.2K_0402_5%~DR159 2.2K_0402_5%~D

1 2

R160 2.2K_0402_5%~DR160 2.2K_0402_5%~D

LDDC_CLK_GPU
LDDC_DATA_GPU

Place near to JLVDS1

DMIC_CLK <27>

+3.3V_RUN

DMIC0 <27>

D48

@

@

D47

D47

SD05.TCT_SOD323-2~D

SD05.TCT_SOD323-2~D

D48

D56

D56

@

@

@

@

2 1

2 1

2 1

SD05.TCT_SOD323-2~D

SD05.TCT_SOD323-2~D

SD05.TCT_SOD323-2~D

SD05.TCT_SOD323-2~D

BIA_PWM_GPU <51>

+5V_ALW

1

C245

C245

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

2

+3.3V_RUN +LCDVDD

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

1

C243

C243

2

Close to JLVD1.28 Close to JLVD1.6,7,8

U50

@U50

@

1

GND

USBP11_D+

IO2

2

IO1

VIN

PRTR5V0U2X_SOT143-4~D

PRTR5V0U2X_SOT143-4~D

3
4

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

1

C244

C244

2

USBP11_D-

+CMOS_VDD

3

2

1

LCD Power

D

+15V_ALW +3.3V_RUN

+LCDVDD

Q13A

2N7002DW-T/R7_SOT363-6~D

2N7002DW-T/R7_SOT363-6~D

LCD_VCC_TEST_EN<37>

ENVDD_GPU<51>

Dual layout for Q17

Overlap on Q16 for pop option

+PWR_SRC

Q17

Q17
SI3457DV-T1_TSOP6~D

4 5

PWR_SRC_ON

SI3457DV-T1_TSOP6~D

D

D

6

S

S

2
1

G

G

3

Q13A

D3

D3

3

1

2

BAT54CW_SOT323~D

BAT54CW_SOT323~D

1 2

R164 0_0402_5%~D@ R164 0_0402_5%~D@

+INV_PWR_SRC

+15V_ALW

470_0402_5%~D

470_0402_5%~D

12

R161

R161

61

2

2

100K_0402_5%~D

100K_0402_5%~D

12

1

O

I

G

3

+PWR_SRC

R162

R162

5

Q15

Q15
DDTC124EUA-7-F_SOT323-3~D

DDTC124EUA-7-F_SOT323-3~D

40mil

1000P_0402_50V7K~D

1000P_0402_50V7K~D

C248

C248

12

R167

R167
100K_0402_5%~D

100K_0402_5%~D

R168 100K_0402_5%~D

R168 100K_0402_5%~D

1

2

SI3457DV : P CHANNAL

12

R158

R158
100K_0402_5%~D

100K_0402_5%~D

2N7002DW-T/R7_SOT363-6~D

2N7002DW-T/R7_SOT363-6~D

3

4

PWR_SRC_ON

1 2

Q13B

Q13B

+LCDVDD

12

RUN_ON<28,37,40,41,50>

D

S

S

4 5

G

G

SI3456DV-T1-E3_TSOP6~D

SI3456DV-T1-E3_TSOP6~D

3

100K_0402_5%~D

100K_0402_5%~D

0.1U_0603_25V7K~D

0.1U_0603_25V7K~D

@R163

@

R163

1

C242

C242

2

Q16

@Q16

@

FDS4435_NL_SO8~D

FDS4435_NL_SO8~D

8
7

1

6

2

5

3

4

D

D

1 3

2

6
2

1

Q12

Q12

40mil

1

C247

C247

0.1U_0603_50V4Z~D

0.1U_0603_50V4Z~D

2

Q18

Q18
2N7002W-7-F_SOT323-3~D

2N7002W-7-F_SOT323-3~D

S

S

G

G

FDS4435: P CHANNAL

1

C241

C241

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

2

+INV_PWR_SRC

Webcam PWR CTRL

13

D

D

CCD_OFF<37>

A A

2

G

G

S

S

Q133

Q133

2N7002W-7-F_SOT323-3~D

2N7002W-7-F_SOT323-3~D

C1027

C1027

1

2

4700P_0402_25V7K~D

4700P_0402_25V7K~D

USBP11-<24>

USBP11+<24>

USBP11-

5

4

L59

@L59

@

DLW21SN121SQ2L_4P~D

DLW21SN121SQ2L_4P~D

1

1

2

4

4

3

1 2

R457 0_0402_5%~D

R457 0_0402_5%~D

1 2

R513 0_0402_5%~D

R513 0_0402_5%~D

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

USBP11_D-

2

USBP11_D+USBP11+

3

2

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, MB A4042

SCHEMATIC, MB A4042

SCHEMATIC, MB A4042

401533

401533

401533

19 56Tuesday, December 18, 2007

19 56Tuesday, December 18, 2007

19 56Tuesday, December 18, 2007

of

of

1

of

A

A

A

2

DA204U_SOT323-3~D

DA204U_SOT323-3~D

1

@

@

D5

+3.3V_RUN

RED_CRT

GREEN_CRT

BLUE_CRT

12

B B

GPU_DAT_DDC<51>

GPU_CLK_DDC<51>

CRT_VSYNC_GPU<51>
CRT_HSYNC_GPU<51>

CRT_RED_GPU<51>
CRT_GRN_GPU<51>
CRT_BLU_GPU<51>
TV_CVBS_GPU<51>
TV_Y_GPU<51>
TV_C_GPU<51>

CRT_SWITCH<37>

SEL CRT TV
0 MB LIO
1 APR/SPR NA

1 2

R669 150_0402_1%~D@R669 150_0402_1%~D@

1 2

R762 150_0402_1%~D@R762 150_0402_1%~D@

1 2

R763 150_0402_1%~D@R763 150_0402_1%~D@

Prevent TV impedance
error when switch

A A

+3.3V_RUN

GPU_DAT_DDC
GPU_CLK_DDC

CRT_SWITCH

TV_CVBS_RSV
TV_Y_RSV
TV_C_RSV

U4

U4

4

VCC

10

VCC

18

VCC

27

VCC

38

VCC

50

VCC

56

VCC

2

A0

3

A1

7

A2

8

A3

11

A4

12

A5

14

A6

15

A7

19

A8

20

A9

17

SEL

1

GND

6

GND

9

GND

13

GND

16

GND

21

GND

24

GND

28

GND

33

GND

39

GND

44

GND

49

GND

53

GND

55

GND

TS3DV520ERHUR_QFN56_11X5~D

TS3DV520ERHUR_QFN56_11X5~D

12

R172

R172

150_0402_1%~D

150_0402_1%~D

48

0B1

47

1B1

43

2B1

42

3B1

37

4B1

36

5B1

32

6B1

31

7B1

22

8B1

23

9B1

46

0B2

45

1B2

41

2B2

40

3B2

35

4B2

34

5B2

30

6B2

29

7B2

25

8B2

26

9B2

52

NC

5

NC

54

NC

51

NC

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

HSYNC_BUF

VSYNC_BUF

12

R173

R173

R174

R174

150_0402_1%~D

150_0402_1%~D

150_0402_1%~D

150_0402_1%~D

DAT_DDC2_CRT
CLK_DDC2_CRT
VSYNC_BUF
HSYNC_BUF
RED_CRT
GREEN_CRT
BLUE_CRT

DAT_DDC2_DOCK
CLK_DDC2_DOCK
VSYNC_DOCK
HSYNC_DOCK
RED_DOCK
GREEN_DOCK
BLUE_DOCK
TV_CVBS_RSV
TV_Y_RSV
TV_C_RSV

+5V_RUN

1 2

C269

C269

1 2

C270

C270

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

21

+5V_RUN_SYNC

10P_0402_50V8J~D

10P_0402_50V8J~D

1

1

C255

C255

2

2

DAT_DDC2_DOCK <35>
CLK_DDC2_DOCK <35>
VSYNC_DOCK <35>
HSYNC_DOCK <35>
RED_DOCK <35>
GREEN_DOCK <35>
BLUE_DOCK <35>

D9

D9
SDM10U45-7_SOD523-2~D

SDM10U45-7_SOD523-2~D

5

1

P

OE#

A2Y

G

U5

U5
SN74AHCT1G125GW_SC70-5~D

SN74AHCT1G125GW_SC70-5~D

3

5

1

P

OE#

A2Y

G

U6

U6
SN74AHCT1G125GW_SC70-5~D

SN74AHCT1G125GW_SC70-5~D

3

10P_0402_50V8J~D

10P_0402_50V8J~D

C256

C256

4

4

10P_0402_50V8J~D

10P_0402_50V8J~D

1

2

1

2

L8

L8
BLM18BB470SN1D_0603~D

BLM18BB470SN1D_0603~D
L9

L9
BLM18BB470SN1D_0603~D

BLM18BB470SN1D_0603~D
L10

L10
BLM18BB470SN1D_0603~D

BLM18BB470SN1D_0603~D

C257

C257

10U_0805_10V4Z~D

10U_0805_10V4Z~D

1 2

1 2

1 2

To MB CRT Conn.

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

C260

C260

1

1

C261

C261

2

2

1

C259

C259

2

1 2

R179 1K_0402_5%~DR179 1K_0402_5%~D

HSYNC_CRT

VSYNC_CRT

RED_CRT_L

GREEN_CRT_L

BLUE_CRT_L

22P_0402_50V8J~D

22P_0402_50V8J~D

22P_0402_50V8J~D

22P_0402_50V8J~D

C390

C390

1

1

C518

C518

2

2

1

2

To Dock Conn.

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

C262

C262

0.1U_0402_16V4Z~D

1

1

C263

C263

C264

C264

2

2

22P_0402_50V8J~D

22P_0402_50V8J~D

1

2

C996

C996

+3.3V_RUN

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

C265

C265

1 2

L61

L61
BLM18BB470SN1D_0603~D

BLM18BB470SN1D_0603~D

1 2

L62

L62
BLM18BB470SN1D_0603~D

BLM18BB470SN1D_0603~D

1 2

L63

L63
BLM18BB470SN1D_0603~D

BLM18BB470SN1D_0603~D

DAT_DDC2_CRT
CLK_DDC2_CRT

HSYNC_CRT

VSYNC_CRT

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

1

C266

C266

2

1 2

R177 0_0402_5%~DR177 0_0402_5%~D

1 2

R178 0_0402_5%~DR178 0_0402_5%~D

D5

2

3

10P_0402_50V8J~D

10P_0402_50V8J~D

1

C251

C251

2

+5V_RUN_SYNC

HSYNC_L2

VSYNC_L2

DA204U_SOT323-3~D

DA204U_SOT323-3~D

1

D6

D6

2

3

10P_0402_50V8J~D

10P_0402_50V8J~D

1

C252

C252

2

2.2K_0402_5%~D

2.2K_0402_5%~D

2.2K_0402_5%~D

2.2K_0402_5%~D

12

12

R794

R794

R793

R793

L11

L11

BLM18AG121SN1D_0603~D

BLM18AG121SN1D_0603~D

1 2

L12

L12

BLM18AG121SN1D_0603~D

BLM18AG121SN1D_0603~D

1 2

1

DA204U_SOT323-3~D

DA204U_SOT323-3~D

1

@

C253

C253

@

D7

D7

2

3

1K_0402_5%~D

1K_0402_5%~D

12

@R176

@

R176

22P_0402_50V8J~D

22P_0402_50V8J~D

1

C268

C268

2

@

@

10P_0402_50V8J~D

10P_0402_50V8J~D

1

2

1K_0402_5%~D

1K_0402_5%~D

12

@R175

@

R175

22P_0402_50V8J~D

22P_0402_50V8J~D

1

C267

C267

2

+5V_RUN

5A_125V_R451005.MRL~D

5A_125V_R451005.MRL~D

@F2

@

F2

1 2

SDM10U45-7_SOD523-2~D

SDM10U45-7_SOD523-2~D

21

D8

D8

+CRT_VCC

+5V_RUN_CRT

0_1206_5%~D

0_1206_5%~D

R171

R171

1 2

R

G
JVGA_HS

B
+CRT_VCC
JVGA_VS
M_ID2#

1

C258

C258

2

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

0.01U_0402_16V7K~D

0.01U_0402_16V7K~D

1

C254

C254

2

JCRT1

JCRT1

6

11

1
7

12

2
8

16

13

17
3
9

14

4

10
15

5

SUYIN_070546FR015S558ZR

SUYIN_070546FR015S558ZR

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

2

1

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

Date: Sheet

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

SCHEMATIC, MB A4042

SCHEMATIC, MB A4042

SCHEMATIC, MB A4042

401533

401533

401533

20 56Tuesday, December 18, 2007

20 56Tuesday, December 18, 2007

20 56Tuesday, December 18, 2007

A

A

A

of

of

of

DELL CONFIDENTIAL/PROPRIETARY

2

1

Display port Connector

+3.3V_RUN

21

D10

D10
SDM10U45-7_SOD523-2~D

SDM10U45-7_SOD523-2~D

+3.3V_RUN_R

0_1206_5%~D

0_1206_5%~D

R184

@F1

@

F1

R184

+VDISPLAY_VCC

0.01U_0402_16V7K~D

1 2

1 2

D11

D11

@

@

1
2
4
5
3

8

8

RCLAMP0524P.TCT~D

RCLAMP0524P.TCT~D

D12

D12

@

@

1
2
4
5
3

8

8

RCLAMP0524P.TCT~D

RCLAMP0524P.TCT~D

D13

D13

@

@

1
2
4
5
3

8

8

RCLAMP0524P.TCT~D

RCLAMP0524P.TCT~D

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

SCHEMATIC, MB A4042

SCHEMATIC, MB A4042

SCHEMATIC, MB A4042

401533

401533

401533

0.01U_0402_16V7K~D

1

2

JDP1

JDP1

20

DP_PWR

19

RTN

18

HP_DET

17

AUX_CH-

16

GND

15

AUX_CH+

14

GND

13

CA_DET

12

LANE3-

11

LANE3_shield

10

LANE3+

9

LANE2-

8

LANE2_shield

7

LANE2+

6

LANE1-

5

LANE1_shield

4

LANE1+

3

LANE0-

2

LANE0_shield

1

LANE0+

MOLEX_105019-0001

MOLEX_105019-0001

DPB_MB_LANE0_C

10

DPB_MB_LANE0#_C

9

DPB_MB_LANE1_C

7

DPB_MB_LANE1#_C

6

DPB_MB_LANE2_C

10

DPB_MB_LANE2#_C

9

DPB_MB_LANE3_C

7

DPB_MB_LANE3#_C

6

DPB_MB_AUX#DPB_MB_AUX#

10
9
7
6

C275

C275

21

GND

22

GND

23

GND

24

GND

A

A

21 56Tuesday, December 18, 2007

21 56Tuesday, December 18, 2007

21 56Tuesday, December 18, 2007

A

of

of

of

R964

R964
0_0402_5%~D

0_0402_5%~D

1 2

R966

R966
0_0402_5%~D

0_0402_5%~D

1 2

100K_0402_5%~D

100K_0402_5%~D

R189

R189

1 2

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

1

C938

C938

C939

C939

2

State
Normal Mode
Low power Mode

DPB_AUX_C

2N7002DW-T/R7_SOT363-6

2N7002DW-T/R7_SOT363-6

1 2

R74 33_0402_5%~DR74 33_0402_5%~D

2N7002DW-T/R7_SOT363-6

2N7002DW-T/R7_SOT363-6

DPB_AUX#C

4

1 2

R89 33_0402_5%~DR89 33_0402_5%~D

DP_PRIORITY<37>

0.01U_0402_16V7K~D

0.01U_0402_16V7K~D

1000P_0402_50V7K~D

1000P_0402_50V7K~D

1

1

C940

C940

C941

C941

2

2

+3.3V_RUN

100K_0402_5%~D

100K_0402_5%~D

100K_0402_5%~D

2

Q19A

Q19A

Q19B

Q19B

5

DPB_LANE_P0_C<51>
DPB_LANE_N0_C<51>

DPB_LANE_P1_C<51>
DPB_LANE_N1_C<51>

DPB_LANE_P2_C<51>
DPB_LANE_N2_C<51>

DPB_LANE_P3_C<51>
DPB_LANE_N3_C<51>

DPB_DOCK_HPD<35>

DPB_DOCK_CA_DET<35>

100K_0402_5%~D

100K_0402_5%~D

R190

R190

1 2

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

1

2

C271

C271

61

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

C273

C273

3

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

5.11K_0402_1%~D

5.11K_0402_1%~D

12

C950

C950

12

12

4

R193

R193

+3.3V_RUN

1

DPB_AUX_SW
DPB_AUX#SW

DP_MB_HPD_EN
DPB_DOCK_HPD

DPB_MB_CA_DET
DPB_DOCK_CA_DET

+3.3V_RUN_LP

DP_PRIORITY

+5V_RUN

R180

R180

1 2

1 2

C277

C277

1 2

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

5

P

NC

A2Y

G

U8

U8
NC7SZ04P5X_NL_SC70-5~D

NC7SZ04P5X_NL_SC70-5~D

3

100K_0402_5%~D

R181

R181

DPB_AUX_SW

DPB_AUX#SW

+3.3V_RUN

DPB_CA_DET

U9

U9

3

ML_IN 0(p)

4

ML_IN 0(n)

6

ML_IN 1(p)

7

ML_IN 1(n)

9

ML_IN 2(p)

10

ML_IN 2(n)

12

ML_IN 3(p)

13

ML_IN 3(n)

36

AUX (p)

35

AUX (n)

40

HPD_A

32

HPD_B

41

CAD_A

33

CAD_B

30

LP

29

Priority

1

DPVadj

38

VDD*1

2

VDD

8

VDD

14

VDD

17

VDD

23

VDD

34

VDD

48

VDD

54

VDD

TS2DP512_QFN56_8X8~D

TS2DP512_QFN56_8X8~D

DescriptionLevel
Standard operational mode for device
Device is forced into a low power mode

causing the output s to go to a high-Z
state, all other inputs are ignore

2

DPC_DOCK_AUX<51>

DPC_DOCK_AUX#<51>

DVI_C_DAT_DDC<51>

DVI_C_CLK_DDC<51>

ML_A 0(p)
ML_A 0(n)

ML_A 1(p)
ML_A 1(n)

ML_A 2(p)
ML_A 2(n)

ML_A 3(p)
ML_A 3(n)

AUX_A (p)
AUX_A (n)

ML_B 0(p)
ML_B 0(n)

ML_B 1(p)
ML_B 1(n)

ML_B 2(p)
ML_B 2(n)

ML_B 3(p)
ML_B 3(n)

AUX_B (p)
AUX_B (n)

Thermal GND

R965

R965
0_0402_5%~D

0_0402_5%~D

DPC_DOCK_AUX_C

1 2

1 2

R92 33_0402_5%~DR92 33_0402_5%~D

R967

R967

0_0402_5%~D

0_0402_5%~D

DPC_DOCK_AUX#C

1 2

1 2

R764 33_0402_5%~DR764 33_0402_5%~D

1 2

R821 100K_0402_5%~DR821 100K_0402_5%~D

1 2

R185 1M_0402_5%~DR185 1M_0402_5%~D

1 2

R186 100K_0402_5%~DR186 100K_0402_5%~D

1 2

R187 1M_0402_5%~DR187 1M_0402_5%~D

1 2

R188 100K_0402_5%~DR188 100K_0402_5%~D

DPB_MB_LANE0 DPB_MB_LANE0_C

56

DPB_MB_LANE0# DPB_MB_LANE0#_C

55

DPB_MB_LANE1 DPB_MB_LANE1_C

53

DPB_MB_LANE1#

52

DPB_MB_LANE2 DPB_MB_LANE2_C

50

DPB_MB_LANE2#

49

DPB_MB_LANE3

47

DPB_MB_LANE3#

46

DPB_MB_AUX

45

DPB_MB_AUX#

43

DPB_DOCK_LANE0

25

DPB_DOCK_LANE0#

24

DPB_DOCK_LANE1

22

DPB_DOCK_LANE1#

21

DPB_DOCK_LANE2

19

DPB_DOCK_LANE2#

18

DPB_DOCK_LANE3

16

DPB_DOCK_LANE3#

15

DPB_DOCK_AUX

28

DPB_DOCK_AUX#

26

DPB_HPD_R

37

HPD

DPB_CA_DET

39

CAD

5

GND

11

GND

20

GND
GND
GND
GND
GND
GND

27
31
42
44
51

57

R875 100K_0402_5%~DR875 100K_0402_5%~D
R876 100K_0402_5%~DR876 100K_0402_5%~D

R877 100K_0402_5%~DR877 100K_0402_5%~D
R878 100K_0402_5%~DR878 100K_0402_5%~D
R879 100K_0402_5%~D@R879 100K_0402_5%~D@
R880 100K_0402_5%~D@R880 100K_0402_5%~D@

2

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

61

Q20A

Q20A

2N7002DW-T/R7_SOT363-6

2N7002DW-T/R7_SOT363-6

Q20B

Q20B

2N7002DW-T/R7_SOT363-6

2N7002DW-T/R7_SOT363-6

C278 0.1U_0402_10V7K~DC278 0.1U_0402_10V7K~D
C279 0.1U_0402_10V7K~DC279 0.1U_0402_10V7K~D

C280 0.1U_0402_10V7K~DC280 0.1U_0402_10V7K~D
C281 0.1U_0402_10V7K~DC281 0.1U_0402_10V7K~D

C282 0.1U_0402_10V7K~DC282 0.1U_0402_10V7K~D
C283 0.1U_0402_10V7K~DC283 0.1U_0402_10V7K~D

C284 0.1U_0402_10V7K~DC284 0.1U_0402_10V7K~D
C285 0.1U_0402_10V7K~DC285 0.1U_0402_10V7K~D

C286 0.1U_0402_10V7K~DC286 0.1U_0402_10V7K~D
C287 0.1U_0402_10V7K~DC287 0.1U_0402_10V7K~D

C288 0.1U_0402_10V7K~DC288 0.1U_0402_10V7K~D
C289 0.1U_0402_10V7K~DC289 0.1U_0402_10V7K~D

C290 0.1U_0402_10V7K~DC290 0.1U_0402_10V7K~D
C291 0.1U_0402_10V7K~DC291 0.1U_0402_10V7K~D

C292 0.1U_0402_10V7K~DC292 0.1U_0402_10V7K~D
C293 0.1U_0402_10V7K~DC293 0.1U_0402_10V7K~D

3

4

5

DPC_CA_DET

DPB_MB_CA_DET
DPB_MB_HPD
DPB_DOCK_CA_DET
DPB_DOCK_HPD

12
12

12
12

12
12

12
12

12
12

12
12

12
12

12
12

DPB_DOCK_AUX <35>
DPB_DOCK_AUX# <35>

DPB_CA_DET <51>

DPB_MB_AUX

12

DPB_MB_AUX#

12

DPB_DOCK_AUX

12

DPB_DOCK_AUX#

12

DPC_DOCK_AUX

12

DPC_DOCK_AUX#

12

Pads for interoperability,
remove in X01 if not needed.

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

C272

C272

12

C274

C274

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

12

4

DPB_MB_LANE1#_C

DPB_MB_LANE2#_C
DPB_MB_LANE3_C

DPB_MB_LANE3#_C

DPB_DOCK_LANE0_C <35>
DPB_DOCK_LANE0#_C <35>

DPB_DOCK_LANE1_C <35>
DPB_DOCK_LANE1#_C <35>

DPB_DOCK_LANE2_C <35>
DPB_DOCK_LANE2#_C <35>

DPB_DOCK_LANE3_C <35>
DPB_DOCK_LANE3#_C <35>

R209 100K_0402_5%~D@R209 100K_0402_5%~D@
R278 100K_0402_5%~D@R278 100K_0402_5%~D@
R336 100K_0402_5%~D@R336 100K_0402_5%~D@
R337 100K_0402_5%~D@R337 100K_0402_5%~D@
R419 100K_0402_5%~D@R419 100K_0402_5%~D@
R647 100K_0402_5%~D@R647 100K_0402_5%~D@

+3.3V_RUN

100K_0402_5%~D

100K_0402_5%~D

100K_0402_5%~D

100K_0402_5%~D

R182

R182

1 2

1 2

C276 0.1U_0402_16V4Z~DC276 0.1U_0402_16V4Z~D

1 2

5

1

NC7SZ04P5X_NL_SC70-5~D

NC7SZ04P5X_NL_SC70-5~D
U7

U7

P

NC

A2Y

G

3

+3.3V_RUN

12
12
12
12
12
12

DOCK_DET#<35,37>

DP_MB_EN<37>

R183

R183

DPC_CA_DET

DPB_HPD_R

+3.3V_RUN

1 2

R911

@ R911

@

1 2

R968

R968

1 2

DPB_MB_HPD

100K_0402_5%~D

100K_0402_5%~D

DPC_DOCK_AUX_SW <35>

DPC_DOCK_AUX#SW <35>

DPC_CA_DET <35,51>

+3.3V_RUN

R798

R798
10K_0402_5%~D

10K_0402_5%~D

1 2
13

D

D

Q10

BSS138_SOT23~D

Q10

BSS138_SOT23~D

2

G

G

S

S

R191

R191

+3.3V_RUN

U66

0_0402_5%~D

0_0402_5%~D
0_0402_5%~D

0_0402_5%~D

U66

1
2

1 2

C1018 0.1U_0402_16V4Z~DC1018 0.1U_0402_16V4Z~D

5

P

A

4

Y

74AHCT1G08GW SOT353~D

74AHCT1G08GW SOT353~D

B

G

3

5A_125V_R451005.MRL~D

5A_125V_R451005.MRL~D

DPB_MB_HPD
DPB_MB_AUX#

DPB_MB_AUX

DPB_MB_P14<51>

DPB_HPD# <51>

DPB_MB_P14
DPB_MB_CA_DET
DPB_MB_LANE3#_C

DPB_MB_LANE3_C
DPB_MB_LANE2#_C

DPB_MB_LANE2_C
DPB_MB_LANE1#_C

DPB_MB_LANE1_C
DPB_MB_LANE0#_C

DPB_MB_LANE0_C

DPB_MB_LANE0_C
DPB_MB_LANE0#_C
DPB_MB_LANE1_C
DPB_MB_LANE1#_C

DPB_MB_LANE2_C
DPB_MB_LANE2#_C
DPB_MB_LANE3_C
DPB_MB_LANE3#_C

DPB_MB_AUX DPB_MB_AUX
DPB_MB_HPD DPB_MB_HPD
DPB_MB_CA_DET DPB_MB_CA_DET

Place close to JDP1 connector

DP_MB_HPD_EN

DELL CONFIDENTIAL/PROPRIETARY

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

1

Date: Sheet

SW for MB side SW for eDOCK side

DPB_AUX<51>

DVI_B_CLK_DDC<51>

DPB_AUX#<51>

DVI_B_DAT_DDC<51>

B B

+3.3V_RUN

+5V_RUN +3.3V_RUN

A A

1U_0603_10V4Z~D

1U_0603_10V4Z~D

1

1

C937

C937

2

2

Pin30

Hi
Low

LP

5

4

3

2

1

+3.3V_RUN

R194 8.2K_0402_5%~DR194 8.2K_0402_5%~D

D D

C C

B B

1 2

R195 8.2K_0402_5%~DR195 8.2K_0402_5%~D

1 2

R196 8.2K_0402_5%~DR196 8.2K_0402_5%~D

1 2

R197 8.2K_0402_5%~D

R197 8.2K_0402_5%~D

1 2

R198 8.2K_0402_5%~D

R198 8.2K_0402_5%~D

1 2

R199 8.2K_0402_5%~D

R199 8.2K_0402_5%~D

1 2

R200 8.2K_0402_5%~D

R200 8.2K_0402_5%~D

1 2

R201 8.2K_0402_5%~D

R201 8.2K_0402_5%~D

1 2

+3.3V_RUN

R202 8.2K_0402_5%~D

R202 8.2K_0402_5%~D

1 2

R203 8.2K_0402_5%~D

R203 8.2K_0402_5%~D

1 2

R204 8.2K_0402_5%~D

R204 8.2K_0402_5%~D

1 2

R205 8.2K_0402_5%~D

R205 8.2K_0402_5%~D

1 2

R207 8.2K_0402_5%~D

R207 8.2K_0402_5%~D

1 2

R208 8.2K_0402_5%~D

R208 8.2K_0402_5%~D

1 2

R702 100K_0402_5%~D

R702 100K_0402_5%~D

1 2

R755 100K_0402_5%~D

R755 100K_0402_5%~D

1 2

R212 100K_0402_5%~DR212 100K_0402_5%~D

1 2

R817 100K_0402_5%~D

R817 100K_0402_5%~D

1 2

PCI_DEVSEL#
PCI_STOP#
PCI_TRDY#
PCI_FRAME#
PCI_PLOCK#
PCI_IRDY#
PCI_SERR#
PCI_PERR#

PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#
PCI_REQ0#
PCI_REQ1#
FAN1_DET#
LVDS_CBL_DET#
CAM_MIC_CBL_DET#
PNL_BKLT_CBL_DET#

PCI_AD[0..31]<31>

PCI_GNT3#

PCI_PIRQB#<31>
PCI_PIRQC#<31>
PCI_PIRQD#<31>

12

R215

@R215

@

1K_0402_5%~D

1K_0402_5%~D

PCI_AD0
PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD6
PCI_AD7
PCI_AD8
PCI_AD9
PCI_AD10
PCI_AD11
PCI_AD12
PCI_AD13
PCI_AD14
PCI_AD15
PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20
PCI_AD21
PCI_AD22
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30
PCI_AD31

PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#

U10B

U10B

D11

AD0

C8
D9

E12

E9

C9

E10

B7
C7
C5

G11

F8

F11

E7

A3
D2

F10

D5

D10

B3

F7
C3

F3

F4
C1
G7
H7
D1
G5
H6
G1
H3

J5

E1

J6

PCI

PCI

AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31

Interrupt I/F

Interrupt I/F

PIRQA#
PIRQB#
PIRQC#
PIRQD#C4PIRQH#/GPIO5

ICH9M REV 1.0

ICH9M REV 1.0

PCI_GNT0#

REQ0#

GNT0#
REQ1#/GPIO50
GNT1#/GPIO51
REQ2#/GPIO52
GNT2#/GPIO53
REQ3#/GPIO54
GNT3#/GPIO55

C/BE0#
C/BE1#
C/BE2#
C/BE3#

IRDY#

PAR
PCIRST#
DEVSEL#

PERR#

PLOCK#

SERR#

STOP#
TRDY#

FRAME#

PLTRST#

PCICLK

PME#

PIRQE#/GPIO2
PIRQF#/GPIO3

PIRQG#/GPIO4

12

F1
G4
B6
A7
F13
F12
E6
F6

D8
B4
D6
A5

D3
E3
R1
C6
E4
C2
J4
A4
F5
D7

C14
D4
R2

H4
K6
F2
G2

R213

R213
1K_0402_5%~D

1K_0402_5%~D

PCI_REQ0#
PCI_GNT0#
PCI_REQ1#
PCI_GNT1#

GNT2#/GPIO53
PCI_GNT3#
PCI_C_BE0#

PCI_C_BE1#
PCI_C_BE2#
PCI_C_BE3#

PCI_IRDY#
PCI_PAR
PCI_PCIRST#
PCI_DEVSEL#
PCI_PERR#
PCI_PLOCK#
PCI_SERR#
PCI_STOP#
PCI_TRDY#
PCI_FRAME#

PCI_PLTRST#
CLK_PCI_ICH
ICH_PME#

LVDS_CBL_DET#
PNL_BKLT_CBL_DET#
CAM_MIC_CBL_DET#
FAN1_DET#

ICH_SPI_CS1#<24>

PCI_REQ1# <31>

PCI_GNT1# <31>

PCIE_MCARD2_DET# <34>

T183PAD~DT183PAD~D

PCIE_MCARD3_DET# <34>

PCI_C_BE0# <31>
PCI_C_BE1# <31>
PCI_C_BE2# <31>
PCI_C_BE3# <31>

PCI_IRDY# <31>
PCI_PAR <31>

PCI_DEVSEL# <31>
PCI_PERR# <31>

PCI_SERR# <31>

PCI_STOP# <31>

PCI_TRDY# <31>

PCI_FRAME# <31>

CLK_PCI_ICH <6>

ICH_PME# <37>

LVDS_CBL_DET# <19>

PNL_BKLT_CBL_DET# <19>

CAM_MIC_CBL_DET# <19>

FAN1_DET# <18>

ICH_SPI_CS1#

12

R214

@R214

@

1K_0402_5%~D

1K_0402_5%~D

PCI_PCIRST#

PCI_PLTRST#

+3.3V_ALW_ICH

14

1

P

IN1

OUT

2

IN2

G

U11A

U11A

7

74VHC08MTCX_NL_TSSOP14~D

74VHC08MTCX_NL_TSSOP14~D

+3.3V_ALW_ICH

14

4

P

IN1

OUT

5

IN2

G

U11B

U11B

7

74VHC08MTCX_NL_TSSOP14~D

74VHC08MTCX_NL_TSSOP14~D

+3.3V_ALW_ICH

14

10

P

IN1

OUT

9

IN2

G

U11C

U11C

7

74VHC08MTCX_NL_TSSOP14~D

74VHC08MTCX_NL_TSSOP14~D

+3.3V_ALW_ICH

14

13

P

IN1

OUT

12

IN2

G

U11D

U11D

7

74VHC08MTCX_NL_TSSOP14~D

74VHC08MTCX_NL_TSSOP14~D

C294

C294

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

PCI_RST#

3

PLTRST1#

6

PLTRST2#

8

PLTRST3#

11

PCI_RST# <31,35>

PLTRST1# <10,32,51>

PLTRST2# <37,38>

PLTRST3# <34,36>

Place closely pin U10.D4

CLK_PCI_ICH

A16 away override strap.

PCI_GNT3#/(MDC_RST_DIS#)

A A

Low = A16 swap override enabled.
High = Default. pull up internal

5

4

Boot BIOS Strap

PCI_GNT0# SPI_CS1#

*

0

1

1

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

1

0

1

3

Boot BIOS Location

SPI

PCI

LPC

R216

@R216

@

10_0402_5%~D

10_0402_5%~D

1 2

CLK_ICH_TERM

1

C295

@C295

@

8.2P_0402_50V8J~D

8.2P_0402_50V8J~D

2

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, MB A4042

SCHEMATIC, MB A4042

SCHEMATIC, MB A4042

401533

401533

401533

A

A

22 56Tuesday, December 18, 2007

22 56Tuesday, December 18, 2007

22 56Tuesday, December 18, 2007

1

A

of

of

of

5

D D

C C

B B

A A

+3.3V_ALW_ICH

R221 10K_0402_5%~D

R221 10K_0402_5%~D

CMOS settingCMOS_CLR1
Shunt
Open

Clear CMOS

Keep CMOS

TPM settingME_CLR1

Shunt

Clear ME RTC Registers

Open

Keep ME RTC Registers

1

1

ME_CLR1 @SHORT PADS~DME_CLR1 @SHORT PADS~D

C298 1U_0603_10V4Z~D

C298 1U_0603_10V4Z~D

Close to U55

ICH_AZ_CODEC_SDOUT<27>

ICH_AZ_CODEC_SYNC<27>

ICH_AZ_CODEC_RST#<27>

ICH_AZ_CODEC_BITCLK<27>

C302

@C302

@

27P_0402_50V8J~D

27P_0402_50V8J~D

ICH_AZ_GPU_SDOUT<51>

ICH_AZ_GPU_SYNC<51>

ICH_AZ_GPU_RST#<51>

ICH_AZ_GPU_BITCLK<51>

C309

@C309

@

27P_0402_50V8J~D

27P_0402_50V8J~D

00

0

1

11

GLAN_DOCK#

12

+RTC_CELL

2

2

1 2

ICH_AZ_SDOUT

1 2

R234 33_0402_5%~D R234 33_0402_5%~D
R235 33_0402_5%~D R235 33_0402_5%~D
R239 33_0402_5%~D

R239 33_0402_5%~D
R241 33_0402_5%~D R241 33_0402_5%~D

1

2

R243 33_0402_5%~D@ R243 33_0402_5%~D@
R244 33_0402_5%~D@ R244 33_0402_5%~D@
R245 33_0402_5%~D@ R245 33_0402_5%~D@
R246 33_0402_5%~D@ R246 33_0402_5%~D@

1

2

1 2
1 2
1 2

1 2
1 2
1 2
1 2

ICH_AZ_SYNC
ICH_AZ_RST#
ICH_AZ_BITCLK

ICH_AZ_SDOUT
ICH_AZ_SYNC
ICH_AZ_RST#
ICH_AZ_BITCLK

XOR Chain Entrance Strap

DescriptionICH RSVD_TP3 HDA SDOUT

RSVD

1

Enter XOR Chain

0

Normal Operation (Default)

Set PCIE port config bit 1

32.768K_12.5P_1TJS125DJ4A420P~D

32.768K_12.5P_1TJS125DJ4A420P~D

R224 20K_0402_5%~D

R224 20K_0402_5%~D

1 2

R225 20K_0402_5%~D

R225 20K_0402_5%~D

1 2

R226 1M_0402_5%~D

R226 1M_0402_5%~D

1 2

1

1

CMOS_CLR1 @SHORT PADS~DCMOS_CLR1 @SHORT PADS~D

1 2

C299 1U_0603_10V4Z~D

C299 1U_0603_10V4Z~D

SATA_ODD_IRX_DTX_N1_C<26>
SATA_ODD_IRX_DTX_P1_C<26>

SATA_ODD_ITX_DRX_N1<26>
SATA_ODD_ITX_DRX_P1<26>

2

2

ICH_AZ_MDC_BITCLK<33>
ICH_AZ_MDC_SYNC<33>

ICH_AZ_MDC_RST#<33>

ICH_AZ_CODEC_SDIN0<27>

ICH_AZ_MDC_SDIN1<33>
ICH_AZ_GPU_SDIN2<51>

ICH_AZ_MDC_SDOUT<33>

ME_FWP<37>

SATA_ACT#_R<42>

PSATA_IRX_DTX_N0_C<26>
PSATA_IRX_DTX_P0_C<26>

PSATA_ITX_DRX_N0<26>
PSATA_ITX_DRX_P0<26>

+3.3V_RUN

4

Package

9.6X4.06 mm

12

C296

C296
15P_0402_50V8J~D

15P_0402_50V8J~D

12

C297 15P_0402_50V8J~D

C297 15P_0402_50V8J~D

LAN_RSTSYNC<29>

C300

@C300

@

27P_0402_50V8J~D

27P_0402_50V8J~D

C307 0.01U_0402_16V7K~D C307 0.01U_0402_16V7K~D
C308 0.01U_0402_16V7K~D C308 0.01U_0402_16V7K~D

C310 0.01U_0402_16V7K~D C310 0.01U_0402_16V7K~D
C311 0.01U_0402_16V7K~D C311 0.01U_0402_16V7K~D

12

R248

@R248

@

1K_0402_5%~D

1K_0402_5%~D

ICH_AZ_SDOUT

12

R249

@R249

@

1K_0402_5%~D

1K_0402_5%~D

Y1

Y1

1 4

2 3

LAN_CLK<29>

LAN_RX0<29>
LAN_RX1<29>
LAN_RX2<29>

LAN_TX0<29>
LAN_TX1<29>
LAN_TX2<29>

+1.5V_RUN_PCIE_ICH

12

R236 33_0402_5%~D

R236 33_0402_5%~D

12
12

12
12

ICH_RSVD_TP3 <24>

12

R222

R222
10M_0402_5%~D

10M_0402_5%~D

T46 PAD~DT46 PAD~D

R223

R223
0_0402_5%~D

0_0402_5%~D

1 2

1 2
1 2

R238 33_0402_5%~D R238 33_0402_5%~D

1 2

R240 33_0402_5%~D

R240 33_0402_5%~D

1 2

R242 33_0402_5%~D R242 33_0402_5%~D

ICH_RTCX1

ICH_RTCX2
ICH_RTCRST#

SRTCRST#
INTRUDER#

ICH_INTVRMEN
LAN100_SLP

LAN_RX0
LAN_RX1
LAN_RX2

LAN_TX0
LAN_TX1
LAN_TX2

GLAN_DOCK#

1 2

R232

R232

24.9_0402_1%~D

24.9_0402_1%~D

ICH_AZ_BITCLK
ICH_AZ_SYNC

ICH_AZ_RST#
ICH_AZ_CODEC_SDIN0

ICH_AZ_MDC_SDIN1
ICH_AZ_GPU_SDIN2

ICH_AZ_SDOUT
ME_FWP

RTC_BAT_DET#

SATA_ACT#_R

PSATA_ITX_DRX_N0_C
PSATA_ITX_DRX_P0_C

SATA_ODD_ITX_DRX_N1_C
SATA_ODD_ITX_DRX_P1_C

R375, R961, R960, R962 Q130 remove for RTC detect function

3

+RTC_CELL +RTC_CELL

12

R217

R217
332K_0402_1%~D

332K_0402_1%~D

ICH_INTVRMEN

R219

@R219

@

0_0402_5%~D

0_0402_5%~D

1 2

ICH9M Internal VR Enable Strap
(Internal VR for VccSus1.05, VccSus1.5, VccCL1.5)

ICH_INTVRMEN

U10A

U10A

C23

RTCX1

C24

RTCX2

A25

RTCRST#

F20

SRTCRST#

C22

INTRUDER#

B22

INTVRMEN

A22

LAN100_SLP

E25

GLAN_CLK

C13

LAN_RSTSYNC

F14

LAN_RXD0

G13

LAN_RXD1

D14

LAN_RXD2

D13

LAN_TXD0

D12

LAN_TXD1

E13

LAN_TXD2

B10

GPIO56

B28

GLAN_COMPI

B27

GLAN_COMPO

AF6

HDA_BIT_CLK

AH4

HDA_SYNC

AE7

HDA_RST#

AF4

HDA_SDIN0

AG4

HDA_SDIN1

AH3

HDA_SDIN2

AE5

HDA_SDIN3

AG5

HDA_SDOUT

AG7

HDA_DOCK_EN#/GPIO33

AE8

HDA_DOCK_RST#/GPIO34

AG8

SATALED#

AJ16

SATA0RXN

AH16

SATA0RXP

AF17

SATA0TXN

AG17

SATA0TXP

AH13

SATA1RXN

AJ13

SATA1RXP

AG14

SATA1TXN

AF14

SATA1TXP

ICH9M REV 1.0

ICH9M REV 1.0

Low = Internal VR Disabled
High = Internal VR Enabled(Default)

LPC_LAD0

K5

RTCLAN / GLANIHDASATA

LPCCPU

RTCLAN / GLANIHDASATA

LPCCPU

FWH0/LAD0
FWH1/LAD1
FWH2/LAD2
FWH3/LAD3

FWH4/LFRAME#

LDRQ0#

LDRQ1#/GPIO23

A20GATE

A20M#

DPRSTP#

DPSLP#

FERR#

CPUPWRGD

IGNNE#

INIT#

INTR

RCIN#

SMI#

STPCLK#

THRMTRIP#

TP12

SATA4RXN
SATA4RXP
SATA4TXN

SATA4TXP

SATA5RXN
SATA5RXP
SATA5TXN

SATA5TXP

SATA_CLKN
SATA_CLKP

SATARBIAS#

SATARBIAS

NMI

K4
L6
K2

K3
J3

J1
N7

AJ27
AJ25

AE23
AJ26
AD22
AF25
AE22

AG25
L3

AF23
AF24

AH27
AG26
AG27

AH11
AJ11
AG12
AF12

AH9
AJ9
AE10
AF10

AH18
AJ18

AJ7
AH7

LPC_LAD1
LPC_LAD2
LPC_LAD3

LPC_LFRAME#
LPC_LDRQ0#

LPC_LDRQ1#
SIO_A20GATE

H_A20M#
H_DPRSTP#

H_DPSLP#

R229

R229

56_0402_5%~D

56_0402_5%~D

H_PWRGOOD
H_IGNNE#
H_INIT#

H_INTR
SIO_RCIN#

H_NMI
H_SMI#

H_STPCLK#
THRMTRIP_ICH#
ICH_TP12

ESATA_ITX_DRX_N4_C
ESATA_ITX_DRX_P4_C

SATA_ITX_DRX_N3_C
SATA_ITX_DRX_P3_C

CLK_PCIE_SATA#
CLK_PCIE_SATA

R247 24.9_0402_1%~D

R247 24.9_0402_1%~D

Within 500 mils

2

12

12

LPC_LAD0 <36,37,38>
LPC_LAD1 <36,37,38>
LPC_LAD2 <36,37,38>
LPC_LAD3 <36,37,38>

SIO_A20GATE <38>
H_A20M# <7>

H_FERR# <7>
H_PWRGOOD <8>
H_IGNNE# <7>
H_INIT# <7>

H_INTR <7>
SIO_RCIN# <38>

H_NMI <7>
H_SMI# <7>

H_STPCLK# <7>

12

1 2

ICH9M LAN100 SLP Strap
(Internal VR for VccLAN1.05 and VccCL1.05)

ICH_LAN100_SLP Low = Internal VR Disabled

LPC_LAD[0..3] <36,37,38>

LPC_LFRAME# <36,37,38>
LPC_LDRQ0# <37>

LPC_LDRQ1# <37>

T41PAD~DT41PAD~D

12

C303 0.01U_0402_16V7K~D C303 0.01U_0402_16V7K~D

12

C304 0.01U_0402_16V7K~D C304 0.01U_0402_16V7K~D

12

C305 0.01U_0402_16V7K~D C305 0.01U_0402_16V7K~D

12

C306 0.01U_0402_16V7K~D C306 0.01U_0402_16V7K~D

CLK_PCIE_SATA# <6>
CLK_PCIE_SATA <6>

High = Internal VR Enabled(Default)

+1.05V_VCCP

56_0402_1%~D

56_0402_1%~D

56_0402_1%~D

56_0402_1%~D

@R228

@

@R227

@

12

12

R228

R227

H_DPRSTP# <8,10,47>
H_DPSLP# <8>

+1.05V_VCCP

12

R237

R237
56_0402_5%~D

56_0402_5%~D

1 2

C301

C301

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

ESATA_IRX_DTX_N4_C <33>

ESATA_IRX_DTX_P4_C <33>
ESATA_ITX_DRX_N4 <33>

ESATA_ITX_DRX_P4 <33>

SATA_SBRX_DTX_N3_C <35>

SATA_SBRX_DTX_P3_C <35>
SATA_SBTX_C_DRX_N3 <35>

SATA_SBTX_C_DRX_P3 <35>

R218

R218
332K_0402_1%~D

332K_0402_1%~D

LAN100_SLP

R220

@R220

@

0_0402_5%~D

0_0402_5%~D

SIO_A20GATE
SIO_RCIN#

H_FERR#

1

12

R230 10K_0402_5%~D

R230 10K_0402_5%~D

12

R231 10K_0402_5%~D

R231 10K_0402_5%~D

12

R233 56_0402_5%~DR233 56_0402_5%~D

+3.3V_RUN

+1.05V_VCCP

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, MB A4042

SCHEMATIC, MB A4042

SCHEMATIC, MB A4042

401533

401533

401533

23 56Tuesday, December 18, 2007

23 56Tuesday, December 18, 2007

23 56Tuesday, December 18, 2007

of

of

1

of

A

A

A

5

+3.3V_RUN +3.3V_RUN

R251 2.2K_0402_5%~D@R251 2.2K_0402_5%~D@
R254 10K_0402_5%~D@ R254 10K_0402_5%~D@
R258 8.2K_0402_5%~DR258 8.2K_0402_5%~D
R261 10K_0402_5%~D

R261 10K_0402_5%~D
R264 1K_0402_5%~D@R264 1K_0402_5%~D@

D D

R834 100K_0402_5%~D

R834 100K_0402_5%~D

R272 10K_0402_5%~D

R272 10K_0402_5%~D
R273 100K_0402_5%~D

R273 100K_0402_5%~D

iTPM function

R270

+3.3V_LAN

R270 1K_0402_5%~D@R270 1K_0402_5%~D@

IMVP_PWRGD

1 2

MCH_ICH_SYNC#

1 2

RSV_THRM#

1 2

IRQ_SERIRQ

12

SPKR

1 2

SPEAKER_DET#

1 2

SIO_EXT_SCI#

1 2

TPM_ID

12

No stuff = Disable
Stuff = Enable

ICH_EC_SPI_DO

1 2

No Reboot Strap

Low = Default

SPKR

High = No Reboot

+3.3V_RUN

12

C C

R282

R282

8.2K_0402_5%~D

8.2K_0402_5%~D

CLKRUN#

12

@R283

@

10_0402_5%~D

10_0402_5%~D

Option to " Disable "

R283

clkrun. Pulling it
down
will keep the clks
running.

MiniWWAN (Mini Card 1)--->

+3.3V_ALW_ICH

B B

MiniWLAN (Mini Card 2)--->

RP1

RP1

USB_OC0_1#

45

USB_OC2#

36

ESATA_USB_OC#

27

USB_OC4#

18

10K_1206_8P4R_5%~D

10K_1206_8P4R_5%~D

RP2

RP2

USB_OC6#

45

USB_OC5#

36

USB_OC7#

27

USB_OC11#

18

10K_1206_8P4R_5%~D

10K_1206_8P4R_5%~D

1 2

R288 10K_0402_5%~D

R288 10K_0402_5%~D

1 2

R291 10K_0402_5%~D

R291 10K_0402_5%~D

1 2

R293 10K_0402_5%~D

R293 10K_0402_5%~D

USB_OC9#
USB_OC10#
USB_OC8#

10/100/1G LAN --->

For iAMT

ICH_SPI_CS0#
ICH_EC_SPI_DIN

A A

1 2

R300

R300
33_0402_5%~D

33_0402_5%~D

SPI_DIN_R1

ICH_SPI_CS1#

ICH_SPI_DIN_R ICH_SPI_DIN_RICH_EC_SPI_DIN

1 2

R306

R306
33_0402_5%~D

33_0402_5%~D

@

@

SPI_DIN_R2

+3.3V_ALW_ICH

SIO_EXT_WAKE#<37>

USB_MCARD1_DET#<34>

USB_MCARD2_DET#<34>

BT/UWB--->

Express card--->

+3.3V_LAN

+3.3V_LAN

5

200 MIL SO8

Flash ROM

12

R298

R298

3.3K_0402_5%~D

3.3K_0402_5%~D
U12

U12

1

CS#

2

SO

3

WP#

4

GND

W25X32VSSIG_SO8~D

W25X32VSSIG_SO8~D

12

R304

@R304

@

3.3K_0402_5%~D

3.3K_0402_5%~D
U13

1

CS#

2

SO

3

WP#

4

GND

W25X32VSSIG_SO8~D

W25X32VSSIG_SO8~D

@U13

@

R252 2.2K_0402_5%~DR252 2.2K_0402_5%~D
R255 2.2K_0402_5%~D

R255 2.2K_0402_5%~D
R259 10K_0402_5%~D@R259 10K_0402_5%~D@
R262 10K_0402_5%~D R262 10K_0402_5%~D
R265 10K_0402_5%~D R265 10K_0402_5%~D
R267 10K_0402_5%~D R267 10K_0402_5%~D
R268 10K_0402_5%~D R268 10K_0402_5%~D
R269 10K_0402_5%~D R269 10K_0402_5%~D
R274 10K_0402_5%~D

R274 10K_0402_5%~D
R787 10K_0402_5%~D

R787 10K_0402_5%~D
R192 10K_0402_5%~D

R192 10K_0402_5%~D
R835 100K_0402_5%~D

R835 100K_0402_5%~D
R963 100K_0402_5%~DR963 100K_0402_5%~D
R823 100K_0402_5%~D

R823 100K_0402_5%~D

HOLD#

SCLK

HOLD#

SCLK

1 2
1 2
1 2
1 2
1 2
1 2

1 2
1 2
1 2
1 2
1 2
1 2

8

VCC

7
6
5

SI

8

VCC

7
6
5

SI

ICH_SMBDATA
ICH_CL_RST1#
AMT_SMBCLK
AMT_SMBDAT
ICH_RI#
ICH_PCIE_WAKE#

ME_SUS_PWR_ACK

12

SIO_EXT_SMI#
ICH_GPIO60
SMB_ALERT#
IO_LOOP
CONTACTLESS_DET#
BIO_DET#

47P_0402_50V8J~D

47P_0402_50V8J~D

@ C313

@

1

1

C313

2

2

1 2

R811 100K_0402_5%~D@R811 100K_0402_5%~D@

PCIE_IRX_WANTX_N1<34>

PCIE_IRX_WANTX_P1<34>
PCIE_ITX_WANRX_N1_C<34>
PCIE_ITX_WANRX_P1_C<34>

PCIE_IRX_WLANTX_N2<34>

PCIE_IRX_WLANTX_P2<34>
PCIE_ITX_WLANRX_N2_C<34>
PCIE_ITX_WLANRX_P2_C<34>

PCIE_IRX_MCARDTX_N3<34>

PCIE_IRX_MCARDTX_P3<34>
PCIE_ITX_MCARDRX_N3_C<34>
PCIE_ITX_MCARDRX_P3_C<34>

PCIE_IRX_EXPTX_N4<32>

PCIE_IRX_EXPTX_P4<32>
PCIE_ITX_EXPRX_N4_C<32>
PCIE_ITX_EXPRX_P4_C<32>

PCIE_IRX_GLANTX_N6<29>

PCIE_IRX_GLANTX_P6<29>
PCIE_ITX_GLANRX_N6_C<29>
PCIE_ITX_GLANRX_P6_C<29>

C328

C328

1 2

12

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

3.3K_0402_5%~D

3.3K_0402_5%~D

SPI_CLK_R1
SPI_DO_R1

R302 33_0402_5%~D

R302 33_0402_5%~D

12

3.3K_0402_5%~D

3.3K_0402_5%~D

@

@

SPI_CLK_R2
SPI_DO_R2

ICH_SMBCLK

1 2

1 2

R277 0_0402_5%~D R277 0_0402_5%~D

1 2

R280 0_0402_5%~D R280 0_0402_5%~D

1 2

R281 0_0402_5%~D R281 0_0402_5%~D

47P_0402_50V8J~D

47P_0402_50V8J~D

4700P_0402_25V7K~D

4700P_0402_25V7K~D

@ C315

@

1

@

@

C315

C316

C316

2

ITP_DBRESET#

ICH_SPI_CS1#<22>

R299

R299

R301

R301
33_0402_5%~D

33_0402_5%~D

1 2
1 2

C329

@C329

@

1 2

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

R305

R305

R308

R308
33_0402_5%~D

33_0402_5%~D

1 2
1 2

R309 33_0402_5%~D

R309 33_0402_5%~D

4

AMT_SMBCLK<38>

AMT_SMBDAT<38>

T184PAD~D T184PAD~D

ITP_DBRESET#<7,37>

PM_SYNC#<10>

H_STP_PCI#<6>
H_STP_CPU#<6>

CLKRUN#<31,37,38>

ICH_PCIE_WAKE#<37>

IRQ_SERIRQ<31,36,37,38>

IMVP_PWRGD<37,41,47>

T45PAD~D T45PAD~D

SIO_EXT_SCI#<38>

SIO_EXT_SMI#<38>

LAN_PHY_PWR_CNTRL<29,37>

CONTACTLESS_DET#<36>

SATA_CLKREQ#<6>

BIO_DET#<33>

MCH_ICH_SYNC#<10>

C317 0.1U_0402_10V7K~D

C317 0.1U_0402_10V7K~D

1 2

C319 0.1U_0402_10V7K~D

C319 0.1U_0402_10V7K~D

1 2

C320 0.1U_0402_10V7K~D

C320 0.1U_0402_10V7K~D

1 2

C321 0.1U_0402_10V7K~D

C321 0.1U_0402_10V7K~D

1 2

C322 0.1U_0402_10V7K~D

C322 0.1U_0402_10V7K~D

1 2

C323 0.1U_0402_10V7K~D

C323 0.1U_0402_10V7K~D

1 2

C803 0.1U_0402_10V7K~D

C803 0.1U_0402_10V7K~D

1 2

C804 0.1U_0402_10V7K~D

C804 0.1U_0402_10V7K~D

1 2

C326 0.1U_0402_10V7K~D

C326 0.1U_0402_10V7K~D

1 2

C327 0.1U_0402_10V7K~D

C327 0.1U_0402_10V7K~D

1 2

ICH_SPI_CS0# ICH_SPI_CS0#_R
ICH_SPI_CS1#

ESATA_USB_OC#<33>

ICH_EC_SPI_CLK
ICH_EC_SPI_DO

ICH_EC_SPI_CLK

@

@

ICH_EC_SPI_DO

@

@

4

T39PAD~D T39PAD~D
T132PAD~D T132PAD~D

SD_DET#<31>

IO_LOOP<33>

ODD_DET#<26>

T48PAD~D T48PAD~D

HDD_DET#<26>

T185PAD~D T185PAD~D

SPKR<27>

ICH_RSVD_TP3<23>

T50PAD~D T50PAD~D
T51PAD~D T51PAD~D
T52PAD~D T52PAD~D

R294

R294
33_0402_5%~D

33_0402_5%~D

1 2
1 2

R295

R295
33_0402_5%~D

33_0402_5%~D

USB_OC0_1#<33>

USB_OC2#<33>

R303

R303

22.6_0402_1%~D

22.6_0402_1%~D

Within 500 mils

Follow Daisy Chain and Star
Topology. Place close to U10
pinE23 within 500mils

ICH_SMBCLK
ICH_SMBDATA
ICH_GPIO60
AMT_SMBCLK
AMT_SMBDAT

ICH_RI#
SUS_STAT#/LPCPD#

ITP_DBRESET#
PM_SYNC#
SMB_ALERT#
H_STP_PCI#

H_STP_CPU#
CLKRUN#
ICH_PCIE_WAKE#

IRQ_SERIRQ
RSV_THRM#

IMVP_PWRGD
ICH_TP11
SIO_EXT_SCI#

TPM_ID
SIO_EXT_SMI#
CONTACTLESS_DET#

ICH_GPIO20
SD_DET#

IO_LOOP
SATA_CLKREQ#
ODD_DET#
WPAN_RADIO_DIS_MINI#
HDD_DET#
ICH_GPIO49
BIO_DET#

SPKR
MCH_ICH_SYNC#
ICH_RSVD_TP3
ICH_TP8
ICH_TP9
ICH_TP10

PCIE_IRX_WANTX_N1
PCIE_IRX_WANTX_P1
PCIE_ITX_WANRX_N1
PCIE_ITX_WANRX_P1

PCIE_IRX_WLANTX_N2
PCIE_IRX_WLANTX_P2
PCIE_ITX_WLANRX_N2
PCIE_ITX_WLANRX_P2

PCIE_IRX_MCARDTX_N3
PCIE_IRX_MCARDTX_P3
PCIE_ITX_MCARDRX_N3
PCIE_ITX_MCARDRX_P3

PCIE_IRX_EXPTX_N4
PCIE_IRX_EXPTX_P4
PCIE_ITX_EXPRX_N4
PCIE_ITX_EXPRX_P4

PCIE_IRX_GLANTX_N6
PCIE_IRX_GLANTX_P6
PCIE_ITX_GLANRX_N6
PCIE_ITX_GLANRX_P6

ICH_EC_SPI_CLK
ICH_SPI_CS1#_R
ICH_EC_SPI_DO

ICH_EC_SPI_DIN
USB_OC0_1#
USB_OC2#

ESATA_USB_OC#
USB_OC4#
USB_OC5#
USB_OC6#
USB_OC7#
USB_OC8#
USB_OC9#
USB_OC10#
USB_OC11#

USBRBIAS

12

1 2

R307 0_0402_5%~DR307 0_0402_5%~D

3

1 2

U10C

U10C

G16

SMBCLK

A13

SMBDATA

E17

LINKALERT#/GPIO60/CLGPIO4

C17

SMLINK0

B18

SMLINK1

F19

RI#

R4

SUS_STAT#/LPCPD#

G19

SYS_RESET#

M6

PMSYNC#/GPIO0

A17

SMBALERT#/GPIO11

A14

STP_PCI#

E19

STP_CPU#

L4

CLKRUN#

E20

WAKE#

M5

SERIRQ

AJ23

THRM#

D21

VRMPWRGD

A20

TP11

AG19

GPIO1

AH21

GPIO6

AG21

GPIO7

A21

GPIO8

C12

GPIO12

C21

GPIO13

AE18

GPIO17

K1

GPIO18

AF8

GPIO20

AJ22

SCLOCK/GPIO22

A9

GPIO27

D19

GPIO28

L1

SATACLKREQ#/GPIO35

AE19

SLOAD/GPIO38

AG22

SDATAOUT0/GPIO39

AF21

SDATAOUT1/GPIO48

AH24

GPIO49

A8

GPIO57/CLGPIO5

M7

SPKR

AJ24

MCH_SYNC#

B21

TP3

AH20

TP8

AJ20

TP9

AJ21

TP10

ICH9M REV 1.0

ICH9M REV 1.0

U10D

U10D

N29

PERN1

N28

PERP1

P27

PETN1

P26

PETP1

L29

PERN2

L28

PERP2

M27

PETN2

M26

PETP2

J29

PERN3

J28

PERP3

K27

PETN3

K26

PETP3

G29

PERN4

G28

PERP4

H27

PETN4

H26

PETP4

E29

PERN5

E28

PERP5

F27

PETN5

F26

PETP5

C29

PERN6/GLAN_RXN

C28

PERP6/GLAN_RXP

D27

PETN6/GLAN_TXN

D26

PETP6/GLAN_TXP

D23

SPI_CLK

D24

SPI_CS0#

F23

SPI_CS1#/GPIO58/CLGPIO6

D25

SPI_MOSI

E23

SPI_MISO

N4

OC0#/GPIO59

N5

OC1#/GPIO40

N6

OC2#/GPIO41

P6

OC3#/GPIO42

M1

OC4#/GPIO43

N2

OC5#/GPIO29

M4

OC6#/GPIO30

M3

OC7#/GPIO31

N3

OC8#/GPIO44

N1

OC9#/GPIO45

P5

OC10#/GPIO46

P3

OC11#/GPIO47

AG2

USBRBIAS

AG1

USBRBIAS#

ICH9M REV 1.0

ICH9M REV 1.0

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

DMI_CLKN

PCI-Express

PCI-Express

DMI_CLKP

Direct Media Interface

Direct Media Interface

DMI_ZCOMP

DMI_IRCOMP

SPI

SPI

USB

USB

SATA0GP/GPIO21
SATA1GP/GPIO19
SATA4GP/GPIO36
SATA5GP/GPIO37

SATA

GPIO

SATA

GPIO

SMBSYS GPIO

SMBSYS GPIO

Clocks

Clocks

S4_STATE#/GPIO26

DPRSLPVR/GPIO16

Power MGTController Link

Power MGTController Link

CK_PWRGD

GPIO

GPIO

MEM_LED/GPIO24

GPIO10/SUS_PWR_ACK

GPIO14/AC_PRESENT

WOL_EN/GPIO9

MISC

MISC

DMI_MTX_IRX_N0

V27

DMI0RXN
DMI0RXP

DMI0TXN
DMI0TXP

DMI1RXN
DMI1RXP

DMI1TXN
DMI1TXP

DMI2RXN
DMI2RXP

DMI2TXN
DMI2TXP

DMI3RXN
DMI3RXP

DMI3TXN
DMI3TXP

USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4N
USBP4P
USBP5N
USBP5P
USBP6N
USBP6P
USBP7N
USBP7P
USBP8N
USBP8P
USBP9N

USBP9P
USBP10N
USBP10P
USBP11N
USBP11P

V26
U29
U28

Y27
Y26
W29
W28

AB27
AB26
AA29
AA28

AD27
AD26
AC29
AC28

T26
T25

AF29
AF28

AC5
AC4
AD3
AD2
AC1
AC2
AA5
AA4
AB2
AB3
AA1
AA2
W5
W4
Y3
Y2
W1
W2
V2
V3
U5
U4
U1
U2

DMI_MTX_IRX_P0
DMI_MRX_ITX_N0
DMI_MRX_ITX_P0

DMI_MTX_IRX_N1
DMI_MTX_IRX_P1
DMI_MRX_ITX_N1
DMI_MRX_ITX_P1

DMI_MTX_IRX_N2
DMI_MTX_IRX_P2
DMI_MRX_ITX_N2
DMI_MRX_ITX_P2

DMI_MTX_IRX_N3
DMI_MTX_IRX_P3
DMI_MRX_ITX_N3
DMI_MRX_ITX_P3

CLK_PCIE_ICH#
CLK_PCIE_ICH

CLK14

CLK48
SUSCLK
SLP_S3#

SLP_S4#
SLP_S5#

PWROK

BATLOW#
PWRBTN#
LAN_RST#

RSMRST#

CLPWROK

SLP_M#

CL_CLK0
CL_CLK1

CL_DATA0
CL_DATA1

CL_VREF0
CL_VREF1

CL_RST0#
CL_RST1#

DMI_IRCOMP
USBP0-

USBP0+
USBP1­USBP1+
USBP2­USBP2+
USBP3­USBP3+
USBP4­USBP4+
USBP5­USBP5+
USBP6­USBP6+
USBP7­USBP7+
USBP8­USBP8+
USBP9­USBP9+
USBP10­USBP10+
USBP11­USBP11+

R256 8.2K_0402_5%~DR256 8.2K_0402_5%~D

AH23

SPEAKER_DET#

AF19

USB_MCARD3_DET#

AE21

1394_DET#

AD20

CLK_ICH_14M

H1

CLK_ICH_48M

AF3

ICH_SUSCLK

P1

SIO_SLP_S3#

C16

SIO_SLP_S4#

E16

SIO_SLP_S5#

G17

ICH_GPIO26

C10

ICH_PWRGD

G20

DPRSLPVR

M2

ICH_BATLOW#

B13

SIO_PWRBTN#

R3

ICH_LAN_RST#

D20

ICH_RSMRST#

D22

CLK_PWRGD

R5

ICH_CL_PWROK

R6

SIO_SLP_M#

B16
F24

B19
F22

C19

+CL_VREF0_ICH

C25

+CL_VREF1_ICH

A19

CL_RST0#

F21

ICH_CL_RST1#

D18
A16

ME_SUS_PWR_ACK

C18

AC_PRESENT

C11

ME_WOL_EN

C20

1 2

R284

@R284

@

10K_0402_5%~D

10K_0402_5%~D

DMI_MTX_IRX_N0 <10>
DMI_MTX_IRX_P0 <10>
DMI_MRX_ITX_N0 <10>
DMI_MRX_ITX_P0 <10>

DMI_MTX_IRX_N1 <10>
DMI_MTX_IRX_P1 <10>
DMI_MRX_ITX_N1 <10>
DMI_MRX_ITX_P1 <10>

DMI_MTX_IRX_N2 <10>
DMI_MTX_IRX_P2 <10>
DMI_MRX_ITX_N2 <10>
DMI_MRX_ITX_P2 <10>

DMI_MTX_IRX_N3 <10>
DMI_MTX_IRX_P3 <10>
DMI_MRX_ITX_N3 <10>
DMI_MRX_ITX_P3 <10>

CLK_PCIE_ICH# <6>
CLK_PCIE_ICH <6>

USBP0- <33>
USBP0+ <33>
USBP1- <33>
USBP1+ <33>
USBP2- <33>
USBP2+ <33>
USBP3- <33>
USBP3+ <33>
USBP4- <34>
USBP4+ <34>
USBP5- <34>
USBP5+ <34>
USBP6- <34>
USBP6+ <34>
USBP7- <32>
USBP7+ <32>
USBP8- <35>
USBP8+ <35>
USBP9- <35>
USBP9+ <35>
USBP10- <36>
USBP10+ <36>
USBP11- <19>
USBP11+ <19>

2

R275 8.2K_0402_5%~D

R275 8.2K_0402_5%~D

+3.3V_ALW_ICH

R292 24.9_0402_1%~D

R292 24.9_0402_1%~D

----->Right Side Top

----->Right Side Bottom

----->Left Side Top

----->Left Side Bottom

----->WLAN

----->WWAN

----->WPAN

----->EXP Card

----->DOCK

----->DOCK

----->BIO

----->Camera

2

SPEAKER_DET# <28>

USB_MCARD3_DET# <34>
1394_DET# <31>

CLK_ICH_14M <6>
CLK_ICH_48M <6>

T44 PAD~DT44 PAD~D

SIO_SLP_S3# <37>
SIO_SLP_S4# <38>
SIO_SLP_S5# <38>

PAD~D

PAD~D

T130

T130

ICH_PWRGD <10,41>

DPRSLPVR <10,47>

12

SIO_PWRBTN# <38>
ICH_LAN_RST# <38>

ICH_RSMRST# <38>

CLK_PWRGD <6>

ICH_CL_PWROK <10,38>

SIO_SLP_M# <38>

CL_CLK0 <10>
ICH_CL_CLK1 <34>

CL_DATA0 <10>
ICH_CL_DATA1 <34>

CL_RST0# <10>

ICH_CL_RST1# <34>

PCIE_MCARD1_DET# <34>

ME_SUS_PWR_ACK <38>
AC_PRESENT <38>

ME_WOL_EN <38>

Within 500 mils

1 2

1

+3.3V_ALW_ICH

+1.5V_RUN_PCIE_ICH

ICH_SMBDATA

+3.3V_M

ICH_SMBCLK

+3.3V_ALW_ICH

ICH_LAN_RST#

+CL_VREF1_ICH

+3.3V_M

6 1

Q27A

Q27A
2N7002DW-T/R7_SOT363-6~D

2N7002DW-T/R7_SOT363-6~D

2
5

3

Q27B

Q27B
2N7002DW-T/R7_SOT363-6~D

2N7002DW-T/R7_SOT363-6~D

4

1394_DET#
ODD_DET#
HDD_DET#

ICH_CL_PWROK
DPRSLPVR
ICH_PWRGD
ICH_RSMRST#
ME_WOL_EN

@

@

1 2

1 2

1

2

2.2K_0402_5%~D

2.2K_0402_5%~D

12

1 2

R836 100K_0402_5%~DR836 100K_0402_5%~D
R760 100K_0402_5%~D

R760 100K_0402_5%~D

1 2

R759 100K_0402_5%~D

R759 100K_0402_5%~D

1 2

R250 100K_0402_5%~DR250 100K_0402_5%~D

1 2

R253 100K_0402_5%~D@R253 100K_0402_5%~D@

1 2

R257 10K_0402_5%~D

R257 10K_0402_5%~D

1 2

R260 10K_0402_5%~D R260 10K_0402_5%~D

1 2

R263 100K_0402_5%~D

R263 100K_0402_5%~D

Place closely pin U10.H1

10K_0402_5%~D

10K_0402_5%~D

10K_0402_5%~D

10K_0402_5%~D

R296

R296

CLK_ICH_14M

12

R271

R271

R276

R276

+3.3V_WLAN

C324

C324

R279

@ R279

@

10_0402_5%~D

10_0402_5%~D

1

C312

@C312

@

4.7P_0402_50V8C~D

4.7P_0402_50V8C~D

2

Place closely pin U10.AF3

CLK_ICH_48M

12

R285

@R285

@

10_0402_5%~D

10_0402_5%~D

1

C318

@C318

@

4.7P_0402_50V8C~D

4.7P_0402_50V8C~D

2

12

R286

R286

+CL_VREF0_ICH

3.24K_0402_1%~D

3.24K_0402_1%~D

12

R289

R289

453_0402_1%~D

453_0402_1%~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

2.2K_0402_5%~D

2.2K_0402_5%~D

12

R297

R297

MEM_SDATA

MEM_SCLK

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, MB A4042

SCHEMATIC, MB A4042

SCHEMATIC, MB A4042

401533

401533

401533

1

12

+3.3V_M

12

12

1

C325

C325

2

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

MEM_SDATA <16,17>

MEM_SCLK <16,17>

24 56Tuesday, December 18, 2007

24 56Tuesday, December 18, 2007

24 56Tuesday, December 18, 2007

of

of

of

+3.3V_RUN

R287

R287

3.24K_0402_1%~D

3.24K_0402_1%~D

R290

R290

453_0402_1%~D

453_0402_1%~D

A

A

A

5

+3.3V_RUN+5V_RUN

12

21

R311

R311

100_0402_5%~D

100_0402_5%~D

D D

D15

D15
RB751S40T1_SOD523-2~D

RB751S40T1_SOD523-2~D

1

C335

C335
1U_0603_10V6K~D

1U_0603_10V6K~D

2

+1.5V_RUN

L13

L13

1 2

BLM21PG600SN1D_0805~D

BLM21PG600SN1D_0805~D

+3.3V_ALW_ICH

+5V_ALW

12

21

R313

R313

100_0402_5%~D

100_0402_5%~D

C C

B B

A A

+1.5V_RUN

+3.3V_LAN

D16

D16
RB751S40T1_SOD523-2~D

RB751S40T1_SOD523-2~D

ICH_V5REF_SUS

1

C342

C342
1U_0603_10V6K~D

1U_0603_10V6K~D

2

+VCCGLANPLL_L

5

10UH_LB2012T100MR_20%_0805~D

10UH_LB2012T100MR_20%_0805~D

+VCCSATAPLLR

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

1

C367

C367

2

1 2

L17

L17
1UH_20%_0805~D

1UH_20%_0805~D

L16

L16

1 2

1

2

+RTC_CELL

1U_0603_10V4Z~D

1U_0603_10V4Z~D

1

C330

C330

2

+1.5V_RUN_PCIE_ICH

+1.5V_RUN_PCIE_ICH

220U_D2_4VY_R15M~D

220U_D2_4VY_R15M~D

1

+

+

2

1

2

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

1

C365

C365

2

+VCCGLANPLL+1.5V_RUN

2.2U_0603_6.3V6K~D

2.2U_0603_6.3V6K~D

10U_0805_4VAM~D

10U_0805_4VAM~D

1

C371

C371

C372

C372

2

1

2

C336

C336

+1.5V_RUN_SATAPLL

10U_0805_4VAM~D

10U_0805_4VAM~D

C370

C370

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

C350

C350

1 2

4

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

1

C332

C332

C331

C331

2

ICH_V5REF_RUN
ICH_V5REF_SUSICH_V5REF_RUN

22U_0805_6.3V6M~D

22U_0805_6.3V6M~D

1

2

+1.5V_RUN

1

2

4

2.2U_0603_6.3V6K~D

2.2U_0603_6.3V6K~D

1

C338

C338

C339

C339

2

1U_0603_10V4Z~D

1U_0603_10V4Z~D

1

C358

C358

2

1U_0603_10V4Z~D

1U_0603_10V4Z~D

1

C359

C359

2

VCCLAN1.05_INT_ICH

4.7U_0603_6.3V6M~D

4.7U_0603_6.3V6M~D

+3.3V_RUN

C373

C373

22U_0805_6.3V6M~D

22U_0805_6.3V6M~D

1

C337

C337

2

1U_0603_10V4Z~D

1U_0603_10V4Z~D

1

C351

C351

2

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

1

C364

C364

2

AA24
AA25
AB24
AB25
AC24
AC25
AD24
AD25
AE25
AE26
AE27
AE28
AE29

M24
M25

W24
W25

AJ19
AC16

AD15
AD16
AE15
AF15
AG15
AH15
AJ15

AC11
AD11
AE11
AF11
AG10
AG11
AH10
AJ10

AC9

AC18
AC19

AC21

AC12
AC13
AC14

AC6
AC7

A23

A6

AE1

F25
G25
H24
H25

J24

J25
K24
K25
L23
L24
L25

N23
N24
N25
P24
P25
R24
R25
R26
R27
T24
T27
T28
T29
U24
U25
V24
V25
U23

K23
Y24
Y25

G10

G9

AJ5
AA7

AB6
AB7

A10
A11

A12
B12

A27
D28

D29
E26
E27

A26

U10F

U10F

VCCRTC
V5REF
V5REF_SUS
VCC1_5_B[1]

VCC1_5_B[2]
VCC1_5_B[3]
VCC1_5_B[4]
VCC1_5_B[5]
VCC1_5_B[6]
VCC1_5_B[7]
VCC1_5_B[8]
VCC1_5_B[9]
VCC1_5_B[10]
VCC1_5_B[11]
VCC1_5_B[12]
VCC1_5_B[13]
VCC1_5_B[14]
VCC1_5_B[15]
VCC1_5_B[16]
VCC1_5_B[17]
VCC1_5_B[18]
VCC1_5_B[19]
VCC1_5_B[20]
VCC1_5_B[21]
VCC1_5_B[22]
VCC1_5_B[23]
VCC1_5_B[24]
VCC1_5_B[25]
VCC1_5_B[26]
VCC1_5_B[27]
VCC1_5_B[28]
VCC1_5_B[29]
VCC1_5_B[30]
VCC1_5_B[31]
VCC1_5_B[32]
VCC1_5_B[33]
VCC1_5_B[34]
VCC1_5_B[35]
VCC1_5_B[36]
VCC1_5_B[37]
VCC1_5_B[38]
VCC1_5_B[39]
VCC1_5_B[40]
VCC1_5_B[41]
VCC1_5_B[42]
VCC1_5_B[43]
VCC1_5_B[44]
VCC1_5_B[45]
VCC1_5_B[46]
VCC1_5_B[47]
VCC1_5_B[48]
VCC1_5_B[49]

VCCSATAPLL
VCC1_5_A[1]

VCC1_5_A[2]
VCC1_5_A[3]
VCC1_5_A[4]
VCC1_5_A[5]
VCC1_5_A[6]
VCC1_5_A[7]
VCC1_5_A[8]

VCC1_5_A[9]
VCC1_5_A[10]
VCC1_5_A[11]
VCC1_5_A[12]
VCC1_5_A[13]
VCC1_5_A[14]
VCC1_5_A[15]
VCC1_5_A[16]

VCC1_5_A[17]
VCC1_5_A[18]

VCC1_5_A[19]
VCC1_5_A[20]
VCC1_5_A[21]

VCC1_5_A[22]
VCC1_5_A[23]

VCC1_5_A[24]
VCC1_5_A[25]

VCCUSBPLL
VCC1_5_A[26]

VCC1_5_A[27]
VCC1_5_A[28]
VCC1_5_A[29]
VCC1_5_A[30]

VCCLAN1_05[1]
VCCLAN1_05[2]

VCCLAN3_3[1]
VCCLAN3_3[2]

VCCGLANPLL
VCCGLAN1_5[1]

VCCGLAN1_5[2]
VCCGLAN1_5[3]
VCCGLAN1_5[4]

VCCGLAN3_3

ICH9M REV 1.0

ICH9M REV 1.0

CORE

CORE

VCCA3GP ATXARX USB CORE

VCCA3GP ATXARX USB CORE

VCCPSUSVCCPUSB

VCCPSUSVCCPUSB

GLAN POWER

GLAN POWER

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

VCC1_05[1]
VCC1_05[2]
VCC1_05[3]
VCC1_05[4]
VCC1_05[5]
VCC1_05[6]
VCC1_05[7]
VCC1_05[8]

VCC1_05[9]
VCC1_05[10]
VCC1_05[11]
VCC1_05[12]
VCC1_05[13]
VCC1_05[14]
VCC1_05[15]
VCC1_05[16]
VCC1_05[17]
VCC1_05[18]
VCC1_05[19]
VCC1_05[20]
VCC1_05[21]
VCC1_05[22]
VCC1_05[23]
VCC1_05[24]
VCC1_05[25]
VCC1_05[26]

VCCDMIPLL

VCC_DMI[1]

VCC_DMI[2]
V_CPU_IO[1]

V_CPU_IO[2]

VCC3_3[1]
VCC3_3[2]

VCC3_3[7]

VCC3_3[3]
VCC3_3[4]
VCC3_3[5]
VCC3_3[6]

VCCP_CORE

VCCP_CORE

VCC3_3[8]

VCC3_3[9]

VCC3_3[10]
VCC3_3[11]
VCC3_3[12]
VCC3_3[13]

PCI

PCI

VCC3_3[14]

VCCHDA

VCCSUSHDA

VCCSUS1_05[1]
VCCSUS1_05[2]

VCCSUS1_5[1]
VCCSUS1_5[2]

VCCSUS3_3[1]
VCCSUS3_3[2]
VCCSUS3_3[3]
VCCSUS3_3[4]

VCCSUS3_3[5]
VCCSUS3_3[6]

VCCSUS3_3[7]
VCCSUS3_3[8]

VCCSUS3_3[9]
VCCSUS3_3[10]
VCCSUS3_3[11]
VCCSUS3_3[12]
VCCSUS3_3[13]
VCCSUS3_3[14]
VCCSUS3_3[15]
VCCSUS3_3[16]
VCCSUS3_3[17]
VCCSUS3_3[18]
VCCSUS3_3[19]
VCCSUS3_3[20]

VCCCL1_05

VCCCL1_5

VCCCL3_3[1]
VCCCL3_3[2]

3

3

+1.05V_VCCP

A15
B15
C15
D15
E15
F15
L11
L12
L14
L16
L17
L18
M11
M18
P11
P18
T11
T18
U11
U18
V11
V12
V14
V16
V17
V18

R29
W23

Y23
AB23

AC23
AG29
AJ6
AC10
AD19

AF20
AG24
AC20

B9
F9
G3
G6
J2
J7
K7

AJ4
AJ3
AC8

F17
AD8
F18

A18
D16
D17
E22

AF1
T1

T2
T3
T4
T5
T6
U6
U7
V6
V7
W6
W7
Y6
Y7
T7

G22
G23
A24

B24

+VCCDMIPLL
+VCC_DMI_ICH

+3.3V_RUN

C349

C349

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

1 2

+3.3V/1.5V_RUN_HDA

TP_VCCSUS1.05_INT_ICH1
TP_VCCSUS1.05_INT_ICH2

VCCSUS1_5_ICH_1
VCCSUS1_5_ICH_2

0.022U_0402_16V7K~D

0.022U_0402_16V7K~D

1

C361

C361

2

VCCCL1_05_ICH
VCCCL1_5

1 2

C366 0.1U_0402_16V4Z~D

C366 0.1U_0402_16V4Z~D

+3.3V_LAN

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

1

C333

C333

2

0.01U_0402_16V7K~D

0.01U_0402_16V7K~D

1

C340

C340

2

1

2

+3.3V_ALW_ICH

0.022U_0402_16V7K~D

0.022U_0402_16V7K~D

1

C362

C362

2

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

1

C334

C334

2

BLM18PG181SN1_0603~D

BLM18PG181SN1_0603~D

1 2

10U_0805_4VAM~D

10U_0805_4VAM~D

1

C341

C341

2

5ohm@100MHz

1 2

4.7U_0603_6.3V6M~D

4.7U_0603_6.3V6M~D
L15

L15
BLM18PG181SN1_0603~D

BLM18PG181SN1_0603~D

C343

C343

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

1

C348

C348

2

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

1

1

C353

C353

2

2

T91T91

+3.3V_ALW_ICH

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

1

C363

C363

2

1U_0603_10V4Z~D

1U_0603_10V4Z~D

1

C368

C368

2

L14

L14

+3.3V_RUN

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

C354

C354

T53

T53
T122

T122

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

1

2

+1.05V_VCCP

R312

R312
1_0603_1%~D

1_0603_1%~D

+3.3V_RUN

+3.3V_RUN

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

1

C355

C355

2

PAD~D

PAD~D
PAD~D

PAD~D

C369

C369

2

D14

D14

2

3

MMBD4148-7-F_SOT23-3~D

MMBD4148-7-F_SOT23-3~D

+1.5V_RUN

12

+1.05V_VCCP

1

2

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

+3.3V/1.5V_RUN_HDA

1

C347

C347

2

+3.3V_ALW_ICH

2

C357

C357

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

1

2

+1.05V_VCCP_D

1

+1.05V_VCCP

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

4.7U_0603_6.3V6M~D

4.7U_0603_6.3V6M~D

1

C344

C344

2

R314

R314
0_0603_5%~D

0_0603_5%~D

@R315

@

0_0603_5%~D

0_0603_5%~D

1

C352

C352

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

2

VCCSUS1_5_ICH_2

1 2

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

1

C345

C345

C346

C346

2

R315

Choice to support GMCH

1

U10E

U10E

AA26

+1.5V_RUN

R310

R310

10_0805_5%~D

10_0805_5%~D

12

+3.3V_RUN

12

+1.5V_RUN

1

C360

C360

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

2

AA27

AA23
AB28
AB29

AC17
AC26
AC27

AD10
AD12
AD13
AD14
AD17
AD18
AD21
AD28
AD29

AE12
AE13
AE14
AE16
AE17

AE20
AE24

AF13
AF16
AF18
AF22
AH26
AF26
AF27

AG13
AG16
AG18
AG20
AG23

AH12
AH14
AH17
AH19

AH22
AH25
AH28

AJ12
AJ14
AJ17

AA3
AA6
AB1

AB4
AB5

AC3
AD1

AD4
AD5
AD6
AD7
AD9

AE2

AE3
AE4
AE6
AE9

AF5
AF7
AF9

AG3
AG6
AG9

AH2

AH5
AH8

AJ8
B11
B14
B17

B2
B20
B23

B5

B8
C26
C27
E11
E14
E18

E2
E21
E24

E5

E8

F16
F28

F29
G12
G14
G18
G21
G24
G26
G27

G8

H2
H23
H28
H29

VSS[1]
VSS[2]
VSS[3]
VSS[4]
VSS[5]
VSS[6]
VSS[7]
VSS[8]
VSS[9]
VSS[10]
VSS[11]
VSS[12]
VSS[13]
VSS[14]
VSS[15]
VSS[16]
VSS[17]
VSS[18]
VSS[19]
VSS[20]
VSS[21]
VSS[22]
VSS[23]
VSS[24]
VSS[25]
VSS[26]
VSS[27]
VSS[28]
VSS[29]
VSS[30]
VSS[31]
VSS[32]
VSS[33]
VSS[34]
VSS[35]
VSS[36]
VSS[37]
VSS[38]
VSS[39]
VSS[40]
VSS[41]
VSS[42]
VSS[43]
VSS[44]
VSS[45]
VSS[46]
VSS[47]
VSS[48]
VSS[49]
VSS[50]
VSS[51]
VSS[52]
VSS[53]
VSS[54]
VSS[55]
VSS[56]
VSS[57]
VSS[58]
VSS[59]
VSS[60]
VSS[61]
VSS[62]
VSS[63]
VSS[64]
VSS[65]
VSS[66]
VSS[67]
VSS[68]
VSS[69]
VSS[70]
VSS[71]
VSS[72]
VSS[73]
VSS[74]
VSS[75]
VSS[76]
VSS[77]
VSS[78]
VSS[79]
VSS[80]
VSS[81]
VSS[82]
VSS[83]
VSS[84]
VSS[85]
VSS[86]
VSS[87]
VSS[88]
VSS[89]
VSS[90]
VSS[91]
VSS[92]
VSS[93]
VSS[94]
VSS[95]
VSS[96]
VSS[97]
VSS[98]
VSS[99]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]

ICH9M REV 1.0

ICH9M REV 1.0

VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
VSS[159]
VSS[160]
VSS[161]
VSS[162]
VSS[163]
VSS[164]
VSS[165]
VSS[166]
VSS[167]
VSS[168]
VSS[169]
VSS[170]
VSS[171]
VSS[172]
VSS[173]
VSS[174]
VSS[175]
VSS[176]
VSS[177]
VSS[178]
VSS[179]
VSS[180]
VSS[181]
VSS[182]
VSS[183]
VSS[184]
VSS[185]
VSS[186]
VSS[187]
VSS[188]
VSS[189]
VSS[190]
VSS[191]
VSS[192]
VSS[193]
VSS[194]
VSS[195]
VSS[196]
VSS[197]
VSS[198]

VSS_NCTF[1]
VSS_NCTF[2]
VSS_NCTF[3]
VSS_NCTF[4]
VSS_NCTF[5]
VSS_NCTF[6]
VSS_NCTF[7]
VSS_NCTF[8]

VSS_NCTF[9]
VSS_NCTF[10]
VSS_NCTF[11]
VSS_NCTF[12]

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, MB A4042

SCHEMATIC, MB A4042

SCHEMATIC, MB A4042

401533

401533

401533

1

H5
J23
J26
J27
AC22
K28
K29
L13
L15
L2
L26
L27
L5
L7
M12
M13
M14
M15
M16
M17
M23
M28
M29
N11
N12
N13
N14
N15
N16
N17
N18
N26
N27
P12
P13
P14
P15
P16
P17
P2
P23
P28
P29
P4
P7
R11
R12
R13
R14
R15
R16
R17
R18
R28
T12
T13
T14
T15
T16
T17
T23
B26
U12
U13
U14
U15
U16
U17
AD23
U26
U27
U3
V1
V13
V15
V23
V28
V29
V4
V5
W26
W27
W3
Y1
Y28
Y29
Y4
Y5
AG28
AH6
AF2
B25

A1
A2
A28
A29
AH1
AH29
AJ1
AJ2
AJ28
AJ29
B1
B29

A

A

25 56Tuesday, December 18, 2007

25 56Tuesday, December 18, 2007

25 56Tuesday, December 18, 2007

A

of

of

of

5

4

3

2

1

D D

+5VMOD Source

For ODD

JSATA1

JSATA1

1

GND

2

RX+

3

RX-

4

GND

5

TX-

6

TX+

7

GND

8

DP

9

+5V

10

+5V

11

MD

12

GND

13

GND

TYCO_1759920-3

TYCO_1759920-3

GND1
GND2

14
15

Main SATA +5V Default

For HDD

JSATA2

JSATA2

1

GND

2

RX+

3

RX-

4

GND

5

TX-

6

TX+

7

GND

8

3.3V

9

3.3V

10

3.3V

11

GND

12

GND

13

GND

14

5V

15

5V

16

5V

17

GND

18
19
20
21
22

GND1

Reserved

GND2

GND
12V
12V
12V

FOX_LD2122H-S4SL6_RV

FOX_LD2122H-S4SL6_RV

Main SATA +5V Default

MODC_EN<37>

R319

R319

100K_0402_5%~D

100K_0402_5%~D

100K_0402_5%~D

100K_0402_5%~D

23
24

HDDC_EN<37>

100K_0402_5%~D

100K_0402_5%~D

R323

R323

C374 0.01U_0402_16V7K~D C374 0.01U_0402_16V7K~D
C375 0.01U_0402_16V7K~D C375 0.01U_0402_16V7K~D

SATA_ODD_ITX_DRX_P1
SATA_ODD_ITX_DRX_N1

SATA_ODD_IRX_DTX_N1

12

SATA_ODD_IRX_DTX_P1

12

ODD_DET#<24>

+5V_MOD

ODD_DET#

+5V_MOD

1

2

SATA_ODD_ITX_DRX_P1<23>

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

1000P_0402_50V7K~D

1000P_0402_50V7K~D

1

C377

C377

C376

C376

2

SATA_ODD_ITX_DRX_N1<23>
SATA_ODD_IRX_DTX_N1_C<23>
SATA_ODD_IRX_DTX_P1_C<23>

close SATA connector

Pleace near ODD CONN

C C

PSATA_ITX_DRX_P0<23>
PSATA_ITX_DRX_N0<23>

PSATA_IRX_DTX_N0_C<23>
PSATA_IRX_DTX_P0_C<23>

+5V_HDD +3.3V_HDD

B B

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

1000P_0402_50V7K~D

1000P_0402_50V7K~D

1

1

C384

C384

2

2

C385

C385

10U_0805_10V4Z~D

10U_0805_10V4Z~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

@C386

@

@C387

C386

@

1

C387

2

1

2

PSATA_ITX_DRX_P0
PSATA_ITX_DRX_N0

C380 0.01U_0402_16V7K~D

C380 0.01U_0402_16V7K~D
C381 0.01U_0402_16V7K~D

C381 0.01U_0402_16V7K~D

close SATA connector

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

@C388

@

1

C388

2

12
12

HDD_DET#<24>

PSATA_IRX_DTX_N0
PSATA_IRX_DTX_P0

+3.3V_HDD

HDD_DET#

+5V_HDD

Pleace near HDD CONN

100K_0402_5%~D

100K_0402_5%~D

12

+3.3V_ALW2

R321

R321

2

12

+3.3V_ALW2

R317

R317

2

12

61

12

61

2N7002DW-T/R7_SOT363-6

2N7002DW-T/R7_SOT363-6

Q34A

Q34A

2N7002DW-T/R7_SOT363-6

2N7002DW-T/R7_SOT363-6

Q31A

Q31A

+15V_ALW

5

12

3

5

4

HDD PWR

12

R320

R320
100K_0402_5%~D

100K_0402_5%~D

HDD_EN_5V

2N7002DW-T/R7_SOT363-6

2N7002DW-T/R7_SOT363-6

3

Q34B

Q34B

4

R316

R316
100K_0402_5%~D

100K_0402_5%~D

2

MOD_EN

2N7002DW-T/R7_SOT363-6

2N7002DW-T/R7_SOT363-6

Q31B

Q31B

1

2

+5V_ALW

G

G

3

0.1U_0603_50V4Z~D

0.1U_0603_50V4Z~D

1

C382

C382

2

+3.3V_ALW

+5V_ALW+15V_ALW

6

2

1

D

D

Q29

Q29

G

G

SI3456BDV-T1-E3_TSOP6~D

SI3456BDV-T1-E3_TSOP6~D

3

S

S

+5V_MOD +5V_RUN

0.1U_0603_50V4Z~D

0.1U_0603_50V4Z~D

4 5

10U_0805_10V4Z~D

10U_0805_10V4Z~D

C378

C378

2

1

4 5

1

2

12

1

C379

C379

2

6

D

D

Q32

Q32
SI3456BDV-T1-E3_TSOP6~D

SI3456BDV-T1-E3_TSOP6~D

S

S

+5V_HDD

1 2

10U_0805_10V4Z~D

10U_0805_10V4Z~D

100K_0402_5%~D

100K_0402_5%~D

12

C383

C383

R322

R322

+5V_HDD Source

1 2

100K_0402_5%~D

100K_0402_5%~D

R318

R318

PJP25

PJP25

PAD-OPEN 4x4m@

PAD-OPEN 4x4m@

Open

PJP23

PJP23

PAD-OPEN 4x4m@

PAD-OPEN 4x4m@

+5V_RUN

6

2

1

D

D

Q131

@

Q131

@

G

G

SI3456BDV-T1-E3_TSOP6~D

SI3456BDV-T1-E3_TSOP6~D

3

S

S

+3.3V_HDD

4 5

10U_0805_10V4Z~D

10U_0805_10V4Z~D

100K_0402_5%~D

@ R974

100K_0402_5%~D

@

@ C1020

@

1

12

R974

C1020

2

A A

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD

5

4

PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

2

+3.3V_HDD Source

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, MB A4042

SCHEMATIC, MB A4042

SCHEMATIC, MB A4042

PJP42

PJP42

1 2

PAD-OPEN 4x4m@

PAD-OPEN 4x4m@

Short

401533

401533

401533

+3.3V_RUN

1

A

A

26 56Tuesday, December 18, 2007

26 56Tuesday, December 18, 2007

26 56Tuesday, December 18, 2007

A

of

of

of

2

1

1 2

R786 0_0402_5%~DR786 0_0402_5%~D

Y5

Y5

1 2

27P_0402_50V8J~D

27P_0402_50V8J~D

12MHZ_18PF_X5H012000FI1H~D

12MHZ_18PF_X5H012000FI1H~D

25

AVDD

38

AVDD

13

SENSE_A

34

SENSE_B

39
41
37

NC

21
22
28

23
24
29

35
36

14
15
31

16
17
30

GPIO3

18

NC

19

NC

20

NC

12

PC_BEEP

32

33

CAP2

27

VREFFILT

26

AVSS

42

AVSS

2N7002DW-T/R7_SOT363-6~D

2N7002DW-T/R7_SOT363-6~D

2

C994

C994

1

AUD_SENSE_A
AUD_SENSE_B

AUD_DOCK_MIC_IN_L
AUD_DOCK_MIC_IN_R

AUD_DOCK_HP_OUT_L AUD_DOCK_HP_L_C

AUD_PC_BEEP

CAP2

VREFFILT

12

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

1

1

C399

C399

2

2

AUD_HP_OUT_L <28>
AUD_HP_OUT_R <28>

AUD_EXT_MIC_L <33>
AUD_EXT_MIC_R <33>

+VREFOUT

C408 1U_0805_10V7K~D

C408 1U_0805_10V7K~D
C409 1U_0805_10V7K~D

C409 1U_0805_10V7K~D
C410 1U_0805_10V7K~D

C410 1U_0805_10V7K~D

C411 1U_0805_10V7K~D

C411 1U_0805_10V7K~D

1

1

C415

C415

C414

C414

2

2

10U_0805_10V6K~D

10U_0805_10V6K~D

AUD_SENSE_B

100K_0402_5%~D

100K_0402_5%~D

R353

R353

12

61

2

Q40A

Q40A

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

Q38A

Q38A

ICH_AZ_CODEC_BITCLK<23>

ICH_AZ_CODEC_SDOUT<23>

ICH_AZ_CODEC_SYNC<23>
ICH_AZ_CODEC_RST#<23>

DMIC_CLK<19>

12

61

2

1 2

R327 20K_0402_5%~D

R327 20K_0402_5%~D

1 2

R828 20K_0402_5%~D

R828 20K_0402_5%~D

1 2

R332 33_0402_5%~D

R332 33_0402_5%~D

1 2

R338 0_0402_5%~D

R338 0_0402_5%~D

AUD_EAPD<28>
SPDIF_OUT<51>

20K_0402_1%~D

20K_0402_1%~D

39.2K_0402_1%~D

39.2K_0402_1%~D

12

R349

R349

R348

R348

3

5

Q38B

Q38B

4

2N7002DW-T/R7_SOT363-6~D

2N7002DW-T/R7_SOT363-6~D

12

+3.3V_RUN

ICH_AZ_CODEC_BITCLK
ICH_AC_SDIN0_R
ICH_AZ_CODEC_SDOUT

DMIC_CLK_R

DMIC0<19>

R346

R346

5.11K_0402_1%~D

5.11K_0402_1%~D
1000P_0402_50V7K~D

1000P_0402_50V7K~D

1

C417

C417

2

AUD_PC_BEEP

TRACE>15 mil

R328

R328
10K_0402_5%~D

10K_0402_5%~D

U16

U16

1

DVDD_CORE

9

DVDD_CORE

40

NC/OTP

3

DVDD_IO

6

HDA_BITCLK

8

HDA_SDI_CODEC

5

HDA_SDO

10

HDA_SYNC

11

HDA_RST#

46

DMIC_CLK

2

DMIC0/VOL_UP/GPIO1

4

DMIC1/VOL_DN/GPIO2

47

SPDIF_OUT_0_1/EAPD/GPIO0

48

SPDIF_OUT_0

43

GPIO5

44

GPIO6

45

SPDIF_OUT_1/GPIO7

7

DVSS

49

Thermal PAD GND

92HD71B8X5NLGXA1X8_QFN48_7x7~D

92HD71B8X5NLGXA1X8_QFN48_7x7~D

+VDDA

12

+3.3V_RUN

12

R355

R355
100K_0402_5%~D

100K_0402_5%~D

AUD_MIC_SWITCH <33>AUD_HP_NB_SENSE<28,33,37>

92HD71B

92HD71B

PORT_A_L

PORT_A_R

PORT_B_L

PORT_B_R

VREFOUT_B

PORT_C_L

PORT_C_R

VREFOUT_C

PORT_D_L

PORT_D_R

PORT_E_L

PORT_E_R

GPIO4/VREFOUT_E

PORT_F_L

PORT_F_R

MONO_OUT

Place closely to Pin 34

SPKR<24>
BEEP<38>

+3.3V_RUN

1000P_0402_50V7K~D

1000P_0402_50V7K~D

10U_0805_10V6K~D

10U_0805_10V6K~D

1

1

C402

C402

2

2

B B

C389 0.1U_0402_16V4Z~D

C389 0.1U_0402_16V4Z~D
C394 0.1U_0402_16V4Z~D

C394 0.1U_0402_16V4Z~D

1U_0603_10V6K~D

1U_0603_10V6K~D

@C403

@

1

C404

C404

C403

2

1 2
1 2

1

2

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

C405

C405

Close to U16 pin1 & pin9

ICH_AZ_CODEC_SDIN0<23>

+3.3V_RUN

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

1

C407

C407

2

Close to U16 pin3

Close to U16 pin6

ICH_AZ_CODEC_BITCLK

12

R343

@R343

@

10_0402_5%~D

10_0402_5%~D

1

C412

@C412

@

10P_0402_50V8J~D

10P_0402_50V8J~D

2

Close to U16 pin5

ICH_AZ_CODEC_SDOUT

12

R344

@R344

@

47_0402_5%~D

47_0402_5%~D

1

C416

@C416

@

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

2

A A

Place closely to Pin 13.

AUD_SENSE_A

+3.3V_RUN

12

R350

R350
100K_0402_5%~D

100K_0402_5%~D

2N7002DW-T/R7_SOT363-6~D

2N7002DW-T/R7_SOT363-6~D

2

XTALO_12MHZ

XTALI_12MHZ

2

1

+VDDA

10U_0805_10V6K~D

10U_0805_10V6K~D

1U_0603_10V6K~D

1U_0603_10V6K~D

@C400

@

1

C400

C401

C401

2

AUD_LINE_OUT_L <28>
AUD_LINE_OUT_R <28>

12
12

12

AUD_DOCK_HP_R_C

12

1U_0603_10V6K~D

1U_0603_10V6K~D

39.2K_0402_1%~D

39.2K_0402_1%~D

20K_0402_1%~D

20K_0402_1%~D

12

R352

R352

R351

R351

+3.3V_RUN +3.3V_RUN

27P_0402_50V8J~D

27P_0402_50V8J~D

C995

C995

1

2

Select I2C & SPI
interface

AUD_DOCK_MIC_IN_L_C
AUD_DOCK_MIC_IN_R_C

R340

R340
0_0603_5%~D

0_0603_5%~D

1 2
1 2

R342

R342
0_0603_5%~D

0_0603_5%~D

R347

R347

5.11K_0402_1%~D

5.11K_0402_1%~D

12

1000P_0402_50V7K~D

1000P_0402_50V7K~D

1

C420

C420

2

3

5

Q40B

Q40B

4

2N7002DW-T/R7_SOT363-6~D

2N7002DW-T/R7_SOT363-6~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

0.1U_0402_16V7K~D

0.1U_0402_16V7K~D

2

C397

C397

1

+3.3V_RUN

1

C398

C398

2

12

R329

@R329

@

10K_0402_5%~D

10K_0402_5%~D

12

R331

R331
10K_0402_5%~D

10K_0402_5%~D

AUD_DOCK_HP_L_R
AUD_DOCK_HP_R_RAUD_DOCK_HP_OUT_R

Place close to U16

EN_I2S_NB_CODEC<37>

+VDDA

+3.3V_RUN+3.3V_RUN

12

R354

R354
100K_0402_5%~D

100K_0402_5%~D

DOCK_MIC_DET <37>DOCK_HP_DET<37>

+3.3V_RUN

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

C395

C395

+3.3V_RUN

2

1

L18

L18

BK1608LM182-T_0603~D

BK1608LM182-T_0603~D

12

0.1U_0402_16V7K~D

0.1U_0402_16V7K~D

1

2

C396

C396

T59PAD~D T59PAD~D
T60PAD~D T60PAD~D

1 2

R330

R330

10K_0402_5%~D

10K_0402_5%~D

+3.3V_RUN

I2S_BCLK
I2S_LRCLK
I2S_DO
I2S_12MHZ

R345

R345
1K_0402_5%~D

1K_0402_5%~D

+3.3V_RUN_I2S_VDD

0.1U_0402_16V7K~D

0.1U_0402_16V7K~D

0.1U_0402_16V7K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

C391

C391

AUD_DOCK_HP_L_R
AUD_DOCK_HP_R_R
DAI_SMBCLK

DAI_SMBDATA
XTALI_12MHZ

XTALO_12MHZ
NC_MICIN

NC_MICBIAS

@

@

DAI_SMBCLK

DAI_SMBDATA

For next version I2S.
will disconnect SMBUS
and PU.
Need check the PU
value.

2

1

+3.3V_RUN +3.3V_RUN

0.1U_0402_16V7K~D

0.1U_0402_16V7K~D

C418

C418

0.1U_0402_16V7K~D

2

2

C392

C392

C393

C393

1

1

+3.3V_RUN_I2S_AVDD
+3.3V_RUN_I2S_HPVDD

10K_0402_5%~D

10K_0402_5%~D

12

R333

R333

1

2

2.2K_0402_5%~D

2.2K_0402_5%~D

12

R334

R334

0.1U_0402_16V7K~D

0.1U_0402_16V7K~D

C413

C413

U17

U17

16

VCC

2

1A

4

2A

6

3A

10

4A

12

5A

14

6A

1

OE1#

15

12

OE2#

CD74HC366M96_SO16~D

CD74HC366M96_SO16~D

2

5

1

1

P

NC

4

A2Y

G

U18

U18

3

74LVC1G14GV_SOT753-5

74LVC1G14GV_SOT753-5

18
12

5
24
23
28

27

1

2
22

21
25
26
20

C406

C406
1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

2.2K_0402_5%~D

2.2K_0402_5%~D

12

R335

R335

+3.3V_RUN

3

1Y#

5

2Y#

7

3Y#

9

4Y#

11

5Y#

13

6Y#

8

GND

0.1U_0402_16V7K~D

0.1U_0402_16V7K~D

C419

C419

DELL CONFIDENTIAL/PROPRIETARY

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

1

Date: Sheet

U15

U15

SSM2602

SSM2602

DCVDD3DVSS
AVDD
HPVDD
DBVDD

LLINEIN
RLINEIN
SCLK

SDIN
MCLK/XTI

XTO/ POR
MICIN

MICBIAS
MODE
CSB
VMID

SSM2602_LFCSP28_5X5~D

SSM2602_LFCSP28_5X5~D

2

1

AVSS

HPVSS

LOUT
ROUT

LHPOUT

RHPOUT

CLKOUT

BCLK

DACDAT
ADCDAT

DACLRC
ADCLRC

Thermal Pad

+3.3V_RUN+3.3V_RUN

2

Q36A

Q36A

5

2N7002DW-T/R7_SOT363-6~D

2N7002DW-T/R7_SOT363-6~D

3

4

Q36B

Q36B
2N7002DW-T/R7_SOT363-6~D

2N7002DW-T/R7_SOT363-6~D

DA204U_SOT323-3~D

DA204U_SOT323-3~D

2

3

2

3

@D17

@

D17

1

1

I2S_DI#

+3.3V_RUN

@

@

5

1

P

NC

4

A2Y

G

U19

U19

3

74LVC1G14GV_SOT753-5

74LVC1G14GV_SOT753-5

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.
SCHEMATIC, MB A4042

SCHEMATIC, MB A4042

SCHEMATIC, MB A4042

401533

401533

401533

4
19
15

AUD_DOCK_MIC_IN_L_C

16

AUD_DOCK_MIC_IN_R_C

17

NC_LHPOUT

13

NC_RHPOUT

14

I2S_12MHZ

6

I2S_BCLK

7

I2S_DI#

8

I2S_DO

10

I2S_LRCLK

9

NC_ADCLRC

11
29

61

DA204U_SOT323-3~D

DA204U_SOT323-3~D

3

@D18

@

D18

1

2

3

1

T56 PAD~DT56 PAD~D
T57 PAD~DT57 PAD~D

T61PAD~DT61PAD~D

CKG_SMBCLK <6,38,48>

CKG_SMBDAT <6,38,48>

DA204U_SOT323-3~D

DA204U_SOT323-3~D

DA204U_SOT323-3~D

2

D20

D20
DA204U_SOT323-3~D

DA204U_SOT323-3~D

DA204U_SOT323-3~D

2

3

@D19

@

@D55

@

D19

D55

1

DAI_DI <35>

27 56Tuesday, December 18, 2007

27 56Tuesday, December 18, 2007

27 56Tuesday, December 18, 2007

DAI_BCLK# <35>
DAI_LRCK# <35>
DAI_DO# <35>
DAI_12MHZ# <35>

A

A

A

of

of

of

5

4

3

2

1

+5V_SPK_AMP

AUD_HP_NB_SENSE

AUD_NB_MUTE

74AHC1G08GW_SOT353-5~D

74AHC1G08GW_SOT353-5~D

AUD_HP_NB_SENSE<27,33,37>

D D

AUD_LINE_OUT_L<27>

AUD_LINE_OUT_R<27>

AUD_HP_OUT_L<27>

AUD_HP_OUT_R<27>

+5V_SPK_AMP

R364

R364

2

Q42A

Q42A

5

Q42B

Q42B

AUD_EAPD

1 2

61

3

4

12

to 2.2uF

R365

R365
100K_0402_5%~D

100K_0402_5%~D

1 2

1 2

1 2

C436

C436

2.2U_1206_25V7M~D

2.2U_1206_25V7M~D

1 2

C437

C437

2.2U_1206_25V7M~D

2.2U_1206_25V7M~D

AUD_EAPD<27>

C C

100K_0402_5%~D

B B

AUD_NB_MUTE<37>

100K_0402_5%~D

AUD_SPK_ENABLE#

AUD_EAPD<27>

2N7002DW-T/R7_SOT363-6~D

2N7002DW-T/R7_SOT363-6~D

2N7002DW-T/R7_SOT363-6~D

2N7002DW-T/R7_SOT363-6~D

C421

C421

1 2

5

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

1

P

IN1

O

2

IN2

G

U20

U20

3

+5V_SPK_AMP

C422

C422

1 2

5

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

1

P

IN1

O

2

IN2

G

U21

U21

3

74AHC1G08GW_SOT353-5~D

74AHC1G08GW_SOT353-5~D

C434

C434

0 .033U_0805_50V7K~D

0 .033U_0805_50V7K~D

C435

C435

0 .033U_0805_50V7K~D

0 .033U_0805_50V7K~D

1 2

R818 0_0402_5%~DR818 0_0402_5%~D

1 2

R827 0_0402_5%~DR827 0_0402_5%~D

R357

@ R357

@C439

@

C439

1

2

@

1 2

0_0402_5%~D

0_0402_5%~D

AUD_HP_EN

47P_0402_50V8J~D

47P_0402_50V8J~D

47P_0402_50V8J~D

47P_0402_50V8J~D

@C440

@

1

C440

2

+5V_SPK_AMP

1 2

R368 0_0402_5%~D R368 0_0402_5%~D

See Note 2

47P_0402_50V8J~D

47P_0402_50V8J~D

@C441

@

@C442

@

1

C441

C442

2

1

2

+5V_SPK_AMP

12

L19

L19

BLM21PG600SN1D_0805~D

BLM21PG600SN1D_0805~D

CPVSS13HPVSS

1 2

+5V_SPK_AMP

8

18

30

VDD

SPVDD

SPVDD

ROUT+

HP_OUTL

HP_OUTR

SPKR_LIN-

REG_OUT

SPKR_RIN-

SPGND21SPGND

SGND

TP

5

28

33

Place Close to Audio Chip Place Close to Audio Chip

1U_0603_10V6K~D

1U_0603_10V6K~D

0.1U_0402_10V7K~D

2

1

C428

C428

1

2

C1P
C1N

C446

C446

12

C450

C450

1U_0603_10V6K~D

1U_0603_10V6K~D

0.1U_0402_10V7K~D

3

2

27

26

24

23
22
25

17

9

10
12
11

+CPVSS

C429

C429

U22

U22

SPKR_LIN+

SPKR_RIN+

HP_INL

HP_INR

BYPASS

/SPKR_EN
HP_EN
REG_EN

HPVDD

CPVDD

C1P
C1N
CPGND

8mil

14

1 2

C438 1U_0603_10V6K~D C438 1U_0603_10V6K~D

10U_0805_10V6K~D

10U_0805_10V6K~D

1U_0603_10V6K~D

1U_0603_10V6K~D

2

C444

C444

C445

C445

1

R363

R363

R367

R367
100K_0402_5%~D

100K_0402_5%~D

@

@

AUD_AMP_MUTE#

1U_0603_10V6K~D

1U_0603_10V6K~D

2

C427

C427

1

SPKR_INL_C

SPKR_INR_C

HP_INL_C

HP_INR_C

AUD_SPK_ENABLE#
AUD_HP_EN
AUD_AMP_MUTE#

1U_0603_10V6K~D

1U_0603_10V6K~D

12

2

1

1M_0402_1%~D

1M_0402_1%~D

TPA6040A4RHBR_QFN32_5X5~D

TPA6040A4RHBR_QFN32_5X5~D

LOUT+

LOUT-

ROUT-

GAIN0
GAIN1

+5V_RUN

2

1

6

7

20

19

16

15

31
32

4

29

1

See Note 2

W=40mils

1U_0603_10V6K~D

1U_0603_10V6K~D

10U_0805_10V6K~D

10U_0805_10V6K~D

1

C430

C430

2

INT_SPK_L1

INT_SPK_L2

INT_SPK_R1

INT_SPK_R2

HP_SPK_L1

HP_SPK_R1

AUD_GAIN1
AUD_GAIN2

R362 0_0402_5%~D@ R362 0_0402_5%~D@

1 2

1 2

0.033U_0402_16V7K~D

0.033U_0402_16V7K~D

SET

0_0402_5%~D

0_0402_5%~D

12

2

R366

R366

1

@

@

C431

C431

C443

C443

0.033U_0402_16V7K~D

0.033U_0402_16V7K~D

C449

C449

+5V_SPK_AMP

1U_0603_10V6K~D

1U_0603_10V6K~D

2

C432

C432

1

HP_SPK_L1 <33>

HP_SPK_R1 <33>

2

1

SPEAKER_DET#<24>

10U_0805_10V6K~D

10U_0805_10V6K~D

1

C433

C433

2

See Note 2

1U_0603_10V6K~D

1U_0603_10V6K~D

1U_0603_10V6K~D

1U_0603_10V6K~D

2

C447

C447

1

15 mils trace

INT_SPK_R1
INT_SPK_R2
INT_SPK_L1
INT_SPK_L2

RUN_ON <19,37,40,41,50>

+VDDA

MINIMAM 150 mA

C448

C448

Speaker Connector

100P_0402_50V8J~D

100P_0402_50V8J~D

100P_0402_50V8J~D

100P_0402_50V8J~D

@C424

@

@C423

@

1

1

C424

C423

2

2

100P_0402_50V8J~D

100P_0402_50V8J~D

@C425

@

1

C425

2

See Note 1

100P_0402_50V8J~D

100P_0402_50V8J~D

@C426

@

1

C426

2

Gain Setting

+5V_SPK_AMP

100K_0402_5%~D

100K_0402_5%~D

12

AUD_GAIN1
AUD_GAIN2

100K_0402_5%~D

100K_0402_5%~D

12

R358

R358

@R360

@

R360

100K_0402_5%~D

100K_0402_5%~D

@R359

@

12

R359

100K_0402_5%~D

100K_0402_5%~D

12

R361

R361

JSPK1

JSPK1

1

1

2

2

3

3

4

4

5

5

6

6

7

GND

8

GND

MOLEX_53780-0670~D

MOLEX_53780-0670~D

See Note 1

GAIN1 INPUTAV(inv)GAIN2

0

0

1

*

*

TPA6040
9789A

6dB

0

1

10dB

15.6dB

0

21.6dB

11

R362 R366 R367 R368

@@

IMPEDANCE

C443 C449

@@

82K ohm

66K ohm

45K ohm

26K ohm

@

@

4

4

47P_0402_50V8J~D

47P_0402_50V8J~D

1

2

RUN_ON

A A

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

Date: Sheet

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.
SCHEMATIC, MB A4042

SCHEMATIC, MB A4042

SCHEMATIC, MB A4042

401533

401533

401533

28 56Tuesday, December 18, 2007

28 56Tuesday, December 18, 2007

28 56Tuesday, December 18, 2007

1

A

A

A

of

of

of

5

4

3

2

1

D D

Layout Notice : Place as close

10U_0805_10V4Z~D

10U_0805_10V4Z~D

2

C455

C455

1

+1.8V_LAN_M

10U_0805_10V4Z~D

10U_0805_10V4Z~D

1

2

chip as possible.

4.7U_0603_6.3V4Z~D

4.7U_0603_6.3V4Z~D

4.7U_0603_6.3V4Z~D

4.7U_0603_6.3V4Z~D

2

C457

C457

C456

C456

1

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

2

C467

C467

C468

C468

1

2

1

2

1

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

+3.3V_LAN

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

C458

C458

2

C469

C469

1

2

1

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

C470

C470

C459

C459

470P_0402_50V7K~D

470P_0402_50V7K~D

4.7U_0603_6.3V4Z~D

4.7U_0603_6.3V4Z~D

2

C471

C471

1

470P_0402_50V7K~D

470P_0402_50V7K~D

1

1

C472

C472

C473

C473

2

2

PCIE_IRX_GLANTX_P6_C

PCIE_IRX_GLANTX_P6<24>

PCIE_IRX_GLANTX_N6<24>

PCIE_ITX_GLANRX_P6_C<24>

PCIE_ITX_GLANRX_N6_C<24>

LAN_CLK<23>

LAN_RSTSYNC<23>

LAN_TX0<23>
LAN_TX1<23>
LAN_TX2<23>

LAN_RX0<23>
LAN_RX1<23>
LAN_RX2<23>

C C

B B

LOM_ACTLED_YEL#<30>

LOM_SPD100LED_ORG#<30>

LOM_SPD10LED_GRN#<30>

R373 0_0402_5%~D@R373 0_0402_5%~D@

LAN_PHY_PWR_CNTRL<24,37>

R376 1K_0402_5%~DR376 1K_0402_5%~D

1 2

R379 0_0402_5%~DR379 0_0402_5%~D

1 2

27P_0402_50V8J~D

27P_0402_50V8J~D

2

C475

C475

1

Y2

Y2

25MHZ_18PF_1BX25000CK1D~D

25MHZ_18PF_1BX25000CK1D~D

Need to ensure
crystal at least
300uW max power
drive-level

12

C451 0.1U_0402_10V7K~DC451 0.1U_0402_10V7K~D

PCIE_IRX_GLANTX_N6_C

12

C452 0.1U_0402_10V7K~DC452 0.1U_0402_10V7K~D

1 2

R369 33_0402_5%~DR369 33_0402_5%~D

R372 4.99K_0402_1%~D

R372 4.99K_0402_1%~D

1 2

12

1 2

R1004 0_0402_5%~DR1004 0_0402_5%~D

1 2

R378 10K_0402_5%~D R378 10K_0402_5%~D

12

LAN_TEST_P
LAN_TEST_N

XTALO
XTALI

27P_0402_50V8J~D

27P_0402_50V8J~D

2

C476

C476

1

XTALO

XTALI

U23

U23

52

GLAN_TXP

53

GLAN_TXN

55

GLAN_RXP

56

GLAN_RXN

45

JKCLK

50

JRSTSYNC

42

JTXD_0

43

JTXD_1

44

JTXD_2

47

JRXD_0

48

JRXD_1

49

JRXD_2

4

LED_0

2

LED_1

1

LED_2

15

RSET

12

IEEE_TEST_P

13

IEEE_TEST_N

34

DIS_REG10

37

LAN_DISABLE_N

36

TEST_EN

9

XTAL2

10

XTAL1

MA use internal 1V,NOT external solutions.
82567LM:
B0 version: 1.05V
A1 version: 1V

VDDO_33_46

DVDD_10_33
DVDD_10_38

RESERVED_NC

JTAG_TMS39JTAG_TCK40JTAG_TRST35JTAG_TDI7JTAG_TDO

82567LM_QFN56~D

82567LM_QFN56~D

6

JTAG_TDO_LAN
JTAG_TDI_LAN
JTAG_TMS_LAN
JTAG_TCK_LAN
JTAG_TRST_LAN

MDI_N_0
MDI_P_0

MDI_N_1
MDI_P_1

MDI_N_2
MDI_P_2

MDI_N_3
MDI_P_3

VDDO_33_3

AVDD_33_28

DVDD_10_5
DVDD_10_8

AVDD_18_11
AVDD_18_14
AVDD_18_19
AVDD_18_18
AVDD_18_24
AVDD_18_25
AVDD_18_41
AVDD_18_54
AVDD_18_32
AVDD_18_30

CTRL18
CTRL10

GND_PAD

26
27

22
23

20
21

16
17

3
46
28

5
8
33
38

11
14
19
18
24
25
41
54
32
30

29
31

51

57

LAN_TX0­LAN_TX0+

LAN_TX1­LAN_TX1+

LAN_TX2­LAN_TX2+LAN_CLK_R

LAN_TX3­LAN_TX3+

T155 PAD~DT155 PAD~D
T156 PAD~DT156 PAD~D
T157 PAD~DT157 PAD~D
T158 PAD~DT158 PAD~D
T159 PAD~DT159 PAD~D

LAN_TX0- <30>
LAN_TX0+ <30>

LAN_TX1- <30>
LAN_TX1+ <30>

LAN_TX2- <30>
LAN_TX2+ <30>

LAN_TX3- <30>
LAN_TX3+ <30>

+1V_LAN_M

+1.8V_LAN_M

REGCTL_PNP18

2

1

+3.3V_LAN

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

C463

C463

+3.3V_ALW

4.7U_0603_6.3V4Z~D

4.7U_0603_6.3V4Z~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

2

2

C453

C453

C454

C454

1

1

4.7U_0603_6.3V4Z~D

4.7U_0603_6.3V4Z~D

2

C464

C464

1

R374

R374

5.1K_0402_5%~D

5.1K_0402_5%~D

+1V_LAN_M

1

2

4.7U_0805_10V4Z~D

4.7U_0805_10V4Z~D

C477

C477

Trace=12mil

4.7U_0805_10V4Z~D

4.7U_0805_10V4Z~D

1

2

C478

C478

2

1

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

C479

C479

2

1

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

C1024

C1024

REGCTL_PNP18

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

2

C1025

C1025

1

ENAB_3VLAN<40>

Q44

Q44
STS11NF30L_SO8~D

STS11NF30L_SO8~D

8
7

5

+3.3V_LAN

12

R370

R370

2_1210_5%~D

2_1210_5%~D

12

1

4

12

R371

R371

2_1210_5%~D

2_1210_5%~D

Trace=12mil

+3.3V_LAN_R

3

Q45

Q45
BCP69_SOT223~D

BCP69_SOT223~D

2

4

1
2
36

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

1

2

1

C465

C465

2

+1.8V_LAN_M

1

2

10U_0805_10V4Z~D

10U_0805_10V4Z~D

10U_0805_10V4Z~D

10U_0805_10V4Z~D

C466

C466

C474

C474

1

2

Follow 82567 schematic
chiplist that VCC_1.0 for
external use 10uF XR5 *2 and

0.1uF *2
for internal use 4.7uF X5R *2
and 0.1uF *3

A A

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, MB A4042

SCHEMATIC, MB A4042

SCHEMATIC, MB A4042

401533

401533

401533

29 56Tuesday, December 18, 2007

29 56Tuesday, December 18, 2007

29 56Tuesday, December 18, 2007

1

of

of

of

A

A

A

5

4

3

2

1

D D

LAN_TX0-<29>
LAN_TX0+<29>

LAN_TX1-<29>
LAN_TX1+<29>

LAN_TX2-<29>

C C

B B

LAN_TX2+<29>

LAN_TX3-<29>
LAN_TX3+<29>

DOCKED<37>

Layout Notice : Place bead as
close PI3L500 as possible

+3.3V_LAN

1 2

L20 36NH_0603CS-360EJTS_5%_0603~D

L20 36NH_0603CS-360EJTS_5%_0603~D

LAN_TX0+

1 2

L21 36NH_0603CS-360EJTS_5%_0603~D

L21 36NH_0603CS-360EJTS_5%_0603~D

LAN_TX1-

LAN_TX2­LAN_TX2+

LAN_TX3­LAN_TX3+

DOCKED

1 2

L22 36NH_0603CS-360EJTS_5%_0603~D

L22 36NH_0603CS-360EJTS_5%_0603~D

1 2

L23 36NH_0603CS-360EJTS_5%_0603~D

L23 36NH_0603CS-360EJTS_5%_0603~D

1 2

L24 36NH_0603CS-360EJTS_5%_0603~D

L24 36NH_0603CS-360EJTS_5%_0603~D

1 2

L25 36NH_0603CS-360EJTS_5%_0603~D

L25 36NH_0603CS-360EJTS_5%_0603~D

1 2

L26 36NH_0603CS-360EJTS_5%_0603~D

L26 36NH_0603CS-360EJTS_5%_0603~D

1 2

L27 36NH_0603CS-360EJTS_5%_0603~D

L27 36NH_0603CS-360EJTS_5%_0603~D

LOM_ACTLED_YEL#<29>
LOM_SPD10LED_GRN#<29>
LOM_SPD100LED_ORG#<29>

FROM NIC DOCKED

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

2

C461

C461

1

LAN_TX0-RLAN_TX0­LAN_TX0+R

LAN_TX1-R
LAN_TX1+RLAN_TX1+

LAN_TX2-R
LAN_TX2+R

LAN_TX3-R
LAN_TX3+R

1: TO DOCK
0: TO RJ45

0.1U_0402_16V4Z~D

2

C462

C462

1

56

U25

U25

2

A0

3

A1

7

A2

8

A3

11

A4

12

A5

14

A6

15

A7

17

SEL

19

LED0

20

LED1

54

LED2

5

NC

57

PAD_GND

GND01GND16GND29GND313GND416GND521GND624GND728GND833GND939GND1044GND1149GND1253GND13

+3.3V_LAN

10K_0402_5%~D

10K_0402_5%~D

10K_0402_5%~D

10K_0402_5%~D

10K_0402_5%~D

12

@R392

@

R392

10K_0402_5%~D

12

12

@R393

@

@R394

@

R393

R394

LAN ANALOG
SWITCH

0B1

VDD04VDD110VDD218VDD327VDD438VDD550VDD6

1B1
2B1

3B1
4B1

5B1
6B1

7B1

0LED1
1LED1
2LED1

0B2
1B2

2B2
3B2

4B2
5B2

6B2
7B2

0LED2
1LED2
2LED2

PI3L500-AZFEX_TQFN56~D

PI3L500-AZFEX_TQFN56~D

55

48
47

43
42

37
36

32
31

22
23
52

46
45

41
40

35
34

30
29

25
26
51

SW_LAN_TX0­SW_LAN_TX0+

SW_LAN_TX1­SW_LAN_TX1+

SW_LAN_TX2­SW_LAN_TX2+

SW_LAN_TX3­SW_LAN_TX3+

LAN_LEDACT#
LINK_LED10#
LINK_LED100#

DOCK_LOM_TRD0­DOCK_LOM_TRD0+

DOCK_LOM_TRD1­DOCK_LOM_TRD1+

DOCK_LOM_TRD2­DOCK_LOM_TRD2+

DOCK_LOM_TRD3­DOCK_LOM_TRD3+

DOCK_LOM_ACTLED_YEL#
DOCK_LOM_SPD10LED_GRN#
DOCK_LOM_SPD100LED_ORG#

SW_LAN_TX0- <33>
SW_LAN_TX0+ <33>

SW_LAN_TX1- <33>
SW_LAN_TX1+ <33>

SW_LAN_TX2- <33>
SW_LAN_TX2+ <33>

SW_LAN_TX3- <33>
SW_LAN_TX3+ <33>

DOCK_LOM_TRD0- <35>
DOCK_LOM_TRD0+ <35>

DOCK_LOM_TRD1- <35>
DOCK_LOM_TRD1+ <35>

DOCK_LOM_TRD2- <35>
DOCK_LOM_TRD2+ <35>

DOCK_LOM_TRD3- <35>
DOCK_LOM_TRD3+ <35>

DOCK_LOM_ACTLED_YEL# <35>
DOCK_LOM_SPD10LED_GRN# <35>
DOCK_LOM_SPD100LED_ORG# <35>

TO
DOCK

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

2

C460

C460

1

C488 0.1U_0402_16V4Z~D@C488 0.1U_0402_16V4Z~D@

1 2

C489 0.1U_0402_16V4Z~D@C489 0.1U_0402_16V4Z~D@

1 2

C490 0.1U_0402_16V4Z~D@C490 0.1U_0402_16V4Z~D@

1 2

C491 0.1U_0402_16V4Z~D@C491 0.1U_0402_16V4Z~D@

1 2

A A

R384 49.9_0402_1%~D@R384 49.9_0402_1%~D@

1 2

R385 49.9_0402_1%~D@R385 49.9_0402_1%~D@

1 2

R386 49.9_0402_1%~D@ R386 49.9_0402_1%~D@

1 2

R387 49.9_0402_1%~D@R387 49.9_0402_1%~D@

1 2

R388 49.9_0402_1%~D@R388 49.9_0402_1%~D@

1 2

R389 49.9_0402_1%~D@R389 49.9_0402_1%~D@

1 2

R390 49.9_0402_1%~D@R390 49.9_0402_1%~D@

1 2

R391 49.9_0402_1%~D@R391 49.9_0402_1%~D@

1 2

Layout Notice : Place
termination as close as
ASIC as possible

The resistors need at
least 1/16W

5

4

LAN_TX0­LAN_TX0+
LAN_TX1­LAN_TX1+
LAN_TX2­LAN_TX2+
LAN_TX3­LAN_TX3+

LOM_ACTLED_YEL#
LOM_SPD10LED_GRN#
LOM_SPD100LED_ORG#

LAN_LEDACT# LAN_ACTLED_YEL_R#
LINK_LED10#
LINK_LED100#

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

1 2

R395 150_0402_5%~D

R395 150_0402_5%~D

1 2

R396 110_0402_5%~D

R396 110_0402_5%~D

1 2

R397 200_0402_5%~D

R397 200_0402_5%~D

LED_10_GRN_R#
LED_100_ORG_R#

LAN_ACTLED_YEL_R# <33>

LED_10_GRN_R# <33>

LED_100_ORG_R# <33>

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.
SCHEMATIC, MB A4042

SCHEMATIC, MB A4042

SCHEMATIC, MB A4042

401533

401533

401533

30 56Tuesday, December 18, 2007

30 56Tuesday, December 18, 2007

30 56Tuesday, December 18, 2007

1

A

A

A

of

of

of

5

U26A

U26A

R5C847-CSP208Q

PCI_AD[0..31]<22>

+3.3V_RUN

D D

C C

B B

1 2

R400 10K_0402_5%~D

R400 10K_0402_5%~D

1 2

R402 100K_0402_5%~D

R402 100K_0402_5%~D

1 2

R405 10K_0402_5%~D

R405 10K_0402_5%~D

+3.3V_RUN_PHY

1 2

R404 0_0402_5%~DR404 0_0402_5%~D

1 2

R406 10K_0402_5%~D

R406 10K_0402_5%~D

0.01U_0402_16V7K~D

0.01U_0402_16V7K~D
10K_0402_1%~D

10K_0402_1%~D

C513

C513

2

1

1 2

R417

R417

CB_HWSPND#
CBS_SPK
UDIO3

CPS
UDIO4

PCI_PAR<22>

PCI_C_BE0#<22>
PCI_C_BE1#<22>
PCI_C_BE2#<22>

PCI_AD17 CBS_IDSEL

PCI_C_BE3#<22>

1 2

R409 100_0402_5%~D

R409 100_0402_5%~D

PCI_REQ1#<22>

PCI_GNT1#<22>
PCI_FRAME#<22>
PCI_IRDY#<22>
PCI_TRDY#<22>
PCI_DEVSEL#<22>
PCI_STOP#<22>

PCI_PERR#<22>

PCI_SERR#<22>

PCI_RST#<22,35>

CLK_PCI_PCM<6>

CLKRUN#<24,37,38>

CB_HWSPND#<37>

PCI_PIRQD#<22>
PCI_PIRQB#<22>
PCI_PIRQC#<22>

IRQ_SERIRQ<24,36,37,38>

PCI_AD0
PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD6
PCI_AD7
PCI_AD8
PCI_AD9
PCI_AD10
PCI_AD11
PCI_AD12
PCI_AD13
PCI_AD14
PCI_AD15
PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20
PCI_AD21
PCI_AD22
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30
PCI_AD31

PCI_PAR
PCI_C_BE0#
PCI_C_BE1#
PCI_C_BE2#
PCI_C_BE3#

PCI_REQ1#
PCI_GNT1#
PCI_FRAME#
PCI_IRDY#
PCI_TRDY#
PCI_DEVSEL#
PCI_STOP#
PCI_PERR#
PCI_SERR#

CBUS_GRST#
PCI_RST#
CLK_PCI_PCM
CLKRUN#
CB_HWSPND#

UDIO3
UDIO4

CBS_SPK
TPAP0

TPAN0
TPBP0
TPBN0
TPBIAS0
CPS
CBVREF
CBREXT
R5C847XI
R5C847XO

close to U26

CLK_PCI_PCM

@

@

10_0402_5%~D

10_0402_5%~D

12

R418

R418

A A

@

@

4.7P_0402_50V8C~D

4.7P_0402_50V8C~D

PCI_CBS_TERM

2

C517

C517

1

+3.3V_RUN

100K_0402_5%~D

100K_0402_5%~D

12

1U_0603_10V4Z~D

1U_0603_10V4Z~D

1

2

5

R420

R420

CBUS_GRST#

C516

C516

R5C847-CSP208Q

W12

AD0

V12

AD1

T12

AD2

W11

AD3

V11

AD4

T11

AD5

W9

AD6

V9

AD7

R9

AD8

W8

AD9

V8

AD10

T8

AD11

R8

AD12

W7

AD13

V7

AD14

T7

AD15

V1

AD16

U1

AD17

U2

AD18

T1

AD19

T2

AD20

R1

AD21

R2

AD22

R4

AD23

P4

AD24

P5

AD25

N1

AD26

N2

AD27

N4

AD28

N5

AD29

M1

AD30

M2

AD31

V6

PAR

T9

C/BE0#

W6

C/BE1#

W2

C/BE2#

P2

C/BE3#

P1

IDSEL

M4

REQ#

M5

GNT#

V3

FRAME#

V4

IRDY#

W4

TRDY#

T5

DEVSEL#

V5

STOP#

W5

PERR#

T6

SERR#

G2

GBRST#

L4

PCIRST#

K1

PCICLK

L5

CLKRUN#

F2

HWSPND#

J2

INTA#

K4

INTB#

K2

INTC#

J4

UDIO0/SRIRQ#

H1

UDIO1

H2

UDIO2

H4

UDIO3

H5

UDIO4

G1

UDIO5

G4

RI_OUT#/PME#

F1

SPKROUT#

B12

TPAP0

A12

TPAN0

B13

TPBP0

A13

TPBN0

D12

TPBIAS0

D11

CPS

D13

VREF

B14

REXT

A16

XI

B16

XO

A14

FIL0

W14

USBDM

V14

USBDP

F4

TEST1

R7

TEST2

R5C847-CSP208Q_CSP208~D

R5C847-CSP208Q_CSP208~D

VPPEN0
SDCLK/MMCCLK

12

C514

C514
18P_0402_50V8J~D

18P_0402_50V8J~D

12

C515

C515
18P_0402_50V8J~D

18P_0402_50V8J~D

4

CDATA10/CAD31

CDATA9/CAD30
CDATA1/CAD29
CDATA8/CAD28
CDATA0/CAD27

CADR0/CAD26
CADR1/CAD25
CADR2/CAD24
CADR3/CAD23
CADR4/CAD22
CADR5/CAD21
CADR6/CAD20

CADR25/CAD19

CADR7/CAD18
CADR24/CAD17
CADR17/CAD16

IOWR#/CAD15

CADR9/CAD14

IORD#/CAD13

CADR11/CAD12

PCI I/F

PCI I/F

OE#/CAD11

CE2#/CAD10

CADR10/CAD9
CDATA15/CAD8

CDATA7/CAD7
CDATA13/CAD6

CDATA6/CAD5
CDATA12/CAD4

CDATA5/CAD3
CDATA11/CAD2

CDATA4/CAD1

CDATA3/CAD0

REG#/CCBE3#

CADR12/CCBE2#

CADR8/CCBE1#

CE1#/CCBE0#

CADR13/CPAR

CADR23/CFRAME#

CADR22/CTRDY#

CADR15/CIRDY#

CADR20/CSTOP#

CADR21/CDEVSEL#

CADR19

CADR14/CPERR#

WAIT#/CSERR#

16 bit PC card I/F

16 bit PC card I/F

INPACK#/CREQ#

WE#/CGNT#

BVD1/CSTSCHG

WP/CCLKRUN#

RST&

CLK

RST&

CLK

AUDIO

AUDIO

R411 100K_0402_5%~D R411 100K_0402_5%~D
R412 100K_0402_5%~D@R412 100K_0402_5%~D@

1 2

R421 0_0402_5%~DR421 0_0402_5%~D

CADR16/CCLK

READY/CINT#

RESET/CRST#

BVD2/CAUDIO

CD1#/CCD1#
CD2#/CCD2#

INT &

INT &

1394 I/F

1394 I/F

USB TEST

USB TEST

1 2
1 2

X3

X3

24.576MHz_16P_1BG24576CKIA~D

24.576MHz_16P_1BG24576CKIA~D

VS1#/CVS1
VS2#/CVS2

CDATA14

CDATA2
CADR18
VPPEN0

VPPEN1
VCC5EN#
VCC3EN#

MDIO00

MDIO01

MDIO02

MDIO03

MDIO04

MDIO05

MDIO06

MDIO07

MDIO08

MDIO09

MDIO10

MDIO11

MDIO12

MDIO13

MDIO14

MDIO15

MDIO16

MDIO17

MDIO18

Media Card I/F

Media Card I/F

MDIO19

R5C847XI

R5C847XO

12

Close to Pin A16,B16

4

B19
C18
D19
D18
E19
E16
F18
F15
G18
G15
H18
H15
J18
J16
J15
P16
P19
R19
P18
R18
T19
T18
U19
U18
W17
V17
W16
V16
W15
V15
T15
R14

F16
K18
P15
V19
N15
K16
L16
K15
M16
L18
N19
N18
G16
G19
M15
E18
A18
L19
M18
H19
F19

T14
D15
R16
H16

W18
C19
N16
V13
W13
R13
T13

B1
A2
A3
B3
B4
A5
B5
D5
A6
B6
D6
E6
A7
B7
D7
E7
A8
B8
D8
E8

CBS_CAD15
CBS_CAD13

CBS_CC/BE3#
CBS_CC/BE2#
CBS_CC/BE1#
CBS_CC/BE0#
CBS_CPAR
CBS_CFRAME#
CBS_CTRDY#
CBS_CIRDY#
CBS_CSTOP#
CBS_CDEVSEL#
CBS_CBLOCK#
CBS_CPERR#
CBS_CSERR#
CBS_CREQ#
CBS_CGNT#
CBS_CSTSCHNG
CBS_CCLKRUN#
CBS_CCLK_R
CBS_CINT#
CBS_CRST#
CBS_CAUDIO

CBS_CCD1#
CBS_CCD2#
CBS_CVS1
CBS_CVS2

CBS_DATA14
CBS_DATA2
CBS_DATA18
VPPEN0
VPPEN1
VCC5EN#
VCC3EN#

SDCD#/MMCCD#

SDWP#
CARD_PWR

MDIO07
SDCMD/MMCCMD
SDCLK/MMCCLK
SDDAT0/MMCDAT0
SDDAT1/MMCDAT1
SDDAT2/MMCDAT2
SDDAT3/MMCDAT3
MMCDAT4
MMCDAT5
MMCDAT6
MMCDAT7

CBS_CAD31 <32>
CBS_CAD30 <32>
CBS_CAD29 <32>
CBS_CAD28 <32>
CBS_CAD27 <32>
CBS_CAD26 <32>
CBS_CAD25 <32>
CBS_CAD24 <32>
CBS_CAD23 <32>
CBS_CAD22 <32>
CBS_CAD21 <32>
CBS_CAD20 <32>
CBS_CAD19 <32>
CBS_CAD18 <32>
CBS_CAD17 <32>
CBS_CAD16 <32>
CBS_CAD15 <32>
CBS_CAD14 <32>
CBS_CAD13 <32>
CBS_CAD12 <32>
CBS_CAD11 <32>
CBS_CAD10 <32>
CBS_CAD9 <32>
CBS_CAD8 <32>
CBS_CAD7 <32>
CBS_CAD6 <32>
CBS_CAD5 <32>
CBS_CAD4 <32>
CBS_CAD3 <32>
CBS_CAD2 <32>
CBS_CAD1 <32>
CBS_CAD0 <32>

CBS_CC/BE3# <32>
CBS_CC/BE2# <32>
CBS_CC/BE1# <32>
CBS_CC/BE0# <32>
CBS_CPAR <32>
CBS_CFRAME# <32>
CBS_CTRDY# <32>
CBS_CIRDY# <32>
CBS_CSTOP# <32>
CBS_CDEVSEL# <32>
CBS_CBLOCK# <32>
CBS_CPERR# <32>
CBS_CSERR# <32>
CBS_CREQ# <32>
CBS_CGNT# <32>
CBS_CSTSCHNG <32>

CBS_CCLKRUN# <32>
CBS_CINT# <32>
CBS_CAUDIO <32>
CBS_CCD1# <32>

CBS_CCD2# <32>
CBS_CVS1 <32>
CBS_CVS2 <32>

CBS_DATA14 <32>

CBS_DATA2 <32>

CBS_DATA18 <32>

3

R410

R410

22_0402_5%~D

22_0402_5%~D

1 2

C501

@C501

@

0.01U_0402_16V7K~D

0.01U_0402_16V7K~D

TPBIAS0

TPAP0
TPAN0

TPBP0
TPBN0

56.2_0402_1%~D

56.2_0402_1%~D

270P_0402_50V7K~D

270P_0402_50V7K~D

must have clean layout

12

CBS_CCLK <32>
CBS_CRST# <32>

56.2_0402_1%~D

56.2_0402_1%~D

12

R398

R398

12

R403

R403

Z3008

2

C494

C494

1

Close to U26

56.2_0402_1%~D

56.2_0402_1%~D

1

12

R399

R399

2

12

R401

56.2_0402_1%~D

56.2_0402_1%~D

R407

R407

5.1K_0402_1%~D

5.1K_0402_1%~D

1 2

+3.3V_RUN +CBS_VCC

must have clean layout

12

R414 0_0402_5%~DR414 0_0402_5%~D
R416 0_0402_5%~D

R416 0_0402_5%~D

1 2

SDCLK/MMC_CLK_R

close to R5C847

For MMC PLUS

U28

U28

5

CARD_PWR

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

IN

4

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

ON/OFF#

AAT4250IGV-T1_SOT23-5~D

AAT4250IGV-T1_SOT23-5~D

1

C509

C509

2

3

OUT
GND

1
2
3

N.C

+3.3V_RUN_CARD+3.3V_RUN

150K_0402_5%~D

150K_0402_5%~D

1U_0603_10V4Z~D

1U_0603_10V4Z~D

0.01U_0402_16V7K~D

0.01U_0402_16V7K~D

1

2

C505

C505

1

R413

R413

C506

C506

2

1 2

Close to JP5 pin5Close to JP5 pin5

2

0.01U_0402_16V7K~D

0.01U_0402_16V7K~D

0.33U_0603_10V7K~D

0.33U_0603_10V7K~D

1

C492

C492

C493

C493

2

1394_DET#<24>

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

+5V_RUN

C495

C495

PWR_BTN_BD_DET#<37>

SNIFFER_BLUE<42>

SNIFFER_YELLOW<42>
SNIFFER_PWR_SW#<38>
WIRELESS_ON/OFF#<37>

INSTANT_ON_SW#<37,38>

POWER_SW#_MB<38,39>

BREATH_BLUE_LED_IO<42>

LID_CL#<37,42>

2

1

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

C498

1

C498

VPPEN0
VPPEN1

2

VCC3EN#
VCC5EN#

R401

1

2

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

+3.3V_ALW

C685

C685

11

13
15

3
4

2
1

5

16

SD_DET#<24>

+3.3V_RUN_CARD

SNIFFER_BLUE
SNIFFER_YELLOW
SNIFFER_PWR_SW#
WIRELESS_ON/OFF#

BREATH_BLUE_LED_IO

U27

U27

VCC3IN

VCCOUT
VCCOUT
VCCOUT

VCC5IN
VCC5IN

EN0

VPPOUT

EN1

VCC3_EN
VCC5_EN

FLG
GND

R5531V002-E2-FA_SSOP16~D

R5531V002-E2-FA_SSOP16~D

NC
NC
NC

+3.3V_ALW_ICH

SD_DET#
SDWP#

SDCD#/MMCCD#

SDDAT1/MMCDAT1
SDDAT0/MMCDAT0
MMCDAT7

MMCDAT6

SDCLK/MMC_CLK_R

MMCDAT5
SDCMD/MMCCMD
MMCDAT4
SDDAT3/MMCDAT3
SDDAT2/MMCDAT2

Some SD Caps move to SD board.

9
14
12

+CBS_VPP

8

7
6
10

R784

R784
100K_0402_5%~D

100K_0402_5%~D

1 2

1

JS1394

JS1394

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

11

11

12

12

13

13

14

14

15

15

16

16

17

17

18

18

19

19

20

20

21

GND1

22

GND2

HRS_FH28E-20S-0.5SH(11)

HRS_FH28E-20S-0.5SH(11)

1

2

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

0.01U_0402_16V7K~D

0.01U_0402_16V7K~D

C499

@ C500

@

1

2

C499

C500

2

1

JSD1

JSD1

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

11

11

12

12

13

13

14

14

15

15

16

16

17

17

18

18

19

19

20

20

21

GND1

22

GND2

HRS_FH28E-20S-0.5SH(11)

HRS_FH28E-20S-0.5SH(11)

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

C496

C496

10U_0805_10V4Z~D

10U_0805_10V4Z~D

@ C497

@

1

C497

2

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.
SCHEMATIC, MB A4042

SCHEMATIC, MB A4042

SCHEMATIC, MB A4042

401533

401533

401533

A

A

31 56Tuesday, December 18, 2007

31 56Tuesday, December 18, 2007

31 56Tuesday, December 18, 2007

1

A

of

of

of

5

4

3

2

1

+3.3V_RUN

0.01U_0402_16V7K~D

0.01U_0402_16V7K~D

10U_0805_10V4Z~D

10U_0805_10V4Z~D

1

C519

C519

1

2

0.01U_0402_16V7K~D

0.01U_0402_16V7K~D

+3.3V_RUN

1

C534

C534

2

2

0.01U_0402_16V7K~D

0.01U_0402_16V7K~D

1

C535

C535

2

CBS_CAD[0..31]<31>

CBS_CC/BE0#<31>

CBS_CC/BE1#<31>
CBS_CPERR#<31>

CBS_CGNT#<31>
CBS_CINT#<31>

CBS_CIRDY#<31>
CBS_CC/BE2#<31>

CBS_CCLKRUN#<31>

D D

+3.3V_RUN

10U_0805_10V4Z~D

10U_0805_10V4Z~D

1

C533

C533

2

C C

B B

A A

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

CBS_CPAR<31>

CBS_CCLK<31>

CBS_DATA2<31>

1

2

10U_0805_10V4Z~D

10U_0805_10V4Z~D

1

2

C536

C536

1

2

+CBS_VCC

+CBS_VPP

C520

C520

C531

C531

0.47U_0402_16V4Z~D

0.47U_0402_16V4Z~D

0.01U_0402_16V7K~D

0.01U_0402_16V7K~D

1

C521

C521

2

0.01U_0402_16V7K~D

0.01U_0402_16V7K~D

C532

C532

1

2

1

C537

C537

2

0.01U_0402_16V7K~D

0.01U_0402_16V7K~D

1

1

C522

C522

2

2

0.01U_0402_16V7K~D

0.01U_0402_16V7K~D

1

1

C529

C529

2

2

0.47U_0402_16V4Z~D

0.47U_0402_16V4Z~D

0.01U_0402_16V7K~D

0.01U_0402_16V7K~D

1

C539

C539

C538

C538

2

CBS_CAD0
CBS_CAD1
CBS_CAD3
CBS_CAD5
CBS_CAD7
CBS_CC/BE0#
CBS_CAD9
CBS_CAD11
CBS_CAD12
CBS_CAD14
CBS_CC/BE1#
CBS_CPAR
CBS_CPERR#
CBS_CGNT#
CBS_CINT#

CBS_CCLK
CBS_CIRDY#
CBS_CC/BE2#
CBS_CAD18
CBS_CAD20
CBS_CAD21
CBS_CAD22
CBS_CAD23
CBS_CAD24
CBS_CAD25
CBS_CAD26
CBS_CAD27
CBS_CAD29
CBS_DATA2
CBS_CCLKRUN#

0.01U_0402_16V7K~D

0.01U_0402_16V7K~D

C523

C523

0.01U_0402_16V7K~D

0.01U_0402_16V7K~D

C530

C530

0.01U_0402_16V7K~D

0.01U_0402_16V7K~D

1

2

0.01U_0402_16V7K~D

0.01U_0402_16V7K~D

1

C776

C776

2

+3.3V_RUN_PHY

C540

C540

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34

69
70

+CBS_VPP

Close to JCBUS1 Pin18/52

5

+3.3V_RUN

U26B

U26B

R5C847-CSP208Q

R5C847-CSP208Q

F5

VCC_3V

G5

VCC_3V

J19

VCC_3V

K19

VCC_3V

W3

VCC_PCI3V

R11

VCC_PCI3V

R12

VCC_PCI3V

R6

VCC_RIN

E13

VCC_RIN

L1

VCC_ROUT

E14

VCC_ROUT

A4

VCC_MD3V

E10

AVCC_PHY3V

E11

AVCC_PHY3V

A17

AVCC_PHY3V

B17

AVCC_PHY3V

D10

NC

E1

NC

C2

NC

D2

NC

E2

NC

L2

NC

E4

NC

JCBUS1

JCBUS1

GND1
CAD0
CAD1
CAD3
CAD5
CAD7
CCBE0#
CAD9
CAD11
CAD12
CAD14
CCBE1#
CPAR
CPERR#
CGNT#
CINT#
VCC
VPP1
CCLK
CIRDY#
CCBE2#
CAD18
CAD20
CAD21
CAD22
CAD23
CAD24
CAD25
CAD26
CAD27
CAD29
CB_D2
CCLKRUN#
GND2

GND5
GND6

MOLEX_48315-0013_RT

MOLEX_48315-0013_RT

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

1

C769

C769

2

L28

L28
BLM21AG601SN1D_0805~D

BLM21AG601SN1D_0805~D

1 2

CBLOCK#

CDEVSEL#

CFRAME#

CSTSCHG

10U_0805_10V4Z~D

10U_0805_10V4Z~D

1

2

DIGITAL

POWER

DIGITAL

POWER

ANALOG

POWER

ANALOG

POWER

NC

NC

R5C847-CSP208Q_CSP208~D

R5C847-CSP208Q_CSP208~D

35

GND3

36

CCD1#

37

CAD2

38

CAD4

39

CAD6

40

CB_D14

41

CAD8

42

CAD10

43

CVS1

44

CAD13

45

CAD15

46

CAD16

47

CB_D18

48
49

CSTOP#

50
51

VCC

52

VPP2

53

CTRDY#

54
55

CAD17

56

CAD19

57

CVS2

58

CRST#

59

CSERR#

60

CREQ#

61

CCBE3#

62

CAUDIO

63
64

CAD28

65

CAD30

66

CAD31

67

CCD2#

68

GND4

71

GND7

72

GND8

4

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

1

1

C524

C524

C525

C525

2

2

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

DIGITAL

GND

DIGITAL

GND

AGND
AGND
AGND
AGND
AGND
AGND

ANALOG

GND

ANALOG

GND

NC
NC
NC
NC
NC
NC
NC

CBS_CCD1#
CBS_CAD2
CBS_CAD4
CBS_CAD6
CBS_DATA14
CBS_CAD8
CBS_CAD10
CBS_CVS1
CBS_CAD13
CBS_CAD15
CBS_CAD16
CBS_DATA18
CBS_CBLOCK#
CBS_CSTOP#
CBS_CDEVSEL#

CBS_CTRDY#
CBS_CFRAME#
CBS_CAD17
CBS_CAD19
CBS_CVS2
CBS_CRST#
CBS_CSERR#
CBS_CREQ#
CBS_CC/BE3#
CBS_CAUDIO
CBS_CSTSCHNG
CBS_CAD28
CBS_CAD30
CBS_CAD31
CBS_CCD2#

1

2

Close to JCBUS1 pin51,17

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

C526

C526

J1
J5
K5
E9
R10
T10
V10
W10
L15
M19

A9
B9
D9
D14
A15
B15

A10
A11
B10
B11
C1
D1
E12

+CBS_VCC

0.01U_0402_16V7K~D

0.01U_0402_16V7K~D

C541

C541

+3.3V_RUN_PHY

1000P_0402_50V7K~D

1000P_0402_50V7K~D

1000P_0402_50V7K~D

1000P_0402_50V7K~D

1

1

C527

C527

2

2

CBS_CCD1# <31>

CBS_CVS1 <31>

+CBS_VCC
+CBS_VPP

CBS_CVS2 <31>

CBS_CCD2# <31>

0.01U_0402_16V7K~D

0.01U_0402_16V7K~D

C542

C542

1

1

2

2

C528

C528

CBS_DATA14 <31>

CBS_DATA18 <31>
CBS_CBLOCK# <31>
CBS_CSTOP# <31>
CBS_CDEVSEL# <31>

CBS_CTRDY# <31>
CBS_CFRAME# <31>

CBS_CRST# <31>
CBS_CSERR# <31>
CBS_CREQ# <31>
CBS_CC/BE3# <31>
CBS_CAUDIO <31>
CBS_CSTSCHNG <31>

10U_0805_10V4Z~D

10U_0805_10V4Z~D

C543

C543

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

1.5Vout

1.5Vout

3.3Vout

3.3Vout

OC#

PERST#

GND

NC

+1.5V_CARD

11
13

3
5

15
19
8
16
7

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

C999

1

C999

2

1

2

CARD_RESET#

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

C314

1

C314

2

+3.3V_CARDAUX

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

C801

C801

+3.3V_CARD

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

C356

1

C356

2

10U_0805_6.3V6M~D

10U_0805_6.3V6M~D

C781

C788

1

1

C781

C788

2

2

+1.5V_RUN

+3.3V_SUS

+3.3V_RUN

0.1U_0402_16V4Z~D

C134

0.1U_0402_16V4Z~D

1

1

C134

2

2

+3.3V_SUS

1 2

R657 100K_0402_5%~D R657 100K_0402_5%~D

EXPRCRD_STDBY#<37>

1 2

R683 0_0402_5%~D R683 0_0402_5%~D

1 2

R684 100K_0402_5%~D R684 100K_0402_5%~D

1 2

R790 100K_0402_5%~D R790 100K_0402_5%~D

EXPRCRD_PWREN#<37>

PLTRST1#<10,22,51>

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

1

0.1U_0402_16V4Z~D

C135

0.1U_0402_16V4Z~D

2

C135

PLTRST1#

EXPRCRD_STBY_R#
EXPRCRD_PWREN#
CPUSB#

C997

C997

12
14

20

10

18

U52

U52

1.5Vin

1.5Vin

2

3.3Vin

4

3.3Vin
AUX_IN17AUX_OUT

6

SYSRST#
SHDN#

1

STBY#
CPPE#

9

CPUSB#
RCLKEN

R5538_QFN20~D

R5538_QFN20~D

Express Card

+1.5V_CARD: Max. 650mA, Average 500mA
+3.3V_CARD: Max. 1300mA, Average 1000mA

C802

C802

USBP7_D­USBP7_D+

+1.5V_CARD

CLK_PCIE_EXP#<6>
CLK_PCIE_EXP<6>

PCIE_IRX_EXPTX_N4<24>
PCIE_IRX_EXPTX_P4<24>

PCIE_ITX_EXPRX_N4_C<24>
PCIE_ITX_EXPRX_P4_C<24>

EXPRCRD_DET#<37>

CPUSB#

EXP_SMBCLK
EXP_SMBDATA

PCIE_WAKE#<34,37>

EXPCLK_REQ#<6>

PCIE_WAKE#

CARD_RESET#

EXPRCRD_PWREN#

DELL CONFIDENTIAL/PROPRIETARY

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

401533

401533

401533

Date: Sheet

Date: Sheet

Date: Sheet

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

1 2

R791 0_0402_5%~D R791 0_0402_5%~D

1 2

R792 0_0402_5%~D R792 0_0402_5%~D

USBP7-<24>

USBP7+<24>

+3.3V_CARDAUX

+3.3V_SUS

6 1

2
5

3

CARD_SMBDAT<34,38>

CARD_SMBCLK<34,38>

3

1

1

4

4

DLW21SN900SQ2_0805~D

DLW21SN900SQ2_0805~D

1

2

+3.3V_SUS

12

Q112A

Q112A

2N7002DW-T/R7_SOT363-6

2N7002DW-T/R7_SOT363-6

Q112B

Q112B

2N7002DW-T/R7_SOT363-6

2N7002DW-T/R7_SOT363-6

4

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

L64

C789

C789

2.2K_0402_5%~D

2.2K_0402_5%~D

2

3

@L64

@

+3.3V_CARD

R126

12

R126

2

3

2.2K_0402_5%~D

2.2K_0402_5%~D

R127

R127

EXP_SMBDATA

EXP_SMBCLK

1

2

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

C790

1

C790

2

2

+3.3V_ALW

R947

R947
100K_0402_5%~D

100K_0402_5%~D

1 2

JEXP1

JEXP1

1

GND1

2

GND2

3

GND3

4

GND4

5

USBD-

6

USBD+

7

CPUSB#

8

RESERVE1

9

RESERVE2

10

SMBCLK

11

SMBDATA

12

+1.5V_1

13

+1.5V_2

14

WAKE#

15

+3.3VAUX

16

PERST#

17

+3.3V_1

18

+3.3V_2

19

+3.3V_3

20

CLKREQ#

21

CPPE#

22

NC

23

REFCLK-

24

REFCLK+

25

GND5

26

GND6

27

GND7

28

GND8

29

PERN0

30

PERP0

31

GND9

32

GND10

33

GND11

34

GND12

35

PETN0

36

PETP0

37

GND13

38

GND14

39

GND15

40

GND16

41

GND17

42

GND18

HRS_FH28-40S-0.5SH(05)

HRS_FH28-40S-0.5SH(05)

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.
SCHEMATIC, MB A4042

SCHEMATIC, MB A4042

SCHEMATIC, MB A4042

32 56Tuesday, December 18, 2007

32 56Tuesday, December 18, 2007

32 56Tuesday, December 18, 2007

1

A

A

A

of

of

of

5

FUSE1

@FUSE1

@

L0603

L0603

1 2

+5V_ALW

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

1

D D

2

C546

C546

1

2

@ PJP26

@

10U_1206_16V4Z~D

10U_1206_16V4Z~D

C547

C547

PJP26

PAD-OPEN 4x4m

PAD-OPEN 4x4m

12

+5V_ALW_FUSE

ESATA_USB_PWR_EN#<37>

U29

U29

1

GND

2

IN

3

EN1#

4

EN2#

TPS2062DR_SO8~D

TPS2062DR_SO8~D

OC1#
OUT1
OUT2
OC2#

8
7
6
5

U53

U53

1

+5V_ALW_FUSE

USB_POWERSHARE_PWR_EN#<37>

C C

B B

A A

+3.3V_LAN +VREFOUT +3.3V_SUS +1.8V_LAN_M

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

1

2

Place close
to JIO1.13

C768

C768

SW_LAN_TX3+<30>
SW_LAN_TX3-<30>

SW_LAN_TX2-<30>
SW_LAN_TX2+<30>

SW_LAN_TX1+<30>
SW_LAN_TX1-<30>

SW_LAN_TX0-<30>
SW_LAN_TX0+<30>

+3.3V_LAN

IO_LOOP<24>

USBP2-<24>

USBP2+<24>

USBP3-<24>

USBP3+<24>

USBP0+<24>
USBP0-<24>

USBP1+<24>
USBP1-<24>

+5V_ALW

USBP2-

USBP2+

USBP3-

USBP3+

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

1

C623

C623

2

5

GND

2

IN

3

EN1#

4

EN2#

TPS2062DR_SO8~D

TPS2062DR_SO8~D

L30

@L30

@

DLW21SN121SQ2L_4P~D

DLW21SN121SQ2L_4P~D

1

1

4

4

1 2

R425 0_0402_5%~D

R425 0_0402_5%~D

1 2

R424 0_0402_5%~D

R424 0_0402_5%~D

L31

@L31

@

DLW21SN121SQ2L_4P~D

DLW21SN121SQ2L_4P~D

1

1

4

4

1 2

R426 0_0402_5%~D

R426 0_0402_5%~D

1 2

R427 0_0402_5%~D

R427 0_0402_5%~D

JIO1

JIO1

26

1

26

27

2

27

28

3

28

29

4

29

30

5

30

31

6

31

32

7

32

33

8

33

34

9

34

35

10

35

36

11

36

37

12

37

38

13

38

39

14

39

40

15

40

41

16

41

42

17

42

43

18

43

44

19

44

45

20

45

46

21

46

47

22

47

48

23

48

49

24

49

50

25

50

TYCO_1759898-1

TYCO_1759898-1

OC1#
OUT1
OUT2
OC2#

2

2

3

3

2

2

3

3

DETECT_GND

ICH_AZ_MDC_RST1#

8
7
6
5

4

+5V_ESATA

ESATA_USB_OC#

+5V_CHGUSB

USB_OC2#

USB_OC2# <24>

USBP2_D-

USBP2_D+

USBP3_D-

USBP3_D+

Left side USB Port

AUD_EXT_MIC_L <27>

AUD_EXT_MIC_R <27>

+VREFOUT

AUD_MIC_SWITCH <27>

LAN_ACTLED_YEL_R# <30>

LED_10_GRN_R# <30>

LED_100_ORG_R# <30>

+3.3V_SUS

+1.8V_LAN_M

USB_SIDE_EN# <37>

USB_OC0_1# <24>

ICH_AZ_MDC_BITCLK <23>

ICH_AZ_MDC_SDOUT <23>

ICH_AZ_MDC_SYNC <23>
ICH_AZ_MDC_SDIN1 <23>

AUD_HP_NB_SENSE <27,28,37>
HP_SPK_L1 <28>

HP_SPK_R1 <28>

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

1

C634

C634

2

Place close
to JIO1.30

4

Place close
to JIO1.35

ESATA_USB_OC# <24>

EN_CELL_CHARGER_DET#<38>

CELL_CHARGER_DET#<37>

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

1

C711

C711

2

3

+5V_ESATA

150U_D_6.3VM_R15M~D

150U_D_6.3VM_R15M~D

1

+

+

2

+5V_CHGUSB

150U_D_6.3VM_R15M~D

150U_D_6.3VM_R15M~D

1

+

+

2

+3.3V_SUS

USBP2_D+ USBP2_D+_SW
USBP2_D-

USBP2_D+_SW

USBP3_D+

Place ESD diodes as close as USB connector.

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

1

C712

C712

2

Place close
to JIO1.36

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

1

C544

C544

C588

C588

R986 0_0402_5%~DR986 0_0402_5%~D
R987 0_0402_5%~DR987 0_0402_5%~D

C545

C545

2

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

1

C548

C548

2

ESATA_IRX_DTX_N4_C<23>
ESATA_IRX_DTX_P4_C<23>

12
12

U54

U54

8

VCC
HSD+2D+

6

HSD-

7

OE#

TS3USB31RSER

TS3USB31RSER

U30

@U30

@

1

GND

IO2

2

IO1

VIN

PRTR5V0U2X_SOT143-4~D

PRTR5V0U2X_SOT143-4~D

U55

@U55

@

1

GND

IO2

2

IO1

VIN

PRTR5V0U2X_SOT143-4~D

PRTR5V0U2X_SOT143-4~D

ICH_AZ_MDC_RST#<23>

MDC_RST_DIS#<37>

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

ESATA_ITX_DRX_P4<23>
ESATA_ITX_DRX_N4<23>

1 2

C1021 0.1U_0402_16V4Z~D

C1021 0.1U_0402_16V4Z~D

1

NC

3
5

D-

4

GND

USBP2_D-_SW

3
4

USBP3_D-

3
4

+5V_RUN

R326

R326
10K_0402_5%~D

10K_0402_5%~D

1 2

3

C549 0.01U_0402_16V7K~D C549 0.01U_0402_16V7K~D
C550 0.01U_0402_16V7K~D C550 0.01U_0402_16V7K~D

USBP2_D-_SW

+5V_CHGUSB

+5V_ESATA

USBP3_D­USBP3_D+

USBP2_D-_SW
USBP2_D+_SW

ESATA_IRX_DTX_N4

12

ESATA_IRX_DTX_P4

12

1 2

R324 0_0402_5%~D@ R324 0_0402_5%~D@

D

D

1 3

S

S

Q35

Q35
2N7002W-7-F_SOT323-3~D

2N7002W-7-F_SOT323-3~D

G

G

2

JESA1

JESA1

1

A_VCC

2

A_D-

3

A_D+

4

A_GND

USB

USB

5

B_VCC

6

B_D-

7

B_D+

8

B_GND

9

GND

10

A+

ESATA

ESATA

11

A-

12

GND

13

B-

14

B+

15

GND

16

DET1

17

DET2

18

G1

19

G2

20

G3

21

G4

TYCO_1759562-1

TYCO_1759562-1

ICH_AZ_MDC_RST1#

12

R325

R325
100K_0402_5%~D

100K_0402_5%~D

2

2

USB PORT#

0
1
2
3
4
5
6
7
8
9
10
11

FP_USBD+<36>

FP_USBD-<36>

+5V_RUN

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

1

@

@

C1015

C1015

2

TYCO_1734820-6

TYCO_1734820-6

FP_USB_D-

1

DESTINATION
JUSB1 (Ext Right Side Top)
JUSB1 (Ext Right Side Bottom)
JESA1 (Ext Left Side Bottom)
JESA1 (Ext Left Side TOP)
WLAN
WWAN
WPAN
Express card
DOCKING
DOCKING
USH->BIO
Camera

L29

@L29

@

DLW21SN121SQ2L_4P~D

DLW21SN121SQ2L_4P~D

1

1

4

4

1 2

R422 0_0402_5%~D

R422 0_0402_5%~D

1 2

R423 0_0402_5%~D

R423 0_0402_5%~D

Fingerprint CONN.

JBIO1

JBIO1

1

1

2

2

3

3

4

4

5

5

6

GND
IO1

1 2

R910

R910
0_0603_5%~D

0_0603_5%~D

7
8

U51

FP_USB_D+

3

IO2

4

VIN

6

GND
GND

@U51

@

1
2

PRTR5V0U2X_SOT143-4~D

PRTR5V0U2X_SOT143-4~D

2

2

3

3

+3.3V_RUN

FP_USB_D­FP_USB_D+

BIO_DET# <24>

@

@

+3.3V_RUN

FP_USB_D+

FP_USB_D-

+5V_RUN

Place close to
JBIO1.1

+3.3V_RUN

1

2

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

C770

C770

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, MB A4042

SCHEMATIC, MB A4042

SCHEMATIC, MB A4042

401533

401533

401533

33 56Tuesday, December 18, 2007

33 56Tuesday, December 18, 2007

33 56Tuesday, December 18, 2007

1

A

A

A

of

of

of

5

2.2K_0402_5%~D

2.2K_0402_5%~D

12

D D

+3.3V_RUN

1

C570

C570

2

1U_0603_10V4Z~D

1U_0603_10V4Z~D

1

2

PCIE_WAKE#

MINI1CLK_REQ#
CLK_PCIE_MINI1#

CLK_PCIE_MINI1

PCIE_IRX_WANTX_N1
PCIE_IRX_WANTX_P1

PCIE_ITX_WANRX_N1_C
PCIE_ITX_WANRX_P1_C

PCIE_MCARD2_DET#

0.047U_0402_16V4Z~D

0.047U_0402_16V4Z~D

0.047U_0402_16V4Z~D

0.047U_0402_16V4Z~D

1

C564

C564

C565

C565

2

JSIM1

JSIM1

1

VCC

2

RST

3

CLK

4

NC

C573

C573

MOLEX_475531001

MOLEX_475531001

Voltage
Tolerance

+-9%

+-9%

+-5%

33P_0402_50V8J~D

33P_0402_50V8J~D

1

C566

C566

2

Primary Power Aux Power

Peak Normal Normal

1000 750

330

500

PCIE_WAKE#<32,37>

MINI1CLK_REQ#<6>

CLK_PCIE_MINI1#<6>
CLK_PCIE_MINI1<6>

PCIE_IRX_WANTX_N1<24>
PCIE_IRX_WANTX_P1<24>

PCIE_ITX_WANRX_N1_C<24>
PCIE_ITX_WANRX_P1_C<24>

PCIE_MCARD2_DET#<22>

C C

+1.5V_RUN

0.047U_0402_16V4Z~D

0.047U_0402_16V4Z~D

33P_0402_50V8J~D

33P_0402_50V8J~D

1

1

C569

C569

2

2

+SIM_PWR

UIM_RESET

B B

UIM_CLK

PWR
Rail

+3.3V

+3.3Vaux

+1.5V

A A

MINI_SMBCLK

MINI_SMBDATA

Mini WWAN

1
3
5
7

9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51

53

22U_0805_6.3VAM~D

22U_0805_6.3VAM~D

33P_0402_50V8J~D

33P_0402_50V8J~D

1

1

C567

C567

C568

C568

2

2

5

GND

6

VPP

7

I/O

8

NC

9

GND

10

GND

JMINI1

JMINI1

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51

GND1

TYCO_1775861-1~D

TYCO_1775861-1~D

330U_D2E_6.3VM_R25~D

330U_D2E_6.3VM_R25~D

1

+

+

C563

C563

2

UIM_DATA

250

375

+3.3V_RUN +3.3V_WLAN+3.3V_ALW+15V_ALW

2.2K_0402_5%~D

2.2K_0402_5%~D

12

R429

R429

R430

R430

2

5

3

4

Q48B

Q48B
2N7002DW-T/R7_SOT363-6~D

2N7002DW-T/R7_SOT363-6~D

+3.3V_RUN+3.3V_RUN

2

2

4

4

6

6

8

8

10

10

12

12

14

14

16

16

18

18

20

20

22

22

24

24

26

26

28

28

30

30

32

32

34

34

36

36

38

38

40

40

42

42

44

44

46

46

48

48

50

50

52

52

54

GND2

USBP5-<24>

USBP5+<24>

UIM_CLKUIM_VPP

33P_0402_50V8J~D

33P_0402_50V8J~D

1

C574

C574

2

250 (Wake enable)
5 (Not wake enable)

NA

5

4

WLAN_RADIO_DIS#<37>

CARD_SMBCLK

61

Q48A

Q48A
2N7002DW-T/R7_SOT363-6~D

2N7002DW-T/R7_SOT363-6~D

CARD_SMBDAT

@

USB_MCARD2_DET# PCIE_MCARD2_DET#

UIM_DATA
UIM_CLK
UIM_RESET
UIM_VPP

WWAN_RADIO_DIS#

1 2

R442 0_0402_5%~DR442 0_0402_5%~D

MINI_SMBCLK
MINI_SMBDATA

USBP5_D­USBP5_D+
USB_MCARD2_DET#
LED_WWAN_OUT#

1 2

R840 0_0402_5%~D@ R840 0_0402_5%~D@

For WIMAX LED debug

USB_MCARD2_DET#
PCIE_MCARD2_DET#

33P_0402_50V8J~D

33P_0402_50V8J~D

1

C575

C575

2

@

1 2

R740 0_0402_5%~D

R740 0_0402_5%~D

+1.5V_RUN
+SIM_PWR

PLTRST3#

USB_MCARD2_DET# <24>
LED_WWAN_OUT# <42>

WIMAX LED

R447 100K_0402_5%~D R447 100K_0402_5%~D

1 2

R449 8.2K_0402_5%~DR449 8.2K_0402_5%~D

L32

@L32

@

DLW21SN121SQ2L_4P~D

DLW21SN121SQ2L_4P~D

1

1

4

4

1 2

R450 0_0402_5%~D

R450 0_0402_5%~D

1 2

R451 0_0402_5%~D

R451 0_0402_5%~D

U31

U31

1

2

3

SRV05-4.TCT_SOT23-6~D

SRV05-4.TCT_SOT23-6~D

4

12

2

2

3

3

6

5

4

WWAN_RADIO_DIS# <37>
PLTRST3# <22,36>

+3.3V_RUN

USBP5_D-

USBP5_D+

UIM_VPPUIM_RESET

UIM_DATA

33P_0402_50V8J~D

33P_0402_50V8J~D

1

C576

C576

2

+SIM_PWR

33P_0402_50V8J~D

33P_0402_50V8J~D

1

2

1 2

R428 0_0402_5%~D @R428 0_0402_5%~D @

D21

D21
RB751S40T1_SOD523-2~D

RB751S40T1_SOD523-2~D

C577

C577

WLAN_RADIO_DIS#_R

21

2N7002DW-T/R7_SOT363-6~D

2N7002DW-T/R7_SOT363-6~D

AUX_EN_WOWL<38>

100K_0402_5%~D

100K_0402_5%~D

COEX2_WLAN_ACTIVE

33P_0402_50V8J~D

33P_0402_50V8J~D

+1.5V_RUN

0.047U_0402_16V4Z~D

0.047U_0402_16V4Z~D

1

C555

C555

2

1

2

3

@ C552

@

R437

R437

C552

+3.3V_WLAN

0.047U_0402_16V4Z~D

0.047U_0402_16V4Z~D

C556

C556

Q53A

Q53A

12

1

2

2

1

2

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

@C557

@

C557

100K_0402_5%~D

100K_0402_5%~D

D

D

6

S

100K_0402_5%~D

100K_0402_5%~D

12

61

0.047U_0402_16V4Z~D

0.047U_0402_16V4Z~D

1

C558

C558

2

12

R432

R431

R431

COEX2_WLAN_ACTIVE
COEX1_BT_ACTIVE

PCIE_IRX_WLANTX_N2<24>
PCIE_IRX_WLANTX_P2<24>

PCIE_ITX_WLANRX_N2_C<24>
PCIE_ITX_WLANRX_P2_C<24>

1

2

R432

2N7002DW-T/R7_SOT363-6~D

2N7002DW-T/R7_SOT363-6~D

3

Q53B

Q53B

5

200K_0402_5%~D

200K_0402_5%~D

4

12

@

@

R436

R436

MINI2CLK_REQ#<6>
CLK_PCIE_MINI2#<6>

CLK_PCIE_MINI2<6>

PCIE_MCARD1_DET#<24>

ICH_CL_CLK1<24> LED_WPAN_OUT# <42>

ICH_CL_DATA1<24>

ICH_CL_RST1#<24>

0.047U_0402_16V4Z~D

0.047U_0402_16V4Z~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

1

1

C559

C559

C560

C560

2

2

S

45

2

Q47

Q47

1

SI3456BDV-T1-E3_TSOP6~D

SI3456BDV-T1-E3_TSOP6~D

G

G

3

470K_0402_5%~D

470K_0402_5%~D

12

@

@

R435

R435

PCIE_WAKE#

R440 0_0402_5%~D

R440 0_0402_5%~D

1 2

R441 0_0402_5%~D

R441 0_0402_5%~D

1 2

PCIE_IRX_WLANTX_N2
PCIE_IRX_WLANTX_P2

PCIE_ITX_WLANRX_N2_C
PCIE_ITX_WLANRX_P2_C

PCIE_MCARD1_DET#

1 2

R448 0_0402_5%~DR448 0_0402_5%~D

4.7U_0603_6.3V4Z~D

4.7U_0603_6.3V4Z~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

C561

C561

1

1

+

+

C562

C562

2

2

2

4700P_0402_25V7K~D

4700P_0402_25V7K~D

1

C551

C551

2

Mini WLAN

+3.3V_WLAN +3.3V_WLAN

330U_D2E_6.3VM_R25~D

330U_D2E_6.3VM_R25~D

C554

C554

Mini-Card Latch Remove
For ME 2007/10/29
Drawing

WPAN Card

JMINI3

C585

C585

JMINI3

1

1

3

3

5

5

7

7

9

9

11

11

13

13

15

15

17

17

19

19

21

21

23

23

25

25

27

27

29

29

31

31

33

33

35

35

37

37

39

39

41

41

43

43

45

45

47

47

49

49

51

51

53

GND1

TYCO_1775861-1~D

TYCO_1775861-1~D

2

GND2

2
4
6

8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

COEX2_WLAN_ACTIVE
COEX1_BT_ACTIVE

MINI3CLK_REQ#<6>

CLK_PCIE_MINI3#<6>
CLK_PCIE_MINI3<6>

HOST_DEBUG_RX<38>

C579

C579

MSCLK<38>

PCIE_MCARD3_DET#<22>

+3.3V_RUN

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

@C580

@

1

1

C580

2

2

PCIE_IRX_MCARDTX_N3<24>
PCIE_IRX_MCARDTX_P3<24>

PCIE_ITX_MCARDRX_N3_C<24>
PCIE_ITX_MCARDRX_P3_C<24>

+1.5V_RUN

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

+3.3V_RUN

0.047U_0402_16V4Z~D

0.047U_0402_16V4Z~D

0.047U_0402_16V4Z~D

0.047U_0402_16V4Z~D

1

1

C578

C578

2

2

3

PCIE_WAKE#

R454 0_0402_5%~D

R454 0_0402_5%~D

1 2

R455 0_0402_5%~D

R455 0_0402_5%~D

1 2

MINI3CLK_REQ#
CLK_PCIE_MINI3#

CLK_PCIE_MINI3
HOST_DEBUG_RX

MSCLK
PCIE_IRX_MCARDTX_N3

PCIE_IRX_MCARDTX_P3

PCIE_ITX_MCARDRX_N3_C
PCIE_ITX_MCARDRX_P3_C

PCIE_MCARD3_DET#

1 2

R458 100K_0402_5%~DR458 100K_0402_5%~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

0.047U_0402_16V4Z~D

0.047U_0402_16V4Z~D

1

1

1

C583

C583

C582

C582

2

2

2

0.047U_0402_16V4Z~D

0.047U_0402_16V4Z~D

C581

C581

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

C584

C584

4.7U_0603_6.3V4Z~D

4.7U_0603_6.3V4Z~D

1

2

WLAN_SMBCLK

WLAN_SMBDATA

JMINI2

JMINI2

1

1

3

3

5

5

7

7

9

9

11

11

13

13

15

15

17

17

19

19

21

21

23

23

25

25

27

27

29

29

31

31

33

33

35

35

37

37

39

39

41

41

43

43

45

45

47

47

49

49

51

51

53

GND1

TYCO_1775861-1~D

TYCO_1775861-1~D

+3.3V_RUN+3.3V_RUN

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

54

+3.3V_WLAN

2.2K_0402_5%~D

2.2K_0402_5%~D

2.2K_0402_5%~D

2.2K_0402_5%~D

12

12

R434

R434

R433

R433

2

2

4

4

6

6

8

8

10

10

12

12

14

14

16

16

18

18

20

20

22

22

24

24

26

26

28

28

30

30

32

32

34

34

36

36

38

38

40

40

42

42

44

44

46

46

48

48

50

50

52

52

54

GND2

USB_MCARD3_DET# PCIE_MCARD3_DET#

HOST_DEBUG_TX

PLTRST3#

12

R456 0_0402_5%~D

R456 0_0402_5%~D

MINI_SMBCLK
MINI_SMBDATA

USBP6_D­USBP6_D+
USB_MCARD3_DET#
MSDATA

1 2

R459 0_0402_5%~D R459 0_0402_5%~D

2

Q49A

Q49A

5

2N7002DW-T/R7_SOT363-6~D

2N7002DW-T/R7_SOT363-6~D

3

4

Q49B

Q49B
2N7002DW-T/R7_SOT363-6~D

2N7002DW-T/R7_SOT363-6~D

+1.5V_RUN

PCIE_MCARD1_DET#

USB_MCARD1_DET#

USB_MCARD1_DET# PCIE_MCARD1_DET#

WLAN_RADIO_DIS#_R

R444 0_0402_5%~D

R444 0_0402_5%~D

WLAN_SMBCLK
WLAN_SMBDATA

USBP4_D­USBP4_D+
USB_MCARD1_DET#
WIMAX LED
LED_WLAN_OUT#

1 2

R446 0_0402_5%~D@ R446 0_0402_5%~D@

USBP4+<24>

USBP4-<24>

@

@

1 2

R742 0_0402_5%~D

R742 0_0402_5%~D

+1.5V_RUN

1 2

C571 4700P_0402_25V7K~DC571 4700P_0402_25V7K~D

HOST_DEBUG_TX <38>

WPAN_RADIO_DIS# <37>

+3.3V_RUN

12

MSDATA <38>

LED_WPAN_OUT#

USBP6-<24>

USBP6+<24>

CARD_SMBCLK

61

CARD_SMBDAT

PLTRST3#

12

LED_WPAN_OUT#

L33

@L33

@

DLW21SN121SQ2L_4P~D

DLW21SN121SQ2L_4P~D

1

1

4

4

1 2

R452 0_0402_5%~D

R452 0_0402_5%~D

1 2

R453 0_0402_5%~D

R453 0_0402_5%~D

R266

R266
100K_0402_5%~D

100K_0402_5%~D

L34

@L34

@

DLW21SN121SQ2L_4P~D

DLW21SN121SQ2L_4P~D

1

1

4

4

1 2

R460 0_0402_5%~D

R460 0_0402_5%~D

1 2

R461 0_0402_5%~D

R461 0_0402_5%~D

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, MB A4042

SCHEMATIC, MB A4042

SCHEMATIC, MB A4042

401533

401533

401533

1

CARD_SMBCLK <32,38>

CARD_SMBDAT <32,38>

+3.3V_ALW_ICH

1 2

R439 100K_0402_5%~D R439 100K_0402_5%~D

1 2

R438 100K_0402_5%~DR438 100K_0402_5%~D

@

@

1 2

R741 0_0402_5%~D

R741 0_0402_5%~D

2

3

1
2
3
4

TYCO_1775868-1~D

TYCO_1775868-1~D

Mini-Card Latch

USB_MCARD3_DET# <24>

2

3

1

+3.3V_RUN

USB_MCARD1_DET# <24>
LED_WLAN_OUT# <42>

WLAN Noise

USB_MCARD1_DET#

1

C553

C553
4700P_0402_25V7K~D

4700P_0402_25V7K~D

2

USBP4_D+

2

USBP4_D-

3

WPAN Noise

USB_MCARD3_DET#

1

C572

C572
4700P_0402_25V7K~D

4700P_0402_25V7K~D

2

JLAT3

JLAT3

GND1
GND2
GND3
GND4

USBP6_D-

2

USBP6_D+

3

34 56Monday, December 17, 2007

34 56Monday, December 17, 2007

34 56Monday, December 17, 2007

of

of

of

A

A

A

2

JP1

JP1

1

1

3

3

5

5

7

7

9

9

11

11

13

13

15

15

17

17

19

19

21

21

23

23

25

25

27

27

29

29

31

31

33

33

35

35

37

37

39

39

41

41

43

43

45

45

47

47

49

49

51

51

53

53

55

55

57

57

59

59

61

61

63

63

65

65

67

67

69

69

71

71

73

73

75

75

77

77

79

79

81

81

83

83

85

85

87

87

89

89

91

91

93

93

95

95

97

97

99

99

101

101

103

103

105

105

107

107

109

109

111

111

113

113

115

115

117

117

119

119

121

121

123

123

125

125

127

127

129

129

131

131

133

133

135

135

137

137

139

139

141

141

143

143

145

GND1

146

PWR1

147

PWR1

148

PWR1

153

Shield_G

154

Shield_G

155

Shield_G

156

Shield_G

157

Shield_G

158

Shield_G

159

Shield_G

160

Shield_G

JAE_SP06-16082-R144-2

JAE_SP06-16082-R144-2

PWR2
PWR2
PWR2

GND2

Shield_G
Shield_G
Shield_G
Shield_G
Shield_G
Shield_G
Shield_G
Shield_G

DOCK_AC_OFF

2

2

4

4
6

8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98

100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144

6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144

149
150
151
152

161
162
163
164
165
166
167
168

DPC_CA_DET
DPC_LANE_P0_C

DPC_LANE_N0_C
DPC_LANE_P1_C

DPC_LANE_N1_C
DPC_LANE_P2_C

DPC_LANE_N2_C
DPC_LANE_P3_C

DPC_LANE_N3_C
DPC_DOCK_AUX_SW

DPC_DOCK_AUX#SW
DPC_DOCK_HP_R

SATA_SBRX_DTX_P3
SATA_SBRX_DTX_N3

TR0/1CT
TR2/3CT

DOCK_DET#

D66

D66

2 1

SD05.TCT_SOD323-2~D

SD05.TCT_SOD323-2~D

DOCK_AC_OFF <37>
DOCK_LOM_SPD100LED_ORG# <30>

DPC_CA_DET <21,51>

DPC_LANE_P0_C <51>

DPC_LANE_N0_C <51>

DPC_LANE_P1_C <51>

DPC_LANE_N1_C <51>

DPC_LANE_P2_C <51>

DPC_LANE_N2_C <51>

DPC_LANE_P3_C <51>

DPC_LANE_N3_C <51>

DPC_DOCK_AUX_SW <21>

DPC_DOCK_AUX#SW <21>

ACAV_IN_DOCK# <38,49>

CLK_DDC2_DOCK <20>

C586 0.01U_0402_16V7K~D C586 0.01U_0402_16V7K~D
C587 0.01U_0402_16V7K~D C587 0.01U_0402_16V7K~D

SATA_SBTX_C_DRX_P3 <23>
SATA_SBTX_C_DRX_N3 <23>

BREATH_LED# <38,42>
DOCK_LOM_ACTLED_YEL# <30>

DOCK_LOM_TRD0+ <30>

DOCK_LOM_TRD0- <30>

DOCK_LOM_TRD1+ <30>

DOCK_LOM_TRD1- <30>

+1.8V_LAN_M

DOCK_LOM_TRD2+ <30>
DOCK_LOM_TRD2- <30>

DOCK_LOM_TRD3+ <30>
DOCK_LOM_TRD3- <30>

PCI_RST# <22,31>
DOCK_DET# <21,37>

+DOCK_PWR_BAR

0.1U_0603_50V4Z~D

0.1U_0603_50V4Z~D
C1016

C1016

1

2

DPC_DOCK_HP_R

DAT_DDC2_DOCK <20>

12
12

USBP8+ <24>
USBP8- <24>

USBP9+ <24>
USBP9- <24>

CLK_KBD <38>
DAT_KBD <38>

DOCK_DCIN_IS+ <48>
DOCK_DCIN_IS- <48>

100K_0402_5%~D

100K_0402_5%~D

R796

R796

1 2

SATA_SBRX_DTX_P3_C <23>
SATA_SBRX_DTX_N3_C <23>

DOCK_DET#

+3.3V_RUN

R795

R795
20K_0402_5%~D

20K_0402_5%~D

1 2
13

D

D

BSS138_SOT23~D

BSS138_SOT23~D

2

G

G

S

S

Q114

Q114

DAI_DI<27>

DAI_DO#<27>

DOCK_DET_1

DPB_DOCK_CA_DET
DPB_DOCK_LANE0_C

DPB_DOCK_LANE0#_C
DPB_DOCK_LANE1_C

DPB_DOCK_LANE1#_C
DPB_DOCK_LANE2_C

DPB_DOCK_LANE2#_C
DPB_DOCK_LANE3_C

DPB_DOCK_LANE3#_C
DPB_DOCK_AUX

DPB_DOCK_AUX#
DPB_DOCK_HPD

BLUE_DOCK

RED_DOCK

GREEN_DOCK

0.1U_0603_50V4Z~D

0.1U_0603_50V4Z~D
C1017

C1017

1

2

2 1

SD05.TCT_SOD323-2~D

SD05.TCT_SOD323-2~D

D65

D65

D23

D23

@

DPB_DOCK_LANE0_C
DPB_DOCK_LANE0#_C
DPB_DOCK_LANE1_C
DPB_DOCK_LANE1#_C

DPB_DOCK_LANE2_C
DPB_DOCK_LANE2#_C

B B

DPB_DOCK_LANE3_C
DPB_DOCK_LANE3#_C

DPB_DOCK_AUX# DPB_DOCK_AUX#
DPB_DOCK_AUX DPB_DOCK_AUX

@

1
2
4
5
3

8

8

RCLAMP0524P.TCT~D

RCLAMP0524P.TCT~D

D25

D25

@

@

1
2
4
5
3

8

8

RCLAMP0524P.TCT~D

RCLAMP0524P.TCT~D

D27

D27

@

@

1
2
4
5
3

8

8

RCLAMP0524P.TCT~D

RCLAMP0524P.TCT~D

DPB_DOCK_LANE0_C

10

DPB_DOCK_LANE0#_C

9

DPB_DOCK_LANE1_C

7

DPB_DOCK_LANE1#_C

6

DPB_DOCK_LANE2_C

10

DPB_DOCK_LANE2#_C

9

DPB_DOCK_LANE3_C

7

DPB_DOCK_LANE3#_C

6

10
9

DPB_DOCK_HPDDPB_DOCK_HPD

7

DPB_DOCK_CA_DETDPB_DOCK_CA_DET

6

Place close to JP1 connector

A A

DOCK_LOM_SPD10LED_GRN#<30>

DPB_DOCK_CA_DET<21>

DPB_DOCK_LANE0_C<21>
DPB_DOCK_LANE0#_C<21>

DPB_DOCK_LANE1_C<21>
DPB_DOCK_LANE1#_C<21>

DPB_DOCK_LANE2_C<21>
DPB_DOCK_LANE2#_C<21>

DPB_DOCK_LANE3_C<21>
DPB_DOCK_LANE3#_C<21>

DPB_DOCK_AUX<21>
DPB_DOCK_AUX#<21>

DPB_DOCK_HPD<21>

BLUE_DOCK<20>

RED_DOCK<20>

GREEN_DOCK<20>

HSYNC_DOCK<20>
VSYNC_DOCK<20>

CLK_MSE<38>

DAT_MSE<38>

DAI_BCLK#<27>
DAI_LRCK#<27>

DAI_12MHZ#<27>

D_LAD0<37>
D_LAD1<37>

D_LAD2<37>
D_LAD3<37>

D_LFRAME#<37>
D_CLKRUN#<37>

D_SERIRQ<37>

D_DLDRQ1#<37>

CLK_PCI_DOCK<6>

DOCK_SMB_CLK<38>

DOCK_SMB_DAT<38>

DOCK_SMB_ALERT#<38>

DOCK_PSID<43>

DOCK_PWR_BTN#<38>

SLICE_BAT_PRES#<37>

+DOCK_PWR_BAR

1

DPC_LANE_P0_C
DPC_LANE_N0_C
DPC_LANE_P1_C
DPC_LANE_N1_C

DPC_LANE_P2_C
DPC_LANE_N2_C DPC_LANE_N2_C
DPC_LANE_P3_C
DPC_LANE_N3_C

DPC_DOCK_AUX_SW
DPC_DOCK_AUX#SW
DPC_DOCK_HP_R DPC_DOCK_HP_R
DPC_CA_DET DPC_CA_DET

+RTC_CELL

R124 100K_0402_5%~DR124 100K_0402_5%~D

12

DPC_DOCK_HPD# <51>

D22

D22

@

@

1
2
4
5
3

8

8

RCLAMP0524P.TCT~D

RCLAMP0524P.TCT~D

D24

D24

@

@

1
2
4
5
3

8

8

RCLAMP0524P.TCT~D

RCLAMP0524P.TCT~D

D26

D26

@

@

1
2
4
5
3

8

8

RCLAMP0524P.TCT~D

RCLAMP0524P.TCT~D

DPC_LANE_P0_C

10

DPC_LANE_N0_C

9

DPC_LANE_P1_C

7

DPC_LANE_N1_C

6

DPC_LANE_P2_C

10
9

DPC_LANE_P3_C

7

DPC_LANE_N3_C

6

DPC_DOCK_AUX_SW

10

DPC_DOCK_AUX#SW

9
7
6

Place close to JP1 connector

CLK_PCI_DOCK

12

R462

@R462

@

10_0402_5%~D

10_0402_5%~D

1

C590

@C590

@

4.7P_0402_50V8C~D

4.7P_0402_50V8C~D

2

Title

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

2

1

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

Date: Sheet

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.
SCHEMATIC, MB A4042

SCHEMATIC, MB A4042

SCHEMATIC, MB A4042

401533

401533

401533

35 56Monday, December 17, 2007

35 56Monday, December 17, 2007

35 56Monday, December 17, 2007

A

A

A

of

of

of

U32A

M7

R6
N5
P5

M6

R5
N6
N7
P6
P7

B5
B4
D6
A4

C5
B3
D5
A3

C4
A2
D4

R13
R14
P14

N11
N12

M11

N13
P13
R15

P8

R7
N15
L14
L15
K15
K14

J14

J15
M10
M15

N14

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

2

C936

C936

1

U32A

LCLK
LPCEN
GPIO_17/LRESET_N
GPIO_18/LFRAME_N
GPIO_19/LSERIRQ
GPIO_20/LAD[0]
GPIO_21/LAD[1]
GPIO_22/LAD[2]
GPIO_23/LAD[3]
GPIO_24/LPCPD_N

GPIO_0/UART_RX
GPIO_1/UART_TX
GPIO_2/UART_CTS
GPIO_3/UART_RTS

GPIO_6/SSP_CLK
GPIO_7/SSP_FSS
GPIO_8/SSP_RXD
GPIO_9/SSP_TXD

GPIO_14
GPIO_15
GPIO_16

USBD_DN
USBD_UP
GPIO_27/USBD_ATATCH

USBH_DN0
USBH_UP0
USBH_OC_0

USBH_DN1
USBH_UP1
USBH_OC_1

GPIO_25/SC_SEL5V
GPIO_26/SC_SEL18V
SC_CINRUSH
SC_CLK
SC_VCC
SC_RST
SC_IO
SC_FCB
SC_FCB_ENB
SC_DET
SC_PWR
SC_PWR

CLK_PCI_TPM<6>

R464

R464
0_0402_5%~D

0_0402_5%~D

SP_TPM_LPC_EN<37>

IRQ_SERIRQ<24,31,37,38>

SP_TPM_LPC_EN<37>

SC_DET

UART_RX/GPIO0

R58

@R58

@

0_0402_5%~D

0_0402_5%~D

1 2

USBP10-<24>

B B

USBP10+<24>

TER_USBH_N1
TER_USBH_P1

BCM5880_SCCLK BCM5880_SCCLK_R

1 2

R486 10M_0402_5%~D

R486 10M_0402_5%~D

@

@

Y3

Y3

4

GND

XI

1

IN

1

27.12MHZ_18PF_9C27100001~D

27.12MHZ_18PF_9C27100001~D
C608

C608
22P_0402_50V8J~D

22P_0402_50V8J~D

2

GND

1 2

PLTRST3#<22,34>

LPC_LFRAME#<23,37,38>

1 2

R842 0_0402_5%~DR842 0_0402_5%~D

LPC_LAD0<23,37,38>
LPC_LAD1<23,37,38>
LPC_LAD2<23,37,38>
LPC_LAD3<23,37,38>

1 2

R466 0_0402_5%~D@R466 0_0402_5%~D@

R849 10K_0402_5%~D

R849 10K_0402_5%~D

R468 22_0402_5%~D

R468 22_0402_5%~D

1 2

R469 22_0402_5%~DR469 22_0402_5%~D

1 2

R470 1.5K_0402_5%~D

R470 1.5K_0402_5%~D

1 2

FP_USBD-<33>
FP_USBD+<33>

R768 22_0402_5%~D

R768 22_0402_5%~D

1 2

R769 22_0402_5%~D

R769 22_0402_5%~D

1 2

3

OUT

2

C600

C600

680P_0402_50V7-K~D

680P_0402_50V7-K~D

1 2

1 2

R472 10_0402_5%~D

R472 10_0402_5%~D

T142

T142

PAD~D

PAD~D

1 2

R481 0_0402_5%~DR481 0_0402_5%~D

1 2

R487

R487
0_0402_5%~D

0_0402_5%~D

XO

1

C609

C609
22P_0402_50V8J~D

22P_0402_50V8J~D

2

12

@

@

+SC_PWR

T171PAD~D T171PAD~D

REF_XOUT

REF_XIN

CLK_PCI_TPM
LPC_EN_R
PLTRST3#
LPC_LFRAME#
IRQ_SERIRQ_R
LPC_LAD0
LPC_LAD1
LPC_LAD2
LPC_LAD3
LPD#

UART_RX/GPIO0
UART_TX/GPIO1
UART_CTS
SC_DET_R

SPI_CLK
SPI_CS
SPI_RXD
SPI_TXD

GPIO14_TER_ON/OFFUART_TX/GPIO1
BCM5880_GPIO15
GPIO16_TER_TRIS

USBP10-_R
USBP10+_R

FP_USBD­FP_USBD+

USBH_OC0#

USBH_N1
USBH_P1
USBH_OC1#

5880_GPIO25
5880_GPIO26

BCM5880_SCVCC
BCM5880_SCRST
BCM5880_IO
AUX1UC
AUX2UC
BCM5880_SCDET

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

2

1

C935

C935

Default setting is CN part

U33

GPIO14_TER_ON/OFF
BCM5880_SCCLK

GPIO16_TER_TRIS SC_USB#
5880_GPIO26
5880_GPIO25
BCM5880_SCRST
BCM5880_SCDET

A A

1

2

+3.3V_RUN

10U_0805_10V4Z~D

10U_0805_10V4Z~D

2

@

@

C958

C958

1

SC_DET

1 2

4.7K_0402_5%~D

4.7K_0402_5%~D

R490 47K_0402_1%~D

R490 47K_0402_1%~D
R766 47K_0402_1%~D R766 47K_0402_1%~D
R767 47K_0402_1%~D R767 47K_0402_1%~D
R770 10K_0402_5%~D

R770 10K_0402_5%~D

R210

R210

12

R771 10K_0402_5%~D

R771 10K_0402_5%~D

T139PAD~D T139PAD~D
T63PAD~D T63PAD~D
T64PAD~D T64PAD~D

8009_VDDMON

1 2
1 2
1 2

12

BCM5880_IO
AUX1UC
AUX2UC

+SC_VCC

0.47U_0402_6.3V4Z~D

0.47U_0402_6.3V4Z~D

C611

C611

SC_RST
SC_CLK
SC_C4

SC_IO
SC_C8

When using the 73S8009C,no-stuff R768,R769,R490
When using the 73S8009CN,stuff R768,R769,R490

12
11

10

9
8
7
6
5
4
3
2
1

U33

24

ON/OFF

7

CLKIN

8

RDY

9

OFF_ACK

11

OFF_REQ

12

CS

13

SC_USB#

4

CMDVCC5#

5

CMDVCC3#

6

RSTIN

32

OFF#

10

TEST1

30

TEST2

1

I/OUC

2

AUX1UC

3

AUX2UC

73S8009CN

73S8009CN

JSC1

JSC1

GND
GND

10
9
8
7
6
5
4
3
2
1

TYCO_1-1734821-0_10P~D

TYCO_1-1734821-0_10P~D

PRES

AUX1
AUX2

GND
GND
GND

Therm_GND

19

VCC

26

VPC

8009_VDDMON

29

VDD

15

VP

+LIN

27

LIN

TER_USBH_N1

23

DM

TER_USBH_P1

25

DP

14

R773 100K_0402_5%~D

R773 100K_0402_5%~D

22

I/O

R491 0_0402_5%~DR491 0_0402_5%~D

21

R493 0_0402_5%~DR493 0_0402_5%~D

20

R492 0_0402_5%~DR492 0_0402_5%~D

16

CLK

R772 0_0402_5%~DR772 0_0402_5%~D

18

RST

17
28
31
33

SPI_TXD
SPI_CLK
SPI_RST

2

BCM5880

BCM5880

LPC

LPC

UARTSPISPISmard Card

UARTSPISPISmard Card

SMC_ADD_15/REFCLK_FREQ_0
SMC_ADD_16/REFCLK_FREQ_1

SMC_ADD_17/BOOT_SRC_0

SMC_ADD_18/BOOT_SR_1

BootStrap

BootStrap

BCM5880KFBG_FBGA225~D

BCM5880KFBG_FBGA225~D

+3.3V_RUN+SC_VCC

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

2

2

C1019

C1019

C920

C920

1

L69 10UH_LQH32CN100K53L_10%~DL69 10UH_LQH32CN100K53L_10%~D

12
1 2
1 2
1 2
1 2

27P_0402_50V8J~D

27P_0402_50V8J~D

2

C633

C633

1

U34

U34

1

D

2

C

3

RESET#

4

S#

M45PE16-VMP6TP_SO8~D

M45PE16-VMP6TP_SO8~D

BCM5880_GPIO15

2

2

1

1

12

8

Q

7

VSS

6

VCC

5

W#

1 2

R341 4.7K_0402_5%~D@R341 4.7K_0402_5%~D@

SMC_ADD_0
SMC_ADD_1
SMC_ADD_2
SMC_ADD_3
SMC_ADD_4
SMC_ADD_5
SMC_ADD_6
SMC_ADD_7
SMC_ADD_8

SMC_ADD_9
SMC_ADD_10
SMC_ADD_11
SMC_ADD_12
SMC_ADD_13
SMC_ADD_14

SMC_ADD_19
SMC_ADD_20
SMC_ADD_21
SMC_ADD_22
SMC_ADD_23

SMC_DATA_0
SMC_DATA_1
SMC_DATA_2
SMC_DATA_3
SMC_DATA_4
SMC_DATA_5
SMC_DATA_6
SMC_DATA_7
SMC_DATA_8
SMC_DATA_9

SMC_DATA_10
SMC_DATA_11
SMC_DATA_12
SMC_DATA_13
SMC_DATA_14
SMC_DATA_15

SMC_ADV_N

SMC_BLS_N_0
SMC_BLS_N_1

SMC_CRE
SMC_CS_N_0
SMC_CS_N_1

SMC_IO_3V

SMC_OE_N

SMC_WE_N

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

1

C620

C620

2

C621

C621

1 2

27P_0402_50V8J~D

27P_0402_50V8J~D

2

C898

C898

1

+3.3V_RUN

1

2

SPI_RXD

BCM5880_GPIO15SPI_CS

H1
J4
H2
H3
G1
H4
F2
G4
G2
G3
E2
F4
F1
F3
D2
E3
D1
E1
C2
D3
C1
E4
B1
C3

R2
P3
R1
P2
R3
M4
N2
N3
P1
M3
M2
L4
N1
L3
L2
K4

K2
J1
K1
J3
M1
K3
P12
J2
L1

10U_0805_10V4Z~D

10U_0805_10V4Z~D

C706

C706

4.7U_0603_6.3V6M~D

4.7U_0603_6.3V6M~D

SC_DET
SC_IO
SC_C4
SC_C8
SC_CLK
SC_RST

1U_0603_10V4Z~D

1U_0603_10V4Z~D

C644

C644

+1.2V_PLL_5880

SMC_ADD15
SMC_ADD16
SMC_ADD17
SMC_ADD18

SPI_RST

1 2

R339

R339

4.7K_0402_5%~D

4.7K_0402_5%~D

+3.3V_RUN

1 2

1 2

R991

R991
0_0402_5%~D

0_0402_5%~D

1 2

T72PAD~D T72PAD~D
T73PAD~D T73PAD~D
T74PAD~D T74PAD~D
T75PAD~D T75PAD~D
T76PAD~D T76PAD~D
T77PAD~D T77PAD~D

+3.3V_RUN

R485

R485

4.7K_0402_5%~D

4.7K_0402_5%~D

SBOOT

R972

@R972

@

4.7K_0402_5%~D

4.7K_0402_5%~D

POR_EXTR

1U_0603_10V4Z~D

1U_0603_10V4Z~D

1U_0603_10V4Z~D

1U_0603_10V4Z~D

1

1

C592

C592

C593

C593

2

2

OVSTB
SCANMOD

T66PAD~D T66PAD~D

SBOOT
SWV
TSTMOD

T68PAD~D T68PAD~D

IDQ_EN

T69PAD~D T69PAD~D

REF_XIN
REF_XOUT

AUX_XIN

T70PAD~D T70PAD~D

AUX_XOUT

T71PAD~D T71PAD~D

RST_N

SPI_RST_R

JTAG_CLK_USH
JTAG_TDI_USH
JTAG_TDO_USH
JTAG_TMS_USH
JTAG_RST#_USH
JTCE_USH

1 2

C594 680P_0402_50V7-K~DC594 680P_0402_50V7-K~D

+3.3V_RUN

R476

R476
510K_0402_5%~D

510K_0402_5%~D

1 2

POR_EXTR

330K_0402_5%~D

330K_0402_5%~D

R488

R488

1 2

+2.5V_AVDD_5880

SC_C4 & SC_C8 is for 90 ohm

CLK_PCI_TPM

10_0402_5%~D

10_0402_5%~D

12

@

@

R744

R744

4.7P_0402_50V8C~D

4.7P_0402_50V8C~D

PCI_TPM_TERM

2

@

@

C589

C589

1

F12
G13
G15
G14

B14
B15
D12
D13
E12
A15

N9
M8
P9

M12

R9

R10
F15

F14
D15

E14

A1
B2

N8
R8

P10
R11
N10
R12
P11

M9

SWV

+3.3V_RUN

BLM18BB100SN1D_0603~D

BLM18BB100SN1D_0603~D
L36

L36

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

2

C624

C624

1

+3.3V_RUN

+3.3V_RUN

U32B

U32B

POR_AVSS
POR_EXTR
POR_INT12
POR_MONITOR

PLL_VDD_1P2I
PLL_AVDD_1P2O
PLL_VSS
PLL_VDD_1P2I
PLL_VSS
NC

OVSTB/ZEROB
SCANACCMODE
SECURE_BOOT
SWV/ERROR,OSC1,OSC2,SPL
TESTMODE/TST_SEC_BOOT
IDDQ_EN/CM3_MODE

REFCLK_XTALIN
REFCLK_XTALOUT

AUXCLK_XTALIN
AUXCLK_XTALOUT

CLKOUT
CLKOUT_EN

RST_N
RSTOUT_N

JTAG_TCK
JTAG_TDI
JTAG_TDO
JTAG_TMS
JTAG_TRSTN
JTCE

BCM5880

BCM5880

HF_RFIDTAG_AVDD2P5
HF_RFIDTAG_AVDD2P5
HF_RFIDTAG_DVDD1P2

HF_RX_ADC_AVDD1P2

HF_RX_AVDD1P2
HF_RX_AVDD2P5

HF_TX_AVDD1P2
HF_TX_AVDD2P5
HF_TX_AVDD3P3

HF_RFIDTAG_AVSS
HF_RFIDTAG_VREF

HF_RFIDTAG_VRX_N

HF_RFIDTAG_VRX_P

HF_RFIDTAG_VTX

HF_RX_TEST0
HF_RX_TEST1
HF_RX_TEST2
HF_RX_TEST3

HF_RX_N

RDIF

RDIF

HF_RX_P

HF_TX_N
HF_TX_P

HF_RFIDTAG_AVSS
HF_RFIDTAG_AVSS

HF_RFIDTAG_DVSS
HF_RX_ADC_AVSS1
HF_RX_ADC_AVSS2

HF_RX_AVSS
HF_RX_AVSS
HF_TX_AVSS
HF_TX_AVSS

JTAG CLK

JTAG CLK

HF_TX_AVSS

BCM5880KFBG_FBGA225~D

BCM5880KFBG_FBGA225~D

LPD#

1 2

R474 4.7K_0402_5%~DR474 4.7K_0402_5%~D

OVSTB

1 2

R484 4.7K_0402_5%~DR484 4.7K_0402_5%~D

TAMPER_N

1 2

R736 4.7K_0402_5%~DR736 4.7K_0402_5%~D

RST_N

1 2

R810 4.7K_0402_5%~DR810 4.7K_0402_5%~D

SMC_ADD16

1 2

R478 4.7K_0402_5%~DR478 4.7K_0402_5%~D

SC_USB#

12

R850 10K_0402_5%~D

R850 10K_0402_5%~D

Function

Boot SRC
REF CLK

+RFID_AVDD2P5

12

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

2

C625

C625

1

1

D28

D28
BAS40-04_SOT23-3~D

BAS40-04_SOT23-3~D

2 3

1

D29

D29
BAS40-04_SOT23-3~D

BAS40-04_SOT23-3~D

2 3

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

R473 10K_0402_5%~D

R473 10K_0402_5%~D
R483 4.7K_0402_5%~D@R483 4.7K_0402_5%~D@
R737 1K_0402_5%~D

R737 1K_0402_5%~D
R479 4.7K_0402_5%~D R479 4.7K_0402_5%~D

00 01 10 11

SSMC

AD[18:17]

SMC SPI RVDUSB

AD[16:15]

RVD

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

+1.2V_AVDD_5880 +3.3V_RUN

C626

C626

1

2

1

2

1

2

1

2

BBCLK

1 2

LPC_EN_R

1 2

JTAG_RST#_USH

1 2

SMC_ADD15

1 2

24MHZ 27.12MHz 48MHz

BLM18BB100SN1D_0603~D

BLM18BB100SN1D_0603~D

12

L37

L37

1U_0603_10V4Z~D

1U_0603_10V4Z~D

C627

C627

RFREADER_RXN

150P_0402_50V8J~D

150P_0402_50V8J~D

RFREADER_TXN1

@ C641

@

RFTAG_VRXN ANT_RFTAG_VRXN_R

C641

RFTAG_VRXP
RFREADER_RXP
RFREADER_TXP1

150P_0402_50V8J~D

150P_0402_50V8J~D

@ C647

@

C647

+RFID_AVDD2P5

A7
F7

+RFID_AVDD1P2

C6
E10
F9

C595 close to Pin A6

G9
D8
A8

+RFID_AVDD3P3

D9

B6
A6
C7
B7
E7
B10
C10
A11
A12
C11
B11
C9
B9

C8
D7
A5
E9
G10
F10
A10
A9
B8
E8

+RFID_AVDD1P2 +RFID_AVDD3P3

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

2

1

C628

C628

+3.3V_RUN

C595

C595

0.01U_0402_25V7K~D

0.01U_0402_25V7K~D

1 2

RFTAG_VRXN
RFTAG_VRXP

RFREADER_RXN
RFREADER_RXP
RFREADER_TXN1
RFREADER_TXP1

SMC_ADD18
SMC_ADD17
USBH_OC0#
USBH_OC1#

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

1

2

1 2

R494 3K_0402_1%~D

R494 3K_0402_1%~D

1 2

R495 1_0402_5%~D

R495 1_0402_5%~D

1 2

R496 4.12K_0402_1%~D

R496 4.12K_0402_1%~D

1 2

R497 4.12K_0402_1%~D

R497 4.12K_0402_1%~D

1 2

R498 3K_0402_1%~D

R498 3K_0402_1%~D

1 2

R499 1_0402_5%~D

R499 1_0402_5%~D

R471 0_0402_5%~D

R471 0_0402_5%~D

+3.3V_RUN

+3.3V_RUN

1 2

1 2

BLM18BB100SN1D_0603~D

BLM18BB100SN1D_0603~D
L38

L38

3.3U_0603_10V4Z~D

3.3U_0603_10V4Z~D

1

C629

C629

2

+1.2V_VDDC_5880

+3.3V_RUN

BBCLK

12

TAMPER_N
+VDD_BBL

4.7K_0402_5%~D

4.7K_0402_5%~D

4.7K_0402_5%~D

4.7K_0402_5%~D

@R475

@

R475

R819

R819

1 2

4.7K_0402_5%~D

4.7K_0402_5%~D

4.7K_0402_5%~D

4.7K_0402_5%~D

R820

R820

@R482

@

R482

1 2

Pull-downs for 5880
Rev A0, and pull-ups
for Rev B0

12

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

2

C630

C630

1

C639 1U_0603_10V4Z~D

C639 1U_0603_10V4Z~D

1 2

C640 1U_1206_100V4Z~D

C640 1U_1206_100V4Z~D
C642 1U_1206_100V4Z~D

C642 1U_1206_100V4Z~D
C643 1U_0603_10V4Z~D

C643 1U_0603_10V4Z~D

CONTACTLESS_DET#<24>

1 2

1 2

C631

C631

1 2
1 2
1 2

C13

E5
F5

J11

K11

K6
K7
K9
N4
P4

E6
F6

G5
H5

J5

K8

L7

K5

L5
L6

L13

M14

K13
H14
H15
H13
H12

J13

L8

L9
L10
L11

4.7K_0402_5%~D

4.7K_0402_5%~D

@R844

@

R844

4.7K_0402_5%~D

4.7K_0402_5%~D
R846

R846

1

U32C

U32C

BCM5880

BCM5880

VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC

VDDO_VAR
VDDO_VAR

VDDO_SMC
VDDO_SMC
VDDO_SMC

VDDO_LPC
VDDO_LPC

VDDO_33CORE
VDDO_33CORE
VDDO_33CORE

VDDO_33SC
VDDO_33SC
VDDO_SC

V3P3_BBLCLK
V3P3_PWRGOOD
V3P3_TAMPER_N
VDD_BB

VDD_BB
VESD
VDDO_33

VDDO_33
VDDO_33

4.7K_0402_5%~D

4.7K_0402_5%~D

@R845

@

R845

1 2

4.7K_0402_5%~D

4.7K_0402_5%~D
R847

R847

1 2

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

1

C632

C632

2

1

1 2

CORE_CINRUSH

CORE_PWRDN

ALDO_PWRDN

AVDD33_LDO25

AVDD_2P5I

AVDD_2P5O
AVDD25_ldo12
AVDD25_ldo12

AVDD_1P2O

AVDD_1P2I_AUX
AVDD_1P2I_REF

AVDD25_PLL

OTP_PWR

AVSS_LDO12

AVSS_ldo25

AVSS_ldo25

AVSS_AUX

AVSS_REF

AVSS_PLL

BCM5880KFBG_FBGA225~D

BCM5880KFBG_FBGA225~D

+1.2V_AVDD_5880 +2.5V_AVDD_5880

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

2

C601

C601

1

+3.3V_RUN

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

2

2

C612

C612

1

1

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

2

2

C635

C635

1

1

CONTACTLESS_DET#

R4
M5
D10
A14
G12
B13
A13
B12
E11
E13
F13
D14
P15

F11
C12
D11
C15
E15
C14

G11

VSS

G6

VSS

G7

VSS

G8

VSS

H10

VSS

H11

VSS

H6

VSS

H7

VSS

H8

VSS

H9

VSS

J10

VSS

J12

VSS

J6

VSS

J7

VSS

J8

VSS

J9

VSS

K10

VSS

K12

VSS

L12

VSS

M13

VSS

F8

VSS

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

2

C602

C602

1

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

2

C613

C613

C614

C614

1

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

2

C637

C637

C636

C636

1

ANT_RFTAG_VRXP_R
ANTENNA_P_C

C591 680P_0402_50V7-K~DC591 680P_0402_50V7-K~D

1 2

R463 2.2K_0402_5%~D

R463 2.2K_0402_5%~D

1 2

R465 4.7K_0402_5%~DR465 4.7K_0402_5%~D

+2.5V_AVDD_5880
+3.3V_RUN
+1.2V_AVDD_5880
+1.2V_PLL_5880

R467 0_0603_5%~D

R467 0_0603_5%~D

@

@

R829 0_0603_5%~D

R829 0_0603_5%~D

+1.2V_VDDC_5880

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

2

1

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

2

1

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

2

2

C605

C605

1

1

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

2

C615

C615

C616

C616

1

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

2

C638

C638

C875

C875

1

2

C596

C596

1

2

C873

C873

1

2

C606

C606

1

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

2

C617

C617

1

4.7U_0603_6.3V6M~D

4.7U_0603_6.3V6M~D

1

C930

C930

2

1
2
3
4
5
6

7
8

MOLEX_53780-0670~D

MOLEX_53780-0670~D

+OTP_PWR

2

1

2

1

12
12

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

JCS1

JCS1

1
2
3
4
5
6

GND
GND

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

Date: Sheet

Compal Electronics, Inc.
SCHEMATIC, MB A4042

SCHEMATIC, MB A4042

SCHEMATIC, MB A4042

401533

401533

401533

+3.3V_RUN
+SC_PWR

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

2

C597

C597

C598

C598

1

4.7U_0603_6.3V6M~D

4.7U_0603_6.3V6M~D

1

@

@

C933

C933

C877

C877

2

4.7U_0603_6.3V6M~D

4.7U_0603_6.3V6M~D

1

@

@

C607

C607

C934

C934

2

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

2

2

C618

C618

1

1

4.7U_0603_6.3V6M~D

4.7U_0603_6.3V6M~D

1

C931

C931

2

4.7U_0603_6.3V6M~D

4.7U_0603_6.3V6M~D

1

2

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

2

C599

C599

1

C619

C619

36 56Monday, December 17, 2007

36 56Monday, December 17, 2007

36 56Monday, December 17, 2007

C932

C932

Place
close
to
pinA14

of

of

of

A

A

A

+3.3V_ALW

5

4

3

2

1

1 2

R501 10K_0402_5%~D

R501 10K_0402_5%~D

1 2

R502 10K_0402_5%~D

R502 10K_0402_5%~D

1 2

R503 100K_0402_5%~D

R503 100K_0402_5%~D

1 2

R504 100K_0402_5%~D

R504 100K_0402_5%~D

1 2

R909 100K_0402_5%~D

R909 100K_0402_5%~D

D D

1 2

R988 100K_0402_5%~D

R988 100K_0402_5%~D

1 2

R951 100K_0402_5%~DR951 100K_0402_5%~D

1 2

R704 100K_0402_5%~DR704 100K_0402_5%~D

remove the circuit, No need for BIOS

C C

ITP_DBRESET#<7,24>

LCD_TST<19>

B B

BID2 BID1 BID0

000
0
0
0
0
1

A A

1 2

BID0
BID1
BID2
CHIPSET_ID0
CHIPSET_ID1

PCIE_WAKE#
USB_SIDE_EN#
SLICE_BAT_PRES# PANEL_BKEN_GPU
USB_POWERSHARE_PWR_EN#
DCIN_CBL_DET#
ESATA_USB_PWR_EN#
CELL_CHARGER_DET#
PWR_BTN_BD_DET#

USB_POWERSHARE_PWR_EN#<33>

MDC_RST_DIS#<33>

1 2

R517 0_0402_5%~D@ R517 0_0402_5%~D@

R969 10K_0402_5%~D@R969 10K_0402_5%~D@

R816 100K_0402_5%~D

R816 100K_0402_5%~D
R505 100K_0402_5%~D

R505 100K_0402_5%~D

+3.3V_RUN

R913 100K_0402_5%~D

R913 100K_0402_5%~D
R788 10K_0402_5%~D

R788 10K_0402_5%~D

PBAT_PRES#<43>

SCRL_LED#<42>

NUM_LED#<42>

DCIN_CBL_DET#<43>

PBATT_OFF<49>

PCIE_WAKE#<32,34>

WIRELESS_ON/OFF#<31>
WPAN_RADIO_DIS#<34>
EXPRCRD_PWREN#<32>
EXPRCRD_STDBY#<32>

BC_INT#_ECE5028<38>
BC_DAT_ECE5028<38>
BC_CLK_ECE5028<38>

QUAD_DET<7>

QUAD_REF_EN<7>

EXPRCRD_DET#<32>

USB_SIDE_EN#<33>

EN_I2S_NB_CODEC<27>

CB_HWSPND#<31>

EN_DOCK_PWR_BAR<49>

PSID_DISABLE#<43>

PANEL_BKEN_GPU<51>

DOCK_DET#<21,35>

AUD_NB_MUTE<28>

CELL_CHARGER_DET#<33>

LCD_VCC_TEST_EN<19>
CCD_OFF<19>

AUD_HP_NB_SENSE<27,28,33>

ESATA_USB_PWR_EN#<33>

1.05V_RUN_ON<40>
GFX_CORE_ON<50>

INSTANT_ON_SW#<31,38>

SLICE_BAT_PRES#<35>
PWR_BTN_BD_DET#<31>

LAN_PHY_PWR_CNTRL<24,29>

CAP_LED#<42>

SYS_LED_MASK#<42>

GFX_OPEN_GL_EN<51>

SIO_EXT_WAKE#<24>

ICH_PME#<22>

ICH_PCIE_WAKE#<24>

WLAN_RADIO_DIS#<34>

WWAN_RADIO_DIS#<34>

REV

X00

00

X01
X02

1

0
1
11

X03

0

A00

00

10K_0402_5%~D

10K_0402_5%~D

10K_0402_5%~D

10K_0402_5%~D

10K_0402_5%~D

@R530

@

@ R529

@

R530

R529

1 2

10K_0402_5%~D

10K_0402_5%~D

10K_0402_5%~D

@ R532

@

@R531

@

R532

R531

1 2

1 2

5

+3.3V_ALW

10K_0402_5%~D

10K_0402_5%~D

@ R533

@

R533

1 2

1 2

R534 10K_0402_5%~D

R534 10K_0402_5%~D

1 2

R535 10K_0402_5%~D

R535 10K_0402_5%~D

1 2

R536 10K_0402_5%~D

R536 10K_0402_5%~D

1 2

R537 10K_0402_5%~D

R537 10K_0402_5%~D

1 2

R538 10K_0402_5%~D

R538 10K_0402_5%~D

SP_TPM_LPC_EN

1 2
1 2

12

1 2

SP_TPM_LPC_EN

@

@

1 2

T42PAD~D T42PAD~D

USB_POWERSHARE_PWR_EN#

T161PAD~D T161PAD~D

ADAPT_OC<48>

DOCKED<30>

HDDC_EN<26>
MODC_EN<26>

R526 0_0402_5%~D

R526 0_0402_5%~D

CHIPSET_ID1

LCD_TST

WIRELESS_ON/OFF#

PBAT_PRES#

DCIN_CBL_DET#
PBATT_OFF
PNL_LED_MASK#
PCIE_WAKE#

WIRELESS_ON/OFF#
WPAN_RADIO_DIS#
EXPRCRD_PWREN#
EXPRCRD_STDBY#
BC_INT#_ECE5028
BC_DAT_ECE5028
BC_CLK_ECE5028

QUAD_DET
QUAD_REF_EN
EXPRCRD_DET#
MDC_RST_DIS#
BIOS_RECOVERY

USB_SIDE_EN#
EN_I2S_NB_CODEC
CB_HWSPND#
EN_DOCK_PWR_BAR
ADAPT_OC

LCD_TST
PSID_DISABLE#
PANEL_BKEN_GPU
DOCKED
DOCK_DET#
AUD_NB_MUTE
CELL_CHARGER_DET#
LCD_VCC_TEST_EN
CCD_OFF
AUD_HP_NB_SENSE
ESATA_USB_PWR_EN#

LID_CL_SIO#

1.05V_RUN_ON
GFX_CORE_ON

INSTANT_ON_SW#
HDDC_EN

MODC_EN
SLICE_BAT_PRES#

PWR_BTN_BD_DET#

SYS_LED_MASK#
GFX_OPEN_GL_EN

1 2

ICH_PME#
ICH_PCIE_WAKE#
WLAN_RADIO_DIS#

WWAN_RADIO_DIS#

VGA_IDENTIFY
CHIPSET_ID1

R528

R528

10K_0402_5%~D

10K_0402_5%~D

CHIPSET_ID0
BID2
BID1
BID0

0
0
1
1

4

12

CHIPSET_ID0

0
1
0
1

U35

U35

97

GPIOA[0]

98

GPIOA[1]

99

GPIOA[2]

100

GPIOA[3]

101

GPIOA[4]

102

GPIOA[5]

103

GPIOA[6]

104

GPIOA[7]

24

GPIOH[0]

25

GPIOH[1]

26

GPIOH[4]

27

GPIOH[5]

58

BC_INT#

59

BC_DAT

60

BC_CLK

1

GPIOE[0]/RXD

2

GPIOE[1]/TXD

3

GPIOE[2]/RTS#

4

GPIOE[3]/DSR#

5

GPIOE[4]/CTS#

84

GPIOE[5]/DTR#

83

GPIOE[6]/RI#

6

GPIOE[7]/DCD#

65

GPIOB[0]/INIT#

66

GPIOB[1]/SLCTIN#

67

GPIOC[2]/SCLT

68

GPIOC[3]/PE

69

GPIOC[4]/BUSY

70

GPIOC[5]/ACK#

71

GPIOC[6]/ERROR#

73

GPIOC[7]/ALF#

74

GPIOD[0]/STROBE#

75

GPIOC[1]/PD7

76

GPIOC[0]/PD6

77

GPIOB[7]/PD5

78

GPIOB[6]/PD4

79

GPIOB[5]/PD3

80

GPIOB[4]/PD2

81

GPIOB[3]/PD1

82

GPIOB[2]/PD0

61

GPIOD[1]

62

GPIOD[2]

63

GPIOD[3]/VBUS_DET

28

GPIOD[4]/OCS1_N

29

GPIOD[5]/OCS2_N

30

GPIOD[6]/OCS3_N

31

GPIOD[7]/OCS4_N

32

GPIOH[6]

33

GPIOH[7]

88

GPIOG[0]

89

GPIOG[1]

90

GPIOG[2]

91

GPIOG[3]

92

GPIOG[4]

93

GPIOG[5]

94

GPIOG[6]

95

GPIOG[7]

106

SYSOPT1/GPIOH[2]

107

SYSOPT0/GPIOH[3]

109

GPIOF[7]

110

GPIOF[6]

111

GPIOF[5]

112

GPIOF[4]

113

IRTX

114

IRRX

115

GPIOF[3]/IRMODE/IRRX3B

116

GPIOF[2]/IRTX2

117

GPIOF[1]/IRRX2

118

GPIOF[0]/IRMODE/IRRX3A

ECE5028-NU_VTQFP128_14X14~D

ECE5028-NU_VTQFP128_14X14~D

ECE5028-NU

ECE5028-NU

Roush-I Foose-I

Roush-A

SmFF

Nike

+3.3V_ALW

34

57

85

108

VCC1

VCC1

VCC1

VCC1

(ECE5018)

(ECE5018)

USB

USB

TEST

GPIO

GPIO

TEST

CLK

CLK

LPC

LPC

DLPC

DLPC

1

C648

C648

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

2

CAP_LDO

TEST_PIN

LAD0
LAD1
LAD2
LAD3

LFRAME#

LRESET#

PCICLK

CLKRUN#

LDRQ0#
LDRQ1#

SER_IRQ

DLAD0
DLAD1
DLAD2
DLAD3

DLFRAME#

DCLK_RUN#

DLDRQ1#

DSER_IRQ

PWRGD

OUT65

VSS

VSS
VSS

VSS
VSS
VSS
VSS

8
14
20

119
9

10
13
12
15
16
19
18
21
22

125
124
120
86
127

35

126
123

122

54
52
49
47
42
41
56
37
46
44
39

64
96
55

53
50
48
43
38
45
40

7
105

11
17
23
36
51
72
87
121
128

R509 0_0402_5%~DR509 0_0402_5%~D

+CAP_LDO

TP_DET#

VCC1(VDDA33)

GPIOJ[7](VDDA33)

GPIOK[4](VDDA33)

GPIOI[1](VCC1)

GPIOJ[2](USBDP0)
GPIOJ[3](USBDN0)
GPIOJ[6](USBDP1)

GPIOJ[5](USBDN1)
GPIOK[0](USBDP2)
GPIOK[1](USBDN2)
GPIOK[3](USBDP3)
GPIOK[2](USBDN3)
GPIOK[5](USBDP4)
GPIOK[6](USBDN4)

GPIOI[6](VDDA33PLL)
GPIOI[5](VDDA18PLL)

GPIOI[2](VDD18)

GPIOJ[0](RBIAS)

GPIOI[7](ATEST)

GPIOI[4](XTAL1/CLKIN)

GPIOI[3](XTAL2)

CLKI (14.318 MHz)

GPIOJ[4](VSS)

GPIOK[7](VSS)

GPIOJ[1](VSS)

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

DOCK_MIC_DET

1.8V_RUN_ON
SNIFFER_BLUE#

SNIFFER_YELLOW#
DOCK_HP_DET
CRT_SWITCH
ME_FWP
NB_AC_OFF

RUN_ON

1.5V_RUN_ON

1 2

0.9V_DDR_VTT_ON

8mil

DP_MB_EN

R514

R514
1K_0402_5%~D

1K_0402_5%~D

3.3V_RUN_ON

LPC_LAD0
LPC_LAD1
LPC_LAD2
LPC_LAD3
LPC_LFRAME#
PLTRST2#
CLK_PCI_5028
CLKRUN#
LPC_LDRQ0#
LPC_LDRQ1#
IRQ_SERIRQ

CLK_SIO_14M

D_LAD0
D_LAD1
D_LAD2
D_LAD3
D_LFRAME#
D_CLKRUN#
D_DLDRQ1#
D_SERIRQ

RUNPWROK

1

C657

C657

4.7U_0603_6.3V4Z~D

4.7U_0603_6.3V4Z~D

2

1

C652

C652

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

2

12

TP_DET# <39>

DOCK_MIC_DET <27>

DOCK_HP_DET <27>

DP_PRIORITY <21>

DP_MB_EN <21>

DOCK_AC_OFF <35>

RUNPWROK <38,41,47>
SP_TPM_LPC_EN <36>

GPIO_PSID_SELECT <43>

1

C649

C649

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

2

MCH_TSATN_EC <10>

T81 PAD~DT81 PAD~D

SNIFFER_BLUE# <42>

SNIFFER_YELLOW# <42>
CRT_SWITCH <20>

ME_FWP <23>

NB_AC_OFF <43,49>

2.5V_RUN_PWRGD <18,41>

RUN_ON <19,28,40,41,50>

1.5V_RUN_ON <45>
IMVP_VR_ON <47>

IMVP_PWRGD <24,41,47>

0.9V_DDR_VTT_ON <46>

SIO_SLP_S3# <24>

3.3V_RUN_ON <40>

LPC_LAD[0..3] <23,36,38>

LPC_LFRAME# <23,36,38>
PLTRST2# <22,38>
CLK_PCI_5028 <6>

CLKRUN# <24,31,38>

LPC_LDRQ0# <23>

LPC_LDRQ1# <23>

IRQ_SERIRQ <24,31,36,38>

CLK_SIO_14M <6>

D_LAD0 <35>

D_LAD1 <35>

D_LAD2 <35>

D_LAD3 <35>

D_LFRAME# <35>

D_CLKRUN# <35>

D_DLDRQ1# <35>

D_SERIRQ <35>

2

+3.3V_ALW

1

2

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

VGA_IDENTIFY
SNIFFER_BLUE#
SNIFFER_YELLOW#
TP_DET#

D_CLKRUN#
D_SERIRQ
D_DLDRQ1#

RUN_ON

1.5V_RUN_ON

1.05V_RUN_ON

3.3V_RUN_ON

0.9V_DDR_VTT_ON
PBATT_OFF

GFX_CORE_ON

R648

R648
10K_0402_5%~D

10K_0402_5%~D

R649

@R649

@

10K_0402_5%~D

10K_0402_5%~D

4.7P_0402_50V8C~D

4.7P_0402_50V8C~D

10_0402_5%~D

10_0402_5%~D

1

C651

C651

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

2

1 2

R522 100K_0402_5%~D

R522 100K_0402_5%~D
R507 100K_0402_5%~D@ R507 100K_0402_5%~D@
R508 100K_0402_5%~D@R508 100K_0402_5%~D@
R756 100K_0402_5%~DR756 100K_0402_5%~D

R510 100K_0402_5%~D

R510 100K_0402_5%~D
R511 100K_0402_5%~D

R511 100K_0402_5%~D
R512 100K_0402_5%~D

R512 100K_0402_5%~D

R515 100K_0402_5%~D

R515 100K_0402_5%~D
R516 100K_0402_5%~D

R516 100K_0402_5%~D
R518 100K_0402_5%~D

R518 100K_0402_5%~D
R519 100K_0402_5%~D

R519 100K_0402_5%~D
R520 100K_0402_5%~D

R520 100K_0402_5%~D
R521 100K_0402_5%~D R521 100K_0402_5%~D

1 2

R523 100K_0402_5%~D

R523 100K_0402_5%~D

CLK_PCI_5028

R527

@ R527

@

10_0402_5%~D

10_0402_5%~D

C656

@ C656

@

R525

R525

LID_CL#

12

12
12
12

12
12
12

12
12
12
12
12
12

12

1

4.7P_0402_50V8C~D

4.7P_0402_50V8C~D

2

+3.3V_ALW

+3.3V_RUN

CLK_SIO_14M

R506

@R506

@

10_0402_5%~D

10_0402_5%~D

C654

@C654

@

LID_CL# <31,42>

12

1

2

1

C650

C650

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

2

C653

C653

+3.3V_RUN

ME_FWP

LID_CL_SIO#

1 2

1 2

+3.3V_ALW

12

R524

R524
1M_0402_5%~D

1M_0402_5%~D

1

C655

C655

0.047U_0402_16V4Z~D

0.047U_0402_16V4Z~D

2

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

Date: Sheet

Compal Electronics, Inc.
SCHEMATIC, MB A4042

SCHEMATIC, MB A4042

SCHEMATIC, MB A4042

401533

401533

401533

37 56Monday, December 17, 2007

37 56Monday, December 17, 2007

37 56Monday, December 17, 2007

1

A

A

A

of

of

of

5

+3.3V_ALW

D D

C C

JDEG1

JDEG1

5

5

4

4

3

3

2

2

1

1

Molex_53261

Molex_53261

B B

JP2

@JP2

@

7

G1

8

G2

ACES_85204-06001~D

ACES_85204-06001~D

32 KHz Clock

MEC5035_XTAL1

MEC5035_XTAL2

A A

CKG_SMBDAT

1 2

R540 2.2K_0402_5%~D R540 2.2K_0402_5%~D
R542 2.2K_0402_5%~D R542 2.2K_0402_5%~D
R543 100K_0402_5%~D

R543 100K_0402_5%~D
R545 100K_0402_5%~DR545 100K_0402_5%~D
R546 100K_0402_5%~DR546 100K_0402_5%~D
R547 10K_0402_5%~D R547 10K_0402_5%~D
R548 8.2K_0402_5%~D

R548 8.2K_0402_5%~D
R549 8.2K_0402_5%~D

R549 8.2K_0402_5%~D
R551 2.2K_0402_5%~D

R551 2.2K_0402_5%~D
R552 2.2K_0402_5%~D

R552 2.2K_0402_5%~D
R553 10K_0402_5%~D R553 10K_0402_5%~D
R557 100K_0402_5%~DR557 100K_0402_5%~D
R558 100K_0402_5%~DR558 100K_0402_5%~D
R837 100K_0402_5%~D@R837 100K_0402_5%~D@
R838 2.2K_0402_5%~D R838 2.2K_0402_5%~D
R839 2.2K_0402_5%~D R839 2.2K_0402_5%~D
R959 10K_0402_5%~D R959 10K_0402_5%~D

R561 1M_0402_5%~D R561 1M_0402_5%~D

1 2

R563 2.7K_0402_5%~D

R563 2.7K_0402_5%~D

1 2

R564 100K_0402_5%~D

R564 100K_0402_5%~D

1 2

R566 100K_0402_5%~D

R566 100K_0402_5%~D

1 2

R568 100K_0402_5%~D

R568 100K_0402_5%~D

1
2
3
4
5
6

CKG_SMBCLK

1 2

BC_DAT_ECE5028

1 2

BC_DAT_EMC4002

12

BC_DAT_ECE1077

12

DOCK_SMB_ALERT#

12

LCD_SMBCLK

1 2

LCD_SMBDAT

1 2

PBAT_SMBDAT

1 2

PBAT_SMBCLK

1 2

HOST_DEBUG_RX

12

BC_DAT_ECE1088

12

EC_SPI_CS#

12

LPC_LDRQ#_MEC5035

12
1 2
1 2

12

M_ON

12

AUX_ON
DDR_ON
SUS_ON
ICH_ALW_ON

+3.3V_ALW

100K_0402_5%~D

100K_0402_5%~D

12

R574

R574

MSDATA
MSCLK

1 2

R577 0_0402_5%~D

R577 0_0402_5%~D

+3.3V_ALW

10K_0402_5%~D

10K_0402_5%~D

49.9_0402_1%~D

49.9_0402_1%~D

12

12

R580

R580

1
2
3
4
5
6

CARD_SMBDAT
CARD_SMBCLK
HOST_DEBUG_TX

R581

R581

Same as Laguna

Y4

Y4

32.768K_12.5P_1TJS125DJ4A420P~D

32.768K_12.5P_1TJS125DJ4A420P~D

14
23

22P_0402_50V8J~D

22P_0402_50V8J~D

1

C674

C674

2

Remove ECE1088 (2007/10/29)

10K_0402_5%~D

10K_0402_5%~D

10K_0402_5%~D

10K_0402_5%~D

12

12

R575

R575

R576

R576

HOST_DEBUG_RX

10K_0402_5%~D

10K_0402_5%~D

10K_0402_5%~D

10K_0402_5%~D

10K_0402_5%~D

10K_0402_5%~D

12

12

R583

R583

R582

R582

R584

R584

1 2

JTAG_TDI
JTAG_TMS
JTAG_CLK
JTAG_TDO

Place closely pin 58

CLK_PCI_5035

10_0402_5%~D

10_0402_5%~D

4.7P_0402_50V8C~D

C675

C675

4.7P_0402_50V8C~D

22P_0402_50V8J~D

22P_0402_50V8J~D

1

2

@ R588

@

@ C673

@

R588

C673

PBAT_SMBDAT<43>
PBAT_SMBCLK<43>

ACAV_IN_DOCK#<35,49>

KYBRD_BKLT_PWM<39>

BC_CLK_EMC4002<18>
BC_DAT_EMC4002<18>
BC_INT#_EMC4002<18>

BC_INT#_ECE1077<39>
BC_DAT_ECE1077<39>

BC_CLK_ECE1077<39>
BC_INT#_ECE5028<37>

BC_DAT_ECE5028<37>
BC_CLK_ECE5028<37>

EC_32KHZ_OUT<18>

12

1

2

CLK_TP_SIO<39>
DAT_TP_SIO<39>
CLK_KBD<35>
DAT_KBD<35>
CLK_MSE<35>
DAT_MSE<35>

SUS_ON<40,41>

BREATH_LED#<35,42>
ICH_ALW_ON<40>

SIO_EXT_SMI#<24>

SIO_RCIN#<23>

IRQ_SERIRQ<24,31,36,37>

PLTRST2#<22,37>

CLK_PCI_5035<6>

LPC_LFRAME#<23,36,37>

LPC_LAD0<23,36,37>
LPC_LAD1<23,36,37>
LPC_LAD2<23,36,37>
LPC_LAD3<23,36,37>
CLKRUN#<24,31,37>
SIO_EXT_SCI#<24>

MEC5035_XTAL2

4

+RTC_CELL

DAT_TP_SIO
CLK_KBD
DAT_KBD
CLK_MSE
DAT_MSE
PBAT_SMBDAT
PBAT_SMBCLK

JTAG_TDI
JTAG_TDO
JTAG_CLK
JTAG_TMS
JTAG_RST#

SUS_ON
BREATH_LED#

ICH_ALW_ON
EC_SPI_CS#

BC_CLK_EMC4002
BC_DAT_EMC4002
BC_INT#_EMC4002

BC_DAT_ECE1088

BC_INT#_ECE1077
BC_DAT_ECE1077
BC_CLK_ECE1077
BC_INT#_ECE5028
BC_DAT_ECE5028
BC_CLK_ECE5028

SIO_EXT_SMI#
SIO_RCIN#
LPC_LDRQ#_MEC5035
IRQ_SERIRQ
PLTRST2#
CLK_PCI_5035
LPC_LFRAME#
LPC_LAD0
LPC_LAD1
LPC_LAD2
LPC_LAD3
CLKRUN#
SIO_EXT_SCI#

MEC5035_XTAL1

12

R587 0_0402_5%~D

R587 0_0402_5%~D

1 2

R544

R544
0_0402_5%~D

0_0402_5%~D

U36

U36

PS/2 INTERFACE

PS/2 INTERFACE

9

GPIO007/I2C1D_DATA/PS2_CLK0B

10

GPIO010/I2C1D_CLK/PS2_DAT0B

75

GPIO110/PS2_CLK2/GPTP-IN6

76

GPIO111/PS2_DAT2/GPTP-OUT6

77

GPIO112/PS2_CLK1A

78

GPIO113/PS2_DAT1A

79

GPIO114/PS2_CLK0A

80

GPIO115/PS2_DAT0A

111

GPIO154/I2C1C_DATA/PS2_CLK1B

112

GPIO155/I2C1C_CLK/PS2_DAT1B

JTAG INTERFACE

JTAG INTERFACE

102

GPIO145/I2C1K_DATA/JTAG_TDI

103

GPIO146/I2C1K_CLK/JTAG_TDO

105

GPIO147/I2C1J_DATA/I2C2C_DATA/JTAG_CLK

106

GPIO150/I2C1J_CLK/I2C2C_CLK/JTAG_TMS

107

JTAG_RST#

FAN PWM & TACH

FAN PWM & TACH

41

GPIO050/FAN_TACH1

42

GPIO051/FAN_TACH2

43

GPIO052/FAN_TACH3

45

GPIO053/PWM0

46

GPIO054/PWM1

47

GPIO055/PWM2

48

GPIO056/PWM3

BC-LINK

BC-LINK

23

GPIO022/BCM_B_CLK/V_CLK

24

GPIO023/BCM_B_DAT/V_DATA

25

GPIO024/BCM_B_INT#/V_FRAME

35

GPIO042/BCM_C_INT#

36

GPIO043/BCM_C_DAT

37

GPIO044/BCM_C_CLK

38

GPIO045/LSBCM_D_INT#

39

GPIO046/LSBCM_D_DAT

40

GPIO047/LSBCM_D_CLK

85

GPIO121/BCM_A_INT#

86

GPIO122/BCM_A_DAT

87

GPIO123/BCM_A_CLK

HOST INTERFACE

HOST INTERFACE

11

GPIO011/nSMI

54

GPIO061/LPCPD#

55

LDRQ#

56

SER_IRQ

57

LRESET#

58

PCI_CLK

59

LFRAME#

60

LAD0

61

LAD1

62

LAD2

63

LAD3

64

CLKRUN#

66

GPIO100/nEC_SCI

MASTER CLOCK

MASTER CLOCK

122

XTAL1

124

XTAL2

117

GPIO160/32KHZ_OUT

L39

BLM18AG121SN1D_0603~D

BLM18AG121SN1D_0603~D

L39

+RTC_CELL_VBAT

1

C660

C660

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

2

AGND

VSS[1]26VSS[2]51VSS[3]74VSS[4]88VSS[5]

125

15mil

+5035_AGND

12

+3.3V_ALW

121

VBAT

20

113

116

104

VTR[1]21VTR[2]44VTR[3]65VTR[4]83VTR[5]

GPIO012/I2C1H_DATA/I2C2D_DATA

GPIO141/I2C1F_DATA/I2C2B_DATA

VSS[7]

VSS[8]

VR_CAP[1]22VSS_RO

53

101

+5035_VSS

+VR_CAP

1

8mil

C671

C671

2

4.7U_0603_6.3V4Z~D

4.7U_0603_6.3V4Z~D

3

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

C661

C661

1

1

2

2

52

VTR[6]

VTR[7]4VTR[8]

MISC INTERFACE

MISC INTERFACE

GPIO021/RC_ID

GPIO025/UART_CLK

VCC_PRWGD

GPIO060/KBRST

GPIO101/ECGP_SCLK

GPIO102/ECGP_SOUT

GPIO103/ECGP_SIN

GPIO104/UART_TX

GPIO105/UART_RX

GPIO106/nRESET_OUT

GPIO116/MSDATA

GPIO117/MSCLK

GPIO127/A20M
GPIO153/LED3
GPIO156/LED1
GPIO157/LED2

GENERAL PURPOSE I/O

GENERAL PURPOSE I/O

SMBUS INTERFACE

SMBUS INTERFACE

GPIO013/I2C1H_CLK/I2C2D_CLK

GPIO142/I2C1F_CLK/I2C2B_CLK

DELL PWR SW INF

DELL PWR SW INF

129

15mil

GPIO001
GPIO002

GPIO014/GPTP-IN7

GPIO015/GPTP-OUT7

GPIO016/GPTP-IN8

GPIO017/GPTP-OUT8

GPIO020

GPIO26/GPTP-IN1

GPIO27/GPTP-OUT1

GPIO30/GPTP-IN2

GPIO31/GPTP-OUT2

GPIO032/GPTP-IN3

GPIO040/GPTP-OUT3

GPIO041
GPIO107
GPIO120

GPIO124/GPTP-OUT5

GPIO125/GPTP-IN5

GPIO126

GPIO151/GPTP-IN4

GPIO152/GPTP-OUT4

GPIO003/I2C1A_DATA

GPIO004/I2C1A_CLK

GPIO005/I2C1B_DATA

GPIO006/I2C1B_CLK

GPIO130/I2C2A_DATA

GPIO131/I2C2A_CLK

GPIO132/I2C1G_DATA

GPIO140/I2C1G_CLK

GPIO143/I2C1E_DATA

GPIO144/I2C1E_CLK

BGPO0
VCI_IN2#
VCI_OUT
VCI_IN1#
VCI_IN0#

VCI_OVRD_IN

VCI_IN3#

thermal GND

MEC5035_XVTQFP128_14X14~D

MEC5035_XVTQFP128_14X14~D

1 2

L40

L40
BLM18AG121SN1D_0603~D

BLM18AG121SN1D_0603~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

10U_0805_10V4Z~D

10U_0805_10V4Z~D

1

1

1

C664

C664

C663

C663

C662

C662

nFWP

2

19
27
49
50
67
68
69
70
71
72
81
82
92
110
114
115
123

2
3
14
15
16
17
18
28
29
30
31
32
33
34
73
84
89
90
91
108
109

5
6
7
8
12
13
93
94
95
96
97
98
99
100

118
119
120
126
127
128
1

2

2

RC_ID
DDR_ON
RUNPWROKCLK_TP_SIO

SPI Rom Remove 2007/10/29

HOST_DEBUG_TX
HOST_DEBUG_RX
RESET_OUT#
MSDATA
MSCLK
SIO_A20GATE
PS_ID
BAT1_LED#
BAT2_LED#
FWP#

SIO_SLP_M#
DOCK_SMB_ALERT#
ME_WOL_ENACAV_IN_DOCK#
ME_SUS_PWR_ACK

1.8V_SUS_PWRGD
ICH_CL_PWROK

3.3V_LAN_PWRGD

1.05V_M_PWRGD
ALW_PWRGD_3V_5V
SUSPWROK
SIO_SLP_S5#
BEEP
AUX_ON

M_ON
ICH_RSMRST#
AC_PRESENT
SIO_PWRBTN#

DOCK_SMB_DAT
DOCK_SMB_CLK
LCD_SMBDAT
LCD_SMBCLK
CKG_SMBDAT
CKG_SMBCLK

ACAV_IN_NB
CARD_SMBDAT

CARD_SMBCLK

SNIFFER/INSTANT_SW#
ALWON
EN_CELL_CHARGER_DET#
POWER_SW_IN#
ACAV_IN_MB/DOCK
DOCK_PWR_SW#

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

1

C665

C665

2

ACAV_IN_MB/DOCK<18>

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

1

C666

C666

1

C667

C667

C668

C668

2

2

DDR_ON <46>

RUNPWROK <37,41,47>

ICH_LAN_RST# <24>

HOST_DEBUG_TX <34>
HOST_DEBUG_RX <34>

RESET_OUT# <41>

MSDATA <34>

MSCLK <34>

SIO_A20GATE <23>

PS_ID <43>
BAT1_LED# <42>
BAT2_LED# <42>

SIO_SLP_M# <24>
DOCK_SMB_ALERT# <35>

ME_WOL_EN <24>

ME_SUS_PWR_ACK <24>

1.8V_SUS_PWRGD <46>
ICH_CL_PWROK <10,24>

3.3V_LAN_PWRGD <41>

1.05V_M_PWRGD <45>
ALW_PWRGD_3V_5V <44>

SUSPWROK <41>

SIO_SLP_S5# <24>

BEEP <27>

AUX_ON <40>

3.3V_M_PWRGD <18,41>

AUX_EN_WOWL <34>

SIO_SLP_S4# <24>

M_ON <40,45>
ICH_RSMRST# <24>

AC_PRESENT <24>

SIO_PWRBTN# <24>

DOCK_SMB_DAT <35>
DOCK_SMB_CLK <35>
LCD_SMBDAT <19>

LCD_SMBCLK <19>
CKG_SMBDAT <6,27,48>
CKG_SMBCLK <6,27,48>

AMT_SMBCLK <24>

ALWON <44>
EN_CELL_CHARGER_DET# <33>

Bat2 = Amber LED
Bat1 = Blue LED

20mA drive pins

AMT_SMBDAT <24>

CARD_SMBDAT <32,34>
CARD_SMBCLK <32,34>

2

+RTC_CELL

12

R539

R539
100K_0402_5%~D

100K_0402_5%~D

POWER_SW_IN#<18> POWER_SW#_MB <31,39>

+RTC_CELL

5

P

4

Y

G

3

+RTC_CELL

5

U64

U64

P

INA

4

O

INB

G

3

POWER_SW_IN#

DOCK_PWR_SW#

+3.3V_ALW

1 2

RC_ID

4700P_0402_25V7K~D

4700P_0402_25V7K~D

1

2

+3.3V_ALW

FWP#

1 2

C827 0.1U_0402_16V4Z~D

C827 0.1U_0402_16V4Z~D

INSTANT_ON_SW#

2

A

SNIFFER_PWR_SW#

1

B

74AHCT1G08GW_SOT353-5~D

74AHCT1G08GW_SOT353-5~D
U62

U62

1 2

C846 0.1U_0402_16V4Z~D

C846 0.1U_0402_16V4Z~D

ACAV_IN_NB

1

ACAV_IN_DOCK

2

SN74AHC1G32DCKR_SC70-5~D

SN74AHC1G32DCKR_SC70-5~D

R211

R211
1K_0402_5%~D

1K_0402_5%~D

C480

C480

R578

R578
10K_0402_5%~D

10K_0402_5%~D

1 2

R586

@R586

@

10K_0402_5%~D

10K_0402_5%~D

1 2

ACAV_IN_NB <48>
ACAV_IN_DOCK <48,49>

1 2

R541 1K_0402_5%~D

R541 1K_0402_5%~D

1

C659

C659
1U_0603_10V4Z~D

1U_0603_10V4Z~D

2

+RTC_CELL

12

R550

R550
100K_0402_5%~D

100K_0402_5%~D

1 2

R554 1K_0402_5%~D

R554 1K_0402_5%~D

1

C670

C670
1U_0603_10V4Z~D

1U_0603_10V4Z~D

2

EN_CELL_CHARGER_DET#
INSTANT_ON_SW#
SNIFFER_PWR_SW#

SNIFFER/INSTANT_SW#

DOCK_SMB_DAT
DOCK_SMB_CLK

CLK_KBD
DAT_KBD
CLK_MSE
DAT_MSE
AC_PRESENT

JTAG_RST#

INSTANT_ON_SW# <31,37>
SNIFFER_PWR_SW# <31>

1

1 2

C658

@C658

@

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1 2

C669

@C669

@

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

DOCK_PWR_BTN# <35>DOCK_PWR_SW#<18>

1 2

R975 100K_0402_5%~DR975 100K_0402_5%~D
R560 100K_0402_5%~D

R560 100K_0402_5%~D

1 2

R562 100K_0402_5%~D

R562 100K_0402_5%~D

1 2

R971 100K_0402_5%~D

R971 100K_0402_5%~D

R565 8.2K_0402_5%~D

R565 8.2K_0402_5%~D
R567 8.2K_0402_5%~D

R567 8.2K_0402_5%~D

R569 4.7K_0402_5%~D

R569 4.7K_0402_5%~D
R570 4.7K_0402_5%~D

R570 4.7K_0402_5%~D
R571 4.7K_0402_5%~D

R571 4.7K_0402_5%~D
R572 4.7K_0402_5%~D

R572 4.7K_0402_5%~D

1 2

R573 10K_0402_5%~D

R573 10K_0402_5%~D

+3.3V_ALW

R579

R579
10K_0402_5%~D

10K_0402_5%~D

1 2

12

@

@

R585

R585

100_0402_1%~D

100_0402_1%~D

EC_JTAG_RST_PAD1

EC_JTAG_RST_PAD1

@SHORT PADS~D

@SHORT PADS~D

1=JTAG interface Reset disabled
0=Reset JTAG interface

+RTC_CELL

12

+3.3V_ALW
12
12

+5V_RUN
12
12
12
12

C978

C978

1

2

1

1

0.1U_0402_16V7K~D

0.1U_0402_16V7K~D

2

2

5

Remove EC SPI rom (2007/10/29)

4

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

2

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, MB A4042

SCHEMATIC, MB A4042

SCHEMATIC, MB A4042

401533

401533

401533

1

38 56Monday, December 17, 2007

38 56Monday, December 17, 2007

38 56Monday, December 17, 2007

of

of

of

A

A

A

5

D D

C C

4

3

TP_DATA
TP_CLK CLK_TP_SIO

2

+5V_RUN

4.7K_0402_5%~D

4.7K_0402_5%~D

12

L41

L41

1 2

BLM18AG601SN1D_0603~D

BLM18AG601SN1D_0603~D

1 2

L42

10P_0402_50V8J~D

10P_0402_50V8J~D

1

C680

C680

2

L42

10P_0402_50V8J~D

10P_0402_50V8J~D

BLM18AG601SN1D_0603~D

BLM18AG601SN1D_0603~D

1

C681

C681

2

10P_0402_50V8J~D

10P_0402_50V8J~D

1

2

R594

R594

C682

C682

4.7K_0402_5%~D

4.7K_0402_5%~D

12

10P_0402_50V8J~D

10P_0402_50V8J~D

1

2

R595

R595

DAT_TP_SIO

C683

C683

1

DAT_TP_SIO <38>
CLK_TP_SIO <38>

Power Switch for debug

JTP1

JTP1

1

1

BC_DAT_ECE1077<38>

BC_CLK_ECE1077<38>
BC_INT#_ECE1077<38>

+3.3V_ALW

TP_CLK
TP_DATA

KYBRD_BKLT_PWM<38>

+5V_RUN
+5V_ALW
+3.3V_RUN

TP_DET#<37>

TP_DET#

B B

For new ALPS KB
Backlight only, need

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

11

11

12

12

13

13

14

14

15

15

16

16

17

17

18

18

19

19

20

20

21

G1

22

G2

+5V_RUN +3.3V_RUN

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

C678

C678

1

2

+3.3V_ALW

1

2

1

2

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

C679

C679

Close to JTP1

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

C771

C771

POWER_SW#_MB<31,38>

POWER_SW#_MB

C684

@C684

@

100P_0402_50V8J~D

100P_0402_50V8J~D

1

2

1

1

PWR_SW1

PWR_SW1

@SHORT PADS~D

@SHORT PADS~D

Place on Top

1

1

PWR_SW2

PWR_SW2

@SHORT PADS~D

@SHORT PADS~D

Place on Bottom

2

2

2

2

modify at next gerber

JST_SM20B-SURS-TF(LF)(SN)

JST_SM20B-SURS-TF(LF)(SN)

TP_CLK
TP_DATA

A A

Place close to JTP1 connector

SD05.TCT_SOD323-2~D

SD05.TCT_SOD323-2~D

SD05.TCT_SOD323-2~D

SD05.TCT_SOD323-2~D

@

@

@

@

D53

D53

D54

D54

2 1

2 1

5

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

4

3

2

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

Date: Sheet

Compal Electronics, Inc.
SCHEMATIC, MB A4042

SCHEMATIC, MB A4042

SCHEMATIC, MB A4042

401533

401533

401533

39 56Monday, December 17, 2007

39 56Monday, December 17, 2007

39 56Monday, December 17, 2007

1

A

A

A

of

of

of

5

4

3

2

1

+5VRUN Source

DC/DC Interface

+3.3V_ALW2

2

12

61

2

+3.3V_ALW2

12

R604

R604
100K_0402_5%~D

100K_0402_5%~D

61

R602

R602
100K_0402_5%~D

100K_0402_5%~D

ALW_ON_3.3V#

Q57A

Q57A
2N7002DW-T/R7_SOT363-6~D

2N7002DW-T/R7_SOT363-6~D

SUS_ON_3.3V#

Q62A

Q62A
2N7002DW-T/R7_SOT363-6~D

2N7002DW-T/R7_SOT363-6~D

D D

ICH_ALW_ON<38>

C C

SUS_ON<38,41>

+15V_ALW

12

R598

R598
100K_0402_5%~D

100K_0402_5%~D

ALW_ENABLE

3

Q57B

Q57B
2N7002DW-T/R7_SOT363-6~D

2N7002DW-T/R7_SOT363-6~D

5

4

+15V_ALW

12

R603

R603
100K_0402_5%~D

100K_0402_5%~D

SUS_ENABLE

3

Q62B

Q62B
2N7002DW-T/R7_SOT363-6~D

2N7002DW-T/R7_SOT363-6~D

5

4

+3.3V_ALW_ICH Source

+3.3V_ALW +3.3V_ALW_ICH

Q54

Q54
SI3456BDV-T1-E3_TSOP6~D

SI3456BDV-T1-E3_TSOP6~D

D

D

6

S

S

45

2

+3.3V_SUS Source

+3.3V_ALW

Q60

Q60
STS11NF30L_SO8~D

STS11NF30L_SO8~D

8
7

5

1

10U_0805_10V4Z~D

10U_0805_10V4Z~D

G

G

3

1

C688

C688
4700P_0402_25V7K~D

4700P_0402_25V7K~D

2

1
2
36

10U_0805_10V4Z~D

10U_0805_10V4Z~D

C690

C690

4

1

C692

C692
4700P_0402_25V7K~D

4700P_0402_25V7K~D

2

C687

C687

1

2

1

2

+3.3V_SUS

12

R601

R601
20K_0402_5%~D

20K_0402_5%~D

20K_0402_5%~D

20K_0402_5%~D

12

R605

R605

12

R599

R599
100K_0402_5%~D

100K_0402_5%~D

RUN_ON_5V#

61

Q56A

Q56A
2N7002DW-T/R7_SOT363-6~D

2N7002DW-T/R7_SOT363-6~D

2

RUN_ON<19,28,37,41,50>

3.3V_RUN_ON<37>

12

R608

R608
100K_0402_5%~D

100K_0402_5%~D

RUN_ON_3V#

61

Q64A

Q64A
2N7002DW-T/R7_SOT363-6~D

2N7002DW-T/R7_SOT363-6~D

2

+15V_ALW+3.3V_ALW2 +5V_ALW

12

R597

R597
100K_0402_5%~D

100K_0402_5%~D

RUN_ENABLE

3

Q56B

Q56B
2N7002DW-T/R7_SOT363-6~D

2N7002DW-T/R7_SOT363-6~D

5

4

12

R606

R606

100K_0402_5%~D

100K_0402_5%~D

3

5

Q64B

Q64B
2N7002DW-T/R7_SOT363-6~D

2N7002DW-T/R7_SOT363-6~D

4

Q55

Q55
STS11NF30L_SO8~D

STS11NF30L_SO8~D

8
7

5

+3.3V_RUN Source

+3.3V_ALW+3.3V_ALW2 +15V_ALW

8
7

5

21

D30

@D30

@

RB751V_SOD323-2~D

RB751V_SOD323-2~D

1 2

R609

R609
0_0402_5%~D

0_0402_5%~D

1
2
36

4

2200P_0402_50V7K~D

2200P_0402_50V7K~D

1

C689

C689

2

Q61

Q61
SI4336DY-T1-E3_SO8~D

SI4336DY-T1-E3_SO8~D

4

1

C693

C693
470P_0402_50V7K~D

470P_0402_50V7K~D

2

+5V_RUN

10U_0805_10V4Z~D

10U_0805_10V4Z~D

12

1

R600

R600

C686

C686

20K_0402_5%~D

20K_0402_5%~D

2

+3.3V_RUN

1
2
36

C691

C691

10U_0805_10V4Z~D

10U_0805_10V4Z~D

12

1

R607

R607

2

20K_0402_5%~D

20K_0402_5%~D

+3.3VM Source

+3.3V_ALW2 +15V_ALW

12

R611

R611
100K_0402_5%~D

100K_0402_5%~D

M_ON_3.3V#

61

Q68A

Q68A
2N7002DW-T/R7_SOT363-6~D

2N7002DW-T/R7_SOT363-6~D

2

B B

A A

M_ON<38,45>

AUX_ON<38>

5

+3.3V_ALW2

2

12

3

4

12

R620

R620
100K_0402_5%~D

100K_0402_5%~D

2N7002DW-T/R7_SOT363-6~D

2N7002DW-T/R7_SOT363-6~D

61

100K_0402_5%~D

100K_0402_5%~D

R610

R610

M_ENABLE

Q68B

Q68B
2N7002DW-T/R7_SOT363-6~D

2N7002DW-T/R7_SOT363-6~D

N21917830

Q74A

Q74A

5

+3.3V_ALW

+15V_ALW

5

200K_0402_5%~D

200K_0402_5%~D

12

@R629

@

R629

Q66

Q66
SI3456BDV-T1-E3_TSOP6~D

SI3456BDV-T1-E3_TSOP6~D

6
2

1

12

R619

R619
100K_0402_5%~D

100K_0402_5%~D

2N7002DW-T/R7_SOT363-6~D

2N7002DW-T/R7_SOT363-6~D

3

Q74B

Q74B

4

D

D

S

S

45

G

G

3

1

C696

C696
4700P_0402_25V7K~D

4700P_0402_25V7K~D

2

1

C698

C698
4700P_0402_25V7K~D

4700P_0402_25V7K~D

2

+3.3V_M

10U_0805_10V4Z~D

10U_0805_10V4Z~D

1

C694

C694

2

12

20K_0402_5%~D

20K_0402_5%~D

12

R612

R612

ENAB_3VLAN <29>

R621

@R621

@

470K_0402_5%~D

470K_0402_5%~D

Discharge Circuit

@R615

@

R615

2N7002W-7-F_SOT323-3~D

2N7002W-7-F_SOT323-3~D

@

@

Q71

Q71

@R627

@

R627

2N7002W-7-F_SOT323-3~D

2N7002W-7-F_SOT323-3~D

@

@

Q81

Q81

+3.3V_M+1.05V_M

12

13

2

G

G

75_0603_5%~D

75_0603_5%~D

12

13

D

M_ON_3.3V#

SUS_ON_3.3V# ALW_ON_3.3V#

2

G

G

+3.3V_SUS

2

G

G

D

S

S

1K_0402_5%~D

1K_0402_5%~D

12

13

D

D

S

S

1K_0402_5%~D

1K_0402_5%~D

@R616

@

R616

2N7002W-7-F_SOT323-3~D

2N7002W-7-F_SOT323-3~D

D

D

@

@

Q72

Q72

S

S

+3.3V_ALW_ICH

2

G

G

12

13

D

D

S

S

1K_0402_5%~D

1K_0402_5%~D

@R628

@

R628

2N7002W-7-F_SOT323-3~D

2N7002W-7-F_SOT323-3~D

@

@

Q82

Q82

12

R617

R617
100K_0402_5%~D

100K_0402_5%~D

RUN_ON_1.05V#

61

Q70A

Q70A
2N7002DW-T/R7_SOT363-6~D

2N7002DW-T/R7_SOT363-6~D

2

1.05V_RUN_ON<37>

Discharge Circuit

1K_0402_5%~D

1K_0402_5%~D

12

@ R622

@

R622

2N7002W-7-F_SOT323-3~D

2N7002W-7-F_SOT323-3~D

13

D

D

@

RUN_ON_5V#

@

2

Q76

Q76

G

G

S

S

12

R613

R613

100K_0402_5%~D

100K_0402_5%~D

3

5

Q70B

Q70B
2N7002DW-T/R7_SOT363-6~D

2N7002DW-T/R7_SOT363-6~D

4

+1.5V_RUN +0.9V_DDR_VTT +3.3V_RUN+5V_RUN

1K_0402_5%~D

1K_0402_5%~D

12

@ R623

@

R623

2N7002W-7-F_SOT323-3~D

2N7002W-7-F_SOT323-3~D

13

D

D

@

@

2

Q77

Q77

G

G

S

S

1K_0402_5%~D

1K_0402_5%~D

12

@ R624

@

R624

2N7002W-7-F_SOT323-3~D

2N7002W-7-F_SOT323-3~D

13

D

D

@

@

2

G

G

RUN_ON_3V# RUN_ON_1.05V#

Q78

Q78

S

S

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

4

3

2

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

Date: Sheet

+1.05V_VCCP Source

Q67

Q67
SI4336DY-T1-E3_SO8~D

+1.05V_M+3.3V_ALW2 +15V_ALW

D31

@D31

@

RB751V_SOD323-2~D

RB751V_SOD323-2~D

R618

R618
0_0402_5%~D

0_0402_5%~D

SI4336DY-T1-E3_SO8~D

8
7

5

21

1 2

12

13

D

D

2

G

G

S

S

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.
SCHEMATIC, MB A4042

SCHEMATIC, MB A4042

SCHEMATIC, MB A4042

401533

401533

401533

1K_0402_5%~D

1K_0402_5%~D

@ R625

@

R625

2N7002W-7-F_SOT323-3~D

2N7002W-7-F_SOT323-3~D

4

1

2

@

@

Q79

Q79

+1.05V_VCCP

1
2
36

1

C695

C695

2

10U_0805_10V4Z~D

10U_0805_10V4Z~D

C697

C697
470P_0402_50V7K~D

470P_0402_50V7K~D

1

12

+1.05V_VCCP

2

G

G

40 56Monday, December 17, 2007

40 56Monday, December 17, 2007

40 56Monday, December 17, 2007

12

13

D

D

S

S

R614

R614

of

of

of

20K_0402_5%~D

20K_0402_5%~D

1K_0402_5%~D

1K_0402_5%~D

@ R626

@

R626

2N7002W-7-F_SOT323-3~D

2N7002W-7-F_SOT323-3~D

@

@

Q80

Q80

A

A

A

5

4

3

2

1

@

@

2.5V_RUN_PWRGD<18,37>

1.5V_RUN_PWRGD<45>

H10

H10

@H_3P0

@H_3P0

GFX_CORE_PWRGD<50,53>

1.1V_GFX_PWRGD<50>

C

C

2

B

B

MMST3904-7-F_SOT323-3~D

MMST3904-7-F_SOT323-3~D

E

E

3 1

C

C

2

B

B

MMST3904-7-F_SOT323-3~D

MMST3904-7-F_SOT323-3~D

E

E

3 1

+3.3V_ALW+3.3V_ALW

8

P

A3Y

G

U39C

U39C
74LVC3G14DC_VSSOP8~D

74LVC3G14DC_VSSOP8~D

4

H11

H11

@H_3P0

@H_3P0

1

1

Q84

Q84

Q86

Q86

5

H22

H22

@H_2P2

@H_2P2

1

+5V_RUN

D D

C C

B B

1

2

+3.3V_RUN

1

2

+3.3V_SUS

H1

@H_3P0H1@H_3P0

H16

H16

@H_4P0

@H_4P0

RB751V_SOD323-2~D

RB751V_SOD323-2~D

C702

C702

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

RB751V_SOD323-2~D

RB751V_SOD323-2~D

C704

C704

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

D34

D34
RB751V_SOD323-2~D

RB751V_SOD323-2~D

2 1

1

C707

C707

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

2

H2

@H_3P0H2@H_3P0

1

1

H17

H17

@H_3P8

@H_3P8

1

1

2 1

D32

D32

2 1

D33

D33

H3

@H_3P0H3@H_3P0

H23

H23

@H_4P0

@H_4P0

1

1

H18

H18

@H_4P0

@H_4P0

12

1

200K_0402_5%~D

200K_0402_5%~D

R642

R642

H4

@H_3P0H4@H_3P0

200K_0402_5%~D

200K_0402_5%~D

12

200K_0402_5%~D

200K_0402_5%~D

12

1

1

R634

R634

2

1

R638

R638

2

10K_0402_5%~D

10K_0402_5%~D

1 2

2200P_0402_50V7K~D

2200P_0402_50V7K~D

C708

C708

1

2

H5

@H_3P0H5@H_3P0

1

H19

H19

@H_4P0

@H_4P0

1

R633

R633

10K_0402_5%~D

10K_0402_5%~D

1 2

C703

C703

2200P_0402_50V7K~D

2200P_0402_50V7K~D

1 2

R637

R637

10K_0402_5%~D

10K_0402_5%~D

C705

C705

2200P_0402_50V7K~D

2200P_0402_50V7K~D

R641

R641

H6

@H_3P0H6@H_3P0

1

H20

H20

@H_3P9

@H_3P9

1

+5V_ALW

B

B

2

+3.3V_ALW

B

B

2

E

E

3

B

B

Q88

Q88

2

MMBT3906WT1G_SC70-3~D

MMBT3906WT1G_SC70-3~D

C

C

1

200K_0402_5%~D

200K_0402_5%~D

12

R643

R643

H7

@H_3P0H7@H_3P0

1

H21

H21

@H_3P3

@H_3P3

1

E

E

3

Q83

Q83

MMBT3906WT1G_SC70-3~D

MMBT3906WT1G_SC70-3~D

C

C

1

R635

R635

4.7K_0402_5%~D

4.7K_0402_5%~D

1 2

E

E

3

Q85

Q85

MMBT3906WT1G_SC70-3~D

MMBT3906WT1G_SC70-3~D

C

C

1

R639

R639

4.7K_0402_5%~D

4.7K_0402_5%~D

1 2

D35

D35
RB751V_SOD323-2~D

RB751V_SOD323-2~D

2 1

H9

H8

@H_3P0H9@H_3P0

@H_3P0H8@H_3P0

1

1

H15

H15

H14

H14

@H_5P3

@H_5P3

@H_5P3

@H_5P3

1

1

R630 0_0402_5%~D

R630 0_0402_5%~D
R631 0_0402_5%~D

R631 0_0402_5%~D
R808 0_0402_5%~D

R808 0_0402_5%~D
R809 0_0402_5%~D

R809 0_0402_5%~D

IO board

H12

H12

@H_3P0

@H_3P0

1

12
12
12

@

@

12

+3.3V_SUS

12

1

2

100K_0402_5%~D

100K_0402_5%~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

R632

R632

C701

C701

+3.3V_ALW

+3.3V_M

1

C709

C709

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

2

C699

C699

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

1 2

8

P

7

A1Y

G

U39A

U39A
74LVC3G14DC_VSSOP8~D

74LVC3G14DC_VSSOP8~D

4

IMVP_PWRGD<24,37,47>
RESET_OUT#<38>

D36

D36
RB751V_SOD323-2~D

RB751V_SOD323-2~D

2 1

IMVP_PWRGD
RESET_OUT#

200K_0402_5%~D

200K_0402_5%~D

12

R645

R645

RUN_ON<19,28,37,40,50>

SUS_ON<38,40>

2200P_0402_50V7K~D

2200P_0402_50V7K~D

1

2

+3.3V_ALW

A6Y

10K_0402_5%~D

10K_0402_5%~D

1 2

C710

C710

8

P

2

G

U39B

U39B
74LVC3G14DC_VSSOP8~D

74LVC3G14DC_VSSOP8~D

4

1 2

R636

R636
0_0402_5%~D

0_0402_5%~D

3.3V_5V_SUS_PWRGD

+3.3V_ALW

14

13

P

IN1

OUT

12

IN2

G

7

R644

R644

E

E

B

B

2

+3.3V_ALW

1
2

+3.3V_ALW

10

9

ICH_PWRGD

11

U40D

U40D
74VHC08MTCX_NL_TSSOP14~D

74VHC08MTCX_NL_TSSOP14~D

3

Q89

Q89
MMBT3906WT1G_SC70-3~D

MMBT3906WT1G_SC70-3~D

C

C

1

2 1

200K_0402_5%~D

200K_0402_5%~D

12

D37

D37
RB751V_SOD323-2~D

RB751V_SOD323-2~D

R646

R646

C700

C700

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

1 2

14

U40A

U40A
74VHC08MTCX_NL_TSSOP14~D

74VHC08MTCX_NL_TSSOP14~D

P

IN1

3

OUT

IN2

G

7

14

P

IN1

8

OUT

IN2

G

U40C

U40C
74VHC08MTCX_NL_TSSOP14~D

74VHC08MTCX_NL_TSSOP14~D

7

100K_0402_5%~D

100K_0402_5%~D

+3.3V_ALW

14

4

P

IN1

OUT

5

IN2

G

7

+3.3V_M

12

R640

R640

ICH_PWRGD#

13

D

D

Q87

Q87

2

2N7002W-7-F_SOT323-3~D

2N7002W-7-F_SOT323-3~D

G

G

S

S

+3.3V_ALW+3.3V_ALW

8

P

7

A1Y

G

U41A

U41A
74LVC3G14DC_VSSOP8~D

74LVC3G14DC_VSSOP8~D

4

U40B

U40B
74VHC08MTCX_NL_TSSOP14~D

74VHC08MTCX_NL_TSSOP14~D

RUNPWROK

6

ICH_PWRGD# <18>

ICH_PWRGD <10,24>

3.3V_M_PWRGD <18,38>

RUNPWROK <37,38,47>

SUSPWROK <38>

CPU x 4 GPU x 3 eDOCK x 2

+3.3V_LAN

D40

D40
RB751V_SOD323-2~D

RB751V_SOD323-2~D

2 1

EMI CLIP

CLIP1

CLIP1

EMI_CLIP

EMI_CLIP

CLIP2

A A

CLIP2
EMI_CLIP

EMI_CLIP

GND

GND

1

1

Fiducial Mark

FD1

FD1

1

FIDUCIAL MARK~D

FIDUCIAL MARK~D

FD3

FD3

1

FIDUCIAL MARK~D

FIDUCIAL MARK~D

FD2

FD2

1

FIDUCIAL MARK~D

FIDUCIAL MARK~D

FD4

FD4

1

FIDUCIAL MARK~D

FIDUCIAL MARK~D

1

C714

C714

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

2

200K_0402_5%~D

200K_0402_5%~D

12

R652

R652

10K_0402_5%~D

10K_0402_5%~D

1 2

2200P_0402_50V7K~D

2200P_0402_50V7K~D

1

C715

C715

2

R651

R651

E

E

3

B

B

Q91

Q91

2

MMBT3906WT1G_SC70-3~D

MMBT3906WT1G_SC70-3~D

C

C

1

200K_0402_5%~D

200K_0402_5%~D

12

R653

R653

2 1

D41

D41
RB751V_SOD323-2~D

RB751V_SOD323-2~D

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

+3.3V_ALW+3.3V_ALW

C713

C713

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

1 2

8

P

2

A6Y

G

U41B

U41B
74LVC3G14DC_VSSOP8~D

74LVC3G14DC_VSSOP8~D

4

3.3V_LAN_PWRGD <38>

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

Date: Sheet

Compal Electronics, Inc.
SCHEMATIC, MB A4042

SCHEMATIC, MB A4042

SCHEMATIC, MB A4042

401533

401533

401533

41 56Monday, December 17, 2007

41 56Monday, December 17, 2007

41 56Monday, December 17, 2007

1

of

of

of

A

A

A

5

R995

R995

+3.3V_ALW

+3.3V_ALW

5

BREATH_LED#<35,38>

D D

A2Y

3

2

1

P

NC

4

G

U42NC7SZ04P5X_NL_SC70-5~D U42NC7SZ04P5X_NL_SC70-5~D

BREATH_LED

+3.3V_ALW

2

BREATH LED

+3.3V_WLAN +5V_RUN

1 2

100K_0402_5%~D

100K_0402_5%~D

61

Q145A

Q145A

MARK_BASE_LEDS#

R998

R998

2N7002DW-T/R7_SOT363-6~D

2N7002DW-T/R7_SOT363-6~D

1 2

100K_0402_5%~D

100K_0402_5%~D

61

Q144A

Q144A

2N7002DW-T/R7_SOT363-6~D

2N7002DW-T/R7_SOT363-6~D

SYS_LED_MASK#

2N7002DW-T/R7_SOT363-6~D

2N7002DW-T/R7_SOT363-6~D
Q145B

Q145B

3

4

5

Q144B

Q144B
2N7002DW-T/R7_SOT363-6~D

2N7002DW-T/R7_SOT363-6~D

3

4

5

WLAN LED solution for Blue LED

12

Q151A

Q151A

R662

R662

2N7002DW-7-F_SOT363-6~D

2N7002DW-7-F_SOT363-6~D

100K_0402_5%~D

LED_WLAN_OUT#<34>

C C

LED_WWAN_OUT#<34>

LED_WPAN_OUT#<34>

B B

100K_0402_5%~D

MARK_BASE_LEDS#

+3.3V_RUN

12

2N7002DW-7-F_SOT363-6~D

2N7002DW-7-F_SOT363-6~D

R206

R206

100K_0402_5%~D

100K_0402_5%~D

MARK_BASE_LEDS#

+3.3V_RUN

12

R660

R660

100K_0402_5%~D

100K_0402_5%~D

MARK_BASE_LEDS#

2

Q151B

Q151B

4

5

Q152A

Q152A
2N7002DW-7-F_SOT363-6~D

2N7002DW-7-F_SOT363-6~D

2

+3.3V_ALW

2

61

+5V_RUN

1 3

Q97

Q97
PDTA114EU_SC70-3~D

PDTA114EU_SC70-3~D

WLAN_LED

1 2

R663 150_0402_5%~D

R663 150_0402_5%~D

LTST-C191TBKT-5A BLU_0603~D

LTST-C191TBKT-5A BLU_0603~D

D45

D45

WWAN LED solution for Blue LED

2

3

2

1 3

+5V_RUN

Q115

Q115
PDTA114EU_SC70-3~D

PDTA114EU_SC70-3~D

WWAN_LED

1 2

R125 150_0402_5%~D

R125 150_0402_5%~D

Q94

Q94
DDTA114EUA-7-F_SOT323-3~D

DDTA114EUA-7-F_SOT323-3~D

LTST-C191TBKT-5A BLU_0603~D

LTST-C191TBKT-5A BLU_0603~D

D61

D61

WPAN LED solution for Blue LED

61

1 3

1 2

R661 150_0402_5%~D

R661 150_0402_5%~D

D43

D43

WPAN_LED

LTST-C191TBKT-5A BLU_0603~D

LTST-C191TBKT-5A BLU_0603~D

SNIFFER LED

2

+5V_ALW

2

Q100

Q100
DDTA114EUA-7-F_SOT323-3~D

DDTA114EUA-7-F_SOT323-3~D

1 3

Q102

Q102
DDTA114EUA-7-F_SOT323-3~D

DDTA114EUA-7-F_SOT323-3~D

1 3

SNIFFER_YELLOW

1 2

R667 220_0402_5%~D

R667 220_0402_5%~D

SNIFFER_BLUE

1 2

R668 150_0402_5%~D

R668 150_0402_5%~D

SNIFFER_YELLOW#<37>

SNIFFER_BLUE#<37>

4

+5V_ALW

2

+5V_ALW

2

12

12

12

SNIFFER_YELLOW <31>

SNIFFER_BLUE <31>

Q143

Q143

1 3

DDTA114EUA-7-F_SOT323-3~D

DDTA114EUA-7-F_SOT323-3~D

1 2

R997 150_0402_5%~D

R997 150_0402_5%~D

Q147

Q147

1 3

DDTA114EUA-7-F_SOT323-3~D

DDTA114EUA-7-F_SOT323-3~D

1 2

R1000 150_0402_5%~D

R1000 150_0402_5%~D

BREATH_BLUE_LED_IO

BREATH_BLUE_LED_LCD

SYS_LED_MASK#<37>

BREATH_BLUE_LED_IO <31>

BREATH_BLUE_LED_LCD <19>

SYS_LED_MASK#

LID_CL#

LID_CL#<31,37>

74AHCT1G08GW_SOT353-5~D

74AHCT1G08GW_SOT353-5~D

2
1

U14

U14

+3.3V_ALW

A
B

5

P

G

3

3

MARK_BASE_LEDS#

4

Y

2

+5V_ALW

+5V_ALW

R996

R996

100K_0402_5%~D

100K_0402_5%~D

2

2

5

5

61

+5V_ALW

61

SYS_LED_MASK#

+3.3V_ALW

1 2

3

+3.3V_ALW

4

1 2

3

4

SYS_LED_MASK#

1 2

R999

R999
100K_0402_5%~D

100K_0402_5%~D

1 2

2N7002DW-7-F_SOT363-6~D

2N7002DW-7-F_SOT363-6~D

R906

R906
100K_0402_5%~D

100K_0402_5%~D

R905

R905
100K_0402_5%~D

100K_0402_5%~D

2N7002DW-7-F_SOT363-6~D

2N7002DW-7-F_SOT363-6~D

2N7002DW-7-F_SOT363-6~D

2N7002DW-7-F_SOT363-6~D

+3.3V_ALW

5

1

P

NC

BAT2_LED#<38>

BAT1_LED#<38>

A2Y

G

U68

U68
NC7SZ04P5X_NL_SC70-5~D

NC7SZ04P5X_NL_SC70-5~D

3

+3.3V_ALW

5

1

P

NC

A2Y

G

U69

U69
NC7SZ04P5X_NL_SC70-5~D

NC7SZ04P5X_NL_SC70-5~D

3

4

2N7002DW-7-F_SOT363-6~D

2N7002DW-7-F_SOT363-6~D

2N7002DW-7-F_SOT363-6~D

2N7002DW-7-F_SOT363-6~D

4

2N7002DW-7-F_SOT363-6~D

2N7002DW-7-F_SOT363-6~D

BAT2_LED

BAT1_LED

Q141A

Q141A

Q140B

Q140B

Q141B

Q141B

Q140A

Q140A

2

1 3

Q142A

Q142A

2

+3.3V_ALW

2

DDTA114EUA-7-F_SOT323-3~D

DDTA114EUA-7-F_SOT323-3~D

1 3

Q142B

Q142B

4

5

Q146

Q146
DDTA114EUA-7-F_SOT323-3~D

DDTA114EUA-7-F_SOT323-3~D

1 2

R665 150_0402_5%~D

R665 150_0402_5%~D

+5V_ALW

61

2

Q149

Q149

1 2

R1003 150_0402_5%~D

R1003 150_0402_5%~D

+3.3V_ALW

2

3

BATT_BLUE_LED

1 3

BATT_YELLOW_LED

1 3

D46

D46

2 1

LTST-C155TBJSKT_Blue/YEL~D

LTST-C155TBJSKT_Blue/YEL~D

Q148

Q148

DDTA114EUA-7-F_SOT323-3~D

DDTA114EUA-7-F_SOT323-3~D

Q150

Q150

DDTA114EUA-7-F_SOT323-3~D

DDTA114EUA-7-F_SOT323-3~D

1

BATTERY LED

ON MB

BLUE

BLUE

2N7002W-7-F_SOT323-3~D

2N7002W-7-F_SOT323-3~D

34

YEL

YEL

MARK_BASE_LEDS#

ON LCD

1 2

R903 150_0402_5%~D

R903 150_0402_5%~D

1 2

R904 150_0402_5%~D

R904 150_0402_5%~D

D64

D64

D

S

D

S

1 3

G

G

2

BATT_BLUE_LED_LCD <19>

BATT_YELLOW_LED_LCD <19>

KEYBOARD STATUS LED

+5V_ALW

2

CAP_LED#<37>

2

2

1 3

Q122

Q122
DDTA114EUA-7-F_SOT323-3~D

DDTA114EUA-7-F_SOT323-3~D

1 3

NUM_LED#<37>

SCRL_LED#<37>

BIOS GPIO Table for LED Control

Q120

Q120
DDTA114EUA-7-F_SOT323-3~D

DDTA114EUA-7-F_SOT323-3~D

1 3

Q121

Q121
DDTA114EUA-7-F_SOT323-3~D

DDTA114EUA-7-F_SOT323-3~D

R_CAP_LED#

1 2

R556 150_0402_5%~D

R556 150_0402_5%~D

R_NUM_LED#

1 2

R596 150_0402_5%~D

R596 150_0402_5%~D

R_SCRL_LED#

1 2

R655 150_0402_5%~D

R655 150_0402_5%~D

12

D57

D57
LTST-C191TBKT-5A BLU_0603~D

LTST-C191TBKT-5A BLU_0603~D

12

D58

D58
LTST-C191TBKT-5A BLU_0603~D

LTST-C191TBKT-5A BLU_0603~D

12

D59

D59
LTST-C191TBKT-5A BLU_0603~D

LTST-C191TBKT-5A BLU_0603~D

SYS_LED_MARK# LID_CL#

A A

SATA_ACT#_R<23>

+3.3V_RUN

R654

R654

100K_0402_5%~D

100K_0402_5%~D

MARK_BASE_LEDS#

12

Q152B

Q152B

2N7002DW-7-F_SOT363-6~D

2N7002DW-7-F_SOT363-6~D

4

5

5

+5V_RUN

HDD LED solution for Blue LED

Q92

Q92
DDTA114EUA-7-F_SOT323-3~D

DDTA114EUA-7-F_SOT323-3~D

2

3

1 3

1 2

R659 150_0402_5%~D

R659 150_0402_5%~D

SATA_LED

D42

D42

LTST-C191TBKT-5A BLU_0603~D

LTST-C191TBKT-5A BLU_0603~D

12

4

MARK ALL LED (SNIFFER FUNCTION)
MARK BASE MB LEDs (Lid Closed)
Do Not Mark LEDs (Lid Opened)

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

Low
High
High High

X
Low

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.
SCHEMATIC, MB A4042

SCHEMATIC, MB A4042

SCHEMATIC, MB A4042

401533

401533

401533

1

42 56Monday, December 17, 2007

42 56Monday, December 17, 2007

42 56Monday, December 17, 2007

A

A

A

of

of

of

5

4

3

2

1

+COINCELL

D D

Primary Battery Connector

FOX_BP02093-P5652-7F~D

FOX_BP02093-P5652-7F~D

11
10

12

PC3

PC3

2200P_0402_50V7K~D

2200P_0402_50V7K~D

C C

B B

9

GND

9

8

GND

PBATT1

PBATT1

8

7

7

6

6

5

5

4

4

3

3

2

2

1

1

NB_PSID

Z4304
Z4305
Z4306

PD2

PD2

DA204U_SOT323~D@

DA204U_SOT323~D@

PR3

PR3

100_0402_5%~D

100_0402_5%~D

1 2

+3.3V_ALW

2

3

PD3

PD3

1

DA204U_SOT323~D@

DA204U_SOT323~D@

PR4

PR4

100_0402_5%~D

100_0402_5%~D

1 2

PL2

PL2

BLM18BD102SN1D_0603~D

BLM18BD102SN1D_0603~D

12

ESD Diodes

2

3

1

PR5

PR5

100_0402_5%~D

100_0402_5%~D

1 2

3

PD4

PD4

100_0402_5%~D

100_0402_5%~D

2

1

DA204U_SOT323~D@

DA204U_SOT323~D@

PR6

1 2

2

3

PD5

PD5

1

DA204U_SOT323~D@

DA204U_SOT323~D@

PC2

@ PR7

@

1 2

0_0402_5%~D

0_0402_5%~D

2

B

B

PR7

1 3

PC2

D

S

D

S

PQ1

PQ1
FDV301N_SOT23~D

FDV301N_SOT23~D

G

G

2

C

C

PQ2

PQ2
MMST3904-7-F_SOT323~D

MMST3904-7-F_SOT323~D

E

E

3 1

PBAT_SMBCLK <38>

PBAT_ALARM#

@

@

PBAT_SMBDAT <38>

PR10

PR10

1 2

100K_0402_1%~D

100K_0402_1%~D

PR12

PR12

1 2

15K_0402_1%~D

15K_0402_1%~D

@PR6

@

2

3

1

PD7

PD7
SM24_SOT23

SM24_SOT23

PL1

PL1

FBMA-L18-453215-900LMA90T_1812~D

FBMA-L18-453215-900LMA90T_1812~D

1 2

PJP1

PJP1

1 2

12

PAD-OPEN 4x4m

PAD-OPEN 4x4m

0.1U_0603_25V7K~D

0.1U_0603_25V7K~D

2

3

PD6

PD6

DA204U_SOT323~D

DA204U_SOT323~D

PR9

PR9

1

+5V_ALW

12

33_0402_5%~D

33_0402_5%~D

1 2

PR11

PR11

10K_0402_1%~D

10K_0402_1%~D

PBATT+

PR13

PR13

1 2

10K_0402_5%~D@

10K_0402_5%~D@

@

@

PD8

PD8

+3.3V_ALW+5V_ALW

PR8

PR8

2.2K_0402_5%~D

2.2K_0402_5%~D

+5V_ALW

DA204U_SOT323~D

DA204U_SOT323~D

+3.3V_ALW

12

PR2

PR2

10K_0402_1%~D

10K_0402_1%~D

1 2

2

3

1

PBAT_PRES# <37>

DOCK_PSID<35> GPIO_PSID_SELECT <37>

NB_PSID_TS5A63157

PSID_DISABLE# <37>

+3.3V_RTC_LDO

2

PD1

PD1

1

BAT54CW_SOT323~D

BAT54CW_SOT323~D

PU1

PU1

1

NO

2

GND

NC3COM

TS5A63157DCKR_SC70-6~D

TS5A63157DCKR_SC70-6~D

12

Z4012

3

COIN RTC Battery

PR1

PR1
1K_0402_5%~D

1K_0402_5%~D

V+

12

6

IN

5

4

+RTC_CELL

PC1

PC1
1U_0603_10V6K~D

1U_0603_10V6K~D

PAD~D@

PAD~D@

T47

T47

Move to power schematic

+5V_ALW

PS_ID <38>

+COINCELL

RTC_BAT_DET_R#

JRTC1

JRTC1

1

1

2

4

2

G1

3

5

3

G2

MOLEX_53398-0371~D

MOLEX_53398-0371~D

PQ3

DCIN_CBL_DET# <37>

PL3

PL3

FBMJ4516HS720NT_1806~D

FBMJ4516HS720NT_1806~D

1 2

1

12

PC5

PJPDC1

PJPDC1

1

1

2

2

-DCIN_JACK

3

3

4

4

5

5

A A

MOLEX_87437-0663

MOLEX_87437-0663

+DCIN_JACK

6

6

PC5

2

0.1U_0603_25V7K~D

0.1U_0603_25V7K~D
PL4

PL4

FBMJ4516HS720NT_1806~D

FBMJ4516HS720NT_1806~D

1 2

12

PC11

PC11

0.1U_0603_25V7K~D

0.1U_0603_25V7K~D

5

NB_AC_OFF_BJT<49> NB_AC_OFF <37,49>

PD9

PD9

@

@

VZ0603M260APT_0603

VZ0603M260APT_0603

@

@

PC10

PC10

12

0.1U_0603_25V7K~D

0.1U_0603_25V7K~D

IMD2AT-108_SC74-6~D

IMD2AT-108_SC74-6~D

12

PR16

PR16

0_0402_5%~D

0_0402_5%~D

@

@

5

+DC_IN

PQ4B

PQ4B

PC4

PC4

43

2

16

PQ4A

PQ4A

IMD2AT-108_SC74-6~D

IMD2AT-108_SC74-6~D

1 2

0.47U_0805_25V7K~D

0.47U_0805_25V7K~D

+DC_IN

1
2
3 6

12

PR14

PR14

240K_0402_5%~D

240K_0402_5%~D

4

PQ3

FDS6679AZ_SO8~D

FDS6679AZ_SO8~D

4

12

PR17

PR17

47K_0402_1%~D

47K_0402_1%~D

DC_IN+ Source

8
7

5

12

PC6

PC6

0.1U_0603_25V7K~D

0.1U_0603_25V7K~D

12

PR18

PR18

47K_0402_1%~D

47K_0402_1%~D

13

D

D

NB_AC_OFF_R

2

G

PQ5

G

PQ5

S

S

12

PC12

PC12

0.1U_0603_25V7K~D

RHU002N06_SOT323

RHU002N06_SOT323

0.1U_0603_25V7K~D

12

PC7

PC7

0.1U_0603_25V7K~D

0.1U_0603_25V7K~D

PR172

PR172
0_0402_5%~D

0_0402_5%~D

1 2

+DC_IN_SS

12

12

PR15

PR15

12

PC9

PC9

4.7K_0805_5%~D

4.7K_0805_5%~D
10U_1206_25V6M~D

10U_1206_25V6M~D

3

PC8

PC8

0.1U_0603_25V7K~D

0.1U_0603_25V7K~D

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, MB A4042

SCHEMATIC, MB A4042

SCHEMATIC, MB A4042
401533

401533

401533

1

43 56Monday, December 17, 2007

43 56Monday, December 17, 2007

43 56Monday, December 17, 2007

A

A

A

of

of

of

5

4

3

2

1

D D

C C

B B

A A

+PWR_SRC

VOUT1=5V
L=4.7uF
Fsw=400KHz
D=0.265
Output Ripple Current=1.97A
Output Ripple Voltage=1.97A*25mOhm=49.37mV)
Input Ripple Current=TDC*(D*(1-D))^0.5=3.28A

Component select
Input CAP 10uF_1206_25V *2
Output Cap 330uF_D3L_6.3VM_R25(Sanyo_6TPE330ML)
H_MOSFET FDS8880
L_MOSFET FDS6676AS(5.9/7.25mOhm@4.5V, 14.5A)
Inductor 4.7U_HMU1356-4R7-R_10A(DELTA)

5 Volt +/-5%
Thermal Design Current:6.62A
Peck current: 9.46A
OCP min: 11.3A

+5V_ALWP

1

+

+

PC32

PC32

2

330U_D3L_6.3VM_R25~D

330U_D3L_6.3VM_R25~D

+5V_ALWP

+3.3V_ALWP

12

PC33

PC33

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

PAD-OPEN 4x4m

PAD-OPEN 4x4m

PAD-OPEN 4x4m

PAD-OPEN 4x4m

PAD-OPEN 4x4m

PAD-OPEN 4x4m

PAD-OPEN 4x4m

PAD-OPEN 4x4m

PJP2

PJP2

1 2

PAD-OPEN 4x4m

PAD-OPEN 4x4m

PR30

PR30

@

@

0_0603_5%~D

0_0603_5%~D

PR34

PR34

0_0603_5%~D

0_0603_5%~D

GNDA_3V5V

PJP34

PJP34

1 2

PJP6

PJP6

1 2

PJP7

PJP7

1 2

PJP35

PJP35

1 2

5

FDS8880_NL_SO8~D

FDS8880_NL_SO8~D

PL5

PL5

3.0UH_HMP1362-3R0-R_17A_20%~D

3.0UH_HMP1362-3R0-R_17A_20%~D

1 2

1 2

+5V_ALW

+3.3V_ALW

+DC1_PWR_SRC

12

PC13

PC13

2200P_0402_50V7K~D

2200P_0402_50V7K~D

8

PQ6

PQ6

D6D5D7D

4

G

S

S

S

3

2

1

12

NC

PC218

PC218

@

@

ALWON<38>

THERM_STP#<18>

786

12

1500P_0603_25V7K~D

1500P_0603_25V7K~D

1 2

5

PQ8

PQ8

FDS6676AS_NL_SO8~D

FDS6676AS_NL_SO8~D

4

123

PR231

PR231

@

@

4.7_1206_5%~D

4.7_1206_5%~D

PR38

PR38

2K_0402_5%~D

2K_0402_5%~D

PR39

PR39

0_0402_5%~D

0_0402_5%~D

12

PC14

PC14

0.1U_0805_50V7K

0.1U_0805_50V7K

12

12

12

12

PC15

PC15

PC16

PC16

10U_1206_25V6M~D

10U_1206_25V6M~D

10U_1206_25V6M~D

10U_1206_25V6M~D

12

PC28

PC28

@

@

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

GNDA_3V5V

PR168

PR168

0_0402_5%~D

0_0402_5%~D

EN_3V_5V

PR40

PR40

1 2

200K_0402_5%

200K_0402_5%

+15V_ALW

PAD-OPEN1x1m

PAD-OPEN1x1m

(100mA,20mils ,Via NO.=1)

4

+3.3V_ALWP/ +5V_ALWP/ +5V_ALW2 / +15V_ALWP

PJP3

PJP3

1 2

12

PC17

PC17

10U_1206_25V6M~D

10U_1206_25V6M~D

1 2

+5V_ALW_PHASE

+5V_ALWP

12

PC38

PC38

0.1U_0603_25V7K~D

0.1U_0603_25V7K~D

PJP5

PJP5

PR19

PR19

0_0805_5%

0_0805_5%

1 2

+3.3V_ALW2

12

PC24

PC24

1U_0603_25V7K~D

1U_0603_25V7K~D

GNDA_3V5V

PR28

PR28

150K_0402_1%~D

150K_0402_1%~D

1 2

ALW_PWRGD_3V_5V

+5V_ALW_UGATE

12

PC30

PC30

0.1U_0603_25V7K~D

0.1U_0603_25V7K~D

1 2

2
3

PD10

PD10

BAT54SW-7-F_SOT323-3~D

BAT54SW-7-F_SOT323-3~D

2
3

PD11

PD11

BAT54SW-7-F_SOT323-3~D

BAT54SW-7-F_SOT323-3~D

+15V_ALWP

12

PR20

PR20

0_0805_5%

0_0805_5%

1 2

GNDA_3V5V

+5V_ALWP

GNDA_3V5V

PR32

PR32

0_0402_5%~D

0_0402_5%~D

+5V_ALW_LGATE

PC36

PC36

0.1U_0603_25V7K~D

0.1U_0603_25V7K~D

1

1 2

PC39

PC39

0.1U_0603_25V7K~D

0.1U_0603_25V7K~D

1 2

1

12

PC40

PC40

0.1U_0603_25V7K~D

0.1U_0603_25V7K~D

+5V_ALW2

12

PC25

PC25

1U_0603_10V6K~D

1U_0603_10V6K~D

PU2

PU2

9

VSW

10

VOUT1

11

VFB1

12

TRIP1

13

PGOOD1

14

EN1

15

DRVH1

16

LL1

33

+5V_ALW_BOOT

3

PR42

PR42

200K_0402_1%~D

200K_0402_1%~D

PAD-OPEN1x1m

PAD-OPEN1x1m

EN_3V_5V

1

5

4

3

7

8

2

6

VIN

LDO

VREF3

V5FILT

TONSEL

EN_LDO

LDOREFIN

VBST117DRVL118V5DRV19SECFB20GND21PGND22DRVL223VBST2

PAD

1

24

+3.3V_ALW_BOOT

GNDA_3V5V

12

PC37

PC37

+5V_ALW2

4.7U_0603_6.3V6K~D

4.7U_0603_6.3V6K~D

PD12

PD12
BAT54CW_SOT323~D

BAT54CW_SOT323~D

2

12

PR43

PR43

1 2

39.2K_0402_1%~D

39.2K_0402_1%~D

GNDA_3V5V

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

PR21

@ PR21

@

10_0603_5%~D

10_0603_5%~D

12

PC23

PC23

4.7U_0805_6.3V6K

4.7U_0805_6.3V6K
PR22

PR22

0_0402_5%~D@

0_0402_5%~D@

1 2

PR23

PR23

0_0402_5%~D

0_0402_5%~D

1 2

PC27

PC27

0.1U_0603_25V7K~D

0.1U_0603_25V7K~D

1 2

1 2

PR24

@PR24

@

0_0603_5%~D

0_0603_5%~D

VREF2

32

REFIN2

31

TRIP2

30

VOUT2

29

SKIPSEL

28

PGOOD2

27

EN2

26

DRVH2

+3.3V_ALW_PHASE

25

LL2

SN0608098_QFN32_5X5~D

SN0608098_QFN32_5X5~D

0_0402_5%~D

0_0402_5%~D

1 2

1 2

PAD-OPEN1x1m

PAD-OPEN1x1m

GNDA_3V5V

3

+5V_VCC1

12

12

PC26

PC26

1U_0603_10V6K~D

1U_0603_10V6K~D

GNDA_3V5V

PR27

PR27

187K_0402_1%~D

187K_0402_1%~D

1 2

PR29 0_0402_5%~D

PR29 0_0402_5%~D

12

POK2

+3.3V_ALW_UGATE

12

PR33

PR33

+3.3V_ALW_LGATE

PJP4

PJP4

12

0_0402_5%~D

0_0402_5%~D
PR25

PR25

PR26

@PR26

@

0_0402_5%~D

0_0402_5%~D

1 2

PR169 0_0402_5%~D

PR169 0_0402_5%~D

GNDA_3V5V

PC31

PC31

0.1U_0603_25V7K~D

0.1U_0603_25V7K~D

12

GNDA_3V5V

EN_3V_5V

12

PC29

PC29

@

@

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

+3.3V_ALW

PR36

PR36

1 2

200K_0402_1%~D

200K_0402_1%~D

POK2

ALW_PWRGD_3V_5V

FDS6676AS_NL_SO8~D

FDS6676AS_NL_SO8~D

+3.3V_ALW

PR37

PR37

@

@

1 2

200K_0402_1%~D

200K_0402_1%~D

12

PR41

PR41

0_0402_5%~D

0_0402_5%~D

2

12

12

PC18

PC18

2200P_0402_50V7K~D

2200P_0402_50V7K~D

8

PQ7

PQ7

D6D5D7D

FDS8880_NL_SO8~D

FDS8880_NL_SO8~D

4

G

S

S

S

3

2

1

786

5

PQ9

PQ9

4

12

PC219

PC219

@

@

1500P_0603_25V7K~D

1500P_0603_25V7K~D

123

1 2

ALW_PWRGD_3V_5V <38>

12

12

12

PC19

PC19

PC20

PC20

PC21

PC21

PC22

0.1U_0805_50V7K

0.1U_0805_50V7K
10U_1206_25V6M~D

10U_1206_25V6M~D

PL6

PL6

3.0UH_HMP1362-3R0-R_17A_20%~D

3.0UH_HMP1362-3R0-R_17A_20%~D

NC

PR232

PR232

@

@

4.7_1206_5%~D

4.7_1206_5%~D

VOUT2=3.3V
L=3.0uF
Fsw=500KHz
D=0.176
Output Ripple Current=1.84A
Output Ripple Voltage=1.84A*25mOhm=46.05mV
Input Ripple Current=TDC*(D*(1-D))^0.5=3.28A

Component select
Input CAP 10uF_1206_25V *2
Output Cap 330uF_D3L_6.3VM_R25(Sanyo_6TPE330ML)
H_MOSFET FDS8880
L_MOSFET FDS6676AS(5.9/7.25mOhm@4.5V, 14.5A)
Inductor 3.0U_HMP1362-3R0-R_17A(DELTA)

PC22

10U_1206_25V6M~D

10U_1206_25V6M~D

10U_1206_25V6M~D

10U_1206_25V6M~D

3.3 Volt +/-5%
Thermal Design Current: 7.39A
Peak current: 10.56A
OCP min: 13A

+3.3V_ALWP

12

12

1

PR31

PR31

0_0402_5%~D

0_0402_5%~D

PR35

PR35

@

@

0_0402_5%~D

0_0402_5%~D

GNDA_3V5V

12

PC34

PC34

12

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

PC35

PC35

1

+

+

+

+

PC169

PC169

2

2

220U_V_6.3VM_R25M~D

220U_V_6.3VM_R25M~D

220U_V_6.3VM_R25M~D

220U_V_6.3VM_R25M~D

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, MB A4042

SCHEMATIC, MB A4042

SCHEMATIC, MB A4042
401533

401533

401533

1

44 56Monday, December 17, 2007

44 56Monday, December 17, 2007

44 56Monday, December 17, 2007

A

A

A

of

of

of

5

4

3

2

1

PJP8

PJP8

+PWR_SRC

D D

1 2

PAD-OPEN 4x4m

PAD-OPEN 4x4m

12

12

PC42

PC42

PC41

PC41

10U_1206_25V6M~D

10U_1206_25V6M~D

12

PC43

PC43

0.1U_0603_25V7K~D

0.1U_0603_25V7K~D
2200P_0402_50V7K~D

2200P_0402_50V7K~D

+DC2_PWR_SRC

1.5 Volt +/-5%
Thermal Design Current: 2.63A
Peak current: 3.76A
OCP min: 4.3A

C C

+1.5V_RUN_P

PL8

3.3UH_MPLC0730L3R3_6.5A_20%~D

3.3UH_MPLC0730L3R3_6.5A_20%~D

1

12

+

+

PC58

PC58

PC55

PC55

@

@

2

10U_1206_6.3V7K

10U_1206_6.3V7K

330U_D2E_2.5VM_R9

330U_D2E_2.5VM_R9

B B

VOUT1=1.5V
L=3.3uF
Fsw=200KHz
D=0.081
Output Ripple Current=2.15A
Output Ripple Voltage=2.15A*15mOhm=32.27mV
Input Ripple Current=TDC*(D*(1-D))^0.5=0.97A

Component select
Input CAP 10uF_1206_25V
Output Cap 220U_D2_4VM_R15(NEC_PSLV0G227M)
H_MOSFET SI4800BDY
L_MOSFET SI4810BDY(16/20mOhm@4.5V, 6A)
Inductor 3.3U_MPL73-3R3_6A(DELTA)

+1.5V_RUN_P +1.5V_RUN

A A

GNDA_1P5V_1P05V

PC59

PC59

1 2

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

1 2

PAD-OPEN 4x4m

PAD-OPEN 4x4m

PJP11

PJP11

PR55

PR55

1 2

0_0603_5%~D

0_0603_5%~D

@

@

PR56

PR56

0_0603_5%~D

0_0603_5%~D

1 2

@

@

PL8

12

PC220

PC220

@

@

1500P_0603_25V7K~D

1500P_0603_25V7K~D

+3.3V_ALW

12

PR233

PR233

@

@

1 2

EN2

4.7_1206_5%~D

4.7_1206_5%~D

EN1

100K_0402_1%~D

100K_0402_1%~D

0_0402_5%~D

0_0402_5%~D

1 2

PQ11

PQ11

SI4800BDY-T1_SO8~D

SI4800BDY-T1_SO8~D

3 6

241

8

D6D5D7D

G

PQ12

PQ12

S

S

S

3

2

1

SI4810BDY-T1-E3_SO8~D

SI4810BDY-T1-E3_SO8~D

+3.3V_SUS

PR60

PR60

@

@

100K_0402_1%~D

100K_0402_1%~D

1.05V_M_PWRGD

1.5V_RUN_PWRGD

PR171

PR171

0_0402_5%~D

0_0402_5%~D

1 2

PR62

@PR62

@

12

PR170

PR170

578

4

12

1 2

+3.3V_ALW

PR61

PR61

100K_0402_1%~D

100K_0402_1%~D

PR63

PR63

0_0402_5%~D

0_0402_5%~D

1 2

5

4

+1.5V_RUN / +1.05V_M/ +3.3V_RTC_LDO

PR44

PR44

1 2

0_0805_5%~D

0_0805_5%~D

+5V_VCC2

GNDA_1P5V_1P05V

PR48

PR48

12

0_0402_5%~D

0_0402_5%~D

1 2

PC63

PC63

PU3

PU3

PC51

PC51

12

0.1U_0402_10V7K~D

PR53

PR53

0.1U_0402_10V7K~D

@

@

1.5V_UGATE

1.5V_PHASE

1 2

+5V_ALW

PC60

PC60

1 2

GNDA_1P5V_1P05V

1 2

130K_0402_1%~D

130K_0402_1%~D

GNDA_1P5V_1P05V

1.05V_M_PWRGD <38>

1.5V_RUN_PWRGD <41>

1.5V_RUN_ON <37>

M_ON <38,40>

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

GNDA_1P5V_1P05V

1U_0603_10V6K~D

1U_0603_10V6K~D

9

VSW

10

VOUT1

11

VFB1

12

TRIP1

13

PGOOD1

EN1 EN2

14

EN1

15

DRVH1

16

LL1

33

GNDA_1P5V_1P05V

0.1U_0603_25V7K~D

0.1U_0603_25V7K~D
PR57

PR57

0_0402_5%~D

0_0402_5%~D

1.5V_LGATE

PR59

@ PR59

@

10_0603_5%~D

10_0603_5%~D

12

PC62

PC62

4.7U_0603_6.3V6K~D

4.7U_0603_6.3V6K~D

3

4

8

7

5

6

VIN

LDO

VREF3

LDOREFIN

SN0608098_QFN32_5X5~D

SN0608098_QFN32_5X5~D

VBST117DRVL118V5DRV19SECFB20GND21PGND22DRVL223VBST2

PAD

+5V_VCC2

12

PR46

PR46

0_0402_5%~D

0_0402_5%~D

PC49

PC49

0.1U_0603_25V7K~D

0.1U_0603_25V7K~D

REF

1 2

1 2

PR49

PR49

0_0402_5%~D@

0_0402_5%~D@

1 2

PR50

PR50

0_0603_5%~D@

0_0603_5%~D@

2

3

1

VREF2

V5FILT

TONSEL

EN_LDO

REFIN2

TRIP2

VOUT2
SKIPSEL
PGOOD2

EN2

DRVH2

LL2

24

0_0402_5%~D

0_0402_5%~D

1 2

GNDA_1P5V_1P05V

1.05V_LGATE

GNDA_1P5V_1P05V

PR45

PR45

1 2

0_0805_5%~D

0_0805_5%~D

1 2

PC48

PC48

1U_0603_25V7K~D

1U_0603_25V7K~D

12

GNDA_1P5V_1P05V

REFIN2_1_05

32
31

PR52 130K_0402_1%~DPR52 130K_0402_1%~D

30

PR54 0_0402_5%~D

PR54 0_0402_5%~D

29

1.05V_M_PWRGD1.5V_RUN_PWRGD

28
27

1.05V_UGATE

26

1.05V_PHASE

25

PC61

PC61

PR58

PR58

+3.3V_RTC_LDO

PC50

PC50

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1 2

1 2

0.1U_0603_25V7K~D

0.1U_0603_25V7K~D

PJP10

PJP10

PAD-OPEN1x1m

PAD-OPEN1x1m

OK to Short if CAD
System can Support

12

PR47

PR47

1 2

12

12

PR51

0_0402_5%~D

0_0402_5%~D

0_0402_5%~D

0_0402_5%~D

PC52

PC52

12

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

@

@

GNDA_1P5V_1P05V

GNDA_1P5V_1P05V

12

PR51

GNDA_1P5V_1P05V

2

PC44

10U_1206_25V6M~D

10U_1206_25V6M~D

8

D6D5D7D

PQ10

PQ10
FDS6298_SO8~D

FDS6298_SO8~D

4

G

S

S

S

3

2

1

578

3 6

241

+1.05V_MP +1.05V_M

12

PC221

PC221

@

@

PQ13

PQ13

1500P_0603_25V7K~D

1500P_0603_25V7K~D

@

@

FDS6299S_SO8~D

FDS6299S_SO8~D

1 2

VOUT2=1.05V
L=0.88uF
Fsw=300KHz
D=0.057
Output Ripple Current=3.88A
Output Ripple Voltage=3.88A*4.5mOhm=17.44mV
Input Ripple Current=TDC*(D*(1-D))^0.5=2.53A

Component select
Input CAP 10uF_1206_25V*2
Output Cap 330U_D2E_2.5VM_R9*2(Sanyo2R5TPE330M9)
H_MOSFET SI4682DY
L_MOSFET SI4362DY(4.2/5.5mOhm@4.5V, 15A)
Inductor 0.88U_MPC1040LR88_17A(NEC_TOKIN)

PC46

PC46

10U_1206_25V6M~D

10U_1206_25V6M~D

1.05 Volt +/-5%
Thermal Design Current: 7.89A
Peack current: 11.27A
OCP min: 13.8A

PL7

PL7

1.4UH_HMU1350-1R4PF_15A_20%~D

1.4UH_HMU1350-1R4PF_15A_20%~D

3

PR234

PR234

4.7_1206_5%~D

4.7_1206_5%~D

PJP9

PJP9

1 2

PAD-OPEN 4x4m

PAD-OPEN 4x4m

PJP12

PJP12

1 2

PAD-OPEN 4x4m

PAD-OPEN 4x4m

12

12

PC45

PC45

PC44

12

12

PC47

PC47

0.1U_0603_25V7K~D

0.1U_0603_25V7K~D
2200P_0402_50V7K~D

2200P_0402_50V7K~D

12

1

+

+

PC53

PC53

2

330U_D2E_2.5VM_R9

330U_D2E_2.5VM_R9

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, MB A4042

SCHEMATIC, MB A4042

SCHEMATIC, MB A4042

401533

401533

401533

1

+1.05V_MP

1

12

+

+

PC54

PC54

2

330U_D2E_2.5VM_R9

330U_D2E_2.5VM_R9

45 56Monday, December 17, 2007

45 56Monday, December 17, 2007

45 56Monday, December 17, 2007

PC57

PC57

PC56

PC56

@

@

1 2

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

10U_1206_6.3V7K

10U_1206_6.3V7K

A

A

A

of

of

of

5

4

3

2

1

PJP13

PJP13

PAD-OPEN 4x4m

+PWR_SRC

D D

1.8 Volt +/-5%
Thermal Design Current: 6.24A
Peck current: 8.91A
OCP min: 9.85A

+1.8V_SUSP

C C

1

1

+

+

+

PC71

PC71

330U_D2E_2.5VM_R15~D

330U_D2E_2.5VM_R15~D

+

PC72

PC72

2

2

330U_D2E_2.5VM_R15~D

330U_D2E_2.5VM_R15~D

PAD-OPEN 4x4m

1 2

1.4UH_HMU1350-1R4PF_15A_20%~D

1.4UH_HMU1350-1R4PF_15A_20%~D

12

PC73

PC73

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

PL9

PL9

1 2

3

PC64

PC64

10U_1206_25V6M~D

10U_1206_25V6M~D

@

@

1

PC65

PC65

2

+1.8VSUSP_L

12

PC222

PC222

1500P_0603_25V7K~D

1500P_0603_25V7K~D

@

@

1 2

10U_1206_25V6M~D

10U_1206_25V6M~D

PR235

PR235

1

12

PC66

PC66

2

0.1U_0603_25V7K~D

0.1U_0603_25V7K~D

8

D6D5D7D

S

S

S

3

2

1

3 5

241

4.7_1206_5%~D

4.7_1206_5%~D

+DDR_PWR_SRC

12

PC67

PC67

2200P_0402_50V7K~D

2200P_0402_50V7K~D

PQ14

PQ14
FDS6298_SO8~D

FDS6298_SO8~D

4

G

TPS51116_DRVL

PQ15

PQ15
FDMS8670AS_POWER56-8_5P~D

FDMS8670AS_POWER56-8_5P~D

1.8V_SUS_PWRGD<38>

0.9V_DDR_VTT_ON<37>

TPS51116_DRVH

DDR_ON<38>

+5V_ALW

PC68

PC68

0.22U_0603_10V7K~D

0.22U_0603_10V7K~D

1 2

+3.3V_ALW

PR68

PR68
200K_0402_1%~D

200K_0402_1%~D

1 2

12

PC75

PC75

1U_0603_10V6K~D

1U_0603_10V6K~D

21

PD13

PD13

RB751V-40_SOD323~D

RB751V-40_SOD323~D

@

@

PR64

PR64

0_0603_5%~D

0_0603_5%~D

PR66

PR66

5.9K_0402_1%~D

5.9K_0402_1%~D

PR70

PR70

1 2

0_0402_5%~D

0_0402_5%~D

PR71

PR71

5.1_0402_1%~D

5.1_0402_1%~D

12

12

12

GNDA_DDRGNDA_DDR

DDR2 Termination

PU4

PU4

22

VBST

21

DRVH

20

LL

19

DRVL

18

PGND_D

16

CS

14

V5FILT

13

PGOOD

11

S5

10

S3

12

PC76

PC76
1U_0603_10V6K~D

1U_0603_10V6K~D

+5V_ALW

12

NC

V5IN

15

GNDA_DDR

7

NC

VLDOIN

VTTGND

VTTSNS

MODE

VTTREF

COMP

VDDQSNS

VDDQSET

CS_GND

TP

TPS51116RGE_QFN24_4X4~D

TPS51116RGE_QFN24_4X4~D

17

25

+1.8V_SUSP

12

PC216

PC216
1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

23

24

VTT

1

2

3

GNDA_DDR

GND

4

5

6

8

9

1

PC70

PC70

PC69

PC69

2

10U_0805_6.3V6M~D

10U_0805_6.3V6M~D

10U_0805_6.3V6M~D

10U_0805_6.3V6M~D

+V_DDR_MCH_REF

12

1

1

PC171

PC171

2

2

10U_0805_6.3V6M~D

10U_0805_6.3V6M~D

PC74

PC74

0.033U_0603_16V6K~D

0.033U_0603_16V6K~D

12

PC170

PC170

@

@

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

+0.9V_DDR_VTTP

+1.8V_SUSP

PR65

PR65
0_0402_5%~D

0_0402_5%~D

1 2

PR69
0_0402_5%~D

0_0402_5%~D

1 2

+5V_ALW

PR67

PR67

0_0402_5%~D

0_0402_5%~D

@PR69

@

Design current 0.7A for +0.9V_DDR_VTTP

@

@

12

GNDA_DDR

Peak current 1A for +0.9V_DDR_VTTP

+1.8VSUSP/ +0.9V_DDR_VTT

B B

A A

PR225

@PR225

@

27.4K_0402_1%~D

27.4K_0402_1%~D

1 2

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

1 2

+5V_ALW

PR226

@PR226

@

17.4K_0603_1%~D

17.4K_0603_1%~D

1 2

PR174

PR174

0_0402_5%~D

0_0402_5%~D

GNDA_DDR

PJP14

PJP14

12

PAD-OPEN1x1m

GNDA_DDR

+1.8V_SUSP

+0.9V_DDR_VTTP

PAD-OPEN1x1m

PJP15

PJP15

PAD-OPEN 4x4m

PAD-OPEN 4x4m

1 2

PJP16

PJP16

PAD-OPEN 4x4m

PAD-OPEN 4x4m

1 2

PJP17

PJP17

2 1

PAD-OPEN 2x2m~D

PAD-OPEN 2x2m~D

+1.8V_MEM

+0.9V_DDR_VTT

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, MB A4042

SCHEMATIC, MB A4042

SCHEMATIC, MB A4042

401533

401533

401533

1

46 56Monday, December 17, 2007

46 56Monday, December 17, 2007

46 56Monday, December 17, 2007

A

A

A

of

of

of

8

7

6

5

4

3

2

1

+CPU_PWR_SRC

H H

+CPU_PWR_SRC

PR73

PR73
10_0603_5%~D

G G

+5V_ALW

PR77

PR77

1 2

10_0603_5%~D

10_0603_5%~D

F F

E E

GNDA_VCORE

H_DPRSTP#<8,10,23>

DPRSLPVR<10,24>

H_PSI#<8>

D D

PWR_MON<18>

PC101

@PC101

@

1U_0603_10V6K~D

1U_0603_10V6K~D

GNDA_VCORE

RUNPWROK<37,38,41>

IMVP_VR_ON<37>

10KB_0603_1%_ERTJ1VG103FA~D

10KB_0603_1%_ERTJ1VG103FA~D

C C

B B

A A

GNDA_VCORE

0_0402_5%~D

0_0402_5%~D

2200P_0402_50V7K~D

2200P_0402_50V7K~D

470p_0402_50V7K~D

470p_0402_50V7K~D

VID0<8>
VID1<8>
VID2<8>
VID3<8>
VID4<8>
VID5<8>
VID6<8>

PR99

@PR99

@

10K_0402_5%~D

10K_0402_5%~D

1 2

PH2

PH2

PR109

PR109

4.99K_0402_1%

4.99K_0402_1%

VSSSENSE<8>

PR113

@PR113

@

332_0402_1%~D

332_0402_1%~D

0.01U_0402_25V7K~D

0.01U_0402_25V7K~D

12

PR128

PR128

0_0402_5%~D

0_0402_5%~D

PR82

PR82

147K_0402_1%~D

147K_0402_1%~D

12

PR84

@PR84

@

12

PC92

@PC92

@

12

PC98

PC98

12

0_0402_5%~D

0_0402_5%~D
0_0402_5%~D

0_0402_5%~D
0_0402_5%~D

0_0402_5%~D

0_0402_5%~D

0_0402_5%~D

12

PR105 0_0402_5%~D@ PR105 0_0402_5%~D@

12

12

GNDA_VCORE

12

@PC111

@

680P_0402_50V7K~D

680P_0402_50V7K~D

1 2

PC117

@ PC117

@

1500P_0402_50V7K~D

1500P_0402_50V7K~D
PC120

PC120

1 2

8

PR87

PR87

PR86

PR86

0_0402_5%~D

0_0402_5%~D

12

PR89

PR89

PR88

PR88

0_0402_5%~D

0_0402_5%~D

12

PR93

PR93

PR92

PR92

0_0402_5%~D

0_0402_5%~D

12

PR94

PR94

0_0402_5%~D

0_0402_5%~D

PR98

PR98

499_0402_1%~D

499_0402_1%~D

12

PR102

PR102

0_0402_5%~D

0_0402_5%~D

12

12

VCCSENSE<8>

PC104 1000P_0402_50V7K~D

PC104 1000P_0402_50V7K~D

PC105 1000P_0402_50V7K~D

PC105 1000P_0402_50V7K~D

1 2

PC111

PR116

@PR116

@

1.69K_0402_1%~D

1.69K_0402_1%~D

82.5K_0402_1%~D

82.5K_0402_1%~D

1000P_0402_50V7K~D

1000P_0402_50V7K~D

909_0402_1%~D

909_0402_1%~D

PR96

PR96

PR110

PR110
0_0402_5%~D

0_0402_5%~D

@PC121

@

PR129

PR129

12

PC90

PC90

1U_0603_10V6K~D

1U_0603_10V6K~D

GNDA_VCORE

PAD~D

PAD~D

IMVP6_PROCHOT#

T1

T1

@

@

PH1

@PH1

@

12

100K_0603_5%_ERTJ1VV104J~D

100K_0603_5%_ERTJ1VV104J~D

12
12
12
12

12

@

CLK_ENABLE#

T2PAD~D@T2PAD~D

PR104 10_0402_1%~D

PR104 10_0402_1%~D

12

12

12

12

PR115

PR115

6.49K_0603_1%~D

6.49K_0603_1%~D

12

12

PR118

PR118

71.5K_0402_1%~D

71.5K_0402_1%~D

12

PR121

@PR121

@

PC121

12

12

GNDA_VCORE

12

12

@

@

PR83

PR83

PR130

PR130

1K_0402_1%~D

1K_0402_1%~D

PC127

@ PC127

@

0.01U_0402_16V7K~D

0.01U_0402_16V7K~D

7

12

0_0603_5%~D

0_0603_5%~D

PR85

PR85

28
29
30
31
32
33
34

37
36

38
35
12
13

11

10

41

GNDA_VCORE

0_0402_5%~D

0_0402_5%~D

330P_0402_50V7K~D

330P_0402_50V7K~D

12

12

1

2

GNDA_VCORE

13K_0402_1%

13K_0402_1%

4
3
5
6

1
2

9

8

@PC122

@

PC123

PC123

10_0603_5%~D

@

@

1 2

12

PC88

PC88

0.01U_0402_25V7K~D@

0.01U_0402_25V7K~D@

+3.3V_RUN

19

18

39

20

PU7

PU7

N.C.

VCC

GND
VRHOT
OSC
THRM
CCV

D0
D1
D2
D3
D4
D5
D6

DPRSTP
DPRSLPVR
PSI
PGD_IN
CLKEN
SHDN
FBS
GNDS

VPS

TIME

REF

TRC
TP

@PR122

@

PC122

V3P3

PWM1

CSP1

PWM2

CSP2

DRSKP

PWM3

CSP3

ILIMPK

PWR

MAX8786GTL+_TQFN40_6X6~D

MAX8786GTL+_TQFN40_6X6~D

CSN215CSN1

CSN3

14

CSN2

CSN3

PR122

1000P_0402_50V7K~D

1000P_0402_50V7K~D

@PR123

@

0_0402_5%~D

0_0402_5%~D

12

12

12

PC125

PC125

1000P_0402_50V7K~D

1000P_0402_50V7K~D

PR79

PR79

1.91K_0603_1%~D

1.91K_0603_1%~D

1 2

40

IMVPOK

27

23

26

22

24

25

21

7

17

16

PR112

@ PR112

@

VO

PR123

12

GNDA_VCORE

4.53K_0402_1%~D

4.53K_0402_1%~D

12

PC115

@ PC115

@

0.33U_0603_10V7K

0.33U_0603_10V7K

1 2

IMVP_PWRGD <24,37,41>

VSUM

PC112

@ PC112

@

2

1

1

2

PC116

@ PC116

@

0.01U_0402_16V7K~D

0.01U_0402_16V7K~D

PC126

PC126

1000P_0402_50V7K~D

1000P_0402_50V7K~D

6

PR106

PR106

226K_0402_1%~D

226K_0402_1%~D

PR107

@PR107

@

11.5K_0402_1%~D

11.5K_0402_1%~D

PR111

@ PR111

@

1 2

0.033U_0402_16V7K~D

0.033U_0402_16V7K~D

12

PH3

@ PH3

@

12

GNDA_VCORE

12

12

2.43K_0402_1%~D

2.43K_0402_1%~D

12

PR117

PR117

17.8K_0402_1%~D

17.8K_0402_1%~D

12

PR124

@ PR124

@

15K_0402_1%~D

15K_0402_1%~D

6.8KB_0603_5%_ERTJ1VR682J~D

6.8KB_0603_5%_ERTJ1VR682J~D

12

PC124

PC124

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

+5V_ALW

12

PC85

PC85

1U_0603_10V6K~D

1U_0603_10V6K~D

12

PR131

PR131

5

PU5

PU5

5

VDD

6

SKIP

2

PWM

3

GND

9

EP

MAX8791GTA+_TQFN8_3X3~D

MAX8791GTA+_TQFN8_3X3~D

+5V_ALW

12

PC95

PC95

PU6

PU6

1U_0603_10V6K~D

1U_0603_10V6K~D

5

VDD

6

SKIP

2

PWM

3

GND

9

EP

MAX8791GTA+_TQFN8_3X3~D

MAX8791GTA+_TQFN8_3X3~D

+5V_ALW

12

PC109

PC109

PU8

PU8

5

VDD

1U_0603_10V6K~D

1U_0603_10V6K~D

6

SKIP

2

PWM

3

GND

9

EP

MAX8791GTA+_TQFN8_3X3~D

MAX8791GTA+_TQFN8_3X3~D

PWR_MON <18>

22.1K_0402_1%~D

22.1K_0402_1%~D

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

BST

DH

LX

DL

BST

DH

LX

DL

BST

DH

LX

DL

PR74

PR74

0_0603_5%~D

0_0603_5%~D

1
8
7
4

PR91

PR91
0_0603_5%~D

0_0603_5%~D

1
8
7
4

PR114

PR114

0_0603_5%~D

0_0603_5%~D

1
8
7
4

12

UGATE1

LGATE1

12

UGATE2

LGATE2

0.22U_0603_10V7K~D

0.22U_0603_10V7K~D

12

UGATE3

LGATE3

4

SI4686DY-T1-E3_SO8~D

SI4686DY-T1-E3_SO8~D

0.22U_0603_10V7K~D

0.22U_0603_10V7K~D

1 2

0.22U_0603_10V7K~D

0.22U_0603_10V7K~D

1 2

PC113

PC113

1 2

PQ16

PQ16

PC86

PC86

3

D

2

G

S

1

SI4686DY-T1-E3_SO8~D

SI4686DY-T1-E3_SO8~D

PC99

PC99

3

D

2

G

S

1

PQ20

PQ20

SI4686DY-T1-E3_SO8~D

SI4686DY-T1-E3_SO8~D

3

D

2

G

S

1

4

FDMS8670AS_POWER56-8_5P~D

FDMS8670AS_POWER56-8_5P~D

PQ18

PQ18

4

PQ19

PQ19

FDMS8670AS_POWER56-8_5P~D

FDMS8670AS_POWER56-8_5P~D

4

PQ21

PQ21

FDMS8670AS_POWER56-8_5P~D

FDMS8670AS_POWER56-8_5P~D

12

PC77

PC77

8

0.1U_0603_25V7K~D

0.1U_0603_25V7K~D

D6D5D7D

G

S

S

S

3

2

1

PQ17

PQ17

8

D6D5D7D

G

S

S

S

3

2

1

8

D6D5D7D

G

S

S

S

3

2

1

@

@

PHASE1

@

@

@

@

PC114

PC114

@

@

PC118

PC118

@

@

3

PC87

PC87

PC91

PC91

1000P_0603_25V7K~D

1000P_0603_25V7K~D

1500P_0603_25V7K~D

1500P_0603_25V7K~D

@

@

1 2

12

1000P_0603_25V7K~D

1000P_0603_25V7K~D

12

1500P_0603_25V7K~D

1500P_0603_25V7K~D

@

@

1 2

1 2

12

PC100

PC100

@

@

1000P_0603_25V7K~D

1000P_0603_25V7K~D

12

PC102

PC102

1500P_0603_25V7K~D

1500P_0603_25V7K~D

1 2

PR108

PR108

@

@

1 2

12

PHASE3

12

@

@

1 2

12

12

PC78

PC78

PC79

PC79

0.1U_0603_25V7K~D

0.1U_0603_25V7K~D
2200P_0402_50V7K~D

2200P_0402_50V7K~D

PR72

PR72

2.4_0805_1%~D

2.4_0805_1%~D

2K_0402_1%~D

2K_0402_1%~D

PR75

PR75

7.68K_0805_1%~D

7.68K_0805_1%~D

2.4_0805_1%~D

2.4_0805_1%~D

1 2

VSUM

PR90

PR90

12

@

@

PC93

PC93

PC94

PC94

2.4_0805_1%~D

2.4_0805_1%~D

0.1U_0603_25V7K~D

0.1U_0603_25V7K~D

PHASE2

PR95

PR95

@

@

2.4_0805_1%~D

2.4_0805_1%~D

+CPU_PWR_SRC

2.4_0805_1%~D

2.4_0805_1%~D

0.45UH_ETQP4LR45XFC_25A_20%~D

0.45UH_ETQP4LR45XFC_25A_20%~D

2K_0402_1%~D

2K_0402_1%~D

PR119

PR119

2.4_0805_1%~D

2.4_0805_1%~D

7.68K_0805_1%~D

7.68K_0805_1%~D

1 2

VSUM

12

PC80

PC80

10U_1206_25V6M~D

10U_1206_25V6M~D

0.45UH_ETQP4LR45XFC_25A_20%~D

0.45UH_ETQP4LR45XFC_25A_20%~D

4
3

PR78

PR78

1 2

PR80

@PR80

@

12

PC96

PC96

2200P_0402_50V7K~D

2200P_0402_50V7K~D

10U_1206_25V6M~D

10U_1206_25V6M~D

2K_0402_1%~D

2K_0402_1%~D

1 2

PR101

7.68K_0805_1%~D

7.68K_0805_1%~D

1 2

VSUM

12

PC106

PC106

PC108

PC108

10U_1206_25V6M~D

10U_1206_25V6M~D

1
2

PR125

PR125

1 2

PR126

@PR126

@

1

+

+

PC82

PC82

2

100U_25V_M~D

100U_25V_M~D

1
2

PC89

PC89

12

12

10U_1206_25V6M~D

10U_1206_25V6M~D

PL12

PL12

0.22U_0603_10V7K~D

0.22U_0603_10V7K~D

12

PC110

PC110

0.1U_0603_25V7K~D

0.1U_0603_25V7K~D
2200P_0402_50V7K~D

2200P_0402_50V7K~D

4
3

PC119

PC119

12

PR276

PR276

0_0402_5%~D

0_0402_5%~D

PC83

PC83

PC103

PC103

12

12

CSN3

1

+

+

2

100U_25V_M~D

100U_25V_M~D

1
2

12

PR275

PR275

1 2

12

VO

12

PC81

PC81

10U_1206_25V6M~D

10U_1206_25V6M~D

PL11

PL11

0.22U_0603_10V7K~D

0.22U_0603_10V7K~D

+CPU_PWR_SRC

12

PC97

PC97

0.45UH_ETQP4LR45XFC_25A_20%~D

0.45UH_ETQP4LR45XFC_25A_20%~D

4
3

PR100

PR100

@PR101

@

12

PC107

PC107

10U_1206_25V6M~D

10U_1206_25V6M~D
PL13

PL13

0.22U_0603_10V7K~D

0.22U_0603_10V7K~D

DELL CONFIDENTIAL/PROPRIETARY

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

Date: Sheet

2

PL10

@ PL10

@

FBMJ4516HS720NT_1806~D

FBMJ4516HS720NT_1806~D

1 2

PJP18

PJP18

1 2

1

+

+

PAD-OPEN 4x4m

PAD-OPEN 4x4m

PC84

PC84

2

100U_25V_M~D

100U_25V_M~D

Iccmax=44A
I_TDC=35A
OCP=65A, Intel spec=50A

+VCC_CORE

PR76

PR76
0_0402_5%~D

0_0402_5%~D

1 2

12

PR81

PR81
0_0402_5%~D

0_0402_5%~D

VO

+VCC_CORE

PR97

PR97
0_0402_5%~D

0_0402_5%~D

1 2

12

12

PR103

@PR103

@

10_0402_1%~D

10_0402_1%~D

0_0402_5%~D

0_0402_5%~D

VO

CSN2

+VCC_CORE

PR120

PR120
0_0402_5%~D

0_0402_5%~D

PR127

@PR127

@

10_0402_1%~D

10_0402_1%~D

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

SCHEMATIC, MB A4042

SCHEMATIC, MB A4042

SCHEMATIC, MB A4042
401533

401533

401533

+PWR_SRC

A

A

47 56Monday, December 17, 2007

47 56Monday, December 17, 2007

47 56Monday, December 17, 2007

1

A

of

of

of

5

PQ22

PQ22

SI4835BDY-T1-E3_SO8~D

SI4835BDY-T1-E3_SO8~D

8

+DC_IN_SS

D D

2

G

G

PR141

PR141

309K_0402_1%

309K_0402_1%

PR145

PR145

49.9K_0402_1%~D

49.9K_0402_1%~D

12

PC136

0.01U_0402_25V7K~D

0.01U_0402_25V7K~D

GNDA_CHG

CKG_SMBCLK<6,27,38>
CKG_SMBDAT<6,27,38>

PC136

12

+3.3V_ALW

PC143

PC143

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

C C

B B

A A

PR134

PR134

10K_0402_5%~D

10K_0402_5%~D

13

D

D

PQ24

PQ24
RHU002N06_SOT323

RHU002N06_SOT323

S

S

+DC_IN_SS

ISL88731_VDDP

1 2

ACAV_IN_NB<38>

12

GNDA_CHG

ISL88731_ICM<18>

7
5

12

PR142

@PR142

@

10K_0402_1%~D

10K_0402_1%~D

12

1
2
36

4

100K_0402_5%~D

100K_0402_5%~D

ACAV_IN_DOCK<38,49>

ISL88731_VREF

PR143

PR143

12

PR147

@PR147

@

15.8K_0402_1%~D

15.8K_0402_1%~D

PR155

PR155

@

@

16.2K_0402_1%~D

16.2K_0402_1%~D

PR135

PR135

10K_0402_5%~D

10K_0402_5%~D

12

12

12

12

PC149

PC149

220P_0402_25V8K~D

220P_0402_25V8K~D

ISL88731_ICM

PR146

PR146

1 2

0_0402_5%~D

0_0402_5%~D

1 2

PR150

PR150

200K_0402_5%~D

200K_0402_5%~D

12

PR152

PR152

4.7K_0402_5%~D

4.7K_0402_5%~D

120P_0402_50VNPO~D

120P_0402_50VNPO~D

1 2

12

PC150

@PC150

@

0.01U_0402_25V7K~D

0.01U_0402_25V7K~D

1 2

8.45K_0402_5%~D

8.45K_0402_5%~D

@ PR164

@

33.2K_0402_1%~D

33.2K_0402_1%~D

1 2

T43PAD~D T43PAD~D

2

G

G

PC148

PC148

PR161

PR161

PR164

13

D

D

S

S

PC151

PC151

@

@

ISL88731_VREF

PC162

PC162

GNDA_CHG GNDA_CHG

5

+DC_IN

PQ66

PQ66

RHU002N06_SOT323

RHU002N06_SOT323

12

0.01U_0402_25V7K~D

0.01U_0402_25V7K~D

12

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

4

12

PR136

PR136

10K_0402_5%~D

10K_0402_5%~D

12

PR139

PR139

33K_0402_5%~D

33K_0402_5%~D

2200P_0402_50V7K~D

2200P_0402_50V7K~D

PC147

PC147

1 2

56P_0402_50VNPO~D

56P_0402_50VNPO~D

12

PC152

@PC152

@

0.01U_0402_25V7K~D

0.01U_0402_25V7K~D

12

PR162

PR162

51.1K_0402_1%~D

51.1K_0402_1%~D

12

PR165

PR165

17.8K_0402_1%

17.8K_0402_1%
PC164

PC164

12

PR167

PR167

GNDA_CHG

348_0402_1%~D

348_0402_1%~D

4

+SDC_IN

12

PR133

PR133

33K_0402_5%~D

33K_0402_5%~D

12

PR137

PR137

10K_0402_5%~D

10K_0402_5%~D

13

D

D

2

G

G

S

S

@

@

12

PC131

PC131

TBD_0603_25V7K~D

TBD_0603_25V7K~D

PC135

PC135

1U_0805_25V6K~D

1U_0805_25V6K~D

GNDA_CHG

12

1 2

PC145

PC145

7.5K_0402_5%~D

7.5K_0402_5%~D

ISL88731_VREF

PR154

PR154

1 2

10K_0402_5%~D

10K_0402_5%~D

12

PC153

PC153

1U_0603_10V6K~D

1U_0603_10V6K~D

GNDA_CHG

GNDA_CHG

Throttle_ICREF

1 2

12

PR228

PR228

@

@

200K_0402_1%~D

200K_0402_1%~D

12

12

PC165

PC165

100P_0402_50V8J

100P_0402_50V8J

0.01U_0402_25V7K~D

0.01U_0402_25V7K~D

GNDA_CHG GNDA_CHG GNDA_CHG GNDA_CHG

PQ26

PQ26

RHU002N06_SOT323

RHU002N06_SOT323

12

ISL88731_ICM

PR151

PR151

PC154

PC154

@

@

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

PR229

PR229
0_0402_5%~D

0_0402_5%~D

PC166

PC166

100P_0402_50V8J

100P_0402_50V8J

@

@

12

PC129

PC129

TBD_0603_25V7K~D

TBD_0603_25V7K~D

PC132

PC132

0.1U_0603_25V7K~D

0.1U_0603_25V7K~D

1 2

Throttle_ICREF

GNDA_CHG

22

2
13
11
10

9
14

8

6

5

4

3

7

12

12

29

PR159

PR159

1M_0402_1%~D

1M_0402_1%~D

1 2

GNDA_CHG

4

2

G

IN-

3

IN+

P

8

12

+5V_ALW

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

PR132

PR132

0.01_1206_1%~D

0.01_1206_1%~D

1
2

13

1

1

2

2

2

PQ25

PQ25

3

3

NTR4502PT1G_SOT23-3~D

NTR4502PT1G_SOT23-3~D

PR138

PR138

10K_0402_5%~D

10K_0402_5%~D

PC133

PC133

0.1U_0603_25V7K~D

0.1U_0603_25V7K~D

1 2

1

28

PU9

PU9

DCIN

CSSP

ICREF

ACIN
ACOK
VDDSMB
SCL
SDA
NC
VICM
FBO
EAI
EAO

VREF

CE

GND
TP

BQ24745RHDR_QFN28_5X5~D

BQ24745RHDR_QFN28_5X5~D

PU10A

PU10A
LM393DR_SO8~D

LM393DR_SO8~D

1

O

12

PC168

PC168

PC167

PC167

100P_0402_50V8J

100P_0402_50V8J

0.01U_0402_25V7K~D

0.01U_0402_25V7K~D

3

4
3

13

1

1

2

2

2

PQ23

PQ23

3

3

NTR4502PT1G_SOT23-3~D

NTR4502PT1G_SOT23-3~D

12

12

@

@

PR140

PR140

0_0402_5%~D

0_0402_5%~D

27

CSSN

UGATE
PHASE

12

Throttle_ICOUT

26

ICOUT

BOOT

VDDP

LGATE

PGND

CSOP

CSON

VFB

NC

GNDA_CHG GNDA_CHG GNDA_CHG

PR144

PR144
0_0603_5%~D

0_0603_5%~D

25

1 2

PC137

PC137

ISL88731_VDDP

21

0.1U_0603_25V7K~D

24
23

12

20

19
18

17
15
16

+5V_ALW +3.3V_ALW

12

PR163

PR163

100K_0402_1%~D

100K_0402_1%~D

12

PC163

PC163

@

@

10P_0402_50V8J~D

10P_0402_50V8J~D

3

0.1U_0603_25V7K~D

PR149

PR149

12

0_0603_5%~D

0_0603_5%~D

PC144

@ PC144

@

220P_0402_50V7K~D

220P_0402_50V7K~D

PR157

PR157

1 2

0_0402_5%~D

0_0402_5%~D

Throttle_ICOUT

12

PR160

PR160

100K_0402_5%~D

100K_0402_5%~D

PR230

PR230

@

@

200K_0402_1%~D

200K_0402_1%~D

2

G

G

PQ31

PQ31
RHU002N06_SOT323

RHU002N06_SOT323

12

12

13

D

D

S

S

@PC134

@

1U_0603_10V6K~D

1U_0603_10V6K~D

1 2

PD14

PD14

1U_0603_10V6K~D

1U_0603_10V6K~D

2 1

RB751V_SOD323~D

RB751V_SOD323~D

CHG_UGATE

CHG_LGATE

PBATT+

PJP19

PJP19

1 2

PAD-OPEN 4x4m

PAD-OPEN 4x4m

PC128

PC128

@

@

DOCK_DCIN_IS+ <35>
DOCK_DCIN_IS- <35>

PC134

1 2

@ PR148

@

33_0603_1%~D

33_0603_1%~D

PC138

PC138

1 2

GNDA_CHG

12

PR166

PR166

GNDA_CHG GNDA_CHG

PR148

1K_0402_5%~D

1K_0402_5%~D

GNDA_CHG

1 2

ADAPT_OC <37>

12

PC130

PC130

@

@

2200P_0402_50V7K~D

2200P_0402_50V7K~D

578

3 6

12

+VCHGR_B

PC146

PC146

@

@

3300PF_0402_50V7K~D

3300PF_0402_50V7K~D

4

G

3

PJP20

PJP20

PAD-OPEN1x1m

PAD-OPEN1x1m

+5V_ALW

8

5

P

IN+

6

IN-

G

4

2

CHAGER_SRC+PWR_SRC

12

0.1U_0603_25V7K~D

0.1U_0603_25V7K~D

578

PQ28

PQ28

SI4800BDY-T1_SO8~D

SI4800BDY-T1_SO8~D

3 6

241

PL14

PL14

5.6U_HMU1356-5R6_8.8A_20%~D

5.6U_HMU1356-5R6_8.8A_20%~D

12

PC217

PC217

@

@

0.1U_0603_25V7K~D

0.1U_0603_25V7K~D

1500P_0603_25V7K~D

1500P_0603_25V7K~D

PR227

PR227

@

@

1 2

4.7_1206_5%~D

4.7_1206_5%~D

GNDA_CHG

PC160

PC160

1 2

PC142

PC142

+VCHGR_L

12

0_0402_5%~D

0_0402_5%~D

PR158

PR158

12

PC139

PC139

0.1U_0603_25V7K~D

0.1U_0603_25V7K~D

2200P_0402_50V7K~D

2200P_0402_50V7K~D

PR153

PR153

0.01_1206_1%~D

0.01_1206_1%~D

1
2

12

PC161

PC161

0.1U_0603_25V7K~D

0.1U_0603_25V7K~D

1 2

241

D6D5D7D

S

2

PQ27

PQ27

SI4800BDY-T1_SO8~D

SI4800BDY-T1_SO8~D

8

PQ29

PQ29

S

S

1

SI4810BDY-T1-E3_SO8~D

SI4810BDY-T1-E3_SO8~D

Maximum charging current is 6.24A

7

O

PU10B

PU10B
LM393DR_SO8~D

LM393DR_SO8~D

DELL CONFIDENTIAL/PROPRIETARY

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

2

Date: Sheet

1

12

12

12

PC140

PC140

PC141

PC141

10U_1206_25V6M~D

10U_1206_25V6M~D

10U_1206_25V6M~D

10U_1206_25V6M~D

PBATT+

4
3

12

12

PC155

PC155

0.1U_0603_25V7K~D

0.1U_0603_25V7K~D

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

SCHEMATIC, MB A4042

SCHEMATIC, MB A4042

SCHEMATIC, MB A4042
401533

401533

401533

12

PC156

PC156

PC157

PC157

10U_1206_25V6M~D

10U_1206_25V6M~D

10U_1206_25V6M~D

10U_1206_25V6M~D

1

12

PC158

PC158

10U_1206_25V6M~D

10U_1206_25V6M~D

ACAV_IN_NB

48 56Tuesday, December 18, 2007

48 56Tuesday, December 18, 2007

48 56Tuesday, December 18, 2007

12

@PR156

@

12

PR156

1.8K_1206_5%~D

PC159

PC159

@

@

2200P_0402_50V7K~D

2200P_0402_50V7K~D

2

G

G

of

of

of

1.8K_1206_5%~D

13

D

D

PQ30

PQ30

S

S

@

@

RHU002N06_SOT323

RHU002N06_SOT323

A

A

A

5

+DOCK_PWR_BAR

D D

+3.3V_ALW2

12

PR299

PR299

100K_0402_5%~D

ACAV_IN_DOCK#<35,38>

C C

100K_0402_5%~D

2

RHU002N06_SOT323

RHU002N06_SOT323

+3.3V_ALW2

12

13

D

D

G

G

S

S

PR300

PR300

100K_0402_5%~D

100K_0402_5%~D

PQ67

PQ67
RHU002N06_SOT323

RHU002N06_SOT323

4

13

D

D

2

G

G

PQ37

PQ37

S

S

ACAV_IN_DOCK <38,48>

+3.3V_ALW +3.3V_ALW

12

12

12

PR271

100K_0402_5%~D

100K_0402_5%~D

22K_0402_5%~D

22K_0402_5%~D

2

G

G

PR271

100K_0402_5%~D

100K_0402_5%~D

13

D

D

PQ51

PQ51
RHU002N06_SOT323

RHU002N06_SOT323

S

S

PR199

PR199

PR273

PR273

2

G

G

2

G

G

PBATT_OFF<37>

12

PR272

PR272

100K_0402_5%~D

100K_0402_5%~D

13

D

D

PQ50

PQ50
RHU002N06_SOT323

RHU002N06_SOT323

S

S

+5V_ALW

12

PR274

PR274

22K_0402_5%~D

22K_0402_5%~D

13

D

D

PQ52

PQ52
RHU002N06_SOT323

RHU002N06_SOT323

S

S

3

NB_AC_OFF <37,43>

NB_AC_OFF_BJT <43>

PBATT+

16

IMD2AT-108_SC74-6~D

IMD2AT-108_SC74-6~D

5

PQ40A

PQ40A
IMD2AT-108_SC74-6~D

IMD2AT-108_SC74-6~D

2

PQ40B

PQ40B

4 3

B540C~D

B540C~D

2 1

FDS6679AZ_SO8~D

FDS6679AZ_SO8~D
PQ34

PQ34

8
7

5

PR202

PR202

240K_0402_5%~D

240K_0402_5%~D

1 2

PD16

PD16

1
2
36

4

12

PR200

PR200

47K_0402_1%~D

47K_0402_1%~D

FDS6679AZ_SO8~D

FDS6679AZ_SO8~D

1
2
3 6

2

12

12

PC192

PC192

0.47U_0805_25V7K~D

0.47U_0805_25V7K~D

IMD2AT-108_SC74-6~D

IMD2AT-108_SC74-6~D

PQ38

PQ38

8
7

5

4

PR204

PR204
47K_0402_5%~D

47K_0402_5%~D

1 2

PQ35B

PQ35B

IMD2AT-108_SC74-6~D

IMD2AT-108_SC74-6~D

PR197

PR197

240K_0402_5%~D

240K_0402_5%~D

4 3

PQ35A

PQ35A

+PBATT_PSRC

2

16

+DC_IN_SS

12

PR198

PR198

22K_0402_5%~D

22K_0402_5%~D

5

PQ36

PQ36

RHU002N06_SOT323

RHU002N06_SOT323

13

D

D

2

G

G

S

S

1 2

PR201

PR201

22K_0402_5%~D

22K_0402_5%~D

FDS6679AZ_SO8~D

FDS6679AZ_SO8~D
PQ39

PQ39

8
7

5

4

PR203

PR203

1 2

33K_0402_5%~D

33K_0402_5%~D

1
2
36

1

EN_DOCK_PWR_BAR <37>

12

PC193

PC193

2200P_0402_50V7K~D

2200P_0402_50V7K~D

+PWR_SRC

12

PC194

PC194

0.1U_0603_25V7K~D

0.1U_0603_25V7K~D

B B

A A

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

Date: Sheet of

Compal Electronics, Inc.

SCHEMATIC, MB A4042

SCHEMATIC, MB A4042

SCHEMATIC, MB A4042
401533

401533

401533

49 56Tuesday, December 18, 2007

49 56Tuesday, December 18, 2007

49 56Tuesday, December 18, 2007

1

of

of

A

A

A

5

4

3

2

1

+GPU_PWR_SRC

10U_1206_25V6M~D

10U_1206_25V6M~D

12

1 2

1

PC197

PC197

2

PC206

PC206

@

@

1000P_0402_50V7K~D

1000P_0402_50V7K~D

2

2

PC198

PC198

1

0.1U_0603_50V4Z~D

0.1U_0603_50V4Z~D
2200P_0402_50V7K~D

2200P_0402_50V7K~D

10_0402_5%~D

10_0402_5%~D

12

PR207

PR207

PC202

PC202

1

12

PR211

PR211

2

24.9K_0402_1%~D

24.9K_0402_1%~D

12

PR213

PR213

88.7K_0402_1%

88.7K_0402_1%

GNDA_GPU_CORE

GPU_VID_1

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

D D

@ PR206

@

61.9K_0402_1%~D

61.9K_0402_1%~D

GFX_CORE_PWRGD<41,53>

1.1V_GFX_PWRGD<41>

RUN_ON<19,28,37,40,41>

GFX_CORE_ON<37>

C C

B B

GNDA_GPU_CORE

A A

+FBVDDQ

+1.1VRUNP

PJP27

PJP27

PAD-OPEN1x1m

PAD-OPEN1x1m

+VCC_GFX_CORE

+1.1VRUNP

5

10U_0805_10V4Z~D

10U_0805_10V4Z~D

12

12

PR208 0_0402_5%~D@PR208 0_0402_5%~D@

12

PR210 0_0402_5%~DPR210 0_0402_5%~D

1

PC207

PC207

2

1

2

PJP36

@PJP36

@

1 2

PAD-OPEN 43X118

PAD-OPEN 43X118

PJP37

@PJP37

@

1 2

PAD-OPEN 43X118

PAD-OPEN 43X118

PJP28

@PJP28

@

1 2

PAD-OPEN 43X79

PAD-OPEN 43X79

GFX_+5V_RUN

12

PR206

GFX_REF

1

PC208

PC208

PC209

PC209

2

22U_0805_6.3VAM~D

22U_0805_6.3VAM~D

PR218

PR218

100K_0402_5%~D

100K_0402_5%~D

+GPU_CORE

+1.1V_GFX_PCIE

22U_0805_6.3VAM~D

22U_0805_6.3VAM~D

+3.3V_RUN

12

GFX_CORE_PWRGD

1.1V_GFX_PWRGD

GNDA_GPU_CORE

487_0402_1%

487_0402_1%

1 2

1

PC214

PC214

2

0.01U_0402_16V7K~D

0.01U_0402_16V7K~D

1

2

GNDA_GPU_CORE

17

5
6

27

7

13

14

11

12

9

10

1

2

PC211

PC211

1U_0603_10V4Z~D

1U_0603_10V4Z~D

PR220

PR220

GNDA_GPU_COREGNDA_GPU_CORE

GPU_VID_0
GPU_VID_1

4

PC199

PC199

1U_0603_10V4Z~D

1U_0603_10V4Z~D

PU12

PU12

VIN
POK1
POK2
SHDN

STBY

VTTI

REFIN

PGND2

VTT
VTTS
VTTR

GND

29

GNDA_GPU_CORE

12

PR221

PR221

4.87K_0402_1%

4.87K_0402_1%

26

28

TP0

AVDD

MAX8632ETI+_TQFN28~D

MAX8632ETI+_TQFN28~D

SS8GND

24

1

PC212

PC212

2

0.047U_0402_16V4Z~D

0.047U_0402_16V4Z~D

0.9V
default

PR205

PR205

10_0805_5%~D

10_0805_5%~D

1 2

2

22

VDD

OVP/ UVP

PGND1

SKIP

ILIM

4

25

GPU_VID_0<51>

1.09V 1.17V

0
0

BST

DH

LX

DL

VOUT

FB

TON

REF

1
0

+5V_RUN

1

PC200

PC200

2.2U_0603_6.3V6K~D

2.2U_0603_6.3V6K~D

12

+3.3V_RUN

10K_0402_5%~D

10K_0402_5%~D

1 2

10K_0402_5%~D

10K_0402_5%~D

3

21

PD17

PD17

0.22U_0603_10V7K~D

0.22U_0603_10V7K~D

1 2

1

PC210

PC210

2

0.22U_0402_10V4Z~D

0.22U_0402_10V4Z~D

12

PR222

PR222

PR223

PR223

RB751V_SOD323~D

RB751V_SOD323~D

PC201

PC201

12

4

5

4

12

PR224

PR224

GNDA_GPU_CORE

output voltage adjustable network

2

PR209

PR209

0_0603_5%~D

0_0603_5%~D

20

1 2

18

19

21

23

16

15

1

PR212

@PR212

@

0_0402_5%~D

0_0402_5%~D

GFX_REF

3

12

PR214

PR214
100K_0402_1%~D

100K_0402_1%~D

GNDA_GPU_CORE

PR216 0_0402_5%~D@PR216 0_0402_5%~D@

12

PR217

PR217
100K_0402_1%~D

100K_0402_1%~D

GNDA_GPU_CORE

GPU_VID_0

1
1

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

1

PC225

PC225

2

10U_1206_25V6M~D

10U_1206_25V6M~D

8

PQ41

PQ41

D6D5D7D

SI4386DY_T1_SO8~D

SI4386DY_T1_SO8~D

G

S

S

S

3

2

1

0.88UH_MPC1040LR88_17A_20%~D

0.88UH_MPC1040LR88_17A_20%~D

1 2

786

123

1

2

100K_0402_5%~D

100K_0402_5%~D

5

PQ42

PQ42

4

FDS6676AS_NL_SO8~D

FDS6676AS_NL_SO8~D

12

13

2

G

G

PC215

PC215

0.01U_0402_16V7K~D

0.01U_0402_16V7K~D

D

D

S

S

1

1

PC196

PC196

PC195

PC195

2

2

10U_1206_25V6M~D

10U_1206_25V6M~D

PL17

PL17

786

PC227

PC227

@

@

1500P_0603_25V7K~D

1500P_0603_25V7K~D

PQ58

PQ58

PR241

PR241

123

FDS6676AS_NL_SO8~D

FDS6676AS_NL_SO8~D

@

@

4.7_1206_5%~D

4.7_1206_5%~D

12

PR215

PR215

90.9K_0402_1%~D

90.9K_0402_1%~D

1

PC213

PC213

2

PR219

PR219

100P_0402_50V8J~D

100P_0402_50V8J~D

GNDA_GPU_CORE

301_0402_1%~D

301_0402_1%~D

PQ43

PQ43

BSS138W-7-F_SOT323~D

BSS138W-7-F_SOT323~D

GPU_VID_1<51>

PL16

PL16

FBMJ4516HS720NT_1806~D

FBMJ4516HS720NT_1806~D

1 2

PJP24

@PJP24

@

1 2

PAD-OPEN 43X118

PAD-OPEN 43X118

+PWR_SRC

GPU_CORE
Thermal Design Current:7.7A
Peak current: 11A
OCP min: 12A

+VCC_GFX_CORE

1

12

+

+

PC226

PC226

2

330U_D2E_2.5VM~D

330U_D2E_2.5VM~D

GPU_VDD_SENSE <53>

12

PR236

PR236
221K_0402_1%

221K_0402_1%

1

PC223

PC223

100P_0402_50V8J~D

100P_0402_50V8J~D

2

GNDA_GPU_CORE

12

1

PR239

PR239

PC224

PC224

2

100K_0402_5%~D

100K_0402_5%~D

GNDA_GPU_CORE

12

13

2

G

G

0.01U_0402_16V7K~D

0.01U_0402_16V7K~D

1

2

1

+

+

PC203

PC203

2

330U_D2E_2.5VM~D

330U_D2E_2.5VM~D

+3.3V_RUN

10K_0402_5%~D

10K_0402_5%~D

1 2

10K_0402_5%~D

10K_0402_5%~D

PC204

PC204

PR240

PR240

+

+

330U_D2E_2.5VM~D

330U_D2E_2.5VM~D

PR237

PR237

1

2

PC205

PC205

2200P_0402_50V7K~D

2200P_0402_50V7K~D

12

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

Date: Sheet

Compal Electronics, Inc.
SCHEMATIC, MB A4042

SCHEMATIC, MB A4042

SCHEMATIC, MB A4042

401533

401533

401533

1

PR238

PR238

301_0402_1%~D

301_0402_1%~D

D

D

PQ44

PQ44

BSS138W-7-F_SOT323~D

BSS138W-7-F_SOT323~D

S

S

50 56Tuesday, December 18, 2007

50 56Tuesday, December 18, 2007

50 56Tuesday, December 18, 2007

of

of

of

A

A

A

5

PEG_MTX_GRX_P[0..15]<12>
PEG_MTX_GRX_N[0..15]<12>

PEG_MRX_GTX_P[0..15]<12>

R694

R694

CRT_DAT_DDC

PEG_MRX_GTX_N[0..15]<12>

+3.3V_RUN

12

12

+3.3V_RUN

DPB_GPU_P14

R695

R695

2.2K_0402_5%~D

2.2K_0402_5%~D

1 2

R860

@R860

@

0_0402_5%~D

0_0402_5%~D

4

1 2

R861

@R861

@

0_0402_5%~D

0_0402_5%~D

12

5

PEG_MRX_GTX_P0
PEG_MRX_GTX_N0

PEG_MRX_GTX_P1
PEG_MRX_GTX_N1

D D

PEG_MRX_GTX_P2
PEG_MRX_GTX_N2

PEG_MRX_GTX_P3
PEG_MRX_GTX_N3

PEG_MRX_GTX_P4
PEG_MRX_GTX_N4

PEG_MRX_GTX_P5
PEG_MRX_GTX_N5

PEG_MRX_GTX_P6
PEG_MRX_GTX_N6

PEG_MRX_GTX_P7
PEG_MRX_GTX_N7

PEG_MRX_GTX_P8
PEG_MRX_GTX_N8

PEG_MRX_GTX_P9
PEG_MRX_GTX_N9

PEG_MRX_GTX_P10
PEG_MRX_GTX_N10

PEG_MRX_GTX_P11
PEG_MRX_GTX_N11

PEG_MRX_GTX_P12
PEG_MRX_GTX_N12

C C

PEG_MRX_GTX_P13
PEG_MRX_GTX_N13

PEG_MRX_GTX_P14
PEG_MRX_GTX_N14

PEG_MRX_GTX_P15
PEG_MRX_GTX_N15

B B

2.2K_0402_5%~D

2.2K_0402_5%~D

A A

PEG_MTX_GRX_P[0..15]
PEG_MTX_GRX_N[0..15]
PEG_MRX_GTX_P[0..15]
PEG_MRX_GTX_N[0..15]

C7160.1U_0402_10V7K~D C7160.1U_0402_10V7K~D

12

C7170.1U_0402_10V7K~D C7170.1U_0402_10V7K~D

12

12

12

12

12

12

12

12

12

12

12

12

12

12

12

12

R855 10K_0402_5%~DR855 10K_0402_5%~D

R797

R797
100K_0402_5%~D

100K_0402_5%~D

C7180.1U_0402_10V7K~D C7180.1U_0402_10V7K~D

12

C7190.1U_0402_10V7K~D C7190.1U_0402_10V7K~D

C7200.1U_0402_10V7K~D C7200.1U_0402_10V7K~D

12

C7210.1U_0402_10V7K~D C7210.1U_0402_10V7K~D

C7220.1U_0402_10V7K~D C7220.1U_0402_10V7K~D

12

C7230.1U_0402_10V7K~D C7230.1U_0402_10V7K~D

C7240.1U_0402_10V7K~D C7240.1U_0402_10V7K~D

12

C7250.1U_0402_10V7K~D C7250.1U_0402_10V7K~D

C7260.1U_0402_10V7K~D C7260.1U_0402_10V7K~D

12

C7270.1U_0402_10V7K~D C7270.1U_0402_10V7K~D

C7280.1U_0402_10V7K~D C7280.1U_0402_10V7K~D

12

C7290.1U_0402_10V7K~D C7290.1U_0402_10V7K~D

C7300.1U_0402_10V7K~D C7300.1U_0402_10V7K~D

12

C7310.1U_0402_10V7K~D C7310.1U_0402_10V7K~D

C7330.1U_0402_10V7K~D C7330.1U_0402_10V7K~D

12

C7340.1U_0402_10V7K~D C7340.1U_0402_10V7K~D

C7350.1U_0402_10V7K~D C7350.1U_0402_10V7K~D

12

C7360.1U_0402_10V7K~D C7360.1U_0402_10V7K~D

C7380.1U_0402_10V7K~D C7380.1U_0402_10V7K~D

12

C7390.1U_0402_10V7K~D C7390.1U_0402_10V7K~D

C7400.1U_0402_10V7K~D C7400.1U_0402_10V7K~D

12

C7410.1U_0402_10V7K~D C7410.1U_0402_10V7K~D

C7420.1U_0402_10V7K~D C7420.1U_0402_10V7K~D

12

C7430.1U_0402_10V7K~D C7430.1U_0402_10V7K~D

C7450.1U_0402_10V7K~D C7450.1U_0402_10V7K~D

12

C7460.1U_0402_10V7K~D C7460.1U_0402_10V7K~D

C7470.1U_0402_10V7K~D C7470.1U_0402_10V7K~D

12

C7490.1U_0402_10V7K~D C7490.1U_0402_10V7K~D

C7520.1U_0402_10V7K~D C7520.1U_0402_10V7K~D

12

C7540.1U_0402_10V7K~D C7540.1U_0402_10V7K~D

PLTRST1#<10,22,32>

CLK_NVSS_27M<6>

61

Q123A

Q123A
2N7002DW-T/R7_SOT363-6~D

2N7002DW-T/R7_SOT363-6~D

2
5

Q123B

Q123B
2N7002DW-T/R7_SOT363-6~D

2N7002DW-T/R7_SOT363-6~D

3

1 2

GPU_CLK_DDCCRT_CLK_DDC

GPU_DAT_DDC

PEG_MRX_GTX_C_P0
PEG_MRX_GTX_C_N0

PEG_MRX_GTX_C_P1
PEG_MRX_GTX_C_N1

PEG_MRX_GTX_C_P2
PEG_MRX_GTX_C_N2

PEG_MRX_GTX_C_P3
PEG_MRX_GTX_C_N3

PEG_MRX_GTX_C_P4
PEG_MRX_GTX_C_N4

PEG_MRX_GTX_C_P5
PEG_MRX_GTX_C_N5

PEG_MRX_GTX_C_P6
PEG_MRX_GTX_C_N6

PEG_MRX_GTX_C_P7
PEG_MRX_GTX_C_N7

PEG_MRX_GTX_C_P8
PEG_MRX_GTX_C_N8

PEG_MRX_GTX_C_P9
PEG_MRX_GTX_C_N9

PEG_MRX_GTX_C_P10
PEG_MRX_GTX_C_N10

PEG_MRX_GTX_C_P11
PEG_MRX_GTX_C_N11

PEG_MRX_GTX_C_P12
PEG_MRX_GTX_C_N12

PEG_MRX_GTX_C_P13
PEG_MRX_GTX_C_N13

PEG_MRX_GTX_C_P14
PEG_MRX_GTX_C_N14

PEG_MRX_GTX_C_P15
PEG_MRX_GTX_C_N15

CLK_PCIE_VGA<6>
CLK_PCIE_VGA#<6>

R681 0_0402_5%~DR681 0_0402_5%~D

1 2

R872 10K_0402_5%~D@R872 10K_0402_5%~D@

1 2

1 2

R686 0_0402_5%~DR686 0_0402_5%~D

1 2

R687 2.49K_0402_1%~DR687 2.49K_0402_1%~D

PEX_TERMP

GPU_CLK_DDC <20>

GPU_DAT_DDC <20>

DPB_MB_P14 <21>

PEG_MTX_GRX_P0
PEG_MTX_GRX_N0
PEG_MTX_GRX_P1
PEG_MTX_GRX_N1
PEG_MTX_GRX_P2
PEG_MTX_GRX_N2
PEG_MTX_GRX_P3
PEG_MTX_GRX_N3
PEG_MTX_GRX_P4
PEG_MTX_GRX_N4
PEG_MTX_GRX_P5
PEG_MTX_GRX_N5
PEG_MTX_GRX_P6
PEG_MTX_GRX_N6
PEG_MTX_GRX_P7
PEG_MTX_GRX_N7
PEG_MTX_GRX_P8
PEG_MTX_GRX_N8
PEG_MTX_GRX_P9
PEG_MTX_GRX_N9
PEG_MTX_GRX_P10
PEG_MTX_GRX_N10
PEG_MTX_GRX_P11
PEG_MTX_GRX_N11
PEG_MTX_GRX_P12
PEG_MTX_GRX_N12
PEG_MTX_GRX_P13
PEG_MTX_GRX_N13
PEG_MTX_GRX_P14
PEG_MTX_GRX_N14
PEG_MTX_GRX_P15
PEG_MTX_GRX_N15

PEG_MRX_GTX_C_P0
PEG_MRX_GTX_C_N0
PEG_MRX_GTX_C_P1
PEG_MRX_GTX_C_N1
PEG_MRX_GTX_C_P2
PEG_MRX_GTX_C_N2
PEG_MRX_GTX_C_P3
PEG_MRX_GTX_C_N3
PEG_MRX_GTX_C_P4
PEG_MRX_GTX_C_N4
PEG_MRX_GTX_C_P5
PEG_MRX_GTX_C_N5
PEG_MRX_GTX_C_P6
PEG_MRX_GTX_C_N6
PEG_MRX_GTX_C_P7
PEG_MRX_GTX_C_N7
PEG_MRX_GTX_C_P8
PEG_MRX_GTX_C_N8
PEG_MRX_GTX_C_P9
PEG_MRX_GTX_C_N9
PEG_MRX_GTX_C_P10
PEG_MRX_GTX_C_N10
PEG_MRX_GTX_C_P11
PEG_MRX_GTX_C_N11
PEG_MRX_GTX_C_P12
PEG_MRX_GTX_C_N12
PEG_MRX_GTX_C_P13
PEG_MRX_GTX_C_N13
PEG_MRX_GTX_C_P14
PEG_MRX_GTX_C_N14
PEG_MRX_GTX_C_P15
PEG_MRX_GTX_C_N15

CLK_PCIE_VGA
CLK_PCIE_VGA#

PEX_TERMP

XTALSSIN_R

4

U44A

U44A

AE12

PEX_RX0

AF12

PEX_RX0_N

AG12

PEX_RX1

AG13

PEX_RX1_N

AF13

PEX_RX2

AE13

PEX_RX2_N

AE15

PEX_RX3

AF15

PEX_RX3_N

AG15

PEX_RX4

AG16

PEX_RX4_N

AF16

PEX_RX5

AE16

PEX_RX5_N

AE18

PEX_RX6

AF18

PEX_RX6_N

AG18

PEX_RX7

AG19

PEX_RX7_N

AF19

PEX_RX8

AE19

PEX_RX8_N

AE21

PEX_RX9

AF21

PEX_RX9_N

AG21

PEX_RX10

AG22

PEX_RX10_N

AF22

PEX_RX11

AE22

PEX_RX11_N

AE24

PEX_RX12

AF24

PEX_RX12_N

AG24

PEX_RX13

AF25

PEX_RX13_N

AG25

PEX_RX14

AG26

PEX_RX14_N

AF27

PEX_RX15

AE27

PEX_RX15_N

AD10

PEX_TX0

AD11

PEX_TX0_N

AD12

PEX_TX1

AC12

PEX_TX1_N

AB11

PEX_TX2

AB12

PEX_TX2_N

AD13

PEX_TX3

AD14

PEX_TX3_N

AD15

PEX_TX4

AC15

PEX_TX4_N

AB14

PEX_TX5

AB15

PEX_TX5_N

AC16

PEX_TX6

AD16

PEX_TX6_N

AD17

PEX_TX7

AD18

PEX_TX7_N

AC18

PEX_TX8

AB18

PEX_TX8_N

AB19

PEX_TX9

AB20

PEX_TX9_N

AD19

PEX_TX10

AD20

PEX_TX10_N

AD21

PEX_TX11

AC21

PEX_TX11_N

AB21

PEX_TX12

AB22

PEX_TX12_N

AC22

PEX_TX13

AD22

PEX_TX13_N

AD23

PEX_TX14

AD24

PEX_TX14_N

AE25

PEX_TX15

AE26

PEX_TX15_N

AB10

PEX_REFCLK

AC10

PEX_REFCLK_N

AD9

PEX_RST_N

AG10

PEX_TERMP

E9

XTALOUTBUFF

D11

XTALSSIN

12

R871

@ R871

@

NB9M-NS_BGA533~D

NB9M-NS_BGA533~D

10K_0402_5%~D

10K_0402_5%~D

+3.3V_RUN

1 2

C610

C610

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

HDCP_WP
HDCP_CLK
HDCP_DAT

HDCP_DAT
HDCP_WP
TV_C_GPU
TV_CVBS_GPU
TV_Y_GPU
CRT_RED_GPU
CRT_GRN_GPU
CRT_BLU_GPU
STRAP_CAL_PU_GND0
STRAP_CAL_PU_GND1
JTAG_RST#_GPU

4

Part 1 of 5

Part 1 of 5

PCI EXPRESS

PCI EXPRESS

CLK

CLK

U56

U56

8

VCC

7

WP

6

SCL

5

SDA

190-00001-0001-T03 AT88SC0808C_SO8~D

190-00001-0001-T03 AT88SC0808C_SO8~D

R758 10K_0402_5%~DR758 10K_0402_5%~D

1 2

R96 10K_0402_5%~DR96 10K_0402_5%~D

1 2

R688 150_0402_5%~DR688 150_0402_5%~D

1 2

R689 150_0402_5%~DR689 150_0402_5%~D

1 2

R690 150_0402_5%~DR690 150_0402_5%~D

1 2

R691 150_0402_5%~DR691 150_0402_5%~D

1 2

R692 150_0402_5%~DR692 150_0402_5%~D

1 2

R693 150_0402_5%~DR693 150_0402_5%~D

1 2

R727 40.2K_0402_1%R727 40.2K_0402_1%

1 2

R731 40.2K_0402_1%R731 40.2K_0402_1%

1 2

R853 1K_0402_5%~D@ R853 1K_0402_5%~D@

GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8

GPIO9
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14
GPIO15

DVO / GPIO

DVO / GPIO

GPIO16
GPIO17
GPIO18
GPIO19

DACA_HSYNC
DACA_VSYNC

DACA_RED

DACA_BLUE

DACA_GREEN

DACA_RSET

DACA_VREF

DACB_RED

DACB_BLUE

DACB_GREEN

DACB_RSET

DACB_CSYNC

DACB_VREF

DACsI2C

DACsI2C

DACC_HSYNC
DACC_VSYNC

DACC_RED

DACC_BLUE

DACC_GREEN

DACC_RSET
DACC_VREF

I2CA_SCL

I2CA_SDA

I2CB_SCL

I2CB_SDA

I2CC_SCL

I2CC_SDA

I2CD_SCL

I2CD_SDA

I2CE_SCL

I2CE_SDA

I2CH_SCL

I2CH_SDA

I2CS_SCL

I2CS_SDA

JTAG_TCK

JTAG_TDI
JTAG_TDO
JTAG_TMS

JTAG_TRST_N

TESTMODE

TEST

TEST

PEX_TSTCLK_OUT

PEX_TSTCLK_OUT_N

XTALIN

XTALOUT

1

A0

2

A1

3

A2

4

GND

+3.3V_RUN

12

N1

DPB_HPD#

G1

BIA_PWM_GPU

C1

ENVDD_GPU

M2

PANEL_BKEN_GPU

M3

GPU_VID_0

K3

GPU_VID_1

K2
J2
C2

1 2

R670 0_0402_5%~DR670 0_0402_5%~D

M1

R889 0_0402_5%~DR889 0_0402_5%~D

1 2

D2
D1
J3
J1
K1

DPC_DOCK_HPD#

F3

GPU_GPIO16

G3

DPB_GPU_P14

G2

GPU_GPIO18

F1

HDMI_DET1

F2

CRT_HSYNC_GPU

AD2

CRT_VSYNC_GPU

AD1

CRT_RED_GPU

AE2

CRT_BLU_GPU

AD3

CRT_GRN_GPU

AE3

DACA_RSET

AE1

DACA_VREF

AF1

TV_C_GPU

F7

TV_CVBS_GPU

E6

TV_Y_GPU

E7

DACB_RSET

F8
D6

DACB_VREF

G6
U6

U4
T5
R4
T4
V6
R6

CRT_CLK_DDC

R1

CRT_DAT_DDC

T3

DVI_C_CLK_DDC

R2

DVI_C_DAT_DDC

R3

LDDC_CLK_GPU

A2

LDDC_DATA_GPU

B1

DVI_B_CLK_DDC

N2

DVI_B_DAT_DDC

N3

I2CE_SCL

Y6

I2CE_SDA

W6

HDCP_CLK

A3

HDCP_DAT

A4
T1
T2

JTAG_TCK_GPU

AF3

JTAG_TDI_GPU

AG4

JTAG_TDO_GPU

AE4

JTAG_TMS_GPU

AF4

JTAG_RST#_GPU

AG3
AD25

AF10
AE10

D10
E10

1 2

R752 0_0402_5%~DR752 0_0402_5%~D

1 2

R753

R753
0_0402_5%~D

0_0402_5%~D

12

R680 10K_0402_5%~DR680 10K_0402_5%~D

1 2

R696 200_0402_1%~DR696 200_0402_1%~D

+3.3V_RUN

HDCP_CLK

Stuff R824 for
standard I2C ROM.
Stuff R801 for
crypto ROM

3

DPB_HPD# <21>

BIA_PWM_GPU <19>
ENVDD_GPU <19>
PANEL_BKEN_GPU <37>
GPU_VID_0 <50>
GPU_VID_1 <50>

THERMTRIP_VGA# <18>

GPIO10_REF_SW <55>

12

C982 0.1U_0402_10V7K~DC982 0.1U_0402_10V7K~D

1 2

R890 10K_0402_5%~DR890 10K_0402_5%~D

DPC_DOCK_HPD# <35>

T119PAD~D

T119PAD~D

CRT_HSYNC_GPU <20>
CRT_VSYNC_GPU <20>
CRT_RED_GPU <20>
CRT_BLU_GPU <20>
CRT_GRN_GPU <20>

1 2

R677 124_0402_1%~DR677 124_0402_1%~D

TV_C_GPU <20>
TV_CVBS_GPU <20>
TV_Y_GPU <20>

1 2

R679 124_0402_1%~DR679 124_0402_1%~D

1 2

C737 0.1U_0402_10V7K~DC737 0.1U_0402_10V7K~D

DVI_C_CLK_DDC <21>

DVI_C_DAT_DDC <21>

LDDC_CLK_GPU <19>

LDDC_DATA_GPU <19>

DVI_B_CLK_DDC <21>

DVI_B_DAT_DDC <21>

@

@

T83 PAD~D

T83 PAD~D

@

@

T84 PAD~D

T84 PAD~D

@

@

T85 PAD~D

T85 PAD~D

@

@

T86 PAD~D

T86 PAD~D

@

@

T87 PAD~D

T87 PAD~D

CLK_NV_27M <6>

12

R929

R929
10K_0402_5%~D

10K_0402_5%~D

12

R801

@R801

@

10K_0402_5%~D

10K_0402_5%~D

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

@

@

1 2

C732

C732

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

DPB_LANE_P0
DPB_LANE_N0
DPB_LANE_P1
DPB_LANE_N1
DPB_LANE_P2
DPB_LANE_N2
DPB_LANE_P3
DPB_LANE_N3

DPC_LANE_P0
DPC_LANE_N0
DPC_LANE_P1
DPC_LANE_N1
DPC_LANE_P2
DPC_LANE_N2
DPC_LANE_P3
DPC_LANE_N3

I2CE_SDA

I2CE_SCL

ICH_AZ_GPU_BITCLK<23>
ICH_AZ_GPU_SYNC<23>
ICH_AZ_GPU_SDIN2<23>
ICH_AZ_GPU_SDOUT<23>
ICH_AZ_GPU_RST#<23>

GPIO16 GPIO17

00
0 1 HDMI

<---CRT
<---DVI C
<---LVDS
<---DVI B

R858 0_0402_5%~D@ R858 0_0402_5%~D@

GPU_GPIO16

1 2

R859 0_0402_5%~D@ R859 0_0402_5%~D@

GPU_GPIO18

1 2

12

C748 0.1U_0402_10V7K~DC748 0.1U_0402_10V7K~D

12

C750 0.1U_0402_10V7K~DC750 0.1U_0402_10V7K~D

12

C751 0.1U_0402_10V7K~DC751 0.1U_0402_10V7K~D

12

C753 0.1U_0402_10V7K~DC753 0.1U_0402_10V7K~D

12

C755 0.1U_0402_10V7K~DC755 0.1U_0402_10V7K~D

12

C756 0.1U_0402_10V7K~DC756 0.1U_0402_10V7K~D

12

C757 0.1U_0402_10V7K~DC757 0.1U_0402_10V7K~D

12

C758 0.1U_0402_10V7K~DC758 0.1U_0402_10V7K~D

12

C759 0.1U_0402_10V7K~DC759 0.1U_0402_10V7K~D

12

C760 0.1U_0402_10V7K~DC760 0.1U_0402_10V7K~D

12

C761 0.1U_0402_10V7K~DC761 0.1U_0402_10V7K~D

12

C762 0.1U_0402_10V7K~DC762 0.1U_0402_10V7K~D

12

C763 0.1U_0402_10V7K~DC763 0.1U_0402_10V7K~D

12

C764 0.1U_0402_10V7K~DC764 0.1U_0402_10V7K~D

12

C765 0.1U_0402_10V7K~DC765 0.1U_0402_10V7K~D

12

C766 0.1U_0402_10V7K~DC766 0.1U_0402_10V7K~D

R841 10K_0402_5%~D@R841 10K_0402_5%~D@

1 2

R843 10K_0402_5%~D@R843 10K_0402_5%~D@

1 2

2

U44C

U44C

AC4

IFPA_TXC

AD4

IFPA_TXC_N

V5

IFPA_TXD0

V4

IFPA_TXD0_N

AA5

IFPA_TXD1

AA4

IFPA_TXD1_N

W4

IFPA_TXD2

Y4

IFPA_TXD2_N

AB4

IFPA_TXD3

AB5

IFPA_TXD3_N

AB3

IFPB_TXC

AB2

IFPB_TXC_N

W1

IFPB_TXD4

V1

IFPB_TXD4_N

W3

IFPB_TXD5

W2

IFPB_TXD5_N

AA2

IFPB_TXD6

AA3

IFPB_TXD6_N

AB1

IFPB_TXD7

AA1

IFPB_TXD7_N

AB6

IFPAB_RSET

A7

HDA_BCLK

B7

HDA_SYNC

A6

HDA_SDI

B6

HDA_SDO

C6

HDA_RST_N

C15

RFU0(NC)

D15

RFU1(NC)

J5

RFU2(NC)

F6

RFU3(NC)

J22

RFU4(NC)

L22

RFU5(NC)

AG9

RFU6(NC)

AE9

RFU7(NC)

AA6

NC0

AC19

NC1

E15

NC2

T6

NC3

NB9M-NS_BGA533~D

NB9M-NS_BGA533~D

Part 3 of 5

Part 3 of 5

LVDS

LVDS

HDA

HDA

GENERAL

GENERAL

STRAP_CAL_PD_3V3(NC)

STRAP_CAL_PD_MIOB(NC)

IFPC_AUX

IFPC_AUX_N

IFPC_L0

IFPC_L0_N

IFPC_L1

IFPC_L1_N

IFPC_L2

IFPC_L2_N

IFPC_L3

IFPC_L3_N

IFPC_RSET

IFPE_AUX

IFPE_AUX_N

IFPE_L0

IFPE_L0_N

IFPE_L1

MXM/DVI/DP

MXM/DVI/DP

IFPE_L1_N

IFPE_L2

IFPE_L2_N

IFPE_L3

IFPE_L3_N
IFPE_RSET
ROM_SCLK

ROM_SI

ROM_SO

ROMCS_N

STRAP0
STRAP1
STRAP2

SPDIF

BUFRST_N

THERMDP
THERMDN

G4
G5
P4
N4
M5
M4
L4
K4
H4
J4

R5
D3

D4
F5
F4
E4
D5
C3
C4
B3
B4

M6
C9

A10
C10
B10

C7
B9
A9
F10
F11

F9
N5

D9
D8

R672 1K_0402_5%~D@ R672 1K_0402_5%~D@

1 2
1 2
1 2
1 2
1 2

DP Conn.
function
DP1X

LCD_ACLK+_GPU
LCD_ACLK-_GPU
LCD_A0+_GPU
LCD_A0-_GPU
LCD_A1+_GPU
LCD_A1-_GPU
LCD_A2+_GPU
LCD_A2-_GPU

LCD_BCLK+_GPU
LCD_BCLK-_GPU
LCD_B0+_GPU
LCD_B0-_GPU
LCD_B1+_GPU
LCD_B1-_GPU
LCD_B2+_GPU
LCD_B2-_GPU

12

LCD_ACLK+_GPU<19>
LCD_ACLK-_GPU<19>
LCD_A0+_GPU<19>
LCD_A0-_GPU<19>
LCD_A1+_GPU<19>
LCD_A1-_GPU<19>
LCD_A2+_GPU<19>
LCD_A2-_GPU<19>

LCD_BCLK+_GPU<19>
LCD_BCLK-_GPU<19>
LCD_B0+_GPU<19>
LCD_B0-_GPU<19>
LCD_B1+_GPU<19>
LCD_B1-_GPU<19>
LCD_B2+_GPU<19>
LCD_B2-_GPU<19>

R673 33_0402_5%~D@R673 33_0402_5%~D@
R674 33_0402_5%~D@R674 33_0402_5%~D@
R675 33_0402_5%~D@R675 33_0402_5%~D@
R676 33_0402_5%~D@R676 33_0402_5%~D@
R678 33_0402_5%~D@R678 33_0402_5%~D@

DVI

check GDDR3 and nonOpenGL

R713

STRAP0
STRAP1
STRAP2
ROM_SCLK_GPU
ROM_SI_GPU
ROM_SO_GPU

1 2

R825 15K_0402_1%~D@R825 15K_0402_1%~D@

4.99K_0402_1%~D

4.99K_0402_1%~D

12

R856

R856

4.99K_0402_1%~D

4.99K_0402_1%~D

12

R857

R857

R713

R728

R728

@

@

DPB_CA_DET <21>

DPC_CA_DET <21,35>

DPB_LANE_P0_C <21>
DPB_LANE_N0_C <21>
DPB_LANE_P1_C <21>
DPB_LANE_N1_C <21>
DPB_LANE_P2_C <21>
DPB_LANE_N2_C <21>
DPB_LANE_P3_C <21>
DPB_LANE_N3_C <21>

DPC_LANE_P0_C <35>
DPC_LANE_N0_C <35>
DPC_LANE_P1_C <35>
DPC_LANE_N1_C <35>
DPC_LANE_P2_C <35>
DPC_LANE_N2_C <35>
DPC_LANE_P3_C <35>
DPC_LANE_N3_C <35>

Each strap pin represents a 4 bit value

Pullup or Pulldown configures the MSB
Resistor Value determines the 3 LSBs
Resistor range is R*n
where n is 0-9 and R is 5K ohm.
For NVG98 NS part stuff R719, no-stuff R716
For NVG98 GLM part stuff R716, no-stuff R719
For Samsung 32Mx16 DDR2 part stuff R725=30K
For Qimonda 32Mx16 DDR2 part stuff R725=35K
For Hynix 32Mx16 DDR2 part stuff R725=45K

ROM_SCLK_GPU

+3.3V_RUN

SPDIF_OUT<27>

1 2

C1032

C1032

0.01U_0402_16V7K~D

0.01U_0402_16V7K~D

1

DPB_LANE_P0
DPB_LANE_N0
DPB_LANE_P1
DPB_LANE_N1
DPB_LANE_P2
DPB_LANE_N2
DPB_LANE_P3
DPB_LANE_N3

1 2

R720 1K_0402_1%~D@ R720 1K_0402_1%~D@

DPC_LANE_P0
DPC_LANE_N0
DPC_LANE_P1
DPC_LANE_N1
DPC_LANE_P2
DPC_LANE_N2
DPC_LANE_P3
DPC_LANE_N3

1 2

R721 1K_0402_1%~D@ R721 1K_0402_1%~D@

ROM_SCLK_GPU
ROM_SI_GPU
ROM_SO_GPU

STRAP0
STRAP1
STRAP2
STRAP_CAL_PU_GND0
STRAP_CAL_PU_GND1

SPDIF_OUT_GPU

1

C744

@C744

@

100P_0402_50V8K~D

100P_0402_50V8K~D

2

Strap pin define

12

45.3K_0402_1%~D

45.3K_0402_1%~D

12

4.99K_0402_1%~D

4.99K_0402_1%~D

3

1

12

R715

R715

R714

R714

@

@

4.99K_0402_1%~D

4.99K_0402_1%~D

12

R729

R729

R730

R730

@

@

10K_0402_1%~D

10K_0402_1%~D

2

D63

D63
DA204U_SOT323-3~D

DA204U_SOT323-3~D

SPDIF_OUT_GPU

12

20K_0402_1%~D

20K_0402_1%~D

12

4.99K_0402_1%~D

4.99K_0402_1%~D

DPB_AUX <21>

DPB_AUX# <21>

DPC_DOCK_AUX <21>

DPC_DOCK_AUX# <21>

VGA_THERMDP <18>

VGA_THERMDN <18>

12

12

R716

R716

R717

R717

15K_0402_1%

15K_0402_1%

@

@

@

@

4.99K_0402_1%~D

4.99K_0402_1%~D

12

12

R719

R719

R725

R725

15K_0402_1%

15K_0402_1%

10K_0402_1%~D

10K_0402_1%~D

GFX_OPEN_GL_EN <37>

+3.3V_RUN

12

R718

R718

4.99K_0402_1%~D

4.99K_0402_1%~D

12

R726

R726

@

@

4.99K_0402_1%~D

4.99K_0402_1%~D

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, MB A4042

SCHEMATIC, MB A4042

SCHEMATIC, MB A4042

401533

401533

401533

1

A

A

51 56Tuesday, December 18, 2007

51 56Tuesday, December 18, 2007

51 56Tuesday, December 18, 2007

A

of

of

of

5

4

3

2

1

0..31 32..63

FBAD[0:63]

D D

DQMA#[0:7]
DQSA_WP[0:7]
DQSA_RN[0:7]
FBA_CMD[0..27]

FBAD[0:63] <55,56>

DQMA#[0:7] <55,56>

DQSA_WP[0:7] <55,56>
DQSA_RN[0:7] <55,56>

FBA_CMD[0..27] <55,56>

FBA_CMD0

FBA_CMD1

FBA_CMD2

FBA_CMD3

FBA_CMD4

FBA_CMD5

U44B

FBAD0
FBAD1
FBAD2
FBAD3
FBAD4
FBAD5
FBAD6
FBAD7
FBAD8
FBAD9
FBAD10
FBAD11
FBAD12
FBAD13
FBAD14
FBAD15
FBAD16

C C

B B

FBAD17
FBAD18
FBAD19
FBAD20
FBAD21
FBAD22
FBAD23
FBAD24
FBAD25
FBAD26
FBAD27
FBAD28
FBAD29
FBAD30
FBAD31
FBAD32
FBAD33
FBAD34
FBAD35
FBAD36
FBAD37
FBAD38
FBAD39
FBAD40
FBAD41
FBAD42
FBAD43
FBAD44
FBAD45
FBAD46
FBAD47
FBAD48
FBAD49
FBAD50
FBAD51
FBAD52
FBAD53
FBAD54
FBAD55
FBAD56
FBAD57
FBAD58
FBAD59
FBAD60
FBAD61
FBAD62
FBAD63

U44B

D21

FBAD0

C22

FBAD1

B22

FBAD2

A22

FBAD3

C24

FBAD4

B25

FBAD5

A25

FBAD6

A26

FBAD7

D22

FBAD8

E22

FBAD9

E24

FBAD10

D24

FBAD11

D26

FBAD12

D27

FBAD13

C27

FBAD14

B27

FBAD15

D16

FBAD16

E16

FBAD17

D17

FBAD18

F18

FBAD19

D20

FBAD20

F20

FBAD21

E21

FBAD22

F21

FBAD23

C16

FBAD24

B18

FBAD25

C18

FBAD26

D18

FBAD27

C19

FBAD28

C21

FBAD29

B21

FBAD30

A21

FBAD31

P22

FBAD32

P24

FBAD33

R23

FBAD34

R24

FBAD35

T23

FBAD36

U24

FBAD37

V23

FBAD38

V24

FBAD39

N25

FBAD40

N26

FBAD41

R25

FBAD42

R26

FBAD43

T25

FBAD44

V26

FBAD45

V25

FBAD46

V27

FBAD47

V22

FBAD48

W22

FBAD49

W23

FBAD50

W24

FBAD51

AA22

FBAD52

AB23

FBAD53

AB24

FBAD54

AC24

FBAD55

W25

FBAD56

W26

FBAD57

W27

FBAD58

AA25

FBAD59

AB25

FBAD60

AB26

FBAD61

AD26

FBAD62

AD27

FBAD63

NB9M-NS_BGA533~D

NB9M-NS_BGA533~D

Part 2 of 5

Part 2 of 5

FBA_CMD0
FBA_CMD1
FBA_CMD2
FBA_CMD3
FBA_CMD4
FBA_CMD5
FBA_CMD6
FBA_CMD7
FBA_CMD8

FBA_CMD9
FBA_CMD10
FBA_CMD11
FBA_CMD12
FBA_CMD13
FBA_CMD14
FBA_CMD15
FBA_CMD16
FBA_CMD17
FBA_CMD18
FBA_CMD19
FBA_CMD20
FBA_CMD21
FBA_CMD22
FBA_CMD23
FBA_CMD24
FBA_CMD25
FBA_CMD26
FBA_CMD27
FBA_CMD28

FBADQM0
FBADQM1

MEMORY

INTERFACE

MEMORY

INTERFACE

FBADQM2
FBADQM3
FBADQM4
FBADQM5
FBADQM6
FBADQM7

FBADQS_RN0
FBADQS_RN1
FBADQS_RN2
FBADQS_RN3
FBADQS_RN4
FBADQS_RN5
FBADQS_RN6
FBADQS_RN7

FBADQS_WP0
FBADQS_WP1
FBADQS_WP2
FBADQS_WP3
FBADQS_WP4
FBADQS_WP5
FBADQS_WP6
FBADQS_WP7

FB_VREF

FBA_CLK0

FBA_CLK0_N

FBA_CLK1

FBA_CLK1_N

FBA_DEBUG

F26
J24
F25
M23
N27
M27
K26
J25
J27
G23
G26
J23
M25
K27
G25
L24
K23
K24
G22
K25
H22
M26
H24
F27
J26
G24
G27
M24
K22

D23
C26
D19
B19
T24
T26
AA23
AB27

B24
D25
E18
A18
R22
R27
Y24
AA27

A24
C25
E19
A19
T22
T27
AA24
AA26

A16
F24

F23
N24
N23
M22

FBA_CMD0
FBA_CMD1
FBA_CMD2
FBA_CMD3
FBA_CMD4
FBA_CMD5
FBA_CMD6
FBA_CMD7
FBA_CMD8
FBA_CMD9
FBA_CMD10
FBA_CMD11
FBA_CMD12
FBA_CMD13
FBA_CMD14
FBA_CMD15
FBA_CMD16
FBA_CMD17
FBA_CMD18
FBA_CMD19
FBA_CMD20
FBA_CMD21
FBA_CMD22
FBA_CMD23
FBA_CMD24
FBA_CMD25
FBA_CMD26
FBA_CMD27
SNN_FBA_CMD28

DQMA#0
DQMA#1
DQMA#2
DQMA#3
DQMA#4
DQMA#5
DQMA#6
DQMA#7

DQSA_RN0
DQSA_RN1
DQSA_RN2
DQSA_RN3
DQSA_RN4
DQSA_RN5
DQSA_RN6
DQSA_RN7

DQSA_WP0
DQSA_WP1
DQSA_WP2
DQSA_WP3
DQSA_WP4
DQSA_WP5
DQSA_WP6
DQSA_WP7

FBA_VREF
CLKA0

CLKA0#
CLKA1
CLKA1#

R701

R701
10K_0402_5%~D

10K_0402_5%~D

12

+FBVDDQ

@

@

T114PAD~D

T114PAD~D

@

@

T115PAD~D

T115PAD~D

FBA_CMD15
FBA_CMD18

Pull-down for initialization
CKE & RESET/ODT

CLKA0 <55,56>
CLKA0# <55,56>
CLKA1 <55,56>
CLKA1# <55,56>

@

@

T88 PAD~D

T88 PAD~D

1

2

1 2

R697 10K_0402_5%~DR697 10K_0402_5%~D

1 2

R698 10K_0402_5%~DR698 10K_0402_5%~D

+FBVDDQ

1K_0402_1%~D

1K_0402_1%~D

12

R699

R699

10mil

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D
1K_0402_1%~D

1K_0402_1%~D

12

R700

R700

C775

C775

FBA_CMD6

FBA_CMD7

FBA_CMD8

FBA_CMD9

FBA_CMD10

FBA_CMD11

FBA_CMD12

FBA_CMD13

FBA_CMD14

FBA_CMD15

FBA_CMD16

FBA_CMD17

FBA_CMD18

FBA_CMD19

FBA_CMD20

FBA_CMD21

FBA_CMD22

FBA_CMD23

FBA_CMD24

FBA_CMD25

FBA_CMD26

FBA_CMD27

FBA_CMD28

FBA_CMD29

FBA_CMD30

A4

RAS#

A5

BA1 BA1

CS1#

CS0#

A11

CAS#

WE#

BA0

A12

RST/ODT

A7

A10

CKE

A0

A9

A6

A2

A8

A3

A1

A13

BA2

RFU0

RFU1 RFU1

RFU2 RFU2

RAS#

A2

A4

A3

CS1#

CS0#

A11

CAS#

WE#

BA0

A5

A12

RST/ODT

A7

A10

CKE

A0

A9

A6

A8

A1

A13

BA2

RFU0

A A

DELL CONFIDENTIAL/PROPRIETARY

Title

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

Date: Sheet

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.
SCHEMATIC, MB A4042

SCHEMATIC, MB A4042

SCHEMATIC, MB A4042

401533

401533

401533

A

A

52 56Tuesday, December 18, 2007

52 56Tuesday, December 18, 2007

52 56Tuesday, December 18, 2007

1

A

of

of

of

5

+3.3V_ALW2

12

D D

GFX_CORE_PWRGD<41,50>

C C

+1.1V_GFX_PCIE

BLM18AG121SN1D_0603~D

BLM18AG121SN1D_0603~D

1 2

B B

+3.3V_RUN

+3.3V_RUN

A A

FB_PLLVDD = 20 mA

L44

L44

1

2

DACA VDD= 120mA

L46

L46

BLM18AG121SN1D_0603~D

BLM18AG121SN1D_0603~D

1 2

DACB VDD= 150mA

L49

L49

BLM18AG121SN1D_0603~D

BLM18AG121SN1D_0603~D

1 2

GFX_CORE_PWRGD_1.8V#

61

2

+FB_PLLVDD

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

4.7U_0603_6.3V6M~D

4.7U_0603_6.3V6M~D

1

C828

C828

C646

C646

2

4.7U_0603_6.3V6M~D

4.7U_0603_6.3V6M~D

1

C852

C852

2

4.7U_0603_6.3V6M~D

4.7U_0603_6.3V6M~D

1

C867

C867

2

R815

R815
100K_0402_5%~D

100K_0402_5%~D

Q117A

Q117A
2N7002DW-T/R7_SOT363-6

2N7002DW-T/R7_SOT363-6

+FB_PLLVDD

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

1

C829

C829

2

+DACA_VDD

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

470P_0402_50V7K~D

470P_0402_50V7K~D

4700P_0402_25V7K~D

4700P_0402_25V7K~D

1

1

1

C854

C854

C853

C853

2

2

2

+DACB_VDD

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

470P_0402_50V7K~D

470P_0402_50V7K~D

4700P_0402_25V7K~D

4700P_0402_25V7K~D

1

C868

C868

1

C869

C869

2

2

1

2

C871

C871

C870

C870

5

+1.8V_MEM

+15V_ALW

100K_0402_5%~D

100K_0402_5%~D

12

R813

R813

1.8V_RUN_ENABLE

3

Q117B

Q117B
2N7002DW-T/R7_SOT363-6

2N7002DW-T/R7_SOT363-6

4

+GPU_CORE

4.7U_0603_6.3V6M~D

4.7U_0603_6.3V6M~D

1

2

0.47U_0402_6.3V4Z~D

0.47U_0402_6.3V4Z~D

1

2

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

1

2

+3.3V_RUN

8
7

5

4.7U_0603_6.3V6M~D

4.7U_0603_6.3V6M~D

1

C791

C791

C792

C792

2

0.47U_0402_6.3V4Z~D

0.47U_0402_6.3V4Z~D

1

C805

C805

C806

C806

2

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

1

C821

C821

C812

C812

2

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1

C844

C844

2

+IFPC_PLLVDD +IFPC_IOVDD

+IFPE_PLLVDD

5

4

+1.8V_RUN Source

Q116

Q116
STS11NF30L_SO8~D

STS11NF30L_SO8~D

4

1

2

4.7U_0603_6.3V6M~D

4.7U_0603_6.3V6M~D

1

1

C793

C793

2

2

0.47U_0402_6.3V4Z~D

0.47U_0402_6.3V4Z~D

1

1

C807

C807

2

2

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

1

1

C822

C822

2

2

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

1

1

C845

C845

2

2

+FBVDDQ

R722 10K_0402_5%~DR722 10K_0402_5%~D

470P_0402_50V7K~D

470P_0402_50V7K~D

1

1

C865

C865

2

2

470P_0402_50V7K~D

470P_0402_50V7K~D

1

1

C878

C878

2

2

+FBVDDQ

1
2
36

10U_0805_10V4Z~D

10U_0805_10V4Z~D

1

C889

C889

4700P_0402_25V7K~D

4700P_0402_25V7K~D

2

C897

C897

Place near Balls

10U_0805_10V4Z~D

10U_0805_10V4Z~D

C645

C645

0.47U_0402_6.3V4Z~D

0.47U_0402_6.3V4Z~D

0.47U_0402_6.3V4Z~D

0.47U_0402_6.3V4Z~D

1

1

C809

C809

C808

C808

2

2

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

1

1

C823

C823

C824

C824

2

2

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

C773

C773

+DACA_VDD
+DACB_VDD

+FB_PLLVDD

1 2

R706 44.2_0402_1%~D

R706 44.2_0402_1%~D

+DACC_VDD

12

L66

L66

BLM18AG121SN1D_0603~D

BLM18AG121SN1D_0603~D

1 2

4.7U_0603_6.3V6M~D

4.7U_0603_6.3V6M~D

4700P_0402_25V7K~D

4700P_0402_25V7K~D

1

C862

C862

C863

C863

2

L75

L75

BLM18AG121SN1D_0603~D

BLM18AG121SN1D_0603~D

1 2

4.7U_0603_6.3V6M~D

4.7U_0603_6.3V6M~D

4700P_0402_25V7K~D

4700P_0402_25V7K~D

1

C767

C767

C783

C783

2

4

0.47U_0402_6.3V4Z~D

0.47U_0402_6.3V4Z~D

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

3

+FBVDDQ

1K_0402_5%~D

1K_0402_5%~D

12

@R500

@

20K_0402_5%~D

20K_0402_5%~D

12

R814

R814

GFX_CORE_PWRGD_1.8V#

U44D

U44D

J10

VDD_0

J12

VDD_1

J13

VDD_2

J9

VDD_3

L9

VDD_4

M11

VDD_5

M17

VDD_6

M9

VDD_7

N11

VDD_8

N12

VDD_9

N13

VDD_10

N14

VDD_11

N15

VDD_12

N16

VDD_13

N17

VDD_14

0.47U_0402_6.3V4Z~D

0.47U_0402_6.3V4Z~D

1

C811

C811

C810

C810

2

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

1

C826

C826

C825

C825

2

FB_CAL_PD_VDDQ

+FBVDDQ +1.1V_GFX_PCIE

N19

VDD_15

N9

VDD_16

P11

VDD_17

P12

VDD_18

P13

VDD_19

P14

VDD_20

P15

VDD_21

P16

VDD_22

P17

VDD_23

R11

VDD_24

R12

VDD_25

R13

VDD_26

R14

VDD_27

R15

VDD_28

R16

VDD_29

R17

VDD_30

R9

VDD_31

T11

VDD_32

T17

VDD_33

T9

VDD_34

U19

VDD_35

U9

VDD_36

W10

VDD_37

W12

VDD_38

W13

VDD_39

W18

VDD_40

W19

VDD_41

W9

VDD_42

A12

VDD33_0

B12

VDD33_1

C12

VDD33_2

D12

VDD33_3

E12

VDD33_4

F12

VDD33_5

AG2

DACA_VDD

D7

DACB_VDD

W5

DACC_VDD

R19

FB_PLLAVDD

T19

FB_DLLAVDD

B15

FBCAL_PD_VDDQ

NB9M-NS_BGA533~D

NB9M-NS_BGA533~D

+IFPE_IOVDD

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

R500

2N7002W-7-F_SOT323-3~D

2N7002W-7-F_SOT323-3~D

@

@

13

D

D

Q2

Q2

2

G

G

S

S

PEX_IOVDD_0

Part 4 of 5

Part 4 of 5

PEX_IOVDD_1
PEX_IOVDD_2
PEX_IOVDD_3
PEX_IOVDD_4

PEX_IOVDD_5
PEX_IOVDDQ_0
PEX_IOVDDQ_1
PEX_IOVDDQ_2
PEX_IOVDDQ_3
PEX_IOVDDQ_4
PEX_IOVDDQ_5
PEX_IOVDDQ_6
PEX_IOVDDQ_7
PEX_IOVDDQ_8
PEX_IOVDDQ_9

PEX_IOVDDQ_10
PEX_IOVDDQ_11

PEX_PLLVDD

VDD_SENSE

FBVDDQ_0
FBVDDQ_1
FBVDDQ_2
FBVDDQ_3
FBVDDQ_4
FBVDDQ_5
FBVDDQ_6
FBVDDQ_7
FBVDDQ_8
FBVDDQ_9

FBVDDQ_10

POWER

POWER

FBVDDQ_11
FBVDDQ_12
FBVDDQ_13
FBVDDQ_14
FBVDDQ_15
FBVDDQ_16
FBVDDQ_17
FBVDDQ_18
FBVDDQ_19
FBVDDQ_20
FBVDDQ_21
FBVDDQ_22
FBVDDQ_23
FBVDDQ_24
FBVDDQ_25

IFPA_IOVDD
IFPB_IOVDD
IFPC_IOVDD
IFPE_IOVDD

IFPAB_PLLVDD

IFPC_PLLVDD

IFPE_PLLVDD

PLLVDD

VID_PLLVDD

SP_PLLVDD

L67

L67

BLM18AG121SN1D_0603~D

BLM18AG121SN1D_0603~D

1 2

4.7U_0603_6.3V6M~D

4.7U_0603_6.3V6M~D

4700P_0402_25V7K~D

4700P_0402_25V7K~D

470P_0402_50V7K~D

470P_0402_50V7K~D

1

1

1

C880

C880

2

470P_0402_50V7K~D

470P_0402_50V7K~D

1

C888

C888

2

C866

C866

C879

C879

2

2

BLM18AG121SN1D_0603~D

BLM18AG121SN1D_0603~D

1 2

4700P_0402_25V7K~D

4700P_0402_25V7K~D

4.7U_0603_6.3V6M~D

4.7U_0603_6.3V6M~D

1

1

C777

C777

C794

C794

2

2

3

L76

L76

AC9
AD7
AD8
AE7
AF7
AG7
AB13
AB16
AB17
AB7
AB8
AB9
AC13
AC7
AD6
AE6
AF6
AG6

AF9
W15
A13

B13
C13
D13
D14
E13
F13
F14
F15
F16
F17
F19
F22
H23
H26
J15
J16
J18
J19
L19
L23
L26
M19
N22
U22
Y22

V3
V2
J6
H6

AD5
P6
N6

K5
K6
L6

G_VDD_S

+IFPAB_IOVDD
+IFPC_IOVDD

+IFPE_IOVDD
+IFPAB_PLLVDD

+IFPC_PLLVDD
+IFPE_PLLVDD

+GPU_PLLVDD

Place near Balls

PEX_IOVDD = 500mA

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

1

1

1

C778

C778

2

C780

C780

C779

C779

2

2

Place near Balls

PEX_IOVDDQ = 1600mA

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

1U_0402_6.3V6K~D

1

2

1

2

1

2

C796

C796

0.022U_0402_16V7K~D

0.022U_0402_16V7K~D

C814

C814

4700P_0402_25V7K~D

4700P_0402_25V7K~D

C831

C831

1U_0402_6.3V6K~D

1

C797

C797

2

+PEX_PLLVDD

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

1

C815

C815

2

4700P_0402_25V7K~D

4700P_0402_25V7K~D

1

C832

C832

2

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

1

C795

C795

2

1 2

R852 0_0402_5%~DR852 0_0402_5%~D

0.022U_0402_16V7K~D

0.022U_0402_16V7K~D

1

C813

C813

2

4700P_0402_25V7K~D

4700P_0402_25V7K~D

1

C830

C830

2

+IFPX_IOVDD= 385mA

+IFPX_PLLVDD= 160mA

IFPAB_IOVDD = 100mA

+IFPAB_IOVDD

4700P_0402_25V7K~D

4700P_0402_25V7K~D

470P_0402_50V7K~D

470P_0402_50V7K~D

1

1

C843

C843

2

2

2

+1.1V_GFX_PCIE

4.7U_0603_6.3V4Z~D

4.7U_0603_6.3V4Z~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1

1

C774

C774

2

2

Place near GPU

+1.1V_GFX_PCIE

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1

C798

C798

2

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D
1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1

C816

C816

2

4700P_0402_25V7K~D

4700P_0402_25V7K~D

4700P_0402_25V7K~D

4700P_0402_25V7K~D

1

C833

C833

2

470P_0402_50V7K~D

470P_0402_50V7K~D

1

C860

C860

2

1

C799

C799

2

1

C817

C817

2

1

C834

C834

2

BLM18AG121SN1D_0603~D

BLM18AG121SN1D_0603~D

4700P_0402_25V7K~D

4700P_0402_25V7K~D

1

2

2

1

2

GPU_VDD_SENSE <50>

1

2

1

2

C858

C858

C782

C782

C861

C861

22U_0805_6.3VAM~D

22U_0805_6.3VAM~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

0.022U_0402_16V7K~D

0.022U_0402_16V7K~D

22U_0805_6.3VAM~D

22U_0805_6.3VAM~D

1

C604

C604

2

C800

C800

+FBVDDQ

1

C818

C818

2

1

C835

C835

2

L48

L48

1 2

4.7U_0603_6.3V6M~D

4.7U_0603_6.3V6M~D

1

C864

C864

2

PEX_PLLVDD = 100mA

+PEX_PLLVDD

1

2

10 mil

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

C784

C784

0.01U_0402_16V7K~D

0.01U_0402_16V7K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1

1

C785

C785

C786

C786

2

2

Place near Balls Place near GPU

4.7U_0603_6.3V4Z~D

4.7U_0603_6.3V4Z~D

4.7U_0603_6.3V4Z~D

4.7U_0603_6.3V4Z~D

1

C819

C819

C820

C820

2

+FBVDDQ

0.1U_0402_10V7K~D

0.022U_0402_16V7K~D

0.022U_0402_16V7K~D

0.022U_0402_16V7K~D

C836

C836

0.022U_0402_16V7K~D

0.022U_0402_16V7K~D

0.022U_0402_16V7K~D

1

1

C838

C838

C837

C837

2

2

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

1

C839

C839

2

0.1U_0402_10V7K~D

1

1

1

C840

C840

C841

C841

2

2

2

GPU_PLLVDD = 140 mA

+GPU_PLLVDD+DACC_VDD

+FBVDDQ

4700P_0402_25V7K~D

4700P_0402_25V7K~D

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

1

1

C848

C848

C847

C847

2

2

IFPAB_PLLVDD = 100 mA

+IFPAB_PLLVDD

4700P_0402_25V7K~D

4700P_0402_25V7K~D

220P_0402_50V8K~D

220P_0402_50V8K~D

1

1

C856

C856

C855

C855

2

2

1

2

1

2

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

Date: Sheet

Compal Electronics, Inc.

401533

401533

401533

1

+1.1V_GFX_PCIE

4.7U_0603_6.3V4Z~D

4.7U_0603_6.3V4Z~D

1

2

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

C842

C842

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1

C849

C849

2

BLM18AG121SN1D_0603~D

BLM18AG121SN1D_0603~D

4.7U_0603_6.3V6M~D

4.7U_0603_6.3V6M~D

C857

C857

SCHEMATIC, MB A4042

SCHEMATIC, MB A4042

SCHEMATIC, MB A4042

12

L65

L65
10UH_LB2012T100MR_20%_0805~D

10UH_LB2012T100MR_20%_0805~D

C787

C787

+1.1V_GFX_PCIE

1 2

L45

L45

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

BLM18AG121SN1D_0603~D

BLM18AG121SN1D_0603~D

C850

C850

+FBVDDQ

L47

L47

1 2

1

4.7U_0603_6.3V6M~D

4.7U_0603_6.3V6M~D

1

C859

C859

2

53 56Tuesday, December 18, 2007

53 56Tuesday, December 18, 2007

53 56Tuesday, December 18, 2007

of

of

of

A

A

A

5

4

3

2

1

D D

U44E

U44E

AC11

GND_0

AC14

GND_1

AC17

GND_2

C C

B B

A A

5

AC2

GND_3

AC20

GND_4

AC23

GND_5

AC26

GND_6

AC5

GND_7

AC8

GND_8

AF11

GND_9

AF14

GND_10

AF17

GND_11

AF2

GND_12

AF20

GND_13

AF23

GND_14

AF26

GND_15

AF5

GND_16

AF8

GND_17

B11

GND_18

B14

GND_19

B17

GND_20

B2

GND_21

B20

GND_22

B23

GND_23

B26

GND_24

B5

GND_25

B8

GND_26

E11

GND_27

E14

GND_28

E17

GND_29

E2

GND_30

E20

GND_31

E23

GND_32

E26

GND_33

E5

GND_34

E8

GND_35

H2

GND_36

H5

GND_37

J11

GND_38

J14

GND_39

J17

GND_40

K19

GND_41

K9

GND_42

L11

GND_43

L12

GND_44

L13

GND_45

L14

GND_46

L15

GND_47

NB9M-NS_BGA533~D

NB9M-NS_BGA533~D

Part 5 of 5

Part 5 of 5

GND

GND

FBCAL_TERM_GND

RFU_GND

GND_SENSE

FBCAL_PU_GND

GND_48
GND_49
GND_50
GND_51
GND_52
GND_53
GND_54
GND_55
GND_56
GND_57
GND_58
GND_59
GND_60
GND_61
GND_62
GND_63
GND_64
GND_65
GND_66
GND_67
GND_68
GND_69
GND_70
GND_71
GND_72
GND_73
GND_74
GND_75
GND_76
GND_77
GND_78
GND_79
GND_80
GND_81
GND_82
GND_83
GND_84
GND_85
GND_86
GND_87

L16
L17
L2
L5
M12
M13
M14
M15
M16
P19
P2
P23
P26
P5
P9
T12
T13
T14
T15
T16
U11
U12
U13
U14
U15
U16
U17
U2
U23
U26
U5
V19
V9
W11
W14
W17
Y2
Y23
Y26
Y5

AC6
W16
A15

B16

GND_SENSE
FB_CAL_PU_GND

FBCAL_TERM_GND

1 2

R707 0_0402_5%~DR707 0_0402_5%~D

1 2

R703 30.9_0402_1%R703 30.9_0402_1%

1 2

R84 40.2_0402_1%~D

R84 40.2_0402_1%~D

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

4

3

2

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, MB A4042

SCHEMATIC, MB A4042

SCHEMATIC, MB A4042

401533

401533

401533

A

A

A

54 56Monday, December 17, 2007

54 56Monday, December 17, 2007

54 56Monday, December 17, 2007

of

of

1

of

5

FBA_CMD19
FBA_CMD25

T143T143

+FBVDDQ

FBA_CMD22
FBA_CMD24
FBA_CMD0
FBA_CMD2
FBA_CMD21
FBA_CMD16
FBA_CMD23
FBA_CMD20
FBA_CMD17
FBA_CMD9

FBA_CMD12
FBA_CMD3
DQMA#3
DQMA#2
DQMA#1
DQMA#0

DQSA_WP3
DQSA_WP2
DQSA_WP1
DQSA_WP0

FBA_VREF_1
FBA_VREF_2

FBA_CMD1
FBA_CMD10
FBA_CMD11
FBA_CMD8
FBA_CMD14
FBA_CMD18
CLKA0
CLKA0#

ZQ1

DQSA_RN3
DQSA_RN2
DQSA_RN1
DQSA_RN0

FBA_CMD15
FBA_CMD27

H11
K10

K11

E10
N10

D11
P11

H12

D10
P10

A11
F12
M12
V11

H10

+FBVDDQ

D D

CLKA0

R750

R750
475_0402_1%~D

475_0402_1%~D

1 2

CLKA0#

243 ohm for NB8P
475 ohm for NB9X
Place close to U57

C C

FBA_VREF_1
FBA_VREF_2

B B

A A

Avia

FBA_VREF_5

2

G

G

need check new value for NB9M

FBA_VREF_1 <56>
FBA_VREF_2 <56> FBA_VREF_3 <56>

+FBVDDQ

12

R734

R734
511_0402_1%~D

511_0402_1%~D

R870

R870

R887

R887

+FBVDDQ

12 mil

FBA_VREF_1

12

12

R738

R738
511_0402_1%~D

511_0402_1%~D

12 mil

FBA_VREF_2

12

R866

R866

1 2

909_0402_1%~D

909_0402_1%~D

1.18K_0402_1%~D

1.18K_0402_1%~D

13

D

D

Q119

Q119

S

S

R869

R869

2N7002W-7-F_SOT323-3~D

2N7002W-7-F_SOT323-3~D

1 2

909_0402_1%~D

909_0402_1%~D

1.18K_0402_1%~D

1.18K_0402_1%~D

GPIO10_REF_SW <51>

5

CLKA0<52,56>
CLKA0#<52,56>

1 2

R862

R862

243_0402_1%~D

243_0402_1%~D

0.01U_0402_16V7K~D

0.01U_0402_16V7K~D

1

C872

C872

2

0.01U_0402_16V7K~D

0.01U_0402_16V7K~D

1

C919

C919

2

4

32Mx32 GDDR3

B12

D12

G11

U57

U57

VSSQB1VSSQB4VSSQB9VSSQ

A0
A1
A2
A3
A4
A5
A6
A7
A8/AP
A9
A10
A11
A12
BA0
BA1
DM0
DM1
DM2
DM3

WDQS0
WDQS1
WDQS2
WDQS3

VREF
VREF

RAS#
CAS#
WE#
CS0#
A12/CS1#
CKE
CK
CK#

ZQ
MF

RDQS0
RDQS1
RDQS2
RDQS3

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

SEN
RESET
BA2

VSSA
VSSA

VSSQD1VSSQD4VSSQD9VSSQ

K4

H2

K3

M4

K9

L9

M9

K2
L4

J2
G4
G9

E3

N3
D2

P2
H1

H3

F4
H9

F9

J3
H4

J11
J10

A4

A9
D3

P3

A2

F1
M1

V2

V4

V9

J1

J12

Place below decoupling caps close U57

4.7U_0603_6.3V6M~D

4.7U_0603_6.3V6M~D

4.7U_0603_6.3V6M~D

4.7U_0603_6.3V6M~D

1

1

C908

C908

C909

C909

2

2

0.01U_0402_16V7K~D

0.01U_0402_16V7K~D

C894

C894

1

2

4

L11

VSSQG2VSSQ

VSSQL2VSSQ

VSSQP1VSSQP4VSSQP9VSSQ

VSSA3VSS

VSSG1VSS

VSSL1VSS

VSSV3VSS

K4J10324QD-BC12_FBGA136~D

K4J10324QD-BC12_FBGA136~D

L12

A10

V10

G12

4.7U_0603_6.3V6M~D

4.7U_0603_6.3V6M~D

C890

C890

1

2

0.01U_0402_16V7K~D

0.01U_0402_16V7K~D

C895

C895

1

2

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

1

1

C910

C910

2

2

0.01U_0402_16V7K~D

0.01U_0402_16V7K~D

0.01U_0402_16V7K~D

0.01U_0402_16V7K~D

C896

C896

1

1

2

2

P12

VSSQT1VSSQT4VSSQT9VSSQ

DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

VDDA
VDDA

1

C911

C911

2

1

C913

C913

2

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9

3

2

1

32Mx32 GDDR3

FBAD[0..63]
DQSA_WP[0..7]

FBA_VREF_6

13

D

D

2

G

G

S

S

GPIO10_REF_SW <51>

DQSA_RN[0..7]
DQMA#[0..7]
FBA_CMD[0..27]

R831

R831

1 2

909_0402_1%~D

909_0402_1%~D

1.18K_0402_1%~D

1.18K_0402_1%~D

Q118

Q118

R867

R867

2N7002W-7-F_SOT323-3~D

2N7002W-7-F_SOT323-3~D

1 2

909_0402_1%~D

909_0402_1%~D

R868

R868

1.18K_0402_1%~D

1.18K_0402_1%~D

R832

R832

T12

+FBVDDQ

4.7U_0603_6.3V6M~D

4.7U_0603_6.3V6M~D

1

2

0.01U_0402_16V7K~D

0.01U_0402_16V7K~D

1

2

+FBVDDQ

1

C881

C881

2

1

C886

C886

2

FBA_CMD5
FBA_CMD13
FBA_CMD21
FBA_CMD20
FBA_CMD19
FBA_CMD25
FBA_CMD4
FBA_CMD9
FBA_CMD17
FBA_CMD6
FBA_CMD23
FBA_CMD16

FBA_CMD3
FBA_CMD12
DQMA#7
DQMA#6
DQMA#4
DQMA#5

DQSA_WP7
DQSA_WP6
DQSA_WP4
DQSA_WP5

FBA_VREF_3
FBA_VREF_4

FBA_CMD27
FBA_CMD8
FBA_CMD18
FBA_CMD10
FBA_CMD14
FBA_CMD11
CLKA1
CLKA1#

DQSA_RN7
DQSA_RN6
DQSA_RN4
DQSA_RN5

FBA_CMD15
FBA_CMD1

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

1

C882

C882

2

0.01U_0402_16V7K~D

0.01U_0402_16V7K~D

1

C887

C887

2

ZQ2

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

1

C884

C884

C883

C883

2

0.01U_0402_16V7K~D

0.01U_0402_16V7K~D

0.01U_0402_16V7K~D

0.01U_0402_16V7K~D

1

C905

C905

C904

C904

2

FBAD25

B2

FBAD26

B3

FBAD27

C2

FBAD24

C3

FBAD29

E2

FBAD28

F3

FBAD31

F2

FBAD30

G3

FBAD17

B11

FBAD16

B10

FBAD18

C11

FBAD21

C10

FBAD20

E11

FBAD22

F10

FBAD23

F11

FBAD19

G10

FBAD9

M11

FBAD8

L10

FBAD15

N11

FBAD14

M10

FBAD12

R11

FBAD11

R10

FBAD10

T11

FBAD13

T10

FBAD5

M2

FBAD7

L3

FBAD4

N2

FBAD6

M3

FBAD3

R2

FBAD1

R3

FBAD2

T2

FBAD0

T3

A1

+FBVDDQ

A12
C1
C4
C9
C12
E1
E4
E9
E12
J4
J9
N1
N4
N9
N12
R1
R4
R9
R12
V1
V12

K1
K12

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

C892

C892

C891

C891

1

2

0.01U_0402_16V7K~D

0.01U_0402_16V7K~D

0.01U_0402_16V7K~D

0.01U_0402_16V7K~D

1

C914

C914

C915

C915

2

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

C893

C893

1

1

C912

C912

2

2

0.01U_0402_16V7K~D

0.01U_0402_16V7K~D

1

C916

C916

2

Mirror U58

RAS# --> BA2
CAS# --> CS0#
WE --> CKE
CS0# --> CAS#
A0 --> A4
A1 --> A5
A2 --> A6
A3 --> A9
A4 --> A0
A5 --> A1
A6 --> A2
A7 --> A11
A8 --> A10
A9 --> A3
A10 --> A8
A11 --> A7
CKE --> WE#
BA0 --> BA1
BA1 --> BA0
BA2 --> RAS#
NC/CS1# --> NV/CS1#

243_0402_1%~D

243_0402_1%~D

FBA_VREF_3
FBA_VREF_4

+FBVDDQ

1

2

FBA_VREF_4 <56>

4.7U_0603_6.3V6M~D

4.7U_0603_6.3V6M~D

C899

C899

T144T144

CLKA1<52,56>
CLKA1#<52,56>

1 2

R863

R863

Place below decoupling caps close U58

4.7U_0603_6.3V6M~D

4.7U_0603_6.3V6M~D

1

C900

C900

2

0.01U_0402_16V7K~D

0.01U_0402_16V7K~D

1

C885

C885

2

B12

VSSQB1VSSQB4VSSQB9VSSQ

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

1

C902

C902

2

0.01U_0402_16V7K~D

0.01U_0402_16V7K~D

1

C907

C907

2

D12

VSSQD1VSSQD4VSSQD9VSSQ

VSSA3VSS

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

1

C903

C903

2

U58

U58

K4

A0

H2

A1

K3

A2

M4

A3

K9

A4

H11

A5

K10

A6

L9

A7

K11

A8/AP

M9

A9

K2

A10

L4

A11

J2

A12

G4

BA0

G9

BA1

E3

DM0

E10

DM1

N10

DM2

N3

DM3

D2

WDQS0

D11

WDQS1

P11

WDQS2

P2

WDQS3

H1

VREF

H12

VREF

U58 is Mirror

H3

RAS#

F4

CAS#

H9

WE#

F9

CS0#

J3

A12/CS1#

H4

CKE

J11

CK

J10

CK#

A4

ZQ

A9

MF

D3

RDQS0

D10

RDQS1

P10

RDQS2

P3

RDQS3

A2

VDD

A11

VDD

F1

VDD

F12

VDD

M1

VDD

M12

VDD

V2

VDD

V11

VDD

V4

SEN

V9

RESET

H10

BA2

J1

VSSA

J12

VSSA

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

1

C901

C901

2

0.01U_0402_16V7K~D

0.01U_0402_16V7K~D

1

C906

C906

2

G11

VSSQG2VSSQ

A10

VSSQL2VSSQ

VSSG1VSS

G12

L11

VSSQP1VSSQP4VSSQP9VSSQ

VSSL1VSS

L12

VSSV3VSS

P12

T12

VSSQT1VSSQT4VSSQT9VSSQ

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8

DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

VDDA
VDDA

K4J10324QD-BC12_FBGA136~D

K4J10324QD-BC12_FBGA136~D

V10

FBAD62

B2

FBAD61

B3

FBAD60

C2

FBAD63

C3

FBAD58

E2

FBAD57

F3

FBAD56

F2

FBAD59

G3

FBAD55

B11

FBAD52

B10

FBAD54

C11

FBAD53

C10

FBAD48

E11

FBAD49

F10

FBAD50

F11

FBAD51

G10

FBAD37

M11

FBAD38

L10

FBAD36

N11

FBAD39

M10

FBAD35

R11

FBAD32

R10

FBAD34

T11

FBAD33

T10

FBAD44

M2

FBAD45

L3

FBAD47

N2

FBAD46

M3

FBAD42

R2

FBAD43

R3

FBAD41

T2

FBAD40

T3

A1
A12
C1
C4
C9
C12
E1
E4
E9
E12
J4
J9
N1
N4
N9
N12
R1
R4
R9
R12
V1
V12

K1
K12

+FBVDDQ

need check new value for NB9M

FBAD[0..63] <52,56>

DQSA_WP[0..7] <52,56>
DQSA_RN[0..7] <52,56>
DQMA#[0..7] <52,56>

FBA_CMD[0..27] <52,56>

CLKA1

1 2

CLKA1#

243 ohm for NB8P
475 ohm for NB9X
Place close to U58

+FBVDDQ

12

R864

R864
511_0402_1%~D

511_0402_1%~D

12 mil

FBA_VREF_3

12

+FBVDDQ

12

12

R865

R865
511_0402_1%~D

511_0402_1%~D

12 mil

FBA_VREF_4

1

2

1

2

R824

R824
475_0402_1%~D

475_0402_1%~D

0.01U_0402_16V7K~D

0.01U_0402_16V7K~D

C917

C917

0.01U_0402_16V7K~D

0.01U_0402_16V7K~D

C918

C918

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

2

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, MB A4042

SCHEMATIC, MB A4042

SCHEMATIC, MB A4042

401533

401533

401533

A

A

55 56Monday, December 17, 2007

55 56Monday, December 17, 2007

55 56Monday, December 17, 2007

1

A

of

of

of

5

4

32Mx32 GDDR3

3

2

1

32Mx32 GDDR3

B12

D12

G11

L11

P12

U59

U59

Mirror U59

RAS# --> BA2

D D

C C

B B

CAS# --> CS0#
WE --> CKE
CS0# --> CAS#
A0 --> A4
A1 --> A5
A2 --> A6
A3 --> A9
A4 --> A0
A5 --> A1
A6 --> A2
A7 --> A11
A8 --> A10
A9 --> A3
A10 --> A8
A11 --> A7
CKE --> WE#
BA0 --> BA1
BA1 --> BA0
BA2 --> RAS#
NC/CS1# --> NV/CS1#

FBA_VREF_1
FBA_VREF_2

1 2

R873

R873

243_0402_1%~D

243_0402_1%~D

FBA_VREF_1 <55>
FBA_VREF_2 <55> FBA_VREF_3 <55>

CLKA0<52,55>
CLKA0#<52,55>

T40T40

ZQ3

+FBVDDQ

+FBVDDQ

FBA_CMD0
FBA_CMD2
FBA_CMD21
FBA_CMD20
FBA_CMD19
FBA_CMD25
FBA_CMD22
FBA_CMD9
FBA_CMD17
FBA_CMD24
FBA_CMD23
FBA_CMD16

FBA_CMD3
FBA_CMD12
DQMA#2
DQMA#3
DQMA#0
DQMA#1

DQSA_WP2
DQSA_WP3

DQSA_WP1
FBA_VREF_1

FBA_VREF_2

FBA_CMD27
FBA_CMD7
FBA_CMD18
FBA_CMD10
FBA_CMD14
FBA_CMD11
CLKA0
CLKA0#

DQSA_RN2
DQSA_RN3
DQSA_RN0
DQSA_RN1

FBA_CMD15
FBA_CMD1

VSSQB1VSSQB4VSSQB9VSSQ

VSSQD1VSSQD4VSSQD9VSSQ

K4

A0

H2

A1

K3

A2

M4

A3

K9

A4

H11

A5

K10

A6

L9

A7

K11

A8/AP

M9

A9

K2

A10

L4

A11

J2

A12

G4

BA0

G9

BA1

E3

DM0

E10

DM1

N10

DM2

N3

DM3

D2

WDQS0

D11

WDQS1

P11

WDQS2

P2

WDQS3

H1

VREF

H12

VREF

U59 is Mirror

H3

RAS#

F4

CAS#

H9

WE#

F9

CS0#

J3

A12/CS1#

H4

CKE

J11

CK

J10

CK#

A4

ZQ

A9

MF

D3

RDQS0

D10

RDQS1

P10

RDQS2

P3

RDQS3

A2

VDD

A11

VDD

F1

VDD

F12

VDD

M1

VDD

M12

VDD

V2

VDD

V11

VDD

V4

SEN

V9

RESET

H10

BA2

J1

VSSA

J12

VSSA

VSSQG2VSSQ

VSSA3VSS

A10

VSSQL2VSSQ

VSSG1VSS

G12

VSSL1VSS

L12

T12

VSSQP1VSSQP4VSSQP9VSSQ

VSSQT1VSSQT4VSSQT9VSSQ

B2

DQ0

B3

DQ1

C2

DQ2

C3

DQ3

E2

DQ4

F3

DQ5

F2

DQ6

G3

DQ7

B11

DQ8

B10

DQ9

C11

DQ10

C10

DQ11

E11

DQ12

F10

DQ13

F11

DQ14

G10

DQ15

M11

DQ16

L10

DQ17

N11

DQ18

M10

DQ19

R11

DQ20

R10

DQ21

T11

DQ22

T10

DQ23

M2

DQ24

L3

DQ25

N2

DQ26

M3

DQ27

R2

DQ28

R3

DQ29

T2

DQ30

T3

DQ31

A1

VDDQ

A12

VDDQ

C1

VDDQ

C4

VDDQ

C9

VDDQ

C12

VDDQ

E1

VDDQ

E4

VDDQ

E9

VDDQ

E12

VDDQ

J4

VDDQ

J9

VDDQ

N1

VDDQ

N4

VDDQ

N9

VDDQ

N12

VDDQ

R1

VDDQ

R4

VDDQ

R9

VDDQ

R12

VDDQ

V1

VDDQ

V12

VDDQ

K1

VDDA

K12

VDDA

VSSV3VSS

K4J10324QD-BC12_FBGA136~D

K4J10324QD-BC12_FBGA136~D

V10

FBAD17
FBAD16
FBAD18
FBAD21
FBAD20
FBAD22
FBAD23
FBAD19
FBAD25
FBAD26
FBAD27
FBAD24
FBAD29
FBAD28
FBAD31
FBAD30
FBAD5
FBAD7
FBAD4
FBAD6
FBAD3
FBAD1DQSA_WP0
FBAD2
FBAD0
FBAD9
FBAD8
FBAD15
FBAD14
FBAD12
FBAD11
FBAD10
FBAD13

+FBVDDQ

FBAD9
FBAD8
FBAD14
FBAD15
FBAD12
FBAD11
FBAD10
FBAD13

1 2

R874

R874

243_0402_1%~D

243_0402_1%~D

FBA_VREF_3
FBA_VREF_4

T146T146

CLKA1<52,55>
CLKA1#<52,55>

+FBVDDQ

FBA_VREF_4 <55>

FBA_CMD19
FBA_CMD25
FBA_CMD4
FBA_CMD6
FBA_CMD5
FBA_CMD13
FBA_CMD21
FBA_CMD16
FBA_CMD23
FBA_CMD20
FBA_CMD17
FBA_CMD9

FBA_CMD12
FBA_CMD3
DQMA#6
DQMA#7
DQMA#5
DQMA#4

DQSA_WP6
DQSA_WP7
DQSA_WP5
DQSA_WP4

FBA_VREF_3
FBA_VREF_4

FBA_CMD1
FBA_CMD10
FBA_CMD11
FBA_CMD7
FBA_CMD14
FBA_CMD18
CLKA1
CLKA1#

ZQ4

DQSA_RN6
DQSA_RN7
DQSA_RN5
DQSA_RN4

FBA_CMD15
FBA_CMD27

B12

D12

G11

L11

VSSQB1VSSQB4VSSQB9VSSQ

VSSQD1VSSQD4VSSQD9VSSQ

VSSQG2VSSQ

VSSQL2VSSQ

VSSA3VSS

A10

VSSG1VSS

G12

VSSQP1VSSQP4VSSQP9VSSQ

VSSL1VSS

VSSV3VSS

L12

K4

A0

H2

A1

K3

A2

M4

A3

K9

A4

H11

A5

K10

A6

L9

A7

K11

A8/AP

M9

A9

K2

A10

L4

A11

J2

A12

G4

BA0

G9

BA1

E3

DM0

E10

DM1

N10

DM2

N3

DM3

D2

WDQS0

D11

WDQS1

P11

WDQS2

P2

WDQS3

H1

VREF

H12

VREF

H3

RAS#

F4

CAS#

H9

WE#

F9

CS0#

J3

A12/CS1#

H4

CKE

J11

CK

J10

CK#

A4

ZQ

A9

MF

D3

RDQS0

D10

RDQS1

P10

RDQS2

P3

RDQS3

A2

VDD

A11

VDD

F1

VDD

F12

VDD

M1

VDD

M12

VDD

V2

VDD

V11

VDD

V4

SEN

V9

RESET

H10

BA2

J1

VSSA

J12

VSSA

P12

V10

T12

VSSQT1VSSQT4VSSQT9VSSQ

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8

DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

VDDA
VDDA

U60

U60
K4J10324QD-BC12_FBGA136~D

K4J10324QD-BC12_FBGA136~D

FBAD55

B2

FBAD52

B3

FBAD54

C2

FBAD53

C3

FBAD48

E2

FBAD49

F3

FBAD50

F2

FBAD51

G3

FBAD62

B11

FBAD61

B10

FBAD60

C11

FBAD63

C10

FBAD58

E11

FBAD57

F10

FBAD56

F11

FBAD59

G10

FBAD44

M11

FBAD45

L10

FBAD47

N11

FBAD46

M10

FBAD42

R11

FBAD43

R10

FBAD41

T11

FBAD40

T10

FBAD37

M2

FBAD38

L3

FBAD36

N2

FBAD39

M3

FBAD35

R2

FBAD32

R3

FBAD34

T2

FBAD33

T3

A1

+FBVDDQ

A12
C1
C4
C9
C12
E1
E4
E9
E12
J4
J9
N1
N4
N9
N12
R1
R4
R9
R12
V1
V12

K1
K12

FBAD[0..63]
DQSA_WP[0..7]
DQSA_RN[0..7]
DQMA#[0..7]
FBA_CMD[0..27]

FBAD[0..63] <52,55>

DQSA_WP[0..7] <52,55>
DQSA_RN[0..7] <52,55>
DQMA#[0..7] <52,55>

FBA_CMD[0..27] <52,55>

+FBVDDQ

A A

Place below decoupling caps close U48

4.7U_0603_6.3V6M~D

4.7U_0603_6.3V6M~D

4.7U_0603_6.3V6M~D

4.7U_0603_6.3V6M~D

0.1U_0402_10V7K~D

4.7U_0603_6.3V6M~D

4.7U_0603_6.3V6M~D

1

1

C961

C961

C960

C960

2

2

0.01U_0402_16V7K~D

0.01U_0402_16V7K~D

1

C946

C946

2

0.1U_0402_10V7K~D

C942

C942

C947

C947

1

1

C943

C943

2

2

0.01U_0402_16V7K~D

0.01U_0402_16V7K~D

1

1

C948

C948

2

2

1

2

0.01U_0402_16V7K~D

0.01U_0402_16V7K~D

1

2

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

1

C945

C945

C944

C944

2

0.01U_0402_16V7K~D

0.01U_0402_16V7K~D

0.01U_0402_16V7K~D

0.01U_0402_16V7K~D

1

C966

C966

C965

C965

2

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

1

C962

C962

2

0.01U_0402_16V7K~D

0.01U_0402_16V7K~D

1

C967

C967

2

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

1

1

C963

C963

C964

C964

2

2

0.01U_0402_16V7K~D

0.01U_0402_16V7K~D

1

C968

C968

2

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

+FBVDDQ

3

Place below decoupling caps close U49

4.7U_0603_6.3V6M~D

4.7U_0603_6.3V6M~D

4.7U_0603_6.3V6M~D

1

C969

C969

2

4.7U_0603_6.3V6M~D

4.7U_0603_6.3V6M~D

4.7U_0603_6.3V6M~D

1

1

C951

C951

C970

C970

2

2

0.01U_0402_16V7K~D

0.01U_0402_16V7K~D

0.01U_0402_16V7K~D

0.01U_0402_16V7K~D

1

1

C955

C955

C956

C956

2

2

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

1

1

C952

C952

2

2

0.01U_0402_16V7K~D

0.01U_0402_16V7K~D

0.01U_0402_16V7K~D

0.01U_0402_16V7K~D

1

1

C957

C957

2

2

C953

C953

C974

C974

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

1

C971

C971

2

0.01U_0402_16V7K~D

0.01U_0402_16V7K~D

1

C975

C975

2

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

1

C972

C972

2

0.01U_0402_16V7K~D

0.01U_0402_16V7K~D

1

C976

C976

2

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

1

1

C954

C954

C973

C973

2

2

0.01U_0402_16V7K~D

0.01U_0402_16V7K~D

1

C977

C977

2

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, MB A4042

SCHEMATIC, MB A4042

SCHEMATIC, MB A4042

401533

401533

401533

A

A

56 56Monday, December 17, 2007

56 56Monday, December 17, 2007

56 56Monday, December 17, 2007

1

A

of

of

of