Compal LA-4021P Schematic 2007-10-26 Rev 0.1

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1 1

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D

E

Compal confidential

Schematics Document

Mobile Penryn uFCPGA with Intel

2 2

Cantiga_GM+ICH9-M SFF core logic

SKYY

2007-10-26

3 3

4 4

A

B

Security Classification

Issued Date

THIS SHEET OF EN GINEE RING D RAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR DISCLO SED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2006/02/13 2006/03/10

Compal Secret Data

Deciphered Date

D

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

Cover Sheet

LA-4021P

E

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Compal confidential

File Name : LA-4021P

B

C

D

E

SKYY

Docking CONN.(Opus 1.0)

1 1

2 2

*RJ-45(LED*2)
*CRT
*S-VIDEO OUT
*LINE IN
*LINE OUT
*USB x4
*DC JACK

*Power on signal
*Docked indicator
signal
*AC present indicator
signal

Express Card 54

PCIE X1 + USB X1

page 25

WWAN Card

WWAN + PCIE X1
+ USB X1

page 25

Thermal Sensor
EMC2103

page 4

Fan Control

page 4

LCD conn

page 18

CRT

page 17

CRT to docking

page 34

S-Video to Docking

page 34

Mobile Penym

LV/ULV Dual Core

uFCPGA-956 CPU - SFF

page 4,5,6,7

H_A#(3..35)
H_D#(0..63)

FSB

667/800/1066MHz 1.05V

Intel Cantiga GMS

FCBGA 1363 - SFF

page 8,9,10,11,12,13

DMI X4

DDR2 800MHz 1.8V

Dual Channel

CK505

Clock Generator
ICS9LPRS397

page 16

DDR2-SO-DIMM X 2

BANK 0, 1, 2, 3

USB x1(Docking)
FingerPrinter AES2810

USBx1

page 14,15

page 34

page 31

Accelerometer

LIS302DLTR

page 26

daughter board

USB conn x 3(For I/O)

PCI-E BUS

Intel ICH9-M

10/100/1000 LAN

Intel Boaz GbE

PHY

page 24

CardBus Controller

Rico R5C833

page 27

PCI BUS

24HST1041A-3

3 3

RJ45 CONN

page 25

LED

page 19

1394 port

SD/MMC Slot

LPC BUS

WBMMAP-569 - SFF

page 20,21,22,23

SPI ROM

AT26DF321

page 32

SPI

USB2.0
Azalia

SATA0

SATA1

BT Conn USB x 1

USB x1(Camara)

page 18

page 31

MDC V1.5

page 30

Audio CKT

AD1984HD

2.5" SATA HDD Connector
SATA ODD Connector

page 28

OR

page 21

1.8" SATA HDD Connector

page 21

TPA6043

AMP & Audio Jack

page 29

RTC CKT.

page 21

TPM1.2

SLB9635TT

page 32

SMSC KBC 1091

page 33

Power OK CKT.

page 35

4 4

Power On/Off CKT.

page 30

Touch Pad CONN.

TrackPoint CONN.

page 30

DC/DC Int erface CKT.

page 36

A

B

Int.KBD

page 30page 30

Security Classification

Issued Date

THIS SHEET OF EN GINEE RING D RAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR DISCLO SED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2006/02/13 2006/03/10

Compal Secret Data

Deciphered Date

D

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

Block Diagram

LA-4021P

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Voltage Rails

State

S0

S1

S3

S5 S4/AC

S5 S4/ Battery only

S5 S4/AC & Battery
don't exist

1 1

( O MEANS ON X MEANS OFF )

+B

power
plane

O
O
O
O
O

X

+5VALW
+3VALW
+3VM
+1.05VM

O
O
O
O

X

+1.8V

+5VS
+3VS
+1.5VS
+0.9V
+VCCP
+CPU_CORE
+0.9V

OO
OO

O

X
XX
X

X

XX X

SMBUS Control Table

SOURCE

SMB_EC_CK1
SMB_EC_DA1

SMB_EC_CK2
SMB_EC_DA2

SMB_CK_CLK1
SMB_CK_DAT1 ICH9

LCD_CLK
LCD_DAT

KB926

KB926

Cantiga

Symbol Note :

: means Digital Ground

: means Analog Ground

@ : means just reserve , no build
CONN@ : means ME part.
45@ : means install after SMT.

INVERTER BATT EEPROM

X
X

X
XX

SERIAL

VV

XX
X

X
XX

THERMAL
SENSOR
(CPU)

SODIMM CLK CHIP

XX

V

X

X

VVV

XX

X
X

MINI CARD

LCD

XX
X

X
X

X

V

I2C / SMBUS ADDRESSING

DEVICE

DDR SO-DIMM 0
CLOCK GENERATOR (EXT.)

HEX ADDRESS

A0
D2

1 0 1 0 0 0 0 0
1 1 0 1 0 0 1 0

Security Classification

Issued Date

THIS SHEET OF EN GINEE RING D RAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR DISCLO SED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

2005/03/10 2006/03/10

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

Notes List

LA-4021P

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D D

H_A#[3..16]8

H_ADSTB#08

H_A#[17..35]8

C C

H_ADSTB#18

H_FERR#21

B B

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16

H_REQ#08
H_REQ#18
H_REQ#28
H_REQ#38
H_REQ#48

H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35

H_A20M#21
H_IGNNE#21
H_STPCLK#21

H_INTR21

H_NMI21
H_SMI#21

T97PAD
T98PAD

T99PAD
T100PAD
T101PAD
T102PAD
T103PAD

U1A

P2

A[3]#

V4

A[4]#

W1

A[5]#

T4

A[6]#

AA1

A[7]#

AB4

A[8]#

T2

A[9]#

AC5

A[10]#

AD2

A[11]#

AD4

A[12]#

AA5

A[13]#

AE5

A[14]#

AB2

A[15]#

AC1

A[16]#

Y4

ADSTB[0]#

R1

REQ[0]#

R5

REQ[1]#

U1

REQ[2]#

P4

REQ[3]#

W5

REQ[4]#

AN1

A[17]#

AK4

A[18]#

AG1

A[19]#

AT4

A[20]#

AK2

A[21]#

AT2

A[22]#

AH2

A[23]#

AF4

A[24]#

AJ5

A[25]#

AH4

A[26]#

AM4

A[27]#

AP4

A[28]#

AR5

A[29]#

AJ1

A[30]#

AL1

A[31]#

AM2

A[32]#

AU5

A[33]#

AP2

A[34]#

AR1

A[35]#

AN5

ADSTB[1]#

C7

A20M#

ICH

D4

FERR#

F10

IGNNE#

F8

STPCLK#

C9

LINT0

C5

LINT1

E5

SMI#

V2

RSVD01

Y2

RSVD02

AG5

RSVD03

AL5

RSVD04

J9

RSVD05

F4

RSVD06

H8

RSVD07

PENRYN SFF_UFCBGA956

ADS#
BNR#
BPRI#

ADDR GROUP 0

DEFER#

DRDY#
DBSY#

BR0#

IERR#

INIT#

CONTROL

LOCK#

RESET#

RS[0]#
RS[1]#
RS[2]#

TRDY#

HITM#

ADDR GROUP 1

BPM[0]#
BPM[1]#
BPM[2]#
BPM[3]#

PRDY#
PREQ#

TRST#

DBR#

XDP/ITP SIGNALS

THERMAL

PROCHOT#

THERMDA
THERMDC

THERMTRIP#

H CLK

BCLK[0]
BCLK[1]

HIT#

TDO
TMS

TCK

M4
J5
L5

N5
F38
J1

M2
B40

D8
N1
G5

K2
H4
K4
L1

H2
F2

AY8
BA7
BA5
AY2
AV10
AV2
AV4
AW7

TDI

AU1
AW5
AV8
J7

D38
BB34
BD34

B10

A35
C35

RESERVED

4

Place close to U1.

H_ADS# 8
H_BNR# 8

H_BPRI# 8
H_DEFER# 8

H_DRDY# 8
H_DBSY# 8

H_BR0# 8

H_INIT# 21
H_LOCK# 8

H_RESET#

H_TRDY# 8

H_HIT# 8
H_HITM# 8

XDP_BPM#0
XDP_BPM#1
XDP_BPM#2
XDP_BPM#3
XDP_BPM#4
XDP_BPM#5_R
XDP_TCK
XDP_TDI
XDP_TDO
XDP_TMS
XDP_TRST#
XDP_DBRESET#

Place Close to U1.

H_THERMDA_R
H_THERMDC_R

H_THERMTRIP# 8,21

H_THERMDA, H_THERMDC routing together,
Trace width / Spacing = 10 / 10 mil

CLK_CPU_BCLK 16
CLK_CPU_BCLK# 16

+VCCP

1 2

1 2

56_0402_5%

R10

H_RS#0 8
H_RS#1 8
H_RS#2 8

Add 0 ohm per EMI request.
10/17

R48
0_0402_5%

1 2

XDP_DBRESET# 22

H_PROCHOT# 42

R20 68_0402_5%

1 2

R21 0_0402_5%

1 2

R22 0_0402_5%

1 2

R609
51_0402_1%

9/20

XDP_BPM#5

+VCCP

H_THERMDA
H_THERMDC

H_RESET# 8

9/14

3

JP1

11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59

U2

1

DN

2

DP

3

VDD

4

GPIO1

5

GPIO2

6

ALERT#

7

SYS_SHDN#

8

SMDATA

1
3
5
7
9

XDP_BPM#5
XDP_BPM#4

XDP_BPM#3
XDP_BPM#2

XDP_BPM#1
XDP_BPM#0

R9
1K_0402_5%

H_PWRGOOD_R

12

1 2

C3 2200P_0402_50V7K

+3VS

1 2

R23 10K_0402_5%@

1 2

R324 0_0402_5%@

12

XDP_HOOK1

XDP_TCK

Update to right package for U2. 10/01

H_THERMDA
H_THERMDC

R24
10K_0402_5%

1 2

H_PWRGOOD5,21 CLK_CPU_XDP 16

C1 0.1U_0402_16V4Z

Thermal Sensor EMC2103-2 with CPU PWM FAN

+3VS

R15
68_0402_5%

1 2

+3VS_THER

C2

1

0.1U_0402_16V4Z

2

THERM_SCI#22

+3VS

ICH_SM_DA22,26

MAINPWON37,39

2

XDP Connector

GND0
OBSFN_A0
OBSFN_A1
GND2
OBSDATA_A0
OBSDATA_A1
GND4
OBSDATA_A2
OBSDATA_A3
GND6
OBSFN_B0
OBSFN_B1
GND8
OBSDATA_B0
OBSDATA_B1
GND10
OBSDATA_B2
OBSDATA_B3
GND12
PWRGOOD/HOOK0
HOOK1
VCC_OBS_AB
HOOK2
HOOK3
GND14
SDA
SCL
TCK1
TCK0
GND16

GND

EMC2103-2-AX_QFN16_4X4

17

SAMTE_BSH-030-01-L-D-Aconn@

DP2/DN3
DN2/DP3

TRIP_SET

SHDN_SEL

GND

PWM

TACH

SMCLK

OBSFN_C0
OBSFN_C1

OBSDATA_C0
OBSDATA_C1

OBSDATA_C2
OBSDATA_C3

OBSFN_D0
OBSFN_D1

OBSDATA_D0
OBSDATA_D1

OBSDATA_D2
OBSDATA_D3

ITPCLK/HOOK4

ITPCLK#/HOOK5

VCC_OBS_CD

RESET#/HOOK6

DBR#/HOOK7

16
15
14
13
12
11
10
9

2

GND1

4
6
8

GND3

10
12
14

GND5

16
18
20

GND7

22
24
26

GND9

28
30
32

GND11

34
36
38

GND13

40
42
44

H_RESET#_R

46
48
50

GND15

TD0

TRST#

TDI

TMS

GND17

REMOTE2+

REMOTE2-

R18 10K_0402_5%
R17 10K_0402_5%

FAN_PWM

TACH

52
54
56
58
60

1 2
1 2

R13 10K_0402_5%

R16 10K_0402_5%

XDP_TDO
XDP_TRST#
XDP_TDI
XDP_TMS
XDP_PRE

1 2

1 2

XDP_DBRESET#_R

XDP_TDI
XDP_TMS
XDP_TDO
XDP_BPM#5
XDP_HOOK1
XDP_TRST#
XDP_TCK

1 2

ICH_SM_CLK 22,26

Change R23, R24 connect to +3VS and add PU/PD for U2. (9/3)
NI R23, reserve R324 and connect to MAINPWON. (10/5)

REMOTE thermal sensor

REMOTE2+

C314

2200P_0402_50V7K

REMOTE2-

C

Q45

2

B

MMBT3904W_SOT323-3

E

3 1

2

1

Layout Note:
place near the hottest spot area for

NB & top SODIMM.

1

R1 1K_0402_5%@

1 2

R2 54.9_0402_1%

1 2

R3 54.9_0402_1%

1 2

R4 54.9_0402_1%

1 2

R5 54.9_0402_1%

1 2

R6 54.9_0402_1%@

1 2

R7 51_0402_1%

1 2

R8 54.9_0402_1%

1 2

This shall place near CPU

CLK_CPU_XDP# 16

+VCCP+VCCP

R11 22.6_0402_1%

1 2

R12 200_0402_1%

R14
0_0402_5%

Place R191 within 200ps
(~1") to CPU

+5VS

+3VS

+3VS

12

JP2

1

1

2

2

3

3

ACES_85204-03001conn@

DEL U3 and add R13. (9/3)

G1
G2

+3VS

+VCCP

H_RESET#
XDP_DBRESET#XDP_DBRESET#_R

4
5

A A

5

4

Security Classification

Issued Date

THIS SHEET OF EN GINEE RING D RAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR DISCLO SED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/02/13 2006/03/10

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

Compal Electronics, Inc.

Penryn(1/3)-AGTL+/ITP-XDP

LA-4021P

1

0.1

of

445Monday, October 29, 2007

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4

3

2

1

H_D#[0..15]8

D D

H_DSTBN#08
H_DSTBP#08
H_DINV#08
H_D#[16..31]8

C C

layout note: Route TEST3 & TEST5 traces on
ground referenced layer to the TPs

H_DSTBN#18
H_DSTBP#18
H_DINV#18

CPU_BSEL016
CPU_BSEL116
CPU_BSEL216

V_CPU_GTLREF

T104
T105
T2
T106
T3
T4

H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_DSTBN#0
H_DSTBP#0
H_DINV#0

H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_DSTBN#1
H_DSTBP#1
H_DINV#1

TEST1
TEST2
TEST3
TEST4
TEST5
TEST6

CPU_BSEL CPU_BSEL2 CPU_BSEL1

B B

166

200

01

0

1

U1B

F40

D[0]#

G43

D[1]#

E43

D[2]#

J43

D[3]#

H40

D[4]#

H44

D[5]#

G39

D[6]#

E41

D[7]#

L41

D[8]#

K44

D[9]#

N41

D[10]#

T40

D[11]#

M40

D[12]#

G41

D[13]#

M44

D[14]#

L43

D[15]#

K40

DSTBN[0]#

J41

DSTBP[0]#

P40

DINV[0]#

P44

D[16]#

V40

D[17]#

V44

D[18]#

AB44

D[19]#

R41

D[20]#

W41

D[21]#

N43

D[22]#

U41

D[23]#

AA41

D[24]#

AB40

D[25]#

AD40

D[26]#

AC41

D[27]#

AA43

D[28]#

Y40

D[29]#

Y44

D[30]#

T44

D[31]#

U43

DSTBN[1]#

W43

DSTBP[1]#

R43

DINV[1]#

AW43

GTLREF

E37

TEST1

D40

TEST2

C43

TEST3

AE41

TEST4

AY10

TEST5

AC43

TEST6

A37

BSEL[0]

C37

BSEL[1]

B38

BSEL[2]

PENRYN SFF_UFCBGA956

CPU_BSEL0

1

0

D[32]#
D[33]#
D[34]#

DATA GROUP 0

D[35]#
D[36]#
D[37]#
D[38]#
D[39]#
D[40]#
D[41]#
D[42]#
D[43]#
D[44]#

DATA GROUP 2DATA GROUP 3

D[45]#
D[46]#

D[47]#
DSTBN[2]#
DSTBP[2]#

DINV[2]#

D[48]#

D[49]#

D[50]#

D[51]#

DATA GROUP 1

D[52]#

D[53]#

D[54]#

D[55]#

D[56]#

D[57]#

D[58]#

D[59]#

D[60]#

D[61]#

D[62]#

D[63]#
DSTBN[3]#
DSTBP[3]#

DINV[3]#
COMP[0]

MISC

COMP[1]
COMP[2]
COMP[3]

DPRSTP#

DPSLP#

DPWR#

PWRGOOD

SLP#

PSI#

Cause CPU core power change to
1 phase, and not need support
the pin, leave it as TP. 10/02

AR43
AH40
AF40
AJ43
AG41
AF44
AH44
AM44
AN43
AM40
AK40
AG43
AP40
AN41
AL41
AK44
AL43
AJ41

AV38
AT44
AV40
AU41
AW41
AR41
BA37
BB38
AY36
AT40
BC35
BC39
BA41
BB40
BA35
AU43
AY40
AY38
BC37

AE43
AD44
AE1
AF2

G7
B8
C41
E7
D10
BD10

H_PSI#

H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_DSTBN#2
H_DSTBP#2
H_DINV#2

H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
H_DSTBN#3
H_DSTBP#3
H_DINV#3

COMP0
COMP1
COMP2
COMP3

H_D#32

AP44

H_DPRSTP# 8,21,42

H_DPSLP# 21
H_DPWR# 8
H_PWRGOOD 4,21

H_CPUSLP# 8

T124

H_D#[32..47] 8

H_DSTBN#2 8
H_DSTBP#2 8
H_DINV#2 8
H_D#[48..63] 8

H_DSTBN#3 8
H_DSTBP#3 8
H_DINV#3 8

R33

R34

R31

R32

12

12

12

12

54.9_0402_1%

27.4_0402_1%

54.9_0402_1%

27.4_0402_1%

Resistor placed within

0.5" of CPU pin.Trace
should be at least 25
mils away from any other
toggling signal.
COMP[0,2] trace width is
18 mils. COMP[1,3] trace
width is 4 mils.

266000

+VCC_CORE +VCC_CORE

U1C

F32

VCC[001]

G33

VCC[002]

H32

VCC[003]

J33

VCC[004]

K32

VCC[005]

L33

VCC[006]

M32

VCC[007]

N33

VCC[008]

P32

VCC[009]

R33

VCC[010]

T32

VCC[011]

U33

VCC[012]

V32

VCC[013]

W33

VCC[014]

Y32

VCC[015]

AA33

VCC[016]

AB32

VCC[017]

AC33

VCC[018]

AD32

VCC[019]

AE33

VCC[020]

AF32

VCC[021]

AG33

VCC[022]

AH32

VCC[023]

AJ33

VCC[024]

AK32

VCC[025]

AL33

VCC[026]

AM32

VCC[027]

AN33

VCC[028]

AP32

VCC[029]

AR33

VCC[030]

AT34

VCC[031]

AT32

VCC[032]

AU33

VCC[033]

AV32

VCC[034]

AY32

VCC[035]

BB32

VCC[036]

BD32

VCC[037]

B28

VCC[038]

B30

VCC[039]

B26

VCC[040]

D28

VCC[041]

D30

VCC[042]

F30

VCC[043]

F28

VCC[044]

H30

VCC[045]

H28

VCC[046]

D26

VCC[047]

F26

VCC[048]

H26

VCC[049]

K30

VCC[050]

K28

VCC[051]

M30

VCC[052]

M28

VCC[053]

K26

VCC[054]

M26

VCC[055]

P30

VCC[056]

P28

VCC[057]

T30

VCC[058]

T28

VCC[059]

V30

VCC[060]

V28

VCC[061]

P26

VCC[062]

T26

VCC[063]

V26

VCC[064]

Y30

VCC[065]

Y28

VCC[066]

AB30

VCC[067]

PENRYN SFF_UFCBGA956

VCC[068]
VCC[069]
VCC[070]
VCC[071]
VCC[072]
VCC[073]
VCC[074]
VCC[075]
VCC[076]
VCC[077]
VCC[078]
VCC[079]
VCC[080]
VCC[081]
VCC[082]
VCC[083]
VCC[084]
VCC[085]
VCC[086]
VCC[087]
VCC[088]
VCC[089]
VCC[090]
VCC[091]
VCC[092]
VCC[093]
VCC[094]
VCC[095]
VCC[096]
VCC[097]
VCC[098]
VCC[099]
VCC[100]

VCCP_001
VCCP_002
VCCP_003
VCCP_004
VCCP_005
VCCP_006
VCCP_007
VCCP_008
VCCP_009
VCCP_010
VCCP_011
VCCP_012
VCCP_013
VCCP_014
VCCP_015
VCCP_016

VCCA[01]
VCCA[02]

VID[0]
VID[1]
VID[2]
VID[3]
VID[4]
VID[5]
VID[6]

VCCSENSE

VSSSENSE

AB28
AD30
AD28
Y26
AB26
AD26
AF30
AF28
AH30
AH28
AF26
AH26
AK30
AK28
AM30
AM28
AP30
AP28
AK26
AM26
AP26
AT30
AT28
AV30
AV28
AY30
AY28
AT26
AV26
AY26
BB30
BB28
BD30

R26 0_0402_5%

J11

1 2

R27 0_0402_5%

E11

1 2

R28 0_0402_5%

G11

1 2
J37
K38
L37
N37
P38
R37
U37
V38
W37
AA37
AB38
AC37
AE37

B34
D34

BD8
BC7
BB10
BB8
BC5
BB4
AY4

VCCSENSE

BD12

VSSSENSE

BC13

Length match within 25 mils.
The trace width/space/other is
20/7/25.

+VCCP

1

+

2

CPU_VID0 42
CPU_VID1 42
CPU_VID2 42
CPU_VID3 42
CPU_VID4 42
CPU_VID5 42
CPU_VID6 42

VCCSENSE 42

VSSSENSE 42

C4
330U_D2E_2.5VM_R7

1

C6

2

0.01U_0402_16V7K

Near pin B34

+1.5VS

1

C7

2

10U_0805_6.3V6M

Near pin D34

+VCC_CORE

R36

+VCCP

12

V_CPU_GTLREF

A A

Close to CPU pin AW43
within 500mils.

5

R35
1K_0402_1%

12

R37
2K_0402_1%

4

Security Classification

Issued Date

THIS SHEET OF EN GINEE RING D RAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR DISCLO SED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/02/13 2006/03/10

Compal Secret Data

Deciphered Date

2

1 2

100_0402_1%
R38

1 2

100_0402_1%

Close to CPU pin
within 500mils.

Title

Size Document Number Rev

Custom

Date: Sheet

VCCSENSE

VSSSENSE

Compal Electronics, Inc.

Penryn(2/3)-AGTL+/ITP-XDP

LA-4021P

1

0.1

of

545Monday, October 29, 2007

电 脑 维 修 网

http://www.dnfix.cn/bbs

伟 力 电 脑 医 院

技术支持：252670528

5

D D

AL37

AN37

AP38

B32

C33

D32

E35

E33

F34

G35

F36

H36

J35

L35

N35

K36

R35

U35

P36

V36

W35

AA35

AC35

AB36

AE35

AG35

VCCP_040

VCCP_041

VCC_120

VCC_121

V22

VCCP_042

VCC_122

Y24

VCCP_043

VCC_123

Y22

AB24

VCCP_044

VCCP_045

VCC_124

VCC_125

AB22

AJ35

VCCP_046

VCC_126

AD24

AD22

C C

VCCP_021

VCCP_022

VCCP_023

VCCP_024

VCCP_025

VCCP_026

VCCP_027

VCCP_028

VCCP_029

VCCP_030

VCCP_031

VCCP_032

VCCP_033

VCCP_034

VCCP_035

VCCP_036

VCCP_037

VCCP_038

VCCP_039

VCC_101

VCC_102

VCC_103

VCC_104

VCC_105

VCC_106

VCC_107

VCC_108

VCC_109

VCC_110

VCC_111

VCC_112

VCC_113

VCC_114

VCC_115

VCC_116

VCC_117

VCC_118

VCC_119

F24

F22

B22

B24

D22

D24

H24

BB26

BD28

BD26

H22

T24

K24

T22

K22

P24

P22

V24

M24

M22

AF36

VCCP_047

VCCP_048

VCC_127

VCC_128

AF24

AL35

AN35

VCCP_049

VCC_129

AF22

AH24

AK36

VCCP_050

VCCP_051

VCC_130

VCC_131

AH22

AP36

B12

VCCP_052

VCC_132

AK24

AK22

4

B14

C13

VCCP_053

VCCP_054

VCC_133

VCC_134

AM24

AM22

D12

VCCP_055

VCCP_056

VCC_135

VCC_136

AP24

D14

E13

VCCP_057

VCC_137

AT24

AP22

F14

VCCP_058

VCCP_059

VCC_138

VCC_139

AT22

F12

G13

VCCP_060

VCC_140

AV24

AV22

H14

VCCP_061

VCCP_062

VCC_141

VCC_142

AY24

H12

J13

VCCP_063

VCC_143

AY22

BB24

K14

K12

VCCP_064

VCCP_065

VCC_144

VCC_145

BB22

BD24

L13

VCCP_066

VCCP_067

VCC_146

VCC_147

BD22

L11

M14

VCCP_068

VCC_148

B16

B18

N13

VCCP_069

VCCP_070

VCC_149

VCC_150

B20

N11

K10

VCCP_071

VCC_151

D16

D18

P14

VCCP_072

VCCP_073

VCC_152

VCC_153

F18

P12

R13

VCCP_074

VCC_154

F16

H18

R11

VCCP_075

VCCP_076

VCC_155

VCC_156

H16

T14

U13

VCCP_077

VCC_157

F20

D20

U11

VCCP_078

VCCP_079

VCC_158

VCC_159

H20

V14

V12

VCCP_080

VCC_160

K18

K16

W13

W11

VCCP_081

VCCP_082

VCC_161

VCC_162

M18

M16

P10

VCCP_083

VCCP_084

VCC_163

VCC_164

K20

V10

Y14

VCCP_085

VCC_165

P18

M20

AA13

VCCP_086

VCCP_087

VCC_166

VCC_167

P16

3

AA11

AB14

VCCP_088

VCC_168

T18

T16

AB12

VCCP_089

VCCP_090

VCC_169

VCC_170

V18

AC13

AC11

VCCP_091

VCC_171

V16

P20

AD14

VCCP_092

VCCP_093

VCC_172

VCC_173

T20

AB10

AE13

VCCP_094

VCC_174

V20

Y18

AE11

VCCP_095

VCCP_096

VCC_175

VCC_176

Y16

AF14

AF12

VCCP_097

VCC_177

AB18

AB16

AG13

VCCP_098

VCCP_099

VCC_178

VCC_179

AD18

AG11

AH14

VCCP_100

VCC_180

Y20

AD16

AJ13

VCCP_101

VCCP_102

VCC_181

VCC_182

AB20

AJ11

AF10

VCCP_103

VCC_183

AF18

AD20

AK14

AK12

VCCP_104

VCCP_105

VCC_184

VCC_185

AF16

AH18

AL13

VCCP_106

VCCP_107

VCC_186

VCC_187

AH16

AL11

AN13

VCCP_108

VCC_188

AF20

AH20

AN11

VCCP_109

VCCP_110

VCC_189

VCC_190

AK18

AP12

AR13

VCCP_111

VCC_191

AK16

AM18

AR11

VCCP_112

VCCP_113

VCC_192

VCC_193

AM16

AK10

AP10

VCCP_114

VCC_194

AP18

AP16

AU13

VCCP_115

VCCP_116

VCC_195

VCC_196

AK20

2

AU11

VCCP_117

VCCP_118L9VCCP_119L7VCCP_120N9VCCP_121N7VCCP_122R9VCCP_123R7VCCP_124U9VCCP_125U7VCCP_126W9VCCP_127W7VCCP_128

VCC_197

VCC_198

VCC_199

VCC_200

VCC_201

VCC_202

VCC_203

VCC_204

VCC_205

AT18

AT16

AP20

AM20

AT20

AV18

AV16

AY18

AY16

VCC_206

VCC_207

AV20

AY20

AA9

AA7

VCC_208

BB18

BB16

AC9

VCCP_129

VCCP_130

VCC_209

VCC_210

BD18

AC7

AE9

VCCP_131

VCC_211

BB20

BD16

AE7

VCCP_132

VCCP_133

VCC_212

VCC_213

BD20

AG9

AG7

VCCP_134

VCC_214

AP14

AM14

AJ9

VCCP_135

VCCP_136

VCC_215

VCC_216

AT14

AJ7

AL9

VCCP_137

VCC_217

AV14

AY14

AL7

VCCP_138

VCCP_139

VCC_218

VCC_219

BB14

AN9

AN7

VCCP_140

VCC_220

BD14

VCCP_141

+VCCP

AR9

AR7

A33

A13

VCCP_142

VCCP_143

VCCP_144

VCCP_018

VCCP_019

VCCP_017

AJ37

AF38

AK38

AG37

U1F
PENRYN SFF_UFCBGA956

VCCP_145

VCCP_020

1

+VCC_CORE +VCCP

B B

A A

5

4

Security Classification

Issued Date

THIS SHEET OF EN GINEE RING D RAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR DISCLO SED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/02/13 2006/03/10

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet of

Compal Electronics, Inc.

Penryn(3/3)-Power

LA-4021P

1

645Monday, October 29, 2007

0.1

电 脑 维 修 网

http://www.dnfix.cn/bbs

伟 力 电 脑 医 院

技术支持：252670528

5

4

3

2

1

U1D

B42

VSS[001]

F44

VSS[002]

D44

VSS[003]

D42

VSS[004]

F42

VSS[005]

H42

VSS[006]

K42

VSS[007]

M42

VSS[008]

P42

VSS[009]

T42

VSS[010]

V42

VSS[011]

Y42

D D

C C

B B

VSS[012]

AB42

VSS[013]

AD42

VSS[014]

AF42

VSS[015]

AH42

VSS[016]

AK42

VSS[017]

AM42

VSS[018]

AP42

VSS[019]

AY44

VSS[020]

AV44

VSS[021]

AT42

VSS[022]

AV42

VSS[023]

AY42

VSS[024]

BA43

VSS[025]

BB42

VSS[026]

C39

VSS[027]

E39

VSS[028]

G37

VSS[029]

H38

VSS[030]

J39

VSS[031]

L39

VSS[032]

M38

VSS[033]

N39

VSS[034]

R39

VSS[035]

T38

VSS[036]

U39

VSS[037]

W39

VSS[038]

Y38

VSS[039]

AA39

VSS[040]

AC39

VSS[041]

AD38

VSS[042]

AE39

VSS[043]

AG39

VSS[044]

AH38

VSS[045]

AJ39

VSS[046]

AL39

VSS[047]

AM38

VSS[048]

AN39

VSS[049]

AR39

VSS[050]

AR37

VSS[051]

AT38

VSS[052]

AU39

VSS[053]

AU37

VSS[054]

AW39

VSS[055]

AW37

VSS[056]

BA39

VSS[057]

BC41

VSS[058]

BD40

VSS[059]

BD38

VSS[060]

B36

VSS[061]

H34

VSS[062]

D36

VSS[063]

K34

VSS[064]

M34

VSS[065]

M36

VSS[066]

P34

VSS[067]

T34

VSS[068]

V34

VSS[069]

T36

VSS[070]

Y34

VSS[071]

AB34

VSS[072]

AD34

VSS[073]

Y36

VSS[074]

AD36

VSS[075]

AF34

VSS[076]

AH34

VSS[077]

AH36

VSS[078]

AK34

VSS[079]

AM34

VSS[080]

AP34

VSS[081]

PENRYN SFF_UFCBGA956

VSS[082]
VSS[083]
VSS[084]
VSS[085]
VSS[086]
VSS[087]
VSS[088]
VSS[089]
VSS[090]
VSS[091]
VSS[092]
VSS[093]
VSS[094]
VSS[095]
VSS[096]
VSS[097]
VSS[098]
VSS[099]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
VSS[159]
VSS[160]
VSS[161]
VSS[162]
VSS[163]

AM36
AR35
AU35
AV34
AW35
AW33
AY34
AT36
AV36
BA33
BC33
BB36
BD36
C27
C29
C31
E29
E27
G29
G27
E31
G31
J29
J27
L29
L27
N29
N27
J31
L31
N31
R29
R27
U29
U27
R31
U31
W29
W27
W31
AA29
AA27
AC29
AC27
AA31
AC31
AE29
AE27
AG29
AG27
AJ29
AJ27
AE31
AG31
AJ31
AL29
AL27
AN29
AN27
AL31
AN31
AR29
AR27
AR31
AU29
AU27
AW29
AW27
AU31
AW31
BA29
BA27
BC29
BC27
BA31
BC31
C21
C23
C25
E25
E23
E21

A A

5

U1E

G25

VSS_164

G23

VSS_165

G21

VSS_166

J25

VSS_167

J23

VSS_168

J21

VSS_169

L25

VSS_170

L23

VSS_171

L21

VSS_172

N25

VSS_173

N23

VSS_174

N21

VSS_175

R25

VSS_176

R23

VSS_177

R21

VSS_178

U25

VSS_179

U23

VSS_180

U21

VSS_181

W25

VSS_182

W23

VSS_183

W21

VSS_184

AA25

VSS_185

AA23

VSS_186

AA21

VSS_187

AC25

VSS_188

AC23

VSS_189

AC21

VSS_190

AE25

VSS_191

AE23

VSS_192

AE21

VSS_193

AG25

VSS_194

AG23

VSS_195

AG21

VSS_196

AJ25

VSS_197

AJ23

VSS_198

AJ21

VSS_199

AL25

VSS_200

AL23

VSS_201

AL21

VSS_202

AN25

VSS_203

AN23

VSS_204

AN21

VSS_205

AR25

VSS_206

AR23

VSS_207

AR21

VSS_208

AU25

VSS_209

AU23

VSS_210

AU21

VSS_211

AW25

VSS_212

AW23

VSS_213

AW21

VSS_214

BA25

VSS_215

BA23

VSS_216

BA21

VSS_217

BC25

VSS_218

BC23

VSS_219

BC21

VSS_220

C17

VSS_221

C19

VSS_222

E19

VSS_223

E17

VSS_224

G19

VSS_225

G17

VSS_226

J19

VSS_227

J17

VSS_228

L19

VSS_229

L17

VSS_230

N19

VSS_231

N17

VSS_232

R19

VSS_233

R17

VSS_234

U19

VSS_235

U17

VSS_236

W19

VSS_237

W17

VSS_238

AA19

VSS_239

AA17

VSS_240

AC19

VSS_241

AC17

VSS_242

AE19

VSS_243

AE17

VSS_244

AG19

VSS_245

AG17

VSS_246

AJ19

VSS_247

AJ17

VSS_248

AL19

VSS_249

AL17

VSS_250

AN19

VSS_251

AN17

VSS_252

AR19

VSS_253

AR17

VSS_254

AU19

VSS_255

AU17

VSS_256

AW19

VSS_257

AW17

VSS_258

BA19

VSS_259

BA17

VSS_260

BC19

VSS_261

BC17

VSS_262

C11

VSS_263

C15

VSS_264

E15

VSS_265

G15

VSS_266

H10

VSS_267

M12

VSS_268

J15

VSS_269

L15

VSS_270

N15

VSS_271

M10

VSS_272

T12

VSS_273

R15

VSS_274

U15

VSS_275

W15

VSS_276

T10

VSS_277

Y12

VSS_278

AD12

VSS_279

PENRYN SFF_UFCBGA956

VSS_280
VSS_281
VSS_282
VSS_283
VSS_284
VSS_285
VSS_286
VSS_287
VSS_288
VSS_289
VSS_290
VSS_291
VSS_292
VSS_293
VSS_294
VSS_295
VSS_296
VSS_297
VSS_298
VSS_299
VSS_300
VSS_301
VSS_302
VSS_303
VSS_304
VSS_305
VSS_306
VSS_307
VSS_308
VSS_309
VSS_310
VSS_311
VSS_312
VSS_313
VSS_314
VSS_315
VSS_316
VSS_317
VSS_318
VSS_319
VSS_320
VSS_321
VSS_322
VSS_323
VSS_324
VSS_325
VSS_326
VSS_327
VSS_328
VSS_329
VSS_330
VSS_331
VSS_332
VSS_333
VSS_334
VSS_335
VSS_336
VSS_337
VSS_338
VSS_339
VSS_340
VSS_341
VSS_342
VSS_343
VSS_344
VSS_345
VSS_346
VSS_347
VSS_348
VSS_349
VSS_350
VSS_351
VSS_352
VSS_353
VSS_354
VSS_355
VSS_356
VSS_357
VSS_358
VSS_359
VSS_360
VSS_361
VSS_362
VSS_363
VSS_364
VSS_365
VSS_366
VSS_367
VSS_368
VSS_369
VSS_370
VSS_371
VSS_372
VSS_373
VSS_374
VSS_375
VSS_376
VSS_377
VSS_378
VSS_379
VSS_380
VSS_381
VSS_382
VSS_383
VSS_384
VSS_385
VSS_386
VSS_387
VSS_388
VSS_389
VSS_390
VSS_391
VSS_392
VSS_393
VSS_394
VSS_395

AA15
AC15
Y10
AD10
AH12
AE15
AG15
AJ15
AH10
AM12
AL15
AN15
AR15
AM10
AT12
AV12
AW13
AW11
AY12
AU15
AW15
AT10
BA13
BA11
BB12
BC11
BA15
BC15
B6
D6
E9
F6
G9
H6
K8
K6
M8
M6
P8
P6
T8
T6
V8
V6
U5
Y8
Y6
AB8
AB6
AD8
AD6
AF8
AF6
AH8
AH6
AK8
AK6
AM8
AM6
AP8
AP6
AT8
AT6
AU9
AV6
AU7
AW9
AY6
BA9
BB6
BC9
BD6
B4
C3
E3
G3
J3
L3
N3
R3
U3
W3
AA3
AC3
AE3
AG3
AJ3
AL3
AN3
AR3
AU3
AW3
BA3
BC3
D2
E1
G1
AW1
BA1
BB2
A41
A39
A29
A27
A31
A25
A23
A21
A19
A17
A11
A15
A7
A5
A9
BD4

+VCC_CORE

Place these capacitors on L8
(North side,Secondary Layer)

Place these capacitors on L8
(North side,Secondary Layer)

Place these capacitors on L8
(Sorth side,Secondary Layer)

Place these capacitors on L8
(Sorth side,Secondary Layer)

1

2

+VCC_CORE

1

2

+VCC_CORE

1

2

+VCC_CORE

1

2

C8
10U_0805_6.3V6M

C16
10U_0805_6.3V6M

C21
10U_0805_6.3V6M

C29
10U_0805_6.3V6M

1

C9
10U_0805_6.3V6M

2

1

C17
10U_0805_6.3V6M

2

1

C22
10U_0805_6.3V6M

2

1

C30
10U_0805_6.3V6M

2

1

C10
10U_0805_6.3V6M

2

1

C18
10U_0805_6.3V6M

2

1

C23
10U_0805_6.3V6M

2

1

C31
10U_0805_6.3V6M

2

1

C11
10U_0805_6.3V6M

2

1

C19
10U_0805_6.3V6M

2

1

C24
10U_0805_6.3V6M

2

1

C32
10U_0805_6.3V6M

2

1

C12
10U_0805_6.3V6M

2

1

C20
10U_0805_6.3V6M

2

1

C25
10U_0805_6.3V6M

2

1

C33
10U_0805_6.3V6M

2

1

2

1

C26
10U_0805_6.3V6M

2

Mid Frequence Decoupling

Near CPU CORE regulator

+VCC_CORE

220U_D2_2VK_R9

1

1

+

C34

C35

2

2

+VCCP

1U_0603_10V4Z

C38

Security Classification

Issued Date

THIS SHEET OF EN GINEE RING D RAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

4

MAY BE USED B Y OR DISCLO SED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

1U_0603_10V4Z

1U_0603_10V4Z

1

1

2

C40

C39

2

2006/02/13 2006/03/10

1U_0603_10V4Z

1

1

C41

2

2

Compal Secret Data

1U_0603_10V4Z

1

C42

2

1U_0603_10V4Z

1U_0603_10V4Z

1

C43

2

Deciphered Date

1

C552

2

ESR <= 1.5m ohm

220U_D2_2VK_R9

+

1U_0603_10V4Z

220U_D2_2VK_R9

1

+

C36

2

1U_0603_10V4Z

1U_0603_10V4Z

1

1

C553

C554

2

2

2

220U_D2_2VK_R9

1

+

C37

2

1U_0603_10V4Z

1U_0603_10V4Z

1

1

C555

2

1

C556

C557

2

2

Title

Size Document Number Rev

Custom

Date: Sheet

C13
10U_0805_6.3V6M

1

C14
10U_0805_6.3V6M

2

1

C27
10U_0805_6.3V6M

2

Compal Electronics, Inc.

Penryn(3/3)-GND/Bypass

LA-4021P

1

1

C15
10U_0805_6.3V6M

2

1

C28
10U_0805_6.3V6M

2

of

745Monday, October 29, 2007

0.1

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5

H_D#[0..63]5

D D

C C

H_RESET#4

H_CPUSLP#5

B B

layout note:
Route H_SCOMP and H_SCOMP# with trace width,

spacing and impedance (55 ohm) same as FSB data
traces

Layout Note:
H_RCOMP / H_VREF / H_SWNG

trace width and spacing is 10/20

+VCCP

12

R53

1K_0402_1%

12

A A

R592K_0402_1%

within 100 mils from NB

Trace < = 500mils

H_VREF

1

C51

2

0.1U_0402_16V4Z

@

H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63

H_SWNG
H_RCOMP

H_VREF

H_RCOMP

12

R60

24.9_0402_1%

5

U4A

J7

H_D#_0

H6

H_D#_1

L11

H_D#_2

J3

H_D#_3

H4

H_D#_4

G3

H_D#_5

K10

H_D#_6

K12

H_D#_7

L1

H_D#_8

M10

H_D#_9

M6

H_D#_10

N11

H_D#_11

L7

H_D#_12

K6

H_D#_13

M4

H_D#_14

K4

H_D#_15

P6

H_D#_16

W9

H_D#_17

V6

H_D#_18

V2

H_D#_19

P10

H_D#_20

W7

H_D#_21

N9

H_D#_22

P4

H_D#_23

U9

H_D#_24

V4

H_D#_25

U1

H_D#_26

W3

H_D#_27

V10

H_D#_28

U7

H_D#_29

W11

H_D#_30

U11

H_D#_31

AC11

H_D#_32

AC9

H_D#_33

Y4

H_D#_34

Y10

H_D#_35

AB6

H_D#_36

AA9

H_D#_37

AB10

H_D#_38

AA1

H_D#_39

AC3

H_D#_40

AC7

H_D#_41

AD12

H_D#_42

AB4

H_D#_43

Y6

H_D#_44

AD10

H_D#_45

AA11

H_D#_46

AB2

H_D#_47

AD4

H_D#_48

AE7

H_D#_49

AD2

H_D#_50

AD6

H_D#_51

AE3

H_D#_52

AG9

H_D#_53

AG7

H_D#_54

AE11

H_D#_55

AK6

H_D#_56

AF6

H_D#_57

AJ9

H_D#_58

AH6

H_D#_59

AF12

H_D#_60

AH4

H_D#_61

AJ7

H_D#_62

AE9

H_D#_63

B6

H_SWING

D4

H_RCOMP

J11

H_CPURST#

G9

H_CPUSLP#

L17

H_AVREF

K18

H_DVREF

CANTIGA GMCH SFF_FCBGA1363

HOST

H_ADSTB#_0
H_ADSTB#_1

H_BREQ#

H_DEFER#

HPLL_CLK

HPLL_CLK#

H_DPWR#

H_DRDY#

H_DINV#_0
H_DINV#_1
H_DINV#_2
H_DINV#_3

H_DSTBN#_0
H_DSTBN#_1
H_DSTBN#_2
H_DSTBN#_3

H_DSTBP#_0
H_DSTBP#_1
H_DSTBP#_2
H_DSTBP#_3

H_REQ#_0
H_REQ#_1
H_REQ#_2
H_REQ#_3
H_REQ#_4

layout note:
Place them close to U4 pin BC51.

Layout Note: V_DDR_MCH_REF trace
width and spacing is 20/20.

+VCCP

12

R54

221_0603_1%

12

100_0402_1%

H_SWNG

1

R61

C52

2

0.1U_0402_16V4Z

Near B6 pin

H_A#_3
H_A#_4
H_A#_5
H_A#_6
H_A#_7
H_A#_8

H_A#_9
H_A#_10
H_A#_11
H_A#_12
H_A#_13
H_A#_14
H_A#_15
H_A#_16
H_A#_17
H_A#_18
H_A#_19
H_A#_20
H_A#_21
H_A#_22
H_A#_23
H_A#_24
H_A#_25
H_A#_26
H_A#_27
H_A#_28
H_A#_29
H_A#_30
H_A#_31
H_A#_32
H_A#_33
H_A#_34
H_A#_35

H_ADS#

H_BNR#
H_BPRI#

H_DBSY#

H_HIT#
H_HITM#

H_LOCK#
H_TRDY#

H_RS#_0
H_RS#_1
H_RS#_2

PM_EXTTS#0
PM_EXTTS#1

4

H_A#3

L15

H_A#4

B14

H_A#5

C15

H_A#6

D12

H_A#7

F14

H_A#8

G17

H_A#9

B12

H_A#10

J15

H_A#11

D16

H_A#12

C17

H_A#13

D14

H_A#14

K16

H_A#15

F16

H_A#16

B16

H_A#17

C21

H_A#18

D18

H_A#19

J19

H_A#20

J21

H_A#21

B18

H_A#22

D22

H_A#23

G19

H_A#24

J17

H_A#25

L21

H_A#26

L19

H_A#27

G21

H_A#28

D20

H_A#29

K22

H_A#30

F18

H_A#31

K20

H_A#32

F20

H_A#33

F22

H_A#34

B20

H_A#35

A19
F10

A15
C19
C9
B8
C11
E5
D6
AH10
AJ11
G11
H2
C7
F8
A11
D8

L9
N7
AA7
AG3

K2
N3
AA3
AF4

L3
M2
Y2
AF2

J13
L13
C13
G13
G15

F4
F2
G7

V_DDR_MCH_REF14,15

R46 10K_0402_5%
R47 10K_0402_5%

Del R48. 9/27

4

V_DDR_MCH_REF

1 2
1 2

H_A#[3..35] 4

Add them for Boundary Scan. 10/23

H_ADS# 4
H_ADSTB#0 4
H_ADSTB#1 4
H_BNR# 4
H_BPRI# 4
H_BR0# 4
H_DEFER# 4
H_DBSY# 4
CLK_MCH_BCLK 16
CLK_MCH_BCLK# 16
H_DPWR# 5
H_DRDY# 4
H_HIT# 4
H_HITM# 4
H_LOCK# 4
H_TRDY# 4

H_DINV#0 5
H_DINV#1 5
H_DINV#2 5
H_DINV#3 5

H_DSTBN#0 5
H_DSTBN#1 5
H_DSTBN#2 5
H_DSTBN#3 5

H_DSTBP#0 5
H_DSTBP#1 5
H_DSTBP#2 5
H_DSTBP#3 5

H_REQ#0 4
H_REQ#1 4
H_REQ#2 4
H_REQ#3 4
H_REQ#4 4

H_RS#0 4
H_RS#1 4
H_RS#2 4

H_THERMTRIP#4,21

PM_DPRSLPVR22,42

C50

0.1U_0402_16V4Z

+3VS

3

T5
T6
T7
T8
T9
T10
T11
T12

1K_0402_5% @

4.7K_0402_5%@

+1.8V

1

1

C44

2

1

C46

2

C45

0.01U_0402_25V7K

2

1

C47

2

0.01U_0402_25V7K

MCH_CLKSEL016
MCH_CLKSEL116
MCH_CLKSEL216

12

R39
1K_0402_1%

12

R40

3.01K_0402_1%

12

R41
1K_0402_1%

T27

T28

CFG510
CFG610
CFG710

T88

CFG910

CFG1010

T89

CFG1210
CFG1310

T90

T91

CFG1610

T92

T93

CFG1910
CFG2010

PM_EXTTS#0
PM_EXTTS#1

R327 0_0402_5%

1 2

R428 100_0402_1%

1 2

+3VS

SMRCOMP_VOH

SMRCOMP_VOL

R251

1 2

R281

1 2

R311 4.7K_0402_5%@

1 2

R619 1K_0402_5% @

1 2

2.2U_0603_6.3V4Z

2.2U_0603_6.3V4Z

PM_BMBUSY#22

H_DPRSTP#5,21,42
PM_EXTTS#014
PM_EXTTS#115
PM_PWROK22,33,42,43
PLT_RST#20,26,32

1 2

R49 0_0402_5%

Add R428 in 9/26

+1.8V

12

R52
10K_0402_1%

12

1

R55
10K_0402_1%

2

Security Classification

Issued Date

THIS SHEET OF EN GINEE RING D RAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR DISCLO SED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/02/13 2006/03/10

T13

TCK
TDI
TDO
TMS

T18
T19

T20

T21

T22
T23
T24
T25

C480.1U_0402_16V4Z @

1

2

U4B

J43

RSVD1

L43

RSVD2

J41

RSVD3

L41

RSVD4

AN11

RSVD5

AM10

RSVD6

AK10

RSVD7

AL11

RSVD8

F12

RSVD9

AN45

RSVD10

AP44

RSVD11

AT44

RSVD12

AN47

RSVD13

C27

RSVD14

D30

RSVD15

J9

RSVD17

AW42

RSVD20

BB20

RSVD22

BE19

RSVD23

BF20

RSVD24

BF18

RSVD25

K26

CFG_0

G23

CFG_1

G25

CFG_2

J25

CFG_3

L25

CFG_4

L27

CFG_5

F24

CFG_6

D24

CFG_7

D26

CFG_8

J23

CFG_9

B26

CFG_10

A23

CFG_11

C23

CFG_12

B24

CFG_13

B22

CFG_14

K24

CFG_15

C25

CFG_16

L23

CFG_17

L33

CFG_18

K32

CFG_19

K34

CFG_20

J35

PM_SYNC#

F6

PM_DPRSTP#

J39

PM_EXT_TS#_0

L39

PM_EXT_TS#_1

AY39

PWROK

BB18

RSTIN#

K28

THERMTRIP#

K36

DPRSLPVR

A7

NC_1

A49

NC_2

A52

NC_3

A54

NC_4

B54

NC_5

D55

NC_6

G55

NC_7

BE55

NC_8

BH55

NC_9

BK55

NC_10

BK54

NC_11

BL54

NC_12

BL52

NC_13

BL49

NC_14

BL7

NC_15

BL4

NC_16

BL2

NC_17

BK2

NC_18

BK1

NC_19

BH1

NC_20

BE1

NC_21

G1

NC_22

Compal Secret Data

CANTIGA GMCH SFF_FCBGA1363

Deciphered Date

2

BB32

SA_CK_0

BA25

SA_CK_1

BA33

SB_CK_0

BA23

SB_CK_1

BA31

SA_CK#_0

BC25

SA_CK#_1

BC33

SB_CK#_0

BB24

SB_CK#_1

BC35

SA_CKE_0

BE33

SA_CKE_1

BE37

SB_CKE_0

BC37

SB_CKE_1

BK18

SA_CS#_0

BK16

SA_CS#_1

BE23

SB_CS#_0

BC19

SB_CS#_1

BJ17

SA_ODT_0

BJ19

SA_ODT_1

BC17

SB_ODT_0

BE17

SB_ODT_1

BL25

SM_RCOMP

SM_VREF

SM_PWROK

SM_REXT

PEG_CLK

PEG_CLK#

DMI_RXN_0
DMI_RXN_1
DMI_RXN_2
DMI_RXN_3

DMI_RXP_0
DMI_RXP_1
DMI_RXP_2
DMI_RXP_3

DMI_TXN_0
DMI_TXN_1
DMI_TXN_2
DMI_TXN_3

DMI_TXP_0
DMI_TXP_1
DMI_TXP_2
DMI_TXP_3

GFX_VID_0
GFX_VID_1
GFX_VID_2
GFX_VID_3
GFX_VID_4

BK26
BK32

BL31
BC51

AY37
BH20
BA37

B42
D42
B50
D50

R49
P50

AG55
AL49
AH54
AL47

AG53
AK50
AH52
AL45

AG49
AJ49
AJ47
AG47

AF50
AH50
AJ45
AG45

G33
G37
F38
F36
G35

G39

SM_RCOMP#

SM_RCOMP_VOH

SM_RCOMP_VOL

SM_DRAMRST#
DPLL_REF_CLK

DPLL_REF_CLK#

DDR CLK/ CONTROL/COMPENSATION

DPLL_REF_SSCLK

DPLL_REF_SSCLK#

CLK

CFGRSVD

DMI

PM

GFX_VR_EN

GRAPHICS VID

AK52

CL_CLK

AK54

CL_DATA

AW40

CL_PWROK

AL53

CL_RST#

AL55

CL_VREF

ME

CLKREQ#

ICH_SYNC#

TSATN#

HDA_BCLK

HDA_RST#

HDA_SDI

HDA_SDO

HDA_SYNC

F34
F32
B38
A37
C31
K42

D10

C29
B30
D28
A27
B28

Title

Size Document Number Rev

Custom

Date: Sheet

NC

2

DDPC_CTRLCLK

DDPC_CTRLDATA

SDVO_CTRLCLK

SDVO_CTRLDATA

MISC

HDA

1

M_CLK_DDR0 14
M_CLK_DDR1 14
M_CLK_DDR2 15
M_CLK_DDR3 15

M_CLK_DDR#0 14
M_CLK_DDR#1 14
M_CLK_DDR#2 15
M_CLK_DDR#3 15

DDR_CKE0_DIMMA 14
DDR_CKE1_DIMMA 14
DDR_CKE2_DIMMB 15
DDR_CKE3_DIMMB 15

DDR_CS0_DIMMA# 14
DDR_CS1_DIMMA# 14
DDR_CS2_DIMMB# 15
DDR_CS3_DIMMB# 15

M_ODT0 14
M_ODT1 14
M_ODT2 15

SMRCOMP
SMRCOMP#

SMRCOMP_VOH
SMRCOMP_VOL

V_DDR_MCH_REF
SM_PWROK
SM_REXT
TP_SM_DRAMRST#

CL_VREF

TSATN#

R616 54.9_0402_1%

Romoved, cause
don't need HDMI.
7/19

M_ODT3 15

R42 80.6_0402_1%

1 2

R43 80.6_0402_1%

1 2

R44 10K_0402_1%

1 2

R45 499_0402_1%

1 2

T26 P AD

CLK_MCH_DREFCLK 16
CLK_MCH_DREFCLK# 16
MCH_SSCDREFCLK 16
MCH_SSCDREFCLK# 16

CLK_MCH_3GPLL 16
CLK_MCH_3GPLL# 16

DMI_TXN0 22
DMI_TXN1 22
DMI_TXN2 22
DMI_TXN3 22

DMI_TXP0 22
DMI_TXP1 22
DMI_TXP2 22
DMI_TXP3 22

DMI_RXN0 22
DMI_RXN1 22
DMI_RXN2 22
DMI_RXN3 22

DMI_RXP0 22
DMI_RXP1 22
DMI_RXP2 22
DMI_RXP3 22

DFGT_VID_0 43
DFGT_VID_1 43
DFGT_VID_2 43
DFGT_VID_3 43
DFGT_VID_4 43

GFXVR_EN 43

CL_CLK0 22
CL_DATA0 22
M_PWROK 22,35
CL_RST# 22

T29
T30
T31
T32

1 2

C49

0.1U_0402_16V4Z

CLKREQ#_B 16
MCH_ICH_SYNC# 22

Modify in 9/26

Compal Electronics, Inc.

Cantiga(1/6)-AGTL/DMI/DDR

LA-4021P

1

+1.8V

+1.05VM

12

R50
1K_0402_1%

12

1

R51
511_0402_1%

2

+VCCP

0.1

of

845Monday, October 29, 2007

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5

D D

DDR_A_D[0..63]14

C C

B B

DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63

U4D

AP46

SA_DQ_0

AU47

SA_DQ_1

AT46

SA_DQ_2

AU49

SA_DQ_3

AR45

SA_DQ_4

AN49

SA_DQ_5

AV50

SA_DQ_6

AP50

SA_DQ_7

AW47

SA_DQ_8

BD50

SA_DQ_9

AW49

SA_DQ_10

BA49

SA_DQ_11

BC49

SA_DQ_12

AV46

SA_DQ_13

BA47

SA_DQ_14

AY50

SA_DQ_15

BF46

SA_DQ_16

BC47

SA_DQ_17

BF50

SA_DQ_18

BF48

SA_DQ_19

BC43

SA_DQ_20

BE49

SA_DQ_21

BA43

SA_DQ_22

BE47

SA_DQ_23

BF42

SA_DQ_24

BC39

SA_DQ_25

BF44

SA_DQ_26

BF40

SA_DQ_27

BB40

SA_DQ_28

BE43

SA_DQ_29

BF38

SA_DQ_30

BE41

SA_DQ_31

BA15

SA_DQ_32

BE11

SA_DQ_33

BE15

SA_DQ_34

BF14

SA_DQ_35

BB14

SA_DQ_36

BC15

SA_DQ_37

BE13

SA_DQ_38

BF16

SA_DQ_39

BF10

SA_DQ_40

BC11

SA_DQ_41

BF8

SA_DQ_42

BG7

SA_DQ_43

BC7

SA_DQ_44

BC9

SA_DQ_45

BD6

SA_DQ_46

BF12

SA_DQ_47

AV6

SA_DQ_48

BB6

SA_DQ_49

AW7

SA_DQ_50

AY6

SA_DQ_51

AT10

SA_DQ_52

AW11

SA_DQ_53

AU11

SA_DQ_54

AW9

SA_DQ_55

AR11

SA_DQ_56

AT6

SA_DQ_57

AP6

SA_DQ_58

AL7

SA_DQ_59

AR7

SA_DQ_60

AT12

SA_DQ_61

AM6

SA_DQ_62

AU7

SA_DQ_63

CANTIGA GMCH SFF_FCBGA1363

DDR SYSTEM MEMORY A

SA_BS_0
SA_BS_1
SA_BS_2

SA_RAS#
SA_CAS#

SA_WE#

SA_DM_0
SA_DM_1
SA_DM_2
SA_DM_3
SA_DM_4
SA_DM_5
SA_DM_6
SA_DM_7

SA_DQS_0
SA_DQS_1
SA_DQS_2
SA_DQS_3
SA_DQS_4
SA_DQS_5
SA_DQS_6

SA_DQS_7
SA_DQS#_0
SA_DQS#_1
SA_DQS#_2
SA_DQS#_3
SA_DQS#_4
SA_DQS#_5
SA_DQS#_6
SA_DQS#_7

SA_MA_0
SA_MA_1
SA_MA_2
SA_MA_3
SA_MA_4
SA_MA_5
SA_MA_6
SA_MA_7
SA_MA_8

SA_MA_9
SA_MA_10
SA_MA_11
SA_MA_12
SA_MA_13
SA_MA_14

4

BC21
BJ21
BJ41

BH22
BK20
BL15

AT50
BB50
BB46
BE39
BB12
BE7
AV10
AR9

AR47
BA45
BE45
BC41
BC13
BB10
BA7
AN7
AR49
AW45
BC45
BA41
BA13
BA11
BA9
AN9

BC23
BF22
BE31
BC31
BH26
BJ35
BB34
BH32
BB26
BF32
BA21
BG25
BH34
BH18
BE25

DDR_A_DM0
DDR_A_DM1
DDR_A_DM2
DDR_A_DM3
DDR_A_DM4
DDR_A_DM5
DDR_A_DM6
DDR_A_DM7

DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7
DDR_A_DQS#0
DDR_A_DQS#1
DDR_A_DQS#2
DDR_A_DQS#3
DDR_A_DQS#4
DDR_A_DQS#5
DDR_A_DQS#6
DDR_A_DQS#7

DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA14

DDR_A_BS0 14
DDR_A_BS1 14
DDR_A_BS2 14

DDR_A_RAS# 14
DDR_A_CAS# 14

DDR_A_WE# 14

DDR_A_DM[0..7] 14

DDR_A_DQS[0..7] 14

DDR_A_DQS#[0..7] 14

DDR_A_MA[0..14] 14

3

DDR_B_D[0..63]15

DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8

DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63

U4E

AP54

AM52

AR55
AV54

AM54

AN53
AT52
AU53

AW53

AY52
BB52
BC53
AV52

AW55

BD52
BC55
BF54
BE51
BH48
BK48
BE53
BH52
BK46

BJ47
BL45
BJ45

BL41
BH44
BH46
BK44
BK40

BJ39
BK10
BH10

BK6
BH6

BJ9

BL11

BG5

BJ5
BG3
BF4
BD4
BA3
BE5
BF2
BB4
AY4
BA1
AP2
AU1
AT2
AT4
AV4
AU3
AR3
AN1
AP4

AL3

AJ1
AK4
AM4
AH2
AK2

CANTIGA GMCH SFF_FCBGA1363

SB_DQ_0
SB_DQ_1
SB_DQ_2
SB_DQ_3
SB_DQ_4
SB_DQ_5
SB_DQ_6
SB_DQ_7
SB_DQ_8
SB_DQ_9
SB_DQ_10
SB_DQ_11
SB_DQ_12
SB_DQ_13
SB_DQ_14
SB_DQ_15
SB_DQ_16
SB_DQ_17
SB_DQ_18
SB_DQ_19
SB_DQ_20
SB_DQ_21
SB_DQ_22
SB_DQ_23
SB_DQ_24
SB_DQ_25
SB_DQ_26
SB_DQ_27
SB_DQ_28
SB_DQ_29
SB_DQ_30
SB_DQ_31
SB_DQ_32
SB_DQ_33
SB_DQ_34
SB_DQ_35
SB_DQ_36
SB_DQ_37
SB_DQ_38
SB_DQ_39
SB_DQ_40
SB_DQ_41
SB_DQ_42
SB_DQ_43
SB_DQ_44
SB_DQ_45
SB_DQ_46
SB_DQ_47
SB_DQ_48
SB_DQ_49
SB_DQ_50
SB_DQ_51
SB_DQ_52
SB_DQ_53
SB_DQ_54
SB_DQ_55
SB_DQ_56
SB_DQ_57
SB_DQ_58
SB_DQ_59
SB_DQ_60
SB_DQ_61
SB_DQ_62
SB_DQ_63

2

BJ13

SB_BS_0

BK12

SB_BS_1

BK38

SB_BS_2

BE21

SB_RAS#

BH14

SB_CAS#

BK14

SB_WE#

DDR_B_DM0

AP52

SB_DM_0
SB_DM_1
SB_DM_2
SB_DM_3
SB_DM_4
SB_DM_5
SB_DM_6
SB_DM_7

SB_DQS_0
SB_DQS_1
SB_DQS_2
SB_DQS_3
SB_DQS_4
SB_DQS_5
SB_DQS_6

SB_DQS_7
SB_DQS#_0
SB_DQS#_1
SB_DQS#_2
SB_DQS#_3
SB_DQS#_4
SB_DQS#_5
SB_DQS#_6
SB_DQS#_7

SB_MA_0
SB_MA_1
SB_MA_2
SB_MA_3
SB_MA_4
SB_MA_5
SB_MA_6
SB_MA_7
SB_MA_8

SB_MA_9
SB_MA_10
SB_MA_11
SB_MA_12
SB_MA_13
SB_MA_14

DDR SYSTEM MEMORY B

AY54
BJ49
BJ43
BH12
BD2
AY2
AJ3

AR53
BA53
BH50
BK42
BH8
BB2
AV2
AM2
AT54
BB54
BJ51
BH42
BK8
BC3
AW3
AN3

BJ15
BJ33
BH24
BA17
BF36
BH36
BF34
BK34
BJ37
BH40
BH16
BK36
BH38
BJ11
BL37

DDR_B_DM1
DDR_B_DM2
DDR_B_DM3
DDR_B_DM4
DDR_B_DM5
DDR_B_DM6
DDR_B_DM7

DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4
DDR_B_DQS5
DDR_B_DQS6

DDR_B_DQS7
DDR_B_DQS#0
DDR_B_DQS#1
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS#4
DDR_B_DQS#5
DDR_B_DQS#6
DDR_B_DQS#7

DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8

DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13
DDR_B_MA14

1

DDR_B_BS0 15
DDR_B_BS1 15
DDR_B_BS2 15

DDR_B_RAS# 15
DDR_B_CAS# 15
DDR_B_WE# 15

DDR_B_DM[0..7] 15

DDR_B_DQS[0..7] 15

DDR_B_DQS#[0..7] 15

DDR_B_MA[0..14] 15

A A

5

4

Security Classification

Issued Date

THIS SHEET OF EN GINEE RING D RAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR DISCLO SED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/02/13 2006/03/10

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

Compal Electronics, Inc.

Cantiga(2/6)-DDR2 A/B CH

LA-4021P

1

0.1

of

945Monday, October 29, 2007

电 脑 维 修 网

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技术支持：252670528

5

BLON_PWM18
ENABLT18

+3VS

DDC2_CLK18
DDC2_DATA18

D D

ENAVDD18

TXCLK_L-18
TXCLK_L+18

TXOUT_L0-18
TXOUT_L1-18
TXOUT_L2-18

TXOUT_L0+18
TXOUT_L1+18
TXOUT_L2+18

For make layout clearance, del
TP for channel B. 10/18

R65 10K_0402_5%

1 2

R66 10K_0402_5%

1 2

R67 2.37K_0402_1%

1 2

T33

For EMI. 9/26

R572 75_0402_5%@

1 2

R336 75_0402_5%@

C C

1 2

R337 75_0402_5%@

1 2

Del TV_LUMA & CRMA in 10/12.

D_BLUE17

D_GREEN17

D_RED17

CRT_DDC_CLK17

CRT_DDC_DATA17

CRT_HSYNC17
CRT_VSYNC17

B B

R70 30.1_0402_1%

1 2

R72 30.1_0402_1%

1 2

Close to pin D32 and keep
30mil space to other
part/trace.

4

10/18

10/19

10/19

10/18

Tie to GND. 9/28

D_BLUE
D_GREEN
D_RED

CRT_HSYNC_R
CRT_VSYNC_R

R74

1.02K_0402_1%

1 2

U4C

D38

L_BKLT_CTRL

C37

L_BKLT_EN

K38

L_CTRL_CLK

L37

L_CTRL_DATA

J37

L_DDC_CLK

L35

L_DDC_DATA

B36

L_VDD_EN

F50

LVDS_IBG

H46

LVDS_VBG

P44

LVDS_VREFH

K46

LVDS_VREFL

D46

LVDSA_CLK#

B46

LVDSA_CLK

D44

LVDSB_CLK#

B44

LVDSB_CLK

G45

LVDSA_DATA#_0

F46

LVDSA_DATA#_1

G41

LVDSA_DATA#_2

C45

LVDSA_DATA#_3

F44

LVDSA_DATA_0

G47

LVDSA_DATA_1

F40

LVDSA_DATA_2

A45

LVDSA_DATA_3

B40

LVDSB_DATA#_0

A41

LVDSB_DATA#_1

F42

LVDSB_DATA#_2

D48

LVDSB_DATA#_3

D40

LVDSB_DATA_0

C41

LVDSB_DATA_1

G43

LVDSB_DATA_2

B48

LVDSB_DATA_3

J27

TVA_DAC

E27

TVB_DAC

G27

TVC_DAC

F26

TVA_RTN

B34

TV_DCONSEL_0

D34

TV_DCONSEL_1

J29

CRT_BLUE

G29

CRT_GREEN

F30

CRT_RED

E29

CRT_IRTN

D36

CRT_DDC_CLK

C35

CRT_DDC_DATA

J33

CRT_HSYNC

D32

CRT_TVO_IREF

G31

CRT_VSYNC

CANTIGA GMCH SFF_FCBGA1363

Del R82, R83. 10/18

PEG_COMPI

PEG_COMPO

PEG_RX#_0
PEG_RX#_1
PEG_RX#_2
PEG_RX#_3
PEG_RX#_4
PEG_RX#_5
PEG_RX#_6
PEG_RX#_7
PEG_RX#_8

LVDS

TV

VGA

PEG_RX#_9
PEG_RX#_10
PEG_RX#_11
PEG_RX#_12
PEG_RX#_13
PEG_RX#_14
PEG_RX#_15

PEG_RX_0
PEG_RX_1
PEG_RX_2
PEG_RX_3
PEG_RX_4
PEG_RX_5
PEG_RX_6
PEG_RX_7
PEG_RX_8

PEG_RX_9
PEG_RX_10
PEG_RX_11
PEG_RX_12
PEG_RX_13
PEG_RX_14
PEG_RX_15

PEG_TX#_0
PEG_TX#_1
PEG_TX#_2
PEG_TX#_3
PEG_TX#_4
PEG_TX#_5
PEG_TX#_6
PEG_TX#_7
PEG_TX#_8
PEG_TX#_9

PEG_TX#_10

PCI-EXPRESS GRAPHICS

PEG_TX#_11
PEG_TX#_12
PEG_TX#_13
PEG_TX#_14
PEG_TX#_15

PEG_TX_0

PEG_TX_1

PEG_TX_2

PEG_TX_3

PEG_TX_4

PEG_TX_5

PEG_TX_6

PEG_TX_7

PEG_TX_8

PEG_TX_9
PEG_TX_10
PEG_TX_11
PEG_TX_12
PEG_TX_13
PEG_TX_14
PEG_TX_15

Remove R84 ~ R86 since
already have 75ohm of
page17. 10/27

3

PEGCOMP trace width
and spacing is 20/25 mils.

PEGCOMP

U45
T44

D52
G49
K54
H50
M52
N49
P54
V46
Y50
V52
W49
AB54
AD46
AC55
AE49
AF54

E51
F48
J55
J49
M54
M50
P52
U47
AA49
V54
V50
AB52
AC47
AC53
AD50
AF52

L47
F52
P46
H54
L55
T46
R53
U49
T54
Y46
AB46
W53
Y54
AC49
AF46
AD54

J47
F54
N47
H52
L53
R47
R55
T50
T52
W47
AA47
W55
Y52
AB50
AE47
AD52

1 2

R64 49.9_0402_1%

layout note:
Place R64 <500mils to U4 pin U45&T44.

+VCC_PEG

2

Strap Pin Table

CFG[2:0] FSB Freq select

CFG[4:3] Reserved

CFG5 (DMI select)

CFG6

CFG6

CFG7 (Intel Management
Engine Crypto strap)

CFG8

CFG9
(PCIE Graphic s Lane Reversal)

CFG10 (PCIE Lookback enable)

CFG11
CFG[13:12] (XOR/ALLZ)

CFG16 (FSB Dynamic ODT)

CFG19 (DMI Lane Reversal)

CFG20 (PCIE/SDVO concurrent)

1

000 = FSB 1066MHz
010 = FSB 800MHz
011 = FSB 667MHz

Others = Reserved

0 = DMI x 2

1 = DMI x 4

0 = The iTPM Host Interface is enable

*

1 = The iTPM Host Interface is disable

0 =(TLS)chip e r s u i t e with no confidentiality

1 =(TLS)chip e r s uite with confidentiality

Reserved

0 = Reverse Lane,15->0, 14->1

1 = Normal Operation,Lane Number in order

0 = Enable

1 = Disable

Reserved

00 = Reserved

01 = XOR Mode Enabled

10 = All Z Mode Enabled

*

(Default)11 = Normal Operation

ReservedCFG[15:14]

0 = Disabled

1 = Enabled

*

ReservedCFG[18:17]

0 = Normal Operation

(Lane number in Order)

*

1 = Reverse Lane

0 = Only PCIE or SDVO is operational.

1 = PCIE/SDVO a r e o p e r a t ing simu.

R91 2.21K_0402_1% @

CFG58
CFG68
CFG78

CFG98
CFG108
CFG128
CFG138
CFG168

CFG198
CFG208

1 2

R69 2.21K_0402_1% @

1 2

R71 2.21K_0402_1% @

1 2

R75 2.21K_0402_1% @

1 2

R76 2.21K_0402_1% @

1 2

R78 2.21K_0402_1%@

1 2

R79 2.21K_0402_1% @

1 2

R93 2.21K_0402_1% @

1 2

R90 4.02K_0402_1%@

1 2

R92 4.02K_0402_1% @

1 2

*

*

*

*

*

+3VS

A A

5

4

Security Classification

Issued Date

THIS SHEET OF EN GINEE RING D RAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR DISCLO SED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/02/13 2006/03/10

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

Compal Electronics, Inc.

Cantiga(3/6)-VGA/LVDS/TV

LA-4021P

10 45Monday, October 29, 2007

1

0.1

of

电 脑 维 修 网

http://www.dnfix.cn/bbs

伟 力 电 脑 医 院

技术支持：252670528

5

+3VS

BLM18PG181SN1D_0603

D D

+1.5VS

C C

B B

+1.05VM_HPLL

+3VS_DAC_CRT

R96

12

0.1U_0402_16V4Z

0.01U_0402_16V7K

+3VS

1

1

C62

2

R104 0_0603_5%

1 2

9/27

+1.05VM

+1.05VM_PEGPLL

1

C97

9/27

2

0.1U_0402_16V4Z

BLM18PG181SN1D_0603

C63

2

+1.5VS_PEG_BG

C78

0.1U_0402_16V4Z

R106 0_0805_5%

1 2

1

+

2

C82

100U_D2_6.3VM

R110 0_0603_5%

1 2

1

C98

+1.8V

2

0.1U_0402_16V4Z

R97

1

2

+1.8V_TXLVDS

9/27

R111 0_0603_5%

+3VS_DAC_BG

12

0.1U_0402_16V4Z

1

2

C64

10U_0805_6.3V6M

0.01U_0402_16V7K

1

1

9/27

C65

+1.05VM_DPLLA

2

2

+1.05VM_DPLLB

+1.05VM_HPLL
+1.05VM_MPLL

C73
1000P_0402_50V7K

+1.05VM_PEGPLL

+1.05VM_A_SM

4.7U_0805_10V4Z

1U_0603_10V4Z

1

1

2

2

C84

C83

+1.05VM_A_SM_CK

10U_0805_6.3V6M

0.1U_0402_16V4Z

1

C92

C93

2

12

1

2

C85

1

2

1U_0603_10V4Z

1

C99

2

+1.8V_LVDS

4

U4H

J31

VCCA_CRT_DAC

L31

VCCA_DAC_BG

M33

VSSA_DAC_BG

J45

VCCA_DPLLA

L49

VCCA_DPLLB

AF10

VCCA_HPLL

AE1

VCCA_MPLL

U43

VCCA_LVDS1

U41

VCCA_LVDS2

V44

VSSA_LVDS

AJ43

VCCA_PEG_BG

AG43

VCCA_PEG_PLL

AW24

VCCA_SM_1

AU24

VCCA_SM_2

AW22

VCCA_SM_3

AU22

VCCA_SM_4

AU21

VCCA_SM_5

AW20

VCCA_SM_6

AU19

VCCA_SM_7

AW18

VCCA_SM_8

AU18

VCCA_SM_9

AW16

VCCA_SM_10

AU16

VCCA_SM_11

AT16

VCCA_SM_12

AR16

VCCA_SM_13

AU15

VCCA_SM_14

AT15

VCCA_SM_15

AR15

VCCA_SM_16

AW14

VCCA_SM_17

AT24

VCCA_SM_NCTF_1

AR24

VCCA_SM_NCTF_2

AT22

VCCA_SM_NCTF_3

AR22

VCCA_SM_NCTF_4

AT21

VCCA_SM_NCTF_5

AR21

VCCA_SM_NCTF_6

AT19

VCCA_SM_NCTF_7

AR19

VCCA_SM_NCTF_8

AT18

VCCA_SM_NCTF_9

AR18

VCCA_SM_NCTF_10

AU27

VCCA_SM_CK_4

AU28

VCCA_SM_CK_3

AU29

VCCA_SM_CK_2

AU31

VCCA_SM_CK_1

AT31

VCCA_SM_CK_NCTF_1

AR31

VCCA_SM_CK_NCTF_2

AT29

VCCA_SM_CK_NCTF_3

AR29

VCCA_SM_CK_NCTF_4

AT28

VCCA_SM_CK_NCTF_5

AR28

VCCA_SM_CK_NCTF_6

AT27

VCCA_SM_CK_NCTF_7

AR27

VCCA_SM_CK_NCTF_8

AH12

VCCD_HPLL

AE43

VCCD_PEG_PLL

M46

VCCD_LVDS_1

L45

VCCD_LVDS_2

CANTIGA GMCH SFF_ FCB GA1363

CRTPLLA PEGA SM

A LVDS

POWER

LVDS

VCCA_TV_DAC

TVD TV/CRT

HDA

VCCD_QDAC

VCCD_TVDAC

VCC_AXF_1
VCC_AXF_2
VCC_AXF_3

AXF

VCC_SM_CK_1
VCC_SM_CK_2
VCC_SM_CK_3
VCC_SM_CK_4

SM CK

VCC_TX_LVDS

HV

VCC_PEG_1
VCC_PEG_2
VCC_PEG_3
VCC_PEG_4

PEG

VCC_DMI_1
VCC_DMI_2
VCC_DMI_3

DMI

VTTLF

VTT_1
VTT_2
VTT_3
VTT_4
VTT_5
VTT_6
VTT_7
VTT_8

VTT_9
VTT_10
VTT_11
VTT_12
VTT_13

VTT

VCC_HDA

VCC_HV_1
VCC_HV_2

VTTLF1
VTTLF2
VTTLF3

R13
T12
R11
T10
R9
T8
R7
T6
R5
T4
R3
T2
R1

K30

A31

N34
N32

M25
N24
M23

BK24
BL23
BJ23
BK22

T41
C33

A33

AB44
Y44
AC43
AA43

AM44
AN43
AL43

K14
Y12
P2

R101
0_0402_5%

1 2

9/27

0.47U_0603_10V7K

1

C100

2

3

0.47U_0603_10V7K

1

2

C58

+1.5VS_QDAC

+1.5VS_TVDAC

+V1.05VM_AXF

+1.8V_SM_CK

+1.8V_TXLVDS

+VCC_PEG

+1.05VM_DMI

9/29

0.47U_0603_10V7K

1

C101

2

2.2U_0805_16V4Z

4.7U_0805_10V4Z

4.7U_0805_10V4Z

1

1

C60

2

2

C59

+3VS_TVDAC

Tie to GND. 9/27

+3VS_HV

0.1U_0402_16V4Z

1

2

C94

0.47U_0603_10V7K

1

C102

2

+VCCP

1

2

C61

0.01U_0402_16V7K

1

C71

2

1

+

2

C57

330U_D2E_2.5VM_R7

1 2

BLM18PG181SN1D_0603

0.1U_0402_16V4Z

1

C72

2

R100

+VCCP

+3VS

2

+1.05VM_DPLLA +1.05VM

9/27

1

1

+

C53

C54

2

2

0.1U_0402_16V4Z

+1.05VM_DPLLB

9/27

1

1

+3VS

+1.05VM_HPLL

9/27

+1.05VM_PEGPLL

2 1

D1 CH751H-40_SC76

+

C66

C70

2

2

0.1U_0402_16V4Z

1

1

2

2

C74

C75

0.1U_0402_16V4Z

4.7U_0805_10V4Z

+1.05VM_MPLL

1

1

C81

C80

2

2

0.1U_0402_16V4Z

10U_0805_6.3V6M

+1.8V_TXLVDS +1.8V

1

1

2

2

C89

1000P_0402_50V7K

10U_0805_10V4Z

0.1U_0402_16V4Z

1

1

C96

C95

2

2

+VCCP_D

R112 10_0402_5%

+1.5VS_QDAC

0.1U_0402_16V4Z

0.01U_0402_16V7K

1

1

C104

C103

2

2

R94

1 2

BLM18PG181SN1D_0603

220U_D2_4VM

R98

1 2

BLM18PG181SN1D_0603

220U_D2_4VM

R102

1 2

BLM18PG181SN1D_0603

R105

1 2

BLM18PG181SN1D_0603

R108 0_0603_5%

1 2

C90

10U_0805_6.3V6M @

L1

1 2

BLM18PG121SN1D_0603

1 2

R114

1 2

BLM18PG181SN1D_0603

9/27

9/27

9/27

9/27

+1.05VM

+1.05VM

+1.05VM

9/29

+1.5VS

9/27

+1.05VM

+1.5VS_TVDAC

+VCC_PEG

4.7U_0805_10V4Z

1

C87

2

+1.05VM_DMI

0.1U_0402_16V4Z

C91

R113 0_0402_5%

1 2

+V1.05VM_AXF

10U_0805_10V4Z

1

C55

2

+1.8V_SM_CK

0.1U_0402_16V4Z

0_0603_5%

C68

R597

1 2

10U_0805_6.3V6M

1

C67

2

0.01U_0402_16V7K

0.1U_0402_16V4Z

1

C76

C77

2

10U_0805_6.3V6M

220U_D2_4VM

1

C88

C86

2

R109 0_0603_5%

1 2

1

2

1U_0603_10V4Z

1

2

1

2

1

+

2

1

9/27

R95 0_0603_5%

1 2

1

C56

2

R99 0_0805_5%

1 2

R103

1 2

1 2

10U_0805_6.3V6M

1

C69

2

BLM18PG181SN1D_0603

R107 0_0805_5%

9/21

+1.05VM

+3VS_HV

+1.05VM

+1.8V

+1.5VS

9/21

+1.05VM

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAI NS CONFIDE NTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/02/13 2006/03/10

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

Compal Electronics, Inc.

Cantiga(4/6)-PWR

LA-4021P

1

0.1

of

11 45Monday, October 29, 2007

电 脑 维 修 网

http://www.dnfix.cn/bbs

伟 力 电 脑 医 院

技术支持：252670528

5

Extnal Graphic: 1210.34mA
integrated Graphic: 1930.4mA

AT41
AR41
AN41

AJ41
AH41
AD41
AC41

Y41

W41
AT40
AM40

AL40

AJ40
AH40
AG40
AE40
AD40
AC40
AA40

Y40
AN35
AM35

AJ35
AH35
AD35
AC35

W35

AM34

AL34

AJ34
AH34
AG34
AE34
AD34

AC34
AA34

Y34

W34

AM32

AL32

AJ32
AH32
AE32
AD32
AA32
AM31

AL31

AJ31
AH31
AM29

AL29
AM28

AL28

AJ28
AM27

AL27
AM25

AL25

AJ25
AM24

N36

U4F

VCC_1
VCC_2
VCC_3
VCC_4
VCC_5
VCC_6
VCC_7
VCC_8
VCC_9
VCC_10
VCC_11
VCC_12

VCC_13
VCC_14
VCC_15
VCC_16
VCC_17
VCC_18
VCC_19
VCC_20
VCC_21
VCC_22
VCC_23
VCC_24
VCC_25
VCC_26
VCC_27
VCC_28
VCC_29
VCC_30
VCC_31
VCC_32
VCC_33
VCC_34

VCC_35
VCC_36

VCC_37
VCC_38
VCC_39
VCC_40
VCC_41
VCC_42
VCC_43
VCC_44
VCC_45
VCC_46
VCC_47
VCC_48
VCC_49
VCC_50
VCC_51
VCC_52
VCC_53
VCC_54
VCC_55
VCC_56
VCC_57
VCC_58
VCC_59
VCC_60
VCC_61

9/21

C115

+1.05VM

0.1U_0402_16V4Z

C116

1

2

D D

220U_D2_4VM_R15

C112

C C

B B

0.22U_0402_10V4Z

10U_0805_6.3V6M

1

+

2

0.22U_0402_10V4Z

C113

C114

1

1

1

2

2

2

CANTIGA GMCH SFF_FCBGA1363

A A

4

VCC CORE

POWER

VCC_NCTF_1
VCC_NCTF_2
VCC_NCTF_3
VCC_NCTF_4
VCC_NCTF_5
VCC_NCTF_6
VCC_NCTF_7
VCC_NCTF_8

VCC_NCTF_9
VCC_NCTF_10
VCC_NCTF_11
VCC_NCTF_12
VCC_NCTF_13
VCC_NCTF_14
VCC_NCTF_15
VCC_NCTF_16
VCC_NCTF_17
VCC_NCTF_18
VCC_NCTF_19
VCC_NCTF_20
VCC_NCTF_21
VCC_NCTF_22
VCC_NCTF_23
VCC_NCTF_24
VCC_NCTF_25
VCC_NCTF_26
VCC_NCTF_27
VCC_NCTF_28
VCC_NCTF_29
VCC_NCTF_30
VCC_NCTF_31

VCC NCTF

VCC_NCTF_32
VCC_NCTF_33
VCC_NCTF_34
VCC_NCTF_35
VCC_NCTF_36
VCC_NCTF_37
VCC_NCTF_38

AT38
AR38
AN38
AM38
AL38
AG38
AE38
AA38
Y38
W38
U38
T38
R38
AT37
AR37
AN37
AM37
AL37
AJ37
AH37
AG37
AE37
AD37
AC37
AA37
Y37
W37
U37
T37
R37
AT35
AR35
U35
AT34
AR34
U34
T34
R34

9/21

+1.05VM

+1.8V

330U_D2E_2.5VM_R9

C117

3

+VCCGFX

2

U4G

3000mA

POWER

VCC SMVCC GFX

VCC GFX NCTF

VCC GFX

VCC_AXG_NCTF_1
VCC_AXG_NCTF_2
VCC_AXG_NCTF_3
VCC_AXG_NCTF_4
VCC_AXG_NCTF_5
VCC_AXG_NCTF_6
VCC_AXG_NCTF_7
VCC_AXG_NCTF_8

VCC_AXG_NCTF_9
VCC_AXG_NCTF_10
VCC_AXG_NCTF_11
VCC_AXG_NCTF_12
VCC_AXG_NCTF_13
VCC_AXG_NCTF_14
VCC_AXG_NCTF_15
VCC_AXG_NCTF_16
VCC_AXG_NCTF_17
VCC_AXG_NCTF_18
VCC_AXG_NCTF_19
VCC_AXG_NCTF_20
VCC_AXG_NCTF_21
VCC_AXG_NCTF_22
VCC_AXG_NCTF_23
VCC_AXG_NCTF_24
VCC_AXG_NCTF_25
VCC_AXG_NCTF_26
VCC_AXG_NCTF_27
VCC_AXG_NCTF_28
VCC_AXG_NCTF_29
VCC_AXG_NCTF_30
VCC_AXG_NCTF_31
VCC_AXG_NCTF_32
VCC_AXG_NCTF_33
VCC_AXG_NCTF_34
VCC_AXG_NCTF_35
VCC_AXG_NCTF_36
VCC_AXG_NCTF_37
VCC_AXG_NCTF_38
VCC_AXG_NCTF_39
VCC_AXG_NCTF_40
VCC_AXG_NCTF_41
VCC_AXG_NCTF_42
VCC_AXG_NCTF_43
VCC_AXG_NCTF_44

VCC_AXG_62
VCC_AXG_63
VCC_AXG_64
VCC_AXG_65
VCC_AXG_66
VCC_AXG_67
VCC_AXG_68
VCC_AXG_69
VCC_AXG_70
VCC_AXG_71
VCC_AXG_72
VCC_AXG_73
VCC_AXG_74
VCC_AXG_75
VCC_AXG_76
VCC_AXG_77
VCC_AXG_78
VCC_AXG_79
VCC_AXG_80

VCC_SM_LF1
VCC_SM_LF2
VCC_SM_LF3
VCC_SM_LF4
VCC_SM_LF5
VCC_SM_LF6
VCC_SM_LF7

VCC SM LF

BB36

VCC_SM_1

BE35

VCC_SM_2

AW34

VCC_SM_3

10U_0805_6.3V6M

10U_0805_6.3V6M

330U_D2E_2.5VM_R9

1

C108

+

2

1

+

2

1

C118

2

1

C119

2

10U_0805_10V4Z

0.01U_0402_16V7K

C109

C110

1

1

2

2

2

1

1

1

C120

C121

2

2

1U_0603_10V4Z

10U_0805_10V4Z

6326.84mA

T46PAD
T47PAD

AW32

VCC_SM_4

BK30

VCC_SM_5

BH30

VCC_SM_6

BF30

C111

0.1U_0402_16V4Z

BD30
BB30

AW30

BL29

BJ29
BG29
BE29
BC29
BA29
AY29
BK28
BH28
BF28
BD28
BB28

BL27

BJ27
BG27
BE27
BC27
BA27
AY27

AW26

BF24

BL19
BB16

W32
AG31
AE31
AD31
AC31
AA31

W31
AH29
AG29
AE29
AD29
AC29
AA29

W29
AH28
AG28
AE28
AA28
AH27
AG27
AE27
AD27
AC27
AA27

W27
AH25
AD25
AC25

W25

AJ24
AH24
AG24
AE24
AD24
AC24
AA24

W24
AM22

AL22

AJ22
AH22
AG22
AE22
AD22
AC22
AA22
AM21

AL21

AJ21
AH21
AD21
AC21
AA21

W21
AM16

AL16

AG13
AE13

Y31

Y29

Y27

Y24

Y21

VCC_SM_7
VCC_SM_8
VCC_SM_9
VCC_SM_10
VCC_SM_11
VCC_SM_12
VCC_SM_13
VCC_SM_14
VCC_SM_15
VCC_SM_16
VCC_SM_17
VCC_SM_18
VCC_SM_19
VCC_SM_20
VCC_SM_21
VCC_SM_22
VCC_SM_23
VCC_SM_24
VCC_SM_25
VCC_SM_26
VCC_SM_27
VCC_SM_28
VCC_SM_29
VCC_SM_30
VCC_SM_31
VCC_SM_32
VCC_SM_33

VCC_AXG_1
VCC_AXG_2
VCC_AXG_3
VCC_AXG_4
VCC_AXG_5
VCC_AXG_6
VCC_AXG_7
VCC_AXG_8
VCC_AXG_9
VCC_AXG_10
VCC_AXG_11
VCC_AXG_12
VCC_AXG_13
VCC_AXG_14
VCC_AXG_15
VCC_AXG_16
VCC_AXG_17
VCC_AXG_18
VCC_AXG_19
VCC_AXG_20
VCC_AXG_21
VCC_AXG_22
VCC_AXG_23
VCC_AXG_24
VCC_AXG_25
VCC_AXG_26
VCC_AXG_27
VCC_AXG_28
VCC_AXG_29
VCC_AXG_30
VCC_AXG_31
VCC_AXG_32
VCC_AXG_33
VCC_AXG_34
VCC_AXG_35
VCC_AXG_36
VCC_AXG_37
VCC_AXG_38
VCC_AXG_39
VCC_AXG_40
VCC_AXG_41
VCC_AXG_42
VCC_AXG_43
VCC_AXG_44
VCC_AXG_45
VCC_AXG_46
VCC_AXG_47
VCC_AXG_48
VCC_AXG_49
VCC_AXG_50
VCC_AXG_51
VCC_AXG_52
VCC_AXG_53
VCC_AXG_54
VCC_AXG_55
VCC_AXG_56
VCC_AXG_57
VCC_AXG_58
VCC_AXG_59
VCC_AXG_60
VCC_AXG_61

VCC_AXG_SENSE
VSS_AXG_SENSE

T32
U31
T31
R31
U29
T29
R29
U28
U27
T27
R27
U25
T25
R25
U24
U22
T22
R22
U21
T21
R21
AM19
AL19
AH19
AG19
AE19
AD19
AC19
W19
U19
AM18
AL18
AJ18
AH18
AG18
AE18
AD18
AC18
AA18
Y18
W18
U18
T18
R18

AJ16
AH16
AD16
AC16
AA16
U16
T16
R16
AM15
AL15
AJ15
AH15
AG15
AE15
AA15
Y15
W15
U15
T15

AU45
BF52
BB38
BA19
BE9
AU9
AL9

+VCCGFX

VCCSM_LF1
VCCSM_LF2
VCCSM_LF3
VCCSM_LF4
VCCSM_LF5
VCCSM_LF6
VCCSM_LF7

1

1

1

2

C105

0.1U_0402_16V4Z

C127 0.1U_0402_16V4Z

1

2

1

2

2

C106

C107

4.7U_0805_10V4Z

0.22U_0402_10V4Z

C122 0.22U_0603_10V7K

C123 0.22U_0603_10V7K

1

1

1

C128 0.1U_0402_16V4Z

1

2

2

2

2

C124 0.47U_0402_6.3V6K

C125 1U_0603_10V4Z

C126 1U_0603_10V4Z

1

1

2

2

CANTIGA GMCH SFF_FCBGA1363

5

4

Security Classification

Issued Date

THIS SHEET OF EN GINEE RING D RAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR DISCLO SED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/02/13 2006/03/10

Compal Secret Data

Deciphered Date

2

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

Cantiga(5/6)-PWR/GND

LA-4021P

1

of

12 45Monday, October 29, 2007

0.1

电 脑 维 修 网

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技术支持：252670528

5

U4I

BA55

VSS_1

AU55

VSS_2

AN55

VSS_3

AJ55

VSS_4

AE55

VSS_5

AA55

VSS_6

U55

VSS_7

N55

VSS_8

BD54

VSS_9

BG53

VSS_10

AJ53

VSS_11

AE53

D D

C C

B B

A A

VSS_12

AA53

VSS_13

U53

VSS_14

N53

VSS_15

J53

VSS_16

G53

VSS_17

E53

VSS_18

K52

VSS_19

BG51

VSS_20

BA51

VSS_21

AW51

VSS_22

AU51

VSS_23

AR51

VSS_24

AN51

VSS_25

AL51

VSS_26

AJ51

VSS_27

AG51

VSS_28

AE51

VSS_29

AC51

VSS_30

AA51

VSS_31

W51

VSS_32

U51

VSS_33

R51
N51
L51

J51
G51
C51

BK50

AM50

K50

BG49

E49
C49

BD48

BB48
AY48
AV48
AT48
AP48

AM48

AK48

AH48

AF48

AD48

AB48

Y48
V48
T48
P48
M48
K48
H48

BL47

BG47

E47
C47
A47

BD46

AY46

AM46

AK46
AH46
BG45

AE45
AC45

AA45

W45

R45
N45
E45

BD44

BB44

AV44

AK44
AH44

AF44
AD44

K44
H44

BL43
BG43

AY43
AR43

W43

R43
M43
E43

CANTIGA GMCH SFF_FCBGA1363

VSS

VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47
VSS_48
VSS_49
VSS_50
VSS_51
VSS_52
VSS_53
VSS_54
VSS_55
VSS_56
VSS_57
VSS_58
VSS_59
VSS_60
VSS_61
VSS_62
VSS_63
VSS_64
VSS_65
VSS_66
VSS_67
VSS_68
VSS_69
VSS_70
VSS_71
VSS_72
VSS_73
VSS_74
VSS_75
VSS_76
VSS_77
VSS_78
VSS_79
VSS_80
VSS_81
VSS_82
VSS_83
VSS_84
VSS_85
VSS_86
VSS_87
VSS_88
VSS_89
VSS_90
VSS_91
VSS_92
VSS_93
VSS_94
VSS_95
VSS_96
VSS_97
VSS_98
VSS_99

+3VS+3VS +3VS +3VS

VSS_100
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105
VSS_106
VSS_107
VSS_108
VSS_109
VSS_110
VSS_111
VSS_112
VSS_113
VSS_114
VSS_115
VSS_116
VSS_117
VSS_118
VSS_119
VSS_120
VSS_121
VSS_122
VSS_123
VSS_124
VSS_125
VSS_126
VSS_127
VSS_128
VSS_129
VSS_130
VSS_131
VSS_132
VSS_133
VSS_134
VSS_135
VSS_136
VSS_137
VSS_138
VSS_139
VSS_140
VSS_141
VSS_142
VSS_143
VSS_144
VSS_145
VSS_146
VSS_147
VSS_148
VSS_149
VSS_150
VSS_151
VSS_152
VSS_153
VSS_154
VSS_155
VSS_156
VSS_157
VSS_158
VSS_159
VSS_160
VSS_161
VSS_162
VSS_163
VSS_164
VSS_165
VSS_166
VSS_167
VSS_168
VSS_169
VSS_170
VSS_171
VSS_172
VSS_173
VSS_174
VSS_175
VSS_176
VSS_177
VSS_178
VSS_179
VSS_180
VSS_181
VSS_182
VSS_183
VSS_184
VSS_185
VSS_186
VSS_187
VSS_188
VSS_189
VSS_190
VSS_191
VSS_192
VSS_193
VSS_194
VSS_195
VSS_196
VSS_197
VSS_198

C43
A43
BD42
H42
BG41
AY41
AU41
AM41
AL41
AG41
AE41
AA41
R41
M41
E41
BD40
AU40
AR40
AN40
W40
U40
T40
R40
K40
H40
BL39
BG39
BA39
E39
C39
A39
BD38
AU38
H38
BG37
AU37
M37
E37
BD36
AW36
H36
BL35
BG35
AY35
AU35
AL35
AG35
AE35
AA35
Y35
M35
E35
A35
BD34
AU34
AN34
H34
BL33
BG33
AY33
E33
BD32
AU32
AN32
AG32
AC32
Y32
H32
B32
BJ31
BG31
AY31
AN31
M31
E31
N30
H30
AN29
AJ29
M29
A29
AW28
AN28
AD28
AC28
Y28
W28
H28
F28
AN27
AJ27
M27
BF26
BD26
N26
H26
BJ25
AY25
AU25

4

3

U4J

AN25

VSS_199

AG25

VSS_200

AE25

VSS_201

AA25

VSS_202

Y25

VSS_203

E25

VSS_204

A25

VSS_205

BD24

VSS_206

AN24

VSS_207

AL24

VSS_208

H24

VSS_209

BG23

VSS_210

AY23

VSS_211

E23

VSS_212

BD22

VSS_213

BB22

VSS_214

AN22

VSS_215

Y22

VSS_216

W22

VSS_217

H22

VSS_218

BL21

VSS_219

BG21

VSS_220

AY21

VSS_221

AN21

VSS_222

AG21

VSS_223

AE21

VSS_224

M21

VSS_225

E21

VSS_226

A21

VSS_227

BD20

VSS_228

H20

VSS_229

BG19
AY19

BD18

BL17
BG17
AY17

BD16
AN16
AG16
AE16

BG15
AY15
AN15
AD15
AC15

BD14

BL13
BG13
AY13
AU13
AR13

AJ13
AC13
AA13

BD12
AV12
AP12

AM12

AK12
AB12

BG11
AG11

BD10
AY10
AP10

M19

M17

W16

M15

W13
M13

BG9

BD8

E19
N18

H18

E17
A17

Y16
N16

H16

R15
E15
H14

U13
E13

A13

V12
P12
H12

E11

H10
BL9

E9
A9

BB8
AY8
AV8
AT8
AP8

VSS

VSS_230
VSS_231
VSS_232
VSS_233
VSS_234
VSS_235
VSS_236
VSS_237
VSS_238
VSS_239
VSS_240
VSS_241
VSS_242
VSS_243
VSS_244
VSS_245
VSS_246
VSS_247
VSS_248
VSS_249
VSS_250
VSS_251
VSS_252
VSS_253
VSS_254
VSS_255
VSS_256
VSS_257
VSS_258
VSS_259
VSS_260
VSS_261
VSS_262
VSS_263
VSS_264
VSS_265
VSS_266
VSS_267
VSS_268
VSS_269
VSS_270
VSS_271
VSS_272
VSS_273
VSS_274
VSS_275
VSS_276
VSS_277
VSS_278
VSS_279
VSS_280
VSS_281
VSS_282
VSS_283
VSS_284
VSS_285
VSS_286
VSS_287
VSS_288
VSS_289
VSS_290
VSS_291
VSS_292
VSS_293
VSS_294
VSS_295
VSS_296
VSS_297
VSS_298
VSS_299

CANTIGA GMCH SFF_FCBGA1363

VSS_NCTF_10
VSS_NCTF_11
VSS_NCTF_12

VSS NCTF

VSS_NCTF_13
VSS_NCTF_14
VSS_NCTF_15
VSS_NCTF_16
VSS_NCTF_17
VSS_NCTF_18
VSS_NCTF_19
VSS_NCTF_20
VSS_NCTF_21
VSS_NCTF_22
VSS_NCTF_23

VSS SCB

VSS_300
VSS_301
VSS_302
VSS_303
VSS_304
VSS_305
VSS_306
VSS_307
VSS_308
VSS_309
VSS_310
VSS_311
VSS_312
VSS_313
VSS_314
VSS_315
VSS_316
VSS_317
VSS_318
VSS_319
VSS_320
VSS_321
VSS_322
VSS_323
VSS_324
VSS_325
VSS_326
VSS_327
VSS_328
VSS_329
VSS_330
VSS_331
VSS_332
VSS_333
VSS_334
VSS_335
VSS_336
VSS_337
VSS_338
VSS_339
VSS_340
VSS_341
VSS_342
VSS_343
VSS_344
VSS_345
VSS_346
VSS_347
VSS_348
VSS_349
VSS_350
VSS_351
VSS_352
VSS_353
VSS_354
VSS_355
VSS_356
VSS_357
VSS_358

VSS_359
VSS_360
VSS_361
VSS_362

VSS_NCTF_1
VSS_NCTF_2
VSS_NCTF_3
VSS_NCTF_4
VSS_NCTF_5
VSS_NCTF_6
VSS_NCTF_7
VSS_NCTF_8
VSS_NCTF_9

VSS_SCB_1
VSS_SCB_2
VSS_SCB_3
VSS_SCB_4
VSS_SCB_5
VSS_SCB_6
VSS_SCB_7

2

AM8
AK8
AH8
AF8
AD8
AB8
Y8
V8
P8
M8
K8
H8
BJ7
E7
BF6
BC5
BA5
AW5
AU5
AR5
AN5
AL5
AJ5
AG5
AE5
AC5
AA5
W5
U5
N5
L5
J5
G5
C5
BH4
BE3
U3
E3
BC1
AW1
AR1
AL1
AG1
AC1
W1
N1
J1
AU43
BB42
AW38
BA35
L29
N28
N22
N20
N14
AL13
B10
AN13

N42
N40
N38
M39

AJ38
AH38
AD38
AC38
T35
R35
AT32
AR32
U32
R32
T28
R28
AT25
AR25
T24
R24
AN19
AJ19
AA19
Y19
T19
R19
AN18

BL55
BL1
A55
D1
B55
B2
A4

MCHGND1

R222 0_0402_5%@

MCHGND2

R224 0_0402_5%@

MCHGND3

R225 0_0402_5%@
R25 0_0402_5%

MCHGND4

R228 0_0402_5%@

1 2
1 2
1 2

1 2
1 2

1

R270

1 2

MCHGND1

Q68

RHU002N06_SOT323

100K_0402_5%

2

G

13

D

S

5

CRACK_BGA

R396

1 2

MCHGND2

Q69

RHU002N06_SOT323

CRACK_BGA

100K_0402_5%

13

D

2

G

S

R397

1 2

MCHGND3

Q70

RHU002N06_SOT323

100K_0402_5%

2

G

13

D

S

4

CRACK_BGA

R398

1 2

MCHGND4

Q71

RHU002N06_SOT323

100K_0402_5%

2

G

13

D

S

CRACK_BGA

CRACK_BGA 23,33

Security Classification

Issued Date

THIS SHEET OF EN GINEE RING D RAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR DISCLO SED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/02/13 2006/03/10

Compal Secret Data

Deciphered Date

2

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

Cantiga(6/6)-PWR/GND

LA-4021P

1

of

13 45Monday, October 29, 2007

0.1

电 脑 维 修 网

http://www.dnfix.cn/bbs

伟 力 电 脑 医 院

技术支持：252670528

5

DDR_A_DQS#[0..7]9

DDR_A_D[0..63]9

DDR_A_DM[0..7]9

DDR_A_DQS[0..7]9

DDR_A_MA[0..14]9

D D

Layout Note:
Place near JP36

+1.8V

Change C131 to 330uF. 9/26

2.2U_0805_16V4Z

1

C131

+

2

330U_D2E_2.5VM_R9

C C

Layout Note:
Place one cap close to every 2 pullup
resistors terminated to +0.9V

+0.9V

0.1U_0402_16V4Z

1

2

C141

B B

2.2U_0805_16V4Z

C132

C133

1

1

2

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

2

2

C143

C142

DDR_A_MA5
DDR_A_MA8

DDR_A_MA1
DDR_A_MA3

DDR_CS0_DIMMA#
DDR_A_RAS#

DDR_A_BS0
DDR_A_MA10

A A

DDR_A_CAS#
DDR_A_WE#

DDR_CS1_DIMMA#
M_ODT1

DDR_A_MA11

1 4
2 3

1 4
2 3

1 4
2 3

1 4
2 3

1 4
2 3

2 3
1 4

1 2

5

2.2U_0805_16V4Z

2.2U_0805_16V4Z

1

2

C144

+0.9V

RP156_0404_4P2R_5%

RP356_0404_4P2R_5%

RP556_0404_4P2R_5%

RP756_0404_4P2R_5%

RP956_0404_4P2R_5%

RP1156_0404_4P2R_5%

R11756_0402_5%

C135

C134

1

1

2

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

2

2

C146

C145

14
23

RP2 56_0404_4P2R_5%

14
23

RP4 56_0404_4P2R_5%

14
23

RP6 56_0404_4P2R_5%

14
23

RP8 56_0404_4P2R_5%

14
23

RP10 56_0404_4P2R_5%

14
23

RP12 56_0404_4P2R_5%

14
23

RP13 56_0404_4P2R_5%

0.1U_0402_16V4Z

2.2U_0805_16V4Z
C136

1

2

0.1U_0402_16V4Z

1

2

C147

DDR_A_BS2
DDR_CKE0_DIMMA

DDR_A_MA6
DDR_A_MA7

DDR_A_MA9
DDR_A_MA12

DDR_A_MA2
DDR_A_MA4

DDR_A_BS1
DDR_A_MA0

DDR_A_MA13
M_ODT0

DDR_A_MA14
DDR_CKE1_DIMMA

0.1U_0402_16V4Z

C137

C138

1

1

2

2

0.1U_0402_16V4Z

1

2

C148

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

2

2

C150

C149

4

0.1U_0402_16V4Z

0.1U_0402_16V4Z

C139

C140

1

1

2

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

2

2

C152

C151

Layout Note:
Place these resistor
closely JP9,all
trace length Max=1.5"

4

3

DDR_A_D4
DDR_A_D1

DDR_A_DQS#0
DDR_A_DQS0

DDR_A_D2
DDR_A_D3

DDR_A_D8
DDR_A_D14

DDR_A_DQS#1
DDR_A_DQS1

DDR_A_D9
DDR_A_D15

DDR_A_D16
DDR_A_D17

DDR_A_DQS#2
DDR_A_DQS2

DDR_A_D18
DDR_A_D19

DDR_A_D29
DDR_A_D24

DDR_A_DM3

DDR_A_D26
DDR_A_D27

DDR_CKE0_DIMMA8

DDR_A_BS29

DDR_A_BS09

DDR_A_WE#9

DDR_A_CAS#9

DDR_CS1_DIMMA#8

0.1U_0402_16V4Z

1

2

C153

M_ODT18

ICH_SMBDATA15,16,22

ICH_SMBCLK15,16,22

Security Classification

Issued Date

THIS SHEET OF EN GINEE RING D RAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR DISCLO SED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

DDR_CKE0_DIMMA

DDR_A_BS2
DDR_A_MA12

DDR_A_MA9
DDR_A_MA8

DDR_A_MA5
DDR_A_MA3
DDR_A_MA1

DDR_A_MA10
DDR_A_BS0
DDR_A_WE#

DDR_A_CAS#
DDR_CS1_DIMMA#

M_ODT1
DDR_A_D37

DDR_A_D36
DDR_A_DQS#4

DDR_A_DQS4
DDR_A_D35

DDR_A_D32
DDR_A_D40

DDR_A_D44
DDR_A_DM5
DDR_A_D41

DDR_A_D46
DDR_A_D49

DDR_A_D48

DDR_A_DQS#6
DDR_A_DQS6

DDR_A_D54
DDR_A_D50

DDR_A_D61
DDR_A_D60

DDR_A_DM7
DDR_A_D59

+3VM

2006/02/13 2006/03/10

+1.8V +1.8V

JP36

1

VREF

3

VSS

5

DQ0

7

DQ1

9

VSS

11

DQS0#

13

DQS0

15

VSS

17

DQ2

19

DQ3

21

VSS

23

DQ8

25

DQ9

27

VSS

29

DQS1#

31

DQS1

33

VSS

35

DQ10

37

DQ11

39

VSS

41

VSS

43

DQ16

45

DQ17

47

VSS

49

DQS2#

51

DQS2

53

VSS

55

DQ18

57

DQ19

59

VSS

61

DQ24

63

DQ25

65

VSS

67

DM3

69

NC

71

VSS

73

DQ26

75

DQ27

77

VSS

79

CKE0

81

VDD

83

NC

85

BA2

87

VDD

89

A12

91

A9

93

A8

95

VDD

97

A5

99

A3

101

A1

103

VDD

105

A10/AP

107

BA0

109

WE#

111

VDD

113

CAS#

115

NC/S1#

117

VDD

119

NC/ODT1

121

VSS

123

DQ32

125

DQ33

127

VSS

129

DQS4#

131

DQS4

133

VSS

135

DQ34

137

DQ35

139

VSS

141

DQ40

143

DQ41

145

VSS

147

DM5

149

VSS

151

DQ42

153

DQ43

155

VSS

157

DQ48

159

DQ49

161

VSS

163

NC,TEST

165

VSS

167

DQS6#

169

DQS6

171

VSS

173

DQ50

175

DQ51

177

VSS

179

DQ56

181

DQ57

183

VSS

185

DM7

187

VSS

189

DQ58

191

DQ59

193

VSS

195

SDA

197

SCL

199

VDDSPD

1

1

C154

C155

2

2

2.2U_0603_6.3V6K

0.1U_0402_16V4Z

SO-DIMM A
4mm Height

Top side

Compal Secret Data

Deciphered Date

2

V_DDR_MCH_REF

2

VSS
DQ4
DQ5
VSS
DM0
VSS
DQ6
DQ7

VSS
DQ12
DQ13

VSS

DM1

VSS

CK0

CK0#

VSS
DQ14
DQ15

VSS

VSS
DQ20
DQ21

VSS

NC
DM2
VSS

DQ22
DQ23

VSS

DQ28
DQ29

VSS

DQS3#

DQS3

VSS

DQ30
DQ31

VSS

NC/CKE1

VDD

NC/A15
NC/A14

VDD

A11

A7
A6

VDD

A4
A2
A0

VDD

BA1

RAS#

S0#

VDD

ODT0

NC/A13

VDD

NC
VSS

DQ36
DQ37

VSS
DM4
VSS

DQ38
DQ39

VSS

DQ44
DQ45

VSS

DQS5#

DQS5

VSS

DQ46
DQ47

VSS

DQ52
DQ53

VSS

CK1

CK1#

VSS
DM6
VSS

DQ54
DQ55

VSS

DQ60
DQ61

VSS

DQS7#

DQS7

VSS

DQ62
DQ63

VSS

SA0
SA1

FOX_ASOA426-M2RN-7Fconn@

2

4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200

DDR_A_D6
DDR_A_D0

DDR_A_DM0
DDR_A_D5

DDR_A_D7
DDR_A_D13

DDR_A_D12
DDR_A_DM1

DDR_A_D11
DDR_A_D10

DDR_A_D20
DDR_A_D21

DDR_A_DM2
DDR_A_D23

DDR_A_D22
DDR_A_D28

DDR_A_D25
DDR_A_DQS#3

DDR_A_DQS3
DDR_A_D31

DDR_A_D30
DDR_CKE1_DIMMA

DDR_A_MA14
DDR_A_MA11

DDR_A_MA7
DDR_A_MA6

DDR_A_MA4
DDR_A_MA2
DDR_A_MA0

DDR_A_BS1
DDR_A_RAS#
DDR_CS0_DIMMA#

M_ODT0
DDR_A_MA13

DDR_A_D39
DDR_A_D38

DDR_A_DM4
DDR_A_D34

DDR_A_D33
DDR_A_D45

DDR_A_D43
DDR_A_DQS#5

DDR_A_DQS5
DDR_A_D47

DDR_A_D42
DDR_A_D52

DDR_A_D53

DDR_A_DM6
DDR_A_D51

DDR_A_D55
DDR_A_D57

DDR_A_D56
DDR_A_DQS#7

DDR_A_DQS7
DDR_A_D62DDR_A_D58

DDR_A_D63

12

R116

R115

10K_0402_5%

10K_0402_5%

12

2.2U_0805_16V4Z
C129

1

2

M_CLK_DDR0 8
M_CLK_DDR#0 8

PM_EXTTS#0 8

DDR_CKE1_DIMMA 8

DDR_A_BS1 9
DDR_A_RAS# 9
DDR_CS0_DIMMA# 8

M_ODT0 8

M_CLK_DDR1 8
M_CLK_DDR#1 8

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

DDRII-SODIMM SLOT

LA-4021P

1

C130

V_DDR_MCH_REF 8,15

14 45Monday, October 29, 2007

1

0.1

of

0.1U_0402_16V4Z

1

2

电 脑 维 修 网

http://www.dnfix.cn/bbs

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技术支持：252670528

5

DDR_B_DQS#[0..7]9

DDR_B_D[0..63]9
DDR_B_DM[0..7]9

DDR_B_DQS[0..7]9

DDR_B_MA[0..14]9

D D

Layout Note:
Place near JP34

+1.8V

Reserve C524. 9/26

2.2U_0805_16V4Z

1

C524

+

2

330U_D2E_2.5VM_R9

@

C C

B B

Layout Note:
Place one cap close to every 2 pullup
resistors terminated to +0.9V

+0.9V

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

2

C575

C567

C566

1

1

2

2

0.1U_0402_16V4Z

1

1

2

2

C577

C576

DDR_B_MA1
DDR_B_MA3

DDR_B_BS0
DDR_B_MA10

DDR_B_MA0
DDR_B_BS1

DDR_B_RAS#
DDR_CS2_DIMMB#

A A

DDR_B_CAS#
DDR_B_WE#

DDR_CS3_DIMMB# M_ODT2
M_ODT3

DDR_B_MA11

1 4
2 3

1 4
2 3

1 4
2 3

1 4
2 3

1 4
2 3

2 3
1 4

1 2

5

2.2U_0805_16V4Z

C568

C569

1

1

2

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

RP2256_0404_4P2R_5%

RP2456_0404_4P2R_5%

RP2656_0404_4P2R_5%

RP2856_0404_4P2R_5%

RP3056_0404_4P2R_5%

RP3256_0404_4P2R_5%

R8056_0402_5%

0.1U_0402_16V4Z

1

1

2

2

C579

C578

+0.9V

RP23 56_0404_4P2R_5%

RP25 56_0404_4P2R_5%

RP27 56_0404_4P2R_5%

RP29 56_0404_4P2R_5%

RP31 56_0404_4P2R_5%

RP33 56_0404_4P2R_5%

RP34 56_0404_4P2R_5%

2.2U_0805_16V4Z

2.2U_0805_16V4Z

0.1U_0402_16V4Z

2.2U_0805_16V4Z
C570

1

2

0.1U_0402_16V4Z

1

1

2

2

C581

C580

DDR_B_MA9

14

DDR_B_MA12

23

DDR_CKE3_DIMMB

14

DDR_B_MA14

23

DDR_B_MA5

14

DDR_B_MA8

23

DDR_B_MA7

14

DDR_B_MA6

23

DDR_B_MA4

14

DDR_B_MA2

23

14

DDR_B_MA13

23

DDR_B_BS2

14

DDR_CKE2_DIMMB

23

0.1U_0402_16V4Z

C571

C572

1

1

2

2

1

2

C582

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

2

2

C583

0.1U_0402_16V4Z

4

0.1U_0402_16V4Z

0.1U_0402_16V4Z

C584

C574

C573

1

1

2

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

2

2

C585

C586

Layout Note:
Place these resistor
closely JP10,all
trace length Max=1.5"

4

3

DDR_B_D57
DDR_B_D56

DDR_B_DQS#7
DDR_B_DQS7

DDR_B_D58
DDR_B_D63

DDR_B_D48
DDR_B_D49

DDR_B_DQS#6
DDR_B_DQS6

DDR_B_D51
DDR_B_D50

DDR_B_D40
DDR_B_D44

DDR_B_DQS#5
DDR_B_DQS5

DDR_B_D42

DDR_B_D37
DDR_B_D32

DDR_B_DM4

DDR_B_D39

DDR_CKE2_DIMMB8

DDR_B_BS29

DDR_B_BS09
DDR_B_WE#9

DDR_B_CAS#9

0.1U_0402_16V4Z

1

2

C587

DDR_CS3_DIMMB#8

M_ODT38

ICH_SMBDATA14,16,22

ICH_SMBCLK14,16,22

Security Classification

Issued Date

THIS SHEET OF EN GINEE RING D RAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR DISCLO SED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

DDR_CKE2_DIMMB

DDR_B_BS2
DDR_B_MA12

DDR_B_MA9
DDR_B_MA8

DDR_B_MA5
DDR_B_MA3
DDR_B_MA1

DDR_B_MA10
DDR_B_BS0
DDR_B_WE#

DDR_B_CAS#
DDR_CS3_DIMMB#

M_ODT3
DDR_B_D30

DDR_B_D27
DDR_B_DQS#3

DDR_B_DQS3
DDR_B_D25

DDR_B_D28
DDR_B_D23

DDR_B_D22
DDR_B_DM2
DDR_B_D17

DDR_B_D16
DDR_B_D11

DDR_B_D10

DDR_B_DQS#1
DDR_B_DQS1

DDR_B_D12 DDR_B_D13

DDR_B_D2
DDR_B_D3

DDR_B_DM0
DDR_B_D0

DDR_B_D5

+3VM +3VM

2006/02/13 2006/03/10

+1.8V +1.8V

JP3

1

VREF

3

VSS

5

DQ0

7

DQ1

9

VSS

11

DQS0#

13

DQS0

15

VSS

17

DQ2

19

DQ3

21

VSS

23

DQ8

25

DQ9

27

VSS

29

DQS1#

31

DQS1

33

VSS

35

DQ10

37

DQ11

39

VSS

41

VSS

43

DQ16

45

DQ17

47

VSS

49

DQS2#

51

DQS2

53

VSS

55

DQ18

57

DQ19

59

VSS

61

DQ24

63

DQ25

65

VSS

67

DM3

69

NC

71

VSS

73

DQ26

75

DQ27

77

VSS

79

CKE0

81

VDD

83

NC

85

BA2

87

VDD

89

A12

91

A9

93

A8

95

VDD

97

A5

99

A3

101

A1

103

VDD

105

A10/AP

107

BA0

109

WE#

111

VDD

113

CAS#

115

NC/S1#

117

VDD

119

NC/ODT1

121

VSS

123

DQ32

125

DQ33

127

VSS

129

DQS4#

131

DQS4

133

VSS

135

DQ34

137

DQ35

139

VSS

141

DQ40

143

DQ41

145

VSS

147

DM5

149

VSS

151

DQ42

153

DQ43

155

VSS

157

DQ48

159

DQ49

161

VSS

163

NC,TEST

165

VSS

167

DQS6#

169

DQS6

171

VSS

173

DQ50

175

DQ51

177

VSS

179

DQ56

181

DQ57

183

VSS

185

DM7

187

VSS

189

DQ58

191

DQ59

193

VSS

195

SDA

197

SCL

199

VDDSPD

0.1U_0402_16V4Z

SUYIN_600008FB200G103ZL

SO-DIMM B

REVERSE

Bottom side

1

C588

2

1

C589

2

2.2U_0603_6.3V6K

Compal Secret Data

Deciphered Date

VSS
DQ4
DQ5
VSS
DM0
VSS
DQ6
DQ7

VSS
DQ12
DQ13

VSS

DM1

VSS

CK0

CK0#

VSS
DQ14
DQ15

VSS

VSS
DQ20
DQ21

VSS

DM2

VSS
DQ22
DQ23

VSS
DQ28
DQ29

VSS

DQS3#

DQS3

VSS
DQ30
DQ31

VSS

NC/CKE1

VDD

NC/A15
NC/A14

VDD

VDD

VDD

RAS#

VDD
ODT0

NC/A13

VDD

VSS
DQ36
DQ37

VSS

DM4

VSS
DQ38
DQ39

VSS
DQ44
DQ45

VSS

DQS5#

DQS5

VSS
DQ46
DQ47

VSS
DQ52
DQ53

VSS

CK1

CK1#

VSS

DM6

VSS
DQ54
DQ55

VSS
DQ60
DQ61

VSS

DQS7#

DQS7

VSS
DQ62
DQ63

VSS

SAO

2

V_DDR_MCH_REF

2

DDR_B_D60

4

DDR_B_D61

6
8

DDR_B_DM7

10
12

DDR_B_D62

14

DDR_B_D59

16
18

DDR_B_D52

20

DDR_B_D53

22
24

DDR_B_DM6

26
28
30
32
34

DDR_B_D54

36

DDR_B_D55

38
40

42

DDR_B_D45

44

DDR_B_D41

46
48
50

NC

A11

A7
A6

A4
A2

A0
BA1
S0#

NC

SA1

2

52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200

DDR_B_DM5
DDR_B_D46

DDR_B_D43DDR_B_D47
DDR_B_D36

DDR_B_D33
DDR_B_DQS#4

DDR_B_DQS4
DDR_B_D34

DDR_B_D38DDR_B_D35
DDR_CKE3_DIMMB

DDR_B_MA14
DDR_B_MA11

DDR_B_MA7
DDR_B_MA6

DDR_B_MA4
DDR_B_MA2
DDR_B_MA0

DDR_B_BS1
DDR_B_RAS#
DDR_CS2_DIMMB#

M_ODT2
DDR_B_MA13

DDR_B_D26
DDR_B_D31

DDR_B_DM3
DDR_B_D24

DDR_B_D29
DDR_B_D18

DDR_B_D19
DDR_B_DQS#2

DDR_B_DQS2
DDR_B_D21

DDR_B_D20
DDR_B_D14

DDR_B_D15

DDR_B_DM1

DDR_B_D8DDR_B_D9
DDR_B_D7

DDR_B_D6
DDR_B_DQS#0

DDR_B_DQS0
DDR_B_D1

DDR_B_D4

10K_0402_5%

12

R77

R73

1 2

10K_0402_5%

Title

Size Document Number Rev

Date: Sheet

0.1U_0402_16V4Z

2.2U_0805_16V4Z
C564

1

1

2

2

M_CLK_DDR3 8
M_CLK_DDR#3 8

PM_EXTTS#1 8

DDR_CKE3_DIMMB 8

DDR_B_BS1 9
DDR_B_RAS# 9
DDR_CS2_DIMMB# 8

M_ODT2 8

M_CLK_DDR2 8
M_CLK_DDR#2 8

Compal Electronics, Inc.

DDRII-SODIMM SLOT

LA-4021P

C565

1

V_DDR_MCH_REF 8,14

15 45Monday, October 29, 2007

1

0.1

of

电 脑 维 修 网

http://www.dnfix.cn/bbs

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5

PCI

CLKSEL1

FSLA

CLKSEL0

MHz

FSLC1FSLB

CLKSEL2

CPU

010002660 33.3

1

0

1

D D

FSA

R128 2.2K_0402_5%

CPU_BSEL05

C C

CPU_BSEL15

FSC

B B

CPU_BSEL25

R143 10K_0402_5%

200

166

12

1 2

R130 0_0402_5%

FSB

1 2

R139
0_0402_5%

9/20

12

1 2

R145 0_0402_5%

SRC

FSB

MHz

MHz

1066

800

1000

667

100

+VCCP

R127

56_0402_5%@

1 2

1 2

R129 1K_0402_5%

12

R131

1K_0402_5%@

+VCCP

R137

1K_0402_5%@

R138

1 2

1K_0402_5%

1 2

12

R62

0_0402_5%@

1 2

R144 1K_0402_5%

12

R146

0_0402_5%@

MHz

33.30

33.3

MCH_CLKSEL1 8

Add for PCIE
port80 debug
port. 10/18.

MCH_CLKSEL2 8

14.31818MHZ_20P_1BX14318BE1A

A A

CLK_XTAL_OUT

CLK_XTAL_IN

Y1

12

2

2

C178

C17733P_0402_50V8J

33P_0402_50V8J

1

1

5

9/149/14

+3VS

R147
10K_0402_5%

1 2

R150

@

10K_0402_5%

1 2

4

+3VM

1 2

R118 0_1206_5%

MCH_CLKSEL0 8

CLK_PCI_139427

CLK_PCI_TCG32
CLK_PCI_EC33

CLK_PCI_DEBUG26

CLK_PCI_DB32

CLK_PCI_ICH20

CLK_48M_ICH22

CLK_14M_ICH22
CLK_14M_KBC33

+3VS +3VS

R148

@

10K_0402_5%

1 2

27_SELITP_EN

R151
10K_0402_5%

1 2

4

3

+3VM_CK505

CLK_PCI_1394
CLK_PCI_TCG
CLK_PCI_EC PCI_CLK3

CLK_PCI_DB
CLK_PCI_ICH

1 2

1 2

CLK_48M_ICH

CLK_14M_ICH
CLK_14M_KBC

R149
10K_0402_5%

PCI2_TME

R152

@

10K_0402_5%

1

2

C158

10U_0805_10V4Z

CLKREQ#_B_R
CLKREQG_WWAN#_R

0.1U_0402_16V4Z

1

2

C159

1 2
1 2
1 2

1 2
1 2
1 2

1

1

2

2

C160

C161

0.1U_0402_16V4Z

0.1U_0402_16V4Z

R120 475_0402_1%
R121 475_0402_1%

9/14

+1.05VM_CK505

R13222_0402_5%
R13322_0402_5%
R13433_0402_1%

R33833_0402_1%@
R13533_0402_1%
R13633_0402_1%

1 2

1 2
1 2

Security Classification

1

2

C162

0.1U_0402_16V4Z

+3VM_CK505

+1.05VM_CK505

PCI2_TME

27_SEL
ITP_EN

CLK_XTAL_IN
CLK_XTAL_OUT

FSA

R14033_0402_1%

FSB

FSC

R14133_0402_1%
R14233_0402_1%

1

2

C163

0.1U_0402_16V4Z

12
12

Issued Date

THIS SHEET OF EN GINEE RING D RAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR DISCLO SED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

+1.05VM_CK505+1.05VM

1 2

R58 0_1206_5%

1

2

C164

0.1U_0402_16V4Z

R119 10K_0402_5%

1 2

R122 10K_0402_5%

1 2

U5

6

VDDREF

12

VDDPCI

19

VDD48

23

VDD96_IO

27

VDDPLL3

55

VDDSRC

72

VDDCPU

31

VDDPLL3_IO

38

VDDSRC_IO

52

VDDSRC_IO

62

VDDSRC_IO

66

VDDCPU_IO

13

PCI

14

PCI2/TME

15

PCI3

16

PCI4/27_Select

17

PCI_F5/ITP_EN

5

X1

4

X2

20

USB_48MHz/FSLA

2

FSLB/TEST_MODE

7

FSLC/TEST_SEL/REF0

59

GNDSRC

18

GNDPCI

22

GND48

26

GND

30

GND

69

GNDCPU

34

GNDSRC

42

GNDSRC

3

GNDREF

ICS9LPRS397AKLFT_MLF72

2006/02/13 2006/03/10

CPUT2_ITP_LPR/SRCT8_LPR
CPUC2_ITP_LPR/SRCC8_LPR

27MHz_NonSS/SRCT1_LPR/SE1

Compal Secret Data

CLKREQ#_B 8
CLKREQG_WWAN# 26 CLKREQ_WLAN# 26

CPU_STOP#

CPUT0_LPR_F

CPUC0_LPR_F

CPUT1_LPR_F

CPUC1_LPR_F

SRCT7_LPR
SRCC7_LPR

SRCT6_LPR
SRCC6_LPR

SRCT10_LPR
SRCC10_LPR

SRCT11_LPR
SRCC11_LPR

SRCT9_LPR
SRCC9_LPR

SRCT4_LPR
SRCC4_LPR

SRCT3_LPR
SRCC3_LPR

SRCT2_LPR/SATAT_LPR
SRCC2_LPR/SATAC_LPR

SRCT0_LPR/DOTT_96_LPR

SRCC0_LPR/DOTC_96_LPR

27MHz_SS/SRCC1_LPR/SE2

CK_PWRGD/PD#

+3VS

+3VS

SCLK

SDATA

PCI_STOP#

CR7#

CR#6

CR10#

CR#11

CR#9

CR#4

CR#3

CR#A

REF1

1

2

C171

10U_0805_10V4Z

0.1U_0402_16V4Z

11

NC

10
9

54
53

71
70

68
67

CLKREQ#_B_R

65
64

63
61

60
58
57

56
49
50

51
46
48

47
43
44

45

41
39

40
37
35

36

32
33

24
25

28
29

1

21

8

Deciphered Date

2

1

1

2

2

C173

C172

CLKREQ_WLAN#_R

CLKREQG_WWAN#_R

CLKSATAREQ#_R

10U_0805_10V4Z

0.1U_0402_16V4Z

CLKREQ_WLAN#_R
CLKSATAREQ#_R

CLK_CPU_BCLK 4
CLK_CPU_BCLK# 4

CLK_MCH_BCLK 8
CLK_MCH_BCLK# 8

R_CPU_XDP
R_CPU_XDP#

CLK_MCH_3GPLL 8
CLK_MCH_3GPLL# 8

CLK_PCIE_MCARD 26
CLK_PCIE_MCARD# 26

CLK_PCIE_WAN 26
CLK_PCIE_WAN# 26

CLK_PCIE_EXP 26
CLK_PCIE_EXP# 26

R_PCIE_ICH
R_PCIE_ICH#

CLK_PCIE_SATA 21
CLK_PCIE_SATA# 21

CLK_MCH_DREFCLK 8
CLK_MCH_DREFCLK# 8

MCH_SSCDREFCLK 8
MCH_SSCDREFCLK# 8

CK_PWRGD 22

1

C156
C157
C165

1

2

C174

1

1

2

2

C175

C176

0.1U_0402_16V4Z

0.1U_0402_16V4Z

C166
C167
C168
C169
C170

Place close to U5

R123 10K_0402_5%

R124 475_0402_1%
R125 475_0402_1%

ICH_SMBCLK 14,15,22
ICH_SMBDATA 14,15,22

H_STP_PCI# 22
H_STP_CPU# 22

RP14 0_0404_4P2R_5%

CLKREQA# 26

RP35 0_0404_4P2R_5%

12
12

1 4
2 3

2 3
1 4

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

CLOCK GENERATOR

LA-4021P

1 2

R126 10K_0402_5%

1 2

CLK_CPU_XDP 4
CLK_CPU_XDP# 4

CLK_PCIE_ICH 22
CLK_PCIE_ICH# 22

1

CLK_48M_ICH

12

5P_0402_50V8C@

CLK_14M_ICH

12

4.7P_0402_50V8C@

CLK_PCI_ICH

12

4.7P_0402_50V8C@

CLK_14M_KBC

12

4.7P_0402_50V8C@

CLK_PCI_EC

12

4.7P_0402_50V8C@

CLK_PCI_TCG

12

4.7P_0402_50V8C@

CLK_PCI_1394

12

5P_0402_50V8C@

CLK_PCI_DB

12

5P_0402_50V8C@

CLKSATAREQ# 22

16 45Monday, October 29, 2007

+3VS

+3VS

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A

CRT Connector

12

1 1

+5VS

C186

0.1U_0402_16V4Z

1

5

P

R16251K_0402_5%

1 2

A2Y

3

R16351K_0402_5%

OE#

G

CRT_HSYNC10

CRT_VSYNC10

2 2

1 2

D_RED
D_GREEN
D_BLUE

R15475_0402_5%

R15575_0402_5%

R15375_0402_5%

12

12

D_RED10

D_GREEN10

D_BLUE10

+5VS

C187

0.1U_0402_16V4Z

1 2

U6
SN74AHCT1G125GW_SOT353-5

4

1 2

1

5

P

4

OE#

A2Y

G

U7
SN74AHCT1G125GW_SOT353-5

3

L

B

Place cloce to GMCH

L

L2

1

C181

2

1

C182

2

10P_0402_50V8J

5P_0402_50V8C@

BK1608LL560-T 0603

1 2

L3
BK1608LL560-T 0603

1 2

L4
BK1608LL560-T 0603

1 2

10P_0402_50V8J

1

C188

2

1

C183

2

1

C189

2

D_RED

D_GREEN

D_BLUE

1

C180

2

10P_0402_50V8J

HSYNC D_HSYNC

R156 0_0603_5%

1 2

VSYNC D_ VSYNC

R161 0_0603_5%

1 2

Place cloce to GMCH

C

F1

1.1A_6VDC_FUSE

BLUE_R34

GREEN_R34

RED_R34

L17
0_0805_5%

1 2

L18
0_0805_5%

1 2

L19
0_0805_5%

1 2

1

1

C184

C185

2

2

10P_0402_50V8J

10P_0402_50V8J

5P_0402_50V8C@

layout note: D_HSYNC
& D_VSYNC should be
routed to docking
connector then to VGA
connector

10P_0402_50V8J

21

D_HSYNC 34

D_VSYNC 34

D_DDCDATA34

D_DDCCLK34

D2
CH491D_SC59

2 1

C179

0.1U_0402_16V4Z

1

2

RED

GREEN

BLUE

+CRTVDD+RCRT_VCC+5VS

W=40mils

JP4

6

11

1
7

12

2
8

13

3
9

14

16

4

17
10
15

5

+CRTVDD

12

12

R157

2.2K_0402_5%

R158

2.2K_0402_5%

Place cloce to GMCH

L

CONN@

SUYIN_070546FR015S235ZR_15P

D

BLUE34

GREEN34

RED34

1 3

D

Q2

BSS138_SOT23

BSS138_SOT23

2

G

1 3

D

Q3

S

BLUE
GREEN
RED
D_HSYNC
D_VSYNC

2

G

S

+3VS

1 2

R159

2.2K_0402_5%

D3

1

2

3

DAN217T146_SC59-3

@

D5

D4

1

2

3

DAN217T146_SC59-3

@

D6

1

1

2

3

2

DAN217T146_SC59-3

@

10/25

RED_R, GREEN _ R , & BLUE_R should
still be con n e c te d to output of RGB
filter (L17-2, L18-2, L19-2). JP4
pins should o n l y connect to RED,
GREEN, & BLUE.

1 2

R160

2.2K_0402_5%

CRT_DDC_DATA 10

CRT_DDC_CLK 10

E

D7

1

3

DAN217T146_SC59-3

@

+CRTVDD

2

3

DAN217T146_SC59-3

@

3 3

4 4

A

B

Security Classification

Issued Date

THIS SHEET OF EN GINEE RING D RAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR DISCLO SED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2006/02/13 2006/07/26

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

D

Date: Sheet

Compal Electronics, Inc.

CRT Connector

LA-4021P

17 45Monday, October 29, 2007

E

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5

D D

ENABLT10

C C

+3VS +5VS

R165

4.7K_0402_5% 1 2

R164

4.7K_0402_5% 1 2

G

2

13

D

S

Q4

2N7002_SOT23

R81
100K_0402_1%

1 2

HP request. (9/4)

4

LCDVDD

DISPLAYOFF#

LCD/PANEL BD. CONN.

B+_LCD

C190 0.1U_0603_50V4Z

12

C191 68P_0402_50V8J

12

L5 0_0805_5%

1 2

B+

+3VS

ALS_EN22

BLON_PWM10

+5VS_KB

+5V_WEBCAM

USB20_P1022
USB20_N1022

JP5

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

3132

ACES_88242-3001_30P

CONN@

3

TXOUT_L0- 10
TXOUT_L0+ 10

TXOUT_L1- 10
TXOUT_L1+ 10

TXOUT_L2- 10
TXOUT_L2+ 10

TXCLK_L- 10
TXCLK_L+ 10

+3VS

R872.2K_0402_5%

R882.2K_0402_5%

HP request. (9/4)

1 2

1 2

WEBCAM_ON/OFF#22

LID_SW#19,22,33

DDC2_CLK 10
DDC2_DATA 10

DISPLAYOFF#

2

+3VALW

1 2

D41

2
3

DAP202U_SOT323-3

R601
10K_0402_5%

1

+5VS

R598

2

G

10K_0402_5%

R493

1 2

220K_0402_1%

1 2

Q65

13

D

RHU002N06_SOT323

S

Q5
SI2301BDS_SOT23

S

G

2

9/14

1

C562

2

R599
10K_0402_5%

1 2

1

+5VALW +5V_WEBCAM

1U_0603_10V4Z

1

C559

2

1 2

R600

100K_0402_5%

1 2

R602 47K_0402_5%

13

D

2

G

0.1U_0402_16V4Z

Q7

S

RHU002N06_SOT323

D

13

+5VALW

G

2

1

C313

2

0.01U_0402_16V7K

Add for slow Q64
on.9/14

Q64

S

BSS84LT1G_SOT23-3

D

1 3

1U_0603_10V4Z

1

C558

2

1

C560

C561

2

0.1U_0402_16V4Z

4.7U_0805_10V4Z

+5VS_KB

1

2

LCD POWER CIRCUIT

LCDVDD

R169

12

R166
100_0402_1%

13

D

Q41

1 2

R168 47K_0402_5%

2

G

S

1

OUT

2

IN

GND

3

1 2

0.1U_0402_16V4Z

Q8
DTC124EKAT146_SC59-3

B B

RHU002N06_SOT323

ENAVDD10

A A

100K_0402_1%

5

4

LCDVDD

Q6

D

S

AO3413_SOT23

1 3

G

2

R167 1M_0402_5%

1 2

C192 0.1U_0402_16V7K

1

2

1

C194

4.7U_0805_10V4Z

2

C193

Security Classification

Issued Date

THIS SHEET OF EN GINEE RING D RAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR DISCLO SED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

1 2

2005/03/10 2006/03/10

Compal Secret Data

J8

2 1

PAD-SHORT 2x2m

J9

2 1

PAD-No SHORT 2x2m

1

C195

4.7U_0805_10V4Z@

2

Deciphered Date

+3VS

+3VALW

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

LCD CONN & Q-Switch & GPIO Ext.

LA-4021P

1

of

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5

4

3

2

1

D D

WL/BT_LED30

BT_LED31

C C

WL/BT_LED

BT_LED

WL_LED

BT_LED

WL_LED

+3VS

9/14

12

R570
47K_0402_5%

13

D

S

2

G

1 2

1 2

Q10
2N7002_SOT23

13

D

Q11
2N7002_SOT23

S

2

G

R170 100K_0402_5%

R171 100K_0402_5%

+3VS

47K

10K

1 3

WW_LED#26

Q9
DTA114YKAT146_SOT23-3

2

WL_LED

2

10K

+3VS

WL_LED# 26

13

Q79
DTA114YKAT146_SOT23-3

47K

Add in 9/26

Cause space issue, move them from LED board to M/B. 10/09

+3VS

Q32

DTA114YKAT146_SOT23-3

13

HDD_HALTLED22

B B

HDD_HALTLED

100K_0402_5%

R334

@

D

Q80

2

G

2N7002_SOT23

S

12

47K

10K

2

1 3

AMBER_BATLED#33

GREEN_BATLED#33

IDE_LED#21

STB_LED30,34

To LED BOARD

+3VS+3VL+5VS

AMBER_BATLED#
GREEN_BATLED#
IDE_LED#
HDD_STP#
STB_LED
WL/BT_LED

To LID switch Board

JP6

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

11

GND

12

GND

ACES_85201-1005NCONN@

LID_SW#18,22,33

+3VS

JP8

1

1

2

4

2

G1

3

5

3

G2

ACES_85204-03001CONN@

A A

5

4

Security Classification

Issued Date

THIS SHEET OF EN GINEE RING D RAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR DISCLO SED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/02/13 2006/03/10

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

Compal Electronics, Inc.

LEDS & LID

LA-4021P

1

0.1

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5

+3VS

1 2

R172 8.2K_0402_5%

1 2
1 2
1 2
1 2
1 2
1 2
1 2

1 2
1 2
1 2
1 2
1 2
1 2
1 2

1 2
1 2
1 2
1 2

12

R173 8.2K_0402_5%
R174 8.2K_0402_5%

D D

C C

R175 8.2K_0402_5%
R176 8.2K_0402_5%
R177 8.2K_0402_5%
R178 8.2K_0402_5%
R179 8.2K_0402_5%

+3VS

R180 8.2K_0402_5%
R181 8.2K_0402_5%
R182 8.2K_0402_5%
R183 8.2K_0402_5%
R184 8.2K_0402_5%
R185 47K_0402_5%
R186 8.2K_0402_5%
R187 8.2K_0402_5%
R188 8.2K_0402_5%
R189 8.2K_0402_5%
R191 8.2K_0402_5%
R192 8.2K_0402_5%

PCI_DEVSEL#
PCI_STOP#
PCI_TRDY#
PCI_FRAME#
PCI_PLOCK#
PCI_IRDY#
PCI_SERR#
PCI_PERR#

PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#
PCI_PIRQE#
ODD_DET#
PCI_PIRQG#
PCI_PIRQH#
PCI_REQ0#
PCI_REQ1#
PCI_REQ2#
PCI_REQ3#

PCI_AD[0..31]27

Change to ODD_DET#. 10/18

4

PCI_AD0
PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD6
PCI_AD7
PCI_AD8
PCI_AD9
PCI_AD10
PCI_AD11
PCI_AD12
PCI_AD13
PCI_AD14
PCI_AD15
PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20
PCI_AD21
PCI_AD22
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30
PCI_AD31

PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#

U8B

A11

AD0

B12
A10
C12

A8
A12
E10
C11

B9

D8

A4

E8

A3

D9
C8
C2
D7

B3
D11

B6

D5
D3

F4

E3

E4

B2

C4
C1
D1

E2

J4

H2

F1

F5

F2

PCI

AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31

Interrupt I/F

PIRQA#
PIRQB#
PIRQC#
PIRQD#C7PIRQH#/GPIO5

ICH9-M SFF ES_FCBGA56 9

REQ0#

GNT0#
REQ1#/GPIO50
GNT1#/GPIO51
REQ2#/GPIO52
GNT2#/GPIO53
REQ3#/GPIO54
GNT3#/GPIO55

C/BE0#
C/BE1#
C/BE2#
C/BE3#

IRDY#

PAR

PCIRST#

DEVSEL#

PERR#

PLOCK#

SERR#

STOP#

TRDY#

FRAME#

PLTRST#

PCICLK

PME#

PIRQE#/GPIO2
PIRQF#/GPIO3

PIRQG#/GPIO4

3

G4
E1
A9
E12
B11
C10
D6
C6

D10
A5
E6
C9

C3
B1
T3
A7
D4
C5
H5
A6
A2
B8

A21
B5
T1

G3
G1
F3
H4

PCI_REQ0#
PCI_GNT0#
PCI_REQ1#

PCI_REQ2#
PCI_REQ3#

PCI_GNT3#
PCI_CBE#0

PCI_CBE#1
PCI_CBE#2
PCI_CBE#3

PCI_IRDY#
PCI_PAR
PCI_RST#
PCI_DEVSEL#
PCI_PERR#
PCI_PLOCK#
PCI_SERR#
PCI_STOP#
PCI_TRDY#
PCI_FRAME#

PLT_RST#
CLK_PCI_ICH
PCI_PME#

PCI_PIRQE#
ODD_DET#
PCI_PIRQG#
PCI_PIRQH#

T113 PAD

PCI_CBE#0 27
PCI_CBE#1 27
PCI_CBE#2 27
PCI_CBE#3 27

PCI_IRDY# 27
PCI_PAR 27
PCI_RST# 26,27
PCI_DEVSEL# 27
PCI_PERR# 27

PCI_SERR# 27,33
PCI_STOP# 27
PCI_TRDY# 27
PCI_FRAME# 27

PLT_RST# 8,26,32
CLK_PCI_ICH 16
PCI_PME# 26

R190 0_0402_5%

12

PCI_REQ2# 27
PCI_GNT2# 27

PCI_PIRQE# 27
ODD_DET# 21

PCI_PIRQG# 27

ACCEL_INT# 26

2

1

B B

PCI_GNT3#

A16 swap override Strap

Low= A16 swap override Enble
High= Default

PCI_GNT3#

*

12

R194

1K_0402_5% @

A A

Boot BIOS Strap

PCI_GNT0# SPI_CS#1

12

R195
1K_0402_5%

1

0

1

0

1

1

PCI_GNT0#

DEL J3. 9/29

Boot BIOS Location

SPI

*

PCI

LPC

KBC_SPI_CS1#22

Security Classification

Issued Date

THIS SHEET OF EN GINEE RING D RAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED B Y OR DISCLO SED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

Place closely pin B10

CLK_PCI_ICH

12

R196

1K_0402_5%@

2006/02/13 2006/03/10

12

@

R193
10_0402_5%

1

@

C196

8.2P_0402_50V

2

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

2

Date: Sheet

Compal Electronics, Inc.

ICH9(1/4)-PCI/INT

LA-4021P

20 45Monday, October 29, 2007

1

0.1

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+RTCVCC

1 2

R197 330K_0402_1%

1 2

R198 1M_0402_5%

1 2

R199 330K_0402_1%

1 2

R200 20K_0402_5%

Change from 180K to 20K
& 0.1u to 1u. 9/29

D D

5

LAN100_SLP
SM_INTRUDER#
ICH_INTVRMEN
ICH_SRTCRST#

C197

1U_0603_10V4Z

1

2

@

1 2

0_0402_5%

0_0402_5%

@

1 2

R202

R201

4

3

2

1

ICH_RSVD HDA_SDOUT_CODEC

00
0
1
11

XOR CHAIN ENTRANCE STRAP:RSVD

+3VS

1 2

R206 1K_0402_5%@

1 2

R208 1K_0402_5%@

HDA_BITCLK

12

@

C C

SATA CD-ROM Connector

B B

JP9
OCTEK_SAT-22DE1G_NR SUYIN_127059

R227
10_0402_5%

1

@

C199
10P_0402_25V8K

2

1

GND

2

A+

3

A-

4

GND

5

B-

6

B+

7

GND

R357 0_0402_5%

8

DP

9

V5

10

V5

11

MD

12

GND

13

GND

1
0

AC97_SDOUT
ICH_RSVD

-*

SATA_TXP1
SATA_TXN1

SATA_RXN1

C204 0.01U_0402_50V7K

SATA_RXP1

C205 0.01U_0402_50V7K

Install. 10/03

1 2

+5VS

+5VS +5VS

A A

C220

C219

1

1

2

2

10U_0805_10V4Z

0.1U_0402_16V4Z

Place component's
closely SATA

L

CONN.(JP9)

C222

C221

1

1

2

2

0.1U_0402_16V4Z

5

Description

FR022S305ZL

1 2
1 2

RV

XOR
Normal(D)
PCIE Bit1

ICH_RSVD 22

1

2

C593

0.1U_0402_16V4Z

+RTCVCC

BT_COMBO# no longer needed
for p-class. Delete signal
and R48. 10/12

AC97_SDOUT_MDC30

AC97_SDOUT_CODEC28

IDE_LED#19

SATA_RXN1_C
SATA_RXP1_C

ODD_DET# 20

R205
20K_0402_5%

1 2

1U_0603_10V4Z

AC97_BITCLK_MDC30

AC97_BITCLK_CODEC28

AC97_SYNC_CODEC28

AC97_SYNC_MDC30

AC97_RST#_CODEC28

AC97_RST#_MDC30

G_BATLED#33

+3VS

SATA_RXN0_C
SATA_RXP0_C

1

C198

AC97_SDIN028

AC97_SDIN130

12

CLRP1

SHORT PADS

2

+1.5VS

R229 10K_0402_5%

SATA_RXN0_C
SATA_RXP0_C
SATA_TXN0
SATA_TXP0

SATA_RXN1_C
SATA_RXP1_C
SATA_TXN1
SATA_TXP1

R220 24.9_0402_1%
R211 33_0402_5%
R212 33_0402_5%
R213 33_0402_5%
R214 33_0402_5%
R215 33_0402_5%
R217 33_0402_5%

Swap in 9/28

R219 33_0402_5%

1 2

R221 33_0402_5%

1 2

12

C200 0.01U_0402_50V7K

1 2

C201 0.01U_0402_50V7K

1 2

C202 0.01U_0402_50V7K

1 2

C203 0.01U_0402_50V7K

1 2

LAN_RSTSYNC24

1 2
1 2
1 2
1 2
1 2
1 2
1 2

GLAN_CLK24

LAN_RXD024
LAN_RXD124
LAN_RXD224

LAN_TXD024
LAN_TXD124
LAN_TXD224

1.8" SATA HDD CONN

SATA_TXP0
SATA_TXN0

C2080.01U_0402_50V7K

12

C2090.01U_0402_50V7K

12

+5VS

T50PAD

AC97_SDOUT

T114PAD

SATA_RXN0
SATA_RXP0

ICH_RTCX1
ICH_RTCX2

ICH_RTCRST#
ICH_SRTCRST#
SM_INTRUDER#

ICH_INTVRMEN
LAN100_SLP

GLAN_COMP

HDA_BITCLK
HDA_SYNC

HDARST#

SATA_TXN0_C
SATA_TXP0_C

SATA_TXN1_C
SATA_TXP1_C

U8A

F25

RTCX1

G25

RTCX2

G24

RTCRST#

C24

SRTCRST#

C23

INTRUDER#

E25

INTVRMEN

D25

LAN100_SLP

G22

GLAN_CLK

D14

LAN_RSTSYNC

A14

LAN_RXD0

D12

LAN_RXD1

B14

LAN_RXD2

D13

LAN_TXD0

C13

LAN_TXD1

A13

LAN_TXD2

D15

GPIO56

H22

GLAN_COMPI

H21

GLAN_COMPO

AE7

HDA_BIT_CLK

AB7

HDA_SYNC

AA7

HDA_RST#

AB6

HDA_SDIN0

AE6

HDA_SDIN1

AC6

HDA_SDIN2

AA5

HDA_SDIN3

AC7

HDA_SDOUT

AD8

HDA_DOCK_EN#/GPIO33

AB8

HDA_DOCK_RST#/GPIO34

AC9

SATALED#

AE14

SATA0RXN

AD14

SATA0RXP

AC15

SATA0TXN

AD15

SATA0TXP

AD13

SATA1RXN

AC13

SATA1RXP

AA14

SATA1TXN

AB14

SATA1TXP

ICH9-M SF F ES_FCBG A569

JP10

1

1

2

2

G1

3

3

4

4

G2

5

5

6

6

7

7

8

8

9

9

10

10

ACES_85205-10001CONN@

RTCLAN / GLAN

IHDA

SATA

11
12

C211

1

2

0.1U_0402_16V4Z

10U_0805_10V4Z

Place component's
closely SATA

L

CONN.(JP10)

4

C213

C212

1

2

0.1U_0402_16V4Z

C214

1

1

2

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

Security Classification

Issued Date

THIS SHEET OF EN GINEE RING D RAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR DISCLO SED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

FWH0/LAD0
FWH1/LAD1
FWH2/LAD2
FWH3/LAD3

FWH4/LFRAME#

LPCCPU

LDRQ0#

LDRQ1#/GPIO23

A20GATE

A20M#

DPRSTP#

DPSLP#

FERR#

CPUPWRGD

IGNNE#

INIT#

INTR

RCIN#

NMI

SMI#

STPCLK#

THRMTRIP#

TP11

SATA4RXN
SATA4RXP
SATA4TXN

SATA4TXP

SATA5RXN
SATA5RXP
SATA5TXN

SATA5TXP

SATA_CLKN
SATA_CLKP

SATARBIAS#

SATARBIAS

1 2

10M_0402_5%

C20612P_0402_50V8J

1

2

2006/02/13 2006/03/10

LPC_AD1

J3

LPC_AD2

K5

LPC_AD3

L3
J2
H1

J1

GATEA20

N3
AB23

H_DPRSTP_R#

AE23
AE24

H_FERR#_R

AD25
AE22
AD23
AE21

AD24

KB_RST#

L1
AD21

H_SMI#

AC21

H_STPCLK#

AC25

THRMTRIP_ICH#

AC23
AC22

AD12
AE12
AB12
AA12

AC11
AD11
AB10
AA10

CLK_PCIE_SATA#

AC16

CLK_PCIE_SATA

AB16
AD10

AE10

R231

C20712P_0402_50V8J

Y2

1

4

32.768KHZ_12.5P_1TJS125BJ2A251

1

IN

OUT

2

NC3NC

2

Compal Secret Data

T49 PAD

R230 24.9_0402_1%

Within 500 mils

ICH_RTCX1

ICH_RTCX2

+RTCVCC +3VL

Deciphered Date

LPC_AD0

H3

LPC_AD[0..3] 26,32,33

LPC_FRAME# 26,32,33

T111 PAD
T48 P AD

GATEA20 33
H_A20M# 4

R209 0_0402_5%

1 2

H_DPSLP# 5

R210 56_0402_5%

1 2

H_PWRGOOD 4,5
H_IGNNE# 4
H_INIT# 4

H_INTR 4

KB_RST# 33

H_NMI 4
H_SMI# 4

H_STPCLK# 4

R226 54.9_0402_1%

1 2

placed within 2" from
ICH9M

CLK_PCIE_SATA# 16
CLK_PCIE_SATA 16

1 2

R232 0_0402_5%

1 2

1

C210
1U_0603_10V4Z

2

2

9/27

for H_DPRSTP# &
H_DPSLP#.

H_DPRSTP# 5,8,42

H_FERR#

Place Close to U8.

+VCCP

12

R223
56_0402_5%

ZZZ1

PCB-MB

DAN202UT106_SC70-3

45@

D8

3

1

2

Title

Size Document Number Rev

Custom

Date: Sheet

9/27Del PU R203~R204

+1.05VM

R207
56_0402_5%

1 2

H_FERR# 4

GATEA20

R216 10K_0402_5%

KB_RST#

BATT1

1 2

R218 10K_0402_5%

1 2

H_THERMTRIP# 4,8

ML1220 MAXELL LITHIUM RTC BATTERY

R233
1K_0402_5%

RTC1

1 2

L

W=20mils

RTC2

1

+

SUYIN_060003FA002G202NLCONN@

Compal Electronics, Inc.

ICH9(2/4)_LAN,HD,IDE,LPC

LA-4021P

1

JBATT1

+3VS

2

-

-+

0.1

of

21 45Monday, October 29, 2007

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+3VS

Add R326 10K. 10/04

1 2

R326 10K_0402_5%

1 2

R234 10K_0402_5%

1 2

R237 8.2K_0402_5%

1 2

R242 8.2K_0402_5%@

1 2

R245 47K_0402_5%

1 2

R246 8.2K_0402_5%

D D

+3VALW

C C

+3VALW

B B

1 2

R248 10K_0402_5%

1 2

R244 8.2K_0402_5%@

1 2

R68 8.2K_0402_5%

1 2

R508 8.2K_0402_5%

Add in 9/27

1 2

R252 10K_0402_5%

1 2

R255 10K_0402_5%

1 2

R258 10K_0402_5%

1 2

R259 1K_0402_5%

1 2

R260 10K_0402_5%

1 2

R321 10K_0402_5%

Add R321 in 10/03.

1 2

R266 10K_0402_5%

1 2

R269 10K_0402_5%@

1 2

R272 10K_0402_5%

1 2

R273 10K_0402_5%

1 2

R331 10K_0402_5%

Add R331 in 10/08.
Change R269 to 10K. 9/29
Del R261, R264, R267 cause no used in 9/21.

RP16

45
36
27
18

10K_1206_8P4R_5%

RP15

45
36
27
18

10K_1206_8P4R_5%

1 2

R238 10K_0402_5%

1 2

R603 10K_0402_5%

Add in 9/14.

Add RP15 back. 9/27

1 2

R335 10K_0402_5%

Add in 10/10.

ICH_SMBDATA14,15,16

ICH_SMBCLK14,15,16

ICH_SM_DA4,26

ICH_SM_CLK4,26

A A

ALS_EN#

2

G

5

LAN_STATUS#_D
SIRQ
PM_CLKRUN#

THERM_SCI#

GPIO19
GPIO22
NPCI_RST#
ALS_EN#

GPIO21
GPIO37

LINKALERT#
PCIE_WAKE#
ICH_RI#
XDP_DBRESET#
S4_STATE#
ICH_LOW_BAT#

SUS_PWR_ACK
AC_PRESENT
ME__EC_CLK1
ME__EC_DATA1
LAN_PHYPC_R

USB_OC#7
USB_OC#5
USB_OC#0
USB_OC#4

USB_OC#1
USB_OC#6
WXMIT_OFF#
USB_OC#2

GPIO11
XMIT_OFF#

EXP_RST

R282

2.2K_0402_5%

ICH_SMBDATA

+3VS

R287

2.2K_0402_5%

+3VS

R292

330_0402_5%

1 2
13

D

Q16
RHU002N06_SOT323

S

5

Del R244. 9/27

Change R238 connect to GPIO11. 9/27

Change from
ODD_DET# to
GPIO19. 10/18

H_STP_PCI#16
H_STP_CPU#16

Change R251 to CH751. 10/04

ISO_PREP#34

LAN_PHYPC24,25

R276
low -->default
High -->No boot

+3VALW

R280

10K_0402_5%

PREP#25,34

+3VM

R283

12

12

2.2K_0402_5%
Q12

RHU002N06_SOT323

D

S

13

S

G

2

G

2

R288

2.2K_0402_5%
Q14

RHU002N06_SOT323

D

S

G

2

13

D

S

13

Q15
RHU002N06_SOT323

G

2

ICH_SMB_DATA
ICH_SMB_CLK

12

+5VS

+3VM

12

ALS_EN 18

Del PU for GPIO39. 9/27

ICH_SMBCLK
ICH_SMBDATA

R241 0_0402_5%@
R243 0_0402_5%@

9/21

+3VM

12

12

R249

10K_0402_5%@

VGATE42

R250

10K_0402_5%@

Change in 7/13

R262 0_0402_5%@
R325 100K_0402_5% @

Reserve in 10/08.

D40 CH751H-40_SC76

R268 0_0402_5%

1 2

Add EXP_RST# in 10/09.

1 2

+3VS

R275 8.2K_0402_5%

R276 1K_0402_5% @

+3VS +3VALW

12

1 2

Change design in 10/08.

R332 0_0402_5%

1 2

ICH_SMB_DATA

D

ICH_SMB_CLKICH_SMBCLK

13

Q13
RHU002N06_SOT323

KBC_SPI_CLK_R33
KBC_SPI_CS0#_R33
KBC_SPI_CS1#_R32,33

KBC_SPI_CS1#20

KBC_SPI_SI_R33

KBC_SPI_SO33

WXMIT_OFF#26

WEBCAM_ON/OFF#18

4

2.2K_0402_5%

12
12

LPC_PD#32

XDP_DBRESET#4

PM_BMBUSY#8

R253 0_0402_5%

1 2

PM_CLKRUN#27,32,33

PCIE_WAKE#26

THERM_SCI#4

1 2
1 2

RUNSCI_EC#33

21

LID_SW#18,19,33

HDD_HALTLED19

CLKSATAREQ#16

EXP_RST26

SB_SPKR28

MCH_ICH_SYNC#8

ICH_RSVD21

ISO_PREP#

PCIE_RXN226
PCIE_RXP226
PCIE_TXN226
PCIE_TXP226

PCIE_RXN326
PCIE_RXP326
PCIE_TXN326
PCIE_TXP326

PCIE_RXN426
PCIE_RXP426
PCIE_TXN426

PCIE_TXP426
ICH_SMB_DATA 26
ICH_SMB_CLK 26

GLAN_RXN24

GLAN_RXP24

GLAN_TXN24

GLAN_TXP24

BT_OFF31

XMIT_OFF#26

FPR_OFF32

4

+3VALW

12

12

R236

R235

2.2K_0402_5%

ICH_SMB_CLK
ICH_SMB_DATA
LINKALERT#
ME__EC_CLK1
ME__EC_DATA1

ICH_RI#

XDP_DBRESET#
PM_BMBUSY#
GPIO11
H_STP_PCI#

R_STP_CPU#
PM_CLKRUN#
PCIE_WAKE#

SIRQ

SIRQ27,32,33

THERM_SCI#
VRMPWRGD

PAD

T54

OCP#44

LAN_STATUS#_DLAN_STATUS#
ISO_PREP#
LAN_PHYPC_R

ALS_EN#

T95PAD

GPIO22

T55PAD
T96PAD

GPIO38
GPIO39

T107PAD

EXP_RST

T116PAD
T117PAD

SB_SPKR
MCH_ICH_SYNC#
ICH_RSVD

T56PAD
T57PAD
T58PAD

C227 0.1U_0402_16V4Z

1 2

C228 0.1U_0402_16V4Z

1 2

C229 0.1U_0402_16V4Z

1 2

C230 0.1U_0402_16V4Z

1 2

C231 0.1U_0402_16V4Z

1 2

C232 0.1U_0402_16V4Z

1 2

C233 0.1U_0402_16V4Z

1 2

C234 0.1U_0402_16V4Z

1 2

R285 15_0402_5%

1 2

R286 15_0402_5%

1 2

R290 15_0402_5%

1 2

R289 15_0402_5%

1 2

R291 0_0402_5%

1 2

12

R293

22.6_0402_1%

U8C

C18

SMBCLK

C15

SMBDATA

B21

LINKALERT#/GPIO60/CLGPIO4

E18

SMLINK0

A24

SMLINK1

C20

RI#

T5

SUS_STAT#/LPCPD#

C25

SYS_RESET#

L2

PMSYNC#/GPIO0

A23

SMBALERT#/GPIO11

B15

STP_PCI#/GPIO15

A20

STP_CPU#/GPIO25

M5

CLKRUN#/GPIO32

C21

WAKE#

L4

SERIRQ

AD20

THRM#

B24

VRMPWRGD

A19

TP12

AE16

GPIO1

AE18

GPIO6

AD18

GPIO7

B25

GPIO8

C14

GPIO12

D20

GPIO13

AE17

GPIO17

K3

GPIO18

AC8

GPIO20

AC19

SCLOCK/GPIO22

D17

GPIO27

E20

GPIO28

M4

SATACLKREQ#/GPIO35

AB18

SLOAD/GPIO38

AC18

SDATAOUT0/GPIO39

AB19

SDATAOUT1/GPIO48

AC20

GPIO49

A16

GPIO57/CLGPIO5

K4

SPKR

AB20

MCH_SYNC#

C19

TP3

AB17

TP8

AC17

TP9

AD17

TP10

ICH9-M SFF ES_FCBGA56 9

PCIE_RXN2
PCIE_RXP2
PCIE_C_TXN2
PCIE_C_TXP2

PCIE_RXN3
PCIE_RXP3
PCIE_C_TXN3
PCIE_C_TXP3

PCIE_RXN4
PCIE_RXP4
PCIE_C_TXN4
PCIE_C_TXP4

GLAN_RXN
GLAN_RXP
GLAN_TXN_C
GLAN_TXP_C

KBC_SPI_CLK
KBC_SPI_CS0#
KBC_SPI_CS1#

KBC_SPI_SI

USB_OC#0
USB_OC#1
USB_OC#2
WXMIT_OFF#
USB_OC#4
USB_OC#5
USB_OC#6
USB_OC#7

XMIT_OFF#

USBRBIAS

Within 500 mils

Security Classification

THIS SHEET OF EN GINEE RING D RAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR DISCLO SED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

U8D

T25

PERN1

T24

PERP1

R24

PETN1

R23

PETP1

P25

PERN2

P24

PERP2

P21

WLAN

PETN2

P22

PETP2

N23

PERN3

N24

PERP3

M21
M22

M25
M24

H24
H25

G23

AE5
AD5

EXP

PETN3
PETP3

PERN4
PERP4

L24

WWAN

PETN4

L23

PETP4

K24

PERN5

K25

PERP5

K21

PETN5

K22

PETP5
PERN6/GLAN_RXN

PERP6/GLAN_RXP

J24

PETN6/GLAN_TXN

J23

PETP6/GLAN_TXP

E24

SPI_CLK

E23

SPI_CS0#

F23

SPI_CS1#/GPIO58/CLGPIO6

F22

SPI_MOSI
SPI_MISO

P4

OC0#/GPIO59

N4

OC1#/GPIO40

N1

OC2#/GPIO41

P5

OC3#/GPIO42

P1

OC4#/GPIO43

P2

OC5#/GPIO29

M3

OC6#/GPIO30

M2

OC7#/GPIO31

P3

OC8#/GPIO44

R1

OC9#/GPIO45

R4

OC10#/GPIO46

R2

OC11#/GPIO47
USBRBIAS

USBRBIAS#

ICH9-M SFF ES_FCBGA56 9

Issued Date

3

PM_PWROK_R

1 2

R328 0_0402_5%

Reserve for DB1 test. 10/05

GPIO21

CLK14

CLK48
SUSCLK
SLP_S3#

SLP_S4#
SLP_S5#

PWROK

BATLOW#
PWRBTN#
LAN_RST#

RSMRST#

CK_PWRGD

CLPWROK

SLP_M#

CL_CLK0
CL_CLK1

CL_DATA0
CL_DATA1

CL_VREF0
CL_VREF1

CL_RST0#
CL_RST1#

AE19

GPIO19

AA18

NPCI_RST#

AE20

GPIO37

AA20

CLK_14M_ICH

K1

CLK_48M_ICH

AB5

ICH_SUSCLK

R3
D18

B20
D16

E14
D23
M1
C16
U4
D22
D19
U1
T4
B23
C22

A18
E22

B18
F21

A17
C17

B17
A22

E16
A15
D21

SLP_S3#
SLP_S4#
SLP_S5#

S4_STATE#
PM_PWROK_R
DPRSLPVR
ICH_LOW_BAT#

RSMRST#
CK_PWRGD_R
M_PWROK

CL_CLK0
CL_CLK1

CL_DATA0
CL_DATA1

CL_VREF0_ICH
CL_VREF1_ICH

CL_RST#
CL_RST#1

SUS_PWR_ACK
AC_PRESENT

T53 PAD

R256 0_0402_5%
D9 CH751H-40_SC76

R263 10K_0402_5%
R265 0_0402_5%

Add WOL_EN back. 10/10

SATA0GP/GPIO21
SATA1GP/GPIO19
SATA4GP/GPIO36
SATA5GP/GPIO37

SATA

GPIO

SMB

Clocks

S4_STATE#/GPIO26

DPRSLPVR/GPIO16

SYS GPIO

Power MGTController Link

GPIO

MEM_LED/GPIO24

GPIO10/SUS_PWR_ACK

GPIO14/AC_PRESENT

WOL_EN/GPIO9

MISC

DMI_RXN0

V25

DMI0RXN
DMI0RXP
DMI0TXN

DMI0TXP

DMI1RXN
DMI1RXP
DMI1TXN

DMI1TXP

DMI2RXN
DMI2RXP
DMI2TXN

DMI2TXP

DMI3RXN
DMI3RXP
DMI3TXN

DMI3TXP

DMI_CLKN

PCI-Express

DMI_CLKP

Direct Media Interface

DMI_ZCOMP

DMI_IRCOMP

USBP0N

USBP0P

USBP1N

GLAN

USBP1P

USBP2N

USBP2P

USBP3N

USBP3P

USBP4N

USBP4P

USBP5N

SPI

USBP5P

USBP6N

USB

USBP6P

USBP7N

USBP7P

USBP8N

USBP8P

USBP9N

USBP9P
USBP10N
USBP10P
USBP11N
USBP11P

2006/02/13 2006/03/10

DMI_RXP0

V24

DMI_TXN0

U24

DMI_TXP0

U23

DMI_RXN1

W23

DMI_RXP1

W24

DMI_TXN1

V21

DMI_TXP1

V22

DMI_RXN2

Y24

DMI_RXP2

Y25

DMI_TXN2

Y21

DMI_TXP2

Y22

DMI_RXN3

AB24

DMI_RXP3

AB25

DMI_TXN3

AA23

DMI_TXP3

AA24

CLK_PCIE_ICH#

T21

CLK_PCIE_ICH

T22
AB21

AB22
AE2

AD1
AD3
AD4
AC2
AC3
AC5
AB4
AB2
AB1
AA3
AA2
Y1
Y2
W2
W3
V1
V2
Y5
Y4
U3
U2
V4
V5

DMI_IRCOMP

USB20_N0 31
USB20_P0 31

USB20_N2 26
USB20_P2 26
USB20_N3 26
USB20_P3 26
USB20_N4 31
USB20_P4 31
USB20_N5 31
USB20_P5 31
USB20_N6 31
USB20_P6 31
USB20_N7 26
USB20_P7 26
USB20_N8 32
USB20_P8 32

USB20_N9 34

USB20_P9 34

USB20_N10 18

Pin connection error, modify in 10/24.

USB20_P10 18

Compal Secret Data

Deciphered Date

2

PM_PWROK 8,33,42,43

NPCI_RST# 33

CLK_14M_ICH 16
CLK_48M_ICH 16

SLP_S3# 24,26,28,33,36,41,42,44
SLP_S4# 36,40
SLP_S5# 36

S4_STATE# 31

R254 10K_0402_5%@

1 2
1 2
2 1

ON/OFFBTN# 30
LAN_DISABLE_N 33

1 2
1 2

M_PWROK 8,35
PM_SLP_M# 33,36,40,41

CL_CLK0 8

CL_CLK1 26

CL_DATA0 8

CL_DATA1 26

CL_RST# 8

CL_RST#1 26

SUS_PWR_ACK 33
AC_PRESENT 33
LAN_WOL_EN 33,36

DMI_RXN0 8
DMI_RXP0 8
DMI_TXN0 8
DMI_TXP0 8

DMI_RXN1 8
DMI_RXP1 8
DMI_TXN1 8
DMI_TXP1 8

DMI_RXN2 8
DMI_RXP2 8
DMI_TXN2 8
DMI_TXP2 8

DMI_RXN3 8
DMI_RXP3 8
DMI_TXN3 8
DMI_TXP3 8

CLK_PCIE_ICH# 16
CLK_PCIE_ICH 16

R284 24.9_0402_1%

1 2

MB

EXPRESS
WLAN

MB
MB
Bluetooth
WWAN
Fingerprint
DOCK
USB Camera

2

1

VRMPWRGD

13

D

S

Q63

RHU002N06_SOT323

R595 10K_0402_5%

R596 0_0402_5%

2

G

1

C547

0.1U_0402_16V4Z @

2

1 2

1 2

Add for find tu ne ti min g.(If have glich issue)

Reserve R254 at 9/19.

PM_DPRSLPVR 8,42

LOW_BAT# 33

R366 0_0402_5%

1 2

PM_RSMRST# 33
CK_PWRGD 16

R271

3.24K_0402_1%

1 2

12

1

R274

2

453_0402_1%

C225

0.1U_0402_16V4Z
R277

3.24K_0402_1%

1 2

12

1

R278

2

C226

453_0402_1%

0.1U_0402_16V4Z

LANLINK_STATUS#24,25,33

Within 500 mils

+1.5VS

Title

Size Document Number Rev

Custom

Date: Sheet

+3VL

R257
10K_0402_5%

1 2

RPGOOD 39

+3VM

Add in 10/04.

5

U10

P

IN1

4

O

IN2

G

SN74AHC1G08DCKR_SC70

3

G

2

R294 10K_0402_5%

LAN_STATUS#

13

D

S

12

@

R239
10_0402_5%

@

1

C223

4.7P_0402_50V8C

2

Q17
RHU002N06_SOT323

Compal Electronics, Inc.

ICH9(3/4)_DMI,USB,GPIO,PCIE

LA-4021P

1

1
2

12

SLP_S3#

Place clos ely pin H1Place closely pin AF3

12

1

2

+3VS

CLK_ENABLE# 42

+3VM_LAN+3VALW

+3VALW

CLK_14M_ICHCLK_48M_ICH

@

R240
10_0402_5%

@

C224

4.7P_0402_50V8C

of

22 45Monday, October 29, 2007

0.1

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技术支持：252670528

5

+RTCVCC

C235

0.1U_0402_16V4Z

R295

D D

C C

B B

+1.5VS

+3VM_WOL

A A

+1.5VS

+5VS +3VS +3VALW+5VALW

12

R298

100_0402_5%

9/19

+1.5VS

1 2

CHB1608U301_0603

R302

1 2

CHB1608U301_0603

1 2

BLM18PG181SN1D_0603

21

D11
CH751H-40_SC76

ICH_V5REF_RUN

20 mils

1

C251
1U_0603_10V4Z

2

R300

1 2

CHB1608U301_0603

1U_0603_10V4Z

+1.5VS_USBPLL

R301

1

1

2

2

C265

C266

0.1U_0402_16V4Z

1

2

C268

+1.5VS

5

0.1U_0402_16V4Z

R303
CHB1608U301_0603

1 2

0.1U_0402_16V4Z

1

1

C236

2

2

1

+

2

C242

220U_D2_4VM

R299

10_0402_5%

1

1

2

2

C257

C256

10U_0805_10V4Z

C267

0.1U_0402_16V4Z

10U_0805_10V4Z

20 mils

ICH_V5REF_RUN
ICH_V5REF_SUS

+1.5VS_PCIE_ICH

0.1U_0402_16V4Z

40 mils

1

1

1

2

2

2

C239

C241

C240

10U_0805_10V4Z

10U_0805_10V4Z

2.2U_0603_6.3V4Z

12

21

D12
CH751H-40_SC76

ICH_V5REF_SUS

20 mils

1

C252

0.1U_0402_16V4Z

2

+1.5VS_VCCSATAPLL

+1.5VS

12

+1.5VS_PCIE_ICH

1

2

C269

1

2

C258

1U_0603_10V4Z

1

2

C259

1U_0603_10V4Z

1

2

C263

0.1U_0402_16V4Z

VCC_LAN1_05_INT_ICH

+1.5VS_GLAN

1

+3VS

2

C270

10U_0805_10V4Z

4

U8F

G17

VCCRTC

G7

V5REF

U7

V5REF_SUS

J19

VCC1_5_B[01]

K18

VCC1_5_B[02]

K19

VCC1_5_B[03]

L18

VCC1_5_B[04]

L19

VCC1_5_B[05]

M18

VCC1_5_B[06]

M19

VCC1_5_B[07]

N18

VCC1_5_B[08]

N19

VCC1_5_B[09]

P18

VCC1_5_B[10]

R18

VCC1_5_B[11]

T18

VCC1_5_B[12]

T19

VCC1_5_B[13]

U18

VCC1_5_B[14]

U19

VCC1_5_B[15]

W17

VCCSATAPLL

U13

VCC1_5_A[01]

V13

VCC1_5_A[02]

W13

VCC1_5_A[03]

U12

VCC1_5_A[04]

V12

VCC1_5_A[05]

W12

VCC1_5_A[06]

W10

VCC1_5_A[07]

U15

VCC1_5_A[08]

V15

VCC1_5_A[09]

W18

VCC1_5_A[10]

G9

VCC1_5_A[11]

H9

VCC1_5_A[12]

V11

VCC1_5_A[13]

U11

VCC1_5_A[14]

U8

VCCUSBPLL

T9

VCC1_5_A[15]

U9

VCC1_5_A[16]

G11

VCCLAN1_05[1]

H11

VCCLAN1_05[2]

G12

VCCLAN3_3[1]

H13

VCCLAN3_3[2]

J17

VCCGLANPLL

H19

VCCGLAN1_5[1]

J18

VCCGLAN1_5[2]

K16

VCCGLAN3_3

ICH9-M SFF ES_FCBGA56 9

4

CORE

VCCA3GP ATXARX USB CORE

VCCPSUSVCCPUSB

GLAN POWER

VCC1_05[01]
VCC1_05[02]
VCC1_05[03]
VCC1_05[04]
VCC1_05[05]
VCC1_05[06]
VCC1_05[07]
VCC1_05[08]
VCC1_05[09]
VCC1_05[10]
VCC1_05[11]
VCC1_05[12]
VCC1_05[13]
VCC1_05[14]
VCC1_05[15]
VCC1_05[16]

VCCDMIPLL
VCC_DMI[1]

VCC_DMI[2]

V_CPU_IO[1]
V_CPU_IO[2]

VCC3_3[01]
VCC3_3[02]

VCC3_3[03]
VCC3_3[04]
VCC3_3[05]

VCC3_3[06]
VCC3_3[07]
VCC3_3[08]

VCCP_CORE

PCI

VCCHDA

VCCSUSHDA

VCCSUS1_05[1]
VCCSUS1_05[2]

VCCSUS1_5[1]
VCCSUS1_5[2]

VCCSUS3_3[01]
VCCSUS3_3[02]
VCCSUS3_3[03]

VCCSUS3_3[04]
VCCSUS3_3[05]

VCCSUS3_3[06]
VCCSUS3_3[07]
VCCSUS3_3[08]
VCCSUS3_3[09]
VCCSUS3_3[10]
VCCSUS3_3[11]
VCCSUS3_3[12]
VCCSUS3_3[13]
VCCSUS3_3[14]
VCCSUS3_3[15]
VCCSUS3_3[16]

VCCCL1_05

VCCCL1_5

VCCCL3_3[1]
VCCCL3_3[2]

L11
L12
L13
L14
L15
M11
M15
N11
N15
P11
P15
R11
R12
R13
R14
R15

P19
T17

U17
V16

U16
V18
AE9

AA9
V14
W14

G8
H7
H8

AD7
V10
T7

H15
H16
V7

G14
G15
H14

W8
J7

J8
K7
K8
L7
L8
M7
M8
N7
N8
P7
P8

G18
H17
J14

K14

+VCCP

+1.5VS_DMIPLL

VCCSUS1_05_ICH_1
VCCSUS1_05_ICH_2

VCCSUS1_5_ICH_1
VCCSUS1_5_ICH_2

VCCCL1_05_ICH

1 2

C264 1U_0603_10V4Z

Security Classification

Issued Date

THIS SHEET OF EN GINEE RING D RAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR DISCLO SED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

1

1

2

2

C237

C238

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

2

C243

10U_0805_10V4Z

0.01U_0402_16V7K

9/29

VCC_DMI

(DMI)

+3VS

1

2

C253

0.1U_0402_16V4Z

T59

T60
T61
T62

+3VALW

1

2

C262

4.7U_0805_10V4Z

9/21

C217

0.1U_0402_16V4Z

1 2

+3VM_WOL

9/21

3

R296

1 2

CHB1608U301_0603

1

2

C244

R297

1 2

CHB1608U301_0603

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

1

2

2

2

C249

C248

C250

+3VALW

1

2

C255

0.1U_0402_16V4Z

+3VALW

1

1

2

2

C261

C260

0.1U_0402_16V4Z

0.1U_0402_16V4Z

2006/02/13 2006/03/10

9/29

+1.5VS

9/29

+VCCP

+3VS

1

2

C254

0.1U_0402_16V4Z

Compal Secret Data

VCC_DMI

1

2

C245

1U_0603_10V4Z

+VCCP

0.1U_0402_16V4Z

4.7U_0805_10V4Z

1

2

C246

+3VS

Deciphered Date

1

2

C247

2

U8E

B4

VSS[001]

B7

VSS[002]

B10

VSS[003]

B13

VSS[004]

B16

VSS[005]

B19

VSS[006]

B22

VSS[007]

D2

VSS[008]

D24

VSS[009]

E5

VSS[010]

E7

VSS[011]

E9

VSS[012]

E11

VSS[013]

E13

VSS[014]

E15

VSS[015]

E17

VSS[016]

E19

VSS[017]

E21

VSS[018]

F24

VSS[019]

G2

VSS[020]

G5

VSS[021]

G10

VSS[022]

G13

VSS[023]

G16

VSS[024]

G19

VSS[025]

G21

VSS[026]

H10

VSS[027]

H12

VSS[028]

H18

VSS[029]

H23

VSS[030]

J5

VSS[031]

J9

VSS[032]

J10

VSS[033]

J11

VSS[034]

J12

VSS[035]

J13

VSS[036]

J15

VSS[037]

J21

VSS[038]

J22

VSS[039]

J25

VSS[040]

K2

VSS[041]

K9

VSS[042]

K10

VSS[043]

K11

VSS[044]

K12

VSS[045]

K13

VSS[046]

K15

VSS[047]

K17

VSS[048]

K23

VSS[049]

L5

VSS[050]

L9

VSS[051]

L10

VSS[052]

L16

VSS[053]

L17

VSS[054]

L21

VSS[055]

L22

VSS[056]

L25

VSS[057]

M9

VSS[058]

M10

VSS[059]

M12

VSS[060]

M13

VSS[061]

M14

VSS[062]

M16

VSS[063]

M17

VSS[064]

M23

VSS[065]

N2

VSS[066]

N5

VSS[067]

N9

VSS[068]

N10

VSS[069]

N12

VSS[070]

N13

VSS[071]

N14

VSS[072]

N16

VSS[073]

N17

VSS[074]

N21

VSS[075]

N22

VSS[076]

N25

VSS[077]

P9

VSS[078]

P10

VSS[079]

P12

VSS[080]

P13

VSS[081]

P14

VSS[082]

P16

VSS[083]

P17

VSS[084]

P23

VSS[085]

R5

VSS[086]

R7

VSS[087]

R8

VSS[088]

R9

VSS[089]

R10

VSS[090]

R16

VSS[091]

R17

VSS[092]

R19

VSS[093]

R21

VSS[094]

R22

VSS[095]

R25

VSS[096]

T2

VSS[097]

T8

VSS[098]

T10

VSS[099]

T11

VSS[100]

T12

VSS[101]

T13

VSS[102]

T14

VSS[103]

T15

VSS[104]

T16

VSS[105]

T23

VSS[106]

ICH9-M SFF ES_FCBGA56 9

2

1

U5

VSS[107]

U10

VSS[108]

W11

VSS[109]

U14

VSS[110]

W16

VSS[111]

U21

VSS[112]

U22

VSS[113]

U25

VSS[114]

V3

VSS[115]

V8

VSS[116]

V19

VSS[117]

V23

VSS[118]

W1

VSS[119]

W4

VSS[120]

W5

VSS[121]

W7

VSS[122]

W9

VSS[123]

W15

VSS[124]

W19

VSS[125]

W21

VSS[126]

W22

VSS[127]

W25

VSS[128]

Y3

VSS[129]

Y23

VSS[130]

AA1

VSS[131]

AA4

VSS[132]

AA6

VSS[133]

AA8

VSS[134]

AA11

VSS[135]

AA13

VSS[136]

AA15

VSS[137]

AA16

VSS[138]

AA17

VSS[139]

AA19

VSS[140]

AA21

VSS[141]

AA22

VSS[142]

AA25

VSS[143]

AB3

VSS[144]

AB9

VSS[145]

AB11

VSS[146]

AB13

VSS[147]

AB15

VSS[148]

AC24

VSS[149]

AC1

VSS[150]

AC4

VSS[151]

AC10

VSS[152]

AC12

VSS[153]

AC14

VSS[154]

AD2

VSS[155]

AD6

VSS[156]

AD9

VSS[157]

AD16

VSS[158]

AD19

VSS[159]

AD22

VSS[160]

AE3

VSS[161]

AE4

VSS[162]

AE11

VSS[163]

AE13

VSS[164]

AE15

VSS[165]

V17

VSS[166]

AE8

VSS[167]

V9

VSS[168]

J16

VSS[169]

ICHGND1

VSS_NCTF[01]
VSS_NCTF[02]
VSS_NCTF[03]
VSS_NCTF[04]

A1
A25
AE1
AE25

Title

Size Document Number Rev

Custom

LA-4021P

Date: Sheet

R358 0_0402_5%@

ICHGND2
ICHGND3
ICHGND4

1 2

R361 0_0402_5%@

1 2

R368 0_0402_5%@

1 2

R399 0_0402_5%@

1 2

Compal Electronics, Inc.

ICH9(4/4)_POWER&GND

+3VS

R247

ICHGND1

RHU002N06_SOT323

+3VS

R414

ICHGND3

RHU002N06_SOT323

ICHGND2

RHU002N06_SOT323

ICHGND4

RHU002N06_SOT323

CRACK_BGA13,33

1

Q72

1 2

1 2

Q73

+3VS

R488

Q74

+3VS

R491

100K_0402_5%

2

G

100K_0402_5%

2

G

1 2

2

G

1 2

Q75

23 45Monday, October 29, 2007

CRACK_BGA

13

D

S

CRACK_BGA

13

D

S

CRACK_BGA

13

100K_0402_5%

D

S

13

100K_0402_5%

D

2

G

S

CRACK_BGA

of

0.1

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5

4

3

2

1

+3VM_WOL +3VM_LAN

ACBS is built i nto Nineveh, so
reserve these parts for test.
(9/4)

D D

LAN_PHYPC

ADP_PRES33,38,39

SLP_S3#22,26,28,33,36,41,42,44

C C

2

G

GLAN_RXP22
GLAN_RXN22

GLAN_TXP22
GLAN_TXN22

Add R309 back. 9/29

B B

Change R315 to 1K and R316 to 10K. 10/10

R305
1M_0402_5%

1 2

R306
100K_0402_5%

1 2

13

D

Q20

2

G

BSS138_SOT23

S

13

D

S

2

G

R308 0_0402_5%

Q21

RHU002N06_SOT323@

13

D

Q22

RHU002N06_SOT323 @

S

C279 0.1U_0402_16V7K

1 2

C280 0.1U_0402_16V7K

1 2

GLAN_CLK21

LAN_RSTSYNC21

LAN_TXD021
LAN_TXD121
LAN_TXD221

LAN_RXD021
LAN_RXD121
LAN_RXD221

LANLINK_STATUS#22,25,33

LAN_ACT#25

LAN_PHYPC22,25

A A

R304 0_1206_5%@

1 2

S

D

13

G

Q18

2

2

C272

1

1 2

R309 33_0402_5%

R312 4.99K_0402_1%

1 2

R313 0_0402_5%@

1 2

R315 1K_0402_5%

R316 10K_0402_5%

+3VM_LAN +3VM_LAN

SI2301BDS_SOT23

1000P_0402_50V7K

Install R308. 9/29

GLAN_RXP_C
GLAN_RXN_C

GLANCLK

1 2

LANLINK_STATUS#
LAN_ACT#

12

IEEE_TEST_P
IEEE_TEST_N

LAN_PHYPC

1 2

XTAL2
XTAL1

R617 1K_0402_5%@
R618 200_0402_5%@

R317 200_0402_5%@

1 2
1 2

1 2

1

C271
10U_0805_10V4Z

2

2

1

U9

52

GLAN_TXP

53

GLAN_TXN

55

GLAN_RXP

56

GLAN_RXN

45

JKCLK

50

JRSTSYNC

42

JTXD_0

43

JTXD_1

44

JTXD_2

47

JRXD_0

48

JRXD_1

49

JRXD_2

4

LED_0

2

LED_1

1

LED_2

15

RSET

12

IEEE_TEST_P

13

IEEE_TEST_N

34

DIS_REG10

37

LAN_DISABLE_N

36

TEST_EN

9

XTAL2

10

XTAL1

Y3

25MHZ_20P_1BG25000CK1A

1 2

C277
27P_0402_50V8J

JTAG_TMS39JTAG_TCK40JTAG_TRST35JTAG_TDI7JTAG_TDO

6

PAD
T68

2

C278
27P_0402_50V8J

1

MDI_N_0

MDI_P_0

MDI_N_1

MDI_P_1

MDI_N_2

MDI_P_2

MDI_N_3

MDI_P_3

VDDO_33_3

VDDO_33_46

AVDD_33_28

DVDD_10_5

DVDD_10_8
DVDD_10_33
DVDD_10_38

AVDD_18_11
AVDD_18_14
AVDD_18_19
AVDD_18_18
AVDD_18_24
AVDD_18_25
AVDD_18_41
AVDD_18_54
AVDD_18_32
AVDD_18_30

CTRL18
CTRL10

RESERVED_NC

GND_PAD

82567LF_QFN56_8X8~D

R318 200_0402_5%@

XTAL1

XTAL2

26
27

22
23

20
21

16
17

R310 0_0603_5%

3
46
28

+V1.0M_LAN

5
8
33
38

11
14
19
18
24

+1.8VM_LAN

25
41
54
32
30

LAN_CTRL_18

29
31

51

57

T65PAD
T67PAD

12

LAN_MDI0N 25

LAN_MDI0P 25

LAN_MDI1N 25

LAN_MDI1P 25

LAN_MDI2N 25

LAN_MDI2P 25

LAN_MDI3N 25

1 2

Del R311 and modify
net name to
+V1.0M_LAN. 10/18

R314
0_0603_5%

1 2

LAN_MDI3P 25

+3VM_LAN_R

+1.8VM

LAN_CTRL_18

+3VM_LAN

+3VM_LAN

C288

2

1

0.1U_0402_16V4Z

C273

1

2

4.7U_0805_10V4Z

2

C275

1

+V1.0M_LAN

C287

2

1

1

2

10U_0805_10V4Z

+1.8VM_LAN

C296

1

1

2

2

10U_0805_10V4Z

+1.8VM

1

C276

2

0.1U_0402_16V4Z

10U_0805_6.3V6M

Q19
BCP69_SOT223

R307

2

C274

1

10U_0805_10V4Z

C289

2

1

4.75K_0402_1%

0.1U_0402_16V4Z

1 2

C282

C281

C283

2

2

2

1

1

1

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

C291

C292

C290

2

2

2

1

1

1

0.1U_0402_16V4Z

0.1U_0402_16V4Z

470P_0402_50V7K

470P_0402_50V7K

3

C284

2

1

C293

2

1

4
2

1

C286

C285

2

1

4.7U_0805_10V4Z

4.7U_0805_10V4Z

C295

C294

2

1

10U_0805_10V4Z

4.7U_0805_10V4Z

5

4

Security Classification

Issued Date

THIS SHEET OF EN GINEE RING D RAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR DISCLO SED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/02/13 2006/07/26

Compal Secret Data

Deciphered Date

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

Intel 82566 Nineveh

LA-4021P

1

of

24 45Monday, October 29, 2007

0.1

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技术支持：252670528

5

4

3

2

1

Del LAN ENERGY DET cause already inside the BOAZ. 9/27

LAN status/link level shift. 9/21

Q78A

D D

LAN_ACT#_DOCK34

LANLINK_STATUS#_DOCK34

2N7002DW-T/R7_SOT363-6

2

Q78B
2N7002DW-T/R7_SOT363-6

4

5

61

LAN_LINK_EN

LANLINK_STATUS#

3

LAN_ACT#

R615
10K_0402_5%

1 2

+3VM_LAN

Delete all termination cause they are already inside BOAZMAN. 9/28

Pin Swap. 10/05
Swap P & N. 10/09

T69

LAN_MDI0P24

C C

B B

+1.8VM

LAN_MDI0N24

12

C297 0.1U_0402_16V7K

C299 0.1U_0402_16V7K

C304 0.1U_0402_16V7K

C305 0.1U_0402_16V7K

LAN_MDI1P24

+1.8VM

LAN_MDI1N24

12

LAN_MDI2P24

+1.8VM

LAN_MDI2N24

12

LAN_MDI3P24

+1.8VM

LAN_MDI3N24

12

TRM_CT

TRM_CT

TRM_CT

TRM_CT

12

TD4-

11

TD4+

10

TCT4

9

TD3-

8

TD3+

7

TCT3

6

TD2-

5

TD21+

4

TCT2

3

TD1-

2

TD1+

1

TCT1

24HST1041A-3_24P

1:1

1:1

1:1

1:1

MX4-

MX4+
MCT4

MX3-

MX3+
MCT3

MX2-

MX2+
MCT2

MX1-

MX1+
MCT1

MDO0+

13

Change design. 10/12

MDO0-

14

MCT0

15

MDO1+

16

MDO1-

17

MCT1

18

MDO2+

19

MDO2-

20

MCT2

21

MDO3+

22

MDO3-

23

MCT3

24

C307 0.01U_0402_50V7K

1 2

C308 0.01U_0402_50V7K

1 2

C309 0.01U_0402_50V7K

1 2

C310 0.01U_0402_50V7K

1 2

R319
75_0402_1%

R323
75_0402_1%

R329
75_0402_1%

R330
75_0402_1%

12

12

12

C306 1000P_1808_3KV7K

12

1 2

JP11

3

MDO3­MDO3+
MDO1­MDO2­MDO2+
MDO1+
MDO0­MDO0+

11

Yellow LED+

12

Yellow LED-

8

PR4-

7
6
5
4
3
2
1
9

10

DETECT PIN1

PR4+
PR2­PR3­PR3+
PR2+
PR1­PR1+
Green LED+
Green LED-

SUYIN_100073FR014G303ZL_13P

2006/02/13 2006/07/26

15

SHLD1

13

14

SHLD1

Compal Secret Data

R89 0_0402_5%@

1 2

Modify JP11 footprint to
same as Meson. 10/25

Deciphered Date

20 mil

LAN_PHYPC 22,24

Title

Size Document Number Rev

LA-4021P

2

Date: Sheet

+3VM_LAN V_3P3_LAN_LED

D

S

20 mil

R340
100K_0402_5%

PREP#22,34

13

12

G

Q23

2

FDN338P_SOT23

13

D

Q24

2

2N7002_SOT23

G

S

Compal Electronics, Inc.

Magnetic & RJ45

25 45Monday, October 29, 2007

1

0.1

of

LAN_ACT#24

A A

LANLINK_STATUS#22,24,33

LAN_ACT#

1 2

0125 EMI request

LANLINK_STATUS#

1 2

V_3P3_LAN_LED

R339 300_0603_5%

1 2

MDO3-34

C311680P_0402_50V7K@

C312680P_0402_50V7K@

MDO3+34

MDO1-34

MDO2-34
MDO2+34
MDO1+34

MDO0-34
MDO0+34

R341 300_0603_5%

1 2

V_3P3_LAN_LED

Security Classification

Issued Date

THIS SHEET OF EN GINEE RING D RAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED B Y OR DISCLO SED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

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A

Express Card Slot

+3VS_PEC

1

1

2

1 1

C322

+1.5VS_PEC

1

2

C328

2 2

+3VALW

R585 100K_0402_5%

+3V_PEC

2

C323

0.1U_0402_16V4Z

4.7U_0805_10V4Z

1

2

C324

1

2

C329

0.1U_0402_16V4Z

C330 0.1U_0402_16V4Z

C331 0.1U_0402_16V4Z

C332 0.1U_0402_16V4Z

1 2

0.1U_0402_16V4Z

4.7U_0805_10V4Z

12

12

12

1

2

C325

+1.5VS

SLP_S3#22,24,28,33,36,41,42,44

+3VS

USB20_N222
USB20_P222

PCI_PME#20

PCIE_RXN322

4.7U_0805_10V4Z

PCIE_RXP322

Express Card Power Switch

+3VALW

21

18
19

NC_CP#

14

CPPE#

15

PLT_RST#

R342 0_0402_5%
R343 0_0402_5%

R344
0_0402_5%

1 2

U11
TPS2231PWPR_PWP24

5

3.3Vin1

6

3.3Vin2

3.3Vaux_in

1.5Vin1

1.5Vin2

CPUSB#
CPPE#

4

STBY#
SHDN#3RCLKEN

2

SYSRST#

GND

NC11NC210NC312NC413NC5

11

1 2
1 2

+3V_PEC
+3VS_PEC

CLK_PCIE_EXP#16

CLK_PCIE_EXP16

C326 0.1U_0402_16V7K

1 2

C327 0.1U_0402_16V7K

1 2

PCIE_TXN322
PCIE_TXP322

3.3Vout1

3.3Vout2

Aux_out

1.5Vout1

1.5Vout2

OC#

PERST#

24

EXP_RST22

+1.5VS_PEC
+1.5VS_PEC

+3VS_PEC

7
8

+3V_PEC

20

16
17

RCLKEN have
internal PU.

23

RCLKEN

22

PERST#

9

Use GPIO48 from ICH9 for this work. 10/9

B

USBP2-_R
USBP2+_R
NC_CP#

ICH_SMB_CLK
ICH_SMB_DATA

PCIE_PME#_R

PERST#

CLKREQA#
CPPE#

PCIE_RXN3_R
PCIE_RX3P_R

+1.5VS_PEC

13

D

2

G

S

2

G

Q26

+3VS

2N7002_SOT23@

R348

@

10K_0402_5%

1 2

CLKREQA#

13

D

Q25

2N7002_SOT23@

S

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26

27
28

JP12

GND-1
USB_D­USB_D+
CPUSB#
RSV-5
RSV-6
SMB_CLK
SMB_DATA
+1.5V-9
+1.5V-10
WAKE#
+3.3VAUX
PERST#
+3.3V-14
+3.3V-15
CLKREQ#
CPPE#
REFCLK­REFCLK+
GND-20
PERn0
PERp0
GND-23
PETn0
PETp0
GND-26

GND-27
GND-28

SANTA_130832-1_LBCONN@

CLKREQA# 16

C

+3V_WLAN

1

1

1

2

2

2

C315

0.01U_0402_16V7K

PCIE_RXN222
PCIE_RXP222

PCIE_TXN222
PCIE_TXP222

Change Power rail same
as pin2, 52. 8/16

CL_CLK122
CL_DATA122
CL_RST#122

MC2_DISABLE33

C317

C316

4.7U_0805_10V4Z

0.1U_0402_16V4Z

CLKREQ_WLAN#16

CLK_PCIE_MCARD#16

CLK_PCIE_MCARD16

10/18

R346 0_0402_5%
R347 0_0402_5%

CL_CLK1
CL_DATA1
CL_RST#1

+3VALW

R605

10K_0402_5%

Change Q66 from
SI2301BDS to
SI2305DS. 10/25

CLK_PCI_DEBUG16

12

+1.5VS

0.1U_0402_16V4Z

1

2

C319

1

2

C320

4.7U_0805_10V4Z

PCIE_WAKE#

PCI_RST#_R

PCIE_C_RXN2
PCIE_C_RXP2

+3V_WLAN

12
12
12

2

T77 PAD

1

2

C318

0.01U_0402_16V7K

PCIE_WAKE#22

1 2
1 2

R349 0_0402_5%
R350 0_0402_5%
R351 0_0402_5%

R606
220K_0402_1%

1 2

D

Reserve for p o r t8 0 c ar d u s e for FCS in factory side. 10/17

DEG_FRAME#
DEBUG_AD3
DEBUG_AD2
DEBUG_AD1
DEBUG_AD0

PCI_RST#_R

R407 0_0402_5%@

1 2

R409 0_0402_5%@

1 2

R528 0_0402_5%@

1 2

R529 0_0402_5%@

1 2

R522 0_0402_5%@

1 2

R530 0_0402_5%@

12

LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0

Mini-Express Card

JP13

Q66
SI2305DS-T1-E3_SOT23-3

31

+3V_WLAN

1

1

3

3

5

5

7

7

9

9

11

11

13

13

15

15

17

17

19

19

21

21

23

23

25

25

27

27

29

29

31

31

33

33

35

35

37

37

39

39

41

41

43

43

45

45

47

47

49

49

51

51

53

GND1

FOX_AS0B226-S40N-7F

conn@

GND2

2

2

10/17

4

4

6

6

DEG_FRAME#

8

8

DEBUG_AD3

10

10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

54

DEBUG_AD2
DEBUG_AD1
DEBUG_AD0

XMIT_D_OFF#
PLT_RST#

ICH_SMB_CLK
ICH_SMB_DATA

WW_LED#
WL_LED#
WP_LED#

WW_LED#
WP_LED#

XMIT_D_OFF#

Add to prevent leakage issue.

PLT_RST# 8,20,32

ICH_SMB_CLK 22
ICH_SMB_DATA 22

USB20_N3 22
USB20_P3 22

WL_LED# 19

R352 0_0402_5%@

1 2

R353 0_0402_5%@

1 2

2 1

D13 CH751H-40_SC76

+3V_WLAN

E

LPC_FRAME# 21,32,33

LPC_AD[0..3 ] 21,32,33
PCI_RST# 20,27

R345
0_1206_5%@

1 2

WL_LED#

XMIT_OFF# 22

+3VS+3V_WLAN

+1.5VS

+3V_WWAN

USB20_N7 22
USB20_P7 22

WW_LED# 19

UIM_DATA

Note2

1

1

1

2

2

2

C590

@

Close to JP14

B

39P_0402_50V8J

C592

39P_0402_50V8J

C591

39P_0402_50V8J

@

@

JP15

4

GND

5

VPP

6

I/O

7

DET

R367

47K_0402_5%

@
1 2

TAITW_PMPAT6-06GLBS7N14N0

UIM_PWR

Note1
Change Power rail same

as pin2, 52. 8/16
Note2

Reserve for 800 & 900MHz
EMI issue. 8/16

0.01U_0402_16V7K

U13

1
2

S DIO(BR) NUP4301MR6T1 TSOP-6@

CH1

CH4
Vn
CH23CH3

6
5

Vp

4

VCC
RST

CLK

GND
GND

Add in 9/27

Mini-Express Card--WWAN

Del BT_COMBO# in 10/12.

3 3

CLKREQG_WWAN#16
CLK_PCIE_WAN#16

CLK_PCIE_WAN16

Note1

+3V_WWAN

R362 0_0402_5%@
R363 0_0402_5%@
R364 0_0402_5%@

CL_RST#1
CL_DATA1
CL_CLK1

4 4

WMC1_DISABLE33

PCIE_WAKE#

T78 PAD
T79 PAD

PCIE_RXN422

PCIE_RXP422

PCIE_TXN422
PCIE_TXP422

R359 0_0603_5%

1 2
1 2

R360 0_0603_5%

12
12
12

T80 PAD

A

DEL in 9/26

JP14

1

1

3
5
7
9

Change Q67 from
SI2301BDS to
SI2305DS. 10/25

2

3

4

5

6

7

8

9

10
111112
131314
151516
171718
191920
212122
232324
252526
272728
292930
313132
333334
353536
373738
393940
414142
434344
454546
474748
494950
515152

GND153GND2

MOLEX_67910-5700conn@

WXMIT_OFF#22

+3VALW

12

R608

R607

220K_0402_1%

10K_0402_5%

1 2

+3V_WWAN

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

54

R354

1 2

UIM_PWR
UIM_DATA
UIM_CLK
UIM_RST
UIM_VPP

M_WXMIT_OFF#
PLT_RST#

ICH_SMB_CLK
ICH_SMB_DATA

WW_LED#
WL_LED#

CH751H-40_SC76

31

2

+3VS

0_1206_5% @

+3V_WWAN

Add back 9/27

D16

M_WXMIT_OFF#

21

Change value
to 47K. 9/27

Q67
SI2305DS-T1-E3_SOT23-3

+3V_WWAN

+3V_WWAN

ACCELEROMETER

1

1

2

C333

1

2

2

C334

C335

0.1U_0402_16V4Z

4.7U_0805_10V4Z

+3VS +3VS_ACL +3VS_ACL_IO

+3V_WWAN

D15

DAN217T146_SC59-3@

UIM_PWR

1

UIM_RSTUIM_VPP

2

UIM_CLK

3

1

C336

2

8
9

1

18P_0402_50V8J

2

@

C342

4.7U_0805_10V4Z

Security Classification

Issued Date

THIS SHEET OF EN GINEE RING D RAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR DISCLO SED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

+3V_WWAN

3

1

2

1

2

C343

0.1U_0402_16V4Z

2005/05/26 2006/07/26

+3VS_ACL_IO

+3VS_ACL

+3VS_ACL

Compal Secret Data

Deciphered Date

ACCEL_INT#20

ICH_SM_DA4,22

ICH_SM_CLK4,22

R365 10K_0402_5%

12

L

D

D14
CH751H-40_SC76

2 1

U12

LIS302DL

1

VDD_IO

6

VDD

8

INT 1
INT 29GND

12

SDO

13

SDA / SDI / SDO

14

SCL / SPC

7

CS

Must be pl aced in the center of the system.

LIS302DLTR_LGA14_3X5

R355
0_0603_5%

1 2

2

GND

4

GND

5

GND

10

3

RSVD

11

RSVD

Title

WLAN&WWAN Mini - C ard/ A ccelerometer

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

LA-4021P

1

C340

2

+3VS_ACL

E

+3VS_ACL

1

C341

2

0.1U_0402_16V4Z

10U_0805_6.3V6M

0.1

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5

PCI_AD[0..31]20

+3VS

D D

12

R369

100K_0402_5%

CBS_GRST#

1

C358
1U_0603_10V4Z

2

C C

Layout Note: Add GND shield.

B B

R372
100_0402_5%

PCI_AD22 CBS_IDSEL

1 2

CLK_PCI_139416

PM_CLKRUN#22,32,33

CLK_PCI_1394

12

R370

10_0402_5%

@

2

C359

1

4.7P_0402_50V8C

@

PCI_CBE#320
PCI_CBE#220
PCI_CBE#120
PCI_CBE#020

PCI_PAR20
PCI_FRAME#20
PCI_TRDY#20
PCI_IRDY#20
PCI_STOP#20
PCI_DEVSEL#20

PCI_PERR#20
PCI_SERR#20,33

PCI_REQ2#20
PCI_GNT2#20

PCI_RST#20,26

R378 10K_0402_5%@

1 2

R380 0_0402_5%

1 2

R381 10K_0402_5%

1 2

+3VS

PCI_PIRQE#20
PCI_PIRQG#20

R384 10K_0402_5%

+3VS

1 2

PCI_AD31
PCI_AD30
PCI_AD29
PCI_AD28
PCI_AD27
PCI_AD26
PCI_AD25
PCI_AD24
PCI_AD23
PCI_AD22
PCI_AD21
PCI_AD20
PCI_AD19
PCI_AD18
PCI_AD17
PCI_AD16
PCI_AD15
PCI_AD14
PCI_AD13
PCI_AD12
PCI_AD11
PCI_AD10
PCI_AD9
PCI_AD8
PCI_AD7
PCI_AD6
PCI_AD5
PCI_AD4
PCI_AD3
PCI_AD2
PCI_AD1
PCI_AD0

PCI_CBE#3
PCI_CBE#2
PCI_CBE#1
PCI_CBE#0

PCI_PAR
PCI_FRAME#
PCI_TRDY#
PCI_IRDY#
PCI_STOP#
PCI_DEVSEL#

PCI_PERR#
PCI_SERR#

PCI_REQ2#
PCI_GNT2#

CLK_PCI_1394
CBS_GRST#

PME#

U14

125

AD31

126

AD30

127

AD29

1

AD28

2
3
5
6

9
11
12
14
15
17
18
19
36
37
38
39
40
42
43
44
46
47
48
49
50
51
52
53

7
21
35
45

33
23
25
24
29
26

8
30
31

124
123

121
119

71

117

70

115
116

69
66

99

102
103
107
111

97

R5C833

AD27
AD26
AD25
AD24
AD23
AD22
AD21
AD20
AD19
AD18
AD17
AD16
AD15
AD14
AD13
AD12
AD11
AD10
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0

C/BE3#
C/BE2#
C/BE1#
C/BE0#

PAR
FRAME#
TRDY#
IRDY#
STOP#
DEVSEL#
IDSEL
PERR#
SERR#

REQ#
GNT#

PCICLK
PCIRST#
GBRST#
CLKRUN#
PME#

INTA#
INTB#

HWSPND#
TEST

AGND
AGND
AGND
AGND
AGND

RSV

R5C833-TQFP128P_TQFP128_14X14~D

4

VCC_PCI3V
VCC_PCI3V
VCC_PCI3V
VCC_PCI3V
VCC_PCI3V
VCC_PCI3V

VCC_RIN

VCC_ROUT
VCC_ROUT
VCC_ROUT
VCC_ROUT
VCC_ROUT

VCC_3V

VCC_MD3V

AVCC_PHY3V
AVCC_PHY3V
AVCC_PHY3V
AVCC_PHY3V

TPBIAS0

MDIO00
MDIO01
MDIO02
MDIO03
MDIO04
MDIO05
MDIO06
MDIO07
MDIO08
MDIO09
MDIO10
MDIO11
MDIO12
MDIO13
MDIO14
MDIO15
MDIO16
MDIO17
MDIO18
MDIO19

UDIO0/SRIRQ#

TPAP0
TPAN0

TPBP0
TPBN0

MSEN
XDEN

REXT
VREF

UDIO1
UDIO2
UDIO3
UDIO4
UDIO5

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

3

+3VS

10
20
27
32
41
128

61
16

34
64
114
120

67
86
98

106
110
112

IEEE1394_TPBIAS0

113

IEEE1394_TPAP0

109

IEEE1394_TPAN0

108

IEEE1394_TPBP0

105

IEEE1394_TPBN0

104

SD_CARD_DET#

80

MSCD#_XDCD1

79

XD_CE#

78

SD_WP

77

SDPWR0_MSPW R _XDPW R

76

XDWP#

75

3IN1_LED#

74

TP_MSEXTCK

73

SD_MMC_CMD

88

SDCLK_MMCCLK

84

SDDATA0_MSDATA0

82

SDDATA1_MSDATA1

81

SDDATA2_MSDATA2

93

SDDATA3_MSDATA3

90

MMC_D4

91

MMC_D5

89

MMC_D6

92

MMC_D7

87

XDCLE

85

XDALE

83

MSEN

58

XDEN

55

R5C832XI

94

XI

R5C832XO

95

XO

96

FIL0

101
100

SIRQ

72

TP_UDIO1

60

TP_UDIO2

56

UDIO3

65

UDIO4

59

UDIO5

57
4

13
22
28
54
62
63
68
118
122

1

1

2

2

C344

C522

0.01U_0402_16V7K

+3V_PHY

Add TP. 10/02

Add TP. 10/02

C365 0.01U _0402_16V7K

1 2

Layout Note:
Please them close to U14.

12

1

C367

R388

2

5.1K_0402_1%

270P_0402_50V7K

1

1

2

C534

0.01U_0402_16V7K

0.01U_0402_16V7K

+3VS

1

2

C357

C356

0.01U_0402_16V7K

GND
GND

SIRQ 22,32,33

1

1

2

2

2

C536

C345

C535

1

2

T118PAD
T119PAD

T120PAD
T121PAD

Layout Note:
Add GND shield for SDCLK_MMCCLK.

T122PAD
T123PAD

T81PAD
T82PAD

10U_0805_10V4Z

0.01U_0402_16V7K

0.01U_0402_16V7K

1

1

1

2

2

2

C354

0.47U_0603_16V4Z

C352

0.01U_0402_16V7K

C353

0.01U_0402_16V7K

10U_0805_10V4Z

Layout Note: Shield GND for
CBS_CCLK_INTERNAL and CBS_CCLK

2

1

1

2

C355

C366

0.01U_0402_16V7K

Layout Not e: Place close to R5C833
and Shield GND f o r SDCLK_MSCLK

1

1

1

2

2

2

0.1U_0402_16V4Z

C349

C350

C348

0.01U_0402_16V7K

0.47U_0603_16V4Z

+3VS

Layout Note:
Place these cap close to U14.

R383

10K_0603_1%

1 2

C551 22P_0402_50V8J@

+3VS

1

2

C351

10U_0805_10V4Z

0.01U_0402_16V7K

L6
BLM21A601SPT_0805

1 2

15P_0603_50V8J

15P_0603_50V8J

1 2

C346

1 2

C347

1 2

R377 10_0402_5%@

1

2

2

Layout Not e: Place close to R5C833
and Shield GND f o r SD_CLK

R5C832XI

X1

24.576MHz_16P_1BG24576CKIA

1 2

R5C832XO

SD,MMC,MS,XD muti-function pin define

MDIO
PIN Name
MDIO00

MDIO01
MDIO02
MDIO03
MDIO04
MDIO05
MDIO06
MDIO07
MDIO08
MDIO09 SDCCLK

+3V_PHY

MDIO10
MDIO11
MDIO12

1

C360

C361

2

10U_0805_6.3V6M

1

C362

2

0.01U_0402_16V7K

9/21

1

C363

2

0.01U_0402_16V7K

1

C364

2

1000P_0402_50V7K

MDIO13
MDIO14
MDIO15
MDIO16

1000P_0402_50V7K

MDIO17
MDIO18
MDIO19

Function set pin define

UDIO3 XDENMSENUDIO4 Function

Pull-up Enable SD,MMC CardPull-up Pull-down

UDIO3
UDIO4
UDIO5

MSEN
XDEN

SDDATA0_MSDATA0
SDDATA1_MSDATA1
SDDATA2_MSDATA2
SDDATA3_MSDATA3

MMC_D4
MMC_D5
MMC_D6
MMC_D7

SDCLK_MMCCLK
SD_MMC_CMD

JP16

7

D0

8

D1

9

D2

1

D3

10

D4

11

D5

12

D6

13

D7

5

CLK

2

CMD

TAI_PSDBT0-16GNBS7N14N0_15P

Pull-down

R373 10K_0402_5%

1 2

R374 10K_0402_5%

1 2

R375 100K_0402_5%

1 2

R371 10K_0402_5%

1 2

R376 10K_0402_5%

1 2

Modify to same as Meson. 9/13

VDD

WP

CD

VSS2
VSS1
VSS3
VSS4

4

14
15

6
3
16
17

SD Card
PIN Name
SDCD#

SDWP#
SDPWR0
SDPWR1
SDLED#

SDCCMD

SDCDAT0
SDCDAT1
SDCDAT2
SDCDAT3

SD_WP
SD_CARD_DET#

+3VS

2

1

C550

100P_0402_50V8J

MMC Card
PIN Name
MMCCD#

MMCPWR

MMCLED#

MMCCMD
MMCCLK
MMCDAT

R379

1 2

150K_0402_5%

1

MS Card
PIN Name

MSCD#

MSWR

MSLED#
MSEXTCK
MSBS
MSCCLK
MSCDAT0
MSCDAT1
MSCDAT2
MSCDAT3

+SD_MMC_3VCC

1

2

C548

C549

4.7U_0805_10V4Z

0.1U_0402_16V4Z

XD Card
PIN Name
XDCD0#

XDCD1#
XDCE#
XDR/B#
XDPWR
XDWP#
XDLED#

XDWE#
XDRE#
XDCDAT0
XDCDAT1
XDCDAT2
XDCDAT3
XDCDAT4
XDCDAT5
XDCDAT6
XDCDAT7
XDCLE
XDALE

Near to JP9.

R390

Layout Note:
Add GND shield for 1394.

GND
GND
GND

IEEE1394_TPBN0
IEEE1394_TPBP0
IEEE1394_TPAN0
IEEE1394_TPAP0

1 2

R389

56.2_0402_1%

A A

IEEE1394_TPBIAS0

5

4

C372

R394

1 2

1

2

0.01U_0402_16V7K

56.2_0402_1%

Reserve them for test

1 2

if any EMI issue. 9/14

56.2_0402_1%
R546 0_0402_5%

R547 0_0402_5%
R568 0_0402_5%
R569 0_0402_5%

1 2

R395 56.2_0402_1%

1

C373

2

0.33U_0603_16V4Z

1 2
1 2
1 2
1 2

JP17

SUYIN_020115FB004S512ZLCONN@

1
2
3
4

Layout Note: Shield GND for
IEEE1394_TPA and TPB

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETAR Y PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM TH E CUSTODY OF THE COM PETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFOR MATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITH OUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC .

3

TPB­TPB+
TPA­TPA+

GND
GND
GND
GND

5
6
7
8

2006/08/04 2006/10/06

SDPWR0_MSPW R _XDPW R

Compal Secret Data

Deciphered Date

+3VS

U15

3

VIN

4

VIN/CE

2

1

C368

2

0.1U_0402_16V4Z

2

GND

RT9701CB_SOT25

+SD_MMC_3VCC +S D_MMC_3VCC

1

VOUT

5

VOUT

1

C369

2

1U_0603_10V4Z

Title

Size Document Number R e v

Custom

Date: Sheet

40mil

1

1

12

2

2

C370

10U_0805_10V4Z

C371

0.1U_0402_16V4Z

R392

150K_0402_5%

Compal Electronics, Inc.

1394+3 in 1 Card

LA-4021P

1

0.1

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27 45Monday, October 29, 2007

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A

B

C

D

E

AMP. FOR INTERNAL SPEAKER

1

R_SPK+
R_SPK-

D18

2

3

1

1

C378

2

2

100P_0402_50V8J

ACES_85204-02001

C379

100P_0402_50V8J

JP18

1

1

2

2

3

G1

4

G2

PACDN042_SOT23~D@

TPA6044 no longer needed. So delete BOM options & co-layout

1 1

components for TPA6044. SGND and SGND1 nets can also be
deleted. Only TPA6041 will be supported. 9/5

VDDA_CODEC

C3740.1U_0402_16V4Z

1

2

+5VALW

Close to Pin29

C3761U_0603_10V4Z

1

2

Close to Pin30

C37510U_0805_10V4Z

1

2

Change in 9/26

VDDA_CODEC

R412
10K_0402_5%

2 2

3 3

4 4

SB_SPKR22

Delete PCM_SPK, Q32, R407, C387, R409.
Leave circuitry to support SB_SPKR. 10/8

DOCK_LINE_IN_L34
DOCK_LINE_IN_R34

VDDA_CODEC

12

R423

20_0402_5%

MIC_BIAS_IN

2

C413

4.7U_0805_10V4Z

1

Place close to U14

C416 0.1U_0805_25V7M

C420 0.1U_0805_25V7M

C421 0.1U_0805_25V7M

C423 0.1U_0805_25V7M

R437 0_1206_5%

12

C402

0.1U_0402_16V4Z

13

D

Q33

2

2N7002_SOT23

G

S

R415 4.7K_0402_5%
R417 4.7K_0402_5%
R418 4.7K_0402_5%
R420 4.7K_0402_5%

INT_MIC129
INT_MIC229

12

12

12

12

12

GNDAGND

A

R413
100K_0402_5%

1 2

1 2

12
12
12
12

VDDA_CODEC

R430 2.67K_0402_1%

1 2

R431 2.67K_0402_1%

1 2

0.1U_0402_16V4Z

C388 0.1U_0402_16V4Z

R41010K_0402_5%

C3910.01U_0402_16V7K

12

2

1

DLINE_IN_R_L DLINE_IN_RC_L

DLINE_IN_R_R DLINE_IN_RC_R

C409 1U_0603_10V4Z

1 2

C410 1U_0603_10V4Z

1 2

MIC129
MIC229

AC97_RST#_CODEC21

AC97_SYNC_CODEC21

AC97_SDOUT_CODEC21

2

C424

1

LINE_OUTL
LINE_OUTR

MONO_IN_HD

1 2

C396

1

2

1 2

C405 1U_0603_10V4Z

1 2

C407 1U_0603_10V4Z

LINE_OUTL

LINE_OUTR
INT_MICL_C
INT_MICR_C

C412 1U_0603_10V4Z

1 2

MIC1_C

1 2

C414 1U_0603_10V4Z
C415 1U_0603_10V4Z

2

1

1 2

DVCORE

C425

4.7U_0805_10V4Z

B

MIC2_C
SENSE_A

SENSE_B

LINE_C_OUTR

12

C381 1U_0603_10V4Z

LINE_C_OUTL

12

C384 1U_0603_10V4Z

VDDA_CODEC

C397

C398

1

1

2

2

U17

10U_0805_10V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

14
15
16
17
23
24

19
21
22
13

34

11
10

5

48

7

AD1984JCPZ-RL_LFCSP48_7X7

1 2
1 2

38

AVDD125AVDD2
AUX1
AUX2
AUX3
AUX4
LINE_IN_L
LINE_IN_R

CD_GND
MIC1

GPIO_1/MIC_BIASE-E
MIC2
SENSE_A/SRC_B

SENSE_B/SRC_A

RESET#
SYNC
SDATA_OUT

S/PDIF_OUT

DVSS

R405 17.4K_0603_1%

12

2 1

MIC_BIAS_B
MIC_BIAS_C

2007/05/29 2008/05/29

1 2

C385 0.47U_0402_6.3V6K
C386 0.47U_0402_6.3V6K

R424 10_0402_5%@

AC97_BITCLK_CODEC 21

R425 33_0402_5%

12

12
12

12

C389 0.47U_0402_6.3V6K

12

C390 0.47U_0402_6.3V6K

+5VALW

C39410U_0805_10V4Z

1

2

R416 60.4_0402_1%
R419 60.4_0402_1%

R421 10K_0402_5%

1 2

R422 10K_0402_5%

1 2

12

12

VDDA_CODEC

A_SD

1

1

C4181U_0603_10V4Z

C4190.1U_0402_16V4Z

2

2

Compal Secret Data

Deciphered Date

1

2

SENSE_A29

LINE_OUT

L_SPK-

C3951U_0603_10V4Z

2
1
3
4
5
6
7
8

12
12

C411 10P_0402_25V8K@

1 2

AC97_SDIN0 21

EAPD 33

A_SD 33

DVCORE

MIC_BIAS_IN

33

1

LINE_OUT_L

MIC_BIAS_IN

LINE_OUT_R

MONO_OUT
HP_LOUT_L
HP_LOUT_R

GPIO_0/EAPD

MIC_BIAS_B
MIC_BIAS_C

R404

0_0402_5%

R406

0_0402_5%

3

DVIO

DVCORE

BIT_CLK

SDATA_IN

GPIO_2
DM_1/DM_2
DM_3/DM_4

DM_CLK

VREF_FILT

PCBEEP

AVSS1
AVSS2

+3VS

N/C
N/C
N/C
N/C
N/C
N/C
N/C

9

DVDD

+3VS_CODEC

35
36
32
39
41

6
8

47
31
30
2
4
46

27
28

29
12
18

20
37
43
44
40
45

26
42

C382 2.2U_0603_16V6K

R411
0_0805_5%

12

C400

C399

1

2

1

2

0.1U_0402_16V4Z

C401

4.7U_0805_10V4Z

2

1

0.1U_0402_16V4Z

+

C406 47U_B2_6.3V-M

1 2

+

C408 47U_B2_6.3V-M

1 2

Correct net name. 10/02

HP_IN_L
HP_IN_R

AC97_SDIN0_CODEC

R427 0_0402_5%
R571 15K_0402_1%

1 2

D37 CH751H-40_SC76

Add R571, D37 in 9/26.

AUD_REF

MONO_IN_HD

PIN42

Security Classification

Issued Date

THIS SHEET OF EN GINEE RING D RAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR DISCLO SED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

+5VALW

R400100K_0402_5%

R401100K_0402_5%

12

12

+5VALW

VDDA_CODEC

GAIN0

GAIN1

32

33

TML
SPKR_RIN+
SPKR_RIN­SPKR_LIN+
SPKR_LIN­SPGND
LOUT+
LOUT­SPVDD

SENSE_A

R434

0_0402_5%@

SENSE_B SENSE_A_C

D

29

30

VDD

GAIN031GAIN1

REG_OUT

C1N

CPVDD

CPGND

C1P10CPVSS13HP_OUTL

9

12

11

1

C403

2

1U_0603_10V4Z

L7

12

CHB1608B121YZF_0603
L8

12

CHB1608B121YZF_0603

12

1

C417
1U_0603_10V4Z

2

R435

39.2K_0402_1%

1 2

1

C422
1U_0603_10V4Z

2

Change value. 9/28

C377 2.2U_0603_16V6K
C380 2.2U_0603_16V6K

HP_INL

HP_INR

26

27

28

25

SGND

HP_INL

HP_INR

REG_EN

SPKR_EN#

HPVSS

HP_OUTR

14

15

16

1

C404

2

1U_0603_10V4Z

HP_DET29

R432 39.2K_0402_1%

1 2

R433 20K_0402_1%

1 2

Title

Size Document Number Rev

Date: Sheet

GAIN1

R402 0_0402_5%@

GAIN0

R403 0_0402_5%@

1 2
1 2

SLP_S3# 22,24,26,33,36,41,42,44

U16
TPA6041A4RHBR QFN 32P

24

BYPASS

23
22

HP_EN

21

SPGND

20

ROUT+

19

ROUT-

18

SPVDD

17

HPVDD

HP_OUTL 29
HP_OUTR 29

DLINE_OUT_L 34

DLINE_OUT_R 34

HP_EN

Q36

13

D

2N7002_SOT23

G

S

100K_0402_5%

2

C383 0.47U_0402_6.3V6K

12

A_SD
HP_EN

1 2

R408 100K_0402_5%@

R_SPK+
R_SPK-L_SPK+

1

C3921U_0603_10V4Z

2

+5VALW

R426

100K_0402_5%
R429

0_0402_5%

1 2

SENSE_A_A
SENSE_A_B

D

S

12

1

R436

2

Compal Electronics, Inc.

AC97 CODEC AD1981HD

LA-4021P

12
12

HP_IN_L
HP_IN_R

+5VALW

1

C39310U_0805_10V4Z

2

1 2

2

G

Q35

13

2N7002_SOT23

2

G

C426

0.1U_0603_50V4Z

E

+5VALW

SENSE_A_A

13

D

Q34
2N7002_SOT23

S

MIC_SENSE 29

LINE_IN_SENSE 34

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A

R439

60.4_0402_1%

1 2

1 2

R443
10K_0402_5%

1 2

1 2

R440

60.4_0402_1%

HP_OUTR28
HP_OUTL28

R442

1 1

10K_0402_5%

L9
CHB1608B121YZF_0603

1 2
1 2

L10
CHB1608B121YZF_0603

Modify to same as Meson. 10/02

MIC_BIAS_B

1 2

R447 3.9K_0402_1%

1 2

R448 3.9K_0402_1%

2 2

EXT_MICB
EXT_MICA

MIC_SENSE28

L11
CHB1608B121YZF_0603

1 2
1 2

L12
CHB1608B121YZF_0603

HP_DET28

C428

1

2

47K_0402_5%

MIC_SENSE

C430

1

2

B

C429

1

2

470P_0402_50V7K

470P_0402_50V7K

VDDA_CODEC

R445

C431

1

2

470P_0402_50V7K

470P_0402_50V7K

12

1

2

HP_OUT_L

C432

0.1U_0402_16V4Z

C

JP19

5
4
3

6
2
1

FOX_JA6033L-B5S3-7F_6PCONN@

D19

3

1

2

PACDN042_SOT23~D@

JP20

5
4
3

6
2
1

FOX_JA6033L-B5S3-7F_6PCONN@

SENSE_A28

4.7U_0805_10V4Z

R438

5.1K_0603_1%

1 2

VDDA_CODEC

1

C433

2

12

12

VDDA_CODEC

+5VALW

R449
47K_0402_5%

R451
47K_0402_5%

D

S

D

Q37

13

2N7002_SOT23

2

G

12

R441

4.7K_0402_5%

R444 0_0402_5%

1 2

R446 0_0402_5%@

1 2

4

3

P

+

1

OUT

TLV2464_TSSOP14

2

-

G

U19A

11

DOCK_HPS# 34

2

C427

0.1U_0402_16V4Z

1

+V_AMP

CODEC_REF+V_AMP

R450 100_0402_5%

1 2

1

C434

4.7U_0805_10V4Z

2

E

EXTERNAL MICROPHONE/LINE OUT JACK

EXT_MICA_2

CODEC_REF

1

C437

2

L13

EXT_MICA EXT_MICA_1

3 3

12

C439 0.47U_0402_6.3V6K

HLC0603CSCCR10JT_0603

1 2

MIC_BIAS_C

1 2

R454 10K_0402_5%

1

C441
68P_0402_50V8J

2

100P_0402_50V8J

3
2

1 2

C435 100P_0402_50V8J

1 2

R453 100K_0402_5%

VDDA_CODEC

4

P

+

1

OUT

-

G

U18A
TLV2464_TSSOP14

11

MIC1

AMP. FOR EXTERNAL MICROPHONE

L14

MIC1 28

EXT_MICB EXT_MICB_1

12

C440 0.47U_0402_6.3V6K

HLC0603CSCCR10JT_0603

1 2

1 2

R455 10K_0402_5%

1

C442
68P_0402_50V8J

2

R457

JP21

ACES_85204-04001CONN@

INT_MIC_1_2

1

1

2

2

INT_MIC_2_2

3

3

4

4

5

G1

6

G2

VDDA_CODEC

4 4

R463 3K_0402_5%

INT_MIC_1_1 INT_MIC_1_3

1 2

3K_0402_5%

R464
3K_0402_5%

1 2

1

C453
1U_0603_10V4Z

2

A

R458
3K_0402_5%

1 2

1 2

L16
HLC0603CSCCR10JT_0603

1 2

1 2

C450 0.068U_0603_16V7K

R465
10K_0402_5%

1 2

1

C454
68P_0402_50V8J

2

INT_MIC_1_4

CODEC_REF

1

C447

2

B

100P_0402_50V8J

C444 220P_0402_50V7K

1 2

1 2

R459 100K_0402_5%

VDDA_CODEC

1

C448

4

2

+

OUT

-

11

0.1U_0402_16V4Z

P

8

G

U18C
TLV2464_TSSOP14

INT_MIC128

10

9

AMP. FOR INTERNAL MICROPHONE

VDDA_CODEC

INT_MIC_2_1 INT_MIC_2_3

1 2

R460 3K_0402_5%

Security Classification

Issued Date

THIS SHEET OF EN GINEE RING D RAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR DISCLO SED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2007/05/29 2008/05/29

INT_MIC_2_2

R461
3K_0402_5%

1 2

1

C451
1U_0603_10V4Z

2

Compal Secret Data

Deciphered Date

1 2

C449 0.068U_0603_16V7K

L15
HLC0603CSCCR10JT_0603

1 2

D

1

2

EXT_MICB_2

CODEC_REF

1

C438

2

100P_0402_50V8J

5
6

INT_MIC_2_4

CODEC_REF

1

C445

2

R462
10K_0402_5%

1 2

C452
68P_0402_50V8J

Title

Size Document Number Rev

LA-4021P

Date: Sheet

1 2

C436 100P_0402_50V8J

1 2

R452 100K_0402_5%

VDDA_CODEC

4

P

+

OUT

-

G

11

100P_0402_50V8J

12
13

MIC2

7

U18B
TLV2464_TSSOP14

C443 680P_0402_50V7K

1 2

1 2

R456 100K_0402_5%

VDDA_CODEC

1

C446

4

2

0.1U_0402_16V4Z

P

+

14

OUT

TLV2464_TSSOP14

-

G

U18D

11

INT_MIC228

Compal Electronics, Inc.

AMP & Audio Jack

E

MIC2 28

0.1

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SWITCH BOARD.

I2C_CLK33
I2C_DAT33
I2C_INT33

AC97_SDOUT_MDC21

AC97_SYNC_MDC21

AC97_SDIN121

AC97_RST#_MDC21

+3VL +3VS +3VL

R4665.1K_0402_5%

R4675.1K_0402_5%

12

12

CAP_RST_EC33

WL/BT_LED19

12

R468

10K_0402_5%

STB_LED19,34

MDC 1.5 Conn.

AC97_SDOUT_MDC
AC97_SYNC_MDC

AC97_SDIN1_MDC

1 2

R469 33_0402_5%

JP25

ACES_88266-02001CONN@

MOD_RING

1

1

MOD_TIP

2

2

3

G1

4

G2

JP23

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

11

GND1

12

GND2

ACES_87213-1000G

JP24

ACES_88025-120L_12PCONN@

1
3
5
7
9

11

1
3
5
7
9
11

GND13GND14GND15GND16GND17GND

2

2

4

4

6

6

8

8

10

10

R470 0_0402_5%

12

12

18

Change design at 10/12.

RJ-11 Conn.

MOD_TIP
MOD_RING

2

2

C459

220P_1808_3KV@

C460

220P_1808_3KV @

1

1

+3VS

C458

1 2

10P_0402_25V8K@

+3VS

1

1

1

C455

12

JP26

1

TIP

2

RING

3

GND

4

GND

ACES_85204-02001_2PCONN@

AC97_BITCLK_MDC 21

2

C457

C456

2

2

4.7U_0805_10V4Z@

0.1U_0402_16V4Z

1000P_0402_50V7K

LEFT
RIGHT

INT_KBD CONN.

KSO[0..11]
KSI[0..7]

KSO11

KSO0
KSO2
KSO5

KSI_D_14
KSI_D_8
KSI_D_12
KSI_D_10

KSI_D_0
KSI_D_4
KSI_D_2
KSI_D_1

D21

KSI_D_0

2

KSI_D_8

3

DAP202U_SOT323-3
D23

KSI_D_1

2

KSI_D_9

3

DAP202U_SOT323-3
D25

KSI_D_2

2

KSI_D_10

3

DAP202U_SOT323-3

100P_1206_8P4C_50V8@

100P_1206_8P4C_50V8@

100P_1206_8P4C_50V8@

KSO11
KSO0
KSO2
KSO5
KSI_D_14
KSI_D_8
KSI_D_12
KSI_D_10
KSI_D_0
KSI_D_4
KSI_D_2
KSI_D_1
KSI_D_3
KSO3
KSO8
KSO4
KSO7
KSO6

KSO10

KSO1
KSI_D_5
KSI_D_6

KSI7

KSI_D_13
KSI_D_11
KSI_D_9

KSO9

KSO[0..11]33
KSI[0..7]33

JP22

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

11

11

12

12

13

13

14

14

15

15

16

16

17

17

18

18

19

19

20

20

21

21

22

22

23

23

24

24

25

25

26

26

27

27

28

28

29

29

30

30

31

GND1

32

GND2

HRS_FH28-60(30)SB-1SH(86)CONN@

KSI0

1

KSI1

1

KSI2

1

CP1

2
3
4 5

CP3

2
3
4 5

CP5

2
3
4 5

81
7
6

81
7
6

81
7
6

KSI3

KSI4

KSI5

KSI6

KSI_D_3
KSO3
KSO8
KSO4

KSO7
KSO6

KSO10

KSO1

KSI_D_5
KSI_D_6
KSI7
KSI_D_13

KSI_D_11
KSI_D_9
KSO9

D20

1

DAP202U_SOT323-3
D22

1

DAP202U_SOT323-3
D24

1

DAP202U_SOT323-3
D26

1

DAP202U_SOT323-3

2
3
4 5

100P_1206_8P4C_50V8@

2
3
4 5

100P_1206_8P4C_50V8@

2
3
4 5

100P_1206_8P4C_50V8@

2
3
4 5

100P_1206_8P4C_50V8@

KSI_D_3

2

KSI_D_11

3

KSI_D_4

2

KSI_D_12

3

KSI_D_5

2

KSI_D_13

3

KSI_D_6

2

KSI_D_14

3

CP2

CP4

CP6

CP7

81
7
6

81
7
6

81
7
6

81
7
6

Power button

2

A

ON/OFF# 34

+3VL

NC

1

5

U20
SN74LVC1G14DCKR_SC70-5

V

4

1 2

Y

R473

G

100K_0402_5%

3

C464
1U_0603_10V4Z

SF10402ML080C_0402@

SW1
1BT002-0121L_4P

3
4

2

D27

1

1
2

5

6

+3VL +5VS

12

R472

ON/OFF#

100K_0402_5%

1

C463

1U_0603_10V4Z

2

+3VL

12

R471
100K_0402_5%

D28

21

CH751H-40_SC76

ON/OFFBTN_KBC# 33

1 2

R474 100K_0402_5%

13

D

2

G

Q38

S

1

2

2N7002_SOT23

TrackPoint CONN.

RIGHT
LEFT

SP_CLK33

+3VALW

ON/OFFBTN# 22

Security Classification

Issued Date

THIS SHEET OF EN GINEE RING D RAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR DISCLO SED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2005/03/10 2006/03/10

SP_DATA33

+5VS

Compal Secret Data

JP27

1
2
3
4
5
6
7
8

ACES_87151-0807G

CONN@

Deciphered Date

+5VS +5VS

1
2
3
4
5
6
7
8

1

C462

0.1U_0402_16V4Z

2

T/P BOARD.

JP28

TP_CLK33

TP_DATA33

2

Title

Size Document Number Rev

LA-4021P

Date: Sheet

1
2
3
4

5
6

CONN@

3

D39

1

ACES_87151-04051_4P

UESD3.3DT5G SOT-723@

Compal Electronics, Inc.

MDC/KBD/ON_OFF/LID

1

C461

0.1U_0402_16V4Z

2

30 45Monday, October 29, 2007

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5

4

3

2

1

BT Connector

D D

+5VALW

S4_STATE#

4.7U_0805_10V4Z

C C

S4_STATE#

4.7U_0805_10V4Z

C465

1

2

+5VALW

C474

U21

1

GND

2

IN

3

IN
EN#4OC#

G548A2P1U

(2A,100mils ,Via NO.=4)

U22

1

GND

2

IN

3

IN

1

2

EN#4OC#

G548A2P1U

(2A,100mils ,Via NO.=4)

OUT
OUT
OUT

OUT
OUT
OUT

8
7
6
5

8
7
6
5

R476
10K_0402_5%

1 2

R481
10K_0402_5%

1 2

W=100mils

1

+

2

W=100mils

1

+

2

USB_VCCA+5VALW

JP30

1

1

USB20_N022
USB20_P022

1

1

C466

2

220U 6.3V M F60

C475

220U 6.3V M F60

C468

C467

2

0.1U_0402_16V4Z
1000P_0402_50V7K

USB_VCCB+5VALW

USB20_N422

1

2

USB20_P422

1

C476

C477

2

0.1U_0402_16V4Z
1000P_0402_50V7K

2

3

D29

1

PACDN042_SOT23~D

@

2

3

1

PACDN042_SOT23~D

@

2

2

3

3

4

4

5

GND

6

GND

7

GND

8

GND

SUYIN_020173MR004S558ZL_4PCONN@

JP31

1

1

2

2

3

3

4

4

5

D30

G1

6

G2

ACES_85204-04001CONN@

JP29

1
2

USB20_P6_R

3

USB20_N6_R

4
5
6
7
8

ACES_87213-0800G_8PCON N@

BT_OFF22

R475 0_0402_5%
R477 0_0402_5%

12

R480
10K_0402_5%

R482

1 2

220K_0402_1%

12
12

Q39
SI2301BDS_SOT23

S

G

2

+3VAUX_BT

D

13

+3VAUX_BT+3VALW

C4710.1U_0402_16V4Z

1

2

USB20_P6 22
USB20_N6 22
BT_LED 19

C47210U_0805_10V4Z

1

2

B B

+3VALW

USB CONNECTOR 3

R356
10K_0402_5%

C321

1 2

12

R485

1K_0402_5%

1

1

C484

2

2

1000P_0402_50V7K

S4_STATE#
FAULT

1

1

1

2

2

C485

2

C486

2200P_0402_50V

C487

1000P_0402_50V7K

1000P_0402_50V7K

S4_STATE#22

A A

13
11
12

3
4

2
6
9

0.1U_0402_16V4Z

U23

ENABLE
FAULT

ISET

PWRGD

ISENSE

TIMER

GATE

VREG
DGND

DISCH

AGND

VSENSE

AGND

TPS2331IPWRG4_TSSOP14

+5VALW USB_VCCC

1

2

C478

2.2U_0805_16V4Z

8

IN

USB_ISENSE1

10

USB_ISENSE2

7
1
14
5

5

4

3.75A nominal with 3.5A minimum

R483

0.01_2512_1%

1 2

C479

1

2

0.1U_0402_16V4Z

12

R484
1K_0805_1%

Security Classification

Issued Date

THIS SHEET OF EN GINEE RING D RAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR DISCLO SED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Q40

8
7
6
5

3

1

S

D

2

S

D

3

S

D

4

G

D

SI4800DY_SO8

1

C483

2

0.1U_0402_16V4Z

2006/02/13 2006/07/26

Compal Secret Data

W=160mils

1

C480

+

2

USB20_N522
USB20_P522

Deciphered Date

1

C481

2

220U_D_6.3VM

0.1U_0402_16V4Z

1

C482

2

1000P_0402_50V7K

2

3

D31PACDN042_SOT23~D

1

@

2

JP32

1

1

2

2

3

3

4

4

5

GND

6

GND

7

GND

8

GND

SUYIN_020173MR004S558ZL_4PCONN@

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

USB & BT Connector

LA-4021P

31 45Monday, October 29, 2007

1

0.1

of

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5

Finger printer

4

3

2

+3VS

+3VALW

1

TPM1.2 on board

D D

+3VALW

Q42
SI2301BDS_SOT23

S

D

13

G

2

R486
10K_0402_5%

1 2

R487
220K_0402_1%

FPR_OFF22

C C

B B

BIOS ROM

7/20

+3VL

20mils

SPI_CLK_JP34 SPI_CLK_JP34
SPI_SI_JP34

A A

1 2

7/20

1

C496

0.1U_0402_16V4Z

R501 3.3K_0402_5%

1 2

SPI_CS0#33

R503 0_0402_5%
R504 0_0402_5%

1 2

R507 0_0402_5%

1 2

R56 0_0402_5%

1 2

2

SPI_CLK33

SPI_SI33

12

1

1

C56310U_08 05_10V4Z

C4920.1U_0402_16V4Z

2

2

+3VL

20mils

SPI_WP#
SPI_HOLD#_0
SPI_CS0#
SPI_CLK

SPI_SI SPI_SO_R
SPI_CS0#SPI_CS0#_JP34
SPI_CLK

SPI_SO_RSPI_SO_JP34

USB20_N822
USB20_P822

PACDN042_SOT23~D@

U25

8

VCC

3

W

7

HOLD

1

S

6

C

5

D

WIESO_G6179-100000_8P

7/20

20mils

+3VL

VSS

Q

USB20_N1_PWR

2

3

D32

1

4

45@

1 2

R502 15_0402_5%

SPI_WP#

2

R505 3.3K_0402_5%

JP33

1

1

2

2

3

3

4

4

E&T_3801-04conn@

&U1

SST25LF080A_SO8-200mil

1 2

R506 0_0402_5%@

1 2

SPI_SO 33

R489 10K_0402_5%

1 2

LPC_PD#22

R492 0_0402_5%

R497

4.7K_0402_5%@

R498

0_0402_5%

+3VS

12

12

12

C494 18P_0402_50V8J

32.768KHZ_12.5P_1TJS125BJ2A251
C495 18P_0402_50V8J

12

C493

10P_0402_50V8K@

PM_CLKRUN#22,27,33

12

Y4

2

NC

3

NC

12

Add SIRQ and connect to
pin5. 10/08

8051_RECOVER#

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
LPC_FRAME#
PLT_RST#

SIRQ

CLK_PCI_TCG16

12

R494 10_0402_5%@

TPM_XTALO
TPM_XTALI

1

IN

4

OUT

+3VL

12

R500

100K_0402_5%

CLK_PCI_DB16

LPC_FRAME#21,26,33

8051_RECOVER#33

VCC1_PWRGD33,35,39

Add in 10/10.

KBC_SPI_CS1#_R22,33

Pin3, 23 tie to GND. 10/10

PLT_RST#8,20,26

LPC_AD021,26,33
LPC_AD121,26,33
LPC_AD221,26,33
LPC_AD321,26,33

8051TX33

8051RX33

1

C488

2

0.1U_0402_16V4Z

TPM_XTALI

12

R499
10M_0402_5%

TPM_XTALO

SIRQ22,27,33

1

1

C489

C490

2

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

10

19

24

U24

26

LAD0

23

LAD1

20

LAD2

17

LAD3

22

LFRAME#

16

LRESET#

28

LPCPD#

27

SERIRQ

21

LCLK

SLB 9635 TT 1.2

15

CLKRUN#

7

PP

14

XTALO

13

XTALI/32K IN

5

VDD

VDD

VDD

GPIO

GPIO2

TEST1

TESTB1/BADD

GND

GND

GND

GND

SLB 9635 TT 1.2_TSSOP28

4

11

18

25

VSB

LPC Debug Port

B+

SIRQ

8051_RECOVER#

SPI_CS0#_JP34
SPI_SI_JP34SPI_SI
SPI_SO_JP34
SPI_HOLD#_0

1

C491

2

0.1U_0402_16V4Z

TPM_GPIO

6

TPM_GPIO2

2

Base I/O Address
0 = 02Eh
1 = 04Eh*

8
9

3

NC

12

NC

1

NC

JP34

1

Ground

2

LPC_PCI_CLK

3

Ground

4

LPC_FRAME#

5

+V3S

6

LPC_RESET#

7

+V3S

8

LPC_AD0

9

LPC_AD1

10

LPC_AD2

11

LPC_AD3

12

VCC_3VA

13

PWR_LED#

14

CAPS_LED#

15

NUM_LED#

16

VCC1_PWRGD

17

SPI_CLK

18

SPI_CS#

19

SPI_SI

20

SPI_SO

21

SPI_HOLD#

22

Reserved

23

Reserved

24

Reserved

ACES_87216-2404_24P

conn@

R495
0_0402_5%

R490

4.7K_0402_5%

12

4.7K_0402_5%@

+3VS+3VS

12

T83PAD
T84PAD

12

R496

5

4

Security Classification

Issued Date

THIS SHEET OF EN GINEE RING D RAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR DISCLO SED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/03/10 2006/03/10

Compal Secret Data

Deciphered Date

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

TCG/BIOS ROM/PS2/SW LPC DEBUG

LA-4021P

1

of

32 45Monday, October 29, 2007

0.1

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+3VL

+3VL

+3VL

RP18

KSI0

1 8

KSI3

2 7

KSI2

3 6

KSI1

4 5

10K_1206_8P4R_5%

RP19

KSI7

1 8

KSI6

2 7

KSI5

3 6

KSI4

4 5

10K_1206_8P4R_5%

+5VS

TP_CLK

1 2

R521 10K_0402_5%

TP_DATA

1 2

R524 10K_0402_5%

RP20

SP_CLK

1 8

SP_DATA

2 7

PS2_CLK

3 6

PS2_DATA

4 5

10K_1206_8P4R_5%

+3VS

RUNSCI_EC#

1 2

R533 10K_0402_5%

R537 2M_0402_5%@

1 2

1

4

IN

OUT

1

NC3NC

2

2

C506 18P_0402_50V8J

32.768KHZ_12.5P_1TJS125BJ2A251

Y5

Change in 10/08

1

C499

0.1U_0402_16V4Z

R539
120K_0402_5%

12

Add in 9/26

1

2

C507 18P_0402_50V8J

R520

1 2

0_0402_5%@

0.1U_0402_16V4Z

2

KSO[0..11]30

9/27

9/21

+RTCVCC

12

R542
0_0402_5%

1

1

2

2

1U_0603_10V4Z

C529

C528

1

C500

0.1U_0402_16V4Z

2

SPI_SI32

KBC_SPI_SI_R22

SPI_CS0#32

KBC_SPI_CS0#_R22

SPI_SO32

KBC_SPI_SO22

KSI[0..7]30

TP_CLK30

TP_DATA30

SP_CLK30

SP_DATA30

PM_CLKRUN#22,27,32

SIRQ22,27,32

CLK_PCI_EC16

RUNSCI_EC#22

LPC_AD321,26,32
LPC_AD221,26,32
LPC_AD121,26,32
LPC_AD021,26,32

LPC_FRAME#21,26,32

NPCI_RST#22

ADP_PS144

+VCC0

KBC_SPI_CLK_R22

SPI_CLK32

MC2_DISABLE26

KBC_SPI_CS1#_R22,32

WMC1_DISABLE26

LAN_WOL_EN22,36

2

1

0.1U_0402_16V4Z

C501

TP_CLK
TP_DATA
SP_CLK
SP_DATA
PS2_CLK
PS2_DATA

CLK_PCI_EC
RUNSCI_EC#

CRY1
CRY2

C339

4.7U_0805_10V4Z

+VCC0

1

0.1U_0402_16V4Z

2

KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11

KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7

C502

U26

128

FLDATAOUT

127

HSTDATAOUT

97

FLCS0#

96

HSTCS0#

95

FLDATAIN

94

HSTDATAIN

21

KSO0

20

KSO1

19

KSO2

18

KSO3

17

KSO4

16

KSO5

13

KSO6

12

KSO7

10

KSO8

9

KSO9

8

KSO10

7

KSO11

6

KSO12/GPIO00/KBRST

5

KSO13/GPIO18

29

KSI0

28

KSI1

27

KSI2

26

KSI3

25

KSI4

24

KSI5

23

KSI6

22

KSI7

35

IMCLK

36

IMDAT

38

KCLK

40

KDAT

41

EMCLK

42

EMDAT

55

CLKRUN#

57

SER_IRQ

54

PCI_CLK

76

EC_SCI#

51

LAD[3]

50

LAD[2]

48

LAD[1]

46

LAD[0]

52

LFRAME#

53

LRESET#

45

LPCPD#/GPIO23

70

XTAL1

71

XTAL2

68

VCC0

1

GPIO40

2

HSTCLK

3

FLCLK

30

GPIO39

31

HSTCS1#

32

FLCS1#

33

GPIO38

34

GPIO37

43

NC

44

NC

C503

1

2

1

4.7U_0805_10V4Z

2

Keyboard/Mouse Interface

Power Mgmt/SIRQ

LPC
Bus

14

106

119

VCC1

VCC139VCC158VCC184VCC1

VCC1

SMSC_1091-NU_TQFP-128P

Access Bus Interface

AGND

VSS11VSS37VSS47VSS56VSS

VSS82VSS

72

104

117

Security Classification

Issued Date

THIS SHEET OF EN GINEE RING D RAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR DISCLO SED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

R511 0_0402_5%

1

C498

2

0.1U_0402_16V4Z

49

VCC2

General Purpose I/O Interface

EA Strap#/GPIO26/KSO17

24MHZ_OUT/GPIO19/WINDMON

Miscellaneous

KBC1091-NU_TQFP128_14X14

12

Del BATSELB_A# pin since only one
battery. 10/18

GPIO28
GPIO29
GPIO30
GPIO31
GPIO32

OUT1/IRQ8#

OUT7/SMI#

OUT8/KBRST

OUT9/PWM2
OUT10/PWM0
OUT11/PWM1

GPIO01
GPIO02

GPIO03
GPIO04/KSO14
GPIO05/KSO15

GPIO07/PWM3

GPIO08/RXD

GPIO09/TXD

GPIO11/AB2A_DATA

GPIO12/AB2A_CLK

GPIO13/AB2B_DATA

GPIO14/AB2B_CLK
GPIO15/FAN_TACH1
GPIO16/FAN_TACH2

GPIO17/A20M

GPIO20/PS2CLK
GPIO21/PS2DAT

GPIO24/KSO16

GPIO27

AB1A_DATA

AB1A_CLK

AB1B_DATA

AB1B_CLK

PGM Strap/GPIO25

CLOCKI

32KHZ_OUT/GPIO22

RESET_OUT#/GPIO06

PWRGD

VCC1_PWRGD

TEST PIN

DMS_LED#/GPIO10

BAT_LED#

PWR_LED#/8051TX

FDD_LED#/8051RX

GPIO33
GPIO34
GPIO35
GPIO36

CAP

OUT0

NC
NC

+3VS

C504 4.7U_0805_10V4Z

15

R515 0_0402_5%

93
98
99
100
126

124
125

123
122
121
120
118

107
79
80
81
83

85
86
87

88
89
90
91
92
101
102

103
105
4
74

111
112

109
110

73
108

59
75
60
78
77
61

69

116
113
115
114

67
66
65
64
63
62

1 2

R517 0_0402_5%

1 2

GREEN_BATLED#

KBRST#

THM_TRAVEL#

KSO14
KSO15

PM_RSMRST#
CRACK_BGA
EC_GPIO9

AB2A_DATA
AB2A_CLK

BATCON

8051_RECOVER#

EC_GPIO27

SMB_EC_DA1
SMB_EC_CK1

AB1B_DATA
AB1B_CLK

EA#
CLK_14M_KBC
32K_CLK

PWR_GD
VCC1_PWRGD

TEST

Change to 1K. 10/03

1 2

R538 100K_0402_5%

R333 0_0402_5%@

1 2

R57 0_0402_5%

1 2

R544 0_0402_5%@

1 2

1 2

Swap BAT_PWM _ O U T a n d LAN_DISABLE_N. 10/08

T85PAD
T86PAD

T87PAD

R526 0_0402_5%

1 2

R527 0_0402_5%

1 2

R279 0_0402_5%

1 2

R516 0_0402_5%

1 2

BAT_ID# 37

GATEA20 21

D35 CH751H-40_SC76

2 1

R534 0_0402_5%

1 2

R531 1K_0402_5%

R536 1K_0402_5%

12

R545 0_0402_5%

1 2

R543 10K_0402_5%

1 2

AGND FILTER

C510 0.1U_0402_16V4Z

1 2

2006/02/13 2006/07/26

Compal Secret Data

Deciphered Date

+3VL

R512

100K_0402_5%@

1 2

SUS_PWR_ACK 22

AC_PRESENT 22

KBC_PWR_ON 39

GREEN_BATLED# 19

LAN_DISABLE_N 22
BAT_PWM_OUT 38
CHGCTRL 38

CRACK_BGA 13,23

10/24

PCI_SERR# 20,27

R519 10K_0402_5%

1 2

ON/OFFBTN_KBC# 30
LOW_BAT# 22

PM_RSMRST# 22

R604 10K_0402_5%

1 2

I2C_DAT 30
I2C_CLK 30
CELLS 38
A_SD 28

Cause VCC2 is +3VS, Del D34 & R530 at 10/05.

SMB_EC_DA1 37
SMB_EC_CK1 37

10/24

I2C_INT 30

R535 10_0402_5% @

+3VL

12

PWR_GD 35,36,42
ADP_PS0 44

ADP_ID 44
AMBER_BATLED# 19
8051TX 32
8051RX 32

+3VL

LANLINK_STATUS# 22,24,25
LID_SW# 18,19,22
CAP_RST_EC 30

PM_SLP_M# 22,36,40,41

EAPD 28

+3VL

21

D33

CH751H-40_SC76

8051_RECOVER# 32
SLP_S3# 22,24,26,28,36,41,42,44

ADP_PRES 24,38,39

PGD_IN

1 2

CLK_14M_KBC 16

PM_PWROKPGD_IN

ADP_EN 44

PM_PWROK 8,22,42,43

VCC1_PWRGD 32,35,39

9/21

LANLINK_STAT U S # n o l onger read by KBC. Add
R333 between s i gn a l and pin 65. 10/08
Install R57. 10/08

Title

Size Document Number Rev

Date: Sheet

R532 10K_0402_5%

R513

1 2

100K_0402_5%

13

GREEN_BATLED#

Del R522 cause already PU for
ADP_PS1 at P44. 10/4

KB_RST# 21

1 2

C505 10P_0402_25V8K @

1 2

2 1

D36 CH751H-40_SC76

D

Q44

2

G

2N7002_SOT23

S

EC_GPIO27

R523 100K_0402_5%

CRACK_BGA

R525 100K_0402_5%

BATCON

R322 100K_0402_5%

THM_TRAVEL#

R320 100K_0402_5%

Add in 10/03.

SMB_EC_CK1
SMB_EC_DA1
AB1B_CLK
AB1B_DATA

VCC1_PWRGDPM_PWROK

Compal Electronics, Inc.

KBC1091

LA-4021P

G_BATLED# 21

1 2
1 2
1 2
1 2

RP21

4.7K_1206_8P4R_5%

1 8
2 7
3 6
4 5

of

33 45Monday, October 29, 2007

+3VL

+3VL

0.1

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10/23

VA

C5110.1U_0402_50V

1

2

C5120.1U_0402_50V

1

2

C5130.1U_0402_50V

1

2

C5140.1U_0402_50V

1

2

C5150.1U_0402_50V

1

2

C5160.1U_0402_50V

1

2

C5170.1U_0402_50V

1

2

1

2

C5180.1U_0402_50V

DOCKING CONNECT

JP35

56

10/23

BLUE_R
GREEN_R
RED_R
PREP#

53

53

51

51

49

49

47

47

45

45

43

43

37

37

35

35

33

33

31

31

29

29

27

27

25

25

23

23

21

21

19

19

17

17

15

15

13

13

11

11

9

9

7

7

5

5

3

3

1

1

VA

MDO0+25

MDO0-25

MDO1+25

MDO1-25

+5VALW +5VALW

+5VS

USB20_P922
USB20_N922

STB_LED19,30

DLINE_OUT_L28
DLINE_OUT_R28

T125
T126

Del R610, Q43. 10/24

FOX_QL0127L-C24E51-4F_54P-TCONN@

56

54

54

52

52

50

50

48

48

46

46

44

44

38

38

36

36

34

34

32

32

30

30

28

28

26

26

24

24
22
20
18
16
14
12
10

8
6
4
2

55

55

PREP#

22
20
18
16
14
12
10
8
6
4
2

MDO2+ 25
MDO2- 25
MDO3+ 25
MDO3- 25

LANLINK_STATUS#_DOCK 25
LAN_ACT#_DOCK 25

ADP_SIGNAL 37,44

ON/OFF# 30

PREP# 22,25
D_DDCDATA 17
D_DDCCLK 17

D_HSYNC 17

D_VSYNC 17

LINE_IN_SENSE 28

DOCK_HPS# 29

DOCK_LINE_IN_L 28

DOCK_LINE_IN_R 28

Change for can 't charge issue. 10/24

+3VS +3VS+3VS

C521

0.1U_0402_16V4Z

1 2

RED_R17

RED17

ISO_PREP#22

RED_R
RED

ISO_PREP#

U29

5

VCC

1

A

2

B

4

OE

3

GND

FSA66P5X_SC70-5

GREEN_R17

GREEN17

Security Classification

Issued Date

THIS SHEET OF EN GINEE RING D RAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR DISCLO SED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C519

0.1U_0402_16V4Z

1 2

GREEN_R
GREEN

ISO_PREP#

U27

5
1

2
4
3

FSA66P5X_SC70-5

9/21

RED_R RED
GREEN_R
BLUE_R

1 2

R548 0_0402_5%@

1 2

R549 0_0402_5%@

1 2

R550 0_0402_5%@

2005/03/10 2006/03/10

VCC
A

B
OE
GND

GREEN
BLUE

Compal Secret Data

Deciphered Date

BLUE_R17

BLUE17

C520

0.1U_0402_16V4Z

1 2

BLUE_R

BLUE

ISO_PREP#

U28

5

VCC

1

A

2

B

4

OE

3

GND

FSA66P5X_SC70-5

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

DOCK CONN

LA-4021P

of

34 45Monday, October 29, 2007

0.1

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Update per change list. 9/14

M_PWROKM_PWROK

M_PROK41

DDR2_PG40

+1.5VS_PG41

D38 CH751H-40_SC76

+VCCP

+3VM
+0.9V

R554 10K_0402_5%

+5VS

R555 169K_0603_1%

+3VS

R559 113K_0603_0.1%

21

R478 35.7K_0402_1%

1 2

12

12

12

1 2

R560 10K_0402_5%

R561

40.2K_0402_1%

R564 10K_0402_5%
R566 76.8K_0402_1%
R509 21K_0402_1%
R386 10K_0402_5%

1 2
1 2
1 2
1 2

12

2VREF_8734

1

C526
1000P_0402_50V7K

2

12

R567

187K_0402_1%

R556 20K_0402_5%

R558 30.1K_0402_5%
R479 44.2K_0402_1%

R565 20K_0402_5%

1

C527
1000P_0402_50V7K

2

12

2VREF_393

12

12

12

2VREF_393

R551
1M_0402_5%

12

+5VALW

8

U30A

3

P

+

1

O

2

-

G

LM393M_SO8

4

1

C523
1000P_0402_50V7K

2

R562 1M_0402_5%

5
6

+5VALW

8

P

+

-

G

LM393M_SO8

4

U30B

12

7

O

+3VS

12

R553
10K_0402_5%

1 2

J6 SHORT PADS

+3VALW

12

R563
10K_0402_5%

M_PWROK

PWR_GD 33,36,42

M_PWROK 8,22

Mini Card STANDOFF WWAN Card STANDOFF

H3

H4

HOLEA

HOLEA

1

1

MDC STANDOFF

H8

H7

HOLEA

HOLEA

1

1

H10

H9

HOLEA

HOLEA

1

1

H17

H18

HOLEA

HOLEA

1

1

H11
HOLEA

1

H19
HOLEA

1

H12
HOLEA

1

H20
HOLEA

1

H31
HOLEA

1

H5
HOLEA

Del H29. 10/17

H1
HOLEA

1

H13

H14

HOLEA

HOLEA

1

H6
HOLEA

1

1

H27
HOLEA

1

H15

H16

HOLEA

HOLEA

1

1

1

H28
HOLEA

1

H30
HOLEA

1

+3VL

R591

23.7K_0402_1%

KBC Power OK

update KBC power good. 9/19

51.1K_0402_1%

1 2

R592

1 2

C216

9/21

C215

0.1U_0402_16V4Z

1 2

2VREF_8734

R552 23.7K_0402_1%

1 2

12

100K_0402_5%

2

G

VLVL

12

13

D

S

1

2

R584

2200P_0402_50V7K

R510
1M_0402_5%

2N7002_SOT23
Q1

R514 1M_0402_5%

3
2

VL

8

P

+

-

G

LM393M_SO8

4

U3A

12

1

O

H21

H22

HOLEA

HOLEA

9/21

R611 10K_0402_5%

1 2

VCC1_PWRGD 32,33,39

+3VL

1

1

FM3

FM2

FM1

1

1

FM4

1

1

Del LAN reset schematic. 9/26

Security Classification

Issued Date

THIS SHEET OF EN GINEE RING D RAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR DISCLO SED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2005/05/26 2006/07/26

Compal Secret Data

Deciphered Date

H23
HOLEA

1

H25

H24
HOLEA

1

Title

Size Document Number Rev

Date: Sheet

H26

HOLEA

HOLEA

1

1

Compal Electronics, Inc.

POK CKT

LA-4021P

0.1

of

35 45Monday, October 29, 2007

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A

Modify at 7/31 after discuss with power team.

+1.05VM to +VCCP Transfer

Q51

SI4362DY-T1-E3_SO8~N

8
7

1 1

1

C596

2

10U_0805_10V4Z

5

1

C542

2

RUNON

0.1U_0402_16V4Z

+VCCP+1.05VM

1
2
36

1

1

C497

4

C543

2

2

10U_0805_10V4Z

0.1U_0402_16V4Z

+3VALW to +3VM_WOL Transfer

PM_SLP_M#22,33,40,41

+3VALW to +3VS Transfer

B+

12

R578
330K_0402_5%

2 2

SLP_S3

2

G

1

2

12

J7
SHORT PADS

13

D

Q52
RHU002N06_SOT323

S

8
7
6

5

C538
10U_0805_10V4Z

RUNON

U35
SI4800DY_SO8

D
D
D
D

12

R579
470_0402_5%

1

C541

0.01U_0402_25V7Z

2

+3VS+3VALW

1

S

2

S

3

S

4

1

G

1

2

2

C539

0.1U_0402_16V4Z

+3VALW to +3VM Transfer

C540

10U_0805_10V4Z

B

PM_SLP_M#

R518
100K_0402_5%

BSS138_SOT23

PM_SLP_M#

LAN_WOL_EN22,33

R574
100K_0402_5%

BSS138_SOT23

C

+3VALW +3VM_WOL

B+

2

G

13

D

Q50
BSS138_SOT23

S

12

13

D

S

+3VALW

12

2

G

LAN_WOL_EN#

13

D

S

R576

100K_0402_5%

R577

100K_0402_5%@

Q47

+3VALW

12

12

R612
100K_0402_5%

2

G

10U_0805_10V4Z

Q76
BSS138_SOT23

C218

1

2

U33

8

D

7

D

6

D

5

D

SI4800DY_SO8

3VM_WOL_EN

12

R613
470_0402_5%

1

C469

0.01U_0402_25V7Z

2

1

S

2

S

3

S

4

1

G

C470

2

0.1U_0402_16V4Z

D

1

C473
10U_0805_10V4Z

2

Discharge circuit-2 for V-M

+1.05VM

12

R580
470_0402_5%

13

D

2

Q53
RHU002N06_SOT323

G

S

LAN_WOL_EN#

Q77
RHU002N06_SOT323

2

G

LAN_EN#LAN_EN#

Q54
RHU002N06_SOT323

+3VM_WOL

12

R614
470_0402_5%

13

D

Add in 9/21

S

E

+3VM

12

R581
470_0402_5%

13

D

2

G

S

Add in 9/21

+3VALW

B+

+3VALW

12

Q49

LAN_EN#

13

D

2

G

S

R573
100K_0402_5%

12

13

D

2

G

S

10U_0805_10V4Z

Q48
BSS138_SOT23

C531

1

2

U32

8

D

7

D

6

D

5

D

SI4800DY_SO8

3VM_EN

12

R575
470_0402_5%

1

C537

0.01U_0402_25V7Z

2

+3VM

1

S

2

S

3

S

4

G

1

C532

2

0.1U_0402_16V4Z

1

C533
10U_0805_10V4Z

2

2

G

+3VL

12

R583
100K_0402_5%

13

D

S

SLP_S3#22,24,26,28,33,41,42,44

SLP_S3

Q56
RHU002N06_SOT323

+5VALW to +5VS Transfer

S
S
S

G

RUNON

+5VS+5VALW

1
2
3
4

1

2

1

C546
10U_0805_10V4Z

2

C545

0.1U_0402_16V4Z

Design Change at 9/14.

SLP

SLP_S5#22

Q55
RHU002N06_SOT323@

2

G

SLP

13

D

S

SLP_S4#22,40

Q57
RHU002N06_SOT323

U36
SI4800DY_SO8

8

D

7

D

6

3 3

1

2

5

C544
10U_0805_10V4Z

D
D

2

G

+3VL

12

R582
100K_0402_5%

13

D

S

Discharge circuit-1

+0.9V

12

R586
470_0402_5%

13

SLP

4 4

D

2

G

Q58

S

RHU002N06_SOT323

A

+3VS

12

R587
470_0402_5%

13

SLP_S3 SLP_S3

D

2

G

S

PWR_GD 33,35,42

Q59
RHU002N06_SOT323

+1.5VS +1.8V

12

R588
470_0402_5%

13

2

G

D

Q60

S

RHU002N06_SOT323

SLP_S3

Security Classification

THIS SHEET OF EN GINEE RING D RAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

B

MAY BE USED B Y OR DISCLO SED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

+5VS

12

13

D

2

G

S

Issued Date

R589
470_0402_5%

Q61
RHU002N06_SOT323

C

12

R590
470_0402_5%

13

SLP

2006/02/13 2006/07/26

Compal Secret Data

D

2

G

Q62

S

RHU002N06_SOT323

Deciphered Date

D

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

DC/DC Circuits

LA-4021P

E

of

36 45Monday, October 29, 2007

0.1

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A

B

C

D

PCN1

4

V-

5

1 1

2 2

V-

6

GND_1

7

GND_2

8

GND_3

9

GND_4

FOX_JPD113D-LBA21-7F

3

ID

1

V+

2

V+

ADPIN

2

3

PD8

1

@PJSOT24C_SOT23

ADP_SIGNAL 34,44

12

PC1

100P_0402_50V8J

VA

12

PC2
1000P_0402_50V7K

PL2

1 2

SMB3025500YA_2P

PL1

1 2

SMB3025500YA_2P

PC3

100P_0402_50V8J

12

12

PC4

1000P_0402_50V7K

VIN

12

PR1
@15K_0402_5%

PH1 under CPU botten side :

CPU thermal protection at 90 +-3 degree C
Recovery at 47 +-3 degree C

12

PR3
100_0402_5%

SMB_EC_CK1

VMB

PJP9

1 2

PAD-OPEN 4x4m

12

PC5
1000P_0402_50V7K

SMB_EC_DA1

PCN2
SUYIN_200275MR005G187ZL

1

1

EC_SMD

2

2

EC_SMC

3

3
GND
GND

4

4

5

5

12

PC903
100P_0402_50V8J

2007/10/17 2007/10/17

12

PR189
1K_0402_1%

1 2

PR187

210K_0402_1%

BAT_ID# 33

100_0402_5%

+3VL

PR2

12

12

100P_0402_50V8J

PC904

12

100P_0402_50V8J

PC905

6
7

3 3

2007/10/04

2007/9/29

1

2

3

PD10
BAV99_SOT323-3

1

2

3

PD11
BAV99_SOT323-3

1

2

3

PD12
BAV99_SOT323-3

+3VL

BATT

12

PC6

0.01U_0402_50V4Z

SMB_EC_DA1 33

SMB_EC_CK1 33

PC7

@0.22U_0603_10V7K

CPU

12

Vin

12

PH1
@10K_TH11-3H103FT_0603_1%

PR6

@15K_0603_1%

1 2
1 2

Vin

12

PR8

@2.55K_0603_1%

PR7

@150K_0402_1%

@150K_0402_1%

PR9

12

PR4

@47K_0402_1%

1 2

8

5

P

+

6

-

G

4

12

PC8
@1000P_0402_50V7K

PU14B

7

O

LM393DG_SO8

Vin

PR5
@10K_0402_5%

1 2

2

G

13

D

PQ1
@RHU002N06_SOT323-3

S

MAINPWON 4,39

4 4

A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SE CRET INFOR MATI ON. T HIS SHEET MAY NOT BE TRANSF ERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

B

2005/03/10 2006/03/10

Compal Secret Data

Deciphered Date

C

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

BATTERY CONN

LA-3261P UMA

D

37 45Monday, October 29, 2007

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A

VIN

PQ300
FDS4435BZ_SO8

1
2
3 6

PC300

0.22U_0603_16V7K

1 1

BATCAL#44

2 2

1 2

PR303

1 2

200K_0402_5%

PR327
220K_0402_5%

1 2

2

G

8
7

5

4

13

D

S

PQ308
2N7002KW_SOT323-3

12

PR306
150K_0402_5%

PD302

12

RLS4148_LL34-2

BAT_PWM_OUT33

8
7

5

2007/9/21

PQ301

FDS4435BZ_SO8

4

1 2

200K_0402_5%

12

PR307
150K_0402_5%

13

D

PQ306

S

2N7002KW_SOT323-3

ADP_EN# 44

PR318

1 2

@422K_0402_5%

PC320

1U_0603_10V6K

PR302

2

G

1
2
36

ADP_PRES

12

1M_0402_1%

+3VL

0.01U_0402_16V7K

2007/9/26

12

12

PR315

PR301

1 2

56K_0402_1%

PC304

PR316
453K_0402_1%

12

PC307

1 2

1U_0603_6.3V6M

39K_0402_5%

2007/9/26

IADAPT44

2007/9/27

3 3

P2

12

PR319

75K_0402_1%

12

PR322

10K_0603_0.1%

4 4

3
2

2VREF_8734

PR314

1 2

255K_0402_1%

2007/9/26

VL

12

PC314

0.1U_0402_10V7K

8

P

+

1

O

-

G

PU302A
LM393DG_SO8

4

Charge Detector
High 17.588
Low 16.706

AC_AND_CHG

BQ24740VREF

2

G

1 2

11.3K_0402_1%

12

PR321
10K_0402_5%

CHGEN#

13

D

PQ305
2N7002KW_SOT323-3

S

PR329

ACDETACDET

12

PR330
100K_0402_1%

2007/9/26

A

BQ24740VREF

+3VL

PR309

100P_0402_50V8J

P2

12

PR313

57.6K_0402_1%

PR328

1 2

4.32K_0402_1%

12

PR317
10K_0603_0.1%

B

B+

PL300

HCB2012KF-121T50_0805

12

PC319
@0.1U_0603_25V7K

2

ACN

CELLS

20

PR310

12

1 2

ACNACP

CHGEN#

1

TP

CHGEN

PVCC

BTST

HIDRV

PH

REGN

LODRV

PGND

DPMDET

21

2007/9/21

29

28

BST_CHG

27

DH_CHG

26

LX_CHG

25

REGNVADJ

24

DL_CHG

23

22

SRSET 44

2007/9/20

CHGCTRL 33

PC305
1U_0805_25V5K

2007/9/27

ACDET

6

7

LPREF

IADSLP

AGND

VREF

VDAC

VADJ

EXTPWR

ISYNSET

ACSET

PU301
BQ24740RHDR_QFN28_5X5

IADAPT

SRSET

15

16

BATT

12

12

PR311
147K_0402_1%

8

9

10

11

12

13

14

12

IADAPT

PC321

PC318

5

ACDET

BAT

17

1 2

PC301

1U_0603_6.3V6M

12

0.1U_0603_25V7K

3

4

ACP

LPMD

SRP

SRN

19

18

210K_0402_1%

12

PC312
1U_0603_10V6K

C

12

PC302

4.7U_0805_25V6M

2007/10/12

1 2

PD300

RLS4148_LL34-2

PC311

12

1U_0603_10V6K

12

PC303

4.7U_0805_25V6M

PR334
10_0805_5%

1 2

PC306

0.1U_0402_10V7K

1 2

12

PR333
100K_0402_5%

1 2

0.1U_0603_25V7K

2007/9/26

AC Detector

PR312

1 2

681K_0402_1%

8

PU302B

5

P

+

7

O

6

-

G

LM393DG_SO8

4

2VREF_8734

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SE CRET INFOR MATI ON. T HIS SHEET MAY NOT BE TRANSF ERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

B

High 13.774

+3VL

Low 13.357

12

PR320

10K_0402_1%

ADP_PRES 24,33,39

2007/05/29 2008/05/29

Compal Secret Data

PC315

CHGCTRL

1 2

1000P_0402_50V7K

Deciphered Date

C

12

PC316

2007/10/08

PC322

0.047U_0402_16V7K

PR325

1 2

1K_0402_5%

4.7U_0805_25V6M

CHG_B+

5

4

5

4

CELLS 33

12

B+P2

CHG_B+

D8D7D6D

PQ303

S1S2S3G

AO4466_SO8

10U_LF919AS-100M-P3_4.5A_20%

D8D7D6D

S1S2S3G

PQ304
AO4466_SO8

ACPACN

12

PC323
@0.1U_0603_25V7K

+3VL

12

PC313

2

G

12

12

PR326

PD301

470K_0402_5%

1SS355_SOD323-2

D

12

8
7

5

P2

PC308

2007/9/28

12

PC309

4.7U_0805_25V6M

0.01_1206_1%

1 2

1 2

4.7U_0805_25V6M

PC310

0.1U_0402_10V7K

PR308

PQ302
FDS4435BZ_SO8

1
2
3 6

4

PR304
0_0402_5%

1 2

PL301

1 2

PR332
0_0402_5%

1 2
1 2

PR331
0_0402_5%

2007/9/27

+3VL

PR323

1 2

470K_0402_5%

13

D

PQ307
2N7002KW_SOT323-3

S

Title

Size Document Number Rev

Date: Sheet

1

5

P

NC

4

A2Y

G

PU300

3

74LVC1G14GW_SOT353-5

PR324

CHG AC_AND_CHG

1 2

10K_0402_5%

Compal Electronics, Inc.

Charger

LA-3941P

D

38 45Monday, October 29, 2007

BATT

12

PC317

of

12

PC324

4.7U_0805_25V6M

0.1

4.7U_0805_25V6M

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http://www.dnfix.cn/bbs

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A

B

C

D

E

+3.3V/+5V

B+

1 1

PL5
HCB2012KF-121T50_0805

1 2

2 2

B++

12

12

PC29

2200P_0402_50V7K

4.7UH_PCMC063T-4R7MN_5.5A_20%

12

PC30

4.7U_0805_25V6M

4.7U_0805_25V6M

5

PC31

12

PL6

D8D7D6D

S1S2S3G

D8D7D6D

S1S2S3G

4

5

4

+5VALWP

B++

1

+

PC40

2

220U_6.3VM_R15

3 3

1 2

1 2

PR46

@10.2K_0402_1%

PR50

0_0402_5%

PR47

47K_0402_5%

12

12

PC41

0.1U_0603_50V4Z

4 4

PQ9
AO4468_SO8

LX5

PQ11
AO4468_SO8

DL5

PC27

0.1U_0603_50V4Z

1 2

2007/10/17

12

PR902
@0_0402_5%

ON3

DH5

VL

12

PC45

0.047U_0603_16V7K

RHU002N06_SOT323-3

BST5B

PR39
0_0402_5%

1 2

BST5A

1 2

0_0402_5%
PR49

PR51

1 2

@0_0402_5%

MAINPWON 4,37

12

PR56
499K_0402_1%

D

PQ13

S

1 2

PR48
0_0402_5%

2VREF_8734

13

2

G

D

S

2

3

1

VL

12

PC36

4.7U_0805_10V4Z

14

BST5

16

DH5

15

LX5

19

DL5

21

OUT5

9

FB5

1

N.C.

6

SHDN#

4

ON5

ON32VREF_8734

3

ON3

12

SKIP#

8

REF

12

PC43

0.22U_0603_10V7K

VL

12

PR57
330K_0402_5%

2007/10/17

13

D

2

G

PQ14

S

RHU002N06_SOT323-3

13

2

G

PQ15
@RHU002N06_SOT323-3

PD4
CHP202UPT_SOT323-3

B++

18

LD05

MAX8734EEI_QSOP28

1 2

12

0.1U_0603_50V4Z

PC37

20

13

17

V+

TON

PU5

PGOOD

GND

LDO3

23

10

25

+3VLP

12

PC44

4.7U_0805_10V4Z

2007/10/17

PR84
330K_0402_5%

1 2

VL

PR40

47_0402_5%

12

VCC

ILIM3

ILIM5
BST3

DH3

DL3
LX3

OUT3

FB3

PRO#

1 2

PD13
1SS355_SOD323-2

12

2VREF_8734

PC38

1U_0805_16V7K

5

11
28

26
24
27
22

7
2

PR53
0_0402_5%

+3VLP

12

BST3B

PC35

0.1U_0402_16V7K

12

PR42

1 2

200K_0402_1%

PR44

1 2

1 2

499K_0402_1%

RPGOOD 22

PJP1

2 1

PAD-OPEN 2x2m

KBC_PWR_ON 33

VCC1_PWRGD 32,33,35

ADP_PRES 24,33,38

PR43

100K_0402_1%

PR45

499K_0402_1%

0.1U_0603_50V4Z

B++

PR41
0_0402_5%

1 2

BST3A

+3VL

PC28

1 2

DH3

12

12

PC32

4.7U_0805_25V6M

2200P_0402_50V7K

AO4468_SO8

PC33

AO4468_SO8

PQ10

PQ12

5

D8D7D6D

S1S2S3G

4

5

4

DL3

LX3

D8D7D6D

S1S2S3G

12

PL7

4.7UH_SIQB745-4R7_4A_30%

+3VALWP

1

+

PC42

2

220U_6.3VM_R15

1 2

1 2

PR52

@3.57K_0402_1%

PR55

0_0402_5%

A

B

Security Classification

Issued Date

THIS SHEET OF EN GINEE RING D RAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR DISCLO SED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2005/03/01 2006/03/01

Compal Secret Data

Deciphered Date

D

Title

Size Document Number Rev

B

Date: Sheet

3.3V / 5V
LA-3261P UMA

of

39 45Monday, October 29, 2007

E

0.1

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http://www.dnfix.cn/bbs

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A

1 2

18.2K_0402_1%

1 1

13

PU6

ILIM

12

EN

11

PGOOD

10

VOUT

9

FB

8

12

PR65

1K_0402_1%

PC58

+5VALW

12

DDR2_PG35

1 2

@10K_0402_5%

+1.8VP

1 2

14.3K_0603_0.1%

1 2

PC56

10P_0402_50V8J

10K_0603_0.1%

+1.8VP

12

10U_0805_10V4Z

PR63

PR60

PC57

PR64

12

12

@10U_0805_10V4Z

SLP_S4#22,36

1 2

0_0402_5%

+1.8VP

2 2

12

PR59

PC50
@1000P_0402_5%

PR901

0_0402_5%

PC901

0.01U_0402_16V7K

12

15

NC14NC

NC7NC

6

16

DH

LX

BST

VCC

DL

GND5RTN

TP

SC412AMLTRT_MLPQ16_3X3

17

B

PR58

DH_1.8V
LX_1.8V

1

1 2

PR61

1 2

0_0402_5%

6
5

NC

7

NC

8

NC

9

TP

BST_1.8V BST_1.8V_LX

2

+5VALW

3

PC902
1U_0603_10V6K

DL_1.8V

4

PU7

VIN1VCNTL

2

GND

3

VREF

4

VOUT

G2992F1U_SO8

PD901

1 2

RLS4148_LL34-2

0.1U_0402_16V7K

1 2

+5VALW

PC51

12

PC59
1U_0603_16V6K

+5VALW

5

4

5

4

1.8V_B+

12

D8D7D6D

S1S2S3G

PQ16
AO4468_SO8

D8D7D6D

PQ17

S1S2S3G

FDS6690AS_SO8

C

12

PC47

4.7U_0805_25V6M

2.2UH_PCMC063T-2R2MN_8A_20%

12

PR62

@4.7_1206_5%

PC55
@680P_0603_50V7K

1 2

PC48

4.7U_0805_25V6M

PL9

1 2

12

PL8

HCB1608KF-121T30_0603

1 2

PC46

2200P_0402_50V7K

1

+

PC52

2

220U_D2_4VY_R25M

B+

12

PC49
680P_0402_50V7K

12

PC53

0.1U_0402_16V7K

D

+1.8VP

12

PC54

0.1U_0402_16V7K

3 3

PM_SLP_M#22,33,36,41

RHU002N06_SOT323-3

1 2

PR67

0_0402_5%

PQ18

2

G

12

PC62
@0.1U_0402_16V7K

12

PR66

13

D

1K_0402_1%

S

12

12

0.1U_0402_16V7K

PC60

+0.9VP

PC61
10U_0805_6.3V6M

2007/9/21

PJP2

+5VALWP

+1.8VP

4 4

+1.05VMP

1 2

PAD-OPEN 4x4m

PJP4

1 2

PAD-OPEN 4x4m

PJP8

1 2

PAD-OPEN 4x4m

(4.5A,180mils ,Via NO.= 9) (3A,120mils ,Via NO.= 6)

+5VALW

(6A,240mils ,Via NO.= 12)

+1.8V

+3VALWP

+0.9VP

2007/9/21

(8A,320mils ,Via NO.= 16)

+1.05VM

A

PJP3

1 2

PAD-OPEN 4x4m

PJP5

1 2

PAD-OPEN 3x3m

PJP7

1 2

PAD-OPEN 4x4m

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SE CRET INFOR MATI ON. T HIS SHEET MAY NOT BE TRANSF ERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

B

+3VALW

+0.9V

+1.5VS+1.5VSP

Issued Date

(2A,80mils ,Via NO.= 4) (5A,200mils ,Via NO.= 10)

+VCCGFX

(4A,160mils ,Via NO.=8)

2007/05/29 2008/05/29

Compal Secret Data

Deciphered Date

C

PJP11

1 2

PAD-OPEN 4x4m

+VCCP

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

1.8VP/0.9VSP/2.5VSP

LA-3941P

D

40 45Monday, October 29, 2007

of

0.1

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技术支持：252670528

5

4

3

2

1

25

7
8

9
10
11
12

PC76

B+++

PR69

75K_0402_1%

1 2

PR72

0_0402_5%

6

PU8

VO2

P PAD

PGOOD2
EN2
VBST2
DR VH2
LL2
DR VL2

PGND2

13

PR79

16.5K_0402_1%

1 2

12

PR82

3.3_0402_5%

31.6K_0402_1%

2007/10/03

24
23
22

UG_1.05V

21
20

LL1

19

+5VALWP

PR71

1 2

PR75
0_0402_5%

1 2

12

PC79
@0.022U_0402_16V7K

BST_1.05V

LX_1.05V

LG_1.05V

PC68
@0.1U_0603_16V7K

1 2

M_PROK35

PR76

0_0402_5%

UG1_1.05V

1 2

PR78

0_0402_5%

1 2

0.1U_0402_16V7K

1 2

0_0402_5%

12

PR83

PC78
@1000P_0402_50V7K

PC70

1 2

578

PQ19
AO4468_SO8

3 6

241

PL11

2.2UH_PCMC063T-2R2MN_8A_20%

1 2

578

PQ21

FDS6690AS_NL_SO8

3 6

241

PM_SLP_M# 22,33,36,40

PC71

4.7U_0805_6.3V6K

+1.05VMP

12

12

PC65

1

+

PC72

2

220U_D2_4VY_R25M

@2200P_0402_50V7K

12

PC66

4.7U_0805_25V6M

12

PC67

4.7U_0805_25V6M

PR70

75K_0402_1%

1 2

1 2

1

4

2

5

3

VO1

GND

VFB1

VFB2

TONSEL

PGOOD1

EN1

VBST1

DR VH1

DR VL1

TRIP117V5FILT

V5IN16TRIP2

PGND1

TPS51124RGER_QFN24_4x4

15

14

12

12

12

4.7U_0603_6.3V6M

18

PR80

18.2K_0402_1%

PC77

PL10

HCB2012KF-121T50_0805

1 2

B+

12

12

D D

PC63

@2200P_0402_50V7K

PC64

4.7U_0805_25V6M

PR68

73.2K_0402_1%

1 2

2007/10/03

PC80

PR74

0_0402_5%

LG_1.5V

@0.022U_0402_16V7K

12

BST_1.5V

UG_1.5V

LX_1.5V

1U_0603_10V6K

+1.5VS_PG35

PQ20

1

D2

2

D2

3

G1

4

S1/A

+1.5VSP

C C

1

+

PC74

2

220U_B2_2.5VM

1 2

PL12

3.3UH_PCMC063T-3R3MN_6A_20%

PC73

4.7U_0805_6.3V6K

12

SP8K10S FD5 2N SOP8

SLP_S3#22,24,26,28,33,36,42,44

D1/S2/K
D1/S2/K
D1/S2/K

G2

UG1_1.5V

8
7
6
5

PR81
0_0402_5%

@1000P_0402_50V7K

1 2

PR73

0_0402_5%

1 2

PR77

PC69

0_0402_5%

12

1 2

0.1U_0402_16V7K

12

12

PC75

B B

A A

5

4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETAR Y PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM TH E CUSTODY OF THE COM PETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFOR MATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITH OUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC .

3

2006/11/23 2007/11/23

Compal Secret Data

Deciphered Date

2

Title

Size Document Number R e v

Date: Sheet

Compal Electronics, Inc.

1.2V_VP/1.5VSP/1.05VP

LA-3732P

1

of

41 45Monday, October 29, 2007

0.2

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http://www.dnfix.cn/bbs

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技术支持：252670528

5

+VCCP

D D

C C

B B

A A

PR209

68_0402_5%

1 2

H_PROCHOT#

VGATE22

0_0402_5%

PM_PWROK8,22,33,43

H_PROCHOT#4

VCCSENSE5

VSSSENSE5

PM_DPRSLPVR8,22

CLK_ENABLE#22

12

PR229

PR215

1 2

@4.22K_0402_1%

PR217

6.81K_0402_1%

PC213

150P_0402_50V8J

H_DPRSTP#5,8,21

+3VS

PR211

1 2

147K_0402_1%

PH202

1 2

@100K_0603_1%_TH11-4H104FT

1 2

0.015U_0603_25V7K
PR216

1 2

6.34K_0402_1%

PC212

1000P_0402_50V7K

1 2

1 2

PR218

1 2

12

464K_0402_1%

1 2

PC214 47P_0402_50V8J

1 2

PR223

0_0402_5%

1 2

PR225

0_0402_5%

PC220

330P_0402_50V7K

12

PR207
@1.91K_0402_1%

12

PC208
@0.1U_0402_16V7K

PR210

1 2

@40.2K_0402_1%

2007/10/11

H_PROCHOT#

PC211

PR221

1 2

5.49K_0402_1%
PR222 2.21K_0402_1%

1 2

PC218 1000P_0603_50V7K

12

PC219
1000P_0603_50V7K

12

PR206 0_0402_5%

1 2

PR205

0_0402_5%

1 2

1 2

390P_0402_50V7K

1 2

PC223 330P_0402_50V7K

1 2

PR227

1K_0402_1%

PC224

0.22U_0603_10V7K

5

PR203

0_0402_5%

1 2

1

FDE

2

PMON

3

RBIAS

4

VR_TT#

5

NTC

6

SOFT

7

OCSET

8

VW

9

COMP

10

FB

PC216

1 2

1 2

4

PR201
0_0402_5%

1 2

12

PC205

1U_0603_6.3V6M

41

40

39

PGOOD

GND PAD

PU201
ISL6261ACRZ-T_QFN40_6X6

VDIFF

12

11

1 2

PR228

5.36K_0402_1%

4

3V3

VSEN

3

1 2

PR202
@0_0402_5%

CPU_VID6

PWR_GD

12

PR208

0_0402_5%

37

38

36

34

35

VR_ON

CLK_EN

DPRSTP#

DPRSLPVR

VSUM

DFB

VO

DROOP

RTN

17

15

16

14

13

18

12

PC221

SLP_S3# 22,24,26,28,33,36,41,44

5

5

5

CPU_VID5

CPU_VID3

CPU_VID4

33,35,36

VID331VID432VID533VID6

30

VID2

29

VID1

28

VID0

27

VCCP

26

LGATE

25

VSSP

24

PHASE

23

UGATE

22

BOOT

21

NC

VSS

VDD

VIN

19

20

1 2

12

PC215
1U_0603_6.3V6M

PR220
10_0603_5%

1 2

PC217

0.22U_0603_16V7K

12

PC222

1 2

0.1U_0402_16V7K

0.068U_0402_10V6K

+5VS

PR204
1_0603_5%

1 2

12

PC207

1U_0603_6.3V6M

3 5

241

PQ201
RQW130N03-FD5_PSOP8

3 5

241

PQ202
SI7336ADP-T1-E3_SO8

2005/06/23 2006/10/22

Compal Secret Data

Deciphered Date

CPU_VID2

CPU_VID1

LGATE_CPU1

PHASE_CPU1
UGATE_CPU1
BOOT_CPU1

+CPU_B+

VSUM

12

4.53K_0402_1%

CPU_VID0

12

1 2

+VCC_CORE

5

5

5

12

PC206

0.01U_0402_25V7K

PC209

0.22U_0603_10V7K

1 2

0_0603_5%

+5VS

PR224

3.57K_0402_1%

PH201
10KB_0603_5%_ERTJ1VR103J

1 2

PR212

5

PR219
10_0603_5%

PR226

Security Classification

Issued Date

THIS SHEET OF EN GINEE RING D RAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR DISCLO SED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

12

PC202

4.7U_0805_25V6M

3 5

241

PQ203
SI7336ADP-T1-E3_SO8

2

+CPU_B+

12

4.7U_0805_25V6M

HCB2012KF-121T50_0805

12

PC203

PC201

4.7U_0805_25V6M

12

PD201
B340A_SMA2

1

PL201

1 2

12

PR213

4.7_1206_5%

12

PC210
680P_0603_50V8J

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

+CPU_CORE

Monday, October 29, 2007

B+

PL202

0.45UH_ETQP4LR45XFC_25A_-25+20%~D

1 2

12

PR214

7.68K_0805_1%

VSUM

IAX00

1

+VCC_CORE

of

42 45

0.1

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5

+3VS

12

PR116

30K_0402_1%

D D

2007/9/27

PM_PWROK8,22,33,42

C C

+3VS

10K_0402_5%

PR130

+5VS

B B

1 2

PR133

1 2

1_0402_5%

PC120

2.2U_0603_6.3V6K

12

VGAVR_ON

DFGT_VID_48
DFGT_VID_38
DFGT_VID_28
DFGT_VID_18
DFGT_VID_08

@0_0402_5%

PR129

1 2

GFXVR_EN8

PC126

68P_0402_50V8J

+3VS

12

PR120

@1.91K_0402_1%

PR121

@0_0402_5%

1 2

PR128 0_0402_5%

1 2

PR122 0_0402_5%

1 2

PR123 0_0402_5%

1 2

PR124 0_0402_5%

1 2

PR125 0_0402_5%

1 2

+3VS

PR126 10K_0402_5%

1 2

PR132 100K_0402_1%

12

374_0402_1%

12

PC121

0.01U_0402_25V7K

12

VCC_PRM

PC122

1 2

1000P_0402_50V7K

1 2

PR141 6.98K_0402_1%

12

180P_0402_50V8J

PC127

12

PR146

+5VS

PR131

1 2

0_0402_5%

PR136
150K_0402_1%

PR139

1 2

12.4K_0603_1%

A A

5

12

PR119
10_0402_5%

12

PC117
1U_0603_10V6K

VGAVR_ON

12

ISL6263_QFN32

PR144

2.21K_0402_1%

PR147

12

4.99K_0402_1%

4

16
31

27
26
25
24
23

30
32
29

22

1

2
3

4
5
6

12

PC130

560P_0402_50V7K

4

3

GFX_B+

12

PR118
10_0402_5%

12

PC116

0.01U_0402_25V7K

15

VCC
PGOOD

D4
D3
D2
D1
D0

SPIR
FDE
VR_ON

PVCC
RBIAS

SOFT
OCSET

VW
COMP
FB

12

PU11

14

VIN

VSS

VDIFF

7

BOOT

UGATE

PHASE

LGATE

PGND

VSUM

I2UA

DFB

DROOP

VSEN

RTN

EP

33

17
18

19

21
20
13
12

VO

28

11
10
8
9

PC131

1000P_0402_50V7K

BST_GFX

PR137

1 2

20K_0402_1%

12

12

PR127
0_0402_5%

1 2

PR142

1 2

1.91K_0402_1%
PC128

1 2

330P_0402_50V7K

12

PC129
1000P_0402_50V7K

PC132
1000P_0402_50V7K

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2005/03/10 2006/03/10

AO4468_SO8

DH_GFX

12

PC118

0.1U_0402_16V7K

FDS6690AS_NL_SO8

VSUM1
VCC_PRM

PR143

1 2

1K_0402_1%

3

DL_GFX

PR145

1 2

0_0402_5%

PR148

1 2

0_0402_5%

Compal Secret Data

PQ26

LX_GFX

PQ27

12

Deciphered Date

5

4

578

3 6

241

PC125

0.1U_0402_16V7K

Parellel from VCCGFX and GND underneath GMCH at Interface Power pin

12

PC112

2200P_0402_50V7K

D8D7D6D

S1S2S3G

2

GFX_B+

12

12

PC114

PC113

4.7U_0805_25V6M

4.7U_0805_25V6M

1.5UH_IHLP-2525CZ-01_9A_+-20%_15mohm

1 2

PL16

12

PR134

1 2

+VCCGFX

7.68K_0805_1%

PR138

3.57K_0402_1%

+VCCGFXP

PH4

1 2

10KB_0603_5%_ERTJ1VR103J

PR140

1 2

4.53K_0402_1%
PC123

1 2

0.033U_0402_16V7K

1 2

PC124

0.022U_0402_16V7K

2

1

PL15

HCB1608KF-121T30_0603

12

PR135
0_0402_5%

PJP10

1 2

PAD-OPEN 4x4m

Title

Size Document Number Rev

B

Date: Sheet

12

+VCCGFXP

1

+

2

+VCCGFX

B+

PC119

330U_D2E_2.5VM_R9

(5A,200mils ,Via NO.= 10)

Compal Electronics, Inc.

VCCGFX

LA-3261P UMA

43 45Monday, October 29, 2007

1

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5

4

3

2

1

2007/9/26

12

8

P

G

PU14A
LM393DG_SO8

4

1

2

3

1_0805_1%

12

1

O

PU9

LMV321M5X-NOPB_SOT23-5

+IN

V-

-IN

1 2

PC140

0.1U_0603_50V7K

VIN

12

PR188

PD14
RLS4148_LL34-2

1 2

12

PC139

1U_0805_25V6K

1SS355_SOD323-2

V+

OUTPUT

PR163
47K_0402_5%

PD6

1 2

ADP_EN# 38

+5VS

5

4

+3VL

12

2007/10/08

12

12

PR192

2.2K_0402_5%

1 2

PD9
1SS355_SOD323-2

PR154
10K_0402_5%

ADP_ID 33

SLP_S3#22,24,26,28,33,36,41,42

PR164
220K_0402_5%

2

G

PR175
220K_0402_5%

1 2

12

+3VL

2

G

12

PR165
47K_0402_5%

13

D

PQ31
RHU002N06_SOT323-3

S

PR155

3.9K_0402_5%

13

D

S

BATCAL#38

2007/9/20

PR149

1 2

100K_0402_5%

2007/9/26

3
2

1

2

PC133

3900P_0402_50V7K

PQ33
RHU002N06_SOT323-3

+5VS

ADP_EN 33

PR177

C

PQ28

2

B

MMBT3904W_SOT323-3

E

3 1

+5VS

8

PU12A

P

+

O

-

G

LM393DG_SO8

4

12

PR168
133K_0402_1%

12

80.6K_0402_1%

SRSET 38

1

1U_0603_10V6K

12

PC136

0.01U_0402_16V7K

PC134

PR169

1 2

100K_0402_5%

8

5

P

+

6

-

G

4

1 2

PR179
200K_0603_1%

+3VS

12

PR150

10K_0402_5%

12

PR156
47K_0402_5%

12

PU12B

7

O

LM393DG_SO8

PR157

12

470K_0402_5%

+5VS

12

2

G

0.1U_0603_16V7K

12

PC135

PR170

10K_0402_5%

12

PR151
10K_0402_5%

PR152

1 2

0_0402_5%

13

D

PQ30
RHU002N06_SOT323-3

S

+3VS

12

PR167

71.5K_0402_1%

12

PR172
21K_0603_1%

12

PR178

3.48K_0402_1%

OCP# 22

PR161

10K_0402_5%

1 2

PR176

21K_0603_1%

1 2

PR158

1M_0402_5%

1 2

PR173

1M_0402_5%

1 2

3
2

5
6

+5VS

+

-

+5VS

+

-

8

P

G

4

8

P

G

4

PU13A

1

O

LM393DG_SO8

PU13B

7

O

LM393DG_SO8

+3VS

12

+3VS

12

PR159
10K_0402_5%

ADP_PS0 33

PR174
10K_0402_5%

ADP_PS1 33

PR193
10K_0402_5%

VIN

12

12

VIN

12

12

PR180

0_0402_5%

1 2

1 2

PR190
165K_0402_1%

1 2

78.7K_0603_1%

S

G

2

PR181

191K_0402_1%

PR191

PQ29

D

NDS0610_NL_SOT23-3

13

2007/9/26

1 2

PR162

1M_0402_5%

3

+

2

-

12

D D

ADP_SIGNAL 34,37

PR153

1 2

100_0402_1%

C C

B B

IADAPT38

PR160

22.6K_0402_1%

PR186

10K_0402_1%

PR166

22.6K_0402_1%

PR171

10K_0402_1%

BQ24740VREF

2007/9/26

A A

5

4

3

Title

<Title>

Size Document Number R ev

LA-3941P 0.1

Custom

2

Date: Sheet

1

of

44 45Monday, October 29, 2007

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5

4

3

2

Version change list (P.I.R. List) Power section Page 1 of 1

1

D D

Item Reason for change PG# Modify List Date Phase

1
2
3
4
5
6
7

C C

8
9
10
11
12

B B

A A

5

4

Security Classification

Issued Date

THIS SHEET OF EN GINEE RING D RAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR DISCLO SED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/02/28 2007/02/28

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

2

Date: Sheet

Compal Electronics, Inc.

Changed-List History-1

LA-3732P

1

45 45Monday, October 29, 2007

0.2

of