COMPAL LA-4021 Schematics

A

B

C

D

E

1 1

Compal confidential

Schematics Document

Mobile Penryn uFCPGA with Intel

2 2

Cantiga_GM+ICH9-M SFF core logic

SKYY

2008-07-29

3 3

4 4

A

B

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2006/02/13 2006/03/10

2006/02/13 2006/03/10

2006/02/13 2006/03/10

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

D

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, M/B LA-4021P

SCHEMATIC, M/B LA-4021P

SCHEMATIC, M/B LA-4021P

401554

401554

401554

E

of

of

of

136Wednesday, June 03, 2009

136Wednesday, June 03, 2009

136Wednesday, June 03, 2009

B

B

B

A

B

C

D

E

Compal confidential

File Name : LA-4021P

Docking CONN.(Opus 1.0)

1 1

*RJ-45(LED*2)
*CRT
*LINE IN
*LINE OUT
*USB x4
*DC JACK

*Power on signal
*Docked indicator
signal
*AC present indicator
signal

2 2

Express Card 54

PCIE X1 + USB X1

page 25

WWAN Card

WWAN + PCIE X1
+ USB X1

page 25

Thermal Sensor
EMC2103

page 4

Fan Control

page 4

LCD conn

page 18

CRT

page 17

CRT to docking

page 34

S-Video to Docking

page 34

PCI-E BUS

10/100/1000 LAN

Intel Boaz GbE

PHY

page 24

CardBus Controller

Rico R5C833

page 27

PCI BUS

24HST1041A-3

3 3

RJ45 CONN

page 25

LED

page 19

1394 port

SD/MMC Slot

LPC BUS

RTC CKT.

page 21

TPM1.2

SLB9635TT

page 32

Power OK CKT.

page 35

Touch Pad CONN.

SKYY

Mobile Penym

LV/ULV Dual Core

uFCPGA-956 CPU - SFF

page 4,5,6,7

H_A#(3..35)
H_D#(0..63)

Intel Cantiga GMS

FCBGA 1363 - SFF

page 8,9,10,11,12,13

Intel ICH9-M

WBMMAP-569 - SFF

page 20,21,22,23

SMSC KBC 1091

page 33

FSB

667/800/1066MHz 1.05V

DMI X4

Int.KBD

page 30page 30

SPI

SPI ROM

AT26DF321

page 32

DDR2 800MHz 1.8V

Dual Channel

USB2.0
Azalia

SATA0

SATA1

CK505

Clock Generator
ICS9LPRS397

page 16

DDR2-SO-DIMM X 2

BANK 0, 1, 2, 3

USB x1(Docking)
FingerPrinter AES2810

USBx1

USB conn x 3(For I/O)
BT Conn USB x 1

USB x1(Camara)

page 18

MDC V1.5

page 30

Audio CKT

AD1984HD

2.5" SATA HDD Connector

OR

SATA ODD Connector

1.8" SATA HDD Connector

page 14,15

page 34

page 31

page 31

page 28

page 21

page 21

Accelerometer

LIS302DLTR

page 26

daughter board

TPA6043

AMP & Audio Jack

page 29

4 4

Power On/Off CKT.

page 30

DC/DC Interface CKT.

page 36

A

TrackPoint CONN.

page 30

B

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2006/02/13 2006/03/10

2006/02/13 2006/03/10

2006/02/13 2006/03/10

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

D

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, M/B LA-4021P

SCHEMATIC, M/B LA-4021P

SCHEMATIC, M/B LA-4021P

401554

401554

401554

E

of

of

of

236Wednesday, June 03, 2009

236Wednesday, June 03, 2009

236Wednesday, June 03, 2009

B

B

B

A

Voltage Rails

State

S0

S1

S3

S5 S4/AC

S5 S4/ Battery only

S5 S4/AC & Battery
don't exist

1 1

( O MEANS ON X MEANS OFF )

+B

power
plane

O
O
O
O
O

X

+5VALW
+3VALW
+3VM
+1.05VM

O
O
O
O

X

+1.8V

O

XX
X

+5VS
+3VS
+1.5VS
+0.9V
+VCCP
+CPU_CORE
+0.9V

OO
OO

X

X

XX X

SMBUS Control Table

SOURCE

SMB_EC_CK1
SMB_EC_DA1

SMB_EC_CK2
SMB_EC_DA2

SMB_CK_CLK1
SMB_CK_DAT1 ICH9

LCD_CLK
LCD_DAT

KB926

KB926

Cantiga

Symbol Note :

: means Digital Ground

: means Analog Ground

@ : means just reserve , no build
CONN@ : means ME part.
45@ : means install after SMT.

INVERTER BATT EEPROM

X
X

X
XX

SERIAL

VV

XX
X

X
XX

THERMAL
SENSOR
(CPU)

SODIMM CLK CHIP

XX

V

X

X

VVV

XX

X
X

MINI CARD

LCD

XX
X

X
X

X

V

I2C / SMBUS ADDRESSING

DEVICE

DDR SO-DIMM 0
CLOCK GENERATOR (EXT.)

HEX ADDRESS

A0
D2

1 0 1 0 0 0 0 0
1 1 0 1 0 0 1 0

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

2005/03/10 2006/03/10

2005/03/10 2006/03/10

2005/03/10 2006/03/10

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, M/B LA-4021P

SCHEMATIC, M/B LA-4021P

SCHEMATIC, M/B LA-4021P

401554

401554

401554

336Wednesday, June 03, 2009

336Wednesday, June 03, 2009

336Wednesday, June 03, 2009

of

of

of

B

B

B

5

4

3

2

1

XDP Connector

JP1

JP1

1

2

1

GND0

3

OBSFN_A0

5

OBSFN_A1

7

GND2

9

OBSDATA_A0

11

OBSDATA_A1

13

GND4

15

OBSDATA_A2

17

OBSDATA_A3

19

GND6

21

OBSFN_B0

23

OBSFN_B1

25

GND8

27

OBSDATA_B0

29

OBSDATA_B1

31

GND10

33

OBSDATA_B2

35

OBSDATA_B3

37

GND12

39

PWRGOOD/HOOK0

41

HOOK1

43

VCC_OBS_AB

45

HOOK2

47

HOOK3

49

GND14

51

SDA

53

SCL

55

TCK1

57

TCK0

59

GND16

U2

U2

1

DN

2

DP

3

VDD

4

GPIO1

5

GPIO2

6

ALERT#

7

SYS_SHDN#

8

SMDATA

C

C

Q45

Q45

2

B

B

MMBT3904W_SOT323-3

MMBT3904W_SOT323-3

E

E

3 1

Layout Note:
place near the hottest spot area for

NB & top SODIMM.

OBSDATA_C0
OBSDATA_C1

OBSDATA_C2
OBSDATA_C3

OBSDATA_D0
OBSDATA_D1

OBSDATA_D2
OBSDATA_D3

ITPCLK/HOOK4

ITPCLK#/HOOK5

VCC_OBS_CD

RESET#/HOOK6

DBR#/HOOK7

SAMTE_BSH-030-01-L-D-ACONN@

SAMTE_BSH-030-01-L-D-ACONN@

Change R18 to 2.94k_1% to change initial
thermal shutdown temp to 85C. 2/13

DP2/DN3
DN2/DP3

TRIP_SET

SHDN_SEL

GND

PWM

TACH

SMCLK

GND

EMC2103-2-AX_QFN16_4X4

EMC2103-2-AX_QFN16_4X4

17

XDP_BPM#5

D D

H_A#[3..16]<8>

H_ADSTB#0<8>

H_A#[17..35]<8>

C C

H_ADSTB#1<8>

H_FERR#<21>

B B

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16

H_REQ#0<8>
H_REQ#1<8>
H_REQ#2<8>
H_REQ#3<8>
H_REQ#4<8>

H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35

H_A20M#<21>
H_IGNNE#<21>
H_STPCLK#<21>

H_INTR<21>

H_NMI<21>
H_SMI#<21>

T97PAD T97PAD
T98PAD T98PAD

T99PAD T99PAD
T100PAD T100PAD
T101PAD T101PAD
T102PAD T102PAD
T103PAD T103PAD

U1A

U1A

P2

A[3]#

V4

A[4]#

W1

A[5]#

T4

A[6]#

AA1

A[7]#

AB4

A[8]#

T2

A[9]#

AC5

A[10]#

AD2

A[11]#

AD4

A[12]#

AA5

A[13]#

AE5

A[14]#

AB2

A[15]#

AC1

A[16]#

Y4

ADSTB[0]#

R1

REQ[0]#

R5

REQ[1]#

U1

REQ[2]#

P4

REQ[3]#

W5

REQ[4]#

AN1

A[17]#

AK4

A[18]#

AG1

A[19]#

AT4

A[20]#

AK2

A[21]#

AT2

A[22]#

AH2

A[23]#

AF4

A[24]#

AJ5

A[25]#

AH4

A[26]#

AM4

A[27]#

AP4

A[28]#

AR5

A[29]#

AJ1

A[30]#

AL1

A[31]#

AM2

A[32]#

AU5

A[33]#

AP2

A[34]#

AR1

A[35]#

AN5

ADSTB[1]#

C7

A20M#

D4

ICH

ICH

FERR#

F10

IGNNE#

F8

STPCLK#

C9

LINT0

C5

LINT1

E5

SMI#

V2

RSVD01

Y2

RSVD02

AG5

RSVD03

AL5

RSVD04

J9

RSVD05

F4

RSVD06

H8

RSVD07

PENRYN SFF_UFCBGA956

PENRYN SFF_UFCBGA956

ADDR GROUP 0

ADDR GROUP 0

DEFER#

CONTROL

CONTROL

RESET#

ADDR GROUP 1

ADDR GROUP 1

BPM[0]#
BPM[1]#
BPM[2]#
BPM[3]#

XDP/ITP SIGNALS

XDP/ITP SIGNALS

THERMAL

THERMAL

PROCHOT#

THERMDA
THERMDC

THERMTRIP#

H CLK

H CLK

BCLK[0]
BCLK[1]

ADS#
BNR#
BPRI#

DRDY#
DBSY#

BR0#

IERR#

INIT#

LOCK#

RS[0]#
RS[1]#
RS[2]#

TRDY#

HIT#

HITM#

PRDY#
PREQ#

TCK

TDI
TDO
TMS

TRST#

DBR#

RESERVED

RESERVED

M4
J5
L5

N5
F38
J1

M2
B40

D8
N1
G5

K2
H4
K4
L1

H2
F2

AY8
BA7
BA5
AY2
AV10
AV2
AV4
AW7
AU1
AW5
AV8
J7

D38
BB34
BD34

B10

A35
C35

Place close to U1.

H_ADS# <8>
H_BNR# <8>

H_BPRI# <8>
H_DEFER# <8>

H_DRDY# <8>
H_DBSY# <8>

H_BR0# <8>

H_INIT# <21>
H_LOCK# <8>

H_RESET#

H_TRDY# <8>

H_HIT# <8>
H_HITM# <8>

XDP_BPM#0
XDP_BPM#1
XDP_BPM#2
XDP_BPM#3
XDP_BPM#4
XDP_BPM#5_R
XDP_TCK
XDP_TDI
XDP_TDO
XDP_TMS
XDP_TRST#
XDP_DBRESET#

Place Close to U1.

H_THERMDA_R
H_THERMDC_R

H_THERMTRIP#

H_THERMDA, H_THERMDC routing together,
Trace width / Spacing = 10 / 10 mil

CLK_CPU_BCLK <16>
CLK_CPU_BCLK# <16>

+VCCP

R609

R609
51_0402_1%

51_0402_1%

9/20

1 2

1 2

56_0402_5%

56_0402_5%

R10

R10

H_RS#0 <8>
H_RS#1 <8>
H_RS#2 <8>

Add 0 ohm per EMI request.
10/17

R48

R48
0_0402_5%

0_0402_5%

1 2

XDP_DBRESET# <22>

H_PROCHOT# <42>

R20 68_0402_5%

R20 68_0402_5%

1 2

R21 0_0402_5%R21 0_0402_5%

1 2

R22 0_0402_5%R22 0_0402_5%

1 2

+VCCP

H_THERMTRIP# <8,21>

H_RESET# <8>

XDP_BPM#5

9/14

H_THERMDA
H_THERMDC

H_PWRGOOD<5,21> CLK_CPU_XDP <16>

C1 0.1U_0402_16V4ZC1 0.1U_0402_16V4Z

Thermal Sensor EMC2103-2 with CPU PWM FAN

+3VS

R15

R15
68_0402_5%

68_0402_5%

1 2

+3VS_THER

C2

C2

1

0.1U_0402_16V4Z

0.1U_0402_16V4Z

2

THERM_SCI#<22>

+3VS

ICH_SM_DA<22,26>

MAINPWON<37,39>

H_THERMTRIP#

Add R641 per HP request. 3/28

R23 10K_0402_5%@R23 10K_0402_5%@

R324 0_0402_5%@R324 0_0402_5%@
R641 0_0402_5%R641 0_0402_5%

Change R23, R24 connect to +3VS and add PU/PD for U2. (9/3)
NI R23, reserve R324 and connect to MAINPWON. (10/5)

XDP_BPM#4
XDP_BPM#3

XDP_BPM#2
XDP_BPM#1

XDP_BPM#0

R9

R9
1K_0402_5%

1K_0402_5%

H_PWRGOOD_R

12

XDP_HOOK1

12

XDP_TCK

Correct to Swap DN&DP. (11/26)

H_THERMDC
H_THERMDA

1 2

C3 2200P_0402_50V7KC3 2200P_0402_50V7K

R24

R24
10K_0402_5%

10K_0402_5%

1 2

+3VS

1 2

1 2
1 2

REMOTE thermal sensor

REMOTE2+

C314

C314

2200P_0402_50V7K

2200P_0402_50V7K

REMOTE2-

2

GND1

4

OBSFN_C0

6

OBSFN_C1

8

GND3

10
12
14

GND5

16
18
20

GND7

22

OBSFN_D0

24

OBSFN_D1

26

GND9

28
30
32

GND11

34
36
38

GND13

40
42
44
46
48
50

GND15

52

TD0

54

TRST#

56

TDI

58

TMS

60

GND17

REMOTE2+

16

REMOTE2-

15

R18 2.05K_0402_1%R18 2.05K_0402_1%

14

1 2

R643 10K_0402_5%@R643 10K_0402_5%@

1 2

R17 10K_0402_5%R17 10K_0402_5%

13

1 2

12

FAN_PWM

11

TACH

10
9

R13 10K_0402_5%R13 10K_0402_5%

R16 10K_0402_5%R16 10K_0402_5%

XDP_TDI
XDP_TMS
XDP_TDO
XDP_BPM#5
XDP_HOOK1
XDP_TRST#
XDP_TCK

H_RESET#_R
XDP_DBRESET#

XDP_TDO
XDP_TRST#
XDP_TDI
XDP_TMS
XDP_PRE

1 2

1 2

ICH_SM_CLK <22,26>

R2 54.9_0402_1%R2 54.9_0402_1%

1 2

R3 54.9_0402_1%R3 54.9_0402_1%

1 2

R4 54.9_0402_1%R4 54.9_0402_1%

1 2

R5 54.9_0402_1%R5 54.9_0402_1%

1 2

R6 54.9_0402_1%@ R6 54.9_0402_1%@

1 2

R7 51_0402_1%

R7 51_0402_1%

1 2

R8 54.9_0402_1%R8 54.9_0402_1%

1 2

This shall place near CPU

CLK_CPU_XDP# <16>

+VCCP+VCCP

R11 22.6_0402_1%R11 22.6_0402_1%

1 2

R14

R14
0_0402_5%

0_0402_5%

1 2

Change R17 to 10K for HW critical
shutdown to internal diode
temperature. 4/23

Place R191 within 200ps
(~1") to CPU

+5VS

+3VS

+3VS

Chnage JP2 to 4pin. 12/06

1
2
3

+VCCP

H_RESET#

JP2

JP2

4

1

4

5

2

G5

6

3

G6

ACES_85205-04001CONN@

ACES_85205-04001CONN@

A A

5

4

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/02/13 2006/03/10

2006/02/13 2006/03/10

2006/02/13 2006/03/10

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, M/B LA-4021P

SCHEMATIC, M/B LA-4021P

SCHEMATIC, M/B LA-4021P

401554

401554

401554

1

of

of

of

436Wednesday, June 03, 2009

436Wednesday, June 03, 2009

436Wednesday, June 03, 2009

B

B

B

5

4

3

2

1

H_D#[0..15]<8>

D D

H_DSTBN#0<8>
H_DSTBP#0<8>
H_DINV#0<8>
H_D#[16..31]<8>

C C

layout note: Route TEST3 & TEST5 traces on
ground referenced layer to the TPs

H_DSTBN#1<8>
H_DSTBP#1<8>
H_DINV#1<8>

CPU_BSEL0<16>
CPU_BSEL1<16>
CPU_BSEL2<16>

V_CPU_GTLREF

T105T105

T3T3
T4T4

H_D#0
H_D#1

H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_DSTBN#0
H_DSTBP#0
H_DINV#0

H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_DSTBN#1
H_DSTBP#1
H_DINV#1

TEST2

TEST5
TEST6

CPU_BSEL CPU_BSEL2 CPU_BSEL1

B B

166

200

01

0

1

U1B

U1B

F40

D[0]#

G43

D[1]#

E43

D[2]#

J43

D[3]#

H40

D[4]#

H44

D[5]#

G39

D[6]#

E41

D[7]#

L41

D[8]#

K44

D[9]#

N41

D[10]#

T40

D[11]#

M40

D[12]#

G41

D[13]#

M44

D[14]#

L43

D[15]#

K40

DSTBN[0]#

J41

DSTBP[0]#

P40

DINV[0]#

P44

D[16]#

V40

D[17]#

V44

D[18]#

AB44

D[19]#

R41

D[20]#

W41

D[21]#

N43

D[22]#

U41

D[23]#

AA41

D[24]#

AB40

D[25]#

AD40

D[26]#

AC41

D[27]#

AA43

D[28]#

Y40

D[29]#

Y44

D[30]#

T44

D[31]#

U43

DSTBN[1]#

W43

DSTBP[1]#

R43

DINV[1]#

AW43

GTLREF

E37

TEST1

D40

TEST2

C43

TEST3

AE41

TEST4

AY10

TEST5

AC43

TEST6

A37

BSEL[0]

C37

BSEL[1]

B38

BSEL[2]

PENRYN SFF_UFCBGA956

PENRYN SFF_UFCBGA956

CPU_BSEL0

1

0

D[32]#
D[33]#
D[34]#

DATA GROUP 0

DATA GROUP 0

D[35]#
D[36]#
D[37]#
D[38]#
D[39]#
D[40]#
D[41]#
D[42]#
D[43]#
D[44]#

DATA GROUP 2DATA GROUP 3

DATA GROUP 2DATA GROUP 3

D[45]#
D[46]#

D[47]#
DSTBN[2]#
DSTBP[2]#

DINV[2]#

D[48]#

D[49]#

D[50]#

D[51]#

DATA GROUP 1

DATA GROUP 1

D[52]#

D[53]#

D[54]#

D[55]#

D[56]#

D[57]#

D[58]#

D[59]#

D[60]#

D[61]#

D[62]#

D[63]#
DSTBN[3]#
DSTBP[3]#

DINV[3]#
COMP[0]

MISC

MISC

COMP[1]
COMP[2]
COMP[3]

DPRSTP#

DPSLP#

DPWR#

PWRGOOD

SLP#

PSI#

Cause CPU core power change to
1 phase, and not need support
the pin, leave it as TP. 10/02

AR43
AH40
AF40
AJ43
AG41
AF44
AH44
AM44
AN43
AM40
AK40
AG43
AP40
AN41
AL41
AK44
AL43
AJ41

AV38
AT44
AV40
AU41
AW41
AR41
BA37
BB38
AY36
AT40
BC35
BC39
BA41
BB40
BA35
AU43
AY40
AY38
BC37

AE43
AD44
AE1
AF2

G7
B8
C41
E7
D10
BD10

H_PSI#

H_D#33
H_D#34H_D#2
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_DSTBN#2
H_DSTBP#2
H_DINV#2

H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
H_DSTBN#3
H_DSTBP#3
H_DINV#3

COMP0
COMP1
COMP2
COMP3

H_D#32

AP44

H_DPRSTP# <8,21,42>

H_DPSLP# <21>
H_DPWR# <8>
H_PWRGOOD <4,21>

H_CPUSLP# <8>

T124T124

H_D#[32..47] <8>

H_DSTBN#2 <8>
H_DSTBP#2 <8>
H_DINV#2 <8>
H_D#[48..63] <8>

H_DSTBN#3 <8>
H_DSTBP#3 <8>
H_DINV#3 <8>

R34

R34

R33

R33

R32

R32

R31

R31

12

12

12

12

27.4_0402_1%

27.4_0402_1%

54.9_0402_1%

54.9_0402_1%

27.4_0402_1%

27.4_0402_1%

54.9_0402_1%

54.9_0402_1%

Resistor placed within

0.5" of CPU pin.Trace
should be at least 25
mils away from any other
toggling signal.
COMP[0,2] trace width is
18 mils. COMP[1,3] trace
width is 4 mils.

266 0 0 0

+VCC_CORE +VCC_CORE

U1C

U1C

F32

VCC[001]

G33

VCC[002]

H32

VCC[003]

J33

VCC[004]

K32

VCC[005]

L33

VCC[006]

M32

VCC[007]

N33

VCC[008]

P32

VCC[009]

R33

VCC[010]

T32

VCC[011]

U33

VCC[012]

V32

VCC[013]

W33

VCC[014]

Y32

VCC[015]

AA33

VCC[016]

AB32

VCC[017]

AC33

VCC[018]

AD32

VCC[019]

AE33

VCC[020]

AF32

VCC[021]

AG33

VCC[022]

AH32

VCC[023]

AJ33

VCC[024]

AK32

VCC[025]

AL33

VCC[026]

AM32

VCC[027]

AN33

VCC[028]

AP32

VCC[029]

AR33

VCC[030]

AT34

VCC[031]

AT32

VCC[032]

AU33

VCC[033]

AV32

VCC[034]

AY32

VCC[035]

BB32

VCC[036]

BD32

VCC[037]

B28

VCC[038]

B30

VCC[039]

B26

VCC[040]

D28

VCC[041]

D30

VCC[042]

F30

VCC[043]

F28

VCC[044]

H30

VCC[045]

H28

VCC[046]

D26

VCC[047]

F26

VCC[048]

H26

VCC[049]

K30

VCC[050]

K28

VCC[051]

M30

VCC[052]

M28

VCC[053]

K26

VCC[054]

M26

VCC[055]

P30

VCC[056]

P28

VCC[057]

T30

VCC[058]

T28

VCC[059]

V30

VCC[060]

V28

VCC[061]

P26

VCC[062]

T26

VCC[063]

V26

VCC[064]

Y30

VCC[065]

Y28

VCC[066]

AB30

VCC[067]

PENRYN SFF_UFCBGA956

PENRYN SFF_UFCBGA956

VCC[068]
VCC[069]
VCC[070]
VCC[071]
VCC[072]
VCC[073]
VCC[074]
VCC[075]
VCC[076]
VCC[077]
VCC[078]
VCC[079]
VCC[080]
VCC[081]
VCC[082]
VCC[083]
VCC[084]
VCC[085]
VCC[086]
VCC[087]
VCC[088]
VCC[089]
VCC[090]
VCC[091]
VCC[092]
VCC[093]
VCC[094]
VCC[095]
VCC[096]
VCC[097]
VCC[098]
VCC[099]
VCC[100]

VCCP_001
VCCP_002
VCCP_003
VCCP_004
VCCP_005
VCCP_006
VCCP_007
VCCP_008
VCCP_009
VCCP_010
VCCP_011
VCCP_012
VCCP_013
VCCP_014
VCCP_015
VCCP_016

VCCA[01]
VCCA[02]

VID[0]
VID[1]
VID[2]
VID[3]
VID[4]
VID[5]
VID[6]

VCCSENSE

VSSSENSE

AB28
AD30
AD28
Y26
AB26
AD26
AF30
AF28
AH30
AH28
AF26
AH26
AK30
AK28
AM30
AM28
AP30
AP28
AK26
AM26
AP26
AT30
AT28
AV30
AV28
AY30
AY28
AT26
AV26
AY26
BB30
BB28
BD30

R26 0_0402_5%R26 0_0402_5%

J11

1 2

R27 0_0402_5% R27 0_0402_5%

E11

1 2

R28 0_0402_5% R28 0_0402_5%

G11

1 2
J37
K38
L37
N37
P38
R37
U37
V38
W37
AA37
AB38
AC37
AE37

B34
D34

BD8
BC7
BB10
BB8
BC5
BB4
AY4

VCCSENSE

BD12

VSSSENSE

BC13

Length match within 25 mils.
The trace width/space/other is
20/7/25.

+VCCP

1

+

+

C4

C4

330U_D2E_2.5VM_R9

330U_D2E_2.5VM_R9

2

CPU_VID0 <42>
CPU_VID1 <42>
CPU_VID2 <42>
CPU_VID3 <42>
CPU_VID4 <42>
CPU_VID5 <42>
CPU_VID6 <42>

VCCSENSE <42>

VSSSENSE <42>

1

C6

C6

2

0.01U_0402_16V7K

0.01U_0402_16V7K

Near pin B34

Change to 330u_R9,
casue high
limitation. 12/14

+1.5VS

1

C7

C7

2

10U_0805_6.3V6M

10U_0805_6.3V6M

Near pin D34

+VCC_CORE

R36

R36

+VCCP

12

R35

R35
1K_0402_1%

1K_0402_1%

V_CPU_GTLREF

A A

Close to CPU pin AW43
within 500mils.

5

12

R37

R37
2K_0402_1%

2K_0402_1%

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/02/13 2006/03/10

2006/02/13 2006/03/10

2006/02/13 2006/03/10

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

1 2

100_0402_1%

100_0402_1%
R38

R38

1 2

100_0402_1%

100_0402_1%

Close to CPU pin
within 500mils.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

VCCSENSE

VSSSENSE

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

SCHEMATIC, M/B LA-4021P

SCHEMATIC, M/B LA-4021P

SCHEMATIC, M/B LA-4021P

401554

401554

401554

1

B

B

B

of

of

of

536Wednesday, June 03, 2009

536Wednesday, June 03, 2009

536Wednesday, June 03, 2009

5

4

3

2

1

D D

+VCCP

AL37

AN37

AP38

B32

C33

D32

E35

E33

F34

G35

F36

H36

J35

L35

N35

K36

R35

U35

P36

V36

W35

AA35

AC35

AB36

AE35

AG35

AJ35

AF36

AL35

AN35

AK36

AP36

B12

B14

C13

D12

D14

E13

F14

F12

G13

H14

H12

J13

K14

K12

L13

L11

M14

N13

N11

K10

P14

P12

R13

R11

T14

U13

U11

V14

V12

W13

W11

P10

V10

Y14

AA13

AA11

AB14

AB12

AC13

AC11

AD14

AB10

AE13

AE11

AF14

AF12

AG13

AG11

AH14

AJ13

AJ11

AF10

AK14

AK12

AL13

AL11

AN13

AN11

AP12

AR13

AR11

AK10

AP10

AU13

VCCP_111

VCC_191

AK16

AM18

VCCP_112

VCCP_113

VCC_192

VCC_193

AM16

VCCP_114

VCC_194

AP18

AP16

VCCP_115

VCCP_116

VCC_195

VCC_196

AK20

AU11

VCCP_117

VCCP_118L9VCCP_119L7VCCP_120N9VCCP_121N7VCCP_122R9VCCP_123R7VCCP_124U9VCCP_125U7VCCP_126W9VCCP_127W7VCCP_128

VCC_197

VCC_198

VCC_199

VCC_200

AT18

AT16

AP20

AV18

AM20

C C

VCCP_021

VCCP_022

VCCP_023

VCCP_024

VCCP_025

VCCP_026

VCCP_027

VCCP_028

VCCP_029

VCCP_030

VCCP_031

VCCP_032

VCCP_033

VCCP_034

VCCP_035

VCCP_036

VCCP_037

VCCP_038

VCCP_039

VCCP_040

VCCP_041

VCCP_042

VCCP_043

VCCP_044

VCCP_045

VCCP_046

VCCP_047

VCCP_048

VCCP_049

VCCP_050

VCCP_051

VCCP_052

VCCP_053

VCCP_054

VCCP_055

VCCP_056

VCCP_057

VCCP_058

VCCP_059

VCCP_060

VCCP_061

VCCP_062

VCCP_063

VCCP_064

VCCP_065

VCCP_066

VCCP_067

VCCP_068

VCCP_069

VCCP_070

VCCP_071

VCCP_072

VCCP_073

VCCP_074

VCCP_075

VCCP_076

VCCP_077

VCCP_078

VCCP_079

VCCP_080

VCCP_081

VCCP_082

VCCP_083

VCCP_084

VCCP_085

VCCP_086

VCCP_087

VCCP_088

VCCP_089

VCCP_090

VCCP_091

VCCP_092

VCCP_093

VCCP_094

VCCP_095

VCCP_096

VCCP_097

VCCP_098

VCCP_099

VCCP_100

VCCP_101

VCCP_102

VCCP_103

VCCP_104

VCCP_105

VCCP_106

VCCP_107

VCCP_108

VCCP_109

VCCP_110

VCC_101

VCC_102

VCC_103

VCC_104

VCC_105

VCC_106

VCC_107

VCC_108

VCC_109

VCC_110

VCC_111

VCC_112

VCC_113

VCC_114

VCC_115

VCC_116

VCC_117

VCC_118

VCC_119

VCC_120

VCC_121

VCC_122

VCC_123

VCC_124

VCC_125

VCC_126

VCC_127

VCC_128

VCC_129

VCC_130

VCC_131

VCC_132

VCC_133

VCC_134

VCC_135

VCC_136

VCC_137

VCC_138

VCC_139

VCC_140

VCC_141

VCC_142

VCC_143

VCC_144

VCC_145

VCC_146

VCC_147

VCC_148

VCC_149

VCC_150

VCC_151

VCC_152

VCC_153

VCC_154

VCC_155

VCC_156

VCC_157

VCC_158

VCC_159

VCC_160

VCC_161

VCC_162

VCC_163

VCC_164

VCC_165

VCC_166

VCC_167

VCC_168

VCC_169

VCC_170

VCC_171

VCC_172

VCC_173

VCC_174

VCC_175

VCC_176

VCC_177

VCC_178

VCC_179

VCC_180

VCC_181

VCC_182

VCC_183

VCC_184

VCC_185

VCC_186

VCC_187

VCC_188

VCC_189

VCC_190

F24

F22

B22

B24

D22

D24

H24

BB26

BD28

BD26

H22

T24

K24

T22

K22

P24

P22

V24

V22

Y24

M24

M22

Y22

AF24

AF22

AB24

AB22

AD24

AD22

AH24

AH22

AT24

AK24

AT22

AK22

AP24

AP22

AV24

AV22

AY24

AY22

BB24

BB22

AM24

AM22

BD24

F18

F16

B16

B18

B20

D16

BD22

F20

K18

D18

K16

H18

H16

D20

H20

T18

T16

K20

P18

M18

M16

M20

T20

P16

V18

V16

P20

V20

Y18

Y16

Y20

AF18

AF16

AB18

AB16

AD18

AD16

AF20

AB20

AD20

AK18

AH18

AH16

AH20

VCC_201

VCC_202

AV16

VCC_203

AY18

AY16

VCC_204

VCC_205

AT20

VCC_206

VCC_207

AV20

AY20

AA9

AA7

VCC_208

BB18

BB16

AC9

VCCP_129

VCCP_130

VCC_209

VCC_210

BD18

AC7

AE9

VCCP_131

VCC_211

BB20

BD16

AE7

VCCP_132

VCCP_133

VCC_212

VCC_213

BD20

AG9

AG7

VCCP_134

VCC_214

AP14

AM14

AJ9

VCCP_135

VCCP_136

VCC_215

VCC_216

AT14

AJ7

AL9

VCCP_137

VCC_217

AV14

AY14

AL7

VCCP_138

VCCP_139

VCC_218

VCC_219

BB14

AN9

AN7

VCCP_140

VCC_220

BD14

VCCP_141

AR9

AR7

A33

VCCP_142

VCCP_143

VCCP_144

VCCP_018

VCCP_019

VCCP_017

AJ37

AF38

AG37

A13

U1F

U1F
PENRYN SFF_UFCBGA956

PENRYN SFF_UFCBGA956

VCCP_145

VCCP_020

AK38

+VCC_CORE +VCCP

B B

A A

5

4

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/02/13 2006/03/10

2006/02/13 2006/03/10

2006/02/13 2006/03/10

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, M/B LA-4021P

SCHEMATIC, M/B LA-4021P

SCHEMATIC, M/B LA-4021P

401554

401554

401554

1

of

of

of

636Wednesday, June 03, 2009

636Wednesday, June 03, 2009

636Wednesday, June 03, 2009

B

B

B

5

U1D

U1D

B42

VSS[001]

F44

VSS[002]

D44

VSS[003]

D42

VSS[004]

F42

VSS[005]

H42

VSS[006]

K42

VSS[007]

M42

VSS[008]

P42

VSS[009]

T42

VSS[010]

V42

VSS[011]

Y42

D D

C C

B B

A A

VSS[012]

AB42

VSS[013]

AD42

VSS[014]

AF42

VSS[015]

AH42

VSS[016]

AK42

VSS[017]

AM42

VSS[018]

AP42

VSS[019]

AY44

VSS[020]

AV44

VSS[021]

AT42

VSS[022]

AV42

VSS[023]

AY42

VSS[024]

BA43

VSS[025]

BB42

VSS[026]

C39

VSS[027]

E39

VSS[028]

G37

VSS[029]

H38

VSS[030]

J39

VSS[031]

L39

VSS[032]

M38

VSS[033]

N39

VSS[034]

R39

VSS[035]

T38

VSS[036]

U39

VSS[037]

W39

VSS[038]

Y38

VSS[039]

AA39

VSS[040]

AC39

VSS[041]

AD38

VSS[042]

AE39

VSS[043]

AG39

VSS[044]

AH38

VSS[045]

AJ39

VSS[046]

AL39

VSS[047]

AM38

VSS[048]

AN39

VSS[049]

AR39

VSS[050]

AR37

VSS[051]

AT38

VSS[052]

AU39

VSS[053]

AU37

VSS[054]

AW39

VSS[055]

AW37

VSS[056]

BA39

VSS[057]

BC41

VSS[058]

BD40

VSS[059]

BD38

VSS[060]

B36

VSS[061]

H34

VSS[062]

D36

VSS[063]

K34

VSS[064]

M34

VSS[065]

M36

VSS[066]

P34

VSS[067]

T34

VSS[068]

V34

VSS[069]

T36

VSS[070]

Y34

VSS[071]

AB34

VSS[072]

AD34

VSS[073]

Y36

VSS[074]

AD36

VSS[075]

AF34

VSS[076]

AH34

VSS[077]

AH36

VSS[078]

AK34

VSS[079]

AM34

VSS[080]

AP34

VSS[081]

PENRYN SFF_UFCBGA956

PENRYN SFF_UFCBGA956

VSS[082]
VSS[083]
VSS[084]
VSS[085]
VSS[086]
VSS[087]
VSS[088]
VSS[089]
VSS[090]
VSS[091]
VSS[092]
VSS[093]
VSS[094]
VSS[095]
VSS[096]
VSS[097]
VSS[098]
VSS[099]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
VSS[159]
VSS[160]
VSS[161]
VSS[162]
VSS[163]

AM36
AR35
AU35
AV34
AW35
AW33
AY34
AT36
AV36
BA33
BC33
BB36
BD36
C27
C29
C31
E29
E27
G29
G27
E31
G31
J29
J27
L29
L27
N29
N27
J31
L31
N31
R29
R27
U29
U27
R31
U31
W29
W27
W31
AA29
AA27
AC29
AC27
AA31
AC31
AE29
AE27
AG29
AG27
AJ29
AJ27
AE31
AG31
AJ31
AL29
AL27
AN29
AN27
AL31
AN31
AR29
AR27
AR31
AU29
AU27
AW29
AW27
AU31
AW31
BA29
BA27
BC29
BC27
BA31
BC31
C21
C23
C25
E25
E23
E21

5

U1E

U1E

G25

VSS_164

G23

VSS_165

G21

VSS_166

J25

VSS_167

J23

VSS_168

J21

VSS_169

L25

VSS_170

L23

VSS_171

L21

VSS_172

N25

VSS_173

N23

VSS_174

N21

VSS_175

R25

VSS_176

R23

VSS_177

R21

VSS_178

U25

VSS_179

U23

VSS_180

U21

VSS_181

W25

VSS_182

W23

VSS_183

W21

VSS_184

AA25

VSS_185

AA23

VSS_186

AA21

VSS_187

AC25

VSS_188

AC23

VSS_189

AC21

VSS_190

AE25

VSS_191

AE23

VSS_192

AE21

VSS_193

AG25

VSS_194

AG23

VSS_195

AG21

VSS_196

AJ25

VSS_197

AJ23

VSS_198

AJ21

VSS_199

AL25

VSS_200

AL23

VSS_201

AL21

VSS_202

AN25

VSS_203

AN23

VSS_204

AN21

VSS_205

AR25

VSS_206

AR23

VSS_207

AR21

VSS_208

AU25

VSS_209

AU23

VSS_210

AU21

VSS_211

AW25

VSS_212

AW23

VSS_213

AW21

VSS_214

BA25

VSS_215

BA23

VSS_216

BA21

VSS_217

BC25

VSS_218

BC23

VSS_219

BC21

VSS_220

C17

VSS_221

C19

VSS_222

E19

VSS_223

E17

VSS_224

G19

VSS_225

G17

VSS_226

J19

VSS_227

J17

VSS_228

L19

VSS_229

L17

VSS_230

N19

VSS_231

N17

VSS_232

R19

VSS_233

R17

VSS_234

U19

VSS_235

U17

VSS_236

W19

VSS_237

W17

VSS_238

AA19

VSS_239

AA17

VSS_240

AC19

VSS_241

AC17

VSS_242

AE19

VSS_243

AE17

VSS_244

AG19

VSS_245

AG17

VSS_246

AJ19

VSS_247

AJ17

VSS_248

AL19

VSS_249

AL17

VSS_250

AN19

VSS_251

AN17

VSS_252

AR19

VSS_253

AR17

VSS_254

AU19

VSS_255

AU17

VSS_256

AW19

VSS_257

AW17

VSS_258

BA19

VSS_259

BA17

VSS_260

BC19

VSS_261

BC17

VSS_262

C11

VSS_263

C15

VSS_264

E15

VSS_265

G15

VSS_266

H10

VSS_267

M12

VSS_268

J15

VSS_269

L15

VSS_270

N15

VSS_271

M10

VSS_272

T12

VSS_273

R15

VSS_274

U15

VSS_275

W15

VSS_276

T10

VSS_277

Y12

VSS_278

AD12

VSS_279

PENRYN SFF_UFCBGA956

PENRYN SFF_UFCBGA956

VSS_280
VSS_281
VSS_282
VSS_283
VSS_284
VSS_285
VSS_286
VSS_287
VSS_288
VSS_289
VSS_290
VSS_291
VSS_292
VSS_293
VSS_294
VSS_295
VSS_296
VSS_297
VSS_298
VSS_299
VSS_300
VSS_301
VSS_302
VSS_303
VSS_304
VSS_305
VSS_306
VSS_307
VSS_308
VSS_309
VSS_310
VSS_311
VSS_312
VSS_313
VSS_314
VSS_315
VSS_316
VSS_317
VSS_318
VSS_319
VSS_320
VSS_321
VSS_322
VSS_323
VSS_324
VSS_325
VSS_326
VSS_327
VSS_328
VSS_329
VSS_330
VSS_331
VSS_332
VSS_333
VSS_334
VSS_335
VSS_336
VSS_337
VSS_338
VSS_339
VSS_340
VSS_341
VSS_342
VSS_343
VSS_344
VSS_345
VSS_346
VSS_347
VSS_348
VSS_349
VSS_350
VSS_351
VSS_352
VSS_353
VSS_354
VSS_355
VSS_356
VSS_357
VSS_358
VSS_359
VSS_360
VSS_361
VSS_362
VSS_363
VSS_364
VSS_365
VSS_366
VSS_367
VSS_368
VSS_369
VSS_370
VSS_371
VSS_372
VSS_373
VSS_374
VSS_375
VSS_376
VSS_377
VSS_378
VSS_379
VSS_380
VSS_381
VSS_382
VSS_383
VSS_384
VSS_385
VSS_386
VSS_387
VSS_388
VSS_389
VSS_390
VSS_391
VSS_392
VSS_393
VSS_394
VSS_395

AA15
AC15
Y10
AD10
AH12
AE15
AG15
AJ15
AH10
AM12
AL15
AN15
AR15
AM10
AT12
AV12
AW13
AW11
AY12
AU15
AW15
AT10
BA13
BA11
BB12
BC11
BA15
BC15
B6
D6
E9
F6
G9
H6
K8
K6
M8
M6
P8
P6
T8
T6
V8
V6
U5
Y8
Y6
AB8
AB6
AD8
AD6
AF8
AF6
AH8
AH6
AK8
AK6
AM8
AM6
AP8
AP6
AT8
AT6
AU9
AV6
AU7
AW9
AY6
BA9
BB6
BC9
BD6
B4
C3
E3
G3
J3
L3
N3
R3
U3
W3
AA3
AC3
AE3
AG3
AJ3
AL3
AN3
AR3
AU3
AW3
BA3
BC3
D2
E1
G1
AW1
BA1
BB2
A41
A39
A29
A27
A31
A25
A23
A21
A19
A17
A11
A15
A7
A5
A9
BD4

4

+VCC_CORE

10U_0805_6.3V6MC810U_0805_6.3V6M

1

C8

2

+VCC_CORE

1U_0402_6.3V6K

1U_0402_6.3V6K

1

C620

C620

2

Mid Frequence Decoupling

10U_0805_6.3V6MC910U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M

1

1

C9

C10

C10

2

2

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1

1

C622

C622

C621

C621

2

2

3

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M

1

C16

C16

C17

C17

2

High Frequence Decoupling

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1

C623

C623

C624

C624

2

10U_0805_6.3V6M

1

1

C18

C18

C21

2

1

2

C21

2

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1

C625

C625

C626

C626

2

10U_0805_6.3V6M

1

1

2

1

2

1

C22

C22

C23

C23

2

2

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1

1

C628

C628

C627

C627

2

2

2

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M

C29

C29

1U_0402_6.3V6K

1U_0402_6.3V6K

C629

C629

10U_0805_6.3V6M

10U_0805_6.3V6M

1

1

C30

C30

C31

C31

2

2

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1

1

2

C630

C630

C631

C631

2

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M

1

C11

C11

2

1U_0402_6.3V6K

1U_0402_6.3V6K

1

C632

C632

2

10U_0805_6.3V6M

10U_0805_6.3V6M

1

1

C12

C12

C13

C13

2

2

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1

1

C634

C634

C633

C633

2

2

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M

1

C14

C14

2

1U_0402_6.3V6K

1U_0402_6.3V6K

1

C635

C635

2

10U_0603_6.3V6M

1

1

C15

C15

C19

C19

2

2

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1

1

C636

C636

C637

C637

2

2

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

1

2

1

2

1

1

C24

C24

C20

C20

2

2

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1

1

C639

C639

C638

C638

2

2

1

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

1

C26

C26

C25

C25

2

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1

C641

C641

C640

C640

2

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

1

2

1

2

1

1

C28

C28

C27

C27

2

2

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1

1

C642

C642

C643

C643

2

2

6/14 :Replace 12pcs 10uF_0805 to 24 pcs 1uF_0402 for CPU transient fail issue.

ESR <= 1.5m ohm

Near CPU CORE regulator

+VCC_CORE

220U_D2_2VK_R9

220U_D2_2VK_R9

1

+

+

C34

C34

2

Del C37 to improve power plan. 6/14

+VCCP

1U_0603_10V4Z

1U_0603_10V4Z

C38

C38

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/02/13 2006/03/10

2006/02/13 2006/03/10

2006/02/13 2006/03/10

1U_0603_10V4Z

1U_0603_10V4Z

1U_0603_10V4Z

1U_0603_10V4Z

1

1

C40

C40

C39

C39

2

2

1U_0603_10V4Z

1U_0603_10V4Z

1U_0603_10V4Z

1U_0603_10V4Z

1

2

Compal Secret Data

Compal Secret Data

Compal Secret Data

1

1

C42

C42

C41

C41

2

2

Deciphered Date

Deciphered Date

Deciphered Date

220U_D2_2VK_R9

220U_D2_2VK_R9

220U_D2_2VK_R9

1

+

+

C35

C35

2

1U_0603_10V4Z

1U_0603_10V4Z

C43

C43

220U_D2_2VK_R9

1

+

+

C36

C36

2

1U_0603_10V4Z

1U_0603_10V4Z

1

C552

C552

2

1U_0603_10V4Z

1U_0603_10V4Z

1U_0603_10V4Z

1U_0603_10V4Z

1

1

C553

C553

C554

2

C554

2

2

1U_0603_10V4Z

1U_0603_10V4Z

1

C555

C555

2

1U_0603_10V4Z

1U_0603_10V4Z

1U_0603_10V4Z

1U_0603_10V4Z

1

1

1

2

C557

C557

C556

C556

2

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, M/B LA-4021P

SCHEMATIC, M/B LA-4021P

SCHEMATIC, M/B LA-4021P

401554

401554

401554

1

B

B

B

of

of

of

736Wednesday, June 03, 2009

736Wednesday, June 03, 2009

736Wednesday, June 03, 2009

5

U4A

H_D#[0..63]<5>

D D

C C

H_RESET#<4>

H_CPUSLP#<5>

B B

H_VREF

1

C51

C51

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

@

@

Trace < = 500mils

layout note:
Route H_SCOMP and H_SCOMP# with trace width,

spacing and impedance (55 ohm) same as FSB data
traces

Layout Note:
H_RCOMP / H_VREF / H_SWNG

trace width and spacing is 10/20

+VCCP

12

R53

R53

1K_0402_1%

1K_0402_1%

12

A A

R592K_0402_1% R592K_0402_1%

within 100 mils from NB

H_SWNG
H_RCOMP

H_VREF

24.9_0402_1%

24.9_0402_1%

5

H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63

H_RCOMP

12

R60

R60

U4A

J7

H_D#_0

H6

H_D#_1

L11

H_D#_2

J3

H_D#_3

H4

H_D#_4

G3

H_D#_5

K10

H_D#_6

K12

H_D#_7

L1

H_D#_8

M10

H_D#_9

M6

H_D#_10

N11

H_D#_11

L7

H_D#_12

K6

H_D#_13

M4

H_D#_14

K4

H_D#_15

P6

H_D#_16

W9

H_D#_17

V6

H_D#_18

V2

H_D#_19

P10

H_D#_20

W7

H_D#_21

N9

H_D#_22

P4

H_D#_23

U9

H_D#_24

V4

H_D#_25

U1

H_D#_26

W3

H_D#_27

V10

H_D#_28

U7

H_D#_29

W11

H_D#_30

U11

H_D#_31

AC11

H_D#_32

AC9

H_D#_33

Y4

H_D#_34

Y10

H_D#_35

AB6

H_D#_36

AA9

H_D#_37

AB10

H_D#_38

AA1

H_D#_39

AC3

H_D#_40

AC7

H_D#_41

AD12

H_D#_42

AB4

H_D#_43

Y6

H_D#_44

AD10

H_D#_45

AA11

H_D#_46

AB2

H_D#_47

AD4

H_D#_48

AE7

H_D#_49

AD2

H_D#_50

AD6

H_D#_51

AE3

H_D#_52

AG9

H_D#_53

AG7

H_D#_54

AE11

H_D#_55

AK6

H_D#_56

AF6

H_D#_57

AJ9

H_D#_58

AH6

H_D#_59

AF12

H_D#_60

AH4

H_D#_61

AJ7

H_D#_62

AE9

H_D#_63

B6

H_SWING

D4

H_RCOMP

J11

H_CPURST#

G9

H_CPUSLP#

L17

H_AVREF

K18

H_DVREF

CANTIGA GMCH SFF_FCBGA1363

CANTIGA GMCH SFF_FCBGA1363

+VCCP

12

R54

R54

221_0603_1%

221_0603_1%

12

R61

100_0402_1%

100_0402_1%

R61

H_SWNG

1

C52

C52

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

Near B6 pin

H_ADSTB#_0
H_ADSTB#_1

H_BREQ#

H_DEFER#

HOST

HOST

HPLL_CLK

HPLL_CLK#

H_DPWR#

H_DRDY#

H_DINV#_0
H_DINV#_1
H_DINV#_2
H_DINV#_3

H_DSTBN#_0
H_DSTBN#_1
H_DSTBN#_2
H_DSTBN#_3

H_DSTBP#_0
H_DSTBP#_1
H_DSTBP#_2
H_DSTBP#_3

H_REQ#_0
H_REQ#_1
H_REQ#_2
H_REQ#_3
H_REQ#_4

layout note:
Place them close to U4 pin BC51.

Layout Note: V_DDR_MCH_REF trace
width and spacing is 20/20.

H_A#_3
H_A#_4
H_A#_5
H_A#_6
H_A#_7
H_A#_8

H_A#_9
H_A#_10
H_A#_11
H_A#_12
H_A#_13
H_A#_14
H_A#_15
H_A#_16
H_A#_17
H_A#_18
H_A#_19
H_A#_20
H_A#_21
H_A#_22
H_A#_23
H_A#_24
H_A#_25
H_A#_26
H_A#_27
H_A#_28
H_A#_29
H_A#_30
H_A#_31
H_A#_32
H_A#_33
H_A#_34
H_A#_35

H_ADS#

H_BNR#
H_BPRI#

H_DBSY#

H_HIT#
H_HITM#

H_LOCK#
H_TRDY#

H_RS#_0
H_RS#_1
H_RS#_2

PM_EXTTS#0
PM_EXTTS#1

4

H_A#3

L15

H_A#4

B14

H_A#5

C15

H_A#6

D12

H_A#7

F14

H_A#8

G17

H_A#9

B12

H_A#10

J15

H_A#11

D16

H_A#12

C17

H_A#13

D14

H_A#14

K16

H_A#15

F16

H_A#16

B16

H_A#17

C21

H_A#18

D18

H_A#19

J19

H_A#20

J21

H_A#21

B18

H_A#22

D22

H_A#23

G19

H_A#24

J17

H_A#25

L21

H_A#26

L19

H_A#27

G21

H_A#28

D20

H_A#29

K22

H_A#30

F18

H_A#31

K20

H_A#32

F20

H_A#33

F22

H_A#34

B20

H_A#35

A19
F10

A15
C19
C9
B8
C11
E5
D6
AH10
AJ11
G11
H2
C7
F8
A11
D8

L9
N7
AA7
AG3

K2
N3
AA3
AF4

L3
M2
Y2
AF2

J13
L13
C13
G13
G15

F4
F2
G7

V_DDR_MCH_REF<14,15>

R46 10K_0402_5%

R46 10K_0402_5%
R47 10K_0402_5%R47 10K_0402_5%

Del R48. 9/27

4

V_DDR_MCH_REF

1 2
1 2

H_A#[3..35] <4>

Add them for Boundary Scan. 10/23

H_ADS# <4>
H_ADSTB#0 <4>
H_ADSTB#1 <4>
H_BNR# <4>
H_BPRI# <4>
H_BR0# <4>
H_DEFER# <4>
H_DBSY# <4>
CLK_MCH_BCLK <16>
CLK_MCH_BCLK# <16>
H_DPWR# <5>
H_DRDY# <4>
H_HIT# <4>
H_HITM# <4>
H_LOCK# <4>
H_TRDY# <4>

H_DINV#0 <5>
H_DINV#1 <5>
H_DINV#2 <5>
H_DINV#3 <5>

H_DSTBN#0 <5>
H_DSTBN#1 <5>
H_DSTBN#2 <5>
H_DSTBN#3 <5>

H_DSTBP#0 <5>
H_DSTBP#1 <5>
H_DSTBP#2 <5>
H_DSTBP#3 <5>

H_REQ#0 <4>
H_REQ#1 <4>
H_REQ#2 <4>
H_REQ#3 <4>
H_REQ#4 <4>

H_RS#0 <4>
H_RS#1 <4>
H_RS#2 <4>

H_THERMTRIP#<4,21>

PM_DPRSLPVR<22,42>

C50

C50

1

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

+3VS

3

T5T5
T6T6
T7T7
T8T8
T9T9
T10T10
T11T11
T12T12
T13T13

R251

+3VS

SMRCOMP_VOH

SMRCOMP_VOL

R251

1 2

R281

R281

1 2

R311 4.7K_0402_5%@R311 4.7K_0402_5%@

1 2

R619 1K_0402_5% @R619 1K_0402_5% @

1 2

2.2U_0603_6.3V4Z

2.2U_0603_6.3V4Z

2.2U_0603_6.3V4Z

2.2U_0603_6.3V4Z

PM_BMBUSY#<22>

H_DPRSTP#<5,21,42>
PM_EXTTS#0<14>
PM_EXTTS#1<15>
PM_PWROK<22,33,42,43>
PLT_RST#<20,26,32>

1 2

R49 0_0402_5%R49 0_0402_5%

1K_0402_5% @

1K_0402_5% @

4.7K_0402_5%@

4.7K_0402_5%@

+1.8V

1

1

C45

C45

0.01U_0402_25V7K

0.01U_0402_25V7K

2

1

C47

C47

2

0.01U_0402_25V7K

0.01U_0402_25V7K

MCH_CLKSEL0<16>
MCH_CLKSEL1<16>
MCH_CLKSEL2<16>

12

12

12

R327 0_0402_5%R327 0_0402_5%
R428 100_0402_1% R428 100_0402_1%

C44

C44

2

1

C46

C46

2

Add R428 in 9/26

+1.8V

12

R52

R52
10K_0402_1%

10K_0402_1%

12

R55

R55
10K_0402_1%

10K_0402_1%

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

TCK
TDI
TDO
TMS

T18T18
T19T19

T20T20

T21T21

T22T22
T23T23
T24T24

R39

R39
1K_0402_1%

1K_0402_1%

R40

R40

3.01K_0402_1%

3.01K_0402_1%

R41

R41
1K_0402_1%

1K_0402_1%

T27T27

T28T28
CFG5<10>
CFG6<10>
CFG7<10>

T88T88
CFG9<10>

CFG10<10>

T89T89

CFG12<10>
CFG13<10>

T90T90

T91T91

CFG16<10>

T92T92

T93T93

CFG19<10>
CFG20<10>

PM_EXTTS#0
PM_EXTTS#1

1 2
1 2

2006/02/13 2006/03/10

2006/02/13 2006/03/10

2006/02/13 2006/03/10

T25T25

C480.1U_0402_16V4Z @ C480.1U_0402_16V4Z @

1

2

U4B

U4B

J43

RSVD1

L43

RSVD2

J41

RSVD3

L41

RSVD4

AN11

RSVD5

AM10

RSVD6

AK10

RSVD7

AL11

RSVD8

F12

RSVD9

AN45

RSVD10

AP44

RSVD11

AT44

RSVD12

AN47

RSVD13

C27

RSVD14

D30

RSVD15

J9

RSVD17

AW42

RSVD20

BB20

RSVD22

BE19

RSVD23

BF20

RSVD24

BF18

RSVD25

K26

CFG_0

G23

CFG_1

G25

CFG_2

J25

CFG_3

L25

CFG_4

L27

CFG_5

F24

CFG_6

D24

CFG_7

D26

CFG_8

J23

CFG_9

B26

CFG_10

A23

CFG_11

C23

CFG_12

B24

CFG_13

B22

CFG_14

K24

CFG_15

C25

CFG_16

L23

CFG_17

L33

CFG_18

K32

CFG_19

K34

CFG_20

J35

PM_SYNC#

F6

PM_DPRSTP#

J39

PM_EXT_TS#_0

L39

PM_EXT_TS#_1

AY39

PWROK

BB18

RSTIN#

K28

THERMTRIP#

K36

DPRSLPVR

A7

NC_1

A49

NC_2

A52

NC_3

A54

NC_4

B54

NC_5

D55

NC_6

G55

NC_7

BE55

NC_8

BH55

NC_9

BK55

NC_10

BK54

NC_11

BL54

NC_12

BL52

NC_13

BL49

NC_14

BL7

NC_15

BL4

NC_16

BL2

NC_17

BK2

NC_18

BK1

NC_19

BH1

NC_20

BE1

NC_21

G1

NC_22

Compal Secret Data

Compal Secret Data

Compal Secret Data

CANTIGA GMCH SFF_FCBGA1363

CANTIGA GMCH SFF_FCBGA1363

Deciphered Date

Deciphered Date

Deciphered Date

CFGRSVD

CFGRSVD

PM

PM

NC

NC

2

BB32

SA_CK_0

BA25

SA_CK_1

BA33

SB_CK_0

BA23

SB_CK_1

BA31

SA_CK#_0

BC25

SA_CK#_1

BC33

SB_CK#_0

BB24

SB_CK#_1

BC35

SA_CKE_0

BE33

SA_CKE_1

BE37

SB_CKE_0

BC37

SB_CKE_1

BK18

SA_CS#_0

BK16

SA_CS#_1

BE23

SB_CS#_0

BC19

SB_CS#_1

BJ17

SA_ODT_0

BJ19

SA_ODT_1

BC17

SB_ODT_0

BE17

SB_ODT_1

SM_RCOMP

SM_RCOMP#

SM_RCOMP_VOH

SM_RCOMP_VOL

SM_VREF

SM_PWROK

SM_REXT

SM_DRAMRST#
DPLL_REF_CLK

DPLL_REF_CLK#

DDR CLK/ CONTROL/COMPENSATION

DDR CLK/ CONTROL/COMPENSATION

DPLL_REF_SSCLK

DPLL_REF_SSCLK#

PEG_CLK

PEG_CLK#

CLK

CLK

DMI_RXN_0
DMI_RXN_1
DMI_RXN_2
DMI_RXN_3

DMI_RXP_0
DMI_RXP_1
DMI_RXP_2
DMI_RXP_3

DMI_TXN_0
DMI_TXN_1
DMI_TXN_2
DMI_TXN_3

DMI_TXP_0
DMI_TXP_1

DMI

DMI

DMI_TXP_2
DMI_TXP_3

GFX_VID_0
GFX_VID_1
GFX_VID_2
GFX_VID_3
GFX_VID_4

GFX_VR_EN

GRAPHICS VID

GRAPHICS VID

CL_CLK

CL_DATA

CL_PWROK

CL_RST#
CL_VREF

ME

ME

DDPC_CTRLCLK

DDPC_CTRLDATA

SDVO_CTRLCLK

SDVO_CTRLDATA

CLKREQ#

ICH_SYNC#

MISC

MISC

TSATN#

HDA_BCLK

HDA_RST#

HDA_SDI

HDA_SDO

HDA_SYNC

HDA

HDA

2

SMRCOMP

BL25

SMRCOMP#

BK26

SMRCOMP_VOH

BK32

SMRCOMP_VOL

BL31

V_DDR_MCH_REF

BC51

SM_PWROK

AY37

SM_REXT

BH20

TP_SM_DRAMRST#

BA37
B42

D42
B50
D50

R49
P50

AG55
AL49
AH54
AL47

AG53
AK50
AH52
AL45

AG49
AJ49
AJ47
AG47

AF50
AH50
AJ45
AG45

G33
G37
F38
F36
G35

G39

AK52
AK54
AW40
AL53

CL_VREF

AL55

F34
F32
B38
A37
C31
K42

TSATN#

D10

C29
B30
D28
A27
B28

R616 54.9_0402_1%R616 54.9_0402_1%

Romoved, cause
don't need HDMI.
7/19

Title

Title

Title

SCHEMATIC, M/B LA-4021P

SCHEMATIC, M/B LA-4021P

SCHEMATIC, M/B LA-4021P

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

401554

401554

401554

Date: Sheet

Date: Sheet

Date: Sheet

M_CLK_DDR0 <14>
M_CLK_DDR1 <14>
M_CLK_DDR2 <15>
M_CLK_DDR3 <15>

M_CLK_DDR#0 <14>
M_CLK_DDR#1 <14>
M_CLK_DDR#2 <15>
M_CLK_DDR#3 <15>

DDR_CKE0_DIMMA <14>
DDR_CKE1_DIMMA <14>
DDR_CKE2_DIMMB <15>
DDR_CKE3_DIMMB <15>

DDR_CS0_DIMMA# <14>
DDR_CS1_DIMMA# <14>
DDR_CS2_DIMMB# <15>
DDR_CS3_DIMMB# <15>

M_ODT0 <14>
M_ODT1 <14>
M_ODT2 <15>
M_ODT3 <15>

R42 80.6_0402_1%

R42 80.6_0402_1%

1 2

R43 80.6_0402_1%R43 80.6_0402_1%

1 2

R44 10K_0402_1%

R44 10K_0402_1%

1 2

R45 499_0402_1%R45 499_0402_1%

1 2

T26 PADT26 PAD

CLK_MCH_DREFCLK <16>
CLK_MCH_DREFCLK# <16>
MCH_SSCDREFCLK <16>
MCH_SSCDREFCLK# <16>

CLK_MCH_3GPLL <16>
CLK_MCH_3GPLL# <16>

DMI_TXN0 <22>
DMI_TXN1 <22>
DMI_TXN2 <22>
DMI_TXN3 <22>

DMI_TXP0 <22>
DMI_TXP1 <22>
DMI_TXP2 <22>
DMI_TXP3 <22>

DMI_RXN0 <22>
DMI_RXN1 <22>
DMI_RXN2 <22>
DMI_RXN3 <22>

DMI_RXP0 <22>
DMI_RXP1 <22>
DMI_RXP2 <22>
DMI_RXP3 <22>

DFGT_VID_0 <43>
DFGT_VID_1 <43>
DFGT_VID_2 <43>
DFGT_VID_3 <43>
DFGT_VID_4 <43>

GFXVR_EN <43>

CL_CLK0 <22>
CL_DATA0 <22>
M_PWROK <22,35>
CL_RST# <22>

T29T29

0.1U_0402_16V4Z

0.1U_0402_16V4Z

T30T30
T31T31
T32T32

CLKREQ#_B <16>
MCH_ICH_SYNC# <22>

1 2

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

1

Modify in 9/26

+1.05VM

1

C49

C49

2

+VCCP

836Wednesday, June 03, 2009

836Wednesday, June 03, 2009

836Wednesday, June 03, 2009

1

+1.8V

12

R50

R50
1K_0402_1%

1K_0402_1%

12

R51

R51
511_0402_1%

511_0402_1%

of

of

of

B

B

B

5

4

3

2

1

D D

DDR_A_D[0..63]<14>

C C

B B

DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63

U4D

U4D

AP46

SA_DQ_0

AU47

SA_DQ_1

AT46

SA_DQ_2

AU49

SA_DQ_3

AR45

SA_DQ_4

AN49

SA_DQ_5

AV50

SA_DQ_6

AP50

SA_DQ_7

AW47

SA_DQ_8

BD50

SA_DQ_9

AW49

SA_DQ_10

BA49

SA_DQ_11

BC49

SA_DQ_12

AV46

SA_DQ_13

BA47

SA_DQ_14

AY50

SA_DQ_15

BF46

SA_DQ_16

BC47

SA_DQ_17

BF50

SA_DQ_18

BF48

SA_DQ_19

BC43

SA_DQ_20

BE49

SA_DQ_21

BA43

SA_DQ_22

BE47

SA_DQ_23

BF42

SA_DQ_24

BC39

SA_DQ_25

BF44

SA_DQ_26

BF40

SA_DQ_27

BB40

SA_DQ_28

BE43

SA_DQ_29

BF38

SA_DQ_30

BE41

SA_DQ_31

BA15

SA_DQ_32

BE11

SA_DQ_33

BE15

SA_DQ_34

BF14

SA_DQ_35

BB14

SA_DQ_36

BC15

SA_DQ_37

BE13

SA_DQ_38

BF16

SA_DQ_39

BF10

SA_DQ_40

BC11

SA_DQ_41

BF8

SA_DQ_42

BG7

SA_DQ_43

BC7

SA_DQ_44

BC9

SA_DQ_45

BD6

SA_DQ_46

BF12

SA_DQ_47

AV6

SA_DQ_48

BB6

SA_DQ_49

AW7

SA_DQ_50

AY6

SA_DQ_51

AT10

SA_DQ_52

AW11

SA_DQ_53

AU11

SA_DQ_54

AW9

SA_DQ_55

AR11

SA_DQ_56

AT6

SA_DQ_57

AP6

SA_DQ_58

AL7

SA_DQ_59

AR7

SA_DQ_60

AT12

SA_DQ_61

AM6

SA_DQ_62

AU7

SA_DQ_63

CANTIGA GMCH SFF_FCBGA1363

CANTIGA GMCH SFF_FCBGA1363

BC21

SA_BS_0

BJ21

SA_BS_1

BJ41

SA_BS_2

BH22

SA_RAS#

BK20

SA_CAS#

BL15

SA_WE#

DDR_A_DM0

AT50

SA_DM_0
SA_DM_1
SA_DM_2
SA_DM_3
SA_DM_4
SA_DM_5
SA_DM_6
SA_DM_7

SA_DQS_0
SA_DQS_1
SA_DQS_2
SA_DQS_3
SA_DQS_4
SA_DQS_5
SA_DQS_6

SA_DQS_7
SA_DQS#_0
SA_DQS#_1
SA_DQS#_2
SA_DQS#_3
SA_DQS#_4
SA_DQS#_5
SA_DQS#_6
SA_DQS#_7

SA_MA_0
SA_MA_1
SA_MA_2
SA_MA_3
SA_MA_4
SA_MA_5
SA_MA_6
SA_MA_7
SA_MA_8

SA_MA_9
SA_MA_10
SA_MA_11
SA_MA_12

DDR SYSTEM MEMORY A

DDR SYSTEM MEMORY A

SA_MA_13
SA_MA_14

BB50
BB46
BE39
BB12
BE7
AV10
AR9

AR47
BA45
BE45
BC41
BC13
BB10
BA7
AN7
AR49
AW45
BC45
BA41
BA13
BA11
BA9
AN9

BC23
BF22
BE31
BC31
BH26
BJ35
BB34
BH32
BB26
BF32
BA21
BG25
BH34
BH18
BE25

DDR_A_DM1
DDR_A_DM2
DDR_A_DM3
DDR_A_DM4
DDR_A_DM5
DDR_A_DM6
DDR_A_DM7

DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7
DDR_A_DQS#0
DDR_A_DQS#1
DDR_A_DQS#2
DDR_A_DQS#3
DDR_A_DQS#4
DDR_A_DQS#5
DDR_A_DQS#6
DDR_A_DQS#7

DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA14

DDR_A_BS0 <14>
DDR_A_BS1 <14>
DDR_A_BS2 <14>

DDR_A_RAS# <14>
DDR_A_CAS# <14>

DDR_A_WE# <14>

DDR_A_DM[0..7] <14>

DDR_A_DQS[0..7] <14>

DDR_A_DQS#[0..7] <14>

DDR_A_MA[0..14] <14>

DDR_B_D[0..63]<15>

DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8

DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63

U4E

U4E

AP54

SB_DQ_0

AM52

SB_DQ_1

AR55

SB_DQ_2

AV54

SB_DQ_3

AM54

SB_DQ_4

AN53

SB_DQ_5

AT52

SB_DQ_6

AU53

SB_DQ_7

AW53

SB_DQ_8

AY52

SB_DQ_9

BB52

SB_DQ_10

BC53

SB_DQ_11

AV52

SB_DQ_12

AW55

SB_DQ_13

BD52

SB_DQ_14

BC55

SB_DQ_15

BF54

SB_DQ_16

BE51

SB_DQ_17

BH48

SB_DQ_18

BK48

SB_DQ_19

BE53

SB_DQ_20

BH52

SB_DQ_21

BK46

SB_DQ_22

BJ47

SB_DQ_23

BL45

SB_DQ_24

BJ45

SB_DQ_25

BL41

SB_DQ_26

BH44

SB_DQ_27

BH46

SB_DQ_28

BK44

SB_DQ_29

BK40

SB_DQ_30

BJ39

SB_DQ_31

BK10

SB_DQ_32

BH10

SB_DQ_33

BK6

SB_DQ_34

BH6

SB_DQ_35

BJ9

SB_DQ_36

BL11

SB_DQ_37

BG5

SB_DQ_38

BJ5

SB_DQ_39

BG3

SB_DQ_40

BF4

SB_DQ_41

BD4

SB_DQ_42

BA3

SB_DQ_43

BE5

SB_DQ_44

BF2

SB_DQ_45

BB4

SB_DQ_46

AY4

SB_DQ_47

BA1

SB_DQ_48

AP2

SB_DQ_49

AU1

SB_DQ_50

AT2

SB_DQ_51

AT4

SB_DQ_52

AV4

SB_DQ_53

AU3

SB_DQ_54

AR3

SB_DQ_55

AN1

SB_DQ_56

AP4

SB_DQ_57

AL3

SB_DQ_58

AJ1

SB_DQ_59

AK4

SB_DQ_60

AM4

SB_DQ_61

AH2

SB_DQ_62

AK2

SB_DQ_63

CANTIGA GMCH SFF_FCBGA1363

CANTIGA GMCH SFF_FCBGA1363

BJ13

SB_BS_0

BK12

SB_BS_1

BK38

SB_BS_2

BE21

SB_RAS#

BH14

SB_CAS#

BK14

SB_WE#

DDR_B_DM0

AP52

SB_DM_0
SB_DM_1
SB_DM_2
SB_DM_3
SB_DM_4
SB_DM_5
SB_DM_6
SB_DM_7

SB_DQS_0
SB_DQS_1
SB_DQS_2
SB_DQS_3
SB_DQS_4
SB_DQS_5
SB_DQS_6

SB_DQS_7
SB_DQS#_0
SB_DQS#_1
SB_DQS#_2
SB_DQS#_3
SB_DQS#_4
SB_DQS#_5
SB_DQS#_6
SB_DQS#_7

SB_MA_0
SB_MA_1
SB_MA_2
SB_MA_3
SB_MA_4
SB_MA_5
SB_MA_6
SB_MA_7
SB_MA_8

SB_MA_9
SB_MA_10
SB_MA_11
SB_MA_12
SB_MA_13
SB_MA_14

DDR SYSTEM MEMORY B

DDR SYSTEM MEMORY B

AY54
BJ49
BJ43
BH12
BD2
AY2
AJ3

AR53
BA53
BH50
BK42
BH8
BB2
AV2
AM2
AT54
BB54
BJ51
BH42
BK8
BC3
AW3
AN3

BJ15
BJ33
BH24
BA17
BF36
BH36
BF34
BK34
BJ37
BH40
BH16
BK36
BH38
BJ11
BL37

DDR_B_DM1
DDR_B_DM2
DDR_B_DM3
DDR_B_DM4
DDR_B_DM5
DDR_B_DM6
DDR_B_DM7

DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4
DDR_B_DQS5
DDR_B_DQS6

DDR_B_DQS7
DDR_B_DQS#0
DDR_B_DQS#1
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS#4
DDR_B_DQS#5
DDR_B_DQS#6
DDR_B_DQS#7

DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8

DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13
DDR_B_MA14

DDR_B_BS0 <15>
DDR_B_BS1 <15>
DDR_B_BS2 <15>

DDR_B_RAS# <15>
DDR_B_CAS# <15>
DDR_B_WE# <15>

DDR_B_DM[0..7] <15>

DDR_B_DQS[0..7] <15>

DDR_B_DQS#[0..7] <15>

DDR_B_MA[0..14] <15>

A A

5

4

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/02/13 2006/03/10

2006/02/13 2006/03/10

2006/02/13 2006/03/10

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, M/B LA-4021P

SCHEMATIC, M/B LA-4021P

SCHEMATIC, M/B LA-4021P

401554

401554

401554

936Wednesday, June 03, 2009

936Wednesday, June 03, 2009

936Wednesday, June 03, 2009

1

of

of

of

B

B

B

5

BLON_PWM<18>
ENABLT<18>

D D

+3VS

DDC2_CLK<18>
DDC2_DATA<18>

ENAVDD<18>

TXCLK_L-<18>
TXCLK_L+<18>

TXOUT_L0-<18>
TXOUT_L1-<18>
TXOUT_L2-<18>

TXOUT_L0+<18>
TXOUT_L1+<18>
TXOUT_L2+<18>

For make layout clearance, del
TP for channel B. 10/18

R65 10K_0402_5%

R65 10K_0402_5%

1 2

R66 10K_0402_5%

R66 10K_0402_5%

1 2

R67 4.22K_0402_1%

R67 4.22K_0402_1%

1 2

T33T33

For EMI. 9/26

R572 75_0402_5%@R572 75_0402_5%@

1 2

R336 75_0402_5%@R336 75_0402_5%@

C C

1 2

R337 75_0402_5%@R337 75_0402_5%@

1 2

Del TV_LUMA & CRMA in 10/12.

D_BLUE<17>

D_GREEN<17>

D_RED<17>

CRT_DDC_CLK<17>

CRT_DDC_DATA<17>

CRT_HSYNC<17>
CRT_VSYNC<17>

B B

R70 30.1_0402_1%

R70 30.1_0402_1%

1 2

R72 30.1_0402_1%

R72 30.1_0402_1%

1 2

Close to pin D32 and keep
30mil space to other
part/trace.

4

10/18

10/19

10/19

10/18

Tie to GND. 9/28

D_BLUE
D_GREEN
D_RED

CRT_HSYNC_R
CRT_VSYNC_R

R74

R74

1.02K_0402_1%

1.02K_0402_1%

1 2

U4C

U4C

D38

L_BKLT_CTRL

C37

L_BKLT_EN

K38

L_CTRL_CLK

L37

L_CTRL_DATA

J37

L_DDC_CLK

L35

L_DDC_DATA

B36

L_VDD_EN

F50

LVDS_IBG

H46

LVDS_VBG

P44

LVDS_VREFH

K46

LVDS_VREFL

D46

LVDSA_CLK#

B46

LVDSA_CLK

D44

LVDSB_CLK#

B44

LVDSB_CLK

G45

LVDSA_DATA#_0

F46

LVDSA_DATA#_1

G41

LVDSA_DATA#_2

C45

LVDSA_DATA#_3

F44

LVDSA_DATA_0

G47

LVDSA_DATA_1

F40

LVDSA_DATA_2

A45

LVDSA_DATA_3

B40

LVDSB_DATA#_0

A41

LVDSB_DATA#_1

F42

LVDSB_DATA#_2

D48

LVDSB_DATA#_3

D40

LVDSB_DATA_0

C41

LVDSB_DATA_1

G43

LVDSB_DATA_2

B48

LVDSB_DATA_3

J27

TVA_DAC

E27

TVB_DAC

G27

TVC_DAC

F26

TVA_RTN

B34

TV_DCONSEL_0

D34

TV_DCONSEL_1

J29

CRT_BLUE

G29

CRT_GREEN

F30

CRT_RED

E29

CRT_IRTN

D36

CRT_DDC_CLK

C35

CRT_DDC_DATA

J33

CRT_HSYNC

D32

CRT_TVO_IREF

G31

CRT_VSYNC

CANTIGA GMCH SFF_FCBGA1363

CANTIGA GMCH SFF_FCBGA1363

Del R82, R83. 10/18

3

PEGCOMP trace width
and spacing is 20/25 mils.

PEGCOMP

PEG_RX#_0
PEG_RX#_1
PEG_RX#_2
PEG_RX#_3
PEG_RX#_4
PEG_RX#_5
PEG_RX#_6
PEG_RX#_7
PEG_RX#_8
PEG_RX#_9

PEG_RX_0
PEG_RX_1
PEG_RX_2
PEG_RX_3
PEG_RX_4
PEG_RX_5
PEG_RX_6
PEG_RX_7
PEG_RX_8

PEG_RX_9
PEG_RX_10
PEG_RX_11
PEG_RX_12
PEG_RX_13
PEG_RX_14
PEG_RX_15

PEG_TX#_0
PEG_TX#_1
PEG_TX#_2
PEG_TX#_3
PEG_TX#_4
PEG_TX#_5
PEG_TX#_6
PEG_TX#_7
PEG_TX#_8
PEG_TX#_9

PEG_TX_0

PEG_TX_1

PEG_TX_2

PEG_TX_3

PEG_TX_4

PEG_TX_5

PEG_TX_6

PEG_TX_7

PEG_TX_8

PEG_TX_9
PEG_TX_10
PEG_TX_11
PEG_TX_12
PEG_TX_13
PEG_TX_14
PEG_TX_15

U45
T44

D52
G49
K54
H50
M52
N49
P54
V46
Y50
V52
W49
AB54
AD46
AC55
AE49
AF54

E51
F48
J55
J49
M54
M50
P52
U47
AA49
V54
V50
AB52
AC47
AC53
AD50
AF52

L47
F52
P46
H54
L55
T46
R53
U49
T54
Y46
AB46
W53
Y54
AC49
AF46
AD54

J47
F54
N47
H52
L53
R47
R55
T50
T52
W47
AA47
W55
Y52
AB50
AE47
AD52

PEG_COMPI

PEG_COMPO

LVDS

LVDS

TV

TV

PEG_RX#_10
PEG_RX#_11
PEG_RX#_12
PEG_RX#_13
PEG_RX#_14
PEG_RX#_15

PEG_TX#_10

PCI-EXPRESS GRAPHICS

PCI-EXPRESS GRAPHICS

PEG_TX#_11
PEG_TX#_12
PEG_TX#_13
PEG_TX#_14
PEG_TX#_15

VGA

VGA

Remove R84 ~ R86 since
already have 75ohm of
page17. 10/27

1 2

R64 49.9_0402_1%R64 49.9_0402_1%

layout note:
Place R64 <500mils to U4 pin U45&T44.

+VCC_PEG

2

Strap Pin Table

CFG[2:0] FSB Freq select

CFG[4:3] Reserved

CFG5 (DMI select)

CFG6

CFG6

CFG7 (Intel Management
Engine Crypto strap)

CFG8

CFG9
(PCIE Graphics Lane Reversal)

CFG10 (PCIE Lookback enable)

CFG11
CFG[13:12] (XOR/ALLZ)

CFG16 (FSB Dynamic ODT)

CFG19 (DMI Lane Reversal)

CFG20 (PCIE/SDVO concurrent)

1

000 = FSB 1066MHz
010 = FSB 800MHz
011 = FSB 667MHz

Others = Reserved

0 = DMI x 2

1 = DMI x 4

0 = The iTPM Host Interface is enable

*

1 = The iTPM Host Interface is disable

0 =(TLS)chiper suite with no confidentiality

1 =(TLS)chiper suite with confidentiality

Reserved

0 = Reverse Lane,15->0, 14->1

1 = Normal Operation,Lane Number in order

0 = Enable

1 = Disable

Reserved

00 = Reserved

01 = XOR Mode Enabled

10 = All Z Mode Enabled

*

(Default)11 = Normal Operation

ReservedCFG[15:14]

0 = Disabled

1 = Enabled

*

ReservedCFG[18:17]

0 = Normal Operation

(Lane number in Order)

*

1 = Reverse Lane

0 = Only PCIE or SDVO is operational.

1 = PCIE/SDVO are operating simu.

R91 2.21K_0402_1% @R91 2.21K_0402_1% @

CFG5<8>
CFG6<8>
CFG7<8>

CFG9<8>
CFG10<8>
CFG12<8>
CFG13<8>
CFG16<8>

CFG19<8>
CFG20<8>

1 2

R69 2.21K_0402_1% @R69 2.21K_0402_1% @

1 2

R71 2.21K_0402_1% @R71 2.21K_0402_1% @

1 2

R75 2.21K_0402_1% @R75 2.21K_0402_1% @

1 2

R76 2.21K_0402_1% @R76 2.21K_0402_1% @

1 2

R78 2.21K_0402_1%@R78 2.21K_0402_1%@

1 2

R79 2.21K_0402_1% @R79 2.21K_0402_1% @

1 2

R93 2.21K_0402_1% @R93 2.21K_0402_1% @

1 2

R90 4.02K_0402_1%@ R90 4.02K_0402_1%@

1 2

R92 4.02K_0402_1% @R92 4.02K_0402_1% @

1 2

*

*

*

*

*

+3VS

A A

5

4

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/02/13 2006/03/10

2006/02/13 2006/03/10

2006/02/13 2006/03/10

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, M/B LA-4021P

SCHEMATIC, M/B LA-4021P

SCHEMATIC, M/B LA-4021P

401554

401554

401554

10 36Wednesday, June 03, 2009

10 36Wednesday, June 03, 2009

10 36Wednesday, June 03, 2009

1

of

of

of

B

B

B

5

R96

R96

1

C97

C97

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

+3VS_DAC_CRT

12

10U_0603_6.3V

10U_0603_6.3V

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

C618

C618

C62

C62

2

2

R104 0_0603_5% R104 0_0603_5%

1 2

9/27

+1.05VM

+1.05VM_PEGPLL

9/27

C63

0.01U_0402_16V7K

0.01U_0402_16V7K
+3VS

R97

1

C63

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

R106 0_0805_5% R106 0_0805_5%

1

+

+

2

C82

C82

R110 0_0603_5%

R110 0_0603_5%

R97

BLM18PG181SN1D_0603

BLM18PG181SN1D_0603

+1.5VS_PEG_BG

1

C78

C78

2

1 2

100U_D2_6.3VM

100U_D2_6.3VM

1 2

1

C98

C98

R111 0_0603_5% R111 0_0603_5%

+1.8V

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

+3VS_DAC_BG

12

22U_0805_6.3V

22U_0805_6.3V

1

C64

C64

2

+1.8V_TXLVDS

1

C73

C73
1000P_0402_50V7K

1000P_0402_50V7K

2

9/27

10U_0805_6.3V6M

10U_0805_6.3V6M

C65

0.01U_0402_16V7K

0.01U_0402_16V7K

1

9/27

C65

+1.05VM_DPLLA

2

+1.05VM_DPLLB

+1.05VM_HPLL
+1.05VM_MPLL

+1.05VM_PEGPLL

+1.05VM_A_SM

1U_0603_10V4Z

1U_0603_10V4Z

4.7U_0805_10V4Z

4.7U_0805_10V4Z

1

1

2

2

C83

C83

C84

C84

+1.05VM_A_SM_CK

0.1U_0402_16V4Z

0.1U_0402_16V4Z

10U_0805_6.3V6M

10U_0805_6.3V6M

1

C93

C93

C92

C92

2

12

1

2

C85

C85

1

2

1U_0603_10V4Z

1U_0603_10V4Z

1

C99

C99

2

+3VS

BLM18PG181SN1D_0603

BLM18PG181SN1D_0603

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

D D

C617

C617

2

install 0.1U & 10U for wavy issue. 7/29

change 0.1U to 22U for wavy issue. 5/20

+1.5VS

C C

B B

+1.05VM_HPLL

+1.8V_LVDS

4

U4H

U4H

J31

VCCA_CRT_DAC

L31

VCCA_DAC_BG

M33

VSSA_DAC_BG

J45

VCCA_DPLLA

L49

VCCA_DPLLB

AF10

VCCA_HPLL

AE1

VCCA_MPLL

U43

VCCA_LVDS1

U41

VCCA_LVDS2

V44

VSSA_LVDS

AJ43

VCCA_PEG_BG

AG43

VCCA_PEG_PLL

AW24

VCCA_SM_1

AU24

VCCA_SM_2

AW22

VCCA_SM_3

AU22

VCCA_SM_4

AU21

VCCA_SM_5

AW20

VCCA_SM_6

AU19

VCCA_SM_7

AW18

VCCA_SM_8

AU18

VCCA_SM_9

AW16

VCCA_SM_10

AU16

VCCA_SM_11

AT16

VCCA_SM_12

AR16

VCCA_SM_13

AU15

VCCA_SM_14

AT15

VCCA_SM_15

AR15

VCCA_SM_16

AW14

VCCA_SM_17

AT24

VCCA_SM_NCTF_1

AR24

VCCA_SM_NCTF_2

AT22

VCCA_SM_NCTF_3

AR22

VCCA_SM_NCTF_4

AT21

VCCA_SM_NCTF_5

AR21

VCCA_SM_NCTF_6

AT19

VCCA_SM_NCTF_7

AR19

VCCA_SM_NCTF_8

AT18

VCCA_SM_NCTF_9

AR18

VCCA_SM_NCTF_10

AU27

VCCA_SM_CK_4

AU28

VCCA_SM_CK_3

AU29

VCCA_SM_CK_2

AU31

VCCA_SM_CK_1

AT31

VCCA_SM_CK_NCTF_1

AR31

VCCA_SM_CK_NCTF_2

AT29

VCCA_SM_CK_NCTF_3

AR29

VCCA_SM_CK_NCTF_4

AT28

VCCA_SM_CK_NCTF_5

AR28

VCCA_SM_CK_NCTF_6

AT27

VCCA_SM_CK_NCTF_7

AR27

VCCA_SM_CK_NCTF_8

AH12

VCCD_HPLL

AE43

VCCD_PEG_PLL

M46

VCCD_LVDS_1

L45

VCCD_LVDS_2

CANTIGA GMCH SFF_FCBGA1363

CANTIGA GMCH SFF_FCBGA1363

CRTPLLA PEGA SM

CRTPLLA PEGA SM

A LVDS

A LVDS

POWER

POWER

LVDS

LVDS

VTT_1
VTT_2
VTT_3
VTT_4
VTT_5
VTT_6
VTT_7
VTT_8

VTT_9
VTT_10
VTT_11
VTT_12
VTT_13

VTT

VTT

VCCA_TV_DAC

TVD TV/CRT

TVD TV/CRT

VCC_HDA

HDA

HDA

VCCD_QDAC

VCCD_TVDAC

VCC_AXF_1
VCC_AXF_2
VCC_AXF_3

AXF

AXF

VCC_SM_CK_1
VCC_SM_CK_2
VCC_SM_CK_3
VCC_SM_CK_4

SM CK

SM CK

VCC_TX_LVDS

VCC_HV_1
VCC_HV_2

HV

HV

VCC_PEG_1
VCC_PEG_2
VCC_PEG_3
VCC_PEG_4

PEG

PEG

VCC_DMI_1
VCC_DMI_2
VCC_DMI_3

DMI

DMI

VTTLF1
VTTLF2
VTTLF3

VTTLF

VTTLF

3

Change to 330u_R9,
casue high
limitation. 12/14

R13
T12
R11
T10
R9
T8
R7
T6
R5
T4
R3
T2
R1

K30

R101

R101
0_0402_5%

0_0402_5%

A31

1 2

N34

+1.5VS_QDAC

N32

+1.5VS_TVDAC

9/27

M25
N24
M23

BK24
BL23
BJ23
BK22

T41
C33

A33

AB44
Y44
AC43
AA43

AM44
AN43
AL43

K14
Y12
P2

0.47U_0603_10V7K

0.47U_0603_10V7K

1

C100

C100

2

+V1.05VM_AXF

+1.8V_SM_CK

+1.8V_TXLVDS

+VCC_PEG

+1.05VM_DMI

0.47U_0603_10V7K

0.47U_0603_10V7K

0.47U_0603_10V7K

0.47U_0603_10V7K

2.2U_0805_16V4Z

2.2U_0805_16V4Z

1

C58

2

C58

9/29

0.47U_0603_10V7K

0.47U_0603_10V7K

1

C101

C101

2

4.7U_0805_10V4Z

4.7U_0805_10V4Z

4.7U_0805_10V4Z

4.7U_0805_10V4Z

1

1

C60

C60

2

2

C59

C59

+3VS_TVDAC

0.01U_0402_16V7K

0.01U_0402_16V7K

Tie to GND. 9/27

+3VS_HV

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

2

C94

C94

1

C102

C102

2

1

2

C61

C61

C71

C71

+VCCP

1

2

C57

C57

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

2

+

+

330U_D2E_2.5VM_R9

330U_D2E_2.5VM_R9

R100

R100

1 2

BLM18PG181SN1D_0603

BLM18PG181SN1D_0603

1

C72

C72

2

9/27

+VCCP

D1 CH751H-40_SC76

D1 CH751H-40_SC76

+3VS

2

+1.05VM_DPLLA +1.05VM

9/27

1

1

@

@

+

+

C54

C54

C53

C53

2

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

+1.05VM_DPLLB

9/27

1

1

@

@

+

+3VS

+1.05VM_HPLL

+1.05VM_PEGPLL

2 1

+

C66

C66

C70

C70

2

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

2

2

C74

C74

C75

C75

0.1U_0402_16V4Z

0.1U_0402_16V4Z

4.7U_0805_10V4Z

4.7U_0805_10V4Z

+1.05VM_MPLL

1

1

C81

C81

C80

C80

2

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

10U_0805_6.3V6M

10U_0805_6.3V6M

+1.8V_TXLVDS +1.8V

1

1

2

2

C89

C89

1000P_0402_50V7K

1000P_0402_50V7K

0.1U_0402_16V4Z

0.1U_0402_16V4Z

10U_0805_10V4Z

10U_0805_10V4Z

1

1

C95

C95

C96

C96

2

2

+VCCP_D

R112 10_0402_5% R112 10_0402_5%

+1.5VS_QDAC

C103

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.01U_0402_16V7K

0.01U_0402_16V7K

1

1

C104

C104

C103

2

2

R94

R94

1 2

BLM18PG181SN1D_0603

BLM18PG181SN1D_0603

220U_D2_4VM_R15

220U_D2_4VM_R15

R98

R98

1 2

BLM18PG181SN1D_0603

BLM18PG181SN1D_0603

220U_D2_4VM_R15

220U_D2_4VM_R15

9/27

R102

R102

1 2

BLM18PG181SN1D_0603

BLM18PG181SN1D_0603

R105

R105

1 2

BLM18PG181SN1D_0603

BLM18PG181SN1D_0603

R108 0_0603_5% R108 0_0603_5%

1 2

C90

C90

10U_0805_6.3V6M @

10U_0805_6.3V6M @

9/27

L1

L1

1 2

BLM18PG121SN1D_0603

BLM18PG121SN1D_0603

1 2

BLM18PG181SN1D_0603

BLM18PG181SN1D_0603

4.7U_0603_6.3V

4.7U_0603_6.3V

1

C619

C619

2

9/27

1 2

9/27

+1.05VM

+1.05VM

+1.05VM

R114

R114

9/27

9/29

R113 0_0402_5% R113 0_0402_5%

+1.05VM

4.7U_0805_10V4Z

4.7U_0805_10V4Z

+1.05VM_DMI

1 2

+1.5VS

+V1.05VM_AXF

10U_0805_10V4Z

10U_0805_10V4Z

+1.8V_SM_CK

0_0603_5%

0_0603_5%

R597

R597

1 2

10U_0805_6.3V6M

10U_0805_6.3V6M

1

C67

C67

2

+1.5VS_TVDAC

C76

0.01U_0402_16V7K

0.01U_0402_16V7K

1

C76

2

+VCC_PEG

10U_0805_6.3V6M

10U_0805_6.3V6M

1

1

C88

C88

C87

C87

2

2

R109 0_0603_5% R109 0_0603_5%

0.1U_0402_16V4Z

0.1U_0402_16V4Z
C91

1

C91

2

1

R95 0_0603_5%

R95 0_0603_5%

1 2

1U_0603_10V4Z

1U_0603_10V4Z

1

C55

C55

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

C68

C68

0.1U_0402_16V4Z

0.1U_0402_16V4Z

C77

C77

220U_D2_4VM_R15

220U_D2_4VM_R15

C86

C86

1 2

1

C56

C56

2

R99 0_0805_5%

R99 0_0805_5%

1 2

10U_0805_6.3V6M

10U_0805_6.3V6M

1

1

C69

C69

2

2

R103

R103

1 2

BLM18PG181SN1D_0603

BLM18PG181SN1D_0603

1

2

R107 0_0805_5%R107 0_0805_5%

1 2

1

+

+

2

+3VS_HV

9/21

9/27

+1.05VM

+1.05VM

+1.8V

+1.5VS

9/21

+1.05VM

A A

install 4.7U for wavy issue. 7/29

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/02/13 2006/03/10

2006/02/13 2006/03/10

2006/02/13 2006/03/10

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, M/B LA-4021P

SCHEMATIC, M/B LA-4021P

SCHEMATIC, M/B LA-4021P

401554

401554

401554

11 36Wednesday, June 03, 2009

11 36Wednesday, June 03, 2009

11 36Wednesday, June 03, 2009

1

B

B

B

of

of

of