COMPAL LA-4021 Schematics

A

B

C

D

E

1 1

Compal confidential

Schematics Document

Mobile Penryn uFCPGA with Intel

2 2

Cantiga_GM+ICH9-M SFF core logic

SKYY

2008-07-29

3 3

4 4

A

B

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2006/02/13 2006/03/10

Compal Secret Data

Deciphered Date

D

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, M/B LA-4021P

401554

E

of

136Wednesday, June 03, 2009

B

A

B

C

D

E

Compal confidential

File Name : LA-4021P

Docking CONN.(Opus 1.0)

1 1

*RJ-45(LED*2) *CRT *LINE IN *LINE OUT *USB x4 *DC JACK

*Power on signal *Docked indicator signal *AC present indicator signal

2 2

Express Card 54

PCIE X1 + USB X1

page 25

WWAN Card

WWAN + PCIE X1 + USB X1

page 25

Thermal Sensor EMC2103

page 4

Fan Control

page 4

LCD conn

page 18

CRT

page 17

CRT to docking

page 34

S-Video to Docking

page 34

PCI-E BUS

10/100/1000 LAN

Intel Boaz GbE

PHY

page 24

CardBus Controller

Rico R5C833

page 27

PCI BUS

24HST1041A-3

3 3

RJ45 CONN

page 25

LED

page 19

1394 port

SD/MMC Slot

LPC BUS

RTC CKT.

page 21

TPM1.2

SLB9635TT

page 32

Power OK CKT.

page 35

Touch Pad CONN.

SKYY

Mobile Penym

LV/ULV Dual Core

uFCPGA-956 CPU - SFF

page 4,5,6,7

H_A#(3..35) H_D#(0..63)

Intel Cantiga GMS

FCBGA 1363 - SFF

page 8,9,10,11,12,13

Intel ICH9-M

WBMMAP-569 - SFF

page 20,21,22,23

SMSC KBC 1091

page 33

FSB

667/800/1066MHz 1.05V

DMI X4

Int.KBD

page 30page 30

SPI

SPI ROM

AT26DF321

page 32

DDR2 800MHz 1.8V

Dual Channel

USB2.0 Azalia

SATA0

SATA1

CK505

Clock Generator ICS9LPRS397

page 16

DDR2-SO-DIMM X 2

BANK 0, 1, 2, 3

USB x1(Docking) FingerPrinter AES2810

USBx1

USB conn x 3(For I/O) BT Conn USB x 1

USB x1(Camara)

page 18

MDC V1.5

page 30

Audio CKT

AD1984HD

2.5" SATA HDD Connector

OR

SATA ODD Connector

1.8" SATA HDD Connector

page 14,15

page 34

page 31

page 28

page 21

Accelerometer

LIS302DLTR

page 26

daughter board

TPA6043

AMP & Audio Jack

page 29

4 4

Power On/Off CKT.

page 30

DC/DC Interface CKT.

page 36

A

TrackPoint CONN.

page 30

B

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2006/02/13 2006/03/10

Compal Secret Data

Deciphered Date

D

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, M/B LA-4021P

401554

E

of

236Wednesday, June 03, 2009

B

A

Voltage Rails

State

S0

S1

S3

S5 S4/AC

S5 S4/ Battery only

S5 S4/AC & Battery don't exist

1 1

( O MEANS ON X MEANS OFF )

+B

power plane

O O O O O

X

+5VALW +3VALW +3VM +1.05VM

O O O O

X

+1.8V

O

XX X

+5VS +3VS +1.5VS +0.9V +VCCP +CPU_CORE +0.9V

OO OO

X

XX X

SMBUS Control Table

SOURCE

SMB_EC_CK1 SMB_EC_DA1

SMB_EC_CK2 SMB_EC_DA2

SMB_CK_CLK1 SMB_CK_DAT1 ICH9

LCD_CLK LCD_DAT

KB926

Cantiga

Symbol Note :

: means Digital Ground

: means Analog Ground

@ : means just reserve , no build CONN@ : means ME part. 45@ : means install after SMT.

INVERTER BATT EEPROM

X X

X XX

SERIAL

VV

XX X

X XX

THERMAL SENSOR (CPU)

SODIMM CLK CHIP

XX

V

X

VVV

XX

X X

MINI CARD

LCD

XX X

X X

X

V

I2C / SMBUS ADDRESSING

DEVICE

DDR SO-DIMM 0 CLOCK GENERATOR (EXT.)

HEX ADDRESS

A0 D2

1 0 1 0 0 0 0 0 1 1 0 1 0 0 1 0

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

2005/03/10 2006/03/10

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, M/B LA-4021P

401554

336Wednesday, June 03, 2009

of

B

5

4

3

2

1

XDP Connector

JP1

1

2

1

GND0

3

OBSFN_A0

5

OBSFN_A1

7

GND2

9

OBSDATA_A0

11

OBSDATA_A1

13

GND4

15

OBSDATA_A2

17

OBSDATA_A3

19

GND6

21

OBSFN_B0

23

OBSFN_B1

25

GND8

27

OBSDATA_B0

29

OBSDATA_B1

31

GND10

33

OBSDATA_B2

35

OBSDATA_B3

37

GND12

39

PWRGOOD/HOOK0

41

HOOK1

43

VCC_OBS_AB

45

HOOK2

47

HOOK3

49

GND14

51

SDA

53

SCL

55

TCK1

57

TCK0

59

GND16

U2

1

DN

2

DP

3

VDD

4

GPIO1

5

GPIO2

6

ALERT#

7

SYS_SHDN#

8

SMDATA

C

Q45

2

B

MMBT3904W_SOT323-3

E

3 1

Layout Note: place near the hottest spot area for

NB & top SODIMM.

OBSDATA_C0 OBSDATA_C1

OBSDATA_C2 OBSDATA_C3

OBSDATA_D0 OBSDATA_D1

OBSDATA_D2 OBSDATA_D3

ITPCLK/HOOK4

ITPCLK#/HOOK5

VCC_OBS_CD

RESET#/HOOK6

DBR#/HOOK7

SAMTE_BSH-030-01-L-D-ACONN@

Change R18 to 2.94k_1% to change initial thermal shutdown temp to 85C. 2/13

DP2/DN3 DN2/DP3

TRIP_SET

SHDN_SEL

GND

PWM

TACH

SMCLK

GND

EMC2103-2-AX_QFN16_4X4

17

XDP_BPM#5

D D

H_A#[3..16]<8>

H_ADSTB#0<8>

H_A#[17..35]<8>

C C

H_ADSTB#1<8>

H_FERR#<21>

B B

H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16

H_REQ#0<8> H_REQ#1<8> H_REQ#2<8> H_REQ#3<8> H_REQ#4<8>

H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 H_A#32 H_A#33 H_A#34 H_A#35

H_A20M#<21> H_IGNNE#<21> H_STPCLK#<21>

H_INTR<21>

H_NMI<21> H_SMI#<21>

T97PAD T97PAD T98PAD T98PAD

T99PAD T99PAD T100PAD T100PAD T101PAD T101PAD T102PAD T102PAD T103PAD T103PAD

U1A

P2

A[3]#

V4

A[4]#

W1

A[5]#

T4

A[6]#

AA1

A[7]#

AB4

A[8]#

T2

A[9]#

AC5

A[10]#

AD2

A[11]#

AD4

A[12]#

AA5

A[13]#

AE5

A[14]#

AB2

A[15]#

AC1

A[16]#

Y4

ADSTB[0]#

R1

REQ[0]#

R5

REQ[1]#

U1

REQ[2]#

P4

REQ[3]#

W5

REQ[4]#

AN1

A[17]#

AK4

A[18]#

AG1

A[19]#

AT4

A[20]#

AK2

A[21]#

AT2

A[22]#

AH2

A[23]#

AF4

A[24]#

AJ5

A[25]#

AH4

A[26]#

AM4

A[27]#

AP4

A[28]#

AR5

A[29]#

AJ1

A[30]#

AL1

A[31]#

AM2

A[32]#

AU5

A[33]#

AP2

A[34]#

AR1

A[35]#

AN5

ADSTB[1]#

C7

A20M#

D4

ICH

FERR#

F10

IGNNE#

F8

STPCLK#

C9

LINT0

C5

LINT1

E5

SMI#

V2

RSVD01

Y2

RSVD02

AG5

RSVD03

AL5

RSVD04

J9

RSVD05

F4

RSVD06

H8

RSVD07

PENRYN SFF_UFCBGA956

ADDR GROUP 0

DEFER#

CONTROL

RESET#

ADDR GROUP 1

BPM[0]# BPM[1]# BPM[2]# BPM[3]#

XDP/ITP SIGNALS

THERMAL

PROCHOT#

THERMDA THERMDC

THERMTRIP#

H CLK

BCLK[0] BCLK[1]

ADS# BNR# BPRI#

DRDY# DBSY#

BR0#

IERR#

INIT#

LOCK#

RS[0]# RS[1]# RS[2]#

TRDY#

HIT#

HITM#

PRDY# PREQ#

TCK

TDI TDO TMS

TRST#

DBR#

RESERVED

M4 J5 L5

N5 F38 J1

M2 B40

D8 N1 G5

K2 H4 K4 L1

H2 F2

AY8 BA7 BA5 AY2 AV10 AV2 AV4 AW7 AU1 AW5 AV8 J7

D38 BB34 BD34

B10

A35 C35

Place close to U1.

H_ADS# <8> H_BNR# <8>

H_BPRI# <8> H_DEFER# <8>

H_DRDY# <8> H_DBSY# <8>

H_BR0# <8>

H_INIT# <21> H_LOCK# <8>

H_RESET#

H_TRDY# <8>

H_HIT# <8> H_HITM# <8>

XDP_BPM#0 XDP_BPM#1 XDP_BPM#2 XDP_BPM#3 XDP_BPM#4 XDP_BPM#5_R XDP_TCK XDP_TDI XDP_TDO XDP_TMS XDP_TRST# XDP_DBRESET#

Place Close to U1.

H_THERMDA_R H_THERMDC_R

H_THERMTRIP#

H_THERMDA, H_THERMDC routing together, Trace width / Spacing = 10 / 10 mil

CLK_CPU_BCLK <16> CLK_CPU_BCLK# <16>

+VCCP

R609

R609 51_0402_1%

51_0402_1%

9/20

1 2

56_0402_5%

R10

H_RS#0 <8> H_RS#1 <8> H_RS#2 <8>

Add 0 ohm per EMI request. 10/17

R48

R48 0_0402_5%

0_0402_5%

1 2

XDP_DBRESET# <22>

H_PROCHOT# <42>

R20 68_0402_5%

1 2

R21 0_0402_5%R21 0_0402_5%

1 2

R22 0_0402_5%R22 0_0402_5%

1 2

+VCCP

H_THERMTRIP# <8,21>

H_RESET# <8>

XDP_BPM#5

9/14

H_THERMDA H_THERMDC

H_PWRGOOD<5,21> CLK_CPU_XDP <16>

C1 0.1U_0402_16V4ZC1 0.1U_0402_16V4Z

Thermal Sensor EMC2103-2 with CPU PWM FAN

+3VS

R15

R15 68_0402_5%

68_0402_5%

1 2

+3VS_THER

C2

1

0.1U_0402_16V4Z

2

THERM_SCI#<22>

+3VS

ICH_SM_DA<22,26>

MAINPWON<37,39>

H_THERMTRIP#

Add R641 per HP request. 3/28

R23 10K_0402_5%@R23 10K_0402_5%@

R324 0_0402_5%@R324 0_0402_5%@ R641 0_0402_5%R641 0_0402_5%

Change R23, R24 connect to +3VS and add PU/PD for U2. (9/3) NI R23, reserve R324 and connect to MAINPWON. (10/5)

XDP_BPM#4 XDP_BPM#3

XDP_BPM#2 XDP_BPM#1

XDP_BPM#0

R9

R9 1K_0402_5%

1K_0402_5%

H_PWRGOOD_R

12

XDP_HOOK1

12

XDP_TCK

Correct to Swap DN&DP. (11/26)

H_THERMDC H_THERMDA

1 2

C3 2200P_0402_50V7KC3 2200P_0402_50V7K

R24

R24 10K_0402_5%

10K_0402_5%

1 2

+3VS

1 2

1 2 1 2

REMOTE thermal sensor

REMOTE2+

C314

2200P_0402_50V7K

REMOTE2-

2

GND1

4

OBSFN_C0

6

OBSFN_C1

8

GND3

10 12 14

GND5

16 18 20

GND7

22

OBSFN_D0

24

OBSFN_D1

26

GND9

28 30 32

GND11

34 36 38

GND13

40 42 44 46 48 50

GND15

52

TD0

54

TRST#

56

TDI

58

TMS

60

GND17

REMOTE2+

16

REMOTE2-

15

R18 2.05K_0402_1%R18 2.05K_0402_1%

14

1 2

R643 10K_0402_5%@R643 10K_0402_5%@

1 2

R17 10K_0402_5%R17 10K_0402_5%

13

1 2

12

FAN_PWM

11

TACH

10 9

R13 10K_0402_5%R13 10K_0402_5%

R16 10K_0402_5%R16 10K_0402_5%

XDP_TDI XDP_TMS XDP_TDO XDP_BPM#5 XDP_HOOK1 XDP_TRST# XDP_TCK

H_RESET#_R XDP_DBRESET#

XDP_TDO XDP_TRST# XDP_TDI XDP_TMS XDP_PRE

1 2

ICH_SM_CLK <22,26>

R2 54.9_0402_1%R2 54.9_0402_1%

1 2

R3 54.9_0402_1%R3 54.9_0402_1%

1 2

R4 54.9_0402_1%R4 54.9_0402_1%

1 2

R5 54.9_0402_1%R5 54.9_0402_1%

1 2

R6 54.9_0402_1%@ R6 54.9_0402_1%@

1 2

R7 51_0402_1%

1 2

R8 54.9_0402_1%R8 54.9_0402_1%

1 2

This shall place near CPU

CLK_CPU_XDP# <16>

+VCCP+VCCP

R11 22.6_0402_1%R11 22.6_0402_1%

1 2

R14

R14 0_0402_5%

0_0402_5%

1 2

Change R17 to 10K for HW critical shutdown to internal diode temperature. 4/23

Place R191 within 200ps (~1") to CPU

+5VS

+3VS

Chnage JP2 to 4pin. 12/06

1 2 3

+VCCP

H_RESET#

JP2

4

1

4

5

2

G5

6

3

G6

ACES_85205-04001CONN@

A A

5

4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/02/13 2006/03/10

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, M/B LA-4021P

401554

1

of

436Wednesday, June 03, 2009

B

5

4

3

2

1

H_D#[0..15]<8>

D D

H_DSTBN#0<8> H_DSTBP#0<8> H_DINV#0<8> H_D#[16..31]<8>

C C

layout note: Route TEST3 & TEST5 traces on ground referenced layer to the TPs

H_DSTBN#1<8> H_DSTBP#1<8> H_DINV#1<8>

CPU_BSEL0<16> CPU_BSEL1<16> CPU_BSEL2<16>

V_CPU_GTLREF

T105T105

T3T3 T4T4

H_D#0 H_D#1

H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 H_DSTBN#0 H_DSTBP#0 H_DINV#0

H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31 H_DSTBN#1 H_DSTBP#1 H_DINV#1

TEST2

TEST5 TEST6

CPU_BSEL CPU_BSEL2 CPU_BSEL1

B B

166

200

01

0

1

U1B

F40

D[0]#

G43

D[1]#

E43

D[2]#

J43

D[3]#

H40

D[4]#

H44

D[5]#

G39

D[6]#

E41

D[7]#

L41

D[8]#

K44

D[9]#

N41

D[10]#

T40

D[11]#

M40

D[12]#

G41

D[13]#

M44

D[14]#

L43

D[15]#

K40

DSTBN[0]#

J41

DSTBP[0]#

P40

DINV[0]#

P44

D[16]#

V40

D[17]#

V44

D[18]#

AB44

D[19]#

R41

D[20]#

W41

D[21]#

N43

D[22]#

U41

D[23]#

AA41

D[24]#

AB40

D[25]#

AD40

D[26]#

AC41

D[27]#

AA43

D[28]#

Y40

D[29]#

Y44

D[30]#

T44

D[31]#

U43

DSTBN[1]#

W43

DSTBP[1]#

R43

DINV[1]#

AW43

GTLREF

E37

TEST1

D40

TEST2

C43

TEST3

AE41

TEST4

AY10

TEST5

AC43

TEST6

A37

BSEL[0]

C37

BSEL[1]

B38

BSEL[2]

PENRYN SFF_UFCBGA956

CPU_BSEL0

1

0

D[32]# D[33]# D[34]#

DATA GROUP 0

D[35]# D[36]# D[37]# D[38]# D[39]# D[40]# D[41]# D[42]# D[43]# D[44]#

DATA GROUP 2DATA GROUP 3

D[45]# D[46]#

D[47]# DSTBN[2]# DSTBP[2]#

DINV[2]#

D[48]#

D[49]#

D[50]#

D[51]#

DATA GROUP 1

D[52]#

D[53]#

D[54]#

D[55]#

D[56]#

D[57]#

D[58]#

D[59]#

D[60]#

D[61]#

D[62]#

D[63]# DSTBN[3]# DSTBP[3]#

DINV[3]# COMP[0]

MISC

COMP[1] COMP[2] COMP[3]

DPRSTP#

DPSLP#

DPWR#

PWRGOOD

SLP#

PSI#

Cause CPU core power change to 1 phase, and not need support the pin, leave it as TP. 10/02

AR43 AH40 AF40 AJ43 AG41 AF44 AH44 AM44 AN43 AM40 AK40 AG43 AP40 AN41 AL41 AK44 AL43 AJ41

AV38 AT44 AV40 AU41 AW41 AR41 BA37 BB38 AY36 AT40 BC35 BC39 BA41 BB40 BA35 AU43 AY40 AY38 BC37

AE43 AD44 AE1 AF2

G7 B8 C41 E7 D10 BD10

H_PSI#

H_D#33 H_D#34H_D#2 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 H_DSTBN#2 H_DSTBP#2 H_DINV#2

H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63 H_DSTBN#3 H_DSTBP#3 H_DINV#3

COMP0 COMP1 COMP2 COMP3

H_D#32

AP44

H_DPRSTP# <8,21,42>

H_DPSLP# <21> H_DPWR# <8> H_PWRGOOD <4,21>

H_CPUSLP# <8>

T124T124

H_D#[32..47] <8>

H_DSTBN#2 <8> H_DSTBP#2 <8> H_DINV#2 <8> H_D#[48..63] <8>

H_DSTBN#3 <8> H_DSTBP#3 <8> H_DINV#3 <8>

R34

R33

R32

R31

12

27.4_0402_1%

54.9_0402_1%

27.4_0402_1%

54.9_0402_1%

Resistor placed within

0.5" of CPU pin.Trace should be at least 25 mils away from any other toggling signal. COMP[0,2] trace width is 18 mils. COMP[1,3] trace width is 4 mils.

266 0 0 0

+VCC_CORE +VCC_CORE

U1C

F32

VCC[001]

G33

VCC[002]

H32

VCC[003]

J33

VCC[004]

K32

VCC[005]

L33

VCC[006]

M32

VCC[007]

N33

VCC[008]

P32

VCC[009]

R33

VCC[010]

T32

VCC[011]

U33

VCC[012]

V32

VCC[013]

W33

VCC[014]

Y32

VCC[015]

AA33

VCC[016]

AB32

VCC[017]

AC33

VCC[018]

AD32

VCC[019]

AE33

VCC[020]

AF32

VCC[021]

AG33

VCC[022]

AH32

VCC[023]

AJ33

VCC[024]

AK32

VCC[025]

AL33

VCC[026]

AM32

VCC[027]

AN33

VCC[028]

AP32

VCC[029]

AR33

VCC[030]

AT34

VCC[031]

AT32

VCC[032]

AU33

VCC[033]

AV32

VCC[034]

AY32

VCC[035]

BB32

VCC[036]

BD32

VCC[037]

B28

VCC[038]

B30

VCC[039]

B26

VCC[040]

D28

VCC[041]

D30

VCC[042]

F30

VCC[043]

F28

VCC[044]

H30

VCC[045]

H28

VCC[046]

D26

VCC[047]

F26

VCC[048]

H26

VCC[049]

K30

VCC[050]

K28

VCC[051]

M30

VCC[052]

M28

VCC[053]

K26

VCC[054]

M26

VCC[055]

P30

VCC[056]

P28

VCC[057]

T30

VCC[058]

T28

VCC[059]

V30

VCC[060]

V28

VCC[061]

P26

VCC[062]

T26

VCC[063]

V26

VCC[064]

Y30

VCC[065]

Y28

VCC[066]

AB30

VCC[067]

PENRYN SFF_UFCBGA956

VCC[068] VCC[069] VCC[070] VCC[071] VCC[072] VCC[073] VCC[074] VCC[075] VCC[076] VCC[077] VCC[078] VCC[079] VCC[080] VCC[081] VCC[082] VCC[083] VCC[084] VCC[085] VCC[086] VCC[087] VCC[088] VCC[089] VCC[090] VCC[091] VCC[092] VCC[093] VCC[094] VCC[095] VCC[096] VCC[097] VCC[098] VCC[099] VCC[100]

VCCP_001 VCCP_002 VCCP_003 VCCP_004 VCCP_005 VCCP_006 VCCP_007 VCCP_008 VCCP_009 VCCP_010 VCCP_011 VCCP_012 VCCP_013 VCCP_014 VCCP_015 VCCP_016

VCCA[01] VCCA[02]

VID[0] VID[1] VID[2] VID[3] VID[4] VID[5] VID[6]

VCCSENSE

VSSSENSE

AB28 AD30 AD28 Y26 AB26 AD26 AF30 AF28 AH30 AH28 AF26 AH26 AK30 AK28 AM30 AM28 AP30 AP28 AK26 AM26 AP26 AT30 AT28 AV30 AV28 AY30 AY28 AT26 AV26 AY26 BB30 BB28 BD30

R26 0_0402_5%R26 0_0402_5%

J11

1 2

R27 0_0402_5% R27 0_0402_5%

E11

1 2

R28 0_0402_5% R28 0_0402_5%

G11

1 2 J37 K38 L37 N37 P38 R37 U37 V38 W37 AA37 AB38 AC37 AE37

B34 D34

BD8 BC7 BB10 BB8 BC5 BB4 AY4

VCCSENSE

BD12

VSSSENSE

BC13

Length match within 25 mils. The trace width/space/other is 20/7/25.

+VCCP

1

+

C4

330U_D2E_2.5VM_R9

2

CPU_VID0 <42> CPU_VID1 <42> CPU_VID2 <42> CPU_VID3 <42> CPU_VID4 <42> CPU_VID5 <42> CPU_VID6 <42>

VCCSENSE <42>

VSSSENSE <42>

1

C6

2

0.01U_0402_16V7K

Near pin B34

Change to 330u_R9, casue high limitation. 12/14

+1.5VS

1

C7

2

10U_0805_6.3V6M

Near pin D34

+VCC_CORE

R36

+VCCP

12

R35

R35 1K_0402_1%

1K_0402_1%

V_CPU_GTLREF

A A

Close to CPU pin AW43 within 500mils.

5

12

R37

R37 2K_0402_1%

2K_0402_1%

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/02/13 2006/03/10

Compal Secret Data

Deciphered Date

2

1 2

100_0402_1%

100_0402_1% R38

R38

1 2

100_0402_1%

Close to CPU pin within 500mils.

Title

Size Document Number Rev

Custom

Date: Sheet

VCCSENSE

VSSSENSE

Compal Electronics, Inc.

SCHEMATIC, M/B LA-4021P

401554

1

B

of

536Wednesday, June 03, 2009

5

4

3

2

1

D D

+VCCP

AL37

AN37

AP38

B32

C33

D32

E35

E33

F34

G35

F36

H36

J35

L35

N35

K36

R35

U35

P36

V36

W35

AA35

AC35

AB36

AE35

AG35

AJ35

AF36

AL35

AN35

AK36

AP36

B12

B14

C13

D12

D14

E13

F14

F12

G13

H14

H12

J13

K14

K12

L13

L11

M14

N13

N11

K10

P14

P12

R13

R11

T14

U13

U11

V14

V12

W13

W11

P10

V10

Y14

AA13

AA11

AB14

AB12

AC13

AC11

AD14

AB10

AE13

AE11

AF14

AF12

AG13

AG11

AH14

AJ13

AJ11

AF10

AK14

AK12

AL13

AL11

AN13

AN11

AP12

AR13

AR11

AK10

AP10

AU13

VCCP_111

VCC_191

AK16

AM18

VCCP_112

VCCP_113

VCC_192

VCC_193

AM16

VCCP_114

VCC_194

AP18

AP16

VCCP_115

VCCP_116

VCC_195

VCC_196

AK20

AU11

VCCP_117

VCCP_118L9VCCP_119L7VCCP_120N9VCCP_121N7VCCP_122R9VCCP_123R7VCCP_124U9VCCP_125U7VCCP_126W9VCCP_127W7VCCP_128

VCC_197

VCC_198

VCC_199

VCC_200

AT18

AT16

AP20

AV18

AM20

C C

VCCP_021

VCCP_022

VCCP_023

VCCP_024

VCCP_025

VCCP_026

VCCP_027

VCCP_028

VCCP_029

VCCP_030

VCCP_031

VCCP_032

VCCP_033

VCCP_034

VCCP_035

VCCP_036

VCCP_037

VCCP_038

VCCP_039

VCCP_040

VCCP_041

VCCP_042

VCCP_043

VCCP_044

VCCP_045

VCCP_046

VCCP_047

VCCP_048

VCCP_049

VCCP_050

VCCP_051

VCCP_052

VCCP_053

VCCP_054

VCCP_055

VCCP_056

VCCP_057

VCCP_058

VCCP_059

VCCP_060

VCCP_061

VCCP_062

VCCP_063

VCCP_064

VCCP_065

VCCP_066

VCCP_067

VCCP_068

VCCP_069

VCCP_070

VCCP_071

VCCP_072

VCCP_073

VCCP_074

VCCP_075

VCCP_076

VCCP_077

VCCP_078

VCCP_079

VCCP_080

VCCP_081

VCCP_082

VCCP_083

VCCP_084

VCCP_085

VCCP_086

VCCP_087

VCCP_088

VCCP_089

VCCP_090

VCCP_091

VCCP_092

VCCP_093

VCCP_094

VCCP_095

VCCP_096

VCCP_097

VCCP_098

VCCP_099

VCCP_100

VCCP_101

VCCP_102

VCCP_103

VCCP_104

VCCP_105

VCCP_106

VCCP_107

VCCP_108

VCCP_109

VCCP_110

VCC_101

VCC_102

VCC_103

VCC_104

VCC_105

VCC_106

VCC_107

VCC_108

VCC_109

VCC_110

VCC_111

VCC_112

VCC_113

VCC_114

VCC_115

VCC_116

VCC_117

VCC_118

VCC_119

VCC_120

VCC_121

VCC_122

VCC_123

VCC_124

VCC_125

VCC_126

VCC_127

VCC_128

VCC_129

VCC_130

VCC_131

VCC_132

VCC_133

VCC_134

VCC_135

VCC_136

VCC_137

VCC_138

VCC_139

VCC_140

VCC_141

VCC_142

VCC_143

VCC_144

VCC_145

VCC_146

VCC_147

VCC_148

VCC_149

VCC_150

VCC_151

VCC_152

VCC_153

VCC_154

VCC_155

VCC_156

VCC_157

VCC_158

VCC_159

VCC_160

VCC_161

VCC_162

VCC_163

VCC_164

VCC_165

VCC_166

VCC_167

VCC_168

VCC_169

VCC_170

VCC_171

VCC_172

VCC_173

VCC_174

VCC_175

VCC_176

VCC_177

VCC_178

VCC_179

VCC_180

VCC_181

VCC_182

VCC_183

VCC_184

VCC_185

VCC_186

VCC_187

VCC_188

VCC_189

VCC_190

F24

F22

B22

B24

D22

D24

H24

BB26

BD28

BD26

H22

T24

K24

T22

K22

P24

P22

V24

V22

Y24

M24

M22

Y22

AF24

AF22

AB24

AB22

AD24

AD22

AH24

AH22

AT24

AK24

AT22

AK22

AP24

AP22

AV24

AV22

AY24

AY22

BB24

BB22

AM24

AM22

BD24

F18

F16

B16

B18

B20

D16

BD22

F20

K18

D18

K16

H18

H16

D20

H20

T18

T16

K20

P18

M18

M16

M20

T20

P16

V18

V16

P20

V20

Y18

Y16

Y20

AF18

AF16

AB18

AB16

AD18

AD16

AF20

AB20

AD20

AK18

AH18

AH16

AH20

VCC_201

VCC_202

AV16

VCC_203

AY18

AY16

VCC_204

VCC_205

AT20

VCC_206

VCC_207

AV20

AY20

AA9

AA7

VCC_208

BB18

BB16

AC9

VCCP_129

VCCP_130

VCC_209

VCC_210

BD18

AC7

AE9

VCCP_131

VCC_211

BB20

BD16

AE7

VCCP_132

VCCP_133

VCC_212

VCC_213

BD20

AG9

AG7

VCCP_134

VCC_214

AP14

AM14

AJ9

VCCP_135

VCCP_136

VCC_215

VCC_216

AT14

AJ7

AL9

VCCP_137

VCC_217

AV14

AY14

AL7

VCCP_138

VCCP_139

VCC_218

VCC_219

BB14

AN9

AN7

VCCP_140

VCC_220

BD14

VCCP_141

AR9

AR7

A33

VCCP_142

VCCP_143

VCCP_144

VCCP_018

VCCP_019

VCCP_017

AJ37

AF38

AG37

A13

U1F

U1F PENRYN SFF_UFCBGA956

PENRYN SFF_UFCBGA956

VCCP_145

VCCP_020

AK38

+VCC_CORE +VCCP

B B

A A

5

4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/02/13 2006/03/10

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, M/B LA-4021P

401554

1

of

636Wednesday, June 03, 2009

B

5

U1D

B42

VSS[001]

F44

VSS[002]

D44

VSS[003]

D42

VSS[004]

F42

VSS[005]

H42

VSS[006]

K42

VSS[007]

M42

VSS[008]

P42

VSS[009]

T42

VSS[010]

V42

VSS[011]

Y42

D D

C C

B B

A A

VSS[012]

AB42

VSS[013]

AD42

VSS[014]

AF42

VSS[015]

AH42

VSS[016]

AK42

VSS[017]

AM42

VSS[018]

AP42

VSS[019]

AY44

VSS[020]

AV44

VSS[021]

AT42

VSS[022]

AV42

VSS[023]

AY42

VSS[024]

BA43

VSS[025]

BB42

VSS[026]

C39

VSS[027]

E39

VSS[028]

G37

VSS[029]

H38

VSS[030]

J39

VSS[031]

L39

VSS[032]

M38

VSS[033]

N39

VSS[034]

R39

VSS[035]

T38

VSS[036]

U39

VSS[037]

W39

VSS[038]

Y38

VSS[039]

AA39

VSS[040]

AC39

VSS[041]

AD38

VSS[042]

AE39

VSS[043]

AG39

VSS[044]

AH38

VSS[045]

AJ39

VSS[046]

AL39

VSS[047]

AM38

VSS[048]

AN39

VSS[049]

AR39

VSS[050]

AR37

VSS[051]

AT38

VSS[052]

AU39

VSS[053]

AU37

VSS[054]

AW39

VSS[055]

AW37

VSS[056]

BA39

VSS[057]

BC41

VSS[058]

BD40

VSS[059]

BD38

VSS[060]

B36

VSS[061]

H34

VSS[062]

D36

VSS[063]

K34

VSS[064]

M34

VSS[065]

M36

VSS[066]

P34

VSS[067]

T34

VSS[068]

V34

VSS[069]

T36

VSS[070]

Y34

VSS[071]

AB34

VSS[072]

AD34

VSS[073]

Y36

VSS[074]

AD36

VSS[075]

AF34

VSS[076]

AH34

VSS[077]

AH36

VSS[078]

AK34

VSS[079]

AM34

VSS[080]

AP34

VSS[081]

PENRYN SFF_UFCBGA956

VSS[082] VSS[083] VSS[084] VSS[085] VSS[086] VSS[087] VSS[088] VSS[089] VSS[090] VSS[091] VSS[092] VSS[093] VSS[094] VSS[095] VSS[096] VSS[097] VSS[098] VSS[099] VSS[100] VSS[101] VSS[102] VSS[103] VSS[104] VSS[105] VSS[106] VSS[107] VSS[108] VSS[109] VSS[110] VSS[111] VSS[112] VSS[113] VSS[114] VSS[115] VSS[116] VSS[117] VSS[118] VSS[119] VSS[120] VSS[121] VSS[122] VSS[123] VSS[124] VSS[125] VSS[126] VSS[127] VSS[128] VSS[129] VSS[130] VSS[131] VSS[132] VSS[133] VSS[134] VSS[135] VSS[136] VSS[137] VSS[138] VSS[139] VSS[140] VSS[141] VSS[142] VSS[143] VSS[144] VSS[145] VSS[146] VSS[147] VSS[148] VSS[149] VSS[150] VSS[151] VSS[152] VSS[153] VSS[154] VSS[155] VSS[156] VSS[157] VSS[158] VSS[159] VSS[160] VSS[161] VSS[162] VSS[163]

AM36 AR35 AU35 AV34 AW35 AW33 AY34 AT36 AV36 BA33 BC33 BB36 BD36 C27 C29 C31 E29 E27 G29 G27 E31 G31 J29 J27 L29 L27 N29 N27 J31 L31 N31 R29 R27 U29 U27 R31 U31 W29 W27 W31 AA29 AA27 AC29 AC27 AA31 AC31 AE29 AE27 AG29 AG27 AJ29 AJ27 AE31 AG31 AJ31 AL29 AL27 AN29 AN27 AL31 AN31 AR29 AR27 AR31 AU29 AU27 AW29 AW27 AU31 AW31 BA29 BA27 BC29 BC27 BA31 BC31 C21 C23 C25 E25 E23 E21

5

U1E

G25

VSS_164

G23

VSS_165

G21

VSS_166

J25

VSS_167

J23

VSS_168

J21

VSS_169

L25

VSS_170

L23

VSS_171

L21

VSS_172

N25

VSS_173

N23

VSS_174

N21

VSS_175

R25

VSS_176

R23

VSS_177

R21

VSS_178

U25

VSS_179

U23

VSS_180

U21

VSS_181

W25

VSS_182

W23

VSS_183

W21

VSS_184

AA25

VSS_185

AA23

VSS_186

AA21

VSS_187

AC25

VSS_188

AC23

VSS_189

AC21

VSS_190

AE25

VSS_191

AE23

VSS_192

AE21

VSS_193

AG25

VSS_194

AG23

VSS_195

AG21

VSS_196

AJ25

VSS_197

AJ23

VSS_198

AJ21

VSS_199

AL25

VSS_200

AL23

VSS_201

AL21

VSS_202

AN25

VSS_203

AN23

VSS_204

AN21

VSS_205

AR25

VSS_206

AR23

VSS_207

AR21

VSS_208

AU25

VSS_209

AU23

VSS_210

AU21

VSS_211

AW25

VSS_212

AW23

VSS_213

AW21

VSS_214

BA25

VSS_215

BA23

VSS_216

BA21

VSS_217

BC25

VSS_218

BC23

VSS_219

BC21

VSS_220

C17

VSS_221

C19

VSS_222

E19

VSS_223

E17

VSS_224

G19

VSS_225

G17

VSS_226

J19

VSS_227

J17

VSS_228

L19

VSS_229

L17

VSS_230

N19

VSS_231

N17

VSS_232

R19

VSS_233

R17

VSS_234

U19

VSS_235

U17

VSS_236

W19

VSS_237

W17

VSS_238

AA19

VSS_239

AA17

VSS_240

AC19

VSS_241

AC17

VSS_242

AE19

VSS_243

AE17

VSS_244

AG19

VSS_245

AG17

VSS_246

AJ19

VSS_247

AJ17

VSS_248

AL19

VSS_249

AL17

VSS_250

AN19

VSS_251

AN17

VSS_252

AR19

VSS_253

AR17

VSS_254

AU19

VSS_255

AU17

VSS_256

AW19

VSS_257

AW17

VSS_258

BA19

VSS_259

BA17

VSS_260

BC19

VSS_261

BC17

VSS_262

C11

VSS_263

C15

VSS_264

E15

VSS_265

G15

VSS_266

H10

VSS_267

M12

VSS_268

J15

VSS_269

L15

VSS_270

N15

VSS_271

M10

VSS_272

T12

VSS_273

R15

VSS_274

U15

VSS_275

W15

VSS_276

T10

VSS_277

Y12

VSS_278

AD12

VSS_279

PENRYN SFF_UFCBGA956

VSS_280 VSS_281 VSS_282 VSS_283 VSS_284 VSS_285 VSS_286 VSS_287 VSS_288 VSS_289 VSS_290 VSS_291 VSS_292 VSS_293 VSS_294 VSS_295 VSS_296 VSS_297 VSS_298 VSS_299 VSS_300 VSS_301 VSS_302 VSS_303 VSS_304 VSS_305 VSS_306 VSS_307 VSS_308 VSS_309 VSS_310 VSS_311 VSS_312 VSS_313 VSS_314 VSS_315 VSS_316 VSS_317 VSS_318 VSS_319 VSS_320 VSS_321 VSS_322 VSS_323 VSS_324 VSS_325 VSS_326 VSS_327 VSS_328 VSS_329 VSS_330 VSS_331 VSS_332 VSS_333 VSS_334 VSS_335 VSS_336 VSS_337 VSS_338 VSS_339 VSS_340 VSS_341 VSS_342 VSS_343 VSS_344 VSS_345 VSS_346 VSS_347 VSS_348 VSS_349 VSS_350 VSS_351 VSS_352 VSS_353 VSS_354 VSS_355 VSS_356 VSS_357 VSS_358 VSS_359 VSS_360 VSS_361 VSS_362 VSS_363 VSS_364 VSS_365 VSS_366 VSS_367 VSS_368 VSS_369 VSS_370 VSS_371 VSS_372 VSS_373 VSS_374 VSS_375 VSS_376 VSS_377 VSS_378 VSS_379 VSS_380 VSS_381 VSS_382 VSS_383 VSS_384 VSS_385 VSS_386 VSS_387 VSS_388 VSS_389 VSS_390 VSS_391 VSS_392 VSS_393 VSS_394 VSS_395

AA15 AC15 Y10 AD10 AH12 AE15 AG15 AJ15 AH10 AM12 AL15 AN15 AR15 AM10 AT12 AV12 AW13 AW11 AY12 AU15 AW15 AT10 BA13 BA11 BB12 BC11 BA15 BC15 B6 D6 E9 F6 G9 H6 K8 K6 M8 M6 P8 P6 T8 T6 V8 V6 U5 Y8 Y6 AB8 AB6 AD8 AD6 AF8 AF6 AH8 AH6 AK8 AK6 AM8 AM6 AP8 AP6 AT8 AT6 AU9 AV6 AU7 AW9 AY6 BA9 BB6 BC9 BD6 B4 C3 E3 G3 J3 L3 N3 R3 U3 W3 AA3 AC3 AE3 AG3 AJ3 AL3 AN3 AR3 AU3 AW3 BA3 BC3 D2 E1 G1 AW1 BA1 BB2 A41 A39 A29 A27 A31 A25 A23 A21 A19 A17 A11 A15 A7 A5 A9 BD4

4

+VCC_CORE

10U_0805_6.3V6MC810U_0805_6.3V6M

1

C8

2

+VCC_CORE

1U_0402_6.3V6K

1

C620

2

Mid Frequence Decoupling

10U_0805_6.3V6MC910U_0805_6.3V6M

10U_0805_6.3V6M

1

C9

C10

2

1U_0402_6.3V6K

1

C622

C621

2

3

10U_0805_6.3V6M

1

C16

C17

2

High Frequence Decoupling

1U_0402_6.3V6K

1

C623

C624

2

10U_0805_6.3V6M

1

C18

C21

2

1

2

C21

2

1U_0402_6.3V6K

1

C625

C626

2

10U_0805_6.3V6M

1

2

1

2

1

C22

C23

2

1U_0402_6.3V6K

1

C628

C627

2

10U_0805_6.3V6M

C29

1U_0402_6.3V6K

C629

10U_0805_6.3V6M

1

C30

C31

2

1U_0402_6.3V6K

1

2

C630

C631

2

10U_0805_6.3V6M

1

C11

2

1U_0402_6.3V6K

1

C632

2

10U_0805_6.3V6M

1

C12

C13

2

1U_0402_6.3V6K

1

C634

C633

2

10U_0603_6.3V6M

10U_0805_6.3V6M

1

C14

2

1U_0402_6.3V6K

1

C635

2

10U_0603_6.3V6M

1

C15

C19

2

1U_0402_6.3V6K

1

C636

C637

2

10U_0603_6.3V6M

1

2

1

2

1

C24

C20

2

1U_0402_6.3V6K

1

C639

C638

2

1

10U_0603_6.3V6M

1

C26

C25

2

1U_0402_6.3V6K

1

C641

C640

2

10U_0603_6.3V6M

1

2

1

2

1

C28

C27

2

1U_0402_6.3V6K

1

C642

C643

2

6/14 :Replace 12pcs 10uF_0805 to 24 pcs 1uF_0402 for CPU transient fail issue.

ESR <= 1.5m ohm

Near CPU CORE regulator

+VCC_CORE

220U_D2_2VK_R9

1

+

C34

2

Del C37 to improve power plan. 6/14

+VCCP

1U_0603_10V4Z

C38

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/02/13 2006/03/10

1U_0603_10V4Z

1

C40

C39

2

1U_0603_10V4Z

1

2

Compal Secret Data

1

C42

C41

2

Deciphered Date

220U_D2_2VK_R9

1

+

C35

2

1U_0603_10V4Z

C43

220U_D2_2VK_R9

1

+

C36

2

1U_0603_10V4Z

1

C552

2

1U_0603_10V4Z

1

C553

C554

2

C554

2

1U_0603_10V4Z

1

C555

2

1U_0603_10V4Z

1

2

C557

C556

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, M/B LA-4021P

401554

1

B

of

736Wednesday, June 03, 2009

5

U4A

H_D#[0..63]<5>

D D

C C

H_RESET#<4>

H_CPUSLP#<5>

B B

H_VREF

1

C51

2

0.1U_0402_16V4Z

@

Trace < = 500mils

layout note: Route H_SCOMP and H_SCOMP# with trace width,

spacing and impedance (55 ohm) same as FSB data traces

Layout Note: H_RCOMP / H_VREF / H_SWNG

trace width and spacing is 10/20

+VCCP

12

R53

1K_0402_1%

12

A A

R592K_0402_1% R592K_0402_1%

within 100 mils from NB

H_SWNG H_RCOMP

H_VREF

24.9_0402_1%

5

H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31 H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63

H_RCOMP

12

R60

U4A

J7

H_D#_0

H6

H_D#_1

L11

H_D#_2

J3

H_D#_3

H4

H_D#_4

G3

H_D#_5

K10

H_D#_6

K12

H_D#_7

L1

H_D#_8

M10

H_D#_9

M6

H_D#_10

N11

H_D#_11

L7

H_D#_12

K6

H_D#_13

M4

H_D#_14

K4

H_D#_15

P6

H_D#_16

W9

H_D#_17

V6

H_D#_18

V2

H_D#_19

P10

H_D#_20

W7

H_D#_21

N9

H_D#_22

P4

H_D#_23

U9

H_D#_24

V4

H_D#_25

U1

H_D#_26

W3

H_D#_27

V10

H_D#_28

U7

H_D#_29

W11

H_D#_30

U11

H_D#_31

AC11

H_D#_32

AC9

H_D#_33

Y4

H_D#_34

Y10

H_D#_35

AB6

H_D#_36

AA9

H_D#_37

AB10

H_D#_38

AA1

H_D#_39

AC3

H_D#_40

AC7

H_D#_41

AD12

H_D#_42

AB4

H_D#_43

Y6

H_D#_44

AD10

H_D#_45

AA11

H_D#_46

AB2

H_D#_47

AD4

H_D#_48

AE7

H_D#_49

AD2

H_D#_50

AD6

H_D#_51

AE3

H_D#_52

AG9

H_D#_53

AG7

H_D#_54

AE11

H_D#_55

AK6

H_D#_56

AF6

H_D#_57

AJ9

H_D#_58

AH6

H_D#_59

AF12

H_D#_60

AH4

H_D#_61

AJ7

H_D#_62

AE9

H_D#_63

B6

H_SWING

D4

H_RCOMP

J11

H_CPURST#

G9

H_CPUSLP#

L17

H_AVREF

K18

H_DVREF

CANTIGA GMCH SFF_FCBGA1363

+VCCP

12

R54

221_0603_1%

12

R61

100_0402_1%

R61

H_SWNG

1

C52

2

0.1U_0402_16V4Z

Near B6 pin

H_ADSTB#_0 H_ADSTB#_1

H_BREQ#

H_DEFER#

HOST

HPLL_CLK

HPLL_CLK#

H_DPWR#

H_DRDY#

H_DINV#_0 H_DINV#_1 H_DINV#_2 H_DINV#_3

H_DSTBN#_0 H_DSTBN#_1 H_DSTBN#_2 H_DSTBN#_3

H_DSTBP#_0 H_DSTBP#_1 H_DSTBP#_2 H_DSTBP#_3

H_REQ#_0 H_REQ#_1 H_REQ#_2 H_REQ#_3 H_REQ#_4

layout note: Place them close to U4 pin BC51.

Layout Note: V_DDR_MCH_REF trace width and spacing is 20/20.

H_A#_3 H_A#_4 H_A#_5 H_A#_6 H_A#_7 H_A#_8

H_A#_9 H_A#_10 H_A#_11 H_A#_12 H_A#_13 H_A#_14 H_A#_15 H_A#_16 H_A#_17 H_A#_18 H_A#_19 H_A#_20 H_A#_21 H_A#_22 H_A#_23 H_A#_24 H_A#_25 H_A#_26 H_A#_27 H_A#_28 H_A#_29 H_A#_30 H_A#_31 H_A#_32 H_A#_33 H_A#_34 H_A#_35

H_ADS#

H_BNR# H_BPRI#

H_DBSY#

H_HIT# H_HITM#

H_LOCK# H_TRDY#

H_RS#_0 H_RS#_1 H_RS#_2

PM_EXTTS#0 PM_EXTTS#1

4

H_A#3

L15

H_A#4

B14

H_A#5

C15

H_A#6

D12

H_A#7

F14

H_A#8

G17

H_A#9

B12

H_A#10

J15

H_A#11

D16

H_A#12

C17

H_A#13

D14

H_A#14

K16

H_A#15

F16

H_A#16

B16

H_A#17

C21

H_A#18

D18

H_A#19

J19

H_A#20

J21

H_A#21

B18

H_A#22

D22

H_A#23

G19

H_A#24

J17

H_A#25

L21

H_A#26

L19

H_A#27

G21

H_A#28

D20

H_A#29

K22

H_A#30

F18

H_A#31

K20

H_A#32

F20

H_A#33

F22

H_A#34

B20

H_A#35

A19 F10

A15 C19 C9 B8 C11 E5 D6 AH10 AJ11 G11 H2 C7 F8 A11 D8

L9 N7 AA7 AG3

K2 N3 AA3 AF4

L3 M2 Y2 AF2

J13 L13 C13 G13 G15

F4 F2 G7

V_DDR_MCH_REF<14,15>

R46 10K_0402_5%

R46 10K_0402_5% R47 10K_0402_5%R47 10K_0402_5%

Del R48. 9/27

4

V_DDR_MCH_REF

1 2 1 2

H_A#[3..35] <4>

Add them for Boundary Scan. 10/23

H_ADS# <4> H_ADSTB#0 <4> H_ADSTB#1 <4> H_BNR# <4> H_BPRI# <4> H_BR0# <4> H_DEFER# <4> H_DBSY# <4> CLK_MCH_BCLK <16> CLK_MCH_BCLK# <16> H_DPWR# <5> H_DRDY# <4> H_HIT# <4> H_HITM# <4> H_LOCK# <4> H_TRDY# <4>

H_DINV#0 <5> H_DINV#1 <5> H_DINV#2 <5> H_DINV#3 <5>

H_DSTBN#0 <5> H_DSTBN#1 <5> H_DSTBN#2 <5> H_DSTBN#3 <5>

H_DSTBP#0 <5> H_DSTBP#1 <5> H_DSTBP#2 <5> H_DSTBP#3 <5>

H_REQ#0 <4> H_REQ#1 <4> H_REQ#2 <4> H_REQ#3 <4> H_REQ#4 <4>

H_RS#0 <4> H_RS#1 <4> H_RS#2 <4>

H_THERMTRIP#<4,21>

PM_DPRSLPVR<22,42>

C50

1

2

0.1U_0402_16V4Z

+3VS

3

T5T5 T6T6 T7T7 T8T8 T9T9 T10T10 T11T11 T12T12 T13T13

R251

+3VS

SMRCOMP_VOH

SMRCOMP_VOL

R251

1 2

R281

1 2

R311 4.7K_0402_5%@R311 4.7K_0402_5%@

1 2

R619 1K_0402_5% @R619 1K_0402_5% @

1 2

2.2U_0603_6.3V4Z

PM_BMBUSY#<22>

H_DPRSTP#<5,21,42> PM_EXTTS#0<14> PM_EXTTS#1<15> PM_PWROK<22,33,42,43> PLT_RST#<20,26,32>

1 2

R49 0_0402_5%R49 0_0402_5%

1K_0402_5% @

4.7K_0402_5%@

+1.8V

1

C45

0.01U_0402_25V7K

2

1

C47

2

0.01U_0402_25V7K

MCH_CLKSEL0<16> MCH_CLKSEL1<16> MCH_CLKSEL2<16>

12

R327 0_0402_5%R327 0_0402_5% R428 100_0402_1% R428 100_0402_1%

C44

2

1

C46

2

Add R428 in 9/26

+1.8V

12

R52

R52 10K_0402_1%

10K_0402_1%

12

R55

R55 10K_0402_1%

10K_0402_1%

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

TCK TDI TDO TMS

T18T18 T19T19

T20T20

T21T21

T22T22 T23T23 T24T24

R39

R39 1K_0402_1%

1K_0402_1%

R40

3.01K_0402_1%

R41

R41 1K_0402_1%

1K_0402_1%

T27T27

T28T28 CFG5<10> CFG6<10> CFG7<10>

T88T88 CFG9<10>

CFG10<10>

T89T89

CFG12<10> CFG13<10>

T90T90

T91T91

CFG16<10>

T92T92

T93T93

CFG19<10> CFG20<10>

PM_EXTTS#0 PM_EXTTS#1

1 2 1 2

2006/02/13 2006/03/10

T25T25

C480.1U_0402_16V4Z @ C480.1U_0402_16V4Z @

1

2

U4B

J43

RSVD1

L43

RSVD2

J41

RSVD3

L41

RSVD4

AN11

RSVD5

AM10

RSVD6

AK10

RSVD7

AL11

RSVD8

F12

RSVD9

AN45

RSVD10

AP44

RSVD11

AT44

RSVD12

AN47

RSVD13

C27

RSVD14

D30

RSVD15

J9

RSVD17

AW42

RSVD20

BB20

RSVD22

BE19

RSVD23

BF20

RSVD24

BF18

RSVD25

K26

CFG_0

G23

CFG_1

G25

CFG_2

J25

CFG_3

L25

CFG_4

L27

CFG_5

F24

CFG_6

D24

CFG_7

D26

CFG_8

J23

CFG_9

B26

CFG_10

A23

CFG_11

C23

CFG_12

B24

CFG_13

B22

CFG_14

K24

CFG_15

C25

CFG_16

L23

CFG_17

L33

CFG_18

K32

CFG_19

K34

CFG_20

J35

PM_SYNC#

F6

PM_DPRSTP#

J39

PM_EXT_TS#_0

L39

PM_EXT_TS#_1

AY39

PWROK

BB18

RSTIN#

K28

THERMTRIP#

K36

DPRSLPVR

A7

NC_1

A49

NC_2

A52

NC_3

A54

NC_4

B54

NC_5

D55

NC_6

G55

NC_7

BE55

NC_8

BH55

NC_9

BK55

NC_10

BK54

NC_11

BL54

NC_12

BL52

NC_13

BL49

NC_14

BL7

NC_15

BL4

NC_16

BL2

NC_17

BK2

NC_18

BK1

NC_19

BH1

NC_20

BE1

NC_21

G1

NC_22

Compal Secret Data

CANTIGA GMCH SFF_FCBGA1363

Deciphered Date

CFGRSVD

PM

NC

2

BB32

SA_CK_0

BA25

SA_CK_1

BA33

SB_CK_0

BA23

SB_CK_1

BA31

SA_CK#_0

BC25

SA_CK#_1

BC33

SB_CK#_0

BB24

SB_CK#_1

BC35

SA_CKE_0

BE33

SA_CKE_1

BE37

SB_CKE_0

BC37

SB_CKE_1

BK18

SA_CS#_0

BK16

SA_CS#_1

BE23

SB_CS#_0

BC19

SB_CS#_1

BJ17

SA_ODT_0

BJ19

SA_ODT_1

BC17

SB_ODT_0

BE17

SB_ODT_1

SM_RCOMP

SM_RCOMP#

SM_RCOMP_VOH

SM_RCOMP_VOL

SM_VREF

SM_PWROK

SM_REXT

SM_DRAMRST# DPLL_REF_CLK

DPLL_REF_CLK#

DDR CLK/ CONTROL/COMPENSATION

DPLL_REF_SSCLK

DPLL_REF_SSCLK#

PEG_CLK

PEG_CLK#

CLK

DMI_RXN_0 DMI_RXN_1 DMI_RXN_2 DMI_RXN_3

DMI_RXP_0 DMI_RXP_1 DMI_RXP_2 DMI_RXP_3

DMI_TXN_0 DMI_TXN_1 DMI_TXN_2 DMI_TXN_3

DMI_TXP_0 DMI_TXP_1

DMI

DMI_TXP_2 DMI_TXP_3

GFX_VID_0 GFX_VID_1 GFX_VID_2 GFX_VID_3 GFX_VID_4

GFX_VR_EN

GRAPHICS VID

CL_CLK

CL_DATA

CL_PWROK

CL_RST# CL_VREF

ME

DDPC_CTRLCLK

DDPC_CTRLDATA

SDVO_CTRLCLK

SDVO_CTRLDATA

CLKREQ#

ICH_SYNC#

MISC

TSATN#

HDA_BCLK

HDA_RST#

HDA_SDI

HDA_SDO

HDA_SYNC

HDA

2

SMRCOMP

BL25

SMRCOMP#

BK26

SMRCOMP_VOH

BK32

SMRCOMP_VOL

BL31

V_DDR_MCH_REF

BC51

SM_PWROK

AY37

SM_REXT

BH20

TP_SM_DRAMRST#

BA37 B42

D42 B50 D50

R49 P50

AG55 AL49 AH54 AL47

AG53 AK50 AH52 AL45

AG49 AJ49 AJ47 AG47

AF50 AH50 AJ45 AG45

G33 G37 F38 F36 G35

G39

AK52 AK54 AW40 AL53

CL_VREF

AL55

F34 F32 B38 A37 C31 K42

TSATN#

D10

C29 B30 D28 A27 B28

R616 54.9_0402_1%R616 54.9_0402_1%

Romoved, cause don't need HDMI. 7/19

Title

SCHEMATIC, M/B LA-4021P

Size Document Number Rev

Custom

401554

Date: Sheet

M_CLK_DDR0 <14> M_CLK_DDR1 <14> M_CLK_DDR2 <15> M_CLK_DDR3 <15>

M_CLK_DDR#0 <14> M_CLK_DDR#1 <14> M_CLK_DDR#2 <15> M_CLK_DDR#3 <15>

DDR_CKE0_DIMMA <14> DDR_CKE1_DIMMA <14> DDR_CKE2_DIMMB <15> DDR_CKE3_DIMMB <15>

DDR_CS0_DIMMA# <14> DDR_CS1_DIMMA# <14> DDR_CS2_DIMMB# <15> DDR_CS3_DIMMB# <15>

M_ODT0 <14> M_ODT1 <14> M_ODT2 <15> M_ODT3 <15>

R42 80.6_0402_1%

1 2

R43 80.6_0402_1%R43 80.6_0402_1%

1 2

R44 10K_0402_1%

1 2

R45 499_0402_1%R45 499_0402_1%

1 2

T26 PADT26 PAD

CLK_MCH_DREFCLK <16> CLK_MCH_DREFCLK# <16> MCH_SSCDREFCLK <16> MCH_SSCDREFCLK# <16>

CLK_MCH_3GPLL <16> CLK_MCH_3GPLL# <16>

DMI_TXN0 <22> DMI_TXN1 <22> DMI_TXN2 <22> DMI_TXN3 <22>

DMI_TXP0 <22> DMI_TXP1 <22> DMI_TXP2 <22> DMI_TXP3 <22>

DMI_RXN0 <22> DMI_RXN1 <22> DMI_RXN2 <22> DMI_RXN3 <22>

DMI_RXP0 <22> DMI_RXP1 <22> DMI_RXP2 <22> DMI_RXP3 <22>

DFGT_VID_0 <43> DFGT_VID_1 <43> DFGT_VID_2 <43> DFGT_VID_3 <43> DFGT_VID_4 <43>

GFXVR_EN <43>

CL_CLK0 <22> CL_DATA0 <22> M_PWROK <22,35> CL_RST# <22>

T29T29

0.1U_0402_16V4Z

T30T30 T31T31 T32T32

CLKREQ#_B <16> MCH_ICH_SYNC# <22>

1 2

Compal Electronics, Inc.

1

Modify in 9/26

+1.05VM

1

C49

2

+VCCP

836Wednesday, June 03, 2009

1

+1.8V

12

R50

R50 1K_0402_1%

1K_0402_1%

12

R51

R51 511_0402_1%

511_0402_1%

of

B

5

4

3

2

1

D D

DDR_A_D[0..63]<14>

C C

B B

DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15 DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63

U4D

AP46

SA_DQ_0

AU47

SA_DQ_1

AT46

SA_DQ_2

AU49

SA_DQ_3

AR45

SA_DQ_4

AN49

SA_DQ_5

AV50

SA_DQ_6

AP50

SA_DQ_7

AW47

SA_DQ_8

BD50

SA_DQ_9

AW49

SA_DQ_10

BA49

SA_DQ_11

BC49

SA_DQ_12

AV46

SA_DQ_13

BA47

SA_DQ_14

AY50

SA_DQ_15

BF46

SA_DQ_16

BC47

SA_DQ_17

BF50

SA_DQ_18

BF48

SA_DQ_19

BC43

SA_DQ_20

BE49

SA_DQ_21

BA43

SA_DQ_22

BE47

SA_DQ_23

BF42

SA_DQ_24

BC39

SA_DQ_25

BF44

SA_DQ_26

BF40

SA_DQ_27

BB40

SA_DQ_28

BE43

SA_DQ_29

BF38

SA_DQ_30

BE41

SA_DQ_31

BA15

SA_DQ_32

BE11

SA_DQ_33

BE15

SA_DQ_34

BF14

SA_DQ_35

BB14

SA_DQ_36

BC15

SA_DQ_37

BE13

SA_DQ_38

BF16

SA_DQ_39

BF10

SA_DQ_40

BC11

SA_DQ_41

BF8

SA_DQ_42

BG7

SA_DQ_43

BC7

SA_DQ_44

BC9

SA_DQ_45

BD6

SA_DQ_46

BF12

SA_DQ_47

AV6

SA_DQ_48

BB6

SA_DQ_49

AW7

SA_DQ_50

AY6

SA_DQ_51

AT10

SA_DQ_52

AW11

SA_DQ_53

AU11

SA_DQ_54

AW9

SA_DQ_55

AR11

SA_DQ_56

AT6

SA_DQ_57

AP6

SA_DQ_58

AL7

SA_DQ_59

AR7

SA_DQ_60

AT12

SA_DQ_61

AM6

SA_DQ_62

AU7

SA_DQ_63

CANTIGA GMCH SFF_FCBGA1363

BC21

SA_BS_0

BJ21

SA_BS_1

BJ41

SA_BS_2

BH22

SA_RAS#

BK20

SA_CAS#

BL15

SA_WE#

DDR_A_DM0

AT50

SA_DM_0 SA_DM_1 SA_DM_2 SA_DM_3 SA_DM_4 SA_DM_5 SA_DM_6 SA_DM_7

SA_DQS_0 SA_DQS_1 SA_DQS_2 SA_DQS_3 SA_DQS_4 SA_DQS_5 SA_DQS_6

SA_DQS_7 SA_DQS#_0 SA_DQS#_1 SA_DQS#_2 SA_DQS#_3 SA_DQS#_4 SA_DQS#_5 SA_DQS#_6 SA_DQS#_7

SA_MA_0 SA_MA_1 SA_MA_2 SA_MA_3 SA_MA_4 SA_MA_5 SA_MA_6 SA_MA_7 SA_MA_8

SA_MA_9 SA_MA_10 SA_MA_11 SA_MA_12

DDR SYSTEM MEMORY A

SA_MA_13 SA_MA_14

BB50 BB46 BE39 BB12 BE7 AV10 AR9

AR47 BA45 BE45 BC41 BC13 BB10 BA7 AN7 AR49 AW45 BC45 BA41 BA13 BA11 BA9 AN9

BC23 BF22 BE31 BC31 BH26 BJ35 BB34 BH32 BB26 BF32 BA21 BG25 BH34 BH18 BE25

DDR_A_DM1 DDR_A_DM2 DDR_A_DM3 DDR_A_DM4 DDR_A_DM5 DDR_A_DM6 DDR_A_DM7

DDR_A_DQS0 DDR_A_DQS1 DDR_A_DQS2 DDR_A_DQS3 DDR_A_DQS4 DDR_A_DQS5 DDR_A_DQS6 DDR_A_DQS7 DDR_A_DQS#0 DDR_A_DQS#1 DDR_A_DQS#2 DDR_A_DQS#3 DDR_A_DQS#4 DDR_A_DQS#5 DDR_A_DQS#6 DDR_A_DQS#7

DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 DDR_A_MA14

DDR_A_BS0 <14> DDR_A_BS1 <14> DDR_A_BS2 <14>

DDR_A_RAS# <14> DDR_A_CAS# <14>

DDR_A_WE# <14>

DDR_A_DM[0..7] <14>

DDR_A_DQS[0..7] <14>

DDR_A_DQS#[0..7] <14>

DDR_A_MA[0..14] <14>

DDR_B_D[0..63]<15>

DDR_B_D0 DDR_B_D1 DDR_B_D2 DDR_B_D3 DDR_B_D4 DDR_B_D5 DDR_B_D6 DDR_B_D7 DDR_B_D8

DDR_B_D9 DDR_B_D10 DDR_B_D11 DDR_B_D12 DDR_B_D13 DDR_B_D14 DDR_B_D15 DDR_B_D16 DDR_B_D17 DDR_B_D18 DDR_B_D19 DDR_B_D20 DDR_B_D21 DDR_B_D22 DDR_B_D23 DDR_B_D24 DDR_B_D25 DDR_B_D26 DDR_B_D27 DDR_B_D28 DDR_B_D29 DDR_B_D30 DDR_B_D31 DDR_B_D32 DDR_B_D33 DDR_B_D34 DDR_B_D35 DDR_B_D36 DDR_B_D37 DDR_B_D38 DDR_B_D39 DDR_B_D40 DDR_B_D41 DDR_B_D42 DDR_B_D43 DDR_B_D44 DDR_B_D45 DDR_B_D46 DDR_B_D47 DDR_B_D48 DDR_B_D49 DDR_B_D50 DDR_B_D51 DDR_B_D52 DDR_B_D53 DDR_B_D54 DDR_B_D55 DDR_B_D56 DDR_B_D57 DDR_B_D58 DDR_B_D59 DDR_B_D60 DDR_B_D61 DDR_B_D62 DDR_B_D63

U4E

AP54

SB_DQ_0

AM52

SB_DQ_1

AR55

SB_DQ_2

AV54

SB_DQ_3

AM54

SB_DQ_4

AN53

SB_DQ_5

AT52

SB_DQ_6

AU53

SB_DQ_7

AW53

SB_DQ_8

AY52

SB_DQ_9

BB52

SB_DQ_10

BC53

SB_DQ_11

AV52

SB_DQ_12

AW55

SB_DQ_13

BD52

SB_DQ_14

BC55

SB_DQ_15

BF54

SB_DQ_16

BE51

SB_DQ_17

BH48

SB_DQ_18

BK48

SB_DQ_19

BE53

SB_DQ_20

BH52

SB_DQ_21

BK46

SB_DQ_22

BJ47

SB_DQ_23

BL45

SB_DQ_24

BJ45

SB_DQ_25

BL41

SB_DQ_26

BH44

SB_DQ_27

BH46

SB_DQ_28

BK44

SB_DQ_29

BK40

SB_DQ_30

BJ39

SB_DQ_31

BK10

SB_DQ_32

BH10

SB_DQ_33

BK6

SB_DQ_34

BH6

SB_DQ_35

BJ9

SB_DQ_36

BL11

SB_DQ_37

BG5

SB_DQ_38

BJ5

SB_DQ_39

BG3

SB_DQ_40

BF4

SB_DQ_41

BD4

SB_DQ_42

BA3

SB_DQ_43

BE5

SB_DQ_44

BF2

SB_DQ_45

BB4

SB_DQ_46

AY4

SB_DQ_47

BA1

SB_DQ_48

AP2

SB_DQ_49

AU1

SB_DQ_50

AT2

SB_DQ_51

AT4

SB_DQ_52

AV4

SB_DQ_53

AU3

SB_DQ_54

AR3

SB_DQ_55

AN1

SB_DQ_56

AP4

SB_DQ_57

AL3

SB_DQ_58

AJ1

SB_DQ_59

AK4

SB_DQ_60

AM4

SB_DQ_61

AH2

SB_DQ_62

AK2

SB_DQ_63

CANTIGA GMCH SFF_FCBGA1363

BJ13

SB_BS_0

BK12

SB_BS_1

BK38

SB_BS_2

BE21

SB_RAS#

BH14

SB_CAS#

BK14

SB_WE#

DDR_B_DM0

AP52

SB_DM_0 SB_DM_1 SB_DM_2 SB_DM_3 SB_DM_4 SB_DM_5 SB_DM_6 SB_DM_7

SB_DQS_0 SB_DQS_1 SB_DQS_2 SB_DQS_3 SB_DQS_4 SB_DQS_5 SB_DQS_6

SB_DQS_7 SB_DQS#_0 SB_DQS#_1 SB_DQS#_2 SB_DQS#_3 SB_DQS#_4 SB_DQS#_5 SB_DQS#_6 SB_DQS#_7

SB_MA_0 SB_MA_1 SB_MA_2 SB_MA_3 SB_MA_4 SB_MA_5 SB_MA_6 SB_MA_7 SB_MA_8

SB_MA_9 SB_MA_10 SB_MA_11 SB_MA_12 SB_MA_13 SB_MA_14

DDR SYSTEM MEMORY B

AY54 BJ49 BJ43 BH12 BD2 AY2 AJ3

AR53 BA53 BH50 BK42 BH8 BB2 AV2 AM2 AT54 BB54 BJ51 BH42 BK8 BC3 AW3 AN3

BJ15 BJ33 BH24 BA17 BF36 BH36 BF34 BK34 BJ37 BH40 BH16 BK36 BH38 BJ11 BL37

DDR_B_DM1 DDR_B_DM2 DDR_B_DM3 DDR_B_DM4 DDR_B_DM5 DDR_B_DM6 DDR_B_DM7

DDR_B_DQS0 DDR_B_DQS1 DDR_B_DQS2 DDR_B_DQS3 DDR_B_DQS4 DDR_B_DQS5 DDR_B_DQS6

DDR_B_DQS7 DDR_B_DQS#0 DDR_B_DQS#1 DDR_B_DQS#2 DDR_B_DQS#3 DDR_B_DQS#4 DDR_B_DQS#5 DDR_B_DQS#6 DDR_B_DQS#7

DDR_B_MA0 DDR_B_MA1 DDR_B_MA2 DDR_B_MA3 DDR_B_MA4 DDR_B_MA5 DDR_B_MA6 DDR_B_MA7 DDR_B_MA8

DDR_B_MA9 DDR_B_MA10 DDR_B_MA11 DDR_B_MA12 DDR_B_MA13 DDR_B_MA14

DDR_B_BS0 <15> DDR_B_BS1 <15> DDR_B_BS2 <15>

DDR_B_RAS# <15> DDR_B_CAS# <15> DDR_B_WE# <15>

DDR_B_DM[0..7] <15>

DDR_B_DQS[0..7] <15>

DDR_B_DQS#[0..7] <15>

DDR_B_MA[0..14] <15>

A A

5

4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/02/13 2006/03/10

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, M/B LA-4021P

401554

936Wednesday, June 03, 2009

1

of

B

5

BLON_PWM<18> ENABLT<18>

D D

+3VS

DDC2_CLK<18> DDC2_DATA<18>

ENAVDD<18>

TXCLK_L-<18> TXCLK_L+<18>

TXOUT_L0-<18> TXOUT_L1-<18> TXOUT_L2-<18>

TXOUT_L0+<18> TXOUT_L1+<18> TXOUT_L2+<18>

For make layout clearance, del TP for channel B. 10/18

R65 10K_0402_5%

1 2

R66 10K_0402_5%

1 2

R67 4.22K_0402_1%

1 2

T33T33

For EMI. 9/26

R572 75_0402_5%@R572 75_0402_5%@

1 2

R336 75_0402_5%@R336 75_0402_5%@

C C

1 2

R337 75_0402_5%@R337 75_0402_5%@

1 2

Del TV_LUMA & CRMA in 10/12.

D_BLUE<17>

D_GREEN<17>

D_RED<17>

CRT_DDC_CLK<17>

CRT_DDC_DATA<17>

CRT_HSYNC<17> CRT_VSYNC<17>

B B

R70 30.1_0402_1%

1 2

R72 30.1_0402_1%

1 2

Close to pin D32 and keep 30mil space to other part/trace.

4

10/18

10/19

10/18

Tie to GND. 9/28

D_BLUE D_GREEN D_RED

CRT_HSYNC_R CRT_VSYNC_R

R74

1.02K_0402_1%

1 2

U4C

D38

L_BKLT_CTRL

C37

L_BKLT_EN

K38

L_CTRL_CLK

L37

L_CTRL_DATA

J37

L_DDC_CLK

L35

L_DDC_DATA

B36

L_VDD_EN

F50

LVDS_IBG

H46

LVDS_VBG

P44

LVDS_VREFH

K46

LVDS_VREFL

D46

LVDSA_CLK#

B46

LVDSA_CLK

D44

LVDSB_CLK#

B44

LVDSB_CLK

G45

LVDSA_DATA#_0

F46

LVDSA_DATA#_1

G41

LVDSA_DATA#_2

C45

LVDSA_DATA#_3

F44

LVDSA_DATA_0

G47

LVDSA_DATA_1

F40

LVDSA_DATA_2

A45

LVDSA_DATA_3

B40

LVDSB_DATA#_0

A41

LVDSB_DATA#_1

F42

LVDSB_DATA#_2

D48

LVDSB_DATA#_3

D40

LVDSB_DATA_0

C41

LVDSB_DATA_1

G43

LVDSB_DATA_2

B48

LVDSB_DATA_3

J27

TVA_DAC

E27

TVB_DAC

G27

TVC_DAC

F26

TVA_RTN

B34

TV_DCONSEL_0

D34

TV_DCONSEL_1

J29

CRT_BLUE

G29

CRT_GREEN

F30

CRT_RED

E29

CRT_IRTN

D36

CRT_DDC_CLK

C35

CRT_DDC_DATA

J33

CRT_HSYNC

D32

CRT_TVO_IREF

G31

CRT_VSYNC

CANTIGA GMCH SFF_FCBGA1363

Del R82, R83. 10/18

3

PEGCOMP trace width and spacing is 20/25 mils.

PEGCOMP

PEG_RX#_0 PEG_RX#_1 PEG_RX#_2 PEG_RX#_3 PEG_RX#_4 PEG_RX#_5 PEG_RX#_6 PEG_RX#_7 PEG_RX#_8 PEG_RX#_9

PEG_RX_0 PEG_RX_1 PEG_RX_2 PEG_RX_3 PEG_RX_4 PEG_RX_5 PEG_RX_6 PEG_RX_7 PEG_RX_8

PEG_RX_9 PEG_RX_10 PEG_RX_11 PEG_RX_12 PEG_RX_13 PEG_RX_14 PEG_RX_15

PEG_TX#_0 PEG_TX#_1 PEG_TX#_2 PEG_TX#_3 PEG_TX#_4 PEG_TX#_5 PEG_TX#_6 PEG_TX#_7 PEG_TX#_8 PEG_TX#_9

PEG_TX_0

PEG_TX_1

PEG_TX_2

PEG_TX_3

PEG_TX_4

PEG_TX_5

PEG_TX_6

PEG_TX_7

PEG_TX_8

PEG_TX_9 PEG_TX_10 PEG_TX_11 PEG_TX_12 PEG_TX_13 PEG_TX_14 PEG_TX_15

U45 T44

D52 G49 K54 H50 M52 N49 P54 V46 Y50 V52 W49 AB54 AD46 AC55 AE49 AF54

E51 F48 J55 J49 M54 M50 P52 U47 AA49 V54 V50 AB52 AC47 AC53 AD50 AF52

L47 F52 P46 H54 L55 T46 R53 U49 T54 Y46 AB46 W53 Y54 AC49 AF46 AD54

J47 F54 N47 H52 L53 R47 R55 T50 T52 W47 AA47 W55 Y52 AB50 AE47 AD52

PEG_COMPI

PEG_COMPO

LVDS

TV

PEG_RX#_10 PEG_RX#_11 PEG_RX#_12 PEG_RX#_13 PEG_RX#_14 PEG_RX#_15

PEG_TX#_10

PCI-EXPRESS GRAPHICS

PEG_TX#_11 PEG_TX#_12 PEG_TX#_13 PEG_TX#_14 PEG_TX#_15

VGA

Remove R84 ~ R86 since already have 75ohm of page17. 10/27

1 2

R64 49.9_0402_1%R64 49.9_0402_1%

layout note: Place R64 <500mils to U4 pin U45&T44.

+VCC_PEG

2

Strap Pin Table

CFG[2:0] FSB Freq select

CFG[4:3] Reserved

CFG5 (DMI select)

CFG6

CFG7 (Intel Management Engine Crypto strap)

CFG8

CFG9 (PCIE Graphics Lane Reversal)

CFG10 (PCIE Lookback enable)

CFG11 CFG[13:12] (XOR/ALLZ)

CFG16 (FSB Dynamic ODT)

CFG19 (DMI Lane Reversal)

CFG20 (PCIE/SDVO concurrent)

1

000 = FSB 1066MHz 010 = FSB 800MHz 011 = FSB 667MHz

Others = Reserved

0 = DMI x 2

1 = DMI x 4

0 = The iTPM Host Interface is enable

*

1 = The iTPM Host Interface is disable

0 =(TLS)chiper suite with no confidentiality

1 =(TLS)chiper suite with confidentiality

Reserved

0 = Reverse Lane,15->0, 14->1

1 = Normal Operation,Lane Number in order

0 = Enable

1 = Disable

Reserved

00 = Reserved

01 = XOR Mode Enabled

10 = All Z Mode Enabled

*

(Default)11 = Normal Operation

ReservedCFG[15:14]

0 = Disabled

1 = Enabled

*

ReservedCFG[18:17]

0 = Normal Operation

(Lane number in Order)

*

1 = Reverse Lane

0 = Only PCIE or SDVO is operational.

1 = PCIE/SDVO are operating simu.

R91 2.21K_0402_1% @R91 2.21K_0402_1% @

CFG5<8> CFG6<8> CFG7<8>

CFG9<8> CFG10<8> CFG12<8> CFG13<8> CFG16<8>

CFG19<8> CFG20<8>

1 2

R69 2.21K_0402_1% @R69 2.21K_0402_1% @

1 2

R71 2.21K_0402_1% @R71 2.21K_0402_1% @

1 2

R75 2.21K_0402_1% @R75 2.21K_0402_1% @

1 2

R76 2.21K_0402_1% @R76 2.21K_0402_1% @

1 2

R78 2.21K_0402_1%@R78 2.21K_0402_1%@

1 2

R79 2.21K_0402_1% @R79 2.21K_0402_1% @

1 2

R93 2.21K_0402_1% @R93 2.21K_0402_1% @

1 2

R90 4.02K_0402_1%@ R90 4.02K_0402_1%@

1 2

R92 4.02K_0402_1% @R92 4.02K_0402_1% @

1 2

*

+3VS

A A

5

4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/02/13 2006/03/10

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, M/B LA-4021P

401554

10 36Wednesday, June 03, 2009

1

of

B

5

R96

1

C97

2

0.1U_0402_16V4Z

+3VS_DAC_CRT

12

10U_0603_6.3V

0.1U_0402_16V4Z

1

C618

C62

2

R104 0_0603_5% R104 0_0603_5%

1 2

9/27

+1.05VM

+1.05VM_PEGPLL

9/27

C63

0.01U_0402_16V7K

0.01U_0402_16V7K +3VS

R97

1

C63

2

0.1U_0402_16V4Z

R106 0_0805_5% R106 0_0805_5%

1

+

2

C82

R110 0_0603_5%

R97

BLM18PG181SN1D_0603

+1.5VS_PEG_BG

1

C78

2

1 2

100U_D2_6.3VM

1 2

1

C98

R111 0_0603_5% R111 0_0603_5%

+1.8V

2

0.1U_0402_16V4Z

+3VS_DAC_BG

12

22U_0805_6.3V

1

C64

2

+1.8V_TXLVDS

1

C73

C73 1000P_0402_50V7K

1000P_0402_50V7K

2

9/27

10U_0805_6.3V6M

C65

0.01U_0402_16V7K

1

9/27

C65

+1.05VM_DPLLA

2

+1.05VM_DPLLB

+1.05VM_HPLL +1.05VM_MPLL

+1.05VM_PEGPLL

+1.05VM_A_SM

1U_0603_10V4Z

4.7U_0805_10V4Z

1

2

C83

C84

+1.05VM_A_SM_CK

0.1U_0402_16V4Z

10U_0805_6.3V6M

1

C93

C92

2

12

1

2

C85

1

2

1U_0603_10V4Z

1

C99

2

+3VS

BLM18PG181SN1D_0603

0.1U_0402_16V4Z

1

D D

C617

2

install 0.1U & 10U for wavy issue. 7/29

change 0.1U to 22U for wavy issue. 5/20

+1.5VS

C C

B B

+1.05VM_HPLL

+1.8V_LVDS

4

U4H

J31

VCCA_CRT_DAC

L31

VCCA_DAC_BG

M33

VSSA_DAC_BG

J45

VCCA_DPLLA

L49

VCCA_DPLLB

AF10

VCCA_HPLL

AE1

VCCA_MPLL

U43

VCCA_LVDS1

U41

VCCA_LVDS2

V44

VSSA_LVDS

AJ43

VCCA_PEG_BG

AG43

VCCA_PEG_PLL

AW24

VCCA_SM_1

AU24

VCCA_SM_2

AW22

VCCA_SM_3

AU22

VCCA_SM_4

AU21

VCCA_SM_5

AW20

VCCA_SM_6

AU19

VCCA_SM_7

AW18

VCCA_SM_8

AU18

VCCA_SM_9

AW16

VCCA_SM_10

AU16

VCCA_SM_11

AT16

VCCA_SM_12

AR16

VCCA_SM_13

AU15

VCCA_SM_14

AT15

VCCA_SM_15

AR15

VCCA_SM_16

AW14

VCCA_SM_17

AT24

VCCA_SM_NCTF_1

AR24

VCCA_SM_NCTF_2

AT22

VCCA_SM_NCTF_3

AR22

VCCA_SM_NCTF_4

AT21

VCCA_SM_NCTF_5

AR21

VCCA_SM_NCTF_6

AT19

VCCA_SM_NCTF_7

AR19

VCCA_SM_NCTF_8

AT18

VCCA_SM_NCTF_9

AR18

VCCA_SM_NCTF_10

AU27

VCCA_SM_CK_4

AU28

VCCA_SM_CK_3

AU29

VCCA_SM_CK_2

AU31

VCCA_SM_CK_1

AT31

VCCA_SM_CK_NCTF_1

AR31

VCCA_SM_CK_NCTF_2

AT29

VCCA_SM_CK_NCTF_3

AR29

VCCA_SM_CK_NCTF_4

AT28

VCCA_SM_CK_NCTF_5

AR28

VCCA_SM_CK_NCTF_6

AT27

VCCA_SM_CK_NCTF_7

AR27

VCCA_SM_CK_NCTF_8

AH12

VCCD_HPLL

AE43

VCCD_PEG_PLL

M46

VCCD_LVDS_1

L45

VCCD_LVDS_2

CANTIGA GMCH SFF_FCBGA1363

CRTPLLA PEGA SM

A LVDS

POWER

LVDS

VTT_1 VTT_2 VTT_3 VTT_4 VTT_5 VTT_6 VTT_7 VTT_8

VTT_9 VTT_10 VTT_11 VTT_12 VTT_13

VTT

VCCA_TV_DAC

TVD TV/CRT

VCC_HDA

HDA

VCCD_QDAC

VCCD_TVDAC

VCC_AXF_1 VCC_AXF_2 VCC_AXF_3

AXF

VCC_SM_CK_1 VCC_SM_CK_2 VCC_SM_CK_3 VCC_SM_CK_4

SM CK

VCC_TX_LVDS

VCC_HV_1 VCC_HV_2

HV

VCC_PEG_1 VCC_PEG_2 VCC_PEG_3 VCC_PEG_4

PEG

VCC_DMI_1 VCC_DMI_2 VCC_DMI_3

DMI

VTTLF1 VTTLF2 VTTLF3

VTTLF

3

Change to 330u_R9, casue high limitation. 12/14

R13 T12 R11 T10 R9 T8 R7 T6 R5 T4 R3 T2 R1

K30

R101

R101 0_0402_5%

0_0402_5%

A31

1 2

N34

+1.5VS_QDAC

N32

+1.5VS_TVDAC

9/27

M25 N24 M23

BK24 BL23 BJ23 BK22

T41 C33

A33

AB44 Y44 AC43 AA43

AM44 AN43 AL43

K14 Y12 P2

0.47U_0603_10V7K

1

C100

2

+V1.05VM_AXF

+1.8V_SM_CK

+1.8V_TXLVDS

+VCC_PEG

+1.05VM_DMI

0.47U_0603_10V7K

2.2U_0805_16V4Z

1

C58

2

C58

9/29

0.47U_0603_10V7K

1

C101

2

4.7U_0805_10V4Z

1

C60

2

C59

+3VS_TVDAC

0.01U_0402_16V7K

Tie to GND. 9/27

+3VS_HV

0.1U_0402_16V4Z

1

2

C94

1

C102

2

1

2

C61

C71

+VCCP

1

2

C57

0.1U_0402_16V4Z

1

2

+

330U_D2E_2.5VM_R9

R100

1 2

BLM18PG181SN1D_0603

1

C72

2

9/27

+VCCP

D1 CH751H-40_SC76

+3VS

2

+1.05VM_DPLLA +1.05VM

9/27

1

@

+

C54

C53

2

0.1U_0402_16V4Z

+1.05VM_DPLLB

9/27

1

@

+

+3VS

+1.05VM_HPLL

+1.05VM_PEGPLL

2 1

+

C66

C70

2

0.1U_0402_16V4Z

1

2

C74

C75

0.1U_0402_16V4Z

4.7U_0805_10V4Z

+1.05VM_MPLL

1

C81

C80

2

0.1U_0402_16V4Z

10U_0805_6.3V6M

+1.8V_TXLVDS +1.8V

1

2

C89

1000P_0402_50V7K

0.1U_0402_16V4Z

10U_0805_10V4Z

1

C95

C96

2

+VCCP_D

R112 10_0402_5% R112 10_0402_5%

+1.5VS_QDAC

C103

0.1U_0402_16V4Z

0.01U_0402_16V7K

1

C104

C103

2

R94

1 2

BLM18PG181SN1D_0603

220U_D2_4VM_R15

R98

1 2

BLM18PG181SN1D_0603

220U_D2_4VM_R15

9/27

R102

1 2

BLM18PG181SN1D_0603

R105

1 2

BLM18PG181SN1D_0603

R108 0_0603_5% R108 0_0603_5%

1 2

C90

10U_0805_6.3V6M @

9/27

L1

1 2

BLM18PG121SN1D_0603

1 2

BLM18PG181SN1D_0603

4.7U_0603_6.3V

1

C619

2

9/27

1 2

9/27

+1.05VM

R114

9/27

9/29

R113 0_0402_5% R113 0_0402_5%

+1.05VM

4.7U_0805_10V4Z

+1.05VM_DMI

1 2

+1.5VS

+V1.05VM_AXF

10U_0805_10V4Z

+1.8V_SM_CK

0_0603_5%

R597

1 2

10U_0805_6.3V6M

1

C67

2

+1.5VS_TVDAC

C76

0.01U_0402_16V7K

1

C76

2

+VCC_PEG

10U_0805_6.3V6M

1

C88

C87

2

R109 0_0603_5% R109 0_0603_5%

0.1U_0402_16V4Z

0.1U_0402_16V4Z C91

1

C91

2

1

R95 0_0603_5%

1 2

1U_0603_10V4Z

1

C55

2

0.1U_0402_16V4Z

C68

0.1U_0402_16V4Z

C77

220U_D2_4VM_R15

C86

1 2

1

C56

2

R99 0_0805_5%

1 2

10U_0805_6.3V6M

1

C69

2

R103

1 2

BLM18PG181SN1D_0603

1

2

R107 0_0805_5%R107 0_0805_5%

1 2

1

+

2

+3VS_HV

9/21

9/27

+1.05VM

+1.8V

+1.5VS

9/21

+1.05VM

A A

install 4.7U for wavy issue. 7/29

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/02/13 2006/03/10

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, M/B LA-4021P

401554

11 36Wednesday, June 03, 2009

1

B

of

5

Extnal Graphic: 1210.34mA

9/21

D D

+1.05VM

0.22U_0402_10V4Z

0.1U_0402_16V4Z

220U_D2_4VM_R15

C112

C C

B B

A A

0.22U_0402_10V4Z

10U_0805_6.3V6M

1

C113

1

+

2

0.1U_0402_16V4Z

C115

C116

C114

1

2

C116

1

2

integrated Graphic: 1930.4mA

U4F

AT41

VCC_1

AR41

VCC_2

AN41

VCC_3

AJ41

VCC_4

AH41

VCC_5

AD41

VCC_6

AC41

VCC_7

Y41

VCC_8

W41

VCC_9

AT40

VCC_10

AM40

VCC_11

AL40

VCC_12

AJ40

VCC_13

AH40

VCC_14

AG40

VCC_15

AE40

VCC_16

AD40

VCC_17

AC40

VCC_18

AA40

VCC_19

Y40

VCC_20

AN35

VCC_21

AM35

VCC_22

AJ35

VCC_23

AH35

VCC_24

AD35

VCC_25

AC35

VCC_26

W35

VCC_27

AM34

VCC_28

AL34

VCC_29

AJ34

VCC_30

AH34

VCC_31

AG34

VCC_32

AE34

VCC_33

AD34

VCC_34

AC34

VCC_35

AA34

VCC_36

Y34

VCC_37

W34

VCC_38

AM32

VCC_39

AL32

VCC_40

AJ32

VCC_41

AH32

VCC_42

AE32

VCC_43

AD32

VCC_44

AA32

VCC_45

AM31

VCC_46

AL31

VCC_47

AJ31

VCC_48

AH31

VCC_49

AM29

VCC_50

AL29

VCC_51

AM28

VCC_52

AL28

VCC_53

AJ28

VCC_54

AM27

VCC_55

AL27

VCC_56

AM25

VCC_57

AL25

VCC_58

AJ25

VCC_59

AM24

VCC_60

N36

VCC_61

CANTIGA GMCH SFF_FCBGA1363

4

VCC CORE

POWER

VCC_NCTF_1 VCC_NCTF_2 VCC_NCTF_3 VCC_NCTF_4 VCC_NCTF_5 VCC_NCTF_6 VCC_NCTF_7 VCC_NCTF_8

VCC_NCTF_9 VCC_NCTF_10 VCC_NCTF_11 VCC_NCTF_12 VCC_NCTF_13 VCC_NCTF_14 VCC_NCTF_15 VCC_NCTF_16 VCC_NCTF_17 VCC_NCTF_18 VCC_NCTF_19 VCC_NCTF_20 VCC_NCTF_21 VCC_NCTF_22 VCC_NCTF_23 VCC_NCTF_24 VCC_NCTF_25 VCC_NCTF_26 VCC_NCTF_27 VCC_NCTF_28 VCC_NCTF_29 VCC_NCTF_30 VCC_NCTF_31

VCC NCTF

VCC_NCTF_32 VCC_NCTF_33 VCC_NCTF_34 VCC_NCTF_35 VCC_NCTF_36 VCC_NCTF_37 VCC_NCTF_38

AT38 AR38 AN38 AM38 AL38 AG38 AE38 AA38 Y38 W38 U38 T38 R38 AT37 AR37 AN37 AM37 AL37 AJ37 AH37 AG37 AE37 AD37 AC37 AA37 Y37 W37 U37 T37 R37 AT35 AR35 U35 AT34 AR34 U34 T34 R34

9/21

+1.05VM

+1.8V

C117

330U_D2E_2.5VM_R9

C117

3

+VCCGFX

3000mA

VCC_SM_1 VCC_SM_2 VCC_SM_3 VCC_SM_4 VCC_SM_5 VCC_SM_6 VCC_SM_7 VCC_SM_8 VCC_SM_9 VCC_SM_10 VCC_SM_11 VCC_SM_12 VCC_SM_13 VCC_SM_14 VCC_SM_15 VCC_SM_16 VCC_SM_17 VCC_SM_18 VCC_SM_19 VCC_SM_20 VCC_SM_21 VCC_SM_22 VCC_SM_23 VCC_SM_24 VCC_SM_25 VCC_SM_26 VCC_SM_27 VCC_SM_28 VCC_SM_29 VCC_SM_30 VCC_SM_31 VCC_SM_32 VCC_SM_33

VCC_AXG_1 VCC_AXG_2 VCC_AXG_3 VCC_AXG_4 VCC_AXG_5 VCC_AXG_6 VCC_AXG_7 VCC_AXG_8 VCC_AXG_9 VCC_AXG_10 VCC_AXG_11 VCC_AXG_12 VCC_AXG_13 VCC_AXG_14 VCC_AXG_15 VCC_AXG_16 VCC_AXG_17 VCC_AXG_18 VCC_AXG_19 VCC_AXG_20 VCC_AXG_21 VCC_AXG_22 VCC_AXG_23 VCC_AXG_24 VCC_AXG_25 VCC_AXG_26 VCC_AXG_27 VCC_AXG_28 VCC_AXG_29 VCC_AXG_30 VCC_AXG_31 VCC_AXG_32 VCC_AXG_33 VCC_AXG_34 VCC_AXG_35 VCC_AXG_36 VCC_AXG_37 VCC_AXG_38 VCC_AXG_39 VCC_AXG_40 VCC_AXG_41 VCC_AXG_42 VCC_AXG_43 VCC_AXG_44 VCC_AXG_45 VCC_AXG_46 VCC_AXG_47 VCC_AXG_48 VCC_AXG_49 VCC_AXG_50 VCC_AXG_51 VCC_AXG_52 VCC_AXG_53 VCC_AXG_54 VCC_AXG_55 VCC_AXG_56 VCC_AXG_57 VCC_AXG_58 VCC_AXG_59 VCC_AXG_60 VCC_AXG_61

VCC_AXG_SENSE VSS_AXG_SENSE

2

VCC_AXG_NCTF_1 VCC_AXG_NCTF_2 VCC_AXG_NCTF_3 VCC_AXG_NCTF_4 VCC_AXG_NCTF_5 VCC_AXG_NCTF_6 VCC_AXG_NCTF_7 VCC_AXG_NCTF_8

VCC_AXG_NCTF_9 VCC_AXG_NCTF_10 VCC_AXG_NCTF_11 VCC_AXG_NCTF_12 VCC_AXG_NCTF_13 VCC_AXG_NCTF_14 VCC_AXG_NCTF_15 VCC_AXG_NCTF_16 VCC_AXG_NCTF_17 VCC_AXG_NCTF_18 VCC_AXG_NCTF_19 VCC_AXG_NCTF_20 VCC_AXG_NCTF_21 VCC_AXG_NCTF_22 VCC_AXG_NCTF_23

POWER

VCC_AXG_NCTF_24 VCC_AXG_NCTF_25 VCC_AXG_NCTF_26 VCC_AXG_NCTF_27 VCC_AXG_NCTF_28 VCC_AXG_NCTF_29 VCC_AXG_NCTF_30 VCC_AXG_NCTF_31

VCC SMVCC GFX

VCC_AXG_NCTF_32 VCC_AXG_NCTF_33 VCC_AXG_NCTF_34 VCC_AXG_NCTF_35 VCC_AXG_NCTF_36 VCC_AXG_NCTF_37 VCC_AXG_NCTF_38 VCC_AXG_NCTF_39

VCC GFX NCTF

VCC_AXG_NCTF_40 VCC_AXG_NCTF_41 VCC_AXG_NCTF_42 VCC_AXG_NCTF_43 VCC_AXG_NCTF_44

VCC GFX

VCC_AXG_62 VCC_AXG_63 VCC_AXG_64 VCC_AXG_65 VCC_AXG_66 VCC_AXG_67 VCC_AXG_68 VCC_AXG_69 VCC_AXG_70 VCC_AXG_71 VCC_AXG_72 VCC_AXG_73 VCC_AXG_74 VCC_AXG_75 VCC_AXG_76 VCC_AXG_77 VCC_AXG_78 VCC_AXG_79 VCC_AXG_80

VCC_SM_LF1 VCC_SM_LF2 VCC_SM_LF3 VCC_SM_LF4 VCC_SM_LF5 VCC_SM_LF6 VCC_SM_LF7

VCC SM LF

T32 U31 T31 R31 U29 T29 R29 U28 U27 T27 R27 U25 T25 R25 U24 U22 T22 R22 U21 T21 R21 AM19 AL19 AH19 AG19 AE19 AD19 AC19 W19 U19 AM18 AL18 AJ18 AH18 AG18 AE18 AD18 AC18 AA18 Y18 W18 U18 T18 R18

AJ16 AH16 AD16 AC16 AA16 U16 T16 R16 AM15 AL15 AJ15 AH15 AG15 AE15 AA15 Y15 W15 U15 T15

AU45 BF52 BB38 BA19 BE9 AU9 AL9

+VCCGFX

VCCSM_LF1 VCCSM_LF2 VCCSM_LF3 VCCSM_LF4 VCCSM_LF5 VCCSM_LF6 VCCSM_LF7

U4G

BB36 BE35

AW34

10U_0805_6.3V6M

0.01U_0402_16V7K

C109

1

2

1

C120

2

10U_0805_6.3V

0.01U_0402_16V7K

C110

1

2

1 C121

C121

2

1U_0603_10V4Z

10U_0805_6.3V6M

330U_D2E_2.5VM_R9

1

C108

+

2

1

+

2

1 C118

C118

2

10U_0805_6.3V

1

C119

2

6326.84mA

T46PAD T46PAD T47PAD T47PAD

AW32

BK30 BH30 BF30

C111

2

BD30 BB30

AW30

1

BL29

BJ29 BG29 BE29 BC29 BA29 AY29 BK28 BH28 BF28 BD28 BB28

BL27

BJ27 BG27 BE27 BC27 BA27 AY27

AW26

BF24

BL19 BB16

W32 AG31 AE31 AD31 AC31 AA31

Y31

W31 AH29

0.1U_0402_16V4Z

AG29 AE29 AD29 AC29 AA29

Y29

W29 AH28 AG28 AE28 AA28 AH27 AG27 AE27 AD27 AC27 AA27

Y27

W27 AH25 AD25 AC25

W25

AJ24 AH24 AG24 AE24 AD24 AC24 AA24

Y24

W24

AM22

AL22

AJ22 AH22 AG22 AE22 AD22 AC22 AA22

AM21

AL21

AJ21 AH21 AD21 AC21 AA21

Y21

W21

AM16

AL16

AG13 AE13

1

2

C105

0.1U_0402_16V4Z

C127 0.1U_0402_16V4Z C127 0.1U_0402_16V4Z

1

2

1

2

C106

C107

4.7U_0805_10V4Z

0.22U_0402_10V4Z

C122 0.22U_0603_10V7K C122 0.22U_0603_10V7K

C123 0.22U_0603_10V7K C123 0.22U_0603_10V7K

1

C128 0.1U_0402_16V4Z C128 0.1U_0402_16V4Z

1

2

C125 1U_0603_10V4Z C125 1U_0603_10V4Z

C126 1U_0603_10V4Z C126 1U_0603_10V4Z

C124 0.47U_0402_6.3V6KC124 0.47U_0402_6.3V6K

1

2

CANTIGA GMCH SFF_FCBGA1363

5

4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/02/13 2006/03/10

Compal Secret Data

CANTIGA GMCH SFF_FCBGA1363

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, M/B LA-4021P

401554

1

B

of

12 36Wednesday, June 03, 2009

5

U4I

BA55

VSS_1

AU55

VSS_2

AN55

VSS_3

AJ55

VSS_4

AE55

VSS_5

AA55

VSS_6

U55

VSS_7

N55

VSS_8

BD54

VSS_9

BG53

VSS_10

AJ53

VSS_11

AE53

D D

C C

B B

A A

VSS_12

AA53

VSS_13

U53

VSS_14

N53

VSS_15

J53

VSS_16

G53

VSS_17

E53

VSS_18

K52

VSS_19

BG51

VSS_20

BA51

VSS_21

AW51

VSS_22

AU51

VSS_23

AR51

VSS_24

AN51

VSS_25

AL51

VSS_26

AJ51

VSS_27

AG51

VSS_28

AE51

VSS_29

AC51

VSS_30

AA51

VSS_31

W51

VSS_32

U51

VSS_33

R51

VSS_34

N51

VSS_35

L51

VSS_36

J51

VSS_37

G51

VSS_38

C51

VSS_39

BK50

VSS_40

AM50

VSS_41

K50

VSS_42

BG49

VSS_43

E49

VSS_44

C49

VSS_45

BD48

VSS_46

BB48

VSS_47

AY48

VSS_48

AV48

VSS_49

AT48

VSS_50

AP48

VSS_51

AM48

VSS_52

AK48

VSS_53

AH48

VSS_54

AF48

VSS_55

AD48

VSS_56

AB48

VSS_57

Y48

VSS_58

V48

VSS_59

T48

VSS_60

P48

VSS_61

M48

VSS_62

K48

VSS_63

H48

VSS_64

BL47

VSS_65

BG47

VSS_66

E47

VSS_67

C47

VSS_68

A47

VSS_69

BD46

VSS_70

AY46

VSS_71

AM46

VSS_72

AK46

VSS_73

AH46

VSS_74

BG45

VSS_75

AE45

VSS_76

AC45

VSS_77

AA45

VSS_78

W45

VSS_79

R45

VSS_80

N45

VSS_81

E45

VSS_82

BD44

VSS_83

BB44

VSS_84

AV44

VSS_85

AK44

VSS_86

AH44

VSS_87

AF44

VSS_88

AD44

VSS_89

K44

VSS_90

H44

VSS_91

BL43

VSS_92

BG43

VSS_93

AY43

VSS_94

AR43

VSS_95

W43

VSS_96

R43

VSS_97

M43

VSS_98

E43

VSS_99

CANTIGA GMCH SFF_FCBGA1363

VSS

+3VS+3VS +3VS +3VS

VSS_100 VSS_101 VSS_102 VSS_103 VSS_104 VSS_105 VSS_106 VSS_107 VSS_108 VSS_109 VSS_110 VSS_111 VSS_112 VSS_113 VSS_114 VSS_115 VSS_116 VSS_117 VSS_118 VSS_119 VSS_120 VSS_121 VSS_122 VSS_123 VSS_124 VSS_125 VSS_126 VSS_127 VSS_128 VSS_129 VSS_130 VSS_131 VSS_132 VSS_133 VSS_134 VSS_135 VSS_136 VSS_137 VSS_138 VSS_139 VSS_140 VSS_141 VSS_142 VSS_143 VSS_144 VSS_145 VSS_146 VSS_147 VSS_148 VSS_149 VSS_150 VSS_151 VSS_152 VSS_153 VSS_154 VSS_155 VSS_156 VSS_157 VSS_158 VSS_159 VSS_160 VSS_161 VSS_162 VSS_163 VSS_164 VSS_165 VSS_166 VSS_167 VSS_168 VSS_169 VSS_170 VSS_171 VSS_172 VSS_173 VSS_174 VSS_175 VSS_176 VSS_177 VSS_178 VSS_179 VSS_180 VSS_181 VSS_182 VSS_183 VSS_184 VSS_185 VSS_186 VSS_187 VSS_188 VSS_189 VSS_190 VSS_191 VSS_192 VSS_193 VSS_194 VSS_195 VSS_196 VSS_197 VSS_198

C43 A43 BD42 H42 BG41 AY41 AU41 AM41 AL41 AG41 AE41 AA41 R41 M41 E41 BD40 AU40 AR40 AN40 W40 U40 T40 R40 K40 H40 BL39 BG39 BA39 E39 C39 A39 BD38 AU38 H38 BG37 AU37 M37 E37 BD36 AW36 H36 BL35 BG35 AY35 AU35 AL35 AG35 AE35 AA35 Y35 M35 E35 A35 BD34 AU34 AN34 H34 BL33 BG33 AY33 E33 BD32 AU32 AN32 AG32 AC32 Y32 H32 B32 BJ31 BG31 AY31 AN31 M31 E31 N30 H30 AN29 AJ29 M29 A29 AW28 AN28 AD28 AC28 Y28 W28 H28 F28 AN27 AJ27 M27 BF26 BD26 N26 H26 BJ25 AY25 AU25

4

3

U4J

AN25

VSS_199

AG25

VSS_200

AE25

VSS_201

AA25

VSS_202

Y25

VSS_203

E25

VSS_204

A25

VSS_205

BD24

VSS_206

AN24

VSS_207

AL24

VSS_208

H24

VSS_209

BG23

VSS_210

AY23

VSS_211

E23

VSS_212

BD22

VSS_213

BB22

VSS_214

AN22

VSS_215

Y22

VSS_216

W22

VSS_217

H22

VSS_218

BL21

VSS_219

BG21

VSS_220

AY21

VSS_221

AN21

VSS_222

AG21

VSS_223

AE21

VSS_224

M21

VSS_225

E21

VSS_226

A21

VSS_227

BD20

VSS_228

H20

VSS_229

BG19 AY19

BD18

BL17 BG17 AY17

BD16 AN16 AG16 AE16

BG15 AY15 AN15 AD15 AC15

BD14

BL13 BG13 AY13 AU13 AR13

AJ13 AC13 AA13

BD12 AV12 AP12

AM12

AK12 AB12

BG11 AG11

BD10 AY10 AP10

M19

M17

W16

M15

W13 M13

BG9

BD8

E19 N18

H18

E17 A17

Y16 N16

H16

R15 E15 H14

U13 E13

A13

V12 P12 H12

E11

H10 BL9

E9 A9

BB8 AY8 AV8 AT8 AP8

VSS

VSS_230 VSS_231 VSS_232 VSS_233 VSS_234 VSS_235 VSS_236 VSS_237 VSS_238 VSS_239 VSS_240 VSS_241 VSS_242 VSS_243 VSS_244 VSS_245 VSS_246 VSS_247 VSS_248 VSS_249 VSS_250 VSS_251 VSS_252 VSS_253 VSS_254 VSS_255 VSS_256 VSS_257 VSS_258 VSS_259 VSS_260 VSS_261 VSS_262 VSS_263 VSS_264 VSS_265 VSS_266 VSS_267 VSS_268 VSS_269 VSS_270 VSS_271 VSS_272 VSS_273 VSS_274 VSS_275 VSS_276 VSS_277 VSS_278 VSS_279 VSS_280 VSS_281 VSS_282 VSS_283 VSS_284 VSS_285 VSS_286 VSS_287 VSS_288 VSS_289 VSS_290 VSS_291 VSS_292 VSS_293 VSS_294 VSS_295 VSS_296 VSS_297 VSS_298 VSS_299

CANTIGA GMCH SFF_FCBGA1363

VSS_NCTF_10 VSS_NCTF_11 VSS_NCTF_12

VSS NCTF

VSS_NCTF_13 VSS_NCTF_14 VSS_NCTF_15 VSS_NCTF_16 VSS_NCTF_17 VSS_NCTF_18 VSS_NCTF_19 VSS_NCTF_20 VSS_NCTF_21 VSS_NCTF_22 VSS_NCTF_23

VSS SCB

VSS_300 VSS_301 VSS_302 VSS_303 VSS_304 VSS_305 VSS_306 VSS_307 VSS_308 VSS_309 VSS_310 VSS_311 VSS_312 VSS_313 VSS_314 VSS_315 VSS_316 VSS_317 VSS_318 VSS_319 VSS_320 VSS_321 VSS_322 VSS_323 VSS_324 VSS_325 VSS_326 VSS_327 VSS_328 VSS_329 VSS_330 VSS_331 VSS_332 VSS_333 VSS_334 VSS_335 VSS_336 VSS_337 VSS_338 VSS_339 VSS_340 VSS_341 VSS_342 VSS_343 VSS_344 VSS_345 VSS_346 VSS_347 VSS_348 VSS_349 VSS_350 VSS_351 VSS_352 VSS_353 VSS_354 VSS_355 VSS_356 VSS_357 VSS_358

VSS_359 VSS_360 VSS_361 VSS_362

VSS_NCTF_1 VSS_NCTF_2 VSS_NCTF_3 VSS_NCTF_4 VSS_NCTF_5 VSS_NCTF_6 VSS_NCTF_7 VSS_NCTF_8 VSS_NCTF_9

VSS_SCB_1 VSS_SCB_2 VSS_SCB_3 VSS_SCB_4 VSS_SCB_5 VSS_SCB_6 VSS_SCB_7

2

AM8 AK8 AH8 AF8 AD8 AB8 Y8 V8 P8 M8 K8 H8 BJ7 E7 BF6 BC5 BA5 AW5 AU5 AR5 AN5 AL5 AJ5 AG5 AE5 AC5 AA5 W5 U5 N5 L5 J5 G5 C5 BH4 BE3 U3 E3 BC1 AW1 AR1 AL1 AG1 AC1 W1 N1 J1 AU43 BB42 AW38 BA35 L29 N28 N22 N20 N14 AL13 B10 AN13

N42 N40 N38 M39

AJ38 AH38 AD38 AC38 T35 R35 AT32 AR32 U32 R32 T28 R28 AT25 AR25 T24 R24 AN19 AJ19 AA19 Y19 T19 R19 AN18

BL55 BL1 A55 D1 B55 B2 A4

MCHGND1

R222 0_0402_5%@R222 0_0402_5%@

MCHGND2

R224 0_0402_5%@R224 0_0402_5%@

MCHGND3

R225 0_0402_5%@R225 0_0402_5%@ R25 0_0402_5%R25 0_0402_5%

MCHGND4

R228 0_0402_5%@R228 0_0402_5%@

1 2 1 2 1 2

1 2 1 2

1

R270

1 2

MCHGND1

Q68

RHU002N06_SOT323

100K_0402_5%

2

G

13

D

S

5

CRACK_BGA

R396

1 2

MCHGND2

Q69

RHU002N06_SOT323

100K_0402_5%

2

G

13

D

S

CRACK_BGA

R397

1 2

MCHGND3

Q70

RHU002N06_SOT323

100K_0402_5%

2

G

13

D

S

4

CRACK_BGA

R398

1 2

MCHGND4

Q71

RHU002N06_SOT323

100K_0402_5%

2

G

13

D

S

CRACK_BGA

CRACK_BGA <23,33>

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/02/13 2006/03/10

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, M/B LA-4021P

401554

1

B

of

13 36Wednesday, June 03, 2009

5

DDR_A_DQS#[0..7]<9>

DDR_A_D[0..63]<9>

DDR_A_DM[0..7]<9>

DDR_A_DQS[0..7]<9>

DDR_A_MA[0..14]<9>

D D

Layout Note: Place near JP36

+1.8V

Change C131 to 330uF. 9/26

2.2U_0805_16V4Z

1

C131

+

2

330U_D2E_2.5VM_R9

C C

B B

A A

Layout Note: Place one cap close to every 2 pullup resistors terminated to +0.9V

+0.9V

0.1U_0402_16V4Z

1

2

C141

DDR_A_MA5 DDR_A_MA8

DDR_A_MA1 DDR_A_MA3

DDR_CS0_DIMMA# DDR_A_RAS#

DDR_A_BS0 DDR_A_MA10

DDR_A_CAS# DDR_A_WE#

DDR_CS1_DIMMA# M_ODT1

1

2

1

2

C142

C132

0.1U_0402_16V4Z

1 4 2 3

2 3 1 4

1

2

C143

C133

1

2

0.1U_0402_16V4Z

DDR_A_MA11

1 2

5

2.2U_0805_16V4Z

C134

C135

1

2

0.1U_0402_16V4Z

1

2

C144

+0.9V

RP156_0404_4P2R_5% RP156_0404_4P2R_5%

RP356_0404_4P2R_5% RP356_0404_4P2R_5%

RP556_0404_4P2R_5% RP556_0404_4P2R_5%

RP756_0404_4P2R_5% RP756_0404_4P2R_5%

RP956_0404_4P2R_5% RP956_0404_4P2R_5%

RP1156_0404_4P2R_5% RP1156_0404_4P2R_5%

R11756_0402_5% R11756_0402_5%

2

C145

C146

14 23

RP2 56_0404_4P2R_5%RP2 56_0404_4P2R_5%

14 23

RP4 56_0404_4P2R_5%RP4 56_0404_4P2R_5%

14 23

RP6 56_0404_4P2R_5%RP6 56_0404_4P2R_5%

14 23

RP8 56_0404_4P2R_5%RP8 56_0404_4P2R_5%

14 23

RP10 56_0404_4P2R_5%RP10 56_0404_4P2R_5%

14 23

RP12 56_0404_4P2R_5%RP12 56_0404_4P2R_5%

14 23

RP13 56_0404_4P2R_5%RP13 56_0404_4P2R_5%

2.2U_0805_16V4Z

2.2U_0805_16V4Z C136

C136

1

2

0.1U_0402_16V4Z

1

2

C147

DDR_A_BS2 DDR_CKE0_DIMMA

DDR_A_MA6 DDR_A_MA7

DDR_A_MA9 DDR_A_MA12

DDR_A_MA2 DDR_A_MA4

DDR_A_BS1 DDR_A_MA0

DDR_A_MA13 M_ODT0

DDR_A_MA14 DDR_CKE1_DIMMA

0.1U_0402_16V4Z

1

2

C148

C138

C137

1

2

0.1U_0402_16V4Z

1

2

C149

C150

4

0.1U_0402_16V4Z

C139

C140

1

2

0.1U_0402_16V4Z

1

2

C151

C152

Layout Note: Place these resistor closely JP9,all trace length Max=1.5"

4

3

DDR_A_D4 DDR_A_D1

DDR_A_DQS#0 DDR_A_DQS0

DDR_A_D2 DDR_A_D3

DDR_A_D8 DDR_A_D14

DDR_A_DQS#1 DDR_A_DQS1

DDR_A_D9 DDR_A_D15

DDR_A_D16 DDR_A_D17

DDR_A_DQS#2 DDR_A_DQS2

DDR_A_D18 DDR_A_D19

DDR_A_D29 DDR_A_D24

DDR_A_DM3

DDR_A_D26 DDR_A_D27

DDR_CKE0_DIMMA<8>

DDR_A_BS2<9>

DDR_A_BS0<9>

DDR_A_WE#<9>

DDR_A_CAS#<9>

DDR_CS1_DIMMA#<8>

0.1U_0402_16V4Z

1

2

C153

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

M_ODT1<8>

ICH_SMBDATA<15,16,22>

ICH_SMBCLK<15,16,22>

3

DDR_CKE0_DIMMA

DDR_A_BS2 DDR_A_MA12

DDR_A_MA9 DDR_A_MA8

DDR_A_MA5 DDR_A_MA3 DDR_A_MA1

DDR_A_MA10 DDR_A_BS0 DDR_A_WE#

DDR_A_CAS# DDR_CS1_DIMMA#

M_ODT1 DDR_A_D37

DDR_A_D36 DDR_A_DQS#4

DDR_A_DQS4 DDR_A_D35

DDR_A_D32 DDR_A_D40

DDR_A_D44 DDR_A_DM5 DDR_A_D41

DDR_A_D46 DDR_A_D49

DDR_A_D48

DDR_A_DQS#6 DDR_A_DQS6

DDR_A_D54 DDR_A_D50

DDR_A_D61 DDR_A_D60

DDR_A_DM7 DDR_A_D59

+3VM

2006/02/13 2006/03/10

+1.8V +1.8V

JP36

1

VREF

3

VSS

5

DQ0

7

DQ1

9

VSS

11

DQS0#

13

DQS0

15

VSS

17

DQ2

19

DQ3

21

VSS

23

DQ8

25

DQ9

27

VSS

29

DQS1#

31

DQS1

33

VSS

35

DQ10

37

DQ11

39

VSS

41

VSS

43

DQ16

45

DQ17

47

VSS

49

DQS2#

51

DQS2

53

VSS

55

DQ18

57

DQ19

59

VSS

61

DQ24

63

DQ25

65

VSS

67

DM3

69

NC

71

VSS

73

DQ26

75

DQ27

77

VSS

79

CKE0

81

VDD

83

NC

85

BA2

87

VDD

89

A12

91

A9

93

A8

95

VDD

97

A5

99

A3

101

A1

103

VDD

105

A10/AP

107

BA0

109

WE#

111

VDD

113

CAS#

115

NC/S1#

117

VDD

119

NC/ODT1

121

VSS

123

DQ32

125

DQ33

127

VSS

129

DQS4#

131

DQS4

133

VSS

135

DQ34

137

DQ35

139

VSS

141

DQ40

143

DQ41

145

VSS

147

DM5

149

VSS

151

DQ42

153

DQ43

155

VSS

157

DQ48

159

DQ49

161

VSS

163

NC,TEST

165

VSS

167

DQS6#

169

DQS6

171

VSS

173

DQ50

175

DQ51

177

VSS

179

DQ56

181

DQ57

183

VSS

185

DM7

187

VSS

189

DQ58

191

DQ59

193

VSS

195

SDA

197

SCL

199

VDDSPD

1

C155

C154

2

2.2U_0603_6.3V6K

Compal Secret Data

0.1U_0402_16V4Z

Deciphered Date

SO-DIMM A 4mm Height

Top side

2

V_DDR_MCH_REF

2.2U_0805_16V4Z

2

VSS DQ4 DQ5 VSS DM0 VSS DQ6 DQ7

VSS DQ12 DQ13

VSS

DM1

VSS

CK0

CK0#

VSS DQ14 DQ15

VSS

VSS DQ20 DQ21

VSS

NC DM2 VSS

DQ22 DQ23

VSS

DQ28 DQ29

VSS

DQS3#

DQS3

VSS

DQ30 DQ31

VSS

NC/CKE1

VDD

NC/A15 NC/A14

VDD

A11

A7 A6

VDD

A4 A2 A0

VDD

BA1

RAS#

S0#

VDD

ODT0

NC/A13

VDD

NC VSS

DQ36 DQ37

VSS DM4 VSS

DQ38 DQ39

VSS

DQ44 DQ45

VSS

DQS5#

DQS5

VSS

DQ46 DQ47

VSS

DQ52 DQ53

VSS

CK1

CK1#

VSS DM6 VSS

DQ54 DQ55

VSS

DQ60 DQ61

VSS

DQS7#

DQS7

VSS

DQ62 DQ63

VSS

SA0 SA1

FOX_ASOA426-M2RN-7FCONN@

2

4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40

42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200

DDR_A_D6 DDR_A_D0

DDR_A_DM0 DDR_A_D5

DDR_A_D7 DDR_A_D13

DDR_A_D12 DDR_A_DM1

DDR_A_D11 DDR_A_D10

DDR_A_D20 DDR_A_D21

DDR_A_DM2 DDR_A_D23

DDR_A_D22 DDR_A_D28

DDR_A_D25 DDR_A_DQS#3

DDR_A_DQS3 DDR_A_D31

DDR_A_D30 DDR_CKE1_DIMMA

DDR_A_MA14 DDR_A_MA11

DDR_A_MA7 DDR_A_MA6

DDR_A_MA4 DDR_A_MA2 DDR_A_MA0

DDR_A_BS1 DDR_A_RAS# DDR_CS0_DIMMA#

M_ODT0 DDR_A_MA13

DDR_A_D39 DDR_A_D38

DDR_A_DM4 DDR_A_D34

DDR_A_D33 DDR_A_D45

DDR_A_D43 DDR_A_DQS#5

DDR_A_DQS5 DDR_A_D47

DDR_A_D42 DDR_A_D52

DDR_A_D53

DDR_A_DM6 DDR_A_D51

DDR_A_D55 DDR_A_D57

DDR_A_D56 DDR_A_DQS#7

DDR_A_DQS7 DDR_A_D62DDR_A_D58

DDR_A_D63

12

R116

R115

10K_0402_5%

12

2.2U_0805_16V4Z C129

C129

1

2

M_CLK_DDR0 <8> M_CLK_DDR#0 <8>

PM_EXTTS#0 <8>

DDR_CKE1_DIMMA <8>

DDR_A_BS1 <9> DDR_A_RAS# <9> DDR_CS0_DIMMA# <8>

M_ODT0 <8>

M_CLK_DDR1 <8> M_CLK_DDR#1 <8>

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, M/B LA-4021P

401554

1

C130

1

V_DDR_MCH_REF <8,15>

of

14 36Wednesday, June 03, 2009

of

14 36Wednesday, June 03, 2009

of

14 36Wednesday, June 03, 2009

B

0.1U_0402_16V4Z

0.1U_0402_16V4Z 1

2

5

DDR_B_DQS#[0..7]<9>

DDR_B_D[0..63]<9> DDR_B_DM[0..7]<9>

DDR_B_DQS[0..7]<9>

DDR_B_MA[0..14]<9>

D D

Layout Note: Place near JP34

+1.8V

1

C524

+

2

@

C C

Layout Note: Place one cap close to every 2 pullup resistors terminated to +0.9V

+0.9V

0.1U_0402_16V4Z

B B

A A

DDR_B_MA1 DDR_B_MA3

DDR_B_BS0 DDR_B_MA10

DDR_B_MA0 DDR_B_BS1

DDR_B_RAS# DDR_CS2_DIMMB#

DDR_B_CAS# DDR_B_WE#

DDR_CS3_DIMMB# M_ODT2 M_ODT3

DDR_B_MA11

Reserve C524. 9/26

2.2U_0805_16V4Z

330U_D2E_2.5VM_R9

1

2

C575

2.2U_0805_16V4Z

0.1U_0402_16V4Z

1

2

C566

1

2

C576

1

2

0.1U_0402_16V4Z

1

2

C577

1 4 2 3

2 3 1 4

1 2

5

C567

2.2U_0805_16V4Z

C568

C569

1

2

0.1U_0402_16V4Z

RP2256_0404_4P2R_5% RP2256_0404_4P2R_5%

RP2456_0404_4P2R_5% RP2456_0404_4P2R_5%

RP2656_0404_4P2R_5% RP2656_0404_4P2R_5%

RP2856_0404_4P2R_5% RP2856_0404_4P2R_5%

RP3056_0404_4P2R_5% RP3056_0404_4P2R_5%

RP3256_0404_4P2R_5% RP3256_0404_4P2R_5%

R8056_0402_5% R8056_0402_5%

0.1U_0402_16V4Z

1

2

C578

C579

+0.9V

RP23 56_0404_4P2R_5%RP23 56_0404_4P2R_5%

RP25 56_0404_4P2R_5%RP25 56_0404_4P2R_5%

RP27 56_0404_4P2R_5%RP27 56_0404_4P2R_5%

RP29 56_0404_4P2R_5%RP29 56_0404_4P2R_5%

RP31 56_0404_4P2R_5%RP31 56_0404_4P2R_5%

RP33 56_0404_4P2R_5%RP33 56_0404_4P2R_5%

RP34 56_0404_4P2R_5%RP34 56_0404_4P2R_5%

2.2U_0805_16V4Z

2.2U_0805_16V4Z 1

2

0.1U_0402_16V4Z

1

2

C580

DDR_B_MA9

14

DDR_B_MA12

23

DDR_CKE3_DIMMB

14

DDR_B_MA14

23

DDR_B_MA5

14

DDR_B_MA8

23

DDR_B_MA7

14

DDR_B_MA6

23

DDR_B_MA4

14

DDR_B_MA2

23

14

DDR_B_MA13

23

DDR_B_BS2

14

DDR_CKE2_DIMMB

23

0.1U_0402_16V4Z

C571

C572

C570

0.1U_0402_16V4Z

1

2

C581

C572

1

2

0.1U_0402_16V4Z

1

2

C582

1

2

C583

4

0.1U_0402_16V4Z

C573

C574

1

2

0.1U_0402_16V4Z

1

2

C586

C585

C584

Layout Note: Place these resistor closely JP10,all trace length Max=1.5"

4

3

DDR_B_D57 DDR_B_D56

DDR_B_DQS#7 DDR_B_DQS7

DDR_B_D58 DDR_B_D63

DDR_B_D48 DDR_B_D49

DDR_B_DQS#6 DDR_B_DQS6

DDR_B_D51 DDR_B_D50

DDR_B_D40 DDR_B_D44

DDR_B_DQS#5 DDR_B_DQS5

DDR_B_D42

DDR_B_D37 DDR_B_D32

DDR_B_DM4

DDR_B_D39

DDR_CKE2_DIMMB<8>

DDR_B_BS2<9>

DDR_B_BS0<9> DDR_B_WE#<9>

DDR_B_CAS#<9>

0.1U_0402_16V4Z

1

2

C587

DDR_CS3_DIMMB#<8>

M_ODT3<8>

ICH_SMBDATA<14,16,22>

ICH_SMBCLK<14,16,22>

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

DDR_CKE2_DIMMB

DDR_B_BS2 DDR_B_MA12

DDR_B_MA9 DDR_B_MA8

DDR_B_MA5 DDR_B_MA3 DDR_B_MA1

DDR_B_MA10 DDR_B_BS0 DDR_B_WE#

DDR_B_CAS# DDR_CS3_DIMMB#

M_ODT3 DDR_B_D30

DDR_B_D27 DDR_B_DQS#3

DDR_B_DQS3 DDR_B_D25

DDR_B_D28 DDR_B_D23

DDR_B_D22 DDR_B_DM2 DDR_B_D17

DDR_B_D16 DDR_B_D11

DDR_B_D10

DDR_B_DQS#1 DDR_B_DQS1

DDR_B_D12 DDR_B_D13

DDR_B_D2 DDR_B_D3

DDR_B_DM0 DDR_B_D0

DDR_B_D5

+3VM +3VM

2006/02/13 2006/03/10

+1.8V +1.8V

JP3

1

VREF

3

VSS

5

DQ0

7

DQ1

9

VSS

11

DQS0#

13

DQS0

15

VSS

17

DQ2

19

DQ3

21

VSS

23

DQ8

25

DQ9

27

VSS

29

DQS1#

31

DQS1

33

VSS

35

DQ10

37

DQ11

39

VSS

41

VSS

43

DQ16

45

DQ17

47

VSS

49

DQS2#

51

DQS2

53

VSS

55

DQ18

57

DQ19

59

VSS

61

DQ24

63

DQ25

65

VSS

67

DM3

69

NC

71

VSS

73

DQ26

75

DQ27

77

VSS

79

CKE0

81

VDD

83

NC

85

BA2

87

VDD

89

A12

91

A9

93

A8

95

VDD

97

A5

99

A3

101

A1

103

VDD

105

A10/AP

107

BA0

109

WE#

111

VDD

113

CAS#

115

NC/S1#

117

VDD

119

NC/ODT1

121

VSS

123

DQ32

125

DQ33

127

VSS

129

DQS4#

131

DQS4

133

VSS

135

DQ34

137

DQ35

139

VSS

141

DQ40

143

DQ41

145

VSS

147

DM5

149

VSS

151

DQ42

153

DQ43

155

VSS

157

DQ48

159

DQ49

161

VSS

163

NC,TEST

165

VSS

167

DQS6#

169

DQS6

171

VSS

173

DQ50

175

DQ51

177

VSS

179

DQ56

181

DQ57

183

VSS

185

DM7

187

VSS

189

DQ58

191

DQ59

193

VSS

195

SDA

197

SCL

199

VDDSPD

SUYIN_600008FB200G103ZLCONN@

1

C588

2

2.2U_0603_6.3V6K

1

C589

2

0.1U_0402_16V4Z

Compal Secret Data

SUYIN_600008FB200G103ZLCONN@

SO-DIMM B

REVERSE

Bottom side

Deciphered Date

VSS DQ4 DQ5 VSS DM0 VSS DQ6 DQ7

VSS DQ12 DQ13

VSS

DM1

VSS

CK0

CK0#

VSS DQ14 DQ15

VSS

VSS DQ20 DQ21

VSS

DM2

VSS DQ22 DQ23

VSS DQ28 DQ29

VSS

DQS3#

DQS3

VSS DQ30 DQ31

VSS

NC/CKE1

VDD

NC/A15 NC/A14

VDD

RAS#

VDD ODT0

NC/A13

VDD

VSS DQ36 DQ37

VSS

DM4

VSS DQ38 DQ39

VSS DQ44 DQ45

VSS

DQS5#

DQS5

VSS DQ46 DQ47

VSS DQ52 DQ53

VSS

CK1

CK1#

VSS

DM6

VSS DQ54 DQ55

VSS DQ60 DQ61

VSS

DQS7#

DQS7

VSS DQ62 DQ63

VSS

SAO

2

V_DDR_MCH_REF

2

DDR_B_D60

4

DDR_B_D61

6 8

DDR_B_DM7

10 12

DDR_B_D62

14

DDR_B_D59

16 18

DDR_B_D52

20

DDR_B_D53

22 24

DDR_B_DM6

26 28 30 32 34

DDR_B_D54

36

DDR_B_D55

38 40

42

DDR_B_D45

44

DDR_B_D41

46 48 50

NC

A11

A7 A6

A4 A2

A0 BA1 S0#

NC

SA1

2

52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200

DDR_B_DM5 DDR_B_D46

DDR_B_D43DDR_B_D47 DDR_B_D36

DDR_B_D33 DDR_B_DQS#4

DDR_B_DQS4 DDR_B_D34

DDR_B_D38DDR_B_D35 DDR_CKE3_DIMMB

DDR_B_MA14 DDR_B_MA11

DDR_B_MA7 DDR_B_MA6

DDR_B_MA4 DDR_B_MA2 DDR_B_MA0

DDR_B_BS1 DDR_B_RAS# DDR_CS2_DIMMB#

M_ODT2 DDR_B_MA13

DDR_B_D26 DDR_B_D31

DDR_B_DM3 DDR_B_D24

DDR_B_D29 DDR_B_D18

DDR_B_D19 DDR_B_DQS#2

DDR_B_DQS2 DDR_B_D21

DDR_B_D20 DDR_B_D14

DDR_B_D15

DDR_B_DM1

DDR_B_D8DDR_B_D9 DDR_B_D7

DDR_B_D6 DDR_B_DQS#0

DDR_B_DQS0 DDR_B_D1

DDR_B_D4

10K_0402_5%

12

R77

2.2U_0805_16V4Z

0.1U_0402_16V4Z

C564

1

2

M_CLK_DDR3 <8> M_CLK_DDR#3 <8>

PM_EXTTS#1 <8>

DDR_CKE3_DIMMB <8>

DDR_B_BS1 <9> DDR_B_RAS# <9> DDR_CS2_DIMMB# <8>

M_ODT2 <8>

M_CLK_DDR2 <8> M_CLK_DDR#2 <8>

R73

1 2 10K_0402_5%

10K_0402_5%

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, M/B LA-4021P

401554

V_DDR_MCH_REF <8,14>

C565

1

B

of

15 36Wednesday, June 03, 2009

of

15 36Wednesday, June 03, 2009

of

15 36Wednesday, June 03, 2009

1

5

PCI

CLKSEL1

FSLA

CLKSEL0

MHz

FSLC1FSLB

CLKSEL2

CPU

0 1000 2660 33.3

1

0

1

D D

200

166

FSA

CPU_BSEL0<5>

C C

CPU_BSEL1<5>

B B

FSC

CPU_BSEL2<5>

12

R128 2.2K_0402_5%

1 2

R130 0_0402_5%R130 0_0402_5%

FSB

1 2

R139

R139 0_0402_5%

0_0402_5%

9/20

12

R143 10K_0402_5%

1 2

R145 0_0402_5%R145 0_0402_5%

SRC

FSB

MHz

1066

800

1000

667

100

+VCCP

R127

56_0402_5%@

1 2

R129 1K_0402_5%

12

R131

1K_0402_5%@

+VCCP

R137

1K_0402_5%@

R138

1 2

1K_0402_5%

1 2

12

R62

0_0402_5%@

1 2

R144 1K_0402_5% R144 1K_0402_5%

12

R146

R146 0_0402_5%

0_0402_5%

MHz

33.30

33.3

MCH_CLKSEL1 <8>

Add for PCIE port80 debug port. 10/18.

MCH_CLKSEL2 <8>

Install. 11/06

14.31818MHZ_20P_1BX14318BE1A

CLK_XTAL_OUT

CLK_XTAL_IN

Y1

A A

12

2

C178

33P_0402_50V8J

1

5

9/149/14

2

C17733P_0402_50V8J C17733P_0402_50V8J

1

+3VS

R147

R147 10K_0402_5%

10K_0402_5%

1 2

R150

R150 @

@

1 2

10K_0402_5%

4

+3VM

1 2

R118 0_1206_5%

MCH_CLKSEL0 <8>

CLK_PCI_1394<27>

CLK_PCI_TCG<32> CLK_PCI_EC<33>

CLK_PCI_DEBUG<26>

CLK_PCI_DB<32>

CLK_PCI_ICH<20>

CLK_48M_ICH<22>

CLK_14M_ICH<22> CLK_14M_KBC<33>

+3VS +3VS

R148

R148 @

@

10K_0402_5%

1 2

27_SELITP_EN

R151

R151 10K_0402_5%

10K_0402_5%

1 2

4

3

+3VM_CK505

CLK_PCI_1394 CLK_PCI_TCG CLK_PCI_EC PCI_CLK3

CLK_PCI_DB CLK_PCI_ICH

CLK_48M_ICH

CLK_14M_ICH CLK_14M_KBC

R149

R149 10K_0402_5%

10K_0402_5%

1 2

PCI2_TME

R152

R152 @

@

10K_0402_5%

1 2

1

2

C159

C158

10U_0805_10V4Z

0.1U_0402_16V4Z

CLKREQ#_B_R CLKREQG_WWAN#_R

1 2 1 2 1 2

1

2

C160

0.1U_0402_16V4Z

9/14

+1.05VM_CK505

1 2

1 2 1 2

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

1

2

0.1U_0402_16V4Z

R120 475_0402_1%

R120 475_0402_1% R121 475_0402_1%

R121 475_0402_1%

R13222_0402_5%

R13222_0402_5% R13322_0402_5%

R13322_0402_5% R13433_0402_1%

R13433_0402_1% R33833_0402_1% R33833_0402_1% R13533_0402_1%

R13533_0402_1% R13633_0402_1%

R13633_0402_1%

Issued Date

C161

C163

C162

0.1U_0402_16V4Z

12 12

+3VM_CK505

+1.05VM_CK505

PCI2_TME

27_SEL ITP_EN

CLK_XTAL_IN CLK_XTAL_OUT

FSA

R14033_0402_1%

FSB

FSC

R14133_0402_1%

R14133_0402_1% R14233_0402_1%

R14233_0402_1%

3

+1.05VM_CK505+1.05VM

1 2

R58 0_1206_5%

1

2

2 C164

C164

0.1U_0402_16V4Z

R119 10K_0402_5% R119 10K_0402_5%

1 2

R122 10K_0402_5%

1 2

U5

6

VDDREF

12

VDDPCI

19

VDD48

23

VDD96_IO

27

VDDPLL3

55

VDDSRC

72

VDDCPU

31

VDDPLL3_IO

38

VDDSRC_IO

52

VDDSRC_IO

62

VDDSRC_IO

66

VDDCPU_IO

13

PCI

14

PCI2/TME

15

PCI3

16

PCI4/27_Select

17

PCI_F5/ITP_EN

5

X1

4

X2

20

USB_48MHz/FSLA

2

FSLB/TEST_MODE

7

FSLC/TEST_SEL/REF0

59

GNDSRC

18

GNDPCI

22

GND48

26

GND

30

GND

69

GNDCPU

34

GNDSRC

42

GNDSRC

3

GNDREF

ICS9LPRS397DKLFT MLF 72P

2006/02/13 2006/03/10

CPUT2_ITP_LPR/SRCT8_LPR CPUC2_ITP_LPR/SRCC8_LPR

27MHz_NonSS/SRCT1_LPR/SE1

Compal Secret Data

10U_0805_10V4Z

CLKREQ#_B <8> CLKREQG_WWAN# <26> CLKREQ_WLAN# <26>

SRCT2_LPR/SATAT_LPR SRCC2_LPR/SATAC_LPR

SRCT0_LPR/DOTT_96_LPR

SRCC0_LPR/DOTC_96_LPR

27MHz_SS/SRCC1_LPR/SE2

+3VS

SDATA

PCI_STOP#

CPU_STOP#

CPUT0_LPR_F

CPUC0_LPR_F

CPUT1_LPR_F

CPUC1_LPR_F

SRCT7_LPR SRCC7_LPR

SRCT6_LPR SRCC6_LPR

SRCT10_LPR SRCC10_LPR

SRCT11_LPR SRCC11_LPR

SRCT9_LPR SRCC9_LPR

SRCT4_LPR SRCC4_LPR

SRCT3_LPR SRCC3_LPR

CK_PWRGD/PD#

Deciphered Date

NC

SCLK

CR7#

CR#6

CR10#

CR#11

CR#9

CR#4

CR#3

CR#A

REF1

2

1

2

C171

C172

0.1U_0402_16V4Z

11

10 9

54 53

71 70

68 67

CLKREQ#_B_R

65 64

63 61

60 58 57

56

CLKREQ_WLAN#_R

49 50

51

CLKREQG_WWAN#_R

46 48

47 43 44

45

41 39

40 37 35

36

32 33

24 25

28 29

1

CLKSATAREQ#_R

21

8

2

1

2

C173

0.1U_0402_16V4Z

CLKREQ_WLAN#_R CLKSATAREQ#_R

R_CPU_XDP R_CPU_XDP#

R_PCIE_ICH R_PCIE_ICH#

1

2

C174

10U_0805_10V4Z

ICH_SMBCLK <14,15,22> ICH_SMBDATA <14,15,22>

H_STP_PCI# <22> H_STP_CPU# <22>

CLK_CPU_BCLK <4> CLK_CPU_BCLK# <4>

CLK_MCH_BCLK <8> CLK_MCH_BCLK# <8>

CLK_MCH_3GPLL <8> CLK_MCH_3GPLL# <8>

CLK_PCIE_MCARD <26> CLK_PCIE_MCARD# <26>

CLK_PCIE_WAN <26> CLK_PCIE_WAN# <26>

CLKREQA# <26>

CLK_PCIE_EXP <26> CLK_PCIE_EXP# <26>

CLK_PCIE_SATA <21> CLK_PCIE_SATA# <21>

CLK_MCH_DREFCLK <8> CLK_MCH_DREFCLK# <8>

MCH_SSCDREFCLK <8> MCH_SSCDREFCLK# <8>

CK_PWRGD <22>

1

2

C175

C176

0.1U_0402_16V4Z

R124 475_0402_1% R124 475_0402_1% R125 475_0402_1% R125 475_0402_1%

RP14 0_0404_4P2R_5%RP14 0_0404_4P2R_5%

1 4 2 3

RP35 0_0404_4P2R_5%RP35 0_0404_4P2R_5%

2 3 1 4

Title

Size Document Number Rev

401554

Date: Sheet

1

C156

C156 C157

C157 C165

C165 C166

C166 C167

C167 C168

C168 C169

C169 C170

C170

1 2

12

12P_0402_50V8J

12

12P_0402_50V8J

12 12 12 12

Place close to U5

Mount C157 & C166 tp solve

WWAN noise issue. 1/23

R123 10K_0402_5%

12 12

Compal Electronics, Inc.

SCHEMATIC, M/B LA-4021P

1 2

R126 10K_0402_5% R126 10K_0402_5%

1 2

CLK_CPU_XDP <4> CLK_CPU_XDP# <4>

CLK_PCIE_ICH <22> CLK_PCIE_ICH# <22>

1

CLKSATAREQ# <22>

CLK_48M_ICH

5P_0402_50V8C@

CLK_14M_ICH CLK_PCI_ICH

4.7P_0402_50V8C@

4.7P_0402_50V8C@ CLK_14M_KBC

CLK_PCI_EC

4.7P_0402_50V8C@

4.7P_0402_50V8C@ CLK_PCI_TCG

4.7P_0402_50V8C@

4.7P_0402_50V8C@ CLK_PCI_1394

5P_0402_50V8C@

CLK_PCI_DB

5P_0402_50V8C@

16 36Wednesday, June 03, 2009

+3VS

B

of

A

CRT Connector

1 1

12

+5VS

C186

0.1U_0402_16V4Z

1

5

P

R16251K_0402_5% R16251K_0402_5%

1 2

A2Y

G

3

R16351K_0402_5% R16351K_0402_5%

OE#

CRT_HSYNC<10>

CRT_VSYNC<10>

2 2

1 2

D_RED D_GREEN D_BLUE

R15475_0402_5% R15475_0402_5%

R15375_0402_5% R15375_0402_5%

R15575_0402_5% R15575_0402_5%

12

D_RED<10>

D_GREEN<10>

D_BLUE<10>

+5VS

C187

0.1U_0402_16V4Z

1 2

U6

U6 SN74AHCT1G125GW_SOT353-5

SN74AHCT1G125GW_SOT353-5

4

1 2

1

5

P

4

OE#

A2Y

G

U7

U7 SN74AHCT1G125GW_SOT353-5

SN74AHCT1G125GW_SOT353-5

3

L

B

Place cloce to GMCH

L

L2

L2 TAIYO BK1608LL560-T 0603

1

C181

2

10P_0402_50V8J

TAIYO BK1608LL560-T 0603

1 2

L3

L3 TAIYO BK1608LL560-T 0603

TAIYO BK1608LL560-T 0603

1 2

L4

L4 TAIYO BK1608LL560-T 0603

TAIYO BK1608LL560-T 0603

1 2

1

C182

2

10P_0402_50V8J

1

C188

5P_0402_50V8C@

2

1

C183

2

1

C189

2

D_RED

D_GREEN

D_BLUE

1

C180

2

10P_0402_50V8J

HSYNC D_HSYNC

R156 0_0603_5%R156 0_0603_5%

1 2

VSYNC D_VSYNC

R161 0_0603_5%R161 0_0603_5%

1 2

Place cloce to GMCH

C

F1

1.1A_6VDC_FUSE

L17

L17 0_0805_5%

0_0805_5%

1 2

L18

L18 0_0805_5%

0_0805_5%

1 2

L19

L19 0_0805_5%

0_0805_5%

1 2

1

C185

C184

2

10P_0402_50V8J

5P_0402_50V8C@

layout note: D_HSYNC & D_VSYNC should be routed to docking connector then to VGA connector

21

D_HSYNC <34>

D_VSYNC <34>

D_DDCDATA<34>

D_DDCCLK<34>

Del L20. 5/16

D2

D2 CH491D_SC59

CH491D_SC59

2 1

0.1U_0402_16V4Z

C179

1

2

RED

GREEN

BLUE

+CRTVDD+RCRT_VCC+5VS

W=40mils

JP4

6

11

1 7

12

2 8

13

3 9

14

4 10 15

5

+CRTVDD

12

R157

2.2K_0402_5%

R157

2.2K_0402_5%

R158

2.2K_0402_5%

R158

2.2K_0402_5%

Place cloce to GMCH

L

CONN@

SUYIN_070546FR015S235ZR_15P

SUYIN_070546FR015S235ZR_15P 16 17

D

BLUE<34>

GREEN<34>

RED<34>

1 3

D

Q2

BSS138_SOT23

2

G

1 3

D

Q3

S

BLUE GREEN RED D_HSYNC D_VSYNC

2

G

S

1 2

R159

2.2K_0402_5%

R159

2.2K_0402_5%

+3VS

D5

D3

1

2

3

DAN217T146_SC59-3

@

D5

D6

D4

1

2

3

DAN217T146_SC59-3

@

D6

1

2

3

2

DAN217T146_SC59-3

@

10/25

RED_R, GREEN_R, & BLUE_R should still be connected to output of RGB filter (L17-2, L18-2, L19-2). JP4 pins should only connect to RED, GREEN, & BLUE.

1 2

R160

2.2K_0402_5%

R160

2.2K_0402_5% CRT_DDC_DATA <10>

CRT_DDC_CLK <10>

E

D7

1

+CRTVDD

2

3

@

DAN217T146_SC59-3

@

3 3

4 4

A

B

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2006/02/13 2006/07/26

Compal Secret Data

Deciphered Date

D

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, M/B LA-4021P

401554

E

of

17 36Wednesday, June 03, 2009

of

17 36Wednesday, June 03, 2009

of

17 36Wednesday, June 03, 2009

B

5

4

3

2

1

LCD/PANEL BD. CONN.

D D

C190 0.1U_0603_50VC190 0.1U_0603_50V

add 4.7UH inductor for CMO flicker issue

Modify design in 1/29.

2N7002DW-T/R7_SOT363-6

+3VS

ENABLT<10>

LID_SW#<19,22,33>

R81

R81 100K_0402_1%

100K_0402_1%

R634

10K_0402_5%

12

2N7002DW-T/R7_SOT363-6

12

C C

Q81A

Q81B

2

5

+5VALW

R164

4.7K_0402_5%

R164

4.7K_0402_5%

1 2

61

3

4

+5VS +5VS_INV

S

Q4

G

SI2301BDS_SOT23

DISPLAY_OFF

G

2

G

Q83

G

Q83

2N7002_SOT23

Reserve for power saving. 3/19

D

13

12

13

D

R165

@

S

LCDVDD

22_0402_5%

B+

LQM21FN4R7N00L_0805

+3VS

+5V_WEBCAM

12

C191 68P_0402_50V8J

12

L5

1 2

ALS_EN<22>

BLON_PWM<10>

USB20_P10<22> USB20_N10<22>

B+_LCD

JP5

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30

ACES_88242-3001_30P

ACES_88242-3001_30P CONN@

CONN@

+3VS

R872.2K_0402_5% R872.2K_0402_5%

1 3 5 7

9 11 13 15 17 19 21 23 25 27 29

3132

TXOUT_L0- <10> TXOUT_L0+ <10>

TXOUT_L1- <10> TXOUT_L1+ <10>

TXOUT_L2- <10> TXOUT_L2+ <10>

TXCLK_L- <10> TXCLK_L+ <10>

R882.2K_0402_5% R882.2K_0402_5%

HP request. (9/4)

1 2

DDC2_CLK <10> DDC2_DATA <10>

WEBCAM_ON/OFF#<22>

+3VALW

1 2

R601

R601 10K_0402_5%

10K_0402_5%

Del D41, Q64, C558, C598, R493 & Q65. 01/29

+5VALW +5V_WEBCAM

1U_0603_10V4Z

1

C559

2

1 2

R600

100K_0402_5%

1 2

R602 47K_0402_5%

13

D

Q7

2

RHU002N06_SOT323

G

S

Q5

Q5 SI2301BDS_SOT23

SI2301BDS_SOT23

S

G

2

1

C562

0.1U_0402_16V4Z

2

D

13

+5VALW

1

C560

C313

C561

2

0.01U_0402_16V7K

2

0.1U_0402_16V4Z

4.7U_0805_10V4Z

Add 10K pull down to prevent floating issue. 2/23

LCD POWER CIRCUIT

LCDVDD

R169

12

R166

R166 100_0402_1%

100_0402_1%

13

D

Q41

1 2

R168 47K_0402_5%R168 47K_0402_5%

2

G

S

1

OUT

2

IN

GND

3

1 2

0.1U_0402_16V4Z

Q8

Q8 DTC124EKAT146_SC59-3

DTC124EKAT146_SC59-3

B B

RHU002N06_SOT323

ENAVDD<10>

100K_0402_1%

A A

5

4

LCDVDD

Q6

Q6 SI2301 1P_SOT23

SI2301 1P_SOT23

D

S

D

S

1 3

G

2

R167 1M_0402_5%R167 1M_0402_5%

1 2

C192 0.1U_0402_16V4ZC192 0.1U_0402_16V4Z

1

2

1

C194

4.7U_0805_10V4Z

2

3

C193

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

1 2

2005/03/10 2006/03/10

+3VS

Connect LCD power source to +3VS directly. 5/16

1

C195

4.7U_0805_10V4Z@

2

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, M/B LA-4021P

401554

1

of

18 36Wednesday, June 03, 2009

of

18 36Wednesday, June 03, 2009

of

18 36Wednesday, June 03, 2009

B

5

4

3

2

1

D D

WL/BT_LED<30>

BT_LED<31>

C C

WL/BT_LED

BT_LED

WL_LED

BT_LED

WL_LED

+3VS

12

R570

R570 47K_0402_5%

47K_0402_5%

61

Q10A

Q10A 2N7002DW-T/R7_SOT363-6

5

1 2

2N7002DW-T/R7_SOT363-6

Q10 & Q11 change to 2 in

3

1 package. 3/17

Q10B

Q10B 2N7002DW-T/R7_SOT363-6

2N7002DW-T/R7_SOT363-6

4

2

R170 100K_0402_5%

R171 100K_0402_5%

+3VS

47K

10K

1 3

WW_LED#<26>

Q9

Q9 DTA114YKAT146_SOT23-3

DTA114YKAT146_SOT23-3

2

WL_LED

2

10K

+3VS

WL_LED# <26>

13

Q79

Q79 DTA114YKAT146_SOT23-3

DTA114YKAT146_SOT23-3

47K

Cause space issue, move them from LED board to M/B. 10/09

+3VS

Q32

47K

DTA114YKAT146_SOT23-3

13

D

HDD_HALTLED<22>

B B

HDD_HALTLED

100K_0402_5%

R334

@ R334

@

D

Q80

2

2N7002_SOT23

G

S

12

47K

10K

2

1 3

AMBER_BATLED#<33>

GREEN_BATLED#<33>

IDE_LED#<21>

STB_LED<30,34>

To LED BOARD

+3VS+3VL+5VS

AMBER_BATLED# GREEN_BATLED# IDE_LED# HDD_STP# STB_LED WL/BT_LED

JP6

1

2

3

4

5

6

7

8

9

10

11

GND

12

GND

ACES_85201-1005NCONN@

To LID switch Board

1

LID_SW#<18,22,33>

D45

BAV99_SOT323-3@

+3VS

3 2

JP8

1

2

4

2

G1

3

5

3

G2

ACES_85204-03001CONN@

+3VL

POWER LED

A A

aquq white

STB_LED

Add in 11/28. Place them close to SW1.

5

12

R620

R620 360_0402_5%

360_0402_5%

21

D42

D42 QSMW-B121

QSMW-B121

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/02/13 2006/03/10

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, M/B LA-4021P

401554

19 36Wednesday, June 03, 2009

1

B

of

5

+3VS

1 2

R172 8.2K_0402_5%

1 2

R173 8.2K_0402_5%

1 2 1 2 1 2 1 2 1 2 1 2

1 2 1 2 1 2 1 2 1 2 1 2 1 2

1 2 1 2 1 2 1 2

12

R174 8.2K_0402_5%

R174 8.2K_0402_5% R175 8.2K_0402_5%

D D

C C

R175 8.2K_0402_5% R176 8.2K_0402_5%

R176 8.2K_0402_5% R177 8.2K_0402_5%

R177 8.2K_0402_5% R178 8.2K_0402_5%

R178 8.2K_0402_5% R179 8.2K_0402_5%

R179 8.2K_0402_5%

+3VS

R180 8.2K_0402_5%

R180 8.2K_0402_5% R181 8.2K_0402_5%

R181 8.2K_0402_5% R182 8.2K_0402_5%

R182 8.2K_0402_5% R183 8.2K_0402_5%

R183 8.2K_0402_5% R184 8.2K_0402_5%

R184 8.2K_0402_5% R185 47K_0402_5%R185 47K_0402_5% R186 8.2K_0402_5%

R186 8.2K_0402_5% R187 8.2K_0402_5%

R187 8.2K_0402_5% R188 8.2K_0402_5%

R188 8.2K_0402_5% R189 8.2K_0402_5%

R189 8.2K_0402_5% R191 8.2K_0402_5%

R191 8.2K_0402_5% R192 8.2K_0402_5%

R192 8.2K_0402_5%

PCI_DEVSEL# PCI_STOP# PCI_TRDY# PCI_FRAME# PCI_PLOCK# PCI_IRDY# PCI_SERR# PCI_PERR#

PCI_PIRQA# PCI_PIRQB# PCI_PIRQC# PCI_PIRQD# PCI_PIRQE# ODD_DET# PCI_PIRQG# PCI_PIRQH# PCI_REQ0# PCI_REQ1# PCI_REQ2# PCI_REQ3#

PCI_AD[0..31]<27>

Change to ODD_DET#. 10/18

4

U8B PCI_AD0 PCI_AD1 PCI_AD2 PCI_AD3 PCI_AD4 PCI_AD5 PCI_AD6 PCI_AD7 PCI_AD8 PCI_AD9 PCI_AD10 PCI_AD11 PCI_AD12 PCI_AD13 PCI_AD14 PCI_AD15 PCI_AD16 PCI_AD17 PCI_AD18 PCI_AD19 PCI_AD20 PCI_AD21 PCI_AD22 PCI_AD23 PCI_AD24 PCI_AD25 PCI_AD26 PCI_AD27 PCI_AD28 PCI_AD29 PCI_AD30 PCI_AD31

PCI_PIRQA# PCI_PIRQB# PCI_PIRQC# PCI_PIRQD#

U8B

A11

AD0

B12 A10

C12

A8 A12 E10 C11

B9

D8

A4

E8

A3

D9 C8 C2 D7

B3 D11

B6

D5 D3

F4

E3

E4

B2

C4 C1 D1

E2

J4

H2

F1

F5

F2

PCI

AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31

Interrupt I/F

PIRQA# PIRQB# PIRQC# PIRQD#C7PIRQH#/GPIO5

ICH9-M SFF ES_FCBGA569

REQ0#

GNT0# REQ1#/GPIO50 GNT1#/GPIO51 REQ2#/GPIO52 GNT2#/GPIO53 REQ3#/GPIO54 GNT3#/GPIO55

C/BE0# C/BE1# C/BE2# C/BE3#

IRDY#

PCIRST#

DEVSEL#

PERR#

PLOCK#

SERR#

STOP#

TRDY#

FRAME#

PLTRST#

PCICLK

PME#

PIRQE#/GPIO2 PIRQF#/GPIO3

PIRQG#/GPIO4

PAR

3

PCI_REQ0#

G4

PCI_GNT0#

E1

PCI_REQ1#

A9 E12 B11 C10 D6 C6

D10 A5 E6 C9

C3 B1 T3 A7 D4 C5 H5 A6 A2 B8

A21 B5 T1

G3 G1 F3 H4

PCI_REQ2# PCI_REQ3#

PCI_GNT3# PCI_CBE#0

PCI_CBE#1 PCI_CBE#2 PCI_CBE#3

PCI_IRDY# PCI_PAR PCI_RST# PCI_DEVSEL# PCI_PERR# PCI_PLOCK# PCI_SERR# PCI_STOP# PCI_TRDY# PCI_FRAME#

PLT_RST# CLK_PCI_ICH PCI_PME#

PCI_PIRQE# ODD_DET# PCI_PIRQG# PCI_PIRQH#

PCI_CBE#0 <27> PCI_CBE#1 <27> PCI_CBE#2 <27> PCI_CBE#3 <27>

PCI_IRDY# <27> PCI_PAR <27> PCI_RST# <26,27> PCI_DEVSEL# <27> PCI_PERR# <27>

PCI_SERR# <27,33> PCI_STOP# <27> PCI_TRDY# <27> PCI_FRAME# <27>

PLT_RST# <8,26,32> CLK_PCI_ICH <16> PCI_PME# <26>

R190 0_0402_5%

12

MODEM_DISABLE# <30> PCI_REQ2# <27> PCI_GNT2# <27>

PCI_PIRQE# <27> ODD_DET# <21>

PCI_PIRQG# <27>

ACCEL_INT# <26>

2

1

B B

PCI_GNT3#

A A

A16 swap override Strap

Low= A16 swap override Enble High= Default

PCI_GNT3#

*

12

R194

1K_0402_5% @

5

Boot BIOS Strap

PCI_GNT0# SPI_CS#1

12

R195

R195 1K_0402_5%

1K_0402_5%

1

0

1

0

1

PCI_GNT0#

DEL J3. 9/29

4

Boot BIOS Location

SPI

*

PCI

LPC

KBC_SPI_CS1#<22>

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

Place closely pin B10

CLK_PCI_ICH

12

R196

1K_0402_5%@

2006/02/13 2006/03/10

12

@

@ R193

R193 10_0402_5%

10_0402_5%

1

@

@ C196

C196

8.2P_0402_50V

2

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, M/B LA-4021P

401554

20 36Wednesday, June 03, 2009

1

B

of

+RTCVCC

1 2

R197 330K_0402_1%

1 2

R198 1M_0402_5%R198 1M_0402_5%

1 2

R199 330K_0402_1%R199 330K_0402_1%

1 2

R200 20K_0402_5%

Change from 180K to 20K & 0.1u to 1u. 9/29

D D

5

LAN100_SLP SM_INTRUDER# ICH_INTVRMEN ICH_SRTCRST#

C197

1U_0603_10V4Z

R201

R202

@

1 2

R202

0_0402_5%

@

1 2

1

2

4

3

2

1

ICH_RSVD HDA_SDOUT_CODEC

00 0 1 11

XOR CHAIN ENTRANCE STRAP:RSVD

+3VS

1 2

R206 1K_0402_5%@R206 1K_0402_5%@

1 2

R208 1K_0402_5%@R208 1K_0402_5%@

C C

Remove R227 & C199

SATA CD-ROM Connector

B B

JP9

1

GND

2

A+

3

A-

4

GND

5

B-

6

B+

7

GND

R357 0_0402_5%R357 0_0402_5%

8

DP

9

V5

10

V5

11

MD

12

GND

13

GND

14

GND

15

GND

+5VS

A A

C219

1

2

10U_0805_10V4Z

Place component's closely SATA

L

CONN.(JP9)

1 0

AC97_SDOUT ICH_RSVD

Add C599 ~ C602 to solve WWAN noise issue. 1/23

OCTEK_SAT-22DE1G_NRSUYIN_127059FR022S305ZLCONN@

SATA_TXP1_C

C203 0.01U_0402_50V7K

SATA_TXN1_C

C202 0.01U_0402_50V7K

SATA_RXN1

C204 0.01U_0402_50V7K

SATA_RXP1

C205 0.01U_0402_50V7K

1 2

+5VS

C222

C221

C220

1

2

0.1U_0402_16V4Z

5

0.1U_0402_16V4Z

AC97_BITCLK_CODEC<28>

AC97_SDOUT_MDC<30>

AC97_SDOUT_CODEC<28>

1 2 1 2

AC97_BITCLK_MDC<30>

Description

RV

XOR Normal(D) PCIE Bit1

ICH_RSVD <22>

56P_0402_50VNPO

56P_0402_50VNPO C599

C599

C600

C600 56P_0402_50VNPO

56P_0402_50VNPO

56P_0402_50VNPO C601

C601

C602

C602 56P_0402_50VNPO

56P_0402_50VNPO

1

2

C593

0.1U_0402_16V4Z

+RTCVCC

12

SATA_TXP1_CR

SATA_TXN1_CR SATA_RXN1_C

SATA_RXP1_C

ODD_DET# <20>

+3VS

ICH_RTCX1

R205

R205 20K_0402_5%

20K_0402_5%

1 2

1

12

C198

1U_0603_10V4Z

AC97_RST#_MDC<30>

IDE_LED#<19>

+1.5VS

AC97_SDIN0<28>

AC97_SDIN1<30>

R219 33_0402_5%

R219 33_0402_5% R221 33_0402_5%

R221 33_0402_5%

+3VS

SATA_RXN0_C SATA_RXP0_C SATA_TXN0_CR SATA_TXP0_CR

SATA_RXN1_C SATA_RXP1_C SATA_TXN1_CR SATA_TXP1_CR

AC97_BITCLK_MDC AC97_BITCLK_CODEC HDA_BITCLK

AC97_SYNC_CODEC<28>

AC97_SYNC_MDC<30>

AC97_RST#_CODEC<28>

AC97_SDOUT_MDC AC97_SDOUT_CODEC

G_BATLED#<33>

CLRP1

2

SHORT PADS

GLAN_CLK<24>

LAN_RSTSYNC<24>

LAN_RXD0<24> LAN_RXD1<24> LAN_RXD2<24>

LAN_TXD0<24> LAN_TXD1<24> LAN_TXD2<24>

R220 24.9_0402_1% R220 24.9_0402_1%

1 2

R211 33_0402_5%

1 2

R212 33_0402_5%

1 2

R213 33_0402_5%

1 2

R214 33_0402_5%

1 2

R215 33_0402_5%

1 2

R217 33_0402_5%

1 2

Swap in 9/28

1 2 1 2

R229 10K_0402_5% R229 10K_0402_5%

12

R646 0_0402_5%R646 0_0402_5%

1 2

R647 0_0402_5%R647 0_0402_5%

1 2

R648 0_0402_5%R648 0_0402_5%

1 2

R649 0_0402_5%R649 0_0402_5%

1 2

ICH_RTCX2 ICH_RTCRST#

ICH_SRTCRST# SM_INTRUDER#

ICH_INTVRMEN LAN100_SLP

T50PAD T50PAD

GLAN_COMP

HDA_SYNC HDARST#

AC97_SDOUT

T114PAD T114PAD

SATA_TXN0_R SATA_TXP0_R

SATA_TXN1_R SATA_TXP1_R

1.8" SATA HDD CONN

SATA_TXP0_CR SATA_TXN0_CR

SATA_RXN0_C SATA_RXP0_C

C211

1

2

10U_0805_10V4Z

Place component's closely SATA

L

CONN.(JP10)

4

SATA_TXP0_C

C2010.01U_0402_50V7K

12

SATA_TXN0_C

C2000.01U_0402_50V7K

12

SATA_RXN0

C2080.01U_0402_50V7K

12

SATA_RXP0

C2090.01U_0402_50V7K

12

C214

C212

1

2

0.1U_0402_16V4Z

C214

C213

1

2

0.1U_0402_16V4Z

U8A

F25

RTCX1

G25

RTCX2

G24

RTCRST#

C24

SRTCRST#

C23

INTRUDER#

E25

INTVRMEN

D25

LAN100_SLP

G22

GLAN_CLK

D14

LAN_RSTSYNC

A14

LAN_RXD0

D12

LAN_RXD1

B14

LAN_RXD2

D13

LAN_TXD0

C13

LAN_TXD1

A13

LAN_TXD2

D15

GPIO56

H22

GLAN_COMPI

H21

GLAN_COMPO

AE7

HDA_BIT_CLK

AB7

HDA_SYNC

AA7

HDA_RST#

AB6

HDA_SDIN0

AE6

HDA_SDIN1

AC6

HDA_SDIN2

AA5

HDA_SDIN3

AC7

HDA_SDOUT

AD8

HDA_DOCK_EN#/GPIO33

AB8

HDA_DOCK_RST#/GPIO34

AC9

SATALED#

AE14

SATA0RXN

AD14

SATA0RXP

AC15

SATA0TXN

AD15

SATA0TXP

AD13

SATA1RXN

AC13

SATA1RXP

AA14

SATA1TXN

AB14

SATA1TXP

ICH9-M SFF ES_FCBGA569

JP10

1 2 3 4 5 6 7 8

ACES_85201-08051CONN@

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

FWH0/LAD0 FWH1/LAD1 FWH2/LAD2 FWH3/LAD3

FWH4/LFRAME#

RTCLAN / GLAN

LPCCPU

RTCLAN / GLAN

LPCCPU

LDRQ0#

LDRQ1#/GPIO23

A20GATE

A20M#

DPRSTP#

DPSLP#

FERR#

CPUPWRGD

IGNNE#

INIT#

INTR

RCIN#

NMI

SMI#

STPCLK#

THRMTRIP#

TP11

SATA4RXN SATA4RXP

IHDA

SATA4TXN

SATA4TXP

SATA5RXN SATA5RXP SATA5TXN

SATA5TXP

SATA_CLKN SATA_CLKP

SATA

SATARBIAS#

SATARBIAS

1 2

10M_0402_5%

C20612P_0402_50V8J C20612P_0402_50V8J

1

2

2006/02/13 2006/03/10

LPC_AD0

H3

LPC_AD1

J3

LPC_AD2

K5

LPC_AD3

L3 J2 H1

J1

GATEA20

N3 AB23

H_DPRSTP_R#

AE23 AE24

H_FERR#_R

AD25 AE22 AD23 AE21

AD24

KB_RST#

L1 AD21

H_SMI#

AC21

H_STPCLK#

AC25

THRMTRIP_ICH#

AC23 AC22

AD12 AE12 AB12 AA12

AC11 AD11 AB10 AA10

CLK_PCIE_SATA#

AC16

CLK_PCIE_SATA

AB16 AD10

AE10

R231

C20712P_0402_50V8J C20712P_0402_50V8J Y2 4

1

32.768KHZ_12.5P_1TJS125BJ2A251Y232.768KHZ_12.5P_1TJS125BJ2A251

1

IN

OUT

2

NC3NC

2

Compal Secret Data

T49 PADT49 PAD

R230 18_0402_1%

Within 500 mils

ICH_RTCX1

ICH_RTCX2

+RTCVCC +3VL

Deciphered Date

LPC_AD[0..3] <26,32,33>

LPC_FRAME# <26,32,33>

T111 PADT111 PAD T48 PADT48 PAD

GATEA20 <33> H_A20M# <4>

R209 0_0402_5% R209 0_0402_5%

1 2

H_DPSLP# <5>

R210 56_0402_5%R210 56_0402_5%

1 2

H_PWRGOOD <4,5> H_IGNNE# <4> H_INIT# <4>

H_INTR <4>

KB_RST# <33>

H_NMI <4> H_SMI# <4>

H_STPCLK# <4>

R226 54.9_0402_1%R226 54.9_0402_1%

1 2

placed within 2" from ICH9M

CLK_PCIE_SATA# <16> CLK_PCIE_SATA <16>

1 2

7/3 change 24.9 ohm to 18 ohm for signal integrity.

R232 0_0402_5%R232 0_0402_5%

1 2

1

C210

C210 1U_0603_10V4Z

1U_0603_10V4Z

2

9/27

for H_DPRSTP# & H_DPSLP#.

H_DPRSTP# <5,8,42>

H_FERR#

Place Close to U8.

+VCCP

12

R223

R223 56_0402_5%

56_0402_5%

ZZZ1

PCB-MB

D8

3

1

DAN202UT106_SC70-3

2

Custom

Date: Sheet

9/27Del PU R203~R204

+1.05VM

R207

R207 56_0402_5%

56_0402_5%

1 2

H_FERR# <4>

+3VS

GATEA20

R216 10K_0402_5%R216 10K_0402_5%

KB_RST#

R233

R233 1K_0402_5%

1K_0402_5%

RTC1

1 2

W=20mils

L

Compal Electronics, Inc.

Title

Size Document Number Rev

Compal Electronics, Inc.

SCHEMATIC, M/B LA-4021P

401554

1 2

R218 10K_0402_5%R218 10K_0402_5%

1 2

H_THERMTRIP# <4,8>

JBATT1

RTC2

1

+

SUYIN_060003FA002G202NLCONN@

1

2

-

-+

of

21 36Wednesday, June 03, 2009

B

+3VS

Add R326 10K. 10/04

1 2

R326 10K_0402_5%

1 2

R234 10K_0402_5%

1 2

R237 8.2K_0402_5%

1 2

R242 8.2K_0402_5%@ R242 8.2K_0402_5%@

1 2

R245 47K_0402_5%R245 47K_0402_5%

1 2

R246 8.2K_0402_5%

D D

+3VALW

C C

+3VALW

B B

A A

1 2

R248 10K_0402_5%

1 2

R244 8.2K_0402_5%@ R244 8.2K_0402_5%@

1 2

R68 8.2K_0402_5%

1 2

R508 8.2K_0402_5%

1 2

R621 10K_0402_5%

1 2

R626 10K_0402_5%@ R626 10K_0402_5%@

1 2

R252 10K_0402_5%R252 10K_0402_5%

1 2

R255 10K_0402_5%

1 2

R258 10K_0402_5%

1 2

R259 1K_0402_5%R259 1K_0402_5%

1 2

R260 10K_0402_5%

1 2

R321 10K_0402_5%

Add R321 in 10/03.

1 2

R266 10K_0402_5%R266 10K_0402_5%

1 2

R269 10K_0402_5%@R269 10K_0402_5%@

1 2

R272 10K_0402_5%R272 10K_0402_5%

1 2

R273 10K_0402_5%R273 10K_0402_5%

1 2

R331 10K_0402_5%R331 10K_0402_5%

RP16

45 36 27 18

10K_1206_8P4R_5%

RP15

45 36 27 18

10K_1206_8P4R_5%

1 2

R238 10K_0402_5%R238 10K_0402_5%

1 2

R603 10K_0402_5%R603 10K_0402_5%

Add in 9/14.

Add RP15 back. 9/27

1 2

R335 10K_0402_5%R335 10K_0402_5%

1 2

R627 10K_0402_5%@ R627 10K_0402_5%@

ICH_SMBDATA<14,15,16>

ICH_SMBCLK<14,15,16>

ICH_SM_DA<4,26>

ICH_SM_CLK<4,26>

ALS_EN#

2

G

5

LAN_STATUS#_D PM_PWROK_R SIRQ PM_CLKRUN#

THERM_SCI#

HDD_HALTLED GPIO22 NPCI_RST# ALS_EN#

GPIO21 GPIO37 GPIO18 GPIO57

LINKALERT# PCIE_WAKE# ICH_RI# XDP_DBRESET# S4_STATE# ICH_LOW_BAT#

SUS_PWR_ACK AC_PRESENT ME__EC_CLK1 ME__EC_DATA1 LAN_PHYPC_R

USB_OC#7 USB_OC#5 USB_OC#0 USB_OC#4

USB_OC#1 USB_OC#6 WXMIT_OFF# USB_OC#2

GPIO11 XMIT_OFF#

EXP_RST GPIO57

R287

2.2K_0402_5%

+3VS

R292

330_0402_5%

1 2 13

D

Q16

Q16 RHU002N06_SOT323

RHU002N06_SOT323

S

R282

2.2K_0402_5%

ICH_SMBDATA

+3VS

12

+5VS

5

Add R621 in 12/03.

R276 low -->default High -->No boot

10K_0402_5%

PREP#<25,34>

+3VM

R283

12

2.2K_0402_5%

S

G

+3VM

12

R288

2.2K_0402_5%

2.2K_0402_5% Q14

Q14 RHU002N06_SOT323

RHU002N06_SOT323

D

S

D

S

13

S

G

2

G

ALS_EN <18>

ICH_SMBCLK ICH_SMBDATA

R241 0_0402_5%@R241 0_0402_5%@ R243 0_0402_5%@R243 0_0402_5%@

9/21

+3VM

12

R250

R249

10K_0402_5%@

H_STP_PCI#<16> H_STP_CPU#<16>

VGATE<42>

Change R251 to CH751. 10/04

LAN_PHYPC<24,25,33>

10K_0402_5%@

Change in 7/13

R262 0_0402_5%@R262 0_0402_5%@ R325 100K_0402_5% @R325 100K_0402_5% @

Reserve in 10/08.

D40 CH751H-40_SC76

R268 10K_0402_5%R268 10K_0402_5%

1 2

for Intel LAN_PHYPC glitch issue 5/7

Add EXP_RST# in 10/09.

1 2

+3VS

R275 8.2K_0402_5% R275 8.2K_0402_5%

R276 1K_0402_5% @R276 1K_0402_5% @

1 2

ICH_SMB_DATA ICH_SMB_CLKICH_SMBCLK

1 2

KBC_SPI_CLK_R<33> KBC_SPI_CS0#_R<33> KBC_SPI_CS1#_R<33>

KBC_SPI_CS1#<20>

KBC_SPI_SI_R<33>

KBC_SPI_SO<33>

WXMIT_OFF#<26>

WEBCAM_ON/OFF#<18>

+3VALW

12

R280

Q12

Q12 RHU002N06_SOT323

RHU002N06_SOT323

D

13

D

S

D

S

13

2

Q13

G

RHU002N06_SOT323

2

ICH_SMB_DATA

D

ICH_SMB_CLK

13

Q15

Q15 RHU002N06_SOT323

RHU002N06_SOT323

2

+3VS +3VALW

Change design in 10/08.

R332 0_0402_5%R332 0_0402_5%

4

2.2K_0402_5%

12 12

LPC_PD#<32>

XDP_DBRESET#<4>

PM_BMBUSY#<8>

R253 0_0402_5%R253 0_0402_5%

1 2

PM_CLKRUN#<27,32,33>

PCIE_WAKE#<26>

THERM_SCI#<4>

1 2 1 2

RUNSCI_EC#<33>

21

LID_SW#<18,19,33>

CLKSATAREQ#<16>

EXP_RST<26>

SB_SPKR<28>

MCH_ICH_SYNC#<8>

ICH_RSVD<21>

ISO_PREP#

PCIE_RXN2<26> PCIE_RXP2<26> PCIE_TXN2<26> PCIE_TXP2<26>

PCIE_RXN3<26> PCIE_RXP3<26> PCIE_TXN3<26> PCIE_TXP3<26>

PCIE_RXN4<26> PCIE_RXP4<26> PCIE_TXN4<26>

PCIE_TXP4<26> ICH_SMB_DATA <26> ICH_SMB_CLK <26>

GLAN_RXN<24>

GLAN_RXP<24>

GLAN_TXN<24>

GLAN_TXP<24>

BT_OFF<31>

XMIT_OFF#<26>

FPR_OFF<32>

4

+3VALW

12

R235

R236

2.2K_0402_5%

2.2K_0402_5% ICH_SMB_CLK

ICH_SMB_DATA LINKALERT# ME__EC_CLK1 ME__EC_DATA1

ICH_RI#

XDP_DBRESET# PM_BMBUSY# GPIO11 H_STP_PCI#

R_STP_CPU# PM_CLKRUN# PCIE_WAKE#

SIRQ

SIRQ<27,32,33>

THERM_SCI# VRMPWRGD

PAD

T54

OCP#<44>

LAN_STATUS#_DLAN_STATUS#

ISO_PREP#

LAN_PHYPC_R ALS_EN#

GPIO18

T95PAD T95PAD

GPIO22

T55PAD T55PAD T96PAD T96PAD

GPIO38 GPIO39

T107PAD T107PAD

EXP_RST

T116PAD T116PAD

GPIO57

SB_SPKR MCH_ICH_SYNC# ICH_RSVD

T56PAD T56PAD T57PAD T57PAD T58PAD T58PAD

Add R626, R627 for iTPM test. 12/11

C227 0.1U_0402_16V4Z

1 2

C228 0.1U_0402_16V4Z

1 2

C229 0.1U_0402_16V4Z

1 2

C230 0.1U_0402_16V4Z

1 2

C231 0.1U_0402_16V4Z

1 2

C232 0.1U_0402_16V4Z

1 2

C233 0.1U_0402_16V4Z C233 0.1U_0402_16V4Z

1 2

C234 0.1U_0402_16V4Z C234 0.1U_0402_16V4Z

1 2

R285 15_0402_5%

1 2

R286 15_0402_5%

1 2

R290 15_0402_5%

1 2

R289 15_0402_5%

1 2

R291 0_0402_5%R291 0_0402_5%

1 2

12

R293

22.6_0402_1%

1 2

R328 0_0402_5%R328 0_0402_5%

Reserve for DB1 test. 10/05

U8C

C18

SMBCLK

C15

SMBDATA

B21

LINKALERT#/GPIO60/CLGPIO4

E18

SMLINK0

A24

SMLINK1

C20

RI#

T5

SUS_STAT#/LPCPD#

C25

SYS_RESET#

L2

PMSYNC#/GPIO0

A23

SMBALERT#/GPIO11

B15

STP_PCI#/GPIO15

A20

STP_CPU#/GPIO25

M5

CLKRUN#/GPIO32

C21

WAKE#

L4

SERIRQ

AD20

THRM#

B24

VRMPWRGD

A19

TP12

AE16

GPIO1

AE18

GPIO6

AD18

GPIO7

B25

GPIO8

C14

GPIO12

D20

GPIO13

AE17

GPIO17

K3

GPIO18

AC8

GPIO20

AC19

SCLOCK/GPIO22

D17

GPIO27

E20

GPIO28

M4

SATACLKREQ#/GPIO35

AB18

SLOAD/GPIO38

AC18

SDATAOUT0/GPIO39

AB19

SDATAOUT1/GPIO48

AC20

GPIO49

A16

GPIO57/CLGPIO5

K4

SPKR

AB20

MCH_SYNC#

C19

TP3

AB17

TP8

AC17

TP9

AD17

TP10

ICH9-M SFF ES_FCBGA569

PCIE_RXN2 PCIE_RXP2 PCIE_C_TXN2 PCIE_C_TXP2

PCIE_RXN3 PCIE_RXP3 PCIE_C_TXN3 PCIE_C_TXP3

PCIE_RXN4 PCIE_RXP4 PCIE_C_TXN4 PCIE_C_TXP4

GLAN_RXN GLAN_RXP GLAN_TXN_C GLAN_TXP_C

KBC_SPI_CLK KBC_SPI_CS0# KBC_SPI_CS1#

KBC_SPI_SI

USB_OC#0 USB_OC#1 USB_OC#2 WXMIT_OFF# USB_OC#4 USB_OC#5 USB_OC#6 USB_OC#7

XMIT_OFF#

USBRBIAS

Within 500 mils

U8D

T25

PERN1

T24

PERP1

R24

PETN1

R23

PETP1

P25

PERN2

P24

PERP2

P21

PETN2

P22

PETP2

N23

PERN3

N24

PERP3

M21

PETN3

M22

PETP3

M25

PERN4

M24

PERP4

L24

PETN4

L23

PETP4

K24

PERN5

K25

PERP5

K21

PETN5

K22

PETP5

H24

PERN6/GLAN_RXN

H25

PERP6/GLAN_RXP

J24

PETN6/GLAN_TXN

J23

PETP6/GLAN_TXP

E24

SPI_CLK

E23

SPI_CS0#

F23

SPI_CS1#/GPIO58/CLGPIO6

F22

SPI_MOSI

G23

SPI_MISO

P4

OC0#/GPIO59

N4

OC1#/GPIO40

N1

OC2#/GPIO41

P5

OC3#/GPIO42

P1

OC4#/GPIO43

P2

OC5#/GPIO29

M3

OC6#/GPIO30

M2

OC7#/GPIO31

P3

OC8#/GPIO44

R1

OC9#/GPIO45

R4

OC10#/GPIO46

R2

OC11#/GPIO47

AE5

USBRBIAS

AD5

USBRBIAS#

ICH9-M SFF ES_FCBGA569

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

SATA0GP/GPIO21 SATA1GP/GPIO19 SATA4GP/GPIO36 SATA5GP/GPIO37

SATA

GPIO

SATA

GPIO

SMB

Clocks

S4_STATE#/GPIO26

DPRSLPVR/GPIO16

SYS GPIO

Power MGTController Link

GPIO

MEM_LED/GPIO24

GPIO10/SUS_PWR_ACK

GPIO14/AC_PRESENT

WOL_EN/GPIO9

MISC

DMI0RXN DMI0RXP DMI0TXN

DMI0TXP

DMI1RXN

WLAN

EXP

WWAN

3

DMI1RXP DMI1TXN

DMI1TXP

DMI2RXN DMI2RXP DMI2TXN

DMI2TXP

DMI3RXN DMI3RXP DMI3TXN

DMI3TXP

DMI_CLKN

PCI-Express

DMI_CLKP

Direct Media Interface

DMI_ZCOMP

DMI_IRCOMP

USBP0N USBP1N

GLAN

USBP2N USBP3N USBP4N USBP5N

SPI

USBP6N

USB

USBP7N USBP8N USBP9N

USBP10N USBP10P USBP11N USBP11P

2006/02/13 2006/03/10

PM_PWROK <8,33,42,43>

AE19 AA18 AE20 AA20

K1

CLK14

AB5

CLK48

R3

SUSCLK

D18

SLP_S3#

B20

SLP_S4#

D16

SLP_S5#

E14 D23

PWROK

M1 C16

BATLOW#

U4

PWRBTN#

D22

LAN_RST#

D19

RSMRST#

U1

CK_PWRGD

T4

CLPWROK

B23

SLP_M#

C22

CL_CLK0

A18

CL_CLK1

E22

CL_DATA0

B18

CL_DATA1

F21

CL_VREF0

A17

CL_VREF1

C17

CL_RST0#

B17

CL_RST1#

A22 E16 A15 D21

DMI_RXN0

V25

DMI_RXP0

V24

DMI_TXN0

U24

DMI_TXP0

U23

DMI_RXN1

W23

DMI_RXP1

W24

DMI_TXN1

V21

DMI_TXP1

V22

DMI_RXN2

Y24

DMI_RXP2

Y25

DMI_TXN2

Y21

DMI_TXP2

Y22

DMI_RXN3

AB24

DMI_RXP3

AB25

DMI_TXN3

AA23

DMI_TXP3

AA24

CLK_PCIE_ICH#

T21

CLK_PCIE_ICH

T22 AB21

AB22 AE2

AD1

USBP0P

AD3 AD4

USBP1P

AC2 AC3

USBP2P

AC5 AB4

USBP3P

AB2 AB1

USBP4P

AA3 AA2

USBP5P

Y1 Y2

USBP6P

W2 W3

USBP7P

V1 V2

USBP8P

Y5 Y4

USBP9P

U3 U2 V4 V5

2

Change HDD_HALTLED from GPIO18 to GPIO19. 11/26

GPIO21

HDD_HALTLED

NPCI_RST# GPIO37

CLK_14M_ICH CLK_48M_ICH

ICH_SUSCLK SLP_S3#

SLP_S4# SLP_S5#

S4_STATE# PM_PWROK_R DPRSLPVR ICH_LOW_BAT#

RSMRST# CK_PWRGD_R M_PWROK

CL_CLK0 CL_CLK1

CL_DATA0 CL_DATA1

CL_VREF0_ICH CL_VREF1_ICH

CL_RST# CL_RST#1

SUS_PWR_ACK AC_PRESENT

R256 0_0402_5%R256 0_0402_5% D9 CH751H-40_SC76

D9 CH751H-40_SC76

R263 10K_0402_5%R263 10K_0402_5% R265 0_0402_5%R265 0_0402_5%

Add WOL_EN back. 10/10

DMI_IRCOMP

USB20_N0 <31> USB20_P0 <31>

USB20_N2 <26> USB20_P2 <26> USB20_N3 <26> USB20_P3 <26> USB20_N4 <31> USB20_P4 <31> USB20_N5 <31> USB20_P5 <31> USB20_N6 <31> USB20_P6 <31> USB20_N7 <26> USB20_P7 <26> USB20_N8 <32> USB20_P8 <32>

USB20_N9 <34>

USB20_P9 <34>

USB20_N10 <18>

Pin connection error, modify in 10/24.

Compal Secret Data

USB20_P10 <18>

Deciphered Date

HDD_HALTLED <19>

NPCI_RST# <33>

CLK_14M_ICH <16> CLK_48M_ICH <16>

T53 PADT53 PAD

SLP_S3# <24,26,28,33,35,36,38,41,42,44> SLP_S4# <36,40> SLP_S5# <36>

S4_STATE# <31>

R254 10K_0402_5%@ R254 10K_0402_5%@

1 2 1 2 2 1

ON/OFFBTN# <30> LAN_DISABLE_N <33>

1 2 1 2

M_PWROK <8,35> PM_SLP_M# <33,36,40,41>

CL_CLK0 <8>

CL_CLK1 <26>

CL_DATA0 <8>

CL_DATA1 <26>

CL_RST# <8>

CL_RST#1 <26>

SUS_PWR_ACK <33> AC_PRESENT <33> LAN_WOL_EN <33,36>

DMI_RXN0 <8> DMI_RXP0 <8> DMI_TXN0 <8> DMI_TXP0 <8>

DMI_RXN1 <8> DMI_RXP1 <8> DMI_TXN1 <8> DMI_TXP1 <8>

DMI_RXN2 <8> DMI_RXP2 <8> DMI_TXN2 <8> DMI_TXP2 <8>

DMI_RXN3 <8> DMI_RXP3 <8> DMI_TXN3 <8> DMI_TXP3 <8>

CLK_PCIE_ICH# <16> CLK_PCIE_ICH <16>

R284 24.9_0402_1% R284 24.9_0402_1%

1 2

Reserve R254 at 9/19.

R366 0_0402_5%R366 0_0402_5%

MB

EXPRESS WLAN

MB MB Bluetooth WWAN Fingerprint DOCK USB Camera

2

1 2

PM_RSMRST# <33> CK_PWRGD <16>

1

VRMPWRGD

13

D

S

Q63

RHU002N06_SOT323

R595 10K_0402_5%

R596 0_0402_5%R596 0_0402_5%

2

G

1

C547

0.1U_0402_16V4Z @

2

1 2

+3VS

CLK_ENABLE# <42>

Add for find tune timing.(If have glich issue)

+3VL

R257

R257 100K_0402_5%

PM_DPRSLPVR <8,42>

LOW_BAT# <33>

12

1

R274

2

453_0402_1%

C225

0.1U_0402_16V4Z

12

1

R278

2

C226

453_0402_1%

0.1U_0402_16V4Z

LANLINK_STATUS#<24,25,33>

Within 500 mils

+1.5VS

R271

3.24K_0402_1%

1 2

R277

3.24K_0402_1%

3.24K_0402_1% 1 2

Add in 10/04.

100K_0402_5%

1 2

RPGOOD <39>

+3VM

U10

4

G

2

R294 10K_0402_5%

13

D

S

D

S

Q17

Q17 RHU002N06_SOT323

RHU002N06_SOT323

5

1

P

IN1

O

2

IN2

G

SN74AHC1G08DCKR_SC70

3

12

LAN_STATUS#

+3VM_LAN+3VALW

SLP_S3#

+3VALW

Place closely pin H1Place closely pin AF3

CLK_14M_ICHCLK_48M_ICH

12

@

@ R239

R239 10_0402_5%

10_0402_5%

@

1

C223

4.7P_0402_50V8C

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, M/B LA-4021P

401554

1

12

@

@ R240

R240 10_0402_5%

10_0402_5%

@

1

C224

4.7P_0402_50V8C

2

22 36Wednesday, June 03, 2009

of

B

5

+RTCVCC

C235

R295

C235

0.1U_0402_16V4Z

D D

+1.5VS

1 2

BLM18PG181SN1D_0603

+5VS +3VS +3VALW+5VALW

21

12

D11

1

9/19

2

R301

1 2

R302

D11 CH751H-40_SC76

CH751H-40_SC76

ICH_V5REF_RUN

20 mils

C251

C251 1U_0603_10V4Z

1U_0603_10V4Z

R300

1 2

MBK1608301YZF 0603

+1.5VS_USBPLL

1

2

C265

0.1U_0402_16V4Z

+1.5VS

1

2

C268

0.1U_0402_16V4Z

5

1U_0603_10V4Z

1

2

C266

0.1U_0402_16V4Z

R303

R303 MBK1608301YZF 0603

MBK1608301YZF 0603

1 2

R298

100_0402_5%

C C

+1.5VS

B B

+1.5VS MBK1608301YZF 0603

MBK1608301YZF 0603

+3VM_WOL

1 2

MBK1608301YZF 0603

A A

1

C236

2

1

+

2

C242

220U_D2_4VM_R15

R299

10_0402_5%

1

2

C257

C256

10U_0805_10V4Z

C267

0.1U_0402_16V4Z

10U_0805_10V4Z

20 mils

+1.5VS_PCIE_ICH

0.1U_0402_16V4Z

40 mils

1

2

C239

C240

10U_0805_10V4Z

12

+1.5VS

12

+1.5VS_PCIE_ICH

1

2

C269

ICH_V5REF_RUN ICH_V5REF_SUS

1

2

C241

10U_0805_10V4Z

2.2U_0603_6.3V4Z

21

D12

D12 CH751H-40_SC76

CH751H-40_SC76

ICH_V5REF_SUS

20 mils

1

C252

0.1U_0402_16V4Z

2

+1.5VS_VCCSATAPLL

1

2

C258

1U_0603_10V4Z

1

2

C259

1U_0603_10V4Z

1

2

C263

0.1U_0402_16V4Z

VCC_LAN1_05_INT_ICH

+1.5VS_GLAN

1

+3VS

2

C270

10U_0805_10V4Z

4

U8F

G17

VCCRTC

G7

V5REF

U7

V5REF_SUS

J19

VCC1_5_B[01]

K18

VCC1_5_B[02]

K19

VCC1_5_B[03]

L18

VCC1_5_B[04]

L19

VCC1_5_B[05]

M18

VCC1_5_B[06]

M19

VCC1_5_B[07]

N18

VCC1_5_B[08]

N19

VCC1_5_B[09]

P18

VCC1_5_B[10]

R18

VCC1_5_B[11]

T18

VCC1_5_B[12]

T19

VCC1_5_B[13]

U18

VCC1_5_B[14]

U19

VCC1_5_B[15]

W17

VCCSATAPLL

U13

VCC1_5_A[01]

V13

VCC1_5_A[02]

W13

VCC1_5_A[03]

U12

VCC1_5_A[04]

V12

VCC1_5_A[05]

W12

VCC1_5_A[06]

W10

VCC1_5_A[07]

U15

VCC1_5_A[08]

V15

VCC1_5_A[09]

W18

VCC1_5_A[10]

G9

VCC1_5_A[11]

H9

VCC1_5_A[12]

V11

VCC1_5_A[13]

U11

VCC1_5_A[14]

U8

VCCUSBPLL

T9

VCC1_5_A[15]

U9

VCC1_5_A[16]

G11

VCCLAN1_05[1]

H11

VCCLAN1_05[2]

G12

VCCLAN3_3[1]

H13

VCCLAN3_3[2]

J17

VCCGLANPLL

H19

VCCGLAN1_5[1]

J18

VCCGLAN1_5[2]

K16

VCCGLAN3_3

ICH9-M SFF ES_FCBGA569

4

CORE

VCCA3GP ATXARX USB CORE

VCCP_CORE

PCI

VCCSUSHDA

VCCSUS1_05[1] VCCSUS1_05[2]

VCCSUS1_5[1] VCCSUS1_5[2]

VCCSUS3_3[01] VCCSUS3_3[02] VCCSUS3_3[03]

VCCPSUSVCCPUSB

VCCSUS3_3[04] VCCSUS3_3[05]

VCCSUS3_3[06] VCCSUS3_3[07] VCCSUS3_3[08] VCCSUS3_3[09] VCCSUS3_3[10] VCCSUS3_3[11] VCCSUS3_3[12] VCCSUS3_3[13] VCCSUS3_3[14] VCCSUS3_3[15] VCCSUS3_3[16]

VCCCL3_3[1] VCCCL3_3[2]

GLAN POWER

VCC1_05[01] VCC1_05[02] VCC1_05[03] VCC1_05[04] VCC1_05[05] VCC1_05[06] VCC1_05[07] VCC1_05[08] VCC1_05[09] VCC1_05[10] VCC1_05[11] VCC1_05[12] VCC1_05[13] VCC1_05[14] VCC1_05[15] VCC1_05[16]

VCCDMIPLL VCC_DMI[1]

VCC_DMI[2]

V_CPU_IO[1] V_CPU_IO[2]

VCC3_3[01] VCC3_3[02]

VCC3_3[03] VCC3_3[04] VCC3_3[05]

VCC3_3[06] VCC3_3[07] VCC3_3[08]

VCCHDA

VCCCL1_05

VCCCL1_5

L11 L12 L13 L14 L15 M11 M15 N11 N15 P11 P15 R11 R12 R13 R14 R15

P19 T17

U17 V16

U16 V18 AE9

AA9 V14 W14

G8 H7 H8

AD7 V10 T7

H15 H16 V7

G14 G15 H14

W8 J7

J8 K7 K8 L7 L8 M7 M8 N7 N8 P7 P8

G18 H17 J14

K14

+VCCP

+1.5VS_DMIPLL

VCCSUS1_05_ICH_1 VCCSUS1_05_ICH_2

VCCSUS1_5_ICH_1 VCCSUS1_5_ICH_2

VCCCL1_05_ICH

1 2

C264 1U_0603_10V4ZC264 1U_0603_10V4Z

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

1

2

C238

C237

0.1U_0402_16V4Z

1

2

C243

0.01U_0402_16V7K

9/29

VCC_DMI

(DMI)

+3VS

1

2

C253

0.1U_0402_16V4Z

T59T59 T60T60

T61T61 T62T62

+3VALW

1

2

C262

4.7U_0805_10V4Z

9/21

C217

0.1U_0402_16V4Z

0.1U_0402_16V4Z 1 2

+3VM_WOL

9/21

3

R296

1 2

MBK1608301YZF 0603

1

2

C244

10U_0805_10V4Z

1 2

MBK1608301YZF 0603

0.1U_0402_16V4Z

1

2

C248

1

2

C255

0.1U_0402_16V4Z

1

2

C260

0.1U_0402_16V4Z

9/29

+1.5VS

VCC_DMI

1

2

C245

1U_0603_10V4Z

R297

1

2

C249

+3VALW

0.1U_0402_16V4Z

9/29

+3VS

0.1U_0402_16V4Z

0.1U_0402_16V4Z 1

2

C250

+3VALW

1

2 C261

C261

2006/02/13 2006/03/10

1U_0603_10V4Z

+VCCP

0.1U_0402_16V4Z

+3VS

1

2

C254

0.1U_0402_16V4Z

Compal Secret Data

Deciphered Date

1

2

C246

+VCCP

4.7U_0805_10V4Z

4.7U_0805_10V4Z 1

2

C247

2

U8E

B4

VSS[001]

B7

VSS[002]

B10

VSS[003]

B13

VSS[004]

B16

VSS[005]

B19

VSS[006]

B22

VSS[007]

D2

VSS[008]

D24

VSS[009]

E5

VSS[010]

E7

VSS[011]

E9

VSS[012]

E11

VSS[013]

E13

VSS[014]

E15

VSS[015]

E17

VSS[016]

E19

VSS[017]

E21

VSS[018]

F24

VSS[019]

G2

VSS[020]

G5

VSS[021]

G10

VSS[022]

G13

VSS[023]

G16

VSS[024]

G19

VSS[025]

G21

VSS[026]

H10

VSS[027]

H12

VSS[028]

H18

VSS[029]

H23

VSS[030]

J5

VSS[031]

J9

VSS[032]

J10

VSS[033]

J11

VSS[034]

J12

VSS[035]

J13

VSS[036]

J15

VSS[037]

J21

VSS[038]

J22

VSS[039]

J25

VSS[040]

K2

VSS[041]

K9

VSS[042]

K10

VSS[043]

K11

VSS[044]

K12

VSS[045]

K13

VSS[046]

K15

VSS[047]

K17

VSS[048]

K23

VSS[049]

L5

VSS[050]

L9

VSS[051]

L10

VSS[052]

L16

VSS[053]

L17

VSS[054]

L21

VSS[055]

L22

VSS[056]

L25

VSS[057]

M9

VSS[058]

M10

VSS[059]

M12

VSS[060]

M13

VSS[061]

M14

VSS[062]

M16

VSS[063]

M17

VSS[064]

M23

VSS[065]

N2

VSS[066]

N5

VSS[067]

N9

VSS[068]

N10

VSS[069]

N12

VSS[070]

N13

VSS[071]

N14

VSS[072]

N16

VSS[073]

N17

VSS[074]

N21

VSS[075]

N22

VSS[076]

N25

VSS[077]

P9

VSS[078]

P10

VSS[079]

P12

VSS[080]

P13

VSS[081]

P14

VSS[082]

P16

VSS[083]

P17

VSS[084]

P23

VSS[085]

R5

VSS[086]

R7

VSS[087]

R8

VSS[088]

R9

VSS[089]

R10

VSS[090]

R16

VSS[091]

R17

VSS[092]

R19

VSS[093]

R21

VSS[094]

R22

VSS[095]

R25

VSS[096]

T2

VSS[097]

T8

VSS[098]

T10

VSS[099]

T11

VSS[100]

T12

VSS[101]

T13

VSS[102]

T14

VSS[103]

T15

VSS[104]

T16

VSS[105]

T23

VSS[106]

ICH9-M SFF ES_FCBGA569

2

1

U5

VSS[107]

U10

VSS[108]

W11

VSS[109]

U14

VSS[110]

W16

VSS[111]

U21

VSS[112]

U22

VSS[113]

U25

VSS[114]

V3

VSS[115]

V8

VSS[116]

V19

VSS[117]

V23

VSS[118]

W1

VSS[119]

W4

VSS[120]

W5

VSS[121]

W7

VSS[122]

W9

VSS[123]

W15

VSS[124]

W19

VSS[125]

W21

VSS[126]

W22

VSS[127]

W25

VSS[128]

Y3

VSS[129]

Y23

VSS[130]

AA1

VSS[131]

AA4

VSS[132]

AA6

VSS[133]

AA8

VSS[134]

AA11

VSS[135]

AA13

VSS[136]

AA15

VSS[137]

AA16

VSS[138]

AA17

VSS[139]

AA19

VSS[140]

AA21

VSS[141]

AA22

VSS[142]

AA25

VSS[143]

AB3

VSS[144]

AB9

VSS[145]

AB11

VSS[146]

AB13

VSS[147]

AB15

VSS[148]

AC24

VSS[149]

AC1

VSS[150]

AC4

VSS[151]

AC10

VSS[152]

AC12

VSS[153]

AC14

VSS[154]

AD2

VSS[155]

AD6

VSS[156]

AD9

VSS[157]

AD16

VSS[158]

AD19

VSS[159]

AD22

VSS[160]

AE3

VSS[161]

AE4

VSS[162]

AE11

VSS[163]

AE13

VSS[164]

AE15

VSS[165]

V17

VSS[166]

AE8

VSS[167]

V9

VSS[168]

J16

VSS[169]

ICHGND1

VSS_NCTF[01] VSS_NCTF[02] VSS_NCTF[03] VSS_NCTF[04]

A1 A25 AE1 AE25

Title

Size Document Number Rev

Custom

401554

Date: Sheet

R358 0_0402_5%@R358 0_0402_5%@ ICHGND2 ICHGND3 ICHGND4

1 2

R361 0_0402_5%@R361 0_0402_5%@

1 2

R368 0_0402_5%@R368 0_0402_5%@

1 2

R399 0_0402_5%@R399 0_0402_5%@

1 2

Compal Electronics, Inc.

SCHEMATIC, M/B LA-4021P

+3VS

R247

ICHGND1

RHU002N06_SOT323

+3VS

R414

ICHGND3

RHU002N06_SOT323

ICHGND2

RHU002N06_SOT323

ICHGND4

RHU002N06_SOT323

CRACK_BGA<13,33>

1

Q72

1 2

Q73

+3VS

R488

Q74

+3VS

R491

100K_0402_5%

2

G

100K_0402_5%

100K_0402_5% 2

G

1 2

2

G

1 2

Q75

23 36Wednesday, June 03, 2009

CRACK_BGA

13

D

S

CRACK_BGA

13

D

S

CRACK_BGA

13

100K_0402_5%

D

S

13

100K_0402_5%

D

2

G

S

CRACK_BGA

of

B

5

4

3

2

1

+3VM_WOL +3VM_LAN

R305

R305 1M_0402_5%

D D

LAN_PHYPC

ADP_PRES<33,36,38>

SLP_S3#<22,26,28,33,35,36,38,41,42,44>

C C

Add R309 back. 9/29

B B

Change R315 to 1K and R316 to 10K. 10/10

2

G

GLAN_RXP<22> GLAN_RXN<22>

GLAN_TXP<22> GLAN_TXN<22>

1M_0402_5%

1 2

13

D

Q20

2

BSS138_SOT23

G

S

13

D

Q21

RHU002N06_SOT323@

S

13

D

Q22

2

G

S

C279 0.1U_0402_16V7KC279 0.1U_0402_16V7K C280 0.1U_0402_16V7KC280 0.1U_0402_16V7K

GLAN_CLK<21>

LAN_RSTSYNC<21>

LANLINK_STATUS#<22,25,33>

R306

R306 100K_0402_5%

100K_0402_5%

R308 0_0402_5%R308 0_0402_5%

RHU002N06_SOT323 @

1 2 1 2

LAN_TXD0<21> LAN_TXD1<21> LAN_TXD2<21>

LAN_RXD0<21> LAN_RXD1<21> LAN_RXD2<21>

LAN_ACT#<25>

LAN_PHYPC<22,25,33>

R304 0_1206_5%@R304 0_1206_5%@

1 2

Q18

Q18 SI2301BDS_SOT23

SI2301BDS_SOT23

S

D

13

G

2

C272

1

1 2

R309 33_0402_5%R309 33_0402_5%

R312 4.99K_0402_1%R312 4.99K_0402_1%

1 2

R313 0_0402_5%@ R313 0_0402_5%@

1 2

R315 1K_0402_5%

R316 10K_0402_5%R316 10K_0402_5%

+3VM_LAN +3VM_LAN

1000P_0402_50V7K

1 2

LANLINK_STATUS# LAN_ACT#

12

IEEE_TEST_P IEEE_TEST_N

LAN_PHYPC

1 2

10U_0805_10V4Z

GLAN_RXP_C GLAN_RXN_C

GLANCLK

XTAL2 XTAL1

R617 1K_0402_5%@R617 1K_0402_5%@ R618 200_0402_5%@R618 200_0402_5%@

R317 200_0402_5%@R317 200_0402_5%@

C271

1 2 1 2

1 2

1

2

U9

U9 52 53

55 56

45 50

42 43 44

47 48 49

4 2 1

15

12 13

34 37 36

9

10

Add R638 & Q84. 3/21

12

R638

R638 470_0402_5%

470_0402_5%

13

D

2

G

S

Y3

25MHZ_20P_1BG25000CK1A

1 2

2

C277

C277 27P_0402_50V8J

27P_0402_50V8J

1

GLAN_TXP GLAN_TXN

GLAN_RXP GLAN_RXN

JKCLK JRSTSYNC

JTXD_0 JTXD_1 JTXD_2

JRXD_0 JRXD_1 JRXD_2

LED_0 LED_1 LED_2

RSET

IEEE_TEST_P IEEE_TEST_N

DIS_REG10 LAN_DISABLE_N TEST_EN XTAL2

XTAL1

Q84

Q84 RHU002N06_SOT323

RHU002N06_SOT323

Y3

2

1

VDDO_33_3

VDDO_33_46

AVDD_33_28

DVDD_10_5

DVDD_10_8 DVDD_10_33 DVDD_10_38

AVDD_18_11 AVDD_18_14 AVDD_18_19 AVDD_18_18 AVDD_18_24 AVDD_18_25 AVDD_18_41 AVDD_18_54 AVDD_18_32 AVDD_18_30

RESERVED_NC

GND_PAD

JTAG_TMS39JTAG_TCK40JTAG_TRST35JTAG_TDI7JTAG_TDO

82567LF_QFN56_8X8~D

6

R318 200_0402_5%@R318 200_0402_5%@

XTAL1

XTAL2

C278

C278 27P_0402_50V8J

27P_0402_50V8J

MDI_N_0

MDI_P_0

MDI_N_1

MDI_P_1

MDI_N_2

MDI_P_2

MDI_N_3

MDI_P_3

CTRL18 CTRL10

26 27

22 23

20 21

16 17

R310 0_0603_5%R310 0_0603_5%

3 46 28

+V1.0M_LAN

5 8 33 38

11 14 19 18 24

+1.8VM_LAN

25 41 54 32 30

LAN_CTRL_18

29 31

51

57

T65PAD T65PAD T67PAD T67PAD

12

1 2

R314

R314 0_0603_5%

0_0603_5%

1 2

+3VM_LAN_R

LAN_CTRL_18

LAN_MDI0N <25>

LAN_MDI0P <25>

LAN_MDI1N <25>

LAN_MDI1P <25>

LAN_MDI2N <25>

LAN_MDI2P <25>

LAN_MDI3N <25>

LAN_MDI3P <25>

+3VM_LAN

+1.8VM

Change value. 11/06

+3VM_LAN

C273

1

2

C274

2

C288

2

1

0.1U_0402_16V4Z

1

10U_0805_10V4Z

0.1U_0402_16V4Z

C597

C598

2

1

0.1U_0402_16V4Z

470P_0402_50V7K

C281

2

1

C290

2

1

2

C275

1

+V1.0M_LAN

C287

2

1

2

10U_0805_10V4Z

+1.8VM_LAN

C296

1

2

10U_0805_10V4Z

+1.8VM

1

C276

2

0.1U_0402_16V4Z

10U_0805_6.3V6M

Q19

Q19 BCP69_SOT223

BCP69_SOT223

R307

5.1K_0402_1%

0.1U_0402_16V4Z

0.1U_0402_16V4Z 1 2

C283

C282

2

1

0.1U_0402_16V4Z

C289

11/26

2

Add R597 close to pin3. Add R598 close to pin46.

1

4.7U_0805_10V4Z

C291

C292

2

1

0.1U_0402_16V4Z

470P_0402_50V7K

3

C284

2

1

C293

2

1

4 2

1

C286

C285

2

1

4.7U_0805_10V4Z

C294

C295

2

1

10U_0805_10V4Z

4.7U_0805_10V4Z

A A

5

4

PAD

PAD T68

T68

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/02/13 2006/07/26

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, M/B LA-4021P

401554

1

of

24 36Wednesday, June 03, 2009

of

24 36Wednesday, June 03, 2009

of

24 36Wednesday, June 03, 2009

B

5

4

3

2

1

D D

Swap Q78A,B D & S pin. 2/22

LAN_ACT#_DOCK<34>

LANLINK_STATUS#_DOCK<34>

Q78A

Q78A 2N7002DW-T/R7_SOT363-6

2N7002DW-T/R7_SOT363-6

6 1

2

Q78B

Q78B 2N7002DW-T/R7_SOT363-6

2N7002DW-T/R7_SOT363-6

3

4

5

LAN_ACT#

LAN_LINK_EN

LANLINK_STATUS#

R615

R615 10K_0402_5%

10K_0402_5%

1 2

+3VM_LAN

Delete all termination cause they are already inside BOAZMAN. 9/28

Pin Swap. 10/05 Swap P & N. 10/09

T69

LAN_MDI0P<24>

C C

B B

+1.8VM

LAN_MDI0N<24>

12

C297 0.1U_0402_16V7K

C299 0.1U_0402_16V7K

C304 0.1U_0402_16V7K

C305 0.1U_0402_16V7K

LAN_MDI1P<24>

+1.8VM

LAN_MDI1N<24>

12

LAN_MDI2P<24>

+1.8VM

LAN_MDI2N<24>

12

LAN_MDI3P<24>

+1.8VM

LAN_MDI3N<24>

12

TRM_CT

12

TD4-

11

TD4+

10

TCT4

9

TD3-

8

TD3+

7

TCT3

6

TD2-

5

TD21+

4

TCT2

3

TD1-

2

TD1+

1

TCT1

X'FORM_ NS692405 LAN_24P

1:1

MX4-

MX4+ MCT4

MX3-

MX3+ MCT3

MX2-

MX2+ MCT2

MX1-

MX1+ MCT1

MDO0+

13

Change design. 10/12

MDO0-

14

MCT0

15

MDO1+

16

MDO1-

17

MCT1

18

MDO2+

19

MDO2-

20

MCT2

21

MDO3+

22

MDO3-

23

MCT3

24

C307 0.01U_0402_50V7K

1 2

C308 0.01U_0402_50V7K

1 2

C309 0.01U_0402_50V7K

1 2

C310 0.01U_0402_50V7K

1 2

R319

R319 75_0402_1%

75_0402_1%

R323

R323 75_0402_1%

75_0402_1%

R329

R329 75_0402_1%

75_0402_1%

R330

R330 75_0402_1%

75_0402_1%

12

C306 1000P_1808_3KV7K

12

1 2

JP11

3

MDO3MDO3+ MDO1MDO2MDO2+ MDO1+ MDO0MDO0+

11

Yellow LED+

12

Yellow LED-

8

PR4-

7 6 5 4 3 2 1 9

10

DETECT PIN1

PR4+ PR2PR3PR3+ PR2+ PR1PR1+ Green LED+ Green LED-

SUYIN_100073FR014G303ZL_13P

SUYIN_100073FR014G303ZL_13P CONN@

CONN@

2006/02/13 2006/07/26

15

SHLD1

13

14

SHLD1

Compal Secret Data

R89 0_0402_5%@R89 0_0402_5%@

1 2

Modify JP11 footprint to same as Meson. 10/25

Deciphered Date

20 mil

LAN_PHYPC <22,24,33>

Title

Size Document Number Rev

401554

Date: Sheet

2

Date: Sheet

+3VM_LAN V_3P3_LAN_LED

D

S

D

S

20 mil

R340

R340 100K_0402_5%

100K_0402_5%

PREP#<22,34>

Compal Electronics, Inc.

SCHEMATIC, M/B LA-4021P

13

12

G

Q23

2

FDN338P_SOT23

13

D

Q24

2

2N7002_SOT23

G

S

25 36Wednesday, June 03, 2009

1

B

of

LAN_ACT#

LANLINK_STATUS#

2

3

D44

PACDN042_SOT23~D@

Reserve to

1

prevent ESD issue as other project. 1/18

A A

5

Swap connection of JP11 pin9 & pin10. 11/26

LAN_ACT#<24>

LANLINK_STATUS#<22,24,33>

4

LAN_ACT#

1 2

LANLINK_STATUS#

1 2

V_3P3_LAN_LED

R339 300_0603_5% R339 300_0603_5%

1 2

MDO3-<34>

C311680P_0402_50V7K@ C311680P_0402_50V7K@

C312680P_0402_50V7K@ C312680P_0402_50V7K@

MDO3+<34>

MDO1-<34>

MDO2-<34> MDO2+<34> MDO1+<34>

MDO0-<34> MDO0+<34>

V_3P3_LAN_LED

R341 300_0603_5%

1 2

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date

A

Express Card Slot

+3VS_PEC

1

2

1 1

C322

+1.5VS_PEC

1

2

C328

2 2

+3VALW

R585 100K_0402_5%R585 100K_0402_5%

+3V_PEC

2

C323

0.1U_0402_16V7K

4.7U_0805_10V4Z

1

2

C324

0.1U_0402_16V7K

1

2

C329

0.1U_0402_16V7K

C330 0.1U_0402_16V7KC330 0.1U_0402_16V7K

C331 0.1U_0402_16V7KC331 0.1U_0402_16V7K

C332 0.1U_0402_16V7KC332 0.1U_0402_16V7K

1 2

0.1U_0402_16V7K

4.7U_0805_10V4Z

12

USB20_N2<22> USB20_P2<22>

Disconnect ICH_SMB_CLK & ICH_SMB_DATA 2/20

PCI_PME#<20>

1

2

C325

4.7U_0805_10V4Z

PCIE_RXN3<22> PCIE_RXP3<22>

Express Card Power Switch

+3VS

+3VALW

21

18

NC_CP# CPPE#

PLT_RST#

19

14 15

+1.5VS

SLP_S3#<22,24,28,33,35,36,38,41,42,44>

R342 0_0402_5%R342 0_0402_5% R343 0_0402_5%R343 0_0402_5%

R344

R344 0_0402_5%

0_0402_5%

1 2

U11

U11 TPS2231PWPR_PWP24

TPS2231PWPR_PWP24

5

3.3Vin1

6

3.3Vin2

3.3Vaux_in

1.5Vin1

1.5Vin2

CPUSB# CPPE#

4

STBY# SHDN#3RCLKEN

2

SYSRST#

GND

NC11NC210NC312NC413NC5

11

1 2 1 2

+3V_PEC +3VS_PEC

CLK_PCIE_EXP#<16>

CLK_PCIE_EXP<16>

C326 0.1U_0402_16V7K C326 0.1U_0402_16V7K

1 2

C327 0.1U_0402_16V7K C327 0.1U_0402_16V7K

1 2

PCIE_TXN3<22> PCIE_TXP3<22>

3.3Vout1

3.3Vout2

Aux_out

1.5Vout1

1.5Vout2

OC#

PERST#

24

EXP_RST<22>

+1.5VS_PEC +1.5VS_PEC

+3VS_PEC

7 8

+3V_PEC

20

16 17

23

RCLKEN

22

PERST#

9

RCLKEN have internal PU.

B

USBP2-_R USBP2+_R NC_CP#

PCIE_PME#_R

PERST#

CLKREQA# CPPE#

PCIE_RXN3_R PCIE_RX3P_R

+3VS

R348

@R348

@ 10K_0402_5%

10K_0402_5%

+1.5VS_PEC

5

1 2

CLKREQA#

61

Q25A 2N7002DW-T/R7_SOT363-6

2N7002DW-T/R7_SOT363-6

2

3

Q25B

@Q25B

@

2N7002DW-T/R7_SOT363-6

Q25 & Q26 change to 2 in

4

1 package. 3/17

10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26

27 28

@Q25A

@

JP12

1 2 3 4 5 6 7 8 9

GND-1 USB_DUSB_D+ CPUSB# RSV-5 RSV-6 SMB_CLK SMB_DATA +1.5V-9 +1.5V-10 WAKE# +3.3VAUX PERST# +3.3V-14 +3.3V-15 CLKREQ# CPPE# REFCLKREFCLK+ GND-20 PERn0 PERp0 GND-23 PETn0 PETp0 GND-26

GND-27 GND-28

SANTA_130832-1_LBCONN@

GND-29 GND-30

CLKREQA# <16>

0.01U_0402_16V7K

29 30

CL_CLK1<22>

CL_DATA1<22>

CL_RST#1<22>

resever for shirly peak issue 5/7

MC2_DISABLE<33>

add C615 1000pF per HP request. 3/31

C

+3V_WLAN

1

2

C315

PCIE_RXN2<22> PCIE_RXP2<22>

PCIE_TXN2<22> PCIE_TXP2<22>

Change Power rail same as pin2, 52. 8/16

1

2

C316

0.1U_0402_16V4Z

2/21

1

2

C317

4.7U_0805_10V4Z

CL_CLK1 CL_DATA1 CL_RST#1

R605

C318

0.01U_0402_16V7K

PCIE_WAKE#<22>

CLKREQ_WLAN#<16>

CLK_PCIE_MCARD#<16>

CLK_PCIE_MCARD<16>

PCI_RST#<20,27>

CLK_PCI_DEBUG<16>

R346 0_0402_5%R346 0_0402_5%

1 2

R347 0_0402_5%R347 0_0402_5%

1 2

+3VALW

12

@

10K_0402_5%

1 2

1

C615

C615 1000P_0402_50V7K

1000P_0402_50V7K

@

2

+1.5VS

1

2

1

2

C320

C319

4.7U_0805_10V4Z

0.1U_0402_16V4Z

Mini-Express Card

PCIE_WAKE#

PCI_RST#

PCIE_C_RXN2 PCIE_C_RXP2

+3V_WLAN

R349 0_0402_5%R349 0_0402_5% R350 0_0402_5%R350 0_0402_5% R351 0_0402_5%R351 0_0402_5%

R606

R606 220K_0402_1%

220K_0402_1%

12 12 12

T77 PADT77 PAD

31

2

Q66

Q66 SI2305DS-T1-E3_SOT23-3

SI2305DS-T1-E3_SOT23-3

D

Delete R407, R409, R522, R528, R529, & R530 of LPC for layout improve. 2/21

Del R345 & improve +3V_WLAN. 12/11

JP13

1

3

5

7

9

11

13

15

17

19

21

23

25

27

29

31

33

35

37

39

41

43

45

47

49

51

53

GND1

FOX_AS0B226-S40N-7F

FOX_AS0B226-S40N-7F CONN@

CONN@

+3V_WLAN

Change Q66 from SI2301BDS to SI2305DS. 10/25

GND2

2

2/21

4

6

LPC_FRAME#

8

LPC_AD3

10

10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52

12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52

54

LPC_AD2 LPC_AD1 LPC_AD0

XMIT_D_OFF# PLT_RST#

ICH_SMB_CLK ICH_SMB_DATA

WW_LED# WL_LED# WP_LED#

WW_LED# WP_LED#

XMIT_D_OFF#

Add to prevent leakage issue.

LPC_FRAME# <21,32,33> LPC_AD3 <21,32,33> LPC_AD2 <21,32,33> LPC_AD1 <21,32,33> LPC_AD0 <21,32,33>

PLT_RST# <8,20,32>

ICH_SMB_CLK <22> ICH_SMB_DATA <22>

USB20_N3 <22> USB20_P3 <22>

WL_LED# <19>

R352 0_0402_5%@R352 0_0402_5%@

1 2

R353 0_0402_5%@R353 0_0402_5%@

1 2

2 1

D13 CH751H-40_SC76D13 CH751H-40_SC76

+3V_WLAN

E

+3V_WLAN

+1.5VS

WL_LED#

XMIT_OFF# <22>

+3V_WWAN

Close to JP14

USB20_N7 <22> USB20_P7 <22>

WW_LED# <19>

UIM_DATA

Note2

1

2

C592

39P_0402_50V8J@C592

39P_0402_50V8J

C591

39P_0402_50V8J@C591

39P_0402_50V8J

C590

39P_0402_50V8J@ C590

39P_0402_50V8J

@

S DIO(BR) NUP4301MR6T1 TSOP-6@

JP15

4

GND

5

VPP

6

I/O

7

DET

R367

47K_0402_5%

@

@ 1 2

Note1 Change Power rail same

as pin2, 52. 8/16 Note2

Reserve for 800 & 900MHz EMI issue. 8/16

B

UIM_PWR

TAITW_PMPAT6-06GLBS7N14N0CONN@

U13

1 2

CH1

CH4 Vn CH23CH3

Vp

0.01U_0402_16V7K

6 5 4

VCC RST

CLK

GND GND

Add in 9/27

Mini-Express Card--WWAN

Del BT_COMBO# in 10/12.

3 3

CLKREQG_WWAN#<16> CLK_PCIE_WAN#<16>

CLK_PCIE_WAN<16>

Note1

+3V_WWAN

delete R362~R364, not support Clink on 2008 products to WWAN slot 5/22

4 4

2/22

WMC1_DISABLE<33>

resever for shirly peak issue 5/7

T78 PADT78 PAD T79 PADT79 PAD

PCIE_RXN4<22>

PCIE_RXP4<22>

PCIE_TXN4<22> PCIE_TXP4<22>

R359 0_0603_5%R359 0_0603_5%

1 2 1 2

R360 0_0603_5%R360 0_0603_5%

T80 PADT80 PAD

1000P_0402_50V7K

PCIE_WAKE#

@ C603

@

A

DEL in 9/26

JP14

1

3

5

7

9

9 111112 131314 151516 171718 191920 212122 232324 252526 272728 292930 313132 333334 353536 373738 393940 414142 434344 454546 474748 494950 515152

GND153GND2

MOLEX_67910-5700CONN@

WXMIT_OFF#<22>

+3VALW

12

1

C603

@

2

@

R607

220K_0402_1%

10K_0402_5%

Change Q67 from SI2301BDS to SI2305DS. 10/25

2

4

6

8

10

12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52

54

R608

1 2

2

Del R354 &

+3V_WWAN

improve +3V_WWAN. 12/11

UIM_PWR UIM_DATA UIM_CLK UIM_RST UIM_VPP

M_WXMIT_OFF# PLT_RST#

ICH_SMB_CLK ICH_SMB_DATA

WW_LED# WL_LED#

Add back 9/27

D16

CH751H-40_SC76

Q67

Q67 SI2305DS-T1-E3_SOT23-3

SI2305DS-T1-E3_SOT23-3

31

+3V_WWAN

M_WXMIT_OFF#

21

Change value to 47K. 9/27

+3V_WWAN

ACCELEROMETER

1

2

C333

C335

C334

4.7U_0805_10V4Z

0.1U_0402_16V4Z

+3VS +3VS_ACL +3VS_ACL_IO

+3V_WWAN

D15

DAN217T146_SC59-3@

UIM_PWR

1

UIM_RSTUIM_VPP

2

UIM_CLK

3

1

C336

2

8 9

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

18P_0402_50V8J

@

Issued Date

1

2

C342

4.7U_0805_10V4Z

C

+3V_WWAN

3

1

2

1

2

C343

0.1U_0402_16V4Z

2005/05/26 2006/07/26

+3VS_ACL_IO

+3VS_ACL

Compal Secret Data

Deciphered Date

ACCEL_INT#<20>

ICH_SM_DA<4,22>

ICH_SM_CLK<4,22> R365 10K_0402_5%R365 10K_0402_5%

12

Must be placed in the center of the system.

L

Change U12 part description from LIS302DLTR LGA to HP302DLTR8 as HP change list. 12/03

D

D14

D14 CH751H-40_SC76

CH751H-40_SC76

2 1

1 6

8

12 13 14

7

+3VS_ACL

1

C341

C340

R355

R355 0_0603_5%

0_0603_5%

1 2

U12

LIS302DL

VDD_IO VDD

INT 1 INT 29GND

SDO SDA / SDI / SDO SCL / SPC

CS

HP302DLTR8_LGA14_3X5

2

GND

4

GND

5

GND

10

3

RSVD

11

RSVD

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, M/B LA-4021P

401554

C340

2

+3VS_ACL

E

2

0.1U_0402_16V4Z

10U_0805_6.3V6M

B

of

26 36Wednesday, June 03, 2009

of

26 36Wednesday, June 03, 2009

of

26 36Wednesday, June 03, 2009

5

U14

PCI_AD[0..31]<20>

+3VS

D D

12

R369

68K_0402_5%

CBS_GRST#

@

1

C358

C358 1U_0603_10V4Z

1U_0603_10V4Z

2

7/2: change R369 from 100K to 68K & reserve C358

C C

R372

R372 100_0402_5%

100_0402_5%

PCI_AD22 CBS_IDSEL

1 2

Layout Note: Add GND shield.

CLK_PCI_1394<16>

PM_CLKRUN#<22,32,33>

B B

CLK_PCI_1394

12

R370

10_0402_5%

@

2

C359

1

4.7P_0402_50V8C

@

PCI_CBE#3<20> PCI_CBE#2<20> PCI_CBE#1<20> PCI_CBE#0<20>

PCI_PAR<20> PCI_FRAME#<20> PCI_TRDY#<20> PCI_IRDY#<20> PCI_STOP#<20> PCI_DEVSEL#<20>

PCI_PERR#<20> PCI_SERR#<20,33>

PCI_REQ2#<20> PCI_GNT2#<20>

PCI_RST#<20,26>

R378 10K_0402_5%@R378 10K_0402_5%@

1 2

R380 0_0402_5%R380 0_0402_5%

1 2

R381 10K_0402_5%

1 2

+3VS

PCI_PIRQE#<20> PCI_PIRQG#<20>

R384 10K_0402_5%R384 10K_0402_5%

+3VS

1 2

PCI_AD31 PCI_AD30 PCI_AD29 PCI_AD28 PCI_AD27 PCI_AD26 PCI_AD25 PCI_AD24 PCI_AD23 PCI_AD22 PCI_AD21 PCI_AD20 PCI_AD19 PCI_AD18 PCI_AD17 PCI_AD16 PCI_AD15 PCI_AD14 PCI_AD13 PCI_AD12 PCI_AD11 PCI_AD10 PCI_AD9 PCI_AD8 PCI_AD7 PCI_AD6 PCI_AD5 PCI_AD4 PCI_AD3 PCI_AD2 PCI_AD1 PCI_AD0

PCI_CBE#3 PCI_CBE#2 PCI_CBE#1 PCI_CBE#0

PCI_PAR PCI_FRAME# PCI_TRDY# PCI_IRDY# PCI_STOP# PCI_DEVSEL#

PCI_PERR# PCI_SERR#

PCI_REQ2# PCI_GNT2#

CLK_PCI_1394 CBS_GRST#

PME#

U14

125

AD31

126

AD30

127

AD29

1

AD28

2 3 5 6

9 11 12 14 15 17 18 19 36 37 38 39 40 42 43 44 46 47 48 49 50 51 52 53

7 21 35 45

33 23 25 24 29 26

8 30 31

124 123

121 119

71

117

70

115 116

69 66

99

102 103 107 111

97

R5C833-TQFP128P_TQFP128_14X14~D

AD27 AD26 AD25 AD24 AD23 AD22 AD21 AD20 AD19 AD18 AD17 AD16 AD15 AD14 AD13 AD12 AD11 AD10 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0

C/BE3# C/BE2# C/BE1# C/BE0#

PAR FRAME# TRDY# IRDY# STOP# DEVSEL# IDSEL PERR# SERR#

REQ# GNT#

PCICLK PCIRST# GBRST# CLKRUN# PME#

INTA# INTB#

HWSPND# TEST

AGND AGND AGND AGND AGND

RSV

R5C833

4

VCC_PCI3V VCC_PCI3V VCC_PCI3V VCC_PCI3V VCC_PCI3V VCC_PCI3V

VCC_RIN

VCC_ROUT VCC_ROUT VCC_ROUT VCC_ROUT VCC_ROUT

VCC_3V

VCC_MD3V

AVCC_PHY3V AVCC_PHY3V AVCC_PHY3V AVCC_PHY3V

TPBIAS0

MDIO00 MDIO01 MDIO02 MDIO03 MDIO04 MDIO05 MDIO06 MDIO07 MDIO08 MDIO09 MDIO10 MDIO11 MDIO12 MDIO13 MDIO14 MDIO15 MDIO16 MDIO17 MDIO18 MDIO19

UDIO0/SRIRQ#

TPAP0 TPAN0

TPBP0 TPBN0

MSEN XDEN

REXT VREF

UDIO1 UDIO2 UDIO3 UDIO4 UDIO5

GND GND GND GND GND GND GND GND GND GND

3

+3VS

10 20 27 32 41 128

61 16

34 64 114 120

67 86 98

106 110 112

113 109

108 105

104 80

79 78 77 76 75 74 73 88 84 82 81 93 90 91 89 92 87 85 83

58 55

94

XI

95

XO

96

FIL0

101 100

72 60 56 65 59 57

4 13 22 28 54 62 63 68 118 122

+3V_PHY

IEEE1394_TPBIAS0 IEEE1394_TPAP0

IEEE1394_TPAN0 IEEE1394_TPBP0

IEEE1394_TPBN0 SD_CARD_DET#

MSCD#_XDCD1 XD_CE# SD_WP SDPWR0_MSPWR_XDPWR XDWP# 3IN1_LED# TP_MSEXTCK SD_MMC_CMD SDCLK_MMCCLK SDDATA0_MSDATA0 SDDATA1_MSDATA1 SDDATA2_MSDATA2 SDDATA3_MSDATA3 MMC_D4 MMC_D5 MMC_D6 MMC_D7 XDCLE XDALE

MSEN XDEN

R5C832XI R5C832XO

SIRQ TP_UDIO1 TP_UDIO2 UDIO3 UDIO4 UDIO5

Layout Note: Please them close to U14.

1

2

C522

C344

C534

0.01U_0402_16V7K

+3VS

1

2

C356

0.01U_0402_16V7K

C356

0.01U_0402_16V7K

Add TP. 10/02

GND GND

Add TP. 10/02

C365 0.01U_0402_16V7K

1 2

SIRQ <22,32,33>

12

1

C367

R388

2

5.1K_0402_1%

270P_0402_50V7K

0.01U_0402_16V7K

C357

1

2

C345

C536

C535

1

2

T118PAD T118PAD T119PAD T119PAD

T120PAD T120PAD T121PAD T121PAD

Layout Note: Add GND shield for SDCLK_MMCCLK.

T122PAD T122PAD T123PAD T123PAD

T81PAD T81PAD T82PAD T82PAD

10U_0805_10V4Z

0.01U_0402_16V7K

1

2

C352

0.01U_0402_16V7K

C352

0.01U_0402_16V7K

C353

0.01U_0402_16V7K

C353

0.01U_0402_16V7K

C354

0.47U_0603_16V4Z

C354

0.47U_0603_16V4Z

10U_0805_10V4Z

Layout Note: Shield GND for CBS_CCLK_INTERNAL and CBS_CCLK

2

1

2

C355

C366

0.01U_0402_16V7K

Layout Note: Place close to R5C833 and Shield GND for SDCLK_MSCLK

1

2

0.1U_0402_16V4Z

C348

0.01U_0402_16V7K

C348

0.01U_0402_16V7K

C349

C350

0.47U_0603_16V4Z

+3VS

Layout Note: Place these cap close to U14.

R383

10K_0603_1%

1 2

+3VS

1

2

C351

10U_0805_10V4Z

0.01U_0402_16V7K

L6

L6 BLM21A601SPT_0805

BLM21A601SPT_0805

1 2

C551 22P_0402_50V8J@C551 22P_0402_50V8J@

15P_0603_50V8J

C346

1 2

C347

1 2

R377 10_0402_5%@R377 10_0402_5%@

1

2

Layout Note: Place close to R5C833 and Shield GND for SD_CLK

R5C832XI

24.576MHz_16P_3XG-24576-43E1

24.576MHz_16P_3XG-24576-43E1 X1

X1

1 2

R5C832XO

SD,MMC,MS,XD muti-function pin define

MDIO PIN Name MDIO00

MDIO01 MDIO02 MDIO03 MDIO04 MDIO05 MDIO06 MDIO07 MDIO08 MDIO09 SDCCLK

+3V_PHY

MDIO10 MDIO11 MDIO12

1000P_0402_50V7K

MDIO13 MDIO14 MDIO15 MDIO16 MDIO17

1

C360

C361

2

10U_0805_6.3V6M

1

C362

2

0.01U_0402_16V7K

1

C364

C363

2

1000P_0402_50V7K

MDIO18 MDIO19

Function set pin define

UDIO3 XDENMSENUDIO4 Function

Pull-up Enable SD,MMC CardPull-up Pull-down

UDIO3 UDIO4 UDIO5

MSEN XDEN

JP16 SDDATA0_MSDATA0 SDDATA1_MSDATA1 SDDATA2_MSDATA2 SDDATA3_MSDATA3

MMC_D4 MMC_D5 MMC_D6 MMC_D7

SDCLK_MMCCLK SD_MMC_CMD

JP16

7

D0

8

D1

9

D2

1

D3

10

D4

11

D5

12

D6

13

D7

5

CLK

2

CMD

TAI_PSDBT0-16GNBS7N14N0_15PCONN@

Pull-down

R373 10K_0402_5% R373 10K_0402_5%

1 2

R374 10K_0402_5% R374 10K_0402_5%

1 2

R375 100K_0402_5% R375 100K_0402_5%

1 2

R371 10K_0402_5% R371 10K_0402_5%

1 2

R376 10K_0402_5%R376 10K_0402_5%

1 2

Modify to same as Meson. 9/13

VDD

WP

CD

VSS2 VSS1 VSS3 VSS4

4

14 15

6 3 16 17

SD Card PIN Name SDCD#

SDWP# SDPWR0 SDPWR1 SDLED#

SDCCMD

SDCDAT0 SDCDAT1 SDCDAT2 SDCDAT3

SD_WP SD_CARD_DET#

MMC Card PIN Name MMCCD#

MMCPWR

MMCLED#

MMCCMD MMCCLK MMCDAT

+3VS

2

1

C550

100P_0402_50V8J

R379

1 2

150K_0402_5%

1

MS Card PIN Name

MSCD#

MSWR

MSLED# MSEXTCK MSBS MSCCLK MSCDAT0 MSCDAT1 MSCDAT2 MSCDAT3

+SD_MMC_3VCC

1

2

C548

C549

4.7U_0805_10V4Z

0.1U_0402_16V4Z

XD Card PIN Name XDCD0#

XDCD1# XDCE# XDR/B# XDPWR XDWP# XDLED#

XDWE# XDRE# XDCDAT0 XDCDAT1 XDCDAT2 XDCDAT3 XDCDAT4 XDCDAT5 XDCDAT6 XDCDAT7 XDCLE XDALE

Near to JP9.

R390

R389

1 2

56.2_0402_1%

R394

1 2

1

C372

2

0.01U_0402_16V7K

56.2_0402_1%

Layout Note: Add GND shield for 1394.

A A

5

GND GND

GND

4

IEEE1394_TPBN0 IEEE1394_TPBP0 IEEE1394_TPAN0 IEEE1394_TPAP0

IEEE1394_TPBIAS0

Reserve them for test

1 2

if any EMI issue. 9/14

56.2_0402_1%

56.2_0402_1% R546 0_0402_5%R546 0_0402_5%

R547 0_0402_5%R547 0_0402_5% R568 0_0402_5%R568 0_0402_5% R569 0_0402_5%R569 0_0402_5%

1 2

R395 56.2_0402_1%

1

C373

2

0.33U_0603_16V4Z

1 2 1 2 1 2 1 2

JP17

SUYIN_020115FB004S512ZLCONN@

1 2 3 4

Layout Note: Shield GND for IEEE1394_TPA and TPB

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

TPBTPB+ TPATPA+

GND GND GND GND

5 6 7 8

2006/08/04 2006/10/06

SDPWR0_MSPWR_XDPWR

Compal Secret Data

Deciphered Date

C368

2

+3VS

1

2

0.1U_0402_16V4Z

U15

3

VIN

4

VIN/CE

2

GND

RT9701CB_SOT25

+SD_MMC_3VCC +SD_MMC_3VCC

1

VOUT

5

VOUT

1

C369

2

1U_0603_10V4Z

Title

Size Document Number Rev

Custom

Date: Sheet

40mil

1

12

2

R392

150K_0402_5%

SCHEMATIC, M/B LA-4021P

401554

C371

C370

10U_0805_10V4Z

0.1U_0402_16V4Z

Compal Electronics, Inc.

1

B

27 36Wednesday, June 03, 2009

B

of

A

TPA6044 no longer needed. So delete BOM options & co-layout components for TPA6044. SGND and SGND1 nets can also be deleted. Only TPA6041 will be supported. 9/5

VDDA_CODEC

R412

1 1

2 2

VDDA_CODEC

3 3

R412 10K_0402_5%

10K_0402_5%

SB_SPKR<22>

Adjust line-in attenuation from -6dB to -10dB by change R415, R418 = 6.04K and changing R417, R420 = 2.0k.

DOCK_LINE_IN_L<34> DOCK_LINE_IN_R<34>

12

R423

20_0402_5%

MIC_BIAS_IN

2

C413

4.7U_0805_10V4Z

1

Place close to U14

4 4

12

C402

0.1U_0402_16V4Z

0.1U_0402_16V4Z 1 2

13

D

Q33

2

2N7002_SOT23

G

S

12

C416 0.1U_0805_25V7MC416 0.1U_0805_25V7M

12

C420 0.1U_0805_25V7MC420 0.1U_0805_25V7M

12

C421 0.1U_0805_25V7MC421 0.1U_0805_25V7M

12

C423 0.1U_0805_25V7MC423 0.1U_0805_25V7M

R437 0_1206_5%@R437 0_1206_5%@

12

GNDAGND

A

R413

R413 100K_0402_5%

100K_0402_5%

1 2

C612 3300P_0402_50V7-K@ C612 3300P_0402_50V7-K@

12

R415 6.04K_0402_1%R415 6.04K_0402_1% R417 2K_0402_5%R417 2K_0402_5% R418 6.04K_0402_1%R418 6.04K_0402_1% R420 2K_0402_5%R420 2K_0402_5%

C613 3300P_0402_50V7-K@ C613 3300P_0402_50V7-K@

INT_MIC1<29> INT_MIC2<29>

12 12 12 12

12

VDDA_CODEC

R430 2.67K_0402_1%R430 2.67K_0402_1% R431 2.67K_0402_1%R431 2.67K_0402_1%

R639

4.7K_0402_5%

1 2

@

GPIO1

R640

1 2

4.7K_0402_5%

@

Add in 3/28

1 2

C388C388

R41010K_0402_5% R41010K_0402_5%

C3910.01U_0402_16V7K C3910.01U_0402_16V7K

12

2

1

DLINE_IN_R_L DLINE_IN_RC_L

DLINE_IN_R_R DLINE_IN_RC_R

C409 1U_0603_10V4Z C409 1U_0603_10V4Z

1 2

C410 1U_0603_10V4Z

1 2

Connect to GNDA. 3/20

MIC1<29> MIC2<29>

1 2 1 2

AC97_RST#_CODEC<21>

AC97_SYNC_CODEC<21>

AC97_SDOUT_CODEC<21>

pull 4.7k to +3VS &

0.01U to GND for ESD solution 2008/04/22

0.1U_0402_16V4Z

B

MONO_IN_HD

LINE_OUTR

C396

C396 1

2

0.1U_0402_16V4Z

1 2

C405 1U_0603_10V4Z

1 2

C407 1U_0603_10V4Z

LINE_OUTL

LINE_OUTR INT_MICL_C INT_MICR_C

C412 1U_0603_10V4Z

1 2

MIC1_C

1 2

C414 1U_0603_10V4ZC414 1U_0603_10V4Z C415 1U_0603_10V4ZC415 1U_0603_10V4Z

+3VS

C424

1 2

R642 4.7K_0402_5%

0.01U_0402_16V7K

DVCORE

2

C425

4.7U_0805_10V4Z

1

B

MIC2_C SENSE_A

SENSE_B

C616

LINE_C_OUTRLINE_OUTL

12

C381 1U_0603_10V4Z

LINE_C_OUTL

12

C384 1U_0603_10V4Z C384 1U_0603_10V4Z

VDDA_CODEC

C398

C397

1

2

U17

10U_0805_10V4Z

0.1U_0402_16V4Z

14

AUX1

15

AUX2

16

AUX3

17

AUX4

23

LINE_IN_L

24

LINE_IN_R

19

CD_GND

21

MIC1

22

MIC2

13

SENSE_A/SRC_B

34

11 10

5

1

2

48

7

SENSE_B/SRC_A

RESET# SYNC SDATA_OUT

S/PDIF_OUT

DVSS

AD1984JCPZ-RL_LFCSP48_7X7

12

PACDN042_SOT23~D@

Change in 3/28

R404

1 2

R406

1 2

DVCORE

MIC_BIAS_IN

33

1

38

AVDD125AVDD2

LINE_OUT_L

MIC_BIAS_IN

LINE_OUT_R

GPIO_0/EAPD

GPIO_1/MIC_BIASE-E

C

AMP. FOR INTERNAL SPEAKER

3/21

1

D18

2

R_SPK+ R_SPK-

3

1

C378

2

100P_0402_50V8J

ACES_85204-02001

ACES_85204-02001 CONN@

CONN@

C379

100P_0402_50V8J

JP18

1

2

3

G1

4

G2

Change in 4/1

R404 2K_0402_1%

2K_0402_1% R406 2K_0402_1%

2K_0402_1%

+3VS

R411

R411 0_0805_5%

0_0805_5%

12

+3VS_CODEC

C400

C399

1

2

9

3

0.1U_0402_16V4Z

DVIO

DVDD

DVCORE

MONO_OUT HP_LOUT_L HP_LOUT_R

BIT_CLK

SDATA_IN

GPIO_2 DM_1/DM_2 DM_3/DM_4

DM_CLK

VREF_FILT

MIC_BIAS_B MIC_BIAS_C

PCBEEP

AVSS1 AVSS2

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C406 47U_B2_6.3V-M

35

C408 47U_B2_6.3V-M

36 32

Correct net name. 10/02

39 41

6

AC97_SDIN0_CODEC

8

47

GPIO1

31 30 2 4 46

AUD_REF

27 28

29

MONO_IN_HD

12 18

N/C

20

N/C

37

N/C

43

N/C

44

N/C

40

N/C

45

N/C

49

NC

26

PIN42

42

Issued Date

C

12

C382 1U_0603_10V4ZC382 1U_0603_10V4Z

2

C401

4.7U_0805_10V4Z

1

+

1 2

+

1 2

HP_IN_L HP_IN_R

R427 0_0402_5%R427 0_0402_5% R571 15K_0402_1%R571 15K_0402_1%

1 2

A_SD_D37 A_SD

2 1

D37 CH751H-40_SC76D37 CH751H-40_SC76

Add R571, D37 in 9/26.

MIC_BIAS_B MIC_BIAS_C

2007/05/29 2008/05/29

VDDA_CODEC

C3740.1U_0402_16V4Z C3740.1U_0402_16V4Z

1

2

Change in 3/28

R405 1K_0402_1%

1 2

C385 0.47U_0402_6.3V6K

C385 0.47U_0402_6.3V6K C386 0.47U_0402_6.3V6K

C386 0.47U_0402_6.3V6K

3/21

R424 10_0402_5%@R424 10_0402_5%@

AC97_BITCLK_CODEC <21>

R425 33_0402_5%R425 33_0402_5%

12

12 12

12

C389 0.47U_0402_6.3V6K

12

C390 0.47U_0402_6.3V6K

+5VS

12

C604 0.1U_0402_16V4ZC604 0.1U_0402_16V4Z

1

C4181U_0603_10V4Z C4181U_0603_10V4Z

C4190.1U_0402_16V4Z C4190.1U_0402_16V4Z

2

Compal Secret Data

+5VS

C37510U_0805_10V4Z C37510U_0805_10V4Z

1

2

C3761U_0603_10V4Z C3761U_0603_10V4Z

1

2

Close to Pin29

LINE_OUT

L_SPK-

C39410U_0805_10V4Z C39410U_0805_10V4Z

C3951U_0603_10V4Z C3951U_0603_10V4Z

1

2

R416 60.4_0402_1%

R416 60.4_0402_1% R419 60.4_0402_1%

R419 60.4_0402_1%

R421 10K_0402_5%R421 10K_0402_5%

1 2

R422 10K_0402_5%R422 10K_0402_5%

1 2

C411 10P_0402_25V8K@C411 10P_0402_25V8K@

12

VDDA_CODEC

SENSE_A<29>

Deciphered Date

D

3/21

+5VS

R400100K_0402_5% R400100K_0402_5%

12

Close to Pin30

GAIN1

33

32

TML

2

SPKR_RIN+

1

SPKR_RIN-

3

SPKR_LIN+

4

SPKR_LIN-

5

SPGND

6

LOUT+

7

LOUT-

8

SPVDD

CPVDD

9

C403

1U_0603_10V4Z

12 12

1 2

AC97_SDIN0 <21>

EAPD <33>

A_SD <33>

ESD Request. 03/19

SENSE_A

12

R434

0_0402_5%@

SENSE_B SENSE_A_C

D

Modify in 3/26

Change gain to 12db.

R401100K_0402_5% R401100K_0402_5%

R402 install.

12

R400 not install.

3/21

+5VS

VDDA_CODEC

GAIN0

GAIN031GAIN1

C1P10CPVSS13HP_OUTL

1

2

1

C417

C417 1U_0603_10V4Z

1U_0603_10V4Z

2

1

C422

C422 1U_0603_10V4Z

1U_0603_10V4Z

2

HP_INL

28

27

29

30

VDD

SGND

REG_OUT

C1N

CPGND

12

14

11

1

C404

2

1U_0603_10V4Z

L7

12

CHB1608B121YZF_0603

CHB1608B121YZF_0603 L8

L8

12

CHB1608B121YZF_0603

R432 39.2K_0402_1% R432 39.2K_0402_1%

1 2

R433 20K_0402_1% R433 20K_0402_1%

1 2

R435

39.2K_0402_1%

1 2

HP_INL

HPVSS

HP_DET<29>

E

GAIN1 GAIN0 10dB 12dB

15.6dB

21.6dB

GAIN1 GAIN0

00 01 1

R402 0_0402_5%@R402 0_0402_5%@ R403 0_0402_5%@R403 0_0402_5%@

12 12

0 11

Change value. 9/28

C377 2.2U_0603_16V6KC377 2.2U_0603_16V6K

1 2

C380 2.2U_0603_16V6KC380 2.2U_0603_16V6K

1 2

HP_INR

26

25

HP_INR

REG_EN

HP_OUTR

15

16

2

3

1

Title

Size Document Number Rev

Date: Sheet

SLP_S3# <22,24,26,33,35,36,38,41,42,44>

U16

U16 TPA6041A4RHBR QFN 32P

TPA6041A4RHBR QFN 32P

24

BYPASS

23

SPKR_EN#

22

HP_EN

21

SPGND

20

ROUT+

19

ROUT-

18

SPVDD

17

HPVDD

HP_OUTL <29> HP_OUTR <29>

DLINE_OUT_L <34>

DLINE_OUT_R <34>

A_SD_D37 A_SD

D50

D50 PJDLC05_SOT23-3

PJDLC05_SOT23-3

HP_EN

SENSE_A_A SENSE_A_B

2N7002DW-T/R7_SOT363-6

Q36

13

D

2N7002_SOT23

2

G

S

100K_0402_5%

Compal Electronics, Inc.

SCHEMATIC, M/B LA-4021P

401554

HP_IN_L HP_IN_R

C383 0.47U_0402_6.3V6K_X5R

12 A_SD HP_EN

1 2

R408 100K_0402_5%@R408 100K_0402_5%@

R_SPK+ R_SPK-L_SPK+

3/21

+5VS

1

C3921U_0603_10V4Z C3921U_0603_10V4Z

C39310U_0805_10V4Z C39310U_0805_10V4Z

2

Add in 3/28

HP_EN

3/26

+5VS

R426

100K_0402_5%

100K_0402_5% R429

R429 0_0402_5%

0_0402_5%

1 2

Q34B

12

R436

1 2

3

4

1

C426

0.1U_0402_16V4Z

2

SENSE_A_A

61

Q34A

Q34A 2N7002DW-T/R7_SOT363-6

2N7002DW-T/R7_SOT363-6

2

Q34 & Q35 change to 2 in 1 package. 3/17

5

LINE_IN_SENSE <34>

28 36Wednesday, June 03, 2009

E

3/21

+5VS

0.1U_0402_16V4Z

@

MIC_SENSE <29>

of

V

1

2

C611

B

A

Add C614 to provide some deglitching. 3/28

HP_DET<28>

L9

R439

60.4_0402_1%

1 2

R443

R443 10K_0402_5%

10K_0402_5%

1 2

1 2 R440

R440

60.4_0402_1%

HP_OUTR<28> HP_OUTL<28>

1 1

R442

10K_0402_5%

Change R445 to 100K to reduce drain and change pin 1 connection to +5VS

L9 CHB1608B121YZF_0603

CHB1608B121YZF_0603

1 2 1 2

L10

L10 CHB1608B121YZF_0603

CHB1608B121YZF_0603

Modify to same as Meson. 10/02

MIC_BIAS_B

1 2

R447 3.9K_0402_1%

1 2

R448 3.9K_0402_1%

2 2

EXT_MICB EXT_MICA

MIC_SENSE<28>

1 2 1 2

L11

L11 CHB1608B121YZF_0603

CHB1608B121YZF_0603

L12

L12 CHB1608B121YZF_0603

CHB1608B121YZF_0603

C428

1

2

470P_0402_50V7K

100K_0402_5%

MIC_SENSE

1

2

1

2

C430

C429

470P_0402_50V7K

B

470P_0402_50V7K

R445

1

2

1

2

C431

C614

+5VS

470P_0402_50V7K

0.01U_0402_16V7K

12

1

2

HP_OUT_L

C432

0.1U_0402_16V4Z

JP19

5 4 3

6 2 1

FOX_JA6033L-B5S3-7F_6PCONN@

D19

3

1

2

PACDN042_SOT23~D@

JP20

5 4 3

6 2 1

FOX_JA6033L-B5S3-7F_6PCONN@

Connect to AGND. 11/26

C

SENSE_A<28>

R438

5.1K_0603_1%

1 2

4.7U_0805_10V4Z

D

Q37

13

D

2N7002_SOT23

S

VDDA_CODEC

1

C433

2

G

12

R449

R449 47K_0402_5%

47K_0402_5%

12

R451

R451 47K_0402_5%

47K_0402_5%

R441

R441 100K_0402_5%

100K_0402_5%

CODEC_REF

1

2

C434

4.7U_0805_10V4Z@

E

DOCK_HPS# <34>

2

C427

0.1U_0402_16V4Z

1

Change R441 to 100K to make Q37 turn on enough for SENSE_A. 11/26

EXTERNAL MICROPHONE/LINE OUT JACK

EXT_MICA_2

CODEC_REF

1

C437

2

100P_0402_50V8J

1 2

10K_0402_5%

1

C454

C454 68P_0402_50V8J

68P_0402_50V8J

2

R465

100P_0402_50V8J

3 2

B

L13

L13 HLC0603CSCCR10JT_0603

EXT_MICA EXT_MICA_1

3 3

JP21

ACES_85204-04001CONN@

4 4

INT_MIC_1_2

1

2

INT_MIC_2_2

3

4

5

G1

6

G2

12

C439 0.47U_0402_6.3V6K_X5R

R457

3K_0402_5%

A

HLC0603CSCCR10JT_0603

1 2

MIC_BIAS_C

R458

R458 3K_0402_5%

3K_0402_5%

1 2

C450 0.068U_0603_16V7K

INT_MIC_1_3

1

2

1 2

R454 10K_0402_5%

C441

C441 68P_0402_50V8J

68P_0402_50V8J

L16

L16 HLC0603CSCCR10JT_0603

HLC0603CSCCR10JT_0603

1 2

C435 100P_0402_50V8J

1 2

R453 100K_0402_5% R453 100K_0402_5%

VDDA_CODEC

4

P

+

1

OUT

-

G

U18A

U18A TLV2464_TSSOP14

TLV2464_TSSOP14

11

INT_MIC_1_4

CODEC_REF

1 C447

C447

2

100P_0402_50V8J

MIC1

C444 220P_0402_50V7K C444 220P_0402_50V7K

1 2

R459 100K_0402_5%

VDDA_CODEC

1

C448

4

2

0.1U_0402_16V4Z

+

OUT

-

11

0.1U_0402_16V4Z

P

8

G

U18C

U18C TLV2464_TSSOP14

TLV2464_TSSOP14

INT_MIC1<28>

10

9

AMP. FOR EXTERNAL MICROPHONE

L14

L14 HLC0603CSCCR10JT_0603

MIC1 <28>

EXT_MICB EXT_MICB_1

12

C440 0.47U_0402_6.3V6K_X5R

HLC0603CSCCR10JT_0603

1 2

AMP. FOR INTERNAL MICROPHONE

L15

L15 HLC0603CSCCR10JT_0603

INT_MIC_2_2 INT_MIC_2_3

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2007/05/29 2008/05/29

Compal Secret Data

1 2

C449 0.068U_0603_16V7K

Deciphered Date

HLC0603CSCCR10JT_0603

1 2

R455 10K_0402_5%

1

C442

C442 68P_0402_50V8J

68P_0402_50V8J

2

1 2

C452

D

1

2

EXT_MICB_2

CODEC_REF

1

C438

2

100P_0402_50V8J

5 6

INT_MIC_2_4

CODEC_REF

1

C445

2

R462

R462 10K_0402_5%

10K_0402_5%

1 2

C452 68P_0402_50V8J

68P_0402_50V8J

Title

Size Document Number Rev

401554

Date: Sheet

1 2

C436 100P_0402_50V8J

1 2

R452 100K_0402_5% R452 100K_0402_5%

VDDA_CODEC

4

P

+

OUT

-

G

11

100P_0402_50V8J

12 13

Compal Electronics, Inc.

MIC2

7

U18B

U18B TLV2464_TSSOP14

TLV2464_TSSOP14

C443 220P_0402_50V7K C443 220P_0402_50V7K

1 2

R456 100K_0402_5%

VDDA_CODEC

1

C446

4

2

0.1U_0402_16V4Z

P

+

14

OUT

TLV2464_TSSOP14

-

G

U18D

11

INT_MIC2<28>

SCHEMATIC, M/B LA-4021P

E

MIC2 <28>

B

of

29 36Wednesday, June 03, 2009

of

29 36Wednesday, June 03, 2009

of

29 36Wednesday, June 03, 2009

SWITCH BOARD.

I2C_CLK<33> I2C_DAT<33> I2C_INT<33>

AC97_SDOUT_MDC<21>

AC97_SYNC_MDC<21>

AC97_SDIN1<21>

Change design at 12/03.

AC97_RST#_MDC<21>

MODEM_DISABLE#<20>

SN74AHC1G08DCKR_SC70

R4665.1K_0402_5% R4665.1K_0402_5%

12

R468

+3VL +3VS +3VL

R4675.1K_0402_5% R4675.1K_0402_5%

12

STB_LED

CAP_RST_EC WL/BT_LED

10K_0402_5%

CAP_RST_EC<33>

STB_LED<19,34>

WL/BT_LED<19>

I2C_CLK I2C_DAT I2C_INT

MDC 1.5 Conn.

AC97_SDOUT_MDC AC97_SYNC_MDC

AC97_SDIN1_MDC

1 2

R469 33_0402_5%R469 33_0402_5%

+3VALW

5

U37

1

P

IN1

4

O

2

IN2

G

3

JP25

G1 G2

ACES_88266-02001CONN@

I2C_CLK I2C_DAT

2

3

D47

1 2

D47

I2C_INT CAP_RST_EC

D49

12

1

2

3

1

JP26

1

TIP

2

RING

3

GND

4

GND

ACES_85204-02001_2PCONN@

AC97_BITCLK_MDC <21>

1

C455

2

KSO11 KSO0 KSO2 KSO5 KSI_D_14 KSI_D_8 KSI_D_12 KSI_D_10 KSI_D_0 KSI_D_4 KSI_D_2 KSI_D_1 KSI_D_3 KSO3 KSO8 KSO4 KSO7 KSO6

KSO10

KSO1 KSI_D_5 KSI_D_6

KSI7

KSI_D_13 KSI_D_11

+3VS

1

C456

C457

2

0.1U_0402_16V4Z

4.7U_0805_10V4Z@

1000P_0402_50V7K

4.7U_0805_10V4Z@

KSI_D_9

KSO9

LEFT RIGHT

PACDN042_SOT23~D

JP23

1

2

3

4

5

6

7

8

9

10

11

GND1

12

GND2

ACES_87213-1000G

ACES_87213-1000G CONN@

CONN@

JP24

ACES_88025-120L_12PCONN@

1

3

5

7

9

11

GND13GND14GND15GND16GND17GND

2 4 6

8 10 12

18

PACDN042_SOT23~D

+3VS

2 4 6 8 10

R470 0_0402_5%R470 0_0402_5%

12

C458

10P_0402_25V8K@

RJ-11 Conn.

MOD_RING

1

MOD_TIP

2

3 4

C459

220P_1808_3KV@

MOD_TIP MOD_RING

2

C460

220P_1808_3KV @

1

KSO[0..11]<33> KSI[0..7]<33>

JP22

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

GND1

32

GND2

HRS_FH28-60(30)SB-1SH(86)CONN@

KSI0

1

KSI1

1

KSI2

1

KSO[0..11] KSI[0..7]

KSO11

KSO0 KSO2 KSO5

KSI_D_14 KSI_D_8 KSI_D_12 KSI_D_10

KSI_D_0 KSI_D_4 KSI_D_2 KSI_D_1

D21

KSI_D_0

2

KSI_D_8

3

DAP202U_SOT323-3

DAP202U_SOT323-3 D23

D23

KSI_D_1

2

KSI_D_9

3

DAP202U_SOT323-3

DAP202U_SOT323-3 D25

D25

KSI_D_2

2

KSI_D_10

3

DAP202U_SOT323-3

2 3 4 5

100P_1206_8P4C_50V8@

2 3 4 5

100P_1206_8P4C_50V8@

2 3 4 5

100P_1206_8P4C_50V8@

CP1

81 7 6

CP3

81 7 6

CP5

81 7 6

D20

KSI3

1

DAP202U_SOT323-3

DAP202U_SOT323-3 D22

D22

KSI4

1

DAP202U_SOT323-3

DAP202U_SOT323-3 D24

D24

KSI5

1

DAP202U_SOT323-3

DAP202U_SOT323-3 D26

D26

KSI6

1

DAP202U_SOT323-3

KSI_D_3 KSO3 KSO8 KSO4

KSO7 KSO6

KSO10

KSO1

KSI_D_5 KSI_D_6 KSI7 KSI_D_13

KSI_D_11 KSI_D_9 KSO9

2 3 4 5

100P_1206_8P4C_50V8@

2 3 4 5

100P_1206_8P4C_50V8@

2 3 4 5

100P_1206_8P4C_50V8@

2 3 4 5

100P_1206_8P4C_50V8@

KSI_D_3

2

KSI_D_11

3

KSI_D_4

2

KSI_D_12

3

KSI_D_5

2

KSI_D_13

3

KSI_D_6

2

KSI_D_14

3

CP2

81 7 6

CP4

81 7 6

CP6

81 7 6

CP7

81 7 6

INT_KBD CONN.

Power button

+3VL +5VS

12

R472

100K_0402_5%

ON/OFF#

100K_0402_5%

1

C463

1U_0603_10V4Z

2

ON/OFF# <34>

SF10402ML080C_0402@

SW1

SW1 1BT002-0121L_4P

1BT002-0121L_4P

3 4

2

D27

1

1 2

5

6

+3VL

5

U20

U20 SN74LVC1G14DCKR_SC70-5

SN74LVC1G14DCKR_SC70-5

V

2

A

Y

NC

G

1

3

4

1 2

R473

R473 100K_0402_5%

100K_0402_5%

C464

C464 1U_0603_10V4Z

1U_0603_10V4Z

+3VL

12

R471

R471 100K_0402_5%

100K_0402_5%

D28

CH751H-40_SC76

ON/OFFBTN_KBC# <33>

1 2

R474 100K_0402_5%R474 100K_0402_5%

21

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

+3VALW

ON/OFFBTN# <22>

Issued Date

13

D

2

G

Q38

S

1

2

2N7002_SOT23

TrackPoint CONN.

JP27

RIGHT LEFT

SP_CLK<33>

SP_DATA<33>

+5VS

Compal Secret Data

2005/03/10 2006/03/10

Compal Secret Data

JP27 1 2 3 4 5 6 7 8

ACES_87151-0807G

ACES_87151-0807G CONN@

CONN@

Deciphered Date

+5VS +5VS

1 2 3 4 5 6 7 8

1

C462

0.1U_0402_16V4Z

2

TP_DATA<33>

T/P BOARD.

JP28

TP_CLK<33>

2

Title

Size Document Number Rev

401554

Date: Sheet

1 2 3 4

5 6

CONN@

ACES_87151-04051_4P

3

D39

1

Compal Electronics, Inc.

SCHEMATIC, M/B LA-4021P

ACES_87151-04051_4P

UESD3.3DT5G SOT-723@

1

C461

0.1U_0402_16V4Z

2

30 36Wednesday, June 03, 2009

B

of

5

4

3

2

1

C466

220U 6.3V M F60

USB_VCCA+5VALW

JP30

1

USB20_N4 USB20_P4

ACES_87213-0600G_6P

2

3

4

5

GND

6

GND

7

GND

8

GND

SUYIN_020173MR004S558ZL_4PCONN@

JP31

1 2 3

8 4 7 5 6

USB20_N0<22> USB20_P0<22>

1

2

C467

C468

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z 1000P_0402_50V7K

1000P_0402_50V7K

USB20_N4<22> USB20_P4<22>

PACDN042_SOT23~D

@

S4_STATE#

2

3

1

+5VALW

D29

D D

R476

+5VALW

S4_STATE#

4.7U_0805_10V4Z

C C

1

C465

2

Change U21 to active high part. 12/11

U21

1

GND

2

IN

3

IN EN#4OC#

G548A1P1U

(2A,100mils ,Via NO.=4)

U22, D30, R481, C474 ~ C477 will move to USB board side to save M/B space.

OUT OUT OUT

8 7 6 5

R476 10K_0402_5%

10K_0402_5%

1 2

W=100mils

1

+

2

JP29

1 2 3 4 5 6 7 8

ACES_87213-0800G_8PCONN@

BT_OFF<22>

BT Connector

USB20_P6_R USB20_N6_R

R475 0_0402_5%R475 0_0402_5% R477 0_0402_5%R477 0_0402_5%

12

R480

R480 10K_0402_5%

10K_0402_5%

R482

1 2

220K_0402_1%

12 12

Q39

Q39 SI2301BDS_SOT23

SI2301BDS_SOT23

S

D

13

G

2

+3VAUX_BT

USB20_P6 <22> USB20_N6 <22> BT_LED <19>

+3VAUX_BT+3VALW

C4710.1U_0402_16V4Z C4710.1U_0402_16V4Z

1

2

C47210U_0805_10V4Z C47210U_0805_10V4Z

B B

+3VALW

+5VALW USB_VCCC

USB CONNECTOR 3

R356

R356 100K_0402_5%

100K_0402_5%

1 2

12

1

2

C484

R629

1 2

0_0402_5%

1

2

C485 1000P_0402_50V7K C485 1000P_0402_50V7K

S4_STATE#_R

FAULT

1

2

C486 82P_0402_50V7KC486 82P_0402_50V7K

1

2

C487

R628 10K_0402_5%R628 10K_0402_5%

1 2

5

R485

1K_0402_5%

1

2

C321 1U_0603_10V4ZC321 1U_0603_10V4Z

0.47U_0402_10V7K

Change for SI1 to prevent USB power short to GND cause system shutdown. 0130

Change C486 from 2200pF to 680pF. Change C321 from 1000pF to 1uF. Change R356 from 10K to 100K. Change C484 from 1000pF to 0.47uF. Change R484 from 1K to 820.

Currently power USB will not enable after OCP, so add R629 make it enable after OCP free.

S4_STATE#<22>

A A

13 11 12

3 4

2 6 9

0.1U_0402_16V4Z

U23

ENABLE FAULT PWRGD

TIMER VREG

DGND AGND AGND

TPS2331IPWRG4_TSSOP14

4

ISET

ISENSE

GATE

DISCH

VSENSE

8

IN

10 7 1 14 5

USB_ISENSE1 USB_ISENSE2

3.75A nominal with 3.5A minimum

R483

0.01_2512_1%

1 2

1

12

2

R484

0.1U_0402_16V4Z

820_0805_1%

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C478

1

2

C479

2.2U_0805_16V4Z

Q40

Q40 8 7 6 5

3

1

S

D

2

S

D

3

S

D

4

G

D

SI4800DY_SO8

1

C483

2

0.1U_0402_16V4Z

Compal Secret Data

2006/02/13 2006/07/26

Compal Secret Data

W=160mils

1

C480

+

2

USB20_N5<22> USB20_P5<22>

Deciphered Date

1

C481

C482

2

220U_D_6.3VM

0.1U_0402_16V4Z

0.1U_0402_16V4Z 1000P_0402_50V7K

1000P_0402_50V7K

D31PACDN042_SOT23~D@D31PACDN042_SOT23~D

@

2

3

1

2

JP32

1

2

3

4

5

GND

6

GND

7

GND

8

GND

SUYIN_020173MR004S558ZL_4PCONN@

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, M/B LA-4021P

401554

1

of

31 36Wednesday, June 03, 2009

of

31 36Wednesday, June 03, 2009

of

31 36Wednesday, June 03, 2009

B

5

Finger printer

4

3

2

+3VS

+3VALW

1

D D

+3VALW

R486

R486 10K_0402_5%

10K_0402_5%

1 2

FPR_OFF<22>

C C

B B

A A

BIOS ROM

7/20

+3VL

SPI_CLK_JP34 SPI_CLK_JP34 SPI_SI_JP34

R501 3.3K_0402_5%R501 3.3K_0402_5%

20mils

R503 0_0402_5%R503 0_0402_5% R504 0_0402_5%R504 0_0402_5% R507 0_0402_5%R507 0_0402_5% R56 0_0402_5%R56 0_0402_5% R632 0_0402_5%R632 0_0402_5%

R487

R487 220K_0402_1%

220K_0402_1%

1 2

0.1U_0402_16V4Z

1 2

SPI_CS0#<33>

SPI_CLK<33>

1 2 1 2 1 2 1 2

Q42

Q42 SI2301BDS_SOT23

SI2301BDS_SOT23

S

G

2

1

C496

2

SPI_SI<33>

12

D

13

1

C4920.1U_0402_16V4Z C4920.1U_0402_16V4Z

C56310U_0805_6.3V4Z C56310U_0805_6.3V4Z

2

USB20_N8<22> USB20_P8<22>

PACDN042_SOT23~D

7/20

+3VL

Change Footprint. 12/13

20mils

SPI_WP# SPI_HOLD#_0 SPI_CS0# SPI_CLK

SPI_SI SPI_SO_R SPI_CS0#SPI_CS0#_JP34 SPI_CLK

SPI_SO_RSPI_SO_JP34 SPI_HOLD#_0SPI_HOLD#_0_JP34

U25

8

VCC

3

W

7

HOLD

1

S

6

C

5

D

WIESO_G6179-100000_8P

7/20

20mils

+3VL

VSS

2/22

USB20_N1_PWR

3

D32

4

2

Q

1 2

R505 3.3K_0402_5%R505 3.3K_0402_5%

JP33

1

2

3

4

2

1

45@

R502 15_0402_5%

SPI_WP#

4

E&T_3801-04CONN@

&U1

SST25LF080A_SO8-200mil

1 2

R506 0_0402_5%@R506 0_0402_5%@

1 2

LPC_PD#<22>

SPI_SO <33>

TPM1.2 on board

R489 10K_0402_5%R489 10K_0402_5%

1 2

R492 0_0402_5%R492 0_0402_5%

R497

4.7K_0402_5%@

R498

0_0402_5%

+3VS

12

32.768KHZ_12.5P_1TJS125BJ2A251

C494 18P_0402_50V8JC494 18P_0402_50V8J

C495 18P_0402_50V8JC495 18P_0402_50V8J

CLK_PCI_TCG<16>

12

C493

10P_0402_50V8K@

R494 10_0402_5%@R494 10_0402_5%@

PM_CLKRUN#<22,27,33>

12

Y4

2 3

12

Add SIRQ and connect to pin5. 10/08

8051_RECOVER#

1

IN

NC

4

OUT

NC

+3VL

12

R500

8051_RECOVER#<33>

VCC1_PWRGD<33,35,39>

Modify in 2/23.

KBC_SPI_CS1#_R_JP34<33>

Pin3, 23 tie to GND. 10/10

1

C488

2

LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3 LPC_FRAME# PLT_RST#

SIRQ

12

TPM_XTALO TPM_XTALI

12

100K_0402_5%

CLK_PCI_DB<16>

LPC_FRAME#<21,26,33>

SIRQ<22,27,33>

PLT_RST#<8,20,26>

LPC_AD0<21,26,33> LPC_AD1<21,26,33> LPC_AD2<21,26,33> LPC_AD3<21,26,33>

8051TX<33>

8051RX<33>

1

C489

2

0.1U_0402_16V4Z

26 23 20 17 22 16 28 27 21

15

14 13

TPM_XTALI

R499

R499 10M_0402_5%

10M_0402_5%

TPM_XTALO

5

10

19

VSB

VDD

GPIO

GPIO2

TEST1

TESTB1/BADD

NC NC NC

GND

SLB 9635 TT 1.2_TSSOP28

4

11

18

1

C491

2

0.1U_0402_16V4Z

U24

LAD0 LAD1 LAD2 LAD3 LFRAME# LRESET# LPCPD# SERIRQ LCLK

CLKRUN#

7

PP

XTALO XTALI/32K IN

C490

1

2

0.1U_0402_16V4Z

24

SLB 9635 TT 1.2

25

LPC Debug Port

B+

1 2 3

SIRQ

8051_RECOVER#

SPI_CS0#_JP34 SPI_SI_JP34SPI_SI SPI_SO_JP34 SPI_HOLD#_0_JP34

4 5 6 7 8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

0.1U_0402_16V4Z

TPM_GPIO

6

TPM_GPIO2

2

Base I/O Address 0 = 02Eh 1 = 04Eh*

R495

R495 0_0402_5%

0_0402_5% 8 9

3 12 1

JP34

Ground LPC_PCI_CLK Ground LPC_FRAME# +V3S LPC_RESET# +V3S LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3 VCC_3VA PWR_LED# CAPS_LED# NUM_LED# VCC1_PWRGD SPI_CLK SPI_CS# SPI_SI SPI_SO SPI_HOLD# Reserved Reserved Reserved

ACES_87216-2404_24P

ACES_87216-2404_24P CONN@

CONN@

R490

4.7K_0402_5%

4.7K_0402_5% 12

4.7K_0402_5%@

+3VS+3VS

12

T83PAD T83PAD T84PAD T84PAD

12

R496

5

4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/03/10 2006/03/10

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, M/B LA-4021P

401554

1

of

32 36Wednesday, June 03, 2009

of

32 36Wednesday, June 03, 2009

of

32 36Wednesday, June 03, 2009

B

+3VL

1

IN

2

KSI0 KSI3 KSI2 KSI1

KSI7 KSI6 KSI5 KSI4

TP_CLK

TP_DATA

SP_CLK SP_DATA PS2_CLK PS2_DATA

RUNSCI_EC#

4

OUT

SMSC guideline

1

suggest to change

NC3NC

18P to 22P

2

C507 22P_0402_50V8JC507 22P_0402_50V8J

RP18

1 8 2 7 3 6 4 5

10K_1206_8P4R_5%

RP19

1 8 2 7 3 6 4 5

10K_1206_8P4R_5%

+5VS

1 2

R521 10K_0402_5%R521 10K_0402_5%

1 2

R524 10K_0402_5%R524 10K_0402_5%

RP20

1 8 2 7 3 6 4 5

10K_1206_8P4R_5%

+3VS

1 2

R533 10K_0402_5%R533 10K_0402_5%

delete R537 & 539 to clean up CRY1 & CRY2 traces

1

2

C506 22P_0402_50V8JC506 22P_0402_50V8J

Y5

32.768KHZ_12.5P_1TJS125BJ2A251

Y5

Change in 10/08

R520

0_0402_5%@

C499

0.1U_0402_16V4Z

1 2

1

2

KBC_SPI_CLK_R<22>

MC2_DISABLE<26>

+RTCVCC

12

1

2

1U_0603_10V4Z

C528

0.1U_0402_16V4Z

KSO[0..11]<30>

KSI[0..7]<30>

PM_CLKRUN#<22,27,32>

CLK_PCI_EC<16>

RUNSCI_EC#<22>

LPC_FRAME#<21,26,32>

LAN_PHYPC<22,24,25>

SPI_CLK<32>

R542

R542 0_0402_5%

0_0402_5%

1

2

0.1U_0402_16V4Z

C529

C500

KBC_SPI_CS0#_R<22>

NPCI_RST#<22>

KBC_SPI_SI_R<22>

TP_DATA<30>

SP_DATA<30>

LPC_AD3<21,26,32> LPC_AD2<21,26,32> LPC_AD1<21,26,32> LPC_AD0<21,26,32>

ADP_PS1<44>

WMC1_DISABLE<26>

SPI_CS0#<32>

KBC_SPI_SO<22>

TP_CLK<30> SP_CLK<30>

SIRQ<22,27,32>

+VCC0

LAN_WOL_EN<22,36>

1

0.1U_0402_16V4Z

2

SPI_SI<32>

SPI_SO<32>

R623

1 2

2

1

C501

KSO0 KSO1 KSO2 KSO3 KSO4 KSO5 KSO6 KSO7 KSO8 KSO9 KSO10 KSO11

KSI0 KSI1 KSI2 KSI3 KSI4 KSI5 KSI6 KSI7

TP_CLK TP_DATA SP_CLK SP_DATA PS2_CLK PS2_DATA

CLK_PCI_EC RUNSCI_EC#

CRY1 CRY2

0_0402_5%

KBC_SPI_CS1#_R

C339

4.7U_0805_10V4Z

+VCC0

1

C502

0.1U_0402_16V4Z

2

U26

128

FLDATAOUT

127

HSTDATAOUT

97

FLCS0#

96

HSTCS0#

95

FLDATAIN

94

HSTDATAIN

21

KSO0

20

KSO1

19

KSO2

18

KSO3

17

KSO4

16

KSO5

13

KSO6

12

KSO7

10

KSO8

9

KSO9

8

KSO10

7

KSO11

6

KSO12/GPIO00/KBRST

5

KSO13/GPIO18

29

KSI0

28

KSI1

27

KSI2

26

KSI3

25

KSI4

24

KSI5

23

KSI6

22

KSI7

35

IMCLK

36

IMDAT

38

KCLK

40

KDAT

41

EMCLK

42

EMDAT

55

CLKRUN#

57

SER_IRQ

54

PCI_CLK

76

EC_SCI#

51

LAD[3]

50

LAD[2]

48

LAD[1]

46

LAD[0]

52

LFRAME#

53

LRESET#

45

LPCPD#/GPIO23

70

XTAL1

71

XTAL2

68

VCC0

1

GPIO40

2

HSTCLK

3

FLCLK

30

GPIO39

31

HSTCS1#

32

FLCS1#

33

GPIO38

34

GPIO37

43

NC

44

NC

Modify in 2/23.

AGND FILTER

1

C503

4.7U_0805_10V4Z

2

Keyboard/Mouse Interface

Power Mgmt/SIRQ

LPC

LPC Bus

Bus

C510

1 2

0_0402_5%

1

2

14

106

VCC1

VCC139VCC158VCC184VCC1

SMSC_1091-NU_TQFP-128P

Access Bus Interface

AGND

VSS11VSS37VSS47VSS56VSS

VSS82VSS

72

104

117

1 2

R633 0_0402_5%R633 0_0402_5%

SMSC guideline suggest to change 0.1U to 0 ohm

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

119

49

VCC1

VCC2

Miscellaneous

KBC_SPI_CS1#_R

Issued Date

R511 0_0402_5%R511 0_0402_5%

1

C498

2

0.1U_0402_16V4Z

General Purpose I/O Interface

EA Strap#/GPIO26/KSO17

24MHZ_OUT/GPIO19/WINDMON

KBC1091-NU_TQFP128_14X14

12

Del BATSELB_A# pin since only one battery. 10/18

GPIO28 GPIO29 GPIO30 GPIO31 GPIO32

OUT1/IRQ8#

OUT7/SMI#

OUT8/KBRST

OUT9/PWM2 OUT10/PWM0 OUT11/PWM1

GPIO01 GPIO02

GPIO03 GPIO04/KSO14 GPIO05/KSO15

GPIO07/PWM3

GPIO08/RXD

GPIO09/TXD

GPIO11/AB2A_DATA

GPIO12/AB2A_CLK

GPIO13/AB2B_DATA

GPIO14/AB2B_CLK GPIO15/FAN_TACH1 GPIO16/FAN_TACH2

GPIO17/A20M

GPIO20/PS2CLK GPIO21/PS2DAT

GPIO24/KSO16

GPIO27

AB1A_DATA

AB1A_CLK

AB1B_DATA

AB1B_CLK

PGM Strap/GPIO25

CLOCKI

32KHZ_OUT/GPIO22

RESET_OUT#/GPIO06

PWRGD

VCC1_PWRGD

TEST PIN

DMS_LED#/GPIO10

BAT_LED#

PWR_LED#/8051TX

FDD_LED#/8051RX

GPIO33 GPIO34 GPIO35 GPIO36

KBC_SPI_CS1#_R <22>KBC_SPI_CS1#_R_JP34<32>

2006/02/13 2006/07/26

CAP

OUT0

+3VS

C504 4.7U_0805_10V4ZC504 4.7U_0805_10V4Z

15 93

98 99 100 126

124 125

123 122 121 120 118

107 79 80 81 83

85 86 87

88 89 90 91 92 101 102

103 105 4 74

111 112

109 110

73 108

59 75 60 78 77 61

69

116 113 115 114

67

NC

66

NC

65 64 63 62

1 2

R515 0_0402_5%R515 0_0402_5%

1 2

R517 0_0402_5%R517 0_0402_5%

1 2

KBC_PWR_ON GREEN_BATLED#

KBRST#

THM_TRAVEL#

KSO14 KSO15

PM_RSMRST# CRACK_BGA

AB2A_DATA

R526 0_0402_5%R526 0_0402_5%

AB2A_CLK

R527 0_0402_5%R527 0_0402_5% R279 0_0402_5%R279 0_0402_5% R516 0_0402_5%R516 0_0402_5%

BATCON

R630 0_0402_5%R630 0_0402_5%

8051_RECOVER#

ADP_PRES

SMB_EC_DA1 SMB_EC_CK1

AB1B_DATA AB1B_CLK

R534 0_0402_5%R534 0_0402_5%

EA#

R531 1K_0402_5%R531 1K_0402_5% CLK_14M_KBC 32K_CLK

PWR_GD VCC1_PWRGD

TEST

Change to 1K. 10/03

ADP_ID

1 2

R538 100K_0402_5%R538 100K_0402_5%

R333 0_0402_5%@R333 0_0402_5%@

1 2

R57 0_0402_5%R57 0_0402_5%

1 2

R544 0_0402_5%@R544 0_0402_5%@

1 2

Compal Secret Data

Deciphered Date

+3VL

R512

100K_0402_5%@

1 2

SUS_PWR_ACK <22>

AC_PRESENT <22>

KBC_PWR_ON <39>

GREEN_BATLED# <19>

LAN_DISABLE_N <22> BAT_PWM_OUT <38> CHGCTRL <38>

Swap BAT_PWM_OUT and LAN_DISABLE_N. 10/08

T85PAD T85PAD T86PAD T86PAD

T127PAD T127PAD

1 2 1 2 1 2 1 2 1 2

BAT_ID# <37>

GATEA20 <21>

8051_RECOVER# <32> SLP_S3# <22,24,26,28,35,36,38,41,42,44>

ADP_PRES <24,36,38>

PCI_SERR# <20,27>

R519 10K_0402_5%@ R519 10K_0402_5%@

1 2

ON/OFFBTN_KBC# <30> LOW_BAT# <22>

PM_RSMRST# <22>

R604 10K_0402_5%R604 10K_0402_5%

1 2

CRACK_BGA <13,23>

SMB_EC_DA1 <37> SMB_EC_CK1 <37>

PM_SLP_M# <22,36,40,41>

EAPD <28>

+3VL

CH751H-40_SC76

I2C_DAT <30> I2C_CLK <30> CELLS <38> A_SD <28> AC_AND_CHG <38>

10/24

1 2

12

R545 0_0402_5%R545 0_0402_5%

1 2

R543 2.2K_0402_5%R543 2.2K_0402_5%

R536 1K_0402_5%R536 1K_0402_5%

1 2

12

PWR_GD <35,42> ADP_PS0 <44>

AMBER_BATLED# <19> 8051TX <32> 8051RX <32>

+3VL

I2C_INT <30>

R535 10_0402_5% @R535 10_0402_5% @

+3VL

LANLINK_STATUS# <22,24,25> LID_SW# <18,19,22> CAP_RST_EC <30>

1 2

PM_PWROKPGD_IN

R513

1 2

100K_0402_5%

@R519 for power saving.

0130.

21

D33

GREEN_BATLED#

Del D35 & @523 for power saving. 0130

KB_RST# <21>

100K_0402_5%

13

D

2

G

S

ADP_PRES CRACK_BGA BATCON THM_TRAVEL#

ADP_ID

G_BATLED# <21>

Q44

Q44 2N7002_SOT23

2N7002_SOT23

1 2

R523 100K_0402_5%@R523 100K_0402_5%@

1 2

R525 100K_0402_5%R525 100K_0402_5%

1 2

R322 100K_0402_5%@R322 100K_0402_5%@

1 2

R320 100K_0402_5%R320 100K_0402_5%

1 2

R624 10K_0402_5%R624 10K_0402_5%

Keep location as PR154. 12/4

KBC_PWR_ON

1 2

R622 10K_0402_5%R622 10K_0402_5%

Add in 12/3.

RP21

Add in 2/1.

PGD_IN

1 2

R532 10K_0402_5%R532 10K_0402_5%

C505 10P_0402_25V8K @C505 10P_0402_25V8K @

CLK_14M_KBC <16> ADP_EN <44>

PM_PWROK <8,22,42,43>

VCC1_PWRGD <32,35,39>

9/21

LANLINK_STATUS# no longer read by KBC. Add R333 between signal and pin 65. 10/08 Install R57. 10/08

Title

Size Document Number Rev

Date: Sheet

1 2

401554

VCC1_PWRGDPM_PWROK

2 1

D36 CH751H-40_SC76D36 CH751H-40_SC76

Compal Electronics, Inc.

SCHEMATIC, M/B LA-4021P

RP21

4.7K_1206_8P4R_5%

4.7K_1206_8P4R_5% SMB_EC_CK1 SMB_EC_DA1 AB1B_CLK AB1B_DATA

33 36Wednesday, June 03, 2009

1 8 2 7 3 6 4 5

of

+3VL

B

DOCKING CONNECT

10/23

VA

C5110.1U_0603_50V C5110.1U_0603_50V

1

2

C5120.1U_0603_50V C5120.1U_0603_50V

C5130.1U_0603_50V C5130.1U_0603_50V

1

2

C5150.1U_0603_50V C5150.1U_0603_50V

C5140.1U_0603_50V C5140.1U_0603_50V

1

2

C5160.1U_0603_50V C5160.1U_0603_50V

C5170.1U_0603_50V C5170.1U_0603_50V

1

2

C5180.1U_0603_50V C5180.1U_0603_50V

1

2

10/23

VA

MDO0+<25> MDO0-<25> MDO1+<25> MDO1-<25>

+5VALW +5VALW

+5VS

USB20_P9<22> USB20_N9<22>

STB_LED<19,30>

GREEN<17>

DLINE_OUT_L<28> DLINE_OUT_R<28>

T125T125 T126T126

BLUE<17>

RED<17>

PREP#

JP35

56

53 51 49

47 45 43

37 35 33 31 29 27 25 23 21 19 17 15 13 11

9 7 5 3 1

54

53

52

51

50

49

50

48

47

48

46

45

46

44

43

44

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

55

Delete:

1. L21 ~ L23.

2. C605 ~ C610.

3. R635 ~ R637.

4. U27 ~ U29.

5. C519 ~ C521.

6. R548 ~ R550.

FOX_QL0127L-C24E51-4F_54P-TCONN@

MDO2+ <25> MDO2- <25> MDO3+ <25> MDO3- <25>

LANLINK_STATUS#_DOCK <25>

PREP#

LAN_ACT#_DOCK <25>

ADP_SIGNAL <37,44>

ON/OFF# <30>

PREP# <22,25> D_DDCDATA <17> D_DDCCLK <17>

D_HSYNC <17>

D_VSYNC <17>

LINE_IN_SENSE <28>

DOCK_HPS# <29>

DOCK_LINE_IN_L <28>

DOCK_LINE_IN_R <28>

Change for can't charge issue. 10/24

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2005/03/10 2006/03/10

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, M/B LA-4021P

401554

34 36Wednesday, June 03, 2009

of

B

Update per change list. 9/14

Change value for SI1. 01/30

M_PWROKM_PWROK

+1.5VS_PG<41>

D38

CH751H-40_SC76

+VCCP

M_PROK<41>

+3VM +0.9V

DDR2_PG<40>

R554 3.3K_0402_5%

+5VS

R555 113K_0603_1%

+3VS

R559 75K_0402_1%R559 75K_0402_1%

21

D43 CH751H-40_SC76D43 CH751H-40_SC76

R478 23.7K_0402_1%R478 23.7K_0402_1%

1 2

Change value for PV-R. 07/08 C527=0.033UF, R564=1K, R385=1K

KBC Power OK

update KBC power good. 9/19

12

1 2

R560 3.3K_0402_5%

2 1

1 2 1 2 1 2 1 2

+3VL

R591

1 2

R592

1 2

12

154K_0402_1%

1

2

C216

R561

R561 28K_0402_1%

28K_0402_1%

R564 1K_0402_5% R564 1K_0402_5% R566 49.9K_0603_1%

R566 49.9K_0603_1% R509 13.7K_0402_1%R509 13.7K_0402_1% R386 1K_0402_5%

R386 1K_0402_5%

23.7K_0402_1%

51.1K_0402_1%

9/21

C215

0.1U_0402_16V4Z

0.1U_0402_16V4Z 1 2

2VREF_8734

R556 10K_0402_5% R556 10K_0402_5%

2VREF_8734

R558 30.1K_0402_5%

R558 30.1K_0402_5% R479 44.2K_0402_1%R479 44.2K_0402_1%

SLP_S3# <22,24,26,28,33,36,38,41,42,44>

12

C526

C526 3300P_0402_50V7K

3300P_0402_50V7K

R565 10K_0402_5% R565 10K_0402_5%

12

R567

R552 23.7K_0402_1%R552 23.7K_0402_1%

1 2

12

R584

2200P_0402_50V7K

100K_0402_5%

2

G

C527

0.033U_0402_16V7K

VLVL

12

R510

R510 1M_0402_5%

1M_0402_5%

13

D

2N7002_SOT23

2N7002_SOT23 Q1

Q1

S

+3VS

12

R553

R553 10K_0402_5%

10K_0402_5%

1 2

J6 SHORT PADSJ6 SHORT PADS

+3VALW

R563

3.3K_0402_5%

1 2

M_PWROK

12 12

12

2VREF_393

R551

R551 1M_0402_5%

1M_0402_5%

12

+5VALW

8

U30A

3

P

+

1

O

2

-

G

LM393M_SO8

4

1

C523

C523 1000P_0402_50V7K

1000P_0402_50V7K

2

R562 1M_0402_5%

5 6

+5VALW

8

P

+

-

G

LM393M_SO8

4

U30B

12

7

O

Change 10K to 3.3K, due to M_PWROK too low (about 2.86V). 03/28

Change value for SI1. 01/30

To reduce hysteresis on PWR_GD & M_PWROK, make following changes: R554=3.3k, R555=113k, R556=10k, R559=75k, R560=3.3k, R478=23.7k, R561=28k, C526=3300pF; R566=49.9k, R509=13.7k, R567=154k, R565=10k; remove R625, and move D43 close to D38 and connect D43-2 to D38-2 and D43-1 to SLP_S3#.

R514 1M_0402_5%R514 1M_0402_5%

3 2

VL

8

P

+

-

G

LM393M_SO8

4

12

U3A

1

O

R611 10K_0402_5%R611 10K_0402_5%

1 2

Change value for DB2. 12/11

Change R555 from 169K to 365K. Change R559 from 113K to 237K. Change R478 from 35.7K to 76.8K. Change R561 from 40.2K to 90.9K. Change R566 from 76.8K to 158K. Change R509 from 21K to 43.2K. Change R567 from 187K to 499K.

PWR_GD <33,42>

M_PWROK <8,22>

+3VL

VCC1_PWRGD <32,33,39>

WWAN Card STANDOFF

H3

H4

HOLEAH3HOLEA

HOLEAH4HOLEA

1

MDC STANDOFF

H5

H6

HOLEAH5HOLEA

HOLEAH6HOLEA

1

Del H1, H7 & H8. 1/18

H11

H10

H9 HOLEAH9HOLEA

H17

H17 HOLEA

HOLEA

1

FM1FM1

1

HOLEA

1

H18

H18 HOLEA

HOLEA

1

FM2FM2

HOLEA

1

H19

H19 HOLEA

HOLEA

1

FM3FM3

1

H12

H12 HOLEA

HOLEA

1

H20

H20 HOLEA

HOLEA

1

FM4FM4

JESD1

CLIP PAD

1

H13

H13 HOLEA

HOLEA

H21

H21 HOLEA

HOLEA

JESD2

CLIP PAD

1

H27

H27 HOLEA

HOLEA

1

H14

H14 HOLEA

HOLEA

JESD3

JESD3 CLIP PAD

CLIP PAD

1

CPU support

H22

H22 HOLEA

HOLEA

1

H30

H30 HOLEA

HOLEA

1

H15

H15 HOLEA

HOLEA

1

JESD4

JESD4 CLIP PAD

CLIP PAD

1

H23

H23 HOLEA

HOLEA

1

H16

H16 HOLEA

HOLEA

1

H26

H26 HOLEA

HOLEA

1

H24

H24 HOLEA

HOLEA

1

H25

H25 HOLEA

HOLEA

1

H31

H31 HOLEA

HOLEA

1

H28

H28 HOLEA

HOLEA

1

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2005/05/26 2006/07/26

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, M/B LA-4021P

401554

of

35 36Wednesday, June 03, 2009

of

35 36Wednesday, June 03, 2009

of

35 36Wednesday, June 03, 2009

B

A

Modify at 7/31 after discuss with power team.

+1.05VM to +VCCP Transfer

D

Q85

Q85 2N7002_SOT23

2N7002_SOT23

S

+VCCP+1.05VM

1 2 36

1

C543

2

0.1U_0402_16V4Z

Q51

Q51 AO4430 1N SOIC-8

AO4430 1N SOIC-8 8 7

RUNON

5

R645

R645 820K_0402_5%

820K_0402_5%

2

G

4

12

13

1 1

1

C596

C542

2

10U_0805_10V4Z

0.1U_0402_16V4Z

add 820k ohm divider with AC select 7/15

ADP_PRES<24,33,38>

+3VALW to +3VM_WOL Transfer

To increase voltage margin, change pull-up rail on R518 from +3VALW to B+. 1/31

1

C497

2

10U_0805_10V4Z

PM_SLP_M#<22,33,40,41>

B

R518

R518 100K_0402_5%

100K_0402_5%

BSS138_SOT23

PM_SLP_M#

LAN_WOL_EN<22,33>

C

+3VALW +3VM_WOL

U33

B+

2

G

13

D

Q50

Q50 BSS138_SOT23

BSS138_SOT23

S

12

13

D

S

B+

12

2

G

LAN_WOL_EN#

13

D

S

R576

100K_0402_5%

R577

100K_0402_5%@

Q47

+3VALW

12

R612

R612 100K_0402_5%

100K_0402_5%

2

G

10U_0805_10V4Z

Q76

Q76 BSS138_SOT23

BSS138_SOT23

C218

1

2

U33 8 7 6 5

SI4800DY_SO8

3VM_WOL_EN

12

R613

R613 470_0402_5%

470_0402_5%

1

C469

0.01U_0402_25V7K

2

1

S

D

2

S

D

3

S

D

4

1

C470

G

D

C470

2

0.1U_0402_16V4Z

D

1

C473

C473 10U_0805_10V4Z

10U_0805_10V4Z

2

Discharge circuit-2 for V-M

+1.05VM

12

R580

R580 470_0402_5%

470_0402_5%

13

D

2

G

Q53

Q53 RHU002N06_SOT323

RHU002N06_SOT323

G

S

LAN_WOL_EN#

Q77

Q77 RHU002N06_SOT323

RHU002N06_SOT323

+3VM_WOL

2

G

E

LAN_EN#LAN_EN#

Q54

Q54 RHU002N06_SOT323

RHU002N06_SOT323

12

R614

R614 470_0402_5%

470_0402_5%

13

D

Add in 9/21

S

+3VM

12

R581

R581 470_0402_5%

470_0402_5%

13

D

2

G

S

Add in 9/21

+3VALW to +3VM Transfer

+3VALW to +3VS Transfer

+3VS+3VALW

1

S

2

S

3

S

4

1

G

1

2

C539

0.1U_0402_16V4Z

R578

R578 330K_0402_5%

330K_0402_5%

SLP_S3

2

G

B+

12

J7

J7 SHORT PADS

SHORT PADS

13

D

Q52

Q52 RHU002N06_SOT323

RHU002N06_SOT323

S

1

C538

C538 10U_0805_10V4Z

10U_0805_10V4Z

2

RUNON

U35

U35 SI4800DY_SO8

SI4800DY_SO8

8

D

7

D

6

D

5

D

12

R579

R579 470_0402_5%

470_0402_5%

1

C541

0.01U_0402_25V7K

2

2 2

+5VALW to +5VS Transfer

S S S

G

RUNON

+5VS+5VALW

1 2 3 4

1

2

C545

0.1U_0402_16V4Z

1

C546

C546 10U_0805_10V4Z

10U_0805_10V4Z

2

U36

3 3

1

2

8 7 6 5

C544

C544 10U_0805_10V4M

10U_0805_10V4M

U36 SI4800DY_SO8

SI4800DY_SO8

D D D D

To increase voltage margin, change pull-up rail on R574 from +3VALW to B+. 1/31

C540

10U_0805_10V4Z

SLP_S5#<22> SLP_S4#<22,40>

R574

R574 100K_0402_5%

100K_0402_5%

Q49

BSS138_SOT23

PM_SLP_M#

2

G

Design Change at 9/14.

SLP

13

D

2

G

Q55

Q55 RHU002N06_SOT323@

RHU002N06_SOT323@

G

S

B+

12

13

D

S

LAN_EN#

SLP

Q57

Q57 RHU002N06_SOT323

RHU002N06_SOT323

R573

R573 100K_0402_5%

100K_0402_5%

2

G

+3VL

12

13

D

2

G

S

B+

12

13

D

Q48

Q48 BSS138_SOT23

BSS138_SOT23

S

R583

R583 100K_0402_5%

100K_0402_5%

10U_0805_10V4Z

+3VALW +3VM

8

1

2

12

1

2

SLP_S3#<22,24,26,28,33,35,38,41,42,44>

7 6 5

R575

R575 470_0402_5%

470_0402_5%

C537

0.01U_0402_25V7K

Q56

Q56 RHU002N06_SOT323

RHU002N06_SOT323

C531

U32

D D D D

SI4800DY_SO8

3VM_EN

SLP_S3

S S S G

2

G

1 2 3 4

+3VL

12

13

D

S

1

C532

2

R582

R582 100K_0402_5%

100K_0402_5%

0.1U_0402_16V4Z

1

C533

C533 10U_0805_10V4Z

10U_0805_10V4Z

2

Discharge circuit-1

Issued Date

Add in 1/31.

SLP_S3

2

G

C

+VCCP

12

R631

R631 470_0402_5%

470_0402_5%

13

D

Q82

S

RHU002N06_SOT323

Compal Secret Data

2006/02/13 2006/07/26

Compal Secret Data

SLP

Deciphered Date

2

G

12

R590

R590 470_0402_5%

470_0402_5%

13

D

Q62

S

RHU002N06_SOT323

D

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, M/B LA-4021P

401554

E

of

36 36Wednesday, June 03, 2009

of

36 36Wednesday, June 03, 2009

of

36 36Wednesday, June 03, 2009

B

SLP_S3

+3VS

2

G

12

R587

R587 470_0402_5%

470_0402_5%

13

D

Q59

S

RHU002N06_SOT323

+1.5VS +1.8V

12

R588

R588 470_0402_5%

470_0402_5%

13

D

2

G

D

Q60

S

RHU002N06_SOT323

SLP_S3

+5VS

2

G

12

R589

R589 470_0402_5%

470_0402_5%

13

D

Q61

S

RHU002N06_SOT323

+0.9V

12

R586

R586 470_0402_5%

470_0402_5%

13

D

2

G

D

Q58

S

RHU002N06_SOT323

SLP

4 4

Del PWR_GD from Q59.1. 12/11

A

B

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

COMPAL LA-4021 Schematics

Specifications and Main Features

Frequently Asked Questions

User Manual