Compal LA-3821P, Vostro 1200, N6000W Schematic

A

1 1

2 2

B

C

D

E

Compal confidential

Schematics Document

Mobile Merom uFCPGA with Satna Rosa Platform

3 3

2007-07-24

REV:0.3

4 4

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2006/02/13 2006/07/26

Compal Secret Data

Deciphered Date

Title

Size Doc ument Number Re v

Cus tom

D

Date: Sheet of

Compal Electronics, Inc.

Cover Sheet

LA-3821P

E

1 43Tues day, July 31, 2007

0.3

A

B

C

D

E

Compal confidential

File Name : LA-3821P

ZZZ 1

PCB

1 1

Supra 1.0 (Merom +Crestline+ICH8) 12"

Fan Control

page 4

H_ A#( 3.. 31)

Mobile Y onah/Merom

uFCPGA-478 CPU

Socket P

FSB

533/ 667/800MHz

H_ D#( 0..6 3)

Thermal Sensor
AD M1032A R

page 4page 4,5,6

DDR2 -4 00/533/667

Clock Generator

ICS 9LPRS355

page 15

DDR2-SO-DIMM X2

BANK 0, 1, 2, 3

page 13,14

LVDS Conn

pa ge 17

LED

page 28

2 2

NB Crestline

page 7,8,9,10,11,12

RTC CKT.

page 19

DM I

PCI-E BUS

SB ICH8

Ma rvall

Giga L AN 8 055

page 26

3 3

RJ45CONN

page 27

Mini-Card
WLAN

page 22

Mini-Card
Robe son

page 22

New card

page 23

page 18,19,20,21

Dual Channel

AC-LINK/Azalia

PATA Master

USB2.0

USB2.0

USB2.0

USB2.0

SATA

Bluetooth Ver:2.0
Conn

FingerPrinter
Conn

PC Camera
Conn

Card Reader
RTS5158

USB Conn X 3

page 29

page 29

page 29

page 26

page 29

Audio Realtek

ALC268

page 24

SATA HDD Connector

page 22

IDE ODD Connector

page 22

RJ11CONN

page 26

MD C V1.5

page 26

AMON Agere

CS P 1 040

page 28

AMP & Audio Jack
TP A6017A2

page 26

LPC BUS

Power On/Off CKT.

page 28

4 4

DC/DC Interface CKT.

page 31

Touch Pad CONN.

Power Circuit DC/DC

Page 3 2,33,34,35,36,37,38

A

B

ENE KB926

page 30

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

SPI

Int.KBD

page 30page 28

2006/02/13 2006/07/26

SPI ROM

25LF080A

page 29

Compal Secret Data

Deciphered Date

Title

Size Doc ument Number Re v

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D

Date: Sheet of

Compal Electronics, Inc.

Block Diagram

LA-3821P

E

2 43Tues day, July 31, 2007

0.3

5

4

3

2

1

Voltage Rails

+5VS

power
plane

D D

State

+B

+5VALW

+3VALW

+1.8V

+3VS

+1.5VS

+1.25V S

+0.9V

+VCCP

+CPU_CORE

Symbol Note :

S0

S1

S3

S5 S4/AC

S5 S4/ Battery only

S5 S4/AC & Battery

C C

B B

don't exist

O

O

O

O

O

X

I2C / SMBUS ADDRESSING

DE VICE

DD R SO -D IMM 0

DD R SO -D IMM 1

CL OCK GENE RATO R (E XT .)

HEX

A 0

D2

O

O

O

O

X

O

X X

X

X X X

AD DR ESS

1 0 1 0 0 0 0 0

1 0 1 0 0 1 0 0A 4

1 1 0 1 0 0 1 0

OO

OO

X

X

SMBUS Control Table

SOURCE

SMB_EC_CK1
SMB_EC_DA1

SMB_EC_CK2
SMB_EC_DA2

SMB_CK_CLK1
SMB_CK_DAT1 ICH8

LCD_CLK
LCD_DAT

KB925

KB925

Cre stl ine

INVERTER BATT EEPROM

X
X

X

X X

: means Digital Ground

: means Analog Ground

@ : means just reserve , no build
DEBUG@ : means just reserve for debug.

SERIAL SENSOR

V V

X X

X

THERMAL

(CPU)

ADM103 2

X X

V

X

X

X X

SODIMM CLK CHIP

X

V V V

X X

X
X

MINI CARD

X X
X

X

LCD

X

X

V

A A

BOM: 43XXXXXX

Jump-Short: PJP?

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/02/13 2006/07/26

Compal Secret Data

Deciphered Date

Title

Size Doc ument Number Re v

2

Date: Sheet of

Compal Electronics, Inc.

Notes List

LA-3821P

3 43Tues day, July 31, 2007

1

0.3

5

D D

4

3

2

1

GND
GND
GND
GND

+3VS

C3

H_THERMDA

H_THERMDC

THERM#

8
7
6
5

7/23

2

1

U1

1

VDD

2

D+

3

D-

THERM#4GND

ADM1032ARMZ-2REEL_MSOP8

Addres s:100_1100

SCLK

SDATA

ALERT#

+5VS

12

12

BAS16_SOT23-3

SMB_EC_CK2

8

SMB_EC_DA2

7

6

5

SMB_EC_DA230,32

SMB_EC_CK230,32

D1

1SS355_SOD323-2

1

D2

C5

2

SMB_EC_DA2
SMB_EC_CK2

+VCC_F AN

FAN_SPEED

1

C6

2

4.7U_0805_10V4Z
1000P_0402_50V7K

JP3

1

1

2

2

3

3

4

GND

5

GND

ACES_85205-03001

+VCCP

H_A#[ 3..16]7

H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16

H_NMI19
H_SMI#19

12

R18

56_0402_5%@

B

2

C

Q2
MMBT3904_SOT23

H_ADSTB#0

H_REQ#0
H_REQ#1
H_REQ#2

H_REQ#4

H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35
H_ADSTB#1

H_A20M#
H_FER R#
H_IGNN E#

H_STPCLK#
H_INT R
H_NMI
H_SMI#

OCP# 20

H_ADSTB#07

H_REQ#07
H_REQ#17
H_REQ#27
H_REQ#37
H_REQ#47

C C

B B

A A

H_A#[ 17..35]7

H_ADSTB#17

H_A20M#19

H_FER R#19

H_IGNN E#19

H_STPCLK#19
H_INT R19

+VCCP

H_PROCH OT# OCP#

E

3 1

@

JP2A

ADDR GROUP 0 ADDR GROUP 1

J4

A[3]#

L5

A[4]#

L4

A[5]#

K5

A[6]#

M3

A[7]#

N2

A[8]#

J1

A[9]#

N3

A[10]#

P5

A[11]#

P2

A[12]#

L2

A[13]#

P4

A[14]#

P1

A[15]#

R1

A[16]#

M1

ADSTB[0]#

K3

REQ[0]#

H2

REQ[1]#

K2

REQ[2]#

J3

REQ[3]#

L1

REQ[4]#

Y2

A[17]#

U5

A[18]#

R3

A[19]#

W6

A[20]#

U4

A[21]#

Y5

A[22]#

U1

A[23]#

R4

A[24]#

T5

A[25]#

T3

A[26]#

W2

A[27]#

W5

A[28]#

Y4

A[29]#

U2

A[30]#

V4

A[31]#

W3

A[32]#

AA4

A[33]#

AB2

A[34]#

AA3

A[35]#

V1

ADSTB[1]#

A6

A20M#

A5

FERR#

C4

IGNNE#

D5

STPCLK#

C6

LINT0

B4

LINT1

A3

SMI#

M4

RSVD[01]

N5

RSVD[02]

T2

RSVD[03]

V3

RSVD[04]

B2

RSVD[05]

C3

RSVD[06]

D2

RSVD[07]

D22

RSVD[08]

D3

RSVD[09]

F6

RSVD[10]

Mero m Ball-out Rev 1a

CONN@

SP07000FP00 S SOCKET TYCO 2-1871873-2 478P H3 CPU
SP07000FD00 S SOCKET FOXCONN PZ4782A-274M-41 478P H3

DEFER#

CONTROL

RESET#

BPM[0]#
BPM[1]#
BPM[2]#
BPM[3]#

XDP/ITP SIGNALS

TH ERMAL

PROCHOT#

THERMDA
THERMDC

ICH

THERMTRIP#

H CLK

BCLK[0]
BCLK[1]

RESERVED

ADS#
BNR#

BPRI#

DRDY#
DBSY#

BR0#

IERR#

INIT#

LOCK#

RS[0]#
RS[1]#
RS[2]#

TRDY#

HIT#

HITM#

PRDY#
PREQ#

TCK

TDO
TMS

TRST#

DBR#

TDI

H_ADS#H_A#3

H1

H_BNR #

E2

H_BPR I#

G5

H_DEF ER#

H5

H_D RDY#

F21

H_ DBSY#

E1

H_BR0#

F1

H_IER R#

D20

H_INIT#

B3

H_LOCK#

H4

H_RESET#

C1

H_RS#0

F3

H_RS#1

F4

H_RS#2

G3

H_ TRDY#H_REQ#3

G2

H_HIT#

G6

H_HITM#

E4

AD4
AD3
AD1
AC4
AC2
AC1

XDP_TCK

AC5

XDP_TDI

AA6
AB3

XDP_TMS

AB5

XDP_TRST#

AB6

XDP_DBRESET#

C20

H_PROCH OT#

D21

H_THERMDA_R

A24

H_THE RMDC_R

B25

H_THERMTRIP#

C7

CLK_CP U_BCLK

A22

CLK_CP U_BCLK#

A21

For Mero m, R14 and R 15 are 0ohm
For Penr yn, R14 an d R15 are 10 0ohm.

H_ADS# 7
H_BNR # 7

H_BPR I# 7

H_DEF ER# 7
H_D RDY# 7
H_D BSY# 7

H_BR0# 7

H_INIT# 19

H_LOCK# 7

H_RESET# 7

H_RS#0 7

H_RS#1 7

H_RS#2 7

H_T RDY# 7

H_HIT# 7
H_HITM# 7

XDP_DBRESET# 20

R14 0_0402_5%

1 2

R15 0_0402_5%

1 2

FAN_SPEED32

R10

56_0402_5%

12

+VCCP

C2 0.1 U_0402_16V4Z

1 2

EMI request 4/1 8

R13

12

68_0402_5%

CLK_CP U_BCLK 15
CLK_CP U_BCLK# 15

H_THERMDA, H_THERMDC routing together,
Trace width / Spacing = 10 / 10 mil

H_THERMDA
H_THERMDC

H_THERMTRIP# 7,19

FAN_SPEED

+VCCP

H_PRO CHOT#

+3VS

R17
10K_0402_5%

1 2

1

C13

2

1000P_0402_50V7K

EN_FAN32

XDP_TDI

XDP_TMS

XDP_TRST#

XDP_TCK

R2 54.9_0402_1%

1 2

R3 54.9_0402_1%

1 2

R7 51_0402_1%

1 2

R8 54.9_0402_1%

1 2

Thermal Sensor ADM1032ARMZ

0.1U_0402_16V4Z

C4

1 2

2200P_0402_50V7K

R16

1 2

+3VS

10K_0402_5%

Voltage Fan Control circuit

+5VS

+VCC_F AN

C12

1 2

4.7U_0805_10V4Z

U24

1

VEN

2

VIN

3

VO

4

VSET

G993P1UF_SOP8

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/02/13 2006/03/10

Compal Secret Data

Deciphered Date

Title

Size Doc ument Number Re v

Cus tom

2

Date: Sheet of

Compal Electronics, Inc.

Merom(1/3)-AGTL+/XDP

LA-3821P

1

4 43Tues day, July 31, 2007

0.3

5

4

3

2

1

H_D #[0..15]7

D D

H_DSTBN#07
H_DSTBP#07

H_DIN V#07

H_D# [16..31]7

C C

H_DSTBN#17
H_DSTBP#17

H_DIN V#17

R21 1K_0402_5%@

1 2

R22 1K_0402_5%@

1 2

C8 0.1U_0402_16V4Z@

1 2

CPU_BSEL015
CPU_BSEL115
CPU_BSEL215

T1

T2
T3

H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_DSTBN#0
H_DSTBP#0
H_DIN V#0

H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_DSTBN#1
H_DSTBP#1
H_DIN V#1 H_DIN V#3

V_CPU_GTLREF

TEST1
TEST2
TEST3
TEST4
TEST5
TEST6

CPU_BSEL0 H_PW RGOOD
CPU_BSEL1
CPU_BSEL2

JP2B

E22

D[0]#

F24

D[1]#

E26

D[2]#

G22

D[3]#

F23

D[4]#

G25

D[5]#

E25

D[6]#

E23

D[7]#

K24

D[8]#

G24

D[9]#

J24

D[10]#

J23

D[11]#

H22

D[12]#

F26

D[13]#

K22

D[14]#

H23

D[15]#

J26

DSTBN[0]#

H26

DSTBP[0]#

H25

DINV[0]#

N22

D[16]#

K25

D[17]#

P26

D[18]#

R23

D[19]#

L23

D[20]#

M24

D[21]#

L22

D[22]#

M23

D[23]#

P25

D[24]#

P23

D[25]#

P22

D[26]#

T24

D[27]#

R24

D[28]#

L25

D[29]#

T25

D[30]#

N25

D[31]#

L26

DSTBN[1]#

M26

DSTBP[1]#

N24

DINV[1]#

AD26

GTLREF

C23

TEST1

D25

TEST2

C24

TEST3

AF26

TEST4

AF1

TEST5

A26

TEST6

B22

BSEL[0]

B23

BSEL[1]

C21

BSEL[2]

Mero m Ball-out Rev 1 a

CONN@

DATA GRP 1

MISC

DATA GRP 0

D[32]#
D[33]#
D[34]#
D[35]#
D[36]#
D[37]#
D[38]#
D[39]#
D[40]#
D[41]#
D[42]#
D[43]#
D[44]#
D[45]#

DATA GRP 2DATA GRP 3

D[46]#

D[47]#
DSTBN[2]#
DSTBP[2]#

DINV[2]#

D[48]#

D[49]#

D[50]#

D[51]#

D[52]#

D[53]#

D[54]#

D[55]#

D[56]#

D[57]#

D[58]#

D[59]#

D[60]#

D[61]#

D[62]#

D[63]#
DSTBN[3]#
DSTBP[3]#

DINV[3]#

COMP[0]
COMP[1]
COMP[2]
COMP[3]

DPRSTP#

DPSLP#

DPWR#

PWRGOOD

SLP#

PSI#

Y22
AB24
V24
V26
V23
T22
U25
U23
Y25
W22
Y23
W24
W25
AA23
AA24
AB25
Y26
AA26
U22

AE24
AD24
AA21
AB22
AB21
AC26
AD20
AE22
AF23
AC25
AE21
AD21
AC22
AD23
AF22
AC23
AE25
AF24
AC20

R26
U26
AA1
Y1

E5
B5
D24
D6
D7
AE6

H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_DSTBN#2
H_DSTBP#2
H_DIN V#2

H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
H_DSTBN#3
H_DSTBP#3

COMP0
COMP1
COMP2
COMP3

H_DPRSTP#
H_DPSLP#
H_DPW R#

H_CPUSLP #
H_PSI#

layo ut n ote: Rout e TEST3 & TEST5 trac es on ground referenced layer to th e TPs

CPU_BSEL CPU_BSEL2 CPU_BSEL1

166

B B

200

0 1

0

1

CPU_BSEL0

1

0

H_D# [32..47] 7

H_DSTBN#2 7
H_DSTBP#2 7
H_DIN V#2 7
H_D# [48..63] 7

H_DSTBN#3 7
H_DSTBP#3 7
H_DIN V#3 7

H_DPRSTP# 7,1 9,39

H_DPSLP# 19
H_DPW R# 7
H_PW RGOOD 19

H_CPUSLP # 7
H_PSI# 39

12

12

R23

54.9_0402_1%

Resistor placed within

0.5" of CPU pin.Trace
should be at least 25
mils away from any other
toggling signal.
COMP[0,2] trace width is
18 mils. COMP[1,3] trace
width is 4 mils.

12

12

R26

R25

R24

27.4_0402_1%

54.9_0402_1%

27.4_0402_1%

+VCC_C ORE +VCC_C ORE

JP2C

A7

VCC[001]

A9

VCC[002]

A10

VCC[003]

A12

VCC[004]

A13

VCC[005]

A15

VCC[006]

A17

VCC[007]

A18

VCC[008]

A20

VCC[009]

B7

VCC[010]

B9

VCC[011]

B10

VCC[012]

B12

VCC[013]

B14

VCC[014]

B15

VCC[015]

B17

VCC[016]

B18

VCC[017]

B20

VCC[018]

C9

VCC[019]

C10

VCC[020]

C12

VCC[021]

C13

VCC[022]

C15

VCC[023]

C17

VCC[024]

C18

VCC[025]

D9

VCC[026]

D10

VCC[027]

D12

VCC[028]

D14

VCC[029]

D15

VCC[030]

D17

VCC[031]

D18

VCC[032]

E7

VCC[033]

E9

VCC[034]

E10

VCC[035]

E12

VCC[036]

E13

VCC[037]

E15

VCC[038]

E17

VCC[039]

E18

VCC[040]

E20

VCC[041]

F7

VCC[042]

F9

VCC[043]

F10

VCC[044]

F12

VCC[045]

F14

VCC[046]

F15

VCC[047]

F17

VCC[048]

F18

VCC[049]

F20

VCC[050]

AA7

VCC[051]

AA9

VCC[052]

AA10

VCC[053]

AA12

VCC[054]

AA13

VCC[055]

AA15

VCC[056]

AA17

VCC[057]

AA18

VCC[058]

AA20

VCC[059]

AB9

VCC[060]

AC10

VCC[061]

AB10

VCC[062]

AB12

VCC[063]

AB14

VCC[064]

AB15

VCC[065]

AB17

VCC[066]

AB18

VCC[067]

Mero m Ball-out Rev 1a

CONN@

VCC[068]
VCC[069]
VCC[070]
VCC[071]
VCC[072]
VCC[073]
VCC[074]
VCC[075]
VCC[076]
VCC[077]
VCC[078]
VCC[079]
VCC[080]
VCC[081]
VCC[082]
VCC[083]
VCC[084]
VCC[085]
VCC[086]
VCC[087]
VCC[088]
VCC[089]
VCC[090]
VCC[091]
VCC[092]
VCC[093]
VCC[094]
VCC[095]
VCC[096]
VCC[097]
VCC[098]
VCC[099]
VCC[100]

VCCP[01]
VCCP[02]
VCCP[03]
VCCP[04]
VCCP[05]
VCCP[06]
VCCP[07]
VCCP[08]
VCCP[09]
VCCP[10]
VCCP[11]
VCCP[12]
VCCP[13]
VCCP[14]
VCCP[15]
VCCP[16]

VCCA[01]
VCCA[02]

VID[0]
VID[1]
VID[2]
VID[3]
VID[4]
VID[5]
VID[6]

VCCSENSE

VSSSENSE

AB20
AB7
AC7
AC9
AC12
AC13
AC15
AC17
AC18
AD7
AD9
AD10
AD12
AD14
AD15
AD17
AD18
AE9
AE10
AE12
AE13
AE15
AE17
AE18
AE20
AF9
AF10
AF12
AF14
AF15
AF17
AF18
AF20

R19 0_0402_5%

G21
V6

R20 0_0402_5%

J6
K6
M6
J21
K21
M21
N21
N6
R21
R6
T21
T6
V21
W21

B26
C26

AD6
AF5
AE5
AF4
AE3
AF3
AE2

VCCSENS E

AF7

VSSSENSE

AE7

.

Length match within 25 mils.

+VCCP

12
12

1

C7

+

2

CPU_V ID0 39
CPU_V ID1 39
CPU_V ID2 39
CPU_V ID3 39
CPU_V ID4 39
CPU_V ID5 39
CPU_V ID6 39

VCCSENSE 39

VSSSENSE 39

330U_D2E_2.5VM _R7

1

C9

2

1

C10

2

0.01U_0402_16V7K

10U_0805_6.3V6M

Near pin B26

+1.5VS

The trace width/space/other is
20/7/25.

+VCC_ CORE

1 2

1 2

R29
100_0402_1%

R31
100_0402_1%

VCCSENS E

VSSSENSE

V_CPU_GTLREF

+VCCP

12

R28
1K_0402_1%

12

R30
2K_0402_1%

Close to CPU pin AD26
within 500mils.

A A

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/02/13 2006/03/10

Compal Secret Data

Deciphered Date

2

Close to CPU pin
within 500mils.

Title

Size Doc ument Number Re v

Cus tom

Date: Sheet of

Compal Electronics, Inc.

Merom(2/3)-AGTL+/PWR

LA-3821P

1

5 43Tues day, July 31, 2007

0.3

5

D D

JP2D

A4

VSS[001]

A8

VSS[002]

A11

VSS[003]

A14

VSS[004]

A16

VSS[005]

A19

VSS[006]

A23

VSS[007]

AF2

VSS[008]

B6

VSS[009]

B8

VSS[010]

B11

VSS[011]

B13

VSS[012]

B16

VSS[013]

B19

VSS[014]

B21

VSS[015]

B24

VSS[016]

C5

VSS[017]

C8

VSS[018]

C11

VSS[019]

C14

VSS[020]

C16

VSS[021]

C19

VSS[022]

C2

VSS[023]

C22

VSS[024]

C25

VSS[025]

D1

VSS[026]

D4

VSS[027]

D8

VSS[028]

D11

C C

B B

VSS[029]

D13

VSS[030]

D16

VSS[031]

D19

VSS[032]

D23

VSS[033]

D26

VSS[034]

E3

VSS[035]

E6

VSS[036]

E8

VSS[037]

E11

VSS[038]

E14

VSS[039]

E16

VSS[040]

E19

VSS[041]

E21

VSS[042]

E24

VSS[043]

F5

VSS[044]

F8

VSS[045]

F11

VSS[046]

F13

VSS[047]

F16

VSS[048]

F19

VSS[049]

F2

VSS[050]

F22

VSS[051]

F25

VSS[052]

G4

VSS[053]

G1

VSS[054]

G23

VSS[055]

G26

VSS[056]

H3

VSS[057]

H6

VSS[058]

H21

VSS[059]

H24

VSS[060]

J2

VSS[061]

J5

VSS[062]

J22

VSS[063]

J25

VSS[064]

K1

VSS[065]

K4

VSS[066]

K23

VSS[067]

K26

VSS[068]

L3

VSS[069]

L6

VSS[070]

L21

VSS[071]

L24

VSS[072]

M2

VSS[073]

M5

VSS[074]

M22

VSS[075]

M25

VSS[076]

N1

VSS[077]

N4

VSS[078]

N23

VSS[079]

N26

VSS[080]
VSS[081]P3VSS[162]

Mero m Ball-out Rev 1a

VSS[082]
VSS[083]
VSS[084]
VSS[085]
VSS[086]
VSS[087]
VSS[088]
VSS[089]
VSS[090]
VSS[091]
VSS[092]
VSS[093]
VSS[094]
VSS[095]
VSS[096]
VSS[097]
VSS[098]
VSS[099]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
VSS[159]
VSS[160]
VSS[161]

VSS[163]

P6
P21
P24
R2
R5
R22
R25
T1
T4
T23
T26
U3
U6
U21
U24
V2
V5
V22
V25
W1
W4
W23
W26
Y3
Y6
Y21
Y24
AA2
AA5
AA8
AA11
AA14
AA16
AA19
AA22
AA25
AB1
AB4
AB8
AB11
AB13
AB16
AB19
AB23
AB26
AC3
AC6
AC8
AC11
AC14
AC16
AC19
AC21
AC24
AD2
AD5
AD8
AD11
AD13
AD16
AD19
AD22
AD25
AE1
AE4
AE8
AE11
AE14
AE16
AE19
AE23
AE26
A2
AF6
AF8
AF11
AF13
AF16
AF19
AF21
A25
AF25

.

Near CPU CORE regulator

C43

@

330U_D2E_2.5VM _R7

07/23 EMI solution

+VCCP

1

C48

0.1U_0402_16V4Z

2

4

3

2

1

Proadlizer

+VCC_ CORE+VCC_C ORE

1

1

1

+

+

2

C44

@

330U_D2E_2.5VM _R7

2

1

C49

0.1U_0402_16V4Z

2

1

C50

0.1U_0402_16V4Z

2

2

+

C11
1200P_PFAF250E128MNTTE_2.5VM

3 4

1

C51

0.1U_0402_16V4Z

2

1

C52

0.1U_0402_16V4Z

2

Plac e these inside
sock et cavity o n L8
(North side
Seco ndary)

1

C53

0.1U_0402_16V4Z

2

A A

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/02/13 2006/03/10

Compal Secret Data

Deciphered Date

Title

Size Doc ument Number Re v

Cus tom

2

Date: Sheet of

Compal Electronics, Inc.

Merom(3/3)-GND&Bypass

LA-3821P

1

6 43Tues day, July 31, 2007

0.3

5

M10
N12

W10

AD12

AE3
AD9
AC9

AC7
AC14
AD11
AC11

AB2

AD7

AB1

AC6

AE2

AC5

AG3

AH8

AJ14

AE9
AE11
AH12

AH5

AE7

AE5

AH2
AH13

E2

G2
G7
M6
H7
H3
G4

F3
N8
H2

N9
H5

P13

K9
M2

Y8

V4
M3

J1
N5
N3
W6
W9
N2

Y7
Y9

P4
W3
N1

Y3

AJ9

AJ5

AJ6

AJ7
AJ2

AJ3

B3
C2

W1
W2

B6

E5

B9

A9

U3A

H_D#_0
H_D#_1
H_D#_2
H_D#_3
H_D#_4
H_D#_5
H_D#_6
H_D#_7
H_D#_8
H_D#_9
H_D#_10
H_D#_11
H_D#_12
H_D#_13
H_D#_14
H_D#_15
H_D#_16
H_D#_17
H_D#_18
H_D#_19
H_D#_20
H_D#_21
H_D#_22
H_D#_23
H_D#_24
H_D#_25
H_D#_26
H_D#_27
H_D#_28
H_D#_29
H_D#_30
H_D#_31
H_D#_32
H_D#_33
H_D#_34
H_D#_35
H_D#_36
H_D#_37
H_D#_38
H_D#_39
H_D#_40
H_D#_41
H_D#_42
H_D#_43
H_D#_44
H_D#_45
H_D#_46
H_D#_47
H_D#_48
H_D#_49
H_D#_50
H_D#_51
H_D#_52
H_D#_53
H_D#_54
H_D#_55
H_D#_56
H_D#_57
H_D#_58
H_D#_59
H_D#_60
H_D#_61
H_D#_62
H_D#_63

H_SWING
H_RCOMP

H_SCOMP
H_SCOMP#

H_CPURST#
H_CPUSLP#

H_AVREF
H_DVREF

CRES TLINE_1p0

H_ADSTB#_0
H_ADSTB#_1

H_DEFER#

HOST

HPLL_CLK

HPLL_CLK#

H_DPWR#

H_DINV#_0
H_DINV#_1
H_DINV#_2
H_DINV#_3

H_DSTBN#_0
H_DSTBN#_1
H_DSTBN#_2
H_DSTBN#_3

H_DSTBP#_0
H_DSTBP#_1
H_DSTBP#_2
H_DSTBP#_3

H_REQ#_0
H_REQ#_1

H_REQ#_2
H_REQ#_3

H_REQ#_4

H_D #[0..63]5

D D

C C

+VCCP

12

12

R40

R41

54.9_0402_1%

54.9_0402_1%

H_RESET#4

H_CPUSLP #5

B B

H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57

H_D#59
H_D#60
H_D#61
H_D#62
H_D#63

H_SW NG
H_RCOMP

H_SCOMP
H_SCOMP#

H_RESET#
H_CPUSLP #

H_VRE F

layo ut note:

Rout e H_ SCOMP and H_SC OMP# with t race width, spacing and
impe danc e (55 o hm) same as FSB data tr aces

Layout Note:
H_RCOM P / H_VREF / H_SWNG

trace width and spacing is 10/20

+VCCP

R46

R52

12

221_0603_1%

H_SW NGH_VRE F

12

1

C61

2

100_0402_1%

0.1U_0402_16V4Z

+VCCP

12

R45

1K_0402_1%

A A

0.1U_0402_16V4Z

12

1

C60

R50

2

2K_0402_1%

H_RCOMP

12

R51

24.9_0402_1%

Near B3 pinwith in 100 mils from NB

5

H_A#_3
H_A#_4
H_A#_5
H_A#_6
H_A#_7
H_A#_8

H_A#_9
H_A#_10
H_A#_11
H_A#_12
H_A#_13
H_A#_14
H_A#_15
H_A#_16
H_A#_17
H_A#_18
H_A#_19
H_A#_20
H_A#_21
H_A#_22
H_A#_23
H_A#_24
H_A#_25
H_A#_26
H_A#_27
H_A#_28
H_A#_29
H_A#_30
H_A#_31
H_A#_32
H_A#_33
H_A#_34
H_A#_35

H_ADS#

H_BNR#

H_BPRI#

H_BREQ#

H_DBSY#

H_DRDY#

H_HIT#
H_HITM#

H_LOCK#
H_TRDY#

H_RS#_0
H_RS#_1
H_RS#_2

J13
B11
C11
M11
C15
F16
L13
G17
C14
K16
B13
L16
J17
B14
K19
P15
R17
B16
H20
L19
D17
M17
N16
J19
B18
E19
B17
B15
E17
C18
A19
B19
N19

G12
H17
G20
C8
E8
F12
D6
C10
AM5
AM7
H8
K7
E4
C6
G10
B7

K5
L2
AD13
AE13

M7
K3
AD2
AH11

L7
K2
AC2
AJ10

M14
E13
A11
H13
B12

E12
D7
D8

4

V_DDR _MCH_REF13,14,37

4

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35

H_ADS#
H_ADSTB#0
H_ADSTB#1
H_BNR #
H_BPR I#
H_BR0#
H_DEF ER#
H_ DBSY#
CLK_MCH_BCLK
CLK_MCH_BCLK#
H_DPW R#
H_D RDY#
H_HIT#
H_HITM#
H_LOCK#
H_ TRDY#

H_DIN V#0
H_DIN V#1
H_DIN V#2
H_DIN V#3

H_DSTBN#0H_D#58
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3

H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

H_RS#0
H_RS#1
H_RS#2

Layout Note:
V_DDR_MCH_REF
trace width and
spacin g is 20/20.

H_A#[ 3..35] 4

H_ADS# 4
H_ADSTB#0 4
H_ADSTB#1 4
H_BNR# 4
H_BPR I# 4
H_BR0# 4
H_DEF ER# 4
H_DB SY# 4
CLK_MCH_BCLK 15
CLK_MCH_BCLK# 15
H_DPW R# 5
H_D RDY# 4
H_HIT# 4
H_HITM# 4
H_LOCK# 4
H_TR DY# 4

H_DIN V#0 5
H_DIN V#1 5
H_DIN V#2 5
H_DIN V#3 5

H_DSTBN#0 5
H_DSTBN#1 5
H_DSTBN#2 5
H_DSTBN#3 5

H_DSTBP#0 5
H_DSTBP#1 5
H_DSTBP#2 5
H_DSTBP#3 5

H_REQ#0 4
H_REQ#1 4
H_REQ#2 4
H_REQ#3 4
H_REQ#4 4

H_RS#0 4
H_RS#1 4
H_RS#2 4

V_DDR _MCH_REF

1

C59

2

0.1U_0402_16V4Z

3

+1.8V

2

2

C54

1

2.2U_0805_16V4Z

SMRCOMP_VOH

SMRCOMP_VOL

2.2U_0805_16V4Z

1

C56

2

PM_EXTTS#0

PM_EXTTS#1

CLKREQ#_B DMI_TXN0

+1.8V

12

R44

@

1K_0402_1%

12

R47

@

1K_0402_1%

MCH_CLKSEL015
MCH_CLKSEL115
MCH_CLKSEL215

PM_BMBUSY#20

PM_PWROK20,32

H_THERMTRIP#4,19

10K_0402_5%

10K_0402_5%

10K_0402_5%

H_DPRSTP#5,19,39
PM_EXTTS#013
PM_EXTTS#114

PLT_RST#18,22,2 3,24

DPRSLPVR20,39

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

12

R32

C55

1

1K_0402_1%

0.01U_0402_16V7K

12

R33

3.01K_0402_1%

NA le ad free

12

R34

1

1K_0402_1%

2

C57

0.01U_0402_16V7K

DDR_A_MA1413
DDR_B_MA1414

R37

R38

R39

<>

+3VS

12

12

12

MCH_CLKSEL0
MCH_CLKSEL1
MCH_CLKSEL2

CFG5

T4

CFG6

T5

CFG7

T6

CFG8

T7

CFG9

T8

CFG10

T9

CFG11

T10

CFG12

T11

CFG13

T12

CFG16

T13

CFG18

T14

CFG19

T15

CFG20

T16

PM_BMBUSY#
H_DPRSTP#
PM_EXTTS#0
PM_EXTTS#1
PM_PWROK
PLT_RST#
H_THERMTRIP#
DPRSLPVR

2006/02/13 2006/03/10

U3B

P36

RSVD1

P37

RSVD2

R35

RSVD3

N35

RSVD4

AR12

RSVD5

AR13

RSVD6

AM12

RSVD7

AN13

RSVD8

J12

RSVD9

AR37

RSVD10

AM36

RSVD11

AL36

RSVD12

AM37

RSVD13

D20

RSVD14

H10

RSVD20

B51

RSVD21

BJ20

RSVD22

BK22

RSVD23

BF19

RSVD24

BH20

RSVD25

BK18

RSVD26

BJ18

RSVD27

BF23

RSVD28

BG23

RSVD29

BC23

RSVD30

BD24

RSVD31

BJ29

RSVD32

BE24

RSVD33

BH39

RSVD34

AW20

RSVD35

BK20

RSVD36

C48

RSVD37

D47

RSVD38

B44

RSVD39

C44

RSVD40

A35

RSVD41

B37

RSVD42

B36

RSVD43

B34

RSVD44

C34

RSVD45

P27

CFG_0

N27

CFG_1

N24

CFG_2

C21

CFG_3

C23

CFG_4

F23

CFG_5

N23

CFG_6

G23

CFG_7

J20

CFG_8

C20

CFG_9

R24

CFG_10

L23

CFG_11

J23

CFG_12

E23

CFG_13

E20

CFG_14

K23

CFG_15

M20

CFG_16

M24

CFG_17

L32

CFG_18

N33

CFG_19

L35

CFG_20

G41

PM_BM_BUSY#

L39

PM_DPRSTP#

L36

PM_EXT_TS#_0

J36

PM_EXT_TS#_1

AW49

PWROK

AV20

RSTIN#

N20

THERMTRIP#

G36

DPRSLPVR

BJ51

NC_1

BK51

NC_2

BK50

NC_3

BL50

NC_4

BL49

NC_5

BL3

NC_6

BL2

NC_7

BK1

NC_8

BJ1

NC_9

E1

NC_10

A5

NC_11

C51

NC_12

B50

NC_13

A50

NC_14

A49

NC_15

BK2

NC_16

CRES TLINE_1p0

Compal Secret Data

Deciphered Date

2

DDR M UXIN GCLK

CFGRS VD

DMI

PM

GRA PHI CS V ID

ME

NC

MI SC

2

SM_CK_0
SM_CK_1
SM_CK_3
SM_CK_4

SM_CK#_0
SM_CK#_1
SM_CK#_3
SM_CK#_4

SM_CKE_0
SM_CKE_1
SM_CKE_3
SM_CKE_4

SM_CS#_0
SM_CS#_1
SM_CS#_2
SM_CS#_3

SM_ODT_0
SM_ODT_1
SM_ODT_2
SM_ODT_3

SM_RCOMP

SM_RCOMP#

SM_RCOMP_VOH

SM_RCOMP_VOL

SM_VREF_0
SM_VREF_1

DPLL_REF_CLK

DPLL_REF_CLK#

DPLL_REF_SSCLK

DPLL_REF_SSCLK#

PEG_CLK

PEG_CLK#

DMI_RXN_0
DMI_RXN_1
DMI_RXN_2
DMI_RXN_3

DMI_RXP_0
DMI_RXP_1
DMI_RXP_2
DMI_RXP_3

DMI_TXN_0
DMI_TXN_1
DMI_TXN_2
DMI_TXN_3

DMI_TXP_0
DMI_TXP_1
DMI_TXP_2
DMI_TXP_3

GFX_VID_0
GFX_VID_1
GFX_VID_2
GFX_VID_3

GFX_VR_EN

CL_DATA

CL_PWROK

CL_RST#

CL_VREF

SDVO_CTRL_CLK

SDVO_CTRL_DATA

CLK_REQ#

ICH_SYNC#

CL_CLK

TEST_1
TEST_2

20K_0402_5%

1

For Crestli ne: 20ohm

M_CLK_DD R0

AV29

M_CLK_DD R1

BB23

M_CLK_DD R2

BA25

M_CLK_DD R3

AV23

M_CLK_DDR#0

AW30

M_CLK_DDR#1

BA23

M_CLK_DDR#2

AW25

M_CLK_DDR#3

AW23

DDR_CKE 0_DIMMA

BE29

DDR_CKE 1_DIMMA

AY32

DDR_CKE 2_DIMMB

BD39

DDR_CKE 3_DIMMB

BG37

DDR_C S0_DIMMA#

BG20

DDR_C S1_DIMMA#

BK16

DDR_C S2_DIMMB#

BG16

DDR_C S3_DIMMB#

BE13

M_ODT0

BH18

M_ODT1

BJ15

M_ODT2

BJ14

M_ODT3

BE16

SMRCOMP

BL15

SMRCOMP#

BK14

SMRCOMP_VOH

BK31

SMRCOMP_VOL

BL31

AR49

V_DDR _MCH_REF

AW4

CLK_M CH_DREFCLK

B42

CLK_M CH_DREFCLK#

C42

MCH_ SSCDREFCLK

H48

MCH_ SSCDREFCLK#

H47

CLK_MCH_3GPLL

K44

CLK_MCH_3GPLL#

K45

AN47

DMI_TXN1

AJ38

DMI_TXN2

AN42

DMI_TXN3

AN46

DMI_TXP0

AM47

DMI_TXP1

AJ39

DMI_TXP2

AN41

DMI_TXP3

AN45

DMI_RXN0

AJ46

DMI_RXN1

AJ41

DMI_RXN2

AM40

DMI_RXN3

AM44

DMI_RXP0

AJ47

DMI_RXP1

AJ42

DMI_RXP2

AM39

DMI_RXP3

AM43

E35
A39
C38
B39
E36

CL_CLK0

AM49

CL_DATA0

AK50

M_PWROK

AT43

CL_RST#

AN49

CL_VRE F CL_VRE F

AM50

H35
K36

CLKREQ#_B

G39

MCH _ICH_SYNC #

G40

A37
R32

12

12

R48

R49

0_0402_5%

Title

CRESTLINE(1/6)-AGTL+/DMI/DDR2

Size Doc ument Number Re v

Cus tom

LA-3821P

Date: Sheet of

For Calero: 8 0.6ohm

M_CLK_DD R0 13
M_CLK_DD R1 13
M_CLK_DD R2 14
M_CLK_DD R3 14

M_CLK_DD R#0 13
M_CLK_DD R#1 13
M_CLK_DD R#2 14
M_CLK_DD R#3 14

DDR_CKE 0_DIMMA 13
DDR_CKE 1_DIMMA 13
DDR_CKE 2_DIMMB 14
DDR_CKE 3_DIMMB 14

DDR_CS0_D IMMA# 13
DDR_CS1_D IMMA# 13
DDR_CS2_D IMMB# 14
DDR_CS3_D IMMB# 14

M_ODT0 13
M_ODT1 13
M_ODT2 14
M_ODT3 14

CLK_M CH_DREFCLK 15
CLK_M CH_DREFCLK# 15
MCH_ SSCDREFCLK 15
MCH_ SSCDREFCLK# 15

CLK_MCH_3GPLL 15
CLK_MCH_3GPLL# 15

DMI_TXN0 20
DMI_TXN1 20
DMI_TXN2 20
DMI_TXN3 20

DMI_TXP0 20
DMI_TXP1 20
DMI_TXP2 20
DMI_TXP3 20

DMI_RXN0 20
DMI_RXN1 20
DMI_RXN2 20
DMI_RXN3 20

DMI_RXP0 20
DMI_RXP1 20
DMI_RXP2 20
DMI_RXP3 20

T17
T18
T19
T20
T21

CL_CLK0 20
CL_DATA0 20
M_PWROK 20,32
CL_RST# 20

0.1U_0402_16V4Z

CLKREQ#_B 15
MCH _ICH_SYNC # 20

20_0402_1%

R35

R36 20_0402_1%

+1.25VM_AXD

1

C58

2

Compal Electronics, Inc.

1

12
12

12

12

7 43Tues day, July 31, 2007

+1.8V

R42

1K_0402_1%

R43
392_0402_1%

0.3

5

D D

DDR_ A_D[0..63 ]13

C C

B B

DDR_A _D0
DDR_A _D1
DDR_A _D2
DDR_A _D3
DDR_A _D4
DDR_A _D5
DDR_A _D6
DDR_A _D7
DDR_A _D8

DDR_A _D9
DDR_A _D10
DDR_A _D11
DDR_A _D12
DDR_A _D13
DDR_A _D14
DDR_A _D15
DDR_A _D16
DDR_A _D17
DDR_A _D18
DDR_A _D19
DDR_A _D20
DDR_A _D21
DDR_A _D22
DDR_A _D23
DDR_A _D24
DDR_A _D25
DDR_A _D26
DDR_A _D27
DDR_A _D28
DDR_A _D29
DDR_A _D30
DDR_A _D31
DDR_A _D32
DDR_A _D33
DDR_A _D34
DDR_A _D35
DDR_A _D36
DDR_A _D37
DDR_A _D38
DDR_A _D39
DDR_A _D40
DDR_A _D41
DDR_A _D42
DDR_A _D43
DDR_A _D44
DDR_A _D45
DDR_A _D46
DDR_A _D47
DDR_A _D48
DDR_A _D49
DDR_A _D50
DDR_A _D51
DDR_A _D52
DDR_A _D53
DDR_A _D54
DDR_A _D55
DDR_A _D56
DDR_A _D57
DDR_A _D58
DDR_A _D59
DDR_A _D60
DDR_A _D61
DDR_A _D62
DDR_A _D63

AR43

AW44

BA45

AY46
AR41
AR45

AT42

AW47

BB45

BF48
BG47

BJ45
BB47
BG50
BH49
BE45

AW43

BE44
BG42
BE40

BF44
BH45
BG40

BF40
AR40

AW40

AT39

AW36
AW41

AY41
AV38

AT38
AV13

AT13

AW11

AV11
AU15

AT11
BA13
BA11
BE10
BD10

BD8
AY9

BG10

AW9

BD7
BB9
BB5
AY7
AT5
AT7
AY6
BB7
AR5
AR8
AR9
AN3
AM8

AN10

AT9
AN9
AM9

AN11

U3D

SA_DQ_0
SA_DQ_1
SA_DQ_2
SA_DQ_3
SA_DQ_4
SA_DQ_5
SA_DQ_6
SA_DQ_7
SA_DQ_8
SA_DQ_9
SA_DQ_10
SA_DQ_11
SA_DQ_12
SA_DQ_13
SA_DQ_14
SA_DQ_15
SA_DQ_16
SA_DQ_17
SA_DQ_18
SA_DQ_19
SA_DQ_20
SA_DQ_21
SA_DQ_22
SA_DQ_23
SA_DQ_24
SA_DQ_25
SA_DQ_26
SA_DQ_27
SA_DQ_28
SA_DQ_29
SA_DQ_30
SA_DQ_31
SA_DQ_32
SA_DQ_33
SA_DQ_34
SA_DQ_35
SA_DQ_36
SA_DQ_37
SA_DQ_38
SA_DQ_39
SA_DQ_40
SA_DQ_41
SA_DQ_42
SA_DQ_43
SA_DQ_44
SA_DQ_45
SA_DQ_46
SA_DQ_47
SA_DQ_48
SA_DQ_49
SA_DQ_50
SA_DQ_51
SA_DQ_52
SA_DQ_53
SA_DQ_54
SA_DQ_55
SA_DQ_56
SA_DQ_57
SA_DQ_58
SA_DQ_59
SA_DQ_60
SA_DQ_61
SA_DQ_62
SA_DQ_63

CRES TLINE_1p0

DDR SYSTEM MEMORY A

SA_BS_0
SA_BS_1
SA_BS_2

SA_CAS#

SA_DM_0
SA_DM_1
SA_DM_2
SA_DM_3
SA_DM_4
SA_DM_5
SA_DM_6
SA_DM_7

SA_DQS_0
SA_DQS_1
SA_DQS_2
SA_DQS_3
SA_DQS_4
SA_DQS_5
SA_DQS_6

SA_DQS_7
SA_DQS#_0
SA_DQS#_1
SA_DQS#_2
SA_DQS#_3
SA_DQS#_4
SA_DQS#_5
SA_DQS#_6
SA_DQS#_7

SA_MA_0
SA_MA_1
SA_MA_2
SA_MA_3
SA_MA_4
SA_MA_5
SA_MA_6
SA_MA_7
SA_MA_8

SA_MA_9
SA_MA_10
SA_MA_11
SA_MA_12
SA_MA_13

SA_RAS#

SA_RCVEN#

SA_WE#

4

DDR_A_BS 0

BB19
BK19
BF29

BL17

AT45
BD44
BD42
AW38
AW13
BG8
AY5
AN6

AT46
BE48
BB43
BC37
BB16
BH6
BB2
AP3
AT47
BD47
BC41
BA37
BA16
BH7
BC1
AP2

BJ19
BD20
BK27
BH28
BL24
BK28
BJ27
BJ25
BL28
BA28
BC19
BE28
BG30
BJ16

BE18
AY20

BA19

DDR_A_BS 1
DDR_A_BS 2

DDR_A _CAS#

DDR_A_DM 0
DDR_A_DM 1
DDR_A_DM 2
DDR_A_DM 3
DDR_A_DM 4
DDR_A_DM 5
DDR_A_DM 6
DDR_A_DM 7

DDR_A _DQS0
DDR_A _DQS1
DDR_A _DQS2

DDR_A _DQS4
DDR_A _DQS5
DDR_A _DQS6
DDR_A _DQS7
DDR_A _DQS#0
DDR_A _DQS#1
DDR_A _DQS#2
DDR_A _DQS#3
DDR_A _DQS#4
DDR_A _DQS#5
DDR_A _DQS#6
DDR_A _DQS#7

DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13

DDR_A _RAS#
SA_RCVEN #

DDR_A_W E#

DDR_A_BS 0 13
DDR_A_BS 1 13
DDR_A_BS 2 13

DDR_A _CAS# 13 DDR_B _CAS# 14
DDR_A _DM[0..7] 13

DDR_ A_DQS[0.. 7] 13

DDR_A _DQS#[0.. 7] 13

DDR_A _MA[0..13] 13

DDR_A _RAS# 13

T23

DDR_A_W E# 13

3

DDR_ B_D[0..63 ]14

DDR_B _D0
DDR_B _D1
DDR_B _D2
DDR_B _D3
DDR_B _D4
DDR_B _D5
DDR_B _D6
DDR_B _D7
DDR_B _D8

DDR_B _D9
DDR_B _D10
DDR_B _D11
DDR_B _D12
DDR_B _D13
DDR_B _D14
DDR_B _D15
DDR_B _D16
DDR_B _D17
DDR_B _D18DDR_A _DQS3
DDR_B _D19
DDR_B _D20
DDR_B _D21
DDR_B _D22
DDR_B _D23
DDR_B _D24
DDR_B _D25
DDR_B _D26
DDR_B _D27
DDR_B _D28
DDR_B _D29
DDR_B _D30
DDR_B _D31
DDR_B _D32
DDR_B _D33
DDR_B _D34
DDR_B _D35
DDR_B _D36
DDR_B _D37
DDR_B _D38
DDR_B _D39
DDR_B _D40
DDR_B _D41

DDR_B _D43
DDR_B _D44
DDR_B _D45
DDR_B _D46
DDR_B _D47
DDR_B _D48
DDR_B _D49
DDR_B _D50
DDR_B _D51
DDR_B _D52
DDR_B _D53
DDR_B _D54
DDR_B _D55
DDR_B _D56
DDR_B _D57
DDR_B _D58
DDR_B _D59
DDR_B _D60
DDR_B _D61
DDR_B _D62
DDR_B _D63

AP49

AR51
AW50
AW51

AN51

AN50

AV50

AV49

BA50

BB50

BA49

BE50

BA51

AY49

BF50

BF49

BJ50
BJ44

BJ43
BL43
BK47
BK49
BK43
BK42

BJ41
BL41

BJ37

BJ36
BK41

BJ40
BL35
BK37
BK13
BE11
BK11
BC11
BC13
BE12
BC12
BG12

BJ10

BK10

BL9
BK5
BL5
BK9

BJ8
BJ6
BF4
BH5
BG1
BC2
BK3
BE4
BD3
BJ2
BA3
BB3
AR1
AT3
AY2
AY3
AU2
AT2

2

U3E

SB_DQ_0
SB_DQ_1
SB_DQ_2
SB_DQ_3
SB_DQ_4
SB_DQ_5
SB_DQ_6
SB_DQ_7
SB_DQ_8
SB_DQ_9
SB_DQ_10
SB_DQ_11
SB_DQ_12
SB_DQ_13
SB_DQ_14
SB_DQ_15
SB_DQ_16
SB_DQ_17
SB_DQ_18
SB_DQ_19
SB_DQ_20
SB_DQ_21
SB_DQ_22
SB_DQ_23
SB_DQ_24
SB_DQ_25
SB_DQ_26
SB_DQ_27
SB_DQ_28
SB_DQ_29
SB_DQ_30
SB_DQ_31
SB_DQ_32
SB_DQ_33
SB_DQ_34
SB_DQ_35
SB_DQ_36
SB_DQ_37
SB_DQ_38
SB_DQ_39
SB_DQ_40
SB_DQ_41
SB_DQ_42
SB_DQ_43
SB_DQ_44
SB_DQ_45
SB_DQ_46
SB_DQ_47
SB_DQ_48
SB_DQ_49
SB_DQ_50
SB_DQ_51
SB_DQ_52
SB_DQ_53
SB_DQ_54
SB_DQ_55
SB_DQ_56
SB_DQ_57
SB_DQ_58
SB_DQ_59
SB_DQ_60
SB_DQ_61
SB_DQ_62
SB_DQ_63

CRES TLINE_1p0

1

DDR_B_BS0

AY17

SB_BS_0
SB_BS_1
SB_BS_2

SB_CAS#

SB_DM_0
SB_DM_1
SB_DM_2
SB_DM_3
SB_DM_4
SB_DM_5
SB_DM_6
SB_DM_7

SB_DQS_0
SB_DQS_1
SB_DQS_2
SB_DQS_3
SB_DQS_4
SB_DQS_5
SB_DQS_6

SB_DQS_7
SB_DQS#_0
SB_DQS#_1
SB_DQS#_2
SB_DQS#_3
SB_DQS#_4
SB_DQS#_5
SB_DQS#_6
SB_DQS#_7

SB_MA_0
SB_MA_1
SB_MA_2
SB_MA_3
SB_MA_4
SB_MA_5
SB_MA_6
SB_MA_7
SB_MA_8

SB_MA_9
SB_MA_10
SB_MA_11
SB_MA_12
SB_MA_13

SB_RAS#

SB_RCVEN#

SB_WE#

DDR SYSTEM MEMORY B

BG18
BG36

BE17

AR50
BD49
BK45
BL39
BH12
BJ7
BF3
AW2

AT50
BD50
BK46
BK39
BJ12
BL7
BE2
AV2
AU50
BC50
BL45
BK38
BK12
BK7
BF2
AV3

BC18
BG28
BG25
AW17
BF25
BE25
BA29
BC28
AY28
BD37
BG17
BE37
BA39
BG13

AV16
AY18

BC17

DDR_B_BS 1
DDR_B_BS 2

DDR_B _CAS#

DDR_B_DM 0
DDR_B_DM 1
DDR_B_DM 2
DDR_B_DM 3
DDR_B_DM 4
DDR_B_DM 5
DDR_B_DM 6
DDR_B_DM 7

DDR_B _DQS0
DDR_B _DQS1
DDR_B _DQS2
DDR_B _DQS3
DDR_B _DQS4
DDR_B _DQS5
DDR_B _DQS6

DDR_B _DQS7
DDR_B _DQS#0
DDR_B _DQS#1
DDR_B _DQS#2
DDR_B _DQS#3
DDR_B _DQS#4
DDR_B _DQS#5
DDR_B _DQS#6
DDR_B _DQS#7

DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8

DDR_B_MA9
DDR_B_MA10DDR_B _D42
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13

DDR_B _RAS#

SB_RCVEN #

DDR_B_W E#

DDR_B _RAS# 14

T22

DDR_B_W E# 14

DDR_B_BS 0 14
DDR_B_BS 1 14
DDR_B_BS 2 14

DDR_B _DM[0..7] 14

DDR_ B_DQS[0.. 7] 14

DDR_B _DQS#[0.. 7] 14

DDR_B _MA[0..13] 14

A A

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/02/13 2006/03/10

Compal Secret Data

Deciphered Date

Title

Size Doc ument Number Re v

Cus tom

2

Date: Sheet of

Compal Electronics, Inc.

CRESTLINE((2/6)-DDR2 A/B CH

LA-3821P

8 43Tues day, July 31, 2007

1

0.3

5

4

3

2

1

Strap Pin Table

010 = FSB 800MHz

CFG[2:0] FSB Freq select

D D

ENABLT17,32

+3VS

LCD_C LK17

For Crestli ne:2.4kohm
For Calero: 1 .5Kohm

C C

LCD_DATA17

ENAVD D17

5/03

+3VS

B B

0312 _Add test point.

T49

ENABLT

R54 10K_0402_5%

1 2

R55 10K_0402_5%

1 2

LCD_C LK
LCD_DATA

ENAVDD

12

R56 2.4K_0402_1%

LVDSAC-17
LVDSAC+17

LVDSA0-17
LVDSA1-17

LVDSA2-17

LVDSA0+17
LVDSA1+17

LVDSA2+17

R247 150_0402_5%
R355 150_0402_5%
R358 150_0402_5%

2.2K_0402_5%

R57

1 2

CRT_B16

CRT_G16

CRT_R16

3VDDC CL16
3VDDC DA16

CRT _HSYNC16

CRT_V SYNC16

BKLT_CTRL

LVDSAC­LVDSAC+

LVDSA0­LVDSA1­LVDSA2-

LVDSA0+
LVDSA1+
LVDSA2+

12
12
12

CRT_B

CRT_G

CRT_R

3VDDC CL
3VDDC DA
CR T_HSYNC

CRT_V SYNC

1.3K_0402_1%

12

R58

U3C

J40

L_BKLT_CTRL

H39

L_BKLT_EN

E39

L_CTRL_CLK

E40

L_CTRL_DATA

C37

L_DDC_CLK

D35

L_DDC_DATA

K40

L_VDD_EN

L41

LVDS_IBG

L43

LVDS_VBG

N41

LVDS_VREFH

N40

LVDS_VREFL

D46

LVDSA_CLK#

C45

LVDSA_CLK

D44

LVDSB_CLK#

E42

LVDSB_CLK

G51

LVDSA_DATA#_0

E51

LVDSA_DATA#_1

F49

LVDSA_DATA#_2

G50

LVDSA_DATA_0

E50

LVDSA_DATA_1

F48

LVDSA_DATA_2

G44

LVDSB_DATA#_0

B47

LVDSB_DATA#_1

B45

LVDSB_DATA#_2

E44

LVDSB_DATA_0

A47

LVDSB_DATA_1

A45

LVDSB_DATA_2

E27

TVA_DAC

G27

TVB_DAC

K27

TVC_DAC

F27

TVA_RTN

J27

TVB_RTN

L27

TVC_RTN

M35

TV_DCONSEL_0

P33

TV_DCONSEL_1

H32

CRT_BLUE

G32

CRT_BLUE#

K29

CRT_GREEN

J29

CRT_GREEN#

F29

CRT_RED

E29

CRT_RED#

K33

CRT_DDC_CLK

G35

CRT_DDC_DATA

F33

CRT_HSYNC

C32

CRT_TVO_IREF

E33

CRT_VSYNC

CRES TLINE_1p0

R53

PEGCOMP

PEG_RX#_0
PEG_RX#_1
PEG_RX#_2
PEG_RX#_3
PEG_RX#_4
PEG_RX#_5
PEG_RX#_6
PEG_RX#_7
PEG_RX#_8
PEG_RX#_9

PEG_RX_0
PEG_RX_1
PEG_RX_2
PEG_RX_3
PEG_RX_4
PEG_RX_5
PEG_RX_6
PEG_RX_7
PEG_RX_8

PEG_RX_9
PEG_RX_10
PEG_RX_11
PEG_RX_12
PEG_RX_13
PEG_RX_14
PEG_RX_15

PEG_TX#_0
PEG_TX#_1
PEG_TX#_2
PEG_TX#_3
PEG_TX#_4
PEG_TX#_5
PEG_TX#_6
PEG_TX#_7
PEG_TX#_8
PEG_TX#_9

PEG_TX_0

PEG_TX_1

PEG_TX_2

PEG_TX_3

PEG_TX_4

PEG_TX_5

PEG_TX_6

PEG_TX_7

PEG_TX_8

PEG_TX_9
PEG_TX_10
PEG_TX_11
PEG_TX_12
PEG_TX_13
PEG_TX_14
PEG_TX_15

N43
M43

J51
L51
N47
T45
T50
U40
Y44
Y40
AB51
W49
AD44
AD40
AG46
AH49
AG45
AG41

J50
L50
M47
U44
T49
T41
W45
W41
AB50
Y48
AC45
AC41
AH47
AG49
AH45
AG42

N45
U39
U47
N51
R50
T42
Y43
W46
W38
AD39
AC46
AC49
AC42
AH39
AE49
AH44

M45
T38
T46
N50
R51
U43
W42
Y47
Y39
AC38
AD47
AC50
AD43
AG39
AE50
AH43

PEG_COMPI

PEG_COMPO

LVDS

PEG_RX#_10
PEG_RX#_11
PEG_RX#_12
PEG_RX#_13
PEG_RX#_14
PEG_RX#_15

TV VGA

PEG_TX#_10

PCI-EXPRESS GRAPHICS

PEG_TX#_11
PEG_TX#_12
PEG_TX#_13
PEG_TX#_14
PEG_TX#_15

24.9_0402_1%

1 2

PE GC OMP tra ce wi dth
and sp aci ng is 20 /25 m ils.

+VCCP

CFG5 (DMI select)

CFG6

CFG7 (CPU Strap)

CFG8 (Low power PCIE)

CFG9

(PCIE Graphics Lane Reversal)

CFG[11:10]

CFG[13:12] (XOR/ALLZ)

CFG16 (FSB Dynamic ODT)

SDVO_CTRLDATA

CFG19 (DMI Lane Reversal)

CFG20 (PCIE/SDVO concurrent)

CFG[17 :3] hav e internal pull up

CFG[19 :18] ha ve internal pull down

011 = FSB 667MHz

Others = Reserved

0 = DMI x 2

1 = DMI x 4

*

Reserved

0 = Reserved

1 = Mobile CPU

*

0 = Normal mode

1 = Low Power mode

*

0 = Reverse Lane

1 = Normal Operation

*

Reserved

00 = Reserved
01 = XOR Mode Enabled
10 = All Z Mode Enabled

11 = Normal Operation

(Default)

*

ReservedCFG[15:14]

0 = Disabled

1 = Enabled

*

ReservedCFG[18:17]

0 = No SDVO Device Present

1 = SDVO Device Present

0 = Normal Operation

(Lane number in Order)

*

*

1 = Reverse Lane

0 = Only PCIE or SDVO is operational.

1 = PCIE/SDVO are operating simu.

*

For Crestli ne:1.3kohm
For Calero: 2 55ohm

A A

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/02/13 2006/03/10

Compal Secret Data

Deciphered Date

Title

Size Doc ument Number Re v

Cus tom

2

Date: Sheet of

Compal Electronics, Inc.

CRESTLINE((3/6)-VGA/LVDS/TV

LA-3821P

9 43Tues day, July 31, 2007

1

0.3

+3VS_DAC_BG

0.022U_0402_16V7K

1

C63

2

BLM18PG181SN1D_0603

0.1U_0402 _16V4Z
C508

1U_0603_10V4Z

1

1

2

2

C64

5

R60

+3VS

+3VS

12

7/2 5

D D

+3VS_DAC_CRT

C C

0.022U_0402_16V7K

C71

+1.25VS

BLM18PG181SN1D_0603

1

1

C72

2

2

220U_6.3V_M

0.1U_0402_16V4Z

0_0603_5%

+3VS

C88

R72

+1.5VS_TV DAC

+3VS

12

R63

R67

0_0603_5%

0.1U_0402_16V 4Z

R69

1 2

0_0805_5%

1

+

10U_0805_10V4Z

2

+1.25VM_A_SM_CK

12

1U_0603_10V4Z

C97

1

2

+3VS_PEG_BG

C83

1

2

C98

1

2

+1.8V_TXLVDS

12

C89

4.7U_0805_10 V4Z

100mA

10U_0805_10V4Z

R450

0_0603_5%

Res erv re sister 4/20

+3VS_TVDACC

B B

0.022U_0402_16V7K

C109

+3VS_TVDACA

0.022U_0402_16V7K

C113

A A

+3VS_TVDACB

0.022U_0402_16V7K

C119

1

C110

2

1

C114

2

1

C120

2

BLM18PG181SN1D_0603

0.1U_0402_16V4Z

1

2

BLM18PG181SN1D_0603

0.1U_0402_16V4Z

1

2

BLM18PG181SN1D_0603

0.1U_0402 _16V4Z

1

2

5

+3VS

12

R75

+3VS

12

R79

+3VS

12

R81

1

2

C99

R59

0_0603_5%

10mA

5mA

+1.25VM_A_SM

C90

1U_0603_10V4Z

1

2

12

+1.25VS_PEGPLL

VCC SYNC

10mA

12

1

C62

2

+3VS_DA C_CRT

+3VS_DAC_BG

+1.25VS_DPLLA

+1.25VS_DPLLB

+1.25VM_HPLL

+1.25VM_MPLL

1000P_0402_50V7K

1

C80

2

+1.25VS_PEGPLL

950mA

1

2

1U_0603_10V4Z

0.1U_0402 _16V4Z

C100

1

+3VS_TVDACA

+3VS_TVDACB

2

+3VS_TVDACC

+1.5VS_TV DAC_R

+1.5VS_Q DAC

+1.25VM_HPLL

+1.8V_LVDS

+1.5VS_QDA C

0.022U_0402_16V7K

C111

+1.8V_LVDS

10U_0805_10V4Z

C117

0.1U_0402 _16V4Z

80mA

80mA

50mA

150mA

1

C91

2

40mA

40mA

40mA

250mA

100mA

150mA

1

2

1

2

75mA

C112

1U_0603_10V4Z

80mA

5mA

20 mils

5mA

1

2

C118

1

2

0.1U_0402 _16V4Z

50mA
25mA

J32

A33
B33

A30

B32

B49

H49

AL2

AM2

A41

B41

K50

K49

U51

AW18

AV19
AU19
AU18
AU17

AT22
AT21
AT19
AT18
AT17
AR17
AR16

BC29
BB29

C25
B25
C27
B27
B28
A28

M32

L29

N28

AN2

U48

J41
H42

R78

100_0603_1%

R82

0_0603_5%

4

U3 H

VCCSYNC

VCCA_CRT_DAC_1
VCCA_CRT_DAC_2

VCCA_DAC_BG

VSSA_DAC_BG

VCCA_DPLLA

VCCA_DPLLB

VCCA_HPLL

VCCA_MPLL

VCCA_LVDS

VSSA_LVDS

VCCA_PEG_BG

VSSA_PEG_BG

VCCA_PEG_PLL

VCCA_SM_1
VCCA_SM_2
VCCA_SM_3
VCCA_SM_4
VCCA_SM_5

VCCA_SM_7
VCCA_SM_8
VCCA_SM_9
VCCA_SM_10
VCCA_SM_11
VCCA_SM_NCTF_1
VCCA_SM_NCTF_2

VCCA_SM_CK_1
VCCA_SM_CK_2

VCCA_TVA_DAC_1
VCCA_TVA_DAC_2
VCCA_TVB_DAC_1
VCCA_TVB_DAC_2
VCCA_TVC_DAC_1
VCCA_TVC_DAC_2

VCCD_CRT
VCCD_TVDAC

VCCD_QDAC

VCCD_HPLL

VCCD_PEG_PLL

VCCD_LVDS_1
VCCD_LVDS_2

CRESTLINE _1p0

+1.5VS

12

12

4

CRTPLLA PEGA SMTV

POWER

A CK A LVDS

D TV/CRTLVDS

+1.8V

VTT_1
VTT_2
VTT_3
VTT_4
VTT_5
VTT_6
VTT_7
VTT_8

VTT_9
VTT_10
VTT_11
VTT_12
VTT_13

VTT

VTT_14
VTT_15
VTT_16
VTT_17
VTT_18
VTT_19
VTT_20
VTT_21
VTT_22

VCC_AXD_1
VCC_AXD_2
VCC_AXD_3
VCC_AXD_4
VCC_AXD_5

AXD

VCC_AXD_6

VCC_AXD_NCTF

VCC_AXF_1
VCC_AXF_2
VCC_AXF_3

AXF

VCC_DMI

VCC_SM_CK_1
VCC_SM_CK_2
VCC_SM_CK_3
VCC_SM_CK_4

SM CK

VCC_TX_LVDS

VCC_HV_1
VCC_HV_2

HV

VCC_PEG_1
VCC_PEG_2
VCC_PEG_3
VCC_PEG_4

PEG

VCC_PEG_5

VCC_RXR_DMI_1
VCC_RXR_DMI_2

DMI

VTTLF1
VTTLF2
VTTLF3

VTTLF

1000P_0402_50V7K

3

+VCCP

850mA

350mA

100mA

120mA

100mA

1200mA

330U_D2E_2. 5VM_R7

C69

C73

+1.25VM_AXD

200mA

1U_0603_10V4Z

1

2

+V1.25VS_AXF

+1.25VS_DMI

+1.8V_SM_CK

+1.8V_TXLVDS

1450mA

+VCC_PEG

1

2

1

2

+

C81

100mA

4.7U_0805_10V4Z

1

C70

2

2.2U_0805 _16V4Z

4.7U_0805 _10V4Z

0.47U_0603_10V7K

C82

1

C74

2

10U_0805_10V4Z

1

2

+3VS_HV

C101

C75

R66

1 2

0_0805_5%

0.1U_0402 _16V4Z

1

2

1

2

+1.25VS

250mA

20mils

0.47U_0603_10V7K

0.47U_0603_10V7K

C107

C106

1

2

1

C116
10U_0805_10V4Z

2

020 8_C han ge C 117 va lue fr om 2 20u F to 10uF.

Issued Date

1

2

0_0603_5%

3

0.47U_0603_10V7K

C108

1

2

R80

12

+1.8V

2006/02/13 2006/03/10

Compal Secret Data

U13
U12
U11
U9
U8
U7
U5
U3
U2
U1
T13
T11
T10
T9
T7
T6
T5
T3
T2
R3
R2
R1

AT23
AU28
AU24
AT29
AT25
AT30

AR29

B23
B21
A21

AJ50

BK24
BK23
BJ24
BJ23

A43

C40
B40

AD51
W50
W51
V49
V50

AH50
AH51

A7
F2
AH1

+1.8V_TXLVDS

1

C115

2

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

+1.25VS_DPLLB

0.1U_0402_16V4Z

+1.25VS_DMI

+1.25VS_PEGPLL

+1.25VS_DP LLA

150U_B_6.3VM_R40M

1

+

C92

@

2

Deciphered Date

10U_0805_10V4Z

C65

1

2

1 2

0.1U_0402 _16V4Z

C79

1

2

0.1U_0402 _16V4Z

C84

1

2

C93

1

2

0.1U_0402_16V 4Z

+VCC_PEG

220U_6.3V_M

1

C102

+

2

2

R61

1 2

10U_FLC-453232-1 00K_0.25A_10%

C66

1

2

+1.25VS

R64

0_0603_5%

BLM18PG121SN1D_0 603

10U_0805_10V4Z

C85

1

2

10U_0805_10V4Z

C94

1

2

C103

1

2

2

+1.25VS

+1.25VS

L1

12

R70

1 2

10U_FLC-453232-1 00K_0.25A_10%

10U_0805_10V4Z

R73

0_0805_5%

+VCCP

+3VS

+1.25VS

12

2 1

1

+V1.25VS_AXF

10U_0805_10V4Z

1U_0603_10V4Z

C67

1

2

+1.8V_SM_CK

10U_0805_10V4Z

10U_0805_10V4Z

C76

1

2

0.1U_0402_16 V4Z

+VCCP

0.1U_0402_16 V4Z

+VCCP_ D

D3

CH751H-40PT_SOD 323-2

Title

Size Documen t Number Re v

Cust om

LA -3 82 1P

Date : Sheet of

C77

1

2

+1.5VS_TVDAC

0.022U_0402_16V7K

1

C86

2

+1.25VM_HPLL

1

C95

2

+1.25VM_MPLL

1

C104

2

R76

12

10_0402_5%

Compal Electronics, Inc.

CRESTLINE(4/6)-PWR

0.1U_0402 _16V4Z

0.1U_0402_16V4Z

1

C87

2

MBK2012121YZF _0805

1

C96

10U_0805_10V4Z

2

MBK2012121YZF _0805

1

C105

10U_0805_10V4Z

2

R77

0_0402_5%

1

C68

1

2

1 2

C78

1

2

1 2

R71

R74

12

1 2

R65

0_0805_5%

R68

0_0805_5%

12

+1.25VS

12

10 43Tu esd ay, J ul y 3 1, 20 07

R62

0_0603_5%

+1.25VS

+3VS_HV

+1.25VS

+1.8V

+1.5VS

0.3

5

4

3

2

1

+VCCP

VCC=1260mA

D D

0.22U_0603_10V7K

0.22U_0402_10V4 Z

220U_D2_2.5VM

C C

B B

10U_0805_10V4Z

1

+

C124

2

0.22U_0402_10V4 Z

C140

1

2

C126

C125

1

2

0.22U_0402_10V4 Z

C141

1

2

1

1

2

2

+VCCP

10U_0805_10V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

C142

1

1

2

2

+VCCP

VCC=1260mA

0.1U_0402_16V4Z

C127

C128

1

2

VCC_AXM=970mA

10U_0805_10V4Z

C134

C133

1

1

2

2

0.1U_0402_16V4Z

C143

C144

1

2

AB33
AB36
AB37
AC33
AC35
AC36
AD35
AD36
AF33
AF36
AH33
AH35
AH36
AH37

AJ33

AJ35
AK33
AK35
AK36
AK37
AD33

AJ36

AM35

AL33

AL35
AA33
AA35
AA36
AP35
AP36
AR35
AR36

AL24

AL26

AL28

AM26
AM28
AM29
AM31
AM32
AM33

AP29
AP31
AP32
AP33

AL29

AL31

AL32
AR31
AR32
AR33

Y32
Y33
Y35
Y36
Y37
T30
T34

T35
U29
U31
U32
U33
U35
U36

V32

V33

V36

V37

U3F

CRES TLINE_1p0

VCC_NCTF_1
VCC_NCTF_2
VCC_NCTF_3
VCC_NCTF_4
VCC_NCTF_5
VCC_NCTF_6
VCC_NCTF_7
VCC_NCTF_8
VCC_NCTF_9
VCC_NCTF_10
VCC_NCTF_11
VCC_NCTF_12
VCC_NCTF_13
VCC_NCTF_14
VCC_NCTF_15
VCC_NCTF_16
VCC_NCTF_17
VCC_NCTF_18
VCC_NCTF_19
VCC_NCTF_20
VCC_NCTF_21
VCC_NCTF_22
VCC_NCTF_23
VCC_NCTF_24
VCC_NCTF_25
VCC_NCTF_26
VCC_NCTF_27
VCC_NCTF_28
VCC_NCTF_29
VCC_NCTF_30
VCC_NCTF_31
VCC_NCTF_32
VCC_NCTF_33
VCC_NCTF_34
VCC_NCTF_35
VCC_NCTF_36
VCC_NCTF_37
VCC_NCTF_38
VCC_NCTF_39
VCC_NCTF_40
VCC_NCTF_41
VCC_NCTF_42
VCC_NCTF_43
VCC_NCTF_44
VCC_NCTF_45
VCC_NCTF_46
VCC_NCTF_47
VCC_NCTF_48
VCC_NCTF_49
VCC_NCTF_50

VCC_AXM_NCTF_1
VCC_AXM_NCTF_2
VCC_AXM_NCTF_3
VCC_AXM_NCTF_4
VCC_AXM_NCTF_5
VCC_AXM_NCTF_6
VCC_AXM_NCTF_7
VCC_AXM_NCTF_8
VCC_AXM_NCTF_9
VCC_AXM_NCTF_10
VCC_AXM_NCTF_11
VCC_AXM_NCTF_12
VCC_AXM_NCTF_13
VCC_AXM_NCTF_14
VCC_AXM_NCTF_15
VCC_AXM_NCTF_16
VCC_AXM_NCTF_17
VCC_AXM_NCTF_18
VCC_AXM_NCTF_19

VCC NCTF

POWER

VCC AXM NCTF

VSS_NCTF_1
VSS_NCTF_2
VSS_NCTF_3
VSS_NCTF_4
VSS_NCTF_5
VSS_NCTF_6
VSS_NCTF_7
VSS_NCTF_8

VSS_NCTF_9
VSS_NCTF_10
VSS_NCTF_11
VSS_NCTF_12
VSS_NCTF_13
VSS_NCTF_14
VSS_NCTF_15

VSS NCTF

VSS_NCTF_16
VSS_NCTF_17
VSS_NCTF_18
VSS_NCTF_19
VSS_NCTF_20
VSS_NCTF_21

VSS_SCB1
VSS_SCB2
VSS_SCB3
VSS_SCB4
VSS_SCB5
VSS_SCB6

VSS SCBVCC AXM

VCC_AXM_1
VCC_AXM_2
VCC_AXM_3
VCC_AXM_4
VCC_AXM_5
VCC_AXM_6
VCC_AXM_7

T27
T37
U24
U28
V31
V35
AA19
AB17
AB35
AD19
AD37
AF17
AF35
AK17
AM17
AM24
AP26
AP28
AR15
AR19
AR28

A3
B2
C1
BL1
BL51
A51

AT33
AT31
AK29
AK24
AK23
AJ26
AJ23

VCC_AXM=970mA

+VCCP

C136

1U_0603_10V4Z

+1.8V

C129

330U_4V_M

1

C135

2

330U_D2E_2.5VM _R7

3720mA

10U_0805_10V4Z

1

+

C137

2

10U_0805_10V4Z

1

+

2

1

C138

2

10U_0805_10V4Z

10U_0805_10V4Z

C130

C131

1

1

2

2

VCC_AXG=7700mA

+VCCP

0.1U_0402_16V4Z

1

C139

2

1 2

0_0603_5%

0.01U_0402_16V7K

2

1

1

2

R83

C132

AT35
AT34
AH28
AC32
AC31
AK32

AJ31

AJ28
AH32
AH31
AH29
AF32

AU32
AU33
AU35
AV33

AW33
AW35

AY35
BA32
BA33
BA35
BB33
BC32
BC33
BC35
BD32
BD35
BE32
BE33
BE35
BF33
BF34
BG32
BG33
BG35
BH32
BH34
BH35

BJ32

BJ33

BJ34
BK32
BK33
BK34
BK35
BL33
AU30

W13
W14

AA20
AA23
AA26
AA28
AB21
AB24
AB29
AC20
AC21
AC23
AC24
AC26
AC28
AC29
AD20
AD23
AD24
AD28
AF21
AF26
AA31
AH20
AH21
AH23
AH24
AH26
AD31

AJ20
AN14

R30

R20
T14

Y12

U3G

VCC_1
VCC_2
VCC_3
VCC_5
VCC_4
VCC_6
VCC_7
VCC_8
VCC_9
VCC_10
VCC_11
VCC_12

VCC_13

VCC_SM_1
VCC_SM_2
VCC_SM_3
VCC_SM_4
VCC_SM_5
VCC_SM_6
VCC_SM_7
VCC_SM_8
VCC_SM_9
VCC_SM_10
VCC_SM_11
VCC_SM_12
VCC_SM_13
VCC_SM_14
VCC_SM_15
VCC_SM_16
VCC_SM_17
VCC_SM_18
VCC_SM_19
VCC_SM_20
VCC_SM_21
VCC_SM_22
VCC_SM_23
VCC_SM_24
VCC_SM_25
VCC_SM_26
VCC_SM_27
VCC_SM_28
VCC_SM_29
VCC_SM_30
VCC_SM_31
VCC_SM_32
VCC_SM_33
VCC_SM_34
VCC_SM_35
VCC_SM_36

VCC_AXG_1
VCC_AXG_2
VCC_AXG_3
VCC_AXG_4
VCC_AXG_5
VCC_AXG_6
VCC_AXG_7
VCC_AXG_8
VCC_AXG_9
VCC_AXG_10
VCC_AXG_11
VCC_AXG_12
VCC_AXG_13
VCC_AXG_14
VCC_AXG_15
VCC_AXG_16
VCC_AXG_17
VCC_AXG_18
VCC_AXG_19
VCC_AXG_20
VCC_AXG_21
VCC_AXG_22
VCC_AXG_23
VCC_AXG_24
VCC_AXG_25
VCC_AXG_26
VCC_AXG_27
VCC_AXG_28
VCC_AXG_29
VCC_AXG_30
VCC_AXG_31
VCC_AXG_32
VCC_AXG_33
VCC_AXG_34

VCC CORE

POWER

VCC SMVCC GFX

VCC_AXG_NCTF_1
VCC_AXG_NCTF_2
VCC_AXG_NCTF_3
VCC_AXG_NCTF_4
VCC_AXG_NCTF_5
VCC_AXG_NCTF_6
VCC_AXG_NCTF_7
VCC_AXG_NCTF_8

VCC_AXG_NCTF_9
VCC_AXG_NCTF_10
VCC_AXG_NCTF_11
VCC_AXG_NCTF_12
VCC_AXG_NCTF_13
VCC_AXG_NCTF_14
VCC_AXG_NCTF_15
VCC_AXG_NCTF_16
VCC_AXG_NCTF_17
VCC_AXG_NCTF_18
VCC_AXG_NCTF_19
VCC_AXG_NCTF_20
VCC_AXG_NCTF_21
VCC_AXG_NCTF_22
VCC_AXG_NCTF_23
VCC_AXG_NCTF_24
VCC_AXG_NCTF_25
VCC_AXG_NCTF_26
VCC_AXG_NCTF_27
VCC_AXG_NCTF_28
VCC_AXG_NCTF_29
VCC_AXG_NCTF_30
VCC_AXG_NCTF_31
VCC_AXG_NCTF_32
VCC_AXG_NCTF_33
VCC_AXG_NCTF_34
VCC_AXG_NCTF_35
VCC_AXG_NCTF_36
VCC_AXG_NCTF_37
VCC_AXG_NCTF_38
VCC_AXG_NCTF_39
VCC_AXG_NCTF_40
VCC_AXG_NCTF_41
VCC_AXG_NCTF_42
VCC_AXG_NCTF_43
VCC_AXG_NCTF_44
VCC_AXG_NCTF_45
VCC_AXG_NCTF_46
VCC_AXG_NCTF_47
VCC_AXG_NCTF_48
VCC_AXG_NCTF_49
VCC_AXG_NCTF_50
VCC_AXG_NCTF_51
VCC_AXG_NCTF_52
VCC_AXG_NCTF_53
VCC_AXG_NCTF_54

VCC GFX NCTF

VCC_AXG_NCTF_55
VCC_AXG_NCTF_56
VCC_AXG_NCTF_57
VCC_AXG_NCTF_58
VCC_AXG_NCTF_59
VCC_AXG_NCTF_60
VCC_AXG_NCTF_61
VCC_AXG_NCTF_62
VCC_AXG_NCTF_63
VCC_AXG_NCTF_64
VCC_AXG_NCTF_65
VCC_AXG_NCTF_66
VCC_AXG_NCTF_67
VCC_AXG_NCTF_68
VCC_AXG_NCTF_69
VCC_AXG_NCTF_70
VCC_AXG_NCTF_71
VCC_AXG_NCTF_72
VCC_AXG_NCTF_73
VCC_AXG_NCTF_74
VCC_AXG_NCTF_75
VCC_AXG_NCTF_76
VCC_AXG_NCTF_77
VCC_AXG_NCTF_78
VCC_AXG_NCTF_79
VCC_AXG_NCTF_80
VCC_AXG_NCTF_81
VCC_AXG_NCTF_82
VCC_AXG_NCTF_83

VCC_SM_LF1
VCC_SM_LF2
VCC_SM_LF3
VCC_SM_LF4
VCC_SM_LF5
VCC_SM_LF6
VCC_SM_LF7

VCC SM LF

T17
T18
T19
T21
T22
T23
T25
U15
U16
U17
U19
U20
U21
U23
U26
V16
V17
V19
V20
V21
V23
V24
Y15
Y16
Y17
Y19
Y20
Y21
Y23
Y24
Y26
Y28
Y29
AA16
AA17
AB16
AB19
AC16
AC17
AC19
AD15
AD16
AD17
AF16
AF19
AH15
AH16
AH17
AH19
AJ16
AJ17
AJ19
AK16
AK19
AL16
AL17
AL19
AL20
AL21
AL23
AM15
AM16
AM19
AM20
AM21
AM23
AP15
AP16
AP17
AP19
AP20
AP21
AP23
AP24
AR20
AR21
AR23
AR24
AR26
V26
V28
V29
Y31

AW45
BC39
BE39
BD17
BD4
AW8
AT6

+VCCP

VCCSM_LF1
VCCSM_LF2
VCCSM_LF3
VCCSM_LF4
VCCSM_LF5
VCCSM_LF6
VCCSM_LF7

VCC_AXG=7700mA

0.1U_0402_16V4Z

C121

1

2

0.22U_0603_10V7K

C145 0.1U_0402_16V4Z

C146 0.1U_0402_16V4Z

1

1

2

2

C122

1

1

2

C147 0.22U_0603_10V7K

1

1

2

2

C148 0.22U_0603_10V7K

1

2

C123

2

4.7U_0805_10V4Z

C149 0.47U_0603_10V7K

C150 1U_0603_10V4Z

1

1

2

2

C151 1U_0603_10V4Z

A A

CRES TLINE_1p0

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/02/13 2006/03/10

Compal Secret Data

Deciphered Date

Title

Size Doc ument Number Re v

Cus tom

2

Date: Sheet of

Compal Electronics, Inc.

CRESTLINE((5/6)-PWR/GND

LA-3821P

1

11 43Tues day, July 3 1, 2007

0.3

5

U3I

A13

VSS_1

A15

VSS_2

A17

VSS_3

A24

VSS_4

AA21

VSS_5

AA24

VSS_6

AA29

VSS_7

AB20

D D

C C

B B

A A

AB23
AB26
AB28

AB31
AC10
AC13

AC39
AC43
AC47

AD21
AD26
AD29

AD41
AD45
AD49

AD50

AE10

AE14

AF20

AF23

AF24

AF31

AG2
AG38
AG43
AG47
AG50

AH40
AH41

AJ11

AJ13

AJ21

AJ24

AJ29

AJ32

AJ43

AJ45

AJ49

AK20
AK21
AK26
AK28
AK31
AK51

AM11
AM13

AM3

AM4
AM41
AM45

AN38
AN39
AN43

AP48
AP50

AR11

AR39
AR44
AR47

AT10
AT14
AT41
AT49

AU23
AU29

AU36
AU49
AU51

AV39
AV48

AW1

AW12
AW16

AC3

AD1

AD3

AD5

AD8

AE6

AH3

AH7
AH9

AL1

AN1

AN5
AN7
AP4

AR2

AR7

AU1

AU3

VSS_8
VSS_9
VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47
VSS_48
VSS_49
VSS_50
VSS_51
VSS_52
VSS_53
VSS_54
VSS_55
VSS_56
VSS_57
VSS_58
VSS_59
VSS_60
VSS_61
VSS_62
VSS_63
VSS_64
VSS_65
VSS_66
VSS_67
VSS_68
VSS_69
VSS_70
VSS_71
VSS_72
VSS_73
VSS_74
VSS_75
VSS_76
VSS_77
VSS_78
VSS_79
VSS_80
VSS_81
VSS_82
VSS_83
VSS_84
VSS_85
VSS_86
VSS_87
VSS_88
VSS_89
VSS_90
VSS_91
VSS_92
VSS_93
VSS_94
VSS_95
VSS_96
VSS_97
VSS_98
VSS_99

CRES TLINE_1p0

VSS

VSS_100
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105
VSS_106
VSS_107
VSS_108
VSS_109
VSS_110
VSS_111
VSS_112
VSS_113
VSS_114
VSS_115
VSS_116
VSS_117
VSS_118
VSS_119
VSS_120
VSS_121
VSS_122
VSS_123
VSS_124
VSS_125
VSS_126
VSS_127
VSS_128
VSS_129
VSS_130
VSS_131
VSS_132
VSS_133
VSS_134
VSS_135
VSS_136
VSS_137
VSS_138
VSS_139
VSS_140
VSS_141
VSS_142
VSS_143
VSS_144
VSS_145
VSS_146
VSS_147
VSS_148
VSS_149
VSS_150
VSS_151
VSS_152
VSS_153
VSS_154
VSS_155
VSS_156
VSS_157
VSS_158
VSS_159
VSS_160
VSS_161
VSS_162
VSS_163
VSS_164
VSS_165
VSS_166
VSS_167
VSS_168
VSS_169
VSS_170
VSS_171
VSS_172
VSS_173
VSS_174
VSS_175
VSS_176
VSS_177
VSS_178
VSS_179
VSS_180
VSS_181
VSS_182
VSS_183
VSS_184
VSS_185
VSS_186
VSS_187
VSS_188
VSS_189
VSS_190
VSS_191
VSS_192
VSS_193
VSS_194
VSS_195
VSS_196
VSS_197
VSS_198

4

AW24
AW29
AW32
AW5
AW7
AY10
AY24
AY37
AY42
AY43
AY45
AY47
AY50
B10
B20
B24
B29
B30
B35
B38
B43
B46
B5
B8
BA1
BA17
BA18
BA2
BA24
BB12
BB25
BB40
BB44
BB49
BB8
BC16
BC24
BC25
BC36
BC40
BC51
BD13
BD2
BD28
BD45
BD48
BD5
BE1
BE19
BE23
BE30
BE42
BE51
BE8
BF12
BF16
BF36
BG19
BG2
BG24
BG29
BG39
BG48
BG5
BG51
BH17
BH30
BH44
BH46
BH8
BJ11
BJ13
BJ38
BJ4
BJ42
BJ46
BK15
BK17
BK25
BK29
BK36
BK40
BK44
BK6
BK8
BL11
BL13
BL19
BL22
BL37
BL47
C12
C16
C19
C28
C29
C33
C36
C41

3

U3J

C46

VSS_199

C50

VSS_200

C7

VSS_201

D13

VSS_202

D24

VSS_203

D3

VSS_204

D32

VSS_205

D39

VSS_206

D45

VSS_207

D49

VSS_208

E10

VSS_209

E16

VSS_210

E24

VSS_211

E28

VSS_212

E32

VSS_213

E47

VSS_214

F19

VSS_215

F36

VSS_216

F4

VSS_217

F40

VSS_218

F50

VSS_219

G1

VSS_220

G13

VSS_221

G16

VSS_222

G19

VSS_223

G24

VSS_224

G28

VSS_225

G29

VSS_226

G33

VSS_227

G42

VSS_228

G45

VSS_229

G48

VSS_230

G8

VSS_231

H24

VSS_232

H28

VSS_233

H4

VSS_234

H45

VSS_235

J11

VSS_236

J16

VSS_237

J2

VSS_238

J24

VSS_239

J28

VSS_240

J33

VSS_241

J35

VSS_242

J39

VSS_243

K12

VSS_245

K47

VSS_246

K8

VSS_247

L1

VSS_248

L17

VSS_249

L20

VSS_250

L24

VSS_251

L28

VSS_252

L3

VSS_253

L33

VSS_254

L49

VSS_255

M28

VSS_256

M42

VSS_257

M46

VSS_258

M49

VSS_259

M5

VSS_260

M50

VSS_261

M9

VSS_262

N11

VSS_263

N14

VSS_264

N17

VSS_265

N29

VSS_266

N32

VSS_267

N36

VSS_268

N39

VSS_269

N44

VSS_270

N49

VSS_271

N7

VSS_272

P19

VSS_273

P2

VSS_274

P23

VSS_275

P3

VSS_276

P50

VSS_277

R49

VSS_278

T39

VSS_279

T43

VSS_280

T47

VSS_281

U41

VSS_282

U45

VSS_283

U50

VSS_284

V2

VSS_285

V3

VSS_286

CRES TLINE_1p0

VSS

VSS_287
VSS_288
VSS_289
VSS_290
VSS_291
VSS_292
VSS_293
VSS_294
VSS_295
VSS_296
VSS_297
VSS_298
VSS_299
VSS_300
VSS_301
VSS_302
VSS_303
VSS_304
VSS_305

VSS_306
VSS_307
VSS_308
VSS_309
VSS_310
VSS_311
VSS_312
VSS_313

W11
W39
W43
W47
W5
W7
Y13
Y2
Y41
Y45
Y49
Y5
Y50
Y11
P29
T29
T31
T33
R28

AA32
AB32
AD32
AF28
AF29
AT27
AV25
H50

2

1

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/02/13 2006/03/10

Compal Secret Data

Deciphered Date

Title

Size Doc ument Number Re v

Cus tom

2

Date: Sheet of

Compal Electronics, Inc.

CRESTLINE((6/6)-PWR/GND

LA-3821P

1

12 43Tues day, July 3 1, 2007

0.3

5

DDR_A _DQS#[0.. 7]8

DDR_ A_D[0..63 ]8

DDR_A _DM[0..7]8

DDR_A _DQS[0..7 ]8

DDR_A _MA[0..14]7,8

D D

Lay out Not e:
Pl ac e near JP3 4

+1.8V

2.2U_0805_16V4Z

2.2U_0805_16V4Z

C C

B B

A A

Lay out Not e:
Pl ac e one ca p c los e t o e ver y 2 pu llu p
res ist ors te rmi nate d to + 0.9VS

+0.9V

0.1U_0402_16V4Z

DDR_A_MA3
DDR_A_MA10

DDR_A_MA8
DDR_A_MA5

DDR_A _RAS#
DDR_C S0_DIMMA#

DDR_A_MA1
DDR_A_BS 0

DDR_A_W E#
DDR_A _CAS#

DDR_C S1_DIMMA# M_ODT0
M_ODT1

DDR_A_MA11

C155

1

2

1

2

C164

C156

1

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

2

C165

RP1

RP3

RP5

RP7

RP9

RP11

R86 56_0402_ 5%

5

2.2U_0805_16V4Z

C157

1

2

0.1U_0402_16V4Z

1

2

C166

1 4
2 3

56_0404_4P2R_5%

1 4
2 3

56_0404_4P2R_5%

1 4
2 3

56_0404_4P2R_5%

1 4
2 3

56_0404_4P2R_5%

1 4
2 3

56_0404_4P2R_5%

2 3
1 4

56_0404_4P2R_5%

1 2

2.2U_0805_16V4Z

C158

1

2

0.1U_0402_16V4Z

1

1

2

2

C167

C168

+0.9V

0.1U_0402_16V4Z

2.2U_0805_16V4Z

C159

1

1

2

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

2

2

C169

C170

RP2 56_0404_4P2R_5%

DDR_CKE 0_DIMMA

14

DDR_A_BS 2

23

RP4 56_0404_4P2R_5%

DDR_A_MA7

14

DDR_A_MA6

23

RP6 56_0404_4P2R_5%

DDR_A_MA12

14

DDR_A_MA9

23

RP8 56_0404_4P2R_5%

DDR_A_MA4

14

DDR_A_MA2

23

RP10 56_0404_4P 2R_5%

DDR_A_MA0

14

DDR_A_BS 1

23

RP12 56_0404_4P 2R_5%

14

DDR_A_MA13

23

RP13 56_0404_4P 2R_5%

DDR_CKE 1_DIMMA

14

DDR_A_MA14

23

0.1U_0402_16V4Z

C160

1

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

2

C171

4

0.1U_0402_16V4Z

0.1U_0402_16V4Z

C162

C161

1

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

2

2

C173

C172

1

C163

1

+

C154

330U_4V_M

2

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

1

2

2

2

C174

La yout Note :
Pl ac e the se res ist or
cl osely JP34 ,all
tr ace len gth Max= 1.5"

C176

C175

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

+1.8V

JP4

1

VREF

3

DDR_A _D4
DDR_A _D1

DDR_A _DQS#0
DDR_A _DQS0

DDR_A _D2
DDR_A _D3

DDR_A _D8
DDR_A _D14

DDR_A _DQS#1
DDR_A _DQS1

DDR_A _D9 DDR_A _D11
DDR_A _D15 DDR_A_D1 0

DDR_A _D16
DDR_A _D17

DDR_A _DQS#2
DDR_A _DQS2

DDR_A _D18
DDR_A _D19

DDR_A_DM 3

DDR_A _D26
DDR_A _D27

DDR_C KE0_DIMMA7

DDR_A_BS 28

DDR_A_BS 08

DDR_A_W E#8

DDR_A _CAS#8

DDR_CS1_D IMMA#7

M_ODT17

CLK_SMBDATA14,15

CLK_SMBCLK14,15

3

DDR_CKE 0_DIMMA

DDR_A_BS 2

DDR_A_MA12
DDR_A_MA9 DDR_A_MA7
DDR_A_MA8

DDR_A_MA5
DDR_A_MA3
DDR_A_MA1

DDR_A_MA10
DDR_A_BS 0
DDR_A_W E#

DDR_A _CAS#
DDR_C S1_DIMMA#

M_ODT1

DDR_A _D37
DDR_A _D36

DDR_A _DQS#4
DDR_A _DQS4

DDR_A _D35
DDR_A _D32

DDR_A _D40
DDR_A _D44

DDR_A_DM 5

DDR_A _D41
DDR_A _D46

DDR_A _D49
DDR_A _D48

DDR_A _DQS#6
DDR_A _DQS6

DDR_A _D50

DDR_A _D61 DDR_A_D5 7
DDR_A _D60

DDR_A_DM 7

DDR_A _D59
DDR_A _D58

CLK_SMBDATA
CLK_SMBCLK

+3VS

1

2

2.2U_0805_16V4Z

2006/02/13 2006/03/10

C178

C177

Compal Secret Data

1

2

VSS

5

DQ0

7

DQ1

9

VSS

11

DQS0#

13

DQS0

15

VSS

17

DQ2

19

DQ3

21

VSS

23

DQ8

25

DQ9

27

VSS

29

DQS1#

31

DQS1

33

VSS

35

DQ10

37

DQ11

39

VSS

41

VSS

43

DQ16

45

DQ17

47

VSS

49

DQS2#

51

DQS2

53

VSS

55

DQ18

57

DQ19

59

VSS

61

DQ24

63

DQ25

65

VSS

67

DM3

69

NC

71

VSS

73

DQ26

75

DQ27

77

VSS

79

CKE0

81

VDD

83

NC

85

BA2

87

VDD

89

A12

91

A9

93

A8

95

VDD

97

A5

99

A3

101

A1

103

VDD

105

A10/AP

107

BA0

109

WE#

111

VDD

113

CAS#

115

NC/S1#

117

VDD

119

NC/ODT1

121

VSS

123

DQ32

125

DQ33

127

VSS

129

DQS4#

131

DQS4

133

VSS

135

DQ34

137

DQ35

139

VSS

141

DQ40

143

DQ41

145

VSS

147

DM5

149

VSS

151

DQ42

153

DQ43

155

VSS

157

DQ48

159

DQ49

161

VSS

163

NC,TEST

165

VSS

167

DQS6#

169

DQS6

171

VSS

173

DQ50

175

DQ51

177

VSS

179

DQ56

181

DQ57

183

VSS

185

DM7

187

VSS

189

DQ58

191

DQ59

193

VSS

195

SDA

197

SCL

199

VDDSPD

203

GND

FOX_ASOA426-M4R-TR

CONN@

SO-DIMM A

SP07F001720 S SOCKET FOXCONN AS0A426-N4RN-7F DR2R H4
FOX_AS0A426-M4R-TR_200P

0.1U_0402_16V4Z

Deciphered Date

VSS
DQ4
DQ5
VSS

DM0

VSS
DQ6
DQ7

VSS
DQ12
DQ13

VSS

DM1

VSS

CK0

CK0#

VSS
DQ14
DQ15

VSS

VSS
DQ20
DQ21

VSS

DM2

VSS
DQ22
DQ23

VSS
DQ28
DQ29

VSS

DQS3#

DQS3

VSS
DQ30
DQ31

VSS

NC/CKE1

VDD
NC/A15
NC/A14

VDD

VDD

VDD

BA1

RAS#

VDD

ODT0

NC/A13

VDD

VSS
DQ36
DQ37

VSS

DM4

VSS
DQ38
DQ39

VSS
DQ44
DQ45

VSS

DQS5#

DQS5

VSS
DQ46
DQ47

VSS
DQ52
DQ53

VSS

CK1

CK1#

VSS

DM6

VSS
DQ54
DQ55

VSS
DQ60
DQ61

VSS

DQS7#

DQS7

VSS
DQ62
DQ63

VSS

SAO

SA1

GND

2

+1.8V

V_DDR _MCH_REF

2

DDR_A _D6

4

DDR_A _D0

6
8

DDR_A_DM 0

10
12

DDR_A _D5

14

DDR_A _D7

16
18

DDR_A _D13

20

DDR_A _D12

22
24

DDR_A_DM 1

26
28

M_CLK_DD R0

30

M_CLK_DDR#0

32
34
36
38
40

42

DDR_A _D20

44

DDR_A _D21

46
48
50

NC

A11

A7
A6

A4
A2
A0

S0#

NC

2

52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
204

DDR_A_DM 2

DDR_A _D23
DDR_A _D22

DDR_A _D28DDR_A _D29
DDR_A _D25DDR_A _D24

DDR_A _DQS#3
DDR_A _DQS3

DDR_A _D31
DDR_A _D30

DDR_CKE 1_DIMMA

DDR_A_MA14

DDR_A_MA11

DDR_A_MA6

DDR_A_MA4
DDR_A_MA2
DDR_A_MA0

DDR_A_BS 1
DDR_A _RAS#
DDR_C S0_DIMMA#

M_ODT0
DDR_A_MA13

DDR_A _D39
DDR_A _D38

DDR_A_DM 4

DDR_A _D34
DDR_A _D33

DDR_A _D45
DDR_A _D43

DDR_A _DQS#5
DDR_A _DQS5

DDR_A _D47
DDR_A _D42

DDR_A _D52
DDR_A _D53

M_CLK_DD R1
M_CLK_DDR#1

DDR_A_DM 6

DDR_A _D51DDR_A _D54
DDR_A _D55

DDR_A _D56

DDR_A _DQS#7
DDR_A _DQS7

DDR_A _D62
DDR_A _D63

12

R84

R85

10K_0402_5%

10K_0402_5%

12

2.2U_0805_16V4Z

C152

1

2

M_CLK_DD R0 7
M_CLK_DD R#0 7

PM_EXTTS#0 7

DDR_C KE1_DIMMA 7

DDR_A_BS 1 8
DDR_A _RAS# 8
DDR_C S0_DIMMA# 7

M_ODT0 7

M_CLK_DD R1 7
M_CLK_DD R#1 7

Title

Size Doc ument Number Re v

Cus tom

Date: Sheet of

Compal Electronics, Inc.

DDRII-SODIMM SLOT1

LA-3821P

1

C153

1

V_DDR _MCH_REF 7,14 ,37

0.3

13 43Tues day, July 3 1, 2007

0.1U_0402_16V4Z

1

2

5

DDR_B _DQS#[0.. 7]8

DDR_ B_D[0..63 ]8

DDR_B _DM[0..7]8

DDR_B _DQS[0..7 ]8

DDR_B _MA[0..14]7,8

D D

C C

B B

A A

Lay out Not e:
Pl ac e near JP1 0

+1.8V

2.2U_0805_16V4Z

0.1U_0402_16V4Z

C182

1

2

0.1U_0402_16V4Z

1

2

C191

RP14

1 4
2 3

56_0404_4P2R_5%

RP16

1 4
2 3

RP18

56_0404_4P2R_5%

1 4
2 3

56_0404_4P2R_5%

RP20

1 4
2 3

56_0404_4P2R_5%

RP22

1 4
2 3

RP24

56_0404_4P2R_5%

2 3
1 4

56_0404_4P2R_5%

1 2

R89

56_0402_5%

5

2.2U_0805_16V4Z

C183

1

2

0.1U_0402_16V4Z

1

2

C192

2.2U_0805_16V4Z

C181

1

2

Lay out Not e:
Pl ac e one ca p c los e t o e ver y 2 pu llu p
res ist ors te rmi nate d to + 0.9VS

+0.9V

0.1U_0402_16V4Z

1

2

C190

DDR_B_MA1
DDR_B_MA3

DDR_B_BS 0
DDR_B_MA10

DDR_B_MA0
DDR_B_BS 1

DDR_B _RAS#
DDR_C S2_DIMMB#

DDR_B _CAS#
DDR_B_W E#

DDR_C S3_DIMMB# M_ODT2
M_ODT3

DDR_CKE 3_DIMMB

2.2U_0805_16V4Z

C184

1

2

0.1U_0402_16V4Z

1

1

2

2

C193

C194

+0.9V

RP15 56_0404_4P 2R_5%

RP17 56_0404_4P 2R_5%

RP19 56_0404_4P 2R_5%

RP21 56_0404_4P 2R_5%

RP23 56_0404_4P 2R_5%

RP25 56_0404_4P 2R_5%

RP26

56_0404_4P2R_5%

2.2U_0805_16V4Z

C185

1

2

0.1U_0402_16V4Z

1

2

C195

14
23

14
23

14
23

14
23

14
23

14
23

14
23

0.1U_0402_16V4Z

0.1U_0402_16V4Z

C186

1

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

2

2

C196

C197

DDR_B_MA9
DDR_B_MA12

DDR_B_MA14
DDR_B_MA11

DDR_B_MA5
DDR_B_MA8

DDR_B_MA7
DDR_B_MA6

DDR_B_MA4
DDR_B_MA2

DDR_B_MA13

DDR_B_BS 2
DDR_CKE 2_DIMMB

0.1U_0402_16V4Z

C187

1

2

0.1U_0402_16V4Z

1

2

C198

0.1U_0402_16V4Z

C188

1

1

2

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

2

2

C200

C199

La yout Note :
Pl ac e the se res ist or
cl osely JP10 ,all
tr ace len gth Max= 1.5"

4

C189

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

2

2

C201

C202

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

+1.8V

JP5

1

VREF

3

DDR_B _D0
DDR_B _D1

DDR_B _DQS#0
DDR_B _DQS0

DDR_B _D2
DDR_B _D3

DDR_B _D8
DDR_B _D9

DDR_B _DQS#1
DDR_B _DQS1

DDR_B _D10
DDR_B _D11

DDR_B _D20

DDR_B _DQS#2
DDR_B _DQS2

DDR_B _D18
DDR_B _D19

DDR_B _D28

DDR_B_DM 3

DDR_B _D30
DDR_B _D31

DDR_CKE 2_DIMMB7

DDR_B _BS28

DDR_B _BS08

DDR_B _WE#8

DDR_B _CAS#8

DDR_CS3_D IMMB#7

M_ODT37

CLK_SMBDATA13,15

CLK_SMBCLK13,15

+3VS

3

DDR_CKE 2_DIMMB

DDR_B_BS 2

DDR_B_MA12
DDR_B_MA9
DDR_B_MA8

DDR_B_MA5
DDR_B_MA3
DDR_B_MA1

DDR_B_MA10
DDR_B_BS 0
DDR_B_W E#

DDR_B _CAS#
DDR_C S3_DIMMB#

M_ODT3

DDR_B _D32
DDR_B _D33

DDR_B _DQS#4
DDR_B _DQS4

DDR_B _D34
DDR_B _D35

DDR_B _D40
DDR_B _D41

DDR_B_DM 5

DDR_B _D42
DDR_B _D43

DDR_B _D48
DDR_B _D49

DDR_B _DQS#6
DDR_B _DQS6

DDR_B _D51
DDR_B _D50

DDR_B _D56
DDR_B _D61 DDR_B_D5 7

DDR_B_DM 7

DDR_B _D59
DDR_B _D58

CLK_SMBDATA
CLK_SMBCLK

C204

1

2

Compal Secret Data

1

C203

2

2.2U_0805_16V4Z

2006/02/13 2006/03/10

VSS

5

DQ0

7

DQ1

9

VSS

11

DQS0#

13

DQS0

15

VSS

17

DQ2

19

DQ3

21

VSS

23

DQ8

25

DQ9

27

VSS

29

DQS1#

31

DQS1

33

VSS

35

DQ10

37

DQ11

39

VSS

41

VSS

43

DQ16

45

DQ17

47

VSS

49

DQS2#

51

DQS2

53

VSS

55

DQ18

57

DQ19

59

VSS

61

DQ24

63

DQ25

65

VSS

67

DM3

69

NC

71

VSS

73

DQ26

75

DQ27

77

VSS

79

CKE0

81

VDD

83

NC

85

BA2

87

VDD

89

A12

91

A9

93

A8

95

VDD

97

A5

99

A3

101

A1

103

VDD

105

A10/AP

107

BA0

109

WE#

111

VDD

113

CAS#

115

NC/S1#

117

VDD

119

NC/ODT1

121

VSS

123

DQ32

125

DQ33

127

VSS

129

DQS4#

131

DQS4

133

VSS

135

DQ34

137

DQ35

139

VSS

141

DQ40

143

DQ41

145

VSS

147

DM5

149

VSS

151

DQ42

153

DQ43

155

VSS

157

DQ48

159

DQ49

161

VSS

163

NC,TEST

165

VSS

167

DQS6#

169

DQS6

171

VSS

173

DQ50

175

DQ51

177

VSS

179

DQ56

181

DQ57

183

VSS

185

DM7

187

VSS

189

DQ58

191

DQ59

193

VSS

195

SDA

197

SCL

199

VDDSPD

201

GND

FOX_AS0A426-N8RN -7F

CONN@

SO-DIMM B

SP07000BZ00 S SOCKET FOXCON AS0A426-N8RN-7F H8 DDR2R
FOX_AS0A426-N8RN-7F_200P

0.1U_0402_16V4Z

Deciphered Date

DQ4
DQ5

DM0

DQ6
DQ7

DQ12
DQ13

DM1

CK0#

DQ14
DQ15

DQ20
DQ21

DM2

DQ22
DQ23

DQ28
DQ29

DQS3#

DQS3

DQ30
DQ31

NC/CKE1

VDD
NC/A15
NC/A14

VDD

VDD

VDD

RAS#

VDD

ODT0

NC/A13

VDD

DQ36
DQ37

DM4

DQ38
DQ39

DQ44
DQ45

DQS5#

DQS5

DQ46
DQ47

DQ52
DQ53

CK1#

DM6

DQ54
DQ55

DQ60
DQ61

DQS7#

DQS7

DQ62
DQ63

GND

VSS

VSS

VSS

VSS

VSS

VSS
CK0

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

BA1

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS
CK1

VSS

VSS

VSS

VSS

VSS

VSS
SA0
SA1

2

+1.8V

V_DDR _MCH_REF

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

42
44
46
48
50

NC

52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90

A11

92

A7

94

A6

96
98

A4

100

A2

102

A0

104
106
108
110

S0#

112
114
116
118
120

NC

122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202

2

DDR_B _D5
DDR_B _D4

DDR_B_DM 0

DDR_B _D6
DDR_B _D7

DDR_B _D12
DDR_B _D13

DDR_B_DM 1

M_CLK_DD R3
M_CLK_DDR#3

DDR_B _D14
DDR_B _D15

DDR_B _D21DDR_B _D17
DDR_B _D16

DDR_B_DM 2

DDR_B _D22
DDR_B _D23

DDR_B _D26
DDR_B _D24DDR_B _D25

DDR_B _DQS#3
DDR_B _DQS3

DDR_B _D29
DDR_B _D27

DDR_CKE 3_DIMMB

DDR_B_MA14

DDR_B_MA11
DDR_B_MA7
DDR_B_MA6

DDR_B_MA4
DDR_B_MA2
DDR_B_MA0

DDR_B_BS 1
DDR_B _RAS#
DDR_C S2_DIMMB#

M_ODT2
DDR_B_MA13

DDR_B _D36
DDR_B _D37

DDR_B_DM 4

DDR_B _D39
DDR_B _D38

DDR_B _D44
DDR_B _D45

DDR_B _DQS#5
DDR_B _DQS5

DDR_B _D46
DDR_B _D47

DDR_B _D52
DDR_B _D53

M_CLK_DD R2
M_CLK_DDR#2

DDR_B_DM 6

DDR_B _D54
DDR_B _D55

DDR_B _D60

DDR_B _DQS#7
DDR_B _DQS7

DDR_B _D62
DDR_B _D63

10K_0402_5%

12

R88

2.2U_0805_16V4Z

0.1U_0402_16V4Z

1

1

C179

2

2

M_CLK_DD R3 7
M_CLK_DD R#3 7

PM_EXTTS#1 7

DDR_C KE3_DIMMB 7

DDR_B_BS 1 8
DDR_B _RAS# 8
DDR_C S2_DIMMB# 7

M_ODT2 7

M_CLK_DD R2 7
M_CLK_DD R#2 7

R87

1 2

10K_0402_5%

Title

Size Doc ument Number Re v

Date: Sheet of

+3VS

Compal Electronics, Inc.

DDRII-SODIMM SLOT2

LA-3821P

1

V_DDR _MCH_REF 7,13 ,37

C180

1

14 43Tues day, July 3 1, 2007

0.3

5

PCI

SRC

CPU

CLK SEL1

FSLA

CLK SEL0

MHz

MHz

MHz

FSLC FSLB

CLK SEL2

0 1 1000 133 33.3

0

1 200

1

FSB Frequency Selet:

D D

CPU Driven

(Default)

*

Stuff

No Stuff

Stuff

667MHz

No Stuff

Stuff

800MHz

C C

CPU_BSEL05

CPU_BSEL15

B B

CPU_BSEL25

+3VS +3VS +3VS

A A

1 2

1 2

No Stuff

R98

2.2K_0402_5%

FSA

NO SHO RT PADS

FSC

R138
10K_0402_5%

XDP@

ITP_EN 27_SEL PCI2_TME

R144
10K_0402_5%

CLRP2

FSB

1 2

R114

0_0402_5%

R128

10K_0402_5%

1 2

R130

0_0402_5%

R139
10K_0402_5%

@

1 2

R145
10K_0402_5%

1 2

12

12

+VCCP

+VCCP

12

5

100

33.30

100

1661

33.30

R1107 R1135 R1083

R1074 R1086 R1098 R1113 R1139

R1139 R1135R1135 R1139

R1083

R1107

R1128

R1098

R1113

R1128

R1074R1086

R1135 R1139

R1083

R1086

R1098

R1074

R1107

R94

1 2

12

56_0402_5%

CLRP1
NO SHO RT PADS

1 2

R99

1K_0402_5%

12

R103

1K_0402_5%@

Remov e PCI L AN,Cha nge to Debug clock

R110

1K_0402_5%@

1 2

1 2

R113

1K_0402_5%

12

R117

@

0_0402_5%

R124

1K_0402_5%@

1 2

1 2

R129

1K_0402_5%

12

R133

@

0_0402_5%

R1128

R1113

+VCCP

MCH_CLKSEL0 7

MCH_CLKSEL1 7

MCH_CLKSEL2 7

CLRP 4,CL RP5 for 66 7/800 FSB se lect
SHOR T CL RP5, NO S HORT CLRP4 -- CPU optio n
SHOR T CL RP4, NO S HORT CLRP5 -- FSB 667

0301 _Cha nge R105 from 22 ohm to 0 ohm.
0312 _Cha nge R10 6, 107, 109 from 22 to 33 ohm.

CLKSATAREQ#20

CLK_DEBU G_PORT_022
CLK_DEBU G_PORT_131
CLK_DEBU G_PORT_232

CLK_P CI_EC32

CLK_P CI_ICH18

Ro utin g t he tra ce at
lea st 10m il

CLK_48M_ICH20

CLK_14M_ICH20

CLK_14M_DEBUG32

For ITP_ EN, 0 =SR C8/SRC8#; 1 = ITP/ITP#

For 27_S EL, 0 = En able DOT96 & SRC1,

R140
10K_0402_5%

1 2

R146
10K_0402_5%

@

1 2

1= E nable S RC0 & 27MHz

For PCI2 _EN, 0 = Overcl ocking of CP U and SRC Al lowed

1 = Over clockin g of CPU and SRC NOT al lowed

For Layout re quest:

1. C hang e MINI_ CLKREQ# from pin 32 to pin 43.

2. C hang e CLK_P CIE_MCARD fr om SRC9 to SRC6.

4

1 2

+3VS

FBMA-L11-201209-221LMA30T_0805

CLKREQ#_B7

C224

18P_0402_50V8J

4

+3VS_CK505

R90

+1.25VS_CK505

1 2

1 2

1 2
1 2
1 2

1 2

1 2

Y1

14.31818MHZ_16P

2

1

1 2

1 2

1 2

3

1

C205

10U_0805_10V4Z

2

FBMA-L11-201209-221LMA30T_0805

1

C206

0.1U_0402_16V4Z

2

+1.25VS

1 2

R93

1

C207
680P_0402_50V7K

2

1

C212

2

10U_0805_10V4Z

0.1U_0402_16V4Z

1

C213

2

1

C208

0.1U_0402_16V4Z

2

680P_0402_50V7K

1

C209
680P_0402_50V7K

2

Pla ce cl ose to U4

10U_0805_10V4Z

1

1

C214

C215

2

2

1

C210

0.1U_0402_16V4Z

2

0.1U_0402_16V4Z

1

C216

2

680P_0402_50V7K

+1.25VS_CK505

0308_Cha nge R89 and R92 form 0 ohm to bead, C209, C211, C216, C218 from 0.1uF to 680pF.

12

2

1

+3VS_CK505

R104475_0402_1%

R105475_0402_1%

R10622_0402_5%
R35422_0402_5%
R1070_0402_5%

R10833_0402_5%

R10933_0402_5%

CLK_XTAL_IN

CLK_XTAL_OUT

C225
18P_0402_50V8J

R11933_0402_1%

R12333_0402_1%

R12533_0402_1% @

+1.25VS_CK505

PCI_CLK1

PCI2_TME

PCI3

FSA

FSB

FSC

U4

2

VDD_PCI

9

VDD48

16

VDDPLL3

61

VDDREF

39

VDDSRC

55

VDDCPU

12

VDD96_IO

20

VDDPLL3_IO

26

VDDSRC_IO

36

VDDSRC_IO

49

VDDCPU_IO

1

PCI0/CR#_A

3

PCI1/CR#_B

4

PCI2/TME

5

PCI3

27_SEL

6

PCI4/27_Select

ITP_EN

7

PCIF5/ITP_EN

60

X1

59

X2

10

USB_48MHZ/FSLA

57

FSLB/TEST MODE

62

REF0/FSLC/TEST_SEL

45

VDDSRC_IO

42

GNDSRC

8

GNDPCI

11

GND48

15

GND

19

GND

52

GNDCPU

23

GNDSRC

29

GNDSRC

58

GNDREF

* Int ernal P ull-Up Resis tor
** In ternal Pull-D own Re sistor

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

CPU_STOP#

SRC11/CR#_H

SRC11#/CR#_G

SRC7/CR#_F

SRC7#/CR#_E

SRC3/CR#_C

SRC3#/CR#_D

SRC2#/SATA#

SRC1/SE1/27MHz_NonSS

SRC1#/SE2/27MHz_SS

SRC0/DOT96

SRC0/DOT96#

CK_PWRGD/PD#

ICS9LPRS355_TSSOP64

2006/02/13 2006/03/10

SCLK

SDATA

PCI_STOP#

CPU0

CPU0#

CPU1_F

CPU1#_F

SRC8/ITP

SRC8#/ITP#

SRC10#

SRC10

SRC9

SRC9#

SRC6

SRC6#

SRC4

SRC4#

SRC2/SATA

48

NC

CLK_SMBCLK

64

CLK_SMBDATA

63

38
37

R_CPU _BCLK

54

R_CPU _BCLK#

53

R_MCH_BCLK

51

R_MCH_BCLK#

50

R_CLK _PCIE_MCARD_ROB

47

R_CLK _PCIE_MCARD_ROB#

46

R_CLK _PCIE_NCAR D#

35

R_CLK _PCIE_NCAR D

34

NCAR D_CLKREQ_R#

33
32

R_CLK _PCIE_LAN

30

R_CLK _PCIE_LAN#

31

R_MIN I_ROB_CLKREQ#

44

R_CLKR EQ#_G

43

R_CLK _PCIE_MCard

41

R_CLK _PCIE_MCard#

40

R_MCH_3GPLL

27

R_MCH_3GPLL#

28

R_P CIE_ICH

24

R_PCI E_ICH#

25

R_PCIE_SATA

21

R_PCIE_SATA#

22

SSCD REFCLK

17

SSCD REFCLK#

18

R_MC H_DREFCLK

13

R_MC H_DREFCLK#

14

56

Compal Secret Data

R95

1 2
1 2

R96

R97

1 2
1 2

R100

R335 475_0402_1%

R111

1 2
1 2

R112

R115

R333

R118

1 2
1 2

R120

R121

1 2
1 2

R122

R126

1 2
1 2

R127

R131

1 2
1 2

R132

R134 0_0402_5%

1 2

R135 0_0402_5%

1 2

R136

1 2
1 2

R137

1 2

R141 0_0402_5%@

1 2

R142 0_0402_5%@

1 2

R143 0_0402_5%

Deciphered Date

2

1

C217

2

R438

1 2
1 2

R437

R440

1 2
1 2

R439

12

475_0402_1%

475_0402_1%

2

1

2

0_0402_5%
0_0402_5%

0_0402_5%
0_0402_5%

1 2

R334

0_0402_5%
0_0402_5%

12
12

0_0402_5%
0_0402_5%

0_0402_5%
0_0402_5%

0_0402_5%
0_0402_5%

0_0402_5%
0_0402_5%

0_0402_5%
0_0402_5%

C211

0.1U_0402_16V4Z

SB, MINI PCI

0_0402_5%
0_0402_5%

0_0402_5%
0_0402_5%

10K_0402_5%

1 2

R332 10K_0402_5%

R116 10K_0402_5%

1 2

1

+3VS

R91

2.2K_0402_5%

D

ICH_SMBDATA20,22,23

ICH_SMBCLK20,22,23

CLK_SMBCLK 13,14
CLK_SMBDATA 13,14

H_STP_PCI# 20
H_STP_CPU# 20

CLK_CP U_BCLK 4
CLK_CP U_BCLK# 4

CLK_MCH_BCLK 7
CLK_MCH_BCLK# 7

CLK_P CIE_MCARD_ROB 22
CLK_P CIE_MCARD_ROB# 22

+3VS

NCAR D_CLKREQ# 23

CLK_P CIE_LAN 24
CLK_P CIE_LAN# 24

+3VS

MINI_R OB_CLKREQ# 22
MINI_C LKREQ# 22

+3VS

CLK_P CIE_MCARD 22
CLK_P CIE_MCARD# 22

CLK_MCH_3GPLL 7
CLK_MCH_3GPLL# 7

CLK_P CIE_ICH 20

CLK_P CIE_ICH# 20

CLK_PCIE_SATA 19
CLK_PCIE_SATA# 19

MCH_ SSCDREFCLK 7
MCH_ SSCDREFCLK# 7

CLK_M CH_DREFCLK 7
CLK_M CH_DREFCLK# 7

VGATE 20,39

CLK_ENABLE 32

CK_PW RGD 20

Title

Size Doc ument Number Re v

Date: Sheet of

1 3

G

+3VS

CLK_P CIE_NCARD# 23
CLK_P CIE_NCARD 23

2

2

1 3

D

G

Ne w c ard WLAN c loc k R EQ

Compal Electronics, Inc.

Clock generator

LA-3821P

Q3

S

2N7002_SOT23-3

Q4
2N7002_SOT23-3

S

C218

C219

C220

C221

C222

C223

C376

12

5P_0402_50V8C@

12

4.7P_0402_50V8C@

12

4.7P_0402_50V8C@

12

4.7P_0402_50V8C@

12

4.7P_0402_50V8C@

12

5P_0402_50V8C@

12

5P_0402_50V8C@

Min i c ard Robeson c lock REQ

Min i c ard WLA N c loc k R EQ

1

R92

2.2K_0402_5%

CLK_SMBDATA

CLK_SMBCLK

CLK_48M_ICH

CLK_14M_ICH

CLK_P CI_ICH

CLK_P CI_EC

CLK_DEBU G_PORT_0

CLK_DEBU G_PORT_1

CLK_DEBU G_PORT_2

15 43Tues day, July 3 1, 2007

0.3

A

B

C

D

E

1 1

2 2

R152

CRT _HSYNC9

CRT_ VSYNC9

1 2

R157

1 2

0_0402_5%

0_0402_5%

CRT_R9

CRT_G9

CRT_B9

C233

1 2

0.1U_0402_16V4Z

CR TVSYNC

CRTL_B
CRTL_G
CRTL_R

+5VS

1

2

5

P

A2Y

G

3

5

P

A2Y

G

3

D5

DAN217_SC5 9

@

2

3

EMI

1

U5

4

OE#

1

U6

4

OE#

D6

1

3

74AHCT1G125GW_SOT353-5

74AHCT1G125GW_SOT353-5

D7

1

DAN217_SC5 9

2

CRT_R

CRT_G

CRT_B

DAN217_SC5 9@

3

R147

@

EMI

Place close to JP6

+CRTVDD

1

2

1 2

75_0402_5%

C227

10P_0402_50V8J

@

CR T_HSYNC_R

CRT_V SYNC_R

R148

1 2

75_0402_5%

C228

+R_CRT_VCC , +CRTVDD (40mils)

+5VS

+R_CRT_VC C

1.1A_6 VDC_FUSE

0.1U_0402_16V4Z

CRTL_R

CRTL_G

CRTL_B

1

2

CR T_HSYNCRF LCRT HSYNC

CRT _VSYNCRFL

F1

21

C226

1

2

C234

10P_0402_50V8J

D8

2 1

RB411D_SOT23

CRT CONNECTOR

EMI

L2
MBK20 12800YZF

1 2

L3
MBK20 12800YZF

1 2

L4
MBK20 12800YZF

1 2

1

2

10P_0402_50V8J

@

1

2

R149

1 2

75_0402_5%

C229

10P_0402_50V8J

@

EMI

1

1

2

2

C230

22P_0402_50V8J

1 2

L5
FBM-L11-160808-800LMT_0603

1 2

L6
FBM-L11-160808-800LMT_0603

C232

C231

22P_0402_50V8J

22P_0402_50V8J

+CRTVDD

1

2

JP6

6

11

1
7

12

2
8

13

D

1 3

2

14

10
15

S

G

D

1 3

3
9

4

16

17

5

SUYIN_0 70549FR015S 208CR

Q5

CONN@

2N7002_SOT23-3

G

2

Q6

S

2N7002_SOT23-3

R155

2.2K_0402_5%

3V_DD CDA

3V_DD CCL

R156

2.2K_0402_5%

+3VS

R153

1 2

R154

1 2

+CRTV DD

R151 4.7K_0402_5%

R150 4.7K_0402_5%

1

2

1

1

2

2

C235 10P_0402_50V8J

C236 220P_ 0402_50V8J

C237 220P_ 0402_50V8J

EMI

NZQA5V6AXV5T1_SOT533-5

2

1 5

D4

@

CLO SE TO JP3

0_0402_5%

0_0402_5%

3VDDC DA 9

3VDDC CL 9

43

3 3

4 4

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2006/02/13 2006/07/26

Compal Secret Data

Deciphered Date

Title

Size Doc ument Number Re v

D

Date: Sheet of

Compal Electronics, Inc.

CRT & TVout Connector

LA-3821P

16 43Tues day, July 3 1, 2007

E

0.3

5

4

3

2

1

LVDS CONN

D D

0.1U_0402_16V4Z

2

112

4

4

3

6

5

6

8

8

7

10

9910

12

111112

14

14

13

16

16

15

18

18

17

20

20

19

22

21

22

24

24

23

26

25

26

28

27

28

30

29

30

GND1
GND2

C246

+LCDV DD

C238

+3VS+LCDVD D

1

2

1

2

1

C239

0.1U_0402_16V4Z

2

LVDSA2+
LVDSA2-

LVDSA1+
LVDSA1-

LVDSA0+
LVDSA0-

LVDSAC+

LVDSAC-

LVDSA2+ 9

LVDSA2- 9

LVDSA1+ 9

LVDSA1- 9

LVDSA0+ 9

LVDSA0- 9

LVDSAC+ 9
LVDSAC- 9

+3VS

R158

2.2K_0402_5%

LCD_C LK
LCD_DATA

+3VS

R292

4.7K_0402_5%

4/14

R161

1 2

0_0402_5%

BKOFF#32

ENABLT9,32

D9

CH751H-40PT_S OD323-2

D10

CH751H-40PT_S OD323-2

R164

100K_0402_5%

1 2

1 2

@

21

21

DIS PLAYOFF#

R159

2.2K_0402_5%

1 2

1 2

@

L7 0_ 0805_5%

1 2

L8

1 2

FBMA-L11-201209-221LMA30T_0805

INVPW R_B+B+

0308 _Res erve L10 and install L11 .

INVPW R_B+

+LCDVD D

+3VS

INV_PWM32

DAC_B RIG32

LCD_C LK9

C244

C243680P_0402_50V7K

C C

C242680P_0402_50V7K

1

12

12

2

680P_0402_50V7K

LCD_DATA9

1

C240

680P_0402_50V7K

2

DIS PLAYOFF#

1

C241

680P_0402_50V7K

2

INVTPWM

DAC_B RIG

LCD_C LK
LCD_DAT

LVDS connector

JP7

3

5

7

13
15
17
19
21
23
25
27
29

31
32

ACES_88242-3001

0308 _Ins tall all c ap for EMI r equest.

R160

100_0402_5%

Q8

1

2

+LCDVD D

12

13

D

S

2N7002_SOT23-3

+5VALW

R162
47K_0402_5%

1 2

2

G

13

D

2

G

S

Q9

C247

0.047U_0402_16V7K

SI2301BDS-T1-E3_SOT23-3

1

C245

4.7U_0805_10V4Z

2

Q7

1 3

D

2

S

G

4.7U_0805_10V4Z

B B

2N7002_SOT23-3

R163

12

1 2

100K_0402_5%

C248

0.22U_0402_10V4Z

ENAVDD9

R165

100K_0402_5%

A A

Avoi d Pa nel dis play garbage after powe r on.

5

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/02/13 2006/07/26

Compal Secret Data

Deciphered Date

Title

Size Doc ument Number Re v

2

Date: Sheet of

Compal Electronics, Inc.

LCD CONN.

LA-3821P

17 43Tues day, July 3 1, 2007

1

0.3

5

4

3

2

1

+3VS

1 2

R167 8.2K_0402_5%

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

12

R168 8.2K_0402_5%

D D

C C

R169 8.2K_0402_5%

R170 8.2K_0402_5%

R171 8.2K_0402_5%

R172 8.2K_0402_5%

R173 8.2K_0402_5%

R174 8.2K_0402_5%

+3VS

R176 8.2K_0402_5%

R177 8.2K_0402_5%

R178 8.2K_0402_5%

R180 8.2K_0402_5%

R181 8.2K_0402_5%

R182 8.2K_0402_5%

R183 8.2K_0402_5%

R184 8.2K_0402_5%

R185 8.2K_0402_5%

R186 8.2K_0402_5%

R188 8.2K_0402_5%

R189 8.2K_0402_5%

PCI_DEVSEL#

PCI_STOP#

PC I_TRDY#

PCI_FRAME#

PCI_PLOCK#

PCI _IRDY#

PCI_S ERR#

PCI_P ERR#

PCI_P IRQA#

PCI_P IRQB#

PCI_P IRQC#

PCI_P IRQD#

PCI_P IRQE#

PCI_P IRQF#

PCI_P IRQG#

PCI_P IRQH#

PCI_R EQ0#

PCI_R EQ1#

PCI_R EQ2#

PCI_R EQ3#

PCI_P IRQA#
PCI_P IRQB#
PCI_P IRQC#
PCI_P IRQD#

U7B

D20

AD0

E19
D19
A20
D17
A21
A19
C19
A18
B16
A12
E16
A14
G16
A15

B6

C11

A9
D11
B12
C12
D10

C7
F13
E11
E13
E12

D8

A6

E8

D6

A3

F9

B5

C5
A10

PCI

AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31

Interrupt I/F

PIRQA#
PIRQB#
PIRQC#
PIRQD#

ICH8M REV 1.0

REQ0#

GNT0#
REQ1#/GPIO50
GNT1#/GPIO51
REQ2#/GPIO52
GNT2#/GPIO53
REQ3#/GPIO54
GNT3#/GPIO55

C/BE0#
C/BE1#
C/BE2#
C/BE3#

IRDY#

PAR

PCIRST#

DEVSEL#

PERR#

PLOCK#

SERR#
STOP#
TRDY#

FRAME#

PLTRST#

PCICLK

PME#

PIRQE#/GPIO2
PIRQF#/GPIO3
PIRQG#/GPIO4
PIRQH#/GPIO5

PCI_R EQ0#

A4

PCI_GNT0#

D7

PCI_R EQ1#

E18
C18

PCI_R EQ2#

B19
F18

PCI_R EQ3#

A11

PCI_GNT3#

C10

C17
E15
F16
E17

PCI _IRDY#

C8
D9

PCI_P CIRST#

G6

PCI_DEVSEL#

D16

PCI_P ERR#

A7

PCI_PLOCK#

B7

PCI_S ERR#

F10

PCI_STOP#

C16

PC I_TRDY#

C9

PCI_FRAME#

A17

PCI_PLTRST#

AG24

CLK_P CI_ICH

B10

PCI_PME#

G7

PCI_P IRQE#

F8

PCI_P IRQF# CLK_PCI_I CH

G11

PCI_P IRQG#

F12

PCI_P IRQH#

B3

T24

R175

0_0402_5%

R179

CLK_P CI_ICH 15
PCI_PME# 32

0_0402_5%

Pla ce cl ose ly pin B10

R187

10_0402_5% @

C249

8.2P_0402_50V@

PCI_RST#

12

PLT_RST#

12

1 2

1

2

PCI_GNT0#

12

R166

@

1K_0402_5%

PCI_RST# 31,32

PLT_RST# 7,22,23,24

Boot BIOS Strap

PCI_GNT0# SPI_CS#1

0

1

1

0

1

Boot BIOS Location

SPI1

PCI

LPC

*

A16 swap override Strap

Low= A16 swap override Enble

*

PCI_GNT3# High= Default

B B

A A

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/02/13 2006/03/10

Compal Secret Data

Deciphered Date

Title

Size Doc ument Number Re v

2

Date: Sheet of

Compal Electronics, Inc.

ICH8(1/4)-PCI/INT

LA-3821P

18 43Tues day, July 3 1, 2007

1

0.3

5

4

3

2

1

+RTCVCC

R190 330K_0402_1%

LAN100_SLP

1 2

R192 1M_0402_5%

SM_INTR UDER#

1 2

R194 330K_0402_1%

ICH_IN TVRMEN

1 2

D D

15P_0402_50V8J

C C

B B

C250

1

2

R198

1 2

10M_0402_5%

2

R196

@

0_0402_5%

ICH_RTCX1

ICH_RTCX2

1

2

Y2

4IN1

OUT

32.768 KHZ_12.5P_1TJS125BJ2A251

NC3NC

020 5_C han ge Crys tal t ype.

@

0_0402_5%

1 2

1 2

C251
15P_0402_50V8J

R193

ICH8 M In ternal VR En able Strap
(Int erna l VR for VccSus1. 05, VccSus1. 5, VccCL1.5 )

ICH_I NTVRMEN

ICH8 M LAN10 0 SLP Strap
(Int erna l VR fo r VccLAN1.05 and VccCL1 .05)

ICH_ LAN100_SLP Low = Internal VR Disabled

Low = Inte rnal VR Disa bled
High = I nternal VR Enabled(Def ault)

High = I nternal VR Enabled(Def ault)

R200

+RTCVCC

ACZ_BITC LK_MDC25
ACZ_BITC LK27

ACZ_SD OUT_MDC25

1 2

20K_0402_5%

1U_0603_10V4Z

ACZ _SYNC27

ACZ_S YNC_MDC25

ACZ_RST#27,32

ACZ_RST#_MDC25

ACZ_S DIN027
ACZ_S DIN125

ACZ_SD OUT27

SATA_LED#30

SATA_RXN0_C22
SATA_RXP0_C22

SATA_TXN022
SATA_TXP022

2

C252

1

R203 24.9_0402_1%
R338 47_0402_5%
R204 47_0402_5%
R206 33_0402_5%
R341 33_0402_5%
R207 33_0402_5%
R445 33_0402_5%

R209 33_0402_5%
R446 33_0402_5%

SATA_LED#

SATA_RXN0_C
SATA_RXP0_C
SATA_TXN0
SATA_TXP0

CLK_PCIE_SATA#15
CLK_PCIE_SATA15

1 2

+1.5VS

3900P_0402_50V7K
C253
C254

3900P_0402_50V7K

1 2
1 2
1 2
1 2
1 2
1 2

1 2
1 2

1 2
1 2

Within 500 mils

ICH_RTCX1
ICH_RTCX2

ICH_R TCRST#

SM_INTR UDER#

ICH_IN TVRMEN
LAN100_SLP

SATA_TXN0_C
SATA_TXP0_C

CLK_PCIE_SATA#
CLK_PCIE_SATA

R212

1 2

24.9_0402_1%

GLAN_COMP

HDA_BITCLK
HDA _SYNC

HDARST#

ACZ_S DIN0
ACZ_S DIN1

HDA_SDOUT

U7A

AG25

RTCX1

AF24

RTCX2

AF23

RTCRST#

AD22

INTRUDER#

AF25

INTVRMEN

AD21

LAN100_SLP

B24

GLAN_CLK

D22

LAN_RSTSYNC

C21

LAN_RXD0

B21

LAN_RXD1

C22

LAN_RXD2

D21

LAN_TXD0

E20

LAN_TXD1

C20

LAN_TXD2

AH21

GLAN_DOCK#/GPIO13

D25

GLAN_COMPI

C25

GLAN_COMPO

AJ16

HDA_BIT_CLK

AJ15

HDA_SYNC

AE14

HDA_RST#

AJ17

HDA_SDIN0

AH17

HDA_SDIN1

AH15

HDA_SDIN2

AD13

HDA_SDIN3

AE13

HDA_SDOUT

AE10

HDA_DOCK_EN#/GPIO33

AG14

HDA_DOCK_RST#/GPIO34

AF10

SATALED#

AF6

SATA0RXN

AF5

SATA0RXP

AH5

SATA0TXN

AH6

SATA0TXP

AG3

SATA1RXN

AG4

SATA1RXP

AJ4

SATA1TXN

AJ3

SATA1TXP

AF2

SATA2RXN

AF1

SATA2RXP

AE4

SATA2TXN

AE3

SATA2TXP

AB7

SATA_CLKN

AC6

SATA_CLKP

AG1

SATARBIAS#

AG2

SATARBIAS

ICH8M REV 1.0

FWH0/LAD0
FWH1/LAD1
FWH2/LAD2
FWH3/LAD3

FWH4/LFRAME#

LDRQ1#/GPIO23

RTCLAN / GLAN

LPCCPU

A20GATE

DPRSTP#

CPUPWRGD/GPIO49

STPCLK#

THRMTRIP#

IHDA

IDE

SATA

LDRQ0#

A20M#

DPSLP#

FERR#

IGNNE#

INIT#

INTR

RCIN#

SMI#

DD10
DD11
DD12
DD13
DD14
DD15

DCS1#
DCS3#

DIOR#

DIOW#

DDACK#

IDEIRQ

IORDY

DDREQ

NMI

TP8

DD0
DD1
DD2
DD3
DD4
DD5
DD6
DD7
DD8
DD9

DA0
DA1
DA2

E5
F5
G8
F6

C4

G9
E6

AF13
AG26

AF26
AE26

AD24

AG29

AF27

AE24
AC20
AH14

AD23
AG28

AA24

AE27

AA23

V1
U2
V3
T1
V4
T5
AB2
T6
T3
R2
T4
V6
V5
U1
V2
U6

AA4
AA1
AB3

Y6
Y5

W4
W3
Y2
Y3
Y1
W5

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3

LPC_FRAME#

LPC_DR Q0#

GATEA20
H_A20M#

H_DPSLP#
H_FER R#

H_PW RGOOD

H_IGNN E#

H_INIT#
H_INT R
KB_RST#

H_NMI
H_SMI#

H_STPCLK#

THRM TRIP_ICH#

IDE_ HDD0
IDE_ HDD1
IDE_ HDD2
IDE_ HDD3
IDE_ HDD4
IDE_ HDD5
IDE_ HDD6
IDE_ HDD7
IDE_ HDD8
IDE_ HDD9
IDE_H DD10
IDE_H DD11
IDE_H DD12
IDE_H DD13
IDE_H DD14
IDE_H DD15

IDE_H DA0
IDE_H DA1
IDE_H DA2

IDE_H DCS1#
IDE_H DCS3#

IDE_ HDIOR#

IDE_H DIOW#

IDE_H DACK#

IDE _HIRQ

IDE _HIO RDY

IDE_H DREQ

T25 PAD

LPC_A D[0..3] 22,31,32

LPC_FRAME# 22,3 1,32

LPC_DR Q#0 32

GATEA20 32
H_A20M# 4

12

R202 0_0402_5%

H_DPSLP# 5

H_FER R# 4

H_PW RGOOD 5

H_IGNN E# 4

H_INIT# 4
H_INT R 4

KB_RST# 32

H_NMI 4
H_SMI# 4

H_STPCLK# 4

1 2

IDE _HDD[0. .15] 22

IDE_H DA0 22
IDE_H DA1 22
IDE_H DA2 22

IDE_H DCS1# 22
IDE_H DCS3# 22

IDE_H DIOR# 22

IDE_H DIOW# 22

IDE_H DACK# 22

IDE_ HIRQ 22
IDE _HIOR DY 22
IDE_H DREQ 22

H_DPRSTP#H_DPRSTP_R#

R208 24_0402_1%

GATEA20

KB_RST#

H_FER R#

H_DPRSTP#

H_DPSLP#

H_DPRSTP# 5,7 ,39

wit hin 2" fr om R1 557

+VCCP

12

R205

56_0402_5%

H_THERMTRIP# 4,7

pla ced wi thi n 2 " fro m ICH 8M

IDE _HIO RDY
IDE _HIRQ

R210 4.7K_0402_5%
R211 8.2K_0402_5%

10K_0402_5%

10K_0402_5%

1 2
1 2

R191

R195

R197

56_0402_5%

R199

@

56_0402_5%

R201

@

56_0402_5%

+3VS

12

12

+VCCP

12

12

12

+3VS

All tra ce 20mils

R214

+RTCVCC BATT1.1

07/23

W=20m ils

1 2

2

C255
1U_0603_10V4Z

1

CLRP3

A A

5

4

042 0_C han ge RTC b atter y to power part .

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/02/13 2006/03/10

SHORT PAD S

Compal Secret Data

Deciphered Date

1 2

100_0603_1%

2

R213

W=20m ils

1 2

0_0603_5%

RB751V_SOD323

D14

21

@

RB751V_SOD323

D11

+CHGRTC

21

Title

Size Doc ument Number Re v

Cus tom

Date: Sheet of

Compal Electronics, Inc.

ICH8(2/4)_LAN,HD,IDE,LPC

LA-3821P

1

19 43Tues day, July 31, 2007

0.3

5

LINKALERT#

+3VALW

D D

+3VS

+3VS

C C

+3VS

1 2

R215 10K_0402_5%

R216 8.2K_0402_5%

1 2

R219 1K_0402_5%

1 2

R222 10K_0402_5%

1 2

R223 1K_0402_5%

R224 10K_0402_5%

R225 10K_0402_5%

1 2

R228 10K_0402_5%

1 2

R230 10K_0402_5%

1 2

R234 8.2K_0402_5%

1 2

R237 8.2K_0402_5%@

1 2

R238 8.2K_0402_5%

1 2

R239 10K_0402_5%@

1 2

R241 10K_0402_5%@

1 2

R243 10K_0402_5%

1 2

R244 10K_0402_5%

1 2

R245 8.2K_0402_5%

1 2

R248 8.2K_0402_5%

1 2

R252 10K_0402_5% @

SB_SPKR

ICH_LOW_B AT#

12

ICH_P CIE_WAKE#

ICH _RI#

XDP_DBRESET#

ME_EC_DATA1

12

ME_EC_CLK1

12

GPIO38

GPIO39

GPIO22

GPIO20

CLKRU N#

OCP#

MCH _ICH_SYNC #

SIRQ

CLKSATAREQ#

IDE_RESET#

PM_BMBUSY# ICH_R SVD

H_STP_PCI#15
H_STP_CPU#15

+3VS

R226

@

10K_0402_5%

ICH_SMBCLK15,22,23
ICH_SMBDATA15,22,23

R227

@

10K_0402_5%

1 2

1 2

R233 100K_0402_5%

low --> defa ult

Hig h - ->No boot

WLAN ( Mini card)

GIGA LAN

B B

New card

Robeson (Mini card)

USB_OC#3

1 2

R254 10K_0402_5%

USB_OC#4

1 2

R255 10K_0402_5%

USB_OC#5

1 2

R257 10K_0402_5%

USB_OC#6

1 2

R258 10K_0402_5%

USB_OC#7

1 2

R259 10K_0402_5%

1 2

R260 10K_0402_5%

USB_OC#9

1 2

R261 10K_0402_5%

USB_OC#2

1 2

R262 10K_0402_5%

A A

USB_OC#0

1 2

R263 10K_0402_5%

1 2

R265 0_0402_5%

5

+3VALW

USB_OC#1

4

+3VALW

12

R217

2.2K_0402_5%

XDP_DBRESET#4

PM_BMBUSY#7

EC_LID_OUT#32

R229 0_0402_5%

12

PCIE_RXN122
PCIE_RXP122
PCIE_TXN122
PCIE_TXP122

PCIE_RXN224
PCIE_RXP224
PCIE_TXN224
PCIE_TXP224

PCIE_RXN323
PCIE_RXP323
PCIE_TXN323
PCIE_TXP323

PCIE_RXN422
PCIE_RXP422
PCIE_TXN422
PCIE_TXP422

12

ICH_P CIE_WAKE#2 2,23,24

SIRQ32

THERM_SCI#32

VGATE15,39

OCP#4

CPUSB#23,32
EC_SMI#32
EC_SC I#32

CLKSATAREQ#15

IDE_RESET#22

SB_SPKR27

MCH _ICH_SYNC#7

R249 1K_0402_5%@

4

3

12

R218

2.2K_0402_5%

ICH_SMBCLK
ICH_SMBDATA
LINKALERT#
ME_EC_CLK1
ME_EC_DATA1

ICH _RI#

SUS_STAT#

T30P AD

XDP_DBRESET#

PM_BMBUSY#

EC_LID_OUT#

H_STP_PCI#
R_STP_CPU#

CLKRU N# DPRSLPVR

ICH_P CIE_WAKE#
SIRQ
THERM_SCI#

VGATE

SST_CTL

T33P AD

OCP#

CPUSB#
EC_SMI#
EC_SC I#

GPIO20
GPIO22

CLKSATAREQ#

SB_SPKR

MCH _ICH_SYNC #

12

R256

@

USB_OC#029
USB_OC#129
USB_OC#229

GPIO27

GPIO38
GPIO39

IDE_RESET#

+3VALW

1 2

T35P AD

10K_0402_5%

12
12

12
12

12
12

12
12

AD19
AG21
AC17
AE19

AF17

AD15

AG12

AG22

AE20
AG18

AH11

AE17
AF12
AC13

AE16
AC19

AH12
AE11
AG10
AH25
AD16
AG13

AD10

C2600.1U_0402_16V4Z
C2610.1U_0402_16V4Z

C2620.1U_0402_16V4Z
C2630.1U_0402_16V4Z

C4940.1U_0402_16V4Z
C4930.1U_0402_16V4Z

C4960.1U_0402_16V4Z
C4950.1U_0402_16V4Z

T36P AD
T37P AD
T38P AD

T39P AD

AJ26

AJ20

AJ22

AJ11

AJ13

AJ21

USB_OC#0
USB_OC#1USB_OC#8
USB_OC#2
USB_OC#3
USB_OC#4
USB_OC#5
USB_OC#6
USB_OC#7
USB_OC#8
USB_OC#9

U7C

SMBCLK
SMBDATA
LINKALERT#
SMLINK0
SMLINK1

RI#

F4

SUS_STAT#/LPCPD#
SYS_RESET#

BMBUSY#/GPIO0

SMBALERT#/GPIO11

STP_PCI#/GPIO15
STP_CPU#/GPIO25

CLKRUN#/GPIO32

WAKE#
SERIRQ
THRM#

VRMPWRGD

TP7

AJ8

TACH1/GPIO1

AJ9

TACH2/GPIO6

AH9

TACH3/GPIO7
GPIO8
GPIO12

AG8

TACH0/GPIO17
GPIO18
GPIO20
SCLOCK/GPIO22
QRT_STATE0/GPIO27
QRT_STATE1/GPIO28
SATACLKREQ#/GPIO35

AF9

SLOAD/GPIO38
SDATAOUT0/GPIO39
SDATAOUT1/GPIO48

AD9

SPKR

MCH_SYNC#

TP3

ICH8M REV 1.0

PCIE_RXN1
PCIE_RXP1
PCIE_C_TXN1
PCIE_C_TXP1

PCIE_RXN2
PCIE_RXP2
PCIE_C_TXN2
PCIE_C_TXP2

PCIE_RXN3
PCIE_RXP3
PCIE_C_TXN3
PCIE_C_TXP3

PCIE_RXN4
PCIE_RXP4
PCIE_C_TXN4
PCIE_C_TXP4

SPICLK
SPI_CS0#
SPI_CS1#

SPI_MOSI
SPI_MISO

AJ19
AG16
AG15
AE15

AF15
AG17
AD12

AJ18
AD14
AH18

P27
P26
N29
N28

M27
M26

K27
K26

H27
H26
G29
G28

E29
E28

D27
D26
C29
C28

C23
B23
E22

D23

L29
L28

J29
J28

F27
F26

F21

SYS

U7D

PERN1
PERP1
PETN1
PETP1

PERN2
PERP2
PETN2
PETP2

PERN3
PERP3
PETN3
PETP3

PERN4
PERP4
PETN4
PETP4

PERN5
PERP5
PETN5
PETP5

PERN6/GLAN_RXN
PERP6/GLAN_RXP
PETN6/GLAN_TXN
PETP6/GLAN_TXP

SPI_CLK
SPI_CS0#
SPI_CS1#

SPI_MOSI
SPI_MISO

OC0#
OC1#/GPIO40
OC2#/GPIO41
OC3#/GPIO42
OC4#/GPIO43
OC5#/GPIO29
OC6#/GPIO30
OC7#/GPIO31
OC8#
OC9#

ICH8M REV 1.0

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

SATA

GPIO

SMB

Clocks

GPIO

Power MGTController Link

GPIO

ME_EC_ALERT/GPIO10
EC_ME_ALERT/GPIO14

MISC

PCI-Express

SPI

USB

3

SATA0GP/GPIO21
SATA1GP/GPIO19
SATA2GP/GPIO36
SATA3GP/GPIO37

CLK14
CLK48

SUSCLK

SLP_S3#
SLP_S4#
SLP_S5#

S4_STATE#/GPIO26

PWROK

DPRSLPVR/GPIO16

BATLOW#

PWRBTN#

LAN_RST#

RSMRST#

CK_PWRGD

CLPWROK

SLP_M#

CL_CLK0
CL_CLK1

CL_DATA0
CL_DATA1

CL_VREF0
CL_VREF1

CL_RST#

MEM_LED/GPIO24

WOL_EN/GPIO9

V27

DMI0RXN

V26

DMI0RXP

U29

DMI0TXN

U28

DMI0TXP

Y27

DMI1RXN

Y26

DMI1RXP

W29

DMI1TXN

W28

DMI1TXP

AB26

DMI2RXN

AB25

DMI2RXP

AA29

DMI2TXN

AA28

DMI2TXP

AD27

DMI3RXN

AD26

DMI3RXP

AC29

DMI3TXN

AC28

DMI3TXP

T26

DMI_CLKN

T25

DMI_CLKP

Direct Media Interface

USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4N
USBP4P
USBP5N
USBP5P
USBP6N
USBP6P
USBP7N
USBP7P
USBP8N
USBP8P
USBP9N
USBP9P

USBRBIAS#

USBRBIAS

Y23
Y24

G3
G2
H5
H4
H2
H1
J3
J2
K5
K4
K2
K1
L3
L2
M5
M4
M2
M1
N3
N2

F2
F3

DMI_ZCOMP

DMI_IRCOMP

2006/02/13 2006/03/10

AJ12
AJ10
AF11
AG11

CLK_14M_ICH

AG9

CLK_48M_ICH

G5

ICH_S USCLK

D3

SLP_S3#

AG23

SLP_S4#

AF21

SLP_S5#

AD18

S4_STATE#

AH27

PM_PWROK

AE23

AJ14

ICH_LOW_B AT#

AE21

PWRBTN_OUT#

C2

AH20

EC_RMRST#

AG27

CK_PW RGD

E1

M_PWROK

E3

PM_SLP_M#

AJ25

CL_CLK0

F23
AE18

CL_DATA0

F22
AF19

CL_VR EF0_ICH

D24

CL_VR EF1_ICH

AH23

AJ23

AJ27
AJ24
AF22
AG19

12

R251

100K_0402_5%

DMI_RXN0
DMI_RXP0
DMI_TXN0
DMI_TXP0

DMI_RXN1
DMI_RXP1
DMI_TXN1
DMI_TXP1

DMI_RXN2
DMI_RXP2
DMI_TXN2
DMI_TXP2

DMI_RXN3
DMI_RXP3
DMI_TXN3
DMI_TXP3

CLK_P CIE_ICH#
CLK_P CIE_ICH

DMI_IRCOM P

USB20_N0
USB20_P0
USB20_N1
USB20_P1
USB20_N2
USB20_P2
USB20_N3
USB20_P3
USB20_N4
USB20_P4
USB20_N5
USB20_P5
USB20_N6
USB20_P6
USB20_N7
USB20_P7

USBR BIAS

Within 500 mi ls

Compal Secret Data

Deciphered Date

T26 PA D
T27 PA D
T28 PA D
T29 PA D

T31 PA D

T32 PA D

R235

1 2

0_0402_5%

1 2

100_0402_5%

T34 PA D

DMI_RXN0 7
DMI_RXP0 7
DMI_TXN0 7
DMI_TXP0 7

DMI_RXP1 7
DMI_TXN1 7
DMI_TXP1 7

DMI_RXN2 7
DMI_RXP2 7
DMI_TXN2 7
DMI_TXP2 7

DMI_RXN3 7
DMI_RXP3 7
DMI_TXN3 7
DMI_TXP3 7

CLK_P CIE_ICH# 15
CLK_P CIE_ICH 15

R253 24.9_0402_1%

1 2

1 2

R264 22.6_0402_1%

2

CLK_14M _ICH 15
CLK_48M _ICH 15

SLP_S3# 32
SLP_S4# 32
SLP_S5# 32

PM_PWROK 7,32

1 2

R231 100K_0402_5%@

PWRBTN_OUT# 32

R236

CK_PW RGD 15

M_PWROK 7,32

CL_CLK0 7

CL_DATA0 7

CL_RST# 7

DMI_RXN1 7

USB20_N0 29
USB20_P0 29
USB20_N1 29
USB20_P1 29
USB20_N2 29
USB20_P2 29
USB20_N3 23
USB20_P3 23

USB20_N4 26

USB20_P4 26

USB20_N5 29

USB20_P5 29

USB20_N6 29

USB20_P6 29

USB20_N7 29

USB20_P7 29

2

DPRSLPVR 7,39

EC_RSMRST#

Within 500 mi ls

+1.5VS

To Ne w Card

To C ard reade r/B.

To Bl uetooth

To PC Camera

To F inger Pri nter

1

Pla ce cl ose ly pin AG9Pla ce cl ose ly pin G5

12

R220

10_0402_5%@

1

C256

4.7P_0402_50V8C@

2

12

R221

1

C257

2

0205 Cha nge to conne ct to GND.

EC_RSMRST# 32

R240 3.24K_0402_1%

1 2

12

1

C258

R242

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

12

1

C259

2

Title

Size Doc ument Number Re v

Cus tom

LA-3821P

Date: Sheet of

+3VS

453_0402_1%

R246 3.24K_0402_1%

1 2

R250
453_0402_1%

+3VALW

Compal Electronics, Inc.

ICH8(3/4)_PM,USB,GPIO

1

CLK_14M_ICHCLK_48M_ICH

10_0402_5%@

4.7P_0402_50V8C@

0.3

20 43Tues day, July 31, 2007

5

D D

R268

100_0402_5%

R269

C C

10_0402_5%

+1.5VS

B B

0.1U_0402_16V4Z

A A

+1.5VS

+5VS +3VS

12

D12

CH751H-40PT_S OD323-2

+3VALW+5VALW

12

D13

CH751H-40PT_S OD323-2

1 2

CHB1608U301_ 0603

C297

R266 CHB 1608U301_0603

1 2

21

20 mils

ICH_V 5REF_RU N

1

C274

0.1U_0402_16V4Z

2

21

ICH_V 5REF_SUS

20 mils

1

C281

0.1U_0402_16V4Z

2

R270

C286

+1.5VS

C294

0.1U_0402_16V4Z

+3VS

1

+1.5VS

2

5

+RTCVCC

1

C264

2

0.1U_0402_16V4Z

40 mils

1

+

C269

C268

2

1U_0603_10V4Z

1

2

C287

C298

10U_0805_10V4Z

1

2

10U_0805_10V4Z

+1.5VS

0.1U_0402_16V4Z

1

C299

2

10U_0805_10V4Z

220U_D2_2.5VM

1

2

R271 CHB 1608U301_0603

1 2

20 mils

1

C265

2

0.1U_0402_16V4Z

10U_0805_10V4Z

1

1

C270

2

2

ICH_VCC SATAPLL

1U_0603_10V4Z

+1.5VS

1U_0603_10V4Z

1

C295

2

T44
T45

ICH_V CCGLANPLL

1

+1.5VS

2

4.7U_0805_10V4Z

+3VS

2.2U_0805_16V4Z

ICH_V 5REF_RU N

ICH_V 5REF_SUS

ICH_V CC1_5

1

C271

2

2.2U_0805_16V4Z

VCC1_5_A=1120mA

+1.5VS

1

C288

2

VCC1_5_A=1120mA

1

C290

2

VCC1_5_A=1120mA

VCC1_5_A=1120mA

+1.5VS

VCC_L AN1_05_INT_ICH_1
VCC_L AN1_05_INT_ICH_2

R272

@

ICH_V CCGLAN1_5

1 2

CHB1608U301_ 0603

1

C300

@

2

ICH_V CCGLAN3_3

1 2

R2730_0402_5%@

770mA

50mA

10mA

12mA

27mA

74mA

1mA

6mA

3mA

AD25

AA25
AA26
AA27
AB27
AB28
AB29

W25

AC10

W23

D28
D29

G24
H23
H24

M24
M25
N23
N24
N25

R24
R25
R26
R27

U24
U25

AE7
AF7
AG7
AH7

AC1
AC2
AC3
AC4
AC5

AC9

AA5
AA6

G12
G17

AC7
AD7

G18

G20

A16

T7

G4

E25
E26
E27
F24
F25

J23

J24
K24
K25
L23
L24
L25

P24
P25

T23
T24
T27
T28
T29

V23
V24
V25

Y25

AJ6

AJ7

H7

D1

F1
L6

L7
M6
M7

F17

F19

A24

A26
A27
B26
B27
B28

B25

4

U7F

VCCRTC

V5REF[1]
V5REF[2]

V5REF_SUS

VCC1_5_B[01]
VCC1_5_B[02]
VCC1_5_B[03]
VCC1_5_B[04]
VCC1_5_B[05]
VCC1_5_B[06]
VCC1_5_B[07]
VCC1_5_B[08]
VCC1_5_B[09]
VCC1_5_B[10]
VCC1_5_B[11]
VCC1_5_B[12]
VCC1_5_B[13]
VCC1_5_B[14]
VCC1_5_B[15]
VCC1_5_B[16]
VCC1_5_B[17]
VCC1_5_B[18]
VCC1_5_B[19]
VCC1_5_B[20]
VCC1_5_B[21]
VCC1_5_B[22]
VCC1_5_B[23]
VCC1_5_B[24]
VCC1_5_B[25]
VCC1_5_B[26]
VCC1_5_B[27]
VCC1_5_B[28]
VCC1_5_B[29]
VCC1_5_B[30]
VCC1_5_B[31]
VCC1_5_B[32]
VCC1_5_B[33]
VCC1_5_B[34]
VCC1_5_B[35]
VCC1_5_B[36]
VCC1_5_B[37]
VCC1_5_B[38]
VCC1_5_B[39]
VCC1_5_B[40]
VCC1_5_B[41]
VCC1_5_B[42]
VCC1_5_B[43]
VCC1_5_B[44]
VCC1_5_B[45]
VCC1_5_B[46]

VCCSATAPLL

VCC1_5_A[01]
VCC1_5_A[02]
VCC1_5_A[03]
VCC1_5_A[04]
VCC1_5_A[05]

VCC1_5_A[06]
VCC1_5_A[07]
VCC1_5_A[08]
VCC1_5_A[09]
VCC1_5_A[10]

VCC1_5_A[11]
VCC1_5_A[12]

VCC1_5_A[13]
VCC1_5_A[14]

VCC1_5_A[15]
VCC1_5_A[16]
VCC1_5_A[17]

VCC1_5_A[18]
VCC1_5_A[19]

VCCUSBPLL

VCC1_5_A[20]
VCC1_5_A[21]
VCC1_5_A[22]
VCC1_5_A[23]
VCC1_5_A[24]

VCC1_5_A[25]

VCCLAN1_05[1]
VCCLAN1_05[2]

VCCLAN3_3[1]
VCCLAN3_3[2]

VCCGLANPLL

VCCGLAN1_5[1]
VCCGLAN1_5[2]
VCCGLAN1_5[3]
VCCGLAN1_5[4]
VCCGLAN1_5[5]

VCCGLAN3_3

ICH8M REV 1.0

4

VCC1_05[01]
VCC1_05[02]
VCC1_05[03]
VCC1_05[04]
VCC1_05[05]
VCC1_05[06]
VCC1_05[07]
VCC1_05[08]
VCC1_05[09]
VCC1_05[10]
VCC1_05[11]
VCC1_05[12]
VCC1_05[13]
VCC1_05[14]
VCC1_05[15]
VCC1_05[16]

CORE

VCC1_05[17]
VCC1_05[18]
VCC1_05[19]
VCC1_05[20]
VCC1_05[21]
VCC1_05[22]
VCC1_05[23]
VCC1_05[24]
VCC1_05[25]
VCC1_05[26]
VCC1_05[27]
VCC1_05[28]

VCCA3 GP ATXA RX

V_CPU_IO[1]
V_CPU_IO[2]

VCCP_ COREVCCPS USVCCPUSB

IDE

PCI

VCCSUSHDA

VCCSUS1_05[1]
VCCSUS1_05[2]

VCCSUS1_5[1]

VCCSUS1_5[2]

VCCSUS3_3[01]

VCCSUS3_3[02]
VCCSUS3_3[03]
VCCSUS3_3[04]
VCCSUS3_3[05]

USB C ORE

VCCSUS3_3[06]

VCCSUS3_3[07]
VCCSUS3_3[08]
VCCSUS3_3[09]
VCCSUS3_3[10]
VCCSUS3_3[11]
VCCSUS3_3[12]
VCCSUS3_3[13]
VCCSUS3_3[14]
VCCSUS3_3[15]
VCCSUS3_3[16]
VCCSUS3_3[17]
VCCSUS3_3[18]
VCCSUS3_3[19]

GLAN POWER

VCCCL3_3[1]
VCCCL3_3[2]

VCCDMIPLL

VCC_DMI[1]
VCC_DMI[2]

VCC3_3[01]

VCC3_3[02]

VCC3_3[03]
VCC3_3[04]
VCC3_3[05]
VCC3_3[06]

VCC3_3[07]
VCC3_3[08]
VCC3_3[09]
VCC3_3[10]
VCC3_3[11]
VCC3_3[12]
VCC3_3[13]

VCC3_3[14]
VCC3_3[15]
VCC3_3[16]
VCC3_3[17]
VCC3_3[18]
VCC3_3[19]
VCC3_3[20]
VCC3_3[21]
VCC3_3[22]
VCC3_3[23]
VCC3_3[24]

VCCHDA

VCCCL1_05

VCCCL1_5

3

+VCCP

1170mA

A13
B13
C13
C14
D14
E14
F14
G14
L11
L12
L14
L16
L17
L18
M11
M18
P11
P18
T11
T18
U11
U18
V11
V12
V14
V16
V17
V18

R29

AE28
AE29

AC23
AC24

AF29

AD2

AC8
AD8
AE8
AF8

VCC3_3=310mA

AA3
U7
V7
W1
W6
W7
Y7

VCC3_3=310mA

A8
B15
B18
B4
B9
C15
D13
D5
E10
E7
F11

AC12

AD11

J6
AF20

VCCS US1_5_ICH_1

AC16

VCCS US1_5_ICH_2

J7

0.1U_0402_16V4Z

C3

AC18
AC21
AC22
AG20
AH28

P6
P7
C1
N7
P1
P2
P3
P4
P5
R1
R3
R5
R6

VCCC L1_05_ICH

G22

A22

12mA

F20
G21

0.1U_0402_16V4Z

1

C267 0.1U _0402_16V4Z

2

ICH_V CCDMIPLL

1

C272

2

0.01U_0402_16V7K

0.1U_0402_16V4Z

+3VS

1

2

0.1U_0402_16V4Z

1

1

C283

C284

2

2

0.1U_0402_16V4Z

C291

+3VALW

1

C292

2

+3VALW

VCCSUS3_3=141mA

1

C296

4.7U_0805_10V4Z

2

T46

C301

@

3

1

2

R267 CHB 1608U301_0603

1 2

1

C273

2

10U_0805_10V4Z

+1.25VS

10U_0805_10V4Z

C275

1

2

0.1U_0402_16V4Z

+3VS

(SA TA)

1

C280

2

+3VS

1

C285

2

0.1U_0402_16V4Z

+3VALW

1

2

VCCSUS3_3=141mA

0.1U_0402_16V4Z

1

C293

2

2006/02/13 2006/03/10

+1.5VS

+3VS

(DM I)

1

C279

2

1

C289

2

Compal Secret Data

+VCCP

4.7U_0805_10V4Z

+3VS

Deciphered Date

0.1U_0402_16V4Z

C276

1

2

C277

1

2

C266

26mA

40mA

14mA

VCC3_3=310mA

VCC3_3=310mA

VCC3_3=310mA

C282

+3VS

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

24mA

4mA

T40
T41

T42

T43

1U_0603_10V4Z

+3VS

1

2

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2

0.1U_0402_16V4Z

C278

1

2

2

U7E

A23

VSS[001]

A5

VSS[002]

AA2

VSS[003]

AA7

VSS[004]

A25

VSS[005]

AB1

VSS[006]

AB24

VSS[007]

AC11

VSS[008]

AC14

VSS[009]

AC25

VSS[010]

AC26

VSS[011]

AC27

VSS[012]

AD17

VSS[013]

AD20

VSS[014]

AD28

VSS[015]

AD29

VSS[016]

AD3

VSS[017]

AD4

VSS[018]

AD6

VSS[019]

AE1

VSS[020]

AE12

VSS[021]

AE2

VSS[022]

AE22

VSS[023]

AD1

VSS[024]

AE25

VSS[025]

AE5

VSS[026]

AE6

VSS[027]

AE9

VSS[028]

AF14

VSS[029]

AF16

VSS[030]

AF18

VSS[031]

AF3

VSS[032]

AF4

VSS[033]

AG5

VSS[034]

AG6

VSS[035]

AH10

VSS[036]

AH13

VSS[037]

AH16

VSS[038]

AH19

VSS[039]

AH2

VSS[040]

AF28

VSS[041]

AH22

VSS[042]

AH24

VSS[043]

AH26

VSS[044]

AH3

VSS[045]

AH4

VSS[046]

AH8

VSS[047]

AJ5

VSS[048]

B11

VSS[049]

B14

VSS[050]

B17

VSS[051]

B2

VSS[052]

B20

VSS[053]

B22

VSS[054]

B8

VSS[055]

C24

VSS[056]

C26

VSS[057]

C27

VSS[058]

C6

VSS[059]

D12

VSS[060]

D15

VSS[061]

D18

VSS[062]

D2

VSS[063]

D4

VSS[064]

E21

VSS[065]

E24

VSS[066]

E4

VSS[067]

E9

VSS[068]

F15

VSS[069]

E23

VSS[070]

F28

VSS[071]

F29

VSS[072]

F7

VSS[073]

G1

VSS[074]

E2

VSS[075]

G10

VSS[076]

G13

VSS[077]

G19

VSS[078]

G23

VSS[079]

G25

VSS[080]

G26

VSS[081]

G27

VSS[082]

H25

VSS[083]

H28

VSS[084]

H29

VSS[085]

H3

VSS[086]

H6

VSS[087]

J1

VSS[088]

J25

VSS[089]

J26

VSS[090]

J27

VSS[091]

J4

VSS[092]

J5

VSS[093]

K23

VSS[094]

K28

VSS[095]

K29

VSS[096]

K3

VSS[097]

K6

VSS[098]

ICH8M REV 1.0

Title

Size Doc ument Number Re v

Cus tom

LA-3821P

Date: Sheet of

VSS_NCTF[01]
VSS_NCTF[02]
VSS_NCTF[03]
VSS_NCTF[04]
VSS_NCTF[05]
VSS_NCTF[06]
VSS_NCTF[07]
VSS_NCTF[08]
VSS_NCTF[09]
VSS_NCTF[10]
VSS_NCTF[11]
VSS_NCTF[12]

Compal Electronics, Inc.

ICH8(4/4)_POWER&GND

VSS[099]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
VSS[159]
VSS[160]
VSS[161]
VSS[162]
VSS[163]
VSS[164]
VSS[165]
VSS[166]
VSS[167]
VSS[168]
VSS[169]
VSS[170]
VSS[171]
VSS[172]
VSS[173]
VSS[174]
VSS[175]
VSS[176]
VSS[177]
VSS[178]
VSS[179]
VSS[180]
VSS[181]
VSS[182]
VSS[183]
VSS[184]

1

K7
L1
L13
L15
L26
L27
L4
L5
M12
M13
M14
M15
M16
M17
M23
M28
M29
M3
N1
N11
N12
N13
N14
N15
N16
N17
N18
N26
N27
N4
N5
N6
P12
P13
P14
P15
P16
P17
P23
P28
P29
R11
R12
R13
R14
R15
R16
R17
R18
R28
R4
T12
T13
T14
T15
T16
T17
T2
U12
U13
U14
U15
U16
U17
U23
U26
U27
U3
U5
V13
V15
V28
V29
W2
W26
W27
Y28
Y29
Y4
AB4
AB23
AB5
AB6
AD5
U4
W24

A1
A2
A28
A29
AH1
AH29
AJ1
AJ2
AJ28
AJ29
B1
B29

1

21 43Tues day, July 31, 2007

0.3

A

B

C

D

E

F

G

+5VS

H

Pl acea cap s. near O DD CO NN.

HDD Connector CD-ROM Connector

IDE _HDD[0. .15] 19

R274 0_0402_5%@

1 2

R275 33_0402_5%

1 2

IDE_H DIOW#19
IDE _HIOR DY19

IDE_ HIRQ19
IDE_H DA119
IDE_H DA019

IDE_H DCS1#19

12

R278 10K_0402_5%

+5VS

IDE_ HDD7
IDE_ HDD6
IDE_ HDD5
IDE_ HDD4
IDE_ HDD3
IDE_ HDD2
IDE_ HDD1
IDE_ HDD0

IDE_H DIOW#

IDE _HIO RDY

IDE _HIRQ
IDE_H DA1
IDE_H DA0
IDE_H DCS1#
IDE_ACT#

SEC_CSEL

12

R279
470_0402_5%

JP9

1 2
3 4
5 6
7 8
9 10
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
29 30
31 32
33 34
35 36
37 38
39 40
41 42
43 44
45 46
47 48
49 50

SUYIN_8 00189MB050S105ZL

CONN@

+5VS

C307

10U_0805_10V4Z

1

2

0.1U_0402_16V4Z

1

1

C308

C309

2

2

0.1U_0402_16V4Z

1

C310

2

0.1U_0402_16V4Z

1 1

Plea ce nea r HD CONN (J P23)

+3VS +3VS_HDD

R2770_0805_5%@

12

0.1U_0402_16V4Z

1

1

C313

@

C314

@

2

2

1000P_0402_50V7K

1U_0603_10V4Z

Plea ce near H D CONN

2 2

1

1

+

C315

@

@

2

2

C312

330U_V_2.5VK_R9

SUYIN_1 27043FR0 22G204ZL_NR

GND

GND

GND

GND
GND
GND

GND

Reserved

GND

JP8

1
2

A+

3

A-

B-

B+

V33
V33
V33

V5
V5
V5

V12
V12
V12

4
5
6
7

8
9
10
11
12
13
14
15
16
17
18
19
20
21
22

0.01U_0402_16V7K

SATA_RXN0

SATA_RXP0

0.01U_0402_16V7K

Near CONN side.

+3VS_HDD

+5VS

12
12

SATA_TXP0
SATA_TXN0

SATA_RXN0_C

C306
C311

SATA_RXP0_C

SATA_TXP0 19

SATA_TXN0 19

SATA_RXN0_C 19

SATA_RXP0_C 19

IDE_RESET#20

PLT_RST#7,18,23,24

+5VS

0213 _Chang e Connector type.

IDE_ HDD8
IDE_ HDD9
IDE_H DD10
IDE_H DD11
IDE_H DD12
IDE_H DD13
IDE_H DD14
IDE_H DD15
IDE_H DREQ
IDE_ HDIOR#

IDE_H DACK#

PDIAG#
IDE_H DA2
IDE_H DCS3#

IDE_H DREQ 19

IDE_H DIOR# 19

IDE_H DACK# 19

R276 100K_0402_5%

1 2

IDE_H DA2 19

IDE_H DCS3# 19

+5VS

+5VS

0.1U_0402_16V4Z

C302

1

C303

2

10U_0805_10V4Z

1U_0603_10V4Z

1

1

C304

2

1

C305
10U_0805_10V4Z

2

2

Mini-Express Card---WLAN

+3VS_MINI +1.5VS_MINI

+3VALW

NAND mini Card(Robson support)

C316

Add i n 4/27.

JP10

1

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51

GND1

GND2

2
4
6

8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

3
5

MINI_R OB_CLKREQ#15

CLK_P CIE_MCARD_ROB#15
CLK_P CIE_MCARD_ROB15

R280 0_0402_5%

PCIE_RXN420

3 3

PCIE_RXP420

PCIE_TXN420
PCIE_TXP420

1 2

R281 0_0402_5%

1 2

PCIE_C_RXN 4
PCIE_C_RXP4

Add in 5/1 6. (Close to JP10)

+3VS +3VS +1.5VS

1

1

1

C323

C324

2

0.01U_0402_16V7K

C325

2

2

0.01U_0402_16V7K

0.01U_0402_16V7K

1

1

C326

2

0.1U_0402_16V4Z

1

C327

C328

2

2

4.7U_0805_10V4Z

0.01U_0402_16V7K

1

1

C330

C329

2

2

4.7U_0805_10V4Z

0.1U_0402_16V4Z

7

9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51

53

FOX_AS0B226-S40N-7F

CONN@

+3VS +1.5VS

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

54

PLT_RST#

0.01U_0402_16V7K

ICH_P CIE_WAKE#20 ,23,24

MINI_C LKREQ#15

CLK_P CIE_MCARD#15

CLK_P CIE_MCARD15

CLK_DEBU G_PORT_015

Mini Card STANDOFF

H4

H3

HOLEA

HOLEA

4 4

1

1

1

0.1U_0402_16V4Z

2

CH_DATA29

CH_CL K29

PCIE_RXN120
PCIE_RXP120

PCIE_TXN120
PCIE_TXP120

Mini Card STANDOFF

H1
HOLEA

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

C

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

D

C317

1 2

R282 0_0402_5%

CLK_P CIE_MCARD#
CLK_P CIE_MCARD

PLT_RST#

PCIE_RXP1

PCIE_TXN1
PCIE_TXP1

H2
HOLEA

1

1

2

4.7U_0805_10V4Z

ICH_P CIE_WAKE#
CH_DATA
CH_CL K

R288 0_0402_5% DEBUG@

R289 0_0402_5%

1 2
1 2

R290 0_0402_5%

1

2006/02/13 2007/08/29

C318

MINI_C LKREQ#_MC

1 2

PCIE_C_RXN 1PCIE_RXN1
PCIE_C_RXP1

E

1

0.01U_0402_16V7K

2

Compal Secret Data

1

C319

0.1U_0402_16V4Z

2

JP11

1

1

3

3

5

5

7

7

9

9

11

11

13

13

15

15

17

17

19

19

21

21

23

23

25

25

27

27

29

29

31

31

33

33

35

35

37

37

39

39

41

41

43

43

45

45

47

47

49

49

51

51

53

GND1

GND2

FOX_AS0B226-S40N-7F

CONN@

Deciphered Date

2
4
6

8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

F

1

C320

2

+1.5VS_MINI

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

54

1

C321

4.7U_0805_10V4Z

2

+3VS_MINI

FBMA-L11-201209-102LMA10T

1 2

L10 FBMA-L11-201209-102LMA10T

R283 0_0402_5% DEBUG@

1 2

R284 0_0402_5% DEBUG@

1 2

R285 0_0402_5% DEBUG@

1 2

R286 0_0402_5% DEBUG@

1 2

R287 0_0402_5% DEBUG@

1 2

WL_ON#
PLT_RST#

WL_LED#

0.1U_0402_16V4Z@

L9

1 2

+3VALW

Title

Size Doc ument Number Re v

Date: Sheet of

1

C322

2

+3VS

+1.5VS

WL_ON# 32

ICH_SMBCLK 1 5,20,23
ICH_SMBDATA 15, 20,23

WL_LED# 30

LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0

Compal Electronics, Inc.

HDD/ODD/Mini Card CONN.

LA-3821P

G

LPC_FRAME# 19 ,31,32

LPC_ AD[0..3] 19,31,32

22 43Tues day, July 31, 2007

H

0.3

A

B

C

D

E

Express Card Power Switch

C331

0.1U_0402_16V4Z

1 1

+3VS

G

2

13

D

USB20_N32 0
USB20_P320

+1.5VS_PEC
+1.5VS_PEC

S

Q10
2N7002_SOT23-3

USB20_N3
USB20_P3
CPUSB#

ICH_SMBCLK
ICH_SMBDATA

ICH_P CIE_WAKE#

PERST#

CLKRE QD#
CPUSB#
CLK_P CIE_NC2#
CLK_P CIE_NC2

PCIE_RXN3
PCIE_RXP3

PCIE_TXN3
PCIE_TXP3

PLT_RST#7,18,22,24

2 2

ICH_SMBCLK15,20,22
ICH_SMBDATA15,20,22

ICH_P CIE_WAKE#20 ,22,24

+3V_PEC

+3VS_PEC

NCAR D_CLKREQ#15

CLK_P CIE_NCARD#15

CLK_P CIE_NCARD15

PCIE_RXN320

3 3

PCIE_RXP320

PCIE_TXN320
PCIE_TXP320

0.1U_0402_16V4Z

0.1U_0402_16V4Z

+3VALW

CPUSB#20,32

SUSP#32,33,35,37,38
SYSO N32,33,37

C332

C333

12

12

12

+3VALW

+1.5VS

R291 100K_0402_5%

+3VS

12

SUSP#
SYS ON
PLTRST#

JP12

1

GND

2

USB_D-

3

USB_D+

4

CPUSB#

5

RSV

6

RSV

7

SMB_CLK

8

SMB_DATA

9

+1.5V

10

+1.5V

11

WAKE#

12

+3.3VAUX

13

PERST#

14

+3.3V

15

+3.3V

16

CLKREQ#

17

CPPE#

18

REFCLK-

19

REFCLK+

20

GND

21

PERn0

22

PERp0

23

GND

24

PETn0

25

PETp0

26

GND

27

GND1

28

GND2

SANTA_131851-A_LT

CONN@

U8

5

3.3Vin1

6

3.3Vin2

21

3.3Vaux_in

18

1.5Vin1

19

1.5Vin2

14

CPUSB#

15

CPPE#

4

STBY#
SHDN#3RCLKEN

2

SYSRST#

GND

11

29

GND3

30

GND4

NC11NC210NC312NC413NC5

3.3Vout1

3.3Vout2

1.5Vout1

1.5Vout2

PERST#

24

7
8

20

Aux_out

16
17

23

OC#

22
9

TPS2231PWPR_PWP24

+3VS_PEC

+3V_PEC

+1.5VS_PEC

PERST#

C334

0.1U_0402_16V4Z

C338

0.1U_0402_16V4Z

Near to Express Card slot. 15.4

+3VS_PEC

4.7U_0805_10V4Z

1

2

+1.5VS_PEC

1

2

1

C335

2

4.7U_0805_10V4Z

1

C339

2

0.1U_0402_16V4Z

C336

+3V_PEC

1

2

1

C337

4.7U_0805_10V4Z

2

4 4

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2005/03/10 2006/03/10

Compal Secret Data

Deciphered Date

Title

Size Doc ument Number Re v

Cus tom

D

Date: Sheet of

Compal Electronics, Inc.

Express Card

LA-3821P

E

23 43Tues day, July 31, 2007

0.3

5

+3V_LAN

R295 10K_0402_5%

R296 10K_0402_5%

R297 10K_0402_5%

D D

C C

12

12

12

ICH_P CIE_WAKE#20 ,22,23

CLK_P CIE_LAN15

CLK_P CIE_LAN#15

GIGA_LA N_CLKREQ

ICH_P CIE_WAKE#

LAN_LOM_DIS

PCIE_RXP220
PCIE_RXN220
PCIE_TXP220
PCIE_TXN220

PLT_RST#7,18,22,23

LAN_MDI0P25

LAN_MDI0N25

LAN_MDI1P25

LAN_MDI1N25

LAN_MDI2P25

LAN_MDI2N25

LAN_MDI3P25

LAN_MDI3N25

ICH_P CIE_WAKE#

+3VS

GIGA_LA N_CLKREQ

R298 0_0402_5%

1 2

+3V_LAN

R299 4.87K_0402_1%

C3410 .1U_0402_16V4Z

12

C3470 .1U_0402_16V4Z

12

LAN_EE_CLK
LAN_EE_DATA

LAN_LOM_DIS

CTRL18
CTRL12

4

PCIE_RXP2_LAN
PCIE_RXN2_LA N

LAN_X1
LAN_X2

C340

12

0.1U_0402_16V4Z

U9

1

A0

VCC

2

A1

WP

3

NC

SCL

4

GND

SDA

CAT24 C08WI-GT3 SO 8P

U10

42

CLKREQn

49

TX_P

50

TX_N

54

RX_P

53

RX_N

6

WAKEn

55

REFCLKP

56

REFCLKN

5

PERSTn

17

MDIP0

18

MDIN0

20

MDIP1

21

MDIN1

26

MDIP2

27

MDIN2

30

MDIP3

31

MDIN3

38

VPD_CLK

41

VPD_DATA

34

SPI_DO

35

SPI_DI

37

SPI_CLK

36

SPI_CS

15

XTALI

14

XTALO

10

LOM_DISABLEn

12

VAUX_AVLBL

11

SWITCH_VCC

47

VMAIN_AVLBL

9

SWITCH_VAUX

16

RSET

4

CTRL18

3

CTRL12

88E8055_QFN64

8
7
6
5

PCI-E

Media

EEPROM

FLASH

MEMORY

CLOCK

Analog

LAN_EE_CLK
LAN_EE_DATA

+3V_LAN

12

R293

R294

1K_0402_5%

LED

LED_ACTn

LED_LINK10/100n

LED_LINK1000n

LED_DUPLEXn

TESTMODE

TEST

POWER

&

GROUND

VDDO_TTL
VDDO_TTL
VDDO_TTL
VDDO_TTL

No Connect

12

1K_0402_5%

AVDDH

AVDD
AVDD
AVDD
AVDD

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

Reserved
Reserved
Reserved
Reserved

VSS

NC
NC
NC
NC
NC

3

59
60
62
63

46

8

19
22
23
28

1
40
45
61

2
7
13
33
39
44
48
58
65

32
51
52
57
64

24
25
29
43

LAN_ACT#

LANLINK_STATUS#

+3V_LAN

V1.8_LAN

+3V_LAN

V1.2_LAN

V1.8_LAN

1

C501

2

LAN_ACT# 25

LANLINK_STATUS# 25

0.1U_0402_16V4Z

1

C500

0.1U_0402_16V4Z

2

LAN_P OWER_OFF32

1

C491

0.1U_0402_16V4Z

2

1

C490

0.1U_0402_16V4Z

2

2

1

C342

0.1U_0402_16V4Z

2

1

C348

0.1U_0402_16V4Z

2

1

C353

0.1U_0402_16V4Z

2

R359
0_1206_5% @

1 2

Q22AP2305GN

1 3

D

2

+3VALW+3V_LAN

S

G

1

C343

0.1U_0402_16V4Z

2

1

C349

0.1U_0402_16V4Z

2

1

C354

0.1U_0402_16V4Z

2

1

C414

0.1U_0402_16V4Z

2

1

C344

0.1U_0402_16V4Z

2

1

C350

0.1U_0402_16V4Z

2

1

C355

0.1U_0402_16V4Z

2

1

C404

0.1U_0402_16V4Z

2

1

Turn off p ower when S3 . 06/14

+3V_LAN

1

C345

0.1U_0402_16V4Z

2

1

C351

0.1U_0402_16V4Z

2

1

C356

0.1U_0402_16V4Z

2

1

C405

0.1U_0402_16V4Z

2

1

2

V1.8_LAN

1

2

V1.2_LAN

1

2

V1.2_LAN

1

2

C346

0.1U_0402_16V4Z

C352

0.1U_0402_16V4Z

C357

0.1U_0402_16V4Z

C403

0.1U_0402_16V4Z

+3V_LAN

C3584.7U_0805_10V4Z

R435 4.7K_0402_5%

12

B B

2SB1188T100R_SC62-3

V1.2_LAN

2SB1188T100R_SC62-3

V1.8_LAN

A A

5

2 3

C3614.7U_0805_10V4Z

12

+3V_LAN

C3624.7U_0805_10V4Z

12

2 3

C3634.7U_0805_10V4Z

12

12

Q11

1

R436 4.7K_0402_5%

12

Q12

1

CTRL12

CTRL18

LAN_X1
LAN_X2

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/02/13 2007/08/29

1 2

Compal Secret Data

C359 27P_0402_50V8J

1 2

Y3
25MHZ_20P_1BG25000CK1A

C360 27P_0402_50V8J

1 2

Deciphered Date

Title

Size Doc ument Number Re v

2

Date: Sheet

Compal Electronics, Inc.

LAN-8100CL

LA-3821P

1

0.3

of

24 43Tues day, July 31, 2007

5

D D

C3640.1U_0402_16V4Z

1 2

1 2

1 2

1 2

C C

R300 49.9_0402_1%

R302 49.9_0402_1%

R303 49.9_0402_1%

C3670.1U_0402_16V4Z

R305 49.9_0402_1%

R306 49.9_0402_1%

C3710.1U_0402_16V4Z

R308 49.9_0402_1%

C3740.1U_0402_16V4Z

R309 49.9_0402_1%

R311 49.9_0402_1%

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

4

LAN_MDI0N 24

LAN_MDI0P 24

LAN_MDI1N 24

LAN_MDI1P 24

LAN_MDI2N 24

LAN_MDI2P 24

LAN_MDI3N 24

LAN_MDI3P 24

3

V1.8_LAN

12

C365

0.1U_0402_16V4Z

12

C368

0.1U_0402_16V4Z

12

C372

0.1U_0402_16V4Z

12

C375

0.1U_0402_16V4Z

TRM_CT
LAN_MDI3P
LAN_M DI3N

TRM_CT
LAN_MDI2P
LAN_M DI2N

TRM_CT
LAN_MDI1P
LAN_M DI1N

TRM_CT
LAN_MDI0P
LAN_M DI0N

T47

1

TCT1

2

TD1+

3

TD1-

4

TCT2

5

TD2+
TD2-6MX2-

7

TCT3

8

TD3+

9

TD3-

10

TCT4

11

TD4+

12

TD4-

0.5u_24HST1041A-2

MCT1
MX1+

MX1-

MCT2
MX2+

MCT3
MX3+

MX3-

MCT4
MX4+

MX4-

2

MDO3+
MDO3-

MDO2+
MDO2-

MDO1+
MDO1-

MDO0+
MDO0-

R301

75_0402_1%

R304

75_0402_1%

R307

75_0402_1%

R310

75_0402_1%

12

12

12

C369

12

1 2

1000P_1808_3KV7K

24
23
22

21
20
19

18
17
16

15
14
13

1

JP13

1

Tip

2

Ring

3

GND1

4

GND2

FOX_305-000-1176

ZZZ 2

MDC cable

45@

RJ11

CONN@

ACES_88020-124GCONN@

GND13GND14GND15GND16GND17GND

JP40

G1
G2

10
12

18

Note: M DO[3..0 ]+/- si gnals should route to JP1 3 first then to JP30.

LAN_ACT#24

+3V_LAN

B B

LANLINK_STATUS#24

+3V_LAN

LAN_ACT#

2

C381

@

300p_0402_25V

1

LAN_ACT#

R312 300_0402_5%

R313 300_0402_5%

12

MDO3-

MDO3+

MDO1-

MDO2-

MDO2+

MDO1+

MDO0-

MDO0+

LANLINK_STATUS#

12

LANLINK_STATUS#

2

C382

@

300p_0402_25V

1

1115 EMI REQUES T

A A

JP14

12

Yellow LED-

11

Yellow LED+

8

PR4-

7

PR4+

6

PR2-

5

PR3-

4

PR3+

3

PR2+

2

PR1-

1

PR1+

10

Green LED-

9

Green LED+

FOX_JM36113-L2R8-7F

GND

GND

ACES_85204-02001

14

13

1 2

ACZ_SD OUT_MDC

ACZ_S YNC_MDC
ACZ_S DIN1_R

1

C383

2

ACZ_SDOUT_M DC19

ACZ_S YNC_MDC19

ACZ_S DIN119

ACZ_RST#_MDC19

R314 33_0402_5%

MDC 1.5 Conn.

Chan ge type 4/2 5

JP15

1

1

3

3

5

5

7

7

9

9

11

11

+3VS

1

C384

2

1000P_0402_50V7K

ACZ_RST#_MDC

1

C385

2

0.1U_0402_16V4Z

4.7U_0805_10V4Z@

TIP

1

1

RIN G

2

2

3
4

+3VS

2

2

4

4

6

6

8

8

10
12

R315

10_0402_5%@

MDC STANDOFF

H5

H6

HOLEA

HOLEA

1

1

2

C5061000P_1808_3KV7K

1

7/24

ACZ_BITC LK_MDC 19

1 2

12

C380

10P_0402_25V8K@

2

1000P_1808_3KV7K

C507

1

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/02/13 2006/07/26

Compal Secret Data

Deciphered Date

Title

Size Doc ument Number Re v

2

Date: Sheet of

Compal Electronics, Inc.

Magnetic & RJ45/RJ11

LA-3821P

1

25 43Tues day, July 31, 2007

0.3

5

D D

4

3

SDPWR0_MSPW R

C386

0.1U_0402_16V4Z

2

+VCC_4in1

C387

@

1

2

40mil

12

R317

@

150K_0402_5%

R316

12

+3VS

1

2

@

0_0603_5%

U12

@

3

VIN

4

VIN/CE

2

GND

RT9701CB_SOT25

1

VOUT

5

VOUT

1U_0603_10V4Z

1

rese rved po wer circuit

+A3V

C389

1

1 2

C388 0.1U_0402_16V4Z

2

1 2

0_0402_5%

U13

1

AV_PLL

3

A3V3

7

A3V3

9

CARD_3V3

11

D3V3

33

D3V3

8

VBUS

44

RST#

45

MODE_SEL

47

XTLI

48

XTLO

4

DM

5

DP

14

GPIO0

2

RREF

12

DGND

32

DGND

6

AGND

46

AGND

RTS51 58-GR_LQFP48_7x7

R325

R319

USB20_N42 0
USB20_P420

6.19K_0402_1%

0.1U_0402_16V4Z

1 2

RST#
MODE SEL
XTLI

XTLO

USB20_N4
USB20_P4

R323

0_0603_5%

1 2

C390

1

1U_0603_10V4Z

C C

+5VS

+5VALW

C393

5.6P_0402_50V

7/25

C394

5.6P_0402_50V

B B

1

C395

0.1U_0402_16V4Z

@

2

R320 0_0603_5%

R321 0_0603_5%

@

1 2

1 2

MODE SEL

R326
10K_0402_5%

1 2

2

12

12

12

Y4

Used 9701 by 10 K

SDPWR0_MSPW R

C392

1

0.1U_0402_16V4Z

2

XTLI

12MHZ_16P_6X12000012

XTLO

+A3V

12

R324
100K_0402_5%

RST#

C396

1

1U_0603_10V4Z

2

1 2

R318 0_0402_5%

VREG

CF_DMACK#

CF_CS0#

XD_CLE/CF_SP19

XD_CE#/CF_D11_SP18

XD_ALE/CF_D4_SP17

SD_DAT2/XD_RE#/CF_D12_SP16

SD_DAT3/XD_WE#/CF_D 5_SP15

XD_RDY/CF_D13_SP14

SD_DAT4/XD_WP#/CF_D 6_SP13

SD_DAT5/XD_D0/CF_D14_SP12

SD_CLK/XD_D1/MS_CLK/CF_D7_S P11

SD_DAT6/XD_D7/MS_D3/CF_D15_S P10

SD_DAT7/XD_D2/MS_D2/CF_IOW R#_SP8

SD_DAT1/XD_D3/MS_D1/CF_IORDY_SP6

MS_INS#/CF_IORD#_SP9

SD_DAT0/XD_D6/MS_D0/CF_RST #_SP7

XD_D5/MS_BS/CF_A2_SP5

CF_A1/XD_D4_SP4

CF_A0/SD_CD#_SP3

CF_D0/SM_WPM#/XD_ WP_SP2

CF_D1/XD_CD#_SP1

CF_D8/SM_CD#_SP0

CF_CD#

CF_DMARQ

CF_D10

CF_D9
CF_D2

SD_CMD

10
22
30

43
42
41
40
39
38
37
35
34
31
29
28
27
26
25
23
21
20
19
18

13
24

15
16
17
36

C391

1 2

1U_0603_10V4Z

XDRE#_SDD2
XDWE#_SDD3

XDD1
XDD7_SDD6_MSD3

MSINS#
XDD2_SDD7_MSD2
XDD6_SDD0_MSD0
XDD3_SDD1_MSD1

XDD5_MSBS

SDCD #

SDWP

SDCMD

R322

22_0402_5%

1 2

SD_MS_CLK

+VCC_4in1

+VCC_4in1

3 in 1 Card Reader

XDD6_SDD0_MSD0
XDD3_SDD1_MSD1
XDRE#_SDD2
XDWE#_SDD3
SD_MS_CLK
SDWP
SDCMD
SDCD #

XDD3_SDD1_MSD1

SD_MS_CLK
MSINS#
XDD6_SDD0_MSD0
XDD5_MSBS
XDD7_SDD6_MSD3
XDD2_SDD7_MSD2

SD_MS_CLK

12

R327

10_0402_5%@

1

@

2

C397 10P_0402_50V8J

JP16

6

VDD_SD

9

DAT0_SD

10

DAT1_SD

2

DAT2_SD

3

CD/DAT3_SD

7

CLK_SD

11

WP_SD

4

CMD_SD

1

CD_SD

5

VSS_SD

8

VSS_SD

19

VCC_MS

13

VCC_MS

14

SCLK_MS

16

INS_MS

18

SDIO_MS

20

BS_MS

15

RESERVED_MS

17

RESERVED_MS

21

VSS_MS

12

VSS_MS

22

GND

23

GND

PROCO_M DR019-C0-1202

CONN@

A A

Compal Electronics, Inc.

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

Size Documen t Number Re v

Date: Sheet of

Ca rd rea der bo ard

LA-38 21P

1

26 43Tuesd ay, July 31 , 2007

0.3

A

1 1

1U_0603_10V4Z

C503

EC_BEEP32

12

R454

1 2

560_0402_5%

B

+VDDA_ALC268

12

12

1

C

2

B

E

3

R452

10K_0402_1%

C502

1U_0603_10V4Z

R453

10K_0402_1%

PCBEEP_R

Q38

2SC2411K_SOT23

C

D

E

F

G

H

28.7K for Module Design (VDDA = 4.702)

1

2

40mil

C402

(output = 250 mA)

+VDDA

4.85V

1

R329

30K_0402_1%

1 2

12

R331
10K_0402_1%

C401
10U_0805_10V4Z

2

L11

+5VS

12

1 2

KC FBM-L11-201209-221LMAT_0805

L12

1 2

KC FBM-L11-201209-221LMAT_0805

+5VAMP

1

C399

10U_0805_10V4Z

2

0.1U_0402_16V4Z

60mil

1

C400

2

U14

4

VIN

2

SENSE or ADJ

DELAY

ERROR7CNOISE

8

SD

SI9182DH-AD_MS OP8

VOUT

GND

5

6

1

3

0.1U_0402_16V4Z

C504

SB_SPKR20

2 2

3 3

12

1U_0603_10V4Z

PCBEEP_R

Sense Pin Impedance Codec Signals

39.2K

SENSE A

4 4

SENSE B

A

20K

10K

5.1K

39.2K

20K

10K

5.1K

R455

1 2

560_0402_5%

12

D29

R456

@

10K_0402_5%

R328
0_0402_5%

PCBEEP_C PCBEEP

1 2

HP_DET#28
EXTMIC_DET#28

R330

@

5.1K_0402_5%

1 2

RB751V_SOD323

2 1

C398

1U_0603_10V4Z

1 2

R339 39.2K_0402_1%

1 2

R340 20K_0402_1%

PORT-A (PIN 39, 41)

PORT-B (PIN 21, 22)

PORT-C (PIN 23, 24)

PORT-D (PIN 35, 36)

PORT-E (PIN 14, 15)

PORT-F (PIN 16, 17)

PORT-G (PIN 43, 44)

PORT-H (PIN 45, 46)

B

+VDDA

MIC_IN _L28

MIC_IN _R28

MIC_EXT_L28

MIC_EXT_R28

12

L14

1 2

FBM-L11-160808-800LMT_0603

C409

10U_0805_10V4Z

MIC_IN _L

MIC_IN _R

MIC_EXT_L

MIC_EXT_R

ACZ_RST#19,32

C

1

2

0.1U_0402_16V4Z

MIC_IN _C_L

MIC_IN _C_R

MIC_EXT_C_L

MIC_EXT_C_R

ACZ_RST#

SENSE_A

T48

1

2

40mil

C411

0.1U_0402_16V4Z

1

C410

2

1 2

C412 2.2U _0603_6.3V4Z

1 2

C413 2.2U _0603_6.3V4Z

1 2

C417 2.2U _0603_6.3V4Z

1 2

C418 2.2U _0603_6.3V4Z

ACZ _SYNC19

ACZ_SD OUT19

DGND

HD Audio Codec

U15

14

15

16

17

23

24

18

20

19

21

22

12

11

10

5

2

3
13
34

47

48

4

7

+VDDA_ALC268

AVDD125AVDD2

NC

NC

MIC2_L

MIC2_R

LINE1_L

LINE1_R

CD_L

CD_R

CD_GND

MIC1_L

MIC1_R

PCBEEP

RESET#

SYNC

SDATA_OUT

GPIO0
GPIO3
SENSE A
SENSE B

EAPD

SPDIFO

DVSS1
DVSS2

20mil

38

ALC268-GR_LQFP48_9X9

1

LINE_OUT_L

LINE_OUT_R

HP_OUT_L

HP_OUT_R

DMIC_CLK

BIT_CLK

SDATA_IN

MONO_OUT

LINE1_VREFO

GPIO1

MIC1_VREFO_L

MIC1_VREFO_R

MIC2_VREFO

VREF

JDREF

AVSS1
AVSS2

DVDD

0.1U_0402_16V4Z

9

DVDD_IO

35

36

39

41

45

NC

46

43

NC

44

NC

6

8

37

29

31

28

32

30

27

40

33

NC

26
42

+3VS_DVDD

1

1

C407

C406

2

2

0.1U_0402_16V4Z

LINE_OUTL

LINE_ OUTR

HP_OUTL

HP_OUTR

C416 22P_0402_50V8J

1 2

R337 33_0402_5%

1 2

10mil

MIC1_VR EFO_L

MIC1_ VREFO_R

MIC2_VR EFO

CODEC _VREF

12

R342
20K_0402_1%

L13

MBK16 08301YZF_0603

1

C408

10U_0805_10V4Z

2

12

LINE_OUTL 28

LINE_OUTR 28

HP_OUTL 28

HP_OUTR 28

R336 0_0402_5%

1 2

ACZ_BITCLK 19

ACZ_S DIN0 19

10mil

1

C419
10U_0805_10V4Z

2

+3VS

AGND

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

D

2006/08/18 2007/8/18

E

Compal Secret Data

Deciphered Date

F

1 2

R343 0_0805_5%

1 2

R344 0_0805_5%

1 2

R345 0_0805_5%

GND GNDA

Title

Size Doc ument Number Re v

B

Date: Sheet of

Compal Electronics, Inc.

HD Audio Codec ALC268

LA-3821P

G

27 43Tues day, July 31, 2007

H

0.3

A

1 1

C428 0.4 7U_0603_ 10V7K

1 2

LIN E_OUT R_R

0_0603_ 5%

R459

@

12

R457

12

R458

12

C431

C492 0.4 7U_0603_ 10V7K

EC_MUTE #32

1 2

1 2

0_0603_ 5%
0_0603_ 5%

0.47 U_0603_10V 7K

EC_MUTE # EXTMIC_DE T#

LINE _OUTR27

LINE_ OUTL27

2 2

7

17

9

5

19

U16

RIN+

RIN-

LIN+

LIN-

SHUTDOWN

GND5

20

21

B

10U _0805_10V4 Z

16

15

6

VDD

PVDD1

PVDD2

GAIN0

GAIN1

ROUT+

ROUT-

LOUT+

LOUT-

BYPASS

GND41GND311GND213GND1

P30 17THF D0 TSSOP 20 P

C421

NC

1

2

2

3

18

14

4

8

12

10

0.1U _0402_16 V4Z

1

C423

C422

2

0.1U _0402_16 V4Z

SPKR+

SPK R-

Ke ep 10 mil wi dth

2

C43 3

0.47 U_0603_10 V7K

1

1 2

1

2

100K_04 02_5%

@

100K_04 02_5%

R346
0_1206_ 5%

R347

R349

12

12

+5VS+5VAMP

10 d B

C

MIC _IN_L27

+5VS

12

R348

@

100K_04 02_5%

12

R350
100K_04 02_5%

MIC2 _VREF O

C499 4 7P_0402_50V8 J@

MIC _IN_R2 7

MIC_EXT_R27

MIC_EXT_L27

MIC1 _VREF O_R

MIC1_ VREFO _L

MIC INT In-L

C430 4 7P_0402_50V8 J@

12

MIC INT In-R

12

D25

2 1

CH7 51H-40 PT_SOD323-2

D28

2 1

CH7 51H-40 PT_SOD323-2

R389 2.2K_ 0402_5%

1 2

R447 2.2K_ 0402_5%

1 2

D

MIC IN_L

12

R3510_0603_ 5%

0_0603_ 5%

12

L20

@

47P_040 2_50V8J

1

C50 9

2

7/31 EMI

M ICIN_ R

12

R4410_0603_ 5%

0_0603_ 5%

47P_040 2_50V8J

R448 2.2K_ 0402_5%

1 2

R449 2.2K_ 0402_5%

1 2

MIC_EXT_R MICE XT_R

MIC_EXT_L

R353 0_0603_5 %

R352 0_0603_5 %

MICEXT_R

MICEXT_L

12

1

L21

C51 0

@

2

M ICIN_ R

MIC IN_L

EXTMIC_DE T#27

C435 4 7P_0402_50V8 J@

12

12

12

12

C434 4 7P_0402_50V8 J@

12

L230_0603_5%

MICEXT_L

12

L220_0603_5%

SPKR+
SPK R-

JP37

1

1

2

2

3

G1

4

G2

ACE S_85204-0200 1

CO NN@

2

3

D15

@

1

SM05_SOT23

E

JP35

1

1

2

2

3

G1

4

G2

ACE S_85204-0200 1

CO NN@

1

1

C49 7

C49 8

2

@

47P _0402_50V8J

2

@

47P _0402_50V8J

MIC EXT In

JP19

5

4

3
6 7
2
1

FOX _JA6333L-B 3S0-7F~N

CO NN@

SPEAKER

JP36

1
2

ACE S_85204-0200

CO NN@

10
9
8

3 3

HeadPhone Out/Line Out

HP_ DET#27

cap. high 5.7mm

C437

HP_ OUTR27

HP_ OUTL27

EC_MUTE32

4 4

HP_ OUTR

HP_ OUTL PL

EC_MUTE EC_MUTE

2N7002_ SOT23-3

+

1 2

Q18

2

G

100 U_D2_6.3VM

C438

+

1 2

13

D

S

100 U_D2_6.3VM

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2006/02/13 2007/08/29

C

HP_ OUT_R

HP_ OUT_L

13

D

G

Q19

2N7002_ SOT23-3

S

2

Compal Secret Data

Deciphered Date

C436 4 7P_0402_50V8 J@

R356 0_0603_5 %

R357 0_0603_5 %

12

12

12

12

C439 4 7P_0402_50V8 J @

D

HP_ DET#

JP20

5

PR

2

D16

@

SM05_SOT23

1

Title

Size D ocum ent Nu mber R ev

Da te: S heet o f

4

3
6 7
2
1

FOX _JA6333L-B 3S0-7F~N

3

CO NN@

0302 _Change A udio Jack .

Compal Electronics, Inc.

AMP & Audio Jack

LA-3821P

E

10
9
8

0.3

28 43Tue sday, July 31, 20 07

5

+5VALW

4

3

2

1

U23

1

C446 0.1U_0402_16V4Z

D D

C443 0.1U_0402_16V4Z

12

SYSON #33,37

+5VALW

12

SYSON #33,37

GND

2

IN

3

IN

4

EN#

RT9711PS_SO8

2nd source: SA005280110

U17

1

GND

2

IN

3

IN

4

EN#

RT9711PS_SO8

2nd source: SA005280110

BT Connector

JP39

1

9

1

GND

2

2

USB20_P5_R

3

3

USB20_N5_R

4

4

5

5

6

C C

ACES_87213-0800G

BT_OFF32

B B

6

7

7

8

10

8

GND

CONN@

1U_0603_10V4Z

C454

1

2

R371 47K_0402_5%

1 2

R363 0_0402_5%
R364 0_0402_5%
R367 1K_0402_5%@
R366 1K_0402_5%@

Chan ge value. 5/10

Rese rve R674, R677
caus e BlueFlame
co-ex istance
issue . 6/14

12

R369
100K_0402_5%

1 2
1 2

S

+USB_VCCB

8

OUT

7

OUT

6

OUT

5

FLG

+USB_VCCA

8

OUT

7

OUT

6

OUT

5

FLG

12
12

Q20

AP2305GN

D

13

G

2

1

2

12

3

1

C4550.01U_0402_16V7K

1

2

C458

0.1U_0402_16V4Z

RV t o Install . 5/10

R361
0_0402_5%

+3VAUX_BT

2

D17
PSOT24C_SOT23-3

@

+3VAUX_BT+3VALW

C4560.1U_0402_16V4Z

1

1

2

2

USB_OC#2 20

USB_OC#0 20

USB_OC#1 20

USB20_P5 20
USB20_N5 20

CH_CL K 22

CH_DATA 22
BT_LED 30

C4574.7U_0805_10V4Z

07/23

1

2

C447

C444

1000P_0402_50V7K

1

2

0.1U_0402_16V4Z

1

2

USB Port

For EMI

R360 0_0402_5%

1 2

L15

1

1

USB20_N020

USB20_P020

4

WCM2012F2S-900T04_0805

R362 0_0402_5%

4

1 2

2

3

0.1U_0402_16V4Z

+

C440

100U_6.3V_M

2

3

10P_0402_50V8J@

For EMI

R365 0_0402_5%

1 2

L16

1

USB20_N12 0

USB20_P120

1

4

4

WCM2012F2S-900T04_0805

1 2

R368 0_0402_5%

For EMI

R372 0_0402_5%

1 2

L17

4

USB20_P220

USB20_N22 0

4

1

1

WCM2012F2S-900T04_0805

1 2

R370 0_0402_5%

2

2

3

3

100U_D2_6.3VM

3

3

USB20_P2_R
USB20_N2_R

2

2

10P_0402_50V8J@

C451

10P_0402_50V8J@

C449

1

+

2

0.1U_0402_16V4Z

C459

C452

1

C441

C448

2

1

@

2

1

2

1

2

1

2

+USB_VCCA

1

1

C442

1000P_0402_50V7K

2

2

USB20_N0_R
USB20_P0_R

C445
10P_0402_50V8J

USB20_N1_R
USB20_P1_R

1

C450
10P_0402_50V8J

@

2

+USB_VCCB

1

C453

1000P_0402_50V7K

2

1

C460

@

2

10P_0402_50V8J

+USB_VCCA

USB20_N1_R
USB20_P1_R

USB20_N0_R
USB20_P0_R

JP24

1

1

2

2

3

3

4

4

5

GND

6

GND

7

GND

8

GND

SUYIN_0 20173MR004S558ZL

CONN@

JP17

1
2
3
4
5
6
789

10

CONN@

SUYIN_0 20122MR008S535ZA

Finger printer

C462

0.1U_0402_16V4Z

USB20_N720

USB20_P720

A A

5

R375 0_0402_5%
R376 0_0402_5%

2

3

D18
PSOT24C_SOT23-3

@

1

12
12

+3VS

1

2

USB20_N7_R
USB20_P7_R

JP26

1

1

2

2

3

3

4

4

5

G1

6

G1

E&T_3802-E04N-01R

CONN@

4

PC Camera

C461

0.1U_0402_16V4Z

USB20_N620
USB20_P620

R373 0_0402_5%
R374 0_0402_5%

2

3

D19
PSOT24C_SOT23-3

@

1

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

12
12

2006/02/13 2006/07/26

+3VS

1

2

USB20_N6_R
USB20_P6_R

ACES_88266-05001

Compal Secret Data

Deciphered Date

JP25

1

1

2

2

3

3

4

4

5

5

6

GND1

7

GND2

CONN@

Title

Size Doc ument Number Re v

2

Date: Sheet of

Compal Electronics, Inc.

USB CONN.

LA-3821P

29 43Tues day, July 31, 2007

1

0.3

5

4

3

2

1

Power ON/OFF

+3VALW

R379

4.7K_0402_5%

I

2

CAP_CLK

CAP_DATA

1

O

1 2

ON/ OFF

51ON#

G

1000P_0402_50V7K

3

1

0216 _Delete D19 .

2

C463

CAP_RESET32

I2C_INT32

LID_SW#32

ON/ OFF 32

51ON# 36

CAP_CLK
CAP_DATA

12

@

12

R442

R444

0_0402_5%

12

4.7K_0402_5%

@

10K_0402_5%

T/P Board

+3VS + 3VL

12

12

R469

R443

4.7K_0402_5%

+5VS

R470

0_0402_5%

@

07/23

JP38

1 9
2 10
3 11
4 12
5
6
7
8

ACES_85203-08421-11_8P

CONN@

13
14
15
16

JP29

CONN@

ACES_87151-06051

TP_DATA
TP_CLK

8

G2

7

G1

6

6

5

5

4

4

3

3

2

2

1

1

C465

@

100P_0402_50V8J

TP_DATA
TP_CLK

1

2

3

1

TP_DATA

TP_CLK

1

@

2

2

D26
PSOT24C_SOT23-3

@

EMI req uest

+5VS

TP_DATA 32
TP_CLK 32

C466
100P_0402_50V8J

1

C464

@

0.1U_0402_16V4Z

2

Wireless ON Amber

D D

C C

SMT1-05-A_4P

3

4

SMB_EC_CK24,32

SMB_EC_DA24,32

ESB_CLK

ESB_DATA

5

SW1

D23

1

2

6

ON/OFF BTN#

EC_ON32

R463 0_0402_5%

SMB_EC_CK2

R464 0_0402_5%

SMB_EC_DA2

R465 0_0402_5%@

ESB_CLK

R466 0_0402_5%

ESB_DATA

DAN20 2U_SC70

EC_ON

1 2

1 2

1 2

@

1 2

1

Q21
DTC124EK_SC59

+3VALW

12

R383

4.7K_0402_5%

2

3

06/15 Change pin define for try ENE cap bottom

Bluethooth ON Blue

Battery Charge LED(Left 2)

B B

BLUE_LED#32

AMBER_LED#32

HDD LED(Left 3)

SATA_LED#19

LTST-C191TBKT-5A_BLUE_0603~D

BLUE

D27

Blue

2

1

4

3

Orang e

AMBER

LTST-C195TBKFKT_BLUE/ORG

BLUE

D22

1 2

R385

R386

R380

1 2

470_0402_5%

12

12

200_0402_5%

+5VALW

820_0402_5%

+5VS

ON/OFF BTN_LED#31,32

POWER LED1

BLUE

ON/OFF BTN_LED#

LTST-C191TBKT-5A_BLUE_0603~D

LTST-C191TBKT-5A_BLUE_0603~D

D20

1 2

D21

1 2

POWER LED2

R377

1 2

470_0402_5%

R384

1 2

470_0402_5%

+5VALW

R381

820_0402_5%

Q25

BT_LED29

2N7002_SOT23-3

2

G

+5VS

Blue

07/23

+3VS

12

12

R382
200_0402_5%

2

4

AMBERBLUE

D24LTST-C195TBKFKT_BLUE/ORG

1

3

Orang e

WL_LED#

13

D

S

+5VS

WL_LED# 22

R232

1 2

4.7K_0201_5%

06/04

WL_LED#

A A

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

2006/02/13 2006/07/26

3

Compal Secret Data

Deciphered Date

Title

Size Doc ument Number Re v

Date: Sheet of

2

Compal Electronics, Inc.

LED/SW

LA-3821P

1

30 43Tues day, July 31, 2007

0.3

+3VALW+3VALW

1

C467

0.1U_0402_16V4Z

SMB_EC_CK132,40
SMB_EC_DA132,40

2

U18

8
7
6
5

AT24C 16AN-10SI-2.7_SO8

A0

VCC

A1

WP
SCL

A2

SDA

GND

SPI ROM

+3VALW

20mil s

1

C468

0.1U_0402_16V4Z

FSEL#32

SPI_CLK32

FWR # FR D#

2

1 2

R392 0_0402_5%

1 2

R393 0_0402_5%

1 2

R394 0_0402_5%

SPI_FSEL#

SPI_CLK_R

B-Test remove SPI ROM socket

U19

8

VCC

3

W

7

HOLD

1

S

6

C

5

D

&U19

SST25LF080B_SO8-200mil

12

R390
100K_0402_5%

1
2
3
4

12

R391
100K_0402_5%

4

VSS

SPI_SOSPI_F WR#

2

Q

WIES ON G6179 8P SPICONN@

1 2

R395 0_0402_5%

FRD # 32FWR #32

+3VALW

ON/OFF BTN_LED#30,32

CAPS_LED#32

NUM_LED#32

VCC1_ PWRGD32

LPC Debug Port

CLK_DEBU G_PORT_115

LPC_FRAME#19,22,32

PCI_RST#18,32

LPC_AD019 ,22,32
LPC_AD119 ,22,32
LPC_AD219 ,22,32
LPC_AD319 ,22,32

SPI_CLK_JP 52
SPI_CS#_JP 52
SPI_S I_JP52
SPI_SO_JP52
SPI_H OLD#_0

Conn ect pin3 & 23
toge ther and pin 24
to G ND in 6/29.

SPI_CLK_R

FSEL#

FWR #

HOLD#

FR D#

R396 0_0402_5%DEBUG@

1 2

R397 0_0402_5%DEBUG@

1 2

R398 0_0402_5%DEBUG@

1 2

R399 0_0402_5%DEBUG@

1 2

R400 0_0402_5%DEBUG@

1 2

1 2

R401 0_0402_5%DEBUG@

1 2

R402 0_0402_5%DEBUG@

1 2

R403 0_0402_5%DEBUG@

1 2

R404 0_0402_5%DEBUG@

Chan ge fro m +3VL to +3 VS. 6/9

Remo ved +3VS. 6/13

B+

JP30

1

Ground

2

LPC_PCI_CLK

3

Ground

4

LPC_FRAME#

5

+V3S

6

LPC_RESET#

7

+V3S

8

LPC_AD0

9

LPC_AD1

10

LPC_AD2

11

LPC_AD3

12

ON/OFF BTNLED#
CAPSLED#
NUMLED#
VCC1P WRGD

SPI_CLK_JP 52

SPI_CS#_JP 52

SPI_S I_JP52

SPI_H OLD#_0

SPI_SO_JP52

ON/OFF BTNLED#

CAPSLED#

NUMLED#

VCC1P WRGD

VCC_3VA

13

PWR_LED#

14

CAPS_LED#

15

NUM_LED#

16

VCC1_PWRGD

17

SPI_CLK

18

SPI_CS#

19

SPI_SI

20

SPI_SO

21

SPI_HOLD#

22

Reserved

23

Reserved

24

Reserved

ACES_87216-2404_24P

CONN@

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2006/02/13 2006/07/26

Compal Secret Data

Deciphered Date

Title

Size Doc ument Number Re v

Date: Sheet of

Compal Electronics, Inc.

BIOS ROM

LA-3821P

31 43Tues day, July 31, 2007

0.3

+3VALW_EC

1

2

0.1U_0402_16V4Z

R417

4.7K_0402_5%

4.7K_0402_5%

PWRBTN_OUT#2 0

ESB_DATA

0.1U_0402_16V4Z

C469

12

R418

SUSP#23,33, 35,37,38

ESB_CLK

1

2

12

C470

12

R415

4.7K_0402_5%

0.1U_0402_16V4Z

1

2

1000P_0402_50V7K

12

R416

4.7K_0402_5%

SMB_EC_DA1
SMB_EC_CK1
SMB_EC_DA2
SMB_EC_CK2

SUSP# EC_SUSP#

SUSP#

PWRBTN_OUT#

ESB_CLK

ESB_DATA

1

C471

2

R467 0_0402_5%

1 2

R468 0_0402_5%

1 2

R451 0_0402_5%@

1 2

R460 0_0402_5%

@

1 2

R461 0_0402_5%@

1 2

R462 0_0402_5%

@

1 2

1

C472

2

C476

@

1 2

15P_0402_50V8J

CLK_P CI_EC15

+3VALW

C477

1 2

0.1U_0402_16V4Z

+3VALW +3VS

1000P_0402_50V7K

C473

R408

@

1 2

33_0402_5%

R409

47K_0402_5%

12

R413
10K_0402_5%

LID_SW#

EC_PWRBTN_OUT#PWRBTN_OUT#

EC_PIN17

EC_PIN18

06/15 Change pin define for try ENE cap bottom

05/23 c hange to

voltage contro l FAN

EC DEBUG port

JP32

CONN@

1

1

2

2

3

3

4

4

ACES_85205-0400

FOR LPC SIO DEBUG PORT

JP33

CONN@

1

1

2

2

3

3

4

4

5

5

6

6

LPC_AD0

7

7

LPC_AD1

8

8

LPC_AD2

9

9

LPC_AD3

10

10

LPC_FRAME#

11

11

LPC_DR Q#0

12

12

PCI_RST#

13

13

14

14

CLK_DEBU G_PORT_1

15

15

SIRQ

16

16

17

17

18

18

19

19

20

20

ACES_85201-2005

URX
UTX

+5VS

+5VALW

+3VS

CLK_14M_DEBUG 15

LPC_DR Q#0 19

R423

@

10K_0402_5%

CLK_DEBU G_PORT_2 15

3

2

12

GATEA2019
KB_RST#19

SIRQ20

LPC_FRAME#19,22,31

LPC_AD319 ,22,31
LPC_AD219 ,22,31
LPC_AD119 ,22,31
LPC_AD019 ,22,31

12

12

1 2

27P_0402_50V8J

NC

NC

Y5

1 2

27P_0402_50V8J
C479

PCI_RST#18,31

EC_SC I#20

12

J1

JOPEN

R414
10K_0402_5%

WL_BTN#

SMB_EC_CK131,40
SMB_EC_DA131,40
SMB_EC_CK24,30
SMB_EC_DA24,30

SLP_S3#20
SLP_S5#20
EC_SMI#20

LID_SW#30

PCI_PME#18

FAN_SPEED4

CAP_RESET30

ON/ OFF30

CPUSB#20,23

NUM_LED#31

C478

4

OUT

1

IN

32.768 KHZ_12.5P_1TJS125DJ2A073

SUSP#

12

R421
100K_0402_5%

GATEA20
KB_RST#
SIRQ
LPC_LFRAME#
LPC_LAD3
LPC_LAD2
LPC_LAD1
LPC_LAD0

CLK_P CI_EC
PCI_RST#
ECRST#
EC_SC I#

KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7
KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15

SMB_EC_CK1
SMB_EC_DA1
SMB_EC_CK2
SMB_EC_DA2

SLP_S3#
SLP_S5#
EC_SMI#
LID_SW#

EC_PIN17
EC_PIN18

CAP_RESET
UTX
URX

ON/ OFF

CPUSB#

NUM_LED#

12

R422

CR Y1

CR Y2

20M_0402_5%@

+3VALW

R406

0_0805_5%

U20

1

GA20/GPIO00

2

KBRST#/GPIO01

3

SERIRQ#

4

LFRAME#

5

LAD3

7

LAD2

8

LAD1

10

LPC & MISC

LAD0

12

PCICLK

13

PCIRST#/GPIO05

37

ECRST#

20

SCI#/GPIO0E

38

CLKRUN#/GPIO1D

55

KSI0/GPIO30

56

KSI1/GPIO31

57

KSI2/GPIO32

58

KSI3/GPIO33

59

KSI4/GPIO34

60

KSI5/GPIO35

61

KSI6/GPIO36

62

KSI7/GPIO37

39

KSO0/GPIO20

40

KSO1/GPIO21

41

KSO2/GPIO22

42

KSO3/GPIO23

43

KSO4/GPIO24

44

KSO5/GPIO25

45

KSO6/GPIO26

46

KSO7/GPIO27

47

KSO8/GPIO28

48

KSO9/GPIO29

49

KSO10/GPIO2A

50

KSO11/GPIO2B

51

KSO12/GPIO2C

52

KSO13/GPIO2D

53

KSO14/GPIO2E

54

KSO15/GPIO2F

81

KSO16/GPIO48

82

KSO17/GPIO49

77

SCL1/GPIO44

78

SDA1/GPIO45

79

SCL2/GPIO46

80

SDA2/GPIO47

6

PM_SLP_S3#/GPIO04

14

PM_SLP_S5#/GPIO07

15

EC_SMI#/GPIO08

16

LID_SW#/GPIO0A

17

SUSP#/GPIO0B

18

PBTN_OUT#/GPIO0C

19

EC_PME#/GPIO0D

25

EC_THERM#/GPIO11

28

FAN_SPEED1/FANFB1/GPIO14

29

FANFB2/GPIO15

30

EC_TX/GPIO16

31

EC_RX/GPIO17

32

ON_OFF/GPIO18

34

PWR_LED#/GPIO19

36

NUMLED#/GPIO1A

122

XCLK1

123

XCLK0

+3VALW_EC

+EC_AVCC

12

+3VALW_EC

12

Int . K/B
Matr ix

SM Bu s

L18
0_0603_5%

1 2

C480

Secur ity Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

+EC_AVCC

9

22

33

96

111

125

VCC

VCC

VCC

VCC

VCC

VCC

INVT_PWM/PWM 1/GPIO0F

ACOFF/FANPWM2/GPIO13

PW M Outp ut

AD Inp ut

DA Ou tpu t

PS 2 Int erf ace

TP_DATA/PSDAT3/GPIO4F

SP I Devi ce Int erfac e

SP I F las h RO M

BATT_CHGI_LED#/GPIO52

GP IO

G PO

GP IO

GP I

GND

GND

GND

GND

GND

11

24

35

94

113

0.1U_0402_16V4Z

Issued Date

67

AVCC

BEEP#/PWM2/GPIO10

FANPWM1/GPIO12

BATT_TEMP/AD0/GPIO38

BATT_OVP/AD1/GPIO39

ADP_I/AD2/GPIO3A

AD3/GPIO3B
AD4/GPIO42

SELIO2#/AD5/GPIO43

DAC_BRIG/DA0/GPIO3C
EN_DFAN1/DA1/GPIO3D

IREF/DA2/GPIO3E

DA3/GPIO3F

PSCLK1/GPIO4A
PSDAT1/GPIO4B
PSCLK2/GPIO4C
PSDAT2/GPIO4D

TP_CLK/PSCLK3/GPIO4E

SDICS#/GPXOA00
SDICLK/GPXOA01

SDIDO/GPXOA02

SDIDI/GPXID0

SPIDI/RD#

SPIDO/WR#

SPICLK/GPIO58

SPICS#

CIR_RX/GPIO40

CIR_RLC_TX/GPIO41

FSTCHG/SELIO#/GPIO50

CAPS_LED#/GPIO53

BATT_LOW_LED#/GPIO54

SUSP_LED#/GPIO55

SYSON/GPIO56

VR_ON/XCLK32K/GPIO57

AC_IN/GPIO59

EC_RSMRST#/GPXO03
EC_LID_OUT#/GPXO04

EC_ON/GPXO05

EC_SWI#/GPXO06

ICH_PWROK/GPXO06

BKOFF#/GPXO08

WL_OFF#/GPXO09

GPXO10
GPXO11

PM_SLP_S4#/GPXID1

ENBKL/GPXID2

GPXID3
GPXID4
GPXID5
GPXID6
GPXID7

V18R

AGND

KB926QFB0_LQFP128_14X14

69

ECAGND

L19

1 2

0_0603_5%

2006/02/13 2006/07/26

INV_PWM

21

EC_BEEP

23
26

ACOF F

27

63
64
65
66
75
76

DAC_B RIG

68

EN_FAN

70

IRE F

71
72

EC_MUTE#

83

ACZ_RST#

84
85
86

TP_CLK

87

TP_DATA

88

R411

97

LAN_P OWER_OFF

98
99
109

FR D#

119

FWR #

120

SPI_CLK

126

FSEL#

128

I2C_INT

73

VCC1_ PWRGD

74

FSTCHG

89
90

CAPS_LED#

91

BAT_LED#

92

ON/OFF BTN_LED#

93

SYS ON

95

VR_ON

121

AC IN

127

EC_RSMRST#

100

R420 0_0402_5%

101

EC_ON

102
103

PM_PWROK

104

BKOFF#

105

M_PWROKPCI_PME#

106
107

WL_ON#

108

SLP_S4#

110

ENABLT

112
114

THERM_SCI#

115

EC_SUSP#

116

EC_PWRBTN_OUT#

117
118

124

INV_PWM 17
EC_BEEP 27

ACOF F 35

BATT_TEMP
BATT_OVP
ADP_I N
M/B_ID

05/23 c hange to

voltage contro l FAN

CLK_ENABLE

12

1 2

C475 0.01U_0402_16V7K

BATT_TEMP 40
BATT_OVP 35
ADP_I 35

DAC_B RIG 17
EN_FAN 4
IREF 35

EC_MUTE# 28
ACZ_RST# 19,27

TP_CLK 30
TP_DATA 30

10K_0402_5%

LAN_P OWER_OFF 24

FRD# 31
FWR # 31
SPI_CLK 31
FSEL# 31

I2C_INT 30
VCC1_ PWRGD 31
FSTCHG 35
AMBER_LED# 30

CAPS_LED# 31

BLUE_LED# 30
ON/OFF BTN_LED# 30,31

SYSO N 23 ,33,37

VR_ON 39
ACIN 35

12

R419 10K_0402_5%

EC_RSMRST# 20

EC_ON 30
BT_OFF 29

PM_PWROK 7,20

BKOFF# 17

M_PWROK 7,20

EC_MUTE 28
WL_ON# 22

SLP_S4# 20

ENABLT 9,17

THERM_SCI# 20

Compal Secret Data

Deciphered Date

1 2

CLK_ENABLE 15

06/14

04/17

EC_LI D_OUT# 20

04/14

ECAGND

05/03

04/04

+3VALW_EC

M/B_ID

1

C474

@

0.1U_0402_16V4Z

2

VCC 3 .3V+/- 5%

Ra 100K+ /-5%

Board ID Rb V

0

0 0V 0V 0V

1

8.2K+ /-5%

2

18K+/- 5%

3

33K+/- 5%

4

56K+/- 5%

5

100K+ /-5%

6

200K+ /-5%

7

NC

min V typ

AD_BID

0.216V

0.436V

0.712V

1.036V

1.453V

1.935V

2.500V

05/23 E C request

TP_CLK

TP_DATA

AC IN

AD_BID

0.250V

0.503V

0.819V

1.185V

1.650V

2.200V

3.300V

Remov e T/P d is/ena

C505

1 2

100P_0402_50V8J

For EMI

JP31

KSO15

1

1

KSO10

2

2

KSO11

3

3

KSO14

4

4

KSO13

5

5

KSO12

6

6

KSO3

7

7

KSO6

8

8

KSO8

9

9

KSO7

10

10

KSO4

11

11

KSO2

12

12

KSI0

13

13

KSO1

14

14

KSO5

15

15

KSI3

16

16

KSI2

17

17

KSO0

18

18

KSI5

19

19

KSI4

20

20

KSO9

21

21

KSI6

22

22

KSI7

23

23

KSI1

24

24

25

GND1

26

GND2

ACES_85201-24051

CONN@

SP01000FF00 85201-24051 24P P1.0
ACES_85201-24051_24P

Title

Size Doc ument Number Re v

Date: Sheet of

Compal Electronics, Inc.

EC KB926/KB conn

LA-3821P

KSO14
KSO11
KSO10
KSO15

KSO6
KSO3
KSO12
KSO13

KSO2
KSO4
KSO7
KSO8

KSI3
KSO5
KSO1
KSI0

KSI4
KSI5
KSO0
KSI2

KSI1
KSI7

100P_1206_8P4C_50V8@

100P_1206_8P4C_50V8@

100P_1206_8P4C_50V8@

100P_1206_8P4C_50V8@

100P_1206_8P4C_50V8@

100P_1206_8P4C_50V8@

Ra

12

R405

100K_0402_5%

Rb

12

R407
0_0402_5%

V

0.289V

0.538V

0.875V

1.264V

1.759V

2.341V

3.300V

12

R41010K_0402_5%

12

R41210K_0402_5%

CP1

2
3
4 5

CP2

2
3
4 5

CP3

2
3
4 5

CP4

2
3
4 5

CP5

2
3
4 5

CP6

2
3
4 5

32 43Tues day, July 31, 2007

AD_BID

+5VS+3VS +5VALW

max

81
7
6

81
7
6

81
7
6

81
7
6

81
7
6

81
7
6

0.3

A

1 1

2 2

+5VALW to +5VS Transfer +3VALW to +3VS Transfer

+5VS+5VALW +3VS+3VALW

U21

1

C481

2

10U_0805_10V4Z

8
7
6
5

D
D
D
D

AO4466_SO8

RU NON

1

S

2

S

3

S

4

G

1

C483

2

0.1U_0402_16V4Z

B

1

C484

10U_0805_10V4Z

2

R424

330K_0402_5%

SUSP

2

G

B+

12

13

D

Q28
2N7002_SOT23-3

S

1

C482

2

10U_0805_10V4Z

RU NON

8

D

7

D

6

D

5

D

AO4466_SO8

12

1

2

C

U22

1

S

2

S

3

S

4

G

0.1U_0402_16V4Z

R425

470_0402_5%

C487

0.01U_0402_16V7K

10U_0805_10V4Z

1

1

C485

2

2

C486

D

C488

1 2

0.1U_0402_16V4Z

C489

+VCCP +1.5VS

1 2

0.1U_0402_16V4Z

E

+VCCP+VCC_C ORE

SUSP

SUSP#

2

G

+5VALW

12

13

D

2

G

S

12

R433

470_0402_5%

13

D

Q36
2N7002_SOT23-3

S

R427

100K_0402_5%

Q30
2N7002_SOT23-3

2

G

12

R434

470_0402_5%

13

D

Q37
2N7002_SOT23-3

S

H7
HOLEA

1

H15
HOLEA

1

H23
HOLEA

1

H32
HOLEA

1

H8
HOLEA

1

H16
HOLEA

1

H24
HOLEA

1

H9
HOLEA

1

H17
HOLEA

1

H25
HOLEA

1

1

H10
HOLEA

1

H18
HOLEA

1

H26
HOLEA

1

FM1

1

H11
HOLEA

1

H19
HOLEA

1

H27
HOLEA

1

FM2

1

H12
HOLEA

1

H20
HOLEA

1

H28
HOLEA

1

FM3

1

H13
HOLEA

1

H21
HOLEA

1

H29
HOLEA

1

FM4

H14
HOLEA

1

H22
HOLEA

1

H31
HOLEA

1

+5VALW

12

R426

100K_0402_5%

SYSON #29,37 SUSP37

3 3

SYSO N#

SYS ON

2

G

13

D

Q29
2N7002_SOT23-3

S

SUSP#23,32, 35,37,38SYSON23,32,37

Discharge circuit

2

G

+1.8V

12

13

D

S

R430

470_0402_5%

Q33
2N7002_SOT23-3

+5VS +3VS

2

G

12

R429

470_0402_5%

13

D

Q32
2N7002_SOT23-3

S

12

R428

470_0402_5%

13

2

G

D

Q31
2N7002_SOT23-3

S

SUSP SUSP SYSON# SUSP S USP SUSP SUSP

4 4

2

G

+1.5VS

12

13

R431

470_0402_5%

D

Q34
2N7002_SOT23-3

S

+1.25VS +VCCP +0.9V

12

R432

470_0402_5%

13

D

Q35

2

G

2N7002_SOT23-3

S

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2006/02/13 2006/07/26

Compal Secret Data

Deciphered Date

Title

Size Doc ument Number Re v

D

Date: Sheet of

Compal Electronics, Inc.

DC/DC Interface

LA-3821P

33 43Tu es day , J ul y 3 1, 20 07

E

0.3

A

1 1

2 2

B

C

D

VIN

PC N1

1

2

G
G

3

A DPIN

12

SINGA _2DC-S 756B200

PC1

100P_04 02_50V8J

3 3

4 4

A

PL1

SMB 3025500YA_2 P

1 2

12

PC2
1000P_0 402_50V7K

12

12

PC 4

PC 3

1000P _0402_50V7K

100 P_0402_50V8J

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

B

<Issued_Date> <Deciphered_Date>

Compal Secret Data

Deciphered Date

C

Title

Size D ocum ent Nu mber R ev

Cu stom

Da te: S heet o f

DC CONN

LA-3821P

D

34 43Tue sday, July 31, 20 07

A

3
2
16

PC 6

7

P2

12

PR 24

1 2

1K_ 0402_5%

12

PR 31
10K _0402_5%

+5VALW

0

3
2
1 6

12

PR 2
200K _0402_5%

0.22 U_060 3_16V7K

PR 7
150K _0402_5 %

1 2

PA CIN

PR 37
10K _0402_5%

1 2

PU 4B
LM3 58ADT_SO8

8

5

P

+

6

-

G

4

PQ2

FDS 4435B Z_SO8

4

MB3 9A126

12

PC 15

0.01 U_040 2_25V7K

IR EF 32

ACIN 32

PACIN 36

8
7

5

PR 11
10K _0402_1%

1 2

12

PR 14

10K _0402_1%

1 2

PR 21

150K _0402_1 %

1

V IN

PR 1

47K _0402_5%

12

1 1

PR 4
47K _0402_1%

1 2

2 2

V IN

12

PR 22

2.15 K_040 2_1%

1 2

12

12

PR 30

PC 26

0.04 7U_04 02_16V7K

3 3

13

D

2

G

S

RHU0 02N06 _SOT 323-3

PA CIN

AC OFF #

133K _0603_1 %

PR 28

10K _0603_0 .1%

12

PC 28

22P _0402_25V 8K

PC 5

PQ6

1 2

47P _0402_5 0V8J

2

3

+

2

-

13

DTC 115EU A_SC7 0-3

PR 10

1 2

3K_ 0402_5%

PD 1

RLS 4148_ LLDS2

1 2

PR 16

1 2

1M_ 0402_5%

P2

12

PR 20
47_1 206_5%

12

8

PU 2A

P

1

O

G

LM3 93DG_SO 8

4

PR 32

1 2

49.9 K_040 2_1%

4

REF

5

ANODE

LMV431 ACM5X_SO T23-5

2

PQ5

PC 22

0.1U _0603 _25V7K

P2

PU 3

CATHODE

+3VALW

12

PR 38

47K _0402_1%

13

PQ14

4 4

FS TCHG32

2

DTC 115EU A_SC7 0-3

13

D

2

G

S

A

8
7

5

PQ4

DTA 144EU A_SC70-3

1 3

2

G

PD 5

3

2

NC

1

NC

CS

PQ13
RHU0 02N06 _SOT 323-3

PQ1
FDS 4435B Z_SO8

4

13

D

PQ9
RHU0 02N06 _SOT 323-3

S

V IN

12

PR 23

10K _0402_1%

3.2V

12

RLZ 4.3B_ LL34

1. 24VRE F

BATT_OVP32

AD P_I3 2

0.22 U_060 3_16V7K

12

PR 15

30K _0603_1%

12

PC 17

0.22 U_060 3_16V7K

8

0

4

B

PC 11

PC 12
4700 P_0402_ 25V7K

1 2

VREF

MB3 9A126

12

PR 25

100K _0402_1 %

+5VALW

12

3

P

+

2

-

G

PU4 A

LM35 8ADT_SO8

B

1 2

PR 18
1K_ 0402_1%

1 2

12

PC 29

0.01 U_040 2_25V7K

PR 8

10K _0402_5%

PR 12
100K _0402_1 %

PC 18
2200 P_0402_ 50V7K

1 2

PC 23

1U_0 603_6. 3V6M

12

PR 33

340K _0402_1 %

12

PR 35

499K _0402_1 %

12

PR 39

105K _0402_1 %

P4

BATT

12

12

PR 26
10K _0402_1%

12

PR 5

1 2

0.02 _2512 _1%

PU 1

MB3 9A126P FV-ER_S SOP24

1

ADP _I_A

2

3

4

5

6

7

8

9

12

10

11

12

RHU0 02N06 _SOT 323-3

PQ12

PC 30

0.01 U_040 2_25V7K

C

B+

PL2
SMB 302550 0YA_2P

1 2

12

PC 8

PC 7

0.1U _0603 _25V7K
2200 P_0402_ 50V7K

12

PR 29

100K _0402_1 %

BATT_DET 40

Compal Secret Data

12

1 2

1 2

12

CHG _B+

+INC2

GND

XACOK

-INE3

FB123

+INC1

CS

VCC

OUT

VH

RT

CTL

24

23

22

21

20

PC 16

0.1U _0603 _25V7K

19

18

17

16

MB3 9A126

15

14

13

-INC2

OUTC2

+INE2

-INE2

ACOK

VREF

ACIN

-INE1

+INE1

OUTC1

SEL

-INC1

+3VALW

PR 34

100K _0402_5 %

1 2

13

D

2

G

S

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

12

PR 13

0_04 02_5%

PC 13

0.22 U_060 3_16V7K

1 2

PR 19
47K _0402_1%

1 2

PR 27
33K _0402_1%

+3VALW

1 2

CS

1 2

PC 25
10P _0402_5 0V8J

1 2

PR 36

100K _0402_5 %

1 2

PC 14

0.1U _0603 _25V7K

1 2

PC 24

1500 P_0402_ 50V7K

1 2

CV=12.6V (6/12 CELLS LI-ION)
CC=3.08A (6/12 CELLS LI-ION)

C

PQ3

FDS 6675B Z_SO8

1
2
3 6

12

PC 9

PC 10

4.7U _1206 _25V6K

4.7U _1206 _25V6K

16

578

PD 3

FS TCHG

RB7 51V- 40_SOD32 3-2
PD 4

RB7 51V- 40_SOD32 3-2

PC 27
47P _0402_5 0V8J

1 2

Deciphered Date

8
7

5

4

CHG_B+

243

PQ11

FDS 4435B Z_SO8

PL3

1 2

12

16UH _SIL 104R- 160P F_3.6A_3 0%

PD 2

EC3 1QS04

SUS P# 23, 32,33 ,37,38

AC OFF #

PR 9
100K _0402_5 %

+3VLP

PA CIN

PQ10

RHU0 02N06 _SOT 323-3

1 2

0.02 _2512_1 %

D

BATT

PR 3

1 2

47K _0402_5%

PR 6
10K _0402_5%

1 2

13

13

D

2

12

2

G

PR 17

Title

Size D ocum ent Numbe r Rev

Cu sto m

Da te: Sheet o f

PQ7

G

S

13

D

S

RHU0 02N06 _SOT 323-3

12

12

PC 19

PC 20

10U_ 1206_25V 6M

10U_ 1206_25V 6M

Compal Electronics, Inc.

Charger

Tu esda y, J uly 31, 2 007

D

VI N

PQ8

DTC 115EU A_SC7 0-3

2

12

PC 21

10U_ 1206_25V 6M

AC OFF 32

BATT

4335

A

B

C

D

E

PR43
0_0402_ 5%

1 2

PC3 2

0.1U _0603_50 V4Z

1 2

B++

12

PC 35

2200P _0402_50V7K

PR 48

0_040 2_5%

1 2

PQ22
TP0610K-T1-E3_ SOT23

1 3

2

12

PC 36

4.7 U_1206_25V 6K

DH_ 3.3V_B

100K_04 02_5%

1 2

PR6 2

578

3 6

578

PQ16
AO4466_ SO8

241

3 6

241

+3VLP

PQ18
AO4466_ SO8

12

PL6

10U _LF919 AS-100M-P3_4.5A_ 20%

+3VALWP

PR 55

1

1 2

+

@3. 57K_0402_1%

PC 44

2

PR 59

1 2

150 U_D2_6.3V M

0_040 2_5%

PC3 1

0.1 U_0603_25V 7K

0.1U _0603_50 V4Z

578

PQ15
AO4466_ SO8

3 6

241

578

PQ17
AO4466_ SO8

3 6

241

VL

PR5 6

499K_06 03_1%

1 2

DH_ 5V_B

PC1 21

@0.1 U_0402_16V 7K

2VREF_1999

MAINP WON

12

12

PC4 6

0.04 7U_0603_1 6V7K

PR4 0

0_0402_ 5%

1 2

12

PR5 0

1 2

0_0402_ 5%

PR5 2

1 2

@0_040 2_5%

1 2

PR53

@10K_04 02_5%

2VREF_1999

MAINP WON 40

D

S

PR4 2
0_0402_ 5%

1 2

BST_5V

DH _5V

LX_5V
DL_ 5V

12

PR 57

1 2

300K_ 0402_5%

12

PQ19

13

2

G

RHU 002N06 _SOT323-3

13

D

S

2

3

PD6
CHP 202UPT_SOT 323-3

1

B++

VL

1

PC 38

2

4.7 U_0805_ 10V4Z

14

16

15
19
21

9
1

6
4
3

12

8

PC 43

0.2 2U_0603_10 V7K

PU5

BST5

DH5

LX5
DL5
OUT5
FB5
N.C.

SHDN#
ON5
ON3

SKIP#

REF

20

18

LD05

GND

23

PC 45

VL

PR60
100K_04 02_5%

2

G

PQ20

RHU 002N06 _SOT323-3

12

PC 39

V+

LDO3

25

1

2

4.7 U_0805_ 10V4Z

PA CIN 35

BST_3.3V _BBST_5V_ B

VL

1 2

0.1 U_0603_ 50V4Z

13

17

ILIM3

TON

VCC

ILIM5

BST3

OUT3

PGOOD

PRO#

10

+3VLP

1 2

12

PC3 7

47_04 02_5%

0.1U _0603_16V7 K

PR 41

2VREF_1999

12

PC 40

1U_ 0805_16V7K

5

11

BST_3.3V

28

DH _3.3V

26

DH3

DL_ 3.3V2VR EF_1999

24

DL3

LX_3.3V

27

LX3

22

7

FB3

2

RT8203P A_SSOP_28P

PR58
0_0402_ 5%

13

D

2

G

PQ21

S

RHU 002N06 _SOT323-3

PR44
0_0402_ 5%

1 2

PR4 6

1 2

@499 K_0402_1%

100K_04 02_1%
PR4 5

1 2

PR 47

1 2

499K_ 0402_1%

PR6 1
100K_04 02_5%

1 2

PL4

HCB 2012KF-121 T50_0805

B+

1 1

2 2

3 3

12

B++

12

12

PC 33

PC 34

10U_1 206_25V6M

2200P _0402_50V7K

4.7U _LF91 9AS-4R7M-P 3_5.2A_20%

PL5

+5VALWP

1

1 2

+

PC 41

2

220 U_6.3VM_R 15

1 2

12

PR 49

@10 .2K_0402_1%

PR 54

0_040 2_5%

B++

12

PR 51

47K_0 402_5%

12

PC 42

RTC Charger Circuit
2007/04/20

PR1 57

560_060 3_5%

1 2

+CH GRTC

1 2

PR1 58
560_060 3_5%

+3VL

BATT1.1

BATT1

W=20 mils

4 4

A

+ -

1 2

@ML1220 T13RE

45@

51ON#30

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

<Issued_Date> <Deciphered_Date>

C

Compal Secret Data

Deciphered Date

Title

Size D ocum ent Nu mber R ev

D

Da te: S heet o f

Compal Electronics, Inc.

3.3VALWP / 5VALWP

Tu esday, July 31, 2 007

E

4336

5

4

3

2

1

25

7

8

9

10

11

12

PC 59

B+++

PR 64

10.2 K_06 03_0.1%

1 2

PR 67

0_04 02_5%

6

PU 6

VO2

P PAD

PGOOD2

EN2

VBST2

DR VH2

LL2

DR VL2

PGND2

13

PR 74

18.2 K_040 2_1%

1 2

12

PR 76

3.3_ 0402_5%

5

VFB2

14

1 2

3

4

GND

TONSEL

V5IN16TRIP2

15

12

12

75K _0402_1%

2

12

PC 60

4.7U _0805 _10V6K

PR 65

1 2

VFB1

PGOOD1

TRIP117V5FILT

PR 75

15.4 K_04 02_1%

73.2 K_040 2_1%

1

VO1

24

23

EN1

22

VBST1

UG_ 1.5V

21

DR VH1

20

LL1

19

DR VL1

PGND1

TPS 51124 RGER _QFN2 4_4x4

18

+5V ALWP

PR 66

1 2

BS T_1.5V

LX_1.5V

LG_ 1.5V

PR 71

0_04 02_5%

UG1 _1.5V

1 2

PR 72

0_04 02_5%

1 2

0.1U _0603 _25V7K

1 2

0_04 02_5%

12

PR 78

PC 61
@10 00P_040 2_50V7K

PC 52

1 2

PQ24

8

G2

D2

7

D2

D1/S2/K

6

G1

D1/S2/K

5

D1/S2/K

S1/A

SP8 K10S FD5 2N SO P8

SUSP# 23,32,3 3,35,38

1
2
3
4

PL16

1 2

3.3U H_SI QB74 -3R3R F_4. 8A_30%

4.7U _0805 _6.3V6K

PC 54

+1.5VSP

12

12

12

PC 51

PC 50

4.7U _1206 _25V6K

@22 00P_04 02_50V7K

1

+

PC 55

2

220U _6.3V M_R15

PL7

HCB 2012K F-121 T50_0805

1 2

B+

12

12

PC 47

D D

C C

680P _0402_50V 7K

+1.8VP

1

12

+

PC 56

2

220U _6.3V M_R15

3.3U H_PC MC06 3T-3R 3MN_6A_20 %

PC 57

0.1U _0402 _16V7K

12

PC 48

2200 P_0402_ 50V7K

12

PC 49

10U_ 1206_25V 6M

578

PQ23

AO4 466_SO8

3 6

241

PL9

12

12

PC 58

0.1U _0402 _16V7K

PR 88

4.7_ 1206_5%

FDS 6690A S_NL_S O8

12

PC 76

680P _0603_50V 7K

SYSON23,32,3 3

PQ25

578

3 6

241

1 2

UG1 _1.8V

PR 77

0_04 02_5%

PR 68

0_04 02_5%

1 2

PR 73

PC 53

0_04 02_5%

1 2

12

0.1U _0603 _25V7K

LG_ 1.8V

PR1 60

100K _0402_5 %

12

PR 63

14.3 K_06 03_0.1%

1 2

BS T_1.8V

UG_ 1.8V

LX_1.8V

1U_0 603_10V 6K

B B

V_DDR_MCH_REF7,13,14

SYSON#29,33

SUSP33

A A

5

4

PC 62

10U_ 0805_ 10V4Z

1 2

PR 80

@0_ 0402_5%

RHU0 02N06 _SOT 323-3

1 2

PR 82

0_04 02_5%

+1.8 V

12

12

PC 67
@0. 1U_04 02_16V7K

PU 7

VIN1VCNTL

12

12

PC 63

PR 79

1K_ 0402_1%

@10 U_080 5_10V4Z

PQ26

2

12

PR 81

13

D

G

1K_ 0402_1%

S

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

GND

3

VREF

4

VOUT

G29 92F1U _SO8

12

12

PC 66
10U_ 1206_ 6.3V7K

0.1U _0402 _16V7K

PC 65

2006/11/23 2007/11/23

+0.9VP

6

5

NC

7

NC

8

NC

9

TP

Compal Secret Data

Deciphered Date

2

12

PC 64
1U_0 603_16V 6K

+5VALW

Title

Size D ocum ent N umber R ev

Da te: Sheet o f

Compal Electronics, Inc.

1.8VP/0 .9VP/1.5VSP

LA -38 21P

1

37 43Tu esday , Ju ly 3 1, 20 07

0. 2

5

PL10

HCB 1608K F-121 T30_0603

B+

D D

1.0 5V_B+

12

12

PC 69

10U_ 1206_25V 6M

12

PR 83

10_0 402_5%

4

PR 84

1M_ 0402_5%

PC 70

1000 P_0402_ 50V7K

3

+5V ALWP

578

3 6

241

PQ27
AO4 466_SO8

12

PD 7

12

1SS 355_SO D323-2

1 2

2

1

SUSP#2 3,32,33,35,37

VCCP_POK

C C

B B

PJP 1

+5V ALWP

+3V ALWP

+1.8 VP

+1.0 5V_V CCP

+1.5V SP

+0.9V P

A A

1 2

PAD -OPE N 4x 4m
PJP 3

1 2

PAD -OPE N 4x 4m

PJP 5

1 2

PAD -OPE N 4x 4m

PJP 6

1 2

PAD -OPE N 4x 4m

PJP 7

1 2

PAD -OPE N 4x 4m

PJP 8

1 2

PAD -OPE N 3x 3m

1 2

PR 85

0_04 02_5%

1U_0 603_1 0V6K

PR 90

0_04 02_5%

+5V ALW

(3A,12 0mils , Via NO. = 6)

+3V ALW

(7A,28 0mils , Via NO. = 14)

+1.8 V

(6A,24 0mils , Via NO. =12)

+V CCP

(6A,24 0mils , Via NO. =12)

+1.5 VS

(2A,80 mils ,V ia NO.= 4)

+0.9 V

@22 00P_040 2_25V7K

PC 74

12

12

PC 72

12

+1.25 VSP

+3VLP +3VL

12

PR 87

10K _0402_1%

PU 8

1

VOUT

2

VCCA

3

FB

4

PGD

17

PJP 2

1 2

PAD -OPE N 3x 3m

PJP 4

2 1

PAD -OPE N 2x 2m

BOO T_1.05V

PR 86

1 2

0_04 02_5%

13

14

15

16

NC

BST

TON

EN/PSV

NC5VSSA

TP

6

12

12

DH

11

LX

10

ILIM

9

VDDP

PGND7DL

SC411M LTRT_MLPQ 16_4X4

8

PR 91

1 2

11K _0402_1%

1 2

PC 78
33P _0402_5 0V8J

PR 92
10K _0402_1%

(500mA ,40mils ,Via N O.= 1)(4.5A, 180mils ,Via N O.= 9)

+1.2 5VS

LX_1. 05V

PR 89

1 2

21K _0402_1%

BOO T1_1.05V

12

PC 77
1U_0 603_10V 6K

1 2

PC 71

0.1U _0402 _16V7K

(100mA ,20mils ,Via N O.= 1)

UG_ 1.05V

LG_ 1.05V

578

3 6

241

SUSP#23,32 ,33,35,37

PQ28
FDS 6690A S_NL_ SO8

1 2

PR 93

@0_ 0402_5%

2.2U H_PC MC06 3T-2R 2MN_8A_20 %

1 2

1 2

PR 94

12

0_04 02_5%

PC 81

@0. 01U_0 402_16V7K

PL11

6

PU 9

7

8

VIN

POK

VIN

VCNTL

VOUT

EN

VOUT

FB

GND

1

APL 5913-K AC-TRL_S O8

+5V ALWP

12

PC 79
1U_0 603_6. 3V6M

5

9

3

4

2

33.2 K_040 2_1%

59K _0402_1%

PR 95

PR 96

1

+

2

12

12

PC 73

220U _V_4VM _R25M

12

PC 83
47P _0402_5 0V8J

PC 75

4.7U _0805 _6.3V6K

1 2

+1.5V S

12

12

PC 82
22U_ 1206_ 6.3V6M

PC 80
10U_ 1206_ 6.3V6M

+1.25VSP

+1.05V_VCCP

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

<Issued_Date> <Deciphered_Date>

Compal Secret Data

Deciphered Date

2

Title

Size D ocum ent N umber R ev

Da te: Sheet o f

Compal Electronics, Inc.

1.05V_VCCP/2.5VSP

LA -38 21P

1

38 43Tu esday , Ju ly 3 1, 20 07

0. 2

5

4

3

2

1

+5VS

12

4700P _0402_25V7K

+VCC_C ORE

B+

PC90

1000P _0402_50V7K

5

5

32

CPU _VID55CPU _VID35CPU _VID4

CPU _VID6

VR_ ON

D D

DPR SLPVR7,2 0

H_DPR STP#5,7, 19

CLK_E NABLE#

+3VS

+3VS

PR111

499_0 402_1%

1 2

VGATE15,20

H_P SI#5

PR159

PGD _IN

C C

@0_0402_5%

VR_TT#

1 2

PR119 14 7K_0402_1%

1 2

PC990.022U _0603_25V7K

PR121 13K_ 0402_1%

1 2

1 2

1 2

PC1001000P_0 402_50V7K

PR124 6. 81K_0402_1%

1 2

1 2

PC102 10 00P_0402_50V7K

1 2

1 2

PC104

12

470P_ 0402_50V7K

PR130 97 .6K_0402_1%

PC107 220P _0402_50V7K

PR134

1 2

PC108 10 00P_0402_50V7K

1 2

255_0 402_1%

B B

1 2

PR136 1K _0402_1%

VCC SENSE5

VSSSE NSE5

VCC _PRM

PR98 4 99_0402_1%

PR100 0_04 02_5%

1 2

PR106 0_04 02_5%

1 2

12

PC91

PR112

1U_06 03_6.3V6M

1.91K_ 0402_1%

1

2

3

4

5

6

7

8

9

10

11

12

PR131

1 2

@0_04 02_5%

PC110 82 0P_0603_50V7K

1 2

12

PC111
@0.0 22U_0603_50V 7K

PC113 18 0P_0402_50V8J

1 2

PR143 1K _0402_1%

PC115

0.22U _0603_10V7K

1 2

PR99 0 _0402_5%

1 2

12

49

GND

PGOOD

PSI#

47

48

3V3

CLK_EN#

PR101

PR107

12

12

0_040 2_5%

43

44

45

46

VR_ON

DPRSTP#

DPRSLPVR

PMON

RBIAS

VR_TT#

NTC

SOFT

OCSET

ISL626 2ACRZ-T _QFN48_7X7

VW

COMP

FB

FB2

VDIFF13VSEN14RTN15DROOP16DFB17VO18VSUM19VIN20GND21VDD22ISEN223ISEN1

12

1K_04 02_1%

PR133

12

PC112

0.01U _0603_50V7K

1 2

1 2

PR144 4. 42K_0402_1%

12

PC114 0. 1U_0402_ 16V7K

1 2

PC116 0. 22U_0402 _6.3V6K

0_040 2_5%

12

PR102

12

0_040 2_5%

PR103

PR108

PR104

12

12

0_040 2_5%

0_040 2_5%

1 2

12

PC109

0.1U_ 0603_25V7K

PR139

12

PR142

11K_0 402_1%

12

0_040 2_5%

12

10_06 03_5%

12

1 2

5

CPU _VID05CPU _VID15CPU _VID2

PR105

PR109

12

12

0_040 2_5%

0_040 2_5%

VID037VID138VID239VID340VID441VID542VID6

36

BOOT1

35

UGATE1

34

PHASE1

33

PGND1

32

LGATE1

31

PVCC

30

LGATE2

29

PGND2

28

PHASE2

UGATE2

BOOT2

1 2

PC105

1U_04 02_6.3V4Z

27

26

25

NC

PU10

24

ISE N1
ISE N2

PR132 1_ 0603_5%

UGAT E_CPU2-1

PR135

CPU_B+

VSUM

2.61K_ 0402_1%
10KB_ 0603_5%_ ERTJ1VR103J

PH2

0.022 U_0402_16V7K

BOOT _CPU1

UGAT E_CPU1-1

PHA SE_CPU1

LGATE _CPU2

PHA SE_CPU2

BOOT _CPU2

1 2

PR123

0_0603_5%

+5VS

12

PC84

0_0603_5%

PR110

1 2

1 2

2.2_0 603_5%
PR113

LGATE _CPU1

PR122

1 2

2.2_0 603_5%

1 2

PC101

0.22U _0603_10V7K

PR97
1_060 3_5%

1 2

12

PC85

2.2U_ 0603_6.3V 6K

0.22U _0603_10V7K
PC92

1 2

UGAT E_CPU2-2

UGAT E_CPU1-2

5

D8D7D6D

S1S2S3G

4

5

4

1

12

5

PQ29

D8D7D6D

SI4684 DY-T1-E 3_SO8

S1S2S3G

12

+

PC86

PC123

PC124

2

4700P _0402_25V7K

4700P _0402_25V7K

4

0.36U H_PCMC 104T-R36 MN1R17_30A_20%

5

PQ30

4

FDS66 76AS_SO8

PR114

D8D7D6D

PQ31

S1S2S3G

6.8_12 06_5%

12

PC93

FDS66 76AS_SO8

12

12

PR115

3.65K_ 0805_1%

VSUM

680P_ 0603_50V8J

5

PQ32

D8D7D6D

SI4684 DY-T1-E 3_SO8

S1S2S3G

4

12

5

D8D7D6D

S1S2S3G

D8D7D6D

PQ33

S1S2S3G

4

FDS66 76AS_SO8

PR125

6.8_1 206_5%

PQ34

12

PC103
680P_ 0603_50V8J

FDS66 76AS_SO8

12

12

PC96

PC95

10U_1 206_25V6M

10U_1 206_25V6M

12

PR126

VSUM

CPU_B+

12

12

PC87

10U_1 206_25V6M

PC89

PC88

2200P _0402_50V7K

10U_1 206_25V6M

47U 25 V M 6.3X6 ESR0.44 C E-LX

12

12

PL13

PR116

PR118 @ 0_0603_5%

10K_0 402_1%

1 2

PC94

1 2

ISE N1

0.22U _0603_10V7K

12

12

12

PC98

0.36U H_PCMC 104T-R36 MN1R17_30A_20%

PC125

2200P _0402_50V7K

4700P _0402_25V7K

PL14

12

PR127

10K_0 402_1%

PR129 @0_ 0603_5%

3.65K_ 0805_1%

1 2

PC106

1 2

0.22U _0603_10V7K

ISE N2

PL12

SMB3 025500YA_2P

12

12

PC127

1000P _0402_50V7K

12

PR117

1_0402_5%

VCC _PRM

CPU_B+

12

PC126

PC128

4700P _0402_25V7K

1000P _0402_50V7K

12

12

PR128

1_0402_5%

VCC _PRM

12

12

PC122

A A

Compal Electronics, Inc.

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

+CPU_CORE

Size D ocum ent Num ber R ev

Cus tom

Dat e: Sheet o f

39 43Tues day, July 31 , 2007

1

0.2

A

PC N2

7

BATT+

SMD
SMC

ID

B/I

9

TS

1 1

G

8

GND

G

SUYIN_ 20027 5MR007 G113ZL

6
5
4
3
2
1

EC_ SMD
EC_ SMC

PR1 56

1K_0402 _5%

100_040 2_5%

PR148

3

2

6.49 K_0402_1%

1 2

12

PR1 47
1K_0402 _5%

BATT_DET 35

PD8 @SM05 _SOT23

1

PR1 46

@1K_040 2_5%

12

12

12

PR149
100_040 2_5%

PCN2 battery connector

SMA

SMA RT

RT

SMASM A

RTRT

Ba t te

Ba t te r y:

ry :

Ba t teB at t e

ry :ry :

7.

7. BATT +

BA T T+

7.7.

BA T T+BAT T+

6.

6. S MD

SMD

6.6 .

SMDS M D

5. S M C

5. S M C

5. S M C5. S M C

4.

4. I D

ID

4.4 .

IDI D

3. B /I

3. B /I

2 2

3. B /I3 .B /I

2.TS

2.TS

2.TS2. T S

1.

1. G N D

GND

1.1 .

GNDG ND

PR1 45

+3VL

SMB _EC_DA1

SMB _EC_CK1

12

B

2

3

1

PD9
@SM24.TC _SOT23-3

BATT_TEMP 32

12

PC1 17
@1000P_ 0402_50V7K

SMB _EC_DA1 3 1,32

SMB _EC_CK1 3 1,32

BATT

12

PC118
@0.0 1U_0402 _50V4Z

C

D

PH3 under CPU botten side :

CPU thermal protection at 90 +-3 degree C
Recovery at 47 +-3 degree C

+5VS

CPU

3 3

12

PC1 19

0.22 U_0603_10V 7K

4 4

12

PH3

10K _TH11-3H103 FT_0603_1%

PR152

15K_060 3_1%

1 2

+5VS

12

PR154

2.55 K_0603_1%

1 2

PR1 53

150K_04 02_1%

150K_04 02_1%

PR155

12

12

PC1 20

1000P_0 402_50V7K

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

B

<Issued_Date> <Deciphered_Date>

PR1 50

47K_040 2_1%

1 2

8

PU2 B

5

P

+

7

O

6

-

G

LM393DG _SO8

4

Compal Secret Data

Deciphered Date

C

+5VS

PR1 51
10K_040 2_5%

1 2

MAINPWON 36

13

D

2

G

Title

Size D ocum ent Nu mber R ev

Cu stom

Da te: S heet o f

PQ35
RHU 002N06 _SOT323-3

S

Compal Electronics, Inc.

BATTERY CONN

LA-3821P

D

40 43T uesd ay, Ju ly 31 , 2007

5

4

3

2

1

Version change list (P.I.R. List) Page 1 of 1

Reason for change PG# Modify List PhaseItem

D D

1

RT8203 cr osstalk issue

2

PU6 pin8 add a resistor to GND

3

remove PL15 remove PL15 2007/06/12

4

C C

EMI request

37 a dd PC1 21 and 0.1uF

38 a dd PR1 60 100K_ohm

36

39

Power section

Date

2007/05/24

2007/05/24

add PC122 ,PC 123 ,PC124,PC125,PC126,PC127,PC128 2007/07/23

SI

SI

SI

PV

5

6

7

8

B B

9

10

11

12

13

A A

14

Compal Electronics, Inc.

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

PWR PIR

Size Doc ument N umber R ev

Cu stom

Dat e: Sheet o f

41 43T uesd ay, Ju ly 31, 20 07

1

0.2

5

4

3

2

1

Version change list (P.I.R. List) Page 1 of 1

Reason for change PG# Modify List PhaseItem

1

D D

2

Change Board ID 32 R407 from 0 Ohm to 8.2K,R405 install 100K 20 07/05/30 SI

3

USB power switch fail 29 U23 & U17 ch ang e pin 4 from SLP_S5# to SYSON# 2007/05/30 SI

4

FAN use v oltage control 4 de l U 2,Q1;add U24,C13 for 3 pin FAN

5

USB JP24 fail 29 Change pin define

6

Speaker output fail 28 Add R457,R458,R459 for Line_out 2007/05/30 SI

7

MS Pro fail 26 Add MS_D1 ,MS_D2,MS_D3 net 2007/06/06 SI

8

WLAN LED fai l when disable WLAN 30 Add R232 pull high +5VS 2007/06/06 SI

C C

9

+3VALW leakage 30 Del R387 2007/06/06 SI

10

11

XDP fail 15 2007/06/06 SI

12

LAN power co nsu mption is too large when S3 24 2007/06/14 SI

13

RJ11' cap is duplicate MDC module. 25

32 ACIN add 100P (C505) to GND 2007/05/30 SIEC team request

Power section

Add net C AP_ RES ET for Capacitor board reset

XDP clock sh are in robeson card

Add Q22

Date

2007/05/30

2007/05/30

2007/06/14 SIDelete C378,C379

SI

SI

SI2007/06/0632Capacitor board fail

14

Reverse s ome re sister for tring ENE cap board 30 32

15

+LCDVDD o ver current when diplay.

B B

16

LAN fail 24 2007/06/06 SI

17

18

19

20

20

21

A A

22

WLAN LED (Amber led) issue 30 WLAN LED need change from +5VS to +3VS 2 007 /07/23 PV

030 proje ct Bluetooth module issue 29 Swap pi n5 & pin7 2007/07/23 P V

change Ca p b oar d LED supply voltage 30 from +3VS to +5VS 2007/07/23 PV

CMOS timi ng can't reset SHOR T P AD (CL RP3) connect between +RTCVCC

EMI issue (CPU core) 5 add C43 & C44 (330U) 2007/07/23 P V

EMI/ESD iss ue (XDO connector) 4 delete XDP connector 2007/07/23 PV

EMI/ESD iss ue (RJ11 connector) 25 a dd 1000P at RJ11 RING & TIP 2007 /07/23 PV

5

4

17 Change R1 63 from 47K to 100K 200 7/06/21 SI

19

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

Add R460~R468,R451 2007/06/14 SI

Change C2 48 from 0.1U to 0.22U

Change JP 14 pin define

2007/07/23

and GND

Compal Electronics, Inc.

Title

PWR PIR

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

Size Doc ument N umber R ev

Cu stom

Dat e: Sheet o f

PV

42 43T uesd ay, Ju ly 31, 20 07

1

0.3

5

4

3

2

1

Version change list (P.I.R. List) Page 1 of 1

Reason for change PG# Modify List PhaseItem

23

D D

24

monitor w ave riple issue 10 2007/07/25 P Vadd C508

25

C C

MIC issue for EMI solution 28 add L20, L21, L22, L23, C509, C510 20 07/ 07/31 PV

26 change C3 93, C394 from 27p to 5.6p 200 7/07/25 PVcar d r ead er RTL5158 chip issue

Power section

Date

B B

A A

Compal Electronics, Inc.

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

PWR PIR

Size Doc ument N umber R ev

Cu stom

Dat e: Sheet o f

43 43T uesd ay, Ju ly 31, 20 07

1

0.3