COMPAL LA-3751P Schematics

5

COMPAL CONFIDENTIAL

4

3

2

1

MODEL NAME :
PCB NO :

D D

BOM P/N :

LA-3751P (DA800008Y0L)

46149031L0121

IAQ20

Converse

C C

uFCPGA Mobile Merom
Intel Crestline + ICH8M

21-05-2007

REV : 0.1(X00)

B B

@ : Nopop Component

A A

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, M/B LA-3751P

401490

148Wednesday, March 28, 2007

1

A

of

5

Compal confidential

4

3

2

1

Pentium-M

Merom -4MB (Socket P)

uFCPGA CPU

D D

NB8E-GLM-A2 G84

DVI CONN.

+5V_RUN

page 18

DVI

VGA BOARD

with LVDS CONN.

LS-3751P

RGB and TV OUT

VGA CONN.

page 18

CRT CONN.

PCIE 16X

& TV-OUT

Docking

C C

Port

page 34

USB7

IDSEL:AD17
(PIRQA/B#,GNT#2,REQ#2)

Memory Card &1394
Controller
RICOH R5C833P

+3.3V_R5C833

5 in 1 CONN.

B B

page 30 page 30

+5V_RUN

Docking Buffer

+5V_RUN

page 30

1394 CONN.

USB6

Smart Card
OZ77CR6

page 32

page 33

3.3V 33MHz

Express
Card

USB2

MINI

ROBSON

page 31

Slot

page 32

Biometric Reader

page 32

A A

page 19

MINI

WLAN

page 31page 32

GIGA Enthernet

BCM5756MKFBG

+3.3V_LAN
+2.5V_LAN
+1.2V_LAN

RJ45 with
Giga Magnetic

+2.5V_LAN

ST M25P16

+3.3V_ALW

page 36

Touch Pad Int.KBD

SPI

+1.05V_VCCP
+VCC_CORE

H_A#(3..35) H_D#(0..63)

478pin

System Bus

FSB 800 MHz

INTEL

+1.25V_RUN
+1.5V_RUN
+1.8V_SUS
+1.05V_VCCP
+3.3V_RUN
+1.8V_RUN

PCI BUS

PCIE BUS

page 28,29

page 29

MEC5025

+RTC_CELL
+3.3V_ALW

Crestline

1299pin BGA

DMI

+1.5V_RUN
100MHz

ICH8-M
676 BGA

Intel 82801HBM

+1.25V_RUN
+3.3V_RUN
+3.3V_SUS
+1.05V_VCCP

page 20,21,22,23

LPC BUS

+3.3V_RUN 33MHz

page 36

ECE5028
Super I/O

BC BUS

ECE1077

+3.3V_ALW

page 37 page 37page 37

page 7,8,9

page 10,11,12,13,14

Azalia

SATA
PATA

48MHz / 480Mb

page 35

Multi-media

Board

Switch Board

LED Board

LS-3752P LS-3753P

5

Bluetooth

+3.3V_RUN

4

page 32
USB3

LS-2884P

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

Clock Generator
CK505

+3.3V_RUN

Memory BUS (DDR2)

+1.8V_SUS 667MHz

CDROM

+5V_RUN

page 24

USBPORT 0
USBPORT 1
USBPORT 2
USBPORT 3

USB2.0
IO PORT

page 27

USBPORT 4
USBPORT 5
USBPORT 6
USBPORT 7
USBPORT 8
USBPORT 9

page 6

SATA HDD

+5V_HDD

page 24

Ext. USB
Ext. USB
EXPRESS CARD
BLUETOOTH
Ext. USB
Ext. USB
OZ77CR6
Docking
Ext. USB
Ext. USB

2

Fan Control

+3.3V_RUN

page 15

DDRII-DIMM X2

BANK 0, 1, 2, 3, 4 ,5 ,6 ,7 ,8

+0.9V_DDR_VTT
+1.8V_SUS

MDC

page 25 page 25

Azalia Codec

STAC9205

+3.3V_RUN
+VDDA

AMP & INT.
Speaker

+5V_RUN

page 26 page 26

Thermal

GUARDIAN III

SMBus

EMC4001

+3.3V_SUS

page 16,17

page 15

RJ11

DC IN &

page 25

HeadPhone
& MIC Jack

+3.3V_RUN

BATT CONN

page 41

3.3V/5V/15V

page 42

1.8V /0.9V/1.25V

page 43

1.5V/1.05V

VCORE

CHARGER

page 44

page 45

page 46

DELL CONFIDENTIAL/PROPRIETARY

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, M/B LA-3751P

401490

248Wednesday, March 28, 2007

1

of

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POWER STATES

State

D D

S0 (Full ON) / M0

S3 (Suspend to RAM) / M1

S4 (Suspend to DISK) / M1 ON ON ON ONOFF

S5 (SOFT OFF) / M1 ON ON ON ONOFFLOW HIGH LOW HIGHLOW

S3 (Suspend to RAM) / M-OFF

S4 (Suspend to DISK) / M-OFF

S5 (SOFT OFF) / M-OFF

Signal

SLP
S3#

HIGH

LOW HIGH HIGH HIGH ON ON ON ONOFF

LOW HIGH HIGH HIGHLOW

LOW HIGH HIGH HIGH LOW ON ONOFF OFF OFF

LOW LOW LOW LOW ON OFF OFF OFF OFF

LOW LOW LOW LOW LOW ON OFF OFF OFF OFF

SLP
S5#

HIGH

S4
STATE#

SLP
S4#

HIGH HIGH HIGH

SLP
M#

HIGH

HIGH

ALWAYS
PLANE

ON

M
PLANE

ON

SUS

RUN

PLANE

PLANE

ON ON ON

CLOCKS

ICH8-M

USB PORT#

0
1
2
3
4
5
6
7

DESTINATION
Rear Right Bottom
Rear Right Top
EXPRESS CARD
Bluetooth
Rear Left Bottom
Rear Left Top
OZ77CR6/Sma r t Card Reader
Docking

8

C C

B B

PM TABLE

State

S0

S3

S5 S4/AC

S5 S4/AC don't exist

power
plane

+15V_ALW
+5V_ALW
+3.3V_ALW +1.8V_SUS
+3.3V_RTC_LDO

ON

ON

ON

+5V_SUS
+3.3V_SUS

ON ON

ON

OFF

OFFOFF

+5V_RUN
+3.3V_RUN
+2.5V_RUN
+1.5V_RUN
+1.25V_RUN
+0.9V_DDR_VTT
+1.05V_VCCP
+VCC_CORE

OFF

OFF

OFF

OZ77CR6

9
UPD+/D-, pin 16/17
DPD+/D-, pin 18/19

EGATED+/D-, pin 20/21

PCI EXPRESS

Lane 1
Lane 2

DESTINATION
MINI CARD 1- Robson
MINI CARD 2- WLAN

Side Bottom
Side Top
ICH8-M
Biometric Reader
SMART CARD

PCI TABLE

Lane 3

R5C833

REQ#/GNT#

REQ#1 / GNT#1AD17 PIRQC, D

PIRQPCI DEVICE IDSEL

Lane 4
Lane 5
Lane 6

A A

AD24 REQ#0 / GNT#0

PIRQADocking

None
EXPRESS CARD
None
GIGA LAN

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, M/B LA-3751P

401490

348Wednesday, March 28, 2007

1

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1

RUN_ON

D D

ADAPTER

FDS6679AZ

(Q106)

+GFX_PWR_SRC

+5V_ALW

SUS_ON

HDDC_EN

+15V_ALW

SI3456BDV

(Q148)

SI3456BDV

(Q111)

+5V_SUS

+5V_HDD

+PWR_SRC

BATTERY

ISL6260

(PU6) (PU2)

CHARGER

C C

RUNPWROK

+VCC_CORE

+1.8V_SUS

ISL6236

DDR_ON

1.25V_RUN_ON

+1.25V_RUN

ISL6236

(PU4)

1.05V_RUN_ON

1.5V_RUN_ON

+1.05V_VCCP +1.5V_RUN

ISL6236

(PU1)

ALWON

+3.3V_ALW

ALWON

RUN_ON

SI4810BDY

(Q154)

AUDIO_AVDD_ON

MAX9789A

+5V_RUN

JUMP

(PJP22)(U41)

0.9V_DDR_VTT_ON

ENAB_3VLAN

SI3456BDV

(Q125)

3.3V_SUS_ON

SI4810BDY

(Q149)

3.3V_RUN_ON

SI4810BDY

(Q157)

WLAN_3V_ENABLE

+VDDA +5V_ODD

SI3456BDV

(Q133)

TPS51100

(PU3)

B B

+3.3V_LAN +3.3V_RUN+3.3V_SUS

+3.3V_WLAN

+0.9V_DDR_VTT

REGCTL_PNP25

REGCTL_PNP12

R1024

MBT35200MT2G PBSS5540Z

(Q126)

(Q127)

+3.3V_R5C833

A A

+2.5V_LAN +1.2V_LAN

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

DELL CONFIDENTIAL/PROPRIETARY

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, M /B LA-3751P

401490

448Wednesday, March 28, 2007

1

of

A

5

4

+3.3V_SUS

3

2

+3.3V_RUN

1

2.2K

ICH_SMBCLK

AJ26

D D

C C

ICH8-M

SIO

ICH_SMBDATA

AD19

LCD_SMBCLK

8

LCD_SMBDAT

7

THRM_SMBCLK

100

THRM_SMBDAT

99

PBAT_SMBCLK

112

PBAT_SMBDAT

111

+3.3V_ALW

8.2K

+3.3V_ALW

4.7K 4.7K

+3.3V_ALW

2.2K 2.2K

2.2K

8.2K

+3.3V_ALW

+3.3V_ALW

+3.3V_ALW

D7B6 911

BCM5756

SMBUS Address [C8]

EXPRESS
CARD

SMBUS Address [TBD]

100

100

3032

MINI WLAN

SMBUS Address [TBD]

8

Graphic BTB CONN

10

12

11

9

10

3

4

inverter

GUARDIAN

EMC4001

CHARGER

ISL88731

BATTERY
Connector

2N7002

MEM_SCLK
MEM_SDATA

2N7002

SMBUS Address [58]

SMBUS Address [2F]

SMBUS Address [12]

SMBUS Address [16]

2.2K 2.2K

197

195

197

195

30

32

DIMMA

SMBUS Address [A0]

DIMMB

SMBUS Address [A4]

MINI
ROBSON

SMBUS Address [TBD]

B B

DOCK_SMBCLK

6

DOCK_SMBDAT

5

+5V_ALW

8.2K 8.2K

+3.3V_ALW

+5V_ALW

39

40

+3.3V_RUN

DOCKING

SMBUS Address [C4, 72, 70, 48]

MEC5025

2.2K 2.2K

CKG_SMBCLK

13

A A

5

CKG_SMBDAT

12

+3.3V_ALW

4

2N7002

2N7002

CLK_SCLK
CLK_SDATA

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

2.2K 2.2K

+3.3V_RUN

2

16

17

CLOCK

GENERATOR

SMBUS Address [D2]

DELL CONFIDENTIAL/PROPRIETARY

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, M/B LA-3751P

401490

548Wednesday, March 28, 2007

1

of

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5

4

3

2

1

CLK_ICH_48M

1

C708

3.3P_0402_50V8C~D

2

CLK_SMC_48M

1

C774

D D

3.3P_0402_50V8C~D

2

CLK_PCI_TPM

1

C777

3.3P_0402_50V8C~D@

2

CLK_PCI_DOCK

1

C778

3.3P_0402_50V8C~D@

2

CLK_PCI_R5C832

1

C779

3.3P_0402_50V8C~D@

2

CLK_PCI_5025

1

C780

C C

3.3P_0402_50V8C~D@

2

CLK_PCI_5028

1

C781

3.3P_0402_50V8C~D@

2

CLK_ICH_14M

1

C775

3.3P_0402_50V8C~D@

2

CLK_SIO_14M

1

C776

3.3P_0402_50V8C~D@

2

CLK_PCI_ICH

1

C785

B B

3.3P_0402_50V8C~D@

2

PGMODE

0
1

TME PIN 32

0
1

*

ITP_EN

01Pin 5/6 as SRC_10

*

A A

FCTSEL1 PIN43 PIN44 PIN47 PIN48
0=UMA
1=DIS

*

+3.3V_RUN +3.3V_RUN

12

R329

10K_0402_5%~D@

FSA PCI_LOM

12

R391

10K_0402_5%~D@

+3.3V_RUN +3.3V_RUN

R290
10K_0402_5%~D

1 2

Place crystal within
500 mils of CK505

12

R318
10K_0402_5%~D

12

R319

10K_0402_5%~D@

12

R304
10K_0402_5%~D

PCI_ICHPCI_R5C832

CPU_MCH_BSEL0<8,10>

CPU_MCH_BSEL2<8,10>

C99

CLK_ICH_48M<22>
CLK_SMC_48M<32>

CLK_PCI_TPM<28>
CLK_PCI_DOCK<34>

CLK_PCI_R5C832<30>

CLK_PCI_5025<36>

CLK_PCI_5028<35>

CLK_ICH_14M<22>
CLK_SIO_14M<35>

CLK_PCI_ICH<20>

PIN 9
VTT_PWRGD#/PD
CKPWRGD/PD#

Normal Operation
Trusted Mode Enabled

PIN 37

CKG_SMBCLK<36>

Pin 5/6 as CPU_ITP

CKG_SMBDAT<36>

DOT96T DOT96C 96/100M_T 96/100M_C
27M_out 27M SSout SRCT0 SRCC0

5

+3.3V_RUN

C471

1

2

+CK_VDD_48

4.7U_0603_6.3V4Z~D
1

1

C799

2

2

C483

27P_0402_50V8J~D

C484

33P_0402_50V8J~D

CLK_ICH_48M
CLK_SMC_48M

CPU_MCH_BSEL1<8,10>

CLK_PCI_TPM
CLK_PCI_DOCK

CLK_PCI_R5C832
CLK_PCI_5025

CLK_PCI_5028

CLK_ICH_14M
CLK_SIO_14M

CLK_PCI_ICH

+3.3V_RUN

+3.3V_RUN

0.1U_0402_16V4Z~D

1 2

BLM21PG600SN1D_0805~D

0.047U_0402_16V4Z~D

12

12

+CK_VDD_REF

0.047U_0402_16V4Z~D

1

C189

2

12

X1

14.31818MHz_20P_1BX14318CC1A~D
R271 0_0402_5%~D

R273 15_0402_5%~D
R275 15_0402_5%~D
R309 2.2K_0402_5%~D

R314 8.2K_0402_5%~D

R277 33_0402_5%~D
R596 33_0402_5%~D

R280 33_0402_5%~D
R282 15_0402_5%~D

R333 15_0402_5%~D
R284 15_0402_5%~D
R285 15_0402_5%~D

R291 33_0402_5%~D

R295 10K_0402_5%~D@
R298 10K_0402_5%~D@

+3.3V_RUN

R435

1 2

0_0402_5%~D@

D

S

1 3

Q34
2N7002W-7-F_SOT323-3~D

G

2
2

G

Q35
2N7002W-7-F_SOT323-3~D

1 3

D

S

1 2

R440

0_0402_5%~D@

4

L28

1 2

BLM21PG600SN1D_0805~D

+CK_VDD_MAIN2

1 2

1 2
1 2

1 2

1 2
1 2
1 2

1 2
1 2

R265

12

12
12

12
12

12

CLK_PWRGD<22>

CLK_SDATA<31>

2.2K_0402_5%~D

12

L87

C482

R760 1_0603_5%~D
R758 2.2_0603_5%~D

CLK_SCLK<31>

R266

0.1U_0402_16V4Z~D

1

2

1 2
1 2

2.2K_0402_5%~D

12

C481

CLK_SCLK

CLK_SDATA

0.1U_0402_16V4Z~D
C480

1

1

2

2

+CK_VDD_REF
+CK_VDD_48

CLK_XTAL_IN

CLK_XTAL_OUT

FSA

FSC

PCI_LOM
PCI_DOCK
PCI_R5C832
PCI_SIO

CLKREF

PCI_ICH
CLK_PWRGD

PGMODE

CLK_SCLK

CLK_SDATA

+CK_VDD_MAIN1

C477

10U_0805_10V4Z~D

1
49
54
65

30
36

12
18
40

20

19

41
45
23

34
33
32
27

22

43
44

37

39

9

16

17

4
15
21
31
35
42
68

73

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D
C473

C474

1

1

2

2

U28

VDD_SRC
VDD_SRC
VDD_SRC
VDD_SRC

VDD_PCI
VDD_PCI

VDD_CPU
VDD_REF
VDD_48

XTAL_IN

XTAL_OUT

USB_48MHz/FSLA
FSL_B/TEST_MODE
REF_0/FSL_C/TEST_SEL

PCICLK4/FCT_SEL
PCICLK3
PCICLK2/TME
PCICLK1

REF_1

DOT_96/27M
DOT_96#/27M_SS

PCICLK_F0/ITP_EN

CKPWRGD/PD#

PGMODE

SMBCLK

SMBDAT

VSS_SRC
VSS_CPU
VSS_REF
VSS_PCI
VSS_PCI
VSS_48
VSS_SRC

THRM_PAD

SLG8LP550VTR_QFN72_10X10~D

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D
C475

C476

1

R759

1

2

2

1

2

1 2

2.2_0603_5%~D

SLG8LP550

CPU_ITP/SRC_10

CPU_ITP#/SRC_10#

LCD_CLK/SRC_0

LCD_CLK#/SRC_0#

3

10U_0805_10V4Z~D

0.1U_0402_16V4Z~D
C472

1

2

+CK_VDD_A

VDD_A
VSS_A

PCI_STP#

CPU_STP#

CPU_1

CPU_1#

CPU_0

CPU_0#

SRC_9

SRC_9#

CLKREQ_9#

SRC_8

SRC_8#

CLKREQ_8#

SRC_7

SRC_7#

CLKREQ_7#

SRC_6

SRC_6#

CLKREQ_6#

SRC_5

SRC_5#

CLKREQ_5#

SRC_4

SRC_4#

CLKREQ_4#

SRC_3

SRC_3#

CLKREQ_3#

SRC_2

SRC_2#

CLKREQ_2#

SRC_1/SATA

SRC_1#/SATA#

CLKREQ_1#

4.7U_0603_6.3V4Z~D

C478

7
8

H_STP_PCI#

25

H_STP_CPU#

24

MCH_BCLK

11

MCH_BCLK#

10

CPU_BCLK

14

CPU_BCLK#

13

CPU_ITP

6

CPU_ITP#

5

PCIE_MINI1

3

PCIE_MINI1#

2
72

PCIE_MINI2

70

PCIE_MINI2#

69
71

PCIE_ICH

66

PCIE_ICH#

67
38

PCIE_LOM

63

PCIE_LOM#

64
62

PCIE_VGA

60

PCIE_VGA#

61
29
58

PCIE_EXP# CLK_PCIE_EXP#

59
57

MCH_3GPLL

55

MCH_3GPLL#

56
28
52
53
26

PCIE_SATA

50

PCIE_SATA#

51
46
47
48

0.047U_0402_16V4Z~D

C479

1

1

2

2

R267 33_0402_5%~D
R268 33_0402_5%~D

R269 33_0402_5%~D
R270 33_0402_5%~D

R272 33_0402_5%~D
R274 33_0402_5%~D

R311 33_0402_5%~D
R313 33_0402_5%~D

R306 33_0402_5%~D
R307 33_0402_5%~D

R288 33_0402_5%~D
R289 33_0402_5%~D

R302 33_0402_5%~D
R303 33_0402_5%~D

R299 33_0402_5%~D
R168 33_0402_5%~D

R1603 33_0402_5%~D
R1604 33_0402_5%~D

R293 33_0402_5%~D
R294 33_0402_5%~D
R419 475_0402_1%~D

R279 33_0402_5%~D
R281 33_0402_5%~D

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2
1 2

1 2
1 2

H_STP_PCI# <22>

H_STP_CPU# <22>

CLK_MCH_BCLK
CLK_MCH_BCLK#

CLK_CPU_BCLK
CLK_CPU_BCLK#

CLK_CPU_ITP
CLK_CPU_ITP#

CLK_PCIE_MINI1
CLK_PCIE_MINI1#

CLK_PCIE_MINI2
CLK_PCIE_MINI2#

CLK_PCIE_ICH
CLK_PCIE_ICH#

CLK_PCIE_LOM
CLK_PCIE_LOM#

CLK_PCIE_VGA
CLK_PCIE_VGA#

CLK_PCIE_EXPPCIE_EXP

CLK_MCH_3GPLL
CLK_MCH_3GPLL#

CLK_PCIE_SATA
CLK_PCIE_SATA#

2

FSC

CLKSEL2

CLKSEL1

0
0

*

0
1
1
1
1

CPU_BSEL

133
166

CLK_MCH_BCLK <10>
CLK_MCH_BCLK# <10>

CLK_CPU_BCLK <7>
CLK_CPU_BCLK# <7>

CLK_CPU_ITP <7>
CLK_CPU_ITP# <7>

CLK_PCIE_MINI1 <31>

CLK_PCIE_MINI1# <31>

MINI1_CLKREQ# <31>

CLK_PCIE_MINI2 <31>
CLK_PCIE_MINI2# <31>

MINI2_CLKREQ# <31>

CLK_PCIE_ICH <22>
CLK_PCIE_ICH# <22>

CLK_PCIE_LOM <28>

CLK_PCIE_LOM# <28>
LOM_CLKREQ# <28>

CLK_PCIE_VGA <18>
CLK_PCIE_VGA# <18>

CLK_PCIE_EXP <32>
CLK_PCIE_EXP# <32>

EXP_CLKREQ# <32>
CLK_MCH_3GPLL <10>

CLK_MCH_3GPLL# <10>

3GPLL_CLKREQ# <10>

CLK_PCIE_SATA <21>

CLK_PCIE_SATA# <21>

SATA_CLKREQ# <22>

DELL CONFIDENTIAL/PROPRIETARY

Title

Size Document Number Rev

401490

Date: Sheet

FSAFSB

CPU
MHz

CLKSEL0

266

00

133

1

0

200

0

10

1
0
1
0
1

166

333

100

400

CPU_BSEL1(FSB)

1
0
0
1
1

CPU_BSEL2(FSC)

0

MINI1_CLKREQ#

MINI2_CLKREQ#

LOM_CLKREQ#

EXP_CLKREQ#

3GPLL_CLKREQ#

SATA_CLKREQ#

1 2

R315 10K_0402_5%~D

1 2

R310 10K_0402_5%~D

1 2

R301 10K_0402_5%~D

1 2

R1602 10K_0402_5%~D

1 2

R297 10K_0402_5%~D

1 2

R283 10K_0402_5%~D

Compal Electronics, Inc.

SCHEMATIC, M/B LA-3751P

1

SRC
MHz

100

100

100

100

100

100

100

100200

PCI
MHz

33.3

33.3

33.3

33.3

33.3

33.3

33.3

33.3

0
10

+3.3V_RUN

648Wednesday, March 28, 2007

A

of

5

4

3

2

1

+1.05V_VCCP

ITP_DBRESET#
ITP_BPM#0

D D

R321

3

22.6_0402_1%~D
1 2

1 2

R1597

22.6_0402_1%~D

CLK_CPU_ITP<6>
CLK_CPU_ITP#<6>

H_A#[3..35]<10>

H_ADSTB#0<10>

H_REQ#0<10>
H_REQ#1<10>
H_REQ#2<10>
H_REQ#3<10>

C C

B B

A A

H_REQ#4<10>

H_ADSTB#1<10>

H_A20M#<21>

H_FERR#<21>

H_IGNNE#<21>
H_STPCLK#<21>

H_INTR<21>
H_NMI<21>
H_SMI#<21>

5

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_ADSTB#0

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35
H_ADSTB#1

H_A20M#
H_FERR#
H_IGNNE#

H_STPCLK#
H_INTR
H_NMI
H_SMI#

+1.05V_VCCP

JCPUA

J4

A[3]#

L5

A[4]#

L4

A[5]#

K5

A[6]#

M3

A[7]#

N2

A[8]#

J1

A[9]#

N3

A[10]#

P5

A[11]#

P2

A[12]#

L2

A[13]#

P4

A[14]#

P1

A[15]#

R1

A[16]#

M1

ADSTB[0]#

K3

REQ[0]#

H2

REQ[1]#

K2

REQ[2]#

J3

REQ[3]#

L1

REQ[4]#

Y2

A[17]#

U5

A[18]#

R3

A[19]#

W6

A[20]#

U4

A[21]#

Y5

A[22]#

U1

A[23]#

R4

A[24]#

T5

A[25]#

T3

A[26]#

W2

A[27]#

W5

A[28]#

Y4

A[29]#

U2

A[30]#

V4

A[31]#

W3

A[32]#

AA4

A[33]#

AB2

A[34]#

AA3

A[35]#

V1

ADSTB[1]#

A6

A20M#

A5

FERR#

C4

IGNNE#

D5

STPCLK#

C6

LINT0

B4

LINT1

A3

SMI#

M4

RSVD[01]

N5

RSVD[02]

T2

RSVD[03]

V3

RSVD[04]

B2

RSVD[05]

C3

RSVD[06]

D2

RSVD[07]

D22

RSVD[08]

D3

RSVD[09]

F6

RSVD[10]

TYCO_1-1674770-2_Merom~D

R327

1 2

56_0402_5%~D

ADDR GROUP 0

CONTROLXDP/ITP SIGNALS

ADDR GROUP 1

THERMAL

PROCHOT#

THERMDA
THERMDC

ICH

THERMTRIP#

H CLK

RESERVED

H_THERMTRIP#

ADS#
BNR#
BPRI#

DEFER#

DRDY#

DBSY#

BR0#
IERR#

INIT#

LOCK#

RESET#

RS[0]#
RS[1]#
RS[2]#

TRDY#

HIT#

HITM#

BPM[0]#
BPM[1]#
BPM[2]#
BPM[3]#

PRDY#
PREQ#

TCK

TDO
TMS

TRST#

DBR#

BCLK[0]
BCLK[1]

H_ADS# CLK_CPU_ITP

H1

H_BNR#

E2

H_BPRI#

G5

H_DEFER#

H5

H_DRDY#

F21

H_DBSY#

E1

H_BR0#

F1

H_IERR#

D20

H_INIT#

B3

H_LOCK#

H4

H_RESET#

C1

H_RS#0

F3

H_RS#1

F4

H_RS#2

G3

H_TRDY#

G2

H_HIT#

G6

H_HITM#

E4

ITP_BPM#0

AD4

ITP_BPM#1

AD3

ITP_BPM#2

AD1

ITP_BPM#3

AC4

ITP_BPM#4

AC2

ITP_BPM#5

AC1

ITP_TCK

AC5

ITP_TDI

AA6

TDI

AB3
AB5
AB6
C20

D21
A24
B25

C7

A22
A21

ITP_TDO
ITP_TMS
ITP_TRST#
ITP_DBRESET#

EC_CPU_PROCHOT#
H_THERMDA

H_THERMDC
H_THERMTRIP#
CLK_CPU_BCLK

CLK_CPU_BCLK#

4

H_ADS# <10>

H_BNR# <10>
H_BPRI# <10>

H_DEFER# <10>
H_DRDY# <10>

H_DBSY# <10>

H_BR0# <10>

H_INIT# <21>

H_LOCK# <10>

H_RESET# <10>
H_RS#0 <10>
H_RS#1 <10>
H_RS#2 <10>
H_TRDY# <10>

H_HIT# <10>

H_HITM# <10>

ITP_DBRESET# <22,35>

1

C417
2200P_0402_50V7K~D

2

H_THERMTRIP# <15>

CLK_CPU_BCLK <6>

CLK_CPU_BCLK# <6>

H_THERMDA, H_THERMDC routing together,
Trace width / Spacing = 10 / 10 mil

R320

56_0402_5%~D

+1.05V_VCCP

12

12

R323
56_0402_5%~D

H_THERMDA <15>

H_THERMDC <15>

H_RESET#

ITP_TDO

+1.05V_VCCP

EC_CPU_PROCHOT# <36>

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

ITP_BPM#1
ITP_BPM#2
ITP_BPM#3
ITP_BPM#4
ITP_BPM#5
ITP_TCK

CLK_CPU_ITP#

ITP_TCK
ITP_TRST#

ITP_TMS
ITP_TDI

Place close to JITP

+1.05V_VCCP

1

C485

2

Place close to JITP

+3.3V_SUS

R324

1 2

150_0402_5%~D

+1.05V_VCCP

R325

51_0402_5%~D

R326

51_0402_1%~D

R328

39_0402_1%~D

R332

27_0402_1%~D

Place close to CPU

+1.05V_VCCP

R330

150_0402_5%~D

R331

649_0402_1%~D

1 2

@

0.1U_0402_16V4Z~D
C486

JITP

28

VTT1

27

VTT0

26

VTAP

25

DBR#

24

DBA#

23

BPM0#

22

GND5

21

BPM1#

20

GND4

19

BPM2#

18

GND3

17

BPM3#

16

GND2

15

BPM4#

14

GND1

13

BPM5#

12

RESET#

11

FBO

10

GND0

9

BCLKP

8

BCLKN

7

TDO

6

NC2

5

TCK

4

NC1

3

TRST#

2

TMS

1

TDI

@

0.1U_0402_16V4Z~D

1

2

ITP_DBRESET#

ITP_TDO

H_RESET#

ITP_TMS

ITP_TCK

ITP_TDI

ITP_TRST#

29

GND6

JCPUD

30

GND7

A4

VSS[001]

A8

VSS[002]

A11

VSS[003]

A14

VSS[004]

A16

VSS[005]

A19

VSS[006]

A23

VSS[007]

AF2

VSS[008]

B6

VSS[009]

B8

VSS[010]

B11

VSS[011]

B13

VSS[012]

B16

VSS[013]

B19

VSS[014]

B21

VSS[015]

B24

VSS[016]

C5

VSS[017]

C8

VSS[018]

C11

VSS[019]

C14

VSS[020]

C16

VSS[021]

C19

VSS[022]

C2

VSS[023]

C22

VSS[024]

C25

MOLEX_52435-2891_28P~D@

VSS[025]

D1

VSS[026]

D4

VSS[027]

D8

VSS[028]

D11

VSS[029]

D13

VSS[030]

D16

VSS[031]

D19

VSS[032]

D23

VSS[033]

D26

VSS[034]

E3

VSS[035]

E6

VSS[036]

E8

VSS[037]

E11

VSS[038]

E14

VSS[039]

E16

VSS[040]

E19

VSS[041]

E21

VSS[042]

E24

VSS[043]

F5

VSS[044]

F8

VSS[045]

F11

VSS[046]

F13

VSS[047]

F16

VSS[048]

F19

VSS[049]

F2

VSS[050]

F22

VSS[051]

F25

VSS[052]

G4

VSS[053]

G1

VSS[054]

G23

VSS[055]

G26

VSS[056]

H3

VSS[057]

H6

VSS[058]

H21

VSS[059]

H24

VSS[060]

J2

VSS[061]

J5

VSS[062]

J22

VSS[063]

J25

VSS[064]

K1

VSS[065]

K4

VSS[066]

K23

VSS[067]

K26

VSS[068]

L3

VSS[069]

L6

VSS[070]

L21

VSS[071]

L24

VSS[072]

M2

VSS[073]

M5

VSS[074]

M22

VSS[075]

M25

VSS[076]

N1

VSS[077]

N4

VSS[078]

N23

VSS[079]

N26

VSS[080]

P3

VSS[081]

TYCO_1-1674770-2_Merom~D

VSS[082]
VSS[083]
VSS[084]
VSS[085]
VSS[086]
VSS[087]
VSS[088]
VSS[089]
VSS[090]
VSS[091]
VSS[092]
VSS[093]
VSS[094]
VSS[095]
VSS[096]
VSS[097]
VSS[098]
VSS[099]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
VSS[159]
VSS[160]
VSS[161]
VSS[162]
VSS[163]

P6
P21
P24
R2
R5
R22
R25
T1
T4
T23
T26
U3
U6
U21
U24
V2
V5
V22
V25
W1
W4
W23
W26
Y3
Y6
Y21
Y24
AA2
AA5
AA8
AA11
AA14
AA16
AA19
AA22
AA25
AB1
AB4
AB8
AB11
AB13
AB16
AB19
AB23
AB26
AC3
AC6
AC8
AC11
AC14
AC16
AC19
AC21
AC24
AD2
AD5
AD8
AD11
AD13
AD16
AD19
AD22
AD25
AE1
AE4
AE8
AE11
AE14
AE16
AE19
AE23
AE26
A2
AF6
AF8
AF11
AF13
AF16
AF19
AF21
A25
AF25

DELL CONFIDENTIAL/PROPRIETARY

Title

Size Document Number Rev

2

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, M /B LA-3751P

401490

748Wednesday, March 28, 2007

1

A

of

5

4

3

2

1

H_D#[0..63]<10>

H_D#0

D D

H_DSTBN#0<10>
H_DSTBP#0<10>

H_DINV#0<10>

C C

H_DSTBN#1<10>
H_DSTBP#1<10>

H_DINV#1<10>

+V_CPU_GTLREF

CPU_MCH_BSEL0<6,10>
CPU_MCH_BSEL1<6,10>
CPU_MCH_BSEL2<6,10>

FSB BSEL2 BSEL0

BCLK BSEL1

133

B B

A A

533
667

166 1

800

200

1K_0402_5%~D@

R335

1K_0402_5%~D@

R336

1 2

1 2

Place C490 close to the
CPU_TEST4 pin. Make sure
CPU_TEST4 routing is
reference to GND and away
from other noisy signal.

C490

H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_DSTBN#0
H_DSTBP#0
H_DINV#0

H_D#16
H_D#17
H_D#18

H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_DSTBN#1
H_DSTBP#1
H_DINV#1

TEST1
TEST2
TEST3
TEST4
TEST5
TEST6

CPU_MCH_BSEL0
CPU_MCH_BSEL1
CPU_MCH_BSEL2

00
0

1

0

TEST1
TEST2
TEST4
TEST6

0.1U_0402_16V4Z~D@
0_0402_5%~D@

R394

2

1

1 2

JCPUB

E22

D[0]#

F24

D[1]#

E26

D[2]#

G22

D[3]#

F23

D[4]#

G25

D[5]#

E25

D[6]#

E23

D[7]#

K24

D[8]#

G24

D[9]#

J24

D[10]#

J23

D[11]#

H22

D[12]#

F26

D[13]#

K22

D[14]#

H23

D[15]#

J26

DSTBN[0]#

H26

DSTBP[0]#

H25

DINV[0]#

N22

D[16]#

K25

D[17]#

P26

D[18]#

R23

D[19]#

L23

D[20]#

M24

D[21]#

L22

D[22]#

M23

D[23]#

P25

D[24]#

P23

D[25]#

P22

D[26]#

T24

D[27]#

R24

D[28]#

L25

D[29]#

T25

D[30]#

N25

D[31]#

L26

DSTBN[1]#

M26

DSTBP[1]#

N24

DINV[1]#

AD26

GTLREF

C23

TSET1

D25

TEST2

C24

TEST3

AF26

TEST4

AF1

TEST5

A26

TEST6

B22

BSEL[0]

B23

BSEL[1]

C21

BSEL[2]

TYCO_1-1674770-2_Merom~D

1
1
0

D[32]#
D[33]#
D[34]#
D[35]#

T30
T31

D[36]#
D[37]#
D[38]#
D[39]#
D[40]#
D[41]#
D[42]#
D[43]#
D[44]#

DATA GRP 2DATA GRP 3

D[45]#
D[46]#

D[47]#
DSTBN[2]#
DSTBP[2]#

DINV[2]#

D[48]#

D[49]#

D[50]#

D[51]#

D[52]#

D[53]#

D[54]#

D[55]#

D[56]#

D[57]#

D[58]#

D[59]#

D[60]#

D[61]#

D[62]#

D[63]#
DSTBN[3]#
DSTBP[3]#

DINV[3]#

COMP[0]
COMP[1]
COMP[2]
COMP[3]

DPRSTP#

DPSLP#

DPWR#

PWRGOOD

SLP#

PSI#

TEST3
TEST5

+V_CPU_GTLREF

DATA GRP 0 DATA GRP 1

MISC

For the purpose of testability, route these signals
through a ground referenced Z0 = 55ohm trace that
ends in a via that is near a GND via and is
accessible through an oscilloscope connection.

AB24
V24
V26
V23
T22
U25
U23
Y25
W22
Y23
W24
W25
AA23
AA24
AB25
Y26
AA26
U22

AE24
AD24
AA21
AB22
AB21
AC26
AD20
AE22
AF23
AC25
AE21
AD21
AC22
AD23
AF22
AC23
AE25
AF24
AC20

R26
U26
AA1
Y1

E5
B5
D24
D6
D7
AE6

+1.05V_VCCP

12

12

H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_DSTBN#2
H_DSTBP#2
H_DINV#2

H_D#48
H_D#49
H_D#50
H_D#51H_D#19
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
H_DSTBN#3
H_DSTBP#3
H_DINV#3

COMP0
COMP1
COMP2
COMP3

H_DPRSTP#
H_DPSLP#
H_DPWR#
H_PWRGOOD
H_CPUSLP#
H_PSI#

R341
1K_0402_1%~D

R344
2K_0402_1%~D

H_DSTBN#2 <10>
H_DSTBP#2 <10>

H_DINV#2 <10>

H_DSTBN#3 <10>
H_DSTBP#3 <10>

H_DINV#3 <10>

H_DPRSTP# <10,21,45>

H_DPSLP# <21>

H_DPWR# <10>

H_PWRGOOD <21>

H_CPUSLP# <10>

H_PSI# <45>

H_D#32

Y22

Layout close CPU PIN AD26
55 ohm, 0.5 inch (max)

54.9_0402_1%~D

12

R337

R338

Resistor placed within 0.5" of
CPU pin.Trace should be at least
25 mils away from any other
toggling signal. COMP0, COMP2
trace should be 27.4 ohm.
COMP1, COMP3 should be 55
ohm.

54.9_0402_1%~D

27.4_0402_1%~D

12

R339

12

12

R340

27.4_0402_1%~D

+VCC_CORE +VCC_CORE

JCPUC

A7

VCC[001]

A9

VCC[002]

A10

VCC[003]

A12

VCC[004]

A13

VCC[005]

A15

VCC[006]

A17

VCC[007]

A18

VCC[008]

A20

VCC[009]

B7

VCC[010]

B9

VCC[011]

B10

VCC[012]

B12

VCC[013]

B14

VCC[014]

B15

VCC[015]

B17

VCC[016]

B18

VCC[017]

B20

VCC[018]

C9

VCC[019]

C10

VCC[020]

C12

VCC[021]

C13

VCC[022]

C15

VCC[023]

C17

VCC[024]

C18

VCC[025]

D9

VCC[026]

D10

VCC[027]

D12

VCC[028]

D14

VCC[029]

D15

VCC[030]

D17

VCC[031]

D18

VCC[032]

E7

VCC[033]

E9

VCC[034]

E10

VCC[035]

E12

VCC[036]

E13

VCC[037]

E15

VCC[038]

E17

VCC[039]

E18

VCC[040]

E20

VCC[041]

F7

VCC[042]

F9

VCC[043]

F10

VCC[044]

F12

VCC[045]

F14

VCC[046]

F15

VCC[047]

F17

VCC[048]

F18

VCC[049]

F20

VCC[050]

AA7

VCC[051]

AA9

VCC[052]

AA10

VCC[053]

AA12

VCC[054]

AA13

VCC[055]

AA15

VCC[056]

AA17

VCC[057]

AA18

VCC[058]

AA20

VCC[059]

AB9

VCC[060]

AC10

VCC[061]

AB10

VCC[062]

AB12

VCC[063]

AB14

VCC[064]

AB15

VCC[065]

AB17

VCC[066]

AB18

VCC[067]

TYCO_1-1674770-2_Merom~D

AB20

VCC[068]

AB7

VCC[069]

AC7

VCC[070]

AC9

VCC[071]

AC12

VCC[072]

AC13

VCC[073]

AC15

VCC[074]

AC17

VCC[075]

AC18

VCC[076]

AD7

VCC[077]

AD9

VCC[078]

AD10

VCC[079]

AD12

VCC[080]

AD14

VCC[081]

AD15

VCC[082]

AD17

VCC[083]

AD18

VCC[084]

AE9

VCC[085]

AE10

VCC[086]

AE12

VCC[087]

AE13

VCC[088]

AE15

VCC[089]

AE17

VCC[090]

AE18

VCC[091]

AE20

VCC[092]

AF9

VCC[093]

AF10

VCC[094]

AF12

VCC[095]

AF14

VCC[096]

AF15

VCC[097]

AF17

VCC[098]

AF18

VCC[099]

AF20

VCC[100]

G21

VCCP[01]

V6

VCCP[02]

J6

VCCP[03]

K6

VCCP[04]

M6

VCCP[05]

J21

VCCP[06]

K21

VCCP[07]

M21

VCCP[08]

N21

VCCP[09]

N6

VCCP[10]

R21

VCCP[11]

R6

VCCP[12]

T21

VCCP[13]

T6

VCCP[14]

V21

VCCP[15]

W21

VCCP[16]

B26

VCCA[1]

C26

VCCA[2]

AD6

VID[0]

AF5

VID[1]

AE5

VID[2]

AF4

VID[3]

AE3

VID[4]

AF3

VID[5]

AE2

VID[6]

AF7

VCCSENSE

AE7

VSSSENSE

VCCSENSE/VSSSENSE trace length
match wit h i n 25 mils, Z0=27.4 ohm

VID0
VID1
VID2
VID3
VID4
VID5
VID6

VCCSENSE

VSSSENSE

Place R342 and R343 near CPU

+VCC_CORE

R342

R343

VCCSENSE

VSSSENSE

1 2

100_0402_1%~D

1 2

100_0402_1%~D

Route VCCSENSE and VSSSENSE trace Zo

27.4 ohms, 7 mils spaci n g and 1 inch (max)

C487

220U_D2_4VY_R15M~D

1

+

2

VID0 <45>
VID1 <45>
VID2 <45>
VID3 <45>
VID4 <45>
VID5 <45>
VID6 <45>

VCCSENSE <45>

VSSSENSE <45>

+1.05V_VCCP

C488

+1.5V_RUN

10U_0805_10V4Z~D

0.01U_0402_16V7K~D

C489

1

1

2

2

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, M /B LA-3751P

401490

848Thursday, March 29, 2007

1

A

of

5

High Frequence Decoupling

+VCC_CORE

4

3

2

1

Place these inside
socket cavity on

D D

C C

North side
Secondary

Place these inside
socket cavity on
Sourth side
Secondary

Place these inside
socket cavity on
North side
Primary

Place these inside
socket cavity on
Sourth side
Primary

1

2

+VCC_CORE

1

2

+VCC_CORE

1

2

+VCC_CORE

1

2

C226
10U_0805_4VAM~D

C54
10U_0805_4VAM~D

C329
10U_0805_4VAM~D

C335
10U_0805_4VAM~D

1

C227
10U_0805_4VAM~D

2

1

C53
10U_0805_4VAM~D

2

1

C330
10U_0805_4VAM~D

2

1

C336
10U_0805_4VAM~D

2

1

C228
10U_0805_4VAM~D

2

1

C52
10U_0805_4VAM~D

2

1

C331
10U_0805_4VAM~D

2

1

C222
10U_0805_4VAM~D

2

1

C229
10U_0805_4VAM~D

2

1

C51
10U_0805_4VAM~D

2

1

C332
10U_0805_4VAM~D

2

1

C223
10U_0805_4VAM~D

2

1

C363
10U_0805_4VAM~D

2

1

C50
10U_0805_4VAM~D

2

1

C333
10U_0805_4VAM~D

2

1

C224
10U_0805_4VAM~D

2

1

C64
10U_0805_4VAM~D

2

1

C364
10U_0805_4VAM~D

2

1

C334
10U_0805_4VAM~D

2

1

C225
10U_0805_4VAM~D

2

1

C65
10U_0805_4VAM~D

2

1

C68
10U_0805_4VAM~D

2

1

C66
10U_0805_4VAM~D

2

1

C67
10U_0805_4VAM~D

2

1

C55
10U_0805_4VAM~D

2

1

C69
10U_0805_4VAM~D

2

1

C190
10U_0805_4VAM~D

2

1

C185
10U_0805_4VAM~D

2

10uF 0805 X6S

Near VCORE regulator.

+VCC_CORE

220U_X_2VM_R7M~D

South Side Secondary

B B

1

C338

C366

+

2

220U_X_2VM_R7M~D

220U_X_2VM_R7M~D

1

1

C365

+

+

2

2

220U_X_2VM_R7M~D

220U_X_2VM_R7M~D

1

C177

C179

+

2

220U_X_2VM_R7M~D

1

C178

+

2

North Side Secondary

1

+

2

ESR <= 1.5m ohm

+1.05V_VCCP

1

C312

0.1U_0402_10V7K~D

2

A A

1

C256

0.1U_0402_10V7K~D

2

1

C293

0.1U_0402_10V7K~D

2

1

C250

0.1U_0402_10V7K~D

2

1

C310

0.1U_0402_10V7K~D

2

1

C264

0.1U_0402_10V7K~D

2

Place these inside
socket cavity on
Secondary side

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, M /B LA-3751P

401490

948Wednesday, March 28, 2007

1

A

of

5

H_D#[0..63]<8>

D D

C C

+1.05V_VCCP

54.9_0402_1%~D

54.9_0402_1%~D
12

12

R348

R347

B B

H_RESET#<7>

12

H_CPUSLP#<8>

R350

24.9_0402_1%~D

Layout Note:
H_RCOMP trace width
and spacing is 10/20

A A

H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63

H_SWNG
H_RCOMP

H_SCOMP
H_SCOMP#

H_RESET#

H_CPUSLP#

H_VREF

C497

1

2

5

U29A

E2

H_D#_0

G2

H_D#_1

G7

H_D#_2

M6

H_D#_3

H7

H_D#_4

H3

H_D#_5

G4

H_D#_6

F3

H_D#_7

N8

H_D#_8

H2

H_D#_9

M10

H_D#_10

N12

H_D#_11

N9

H_D#_12

H5

H_D#_13

P13

H_D#_14

K9

H_D#_15

M2

H_D#_16

W10

H_D#_17

Y8

H_D#_18

V4

H_D#_19

M3

H_D#_20

J1

H_D#_21

N5

H_D#_22

N3

H_D#_23

W6

H_D#_24

W9

H_D#_25

N2

H_D#_26

Y7

H_D#_27

Y9

H_D#_28

P4

H_D#_29

W3

H_D#_30

N1

H_D#_31

AD12

H_D#_32

AE3

H_D#_33

AD9

H_D#_34

AC9

H_D#_35

AC7

H_D#_36

AC14

H_D#_37

AD11

H_D#_38

AC11

H_D#_39

AB2

H_D#_40

AD7

H_D#_41

AB1

H_D#_42

Y3

H_D#_43

AC6

H_D#_44

AE2

H_D#_45

AC5

H_D#_46

AG3

H_D#_47

AJ9

H_D#_48

AH8

H_D#_49

AJ14

H_D#_50

AE9

H_D#_51

AE11

H_D#_52

AH12

H_D#_53

AJ5

H_D#_54

AH5

H_D#_55

AJ6

H_D#_56

AE7

H_D#_57

AJ7

H_D#_58

AJ2

H_D#_59

AE5

H_D#_60

AJ3

H_D#_61

AH2

H_D#_62

AH13

H_D#_63

B3

H_SWING

C2

H_RCOMP

W1

H_SCOMP

W2

H_SCOMP#

B6

H_CPURST#

E5

H_CPUSLP#

B9

H_AVREF

A9

H_DVREF

LE88CLPM C0 QP21_FCBGA1299~D

+1.05V_VCCP

12

R356
221_0402_1%~D

H_SWNG

0.1U_0402_16V4Z~D

100_0402_1%~D

12

R362

C496

HOST

+1.05V_VCCP

0.1U_0402_16V4Z~D
R361

1

2

H_A#_3
H_A#_4
H_A#_5
H_A#_6
H_A#_7
H_A#_8

H_A#_9
H_A#_10
H_A#_11
H_A#_12
H_A#_13
H_A#_14
H_A#_15
H_A#_16
H_A#_17
H_A#_18
H_A#_19
H_A#_20
H_A#_21
H_A#_22
H_A#_23
H_A#_24
H_A#_25
H_A#_26
H_A#_27
H_A#_28
H_A#_29
H_A#_30
H_A#_31
H_A#_32
H_A#_33
H_A#_34
H_A#_35

H_ADS#
H_ADSTB#_0
H_ADSTB#_1

H_BNR#

H_BPRI#

H_BREQ#

H_DEFER#

H_DBSY#

HPLL_CLK

HPLL_CLK#

H_DPWR#

H_DRDY#

H_HIT#

H_HITM#
H_LOCK#
H_TRDY#

H_DINV#_0
H_DINV#_1
H_DINV#_2
H_DINV#_3

H_DSTBN#_0
H_DSTBN#_1
H_DSTBN#_2
H_DSTBN#_3

H_DSTBP#_0
H_DSTBP#_1
H_DSTBP#_2
H_DSTBP#_3

H_REQ#_0
H_REQ#_1
H_REQ#_2
H_REQ#_3
H_REQ#_4

H_RS#_0

H_RS#_1

H_RS#_2

12

R355
1K_0402_1%~D
H_VREF

2K_0402_1%~D

12

J13
B11
C11
M11
C15
F16
L13
G17
C14
K16
B13
L16
J17
B14
K19
P15
R17
B16
H20
L19
D17
M17
N16
J19
B18
E19
B17
B15
E17
C18
A19
B19
N19

G12
H17
G20
C8
E8
F12
D6
C10
AM5
AM7
H8
K7
E4
C6
G10
B7

K5
L2
AD13
AE13

M7
K3
AD2
AH11

L7
K2
AC2
AJ10

M14
E13
A11
H13
B12

E12
D7
D8

+1.8V_SUS

R359

R363

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35

H_ADS#
H_ADSTB#0
H_ADSTB#1
H_BNR#
H_BPRI#
H_BR0#
H_DEFER#
H_DBSY#
CLK_MCH_BCLK
CLK_MCH_BCLK#
H_DPWR#
H_DRDY#
H_HIT#
H_HITM#
H_LOCK#
H_TRDY#

H_DINV#0
H_DINV#1
H_DINV#2
H_DINV#3

H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3

H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

H_RS#0
H_RS#1
H_RS#2

12

R353
1K_0402_1%~D

3.01K_0402_1%~D
C494

1

12

2

1K_0402_1%~D

12

C498

1

2

4

0.01U_0402_16V7K~D
C495

0.01U_0402_16V7K~D
C499

4

SMRCOMP_VOH

1

2

SMRCOMP_VOL

1

2

H_A#[3..35] <7>

V_DDR_MCH_REF

H_ADS# <7>

H_ADSTB#0 <7>

H_ADSTB#1 <7>
H_BNR# <7>
H_BPRI# <7>
H_BR0# <7>
H_DEFER# <7>
H_DBSY# <7>

CLK_MCH_BCLK <6>

CLK_MCH_BCLK# <6>
H_DPWR# <8>
H_DRDY# <7>

H_HIT# <7>
H_HITM# <7>
H_LOCK# <7>

H_TRDY# <7>

H_DINV#0 <8>
H_DINV#1 <8>
H_DINV#2 <8>
H_DINV#3 <8>

H_DSTBN#0 <8>
H_DSTBN#1 <8>
H_DSTBN#2 <8>
H_DSTBN#3 <8>

H_DSTBP#0 <8>
H_DSTBP#1 <8>
H_DSTBP#2 <8>
H_DSTBP#3 <8>

H_REQ#0 <7>
H_REQ#1 <7>
H_REQ#2 <7>
H_REQ#3 <7>
H_REQ#4 <7>

H_RS#0 <7>
H_RS#1 <7>
H_RS#2 <7>

2.2U_0603_6.3V6K~D

2.2U_0603_6.3V6K~D

+1.8V_SUS

0.1U_0402_16V4Z~D

20_0402_1%~D

20_0402_1%~D

C491

+1.25V_RUN

12

R349

12

R351

R345

1 2
1 2

R346

1K_0402_1%~D

392_0402_1~D

M_CLK_DDR0<17>
M_CLK_DDR1<17>
M_CLK_DDR2<16>
M_CLK_DDR3<16>

M_CLK_DDR#0<17>
M_CLK_DDR#1<17>
M_CLK_DDR#2<16>
M_CLK_DDR#3<16>

DDR_CKE0_DIMMA<17>
DDR_CKE1_DIMMA<17>
DDR_CKE2_DIMMB<16>
DDR_CKE3_DIMMB<16>

DDR_CS0_DIMMA#<17>
DDR_CS1_DIMMA#<17>
DDR_CS2_DIMMB#<16>
DDR_CS3_DIMMB#<16>

1

1

C492

0.1U_0402_16V4Z~D

2

2

CLK_MCH_3GPLL<6>
CLK_MCH_3GPLL#<6>

DMI_MRX_ITX_N0<22>
DMI_MRX_ITX_N1<22>
DMI_MRX_ITX_N2<22>
DMI_MRX_ITX_N3<22>

DMI_MRX_ITX_P0<22>
DMI_MRX_ITX_P1<22>
DMI_MRX_ITX_P2<22>
DMI_MRX_ITX_P3<22>

DMI_MTX_IRX_N0<22>
DMI_MTX_IRX_N1<22>
DMI_MTX_IRX_N2<22>
DMI_MTX_IRX_N3<22>

DMI_MTX_IRX_P0<22>
DMI_MTX_IRX_P1<22>
DMI_MTX_IRX_P2<22>
DMI_MTX_IRX_P3<22>

CL_CLK0<22>
CL_DATA0<22>

ICH_CL_PWROK<22,36>

CL_RST0#<22>

1

C493

0.1U_0402_16V4Z~D

2

3GPLL_CLKREQ#<6>
MCH_ICH_SYNC#<22>

3

U29B

M_CLK_DDR0
M_CLK_DDR1
M_CLK_DDR2
M_CLK_DDR3

M_CLK_DDR#0
M_CLK_DDR#1
M_CLK_DDR#2
M_CLK_DDR#3

DDR_CKE0_DIMMA
DDR_CKE1_DIMMA
DDR_CKE2_DIMMB
DDR_CKE3_DIMMB

DDR_CS0_DIMMA#
DDR_CS1_DIMMA#
DDR_CS2_DIMMB#
DDR_CS3_DIMMB#

M_ODT0<17>
M_ODT1<17>
M_ODT2<16>
M_ODT3<16>

V_DDR_MCH_REF

M_ODT0
M_ODT1
M_ODT2
M_ODT3

SMRCOMP
SMRCOMP#

SMRCOMP_VOH
SMRCOMP_VOL

CLK_MCH_3GPLL
CLK_MCH_3GPLL#

DMI_MRX_ITX_N0
DMI_MRX_ITX_N1
DMI_MRX_ITX_N2
DMI_MRX_ITX_N3

DMI_MRX_ITX_P0
DMI_MRX_ITX_P1
DMI_MRX_ITX_P2
DMI_MRX_ITX_P3

DMI_MTX_IRX_N0
DMI_MTX_IRX_N1
DMI_MTX_IRX_N2
DMI_MTX_IRX_N3

DMI_MTX_IRX_P0
DMI_MTX_IRX_P1
DMI_MTX_IRX_P2
DMI_MTX_IRX_P3

T42
T43
T44
T45

T46

CL_CLK0
CL_DATA0
ICH_CL_PWROK
CL_RST0#
CL_VREF

3GPLL_CLKREQ#
MCH_ICH_SYNC#

R774 0_0402_5%~D

R357 20K_0402_5%~D

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

AV29

SM_CK_0

BB23

SM_CK_1

BA25

SM_CK_3

AV23

SM_CK_4

AW30

SM_CK#_0

BA23

SM_CK#_1

AW25

SM_CK#_3

AW23

SM_CK#_4

BE29

SM_CKE_0

AY32

SM_CKE_1

BD39

SM_CKE_3

BG37

SM_CKE_4

BG20

SM_CS#_0

BK16

SM_CS#_1

BG16

SM_CS#_2

BE13

SM_CS#_3

BH18

SM_ODT_0

BJ15

SM_ODT_1

BJ14

SM_ODT_2

BE16

SM_ODT_3

BL15

SM_RCOMP

BK14

SM_RCOMP#

BK31

SM_RCOMP_VOH

BL31

SM_RCOMP_VOL

AR49

SM_VREF_0

AW4

SM_VREF_1

B42

DPLL_REF_CLK

C42

DPLL_REF_CLK#

H48

DPLL_REF_SSCLK

H47

DPLL_REF_SSCLK#

K44

PEG_CLK

K45

PEG_CLK#

AN47

DMI_RXN_0

AJ38

DMI_RXN_1

AN42

DMI_RXN_2

AN46

DMI_RXN_3

AM47

DMI_RXP_0

AJ39

DMI_RXP_1

AN41

DMI_RXP_2

AN45

DMI_RXP_3

AJ46

DMI_TXN_0

AJ41

DMI_TXN_1

AM40

DMI_TXN_2

AM44

DMI_TXN_3

AJ47

DMI_TXP_0

AJ42

DMI_TXP_1

AM39

DMI_TXP_2

AM43

DMI_TXP_3

E35

GFX_VID_0

A39

GFX_VID_1

C38

GFX_VID_2

B39

GFX_VID_3

E36

GFX_VR_EN

AM49

CL_CLK

AK50

CL_DATA

AT43

CL_PWROK

AN49

CL_RST#

AM50

CL_VREF

H35

SDVO_CTRL_CLK

K36

SDVO_CTRL_DATA

G39

CLK_REQ#

G40

ICH_SYNC#

A37

12
12

TEST_1

R32

TEST_2

LE88CLPM C0 QP21_FCBGA1299~D

DDR MUXINGCLKDMIGRAPHICS VIDMEMISC

RSVD CFG PM NC

2

RSVD10
RSVD11
RSVD12
RSVD13
RSVD14

RSVD20
RSVD21
RSVD22
RSVD23
RSVD24
RSVD25
RSVD26
RSVD27
RSVD28
RSVD29
RSVD30
RSVD31
RSVD32
RSVD33
RSVD34
RSVD35
RSVD36
RSVD37
RSVD38
RSVD39
RSVD40
RSVD41
RSVD42
RSVD43

CFG_10
CFG_11
CFG_12
CFG_13
CFG_14
CFG_15
CFG_16
CFG_17
CFG_18
CFG_19
CFG_20

PM_BM_BUSY#

PM_DPRSTP#
PM_EXT_TS#_0
PM_EXT_TS#_1

PWROK

THERMTRIP#

DPRSLPVR

2

RSVD1
RSVD2
RSVD3
RSVD4
RSVD5
RSVD6
RSVD7
RSVD8
RSVD9

CFG_0
CFG_1
CFG_2
CFG_3
CFG_4
CFG_5
CFG_6
CFG_7
CFG_8
CFG_9

RSTIN#

NC_1
NC_2
NC_3
NC_4
NC_5
NC_6
NC_7
NC_8

NC_9
NC_10
NC_11
NC_12
NC_13
NC_14
NC_15
NC_16

Strap Pin Table

P36
P37
R35
N35
AR12
AR13
AM12
AN13
J12
AR37
AM36
AL36
AM37
D20

H10
B51
BJ20
BK22
BF19
BH20
BK18
BJ18
BF23
BG23
BC23
BD24
BH39
AW20
BK20
C48
D47
B44
C44
A35
B37
B36
B34
C34

P27
N27
N24
C21
C23

CFG5

F23
N23
G23
J20

CFG9

C20
R24
L23
J23
E23
E20
K23

CFG16

M20
M24
L32

CFG19

N33

CFG20

L35

PM_BMBUSY#

G41

H_DPRSTP#

L39

PM_EXTTS#0

L36

PM_EXTTS#1

J36

ICH_PWRGD

AW49

PLTRST1#_R

AV20

THERMTRIP_MCH#

N20

DPRSLPVR

G36

BJ51
BK51
BK50
BL50
BL49
BL3
BL2
BK1
BJ1
E1
A5
C51
B50
A50
A49
BK2

1

DMI X2 Select

CFG5

PCI Express

CFG9

Graphic Lane

FSB Dynamic

CFG16

ODT

DMI Lane

CFG19

Reversal

SDVO/PCIE
Concurrent

CFG20

Operation

SDVO_CRTL_DATA

Low = DMI x 2
High = DMI x 4 (Default)

Low = Reverse Lane
High = Normal O p e r a t i o n ( Default)

Low=Dynamic O D T Disable
High=Dynamic ODT Enable(default)

Low=Normal (default)
High=Lane Reversed

Low=Only SDVO or PCIEx1 is
operational (defaults)

High=SDVO and P C I E x 1 a r e o p e rating
simultaneously via PEG port

Low=No SDVO Device Present
(default)

High=SDVO Dev i ce Present

CFG[3:17] have internal pullup

CFG5

1 2

R365 4.02K_0402_1%~D@

CFG9

1 2

R368 4.02K_0402_1%~D@

CFG16

1 2

R372 4.02K_0402_1%~D@

CPU_MCH_BSEL0 <6,8>
CPU_MCH_BSEL1 <6,8>

CPU_MCH_BSEL2 <6,8>
T63
T64

T65
T66
T67

T68
T69
T70
T71
T72
T73

T74
T75

CFG[18:19] have internal pulldown

CFG19

1 2

R373 4.02K_0402_1%~D@

CFG20

1 2

R374 4.02K_0402_1%~D@

PM_BMBUSY# <22>
H_DPRSTP# <8,21,45>

PM_EX TTS#0 <17>

PM_EX TTS#1 <16>

ICH_PWRGD <22,39>

THERMTRIP_MCH# <15>

DPRSLPVR <22,45>

R589

0_0402_5%~D@

R583

0_0402_5%~D

R36

100_0402_5%~D

THERMTRIP_MCH#

PM_EXTTS#0

PM_EXTTS#1

12

12

PLTRST1#_R

12

R358

1 2

56_0402_5%~D

+3.3V_RUN

R352

10K_0402_5%~D

R354

10K_0402_5%~D

SB_NB_PCIE_RST# <20>

PLTRST1# <20,32>

+1.05V_VCCP

DELL CONFIDENTIAL/PROPRIETARY

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, M/B LA-3751P

401490

10 48Wednesday, March 28, 2007

1

12

12

of

+3.3V_RUN

A

5

D D

4

3

2

1

DDR_A_BS0<17>
DDR_A_BS1<17>
DDR_A_BS2<17>

DDR_A_DM[0..7]<17>

DDR_A_DQS[0..7]<17>

C C

DDR_A_DQS#[0..7]<17>

DDR_A_MA[0..14]<17>

B B

DDR_A_CAS#<17>
DDR_A_RAS#<17>
DDR_A_WE#<17>

DDR_A_BS0
DDR_A_BS1
DDR_A_BS2

DDR_A_DM0
DDR_A_DM1
DDR_A_DM2
DDR_A_DM3
DDR_A_DM4
DDR_A_DM5
DDR_A_DM6
DDR_A_DM7

DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7

DDR_A_DQS#0
DDR_A_DQS#1
DDR_A_DQS#2
DDR_A_DQS#3

DDR_A_DQS#4

DDR_A_DQS#5
DDR_A_DQS#6

DDR_A_DQS#7

DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA14 DDR_B_MA14

DDR_A_CAS#
DDR_A_RAS#
DDR_A_WE#

SA_RCVEN#

T10

BB19
BK19
BF29

AT45
BD44

BD42
AW38
AW13

AT46

BE48

BB43

BC37

BB16

AT47

BD47

BC41

BA37

BA16

BJ19
BD20
BK27
BH28

BL24
BK28

BJ27

BJ25

BL28
BA28
BC19
BE28
BG30

BJ16

BJ29

BL17
BE18
BA19

AY20

BG8
AY5
AN6

BH6
BB2
AP3

BH7
BC1
AP2

U29D

SA_BS_0
SA_BS_1
SA_BS_2

SA_DM_0
SA_DM_1
SA_DM_2
SA_DM_3
SA_DM_4
SA_DM_5
SA_DM_6
SA_DM_7

SA_DQS_0
SA_DQS_1
SA_DQS_2
SA_DQS_3
SA_DQS_4
SA_DQS_5
SA_DQS_6
SA_DQS_7

SA_DQS#_0
SA_DQS#_1
SA_DQS#_2
SA_DQS#_3
SA_DQS#_4
SA_DQS#_5
SA_DQS#_6
SA_DQS#_7

SA_MA_0
SA_MA_1
SA_MA_2
SA_MA_3
SA_MA_4
SA_MA_5
SA_MA_6
SA_MA_7
SA_MA_8
SA_MA_9
SA_MA_10
SA_MA_11
SA_MA_12
SA_MA_13
SA_MA_14

SA_CAS#
SA_RAS#
SA_WE#

SA_RCVEN#

LE88CLPM C0 QP21_FCBGA1299~D

SA_DQ_0
SA_DQ_1
SA_DQ_2
SA_DQ_3
SA_DQ_4
SA_DQ_5
SA_DQ_6
SA_DQ_7
SA_DQ_8

SA_DQ_9
SA_DQ_10
SA_DQ_11
SA_DQ_12
SA_DQ_13
SA_DQ_14
SA_DQ_15
SA_DQ_16
SA_DQ_17
SA_DQ_18
SA_DQ_19
SA_DQ_20
SA_DQ_21
SA_DQ_22
SA_DQ_23
SA_DQ_24
SA_DQ_25
SA_DQ_26
SA_DQ_27
SA_DQ_28
SA_DQ_29
SA_DQ_30
SA_DQ_31
SA_DQ_32
SA_DQ_33
SA_DQ_34
SA_DQ_35
SA_DQ_36
SA_DQ_37
SA_DQ_38
SA_DQ_39
SA_DQ_40
SA_DQ_41
SA_DQ_42
SA_DQ_43

DDR SYSTEM MEMORY A

SA_DQ_44
SA_DQ_45
SA_DQ_46
SA_DQ_47
SA_DQ_48
SA_DQ_49
SA_DQ_50
SA_DQ_51
SA_DQ_52
SA_DQ_53
SA_DQ_54
SA_DQ_55
SA_DQ_56
SA_DQ_57
SA_DQ_58
SA_DQ_59
SA_DQ_60
SA_DQ_61
SA_DQ_62
SA_DQ_63

DDR_A_D0

AR43

DDR_A_D1 DDR_B_BS1

AW44

DDR_A_D2

BA45

DDR_A_D3

AY46

DDR_A_D4

AR41

DDR_A_D5

AR45

DDR_A_D6

AT42

DDR_A_D7

AW47

DDR_A_D8

BB45

DDR_A_D9

BF48

DDR_A_D10

BG47

DDR_A_D11

BJ45

DDR_A_D12

BB47

DDR_A_D13

BG50

DDR_A_D14

BH49

DDR_A_D15

BE45

DDR_A_D16

AW43

DDR_A_D17

BE44

DDR_A_D18

BG42

DDR_A_D19

BE40

DDR_A_D20

BF44

DDR_A_D21

BH45

DDR_A_D22

BG40

DDR_A_D23

BF40

DDR_A_D24

AR40

DDR_A_D25

AW40

DDR_A_D26

AT39

DDR_A_D27

AW36

DDR_A_D28

AW41

DDR_A_D29

AY41

DDR_A_D30

AV38

DDR_A_D31

AT38

DDR_A_D32

AV13

DDR_A_D33

AT13

DDR_A_D34

AW11

DDR_A_D35

AV11

DDR_A_D36

AU15

DDR_A_D37

AT11

DDR_A_D38

BA13

DDR_A_D39

BA11

DDR_A_D40

BE10

DDR_A_D41

BD10

DDR_A_D42

BD8

DDR_A_D43

AY9

DDR_A_D44

BG10

DDR_A_D45

AW9

DDR_A_D46

BD7

DDR_A_D47

BB9

DDR_A_D48

BB5

DDR_A_D49

AY7

DDR_A_D50

AT5

DDR_A_D51

AT7

DDR_A_D52

AY6

DDR_A_D53

BB7

DDR_A_D54

AR5

DDR_A_D55

AR8

DDR_A_D56

AR9

DDR_A_D57

AN3

DDR_A_D58

AM8

DDR_A_D59

AN10

DDR_A_D60

AT9

DDR_A_D61

AN9

DDR_A_D62

AM9

DDR_A_D63

AN11

DDR_B_BS0<16>
DDR_B_BS1<16>
DDR_B_BS2<16>

DDR_B_DM[0..7]<16>

DDR_B_DQS[0..7]<16>

DDR_B_DQS#[0..7]<16>

DDR_B_MA[0..14]<16>

DDR_B_CAS#<16>
DDR_B_RAS#<16>
DDR_B_WE#<16>

T11

DDR_B_BS0
DDR_B_BS2

DDR_B_DM0
DDR_B_DM1
DDR_B_DM2
DDR_B_DM3
DDR_B_DM4
DDR_B_DM5
DDR_B_DM6
DDR_B_DM7

DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4
DDR_B_DQS5
DDR_B_DQS6
DDR_B_DQS7

DDR_B_DQS#0
DDR_B_DQS#1
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS#4
DDR_B_DQS#5
DDR_B_DQS#6
DDR_B_DQS#7

DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13

DDR_B_CAS#
DDR_B_RAS#
DDR_B_WE#

SB_RCVEN#

AY17
BG18
BG36

AR50
BD49
BK45

BL39

BH12

AW2

AT50
BD50
BK46
BK39

BJ12

AU50
BC50

BL45
BK38
BK12

BC18
BG28
BG25

AW17

BF25
BE25
BA29
BC28
AY28
BD37
BG17
BE37
BA39
BG13
BE24

BE17
AV16
BC17

AY18

BJ7

BF3

BL7
BE2
AV2

BK7
BF2
AV3

U29E

SB_BS_0
SB_BS_1
SB_BS_2

SB_DM_0
SB_DM_1
SB_DM_2
SB_DM_3
SB_DM_4
SB_DM_5
SB_DM_6
SB_DM_7

SB_DQS_0
SB_DQS_1
SB_DQS_2
SB_DQS_3
SB_DQS_4
SB_DQS_5
SB_DQS_6
SB_DQS_7

SB_DQS#_0
SB_DQS#_1
SB_DQS#_2
SB_DQS#_3
SB_DQS#_4
SB_DQS#_5
SB_DQS#_6
SB_DQS#_7

SB_MA_0
SB_MA_1
SB_MA_2
SB_MA_3
SB_MA_4
SB_MA_5
SB_MA_6
SB_MA_7
SB_MA_8
SB_MA_9
SB_MA_10
SB_MA_11
SB_MA_12
SB_MA_13
SB_MA_14

SB_CAS#
SB_RAS#
SB_WE#

SB_RCVEN#

LE88CLPM C0 QP21_FCBGA1299~D

SB_DQ_0
SB_DQ_1
SB_DQ_2
SB_DQ_3
SB_DQ_4
SB_DQ_5
SB_DQ_6
SB_DQ_7
SB_DQ_8

SB_DQ_9
SB_DQ_10
SB_DQ_11
SB_DQ_12
SB_DQ_13
SB_DQ_14
SB_DQ_15
SB_DQ_16
SB_DQ_17
SB_DQ_18
SB_DQ_19
SB_DQ_20
SB_DQ_21
SB_DQ_22
SB_DQ_23
SB_DQ_24
SB_DQ_25
SB_DQ_26
SB_DQ_27
SB_DQ_28
SB_DQ_29
SB_DQ_30
SB_DQ_31
SB_DQ_32
SB_DQ_33
SB_DQ_34
SB_DQ_35
SB_DQ_36
SB_DQ_37
SB_DQ_38
SB_DQ_39
SB_DQ_40
SB_DQ_41
SB_DQ_42
SB_DQ_43

DDR SYSTEM MEMORY B

SB_DQ_44
SB_DQ_45
SB_DQ_46
SB_DQ_47
SB_DQ_48
SB_DQ_49
SB_DQ_50
SB_DQ_51
SB_DQ_52
SB_DQ_53
SB_DQ_54
SB_DQ_55
SB_DQ_56
SB_DQ_57
SB_DQ_58
SB_DQ_59
SB_DQ_60
SB_DQ_61
SB_DQ_62
SB_DQ_63

AP49
AR51
AW50
AW51
AN51
AN50
AV50
AV49
BA50
BB50
BA49
BE50
BA51
AY49
BF50
BF49
BJ50
BJ44
BJ43
BL43
BK47
BK49
BK43
BK42
BJ41
BL41
BJ37
BJ36
BK41
BJ40
BL35
BK37
BK13
BE11
BK11
BC11
BC13
BE12
BC12
BG12
BJ10
BL9
BK5
BL5
BK9
BK10
BJ8
BJ6
BF4
BH5
BG1
BC2
BK3
BE4
BD3
BJ2
BA3
BB3
AR1
AT3
AY2
AY3
AU2
AT2

DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63

DDR_B_D[0..63] <16>DDR_A_D[0..63] <17>

A A

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, M/B LA-3751P

401490

11 48Wednesday, March 28, 2007

1

A

of

5

D D

U29C

J40

L_BKLT_CTRL

H39

L_BKLT_EN

E39

L_CTRL_CLK

E40

L_CTRL_DATA

C37

L_DDC_CLK

D35

L_DDC_DATA

K40

L_VDD_EN

L41

LVDS_IBG

L43

LVDS_VBG

N41

LVDS_VREFH

N40

LVDS_VREFL

D46

LVDSA_CLK#

C45

LVDSA_CLK

D44

LVDSB_CLK#

E42

LVDSB_CLK

G51

LVDSA_DATA#_0

E51

LVDSA_DATA#_1

F49

C C

B B

A A

LVDSA_DATA#_2

G50

LVDSA_DATA_0

E50

LVDSA_DATA_1

F48

LVDSA_DATA_2

G44

LVDSB_DATA#_0

B47

LVDSB_DATA#_1

B45

LVDSB_DATA#_2

E44

LVDSB_DATA_0

A47

LVDSB_DATA_1

A45

LVDSB_DATA_2

E27

TVA_DAC

G27

TVB_DAC

K27

TVC_DAC

F27

TVA_RTN

J27

TVB_RTN

L27

TVC_RTN

M35

TV_DCONSEL_0

P33

TV_DCONSEL_1

H32

CRT_BLUE

G32

CRT_BLUE#

K29

CRT_GREEN

J29

CRT_GREEN#

F29

CRT_RED

E29

CRT_RED#

K33

CRT_DDC_CLK

G35

CRT_DDC_DATA

F33

CRT_HSYNC

E33

CRT_VSYNC

C32

CRT_TVO_IREF

LE88CLPM C0 QP21_FCBGA1299~D

LVDS TV VGA

PEG_COMPI

PEG_COMPO

PEG_RX#_0
PEG_RX#_1
PEG_RX#_2
PEG_RX#_3
PEG_RX#_4
PEG_RX#_5
PEG_RX#_6
PEG_RX#_7
PEG_RX#_8

PEG_RX#_9
PEG_RX#_10
PEG_RX#_11
PEG_RX#_12
PEG_RX#_13
PEG_RX#_14
PEG_RX#_15

PEG_RX_0
PEG_RX_1
PEG_RX_2
PEG_RX_3
PEG_RX_4
PEG_RX_5
PEG_RX_6
PEG_RX_7
PEG_RX_8

PEG_RX_9
PEG_RX_10
PEG_RX_11
PEG_RX_12
PEG_RX_13
PEG_RX_14
PEG_RX_15

PEG_TX#_0
PEG_TX#_1
PEG_TX#_2
PEG_TX#_3
PEG_TX#_4
PEG_TX#_5
PEG_TX#_6
PEG_TX#_7

PCI-EXPRESS GRAPHICS

PEG_TX#_8
PEG_TX#_9

PEG_TX#_10
PEG_TX#_11
PEG_TX#_12
PEG_TX#_13
PEG_TX#_14
PEG_TX#_15

PEG_TX_0

PEG_TX_1

PEG_TX_2

PEG_TX_3

PEG_TX_4

PEG_TX_5

PEG_TX_6

PEG_TX_7

PEG_TX_8

PEG_TX_9
PEG_TX_10
PEG_TX_11
PEG_TX_12
PEG_TX_13
PEG_TX_14
PEG_TX_15

PEGCOMP

N43
M43

PEG_MRX_GTX_N0

J51

PEG_MRX_GTX_N1

L51

PEG_MRX_GTX_N2

N47

PEG_MRX_GTX_N3

T45

PEG_MRX_GTX_N4

T50

PEG_MRX_GTX_N5

U40

PEG_MRX_GTX_N6

Y44

PEG_MRX_GTX_N7

Y40

PEG_MRX_GTX_N8

AB51

PEG_MRX_GTX_N9

W49

PEG_MRX_GTX_N10

AD44

PEG_MRX_GTX_N11

AD40

PEG_MRX_GTX_N12

AG46

PEG_MRX_GTX_N13

AH49

PEG_MRX_GTX_N14

AG45

PEG_MRX_GTX_N15

AG41

PEG_MRX_GTX_P0

J50

PEG_MRX_GTX_P1

L50

PEG_MRX_GTX_P2

M47

PEG_MRX_GTX_P3

U44

PEG_MRX_GTX_P4

T49

PEG_MRX_GTX_P5

T41

PEG_MRX_GTX_P6

W45

PEG_MRX_GTX_P7

W41

PEG_MRX_GTX_P8

AB50

PEG_MRX_GTX_P9

Y48

PEG_MRX_GTX_P10

AC45

PEG_MRX_GTX_P11

AC41

PEG_MRX_GTX_P12

AH47

PEG_MRX_GTX_P13

AG49

PEG_MRX_GTX_P14

AH45

PEG_MRX_GTX_P15

AG42

PEG_MTX_GRX_C_N0

N45

PEG_MTX_GRX_C_N1

U39

PEG_MTX_GRX_C_N2

U47

PEG_MTX_GRX_C_N3

N51

PEG_MTX_GRX_C_N4

R50

PEG_MTX_GRX_C_N5

T42

PEG_MTX_GRX_C_N6

Y43

PEG_MTX_GRX_C_N7

W46

PEG_MTX_GRX_C_N8

W38

PEG_MTX_GRX_C_N9

AD39

PEG_MTX_GRX_C_N10

AC46

PEG_MTX_GRX_C_N11

AC49

PEG_MTX_GRX_C_N12

AC42

PEG_MTX_GRX_C_N13

AH39

PEG_MTX_GRX_C_N14

AE49

PEG_MTX_GRX_C_N15

AH44

PEG_MTX_GRX_C_P0

M45

PEG_MTX_GRX_C_P1

T38

PEG_MTX_GRX_C_P2

T46

PEG_MTX_GRX_C_P3

N50

PEG_MTX_GRX_C_P4

R51

PEG_MTX_GRX_C_P5

U43

PEG_MTX_GRX_C_P6

W42

PEG_MTX_GRX_C_P7

Y47

PEG_MTX_GRX_C_P8

Y39

PEG_MTX_GRX_C_P9

AC38

PEG_MTX_GRX_C_P10

AD47

PEG_MTX_GRX_C_P11

AC50

PEG_MTX_GRX_C_P12

AD43

PEG_MTX_GRX_C_P13

AG39

PEG_MTX_GRX_C_P14

AE50

PEG_MTX_GRX_C_P15

AH43

4

+VCC_PEG

1 2

R366

24.9_0402_1%~D

PEG_MRX_GTX_N[0..15] <18>

PEG_MRX_GTX_P[0..15] <18>

PEG_MTX_GRX_C_N[0..15] <18>

PEG_MTX_GRX_C_P[0..15] <18>

Place R366 within 500 mil
of the GMCHand avoid routing
next to clock pins

3

U29I

A13

VSS_1

A15

VSS_2

A17

VSS_3

A24

VSS_4

AA21

VSS_5

AA24

VSS_6

AA29

VSS_7

AB20

VSS_8

AB23

VSS_9

AB26

VSS_10

AB28

VSS_11

AB31

VSS_12

AC10

VSS_13

AC13

VSS_14

AC3

VSS_15

AC39

VSS_16

AC43

VSS_17

AC47

VSS_18

AD1

VSS_19

AD21

VSS_20

AD26

VSS_21

AD29

VSS_22

AD3

VSS_23

AD41

VSS_24

AD45

VSS_25

AD49

VSS_26

AD5

VSS_27

AD50

VSS_28

AD8

VSS_29

AE10

VSS_30

AE14

VSS_31

AE6

VSS_32

AF20

VSS_33

AF23

VSS_34

AF24

VSS_35

AF31

VSS_36

AG2

VSS_37

AG38

VSS_38

AG43

VSS_39

AG47

VSS_40

AG50

VSS_41

AH3

VSS_42

AH40

VSS_43

AH41

VSS_44

AH7

VSS_45

AH9

VSS_46

AJ11

VSS_47

AJ13

VSS_48

AJ21

VSS_49

AJ24

VSS_50

AJ29

VSS_51

AJ32

VSS_52

AJ43

VSS_53

AJ45

VSS_54

AJ49

VSS_55

AK20

VSS_56

AK21

VSS_57

AK26

VSS_58

AK28

VSS_59

AK31

VSS_60

AK51

VSS_61

AL1

VSS_62

AM11

VSS_63

AM13

VSS_64

AM3

VSS_65

AM4

VSS_66

AM41

VSS_67

AM45

VSS_68

AN1

VSS_69

AN38

VSS_70

AN39

VSS_71

AN43

VSS_72

AN5

VSS_73

AN7

VSS_74

AP4

VSS_75

AP48

VSS_76

AP50

VSS_77

AR11

VSS_78

AR2

VSS_79

AR39

VSS_80

AR44

VSS_81

AR47

VSS_82

AR7

VSS_83

AT10

VSS_84

AT14

VSS_85

AT41

VSS_86

AT49

VSS_87

AU1

VSS_88

AU23

VSS_89

AU29

VSS_90

AU3

VSS_91

AU36

VSS_92

AU49

VSS_93

AU51

VSS_94

AV39

VSS_95

AV48

VSS_96

AW1

VSS_97

AW12

VSS_98

AW16

VSS_99

LE88CLPM C0 QP21_FCBGA1299~D

VSS

VSS_100
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105
VSS_106
VSS_107
VSS_108
VSS_109
VSS_110
VSS_111
VSS_112
VSS_113
VSS_114
VSS_115
VSS_116
VSS_117
VSS_118
VSS_119
VSS_120
VSS_121
VSS_122
VSS_123
VSS_124
VSS_125
VSS_126
VSS_127
VSS_128
VSS_129
VSS_130
VSS_131
VSS_132
VSS_133
VSS_134
VSS_135
VSS_136
VSS_137
VSS_138
VSS_139
VSS_140
VSS_141
VSS_142
VSS_143
VSS_144
VSS_145
VSS_146
VSS_147
VSS_148
VSS_149
VSS_150
VSS_151
VSS_152
VSS_153
VSS_154
VSS_155
VSS_156
VSS_157
VSS_158
VSS_159
VSS_160
VSS_161
VSS_162
VSS_163
VSS_164
VSS_165
VSS_166
VSS_167
VSS_168
VSS_169
VSS_170
VSS_171
VSS_172
VSS_173
VSS_174
VSS_175
VSS_176
VSS_177
VSS_178
VSS_179
VSS_180
VSS_181
VSS_182
VSS_183
VSS_184
VSS_185
VSS_186
VSS_187
VSS_188
VSS_189
VSS_190
VSS_191
VSS_192
VSS_193
VSS_194
VSS_195
VSS_196
VSS_197
VSS_198

2

AW24
AW29
AW32
AW5
AW7
AY10
AY24
AY37
AY42
AY43
AY45
AY47
AY50
B10
B20
B24
B29
B30
B35
B38
B43
B46
B5
B8
BA1
BA17
BA18
BA2
BA24
BB12
BB25
BB40
BB44
BB49
BB8
BC16
BC24
BC25
BC36
BC40
BC51
BD13
BD2
BD28
BD45
BD48
BD5
BE1
BE19
BE23
BE30
BE42
BE51
BE8
BF12
BF16
BF36
BG19
BG2
BG24
BG29
BG39
BG48
BG5
BG51
BH17
BH30
BH44
BH46
BH8
BJ11
BJ13
BJ38
BJ4
BJ42
BJ46
BK15
BK17
BK25
BK29
BK36
BK40
BK44
BK6
BK8
BL11
BL13
BL19
BL22
BL37
BL47
C12
C16
C19
C28
C29
C33
C36
C41

U29J

C46

VSS_199

C50

VSS_200

C7

VSS_201

D13

VSS_202

D24

VSS_203

D3

VSS_204

D32

VSS_205

D39

VSS_206

D45

VSS_207

D49

VSS_208

E10

VSS_209

E16

VSS_210

E24

VSS_211

E28

VSS_212

E32

VSS_213

E47

VSS_214

F19

VSS_215

F36

VSS_216

F4

VSS_217

F40

VSS_218

F50

VSS_219

G1

VSS_220

G13

VSS_221

G16

VSS_222

G19

VSS_223

G24

VSS_224

G28

VSS_225

G29

VSS_226

G33

VSS_227

G42

VSS_228

G45

VSS_229

G48

VSS_230

G8

VSS_231

H24

VSS_232

H28

VSS_233

H4

VSS_234

H45

VSS_235

J11

VSS_236

J16

VSS_237

J2

VSS_238

J24

VSS_239

J28

VSS_240

J33

VSS_241

J35

VSS_242

J39

VSS_243

K12

VSS_245

K47

VSS_246

K8

VSS_247

L1

VSS_248

L17

VSS_249

L20

VSS_250

L24

VSS_251

L28

VSS_252

L3

VSS_253

L33

VSS_254

L49

VSS_255

M28

VSS_256

M42

VSS_257

M46

VSS_258

M49

VSS_259

M5

VSS_260

M50

VSS_261

M9

VSS_262

N11

VSS_263

N14

VSS_264

N17

VSS_265

N29

VSS_266

N32

VSS_267

N36

VSS_268

N39

VSS_269

N44

VSS_270

N49

VSS_271

N7

VSS_272

P19

VSS_273

P2

VSS_274

P23

VSS_275

P3

VSS_276

P50

VSS_277

R49

VSS_278

T39

VSS_279

T43

VSS_280

T47

VSS_281

U41

VSS_282

U45

VSS_283

U50

VSS_284

V2

VSS_285

V3

VSS_286

LE88CLPM C0 QP21_FCBGA1299~D

VSS

VSS_287
VSS_288
VSS_289
VSS_290
VSS_291
VSS_292
VSS_293
VSS_294
VSS_295
VSS_296
VSS_297
VSS_298
VSS_299
VSS_300
VSS_301
VSS_302
VSS_303
VSS_304
VSS_305

VSS_306
VSS_307
VSS_308
VSS_309
VSS_310
VSS_311
VSS_312
VSS_313

1

W11
W39
W43
W47
W5
W7
Y13
Y2
Y41
Y45
Y49
Y5
Y50
Y11
P29
T29
T31
T33
R28

AA32
AB32
AD32
AF28
AF29
AT27
AV25
H50

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, M/B LA-3751P

401490

12 48Wednesday, March 28, 2007

1

A

of

5

4

3

2

1

45mA Max.

+1.25V_RUN_HPLL +1 . 2 5V_RUN

22U_0805_6.3V6M~D

0.1U_0402_16V4Z~D
C572

C571

1

1

2

2

45mA Max.

22U_0805_6.3V6M~D

0.1U_0402_16V4Z~D
C575

C574

1

1

2

2

+1.25V_RUN

1

2

C566

0.1U_0402_16V4Z~D

1 2

22U_0805_6.3V6M~D

0_0805_5%~D

1U_0603_10V4Z~D

1

2

C582

R406

1 2

0_0603_5%~D

1

2

R408

10U_0805_4VAM~D

C583

100U_D2E_6.3VM_R18M~D

1

C558

+

2

+1.25V_RUN

+1.5V_RUN

0.022U_0402_16V7K~D
C584

1

2

0.1U_0402_16V4Z~D

1

2

4.7U_0603_6.3V4Z~D

1

2

L33

22U_0805_6.3V6M~D

C552

0.1U_0402_16V4Z~D

1

2

C597

1

2

+1.05V_VCCP

0.47U_0402_10V4Z~D

1

C537

2

2.2U_0603_6.3V6K~D

C544

1

2

+1.25V_RUN_AXD

12

1U_0603_10V4Z~D

1

+1.25V_RUN

2

+1.8V_SM_CK

0.1U_0402_16V4Z~D

1

+VCC_PEG

2

0.47U_0402_10V4Z~D
C577

1

2

0.47U_0402_10V4Z~D
C578

220U_D2_4VY_R15M~D

C542

+1.25V_RUN

BLM18AG121SN1D_0603~D

+1.25V_RUN

+3.3V_RUN

1

+

C535

2

4.7U_0603_6.3V4Z~D

C543

1

2

C551

1

2

C591

+VCC_RXR_DMI

C576

D D

+1.8V_SUS +1.8V_SM_CK

C C

B B

A A

L41

BLM18AG121SN1D_0603~D

BLM18PG181SN1_0603~D

BLM18PG181SN1_0603~D

1 2

1 2

Place CAPs close to
VCC_AXF (pin A21, B21, B23)

+1.25V_RUN

C589

12

L32

L34

1_0603_5%~D

12

R416

1

C594
10U_0805_4VAM~D

2

10U_0805_4VAM~D

1U_0603_10V4Z~D

C590

1

1

2

2

22U_0805_6.3V6M~D

0.1U_0402_16V4Z~D
C593

C592

1

1

C549

C557

2

2

+VCC_PEG+1.05V_VCCP

220U_D2_4VY_R15M~D

10U_0805_4VAM~D

1

C548

1

+

2

2

+VCC_RXR_DMI+1.05V_VCCP

220U_D2_4VY_R15M~D

10U_0805_4VAM~D

1

C556

1

+

2

2

U29H

U13

VTT_1

U12

VTT_2

U11

VTT_3

U9

VTT_4

U8

VTT_5

U7

VTT_6

U5

VTT_7

U3

VTT_8

U2

VTT_9

U1

VTT_10

T13

VTT_11

T11

VTT_12

T10

VTT_13

T9

VTT_14

T7

VTT_15

T6

VTT_16

T5

VTT_17

T3

VTT_18

T2

VTT_19

R3

VTT_20

R2

VTT_21

R1

VTT_22

AT23

VCC_AXD_1

AU28

VCC_AXD_2

AU24

VCC_AXD_3

AT29

VCC_AXD_4

AT25

VCC_AXD_5

AT30

VCC_AXD_6

AR29

VCC_AXD_NCTF

B23

VCC_AXF_1

B21

VCC_AXF_2

A21

VCC_AXF_3

AJ50

VCC_DMI

BK24

VCC_SM_CK_1

BK23

VCC_SM_CK_2

BJ24

VCC_SM_CK_3

BJ23

VCC_SM_CK_4

A43

VCC_TX_LVDS

C40

VCC_HV_1

B40

VCC_HV_2

AD51

VCC_PEG_1

W50

VCC_PEG_2

W51

VCC_PEG_3

V49

VCC_PEG_4

V50

VCC_PEG_5

AH50

VCC_RXR_DMI_1

AH51

VCC_RXR_DMI_2

A7

VTTLF1

F2

VTTLF2

AH1

VTTLF3

0.47U_0402_10V4Z~D

1

2

LE88CLPM C0 QP21_FCBGA1299~D

+1.05V_VCCP

CRT

VTT

PLL

LVDS PEG

AXD

AXF

SM

CLK

POWER

TV

PEG

DMI

VTTLF

D16

2 1

RB751V_SOD323-2~D

VCCSYNC

VCCA_CRT_DAC_1
VCCA_CRT_DAC_2

VCCA_DAC_BG
VSSA_DAC_BG

VCCA_DPLLA
VCCA_DPLLB

VCCA_HPLL

VCCA_MPLL

VCCA_LVDS
VSSA_LVDS

VCCA_PEG_BG
VSSA_PEG_BG

VCCA_PEG_PLL

VCCA_SM_1
VCCA_SM_2
VCCA_SM_3
VCCA_SM_4
VCCA_SM_5
VCCA_SM_7
VCCA_SM_8

VCCA_SM_9
VCCA_SM_10
VCCA_SM_11

VCCA_SM_NCTF_1
VCCA_SM_NCTF_2

VCCA_SM_CK_1
VCCA_SM_CK_2

VCCA_TVA_DAC_1
VCCA_TVA_DAC_2
VCCA_TVB_DAC_1
VCCA_TVB_DAC_2
VCCA_TVC_DAC_1
VCCA_TVC_DAC_2

TV/CRT

VCCD_CRT

VCCD_TVDAC

VCCD_QDAC

VCCD_HPLL

VCCD_PEG_PLL

LVDS

VCCD_LVDS_1
VCCD_LVDS_2

R417

1 2

10_0603_5%~D

J32
A33

B33

A30
B32

B49
H49
AL2
AM2

A41
B41

K50
K49

U51

AW18
AV19
AU19
AU18
AU17
AT22
AT21
AT19
AT18
AT17
AR17
AR16

BC29
BB29

C25
B25
C27
B27
B28
A28

M32
L29

N28

AN2
U48

J41
H42

+3.3V_RUN

+1.25V_RUN_HPLL
+1.25V_RUN_MPLL

+1.25V_RUN_PEGPLL

+VCCA_SM

C559

1

2

+VCCA_SM_CK

C563

+1.25V_RUN_PEGPLL

0.1U_0402_16V4Z~D

C554

1

2

1U_0603_10V4Z~D

1

2

C560

1

2

0.1U_0402_16V4Z~D

+3.3V_RUN

4.7U_0603_6.3V4Z~D

C564

1

2

C550

C561

1

2

1

2

22U_0805_6.3V6M~D

0.1U_0402_16V4Z~D

22U_0805_6.3V6M~D

C562

1U_0603_10V4Z~D

C565

1

2

+1.25V_RUN

C642

1

2

L37

12

BLM18AG121SN1D_0603~D

L38

BLM18AG121SN1D_0603~D

0.1U_0402_16V4Z~D

C573

1

2

+1.25V_RUN+1.25V_RUN_MPLL

12

+1.25V_RUN_PEGPLL +1.25V_RUN

0.1U_0402_16V4Z~D

C568

1

2

1_0402_5%~D

R409

1

C567
10U_0805_4VAM~D

2

L35

BLM21PG221SN1D_0805~D

12

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, M/B LA-3751P

401490

13 48Wednesday, March 28, 2007

1

A

of

5

4

3

2

1

+1.05V_VCCP

22U_0805_6.3V6M~D

0.22U_0402_10V4Z~D

C617

C620

C604

C614

+1.05V_VCCP

0.22U_0402_10V4Z~D

1

2

0.1U_0402_10V7K~D

1

2

0.22U_0402_10V4Z~D

1

2

0.1U_0402_10V7K~D

1

2

U29F

AB33

VCC_NCTF_1

AB36

VCC_NCTF_2

AB37

VCC_NCTF_3

AC33

VCC_NCTF_4

AC35

VCC_NCTF_5

AC36

VCC_NCTF_6

AD35

VCC_NCTF_7

AD36

VCC_NCTF_8

AF33

VCC_NCTF_9

AF36

VCC_NCTF_10

AH33

VCC_NCTF_11

AH35

VCC_NCTF_12

AH36

VCC_NCTF_13

AH37

VCC_NCTF_14

AJ33

VCC_NCTF_15

AJ35

VCC_NCTF_16

AK33

VCC_NCTF_17

AK35

VCC_NCTF_18

AK36

VCC_NCTF_19

AK37

VCC_NCTF_20

AD33

VCC_NCTF_21

AJ36

VCC_NCTF_22

AM35

VCC_NCTF_23

AL33

VCC_NCTF_24

AL35

VCC_NCTF_25

AA33

VCC_NCTF_26

AA35

VCC_NCTF_27

AA36

VCC_NCTF_28

AP35

VCC_NCTF_29

AP36

VCC_NCTF_30

AR35

VCC_NCTF_31

AR36

VCC_NCTF_32

Y32

VCC_NCTF_33

Y33

VCC_NCTF_34

Y35

VCC_NCTF_35

Y36

VCC_NCTF_36

Y37

VCC_NCTF_37

T30

VCC_NCTF_38

T34

VCC_NCTF_39

T35

VCC_NCTF_40

U29

VCC_NCTF_41

U31

VCC_NCTF_42

U32

VCC_NCTF_43

U33

VCC_NCTF_44

U35

VCC_NCTF_45

U36

VCC_NCTF_46

V32

VCC_NCTF_47

V33

VCC_NCTF_48

V36

VCC_NCTF_49

V37

VCC_NCTF_50

AL24

VCC_AXM_NCTF_1

AL26

VCC_AXM_NCTF_2

AL28

VCC_AXM_NCTF_3

AM26

VCC_AXM_NCTF_4

AM28

VCC_AXM_NCTF_5

AM29

VCC_AXM_NCTF_6

AM31

VCC_AXM_NCTF_7

AM32

VCC_AXM_NCTF_8

AM33

VCC_AXM_NCTF_9

AP29

VCC_AXM_NCTF_10

AP31

VCC_AXM_NCTF_11

AP32

VCC_AXM_NCTF_12

AP33

VCC_AXM_NCTF_13

AL29

VCC_AXM_NCTF_14

AL31

VCC_AXM_NCTF_15

AL32

VCC_AXM_NCTF_16

AR31

VCC_AXM_NCTF_17

AR32

VCC_AXM_NCTF_18

AR33

VCC_AXM_NCTF_19

LE88CLPM C0 QP21_FCBGA1299~D

POWER

VSS_NCTF_1
VSS_NCTF_2
VSS_NCTF_3
VSS_NCTF_4
VSS_NCTF_5
VSS_NCTF_6
VSS_NCTF_7
VSS_NCTF_8

VSS_NCTF_9
VSS_NCTF_10
VSS_NCTF_11
VSS_NCTF_12
VSS_NCTF_13
VSS_NCTF_14
VSS_NCTF_15
VSS_NCTF_16
VSS_NCTF_17
VSS_NCTF_18
VSS_NCTF_19
VSS_NCTF_20
VSS_NCTF_21

VSS_SCB1
VSS_SCB2
VSS_SCB3
VSS_SCB4
VSS_SCB5
VSS_SCB6

VCC_AXM_1
VCC_AXM_2
VCC_AXM_3
VCC_AXM_4
VCC_AXM_6
VCC_AXM_5
VCC_AXM_7

T27
T37
U24
U28
V31
V35
AA19
AB17
AB35
AD19
AD37
AF17
AF35
AK17
AM17
AM24
AP26
AP28
AR15
AR19
AR28

A3
B2
C1
BL1
BL51
A51

+1.05V_VCCP

AT33
AT31
AK29
AK24
AK23
AJ26
AJ23

+3.3V_RUN

R420

1 2

10_0603_5%~D@

Layout Note:
Place C901 where
LVDS and DDR2 taps

+1.8V_SUS

330U_D2_2.5VM_R15~D

0.1U_0402_10V7K~D
1

C605

C608

2

+

2

1

Layout Note:
Place on the edge

22U_0805_6.3V6M~D

22U_0805_6.3V6M~D

C606

C607

1

1

2

2

+1.05V_VCCP

2

1

D17

3

BAT54CW_SOT323~D@

D D

Layout Note:
370 mil from edge

220U_D2_4VY_R15M~D

1

C602

+

2

C C

B B

Layout Note:
Inside GMCH cavity

C603

1

2

C613

1

2

Layout Note:
Place close to GMCH edge

+1.05V_VCCP

0.22U_0402_10V4Z~D

22U_0805_6.3V6M~D

C616

C615

1

1

2

2

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

C619

C618

1

1

2

2

Layout Note: Inside GMCH cavity

A A

U29G

AT35

VCC_1

AT34

VCC_2

AH28

VCC_3

AC32

VCC_4

AC31

VCC_5

AK32

VCC_6

AJ31

VCC_7

AJ28

VCC_8

AH32

VCC_9

AH31

VCC_10

AH29

VCC_11

AF32

VCC_12

R30

VCC_13

POWER

AU32

VCC_SM_1

AU33

VCC_SM_2

AU35

VCC_SM_3

AV33

VCC_SM_4

AW33

VCC_SM_5

AW35

VCC_SM_6

AY35

VCC_SM_7

BA32

VCC_SM_8

BA33

VCC_SM_9

BA35

VCC_SM_10

BB33

VCC_SM_11

BC32

VCC_SM_12

BC33

VCC_SM_13

BC35

VCC_SM_14

BD32

VCC_SM_15

BD35

VCC_SM_16

BE32

VCC_SM_17

BE33

VCC_SM_18

BE35

VCC_SM_19

BF33

VCC_SM_20

BF34

VCC_SM_21

BG32

VCC_SM_22

BG33

VCC_SM_23

BG35

VCC_SM_24

BH32

VCC_SM_25

BH34

VCC_SM_26

BH35

VCC_SM_27

BJ32

VCC_SM_28

BJ33

VCC_SM_29

BJ34

VCC_SM_30

BK32

VCC_SM_31

BK33

VCC_SM_32

BK34

VCC_SM_33

BK35

VCC_SM_34

BL33

VCC_SM_35

AU30

VCC_SM_36

R20

VCC_AXG_1

T14

VCC_AXG_2

W13

VCC_AXG_3

W14

VCC_AXG_4

Y12

VCC_AXG_5

AA20

VCC_AXG_6

AA23

VCC_AXG_7

AA26

VCC_AXG_8

AA28

VCC_AXG_9

AB21

VCC_AXG_10

AB24

VCC_AXG_11

AB29

VCC_AXG_12

AC20

VCC_AXG_13

AC21

VCC_AXG_14

AC23

VCC_AXG_15

AC24

VCC_AXG_16

AC26

VCC_AXG_17

AC28

VCC_AXG_18

AC29

VCC_AXG_19

AD20

VCC_AXG_20

AD23

VCC_AXG_21

AD24

VCC_AXG_22

AD28

VCC_AXG_23

AF21

VCC_AXG_24

AF26

VCC_AXG_25

AA31

VCC_AXG_26

AH20

VCC_AXG_27

AH21

VCC_AXG_28

AH23

VCC_AXG_29

AH24

VCC_AXG_30

AH26

VCC_AXG_31

AD31

VCC_AXG_32

AJ20

VCC_AXG_33

AN14

VCC_AXG_34

LE88CLPM C0 QP21_FCBGA1299~D

VCC GFX

VCC CORE

VCC SM

VCC_AXG_NCTF_1
VCC_AXG_NCTF_2
VCC_AXG_NCTF_3
VCC_AXG_NCTF_4
VCC_AXG_NCTF_5
VCC_AXG_NCTF_6
VCC_AXG_NCTF_7
VCC_AXG_NCTF_8

VCC_AXG_NCTF_9
VCC_AXG_NCTF_10
VCC_AXG_NCTF_11
VCC_AXG_NCTF_12
VCC_AXG_NCTF_13
VCC_AXG_NCTF_14
VCC_AXG_NCTF_15
VCC_AXG_NCTF_16
VCC_AXG_NCTF_17
VCC_AXG_NCTF_18
VCC_AXG_NCTF_19
VCC_AXG_NCTF_20
VCC_AXG_NCTF_21
VCC_AXG_NCTF_22
VCC_AXG_NCTF_23
VCC_AXG_NCTF_24
VCC_AXG_NCTF_25
VCC_AXG_NCTF_26
VCC_AXG_NCTF_27
VCC_AXG_NCTF_28
VCC_AXG_NCTF_29
VCC_AXG_NCTF_30
VCC_AXG_NCTF_31
VCC_AXG_NCTF_32
VCC_AXG_NCTF_33
VCC_AXG_NCTF_34
VCC_AXG_NCTF_35
VCC_AXG_NCTF_36
VCC_AXG_NCTF_37
VCC_AXG_NCTF_38
VCC_AXG_NCTF_39
VCC_AXG_NCTF_40
VCC_AXG_NCTF_41
VCC_AXG_NCTF_42
VCC_AXG_NCTF_43
VCC_AXG_NCTF_44
VCC_AXG_NCTF_45
VCC_AXG_NCTF_46
VCC_AXG_NCTF_47
VCC_AXG_NCTF_48

VCC GFX NCTFVCC SM LF

VCC_AXG_NCTF_49
VCC_AXG_NCTF_50
VCC_AXG_NCTF_51
VCC_AXG_NCTF_52
VCC_AXG_NCTF_53
VCC_AXG_NCTF_54
VCC_AXG_NCTF_55
VCC_AXG_NCTF_56
VCC_AXG_NCTF_57
VCC_AXG_NCTF_58
VCC_AXG_NCTF_59
VCC_AXG_NCTF_60
VCC_AXG_NCTF_61
VCC_AXG_NCTF_62
VCC_AXG_NCTF_63
VCC_AXG_NCTF_64
VCC_AXG_NCTF_65
VCC_AXG_NCTF_66
VCC_AXG_NCTF_67
VCC_AXG_NCTF_68
VCC_AXG_NCTF_69
VCC_AXG_NCTF_70
VCC_AXG_NCTF_71
VCC_AXG_NCTF_72
VCC_AXG_NCTF_73
VCC_AXG_NCTF_74
VCC_AXG_NCTF_75
VCC_AXG_NCTF_76
VCC_AXG_NCTF_77
VCC_AXG_NCTF_78
VCC_AXG_NCTF_79
VCC_AXG_NCTF_80
VCC_AXG_NCTF_81
VCC_AXG_NCTF_82
VCC_AXG_NCTF_83

VCC_SM_LF1
VCC_SM_LF2
VCC_SM_LF3
VCC_SM_LF4
VCC_SM_LF5
VCC_SM_LF6
VCC_SM_LF7

T17
T18
T19
T21
T22
T23
T25
U15
U16
U17
U19
U20
U21
U23
U26
V16
V17
V19
V20
V21
V23
V24
Y15
Y16
Y17
Y19
Y20
Y21
Y23
Y24
Y26
Y28
Y29
AA16
AA17
AB16
AB19
AC16
AC17
AC19
AD15
AD16
AD17
AF16
AF19
AH15
AH16
AH17
AH19
AJ16
AJ17
AJ19
AK16
AK19
AL16
AL17
AL19
AL20
AL21
AL23
AM15
AM16
AM19
AM20
AM21
AM23
AP15
AP16
AP17
AP19
AP20
AP21
AP23
AP24
AR20
AR21
AR23
AR24
AR26
V26
V28
V29
Y31

VCCSM_LF1

AW45

VCCSM_LF2

BC39

VCCSM_LF3

BE39

VCCSM_LF4

BD17

VCCSM_LF5

BD4

VCCSM_LF6

AW8
AT6

VCCSM_LF7

C621

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

C622

C623

1

1

2

1

2

2

0.22U_0402_10V4Z~D

0.22U_0402_10V4Z~D

C624

C625

1

2

1U_0402_6.3V4Z~D

0.47U_0402_10V4Z~D

C626

1

2

1U_0402_6.3V4Z~D

C627

1

1

2

2

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, M/B LA-3751P

401490

14 48Wednesday, March 28, 2007

1

A

of

5

4

3

2

1

VGA fan control and Tachometer

+15V_ALW

C1441

1 2

0.1U_0603_50V4Z~D

FAN2_PWM

D D

+15V_ALW

5

IN+

6

IN-

1 2

120K_0402_5%~D

8

P

7

O

G

U73B
LM358DR2G_SOIC8~D

4

R1605

FAN2VREF

0.22U_0603_10V7K~D
FAN2_VFB

1

C1442

2

2200P_0402_50V7K~D

R1606 78.7K_0402_1%~D

120K_0402_5%~D

R1607

1 2

3
2

C1443

1 2

8

P

IN+
IN-

FAN2_ON

1

O

G

U73A
LM358DR2G_SOIC8~D

4

12

D47

2 1

+5V_RUN

6

2

1

D

Q182

G

22U_0805_6.3V6M~D

S

4 5

1000P_0402_50V7K~D@

C1445

1

2

SI3456BDV-T1-E3_TSOP6~D

FAN2_5V

MOLEX_53398-0371~D

3

RB751S40T1_SOD523-2~D@

C1439

1

2

+3.3V_RUN

12

R1270
10K_0402_5%~D

FAN2_TACH <36>

1000P_0402_50V7K~D@

C1444

1

JFAN2

1

1

2

2

3

2

3

R438

VSET = 0.865V=

x 3.3V

R436+R438

Tp-70

VSET =

=> Tp = 88.2 C

21

Place close to JDIMA

+5V_SUS

12

R771

2.21K_0603_1%~D

VCP2

1

C750
2200P_0402_50V7K~D

2

12

R772
10K_0603_1%_TSM1A103F34D3RZ~D

Q102

13

D

2N7002W-7-F_SOT323-3~D

2

G

S

+3.3V_SUS

12

R773
10K_0402_5%~D

Place Q41 close to JDIMMB
REM_DIODE3_N, REM_DIODE3_P routing together.

Trace width / Spacing = 10 / 10 mil

5V_CAL_SIO#

Main fan cont ro l a nd Tachometer

Place under CPU

RB751S40T1_SOD523-2~D@

H_THERMTRIP#<7>

C630

1

2

+1.05V_VCCP

+3.3V_RUN

22U_0805_6.3V6M~D

+1.05V_VCCP

12

R424
10K_0402_5%~D

12

FAN1_TACH <36>

R414
0_0402_5%~D

+FAN1_VOUT
FAN1_TACH_FB

MOLEX_53398-0371~D

R425

1 2

2.2K_0402_5%~D

MMST3904-7-F_SOT323-3~D

R427

1 2

2.2K_0402_5%~D@

MMST3904-7-F_SOT323-3~D@

5

1
2
3

+3.3V_SUS

2

B

Q38

+3.3V_SUS

2

B

Q39

JFAN1

1
2
3

12

R423

8.2K_0402_5%~D

C

E

3 1

12

R426

8.2K_0402_5%~D

C

E

3 1

C C

D19

2 1

B B

A A

+3.3V_SUS

THERMATRIP1#

1

C628

0.1U_0402_16V4Z~D

2

THERMATRIP2#

1

C632

0.1U_0402_16V4Z~D@

2

2

C633

1

2200P_0402_50V7K~D@

Place C636 close to Guardian pin as possible

H_THERMDA<7>

H_THERMDC<7>

R428

1 2

49.9_0603_1%~D

THERMTRIP_VGA#<18>THERMTRIP_MCH#<10>

Place C633 close to the Q40 as possible

C

Q40

2

B

E

MMST3904-7-F_SOT323-3~D

3 1

C636

470P_0402_50V7K~D

0.1U_0402_16V4Z~D

1

+RTC_CELL

C637

2

+3.3V_SUS

0.1U_0402_16V4Z~D

+3.3V_SUS

C639

1 2

10K_0402_5%~D@

1 2

10K_0402_5%~D@

4

R196

R194

332K_0402_1%~D

1

2

+3.3V_RUN

12

R186

1

2

R436

1 2

MDC_RST_DIS#

SIO_GFX_PWR

R187

8.2K_0402_5%~D

2

C634
2200P_0402_50V7K~D

1

1

2

C638

ICH_PWRGD#<39>

0.1U_0402_16V4Z~D

118K_0402_1%~D

12

R438

2.2K_0402_5%~D@

12

THERM_B3

MMST3904-7-F_SOT323-3~D@

SUSPWROK<39>

C100

Place C634 close to the
Guardian pins as possible

THRM_SMBDAT<36,46>
THRM_SMBCLK<36,46>

REM_DIODE1_P
REM_DIODE1_N

+3VSUS_THRM

R429 1K_0402_5%~D

1 2

R432 1K_0402_5%~D

1 2
THERMATRIP1#
THERMATRIP2#
THERMATRIP3#

2200P_0402_50V7K~D

R437

MDC_RST_DIS#<25>
SIO_GFX_PWR<18>

12

C

C203

E

3 1

1K_0402_5%~D

1 2

R433

8.2K_0402_5%~D

0.1U_0402_16V4Z~D@

1

2

2

1

AUDIO_AVDD_ON<26>

+3.3V_SUS

2

B

Q76

PWR_MON<45>

U31

11

SMDATA

12

SMBCLK

38

DP1

37

DN1

41

DP2

40

DN2

35

3V_SUS

21

RTC_PWR3V

23

+FAN1_VOUT

FAN2_PWM

MDC_RST_DIS#
SIO_GFX_PWR
5V_CAL_SIO#

AUDIO_AVDD_ON

VSUS_PWRGD

16

3V_PWROK#

17

THERMTRIP1#

18

THERMTRIP2#

19

THERMTRIP3#

42

VSET

26

XEN

34

VSS

7

FAN_OUT

8

FAN_OUT

39

FAN_DAC1

10

GPIO1

13

GPIO2

14

GPIO3

15

GPIO4

22

GPIO5

36

GPIO6/FAN_DAC2

49

PAD_GND

EMC4001_QFN48~D

POWER_SW#

ACAVAIL_CLR

THERMTRIP_SIO

LDO_SHDN#/ADDR

SMBus address: 2F

THERMATRIP3#

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

VCP1
VCP2

DP3
DN3

DP4
DN4

DP5
DN5

ATF_INT#

SYS_SHDN#

LDO_POK
LDO_SET
LDO_OUT

LDO_OUT

LDO_IN
LDO_IN

VDD_3V
VDD_5V

VDD_5V

43
46

45
44

48
47

2
1

20
3
4
25
24
27
33
28
32

31

30
29

9
5

6

+5V_RUN

C645

1

2

VCP2
REM_DIODE3_P

REM_DIODE3_N
REM_DIODE4_P

REM_DIODE4_N

7.5K_0402_5%~D
LDO_SET

+3V_LDOIN

10U_0805_10V4Z~D

C646

1

2

R434

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

2

ATF_INT#

ATF_INT# <35>

POWER_SW# <36,37>

ACAV_IN <18,36,46>

12

0.1U_0402_16V4Z~D

1

C649

2

2200P_0402_50V7K~D

Diode circuit at DP4/DN4 is used for skin temp sensor
(placed optimally between CPU, MCH and GPU)

1

C418

2

2200P_0402_50V7K~D

R96

10K_0402_5%~D

+3.3V_SUS

2.5V_RUN_PWRGD <39>

1

1

2

1

2

1

2

C640

2

0_1210_5%~D

C643

1U_0603_10V4Z~D

@

+3.3V_RUN

1

C647
10U_0805_10V4Z~D

2

C644

C641

1

2

C648

C

Q41

2

B

E

2

B

12

+3.3V_SUS

R430

10K_0402_5%~D

R431

10K_0402_5%~D@

+2.5V_RUN

10U_0805_10V4Z~D@

+3.3V_RUN

R439

12

2200P_0402_50V7K~D@

MMST3904-7-F_SOT323-3~D

3 1

C649 close to Guardian and
C650 close to diode Q41

C

Q19

2200P_0402_50V7K~D@

MMST3904-7-F_SOT323-3~D

C418 close to Guardian and
C904 close to diode Q19

R1608

0_0402_5%~D@

1 2

THERM_STP# <42>

+RTC_CELL

Voltage margining
circuit for LDO output

LDO_SET

For Vmargin, stuff Ra=31.6K and Rb=30K
For production, stuff Rb=1K only

12

E

3 1

+3.3V_ALW

12

DELL CONFIDENTIAL/PROPRIETARY

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.
SCHEMATIC, M /B LA-3751P

401490

C650

+2.5V_RUN

12

R485

12

R441

1

1

2

1

C904

2

THERMTRIP_SIO <35>

31.6K_0402_1%~D@

Ra

1K_0402_1%~D

Rb

15 48Wednesday, March 28, 2007

A

of