COMPAL LA-3751P Schematics

5

COMPAL CONFIDENTIAL

4

3

2

1

MODEL NAME :
PCB NO :

D D

BOM P/N :

LA-3751P (DA800008Y0L)

46149031L0121

IAQ20

Converse

C C

uFCPGA Mobile Merom
Intel Crestline + ICH8M

21-05-2007

REV : 0.1(X00)

B B

@ : Nopop Component

A A

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, M/B LA-3751P

401490

148Wednesday, March 28, 2007

1

A

of

5

Compal confidential

4

3

2

1

Pentium-M

Merom -4MB (Socket P)

uFCPGA CPU

D D

NB8E-GLM-A2 G84

DVI CONN.

+5V_RUN

page 18

DVI

VGA BOARD

with LVDS CONN.

LS-3751P

RGB and TV OUT

VGA CONN.

page 18

CRT CONN.

PCIE 16X

& TV-OUT

Docking

C C

Port

page 34

USB7

IDSEL:AD17
(PIRQA/B#,GNT#2,REQ#2)

Memory Card &1394
Controller
RICOH R5C833P

+3.3V_R5C833

5 in 1 CONN.

B B

page 30 page 30

+5V_RUN

Docking Buffer

+5V_RUN

page 30

1394 CONN.

USB6

Smart Card
OZ77CR6

page 32

page 33

3.3V 33MHz

Express
Card

USB2

MINI

ROBSON

page 31

Slot

page 32

Biometric Reader

page 32

A A

page 19

MINI

WLAN

page 31page 32

GIGA Enthernet

BCM5756MKFBG

+3.3V_LAN
+2.5V_LAN
+1.2V_LAN

RJ45 with
Giga Magnetic

+2.5V_LAN

ST M25P16

+3.3V_ALW

page 36

Touch Pad Int.KBD

SPI

+1.05V_VCCP
+VCC_CORE

H_A#(3..35) H_D#(0..63)

478pin

System Bus

FSB 800 MHz

INTEL

+1.25V_RUN
+1.5V_RUN
+1.8V_SUS
+1.05V_VCCP
+3.3V_RUN
+1.8V_RUN

PCI BUS

PCIE BUS

page 28,29

page 29

MEC5025

+RTC_CELL
+3.3V_ALW

Crestline

1299pin BGA

DMI

+1.5V_RUN
100MHz

ICH8-M
676 BGA

Intel 82801HBM

+1.25V_RUN
+3.3V_RUN
+3.3V_SUS
+1.05V_VCCP

page 20,21,22,23

LPC BUS

+3.3V_RUN 33MHz

page 36

ECE5028
Super I/O

BC BUS

ECE1077

+3.3V_ALW

page 37 page 37page 37

page 7,8,9

page 10,11,12,13,14

Azalia

SATA
PATA

48MHz / 480Mb

page 35

Multi-media

Board

Switch Board

LED Board

LS-3752P LS-3753P

5

Bluetooth

+3.3V_RUN

4

page 32
USB3

LS-2884P

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

Clock Generator
CK505

+3.3V_RUN

Memory BUS (DDR2)

+1.8V_SUS 667MHz

CDROM

+5V_RUN

page 24

USBPORT 0
USBPORT 1
USBPORT 2
USBPORT 3

USB2.0
IO PORT

page 27

USBPORT 4
USBPORT 5
USBPORT 6
USBPORT 7
USBPORT 8
USBPORT 9

page 6

SATA HDD

+5V_HDD

page 24

Ext. USB
Ext. USB
EXPRESS CARD
BLUETOOTH
Ext. USB
Ext. USB
OZ77CR6
Docking
Ext. USB
Ext. USB

2

Fan Control

+3.3V_RUN

page 15

DDRII-DIMM X2

BANK 0, 1, 2, 3, 4 ,5 ,6 ,7 ,8

+0.9V_DDR_VTT
+1.8V_SUS

MDC

page 25 page 25

Azalia Codec

STAC9205

+3.3V_RUN
+VDDA

AMP & INT.
Speaker

+5V_RUN

page 26 page 26

Thermal

GUARDIAN III

SMBus

EMC4001

+3.3V_SUS

page 16,17

page 15

RJ11

DC IN &

page 25

HeadPhone
& MIC Jack

+3.3V_RUN

BATT CONN

page 41

3.3V/5V/15V

page 42

1.8V /0.9V/1.25V

page 43

1.5V/1.05V

VCORE

CHARGER

page 44

page 45

page 46

DELL CONFIDENTIAL/PROPRIETARY

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, M/B LA-3751P

401490

248Wednesday, March 28, 2007

1

of

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POWER STATES

State

D D

S0 (Full ON) / M0

S3 (Suspend to RAM) / M1

S4 (Suspend to DISK) / M1 ON ON ON ONOFF

S5 (SOFT OFF) / M1 ON ON ON ONOFFLOW HIGH LOW HIGHLOW

S3 (Suspend to RAM) / M-OFF

S4 (Suspend to DISK) / M-OFF

S5 (SOFT OFF) / M-OFF

Signal

SLP
S3#

HIGH

LOW HIGH HIGH HIGH ON ON ON ONOFF

LOW HIGH HIGH HIGHLOW

LOW HIGH HIGH HIGH LOW ON ONOFF OFF OFF

LOW LOW LOW LOW ON OFF OFF OFF OFF

LOW LOW LOW LOW LOW ON OFF OFF OFF OFF

SLP
S5#

HIGH

S4
STATE#

SLP
S4#

HIGH HIGH HIGH

SLP
M#

HIGH

HIGH

ALWAYS
PLANE

ON

M
PLANE

ON

SUS

RUN

PLANE

PLANE

ON ON ON

CLOCKS

ICH8-M

USB PORT#

0
1
2
3
4
5
6
7

DESTINATION
Rear Right Bottom
Rear Right Top
EXPRESS CARD
Bluetooth
Rear Left Bottom
Rear Left Top
OZ77CR6/Sma r t Card Reader
Docking

8

C C

B B

PM TABLE

State

S0

S3

S5 S4/AC

S5 S4/AC don't exist

power
plane

+15V_ALW
+5V_ALW
+3.3V_ALW +1.8V_SUS
+3.3V_RTC_LDO

ON

ON

ON

+5V_SUS
+3.3V_SUS

ON ON

ON

OFF

OFFOFF

+5V_RUN
+3.3V_RUN
+2.5V_RUN
+1.5V_RUN
+1.25V_RUN
+0.9V_DDR_VTT
+1.05V_VCCP
+VCC_CORE

OFF

OFF

OFF

OZ77CR6

9
UPD+/D-, pin 16/17
DPD+/D-, pin 18/19

EGATED+/D-, pin 20/21

PCI EXPRESS

Lane 1
Lane 2

DESTINATION
MINI CARD 1- Robson
MINI CARD 2- WLAN

Side Bottom
Side Top
ICH8-M
Biometric Reader
SMART CARD

PCI TABLE

Lane 3

R5C833

REQ#/GNT#

REQ#1 / GNT#1AD17 PIRQC, D

PIRQPCI DEVICE IDSEL

Lane 4
Lane 5
Lane 6

A A

AD24 REQ#0 / GNT#0

PIRQADocking

None
EXPRESS CARD
None
GIGA LAN

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, M/B LA-3751P

401490

348Wednesday, March 28, 2007

1

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1

RUN_ON

D D

ADAPTER

FDS6679AZ

(Q106)

+GFX_PWR_SRC

+5V_ALW

SUS_ON

HDDC_EN

+15V_ALW

SI3456BDV

(Q148)

SI3456BDV

(Q111)

+5V_SUS

+5V_HDD

+PWR_SRC

BATTERY

ISL6260

(PU6) (PU2)

CHARGER

C C

RUNPWROK

+VCC_CORE

+1.8V_SUS

ISL6236

DDR_ON

1.25V_RUN_ON

+1.25V_RUN

ISL6236

(PU4)

1.05V_RUN_ON

1.5V_RUN_ON

+1.05V_VCCP +1.5V_RUN

ISL6236

(PU1)

ALWON

+3.3V_ALW

ALWON

RUN_ON

SI4810BDY

(Q154)

AUDIO_AVDD_ON

MAX9789A

+5V_RUN

JUMP

(PJP22)(U41)

0.9V_DDR_VTT_ON

ENAB_3VLAN

SI3456BDV

(Q125)

3.3V_SUS_ON

SI4810BDY

(Q149)

3.3V_RUN_ON

SI4810BDY

(Q157)

WLAN_3V_ENABLE

+VDDA +5V_ODD

SI3456BDV

(Q133)

TPS51100

(PU3)

B B

+3.3V_LAN +3.3V_RUN+3.3V_SUS

+3.3V_WLAN

+0.9V_DDR_VTT

REGCTL_PNP25

REGCTL_PNP12

R1024

MBT35200MT2G PBSS5540Z

(Q126)

(Q127)

+3.3V_R5C833

A A

+2.5V_LAN +1.2V_LAN

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

DELL CONFIDENTIAL/PROPRIETARY

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, M /B LA-3751P

401490

448Wednesday, March 28, 2007

1

of

A

5

4

+3.3V_SUS

3

2

+3.3V_RUN

1

2.2K

ICH_SMBCLK

AJ26

D D

C C

ICH8-M

SIO

ICH_SMBDATA

AD19

LCD_SMBCLK

8

LCD_SMBDAT

7

THRM_SMBCLK

100

THRM_SMBDAT

99

PBAT_SMBCLK

112

PBAT_SMBDAT

111

+3.3V_ALW

8.2K

+3.3V_ALW

4.7K 4.7K

+3.3V_ALW

2.2K 2.2K

2.2K

8.2K

+3.3V_ALW

+3.3V_ALW

+3.3V_ALW

D7B6 911

BCM5756

SMBUS Address [C8]

EXPRESS
CARD

SMBUS Address [TBD]

100

100

3032

MINI WLAN

SMBUS Address [TBD]

8

Graphic BTB CONN

10

12

11

9

10

3

4

inverter

GUARDIAN

EMC4001

CHARGER

ISL88731

BATTERY
Connector

2N7002

MEM_SCLK
MEM_SDATA

2N7002

SMBUS Address [58]

SMBUS Address [2F]

SMBUS Address [12]

SMBUS Address [16]

2.2K 2.2K

197

195

197

195

30

32

DIMMA

SMBUS Address [A0]

DIMMB

SMBUS Address [A4]

MINI
ROBSON

SMBUS Address [TBD]

B B

DOCK_SMBCLK

6

DOCK_SMBDAT

5

+5V_ALW

8.2K 8.2K

+3.3V_ALW

+5V_ALW

39

40

+3.3V_RUN

DOCKING

SMBUS Address [C4, 72, 70, 48]

MEC5025

2.2K 2.2K

CKG_SMBCLK

13

A A

5

CKG_SMBDAT

12

+3.3V_ALW

4

2N7002

2N7002

CLK_SCLK
CLK_SDATA

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

2.2K 2.2K

+3.3V_RUN

2

16

17

CLOCK

GENERATOR

SMBUS Address [D2]

DELL CONFIDENTIAL/PROPRIETARY

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, M/B LA-3751P

401490

548Wednesday, March 28, 2007

1

of

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5

4

3

2

1

CLK_ICH_48M

1

C708

3.3P_0402_50V8C~D

2

CLK_SMC_48M

1

C774

D D

3.3P_0402_50V8C~D

2

CLK_PCI_TPM

1

C777

3.3P_0402_50V8C~D@

2

CLK_PCI_DOCK

1

C778

3.3P_0402_50V8C~D@

2

CLK_PCI_R5C832

1

C779

3.3P_0402_50V8C~D@

2

CLK_PCI_5025

1

C780

C C

3.3P_0402_50V8C~D@

2

CLK_PCI_5028

1

C781

3.3P_0402_50V8C~D@

2

CLK_ICH_14M

1

C775

3.3P_0402_50V8C~D@

2

CLK_SIO_14M

1

C776

3.3P_0402_50V8C~D@

2

CLK_PCI_ICH

1

C785

B B

3.3P_0402_50V8C~D@

2

PGMODE

0
1

TME PIN 32

0
1

*

ITP_EN

01Pin 5/6 as SRC_10

*

A A

FCTSEL1 PIN43 PIN44 PIN47 PIN48
0=UMA
1=DIS

*

+3.3V_RUN +3.3V_RUN

12

R329

10K_0402_5%~D@

FSA PCI_LOM

12

R391

10K_0402_5%~D@

+3.3V_RUN +3.3V_RUN

R290
10K_0402_5%~D

1 2

Place crystal within
500 mils of CK505

12

R318
10K_0402_5%~D

12

R319

10K_0402_5%~D@

12

R304
10K_0402_5%~D

PCI_ICHPCI_R5C832

CPU_MCH_BSEL0<8,10>

CPU_MCH_BSEL2<8,10>

C99

CLK_ICH_48M<22>
CLK_SMC_48M<32>

CLK_PCI_TPM<28>
CLK_PCI_DOCK<34>

CLK_PCI_R5C832<30>

CLK_PCI_5025<36>

CLK_PCI_5028<35>

CLK_ICH_14M<22>
CLK_SIO_14M<35>

CLK_PCI_ICH<20>

PIN 9
VTT_PWRGD#/PD
CKPWRGD/PD#

Normal Operation
Trusted Mode Enabled

PIN 37

CKG_SMBCLK<36>

Pin 5/6 as CPU_ITP

CKG_SMBDAT<36>

DOT96T DOT96C 96/100M_T 96/100M_C
27M_out 27M SSout SRCT0 SRCC0

5

+3.3V_RUN

C471

1

2

+CK_VDD_48

4.7U_0603_6.3V4Z~D
1

1

C799

2

2

C483

27P_0402_50V8J~D

C484

33P_0402_50V8J~D

CLK_ICH_48M
CLK_SMC_48M

CPU_MCH_BSEL1<8,10>

CLK_PCI_TPM
CLK_PCI_DOCK

CLK_PCI_R5C832
CLK_PCI_5025

CLK_PCI_5028

CLK_ICH_14M
CLK_SIO_14M

CLK_PCI_ICH

+3.3V_RUN

+3.3V_RUN

0.1U_0402_16V4Z~D

1 2

BLM21PG600SN1D_0805~D

0.047U_0402_16V4Z~D

12

12

+CK_VDD_REF

0.047U_0402_16V4Z~D

1

C189

2

12

X1

14.31818MHz_20P_1BX14318CC1A~D
R271 0_0402_5%~D

R273 15_0402_5%~D
R275 15_0402_5%~D
R309 2.2K_0402_5%~D

R314 8.2K_0402_5%~D

R277 33_0402_5%~D
R596 33_0402_5%~D

R280 33_0402_5%~D
R282 15_0402_5%~D

R333 15_0402_5%~D
R284 15_0402_5%~D
R285 15_0402_5%~D

R291 33_0402_5%~D

R295 10K_0402_5%~D@
R298 10K_0402_5%~D@

+3.3V_RUN

R435

1 2

0_0402_5%~D@

D

S

1 3

Q34
2N7002W-7-F_SOT323-3~D

G

2
2

G

Q35
2N7002W-7-F_SOT323-3~D

1 3

D

S

1 2

R440

0_0402_5%~D@

4

L28

1 2

BLM21PG600SN1D_0805~D

+CK_VDD_MAIN2

1 2

1 2
1 2

1 2

1 2
1 2
1 2

1 2
1 2

R265

12

12
12

12
12

12

CLK_PWRGD<22>

CLK_SDATA<31>

2.2K_0402_5%~D

12

L87

C482

R760 1_0603_5%~D
R758 2.2_0603_5%~D

CLK_SCLK<31>

R266

0.1U_0402_16V4Z~D

1

2

1 2
1 2

2.2K_0402_5%~D

12

C481

CLK_SCLK

CLK_SDATA

0.1U_0402_16V4Z~D
C480

1

1

2

2

+CK_VDD_REF
+CK_VDD_48

CLK_XTAL_IN

CLK_XTAL_OUT

FSA

FSC

PCI_LOM
PCI_DOCK
PCI_R5C832
PCI_SIO

CLKREF

PCI_ICH
CLK_PWRGD

PGMODE

CLK_SCLK

CLK_SDATA

+CK_VDD_MAIN1

C477

10U_0805_10V4Z~D

1
49
54
65

30
36

12
18
40

20

19

41
45
23

34
33
32
27

22

43
44

37

39

9

16

17

4
15
21
31
35
42
68

73

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D
C473

C474

1

1

2

2

U28

VDD_SRC
VDD_SRC
VDD_SRC
VDD_SRC

VDD_PCI
VDD_PCI

VDD_CPU
VDD_REF
VDD_48

XTAL_IN

XTAL_OUT

USB_48MHz/FSLA
FSL_B/TEST_MODE
REF_0/FSL_C/TEST_SEL

PCICLK4/FCT_SEL
PCICLK3
PCICLK2/TME
PCICLK1

REF_1

DOT_96/27M
DOT_96#/27M_SS

PCICLK_F0/ITP_EN

CKPWRGD/PD#

PGMODE

SMBCLK

SMBDAT

VSS_SRC
VSS_CPU
VSS_REF
VSS_PCI
VSS_PCI
VSS_48
VSS_SRC

THRM_PAD

SLG8LP550VTR_QFN72_10X10~D

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D
C475

C476

1

R759

1

2

2

1

2

1 2

2.2_0603_5%~D

SLG8LP550

CPU_ITP/SRC_10

CPU_ITP#/SRC_10#

LCD_CLK/SRC_0

LCD_CLK#/SRC_0#

3

10U_0805_10V4Z~D

0.1U_0402_16V4Z~D
C472

1

2

+CK_VDD_A

VDD_A
VSS_A

PCI_STP#

CPU_STP#

CPU_1

CPU_1#

CPU_0

CPU_0#

SRC_9

SRC_9#

CLKREQ_9#

SRC_8

SRC_8#

CLKREQ_8#

SRC_7

SRC_7#

CLKREQ_7#

SRC_6

SRC_6#

CLKREQ_6#

SRC_5

SRC_5#

CLKREQ_5#

SRC_4

SRC_4#

CLKREQ_4#

SRC_3

SRC_3#

CLKREQ_3#

SRC_2

SRC_2#

CLKREQ_2#

SRC_1/SATA

SRC_1#/SATA#

CLKREQ_1#

4.7U_0603_6.3V4Z~D

C478

7
8

H_STP_PCI#

25

H_STP_CPU#

24

MCH_BCLK

11

MCH_BCLK#

10

CPU_BCLK

14

CPU_BCLK#

13

CPU_ITP

6

CPU_ITP#

5

PCIE_MINI1

3

PCIE_MINI1#

2
72

PCIE_MINI2

70

PCIE_MINI2#

69
71

PCIE_ICH

66

PCIE_ICH#

67
38

PCIE_LOM

63

PCIE_LOM#

64
62

PCIE_VGA

60

PCIE_VGA#

61
29
58

PCIE_EXP# CLK_PCIE_EXP#

59
57

MCH_3GPLL

55

MCH_3GPLL#

56
28
52
53
26

PCIE_SATA

50

PCIE_SATA#

51
46
47
48

0.047U_0402_16V4Z~D

C479

1

1

2

2

R267 33_0402_5%~D
R268 33_0402_5%~D

R269 33_0402_5%~D
R270 33_0402_5%~D

R272 33_0402_5%~D
R274 33_0402_5%~D

R311 33_0402_5%~D
R313 33_0402_5%~D

R306 33_0402_5%~D
R307 33_0402_5%~D

R288 33_0402_5%~D
R289 33_0402_5%~D

R302 33_0402_5%~D
R303 33_0402_5%~D

R299 33_0402_5%~D
R168 33_0402_5%~D

R1603 33_0402_5%~D
R1604 33_0402_5%~D

R293 33_0402_5%~D
R294 33_0402_5%~D
R419 475_0402_1%~D

R279 33_0402_5%~D
R281 33_0402_5%~D

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2
1 2

1 2
1 2

H_STP_PCI# <22>

H_STP_CPU# <22>

CLK_MCH_BCLK
CLK_MCH_BCLK#

CLK_CPU_BCLK
CLK_CPU_BCLK#

CLK_CPU_ITP
CLK_CPU_ITP#

CLK_PCIE_MINI1
CLK_PCIE_MINI1#

CLK_PCIE_MINI2
CLK_PCIE_MINI2#

CLK_PCIE_ICH
CLK_PCIE_ICH#

CLK_PCIE_LOM
CLK_PCIE_LOM#

CLK_PCIE_VGA
CLK_PCIE_VGA#

CLK_PCIE_EXPPCIE_EXP

CLK_MCH_3GPLL
CLK_MCH_3GPLL#

CLK_PCIE_SATA
CLK_PCIE_SATA#

2

FSC

CLKSEL2

CLKSEL1

0
0

*

0
1
1
1
1

CPU_BSEL

133
166

CLK_MCH_BCLK <10>
CLK_MCH_BCLK# <10>

CLK_CPU_BCLK <7>
CLK_CPU_BCLK# <7>

CLK_CPU_ITP <7>
CLK_CPU_ITP# <7>

CLK_PCIE_MINI1 <31>

CLK_PCIE_MINI1# <31>

MINI1_CLKREQ# <31>

CLK_PCIE_MINI2 <31>
CLK_PCIE_MINI2# <31>

MINI2_CLKREQ# <31>

CLK_PCIE_ICH <22>
CLK_PCIE_ICH# <22>

CLK_PCIE_LOM <28>

CLK_PCIE_LOM# <28>
LOM_CLKREQ# <28>

CLK_PCIE_VGA <18>
CLK_PCIE_VGA# <18>

CLK_PCIE_EXP <32>
CLK_PCIE_EXP# <32>

EXP_CLKREQ# <32>
CLK_MCH_3GPLL <10>

CLK_MCH_3GPLL# <10>

3GPLL_CLKREQ# <10>

CLK_PCIE_SATA <21>

CLK_PCIE_SATA# <21>

SATA_CLKREQ# <22>

DELL CONFIDENTIAL/PROPRIETARY

Title

Size Document Number Rev

401490

Date: Sheet

FSAFSB

CPU
MHz

CLKSEL0

266

00

133

1

0

200

0

10

1
0
1
0
1

166

333

100

400

CPU_BSEL1(FSB)

1
0
0
1
1

CPU_BSEL2(FSC)

0

MINI1_CLKREQ#

MINI2_CLKREQ#

LOM_CLKREQ#

EXP_CLKREQ#

3GPLL_CLKREQ#

SATA_CLKREQ#

1 2

R315 10K_0402_5%~D

1 2

R310 10K_0402_5%~D

1 2

R301 10K_0402_5%~D

1 2

R1602 10K_0402_5%~D

1 2

R297 10K_0402_5%~D

1 2

R283 10K_0402_5%~D

Compal Electronics, Inc.

SCHEMATIC, M/B LA-3751P

1

SRC
MHz

100

100

100

100

100

100

100

100200

PCI
MHz

33.3

33.3

33.3

33.3

33.3

33.3

33.3

33.3

0
10

+3.3V_RUN

648Wednesday, March 28, 2007

A

of

5

4

3

2

1

+1.05V_VCCP

ITP_DBRESET#
ITP_BPM#0

D D

R321

3

22.6_0402_1%~D
1 2

1 2

R1597

22.6_0402_1%~D

CLK_CPU_ITP<6>
CLK_CPU_ITP#<6>

H_A#[3..35]<10>

H_ADSTB#0<10>

H_REQ#0<10>
H_REQ#1<10>
H_REQ#2<10>
H_REQ#3<10>

C C

B B

A A

H_REQ#4<10>

H_ADSTB#1<10>

H_A20M#<21>

H_FERR#<21>

H_IGNNE#<21>
H_STPCLK#<21>

H_INTR<21>
H_NMI<21>
H_SMI#<21>

5

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_ADSTB#0

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35
H_ADSTB#1

H_A20M#
H_FERR#
H_IGNNE#

H_STPCLK#
H_INTR
H_NMI
H_SMI#

+1.05V_VCCP

JCPUA

J4

A[3]#

L5

A[4]#

L4

A[5]#

K5

A[6]#

M3

A[7]#

N2

A[8]#

J1

A[9]#

N3

A[10]#

P5

A[11]#

P2

A[12]#

L2

A[13]#

P4

A[14]#

P1

A[15]#

R1

A[16]#

M1

ADSTB[0]#

K3

REQ[0]#

H2

REQ[1]#

K2

REQ[2]#

J3

REQ[3]#

L1

REQ[4]#

Y2

A[17]#

U5

A[18]#

R3

A[19]#

W6

A[20]#

U4

A[21]#

Y5

A[22]#

U1

A[23]#

R4

A[24]#

T5

A[25]#

T3

A[26]#

W2

A[27]#

W5

A[28]#

Y4

A[29]#

U2

A[30]#

V4

A[31]#

W3

A[32]#

AA4

A[33]#

AB2

A[34]#

AA3

A[35]#

V1

ADSTB[1]#

A6

A20M#

A5

FERR#

C4

IGNNE#

D5

STPCLK#

C6

LINT0

B4

LINT1

A3

SMI#

M4

RSVD[01]

N5

RSVD[02]

T2

RSVD[03]

V3

RSVD[04]

B2

RSVD[05]

C3

RSVD[06]

D2

RSVD[07]

D22

RSVD[08]

D3

RSVD[09]

F6

RSVD[10]

TYCO_1-1674770-2_Merom~D

R327

1 2

56_0402_5%~D

ADDR GROUP 0

CONTROLXDP/ITP SIGNALS

ADDR GROUP 1

THERMAL

PROCHOT#

THERMDA
THERMDC

ICH

THERMTRIP#

H CLK

RESERVED

H_THERMTRIP#

ADS#
BNR#
BPRI#

DEFER#

DRDY#

DBSY#

BR0#
IERR#

INIT#

LOCK#

RESET#

RS[0]#
RS[1]#
RS[2]#

TRDY#

HIT#

HITM#

BPM[0]#
BPM[1]#
BPM[2]#
BPM[3]#

PRDY#
PREQ#

TCK

TDO
TMS

TRST#

DBR#

BCLK[0]
BCLK[1]

H_ADS# CLK_CPU_ITP

H1

H_BNR#

E2

H_BPRI#

G5

H_DEFER#

H5

H_DRDY#

F21

H_DBSY#

E1

H_BR0#

F1

H_IERR#

D20

H_INIT#

B3

H_LOCK#

H4

H_RESET#

C1

H_RS#0

F3

H_RS#1

F4

H_RS#2

G3

H_TRDY#

G2

H_HIT#

G6

H_HITM#

E4

ITP_BPM#0

AD4

ITP_BPM#1

AD3

ITP_BPM#2

AD1

ITP_BPM#3

AC4

ITP_BPM#4

AC2

ITP_BPM#5

AC1

ITP_TCK

AC5

ITP_TDI

AA6

TDI

AB3
AB5
AB6
C20

D21
A24
B25

C7

A22
A21

ITP_TDO
ITP_TMS
ITP_TRST#
ITP_DBRESET#

EC_CPU_PROCHOT#
H_THERMDA

H_THERMDC
H_THERMTRIP#
CLK_CPU_BCLK

CLK_CPU_BCLK#

4

H_ADS# <10>

H_BNR# <10>
H_BPRI# <10>

H_DEFER# <10>
H_DRDY# <10>

H_DBSY# <10>

H_BR0# <10>

H_INIT# <21>

H_LOCK# <10>

H_RESET# <10>
H_RS#0 <10>
H_RS#1 <10>
H_RS#2 <10>
H_TRDY# <10>

H_HIT# <10>

H_HITM# <10>

ITP_DBRESET# <22,35>

1

C417
2200P_0402_50V7K~D

2

H_THERMTRIP# <15>

CLK_CPU_BCLK <6>

CLK_CPU_BCLK# <6>

H_THERMDA, H_THERMDC routing together,
Trace width / Spacing = 10 / 10 mil

R320

56_0402_5%~D

+1.05V_VCCP

12

12

R323
56_0402_5%~D

H_THERMDA <15>

H_THERMDC <15>

H_RESET#

ITP_TDO

+1.05V_VCCP

EC_CPU_PROCHOT# <36>

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

ITP_BPM#1
ITP_BPM#2
ITP_BPM#3
ITP_BPM#4
ITP_BPM#5
ITP_TCK

CLK_CPU_ITP#

ITP_TCK
ITP_TRST#

ITP_TMS
ITP_TDI

Place close to JITP

+1.05V_VCCP

1

C485

2

Place close to JITP

+3.3V_SUS

R324

1 2

150_0402_5%~D

+1.05V_VCCP

R325

51_0402_5%~D

R326

51_0402_1%~D

R328

39_0402_1%~D

R332

27_0402_1%~D

Place close to CPU

+1.05V_VCCP

R330

150_0402_5%~D

R331

649_0402_1%~D

1 2

@

0.1U_0402_16V4Z~D
C486

JITP

28

VTT1

27

VTT0

26

VTAP

25

DBR#

24

DBA#

23

BPM0#

22

GND5

21

BPM1#

20

GND4

19

BPM2#

18

GND3

17

BPM3#

16

GND2

15

BPM4#

14

GND1

13

BPM5#

12

RESET#

11

FBO

10

GND0

9

BCLKP

8

BCLKN

7

TDO

6

NC2

5

TCK

4

NC1

3

TRST#

2

TMS

1

TDI

@

0.1U_0402_16V4Z~D

1

2

ITP_DBRESET#

ITP_TDO

H_RESET#

ITP_TMS

ITP_TCK

ITP_TDI

ITP_TRST#

29

GND6

JCPUD

30

GND7

A4

VSS[001]

A8

VSS[002]

A11

VSS[003]

A14

VSS[004]

A16

VSS[005]

A19

VSS[006]

A23

VSS[007]

AF2

VSS[008]

B6

VSS[009]

B8

VSS[010]

B11

VSS[011]

B13

VSS[012]

B16

VSS[013]

B19

VSS[014]

B21

VSS[015]

B24

VSS[016]

C5

VSS[017]

C8

VSS[018]

C11

VSS[019]

C14

VSS[020]

C16

VSS[021]

C19

VSS[022]

C2

VSS[023]

C22

VSS[024]

C25

MOLEX_52435-2891_28P~D@

VSS[025]

D1

VSS[026]

D4

VSS[027]

D8

VSS[028]

D11

VSS[029]

D13

VSS[030]

D16

VSS[031]

D19

VSS[032]

D23

VSS[033]

D26

VSS[034]

E3

VSS[035]

E6

VSS[036]

E8

VSS[037]

E11

VSS[038]

E14

VSS[039]

E16

VSS[040]

E19

VSS[041]

E21

VSS[042]

E24

VSS[043]

F5

VSS[044]

F8

VSS[045]

F11

VSS[046]

F13

VSS[047]

F16

VSS[048]

F19

VSS[049]

F2

VSS[050]

F22

VSS[051]

F25

VSS[052]

G4

VSS[053]

G1

VSS[054]

G23

VSS[055]

G26

VSS[056]

H3

VSS[057]

H6

VSS[058]

H21

VSS[059]

H24

VSS[060]

J2

VSS[061]

J5

VSS[062]

J22

VSS[063]

J25

VSS[064]

K1

VSS[065]

K4

VSS[066]

K23

VSS[067]

K26

VSS[068]

L3

VSS[069]

L6

VSS[070]

L21

VSS[071]

L24

VSS[072]

M2

VSS[073]

M5

VSS[074]

M22

VSS[075]

M25

VSS[076]

N1

VSS[077]

N4

VSS[078]

N23

VSS[079]

N26

VSS[080]

P3

VSS[081]

TYCO_1-1674770-2_Merom~D

VSS[082]
VSS[083]
VSS[084]
VSS[085]
VSS[086]
VSS[087]
VSS[088]
VSS[089]
VSS[090]
VSS[091]
VSS[092]
VSS[093]
VSS[094]
VSS[095]
VSS[096]
VSS[097]
VSS[098]
VSS[099]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
VSS[159]
VSS[160]
VSS[161]
VSS[162]
VSS[163]

P6
P21
P24
R2
R5
R22
R25
T1
T4
T23
T26
U3
U6
U21
U24
V2
V5
V22
V25
W1
W4
W23
W26
Y3
Y6
Y21
Y24
AA2
AA5
AA8
AA11
AA14
AA16
AA19
AA22
AA25
AB1
AB4
AB8
AB11
AB13
AB16
AB19
AB23
AB26
AC3
AC6
AC8
AC11
AC14
AC16
AC19
AC21
AC24
AD2
AD5
AD8
AD11
AD13
AD16
AD19
AD22
AD25
AE1
AE4
AE8
AE11
AE14
AE16
AE19
AE23
AE26
A2
AF6
AF8
AF11
AF13
AF16
AF19
AF21
A25
AF25

DELL CONFIDENTIAL/PROPRIETARY

Title

Size Document Number Rev

2

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, M /B LA-3751P

401490

748Wednesday, March 28, 2007

1

A

of

5

4

3

2

1

H_D#[0..63]<10>

H_D#0

D D

H_DSTBN#0<10>
H_DSTBP#0<10>

H_DINV#0<10>

C C

H_DSTBN#1<10>
H_DSTBP#1<10>

H_DINV#1<10>

+V_CPU_GTLREF

CPU_MCH_BSEL0<6,10>
CPU_MCH_BSEL1<6,10>
CPU_MCH_BSEL2<6,10>

FSB BSEL2 BSEL0

BCLK BSEL1

133

B B

A A

533
667

166 1

800

200

1K_0402_5%~D@

R335

1K_0402_5%~D@

R336

1 2

1 2

Place C490 close to the
CPU_TEST4 pin. Make sure
CPU_TEST4 routing is
reference to GND and away
from other noisy signal.

C490

H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_DSTBN#0
H_DSTBP#0
H_DINV#0

H_D#16
H_D#17
H_D#18

H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_DSTBN#1
H_DSTBP#1
H_DINV#1

TEST1
TEST2
TEST3
TEST4
TEST5
TEST6

CPU_MCH_BSEL0
CPU_MCH_BSEL1
CPU_MCH_BSEL2

00
0

1

0

TEST1
TEST2
TEST4
TEST6

0.1U_0402_16V4Z~D@
0_0402_5%~D@

R394

2

1

1 2

JCPUB

E22

D[0]#

F24

D[1]#

E26

D[2]#

G22

D[3]#

F23

D[4]#

G25

D[5]#

E25

D[6]#

E23

D[7]#

K24

D[8]#

G24

D[9]#

J24

D[10]#

J23

D[11]#

H22

D[12]#

F26

D[13]#

K22

D[14]#

H23

D[15]#

J26

DSTBN[0]#

H26

DSTBP[0]#

H25

DINV[0]#

N22

D[16]#

K25

D[17]#

P26

D[18]#

R23

D[19]#

L23

D[20]#

M24

D[21]#

L22

D[22]#

M23

D[23]#

P25

D[24]#

P23

D[25]#

P22

D[26]#

T24

D[27]#

R24

D[28]#

L25

D[29]#

T25

D[30]#

N25

D[31]#

L26

DSTBN[1]#

M26

DSTBP[1]#

N24

DINV[1]#

AD26

GTLREF

C23

TSET1

D25

TEST2

C24

TEST3

AF26

TEST4

AF1

TEST5

A26

TEST6

B22

BSEL[0]

B23

BSEL[1]

C21

BSEL[2]

TYCO_1-1674770-2_Merom~D

1
1
0

D[32]#
D[33]#
D[34]#
D[35]#

T30
T31

D[36]#
D[37]#
D[38]#
D[39]#
D[40]#
D[41]#
D[42]#
D[43]#
D[44]#

DATA GRP 2DATA GRP 3

D[45]#
D[46]#

D[47]#
DSTBN[2]#
DSTBP[2]#

DINV[2]#

D[48]#

D[49]#

D[50]#

D[51]#

D[52]#

D[53]#

D[54]#

D[55]#

D[56]#

D[57]#

D[58]#

D[59]#

D[60]#

D[61]#

D[62]#

D[63]#
DSTBN[3]#
DSTBP[3]#

DINV[3]#

COMP[0]
COMP[1]
COMP[2]
COMP[3]

DPRSTP#

DPSLP#

DPWR#

PWRGOOD

SLP#

PSI#

TEST3
TEST5

+V_CPU_GTLREF

DATA GRP 0 DATA GRP 1

MISC

For the purpose of testability, route these signals
through a ground referenced Z0 = 55ohm trace that
ends in a via that is near a GND via and is
accessible through an oscilloscope connection.

AB24
V24
V26
V23
T22
U25
U23
Y25
W22
Y23
W24
W25
AA23
AA24
AB25
Y26
AA26
U22

AE24
AD24
AA21
AB22
AB21
AC26
AD20
AE22
AF23
AC25
AE21
AD21
AC22
AD23
AF22
AC23
AE25
AF24
AC20

R26
U26
AA1
Y1

E5
B5
D24
D6
D7
AE6

+1.05V_VCCP

12

12

H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_DSTBN#2
H_DSTBP#2
H_DINV#2

H_D#48
H_D#49
H_D#50
H_D#51H_D#19
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
H_DSTBN#3
H_DSTBP#3
H_DINV#3

COMP0
COMP1
COMP2
COMP3

H_DPRSTP#
H_DPSLP#
H_DPWR#
H_PWRGOOD
H_CPUSLP#
H_PSI#

R341
1K_0402_1%~D

R344
2K_0402_1%~D

H_DSTBN#2 <10>
H_DSTBP#2 <10>

H_DINV#2 <10>

H_DSTBN#3 <10>
H_DSTBP#3 <10>

H_DINV#3 <10>

H_DPRSTP# <10,21,45>

H_DPSLP# <21>

H_DPWR# <10>

H_PWRGOOD <21>

H_CPUSLP# <10>

H_PSI# <45>

H_D#32

Y22

Layout close CPU PIN AD26
55 ohm, 0.5 inch (max)

54.9_0402_1%~D

12

R337

R338

Resistor placed within 0.5" of
CPU pin.Trace should be at least
25 mils away from any other
toggling signal. COMP0, COMP2
trace should be 27.4 ohm.
COMP1, COMP3 should be 55
ohm.

54.9_0402_1%~D

27.4_0402_1%~D

12

R339

12

12

R340

27.4_0402_1%~D

+VCC_CORE +VCC_CORE

JCPUC

A7

VCC[001]

A9

VCC[002]

A10

VCC[003]

A12

VCC[004]

A13

VCC[005]

A15

VCC[006]

A17

VCC[007]

A18

VCC[008]

A20

VCC[009]

B7

VCC[010]

B9

VCC[011]

B10

VCC[012]

B12

VCC[013]

B14

VCC[014]

B15

VCC[015]

B17

VCC[016]

B18

VCC[017]

B20

VCC[018]

C9

VCC[019]

C10

VCC[020]

C12

VCC[021]

C13

VCC[022]

C15

VCC[023]

C17

VCC[024]

C18

VCC[025]

D9

VCC[026]

D10

VCC[027]

D12

VCC[028]

D14

VCC[029]

D15

VCC[030]

D17

VCC[031]

D18

VCC[032]

E7

VCC[033]

E9

VCC[034]

E10

VCC[035]

E12

VCC[036]

E13

VCC[037]

E15

VCC[038]

E17

VCC[039]

E18

VCC[040]

E20

VCC[041]

F7

VCC[042]

F9

VCC[043]

F10

VCC[044]

F12

VCC[045]

F14

VCC[046]

F15

VCC[047]

F17

VCC[048]

F18

VCC[049]

F20

VCC[050]

AA7

VCC[051]

AA9

VCC[052]

AA10

VCC[053]

AA12

VCC[054]

AA13

VCC[055]

AA15

VCC[056]

AA17

VCC[057]

AA18

VCC[058]

AA20

VCC[059]

AB9

VCC[060]

AC10

VCC[061]

AB10

VCC[062]

AB12

VCC[063]

AB14

VCC[064]

AB15

VCC[065]

AB17

VCC[066]

AB18

VCC[067]

TYCO_1-1674770-2_Merom~D

AB20

VCC[068]

AB7

VCC[069]

AC7

VCC[070]

AC9

VCC[071]

AC12

VCC[072]

AC13

VCC[073]

AC15

VCC[074]

AC17

VCC[075]

AC18

VCC[076]

AD7

VCC[077]

AD9

VCC[078]

AD10

VCC[079]

AD12

VCC[080]

AD14

VCC[081]

AD15

VCC[082]

AD17

VCC[083]

AD18

VCC[084]

AE9

VCC[085]

AE10

VCC[086]

AE12

VCC[087]

AE13

VCC[088]

AE15

VCC[089]

AE17

VCC[090]

AE18

VCC[091]

AE20

VCC[092]

AF9

VCC[093]

AF10

VCC[094]

AF12

VCC[095]

AF14

VCC[096]

AF15

VCC[097]

AF17

VCC[098]

AF18

VCC[099]

AF20

VCC[100]

G21

VCCP[01]

V6

VCCP[02]

J6

VCCP[03]

K6

VCCP[04]

M6

VCCP[05]

J21

VCCP[06]

K21

VCCP[07]

M21

VCCP[08]

N21

VCCP[09]

N6

VCCP[10]

R21

VCCP[11]

R6

VCCP[12]

T21

VCCP[13]

T6

VCCP[14]

V21

VCCP[15]

W21

VCCP[16]

B26

VCCA[1]

C26

VCCA[2]

AD6

VID[0]

AF5

VID[1]

AE5

VID[2]

AF4

VID[3]

AE3

VID[4]

AF3

VID[5]

AE2

VID[6]

AF7

VCCSENSE

AE7

VSSSENSE

VCCSENSE/VSSSENSE trace length
match wit h i n 25 mils, Z0=27.4 ohm

VID0
VID1
VID2
VID3
VID4
VID5
VID6

VCCSENSE

VSSSENSE

Place R342 and R343 near CPU

+VCC_CORE

R342

R343

VCCSENSE

VSSSENSE

1 2

100_0402_1%~D

1 2

100_0402_1%~D

Route VCCSENSE and VSSSENSE trace Zo

27.4 ohms, 7 mils spaci n g and 1 inch (max)

C487

220U_D2_4VY_R15M~D

1

+

2

VID0 <45>
VID1 <45>
VID2 <45>
VID3 <45>
VID4 <45>
VID5 <45>
VID6 <45>

VCCSENSE <45>

VSSSENSE <45>

+1.05V_VCCP

C488

+1.5V_RUN

10U_0805_10V4Z~D

0.01U_0402_16V7K~D

C489

1

1

2

2

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, M /B LA-3751P

401490

848Thursday, March 29, 2007

1

A

of

5

High Frequence Decoupling

+VCC_CORE

4

3

2

1

Place these inside
socket cavity on

D D

C C

North side
Secondary

Place these inside
socket cavity on
Sourth side
Secondary

Place these inside
socket cavity on
North side
Primary

Place these inside
socket cavity on
Sourth side
Primary

1

2

+VCC_CORE

1

2

+VCC_CORE

1

2

+VCC_CORE

1

2

C226
10U_0805_4VAM~D

C54
10U_0805_4VAM~D

C329
10U_0805_4VAM~D

C335
10U_0805_4VAM~D

1

C227
10U_0805_4VAM~D

2

1

C53
10U_0805_4VAM~D

2

1

C330
10U_0805_4VAM~D

2

1

C336
10U_0805_4VAM~D

2

1

C228
10U_0805_4VAM~D

2

1

C52
10U_0805_4VAM~D

2

1

C331
10U_0805_4VAM~D

2

1

C222
10U_0805_4VAM~D

2

1

C229
10U_0805_4VAM~D

2

1

C51
10U_0805_4VAM~D

2

1

C332
10U_0805_4VAM~D

2

1

C223
10U_0805_4VAM~D

2

1

C363
10U_0805_4VAM~D

2

1

C50
10U_0805_4VAM~D

2

1

C333
10U_0805_4VAM~D

2

1

C224
10U_0805_4VAM~D

2

1

C64
10U_0805_4VAM~D

2

1

C364
10U_0805_4VAM~D

2

1

C334
10U_0805_4VAM~D

2

1

C225
10U_0805_4VAM~D

2

1

C65
10U_0805_4VAM~D

2

1

C68
10U_0805_4VAM~D

2

1

C66
10U_0805_4VAM~D

2

1

C67
10U_0805_4VAM~D

2

1

C55
10U_0805_4VAM~D

2

1

C69
10U_0805_4VAM~D

2

1

C190
10U_0805_4VAM~D

2

1

C185
10U_0805_4VAM~D

2

10uF 0805 X6S

Near VCORE regulator.

+VCC_CORE

220U_X_2VM_R7M~D

South Side Secondary

B B

1

C338

C366

+

2

220U_X_2VM_R7M~D

220U_X_2VM_R7M~D

1

1

C365

+

+

2

2

220U_X_2VM_R7M~D

220U_X_2VM_R7M~D

1

C177

C179

+

2

220U_X_2VM_R7M~D

1

C178

+

2

North Side Secondary

1

+

2

ESR <= 1.5m ohm

+1.05V_VCCP

1

C312

0.1U_0402_10V7K~D

2

A A

1

C256

0.1U_0402_10V7K~D

2

1

C293

0.1U_0402_10V7K~D

2

1

C250

0.1U_0402_10V7K~D

2

1

C310

0.1U_0402_10V7K~D

2

1

C264

0.1U_0402_10V7K~D

2

Place these inside
socket cavity on
Secondary side

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, M /B LA-3751P

401490

948Wednesday, March 28, 2007

1

A

of

5

H_D#[0..63]<8>

D D

C C

+1.05V_VCCP

54.9_0402_1%~D

54.9_0402_1%~D
12

12

R348

R347

B B

H_RESET#<7>

12

H_CPUSLP#<8>

R350

24.9_0402_1%~D

Layout Note:
H_RCOMP trace width
and spacing is 10/20

A A

H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63

H_SWNG
H_RCOMP

H_SCOMP
H_SCOMP#

H_RESET#

H_CPUSLP#

H_VREF

C497

1

2

5

U29A

E2

H_D#_0

G2

H_D#_1

G7

H_D#_2

M6

H_D#_3

H7

H_D#_4

H3

H_D#_5

G4

H_D#_6

F3

H_D#_7

N8

H_D#_8

H2

H_D#_9

M10

H_D#_10

N12

H_D#_11

N9

H_D#_12

H5

H_D#_13

P13

H_D#_14

K9

H_D#_15

M2

H_D#_16

W10

H_D#_17

Y8

H_D#_18

V4

H_D#_19

M3

H_D#_20

J1

H_D#_21

N5

H_D#_22

N3

H_D#_23

W6

H_D#_24

W9

H_D#_25

N2

H_D#_26

Y7

H_D#_27

Y9

H_D#_28

P4

H_D#_29

W3

H_D#_30

N1

H_D#_31

AD12

H_D#_32

AE3

H_D#_33

AD9

H_D#_34

AC9

H_D#_35

AC7

H_D#_36

AC14

H_D#_37

AD11

H_D#_38

AC11

H_D#_39

AB2

H_D#_40

AD7

H_D#_41

AB1

H_D#_42

Y3

H_D#_43

AC6

H_D#_44

AE2

H_D#_45

AC5

H_D#_46

AG3

H_D#_47

AJ9

H_D#_48

AH8

H_D#_49

AJ14

H_D#_50

AE9

H_D#_51

AE11

H_D#_52

AH12

H_D#_53

AJ5

H_D#_54

AH5

H_D#_55

AJ6

H_D#_56

AE7

H_D#_57

AJ7

H_D#_58

AJ2

H_D#_59

AE5

H_D#_60

AJ3

H_D#_61

AH2

H_D#_62

AH13

H_D#_63

B3

H_SWING

C2

H_RCOMP

W1

H_SCOMP

W2

H_SCOMP#

B6

H_CPURST#

E5

H_CPUSLP#

B9

H_AVREF

A9

H_DVREF

LE88CLPM C0 QP21_FCBGA1299~D

+1.05V_VCCP

12

R356
221_0402_1%~D

H_SWNG

0.1U_0402_16V4Z~D

100_0402_1%~D

12

R362

C496

HOST

+1.05V_VCCP

0.1U_0402_16V4Z~D
R361

1

2

H_A#_3
H_A#_4
H_A#_5
H_A#_6
H_A#_7
H_A#_8

H_A#_9
H_A#_10
H_A#_11
H_A#_12
H_A#_13
H_A#_14
H_A#_15
H_A#_16
H_A#_17
H_A#_18
H_A#_19
H_A#_20
H_A#_21
H_A#_22
H_A#_23
H_A#_24
H_A#_25
H_A#_26
H_A#_27
H_A#_28
H_A#_29
H_A#_30
H_A#_31
H_A#_32
H_A#_33
H_A#_34
H_A#_35

H_ADS#
H_ADSTB#_0
H_ADSTB#_1

H_BNR#

H_BPRI#

H_BREQ#

H_DEFER#

H_DBSY#

HPLL_CLK

HPLL_CLK#

H_DPWR#

H_DRDY#

H_HIT#

H_HITM#
H_LOCK#
H_TRDY#

H_DINV#_0
H_DINV#_1
H_DINV#_2
H_DINV#_3

H_DSTBN#_0
H_DSTBN#_1
H_DSTBN#_2
H_DSTBN#_3

H_DSTBP#_0
H_DSTBP#_1
H_DSTBP#_2
H_DSTBP#_3

H_REQ#_0
H_REQ#_1
H_REQ#_2
H_REQ#_3
H_REQ#_4

H_RS#_0

H_RS#_1

H_RS#_2

12

R355
1K_0402_1%~D
H_VREF

2K_0402_1%~D

12

J13
B11
C11
M11
C15
F16
L13
G17
C14
K16
B13
L16
J17
B14
K19
P15
R17
B16
H20
L19
D17
M17
N16
J19
B18
E19
B17
B15
E17
C18
A19
B19
N19

G12
H17
G20
C8
E8
F12
D6
C10
AM5
AM7
H8
K7
E4
C6
G10
B7

K5
L2
AD13
AE13

M7
K3
AD2
AH11

L7
K2
AC2
AJ10

M14
E13
A11
H13
B12

E12
D7
D8

+1.8V_SUS

R359

R363

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35

H_ADS#
H_ADSTB#0
H_ADSTB#1
H_BNR#
H_BPRI#
H_BR0#
H_DEFER#
H_DBSY#
CLK_MCH_BCLK
CLK_MCH_BCLK#
H_DPWR#
H_DRDY#
H_HIT#
H_HITM#
H_LOCK#
H_TRDY#

H_DINV#0
H_DINV#1
H_DINV#2
H_DINV#3

H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3

H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

H_RS#0
H_RS#1
H_RS#2

12

R353
1K_0402_1%~D

3.01K_0402_1%~D
C494

1

12

2

1K_0402_1%~D

12

C498

1

2

4

0.01U_0402_16V7K~D
C495

0.01U_0402_16V7K~D
C499

4

SMRCOMP_VOH

1

2

SMRCOMP_VOL

1

2

H_A#[3..35] <7>

V_DDR_MCH_REF

H_ADS# <7>

H_ADSTB#0 <7>

H_ADSTB#1 <7>
H_BNR# <7>
H_BPRI# <7>
H_BR0# <7>
H_DEFER# <7>
H_DBSY# <7>

CLK_MCH_BCLK <6>

CLK_MCH_BCLK# <6>
H_DPWR# <8>
H_DRDY# <7>

H_HIT# <7>
H_HITM# <7>
H_LOCK# <7>

H_TRDY# <7>

H_DINV#0 <8>
H_DINV#1 <8>
H_DINV#2 <8>
H_DINV#3 <8>

H_DSTBN#0 <8>
H_DSTBN#1 <8>
H_DSTBN#2 <8>
H_DSTBN#3 <8>

H_DSTBP#0 <8>
H_DSTBP#1 <8>
H_DSTBP#2 <8>
H_DSTBP#3 <8>

H_REQ#0 <7>
H_REQ#1 <7>
H_REQ#2 <7>
H_REQ#3 <7>
H_REQ#4 <7>

H_RS#0 <7>
H_RS#1 <7>
H_RS#2 <7>

2.2U_0603_6.3V6K~D

2.2U_0603_6.3V6K~D

+1.8V_SUS

0.1U_0402_16V4Z~D

20_0402_1%~D

20_0402_1%~D

C491

+1.25V_RUN

12

R349

12

R351

R345

1 2
1 2

R346

1K_0402_1%~D

392_0402_1~D

M_CLK_DDR0<17>
M_CLK_DDR1<17>
M_CLK_DDR2<16>
M_CLK_DDR3<16>

M_CLK_DDR#0<17>
M_CLK_DDR#1<17>
M_CLK_DDR#2<16>
M_CLK_DDR#3<16>

DDR_CKE0_DIMMA<17>
DDR_CKE1_DIMMA<17>
DDR_CKE2_DIMMB<16>
DDR_CKE3_DIMMB<16>

DDR_CS0_DIMMA#<17>
DDR_CS1_DIMMA#<17>
DDR_CS2_DIMMB#<16>
DDR_CS3_DIMMB#<16>

1

1

C492

0.1U_0402_16V4Z~D

2

2

CLK_MCH_3GPLL<6>
CLK_MCH_3GPLL#<6>

DMI_MRX_ITX_N0<22>
DMI_MRX_ITX_N1<22>
DMI_MRX_ITX_N2<22>
DMI_MRX_ITX_N3<22>

DMI_MRX_ITX_P0<22>
DMI_MRX_ITX_P1<22>
DMI_MRX_ITX_P2<22>
DMI_MRX_ITX_P3<22>

DMI_MTX_IRX_N0<22>
DMI_MTX_IRX_N1<22>
DMI_MTX_IRX_N2<22>
DMI_MTX_IRX_N3<22>

DMI_MTX_IRX_P0<22>
DMI_MTX_IRX_P1<22>
DMI_MTX_IRX_P2<22>
DMI_MTX_IRX_P3<22>

CL_CLK0<22>
CL_DATA0<22>

ICH_CL_PWROK<22,36>

CL_RST0#<22>

1

C493

0.1U_0402_16V4Z~D

2

3GPLL_CLKREQ#<6>
MCH_ICH_SYNC#<22>

3

U29B

M_CLK_DDR0
M_CLK_DDR1
M_CLK_DDR2
M_CLK_DDR3

M_CLK_DDR#0
M_CLK_DDR#1
M_CLK_DDR#2
M_CLK_DDR#3

DDR_CKE0_DIMMA
DDR_CKE1_DIMMA
DDR_CKE2_DIMMB
DDR_CKE3_DIMMB

DDR_CS0_DIMMA#
DDR_CS1_DIMMA#
DDR_CS2_DIMMB#
DDR_CS3_DIMMB#

M_ODT0<17>
M_ODT1<17>
M_ODT2<16>
M_ODT3<16>

V_DDR_MCH_REF

M_ODT0
M_ODT1
M_ODT2
M_ODT3

SMRCOMP
SMRCOMP#

SMRCOMP_VOH
SMRCOMP_VOL

CLK_MCH_3GPLL
CLK_MCH_3GPLL#

DMI_MRX_ITX_N0
DMI_MRX_ITX_N1
DMI_MRX_ITX_N2
DMI_MRX_ITX_N3

DMI_MRX_ITX_P0
DMI_MRX_ITX_P1
DMI_MRX_ITX_P2
DMI_MRX_ITX_P3

DMI_MTX_IRX_N0
DMI_MTX_IRX_N1
DMI_MTX_IRX_N2
DMI_MTX_IRX_N3

DMI_MTX_IRX_P0
DMI_MTX_IRX_P1
DMI_MTX_IRX_P2
DMI_MTX_IRX_P3

T42
T43
T44
T45

T46

CL_CLK0
CL_DATA0
ICH_CL_PWROK
CL_RST0#
CL_VREF

3GPLL_CLKREQ#
MCH_ICH_SYNC#

R774 0_0402_5%~D

R357 20K_0402_5%~D

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

AV29

SM_CK_0

BB23

SM_CK_1

BA25

SM_CK_3

AV23

SM_CK_4

AW30

SM_CK#_0

BA23

SM_CK#_1

AW25

SM_CK#_3

AW23

SM_CK#_4

BE29

SM_CKE_0

AY32

SM_CKE_1

BD39

SM_CKE_3

BG37

SM_CKE_4

BG20

SM_CS#_0

BK16

SM_CS#_1

BG16

SM_CS#_2

BE13

SM_CS#_3

BH18

SM_ODT_0

BJ15

SM_ODT_1

BJ14

SM_ODT_2

BE16

SM_ODT_3

BL15

SM_RCOMP

BK14

SM_RCOMP#

BK31

SM_RCOMP_VOH

BL31

SM_RCOMP_VOL

AR49

SM_VREF_0

AW4

SM_VREF_1

B42

DPLL_REF_CLK

C42

DPLL_REF_CLK#

H48

DPLL_REF_SSCLK

H47

DPLL_REF_SSCLK#

K44

PEG_CLK

K45

PEG_CLK#

AN47

DMI_RXN_0

AJ38

DMI_RXN_1

AN42

DMI_RXN_2

AN46

DMI_RXN_3

AM47

DMI_RXP_0

AJ39

DMI_RXP_1

AN41

DMI_RXP_2

AN45

DMI_RXP_3

AJ46

DMI_TXN_0

AJ41

DMI_TXN_1

AM40

DMI_TXN_2

AM44

DMI_TXN_3

AJ47

DMI_TXP_0

AJ42

DMI_TXP_1

AM39

DMI_TXP_2

AM43

DMI_TXP_3

E35

GFX_VID_0

A39

GFX_VID_1

C38

GFX_VID_2

B39

GFX_VID_3

E36

GFX_VR_EN

AM49

CL_CLK

AK50

CL_DATA

AT43

CL_PWROK

AN49

CL_RST#

AM50

CL_VREF

H35

SDVO_CTRL_CLK

K36

SDVO_CTRL_DATA

G39

CLK_REQ#

G40

ICH_SYNC#

A37

12
12

TEST_1

R32

TEST_2

LE88CLPM C0 QP21_FCBGA1299~D

DDR MUXINGCLKDMIGRAPHICS VIDMEMISC

RSVD CFG PM NC

2

RSVD10
RSVD11
RSVD12
RSVD13
RSVD14

RSVD20
RSVD21
RSVD22
RSVD23
RSVD24
RSVD25
RSVD26
RSVD27
RSVD28
RSVD29
RSVD30
RSVD31
RSVD32
RSVD33
RSVD34
RSVD35
RSVD36
RSVD37
RSVD38
RSVD39
RSVD40
RSVD41
RSVD42
RSVD43

CFG_10
CFG_11
CFG_12
CFG_13
CFG_14
CFG_15
CFG_16
CFG_17
CFG_18
CFG_19
CFG_20

PM_BM_BUSY#

PM_DPRSTP#
PM_EXT_TS#_0
PM_EXT_TS#_1

PWROK

THERMTRIP#

DPRSLPVR

2

RSVD1
RSVD2
RSVD3
RSVD4
RSVD5
RSVD6
RSVD7
RSVD8
RSVD9

CFG_0
CFG_1
CFG_2
CFG_3
CFG_4
CFG_5
CFG_6
CFG_7
CFG_8
CFG_9

RSTIN#

NC_1
NC_2
NC_3
NC_4
NC_5
NC_6
NC_7
NC_8

NC_9
NC_10
NC_11
NC_12
NC_13
NC_14
NC_15
NC_16

Strap Pin Table

P36
P37
R35
N35
AR12
AR13
AM12
AN13
J12
AR37
AM36
AL36
AM37
D20

H10
B51
BJ20
BK22
BF19
BH20
BK18
BJ18
BF23
BG23
BC23
BD24
BH39
AW20
BK20
C48
D47
B44
C44
A35
B37
B36
B34
C34

P27
N27
N24
C21
C23

CFG5

F23
N23
G23
J20

CFG9

C20
R24
L23
J23
E23
E20
K23

CFG16

M20
M24
L32

CFG19

N33

CFG20

L35

PM_BMBUSY#

G41

H_DPRSTP#

L39

PM_EXTTS#0

L36

PM_EXTTS#1

J36

ICH_PWRGD

AW49

PLTRST1#_R

AV20

THERMTRIP_MCH#

N20

DPRSLPVR

G36

BJ51
BK51
BK50
BL50
BL49
BL3
BL2
BK1
BJ1
E1
A5
C51
B50
A50
A49
BK2

1

DMI X2 Select

CFG5

PCI Express

CFG9

Graphic Lane

FSB Dynamic

CFG16

ODT

DMI Lane

CFG19

Reversal

SDVO/PCIE
Concurrent

CFG20

Operation

SDVO_CRTL_DATA

Low = DMI x 2
High = DMI x 4 (Default)

Low = Reverse Lane
High = Normal O p e r a t i o n ( Default)

Low=Dynamic O D T Disable
High=Dynamic ODT Enable(default)

Low=Normal (default)
High=Lane Reversed

Low=Only SDVO or PCIEx1 is
operational (defaults)

High=SDVO and P C I E x 1 a r e o p e rating
simultaneously via PEG port

Low=No SDVO Device Present
(default)

High=SDVO Dev i ce Present

CFG[3:17] have internal pullup

CFG5

1 2

R365 4.02K_0402_1%~D@

CFG9

1 2

R368 4.02K_0402_1%~D@

CFG16

1 2

R372 4.02K_0402_1%~D@

CPU_MCH_BSEL0 <6,8>
CPU_MCH_BSEL1 <6,8>

CPU_MCH_BSEL2 <6,8>
T63
T64

T65
T66
T67

T68
T69
T70
T71
T72
T73

T74
T75

CFG[18:19] have internal pulldown

CFG19

1 2

R373 4.02K_0402_1%~D@

CFG20

1 2

R374 4.02K_0402_1%~D@

PM_BMBUSY# <22>
H_DPRSTP# <8,21,45>

PM_EX TTS#0 <17>

PM_EX TTS#1 <16>

ICH_PWRGD <22,39>

THERMTRIP_MCH# <15>

DPRSLPVR <22,45>

R589

0_0402_5%~D@

R583

0_0402_5%~D

R36

100_0402_5%~D

THERMTRIP_MCH#

PM_EXTTS#0

PM_EXTTS#1

12

12

PLTRST1#_R

12

R358

1 2

56_0402_5%~D

+3.3V_RUN

R352

10K_0402_5%~D

R354

10K_0402_5%~D

SB_NB_PCIE_RST# <20>

PLTRST1# <20,32>

+1.05V_VCCP

DELL CONFIDENTIAL/PROPRIETARY

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, M/B LA-3751P

401490

10 48Wednesday, March 28, 2007

1

12

12

of

+3.3V_RUN

A

5

D D

4

3

2

1

DDR_A_BS0<17>
DDR_A_BS1<17>
DDR_A_BS2<17>

DDR_A_DM[0..7]<17>

DDR_A_DQS[0..7]<17>

C C

DDR_A_DQS#[0..7]<17>

DDR_A_MA[0..14]<17>

B B

DDR_A_CAS#<17>
DDR_A_RAS#<17>
DDR_A_WE#<17>

DDR_A_BS0
DDR_A_BS1
DDR_A_BS2

DDR_A_DM0
DDR_A_DM1
DDR_A_DM2
DDR_A_DM3
DDR_A_DM4
DDR_A_DM5
DDR_A_DM6
DDR_A_DM7

DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7

DDR_A_DQS#0
DDR_A_DQS#1
DDR_A_DQS#2
DDR_A_DQS#3

DDR_A_DQS#4

DDR_A_DQS#5
DDR_A_DQS#6

DDR_A_DQS#7

DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA14 DDR_B_MA14

DDR_A_CAS#
DDR_A_RAS#
DDR_A_WE#

SA_RCVEN#

T10

BB19
BK19
BF29

AT45
BD44

BD42
AW38
AW13

AT46

BE48

BB43

BC37

BB16

AT47

BD47

BC41

BA37

BA16

BJ19
BD20
BK27
BH28

BL24
BK28

BJ27

BJ25

BL28
BA28
BC19
BE28
BG30

BJ16

BJ29

BL17
BE18
BA19

AY20

BG8
AY5
AN6

BH6
BB2
AP3

BH7
BC1
AP2

U29D

SA_BS_0
SA_BS_1
SA_BS_2

SA_DM_0
SA_DM_1
SA_DM_2
SA_DM_3
SA_DM_4
SA_DM_5
SA_DM_6
SA_DM_7

SA_DQS_0
SA_DQS_1
SA_DQS_2
SA_DQS_3
SA_DQS_4
SA_DQS_5
SA_DQS_6
SA_DQS_7

SA_DQS#_0
SA_DQS#_1
SA_DQS#_2
SA_DQS#_3
SA_DQS#_4
SA_DQS#_5
SA_DQS#_6
SA_DQS#_7

SA_MA_0
SA_MA_1
SA_MA_2
SA_MA_3
SA_MA_4
SA_MA_5
SA_MA_6
SA_MA_7
SA_MA_8
SA_MA_9
SA_MA_10
SA_MA_11
SA_MA_12
SA_MA_13
SA_MA_14

SA_CAS#
SA_RAS#
SA_WE#

SA_RCVEN#

LE88CLPM C0 QP21_FCBGA1299~D

SA_DQ_0
SA_DQ_1
SA_DQ_2
SA_DQ_3
SA_DQ_4
SA_DQ_5
SA_DQ_6
SA_DQ_7
SA_DQ_8

SA_DQ_9
SA_DQ_10
SA_DQ_11
SA_DQ_12
SA_DQ_13
SA_DQ_14
SA_DQ_15
SA_DQ_16
SA_DQ_17
SA_DQ_18
SA_DQ_19
SA_DQ_20
SA_DQ_21
SA_DQ_22
SA_DQ_23
SA_DQ_24
SA_DQ_25
SA_DQ_26
SA_DQ_27
SA_DQ_28
SA_DQ_29
SA_DQ_30
SA_DQ_31
SA_DQ_32
SA_DQ_33
SA_DQ_34
SA_DQ_35
SA_DQ_36
SA_DQ_37
SA_DQ_38
SA_DQ_39
SA_DQ_40
SA_DQ_41
SA_DQ_42
SA_DQ_43

DDR SYSTEM MEMORY A

SA_DQ_44
SA_DQ_45
SA_DQ_46
SA_DQ_47
SA_DQ_48
SA_DQ_49
SA_DQ_50
SA_DQ_51
SA_DQ_52
SA_DQ_53
SA_DQ_54
SA_DQ_55
SA_DQ_56
SA_DQ_57
SA_DQ_58
SA_DQ_59
SA_DQ_60
SA_DQ_61
SA_DQ_62
SA_DQ_63

DDR_A_D0

AR43

DDR_A_D1 DDR_B_BS1

AW44

DDR_A_D2

BA45

DDR_A_D3

AY46

DDR_A_D4

AR41

DDR_A_D5

AR45

DDR_A_D6

AT42

DDR_A_D7

AW47

DDR_A_D8

BB45

DDR_A_D9

BF48

DDR_A_D10

BG47

DDR_A_D11

BJ45

DDR_A_D12

BB47

DDR_A_D13

BG50

DDR_A_D14

BH49

DDR_A_D15

BE45

DDR_A_D16

AW43

DDR_A_D17

BE44

DDR_A_D18

BG42

DDR_A_D19

BE40

DDR_A_D20

BF44

DDR_A_D21

BH45

DDR_A_D22

BG40

DDR_A_D23

BF40

DDR_A_D24

AR40

DDR_A_D25

AW40

DDR_A_D26

AT39

DDR_A_D27

AW36

DDR_A_D28

AW41

DDR_A_D29

AY41

DDR_A_D30

AV38

DDR_A_D31

AT38

DDR_A_D32

AV13

DDR_A_D33

AT13

DDR_A_D34

AW11

DDR_A_D35

AV11

DDR_A_D36

AU15

DDR_A_D37

AT11

DDR_A_D38

BA13

DDR_A_D39

BA11

DDR_A_D40

BE10

DDR_A_D41

BD10

DDR_A_D42

BD8

DDR_A_D43

AY9

DDR_A_D44

BG10

DDR_A_D45

AW9

DDR_A_D46

BD7

DDR_A_D47

BB9

DDR_A_D48

BB5

DDR_A_D49

AY7

DDR_A_D50

AT5

DDR_A_D51

AT7

DDR_A_D52

AY6

DDR_A_D53

BB7

DDR_A_D54

AR5

DDR_A_D55

AR8

DDR_A_D56

AR9

DDR_A_D57

AN3

DDR_A_D58

AM8

DDR_A_D59

AN10

DDR_A_D60

AT9

DDR_A_D61

AN9

DDR_A_D62

AM9

DDR_A_D63

AN11

DDR_B_BS0<16>
DDR_B_BS1<16>
DDR_B_BS2<16>

DDR_B_DM[0..7]<16>

DDR_B_DQS[0..7]<16>

DDR_B_DQS#[0..7]<16>

DDR_B_MA[0..14]<16>

DDR_B_CAS#<16>
DDR_B_RAS#<16>
DDR_B_WE#<16>

T11

DDR_B_BS0
DDR_B_BS2

DDR_B_DM0
DDR_B_DM1
DDR_B_DM2
DDR_B_DM3
DDR_B_DM4
DDR_B_DM5
DDR_B_DM6
DDR_B_DM7

DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4
DDR_B_DQS5
DDR_B_DQS6
DDR_B_DQS7

DDR_B_DQS#0
DDR_B_DQS#1
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS#4
DDR_B_DQS#5
DDR_B_DQS#6
DDR_B_DQS#7

DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13

DDR_B_CAS#
DDR_B_RAS#
DDR_B_WE#

SB_RCVEN#

AY17
BG18
BG36

AR50
BD49
BK45

BL39

BH12

AW2

AT50
BD50
BK46
BK39

BJ12

AU50
BC50

BL45
BK38
BK12

BC18
BG28
BG25

AW17

BF25
BE25
BA29
BC28
AY28
BD37
BG17
BE37
BA39
BG13
BE24

BE17
AV16
BC17

AY18

BJ7

BF3

BL7
BE2
AV2

BK7
BF2
AV3

U29E

SB_BS_0
SB_BS_1
SB_BS_2

SB_DM_0
SB_DM_1
SB_DM_2
SB_DM_3
SB_DM_4
SB_DM_5
SB_DM_6
SB_DM_7

SB_DQS_0
SB_DQS_1
SB_DQS_2
SB_DQS_3
SB_DQS_4
SB_DQS_5
SB_DQS_6
SB_DQS_7

SB_DQS#_0
SB_DQS#_1
SB_DQS#_2
SB_DQS#_3
SB_DQS#_4
SB_DQS#_5
SB_DQS#_6
SB_DQS#_7

SB_MA_0
SB_MA_1
SB_MA_2
SB_MA_3
SB_MA_4
SB_MA_5
SB_MA_6
SB_MA_7
SB_MA_8
SB_MA_9
SB_MA_10
SB_MA_11
SB_MA_12
SB_MA_13
SB_MA_14

SB_CAS#
SB_RAS#
SB_WE#

SB_RCVEN#

LE88CLPM C0 QP21_FCBGA1299~D

SB_DQ_0
SB_DQ_1
SB_DQ_2
SB_DQ_3
SB_DQ_4
SB_DQ_5
SB_DQ_6
SB_DQ_7
SB_DQ_8

SB_DQ_9
SB_DQ_10
SB_DQ_11
SB_DQ_12
SB_DQ_13
SB_DQ_14
SB_DQ_15
SB_DQ_16
SB_DQ_17
SB_DQ_18
SB_DQ_19
SB_DQ_20
SB_DQ_21
SB_DQ_22
SB_DQ_23
SB_DQ_24
SB_DQ_25
SB_DQ_26
SB_DQ_27
SB_DQ_28
SB_DQ_29
SB_DQ_30
SB_DQ_31
SB_DQ_32
SB_DQ_33
SB_DQ_34
SB_DQ_35
SB_DQ_36
SB_DQ_37
SB_DQ_38
SB_DQ_39
SB_DQ_40
SB_DQ_41
SB_DQ_42
SB_DQ_43

DDR SYSTEM MEMORY B

SB_DQ_44
SB_DQ_45
SB_DQ_46
SB_DQ_47
SB_DQ_48
SB_DQ_49
SB_DQ_50
SB_DQ_51
SB_DQ_52
SB_DQ_53
SB_DQ_54
SB_DQ_55
SB_DQ_56
SB_DQ_57
SB_DQ_58
SB_DQ_59
SB_DQ_60
SB_DQ_61
SB_DQ_62
SB_DQ_63

AP49
AR51
AW50
AW51
AN51
AN50
AV50
AV49
BA50
BB50
BA49
BE50
BA51
AY49
BF50
BF49
BJ50
BJ44
BJ43
BL43
BK47
BK49
BK43
BK42
BJ41
BL41
BJ37
BJ36
BK41
BJ40
BL35
BK37
BK13
BE11
BK11
BC11
BC13
BE12
BC12
BG12
BJ10
BL9
BK5
BL5
BK9
BK10
BJ8
BJ6
BF4
BH5
BG1
BC2
BK3
BE4
BD3
BJ2
BA3
BB3
AR1
AT3
AY2
AY3
AU2
AT2

DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63

DDR_B_D[0..63] <16>DDR_A_D[0..63] <17>

A A

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, M/B LA-3751P

401490

11 48Wednesday, March 28, 2007

1

A

of

5

D D

U29C

J40

L_BKLT_CTRL

H39

L_BKLT_EN

E39

L_CTRL_CLK

E40

L_CTRL_DATA

C37

L_DDC_CLK

D35

L_DDC_DATA

K40

L_VDD_EN

L41

LVDS_IBG

L43

LVDS_VBG

N41

LVDS_VREFH

N40

LVDS_VREFL

D46

LVDSA_CLK#

C45

LVDSA_CLK

D44

LVDSB_CLK#

E42

LVDSB_CLK

G51

LVDSA_DATA#_0

E51

LVDSA_DATA#_1

F49

C C

B B

A A

LVDSA_DATA#_2

G50

LVDSA_DATA_0

E50

LVDSA_DATA_1

F48

LVDSA_DATA_2

G44

LVDSB_DATA#_0

B47

LVDSB_DATA#_1

B45

LVDSB_DATA#_2

E44

LVDSB_DATA_0

A47

LVDSB_DATA_1

A45

LVDSB_DATA_2

E27

TVA_DAC

G27

TVB_DAC

K27

TVC_DAC

F27

TVA_RTN

J27

TVB_RTN

L27

TVC_RTN

M35

TV_DCONSEL_0

P33

TV_DCONSEL_1

H32

CRT_BLUE

G32

CRT_BLUE#

K29

CRT_GREEN

J29

CRT_GREEN#

F29

CRT_RED

E29

CRT_RED#

K33

CRT_DDC_CLK

G35

CRT_DDC_DATA

F33

CRT_HSYNC

E33

CRT_VSYNC

C32

CRT_TVO_IREF

LE88CLPM C0 QP21_FCBGA1299~D

LVDS TV VGA

PEG_COMPI

PEG_COMPO

PEG_RX#_0
PEG_RX#_1
PEG_RX#_2
PEG_RX#_3
PEG_RX#_4
PEG_RX#_5
PEG_RX#_6
PEG_RX#_7
PEG_RX#_8

PEG_RX#_9
PEG_RX#_10
PEG_RX#_11
PEG_RX#_12
PEG_RX#_13
PEG_RX#_14
PEG_RX#_15

PEG_RX_0
PEG_RX_1
PEG_RX_2
PEG_RX_3
PEG_RX_4
PEG_RX_5
PEG_RX_6
PEG_RX_7
PEG_RX_8

PEG_RX_9
PEG_RX_10
PEG_RX_11
PEG_RX_12
PEG_RX_13
PEG_RX_14
PEG_RX_15

PEG_TX#_0
PEG_TX#_1
PEG_TX#_2
PEG_TX#_3
PEG_TX#_4
PEG_TX#_5
PEG_TX#_6
PEG_TX#_7

PCI-EXPRESS GRAPHICS

PEG_TX#_8
PEG_TX#_9

PEG_TX#_10
PEG_TX#_11
PEG_TX#_12
PEG_TX#_13
PEG_TX#_14
PEG_TX#_15

PEG_TX_0

PEG_TX_1

PEG_TX_2

PEG_TX_3

PEG_TX_4

PEG_TX_5

PEG_TX_6

PEG_TX_7

PEG_TX_8

PEG_TX_9
PEG_TX_10
PEG_TX_11
PEG_TX_12
PEG_TX_13
PEG_TX_14
PEG_TX_15

PEGCOMP

N43
M43

PEG_MRX_GTX_N0

J51

PEG_MRX_GTX_N1

L51

PEG_MRX_GTX_N2

N47

PEG_MRX_GTX_N3

T45

PEG_MRX_GTX_N4

T50

PEG_MRX_GTX_N5

U40

PEG_MRX_GTX_N6

Y44

PEG_MRX_GTX_N7

Y40

PEG_MRX_GTX_N8

AB51

PEG_MRX_GTX_N9

W49

PEG_MRX_GTX_N10

AD44

PEG_MRX_GTX_N11

AD40

PEG_MRX_GTX_N12

AG46

PEG_MRX_GTX_N13

AH49

PEG_MRX_GTX_N14

AG45

PEG_MRX_GTX_N15

AG41

PEG_MRX_GTX_P0

J50

PEG_MRX_GTX_P1

L50

PEG_MRX_GTX_P2

M47

PEG_MRX_GTX_P3

U44

PEG_MRX_GTX_P4

T49

PEG_MRX_GTX_P5

T41

PEG_MRX_GTX_P6

W45

PEG_MRX_GTX_P7

W41

PEG_MRX_GTX_P8

AB50

PEG_MRX_GTX_P9

Y48

PEG_MRX_GTX_P10

AC45

PEG_MRX_GTX_P11

AC41

PEG_MRX_GTX_P12

AH47

PEG_MRX_GTX_P13

AG49

PEG_MRX_GTX_P14

AH45

PEG_MRX_GTX_P15

AG42

PEG_MTX_GRX_C_N0

N45

PEG_MTX_GRX_C_N1

U39

PEG_MTX_GRX_C_N2

U47

PEG_MTX_GRX_C_N3

N51

PEG_MTX_GRX_C_N4

R50

PEG_MTX_GRX_C_N5

T42

PEG_MTX_GRX_C_N6

Y43

PEG_MTX_GRX_C_N7

W46

PEG_MTX_GRX_C_N8

W38

PEG_MTX_GRX_C_N9

AD39

PEG_MTX_GRX_C_N10

AC46

PEG_MTX_GRX_C_N11

AC49

PEG_MTX_GRX_C_N12

AC42

PEG_MTX_GRX_C_N13

AH39

PEG_MTX_GRX_C_N14

AE49

PEG_MTX_GRX_C_N15

AH44

PEG_MTX_GRX_C_P0

M45

PEG_MTX_GRX_C_P1

T38

PEG_MTX_GRX_C_P2

T46

PEG_MTX_GRX_C_P3

N50

PEG_MTX_GRX_C_P4

R51

PEG_MTX_GRX_C_P5

U43

PEG_MTX_GRX_C_P6

W42

PEG_MTX_GRX_C_P7

Y47

PEG_MTX_GRX_C_P8

Y39

PEG_MTX_GRX_C_P9

AC38

PEG_MTX_GRX_C_P10

AD47

PEG_MTX_GRX_C_P11

AC50

PEG_MTX_GRX_C_P12

AD43

PEG_MTX_GRX_C_P13

AG39

PEG_MTX_GRX_C_P14

AE50

PEG_MTX_GRX_C_P15

AH43

4

+VCC_PEG

1 2

R366

24.9_0402_1%~D

PEG_MRX_GTX_N[0..15] <18>

PEG_MRX_GTX_P[0..15] <18>

PEG_MTX_GRX_C_N[0..15] <18>

PEG_MTX_GRX_C_P[0..15] <18>

Place R366 within 500 mil
of the GMCHand avoid routing
next to clock pins

3

U29I

A13

VSS_1

A15

VSS_2

A17

VSS_3

A24

VSS_4

AA21

VSS_5

AA24

VSS_6

AA29

VSS_7

AB20

VSS_8

AB23

VSS_9

AB26

VSS_10

AB28

VSS_11

AB31

VSS_12

AC10

VSS_13

AC13

VSS_14

AC3

VSS_15

AC39

VSS_16

AC43

VSS_17

AC47

VSS_18

AD1

VSS_19

AD21

VSS_20

AD26

VSS_21

AD29

VSS_22

AD3

VSS_23

AD41

VSS_24

AD45

VSS_25

AD49

VSS_26

AD5

VSS_27

AD50

VSS_28

AD8

VSS_29

AE10

VSS_30

AE14

VSS_31

AE6

VSS_32

AF20

VSS_33

AF23

VSS_34

AF24

VSS_35

AF31

VSS_36

AG2

VSS_37

AG38

VSS_38

AG43

VSS_39

AG47

VSS_40

AG50

VSS_41

AH3

VSS_42

AH40

VSS_43

AH41

VSS_44

AH7

VSS_45

AH9

VSS_46

AJ11

VSS_47

AJ13

VSS_48

AJ21

VSS_49

AJ24

VSS_50

AJ29

VSS_51

AJ32

VSS_52

AJ43

VSS_53

AJ45

VSS_54

AJ49

VSS_55

AK20

VSS_56

AK21

VSS_57

AK26

VSS_58

AK28

VSS_59

AK31

VSS_60

AK51

VSS_61

AL1

VSS_62

AM11

VSS_63

AM13

VSS_64

AM3

VSS_65

AM4

VSS_66

AM41

VSS_67

AM45

VSS_68

AN1

VSS_69

AN38

VSS_70

AN39

VSS_71

AN43

VSS_72

AN5

VSS_73

AN7

VSS_74

AP4

VSS_75

AP48

VSS_76

AP50

VSS_77

AR11

VSS_78

AR2

VSS_79

AR39

VSS_80

AR44

VSS_81

AR47

VSS_82

AR7

VSS_83

AT10

VSS_84

AT14

VSS_85

AT41

VSS_86

AT49

VSS_87

AU1

VSS_88

AU23

VSS_89

AU29

VSS_90

AU3

VSS_91

AU36

VSS_92

AU49

VSS_93

AU51

VSS_94

AV39

VSS_95

AV48

VSS_96

AW1

VSS_97

AW12

VSS_98

AW16

VSS_99

LE88CLPM C0 QP21_FCBGA1299~D

VSS

VSS_100
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105
VSS_106
VSS_107
VSS_108
VSS_109
VSS_110
VSS_111
VSS_112
VSS_113
VSS_114
VSS_115
VSS_116
VSS_117
VSS_118
VSS_119
VSS_120
VSS_121
VSS_122
VSS_123
VSS_124
VSS_125
VSS_126
VSS_127
VSS_128
VSS_129
VSS_130
VSS_131
VSS_132
VSS_133
VSS_134
VSS_135
VSS_136
VSS_137
VSS_138
VSS_139
VSS_140
VSS_141
VSS_142
VSS_143
VSS_144
VSS_145
VSS_146
VSS_147
VSS_148
VSS_149
VSS_150
VSS_151
VSS_152
VSS_153
VSS_154
VSS_155
VSS_156
VSS_157
VSS_158
VSS_159
VSS_160
VSS_161
VSS_162
VSS_163
VSS_164
VSS_165
VSS_166
VSS_167
VSS_168
VSS_169
VSS_170
VSS_171
VSS_172
VSS_173
VSS_174
VSS_175
VSS_176
VSS_177
VSS_178
VSS_179
VSS_180
VSS_181
VSS_182
VSS_183
VSS_184
VSS_185
VSS_186
VSS_187
VSS_188
VSS_189
VSS_190
VSS_191
VSS_192
VSS_193
VSS_194
VSS_195
VSS_196
VSS_197
VSS_198

2

AW24
AW29
AW32
AW5
AW7
AY10
AY24
AY37
AY42
AY43
AY45
AY47
AY50
B10
B20
B24
B29
B30
B35
B38
B43
B46
B5
B8
BA1
BA17
BA18
BA2
BA24
BB12
BB25
BB40
BB44
BB49
BB8
BC16
BC24
BC25
BC36
BC40
BC51
BD13
BD2
BD28
BD45
BD48
BD5
BE1
BE19
BE23
BE30
BE42
BE51
BE8
BF12
BF16
BF36
BG19
BG2
BG24
BG29
BG39
BG48
BG5
BG51
BH17
BH30
BH44
BH46
BH8
BJ11
BJ13
BJ38
BJ4
BJ42
BJ46
BK15
BK17
BK25
BK29
BK36
BK40
BK44
BK6
BK8
BL11
BL13
BL19
BL22
BL37
BL47
C12
C16
C19
C28
C29
C33
C36
C41

U29J

C46

VSS_199

C50

VSS_200

C7

VSS_201

D13

VSS_202

D24

VSS_203

D3

VSS_204

D32

VSS_205

D39

VSS_206

D45

VSS_207

D49

VSS_208

E10

VSS_209

E16

VSS_210

E24

VSS_211

E28

VSS_212

E32

VSS_213

E47

VSS_214

F19

VSS_215

F36

VSS_216

F4

VSS_217

F40

VSS_218

F50

VSS_219

G1

VSS_220

G13

VSS_221

G16

VSS_222

G19

VSS_223

G24

VSS_224

G28

VSS_225

G29

VSS_226

G33

VSS_227

G42

VSS_228

G45

VSS_229

G48

VSS_230

G8

VSS_231

H24

VSS_232

H28

VSS_233

H4

VSS_234

H45

VSS_235

J11

VSS_236

J16

VSS_237

J2

VSS_238

J24

VSS_239

J28

VSS_240

J33

VSS_241

J35

VSS_242

J39

VSS_243

K12

VSS_245

K47

VSS_246

K8

VSS_247

L1

VSS_248

L17

VSS_249

L20

VSS_250

L24

VSS_251

L28

VSS_252

L3

VSS_253

L33

VSS_254

L49

VSS_255

M28

VSS_256

M42

VSS_257

M46

VSS_258

M49

VSS_259

M5

VSS_260

M50

VSS_261

M9

VSS_262

N11

VSS_263

N14

VSS_264

N17

VSS_265

N29

VSS_266

N32

VSS_267

N36

VSS_268

N39

VSS_269

N44

VSS_270

N49

VSS_271

N7

VSS_272

P19

VSS_273

P2

VSS_274

P23

VSS_275

P3

VSS_276

P50

VSS_277

R49

VSS_278

T39

VSS_279

T43

VSS_280

T47

VSS_281

U41

VSS_282

U45

VSS_283

U50

VSS_284

V2

VSS_285

V3

VSS_286

LE88CLPM C0 QP21_FCBGA1299~D

VSS

VSS_287
VSS_288
VSS_289
VSS_290
VSS_291
VSS_292
VSS_293
VSS_294
VSS_295
VSS_296
VSS_297
VSS_298
VSS_299
VSS_300
VSS_301
VSS_302
VSS_303
VSS_304
VSS_305

VSS_306
VSS_307
VSS_308
VSS_309
VSS_310
VSS_311
VSS_312
VSS_313

1

W11
W39
W43
W47
W5
W7
Y13
Y2
Y41
Y45
Y49
Y5
Y50
Y11
P29
T29
T31
T33
R28

AA32
AB32
AD32
AF28
AF29
AT27
AV25
H50

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, M/B LA-3751P

401490

12 48Wednesday, March 28, 2007

1

A

of

5

4

3

2

1

45mA Max.

+1.25V_RUN_HPLL +1 . 2 5V_RUN

22U_0805_6.3V6M~D

0.1U_0402_16V4Z~D
C572

C571

1

1

2

2

45mA Max.

22U_0805_6.3V6M~D

0.1U_0402_16V4Z~D
C575

C574

1

1

2

2

+1.25V_RUN

1

2

C566

0.1U_0402_16V4Z~D

1 2

22U_0805_6.3V6M~D

0_0805_5%~D

1U_0603_10V4Z~D

1

2

C582

R406

1 2

0_0603_5%~D

1

2

R408

10U_0805_4VAM~D

C583

100U_D2E_6.3VM_R18M~D

1

C558

+

2

+1.25V_RUN

+1.5V_RUN

0.022U_0402_16V7K~D
C584

1

2

0.1U_0402_16V4Z~D

1

2

4.7U_0603_6.3V4Z~D

1

2

L33

22U_0805_6.3V6M~D

C552

0.1U_0402_16V4Z~D

1

2

C597

1

2

+1.05V_VCCP

0.47U_0402_10V4Z~D

1

C537

2

2.2U_0603_6.3V6K~D

C544

1

2

+1.25V_RUN_AXD

12

1U_0603_10V4Z~D

1

+1.25V_RUN

2

+1.8V_SM_CK

0.1U_0402_16V4Z~D

1

+VCC_PEG

2

0.47U_0402_10V4Z~D
C577

1

2

0.47U_0402_10V4Z~D
C578

220U_D2_4VY_R15M~D

C542

+1.25V_RUN

BLM18AG121SN1D_0603~D

+1.25V_RUN

+3.3V_RUN

1

+

C535

2

4.7U_0603_6.3V4Z~D

C543

1

2

C551

1

2

C591

+VCC_RXR_DMI

C576

D D

+1.8V_SUS +1.8V_SM_CK

C C

B B

A A

L41

BLM18AG121SN1D_0603~D

BLM18PG181SN1_0603~D

BLM18PG181SN1_0603~D

1 2

1 2

Place CAPs close to
VCC_AXF (pin A21, B21, B23)

+1.25V_RUN

C589

12

L32

L34

1_0603_5%~D

12

R416

1

C594
10U_0805_4VAM~D

2

10U_0805_4VAM~D

1U_0603_10V4Z~D

C590

1

1

2

2

22U_0805_6.3V6M~D

0.1U_0402_16V4Z~D
C593

C592

1

1

C549

C557

2

2

+VCC_PEG+1.05V_VCCP

220U_D2_4VY_R15M~D

10U_0805_4VAM~D

1

C548

1

+

2

2

+VCC_RXR_DMI+1.05V_VCCP

220U_D2_4VY_R15M~D

10U_0805_4VAM~D

1

C556

1

+

2

2

U29H

U13

VTT_1

U12

VTT_2

U11

VTT_3

U9

VTT_4

U8

VTT_5

U7

VTT_6

U5

VTT_7

U3

VTT_8

U2

VTT_9

U1

VTT_10

T13

VTT_11

T11

VTT_12

T10

VTT_13

T9

VTT_14

T7

VTT_15

T6

VTT_16

T5

VTT_17

T3

VTT_18

T2

VTT_19

R3

VTT_20

R2

VTT_21

R1

VTT_22

AT23

VCC_AXD_1

AU28

VCC_AXD_2

AU24

VCC_AXD_3

AT29

VCC_AXD_4

AT25

VCC_AXD_5

AT30

VCC_AXD_6

AR29

VCC_AXD_NCTF

B23

VCC_AXF_1

B21

VCC_AXF_2

A21

VCC_AXF_3

AJ50

VCC_DMI

BK24

VCC_SM_CK_1

BK23

VCC_SM_CK_2

BJ24

VCC_SM_CK_3

BJ23

VCC_SM_CK_4

A43

VCC_TX_LVDS

C40

VCC_HV_1

B40

VCC_HV_2

AD51

VCC_PEG_1

W50

VCC_PEG_2

W51

VCC_PEG_3

V49

VCC_PEG_4

V50

VCC_PEG_5

AH50

VCC_RXR_DMI_1

AH51

VCC_RXR_DMI_2

A7

VTTLF1

F2

VTTLF2

AH1

VTTLF3

0.47U_0402_10V4Z~D

1

2

LE88CLPM C0 QP21_FCBGA1299~D

+1.05V_VCCP

CRT

VTT

PLL

LVDS PEG

AXD

AXF

SM

CLK

POWER

TV

PEG

DMI

VTTLF

D16

2 1

RB751V_SOD323-2~D

VCCSYNC

VCCA_CRT_DAC_1
VCCA_CRT_DAC_2

VCCA_DAC_BG
VSSA_DAC_BG

VCCA_DPLLA
VCCA_DPLLB

VCCA_HPLL

VCCA_MPLL

VCCA_LVDS
VSSA_LVDS

VCCA_PEG_BG
VSSA_PEG_BG

VCCA_PEG_PLL

VCCA_SM_1
VCCA_SM_2
VCCA_SM_3
VCCA_SM_4
VCCA_SM_5
VCCA_SM_7
VCCA_SM_8

VCCA_SM_9
VCCA_SM_10
VCCA_SM_11

VCCA_SM_NCTF_1
VCCA_SM_NCTF_2

VCCA_SM_CK_1
VCCA_SM_CK_2

VCCA_TVA_DAC_1
VCCA_TVA_DAC_2
VCCA_TVB_DAC_1
VCCA_TVB_DAC_2
VCCA_TVC_DAC_1
VCCA_TVC_DAC_2

TV/CRT

VCCD_CRT

VCCD_TVDAC

VCCD_QDAC

VCCD_HPLL

VCCD_PEG_PLL

LVDS

VCCD_LVDS_1
VCCD_LVDS_2

R417

1 2

10_0603_5%~D

J32
A33

B33

A30
B32

B49
H49
AL2
AM2

A41
B41

K50
K49

U51

AW18
AV19
AU19
AU18
AU17
AT22
AT21
AT19
AT18
AT17
AR17
AR16

BC29
BB29

C25
B25
C27
B27
B28
A28

M32
L29

N28

AN2
U48

J41
H42

+3.3V_RUN

+1.25V_RUN_HPLL
+1.25V_RUN_MPLL

+1.25V_RUN_PEGPLL

+VCCA_SM

C559

1

2

+VCCA_SM_CK

C563

+1.25V_RUN_PEGPLL

0.1U_0402_16V4Z~D

C554

1

2

1U_0603_10V4Z~D

1

2

C560

1

2

0.1U_0402_16V4Z~D

+3.3V_RUN

4.7U_0603_6.3V4Z~D

C564

1

2

C550

C561

1

2

1

2

22U_0805_6.3V6M~D

0.1U_0402_16V4Z~D

22U_0805_6.3V6M~D

C562

1U_0603_10V4Z~D

C565

1

2

+1.25V_RUN

C642

1

2

L37

12

BLM18AG121SN1D_0603~D

L38

BLM18AG121SN1D_0603~D

0.1U_0402_16V4Z~D

C573

1

2

+1.25V_RUN+1.25V_RUN_MPLL

12

+1.25V_RUN_PEGPLL +1.25V_RUN

0.1U_0402_16V4Z~D

C568

1

2

1_0402_5%~D

R409

1

C567
10U_0805_4VAM~D

2

L35

BLM21PG221SN1D_0805~D

12

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, M/B LA-3751P

401490

13 48Wednesday, March 28, 2007

1

A

of

5

4

3

2

1

+1.05V_VCCP

22U_0805_6.3V6M~D

0.22U_0402_10V4Z~D

C617

C620

C604

C614

+1.05V_VCCP

0.22U_0402_10V4Z~D

1

2

0.1U_0402_10V7K~D

1

2

0.22U_0402_10V4Z~D

1

2

0.1U_0402_10V7K~D

1

2

U29F

AB33

VCC_NCTF_1

AB36

VCC_NCTF_2

AB37

VCC_NCTF_3

AC33

VCC_NCTF_4

AC35

VCC_NCTF_5

AC36

VCC_NCTF_6

AD35

VCC_NCTF_7

AD36

VCC_NCTF_8

AF33

VCC_NCTF_9

AF36

VCC_NCTF_10

AH33

VCC_NCTF_11

AH35

VCC_NCTF_12

AH36

VCC_NCTF_13

AH37

VCC_NCTF_14

AJ33

VCC_NCTF_15

AJ35

VCC_NCTF_16

AK33

VCC_NCTF_17

AK35

VCC_NCTF_18

AK36

VCC_NCTF_19

AK37

VCC_NCTF_20

AD33

VCC_NCTF_21

AJ36

VCC_NCTF_22

AM35

VCC_NCTF_23

AL33

VCC_NCTF_24

AL35

VCC_NCTF_25

AA33

VCC_NCTF_26

AA35

VCC_NCTF_27

AA36

VCC_NCTF_28

AP35

VCC_NCTF_29

AP36

VCC_NCTF_30

AR35

VCC_NCTF_31

AR36

VCC_NCTF_32

Y32

VCC_NCTF_33

Y33

VCC_NCTF_34

Y35

VCC_NCTF_35

Y36

VCC_NCTF_36

Y37

VCC_NCTF_37

T30

VCC_NCTF_38

T34

VCC_NCTF_39

T35

VCC_NCTF_40

U29

VCC_NCTF_41

U31

VCC_NCTF_42

U32

VCC_NCTF_43

U33

VCC_NCTF_44

U35

VCC_NCTF_45

U36

VCC_NCTF_46

V32

VCC_NCTF_47

V33

VCC_NCTF_48

V36

VCC_NCTF_49

V37

VCC_NCTF_50

AL24

VCC_AXM_NCTF_1

AL26

VCC_AXM_NCTF_2

AL28

VCC_AXM_NCTF_3

AM26

VCC_AXM_NCTF_4

AM28

VCC_AXM_NCTF_5

AM29

VCC_AXM_NCTF_6

AM31

VCC_AXM_NCTF_7

AM32

VCC_AXM_NCTF_8

AM33

VCC_AXM_NCTF_9

AP29

VCC_AXM_NCTF_10

AP31

VCC_AXM_NCTF_11

AP32

VCC_AXM_NCTF_12

AP33

VCC_AXM_NCTF_13

AL29

VCC_AXM_NCTF_14

AL31

VCC_AXM_NCTF_15

AL32

VCC_AXM_NCTF_16

AR31

VCC_AXM_NCTF_17

AR32

VCC_AXM_NCTF_18

AR33

VCC_AXM_NCTF_19

LE88CLPM C0 QP21_FCBGA1299~D

POWER

VSS_NCTF_1
VSS_NCTF_2
VSS_NCTF_3
VSS_NCTF_4
VSS_NCTF_5
VSS_NCTF_6
VSS_NCTF_7
VSS_NCTF_8

VSS_NCTF_9
VSS_NCTF_10
VSS_NCTF_11
VSS_NCTF_12
VSS_NCTF_13
VSS_NCTF_14
VSS_NCTF_15
VSS_NCTF_16
VSS_NCTF_17
VSS_NCTF_18
VSS_NCTF_19
VSS_NCTF_20
VSS_NCTF_21

VSS_SCB1
VSS_SCB2
VSS_SCB3
VSS_SCB4
VSS_SCB5
VSS_SCB6

VCC_AXM_1
VCC_AXM_2
VCC_AXM_3
VCC_AXM_4
VCC_AXM_6
VCC_AXM_5
VCC_AXM_7

T27
T37
U24
U28
V31
V35
AA19
AB17
AB35
AD19
AD37
AF17
AF35
AK17
AM17
AM24
AP26
AP28
AR15
AR19
AR28

A3
B2
C1
BL1
BL51
A51

+1.05V_VCCP

AT33
AT31
AK29
AK24
AK23
AJ26
AJ23

+3.3V_RUN

R420

1 2

10_0603_5%~D@

Layout Note:
Place C901 where
LVDS and DDR2 taps

+1.8V_SUS

330U_D2_2.5VM_R15~D

0.1U_0402_10V7K~D
1

C605

C608

2

+

2

1

Layout Note:
Place on the edge

22U_0805_6.3V6M~D

22U_0805_6.3V6M~D

C606

C607

1

1

2

2

+1.05V_VCCP

2

1

D17

3

BAT54CW_SOT323~D@

D D

Layout Note:
370 mil from edge

220U_D2_4VY_R15M~D

1

C602

+

2

C C

B B

Layout Note:
Inside GMCH cavity

C603

1

2

C613

1

2

Layout Note:
Place close to GMCH edge

+1.05V_VCCP

0.22U_0402_10V4Z~D

22U_0805_6.3V6M~D

C616

C615

1

1

2

2

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

C619

C618

1

1

2

2

Layout Note: Inside GMCH cavity

A A

U29G

AT35

VCC_1

AT34

VCC_2

AH28

VCC_3

AC32

VCC_4

AC31

VCC_5

AK32

VCC_6

AJ31

VCC_7

AJ28

VCC_8

AH32

VCC_9

AH31

VCC_10

AH29

VCC_11

AF32

VCC_12

R30

VCC_13

POWER

AU32

VCC_SM_1

AU33

VCC_SM_2

AU35

VCC_SM_3

AV33

VCC_SM_4

AW33

VCC_SM_5

AW35

VCC_SM_6

AY35

VCC_SM_7

BA32

VCC_SM_8

BA33

VCC_SM_9

BA35

VCC_SM_10

BB33

VCC_SM_11

BC32

VCC_SM_12

BC33

VCC_SM_13

BC35

VCC_SM_14

BD32

VCC_SM_15

BD35

VCC_SM_16

BE32

VCC_SM_17

BE33

VCC_SM_18

BE35

VCC_SM_19

BF33

VCC_SM_20

BF34

VCC_SM_21

BG32

VCC_SM_22

BG33

VCC_SM_23

BG35

VCC_SM_24

BH32

VCC_SM_25

BH34

VCC_SM_26

BH35

VCC_SM_27

BJ32

VCC_SM_28

BJ33

VCC_SM_29

BJ34

VCC_SM_30

BK32

VCC_SM_31

BK33

VCC_SM_32

BK34

VCC_SM_33

BK35

VCC_SM_34

BL33

VCC_SM_35

AU30

VCC_SM_36

R20

VCC_AXG_1

T14

VCC_AXG_2

W13

VCC_AXG_3

W14

VCC_AXG_4

Y12

VCC_AXG_5

AA20

VCC_AXG_6

AA23

VCC_AXG_7

AA26

VCC_AXG_8

AA28

VCC_AXG_9

AB21

VCC_AXG_10

AB24

VCC_AXG_11

AB29

VCC_AXG_12

AC20

VCC_AXG_13

AC21

VCC_AXG_14

AC23

VCC_AXG_15

AC24

VCC_AXG_16

AC26

VCC_AXG_17

AC28

VCC_AXG_18

AC29

VCC_AXG_19

AD20

VCC_AXG_20

AD23

VCC_AXG_21

AD24

VCC_AXG_22

AD28

VCC_AXG_23

AF21

VCC_AXG_24

AF26

VCC_AXG_25

AA31

VCC_AXG_26

AH20

VCC_AXG_27

AH21

VCC_AXG_28

AH23

VCC_AXG_29

AH24

VCC_AXG_30

AH26

VCC_AXG_31

AD31

VCC_AXG_32

AJ20

VCC_AXG_33

AN14

VCC_AXG_34

LE88CLPM C0 QP21_FCBGA1299~D

VCC GFX

VCC CORE

VCC SM

VCC_AXG_NCTF_1
VCC_AXG_NCTF_2
VCC_AXG_NCTF_3
VCC_AXG_NCTF_4
VCC_AXG_NCTF_5
VCC_AXG_NCTF_6
VCC_AXG_NCTF_7
VCC_AXG_NCTF_8

VCC_AXG_NCTF_9
VCC_AXG_NCTF_10
VCC_AXG_NCTF_11
VCC_AXG_NCTF_12
VCC_AXG_NCTF_13
VCC_AXG_NCTF_14
VCC_AXG_NCTF_15
VCC_AXG_NCTF_16
VCC_AXG_NCTF_17
VCC_AXG_NCTF_18
VCC_AXG_NCTF_19
VCC_AXG_NCTF_20
VCC_AXG_NCTF_21
VCC_AXG_NCTF_22
VCC_AXG_NCTF_23
VCC_AXG_NCTF_24
VCC_AXG_NCTF_25
VCC_AXG_NCTF_26
VCC_AXG_NCTF_27
VCC_AXG_NCTF_28
VCC_AXG_NCTF_29
VCC_AXG_NCTF_30
VCC_AXG_NCTF_31
VCC_AXG_NCTF_32
VCC_AXG_NCTF_33
VCC_AXG_NCTF_34
VCC_AXG_NCTF_35
VCC_AXG_NCTF_36
VCC_AXG_NCTF_37
VCC_AXG_NCTF_38
VCC_AXG_NCTF_39
VCC_AXG_NCTF_40
VCC_AXG_NCTF_41
VCC_AXG_NCTF_42
VCC_AXG_NCTF_43
VCC_AXG_NCTF_44
VCC_AXG_NCTF_45
VCC_AXG_NCTF_46
VCC_AXG_NCTF_47
VCC_AXG_NCTF_48

VCC GFX NCTFVCC SM LF

VCC_AXG_NCTF_49
VCC_AXG_NCTF_50
VCC_AXG_NCTF_51
VCC_AXG_NCTF_52
VCC_AXG_NCTF_53
VCC_AXG_NCTF_54
VCC_AXG_NCTF_55
VCC_AXG_NCTF_56
VCC_AXG_NCTF_57
VCC_AXG_NCTF_58
VCC_AXG_NCTF_59
VCC_AXG_NCTF_60
VCC_AXG_NCTF_61
VCC_AXG_NCTF_62
VCC_AXG_NCTF_63
VCC_AXG_NCTF_64
VCC_AXG_NCTF_65
VCC_AXG_NCTF_66
VCC_AXG_NCTF_67
VCC_AXG_NCTF_68
VCC_AXG_NCTF_69
VCC_AXG_NCTF_70
VCC_AXG_NCTF_71
VCC_AXG_NCTF_72
VCC_AXG_NCTF_73
VCC_AXG_NCTF_74
VCC_AXG_NCTF_75
VCC_AXG_NCTF_76
VCC_AXG_NCTF_77
VCC_AXG_NCTF_78
VCC_AXG_NCTF_79
VCC_AXG_NCTF_80
VCC_AXG_NCTF_81
VCC_AXG_NCTF_82
VCC_AXG_NCTF_83

VCC_SM_LF1
VCC_SM_LF2
VCC_SM_LF3
VCC_SM_LF4
VCC_SM_LF5
VCC_SM_LF6
VCC_SM_LF7

T17
T18
T19
T21
T22
T23
T25
U15
U16
U17
U19
U20
U21
U23
U26
V16
V17
V19
V20
V21
V23
V24
Y15
Y16
Y17
Y19
Y20
Y21
Y23
Y24
Y26
Y28
Y29
AA16
AA17
AB16
AB19
AC16
AC17
AC19
AD15
AD16
AD17
AF16
AF19
AH15
AH16
AH17
AH19
AJ16
AJ17
AJ19
AK16
AK19
AL16
AL17
AL19
AL20
AL21
AL23
AM15
AM16
AM19
AM20
AM21
AM23
AP15
AP16
AP17
AP19
AP20
AP21
AP23
AP24
AR20
AR21
AR23
AR24
AR26
V26
V28
V29
Y31

VCCSM_LF1

AW45

VCCSM_LF2

BC39

VCCSM_LF3

BE39

VCCSM_LF4

BD17

VCCSM_LF5

BD4

VCCSM_LF6

AW8
AT6

VCCSM_LF7

C621

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

C622

C623

1

1

2

1

2

2

0.22U_0402_10V4Z~D

0.22U_0402_10V4Z~D

C624

C625

1

2

1U_0402_6.3V4Z~D

0.47U_0402_10V4Z~D

C626

1

2

1U_0402_6.3V4Z~D

C627

1

1

2

2

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, M/B LA-3751P

401490

14 48Wednesday, March 28, 2007

1

A

of

5

4

3

2

1

VGA fan control and Tachometer

+15V_ALW

C1441

1 2

0.1U_0603_50V4Z~D

FAN2_PWM

D D

+15V_ALW

5

IN+

6

IN-

1 2

120K_0402_5%~D

8

P

7

O

G

U73B
LM358DR2G_SOIC8~D

4

R1605

FAN2VREF

0.22U_0603_10V7K~D
FAN2_VFB

1

C1442

2

2200P_0402_50V7K~D

R1606 78.7K_0402_1%~D

120K_0402_5%~D

R1607

1 2

3
2

C1443

1 2

8

P

IN+
IN-

FAN2_ON

1

O

G

U73A
LM358DR2G_SOIC8~D

4

12

D47

2 1

+5V_RUN

6

2

1

D

Q182

G

22U_0805_6.3V6M~D

S

4 5

1000P_0402_50V7K~D@

C1445

1

2

SI3456BDV-T1-E3_TSOP6~D

FAN2_5V

MOLEX_53398-0371~D

3

RB751S40T1_SOD523-2~D@

C1439

1

2

+3.3V_RUN

12

R1270
10K_0402_5%~D

FAN2_TACH <36>

1000P_0402_50V7K~D@

C1444

1

JFAN2

1

1

2

2

3

2

3

R438

VSET = 0.865V=

x 3.3V

R436+R438

Tp-70

VSET =

=> Tp = 88.2 C

21

Place close to JDIMA

+5V_SUS

12

R771

2.21K_0603_1%~D

VCP2

1

C750
2200P_0402_50V7K~D

2

12

R772
10K_0603_1%_TSM1A103F34D3RZ~D

Q102

13

D

2N7002W-7-F_SOT323-3~D

2

G

S

+3.3V_SUS

12

R773
10K_0402_5%~D

Place Q41 close to JDIMMB
REM_DIODE3_N, REM_DIODE3_P routing together.

Trace width / Spacing = 10 / 10 mil

5V_CAL_SIO#

Main fan cont ro l a nd Tachometer

Place under CPU

RB751S40T1_SOD523-2~D@

H_THERMTRIP#<7>

C630

1

2

+1.05V_VCCP

+3.3V_RUN

22U_0805_6.3V6M~D

+1.05V_VCCP

12

R424
10K_0402_5%~D

12

FAN1_TACH <36>

R414
0_0402_5%~D

+FAN1_VOUT
FAN1_TACH_FB

MOLEX_53398-0371~D

R425

1 2

2.2K_0402_5%~D

MMST3904-7-F_SOT323-3~D

R427

1 2

2.2K_0402_5%~D@

MMST3904-7-F_SOT323-3~D@

5

1
2
3

+3.3V_SUS

2

B

Q38

+3.3V_SUS

2

B

Q39

JFAN1

1
2
3

12

R423

8.2K_0402_5%~D

C

E

3 1

12

R426

8.2K_0402_5%~D

C

E

3 1

C C

D19

2 1

B B

A A

+3.3V_SUS

THERMATRIP1#

1

C628

0.1U_0402_16V4Z~D

2

THERMATRIP2#

1

C632

0.1U_0402_16V4Z~D@

2

2

C633

1

2200P_0402_50V7K~D@

Place C636 close to Guardian pin as possible

H_THERMDA<7>

H_THERMDC<7>

R428

1 2

49.9_0603_1%~D

THERMTRIP_VGA#<18>THERMTRIP_MCH#<10>

Place C633 close to the Q40 as possible

C

Q40

2

B

E

MMST3904-7-F_SOT323-3~D

3 1

C636

470P_0402_50V7K~D

0.1U_0402_16V4Z~D

1

+RTC_CELL

C637

2

+3.3V_SUS

0.1U_0402_16V4Z~D

+3.3V_SUS

C639

1 2

10K_0402_5%~D@

1 2

10K_0402_5%~D@

4

R196

R194

332K_0402_1%~D

1

2

+3.3V_RUN

12

R186

1

2

R436

1 2

MDC_RST_DIS#

SIO_GFX_PWR

R187

8.2K_0402_5%~D

2

C634
2200P_0402_50V7K~D

1

1

2

C638

ICH_PWRGD#<39>

0.1U_0402_16V4Z~D

118K_0402_1%~D

12

R438

2.2K_0402_5%~D@

12

THERM_B3

MMST3904-7-F_SOT323-3~D@

SUSPWROK<39>

C100

Place C634 close to the
Guardian pins as possible

THRM_SMBDAT<36,46>
THRM_SMBCLK<36,46>

REM_DIODE1_P
REM_DIODE1_N

+3VSUS_THRM

R429 1K_0402_5%~D

1 2

R432 1K_0402_5%~D

1 2
THERMATRIP1#
THERMATRIP2#
THERMATRIP3#

2200P_0402_50V7K~D

R437

MDC_RST_DIS#<25>
SIO_GFX_PWR<18>

12

C

C203

E

3 1

1K_0402_5%~D

1 2

R433

8.2K_0402_5%~D

0.1U_0402_16V4Z~D@

1

2

2

1

AUDIO_AVDD_ON<26>

+3.3V_SUS

2

B

Q76

PWR_MON<45>

U31

11

SMDATA

12

SMBCLK

38

DP1

37

DN1

41

DP2

40

DN2

35

3V_SUS

21

RTC_PWR3V

23

+FAN1_VOUT

FAN2_PWM

MDC_RST_DIS#
SIO_GFX_PWR
5V_CAL_SIO#

AUDIO_AVDD_ON

VSUS_PWRGD

16

3V_PWROK#

17

THERMTRIP1#

18

THERMTRIP2#

19

THERMTRIP3#

42

VSET

26

XEN

34

VSS

7

FAN_OUT

8

FAN_OUT

39

FAN_DAC1

10

GPIO1

13

GPIO2

14

GPIO3

15

GPIO4

22

GPIO5

36

GPIO6/FAN_DAC2

49

PAD_GND

EMC4001_QFN48~D

POWER_SW#

ACAVAIL_CLR

THERMTRIP_SIO

LDO_SHDN#/ADDR

SMBus address: 2F

THERMATRIP3#

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

VCP1
VCP2

DP3
DN3

DP4
DN4

DP5
DN5

ATF_INT#

SYS_SHDN#

LDO_POK
LDO_SET
LDO_OUT

LDO_OUT

LDO_IN
LDO_IN

VDD_3V
VDD_5V

VDD_5V

43
46

45
44

48
47

2
1

20
3
4
25
24
27
33
28
32

31

30
29

9
5

6

+5V_RUN

C645

1

2

VCP2
REM_DIODE3_P

REM_DIODE3_N
REM_DIODE4_P

REM_DIODE4_N

7.5K_0402_5%~D
LDO_SET

+3V_LDOIN

10U_0805_10V4Z~D

C646

1

2

R434

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

2

ATF_INT#

ATF_INT# <35>

POWER_SW# <36,37>

ACAV_IN <18,36,46>

12

0.1U_0402_16V4Z~D

1

C649

2

2200P_0402_50V7K~D

Diode circuit at DP4/DN4 is used for skin temp sensor
(placed optimally between CPU, MCH and GPU)

1

C418

2

2200P_0402_50V7K~D

R96

10K_0402_5%~D

+3.3V_SUS

2.5V_RUN_PWRGD <39>

1

1

2

1

2

1

2

C640

2

0_1210_5%~D

C643

1U_0603_10V4Z~D

@

+3.3V_RUN

1

C647
10U_0805_10V4Z~D

2

C644

C641

1

2

C648

C

Q41

2

B

E

2

B

12

+3.3V_SUS

R430

10K_0402_5%~D

R431

10K_0402_5%~D@

+2.5V_RUN

10U_0805_10V4Z~D@

+3.3V_RUN

R439

12

2200P_0402_50V7K~D@

MMST3904-7-F_SOT323-3~D

3 1

C649 close to Guardian and
C650 close to diode Q41

C

Q19

2200P_0402_50V7K~D@

MMST3904-7-F_SOT323-3~D

C418 close to Guardian and
C904 close to diode Q19

R1608

0_0402_5%~D@

1 2

THERM_STP# <42>

+RTC_CELL

Voltage margining
circuit for LDO output

LDO_SET

For Vmargin, stuff Ra=31.6K and Rb=30K
For production, stuff Rb=1K only

12

E

3 1

+3.3V_ALW

12

DELL CONFIDENTIAL/PROPRIETARY

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.
SCHEMATIC, M /B LA-3751P

401490

C650

+2.5V_RUN

12

R485

12

R441

1

1

2

1

C904

2

THERMTRIP_SIO <35>

31.6K_0402_1%~D@

Ra

1K_0402_1%~D

Rb

15 48Wednesday, March 28, 2007

A

of

5

Layout Note:
Place near JDIMB

0.1U_0402_16V4Z~D

C918

1

2

M_ODT3
DDR_CS3_DIMMB#
DDR_B_CAS#
DDR_B_WE#

DDR_B_BS0
DDR_B_MA10
DDR_B_MA1
DDR_B_MA3

DDR_B_MA5
DDR_B_MA8
DDR_B_MA9
DDR_B_MA12

5

+1.8V_SUS

C907

C912

Layout Note:
Place one cap close to every 2 pullup
resistors terminated to +0.9V_DDR_VTT

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

C920

C919

1

1

2

2

RP1
1 8
2 7
3 6
4 5

56_1206_8P4R_5%~D

RP3
1 8
2 7
3 6
4 5

56_1206_8P4R_5%~D

RP5
1 8
2 7
3 6
4 5

56_1206_8P4R_5%~D

2.2U_0603_6.3V6K~D

1

2

0.1U_0402_16V4Z~D

1

2

0.1U_0402_16V4Z~D

C921

1

2

+0.9V_DDR_VTT

C908

C913

2.2U_0603_6.3V6K~D

C909

1

1

2

2

0.1U_0402_16V4Z~D

C914

1

1

2

2

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

C922

C923

1

1

2

2

RP2
1 8
2 7
3 6
4 5

56_1206_8P4R_5%~D

RP4
1 8
2 7
3 6
4 5

56_1206_8P4R_5%~D

RP6
1 8
2 7
3 6
4 5

56_1206_8P4R_5%~D

1 2

R1272 56_0402_5%~D

1 2

R777 56_0402_5%~D

1 2

R778 56_0402_5%~D

2.2U_0603_6.3V6K~D

C910

1

2

0.1U_0402_16V4Z~D

C915

1

2

0.1U_0402_16V4Z~D

C924

1

2

DDR_B_MA13
M_ODT2
DDR_CS2_DIMMB#
DDR_B_RAS#

DDR_B_BS1
DDR_B_MA0
DDR_B_MA2
DDR_B_MA4

DDR_B_MA6
DDR_B_MA7
DDR_B_MA11
DDR_CKE3_DIMMB

DDR_B_MA14

DDR_B_BS2

DDR_CKE2_DIMMB

2.2U_0603_6.3V6K~D

C911

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

C925

1

2

D D

C C

+0.9V_DDR_VTT

0.1U_0402_16V4Z~D

C916

C917

1

2

B B

A A

4

DDR_B_D[0..63]<11>
DDR_B_DM[0..7]<11>
DDR_B_DQS[0..7]<11>
DDR_B_DQS#[0..7]<11>

2.2U_0603_6.3V6K~D

1

2

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

C926

C927

1

1

2

2

Layout Note:
Place these resistors
close to JDIMB

C928

1

2

DDR_B_MA[0..14]<11>

0.1U_0402_16V4Z~D

1

2

DDR_CKE2_DIMMB<10>

DDR_CS3_DIMMB#<10>

3

DDR_B_BS2<11>

DDR_B_BS0<11>
DDR_B_WE#<11>

DDR_B_CAS#<11>

MEM_SDATA<17,22,31>
MEM_SCLK<17,22,31>

+3.3V_RUN

VSS
DQ4
DQ5
VSS

DM0

VSS
DQ6
DQ7

VSS
DQ12
DQ13

VSS

DM1

VSS

CK0

CK0#

VSS
DQ14
DQ15

VSS

VSS
DQ20
DQ21

VSS

DM2

VSS
DQ22
DQ23

VSS
DQ28
DQ29

VSS

DQS3#

DQS3

VSS
DQ30
DQ31

VSS

NC/CKE1

VDD
NC/A15
NC/A14

VDD

VDD

VDD

BA1

RAS#

VDD

ODT0

NC/A13

VDD

VSS
DQ36
DQ37

VSS

DM4

VSS
DQ38
DQ39

VSS
DQ44
DQ45

VSS

DQS5#

DQS5

VSS
DQ46
DQ47

VSS
DQ52
DQ53

VSS

CK1

CK1#

VSS

DM6

VSS
DQ54
DQ55

VSS
DQ60
DQ61

VSS

DQS7#

DQS7

VSS
DQ62
DQ63

VSS

SAO

SA1

2

2.2U_0603_6.3V6K~D

0.1U_0402_16V4Z~D

C906

1

1

2

2

R775

C905

M_CLK_DDR2 <10>

M_CLK_DDR#2 <10>

PM_EXTTS#1 <10>

DDR_CKE3_DIMMB <10>

DDR_B_BS1 <11>

DDR_B_RAS# <11>
DDR_CS2_DIMMB# <10>

M_ODT2 <10>

M_CLK_DDR3 <10>

M_CLK_DDR#3 <10>

+3.3V_RUN

2

DDR_B_D5

4

DDR_B_D4

6
8

DDR_B_DM0

10
12

DDR_B_D6DDR_B_DQS0

14

DDR_B_D7

16
18

DDR_B_D13

20

DDR_B_D12

22
24

DDR_B_DM1

26
28

M_CLK_DDR2

30

M_CLK_DDR#2

32
34

DDR_B_D10

36

DDR_B_D11

38
40

42

DDR_B_D16

44

DDR_B_D21

46
48

PM_EXTTS#1

50

NC

A11

A7
A6

A4
A2
A0

S0#

NC

DDR_B_DM2

52
54

DDR_B_D18

56

DDR_B_D19

58
60

DDR_B_D24

62

DDR_B_D25

64
66

DDR_B_DQS#3

68

DDR_B_DQS3

70
72

DDR_B_D26

74

DDR_B_D27

76
78

DDR_CKE3_DIMMB

80
82
84

DDR_B_MA14

86
88

DDR_B_MA11

90

DDR_B_MA7

92

DDR_B_MA6

94
96

DDR_B_MA4

98

DDR_B_MA2

100

DDR_B_MA0

102
104

DDR_B_BS1

106

DDR_B_RAS#

108

DDR_CS2_DIMMB#

110
112

M_ODT2

114

DDR_B_MA13

116
118
120
122

DDR_B_D36

124

DDR_B_D32

126
128

DDR_B_DM4

130
132

DDR_B_D38

134

DDR_B_D39

136
138

DDR_B_D44

140

DDR_B_D45

142
144

DDR_B_DQS#5

146

DDR_B_DQS5

148
150

DDR_B_D46

152

DDR_B_D43

154
156

DDR_B_D48

158

DDR_B_D52

160
162

M_CLK_DDR3

164

M_CLK_DDR#3

166
168

DDR_B_DM6

170
172

DDR_B_D55

174

DDR_B_D50

176
178

DDR_B_D60

180

DDR_B_D57

182
184

DDR_B_DQS#7

186

DDR_B_DQS7

188
190

DDR_B_D58

192

DDR_B_D59

194
196
198
200

R776

12

1 2

100K_0402_5%~D

10K_0402_5%~D

+1.8V_SUS +1.8V_SUS V_DDR_MCH_REF

JDIMB

1

VREF

3
DDR_B_D0
DDR_B_D1

DDR_B_DQS#0

DDR_B_D2
DDR_B_D3

DDR_B_D8
DDR_B_D9

DDR_B_DQS#1
DDR_B_DQS1

DDR_B_D14
DDR_B_D15

DDR_B_D20
DDR_B_D17

DDR_B_DQS#2
DDR_B_DQS2

DDR_B_D22
DDR_B_D23

DDR_B_D28
DDR_B_D29

DDR_B_DM3

DDR_B_D30
DDR_B_D31

DDR_CKE2_DIMMB

DDR_B_BS2
DDR_B_MA12

DDR_B_MA9
DDR_B_MA8

DDR_B_MA5
DDR_B_MA3
DDR_B_MA1

DDR_B_MA10
DDR_B_BS0
DDR_B_WE#

DDR_B_CAS#
DDR_CS3_DIMMB#

M_ODT3<10>

M_ODT3
DDR_B_D33

DDR_B_D37
DDR_B_DQS#4

DDR_B_DQS4
DDR_B_D34

DDR_B_D35
DDR_B_D40

DDR_B_D41
DDR_B_DM5
DDR_B_D42

DDR_B_D47
DDR_B_D49

DDR_B_D53

DDR_B_DQS#6
DDR_B_DQS6

DDR_B_D54
DDR_B_D51

DDR_B_D56
DDR_B_D61

DDR_B_DM7
DDR_B_D62

DDR_B_D63
MEM_SDATA

MEM_SCLK

0.1U_0402_16V4Z~D

C929

1

2

C930

2.2U_0603_6.3V6K~D

1

2

5

7

9

11
13
15
17
19
21
23
25
27
29
31
33
35
37
39

41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97

99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199

VSS
DQ0
DQ1
VSS
DQS0#
DQS0
VSS
DQ2
DQ3
VSS
DQ8
DQ9
VSS
DQS1#
DQS1
VSS
DQ10
DQ11
VSS

VSS
DQ16
DQ17
VSS
DQS2#
DQS2
VSS
DQ18
DQ19
VSS
DQ24
DQ25
VSS
DM3
NC
VSS
DQ26
DQ27
VSS
CKE0
VDD
NC
BA2
VDD
A12
A9
A8
VDD
A5
A3
A1
VDD
A10/AP
BA0
WE#
VDD
CAS#
NC/S1#
VDD
NC/ODT1
VSS
DQ32
DQ33
VSS
DQS4#
DQS4
VSS
DQ34
DQ35
VSS
DQ40
DQ41
VSS
DM5
VSS
DQ42
DQ43
VSS
DQ48
DQ49
VSS
NC,TEST
VSS
DQS6#
DQS6
VSS
DQ50
DQ51
VSS
DQ56
DQ57
VSS
DM7
VSS
DQ58
DQ59
VSS
SDA
SCL
VDDSPD

FOX_AS0A426-M2S-TR~D

DIMMB

STANDARD

1

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

4

3

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.
SCHEMATIC, M /B LA-3751P

401490

1

16 48Thursday, March 29, 2007

A

of

5

Layout Note:
Place near JDIMA

C943

1

2

DDR_A_BS0
DDR_A_MA10
DDR_A_MA1
DDR_A_MA3

DDR_A_MA5
DDR_A_MA8

DDR_A_MA12

M_ODT1
DDR_CS1_DIMMA#
DDR_A_CAS#
DDR_A_WE#

+1.8V_SUS

C933

C938

Layout Note:
Place one cap close to every 2 pullup
resistors terminated to +0.9V_DDR_VTT

0.1U_0402_16V4Z~D

C945

1

1

2

2

56_1206_8P4R_5%~D

56_1206_8P4R_5%~D

56_1206_8P4R_5%~D

0.1U_0402_16V4Z~D

C946

1 8
2 7
3 6
4 5

1 8
2 7
3 6
4 5

1 8
2 7
3 6
4 5

0.1U_0402_16V4Z~D

C944

5

2.2U_0603_6.3V6K~D

1

2

0.1U_0402_16V4Z~D

1

2

1

2

RP7

RP9

RP11

2.2U_0603_6.3V6K~D

C934

1

2

0.1U_0402_16V4Z~D

C939

1

2

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

C947

1

2

+0.9V_DDR_VTT

C948

1 8
2 7
3 6
4 5

56_1206_8P4R_5%~D

1 8
2 7
3 6
4 5

56_1206_8P4R_5%~D

1 8
2 7
3 6
4 5

56_1206_8P4R_5%~D

1 2

R1273 56_0402_5%~D

1 2

R782 56_0402_5%~D

1 2

R783 56_0402_5%~D

C935

C940

1

2

1

2

1

2

RP8

RP10

RP12

2.2U_0603_6.3V6K~D

C936

0.1U_0402_16V4Z~D

C941

0.1U_0402_16V4Z~D

C949

1

2

2.2U_0603_6.3V6K~D

C937

1

2

0.1U_0402_16V4Z~D

1

2

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

C950

C951

1

2

DDR_A_MA6
DDR_A_MA7
DDR_A_MA11
DDR_A_MA14

DDR_A_MA13
M_ODT0
DDR_A_RAS#DDR_A_MA9
DDR_CS0_DIMMA#

DDR_A_BS1
DDR_A_MA0
DDR_A_MA2
DDR_A_MA4

DDR_CKE1_DIMMA

DDR_A_BS2

DDR_CKE0_DIMMA

D D

C C

+0.9V_DDR_VTT

0.1U_0402_16V4Z~D

C942

1

2

B B

A A

4

DDR_A_D[0..63]<11>
DDR_A_DQS[0..7]<11>
DDR_A_DQS#[0..7]<11>
DDR_A_DM[0..7]<11>

2.2U_0603_6.3V6K~D

1

2

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

C952

1

2

0.1U_0402_16V4Z~D

C953

1

1

2

2

Layout Note:
Place these resistors
close to JDIMA

4

DDR_A_MA[0..14]<11>

0.1U_0402_16V4Z~D

C954

1

2

DDR_CKE0_DIMMA<10>

DDR_CS1_DIMMA#<10>

3

DDR_A_BS2<11>

DDR_A_BS0<11>
DDR_A_WE#<11>

DDR_A_CAS#<11>

MEM_SDATA<16,22,31>
MEM_SCLK<16,22,31>

+3.3V_RUN

+1.8V_SUS +1.8V_SUS

JDIMA

1

VREF

3
DDR_A_D4
DDR_A_D0

DDR_A_DQS#0
DDR_A_DQS0

DDR_A_D1
DDR_A_D2

DDR_A_D9
DDR_A_D8

DDR_A_DQS#1
DDR_A_DQS1

DDR_A_D10
DDR_A_D11

DDR_A_D20
DDR_A_D16

DDR_A_DQS#2
DDR_A_DQS2

DDR_A_D18
DDR_A_D22

DDR_A_D28
DDR_A_D29

DDR_A_DM3

DDR_A_D27
DDR_A_D26

DDR_CKE0_DIMMA

DDR_A_BS2
DDR_A_MA12

DDR_A_MA9 DDR_A_MA7
DDR_A_MA8

DDR_A_MA5
DDR_A_MA3
DDR_A_MA1

DDR_A_MA10
DDR_A_BS0
DDR_A_WE#

DDR_A_CAS#
DDR_CS1_DIMMA#

M_ODT1<10>

M_ODT1
DDR_A_D36

DDR_A_D37
DDR_A_DQS#4

DDR_A_DQS4
DDR_A_D34

DDR_A_D39
DDR_A_D40

DDR_A_D41
DDR_A_DM5
DDR_A_D43

DDR_A_D47
DDR_A_D52

DDR_A_D53

DDR_A_DQS#6
DDR_A_DQS6

DDR_A_D51
DDR_A_D55

DDR_A_D61
DDR_A_D57

DDR_A_DM7
DDR_A_D59

DDR_A_D63
MEM_SDATA

MEM_SCLK

C955

1

2

0.1U_0402_16V4Z~D

2.2U_0603_6.3V6K~D

C956

1

2

5

7

9

11
13
15
17
19
21
23
25
27
29
31
33
35
37
39

41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97

99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199

FOX_AS0A426-M2R-TR~D

VSS
DQ0
DQ1
VSS
DQS0#
DQS0
VSS
DQ2
DQ3
VSS
DQ8
DQ9
VSS
DQS1#
DQS1
VSS
DQ10
DQ11
VSS

VSS
DQ16
DQ17
VSS
DQS2#
DQS2
VSS
DQ18
DQ19
VSS
DQ24
DQ25
VSS
DM3
NC
VSS
DQ26
DQ27
VSS
CKE0
VDD
NC
BA2
VDD
A12
A9
A8
VDD
A5
A3
A1
VDD
A10/AP
BA0
WE#
VDD
CAS#
NC/S1#
VDD
NC/ODT1
VSS
DQ32
DQ33
VSS
DQS4#
DQS4
VSS
DQ34
DQ35
VSS
DQ40
DQ41
VSS
DM5
VSS
DQ42
DQ43
VSS
DQ48
DQ49
VSS
NC,TEST
VSS
DQS6#
DQS6
VSS
DQ50
DQ51
VSS
DQ56
DQ57
VSS
DM7
VSS
DQ58
DQ59
VSS
SDA
SCL
VDDSPD

DIMMA

VSS
DQ4
DQ5
VSS

DM0

VSS
DQ6
DQ7

VSS
DQ12
DQ13

VSS

DM1

VSS

CK0

CK0#

VSS
DQ14
DQ15

VSS

VSS
DQ20
DQ21

VSS

DM2

VSS
DQ22
DQ23

VSS
DQ28
DQ29

VSS

DQS3#

DQS3

VSS
DQ30
DQ31

VSS

NC/CKE1

VDD
NC/A15
NC/A14

VDD

VDD

VDD

BA1

RAS#

VDD

ODT0

NC/A13

VDD

VSS
DQ36
DQ37

VSS

DM4

VSS
DQ38
DQ39

VSS
DQ44
DQ45

VSS

DQS5#

DQS5

VSS
DQ46
DQ47

VSS
DQ52
DQ53

VSS

CK1

CK1#

VSS

DM6

VSS
DQ54
DQ55

VSS
DQ60
DQ61

VSS

DQS7#

DQS7

VSS
DQ62
DQ63

VSS

SAO

SA1

2

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

42
44
46
48
50

NC

52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90

A11

92

A7

94

A6

96
98

A4

100

A2

102

A0

104
106
108
110

S0#

112
114
116
118
120

NC

122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200

REVERSE

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

2

DDR_A_D5
DDR_A_D6

DDR_A_DM0
DDR_A_D7

DDR_A_D3
DDR_A_D12

DDR_A_D13
DDR_A_DM1
M_CLK_DDR0

M_CLK_DDR#0
DDR_A_D15

DDR_A_D14

DDR_A_D21
DDR_A_D17

PM_EXTTS#0
DDR_A_DM2

DDR_A_D19
DDR_A_D23

DDR_A_D25
DDR_A_D24

DDR_A_DQS#3
DDR_A_DQS3

DDR_A_D30
DDR_A_D31

DDR_CKE1_DIMMA

DDR_A_MA14
DDR_A_MA11
DDR_A_MA6
DDR_A_MA4

DDR_A_MA2
DDR_A_MA0

DDR_A_BS1
DDR_A_RAS#
DDR_CS0_DIMMA#

M_ODT0
DDR_A_MA13

DDR_A_D33
DDR_A_D32

DDR_A_DM4
DDR_A_D35

DDR_A_D38
DDR_A_D44

DDR_A_D45
DDR_A_DQS#5

DDR_A_DQS5
DDR_A_D42

DDR_A_D46
DDR_A_D48

DDR_A_D49
M_CLK_DDR1

M_CLK_DDR#1
DDR_A_DM6
DDR_A_D50

DDR_A_D54
DDR_A_D60

DDR_A_D56
DDR_A_DQS#7

DDR_A_DQS7
DDR_A_D58

DDR_A_D62

100K_0402_5%~D

12

R780

R781

1

C931

M_CLK_DDR0 <10>
M_CLK_DDR#0 <10>

PM_EXTTS#0 <10>

DDR_CKE1_DIMMA <10>

DDR_A_BS1 <11>
DDR_A_RAS# <11>
DDR_CS0_DIMMA# <10>

M_ODT0 <10>

M_CLK_DDR1 <10>
M_CLK_DDR#1 <10>

100K_0402_5%~D

12

V_DDR_MCH_REF

2.2U_0603_6.3V6K~D

1

2

C932

0.1U_0402_16V4Z~D

1

2

DELL CONFIDENTIAL/PROPRIETARY

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.
SCHEMATIC, M /B LA-3751P

401490

1

17 48Thursday, March 29, 2007

A

of

5

+3.3V_RUN

C959

D D

C996

RUN_ON

5

0.1U_0603_50V4Z~D

2

1

G

S

PEG_MTX_GRX_C_P[0..15]

PEG_MTX_GRX_C_N[0..15]

C997

2

PEG_MTX_GRX_C_P[0..15]<12>

PEG_MTX_GRX_C_N[0..15]<12>

PEG_MTX_GRX_C_P0
PEG_MTX_GRX_C_N0

PEG_MTX_GRX_C_P1
PEG_MTX_GRX_C_N1

PEG_MTX_GRX_C_P2
PEG_MTX_GRX_C_N2

PEG_MTX_GRX_C_P3
PEG_MTX_GRX_C_N3

PEG_MTX_GRX_C_P4

C C

B B

A A

PEG_MTX_GRX_C_N4
PEG_MTX_GRX_C_P5

PEG_MTX_GRX_C_N5
PEG_MTX_GRX_C_P6

PEG_MTX_GRX_C_N6
PEG_MTX_GRX_C_P7

PEG_MTX_GRX_C_N7
PEG_MTX_GRX_C_P8

PEG_MTX_GRX_C_N8
PEG_MTX_GRX_C_P9

PEG_MTX_GRX_C_N9
PEG_MTX_GRX_C_P10

PEG_MTX_GRX_C_N10
PEG_MTX_GRX_C_P11

PEG_MTX_GRX_C_N11
PEG_MTX_GRX_C_P12

PEG_MTX_GRX_C_N12
PEG_MTX_GRX_C_P13

PEG_MTX_GRX_C_N13
PEG_MTX_GRX_C_P14

PEG_MTX_GRX_C_N14
PEG_MTX_GRX_C_P15

PEG_MTX_GRX_C_N15

RUN_ON<36,38,39>

0.047U_0402_16V4Z~D

0.047U_0402_16V4Z~D

C960

1

2

C962 0.1U_0402_10V7K~D

1 2

C964 0.1U_0402_10V7K~D

1 2

C966 0.1U_0402_10V7K~D

1 2

C968 0.1U_0402_10V7K~D

1 2

C970 0.1U_0402_10V7K~D

1 2

C972 0.1U_0402_10V7K~D

1 2

C975 0.1U_0402_10V7K~D

1 2

C977 0.1U_0402_10V7K~D

1 2

C979 0.1U_0402_10V7K~D

1 2

C982 0.1U_0402_10V7K~D

1 2

C984 0.1U_0402_10V7K~D

1 2

C986 0.1U_0402_10V7K~D

1 2

C988 0.1U_0402_10V7K~D

1 2

C990 0.1U_0402_10V7K~D

1 2

C992 0.1U_0402_10V7K~D

1 2

C994 0.1U_0402_10V7K~D

1 2

+GFX_PWR_SRC

0.1U_0603_50V4Z~D

R791

2

1

PEG_PWRON#

13

D

Q107
2N7002W-7-F_SOT323-3~D

0.047U_0402_16V4Z~D

C961

1

1

2

2

C963 0.1U_0402_10V7K~D

1 2

C965 0.1U_0402_10V7K~D

1 2

C967 0.1U_0402_10V7K~D

1 2

C969 0.1U_0402_10V7K~D

1 2

C971 0.1U_0402_10V7K~D

1 2

C974 0.1U_0402_10V7K~D

1 2

C976 0.1U_0402_10V7K~D

1 2

C978 0.1U_0402_10V7K~D

1 2

C981 0.1U_0402_10V7K~D

1 2

C983 0.1U_0402_10V7K~D

1 2

C985 0.1U_0402_10V7K~D

1 2

C987 0.1U_0402_10V7K~D

1 2

C989 0.1U_0402_10V7K~D

1 2

C991 0.1U_0402_10V7K~D

1 2

C993 0.1U_0402_10V7K~D

1 2

C995 0.1U_0402_10V7K~D

1 2

1
2
3 6

100K_0402_5%~D

1 2

1

C998

0.1U_0603_50V4Z~D

2

4

GPWR_SRC_ON

12

R793
100K_0402_5%~D

DVI2_TX0+<34>
DVI2_TX0-<34>

DVI2_TX1+<34>
DVI2_TX1-<34>

DVI2_TX2+<34>
DVI2_TX2-<34>

DVI2_CLK+<34>
DVI2_CLK-<34>

RUNPWROK<35,36,39,45>

+GFX_PWR_SRC+PWR_SRC

8
7

5

Q106
FDS6679AZ_SO8~D

DVI_CLK+
DVI_CLK-

DVI2_TX0+
DVI2_TX0-

DVI2_TX1+
DVI2_TX1-

DVI2_TX2+
DVI2_TX2-

DVI2_CLK+
DVI2_CLK-

DVI_TX0+
DVI_TX0-

DVI_TX1+
DVI_TX1-

DVI_TX2+
DVI_TX2-

PEG_MTX_GRX_P0
PEG_MTX_GRX_N0

PEG_MTX_GRX_P1
PEG_MTX_GRX_N1

PEG_MTX_GRX_P2
PEG_MTX_GRX_N2

PEG_MTX_GRX_P3
PEG_MTX_GRX_N3

PEG_MTX_GRX_P4
PEG_MTX_GRX_N4

PEG_MTX_GRX_P5
PEG_MTX_GRX_N5

PEG_MTX_GRX_P6
PEG_MTX_GRX_N6

PEG_MTX_GRX_P7
PEG_MTX_GRX_N7

PEG_MTX_GRX_P8
PEG_MTX_GRX_N8

PEG_MTX_GRX_P9
PEG_MTX_GRX_N9

PEG_MTX_GRX_P10
PEG_MTX_GRX_N10

PEG_MTX_GRX_P11
PEG_MTX_GRX_N11

PEG_MTX_GRX_P12
PEG_MTX_GRX_N12

PEG_MTX_GRX_P13
PEG_MTX_GRX_N13

PEG_MTX_GRX_P14
PEG_MTX_GRX_N14

PEG_MTX_GRX_P15
PEG_MTX_GRX_N15

+3.3V_SUS

1

C999

0.1U_0603_50V4Z~D

2

+15V_ALW

+2.5V_RUN

4

4

JVGA

1

1

3

3

5

5

7

7

9

9

11

11

13

13

15

15

17

17

19

19

21

21

23

23

25

25

27

27

29

29

31

31

33

33

35

35

37

37

39

39

41

41

43

43

45

45

47

47

49

49

51

51

53

53

55

55

57

57

59

59

61

61

63

63

65

65

67

67

69

69

71

71

73

73

75

75

77

77

79

79

81

81

83

83

85

85

87

87

89

89

91

91

93

93

95

95

97

97

99

99

101

101

103

103

105

105

107

107

109

109

111

111

113

113

115

115

117

117

119

119

121

121

123

123

125

125

127

127

129

129

131

131

133

133

135

135

137

137

139

139

141

141

143

143

145

145

147

147

149

149

151

151

153

153

155

155

157

157

159

159

161

161

163

163

165

165

167

167

169

169

171

171

173

173

175

175

177

177

179

179

181

181

183

183

185

185

187

187

189

189

191

191

193

193

195

195

197

197

199

199

201

201

203

203

205

205

JAE_WB3M200VD1~D

+5V_ALW

2

2
4
6

8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98

100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204
206

4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204
206

LCD_TST
LCD_SMBCLK

LCD_SMBDAT
TV_Y_VGA
TV_CVBS_VGA
TV_C_VGA
VSYNC_VGA

HSYNC_VGA
BLU_VGA
GRN_VGA
RED_VGA
CLK_DDC2_VGA

DAT_DDC2_VGA
DVI_DETECT_L
DVI_SCLK_L
DVI_SDAT_L
PLTRST_DELAY#

CLK_PCIE_VGA
CLK_PCIE_VGA#

PEG_MRX_GTX_P0
PEG_MRX_GTX_N0

PEG_MRX_GTX_P1
PEG_MRX_GTX_N1

PEG_MRX_GTX_P2
PEG_MRX_GTX_N2

PEG_MRX_GTX_P3
PEG_MRX_GTX_N3

PEG_MRX_GTX_P4
PEG_MRX_GTX_N4

PEG_MRX_GTX_P5
PEG_MRX_GTX_N5

PEG_MRX_GTX_P6
PEG_MRX_GTX_N6

PEG_MRX_GTX_P7
PEG_MRX_GTX_N7

PEG_MRX_GTX_P8
PEG_MRX_GTX_N8

PEG_MRX_GTX_P9
PEG_MRX_GTX_N9

PEG_MRX_GTX_P10
PEG_MRX_GTX_N10

PEG_MRX_GTX_P11
PEG_MRX_GTX_N11

PEG_MRX_GTX_P12
PEG_MRX_GTX_N12

PEG_MRX_GTX_P13
PEG_MRX_GTX_N13

PEG_MRX_GTX_P14
PEG_MRX_GTX_N14

PEG_MRX_GTX_P15
PEG_MRX_GTX_N15

+3.3V_RUN

GFX_CORE_PWRGD
LCD_VCC_TEST_EN
THERMTRIP_VGA#

+5V_RUN

0.1U_0603_50V4Z~D

C1000

C1001

2

1

GFX_PWR_LIMIT

3

LCD_TST <35>
LCD_SMBCLK <36>

LCD_SMBDAT <36>
TV_Y_VGA <19,34>
TV_CVBS_VGA <19,34>
TV_C_VGA <19,34>

VSYNC_VGA <19>

HSYNC_VGA <19>
BLU_VGA <19,34>
GRN_VGA <19,34>
RED_VGA <19,34>

CLK_DDC2_VGA <19,34>

DAT_DDC2_VGA <19,34>

DVI_SCLK_L <34>
DVI_SDAT_L <34>

PLTRST_DELAY# <22>

CLK_PCIE_VGA <6>
CLK_PCIE_VGA# <6>

PEG_MRX_GTX_P[0..15]

PEG_MRX_GTX_N[0..15]

GFX_CORE_PWRGD <39>

LCD_VCC_TEST_EN <36>
THERMTRIP_VGA# <15>

PANEL_BKEN <35>

2

1

4

0.1U_0603_50V4Z~D

C1003

2

1

+3.3V_RUN

5

IN1

O

IN2

3

3

0.1U_0603_50V4Z~D

C1004

1

2

C1005

0.1U_0402_16V4Z~D
1

P

2

G

U37
74AHC1G08GW_SOT353-5~D

0.1U_0603_50V4Z~D

C1002

2

1

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

+GFX_PWR_SRC

10U_1206_25V6M~D@

12

SIO_GFX_PWR
ACAV_IN

+3.3V_RUN

C

1 2

2

B

E

100K_0402_5%~D

3 1

Q103

MMST3904-7-F_SOT323-3~D

12

R787
10K_0402_5%~D

PEG_MRX_GTX_P[0..15] <12>

PEG_MRX_GTX_N[0..15] <12>

SIO_GFX_PWR <15>
ACAV_IN <15,36,46>

R786

DVI_DETECT

DVI_DETECT_L <34>

2

DVI_CLK- DVI_C_CLK-

DVI_TX0+ DVI_C_TX0+

DVI_TX1- DVI_C_TX1-

DVI_TX2- DVI_C_TX2-

+5V_RUN

DVI_SCLK_L

2

DVI_C_TX2­DVI_C_TX2+

DVI_SCLK
DVI_SDAT
DVI_C_TX1­DVI_C_TX1+

+5V_RUN

RB500V-40 TE-17_SOD323-2~D

JDVI

1

DATA2#

2

DATA2

3

SHIELD24

4

DATA4#

5

DATA4

6

DDCCLK

7

DDCDATA

9

DATA1#

10

DATA1

11

SHIELD13

12

DATA3#

8

CRT_VSYNC

26

G1

27

G3

29

G5

31

NC1

JAE_DV2R024NDA~D

0_0402_5%~D

1 2

0_0402_5%~D

1 2

1

1

4

4

L133

0_0402_5%~D

1 2

0_0402_5%~D

1 2

1

1

4

4

L134

0_0402_5%~D

1 2

0_0402_5%~D

1 2

1

1

4

4

L135

0_0402_5%~D

1 2

0_0402_5%~D

1 2

1

1

4

4

L136

R789

1 2

4.7K_0402_5%~D

S

Q105

2N7002W-7-F_SOT323-3~D

1

2 1

SHIELDCLK

R1621

R1622

DLW21SN121SQ2L_4P~D@

R1623

R1624

DLW21SN121SQ2L_4P~D@

R1625

R1626

DLW21SN121SQ2L_4P~D@

R1627

R1628

DLW21SN121SQ2L_4P~D@

S

G

2

13

D

D20

DATA0#

SHIELD5

DATA5#

G

2

DATA3

HPDET

DATA0

DATA5

1 2

BLM31AJ260SN1L_1206~D

13
14

VCC5

15

GND5

16
17
18
19
20
21
22
23

CLK

24

CLK#

25

G2

28

G4

30

G6

32

NC2

2

2

3

3

2

2

3

3

2

2

3

3

2

2

3

3

Q104
2N7002W-7-F_SOT323-3~D

13

D

1

C973
220P_0402_50V7K~D

2

1

C980
220P_0402_50V7K~D

2

L88

DVI_DETECT
DVI_C_TX0­DVI_C_TX0+

DVI_C_CLK+
DVI_C_CLK-

DVI_C_CLK+DVI_CLK+

DVI_C_TX0-DVI_TX0-

DVI_C_TX1+DVI_TX1+

DVI_C_TX2+DVI_TX2+

DVI_SCLK

DVI_SDATDVI_SDAT_L

+5V_DVI

10U_0805_10V4Z~D

0.1U_0402_16V4Z~D
C958

C957

1

1

2

2

+5V_DVI

5.6K_0402_5%~D

12

R788

5.6K_0402_5%~D

12

R790

DELL CONFIDENTIAL/PROPRIETARY

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.
SCHEMATIC, M /B LA-3751P

401490

1

18 48Wednesday, March 28, 2007

of

A

5

4

3

2

1

Close to JSVID

C1006

22P_0402_50V8J~D@

TV_C_VGA<18,34>

D D

TV_CVBS_VGA<18,34>

TV_Y_VGA<18,34>

C C

150_0402_1%~D

R794

R795

R796

47P_0402_50V8J~D

12

C1007

1

2

47P_0402_50V8J~D

150_0402_1%~D

12

C1010

1

2

150_0402_1%~D

47P_0402_50V8J~D

12

C1014

1

2

1 2

470NH_LQM18NNR47K00D_10%_0603~D

470NH_LQM18NNR47K00D_10%_0603~D

470NH_LQM18NNR47K00D_10%_0603~D

L89

C1009

22P_0402_50V8J~D@

1 2

L90

C1012

22P_0402_50V8J~D@

1 2

L91

AUD_SPDIF_OUT<25,34>

47P_0402_50V8J~D

C1008

1

2

47P_0402_50V8J~D

C1011

1

2

47P_0402_50V8J~D

C1015

1

2

AUD_SPDIF_OUT

+3.3V_RUN

SVIDEO_C
SVIDEO_CVBS

SVIDEO_Y

+5V_RUN

C1013

0.1U_0402_16V4Z~D
AUD_SPDIF_SHDN

1

5

P

4

OE#

A2Y

G

U33

3

74AHCT1G125GW_SOT353-5~D

1

D21

DA204U_SOT323-3~D@

2

3

12

AUD_SPDIF_SHDN <25,35>

R798

SP_DIF SP_DIFB

12

220_0603_1%~D

1

2

C1016

SP_DIF_C

12

0.01U_0402_16V7K~D

1

2

3

SP_DIF_D

D23

C1017

DA204U_SOT323-3~D@

JSVID
2
4
6
7
5
3
1
8
9

FOX_MH11777-BUR6-7F~D

SP_DIF_E

300P_1808_3KV8K~D@

0_0805_5%~D

12

R1274

1

2

D22

DA204U_SOT323-3~D@

3

R799

1 2

110_0603_1%~D

0_0805_5%~D

12

R801

R809

1

D26

DA204U_SOT323-3~D@

2

3

+5V_RUN

21

D27
RB500V-40 TE-17_SOD323-2~D

10P_0402_50V8J~D@

C1021

1

2

2.2K_0402_5%~D

1 2

+CRT_VCC

1

2

R
DAT_DDC2_VGA

G
JVGA_HS

B
JVGA_VS

M_ID2#
CLK_DDC2_VGA

1

C1026

0.1U_0402_16V4Z~D

2

C1022

0.01U_0402_16V7K~D
JCRT

6

11

1
7

12

2
8

13

18

19
3
9

14

4

10
15

5

FOX_DZ11A91-ND201-7F~D

DELL CONFIDENTIAL/PROPRIETARY

Title

Size Document Number Rev

2

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, M/B LA-3751P

401490

1

19 48Wednesday, March 28, 2007

A

of

1

D24

Close to JCRT

L92

RED_VGA<18,34>

GRN_VGA<18,34>

BLU_VGA<18,34>

B B

A A

R803

150_0402_1%~D

150_0402_1%~D

12

12

R804

R805

HSYNC_VGA<18>

VSYNC_VGA<18>

150_0402_1%~D

12

C1023

1

2

22P_0402_50V8J~D@

22P_0402_50V8J~D@

C1024

C1025

1

2

R812

1 2

39_0402_5%~D

74AHCT1G125GW_SOT353-5~D

R814

1 2

39_0402_5%~D

1 2

BLM18BB600SN1D_0603~D

1 2

BLM18BB600SN1D_0603~D

1 2

BLM18BB600SN1D_0603~D

22P_0402_50V8J~D@

1

2

+CRT_VCC

U35

+CRT_VCC

L93

L94

1

5

P

OE#

A2Y

G

3

5

1

P

OE#

A2Y

G

U36

3

74AHCT1G125GW_SOT353-5~D

4

4

+3.3V_RUN

R811

1 2

1K_0402_5%~D

R813

0_0402_5%~D

R815

0_0402_5%~D

C1019

1

2

Place R813 near U35 and R815 near U36

5

4

DA204U_SOT323-3~D@

2

3

10P_0402_50V8J~D@

DAT_DDC2_VGA<18,34>

CLK_DDC2_VGA<18,34>

HSYNC_DOCK <34>

L95

1 2

BLM18AG121SN1D_0603~D

L96

1 2

BLM18AG121SN1D_0603~D

VSYNC_DOCK <34>

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

1

D25

DA204U_SOT323-3~D@

2

3

10P_0402_50V8J~D@

C1020

1

2

+CRT_VCC

R806

C1027

1K_0402_5%~D@

12

R807

22P_0402_50V8J~D

C1028

1

2

2.2K_0402_5%~D

1K_0402_5%~D@

12

R808

1 2

22P_0402_50V8J~D

1

2

5

4

3

2

1

+3.3V_RUN

R817 8.2K_0402_5%~D

D D

+3.3V_RUN

C C

1 2

R818 8.2K_0402_5%~D

1 2

R819 8.2K_0402_5%~D

1 2

R820 8.2K_0402_5%~D

1 2

R821 8.2K_0402_5%~D

1 2

R822 8.2K_0402_5%~D

1 2

R823 8.2K_0402_5%~D

1 2

R824 8.2K_0402_5%~D

1 2

R825 8.2K_0402_5%~D

1 2

R826 8.2K_0402_5%~D

1 2

R827 8.2K_0402_5%~D

1 2

R828 8.2K_0402_5%~D

1 2

R831 8.2K_0402_5%~D

1 2

R832 8.2K_0402_5%~D

1 2

R829 8.2K_0402_5%~D

1 2

PCI_DEVSEL#
PCI_STOP#
PCI_TRDY#
PCI_FRAME#
PCI_PLOCK#
PCI_IRDY#
PCI_SERR#
PCI_PERR#

PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#

PCI_REQ0#
PCI_REQ1#

ICH_GPIO2_PIRQE#

PCI_AD[0..31]<30,33>

PCI_PIRQA#<33>
PCI_PIRQC#<30>

PCI_PIRQD#<30>

PCI_AD0
PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD6
PCI_AD7
PCI_AD8
PCI_AD9
PCI_AD10
PCI_AD11
PCI_AD12
PCI_AD13
PCI_AD14
PCI_AD15
PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20
PCI_AD21
PCI_AD22
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30
PCI_AD31

PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#

U32B

D20

AD0

E19

AD1

D19

AD2

A20

AD3

D17

AD4

A21

AD5

A19

AD6

C19

AD7

A18

AD8

B16

AD9

A12

AD10

E16

AD11

A14

AD12

G16

AD13

A15

AD14

B6

AD15

C11

AD16

A9

AD17

D11

AD18

B12

AD19

C12

AD20

D10

AD21

C7

AD22

F13

AD23

E11

AD24

E13

AD25

E12

AD26

D8

AD27

A6

AD28

E8

AD29

D6

AD30

A3

AD31

F9

PIRQA#

B5

PIRQB#

C5

PIRQC#

A10

PIRQD#

NH82801HEM B1 QN24_BGA676~D

PCI

Interrupt I/F

REQ1#/GPIO50
GNT1#/GPIO51
REQ2#/GPIO52
GNT2#/GPIO53
REQ3#/GPIO54
GNT3#/GPIO55

PCIRST#

DEVSEL#

FRAME#

PLTRST#

PIRQE#/GPIO2

PIRQF#/GPIO3
PIRQG#/GPIO4
PIRQH#/GPIO5

REQ0#
GNT0#

C/BE0#
C/BE1#
C/BE2#
C/BE3#

IRDY#

PAR

PERR#

PLOCK#

SERR#

STOP#
TRDY#

PCICLK

PME#

PCI_REQ0#

A4

PCI_GNT0#

D7

PCI_REQ1#

E18

PCI_GNT1#

C18

SB_ROBSON_PCIE_RST#

B19
F18
A11

PCI_GNT3#

C10

PCI_C_BE0#

C17

PCI_C_BE1#

E15

PCI_C_BE2#

F16

PCI_C_BE3#

E17

PCI_IRDY#

C8

PCI_PAR

D9

PCI_PCIRST#

G6

PCI_DEVSEL#

D16

PCI_PERR#

A7

PCI_PLOCK#

B7

PCI_SERR#

F10

PCI_STOP#

C16

PCI_TRDY#

C9

PCI_FRAME#

A17

PCI_PLTRST#

AG24

CLK_PCI_ICH

B10

ICH_PME#

G7

ICH_GPIO2_PIRQE#

F8

SB_WLAN_PCIE_RST#

G11

SB_NB_PCIE_RST#

F12

PCIE_MCARD2_DET#

B3

PCI_REQ0# <34>

PCI_GNT0# <33,34>

PCI_REQ1# <30>

PCI_GNT1# <30>

SB_ROBSON_PCIE_RST# <31>

T77

SB_LOM_PCIE_RST# <28>

T78

PCI_SERR# <30,33>

CLK_PCI_ICH <6>

ICH_PME# <35>

SB_WLAN_PCIE_RST# <31>
SB_NB_PCIE_RST# <10>
PCIE_MCARD2_DET# <31>

PCI_C_BE0# <30,33>
PCI_C_BE1# <30,33>
PCI_C_BE2# <30,33>
PCI_C_BE3# <30,33>

PCI_IRDY# <30,33,34>
PCI_PAR <30,33>

PCI_DEVSEL# <30,33>
PCI_PERR# <30,33>

PCI_PLOCK# <33>

PCI_STOP# <30,33>

PCI_TRDY# <30,33>

PCI_FRAME# <30,33,34>

PCI_PCIRST#

PCI_PLTRST#

+3.3V_SUS

1
2

+3.3V_SUS

4
5

+3.3V_SUS

10

9

+3.3V_SUS

13
12

C1031

0.1U_0402_16V4Z~D

14

U38A

P

IN1
IN2

IN1
IN2

IN1
IN2

IN1
IN2

PCI_RST#

3

OUT
G

74VHC08MTCX_NL_TSSOP14~D

7

14

U38B

P

PLTRST1#

6

OUT
G

74VHC08MTCX_NL_TSSOP14~D

7

14

U38C

P

PLTRST2#

8

OUT
G

74VHC08MTCX_NL_TSSOP14~D

7

14

U38D

P

PLTRST3#PCI_PIRQD#

11

OUT
G

74VHC08MTCX_NL_TSSOP14~D

7

PCI_RST# <30,32,33>

PLTRST1# <10,32>

PLTRST2# <35,36>

PLTRST3# <28,31>

BIOS should not enable the internal GPIO pull up resistor

1

C1034
1U_0603_10V4Z~D

2

+RTC_CELL

SB_LOM_PCIE_RST#
SB_ROBSON_PCIE_RST#
SB_WLAN_PCIE_RST#
SB_NB_PCIE_RST#

JCOIN

1

1

2

2

MOLEX_53398-0290~D

4

A16 away override strap.

PCI_GNT3#

BOOT BIOS STRAP

PCI_GNT0# SPI_CS1#

*

0

1

1

Low = A16 swap override enabled.
High = Default.

Boot BIOS Location

1

0

1

SPI

PCI

LPC

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

PCI_GNT3#

PCI_GNT0#

12

R837

1K_0402_5%~D@

12

R838
1K_0402_5%~D

2

Place close to pin U32.B10

CLK_PCI_ICH

R840

10_0402_5%~D@

1 2

CLK_ICH_TERM

1

C1033

8.2P_0402_50V8J~D@

2

DELL CONFIDENTIAL/PROPRIETARY

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, M/B LA-3751P

401490

20 48Wednesday, March 28, 2007

1

of

A

R833 20K_0402_5%~D

1 2
1 2
1 2
1 2

R834 20K_0402_5%~D
R835 20K_0402_5%~D
R836 20K_0402_5%~D

B B

COIN CELL RTC BATTERY

+COINCELL

12

R841
1K_0402_5%~D

+COINCELL

+3.3V_RTC_LDO

A A

3

COINCELL_R

2

1

5

D28
BAT54CW_SOT323~D

5

ICH8-M Inte rna l VR Ena ble St rap
(Internal VR for VccSus1.05, VccSus1.5, VccCL1.5)

D D

C C

ICH_INTVRMEN

ICH8-M LAN100 SLP Strap
(Internal VR for VccLAN1.05 and VccCL1.05)

ICH_LAN100_SLP

B B

+3.3V_RUN

Low = Internal VR Disabled
High = Internal VR Enabled(Default)

+RTC_CELL

12

R842
332K_0402_1%~D

ICH_INTVRMEN

12

R844

0_0402_1%~D@

Low = Internal VR Disabled
High = Internal VR Enabled(Default)

+RTC_CELL

12

R843
332K_0402_1%~D

LAN100_SLP

R845

0_0402_5%~D@

1 2

R1615

SATA_ACT#

12

10K_0402_5%~D@

+RTC_CELL

PSATA_ITX_DRX_N0<24>

PSATA_ITX_DRX_P0<24>

Place close to U32

R862

R858

R860

ICH_AZ_BITCLK

ICH_AZ_SYNC

ICH_AZ_RST#

ICH_AZ_CODEC_BITCLK<25>

A A

ICH_AZ_CODEC_SYNC<25>

ICH_AZ_CODEC_RST#<25>

5

33_0402_5%~D

1

C1040
27P_0402_50V8J~D

2

33_0402_5%~D

33_0402_5%~D

1 2

1 2

1 2

4

C1035

15P_0402_50V8J~D

12

32.768K_12.5P_1TJS125DJ4A420P~D

15P_0402_50V8J~D

R849 20K_0402_5%~D
R850 1M_0402_5%~D

ICH_AZ_MDC_BITCLK<25>
ICH_AZ_MDC_SYNC<25>

ICH_AZ_MDC_RST#<25>

ICH_AZ_MDC_SDOUT<25>

ICH_AZ_CODEC_SDOUT<25>

C1041 3900P_0402_50V7K~D

C1042 3900P_0402_50V7K~D

C1036

12
1 2
1 2

1

1U_0603_10V4Z~D

C1038

27P_0402_50V8J~D

1

ICH_AZ_CODEC_SDIN0<25>

12

12

Y1

1 2

C1037

ICH_AZ_MDC_SDIN1<25>

PSATA_IRX_DTX_N0_C<24>
PSATA_IRX_DTX_P0_C<24>

Within 500 mils

4

ICH_RTCX1

1 4

2 3

R848

0_0402_5%~D

1 2

2

2

CMOS_CLR

12

R855 33_0402_5%~D

1 2
1 2

R857 33_0402_5%~D

1 2

R859 33_0402_5%~D

R863

33_0402_5%~D

1 2
1 2

R854

33_0402_5%~D

SATA_ACT#<37>

CLK_PCIE_SATA#<6>
CLK_PCIE_SATA<6>

12

+1.5V_RUN_PCIE_ICH

1 2

R866

24.9_0402_1%~D

R846
10M_0402_5%~D

ICH_RTCX2
ICH_RTCRST#
INTRUDER#
ICH_INTVRMEN

LAN100_SLP

24.9_0402_1%~D

12

R853

ICH_AZ_BITCLK
ICH_AZ_SYNC

ICH_AZ_RST#

ICH_AZ_SDOUT

SATA_ACT#

SATA_TX0-_N0
SATA_TX0+_P0

CLK_PCIE_SATA#
CLK_PCIE_SATA

3

2

XOR Chain Entrance STRAP

0
0
1

0
1
0

11

U32A

AG25

RTCX1

AF24

RTCX2

AF23

RTCRST#

AD22

INTRUDER#

AF25

INTVRMEN

AD21

LAN100_SLP

B24

GLAN_CLK

D22

LAN_RSTSYNC

C21

LAN_RXD0

B21

LAN_RXD1

C22

LAN_RXD2

D21

LAN_TXD_0

E20

LAN_TXD_1

C20

LAN_TXD_2

AH21

GLAN_DOCK#/GPIO13

D25

GLAN_COMPI

C25

GLAN_COMPO

AJ16

HDA_BIT_CLK

AJ15

HDA_SYNC

AE14

HDA_RST#

AJ17

HDA_SDIN0

AH17

HDA_SDIN1

AH15

HDA_SDIN2

AD13

HDA_SDIN3

AE13

HDA_SDOUT

AE10

HDA_DOCK_EN#/GPIO33

AG14

HDA_DOCK_RST#/GPIO34

AF10

SATALED#

AF6

SATA0RXN

AF5

SATA0RXP

AH5

SATA0TXN

AH6

SATA0TXP

AG3

SATA1RXN

AG4

SATA1RXP

AJ4

SATA1TXN

AJ3

SATA1TXP

AF2

SATA2RXN

AF1

SATA2RXP

AE4

SATA2TXN

AE3

SATA2TXP

AB7

SATA_CLKN

AC6

SATA_CLKP

AG1

SATARBIAS#

AG2

SATARBIAS

NH82801HEM B1 QN24_BGA676~D

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

RTC

LAN / GLAN

IHDA

SATA

LPCCPU

CPUPWRGD/GPIO49

IDE

FWH4/LFRAME#

LDRQ1#/GPIO23

FWH0/LAD0
FWH1/LAD1
FWH2/LAD2
FWH3/LAD3

LDRQ0#

A20GATE

A20M#

DPRSTP#

DPSLP#

FERR#

IGNNE#

INIT#
INTR

RCIN#

SMI#

STPCLK#

THRMTRIP#

DD10
DD11
DD12
DD13
DD14
DD15

DCS1#
DCS3#

DIOR#

DIOW#

DDACK#

IDEIRQ

IORDY

DDREQ

NMI

TP8
DD0

DD1
DD2
DD3
DD4
DD5
DD6
DD7
DD8
DD9

DA0
DA1
DA2

E5
F5
G8
F6

C4
G9

E6
AF13

AG26
AF26

AE26
AD24
AG29
AF27
AE24

AC20
AH14

AD23
AG28

AA24
AE27
AA23
V1

U2
V3
T1
V4
T5
AB2
T6
T3
R2
T4
V6
V5
U1
V2
U6

AA4
AA1
AB3

Y6
Y5

W4
W3
Y2
Y3
Y1
W5

2

DescriptionICH RSVD HDA SDOUT
RSVD
Enter XOR Chain
Normal Operation (Default)
Set PCIE port c onfig bit 1

LPC_LAD0
LPC_LAD1
LPC_LAD2
LPC_LAD3

LPC_LFRAME#
LPC_LDRQ0#

LPC_LDRQ1#
SIO_A20GATE

H_A20M#
H_DPRSTP#

H_DPSLP#
H_FERR#
H_PWRGOOD
H_IGNNE#
H_INIT#

H_INTR
SIO_RCIN#

H_NMI
H_SMI#

H_STPCLK#
THRMTRIP_ICH#
ICH_TP8
IDE_DD0

IDE_DD1
IDE_DD2
IDE_DD3
IDE_DD4
IDE_DD5
IDE_DD6
IDE_DD7
IDE_DD8
IDE_DD9
IDE_DD10
IDE_DD11
IDE_DD12
IDE_DD13
IDE_DD14
IDE_DD15

IDE_DA0
IDE_DA1
IDE_DA2

IDE_DCS1#
IDE_DCS3#

IDE_DIOR#
IDE_DIOW#
IDE_DDACK#
IDE_IRQ
IDE_DIORDY
IDE_DDREQ

LPC_LAD0 <28,35,36>
LPC_LAD1 <28,35,36>
LPC_LAD2 <28,35,36>
LPC_LAD3 <28,35,36>

LPC_LFRAME# <28,35,36>
LPC_LDRQ0# <35>

LPC_LDRQ1# <35>

SIO_A20GATE <36>
H_A20M# <7>

H_FERR# <7>
H_PWRGOOD <8>
H_IGNNE# <7>
H_INIT# <7>

H_INTR <7>
SIO_RCIN# <36>

H_NMI <7>
H_SMI# <7>

H_STPCLK# <7>

T79

IDE_DA0 <24>
IDE_DA1 <24>
IDE_DA2 <24>

IDE_DCS1# <24>
IDE_DCS3# <24>

IDE_DIOR# <24>
IDE_DIOW# <24>
IDE_DDACK# <24>
IDE_IRQ <24>
IDE_DIORDY <24>
IDE_DDREQ <24>

IDE_DD[0..15] <24>

DELL CONFIDENTIAL/PROPRIETARY

Title

Size Document Number Rev

Date: Sheet

+3.3V_RUN

12

R867

1K_0402_5%~D@

ICH_AZ_SDOUT

12

R868

1K_0402_5%~D@

+1.05V_VCCP

56_0402_1%~D@

56_0402_1%~D@

12

12

R851

R852

+1.05V_VCCP

12

R856
56_0402_5%~D

1

C1039

0.1U_0402_16V4Z~D@

2

SIO_A20GATE

SIO_RCIN#

H_FERR#

IDE_DIORDY

IDE_IRQ

Compal Electronics, Inc.

SCHEMATIC, M/B LA-3751P

401490

1

ICH_RSVD <22>

H_DPRSTP# <8,10,45>
H_DPSLP# <8>

R861

10K_0402_5%~D

R864

10K_0402_5%~D

R865

56_0402_5%~D

R1616

1 2

4.7K_0402_5%~D
R847

8.2K_0402_5%~D

21 48Wednesday, March 28, 2007

1

+3.3V_RUN

12

12

+1.05V_VCCP

12

+3.3V_RUN

12

A

of

5

+3.3V_RUN

12

12

R907

2.2K_0402_5%~D

MEM_SCLK<16,17,31>

D D

+3.3V_SUS

+3.3V_RUN

C C

MEM_SDATA<16,17,31>

ICH_CL_RST1#

ICH_RI#

LOM_ICH_SMBALERT#

ICH_PCIE_W AKE#

SIO_EXT_SMI#

SIO_EXT_SCI#

IRQ_SERIRQ

12

RSV_THRM#

12

IMVP_PWRGD

RSVD_GPIO39

RSVD_GPIO48

SPKR

MCH_ICH_SYNC#

1 2

R876 10K_0402_5%~D@

1 2

R883 10K_0402_5%~D

1 2

R892 10K_0402_5%~D

1 2

R887 1K_0402_5%~D

1 2

R895 10K_0402_5%~D

1 2

R886 10K_0402_5%~D

R875 10K_0402_5%~D

R873 10K_0402_5%~D

1 2

R870 2.2K_0402_5%~D@

1 2

R879 10K_0402_5%~D

1 2

R882 10K_0402_5%~D

1 2

R885 1K_0402_5%~D@

1 2

R871 10K_0402_5%~D@

MINI ROBSON (Mini Card 1)--->

MINI WLAN ( Mi n i Ca rd 2)--->

B B

A A

5

R906

2.2K_0402_5%~D

+3.3V_RUN

S

G

2

G

2

S

Pull down will disable CLKRUN#

EXPRESS CARD --->

GIGA LAN --->

ICH_SPI_CS1#

1K_0402_5%~D@

12

R839

D

ICH_SMBCLK

13

Q108

2N7002W-7-F_SOT323-3~D

ICH_SMBDATA

13

D

Q109

2N7002W-7-F_SOT323-3~D

+3.3V_RUN

12

R896

8.2K_0402_5%~D

CLKRUN#

12

R897

10_0402_5%~D@

No Reboot Strap

Low = Default

SPKR

High = No Reboot

PCIE_IRX_ROBSONTX_N1<31>
PCIE_IRX_ROBSONTX_P1<31>
PCIE_ITX_ROBSONRX_N1_C<31>
PCIE_ITX_ROBSONRX_P1_C<31>

PCIE_IRX_WLANTX_N2<31>

PCIE_IRX_WLANTX_P2<31>
PCIE_ITX_WLANRX_N2_C<31>
PCIE_ITX_WLANRX_P2_C<31>

PCIE_IRX_EXPTX_N4<32>

PCIE_IRX_EXPTX_P4<32>
PCIE_ITX_EXPRX_N4_C<32>
PCIE_ITX_EXPRX_P4_C<32>

+3.3V_SUS

PCIE_IRX_LANTX_N6<28>
PCIE_IRX_LANTX_P6<28>
PCIE_ITX_LANRX_N6_C<28>
PCIE_ITX_LANRX_P6_C<28>

ICH_EC_SPI_CLK<36>

ICH_SPI_CS0#<36>

ICH_EC_SPI_DO<36>

ICH_EC_SPI_DIN<36>

RP13

10K_1206_8P4R_5%~D

RP14

10K_1206_8P4R_5%~D

4

ICH_SMBCLK<28,31,32>

ICH_SMBDATA<28,31,32>

LOM_SMB_ALERT#<28,36>

PCIE_MCARD1_DET#<31>

USB_MCARD1_DET#<31>

C1045 0.1U_0402_10V7K~D

1 2

C1046 0.1U_0402_10V7K~D

1 2

C1047 0.1U_0402_10V7K~D

1 2

C1048 0.1U_0402_10V7K~D

1 2

C1049 0.1U_0402_10V7K~D

1 2

C1050 0.1U_0402_10V7K~D

1 2

C1052 0.1U_0402_10V7K~D

1 2

C1053 0.1U_0402_10V7K~D

1 2

ICH_EC_SPI_CLK
ICH_SPI_CS0#
ICH_SPI_CS1#

ICH_EC_SPI_DO
ICH_EC_SPI_DIN

USB_OC0_1#

45

USB_OC4_5#

36

USB_OC8_9#

27

USB_OC2#

18

45

USB_OC3#

36

USB_OC6#

27

USB_OC7#

18

4

+3.3V_SUS

12

R888

2.2K_0402_5%~D

ITP_DBRESET#<7,35>

PM_BMBUSY#<10>

1 2

R890 0_0402_5%~D@

H_STP_PCI#<6>
H_STP_CPU#<6>

CLKRUN#<30,35,36>

ICH_PCIE_W AKE#<35>

IRQ_SERIRQ<28,30,35,36>

IMVP_PWRGD<36,39,45>

T82

SIO_EXT_WAKE#<35>
SIO_EXT_SMI#<36>

SIO_EXT_SCI#<36>

R1641 4.7K_0402_5%~D

1 2

USB_MCARD2_DET#<31>

T106

IDE_RST_MOD<24>
SATA_CLKREQ#<6>

PLTRST_DELAY#<18>

SPKR<25>

MCH_ICH_SYNC#<10>

ICH_RSVD<21>

R902 15_0402_5%~D

1 2

R903 15_0402_5%~D

1 2

R904 15_0402_5%~D

1 2

R905 15_0402_5%~D

1 2

USB_OC0_1#<27>

USB_OC4_5#<27>

USB_OC8_9#<27>

12

R889

2.2K_0402_5%~D
ICH_SMBCLK

ICH_SMBDATA
ICH_CL_RST1#
ICH_SMLINK0
ICH_SMLINK1

ICH_RI#

ITP_DBRESET#
PM_BMBUSY#

LOM_ICH_SMBALERT#

H_STP_PCI#
H_STP_CPU#

CLKRUN#
ICH_PCIE_W AKE#

IRQ_SERIRQ
RSV_THRM#

IMVP_PWRGD
ICH_TP7

SIO_EXT_WAKE#
SIO_EXT_SMI#
SIO_EXT_SCI#

RSVD_GPIO27
IDE_RST_MOD
SATA_CLKREQ#
PLTRST_DELAY#
RSVD_GPIO39
RSVD_GPIO48

SPKR
MCH_ICH_SYNC#
ICH_RSVD

PCIE_IRX_ROBSONTX_N1
PCIE_IRX_ROBSONTX_P1
PCIE_ITX_ROBSONRX_N1
PCIE_ITX_ROBSONRX_P1

PCIE_IRX_WLANTX_N2
PCIE_IRX_WLANTX_P2
PCIE_ITX_WLANRX_N2
PCIE_ITX_WLANRX_P2

PCIE_IRX_EXPTX_N4
PCIE_IRX_EXPTX_P4
PCIE_ITX_EXPRX_N4
PCIE_ITX_EXPRX_P4

PCIE_IRX_LANTX_N6
PCIE_IRX_LANTX_P6
PCIE_ITX_LANRX_N6
PCIE_ITX_LANRX_P6

USB_OC0_1#
USB_OC2#

USB_OC3#
USB_OC4_5#

USB_OC6#
USB_OC7#
USB_OC8_9#

3

+3.3V_RUN

R872

U32C

AJ26

SMBCLK

AD19

SMBDATA

AG21

LINKALERT#

AC17

SMLINK0

AE19

SMLINK1

AF17

RI#

F4

SUS_STAT#/LPCPD#

AD15

SYS_RESET#

AG12

BMBUSY#/GPIO0

AG22

SMBALERT#/GPIO11

AE20

STP_PCI#/GPIO15

AG18

STP_CPU#/GPIO25

AH11

CLKRUN#/GPIO32

AE17

WAKE#

AF12

SERIRQ

AC13

THRM#

AJ20

VRMPWRGD

AJ22

TP7

AJ8

TACH1/GPIO1

AJ9

TACH2/GPIO6

AH9

TACH3/GPIO7

AE16

GPIO8

AC19

GPIO12

AG8

TACH0/GPIO17

AH12

GPIO18

AE11

GPIO20

AG10

SCLOCK/GPIO22

AH25

QRT_STATE0/GPIO27

AD16

QRT_STATE1/GPIO28

AG13

SATACLKREQ#/GPIO35

AF9

SLOAD/GPIO38

AJ11

SDATAOUT0/GPIO39

AD10

SDATAOUT1/GPIO48

AD9

SPKR

AJ13

MCH_SYNC#

AJ21

TP3

NH82801HEM B1 QN24_BGA676~D

U32D

P27

PERN1

P26

PERP1

N29

PETN1

N28

PETP1

M27

PERN2

M26

PERP2

L29

PETN2

L28

PETP2

K27

PERN3

K26

PERP3

J29

PETN3

J28

PETP3

H27

PERN4

H26

PERP4

G29

PETN4

G28

PETP4

F27

PERN5

F26

PERP5

E29

PETN5

E28

PETP5

D27

PERN6/GLAN_RXN

D26

PERP6/GLAN_RXP

C29

PETN6/GLAN_TXN

C28

PETP6/GLAN_TXP

C23

SPI_CLK

B23

SPI_CS0#

E22

SPI_CS1#

D23

SPI_MOSI

F21

SPI_MISO

AJ19

OC0#

AG16

OC1#/GPIO40

AG15

OC2#/GPIO41

AE15

OC3#/GPIO42

AF15

OC4#/GPIO43

AG17

OC5#/GPIO29

AD12

OC6#/GPIO30

AJ18

OC7#/GPIO31

AD14

OC8#

AH18

OC9#

NH82801HEM B1 QN24_BGA676~D

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

PCI - Express

SPI

USB

SMB

SATA

clocks

SYS / GPIOGPIOMISC

Power MGT

ME_EC_ALERT/GPIO10
EC_ME_ALERT/GPIO14

Controller Link

DMI0RXN
DMI0RXP

DMI1RXN
DMI1RXP

DMI2RXN
DMI2RXP

DMI3RXN
DMI3RXP

DMI_CLKN

DMI_CLKP

Direct Media Interface

DMI_ZCOMP

DMI_IRCOMP

USBRBIAS#

USBRBIAS

SATA0GP/GPIO21
SATA1GP/GPIO19
SATA2GP/GPIO36
SATA3GP/GPIO37

GPIO

S4_STATE#/GPIO26

DPRSLPVR/GPIO16

MEM_LED/GPIO24

WOL_EN/GPIO9

DMI0TXN
DMI0TXP

DMI1TXN
DMI1TXP

DMI2TXN
DMI2TXP

DMI3TXN
DMI3TXP

USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4N
USBP4P
USBP5N
USBP5P
USBP6N
USBP6P
USBP7N
USBP7P
USBP8N
USBP8P
USBP9N
USBP9P

CLK14
CLK48

SUSCLK

SLP_S3#
SLP_S4#
SLP_S5#

PWROK

BATLOW#
PWRBTN#

LAN_RST#

RSMRST#

CK_PWRGD

CLPWROK

SLP_M#

CL_CLK0
CL_CLK1

CL_DATA0
CL_DATA1

CL_VREF0
CL_VREF1

CL_RST#

DMI_MTX_IRX_N0

V27

DMI_MTX_IRX_P0

V26

DMI_MRX_ITX_N0

U29

DMI_MRX_ITX_P0

U28

DMI_MTX_IRX_N1

Y27

DMI_MTX_IRX_P1

Y26

DMI_MRX_ITX_N1

W29

DMI_MRX_ITX_P1

W28

DMI_MTX_IRX_N2

AB26

DMI_MTX_IRX_P2

AB25

DMI_MRX_ITX_N2

AA29

DMI_MRX_ITX_P2

AA28

DMI_MTX_IRX_N3

AD27

DMI_MTX_IRX_P3

AD26

DMI_MRX_ITX_N3

AC29

DMI_MRX_ITX_P3

AC28

CLK_PCIE_ICH#

T26

CLK_PCIE_ICH

T25
Y23

Y24
G3

G2
H5
H4
H2
H1
J3
J2
K5
K4
K2
K1
L3
L2
M5
M4
M2
M1
N3
N2

F2
F3

Within 500 mils

AJ12
AJ10
AF11
AG11

AG9
G5

D3
AG23

AF21
AD18

AH27
AE23
AJ14
AE21
C2
AH20
AG27
E1
E3
AJ25
F23

AE18
F22

AF19
D24

AH23
AJ23
AJ27

AJ24
AF22
AG19

DMI_IRCOMP
USBP0-

USBP0+
USBP1­USBP1+
USBP2­USBP2+
USBP3­USBP3+
USBP4­USBP4+
USBP5­USBP5+
USBP6­USBP6+
USBP7­USBP7+
USBP8­USBP8+
USBP9­USBP9+

USBRBIAS

8.2K_0402_5%~D

12

CLK_ICH_14M
CLK_ICH_48M

ICH_SUSCLK
SIO_SLP_S3#
SIO_SLP_S5#

ICH_PWRGD
DPRSLPVR
ICH_BATLOW#
SIO_PWRBTN#
ICH_LAN_RST#
ICH_RSMRST#
CLK_PWRGD
ICH_CL_PWROK

CL_CLK0

CL_DATA0

CL_VREF0_ICH

CL_RST0#

EC_ME_ALERT

DMI_MTX_IRX_N0 <10>
DMI_MTX_IRX_P0 <10>
DMI_MRX_ITX_N0 <10>
DMI_MRX_ITX_P0 <10>

DMI_MTX_IRX_N1 <10>
DMI_MTX_IRX_P1 <10>
DMI_MRX_ITX_N1 <10>
DMI_MRX_ITX_P1 <10>

DMI_MTX_IRX_N2 <10>
DMI_MTX_IRX_P2 <10>
DMI_MRX_ITX_N2 <10>
DMI_MRX_ITX_P2 <10>

DMI_MTX_IRX_N3 <10>
DMI_MTX_IRX_P3 <10>
DMI_MRX_ITX_N3 <10>
DMI_MRX_ITX_P3 <10>

CLK_PCIE_ICH# <6>
CLK_PCIE_ICH <6>

1 2

22.6_0402_1%~D

2

CLK_ICH_14M <6>
CLK_ICH_48M <6>

R893 8.2K_0402_5%~D

SIO_PWRBTN# <36>

ICH_RSMRST# <36>

ICH_CL_PWROK <10,36>

1 2

R891

8.2K_0402_5%~D

USBP0- <27>
USBP0+ <27>
USBP1- <27>

USBP1+ <27>

USBP2- <32>

USBP2+ <32>

USBP3- <32>

USBP3+ <32>

USBP4- <27>

USBP4+ <27>

USBP5- <27>

USBP5+ <27>

USBP6- <32>

USBP6+ <32>

USBP7- <34>

USBP7+ <34>

USBP8- <27>

USBP8+ <27>

USBP9- <27>

USBP9+ <27>

R908

2

T80

SIO_SLP_S3# <36>

SIO_SLP_S5# <36>

ICH_PWRGD <10,39>
DPRSLPVR <10,45>

12

CLK_PWRGD <6>

CL_CLK0 <10>

CL_DATA0 <10>

T85

CL_RST0# <10>

+3.3V_SUS

R901

24.9_0402_1%~D
1 2

--->Rear Right Bottom

--->Rear Right Top

--->Express Card

--->Bluetooth

--->Rear Left Bottom

--->Rear Left Top

--->OZ77CR6

--->Docking

--->Side Bottom

--->Side Top

1

Place closely pin U32.G5Place closely pin U32.AG9

CLK_ICH_48MCLK_ICH_14M

12

R894

10_0402_5%~D@

1

C1043

4.7P_0402_50V8C~D@

2

+3.3V_SUS

ICH_PWRGD

DPRSLPVR

ICH_LAN_RST#

ICH_RSMRST#

ICH_CL_PWROK

Place R901 within 500 mil
of the ICH8-M and avoid routing
next to clock pins

+1.5V_RUN_PCIE_ICH

R881 10K_0402_5%~D

R874 100K_0402_5%~D

R1642 1M_0402_1%~D

R884 10K_0402_5%~D

R869 1M_0402_1%~D

CL_VREF0_ICH

1 2

1 2

1 2

1 2

1 2

C1051

+3.3V_RUN

0.1U_0402_16V4Z~D

1

2

12

R898

10_0402_5%~D@

1

C1044

4.7P_0402_50V8C~D@

2

12

R899

3.24K_0402_1%~D

453_0402_1%~D

12

R900

DELL CONFIDENTIAL/PROPRIETARY

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, M/B LA-3751P

401490

22 48Wednesday, March 28, 2007

1

of

A

5

4

3

2

1

L97

1 2

L99

C1088

0.1U_0402_16V4Z~D

1

2

+RTC_CELL

C1054

1

2

+1.5V_RUN

C1090

C1074

1U_0603_10V4Z~D

0.1U_0402_16V4Z~D
C1056

C1055

1

1

2

2

1

C1060

+

2

10U_0805_4VAM~D

C1075

1

1

2

2

+1.5V_RUN

C1084

1

2

T90
T91

0.1U_0402_16V4Z~D

+1.5V_RUN_PCIE_ICH

220U_D2_4VY_R15M~D

C1061

1U_0603_10V4Z~D

0.1U_0402_16V4Z~D

+1.5V_RUN

4

+1.5V_RUN_PCIE_ICH

1

2

0.1U_0402_16V4Z~D
ICH_V5REF_RUN

ICH_V5REF_SUS

22U_0805_6.3V6M~D

22U_0805_6.3V6M~D

C1062

C1063

1

1

2

+1.5V_RUN_SATAPLL

+1.5V_RUN

C1081

1

2

C1091

1

2

2

1U_0603_10V4Z~D

1

+1.5V_RUN

2

C1082

1

2

C1085

0.1U_0402_16V4Z~D

+1.5V_RUN

TP_VCCLAN1.05_INT_ICH1
TP_VCCLAN1.05_INT_ICH2

4.7U_0603_6.3V4Z~D

1

+3.3V_RUN

2

2.2U_0603_6.3V6K~D

1U_0603_10V4Z~D

U32F

AD25

VCCRTC

A16

V5REF[1]

T7

V5REF[2]

G4

V5REF_SUS

AA25

VCC1_5_B[01]

AA26

VCC1_5_B[02]

AA27

VCC1_5_B[03]

AB27

VCC1_5_B[04]

AB28

VCC1_5_B[05]

AB29

VCC1_5_B[06]

D28

VCC1_5_B[07]

D29

VCC1_5_B[08]

E25

VCC1_5_B[09]

E26

VCC1_5_B[10]

E27

VCC1_5_B[11]

F24

VCC1_5_B[12]

F25

VCC1_5_B[13]

G24

VCC1_5_B[14]

H23

VCC1_5_B[15]

H24

VCC1_5_B[16]

J23

VCC1_5_B[17]

J24

VCC1_5_B[18]

K24

VCC1_5_B[19]

K25

VCC1_5_B[20]

L23

VCC1_5_B[21]

L24

VCC1_5_B[22]

L25

VCC1_5_B[23]

M24

VCC1_5_B[24]

M25

VCC1_5_B[25]

N23

VCC1_5_B[26]

N24

VCC1_5_B[27]

N25

VCC1_5_B[28]

P24

VCC1_5_B[29]

P25

VCC1_5_B[30]

R24

VCC1_5_B[31]

R25

VCC1_5_B[32]

R26

VCC1_5_B[33]

R27

VCC1_5_B[34]

T23

VCC1_5_B[35]

T24

VCC1_5_B[36]

T27

VCC1_5_B[37]

T28

VCC1_5_B[38]

T29

VCC1_5_B[39]

U24

VCC1_5_B[40]

U25

VCC1_5_B[41]

V23

VCC1_5_B[42]

V24

VCC1_5_B[43]

V25

VCC1_5_B[44]

W25

VCC1_5_B[45]

Y25

VCC1_5_B[46]

AJ6

VCCSATAPLL

AE7

VCC1_5_A[01]

AF7

VCC1_5_A[02]

AG7

VCC1_5_A[03]

AH7

VCC1_5_A[04]

AJ7

VCC1_5_A[05]

AC1

VCC1_5_A[06]

AC2

VCC1_5_A[07]

AC3

VCC1_5_A[08]

AC4

VCC1_5_A[09]

AC5

VCC1_5_A[10]

AC10

VCC1_5_A[11]

AC9

VCC1_5_A[12]

AA5

VCC1_5_A[13]

AA6

VCC1_5_A[14]

G12

VCC1_5_A[15]

G17

VCC1_5_A[16]

H7

VCC1_5_A[17]

AC7

VCC1_5_A[18]

AD7

VCC1_5_A[19]

D1

VCCUSBPLL

F1

VCC1_5_A[20]

L6

VCC1_5_A[21]

L7

VCC1_5_A[22]

M6

VCC1_5_A[23]

M7

VCC1_5_A[24]

W23

VCC1_5_A[25]

F17

VCCLAN1_05[1]

G18

VCCLAN1_05[2]

F19

VCCLAN3_3[1]

G20

VCCLAN3_3[2]

A24

VCCGLANPLL

A26

VCCGLAN1_5[1]

A27

VCCGLAN1_5[2]

B26

VCCGLAN1_5[3]

B27

VCCGLAN1_5[4]

B28

VCCGLAN1_5[5]

B25

VCCGLAN3_3

NH82801HEM B1 QN24_BGA676~D

VCC1_05[01]
VCC1_05[02]
VCC1_05[03]
VCC1_05[04]
VCC1_05[05]
VCC1_05[06]
VCC1_05[07]
VCC1_05[08]
VCC1_05[09]
VCC1_05[10]
VCC1_05[11]
VCC1_05[12]
VCC1_05[13]
VCC1_05[14]
VCC1_05[15]
VCC1_05[16]

CORE

VCC1_05[17]
VCC1_05[18]
VCC1_05[19]
VCC1_05[20]
VCC1_05[21]
VCC1_05[22]
VCC1_05[23]

VCCA3GP

ARX

ATX

USB CORE

GLAN POWER

VCC1_05[24]
VCC1_05[25]
VCC1_05[26]
VCC1_05[27]
VCC1_05[28]

VCCDMIPLL
VCC_DMI[1]

VCC_DMI[2]

V_CPU_IO[1]
V_CPU_IO[2]

VCC3_3[01]
VCC3_3[02]
VCC3_3[03]

VCC3_3[04]
VCC3_3[05]
VCC3_3[06]

VCCP_CORE

VCC3_3[07]
VCC3_3[08]
VCC3_3[09]
VCC3_3[10]

IDEPCI

VCC3_3[11]
VCC3_3[12]
VCC3_3[13]

VCC3_3[14]
VCC3_3[15]
VCC3_3[16]
VCC3_3[17]
VCC3_3[18]
VCC3_3[19]
VCC3_3[20]
VCC3_3[21]
VCC3_3[22]
VCC3_3[23]
VCC3_3[24]

VCCHDA

VCCSUSHDA

VCCSUS1_05[1]
VCCSUS1_05[2]

VCCSUS1_5[1]

VCCSUS1_5[2]
VCCSUS3_3[01]
VCCSUS3_3[02]

VCCSUS3_3[03]
VCCSUS3_3[04]
VCCSUS3_3[05]
VCCSUS3_3[06]

VCCPSUS

VCCSUS3_3[07]
VCCSUS3_3[08]
VCCSUS3_3[09]
VCCSUS3_3[10]
VCCSUS3_3[11]
VCCSUS3_3[12]
VCCSUS3_3[13]
VCCSUS3_3[14]
VCCSUS3_3[15]

VCCPUSB

VCCSUS3_3[16]
VCCSUS3_3[17]
VCCSUS3_3[18]
VCCSUS3_3[19]

VCCCL1_05

VCCCL1_5

VCCCL3_3[1]
VCCCL3_3[2]

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

+3.3V_RUN+5V_RUN

12

12

+1.5V_RUN

2

3

21

D30
RB751V_SOD323-2~D

ICH_V5REF_RUN

1

C1059

0.1U_0402_16V4Z~D

2

+3.3V_SUS+5V_SUS

21

D31
RB751V_SOD323-2~D

ICH_V5REF_SUS

1

C1068

0.1U_0402_16V4Z~D

2

R913

1 2

0_0603_5%~D

+VCCSATAPLLR

1 2

1

10_0805_5%~D
D29
MMBD4148-7-F_SOT23-3~D

5

R909

+3.3V_RUN

+1.5V_RUN

BLM21PG600SN1D_0805~D

1 2

10UH_LB2012T100MR_20%_0805~D

+1.5V_RUN

R914

1 2

0_0603_5%~D

R910

100_0402_5%~D

D D

R912

10_0402_5%~D

C C

+1.05V_VCCP

B B

A A

+1.05V_VCCP

A13
B13
C13
C14
D14
E14
F14
G14
L11
L12
L14
L16
L17
L18
M11
M18
P11
P18
T11
T18
U11
U18
V11
V12
V14
V16
V17
V18

R29
AE28

AE29
AC23

AC24
AF29
AD2
AC8

AD8
AE8
AF8

+3.3V_RUN

AA3
U7
V7
W1
W6
W7
Y7

A8
B15
B18
B4

C1077
B9
C15
D13
D5
E10
E7
F11

AC12
AD11

TP_VCCSUS1.05_INT_ICH1

J6

TP_VCCSUS1.05_INT_ICH2

AF20

VCCSUS1_5_ICH_1

AC16

VCCSUS1_5_ICH_2

J7
C3
AC18

AC21
AC22
AG20
AH28

P6
P7
C1
N7
P1
P2
P3
P4
P5
R1
R3
R5
R6

VCCCL1_05_ICH

G22
A22
F20

G21

0.1U_0402_16V4Z~D
C1058

C1057

1

2

C1064

1

2

C1066

+3.3V_RUN

1

C1076

0.1U_0402_16V4Z~D

2

0.1U_0402_16V4Z~D
C1078

1

2

C1086

+3.3V_SUS

0.1U_0402_16V4Z~D

C1089

1

2

+3.3V_RUN

1

2

0.01U_0402_16V7K~D

1

2

1

2

1

2

0.1U_0402_16V4Z~D

C1065

1

2

0.1U_0402_16V4Z~D

1

2

+3.3V_RUN

0.1U_0402_16V4Z~D
C1079

T88
T89

0.022U_0402_16V7K~D

T92

L98

1 2

BLM18PG181SN1_0603~D

10U_0805_4VAM~D

+1.25V_RUN

22U_0805_6.3V6M~D

C1067

1

2

+3.3V_RUN

C1073

0.1U_0402_16V4Z~D

+3.3V_RUN

0.1U_0402_16V4Z~D

1

2

+3.3V_SUS

T86
T87

+3.3V_SUS

0.022U_0402_16V7K~D

C1087

1

2

4.7U_0603_6.3V4Z~D
C1070

C1069

1

2

1

C1072

0.1U_0402_16V4Z~D

2

1

C1080

0.1U_0402_16V4Z~D

2

1

C1083

0.1U_0402_16V4Z~D

2

2

1_0603_1%~D

+1.05V_VCCP

0.1U_0402_16V4Z~D
C1071

1

2

+3.3V_RUN

R911

1

2

0.1U_0402_16V4Z~D

+1.5V_RUN

12

U32E

A23

VSS[001]

A5

VSS[002]

AA2

VSS[003]

AA7

VSS[004]

A25

VSS[005]

AB1

VSS[006]

AB24

VSS[007]

AC11

VSS[008]

AC14

VSS[009]

AC25

VSS[010]

AC26

VSS[011]

AC27

VSS[012]

AD17

VSS[013]

AD20

VSS[014]

AD28

VSS[015]

AD29

VSS[016]

AD3

VSS[017]

AD4

VSS[018]

AD6

VSS[019]

AE1

VSS[020]

AE12

VSS[021]

AE2

VSS[022]

AE22

VSS[023]

AD1

VSS[024]

AE25

VSS[025]

AE5

VSS[026]

AE6

VSS[027]

AE9

VSS[028]

AF14

VSS[029]

AF16

VSS[030]

AF18

VSS[031]

AF3

VSS[032]

AF4

VSS[033]

AG5

VSS[034]

AG6

VSS[035]

AH10

VSS[036]

AH13

VSS[037]

AH16

VSS[038]

AH19

VSS[039]

AH2

VSS[040]

AF28

VSS[041]

AH22

VSS[042]

AH24

VSS[043]

AH26

VSS[044]

AH3

VSS[045]

AH4

VSS[046]

AH8

VSS[047]

AJ5

VSS[048]

B11

VSS[049]

B14

VSS[050]

B17

VSS[051]

B2

VSS[052]

B20

VSS[053]

B22

VSS[054]

B8

VSS[055]

C24

VSS[056]

C26

VSS[057]

C27

VSS[058]

C6

VSS[059]

D12

VSS[060]

D15

VSS[061]

D18

VSS[062]

D2

VSS[063]

D4

VSS[064]

E21

VSS[065]

E24

VSS[066]

E4

VSS[067]

E9

VSS[068]

F15

VSS[069]

E23

VSS[070]

F28

VSS[071]

F29

VSS[072]

F7

VSS[073]

G1

VSS[074]

E2

VSS[075]

G10

VSS[076]

G13

VSS[077]

G19

VSS[078]

G23

VSS[079]

G25

VSS[080]

G26

VSS[081]

G27

VSS[082]

H25

VSS[083]

H28

VSS[084]

H29

VSS[085]

H3

VSS[086]

H6

VSS[087]

J1

VSS[088]

J25

VSS[089]

J26

VSS[090]

J27

VSS[091]

J4

VSS[092]

J5

VSS[093]

K23

VSS[094]

K28

VSS[095]

K29

VSS[096]

K3

VSS[097]

K6

VSS[098]

NH82801HEM B1 QN24_BGA676~D

VSS_NCTF[01]
VSS_NCTF[02]
VSS_NCTF[03]
VSS_NCTF[04]
VSS_NCTF[05]
VSS_NCTF[06]
VSS_NCTF[07]
VSS_NCTF[08]
VSS_NCTF[09]
VSS_NCTF[10]
VSS_NCTF[11]
VSS_NCTF[12]

VSS[099]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
VSS[159]
VSS[160]
VSS[161]
VSS[162]
VSS[163]
VSS[164]
VSS[165]
VSS[166]
VSS[167]
VSS[168]
VSS[169]
VSS[170]
VSS[171]
VSS[172]
VSS[173]
VSS[174]
VSS[175]
VSS[176]
VSS[177]
VSS[178]
VSS[179]
VSS[180]
VSS[181]
VSS[182]
VSS[183]
VSS[184]

K7
L1
L13
L15
L26
L27
L4
L5
M12
M13
M14
M15
M16
M17
M23
M28
M29
M3
N1
N11
N12
N13
N14
N15
N16
N17
N18
N26
N27
N4
N5
N6
P12
P13
P14
P15
P16
P17
P23
P28
P29
R11
R12
R13
R14
R15
R16
R17
R18
R28
R4
T12
T13
T14
T15
T16
T17
T2
U12
U13
U14
U15
U16
U17
U23
U26
U27
U3
U5
V13
V15
V28
V29
W2
W26
W27
Y28
Y29
Y4
AB4
AB23
AB5
AB6
AD5
U4
W24

A1
A2
A28
A29
AH1
AH29
AJ1
AJ2
AJ28
AJ29
B1
B29

DELL CONFIDENTIAL/PROPRIETARY

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, M/B LA-3751P

401490

23 48Wednesday, March 28, 2007

1

of

A

A

B

C

D

E

F

G

H

0.1U_0402_16V4Z~D@
C1104

1

2

JHDD

S1

GND

S2

RX+

S3

RX-

S4

GND

S5

TX-

S6

TX+

S7

GND

P1

3.3V

P2

3.3V

P3

3.3V

P4

GND

P5

GND

P6

GND

P7

5V

P8

5V

P9

5V

P10

GND

P11

Reserved

P12

GND

P13

12V

P14

12V

P15

GND1

12V

GND2

TYCO_1770615-2_RV~D

1U_0603_10V4Z~D@

C1095

1

1

2

2

1
2

10U_0805_10V4Z~D@

JODD

R1617

+5V_ODD

1 2

1 2

56_0402_5%~D

IDE_DIOW#<21>
IDE_DIORDY<21>

IDE_IRQ<21>

IDE_DA1<21>
IDE_DA0<21>
IDE_DCS1#<21>

IDE_DD0
IDE_DD1
IDE_DD2
IDE_DD3
IDE_DD4
IDE_DD5
IDE_DD6
IDE_DD7
IDE_DD8
IDE_DD9
IDE_DD10
IDE_DD11
IDE_DD12
IDE_DD13
IDE_DD14
IDE_DD15

1 1

2 2

IDE_RST_MOD<22>

R916

510_0402_5%~D

ODD_RST
IDE_DD7
IDE_DD6
IDE_DD5
IDE_DD4
IDE_DD3
IDE_DD2
IDE_DD1
IDE_DD0

IDE_DIOW#
IDE_DIORDY
IDE_IRQ
IDE_DA1
IDE_DA0
IDE_DCS1#
IDE_LED#

+5V_ODD

PRI_CSEL

R918
470_0402_5%~D

1 2

IDE_DD[0..15] <21>

1
3
5
7

9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49

SUYIN_80095AR-050G1T~D

2

1

2

4

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

IDE_DD8

6

IDE_DD9

8

IDE_DD10

10

IDE_DD11

12

IDE_DD12

14

IDE_DD13

16

IDE_DD14

18

IDE_DD15

20

IDE_DDREQ

22

IDE_DIOR#

24
26

RPDDACK#

28
30

PDIAG#

32

IDE_DA2

34

IDE_DCS3#

36
38
40
42
44

C1094

46
48

1 2

50

0.1U_0402_16V4Z~D

IDE_DDREQ <21>
IDE_DIOR# <21>

R915 22_0402_5%~D
R917 100K_0402_5%~D

1 2
1 2

IDE_DA2 <21>
IDE_DCS3# <21>

+5V_ODD

Layout Note: W=80 mils

IDE_DDACK# <21>

+5V_ODD

PSATA_IRX_DTX_N0_C<21>

PSATA_IRX_DTX_P0_C<21>

Layout Note: Place close to ODD CONN

+5V_ODD

0.1U_0402_16V4Z~D

1000P_0402_50V7K~D

C1106

C1105

1

2

C1107

1

2

10U_0805_10V4Z~D

1U_0603_10V4Z~D

C1108

1

1

2

2

Close SATA connector

C1092

3900P_0402_50V7K~D

12

12

C1093

3900P_0402_50V7K~D

Pleace close to HDD CONNECTOR

+5V_HDD +3.3V_RUN

1000P_0402_50V7K~D

C1096

C1097

1

2

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

C1098

C1099

1

1

2

2

1000P_0402_50V7K~D@

C1101

1

2

PSATA_ITX_DRX_P0
PSATA_ITX_DRX_N0

SATA_RX0-_N0

SATA_RX0+_P0

+3.3V_RUN

+5V_HDD

0.1U_0402_16V4Z~D@

C1102

C1103

1

2

PSATA_ITX_DRX_P0<21>
PSATA_ITX_DRX_N0<21>

10U_0805_10V4Z~D

1U_0603_10V4Z~D

C1100

1

1

2

2

3 3

4 4

+5V_ODD SOURCE

100K_0402_5%~D@

MODC_EN<35>

12

R925

1

2

MOD_EN

0.1U_0603_50V4Z~D@

+5V_ALW

1

G

3

6

2

D

Q110

SI3456BDV-T1-E3_TSOP6~D@

S

+5V_ODD

4 5

C1110

1

2

10U_0805_10V4Z~D

R923

100K_0402_5%~D

12

1 2

PAD-OPEN 4x4m

SHORT

PJP22

+5V_RUN

+15V_ALW

12

R919

+3.3V_ALW2

12

R920

2N7002W-7-F_SOT323-3~D@

13

D

Q114

2

2N7002W-7-F_SOT323-3~D@

G

S

100K_0402_5%~D@

Q112

100K_0402_5%~D@

2

C1109

13

D

2

G

S

+5V_HDD SOURCE

100K_0402_5%~D

HDDC_EN<35>

R926

12

100K_0402_5%~D

+3.3V_ALW2

R922

2

G

12

13

D

S

2N7002W-7-F_SOT323-3~D
Q115

2N7002W-7-F_SOT323-3~D

Q113

2

G

+15V_ALW

12

R921
100K_0402_5%~D

13

D

S

C1112

HDD_EN_5V

0.1U_0603_50V4Z~D

1

2

+5V_ALW

G

3

6

2

1

D

Q111
SI3456BDV-T1-E3_TSOP6~D

S

+5V_HDD

4 5

10U_0805_10V4Z~D

R924

C1113

1

2

100K_0402_5%~D

12

PJP23

1 2

PAD-OPEN 4x4m

OPEN

+5V_RUN

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

A

B

C

D

E

F

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, M /B LA-3751P

401490

G

24 48Wednesday, March 28, 2007

H

A

of

5

4

3

2

1

R1598

1 2

W = 30 mil

1U_0603_10V4Z~D

C1118

1

2

ICH_AZ_CODEC_BITCLK
ICH_AC_SDIN0_R

ICH_AZ_CODEC_SDOUT
ICH_AZ_CODEC_SYNC
ICH_AZ_CODEC_RST#

1 2

1000P_0402_50V7K~D

C1440

+3.3V_RUN

0.1U_0402_16V4Z~D

C1117

D D

1

2

ICH_AZ_CODEC_SDIN0<21>

Close to Pin 6

ICH_AZ_CODEC_BITCLK

12

R936
10_0402_5%~D

1

C1124
10P_0402_50V8J~D

2

C C

100K_0402_5%~D

1

2

ICH_AZ_CODEC_BITCLK<21>

R932 33_0402_5%~D

ICH_AZ_CODEC_SDOUT<21>

ICH_AZ_CODEC_SYNC<21>
ICH_AZ_CODEC_RST#<21>

Close to Pin 5

ICH_AZ_CODEC_SDOUT

12

R937

47_0402_5%~D @

1

C1125

0.1U_0402_16V4Z~D @

2

B B

AUD_EAPD<26>

AUD_SPDIF_OUT<19,34>

12

0.1U_0402_16V4Z~D
C1120

C1119

1

2

AUD_EAPD
AUD_SPDIF_OUT

R1599
10K_0402_5%~D

+3.3V_RUN

10U_0805_10V4Z~D@

1

2

U40

1

DVDD_CORE

9

DVDD_CORE

40

DVDD_CORE/VPP

3

DVDD_IO

6

HDA_BIT_CLK

8

HDA_SDI_CODEC

5

HDA_SDO

10

HDA_SYNC

11

HDA_RST#

STAC9205

43

NC1

44

NC2

45

NC3

46

DMIC_CLK

2

VOL_UP/DMIC0/GPIO1

4

VOL_DN/DMIC1/GPIO2

47

SPDIF_ IN//GPIO0/EAPD

48

SPDIF _OUT

7

DVSS

26

AVSS1

42

AVSS2

49

Thermal PAD GND

QFN 7x7 & LQFP 9x9 colay footprint.

STAC9205X5NBEB2XR_QFN48_COMON~D

AVDD1
AVDD2

SENSE_A
SENSE_B

PORT_A_L

PORT_A_R

VREFOUT_A

PORT_B_L

PORT_B_R

VREFOUT_B

PORT_C_L
PORT_C_R

VREFOUT_C

PORT_D_L
PORT_D_R

PORT_E_L

PORT_E_R

VREFOUT_E/GPIO4

PORT_F_L

PORT_F_R

VREFOUT_F/GPIO3

CD_L

CD_GND

CD_R

PC_BEEP

MONO_OUT

CAP2

VREFFILT

25
38

13
34

39
41
37

21
22
28

23
24
29

35
36

14
15
31

16
17
30

18
19
20

12
32

33
27

+VDDA

C1121

AUD_SENSE_A
AUD_SENSE_B

AUD_HP_OUT_L
AUD_HP_OUT_R

AUD_EXT_MIC_L
AUD_EXT_MIC_R

AUD_LINE_OUT_L
AUD_LINE_OUT_R

DOCK_HP_MUTE#

AUD_SPDIF_SHDN

AUD_PC_BEEP

10U_0805_10V4Z~D

C1126

1

2

1

2

VREFOUT

C1127

1U_0603_10V4Z~D

0.1U_0402_16V4Z~D

C1122

1

2

10U_0805_10V4Z~D

1

2

10U_0805_10V4Z~D@

C1123

1

2

AUD_HP_OUT_L <26>
AUD_HP_OUT_R <26>

AUD_EXT_MIC_L <26>
AUD_EXT_MIC_R <26>

AUD_LINE_OUT_L <26>
AUD_LINE_OUT_R <26>

DOCK_HP_MUTE# <35>

AUD_SPDIF_SHDN <19,35>

2N7002W-7-F_SOT323-3~D

C1115

12

0.1U_0402_10V7K~D

AUD_SENSE_A

AUD_SENSE_B

DOCK_HP_MUTE#

AUD_SPDIF_SHDN

12

R928

2.2K_0402_5%~D

39.2K_0402_1%~D

12

R930

13

D

2

G

Q116

S

BEEP2AUD_PC_BEEP BEEP1

R927

10K_0402_5%~D

20K_0402_1%~D

12

R931

13

D

S

R933 10K_0402_5%~D

R934 10K_0402_5%~D

R935 10K_0402_5%~D

12

5.11K_0402_1%~D

C1116

1

2

2

AUD_MIC_SWITCH <26>AUD_HP_N B_SENSE<26,35>

G

Q117
2N7002W-7-F_SOT323-3~D

12

12

12

4

Y

+VDDA

5

3

R929

1000P_0402_50V7K~D

+VDDA

12

+VDDA

TRACE>15 milU39 place as close to CODEC as possible

1

C1114

0.1U_0402_16V4Z~D

2

1

P

B

2

A

G

U39
74AHCT1G86GW_SOT353-5~D

SPKR <22>

BEEP <36>

MDC CONNECTOR

+3.3V_SUS

4.7U_0603_6.3V4Z~D

0.1U_0402_16V4Z~D

C1172

1

1

2

2

2
4
6
8
10
12

C1171

ICH_AZ_MDC_BITCLK

R962

ICH_AZ_MDC_SDOUT<21>

ICH_AZ_MDC_SYNC<21>

R958

D

1 3

2

1 2

33_0402_5%~D

S

G

R961

10K_0402_5%~D

+5V_SUS

12

MDC_SDIN
ICH_RST_MDC_R#

12

R959
100K_0402_5%~D

JMDC

1

GND1

3

IAC_SDATA_OUT

5

GND2

7

IAC_SYNC

9

IAC_SDATA_IN

11

IAC_RESET#

TYCO_1-1734054-2~D

RES0
RES1

3.3V
GND3
GND4

IAC_BITCLK

ICH_AZ_MDC_SDIN1<21>

1 2

0_0402_5%~D@

ICH_AZ_MDC_RST#<21>

BSS138W-7-F_SOT323-3~D

A A

MDC_RST_DIS#<15>

Q120

PWR/GND Minimum Spacing W=20 mil

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

ICH_AZ_MDC_BITCLK
ICH_AZ_MDC_SDOUT

ICH_AZ_MDC_BITCLK <21>

R956

C1165

10_0402_5%~D

10_0402_5%~D@

R957

1 2

1 2

10P_0402_50V8J~D@

AZ_MDC_SDOUT_TERM

10P_0402_50V8J~D

AZ_MDC_BITCLK_TERM

C1166

1

1

2

2

RJ11 CONNECTOR

FBMA-L11-160808-301LMA20T_0603~D
RJ_TIP
RJ_RING

FBMA-L11-160808-301LMA20T_0603~D

RJ_RING
RJ_TIP

L105

1 2
1 2

L106

JWIRE1

1

1

G1

22G2

MOLEX_48227-0201~D

JPHON

1

1

2

2

330P_1808_5KV7K~D@

C1169

C1170

1

2

3
4

3

330P_1808_5KV7K~D@

GND1

4

1

2

GND2

JM34613-L002-TR~D

DELL CONFIDENTIAL/PROPRIETARY

Title

Size Document Number Rev

2

Date: Sheet

Compal Electronics, Inc.
SCHEMATIC, M /B LA-3751P

401490

1

25 48Wednesday, March 28, 2007

A

of

5

4

3

2

1

For MAX9789A, depop R948 and pop R947

+5V_AMPVCC

12

R947

D D

C C

B B

A A

AUDIO_AVDD_ON

AUD_HP_NB_SENSE<25,35>

NB_MUTE#<35>

12

R955

1

C1163

2

AUD_HP_NB_ SENSE
NB_MUTE#

AUD_EAPD

10_0402_5%~D@

10P_0402_50V8J~D@

R948

1 2

0_0402_5%~D

100K_0402_5%~D@

AUD_AMP_MUTE#

C1146 0.033U_1206_50V7K~D

AUD_LINE_OUT_L<25>

AUD_LINE_OUT_R<25>

AUD_HP_OUT_L<25>

AUD_HP_OUT_R<25>

+5V_AMPVCC

5

1

P

IN1

2

IN2

G

3

AUD_EAPD<25>

AUD_EXT_MIC_L<25>

AUD_EXT_MIC_R<25>

12

C1147 0.033U_1206_50V7K~D

12

C1148 1U_1206_25V7K~D

1 2

C1149 1U_1206_25V7K~D

1 2

4

O

U42
74AHC1G08GW_SOT353-5~D

2N7002W-7-F_SOT323-3~D

C1151

AUD_SPK_ENABLE#

NB_MUTE#

R940

5.1_0402_1%~D
1 2

1 2

R941

5.1_0402_1%~D

47P_0402_50V8J~D@

47P_0402_50V8J~D@

C1153

C1152

1

1

2

2

+5V_AMPVCC

+5V_AMPVCC

100K_0402_5%~D

R952

1 2

R953

13

D

2

G

S

Q118

13

D

Q119

2

2N7002W-7-F_SOT323-3~D

G

S

1U_0603_10V6K~D

MIC_L1 MIC_L3

1U_0603_10V6K~D

47P_0402_50V8J~D@

47P_0402_50V8J~D@

C1154

1

1

2

100K_0402_5%~D

12

C1131

C1132

12

12

2

C1156

10U_0805_10V4Z~D

1

2

VREFOUT

MIC_L2

MIC_R2MIC_R1

C1157

C1150 1U_0603_10V4Z~D

1U_0603_10V4Z~D

1

2

12

R938

12

R942

+5V_RUN

1U_0603_10V4Z~D

C1139

1

2

SPKR_INL_C INT_SPK_L1

HP_INL_C

HP_INR_C

12

AUD_SPK_ENABLE#

C1P

1U_0603_10V4Z~D

1M_0402_1%~D

C1158

4.7K_0402_5%~D

12

20K_0402_1%~D@

12

C1N

1

2

2

C1128
10U_0805_10V4Z~D

1

+3.3V_RUN

12

R1600

4.7K_0402_5%~D
R939

20K_0402_1%~D@

R943

AUD_MIC_SWIT CH<25>

L104

1 2

BLM21PG600SN1D_0805~D

0.1U_0402_16V4Z~D

1U_0603_10V4Z~D

C1141

C1140

1

1

2

2

U41

3

SPKR_LIN+

2

SPKR_RIN+

27

HP_INL

26

HP_INR

24

BYPASS

23

/SPKR_EN

22

HP_EN

25

REG_EN

17

HPVDD

9

CPVDD

10

C1P

12

C1N

11

CPGND

CPVSS13HPVSS

14

C1162

12

1U_0603_10V4Z~D

L102

BLM18BD601SN1D_0603~D

BLM18BD601SN1D_0603~D

12

L103

12

R944

1 2

100K_0402_5%~D

C1142

30

8

18

VDD

SPVDD

SPVDD

HP_OUTL

HP_OUTR

SPKR_LIN-

REG_OUT

SPKR_RIN-

SPGND21SPGND

SGND

TP

TPA6040A4RHBR_QFN32_5X5~D

5

28

33

MIC_R3

1U_0603_10V4Z~D

1

2

LOUT+

LOUT-

ROUT+

ROUT-

GAIN0
GAIN1

C1144

1

2

6

7

20

19

16

15

31
32

4

29

1

HP_SPK_L2

HP_SPK_R2

AUD_HP_NB_ SENSE

C1133

2

1

W=60milsPlace close to Audio Chip

+5V_AMPVCC

1U_0603_10V4Z~D

10U_0805_10V4Z~D

C1143

10U_0805_10V4Z~D

C1145

1

1

2

2

INT_SPK_R1
INT_SPK_R2
INT_SPK_L1
INT_SPK_L2

Place close to speaker connector

INT_SPK_L2
INT_SPK_L1
INT_SPK_R2

INT_SPK_L2S P KR_INR_C

INT_SPK_R1

INT_SPK_R2

HP_SPK_L1

HP_SPK_R1

AUD_GAIN1AUD_AMP_MUTE#
AUD_GAIN2

R951 0_0402_5%~D@

1 2

C1155 0.033U_1206_50V7K~D

1 2

R954

For MAX9789A, depop C1155 and pop R951

0.033U_1206_50V7K~D

SET
0_0402_5%~D@

12

C1161

2

1

INT_SPK_R1

15 mil trace

C1159

1

2

For MAX9789A, depop C1161 and pop R954

+3.3V_RUN

100K_0402_5%~D

100P_0402_50V8J~D

C1134

2

1

100P_0402_50V8J~D

R1601

12

JAUDO

7
8

12

9
10
11

1

2

6

3

4

5

FOX_JA8333L-B2P4-7F~D

131415

1U_0603_10V4Z~D

C1160

1

2

JSPK

1

1

2

2

3

3

4

4

MOLEX_53398-0490~D

0.1U_0402_16V4Z~D@
1

1

C1136

C1135

2

2

AUDIO_AVDD_ON <15>

1U_0603_10V4Z~D

+VDDA

Gain Setting for MAX9789

+5V_AMPVCC

100K_0402_5%~D

12

R945

AUD_GAIN1
AUD_GAIN2

0.1U_0402_16V4Z~D@
C1137

0.1U_0402_16V4Z~D@

0.1U_0402_16V4Z~D@
1

1

C1138

2

2

R949

100K_0402_5%~D@

12

GAIN1 GAIN2 AV(inv)

0

100P_0402_50V8J~D

1
0
1

C1130

1

2

10dB

15.6dB

21.6dB

100P_0402_50V8J~D

HP_SPK_R2

0
1
1 26K ohm

*

L100
HP_SPK_L1 HP_SPK_L2
HP_SPK_R1

BLM18BD121SN1D_0603~D

BLM18BD121SN1D_0603~D

12
12

L101

C1129

1

2

R946

R950

100K_0402_5%~D

12

100K_0402_5%~D@

12

INPUT

IMPEDANCE

82K ohm06dB
66K ohm
45K ohm

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, M /B LA-3751P

401490

1

26 48Wednesday, March 28, 2007

A

of

DELL CONFIDENTIAL/PROPRIETARY

5

4

3

2

1

Rear Right USB Port

R1629

0_0402_5%~D

L137

L138

1

1

4

4

1

1

4

4

1 2

R1630

0_0402_5%~D

1 2

DLW21SN121SQ2L_4P~D@

R1631

0_0402_5%~D

1 2

R1632

0_0402_5%~D

1 2

DLW21SN121SQ2L_4P~D@

2

2

3

3

2

2

3

3

USBP0_D+USBP0+

USBP0_D-

USBP1_D+USBP1+

F1

1 2

L0603@
F2

D D

+5V_ALW

C1192

1

2

10U_1206_16V4Z~D@

0.1U_0402_16V4Z~D
C1193

1

2

1 2

5A_125V_R451005.MRL~D@

PJP24

PAD-OPEN 4x4m

SHORT

OC1#
OUT1
OUT2
OC2#

+USB_R_PWR

8
7
6
5

USB_OC0_1# <22>

U44

1

GND

12

USB_BACK_EN#<35>

2

IN

3

EN1#

4

EN2#

TPS2062DR_SO8~D

USBP0+<22>

USBP0-<22>

USBP1+<22>

USBP1-<22>

USBP0-

USBP1- USBP1_D-

+USB_R_PWR

150U_D2_6.3VM~D

1

C1189

+

2

C1190

C1191

0.1U_0402_16V4Z~D

1

2

USBP1_D­USBP1_D+

USBP0_D-

0.1U_0402_16V4Z~D
USBP0_D+

1

2

JUSB_R

A1

A_VCC

A2

A_D-

A3

A_D+

A4

A_GND

B1

B_VCC

B2

B_D-

B3

B_D+

B4

B_GND

9

G1

10

G2

11

G3

12

G4

FOX_UB1112H-8Z4-HT~D

Side USB Port

C C

+5V_ALW

10U_1206_16V4Z~D@

0.1U_0402_16V4Z~D
C1202

C1201

1

1

2

2

B B

Rear Left USB Port

+5V_ALW

0.1U_0402_16V4Z~D

C1197

A A

10U_1206_16V4Z~D@

C1198

1

1

2

2

1 2

1 2

5A_125V_R451005.MRL~D@

PJP26

PAD-OPEN 4x4m

SHORT

F3

1 2

L0603@
F4

1 2

5A_125V_R451005.MRL~D@

PJP25

PAD-OPEN 4x4m

SHORT

USB_BACK_EN#<35>

F5

L0603@
F6

U49

1

GND

OC1#
OUT1
OUT2
OC2#

2
3
4

TPS2062DR_SO8~D

+USB_L_PWR

8
7
6
5

IN
EN1#
EN2#

USBP5­USBP5+
USBP4­USBP4+

12

USB_SIDE_EN#<35>

USBP5-<22>
USBP5+<22>
USBP4-<22>
USBP4+<22>

U46

1

GND

12

2

IN

3

EN1#

4

EN2#

TPS2062DR_SO8~D

+USB_S_PWR

8

OC1#

7

OUT1

6

OUT2

5

OC2#

+USB_L_PWR

USB_OC4_5# <22>

USB_OC8_9# <22>

150U_D2_6.3VM~D

1

C1194

+

2

C1195

C1196

USBP8+<22>

USBP8-<22>

USBP9+<22>

USBP9-<22>

0.1U_0402_16V4Z~D

1

2

USBP5­USBP5+

USBP4-

0.1U_0402_16V4Z~D
USBP4+

1

2

USBP8- USBP8_D-

USBP9- USBP9_D-

JUSB_L

A1

A_VCC

A2

A_D-

A3

A_D+

A4

A_GND

B1

B_VCC

B2

B_D-

B3

B_D+

B4

B_GND

9

G1

10

G2

11

G3

12

G4

FOX_UB1112H-8Z4-HT~D

R1633

0_0402_5%~D

1 2

R1634

0_0402_5%~D

L139

L140

1

1

4

4

1

1

4

4

1 2

DLW21SN121SQ2L_4P~D@

R1635

0_0402_5%~D

1 2

R1636

0_0402_5%~D

1 2

DLW21SN121SQ2L_4P~D@

2

2

3

3

2

2

3

3

USBP8_D+USBP8+

USBP9_D+USBP9+

Place U45, U47, U48 as close as USB connector

USBP0+

USBP1-

USBP5+

USBP4-

USBP8+

USBP9-

U45

1

D2+

D1+

2

VCC

GND

3

D1-

D2-

IP4220CZ6_SO6~D@

U47

1

D2+

D1+

2

VCC

GND

3

D1-

D2-

IP4220CZ6_SO6~D@

U48

1

D2+

D1+

2

VCC

GND

3

D1-

D2-

IP4220CZ6_SO6~D@

+USB_R_PWR

4
5
6

+USB_L_PWR

4
5
6

+USB_S_PWR

4
5
6

+USB_S_PWR

USBP1+

USBP0-

USBP4+

USBP5-

USBP9+

USBP8-

150U_D2_6.3VM~D

1

C1199

+

2

USB PORT#

0.1U_0402_16V4Z~D

C1200

1

2

USBP8_D­USBP8_D+

USBP9_D-

0.1U_0402_16V4Z~D

C1203

USBP9_D+

1

2

JUSB_S

8

8

7

7

6

6

5

5

10

10

9

9

4

4

3

3

2

2

1

1

JST_SM8B-SRSS~D

DESTINATION

0

1

4

5

8

9

JUSB_R (Rear Right Bottom)

JUSB_R (Rear Right Top)

JUSB_L (Rear Left Bottom)

JUSB_L (Rea r Left Top)

JUSB_S (Side Bottom)

JUSB_S (Side Top)

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, M /B LA-3751P

401490

27 48Wednesday, March 28, 2007

1

A

of

5

4

3

2

1

+1.2V_LAN Regu l a rtor Control +2.5V_LAN Regu l a rtor Control

4.7U_0603_6.3V4Z~D

0.1U_0402_16V4Z~D

+3.3V_LAN SOURCE

2_1210_5%~D

2_1210_5%~D

12

12

C1208

C1231

1

2

+1.2V_LAN

10U_0805_10V4Z~D

1

2

+3.3V_ALW

0.1U_0402_16V4Z~D

D D

4.7U_0603_6.3V4Z~D
C1207

C1206

2

2

1

1

Q125

SI3456BDV-T1-E3_TSOP6~D

D

6

S

45
2
1

G

3

+3.3V_LAN

ENAB_3VLAN <38>

REGCTL_PNP12

C1226

R973

R974

Q127

1

PBSS5540Z_SOT223-3~D

0.047U_0402_16V4Z~D@

1

2 3

4

C1230

0.1U_0402_16V4Z~D

1

2

2

+3.3V_LAN

3

0.047U_0402_16V4Z~D@

C1204

41

Q126
MBT35200MT2G_TSOP6~D

256

C1227

1

C1209

2

REGCTL_PNP25

C1224

1

2

4.7U_0603_6.3V4Z~D

0.1U_0402_16V4Z~D

+3.3V_LAN

C1205

1

1

2

2

+2.5V_LAN

0.1U_0402_16V4Z~D

10U_0805_10V4Z~D

1

1

C1228

2

2

Place close to pin G7

CLK_PCI_TPM

12

R975

33_0402_5%~D@

C C

B B

A A

1

C1232

22P_0402_50V8J~D@

2

4.7K_0402_5%~D

Drive level should be
at least 300uW Max. power

5

R977

LOM_TPM_EN#<35>

LOM_SMB_ALERT#<22,36>

LOM_LOW_PWR<35>

LOM_SUPER_IDDQ<35>

R979 10K_0402_5%~D@
R981 10K_0402_5%~D@
R982 10K_0402_5%~D@

+3.3V_LAN

LOM_LOW_PWR

12

+3.3V_RUN

+3.3V_LAN

LOM_SPD10LED_GRN#<29>

LOM_SPD100LED_ORG#<29>

LOM_ACTLED_YEL#<29>

DOCK_SPD10LED_GRN#<34>
DOCK_SPD100LED_ORG#<34>

DOCK_ACTLED_YEL#<34>

+3.3V_LAN

C1246

2

1

CLK_PCI_TPM<6>

LPC_LAD[0..3]<21,35,36>

LPC_LFRAME#<21,35,36>
PLTRST3#<20,31>
IRQ_SERIRQ<22,30,35,36>

12
12
12

R984 0_0402_5%~D
R987 4.7K_0402_5%~D@

LOM_SMB_ALERT#

R976 4.7K_0402_5%~D
R988 1K_0402_5%~D

R978 0_0402_5%~D@
R983 1K_0402_5%~D
R985 1K_0402_5%~D
R980 20K_0402_5%~D

R986 39K_0402_5%~D

R999 4.7K_0402_5%~D@
R1001 0_0402_5%~D@
R1646 4.7K_0402_5%~D@
R1002 4.7K_0402_5%~D@

200_0402_1%~D

27P_0402_50V8J~D

25MHZ_18PF_1BX25000CK1D~D

12
12

1 2

ICH_SMBCLK<22,31,32>
ICH_SMBDATA<22,31,32>

1 2
1 2
1 2
1 2

1 2

LOM_SPD10LED_GRN#
LOM_SPD100LED_ORG#

LOM_ACTLED_YEL#
DOCK_SPD10LED_GRN#

DOCK_SPD100LED_ORG#
DOCK_ACTLED_YEL#

12
12
12
12

R1000

12

1 2

Y2

CLK_PCI_TPM
LPC_LAD0

LPC_LAD1
LPC_LAD2
LPC_LAD3

LPC_LFRAME#
PLTRST3#
IRQ_SERIRQ

TPM_GPIO0
TPM_GPIO1
TPM_GPIO2

12

C1247

2

1

XTALO

XTALI

27P_0402_50V8J~D

G7

K8
H7

J9

H9

K10

K7
K9

J8
J7

H8
K1

M7

L7
B4

D7
B6

H1

G10

A5

J10

A7
B7
C7
C6

D2
D1
C2
E2

B5
F2
C4
E1
B2

E9
H2
K2

M8

L8

4

U50A

LCLK
LAD0

LAD1
LAD2
LAD3

LFRAME#
LRESET#
SERIRQ

TPM_GPIO0
TPM_GPIO1
TPM_GPIO2/TPM_STATUS

TPM_EN#

GPIO0
GPIO1
GPIO2

SMB_CLK
SMB_DATA

LOW_PWR
VMAINPRSNT
VAUXPRSNT
Super_LOW_PWR

NB_LINKLED#
NB_SPD100LED#
NB_SPD1000LED#
NB_TRAFFICLED#

DK_LINKLED#
DK_SPD100LED#
DK_SPD1000LED#
DK_TRAFFICLED#

TCK
TDI
TDO
TMS
TRST#

GPHY_TVCOI
SERIAL_DI
SERIAL_DO

XTALO

XTALI

BCM5756MKFBG_FBGA144~D

BCM5756M

TPM

GPIO

SMBUS

Power
Control

TESTLED

Clock

NB_TRD0+

NB_TRD0-

NB_TRD1+

NB_TRD1-

NB_TRD2+

NB_TRD2-

NB_TRD3+

NB_TRD3-

DK_TRD0+

DK_TRD0-

DK_TRD1+

Media

DK_TRD1-

DK_TRD2+

DK_TRD2-

DK_TRD3+

DK_TRD3-

E_Switch_Control

EnergyDet

PCIE_TXDP
PCIE_TXDN
PCIE_RXDP
PCIE_RXDN

REFCLK+
REFCLK-

PCI-E

REFCLK_SEL

PERST#

CLKREQ#

REGSUP12
REGCTL12
REGSEN12
REGSUP25
REGCTL25
REGSEN25

RegulatorS

SPI

NV_STRAP0
NV_STRAP1

NB_RDAC
DK_RDAC

Bias

WAKE#

SCLK

CS#

D11
D12
C11
C12
B11
B12
A11
A12

G11
G12
H11
H12
J11
J12
K11
K12

E3
B3

M2
L2
M6
L6
A4
M4

L4
A2
A1
B1

M10
L10
L11
L12
M11
M12

A8
C8

SI

B8

SO

B9
J1

L1

E12
F12

LOM_TX0+
LOM_TX0­LOM_TX1+
LOM_TX1­LOM_TX2+
LOM_TX2­LOM_TX3+
LOM_TX3-

DOCK_LOM_TX0+
DOCK_LOM_TX0­DOCK_LOM_TX1+
DOCK_LOM_TX1­DOCK_LOM_TX2+
DOCK_LOM_TX2­DOCK_LOM_TX3+
DOCK_LOM_TX3-

DOCKED

PCIE_IRX_LANTX_P6_C
PCIE_IRX_LANTX_N6_C

PCIE_WAKE#
CLK_PCIE_LOM

CLK_PCIE_LOM#

R992 4.7K_0402_5%~D@

1 2

+3.3V_LAN

REGCTL_PNP12

+1.2V_LAN
+3.3V_LAN

REGCTL_PNP25

+2.5V_LAN

LOM_SCLK
LOM_SI
LOM_SO
LOM_CS#

NV_STRAP0

1.24K_0402_1%~D
R1003

R1275

1 2

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

LOM_TX 0 + <29>
LOM_TX0- <29>
LOM_TX 1 + <29>
LOM_TX1- <29>
LOM_TX 2 + <29>
LOM_TX2- <29>
LOM_TX 3 + <29>
LOM_TX3- <29>

DOCK_LOM_TX0+ <34>
DOCK_LOM_TX0- <34>
DOCK_LOM_TX1+ <34>
DOCK_LOM_TX1- <34>
DOCK_LOM_TX2+ <34>
DOCK_LOM_TX2- <34>
DOCK_LOM_TX3+ <34>
DOCK_LOM_TX3- <34>

DOCKED <34,35>

LOM_CABLE_DETECT <35>

C1242

0.1U_0402_10V7K~D
1 2

1 2

C1243

0.1U_0402_10V7K~D

PCIE_WAKE# <31,32,35>
CLK_PCIE_LOM <6>

CLK_PCIE_LOM# <6>

R993 0_0402_5%~D@

1 2

R994 0_0402_5%~D

1 2

R991 0_0402_5%~D

1 2

+3.3V_LAN

R990

12

4.7K_0402_5%~D@

1.24K_0402_1%~D

1 2

3

PCIE_IRX_LANTX_P6 <22>
PCIE_IRX_LANTX_N6 <22>
PCIE_ITX_LANRX_P6_C <22>
PCIE_ITX_LANRX_N6_C <22>

SB_LOM_PCIE_RST# <20>

PLTRST3# <20,31>
LOM_CLKREQ# <6>

LOM_CABLE_DETECT goes to an input on a system microcontroller that can poll this
signal periodically and can de-assert the LOM_LOW_PWR when LOM_CABLE_DETECT
signal is hig h. Con ne c t t o a n E C G PIOC defined by the GPIO mapping

+3.3V_LAN

R995

U51

8

Q

7

VSS

6

VCC

5

W#

M45PE20-VMN6TP_SO8~D
U52

8

SO

7

GND

6

VCC

5

WP#

D
C

RESET#

S#

SI

SCK

RESET#

CS#

AT45BCM021B-SU_SO8~D@

1
2
3
4

1
2
3
4

LOM_SI

+3.3V_LAN

2

C1248

0.1U_0402_16V4Z~D

1

NV_STRAP1 NV_STRAP0 SO CS#SI

Auto-Sense Mode

(Default) 0 0 0 0 0

Atmel AT45BCM021B

ST M45PE20

0

00011

00011 1

DELL CONFIDENTIAL/PROPRIETARY

Title

Size Document Number Rev

2

Date: Sheet

Compal Electronics, Inc.
SCHEMATIC, M /B LA-3751P

401490

4.7K_0402_5%~D@

12

R996

4.7K_0402_5%~D@

4.7K_0402_5%~D@
12

12

R997

LOM_SO

LOM_SCLK

LOM_CS#

SCLK

1

28 48Wednesday, March 28, 2007

1

A

of

5

4

3

2

1

Place as close as U50 as possible

+1.2V_LAN

0.1U_0402_16V4Z~D

4.7U_0603_6.3V4Z~D@

D D

C1210

0.1U_0402_16V4Z~D

C1211

C1212

1

2

2

1

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D
C1213

C1214

2

2

1

1

0.1U_0402_16V4Z~D
C1216

C1215

2

2

1

1

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D
C1218

C1217

2

2

2

1

1

1

0_0402_5%~D

0.1U_0402_16V4Z~D

C1256

1

2

2

R1005

0.1U_0402_16V4Z~D

+3.3V_LAN

12

150_0402_5%~D

1 2
1 2

150_0402_5%~D

12

R1006
150_0402_5%~D

JLOM

13

YELLOW

14

COMMON0

11

TRD1P

12

TRCT1

10

TRD1N

4

TRD2P

6

TRCT2

5

TRD2N

3

TRD3P

1

TRCT3

2

TRD3N

8

TRD4P

7

TRCT4

9

TRD4N

16

R1638

R1639

LOM_ACTLED_YEL#
LOM_SPD10LED_GRN#
LOM_SPD100LED_ORG#

COMMON1

17

GREEN

15

ORANGE

TYCO_1368398-2~D

1CT:1CT

1CT:1CT

1CT:1CT

1CT:1CT

4 X 75 OHMS

1000pF 2KV

SHIELD018SHIELD1

+3.3V_LAN

10K_0402_5%~D@

10K_0402_5%~D@

12

R1019

R1018

10K_0402_5%~D@

12

12

R1020

TRP1P

TRP1N

TRP2P

TRP2N

TRP3P

TRP3N

TRP4P

TRP4N

19

DELL CONFIDENTIAL/PROPRIETARY

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, M/B LA-3751P

401490

1

29 48Wednesday, March 28, 2007

of

A

+2.5V_LAN

L142
BLM18AG601SN1D_0603~D

+2.5V_LAN

0.1U_0402_16V4Z~D

1

1

C1234

C1235

2

2

C C

+2.5V_LAN

B B

+1.2V_LAN

A A

L109

BLM18AG601SN1D_0603~D

L110

BLM18AG601SN1D_0603~D

L111

BLM21AG601SN1D_0805~D

L141

BLM18AG601SN1D_0603~D

4.7U_0603_6.3V4Z~D@

L112

BLM18AG601SN1D_0603~D

4.7U_0603_6.3V4Z~D

L114

BLM18AG601SN1D_0603~D

4.7U_0603_6.3V4Z~D

L113

BLM18AG601SN1D_0603~D

4.7U_0603_6.3V4Z~D

+3.3V_LAN

0.1U_0402_16V4Z~D

12

12

12

12

12

12

12

5

C1244

C1236

C1240

C1238

4.7U_0603_6.3V4Z~D
C1220

C1219

2

1

+XTALVDD

1

C1225

0.1U_0402_16V4Z~D

2

+BIASVDD

1

C1229

0.1U_0402_16V4Z~D

2

+AVDD

1

C1233

0.1U_0402_16V4Z~D

2

1

1

2

2

1

1

2

2

1

1

2

2

1

1

2

2

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D
C1221

2

2

1

1

+PCIE_SDSVDD

C1245

0.1U_0402_16V4Z~D@

+AVDDL

C1237

0.1U_0402_16V4Z~D

+PCIE_PLLVDD

C1241

0.1U_0402_16V4Z~D

+GPHY_PLLVDD

C1239

0.1U_0402_16V4Z~D

C1222

0.1U_0402_16V4Z~D

2

1

+PCIE_SDSVDD

+PCIE_PLLVDD

+GPHY_PLLVDD

+3.3V_LAN

+2.5V_LAN

+XTALVDD

+BIASVDD

+AVDD

+AVDDL

4

+1.2V_LAN

U50B

D3

VDDC_0

D6

VDDC_1

E4

VDDC_2

G8

VDDC_3

H3

VDDC_4

J3

VDDC_5

J6

VDDC_6

K3

VDDC_7

A6

VDDIO_0

A10

VDDIO_1

C1

VDDIO_2

F10

VDDIO_3

G1

VDDIO_4

J2

VDDIO_5

M1

VDDIO_6

C3

VDDP_0

F3

VDDP_1

H10

VDDP_2

K6

XTALVDD

M3

PCIE_SDSVDD

E11

BIASVDD

BIAS

C9
D9

E10
B10

C10
D10

K4

F11

POWER

AVDD_0
AVDD_1
AVDD_2

AVDDL_0
AVDDL_1
AVDDL_2

PCIE_PLLVDD

PLL

GPHY_PLLVDD

BCM5756MKFBG_FBGA144~D

BCM5756

Digial POWER

GND

Analog

VSS_0
VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8

VSS_9
VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25

NC_0
NC_1
NC_2
NC_3
NC_4
NC_5
NC_6
NC_7

A3
A9
C5
D4
D8
E5
E6
E7
E8
F4
F5
F6
F7
F8
F9
G3
G4
G5
G6
G9
H4
J4
K5
L3
L5
M5

M9
L9
J5
H6
H5
G2
F1
D5

LOM_ACTLED_YEL#<28>

LOM_TX0+<28>

LOM_TX0-<28>
LOM_TX1+<28>

LOM_TX1-<28>
LOM_TX2+<28>

LOM_TX2-<28>
LOM_TX3+<28>

LOM_TX3-<28>

LOM_SPD10LED_GRN#<28>
LOM_SPD100LED_ORG#<28>

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

LOM_ACTLED_YEL#

LOM_TX0+

LOM_TX0­LOM_TX1+

LOM_TX1­LOM_TX2+

LOM_TX2­LOM_TX3+

LOM_TX3-

1 2

+2.5V_LAN_CT

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

C1253

Place these caps as close
to the center tap pins
of the mag/connector

C1254

C1255

1

1

1

2

2

2

5

PCI_AD[0..31]<20,33>

+3.3V_R5C833

100K_0402_5%~D

D D

CLK_PCI_R5C832

R1028

C1277

PCI_AD17

CLKRUN#<22,35,36>

PCI_PIRQD#<20>

PCI_PIRQC#<20>

+3.3V_R5C833

1 2

0_0402_5%~D@

R1035 0_0402_5%~D@

CBUS_GRST#<35>

@

10_0402_5%~D

12

10P_0402_50V8J~D@

1

2

C C

CB_HWSPND#<35>

B B

R1025

R1026

C1273

1 2

CLK_PCI_R5C832<6>

R1031 0_0402_5%~D

1 2

SYS_PME#<33,35>

1 2

R1039

1 2

10K_0402_5%~D

12

1U_0603_10V4Z~D

1

2

PCI_C_BE3#<20,33>
PCI_C_BE2#<20,33>
PCI_C_BE1#<20,33>
PCI_C_BE0#<20,33>

PCI_PAR<20,33>
PCI_FRAME#<20,33,34>
PCI_TRDY#<20,33>
PCI_IRDY#<20,33,34>
PCI_STOP#<20,33>
PCI_DEVSEL#<20,33>

PCI_PERR#<20,33>
PCI_SERR#<20,33>

PCI_REQ1#<20>

PCI_GNT1#<20>

BUS_GRST#

PCI_RST#<20,32,33>

R1029100_0402_5%~D

R1032

1 2

0_0402_5%~D@

PCI_AD31
PCI_AD30
PCI_AD29
PCI_AD28
PCI_AD27
PCI_AD26
PCI_AD25
PCI_AD24
PCI_AD23
PCI_AD22
PCI_AD21
PCI_AD20
PCI_AD19
PCI_AD18
PCI_AD17
PCI_AD16
PCI_AD15
PCI_AD14
PCI_AD13
PCI_AD12
PCI_AD11
PCI_AD10
PCI_AD9
PCI_AD8
PCI_AD7
PCI_AD6
PCI_AD5
PCI_AD4
PCI_AD3
PCI_AD2
PCI_AD1
PCI_AD0

PCI_C_BE3#
PCI_C_BE2#
PCI_C_BE1#
PCI_C_BE0#

PCI_PAR
PCI_FRAME#
PCI_TRDY#
PCI_IRDY#
PCI_STOP#
PCI_DEVSEL#

PCI_IDSEL

PCI_PERR#
PCI_SERR#

PCI_REQ1#
PCI_GNT1#

PCI_RST#
BUS_GRST#

100K_0402_5%~D

R1041

1 2

Layout Note: Place close to R5C832 Chip

TPBIAS0

TPA0+

TPA0­TPB0+

TPB0-

A A

R1047

R1053

C1289

56.2_0603_1%~D

12

R1048

56.2_0603_1%~D

12

R1054

270P_0402_50V7K~D

R1057

2

1

0.01U_0402_16V7K~D

56.2_0603_1%~D

12

C1286

C1287

1

2

56.2_0603_1%~D

12

5.1K_0603_1%~D

1 2

5

Layout Note: Place close to 1394 connector

0.33U_0603_10V7K~D

1

2

U54

125

AD31

126

AD30

127

AD29

1

AD28

2

AD27

3

AD26

5

AD25

6

AD24

9

AD23

11

AD22

12

AD21

14

AD20

15

AD19

17

AD18

18

AD17

19

AD16

36

AD15

37

AD14

38

AD13

39

AD12

40

AD11

42

AD10

43

AD9

44

AD8

46

AD7

47

AD6

48

AD5

49

AD4

50

AD3

51

AD2

52

AD1

53

AD0

7

C/BE3#

21

C/BE2#

35

C/BE1#

45

C/BE0#

33

PAR

23

FRAME#

25

TRDY#

24

IRDY#

29

STOP#

26

DEVSEL#

8

IDSEL

30

PERR#

31

SERR#

124

REQ#

123

GNT#

121

PCICLK

119

PCIRST#

71

GBRST#

117

CLKRUN#

70

PME#

115

INTA#

116

INTB#

69

HWSPND#

66

TEST

99

AGND

102

AGND

103

AGND

107

AGND

111

AGND

97

RSV

R5C833-TQFP128P_TQFP128_14X14~D

L124 DLW21SN121SQ2L_4P~D@

1

1

4

4

1

1

4

4

L125 DLW21SN121SQ2L_4P~D@

R1049

0_0402_5%~D

1 2

R1050

0_0402_5%~D

1 2

R1055

0_0402_5%~D

1 2

R1056

0_0402_5%~D

1 2

R5C833

2

3
2

3

4

10

VCC_PCI3V

20

VCC_PCI3V

27

VCC_PCI3V

32

VCC_PCI3V

41

VCC_PCI3V

128

VCC_PCI3V

61

VCC_RIN

VCC_ROUT
VCC_ROUT
VCC_ROUT
VCC_ROUT
VCC_ROUT

VCC_3V

VCC_MD3V

AVCC_PHY3V
AVCC_PHY3V
AVCC_PHY3V
AVCC_PHY3V

TPBIAS0

TPAP0
TPAN0

TPBP0
TPBN0

MDIO00
MDIO01
MDIO02
MDIO03
MDIO04
MDIO05
MDIO06
MDIO07
MDIO08
MDIO09
MDIO10
MDIO11
MDIO12
MDIO13
MDIO14
MDIO15
MDIO16
MDIO17
MDIO18
MDIO19

MSEN
XDEN

XI

XO

FIL0
REXT
VREF

UDIO0/SRIRQ#

UDIO1
UDIO2
UDIO3
UDIO4
UDIO5

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

TPA0_D+

2

TPA0_D-

3

TPB0_D+

2

TPB0_D-

3

+3.3V_R5C833

CARD_EN

4

+VCC_ROUT
16
34

64
114
120

67
86

+3.3V_RUN_PHY

98
106
110
112

TPBIAS0

113

TPA0+

109

TPA0-

108

TPB0+

105

TPB0-

104

SDCD#_XDCD0#

80

MSCD#_XDCD1

79

XD_CE#

78

SDWP#_XDRB#

77

CARD_EN

76

XDWP#

75

TP_SD/MMC/MS/XD_LED#

74
73

SDCMD_MSBS_XDWE#

88

SDCLK_MSCLK_XDRE#

84

SDDATA0_MSDATA0_XDD0

82

SDDATA1_MSDATA1_XDD1

81

SDDATA2_MSDATA2_XDD2

93

SDDATA3_MSDATA3_XDD3

90

XDD4

91

XDD5

89

XDD6

92

XDD7

87

XDCLE

85

XDALE

83
58

55
94

95
96

101
100

72
60
56
65

UDIO4

59

UDIO5

57
4

13
22
28
54
62
63
68
118
122

J1394

4

5

4

G1

3

3

2

2

1

6

1

G2

TYCO_1775260-1~D

U55

5

IN

4

EN

G5240B1T1U_SOT23-5~D

1

C1291

0.1U_0402_16V4Z~D

2

+3.3V_R5C833

C1267

0.01U_0402_16V7K~D

1

2

R5C832XI
R5C832XO

IRQ_SERIRQ <22,28,35,36>

10K_0402_5%~D

100K_0402_5%~D

MSCD#_XDCD1

OUT

GND

N.C.

C1263

C1268

10U_0805_6.3V6M~D

1

2

1 2

R1036

1 2
1 2

R1038

RB751V_SOD323-2~D

RB751V_SOD323-2~D

RB751V_SOD323-2~D

R1046 0_0402_5%~D@

+3.3V_RUN_CARD

1
2
3

C1290

0.01U_0402_16V7K~D
C1264

1

2

Place close to J5IN1

+3.3V_RUN_CARD

C1274

T94

C12820.01U_0402_16V7K~D

+3.3V_R5C833

D33

2 1

D34

2 1

D35
2 1
1 2

XD_SW#
SDWP#_XDRB#
SDCLK_MSCLK_XDRE#
XD_CE#
XDCLE
XDALE
SDCMD_MSBS_XDWE#
XDWP#
SDDATA0_MSDATA0_XDD0
SDDATA1_MSDATA1_XDD1
SDDATA2_MSDATA2_XDD2
SDDATA3_MSDATA3_XDD3
XDD4
XDD5
XDD6
XDD7

+3.3V_RUN_XD

1U_0603_10V4Z~D

1

2

3

+3.3V_R5C833

0.1U_0402_16V4Z~D

0.01U_0402_16V7K~D
C1266

C1265

1

1

2

2

0.01U_0402_16V7K~D

0.01U_0402_16V7K~D

C1275

C1276

1

1

2

2

Layout Note:
Place C1282,C1284,R1034 close to R5C832

0.01U_0402_16V7K~D

C1284

2

1

XD_CDSW#SDCD#_XDCD0#

MS_INS#

C1288

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

0.01U_0402_16V7K~D

10U_0805_6.3V6M~D

C1257

C1258

1

1

2

2

150K_0402_5%~D

0.01U_0402_16V7K~D

R1027

1

2

10K_0402_1%~D

R1034

1 2

13

D

2

G

S

2
3
4
5
6
7
8

9
11
12
13
14
15
16
17
18

19

2.2U_0603_6.3V6K~D

1

2

1
10

42
43
44

0.01U_0402_16V7K~D

0.01U_0402_16V7K~D

C1259

C1260

1

1

2

2

+3.3V_R5C833

BLM21AG601SN1D_0805~D

C1283

22P_0402_50V8J~D

1 2

1 2

C1285

22P_0402_50V8J~D

2N7002W-7-F_SOT323-3~D

12

Q132

0_0402_5%~D@

R1045

J5IN1

MOLEX_480001002~D

XD1_CD
XD2_R/B#
XD3_RE#
XD4_CE#
XD5_CLE
XD6_ALE
XD7_WE#
XD8_WP#
XD10_D0
XD11_D1
XD12_D2
XD13_D3
XD14_D4
XD15_D5
XD16_D6
XD17_D7

XD18_VCC
XD0_GND

XD9_GND
GND0

GND1
GND2

4 IN 1 CONN

+3.3V_R5C833

0.01U_0402_16V7K~D

0.01U_0402_16V7K~D

C1261

C1262

1

1

2

2

+VCC_ROUT

L123

1 2

Layout Note: Place close to
R5C832 and Shield GND

X2

24.576MHz_16P_1BG24576CKIA~D

1 2

R1043

10K_0402_5%~D

12
12

R1044

10K_0402_5%~D

MS4_DATA0
MS3_DATA1

xD Card

Interface

MS5_DATA2
MS7_DATA3

MS8_SCLK

MS Card

MS10_VSS

Interface

SD7_DAT0
SD8_DAT1
SD9_DAT2

SD1_CD/DAT3

SD_SW/WP

SD Card

Interface

10U_0805_6.3V6M~D

1

2

C1269

1

2

C1278

1

2

1 2

220_0402_5%~D

MS2_BS

MS6_INS

MS9_VCC

MS1_VSS

SD5_CLK

SD2_CMD

SD_SW
SD4_VDD
SD3_VSS

SD6_VSS

SD_GND

+3.3V_R5C833

0.01U_0402_16V7K~D

0.01U_0402_16V7K~D

C1270

1

2

0.01U_0402_16V7K~D

10U_0805_6.3V6M~D

C1279

1

2

R5C832XI

R5C832XO

R1040

+3.3V_R5C833

+3.3V_RUN_CARD

23
22
24
26
27
21
25
28
20
29

36
37
38
30

34
31
40
41
33

32
35
39

2

R1024

1 2

0_0805_5%~D

0.47U_0402_10V4Z~D

C1271

C1272

1

2

+3.3V_RUN_PHY

0.1U_0402_16V4Z~D

C1281

C1280

1

2

SDDATA0_MSDATA0_XDD0
SDDATA1_MSDATA1_XDD1
SDDATA2_MSDATA2_XDD2
SDDATA3_MSDATA3_XDD3

SDCMD_MSBS_XDWE#
MS_INS#

SDDATA0_MSDATA0_XDD0
SDDATA1
SDDATA2
SDDATA3_MSDATA3_XDD3

SDCMD_MSBS_XDWE#
SDCD#_XDCD0#
SDWP#_XDRB#

2

+3.3V_RUN

0.47U_0402_10V4Z~D

1

2

1000P_0402_50V7K~D

1

2

Function set pin define

SDDATA1_MSDATA1_XDD1

SDDATA2_MSDATA2_XDD2

+15V_ALW

SDCD#_XDCD0#

1

SD,MMC,MS,XD muti-function pin define

Media I/F

SD Card
MDIO00 SDCD#
MDIO01

MMC Card
MMCCD#

MS Card

MSCD#
MDIO02
MDIO03
MDIO04
MDIO05
MDIO06
MDIO07
MDIO08
MDIO09
MDIO10
MDIO11
MDIO12
MDIO13

SDWP#
SDPWR0
SDPWR1
SDLED#
SDEXTCK
SDCCMD
SDCCLK
SDCDAT0
SDCDAT1
SDCDAT2
SDCDAT3

MMCPWR

MMCLED#

MMCCMD
MMCCLK
MMCDAT

MSWR

MSLED#

MSEXTCK

MSBS

MSCCLK

MSCDAT0

MSCDAT1

MSCDAT2

MSCDAT3
MDIO14
MDIO15
MDIO16
MDIO17
MDIO18
MDIO19

MSEN

Function
Enable

SD,XD,MS,MMC Card

Pull-up

UDIO4UDIO3 XDEN

Pull-up Pull-up Pull-up

Solve MS Duo Adaptor short problem

R1030 0_0402_5%~D@

1 2

Q128

D

S

2N7002W-7-F_SOT323-3~D

1 3

R1033 0_0402_5%~D@

1 2

G

+3.3V_RUN_CARD

R1042

1 2

10K_0402_5%~D

R1051

0_0402_5%~D

1 2

R1052

0_0402_5%~D

2

13

D

2

G

Q131

S

2N7002W-7-F_SOT323-3~D

SDCLK_MSCLK_XDRE#MSCLK

SDCLK_MSCLK_XDRE#SDCLK

12

Q129

D

S

2N7002W-7-F_SOT323-3~D

1 3

1 2

R1037 0_0805_5%~D@

G

2

S

G

2

XD_CDSW#

Note: If countermeasure
circuit is needed, please
populate D35,R1042~R1044
,Q128-Q132 and
no-stuff R1045,R1046,R1030
,R1033,R1037. If
countermeasurecircuit is
NOT needed,please no-stuff
D35,R1042~R1044,Q128-Q132
and stuff R1045,R1046,R1030
,R1033,R1037.

D

13

Q130

SI2303BDS-T1-E3_SOT23-3~D

DELL CONFIDENTIAL/PROPRIETARY

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.
SCHEMATIC, M /B LA-3751P

401490

1

30 48Wednesday, March 28, 2007

XD Card
XDCD0#
XDCD1#
XDCE#
XDR/B#
XDPWR
XDWP#
XDLED#

XDWE#

XDRE#
XDCDAT0
XDCDAT1
XDCDAT2
XDCDAT3
XDCDAT4
XDCDAT5
XDCDAT6
XDCDAT7

XDCLE

XDALE

SDDATA1

SDDATA2

+3.3V_RUN_XD

A

of

5

4

3

2

1

Mini Card 1---Robson

+3.3V_RUN+3.3V_RUN

JMINI1

PCIE_WAKE#<28,32,35>

D D

PCIE_MCARD2_DET#<20>

C C

MINI1_CLKREQ#<6>

CLK_PCIE_MINI1#<6>
CLK_PCIE_MINI1<6>

PCIE_IRX_ROBSONTX_N1<22>
PCIE_IRX_ROBSONTX_P1<22>

PCIE_ITX_ROBSONRX_N1_C<22>
PCIE_ITX_ROBSONRX_P1_C<22>

R1609 0_0402_5%~D

1 2

+3.3V_RUN

1 2

100K_0402_5%~D

R1067

1

1

3

3

5

5

7

7

9

9

11

11

13

13

15

15

17

17

19

19

21

21

23

23

25

25

27

27

29

29

31

31

33

33

35

35

37

37

39

39

41

41

43

43

45

45

47

47

49

49

51

51

53

GND1

TYCO_1775838-1~D

GND2

+1.5V_RUN

2

2

4

4

6

6

8

8

10

10

12

12

14

14

16

16

18

18

20

20

22

22

24

24

26

26

28

28

30

30

32

32

34

34

36

36

38

38

40

40

42

42

44

44

46

46

48

48

50

50

52

52

54

ROBSON_PLTRST3#_R

RBSON_SCLK
RBSON_SDATA

T96

ROBSON_RADIO_DIS# <35>

R1065 0_0402_5%~D
R1059 0_0402_5%~D@

R1643 0_0402_5%~D@

1 2

R1644 0_0402_5%~D@

1 2

R1610

1 2

0_0402_5%~D

R1068

12

100K_0402_5%~D

12
12

USB_MCARD2_DET# <22>

+3.3V_RUN

PLTRST3# <20,28>

SB_ROBSON_PCIE_RST# <20>

MEM_SCLK <16,17,22>
MEM_SDATA <16,17,22>

+1.5V_RUN

C1299

33P_0402_50V8J~D

+3.3V_RUN

33P_0402_50V8J~D

C1298

1

1

C1300

2

2

0.047U_0402_16V4Z~D

33P_0402_50V8J~D

C1294

C1296

1

1

2

2

0.047U_0402_16V4Z~D

0.047U_0402_16V4Z~D

C1295

C1297

1

1

2

2

330U_D2E_6.3VM_R25~D

22U_0805_6.3V6M~D

1

C1293

1

+

2

2

Mini Card 2---WLAN

+1.5V_RUN

C1302

1

2

B B

A A

COEX2_WLAN_ACTIVE<32>

PCIE_MCARD1_DET#<22>

0.047U_0402_16V4Z~D

COEX1_BT_ACTIVE<32>

+3.3V_WLAN

0.047U_0402_16V4Z~D

C1303

C1305

1

2

PCIE_WAKE#<28,32,35>

1

2

PCIE_IRX_WLANTX_N2<22>
PCIE_IRX_WLANTX_P2<22>

PCIE_ITX_WLANRX_N2_C<22>
PCIE_ITX_WLANRX_P2_C<22>

R1611 0_0402_5%~D

1 2

+3.3V_RUN

0.047U_0402_16V4Z~D

0.047U_0402_16V4Z~D

C1306

C1304

1

2

R1069 0_0402_5%~D

1 2

R1070 0_0402_5%~D

1 2

MINI2_CLKREQ#<6>
CLK_PCIE_MINI2#<6>

CLK_PCIE_MINI2<6>
HOST_DEBUG_RX<36>

8051_TX<36>

0.1U_0402_16V4Z~D@
C1307

1

1

2

2

R1073

1 2

100K_0402_5%~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

C1308

1

2

+3.3V_WLAN

4.7U_0603_6.3V4Z~D

C1309

1

2

1
3
5
7

9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51

53

330U_D2E_6.3VM_R25~D

1

C1301

+

2

JMINI2

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

GND1

GND2

TYCO_1775838-1~D

+3.3V_WLAN

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

54

+1.5V_RUN

WLAN_RADIO_DIS#_R
WLAN_PLTRST3#_R

WLAN_SMBCLK
WLAN_SMBDATA

100K_0402_5%~D

1 2

1 2

0_0402_5%~D@

R1072

R1074

WLAN_RADIO_DIS#_R

RB751S40T1_SOD523-2~D

HOST_DEBUG_TX <36>

R1071 0_0402_5%~D
R1066 0_0402_5%~D@

+3.3V_RUN

8051_RX <36>
LED_WLAN_OUT# <37>
BT_ACTIVE <32,37>

12
12

R1612

0_0402_5%~D

1 2

R1058

12

0_0402_5%~D @

2 1

D36

USB_MCARD1_DET# <22>

JCLIP2

1

GND1

2

GND2

3

GND3

4

GND4

TYCO_1775837-1~D

WLAN_RADIO_DIS# <35>

PLTRST3# <20,28>

SB_WLAN_PCIE_RST# <20>

WLAN_SMBCLK

WLAN_SMBDATA

+PWR_SRC

100K_0402_5%~D

12

R1060

2N7002W-7-F_SOT323-3~D

WLAN_3V_ENABLE<36>

+3.3V_WLAN

2.2K_0402_5%~D

2.2K_0402_5%~D

12

12

R1075

R1076

Q136

G

2

2N7002W-7-F_SOT323-3~D@

13

D

S

R1077

1 2

G

2

0_0402_5%~D @

13

D

S

Q137

2N7002W-7-F_SOT323-3~D@

R1078

1 2

0_0402_5%~D@

Q135

2

G

100K_0402_5%~D

12

R1064

ICH_SMBDATA <22,28,32>

CLK_SDATA <6>

13

D

R1063

S

ICH_SMBCLK <22,28,32>

CLK_SCLK <6>

+3.3V_ALW

100K_0402_5%~D

6

12

R1061

2
1

2N7002W-7-F_SOT323-3~D

13

D

Q134

2

G

200K_0402_5%~D

12

R1062

S

+3.3V_WLAN

D

S

45

Q133
SI3456BDV-T1-E3_TSOP6~D

G

3

470K_0402_5%~D

12

C1292

1

2

4700P_0402_25V7K~D

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, M/B LA-3751P

401490

1

31 48Wednesday, March 28, 2007

A

of

5

4

3

2

1

EXPRESS CARD

OC#

GND

+1.5V_CARD

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

C1312

1

2

+3.3V_CARDAUX

0.1U_0402_16V4Z~D

+3.3V_CARD

C1316

10U_0805_6.3V6M~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

C1318

C1317

1

1

1

2

2

2

C1311

1

2

11
13

3
5

15
19
8

C1321

16

NC

7

1

2

EXPR_CARD_RST#

+1.5V_CARD

+3.3V_CARDAUX

0.1U_0402_16V4Z~D

R1079

0_0402_5%~D

L126

1

1

4

4

1 2

R1080

0_0402_5%~D

1 2

DLW21SN121SQ2L_4P~D@

2

2

3

3

PCIE_IRX_EXPTX_N4<22>
PCIE_IRX_EXPTX_P4<22>

PCIE_ITX_EXPRX_N4_C<22>
PCIE_ITX_EXPRX_P4_C<22>

USBP2_D-

USBP2_D+

ICH_SMBCLK<22,28,31>

CLK_PCIE_EXP#<6>
CLK_PCIE_EXP<6>

CPUSB#

31

FOX_QTS0030A-3121-9F~D

D D

USBP2-<22>

USBP2+<22>

JEXP

112
334
GND5GND
778
9910
111112
131314
151516
171718
191920
212122
232324
GND25GND
272728
292930
GND

C1315

GND

+3.3V_CARD

1

2

C1320

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32

PCIE_WAKE#
EXPR_CARD_RST#

EXP_CLKREQ#
CPPE#

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D
C1319

1

1

2

2

PCIE_WAKE# <28,31,35>ICH_SMBDATA<22,28,31>

EXPRCRD_STBY#<35>

EXP_CLKREQ# <6>

+3.3V_SUS

R1081 100K_0402_5%~D

1 2

R1082 0_0402_5%~D@

1 2

R1083 100K_0402_5%~D

1 2

R1084 100K_0402_5%~D

1 2

+3.3V_SUS

+3.3V_RUN

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D
C1314

C1313

CPPE#<35>

1

1

2

2

PLTRST1#<10,20>

+1.5V_RUN

0.1U_0402_16V4Z~D

C1310

1

2

PLTRST1#

EXPRCRD_STBY_R#

CPPE#
CPUSB#

U56

12

1.5Vin

14

1.5Vin

2

3.3Vin

4

3.3Vin
AUX_IN17AUX_OUT

6

SYSRST#

20

SHDN#

1

STBY#

10

CPPE#

9

CPUSB#

18

RCLKEN

R5538D001-TR-F_QFN20_4X4~D

1.5Vout

1.5Vout

3.3Vout

3.3Vout

PERST#

+1.5V_CARD: Max. 650mA, A verage 500mA
+3.3V_CA R D: Max. 1300mA, Average 1000mA

C C

SMART CARD and Biometric Reader

+3.3V_RUN

4

D2+

5

VCC

D1-

C1323

1

2

USB_BIO_L-

6

USB_BIO_L-

USB_BIO_L+

0.1U_0402_16V4Z~D

VR_CPR0
VR_CPR1

3V_CPR

EGATED-

EGATED+

SC_VCC

SC_RST#

SC_CLK

SC_C4

SC_IO

SC_DET#

NC1
NC2
NC3

GND0
GND1
GND2

Layout Notes

USB_BIO-+/U SB_SC-+ msut b e kept equal length
with a differ en ti al impedance of 90 ohms

12

C1324

PCI_RST#<20,30,33>

15K_0402_5%~D

R1619

USB_BIO_L+

4.7U_0603_6.3V4Z~D
C1325

1

2

USB_BIO_L­USB_BIO_L+

15K_0402_5%~D

12

1

2

R1094

+5V_RUN

0.1U_0402_16V4Z~D

PCI_RST#

MD0

12

Place close to pin 3

CLK_SMC_48M

12

R1095

10_0402_5%~D@

1

C1332

4.7P_0402_50V8C~D@

2

B B

USBP6-<22>
USBP6+<22>

A A

+3.3V_RUN

1.5K_0402_5%~D

12

R1085

CLK_SMC_48M<6>

R1618

5

4.7K_0402_5%~D

U74

1

D1+

2

GND

3

D2-

IP4220CZ6_SO6~D@

+3.3V_RUN

4.7U_0603_6.3V4Z~D

C1322

1

2

U57

8

3.3VCC

5

VCC5V_IN0

28

VCC5V_IN1

17

UPD-

16

UPD+

19

DPD-

18

DPD+

12

RST#

14

RFIO0

15

RFIO1

3

XI/48M_IN

4

XO

32

MODE0/LED#

1

MODE1

2

MODE2

OZ77CR6LN_QFN32~D

Layout Note: Place close to BIO connector

4

4

1

1

15K_0402_5%~D

15K_0402_5%~D

12

R1595

C1331

1U_0603_10V4Z~D

6

1 2
10
29

1 2

C1446 1U_0603_10V4Z~D

USB_SC-

21

USB_SC+

20
27

SC_RST#

24

SC_CLK

23

SC_C4

22

SC_IO

25

SC_DET#

13
7

30
31

9
11
26

4

12

R1596

L132 DLW21SN121SQ2L_4P~D@

R1090 220_0402_5%~D
R1091 33_0402_5%~D
R1092 220_0402_5%~D
R1093 220_0402_5%~D

R1096 15K_0402_5%~D

1 2

R1097 15K_0402_5%~D

1 2

R1087

33_0402_5%~D

1 2

R1088

33_0402_5%~D

1 2

C1326

1

2

12
12
12
12

+3.3V_ALW

100K_0402_5%~D

12

R1613

+3.3V_RUN

JBIO

7

1

7

3

3

2

2

C84

0.1U_0402_16V4Z~D

4.7U_0603_6.3V4Z~D

C1327

1

+SC_VCC

12

2

R1089

USB_SC+
USB_SC-

SC_DET#<35>

USB_BIO-

USB_BIO+

47P_0402_50V8J~D@

47P_0402_50V8J~D@

1

1

C83

2

2

0.1U_0402_16V4Z~D

10K_0402_5%~D

12

C1329

C1328

R1086

47K_0402_5%~D

1

2

0.1U_0402_16V4Z~D

C1330

1

2

R1614

+SC_VCC+SC_VCC

1U_0603_10V4Z~D

1

2

0_0402_5%~D

12

JSMART

10

10

9

9

8

8

7

7

6

6

5

5

4

4

3

3

2

2

1

1

MOLEX_52610-1075~D

Layout Note: Place R1089~R1093 and C1330 closely JSC

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

1

2

2

3

3

4

4

5

5

6

6

MOLEX_53398-0671~D

BIO_DET# <35>

20

20

19

19

18

18

17

17

16

16

15

15

14

14

13

13

12

12

11

11

8

BLUETOOTH

8

COEX2_WLAN_ACTIVE<31>

BT_RADIO_DIS#<35>

COEX1_BT_ACTIVE<31>

USBP3-<22>
USBP3+<22>

BT_ACTIVE<31,37>

10K_0402_5%~D

33P_0402_50V8J~D

C1168

12

R960

C1167

1

2

+3.3V_RUN

1

C1164

0.1U_0402_16V4Z~D

2

JBT

1

1

2

2

3

3

4

4

5

11

5

11

6

12

6

12

7

T93

100P_0402_50V8J~D@

1

2

7

8

8

9

9

10

10

JST_BM10B-SRSS-TB~D

DELL CONFIDENTIAL/PROPRIETARY

Title

SCHEMATIC, M/B LA-3751P

Size Document Number Rev

2

Date: Sheet

Compal Electronics, Inc.

401490

32 48Wednesday, March 28, 2007

1

A

of

5

4

3

2

1

+5V_RUN

D D

+3.3V_RUN

100K_0402_5%~D

R1099

DOCK_PCI_EN#<34>

QBUFEN#<35>

C C

DOCK_PCI_EN#
QBUFEN#

1 2

5

1

P

INA

2

INB

G

3

0.1U_0402_16V4Z~D

C1337

1

2

4

O

U59
74AHC1G32GW_SOT353-5~D

QUIETE#

PCI_AD[0..31]<20,30>

D37

2 1

RB751V_SOD323-2~D

QUIETE#

PCI_AD31
PCI_AD30
PCI_AD29
PCI_AD28
PCI_AD27
PCI_AD26
PCI_AD24
PCI_AD25

PCI_AD23
PCI_AD20
PCI_AD22
PCI_AD19
PCI_AD21
PCI_AD16
PCI_AD18
PCI_AD17

PCI_AD15
PCI_AD14
PCI_AD13
PCI_AD11
PCI_AD12
PCI_AD10
PCI_AD9
PCI_AD8

PCI_AD7
PCI_AD6
PCI_AD4
PCI_AD5
PCI_AD3
PCI_AD2
PCI_AD0
PCI_AD1

+VCC_QBUFD

2 1

RB751V_SOD323-2~D

U58

1

NC1

2

A1

3

A2

4

A3

5

A4

6

A5

7

A6

8

A7

9

A8

10

GND1

11

NC2

12

A9

13

A10

14

A11

15

A12

16

A13

17

A14

18

A15

19

A16

20

GND2

21

NC3

22

A17

23

A18

24

A19

25

A20

26

A21

27

A22

28

A23

29

A24

30

GND3

31

NC4

32

A25

33

A26

34

A27

35

A28

36

A29

37

A30

38

A31

39

A32

40

GND4

PI5C34X2245BE_BQSOP80~D

D38

80

VCC4

79

OE1#

78

B1

77

B2

76

B3

75

B4

74

B5

73

B6

72

B7

71

B8

70

VCC3

69

OE2#

68

B9

67

B10

66

B11

65

B12

64

B13

63

B14

62

B15

61

B16

60

VCC2

59

OE3#

58

B17

57

B18

56

B19

55

B20

54

B21

53

B22

52

B23

51

B24

50

VCC1

49

OE4#

48

B25

47

B26

46

B27

45

B28

44

B29

43

B30

42

B31

41

B32

+VCC_QBUF

DOCK_AD31
DOCK_AD30
DOCK_AD29
DOCK_AD28
DOCK_AD27
DOCK_AD26
DOCK_AD24
DOCK_AD25

DOCK_AD23
DOCK_AD20
DOCK_AD22
DOCK_AD19
DOCK_AD21
DOCK_AD16
DOCK_AD18
DOCK_AD17

DOCK_AD15
DOCK_AD14
DOCK_AD13
DOCK_AD11
DOCK_AD12
DOCK_AD10
DOCK_AD9
DOCK_AD8

DOCK_AD7
DOCK_AD6
DOCK_AD4
DOCK_AD5
DOCK_AD3
DOCK_AD2
DOCK_AD0
DOCK_AD1

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

4.7K_0402_5%~D

12

C1334

C1333

R1098

1

2

DOCK_AD[0..31] <34>

0.047U_0402_16V4Z~D

C1336

1

1

2

2

C1335

1 2

0.047U_0402_16V4Z~D
C1338

B B

PCI_RST#<20,30,32>
PCI_GNT0#<20,34>

SYS_PME#<30,35>
PCI_C_BE3#<20,30>
PCI_PIRQA#<20>
PCI_STOP#<20,30>
PCI_TRDY#<20,30>
PCI_FRAME#<20,30,34>

PCI_C_BE2#<20,30>
PCI_PERR#<20,30>
PCI_PLOCK#<20>
PCI_IRDY#<20,30,34>
PCI_C_BE1#<20,30>
PCI_PAR<20,30>
PCI_SERR#<20,30>

PCI_DEVSEL#<20,30>

PCI_C_BE0#<20,30>

A A

QUIETE#

PCI_RST#
PCI_GNT0#

SYS_PME#
PCI_C_BE3#
PCI_PIRQA#
PCI_STOP#
PCI_TRDY#
PCI_FRAME#

PCI_C_BE2#
PCI_PERR#
PCI_PLOCK#
PCI_IRDY#
PCI_C_BE1#
PCI_PAR
PCI_SERR#
PCI_DEVSEL#
PCI_C_BE0# DOCK_C_BE0#
PCI_AD24 DOCK_PCI_IDSEL

U60

47

OE1
OE235VCC2

2

A0

3

A1

4

A2

5

A3

6

A4

7

A5

8

A6

9

A7

10

A8

11

A9

14

A10

15

A11

16

A12

17

A13

18

A14

19

A15

20

A16

21

A17

22

A18

23

A19

1

NC1

13

NC2

PI5C162861BE_BQSOP48~D

VCC1

GND1
GND2

B0
B1
B2
B3
B4
B5
B6
B7
B8
B9

B10
B11
B12
B13
B14
B15
B16
B17
B18
B19

36
48

46
45
44
43
42
41
40
39
38
37

34
33
32
31
30
29
28
27
26
25

12
24

1 2

0.1U_0402_16V4Z~D

DOCK_PCIRST#
DOCK_GNT0#

DOCK_PME#
DOCK_C_BE3#
DOCK_PIRQA#
DOCK_STOP#
DOCK_TRDY#
DOCK_FRAME#

DOCK_C_BE2#
DOCK_PERR#
DOCK_LOCK#
DOCK_IRDY#
DOCK_C_BE1#
DOCK_PAR
DOCK_SERR#
DOCK_DEVSEL#

DOCK_PCIRST# <34>
DOCK_GNT0# <34>

DOCK_PME# <34>
DOCK_C_BE3# <34>
DOCK_PIRQA# <34>
DOCK_STOP# <34>
DOCK_TRDY# <34>
DOCK_FRAME# <34>

DOCK_C_BE2# <34>
DOCK_PERR# <34>
DOCK_LOCK# <34>
DOCK_IRDY# <34>
DOCK_C_BE1# <34>
DOCK_PAR <34>
DOCK_SERR# <34>
DOCK_DEVSEL# <34>
DOCK_C_BE0# <34>
DOCK_PCI_IDSEL <34>

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, M/B LA-3751P

401490

33 48Wednesday, March 28, 2007

1

A

of

5

JDOCKA

1

S1

2

DVI2_CLK-

DVI2_CLK-<18>

DVI2_CLK+<18>

D D

DVI2_TX2+<18>

DVI2_TX2-<18>

DVI2_TX1+<18>

DVI2_TX1-<18>

DVI2_TX0+<18>

DVI2_TX0-<18>

CLK_PCI_DOCK<6>

DOCK_PIRQA#<33>

DOCK_SMBCLK<36>

DOCK_SMBDAT<36>

CLK_DOCK<36>
DAT_DOCK<36>

C C

B B

A A

Place close to pin 35

CLK_PCI_DOCK

33_0402_5%~D@

12

R1102

C1347

22P_0402_50V8J~D@

1

2

DVI2_CLK+

DOCK_PSID

DVI2_TX2+
DVI2_TX2-

DVI2_TX1+
DVI2_TX1-

DVI2_TX0+
DVI2_TX0-

DOCK_AD31
CLK_PCI_DOCK DOCK_PCIRST#
DOCK_PIRQA#

DOCK_SMBCLK
DOCK_SMBDAT
CLK_DOCK
DAT_DOCK

DOCKED<28,35>

D39

2

1

3

SM05TCT_SOT23-3~D@

DOCK_PWR_EN<35>

DOCK_PWR_EN

S2

3

S3

4

S4

5

S5

6

S6

7

S7

8

S8

9

S9

10

S10

11

S11

12

S12

13

S13

15

S15

17

S17

18

S18

19

S19

20

S20

21

S21

22

S22

23

S23

24

S24

25

S25

26

S26

27

S27

28

S28

29

S29

30

S30

31

S31

32

S32

33

S33

34

S34

35

S35

36

S36

37

S37

38

S38

39

S39

40

S40

41

S41

42

S42

43

S43

45

S45

47

S47

48

S48

49

S49

50

S50

51

S51

52

S52

53

S53

54

S54

55

S55

AMP_1473681~D

+3.3V_ALW

12

13

69

S69

70

S70

71

S71

72

S72

73

S73

74

S74

75

S75

76

S76

77

S77

78

S78

79

S79

80

S80

81

S81

82

S82

83

S83

84

S84

85

S85

86

S86

87

S87

88

S88

89

S89

90

S90

91

S91

92

S92

93

S93

94

S94

95

S95

96

S96

97

S97

98

S98

99

S99

100

S100

101

S101

102

S102

103

S103

104

S104

105

S105

106

S106

107

S107

108

S108

109

S109

110

S110

111

S111

112

S112

113

S113

114

S114

115

S115

116

S116

117

S117

118

S118

119

S119

120

S120

121

S121

122

S122

125

S125

126

S126

127

S127

128

S128

136

M136

R1104
100K_0402_5%~D

DOCK_DET#

2

Q139
DDTC144EUA-7-F_SOT323-3~D

+3.3V_SUS

0.1U_0603_50V4Z~D

5

2

P

A

1

B

G

3

D_SERIRQ
DOCK_PCI_IDSEL

D_DLRQ1#
D_LFRAME#

DVI_SCLK_L
DVI_SDAT_L
DVI_DETECT_L
DOCK_AD8
DOCK_C_BE0#

DOCK_AD14
DOCK_AD15

DOCK_DEVSEL#
DOCK_IRDY#

DOCK_AD19
DOCK_AD20

DOCK_AD27
DOCK_AD28
DOCK_AD30

USBP7­USBP7+

CLK_KBD
DAT_KBD

+2.5V_LAN

0_0402_5%~D

DOCK_RING

+PWR_SRC

+5V_ALW

12

C1352

1 2

4

Y

U64
74AHCT1G08GW_SOT353-5~D

4

RED_VGA <18,19>

D_SERIRQ <35>

R1101

DOCK_PCI_IDSEL <33>

D_DLRQ1# <35>
D_LFRAME# <35>

DVI_SCLK_L <18>
DVI_SDAT_L <18>
DVI_DETECT_L <18>DOCK_PSID<41>

DOCK_C_BE0# <33>

DOCK_DEVSEL# <33>
DOCK_IRDY# <33>

DOCK_GNT0# <33>

USBP7- <22>
USBP7+ <22>

DOCK_SMB_PME# <35>

CLK_KBD <36>
DAT_KBD <36>

12

C1343

0.01U_0402_16V7K~D
1 2

C1345

0.01U_0402_16V7K~D
1 2

DOCK_LOM_TX3- <28>
DOCK_LOM_TX3+ <28>
DOCK_LOM_TX2- <28>
DOCK_LOM_TX2+ <28>

+3.3V_RUN

+2.5V_LAN_R

D_LAD1<35>
D_LAD2<35>
D_LAD3<35>

DOCK_PAR<33>
DOCK_SERR#<33>
DOCK_LOCK#<33>

DOCK_FRAME#<33>

DOCK_C_BE2#<33>

DOCK_PME#<33>

TV_C_VGA<18,19>

DOCK_PCI_EN#<33>

DOCK_SPD10LED_GRN#<28>

DOCK_SPD100LED_ORG#<28>

R1100 100K_0402_5%~D@

C1344

0.01U_0402_16V7K~D
12

C1346

0.01U_0402_16V7K~D
12

DOCK_LOM_TX1-<28>
DOCK_LOM_TX1+<28>
DOCK_LOM_TX0-<28>
DOCK_LOM_TX0+<28>

PLACE TERMINATIONS CLOSE TO DOCK CONNECTOR

8

+DOCK_PW R_ SRC

7

1
2

100K_0603_5%~D

3

+G_DOC_PWRSRC

2

100K_0402_5%~D

12

R1111

G

4

12

R1107
100K_0402_5%~D

Z3307

13

D

S

6
5

Q138
FDS4435BZ_SO8~D

Q140
2N7002W-7-F_SOT323-3~D

R1106
100K_0402_5%~D

C1350

2

1

Z3308

0.47U_0805_25V7K~D

12

R1103

3

GRN_VGA<18,19>
BLU_VGA<18,19>

DOCK_DET# DOCK_DET#

D_LAD1
D_LAD2
D_LAD3

DOCK_AD1
DOCK_AD0

DOCK_AD3
DOCK_AD4
DOCK_AD7

DOCK_AD9
DOCK_AD10
DOCK_AD11

DOCK_PAR
DOCK_SERR#
DOCK_LOCK#

DOCK_FRAME#
DOCK_C_BE2#
DOCK_AD16

DOCK_AD22
DOCK_AD23
DOCK_AD24

DOCK_AD29
DOCK_PME#

DOCK_PCI_EN#
SPDIF_DOCK

DOCK_OWNS_PCI

12

DOCK_TIP

JDOCKB

137

S137

138

S138

139

S139

140

S140

141

S141

142

S142

143

S143

144

S144

145

S145

146

S146

147

S147

148

S148

149

S149

150

S150

151

S151

152

S152

153

S153

154

S154

155

S155

156

S156

157

S157

158

S158

159

S159

160

S160

161

S161

162

S162

163

S163

164

S164

165

S165

166

S166

167

S167

168

S168

169

S169

170

S170

171

S171

172

S172

173

S173

174

S174

175

S175

176

S176

177

S177

178

S178

179

S179

180

S180

181

S181

182

S182

183

S183

184

S184

185

S185

186

S186

187

S187

188

S188

189

S189

190

S190

193

S193

194

S194

195

S195

196

S196

204

M204

AMP_1473681~D

205

S205

206

S206

207

S207

208

S208
S209
S210
S211
S212
S213
S214
S215
S216
S217
S218

S220
S222

S223
S224
S225
S226
S227
S228
S229
S230
S231
S232
S233
S234
S235
S236
S237
S238
S239
S240
S241
S242
S243
S244
S245
S246
S247
S248

S250
S252

S253
S254
S255
S256
S257
S258
S259

AUD_SPDIF_OUT<19,25>

PCI_GNT0#<20,33>

HSYNC_DOCK

209

VSYNC_DOCK

210
211

D_CLKRUN#

212

D_LAD0

213

DOCK_SMB_ALERT#

214
215

DOCK_AD2

216

DOCK_AD5

217

DOCK_AD6

218
220

DOCK_AD12

222

DOCK_AD13

223

DOCK_C_BE1#

224
225

DOCK_PERR#

226

DOCK_STOP#

227

DOCK_TRDY#

228
229

DOCK_AD17

230

DOCK_AD18

231

DOCK_AD21

232
233

DOCK_C_BE3#

234

DOCK_AD25

235

DOCK_AD26

236
237

PCI_REQ0#

238
239
240
241
242
243
244
245

DOCK_ACTLED_YEL#

246
247

HDD_LED

248
250
252

253
254
255
256
257
258
259

PCI_GNT0# Z3305

PCI_IRDY#<20,30,33>

PCI_FRAME#<20,30,33>

DOCK_TIP
DOCK_RING

0.1U_0402_16V4Z~D

+3.3V_RUN

0.1U_0402_16V4Z~D

5

P

A2Y

G

3

PCI_IRDY#
PCI_FRAME#

2

DAT_DDC2_VGA <18,19>
CLK_DDC2_VGA <18,19>

HSYNC_DOCK <19>
VSYNC_DOCK <19>

D_CLKRUN# <35>
D_LAD0 <35>

DOCK_SMB_ALERT# <36>

DOCK_C_BE1# <33>

DOCK_PERR# <33>
DOCK_STOP# <33>
DOCK_TRDY# <33>

DOCK_C_BE3# <33>

PCI_REQ0# <20>

DOCK_PCIRST# <33>
TV_CVBS_VGA <18,19>
TV_Y_VGA <18,19>

DOCK_ACTLED_YEL# <28>

HDD_LED <37>

JWIRE2

1

1

2

2

3

3
44G2

+5V_RUN

1

C1018

2

1

5

P

OE#

A2Y

G

3

C1348

1 2

1

U61

NC

4

NC7SZ04P5X_NL_SC70-5~D

+3.3V_RUN

0.1U_0402_16V4Z~D

5

1

P

IN1

2

IN2

G

3

+DOCK_PW R_ SRC

1000P_0402_50V7K~D

C1341

1

2

5

G1

6

MOLEX_48227-0401~D

SPDIF_DOCKAUD_SPDIF_OUT

4

U34
74AHCT1G125GW_SOT353-5~D

C1351

1 2

4

O

U63
74AHC1G08GW_SOT353-5~D

Z3306

1

JDOCKC

P1

P1

P2

P2

P3

P3

P4

MH1
MH5
MH6
MH9

MH10

MH3
MH13
MH15

DOCK_AD0
DOCK_AD1
DOCK_AD2
DOCK_AD3
DOCK_AD4
DOCK_AD5
DOCK_AD6
DOCK_AD7
DOCK_AD8
DOCK_AD9
DOCK_AD10
DOCK_AD11
DOCK_AD12
DOCK_AD13
DOCK_AD14
DOCK_AD15
DOCK_AD16
DOCK_AD17
DOCK_AD18
DOCK_AD19
DOCK_AD20
DOCK_AD21
DOCK_AD22
DOCK_AD23
DOCK_AD24
DOCK_AD25
DOCK_AD26
DOCK_AD27
DOCK_AD28
DOCK_AD29
DOCK_AD30
DOCK_AD31

+3.3V_RUN

1

IN1

2

IN2

P4

MH1
SHLD1
SHLD2
SHLD5
SHLD6

MH3
MH13
MH15

AMP_1473681~D

C1349

1 2

0.1U_0402_16V4Z~D

5

P

4

O

G

U62
74AHC1G08GW_SOT353-5~D

3

0.1U_0603_50V4Z~D

C1342

1

2

P5

P5

P6

P6

P7

P7

P8

P8

MH2

MH2

MH7

SHLD3

MH8

SHLD4

MH11

SHLD7

MH12

SHLD8

MH4

MH4

MH14

MH14

MH16

MH16

DOCK_AD[0..31] <33>

DOCK_OWNS_PCI

+DC_IN

0.1U_0603_50V4Z~D

C1339

1000P_0402_50V7K~D

C1340

1

1

2

2

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.
SCHEMATIC, M /B LA-3751P

401490

1

34 48Wednesday, March 28, 2007

A

of

5

+3.3V_ALW

1 2

R1114 10K_0402_5%~D

1 2

R1116 10K_0402_5%~D

+5V_ALW

1 2

D D

C C

B B

A A

R1115 10K_0402_5%~D

+3.3V_RUN

1 2

R1117 100K_0402_5%~D

R1136 100K_0402_5%~D

Note: For system debug
pin4 connect to seria l port pin3

T97

LID_CL#<37>

12

+5V_SUS

1

5

P

NC

4

A2Y

G

3

LID_CL#

R1140 10K_0402_5%~D
R1141 10K_0402_5%~D
R1142 10K_0402_5%~D

5

DOCK_SMB_PME#

IMVP6_PROCHOT#

TXD0

U67

NC7SZ04P5X_NL_SC70-5~D@

R1130

1 2

10_0402_5%~D

12
12
12

SYS_PME#
PCIE_WAKE#

PANEL_BKEN

+3.3V_ALW

+3.3V_ALW

ITP_DBRESET#<7,22>

12

R1129
1M_0402_5%~D

1

C1366

0.047U_0402_16V4Z~D

2

LID_CL_SIO#

10K_0402_5%~D@

R1139

1 2

R1127 0_0402_5%~D@

R1138

1 2

1 2

10K_0402_5%~D@

R1137

1 2

ROBSON_RADIO_DIS#<31>

10K_0402_5%~D@

CHIPSET_ID

4

U66

PBAT_PRES#<41>

SYS_PME#<30,33>

PCIE_WAKE#<28,31,32>

USB_BACK_EN#<27>

CB_HWSPND#<30>

BT_RADIO_DIS#<32>

CPPE#<32>

EXPRCRD_STBY#<32>

BC_INT#<36>

BC_DAT<36>

BC_CLK<36>
M_LED_BK<37>

USB_SIDE_EN#<27>

QBUFEN#<33>

DOCK_PWR_EN<34>

ADAPT_OC<46>

ADAPT_TRIP_SET<46>

PSID_DISABLE#<41>

PANEL_BKEN<18>

DOCKED<28,34>

DOCK_SMB_PME#<34>

NB_MUTE#<26>

AUD_SPDIF_SHDN<19,25>

DOCK_HP_MUTE#<25>

AUD_HP_NB_SENSE<25,26>

1.05V_RUN_ON<44>
PBAT_ALARM#<41>

HDDC_EN<24>

IMVP6_PROCHOT#<45>

1.5V_3.3V_5V_RUN_PWRGD<39>
LOM_LOW_PWR<28>

SC_DET#<32>

THERMTRIP_SIO<15>

CBUS_GRST#<30>

SIO_EXT_WAKE#<22>

LOM_CABLE_DETECT<28>

R1132 0_0402_5%~D

ICH_PME#<20>

ICH_PCIE_WAKE#<22>

WLAN_RADIO_DIS#<31>

R1134 0_0402_5%~D

LOM_TPM_EN#<28>

LOM_SUPER_IDDQ<28>

R1135 10K_0402_5%~D

ATF_INT#<15>

REV
X00

BID1
BID0

4

PBAT_PRES#

SYS_PME#
PCIE_WAKE#
USB_BACK_EN#

CB_HWSP ND#
BT_RADIO_DIS#
CPPE#
EXPRCRD_STBY#
BC_INT#
BC_DAT
BC_CLK

M_LED_BK
TXD0

USB_SIDE_EN#
QBUFEN#

DOCK_PWR_EN
ADAPT_OC
ADAPT_TRIP_SET
ITP_DBRESET#_R
PSID_DISABLE#
PANEL_BKEN
DOCKED
DOCK_SMB_PME#
NB_MUTE#

AUD_SPDIF_SHDN
DOCK_HP_MUTE#
AUD_HP_NB_ SENSE

LID_CL_SIO#

1.05V_RUN_ON
PBAT_ALARM#

HDDC_EN
MODC_EN CLK_SIO_14M

IMVP6_PROCHOT#

1.5V_3.3V_5V_RUN_PW RGD1.5V_3.3V_5V_RUN_PWRGD
LOM_LOW_PWR

SC_DET#
THERMTRIP_SIO
CBUS_GRST#

1 2

ICH_PME#
ICH_PCIE_W AKE#
WLAN_RADIO_DIS#

ROBSON_RADIO_DIS#

1 2

LOM_TPM_EN#
LOM_SUPER_IDDQ

CHIPSET_ID

12

BID1
BID0
ATF_INT#

BID1 BID0

00
1X01

0

97
98

99
100
101
102
103
104

24

25

26

27

58

59

60

1
2
3
4

5
84
83

6
65

66
67
68
69
70
71
73
74
75
76
77
78
79
80
81
82

61
62

63
28
29
30
31

32
33

88
89
90
91
92
93
94
95

106
107

109
110
111
112

113
114

115
116
117
118

ECE5028-NU_VTQFP128_14X14~D

3

+3.3V_ALW

0.1U_0402_16V4Z~D

C1355

1

34

57

85

108

VCC1

VCC1

VCC1

GPIO

VCC1

USB

TEST

CLK

LPC

DLPC

VCC1(VDDA33)

GPIOJ[7](VDDA33)

GPIOK[4](VDDA33)

GPIOI[1](VCC1)

GPIOJ[2](USBDP0)
GPIOJ[3](USBDN0)
GPIOJ[6](USBDP1)

GPIOJ[5](USBDN1)
GPIOK[0](USBDP2)
GPIOK[1](USBDN2)
GPIOK[3](USBDP3)
GPIOK[2](USBDN3)
GPIOK[5](USBDP4)
GPIOK[6](USBDN4)

GPIOI[6](VDDA33PLL)
GPIOI[5](VDDA18PLL)

GPIOI[2](VDD18)

CAP_LDO

GPIOJ[0](RBIAS)

TEST_PIN

GPIOI[7](ATEST)

GPIOI[4](XTAL1/CLKIN)

GPIOI[3](XTAL2)

LAD0
LAD1
LAD2
LAD3

LFRAME#

LRESET#

PCICLK

CLKRUN#

LDRQ0#
LDRQ1#

SER_IRQ

CLKI (14.318 MHz)

DLAD0
DLAD1
DLAD2
DLAD3

DLFRAME#

DCLK_RUN#

DLDRQ1#

DSER_IRQ

PWRGD

OUT65

GPIOJ[4](VSS)
GPIOK[7](VSS)

GPIOJ[1](VSS)

GPIOA[0]
GPIOA[1]
GPIOA[2]
GPIOA[3]
GPIOA[4]
GPIOA[5]
GPIOA[6]
GPIOA[7]

GPIOH[0]
GPIOH[1]
GPIOH[4]
GPIOH[5]
BC_INT#
BC_DAT
BC_CLK

GPIOE[0]/RXD
GPIOE[1]/TXD
GPIOE[2]/RTS#
GPIOE[3]/DSR#
GPIOE[4]/CTS#
GPIOE[5]/DTR#
GPIOE[6]/RI#
GPIOE[7]/DCD#

GPIOB[0]/INIT#
GPIOB[1]/SLCTIN#
GPIOC[2]/SCLT
GPIOC[3]/PE
GPIOC[4]/BUSY
GPIOC[5]/ACK#
GPIOC[6]/ERROR#
GPIOC[7]/ALF#
GPIOD[0]/STROBE#
GPIOC[1]/PD7
GPIOC[0]/PD6
GPIOB[7]/PD5
GPIOB[6]/PD4
GPIOB[5]/PD3
GPIOB[4]/PD2
GPIOB[3]/PD1
GPIOB[2]/PD0

GPIOD[1]
GPIOD[2]

GPIOD[3]/VBUS_DET
GPIOD[4]/OCS1_N
GPIOD[5]/OCS2_N
GPIOD[6]/OCS3_N
GPIOD[7]/OCS4_N

GPIOH[6]
GPIOH[7]

GPIOG[0]
GPIOG[1]
GPIOG[2]
GPIOG[3]
GPIOG[4]
GPIOG[5]
GPIOG[6]
GPIOG[7]

SYSOPT1/GPIOH[2]
SYSOPT0/GPIOH[3]

GPIOF[7]
GPIOF[6]
GPIOF[5]
GPIOF[4]

IRTX
IRRX

GPIOF[3]/IRMODE/IRRX3B
GPIOF[2]/IRTX2
GPIOF[1]/IRRX2
GPIOF[0]/IRMODE/IRRX3A

ECE5028-NU

(ECE5018)

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

VSS

VSS
VSS

VSS
VSS
VSS
VSS

2

8
14
20

119
9

10
13
12
15
16
19
18
21
22

125
124
120
86
127

35

126
123

122

54
52
49
47
42
41
56
37
46
44
39

64
96
55

53
50
48
43
38
45
40

7
105

11
17
23
36
51
72
87
121
128

0.1U_0402_16V4Z~D

BIO_DET#

4.7U_0603_6.3V4Z~D

C1368

1

2

2

0.1U_0402_10V7K~D
C1357

C1356

1

2

SIO_VDDA

C1359

1 2

BIO_DET# <32>

BATTERY_SAVER#

12K_0402_1%~D@

12

R1125

R1128 10K_0402_5%~D@

1 2

LPC_LAD0
LPC_LAD1
LPC_LAD2
LPC_LAD3
LPC_LFRAME#
PLTRST2#
CLK_PCI_5028
CLKRUN#
LPC_LDRQ0#
LPC_LDRQ1#
IRQ_SERIRQ

D_LAD0
D_LAD1
D_LAD2
D_LAD3
D_LFRAME#
D_CLKRUN#
D_DLRQ1#
D_SERIRQ

RUNPWROK

R1645

1 2

0_0402_5%~D

4.7U_0603_6.3V4Z~D@

0.1U_0402_16V4Z~D@

C1370

C1369

1

1

2

2

2

0.1U_0402_16V4Z~D
C1358

1

1

2

2

0.1U_0402_16V4Z~D

C1360

1

2

REG_EN

C1371

1

2

1

+3.3V_ALW

12

R1159
100K_0402_5%~D

0.1U_0402_16V4Z~D

C1361

1

2

BATTERY_SAVER#

0.1U_0402_16V4Z~D@

0.1U_0402_16V4Z~D@

C1362

1

2

4.7U_0603_6.3V4Z~D@

C1363

1

2

1

2

C1364

1

2

R1161

1 2

10K_0402_5%~D

C1379
1U_0603_10V4Z~D

R1118

1 2

4.7U_0603_6.3V4Z~D@
0_0603_5%~D

BATTERY_SAVER_SW# <37>

+3.3V_ALW

Place close to pin 56

CLK_PCI_5028

10_0402_5%~D@

+3.3V_ALW

12

R1126

10K_0402_5%~D@

4.7P_0402_50V8C~D@

Place close to pin 64

LPC_LAD[0..3] <21,28,36>

LPC_LFRAME# <21,28,36>
PLTRST2# <20,36>
CLK_PCI_5028 <6>
CLKRUN# <22,30,36>
LPC_LDRQ0# <21>
LPC_LDRQ1# <21>
IRQ_SERIRQ <22,28,30,36>

CLK_SIO_14M <6>MODC_EN<24>

D_LAD0 <34>
D_LAD1 <34>
D_LAD2 <34>
D_LAD3 <34>
D_LFRAME# <34>
D_CLKRUN# <34>
D_DLRQ1# <34>
D_SERIRQ <34>

RUNPW ROK <18,36,39,45>

LCD_TST <18>

4.7U_0603_6.3V4Z~D@

D_CLKRUN#
D_DLRQ1#
D_SERIRQ

CLK_SIO_14M

10_0402_5%~D@

4.7P_0402_50V8C~D@

R1120 100K_0402_5%~D
R1123 100K_0402_5%~D
R1121 100K_0402_5%~D

DELL CONFIDENTIAL/PROPRIETARY

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, M /B LA-3751P

401490

1

R1131

C1367

R1119

C1365

12

1

2

12

1

2

+3.3V_RUN

12
12
12

35 48Wednesday, March 28, 2007

A

of

5

M_ON
DDR_ON
AUX_ON
SUS_ON
RUN_ON
AC_OFF

10K_0402_5%~D

10K_0402_5%~D

12

R1178

DEBUG_ENABLE#

+5V_RUN

1 2

R1162 4.7K_0402_5%~D

1 2

R1163 4.7K_0402_5%~D

1 2

R1164 4.7K_0402_5%~D

1 2

R1166 4.7K_0402_5%~D

1.8V_SUS_PWRGD<43>
EC_CPU_PROCHOT#<7>

ICH_CL_PWROK<10,22>

ALW_PWRGD_3V_5V<42>

ICH_EC_SPI_CLK<22>

ICH_EC_SPI_DIN<22>

ICH_EC_SPI_DO<22>

SIO_PWRBTN#<22>

MEC5004_XTAL2

CLK_KBD

DAT_KBD

CLK_DOCK

DAT_DOCK

CKG_SMBDAT<6>
CKG_SMBCLK<6>

ICH_RSMRST#<22>

DDR_ON<43>
TP_DET#<37>

SIO_SLP_S3#<22>
SIO_SLP_S5#<22>

3.3V_RUN_ON<38>
AUX_ON<38>

SUS_ON<38,39>
RUN_ON<18,38,39>
AC_OFF<41>

BC_A_INT#<37>
BC_A_DAT<37>
BC_A_CLK<37>

SIO_A20GATE<21>

CLK_TP_SIO<37>
DAT_TP_SIO<37>
CLK_KBD<34>
DAT_KBD<34>
CLK_DOCK<34>
DAT_DOCK<34>

8051_RX<31>

8051_TX<31>

PLTRST2#<20,35>

CLK_PCI_5025<6>

LPC_LFRAME#<21,28,35>

LPC_LAD0<21,28,35>
LPC_LAD1<21,28,35>
LPC_LAD2<21,28,35>
LPC_LAD3<21,28,35>
CLKRUN#<22,30,35>

IRQ_SERIRQ<22,28,30,35>

BC_CLK<35>
BC_DAT<35>

BC_INT#<35>

CKG_SMBDAT
CKG_SMBCLK
ATI_ Intel_IDENTIFY

3.3V_M_PWRGD

T98

1.8V_SUS_PWRGD
EC_CPU_PROCHOT#

ICH_CL_PWROK
ICH_RSMRST#

M_ON

T100

SIO_SLP_M#

T101

DDR_ON
TP_DET#
ALW_PWRGD_3V_5V
SIO_SLP_S3#
SIO_SLP_S5#

3.3V_RUN_ON
AUX_ON

SUS_ON
RUN_ON
AC_OFF

1.05V_1.25V_M_PWRGD

T104

BC_A_INT#
BC_A_DAT
BC_A_CLK

SIO_A20GATE

CLK_TP_SIO
DAT_TP_SIO
CLK_KBD
DAT_KBD

DAT_DOCK
8051_RX
8051_TX

PLTRST2#
CLK_PCI_5025
LPC_LFRAME#
LPC_LAD0
LPC_LAD1
LPC_LAD2
LPC_LAD3
CLKRUN#
IRQ_SERIRQ

ICH_EC_SPI_CLK
ICH_EC_SPI_DIN
ICH_EC_SPI_DO

EC_FLASH_SPI_CLK
EC_FLASH_SPI_DIN
EC_FLASH_SPI_DO

SIO_PWRBTN#

BC_CLK
BC_DAT
BC_INT#

MEC5004_XTAL1

R1189 0_0402_5%~D

+3.3V_ALW

1 2

R1151 2.2K_0402_5%~D

1 2

R1153 2.2K_0402_5%~D

1 2

R1155 100K_0402_5%~D

R1157 0_0402_5%~D

R1146 1M_0402_5%~D

D D

1 2

R1152 100K_0402_5%~D

1 2

R1154 2.7K_0402_5%~D
R1144 2.7K_0402_5%~D
R1149 2.7K_0402_5%~D

1 2

R1156 2.7K_0402_5%~D@

CKG_SMBDAT
CKG_SMBCLK

ATI_ Intel_IDENTIFY

12

12

12
12

BC_DAT

R1752 no stuff when doing flash recovery

+3.3V_ALW

1M_0402_5%~D

12

12

R1176

R1177

JDEBUG

5

5

8051_RX

4

4

8051_TX

3

3

2

2

R1183 0_0402_5%~D

1

1

C C

Molex_53261@

1 2

Place close to pin 58

CLK_PCI_5025

12

R1187

10_0402_5%~D@

1

C1381

4.7P_0402_50V8C~D@

2

MEC5004_XTAL1

Y3

B B

32.768K_12.5P_1TJS125DJ4A420P~D

1 4

22P_0402_50V8J~D

2 3

C1386

1

2

C1385

MEC5004_XTAL2

22P_0402_50V8J~D

1

2

Non-AMT BroacomAMT IntelNet & Part

3.3V_M_PWRGD
CH_RSMRST#
M_ON
SIO_SLP_M#

1.05V_1.25V_M_PWRGD

A A

LOM_SUPER_IDDQ
LOM_LOW_PWR
LOM_CABLE_DETECT

Pin15 of 5025
Pin23 of 5025
Pin24 of 5025
Pin25 of 5025
Pin37 of 5025

NC
NC
NC

5

NC
NC
NC
NC
NC

NCR238 Pin24 of 5025
Refer to UMA
Refer to UMA
Refer to UMA

4

R1147

+RTC_CELL

12

12

R1191
10K_0402_5%~D

1 2

0_0402_5%~D

0.1U_0402_16V4Z~D

U68

12

KSO17/GPIOA1/AB1H_DATA

13

KSO16/GPIOA0/AB1H_CLK

14

GPIO5/KSO15

15

GPIO4/KSO14

16

KSO13/GPIO18

17

KSO12/OUT8

18

KSO11/GPIOC7

19

KSO10/GPIOC6

20

KSO9/GPIOC5

23

KSO8/GPIOC4

24

KSO7/GPIO3

25

KSO6/GPIO2

27

KSO5/GPIO1

28

KSO4/GPIO0

29

KSO3/GPIOC3

30

KSO2/GPIOC2

31

KSO1/GPIOC1

32

KSO0/GPIOC0

33

KSI7/GPIO19

34

KSI6/GPIO17

35

KSI5/GPIO10

36

KSI4/GPIO9

37

KSI3/GPIO8

38

KSI2/GPIO7/BC_A_INT#

39

KSI1/GPIO6/BC_A_DAT

40

KSI0/SGPIO30/BC_A_CLK

92

SGPIO34/A20M

50

OUT5/KBRST

75

GPIO94/IMCLK

76

GPIO95/IMDAT

77

KCLK

78

KDAT

79

GPIOA6/EMCLK

80

GPIOA7/EMDAT

81

GPIO20/PS2CLK/8051RX

82

GPIO21/PS2DAT/8051TX

57

LRESET#

58

PCICLK

59

LFRAME#

60

LAD0

61

LAD1

62

LAD2

63

LAD3

64

CLKRUN#

56

SER_IRQ

102

HSTCLK

105

HSTDATAIN

107

HSTDATAOUT

103

FLCLK

106

FLDATAIN

108

FLDATAOUT

109

GPIO80

110

GPIO81

87

BC_CLK

86

BC_DAT

85

BC_INT#

122

XTAL1

124

XTAL2

123

XOSEL

BLM18AG121SN1D_0603~D

low=write protected

+3.3V_ALW

FWP#

Flash writ e protect bottom 4K
of internal bootblock flash

4

C1372

L127

12

R1196
100K_0402_5%~D

12

R1198

100K_0402_5%~D@

AGND

125
12

1

2

VSS26VSS51VSS74VSS88VSS

+3.3V_ALW

121

VCC0

VCC121VCC144VCC165VCC183VCC1

113

C1383

1

C1373

0.1U_0402_16V4Z~D

2

116

POWER_ SW_IN2#/GPIO23
POWER_ SW_IN1#/GPIO22

SGPIO45/MSDATA/SPDOUT2

SGPIO44/MSCLK/SPCLK2

SYSOPT0/SGPIO32/LPC_TX
SYSOPT1/SGPIO33/LPC_RX

VR_CAP22VSS_PLL

4.7U_0603_6.3V4Z~D
101

1

C1382

2

0.1U_0402_16V4Z~D

BLM18AG121SN1D_0603~D

3

120
119
126
127
128
118

8
7
6
5
93
94
95
96
111
112
9
10
97
98
99
100

43
42
41

48

R1179 0_0402_5%~D

47
46
45

66
55
54
69

RSV_1.25V_GFX_PCIE_ON

68
67

70
71

91
90
89
4

1
2
3

52
11

115
114

84
73
117
49
53
72

1

C1376

0.1U_0402_16V4Z~D

2

ALWON

POWER_SW_IN#
ACAV_IN

LCD_SMBCLK
LCD_SMBDAT
DOCK_SMBCLK
DOCK_SMBDAT

PBAT_SMBDAT
PBAT_SMBCLK
SBAT_SMBDAT
SBAT_SMBCLK

1.5V_RUN_ON

1.25V_RUN_ON
THRM_SMBDAT

IMVP_PWRGD
FAN2_TACH
FAN1_TACH

1 2

3.3V_SUS_ON
BREATH_LEDCLK_DOCK

SIO_EXT_SCI#
PS_ID
SIO_RCIN#
BEEP

DEBUG_ENABLE#
HOST_DEBUG_TX

HOST_DEBUG_RX
CAP_LED#

SCRL_LED#
NUM_LED#
SIO_SPI_CS#

LOM_SMB_ALERT#
SFPI_EN
DOCK_SMB_ALERT#

0.9V_DDR_VTT_ON
SIO_EXT_SMI#

BAT2_ORG_LED#
BAT1_GRN_LED#

FWP#

RUNPWROK
RESET_OUT#
MEC_TEST_PIN

+3.3V_ALW

1

C1374

0.1U_0402_16V4Z~D

2

ALWON

POWER_ SW_IN0#

ACAV_IN

BGPO0/GPIOA5

AB1B_CLK/GPIOA4

AB1B_DATA/GPIOA2

AB1A_CLK

AB1A_DATA

GPIO11/AB2_DATA

GPIO12/AB2_CLK

GPIO13/AB1G_DATA

GPIO14/AB1G_CLK

GPIO87/AB1C_DATA

GPIO86/AB1C_CLK

GPIO85/AB1D_DATA

GPIO84/AB1D_CLK

GPIO93/AB1F_DATA

GPIO92/AB1F_CLK

GPIO91/AB1E_DATA

GPIO90/AB1E_CLK

GPIO82/FAN_TACH3
GPIO16/FAN_TACH2
GPIO15/FAN_TACH1

OUT2/PWM3

OUT9/PWM2
OUT11/PWM1
OUT10/PWM0

nEC_SCI/SPDIN2

SGPIO46/SPDIN1

SGPIO47/SPDOUT1

SGPIO31/TIN1/SPCLK1

SGPIO40
SGPIO41
SGPIO42
SGPIO43

SGPIO35

SGPIO36 (SFPI_EN)

SGPIO37

GPIO96/TOUT1

OUT7/nSMI
nPWR_LED

nBAT_LED

nFWP

GPIOA3/WINDMON

GPIO83/32KHZ_OUT

PWRGD

nRESET_OUT/OUT6

TEST_PIN

VCC_PLL

MEC5025-NU_VTQFP128~D

104

L128

BLM18AG121SN1D_0603~D

12

1 2

L129

1 2

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

1

C1377

0.1U_0402_16V4Z~D

2

+RTC_CELL

12

R1276

ALWON <42>

ACAV_IN <15,18,46>

T99

LCD_SMBCLK <18>
LCD_SMBDAT <18>
DOCK_SMBCLK <34>
DOCK_SMBDAT <34>

LCD_VCC_TEST_EN <18>

T102
T103

PBAT_SMBDAT <41>
PBAT_SMBCLK <41>

1.5V_RUN_ON <44>

1.25V_RUN_ON <43>
THRM_SMBDAT <15,46>
THRM_SMBCLK <15,46>

IMVP_PWRGD <22,39,45>

FAN2_TACH <15>
FAN1_TACH <15>

IMVP_VR_ON <45>

WLAN_3V_ENABLE <31>

3.3V_SUS_ON <38>
BREATH_LED <37>

SIO_EXT_SCI# <22>

PS_ID <41>

SIO_RCIN# <21>

BEEP <25>

T105

HOST_DEBUG_TX <31>
HOST_DEBUG_RX <31>

CAP_LED# <37>
SCRL_LED# <37>
NUM_LED# <37>

LOM_SMB_ALERT# <22,28>

DOCK_SMB_ALERT# <34>

0.9V_DDR_VTT_ON <43>

SIO_EXT_SMI# <22>
BAT2_ORG_LED# <37>
BAT1_GRN_LED# <37>

RUNPW ROK <18,35,39,45>
RESET_OUT# <39>

1 2

R1190

0_0402_5%~D

Place R1194 close to Flash ROM.

SPI_CS0#
EC_FLASH_SPI_DIN

+RTC_CELL

100K_0402_5%~D

R1158

2

1

C1375
10U_0805_10V4Z~D

2

100K_0402_5%~D

12

1=Flash Recovery Enabled
0=Flash Recovery Disabled

SFPI_EN

Bat2 = Amber LED
Bat1 = Green LED
20mA drive pins

1 2

R1194 15_0402_5%~D

2

EC_FLASH_PAD

R1186

1K_0402_5%~D

ICH_SPI_CS0#<22>

+3.3V_SUS

1

+RTC_CELL

12

R1143
100K_0402_5%~D

POWER_SW_IN#

+3.3V_ALW

1

1

2

2

12

1K_0402_5%~D

12

R1188

SIO_SPI_CS#

R1150

1 2

10K_0402_5%~D

1

C1378
1U_0603_10V4Z~D

2

LCD_SMBCLK
LCD_SMBDATTHRM_SMBCLK
PBAT_SMBDAT
PBAT_SMBCLK
SBAT_SMBDAT
SBAT_SMBCLK
THRM_SMBDAT
THRM_SMBCLK
HOST_DEBUG_RX
DOCK_SMB_ALERT#

DOCK_SMBCLK
DOCK_SMBDAT

LOM_SMB_ALERT#

+3.3V_ALW

0.1U_0402_16V4Z~D@

5

1

P

IN1

O

2

IN2

G

U69

3

1 2

0_0402_5%~D

POWER_SW# <15,37>

1 2

R1165 8.2K_0402_5%~D

1 2

R1167 8.2K_0402_5%~D

1 2

R1173 2.2K_0402_5%~D

1 2

R1175 2.2K_0402_5%~D

1 2

R1170 2.2K_0402_5%~D@

1 2

R1171 2.2K_0402_5%~D@

1 2

R1168 4.7K_0402_5%~D

1 2

R1169 4.7K_0402_5%~D

1 2

R1181 1M_0402_5%~D
R1180 10K_0402_5%~D

R1172 8.2K_0402_5%~D
R1174 8.2K_0402_5%~D

1 2

R1182 4.7K_0402_5%~D

C1380

1 2

R1184

15_0402_5%~D@

4

1 2

74AHC1G08GW_SOT353-5~D @
R1185

12

12
12

Place R1195 and R1197 close to EMC5025.

C1384

1 2

12

R1192
10K_0402_5%~D

U70

1

CE#

2
3
4

SST25VF016B-50-4C-S2AF_SO8~D

VDD

SO

HOLD#

WP#

SCLK

VSS

SI

Title

Size Document Number Rev

401490

Date: Sheet

0.1U_0402_16V4Z~D

12

R1193
10K_0402_5%~D

8
7
6
5

R1195

15_0402_5%~D

1 2
1 2

R1197

15_0402_5%~D

EC_FLASH_SPI_CLK
EC_FLASH_SPI_DO

Compal Electronics, Inc.

SCHEMATIC, M /B LA-3751P

36 48Wednesday, March 28, 2007

1

+3.3V_ALW

+5V_ALW

+3.3V_LAN

SPI_CS0#

A

of

5

4

3

2

1

+5V_RUN

R_BT_MPCI_ACT_R

D D

BT_ACTIVE<31,32> DAT_TP_SIO<36>

C C

BREATH_LED<36>

B B

BC_A_DAT<36>
BC_A_CLK<36>
BC_A_INT#<36>

A A

C1353

1

2

+3.3V_ALW

R1218

1 2

10K_0402_5%~D

R1211

1 2

10K_0402_5%~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

C1354

1

2

12

R1112

100K_0402_5%~D@
BC_A_DAT
BC_A_CLK
BC_A_INT#

R1113

1K_0402_5%~D

+3.3V_ALW

12

BT_MPCI_ACTIVE

BREATH_LED_B

U65

30

VCC1

10

VCC1

39

NC3

37

NC1

38

NC2

34

BC_DATA

35

BC_CLK

36

BC_INT#

40

TEST_PIN

41

GND_PAD

ECE1077-FZG_QFN40~D

C

Q146

2

B

MMST3904-7-F_SOT323-3~D

E

3 1

+3.3V_ALW

56_0402_5%~D

R1199

1 2

Z3901

C

Q141

2

B

MMST3904-7-F_SOT323-3~D

E

3 1

R_BREATH_LED

ECE1077

KSO16/GPIO_0
KSO17/GPIO_1
KSO18/GPIO_2
KSO19/GPIO_3
KSO20/GPIO_4
KSO21/GPIO_5
KSO22/GPIO_6

KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8

KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15

KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7

2

9
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
31
32
33

1
2
3
4
5
6
7
8

Q143
DDTA114EUA-7-F_SOT323-3~D

1 3

R_BT_MPCI_ACT

LED_WLAN_OUT#<31>

KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8

KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15
KSO16
KSO17

KSI0

KSI1

KSI2

KSI3

KSI4

KSI5

KSI6

KSI7

KSI7
KSI6
KSI4
KSI2
KSI5
KSI1
KSI3
KSI0
KSO5
KSO4
KSO7
KSO6
KSO8
KSO3
KSO1
KSO2
KSO0
KSO12
KSO16
KSO15
KSO13
KSO14
KSO9
KSO11
KSO10

CLK_TP_SIO<36>

+3.3V_RUN

2

1 3

R_LED_WLAN_OUT LED_WLAN_OUT

@

@

100P_0402_50V8J~D

C1393

100P_0402_50V8J~D

C1394

C1395

1

1

2

2

+5V_RUN

4.7K_0402_5%~D

12

R1202

R1203

DAT_TP_SIO
CLK_TP_SIO

Q142
DDTA114EUA-7-F_SOT323-3~D

@

100P_0402_50V8J~D

C1396

1

2

@

1

2

C1388

100P_0402_50V8J~D

C1397

10P_0402_50V8J~D

C1389

1

2

R1213

150_0402_5%~D

@

100P_0402_50V8J~D

C1398

1

2

4.7K_0402_5%~D

12

L130

BLM18AG601SN1D_0603~D

1 2
1 2

10P_0402_50V8J~D

L131

BLM18AG601SN1D_0603~D

1

2

12

@

@

100P_0402_50V8J~D

100P_0402_50V8J~D

C1399

C1400

1

1

2

2

JTP

2

KSO17

R1200 0_0402_5%~D

M_LED_BK<35>

TP_DATA

TP_CLK

10P_0402_50V8J~D

10P_0402_50V8J~D

C1392

C1391

1

1

@

@

100P_0402_50V8J~D

100P_0402_50V8J~D

C1401

C1402

1

1

2

2

2

2

SATA_ACT#<21>

HDD_LED<34>

@

@

100P_0402_50V8J~D

100P_0402_50V8J~D

C1404

C1403

1

1

2

2

1

2

2

@

100P_0402_50V8J~D

+3.3V_RUN

C1405

1

2

TP_DET#<36>

Q144
DDTA114EUA-7-F_SOT323-3~D

1 3

@

@

100P_0402_50V8J~D

100P_0402_50V8J~D

C1406

1

2

R1204 0_0402_5%~D

R1637 0_0402_5%~D

R1220

1 2

100_0402_5%~D

@

@

100P_0402_50V8J~D

100P_0402_50V8J~D

C1408

C1407

1

1

2

2

LID_CL#<35>

+5V_ALW

ACTLED

C1409

12
12

LID_CL#
TP_DATA

12

1

C1387

0.1U_0402_16V4Z~D

2

BATTERY_SAVER_SW#<35>

@

100P_0402_50V8J~D

C1410

1

2

@

@

100P_0402_50V8J~D

100P_0402_50V8J~D

C1411

1

1

2

2

112
334
556
778
9910

11

11

13

13
151516

17

17

19

19

JST_BM20B-SRDS-G-TFC

BAT2_ORG_LED#<36>
BAT1_GRN_LED#<36>

CAP_LED#<36>
NUM_LED#<36>
SCRL_LED#<36>

POWER_SW#<15,36>

@

100P_0402_50V8J~D

C1412

C1413

1

1

2

2

4
6
8
10
12

12

14

14

16
18

18

20

20

R_BT_MPCI_ACT
BAT2_ORG_LED#
BAT1_GRN_LED#
R_BREATH_LED
ACTLED
CAP_LED#
NUM_LED#
SCRL_LED#

LED_WLAN_OUT
POWER_SW#
BATTERY_SAVER_SW#

+3.3V_ALW

@

@

100P_0402_50V8J~D

100P_0402_50V8J~D

C1415

C1414

1

2

R1201 0_0402_5%~D

1 2

R1205 0_0402_5%~D

1 2

R1206 0_0402_5%~D

1 2

R1207 0_0402_5%~D

1 2
R1208 0_0402_5%~D
R1209 0_0402_5%~D
R1210 0_0402_5%~D

@

100P_0402_50V8J~D

C1416

1

2

1 2

1 2

1 2

+5V_RUN

1

C1390

0.1U_0402_16V4Z~D

2

JSW
15
14
13
12
11
10

9
8
7
6
5
4
3
2
1

MOLEX_53398-1371~D

@

@

100P_0402_50V8J~D

100P_0402_50V8J~D

C1417

1

1

2

2

GND2
GND1
13
12
11
10
9
8
7
6
5
4
3
2
1

JKYBD

25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

HRS_FH28D-25SB-1SH~D

KSI0
KSI1
KSI2
KSI3
KSI4
KSI5TP_CLK
KSI6

27
26

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, M/B LA-3751P

401490

1

37 48Wednesday, March 28, 2007

A

of

5

4

3

2

1

+3.3V_RUN Source

+3.3V_ALW

Q157

SI4810BDY-T1-E3_SO8~D
8
7

5

D D

3.3V_RUN_ON<36>

+3.3V_ALW2

2

G

12

R1234
100K_0402_5%~D

13

D

S

RUN_ON_3.3V#

Q162
2N7002W-7-F_SOT323-3~D

+15V_ALW

12

R1231
100K_0402_5%~D

RUN_ON_3.3V

13

D

2

G

S

Q160
2N7002W-7-F_SOT323-3~D

RB751V_SOD323-2~D@

1 2

0_0402_5%~D

D40

21

R1236

Q158

SI4336DY-T1-E3_SO8~D@
8
7

RUN_ON_R

5

1

C1426

4700P_0402_25V7K~D@

2

1
2
36

4

1
2
36

4

C1424

1

2

+3.3V_RUN

10U_0805_10V4Z~D

12

R1232

20K_0402_5%~D

+5V_RUN Source

+5V_ALW +5V_RUN

+15V_ALW

+3.3V_ALW2

C C

RUN_ON<18,36,39>

12

R1229
100K_0402_5%~D

13

D

2

G

S

RUN_ON_5V#
Q156
2N7002W-7-F_SOT323-3~D

12

13

D

2

G

S

R1227
100K_0402_5%~D

RUN_ENABLE

Q155
2N7002W-7-F_SOT323-3~D

8
7

5

Q154

SI4810BDY-T1-E3_SO8~D

1

C1423
2200P_0402_50V7K~D

2

1

10U_0805_10V4Z~D
2
36

C1422

4

20K_0402_5%~D

12

R1228

1

2

+3.3V_SUS Source

3.3V_SUS_ON<36>

+5V_SUS Source

SUS_ON<36,39>

SUS_ON

+3.3V_ALW2

2

G

+3.3V_ALW2

2

G

12

R1225
100K_0402_5%~D

13

D

S

12

R1223
100K_0402_5%~D

13

D

S

SUS_ON_3.3V#

Q153
2N7002W-7-F_SOT323-3~D

SUS_ON_5V#
Q151
2N7002W-7-F_SOT323-3~D

2

2

+15V_ALW

G

+15V_ALW

G

12

R1224
100K_0402_5%~D

13

D

S

12

R1221
100K_0402_5%~D

13

D

S

+3.3V_ALW

Q152
2N7002W-7-F_SOT323-3~D

Q150
2N7002W-7-F_SOT323-3~D

SI4810BDY-T1-E3_SO8~D

SUS_ON_3.3V

SI3456BDV-T1-E3_TSOP6~D

SUS_ENABLE

Q149

8
7

5

4

4700P_0402_25V7K~D@

C1421

1

2

+5V_ALW

6
2

Q148

1

4700P_0402_25V7K~D@

C1419

1

2

+3.3V_SUS

1

10U_0805_10V4Z~D
2
36

C1420

D

S

C1418

G

3

20K_0402_5%~D

12

R1226

1

2

+5V_SUS

45

10U_0805_10V4Z~D

20K_0402_5%~D

12

R1222

1

2

Discharg Circuit

+5V_SUS+1.8V_SUS +3.3V_SUS

12

R1238

75_0603_5%~D@

Z4002

Q163

13

B B

SUS_ON_3.3V#

D

2N7002W-7-F_SOT323-3~D@

2

G

S

12

R1239

1K_0402_5%~D@

Z4003

Q164

13

D

2N7002W-7-F_SOT323-3~D@

2

G

S

12

R1240

1K_0402_5%~D@

Q165

13

D

2N7002W-7-F_SOT323-3~D@

2

G

S

AUX_ON<36>

+PWR_SRC

2

G

12

R1233
100K_0402_5%~D

13

D

S

N21917830
Q161
2N7002W-7-F_SOT323-3~D

+PWR_SRC

12

R1230
100K_0402_5%~D

R1235

470K_0402_5%~D

12

ENAB_3VLAN <28>

13

D

Q159

2

G

2N7002W-7-F_SOT323-3~D

200K_0402_5%~D

S

12

R1237

4700P_0402_25V7K~D@

C1425

1

2

Discharg Circuit

+1.25V_RUN+VCC_CORE +0.9V_DDR_VTT +3.3V_RUN +1.5V_RUN +1.05V_VCCP +GFX_PWR_SRC +2.5 V _RUN +5V_RUN

12

R1241

30_0805_5%~D@

2N7002W-7-F_SOT323-3~D@

Z4005

13

D

RUN_ON_5V#

A A

Q166

2

G

S

12

R1242

30_0805_5%~D@

2N7002W-7-F_SOT323-3~D@

Z4006

13

D

Q167

2

G

S

12

R1243

30_0805_5%~D@

2N7002W-7-F_SOT323-3~D@

Z4007

13

D

Q168

2

G

S

12

R1244

30_0805_5%~D@

2N7002W-7-F_SOT323-3~D@

Z4008

13

D

Q169

2

G

S

12

R1245

30_0805_5%~D@

2N7002W-7-F_SOT323-3~D@

Z4009

13

D

Q170

2

G

S

2

G

12

R1246
150_0805_5%~D

Z4010

13

D

Q171

S

12

R1247

30_0805_5%~D@

2N7002W-7-F_SOT323-3~D

2

2N7002W-7-F_SOT323-3~D@

Z4011

13

D

Q172

G

S

12

R1248

30_0805_5%~D@

2N7002W-7-F_SOT323-3~D@

Z4012
13

D

Q173

2

G

S

12

R1249

1K_0402_5%~D@

Z4013

Q174

13

D

2N7002W-7-F_SOT323-3~D@

2

G

S

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, M /B LA-3751P

401490

38 48Wednesday, March 28, 2007

1

A

of

5

4

3

2

1

1.25V_RUN_PWRGD<43>

2.5V_RUN_PWRGD<15>

D D

+5V_RUN

C1430

1

2

+3.3V_RUN

C1432

1

C C

2

+3.3V_SUS

C1435

1

2

2 1

0.1U_0402_16V4Z~D
RB751V_SOD323-2~D

2 1

0.1U_0402_16V4Z~D
RB751V_SOD323-2~D

2 1

0.1U_0402_16V4Z~D
RB751V_SOD323-2~D

D41

D42

D43

200K_0402_5%~D

12

C1431

R1256

200K_0402_5%~D

12

C1433

R1260

200K_0402_5%~D

12

C1436

R1264

2200P_0402_50V7K~D

1

2

2200P_0402_50V7K~D

1

2

2200P_0402_50V7K~D

1

2

R1255

1 2

10K_0402_5%~D

R1259

1 2

10K_0402_5%~D

R1263

1 2

10K_0402_5%~D

2

2

2

1.5V_RUN_PWRGD<44>

1.05V_RUN_PWRGD<44>

GFX_CORE_PWRGD<18>

+5V_ALW

E

3

Q175

B

MMBT3906WT1G_SC70-3~D

C

1

R1257

1 2

4.7K_0402_5%~D

+3.3V_ALW

E

3

Q177

B

MMBT3906WT1G_SC70-3~D

C

1

R1261

1 2

4.7K_0402_5%~D

+3.3V_ALW

E

3

Q180

B

MMBT3906WT1G_SC70-3~D

C

1

200K_0402_5%~D

RB751V_SOD323-2~D

12

R1265

D44

2 1

2

B

2

B

1 2

R1250 0_0402_5%~D

R1251 0_0402_5%~D@

R1252 0_0402_5%~D

R1253 0_0402_5%~D

R1620 0_0402_5%~D

C

Q176
MMST3904-7-F_SOT323-3~D

E

3 1

C

Q178
MMST3904-7-F_SOT323-3~D

E

3 1

+3.3V_ALW

8

P

A3Y

G

U71C
74LVC3G14DC_VSSOP8~D

4

12

12

12

12

5

+3.3V_SUS

20K_0402_5%~D

+3.3V_ALW

12

R1254

A1Y

0.01U_0402_16V7K~D

C1429

1

2

1.5V_3.3V_5V_RUN_PWRGD <35>

C1427

1 2

8

0.1U_0402_16V4Z~D

P

7

G

U71A
74LVC3G14DC_VSSOP8~D

4

+3.3V_ALW

8

P

A6Y

G

U71B
74LVC3G14DC_VSSOP8~D

4

3.3V_5V_SUS_PWRGD

R1258

2

RUN_ON<18,36,38>

1 2

0_0402_5%~D

SUS_ON<36,38>

+3.3V_ALW

1

IN1

2

IN2

+3.3V_ALW

10

IN1

9

IN2

C1428

1 2

0.1U_0402_16V4Z~D

14

U72A
74VHC08MTCX_NL_TSSOP14~D

P

3

OUT
G

7

4
5

14

P

8

OUT
G

U72C
74VHC08MTCX_NL_TSSOP14~D

7

+3.3V_ALW

14

P

IN1

6

OUT

IN2

G

U72B
74VHC08MTCX_NL_TSSOP14~D

7

RUNPWROK

RUNPWROK <18,35,36,45>

SUSPWROK <15>

+5V_SUS

B B

A A

C1437

1

2

D45

2 1

0.1U_0402_16V4Z~D
RB751V_SOD323-2~D

200K_0402_5%~D

12

C1438

R1267

2200P_0402_50V7K~D

1

2

R1266

1 2

10K_0402_5%~D

+5V_ALW

E

3

Q181

B

MMBT3906WT1G_SC70-3~D

2

C

1

200K_0402_5%~D

12

R1268

D46

2 1

RB751V_SOD323-2~D

+3.3V_SUS

2

G

12

R1262
100K_0402_5%~D

13

D

S

ICH_PWRGD#
Q179
2N7002W-7-F_SOT323-3~D

ICH_PWRGD <10,22>

ICH_PWRGD# <15>

200K_0402_5%~D

12

R1269

IMVP_PWRGD<22,36,45>
RESET_OUT#<36>

+3.3V_ALW

U72D

14

74VHC08MTCX_NL_TSSOP14~D

13

P

IN1

OUT

12

IN2

G

7

11

ICH_PWRGD

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, M/B LA-3751P

401490

39 48Wednesday, March 28, 2007

1

A

of

5

HEX STANDOFF

STAND1

1

HEX_STANDOFF~D@

D D

1

HEX_STANDOFF~D@

STAND2

1

HEX_STANDOFF~D@

STAND3

1

HEX_STANDOFF~D@

STAND4

Fiducial Mark

FD1

1

SMD40M80

H6

H5
C256D126@

C C

1

H16
C276D110@

1

H18

C315D126@

C276D126@

1

1

H15

H20

TC315BC197D110@

C276D110@

1

1

H27
C315D126@

FIDUCAL

1

FD2

1

H29
C276D110@

1

FD3

1

SMD40M80

H30

H26

C276D126@

C315D126@

1

H13
C236D126@

1

FD4

1

FIDUCAL

H7
TC236BC315D118@

1

1

H22

H11

TC354BC276D126@

C276D126@

1

1

4

H9

H1
C315D91@

1

H19
O531X571D452X492@

1

H2

C315D91@

C315D91@

1

1

H3

H10

C315D110@

C315D91@

1

1

3

MY1

MYLAR(ZZZ)

1

NC

MYLAR_DIMMA~D@

MY3

MYLAR(ZZZ)

1

NC

MYLAR_DIMMB~D@

MY4

MYLAR(ZZZ)

1

NC

MYLAR_MINIPCI~D@

CABLE2

Cable

1

NC

BlueTooth Cable@

MY2

MYLAR(ZZZ)

1

NC

SD_MINIPCI~D@

TAPE

CONDUCTIVE
TAPE(ZZZ)

1

NC

CONDUCTIVE_TAPE~D@

ZZZ

LOG LOW
GASKET(ZZZ)

1

NC

LOG_LOW_GASKET~D@

CABLE3

Cable

1

NC

Switch Board Cable@

2

BRKT

IO BRACKET(ZZZ)

1

NC

IO_BRACKET~D@

RUBER

SD_RUBBER (ZZZ)

1

NC

SD_RUBBER~D@

COVER

RJ11_RUBBER (ZZZ)

1

NC

RJ11_RUBBER~D@

CABLE5

Cable

1

NC

Media Board Cable@

1

PCB

BARE PCB

1

NC

Converse_LA-3751P_REV0_M/B~D

CABLE1

Cable

1

NC

17" LCD Caxil Cable@

CABLE4

Cable

1

NC

RJ11 MDC Cable@

CABLE6

Cable

1

NC

LED FFC Cable@

H25
TC276BC197D110

3@

1

VGA Standoffs

H28
O236X134D236X134N@

1

H14
TC276BC197D110

3@

1

H4
C134D134N@

H17
TC276BC197D110

3@

1

1

MDC Standoff

H32
TC236BC114D110@

1

H21
C276D146

1

H12
C315D102

Keyboard
Standoff for
Zanzibar

Power SW Support
Standoff

H23
C275D102

1@

1

1@

1

H31
TP276@

1

H8
O531X571D452X492@

1

H24

B B

TC276BC197D110

3@

1

A A

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, M /B LA-3751P

401490

1

40 48Wednesday, March 28, 2007

A

of

5

4

+3.3V_ALW

3

2

1

ESD Diodes

2

PD1

PR2

1 2

3

1

PR3

100_0402_5%~D

1 2

D D

PC2

Battery Connector

PJBAT1
SUYIN_200028MR009G502ZL~D

12

2200P_0402_50V7K~D

10
11

BATT_PRES#

GND
GND

BATT1+

BATT2+
SMB_CLK
SMB_DAT

SYSPRES#

BATT_VOLT

BATT1­BATT2-

1
2
3
4
5
6
7
8
9

Z4304
Z4305
Z4306

DA204U_SOT323~D @

100_0402_5%~D

PD2
DA204U_SOT323~D @

2

3

1

PR4

100_0402_5%~D

1 2

3

PD3

100_0402_5%~D

1 2

2

3

2

12

PL1

1 2

PL2

1 2

FBMA-L18-453215-900LMA90T_1812~D

PD4

1
DA204U_SOT323~D @

PR5

1

DA204U_SOT323~D @

PBAT_SMBCLK <36>
PBAT_SMBDAT <36>

PBAT_ALARM# <35>

FBMA-L18-453215-900LMA90T_1812~D

PC1

0.1U_0603_25V7K~D

+VCHGR

+3.3V_ALW

12

PR1

10K_0402_1%~D

PBAT_PRES# <35>

PR8

33_0402_5%~D

1 2

PD5

DA204U_SOT323~D

+5V_ALW

3

2

1

+5V_ALW

12

PR10

10K_0402_1%~D

PR12

1 2

10K_0402_5%~D @

+3.3V_ALW

PR6

2.2K_0402_5%~D

PD7

@

1 2

+5V_ALW

DA204U_SOT323~D

PS_ID <36>

2

3

1

PSID_DISABLE# <35>

C C

PR7

@

1 2

0_0402_5%~D

GPIO Input from EC

Z-series AC Adaptor
Connctor

PJPDC1
TYCO_1566065-2~D

9

GND_4

8

B B

GND_3

7

GND_2

6

GND_1

MH1

MH2

Low_PWR

DC+_1
DC+_2

DC-_1
DC-_2

1
2
3
4
5

1

PD9

@

2

+DCIN_JACK

-DCIN_JACK

PL3

BLM18BD102SN1D 0603

FBMA-L18-453215-900LMA90T_1812~D

FBMA-L18-453215-900LMA90T_1812~D

VZ0603M260APT_0603

PL5

1 2

1

PD8

@

2

1 2

PL6

AC_OFF<36>

12

VZ0603M260APT_0603

PC8

12

0.1U_0603_25V7K~D

@

IMD2AT-108_SC74-6~D

PQ4B

12

2

PR15

0_0402_5%~D

@

16

5

IMD2AT-108_SC74-6~D
PQ4A

@

+DC_IN

PC3

43

@

+DC_IN

FDS6679AZ_SO8~D

1
2
3 6

12

1 2

PR11

240K_0402_5%~D

0.47U_0805_25V7K~D

DOCK_PSID<34>

PQ2

PR16

47K_0402_1%~D

DC_IN+ Source

8
7

5

4

12

PC4

+DC_IN_SS

12

12

12

PC5

PC6

PR14

0.1U_0603_25V7K~D

0.1U_0603_25V7K~D

0.1U_0603_25V7K~D

12

PC7

4.7K_0805_5%~D
10U_1206_25VAK~D

2

3

PR9

@

1

PD6
SM24.TC_SOT23-3

12

1 2

100K_0402_1%~D

PR13

1 2

15K_0402_1%~D

PQ1

D

1 3

G

2

FDV301N_NL_SOT23-3~D

C

PQ3

2

B

MMST3904-7-F_SOT323~D

E

3 1

S

A A

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, M/B LA-3751P

401490

1

41 48Wednesday, March 28, 2007

A

of

+5V_ALWP

5

4

3

2

1

Iocp=Vlimit /Rds on + dI/2
dI=(Vin-Vout)*(Vout/Vin)/f*L =1.96A
Vlimit=Ibi*PR26/10=6.125u*150K/10=0.92V
Iocp min =0.92/ 7.25m*1.3 + 1.96/2 =10.73A

PJP1

+PWR_SRC

D D

1 2

PAD-OPEN 4x4m

+DC1_PWR_SRC

PC13

12

12

PC14

0.1U_0805_50V7K

2200P_0402_50V7K~D

+5 Volt +/-5%
Thermal Design Current: 7.2A
Peak current: 9.65A
OCP min:10.73A

8

PQ5

PQ7

PJP5

PJP6

D6D5D7D

S

1

123

S

2

786

G

S

3

5

4

4

PR34

2K_0402_5%~D

PR38

0_0402_5%~D

+5V_ALW

+3.3V_ALW

12

12

4

C C

+5V_ALWP

1

+

PC26

2

330U_D3L_6.3VM_R25~D

B B

PR35

@

+3.3V_ALWP

+3.3V_ALWP

A A

100K_0402_1%~D

PR39

100K_0402_1%~D

PR28

@

0_0402_5%~D

1 2

12

PC28

0.1U_0402_10V7K~D

PR32

0_0402_5%~D

1 2

GNDA_3V5V

ALW_PWRGD_3V_5V<36>

PR36

12

1 2

0_0402_5%~D

12

3V5V_POK2

5

FDS8880_NL_SO8~D

PL8

4.7U_HMU1356-4R7-R_10A~D

FDS6676AS_NL_SO8~D

THERM_STP#<15>

3V5V_POK1

+5V_ALWP

+3.3V_ALWP

12

ALWON<36>

1 2

PAD-OPEN 4x4m

1 2

PAD-OPEN 4x4m

+3.3V_ALWP/ +5V_ALWP/ +5V_ALW2 / +15V_ALWP/+15V_SUBWOOFERP

Ton=GND 400KHz/500KHz

+5V_VCC1

PR19

@

10_0603_5%~D

12

12

PC20

1U_0603_10V6K~D

12

PR25

1 2

12

PC25

0.1U_0603_25V7K~D

0_0402_5%~D
PR22

@

GNDA_3V5V

200K_0402_1%~D

32
31

1 2

30

PR27 0_0402_5%~D

29

3V5V_POK2

28

EN_3V_5VEN_3V_5V

27

+3.3V_ALW_UGATE

26

+3.3V_ALW_PHASE

25

PR31

1_0603_5%~D

1 2

+3.3V_ALW_LGATE

PJP3

1 2

PAD-OPEN1x1m

+3.3V_ALWP
Iocp=Vlimit /Rds on + dI/2
dI=(Vin-Vout)*(Vout/Vin)/f*L =1.82A
Vlimit=Ibi*PR25/10=6.125u*200K/10=0.123V
Iocp min =0.123/ 7.25m*1.3 + 1.82/2 =13.96A

12

12

PC16

PC15

10U_1206_25VAK~D

10U_1206_25VAK~D

12

PC23

@

0.1U_0402_10V7K~D

(100mA,20mils ,Via NO.=1)

+15V_ALW

GNDA_3V5V

GNDA_3V5V

PR37

1 2

200K_0402_5%

PAD-OPEN1x1m

+5V_ALW_UGATE

+5V_ALW_PHASE

+5V_ALWP

12

PC32

0.1U_0603_25V7K~D

PJP4

12

PR18

PR17

PC18

GNDA_3V5V

0.1U_0603_25V7K~D

BAT54SW-7-F_SOT323-3~D

BAT54SW-7-F_SOT323-3~D

0_0805_5%

1 2

+3.3V_ALW2

12

@

0.1U_0603_25V7K~D

GNDA_3V5V

PC175

@

12

PR26

150K_0402_1%~D

1 2

12

PC24

1_0603_5%~D

0.1U_0603_25V7K~D
1 2

+5V_ALW_LGATE

2
3

PD10

2
3

PD11

+15V_ALWP

0_0805_5%

1 2

12

PC19

0.1U_0603_25V7K~D

+5V_ALWP

3V5V_POK1

PR30

PC30

0.1U_0603_25V7K~D
1 2

1

PC33

0.1U_0603_25V7K~D

1

1 2

PC34

0.1U_0603_25V7K~D

PJP2

8

7

LDOREFIN

BYP
OUT1
FB1
ILIM1

ISL6236IRZA_QFN32~D

POK1
EN1
UGATE1
PHASE1

BOOT117LGATE118PVCC19SECFB20GND21PGND22LGATE223BOOT2

PAD

33

PD12

1

BAT54CW_SOT323~D

3

2

PR40

12

PR41

GNDA_3V5V

3

1 2

PAD-OPEN1x1m

EN_3V_5V

6

2

3

4

5

VIN

LDO

VCC

VREF3

EN_LDO

PU1

GNDA_3V5V

PC31

+5V_ALW2

1U_0603_10V6K~D

1 2

39.2K_0402_1%~D

12

PC17

4.7U_0805_6.3V6K
PR20

0_0402_5%~D@

1 2

PR21

0_0402_5%~D

1 2

PC21

0.1U_0603_25V7K~D
1 2

PR23

@

1 2

0_0402_5%~D

1

REF

TON

REFIN2

ILIM2

OUT2

SKIP#

POK2

EN2

UGATE2

PHASE2

24

+3.3V_ALW_BOOT

12

GNDA_3V5V

+5V_ALW2

9
10
11
12
13
14
15
16

GNDA_3V5V

+5V_ALW_BOOT

200K_0402_1%~D

12

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

PR24

12

0_0402_5%~D

GNDA_3V5V

GNDA_3V5V

12

12

PC12

10U_1206_25VAK~D

PC9

12

12

PC10

PC11

0.1U_0805_50V7K

2200P_0402_50V7K~D

10U_1206_25VAK~D

3.3 Volt +/-5%
Thermal Design Current: 8.6A
Peak current: 12.3A
OCP min:13.96A

12

PC22

@

0.1U_0402_10V7K~D

4

PQ6
S TR BSC079N03S G 1N PG-TDSON-8

3 5

241

3.0U_HMP1362-3R0-R_17A~D

786

5

PQ8
FDS6676AS_NL_SO8~D

123

PL9

12

12

PR29

0_0402_5%~D

12

PR33

@

0_0402_5%~D

GNDA_3V5V

+3.3V_ALWP

1

12

PC29

0.1U_0402_10V7K~D

+

PC27

2

330U_D3L_6.3VM_R25~D

DELL CONFIDENTIAL/PROPRIETARY

Title

Size Document Number Rev

2

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, M/B LA-3751P

401490

42 48Wednesday, March 28, 2007

1

A

of

5

4

3

2

1

1.8V/1.25V/0.9V VTT

PJP7

+PWR_SRC

D D

1 2

PAD-OPEN 4x4m

12

PC35

10U_1206_25VAK~D

12

12

PC36

PC37

0.1U_0603_25V7K~D

10U_1206_25VAK~D

Place these CAPs
close to FETs

12

PC38

2200P_0402_50V7K~D

+1P8V_1P23V_PWRSRC

1.8 Volt +/-5%
Thermal Design Current:4.2A
Peak current: 5.7A
OCP min:8.61A

+1.8V_SUSP

C C

1

1

+

+

PC48

PC47

2

330U_D2E_2.5VM_R15~D

B B

PC49

2

0.1U_0402_10V7K~D

330U_D2E_2.5VM_R15~D

1.4UH_HMU1350-1R4PF_15A_20%~D

12

12

PR53

PC53

@

27.4K_0603_1%~D

12

PR59

17.4K_0402_1%~D

FDS8880_NL_SO8~D

3

PL10

FDS6676AS_NL_SO8~D

12

1000P_0402_50V7K~D

GNDA_DC2

PQ9

12

PQ11

PJP8

12

PAD-OPEN1x1m

8

S

1

123

D6D5D7D

4

G

S

S

3

2

786

5

DDR_ON<36>

4

1.8V_SUS_PWRGD<36>

+1.8V
Iocp=Vlimit /Rds on + dI/2
dI=(Vin-Vout)*(Vout/Vin)/f*L =2.92 A

+5V_ALW

Vlimit=Ibi*PR50/10=6.125u*110K/10=0.0674V
Iocp min =0.0674/(7.25m*1.3)+2.92/2 =8.61A

+1.8V_SUS

0.9V_DDR_VTT_ON<36>

A A

+1.8V_SUSP

+0.9V_P

PJP11

1 2

PAD-OPEN 4x4m

PJP12

2 1

PAD-OPEN 2x2m~D

5

+1.8V_SUS

+0.9V_DDR_VTT

DDR_ON<36>

PJP10

2 1

PAD-OPEN 2x2m~D

4

12

PC60

1 2

PC61

0.1U_0603_25V7K~D

10U_0805_6.3V6M~D

Ton=REF 400KHz/300KHz

12

PC45

@

0.1U_0402_10V7K~D

+3.3V_ALW

PR60

1 2

20K_0402_5%~D

GNDA_DC2

PR50

110K_0402_1%

GNDA_DC2

1 2

1 2

1.8V_UGATE

PR52

PC54

0.1U_0603_25V7K~D

+5V_ALW

1 2

PC55

1.8V_PHASE

1U_0603_10V6K~D

0_0402_5%~D

0.9 Volt +/-5%

PR55

0_0603_5%~D

1 2

10_0603_5%~D

12

10
11
12
13
14
15
16

PR57

@

Thermal Design Current: 0.7A
Peak current: 1A

V_DDR_MCH_REF

PU3

10

VIN

2

VLDOIN

1

VDDQSNS

7

S3

9

S5

TPS51100DGQRG4_MSOP10~D

VTTSNS

VTTREF

PGND

GND

3

VTT

5
6
4

8
11

BP

PC59

1U_0603_10V6K~D

GND

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

9

BYP
OUT1
FB1
ILIM1
POK1
EN1
UGATE1
PHASE1

GNDA_DC2

1.8V_LGATE

12

+0.9V_P

PC57

1 2

PC56

10U_0805_6.3V6M~D

PR42

0_0805_5%

1 2

+5V_VCC3

@

8

6

7

5

VIN

LDO

VREF3

LDOREFIN

PU2

ISL6236IRZA_QFN32~D

BOOT117LGATE118PVCC19SECFB20GND21PGND22LGATE223BOOT2

PAD

33

+5V_VCC3

GNDA_DC2

12

1U_0603_10V6K~D

GNDA_DC2GNDA_DC2

PC58

1 2

1 2

10U_0805_6.3V6M~D

3

PR44

4

EN_LDO

PR43

0_0805_5%

1 2

@

1 2

PC43

1 2

0_0402_5%~D

2

1

REF

VCC

TON

24

1.25V_LGATE

0.1U_0603_25V7K~D

1 2

PR45

1 2

PR47

@

0_0402_5%~D

REFIN2

ILIM2
OUT2
SKIP#
POK2

EN2
UGATE2
PHASE2

PR54

0_0603_5%~D

1 2

VGA_ISL6236_REF

12

PC44

0.1U_0603_25V7K~D

GNDA_DC2

32
31

1 2

30

PR51 0_0402_5%~D

29

1 2
28
27

1.25V_UGATE

26

1.25V_PHASE

25

PC52

1 2

0.1U_0603_25V7K~D

PR49

51.1K_0402_1%~D

0.1U_0402_10V7K~D

1 2

1 2

GNDA_DC2

@

PC46

PR46

10K_0402_1%~D

PR48

12

16.9K_0402_1%~D

GNDA_DC2

+3.3V_SUS

+3.3V_ALW

4

2

G1

G2

@
100K_0402_1%~D

100K_0402_1%~D

0_0402_5%~D

3

+1.25V
Iocp=Vlimit /Rds on + dI/2
dI=(Vin-Vout)*(Vout/Vin)/f*L =1.18 A
Vlimit=Ibi*PR49/10=6.13u*51.1K/10=0.0313V
Iocp min =0.0313/(16.5m*1.3) + 1.18/2 =2.02A

PGND and GND sholud be tied
together at one point near the GND Pin

2

12

PC40

10U_1206_25VAK~D

Place these CAPs
close to FETs

PQ10

5

FDS6982AS_NL_SO8~D

D16D1

S1
D2
D2

S2

1

PR56

PR58

12

12

PC41

PC39

10U_1206_25VAK~D

12

PC42

0.1U_0603_25V7K~D
2200P_0402_50V7K~D

1.25 Volt +/-5%
Thermal Design Current: 1A
Peak current: 1.28A
OCP min:2.02A

3

3.3UH_MPL73-3R3_6A_20%~D

7
8

12

12

+1.25V_RUNP +1.25V_RUN

PL11

12

1.25V_RUN_PWRGD <39>

1.25V_RUN_ON <36>

PJP9

1 2

PAD-OPEN 4x4m

1

+

PC50

2

220U_D2E_2.5VM_R15~D

DELL CONFIDENTIAL/PROPRIETARY

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.
SCHEMATIC, M /B LA-3751P

401490

1

43 48Wednesday, March 28, 2007

+1.25V_RUNP

PC51

12

0.1U_0402_10V7K~D

A

5

4

3

2

1

+1.05V
Iocp=Vlimit /Rds on + dI/2

+DC2_PWR_SRC

PJP13

+PWR_SRC

D D

1 2

PAD-OPEN 4x4m

12

12

PC63

PC62

10U_1206_25VAK~D

12

PC64

0.1U_0603_25V7K~D
2200P_0402_50V7K~D

1.5 Volt +/-5%
Thermal Design Current: 2A
Peak current: 2.82A
OCP min: 3.44A

C C

+1.5V_RUN_P

3.3UH_MPL73-3R3_6A_20%~D

1

12

+

PC79

PC78

330U_D2E_2.5VM_R9

B B

2

10U_1206_6.3V7K

GNDA_1P5V_1P05V

PR72

PC80

0.1U_0402_10V7K~D

1 2

0_0402_5%~D

1 2

@

PR73

0_0402_5%~D

1 2

@

PL13

12

578

PQ13

4

GNDA_1P5V_1P05V

100K_0402_1%~D

GNDA_1P5V_1P05V

SI4800BDY-T1_SO8~D

3 6

241

8

D6D5D7D

G

PQ15

S

S

S

3

2

1

SI4810BDY-T1-E3_SO8~D

12

PR70

1 2

PC72

@

0.1U_0402_10V7K~D

+5V_ALW

+1.5V
Iocp=Vlimit /Rds on + dI/2
dI=(Vin-Vout)*(Vout/Vin)/f*L =2.1 A
Vlimit=Ibi*PR70/10=6.125u*100K/10=0.06V
Iocp min =0.06/(20m*1.3) + 2.1/2 =3.44A

+1.5V_RUN_P +1.5V_RUN

A A

PJP17

1 2

PAD-OPEN 4x4m

Ton=VCC 200KHz/300KHz

PR61

0_0805_5%

1 2

+5V_VCC2

PR63

0_0402_5%~D

PC70

0.1U_0603_25V7K~D

REF

1 2

1 2

GNDA_1P5V_1P05V

PR67

0_0402_5%~D

1 2

10
11

1.5V1.05V_POK1

1.5V_UGATE

1.5V_PHASE

12
13

EN1 EN2

14
15
16

PC81

1 2

GNDA_1P5V_1P05V

0.1U_0603_25V7K~D
PR74

1_0603_1%~D

1 2

1.5V_LGATE

12

PC84

1U_0603_10V6K~D

9

BYP
OUT1
FB1
ILIM1
POK1
EN1
UGATE1
PHASE1

PAD

33

PR76

@

10_0603_5%~D

8

6

7

5

VIN

LDO

VREF3

LDOREFIN

PU4

ISL6236IRZA_QFN32~D

BOOT117LGATE118PVCC19SECFB20GND21PGND22LGATE223BOOT2

12

0_0402_5%~D@

1 2

0_0402_5%~D@

2

3

1

4

REF

VCC

TON

EN_LDO

REFIN2

OUT2
SKIP#
POK2

UGATE2
PHASE2

24

1_0603_1%~D

GNDA_1P5V_1P05V

+5V_VCC2

12

PC83

1U_0603_10V6K~D

GNDA_1P5V_1P05V

PR66

PR68

ILIM2

EN2

1 2

GNDA_1P5V_1P05V

PR62

0_0805_5%

1 2

1 2

PC69

0.1U_0603_25V7K~D

12

GNDA_1P5V_1P05V

REFIN2_1_05

32
31

PR69 267K_0402_1%~D

30

PR71 0_0402_5%~D

29

1.5V1.05V_POK2

28
27
26
25

PC82

PR75

1.05V_LGATE

+3.3V_RTC_LDO

12

1 2

PC71

0.01U_0402_25V7K~D

1 2

12

1.05V_UGATE

1.05V_PHASE

1 2

0.1U_0603_25V7K~D

PJP15

PAD-OPEN1x1m

OK to Short if CAD
System can Support

PR64

@

PR65

0_0402_5%~D

0_0402_5%~D

PC73

12

0.1U_0402_10V7K~D

@

GNDA_1P5V_1P05V

GNDA_1P5V_1P05V

12

12

GNDA_1P5V_1P05V

1.5V1.05V_POK2

1.5V1.05V_POK1

+1.5V_RUN / +1.05V_VCCP / +3.3V_ALW / +3.3V_RTC_LDO

dI=(Vin-Vout)*(Vout/Vin)/f*L =3.31A
Vlimit=Ibi*PR69/10=6.125u*267K/10=0.163V
Iocp min =0.163/(20m*1.3) + 3.31/2 =7.95A

12

12

12

12

PC65

PC66

PC67

10U_1206_25VAK~D

10U_1206_25VAK~D

8

D6D5D7D

4

PR78

@

100K_0402_1%~D

PQ12

G

S

S

S

3

2

1

SI4800BDY-T1-E3_SO8~D

1 2

578

PQ14

3 6

241

FDS6690AS_NL_SO8~D

+3.3V_SUS

12

PR79

1 2

100K_0402_1%~D

@

+1.05V_VCCP_P +1.05V_VCCP

1.05 Volt +/-5%
Thermal Design Current: 5.3A
Peak current: 7.62A
OCP min:7.95A

PL12

1UH_MPLC0730L1R0_11A_20%~D

EN1

EN2

1.05V_RUN_PWRGD <39>

1.5V_RUN_PWRGD <39>

PJP14

1 2

PAD-OPEN 4x4m

PJP16

1 2

PAD-OPEN 4x4m

0.1U_0603_25V7K~D

PR77

0_0402_5%~D

1 2

PC68

2200P_0402_50V7K~D

PC74

1

+

2

330U_D2E_2.5VM_R9

1.5V_RUN_ON <36>

1.05V_RUN_ON <35>

+1.05V_VCCP_P

1

12

+

PC75

PC76

PC77

2

330U_D2E_2.5VM_R9

1 2

0.1U_0402_10V7K~D

10U_1206_6.3V7K

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, M /B LA-3751P

401490

1

44 48Wednesday, March 28, 2007

A

of

8

H H

G G

F F

E E

GNDA_VCORE

H_DPRSTP#<8,10,21>

DPRSLPVR<10,22>

H_PSI#<8>

D D

PWR_MON<15>

PC107

1U_0603_10V6K~D

GNDA_VCORE

RUNPWROK<18,35,36,39>

IMVP_VR_ON<36>

10KB_0603_1%_ERTJ1VG103FA~D

C C

B B

@

A A

GNDA_VCORE

0_0402_5%~D

2200P_0402_50V7K~D

0.015U_0402_16V7K

VID0<8>
VID1<8>
VID2<8>
VID3<8>
VID4<8>
VID5<8>
VID6<8>

PR104

10K_0402_5%~D

1 2

PH2

@

PR112

4.99K_0402_1%@

VSSSENSE<8>

PR117

332_0402_1%~D

220P_0402_50V8J~D

12

PR132

0_0402_5%~D

PR88

147K_0402_1%~D

12

PR90

@

12

PC97

@

12

PC103

12

0_0402_5%~D
0_0402_5%~D
0_0402_5%~D

0_0402_5%~D

12

PR109 0_0402_5%~D@

12

12

GNDA_VCORE

12

680P_0402_50V7K~D

1 2

PC120

1500P_0402_50V7K~D
PC123

1 2

8

IMVP6_PROCHOT#<35>

PH1

@

470KB_0402_5%_NCP15WM474J03RB~D

PR93

PR94
PR96
PR98

PR102

PR107

@
0_0402_5%~D

12

1 2
PC117

12

0_0402_5%~D

12

PR95

12

0_0402_5%~D

12

PR97

12

0_0402_5%~D

12

PR99

12

0_0402_5%~D

PR101

499_0402_1%~D

12

12

PR108 0_0402_5%~D

VCCSENSE<8>

PC108 1000P_0402_50V7K~D

12

PC113 1000P_0402_50V7K~D

12

PR114
0_0402_5%~D

PR120

12

1.69K_0402_1%~D

PR123

82.5K_0402_1%~D

PC124

12

1000P_0402_50V7K~D

PR130

6.34K_0402_1%~D

0.01U_0402_16V7K~D

+5V_ALW

PR83

10_0603_5%~D

PC96

1U_0603_10V6K~D

GNDA_VCORE

12

12

CLK_ENABLE#

12

PR118

0_0603_5%~D

PR121

0_0402_5%~D

12

12

7

1 2
12

12

12

12

12

PR131

PC130

GNDA_VCORE

7

PR89

1K_0402_1%~D

0_0603_5%~D

12

1

2

GNDA_VCORE

12

PR91

@

13K_0402_5%~D
4

VR_TT#

3

RBIAS

5

NTC

6

SOFT

28

VID0

29

VID1

30

VID2

31

VID3

32

VID4

33

VID5

34

VID6

37

DPRSTP#

36

DPRSLPVR

1

PSI#

2

PMON

38

CLK_EN#

35

VR_ON

12

VSEN

13

RTN

11

VDIFF

10

FB

9

COMP

8

VW

41

GND

GNDA_VCORE

10.5K_0402_1%

330P_0402_50V7K~D

12

PC127

@

0.01U_0402_25V7K~D

PR125

PC125

1000P_0402_50V7K~D

PC93

19

12

VSS

DROOP

14

12

+CPU_PWR_SRC

PR80
10_0603_5%~D

1 2

+3.3V_RUN

39

18

20

VIN

3V3

VDD

PWM1

ISEN1

PU6

PWM2

ISEN2

ISL6260CCRZ_QFN40~D

FCCM

PWM3

ISEN3

OCSET

VSUM

DFB15VO

1K_0402_1%~D

12

12

PC128

@

1000P_0402_50V7K~D

PR87

1.91K_0603_1%~D

1 2

40

PGOOD

27

23

26

22

24

25

21

7

17

16

PR116

4.53K_0402_1%~D

VO

PR126

12

GNDA_VCORE

6

VSUM

12

2

1

PC118

0.33U_0603_10V7K

PC119

0.01U_0402_16V7K~D

2

PC129

0.1U_0402_16V7K~D

1

6

IMVP_PWRGD <22,36,39>

PR110

@
226K_0402_1%~D

PR111

13.7K_0402_1%

12

PR113

PC116

1 2

2.43K_0402_1%~D

0.033U_0402_16V7K~D

1

12

2

PH3

6.8KB_0603_5%_ERTJ1VR682J~D

5

CPU Core
Thermal Design Current: 36A
Peak current: 44A
OCP min: 65A

+5V_ALW

12

PC91

1U_0603_10V6K~D

12

GNDA_VCORE

12

12

PR119

@

17.8K_0402_1%

12

PR124

15K_0402_1%~D

1

2

@

12

PC126

PR133

@

0.1U_0402_16V7K~D

5

+5V_ALW

12

PC102

+5V_ALW

12

PC114

PWR_ MON <15>

22.1K_0402_1%

PU5

5

BOOT

VCC

6

FCCM

UGATE

2

PWM

PHASE

3

LGATE

GND

ISL6208CRZ-T_QFN8~D

PU7

1U_0603_10V6K~D

5

VCC

6

FCCM

UGATE

2

PWM

PHASE

3

LGATE

GND

ISL6208CRZ-T_QFN8~D

PU8

5

BOOT

VCC

1U_0603_10V6K~D

6

FCCM

UGATE

2

PWM

PHASE

3

LGATE

GND

ISL6208CRZ-T_QFN8~D

BOOT

4

8

PQ16

SI4392DY_SO8~D

1

PR81

0_0603_5%~D

1

UGATE1

8
7
4

PR92
0_0603_5%~D

1
8
7
4

PR115

0_0603_5%~D

1

UGATE3

8
7
4

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

0.22U_0603_10V7K~D

12

1 2

LGATE1

0.22U_0603_10V7K~D

12

1 2

UGATE2

LGATE2

PC115

0.22U_0603_10V7K~D
1 2

12

LGATE3

4

PC92

3

D

2

G

S

FDMS8670S_SO8~D

1

PQ20

PC104

2

SI4392DY_SO8~D

3

D

2

G

S

FDMS8670S_SO8~D

1

8

PQ24

SI4392DY_SO8~D

1

3

D

PQ26

G

2

S

FDMS8670S_SO8~D

1

3

+CPU_PWR_SRC

12

PC86

D5D6D7D

G4S3S2S

PHASE1

3

D

PQ18

2

G

S

1

8

D5D6D7D

G4S3S2S

1

3

D

PQ22

2

G

S

1

D5D6D7D

G4S3S2S

3

D

G

S

1

12

PC95

@

PQ19

12

1500P_0603_25V7K~D

FDMS8670S_SO8~D

12

PC106

PQ23

@

12

1500P_0603_25V7K~D

FDMS8670S_SO8~D

12

PC122

@

PQ27

12

1500P_0603_25V7K~D

FDMS8670S_SO8~D

@

3

12

PC87

10U_1206_25VAK~D

0.1U_0603_25V7K~D

0.45UH_ETQP4LR45XFC_25A_-25+20%~D

10K_0402_1%~D

1 2

PR166

PR85

@

7.68K_0805_1%~D

2.2_1206_5%
1 2

VSUM

12

12

PC98

PC99

0.1U_0603_25V7K~D
2200P_0402_50V7K~D

PHASE2

PR163

@

2.2_1206_5%

1 2

VSUM

+CPU_PWR_SRC

PC109

0.45UH_ETQP4LR45XFC_25A_-25+20%~D

PHASE3

10K_0402_1%~D

1 2

PR164

PR128

2.2_1206_5%

7.68K_0805_1%~D

1 2

2

12

12

PC89

PC88

2200P_0402_50V7K~D

4
3

PR84

PC100

10U_1206_25VAK~D

10K_0402_1%~D

1 2

PR105

7.68K_0805_1%~D

12

PC110

10U_1206_25VAK~D

1
2

PR127

PC90

<BOM Structure>

10U_1206_25VAK~D

10U_1206_25VAK~D

PL14

1
2

PC94

0.22U_0603_10V7K~D
12

12

12

PC171

PC101

10U_1206_25VAK~D

10U_1206_25VAK~D

PL15

0.45UH_ET QP4LR45XFC_25A_-25+20%~D
4
3

PR103

0.22U_0603_10V7K~D

12

12

PC111

PC112

0.1U_0603_25V7K~D

10U_1206_25VAK~D

PL16

2200P_0402_50V7K~D

4
3

PC121

0.22U_0603_10V7K~D
12

DELL CONFIDENTIAL/PROPRIETARY

Title

Size Doc um e n t N u mb er Re v

Date: Sheet

2

FBMA-L18-453215-900LMA90T_1812~D

1

1

1

12

12

1
2

PC105

12

+

PC165

2

100U_25V_M~D

1 2

12

VO

12

PR122

10_0402_1%~D
1 2
12

PR129

0_0402_5%~D

VOVSUM

+VCC_CORE

+

PC167

2

100U_25V_M~D

PR82
10_0402_1%~D

PR86
0_0402_5%~D

+CPU_PWR_SRC

PR100
10_0402_1%~D

1 2

12

PR106
0_0402_5%~D

VO

12

PC170

10U_1206_25VAK~D

PC169

2

100U_25V_M~D

+

+VCC_CORE

+VCC_CORE

Compal Electronics, Inc.

SCHEMATIC, M/B LA-3751P

401490

PL20

@

1 2

PJP18

1 2

PAD-OPEN 4x4m

PJP19

1 2

PAD-OPEN 4x4m

1

+PWR_SRC

1

+

PC168

@

2

100U_25V_M~D

45 48Thursday, March 29, 2007

1

A

of

5

FDS6679AZ_SO8~D
PQ28

8

10K_0402_5%~D

13

D

PQ31

S

RHU002N06_SOT323-3~D

PR148

12

PC156

PC155

0.1U_0402_10V7K~D

7
5

PR139

2.2K_0402_5%~D

0.01U_0402_25V7K~D

12

PC147

@

12

+DC_IN_SS

D D

C C

B B

0.01U_0402_25V7K~D

GNDA_CHG

12

@
PC131
10U_1206_25VAK~D

PR143

49.9K_0402_1%~D
12

PC137

12

THRM_SMBCLK<15,36>

THRM_SMBDAT<15,36>

PR137
215K_0402_1%

1 2

ACAV_IN<15,18,36>

ISL88731_VDDP

PR141

ACAV_IN<15,18,36>

PR146

+5V_ALW

PC144

0.1U_0402_10V7K~D

GNDA_CHG

2

G

12

10K_0402_1%~D

12

15.8K_0402_1%~D

12

12

PR152

@

@

8.45K_0402_1%~D

Ref DES MAXIM INTERSIL

PR152 8.45K 0402 1% No STUFF
PC159 0.01uf o.1uF
PC155 0.1uf 0402 10V No STUFF
PC149 1.0uf 0603 10V No STUFF
PR137 365k 0402 1% 215k 0402 1%
PR153 0 0402 5% 10 0402 5%
PR136 0 0402 5% 10 0402 5%
PC157 No STUFF 0.22uf
PC134 No STUFF 0.22uf
PC147 0.01uf No STUFF
PC154 0.1uf 0402 10V No STUFF
PC145 220pf 0402 50V No STUFF
PD13 RB751V-40 No STUFF
PC146 3.3nf No STUFF
PR147 1 0603 1% 0 0603 5%
PR151 100 0402 5% 0 0402 5%
PC156 0.01uf 0.01uf
PC148 0.01uf 0.01uf
PD14 1SS355 No STUFF
PR150 1K_0603_1%~D No STUFF

A A

PR157 0 0402 5% 8.45K 0402 5%
PR148 10K 0402 5% 2.2K 0402 5%
PR165 1.8K 1206 5% No STUFF
PQ37 RHU002N06 No STUFF

5

ISL88731_ICM

<35>

ADAPT_TRIP_SET

ISL88731_VREF

PR157

8.45K_0402_1%~D

1 2

PR159

27.4K_0402_1%
1 2

PC159

GNDA_CHG GNDA_CHG

4

12

PR145

1 2

0_0402_5%~D

12

0.01U_0402_25V7K~D

12

0.1U_0402_10V7K~D

4

1
2
36

PR140
100K_0402_5%~D

12

12

ISL88731_ICM

ISL88731_VREF

PC154

@

GNDA_CHG

12

PC162

GNDA_CHG

12

0.1U_0402_10V7K~D

12

100P_0402_50V8K

1M_0402_1%~D

1 2

2

IN-

3

IN+

+5V_ALW

22

2
13
11
10

9
14

8

6

5

4

3

7

12
29

PR154

GNDA_CHG

4

G

P

8

PC136

1U_0805_25V4Z~D

GNDA_CHG

12

PC148

0.01U_0402_25V7K~D

PR161

20.5K_0402_1%~D

PR162

100_0402_1%~D

12

PC149

@

1U_0603_10V6K~D

12

PR156

32.4K_0402_1%~D

12

12

PC160

PC161

12

GNDA_CHG

4

100P_0402_50V8K

0.01U_0402_25V7K~D
GNDA_CHG GNDA_CHG GNDA_CHG GNDA_CHG

PU9

DCIN
ACIN
ACOK
VDDSMB
SCL
SDA
NC
ICM
VCOMP
NC
ICOMP

VREF

NC

GND
GND

PU10A
LM393DR_SO8~D

1

O

12

PC163

100P_0402_50V8K

3

PL17

@

FBM-L11-453215-900LMAT_1812~D

1 2

PL18

@

0.01_2512_1%~D
1
2

0.22U_0402_6.3V6K

1

ISL88731_TQFN28~D

4
3

12

10_0402_1%~D

PR136

PC134

1 2

27

28

NC

CSSP

PC164

0.01U_0402_25V7K~D

26

VCC

CSSN

25

BOOT

21

VDDP

24

UGATE

23

PHASE

20

LGATE

19

PGND

18

CSOP

17

CSON

15

VFB

16

NC

+5V_ALW +3.3V_ALW

PR158

PC158

@

12

GNDA_CHG GNDA_CHG GNDA_CHG

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

+PWR_SRC

PR134

FBM-L11-453215-900LMAT_1812~D

PR144
0_0603_5%~D

1 2

ISL88731_VDDP

PR147

0_0603_1%~D

12

PC145

@
220P_0402_50V7K~D

12

PQ35

100K_0402_1%~D

2

G

RHU002N06_SOT323-3~D

12

10P_0402_50V8J~D

1 2

PJP20

1 2

PAD-OPEN 4x4m

1U_0603_10V6K~D

12

PC138

PD13

@

CHG_UGATE

0.1U_0603_25V7K~D

12

CHG_LGATE

PR151

1 2

0_0603_5%~D

12

PR155

100K_0402_5%~D

13

D

S

@

PC135

1 2

PR142

4.7_0603_1%~D

1 2

PC139

1U_0603_10V6K~D

2 1

RB751V_SOD323~D

1 2

+VCHGR

GNDA_CHG

12

PR160
@

GNDA_CHG GNDA_CHG

PC132

2200P_0402_50V7K~D

1K_0402_5%~D

12

PC133

@

ADAPT_OC <35>

CHAGER_SRC

12

0.1U_0603_25V7K~D

GNDA_CHG

PC146

@

3300PF_0402_50V7K~D

PJP21

1 2

PAD-OPEN1x1m

+5V_ALW

5

IN+

6

IN-

12

578

8

P

G

4

PQ32

3 6

241

+VCHGR_B

4

G

7

O

PU10B
LM393DR_SO8~D

2

PQ36

FDS6679AZ_SO8~D

1
2
3 6

PQ29

FDS6679AZ_SO8~D

1
2
3 6

PR138

578

SI4800BDY-T1_SO8~D

8

D6D5D7D

S

S

S

3

2

1

8
7

5

4

8

+VCHGR

7
5

4
12

470K_0402_5%~D

PQ33

SI4800BDY-T1_SO8~D

3 6

241

1 2

5.6U_HMU1356-5R6_8.8A_20%~D

PQ34

SI4810BDY-T1-E3_SO8~D

PL19

PC140

+VCHGR_L

10_0402_1%~D

PR153

+DC_IN_SS

12

PC141

2200P_0402_50V7K~D

PR149

0.01_2512_1%~D
1
2

12

PC157

0.22U_0402_6.3V6K
1 2

12

12

PC143

PC142

12

10U_1206_25VAK~D

10U_1206_25VAK~D

0.1U_0603_25V7K~D

4
3

12

PC151

PC150

10U_1206_25V6M~D

0.1U_0603_25V7K~D

Maximum charging current is 6.24A

ADAPTER (W) TRIP current PR156 PR161 PR162 PR159
130W 6.43A 32.4k 20.5k 100 27.4k

Title

Size Document Number Rev

2

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, M/B LA-3751P

401490

1

+VCHGR

12

1

+5V_ALW

@

PD14

1 2

RB500V-40 TE-17_SOD323-2~D

@

PR150

1 2

1K_0603_1%~D

12

12

12

PC152

PC153

10U_1206_25V6M~D

10U_1206_25V6M~D

ACAV_IN<15,18,36>

@

1.8K_1206_5%
PR165

13

D

2

PQ37

G

S

@

RHU002N06_SOT323-3~D

46 48Thursday, March 29, 2007

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DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

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SCHEMATIC, M/B LA-3751P

401490

47 48Wednesday, March 28, 2007

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C C

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12

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Solution Description Rev.Page#

Request

16

B B

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A A

25

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.
SCHEMATIC, M /B LA-3751P

401490

1

48 48Wednesday, March 28, 2007

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