5
4
3
2
1
Power On Sequence (AC IN mod e)
ACIN
+5VA LW/+3V ALW
-->E C
+1.2 VALW
EC_R SMRST#
(PWR GD_SB)
ON_O FF
PWRB TN_OUT #
(PWR BTN#)
SLP_ S5#MCP6 7-->EC
SYS_ ONEC-- >PWR
+1.8 V/+0.9 V
MEM_ VLD
SLP_ S3#
SUSP #
+5VS /+3VS
+1.8 VS/+1. 2VS
MCP_ PWRGD
(PWR GD)
VR_O N
(CPU VDD_EN )
CPU_ CORE
VGAT E
(CPU _VLD)
VLDT _EN
(MCP VDD/HT _EN)
+1.2 V_HT
HT_V LD
(MCP VLD/HT _VLD)
CPUC LK/#
HT_C PU_PWR GD
(HT_ MCP_PW RGD)
KB_R ST#
LPC_ RST#
HTCP U_RST#
(HT_ MCP_RS T#)
10~1 2ms
>0ms
10~1 5ms
>0ms
>0ms
>0ms
50~7 3ms
>0ms
10~1 5ms
>0ms
>0ms
>0ms
max :70ms
1~12 8ms
1~10 0ms
D D
EC-- >MCP67
EC-- >MCP67
PU6- ->MCP6 7
C C
MCP6 7-->EC
EC-- >PWR
EC-- >MCP67
MCP6 7-->PU 11
B B
PU11 -->MCP 67
MCP6 7-->PW R
PWR- ->MCP6 7
MCP6 7-->CP U
EC-- >MCP67
A A
MCP6 7-->LP C
MCP6 7-->CP U
5
4
3
2
1
A
1 1
B
C
D
E
2 2
Compal Confidential
Schematics Document
AMD Turion/Sempron + Nvidia MCP67-MV
2007-01-12
3 3
4 4
A
B
Rev:0.1
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2007/01/07 2008/01/12
C
Compal Secret Data
Deciphered Date
D
Compal Electr onics, Inc.
Title
Cover Sheet
Size Docume nt Number Re v
Cus tom
LA- 3733P
Date: Sheet of
1 36Monday , Marc h 05, 2007
E
0.1
5
4
3
2
1
Compal confidential
533/667/800
Project Code: IBL80
File Name : LA-3733P
D D
Therm al S ensor
AD M 10 32AR M
page 4
AMD Turion/Sempron CPU
So ck et S1 638 P
page 4 ,5,6,7
HT L INK
200-800MHz
DD RI I DD RI I-SO-DIM M X2
page 08,09
Dual Channel
USB con n x1
CRT & TV-ou t
page 19
LCD Co nn. 2C H LVDS
page 18
Nvidia
MCP67-MV
836 BGA
USB 2.0 BUS
HD Audio
IDE BUS
SATA2.0 BUS
3.3V 2 4.576MHz/48Mhz
3.3V A TA-100
CD RO M
C C
PCI- Express
port 1
Co nn.
page 20
USB SU B/ B
page 26page 26
HD A Codec
CX20549
page 22
S- ATA HDD
MI NI C ard
WLAN
page 20
B B
Po wer On /Of f C KT / L ID swi tch / Power O K CKT
DC /DC Inter face CKT.
Power Circu it DC/ DC
A A
page 28
page 29~36
L ED
page 25
LAN (10/100)
RTL8201CL
page 21
RJ -4 5
page 21
page 25
RTC CKT.
page 16
MI I
page 1 0,11,12 ,13,14,15,16,17
LP C BUS
ENE KB926
page 27
To uc h P ad
page 25
EC I/ O Buffer SP I RO M
page 26
Int. KBD
page 27
page 26
Co nn.
page 20
Audio A MP
TI6017 CX20548
page 24
Phone Jack
page 24
AM O M
page 24
RJ -1 1
page 21
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2007/01/07 2008/01/12
3
Compal Secret Data
Deciphered Date
Title
BLOCK D IAGRAM
Size Docume nt Number Re v
Custo m
LA- 3733P
2
Date: Sheet of
2 36Monda y, Marc h 05, 2007
1
0.1
5
Voltage Rails
Power Plane Description
D D
C C
VIN
B+
+CPU_CORE
+0.9V 0.9V switch ed power rail for DDR terminator
+1.5VS
+1.2VALW ON ON ON*
+1.2VS ON OFF OFF
+1.2V_HT
+1.8V 1.8V power rail for DDR
+1.8VS 1.8V switch ed power rail
+3VALW
+3VS
+5VALW
+5VS
Note : ON* m eans that this power plane is ON only with AC power available, otherwise it is OFF.
Adapter power supply (19V)
AC or batt ery power rail for power circuit.
Core voltage for CPU
1.5V switch ed power rail
1.2V alway s on power rail
1.2V switch ed power rail
1.2V switch ed power rail ON OFF OFF
2.5V switch ed power rail+2.5VS OFFON OFF
3.3V alway s on power rail
3.3V switch ed power rail
5V always on power rail
5V switched power rail
4
S1 S3 S5
N/A N/A N/A
ON OFF
ON ON
ON OFFOFF
ON
ON OFF
ON
ON
ON
ON OFF
ON+RTCVCC
3
STATE
Full ON
S1(P ower On Suspend)
N/AN/AN/A
OFF
OFF
S3 ( Suspe nd to RAM)
S4 ( Suspe nd to Disk)
S5 ( Soft OFF)
SIGNAL
SLP_S1# SLP_S3# SLP_S5# +VALW +V +VS Clock
HIGH HIGH H IGH
LOW
LOW
LOW LOW LOW
2
ON
ONONON ON
ON
HIGHHIGH
HIGH
HIGH
ON
ON
LOW
LOWLOW
ON
ON
LOW
ON
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
1
Board ID / SKU ID Table for AD channel
OFF
ON
OFF
ON*
ON
OFF
OFF
ON
ON*
OFF
ON
ONRTC power
Vcc 3.3V +/- 5%
100K +/- 5%Ra/Rc/Re
Board ID
Rb / Rd / Rf V min
0
1
2
3
4
5
6
7 NC
0
8.2K +/- 5%
18K +/- 5%
33K +/- 5%
56K +/- 5%
100K +/- 5%
200K +/- 5%
AD_BID
0 V
0.216 V 0.250 V 0.289 V
0.436 V
0.712 V
1.036 V
1.453 V 1.650 V 1.759 V
1.935 V
2.500 V
V typ
AD_BID
0.503 V
0.819 V
1.185 V 1.264 V
2.200 V
3.300 V
V
max
0 V 0 V
AD_BID
0.538 V
0.875 V
2.341 V
3.300 V
External PCI Devices
Device IDSEL# REQ#/GNT# Interrupts
B B
EC SM Bus1 address
Device
Smart Battery
Address Address
EC SM Bus2 address
Device
ADM1032
1001 10 0X b0001 01 1X b
BTO Option Table
BTO Item BOM Structure
45@DIP CAP & RTC
MCP67 SM Bus address
Device Address
DDR DIMM0
A A
DDR DIMM2
MINI CARD
5
1001 00 0Xb
1001 001Xb
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2007/01/07 2008/01/12
3
Compal Secret Data
Deciphered Date
Title
TABLE OF CONTENTS
Size Docume nt Number Re v
Custo m
LA- 3733P
2
Date: Sheet of
3 36Monda y, Marc h 05, 2007
1
0.1
5
4
3
2
1
PROCESS OR HYPE RTRANSPORT INTERFACE
D D
H_CAD IP1510 H_CAD OP15 10
H_CA DIN1510
H_CAD IP1410
H_CA DIN1410
H_CAD IP1310
H_CA DIN1310
H_CAD IP1210
H_CA DIN1210
H_CAD IP1110
H_CA DIN1110
H_CAD IP1010
H_CA DIN1010
H_CA DIP910
H_C ADIN910
H_CA DIP810
C C
B B
H_C ADIN810
H_CA DIP710
H_C ADIN710
H_CA DIP610
H_C ADIN610
H_CA DIP510
H_C ADIN510
H_CA DIP410
H_C ADIN410
H_CA DIP310
H_C ADIN310
H_CA DIP210
H_C ADIN210
H_CA DIP110
H_C ADIN110
H_CA DIP010
H_C ADIN010
+1.2V_HT
R2 51_0402_1%
1 2
R3 51_0402_1%
1 2
+1.2V_HT
1
C6
2
4.7U_0 805_10V4Z
H_CLK IP110
H_CLK IN110
H_CLK IP010
H_CLK IN010
H_CTLIP010
H_CTL IN010
4.7U_0 805_10V4Z
1
2
VLDT_Ax AND VLDT_Bx ARE CONNECTED TO THE LDT_RUN POWER
SUPPLY THROUGH THE PACKAGE OR ON THE DIE. IT IS ONLY CONNECTED
ON THE BOARD TO DECOUPLING NEAR THE CPU PACKAGE
+1.2V_HT
JP1A
D4
VLDT_A3
D3
VLDT_A2
D2
VLDT_A1
D1
VLDT_A0
N5
L0_CADIN_H15
P5
L0_CADIN_L15
M3
L0_CADIN_H14
M4
L0_CADIN_L14
L5
L0_CADIN_H13
M5
L0_CADIN_L13
K3
L0_CADIN_H12
K4
L0_CADIN_L12
H3
L0_CADIN_H11
H4
L0_CADIN_L11
G5
L0_CADIN_H10
H5
L0_CADIN_L10
F3
L0_CADIN_H9
F4
L0_CADIN_L9
E5
L0_CADIN_H8
F5
L0_CADIN_L8
N3
L0_CADIN_H7
N2
L0_CADIN_L7
L1
L0_CADIN_H6
M1
L0_CADIN_L6
L3
L0_CADIN_H5
L2
L0_CADIN_L5
J1
L0_CADIN_H4
K1
L0_CADIN_L4
G1
L0_CADIN_H3
H1
L0_CADIN_L3
G3
L0_CADIN_H2
G2
L0_CADIN_L2
E1
L0_CADIN_H1
F1
L0_CADIN_L1
E3
L0_CADIN_H0
E2
L0_CADIN_L0
J5
L0_CLKIN_H1
K5
L0_CLKIN_L1
J3
L0_CLKIN_H0
J2
L0_CLKIN_L0
P3
L0_CTLIN_H1
P4
L0_CTLIN_L1
N1
L0_CTLIN_H0
P1
L0_CTLIN_L0
FOX_PZ63823-284S-41F
0.22U_ 0402_10V4Z
1
C9
2
180P_0402_50V8J
1
2
C10
L0_CADOUT_H15
L0_CADOUT_L15
L0_CADOUT_H14
L0_CADOUT_L14
L0_CADOUT_H13
L0_CADOUT_L13
L0_CADOUT_H12
L0_CADOUT_L12
L0_CADOUT_H11
L0_CADOUT_L11
L0_CADOUT_H10
L0_CADOUT_L10
ace
ace
ace
ace
HT T In te r f
HT T In te r f
HT T In te r f
HT T In te r f
Athlon 64 S1
Processor Socket
180P_0402_50V8J
1
2
L0_CADOUT_H9
L0_CADOUT_L9
L0_CADOUT_H8
L0_CADOUT_L8
L0_CADOUT_H7
L0_CADOUT_L7
L0_CADOUT_H6
L0_CADOUT_L6
L0_CADOUT_H5
L0_CADOUT_L5
L0_CADOUT_H4
L0_CADOUT_L4
L0_CADOUT_H3
L0_CADOUT_L3
L0_CADOUT_H2
L0_CADOUT_L2
L0_CADOUT_H1
L0_CADOUT_L1
L0_CADOUT_H0
L0_CADOUT_L0
L0_CLKOUT_H1
L0_CLKOUT_L1
L0_CLKOUT_H0
L0_CLKOUT_L0
L0_CTLOUT_H1
L0_CTLOUT_L1
L0_CTLOUT_H0
L0_CTLOUT_L0
C11
C7
H_CAD IP15
H_CAD IP14
H_C ADIN14
H_CAD IP13
H_C ADIN13
H_CAD IP12
H_C ADIN12
H_CAD IP11
H_C ADIN11
H_CAD IP10
H_C ADIN10
H_CA DIP9
H_C ADIN9
H_CA DIP8
H_C ADIN8
H_CA DIP7
H_C ADIN7
H_CA DIP6
H_C ADIN6
H_CA DIP5
H_C ADIN5
H_CA DIP4
H_C ADIN4
H_CA DIP3
H_C ADIN3
H_CA DIP2
H_C ADIN2
H_CA DIP1
H_C ADIN1
H_CA DIP0
H_C ADIN0
H_CLK IP1
H_CL KIN1
H_CLK IP0
H_CL KIN0
H_CTLIP1
H_CTL IN1
H_CTLIP0
H_CTL IN0
1
C8
2
0.22U_ 0402_10V4Z
C1
AE5
VLDT_B3
VLDT_B2
VLDT_B1
VLDT_B0
1 2
4.7U_0 805_10V4Z
AE4
AE3
AE2
H_CAD OP15
T4
H_CAD ON15H_C ADIN15
T3
H_CAD OP14
V5
H_CAD ON14
U5
H_CAD OP13
V4
H_CAD ON13
V3
H_CAD OP12
Y5
H_CAD ON12
W5
H_CAD OP11
AB5
H_CAD ON11
AA5
H_CAD OP10
AB4
H_CAD ON10
AB3
H_CAD OP9
AD5
H_CA DON9
AC5
H_CAD OP8
AD4
H_CA DON8
AD3
H_CAD OP7
T1
H_CA DON7
R1
H_CAD OP6
U2
H_CA DON6
U3
H_CAD OP5
V1
H_CA DON5
U1
H_CAD OP4
W2
H_CA DON4
W3
H_CAD OP3
AA2
H_CA DON3
AA3
H_CAD OP2
AB1
H_CA DON2
AA1
H_CAD OP1
AC2
H_CA DON1
AC3
H_CAD OP0
AD1
H_CA DON0
AC1
H_CLKOP1
Y4
H_CLK ON1
Y3
H_CLKOP0
Y1
H_CLK ON0
W1
T5
R5
H_CTLOP0
R2
H_CTLON0
R3
LAYOUT: Place bypass cap on topside of board
NEAR HT POWER PINS THAT ARE NOT CONNECTED DIRECTLY
TO DOWNSTREAM HT DEVICE, BUT CONNECTED INTERNALLY
TO OTHER HT POWER PINS
PLACE CLOSE TO VLDT0 POWER PINS
H_CAD ON15 10
H_CAD OP14 10
H_CAD ON14 10
H_CAD OP13 10
H_CAD ON13 10
H_CAD OP12 10
H_CAD ON12 10
H_CAD OP11 10
H_CAD ON11 10
H_CAD OP10 10
H_CAD ON10 10
H_CAD OP9 10
H_CA DON9 10
H_CAD OP8 10
H_CA DON8 10
H_CAD OP7 10
H_CA DON7 10
H_CAD OP6 10
H_CA DON6 10
H_CAD OP5 10
H_CA DON5 10
H_CAD OP4 10
H_CA DON4 10
H_CAD OP3 10
H_CA DON3 10
H_CAD OP2 10
H_CA DON2 10
H_CAD OP1 10
H_CA DON1 10
H_CAD OP0 10
H_CA DON0 10
H_CLK OP1 10
H_CLK ON1 10
H_CLK OP0 10
H_CLK ON0 10
H_CTLOP0 10
H_CTLON 0 10
Thermal Sensor ADM1032ARMZ
C2
0.1U_0 402_16V4Z
H_THERM DA
H_THERM DC
+3VS
R1
1 2
10K_0402_5%
2
C3
2200P_0402_50V7K
1
H_THERM DA6
H_THERM DC6
PWM Fan Control circuit
+3VS
5
U2
1
THERM#
INB
2
INA
P
4
O
G
TC7SH00 FU_SSOP5
3
3
FAN_PWM27
G
+3VS
THERM#
2
1
2
1
+5VS
2 1
6
S
4 5
U1
1
VDD
2
D+
3
D-
THERM#4GND
ADM10 32ARMZ-2REEL_MSOP8
Addres s:100_1100
1
D1
RB751 V_SOD323
2
D
Q1
SI3456 BDV-T1-E3_TSOP6
CLOSE CPU,
CPU_THERMDA&CPU_THERMDC PLACE
CLOSE TO PROCESSOR WITHIN 1" INCH
SMB_EC_CK2
8
SCLK
SMB_EC_DA2
7
SDATA
6
ALERT#
5
1
C5
0.1U_0 402_16V4Z
2
12
ZD1
@
RLZ5.1B _LL34
SMB_EC_DA2
SMB_EC_CK2
SMB_EC_DA227
SMB_EC_CK227
SP02000D000 S W-CONN ACES 85204-02001 2P P1.25
ACES_85204-02001_2P
C4
4.7U_0 805_10V4Z
FAN
JP2
1
1
2
2
3
G1
4
G2
ACES_85204-02001
CONN @
A1
A26
ZZZ1
A A
PCB
LA-3733P
DA600005I00
5
AF1
Athlon 64 S1g1
uPGA638
Top View
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2007/01/07 2008/01/12
3
Compal Secret Data
Deciphered Date
Title
AMD CPU HT I/F
Size Docume nt Number Re v
Custo m
LA- 3733P
2
Date: Sheet of
4 36Monda y, Marc h 05, 2007
1
0.1
A
B
C
D
E
Processor DDR2 Memory Interface
VDD_VTT_SUS_CPU IS CONNECTED TO THE VDD_VTT_SUS POWER
SUPPLY THROUGH THE PACKAGE OR ON THE DIE. IT IS ONLY CONNECTED
ON THE BOARD TO DECOUPLING NEAR THE CPU PACKAGE
+1.8V
4 4
12
R4
39.2_ 0402_1%~D
R5
12
39.2_ 0402_1%~D
DDR_ CS3_ DIMMA#8
DDR_ CS2_ DIMMA#8
DDR_ CS1_ DIMMA#8
DDR_ CS0_ DIMMA#8
DDR_ CS3_ DIMMB#9
DDR_ CS2_ DIMMB#9
PLACE THEM CLOSE TO
CPU WITHIN 1"
3 3
2 2
DDR_ CS1_ DIMMB#9
DDR_ CS0_ DIMMB#9
DDR_ CKE1 _DIMMB9
DDR_ CKE0 _DIMMB9
DDR_ CKE1 _DIMMA8
DDR_ CKE0 _DIMMA8
DDR_ A_MA[1 5..0 ]8
DDR_ A_BS#28
DDR_ A_BS#18
DDR_ A_BS#08
DDR_ A_RAS #8
DDR_ A_CAS #8
DDR_ A_WE #8
DDR_ A_CLK 2
DDR_ A_CLK #2
DDR_ A_CLK 1
DDR_ A_CLK #1
PLACE CLOSE TO PROCESSOR
WITHIN 1.2 INCH
1K_0402_1 %
1K_0402_1 %
R6
R7
10:8:1 0:8:10
1
2
1
2
+1.8V
12
12
+0.9 VREF_ CPU
TP1PAD
M_Z N
M_ZP
DDR_ CS3_ DIMMA#
DDR_ CS2_ DIMMA#
DDR_ CS1_ DIMMA#
DDR_ CS0_ DIMMA#
DDR_ CS3_ DIMMB#
DDR_ CS2_ DIMMB#
DDR_ CS1_ DIMMB#
DDR_ CS0_ DIMMB#
DDR_ CKE1 _DIMMB
DDR_ CKE0 _DIMMB
DDR_ CKE1 _DIMMA
DDR_ CKE0 _DIMMA
DDR_ A_MA15
DDR_ A_MA14
DDR_ A_MA13
DDR_ A_MA12
DDR_ A_MA11
DDR_ A_MA10
DDR_ A_MA9
DDR_ A_MA8
DDR_ A_MA7
DDR_ A_MA6
DDR_ A_MA5
DDR_ A_MA4
DDR_ A_MA3
DDR_ A_MA2
DDR_ A_MA1
DDR_ A_MA0
DDR_ A_BS#2
DDR_ A_BS#1
DDR_ A_BS#0
DDR _A_RA S#
DDR _A_CA S#
DDR_ A_WE #
C12
1.5P _0402_50 V8C
C14
1.5P _0402_50 V8C
VTT_SE NSE
JP1B
W17
M_VREF
Y10
VTT_SENSE
AE10
M_ZN
AF10
M_ZP
V19
MA0_CS_L3
J22
MA0_CS_L2
V22
MA0_CS_L1
T19
MA0_CS_L0
Y26
MB0_CS_L3
J24
MB0_CS_L2
W24
MB0_CS_L1
U23
MB0_CS_L0
H26
MB_CKE1
J23
MB_CKE0
J20
MA_CKE1
J21
MA_CKE0
K19
MA_ADD15
K20
MA_ADD14
V24
MA_ADD13
K24
MA_ADD12
L20
MA_ADD11
R19
MA_ADD10
L19
MA_ADD9
L22
MA_ADD8
L21
MA_ADD7
M19
MA_ADD6
M20
MA_ADD5
M24
MA_ADD4
M22
MA_ADD3
N22
MA_ADD2
N21
MA_ADD1
R21
MA_ADD0
K22
MA_BANK2
R20
MA_BANK1
T22
MA_BANK0
T20
MA_RAS_L
U20
MA_CAS_L
U21
MA_WE_L
FOX_PZ63823-284S-41F
Athlon 64 S1
Processor
Socket
CPU _VRE F_RE F
0.1U_ 0402 _16V4Z
VTT1
VTT2
VTT3
VTT4
VTT5
VTT6
VTT7
VTT8
VTT9
MA0_CLK_H2
MA0_CLK_L2
MA0_CLK_H1
MA0_CLK_L1
MB0_CLK_H2
MB0_CLK_L2
MB0_CLK_H1
MB0_CLK_L1
MB0_ODT1
MB0_ODT0
MA0_ODT1
MA0_ODT0
MB_ADD15
Cm d/ Ctr l/ /C lk
Cm d/ Ctr l/ /C lk
MB_ADD14
Cm d/ Ctr l/ /C lk
Cm d/ Ctr l/ /C lk
MB_ADD13
MB_ADD12
MB_ADD11
MB_ADD10
MB_ADD9
MB_ADD8
DD RI I
DD RI I
DD RI I
DD RI I
MB_ADD7
MB_ADD6
MB_ADD5
MB_ADD4
MB_ADD3
MB_ADD2
MB_ADD1
MB_ADD0
MB_BANK2
MB_BANK1
MB_BANK0
MB_RAS_L
MB_CAS_L
MB_WE_L
DDR_ B_CL K2
DDR_ B_CL K#2
DDR_ B_CL K1
DDR_ B_CL K#1
PLACE CLOSE TO PROCESSOR
WITHIN 1.2 INCH
1
1
C16
C17
2
2
1000P_040 2_50V7K
D10
C10
B10
AD10
W10
AC10
AB10
AA10
A10
Y16
AA16
E16
F16
AF18
AF17
A17
A18
W23
W26
V20
U19
J25
J26
W25
L23
L25
U25
L24
M26
L26
N23
N24
N25
N26
P24
P26
T24
K26
T26
U26
U24
V26
U22
DDR_ A_CLK 2
DDR_ A_CLK #2
DDR_ A_CLK 1
DDR_ A_CLK #1
DDR_ B_CL K2
DDR_ B_CL K#2
DDR_ B_CL K1
DDR_ B_CL K#1
DDR_ B_ODT1
DDR_ B_ODT0
DDR_ A_ODT1
DDR_ A_ODT0
DDR_ B_MA15
DDR_ B_MA14
DDR_ B_MA13
DDR_ B_MA12
DDR_ B_MA11
DDR_ B_MA10
DDR_ B_MA9
DDR_ B_MA8
DDR_ B_MA7
DDR_ B_MA6
DDR_ B_MA5
DDR_ B_MA4
DDR_ B_MA3
DDR_ B_MA2
DDR_ B_MA1
DDR_ B_MA0
DDR_ B_BS#2
DDR_ B_BS#1
DDR_ B_BS#0
DDR_ B_RAS #
DDR_ B_CAS #
DDR_ B_W E#
1
2
1
2
+0.9 VREF_ CPU
+0.9V
C13
1.5P _0402_50 V8C
C15
1.5P _0402_50 V8C
DDR_ A_CLK 2 8
DDR_ A_CLK #2 8
DDR_ A_CLK 1 8
DDR_ A_CLK #1 8
DDR_ B_CL K2 9
DDR_ B_CL K#2 9
DDR_ B_CL K1 9
DDR_ B_CL K#1 9
DDR_ B_ODT1 9
DDR_ B_ODT0 9
DDR_ A_ODT1 8
DDR_ A_ODT0 8
DDR_ B_MA[ 15..0 ] 9
DDR_ B_BS#2 9
DDR_ B_BS#1 9
DDR_ B_BS#0 9
DDR_ B_RAS # 9
DDR_ B_CAS # 9
DDR_ B_W E# 9
DDR_ B_D[ 63.. 0]9
To reverse SODIMM socket
DDR_ B_DM[ 7..0 ]9 DDR_ A_DM[ 7..0 ] 8
DDR_ B_DQS 79
DDR_ B_DQS #79
DDR_ B_DQS 69
DDR_ B_DQS #69
DDR_ B_DQS 59
DDR_ B_DQS #59
DDR_ B_DQS 49
DDR_ B_DQS #49
DDR_ B_DQS 39
DDR_ B_DQS #39
DDR_ B_DQS 29
DDR_ B_DQS #29
DDR_ B_DQS 19
DDR_ B_DQS #19
DDR_ B_DQS 09
DDR_ B_DQS #09
DDR_ B_D6 3
DDR_ B_D6 2
DDR_ B_D6 1
DDR_ B_D6 0
DDR_ B_D5 9
DDR_ B_D5 8
DDR_ B_D5 7
DDR_ B_D5 6
DDR_ B_D5 5
DDR_ B_D5 4
DDR_ B_D5 3
DDR_ B_D5 2
DDR_ B_D5 1
DDR_ B_D5 0
DDR_ B_D4 9
DDR_ B_D4 8
DDR_ B_D4 7
DDR_ B_D4 6
DDR_ B_D4 5
DDR_ B_D4 4
DDR_ B_D4 3
DDR_ B_D4 2
DDR_ B_D4 1
DDR_ B_D4 0
DDR_ B_D3 9
DDR_ B_D3 8
DDR_ B_D3 7
DDR_ B_D3 6
DDR_ B_D3 5
DDR_ B_D3 4
DDR_ B_D3 3
DDR_ B_D3 2
DDR_ B_D3 1
DDR_ B_D3 0
DDR_ B_D2 9
DDR_ B_D2 8
DDR_ B_D2 7
DDR_ B_D2 6
DDR_ B_D2 5
DDR_ B_D2 4
DDR_ B_D2 3
DDR_ B_D2 2
DDR_ B_D2 1
DDR_ B_D2 0
DDR_ B_D1 9
DDR_ B_D1 8
DDR_ B_D1 7
DDR_ B_D1 6
DDR_ B_D1 5
DDR_ B_D1 4
DDR_ B_D1 3
DDR_ B_D1 2
DDR_ B_D1 1
DDR_ B_D1 0
DDR _B_D 9
DDR _B_D 8
DDR _B_D 7
DDR _B_D 6
DDR _B_D 5
DDR _B_D 4
DDR _B_D 3
DDR _B_D 2
DDR _B_D 1
DDR _B_D 0
DDR_ B_DM7
DDR_ B_DM6
DDR_ B_DM5
DDR_ B_DM4
DDR_ B_DM3
DDR_ B_DM2
DDR_ B_DM1
DDR_ B_DM0
DDR_ B_DQS 7
DDR_ B_DQS #7
DDR_ B_DQS 6
DDR_ B_DQS #6
DDR_ B_DQS 5
DDR_ B_DQS #5
DDR_ B_DQS 4
DDR_ B_DQS #4
DDR_ B_DQS 3
DDR_ B_DQS #3
DDR_ B_DQS 2
DDR_ B_DQS #2
DDR_ B_DQS 1
DDR_ B_DQS #1
DDR_ B_DQS 0
DDR_ B_DQS #0
JP1C
AD11
MB_DATA63
AF11
MB_DATA62
AF14
MB_DATA61
AE14
MB_DATA60
Y11
MB_DATA59
AB11
MB_DATA58
AC12
MB_DATA57
AF13
MB_DATA56
AF15
MB_DATA55
AF16
MB_DATA54
AC18
MB_DATA53
AF19
MB_DATA52
AD14
MB_DATA51
AC14
MB_DATA50
AE18
MB_DATA49
AD18
MB_DATA48
AD20
MB_DATA47
AC20
MB_DATA46
AF23
MB_DATA45
AF24
MB_DATA44
AF20
MB_DATA43
AE20
MB_DATA42
AD22
MB_DATA41
AC22
MB_DATA40
AE25
MB_DATA39
AD26
MB_DATA38
AA25
MB_DATA37
AA26
MB_DATA36
AE24
MB_DATA35
AD24
MB_DATA34
AA23
MB_DATA33
AA24
MB_DATA32
G24
MB_DATA31
G23
MB_DATA30
D26
MB_DATA29
C26
MB_DATA28
G26
MB_DATA27
G25
MB_DATA26
E24
MB_DATA25
E23
MB_DATA24
C24
MB_DATA23
B24
MB_DATA22
C20
MB_DATA21
B20
MB_DATA20
C25
MB_DATA19
D24
MB_DATA18
A21
MB_DATA17
D20
MB_DATA16
D18
MB_DATA15
C18
MB_DATA14
D14
MB_DATA13
C14
MB_DATA12
A20
MB_DATA11
A19
MB_DATA10
A16
MB_DATA9
A15
MB_DATA8
A13
MB_DATA7
D12
MB_DATA6
E11
MB_DATA5
G11
MB_DATA4
B14
MB_DATA3
A14
MB_DATA2
A11
MB_DATA1
C11
MB_DATA0
AD12
MB_DM7
AC16
MB_DM6
AE22
MB_DM5
AB26
MB_DM4
E25
MB_DM3
A22
MB_DM2
B16
MB_DM1
A12
MB_DM0
AF12
MB_DQS_H7
AE12
MB_DQS_L7
AE16
MB_DQS_H6
AD16
MB_DQS_L6
AF21
MB_DQS_H5
AF22
MB_DQS_L5
AC25
MB_DQS_H4
AC26
MB_DQS_L4
F26
MB_DQS_H3
E26
MB_DQS_L3
A24
MB_DQS_H2
A23
MB_DQS_L2
D16
MB_DQS_H1
C16
MB_DQS_L1
C12
MB_DQS_H0
B12
MB_DQS_L0
FOX_PZ63823-284S-41F
Athlon 64 S1
Processor Socket
MA_DATA63
MA_DATA62
MA_DATA61
MA_DATA60
MA_DATA59
MA_DATA58
MA_DATA57
MA_DATA56
MA_DATA55
MA_DATA54
MA_DATA53
MA_DATA52
MA_DATA51
MA_DATA50
MA_DATA49
MA_DATA48
MA_DATA47
MA_DATA46
MA_DATA45
MA_DATA44
MA_DATA43
MA_DATA42
MA_DATA41
MA_DATA40
MA_DATA39
MA_DATA38
MA_DATA37
MA_DATA36
MA_DATA35
MA_DATA34
MA_DATA33
MA_DATA32
MA_DATA31
MA_DATA30
MA_DATA29
MA_DATA28
MA_DATA27
MA_DATA26
MA_DATA25
MA_DATA24
MA_DATA23
MA_DATA22
MA_DATA21
MA_DATA20
MA_DATA19
MA_DATA18
MA_DATA17
MA_DATA16
DR II Da t a
DR II Da t a
DR II Da t a
DR II Da t a
MA_DATA15
MA_DATA14
D
D
D
D
MA_DATA13
MA_DATA12
MA_DATA11
MA_DATA10
MA_DQS_H7
MA_DQS_L7
MA_DQS_H6
MA_DQS_L6
MA_DQS_H5
MA_DQS_L5
MA_DQS_H4
MA_DQS_L4
MA_DQS_H3
MA_DQS_L3
MA_DQS_H2
MA_DQS_L2
MA_DQS_H1
MA_DQS_L1
MA_DQS_H0
MA_DQS_L0
MA_DATA9
MA_DATA8
MA_DATA7
MA_DATA6
MA_DATA5
MA_DATA4
MA_DATA3
MA_DATA2
MA_DATA1
MA_DATA0
MA_DM7
MA_DM6
MA_DM5
MA_DM4
MA_DM3
MA_DM2
MA_DM1
MA_DM0
AA12
AB12
AA14
AB14
W11
Y12
AD13
AB13
AD15
AB15
AB17
Y17
Y14
W14
W16
AD17
Y18
AD19
AD21
AB21
AB18
AA18
AA20
Y20
AA22
Y22
W21
W22
AA21
AB22
AB24
Y24
H22
H20
E22
E21
J19
H24
F22
F20
C23
B22
F18
E18
E20
D22
C19
G18
G17
C17
F14
E14
H17
E17
E15
H15
E13
C13
H12
H11
G14
H14
F12
G12
Y13
AB16
Y19
AC24
F24
E19
C15
E12
W12
W13
Y15
W15
AB19
AB20
AD23
AC23
G22
G21
C22
C21
G16
G15
G13
H13
DDR _A_D6 3
DDR _A_D6 2
DDR _A_D6 1
DDR _A_D6 0
DDR _A_D5 9
DDR _A_D5 8
DDR _A_D5 7
DDR _A_D5 6
DDR _A_D5 5
DDR _A_D5 4
DDR _A_D5 3
DDR _A_D5 2
DDR _A_D5 1
DDR _A_D5 0
DDR _A_D4 9
DDR _A_D4 8
DDR _A_D4 7
DDR _A_D4 6
DDR _A_D4 5
DDR _A_D4 4
DDR _A_D4 3
DDR _A_D4 2
DDR _A_D4 1
DDR _A_D4 0
DDR _A_D3 9
DDR _A_D3 8
DDR _A_D3 7
DDR _A_D3 6
DDR _A_D3 5
DDR _A_D3 4
DDR _A_D3 3
DDR _A_D3 2
DDR _A_D3 1
DDR _A_D3 0
DDR _A_D2 9
DDR _A_D2 8
DDR _A_D2 7
DDR _A_D2 6
DDR _A_D2 5
DDR _A_D2 4
DDR _A_D2 3
DDR _A_D2 2
DDR _A_D2 1
DDR _A_D2 0
DDR _A_D1 9
DDR _A_D1 8
DDR _A_D1 7
DDR _A_D1 6
DDR _A_D1 5
DDR _A_D1 4
DDR _A_D1 3
DDR _A_D1 2
DDR _A_D1 1
DDR _A_D1 0
DD R_A_D 9
DD R_A_D 8
DD R_A_D 7
DD R_A_D 6
DD R_A_D 5
DD R_A_D 4
DD R_A_D 3
DD R_A_D 2
DD R_A_D 1
DD R_A_D 0
DDR_ A_DM7
DDR_ A_DM6
DDR_ A_DM5
DDR_ A_DM4
DDR_ A_DM3
DDR_ A_DM2
DDR_ A_DM1
DDR_ A_DM0
DDR _A_DQ S7
DDR_ A_DQS #7
DDR _A_DQ S6
DDR_ A_DQS #6
DDR _A_DQ S5
DDR_ A_DQS #5
DDR _A_DQ S4
DDR_ A_DQS #4
DDR _A_DQ S3
DDR_ A_DQS #3
DDR _A_DQ S2
DDR_ A_DQS #2
DDR _A_DQ S1
DDR_ A_DQS #1
DDR _A_DQ S0
DDR_ A_DQS #0
DDR_ A_D[6 3..0 ] 8
DDR_ A_DQS 7 8
DDR_ A_DQS #7 8
DDR_ A_DQS 6 8
DDR_ A_DQS #6 8
DDR_ A_DQS 5 8
DDR_ A_DQS #5 8
DDR_ A_DQS 4 8
DDR_ A_DQS #4 8
DDR_ A_DQS 3 8
DDR_ A_DQS #3 8
DDR_ A_DQS 2 8
DDR_ A_DQS #2 8
DDR_ A_DQS 1 8
DDR_ A_DQS #1 8
DDR_ A_DQS 0 8
DDR_ A_DQS #0 8
To normal SODIMM socket
VDD_VREF_SUS_CPU
1 1
A
LAYOUT:PLACE CLOSE TO CPU
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
Compal Secret Data
2007/01/07 2008/01/12
Deciphered Date
D
Title
AMD CPU DDRII MEMORY I/F
Size Docume nt Numb er Rev
Cus tom
LA-3 733P
Date : Sheet o f
5 36Monda y, M arch 05, 2007
E
0.1
5
+2.5VS
1
C18
22U_0 805_6.3 V6M
2
D D
C C
HTCP U_PW RGD10
HTCPU_ STOP#10
HTCPU_ RST#10
1 2
FCM2 012C-800_ 0805
L1
1
C19
2
4.7U_ 0805 _10V4Z
+1.8V
12
R17
300_0402_ 5%
+1.8V
12
R20
300_0402_ 5%
+1.8V
12
R22
300_0402_ 5%
1
C20
2
0.22 U_0603_ 16V7K
1 2
R19 0_0402_5%
1 2
R21 0_0402_5%
1 2
R23 0_0402_5%
4
W=50mils
1
C21
3300P_040 2_50V7K
2
CPU_ SIC15
CPU_ SID15
+1.8V
+1.2 V_HT
R10 300_0402_ 5%
1 2
R11 300_0402_ 5%
1 2
R12 0_0402_5%
1 2
R13 0_0402_5%
1 2
R14 44.2_0603 _1%
1 2
R15 44.2_0603 _1%
1 2
place t hem to CPU within 1"
CPU CLK10
CPUC LK#10
CPU_AL L_P WROK
CPU_L DTSTOP#
CPU_HT _RES ET#
3
ATHLON Control and Debug
LAYOUT: ROUTE VDDA TRACE APPROX.
50 mils WIDE (USE 2x25 mil TRACES TO
EXIT BALL FIELD) AND 500 mils LONG.
+2.5 VS_VDD A
CP U_SIC _R
CP U_SID _R
CP U_HTRE F1
CP U_HTRE F0 VID0
5:10
CPU _VCC_ SENS E34
CPU_VS S_SE NSE34
C22
1 2
12
3900P_040 2_50V7K
R16
169_0402_ 1%
1 2
H_T HERMD C4
H_T HERMDA4
R24 300_0402_ 5%
R25 1K_0402_5 %
R26 510_0402_ 5%
R27 300_0402_ 5%
R28 510_0402_ 5%
R29 300_0402_ 5%
R30 300_0402_ 5%
C23
3900P_040 2_50V7K
CPU_ TEST2 6_B URNIN#
CPU_P RESE NT#
CPU_TE ST25 _H_B YPASS CLK_H
CPU_TE ST21 _SCAN EN
CPU_TE ST25 _L_ BYPASSCLK_L
CPU_TE ST19_PLL TEST0
CPU_TE ST18_PLL TEST1
TP2PAD
TP3PAD
CPU_ CLKI N_SC _P
CPU _CL KIN_S C_N
CPU_TE ST25 _H_B YPASS CLK_H
CPU_TE ST25 _L_ BYPASSCLK_L
CPU_TE ST19_PLL TEST0
CPU_TE ST18_PLL TEST1
H_T HERMD C
H_T HERMD A
10:10
1 2
1 2
1 2
1 2
1 2
1 2
1 2
CPU_HT _RES ET#
CPU_AL L_P WROK
CPU_L DTSTOP#
CP U_VCC_ SENS E
CPU_VS S_SE NSE
CPU _DB RD Y
CPU_TMS
CPU_ TCK
CPU_TR ST#
CP U_TDI
TP4
TP6
TP8
TP10
TP11
+1.8V
JP1D
F8
VDDA2
F9
VDDA1
B7
RESET_L
A7
PWROK
F10
LDTSTOP_L
AF4
SIC
AF5
SID
P6
HTREF1
R6
HTREF0
F6
VDD_FB_H
E6
VDD_FB_L
W9
VDDIO_FB_H
Y9
VDDIO_FB_L
A9
CLKIN_H
A8
CLKIN_L
G10
DBRDY
AA9
TMS
AC9
TCK
AD9
TRST_L
AF9
TDI
TEST25_HE9TEST29_H
E8
TEST25_L
G9
TEST19
H10
TEST18
AA7
TEST13
C2
TEST9
D7
TEST17
E7
TEST16
F7
TEST15
C7
TEST14
AC8
TEST12
C3
TEST7
AA6
TEST6
W7
THERMDC
W8
THERMDA
Y6
TEST3
AB6
TEST2
P20
RSVD0
P19
RSVD1
N20
RSVD2
N19
RSVD3
R26
RSVD4
R25
RSVD5
P22
RSVD6
R22
RSVD7
FOX_PZ63823-284S-41F
2
THERMTRIP_L
PROCHOT_L
CPU_PRESENT_L
SC
SC
SC
SC
MI
MI
MI
MI
AMD NPT S1 SOCKET
Processor Socket
DBREQ_L
TEST29_L
TEST24
TEST23
TEST22
TEST21
TEST20
TEST28_H
TEST28_L
TEST27
TEST26
TEST10
RSVD8
RSVD9
RSVD10
RSVD11
RSVD12
RSVD13
RSVD14
RSVD15
RSVD16
RSVD17
RSVD18
RSVD19
RSVD20
TEST8
AF6
AC7
A5
VID5
C6
VID4
A6
VID3
A4
VID2
C5
VID1
B5
VID0
AC6
A3
PSI_L
E10
AE9
TDO
C9
C8
AE7
AD7
AE8
AB8
AF7
J7
H8
AF8
AE6
K8
C4
H16
B18
B3
C1
H6
G6
D5
R24
W18
R23
AA8
H18
H19
R8
300_0402_ 5%
H_THER MTRIP_ S#
CPU_P ROCHO T#_1. 8
VID5
VID4
VID3
VID2
VID1
CPU_P RESE NT#
PSI#
CPU_ DBRE Q#
CP U_TDO
CPU_TE ST29 _H_F BCLKOUT_P
CPU_TE ST29 _L_ FBCLKOUT_N
5:5:5
TP5
TP7
TP9
CPU_TE ST21 _SCAN EN
TP12
CPU_ TEST2 6_B URNIN#
+1.8V
12
PSI# 34
1 2
80.6_0402 _1%
R18
12
R9
300_0402_ 5%
1
VID5 34
VID4 34
VID3 34
VID2 34
VID1 34
VID0 34
ROUTE AS 80 Ohm DIFFERENTIAL PAIR
PLACE IT CLOSE TO CPU WITHIN 1"
HDT Connector
B B
CPU_ DBRE Q#
CPU _DB RD Y
CPU_ TCK
CP U_TDI
CPU_TR ST#
CP U_TDO
NOTE: HDT TERMINATION IS REQUIRED
FOR REV. Ax SILICON ONLY.
A A
+1.8V
JP3
2
1
4
3
6
5
8
7
10
9
12
11
14
13
16
15
18
17
20
19
22
21
2423
26
SAMTEC _ASP-68200-0 7
@
R35
220_0402_ 5%@
3V_L DT_RST# CPU_HT_R ESET#
+3VALW+3VS
12
2
G
1 3
D
S
Q4
2N700 2_SOT23@
PRO CHOT#10
+1.8V + 1.8V +3VALW +3VAL W
12
@
Q2
3 1
MMBT3904_SOT23
1 2
R36 0_0402_5%
CPU_P ROCHO T#_1. 8
12
2
10K_0402_ 5%
R31
300_0402_ 5%
H_THER MTRIP_ S# H_THER MTRIP#CPU_TMS
1 2
R39 0_0402_5%
R32
1K_0402_5 %
@
R37
+1.8V +3VS
12
CP U_PH_G
B
2
Q5
E
3 1
C
MMBT3904_SOT23
12
R34
10K_0402_ 5%
@
12
12
2
3 1
R38
4.7K_0402_ 5%
R33
1K_0402_5 %@
Q3
MMBT3904_SOT23
@
EC_THE RM# 15,27
MAI NPWO N 31,35
H_THER MTRIP# 10
Connect to MCP67
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
Compal Secret Data
2007/01/07 2008/01/12
Deciphered Date
2
Title
AMD CPU CTRL & DEBUG
Size Docume nt Numb er Rev
C
LA-3 733P
Date : Sheet o f
6 36Monda y, M arch 05, 2007
1
0.1
5
4
3
2
1
+CPU_ CORE
1
+
C24
330U_ 4V_M
D D
PROCESSOR POWER AND GROUND
JP1F
AA4
VSS1
AA11
VSS2
AA13
VSS3
AA15
VSS4
AA17
VSS5
AA19
VSS6
AB2
VSS7
AB7
VSS8
AB9
VSS9
AB23
VSS10
AB25
VSS11
AC11
VSS12
AC13
VSS13
AC15
VSS14
AC17
VSS15
AC19
VSS16
AC21
VSS17
AD6
VSS18
AD8
VSS19
AD25
VSS20
AE11
VSS21
AE13
VSS22
AE15
VSS23
AE17
VSS24
AE19
VSS25
AE21
VSS26
AE23
VSS27
B4
VSS28
B6
VSS29
B8
VSS30
B9
VSS31
B11
VSS32
B13
VSS33
B15
VSS34
B17
VSS35
B19
VSS36
B21
VSS37
B23
VSS38
B25
VSS39
D6
VSS40
D8
VSS41
D9
VSS42
D11
VSS43
D13
VSS44
D15
VSS45
D17
VSS46
D19
VSS47
D21
VSS48
D23
VSS49
D25
VSS50
E4
VSS51
F2
VSS52
F11
VSS53
F13
VSS54
F15
VSS55
F17
VSS56
F19
VSS57
F21
VSS58
F23
VSS59
F25
VSS60
H7
VSS61
H9
VSS62
H21
VSS63
H23
VSS64
J4
VSS65
FOX_PZ63823-284S-41F
er
er
er
er
Po w
Po w
Po w
Po w
VDDIO1
VDDIO2
VDDIO3
VDDIO4
VDDIO5
VDDIO6
VDDIO7
VDDIO8
VDDIO9
VDDIO10
VDDIO11
VDDIO12
VDDIO13
VDDIO14
VDDIO15
VDDIO16
VDDIO17
VDDIO18
VDDIO19
VDDIO20
VDDIO21
VDDIO22
VDDIO23
VDDIO24
VDDIO25
VDDIO26
VDDIO27
VDD43
VDD44
VDD45
VDD46
VDD47
VDD48
VDD49
VDD50
VDD51
VDD52
VDD53
VDD54
+CP U_COR E+CP U_COR E
V12
V14
W4
Y2
J15
K16
L15
M16
P16
T16
U15
V16
+1.8V
H25
J17
K18
K21
K23
K25
L17
M18
M21
M23
M25
N17
P18
P21
P23
P25
R17
T18
T21
T23
T25
U17
V18
V21
V23
V25
Y25
JP1E
AC4
VDD1
AD2
VDD2
G4
VDD3
H2
VDD4
J9
VDD5
J11
VDD6
J13
VDD7
K6
VDD8
K10
VDD9
K12
VDD10
K14
VDD11
L4
VDD12
L7
VDD13
L9
VDD14
L11
VDD15
L13
VDD16
M2
C C
B B
VDD17
M6
VDD18
M8
VDD19
M10
VDD20
N7
VDD21
N9
VDD22
N11
VDD23
P8
VDD24
P10
VDD25
R4
VDD26
R7
VDD27
R9
VDD28
R11
VDD29
T2
VDD30
T6
VDD31
T8
VDD32
T10
VDD33
T12
VDD34
T14
VDD35
U7
VDD36
U9
VDD37
U11
VDD38
U13
VDD39
V6
VDD40
V8
VDD41
V10
VDD42
FOX_PZ63823-284S-41F
Athlon 64 S1
Processor Socket
Athlon 64 S1
Processor Socket
J6
VSS66
J8
VSS67
J10
VSS68
J12
VSS69
J14
VSS70
J16
VSS71
J18
VSS72
K2
VSS73
K7
VSS74
K9
VSS75
K11
VSS76
K13
VSS77
K15
VSS78
K17
VSS79
L6
VSS80
L8
VSS81
L10
VSS82
L12
VSS83
L14
VSS84
L16
VSS85
L18
VSS86
M7
VSS87
M9
VSS88
M11
VSS89
M17
VSS90
N4
VSS91
N8
VSS92
N10
VSS93
N16
VSS94
N18
VSS95
P2
VSS96
P7
VSS97
P9
und
und
VSS98
und
und
P11
VSS99
P17
VSS100
R8
VSS101
R10
Gr o
Gr o
VSS102
Gr o
Gr o
R16
VSS103
R18
VSS104
T7
VSS105
T9
VSS106
T11
VSS107
T13
VSS108
T15
VSS109
T17
VSS110
U4
VSS111
U6
VSS112
U8
VSS113
U10
VSS114
U12
VSS115
U14
VSS116
U16
VSS117
U18
VSS118
V2
VSS119
V7
VSS120
V9
VSS121
V11
VSS122
V13
VSS123
V15
VSS124
V17
VSS125
W6
VSS126
Y21
VSS127
Y23
VSS128
N6
VSS129
2
+CPU_ CORE
1
2
C29
10U_0 805_10V6M
CPU SOCKET S1 DECOUPLING
+CP U_COR E
22U_0 805_6.3 V
+CP U_COR E
0.22 U_0603_ 10V7K
DECOUPLING BETWEEN PROCESSOR AND DIMMs
PLACE CLOSE TO PROCESSOR AS POSSIBLE
+1.8V
1
2
1
2
+0.9V
1
2
C30
10U_0 805_10V6M
1
2
22U_0 805_6.3 V
1
1
C36
2
2
0.22 U_0603_ 10V7K
1
1
C45
2
2
C54
4.7U_ 0805 _10V4Z
C61
0.22 U_040 2_10V4Z
C66
4.7U_ 0805 _10V4Z
0125 Cost down $0.155
1
+
C25
330U_ 4V_M
2
1
2
C31
10U_0 805_10V6M
1
C38
C37
2
22U_0 805_6.3 V
180P _0402_50V8J
1
C46
C47
2
0.01 U_0402_ 16V7K
1
C55
4.7U_ 0805 _10V4Z
2
1
C62
0.01 U_0402_ 16V7K
2
1
C67
4.7U_ 0805 _10V4Z
2
C32
10U_0 805_10V6M
1
2
22U_0 805_6.3 V
1
C39
2
1
C48
2
1
+
C26
330U_ 4V_M
2
1
2
C33
10U_0 805_10V6M
1
C40
2
22U_0 805_6.3 V
1
C49
180P _0402_50V8J
2
1
C56
4.7U_ 0805 _10V4Z
2
1
C63
0.01 U_0402_ 16V7K
2
1
C68
4.7U_ 0805 _10V4Z
2
C34
10U_0 805_10V6M
1
2
22U_0 805_6.3 V
1
C41
2
1
2
1
2
1
+
2
1
2
C35
10U_0 805_10V6M
1
2
22U_0 805_6.3 V
C57
4.7U_ 0805 _10V4Z
1
C64
180P_0402 _50V8J
2
C69
4.7U_ 0805 _10V4Z
C27
330U_ 4V_M
22U_0 805_6.3 V
C42
1
C43
2
+1.8V
10U_0 805_10V6M
1
2
1
C58
0.22 U_040 2_10V4Z
2
1
2
1
C70
0.22 U_040 2_10V4Z
2
1
C44
22U_0 805_6.3 V
2
C50
C65
180P_0402 _50V8J
+CPU_ CORE
1
+
2
1
C51
2
10U_0 805_10V6M
1
C59
0.22 U_040 2_10V4Z
2
1
C71
0.22 U_040 2_10V4Z
2
C28
820U_ E9_2 .5V_M_R7
45@
0.22 U_040 2_10V4Z
1
C52
2
1
C60
0.22 U_040 2_10V4Z
2
1
C72
0.22 U_040 2_10V4Z
2
1
C53
0.22 U_040 2_10V4Z
2
1
C73
0.22 U_040 2_10V4Z
2
1
C76
1000P_040 2_50V7K
2
Compal Secret Data
Deciphered Date
2
1
C77
1000P_040 2_50V7K
2
1
1
2
A A
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
C75
C74
1000P_040 2_50V7K
1000P_040 2_50V7K
2
2007/01/07 2008/01/12
1
C78
180P_0402 _50V8J
2
1
C79
180P_0402 _50V8J
2
Title
Size Docume nt Numb er Rev
C
Date : Sheet o f
1
1
C80
180P_0402 _50V8J
2
2
AMD CPU PWR & GND
LA-3 733P
C81
180P_0402 _50V8J
1
0.1
7 36Monda y, M arch 05, 2007
5
DDR_ CKE0_ DIMMA5
DDR_ CS2_D IMMA#5
DDR_ A_BS#25
DDR_ A_BS#05
DDR_ A_WE #5
DDR_ A_CAS #5
DDR_ CS1_D IMMA#5
DDR_ A_ODT15
MEM_SMBDATA9,15
MEM_SMBCL K9,15
DD R_A_D [0..6 3]
DD R_A_D M[0..7 ]
DDR _A_ DQS[0 ..7]
DDR_ A_MA[0 ..15]
DD R_A_D QS#[0 ..7]
DDR_ A_D0
DDR_ A_D1
DDR_ A_DQS #0
DDR_ A_DQS 0
DDR_ A_D2
DDR_ A_D3
DDR_ A_D8
DDR_ A_D9
DDR_ A_DQS #1
DDR_ A_DQS 1
DDR_ A_D10
DDR_ A_D11
DDR_ A_D16
DDR_ A_D17
DDR_ A_DQS #2
DDR_ A_DQS 2
DDR_ A_D18 DDR_ A_D22
DDR_ A_D19
DDR_ A_D24
DDR_ A_D25
DDR_ A_DM3
DDR_ A_D26
DDR_ A_D27
DDR_ CKE0_ DIMMA
DDR_ CS2_D IMMA#
DDR_ A_BS#2
DDR_ A_MA12
DDR_ A_MA9
DDR_ A_MA5
DDR_ A_MA3
DDR_ A_MA1
DDR_ A_MA10
DDR_ A_BS#0
DDR_ A_WE#
DDR_ A_CAS #
DDR_ CS1_D IMMA#
DDR_ A_ODT1
DDR_ A_D32
DDR_ A_D33
DDR_ A_DQS #4
DDR_ A_DQS 4
DDR_ A_D34
DDR_ A_D35
DDR_ A_D40
DDR_ A_D41
DDR_ A_DM5
DDR_ A_D42
DDR_ A_D43 DDR_ A_D47
DDR_ A_D48
DDR_ A_D49 DDR_ A_D53
DDR_ A_DQS #6
DDR_ A_DQS 6
DDR_ A_D50
DDR_ A_D51 DDR_ A_D55
DDR_ A_D56
DDR_ A_D57
DDR_ A_DM7
DDR_ A_D58
DDR_ A_D59
MEM_SMBDATA
MEM_SMBCL K
+3VS
1
C111
0.1U_ 0402_1 6V4Z
2
5
JP4
1
VREF
3
VSS
5
DQ0
7
DQ1
9
VSS
11
DQS0#
13
DQS0
15
VSS
17
DQ2
19
DQ3
21
VSS
23
DQ8
25
DQ9
27
VSS
29
DQS1#
31
DQS1
33
VSS
35
DQ10
37
DQ11
39
VSS
41
VSS
43
DQ16
45
DQ17
47
VSS
49
DQS2#
51
DQS2
53
VSS
55
DQ18
57
DQ19
59
VSS
61
DQ24
63
DQ25
65
VSS
67
DM3
69
NC
71
VSS
73
DQ26
75
DQ27
77
VSS
79
CKE0
81
VDD
83
NC
85
BA2
87
VDD
89
A12
91
A9
93
A8
95
VDD
97
A5
99
A3
101
A1
103
VDD
105
A10/AP
107
BA0
109
WE#
111
VDD
113
CAS#
115
NC/S1#
117
VDD
119
NC/ODT1
121
VSS
123
DQ32
125
DQ33
127
VSS
129
DQS4#
131
DQS4
133
VSS
135
DQ34
137
DQ35
139
VSS
141
DQ40
143
DQ41
145
VSS
147
DM5
149
VSS
151
DQ42
153
DQ43
155
VSS
157
DQ48
159
DQ49
161
VSS
163
NC,TEST
165
VSS
167
DQS6#
169
DQS6
171
VSS
173
DQ50
175
DQ51
177
VSS
179
DQ56
181
DQ57
183
VSS
185
DM7
187
VSS
189
DQ58
191
DQ59
193
VSS
195
SDA
197
SCL
199
VDDSPD
FOX_A S0A426-M2RN -7F
<BOM S tructure>
DIMM1 REV H:4mm (BOT)
DDR _A_D [0..6 3]5
DDR _A_DM [0..7]5
DDR _A_D QS[0. .7]5
DDR_ A_MA[0 ..15]5
DDR _A_D QS#[0. .7]5
D D
C C
B B
A A
DQS3#
NC/CKE1
NC/A15
NC/A14
NC/A13
DQS5#
DQS7#
4
2
VSS
4
DQ4
6
DQ5
8
VSS
10
DM0
12
VSS
14
DQ6
16
DQ7
18
VSS
20
DQ12
22
DQ13
24
VSS
26
DM1
28
VSS
30
CK0
32
CK0#
34
VSS
36
DQ14
38
DQ15
40
VSS
42
VSS
44
DQ20
46
DQ21
48
VSS
50
NC
52
DM2
54
VSS
56
DQ22
58
DQ23
60
VSS
62
DQ28
64
DQ29
66
VSS
68
70
DQS3
72
VSS
74
DQ30
76
DQ31
78
VSS
80
82
VDD
84
86
88
VDD
90
A11
92
A7
94
A6
96
VDD
98
A4
100
A2
102
A0
104
VDD
106
BA1
108
RAS#
110
S0#
112
VDD
114
ODT0
116
118
VDD
120
NC
122
VSS
124
DQ36
126
DQ37
128
VSS
130
DM4
132
VSS
134
DQ38
136
DQ39
138
VSS
140
DQ44
142
DQ45
144
VSS
146
148
DQS5
150
VSS
152
DQ46
154
DQ47
156
VSS
158
DQ52
160
DQ53
162
VSS
164
CK1
166
CK1#
168
VSS
170
DM6
172
VSS
174
DQ54
176
DQ55
178
VSS
180
DQ60
182
DQ61
184
VSS
186
188
DQS7
190
VSS
192
DQ62
194
DQ63
196
VSS
198
SAO
200
SA1
4
DDR_ A_D4
DDR_ A_D5
DDR_ A_DM0
DDR_ A_D6
DDR_ A_D7
DDR_ A_D12
DDR_ A_D13
DDR_ A_DM1
DDR_ A_CLK1
DDR_ A_CLK #1
DDR_ A_D14
DDR_ A_D15
DDR_ A_D20
DDR_ A_D21
DDR_ A_DM2
DDR_ A_D23
DDR_ A_D28
DDR_ A_D29
DDR_ A_DQS #3
DDR_ A_DQS 3
DDR_ A_D30
DDR_ A_D31
DDR_ CKE1_ DIMMA
DDR_ A_MA15
DDR_ A_MA14
DDR_ A_MA11
DDR_ A_MA7
DDR_ A_MA6DDR_ A_MA8
DDR_ A_MA4
DDR_ A_MA2
DDR_ A_MA0
DDR_ A_BS#1
DDR_ A_RAS #
DDR_ CS0_D IMMA#
DDR_ A_ODT0
DDR_ A_MA13
DDR_ CS3_D IMMA#
DDR_ A_D36
DDR_ A_D37
DDR_ A_DM4
DDR_ A_D38
DDR_ A_D39
DDR_ A_D44
DDR_ A_D45
DDR_ A_DQS #5
DDR_ A_DQS 5
DDR_ A_D46
DDR_ A_D52
DDR_ A_CLK2
DDR_ A_CLK #2
DDR_ A_DM6
DDR_ A_D54
DDR_ A_D60
DDR_ A_D61
DDR_ A_DQS #7
DDR_ A_DQS 7
DDR_ A_D62
DDR_ A_D63
R42 10K_0402_5 %
1 2
R43 10K_0402_5 %
1 2
DDR_ A_CLK1 5
DDR_ A_CLK# 1 5
DDR_ CKE1_ DIMMA 5
DDR_ A_BS#1 5
DDR_ A_RAS # 5
DDR_ CS0_D IMMA# 5
DDR_ A_ODT0 5
DDR_ CS3_D IMMA# 5
DDR_ A_CLK2 5
DDR_ A_CLK# 2 5
3
+1.8V+DIMM_ VREF+1.8V+1.8V
C83 0 .1U_04 02_16V4Z
C82 4 .7U_08 05_10V4Z
1
2
12
R40
1
1K_0402_ 1%
2
12
R41
1K_0402_ 1%
2
+1.8V
0.1U_ 0402_1 6V4Z
1
2
C84
+0.9V
+0.9V
0.1U_ 0402_1 6V4Z
1
2
C93
+1.8V
+0.9V
DDR_ A_MA8
DDR_A _MA9
DDR_ A_MA3
DDR_ A_MA5
DDR_ CKE0_ DIMMA
DDR_ CS2_D IMMA#
DDR_ A_MA12
DDR_ A_BS#2
DDR_ A_BS#1
DDR_ A_MA0
DDR_ A_RAS #
DDR_ CS0_D IMMA#
DDR_ A_MA7
DDR_A _MA6
DDR_ A_MA4
DDR_ A_MA2
DDR_ A_ODT0
DDR_ A_MA13
DDR_ CS3_D IMMA#
DDR_ A_CAS #
DDR_ CS1_D IMMA#
DDR_ A_ODT1
DDR_ A_MA1
DDR_ A_MA10
DDR_ A_BS#0
DDR_ A_WE#
DDR_ A_MA15
DDR_ A_MA14
DDR_ CKE1_ DIMMA
DDR_A _MA11
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
RP1
18
27
36
45
47_0 804_8P4R_5%
RP2
18
27
36
45
47_0 804_8P4R_5%
RP3
45
36
27
18
47_0 804_8P4R_5%
RP4
45
36
27
18
47_0 804_8P4R_5%
RP5
45
36
27
18
47_0 804_8P4R_5%
RP6
18
27
36
45
47_0 804_8P4R_5%
RP7
18
27
36
45
47_0 804_8P4R_5%
RP8
45
36
27
18
47_0 804_8P4R_5%
2007/01/07 2008/01/12
Compal Secr et Data
Deciphered Date
220U_ D2_4V M_R15
1
C101
+
2
2
Layout Note:
Plac e one ca p close to every 2 pul lup
resi stors term inated to + 0.9V
0.1U_ 0402_1 6V4Z
0.1U_ 0402_1 6V4Z
1
2
C85
0.1U_ 0402_1 6V4Z
0.1U_ 0402_1 6V4Z
1
2
C94
2.2U_ 0805_ 16V4Z
C102
1
2
0.1U_ 0402_1 6V4Z
0.1U_ 0402_1 6V4Z
1
2
C86
Layout Note:
Plac e one ca p close to every 2 pul lup
resi stors term inated to + 0.9V
0.1U_ 0402_1 6V4Z
1
2
C95
2.2U_ 0805_ 16V4Z
C103
1
2
0.1U_ 0402_1 6V4Z
1
1
2
C87
1
2
C96
2.2U_ 0805_ 16V4Z
1
2
2
C88
C89
0.1U_ 0402_1 6V4Z
0.1U_ 0402_1 6V4Z
1
1
2
2
C98
C97
2.2U_ 0805_ 16V4Z
2.2U_ 0805_ 16V4Z
C104
C105
1
1
2
2
Title
DDR2 SO-DIMM I
Size Doc ument Number Re v
Cus tom
LA- 3733P
Date : Sheet of
1
0.1U_ 0402_1 6V4Z
0.1U_ 0402_1 6V4Z
1
1
2
2
C90
C91
0.1U_ 0402_1 6V4Z
0.1U_ 0402_1 6V4Z
1
1
2
C99
0.1U_ 0402_ 16V4Z
C106
C107
1
1
2
2
C92
1
+
150U _D2_6.3VM
2
2
C100
0.1U_ 0402_ 16V4Z
0.1U_ 0402_ 16V4Z
0.1U_ 0402_ 16V4Z
C108
C109
1
2
1
C110
1
1
2
2
0.1
8 36Monday, Marc h 05, 2 007
5
DDR _B_D [0..6 3]5
DDR _B_DM [0..7]5
DDR _B_D QS[0. .7]5
DDR_ B_MA[0 ..15]5
DDR _B_D QS#[0. .7]5
D D
C C
B B
A A
DD R_B_D [0..6 3]
DD R_B_D M[0..7 ]
DDR _B_ DQS[0 ..7]
DDR_ B_MA[0 ..15]
DD R_B_D QS#[0 ..7]
DDR_ B_D0
DDR_ B_D1
DDR_ B_DQS #0
DDR_ B_DQS 0
DDR_ B_D2
DDR_ B_D3
DDR_ B_D8
DDR_ B_D9
DDR_ B_DQS #1
DDR_ B_DQS 1
DDR_ B_D10
DDR_ B_D11
DDR_ B_D16
DDR_ B_D17
DDR_ B_DQS #2
DDR_ B_DQS 2
DDR_ B_D18 DDR_ B_D22
DDR_ B_D19
DDR_ B_D24
DDR_ B_D25
DDR_ B_DM3
DDR_ B_D26
DDR_ B_D27
DDR_ CKE0_ DIMMB5
DDR_ CS2_D IMMB#5
DDR_ B_BS#25
DDR_ B_BS#05
DDR_ B_WE #5
DDR_ B_CAS #5
DDR_ CS1_D IMMB#5
DDR_ B_ODT15
MEM_SMBDATA8,15
MEM_SMBCL K8,15
DDR_ CKE0_ DIMMB
DDR_ CS2_D IMMB#
DDR_ B_BS#2
DDR_ B_MA12
DDR_ B_MA9
DDR_ B_MA5
DDR_ B_MA3
DDR_ B_MA1
DDR_ B_MA10
DDR_ B_BS#0
DDR_ B_WE#
DDR_ B_CAS #
DDR_ CS1_D IMMB#
DDR_ B_ODT1
DDR_ B_D32
DDR_ B_D33
DDR_ B_DQS #4
DDR_ B_DQS 4
DDR_ B_D34
DDR_ B_D35
DDR_ B_D40
DDR_ B_D41
DDR_ B_DM5
DDR_ B_D42
DDR_ B_D43 DDR_ B_D47
DDR_ B_D48
DDR_ B_D49 DDR_ B_D53
DDR_ B_DQS #6
DDR_ B_DQS 6
DDR_ B_D50
DDR_ B_D51 DDR_ B_D55
DDR_ B_D56
DDR_ B_D57
DDR_ B_DM7
DDR_ B_D58
DDR_ B_D59
MEM_SMBDATA
MEM_SMBCL K
+3VS
1
C139
0.1U_ 0402_1 6V4Z
2
5
JP5
1
VREF
3
VSS
5
DQ0
7
DQ1
9
VSS
11
DQS0#
13
DQS0
15
VSS
17
DQ2
19
DQ3
21
VSS
23
DQ8
25
DQ9
27
VSS
29
DQS1#
31
DQS1
33
VSS
35
DQ10
37
DQ11
39
VSS
41
VSS
43
DQ16
45
DQ17
47
VSS
49
DQS2#
51
DQS2
53
VSS
55
DQ18
57
DQ19
59
VSS
61
DQ24
63
DQ25
65
VSS
67
DM3
69
NC
71
VSS
73
DQ26
75
DQ27
77
VSS
79
CKE0
81
VDD
83
NC
85
BA2
87
VDD
89
A12
91
A9
93
A8
95
VDD
97
A5
99
A3
101
A1
103
VDD
105
A10/AP
107
BA0
109
WE#
111
VDD
113
CAS#
115
NC/S1#
117
VDD
119
NC/ODT1
121
VSS
123
DQ32
125
DQ33
127
VSS
129
DQS4#
131
DQS4
133
VSS
135
DQ34
137
DQ35
139
VSS
141
DQ40
143
DQ41
145
VSS
147
DM5
149
VSS
151
DQ42
153
DQ43
155
VSS
157
DQ48
159
DQ49
161
VSS
163
NC,TEST
165
VSS
167
DQS6#
169
DQS6
171
VSS
173
DQ50
175
DQ51
177
VSS
179
DQ56
181
DQ57
183
VSS
185
DM7
187
VSS
189
DQ58
191
DQ59
193
VSS
195
SDA
197
SCL
199
VDDSPD
FOX_A S0A426-MARG- 7F
Change PCB Footprint
DIMM0 REV H:8mm (BOT)
DQS3#
NC/CKE1
NC/A15
NC/A14
NC/A13
DQS5#
DQS7#
4
2
VSS
4
DQ4
6
DQ5
8
VSS
10
DM0
12
VSS
14
DQ6
16
DQ7
18
VSS
20
DQ12
22
DQ13
24
VSS
26
DM1
28
VSS
30
CK0
32
CK0#
34
VSS
36
DQ14
38
DQ15
40
VSS
42
VSS
44
DQ20
46
DQ21
48
VSS
50
NC
52
DM2
54
VSS
56
DQ22
58
DQ23
60
VSS
62
DQ28
64
DQ29
66
VSS
68
70
DQS3
72
VSS
74
DQ30
76
DQ31
78
VSS
80
82
VDD
84
86
88
VDD
90
A11
92
A7
94
A6
96
VDD
98
A4
100
A2
102
A0
104
VDD
106
BA1
108
RAS#
110
S0#
112
VDD
114
ODT0
116
118
VDD
120
NC
122
VSS
124
DQ36
126
DQ37
128
VSS
130
DM4
132
VSS
134
DQ38
136
DQ39
138
VSS
140
DQ44
142
DQ45
144
VSS
146
148
DQS5
150
VSS
152
DQ46
154
DQ47
156
VSS
158
DQ52
160
DQ53
162
VSS
164
CK1
166
CK1#
168
VSS
170
DM6
172
VSS
174
DQ54
176
DQ55
178
VSS
180
DQ60
182
DQ61
184
VSS
186
188
DQS7
190
VSS
192
DQ62
194
DQ63
196
VSS
198
SAO
200
SA1
4
DDR_ B_D4
DDR_ B_D5
DDR_ B_DM0
DDR_ B_D6
DDR_ B_D7
DDR_ B_D12
DDR_ B_D13
DDR_ B_DM1
DDR_ B_CLK1
DDR_ B_CLK #1
DDR_ B_D14
DDR_ B_D15
DDR_ B_D20
DDR_ B_D21
DDR_ B_DM2
DDR_ B_D23
DDR_ B_D28
DDR_ B_D29
DDR_ B_DQS #3
DDR_ B_DQS 3
DDR_ B_D30
DDR_ B_D31
DDR_ CKE1_ DIMMB
DDR_ B_MA15
DDR_ B_MA14
DDR_ B_MA11
DDR_ B_MA7
DDR_ B_MA6DDR_ B_MA8
DDR_ B_MA4
DDR_ B_MA2
DDR_ B_MA0
DDR_ B_BS#1
DDR_ B_RAS #
DDR_ CS0_D IMMB#
DDR_ B_ODT0
DDR_ B_MA13
DDR_ CS3_D IMMB#
DDR_ B_D36
DDR_ B_D37
DDR_ B_DM4
DDR_ B_D38
DDR_ B_D39
DDR_ B_D44
DDR_ B_D45
DDR_ B_DQS #5
DDR_ B_DQS 5
DDR_ B_D46
DDR_ B_D52
DDR_ B_CLK2
DDR_ B_CLK #2
DDR_ B_DM6
DDR_ B_D54
DDR_ B_D60
DDR_ B_D61
DDR_ B_DQS #7
DDR_ B_DQS 7
DDR_ B_D62
DDR_ B_D63
R44 10K_0 402_5%
1 2
R45 10K_0 402_5%
1 2
4.7U_ 0805_1 0V4Z
DDR_ B_CLK1 5
DDR_ B_CLK# 1 5
DDR_ CKE1_ DIMMB 5
DDR_ B_BS#1 5
DDR_ B_RAS # 5
DDR_ CS0_D IMMB# 5
DDR_ B_ODT0 5
DDR_ CS3_D IMMB# 5
DDR_ B_CLK2 5
DDR_ B_CLK# 2 5
+3VS
3
+DIMM_ VREF+1.8V+1.8V
0.1U_ 0402_1 6V4Z
C113
C112
1
1
2
2
DDR_ B_RAS #
DDR_ CS0_D IMMB#
DDR_ B_BS#1
DDR_ B_MA0
DDR_ B_MA2
DDR_ B_MA4
DDR_B _MA6
DDR_ B_MA7
DDR_ CKE0_ DIMMB
DDR_ CS2_D IMMB#
DDR_ B_BS#2
DDR_ B_MA12
DDR_B _MA8
DDR_ B_MA3
DDR_ B_MA9
DDR_ B_MA5
DDR_ B_MA1
DDR_ B_WE#
DDR_ B_BS#0
DDR_ B_MA10
DDR_ CS1_D IMMB#
DDR_ B_CAS #
DDR_ B_ODT1
DDR_ CS3_D IMMB#
DDR_ B_MA13
DDR_ B_ODT0
DDR_B _MA11
DDR_ B_MA14
DDR_ B_MA15
DDR_ CKE1_ DIMMB
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
+0.9V
0.1U_ 0402_1 6V4Z
0.1U_ 0402_1 6V4Z
1
2
C114
+1.8V
0.1U_ 0402_ 16V4Z
0.1U_ 0402_ 16V4Z
1
2
C122
+0.9V
RP9
47_0 804_8P4R_5%
RP10
47_0 804_8P4R_5%
RP11
47_0 804_8P4R_5%
RP12
47_0 804_8P4R_5%
RP13
47_0 804_8P4R_5%
RP14
47_0 804_8P4R_5%
RP15
47_0 804_8P4R_5%
RP16
47_0 804_8P4R_5%
2007/01/07 2008/01/12
1
2
C115
1
2
C123
45
36
27
18
45
36
27
18
18
27
36
45
18
27
36
45
18
27
36
45
18
27
36
45
45
36
27
18
45
36
27
18
0.1U_ 0402_1 6V4Z
0.1U_ 0402_1 6V4Z
1
2
C116
0.1U_ 0402_ 16V4Z
0.1U_ 0402_ 16V4Z
1
2
C124
+0.9V
Compal Secr et Data
1
2
C117
1
2
C125
Deciphered Date
2
0.1U_ 0402_1 6V4Z
0.1U_ 0402_1 6V4Z
0.1U_ 0402_1 6V4Z
1
1
2
2
C119
C118
0.1U_ 0402_ 16V4Z
0.1U_ 0402_ 16V4Z
0.1U_ 0402_ 16V4Z
1
1
2
2
C127
C126
2
1
0.1U_ 0402_1 6V4Z
1
1
2
C120
1
2
C128
Layout Note:
Plac e one ca p close to every 2 pul lup
2
resi stors term inated to + 0.9V
C121
0.1U_ 0402_ 16V4Z
Layout Note:
1
Plac e one ca p close to every 2 pul lup
resi stors term inated to + 0.9V
2
C129
+1.8V
2.2U_ 0805_1 6V4Z
2.2U_ 0805_1 6V4Z
2.2U_ 0805_1 6V4Z
C130
C131
1
1
2
2
2.2U_ 0805_1 6V4Z
2.2U_ 0805_1 6V4Z
C132
C133
1
1
2
2
Title
DDR2 SO-DIMM II
Size Doc ument Number Re v
Cus tom
LA- 3733P
Date : Sheet of
0.1U_ 0402_1 6V4Z
0.1U_ 0402_1 6V4Z
C134
C135
1
1
2
2
1
0.1U_ 0402_1 6V4Z
0.1U_ 0402_1 6V4Z
C138
C137
C136
1
1
1
2
2
2
0.1
9 36Monday, Marc h 05, 2 007
5
4
3
2
1
U3A
AF16
HT_MCP_RXD0_P
AG16
HT_MCP_RXD0_N
AH16
HT_MCP_RXD1_P
AJ16
HT_MCP_RXD1_N
AJ15
HT_MCP_RXD2_P
AK15
HT_MCP_RXD2_N
AK16
HT_MCP_RXD3_P
AL16
HT_MCP_RXD3_N
AG17
HT_MCP_RXD4_P
AF17
HT_MCP_RXD4_N
AL17
HT_MCP_RXD5_P
AK17
HT_MCP_RXD5_N
AL18
HT_MCP_RXD6_P
AK18
HT_MCP_RXD6_N
AJ19
HT_MCP_RXD7_P
AK19
HT_MCP_RXD7_N
AD14
HT_MCP_RXD8_P
AE14
HT_MCP_RXD8_N
AF14
HT_MCP_RXD9_P
AG14
HT_MCP_RXD9_N
AH14
HT_MCP_RXD10_P
AJ14
HT_MCP_RXD10_N
AL13
HT_MCP_RXD11_P
AK13
HT_MCP_RXD11_N
AC15
HT_MCP_RXD12_P
AD15
HT_MCP_RXD12_N
AD16
HT_MCP_RXD13_P
AE16
HT_MCP_RXD13_N
AE17
HT_MCP_RXD14_P
AD17
HT_MCP_RXD14_N
AB17
HT_MCP_RXD15_P
AC17
HT_MCP_RXD15_N
AJ17
HT_MCP_RX_CLK0_P
AH17
HT_MCP_RX_CLK0_N
AL14
HT_MCP_RX_CLK1_P
AK14
HT_MCP_RX_CLK1_N
AH19
HT_MCP_RXCTL0_P
AG19
HT_MCP_RXCTL0_N
AC18
HT_MCP_RXCTL1_P/RESERVED
AD18
HT_MCP_RXCTL1_N/RESERVED
AC13
THERMTRIP#/GPIO_58
AB13
PROCHOT#/GPIO_20
AB16
+3.3V_PLL_CPU
AB15
+1.2V_PLL_CPU_HT
AM12
HT_MCP_COMP_VDD
AL12
HT_MCP_COMP_GND
MCP67-MV_PBGA836
0.1U_0 402_16V4Z
C141
C144
0.1U_0 402_16V4Z
H_CAD OP0
H_CA DON0
H_CAD OP1
H_CA DON1
H_CAD OP2
H_CA DON2
H_CAD OP3
H_CA DON3
H_CAD OP4
H_CA DON4
H_CAD OP5
H_CA DON5
H_CAD OP6
H_CA DON6
H_CAD OP7
H_CA DON7
H_CAD OP8
H_CA DON8
H_CAD OP9
H_CA DON9
H_CAD OP10
H_CAD ON10
H_CAD OP11
H_CAD ON11
H_CAD OP12
H_CAD ON12
H_CAD OP13
H_CAD ON13
H_CAD OP14
H_CAD ON14
H_CAD OP15
H_CAD ON15
H_CLKOP0
H_CLK ON0
H_CLKOP1
H_CLK ON1
H_CTLOP0
H_CTLON0
+1.2V _PLL_CPU_HT
+1.2V_HT
1 2
R47 150_0402_1%
1 2
R48 150_0402_1%
H_CAD OP04
H_CAD ON04
H_CAD OP14
D D
C C
+3.3V_PLL
4.7U_0 805_10V4Z
B B
+1.2V_HT
L2
1 2
MBK16 08121YZF_0603
10U_0805_10V 4Z
H_CAD ON14
H_CAD OP24
H_CAD ON24
H_CAD OP34
H_CAD ON34
H_CAD OP44
H_CAD ON44
H_CAD OP54
H_CAD ON54
H_CAD OP64
H_CAD ON64
H_CAD OP74
H_CAD ON74
H_CAD OP84
H_CAD ON84
H_CAD OP94
H_CAD ON94
H_CAD OP104
H_CAD ON104
H_CAD OP114
H_CAD ON114
H_CAD OP124
H_CAD ON124
H_CAD OP134
H_CAD ON134
H_CAD OP144
H_CAD ON144
H_CAD OP154
H_CAD ON154
H_CLKOP04
H_CLK ON04
H_CLKOP14
H_CLK ON14
H_CTLOP04
H_CTLON04
H_THERM TRIP#6
PROCHO T#6
1
1
C140
2
2
1
1
C143
2
2
MC P67
PA RT 1 OF 8
HT
RESERVED/HT_MCP_TXCTL1_P
RESERVED/HT_MCP_TXCTL1_N
HT_MCP_TXD0_P
HT_MCP_TXD0_N
HT_MCP_TXD1_P
HT_MCP_TXD1_N
HT_MCP_TXD2_P
HT_MCP_TXD2_N
HT_MCP_TXD3_P
HT_MCP_TXD3_N
HT_MCP_TXD4_P
HT_MCP_TXD4_N
HT_MCP_TXD5_P
HT_MCP_TXD5_N
HT_MCP_TXD6_P
HT_MCP_TXD6_N
HT_MCP_TXD7_P
HT_MCP_TXD7_N
HT_MCP_TXD8_P
HT_MCP_TXD8_N
HT_MCP_TXD9_P
HT_MCP_TXD9_N
HT_MCP_TXD10_P
HT_MCP_TXD10_N
HT_MCP_TXD11_P
HT_MCP_TXD11_N
HT_MCP_TXD12_P
HT_MCP_TXD12_N
HT_MCP_TXD13_P
HT_MCP_TXD13_N
HT_MCP_TXD14_P
HT_MCP_TXD14_N
HT_MCP_TXD15_P
HT_MCP_TXD15_N
HT_MCP_TX_CLK0_P
HT_MCP_TX_CLK0_N
HT_MCP_TX_CLK1_P
HT_MCP_TX_CLK1_N
HT_MCP_TXCTL0_P
HT_MCP_TXCTL0_N
HT_MCP_REQ#
HT_MCP_STOP#
HT_MCP_RST#
HT_MCP_PWRGD
CLKOUT_200MHZ_P
CLKOUT_200MHZ_N
CLKOUT_25MHZ
CPU_SBVREF
CLK200_TERM_GND
H_CA DIP0
AK27
H_C ADIN0
AJ27
H_CA DIP1
AK26
H_C ADIN1
AL26
H_CA DIP2
AK25
H_C ADIN2
AL25
H_CA DIP3
AL24
H_C ADIN3
AK24
H_CA DIP4
AK22
H_C ADIN4
AL22
H_CA DIP5
AK21
H_C ADIN5
AL21
H_CA DIP6
AH21
H_C ADIN6
AJ21
H_CA DIP7
AL20
H_C ADIN7
AM20
H_CA DIP8
AG27
H_C ADIN8
AH27
H_CA DIP9
AF25
H_C ADIN9
AG25
H_CAD IP10
AH25
H_C ADIN10
AJ25
H_CAD IP11
AE23
H_C ADIN11
AF23
H_CAD IP12
AD21
H_C ADIN12
AE21
H_CAD IP13
AF21
H_C ADIN13
AG21
H_CAD IP14
AC20
H_C ADIN14
AD20
H_CAD IP15
AE19
H_C ADIN15
AF19
H_CLK IP0
AK23
H_CL KIN0
AJ23
H_CLK IP1
AG23
H_CL KIN1
AH23
H_CTLIP0
AK20
H_CTL IN0
AJ20
AD19
AC19
HTCPU_R EQ#
AD23
HTCPU_S TOP#
AB20
HTCPU_R ST#
AC21
HTCPU_P WRGD
AD22
AL28
AM28
0208 _chan ge to page 12
AK28
AG28
CLK20 0_TERM_GND
AJ28
R49
2.37K_0402_1%
H_CA DIP0 4
H_C ADIN0 4
H_CA DIP1 4
H_C ADIN1 4
H_CA DIP2 4
H_C ADIN2 4
H_CA DIP3 4
H_C ADIN3 4
H_CA DIP4 4
H_C ADIN4 4
H_CA DIP5 4
H_C ADIN5 4
H_CA DIP6 4
H_C ADIN6 4
H_CA DIP7 4
H_C ADIN7 4
H_CA DIP8 4
H_C ADIN8 4
H_CA DIP9 4
H_C ADIN9 4
H_CAD IP10 4
H_CA DIN10 4
H_CAD IP11 4
H_CA DIN11 4
H_CAD IP12 4
H_CA DIN12 4
H_CAD IP13 4
H_CA DIN13 4
H_CAD IP14 4
H_CA DIN14 4
H_CAD IP15 4
H_CA DIN15 4
H_CLK IP0 4
H_CLK IN0 4
H_CLK IP1 4
H_CLK IN1 4
H_CTLIP0 4
H_CTLIN 0 4
HTCPU_S TOP# 6
HTCPU_R ST# 6
HTCPU_P WRGD 6
CPUCL K 6
CPUCL K# 6
1
12
C142
0.1U_0 402_16V4Z
2
+3VS
12
+1.2V_HT
R46
22K_0402_5%
A A
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2007/01/07 2008/01/12
3
Compal Secret Data
Deciphered Date
Title
MCP67 HT LINK
Size Docume nt Number Re v
Custo m
LA- 3733P
2
Date: Sheet of
10 36Monda y, Marc h 05, 2007
1
0.1
5
D D
C C
B B
L3
1 2
+1.2VS
MBK16 08121YZF_0603
L4
1 2
+1.2VS
MBK16 08121YZF_0603
A A
5
C150
4.7U_0 805_10V4Z
1
2
MINI_CL KREQ#20
C148
4.7U_0 805_10V4Z
1
2
1
C151
0.1U_0 402_16V4Z
2
4.7U_0 805_10V4Z
4
PCIE_WA KE#20
PCIE_RXP120
PCIE_RXN120
4
0209_new card doesn't use
C149
0.1U_0 402_16V4Z
1
2
+3.3V_PLL
1
C152
2
+1.2V_PLL_PE_SS1
+1.2V_PLL_PE1
1
C153
0.1U_0 402_16V4Z
2
PE_CLK_COMP
12
R53
2.37K_0402_1%
3
U3B
MV P67
F23
G23
F24
F25
D25
D26
C28
D28
C29
C30
D29
D30
F26
F27
F28
F29
H23
H24
H25
H26
H27
H28
K24
K25
K27
K26
K28
K29
J31
J30
K31
K30
H17
U31
U30
U29
U28
L29
L30
W27
W28
M26
M27
U26
U27
N23
N22
U25
U24
N30
N31
R22
U23
P31
P30
T22
V31
P26
P27
U22
V30
U19
U20
R20
R19
P19
P20
V24
PA RT 2 OF 8
PE0_RX0_P
PE0_RX0_N
PE0_RX1_P
PE0_RX1_N
PE0_RX2_P
PE0_RX2_N
PE0_RX3_P
PE0_RX3_N
PE0_RX4_P
PE0_RX4_N
PE0_RX5_P
PE0_RX5_N
PE0_RX6_P
PE0_RX6_N
PE0_RX7_P
PE0_RX7_N
PE0_RX8_P
PE0_RX8_N
PE0_RX9_P
PE0_RX9_N
PE0_RX10_P
PE0_RX10_N
PE0_RX11_P
PE0_RX11_N
PE0_RX12_P
PE0_RX12_N
PE0_RX13_P
PE0_RX13_N
PE0_RX14_P
PE0_RX14_N
PE0_RX15_P
PE0_RX15_N
PE_WAKE#/GPIO_21
PE0_PRSNTX1#/DDC_CLK1
PE0_PRSNTX4#/DDC_DATA1
PE0_PRSNTX8#/EXP_EN
PE0_PRSNTX16#
PE1_RX_P
PE1_RX_N
PEA_CLKREQ#
PEA_PRSNT#
PE2_RX_P
PE2_RX_N
PEB_CLKREQ#
PEB_PRSNT#
PE3_RX_P
PE3_RX_N
PEC_CLKREQ#
PEC_PRSNT#
PE4_RX_P
PE4_RX_N
PED_CLKREQ#/GPIO_16
PED_PRSNT#
PE5_RX_P
PE5_RX_N
PEE_CLKREQ#/GPIO_17
PEE_PRSNT#
PE6_RX_P
PE6_RX_N
PEF_CLKREQ#/GPIO_18
PEF_PRSNT#
+1.2V_PLL_PE_SS1
+1.2V_PLL_PE_SS2
+1.2V_PLL_PE1
+1.2V_PLL_PE2
+3.3V_PLL_PE_SS1
+3.3V_PLL_PE_SS2
PE_CLK_COMP
MCP67-MV_PBGA836
Security Classification
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PCIE GFX I/F
Issued Date
3
D24
PE0_TX0_P
C24
PE0_TX0_N
A24
PE0_TX1_P
B24
PE0_TX1_N
B25
PE0_TX2_P
C25
PE0_TX2_N
B26
PE0_TX3_P
C26
PE0_TX3_N
C27
PE0_TX4_P
D27
PE0_TX4_N
A28
PE0_TX5_P
B28
PE0_TX5_N
A29
PE0_TX6_P
B29
PE0_TX6_N
A30
PE0_TX7_P
B30
PE0_TX7_N
B31
PE0_TX8_P
B32
PE0_TX8_N
C31
PE0_TX9_P
C32
PE0_TX9_N
D31
PE0_TX10_P
D32
PE0_TX10_N
E31
PE0_TX11_P
E30
PE0_TX11_N
F31
PE0_TX12_P
F30
PE0_TX12_N
G29
PE0_TX13_P
G30
PE0_TX13_N
H29
PE0_TX14_P
H30
PE0_TX14_N
H32
PE0_TX15_P
H31
PE0_TX15_N
R29
PE0_REFCLK_P
R30
PE0_REFCLK_N
PCIE_TXP1_R
M28
PE1_TX_P
PCIE_TXN1_R
M29
PE1_TX_N
T32
PE1_REFCLK_P
T31
PE1_REFCLK_N
M24
PE2_TX_P
M25
PE2_TX_N
T29
PE2_REFCLK_P
T30
PE2_REFCLK_N
M22
PE3_TX_P
M23
PE3_TX_N
T27
PE3_REFCLK_P
T28
PE3_REFCLK_N
M30
PE4_TX_P
M31
PE4_TX_N
T25
PE4_REFCLK_P
T26
PE4_REFCLK_N
P29
PE5_TX_P
P28
PE5_TX_N
T23
PE5_REFCLK_P
T24
PE5_REFCLK_N
P24
PE6_TX_P
P25
PE6_TX_N
P23
PE6_REFCLK_P
R23
PE6_REFCLK_N
W30
PEX_RST#
W29
PEX_RST1#
2007/01/07 2008/01/12
C145 0.1U _0402_16V7K
C146 0.1U _0402_16V7K
R52 0_0402_5%
1 2
Compal Secret Data
Deciphered Date
1 2
1 2
PE_RST0#
PCIE_R ST1#
2
PCIE_TXP1 20
PCIE_TXN1 20
CLK_P CIE_MCARD 20
CLK_P CIE_MCARD# 20
1
MINI CARD
01/24
+3VALW
HT_VLD15,26
HT_VLD
PE_RST0#
2
2
1
R51 0_0402_5%
1 2
PCIE_R ST1# 20
FOR MINI CARD
Title
Size Docume nt Number Re v
Custo m
Date: Sheet of
5
U4
P
B
4
Y
A
G
NC7SZ0 8P5X_NL_SC70-5
3
@
MCP67 PC IE LINK
LA- 3733P
1
C147
0.1U_0 402_16V4Z
2
PCIE_R ST#
PCIE_R ST# 20
FOR LAN, ID E
1
11 36Monda y, Marc h 05, 2007
0.1
5
01/24
1
C156
2
+3.3V_PLL
4.7U_0 805_10V4Z
L7
MBK16 08121YZF_0603
1
1
C170
2
2
0.1U_0 402_16V4Z
5
12
L5
MBK16 08121YZF_0603
C157
1
0.1U_0 402_16V4Z
2
+3VS
C171
1U_04 02_6.3V4Z
C161
1
2
1 2
L8
4.7U_0 805_10V4Z
01/24
+3VALW
C162
1
0.1U_0 402_16V4Z
2
MBK16 08121YZF_0603
C172
1
2
+3VS
C177
4.7U_0 805_10V4Z
D D
4.7U_0 805_10V4Z
C C
+1.8VS
C169
0.1U_0 402_16V4Z
12
1
2
B B
A A
4
MII_RXD021
MII_RXD121
MII_RXD221
MII_RXD321
MII_RXCLK21
MII_RXDV21
MII_RXER21
MII_COL21
MII_C RS21
R58 10K_0402_5%
12
R60 49.9_0402_1%
1 2
1 2
R61 49.9_0402_1%
R63 124_0402_1%
1 2
1 2
C159 0.01U_0402_16 V7K
1 2
R64 124_0402_1%
1 2
C160 0.01U_0 402_16V7K
Y1
1 2
27MHZ_20P_7A270000 10
1
C165
18P_0402_50V8J
2
ENABLT18
R72 22K_0402_5%
R73 6.2K_0402_5%
R74 10K_0402_5%
+3VS
0125 checklist
1
C178
2
0.1U_0 402_16V4Z
4
R67 0_0402_5%@
1 2
1 2
1 2
C174
1
0.1U_0 402_16V4Z
2
1K_0402_1%
INV_PWM18,27
ENAVD D18
1
C173
0.1U_0 402_16V4Z
2
1
2
1
2
1 2
+1.8V _IFP_MCP
+3.3V _PLL_IFPP
R78
@
MII_RXD0
MII_RXD1
MII_RXD2
MII_RXD3
MII_RXCLK
MII_RXDV
MII_RXER
MII_COL
MII_C RS
MII_COMP_3P3V
MII_COMP _GND
RGB_DA C_RSET
RGB_DA C_VREF
TV_DAC_RSET
TV_DAC_ VREF
NB_XTALIN
NB_XTALOUT
C166
18P_0402_50V8J
12
HDMI_RS ET
1
2
3
U3C
B20
RGMII_RXD0/MII_RXD0
C20
RGMII_RXD1/MII_RXD1
E19
RGMII_RXD2/MII_RXD2
F19
RGMII_RXD3/MII_RXD3
G19
RGMII_RXC/MII_RXCLK
J20
RGMII_RXCTL/MII_RXDV
C19
MII_RXER/GPIO_36
J18
MII_COL/MI2C_DATA
D19
MII_CRS/MI2C_CLK
B18
RGMII/MII_INTR/GPIO35
N13
+3.3V_PLL_MAC_DUAL
B17
MII_COMP_3P3V
C17
MII_COMP_GND
K21
RGB_DAC_RSET
D21
RGB_DAC_VREF
E23
TV_DAC_RSET
H22
TV_DAC_VREF
N15
+3.3V_PLL_DISP
E17
TV_XTALIN
F17
TV_XTALOUT
U11
GPIO_6/FERR//SYS_SERR/IGPU_GPIO_6*
T11
GPIO_7/NFERR//SYS_PERR/IGPU_GPIO_7*
AD24
LCD_BKL_CTL
AE25
LCD_BKL_ON
AE27
LCD_PANEL_PWR
AL29
HDMI_TXC_P
AM29
HDMI_TXC_N
AK29
HDMI_TXD0_P
AJ29
HDMI_TXD0_N
AM30
HDMI_TXD1_P
AL30
HDMI_TXD1_N
AK30
HDMI_TXD2_P
AJ30
HDMI_TXD2_N
AE26
HPLUG_DET3
AL32
HPLUG_DET2
AD25
HDCP_ROM_SCLK
AC26
HDCP_ROM_SDATA
AC24
+1.8V_IFPA
AC25
+1.8V_IFPB
AC23
+3.3V_IFPAB_HVDD
AC22
+3.3V_HDMI_PLL_HVDD
AH29
+3.3V_HDMI
AK31
HDMI_RSET
AK32
HDMI_VPROBE
MCP67-MV_PBGA836
C175
@
0.1U_0 402_16V4Z
Security Classification
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
MCP 67
PART 3 OF 8
LAN
DACS
+3.3V_DUAL_RMGT
+1.2V_DUAL_RMGT
RGMII_TXD0/MII_TXD0
RGMII_TXD1/MII_TXD1
RGMII_TXD2/MII_TXD2
RGMII_TXD3/MII_TXD3
RGMII_TXCLK/MII_TXCLK
RGMII_TXCTL/MII_TXEN
RGMII/MII_PWRDWN#/GPIO_37
RGB_DAC_GREEN
RGB_DAC_HSYNC
RGB_DAC_VSYNC
FLAT PANEL
2007/01/07 2008/01/12
3
RGMII/MII_MDC
RGMII/MII_MDIO
BUF_25MHZ
MII_RESET#
MII_VREF
RGB_DAC_RED
RGB_DAC_BLUE
DDC_CLK0
DDC_DATA0
+3.3V_RGB_DAC
+3.3V_TV_DAC
TV_DAC_RED
TV_DAC_GREEN
TV_DAC_BLUE
IFPA_TXC_P
IFPA_TXC_N
IFPA_TXD0_P
IFPA_TXD0_N
IFPA_TXD1_P
IFPA_TXD1_N
IFPA_TXD2_P
IFPA_TXD2_N
IFPA_TXD3_P
IFPA_TXD3_N
IFPB_TXC_P
IFPB_TXC_N
IFPB_TXD4_P
IFPB_TXD4_N
IFPB_TXD5_P
IFPB_TXD5_N
IFPB_TXD6_P
IFPB_TXD6_N
IFPB_TXD7_P
IFPB_TXD7_N
DDC_CLK2
DDC_DATA2
DDC_CLK3
DDC_DATA3
IFPAB_RSET
IFPAB_VPROBE
L14
N18
J19
K19
L19
L18
H19
K18
K20
L20
D17
0208 _chan ge fr om page 10
G17
C18
H20
B21
C21
B22
G21
H21
G8
H8
E21
F21
C23
C22
D23
AE30
AE31
AC30
AC29
AC27
AC28
AD30
AD29
AD31
AD32
AJ31
AJ32
AE28
AE29
AF30
AF31
AG30
AG29
AH31
AH30
L21
J22
L22
K22
AB31
AB30
0.01U_0402_16 V7K
Compal Secret Data
Deciphered Date
C163
0.1U_0 402_16V4Z
IFPAB_ RSET
IFPAB_ PROBE
R54 0_0603_5%
R55 0_0603_5%
MII_TXD0
MII_TXD1
MII_TXD2
MII_TXD3
MII_TXCLK_R
0130 _same name
MII_MDC
MII_MDIO
MII_PW RDWN
MII_RESET#
1
2
TV_CRMA
TV_LUMA
TV_COMPS
LVDSAC+
LVDSAC-
LVDSA0+
LVDSA0ÂLVDSA1+
LVDSA1ÂLVDSA2+
LVDSA2-
LVDSBC+
LVDSBC-
LVDSB0+
LVDSB0-
LVDSB1+
LVDSB1-
LVDSB2+
LVDSB2-
LCD_CLK
LCD_DA T
DDC_DA TA3
1
C176
@
2
2
1 2
1 2
1 2
R5622_0402_5%
1 2
R33422_0402_5%
CRT_R 19
CRT_G 19
CRT_B 19
CRT_ HSYNC 19
CRT_V SYNC 19
3VDD CCL 19
3VDD CDA 19
C164
4.7U_0 805_10V4Z
1
2
R77 10K_0402_5%
2
LVDSAC+ 18
LVDSAC- 18
LVDSA0+ 18
LVDSA0- 18
LVDSA1+ 18
LVDSA1- 18
LVDSA2+ 18
LVDSA2- 18
LVDSBC+ 18
LVDSBC- 18
LVDSB0+ 18
LVDSB0- 18
LVDSB1+ 18
LVDSB1- 18
LVDSB2+ 18
LVDSB2- 18
LCD_CL K 18
LCD_DA TA 18
1 2
12
R79
@
1K_0402_1%
1
2
TV_CRMA 19
TV_LUMA 19
TV_COMPS 19
01/24
+3VALW
01/24
+1.2VALW+3VALW
C155
1
MII_TXD0 21
MII_TXD1 21
MII_TXD2 21
2
0.1U_0 402_16V4Z
MII_TXD3 21
MII_TXCLK 21
MII_TXEN 21
MII_MDC 21
MII_MDIO 21
MII_PW RDWN# 21
MII_RESE T# 21
C158
1
0.1U_0 402_16V4Z
2
C167
0.1U_0 402_16V4Z
C168
1
4.7U_0 805_10V4Z
2
+3VS
Title
Size Docume nt Number Re v
Custo m
Date: Sheet of
C154
1
0.1U_0 402_16V4Z
2
01/24
+3VALW
12
R59
1.47K_0402_1%
12
R62
1.47K_0402_1%
L6
1 2
MBK20 12121YZF_0805
CRT_R
R65 150_0402_1%
CRT_G
CRT_B
TV_CRMA
TV_LUMA
TV_COMPS
LCD_CLK
LCD_DA T
1 2
R66 150_0402_1%
1 2
R68 150_0402_1%
1 2
R69
1 2
R70
1 2
R71
1 2
CLOS E to CHIP
MCP67 LAN/ CRT/ LVDS
LA- 3733P
1
MII_MDIO
+3VS
1
1 2
R57 1.5K_0402_5%
150_0402_1%
150_0402_1%
150_0402_1%
+3VS
R752.7K_0402_5%
12
R762.7K_0402_5%
12
12 36Monda y, Marc h 05, 2007
01/24
+3VALW
0.1
5
4
3
2
1
RP17
PCI_REQ#0
1 8
+3VS
D D
+3VS
+3VS
+3VS
C C
+3VS
B B
PCI_REQ#1
2 7
PCI_REQ#2
3 6
PCI_REQ#3
4 5
8.2K_1206_8P4R_5%
RP18
PCI_PIRQG#
1 8
PCI_PI RQH#
2 7
PCI_PIRQE #
3 6
PCI_P IRQF#
4 5
8.2K_1206_8P4R_5%
RP20
PCI_SERR#
1 8
PCI_STOP#
2 7
PCI_FRAME#
3 6
PCI_T RDY#
4 5
8.2K_1206_8P4R_5%
RP21
PCI_DEVSEL#
1 8
PCI_PERR#
2 7
PCI_ IRDY#
3 6
4 5
8.2K_1206_8P4R_5%
R332 8.2K_0402_5%
1 2
R333 8.2K_0402_5%
1 2
PCI_REQ#4
CLKRU N#
LPC_DRQ#0
SIRQ
SIRQ27
CLKRU N#
IDE_IR Q20
IDE_IO R#20
IDE _D[15..0]
IDE_IO R#
1 2
R92 33_0402_5%
R93 15K_0402_5%
9/21 Add 33ohm for IDE_IOR#
IDE_D [15..0]20
IDE_DRE Q20
IDE_ IORDY20
PCI_REQ#0
PCI_REQ#1
PCI_REQ#2
PCI_REQ#3
PCI_REQ#4
PCI_AD0
PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD6
PCI_AD7
PCI_AD8
PCI_AD9
PCI_AD10
PCI_AD11
PCI_AD12
PCI_AD13
PCI_AD14
PCI_AD15
PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20
PCI_AD21
PCI_AD22
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30
PCI_AD31
PCI_PIRQE #
PCI_P IRQF#
PCI_PIRQG#
PCI_PI RQH#
PCI_T RDY#
IDE_D0
IDE_D1
IDE_D2
IDE_D3
IDE_D4
IDE_D5
IDE_D6
IDE_D7
IDE_D8
IDE_D9
IDE_D10
IDE_D11
IDE_D12
IDE_D13
IDE_D14
IDE_D15
IDE_DR EQ
IDE_I RQ
IDE_ IORDY
12
U3D
E10
PCI_REQ0#
G10
PCI_REQ1#
J10
PCI_REQ2#/GPIO_40/RS232_ DSR#
M11
PCI_REQ3#/GPIO_38/RS232_ CTS#
E8
PCI_REQ4#/GPIO_52/RS232_ SIN#
D10
PCI_AD0
B10
PCI_AD1
C10
PCI_AD2
L12
PCI_AD3
K11
PCI_AD4
J11
PCI_AD5
D11
PCI_AD6
C11
PCI_AD7
J12
PCI_AD8
H12
PCI_AD9
G12
PCI_AD10
F12
PCI_AD11
E12
PCI_AD12
D12
PCI_AD13
C12
PCI_AD14
B12
PCI_AD15
G14
PCI_AD16
E14
PCI_AD17
D14
PCI_AD18
J15
PCI_AD19
C14
PCI_AD20
D15
PCI_AD21
K15
PCI_AD22
C15
PCI_AD23
L16
PCI_AD24
G16
PCI_AD25
J16
PCI_AD26
E16
PCI_AD27
H16
PCI_AD28
D16
PCI_AD29
F16
PCI_AD30
A16
PCI_AD31
L17
PCI_INTW#
J17
PCI_INTX#
B16
PCI_INTY#
K17
PCI_INTZ#
K14
PCI_TRDY#
C6
LPC_DRQ1#/GPIO19/FANR PM1
B6
LPC_DRQ0#/GPIO_50
D6
LPC_SERIRQ
D5
LPC_CLKRUN/GPIO_42
AF10
IDE_DATA_P0
AL9
IDE_DATA_P1
AK8
IDE_DATA_P2
AK7
IDE_DATA_P3
AK6
IDE_DATA_P4
AJ6
IDE_DATA_P5
AL5
IDE_DATA_P6
AL4
IDE_DATA_P7
AJ5
IDE_DATA_P8
AK5
IDE_DATA_P9
AL6
IDE_DATA_P10
AJ7
IDE_DATA_P11
AJ8
IDE_DATA_P12
AL8
IDE_DATA_P13
AK9
IDE_DATA_P14
AG10
IDE_DATA_P15
AK11
IDE_DREQ_P
AH10
IDE_INTR_P
AK10
IDE_RDY_P
AL10
IDE_IOR_P#
AF12
CABLE_DET_P/GPIO_63
MCP67-MV_PBGA836
MC P67
PART 4 OF 8
PCI_GNT4#/GPIO_53/RS232_ SOUT#
PCI
LPC_PWRDW N#/GPIO_54/EXT_NMI#
LP C
IDE
PCI_GNT0#
PCI_GNT1#
PCI_GNT2#/GPIO_41/RS232_ DTR#
PCI_GNT3#/GPIO_39/RS232_ RTS#
PCI_CBE0#
PCI_CBE1#
PCI_CBE2#
PCI_CBE3#
PCI_DEVSEL#
PCI_FRAME#
PCI_IRDY#
PCI_PERR#/GPIO_43/RS232_D CD#
PCI_PAR
PCI_SERR#
PCI_STOP#
PCI_PME#/GPIO_30
PCI_RESET0#
PCI_RESET1#
PCI_RESET2#
PCI_RESET3#
PCI_CLK0
PCI_CLK1
PCI_CLK2
PCI_CLK3
PCI_CLK4
PCI_CLKIN
LPC_FRAME#
LPC_RESET#
LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
LPC_CLK0
LPC_CLK1
IDE_ADDR_P0
IDE_ADDR_P1
IDE_ADDR_P2
IDE_CS1_P#
IDE_CS3_P#
IDE_DACK_P#
IDE_IOW_P#
IDE_COMP_3P3V
IDE_COMP_GND
F10
H10
K10
L10
F8
K12
K13
F14
K16
L13
J14
H14
B14
J13
C13
B13
C16
J9
K9
K8
L9
C9
B9
B8
A8
C8
D8
D7
B3
C7
A4
B4
C4
A3
B5
C5
AG12
AE12
AH12
AJ12
AK12
AJ11
AJ10
AM4
AK4
PCI_CB E#0
PCI_DEVSEL#
PCI_FRAME#
PCI_ IRDY#
PCI_PERR#
PCI_SERR#
PCI_STOP#
PCICLK 0_R
PCICLK 1_R
PCI_CLK4
PCI_CLK IN
CLK_PCI_LP C_R
IDE_A0
IDE_A1
IDE_A2
IDE_CS1#
IDE_CS3#
IDE_DACK#
IDE_IO W#
C411 10P_0402_50V8J@
1 2
C412 10P_0402_50V8J@
1 2
R330 22_0402_5%
1 2
R331 22_0402_5%
1 2
R83 22_0402_5%
C180
1
10P_0402_50V8J@
2
R84 22_0402_5%
1 2
T1PAD
R85 33_0402_5%
1 2
R86 22_0402_5%
1 2
R87 22_0402_5%
1 2
R88 22_0402_5%
1 2
R89 22_0402_5%
1 2
R90 22_0402_5%
1 2
IDE_A0 20
IDE_A1 20
IDE_A2 20
IDE_CS1# 20
IDE_CS3# 20
IDE_DACK# 20
IDE_IO W# 20
0201 _ad d cl k so urc e to debug port
CLK_DEBUG _PORT 20
CLK_LPC_DE BUG 26
1 2
LPC_FRAME#LPC_DRQ#1
LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
LPC_FRAME# 14,20,26 ,27
LPC_RST# 26,27
LPC_AD0 20,26,27
LPC_AD1 20,26,27
LPC_AD2 20,26,27
LPC_AD3 20,26,27
CLK_PCI_LPC 27
+3VS
12
R91
121_0402_1%
12
R94
121_0402_1%
9/20 Added
LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
LPC_DRQ#0
LPC_DRQ#1
SIRQ
CLK_PCI_LP C_R
PCI_CB E#0
PCI_AD31
PCI_AD30
PCI_AD29
PCI_AD28
PCI_AD27
PCI_AD26
PCI_AD25
PCI_AD24
PCI_AD23
PCI_AD22
PCI_AD21
PCI_AD20
PCI_AD19
PCI_AD18
PCI_AD17
PCI_AD16
RP19
1 8
2 7
3 6
4 5
8.2K_1206_8P4R_5%
@
R80 8.2K_0402_5% @
1 2
R81 8.2K_0402_5% @
1 2
R82 10K_0402_5% @
1 2
@
JP6
NC1NC
NC3NC
CLK05CLK1
A3<7>7A1<7>
A3<6>9A1<6>
A3<5>11A1<5>
A3<4>13A1<4>
A3<3>15A1<3>
A3<2>17A1<2>
A3<1>19A1<1>
A3<0>21A1<0>
A2<7>23A0<7>
A2<6>25A0<6>
A2<5>27A0<5>
A2<4>29A0<4>
A2<3>31A0<3>
A2<2>33A0<2>
A2<1>35A0<1>
A2<0>37A0<0>
39
GND
40
GND
41
GND
42
GND
43
GND
S W-CONN A MP 2-76700 4-2 38P
@
Debug Port
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
+3VS
1
2
C179
10P_0402_50V8J
PCI_AD15
PCI_AD14
PCI_AD13
PCI_AD12
PCI_AD11
PCI_AD10
PCI_AD9
PCI_AD8
PCI_AD7
PCI_AD6
PCI_AD5
PCI_AD4
PCI_AD3
PCI_AD2
PCI_AD1
PCI_AD0
A A
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2007/01/07 2008/01/12
Compal Secret Data
Deciphered Date
Title
MCP67 PCI/ LPC/ IDE
Size Do cument Number Rev
Custo m
LA -373 3P
2
Date: Sheet of
1
0.1
13 36Monday, March 05, 2007
5
PLACE SATA AC COUPLING
CAPS CLOSE TO MCP67
1 2
LPC_FRAME# 13,2 0,26,27
SATA_LED#25
+1.2VS
L10
1 2
MBK16 08121YZF_0603
"0"
"1"
"0"
"1"
1
2
5
SATA_STX_C_DRX_P0
SATA_DTX_C_SRX_N0
SATA_DTX_C_SRX_P0
R104
8.2K_0402_5%
@
1 2
LPC_FRAME#
R110
8.2K_0402_5%
1 2
+3VS
12
R126
10K_0402_5%
C190
10U_0 805_10V4Z
FUNCTION
LPC BIOS*
PCI BIOS
SPI BIOS
RESERVED
SATA_LED#
1
2
C191
0.1U_0 402_16V4Z
SATA_TXP020
SATA_TXN020
SATA_RXN0_C20
D D
C C
SATA_RXP0_C20
+3VS +3VS
R103
8.2K_0402_5%
@
1 2
HDA _SDOUT_ ICH
R109
8.2K_0402_5%
1 2
HDA_SDOUT LPC_FRAME
"0"
"0"
"1"
"1"
*DEFAULT
B B
+1.2VS +3VS+1.2V_PLL_SP_V DD
A A
L9
1 2
MBK16 08121YZF_0603
SATA_STX_DRX_P0
C1810.01U_0402_1 6V7K
1 2
SATA_STX_DRX_N0SATA_STX_C_DRX_N0
C1820.01U_0402_1 6V7K
1 2
R123 2.49K_0402_1%
+1.2V _PLL_SP_VDD
1
+3.3V_PLL
2
C185
0.1U_0 402_16V4Z
+3.3V_PLL
4.7U_0 805_10V4Z
1
C192
2
0.1U_0 402_16V4Z
4
4
SATA_LED#
1
C193
2
AE4
AE5
AG5
AG6
AD1
AD2
AE2
AE3
AG4
AG3
AH3
AH2
AG7
AG8
AF2
AF3
AL1
AL2
AK3
AL3
AJ1
AJ2
AK1
AK2
AJ4
D4
W13
V13
R13
P13
1
C194
0.1U_0 402_16V4Z
2
U3E
SATA_A0_TX_P
SATA_A0_TX_N
SATA_A0_RX_N
SATA_A0_RX_P
SATA_A1_TX_P
SATA_A1_TX_N
SATA_A1_RX_N
SATA_A1_RX_P
SATA_B0_TX_P
SATA_B0_TX_N
SATA_B0_RX_N
SATA_B0_RX_P
SATA_B1_TX_P
SATA_B1_TX_N
SATA_B1_RX_N
SATA_B1_RX_P
RESERVED/SATA_C0_TX_P
RESERVED/SATA_C0_TX_N
RESERVED/SATA_C0_RX_N
RESERVED/SATA_C0_RX_P
RESERVED/SATA_C1_TX_P
RESERVED/SATA_C1_TX_N
RESERVED/SATA_C1_RX_N
RESERVED/SATA_C1_RX_P
SATA_TERMP
SATA_LED#/GPIO_57
+1.2V_PLL_SP_VDD
+1.2V_PLL_SP_SS
+3.3V_PLL_SP_SS
+3.3V_PLL_LEG
MCP67-MV_PBGA836
3
MCP 67
PAR 5 OF 8
SATA
USB
RESERVED/USB10_P
RESERVED/USB10_N
RESERVED/USB11_P
RESERVED/USB11_N
RESERVED
RESERVED
USB_RBIAS_GND
USB_OC0#/GPIO_25
USB_OC1#/GPIO_26
USB_OC2#/GPIO_27
USB_OC3#/GPIO_28/MGPIO_1
USB_OC4#/GPIO_29/MGPIO_3
+3.3V_USB_DUAL1
+3.3V_USB_DUAL2
HDA
HDA_SDATA_IN1/GPIO_23/MGPIO_0
HDA_SDATA_IN2/GPIO_24/MGPIO_2
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
HDA_BITCLK
HDA_SDATA_OUT/GPIO_45
HDA_SDATA_IN0/GPIO_22
HDA_RESET#
HDA_SYNC/GPIO_44
HDA_DOCK_EN#/GPIO_51
HDA_DOCK_RST#/GPIO_46
2007/01/07 2008/01/12
3
USB0_P
USB0_N
USB1_P
USB1_N
USB2_P
USB2_N
USB3_P
USB3_N
USB4_P
USB4_N
USB5_P
USB5_N
USB6_P
USB6_N
USB7_P
USB7_N
USB8_P
USB8_N
USB9_P
USB9_N
USB20_P0
U3
USB20_N0
U2
USB20_P1
U4
USB20_N1
U5
USB20_P2
U6
USB20_N2
U7
USB20_P3
V3
USB20_N3
V2
USB20_P4
W4
USB20_N4
W3
USB20_P5
W5
USB20_N5
W6
USB20_P6
W7
USB20_N6
W8
USB20_P7
Y2
USB20_N7
Y3
USB20_P8
AA3
USB20_N8
AA2
USB20_P9
AA5
USB20_N9
AA4
AA7
AA6
AB3
AB2
AC3
AC4
USB_R BIAS_GND
T1
T2
USB_OC#1
T3
USB_OC#2
T4
USB_OC#3
T5
USB_OC#4
T6
Y8
Y9
HDA_ BITCLK_I CH
D2
HDA _SDOUT_ ICH
B1
HDA_ SDIN0
B2
A2
D1
HDA_R ST_ICH#
C2
HDA _SY NC_ICH
C1
D3
C3
Compal Secret Data
Deciphered Date
0305_for MCP67D
R122
1.1K_0402_1%
2
1 2
R95 15K_0402_5%
1 2
R97 15K_0402_5%
1 2
R99 15K_0402_5%
1 2
R101 15K_0402_5%
1 2
R105 15K_0402_5%
1 2
R107 15K_0402_5%
1 2
R111 15K_0402_5%
1 2
R113 15K_0402_5%
1 2
R115 15K_0402_5%
1 2
R117 15K_0402_5%
1 2
USB_OC#0 26
USB_OC#4 26
1 2
R12722_0402_5%
1 2
R12822_0402_5%
1 2
R12922_0402_5%
1 2
R13022_0402_5%
2
1 2
R96 15K_0402_5%
1 2
R98 15K_0402_5%
1 2
R100 15K_0402_5%
1 2
R102 15K_0402_5%
1 2
R106 15K_0402_5%
1 2
R108 15K_0402_5%
1 2
R112 15K_0402_5%
1 2
R114 15K_0402_5%
1 2
R116 15K_0402_5%
1 2
R118 15K_0402_5%
1
C183
0.1U_0 402_16V4Z
2
HDA_B ITCLK_AU DIO 22
HDA_S DOUT_AUD IO 22
HDA_ SDIN0 22
HDA_R ST_AUDIO# 22,27
HDA _SYNC _AUDIO 22
1
USB PORT
USB20_P0 26
USB20_N0 26
NON- USE
NON- USE
NON- USE
USB/B
USB20_P4 26
Connec tor
USB20_N4 26
NON- USE
USB20_P7 26
USB20_N7 26
NON- USE
USB/B
Connec tor
0130 _for easy layout
NON- USE
NON- USE
+3VALW
USB_OC#3
1 2
R119 10K_0402_5%
USB_OC#2
1 2
R120 10K_0402_5%
R121 10K_0402_5%
+3VALW
1
C184
0.1U_0 402_16V4Z
2
HDA_ BITCLK_I CH
HDA _SY NC_ICH
HDA_R ST_ICH#
HDA _SDOUT_ ICH
Title
MCP67 SATA/ USB/ HDAUDIO
Size Docume nt Number Re v
Custo m
LA- 3733P
Date: Sheet of
R124 10K_0402_5%
R125 10K_0402_5%
C186
1
2
10P_0402_50V8J@
10P_0402_50V8J@
1 2
STRAP FOR SIO 14.318MHz
HDA _SY NC_ICH
1 2
HDA_R ST_ICH#
1 2
STRAP FOR MII
C188
C187
1
1
2
2
10P_0402_50V8J@
1
USB_OC#1
C189
1
2
14 36Monda y, Marc h 05, 2007
10P_0402_50V8J@
0.1
5
4
3
2
1
+3VALW
LID#
1 2
R131 10K_0402_5% @
D D
C C
B B
R133 10K_0402_5% @
Clos e To RAM Door
JCMOS1
2 1
PAD-NO SHORT 2 x2m
@
1 2
C196
1U_06 03_10V4Z
2
C197
15P_0402_50V8J
1
1 2
ACIN27,30
+RTCVC C
X1
1 2
25MHZ_20P
+3VS
12
R140
49.9K_0402_1%
LLB#
D2 R B751V_SOD323
R137
1M_0402_5%
12
2
C198
15P_0402_50V8J
1
IDE_RESE T#20
ACI N_R
21
ACI N_R
1 2
R136 47K_0402_5%
GATEA2027
KB_RST#27
R138 0_0402_5%
EC_SC I#27
EC_SMI#27
R139 0_0402_5%
PWR BTN_OUT#27
EC_RSMRS T#27
MCP_PW RGD27
MEM_VLD32
HT_VLD11,26
VGATE27,34
XTALIN
XTALOUT
C199
1 2
15P_0402_50V8J
X2
2
NC
3
NC
32.76 8KHZ_12 .5P_1TJS125DJ2A073
1 2
C201
15P_0402_50V8J
Change P/N SJ100002400
IDE_RE SET#
R134
EC_SMI#
1 2
1 2
1 2
C195
1U_0603_10V 4Z
1 2
1 2
R141 33_0402_5%
EC_RSMRS T#
MEM_VLD
HT_VLD
R148 10K_0402_5%
R150 10K_0402_5%
1
IN
4
OUT
XTALIN_RTC
XTAOUT_RTC
12
12
@
R153
1 2
10M_0402_5%
0_0402_5%@
SIO_PME#
EXT_SMI#
SM_INTR UDER#
LID#
LLB#
PBTN_OUT#
U3F
P6
GPIO_1/PWRDN_OK/SPI_CS1
N11
GPIO_2/NMI/PS2_CLK0
R11
GPIO_3/SMI#/PS2_DATA0
M9
GPIO_4/SCI/INTR/PS2_CLK1
M10
GPIO_5/INIT#/PS2_DATA1
M4
GPIO_12/SUS_STAT#
K7
A20GATE/GPIO_55
K6
KBRDRSTIN#/GPIO_56
M6
SIO_PME#/GPIO_31
P4
EXT_SMI#/GPIO_32
P8
RI#/GPIO33
L3
INTRUDER#
P5
LID#
N10
LLB#
R10
PWRBTN#
P9
RSTBTN#
M5
RTC_RST#
L4
PWRGD_SB
T10
PWRGD
M8
MEM_VLD
P7
MCP_VLD/HT_VLD
M3
CPU_VLD
U9
JTAG_TDI
T8
JTAG_TDO
T7
JTAG_TMS
U8
JTAG_TRST#
T9
JTAG_TCK
H4
XTALIN
H3
XTALOUT
H2
XTALIN_RTC
H1
XTALOUT_RTC
MCP67-MV_PBGA836
MCP 67
PAR 6 OF 8
MS IC
THERM_SID1/GPIO_47/PWR_LED#
SLP_S3#
SLP_RMGT#
SLP_S5#
MCP_VID0/GPIO_13
MCP_VID1/GPIO_14
MCP_VID2/GPIO_15
SPKR
SMB_CLK0
SMB_DATA0
SMB_CLK1/MSMB_CLK
SMB_DATA1/MSMB_DATA
SMB_ALERT#/GPIO_64
THERM#/GPIO_59
THERM_SIC/GPIO_48
THERM_SID0/GPIO_49
FANRPM0/GPIO_60
FANCTL0/GPIO_61
FANCTL1/GPIO_62
MCPVDD_EN/HTVDD_EN
CPUVDD_EN
SPI_CS0/GPIO_10
SPI_CLK/GPIO_11
SPI_DI/GPIO_8
SPI_DO/GPIO_9
SUS_CLK/GPIO_34
BUF_SIO_CLK
TEST_MODE_EN
PKG_TEST
R3
P3
R4
H5
H6
H7
K4
E3
G3
E2
F2
F3
K5
AC14
AB14
AD12
F6
F5
F4
N3
M2
K2
K3
M7
J2
P2
J3
P11
P10
SLP_S3#
SLP_S5#
SB_SPKR
SMBCLK0
SMBDATA0
M_SMBCLK
M_SMBDATA
EC_LID _OUT#
TEST_MODE_EN
PKG_TEST
R154
0_0402_5%
SLP_S3# 27
SLP_S5# 27
SB_SPKR 22
SMBCLK0 20
SMBDATA0 20
MEM_SMBCLK 8,9
MEM_SMBDATA 8,9
EC_LID _OUT# 27
EC_THERM# 6,27
1 2
R143 15K_0402_5%
1 2
R149 10K_0402_5%@
1 2
R151 10K_0402_5%@
1 2
R152 10K_0402_5%@
C200
1
10P_0402_50V8J
@
2
9/25 Added for EMI
12
12
R155
1K_0402_1%
01/24
CPU_ SIC 6
CPU_ SID 6
VLDT_EN 28
VR_ON 27,34
L: U ser M ode B oot Init tab le
H: S afe M ode B oot Init tab le
+3VALW
+3VS
+3VS
R132
10K_0402_5%
1 2
SB_SPKR
R135
10K_0402_5%@
1 2
SMBCLK0
1 2
R142 2.7K_0402_5%
SMBDATA0
1 2
R144 2.7K_0402_5%
EC_LID _OUT#
1 2
R145 2.7K_0402_5%
M_SMBCLK
1 2
R146 2.7K_0402_5%
M_SMBDATA
1 2
R147 2.7K_0402_5%
A A
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2007/01/07 2008/01/12
3
Compal Secret Data
Deciphered Date
Title
MCP67 MISC
Size Docume nt Number Re v
Custo m
LA- 3733P
2
Date: Sheet of
15 36Monda y, Marc h 05, 2007
1
0.1
5
4
3
2
1
22U_0805_6.3V6M
D D
+3VS+3VALW
C224
0.1U_0 402_16V4Z
1
12
R156
0_0603_5%
1
2
C229
C C
0.1U_0 402_16V4Z
2
C223
0.1U_0 402_16V4Z
C230
0.1U_0 402_16V4Z
1
2
1
2
C226
0.1U_0 402_16V4Z
1
1
2
2
C225
0.1U_0 402_16V4Z
1
2
C227
0.1U_0 402_16V4Z
+RTCVC C
0.1U_0 402_16V4Z
1
C228
0.1U_0 402_16V4Z
2
+3.3V_DUA L1
C231
1
2
RTC Battery
+RTCVC C +3VL
0305_Ting suggest_+RTCVCC current limit issue
1. u nder BATT1 batt ery body , no t race no via
2. B ATT1+ /- pi n kee p 80 mil from other component
B B
MCP67-MV POWER STATES
Power Signal S1
A A
R159
1 2
0_0402_5%
5
D3
1
DAN20 2U_SC70
S0
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
3
2
S3
S4/S5
ON
OFF
OFF
ON
OFF
OFF
ON
OFF
OFF
ON
OFF
OFF
ON
OFF
OFF
ON
OFF
OFF
ON
OFF
OFF
ON
OFF
OFF
ON
OFF
OFF
ON
OFF
OFF
ON
OFF
OFF
ON
OFF
OFF
ON
OFF
OFF
JBATT1
BATT1.1
1
+
W=20mils
SUYIN_0 60003F A002TX00NL~D
CON N@
BATT1
ML1220 MAXELL LITHIUM RTC BATTERY
G3
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFFON ON OFF OFF
-+
2
-
4
U3G
V15
+1.2V_RBB1
V16
+1.2V_RBB2
W16
+1.2V_RBB3
W15
+1.2V_RBB4
AJ9
+3.3V1
AG9
+3.3V2
F11
+3.3V3
H11
+3.3V4
L6
+3.3V_DUAL1
L8
+3.3V_DUAL2
N2
+3.3V_VBAT
AD9
GND
AH6
GND
AE32
GND
Y32
GND
AD8
GND
M32
GND
AE18
GND
AB25
GND
AB27
GND
U15
GND
AE11
GND
V27
GND
R27
GND
N27
GND
G27
GND
Y14
GND
F15
GND
V29
GND
AC12
GND
AB19
GND
AM9
GND
AB12
GND
AM8
GND
AF8
GND
AH4
GND
E27
GND
AM31
GND
F22
GND
AF4
GND
AM32
GND
AG11
GND
L15
GND
AD27
GND
P22
GND
AD11
GND
V11
GND
L23
GND
P15
GND
MCP67-MV_PBGA836
MCP 67
PART 7 OF 8
POWER
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
AA22
+1.2V1
+1.2V10
+1.2V11
+1.2V12
+1.2V13
+1.2V14
+1.2V15
+1.2V16
+1.2V17
+1.2V18
+1.2V19
+1.2V2
+1.2V20
+1.2V21
+1.2V22
+1.2V23
+1.2V24
+1.2V25
+1.2V26
+1.2V27
+1.2V28
+1.2V29
+1.2V3
+1.2V4
+1.2V5
+1.2V6
+1.2V7
+1.2V8
+1.2V9
+1.2V_HT1
+1.2V_HT2
+1.2V_HT3
+1.2V_PED1
+1.2V_PED2
+1.2V_PED3
+1.2V_PED4
+1.2V_PED5
+1.2V_PEA1
+1.2V_PEA2
+1.2V_PEA3
+1.2V_PEA4
+1.2V_PEA5
+1.2V_PEA6
+1.2V_PEA7
+1.2V_PEA8
+1.2V_SP_D1
+1.2V_SP_D2
+1.2V_SP_D3
+1.2V_SP_D4
+1.2V_SP_A1
+1.2V_SP_A2
+1.2V_SP_A3
+1.2V_SP_A4
+1.2V_SP_A5
+1.2V_DUAL1
+1.2V_DUAL2
2007/01/07 2008/01/12
V19
W20
Y20
Y19
V17
AB21
AA23
Y30
47U_1 210_6.3V
U17
U18
Y31
W17
Y18
U16
AA24
V18
AA25
AA26
AB22
W18
AB23
AA27
AA28
AA29
W19
AA30
AA31
V20
Y15
Y17
Y16
V23
W25
W24
V22
W26
Y22
Y23
Y27
Y29
Y25
W22
W23
Y24
AE8
AE7
AE9
AE6
0.1U_0 402_16V4Z
AB11
AB10
AD10
AC10
AE10
N16
N17
Compal Secret Data
Deciphered Date
22U_0805_6.3V6M
1
C212
2
C233
0.1U_0 402_16V4Z
+1.2V_HT1
+1.2V_PED
+1.2V_PEA
+1.2V_SP_D
+1.2V_SP_A
C254
1
0.1U_0 402_16V4Z
2
1
C202
2
4.7U_0 805_10V4Z
1
C213
2
4.7U_0 805_10V4Z
+1.2V_HT
1
2
C238
0.1U_0 402_16V4Z
1
2
1
C246
2
1
2
C255
0.1U_0 402_16V4Z
4.7U_0 805_10V4Z
1
1
C204
C203
2
2
0.1U_0 402_16V4Z
4.7U_0 805_10V4Z
1
1
C214
2
2
12
R157
0_0603_5%
C234
1
1U_04 02_6.3V4Z
2
C240
0.1U_0 402_16V4Z
1
1
2
2
C239
0.1U_0 402_16V4Z
C248
1
1
10U_0805_10V 4Z
2
2
C247
0.1U_0 402_16V4Z
L12 M BK2012 121YZF_0805
C256
1
1
4.7U_0 805_10V4Z
2
2
4.7U_0 805_10V4Z
2
0.1U_0 402_16V4Z
1
C205
2
1
C215
C216
2
0.1U_0 402_16V4Z
C235
0.1U_0 402_16V4Z
1
2
1
2
C241
1U_04 02_6.3V4Z
1
2
C249
10U_0 805_10V4Z
1 2
C257
0.1U_0 402_16V4Z
1
1
C207
C206
2
2
0.1U_0 402_16V4Z
0.1U_0 402_16V4Z
0.1U_0 402_16V4Z
1
1
C218
C217
2
2
0.1U_0 402_16V4Z
C237
0.1U_0 402_16V4Z
1
1
2
2
C236
0.1U_0 402_16V4Z
C242
4.7U_0 805_10V4Z
1
2
+1.2VS
Title
Size Docume nt Number Re v
Custo m
Date: Sheet of
1
1
C209
C208
2
2
0.1U_0 402_16V4Z
1
C219
2
0.1U_0 402_16V4Z
+1.2VS
C244
22U_0805_6.3V6M
1
1
2
2
C243
22U_0805_6.3V6M
C250
1
0.1U_0 402_16V4Z
2
C258
0.1U_0 402_16V4Z
1
2
MCP67 POW ER
LA- 3733P
0.1U_0 402_16V4Z
1
C210
2
0.1U_0 402_16V4Z
1
1
C220
2
2
+1.2VS
12
1
2
C245
22U_0805_6.3V6M
1
2
C251
0.1U_0 402_16V4Z
+1.2VALW
C259
0.1U_0 402_16V4Z
1
2
C221
L11
KC FB M-L11-201209-221LMAT_0805
C252
1
10U_0 805_10V4Z
2
1
1
C211
0.1U_0 402_16V4Z
2
1
C222
0.1U_0 402_16V4Z
2
C232
1
150U_D2_6.3V M
+
2
+1.2VS
+1.2VS
12
R158
0_0805_5%
1
2
C253
4.7U_0 805_10V4Z
16 36Monda y, Marc h 05, 2007
0.1
5
U3H
MCP 67
WUSB_VREF
WUSB_CCA_STATUS
WUSB_SERIAL_DATA
WUSB_PHY_RESET*
WUSB_TX_EN
WUSB_RX_EN
WUSB_PHY_ACTIVE
WUSB_STOPC
WUSB_VDD
GND
GND
GND
GROUND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
MCP67-MV_PBGA836
PAR 8 OF 8
AB9
D D
C C
B B
AC6
AC8
AA8
AD3
AD4
AA9
AC5
AC9
L11
V8
H13
N6
AA1
AD13
K23
AM16
AH1
U13
R6
R8
M1
N1
U1
J1
J4
J6
Y13
AE1
Y6
A5
A12
N8
E6
AC11
H15
T17
J21
D18
A20
N4
G6
AG22
P16
T19
AE24
AJ26
AJ24
U32
T20
AM24
AF29
AJ13
AA32
AG13
AE15
F13
AF6
AB4
AG15
E25
AM17
R15
A17
AG24
N20
N24
AM1
AM21
A21
V25
AJ3
L25
P17
H18
L24
AM5
U14
AC16
U10
N29
AM2
AM3
WUSB_PCLK
WUSB_DATA_EN
WUSB_DATA7
WUSB_DATA6
WUSB_DATA5
WUSB_DATA4
WUSB_DATA3
WUSB_DATA2
WUSB_DATA1
WUSB_DATA0
4
AC7
AB8
V9
W11
W10
W9
Y11
Y10
AA11
AA10
R18
GND
H9
GND
R17
GND
A1
GND
D9
GND
AG26
GND
G4
GND
AB6
GND
J25
GND
R25
GND
T16
GND
T15
GND
J29
GND
W14
GND
AD6
GND
AB24
GND
AM13
GND
R16
GND
V6
GND
A13
GND
N32
GND
AM25
GND
F9
GND
N9
GND
AL31
GND
G25
GND
AB18
GND
AH32
GND
D13
GND
N25
GND
A25
GND
R9
GND
R14
GND
AF27
GND
AH8
GND
A32
GND
P14
GND
E29
GND
E32
GND
V10
GND
J23
GND
N14
GND
AB29
GND
E4
GND
AE13
GND
L27
GND
J27
GND
A9
GND
J32
GND
AE20
GND
AJ22
GND
AG18
GND
AG20
GND
V14
GND
F18
GND
F20
GND
D20
GND
E1
GND
V4
GND
J8
GND
F7
GND
T18
GND
J24
GND
A31
GND
Y1
GND
T13
GND
D22
GND
Y4
GND
P18
GND
AJ18
GND
AE22
GND
R24
GND
N19
GND
T14
GND
3
2
1
A A
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2007/01/07 2008/01/12
3
Compal Secret Data
Deciphered Date
Compal Electronics, Inc.
Title
MCP67 GROUND
Size Docume nt Number Re v
Custo m
LA-3733P
2
Date: Sheet of
17 36Monda y, Marc h 05, 2007
1
0.1
5
4
3
2
1
LVDS CONN
D D
L13 0_0805_5 %
1 2
L14 0_0805_5 %
1 2
INVPW R_B+
+LCD VDD
+3VS
C262680P_0402_50V7K
C263680P_0402_50V7K
C C
C264
@
@
@
1
12
12
2
680P_0402_50V7K
EMI request
INVPW R_B+B+
LVDSBC+12
LVDSBC-12
LVDSB0+12
LVDSB0-12
LVDSB1+12
LVDSB1-12
LVDSB2+12
LVDSB2-12
LVDSBC+
LVDSBC-
LVDSB0+
LVDSB0-
LVDSB1+
LVDSB1-
LVDSB2+
LVDSB2-
JP7
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
ACES_88242-4001
CONN @
LVDS connector
SP02000EA00 S W-CONN ACES 88242-4001 40P P1
ACES_88242-4001_40P
0.1U_0 402_16V4Z
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
GND41GND
+LCDV DD
1
1
C260
C261
0.1U_0 402_16V4Z
2
2
2
2
LVDSA2+
4
4
LVDSA2-
6
6
8
8
LVDSA1+
10
10
LVDSA1-
12
12
14
14
LVDSA0+
16
16
LVDSA0-
18
18
20
20
LVDSAC+
22
22
LVDSAC-
24
24
26
26
INVTPWM
28
28
DISP LAYOFF#
30
30
DAC_ BRIG
32
32
LCD_CLK
34
34
LCD_DA T
36
36
38
38
40
40
42
LVDSA2+ 12
LVDSA2- 12
LVDSA1+ 12
LVDSA1- 12
LVDSA0+ 12
LVDSA0- 12
LVDSAC+ 12
LVDSAC- 12
12
C265
@
680P_0402_50V7K
INV_PWM 12,27
DAC_ BRIG 27
LCD_CL K 12
LCD_DA TA 12
12
C266
@
680P_0402_50V7K
BKOFF#27
ENABLT12
CH751H -40PT_SOD323-2
CH751H -40PT_SOD323-2
R161
100K_0402_5%
1 2
+3VS
R160
4.7K_0402_5%
D4
D5
1 2
21
21
DISP LAYOFF#
EMI request
100_0402_5%
2N7002_SOT23-3
C270
R162
Q7
1
2
+LCDV DD
12
13
D
S
2N7002_SOT23-3
+5VALW
R163
47K_0402_5%
1 2
2
G
13
D
2
G
Q8
4
C269
0.047U_0402_ 16V7K
S
1
2
Q6
SI2301 BDS-T1-E3_SOT23-3
1 3
D
G
2
C267
4.7U_0 805_10V4Z
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
+3VS+LCDV DD
S
1
C268
4.7U_0 805_10V4Z
2
2007/01/07 2008/01/12
3
Compal Secret Data
Deciphered Date
Compal Electronics, Inc.
Title
Size Docume nt Number Re v
2
Date: Sheet of
LA -37 33P
LCD CONN.
1
18 36Monda y, Marc h 05, 2007
0.1
B B
R164
ENAVD D12
100K_0402_5%
A A
5
1 2
47K_0402_5%
12
R165
0.1U_0 402_16V4Z
A
B
C
D
E
1 1
2 2
R171
CRT_ HSYNC12
CRT_ VSYNC12
3 3
4 4
1 2
R176
1 2
CRTL_B
CRTL_G
CRTL_ R
CRT_R12
CRT_G12
CRT_B12
+5VS
C278
1 2
0.1U_0 402_16V4Z
0_0402_5%
CRTV SYNC
0_0402_5%
TV-Out Connector
S-Video
TV_LUMA12
TV_CRMA12
TV_COMPS12
A
1
2
5
P
A2Y
G
3
5
P
A2Y
G
3
D7
DAN21 7_SC59
@
2
3
EMI
1
U5
4
OE#
1
U6
4
OE#
1 2
1 2
1 2
D8
D9
1
1
DAN21 7_SC59
DAN21 7_SC59@
@
3
2
3
CRT_R
CRT_G
CRT_B
R166
74AHC T1G125GW_SOT353-5
74AHC T1G125GW_SOT353-5
R177
0_0402_5%
R178
0_0402_5%
R179
0_0402_5%
EMI
Place close to JP6
+3VS
1
2
R167
C272
10P_0402_50V8J@
CRT_ HSYNC _R
CRT _VSYNC_ R
TVLUMA
TVCRMA
1 2
R181
150_0402_1%
B
1 2
150_0402_1%
1 2
R182
1 2
150_0402_1%
150_0402_1%
150_0402_1%
1 2
TVCOMPS
R180
+R_CRT_VCC , +CRTVDD (40mils)
+5VS
+R_CR T_VCC
D10
F1
2 1
RB411 D_SOT23
1.1A_ 6VDC_FUSE
CRT CONNECTOR
EMI
L15
MBK20 12800YZF
1 2
L16
MBK20 12800YZF
1 2
L17
MBK20 12800YZF
1 2
1
2
C273
10P_0402_50V8J@
C283
1
2
R168
1 2
150_0402_1%
C274
10P_0402_50V8J@
R172
1 2
0_0402_5%
R173
1 2
0_0402_5%
EMI
L20
MBC16 08121YZF_0603
1 2
L21
MBC16 08121YZF_0603
1 2
L22
MBC16 08121YZF_0603
1 2
1
1
C284
C285
2
2
270P_0402_50V7K
270P_0402_50V7K
1
2
270P_0402_50V7K
1 2
0_0805_5%
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
EMI
1
2
C275
22P_0402_50V8J
C276
1 2
L18
FBM-L11-160808-800LMT_0603
1 2
L19
FBM-L11-160808-800LMT_0603
R183
TVGND
C
C271
0.1U_0 402_16V4Z
CRTL_ R
CRTL_G
CRTL_B
1
1
2
2
C277
22P_0402_50V8J
22P_0402_50V8J
CRT_ HSYN CRFLCRTH SYNC
CRT_ VSYNC RFL
C279
10P_0402_50V8J
LUMA_CL
CRMA_CL
COMPS_CL
1
1
C286
C287
2
2
330P_0402_50V7K
330P_0402_50V7K
2007/01/07 2008/01/12
Compal Secret Data
21
1
2
R169
2.2K_0402_5%
1
1
2
2
1
C288
2
330P_0402_50V7K
Deciphered Date
+CRTVD D
CONN @
+CRTVDD
R170
2.2K_0402_5%
C280 10P _0402_50V8J
D
1 3
1
2
C281 220P_ 0402_50V8J
1
2
3
4
5
6
7
DC230001300 CONN SUYIN 030107FR007G317ZR 7P S_VIDEO
SUYIN_030107FR007G317ZR_7P
2N7002_SOT23-3
G
2
D
1 3
1
2
C282 220P_ 0402_50V8J
JP9
1
2
3
4
5
8
6
GND
9
7
GND
SUYIN_0 30107F R007G317ZR
CON N@
D
0125 ME r equest
chan ge fo otprint
JP8
6
11
1
16
7
17
12
2
8
13
3
9
DC060001M00 D-CONN 15P D-SUB_F C10510-11505-L
14
4
DC060002300 D-CONN 15P VGA_F 070546FR015S235ZR SUYIN
10
15
5
ALLTO_C10510-115A5-L
Q9
S
2N7002_SOT23-3
Q10
S
R174
R175
G
2
2.2K_0402_5%
2.2K_0402_5%
+3VS
Compal Electronics, Inc.
Title
Size Docume nt Number Re v
Date: Sheet of
EMI
NZQA5V6AXV 5T1_SOT533-5
2
1 5
D6
@
CLOS E TO JP3
3VDD CDA 12
3VDD CCL 12
CRT & TVout Connector
LA -37 33P
19 36Monda y, Marc h 05, 2007
E
43
0.1
A
B
C
D
E
F
G
+5VS
H
Pla cea cap s. n ear ODD CON N.
HDD Connector CD-ROM Connector
+5VS
1 1
1
1
C294
2
2
0.1U_ 0402_ 16V4Z
10U_0 805_ 10V4Z
Pleace near H D CONN (JP23)
+3VS + 3VS _HDD
R1870_08 05_5%@
12
0.1U_ 0402_ 16V4Z
1
C300
@
2
1000 P_040 2_50V7K
Pleace near HD CONN
2 2
C295
1
2
@
C301
1U_06 03_1 0V4Z
1
C296
2
0.1U_ 0402_ 16V4Z
1
C302
@
2
1
C297
2
0.1U_ 0402_ 16V4Z
1
+
C299
@
330U_ 4V_M
2
0125 Cost down $0.155
SUY IN_1 27 043FR 022G2 04ZL _NR
JP10
1
GND
2
A+
3
A-
0.01U _0402 _16V7K
4
GND
SATA_R XN0
5
B-
SATA_R XP0
6
B+
0.01U _0402 _16V7K
7
GND
V33
V33
V33
GND
GND
GND
V5
V5
V5
GND
Reserved
GND
V12
V12
V12
CO NN@
DC010003M00 HOUSING SUYIN 127043FR022G204ZL 22P SATA
SUYIN_127043FR022G204ZL_22P_NR DC030001P00 WAFER OCTEK CDR-50JD1 50P P0.822P SATA
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
Near CONN side.
+3V S_HD D
+5VS
SATA_TXP0
SATA_T XN0
C293
SAT A_RXN0 _C
12
C298
SATA_R XP0_C
12
SATA_TXP0 14
SATA_T XN0 14
SATA _RXN0_ C 14
SATA_R XP0_C 14
IDE_ RESET #15
PCIE _RST#11
R184 0_0 402_5%@
1 2
R185
1 2
33_0 402_5%
IDE_ IO W#13
ID E_ IOR DY13
ID E_IR Q13
+5VS
IDE_ A113
IDE_ A013
IDE_ CS1 #13
R188 10K_ 0402_5 %
+5VS
IDE_ D[0 ..1 5] 13
JP11
1
3
5
IDE_ D7
7
IDE_ D6
9
IDE_ D5
11
IDE_ D4
13
IDE_ D3
15
IDE_ D2
17
IDE_ D1
19
IDE_ D0
21
23
IDE_ IO W#
25
ID E_ IOR DY
27
ID E_I RQ
29
IDE _A1
31
IDE _A0
33
IDE_ CS1 #
35
IDE_ ACT#
12
12
SEC _CSE L
R19 0
470_ 0402_5%
37
39
41
43
45
47
49
51 52
OCT EK_ CDR-5 0JD1
CO NN@
OCTEK_CDR-50JD1_50P
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
IDE_ D8
IDE_ D9
IDE_ D1 0
IDE_ D1 1
IDE_ D1 2
IDE_ D1 3
IDE_ D1 4
IDE_ D1 5
ID E_D REQ
ID E_DR EQ 13
IDE_ IO R#
IDE_ IO R# 13
IDE_ DAC K#
PDIA G#
IDE _A2
IDE_ CS3 #
IDE_ DAC K# 13
R186 100K _0402 _5%
1 2
IDE_ A2 13
IDE_ CS3 # 13
+5VS
0.1U_ 0402_ 16V4Z
C289
1
2
+5VS
ID E_ IOR DY
ID E_D REQ
ID E_I RQ
IDE_ D7
1U_06 03_1 0V4Z
1
C291
C290
2
1 2
R189 4.7K _040 2_5%
1 2
R191 5.6K _040 2_5%
R192 10K _0402_ 5%
1 2
R193 10K _0402_ 5%
10U_0 805_ 10V4Z
1
1
C29 2
10U_0 805_ 10V4Z
2
2
+3VS
12
Mini-Express Card---WLAN
.01U_ 0402_ 16V7K
C303
1
0.1U_ 0402_ 16V4Z
2
C304
+3V S_MINI +1. 5VS_M INI
1
2
4.7U_ 0805_ 10V4Z
1
C305
2
.01U_ 0402_ 16V7K
C306
1
0.1U_ 0402_ 16V4Z
2
C307
1
4.7U_ 0805_ 10V4Z
2
1
C308
2
+3VA LW
1
C309
0.1U_ 0402_ 16V4Z@
2
3 3
PCIE _WA KE#11
MIN I_CL KREQ#11
CLK _PC IE_ MCARD#11
CLK _PC IE_ MCARD11
PCIE _RST1 #11
CLK _DE BUG_PO RT13
PCIE _RXN111
PCIE _RXP111
PCIE_ TXN111
PCIE_T XP111
4 4
A
B
Mini Card STANDOFF
H21
H20
HOL EA
HOL EA
1
1
EC029000100 MINICARD_STANDOFF_8
C
1 2
R194 0_0 402_5%
CLK _PC IE_ MCARD#
CLK _PC IE_ MCARD
PCIE _RST 1#
PCI E_RXP1
PCIE_ TXN1
PCIE_T XP1
PCIE _W AKE#
MIN I_CL KREQ #_MC
1 2
R200 0_ 0402 _5% DEB UG@
R201 0_0 402_5%
1 2
1 2
R202 0_0 402_5%
11
13
15
17
19
PCIE _C _RXN1PCI E_ RXN1
PCIE _C_ RXP1
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
FOX_A S0B22 6-S40 N-7F~D
SP01000P700 S H-CONN ACES 88914-5204 52P P0.8
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
D
+1. 5VS_M INI
+3V S_MINI
JP12
1
2
1
2
3
4
3
4
5
6
5
6
7
8
7
8
9
10
9
10
12
11
12
14
13
14
16
15
16
18
17
18
20
19
20
22
21
22
24
23
24
26
25
26
28
27
28
30
29
30
32
31
32
34
33
34
36
35
36
38
37
38
40
39
40
42
41
42
44
43
44
46
45
46
48
47
48
50
49
50
52
51
52
54
GND1
GND2
FBMA- L11-2 01209- 102LMA10T
1 2
L24 FBMA- L11-2 01209- 102LMA10T
R195 0_04 02_5% DE BUG @
1 2
R196 0_04 02_5% DE BUG @
1 2
R197 0_04 02_5% DE BUG @
1 2
R198 0_04 02_5% DE BUG @
1 2
R199 0_04 02_5% DE BUG @
1 2
WL_ OFF #
PCIE _RST 1#
WL_ LED#
2007/01/07 2008/01/12
Compal Secret Data
E
L23
1 2
WL_ OFF# 27
+3VA LW
SMBCL K0 15
SMBDA TA0 15
Deciphered Date
+3VS
WL_ LED# 25
+1.5 VS
F
LPC _AD3
LPC _AD2
LPC _AD1
LPC _AD0
LPC _FRAM E# 13 ,14,2 6,27
LPC _AD [0..3 ] 13,2 6,27
Compal Electronics, Inc.
Title
HDD/ODD/Mini Card CONN.
Size Do cume nt N umber Re v
Dat e: Shee t o f
LA -37 33 P
G
0.1
20 36Monda y, Mar ch 05 , 2007
H
A
0206_delet PU , PU in page 12
MII _MDC12
MII _MDIO12
MII_T XD012
MII_T XD112
MII_T XD212
MII_T XD312
MII_T XEN12
MII_T XCLK12
4 4
MII _RXDV12
MII _RXD012
MII _RXD112
MII _RXD212
MII _RXD312
MII _RXCLK12
MII _COL12
MII _CR S12
MII _RXER12
+3V ALW
1 2
2
C41 3
15P _0402_ 50V8J
1
3 3
MII _MDC
MII _MDI O
MII_T XD0
MII_T XD1
MII_T XD2
MII_T XD3
MII_T XEN
MII_T XCLK
MI I_RXDV
MI I_RXD0
MI I_RXD1
MI I_RXD2
MI I_RXD3
R20 6
1 2
MII _COL
MII _CR S
MI I_RXER
0205_same name between R206
X3
25M HZ_20P
12
R2 18 5 .1K _0402_1 %
C41 4
2
15P _0402_ 50V8J
PH YA D0
1
PH YA D1
ACT IVI TY#/ PHY AD2
LIN K_10 0#/ PHYA D3
PH YA D4
022 7_nV idi a r ecom mend
+3V ALW
R23 05.1 K_0402_ 1% @
12
R22 35.1 K_0402_ 1%
1 2
R22 55.1 K_0402_ 1%
1 2
R22 65.1 K_0402_ 1%
1 2
R22 75.1 K_0402_ 1%
1 2
R22 85.1 K_0402_ 1%
2 2
1 1
1 2
A
12
12
R23 15.1 K_0402_ 1% @
R22 95.1 K_0402_ 1% @
C32 1
220 P_1808_ 3KV@
U3 4
25
MDC
26
MDI/O
6
TXD0
5
TXD1
4
TXD2
3
TXD3
2
TXEN
7
TXC
22
RXDV
21
RXD0
20
RXD1
19
RXD2
18
RXD3
MII _RXC LK_R
16
RXC
22_ 0402_5%
1
COL
23
CRS
24
RXER/FXEN
44
MII/SNIB
46
X1
47
X2
9
PHYAD0/LED0
10
PHYAD1/LED1
12
PHYAD2/LED2
13
PHYAD3/LED3
15
PHYAD4/LED4
RTL 8201 CL_LQF P48
MII _COL
PH YA D0
PH YA D1
ACT IVI TY#/ PHY AD2
LIN K_10 0#/ PHYA D3
PH YA D4
MII _CR S
MI I_RXER
SP020008Y00 S W-CONN ACES 88266-02001 2P P1.25
ACES_88266-02001_2P
RI NG
TIP
2
2
C32 2
@
1
1
220 P_1808_ 3KV
JP1 4
1
1
2
2
3
G1
4
G2
ACE S_882 66-02001
CO NN @
MII I/F
CLK
PHY/LED
RJ11
DVDD33
DVDD33
AVDD33
PWFBOUT
PWRGND
PWFBIN
TPRX-
TPRX+
TPTX-
TPTX+
RTSET
ISOLATE
RPTR
SPEED
DUPLEX
Network I/F
LDPS
RESETB
DGND
DGND
DGND
AGND
AGND
B
+3V ALW
14
48
AV DD3 3
36
PWF BOUT
32
PW FB IN
TPRXÂTPRX+
TPTXÂTPTX+
R21 1 2 K_040 2_1%
R21 3 5 .1K_ 0402_1%
R21 4 5 .1K_ 0402_1%
R21 5 5 .1K_ 0402_1%
R21 6 5 .1K_ 0402_1%
R21 7 5 .1K_ 0402_1%
C3 14
0.1 U_04 02_16V7K
0.1 U_04 02_16V7K
12
12
12
12
12
12
8
30
31
33
34
28
43
40
39
38
37
ANE
41
42
27
NC
11
17
45
29
35
2
C31 5
0.1 U_04 02_16V7K
1
1 2
5.1 K_0402 _1%
R22 1
12
R2 200_0 402_5%
2
1
close to magnetic
R20 8
49. 9_0402 _1%
TPRX-
TPRX+
R21 0
49. 9_0402 _1%
TPTX-
TPTX+
R20 7
49. 9_0402 _1%
R20 9
49. 9_0402 _1%
close to chip
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
+3V ALW
L25MBK 2012 221Y ZF 080 5
12
C31 6
close to pin14 close to pin48
+3V ALW
+3V ALW
MII _RESET # 1 2
PWF BOUT
C31 3
0.0 1U_0 402_16V 7K
12
12
C31 2
0.0 1U_0 402_16V 7K
12
12
2
2
C31 7
1
1
MI I_P WRDW N# 12
R32 6 0 _0402 _5%
R32 7 0 _0402 _5%
0.1 U_04 02_16V4 Z
12
12
0.1 U_04 02_16V7K
+3V ALW
12
R32 55.1 K_0402 _1%@
12
R21 25.1 K_0402 _1%
12
12
2
C31 1
1
2
C40 8
1
0.1 U_04 02_16V 4Z
01/ 24
C
Compal Secret Data
Deciphered Date
2007/01/07 2008/01/12
D
PWF BOUT PW FB IN
C3 18
22U _120 6_10V4Z
TPTXÂTPTX+
TPRXÂTPRX+
7
6
3
2
1
MBK 2012 221Y ZF 080 5
2
C3 19
0.1 U_04 02_16V7 K
1
U7
TD-8TXÂTD+
TX+
CT
CT
CT
CT
RD-
RX-
RD+
RX+
NS0 013_16 P
ACT IVI TY#/ PHY AD2
@
C40 9
1 2
680 P_0402 _50V7K
L26
1 2
012 5 EM I r eques t
LIN K_10 0#/ PHYA D3
@
C41 0
1 2
680 P_0402 _50V7K
012 5 EM I r eques t
D
E
2
C3 20
0.1 U_04 02_16V7 K
1
MDO 0+
9
MD O0-
10
11
14
MDO 1+
15
MD O1-
16
R21 9
300 _0603_5 %
1 2
R22 4
300 _0603_5 %
1 2
+3V ALW
Title
Size Do cume nt Numbe r R ev
B
Dat e: Shee t o f
R20 4
75_ 0402_5%
12
12
R20 5
75_ 0402_5%
+3V ALW
11
12
8
7
MD O1-
6
5
4
MDO 1+
3
MD O0-
2
MDO 0+
1
10
9
TIP
13
RI NG
14
Compal Electronics, Inc.
MII LAN RTL8201CL
LA3733P
JP1 3
C31 0
RJ 45_ GND
100 0P_120 6_2KV7K
Yellow LED+
Yellow LED-
RX2-
RX2+
RX1-
TX2-
TX2+
RX1+
TX1-
TX1+
Green LED-
Green LED+
RJ11_1
RJ11_2
SGND1
SGND2
RJ45 / LED
RJ11
JM3 4F2-M5 125-7FCON N@
JM34F2*-N5125-7F
JM34F2A-M5125-7F
21 36Mon day, Ma rch 05, 2007
E
12
15
16
0.1
A
B
C
D
E
AUDIO CODEC
8
45
DVDD
DVDDM
DVSS
VSSIO_46
6
C342
@
0.1U_0 402_16V4Z
1 2
C343
@
0.1U_0 402_16V4Z
1 2
C344
@
0.1U_0 402_16V4Z
1 2
C345
@
0_0402_5%
1 2
C346
@
0.1U_0 402_16V4Z
1 2
R248
0_1206_5%
1 2
R249
@
0_1206_5%
1 2
For L ayout:
Place decoupling caps near the
power pins of SmartAMC
device.
1
2
C331
0.1U_0 402_16V4Z@
20
37
31
AVDDHP
AVDD_20
AVDD_31
MIC_BIAS_L
MIC_BIAS_R
MIC_L
MIC_R
LINEOUT_L
LINEOUT_R
PORT-A_BIAS_L
PORT-A_BIAS_R
PORT-A_L
PORT-A_R
PORT-B_BIAS_L
PORT-B_BIAS_R
PORT-B_L
PORT-B_R
CD_L
CD_GND
CD_R
SENSE
VREF_HI
VREF_LO
VC_REFA
AVSS_25
AVSSHP
AVSS_12
AVSS_32
CX20549-12Z_LQFP48_9X9
25
40
12
32
GND AGN D
C332
0.1U_0 402_16V4Z
29
30
21
22
35
36
33
34
38
39
14
15
23
24
17
18
19
13
26
27
28
+3VAMP_CODEC
1
2
1U_0603_10V 4Z
C333
MIC_I NL
MIC _INR
LINE_OU TL
LINE _OUTR
HP_OUTL
HP_OUTR
MIC_EXTL
MIC_EXTR
SENSE
For Vista
VRE F_HI
VREF_LO
VC_RE FA
GNDA 24
R233 0_0805_5%
1 2
1
2
C335 10U_0 805_10V4Z
C336 10U_0 805_10V4Z
+CODEC _REFF_EXTL
+CODEC _REFF_EXTR
C337 10U_0 805_10V4Z
C339 10U_0 805_10V4Z
1 2
R244 20K_0402 _1%
1 2
R245 5.1K_040 2_1%
1 2
R246 5.1K_040 2_1%
1 2
1
C340 1U _0603_10V4Z
C341
1U_06 03_10V4Z
2
+VDDA _CODEC
R236 2.2K_0402_5%
1 2
1 2
LINE_OU TL 24
LINE_ OUTR 24
HP_OUTL 24
HP_OUTR 24
1 2
1 2
1 2
MIC_DET# 24
HP_DET# 24
+CODEC _REFF_EXTR
R239
2.2K_0402_5%
+3VAMP_CODEC
0201 _dele t 1 mic
MIC_I N_R 24
+CODEC _REFF_EXTL
12
12
R240
2.2K_0402_5%
MIC_EXT_L 24
MIC_EXT_R 24SB_SPKR15
1/22
HP_D ET#
0(LOW)
0(LOW)
W=40 Mil
DIB_P
DIB_ N
NC
NC N C
In orde r for t he mod em w ake on ring f eature to func tion,
the C ODEC m ust be powe red by a rail that i s not
remove d when the s ystem is in stand by.
1
2
C328
0.1U_0 402_16V4Z@
HDA_R ST_AUDIO#
R238 0_0402_5%
1 2
R241 0_0402_5%
1 2
C338
1U_0603_10V 4Z
1 2
12
+3VDD _CODEC
1
1
1
2
2
2
C330
C329
0.1U_0 402_16V4Z@
0.1U_0 402_16V4Z
3
U10
VDDIO
10
RESET#
5
BIT_CLK
9
SYNC
7
SDI
4
SDO
DIBP _C
44
DIBP
DIB N_C
43
DIBN
11
PCBEEP
48
EAPD
RCO SC
SPDIF
47
EAPD
1
NC_1
2
NC_2
16
NC_16
41
RCOSC
VSSIO_42
46
42
DIGITAL ANALOG
1 1
HDA_B ITCLK_AU DIO
R234
@
10_0402_5%
1 2
1
C334
@
10P_0402_25V8K
2
2 2
3 3
4 4
R232
0_0805_5%
1 2
+3VS
HDA_R ST_AUDIO#14,27
HDA_B ITCLK_AU DIO14
HDA _SYNC _AUDIO14
HDA_S DOUT_AUD IO14
R242
0_0402_5%
SB_SPKR MONO_IN1 MONO_ INR
1 2
HDA_ SDIN014
+3VDD _CODEC
DIB_P23
DIB_ N23
C326
10U_0805_10V 4Z@
@
1 2
1
2
C327
1U_06 03_10V4Z
1 2
R237 33_0402_5%
R243
5.1K_0402_5%
TP13
R247 2 37K_0402_1%
CODEC POWER
+5VS
1 2
C323 0. 1U_0402_16V4Z
+5VS
JP47
1
GND1
3
IAC_SDATA_OUT
5
GND2
7
IAC_SYNC
9
IAC_SDATA_IN
11
IAC_RESET#
MIC_ DET
0(LOW)
NC
0(LOW)
U9
1
VIN
2
GND
SHDN#3BP
APE88 05A-33Y5P_SOT23-5
0.1U_0 402_16V4Z
RES0
RES1
GND3
GND4
IAC_BITCLK
131314141515161617171818191920
LINE OUT
OFF
OFF
ON
ON Enable
+VDDA _CODEC
5
OUT
1
C324
0.1U_0 402_16V4Z
4
2
1
C325
2
2
4
6
3.3V
8
10
12
TYCO_1-1 79396-2~D
20
Connector for MDC Rev1.5
PORT -A
<Ear phone OUT>
ON
ON
OFF
OFF
MIC
ON
OFF
ON
OFF
(3.33V)
250mA
EQ
Disable
Disable
Enable
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2007/01/07 2008/01/12
C
Compal Secret Data
Deciphered Date
Compal Electronics, Inc.
Title
AMOM_codec
Size Docume nt Number Re v
Custo m
LA -37 33P
D
Date: Sheet of
22 36Monda y, Marc h 05, 2007
E
0.1
5
4
3
2
1
MU1
AVdd
AGN D_L SD
AGN D_L SD
D IBN
PWR +
MC3
0.1 uF
DI BP
DVd d
12
16
15
cap_ 040 2_01uf
14
CX20548
TEST
DIBN
PWR
2
AVDD
DIBP
1
DVDD
MC2
0.1 uF
cap_ 040 2_01uf
3
VC_ LSD
AGN D_L SD
R AC1
4
RAC
TAC 1
5
TAC
EIC
11
EIC
R810 a nd C81 0 must be placed near pin 6 (RXI)
and th ere sh ould be no vias on the(RXI)net.
RXI
6
RXI
10
EIO
E IF
9
EIF
TXO
8
TXO
TXF
7
TXF
13
GPIO
VC
EP
17
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
D D
DIB _P22
C C
B B
DIB _N22
MC12
GN D
150p F
MJ4@
2
1
MJ5@
1
2
GN D
DIB N_ HS
DIB P_H S
CAP _04 02_150P F
MC13
150p F
CAP _04 02_150P F
GN D
MT1
2 3
1
MODEM -SMA R
4
MC6
47P _040 2_50V8J
CAP _04 02_47P F
MC5
0.1 uF
cap_ 040 2_01u f
MC4
0.1 uF
cap_ 040 2_01uf
Revision History
Description
0
Initial Release
No cha nges to schematic. PCB updated to -003.
1
Update d footprints and corrected via spacing errors.
A A
Change d MC8 and MC9 pads. No schematic changes.
2
PCB updated to -005.
3
Added MR11 and MR12. PCB updated to -007.
4
Added MR13. PCB updated to -009.
4.01
AVL update only.
5
DateREV
April 26, 2005
August 18, 2005
November 3, 2005
November 18, 2005
January 3, 2006
April 20, 2006
4
RAC 1_R IN G
MR3 6. 81M
MR1 6. 81M
res _080 5_681m
MC11 0.1u F
MR2
237K
cap_ 040 2_01u f
AGN D_L SD
RX1_1
MR13 100 _0402 _5%
MMB D3004S
MMB D3004S
TAC 1_TIP TIP _1
MC1 0.0 47uF
100. 0V
RES _0402 _100
2007/01/07 2008/01/12
5335R13-005
MBR 1
AGN D_L SD
142
@
MBR 2
5335 R13- 005
MQ2
MMBTA42
MR4
110
5%
Compal Secret Data
Deciphered Date
MFB2
3
ML1
Optional
MFB1
MC10 0.01 uF
cap_ 060 3_001u f
BRI DG E_C C
MQ1
MMBTA42
QBAS E
MR8
56
5%
RES _0603 _56@
AGN D_L SD
2
MC8
AGN D_L SD
MR9
280
RES _1206 _280
MQ3
MMBTA42
MR11
3.01
res _0402 _301
MR7
9.1
res _1206_9 1
RIN G_1
2
MRV1
MC9
MC7
470 pF470 pF
Omit
@
Note: MC8 and MC9 can be optionally
popula ted here or behind the RJ-11
connector.
GN D
MR5
MR6
280
280
RES _1206 _280
RES _1206 _280
BRI DG E_ CC2
MQ4
MMBTA42
MR12
3.01
res _0402_3 01
Title
AMOM -CX20548
Size Docu men t Number Re v
Dat e: Sheet of
1
MJ2
@
2
1
MJ1
@
2
1
MJ3
@
MR10
280
RES _1206 _280
Compal Electronics, Inc.
LA -37 33P
1
0.1
23 36Mon day, M arch 0 5, 200 7
A
1 1
C354 0 .47U_060 3_10V7K
1 2
C356 0 .47U_060 3_10V7K
A
1 2
C359 0 .47U_060 3_10V7K
1 2
EC_MUTE#27
HP_OUTR22
HP_OUTL22
C357 0 .47U_060 3_10V7K
LINE_OU TR22
LINE_OU TL22
2 2
3 3
4 4
LINE_C _OUTR
1 2
LINE_C _OUTL
EC_MUTE#
HP_OUT R
HP_OUTL
B
U11
7
RIN+
17
RIN-
9
LIN+
5
LIN-
19
SHUTDOWN
cap. high 5.7mm
C364
+
100U_6.3V_M
1 2
+
100U_6.3V_M
1 2
C365
2N7002_SOT23-3
B
GND5
20
21
1K_0402_5%
10U_080 5_10V4Z
16
15
6
VDD
PVDD1
PVDD2
BYPASS
GND41GND311GND213GND1
12
R263
Q15
13
D
S
C
+5VS+5VAMP
0.1U_04 02_16V4Z
1
C348
C347
2
2
GAIN0
3
GAIN1
ROUT+
ROUT-
LOUT+
LOUT-
TPA6017A2_TSSOP20
SPKR+
18
SPKR-
14
SPKL+
4
SPKL-
8
12
NC
10
2
1
EC_MUTE#
HP_OUT_ R
1 3
D
HP_OUT_L
D
1 3
12
R264
1K_0402_5%
2
G
13
D
Q16
2
G
2N7002_SOT23-3
S
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
R250
0_1206_5%
1 2
1
1
C349
2
2
0.1U_04 02_16V4Z
100K_0402_5%
100K_0402_5%
Ke ep 10 mil wi dth
C360
0.47U_0 603_10V7K
Q11
2N7002_SOT23-3
2
G
Q13
S
2N7002_SOT23-3
Q14
S
2N7002_SOT23-3
G
2
10 dB
+5VS
12
12
R251
12
R254
@
B+
12
R259
330K_0402_5%
13
D
2
G
S
HP_OUTR+
HP_OUTL+
2007/01/07 2008/01/12
C
@
100K_0402_5%
12
R255
100K_0402_5%
B+
12
R260
330K_0402_5%
13
D
Q12
2
G
2N7002_SOT23-3
S
Compal Secret Data
R252
MIC_EXT_L22
MIC_EXT_R22
Deciphered Date
HP_OUTR+
HP_OUTL+
D
SP02000D000 S W-CONN ACES 85204-04001 4P P1.25
SPKL+
SPKLÂSPKR+
SPKR-
1
1
C350
C351
2
2
@
@
47P_0402_50V8J
47P_0402_50V8J
020 1_d elet 1 mic
C358 4 7P_0402_50V8J@
12
MIC_I N_R22
MIC_DET#22
C361 4 7P_0402_50V8J@
12
MIC_EXT_L MICEXT_L
MIC_EXT_R MICEXT_R
R257 0_0 603_5%
12
12
R258 0_0 603_5%
12
C362 4 7P_0402_50V8J@
HP_DET#22
C363 4 7P_0402_50V8J@
12
R261 0_0 603_5%
12
12
R262 0_0 603_5%
12
C366 4 7P_0402_50V8J @
DC230002X00
This is real footprint ,
JP18 & JP19 are temporary footprint
6
5
4
3
020 1 M E c hange s part
2
1
D
R256 0_ 0603_5%
MIC_DET#
HP_DET#
PR
PL
3
Compal Electronics, Inc.
Title
AMP & Audio Jack
Size Docume nt Number Re v
Date: Sheet of
E
SPEAKER
JP15
1
1
2
2
3
3
4
4
E&T_3801-04
1
C352
C353
2
@
@
47P_0402_50V8J
47P_0402_50V8J
SP0200 0D000 S W-CONN ACES 85204-02001 2P P1.25
ACES_85204-02001_2P
12
2
3
D11
@
1
SM05_SOT23
012 5 E MI r equest
cha nge par t no.
HeadPhone Out/Line Out
2
5
4
3
6
1
2
D12
@
1
SM05_SOT23
012 5 E MI r equest
cha nge par t no.
LA -37 33P
CON N@
1
2
MIC INT In-R
MICI N_R
CON N@
SUYIN_0 10030FR0 06G101ZL_6P
JP19
JP17
1
1
2
2
3
G1
4
G2
ACES_8 5204-02001
CON N@
MIC EXT In
CON N@
SUYIN_0 10030FR0 06G101ZL_6P
2
5
4
3
6
1
JP18
24 36Mon day, M arch 05, 2007
E
8
7
8
7
0.1
5
D D
Power ON/OFF
+3VALW
R267
Can NO STUFF
4.7K_0402_5%
D16
1
DAN20 2U_SC70
Q17
DTC124E K_SC59
+3VALW
12
2
3
R271
4.7K_0402_5%
ON/OF FBTN#
C C
Can NO STUFF
EC_ON
EC_ON27,30
1 2
ON/ OFF
51ON#
1
O
1
2
G3I
C367
1000P_0402_50V7K
2
ON/ OFF 27
51ON# 31
12
D17
RLZ20A_LL34
4
NUM_LED#26,27
WL_BTN#27
ON/OFFB TN_LED#26,27
LID_SW #27
3
M/BtoS/B
+3VALW
+3VS
JP20
1
1
2
ON/OF FBTN#
WL_BTN#
ON/OFFB TN_LED#
WL_LED#
LID_SW #
SP01000H400 S H-CONN ACES 85201-1005N 10P P1.0
ACES_85201-1005N_10P
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
GND
12
GND
ACES_ 85201-1005N
CONN @
2
POWER LED(Left 1)
ON/OFFB TN_LED#
HSMB- C172 BLUE_0805
Battery Charge LED(Left 2)
BAT_LED#27
SATA_LED#14
HSMB- C172 BLUE_0805
HDD LED(Left 3)
HSMB- C172 BLUE_0805
BLUE
BLUE
BLUE
1
+3VALW
R265
D13
1 2
21
200_0402_5%
+3VALW
R266
D14
21
12
200_0402_5%
+3VS
R268
D15
1 2
21
200_0402_5%
Wireless ON/OFF LED(Left 4)
+5VS
M/B to SB(Caps Lock LED)
+3VALW
JP21
1
1
CAPS_LE D#26,27
SP02000D000 S W-CONN ACES 85204-02001 2P P1.25
ACES_85204-02001_2P
2
2
3
G1
4
G2
ACES_85204-02001
CONN @
LTST-C19 5TBKFKT_BLU/ORG
On ( WL_ON #=L)-> Blue
Off (WL_O N#=H)-> Amber
WL_LED#20
WL_LED#
12
12
R269
200_0402_5%
AMBER BLUE
R270
200_0402_5%
1
2
D18
Orange
Blue
3
4
13
D
Q18
2
2N7002_SOT23-3
G
S
13
D
Q19
2
2N7002_SOT23-3
G
S
10K_0402_5%
WL_ LED#_LIGHT
+5VS
12
R272
B B
+5VS
TouchPAD ON/OFF LED
12
12
R273
R274
200_0402_5%
+5VS
12
R277
10K_0402_5%
2N7002_SOT23-3
TP_LED #_LIGHT
A A
5
200_0402_5%
1
2
AMBERBLUE
Blue
D20
Orange
3
4
2
G
LTST-C19 5TBKFKT_BLU/ORG
13
D
On ( TP_LE D#=L)-> Blu e
S
Off (TP_L ED#=H)-> Amber
13
D
TP_LED#
Q23
2
2N7002_SOT23-3
G
S
Q22
D21, D25, D23 Footp rint can not match part number.
0206_delet 14.1" TP
0206_delet 14.1" led
TP_LED# 27
4
3
4
SN100000F00 S TACT SW SMT1-05-A SPST HCH H1.5 4P
SW_SMT1-05-A_4P
TP ON/OFF
SW2
SMT1-05-A_4P
1
2
5
6
1
1
2
2
TP_DATA
TP_CLK
C370
@
100P_0603_50V8J
EMI reques t
2
TP_CLK 27
TP_DATA 27
+5V
R275
10K_0402_5%
1 2
TP_BTN#
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
TP_BTN# 27
ACES_ 85201-0405N
SP01000H300 S H-CONN ACES 85201-0405N 4P P1.0
ACES_85201-0405N_4P
2007/01/07 2008/01/12
3
+5V
JP22
1
1
2
2
3
3
4
4
5
G1
6
G2
CONN @
100P_0603_50V8J
Compal Secret Data
Deciphered Date
1
C368
@
0.1U_0 402_16V4Z
2
C369
@
T/P Board
2
3
D19
PSOT24C_SOT23-3
@
1
EMI reques t
SYSO N27, 28,32
Title
LED/SW
Size Docum ent Number R ev
Date: Sheet of
+5VALW +5V
SI2301 BDS-T1-E3_SOT23-3
S
12
R276
10K_0402_5%
13
D
SYS ON
2
G
S
Compal Electronics, Inc.
LA -37 33P
1
Q20
D
13
G
2
Q21
2N7002_SOT23-3
25 36Monda y, Marc h 05, 2007
0.1
USB Port
+5VALW
U12
1
2
3
SYSO N# USB_OC#0
4
GND
IN
IN
EN#
G528P1 UF_SO8
8
OUT
7
OUT
6
OUT
5
FLG
+USB_V CCA
USB20_N014
USB20_P014
USB_OC#0 14
0125 EMI request
USB20_N0
R328 0_0402_5%
1 2
L29
4
1
WCM 2012F2S-670T04_0805@
1 2
3
3
2
2
4
1
R329 0_0402_5%
SUYIN _020173MR004G533ZR_4P
220U_6.3V_M
C371
USB20 _N0_R
USB20_P 0_RUSB20_P0
D22
1
GND
2
I/O
PRTR5V0U2X_SOT143@
1
+
C372
2
0.1U_0 402_16V4Z
4
VCC
3
I/O
+USB_V CCA
1
1
C373
1000P_0402_50V7K
2
2
0302 _foot print erro r ; 1234 shift 4321
JP24
4
4
3
3
2
2
1
1
5
GND
6
GND
7
GND
8
GND
SUYIN_0 20173M R004S558ZL
CON N@
DC233000U00 CONN SUYIN 020173MR004S558ZL 4P USB
SUYIN_020173MR004S558ZL_4P SP02000DX00 S W-CONN ACES 87213-1000G 10P P1.0
+USB_V CCA
USB20 _N0_RUSB20_P0_R
0125 EMI request
chan ge EM I diode
USB20_N414
USB20_P414
USB20_N714
USB20_P714
USB_OC#414
SYSON #28,32
SYSO N#
+5VALW
ACES_87213-1000G_10P
JP23
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
GND1
12
GND2
ACES_87 213-1000G
CON N@
C375
0.1U_0 402_16V4Z
SMB_EC_CK127,35
SMB_EC_DA127,35
12
R279
47K_0402_5%
1
2
0.1U_0 402_16V4Z
2
C377
12
R280
47K_0402_5%
Q25
MMBT3904_SOT23
3 1
1
2
+3VS+5VALW+1.2V_HT
Q24
BSS138_SOT23
2
G
1
C376
0.1U_0 402_16V4Z
2
U14
8
A0
VCC
7
A1
WP
6
SCL
A2
5
SDA
GND
AT24C1 6AN-10SI-2.7_SO8
12
13
D
S
1
2
3
4
R278
47K_0402_5%
HT_VLD
+3VALW+3VALW
12
12
R286
100K_0402_5%
R291
100K_0402_5%
HT_VLD 11,15
SPI ROM
+3VALW
20mils
1
C374
0.1U_0 402_16V4Z
FSEL#27
SPI_CLK27
2
1 2
R281 0_0402_5%
1 2
R282 0_0402_5%
FWR# FR D#
1 2
R283 0_0402_5%
SPI_CLK
FSEL#
FWR#
HOLD#
FRD #
U13
8
VCC
WP#
3
W
HOLD#
7
HOLD
SPI_FSEL#
1
S
SPI_CL K_R
6
C
5
D
SP07000F500 S SOCKET WIESON G6179-100000 8P SPIFLASH
WIESO_G6179-100000_8P
&U1
45level
45@
SST25LF080B_SO8-200mil
R285 0_0402_5%
1 2
R287 0_0402_5%
1 2
R288 0_0402_5%
1 2
R289 0_0402_5%
1 2
R290 0_0402_5%
1 2
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4
VSS
SPI_SOSPI_FW R#
1 2
2
Q
WIES ON G617 9 8P SPICON N@
R284 0_0402_5%
SPI_CLK_ JP52
SPI_CS#_ JP52
SPI_SI_ JP52
SPI_HO LD#_0
SPI_SO_JP52
2007/01/07 2008/01/12
Compal Secret Data
FRD# 27FWR#27
Deciphered Date
LPC Debug Port
0201_change clk name
CLK_L PC_DEBUG13
LPC_FRAME#13,14,20,27
LPC_RST#13,27
LPC_AD013 ,20,27
LPC_AD113 ,20,27
LPC_AD213 ,20,27
LPC_AD313 ,20,27
ON/OFFB TN_LED#25,27
CAPS_LED#25,27
NUM_LED#25,27
VCC1_ PWRGD27
Conn ect p in3 & 23
toge ther and pin 24
to G ND in 6 /29.
Title
Size Docume nt Number Re v
Date: Sheet of
Chan ge fr om +3 VL to +3VS . 6/9
Remo ved + 3VS. 6/13
B+
JP25
1
Ground
2
LPC_PCI_CLK
3
Ground
4
LPC_FRAME#
5
+V3S
6
LPC_RESET#
7
+V3S
8
LPC_AD0
9
LPC_AD1
10
LPC_AD2
11
LPC_AD3
12
VCC_3VA
13
PWR_LED#
14
NUM_LED#
SPI_CLK_ JP52
SPI_CS#_ JP52
SPI_SI_ JP52
SPI_SO_JP52
SPI_HO LD#_0
CAPS_LED#
15
NUM_LED#
16
VCC1_PWRGD
17
SPI_CLK
18
SPI_CS#
19
SPI_SI
20
SPI_SO
21
SPI_HOLD#
22
Reserved
23
Reserved
24
Reserved
ACES_87216-2404_2 4P
CON N@
Compal Electronics, Inc.
USB/BIOS ROM
LA -373 3P
26 36Monda y, Marc h 05, 2007
0.1
+3VALW_EC
1
2
0.1U_0 402_16V4Z
R303
4.7K_0402_5%
4.7K_0402_5%
0.1U_0 402_16V4Z
1
C378
2
+3VS +5VALW
12
12
R304
C379
1000P_0402_50V7K
12
12
R301
4.7K_0402_5%
4.7K_0402_5%
SMB_EC_DA1
SMB_EC_CK1
SMB_EC_DA2
SMB_EC_CK2
1
2
R302
0.1U_0 402_16V4Z
C380
1
2
EC DEBUG port
JP27
@
1
1
2
2
3
3
4
4
ACES_85205-0400
0201 _dele t deb ug po rt_f uncti on same to JP25
+5VALW
URX
UTX
1000P_0402_50V7K
1
C382
C381
2
C385
@
1 2
15P_0402_50V8J
CLK_P CI_LPC13
+3VALW
12
C386 0.1U_0402_16V 4Z
R295
@
1 2
33_0402_5%
47K_0402_5%
R296
12
12
J1
JOPEN
1 2
10P_0402_50V8J
C387
3
NC
2
NC
32.76 8KHZ_12 .5P_1TJS125DJ2A073
Y2
1 2
10P_0402_50V8J
C388
+3VALW_EC
12
Ra
1
C383
2
AD_BIDVAD_BID
0.250V
0.503V
0.819V
1.185V
1.650V
2.200V
3.300V
For EMI
KSO15
KSO10
KSO11
KSO14
100P_1206_8P4C_5 0V8@
KSO13
KSO12
KSO3
KSO6
100P_1206_8P4C_5 0V8@
KSO8
KSO7
KSO4
KSO2
100P_1206_8P4C_5 0V8@
KSI0
KSO1
KSO5
KSI3
100P_1206_8P4C_5 0V8@
KSI2
KSO0
KSI5
KSI4
100P_1206_8P4C_5 0V8@
KSI7
KSI1
R292
100K_0402_5%
12
R29910K_0402_5%
R30010K_0402_5%
CP1
2
3
4 5
CP2
2
3
4 5
CP3
2
3
4 5
CP4
2
3
4 5
CP5
2
3
4 5
CP6
2
3
4 5
100P_1206_8P4C_5 0V8@
27 36Monda y, Marc h 05, 2007
Rb
R294
0_0402_5%
0.289V
0.538V
0.875V
1.264V
1.759V
2.341V
3.300V
+5V
12
12
max
81
7
6
81
7
6
81
7
6
81
7
6
81
7
6
81
7
6
0.1
+3VALW
R293
12
0_0805_5%
U15
GATEA20
GATEA2015
KB_RST#15
SIRQ13
LPC_FRAME#13,14,20,26
LPC_AD313 ,20,26
LPC_AD213 ,20,26
LPC_AD113 ,20,26
LPC_AD013 ,20,26
LPC_RST#13,26
EC_SC I#15
SMB_EC_CK126,35
SMB_EC_DA126,35
SMB_EC_CK24
SMB_EC_DA24
SLP_S3#15
SLP_S5#15
EC_SMI#15
LID_SW #25
SUSP#28
PWR BTN_OUT#15
0208_delete PGD_IN
TP_BTN#25
ON/ OFF25
NUM_LED#25,26
4
OUT
1
IN
KB_RST#
SIRQ
LPC_LFRAME #
LPC_LAD3
LPC_LAD2
LPC_LAD1
LPC_LAD0
CLK_P CI_EC
LPC_RST#
ECRST#
EC_SC I#
KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7
KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15
SMB_EC_CK1
SMB_EC_DA1
SMB_EC_CK2
SMB_EC_DA2
SLP_S3#
SLP_S5#
EC_SMI#
LID_SW #
SUSP#
PWR BTN_OUT#
TP_BTN#
UTX
URX
ON/ OFF
NUM_LED#
CR Y2
12
20M_0402_5%@
R306
CR Y1
1
GA20/GPIO00
2
KBRST#/GPIO01
3
SERIRQ#
4
LFRAME#
5
LAD3
7
LAD2
8
LAD1
10
LPC & MISC
LAD0
12
PCICLK
13
PCIRST#/GPIO05
37
ECRST#
20
SCI#/GPIO0E
38
CLKRUN#/GPIO1D
55
KSI0/GPIO30
56
KSI1/GPIO31
57
KSI2/GPIO32
58
KSI3/GPIO33
59
KSI4/GPIO34
60
KSI5/GPIO35
61
KSI6/GPIO36
62
KSI7/GPIO37
39
KSO0/GPIO20
40
KSO1/GPIO21
41
KSO2/GPIO22
42
KSO3/GPIO23
43
KSO4/GPIO24
44
KSO5/GPIO25
45
KSO6/GPIO26
46
KSO7/GPIO27
47
KSO8/GPIO28
48
KSO9/GPIO29
49
KSO10/GPIO2A
50
KSO11/GPIO2B
51
KSO12/GPIO2C
52
KSO13/GPIO2D
53
KSO14/GPIO2E
54
KSO15/GPIO2F
81
KSO16/GPIO48
82
KSO17/GPIO49
77
SCL1/GPIO44
78
SDA1/GPIO45
79
SCL2/GPIO46
80
SDA2/GPIO47
6
PM_SLP_S3#/GPIO04
14
PM_SLP_S5#/GPIO07
15
EC_SMI#/GPIO08
16
LID_SW#/GPIO0A
17
SUSP#/GPIO0B
18
PBTN_OUT#/GPIO0C
19
EC_PME#/GPIO0D
25
EC_THERM#/GPIO11
28
FAN_SPEED1/FANFB1/GPIO14
29
FANFB2/GPIO15
30
EC_TX/GPIO16
31
EC_RX/GPIO17
32
ON_OFF/GPIO18
34
PWR_LED#/GPIO19
36
NUMLED#/GPIO1A
122
XCLK1
123
XCLK0
+3VALW_EC
12
+EC_AV CC
Int. K/B
Matrix
L27
0_0603_5%
+EC_A VCC
+3VALW_EC
9
22
33
67
96
111
125
VCC
VCC
VCC
VCC
VCC
VCC
AVCC
INVT_PWM/PWM1/GPIO0F
BEEP#/PWM2/GPIO10
FANPWM1/GPIO12
ACOFF/FANPWM2/GPIO13
PWM Ou tput
BATT_TEMP/AD0/GPIO38
BATT_OVP/AD1/GPIO39
ADP_I/AD2/GPIO3A
AD Inpu t
DA Ou tput
PS2 I nterface
SPI De vice In terface
SPI F lash ROM
GPIO
SM B us
GPIO
GND
GND
GND
11
24
35
94
1 2
C389
0.1U_0 402_16V4Z
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
SELIO2#/AD5/GPIO43
DAC_BRIG/DA0/GPIO3C
EN_DFAN1/DA1/GPIO3D
TP_CLK/PSCLK3/GPIO4E
TP_DATA/PSDAT3/GPIO4F
CIR_RLC_TX/GPIO41
FSTCHG/SELIO#/GPIO50
BATT_CHGI_LED#/GPIO52
CAPS_LED#/GPIO53
BATT_LOW_LED#/GPIO54
SUSP_LED#/GPIO55
VR_ON/XCLK32K/GPIO57
EC_RSMRST#/GPXO03
EC_LID_OUT#/GPXO04
ICH_PWROK/GPXO06
GPO
WL_OFF#/GPXO09
PM_SLP_S4#/GPXID1
GPI
AGND
GND
GND
KB926QFB0_LQFP128_14X1 4
69
113
ECA GND
AD3/GPIO3B
AD4/GPIO42
IREF/DA2/GPIO3E
DA3/GPIO3F
PSCLK1/GPIO4A
PSDAT1/GPIO4B
PSCLK2/GPIO4C
PSDAT2/GPIO4D
SDICS#/GPXOA00
SDICLK/GPXOA01
SDIDO/GPXOA02
SDIDI/GPXID0
SPIDI/RD#
SPIDO/WR#
SPICLK/GPIO58
CIR_RX/GPIO40
SYSON/GPIO56
AC_IN/GPIO59
EC_ON/GPXO05
EC_SWI#/GPXO06
BKOFF#/GPXO08
ENBKL/GPXID2
L28
1 2
INV_PWM
21
FAN_PWM
23
26
ACO FF
27
63
64
65
66
75
76
DAC_ BRIG
68
70
IREF
71
72
EC_MUTE#
83
84
85
TP_LED#
86
TP_CLK
87
TP_DATA
88
97
R298 10K_0402_5%
98
99
WL_BTN#
109
FRD #
119
FWR#
120
SPI_CLK
126
FSEL#
128
SPICS#
73
VCC1_ PWRGD
74
FSTCH G
89
90
CAPS_LED#
91
BAT_LED#
92
ON/OFFB TN_LED#
93
SYS ON
95
VR_ON
121
ACIN
127
EC_RSMRS T#
100
EC_LID _OUT#
101
EC_ON
102
103
MCP_PW RGD
104
BKOFF#
105
WL_ OFF# KSI5
106
107
GPXO10
108
GPXO11
110
112
114
GPXID3
EC_THERM#
115
GPXID4
116
GPXID5
117
GPXID6
118
GPXID7
124
V18R
0_0603_5%
2007/01/07 2008/01/12
Compal Secret Data
BATT_TEMP
BATT_OVP
ADP _IN
M/B_ID
R297 0_0402_5%@
1 2
12
R305 10K_0402 _5%
BKOFF# 18
WL_ OFF# 20
EC_THERM# 6,15
Deciphered Date
INV_PWM 12,18
FAN_PWM 4
ACOF F 30
BATT_TEMP 35
BATT_OVP 30
ADP_I 30
PM_DPRS LPVR 34
DAC_ BRIG 18
IREF 30
EC_MUTE# 24
HDA_R ST_AUDIO# 14,22
TP_LED# 25
TP_CLK 25
TP_DATA 25
WL_BTN# 25
FRD # 26
FWR# 26
SPI_CLK 26
FSEL# 26
VCC1_ PWRGD 26
FSTCHG 30
CAPS_LE D# 25,26
BAT_LED# 25
ON/OFFB TN_LED# 25,26
SYSO N 25,28,32
VR_ON 15,34
ACIN 15,30
EC_RSMRS T# 15
EC_LID _OUT# 15
EC_ON 25,30
MCP_PW RGD 15
ECA GND
1 2
C384 0.01U_0402_16V7K
0207_
VGATE
VGATE 15,34
sele ct SP I ROM or LPC ROM
NO OUTPUT, CONTROL BY MCP67
12
M/B_ID
0.1U_0 402_16V4Z
VCC 3. 3V+/-5%
Ra 100K+/- 5%
Boar d ID Rb V
0
0 0V 0V 0V
1
8.2K +/-5%
2
18K+ /-5%
3
33K+ /-5%
4
56K+ /-5%
5
100K +/-5%
6
200K +/-5%
7
NC
JP26
KSI1
1
1
KSI7
2
2
KSI6
3
3
KSO9
4
4
KSI4
5
5
6
6
KSO0
7
7
KSI2
8
8
KSI3
9
9
KSO5
10
10
KSO1
11
11
KSI0
12
12
KSO2
13
13
KSO4
14
14
KSO7
15
15
KSO8
16
16
KSO6
17
17
KSO3
18
18
KSO12
19
19
KSO13
20
20
KSO14
21
21
KSO11
22
22
KSO10
23
23
KSO15
24
24
25
GND1
26
GND2
ACES_85201-24051
CONN @
SP01000FF00 85201-24051 24P P1.0
ACES_85201-24051_24P
Compal Electronics, Inc.
Title
EC KB926/KB conn
Size Docume nt Number Re v
Date: Sheet of
AD_BID
0.216V
0.436V
0.712V
1.036V
1.453V
1.935V
2.500V
LA -373 3P
min V typ
TP_CLK
TP_DATA
A
B
C
D
E
+3VALW to +3VS Transfer
B+
12
R309
330K_0402_5%
1 1
13
D
SUSP
2
G
S
1
C392
2
10U_0805_10V 4Z
Q29
2N7002_SOT23-3
RUN ON
8
7
6
5
AO4422_SO8
U16
S
D
S
D
S
D
G
D
12
R311
470_0402_5%
1
C400
0.01U_0402_1 6V7K
2
+3VS+3VALW
1
2
3
4
0.1U_0 402_16V4Z
10U_0 805_10V4Z
1
1
C393
2
2
C394
+5VALW to +5VS Transfer
+5VS+5VALW
U18
1
8
S
D
2
7
S
D
3
6
1
C401
2
2 2
10U_0 805_10V4Z
3 3
D
5
D
AO4422_SO8
S
G
RUN ON
4
0.1U_0 402_16V4Z
1
1
C403
C402
10U_0 805_10V4Z
2
2
+1.8V to +1.8VS Transfer
1 3
1
2
1 2
Q26
D
S
G
2
C399
0.1U_0 603_25V7K
1 2
C404
4.7U_0 805_10V4Z
R315
60.4K_0402_1%
+1.8VS+1.8V
1
C396
1U_0603_10V 4Z
2
+1.2VALW
8
D
7
D
6
D
5
D
1
C406
4.7U_0 805_10V4Z
2
SI2306 DS-T1 1N_SOT23
1
C395
1U_06 03_10V4Z
2
R312
RUN ON
1 2
60.4K_0402_1%
+1.2VALW TO +1.2VS
U19
1
S
2
S
3
S
4
G
SI4856 ADY-T1-E3_SO8
C407
0.1U_0603_25 V7K
1 2
1
C405
1U_0805_25V 4Z
2
RUN ON
+1.2VS
Discharge circuit
R319
470_0402_5%
Q35
2N7002_SOT23-3
+1.8V
12
13
D
2
G
S
+5VS +3VS
12
R318
470_0402_5%
13
D
SUSP SUSP SYSON# SUSP SUSP SYSON#
2
G
S
Q34
4 4
2N7002_SOT23-3
12
13
D
2
G
S
R320
470_0402_5%
Q36
2N7002_SOT23-3
+1.8VS
12
13
D
2
G
S
R321
470_0402_5%
VLDT_EN#
Q37
2N7002_SOT23-3
2
G
+1.2V_HT
1 2
13
D
S
R322
470_0402_5%
Q38
2N7002_SOT23
+1.2VS +0.9V
12
R323
470_0402_5%
13
D
2
G
S
Q39
2N7002_SOT23-3
2
G
12
R324
470_0402_5%
13
D
S
Q40
2N7002_SOT23-3
+1.2VALW TO +1.2V_HT
1
+1.2VALW
H3
HOLEA
H5
HOLEA
H17
HOLEA
1
U17
8
D
7
D
6
D
5
D
SI4800 BDY_SO8
1
C397
10U_0 805_10V4Z
2
1
1
1
FM1
1
H4
HOLEA
H6
HOLEA
H18
HOLEA
FM2
1
1
1
C390
1U_08 05_25V4Z
2
1
S
2
S
3
S
1.2VHT_GATE
4
G
C398
0.1U_0603_25V 7K
1 2
H7
H8
HOLEA
HOLEA
1
H19
HOLEA
1
FM3
FM4
1
1
1
SYSO N#
SYS ON
SUSP
SUSP#
VLDT_EN#
VLDT_EN
H29
HOLEA
+5VALW
12
R308
100K_0402_5%
13
D
Q27
2
2N7002_SOT23-3
G
S
+5VALW
12
R314
100K_0402_5%
13
D
Q30
2
2N7002_SOT23-3
G
S
+5VALW
12
R316
100K_0402_5%
13
D
Q31
2
2N7002_SOT23-3
G
S
H30
HOLEA
1
1
+1.2V_HT
1
C391
10U_0 805_10V4Z
2
R310
100K_0402_5%
12
R313
1 2
13
D
S
VLDT_EN#
2
G
Q28
2N7002_SOT23
1M_0402_1%@
01/24
H12
H9
HOLEA
1
FM5
H11
H10
HOLEA
HOLEA
1
1
1
FM7
FM6
1
1
H13
HOLEA
HOLEA
1
1
FM9
FM8
1
1
1
SYSON #26,32
SYSO N25, 27,32
B+
SUSP32,33
SUSP#27
VLDT_EN15
H15
H14
HOLEA
1
H26
HOLEA
1
FM11
FM10
1
H16
HOLEA
HOLEA
1
1
H28
H27
HOLEA
HOLEA
1
1
FM12
1
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2007/01/07 2008/01/12
C
Compal Secret Data
Deciphered Date
Compal Electronics, Inc.
Title
Size Docume nt Number Re v
D
Date: Sheet of
DC/DC Interface
LA -373 3P
E
28 36Monda y, Marc h 05, 2007
0.1
A
1 1
B
C
D
VIN
PL1
PC1
12
100P_040 2_50V8J
HCB4532 KF-800T90_1812
1 2
12
PC2
1000P_0402_50V7K
12
12
PC4
PC3
1000P_0402_50V7K
100P_0402_50V8J
PCN1
2 2
ACES_8 8334-057N
ADP IN
1
1
2
2
3
3
4
4
5
5
PR1
1 2
1.5K_1206_5%
3 3
4 4
A
VIN
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
B
2007/01/07 2008/01/12
Compal Secret Data
Deciphered Date
C
Title
Size Docum ent Numbe r Re v
Cus tom
Date: Sheet o f
DC CONN
LA-37 33P
D
29 36Mon day, M arch 05, 2007
A
3
2
16
4
PQ8
RHU 002 N06_S OT323- 3
VIN
12
PR2 2
10K _0402_1 %
3.2V
12
RLZ 4.3 B_LL34
7
12
PC6
PR3 8
1 2
1K_ 0402_5%
12
PR2 9
10K _0402_5 %
VIN
0
P2
0.1 U_0 603_16V 7K
1 2
8
P
G
4
12
PR7
150K _040 2_5%
10K _0402_5 %
1 2
PU4 B
LM358 ADT_S O8
+
-
PQ2
FDS 443 5BZ_S O8
3
2
1 6
4
PR 3
200K _040 2_5%
MB39 A126
12
PC1 5
IR EF 27
PAC IN
PR3 3
5
6
0.0 1U_ 0402_25V 7K
ACIN 15,27
PACIN 31
VIN
PR2
47K _0402_5 %
1 1
2 2
PR2 3
12
PR2 8
PC2 6
0.0 47U _0402_16 V7K
3 3
4 4
FST CHG27
PR5
47K _0402_1 %
1 2
VI N
12
133K _0603_ 1%
PR2 7
2.1 5K_040 2_1%
1 2
12
10K _0603_0 .1%
PC5
47P _040 2_50V8J
2
13
D
2
G
PQ6
S
RHU 002 N06_ SOT323 -3
PAC IN
A COF F#
3
2
12
PC2 8
0.0 22U _0402_16 V7K
+3VALW
12
13
2
1 2
13
PQ5
DTC 115 EUA_S C70-3
PR1 0
1 2
3K_ 0402_5%
PD5
RLS 414 8_LLDS 2
1 2
PR1 8
1 2
1M_ 0402_5%
P2
12
PC2 4
0.1 U_0 603_25V 7K
8
PU2 A
P
+
1
O
-
G
LM3 93DG_S O8
4
PR3 0
1 2
75K _0402_1 %
4
REF
5
ANODE
LMV431A CM5X _SOT23-5
PR3 4
47K _0402_1 %
2
G
PQ1 2
DDT C11 5EUA -7-F_S OT323- 3
A
2
CATHODE
P2
13
D
S
12
DTA 144EU A_SC 70-3
1 3
2
G
PU 3
3
2
NC
1
NC
CS
PQ1 1
2N7 002- 7-F_SOT 23-3
PQ1
FDS 443 5BZ_S O8
8
7
5
PQ4
13
D
S
PD 4
1.2 4VR EF
BATT_OVP27
8
7
5
ADP _I27
PR1 1
10K _0402_1 %
1 2
12
12
PR1 5
10K _0402 _1%
12
1 2
PR2 1
150K _0402_ 1%
1
0
0.2 2U_0 603_16V7 K
VREF
PR1 6
34. 8K_0 603_1%
PC1 7
MB39 A126
0.2 2U_0 603_16V7 K
12
PR2 4
VIN
8
3
P
+
2
-
G
4
PU4 A
LM358 ADT_S O8
B
PC1 1
1 2
PC1 2
4700 P_0402 _25V7K
1 2
65W: PR46 =34.8K
90W: PR46 =21.0K
PR1 9
1K_ 0402_1%
1 2
12
100K _0402_ 1%
12
PC2 9
0.0 1U_ 0402_25V 7K
B
10K _0402_5 %
1 2
PC2 2
1U_ 0603_6. 3V6M
12
PR3 1
12
PR3 2
12
PR3 5
P4
12
PR 8
PR1 4
100K _040 2_1%
12
PC1 8
2200 P_04 02_50V7K
BATT
340K _0402_ 1%
499K _0402_ 1%
105K _0402_ 1%
AD P_I_A
PR2 5
10K _0402_1 %
12
PC3 0
0.0 1U_0 402_25V7 K
C
B+
PR6
1 2
0.0 15_25 12_1%
PU 1
MB3 9A126 PFV-E R_SSO P24
1
-INC2
2
OUTC2
3
+INE2
4
-INE2
5
ACOK
6
VREF
7
ACIN
8
-INE1
9
+INE1
12
10
OUTC1
11
SEL
12
-INC1
RHU 002 N06_ SOT323 -3
PL2
FBM A-L1 8-453215 -900LMA 90T_1812
1 2
12
12
CHG _B+
24
+INC2
23
GND
22
CS
21
VCC
20
OUT
19
VH
18
XACOK
17
RT
16
-INE3
15
FB123
14
CTL
13
+INC1
+3VALW
PQ1 4
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
12
CS
PC1 4
0.1 U_0 603_25V 7K
PC1 6
0.1 U_06 03_25V7K
1 2
PR2 0
47K _0402_1 %
1 2
PR2 6
1500 P_04 02_50V7K
33K _0402_1 %
MB39 A126
1 2
PC2 5
10P _0402 _50V8J
1 2
CV=12.6V (6/12 CELLS LI-ION)
CC=3.08A (6/12 CELLS LI-ION)
+3VALW
PR3 9
100K _0402_ 5%
1 2
13
D
S
100K _040 2_5%
1 2
2
G
PR1 3
0_04 02_5%
PC1 3
0.2 2U_0 603_16V7 K
1 2
1 2
PC2 3
1 2
PR1 2
C
12
PC7
PC8
0.1 U_06 03_25V7K
12
PR3 6
100K _0402_ 1%
Compal Secret Data
12
PC9
4.7 U_12 06_25V6K
2200 P_0402 _50V7K
PD2
1 2
RB7 51V -40_SO D323-2
PD3
1 2
RB7 51V -40_SO D323-2
PC2 7
47P _0402 _50V8J
1 2
BATT_DET 35
Deciphered Date
PC1 0
PQ3
FDS 443 5BZ_S O8
3
2
1 6
4
CHG_B+
4.7 U_1 206_25V 6K
16
243
PQ1 0
FDS 443 5BZ_S O8
578
16U H_S IL1 045R- 160_4.1 A_30%
1 2
12
PD1
EC3 1QS0 4
FST CHG
8
7
5
PL3
EC_ ON 25, 27
D
PR3 7
10K _0402_5 %
A COF F#
PR9
100K _0402_ 5%
12
+3VLP
RHU 002 N06_S OT323- 3
2
13
D
PAC IN
2
G
PQ9
S
PR1 7
1 2
0.0 2_251 2_1%
Title
Size Docu men t N umber Re v
Cu sto m
Dat e: Sheet of
1 2
13
13
D
PQ7
G
S
RHU 002 N06_ SOT323 -3
12
12
PC2 0
PC1 9
10U _1206 _25VAK
10U _1206 _25VAK
Compal Electronics, Inc.
Charger
Mon day, M arch 0 5, 200 7
D
BATT
PR 4
1 2
47K _0402_5 %
PQ13
DTC 115 EUA_S C70-3
2
12
PC2 1
10U _1206 _25VAK
VIN
AC OF F 27
BATT
3630
A
B
C
D
E
1 1
PL4
FBM-L11-322513-151LMAT_1210
B+
B++
12
12
12
PC33
PC34
10U_1206_25V6M
2200P_0402_50V7K
PQ15
FDS888 4_SO8
PQ21
FDS888 4_SO8
12
2 2
10U_LF9 19AS-100M-P3_4.5A_20%
PL5
+5VALWP
B++
PC41
3 3
4 4
PR48
1
1 2
+
2
PR53
1 2
220U_6 .3VM_R15
12
10.2K_0402_1%
@
PR51
47K_0402_5%
0_0402_5%
12
PC42
0.1U_0 603_25V7K
0.1U_06 03_50V4Z
578
3 6
241
578
3 6
241
VL
PR55
499K_0603_1%
PC31
1 2
DH_5V_B
2VREF_1999
MAINPW ON
12
12
PC46
0.047U_ 0603_16V7K
PR61
0_0402_5%
1 2
PR49
1 2
0_0402_5%
@
PR50
1 2
0_0402_5%@
1 2
PR52
10K_0402_5%
2VREF_1999
MAINPW ON 6,35
D
S
PR41
0_0402_5%
1 2
BST_5V
DH_ 5V
LX_5V
DL_5V
12
PR56
1 2
300K_0402_5%
PQ17
13
2
G
RHU002N0 6_SOT323-3
D
S
2
3
PD6
CHP202UPT_ SOT323-3
1
B++
VL
1
PC40
2
4.7U_0 805_10V4Z
18
PU5
14
BST5
LD05
16
DH5
15
LX5
19
DL5
21
OUT5
9
FB5
1
N.C.
6
SHDN#
4
ON5
3
ON3
12
SKIP#
8
REF
23
PC44
0.22U_ 0603_10V7K
VL
12
PR59
100K_0402_5%
13
2
G
PQ18
RHU002N0 6_SOT323-3
20
V+
GND
PC45
12
PC38
LDO3
25
1
2
4.7U_0 805_10V4Z
PACI N 30
0.1U_0 603_50V4Z
BST_3.3V_BBST_5V_B
VL
PR40
1 2
13
17
TON
VCC
ILIM3
ILIM5
BST3
DH3
DL3
LX3
OUT3
FB3
PGOOD
PRO#
MAX8734AEEI+_QSOP28
10
+3VLP
PR57
0_0402_5%
1 2
12
47_0402_5%
12
PC39
1U_0805_16V7K
5
11
28
26
24
27
22
7
2
13
D
S
RHU002N0 6_SOT323-3
PC35
0.1U_06 03_16V7K
2VREF_1999
PR43
0_0402_5%
1 2
PR45
1 2
499K_0402_1%
@
BST_3.3V
DH_3. 3V
DL_3.3V2VREF_1999
LX_3.3V
2
G
PQ19
0_0402_5%
PR44
1 2
1 2
PR46
499K_0402_1%
@
PR60
100K_0402_5%
1 2
PC32
0.1U_06 03_50V4Z
1 2
B++
12
PR42
0_0402_5%
1 2
PR47
0_0402_5%
1 2
+3VLP
PR62
1 2
100K_0402_5%
PQ20
TP0610K-T1-E3_SOT23
1 3
12
PC36
2200P_0402_50V7K
DH_3.3 V_B
578
PQ16
3 6
241
578
FDS888 4_SO8
PQ22
FDS8884_SO8
PC37
4.7U_1 206_25V6K
12
3 6
241
PL6
10U_LF9 19AS-100M-P3_4.5A_20%
+3VALWP
PR54
1
1 2
+
3.57K_0402_1%
@
PC43
220U_6. 3VM_R15
SPOK 33
2
PR58
1 2
0_0402_5%
+3VLP
PR63
2
100K_0402_5%
1 2
51ON#25
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2007/01/07 2008/01/12
C
Compal Secret Data
Deciphered Date
Compal Electronics, Inc.
Title
Size Docume nt Number Re v
D
Date: Sheet of
3.3VALWP / 5VALWP
Monday , Marc h 05, 2007
E
3631
5
PL7
FBM A-L1 1-322513 -151LMA 50T_1210
B+
12
D D
PC6 1
680P _0402_ 50V7K
SYSON25,27,28
C C
B B
PJP 1
1 2
+5V ALWP
PAD -O PEN 4x4m
PJP 3
1 2
+3V ALWP
PAD -O PEN 4x4m
PJP 4
2 1
PAD -O PEN 2x2m
PJP 5
1 2
+1.8V P
A A
PAD -O PEN 4x4m
PJP 7
1 2
+1.5V SP +1.5V S
PAD -O PEN 4x4m
12
12
PC6 2
2200 P_04 02_50V7K
1 2
PR6 4
0_04 02_5%
MEM_V LD15
0208_add it
+5V ALW
+3V ALW
(400mA ,20mils ,Via NO.= 1)
+2.5V S+2.5VSP
+1.8V
5
1.8V _B+
12
PC6 9
10U _1206 _25V6M
12
PR7 7
470K _040 2_5%
PC5 7
1U_ 0603_ 10V6K
(4.5A, 180mils ,Via NO.= 9)
(3A,12 0mils , Via NO.= 6)
(7A,28 0mils , Via NO.= 14)
(4A,16 0mils , Via NO.=8)
4
12
PR6 7
PC5 5
2200 P_0402 _25V7K
12
+3VLP + 3VL
+1. 2VALW P
+0.9V P
10_0 402_5%
1000 P_0402 _50V7K
@
4
1M_ 0402_5%
12
2 1
PAD -O PEN 2x2m
1 2
PAD -O PEN 4x4m
PJP 8
1 2
PAD -O PEN 3x3m
PR7 6
PC5 4
12
PR6 6
100K _040 2_5%
1
2
3
4
PJP 2
PJP 6
PU6
+5V ALW
12
12
14
15
16
NC
TON
VOUT
EN/PSV
VCCA
FB
PGD
NC5VSSA
PGND7DL
TP
6
17
12
PR7 1
10K _0603_1 %
+1. 2VALW
+0.9V
21
PD7
CH7 51H -40PT_ SOD323 -2
BO OT_1.8V
PR6 5
1 2
0_04 02_5%
13
BST
12
DH
11
LX
10
ILIM
9
VDDP
SC411M LTRT_ML PQ16_4X 4
8
PR7 0
1 2
27K _0603 _0.1%
1 2
PC6 0
33P _0402 _50V8J
LX_1.8 V
PR6 9
1 2
16. 9K_0 402_1%
BO OT1_1.8 V
12
PC5 9
1U_ 0603_ 10V6K
(100mA ,20mils ,Via NO.= 1)
(8A,32 0mils , Via NO.= 16)
(2A,80 mils ,V ia NO.= 4)
3
1
PC5 3
2
10U _1206_2 5V6M
@
1 2
PC5 6
0.1 U_04 02_16V7K
UG_ 1.8V
LG_ 1.8V
578
578
3 6
3 6
241
PQ2 3
FDS 888 4_SO8
241
PQ24
FDS 669 0AS_N L_SO8
2
3.3 UH_ SI L104 5R-3 R3PF_8. 2A_30%
12
PR6 8
4.7 _1206_5 %@
12
PC5 8
680P _0603_ 50V7K@
(400mA ,40mils ,Via NO.= 1)
PU8 APL 5508- 25DC- TRL_SO T89-3
2
+3VS
0208 _use SYSON# to turn o n
SYSON#26,28
SUSP28,33
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
12
PC7 0
1U_ 0603_ 10V6K
+1.8V
12
PC6 3
10U _080 5_10V4 Z
1 2
PR7 3
0_04 02_5%
RHU 002 N06_S OT323- 3
1 2
PR7 5
0_04 02_5%
12
@
PC6 8
2007/01/07 2008/01/12
IN
OUT
GND
1
12
PC6 4
10U _080 5_10V4 Z
@
PQ25
13
D
2
G
S
0.1 U_04 02_16V7K@
Compal Secret Data
Deciphered Date
3
12
PR7 2
1K_ 0402_1%
12
PR7 4
1K_ 0402_1%
2
PL8
1 2
12
PC7 1
4.7 U_0 805_6.3 V6K
12
0.1 U_04 02_16V7K
PC6 6
+2.5V SP
12
PR7 8
150_ 1206_ 5%
PU7
VIN1VCNTL
2
GND
3
VREF
4
VOUT
G29 92F1 U_SO8
12
PC6 7
10U _1206 _6.3V7K
1
+1.8VP
1
12
12
+
PC5 1
PC5 0
2
6
5
NC
7
NC
8
NC
9
TP
PC5 2
220U _6. 3VM_R1 5
0.1 U_04 02_16V7K
0.1 U_04 02_16V7K
+5VALW
12
PC6 5
1U_ 0603_ 16V6K
+0.9VP
Compal Electronics, Inc.
Title
1.8 VP/0.9VSP/2 .5VSP
Size Docu men t Number Re v
Dat e: Sheet of
LA -37 33P
1
0.1
32 36Mon day, M arch 05, 20 07
5
4
3
2
1
PL9
FBM A-L1 1-322513 -151LMA 50T_1210
B+
D D
C C
B B
A A
12
12
12
PC8 1
PC8 2
2200 P_0402 _50V7K
10U _1206 _25V6M
PR8 8
470K _0402_ 5%
SPOK31
10U _120 6_6.3V 7K
PR9 1
0_04 02_5%
1 2
SUS P28, 32
PC8 8
0.1 U_0 402_16V 7K@
12
1U_ 0603_ 10V6K
PC8 3
N9
12
2
G
12
PR8 6
10_0 402_5 %
1 2
0_04 02_5%
PR7 9
2200 P_0402 _25V7K@
12
PC7 7
+1.8V +1.8V
12
PR8 9
1K_ 0402_1%
13
D
PQ2 6
S
RHU 002 N06_S OT323- 3
1000 P_04 02_50V7K
PC7 6
12
VRE F1. 5
12
PR9 0
5.1 K_0402 _1%
12
PR8 7
1M_ 0402_5%
PC7 4
12
@
100K _0402_ 5%
12
PC8 7
0.1 U_04 02_16V7K
+5V ALW
12
21
PD8
12
CH7 51H -40P T_SOD3 23-2
+1.2 V_BOO T
PR8 0
1 2
15
16
TON
EN/PSV
NC5VSSA
6
12
PU1 0
G29 92F1 U_SO8
VIN1VCNTL
2
GND
3
VREF
4
VOUT
12
PC8 6
10U _1206 _6.3V7K
0_04 02_5%
13
14
NC
BST
12
DH
11
LX
10
ILIM
9
VDDP
PGND7DL
SC411 MLTRT_M LPQ16_ 4X4
8
+1. 2V_LG
PR8 4
1 2
14K _0402 _1%
1 2
PC8 0
33P _0402 _50V8J
PR8 5
10K _0402_1 %
6
5
NC
7
NC
8
NC
9
TP
+1.5V SP
+1. 2V_U G
+1.2V _LX
1 2
PR8 1
PU9
1
VOUT
2
VCCA
3
FB
4
PGD
TP
17
+1.2 V_BOO T1
PR8 3
1 2
15. 8K_0 402_1%
12
PC7 9
1U_ 0603_ 10V6K
PC8 4
1U_ 0603_ 10V6K
+5V ALW
B+++
1
PC7 3
2
10U _1206 _25V6M
@
1 2
PC7 5
0.1 U_0 402_16V 7K
578
3 6
578
3 6
241
241
PQ2 7
FDS 8884 _SO8
PQ28
FDS 667 0S_SO 8~D
PL10
1UH _SI L10 4-1R 0-R_11A _30%
1 2
12
PR8 2
@
4.7 _1206 _5%
12
PC7 8
680P _0603_5 0V7K@
4.7 U_0 805_6.3 V6K
+1.2VALWP
1
12
+
PC8 5
PC7 2
2
330U _4V_M
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
Compal Secret Data
2007/01/07 2008/01/12
Deciphered Date
2
Compal Electronics, Inc.
Title
1.2 V_VP/1. 5VSP/1.0 5VP
Size Docu men t Number Re v
Dat e: Sheet of
LA -37 33P
33 36Mon day, M arch 05, 20 07
1
0.1
5
+3VS
D D
PR99
10K_0402_1%
VID06
VID16
VID26
VID36
VID46
VID56
VGATE15 ,27
+3VS
PR114
1 2
PC95
0.1U_04 02_16V7K
1 2
PR123
31.6K_0402_1%
169K_0603_1%
0_0402_5%
1 2
PR126
2
G
1 2
PR95
0_0402_5%
1 2
PR115
100K_0402_1%@
1 2
PR119
10K_0402_1%
CPU_B+
12
N79
13
D
PQ29
2N7002LT1G_SOT23-3
S
PR129
100K_0402_1%
N71
N83
2
PR122
200K_0402_1%
C C
VR_ON1 5,27
PM_DPRSLPVR27
8774REF
B B
PSI#6
A A
12
PR100 0_0402_5%
12
PR102 0_0402_5%
12
PR104 0_0402_5%
12
PR105 0_0402_5%
12
PR106 0_0402_5%
12
PR108 0_0402_5%
1 2
PR110 0_0402_5%
1 2
PR111 100K_0402_1%
PC93
150P_040 2_50V8J
PC96
PC97
470P_040 2_50V8J
1 2
12
PR130
100K_0402_1%
N72
2
G
1
PQ34
PMBT2222A_SOT23-3
3
0.1U_06 03_25V7K
+5VS
12
13
D
S
1 2
PR116 71.5K _0402_1%
1 2
PQ31
2N7002LT1G_SOT23-3
12
12
PR127
0_0402_5%
12
PR98
10_0402_5%
PC114
2.2U_06 03_10V6K
1 2
8774VCC
8774PW RGD
8774PHASEGD
8774VCC
8774SHD N#
8774TIME
12
8774CCV
8774POUT
8774REF
8774TON
8774OFS
12
4
D0
D1
D2
D3
D4
D5
8774SKIP#
+5VS
PU11
MAX8774GTL+_TQFN40
19
VCC
31
D0
32
D1
33
D2
34
D3
35
D4
36
D5
1
PWRGD
17
PHASEGD
37
TWO-PH
38
SHDN#
6
TIME
8
CCV
3
POUT
10
REF
7
TON
2
OFS
4
VRHOT#
39
SKIP#
41
4700P_0402_25V7K
EP
PC102
PR94
10_0402_5%
THRM
PGND1
PGND2
GNDS
12
12
BST1
CSP1
CSN1
BST2
CSP2
CSN2
12
PC113
VDD
DH1
LX1
DL1
GND
IC
FB
CCI
DH2
LX2
DL2
N70
CPU_VSS_S ENSE6
1 2
2.2U_0 603_6.3V6K
25
PR103
5
2.2_0402_5%
8774BST1 8774BST1A
30
1 2
8774DH1
29
8774LX1
28
8774DL1
26
27
8774CSP1
16
8774CS N1
15
AGND
18
PR117
40
2K_0402_1%
8774FB
11
1 2
8774CCI N77
9
1 2
PC94
8774BST2
470P_040 2_50V8J
20
8774DH2
21
8774LX2
22
8774DL2
24
23
8774CSP2
13
8774CS N2
14
12
PR131
100_0402_1%
3
PC119
0.22U_0 603_16V7K
1 2
PC91
4700P_0402_25V7K
1 2
1 2
PR118
20K_0402_1%
1 2
2.2_0402_5%
PR125
8774BST2A
12
PC103
0.22U_ 0603_16V7K
PC105
12
4700P_0402_25V7K@
PR101
0_0402_5%
1 2
1 2
PR128
0_0402_5%
AO4456_SO8
2
CPU_B+ B+
PQ32
12
10U_1206_25V6M
PC109
PQ35
SI7840 DP-T1-E3_SO8
N82
PQ36
3 5
241
AO4456_SO8
578
AO4456_SO8
578
12
PC89
3 6
241
3 6
PQ30
SI7840 DP-T1-E3_SO8
PQ33
AO4456_SO8
578
3 6
241
241
4700P_0402_25V7K
@
1 2
PR120
0_0402_5%
N78
3 5
241
578
3 6
241
1 2
PR97
0_0402_5%
12
12
12
10U_1206_25V6M
PC110
PC108
PC112
PC111
0.01U_ 0402_25V7K
2200P_0402_50V7K
020 7_p owe r c heck f ootpr int
PQ37
PR107
4.7_1206_5%
@
12
PR92
4.7_1206_5%
@
1 2
N76
12
0.36UH_ PCMC104T- R36MN1R17_30A_20%
12
1 2
N81
12
PD9
EC31QS04
PC90
680P_0603_50V8J
@
CPU_B+
12
12
PC98
PC99
10U_1206_25V6M
10U_1206_25V6M
PC100
0.36UH_ PCMC104T- R36MN1R17_30A_20%
12
PD10
EC31QS04
680P_0603_50V8J
PC104
@
12
0.01U_ 0402_25V7K
1
+
68U_25V_M
2
@
1 2
PR109
4.22K_0402_1%
PR112
2.1K_0402_1%
1 2
12
PC101
2200P_0402_50V7K
PR93
4.22K_0402_1%
1 2
PR96
2.1K_0402_1%
1 2
PC92
0.22U_0 603_16V7K
1 2
PC106
0.22U_0 603_16V7K
FBMA-L18-453215-900LMA90T_1812
1 2
12
PC107
1000P_0402_50V7K
PL13
10KB_06 03_5%_ERTJ1VR103J
N80
1 2
1 2
1 2
PL11
10KB_06 03_5%_ERTJ1VR103J
N75
1 2
1 2
PL12
PH1
PR121
100_0402_1%
PH2
1
N73N74
+CPU_CORE
12
PR113
10_0402_5%
12
PR124
0_0402_5%
CPU_VC C_SENSE 6
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2007/01/07 2008/01/12
3
Compal Secret Data
Deciphered Date
Compal Electronics, Inc.
Title
Size Docume nt Number Re v
2
Date: Sheet of
+CPU_CORE
LA -37 33P
1
34 36Mon day, M arch 05, 2007
0.1
A
B
C
D
VMB
PCN2
1 1
TYCO_C -1746706_6P
2 2
3 3
BATT+
6
EC_SMD
5
SMD
EC_SMC
4
SMC
3
RES
2
TS
1
GND
PR135
100_0402_5%
12
12
020 8_r efe r to SPARTA N
3
2
PR133
6.49K_0402_1%
1 2
12
PR134
1K_0402_5%
PR136
100_0402_5%
BATT_DET 30
PR132
@1K_0402_5%
PD11 @SM05_SOT23
1
0.22U_0 603_10V7K
12
+3VL
SMB_EC_DA1
SMB_EC_CK1
PC116
2
3
1
PD12
@SM24.TC_SOT23-3
BATT_TEMP 27
PH1 un der CPU botten side :
CPU th ermal p rotecti on at 90 +-3 degree C
Recove ry at 4 7 +-3 degree C
+5VS
12
CPU
PH3
10K_TH11 -3H103FT_0603_1%
+5VS
12
PR141
12
2.55K_0603_1%
PL14
HCB4532 KF-800T90_1812
1 2
12
PC118
1000P_0402_50V7K
SMB_EC_DA1 26,27
SMB_EC_CK1 26,27
PR139
15K_0603_1%
1 2
1 2
PR140
150K_0402_1%
PR142
150K_0402_1%
12
12
PC115
0.01U_0 402_50V4Z
12
PC117
1000P_0402_50V7K
BATT
PR137
47K_0402_1%
1 2
5
6
8
+
-
4
PU2B
P
7
O
G
LM393DG_SO8
+5VS
PR138
10K_0402_5%
1 2
2
G
13
D
PQ38
RHU002N0 6_SOT323-3
S
MAINPWON 6,31
4 4
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
B
2007/01/07 2008/01/12
Compal Secret Data
Deciphered Date
Compal Electronics, Inc.
Title
Size Docum ent Numbe r Re v
Cus tom
C
Date: Sheet of
LA -37 33P
BATTERY CONN
D
3536Mond ay, Ma rch 05, 2007
5
4
3
2
1
Version change list (P.I.R. List) Page 1 of 1
Reason for change P G# Mo dif y List Phas eIt em
D D
1
Power section
Date
2
3
4
C C
5
6
7
8
B B
9
10
11
12
13
A A
14
Compal Electronics, Inc.
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2
PWR PIR
Size Docum ent N umber Re v
Cus tom
Date : Sh eet of
36 36Monday, March 05, 2007
1
0.1
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