Page 1
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ZZZ1
B
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SE000008600
PCB
1 1
Compal Confidential
2 2
Everest Schematics Document
Intel Merom Processor with Crestline + DDRII + ICH8M
3 3
2007-03-05
REV: 0.2
4 4
Security Classification
Issued Date
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
A
B
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2006/08/18 2007/8/18
Compal Secret Data
Deciphered Date
Title
Size Document Number Rev
B
D
Date: Sheet
Compal Electronics, Inc.
Cover Page
LA-3691P
0.2
of
145Thursday, March 08, 2007
E
Page 2
A
Compal Confidential
B
C
D
E
Model Name : Everest
File Name : LA-3691P
1 1
NB7M
CRT
CRT
page 19
CRT
128M
VGA/B
2 2
LVDS
LCD Conn.
New Card
Socket
page 33
page 18
MINI Card
WLAN,
3G/TV-Tuner
Robson
page 32
LVDS
PCI-Express
PCI-Express
LAN(10/100M)
BCM5906
page 30
Intel Merom Processor
uPGA-478 Package
page 4,5,6
H_A#(3..35) H_D#(0..63)
DMI
X4 mode
FSB
667/800MHz
Intel Crestline
uFCBGA-1299
page 7,8,9,10,11,12,13
Intel ICH8-M
BGA-676
page 20,21,22,23
LPC BUS
Memory BUS(DDRII)
USB conn x2
TO M/B
3.3V 48MHz
3.3V 24.576MHz/48Mhz
3.3V ATA-100
S-ATA
Dual Channel
1.8V DDRII 533/667
page 33
USB
IDE
port 0
S-ATA HDD
Conn.
page 24
200pin DDRII-SO-DIMM X2
BANK 0, 1, 2, 3
USB conn x2
TO I/O/B
page 37 page 33
CDROM
Conn.
Bluetooth
Conn
HD Audio
page 24
page 14,15
MDC 1.5
Conn
page 42
Card Reader
RTS 5158
page 28
HDA Codec
ALC861VD
page 38
3 in 1
socket
page 29
Audio AMP
RJ45
3 3
page 31
page 39
BIOS
page 36
Int SPK
Mic/Int
Mic/ExtLine-out
Sub BD
Fan Control
page 4
Clock Generator
ICS9LPRS365
page 16
USB BD
K_SW
USBx2
Audio BD
Touch Pad
page 36
ENE KB926
page 34
SPI ROM
Int.KBD
page 35
Thermal Sensor
4 4
ADM1032
Power circuit
page 4
page X
SW Board
HDD/ODD NUM CAP Scroll PowerUserMute
MB
A
NOVO
Power Battery W/L
B
Security Classification
Issued Date
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2006/08/18 2007/8/18
Compal Secret Data
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D
Title
Size Document Number Rev
B
Date: Sheet
Compal Electronics, Inc.
Block Diagrams
LA-3691P
of
245Thursday, March 08, 2007
E
0.2
Page 3
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B
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1 1
2 2
Voltage Rails
VIN
B+
+CPU_CORE
+1.05VS
+1.5VS
+1.8V
+2.5VS
+3VALW
+3VS
+5VALW
+5VS
STATE
Full ON
S1(Power On Suspend)
S3 (Suspend to RAM)
S4 (Suspend to Disk)
S5 (Soft OFF)
SIGNAL
DescriptionPower Plane
Adapter power supply (19V)
AC or battery power rail for power circuit.
Core voltage for CPU
0.9V switched power rail for DDR terminator+0.9VS
1.05V switched power rail
1.5V switched power rail
1.8V power rail for DDR
1.8V switched power rail+1.8VS
2.5V switched power rail
3.3V always on power rail
3.3V switched power rail
5V always on power rail
5V switched power rail
RTC power+RTCVCC
SLP_S3#SLP_S1#
SLP_S4#
SLP_S5#
HIGHHIGHHIGHHIGH
HIGH HIGH HIGH
LOW
HIGH
LOW
LOW
LOW LOW LOW
HIGH
HIGH
LOWLOWLOW
LOW
S3S1
N/A N/A N/A
OFFON
OFFON
ON1.25V switched power rail+1.25VS
ON
ON
OFF
ON
ON
OFF
ON
ON
OFF
ON
ON
OFF
ON OFF
ONONON
+VALW
+V +VS Clock
ON
ON
ON
ON
ON
ON
ON
OFF
ON
OFF
S5
N/AN/AN/A
OFF
OFF
OFFOFFON
OFFOFF
OFFOFFON
OFF
OFF
OFF
ON*ON
OFF
ON*
ON*ONVSB always on power rail+VSB
ON
ON
OFF
OFF
OFF
ONON
LOW
OFF
OFF
OFF
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.
External PCI Devices
DEVIC E REQ/GNT #
IDSEL #
PIRQ
No PCI Device
EC SM Bus1 address
Device
Smart Battery
EEPROM(24C16/02)
Address
1010 000X b
EC SM Bus2 address
Device
GMT-781
NVIDIA NB8X
Address
1001 100X b0001 011X b
3 3
BOARD ID Table
ID1
0(R744)
1(R741)
ID0
0(R745)
1(R742)0(R744)
0(R745)
TEST
A-TEST
B-TEST
C-TEST
ICH8M SM Bus address
Device
Clock Generator
(ICS9LPRS325AKLFT_MLF72)
DDR DIMM0
DDR DIMM1
Address
1101 001Xb
1010 000Xb
1010 010Xb
PANEL ID Table
R
Ra (R743)
4 4
A
Size
15W
14WRb (R740)
Security Classification
Issued Date
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
B
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2006/08/18 2007/8/18
Compal Secret Data
Deciphered Date
Title
Size Document Number Rev
B
D
Date: Sheet
Compal Electronics, Inc.
Notes List
LA-3691P
0.2
of
345Thursday, March 08, 2007
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Page 4
5
4
3
2
1
Place close to CPU within 500mil
H_A#[3..35]<7>
H_REQ#[0..4]<7>
H_RS#[0..2]<7>
D D
C C
B B
A A
H_A#[3..35]
H_REQ#[0..4]
H_RS#[0..2]
H_ADSTB#0<7>
H_ADSTB#1<7>
H_STPCLK#<21>
H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35
H_A20M#<21>
H_FERR#<21>
H_IGNNE#<21>
H_INTR<21>
H_NMI<21>
H_SMI#<21>
H_PROCHOT# OCP#
JP15A
J4
ADDR GROUP 0 ADDR GROUP 1
A[3]#
L5
A[4]#
L4
A[5]#
K5
A[6]#
M3
A[7]#
N2
A[8]#
J1
A[9]#
N3
A[10]#
P5
A[11]#
P2
A[12]#
L2
A[13]#
P4
A[14]#
P1
A[15]#
R1
A[16]#
M1
ADSTB[0]#
K3
REQ[0]#
H2
REQ[1]#
K2
REQ[2]#
J3
REQ[3]#
L1
REQ[4]#
Y2
A[17]#
U5
A[18]#
R3
A[19]#
W6
A[20]#
U4
A[21]#
Y5
A[22]#
U1
A[23]#
R4
A[24]#
T5
A[25]#
T3
A[26]#
W2
A[27]#
W5
A[28]#
Y4
A[29]#
U2
A[30]#
V4
A[31]#
W3
A[32]#
AA4
AB2
AA3
V1
A6
A5
C4
D5
C6
B4
A3
M4
N5
T2
V3
B2
C3
D2
D22
D3
F6
FOX_PZ4782A-274M-41_Merom
ME@
+VCCP
12
B
2
E
3 1
Q4
@
MMBT3904_SOT23
A[33]#
A[34]#
A[35]#
ADSTB[1]#
A20M#
FERR#
IGNNE#
STPCLK#
LINT0
LINT1
SMI#
RSVD[01]
RSVD[02]
RSVD[03]
RSVD[04]
RSVD[05]
RSVD[06]
RSVD[07]
RSVD[08]
RSVD[09]
RSVD[10]
R68
56_0402_5%@
C
THERMAL
PROCHOT#
ICH
THERMTRIP#
RESERVED
ADS#
BNR#
BPRI#
DEFER#
DRDY#
DBSY#
BR0#
IERR#
INIT#
LOCK#
CONTROL
RESET#
RS[0]#
RS[1]#
RS[2]#
TRDY#
HIT#
HITM#
BPM[0]#
BPM[1]#
BPM[2]#
BPM[3]#
PRDY#
PREQ#
TCK
TDO
TMS
TRST#
DBR#
XDP/ITP SIGNALS
THERMDA
THERMDC
H CLK
BCLK[0]
BCLK[1]
OCP# <22>
H1
E2
G5
H5
F21
E1
F1
H_IERR#
D20
B3
H4
H_RESET#
C1
H_RS#0
F3
H_RS#1
F4
H_RS#2
G3
G2
G6
E4
XDP_BPM#0
AD4
XDP_BPM#1
AD3
XDP_BPM#2
AD1
XDP_BPM#3
AC4
XDP_BPM#4
AC2
XDP_BPM#5
AC1
XDP_TCK
AC5
XDP_TDI
AA6
TDI
AB3
AB5
AB6
C20
D21
A24
B25
C7
A22
A21
XDP_TDO
XDP_TMS
XDP_TRST#
XDP_DBRESET#
H_PROCHOT#
R70 56_0402_5%
H_THERMDA
H_THERMDC
H_ADS# <7>
H_BNR# <7>
H_BPRI# <7>
H_DEFER# <7>
H_DRDY# <7>
H_DBSY# <7>
H_BR0# <7>
R73 56_0402_5%
Connect SB SYS_RESET# or just left NC
12
12
H_INIT# <21>
H_LOCK# <7>
H_RESET# <7>
H_TRDY# <7>
H_HIT# <7>
H_HITM# <7>
T1
T4
T3
T7
T6
T9
T5
T12
T10
T11
T8
XDP_DBRESET# <22>
H_PROCHOT# <45>
+VCCP
H_THERMTRIP# <8,21>
CLK_CPU_BCLK <16>
CLK_CPU_BCLK# <16>
+VCCP
H_THERMDA
C328
1 2
EC_SMB_CK2<32>
EC_SMB_DA2<32>
H_THERMDC
2200P_0402_50V7K
EC_SMB_DA2
U19
2
3
8
7
G781F_SOP8
Address:100_1100
FAN1 Conn
H_THERMDA, H_THERMDC routing together,
Trace width / Spacing = 10 / 10 mil
+5VS
+VCC_FAN1
EN_FAN1<32>
EN_FAN1
FAN_SPEED1<32>
XDP Reserve
XDP_TDI
XDP_TMS
XDP_TDO
XDP_BPM#5
XDP_HOOK1
XDP_TRST#
XDP_TCK
1 2
0.1U_0402_16V4Z
VDD1
D+
ALERT#
D-
THERM#
SCLK
GND
SDATA
C100 2.2U_0603_16V6K
1 2
U6
1
VEN
2
3
4
GND
VIN
GND
GND
VO
GND
VSET
G993P1UF_SOP8
+3VS
12
R276
10K_0402_5%
1
C341
1000P_0402_50V7K
2
+VCCP
R33 150_0402_1%
1 2
R32 39_0402_1%
1 2
R31 54.9_0402_1%@
1 2
R28 54.9_0402_1%
1 2
R27 54.9_0402_1%@
1 2
R24 560_0402_5%
1 2
R17 27_0402_5%
1 2
+3VS
C327
1
THERM_SCI#
6
THERM#EC_SMB_CK2
4
5
8
7
6
5
R268
10K_0402_5%
1 2
R267 0_0402_5%@
+5VS
12
R26910K_0402_5%
D8
1SS355_SOD323
@
2.2U_0603_16V6K
1000P_0402_50V7K
40mil
+VCC_FAN1
12
12
+3VS
DIODE
Closed to
Connector
D7
1N4148_SOT23@
1 2
C94
1 2
C358
1 2
ME@
EC_THERM# <22,32>
Check : to sb
JP17
1
1
2
2
3
3
4
GND
5
GND
ACES_85205-03001
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2006/08/18 2007/8/18
3
Compal Secret Data
Deciphered Date
Title
Size Document Number Rev
B
2
Date: Sheet
Compal Electronics, Inc.
Merom (1/3)
LA-3691P
0.2
445Thursday, March 08, 2007
1
of
Page 5
5
4
3
2
1
H_D#[0..63]
H_D#0
PAD
PAD
PAD
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
GTL_REF
TEST1
TEST2
TEST3
TEST4
TEST5
TEST6
D D
H_DSTBN#0<7> H_DSTBN#2 <7>
H_DSTBP#0<7> H_DSTBP#2 <7>
H_DINV#0<7>
Close to CPU pin AD26
within 500mils.
C C
Width=20 mil
B B
layout note: Route TEST3 & TEST5 traces on ground referenced layer to the TPs
R263
1K_0402_1%
R261
2K_0402_1%
+VCCP
1 2
1 2
H_DSTBN#1<7> H_DSTBN#3 <7>
H_DSTBP#1<7> H_DSTBP#3 <7>
H_DINV#1<7>
R76 1K_0402_5%@
R67 1K_0402_5%@
C303 0.1U_0402_16V4Z@
1 2
12
12
T14
T2
T13
CPU_BSEL0<16>
CPU_BSEL1<16>
CPU_BSEL2<16>
CPU_BSEL CPU_BSEL2 CPU_BSEL1
JP15B
E22
D[0]#
F24
D[1]#
E26
D[2]#
G22
D[3]#
F23
D[4]#
G25
D[5]#
E25
D[6]#
E23
D[7]#
K24
D[8]#
G24
D[9]#
J24
D[10]#
J23
D[11]#
H22
D[12]#
F26
D[13]#
K22
D[14]#
H23
D[15]#
J26
DSTBN[0]#
H26
DSTBP[0]#
H25
DINV[0]#
N22
D[16]#
K25
D[17]#
P26
D[18]#
R23
D[19]#
L23
D[20]#
M24
D[21]#
L22
D[22]#
M23
D[23]#
P25
D[24]#
P23
D[25]#
P22
D[26]#
T24
D[27]#
R24
D[28]#
L25
D[29]#
T25
D[30]#
N25
D[31]#
L26
DSTBN[1]#
M26
DSTBP[1]#
N24
DINV[1]#
AD26
GTLREF
C23
D25
C24
AF26
AF1
A26
B22
B23
C21
MISC
TEST1
TEST2
TEST3
TEST4
TEST5
TEST6
BSEL[0]
BSEL[1]
BSEL[2]
FOX_PZ4782A-274M-41_Merom
ME@
CPU_BSEL0
DATA GRP 0
DATA GRP 1
D[32]#
D[33]#
D[34]#
D[35]#
D[36]#
D[37]#
D[38]#
D[39]#
D[40]#
D[41]#
D[42]#
D[43]#
D[44]#
D[45]#
D[46]#
DATA GRP 2
D[47]#
DSTBN[2]#
DSTBP[2]#
DINV[2]#
D[48]#
D[49]#
D[50]#
D[51]#
D[52]#
D[53]#
D[54]#
D[55]#
D[56]#
D[57]#
D[58]#
D[59]#
D[60]#
D[61]#
D[62]#
D[63]#
DSTBN[3]#
DATA GRP 3
DSTBP[3]#
DINV[3]#
COMP[0]
COMP[1]
COMP[2]
COMP[3]
DPRSTP#
DPSLP#
DPWR#
PWRGOOD
SLP#
PSI#
Y22
AB24
V24
V26
V23
T22
U25
U23
Y25
W22
Y23
W24
W25
AA23
AA24
AB25
Y26
AA26
U22
AE24
AD24
AA21
AB22
AB21
AC26
AD20
AE22
AF23
AC25
AE21
AD21
AC22
AD23
AF22
AC23
AE25
AF24
AC20
R26
U26
AA1
Y1
E5
B5
D24
D6
D7
AE6
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
COMP0
COMP1
COMP2
COMP3
H_PWRGOOD
H_CPUSLP#
H_DINV#2 <7>
R266 27.4_0402_1%
R264 54.9_0402_1%
R35 27.4_0402_1%
R39 54.9_0402_1%
H_DINV#3 <7>
1 2
1 2
1 2
1 2
H_DPRSTP# <8,21,45>
H_DPSLP# <21>
H_DPWR# <7>
H_PWRGOOD <21>
H_CPUSLP# <7>
H_PSI# <45>
H_D#[0..63] <7>
Resistor placed within
0.5" of CPU pin.Trace
should be at least 25
mils away from any other
toggling signal.
COMP[0,2] trace width is
18 mils. COMP[1,3] trace
width is 4 mils.
+CPU_CORE
JP15C
A7
VCC[001]
A9
VCC[002]
A10
VCC[003]
A12
VCC[004]
A13
VCC[005]
A15
VCC[006]
A17
VCC[007]
A18
VCC[008]
A20
VCC[009]
B7
VCC[010]
B9
VCC[011]
B10
VCC[012]
B12
VCC[013]
B14
VCC[014]
B15
VCC[015]
B17
VCC[016]
B18
VCC[017]
B20
VCC[018]
C9
VCC[019]
C10
VCC[020]
C12
VCC[021]
C13
VCC[022]
C15
VCC[023]
C17
VCC[024]
C18
VCC[025]
D9
VCC[026]
D10
VCC[027]
D12
VCC[028]
D14
VCC[029]
D15
VCC[030]
D17
VCC[031]
D18
VCC[032]
E7
VCC[033]
E9
VCC[034]
E10
VCC[035]
E12
VCC[036]
E13
VCC[037]
E15
VCC[038]
E17
VCC[039]
E18
VCC[040]
E20
VCC[041]
F7
VCC[042]
F9
VCC[043]
F10
VCC[044]
F12
VCC[045]
F14
VCC[046]
F15
VCC[047]
F17
VCC[048]
F18
VCC[049]
F20
VCC[050]
AA7
VCC[051]
AA9
VCC[052]
AA10
VCC[053]
AA12
VCC[054]
AA13
VCC[055]
AA15
VCC[056]
AA17
VCC[057]
AA18
VCC[058]
AA20
VCC[059]
AB9
VCC[060]
AC10
VCC[061]
AB10
VCC[062]
AB12
VCC[063]
AB14
VCC[064]
AB15
AB17
AB18
VCCSENSE
VCC[065]
VCC[066]
VCC[067]
VSSSENSE
FOX_PZ4782A-274M-41_Merom
VCC[068]
VCC[069]
VCC[070]
VCC[071]
VCC[072]
VCC[073]
VCC[074]
VCC[075]
VCC[076]
VCC[077]
VCC[078]
VCC[079]
VCC[080]
VCC[081]
VCC[082]
VCC[083]
VCC[084]
VCC[085]
VCC[086]
VCC[087]
VCC[088]
VCC[089]
VCC[090]
VCC[091]
VCC[092]
VCC[093]
VCC[094]
VCC[095]
VCC[096]
VCC[097]
VCC[098]
VCC[099]
VCC[100]
VCCP[01]
VCCP[02]
VCCP[03]
VCCP[04]
VCCP[05]
VCCP[06]
VCCP[07]
VCCP[08]
VCCP[09]
VCCP[10]
VCCP[11]
VCCP[12]
VCCP[13]
VCCP[14]
VCCP[15]
VCCP[16]
VCCA[01]
VCCA[02]
VID[0]
VID[1]
VID[2]
VID[3]
VID[4]
VID[5]
VID[6]
.
ME@
AB20
AB7
AC7
AC9
AC12
AC13
AC15
AC17
AC18
AD7
AD9
AD10
AD12
AD14
AD15
AD17
AD18
AE9
AE10
AE12
AE13
AE15
AE17
AE18
AE20
AF9
AF10
AF12
AF14
AF15
AF17
AF18
AF20
G21
V6
J6
K6
M6
J21
K21
M21
N21
N6
R21
R6
T21
T6
V21
W21
B26
C26
AD6
AF5
AE5
AF4
AE3
AF3
AE2
AF7
AE7
+CPU_CORE
VCCSENSE
VSSSENSE
Place this cap more close to
B26/C26 rather than 10UF
1
CPU_VID0 <45>
CPU_VID1 <45>
CPU_VID2 <45>
CPU_VID3 <45>
CPU_VID4 <45>
CPU_VID5 <45>
CPU_VID6 <45>
1 2
R13 100_0402_1%
R14 100_0402_1%
1 2
C326
2
0.01U_0402_16V7K
1
+
C317
330U_D2E_2.5VM_R9
2
20mils
VCCSENSE <45>
VSSSENSE <45>
+VCCP
1
C325
10U_0805_10V4Z
2
+CPU_CORE
+1.5VS
166
200
01
0
1
1
0
Length match within 25 mils.
The trace width/space/other is
20/7/25.
Close to CPU pin
A A
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2006/08/18 2007/8/18
3
Compal Secret Data
Deciphered Date
2
within 500mils.
Title
Size Document Number Rev
B
LA-3691P
Date: Sheet
Compal Electronics, Inc.
Merom (2/3)
545Thursday, March 08, 2007
1
0.2
of
Page 6
5
4
3
2
1
+CPU_CORE
JP15D
A4
VSS[001]
A8
VSS[002]
A11
VSS[003]
A14
VSS[004]
A16
VSS[005]
A19
VSS[006]
D D
C C
B B
A23
VSS[007]
AF2
VSS[008]
B6
VSS[009]
B8
VSS[010]
B11
VSS[011]
B13
VSS[012]
B16
VSS[013]
B19
VSS[014]
B21
VSS[015]
B24
VSS[016]
C5
VSS[017]
C8
VSS[018]
C11
VSS[019]
C14
VSS[020]
C16
VSS[021]
C19
VSS[022]
C2
VSS[023]
C22
VSS[024]
C25
VSS[025]
D1
VSS[026]
D4
VSS[027]
D8
VSS[028]
D11
VSS[029]
D13
VSS[030]
D16
VSS[031]
D19
VSS[032]
D23
VSS[033]
D26
VSS[034]
E3
VSS[035]
E6
VSS[036]
E8
VSS[037]
E11
VSS[038]
E14
VSS[039]
E16
VSS[040]
E19
VSS[041]
E21
VSS[042]
E24
VSS[043]
F5
VSS[044]
F8
VSS[045]
F11
VSS[046]
F13
VSS[047]
F16
VSS[048]
F19
VSS[049]
F2
VSS[050]
F22
VSS[051]
F25
VSS[052]
G4
VSS[053]
G1
VSS[054]
G23
VSS[055]
G26
VSS[056]
H3
VSS[057]
H6
VSS[058]
H21
VSS[059]
H24
VSS[060]
J2
VSS[061]
J5
VSS[062]
J22
VSS[063]
J25
VSS[064]
K1
VSS[065]
K4
VSS[066]
K23
VSS[067]
K26
VSS[068]
L3
VSS[069]
L6
VSS[070]
L21
VSS[071]
L24
VSS[072]
M2
VSS[073]
M5
VSS[074]
M22
VSS[075]
M25
VSS[076]
N1
VSS[077]
N4
VSS[078]
N23
VSS[079]
N26
VSS[080]
VSS[081]P3VSS[162]
FOX_PZ4782A-274M-41_Merom
VSS[082]
VSS[083]
VSS[084]
VSS[085]
VSS[086]
VSS[087]
VSS[088]
VSS[089]
VSS[090]
VSS[091]
VSS[092]
VSS[093]
VSS[094]
VSS[095]
VSS[096]
VSS[097]
VSS[098]
VSS[099]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
VSS[159]
VSS[160]
VSS[161]
VSS[163]
.
ME@
P6
P21
P24
R2
R5
R22
R25
T1
T4
T23
T26
U3
U6
U21
U24
V2
V5
V22
V25
W1
W4
W23
W26
Y3
Y6
Y21
Y24
AA2
AA5
AA8
AA11
AA14
AA16
AA19
AA22
AA25
AB1
AB4
AB8
AB11
AB13
AB16
AB19
AB23
AB26
AC3
AC6
AC8
AC11
AC14
AC16
AC19
AC21
AC24
AD2
AD5
AD8
AD11
AD13
AD16
AD19
AD22
AD25
AE1
AE4
AE8
AE11
AE14
AE16
AE19
AE23
AE26
A2
AF6
AF8
AF11
AF13
AF16
AF19
AF21
A25
AF25
330U_D2E_2.5VM
3 x 330uF(9mOhm/2)
1
+
C298
330U_D2E_2.5VM_R9
2
South Side Seco ndary North Side Sec ondary
+CPU_CORE
1
C26
10U_0805_6.3V6M
2
10U_0805_6.3V6M
(Place these capacitors on South side,Secondary Layer)
+CPU_CORE
1
C56
10U_0805_6.3V6M
2
10U_0805_6.3V6M
(Place these capacitors on North side,Secondary Layer)
+CPU_CORE
1
C315
10U_0805_6.3V6M
2
10U_0805_6.3V6M
(Place these capacitors on South side,Primary Layer)
+CPU_CORE
1
C313
10U_0805_6.3V6M
2
10U_0805_6.3V6M
(Place these capacitors on North side,Primary Layer)
+CPU-CORE
Decoupling
SPCAP,Polymer
MLCC 0805 X5R
1
+
C324
2
0.1U_0402_16V4Z
1
+
C297
2
330U_D2E_2.5VM_R9
1
C27
2
10U_0805_6.3V6M
1
C55
2
10U_0805_6.3V6M
1
C316
2
10U_0805_6.3V6M
1
C314
2
10U_0805_6.3V6M
+VCCP
1
C38
0.1U_0402_16V4Z
2
1
C28
10U_0805_6.3V6M
2
1
C54
10U_0805_6.3V6M
2
1
C305
10U_0805_6.3V6M
2
1
C323
10U_0805_6.3V6M
2
C,uF ESR, mohm ESL,nH
6X330uF 9m ohm/6 1.8nH/6
32X22uF 3m ohm/32 0.6nH/32
32X10uF 3m ohm/32 0.6nH/32
1
C43
2
0.1U_0402_16V4Z
1
2
1
2
1
2
1
2
1
C58
0.1U_0402_16V4Z
2
+CPU_CORE
1
+
C332
330U_D2E_2.5VM_R9
2
330U_D2E_2.5VM_R9
C29
C53
C306
C322
1
C30
2
10U_0805_6.3V6M
1
C52
2
10U_0805_6.3V6M
1
C307
2
10U_0805_6.3V6M
1
C321
2
10U_0805_6.3V6M
1
C24
2
0.1U_0402_16V4Z
3 x 330uF(9mOhm/2)
1
+
C331
2
1
C31
10U_0805_6.3V6M
2
10U_0805_6.3V6M
1
C51
10U_0805_6.3V6M
2
10U_0805_6.3V6M
1
C308
10U_0805_6.3V6M
2
10U_0805_6.3V6M
1
C320
10U_0805_6.3V6M
2
10U_0805_6.3V6M
1
2
C39
0.1U_0402_16V4Z
1
C45
2
1
2
1
2
1
2
1
2
C32
C50
C309
C319
10U_0805_6.3V6M
10U_0805_6.3V6M
10U_0805_6.3V6M
10U_0805_6.3V6M
1
C33
2
1
C49
2
1
C310
2
1
C318
2
9/25 10U checked. OK for use!
A A
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2006/08/18 2007/8/18
3
Compal Secret Data
Deciphered Date
Title
Size Document Number Rev
B
2
Date: Sheet
Compal Electronics, Inc.
Merom (3/3)
LA-3691P
0.2
645Thursday, March 08, 2007
1
of
Page 7
5
4
3
2
1
H_A#[3..35] <4>
H_ADS# <4>
H_ADSTB#0 <4>
H_ADSTB#1 <4>
H_BNR# <4>
H_BPRI# <4>
H_BR0# <4>
H_DEFER# <4>
H_DBSY# <4>
CLK_MCH_BCLK <16>
CLK_MCH_BCLK# <16>
H_DPWR# <5>
H_DRDY# <4>
H_HIT# <4>
H_HITM# <4>
H_LOCK# <4>
H_TRDY# <4>
H_DINV#0 <5>
H_DINV#1 <5>
H_DINV#2 <5>
H_DINV#3 <5>
H_DSTBN#0 <5>
H_DSTBN#1 <5>
H_DSTBN#2 <5>
H_DSTBN#3 <5>
H_DSTBP#0 <5>
H_DSTBP#1 <5>
H_DSTBP#2 <5>
H_DSTBP#3 <5>
H_REQ#[0..4] <4>
H_RS#[0..2] <4>
U20
965GM
@
U20
960GM
GM@
M10
N12
P13
W10
AD12
AE3
AD9
AC9
AC7
AC14
AD11
AC11
AB2
AD7
AB1
AC6
AE2
AC5
AG3
AJ9
AH8
AJ14
AE9
AE11
AH12
AJ5
AH5
AJ6
AE7
AJ7
AJ2
AE5
AJ3
AH2
AH13
E2
G2
G7
M6
H7
H3
G4
F3
N8
H2
N9
H5
K9
M2
Y8
V4
M3
J1
N5
N3
W6
W9
N2
Y7
Y9
P4
W3
N1
Y3
B3
C2
W1
W2
B6
E5
B9
A9
U20A
H_D#_0
H_D#_1
H_D#_2
H_D#_3
H_D#_4
H_D#_5
H_D#_6
H_D#_7
H_D#_8
H_D#_9
H_D#_10
H_D#_11
H_D#_12
H_D#_13
H_D#_14
H_D#_15
H_D#_16
H_D#_17
H_D#_18
H_D#_19
H_D#_20
H_D#_21
H_D#_22
H_D#_23
H_D#_24
H_D#_25
H_D#_26
H_D#_27
H_D#_28
H_D#_29
H_D#_30
H_D#_31
H_D#_32
H_D#_33
H_D#_34
H_D#_35
H_D#_36
H_D#_37
H_D#_38
H_D#_39
H_D#_40
H_D#_41
H_D#_42
H_D#_43
H_D#_44
H_D#_45
H_D#_46
H_D#_47
H_D#_48
H_D#_49
H_D#_50
H_D#_51
H_D#_52
H_D#_53
H_D#_54
H_D#_55
H_D#_56
H_D#_57
H_D#_58
H_D#_59
H_D#_60
H_D#_61
H_D#_62
H_D#_63
H_SWING
H_RCOMP
H_SCOMP
H_SCOMP#
H_CPURST#
H_CPUSLP#
H_AVREF
H_DVREF
CRESTLINE_1p0
PM@
HOST
H_A#_3
H_A#_4
H_A#_5
H_A#_6
H_A#_7
H_A#_8
H_A#_9
H_A#_10
H_A#_11
H_A#_12
H_A#_13
H_A#_14
H_A#_15
H_A#_16
H_A#_17
H_A#_18
H_A#_19
H_A#_20
H_A#_21
H_A#_22
H_A#_23
H_A#_24
H_A#_25
H_A#_26
H_A#_27
H_A#_28
H_A#_29
H_A#_30
H_A#_31
H_A#_32
H_A#_33
H_A#_34
H_A#_35
H_ADS#
H_ADSTB#_0
H_ADSTB#_1
H_BNR#
H_BPRI#
H_BREQ#
H_DEFER#
H_DBSY#
HPLL_CLK
HPLL_CLK#
H_DPWR#
H_DRDY#
H_HIT#
H_HITM#
H_LOCK#
H_TRDY#
H_DINV#_0
H_DINV#_1
H_DINV#_2
H_DINV#_3
H_DSTBN#_0
H_DSTBN#_1
H_DSTBN#_2
H_DSTBN#_3
H_DSTBP#_0
H_DSTBP#_1
H_DSTBP#_2
H_DSTBP#_3
H_REQ#_0
H_REQ#_1
H_REQ#_2
H_REQ#_3
H_REQ#_4
H_RS#_0
H_RS#_1
H_RS#_2
J13
B11
C11
M11
C15
F16
L13
G17
C14
K16
B13
L16
J17
B14
K19
P15
R17
B16
H20
L19
D17
M17
N16
J19
B18
E19
B17
B15
E17
C18
A19
B19
N19
G12
H17
G20
C8
E8
F12
D6
C10
AM5
AM7
H8
K7
E4
C6
G10
B7
K5
L2
AD13
AE13
M7
K3
AD2
AH11
L7
K2
AC2
AJ10
M14
E13
A11
H13
B12
E12
D7
D8
H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35
H_ADS#
H_ADSTB#0
H_ADSTB#1
H_BNR#
H_BPRI#
H_BR0#
H_DEFER#
H_DBSY#
CLK_MCH_BCLK
CLK_MCH_BCLK#
H_DPWR#
H_DRDY#
H_HIT#
H_HITM#
H_LOCK#
H_TRDY#
H_DINV#0
H_DINV#1
H_DINV#2
H_DINV#3
H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3
H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
H_RS#0
H_RS#1
H_RS#2
H_D#[0..63]<5>
D D
+VCCP
12
R279
221_0402_1%
H_SWNG
1
C C
R282
100_0402_1%
1 2
C360
0.1U_0402_16V4Z
2
Near B3 pin
H_RCOMP
12
R283
24.9_0402_1%
layout note:
Route H_SCOMP and H_SCOMP# with
trace width, spacing and
impedance (55 ohm) same as FSB
data traces
B B
+VCCP
R112
1K_0402_1%
1 2
12
R117
2K_0402_1%
54.9_0402_1%
R164
1
2
+VCCP
1 2
H_RESET#<4>
H_CPUSLP#<5>
C91
0.1U_0402_16V4Z
R168
54.9_0402_1%
1 2
H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
H_SWNG
H_RCOMP
H_SCOMP
H_SCOMP#
H_RESET#
H_CPUSLP#
H_VREF
within 100mil to Ball A9,B9
A A
Layout Note:
H_RCOMP / H_VREF / H_SWNG
trace width and spacing is 10/20
5
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2006/08/18 2007/8/18
3
Compal Secret Data
Deciphered Date
Title
Size Document Number Rev
B
2
Date: Sheet
Compal Electronics, Inc.
Crestline (1/7)-GTL
LA-3691P
1
0.2
745Thursday, March 08, 2007
of
Page 8
5
D D
DDRA_SMA14<14>
DDRB_SMA14<15>
DDRA_SMA14
DDRB_SMA14
9/20 Modify NB symbol for Pin BJ29/BE24/C48/D47
C C
MCH_CLKSEL0<16>
MCH_CLKSEL1<16>
MCH_CLKSEL2<16>
B B
PM_BMBUSY#<22>
H_DPRSTP#<5,21,45>
PM_EXTTS#0<14>
PLT_RST_BUF#<17,20,22,24,25,30>
H_THERMTRIP#<4,21>
PM_EXTTS#1<15>
PM_DPRSLPVR<22,45>
PM_EXTTS#0
PM_EXTTS#1
R176 100_0402_5%
R104 0_0402_5%
1 2
MCH_CLKSEL0
MCH_CLKSEL1
MCH_CLKSEL2
MCH_CFG_5
MCH_CFG_7
MCH_CFG_8
MCH_CFG_9
MCH_CFG_12
MCH_CFG_13
MCH_CFG_16
MCH_CFG_19
MCH_CFG_20
GMCH_PWROK
MCH_RSTIN#
If THERMTRIP no used, left NC
Use VGATE for GMCH_PWROK
VGATE<22,45>
ICH_POK<22,32>
A A
VGATE
ICH_POK
1 2
R184 0_0402_5%@
1 2
R186 0_0402_5%
GMCH_PWROK
P36
P37
R35
N35
AR12
AR13
AM12
AN13
AR37
AM36
AL36
AM37
D20
H10
B51
BJ20
BK22
BF19
BH20
BK18
BJ18
BF23
BG23
BC23
BD24
BJ29
BE24
BH39
AW20
BK20
C48
D47
B44
C44
A35
B37
B36
B34
C34
M20
M24
G41
AW49
AV20
N20
G36
BJ51
BK51
BK50
BL50
BL49
BL3
BL2
BK1
C51
B50
A50
A49
BK2
J12
P27
N27
N24
C21
C23
F23
N23
G23
J20
C20
R24
L23
J23
E23
E20
K23
L32
N33
L35
L39
L36
J36
BJ1
4
E1
A5
U20B
RSVD1
RSVD2
RSVD3
RSVD4
RSVD5
RSVD6
RSVD7
RSVD8
RSVD9
RSVD10
RSVD11
RSVD12
RSVD13
RSVD14
RSVD20
RSVD21
RSVD22
RSVD23
RSVD24
RSVD25
RSVD26
RSVD27
RSVD28
RSVD29
RSVD30
RSVD31
SA_MA_14
SB_MA_14
RSVD34
RSVD35
RSVD36
LVDSA_DATA#_3
LVDSA_DATA_3
RSVD39
RSVD40
RSVD41
RSVD42
RSVD43
RSVD44
RSVD45
CFG_0
CFG_1
CFG_2
CFG_3
CFG_4
CFG_5
CFG_6
CFG_7
CFG_8
CFG_9
CFG_10
CFG_11
CFG_12
CFG_13
CFG_14
CFG_15
CFG_16
CFG_17
CFG_18
CFG_19
CFG_20
PM_BM_BUSY#
PM_DPRSTP#
PM_EXT_TS#_0
PM_EXT_TS#_1
PWROK
RSTIN#
THERMTRIP#
DPRSLPVR
NC_1
NC_2
NC_3
NC_4
NC_5
NC_6
NC_7
NC_8
NC_9
NC_10
NC_11
NC_12
NC_13
NC_14
NC_15
NC_16
CRESTLINE_1p0
PM@
DDR MUXINGCLK
DPLL_REF_SSCLK#
CFGRSVD
DMI
PM
GRAPHICS VID
ME
NC
SDVO_CTRL_DATA
MISC
SM_CK_0
SM_CK_1
SM_CK_3
SM_CK_4
SM_CK#_0
SM_CK#_1
SM_CK#_3
SM_CK#_4
SM_CKE_0
SM_CKE_1
SM_CKE_3
SM_CKE_4
SM_CS#_0
SM_CS#_1
SM_CS#_2
SM_CS#_3
SM_ODT_0
SM_ODT_1
SM_ODT_2
SM_ODT_3
SM_RCOMP
SM_RCOMP#
SM_RCOMP_VOH
SM_RCOMP_VOL
SM_VREF_0
SM_VREF_1
DPLL_REF_CLK
DPLL_REF_CLK#
DPLL_REF_SSCLK
PEG_CLK
PEG_CLK#
DMI_RXN_0
DMI_RXN_1
DMI_RXN_2
DMI_RXN_3
DMI_RXP_0
DMI_RXP_1
DMI_RXP_2
DMI_RXP_3
DMI_TXN_0
DMI_TXN_1
DMI_TXN_2
DMI_TXN_3
DMI_TXP_0
DMI_TXP_1
DMI_TXP_2
DMI_TXP_3
GFX_VID_0
GFX_VID_1
GFX_VID_2
GFX_VID_3
GFX_VR_EN
CL_CLK
CL_DATA
CL_PWROK
CL_RST#
CL_VREF
SDVO_CTRL_CLK
CLK_REQ#
ICH_SYNC#
TEST_1
TEST_2
AV29
BB23
BA25
AV23
AW30
BA23
AW25
AW23
BE29
AY32
BD39
BG37
BG20
BK16
BG16
BE13
BH18
BJ15
BJ14
BE16
BL15
BK14
BK31
BL31
AR49
AW4
B42
C42
H48
H47
K44
K45
AN47
AJ38
AN42
AN46
AM47
AJ39
AN41
AN45
AJ46
AJ41
AM40
AM44
AJ47
AJ42
AM39
AM43
E35
A39
C38
B39
E36
AM49
AK50
AT43
AN49
AM50
H35
K36
G39
G40
A37
R32
3
SMRCOMP
SMRCOMP#
SM_RCOMP_VOH
SM_RCOMP_VOL
CLK_DREF_96M
CLK_DREF_96M#
CLK_DREF_SSC
CLK_DREF_SSC#
CLK_MCH_3GPLL
CLK_MCH_3GPLL#
DMI_ITX_MRX_N0
DMI_ITX_MRX_N1
DMI_ITX_MRX_N2
DMI_ITX_MRX_N3
DMI_ITX_MRX_P0
DMI_ITX_MRX_P1
DMI_ITX_MRX_P2
DMI_ITX_MRX_P3
DMI_MTX_IRX_N0
DMI_MTX_IRX_N1
DMI_MTX_IRX_N2
DMI_MTX_IRX_N3
DMI_MTX_IRX_P0
DMI_MTX_IRX_P1
DMI_MTX_IRX_P2
DMI_MTX_IRX_P3
CL_VREF
SDVO_CTRL_CLK
SDVO_CTRL_DATA
MCH_CLKREQ#
MCH_TEST_1
MCH_TEST_2
DDRA_CLK0 <14>
DDRA_CLK1 <14>
DDRB_CLK0 <15>
DDRB_CLK1 <15>
DDRA_CLK0# <14>
DDRA_CLK1# <14>
DDRB_CLK0# <15>
DDRB_CLK1# <15>
DDRA_CKE0 <14>
DDRA_CKE1 <14>
DDRB_CKE0 <15>
DDRB_CKE1 <15>
DDRA_SCS0# <14>
DDRA_SCS1# <14>
DDRB_SCS0# <15>
DDRB_SCS1# <15>
DDRA_ODT0 <14>
DDRA_ODT1 <14>
DDRB_ODT0 <15>
DDRB_ODT1 <15>
R382 20_0402_1%
1 2
R381 20_0402_1%
1 2
SM_VREF
CLK_DREF_96M <16>
CLK_DREF_96M# <16>
CLK_DREF_SSC <16>
CLK_DREF_SSC# <16>
CLK_MCH_3GPLL <16>
CLK_MCH_3GPLL# <16>
DMI_ITX_MRX_N0 <22>
DMI_ITX_MRX_N1 <22>
DMI_ITX_MRX_N2 <22>
DMI_ITX_MRX_N3 <22>
DMI_ITX_MRX_P0 <22>
DMI_ITX_MRX_P1 <22>
DMI_ITX_MRX_P2 <22>
DMI_ITX_MRX_P3 <22>
DMI_MTX_IRX_N0 <22>
DMI_MTX_IRX_N1 <22>
DMI_MTX_IRX_N2 <22>
DMI_MTX_IRX_N3 <22>
DMI_MTX_IRX_P0 <22>
DMI_MTX_IRX_P1 <22>
DMI_MTX_IRX_P2 <22>
DMI_MTX_IRX_P3 <22>
CL_CLK0 <22>
CL_DATA0 <22>
CL_PWROK <22>
CL_RST# <22>
MCH_CLKREQ# <16>
MCH_ICH_SYNC# <22>
R124 0_0402_5%
R158 20K_0402_5%
20mil
+1.8V
1
C161
0.1U_0402_16V4Z
2
C142
1
0.1U_0402_16V4Z
2
2
Layout Note:
SM_VREF trace
width and spacing
is 20/20.
+1.8V
R182
1K_0402_1%
1 2
R180
1K_0402_1%
1 2
+1.25VS
R173
1K_0402_1%
1 2
R172
392_0402_1%
1 2
+1.8V
R410
1K_0402_1%
R397
3.01K_0402_1%
R384
1K_0402_1%
C469
2.2U_0805_10V6K
C467
2.2U_0805_10V6K
C465
0.01U_0402_16V7K
C464
0.01U_0402_16V7K
CLK_DREF_96M#
CLK_DREF_SSC#
CLK_DREF_96M
CLK_DREF_SSC
SM_RCOMP_VOH
SM_RCOMP_VOH
SM_RCOMP_VOL
CFG[17:3] have internal pull up
CFG[19:18] have internal pull down
CFG[2:0]
CFG5
CFG9
CFG[13:12]
CFG16
CFG19
CFG20
(PCIE/SDVO select)
SDVO_CTRLDATA
MCH_CFG_5
MCH_CFG_9
MCH_CFG_12
MCH_CFG_13
MCH_CFG_16
MCH_CFG_7
MCH_CFG_8
MCH_CFG_19
MCH_CFG_20
PM_EXTTS#0
PM_EXTTS#1
MCH_CLKREQ#
SDVO_CTRL_CLK
SDVO_CTRL_DATA
011 = 667MT/s FSB
010 = 800MT/s FSB
0 = DMI x 2
1 = DMI x 4
0 = Lane Reversal Enable
1 = Normal Operation
00 = Reserved
01 = XOR Mode Enabled
10 = All Z Mode Enabled
11 = Normal Operation
0 = Dynamic ODT Disabled
1 = Dynamic ODT Enabled
0 = Normal Operation
1 = DMI Lane Reversal Enable
0 = Only PCIE or SDVO is operational.
*
(Default)
1 = PCIE/SDVO are operating simu.
0 = No SDVO Device Present
1 = SDVO Device Present
R132 4.02K_0402_1%@
R141 4.02K_0402_1%@
R145 4.02K_0402_1%@
R133 4.02K_0402_1%@
R155 4.02K_0402_1%@
R135 4.02K_0402_1%@
R151 4.02K_0402_1%@
R113 4.02K_0402_1%@
R126 4.02K_0402_1%@
R114 10K_0402_5%
R138 10K_0402_5%
R125 10K_0402_5%
1 2
R149 0_0402_5%@
1 2
R160 0_0402_5%@
1
Maybe not used
1 2
R122 0_0402_5%PM@
1 2
R146 0_0402_5%PM@
1 2
R123 0_0402_5%PM@
1 2
R142 0_0402_5%PM@
Strap Pin Table
*
(Default)
*
(Default)
(Default)
*
*
*
(Default)
(Default)
(Default)
*
+3VS
+3VS
+VCCP
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2006/08/18 2007/8/18
3
Compal Secret Data
Deciphered Date
Title
Size Document Number Rev
Custom
2
Date: Sheet
Compal Electronics, Inc.
Crestline (2/7)-DMI/DDR
LA-3691P
1
845Thursday, Ma r c h 08, 2007
0.2
of
Page 9
5
4
3
2
1
DDRA_SDQ[0..63]< 14>
D D
DDRA_SDQ0
DDRA_SDQ1
DDRA_SDQ2
DDRA_SDQ3
DDRA_SDQ4
DDRA_SDQ5
DDRA_SDQ6
DDRA_SDQ7
DDRA_SDQ8
DDRA_SDQ9
DDRA_SDQ10
DDRA_SDQ11
DDRA_SDQ12
DDRA_SDQ13
DDRA_SDQ14
DDRA_SDQ15
DDRA_SDQ16
DDRA_SDQ17
C C
B B
DDRA_SDQ18
DDRA_SDQ19
DDRA_SDQ20
DDRA_SDQ21
DDRA_SDQ22
DDRA_SDQ23
DDRA_SDQ24
DDRA_SDQ25
DDRA_SDQ26
DDRA_SDQ27
DDRA_SDQ28
DDRA_SDQ29
DDRA_SDQ30
DDRA_SDQ31
DDRA_SDQ32
DDRA_SDQ33
DDRA_SDQ34
DDRA_SDQ35
DDRA_SDQ36
DDRA_SDQ37
DDRA_SDQ38
DDRA_SDQ39
DDRA_SDQ40
DDRA_SDQ41
DDRA_SDQ42
DDRA_SDQ43
DDRA_SDQ44
DDRA_SDQ45
DDRA_SDQ46
DDRA_SDQ47
DDRA_SDQ48
DDRA_SDQ49
DDRA_SDQ50
DDRA_SDQ51
DDRA_SDQ52
DDRA_SDQ53
DDRA_SDQ54
DDRA_SDQ55
DDRA_SDQ56
DDRA_SDQ57
DDRA_SDQ58
DDRA_SDQ59
DDRA_SDQ60
DDRA_SDQ61
DDRA_SDQ62
DDRA_SDQ63
DDRA_SDM[0..7]<14>
DDRA_SMA[0..13]<14>
AR43
AW44
BA45
AY46
AR41
AR45
AT42
AW47
BB45
BF48
BG47
BJ45
BB47
BG50
BH49
BE45
AW43
BE44
BG42
BE40
BF44
BH45
BG40
BF40
AR40
AW40
AT39
AW36
AW41
AY41
AV38
AT38
AV13
AT13
AW11
AV11
AU15
AT11
BA13
BA11
BE10
BD10
BD8
AY9
BG10
AW9
BD7
BB9
BB5
AY7
AT5
AT7
AY6
BB7
AR5
AR8
AR9
AN3
AM8
AN10
AT9
AN9
AM9
AN11
U20D
SA_DQ_0
SA_DQ_1
SA_DQ_2
SA_DQ_3
SA_DQ_4
SA_DQ_5
SA_DQ_6
SA_DQ_7
SA_DQ_8
SA_DQ_9
SA_DQ_10
SA_DQ_11
SA_DQ_12
SA_DQ_13
SA_DQ_14
SA_DQ_15
SA_DQ_16
SA_DQ_17
SA_DQ_18
SA_DQ_19
SA_DQ_20
SA_DQ_21
SA_DQ_22
SA_DQ_23
SA_DQ_24
SA_DQ_25
SA_DQ_26
SA_DQ_27
SA_DQ_28
SA_DQ_29
SA_DQ_30
SA_DQ_31
SA_DQ_32
SA_DQ_33
SA_DQ_34
SA_DQ_35
SA_DQ_36
SA_DQ_37
SA_DQ_38
SA_DQ_39
SA_DQ_40
SA_DQ_41
SA_DQ_42
SA_DQ_43
SA_DQ_44
SA_DQ_45
SA_DQ_46
SA_DQ_47
SA_DQ_48
SA_DQ_49
SA_DQ_50
SA_DQ_51
SA_DQ_52
SA_DQ_53
SA_DQ_54
SA_DQ_55
SA_DQ_56
SA_DQ_57
SA_DQ_58
SA_DQ_59
SA_DQ_60
SA_DQ_61
SA_DQ_62
SA_DQ_63
CRESTLINE_1p0
PM@
DDRA_SDQ[0..63]
DDRA_SDM[0..7]
DDRA_SMA[0..13]
BB19
SA_BS_0
BK19
SA_BS_1
BF29
SA_BS_2
BL17
SA_CAS#
SA_DM_0
SA_DM_1
SA_DM_2
SA_DM_3
SA_DM_4
SA_DM_5
SA_DM_6
SA_DM_7
SA_DQS_0
SA_DQS_1
SA_DQS_2
SA_DQS_3
SA_DQS_4
SA_DQS_5
SA_DQS_6
SA_DQS_7
SA_DQS#_0
SA_DQS#_1
SA_DQS#_2
SA_DQS#_3
SA_DQS#_4
SA_DQS#_5
SA_DQS#_6
SA_DQS#_7
SA_MA_0
SA_MA_1
SA_MA_2
SA_MA_3
SA_MA_4
SA_MA_5
SA_MA_6
SA_MA_7
SA_MA_8
SA_MA_9
SA_MA_10
SA_MA_11
SA_MA_12
SA_MA_13
SA_RAS#
SA_RCVEN#
DDR SYSTEM MEMORY A
SA_WE#
AT45
BD44
BD42
AW38
AW13
BG8
AY5
AN6
AT46
BE48
BB43
BC37
BB16
BH6
BB2
AP3
AT47
BD47
BC41
BA37
BA16
BH7
BC1
AP2
BJ19
BD20
BK27
BH28
BL24
BK28
BJ27
BJ25
BL28
BA28
BC19
BE28
BG30
BJ16
BE18
AY20
BA19
DDRA_SDM0
DDRA_SDM1
DDRA_SDM2
DDRA_SDM3
DDRA_SDM4
DDRA_SDM5
DDRA_SDM6
DDRA_SDM7
DDRA_SDQS0
DDRA_SDQS1
DDRA_SDQS2
DDRA_SDQS3
DDRA_SDQS4
DDRA_SDQS5
DDRA_SDQS6
DDRA_SDQS7
DDRA_SDQS0#
DDRA_SDQS1#
DDRA_SDQS2#
DDRA_SDQS3#
DDRA_SDQS4#
DDRA_SDQS5#
DDRA_SDQS6#
DDRA_SDQS7#
DDRA_SMA0
DDRA_SMA1
DDRA_SMA2
DDRA_SMA3
DDRA_SMA4
DDRA_SMA5
DDRA_SMA6
DDRA_SMA7
DDRA_SMA8
DDRA_SMA9
DDRA_SMA10
DDRA_SMA11
DDRA_SMA12
DDRA_SMA13
SA_RCVEN#
DDRA_SBS0 <14>
DDRA_SBS1 <14>
DDRA_SBS2 <14>
DDRA_SCAS# <14>
DDRA_SDQS0 <14>
DDRA_SDQS1 <14>
DDRA_SDQS2 <14>
DDRA_SDQS3 <14>
DDRA_SDQS4 <14>
DDRA_SDQS5 <14>
DDRA_SDQS6 <14>
DDRA_SDQS7 <14>
DDRA_SDQS0# <14>
DDRA_SDQS1# <14>
DDRA_SDQS2# <14>
DDRA_SDQS3# <14>
DDRA_SDQS4# <14>
DDRA_SDQS5# <14>
DDRA_SDQS6# <14>
DDRA_SDQS7# <14>
DDRA_SRAS# <14>
PAD
T15
DDRA_SWE# <14>
DDRB_SDQ0
DDRB_SDQ1
DDRB_SDQ2
DDRB_SDQ3
DDRB_SDQ4
DDRB_SDQ5
DDRB_SDQ6
DDRB_SDQ7
DDRB_SDQ8
DDRB_SDQ9
DDRB_SDQ10
DDRB_SDQ11
DDRB_SDQ12
DDRB_SDQ13
DDRB_SDQ14
DDRB_SDQ15
DDRB_SDQ16
DDRB_SDQ17
DDRB_SDQ18
DDRB_SDQ19
DDRB_SDQ20
DDRB_SDQ21
DDRB_SDQ22
DDRB_SDQ23
DDRB_SDQ24
DDRB_SDQ25
DDRB_SDQ26
DDRB_SDQ27
DDRB_SDQ28
DDRB_SDQ29
DDRB_SDQ30
DDRB_SDQ31
DDRB_SDQ32
DDRB_SDQ33
DDRB_SDQ34
DDRB_SDQ35
DDRB_SDQ36
DDRB_SDQ37
DDRB_SDQ38
DDRB_SDQ39
DDRB_SDQ40
DDRB_SDQ41
DDRB_SDQ42
DDRB_SDQ43
DDRB_SDQ44
DDRB_SDQ45
DDRB_SDQ46
DDRB_SDQ47
DDRB_SDQ48
DDRB_SDQ49
DDRB_SDQ50
DDRB_SDQ51
DDRB_SDQ52
DDRB_SDQ53
DDRB_SDQ54
DDRB_SDQ55
DDRB_SDQ56
DDRB_SDQ57
DDRB_SDQ58
DDRB_SDQ59
DDRB_SDQ60
DDRB_SDQ61
DDRB_SDQ62
DDRB_SDQ63
DDRB_SDQ[0..63]< 15>
AP49
AR51
AW50
AW51
AN51
AN50
AV50
AV49
BA50
BB50
BA49
BE50
BA51
AY49
BF50
BF49
BJ50
BJ44
BJ43
BL43
BK47
BK49
BK43
BK42
BJ41
BL41
BJ37
BJ36
BK41
BJ40
BL35
BK37
BK13
BE11
BK11
BC11
BC13
BE12
BC12
BG12
BJ10
BK10
BH5
BG1
BC2
BD3
AR1
AU2
DDRB_SMA[0..13]<15>
BL9
BK5
BL5
BK9
BF4
BK3
BE4
BA3
BB3
AT3
AY2
AY3
AT2
DDRB_SDM[0..7]<15>
BJ8
BJ6
BJ2
U20E
SB_DQ_0
SB_DQ_1
SB_DQ_2
SB_DQ_3
SB_DQ_4
SB_DQ_5
SB_DQ_6
SB_DQ_7
SB_DQ_8
SB_DQ_9
SB_DQ_10
SB_DQ_11
SB_DQ_12
SB_DQ_13
SB_DQ_14
SB_DQ_15
SB_DQ_16
SB_DQ_17
SB_DQ_18
SB_DQ_19
SB_DQ_20
SB_DQ_21
SB_DQ_22
SB_DQ_23
SB_DQ_24
SB_DQ_25
SB_DQ_26
SB_DQ_27
SB_DQ_28
SB_DQ_29
SB_DQ_30
SB_DQ_31
SB_DQ_32
SB_DQ_33
SB_DQ_34
SB_DQ_35
SB_DQ_36
SB_DQ_37
SB_DQ_38
SB_DQ_39
SB_DQ_40
SB_DQ_41
SB_DQ_42
SB_DQ_43
SB_DQ_44
SB_DQ_45
SB_DQ_46
SB_DQ_47
SB_DQ_48
SB_DQ_49
SB_DQ_50
SB_DQ_51
SB_DQ_52
SB_DQ_53
SB_DQ_54
SB_DQ_55
SB_DQ_56
SB_DQ_57
SB_DQ_58
SB_DQ_59
SB_DQ_60
SB_DQ_61
SB_DQ_62
SB_DQ_63
CRESTLINE_1p0
PM@
DDRB_SDQ[0..63]
DDRB_SDM[0..7]
DDRB_SMA[0..13]
AY17
SB_BS_0
BG18
SB_BS_1
BG36
SB_BS_2
BE17
SB_CAS#
SB_DM_0
SB_DM_1
SB_DM_2
SB_DM_3
SB_DM_4
SB_DM_5
SB_DM_6
SB_DM_7
SB_DQS_0
SB_DQS_1
SB_DQS_2
SB_DQS_3
SB_DQS_4
SB_DQS_5
SB_DQS_6
SB_DQS_7
SB_DQS#_0
SB_DQS#_1
SB_DQS#_2
SB_DQS#_3
SB_DQS#_4
SB_DQS#_5
SB_DQS#_6
SB_DQS#_7
SB_MA_0
SB_MA_1
SB_MA_2
SB_MA_3
SB_MA_4
SB_MA_5
SB_MA_6
SB_MA_7
SB_MA_8
SB_MA_9
SB_MA_10
SB_MA_11
SB_MA_12
SB_MA_13
SB_RAS#
SB_RCVEN#
SB_WE#
DDR SYSTEM MEMORY B
AR50
BD49
BK45
BL39
BH12
BJ7
BF3
AW2
AT50
BD50
BK46
BK39
BJ12
BL7
BE2
AV2
AU50
BC50
BL45
BK38
BK12
BK7
BF2
AV3
BC18
BG28
BG25
AW17
BF25
BE25
BA29
BC28
AY28
BD37
BG17
BE37
BA39
BG13
AV16
AY18
BC17
DDRB_SDM0
DDRB_SDM1
DDRB_SDM2
DDRB_SDM3
DDRB_SDM4
DDRB_SDM5
DDRB_SDM6
DDRB_SDM7
DDRB_SDQS0
DDRB_SDQS1
DDRB_SDQS2
DDRB_SDQS3
DDRB_SDQS4
DDRB_SDQS5
DDRB_SDQS6
DDRB_SDQS7
DDRB_SDQS0#
DDRB_SDQS1#
DDRB_SDQS2#
DDRB_SDQS3#
DDRB_SDQS4#
DDRB_SDQS5#
DDRB_SDQS6#
DDRB_SDQS7#
DDRB_SMA0
DDRB_SMA1
DDRB_SMA2
DDRB_SMA3
DDRB_SMA4
DDRB_SMA5
DDRB_SMA6
DDRB_SMA7
DDRB_SMA8
DDRB_SMA9
DDRB_SMA10
DDRB_SMA11
DDRB_SMA12
DDRB_SMA13
SB_RCVEN#
DDRB_SBS0 <15>
DDRB_SBS1 <15>
DDRB_SBS2 <15>
DDRB_SCAS# <15>
DDRB_SDQS0 <15>
DDRB_SDQS1 <15>
DDRB_SDQS2 <15>
DDRB_SDQS3 <15>
DDRB_SDQS4 <15>
DDRB_SDQS5 <15>
DDRB_SDQS6 <15>
DDRB_SDQS7 <15>
DDRB_SDQS0# <15>
DDRB_SDQS1# <15>
DDRB_SDQS2# <15>
DDRB_SDQS3# <15>
DDRB_SDQS4# <15>
DDRB_SDQS5# <15>
DDRB_SDQS6# <15>
DDRB_SDQS7# <15>
DDRB_SRAS# <15>
PAD
T16
DDRB_SWE# <15>
A A
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2006/08/18 2007/8/18
3
Compal Secret Data
Deciphered Date
Title
Size Document Number Rev
B
2
Date: Sheet of
Compal Electronics, Inc.
Crestline ( 3/7)- DDRII
LA-3691P
0.2
945Thursday, March 08, 2007
1
Page 10
5
CRB 2.37K_1% to GND
D D
C C
GMCH_CRT_B<19>
GMCH_CRT_G<19>
GMCH_CRT_R<19>
R140
0_0402_5%
PM@
R143
150_0402_5%
Change to 0Ohm when use PM chip
R147 150_0402_1%GM@
R152 150_0402_1%GM@
R140 150_0402_1%GM@
1 2
R85 39_0402_1%GM@
1 2
R88 39_0402_1%GM@
LCTLB_DATA
LCTLA_CLK
TV_DCONSEL_0
TV_DCONSEL_1
R147
0_0402_5%
PM@
B B
CRB 2.2K , Follow!
+3VS
R152
0_0402_5%
PM@
GMCH_CRT_HSYNC<19>
GMCH_CRT_VSYNC<19>
R131 10K_0402_5%
1 2
R130 10K_0402_5%
1 2
R108 2.2K_0402_5%
R109 2.2K_0402_5%
GMCH_ENBKL<18>
LVDS_SCL<18>
LVDS_SDA<18>
GMCH_ENVDD<18> PCIE_MTX_C_GRX_N[0..15] <17>
1 2
R150 2.4K_0402_1%
LVDS_ACLK#<18>
LVDS_ACLK<18>
LVDS_BCLK#<18>
LVDS_BCLK<18>
LVDS_A0#<18>
LVDS_A1#<18>
LVDS_A2#<18>
LVDS_A0<18>
LVDS_A1<18>
LVDS_A2<18>
LVDS_B0#<18>
LVDS_B1#<18>
LVDS_B2#<18>
LVDS_B0<18>
LVDS_B1<18>
LVDS_B2<18>
R153
R148
150_0402_5%
1 2
1 2
1 2
150_0402_5%
12
12
12
GMCH_CRT_CLK<19>
GMCH_CRT_DATA<19>
R86
0_0402_5%
PM@
R87
0_0402_5%
PM@
4
LBKLT_EN
LCTLA_CLK
LCTLB_DATA
LVDS_IBG
LVDS_ACLK#
LVDS_ACLK
LVDS_BCLK#
LVDS_BCLK
LVDS_A0#
LVDS_A1#
LVDS_A2#
LVDS_A0
LVDS_A1
LVDS_A2
LVDS_B0#
LVDS_B1#
LVDS_B2#
LVDS_B0
LVDS_B1
LVDS_B2
GMCH_TV_COMPS
GMCH_TV_LUMA
GMCH_TV_CRMA
TV_DCONSEL_0
TV_DCONSEL_1
GMCH_CRT_CLK
GMCH_CRT_DATA
CRT_IREF
R110
1.3K_0402_1%
1 2
U20C
J40
L_BKLT_CTRL
H39
L_BKLT_EN
E39
L_CTRL_CLK
E40
L_CTRL_DATA
C37
L_DDC_CLK
D35
L_DDC_DATA
K40
L_VDD_EN
L41
LVDS_IBG
L43
LVDS_VBG
N41
LVDS_VREFH
N40
LVDS_VREFL
D46
LVDSA_CLK#
C45
LVDSA_CLK
D44
LVDSB_CLK#
E42
LVDSB_CLK
G51
LVDSA_DATA#_0
E51
LVDSA_DATA#_1
F49
LVDSA_DATA#_2
G50
LVDSA_DATA_0
E50
LVDSA_DATA_1
F48
LVDSA_DATA_2
G44
LVDSB_DATA#_0
B47
LVDSB_DATA#_1
B45
LVDSB_DATA#_2
E44
LVDSB_DATA_0
A47
LVDSB_DATA_1
A45
LVDSB_DATA_2
E27
TVA_DAC
G27
TVB_DAC
K27
TVC_DAC
F27
TVA_RTN
J27
TVB_RTN
L27
TVC_RTN
M35
TV_DCONSEL_0
P33
TV_DCONSEL_1
H32
CRT_BLUE
G32
CRT_BLUE#
K29
CRT_GREEN
J29
CRT_GREEN#
F29
CRT_RED
E29
CRT_RED#
K33
CRT_DDC_CLK
G35
CRT_DDC_DATA
F33
CRT_HSYNC
C32
CRT_TVO_IREF
E33
CRT_VSYNC
CRESTLINE_1p0
PM@
LVDS
TV VGA
PCI-EXPRESS GRAPHICS
3
PEG_COMPI
PEG_COMPO
PEG_RX#_0
PEG_RX#_1
PEG_RX#_2
PEG_RX#_3
PEG_RX#_4
PEG_RX#_5
PEG_RX#_6
PEG_RX#_7
PEG_RX#_8
PEG_RX#_9
PEG_RX#_10
PEG_RX#_11
PEG_RX#_12
PEG_RX#_13
PEG_RX#_14
PEG_RX#_15
PEG_RX_0
PEG_RX_1
PEG_RX_2
PEG_RX_3
PEG_RX_4
PEG_RX_5
PEG_RX_6
PEG_RX_7
PEG_RX_8
PEG_RX_9
PEG_RX_10
PEG_RX_11
PEG_RX_12
PEG_RX_13
PEG_RX_14
PEG_RX_15
PEG_TX#_0
PEG_TX#_1
PEG_TX#_2
PEG_TX#_3
PEG_TX#_4
PEG_TX#_5
PEG_TX#_6
PEG_TX#_7
PEG_TX#_8
PEG_TX#_9
PEG_TX#_10
PEG_TX#_11
PEG_TX#_12
PEG_TX#_13
PEG_TX#_14
PEG_TX#_15
PEG_TX_0
PEG_TX_1
PEG_TX_2
PEG_TX_3
PEG_TX_4
PEG_TX_5
PEG_TX_6
PEG_TX_7
PEG_TX_8
PEG_TX_9
PEG_TX_10
PEG_TX_11
PEG_TX_12
PEG_TX_13
PEG_TX_14
PEG_TX_15
2
PEG_COMP
N43
M43
J51
L51
N47
T45
T50
U40
Y44
Y40
AB51
W49
AD44
AD40
AG46
AH49
AG45
AG41
J50
L50
M47
U44
T49
T41
W45
W41
AB50
Y48
AC45
AC41
AH47
AG49
AH45
AG42
N45
U39
U47
N51
R50
T42
Y43
W46
W38
AD39
AC46
AC49
AC42
AH39
AE49
AH44
M45
T38
T46
N50
R51
U43
W42
Y47
Y39
AC38
AD47
AC50
AD43
AG39
AE50
AH43
20/25mils
PCIE_GTX_C_MRX_N0
PCIE_GTX_C_MRX_N1
PCIE_GTX_C_MRX_N2
PCIE_GTX_C_MRX_N3
PCIE_GTX_C_MRX_N4
PCIE_GTX_C_MRX_N5
PCIE_GTX_C_MRX_N6
PCIE_GTX_C_MRX_N7
PCIE_GTX_C_MRX_N8
PCIE_GTX_C_MRX_N9
PCIE_GTX_C_MRX_N10
PCIE_GTX_C_MRX_N11
PCIE_GTX_C_MRX_N12
PCIE_GTX_C_MRX_N13
PCIE_GTX_C_MRX_N14
PCIE_GTX_C_MRX_N15
PCIE_GTX_C_MRX_P0
PCIE_GTX_C_MRX_P1
PCIE_GTX_C_MRX_P2
PCIE_GTX_C_MRX_P3
PCIE_GTX_C_MRX_P4
PCIE_GTX_C_MRX_P5
PCIE_GTX_C_MRX_P6
PCIE_GTX_C_MRX_P7
PCIE_GTX_C_MRX_P8
PCIE_GTX_C_MRX_P9
PCIE_GTX_C_MRX_P10
PCIE_GTX_C_MRX_P11
PCIE_GTX_C_MRX_P12
PCIE_GTX_C_MRX_P13
PCIE_GTX_C_MRX_P14
PCIE_GTX_C_MRX_P15
PCIE_MTX_GRX_N0
PCIE_MTX_GRX_N1
PCIE_MTX_GRX_N2
PCIE_MTX_GRX_N3
PCIE_MTX_GRX_N4 PCIE_MTX_C_GRX_N4
PCIE_MTX_GRX_N5
PCIE_MTX_GRX_N6
PCIE_MTX_GRX_N7
PCIE_MTX_GRX_N8
PCIE_MTX_GRX_N9
PCIE_MTX_GRX_N10
PCIE_MTX_GRX_N11
PCIE_MTX_GRX_N12
PCIE_MTX_GRX_N13
PCIE_MTX_GRX_N14
PCIE_MTX_GRX_N15
PCIE_MTX_GRX_P0
PCIE_MTX_GRX_P1
PCIE_MTX_GRX_P2
PCIE_MTX_GRX_P3
PCIE_MTX_GRX_P4
PCIE_MTX_GRX_P5
PCIE_MTX_GRX_P6
PCIE_MTX_GRX_P7
PCIE_MTX_GRX_P8
PCIE_MTX_GRX_P9
PCIE_MTX_GRX_P10
PCIE_MTX_GRX_P11
PCIE_MTX_GRX_P12
PCIE_MTX_GRX_P13
PCIE_MTX_GRX_P14
PCIE_MTX_GRX_P15
1 2
R154 24.9_0402_1%
C396 0.1U_0402_10V7KPM@
1 2
C400 0.1U_0402_10V7KPM@
1 2
C410 0.1U_0402_10V7KPM@
1 2
C422 0.1U_0402_10V7KPM@
1 2
C425 0.1U_0402_10V7KPM@
1 2
C430 0.1U_0402_10V7KPM@
1 2
C432 0.1U_0402_10V7KPM@
1 2
C442 0.1U_0402_10V7KPM@
1 2
C394 0.1U_0402_10V7KPM@
1 2
C397 0.1U_0402_10V7KPM@
1 2
C402 0.1U_0402_10V7KPM@
1 2
C417 0.1U_0402_10V7KPM@
1 2
C424 0.1U_0402_10V7KPM@
1 2
C427 0.1U_0402_10V7KPM@
1 2
C431 0.1U_0402_10V7KPM@
1 2
C438 0.1U_0402_10V7KPM@
1 2
+VCCP
PCIE_MTX_C_GRX_N[0..15]
PCIE_MTX_C_GRX_P[0..15]
PCIE_GTX_C_MRX_N[0..15]
PCIE_GTX_C_MRX_P[0..15]
C124 0.1U_0402_10V7KPM@
1 2
C130 0.1U_0402_10V7KPM@
1 2
C140 0.1U_0402_10V7KPM@
1 2
C145 0.1U_0402_10V7KPM@
1 2
C153 0.1U_0402_10V7KPM@
1 2
C157 0.1U_0402_10V7KPM@
1 2
C165 0.1U_0402_10V7KPM@
1 2
C171 0.1U_0402_10V7KPM@
1 2
C121 0.1U_0402_10V7KPM@
1 2
C126 0.1U_0402_10V7KPM@
1 2
C134 0.1U_0402_10V7KPM@
1 2
C143 0.1U_0402_10V7KPM@
1 2
C148 0.1U_0402_10V7KPM@
1 2
C154 0.1U_0402_10V7KPM@
1 2
C163 0.1U_0402_10V7KPM@
1 2
C168 0.1U_0402_10V7KPM@
1 2
PCIE_MTX_C_GRX_N0
PCIE_MTX_C_GRX_N1
PCIE_MTX_C_GRX_N2
PCIE_MTX_C_GRX_N3
PCIE_MTX_C_GRX_N5
PCIE_MTX_C_GRX_N6
PCIE_MTX_C_GRX_N7
PCIE_MTX_C_GRX_N8
PCIE_MTX_C_GRX_N9
PCIE_MTX_C_GRX_N10
PCIE_MTX_C_GRX_N11
PCIE_MTX_C_GRX_N12
PCIE_MTX_C_GRX_N13
PCIE_MTX_C_GRX_N14
PCIE_MTX_C_GRX_N15
PCIE_MTX_C_GRX_P0
PCIE_MTX_C_GRX_P1
PCIE_MTX_C_GRX_P2
PCIE_MTX_C_GRX_P3
PCIE_MTX_C_GRX_P4
PCIE_MTX_C_GRX_P5
PCIE_MTX_C_GRX_P6
PCIE_MTX_C_GRX_P7
PCIE_MTX_C_GRX_P8
PCIE_MTX_C_GRX_P9
PCIE_MTX_C_GRX_P10
PCIE_MTX_C_GRX_P11
PCIE_MTX_C_GRX_P12
PCIE_MTX_C_GRX_P13
PCIE_MTX_C_GRX_P14
PCIE_MTX_C_GRX_P15
1
PCIE_MTX_C_GRX_P[0..15] <17>
PCIE_GTX_C_MRX_N[0..15] <17>
PCIE_GTX_C_MRX_P[0..15] <17>
A A
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2006/08/18 2007/8/18
3
Compal Secret Data
Deciphered Date
Title
Size Document Number Rev
B
2
Date: Sheet
Compal Electronics, Inc.
Crestline (4/7)-VGA/LVDS/TV
LA-3691P
10 45Thursday, March 08, 2007
1
0.2
of
Page 11
5
U20G
+VCCP
D D
Replace 0 Ohm
by directly
connection
C C
B B
A A
+1.8V
+VCC_AXG
AT35
AT34
AH28
AC32
AC31
AK32
AJ31
AJ28
AH32
AH31
AH29
AF32
R30
AU32
AU33
AU35
AV33
AW33
AW35
AY35
BA32
BA33
BA35
BB33
BC32
BC33
BC35
BD32
BD35
BE32
BE33
BE35
BF33
BF34
BG32
BG33
BG35
BH32
BH34
BH35
BJ32
BJ33
BJ34
BK32
BK33
BK34
BK35
BL33
AU30
R20
T14
W13
W14
Y12
AA20
AA23
AA26
AA28
AB21
AB24
AB29
AC20
AC21
AC23
AC24
AC26
AC28
AC29
AD20
AD23
AD24
AD28
AF21
AF26
AA31
AH20
AH21
AH23
AH24
AH26
AD31
AJ20
AN14
VCC_1
VCC_2
VCC_3
VCC_5
VCC_4
VCC_6
VCC_7
VCC_8
VCC_9
VCC_10
VCC_11
VCC_12
VCC_13
VCC_SM_1
VCC_SM_2
VCC_SM_3
VCC_SM_4
VCC_SM_5
VCC_SM_6
VCC_SM_7
VCC_SM_8
VCC_SM_9
VCC_SM_10
VCC_SM_11
VCC_SM_12
VCC_SM_13
VCC_SM_14
VCC_SM_15
VCC_SM_16
VCC_SM_17
VCC_SM_18
VCC_SM_19
VCC_SM_20
VCC_SM_21
VCC_SM_22
VCC_SM_23
VCC_SM_24
VCC_SM_25
VCC_SM_26
VCC_SM_27
VCC_SM_28
VCC_SM_29
VCC_SM_30
VCC_SM_31
VCC_SM_32
VCC_SM_33
VCC_SM_34
VCC_SM_35
VCC_SM_36
VCC_AXG_1
VCC_AXG_2
VCC_AXG_3
VCC_AXG_4
VCC_AXG_5
VCC_AXG_6
VCC_AXG_7
VCC_AXG_8
VCC_AXG_9
VCC_AXG_10
VCC_AXG_11
VCC_AXG_12
VCC_AXG_13
VCC_AXG_14
VCC_AXG_15
VCC_AXG_16
VCC_AXG_17
VCC_AXG_18
VCC_AXG_19
VCC_AXG_20
VCC_AXG_21
VCC_AXG_22
VCC_AXG_23
VCC_AXG_24
VCC_AXG_25
VCC_AXG_26
VCC_AXG_27
VCC_AXG_28
VCC_AXG_29
VCC_AXG_30
VCC_AXG_31
VCC_AXG_32
VCC_AXG_33
VCC_AXG_34
VCC CORE
POWER
VCC SMVCC GFX
VCC_AXG_NCTF_1
VCC_AXG_NCTF_2
VCC_AXG_NCTF_3
VCC_AXG_NCTF_4
VCC_AXG_NCTF_5
VCC_AXG_NCTF_6
VCC_AXG_NCTF_7
VCC_AXG_NCTF_8
VCC_AXG_NCTF_9
VCC_AXG_NCTF_10
VCC_AXG_NCTF_11
VCC_AXG_NCTF_12
VCC_AXG_NCTF_13
VCC_AXG_NCTF_14
VCC_AXG_NCTF_15
VCC_AXG_NCTF_16
VCC_AXG_NCTF_17
VCC_AXG_NCTF_18
VCC_AXG_NCTF_19
VCC_AXG_NCTF_20
VCC_AXG_NCTF_21
VCC_AXG_NCTF_22
VCC_AXG_NCTF_23
VCC_AXG_NCTF_24
VCC_AXG_NCTF_25
VCC_AXG_NCTF_26
VCC_AXG_NCTF_27
VCC_AXG_NCTF_28
VCC_AXG_NCTF_29
VCC_AXG_NCTF_30
VCC_AXG_NCTF_31
VCC_AXG_NCTF_32
VCC_AXG_NCTF_33
VCC_AXG_NCTF_34
VCC_AXG_NCTF_35
VCC_AXG_NCTF_36
VCC_AXG_NCTF_37
VCC_AXG_NCTF_38
VCC_AXG_NCTF_39
VCC_AXG_NCTF_40
VCC_AXG_NCTF_41
VCC_AXG_NCTF_42
VCC_AXG_NCTF_43
VCC_AXG_NCTF_44
VCC_AXG_NCTF_45
VCC_AXG_NCTF_46
VCC_AXG_NCTF_47
VCC_AXG_NCTF_48
VCC_AXG_NCTF_49
VCC_AXG_NCTF_50
VCC_AXG_NCTF_51
VCC_AXG_NCTF_52
VCC_AXG_NCTF_53
VCC_AXG_NCTF_54
VCC GFX NCTF
VCC_AXG_NCTF_55
VCC_AXG_NCTF_56
VCC_AXG_NCTF_57
VCC_AXG_NCTF_58
VCC_AXG_NCTF_59
VCC_AXG_NCTF_60
VCC_AXG_NCTF_61
VCC_AXG_NCTF_62
VCC_AXG_NCTF_63
VCC_AXG_NCTF_64
VCC_AXG_NCTF_65
VCC_AXG_NCTF_66
VCC_AXG_NCTF_67
VCC_AXG_NCTF_68
VCC_AXG_NCTF_69
VCC_AXG_NCTF_70
VCC_AXG_NCTF_71
VCC_AXG_NCTF_72
VCC_AXG_NCTF_73
VCC_AXG_NCTF_74
VCC_AXG_NCTF_75
VCC_AXG_NCTF_76
VCC_AXG_NCTF_77
VCC_AXG_NCTF_78
VCC_AXG_NCTF_79
VCC_AXG_NCTF_80
VCC_AXG_NCTF_81
VCC_AXG_NCTF_82
VCC_AXG_NCTF_83
VCC SM LF
VCC_SM_LF1
VCC_SM_LF2
VCC_SM_LF3
VCC_SM_LF4
VCC_SM_LF5
VCC_SM_LF6
VCC_SM_LF7
4
9/18 modify from +1.05VS to +VCC_AXG
T17
T18
T19
T21
T22
T23
T25
U15
U16
U17
U19
U20
U21
U23
U26
V16
V17
V19
V20
V21
V23
V24
Y15
Y16
Y17
Y19
Y20
Y21
Y23
Y24
Y26
Y28
Y29
AA16
AA17
AB16
AB19
AC16
AC17
AC19
AD15
AD16
AD17
AF16
AF19
AH15
AH16
AH17
AH19
AJ16
AJ17
AJ19
AK16
AK19
AL16
AL17
AL19
AL20
AL21
AL23
AM15
AM16
AM19
AM20
AM21
AM23
AP15
AP16
AP17
AP19
AP20
AP21
AP23
AP24
AR20
AR21
AR23
AR24
AR26
V26
V28
V29
Y31
AW45
BC39
BE39
BD17
BD4
AW8
AT6
+VCC_AXG
VCC: 1573mA
+VCCP
(220UF*1, 22UF*1, 0.22UF*2, 0.1UF*1)
1
+
C408
220U_D2_4VMR15
2
@
C474
330U_D2E_2.5VM
10U_0805_10V4Z
VCC_SM: 3300mA
+1.8V
(330UF*1, 22UF*2, 0.1UF*1)
1
+
2
10U_0805_10V4Z
9/18 modify from +1.05VS to +VCC_AXG 9/18 Add for 965PM use
VCC_AXG: 7700mA
(330UF*2, 22UF*1, 10UF*1, 1U*1, 0.47U*1, 0.1UF*2)
1
C434
+
2
330U_D2E_2.5VM
+VCCP
1
C158
0.22U_0603_16V7K
2
0.1U_0402_16V4Z
VCCSM_LF1
VCCSM_LF2
VCCSM_LF3
VCCSM_LF4
VCCSM_LF5
VCCSM_LF6
VCCSM_LF7
C152
0.1U_0402_16V4Z
+VCC_AXG
C433
330U_D2E_2.5VM
GM@
1
2
3
CRB 270uF , there is no 270u part.
9/19 change to 330u, 9/29 change to 220u
1
C118
0.22U_0603_16V7K
2
1
C164
2
1
+
2
@
C114
0.22U_0603_16V7K
1
C177
10U_0805_10V4Z
2
4.7U_0805_10V4Z
C115
1
10U_0805_10V4Z
2
GM@
1
C147
22U_0805_6.3V6M
2
0.22U_0603_16V7K
C112
1
2
GM@
10U_0805_10V4Z
VCC_AXM: 540mA
(22UF*2, 0.22UF *2, 0.1UF*2)
C139
1
C122
0.1U_0402_16V4Z
2
C181
1U_0603_10V4Z
C141
1U_0603_10V4Z
GM@
C146
0.22U_0603_16V7K
C128
C156
0.47U_0603_16V4Z
0.1U_0402_16V4Z
9/29 +1.05VS_AXM change to +1.05VS
J6
1 2
C173
PAD-OPEN 3x3m
@
J2
1 2
PAD-OPEN 3x3m
@
C175
0.47U_0603_16V4Z
C166
1U_0603_10V4Z
+VCCP +VCC_AXG
C172
0.22U_0603_16V7K
Follow DG 1.1
9/14 add for reservation
0.1U_0402_16V4Z@
C136
GM@
C138
1
2
1
2
C170
C127
1
0.1U_0402_16V4Z
2
GM@
1
C137
0.1U_0402_16V4Z
2
C183
1U_0603_10V4Z
@
C119
GM@
0.1U_0402_16V4Z
C150
0.1U_0402_16V4Z
1005 This is for GM@
Remember open stencil at GM@
C159
1U_0603_10V4Z
2
U20F
+VCCP
1
2
1
2
R159
0_0805_5%
PM@
+VCCP
AB33
VCC_NCTF_1
AB36
VCC_NCTF_2
AB37
VCC_NCTF_3
AC33
VCC_NCTF_4
AC35
VCC_NCTF_5
AC36
VCC_NCTF_6
AD35
VCC_NCTF_7
AD36
VCC_NCTF_8
AF33
VCC_NCTF_9
AF36
VCC_NCTF_10
AH33
VCC_NCTF_11
AH35
VCC_NCTF_12
AH36
VCC_NCTF_13
AH37
VCC_NCTF_14
AJ33
VCC_NCTF_15
AJ35
VCC_NCTF_16
AK33
VCC_NCTF_17
AK35
VCC_NCTF_18
AK36
VCC_NCTF_19
AK37
VCC_NCTF_20
AD33
VCC_NCTF_21
AJ36
VCC_NCTF_22
AM35
VCC_NCTF_23
AL33
VCC_NCTF_24
AL35
VCC_NCTF_25
AA33
VCC_NCTF_26
AA35
VCC_NCTF_27
AA36
VCC_NCTF_28
AP35
VCC_NCTF_29
AP36
VCC_NCTF_30
AR35
VCC_NCTF_31
AR36
VCC_NCTF_32
Y32
VCC_NCTF_33
Y33
VCC_NCTF_34
Y35
VCC_NCTF_35
Y36
VCC_NCTF_36
Y37
VCC_NCTF_37
T30
VCC_NCTF_38
T34
VCC_NCTF_39
T35
VCC_NCTF_40
U29
VCC_NCTF_41
U31
VCC_NCTF_42
U32
VCC_NCTF_43
U33
VCC_NCTF_44
U35
VCC_NCTF_45
U36
VCC_NCTF_46
V32
VCC_NCTF_47
V33
VCC_NCTF_48
V36
VCC_NCTF_49
V37
VCC_NCTF_50
AL24
VCC_AXM_NCTF_1
AL26
VCC_AXM_NCTF_2
AL28
VCC_AXM_NCTF_3
AM26
VCC_AXM_NCTF_4
AM28
VCC_AXM_NCTF_5
AM29
VCC_AXM_NCTF_6
AM31
VCC_AXM_NCTF_7
AM32
VCC_AXM_NCTF_8
AM33
VCC_AXM_NCTF_9
AP29
VCC_AXM_NCTF_10
AP31
VCC_AXM_NCTF_11
AP32
VCC_AXM_NCTF_12
AP33
VCC_AXM_NCTF_13
AL29
VCC_AXM_NCTF_14
AL31
VCC_AXM_NCTF_15
AL32
VCC_AXM_NCTF_16
AR31
VCC_AXM_NCTF_17
AR32
VCC_AXM_NCTF_18
AR33
VCC_AXM_NCTF_19
CRESTLINE_1p0
PM@
VSS NCTF
VCC NCTF
POWER
VCC AXM NCTF
VSS_NCTF_1
VSS_NCTF_2
VSS_NCTF_3
VSS_NCTF_4
VSS_NCTF_5
VSS_NCTF_6
VSS_NCTF_7
VSS_NCTF_8
VSS_NCTF_9
VSS_NCTF_10
VSS_NCTF_11
VSS_NCTF_12
VSS_NCTF_13
VSS_NCTF_14
VSS_NCTF_15
VSS_NCTF_16
VSS_NCTF_17
VSS_NCTF_18
VSS_NCTF_19
VSS_NCTF_20
VSS_NCTF_21
VSS_SCB1
VSS_SCB2
VSS_SCB3
VSS_SCB4
VSS_SCB5
VSS_SCB6
VSS SCBVCC AXM
VCC_AXM_1
VCC_AXM_2
VCC_AXM_3
VCC_AXM_4
VCC_AXM_5
VCC_AXM_6
VCC_AXM_7
1
T27
T37
U24
U28
V31
V35
AA19
AB17
AB35
AD19
AD37
AF17
AF35
AK17
AM17
AM24
AP26
AP28
AR15
AR19
AR28
A3
B2
C1
BL1
BL51
A51
AT33
AT31
AK29
AK24
AK23
AJ26
AJ23
+VCCP
9/29
+1.05VS_AXM
change to
+1.05VS
CRESTLINE_1p0
PM@
9/18 modify from +1.05VS to +VCC_AXG
5
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SE CRET INFO RMATI ON. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2006/08/18 2007/8/18
3
Compal Secret Data
Deciphered Date
Title
Size Document Number Rev
B
2
Date: Sheet
Compal Electronics, Inc.
Crestline (5/7)-VCC
LA-3691P
11 45Thursday, March 08, 2007
1
0.2
of
Page 12
5
VCCA_HPLL: 50mA
(22UF*1, 0.1UF*1)
L26
+1.25VS
D D
C C
VCC_SYNC: 10mA (0.1UF*1)
+3VS
1 2
MBK1608121YZF_0603
10U_0805_10V4Z
VCCA_MPLL:150mA
(10UF*1, 0.1UF*1)
L25
1 2
MBK1608121YZF_0603
10U_0805_10V4Z
1 2
R119 0_0603_5%
GM@
0.1U_0402_16V4Z
C421
R327
0.5_0603_1%
C404
C102
GM@
VCCA_CRT_DAC: 80mA (0.1UF*1, 0.022UF*1)
L9
+3VS
B B
+3VS
+3VS
A A
1 2
MBK1608121YZF_0603
GM@
R89
22u_0805
GM@
VCCA_DAC_BG: 5mA (0.1UF*1, 0.022UF*1)
L13
1 2
MBK1608121YZF_0603
GM@
R106
22u_0805
GM@
L19
1 2
MBK1608121YZF_0603
GM@
L11
+1.5VS
1 2
MBK1608121YZF_0603
22U_0805_10V4Z
C352
GM@
0.1U_0402_16V4Z
C350
0.1U_0402_16V4Z
GM@
VCCA_TV_DAC: 40mA each DAC (0.1UF*1, 0.022UF*1 for each DAC)
1
C335
2
22U_0805_10V4Z
GM@
+1.5VS_TVDAC
1
C87
2
PM@
5
1
2
1
2
+3VS_SYNC
1
R136
0_0402_5%
2
PM@
1
C351
GM@
2
1
C88
2
GM@
1
C348
GM@
0.1U_0402_16V4Z
2
+1.25VS_HPLL
1
C418
0.1U_0402_16V4Z
2
+1.25VS_MPLL
1
C403
0.1U_0402_16V4Z
2
+1.25VS
+3VS_CRTDAC
0.022U_0402_16V7K
+3VS_DACBG
0.022U_0402_16V7K
C344
C349
GM@
0.1U_0402_16V4Z
0.022U_0402_16V7K
GM@
+1.5VS
R127
22u_0805
GM@
+1.25VS
+1.25VS
R89
0_0805_5%
PM@
R106
0_0805_5%
PM@
VCCA_DPLLA/B: 100mA
(470UF*1, 0.1UF*1)
L20
1 2
10U_FLC-453232-100K_0.25A_10%
220U_D2_4VMR15
VCCA_DPLLA/B: 100mA
(470UF*1, 0.1UF*1)
L22
1 2
10U_FLC-453232-100K_0.25A_10%
220U_D2_4VMR15
0.1U_0402_16V4Z
+1.25VS
12
C387
10U_0805_10V4Z
R190 0_0603_5%
1
C345
2
0.022U_0402_16V7K
GM@
L14
1 2
MBK1608121YZF_0603
GM@
R302 1_0603_5%
1 2
R189 0_0805_5%
22U_0805_6.3V6M
+1.5VS_TVDAC
0.1U_0402_16V4Z
VCCA_PEG_PLL: 100mA
(0.1UF*1)
C337
GM@
0.1U_0402_16V4Z
VCCD_QDAC: 5mA
(0.1UF*1, 0.022UF*1)
C110
0.1U_0402_16V4Z
GM@
4
+1.25VS_DPLLA
1
+
C357
0.1U_0402_16V4Z
2
1
+
C378
0.1U_0402_16V4Z
2
+1.8V_TX_LVDS
+3VS
L24
1 2
MBK1608121YZF_0603
C182
22U_0805_6.3V6M
@
+1.25VS_A_SM_CK
C188
VCCD_TVDAC / CRT: each 60mA (0.1UF*1, 0.022UF*1)
C105
1
C338
2
0.022U_0402_16V7K
GM@
1
2
C90
1000P_0402_50V7K
GM@
1
C106
2
+1.25VS_A_PEGPLL
0.1U_0402_16V4Z
+1.25VS_A_SM
1
C180
2
22U_0805_6.3V6M
VCCA_SM_CK: 35mA
(22UF*1, 1UF*2, 0.1UF*1)
1
C178
2
@
1U_0603_10V4Z
R115 0_0402_5%
1
C93
2
0.022U_0402_16V7K
VCCD_HPLL: 250mA (0.1UF*1)
+1.25VS
C149
0.1U_0402_16V4Z
+3VS_A_TVDAC
C109
0.022U_0402_16V7K
GM@
4
1
C95
2
+3VS_SYNC
+1.25VS_DPLLB
C103
1
2
VCCA_PEG_BG: 5mA
(0.1UF*1)
C385
VCCA_SM: 640mA
(22UF*21, 4.7UF*1, 1UF*1)
1
2
C186
1U_0603_10V4Z
+3VS_A_TVDAC
GM@
1
2
R134
0_0402_5%
PM@
+1.5VS_QDAC
+3VS_CRTDAC
+3VS_DACBG
1
2
+1.25VS_DPLLA
+1.25VS_DPLLB
+1.25VS_HPLL
+1.25VS_MPLL
VCCA_LVDS: 10mA
(0.1UF*1)
1
VCCA_PEG_PLL: 100mA
(0.1UF*1)
2
C187
4.7U_0805_10V4Z
@
R118
+1.8V
R127
PM@
0_0805_5%
C162
1U_0603_10V4Z
C167
0.1U_0402_16V4Z
0_0402_5%
PM@
+1.25VS_A_PEGPLL
C113
0.1U_0402_16V4Z
R120 0_0402_5%
10U_0805_10V4Z
1
2
VCCD_CRT
+1.5VS_TVDAC
+1.5VS_QDAC
1
2
GM@
C89
@
VCCD_LVDS: 150mA
(10UF*1, 0.1UF*1)
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
J32
A33
B33
A30
B32
B49
H49
AL2
AM2
A41
B41
K50
K49
U51
AW18
AV19
AU19
AU18
AU17
AT22
AT21
AT19
AT18
AT17
AR17
AR16
BC29
BB29
C25
B25
C27
B27
B28
A28
M32
L29
N28
AN2
U48
J41
H42
+1.8V_LVDS
1
C96
2
GM@
1U_0603_10V4Z
3
U20H
VCCSYNC
VCCA_CRT_DAC_1
VCCA_CRT_DAC_2
VCCA_DAC_BG
VSSA_DAC_BG
VCCA_DPLLA
VCCA_DPLLB
VCCA_HPLL
VCCA_MPLL
VCCA_LVDS
VSSA_LVDS
VCCA_PEG_BG
VSSA_PEG_BG
VCCA_PEG_PLL
VCCA_SM_1
VCCA_SM_2
VCCA_SM_3
VCCA_SM_4
VCCA_SM_5
VCCA_SM_7
VCCA_SM_8
VCCA_SM_9
VCCA_SM_10
VCCA_SM_11
VCCA_SM_NCTF_1
VCCA_SM_NCTF_2
VCCA_SM_CK_1
VCCA_SM_CK_2
VCCA_TVA_DAC_1
VCCA_TVA_DAC_2
VCCA_TVB_DAC_1
VCCA_TVB_DAC_2
VCCA_TVC_DAC_1
VCCA_TVC_DAC_2
VCCD_CRT
VCCD_TVDAC
VCCD_QDAC
VCCD_HPLL
VCCD_PEG_PLL
VCCD_LVDS_1
VCCD_LVDS_2
CRESTLINE_1p0
PM@
2006/08/18 2007/8/18
3
R129
0_0402_5%
PM@
CRTPLLA PEGA SMTV
POWER
A CK A LVDS
D TV/CRTLVDS
Compal Secret Data
VCC_AXD_1
VCC_AXD_2
VCC_AXD_3
VCC_AXD_4
VCC_AXD_5
AXD
VCC_AXD_6
VCC_AXD_NCTF
VCC_AXF_1
VCC_AXF_2
VCC_AXF_3
AXF
VCC_SM_CK_1
VCC_SM_CK_2
VCC_SM_CK_3
VCC_SM_CK_4
SM CK
VCC_TX_LVDS
HV
VCC_PEG_1
VCC_PEG_2
VCC_PEG_3
VCC_PEG_4
PEG
VCC_PEG_5
VCC_RXR_DMI_1
VCC_RXR_DMI_2
DMI
+VCCP +3VS
RB751V-40TE17_SOD323-2
Deciphered Date
VTT_1
VTT_2
VTT_3
VTT_4
VTT_5
VTT_6
VTT_7
VTT_8
VTT_9
VTT_10
VTT_11
VTT_12
VTT_13
VTT
VTT_14
VTT_15
VTT_16
VTT_17
VTT_18
VTT_19
VTT_20
VTT_21
VTT_22
VCC_DMI
VCC_HV_1
VCC_HV_2
VTTLF1
VTTLF2
VTTLF3
VTTLF
D9
U13
U12
U11
U9
U8
U7
U5
U3
U2
U1
T13
T11
T10
T9
T7
T6
T5
T3
T2
R3
R2
R1
AT23
AU28
AU24
AT29
AT25
AT30
AR29
B23
B21
A21
AJ50
BK24
BK23
BJ24
BJ23
A43
C40
B40
AD51
W50
W51
V49
V50
AH50
AH51
A7
F2
AH1
0.47U_0603_16V4Z
12
R156 10_0603_5%
2
+VCCP
1
+
C395
330U_D2E_2.5VM
2
+1.25VS_AXD
C155
1U_0603_10V4Z
+1.8V_TX_LVDS: 100mA
(220UF*1, 1000PF*1)
VCC_HV: 100mA
VTTLF_CAP1
VTTLF_CAP2
VTTLF_CAP3
1 2
C398
0.47U_0603_16V4Z
2
+3VS
220U_D2_4VMR15
GM@
C371
VTT: 850mA
(220UF*1, 4.7UF*21, 2.2UF*1, 0.47UF*1)
C390
4.7U_0805_10V4Z
VCC_AXD: 515mA
(22UF*1, 1UF*1)
+1.25VS_AXF
C343
10U_0805_10V4Z
0.1U_0402_16V4Z
22U_0805_6.3V6M
+1.8V_TX_LVDS
C336
C389
4.7U_0805_10V4Z
R188 0_0603_5%
1
C179
22U_0805_6.3V6M
2
VCC_AXF: 495mA
(10UF*1, 1UF*1)
1
2
1
C133
2
+1.8V_SM_CK
C466
1
1
+
C353
2
2
GM@
1000P_0402_50V7K
+VCCP_PEG
C393
220U_D2_4VMR15
C108
2.2U_0805_10V6K
R273 0_0603_5%
C346
1U_0603_10V4Z
VCC_DMI: 100mA (0.1UF*1)
+1.25VS
VCC_SM_CK: 2 00mA (22UF*1, 0.1UF*1)
1
2
1
C463
2
0.1U_0402_16V4Z
L12
1 2
MBK1608121YZF_0603
GM@
R105
0_0402_5%
PM@
+1.05VS_P E G : 1 2 6 0 mA (220UF*1, 10UF*1)
1
2
+
C120
10U_0805_10V4Z
1
2
+1.05VS_DMI: 100mA (220UF*1, 10UF*1)
C347
0.47U_0603_16V4Z
1
2
Title
Size Document Number Rev
B
Date: Sheet
+VCCP_PEG
C129
10U_0805_10V4Z
Compal Electronics, Inc.
LA-3691P
1
C111
0.47U_0603_16V4Z
+1.25VS
+1.25VS
1 2
L34
MBK1608121YZF_0603
R396
1_0603_5%
1 2
R162 0_0805_5%
C472
10U_0805_10V4Z
+1.8V
C98
0.1U_0402_16V4Z
1 2
+VCCP
+3VS
1
2
+1.8V
Close to VCC_HV (pin C40/B40)
Crestline (6/7)-VCC
12 45Thursday, March 08, 2007
1
0.2
of
Page 13
5
U20I
A13
VSS_1
A15
VSS_2
A17
VSS_3
A24
VSS_4
AA21
VSS_5
AA24
VSS_6
AA29
VSS_7
AB20
VSS_8
AB23
VSS_9
AB26
VSS_10
D D
C C
B B
A A
AB28
VSS_11
AB31
VSS_12
AC10
VSS_13
AC13
VSS_14
AC3
VSS_15
AC39
VSS_16
AC43
VSS_17
AC47
VSS_18
AD1
VSS_19
AD21
VSS_20
AD26
VSS_21
AD29
VSS_22
AD3
VSS_23
AD41
VSS_24
AD45
VSS_25
AD49
VSS_26
AD5
VSS_27
AD50
VSS_28
AD8
VSS_29
AE10
VSS_30
AE14
VSS_31
AE6
VSS_32
AF20
VSS_33
AF23
VSS_34
AF24
VSS_35
AF31
VSS_36
AG2
VSS_37
AG38
VSS_38
AG43
VSS_39
AG47
VSS_40
AG50
VSS_41
AH3
VSS_42
AH40
VSS_43
AH41
VSS_44
AH7
VSS_45
AH9
VSS_46
AJ11
VSS_47
AJ13
VSS_48
AJ21
VSS_49
AJ24
VSS_50
AJ29
VSS_51
AJ32
VSS_52
AJ43
VSS_53
AJ45
VSS_54
AJ49
VSS_55
AK20
VSS_56
AK21
VSS_57
AK26
VSS_58
AK28
VSS_59
AK31
VSS_60
AK51
VSS_61
AL1
VSS_62
AM11
VSS_63
AM13
VSS_64
AM3
VSS_65
AM4
VSS_66
AM41
VSS_67
AM45
VSS_68
AN1
VSS_69
AN38
VSS_70
AN39
VSS_71
AN43
VSS_72
AN5
VSS_73
AN7
VSS_74
AP4
VSS_75
AP48
VSS_76
AP50
VSS_77
AR11
VSS_78
AR2
VSS_79
AR39
VSS_80
AR44
VSS_81
AR47
VSS_82
AR7
VSS_83
AT10
VSS_84
AT14
VSS_85
AT41
VSS_86
AT49
VSS_87
AU1
VSS_88
AU23
VSS_89
AU29
VSS_90
AU3
VSS_91
AU36
VSS_92
AU49
VSS_93
AU51
VSS_94
AV39
VSS_95
AV48
VSS_96
AW1
VSS_97
AW12
VSS_98
AW16
VSS_99
CRESTLINE_1p0
PM@
5
VSS
VSS_100
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105
VSS_106
VSS_107
VSS_108
VSS_109
VSS_110
VSS_111
VSS_112
VSS_113
VSS_114
VSS_115
VSS_116
VSS_117
VSS_118
VSS_119
VSS_120
VSS_121
VSS_122
VSS_123
VSS_124
VSS_125
VSS_126
VSS_127
VSS_128
VSS_129
VSS_130
VSS_131
VSS_132
VSS_133
VSS_134
VSS_135
VSS_136
VSS_137
VSS_138
VSS_139
VSS_140
VSS_141
VSS_142
VSS_143
VSS_144
VSS_145
VSS_146
VSS_147
VSS_148
VSS_149
VSS_150
VSS_151
VSS_152
VSS_153
VSS_154
VSS_155
VSS_156
VSS_157
VSS_158
VSS_159
VSS_160
VSS_161
VSS_162
VSS_163
VSS_164
VSS_165
VSS_166
VSS_167
VSS_168
VSS_169
VSS_170
VSS_171
VSS_172
VSS_173
VSS_174
VSS_175
VSS_176
VSS_177
VSS_178
VSS_179
VSS_180
VSS_181
VSS_182
VSS_183
VSS_184
VSS_185
VSS_186
VSS_187
VSS_188
VSS_189
VSS_190
VSS_191
VSS_192
VSS_193
VSS_194
VSS_195
VSS_196
VSS_197
VSS_198
AW24
AW29
AW32
AW5
AW7
AY10
AY24
AY37
AY42
AY43
AY45
AY47
AY50
B10
B20
B24
B29
B30
B35
B38
B43
B46
B5
B8
BA1
BA17
BA18
BA2
BA24
BB12
BB25
BB40
BB44
BB49
BB8
BC16
BC24
BC25
BC36
BC40
BC51
BD13
BD2
BD28
BD45
BD48
BD5
BE1
BE19
BE23
BE30
BE42
BE51
BE8
BF12
BF16
BF36
BG19
BG2
BG24
BG29
BG39
BG48
BG5
BG51
BH17
BH30
BH44
BH46
BH8
BJ11
BJ13
BJ38
BJ4
BJ42
BJ46
BK15
BK17
BK25
BK29
BK36
BK40
BK44
BK6
BK8
BL11
BL13
BL19
BL22
BL37
BL47
C12
C16
C19
C28
C29
C33
C36
C41
4
U20J
C46
VSS_199
C50
VSS_200
C7
VSS_201
D13
VSS_202
D24
VSS_203
D3
VSS_204
D32
VSS_205
D39
VSS_206
D45
VSS_207
D49
VSS_208
E10
VSS_209
E16
VSS_210
E24
VSS_211
E28
VSS_212
E32
VSS_213
E47
VSS_214
F19
VSS_215
F36
VSS_216
F4
VSS_217
F40
VSS_218
F50
VSS_219
G1
VSS_220
G13
VSS_221
G16
VSS_222
G19
VSS_223
G24
VSS_224
G28
VSS_225
G29
VSS_226
G33
VSS_227
G42
VSS_228
G45
VSS_229
G48
VSS_230
G8
VSS_231
H24
VSS_232
H28
VSS_233
H4
VSS_234
H45
VSS_235
J11
VSS_236
J16
VSS_237
J2
VSS_238
J24
VSS_239
J28
VSS_240
J33
VSS_241
J35
VSS_242
J39
VSS_243
K12
VSS_245
K47
VSS_246
K8
VSS_247
L1
VSS_248
L17
VSS_249
L20
VSS_250
L24
VSS_251
L28
VSS_252
L3
VSS_253
L33
VSS_254
L49
VSS_255
M28
VSS_256
M42
VSS_257
M46
VSS_258
M49
VSS_259
M5
VSS_260
M50
VSS_261
M9
VSS_262
N11
VSS_263
N14
VSS_264
N17
VSS_265
N29
VSS_266
N32
VSS_267
N36
VSS_268
N39
VSS_269
N44
VSS_270
N49
VSS_271
N7
VSS_272
P19
VSS_273
P2
VSS_274
P23
VSS_275
P3
VSS_276
P50
VSS_277
R49
VSS_278
T39
VSS_279
T43
VSS_280
T47
VSS_281
U41
VSS_282
U45
VSS_283
U50
VSS_284
V2
VSS_285
V3
VSS_286
CRESTLINE_1p0
PM@
VSS
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
W11
VSS_287
W39
VSS_288
W43
VSS_289
W47
VSS_290
W5
VSS_291
W7
VSS_292
Y13
VSS_293
Y2
VSS_294
Y41
VSS_295
Y45
VSS_296
Y49
VSS_297
Y5
VSS_298
Y50
VSS_299
Y11
VSS_300
P29
VSS_301
T29
VSS_302
T31
VSS_303
T33
VSS_304
R28
VSS_305
AA32
VSS_306
AB32
VSS_307
AD32
VSS_308
AF28
VSS_309
AF29
VSS_310
AT27
VSS_311
AV25
VSS_312
H50
VSS_313
2006/08/18 2007/8/18
3
Compal Secret Data
Deciphered Date
2
Title
Size Document Number Rev
B
2
Date: Sheet
Compal Electronics, Inc.
Crestline (7/7)-GND
LA-3691P
1
0.2
13 45Thursday, March 08, 2007
1
of
Page 14
5
4
3
2
1
+1.8V +1.8V
JP25
+DIMM_VREF
DDRA_SDQ0
DDRA_SDQ1
1
C228
0.1U_0402_16V4Z
2
DDRA_SDQS0#
DDRA_SDQS0
DDRA_SDQ2
DDRA_SDQ3
DDRA_SDQ8
DDRA_SDQ9
DDRA_SDQS1#
DDRA_SDQS1
DDRA_SDQ10
DDRA_SDQ11
DDRA_SDQ16
DDRA_SDQ17
DDRA_SDQS2#
DDRA_SDQS2
DDRA_SDQ18
DDRA_SDQ19
DDRA_SDQ24
DDRA_SDQ25
DDRA_SDM3
EC_TX_P80_DATA
DDRA_SDQ26
DDRA_SDQ27
DDRA_CKE0
EC_RX_P80_CLK
DDRA_SBS2
DDRA_SMA12
DDRA_SMA9
DDRA_SMA8
DDRA_SMA5
DDRA_SMA3
DDRA_SMA1
DDRA_SMA10
DDRA_SBS0
DDRA_SWE#
DDRA_SCAS#
DDRA_SCS1#
DDRA_ODT1
DDRA_SDQ32
DDRA_SDQ33
DDRA_SDQS4#
DDRA_SDQS4
DDRA_SDQ34
DDRA_SDQ35
DDRA_SDQ40
DDRA_SDQ41
DDRA_SDM5
DDRA_SDQ42
DDRA_SDQ43
DDRA_SDQ48
DDRA_SDQ49
EC_RX_P80_CLK_R
DDRA_SDQS6#
DDRA_SDQS6
DDRA_SDQ50
DDRA_SDQ51
DDRA_SDQ56
DDRA_SDQ57
DDRA_SDM7
DDRA_SDQ58
DDRA_SDQ59
D_CK_SDATA
D_CK_SCLK
+3VS
1
2
DIMM0 STD H:5.2mm (BOT)
DDRA_SDQS0#<9>
DDRA_SDQS0<9>
D D
DDRA_SDQS1#<9>
DDRA_SDQS1<9>
DDRA_SDQS2#<9>
DDRA_SDQS2<9>
EC_TX_P80_DATA<15,32,34>
C C
EC_RX_P80_CLK<15,32,34>
B B
EC_RX_P80_CLK
A A
DDRA_CKE0<8>
DDRA_SBS2<9>
DDRA_SBS0<9>
DDRA_SWE#<9>
DDRA_SCAS#<9>
DDRA_SCS1#<8>
DDRA_ODT1<8>
DDRA_SDQS4#<9>
DDRA_SDQS4<9>
R201 0_0402_5%
1 2
EC_RX_P80_CLK_R<15>
DDRA_SDQS6#<9>
DDRA_SDQS6<9>
D_CK_SDATA<15,16,24,25>
D_CK_SCLK<15,16,24,25>
+3VS
C234
2.2U_0805_10V6K
5
1
VREF
3
VSS
5
DQ0
7
DQ1
9
VSS
11
DQS0#
13
DQS0
15
VSS
17
DQ2
19
DQ3
21
VSS
23
DQ8
25
DQ9
27
VSS
29
DQS1#
31
DQS1
33
VSS
35
DQ10
37
DQ11
39
VSS
41
VSS
43
DQ16
45
DQ17
47
VSS
49
DQS2#
51
DQS2
53
VSS
55
DQ18
57
DQ19
59
VSS
61
DQ24
63
DQ25
65
VSS
67
DM3
69
NC
71
VSS
73
DQ26
75
DQ27
77
VSS
79
CKE0
81
VDD
83
NC
85
BA2
87
VDD
89
A12
91
A9
93
A8
95
VDD
97
A5
99
A3
101
A1
103
VDD
105
A10/AP
107
BA0
109
WE#
111
VDD
113
CAS#
115
NC/S1#
117
VDD
119
NC/ODT1
121
VSS
123
DQ32
125
DQ33
127
VSS
129
DQS4#
131
DQS4
133
VSS
135
DQ34
137
DQ35
139
VSS
141
DQ40
143
DQ41
145
VSS
147
DM5
149
VSS
151
DQ42
153
DQ43
155
VSS
157
DQ48
159
DQ49
161
VSS
163
NC,TEST
165
VSS
167
DQS6#
169
DQS6
171
VSS
173
DQ50
175
DQ51
177
VSS
179
DQ56
181
DQ57
183
VSS
185
DM7
187
VSS
189
DQ58
191
DQ59
193
VSS
195
SDA
197
SCL
199
VDDSPD
TYCO_292526-4
ME@
Change PCB F ootprint
VSS
DQ4
DQ5
VSS
DM0
VSS
DQ6
DQ7
VSS
DQ12
DQ13
VSS
DM1
VSS
CK0
CK0#
VSS
DQ14
DQ15
VSS
VSS
DQ20
DQ21
VSS
DM2
VSS
DQ22
DQ23
VSS
DQ28
DQ29
VSS
DQS3#
DQS3
VSS
DQ30
DQ31
VSS
NC/CKE1
VDD
NC/A15
NC/A14
VDD
VDD
VDD
RAS#
VDD
ODT0
NC/A13
VDD
VSS
DQ36
DQ37
VSS
DM4
VSS
DQ38
DQ39
VSS
DQ44
DQ45
VSS
DQS5#
DQS5
VSS
DQ46
DQ47
VSS
DQ52
DQ53
VSS
CK1
CK1#
VSS
DM6
VSS
DQ54
DQ55
VSS
DQ60
DQ61
VSS
DQS7#
DQS7
VSS
DQ62
DQ63
VSS
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
NC
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
A11
92
A7
94
A6
96
98
A4
100
A2
102
A0
104
106
BA1
108
110
S0#
112
114
116
118
120
NC
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
SA0
200
SA1
4
9/25 Change DIMM0 to SP070004Z00 (HBL50)
DDRA_SDQ4
DDRA_SDQ5
DDRA_SDM0
DDRA_SDQ6
DDRA_SDQ7
DDRA_SDQ12
DDRA_SDQ13
DDRA_SDM1
DDRA_SDQ14
DDRA_SDQ15
DDRA_SDQ20
DDRA_SDQ21
DDRA_SDM2
DDRA_SDQ22
DDRA_SDQ23
DDRA_SDQ28
DDRA_SDQ29
DDRA_SDQS3#
DDRA_SDQS3
DDRA_SDQ30
DDRA_SDQ31
DDRA_CKE1
DDRA_SMA14
DDRA_SMA11
DDRA_SMA7
DDRA_SMA6
DDRA_SMA4
DDRA_SMA2
DDRA_SMA0
DDRA_SBS1
DDRA_SRAS#
DDRA_SCS0#
DDRA_ODT0
DDRA_SMA13
DDRA_SDQ36
DDRA_SDQ37
DDRA_SDM4
DDRA_SDQ38
DDRA_SDQ39
DDRA_SDQ44
DDRA_SDQ45
DDRA_SDQS5#
DDRA_SDQS5
DDRA_SDQ46
DDRA_SDQ47
DDRA_SDQ52
DDRA_SDQ53
DDRA_SDM6
DDRA_SDQ54
DDRA_SDQ55
DDRA_SDQ60
DDRA_SDQ61
DDRA_SDQS7#
DDRA_SDQS7
DDRA_SDQ62
DDRA_SDQ63
R204 10K_0402_5%
1 2
R205 10K_0402_5%
1 2
DDRA_CLK0 <8>
DDRA_CLK0# <8>
R207 0_0402_5%
1 2
DDRA_SDQS3# <9>
DDRA_SDQS3 <9>
DDRA_CKE1 <8>
DDRA_SBS1 <9>
DDRA_SRAS# <9>
DDRA_SCS0# <8>
DDRA_ODT0 <8>
DDRA_SDQS5# <9>
DDRA_SDQS5 <9>
DDRA_CLK1 <8>
DDRA_CLK1# <8>
DDRA_SDQS7# <9>
DDRA_SDQS7 <9>
PM_EXTTS#0 <8>
DDRA_SMA14<8>
Security Classification
Issued Date
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
+DIMM_VREF
1
2
95.10.5 modify
2006/08/18 2007/8/18
3
20mils
C224
0.1U_0402_16V4Z
DDRA_SMA[0..13]<9>
DDRA_SDQ[0..63]<9>
DDRA_SDM[0..7]<9>
DDRA_CKE0
DDRA_SBS2
DDRA_SMA12
DDRA_SMA9
DDRA_SMA8
DDRA_SMA5
DDRA_SMA3
DDRA_SMA1
DDRA_SMA10
DDRA_SBS0
DDRA_SWE#
DDRA_SCAS#
DDRA_SCS1#
DDRA_ODT1
DDRA_SMA11
DDRA_SMA14
DDRA_SMA6
DDRA_SMA7
DDRA_SMA2
DDRA_SMA4
DDRA_SBS1
DDRA_SMA0
DDRA_SCS0#
DDRA_SRAS#
DDRA_SMA13
DDRA_ODT0
DDRA_CKE1
1
C225
2.2U_0805_10V6K
2
1 4
2 3
RP14 56_0404_4P2R_5%
1 4
2 3
RP15 56_0404_4P2R_5%
RP16 56_0404_4P2R_5%
RP17 56_0404_4P2R_5%
RP18 56_0404_4P2R_5%
RP19 56_0404_4P2R_5%
RP20 56_0404_4P2R_5%
RP21 56_0404_4P2R_5%
RP22 56_0404_4P2R_5%
RP23 56_0404_4P2R_5%
RP24 56_0404_4P2R_5%
RP25 56_0404_4P2R_5%
RP26 56_0404_4P2R_5%
R208 56_0402_5%
Layout Note:
Place these resistor
closely JP35,all
trace length Max=1.5"
1 4
2 3
1 4
2 3
1 4
2 3
1 4
2 3
1 4
2 3
1 4
2 3
1 4
2 3
1 4
2 3
1 4
2 3
1 4
2 3
1 4
2 3
1 2
Compal Secret Data
Deciphered Date
1K_0402_1%
1K_0402_1%
DDRA_SMA[0..13]
DDRA_SDQ[0..63]
DDRA_SDM[0..7]
+0.9VS
R195
R198
+1.8V
12
Layout Note:
Place near JP35
+DIMM_VREF
1
C245
2.2U_0805_10V6K
2
1
C244
0.1U_0402_16V4Z
2
1
C236
0.1U_0402_16V4Z
2
1
C241
0.1U_0402_16V4Z
2
1
C254
0.1U_0402_16V4Z
2
Date: Sheet of
1
Title
Size Document Number Rev
B
C233
2.2U_0805_10V6K
2
1
C230
0.1U_0402_16V4Z
2
1
C237
0.1U_0402_16V4Z
2
1
C250
0.1U_0402_16V4Z
2
1
C255
0.1U_0402_16V4Z
2
LA-3691P
1
C242
2.2U_0805_10V6K
2
1
C231
0.1U_0402_16V4Z
2
1
C238
0.1U_0402_16V4Z
2
1
C251
0.1U_0402_16V4Z
2
1
C246
2.2U_0805_10V6K
2
1
C239
0.1U_0402_16V4Z
2
1
C252
0.1U_0402_16V4Z
2
Compal Electronics, Inc.
DDRII-SODIMM0
14 45Thursday, March 08, 2007
1
0.2
12
1
C221
220P_0402_50V7K
2
@
+1.8V
1
C232
2.2U_0805_10V6K
2
+1.8V
1
C243
0.1U_0402_16V4Z
2
+0.9VS
1
C235
0.1U_0402_16V4Z
2
+0.9VS
1
C240
0.1U_0402_16V4Z
2
+0.9VS
1
C253
0.1U_0402_16V4Z
2
Layout Note:
Place one cap close to every 2 pullup
resistors terminated to +0.9VS
2
Page 15
A
B
C
D
E
9/25 Change DIMM1 to SP070006F00
JP23
+DIMM_VREF
DDRB_SDQ0
DDRB_SDQ1
1 1
2 2
3 3
4 4
EC_TX_P80_DATA<14,32,34>
EC_RX_P80_CLK<14,32,34>
EC_RX_P80_CLK_R<14>
DDRB_SDQS0#<9>
DDRB_SDQS0<9>
DDRB_SDQS1#<9>
DDRB_SDQS1<9>
DDRB_SDQS2#<9>
DDRB_SDQS2<9>
DDRB_CKE0<8>
DDRB_SBS2<9>
DDRB_SBS0<9>
DDRB_SWE#<9>
DDRB_SCAS#<9>
DDRB_SCS1#<8>
DDRB_ODT1<8>
DDRB_SDQS4#<9>
DDRB_SDQS4<9>
DDRB_SDQS6#<9>
DDRB_SDQS6<9>
D_CK_SDATA<14,16,24,25>
D_CK_SCLK<14,16,24,25>
DDRB_SDQS0#
DDRB_SDQS0
DDRB_SDQ2
DDRB_SDQ3
DDRB_SDQ8
DDRB_SDQ9
DDRB_SDQS1#
DDRB_SDQS1
DDRB_SDQ10
DDRB_SDQ11
DDRB_SDQ16
DDRB_SDQ17
DDRB_SDQS2#
DDRB_SDQS2
DDRB_SDQ18
DDRB_SDQ19
DDRB_SDQ24
DDRB_SDQ25
DDRB_SDM3
EC_TX_P80_DATA
DDRB_SDQ26
DDRB_SDQ27
DDRB_CKE0
EC_RX_P80_CLK
DDRB_SBS2
DDRB_SMA12
DDRB_SMA9
DDRB_SMA8
DDRB_SMA5
DDRB_SMA3
DDRB_SMA1
DDRB_SMA10
DDRB_SBS0
DDRB_SWE#
DDRB_SCAS#
DDRB_SCS1#
DDRB_ODT1
DDRB_SDQ32
DDRB_SDQ33
DDRB_SDQS4#
DDRB_SDQS4
DDRB_SDQ34
DDRB_SDQ35
DDRB_SDQ40
DDRB_SDQ41
DDRB_SDM5
DDRB_SDQ42
DDRB_SDQ43
DDRB_SDQ48
DDRB_SDQ49
EC_RX_P80_CLK_R
DDRB_SDQS6#
DDRB_SDQS6
DDRB_SDQ50
DDRB_SDQ51
DDRB_SDQ56
DDRB_SDQ57
DDRB_SDM7
DDRB_SDQ58
DDRB_SDQ59
D_CK_SDATA
D_CK_SCLK
+3VS
1
VREF
3
VSS
5
DQ0
7
DQ1
9
VSS
11
DQS0#
13
DQS0
15
VSS
17
DQ2
19
DQ3
21
VSS
23
DQ8
25
DQ9
27
VSS
29
DQS1#
31
DQS1
33
VSS
35
DQ10
37
DQ11
39
VSS
41
VSS
43
DQ16
45
DQ17
47
VSS
49
DQS2#
51
DQS2
53
VSS
55
DQ18
57
DQ19
59
VSS
61
DQ24
63
DQ25
65
VSS
67
DM3
69
NC
71
VSS
73
DQ26
75
DQ27
77
VSS
79
CKE0
81
VDD
83
NC
85
BA2
87
VDD
89
A12
91
A9
93
A8
95
VDD
97
A5
99
A3
101
A1
103
VDD
105
A10/AP
107
BA0
109
WE#
111
VDD
113
CAS#
115
NC/S1#
117
VDD
119
NC/ODT1
121
VSS
123
DQ32
125
DQ33
127
VSS
129
DQS4#
131
DQS4
133
VSS
135
DQ34
137
DQ35
139
VSS
141
DQ40
143
DQ41
145
VSS
147
DM5
149
VSS
151
DQ42
153
DQ43
155
VSS
157
DQ48
159
DQ49
161
VSS
163
NC,TEST
165
VSS
167
DQS6#
169
DQS6
171
VSS
173
DQ50
175
DQ51
177
VSS
179
DQ56
181
DQ57
183
VSS
185
DM7
187
VSS
189
DQ58
191
DQ59
193
VSS
195
SDA
197
SCL
199
VDDSPD
TYCO_292530-4
ME@
DQS3#
NC/CKE1
NC/A15
NC/A14
NC/A13
DQS5#
DQS7#
DIMM1 STD H:9.2mm (BOT)
A
VSS
DQ4
DQ5
VSS
DM0
VSS
DQ6
DQ7
VSS
DQ12
DQ13
VSS
DM1
VSS
CK0
CK0#
VSS
DQ14
DQ15
VSS
VSS
DQ20
DQ21
VSS
DM2
VSS
DQ22
DQ23
VSS
DQ28
DQ29
VSS
DQS3
VSS
DQ30
DQ31
VSS
VDD
VDD
VDD
VDD
BA1
RAS#
VDD
ODT0
VDD
VSS
DQ36
DQ37
VSS
DM4
VSS
DQ38
DQ39
VSS
DQ44
DQ45
VSS
DQS5
VSS
DQ46
DQ47
VSS
DQ52
DQ53
VSS
CK1
CK1#
VSS
DM6
VSS
DQ54
DQ55
VSS
DQ60
DQ61
VSS
DQS7
VSS
DQ62
DQ63
VSS
SAO
SA1
+1.8V+1.8V
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
NC
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
A11
92
A7
94
A6
96
98
A4
100
A2
102
A0
104
106
108
110
S0#
112
114
116
118
120
NC
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
B
DDRB_SDQ4
DDRB_SDQ5
DDRB_SDM0
DDRB_SDQ6
DDRB_SDQ7
DDRB_SDQ12
DDRB_SDQ13
DDRB_SDM1
DDRB_CLK0 <8>
R199
DDRB_CLK0# <8>
0_0402_5%
1 2
DDRB_CKE1 <8>
DDRB_SMA14 <8>
DDRB_SBS1 <9>
DDRB_SRAS# <9>
DDRB_SCS0# <8>
DDRB_ODT0 <8>
DDRB_CLK1 <8>
DDRB_CLK1# <8>
DDRB_SDQ14
DDRB_SDQ15
DDRB_SDQ20
DDRB_SDQ21
DDRB_SDM2
DDRB_SDQ22
DDRB_SDQ23
DDRB_SDQ28
DDRB_SDQ29
DDRB_SDQS3#
DDRB_SDQS3
DDRB_SDQ30
DDRB_SDQ31
DDRB_CKE1
DDRB_SMA14
DDRB_SMA11
DDRB_SMA7
DDRB_SMA6
DDRB_SMA4
DDRB_SMA2
DDRB_SMA0
DDRB_SBS1
DDRB_SRAS#
DDRB_SCS0#
DDRB_ODT0
DDRB_SMA13
DDRB_SDQ36
DDRB_SDQ37
DDRB_SDM4
DDRB_SDQ38
DDRB_SDQ39
DDRB_SDQ44
DDRB_SDQ45
DDRB_SDQS5#
DDRB_SDQS5
DDRB_SDQ46
DDRB_SDQ47
DDRB_SDQ52
DDRB_SDQ53
DDRB_SDM6
DDRB_SDQ54
DDRB_SDQ55
DDRB_SDQ60
DDRB_SDQ61
DDRB_SDQS7
DDRB_SDQ62
DDRB_SDQ63
R196 10K_0402_5%
1 2
R197 10K_0402_5%
1 2
DDRB_SMA[0..13]<9>
DDRB_SDQ[0..63]<9>
DDRB_SDM[0..7]<9>
DDRB_SMA[0..13]
DDRB_SDQ[0..63]
DDRB_SDM[0..7]
DDRB_CLK0?
PM_EXTTS#1 <8>
DDRB_SDQS3# <9>
DDRB_SDQS3 <9>
DDRB_CKE0
DDRB_SBS2
DDRB_SMA12
DDRB_SMA9
DDRB_SMA8
DDRB_SMA5
DDRB_SMA3
DDRB_SMA1
DDRB_SMA10
DDRB_SBS0
DDRB_SWE#
DDRB_SCAS#
DDRB_SCS1#
DDRB_ODT1
DDRB_SMA11
DDRB_CKE1
DDRB_SDQS5# <9>
DDRB_SDQS5 <9>
DDRB_CLK1?
DDRB_SDQS7# <9>
DDRB_SDQS7 <9>
+3VS
Security Classification
Issued Date
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
DDRB_SMA14<8>
2006/08/18 2007/8/18
DDRB_SMA6
DDRB_SMA7
DDRB_SMA2
DDRB_SMA4
DDRB_SBS1
DDRB_SMA0
DDRB_SCS0#
DDRB_SRAS#
DDRB_SMA13
DDRB_ODT0
DDRB_SMA14DDRB_SDQS7#
Layout Note:
Place these resistor
closely JP35,all
trace length Max=1.5"
Compal Secret Data
1 4
2 3
RP1 56_0404_4P2R_5%
1 4
2 3
RP2 56_0404_4P2R_5%
1 4
2 3
RP3 56_0404_4P2R_5%
1 4
2 3
RP4 56_0404_4P2R_5%
1 4
2 3
RP5 56_0404_4P2R_5%
1 4
2 3
RP6 56_0404_4P2R_5%
1 4
2 3
RP7 56_0404_4P2R_5%
1 4
2 3
RP8 56_0404_4P2R_5%
1 4
2 3
RP9 56_0404_4P2R_5%
1 4
2 3
RP10 56_0404_4P2R_5%
1 4
2 3
RP11 56_0404_4P2R_5%
1 4
2 3
RP12 56_0404_4P2R_5%
1 4
2 3
RP13 56_0404_4P2R_5%
1 2
R194 56_0402_5%
Deciphered Date
D
+0.9VS
+DIMM_VREF
1
C199
2.2U_0805_10V6K
2
Layout Note:
Place near JP34
+1.8V
1
C487
C483
2.2U_0805_10V6K
2
2.2U_0805_10V6K
+1.8V
1
C218
C217
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z
+0.9VS
1
C192
C193
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z
+0.9VS
1
C197
C198
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z
+0.9VS
1
C207
C206
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z
Layout Note:
Place one cap close to every 2 pullup
resistors terminated to +0.9VS
Title
Size Document Number Rev
B
Date: Sheet
1
C200
2
0.1U_0402_16V4Z
1
2
1
2
1
2
1
2
1
2
C219
2.2U_0805_10V6K
C482
0.1U_0402_16V4Z
C194
0.1U_0402_16V4Z
C203
0.1U_0402_16V4Z
C208
0.1U_0402_16V4Z
1
C220
2
2.2U_0805_10V6K
1
C479
0.1U_0402_16V4Z
2
1
C195
0.1U_0402_16V4Z
2
1
C204
2
0.1U_0402_16V4Z
1
2
1
2
1
2
1
2
1
2
Compal Electronics, Inc.
DDRII-SODIMM1
LA-3691P
E
1
C216
2.2U_0805_10V6K
2
1
C196
2
0.1U_0402_16V4Z
1
C205
0.1U_0402_16V4Z
2
15 45Thursday, March 08, 2007
0.2
of
Page 16
5
PCI
SRC
CPU
CLKSEL1
1
1
FSLA
CLKSEL0
MHz
200
166
MHz
1000
100
MHz
33.30
33.3
FSLC1FSLB
CLKSEL2
0
FSB Frequency Selet:
D D
CPU Driven
(Default)
*
667MHz
800MHz
CPU_BSEL0<5>
C C
CPU_BSEL1<5>
B B
CPU_BSEL2<5>
C525 27P_0402_50V8J
A A
14.31818MHZ_16PF_DSX840GA
C524 27P_0402_50V8J
Routing the t race at least 10mil
FSC
Stuff
No Stuff
Stuff
No Stuff
Stuff
No Stuff
FSA
R386
2.2K_0402_5%
1 2
R393
0_0402_5%
FSB
1 2
R450
0_0402_5%
R451
2.2K_0402_5%
1 2
R456
0_0402_5%
Y3
R401 R408 R417 R430 R447R438
R401 R417 R447
R408 R430 R438
R408 R417 R447
R401 R430 R438
+VCCP
R387
56_0402_5%
@
1 2
12
12
+VCCP
+VCCP
1 2
R388
1K_0402_5%
12
R385
1K_0402_5%
@
R444
1K_0402_5%
@
1 2
1 2
R448
1K_0402_5%
12
R445
0_0402_5%
@
R453
1K_0402_5%
@
1 2
1 2
R455
1K_0402_5%
12
R452
0_0402_5%
@
MCH_CLKSEL0 <8>
MCH_CLKSEL1 <8>
MCH_CLKSEL2 <8>
For ITP_EN, 0 =SRC8/SRC8#; 1 = ITP/ITP#
For 27_SEL, 0 = Enable DOT96 & SRC1,
For PCI2_EN, 0 = Overclocking of CPU and SRC Allowed
+3VS +3VS +3VS
12
5
CLK_XTAL_IN
CLK_XTAL_OUT
R395
10K_0402_5%
@
1 2
ITP_EN
R400
10K_0402_5%
1 2
SATA_CLKREQ#<22>
MCH_CLKREQ#<8>
CLK_PCI_LPC<32>
CLK_PCI_DB<34>
CLK_PCI_ICH<20>
CLK_ICH_48M<22>
CLK_14M_SIO<34>
CLK_ICH_14M<22>
1= Enable SRC0 & 27MHz
1 = Overclocking of CPU and SRC NOT allowed
+3VS
R460 0_1206_5%
R408
10K_0402_5%
PM@
1 2
27_SEL
R402
10K_0402_5%
GM@
1 2
4
1 2
+1.25VS
4
+3VM_CK505
1
C534
10U_0805_10V4Z
2
1 2
R461 0_1206_5%
+1.25VM_CK505
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
+1.25VM_CK505
R418
10K_0402_5%
1 2
PCI2_TME
R414
10K_0402_5%
@
1 2
+1.25VM_CK505
R415475_0402_1%
R403475_0402_1%
R40122_0402_5%
R41333_0402_5%
R41233_0402_5%
CLK_XTAL_IN
CLK_XTAL_OUT
R39933_0402_5%
R44222_0402_5%
R44322_0402_5%
1
2
1
C518
0.1U_0402_16V4Z
2
1
C533
10U_0805_10V4Z
2
+3VM_CK505
PCI_CLK0
PCI_CLK1
PCI2_TME
PCI_CLK3
27_SEL
ITP_EN
FSA
FSB
FSC
C489
0.1U_0402_16V4Z
3
1
C522
0.1U_0402_16V4Z
2
1
C520
0.1U_0402_16V4Z
2
10/17 : Change P/N from SA0001GT00 to SA00001GT10
1
C521
0.1U_0402_16V4Z
2
1
C519
0.1U_0402_16V4Z
2
1
C494
0.1U_0402_16V4Z
2
1
C517
0.1U_0402_16V4Z
2
1
C493
0.1U_0402_16V4Z
2
1
C490
0.1U_0402_16V4Z
2
2
1
C491
0.1U_0402_16V4Z
2
1
C492
0.1U_0402_16V4Z
2
Need to update Symbol
U23
2
VDD_PCI
9
VDD48
16
VDDPLL3
61
VDDREF
39
VDDSRC
55
VDDCPU
12
VDD96_IO
20
VDDPLL3_IO
26
VDDSRC_IO
36
VDDSRC_IO
49
VDDCPU_IO
1
PCI0/CR#_A
3
PCI1/CR#_B
4
PCI2/TME
5
PCI3
6
PCI4/27_Select
7
PCIF5/ITP_EN
60
X1
59
X2
10
USB_48MHZ/FSLA
57
FSLB/TEST MODE
62
REF0/FSLC/TEST_SEL
45
VDDSRC_IO
42
GNDSRC
8
GNDPCI
11
GND48
15
GND
19
GND
52
GNDCPU
23
GNDSRC
29
GNDSRC
58
GNDREF
* Internal Pull-Up Resistor
<BOM Structure>
** Internal Pull-Down Resistor
Security Classification
Issued Date
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
SRC11/CR#_H
SRC11#/CR#_G
SRC7#/CR#_E
SRC3#/CR#_D
SRC2#/SATA#
SRC1/SE1/27MHz_NonSS
SRC1#/SE2/27MHz_SS
SRC0/DOT96#
CK_PWRGD/PD#
ICS9LPRS365
2006/08/04 2006/10/06
SCLK
SDATA
PCI_STOP#
CPU_STOP#
CPU0
CPU0#
CPU1_F
CPU1#_F
SRC8/ITP
SRC8#/ITP#
SRC10#
SRC10
SRC9
SRC9#
SRC7/CR#_F
SRC6
SRC6#
SRC4
SRC4#
SRC3/CR#_C
SRC2/SATA
SRC0/DOT96
48
NC
D_CK_SCLK
64
D_CK_SDATA
63
PM_STP_PCI#
38
PM_STP_CPU#
37
CLK_CPU_BCLK
54
CLK_CPU_BCLK#
53
CLK_MCH_BCLK
51
CLK_MCH_BCLK#
50
47
46
CLK_PCIE_EXP#
35
CLK_PCIE_EXP
34
33
32
CLK_PCIE_WLAN
30
CLK_PCIE_WLAN#
31
44
R_CLKREQ#_E
43
CLK_PCIE_LAN
41
CLK_PCIE_LAN#
40
CLK_MCH_3GPLL
27
CLK_MCH_3GPLL#
28
CLK_PCIE_ICH
24
CLK_PCIE_ICH#
25
CLK_PCIE_SATA
21
CLK_PCIE_SATA#
22
CLK_PCIE0
17
CLK_PCIE0#
18
13
R_CLK_DOT#
14
CK_PWRGD
56
R439 475_0402_1%
R417 475_0402_1%
R440 475_0402_1%
R405 0_0402_5%GM@
R404 0_0402_5%GM@
R390 0_0402_5%PM@
R389 0_0402_5%PM@
R407 0_0402_5%GM@
R406 0_0402_5%GM@
R392 0_0402_5%PM@
R391 0_0402_5%PM@
ICS9LPRS365/SA00001GT00
Compal Secret Data
Deciphered Date
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
R441 10K_0402_5%
1 2
R411 10K_0402_5%
1 2
R449 10K_0402_5%
1 2
2
ICH_SMBDATA<22,30>
+3VS
ICH_SMBCLK<22,30>
D_CK_SCLK <14,15,24,25>
D_CK_SDATA <14,15,24,25>
PM_STP_PCI# <22>
PM_STP_CPU# <22>
CLK_CPU_BCLK <4>
CLK_CPU_BCLK# <4>
CLK_MCH_BCLK <7>
CLK_MCH_BCLK# <7>
CLK_PCIE_EXP# <25>
CLK_PCIE_EXP <25>
EXP_CLKREQ# <25>
WLAN_CLKREQ# <24>
CLK_PCIE_WLAN <24>
CLK_PCIE_WLAN# <24>
CLKREQ_LAN# <30>
CLK_PCIE_LAN <30>
CLK_PCIE_LAN# <30>
CLK_MCH_3GPLL <8>
CLK_MCH_3GPLL# <8>
CLK_PCIE_ICH <22>
CLK_PCIE_ICH# <22>
CLK_PCIE_SATA <21>
CLK_PCIE_SATA# <21>
CLK_DREF_SSC <8>
CLK_DREF_SSC# <8>
CLK_27M_VGA <17>
CLK_27M_VGA# <17>
CLK_DREF_96M <8>
CLK_DREF_96M# <8>
CLK_PCIE_VGA <17>
CLK_PCIE_VGA# <17>
+3VS
+3VS
+3VS
CK_PWRGD <22>
Title
Size Document Number Rev
Date: Sheet
1
+3VS
R430
2.2K_0402_5%
D_CK_SDATA
D_CK_SCLK
CLK_ICH_48M
12
5P_0402_50V8C@
CLK_ICH_14M
12
4.7P_0402_50V8C@
CLK_PCI_ICH
12
4.7P_0402_50V8C@
CLK_14M_SIO
12
4.7P_0402_50V8C@
CLK_PCI_LPCR_CLK_DOT
12
4.7P_0402_50V8C@
CLK_PCI_DB
12
4.7P_0402_50V8C@
2.2K_0402_5%
D
1 3
2
2
1 3
D
R434
S
Q34
2N7002_SOT23
G
G
S
Q32
2N7002_SOT23
C471
C530
C480
C529
C477
C485
Place close to U35
Compal Electronics, Inc.
Clock generator
LA-3691P
16 45Thursday, March 08, 2007
1
0.2
of
Page 17
5
4
3
2
1
D D
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
PCIE_MTX_C_GRX_N[0..15]
PCIE_MTX_C_GRX_P[0..15]
PCIE_GTX_C_MRX_N[0..15]
PCIE_GTX_C_MRX_P[0..15]
PCIE_GTX_C_MRX_P0
PCIE_GTX_C_MRX_N0
PCIE_GTX_C_MRX_P2
PCIE_GTX_C_MRX_N2
PCIE_GTX_C_MRX_P4
PCIE_GTX_C_MRX_N4
PCIE_GTX_C_MRX_P6
PCIE_GTX_C_MRX_N6
PCIE_GTX_C_MRX_P8
PCIE_GTX_C_MRX_N8
PCIE_GTX_C_MRX_P10
PCIE_GTX_C_MRX_N10
PCIE_GTX_C_MRX_P12
PCIE_GTX_C_MRX_N12
PCIE_GTX_C_MRX_P14
PCIE_GTX_C_MRX_N14
SUSP#
VGA_THER_ALERT#
SUSP# <25,32,37,40,42,43,44>
VGA_THER_ALERT# <22>
VGA_ENBKL <18>
PLT_RST_BUF# <8,20,22,24,25,30>
CLK_27M_VGA <16>
CLK_27M_VGA# <16>
CARD_COMP
CARD_LUMA
CARD_CRMA
PCIE_MTX_C_GRX_N[0..15]<10>
PCIE_MTX_C_GRX_P[0..15]<10>
PCIE_GTX_C_MRX_N[0..15]<10>
PCIE_GTX_C_MRX_P[0..15]<10>
JP19
1
PCIE_MTX_C_GRX_P1
PCIE_MTX_C_GRX_N1
PCIE_MTX_C_GRX_P3
PCIE_MTX_C_GRX_N3
PCIE_MTX_C_GRX_P5
PCIE_MTX_C_GRX_N5
PCIE_MTX_C_GRX_P7
C C
B B
PCIE_MTX_C_GRX_N7
PCIE_MTX_C_GRX_P9
PCIE_MTX_C_GRX_N9
PCIE_MTX_C_GRX_P11
PCIE_MTX_C_GRX_N11
PCIE_MTX_C_GRX_P13
PCIE_MTX_C_GRX_N13
PCIE_MTX_C_GRX_P15
PCIE_MTX_C_GRX_N15
+1.5VS
+2.5VS
+3VS +5VS
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
20
21
21
22
22
23
23
24
24
25
25
26
26
27
27
28
28
29
29
30
30
31
31
32
32
33
33
34
34
35
35
36
36
37
37
38
38
39
39
40
40
HRS_FX8-80P-SV1(92)
ME@
41
41
42
42
43
43
44
44
45
45
46
46
47
47
48
48
49
49
50
50
51
51
52
52
53
53
54
54
55
55
56
56
57
57
58
58
59
59
60
60
61
61
62
62
63
63
64
64
65
65
66
66
67
67
68
68
69
69
70
70
71
71
72
72
73
73
74
74
75
75
76
76
77
77
78
78
79
79
80
80
PCIE_GTX_C_MRX_P1
PCIE_GTX_C_MRX_N1
PCIE_GTX_C_MRX_P3
PCIE_GTX_C_MRX_N3
PCIE_GTX_C_MRX_P5
PCIE_GTX_C_MRX_N5
PCIE_GTX_C_MRX_P7
PCIE_GTX_C_MRX_N7
PCIE_GTX_C_MRX_P9
PCIE_GTX_C_MRX_N9
PCIE_GTX_C_MRX_P11
PCIE_GTX_C_MRX_N11
PCIE_GTX_C_MRX_P13
PCIE_GTX_C_MRX_N13
PCIE_GTX_C_MRX_P15
PCIE_GTX_C_MRX_N15
+1.8VS
B+
PCIE_MTX_C_GRX_P0
PCIE_MTX_C_GRX_N0
PCIE_MTX_C_GRX_P2
PCIE_MTX_C_GRX_N2
PCIE_MTX_C_GRX_P4
PCIE_MTX_C_GRX_N4
PCIE_MTX_C_GRX_P6
PCIE_MTX_C_GRX_N6
PCIE_MTX_C_GRX_P8
PCIE_MTX_C_GRX_N8
PCIE_MTX_C_GRX_P10
PCIE_MTX_C_GRX_N10
PCIE_MTX_C_GRX_P12
PCIE_MTX_C_GRX_N12
PCIE_MTX_C_GRX_P14
PCIE_MTX_C_GRX_N14
CLK_PCIE_VGA<16>
CLK_PCIE_VGA#<16>
VGA_DDCCLK<19>
VGA_DDCDATA<19>
VGA_VSYNC<19>
VGA_HSYNC<19>
VGA_CRT_R<19>
VGA_CRT_G<19>
VGA_CRT_B<19>
JP20
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
20
21
21
22
22
23
23
24
24
25
25
26
26
27
27
28
28
29
29
30
30
31
31
32
32
33
33
34
34
35
35
36
36
37
37
38
38
39
39
40
40
HRS_FX8-80P-SV1(92)
ME@
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
MAX. 4.06A @ 1.8V
MAX. 130mA @ 2.5V
MAX. 655mA @ 3.3V
2
PM@
2
C174
1
0.1U_0402_16V4Z
PM@
C444
PM@
1
+3VS
0.047U_0402_16V4Z
2
C176
1
0.1U_0402_16V4Z
@
1
1
C445
2
2
0.047U_0402_16V4Z
PM@
+2.5VS+5VS
2
C454
C458
1
0.1U_0402_16V4Z
0.1U_0402_16V4Z
@
A A
Title
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2
Size Document Number Rev
Custom
Date: Sheet
Compal Electronics, Inc.
VGA/B connector
IEL10 LA-3451P
1
0.2
of
17 45Thursday, March 08, 2007
Page 18
5
LCD POWER CIRCUIT
4
3
2
1
INVERTER Conn.
2
GM@
LVDS_B0#
LVDS_B0
LVDS_B1#
LVDS_B1
LVDS_B2#
LVDS_B2
LVDS_BCLK#
LVDS_BCLK
LVDS_DATA
LVDS_CLK
+3VS
W=60mils
S
G
Q29
AO3413_SOT23-3
D
GM@
1 3
1
C334
4.7U_0805_10V4Z
2
+3VS
1
C329
4.7U_0805_10V4Z
2
+LCDVDD
1
C333
0.1U_0402_16V4Z
2
LVDS_B0# <10>
LVDS_B0 <10>
LVDS_B1# <10>
LVDS_B1 <10>
LVDS_B2# <10>
LVDS_B2 <10>
LVDS_BCLK# <10>
LVDS_BCLK <10>
GM@
W=60mils
GM@
JP3
1
INVT_PWM<32>
B+
DAC_BRIG<32>
DISPOFF#
L1
FBMA-L11-201209-221LMA30T_0805
BKOFF#<32>
GMCH_ENBKL<10>
VGA_ENBKL<17>
+INVPWR_B+
12
C14
0.1U_0603_50V4Z
BKOFF# DISPOFF#
2
3
4
5
6
7
MOLEX_53780-0790
ME@
D3
1 2
RB751V-40TE17_SOD323-2
R69 0_0402_5%GM@
R72 0_0402_5%PM@
+3VS
12
R6
4.7K_0402_5%
12
12
ENBKL
R66
100K_0402_5%
1 2
ENBKL <32>
R90
300_0603_5%
GM@
2
G
DTC124EK
2
12
+3VALW
12
R271
10K_0402_5%
GM@
R270 1K_0402_5%GM@
1
OUT
IN
GND
Q5
3
DTC124EKAT146_SC59-3
GM@
12
GM@
2
C330
0.047U_0402_16V7K
1
+LCDVDD
12
D D
13
D
Q6
GM@
2N7002_SOT23
R74 0_0402_5%
GMCH_ENVDD<10>
GM@
1 2
S
R71
@
100K_0402_5%
LCD/PANEL BD. Conn.
ME@
ACES_87216-3006
12
(60 MIL)
LVDS_A0#
LVDS_A0
LVDS_A1#
LVDS_A1
LVDS_A2#
LVDS_A2
LVDS_ACLK#
LVDS_ACLK
+LCDVDD_L
LVDS_A0#<10>
C C
+LCDVDD
LVDS_A0<10>
LVDS_A1#<10>
LVDS_A1<10>
LVDS_A2#<10>
LVDS_A2<10>
LVDS_ACLK#<10>
LVDS_ACLK<10>
L18
FBMA-L11-201209-221LMA30T_0805
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
GND31GND
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
JP16
32
30
30
29
29
28
28
27
27
26
26
25
25
24
24
23
23
22
22
21
21
20
20
19
19
18
18
17
17
16
16
Follow HEL80's pin definition
Except pin 29
+3VS
B B
LVDS_SDA<10>
LVDS_SCL<10>
A A
5
R77
2.2K_0402_5%
GM@
R75
GM@
2.2K_0402_5%
LVDS_DATA
LVDS_CLK
Security Classification
Issued Date
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
4
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2006/08/18 2007/8/18
Compal Secret Data
Deciphered Date
Title
Size Document Number Rev
B
2
Date: Sheet
Compal Electronics, Inc.
LVDS & DVI Connector
LA-3691P
1
0.2
of
18 45Thursday, March 08, 2007
Page 19
A
B
C
D
E
CRT Connector
1 1
VGA_CRT_R<17>
GMCH_CRT_R<10>
VGA_CRT_G<17>
GMCH_CRT_G<10>
VGA_CRT_B<17>
GMCH_CRT_B<10>
2 2
3 3
4 4
Place closed to chipset
1 2
R78 0_0402_5%PM@
1 2
R91 0_0402_5%GM@
1 2
R80 0_0402_5%PM@
1 2
R93 0_0402_5%GM@
1 2
R79 0_0402_5%PM@
1 2
R92 0_0402_5%GM@
VGA_HSYNC<17>
GMCH_CRT_HSYNC<10>
VGA_DDCDATA<17>
GMCH_CRT_DATA<10>
GMCH_CRT_CLK<10>
VGA_DDCCLK<17>
A
1 2
R82 0_0402_5%PM@
1 2
R81 0_0402_5%GM@
Place closed to chipset
VGA_VSYNC<17>
GMCH_CRT_VSYNC<10>
2.2K_0402_5%
1 2
12
R8
150_0402_1%
C34 0.1U_0402_16V4Z
1 2
R83 0_0402_5%PM@
1 2
R84 0_0402_5%GM@
+3VS
12
R53
12
R580_0402_5% PM@
R550_0402_5% GM@
1 2
R610_0402_5% GM@
12
R640_0402_5% PM@
12
R9
150_0402_1%
1 2
12
2.2K_0402_5%
R60
R12
150_0402_1%
12
+CRT_VCC
1
5
U2
P
OE#
A2Y
G
SN74AHCT1G125DCKR_SC70-5
3
1 2
C42 0.1U_0402_16V4Z
Update Footprint
+3VS
R62
2.2K_0402_5%
G
2
13
D
S
2
2N7002_SOT23
13
D
Q3
B
Q2
100P_0402_50V8J
G
S
2N7002_SOT23
4
+CRT_VCC
1
5
P
OE#
A2Y
G
SN74AHCT1G125DCKR_SC70-5
3
+CRT_VCC
2.2K2.2K
12
12
R56
2.2K_0402_5%
VGA_DDC_DAT
VGA_DDC_CLK
C9
@
U3
4
1
2
C8
@
68P_0402_50V8K
CRT_R_1
CRT_G_1
CRT_B_1
1
C16
22P_0402_50V8J
2
C
1
2
1 2
L5 FCM1608C-121T_0603
1 2
L6 FCM1608C-121T_0603
C15
22P_0402_50V8J
12
R30 1K_0402_5%
CRT_HSYNC_1
CRT_VSYNC_1
1
2
Security Classification
Issued Date
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
L2
1 2
FLM1608081R8K_0603
L3
1 2
FLM1608081R8K_0603
L4
1 2
FLM1608081R8K_0603
1
C17
22P_0402_50V8J
2
10P_0402_50V8J
2006/08/18 2007/8/18
1
C6
22P_0402_50V8J
2
1
C10
@
2
Compal Secret Data
1
C13
22P_0402_50V8J
2
1
C11
@
10P_0402_50V8J
2
Deciphered Date
1
C12
22P_0402_50V8J
2
JVGA_HS
JVGA_VS
PIN ASSIGMENT
D-SUB
PIN
1
2
3
4
5
6
7
8
9
1
6
2
7
3
8
14
10 GND
9
13
11
10
11
12
12
15
4
D
RED
GREEN
BLUE
+5VS
D1
2 1
RB411DT146_SOT23-3
RED
GREEN
BLUE
JVGA_VS
JVGA_HS
VGA_DDC_DAT
VGA_DDC_CLK
FUNCTION
W=40mils
0.1U_0402_16V4Z
+CRT_VCC
1
C5
2
+CRT_VCC
PIN4
1
C7
2
0.1U_0402_16V4Z
JP1
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
GND1
14
GND2
ACES_87213-1200G
ME@
+CRT_VCC
RED
GND
GREEN
GND
BLUE
GND
VSYNC
HSYNC
SENSE
SM_DAT
SM_CLK
PIN4
Title
Size Document Number Rev
B
Date: Sheet
Compal Electronics, Inc.
CRT & TV-OUT Connector
LA-3691P
E
19 45Thursday, March 08, 2007
0.2
of
Page 20
5
4
3
2
1
+3VS
10/17 : Change P/N from SA000010G00 to SA00001JU10
R97 8.2K_0402_5%
1 2
R96 8.2K_0402_5%
1 2
D D
C C
R281 8.2K_0402_5%
R101 8.2K_0402_5%
R111 8.2K_0402_5%
R278 8.2K_0402_5%
R297 8.2K_0402_5%
R107 8.2K_0402_5%
+3VS
R301 8.2K_0402_5%
R128 8.2K_0402_5%
R139 8.2K_0402_5%
R99 8.2K_0402_5%
R298 8.2K_0402_5%
R300 8.2K_0402_5%
R296 8.2K_0402_5%
R121 8.2K_0402_5%
R116 8.2K_0402_5%
R102 8.2K_0402_5%
R103 8.2K_0402_5%
R100 8.2K_0402_5%
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
PCI_DEVSEL#
PCI_STOP#
PCI_TRDY#
PCI_FRAME#
PCI_PLOCK#
PCI_IRDY#
PCI_SERR#
PCI_PERR#
PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#
PCI_PIRQE#
PCI_PIRQF#
PCI_PIRQG#
PCI_PIRQH#
PCI_REQ#0
PCI_REQ#1
PCI_REQ#2
PCI_REQ#3
PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#
10/17 : FootPrint : SA000010G00
BOM : SA00001JU10
U5B
D20
AD0
G16
E19
D19
A20
D17
A21
A19
C19
A18
B16
A12
E16
A14
A15
C11
D11
B12
C12
D10
F13
E11
E13
E12
A10
B6
A9
C7
D8
A6
E8
D6
A3
F9
B5
C5
PCI
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
Interrupt I/F
PIRQA#
PIRQB#
PIRQC#
PIRQD#
ICH8M REV 1.0
REQ0#
GNT0#
REQ1#/GPIO50
GNT1#/GPIO51
REQ2#/GPIO52
GNT2#/GPIO53
REQ3#/GPIO54
GNT3#/GPIO55
C/BE0#
C/BE1#
C/BE2#
C/BE3#
IRDY#
PAR
PCIRST#
DEVSEL#
PERR#
PLOCK#
SERR#
STOP#
TRDY#
FRAME#
PLTRST#
PCICLK
PME#
PIRQE#/GPIO2
PIRQF#/GPIO3
PIRQG#/GPIO4
PIRQH#/GPIO5
A4
D7
E18
C18
B19
F18
A11
C10
C17
E15
F16
E17
C8
D9
G6
D16
A7
B7
F10
C16
C9
A17
AG24
B10
G7
F8
G11
F12
B3
PCI_REQ#0
PCI_GNT#0
PCI_REQ#1
PCI_REQ#2
PCI_REQ#3
PCI_GNT#3
PCI_IRDY#
PCIRST#
PCI_DEVSEL#
PCI_PERR#
PCI_PLOCK#
PCI_SERR#
PCI_STOP#
PCI_TRDY#
PCI_FRAME#
PLT_RST#
CLK_PCI_ICH
PCI_PME#
PCI_PIRQE#
PCI_PIRQF#
PCI_PIRQG#
PCI_PIRQH#
CLK_PCI_ICH <16>
PCI_PME# <32>
Place closely pin B10
CLK_PCI_ICH
R280
10_0402_5%
@
1 2
1
C356
10P_0402_50V8J
@
2
A16 Swap Override Strap
R284 1K_0402_5%
1 2
R286 1K_0402_5%
1 2
B B
R285 1K_0402_5%
1 2
@
@
@
PCI_GNT#3
PCI_GNT#0
PCI_GNT#3
PCI_GNT#0 SPI_CS#1 Boot BIOS Loaction
0
11
A A
Low= A16 swap override Enable
High= Default*
Boot BIOS Strap
1 SPI
01
PCI
LPC*
PLT_RST#
PCIRST#
+3VS
2
B
1
A
1 2
R340 0_0402_5%
+3VS
2
B
1
A
1 2
R144 0_0402_5%
U21
5
NC7SZ08P5X_NL_SC70-5
@
P
4
Y
G
3
U8
5
NC7SZ08P5X_NL_SC70-5
@
P
4
Y
G
3
12
R370
100K_0402_5%
12
R157
100K_0402_5%
PLT_RST_BUF# <8,17,22,24,25,30>SPI_CS#1 <22>
PCI_RST# <32,34>
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2006/08/18 2007/8/18
3
Compal Secret Data
Deciphered Date
Title
Size Document Number Rev
2
Date: Sheet
Compal Electronics, Inc.
ICH8M(1/4)-PCI
LA-3691P
1
0.2
of
20 45Thursday, March 08, 2007
Page 21
5
+RTCVCC
+3VS
SM_INTRUDER#
ICH_INTVRMEN
LAN100_SLP
1 2
R362 33_0402_5%
1 2
R361 33_0402_5%
1 2
R347 33_0402_5%
1 2
R346 33_0402_5%
1 2
R365 33_0402_5%
1 2
R364 33_0402_5%
1 2
R367 33_0402_5%
1 2
R366 33_0402_5%
R353
1 2
10K_0402_5%
C436 3900P_0402_50V7K
SATA_ITX_C_DRX_N0
C435 3900P_0402_50V7K
32.768KHZ_12.5P_MC-306
+RTCVCC
HDA_SYNC_ICH
HDA_BITCLK_ICH
HDA_RST_ICH#
HDA_SDOUT_ICH
SATA_LED#
close ICH8
12
12
same as GT30
R308
20K_0402_5%
close to RAM door
SATA_DTX_C_IRX_N0<28>
SATA_DTX_C_IRX_P0<28>
SATA_ITX_DRX_P0SATA_ITX_C_DRX_P0
SATA_ITX_DRX_N0
CLK_PCIE_SATA#<16>
CLK_PCIE_SATA<16>
1 2
R315 1M_0402_5%
1 2
R314 330K_0402_1%
D D
C C
SATA_ITX_C_DRX_P0<28>
B B
High = Internal VR Enable
1 2
R316 330K_0402_1%
HDA_SYNC_AUDIO<26>
HDA_SYNC_MDC<25>
HDA_BITCLK_AUDIO<26>
HDA_BITCLK_MDC<25>
HDA_RST_AUDIO#<26>
HDA_RST_MDC#<25>
HDA_SDOUT_AUDIO<26>
HDA_SDOUT_MDC<25>
SATA_ITX_C_DRX_N0<28>
4
C441
15P_0402_50V8J
12
X2
3
NC
2
NC
15P_0402_50V8J
1 2
J5 JOPEN@
C392
1U_0603_10V4Z
1 2
+1.5VS
HDA_SDIN0<26>
HDA_SDIN1<25>
IDE_HRESET#<28>
SATA_LED#<28>
R181 24.9_0402_1%
1 2
4
OUT
1
IN
C440
12
12
1 2
R274 24.9_0402_1%
10mils width less than 500mils
ICH_RTCX1
12
R341
10M_0402_5%
ICH_RTCX2
ICH_RTCRST#
SM_INTRUDER#
ICH_INTVRMEN
LAN100_SLP
HDA_BITCLK_ICH
HDA_SYNC_ICH
HDA_RST_ICH#
HDA_SDOUT_ICH
IDE_HRESET#
SATA_LED#
SATA_DTX_C_IRX_N0
SATA_DTX_C_IRX_P0
SATA_ITX_DRX_N0
SATA_ITX_DRX_P0
SATA_DTX_C_IRX_N1
SATA_DTX_C_IRX_P1
SATA_DTX_C_IRX_N2
SATA_DTX_C_IRX_P2
CLK_PCIE_SATA#
CLK_PCIE_SATA
SATARBIAS
U5A
AG25
RTCX1
AF24
RTCX2
AF23
RTCRST#
AD22
INTRUDER#
AF25
INTVRMEN
AD21
LAN100_SLP
B24
GLAN_CLK
D22
LAN_RSTSYNC
C21
LAN_RXD0
B21
LAN_RXD1
C22
LAN_RXD2
D21
LAN_TXD0
E20
LAN_TXD1
C20
LAN_TXD2
AH21
GLAN_DOCK#/GPIO13
D25
GLAN_COMPI
C25
GLAN_COMPO
AJ16
HDA_BIT_CLK
AJ15
HDA_SYNC
AE14
HDA_RST#
AJ17
HDA_SDIN0
AH17
HDA_SDIN1
AH15
HDA_SDIN2
AD13
HDA_SDIN3
AE13
HDA_SDOUT
AE10
HDA_DOCK_EN#/GPIO33
AG14
HDA_DOCK_RST#/GPIO34
AF10
SATALED#
AF6
SATA0RXN
AF5
SATA0RXP
AH5
SATA0TXN
AH6
SATA0TXP
AG3
SATA1RXN
AG4
SATA1RXP
AJ4
SATA1TXN
AJ3
SATA1TXP
AF2
SATA2RXN
AF1
SATA2RXP
AE4
SATA2TXN
AE3
SATA2TXP
AB7
SATA_CLKN
AC6
SATA_CLKP
AG1
SATARBIAS#
AG2
SATARBIAS
ICH8M REV 1.0
<BOM Structu re>
3
FWH0/LAD0
FWH1/LAD1
FWH2/LAD2
FWH3/LAD3
FWH4/LFRAME#
LDRQ0#
LDRQ1#/GPIO23
RTCLAN / GLAN
LPCCPU
A20GATE
DPRSTP#
DPSLP#
CPUPWRGD/GPIO49
IGNNE#
STPCLK#
THRMTRIP#
IHDA
IDE
SATA
DDACK#
DDREQ
A20M#
FERR#
INIT#
INTR
RCIN#
NMI
SMI#
TP8
DD0
DD1
DD2
DD3
DD4
DD5
DD6
DD7
DD8
DD9
DD10
DD11
DD12
DD13
DD14
DD15
DA0
DA1
DA2
DCS1#
DCS3#
DIOR#
DIOW#
IDEIRQ
IORDY
E5
F5
G8
F6
C4
G9
E6
AF13
AG26
AF26
AE26
AD24
AG29
AF27
AE24
AC20
AH14
AD23
AG28
AA24
AE27
AA23
V1
U2
V3
T1
V4
T5
AB2
T6
T3
R2
T4
V6
V5
U1
V2
U6
AA4
AA1
AB3
Y6
Y5
W4
W3
Y2
Y3
Y1
W5
LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
LPC_FRAME#
LPC_DRQ0#
GATEA20
H_A20M#
R169 0_0402_5%
R161 0_0402_5%
H_FERR#
H_PWRGOOD
H_IGNNE#
H_INIT#
H_INTR
KB_RST#GLAN_COMP
H_NMI
H_SMI#
H_STPCLK#
THRMTRIP_ICH#
IDE_DD0
IDE_DD1
IDE_DD2
IDE_DD3
IDE_DD4
IDE_DD5
IDE_DD6
IDE_DD7
IDE_DD8
IDE_DD9
IDE_DD10
IDE_DD11
IDE_DD12
IDE_DD13
IDE_DD14
IDE_DD15
IDE_DA0
IDE_DA1
IDE_DA2
IDE_DCS1#
IDE_DCS3#
IDE_DIOR#
IDE_DIOW#
IDE_DDACK#
IDE_IRQ
IDE_DIORDY
IDE_DDREQ
2
LPC_AD0 <32,34>
LPC_AD1 <32,34>
LPC_AD2 <32,34>
LPC_AD3 <32,34>
LPC_FRAME# <32,34>
LPC_DRQ0# <34>
R304 10K_0402_5%
12
GATEA20 <32>
H_A20M# <4>
1 2
1 2
H_FERR# <4>
H_PWRGOOD <5>
H_IGNNE# <4>
H_INIT# <4>
H_INTR <4>
H_NMI <4>
H_SMI# <4>
H_STPCLK# <4>
R287 24.9_0402_1%
1 2
IDE_DD[0..15] <28>
IDE_DA[0..2] <28>
IDE_DCS1# <28>
IDE_DCS3# <28>
IDE_DIOR# <28>
IDE_DIOW# <28>
IDE_DDACK# <28>
IDE_IRQ <28>
IDE_DIORDY <28>
IDE_DDREQ <28>
+3VS
H_DPRSTP#DPRSTP#
H_DPSLP#D PSLP#
R349 10K_0402_5%
IDE_DIORDY
IDE_IRQ
H_DPRSTP # <5,8,45>
H_DPSLP# <5>
12
KB_RST# <32>
R291 56_0402_5%
H_THERMTRIP#
R171 4.7K_0402_5%
R324 8.2K_0402_5%
H_DPRSTP#
H_DPSLP#
H_FERR#
+3VS
12
1 2
1 2
1
R167 56_0402_5%@
R163 56_0402_5%@
R292 56_0402_5%
+VCCP
H_THERMTRIP# <4,8>
+VCCP
12
12
12
+3VS
RTC Battery
Change BATT1 P/N : SP093PA0200 (Panasonic)
1 2
R335 1K_0402_5%
1 2
Issued Date
R339 1K_0402_5%
1 2
R179 1K_0402_5%
1 2
R177
+3VS
R368
1K_0402_5%
A A
HDA_SDOUT_ICH
ICH_TP3<22>
5
@
R356
1K_0402_5%
@
XOR Chain Entr ance Strap
HDA_SDOUTICH_TP3 Description
0
0
1
0
1
0
11
RSVD
Enter XOR Chain
Normal Operation
Set PCIE port config bit 1
4
SATA_RXn/p need tie to ground when SATA port no used
Security Classification
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
SATA_DTX_C_IRX_N1
SATA_DTX_C_IRX_P1
SATA_DTX_C_IRX_N2
SATA_DTX_C_IRX_P2
1K_0402_5%
2006/08/18 2007/8/18
3
Compal Secret Data
Deciphered Date
SP093MX0000 (MAXELL)
BATT1
-+
12
ML1220T13RE
45@
+RTCBATT
R293
1 2
510_0603_1%
9/29 Checked. Same as HEL80's
2
+RTC_BATT
Title
Size Document Number Rev
B
Date: Sheet
9/29 mod ified to follow ISKAA
D15
2
1
3
BAS40-04_SOT23
+CHGRTC
1
C420
0.1U_0402_16V4Z
2
Compal Electronics, Inc.
ICH8M(2/4)-LAN,IDELPC,RTC
LA-3691P
1
21 45Thursday, March 08, 2007
+RTCVCC
0.2
of
Page 22
5
+3VS
10K_0402_5%
R351
1 2
8.2K_0402_5%
R352
1 2
8.2K_0402_5%
R322
1 2
10K_0402_5%
R360
@
1 2
D D
+3V_STB
C C
B B
@
@
@
R344
R350
R376
R354
R329
R494
R338
R328
R311
R318
R310
R312
R319
R325
R187
R345
R498
R363
R337
10K_0402_5%
1 2
10K_0402_5%
1 2
10K_0402_5%
1 2
10K_0402_5%
1 2
10K_0402_5%
1 2
10K_0402_5%
1 2
10K_0402_5%
1 2
10K_0402_5%
1 2
10K_0402_5%
1 2
10K_0402_5%
1 2
10K_0402_5%
1 2
10K_0402_5%
1 2
1K_0402_5%
1 2
8.2K_0402_5%
10K_0402_5%
1 2
10K_0402_5%
1 2
10K_0402_5%
1 2
10K_0402_5%
1 2
100K_0402_5%
1 2
Not in CRB,Keep!
+3V_STB
A A
SERIRQ
PM_CLKRUN#
EC_THERM#
PM_STP_PCI#
PM_STP_CPU#
SATA_CLKREQ#
VGA_THER_ALERT#
OCP#
GPIO48
WOL_EN
GPIO39
ICH_RI#
ICH_SMLINK0
ICH_SMLINK1
LINKALERT#
XDP_DBRESET#
ICH_PCIE_W AKE#
PM_BATLOW#
12
D_ACIN
EC_LID_OUT#
CL_RST#
PM_DPRSLPVR
ICH_VGATE
RP27
USB_OC#2
45
CPUSB#
36
USB_OC#4
27
USB_OC#5
18
10K_1206_8P4R_5%
1 2
R313 10K_0402_5%
1 2
R358 10K_0402_5%
1 2
R320 10K_0402_5%
1 2
R321 10K_0402_5%
1 2
R379 10K_0402_5%
1 2
R378 10K_0402_5%
ICH_SMBCLK<16,30>
ICH_SMBDATA<16,30>
T20
XDP_DBRESET#<4>
PM_BMBUSY#<8>
EC_LID_OUT#<32>
PM_STP_PCI#<16>
PM_STP_CPU#<16> ICH_POK <8,32>
WLAN
NEW Card
LAN
USB_OC#0
USB_OC#6
USB_OC#3
USB_OC#8
USB_OC#9
CP_PE#
EC_LID_OUT#
PM_STP_PCI#
PM_STP_CPU#
ICH_PCIE_WAKE#<24,25,30>
SERIRQ<32,34>
EC_THERM#<4,32>
VGATE<8,45>
OCP#<4>
EC_SMI#<32>
EC_SCI#<32>
SATA_CLKREQ#<16>
VGA_THER_ALERT#<17>
SB_SPKR<26>
MCH_ICH_SYNC#<8>
ICH_TP3<21>
PCIE_PTX_C_IRX_N2<24>
PCIE_PTX_C_IRX_P2<24>
PCIE_ITX_C_PRX_N2<24>
PCIE_ITX_C_PRX_P2<24>
PCIE_PTX_C_IRX_N3<25>
PCIE_PTX_C_IRX_P3<25>
PCIE_ITX_C_PRX_N3<25>
PCIE_ITX_C_PRX_P3<25>
PCIE_PTX_C_IRX_N4<30>
PCIE_PTX_C_IRX_P4<30>
PCIE_ITX_C_PRX_N4<30>
PCIE_ITX_C_PRX_P4<30>
4
+3V_STB
12
R355
2.2K_0402_5%
PAD
R336 0_0402_5%
R343 0_0402_5%
R342 0_0402_5%
C107 0.1U_0402_10V7K
C104 0.1U_0402_10V7K
C101 0.1U_0402_10V7K
C99 0.1U_0402_10V7K
C97 0.1U_0402_10V7K
C92 0.1U_0402_10V7K
12
R317
2.2K_0402_5%
ICH_SMBCLK
ICH_SMBDATA
LINKALERT#
ICH_SMLINK0
ICH_SMLINK1
ICH_RI#
SUS_STAT#
XDP_DBRESET#
PM_BMBUSY#
12
12
PM_CLKRUN#
ICH_PCIE_W AKE#
SERIRQ
EC_THERM#
OCP#
EC_SMI#
EC_SCI#
SATA_CLKREQ#
VGA_THER_ALERT#
GPIO39
GPIO48
SB_SPKR
ICH_VGATE
12
PAD
T28
12
12
12
12
12
12
SPI not used, Left NC
SPI_CS#1<20>
USB_OC#0<36>
CPUSB#<25>
USB_OC#2<36>
USB_OC#4<36>
USB_OC#5
USB_OC#6<36>
U5C
AJ26
SMBCLK
AD19
SMBDATA
AG21
LINKALERT#
AC17
SMLINK0
AE19
SMLINK1
AF17
RI#
F4
SUS_STAT#/LPCPD#
AD15
SYS_RESET#
AG12
BMBUSY#/GPIO0
AG22
SMBALERT#/GPIO11
AE20
STP_PCI#/GPIO15
AG18
STP_CPU#/GPIO25
AH11
CLKRUN#/GPIO32
AE17
WAKE#
AF12
SERIRQ
AC13
THRM#
AJ20
VRMPWRGD
AJ22
TP7
AJ8
TACH1/GPIO1
AJ9
TACH2/GPIO6
AH9
TACH3/GPIO7
AE16
GPIO8
AC19
GPIO12
AG8
TACH0/GPIO17
AH12
GPIO18
AE11
GPIO20
AG10
SCLOCK/GPIO22
AH25
QRT_STATE0/GPIO27
AD16
QRT_STATE1/GPIO28
AG13
SATACLKREQ#/GPIO35
AF9
SLOAD/GPIO38
AJ11
SDATAOUT0/GPIO39
AD10
SDATAOUT1/GPIO48
AD9
SPKR
AJ13
MCH_SYNC#
AJ21
TP3
ICH8M REV 1.0
PCIE_PTX_C_IRX_N2
PCIE_PTX_C_IRX_P2
PCIE_ITX_PRX_N2
PCIE_ITX_PRX_P2
PCIE_PTX_C_IRX_N3
PCIE_PTX_C_IRX_P3
PCIE_ITX_PRX_N3
PCIE_ITX_PRX_P3
PCIE_PTX_C_IRX_N4
PCIE_PTX_C_IRX_P4
PCIE_ITX_PRX_N4
PCIE_ITX_PRX_P4
USB_OC#0
CPUSB#
USB_OC#2
USB_OC#3
USB_OC#4
USB_OC#5
USB_OC#6
CP_PE#
USB_OC#8
USB_OC#9
M27
M26
G29
G28
AJ19
AG16
AG15
AE15
AF15
AG17
AD12
AJ18
AD14
AH18
SYS
P27
P26
N29
N28
L29
L28
K27
K26
J29
J28
H27
H26
F27
F26
E29
E28
D27
D26
C29
C28
C23
B23
E22
D23
F21
3
SATA
GPIO
SMB
Clocks
S4_STATE#/GPIO26
GPIO
DPRSLPVR/GPIO16
Power MGTController Link
GPIO
MEM_LED/GPIO24
ME_EC_ALERT/GPIO10
EC_ME_ALERT/GPIO14
MISC
U5D
PERN1
PERP1
PETN1
PETP1
PERN2
PERP2
PETN2
PETP2
PERN3
PERP3
PETN3
PETP3
PERN4
PERP4
PETN4
PETP4
PERN5
PERP5
PETN5
PETP5
PERN6/GLAN_RXN
PERP6/GLAN_RXP
PETN6/GLAN_TXN
PETP6/GLAN_TXP
SPI_CLK
SPI_CS0#
SPI_CS1#
SPI_MOSI
SPI_MISO
OC0#
OC1#/GPIO40
OC2#/GPIO41
OC3#/GPIO42
OC4#/GPIO43
OC5#/GPIO29
OC6#/GPIO30
OC7#/GPIO31
OC8#
OC9#
ICH8M REV 1.0
SATA0GP/GPIO21
SATA1GP/GPIO19
SATA2GP/GPIO36
SATA3GP/GPIO37
CLK14
CLK48
SUSCLK
SLP_S3#
SLP_S4#
SLP_S5#
PWROK
BATLOW#
PWRBTN#
LAN_RST#
RSMRST#
CK_PWRGD
CLPWROK
SLP_M#
CL_CLK0
CL_CLK1
CL_DATA0
CL_DATA1
CL_VREF0
CL_VREF1
CL_RST#
WOL_EN/GPIO9
PCI-Express
DMI_ZCOMP
DMI_IRCOMP
Direct Media Interface
SPI
USB
USBRBIAS#
DMI0RXN
DMI0RXP
DMI0TXN
DMI0TXP
DMI1RXN
DMI1RXP
DMI1TXN
DMI1TXP
DMI2RXN
DMI2RXP
DMI2TXN
DMI2TXP
DMI3RXN
DMI3RXP
DMI3TXN
DMI3TXP
DMI_CLKN
DMI_CLKP
USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4N
USBP4P
USBP5N
USBP5P
USBP6N
USBP6P
USBP7N
USBP7P
USBP8N
USBP8P
USBP9N
USBP9P
USBRBIAS
AJ12
AJ10
AF11
AG11
AG9
G5
D3
AG23
AF21
AD18
AH27
AE23
AJ14
AE21
C2
AH20
AG27
E1
E3
AJ25
F23
AE18
F22
AF19
D24
AH23
AJ23
AJ27
AJ24
AF22
AG19
CLK_ICH_14M
CLK_ICH_48M
SUS_CLK
PM_SLP_S3#
PM_SLP_S4#
PM_SLP_S5#
DPRSLPVR
PM_BATLOW#
PBTN_OUT#
R359 0_0402_5%
EC_RSMRST#R
CK_PWRGD
R290 0_0402_5%
PM_SLP_M#
CL_VREF0_ICH
CL_VREF1_ICH
WOL_EN
DMI_MTX_IRX_N0
V27
DMI_MTX_IRX_P0
V26
DMI_ITX_MRX_N0
U29
DMI_ITX_MRX_P0
U28
DMI_MTX_IRX_N1
Y27
DMI_MTX_IRX_P1
Y26
DMI_ITX_MRX_N1
W29
DMI_ITX_MRX_P1
W28
DMI_MTX_IRX_N2
AB26
DMI_MTX_IRX_P2
AB25
DMI_ITX_MRX_N2
AA29
DMI_ITX_MRX_P2
AA28
DMI_MTX_IRX_N3
AD27
DMI_MTX_IRX_P3
AD26
DMI_ITX_MRX_N3
AC29
DMI_ITX_MRX_P3
AC28
T26
T25
Y23
Y24
G3
G2
H5
H4
H2
H1
J3
J2
K5
K4
K2
K1
L3
L2
M5
M4
M2
M1
N3
N2
F2
F3
1 2
PAD
R348 100_0402_1%
CLK_PCIE_ICH#
CLK_PCIE_ICH
DMI_IRCOMP
USB20_N0
USB20_P0
USB20_N1
USB20_P1
USB20_N2
USB20_P2
USB20_N3
USB20_P3
USB20_N4
USB20_P4
USB20_N5
USB20_P5
USB20_N6
USB20_P6
USB20_N7
USB20_P7
USB20_N8
USB20_P8
USB20_N9
USB20_P9
USBRBIAS
USBRBIAS
R326 8.2K_0402_5%
+3VS
CLK_ICH_14M <16>
CLK_ICH_48M <16>
PAD
T17
PM_SLP_S3# <32>
PM_SLP_S4# <32>
PM_SLP_S5# <32>
ICH_POK
T27
12
PLT_RST_BUF#
12
1 2
R332 10K_0402_5%
12
PAD
D_ACIN
R334 100K_0402_5%
1 2
R330 10K_0402_5%@
ICH_POK
PBTN_OUT# <32>
ICH_POK
T29
CL_CLK0 <8>
CL_DATA0 <8>
CL_RST# <8>
DMI_MTX_IRX_N0 <8>
DMI_MTX_IRX_P0 <8>
DMI_ITX_MRX_N0 <8>
DMI_ITX_MRX_P0 <8>
DMI_MTX_IRX_N1 <8>
DMI_MTX_IRX_P1 <8>
DMI_ITX_MRX_N1 <8>
DMI_ITX_MRX_P1 <8>
DMI_MTX_IRX_N2 <8>
DMI_MTX_IRX_P2 <8>
DMI_ITX_MRX_N2 <8>
DMI_ITX_MRX_P2 <8>
DMI_MTX_IRX_N3 <8>
DMI_MTX_IRX_P3 <8>
DMI_ITX_MRX_N3 <8>
DMI_ITX_MRX_P3 <8>
CLK_PCIE_ICH# <16>
CLK_PCIE_ICH <16>
R309 24.9_0402_1%
1 2
USB20_N0 <36>
USB20_P0 <36>
USB20_N1 <24>
USB20_P1 <24>
USB20_N2 <36>
USB20_P2 <36>
USB20_N3
USB20_P3
USB20_N4 <36>
USB20_P4 <36>
USB20_N5 <25>
USB20_P5 <25>
USB20_N6 <36>
USB20_P6 <36>
USB20_N7 <24>
USB20_P7 <24>
USB20_N8 <29>
USB20_P8 <29>
1 2
R289
22.6_0402_1%
Within 500 mils
2
1 2
PM_DPRSLPVR <8,45>
PLT_RST_BUF# <8,17,20,24,25,30>
CK_PWRGD <16>
CL_PWROK <8>
Q13 2N7002LT1G_SOT23-3@
D
S
13
+3V_STB
G
2
Within 500 mils
+1.5VS
ACIN <32,38>
USB
WLAN
USB
USB
New Card
USB
BT
Card Reader
1
Place closely pin B2 Place closely pin AC1
CLK_ICH_48M
12
R294
@
10_0402_5%
1
C375
@
10P_0402_50V8J
2
CLK_ICH_14M
12
@
R333
10_0402_5%
1
C426
@
10P_0402_50V8J
2
CL_VREF0_ICH
C342
0.1U_0402_16V4Z
CL_VREF1_ICH
C429
@
0.1U_0402_16V4Z
+3VS
1
2
@
+3V_STB
@
1
@
2
RSMRST circuit
R421
0_0402_5%
1 2
Q30
C
EC_RSMRST#R
123
EC_RSMRST#<32>
R435
@
2.2K_0402_5%
BAV99DW-7_SOT363
@
1 2
R429
1 2
D18B
E
MMBT3906_SOT23@
B
1 2
R423 4.7K_0402_5%@
4
5
1
2
D18A
@
BAV99DW-7_SOT363
3
6
2.2K_0402_5%@
R272
3.24K_0402_1%
@
R275
453_0402_1%
@
R377
3.24K_0402_1%
R369
453_0402_1%
+3V_STB
Security Classification
Issued Date
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2006/08/18 2007/8/18
Compal Secret Data
Deciphered Date
Title
Size Document Number Rev
Custom
2
Date: Sheet
Compal Electronics, Inc.
ICH8M(3/4)-USB,GPIO,PCIE
LA-3691P
1
0.2
of
22 45Thursday, March 08, 2007
Page 23
5
+5VS
+3VS
1 2
1 2
C355
0.1U_0402_16V4Z
+3V_STB+5VALW
D14
RB751V-40TE17_SOD323-2
2
1
R277
100_0402_5%
D D
+ICH_V5REF
+RTCVCC
0.1U_0402_16V4Z
C409
1U_0603_10V4Z
C411
1
2
+ICH_V5REF
+ICH_V5REF_SUS
1mA
ALW or V
D16
1 2
L23
+1.5VS
RB751V-40TE17_SOD323-2
1 2
+ICH_V5REF_SUS
2
C373
0.1U_0402_16V4Z
1
+1.5VS_PCIE_ICH
(220UF*1, 22UF*2, 2.2UF*1)
12
1
+
C376
220U_D2_4VMR15
2
10U_0805_10V4Z
L32
1 2
MBK1608121YZF_0603
(10UF*1, 1UF*1)
close to AE7
1
C363
C384
10U_0805_10V4Z
2
+1.5VS_SATAPLL_ICH
1
C448
10U_0805_10V4Z
2
+1.5VS
C419
1U_0603_10V4Z
1
C377
2
2.2U_0805_10V6K
C437
1U_0603_10V4Z
C414
1U_0603_10V4Z
R299
10_0402_5%
+1.5VS
FBMA-L11-201209-221LMA30T_0805
VCC1_5_B ~675mA
C C
close to AC1
VCC1_5_A ~1.56A
B B
+3VS
VCCLAN3_3 ~18mA
+1.5VS
R95 1_0603_5%
VCCGLANPLL~23mA
A A
VCCGLAN1_5 ~80mA 1mA
VCCUSBPLL ~10mA
+1.5VS
1
C379
+
C382
@
0.1U_0402_16V4Z
2
220U_D2_4VMR15
close to D1
1
C372
0.1U_0402_16V4Z
+VCC_GLANPLL_R +VCC_GLANPLL_ICH
2
T19
T18
1 2
L10 MBK1608121YZF_0603
(10UF*1, 1UF*1)
+1.5VS_PCIE_ICH
(220UF*1, 1UF*1)
5
1
C374 0.1U_0402_16V4Z
2
close to F1
PAD
PAD
1
C72
10U_0805_10V4Z
2
C340
4.7U_0805_10V4Z
1
2
TP_VCCLAN1_05_ICH_1
TP_VCCLAN1_05_ICH_2
C71
2.2U_0805_10V6K
+3VS
AD25
1mA
A16
T7
G4
AA25
AA26
AA27
AB27
AB28
AB29
D28
D29
E25
E26
E27
F24
F25
G24
H23
H24
J23
J24
K24
K25
L23
L24
L25
M24
M25
N23
N24
N25
P24
P25
R24
R25
R26
R27
T23
T24
T27
T28
T29
U24
U25
V23
V24
V25
W25
Y25
AJ6
AE7
AF7
AG7
AH7
AJ7
AC1
AC2
AC3
AC4
AC5
AC10
AC9
AA5
AA6
G12
G17
H7
AC7
AD7
D1
F1
M6
M7
W23
F17
G18
F19
G20
A24
A26
A27
B26
B27
B28
B25
U5F
VCCRTC
V5REF[1]
V5REF[2]
V5REF_SUS
VCC1_5_B[01]
VCC1_5_B[02]
VCC1_5_B[03]
VCC1_5_B[04]
VCC1_5_B[05]
VCC1_5_B[06]
VCC1_5_B[07]
VCC1_5_B[08]
VCC1_5_B[09]
VCC1_5_B[10]
VCC1_5_B[11]
VCC1_5_B[12]
VCC1_5_B[13]
VCC1_5_B[14]
VCC1_5_B[15]
VCC1_5_B[16]
VCC1_5_B[17]
VCC1_5_B[18]
VCC1_5_B[19]
VCC1_5_B[20]
VCC1_5_B[21]
VCC1_5_B[22]
VCC1_5_B[23]
VCC1_5_B[24]
VCC1_5_B[25]
VCC1_5_B[26]
VCC1_5_B[27]
VCC1_5_B[28]
VCC1_5_B[29]
VCC1_5_B[30]
VCC1_5_B[31]
VCC1_5_B[32]
VCC1_5_B[33]
VCC1_5_B[34]
VCC1_5_B[35]
VCC1_5_B[36]
VCC1_5_B[37]
VCC1_5_B[38]
VCC1_5_B[39]
VCC1_5_B[40]
VCC1_5_B[41]
VCC1_5_B[42]
VCC1_5_B[43]
VCC1_5_B[44]
VCC1_5_B[45]
VCC1_5_B[46]
VCCSATAPLL
VCC1_5_A[01]
VCC1_5_A[02]
VCC1_5_A[03]
VCC1_5_A[04]
VCC1_5_A[05]
VCC1_5_A[06]
VCC1_5_A[07]
VCC1_5_A[08]
VCC1_5_A[09]
VCC1_5_A[10]
VCC1_5_A[11]
VCC1_5_A[12]
VCC1_5_A[13]
VCC1_5_A[14]
VCC1_5_A[15]
VCC1_5_A[16]
VCC1_5_A[17]
VCC1_5_A[18]
VCC1_5_A[19]
VCCUSBPLL
VCC1_5_A[20]
L6
VCC1_5_A[21]
L7
VCC1_5_A[22]
VCC1_5_A[23]
VCC1_5_A[24]
VCC1_5_A[25]
VCCLAN1_05[1]
VCCLAN1_05[2]
VCCLAN3_3[1]
VCCLAN3_3[2]
VCCGLANPLL
VCCGLAN1_5[1]
VCCGLAN1_5[2]
VCCGLAN1_5[3]
VCCGLAN1_5[4]
VCCGLAN1_5[5]
VCCGLAN3_3
ICH8M REV 1.0
4
VCCDMIPLL
VCC_DMI[1]
VCC_DMI[2]
VCC3_3[01]
VCC3_3[02]
VCC3_3[03]
VCC3_3[04]
VCC3_3[05]
VCC3_3[06]
VCC3_3[07]
VCC3_3[08]
VCC3_3[09]
VCC3_3[10]
VCC3_3[11]
VCC3_3[12]
VCC3_3[13]
VCC3_3[14]
VCC3_3[15]
VCC3_3[16]
VCC3_3[17]
VCC3_3[18]
VCC3_3[19]
VCC3_3[20]
VCC3_3[21]
VCC3_3[22]
VCC3_3[23]
VCC3_3[24]
VCCHDA
VCCCL1_05
VCCCL1_5
A13
B13
C13
C14
D14
E14
F14
G14
L11
L12
L14
L16
L17
L18
M11
M18
P11
P18
T11
T18
U11
U18
V11
V12
V14
V16
V17
V18
R29
AE28
AE29
AC23
AC24
AF29
AD2
AC8
AD8
AE8
AF8
AA3
U7
V7
W1
W6
W7
Y7
A8
B15
B18
B4
B9
C15
D13
D5
E10
E7
F11
AC12
AD11
TP_VCCSUS1_05_ICH_1
J6
TP_VCCSUS1_05_ICH_2
AF20
TP_VCCSUS1_5_ICH_1
AC16
TP_VCCSUS1_5_ICH_2
J7
VCCSUS3_3
C3
AC18
AC21
AC22
4.7U_0805_10V4Z
AG20
AH28
P6
P7
C1
N7
P1
P2
P3
P4
P5
R1
R3
R5
R6
TP_VCCCL1_05_ICH
G22
+VCCCL1_5_INT_ICH
A22
F20
G21
18mA
1
C380
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z
+1.5VS_DMIPLL_ICH
C381
10U_0805_10V4Z
C388
4.7U_0805_10V4Z
0.1U_0402_16V4Z
1
C423
0.1U_0402_16V4Z
2
close to AF29
1
C362
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z
VCCHDA~32mA
VCCSusHDA~32mA
C386
close to P6 close to AC18
+3VS
VCC1_05[01]
VCC1_05[02]
VCC1_05[03]
VCC1_05[04]
VCC1_05[05]
VCC1_05[06]
VCC1_05[07]
VCC1_05[08]
VCC1_05[09]
VCC1_05[10]
VCC1_05[11]
VCC1_05[12]
VCC1_05[13]
VCC1_05[14]
VCC1_05[15]
VCC1_05[16]
CORE
VCC1_05[17]
VCC1_05[18]
VCC1_05[19]
VCC1_05[20]
VCC1_05[21]
VCC1_05[22]
VCC1_05[23]
VCC1_05[24]
VCC1_05[25]
VCC1_05[26]
VCC1_05[27]
VCC1_05[28]
VCCA3GP ATXARX
V_CPU_IO[1]
V_CPU_IO[2]
VCCP_COREVCCPSUSVCCPUSB
IDE
PCI
VCCSUSHDA
VCCSUS1_05[1]
VCCSUS1_05[2]
VCCSUS1_5[1]
VCCSUS1_5[2]
VCCSUS3_3[01]
VCCSUS3_3[02]
VCCSUS3_3[03]
VCCSUS3_3[04]
VCCSUS3_3[05]
USB CORE
VCCSUS3_3[06]
VCCSUS3_3[07]
VCCSUS3_3[08]
VCCSUS3_3[09]
VCCSUS3_3[10]
VCCSUS3_3[11]
VCCSUS3_3[12]
VCCSUS3_3[13]
VCCSUS3_3[14]
VCCSUS3_3[15]
VCCSUS3_3[16]
VCCSUS3_3[17]
VCCSUS3_3[18]
VCCSUS3_3[19]
GLAN POWER
VCCCL3_3[1]
VCCCL3_3[2]
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
1
C391
2
1
C383
2
0.01U_0402_16V7K
1
C144
22U_0805_6.3V6M
2
1
C401
C412
0.1U_0402_16V4Z
2
close to AD2
1
C415
2
0.1U_0402_16V4Z
1
C359
C361
0.1U_0402_16V4Z
2
PAD
PAD
PAD
PAD
1
C407
2
0.1U_0402_16V4Z
PAD
T21
3
VCC1_05 ~1.13A
+VCCP
(47UF*1, 0.047UF*1, 0.022UF*1)
+1.5VS_DMIPLL_R
L21
1 2
MBK1608121YZF_0603
(10UF*1, 0.01UF*1)
+1.25VS
R295 1_0603_5%
VCCDMIPLL~23mA
+1.5VS
(22UF*1, 0.1UF*1)
VCCDMI ~50mA
+VCCP
1
2
C399
0.1U_0402_16V4Z
close to AA3
1
2
T22
T26
T25
T23
C406
0.1U_0402_16V4Z
V_CPU_IO ~1mA
(4.7UF*1, 0.1UF*2)
+3VS
1
VCC3_3 ~278mA
2
+3VS
+VCCSUS_HDA_ICH
1 2
R303 0_0805_5%
1
VCCSus3_3~177mA
2
C339
@
1U_0603_10V4Z
Add for Audio low voltage mode
+3VS
1
C405
0.1U_0402_16V4Z
2
R323
0_0603_5%
1
C416
0.1U_0402_16V4Z
2
+3V_STB
(0.1UF*1, 0.022UF*2)
1
C354
@
0.1U_0402_16V4Z
2
(0.1UF*1)
2006/08/18 2007/8/18
3
Compal Secret Data
Deciphered Date
+3V_STB
2
U5E
A23
VSS[001]
A5
VSS[002]
AA2
VSS[003]
AA7
VSS[004]
A25
VSS[005]
AB1
VSS[006]
AB24
VSS[007]
AC11
VSS[008]
AC14
VSS[009]
AC25
VSS[010]
AC26
VSS[011]
AC27
VSS[012]
AD17
VSS[013]
AD20
VSS[014]
AD28
VSS[015]
AD29
VSS[016]
AD3
VSS[017]
AD4
VSS[018]
AD6
VSS[019]
AE1
VSS[020]
AE12
VSS[021]
AE2
VSS[022]
AE22
VSS[023]
AD1
VSS[024]
AE25
VSS[025]
AE5
VSS[026]
AE6
VSS[027]
AE9
VSS[028]
AF14
VSS[029]
AF16
VSS[030]
AF18
VSS[031]
AF3
VSS[032]
AF4
VSS[033]
AG5
VSS[034]
AG6
VSS[035]
AH10
VSS[036]
AH13
VSS[037]
AH16
VSS[038]
AH19
VSS[039]
AH2
VSS[040]
AF28
VSS[041]
AH22
VSS[042]
AH24
VSS[043]
AH26
VSS[044]
AH3
VSS[045]
AH4
VSS[046]
AH8
VSS[047]
AJ5
VSS[048]
B11
VSS[049]
B14
VSS[050]
B17
VSS[051]
B2
VSS[052]
B20
VSS[053]
B22
VSS[054]
B8
VSS[055]
C24
VSS[056]
C26
VSS[057]
C27
VSS[058]
C6
VSS[059]
D12
VSS[060]
D15
VSS[061]
D18
VSS[062]
D2
VSS[063]
D4
VSS[064]
E21
VSS[065]
E24
VSS[066]
E4
VSS[067]
E9
VSS[068]
F15
VSS[069]
E23
VSS[070]
F28
VSS[071]
F29
VSS[072]
F7
VSS[073]
G1
VSS[074]
E2
VSS[075]
G10
VSS[076]
G13
VSS[077]
G19
VSS[078]
G23
VSS[079]
G25
VSS[080]
G26
VSS[081]
G27
VSS[082]
H25
VSS[083]
H28
VSS[084]
H29
VSS[085]
H3
VSS[086]
H6
VSS[087]
J1
VSS[088]
J25
VSS[089]
J26
VSS[090]
J27
VSS[091]
J4
VSS[092]
J5
VSS[093]
K23
VSS[094]
K28
VSS[095]
K29
VSS[096]
K3
VSS[097]
K6
VSS[098]
ICH8M REV 1.0
Title
Size Document Number Rev
Custom
LA-3691P
2
Date: Sheet
VSS_NCTF[01]
VSS_NCTF[02]
VSS_NCTF[03]
VSS_NCTF[04]
VSS_NCTF[05]
VSS_NCTF[06]
VSS_NCTF[07]
VSS_NCTF[08]
VSS_NCTF[09]
VSS_NCTF[10]
VSS_NCTF[11]
VSS_NCTF[12]
Compal E lectronics, Inc.
IFTXX M/B LA-3541P Schematic
VSS[099]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
VSS[159]
VSS[160]
VSS[161]
VSS[162]
VSS[163]
VSS[164]
VSS[165]
VSS[166]
VSS[167]
VSS[168]
VSS[169]
VSS[170]
VSS[171]
VSS[172]
VSS[173]
VSS[174]
VSS[175]
VSS[176]
VSS[177]
VSS[178]
VSS[179]
VSS[180]
VSS[181]
VSS[182]
VSS[183]
VSS[184]
1
K7
L1
L13
L15
L26
L27
L4
L5
M12
M13
M14
M15
M16
M17
M23
M28
M29
M3
N1
N11
N12
N13
N14
N15
N16
N17
N18
N26
N27
N4
N5
N6
P12
P13
P14
P15
P16
P17
P23
P28
P29
R11
R12
R13
R14
R15
R16
R17
R18
R28
R4
T12
T13
T14
T15
T16
T17
T2
U12
U13
U14
U15
U16
U17
U23
U26
U27
U3
U5
V13
V15
V28
V29
W2
W26
W27
Y28
Y29
Y4
AB4
AB23
AB5
AB6
AD5
U4
W24
A1
A2
A28
A29
AH1
AH29
AJ1
AJ2
AJ28
AJ29
B1
B29
1
23 45Thursday, Mar c h 08, 2007
0.2
of
Page 24
A
B
C
D
E
Mini-Express Card for 3G Or TV Tuner
Mini-Express Card for WLAN
+3VS
1
C365
4.7U_0805_10V4Z
1 1
2
1
C370
0.1U_0402_16V4Z
2
+1.5VS
1
C364
4.7U_0805_10V4Z
2
1
C369
0.1U_0402_16V4Z
2
1
C368
0.1U_0402_16V4Z
2
+3VALW
1
C367
0.1U_0402_16V4Z
2
ICH_PCIE_W AKE#<22,25,30>
WLAN_CLKREQ#<16>
2 2
3 3
ICH_PCIE_W AKE#
WLAN_CLKREQ#
BT_ACTIVE
WLAN_ACTIVE
2005/09/27 modified.
Base on OPTION GTM351E Datasheet Rev0.1
Vcc 3.3V +/- 8%
Peak Icc 2750mA
with max supply droop 50mA
Average Icc 1000mA
BT_OFF#<32>
BT_LED#<35>
R306 0_0402_5%@
R305 0_0402_5%@
CLK_PCIE_WLAN#<16>
CLK_PCIE_WLAN<16>
PCIE_PTX_C_IRX_N2<22>
PCIE_PTX_C_IRX_P2<22>
PCIE_ITX_C_PRX_N2<22>
PCIE_ITX_C_PRX_P2<22>
+5VS
12
13
2
Q7
DTC124EK_SC59
1 2
1 2
R98
10K_0402_1%
Q9
DTC114EKA_SC59-3
13
2
12
R94
10K_0402_5%
JP18
1
1
3
3
5
5
7
7
9
9
11
11
13
13
15
15
17
17
19
19
21
21
23
23
25
25
27
27
29
29
31
31
33
33
35
35
37
37
39
39
41
41
43
43
45
45
47
47
49
49
51
51
53
GND1
FOX_AS0B226-S56N-7F
ME@
GND2
2
2
4
4
6
6
8
8
10
10
12
12
14
14
16
16
18
18
20
20
22
22
24
24
26
26
28
28
30
30
32
32
34
34
36
36
38
38
40
40
42
42
(WWAN_LED#)
44
44
46
46
48
48
50
50
52
52
54
BT MODULE CONN
+3VS
USB20_N7<22>
USB20_P7<22>
D
S
13
G
2
USB20_N7
USB20_P7
BTON_LED
BT_ACTIVE
WLAN_ACTIVE
Q8
AO3413_SOT23-3
+3VS_BT
C60
0.1U_0402_16V4Z
10
MOLEX_53780-0870
WL_OFF#
PLT_RST_BUF#
WLAN_LED#
@
12
JP6
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
GND1
GND2
ME@
+3VALW
R288
1 2
100K_0402_5%
+3VS
+1.5VS
WL_OFF# <32>
PLT_RST_BUF# <8,17,20,22,25,30>
D_CK_SCLK <14,15,16,25>
D_CK_SDATA <14,15,16,25>
USB20_N1 <22>
USB20_P1 <22>
R500 0_0402_5%
@
1 2
+5VS
WLAN_LED# <35>
4 4
Security Classification
Issued Date
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
A
B
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2006/08/05 2007/08/05
Compal Secret Data
Deciphered Date
Title
Size Document Number Rev
D
Date: Sheet
Compal Electronics, Inc.
Mini-Card/3G/FeliCa/FP
LA-3691P
E
0.2
of
24 45Thursday, March 08, 2007
Page 25
A
Express Card Power Switch
+1.5VS
1 1
PLT_RST_BUF#<8,17,20,22,24,30>
+3VALW
CPUSB#<22>
2 2
12
C222 0.1U_0402_16V4Z
C223 0.1U_0402_16V4Z
C212 0.1U_0402_16V4Z
SYSON<32,37,42>
SUSP#<17,32,37,40,42,43,44>
R200 100K_0402_5%
12
12
CPUSB#
+3VS
+3VALW
12
PLT_RST#
SYSON
SUSP#
U11
12
1.5Vin
14
1.5Vin
2
3.3Vin
4
3.3Vin
AUX_IN17AUX_OUT
6
SYSRST#
20
SHDN#
1
STBY#
10
CPPE#
9
CPUSB#
18
RCLKEN
R5538_QFN20
1.5Vout
1.5Vout
3.3Vout
3.3Vout
OC#
PERST#
GND
NC
11
13
3
5
15
19
8
16
7
B
+1.5VS_CARD1
+3VS_CARD1
+3VALW_CARD1
PERST#
40mil
60mils
40mil
+1.5VS_CARD1
C202
10U_0805_10V4Z
+3VS_CARD1
C213
10U_0805_10V4Z
+3VALW_CARD1
C210
10U_0805_10V4Z
Imax = 0.75A
1
C201
0.1U_0402_16V4Z
2
Imax = 1.35A
1
C214
0.1U_0402_16V4Z
2
Imax = 0.275A
1
C211
0.1U_0402_16V4Z
2
C
D
E
New Card Socket (Left/TOP)
1
2
1
2
1
2
D_CK_SCLK<14,15,16,24>
D_CK_SDATA<14,15,16,24>
+1.5VS_CARD1
ICH_PCIE_WAKE#<22,24,30>
+3VALW_CARD1
+3VS_CARD1
EXP_CLKREQ#<16>
CLK_PCIE_EXP#<16>
CLK_PCIE_EXP<16>
PCIE_PTX_C_IRX_N3<22>
PCIE_PTX_C_IRX_P3<22>
PCIE_ITX_C_PRX_N3<22>
PCIE_ITX_C_PRX_P3<22>
USB20_N5<22>
USB20_P5<22>
CPUSB#
PERST#
CPUSB#
JP9
1
GND
2
USB_D-
3
USB_D+
4
CPUSB#
5
RSV
6
RSV
7
SMB_CLK
8
SMB_DATA
9
+1.5V
10
+1.5V
11
WAKE#
12
+3.3VAUX
13
PERST#
14
+3.3V
15
+3.3V
16
CLKREQ#
17
CPPE#
18
REFCLK-
19
REFCLK+
20
GND
21
PERn0
22
PERp0
23
GND
24
PETn0
25
PETp0
26
GND
27
GND
28
GND
FOX_1CH4110C
ME@
(NEW)
3 3
R489 0_0402_5%
1 2
@
HDA_RST_MDC#<21>
4 4
A
DAP202U_SOT323-3
+3V_STB
12
R485
10K_0402_5%
D20
2
3
HDA_SDOUT_MDC<21>
HDA_SYNC_MDC<21>
1
HDA_SDIN1<21>
R474
MDC_RST#
1 2
10K_0402_5%
AZ_SYNC
AZ_SDIN3
33_0402_5%
R475
Security Classification
Issued Date
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
B
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MDC CONN.
JP10
1
GND1
3
IAC_SDATA_OUT
5
GND2
7
IAC_SYNC
9
IAC_SDATA_IN
11
IAC_RESET#
Connector for MDC Rev1.5
2006/08/18 2007/8/18
C
IAC_BITCLK
GND13GND14GND15GND16GND17GND
18
C559 1U_0805_25V4Z
2
RES0
4
RES1
6
3.3V
8
GND3
10
GND4
12
ACES_88018-124G
ME@
Compal Secret Data
Deciphered Date
1 2
12
R481
@
10_0402_5%
1
C560
@
22P_0402_50V8J
2
D
+3V_STB
HDA_BITCLK_MDC <21>
Title
Size Document Number Rev
B
Date: Sheet
Compal Electronics, Inc.
NEW CARD & US B Connector
LA-3691P
E
of
25 45Thursday, March 08, 2007
0.2
Page 26
A
1 1
R236 560_0402_5%
1 2
BEEP#<32>
C267
@
0.1U_0402_16V4Z
SB_SPKR<22>
Window mode
1U_0603_10V4Z
C279
1
1U_0603_10V4Z
2
C273
DOS mode
12
1 2
12
560_0402_5%
10K_0402_5%
Driver initial
R227
@
R231
+VDDA
2
B
12
12
R242
10K_0402_1%
12
12
1U_0603_10V4Z
R245
10K_0402_1%
1 2
R238 20K_0402_5%
1
C
Q26
2SC2411KT146_SOT23-3
E
3
D11
RB751V_SOD323
2 1
C285
MONO_IN1 MONO_IN
R239 20K_0402_5%
ACPI
RST
2 2
EC_MUTE
DOS mode
12sec
DOS mode
RST
3 3
EC_MUTE
1 2
R463 0_0603_5%
4 4
1 2
R466 0_0603_5%
1 2
R482 0_0603_5%
12sec
CD_AGND<28>
GND GNDA
A
20K_0402_5%
+3VS
12
@
10K_0402_1%
12
@
10K_0402_1%
B
C272
470P_0402_50V7K
1 2
C271 1U_0603_10V4Z
12
1 2
INT_CD_L<28>
INT_CD_R<28>
12
R470
R214
GPIO
R217
B
+VDDA
C562
@
1U_0603_10V4Z
R468 20K_0402_5%
R469 20K_0402_5%
R479 20K_0402_5%
R478 20K_0402_5%
12
R472
20K_0402_5%
GNDA
C
12
R229
10K_0402_1%
12
R230
10K_0402_1%
1
2
13
D
EAPD
2
G
S
10mil 10mil 10mil
1
2
GNDA
+VDDA
12
12
12
12
EXT_MIC<27>
HDA_RST_AUDIO#<21>
HDA_SYNC_AUDIO<21>
HDA_SDOUT_AUDIO<21>
JACK_PLUG_MIC<27>
DOS_BEEP# <27>
10U_0805_10V4Z
C573 680P_0402_50V7K
C572 680P_0402_50V7K
Q24
2N7002_SOT23-3
@
+MIC1_VREFO_L+MIC2_VREFO +AUD_VREF
C561
@
0.1U_0402_16V4Z
L40
CHB1608U301_0603
1 2
10U_0805_10V4Z
INT_MIC<27>
CD_R_L
CD_R_R
JACK_PLUG<27>
EAPD<27,32>
1
@
1U_0603_10V4Z
2
GNDA
C569
HP_R<27>
C550 1U_0402_6.3V4Z
1 2
C558 1U_0402_6.3V4Z
1 2
C554 1U_0603_10V4Z
1 2
MIC
1 2
C563 2.2U_0603_6.3V6K
1 2
C564 2.2U_0603_6.3V6K
EAPD
GPIO
JACK_PLUG
EAPD
Security Classification
Issued Date
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
1
C265
1
2
HP_L<27>
C263
@
0.1U_0402_16V4Z
2
1
2
HP_L
HP_R
1 2
1 2
1 2
1 2
1 2
1 2
1 2
C
1
0.1U_0402_16V4Z
2
1 2
C549 4.7U_0603_6.3V6K
1 2
C552 4.7U_0603_6.3V6K
C555
0.1U_0402_16V4Z
C553 2.2U_0603_6.3V6K
C556 2.2U_0603_6.3V6K
R213 0_0402_5%@
R212 0_0402_5%
R467 20K_0402_1%
R232 39.2K_0402_1%
L37 0_0603_5%
@
1U_0603_10V4Z
C260
CD_RC_L
CD_RC_R
CD_GNDACD_GNACD_GNACD_AGND
C_MIC
MONO_IN
2006/08/04 2006/10/06
+5VS +5VAMP
L17
1 2
FBMA-L11-201209-221LMA30T_0805
L16
@
1 2
FBMA-L11-201209-221LMA30T_0805
1
1
2
GNDA
C266
C567
2
1
C264
@
0.1U_0402_16V4Z
2
+AVDD_AC97
U13
14
LINE2_L
15
LINE2_R
16
MIC2_L
17
MIC2_R
23
LINE1_L
24
LINE1_R
18
CD_L
20
CD_R
19
CD_GND
21
MIC1_L
22
MIC1_R
12
PCBEEP
11
RESET#
10
SYNC
5
SDATA_OUT
2
GPIO0
3
GPIO1
13
SENSE A
34
SENSE B
47
EAPD
48
SPDIFO
4
DVSS1
7
DVSS2
LINE_OUTL
LINE_OUTR
38
AVDD125AVDD2
10U_1206_10V4Z
+VDDC
DVDD11DVDD2
FRONT_OUT_L
FRONT_OUT_R
SURR_OUT_L
SURR_OUT_R
SIDESURR_OUT_L
SIDESURR_OUT_R
CEN_OUT
LFE_OUT
BIT_CLK
SDATA_IN
NC
NC
LINE2_VREFO
MIC1_VREFO_L
MIC1_VREFO_R
MIC2_VREFO
VREF
JDREF
NC
AVSS1
AVSS2
ALC861-VD-GR_LQFP48
Compal Secret Data
Deciphered Date
D
60mil
1
C280
2
1
C257
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
9
35
36
39
41
45
46
43
44
6
250_SDIN
8
37
29
31
10mil
28
10mil
32
30
10mil
27
40
33
26
42
D
28.7K for Module Design (VDDA = 4.702)
U15
4
VIN
2
SENSE or ADJ
DELAY
ERROR7CNOISE
8
SD
SI9182DH-AD_MSOP8
VOUT
GND
5
6
1
3
C578
0.1U_0402_16V4Z
SUB WOOFER SUPPORT
ALC262
ALC861D
1 2
R218 CHB1608U301_0603
1
1
C259
C258
2
2
10U_0805_10V4Z
C_LINE_OUTL
C_LINE_OUTR
C_HP_OUTL
C_HP_OUTR
1 2
R216 22_0402_5%@
1 2
R215 33_0402_5%
+MIC1_VREFO_L
+AUD_VREF
+MIC2_VREFO
12
C270 10U_0805_10V4Z
12
1 2
Title
Size Document Number Rev
Custom
Date: Sheet
R471 20K_0402_1%
R228 10K_0402_5%@
1 2
C262 1000P_0402_50V7K@
1 2
C261 1000P_0402_50V7K@
1 2
C566 1U_0603_10V4Z
1 2
C565 1U_0603_10V4Z
1 2
C557 1U_0603_10V4Z@
1 2
C551 1U_0603_10V4Z@
HDA_BITCLK_AUDIO
HDA_SDIN0
+VDDA
Compal Electronics, Inc.
ALC861 VD Codec
IEL10 LA-3451P
E
AC97 Codec
40mil
1
2
LINE_OUTL
LINE_OUTR
1 2
C256 22P_0402_50V8J@
(output = 250 mA)
R493
150K_0603_1%
1 2
12
R492
51K_0603_1%
+3VS
HP_L
HP_R
E
HDA_BITCLK_AUDIO <21>
HDA_SDIN0 <21>
+VDDA
4.85V
1
C278
10U_0805_10V4Z
2
LINE_OUTL <27>
LINE_OUTR <27>
of
26 45Thursday, March 08, 2007
0.2
Page 27
A
APA2057A SPK/HP Amplifier
W=40mil
1 1
fo=1/(2*3.14*R*C)=106Hz
R=1.5K / C= 1uF
LINE_OUTR<26>
LINE_OUTL<26>
9/19 Realtek suggest
Change C43/C44 from 2.2uf to 4.7uf.
HP_R<26>
HP_L<26>
DOS_BEEP#<26>
9/5 If implement AMP BEEP, Swap C155 and R79.
R79 change from 0 Ohm to 47K
2 2
1 2
R237 0_0402_5%@
1 2
R240 1.5K_0402_1%@
1 2
R253 1.5K_0402_1%@
R254 100K_0402_5%
1 2
R226 100K_0402_5%
AMP_RHPIN
AMP_LHPIN
AMP_SD#
1 2
C281
@
0.47U_0402_6.3V6K
1 2
R491 39K_0402_5%
R488 39K_0402_5%
+5VS
1 2
1 2
C269 1U_0402_6.3V4Z
C282 2.2U_0603_6.3V6K
C288 0.1U_0402_16V4Z
R247 0_0402_5%
R243 0_0402_5%
R246 0_0402_5%@
1 2
+5VS
1 2
C274
1 2
1 2
12
B
R504
0_0402_5%
C277
680P_0402_50V7K
12
AMP_CP+
AMP_CP-
AMP_BIAS
1
2
INR_A
INL_A
AMP_EN#
HP_EN
INR_H
INL_H
AMP_BEEP
+3VS
L44 BLM15BB121SN1D_0402
0.1U_0402_16V4Z
27
24
26
28
12
14
25
3
5
4
6
C275
INR_A
INL_A
/AMP EN
HP EN
INR_H
INL_H
/SD
BEEP
CP+
CPBIAS
1 2
1
2
10U_0805_10V4Z
Change
2007-02-13
Revision
2057A
APA2056_TSSOP28
11
CVDD
19
HVDD
20
PVDD
9/5 ANPEC Suggest
Place 1U cap between pin 1 and 2
2
C290
1U_0402_6.3V4Z
1
1
10
U16
VDD
PVDD
22
ROUT+
21
ROUT-
8
LOUT+
9
LOUT-
17
HP_R
18
HP_L
15
CVSS
16
VSS
2
GND
23
PGND
7
PGND
13
CGND
IN_A Gain = 10dB (Internal Speaker)
IN_H Gain = 0dB (Headphone)
SPKR+
SPKR-
SPKL+
SPKL-
HP_ROUT
HP_LOUT
CVSS
C
1
C268
1U_0402_6.3V4Z
2
Speaker
Speaker
Headphone
Headphone
D
SPKL+ SPK_L1+
SPKLSPKR+
SPKR-
R5 0_0402_5%
R4 0_0402_5%
R3 0_0402_5%
R2 0_0402_5%
20mil
Speaker Conn.
1 2
1 2
1 2
1 2
SPK_L1SPK_R1+
SPK_R1-
E
ME@
ACES_87213-0400G
4
6
4
GND
3
5
3
GND
2
2
1
1
JP2
C4 22P_0402_50V8J@
1
1
2
2
C1 22P_0402_50V8J@
C2 22P_0402_50V8J@
C3 22P_0402_50V8J@
1
1
2
2
12
R1
0_0402_5%
@
EC_MUTE#
EAPD
AMP_SD#
EC_MUTE#<32>
EAPD<26,32>
1
C585
0.1U_0402_16V4Z
2
+5VAMP
12
R509
39K_0402_5%
13
EC_MUTE#<32>
3 3
EC_MUTE#
R510 0_0402_5%
12
D
2
G
S
Q39
2N7002KW_SOT323-3
R505
100K_0402_5%
@
1 2
+MIC2_VREFO
R233 0_0402_5%@
R234 0_0402_5%@
12
12
INT MIC
INT_MIC
12
R490
3K_0402_5%
1
C574
47P_0402_50V8J
2
GNDA
INT_MIC <26>
B
End or Begain
MIC1
1
GNDA
2
WM-64PCY_2P
45@
4 4
A
AMP_SD#
+MIC1_VREFO_L
EXT MIC
Audio Jack
12
C546
@
JACK_PLUG_MIC
EXT_MIC_L-2
1
C547
@
10P_0402_50V8J
2
GNDA
1
2
GNDA
JACK_PLUG
PR-OUT
PL-OUT
1
@
10P_0402_50V8J
2
D
R465
3K_0402_5%
EXT_MIC<26>
HP_ROUT
HP_LOUT
EXT_MIC_L
1
C542
47P_0402_50V8J
2
GNDA
1 2
R476 47_0402_5%
1 2
R477 47_0402_5%
1K_0402_5%
Security Classification
Issued Date
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
JACK_PLUG_MIC<26>
12
12
R473
@
GNDA
1 2
L36 FBM-11-160808-700T_0603
JACK_PLUG<26>
1 2
L38 FBM-11-160808-700T_0603
1 2
L39 FBM-11-160808-700T_0603
R480
@
1K_0402_5%
GNDA
10P_0402_50V8J
Compal Secret Data
Deciphered Date
C548
2007/08/052006/08/05
+AUD_VREF
EXT_MIC_L-2
Title
Size Document Number Rev
Custom
Date: Sheet
JP27
1
3
5
7
9
11
15
17
ACES_88028-1210M
ME@
1
3
5
7
9
11
G113G2
G3
G5
2
2
4
4
6
6
8
8
10
12
G4
G6
JACK_PLUGJACK _PLUG_MIC
10
12
14
16
18
Compal Electronics, Inc.
AMP/VR/Audio Jack/MIC
LA-3691P
E
PL-OUT
PR-OUT
0.2
of
27 45Thursday, March 08, 2007
Page 28
A
B
C
D
E
F
G
H
Placea caps. near ODD CONN.
+5VS
1 1
2 2
1
C248
1000P_0402_50V7K
+5VS
0.1U_0402_16V4Z
2
R209 100K_0402_5%
IDE_CSEL
Grounding for Master (When use SATA HDD)
Open or Hi gh fo r Slave r (N ormal)
1
1
C247
1U_0603_10V4Z
2
2
IDE_DIOW#<21>
IDE_DIORDY<21>
IDE_DCS1#<21>
12
1
C249
10U_0805_10V4Z
2
INT_CD_L<26> INT_CD_R <26>
CD_AGND<26>
IDE_IRQ<21>
1 2
R206 470_0402_5%
1
10U_0805_10V4Z
2
IDE_RST#
IDE_DD7
IDE_DD6
IDE_DD5
IDE_DD4
IDE_DD2
IDE_DD1
IDE_DD0
IDE_DIOW#
IDE_DIORDY
IDE_IRQ
IDE_DA1
IDE_DA0
IDE_DCS1#
IDE_LED#
IDE_CSEL
C541
JP28
112
334
556
778
9910
111112
131314
151516
171718
191920
212122
232324
252526
272728
292930
313132
333334
353536
373738
393940
414142
434344
454546
474748
494950
OCTEK_CDR-50DY1G
ME@
(NEW)
C540
+5VS +5VS
+3VS
IDE_DD[0..15]<21>
IDE_DA[0..2]<21>
2
4
IDE_DD8
6
IDE_DD9
8
IDE_DD10
10
IDE_DD11
12
IDE_DD12
14
IDE_DD13IDE_DD3
16
IDE_DD14
18
IDE_DD15
20
IDE_DDREQ
22
IDE_DIOR#
24
26
IDE_DDACK#
28
30
IDE_PDIAG#
32
IDE_DA2
34
IDE_DCS3#
36
38
40
42
44
46
48
50
IDE_DD[0..15]
IDE_DA[0..2]
1 2
R210 100K_0402_5%
IDE_DDREQ <21>
IDE_DIOR# <21>
IDE_DDACK# <21>
IDE_DCS3# <21>
1000P_0402_50V7K
+5VS
+5VS +3VS
C296
1
2
C295
0.1U_0402_16V4Z
SATA_DTX_C_IRX_N0<21>
SATA_DTX_C_IRX_P0<21>
1
1
1U_0603_10V4Z
2
2
1
C299
C300
10U_0805_10V4Z
2
SATA_DTX_C_IRX_N0
SATA_DTX_C_IRX_P0
1
C302
10U_0805_10V4Z
2
SATA_ITX_C_DRX_P0<21>
SATA_ITX_C_DRX_N0<21>
1 2
C312 3900P_0402_50V7K
1 2
C311 3900P_0402_50V7K
1
C304
0.1U_0402_16V4Z
2
@
SATA_ITX_C_DRX_P0
SATA_ITX_C_DRX_N0
SATA_DTX_IRX_N0
SATA_DTX_IRX_P0
+3VS
+5VS
SATA HDD Conn.
JP14
1
GND
2
A+
3
A-
4
GND
5
B-
6
B+
7
GND
8
V33
9
V33
10
V33
11
GND
12
GND
13
GND
14
V5
15
V5
16
V5
17
GND
18
Reserved
19
GND
20
V12
21
V12
22
V12
SUYIN_127043FB022S338ZR_RV
ME@
(NEW)
Change Library
1 2
R221 0_0402_5%
3 3
D
S
12
B
1 3
@
2N7002_SOT23-3
G
2
U12
2
3
DAP202U_SOT323-3
1
Q21
DRIVE_LED#
IDE_HRESET#<21>
+5VS
4 4
A
SATA_LED#<21>
R219 100K_0402_5%@
IDE_LED#
SATA_LED#
12
R220
@
10K_0402_5%
IDE_RST#
DRIVE_LED# <33>
C
Security Classification
Issued Date
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
D
2006/08/18 2007/8/18
E
Compal Secret Data
Deciphered Date
F
Title
Size Document Number Rev
B
Date: Sheet
Compal Electronics, Inc.
HDD & ODD Connector
LA-3691P
G
of
28 45Thursday, March 08, 2007
H
0.2
Page 29
5
4
3
2
1
D D
C531
R454
RST#
MODE SEL
XTLI
XTLO
USB20_N8
USB20_P8
1 2
1
2
1 2
C580 0. 1 U_0402_16V4Z
U25
1
AV_PLL
3
A3V3
7
A3V3
9
CARD_3V3
11
D3V3
33
D3V3
8
VBUS
44
RST#
45
MODE_SEL
47
XTLI
48
XTLO
4
DM
5
DP
14
GPIO0
SD_DAT7/XD_D2/MS_D2/CF_IOWR#_SP8
SD_DAT1/XD_D3/MS_D1/CF_IORDY_SP6
2
RREF
12
DGND
32
DGND
6
AGND
46
AGND
RTS5158-GR_LQFP48_7x7
R433
0_0402_5%
1 2
C511 27P_0402_50V8J
C515 27P_0402_50V8J
0.1U_0402_16V4Z
1
2
1
2
SDPWR0_MSPWR
C532
0.1U_0402_16V4Z
Used 9701 by 10K
0_0402_5%
1 2
<BOM Structure>
USB20_N8<22>
USB20_P8<22>
R447
6.19K_0402_1%
MODE SEL
12
R436
10K_0402_5%
1
C526
1U_0603_16V4Z
R495 0_0402_5%@
+5VS
R496 0_0402_5%
+5VALW
C C
B B
2
1 2
1 2
+3VS
1 2
RST#
1
2
@
0.1U_0402_16V4Z
R437
100K_0402_5%
C514
1U_0402_6.3V4Z
C513
12
R438 0_0402_5%
VREG
CF_DMACK#
CF_CS0#
XD_CLE/CF_SP19
XD_CE#/CF_D11_SP18
XD_ALE/CF_D4_SP17
SD_DAT2/XD_RE#/CF_D12_SP16
SD_DAT3/XD_WE#/CF_D5_SP15
XD_RDY/CF_D13_SP14
SD_DAT4/XD_WP#/CF_D6_SP13
SD_DAT5/XD_D0/CF_D14_SP12
SD_CLK/XD_D1/MS_CLK/CF_D7_SP11
SD_DAT6/XD_D7/MS_D3/CF_D15_SP10
MS_INS#/CF_IORD#_SP9
SD_DAT0/XD_D6/MS_D0/CF_RST#_SP7
XD_D5/MS_BS/CF_A2_SP5
CF_A1/XD_D4_SP4
CF_A0/SD_CD#_SP3
CF_D0/SM_WPM#/XD_WP_SP2
CF_D1/XD_CD#_SP1
CF_D8/SM_CD#_SP0
CF_CD#
CF_DMARQ
CF_D10
CF_D9
CF_D2
SD_CMD
XTLI
12
Y2
12MHZ_16P_6X12000012
XTLO
10
22
30
43
42
41
40
39
38
37
35
34
31
29
28
27
26
25
23
21
20
19
18
13
24
15
16
17
36
1 2
C523 1 U_0603_16V4Z
R446 22_0402_5%
1 2
SDPWR0_MSPWR
R501
100K_0402_5%
3 in 1 Card Reader
JP26
R459
C537
6
VDD_SD
9
DAT0_SD
10
DAT1_SD
2
DAT2_SD
3
CD/DAT3_SD
7
CLK_SD
11
WP_SD
4
CMD_SD
1
CD_SD
5
VSS_SD
8
VSS_SD
19
VCC_MS
13
VCC_MS
14
SCLK_MS
16
INS_MS
18
SDIO_MS
20
BS_MS
15
RESERVED_MS
17
RESERVED_MS
21
VSS_MS
12
VSS_MS
22
GND
23
GND
PROCO_MDR019- C0- 1202
ME@
SD_DATA2
SD_DATA3
SD_MS_CLK
MS_DATA3_SD_DATA6
MSCD# SDCD#
MS_DATA2_SD_DATA7
SD_MS_DATA0
SD_MS_DATA1
MSBS
SDCD#
SDWP#
SDCMD
1 2
R497 0_0402_5%
40mil
C535
0.1U_0402_16V4Z
U26
3
VIN
VOUT
4
VIN/CE
VOUT
2
GND
RT9701-PB_SOT23-5
@
+3VS
12
1
2
@
+VCC_3IN1
1
5
12
1
C538
R462
@
2
150K_0402_5%
1U_0603_10V4Z
+VCC_3IN1
SD_MS_DATA0
SD_MS_DATA1
SD_DATA2
SD_DATA3
SD_MS_CLK
SDWP#
SDCMD
SD_MS_DATA1
SD_MS_CLK MSCLK
MSCD#
SD_MS_DATA0
MSBS
MS_DATA3_SD_DATA6
MS_DATA2_SD_DATA7
R458 22_0402_5%
1 2
@
10_0402_5%
@
10P_0402_50V8J
R457
C536
12
SDCLK
12
@
10_0402_5%
@
10P_0402_50V8J
reserved power circuit
A A
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETAR Y PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INF ORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITH OUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
3
2006/08/04 2006/10/06
Compal Secret Data
Deciphered Date
2
Title
Size D oc um ent Num ber Re v
Custom
Date: Sheet
Compal Electronics, Inc.
1394+3 in 1 Card
LA-3691P
1
29 45Thursday, March 08, 2007
of
0.2
Page 30
A
Layout Notice : Filter place as close
chip as possible.
+2.5V_LAN
4 4
+1.2V_LAN
L28 FBM-L11-160808-601LMT_0603
L27 FBM-L11-160808-601LMT_0603
3 3
L33 FBM-L11-160808-601LMT_0603
L30 FBM-L11-160808-601LMT_0603
12
L35 FBM-L11-160808-601LMT_0603
0.1U_0402_16V4Z
L31 FBM-L11-160808-601LMT_0603
0.1U_0402_16V4Z
L29 FBM-L11-160808-601LMT_0603
4.7U_0805_6.3V6K
4.7U_0805_6.3V6K
4.7U_0805_6.3V6K
4.7U_0805_6.3V6K
12
12
C439
C443
C459
C453
C488
C450
+LAN_BIASVDD
1
2
12
2
1
12
2
1
12
2
1
12
1
2
PCIE_GND
2
1
2
1
C455
0.1U_0402_16V4Z
+XTALVDD
+LAN_AVDD
2
C449
0.1U_0402_16V4Z
1
close to each of the pins 38, 45, and 52
+AVDDL
2
C451
0.1U_0402_16V4Z
1
+GPHY_PLLVDD
2
C452
0.1U_0402_16V4Z
1
+PCIE_PLLVDD
2
C470
0.1U_0402_16V4Z
1
+PCIE_VDD
2
C475
0.1U_0402_16V4Z
1
+3VALW
1 2
+VSB
R174 33K_0402_5%
EN_WOL
EN_WOL<32>
(CLKREQ#) and (ENERGY_DET) are
only supported in BCM5787M
LAN_LOW_PWR
2
Q11
2N7002_SOT23
1 2
R428 100K_0402_5%@
G
No CIS Symbol
R422 200_0603_1%
2 2
1 1
A
Y1
2
25MHZ_20P_1BG25000CK1A
C495
1
27P_0402_50V8J
12
1 2
XTALO
XTALI
2
C501
1
27P_0402_50V8J
B
L15
FBM-L11-321611-260-LMT_1206
1 2
Q12
AO3414_SOT23
D
S
1 3
G
2
1
13
D
C132
0.1U_0603_25V7K
2
S
CLK_PCIE_LAN#<16>
CLK_PCIE_LAN<16>
CLKREQ_LAN#<16>
1 2
R432 0_0402_5%@
LAN_ENERGY_DET
PCIE_ITX_C_PRX_N4<22>
PCIE_ITX_C_PRX_P4<22>
PCIE_PTX_C_IRX_N4<22>
PCIE_PTX_C_IRX_P4<22>
PLT_RST_BUF#<8,17,20,22,24,25>
ICH_PCIE_WAKE#<22,24,25>
LAN_WAKE#<32>
ICH_SMBCLK<16,22>
ICH_SMBDATA<16,22>
SMBus to support ASF
Pin16 conect to C1206 Pin1
R165
4.7K_0402_5%
LAN_WP
LAN_CLK
LAN_DATA
B
Layout Notice : Place as close
chip as possible.
C468
4.7U_0805_10V4Z
+3VS
+3VALW_VDDIO
+3VALW_VDDIO
12
12
R166
4.7K_0402_5%
LAN_CLK
1 2
R419 4.7K_0402_5%
SI
R416 4.7K_0402_5%@
CS#
1 2
R409 4.7K_0402_5%@
+3VALW_VDDIO
2
C505
1
0.1U_0402_16V4Z
1 2
R426
1 2
R371 1K_0402_5%
1 2
R380 1K_0402_5%
1 2
R398 0_0402_5%@
12
C4840.1U_0402_16V4Z
12
C4780.1U_0402_16V4Z
1 2
R427 0_0402_5%@
1 2
R431 0_0402_5%
1 2
R394 0_0402_5%@
1 2
R383 0_0402_5%@
1 2
R502 0_0402_5%@
LAN_WP
2
2
C507
C486
1
1
0.1U_0402_16V4Z
0.1U_0402_16V4Z
4.7K_0402_5%
+GPHY_PLLVDD
PCIE_MRX_C_LTX_N2
PCIE_MRX_C_LTX_P2
XTALI
XTALO
REG_GND
PCIE_GND
Pin 24 conect to C1339 Pin1
1 2
C116
0.1U_0402_16V4Z
12
U7
8
VCC
7
WP
6
SCL
5
SDA
AT24C02_SO8
1
A0
2
A1
3
NC
4
GND
Security Classification
Issued Date
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
CBE#1
C
U22
28
PCIE_REFCLK_N
29
PCIE_REFCLK_P
11
CLKREQ#
3
LOW PWR
53
VMAIN_PRSNT
54
VAUX_PRSNT
59
ENERGY_DET
35
DC
32
PCIE_RXD_N
31
PCIE_RXD_P
25
PCIE_TXD_N
26
PCIE_TXD_P
10
PERST#
12
WAKE
58
DC
57
DC
4
GPIO_0
7
GPIO_1
8
GPIO_2
9
UART_MODE
21
XTALI
22
XTALO
16
VSS
24
VSS
C
D
LAN_TX0-
41
RDN
LAN_TX0+
40
RDP
LAN_RX1-
42
TDN
LAN_RX1+
43
TDP
LAN_TX2-
48
DC
LAN_TX2+
47
DC
LAN_TX3-
49
DC
LAN_TX3+
50
DC
R425 0_0402_5%
2
LINKLED#
SPD100LED#
SERIAL_DI
TRAFFICLED#
SERIAL_DO
REGCTL12
REGCTL25
XTALVDD
PCIE_PLLVDD
PCIE_VDD
PCIE_VDD
GND
BCM5906MKMLG P12_QFN68_10x10
69
R424 0_0402_5%
1
R420 0_0402_5%@
67
66
65
SCLK
63
NC
64
SO
62
14
CTL25
18
37
RDAC
R357 1K_0402_1%
23
6
VDDIO
15
VDDIO
19
VDDIO
56
VDDIO
61
VDDIO
17
VDDP
68
VDDP
5
VDDC
13
VDDC
20
VDDC
34
VDDC
55
VDDC
60
VDDC
36
BIASVDD
30
27
33
38
DC
45
DC
52
DC
39
AVDDL
44
DC
46
DC
51
DC
CTL12
+LAN_BIASVDD
2006/08/04 2006/10/06
LAN_TX0- <31>
LAN_TX0+ <31>
LAN_RX1- <31>
LAN_RX1+ <31>
1 2
1 2
1 2
LAN_CLK
SI
LAN_DATA
CS#
12
+XTALVDD
+3VALW_VDDIO
+2.5V_LAN
+1.2V_LAN
+PCIE_PLLVDD
+PCIE_VDD
+LAN_AVDD
+AVDDL
Compal Secret Data
Deciphered Date
LINKLED# <31>
ACTIVITY# <31>
D
Layout Notice : 1.2V filter. Place as close
chip as possible.
+1.2V_LAN
2
2
C456
1
4.7U_0805_6.3V6K
CTL12
MMJT9435T1G_SOT223
2
C503
C502
1
0.1U_0402_16V4Z
+3VALW_VDDIO
Q33
1
CTL25
MBT35200MT1G_TSOP6
2
C506
1
1
0.1U_0402_16V4Z
0.1U_0402_16V4Z
C516 0.1U_0402_16V4Z
C512 4.7U_0603_6.3V6K
2 3
4
C510
0.1U_0402_16V4Z
+3VALW_VDDIO
Q31
+2.5V_LAN
Notice : 4.7u 6. 3V c apa cto r T hic kness 1.25mm
Layout Notice : Filter place as close
chip as possible.
Layout Notice : Place as close
chip as possible.
C504
Compal Electronics, Inc.
Title
BCM5787M-GLAN
Size Document Number Rev
Custom
IEL20 LA-3471P
Thursday, March 08, 2007
Date: Sheet
E
2
2
C481
0.1U_0402_16V4Z
C460
C461
1
1
0.1U_0402_16V4Z
0.1U_0402_16V4Z
Place closed to L14 & K14
1 2
1 2
+1.2V_LAN
1
2
REG_GND
1
10U_0805_10V4Z
2
1 2
C508
0.1U_0402_16V4Z
4.7uF
41
3
256
+2.5V_LAN
0.1U_0402_16V4Z
C496
C498
2
1
1
2
10U_0805_10V4Z
2
1
Close to U87
E
2
1
C509
0.1U_0402_16V4Z
2
C476
1
0.1U_0402_16V4Z
30 45
C457
2
1
0.1U_0402_16V4Z
0.2
of
Page 31
5
+2.5V_LAN
12
D D
C413 0.1U_0402_16V4Z
1 2
C428 0.1U_0402_16V4Z
1 2
R331
0_0402_5%
LAN_TX0+<30>
LAN_TX0-<30>
LAN_RX1+<30>
LAN_RX1-<30>
LAN_TX0+
LAN_TX0-
LAN_RX1+
LAN_RX1-
TCT
TCT
Change C468,C470,C473,C474,C475,C476 from 0.01uF to 0.1uF
LAN_RX1-
R373 49.9_0402_1%
LAN_RX1+
R372 49.9_0402_1%
C C
LAN_TX0-
R374 49.9_0402_1%
LAN_TX0+
R375 49.9_0402_1%
12
12
12
12
C446
1 2
C447
1 2
near LAN controller
4
1
2
3
4
5
6
7
0.1U_0402_16V4Z
0.1U_0402_16V4Z
T24
RD+
RX+
RD-
RX-
CT
CT
NC
NC
NC
NC
CT
CT
TD+
TX+
TD-8TX-
350uH_NS0013LF
3
2
1
Lan Conn.
MDO0+
16
MDO0-
15
MCT0
14
13
12
MCT1
11
MDO1+
10
MDO1-
9
R175
12
75_0402_5%
R178
12
75_0402_5%
+3VALW_VDDIO
RJ45_PR
C169 220P_0402_50V7K@
1 2
ACTIVITY#<30>
C151 1000P_1206_2KV7K
1 2
ACTIVITY#
LINKLED#<30>
LINKLED#
12
C125 68P_0402_50V8K
1 2
R170 300_0402_5%
10mil
10mil
1 2
R183 300_0402_5%
+3VALW_VDDIO
12
C160 68P_0402_50V8K
C123 220P_0402_50V7K@
1 2
MDO3MDO3+
MDO1MDO2MDO2+
MDO1+
MDO0MDO0+
JP21
12
Amber LED-
11
Amber LED+
8
PR4-
7
PR4+
6
PR2-
5
PR3-
4
PR3+
3
PR2+
2
PR1-
1
PR1+
10
Green LED-
9
Green LED+
TYCO_2-1734819-5
SHLD4
SHLD3
SHLD2
SHLD1
16
15
14
13
B B
A A
Security Classification
Issued Date
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2006/08/04 2006/10/06
Compal Secret Data
Deciphered Date
Title
Size Document Number Rev
Custom
2
Date: Sheet
Compal Electronics, Inc.
LAN CONTROLLER
LA-3691P
1
0.2
of
31 45Thursday, March 08, 2007
Page 32
L8
+3VALW +EC_AVCC
+3V_STB
LAN_WAKE#<30>
PCI_PME#<20>
+3VALW
+5VALW
+3VS
1 2
FBM-11-160808-601-T_0603
0.1U_0402_16V4Z
1 2
L7 FBM-11-160808-601-T_0603
1 2
KB_RST#<21>
1 2
R20 100K_0402_1%@
1 2
R18 100K_0402_1%@
1 2
R41 10K_0402_5%@
1 2
R48 4.7K_0402_5%
1 2
R44 4.7K_0402_5%
1 2
R49 4.7K_0402_5%
1 2
R43 4.7K_0402_5%
R29 10K_0402_5%@
12
C35 22P_0402_50V8J@
+3VALW
1 2
R46 0_0402_5%
1 2
R507 0_0402_5%@
S
+3V_STB
FRD#SPI_SO
FSEL#SPICS#
KSO17
EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2
100P_0402_50V8J@
2
C44
1
ECAGND
1 2
R59 47K_0402_5%
0.1U_0402_16V4Z
D
13
Q1
@
G
2N7002_SOT23
2
1
C36
2
1
C46
1000P_0402_50V7K
2
2 1
D6 RB751V_SOD323
12
R38 10_0402_5%@
2
C57
1
KSO[0..15]<34>
KSI[0..7]<33,34>
+3VALW
R47
10K_0402_5%
1 2
EC_PME#
XCLKI
1 2
R25 20M_0603_5%@
C20
15P_0402_50V8J
1
2
1
2
32.768KHZ_12.5P_1TJS125BJ2A251
X1
C37
100P_0402_50V8J@
+3VALW
0.1U_0402_16V4Z
0.1U_0402_16V4Z
SERIRQ<22,34>
KSI1<34>
KSO16<33>
KSI2<33,34>
KSO17<33>
0.1U_0402_16V4Z
C22
C21
1
1
2
2
LPC_AD3
LPC_AD2
LPC_AD1 BATT_TEMP
LPC_AD0
EC_RST#
EC_SCI#
PM_CLKRUN#
KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7
KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15
KSO16
KSO17
EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2
PM_SLP_S3#
PM_SLP_S5#
EC_SMI#
LID_SW#
SUSP#
PBTN_OUT#
EC_THERM#
FAN_SPEED1
EC_TX_P80_DATA
EC_RX_P80_CLK
XCLKI
XCLKO
C23
1
2
GATEA20<21>
LPC_FRAME#<21,34>
LPC_AD3<21,34>
LPC_AD2<21,34>
LPC_AD1<21,34>
LPC_AD0<21,34>
CLK_PCI_LPC<16>
PCI_RST#<20,34>
EC_SCI#<22>
KSO[0..15]
KSI[0..7]
EC_SMB_CK1<39>
EC_SMB_DA1<39>
EC_SMB_CK2<4>
EC_SMB_DA2<4>
PM_SLP_S3#<22>
PM_SLP_S5#<22>
EC_SMI#<22>
LID_SW#<33>
SUSP#<17,25,37,40,42,43,44>
PBTN_OUT#<22>
EC_THERM#<4,22>
FAN_SPEED1<4>
EC_TX_P80_DATA<14,15,34>
EC_RX_P80_CLK<14,15,34>
ON/OFF#<33>
PWR_LED#<35>
NUM_LED#<33>
XCLKO
C19
4
IN
OUT
NC3NC
15P_0402_50V8J
0.1U_0402_16V4Z
C25
1
2
1
2
3
4
5
7
8
10
12
13
37
20
38
55
56
57
58
59
60
61
62
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
81
82
77
78
79
80
6
14
15
16
17
18
19
25
28
29
30
31
32
34
36
122
123
1000P_0402_50V7K
1000P_0402_50V7K
C40
C48
1
1
2
2
U1
GA20/GPIO00
KBRST#/GPIO01
SERIRQ#
LFRAME#
LAD3
LAD2
LAD1
LPC & MISC
LAD0
PCICLK
PCIRST#/GPIO05
ECRST#
SCI#/GPIO0E
CLKRUN#/GPIO1D
KSI0/GPIO30
KSI1/GPIO31
KSI2/GPIO32
KSI3/GPIO33
KSI4/GPIO34
KSI5/GPIO35
KSI6/GPIO36
KSI7/GPIO37
KSO0/GPIO20
KSO1/GPIO21
KSO2/GPIO22
KSO3/GPIO23
KSO4/GPIO24
Int. K/B
KSO5/GPIO25
Matrix
KSO6/GPIO26
KSO7/GPIO27
KSO8/GPIO28
KSO9/GPIO29
KSO10/GPIO2A
KSO11/GPIO2B
KSO12/GPIO2C
KSO13/GPIO2D
KSO14/GPIO2E
KSO15/GPIO2F
KSO16/GPIO48
KSO17/GPIO49
SCL1/GPIO44
SDA1/GPIO45
SCL2/GPIO46
SDA2/GPIO47
PM_SLP_S3#/GPIO04
PM_SLP_S5#/GPIO07
EC_SMI#/GPIO08
LID_SW#/GPIO0A
SUSP#/GPIO0B
PBTN_OUT#/GPIO0C
EC_PME#/GPIO0D
EC_THERM#/GPIO11
FAN_SPEED1/FANFB1/GPIO14
FANFB2/GPIO15
EC_TX/GPIO16
EC_RX/GPIO17
ON_OFF/GPIO18
PWR_LED#/GPIO19
NUMLED#/GPIO1A
XCLK1
XCLK0
KB926QFA1_LQFP128
SM Bus
+EC_AVCC
1 2
9
22
33
96
111
125
67
VCC
VCC
VCC
VCC
VCC
VCC
AVCC
INVT_PWM/PWM1/GPIO0F
BEEP#/PWM2/GPIO10
FANPWM1/GPIO12
ACOFF/FANPWM2/GPIO13
PWM Output
BATT_TEMP/AD0/GPIO38
BATT_OVP/AD1/GPIO39
ADP_I/AD2/GPIO3A
AD Input
DA Output
PS2 Interface
SPI Device Interface
SPI Flash ROM
GPIO
GPO
GPIO
GPI
GND
GND
GND
GND
GND
11
24
35
94
113
AD3/GPIO3B
AD4/GPIO42
SELIO2#/AD5/GPIO43
DAC_BRIG/DA0/GPIO3C
EN_DFAN1/DA1/GPIO3D
IREF/DA2/GPIO3E
DA3/GPIO3F
PSCLK1/GPIO4A
PSDAT1/GPIO4B
PSCLK2/GPIO4C
PSDAT2/GPIO4D
TP_CLK/PSCLK3/GPIO4E
TP_DATA/PSDAT3/GPIO4F
SDICS#/GPXOA00
SDICLK/GPXOA01
SDIDO/GPXOA02
SDIDI/GPXID0
SPIDI/RD#
SPIDO/WR#
SPICLK/GPIO58
SPICS#
CIR_RX/GPIO40
CIR_RLC_TX/GPIO41
FSTCHG/SELIO#/GPIO50
BATT_CHGI_LED#/GPIO52
CAPS_LED#/GPIO53
BATT_LOW_LED#/GPIO54
SUSP_LED#/GPIO55
SYSON/GPIO56
VR_ON/XCLK32K/GPIO57
AC_IN/GPIO59
EC_RSMRST#/GPXO03
EC_LID_OUT#/GPXO04
EC_ON/GPXO05
EC_SWI#/GPXO06
ICH_PWROK/GPXO06
BKOFF#/GPXO08
WL_OFF#/GPXO09
GPXO10
GPXO11
PM_SLP_S4#/GPXID1
ENBKL/GPXID2
GPXID3
GPXID4
GPXID5
GPXID6
GPXID7
V18R
AGND
69
ECAGND
ECAGND
TP_CLK
1 2
R36 4.7K_0402_5%
TP_DATA
1 2
R34 4.7K_0402_5%
Security Classification
Issued Date
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
INVT_PWM
21
BEEP#
23
26
ACOFF
27
63
BATT_OVP
64
65
BRD_ID
66
SKU_ID
75
UMA_DES
76
DAC_BRIG
68
EN_FAN1
70
IREF
71
72
83
84
85
86
TP_CLK
87
TP_DATA
88
97
98
99
109
R23 10K_0402_5%
FRD#SPI_SO
119
FWR#SPI_SI
120
SPI_CLK
126
FSEL#SPICS#
128
73
R52 10K_0402_5%
74
89
CHARGE_LED0#
90
CAPS_LED#
91
CHARGE_LED1#
92
93
95
121
127
100
EC_LID_OUT#
101
102
103
104
105
106
107
108
110
112
114
115
116
R21 10K_0402_5%
117
BATT_IN
118
no used at B-test
124
2006/08/04 2006/10/06
R506 10K_0402_5%
12
12
SYSON
EC_ON
BKOFF#
12
+5VS
10P_0402_25V8K
USB_ON
INVT_PWM <18>
BEEP# <26>
EN_WOL <30>
ACOFF <38,40>
BATT_TEMP <39>
BATT_OVP <40>
ADP_I <40>
DAC_BRIG <18>
EN_FAN1 <4>
IREF <40>
EC_MUTE#
EC_MUTE# <27>
USB_ON <36>
TP_CLK <34>
TP_DATA <34>
BT_OFF# <24>
+3VALW
+3VALW
FSTCHG <40>
CHARGE_LED0# <35>
CAPS_LED# <33>
CHARGE_LED1# <35>
NOVO# <33>
SYSON <25,37,42>
VR_ON <45>
ACIN <22,38>
EC_RSMRST# <22>
EC_LID_OUT# <22>
EC_ON <33>
BKOFF# <18>
WL_OFF# <24>
SCROLL_LED# <33>
PM_SLP_S4# <22>
ENBKL <18>
EAPD <26,27>
KILL_SW# <36>
STB <37>
BATT_IN
C292
@
KB925 SPI STRAP PIN
R26 4.7K_0402_5%
1 2
RB751V_SOD323
D5
1 2
R16 0_0402_5%
@
+3VALW
12
R256 15_0402_5%@
Compal Secret Data
Deciphered Date
1 2
R40 10K_0402_5%@
ID
0
1
2
3
4
5
6
7
0.1U_0402_16V4Z
FSEL#SPICS#
SPI_CLK
UMA_DES
IHL00/IGT30 UMA
IHL00V2/V3 UMA
IHL00V2/V3 VGA
IHL00/IGT30 VGA
ICH_POKICH_POK_EC
21
1 2
R22 10K_0402_5%
+3VALW
1
C293
2
R259 15_0402_5%
R19 15_0402_5%
R257 15_0402_5%
SPI_CLK_R
12
+3VALW
+3VALW
3.30V
2.20V
0.25V
ICH_POK <8,22>
+3VS
+5VALW
EC_SMB_CK1
EC_SMB_DA1
Analog Board ID definition,
Please see page 3.
+3VALW+3VALW
R50
@
100K_0402_1%
1 2
SKU_ID
1
C41
@
R51
2
1 2
Vab
56K_0402_5%
0.1U_0402_16V4Z
ID
I
I
0
H
H
L
L
1
0
0
0
0
2
V
0V
2
3
3
I
4
G
T
5
3
0
6
C59
0.1U_0402_16V4Z
1 2
U4
8
VCC
7
WP
6
SCL
5
SDA
AT24C16AN-10SU-2.7_SO8
R57
100K_0402_1%
1 2
BRD_ID
1
R54
C47
2
1 2
8.2K_0402_5%
BRD ID
R01 (EVT)
R02 (DVT)
R03 (PVT)
R10A (MP)
R01 (EVT)
R02 (DVT)
R03 (PVT)
R10A (MP)7
Vab
0.1U_0402_16V4Z
R57/45(Ra)=100K Ohm
8M SPI ROM
20mils
SPI_CS#
12
SPI_CLK_R
12
SPI_SIFWR#SPI_SI FRD#SPI_SO
12
SPI_CS#
SPI_SO
U18
8
VCC
3
W
7
HOLD
1
S
6
C
5
D
SST25LF080A_SO8-200mil
Title
Size Document Number Rev
Custom
Date: Sheet
4
VSS
SPI_SO
2
Q
JP11
112
334
556
778
E&T_2941-G08N-00E~D
ME@
2
4
6
8
R260 15_0402_5%
SPI_CLK_R
SPI_SI
Compal Electronics, Inc.
BIOS & EC I/O Port
IGT30 LA-3571P
12
+3VALW
+5VALW
12
1
A0
2
A1
3
A2
4
GND
12
+3VALW
R45
GM@
100K_0402_1%
1 2
UMA_DES
R42
PM@
56K_0402_5%
1 2
R54/42(Rb) Vab
0
8.2K
18K
33K
56K
100K
200K
NC
of
32 45Thursday, March 08, 2007
R65
100K_0402_1%
R63
100K_0402_1%
0V
0.25V
0.50V
0.82V
1.19V
1.65V
2.20V
3.30V
0.2
Page 33
ON/OFF switch
ON/OFFBTN#
EC_ON<32>
Power Button
SW1
3
4
SMT1-05_4P
5
6
12
12
+3VALW
12
R258
4.7K_0402_5%
1 2
R511 33K_0402_5%
13
D
2
G
Q27
S
2N7002_SOT23
J1 JOPEN@
J3 JOPEN@
Bottom Side
ON/OFFBTN#
EC_ON
1
2
TOP Side
D12
1
DAN202UT106_SC70-3
2
+3VALW
2
3
R255
100K_0402_5%
1 2
ON/OFF#
51_ON#
Q40
DTC124EK_SC59
13
ON/OFF# <32>
C291
1000P_0402_50V7K
ACES_88716-1601-01
4477101013
1
6
223355889911111212141415151616GND17GND
1
6
KSO16<32>
KSI0<32,34>
KSO17<32>
KSI2<32,34>
2
3
DAN202U_SC70
+5VALW
+5VS
DRIVE_LED#
CAPS_LED#
NUM_LED#
NOVO_BTN#
SCROLL_LED#
ON/OFFBTN#
NOVO_BTN#
MUTE# MUTE# KSI0 & KSO16
USER# KSI2 & KSO17
D4
1
Switch Board Conn.
+5VALW
+3VALW
51_ON# <38>
2
1
12
D13
RLZ20A_LL34
NOVO#<32>
51_ON#<38>
1 2
R11 0_0402_5%
1 2
R10 0_0402_5%@
100K_0402_5%
NOVO#
51_ON#
R15
SCROLL_LED#<32>
+3VALW
DRIVE_LED#<28>
CAPS_LED#<32>
NUM_LED#<32>
1 2
JP4
13
18
+3VALW
Lid Switch
1 2
R241 0_0402_5%
C289
0.1U_0402_16V4Z
+VCC_LID
1
2
R244 100K_0402_5%
1 2
2
A3212ELHLT-T_SOT23W-3
VDD
3
OUTPUT
GND
U14
1
2
C276
10P_0402_50V8J
1
LID_SW# <32>
Security Classification
Issued Date
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2006/08/18 2007/8/18
Compal Secret Data
Deciphered Date
Title
Size Document Number Rev
B
Date: Sheet
Compal Electronics, Inc.
BIOS, I/O Port & K/B Connector
LA-3691P
33 45Thursday, March 08, 2007
of
0.2
Page 34
5
4
3
2
1
D D
C C
KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7
KSO0
KSO1
KSO2
KSO3
KSI[0..7]
KSO[0..15]
C65 100P_0402_50V8J@
C73 100P_0402_50V8J@
C63 100P_0402_50V8J@
C78 100P_0402_50V8J@
C76 100P_0402_50V8J@
C62 100P_0402_50V8J@
C75 100P_0402_50V8J@
C74 100P_0402_50V8J@
C77 100P_0402_50V8J@
C79 100P_0402_50V8J@
C80 100P_0402_50V8J@
C68 100P_0402_50V8J@
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
KSI[0..7] <32,33>
KSO[0..15] <32>
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15
C66 100P_0402_50V8J@
1 2
C64 100P_0402_50V8J@
1 2
C82 100P_0402_50V8J@
1 2
C81 100P_0402_50V8J@
1 2
C67 100P_0402_50V8J@
1 2
C61 100P_0402_50V8J@
1 2
C85 100P_0402_50V8J@
1 2
C70 100P_0402_50V8J@
1 2
C83 100P_0402_50V8J@
1 2
C69 100P_0402_50V8J@
1 2
C84 100P_0402_50V8J@
1 2
C86 100P_0402_50V8J@
1 2
INT_KBD Conn.
For IHL00
KSI1
KSI7
KSI6
KSO9
KSI4
KSI5
KSO0
KSI2
KSI3
KSO5
KSO1
KSI0
KSO2
KSO4
KSO7
KSO8
KSO6
KSO3
KSO12
KSO13
KSO14
KSO11
KSO10
KSO15
ME@
ACES_85202-24051
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
20
21
21
22
22
23
23
24
24
25
G1
26
G2
JP7
To TP/B Conn.
JP8
+5VS
TP_DATA<32>
TP_CLK<32>
TP_DATA
TP_CLK
+5VS
C117
0.1U_0402_16V4Z
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
ACES_87151-0807G
ME@
TP_DATA
TP_CLK
2
3
D10
@
PSOT24C_SOT23
1
Update Footprint
FOR LPC SIO DEBUG PORT
JP13
1
B B
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
20
ACES_85201-2005
ME@
+5VS
LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
LPC_FRAME#
LPC_DRQ0#
PCI_RST#
CLK_PCI_DB
SERIRQ
+3VS
CLK_14M_SIO <16>
LPC_AD0 <21,32>
LPC_AD1 <21,32>
LPC_AD2 <21,32>
LPC_AD3 <21,32>
LPC_FRAME# <21,32>
LPC_DRQ0# <21>
PCI_RST# <20,32>
CLK_PCI_DB <16>
SERIRQ <22,32>
R265 10K_0402_5%
12
EC DEBUG PORT
JP12
+3VALW
EC_TX_P80_DATA<14,15,32>
EC_RX_P80_CLK<14,15,32>
EC_TX_P80_DATA
EC_RX_P80_CLK
1
1
2
2
3
3
4
4
ACES_85205-0400
ME@
A A
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2006/08/18 2007/8/18
3
Compal Secret Data
Deciphered Date
Title
Size Document Number Rev
B
2
Date: Sheet
Compal Electronics, Inc.
EC ENE KB910L(Reserved)
LA-3691P
34 45Thursday, March 08, 2007
1
0.2
of
Page 35
LED
+5VALW
+3VALW
+5VALW
+3VS
+5VS
A
B
LED3
HT-191NB_BLUE_0603
Amber
Blue
PWR_LED# <32>
CHARGE_LED1# <32>
CHARGE_LED0# <32>
1 2
R249 300_0402_5%
1 2
R248 300_0402_5%
1 2
R250 300_0402_5%
4 3
2 1
2 1
LED1
HT-297UD/ C B _ B L U E/ A M B _0603
Blue&Amber
LED2
1 2
R252 300_0402_5%
1 2
R251 300_0402_5%
4 3
2 1
HT-297UD/ C B _ B L U E/ A M B _0603
Security Classification
Issued Date
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Amber
A
Blue
B
2006/08/18 2007/8/18
BT_LED# <24>
WLAN_LED# <24>
Compal Secret Data
Deciphered Date
Title
Size Document Number Rev
B
Date: Sheet
Compal Electronics, Inc.
MDC/CIR & LED
LA-3691P
of
35 45Thursday, March 08, 2007
0.2
Page 36
A
B
C
D
E
USB Conn.
W=80mils
ME@
Kill SWITCH
1 1
D2
@
+USB_VCCC
+USB_VCCC
1
+
150U_D2_6.3VM
2
C497
1
C499
470P_0402_50V7K
2
+USB_VCCC
+USB_VCCC
1
470P_0402_50V7K
2
C18
DAN217_SC59
+3VALW
3
1
2
KILL_SW#
+3VS
R7
100K_0402_5%
1 2
KILL_SW# <32>
ACES_87213-1000G
12
GND2
11
GND1
10
10
9
9
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
JP5
+USB_VCCC
KILL_SW#
USB20_P4
USB20_N4
USB20_P2
USB20_N2
W=80mils
USB20_P4 <22>
USB20_N4 <22>
USB20_P2 <22>
USB20_N2 <22>
2 2
4.7U_0805_10V4Z
3 3
C527 0.1U_0402_16V4Z
+5VALW
1
C301
2
USB_ON<32>
+5VALW
12
USB_ON<32>
USB_ON
U17
1
GND
2
IN
3
IN
4
EN#
G545A1P1U_SO8
U24
1
GND
2
IN
3
IN
4
EN#
G545A1P1U_SO8
OUT
OUT
OUT
OC#
OUT
OUT
OUT
OC#
+USB_VCCC
8
7
6
5
+USB_VCCA
8
7
6
5
1
C294
0.1U_0402_16V4Z
2
@
1
C500
1000P_0402_50V7K@
2
USB_OC#4 <22>
USB_OC#2 <22>
USB_OC#6 <22>
USB_OC#0 <22>
D17
@
6
CH3
+USB_VCCA
USB20_P6 USB20_N0
5
Vp
4
CH4
CM1293-04SO_SOT23-6
CH2
CH1
3
2
Vn
1
USB20_N6
USB CONN. 1
+USB_VCCA
+USB_VCCAUSB20_P0
1
+
C462
150U_D2_6.3VM
2
USB20_N0<22>
USB20_P0<22>
USB CONN. 2
USB20_N6<22>
USB20_P6<22>
W=80mils
1
C473
470P_0402_50V7K
2
USB20_N0
USB20_P0
+USB_VCCA
1
C528
470P_0402_50V7K
2
W=80mils
USB20_N6
USB20_P6
JP22
1
VCC
2
D-
3
D+
4
GND
5
GND1
6
GND2
7
GND3
8
GND4
SUYIN_020173MR004G579ZR
ME@
JP24
1
VCC
2
D-
3
D+
4
GND
5
GND1
6
GND2
7
GND3
8
GND4
SUYIN_020173MR004G579ZR
ME@
4 4
Security Classification
Issued Date
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
A
B
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2006/08/18 2007/8/18
Compal Secret Data
Deciphered Date
Title
Size Document Number Rev
B
D
Date: Sheet
Compal Electronics, Inc.
Power OK, R eset and RTC Circuit, TP
LA-3691P
E
of
36 45Thursday, March 08, 2007
0.2
Page 37
A
B
C
D
E
C571
10U_0805_10V4Z
SUSP
2N7002_SOT23
1
2
Q37
STB<32>
+5VALW TO +5VS
+5VALW
U28
D
D
D
D
AO4468_SO8
5VS_GATE
D
S
STB
1
S
2
S
3
S
4
G
2
G
8
7
6
5
13
2
G
+5VS
1
1
C579
C575
10U_0805_10V4Z
1
C568
0.1U_0603_25V7K
2
+VSB
12
R464
33K_0402_5%
13
D
Q36
2N7002_SOT23-3
S
+1.5VS +2.5VS +VCCP +1.8V+0.9VS
R235
470_0603_5%
1 2
13
D
G
Q25
S
2N7002_SOT23
2
2
1U_0603_10V4Z
C539
10U_0805_10V4Z
SUSP SUSP SUSP SUSP SYSON#
2
R484
470_0603_5%
1 2
13
D
SUSP
2
G
Q38
S
2N7002_SOT23
+3VALW to +3V Transfer
+3VALW +3V_STB
1
2
1
C544
0.1U_0603_25V7K
2
R137
470_0603_5%
1 2
13
D
S
U27
8
D
7
D
6
D
5
D
AO4468_SO8@
Q35 AOS3414
D
1 3
2
G
Q10
2N7002_SOT23
J4
@
PAD-OPEN 3x3m
1 2
1
S
2
S
3
S
4
G
S
G
2
D
S
+VSB
R262
470_0603_5%
1 2
13
2
G
Q28
2N7002_SOT23
1
C583
10U_0805_10V4Z
2
1 2
R202
47K_0402_5%
SUSP
2N7002_SOT23
+3VALW TO +3VS
+3VALW
1
C584
2
10U_0805_10V4Z
2
Q18
G
0.1U_0402_16V4Z
1
1
C543
C545
2
2
R211
470_0603_5%
1 2
13
D
Q20
S
2N7002_SOT23
8
7
6
5
2
G
U10
D
D
D
D
AO4468_SO8
13
D
S
10U_0805_10V4Z
S
S
S
G
1
2
3
C581
4
10U_0805_10V4Z
1
2
D
S
1
C582
2
1U_0603_10V4Z
C209
0.1U_0603_25V7K
R191
470_0603_5%
1 2
13
2
G
Q16
2N7002_SOT23
+3VS
1
2
D
S
R203
470_0603_5%
1 2
13
2
G
Q19
2N7002_SOT23
SUSP
+1.25VS
D
S
R185
470_0603_5%
1 2
13
2
G
Q14
2N7002_SOT23
SUSP
1
C190
PM@
10U_0805_10V4Z
2
+VSB
R192
33K_0402_5%
SUSP
+1.8V to +1.8VS
+1.8V
8
7
6
5
1
C191
PM@
10U_0805_10V4Z
Q15
2N7002_SOT23
PM@
PM@
2
2
SYSON<25,32,42>
SUSP<44>
SUSP#<17,25,32,40,42,43,44>
G
AO4468_SO8
1.8VS_GATE
13
D
S
SYSON#
100K_0402_5%
100K_0402_5%
+1.8VS
PM@
U9
1
S
D
2
S
D
D
D
SYSON
R224
SUSP
R222
3
S
4
G
SYSON#
12
RTCVREF
1 2
12
C184
PM@
10U_0805_10V4Z
1
C189
PM@
0.1U_0603_25V7K
2
+5VALW
2
G
+5VALW
R508
10K_0402_5%
@
2
G
1 2
13
D
S
1 2
13
D
S
1
C185
PM@
2
1U_0603_10V4Z
R225
100K_0402_5%
Q23
2N7002_SOT23
R223
100K_0402_5%
Q22
2N7002_SOT23
1
2
R193
PM@
470_0603_5%
1 2
13
D
S
SUSP
2
G
Q17
PM@
2N7002_SOT23
1 1
1
C577
10U_0805_10V4Z
2
+VSB
R483
33K_0402_5%
2 2
3 3
4 4
Security Classification
Issued Date
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
A
B
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2006/08/18 2007/8/18
Compal Secret Data
Deciphered Date
Title
Size Document Number Rev
B
D
Date: Sheet
Compal Electronics, Inc.
DC Interface
LA-3691P
E
0.2
of
37 45Thursday, March 08, 2007
Page 38
A
DC030005Q00
PJP1
1
1
2
2
3
1 1
2 2
3
4
4
JST_B4B-EH-A(LF)(SN)
12
PC6
1000P_0402_50V7K
VIN
12
PR10
12
PR15
PR13
84.5K_0402_1%
22K_0402_1%
1 2
20K_0402_1%
ADPIN
12
PC1
1000P_0402_50V7K
PR4
10K_0402_1% @
1 2
PR6
1M_0402_1%
1 2
VS
8
3
P
+
12
PC7
0.1U_0402_16V7K
2
-
4
PR17
10K_0402_1%
O
G
PU1A
LM393DG_SO8
12
PL11
FBMA-L11-322513-201LMA40T_1210
1 2
12
PC2
PC5
0.01U_0402_25V7K@
1 2
1
RTCVREF
100P_0402_50V8J
3.3V
12
VS
12
PR11
12
PD3
GLZ4.3B_LL34-2
PC3
100P_0402_50V8J
10K_0402_1%
12
PC4
1000P_0402_50V7K
12
PR16
10K_0402_1%
B
VIN
12
PR1
10_1206_5%
@
12
PD1
RLZ24B_LL34
@
PR12
10K_0402_1%
1 2
PACIN
ACIN <22,32>
PACIN <40>
Vin Detector
High 18.764 17.901 17.063
Low 17.745 16.9 16.03
C
ACIN
Precharge detector
Min. typ. Max.
H-->L 14.589V 14.84V 15.243V
L-->H 15.562V 15.97V 16.388V
PR2
1K_1206_5%
1 2
ACOFF<32,40>
PR3
1K_1206_5%
1 2
PR5
1K_1206_5%
1 2
PR7
1K_1206_5%
1 2
VIN
PD2
12
LL4148_LL34-2
D
BATT ONLY
Precharge detector
Min. typ. Max.
H-->L 6.138V 6.214V 6.359V
L-->H 7.196V 7.349V 7.505V
12
12
PR9
PR8
13
2
100K_0402_5%
100K_0402_5%
PQ2
DTC115EUA_SC70-3
2
TP0610K-T1-E3_SOT23-3
13
2
12
PR14
100K_0402_5%
13
PQ3
DTC115EUA_SC70-3
PQ1
B+
VIN
VL
PD4
LL4148_LL34-2
PD5
12
RB751V-40_SOD323-2
PR29
22K_0402_1%
1 2
+1.8V
+0.9VS
+2.5VS
12
PR26
100K_0402_5%
12
PC10
2
0.22U_1206_25V7K
PQ4
TP0610K-T1-E3_SOT23-3
+VCCPP
(16A,800mils ,Via NO.= 24)
Security Classification
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SE CRET INFOR MATI ON. THIS SHEET MAY NOT BE TRANSF ERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
B
12
51_ON#<33>
PJ3
PAD-OPEN 3x3m
BATT+
CHGRTCP
3.3V
RTCVREF
PR24
PR23
560_0603_5%
1 2
3 3
+CHGRTC
560_0603_5%
1 2
PJ2
PAD-OPEN 3x3m
12
PC8
21
G920AT24U_SOT89-3
PU2
3
OUT
4.7U_0805_6.3V6K
+1.5VS+1.5VSP
GND
PR25
200_0805_5%
2
IN
1
+1.8VP
12
PC9
1U_0805_25V4Z
1 2
(7A,280mils ,Via NO.=14) (8A,320mils ,Via NO.= 16)
PJ5
PAD-OPEN 3x3m
+5VALWP
1 2
(6A,240mils ,Via NO.= 12)
4 4
+3VALWP
PJ7
PAD-OPEN 3x3m
1 2
(6A,240mils ,Via NO.=12)
PJ9
PAD-OPEN 3x3m
+1.25VP +1.25VS
1 2
(6A,240mils ,Via NO.=12)
+5VALW
+3VALW
A
+0.9VSP
(2A,80mils ,Via NO.= 4)
+2.5VSP
(1A,40mils ,Via NO.= 2)
+VSBP +VSB
(0.3A,40mils ,Via NO.= 2)
PJ6
PAD-OPEN 3x3m
1 2
PJ8
112
JUMP_43X79
PJ10
PAD-OPEN 3x3m
1 2
2
12
PR20
68_1206_5%
13
PJ4
PAD-OPEN 3x3m
1 2
Issued Date
1 2
12
PR21
12
VS
68_1206_5%
PC11
0.1U_0603_25V7K
12
PR22
PD6
MAINPWON<39,41>
ACON<40>
2
3
BAS40CW_SOT323-3
1
12
RTCVREF
+VCCP
2005/10/17 2006/10/17
Compal Secret Data
Deciphered Date
C
100K_0402_1%
LM393DG_SO8
PC12
0.1U_0603_25V7K
7
O
PU1B
PR30
34K_0402_1%
PR18
2.2M_0402_5%
VS
8
5
P
+
6
-
G
4
12
12
12
12
PR19
499K_0402_1%
PR31
47K_0402_1%
PQ6
DTC115EUA_SC70-3
2
D
12
PR28
499K_0402_1%
12
12
PC14
38 45Thursday, March 08, 2007
0.01U_0402_25V7K
PACIN <40>
+5VALWP
of
12
PR27
12
PR32
@
D
PQ5
S
66.5K_0402_1%
PRG++
13
191K_0402_1%
2N7002W-T/R7_SOT323-3
2
G
13
Compal Electronics, Inc.
DCIN/DECTOR
IHL00 LA-3691P
PC13
1000P_0402_50V7K
Title
Size Document Number Rev
B
Date: Sheet
0.2
Page 39
A
DC040003600
PJP2
1
2
3
4
5
6
1 1
2 2
3 3
7
8
9
G1
G2
SUYIN_200275MR009G180ZR
SPOK<41>
1
2
3
4
5
6
7
8
9
10
11
VL
PR49
1 2
100K_0402_5%
1 2
BATT++
ID
B/I
SMC
SMD
TS
GND
PR50
0_0402_5%
1 2
12
PR40
100_0402_1%
12
PR41
100_0402_1%
1 2
PR35
1 2
PR34
100K_0402_5%@
1K_0402_1%
+3VALWP
PR36
1 2
1K_0402_5%
PR33
100K_0402_5%
1 2
PR44
12
PR47
100K_0402_5%
6.49K_0402_1%
12
PC21
0.22U_1206_25V7K
PQ7
TP0610K-T1-E3_SOT23-3
2
12
PR45
1K_0402_1%
B+
PR48
22K_0402_1%
1 2
13
D
PQ8
2
G
2N7002W-T/R7_SOT323-3
S
12
PC23
B
BATT++
+3VALWP
12
PC15
1000P_0603_50V7K
ALI/MH# <40>
EC_SMB_CK1 <32>
EC_SMB_DA1 <32>
+3VALWP
13
+VSBP
PL12
HCB4532KF-800T90_1812
1 2
12
PC16
1000P_0603_50V7K
BATT_TEMP <32>
BATT+
12
PC17
0.01U_0603_50V7K
C
D
PH1 under CPU botten side :
CPU thermal protection at 87 degree C
Recovery at 70 degree C
VL
12
PR37
12
12
PC19
1000P_0402_50V7K
10.5K_0402_1%
PR42
69.8K_0603_1%
1 2
PH1
12
100K_0603_1%_TH11-4H104FT
12
TM_REF1
PC20
PC18
1U_0603_6.3V6M
12
0.1U_0603_25V7K
3
2
PR43
150K_0402_1%
PR46
150K_0402_1%
VS
8
P
+
-
G
4
PR39
442K_0603_1%
1 2
1
O
PU3A
LM393DG_SO8
12
VL
VL
PR38
1 2
150K_0402_1%
MAINPWON <38,41>
12
PC22
0.1U_0603_25V7K
5
6
VS
8
P
+
-
G
LM393DG_SO8
4
7
O
PU3B
0.1U_0402_16V7K
4 4
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SE CRET INFOR MATI ON. THIS SHEET MAY NOT BE TRANSF ERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
B
2005/10/17 2006/10/17
Compal Secret Data
Deciphered Date
C
Title
Size Document Number Rev
B
Date: Sheet
Compal Electronics, Inc.
BATTERY CONN. / OTP
IHL00 LA-3691P
D
39 45Thursday, March 08, 2007
of
0.2
Page 40
A
65W, Iadapter=0~3.42A, Current sense=0.02ohm, PR70=39.2K, CP=3.079A
90W, Iadapter=0~4.74A, Current Sense=0.015ohm, PR70=28.7K, CP=4.263A
PQ9
AO4407_SO8
2
13
PQ13
DTC115EUA_SC70-3
22K_0402_1%
PACIN
1 2
ACON
8
7
5
PR66
1 3
PQ12
DTA144EUA_SC70-3
2
4
150K_0402_1%
13
VIN
1 1
12
PR52
47K_0402_1%
2
13
D
PQ16
2
2N7002W-T/R7_SOT323-3
G
S
2 2
3 3
PACIN<38>
ACON<38>
ACOFF<32,38>
Be careful the
P2
1
2
36
12
12
PR53
200K_0402_1%
PC28
0.1U_0603_25V7K
12
PR60
13
D
PQ18
2
G
S
PQ20
DTC115EUA_SC70-3
PQ10
AO4407_SO8
1
2
3 6
4
FSTCHG<32>
680P_0402_50V7K@
2N7002W-T/R7_SOT323-3
IREF<32>
PC34
CSON
1 2
6800P_0402_25V7K
0.01U_0402_25V7K
PR67
143K_0402_1%
PR69
100K_0402_1%
8
7
5
1 2
PC29
5600P_0402_25V7K
1SS355_SOD323-2
PD8
1 2
PR57
10K_0402_5%
PC36
1 2
PC37
12
12
PC44
12
PR63
1 2
10K_0402_1%
1 2
12
0.01U_0402_25V7K
P3
CSIP CSIN
VIN
PR208
100K_0402_1%
12
PR59
100K_0402_1%
1 2
ADP_I<32>
0.1U_0402_16V7K
6251VREF
IREF voltage!!
6251VREF
12
CP mode
Iinput=(1/0.02)(0.05*Vaclm/2.39+0.05)
where Vaclm=0.5535V, Iinput=3.079A
PR74
100K_0402_1%@
2
where Vaclm=0.6667V, Iinput=4.263A
CC=0.6~3.4A
VCHLM=0.24V~1.36V
If this area float, Charge voltage is 4.2V/cell
CHGSEL
IREF=0.972*Icharge
IREF=0.5832V~3.3V
4 4
BATT Type
2800mAH 3S pack
Normal 3S LI-ON Cells
Charging Voltage
(0x15)
13050mV
12600mV
A
CHGSEL
CV mode
LOW 12.90V
HIGH
12.60V
B
1
2
PR51
0.02_2512_1%
TP0610K-T1-E3_SOT23-3
12
6251VDD
PC31
2.2U_0603_6.3V6K
6251_EN
12
PC156
0.1U_0402_16V7K
100P_0402_50V8J
PC39
PC40
1 2
39.2K_0402_1%
PR70
1 2
10K_0402_1%
PR72
1 2
13
274K_0402_1%@
PQ21
SI2301BDS-T1-E3_SOT23-3@
B
4
3
PQ42
2
100_0402_1%
1 2
12
PR73
CSON
13
12
CELLS
PR64
6251VREF
C
ADP_I = 19.9*Iadapter*Rsense
B+
PJ12
2
112
JUMP_43X118
6251DC_IN
12
PC30
0.1U_0603_25V7K
1 2
PR209
100K_0402_1%
PU4
1
2
3
4
5
6
7
8
9
10
11
12
ISL6251AHAZ-T_QSOP24
12
PC157
0.01U_0402_25V7K
VDD
ACSET
EN
CELLS
ICOMP
VCOMP
ICM
VREF
CHLIM
ACLIM
VADJ
GND
DCIN
ACPRN
CSON
CSOP
CSIN
CSIP
PHASE
UGATE
BOOT
VDDP
LGATE
PGND
6251VREF
12
PR210
100K_0402_1%
12
PR211
20K_0402_1%
BATT_OVP<32>
PQ43
13
DTC115EUA_SC70-3
2
6251DC_IN
24
23
22
21
1 2
20
19
1 2
LX_CHG
18
DH_CHG
17
BST_CHG
16
6251VDDP
15
DL_CHG
14
13
6251_EN
C
PQ44
2
B
E
2SC2411KT146_SOT23-3
3 1
@
PD16
2
1
3
BAS40CW_SOT323-3
PC32
0.1U_0603_25V7K
12
BATT+
PR219
20_0603_5%
1 2
PC35
0.047U_0603_25V7M
1 2
PR61 20_0603_5%
PC38
PR62 20_0603_5%
0.1U_0603_25V7K
1 2
PR220
2.2_0603_5%
PR68
1 2
2.2_0603_5%
PC45
1 2
4.7U_0805_6.3V6K
PR77
10K_0402_1%
1 2
12
PC47
@
0.01U_0402_25V7K
FSTCHG
12
BST_CHGA
12
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
CHG_B+
12
PC24
10U_1206_25V6M
SUSP# <17,25,32,37,42,43,44>
CSON
CSOP
CSIN
CSIP
PD10
1 2
4.7_0603_5%
PR71
1
0.1U_0603_25V7K
6251VDD
8
P
0
G
4
RB751V-40_SOD323-2
Compal Secret Data
Deciphered Date
C
12
PC25
10U_1206_25V6M
12
PC41
VS
12
PU5A
3
+
2
-
LM358ADR_SO8
PC26
0.1U_0603_25V7K
PC46
0.01U_0402_25V7K
12
PC27
2200P_0402_50V7K
BATT+
12
12
12
12
5
D8D7D6D
S1S2S3G
4
5
D8D7D6D
S1S2S3G
4
PR75
340K_0402_1%
PR76
499K_0402_1%
PR78
105K_0402_1%
2007/05/182006/05/18
PQ11
AO4407_SO8
1
2
3 6
4
PR55
10K_0402_1%
1 2
13
PQ14
DTC115EUA_SC70-3
PQ17
SI4800BDY-T1-E3_SO8
PL1
10U_LF919AS-100M-P3_4.5A_20%
1 2
PQ19
SI4800BDY-T1-E3_SO8
ALI/MH#<39>
12
PC48
0.01U_0402_25V7K
D
8
7
5
PR54
47K_0402_1%
2
CSOP
1 2
PR58
47K_0402_5%
1 2
PD7
1 2
1SS355_SOD323-2
PD9
1 2
1SS355_SOD323-2
CHG
1
2
2
12
PC33
0.1U_0603_25V7K
PR65
0.02_2512_1%
13
VIN
ACOFF <32,38>
200K_0402_1%
PR56
1 2
2N7002W-T/R7_SOT323-3
13
D
PQ15
2
G
S
4
CSON
3
CELLS6251VDD
PQ45
DTC115EUA_SC70-3
VIN
PACIN <38>
12
12
PC42
10U_1206_25V6M
BATT+
PC43
10U_1206_25V6M
OVP voltage :
LI-3S :13.50V--BATT-OVP=1.5V
BATT-OVP=0.111*BATT+
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
CHARGER
IHL00 LA-3691P
D
40 45Thursday, March 08, 2007
of
0.2
Page 41
A
B+
2
PJ13
2
JUMP_43X118
1
1
1 1
B+++
PC49
0.1U_0402_16V7K
1 2
<BOM Structu re>
5
12
PC51
10U_1206_25V6M
D8D7D6D
S1S2S3G
PQ22
4
5HG
5
PR83
0_0603_5%
SI4800BDY-T1-E3_SO8
1 2
DH5
LX5
D8D7D6D
S1S2S3G
PQ24
4
SI4810BDY-T1-E3_SO8
DL5
2 2
+5VALWP
1
+
PC59
2
150U_D2_6.3VM
+5V Ipeak = 6.66A ~ 10A
3 3
PL2
<BOM Structu re>
1 2
10UH_1164AY-100M=P3_4.7A_20%
PR90
1 2
10.5K_0402_1%
PR92
1 2
6.81K_0402_1%
VS
PZD1
1 2
GLZ5.1B_LL34-2
PR93
47K_0402_1%
1 2
PR96
1 2
100K_0402_5%
12
PC60
0.047U_0603_16V7K
B
1 2
PR98
47K_0402_1%
1 2
PR79
0_0603_5%
BST5A
1 2
1 2
12
PC64
PR91
0_0402_5%
8734_VREF
PR94
0_0402_5%
0.047U_0603_16V7K
3
PD11
1
BAW56W_SOT323-3
VL
12
PC56
4.7U_0805_6.3V6K
14
BST5
16
DH5
15
LX5
19
DL5
21
OUT5
9
FB5
1
N.C.
MAX8734AEEI+_QSOP28
6
SHDN#
4
ON5
3
ON3
12
SKIP#
8
REF
12
PC61
0.22U_0603_16V7K
2
12
12
B+++
PR80
4.7_1206_5%
PC55
18
LD05
23
GND
1U_0805_25V4Z
20
PU7
C
PC50
1 2
0.1U_0402_16V7K
1 2
B+++
PR84
0_0603_5%
BST3A
DH3
12
12
PC54
PC53
2200P_0402_50V7K
10U_1206_25V6M
PR87
0_0603_5%
1 2
3HG
LX3
DL3
1 2
BST3BBST5B
VL
PR82
1 2
4.7_1206_5%
47_0402_5%
12
PC52
0.1U_0402_16V7K
12
PR81
@
8734_VREF
12
25
0.1U_0603_25V7K
13
LDO3
TON
17
ILIM3
VCC
ILIM5
BST3
DH3
DL3
OUT3
FB3
PGOOD
PRO#
10
LX3
12
PC57
5
11
28
26
24
27
22
7
2
PC58
V+
12
PC63
PR97
0_0402_5%
4.7U_0805_6.3V6K
1 2
1U_0805_16V7K
SPOK<39>
PR85
1 2
200K_0402_1%
PR88
1 2
499K_0402_1%
PR86
1 2
200K_0402_1%
PR89
1 2
499K_0402_1%
1 2
VFB=2V
5
4
5
4
PR95
6.81K_0402_1%
PR99
10K_0402_1%
D
D8D7D6D
PQ23
S1S2S3G
SI4800BDY-T1-E3_SO8
D8D7D6D
PQ25
S1S2S3G
SI4810BDY-T1-E3_SO8
PL3
1 2
10UH_1164AY-100M=P3_4.7A_20%
+3VALWP
1
+
PC62
2
330U_D3L_6.3VM_R25M
+3.3V Ipeak = 6.66A ~ 10A
MAINPWON <38,39>
12
PC65
1U_0603_6.3V6M
4 4
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SE CRET INFOR MATI ON. THIS SHEET MAY NOT BE TRANSF ERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
B
2005/10/17 2006/10/17
Compal Secret Data
Deciphered Date
C
Title
Size Document Number Rev
Custom
Date: Sheet
Compal Electronics, Inc.
+5VALWP/+3VALWP
IHL00 LA-3691P
D
41 45Thursday, March 08, 2007
of
0.2
Page 42
5
+5VALW
4
3
2
1
D D
B+
PJ14
112
JUMP_43X118
Maximum continuous current=>6A
+1.8VP
Vout_1.8V
C C
1
+
PC85
2
220U_D2_4VY_R15M
Close to IC Side
Differential routing of feedback
to VSSA1 and VOUT1 PIN
B B
B+_1.8/1.05
2
12
PC87
PC86
4.7U_1206_25V6K
1.8UH_1164AY-1R8N=P3_9.5A_30%
12
PR122
26.1K_0402_1%
12
PR121
10K_0402_1%
4.7U_1206_25V6K
1 2
12
PC89
33P_0402_50V8K
FB_1.8V
PGOOD2_1.05V
12
PC83
2.2U_0603_6.3V6K
12
PL5
D8D7D6D
S1S2S3G
D8D7D6D
S1S2S3G
5
4
DH_1.8V-1
5
4
PQ28
SI4800BDY-T1-E3_SO8
PR119
0_0402_5%
1 2
PQ29
SI4810BDY-T1-E3_SO8
SUSP#<17,25,32,37,40,43,44>
+5VALW
12
PR113
100K_0402_5%
@
PR103
0_0402_5%
1 2
12
PR110
10_0603_5%
VCCA_1.05V
12
PC90
1U_0603_10V6K
B+_1.8/1.05
1000P_0402_50V7K
0.1U_0603_25V7K
1M_0402_5%
12
@
0.1U_0402_16V7K
PC82
1 2
PR116
PC70
12
PC68
12
PR101
10_0603_5%
VCCA_1.8V
12
PC91
1U_0603_10V6K
DL_1.8V
PC80
1 2
1U_0603_10V6K
1 2
PR114 27.4K_0402_1%
DH_1.8V
PR115
1 2
0_0402_5%
Vout_1.05V
12
VCCA_1.05V
+5VALW
ILIM_1.8V
LX_1.8V
BST_1.8V
FB_1.05V
PU8
1
PGND1
2
DL1
3
VDDP1
4
ILIM1
5
LX1
6
DH1
7
BST1
8
EN/PSV2
9
TON2
10
VOUT2
11
VCCA2
12
FB2
13
PGD2
14
VSSA2
SC413TSTRT_TSSOP28
VFB=0.5V
2
EN/PSV1
1
BAW56W_SOT323-3
3
VSSA1
PGD1
FB1
VCCA1
VOUT1
TON1
BST2
DH2
LX2
ILIM2
VDDP2
DL2
PGND2
PD12
28
27
26
25
24
23
22
21
20
19
18
17
16
15
FB_1.8V
VCCA_1.8V
Vout_1.8V
BST_1.05V
DH_1.05V
LX_1.05V
ILIM_1.05V
+5VALW
DL_1.05V
SYSON<25,32,37>
BST_1.05V-1BST_1.8V-1
PR108
1 2
0_0402_5%
PR109
1 2
34K_0402_1%
12
PC84
1000P_0402_50V7K
1 2
820K_0402_5%
PC72
1 2
0.1U_0603_25V7K
PC78
1U_0603_10V6K
0_0402_5%
PR112
PR124
1 2
B+_1.8/1.05
12
0_0402_5%
1 2
SI4810BDY-T1-E3_SO8
12
12
PR100
100K_0402_5%
@
SI4800BDY-T1-E3_SO8
PQ26
PR102
DH_1.05V-1
PQ27
PC170
@
0.1U_0402_16V7K
PGOOD1_1.8V
B+_1.8/1.05
4.7U_1206_25V6K
Maximum continuous current=>6A
330U_D2_2V_Y
+VCCPP
1
+
PC71
2
330U_D2_2V_Y
12
PR106
12
Vout_1.05V
1
+
11.5K_0402_1%
2
PC69
@
5
D8D7D6D
S1S2S3G
4
5
4
PL4
1.8UH_1164AY-1R8N=P3_9.5A_30%
1 2
D8D7D6D
33P_0402_50V8K
S1S2S3G
PC66
12
4.7U_1206_25V6K
PC74
FB_1.05V
12
12
PR107
10K_0402_1%
PC67
Close to IC Side
Differential routing of feedback to VSSA2 and VOUT2 PIN
VFB=0.5V
VFB=0.5V
Vo=VFB*(1+PR122/PR127)=1.805V
Ipeak=12.17A, Imax=8.519A
Ton=(3.3E-12*(PR121+37K)*(Vout/VBat))+50ns
=3.3*10e-12*(820K+37K)*(1.8/19)+50ns=0.3179us
FDS6670AS:Rds(on)=>Typ:9 mOhm
Max:11.5 mOhm
Iocp=Ivalley+ Iripple
/2
Iripple=(vin-vout)*(Ton/L)=5.467A, 1/2 Iripple=2.734A.
A A
Ivalleymin=10E-6*(PR120/Rds(ON)max*1.5)
=9*10e-6*(27.4K/0.0115*1.5)=14.295A>11.73*1.2=14.076A
Vo=VFB*(1+PR129/PR130)=1.5V
Ipeak=5.16A, Imax=3.612A
Ton=(3.3E-12*(PR125+37K)*(Vout/VBat))+50ns
=0.3201us
AO4916 Rds(on)=>Typ:21 mOhm
Max:27 mOhm
Ivalleymin=9*10u*(29.4K/0.027*1.4)=7A
Ivalleymax=11*E-6*(29.4K/0.021*1.1)=12.833A
Iripple=(vin-vout)*(Ton/L)=2.546A, 1/2Iriiple=1.273A
Iocp=Ivalley+ Iripple
/2
OCP==>8.273A~14.106A
Ivalleymax=10E-6*(PR120/Rds(ON)typ*1.2)
=11*10e-6*(27.4K/0.009*1.2)=27.907A.
OCP==>17.029A~30.641A
5
4
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2005/10/17 2006/10/17
3
Compal Secret Data
Deciphered Date
2
Compal Electronics, Inc.
Title
Size Document Number Rev
Custom
Date: Sheet
VCCPP/1.8VP
Thursday, March 08, 2007
IHL00 LA-3691P
1
42 45
of
0.2
Page 43
5
4
3
2
1
+5VALW
12
EN/PSV
14
NC
PGND7DL
PC97
2.2U_0603_6.3V6K
13
BST
DH
LX
ILIM
VDDP
8
12
11
10
9
PR212
0_0402_5%
D D
C C
SUSP#<17,25,32,37,40,42,44>
1 2
12
@
0.1U_0402_16V7K
PGOOD2_1.5V
PC163
+5VALW
B+_1.5VSP
12
PR214
100K_0402_5%
PR213
1M_0402_5%
12
PC164
1000P_0402_50V7K
Vout_1.5V
VCCA_1.5V
FB_1.5V
SC411MLTRT_MLPQ16_4X4
VFB=0.5V
12
15
16
TON
1
VOUT
2
VCCA
3
FB
4
PGD
NC5VSSA
TP
PU9
6
17
12
PR127
10_0603_5%
VCCA_1.5V
12
PC99
BST_1.5V
DH_1.5V
LX_1.5V Vout_1.5V
ILIM_1.5V
+5VALW
DL_1.5V
12
1U_0603_10V6K
PR126
1 2
0_0603_5%
PR128
1 2
26.1K_0402_1%
PC108
1U_0603_10V6K
PD14
1SS355_SOD323-2
1 2
BST_1.5V-1
PC100
1 2
0.1U_0603_25V7K
SI4810BDY-T1-E3_SO8
PQ31
5
D8D7D6D
PQ30
S1S2S3G
SI4800BDY-T1-E3_SO8
4
1.8UH_1164AY-1R8N=P3_9.5A_30%
5
D8D7D6D
S1S2S3G
4
PC111
4.7U_1206_25V6K
PL6
1 2
33P_0402_50V8K
FB_1.5V
B+_1.5VSP
12
12
PC93
12
PC101
PR133
10K_0402_1%
4.7U_1206_25V6K
Maximum continuous current=>6A
12
PR132
30K_0402_1%
12
PJ15
112
JUMP_43X118
1
+
PC96
2
470U_D2_2.5VM
2
+1.5VSP
B+
Close to IC Side
Differential routing of feedback to VSSA2 and VOUT2 PIN
VFB=0.5V, Ipeak=14.02A, Imax=9.814A
The current rating of +1.05VSP include +VCC_GFX current.
Vo=VFB*(1+PR146/PR147)=1.05V
Ipeak=2.91A, Imax=2A.
Vo=0.8*(1+PR190/PR191)=1.2608V
+5VS
Ton=(3.3E-12*(PR142+37K)*(Vout/VBat))+50ns=0.2391us
SI4810BDY:Rds(on)=>Typ:9mOhm
Max:11.5 mOhm
Ivalleymin=9*10E-6*(PR145/Rds(ON)max*1.5)
=9*10E-6*(26.1K/(0.0115*1.5))=13.617A
PR215
10K_0402_1%
1 2
B B
PR216
100K_0402_5%
SUSP#<17,25,32,37,40,42,44>
A A
1 2
PC169
0.1U_0402_16V7K
JUMP_43X118
PJP3
12
+1.5VS
1
1
2
2
12
PC162
22U_1206_10V6M
PC165
12
1U_0603_6.3V6M
PU13
6
VCNTL
5
VIN
9
VIN
8
EN
7
POK
3
VOUT
4
VOUT
2
FB
GND
APL5913-KAC-TRL_SO8
1
PR217
576_0402_1%
PR218
1K_0402_1%
12
12
12
PC166
0.01U_0402_25V
12
PC167
22U_1206_10V6M
1
+
2
+1.25VP
PC168
150U_D2E_6.3VM_R18@
Ivalleymax=11*10E-6*(PR145/Rds(ON)min*1.2)
=11*10E-6*(26.1K/(0.009*1.3))=20.076A
Iripple=(vin-vout)*(Ton/L)=4.292A, 1/2Iripple=2.146A
Iocp=Ivalley+ Iripple /2
OCP==>15.763A~22.222A
Security Classification
Issued Date
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2005/10/17 2006/10/17
Compal Secret Data
Deciphered Date
Compal Electronics, Inc.
Title
Size Document Number Rev
Custom
2
Date: Sheet
1.5VSP/1.25VP
Thursday, March 08, 2007
IHL00 LA-3691P
1
43 45
0.2
of
Page 44
5
D D
C C
4
1
PJ16
1
JUMP_43X79
2
2
12
PC118
10U_0805_6.3V6M
SUSP#<17,25,32,37,40,42,43>
0.1U_0402_16V7K @
PR150
0_0402_5%
1 2
PC121
3
+5VS+3VS
12
PC117
1U_0603_6.3V6M
PU10
6
VCNTL
5
VIN
9
VIN
8
EN
7
12
POK
3
VOUT
4
VOUT
2
FB
GND
APL5913-KAC-TRL_SO8
1
PR151
2.15K_0402_1%
12
12
PR152
1K_0402_1%
12
PC119
0.01U_0402_25V7K
12
PC120
22U_1206_6.3V6M
+2.5VSP
2
1
+1.8V
1
PJ17
1
JUMP_43X118
2
2
B B
PR154
0_0402_5%
SUSP<37>
A A
1 2
0.1U_0402_16V7K@
PC126
12
PC122
10U_0805_6.3V6M
13
D
PQ34
2
G
S
12
2N7002W-T/R7_SOT323-3
PR153
1K_0402_1%
PR155
1K_0402_1%
12
12
0.1U_0402_16V7K
12
PC124
Security Classification
Issued Date
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
PU11
1
2
3
4
RT9173DPSP_SO8
+0.9VSP
12
PC125
22U_1206_6.3V6M
VIN
GND
REFEN
VOUT
6
VCNTL
5
NC
7
NC
8
NC
9
GND
2005/10/17 2006/10/17
Compal Secret Data
+3VALW
12
PC123
1U_0603_6.3V6M
Deciphered Date
2
Compal Electronics, Inc.
Title
Size Document Number Rev
Custom
Date: Sheet
+2.5VSP/0.9VSP
Thursday, March 08, 2007
IHL00 LA-3691P
1
of
44 45
0.2
Page 45
5
D D
PR159
13K_0402_5%
NTC
100K_0402_5%
PR160
1 2
PR162 0_0402_5%
PR164 0_0402_5%
PR165 0_0402_5%
PR166 0_0402_5%
PR167 0_0402_5%
PR168 0_0402_5%
PR171 0_0402_5%
C C
PR175 499_0402_1%
PR176 0_0402_5%
PR177 0_0402_5%
PR186
0_0402_5%
VGATE<8,22>
CLK_ENABLE#
VR_ON<32>
B B
A A
1 2
@
1 2
1 2
0_0402_5%
0_0402_5%
PR189
PR190
PM_DPRSLPVR<8,22>
H_DPRSTP#<5,8,21>
+3VS
H_PROCHOT#<4>
CPU_VID0<5>
CPU_VID1<5>
CPU_VID2<5>
CPU_VID3<5>
CPU_VID4<5>
CPU_VID5<5>
CPU_VID6<5>
H_PSI#<5>
PR182
10K_0402_1%
1 2
PR192
10K_0402_5%@
1 2
POUT
1 2
1 2
1 2
1 2
PR183
2K_0402_1%@
1 2
PR195 0_0402_5%
PC151
0.1U_0402_16V7K
1 2
12
12
12
12
12
12
@
56_0402_5%
1 2
1 2
PR197 10K_0402_1%
1 2
PR173 71.5K_0402_1%
1 2
PC138 0.22U_0603_16V7K
+3VS
12
PR193
4
+5VS
PR156
12
PR157
10_0402_5%
VCC
12
12
PC13947P_0402_50V8J
5VS1
PC134
1U_0603_6.3V6M
1 2
PU12
19
Vcc
6
THRM
31
D0
32
D1
33
D2
34
D3
35
D4
36
D5
37
D6
7
TIME
9
CCV
11
REF
39
DPRSLPVR
40
DPRSTP
3
PSI
2
PWRGD
1
CLKEN
38
SHDN
5
VRHOT
4
POUT
MAX8770GTL+_TQFN40
<BOM Structure>
VSSSENSE<5>
12
0_1206_5%
PC135
2.2U_0603_6.3V6K
VDD
TON
BST1
DH1
LX1
DL1
PGND1
GND
CSP1
CSN1
FB
CCI
DH2
BST2
LX2
DL2
PGND2
CSP2
CSN2
GNDS
41
4700P_0402_25V7K
VSSSENSE
12
12
PR158
1 2
25
8
30
29
28
26
27
18
17
16
12
10
21
20
22
24
23
14
15
13
TP
@
PC143
PR194
100_0402_1%
PR198
10_0402_5%
200K_0402_1%
0_0603_5%
1 2
12
PR163
1 2
BST1_CPU BSTM1_CPU
DH1__CPU-1
LX1__CPU
DL1__CPU
CSP1__CPU
CSN1_CPU
FB_CPU
CCI_CPU
DH2_CPU-1
BST2_CPU
LX2_CPU
DL2__CPU
CSP2_CPU
CSN2__CPU
1 2
PC127
0.01U_0402_25V7K
3
0.22U_0603_16V7K
PR180
0_0603_5%
1 2
BSTM2_CPU
12
PC145
0.22U_0603_16V7K
PC136
1 2
PQ36
IRF8113PBF_SO8
NTC
1 2
PR191
20K_0402_1%
0_0603_5%
1 2
PQ39
IRF8113PBF_SO8
0_0603_5%
PR161
DH1_CPU-2
1 2
578
3 6
241
PR181 3K_0603_1%@
1 2
PR184 3.92K_0402_1%
1 2
1 2
PR187
3K_0603_1%@
PR196
DH2_CPU-2
578
3 6
241
CPU_B+
DL1__CPU
1 2
PR188
3K_0603_1%@
DL2__CPU
PQ35
SI7686DP-T1-E3_SO8
3 5
241
578
PQ37
3 6
241
IRF8113PBF_SO8
PR179 0_0402_5%
1 2
1 2
PC144
470P_0603_50V8J
PQ38
SI7686DP-T1-E3_SO8
3 5
241
578
IRF8113PBF_SO8
3 6
241
PR202 0_0402_5%
1 2
2
12
PC128
10U_1206_25V6M
12
4.7_1206_5%
PR169
12
1 2
12
PQ40
12
12
12
PC130
PC129
10U_1206_25V6M
PC137
PC141 0.022U_0402_16V7K
PC142
4700P_0402_25V7K
@
PR199
PC152
PC131
0.1U_0603_25V7K
10U_1206_25V6M
PL9
0.36H_ETQP4LR36WFC_24A_20%
PR170
3.48K_0402_1%
1 2
2.1K_0402_1%
PR174
1 2
10KB_0603_5%_ERTJ1VR103J
1 2
PC140 0.22U_0603_16V7K
680P_0603_50V7K
1 2
1 2
PR185 100_0402_1%
PC146
12
4.7_1206_5%
PR200
2.1K_0402_1%
680P_0603_50V7K
HCB4532KF-800T90_1812
1
12
12
PC132
2200P_0402_50V7K
12
1 2
CPU_VCC_SENSE
12
PC147
10U_1206_25V6M
0.36H_ETQP4LR36WFC_24A_20%
PR201
3.48K_0402_1%
1 2
PC153 0.22U_0603_16V7K
+
2
NTC
PH2
10U_1206_25V6M
@
12
12
PC148
PC149
10U_1206_25V6M
12
PL10
1 2
10KB_0603_5%_ERTJ1VR103J
1 2
PL8
1 2
PC133
100U_25V_M
+CPU_CORE
12
VCCSENSE<5>
PR172 10_0402_5%
CPU_B+
12
PC150
0.1U_0603_25V7K
NTC
PH3
1
+CPU_CORE
PR178
0_0402_5%
1 2
12
2200P_0402_50V7K
B+
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITT EN CON SENT O F COMPAL ELECTRONICS, INC.
2005/10/17 2006/10/17
3
Compal Secret Data
Deciphered Date
Compal Electronics, Inc.
Title
Size Document Number Rev
Custom
2
Date: Sheet
+CPU_CORE
IHL00 LA-3691P
0.2
of
45 45Thursday, March 08, 2007
1
Page 46
5
4
3
2
1
Version change list (P.I.R. List) Page 1 of 1
Rev. PG# Modify List B.Ver# PhaseFixed IssueItem
D D
1
2
3
4
5
6
7
C C
8
9
10
11
12
13
14
B B
15
16
17
A A
Compal Electronics, Inc.
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SE CRET INFO RMATI ON. THIS SHEET MAY NO T BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
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2
POWER PIR
Size Document Number Rev
Date: Sheet
1
of
48 48Thursday, March 08, 2007
Page 47
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1
Version change list (P.I.R. List) Page 1 of 1
Rev. PG# Modify List B.Ver# PhaseFixed IssueItem
D D
C C
10
11
12
13
14
B B
15
16
17
XDP_BPM#0~4 test point short as EMI request Modify Layout4
1
ADD J6 for +VCC_AXG UMA VGA power shape B 11 Modify Layout
2
Fixed Speaker no function A2 37 Change Q91 form SI2301BDS to MMBT3906, Del R895
3
Fixed SWDJ function can't work A2 36 Add R904
4
5
6
Fixed USB Port4 can't work A2 27 Swap USB_N4 & USB_P4
7
Fixed EMI issue A2 32 37 Add R908,C878,C879
8
Fixed SWDJ mode EC_MUTE# ISSUE
Fixed CMOS noise B 36 Add R912,C880
9
Fixed EMI B 25 Add C881,C882
Add chipset id B 33 Add R915,R916
Fix SWDJ Subwoofer issue B 31 Add R917
Fix DFX issue C 22,33 Change Y3,X1,Y2 footprint
FOR E-STAR V4 wake on lan C 22,33 Add R918,R919
For ESD issue C 36 Add C883~C887 D40,D41
For AUDIO team design C 30 Add R920 R921
Change LAN led function C 25 Swap JP73 PIN12 & PIN14
B
Add R905,Q9629A2Fixed Audio Codec can't work
B 30 Add D39,Q99,R914
A A
Compal Electronics, Inc.
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SE CRET INFO RMATI ON. THIS SHEET MAY NO T BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2
POWER PIR
Size Document Number Rev
Date: Sheet
1
of
48 48Thursday, March 08, 2007
Page 48
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