COMPAL LA-3611P Schematics

A

1 1

B

C

D

E

2 2

Compal Confidential

Schematics Document

AMD S1/ ATI RS690MC / SB600

2007 / 4 / 10

3 3

Rev:0.4

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2007/1/25 2008/01/25

Compal Secret Data

Deciphered Date

Title

Cover Sheet

Size Document Number Rev

Custom

LA-3611P

D

Date: Sheet

E

140Wednesday, April 11, 2007

0.4

of

A

B

C

D

E

Compal confidential

Project Code: ANRIBL5000(IBL50)
File Name : LA-3611P
PCB P/N: DA800008C00

1 1

Thermal Sensor
ADM1032ARM

page 6 page 13

Clock Generator
ICS951462

Turion64 x2 TLxx / Sempron

CRT

page 14

AMD S1 CPU

page 4,5,6,7

HT 16x16 800MHZ

ATI-RS690M(C)

DDR-2 DDR2-SO-DIMM X2

page 8,9

Daul Channel DDR-2

LCD CONN

page 14

PCI EXPRESS

2 2

Realtek

RTL8111B

page 22

Express Card
(New Card)

page 27

Mini Card1
WLAN

page 25

RJ45 CONN

page 22

PCI BUS

CradBus Controller

BGA465

page 10,11,12

A-Link Express

2 x PCIE

ATI-SB600

BGA548

page 15,16,17,18

USB 2.0

USB 2.0

USB 2.0

HD-Interface

USB conn x 4

Felica Conn

page 28

page 27

Audio CKT

ALC262 C2

page 23

MDC Conn.

page 23

Mini Card2
TV

page 25

AMP & Audio Jack

RJ11 CONN(Combine RJ45)

page 24

page 22

Ricoh R5C847

page 20,21

3 3

Slot 0

page 21

Media Card

page 21

1394
Conn.

page 20

Power On/Off CKT.

page 29

LPC BUS

SATA

PATA

SATA HDD Conn.

page 19

HDD Conn.
CDROM Conn.

page 19

ENE KB926

DC/DC Interface CKT.

page 30

Power Circuit DC/DC

page 31~38

4 4

RTC CKT.

page 15

Power OK CKT.

page 29

Touch Pad
CONN.

page 27

page 26

Int. KBD

page 27

SPI BIOS

page 26

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2007/1/25 2008/01/25

Compal Secret Data

Deciphered Date

Title

Block Diagrams

Size Document Number Rev

Custom

LA-3611P

D

Date: Sheet

E

240Wednesday, April 11, 2007

0.4

of

A

Voltage Rails

Power Plane Description

VIN

1 1

2 2

B+
+CPU_CORE
+1.2V_HT
+0.9V 0.9V switched power rail for DDR terminator
+1.2VALW 1.2V always on power rail
+1.5VS
+1.8VS 1.8V switched power rail
+1.8V
+3VALW
+3V
+3VS
+5VALW
+5VS
+RTCVCC RTC power

Adapter power supply (19V)
AC or battery power rail for power circuit.
Core voltage for CPU

1.2V switched power rail

1.5V switched power rail

1.8V power rail for DDR

3.3V always on power rail

3.3V power rail

3.3V switched power rail
5V always on power rail
5V switched power rail

B

S1 S3 S4/ S5

ON ON ON

ON OFF
ON OFF
ON OFF
ON
ON OFF OFF
ON OFF OFF
ON
ON
ON
ON
ON

ON ONON

ONONON
OFF
OFF

ON

ONON

OFF

ON
ON ON

OFF

ON

OFF

OFF
ON

ON
OFFON

OFF

C

SIGNAL

STATE

Full ON

S1(Power On Suspend)

S3 (Suspend to RAM)

SLP_S1# SLP_S3#

HIGH HIGH HIGH HIGH

LOW

LOW

LOW

S4 (Suspend to Disk)

S5 (Soft OFF)

LOW LOW LOW LOW

Board ID Table for AD channel

Vcc 3.3V +/- 5%

Board ID

0
1
2
3
4
5
6
7 NC

100K +/- 5%Ra / Rc

Rb / Rd V min

0

8.2K +/- 5%
18K +/- 5%
33K +/- 5%
56K +/- 5%
100K +/- 5%
200K +/- 5%

AD_BID

0 V

0.216 V 0.250 V 0.289 V

0.436 V

0.712 V

1.036 V

1.453 V 1.650 V 1.759 V

1.935 V

2.500 V

D

SLP_S4# SLP_S5# +VALW +V +VS Clock

ON

ON

ON

OFF

OFF

V

AD_BID

ON ON

ON

OFF

OFF

OFF

max

LOW

OFF

OFF

OFF

HIGH

LOWLOWLOW

HIGHHIGHHIGH

HIGH

HIGH

V typ

AD_BID

ON

ON

ON

ON

ON

0 V 0 V

0.503 V

0.819 V

0.538 V

0.875 V

1.185 V 1.264 V

2.200 V

3.300 V

2.341 V

3.300 V

E

External PCI Devices

Device IDSEL# REQ#/GNT# Interrupts

CardBus

AD21

0

PIRQE/PIRQF/PIRQG

BOARD ID Table

Board ID

0
1
2

PCB Revision

0.2 (KH4 ES1)

0.3 (KH4 ES2)

0.4 (KH4 PP)

BTO Item BOM Structure

BTO Option Table

3
4
5
6
7

EC SM Bus1 address

3 3

Device

Smart Battery
EEPROM(24C16/02)

(24C04)

Address Address

1010 000X b?
1011 000Xb?

EC SM Bus2 address

Device

ADM1032

1001 110X b?0001 011X b?

SB600 SM Bus address

Device

Clock Generator
(ICS 951462AGT)

DDRII DIMM0
DDRII DIMM2

4 4

Address

1101 001Xb?

1001 000Xb?
1001 010Xb?

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2007/1/25 2008/01/25

Compal Secret Data

Deciphered Date

Title

Notes

Size Document Number Rev

Custom

LA-3611P

D

Date: Sheet

E

340Wednesday, April 11, 2007

0.4

of

5

4

3

2

1

H_CADIP[0..15]10

H_CADIP[0..15]
H_CADIN[0..15]

H_CADOP[0..15]
H_CADON[0..15]

H_CADOP[0..15] 10
H_CADON[0..15] 10H_CADIN[0..15]10

PROCESSOR HYPERTRANSPORT INTERFACE

D D

C C

+1.2V_HT

R236 51_0402_1%
R235 51_0402_1%

B B

A A

2006-10-17 Change from 49.9 1% to 51 1%

VLDT_Ax AND VLDT_Bx ARE CONNECTED TO THE LDT_RUN POWER
SUPPLY THROUGH THE PACKAGE OR ON THE DIE. IT IS ONLY CONNECTED
ON THE BOARD TO DECOUPLING NEAR THE CPU PACKAGE

+1.2V_HT

D4

VLDT_A3

D3

VLDT_A2

D2

VLDT_A1

D1

VLDT_A0

H_CADIP15

N5

P5
M3
M4

L5
M5

K3

K4
H3
H4
G5
H5

F3

F4

E5

F5
N3
N2

L1
M1

L3

L2

J1

K1
G1
H1
G3
G2

E1

F1

E3

E2

J5

K5

J3

J2

P3

P4
N1

P1

+1.2V_HT

1

C4314.7U_0805_6.3V6K~N

2

L0_CADIN_H15
L0_CADIN_L15
L0_CADIN_H14
L0_CADIN_L14
L0_CADIN_H13
L0_CADIN_L13
L0_CADIN_H12
L0_CADIN_L12
L0_CADIN_H11
L0_CADIN_L11
L0_CADIN_H10
L0_CADIN_L10
L0_CADIN_H9
L0_CADIN_L9
L0_CADIN_H8
L0_CADIN_L8
L0_CADIN_H7
L0_CADIN_L7
L0_CADIN_H6
L0_CADIN_L6
L0_CADIN_H5
L0_CADIN_L5
L0_CADIN_H4
L0_CADIN_L4
L0_CADIN_H3
L0_CADIN_L3
L0_CADIN_H2
L0_CADIN_L2
L0_CADIN_H1
L0_CADIN_L1
L0_CADIN_H0
L0_CADIN_L0

L0_CLKIN_H1
L0_CLKIN_L1
L0_CLKIN_H0
L0_CLKIN_L0

L0_CTLIN_H1
L0_CTLIN_L1

L0_CTLIN_H0
L0_CTLIN_L0

H_CADIN15
H_CADIP14
H_CADIN14
H_CADIP13
H_CADIN13
H_CADIP12
H_CADIN12
H_CADIP11
H_CADIN11
H_CADIP10
H_CADIN10
H_CADIP9
H_CADIN9
H_CADIP8
H_CADIN8
H_CADIP7
H_CADIN7
H_CADIP6
H_CADIN6
H_CADIP5
H_CADIN5
H_CADIP4
H_CADIN4
H_CADIP3
H_CADIN3
H_CADIP2
H_CADIN2
H_CADIP1
H_CADIN1
H_CADIP0
H_CADIN0

H_CLKIP110
H_CLKIN110
H_CLKIP010
H_CLKIN010

1 2
1 2

H_CTLIP010 H_CTLOP0 10
H_CTLIN010

H_CLKIP1
H_CLKIN1
H_CLKIP0
H_CLKIN0

H_CTLIP0
H_CTLIN0

1

C4284.7U_0805_6.3V6K~N

2

CPU1A

Athlon 64 S1
Processor Socket

1

C4300.22U_0603_10V7K

2

AE5

VLDT_B3

AE4

VLDT_B2

AE3

VLDT_B1

AE2

VLDT_B0

H_CADOP15

1

C427180P_0402_50V8J~N

2

1

C429180P_0402_50V8J~N

2

T4
T3
V5
U5
V4
V3
Y5
W5
AB5
AA5
AB4
AB3
AD5
AC5
AD4
AD3
T1
R1
U2
U3
V1
U1
W2
W3
AA2
AA3
AB1
AA1
AC2
AC3
AD1
AC1

Y4
Y3
Y1
W1

T5
R5

R2
R3

H_CADON15
H_CADOP14
H_CADON14
H_CADOP13
H_CADON13
H_CADOP12
H_CADON12
H_CADOP11
H_CADON11
H_CADOP10
H_CADON10
H_CADOP9
H_CADON9
H_CADOP8
H_CADON8
H_CADOP7
H_CADON7
H_CADOP6
H_CADON6
H_CADOP5
H_CADON5
H_CADOP4
H_CADON4
H_CADOP3
H_CADON3
H_CADOP2
H_CADON2
H_CADOP1
H_CADON1
H_CADOP0
H_CADON0

H_CLKOP1
H_CLKON1
H_CLKOP0
H_CLKON0

H_CTLOP0
H_CTLON0

L0_CADOUT_H15

L0_CADOUT_L15

L0_CADOUT_H14

L0_CADOUT_L14

L0_CADOUT_H13

L0_CADOUT_L13

L0_CADOUT_H12

L0_CADOUT_L12

L0_CADOUT_H11

L0_CADOUT_L11

L0_CADOUT_H10

L0_CADOUT_L10

L0_CADOUT_H9
L0_CADOUT_L9
L0_CADOUT_H8
L0_CADOUT_L8
L0_CADOUT_H7
L0_CADOUT_L7
L0_CADOUT_H6
L0_CADOUT_L6
L0_CADOUT_H5
L0_CADOUT_L5
L0_CADOUT_H4
L0_CADOUT_L4
L0_CADOUT_H3
L0_CADOUT_L3
L0_CADOUT_H2
L0_CADOUT_L2
L0_CADOUT_H1
L0_CADOUT_L1
L0_CADOUT_H0

HTT Interface

L0_CADOUT_L0
L0_CLKOUT_H1

L0_CLKOUT_L1

L0_CLKOUT_H0

L0_CLKOUT_L0

L0_CTLOUT_H1
L0_CTLOUT_L1

L0_CTLOUT_H0
L0_CTLOUT_L0

1

C4260.22U_0603_10V7K

2

1 2

C394 4.7U_0805_6.3V6K~N

H_CLKOP1 10
H_CLKON1 10
H_CLKOP0 10
H_CLKON0 10

H_CTLON0 10

FAN1 Control and Tachometer

EN_DFAN126

FAN_SPEED126

EN_DFAN1

R38

10K_0402_5%

+3VS

12

2

C114

0.01U_0402_16V7K

1

+5VS

12

D3

1SS355_SOD323 @

@

12

D14 1N4148_SOT23

C424

10U_0805_10V4Z~N

12

C113

1000P_0402_50V7K~N

12

FAN1_POWER

+5VS

40mil

1 2

C410 10U_0805_10V4Z~N
U20

1

VEN

2

VIN

3

VO

4

VSET

G993P1UF_SOP8
JFAN1

1
2
3

4

G

5

G

MOLEX_53398-0371~N

CONN@

GND
GND
GND
GND

8
7
6
5

FAN1

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2007/1/25 2008/01/25

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

Compal Electronics, Inc.

TURION64 HT I/F & FAN

LA-3611P

1

0.4

of

440Wednesday, April 11, 2007

A

B

C

D

E

VDD_VTT_SUS_CPU IS CONNECTED TO THE VDD_VTT_SUS POWER
SUPPLY THROUGH THE PACKAGE OR ON THE DIE. IT IS ONLY CONNECTED

ON THE BOARD TO DECOUPLING NEAR THE CPU PACKAGE

+1.8V

4 4

3 3

2 2

12

R222

39.2_0603_1%

12

R223

39.2_0603_1%

PLACE THEM CLOSE TO
CPU WITHIN 1"

DDR_CS3_DIMMA#8
DDR_CS2_DIMMA#8
DDR_CS1_DIMMA#8
DDR_CS0_DIMMA#8

DDR_CS3_DIMMB#9
DDR_CS2_DIMMB#9
DDR_CS1_DIMMB#9
DDR_CS0_DIMMB#9

DDR_CKE1_DIMMB9
DDR_CKE0_DIMMB9
DDR_CKE1_DIMMA8
DDR_CKE0_DIMMA8

DDR_A_MA[15..0]8

DDR_A_BS#28
DDR_A_BS#18
DDR_A_BS#08

DDR_A_RAS#8
DDR_A_CAS#8
DDR_A_WE#8

DDR_A_CLK2

DDR_A_CLK#2
DDR_A_CLK1

DDR_A_CLK#1

PLACE CLOSE TO PROCESSOR
WITHIN 1.5 INCH

TP1

M_ZN
M_ZP

1

C392

1.5P 50V F NPO 0402

2

1

C439

1.5P 50V F NPO 0402

2

+CPU_M_VREF

VTT_SENSE

DDR_CS3_DIMMA#
DDR_CS2_DIMMA#
DDR_CS1_DIMMA#
DDR_CS0_DIMMA#

DDR_CS3_DIMMB#
DDR_CS2_DIMMB#
DDR_CS1_DIMMB#
DDR_CS0_DIMMB#

DDR_CKE1_DIMMB
DDR_CKE0_DIMMB
DDR_CKE1_DIMMA
DDR_CKE0_DIMMA

DDR_A_MA15
DDR_A_MA14
DDR_A_MA13
DDR_A_MA12
DDR_A_MA11
DDR_A_MA10
DDR_A_MA9
DDR_A_MA8
DDR_A_MA7
DDR_A_MA6
DDR_A_MA5
DDR_A_MA4
DDR_A_MA3
DDR_A_MA2
DDR_A_MA1
DDR_A_MA0

DDR_A_BS#2
DDR_A_BS#1
DDR_A_BS#0

DDR_A_RAS#
DDR_A_CAS#
DDR_A_WE#

AE10
AF10

W17

Y10

V19
J22
V22
T19

Y26
J24

W24

U23
H26

J23
J20
J21

K19
K20
V24
K24
L20
R19
L19
L22

L21
M19
M20
M24
M22

N22

N21

R21

K22

R20

T22

T20

U20

U21

M_VREF
VTT_SENSE

M_ZN
M_ZP

MA0_CS_L3
MA0_CS_L2
MA0_CS_L1
MA0_CS_L0

MB0_CS_L3
MB0_CS_L2
MB0_CS_L1
MB0_CS_L0

MB_CKE1
MB_CKE0
MA_CKE1
MA_CKE0

MA_ADD15
MA_ADD14
MA_ADD13
MA_ADD12
MA_ADD11
MA_ADD10
MA_ADD9
MA_ADD8
MA_ADD7
MA_ADD6
MA_ADD5
MA_ADD4
MA_ADD3
MA_ADD2
MA_ADD1
MA_ADD0

MA_BANK2
MA_BANK1
MA_BANK0

MA_RAS_L
MA_CAS_L
MA_WE_L

Athlon 64 S1
Processor
Socket

CPU1B

VTT1
VTT2
VTT3
VTT4
VTT5
VTT6
VTT7
VTT8
VTT9

MA0_CLK_H2
MA0_CLK_L2
MA0_CLK_H1
MA0_CLK_L1

MB0_CLK_H2
MB0_CLK_L2
MB0_CLK_H1
MB0_CLK_L1

MB0_ODT1
MB0_ODT0
MA0_ODT1
MA0_ODT0

MB_ADD15
MB_ADD14
MB_ADD13
MB_ADD12
MB_ADD11
MB_ADD10

MB_ADD9

DDRII Cmd/Ctrl//Clk

MB_ADD8
MB_ADD7
MB_ADD6
MB_ADD5
MB_ADD4
MB_ADD3
MB_ADD2
MB_ADD1
MB_ADD0

MB_BANK2
MB_BANK1
MB_BANK0

MB_RAS_L
MB_CAS_L

MB_WE_L

DDR_B_CLK2

DDR_B_CLK#2
DDR_B_CLK1

DDR_B_CLK#1

PLACE CLOSE TO PROCESSOR
WITHIN 1.5 INCH

D10
C10
B10
AD10
W10
AC10
AB10
AA10
A10

Y16
AA16
E16
F16

AF18
AF17
A17
A18

W23
W26
V20
U19

J25
J26
W25
L23
L25
U25
L24
M26
L26
N23
N24
N25
N26
P24
P26
T24

K26
T26
U26

U24
V26
U22

+0.9V

DDR_A_CLK2
DDR_A_CLK#2
DDR_A_CLK1
DDR_A_CLK#1

DDR_B_CLK2
DDR_B_CLK#2
DDR_B_CLK1
DDR_B_CLK#1

DDR_B_ODT1
DDR_B_ODT0
DDR_A_ODT1
DDR_A_ODT0

DDR_B_MA15
DDR_B_MA14
DDR_B_MA13
DDR_B_MA12
DDR_B_MA11
DDR_B_MA10
DDR_B_MA9
DDR_B_MA8
DDR_B_MA7
DDR_B_MA6
DDR_B_MA5
DDR_B_MA4
DDR_B_MA3
DDR_B_MA2
DDR_B_MA1
DDR_B_MA0

DDR_B_BS#2
DDR_B_BS#1
DDR_B_BS#0

DDR_B_RAS#
DDR_B_CAS#
DDR_B_WE#

1

2

1

2

C393

1.5P 50V F NPO 0402

C438

1.5P 50V F NPO 0402

DDR_A_CLK2 8
DDR_A_CLK#2 8
DDR_A_CLK1 8
DDR_A_CLK#1 8

DDR_B_CLK2 9
DDR_B_CLK#2 9
DDR_B_CLK1 9
DDR_B_CLK#1 9

DDR_B_ODT1 9
DDR_B_ODT0 9
DDR_A_ODT1 8
DDR_A_ODT0 8

DDR_B_MA[15..0] 9

DDR_B_BS#2 9
DDR_B_BS#1 9
DDR_B_BS#0 9

DDR_B_RAS# 9
DDR_B_CAS# 9
DDR_B_WE# 9

Processor DDR2 Memory Interface

DDR_B_D[63..0]9

To reverse SODIMM socket

DDR_B_DM[7..0]9 DDR_A_DM[7..0] 8

DDR_B_DQS79
DDR_B_DQS#79
DDR_B_DQS69
DDR_B_DQS#69
DDR_B_DQS59
DDR_B_DQS#59
DDR_B_DQS49
DDR_B_DQS#49
DDR_B_DQS39
DDR_B_DQS#39
DDR_B_DQS29
DDR_B_DQS#29
DDR_B_DQS19
DDR_B_DQS#19
DDR_B_DQS09
DDR_B_DQS#09

DDR_B_D63
DDR_B_D62
DDR_B_D61
DDR_B_D60
DDR_B_D59
DDR_B_D58
DDR_B_D57
DDR_B_D56
DDR_B_D55
DDR_B_D54
DDR_B_D53
DDR_B_D52
DDR_B_D51
DDR_B_D50
DDR_B_D49
DDR_B_D48
DDR_B_D47
DDR_B_D46
DDR_B_D45
DDR_B_D44
DDR_B_D43
DDR_B_D42
DDR_B_D41
DDR_B_D40
DDR_B_D39
DDR_B_D38
DDR_B_D37
DDR_B_D36
DDR_B_D35
DDR_B_D34
DDR_B_D33
DDR_B_D32
DDR_B_D31
DDR_B_D30
DDR_B_D29
DDR_B_D28
DDR_B_D27
DDR_B_D26
DDR_B_D25
DDR_B_D24
DDR_B_D23
DDR_B_D22
DDR_B_D21
DDR_B_D20
DDR_B_D19
DDR_B_D18
DDR_B_D17
DDR_B_D16
DDR_B_D15
DDR_B_D14
DDR_B_D13
DDR_B_D12
DDR_B_D11
DDR_B_D10
DDR_B_D9
DDR_B_D8
DDR_B_D7
DDR_B_D6
DDR_B_D5
DDR_B_D4
DDR_B_D3
DDR_B_D2
DDR_B_D1
DDR_B_D0

DDR_B_DM7
DDR_B_DM6
DDR_B_DM5
DDR_B_DM4
DDR_B_DM3
DDR_B_DM2
DDR_B_DM1
DDR_B_DM0

DDR_B_DQS7
DDR_B_DQS#7
DDR_B_DQS6
DDR_B_DQS#6
DDR_B_DQS5
DDR_B_DQS#5
DDR_B_DQS4
DDR_B_DQS#4
DDR_B_DQS3
DDR_B_DQS#3
DDR_B_DQS2
DDR_B_DQS#2
DDR_B_DQS1
DDR_B_DQS#1
DDR_B_DQS0
DDR_B_DQS#0

AD11
AF11
AF14
AE14

AB11
AC12
AF13
AF15
AF16
AC18
AF19
AD14
AC14
AE18
AD18
AD20
AC20
AF23
AF24
AF20
AE20
AD22
AC22
AE25
AD26
AA25
AA26
AE24
AD24
AA23
AA24

AD12
AC16
AE22
AB26

AF12
AE12
AE16
AD16
AF21
AF22
AC25
AC26

Y11

G24
G23
D26
C26
G26
G25
E24
E23
C24
B24
C20
B20
C25
D24
A21
D20
D18
C18
D14
C14
A20
A19
A16
A15
A13
D12
E11
G11
B14
A14
A11
C11

E25
A22
B16
A12

F26
E26
A24
A23
D16
C16
C12
B12

MB_DATA63
MB_DATA62
MB_DATA61
MB_DATA60
MB_DATA59
MB_DATA58
MB_DATA57
MB_DATA56
MB_DATA55
MB_DATA54
MB_DATA53
MB_DATA52
MB_DATA51
MB_DATA50
MB_DATA49
MB_DATA48
MB_DATA47
MB_DATA46
MB_DATA45
MB_DATA44
MB_DATA43
MB_DATA42
MB_DATA41
MB_DATA40
MB_DATA39
MB_DATA38
MB_DATA37
MB_DATA36
MB_DATA35
MB_DATA34
MB_DATA33
MB_DATA32
MB_DATA31
MB_DATA30
MB_DATA29
MB_DATA28
MB_DATA27
MB_DATA26
MB_DATA25
MB_DATA24
MB_DATA23
MB_DATA22
MB_DATA21
MB_DATA20
MB_DATA19
MB_DATA18
MB_DATA17
MB_DATA16
MB_DATA15
MB_DATA14
MB_DATA13
MB_DATA12
MB_DATA11
MB_DATA10
MB_DATA9
MB_DATA8
MB_DATA7
MB_DATA6
MB_DATA5
MB_DATA4
MB_DATA3
MB_DATA2
MB_DATA1
MB_DATA0

MB_DM7
MB_DM6
MB_DM5
MB_DM4
MB_DM3
MB_DM2
MB_DM1
MB_DM0

MB_DQS_H7
MB_DQS_L7
MB_DQS_H6
MB_DQS_L6
MB_DQS_H5
MB_DQS_L5
MB_DQS_H4
MB_DQS_L4
MB_DQS_H3
MB_DQS_L3
MB_DQS_H2
MB_DQS_L2
MB_DQS_H1
MB_DQS_L1
MB_DQS_H0
MB_DQS_L0

CPU1C

DDRII Data

Athlon 64 S1
Processor Socket

MA_DATA63
MA_DATA62
MA_DATA61
MA_DATA60
MA_DATA59
MA_DATA58
MA_DATA57
MA_DATA56
MA_DATA55
MA_DATA54
MA_DATA53
MA_DATA52
MA_DATA51
MA_DATA50
MA_DATA49
MA_DATA48
MA_DATA47
MA_DATA46
MA_DATA45
MA_DATA44
MA_DATA43
MA_DATA42
MA_DATA41
MA_DATA40
MA_DATA39
MA_DATA38
MA_DATA37
MA_DATA36
MA_DATA35
MA_DATA34
MA_DATA33
MA_DATA32
MA_DATA31
MA_DATA30
MA_DATA29
MA_DATA28
MA_DATA27
MA_DATA26
MA_DATA25
MA_DATA24
MA_DATA23
MA_DATA22
MA_DATA21
MA_DATA20
MA_DATA19
MA_DATA18
MA_DATA17
MA_DATA16
MA_DATA15
MA_DATA14
MA_DATA13
MA_DATA12
MA_DATA11
MA_DATA10

MA_DATA9
MA_DATA8
MA_DATA7
MA_DATA6
MA_DATA5
MA_DATA4
MA_DATA3
MA_DATA2
MA_DATA1
MA_DATA0

MA_DM7
MA_DM6
MA_DM5
MA_DM4
MA_DM3
MA_DM2
MA_DM1
MA_DM0

MA_DQS_H7

MA_DQS_L7

MA_DQS_H6

MA_DQS_L6

MA_DQS_H5

MA_DQS_L5

MA_DQS_H4

MA_DQS_L4

MA_DQS_H3

MA_DQS_L3

MA_DQS_H2

MA_DQS_L2

MA_DQS_H1

MA_DQS_L1

MA_DQS_H0

MA_DQS_L0

AA12
AB12
AA14
AB14
W11
Y12
AD13
AB13
AD15
AB15
AB17
Y17
Y14
W14
W16
AD17
Y18
AD19
AD21
AB21
AB18
AA18
AA20
Y20
AA22
Y22
W21
W22
AA21
AB22
AB24
Y24
H22
H20
E22
E21
J19
H24
F22
F20
C23
B22
F18
E18
E20
D22
C19
G18
G17
C17
F14
E14
H17
E17
E15
H15
E13
C13
H12
H11
G14
H14
F12
G12

Y13
AB16
Y19
AC24
F24
E19
C15
E12

W12
W13
Y15
W15
AB19
AB20
AD23
AC23
G22
G21
C22
C21
G16
G15
G13
H13

DDR_A_D63
DDR_A_D62
DDR_A_D61
DDR_A_D60
DDR_A_D59
DDR_A_D58
DDR_A_D57
DDR_A_D56
DDR_A_D55
DDR_A_D54
DDR_A_D53
DDR_A_D52
DDR_A_D51
DDR_A_D50
DDR_A_D49
DDR_A_D48
DDR_A_D47
DDR_A_D46
DDR_A_D45
DDR_A_D44
DDR_A_D43
DDR_A_D42
DDR_A_D41
DDR_A_D40
DDR_A_D39
DDR_A_D38
DDR_A_D37
DDR_A_D36
DDR_A_D35
DDR_A_D34
DDR_A_D33
DDR_A_D32
DDR_A_D31
DDR_A_D30
DDR_A_D29
DDR_A_D28
DDR_A_D27
DDR_A_D26
DDR_A_D25
DDR_A_D24
DDR_A_D23
DDR_A_D22
DDR_A_D21
DDR_A_D20
DDR_A_D19
DDR_A_D18
DDR_A_D17
DDR_A_D16
DDR_A_D15
DDR_A_D14
DDR_A_D13
DDR_A_D12
DDR_A_D11
DDR_A_D10
DDR_A_D9
DDR_A_D8
DDR_A_D7
DDR_A_D6
DDR_A_D5
DDR_A_D4
DDR_A_D3
DDR_A_D2
DDR_A_D1
DDR_A_D0

DDR_A_DM7
DDR_A_DM6
DDR_A_DM5
DDR_A_DM4
DDR_A_DM3
DDR_A_DM2
DDR_A_DM1
DDR_A_DM0

DDR_A_DQS7
DDR_A_DQS#7
DDR_A_DQS6
DDR_A_DQS#6
DDR_A_DQS5
DDR_A_DQS#5
DDR_A_DQS4
DDR_A_DQS#4
DDR_A_DQS3
DDR_A_DQS#3
DDR_A_DQS2
DDR_A_DQS#2
DDR_A_DQS1
DDR_A_DQS#1
DDR_A_DQS0
DDR_A_DQS#0

DDR_A_D[63..0] 8

DDR_A_DQS7 8
DDR_A_DQS#7 8
DDR_A_DQS6 8
DDR_A_DQS#6 8
DDR_A_DQS5 8
DDR_A_DQS#5 8
DDR_A_DQS4 8
DDR_A_DQS#4 8
DDR_A_DQS3 8
DDR_A_DQS#3 8
DDR_A_DQS2 8
DDR_A_DQS#2 8
DDR_A_DQS1 8
DDR_A_DQS#1 8
DDR_A_DQS0 8
DDR_A_DQS#0 8

To normal SODIMM socket

+1.8V

R35

1K_0402_1%

1 2

1 1

R34

1K_0402_1%

1 2

1

C54

2

0.1U_0402_16V7K~N

A

VDD_VREF_SUS_CPU

+CPU_M_VREF

1

C53

2

1000P_0402_50V7K~N

LAYOUT:PLACE CLOSE TO CPU

Placement between CPU to DDR area(Reserved for EMI)

+1.8V

1

C609

2

0.1U_0402_16V7K~N

1

C613

2

0.1U_0402_16V7K~N

B

1

C610

2

1

C614

2

1

2

0.1U_0402_16V7K~N

1

2

0.1U_0402_16V7K~N

1

C611

0.1U_0402_16V7K~N

C615

0.1U_0402_16V7K~N

C612

2

0.1U_0402_16V7K~N

1

C616

2

0.1U_0402_16V7K~N

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2007/1/25 2008/01/25

Compal Secret Data

Deciphered Date

D

Title

Size Document Number Rev

Custom

Date: Sheet

A1

Athlon 64 S1g1

uPGA638
Top View

AF1

TURION64 DDRII MEMORY I/F

LA-3611P

E

A26

540Wednesday, April 11, 2007

0.4

of

5

R252

@

0_0805_5%

+3VALW

+3VS +2.5VDDA

D D

C C

B B

CPUCLK0_H
CPUCLK0_L

CPU_VDD_FB_H
CPU_VDD_FB_L

CPU_TEST29_H_FBCLKOUT_P
CPU_TEST29_L_FBCLKOUT_N

CPU_ALL_PWROK
CPU_LDTSTOP#
CPU_HT_RESET#
CPU_THERMTRIP#_R

A A

12

12

R2530_0805_5%
1U_0603_10V6K

C433

470_0402_5%

SSM3K7002FU_SC70-3

SB_PWRGD16,26

U21

1

12

13

D

S

LDT_STOP#11,15

LDT_RST#15

SB_PWRGD
LDT_RST#

5

2

2

G

IN
GND
SHDN3BYP

G914E_SOT23-5

SYSON#

TP49PAD
TP51PAD

TP12PAD
TP20PAD

TP18PAD
TP17PAD

TP46PAD
TP16PAD
TP45PAD
TP30PAD

2
1

2

1

R241

Q42

@

CPU_PWRGD15

5

OUT

4

C432

0.01U_0402_16V7K

CPU_SIC_SB15

SYSON# 30,35

1 2

1 2

1 2

+3VALW

5

U3

P

B

4

Y

A

G

NC7SZ08P5X_NL_SC70-5

3

@

2

1

1

2

R248

1 2

0_0402_5%

R255
680_0402_5%

R48

1 2

0_0402_5%

R51
680_0402_5%

R247

1 2

0_0402_5%

R58
680_0402_5%

CPU_DBREQ#
CPU_DBRDY CPU_TDO
CPU_TCK
CPU_TMS
CPU_TDI
CPU_TRST#

NOTE: HDT TERMINATION IS REQUIRED
FOR REV. Ax SILICON ONLY.

HDT_RST#

+2.5VDDA

150U_D2_6.3VM

C444
1U_0603_10V6K

R31

1 2

0_0402_5%

@

CPU_ALL_PWROK

CPU_LDTSTOP#

2007-01-17 ATI recommend

CPU_HT_RESET#

12

TP54

+1.8V

R22220_0402_5%

4

L35
LQG21F4R7N00_0805

1 2

1

+

C457

+1.8V

12

@

12

2

R226
300_0402_5%

CPU_SIC

R228
300_0402_5%

4.7U_0805_6.3V6K~N

CPU_SID_SB15

CPUCLK0_H13

CPUCLK0_L13

HDT Connector

R21220_0402_5%

R18220_0402_5%

R24220_0402_5%

R20220_0402_5%

12

R23

0_0402_5%

@

4

R19220_0402_5%

12

@

12

12

@

12

@

12

12

12

LAYOUT: ROUTE VDDA TRACE APPROX.
50 mils WIDE (USE 2x25 mil TRACES TO
EXIT BALL FIELD) AND 500 mils LONG.

1

1

1

C458

2

C459

C460

0.22U_0603_10V7K

2

2

3300P_0402_50V7K

R30

1 2

0_0402_5%

@

place them to CPU within 1"

3900P_0402_50V7K

1 2

C446

1 2

C445 3900P_0402_50V7K

R16220_0402_5%

R17
0_0402_5%

3

ATHLON Control and Debug

CPU_+VDDA

F8

+1.8V

12

R29

@

300_0402_5%

R234 44.2_0402_1%

+1.2V_HT

R233 44.2_0402_1%

CPU_CLKIN_SC_P

R249
169_0402_1%

TP15
TP19

TP23
TP21
TP13
TP44

TP33

THERMDC_CPU
THERMDA_CPU

TP7
TP10
TP9
TP11

TP39
TP40
TP6
TP8

CPU_CLKIN_SC_N

12

1 2
1 2

CPU_TEST25_H_BYPASSCLK_H
CPU_TEST25_L_BYPASSCLK_L
CPU_TEST19_PLLTEST0
CPU_TEST18_PLLTEST1

CPU_TEST17_BP3
CPU_TEST16_BP2
CPU_TEST15_BP1
CPU_TEST14_BP0
CPU_TEST12_SCANSHIFTENB

CPU_RSVD_MA0_CLK3_P
CPU_RSVD_MA0_CLK3_N
CPU_RSVD_MA0_CLK0_P
CPU_RSVD_MA0_CLK0_N

CPU_RSVD_MB0_CLK3_P
CPU_RSVD_MB0_CLK3_N
CPU_RSVD_MB0_CLK0_P
CPU_RSVD_MB0_CLK0_N

CPU_VDD_FB_H36
CPU_VDD_FB_L36

CPU_SIC
CPU_SID

TP2
TP26

CPU_HT_RESET#
CPU_ALL_PWROK
CPU_LDTSTOP#

VDDIOFB_H
VDDIOFB_L

CPU_DBRDY
CPU_TMS

CPU_TCK
CPU_TRST#
CPU_TDI

CPU_HTREF1
CPU_HTREF0

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

VDDA2

F9

VDDA1

B7

RESET_L

A7

PWROK

F10

LDTSTOP_L

AF4

SIC

AF5

SID

P6

HTREF1

R6

HTREF0

F6

VDD_FB_H

E6

VDD_FB_L

W9

VDDIO_FB_H

Y9

VDDIO_FB_L

A9

CLKIN_H

A8

CLKIN_L

G10

DBRDY

AA9

TMS

AC9

TCK

AD9

TRST_L

AF9

TDI
TEST25_HE9TEST29_H

E8

TEST25_L

G9

TEST19

H10

TEST18

AA7

TEST13

C2

TEST9

D7

TEST17

E7

TEST16

F7

TEST15

C7

TEST14

AC8

TEST12

C3

TEST7

AA6

TEST6

W7

THERMDC

W8

THERMDA

Y6

TEST3

AB6

TEST2

P20

RSVD0

P19

RSVD1

N20

RSVD2

N19

RSVD3

R26

RSVD4

R25

RSVD5

P22

RSVD6

R22

RSVD7

THERMDA_CPU

2200P_0402_50V7K

THERMDC_CPU

EC_SMB_CK226
EC_SMB_DA226

2007/1/25 2008/01/25

CPU1D

THERMTRIP_L

PROCHOT_L

VID5
VID4
VID3
VID2
VID1
VID0

CPU_PRESENT_L

PSI_L

DBREQ_L

TDO

TEST29_L

TEST24
TEST23

MISC

TEST22
TEST21
TEST20

TEST28_H

TEST28_L

TEST27
TEST26
TEST10

TEST8

RSVD8
RSVD9

RSVD10
RSVD11

RSVD12
RSVD13
RSVD14

RSVD15
RSVD16
RSVD17
RSVD18
RSVD19
RSVD20

1

C396

2

EC_SMB_CK2
EC_SMB_DA2

SMBus Address: 1001110X (b)

Compal Secret Data

Deciphered Date

AF6
AC7

A5
C6
A6
A4
C5
B5

AC6
A3

E10

AE9

C9
C8

AE7
AD7
AE8
AB8
AF7

J7
H8
AF8
AE6
K8
C4

H16
B18

B3
C1

H6
G6
D5

R24
W18
R23
AA8
H18
H19

2

+1.8V

12

12

R227

CPU_THERMTRIP#_R
CPU_PROCHOT#_1.8

VID5
VID4
VID3
VID2
VID1
VID0

CPU_PRESENT#
CPU_PSI#

CPU_DBREQ#

CPU_TDO

CPU_TEST29_H_FBCLKOUT_P
CPU_TEST29_L_FBCLKOUT_N

ROUTE AS 80 Ohm DIFFERENTIAL PAIR
PLACE IT CLOSE TO CPU WITHIN 1"

CPU_TEST24_SCANCLK1
CPU_TEST23_TSTUPD
CPU_TEST22_SCANSHIFTEN
CPU_TEST21_SCANEN
CPU_TEST20_SCANCLK2

CPU_TEST26_BURNIN#

CPU_MA_RESET#
CPU_MB_RESET#

CPU_RSVD_VIDSTRB1
CPU_RSVD_VIDSTRB0

CPU_RSVD_VDDNB_FB_P
CPU_RSVD_VDDNB_FB_N
CPU_RSVD_CORE_TYPE

AMD NPT S1 SOCKET
Processor Socket

U19

2

D+

3

D-

8

SCLK

7

SDATA

ADM1032ARMZ MSOP 8P

2

300_0402_5%

TP50

CPU_PSI# 36

+3VS

1

C395

0.1U_0402_16V7K~N

2

VDD1

ALERT#

THERM#

GND

1
6
4
5

+1.8V +3VALW

R254

R221

Q41

300_0402_5%

1 2

300_0402_5%

3 1

MMBT3904_NL_SOT23

R44

80.6_0402_1%

1 2

TP27
TP31
TP29
TP32
TP28

TP14
TP48

TP47 R47 300_0402_5%
TP41 R46 510_0402_5%

TP37
TP38
TP22

12

THERM#

1

2006-10-02 unpop (ATI recommend)

R229

R220

@

1 2
2

10K_0402_5%

4.7K_0402_5%

1 2

H_THERMTRIP# 16

+1.8V

VID5 36
VID4 36
VID3 36
VID2 36
VID1 36
VID0 36

CPU_PROCHOT#_1.8

CPU_TEST26_BURNIN#
CPU_PRESENT#
CPU_TEST25_H_BYPASSCLK_H

CPU_TEST21_SCANEN
CPU_TEST19_PLLTEST0
CPU_TEST25_L_BYPASSCLK_L
CPU_TEST18_PLLTEST1

MMBT3904_NL_SOT23

@

@

+3VALW

R219

1 2

10K_0402_5%

R218

CPU_PH_G

@

1 2

2

Q40

CPU_PROCHOT#

31

R225 300_0402_5%

1 2

R224 1K_0402_5%

1 2

R45 510_0402_5%

1 2

R230 300_0402_5%

1 2
1 2
1 2

R50 300_0402_5%

1 2

4.7K_0402_5%

TP25

+1.8V

Thermal Sensor
ADM1032

R232

10K_0402_5%@

CPU_PROCHOT#

R231 0_0402_5%

Title

Size Document Number Rev

Custom

Date: Sheet

12

@

Compal Electronics, Inc.

TURION64 CTRL & ADM1032

LA-3611P

1

640Wednesday, April 11, 2007

of

0.4

5

4

3

2

1

Athlon 64 S1
Processor Socket

1

C70

2

180P_0402_50V8J~N

C436

1000P_0402_50V7K~N

CPU1F

VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77
VSS78
VSS79
VSS80
VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS97
VSS98

VSS99
VSS100
VSS101

Ground

VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129

C89

180P_0402_50V8J~N

C434

1000P_0402_50V7K~N

J6
J8
J10
J12
J14
J16
J18
K2
K7
K9
K11
K13
K15
K17
L6
L8
L10
L12
L14
L16
L18
M7
M9
M11
M17
N4
N8
N10
N16
N18
P2
P7
P9
P11
P17
R8
R10
R16
R18
T7
T9
T11
T13
T15
T17
U4
U6
U8
U10
U12
U14
U16
U18
V2
V7
V9
V11
V13
V15
V17
W6
Y21
Y23
N6

+1.8V

330U_D2E_2.5VM

330U_D2E_2.5VM

1

1

C92

C166

+

+

@

2

2

2

2

1

C388

1

180P_0402_50V8J~N

180P_0402_50V8J~N

C437

2

2

1

C462

1

C463

180P_0402_50V8J~N

180P_0402_50V8J~N

AA4

VSS1

AA11

VSS2

AA13

VSS3

AA15

VSS4

AA17

VSS5

AA19

+CPU_CORE +CPU_CORE

AC4

VDD1

AD2

VDD2

G4

VDD3

H2

D D

BOTTOMSIDE DECOUPLING

+CPU_CORE

330U_D2E_2.5VM

1

proadlizer 1200uF

C C

PLACE CLOSE TO SO-DIMM1 AS POSSIBLE

+1.8V

0.1U_0402_16V7K~N

0.1U_0402_16V7K~N

1

2

C85

B B

A A

+1.8V

0.1U_0402_16V7K~N

0.1U_0402_16V7K~N

1

2

C88

0.1U_0402_16V7K~N

0.1U_0402_16V7K~N

1

1

2

2

C84

C60

PLACE CLOSE TO SO-DIMM2 AS POSSIBLE

0.1U_0402_16V7K~N

0.1U_0402_16V7K~N

1

1

2

2

C109

C62

2

+

PC44
1200P_PFAF250E128MNTTE_2.5VM

3 4

+1.8V

1

1

C69

C101

2

2

10U_0805_6.3V6M

10U_0805_6.3V6M

0.1U_0402_16V7K~N

0.1U_0402_16V7K~N

1

1

2

2

C50

C96

0.1U_0402_16V7K~N

0.1U_0402_16V7K~N

1

1

2

2

C73

C83

1

2

1

2

C67

C405

0.1U_0402_16V7K~N

0.1U_0402_16V7K~N

0.1U_0402_16V7K~N

1

2

1

2

C409

C402

0.1U_0402_16V7K~N

1

2

C406

0.1U_0402_16V7K~N

0.1U_0402_16V7K~N

1

2

C400

C403

C385

@

1

1

C398

2

2

0.22U_0603_10V7K

0.1U_0402_16V7K~N

1

1

2

2

C74

C108

0.1U_0402_16V7K~N

1

1

2

2

C399

C99

330U_D2E_2.5VM

1

1

C386

+

+

@

2

2

0.22U_0603_10V7K

0.1U_0402_16V7K~N

0.1U_0402_16V7K~N

C126

C55

1

1

C100

2

2

4.7U_0805_6.3V6K~N

4.7U_0805_6.3V6K~N

1

1

C48

2

2

4.7U_0805_6.3V6K~N

4.7U_0805_6.3V6K~N

1

1

2

2

C77

C87

0.1U_0402_16V7K~N

0.1U_0402_16V7K~N

1

1

2

2

C61

C68

VDD4

J9

VDD5

J11

VDD6

J13

VDD7

K6

VDD8

K10

VDD9

K12

VDD10

K14

VDD11

L4

VDD12

L7

VDD13

L9

VDD14

L11

VDD15

L13

VDD16

M2

VDD17

M6

VDD18

M8

VDD19

M10

VDD20

N7

VDD21

N9

VDD22

N11

VDD23

P8

VDD24

P10

VDD25

R4

VDD26

R7

VDD27

R9

VDD28

R11

VDD29

T2

VDD30

T6

VDD31

T8

VDD32

T10

VDD33

T12

VDD34

T14

VDD35

U7

VDD36

U9

VDD37

U11

VDD38

U13

VDD39

V6

VDD40

V8

VDD41

V10

VDD42

CPU1E

V12

VDD43

V14

VDD44

W4

VDD45

Y2

VDD46

J15

VDD47

K16

VDD48

L15

VDD49

M16

VDD50

P16

VDD51

T16

VDD52

U15

VDD53

V16

Athlon 64 S1
Processor Socket

VDD54

VDDIO1
VDDIO2
VDDIO3
VDDIO4
VDDIO5
VDDIO6
VDDIO7
VDDIO8
VDDIO9

VDDIO10

Power

VDDIO11
VDDIO12
VDDIO13
VDDIO14
VDDIO15
VDDIO16
VDDIO17
VDDIO18
VDDIO19
VDDIO20
VDDIO21
VDDIO22
VDDIO23
VDDIO24
VDDIO25
VDDIO26
VDDIO27

+1.8V+CPU_CORE

H25
J17
K18
K21
K23
K25
L17
M18
M21
M23
M25
N17
P18
P21
P23
P25
R17
T18
T21
T23
T25
U17
V18
V21
V23
V25
Y25

DECOUPLING BETWEEN PROCESSOR AND DIMMs
PLACE CLOSE TO PROCESSOR AS POSSIBLE

+1.8V

C391

1

1

C49

C397

2

2

4.7U_0805_6.3V6K~N

+0.9V

1

2

1

1

C447

C461

2

2

4.7U_0805_6.3V6K~N

4.7U_0805_6.3V6K~N

1

1

C125

C423

2

2

4.7U_0805_6.3V6K~N

4.7U_0805_6.3V6K~N

1

1

C52

C111

2

2

4.7U_0805_6.3V6K~N

4.7U_0805_6.3V6K~N

1

1

C401

C408

2

2

0.22U_0603_10V7K

4.7U_0805_6.3V6K~N

1

C464

C448

2

0.22U_0603_10V7K

4.7U_0805_6.3V6K~N

1

1

C404

C102

2

0.22U_0603_10V7K

1

2

0.22U_0603_10V7K

C390

C91

2

0.22U_0603_10V7K

0.22U_0603_10V7K

1

1

C387

C389

2

2

0.22U_0603_10V7K

0.22U_0603_10V7K

VSS6

AB2

VSS7

AB7

VSS8

AB9

VSS9

AB23

VSS10

AB25

VSS11

AC11

VSS12

AC13

VSS13

AC15

VSS14

AC17

VSS15

AC19

VSS16

AC21

VSS17

AD6

VSS18

AD8

VSS19

AD25

VSS20

AE11

VSS21

AE13

VSS22

AE15

VSS23

AE17

VSS24

AE19

VSS25

AE21

VSS26

AE23

VSS27

B4

VSS28

B6

VSS29

B8

VSS30

B9

VSS31

B11

VSS32

B13

VSS33

B15

VSS34

B17

VSS35

B19

VSS36

B21

VSS37

B23

VSS38

B25

VSS39

D6

VSS40

D8

VSS41

D9

VSS42

D11

VSS43

D13

VSS44

D15

VSS45

D17

VSS46

D19

VSS47

D21

VSS48

D23

VSS49

D25

VSS50

E4

VSS51

F2

VSS52

F11

VSS53

F13

VSS54

F15

VSS55

F17

VSS56

F19

VSS57

F21

VSS58

F23

VSS59

F25

VSS60

H7

VSS61

H9

VSS62

H21

VSS63

H23

VSS64

J4

VSS65

1

C90

2

0.01U_0402_16V7K

0.01U_0402_16V7K

C435

1000P_0402_50V7K~N

1000P_0402_50V7K~N

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2007/1/25 2008/01/25

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

Compal Electronics, Inc.

TURION64 PWR & GND

LA-3611P

1

0.4

of

740Wednesday, April 11, 2007

5

JDIM1

1

VREF

3

DDR_A_D0

D D

C C

DDR_CKE0_DIMMA5
DDR_CS2_DIMMA#5

DDR_A_BS#25

DDR_A_BS#05
DDR_A_WE#5

DDR_A_CAS#5
DDR_CS1_DIMMA#5

DDR_A_ODT15

B B

A A

SMB_CK_DAT19,13,16,27

SMB_CK_CLK19,13,16,27

DDR_A_D1
DDR_A_DQS#0

DDR_A_DQS0
DDR_A_D2

DDR_A_D3
DDR_A_D8

DDR_A_D9
DDR_A_DQS#1

DDR_A_DQS1
DDR_A_D10

DDR_A_D11

DDR_A_D16
DDR_A_D17

DDR_A_DQS#2
DDR_A_DQS2

DDR_A_D18 DDR_A_D22
DDR_A_D19

DDR_A_D24
DDR_A_D25

DDR_A_DM3

DDR_A_D26
DDR_A_D27

DDR_CKE0_DIMMA
DDR_CS2_DIMMA#

DDR_A_BS#2
DDR_A_MA12

DDR_A_MA9

DDR_A_MA5
DDR_A_MA3
DDR_A_MA1

DDR_A_MA10
DDR_A_BS#0
DDR_A_WE#

DDR_A_CAS#
DDR_CS1_DIMMA#

DDR_A_ODT1
DDR_A_D32

DDR_A_D33
DDR_A_DQS#4

DDR_A_DQS4
DDR_A_D34

DDR_A_D35
DDR_A_D40

DDR_A_D41
DDR_A_DM5
DDR_A_D42

DDR_A_D43 DDR_A_D47
DDR_A_D48

DDR_A_D49 DDR_A_D53

DDR_A_DQS#6
DDR_A_DQS6

DDR_A_D50
DDR_A_D51 DDR_A_D55

DDR_A_D56
DDR_A_D57

DDR_A_DM7
DDR_A_D58

DDR_A_D59
SMB_CK_DAT1

SMB_CK_CLK1

+3VS

5

VSS

5

DQ0

7

DQ1

9

VSS

11

DQS0#

13

DQS0

15

VSS

17

DQ2

19

DQ3

21

VSS

23

DQ8

25

DQ9

27

VSS

29

DQS1#

31

DQS1

33

VSS

35

DQ10

37

DQ11

39

VSS

41

VSS

43

DQ16

45

DQ17

47

VSS

49

DQS2#

51

DQS2

53

VSS

55

DQ18

57

DQ19

59

VSS

61

DQ24

63

DQ25

65

VSS

67

DM3

69

NC

71

VSS

73

DQ26

75

DQ27

77

VSS

79

CKE0

81

VDD

83

NC

85

BA2

87

VDD

89

A12

91

A9

93

A8

95

VDD

97

A5

99

A3

101

A1

103

VDD

105

A10/AP

107

BA0

109

WE#

111

VDD

113

CAS#

115

NC/S1#

117

VDD

119

NC/ODT1

121

VSS

123

DQ32

125

DQ33

127

VSS

129

DQS4#

131

DQS4

133

VSS

135

DQ34

137

DQ35

139

VSS

141

DQ40

143

DQ41

145

VSS

147

DM5

149

VSS

151

DQ42

153

DQ43

155

VSS

157

DQ48

159

DQ49

161

VSS

163

NC,TEST

165

VSS

167

DQS6#

169

DQS6

171

VSS

173

DQ50

175

DQ51

177

VSS

179

DQ56

181

DQ57

183

VSS

185

DM7

187

VSS

189

DQ58

191

DQ59

193

VSS

195

SDA

197

SCL

199

VDDSPD

P-TWO_A5692C-A0G16

CONN@

VSS
DQ4
DQ5

VSS
DM0
VSS
DQ6
DQ7
VSS

DQ12
DQ13

VSS
DM1
VSS

CK0

CK0#

VSS

DQ14
DQ15

VSS

VSS

DQ20
DQ21

VSS
DM2

VSS

DQ22
DQ23

VSS

DQ28
DQ29

VSS

DQS3#

DQS3

VSS

DQ30
DQ31

VSS

NC/CKE1

VDD

NC/A15
NC/A14

VDD

A11

VDD

VDD

BA1

RAS#

S0#
VDD

ODT0

NC/A13

VDD
VSS

DQ36
DQ37

VSS
DM4
VSS

DQ38
DQ39

VSS

DQ44
DQ45

VSS

DQS5#

DQS5

VSS

DQ46
DQ47

VSS

DQ52
DQ53

VSS

CK1

CK1#

VSS
DM6
VSS

DQ54
DQ55

VSS

DQ60
DQ61

VSS

DQS7#

DQS7

VSS

DQ62
DQ63

VSS
SAO

SA1

4

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

42
44
46
48
50

NC

52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92

A7

94

A6

96
98

A4

100

A2

102

A0

104
106
108
110
112
114
116
118
120

NC

122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200

4

DDR_A_D4
DDR_A_D5

DDR_A_DM0
DDR_A_D6

DDR_A_D7
DDR_A_D12

DDR_A_D13
DDR_A_DM1
DDR_A_CLK1

DDR_A_CLK#1
DDR_A_D14

DDR_A_D15

DDR_A_D20
DDR_A_D21

DDR_A_DM2

DDR_A_D23
DDR_A_D28

DDR_A_D29
DDR_A_DQS#3

DDR_A_DQS3
DDR_A_D30

DDR_A_D31
DDR_CKE1_DIMMA
DDR_A_MA15

DDR_A_MA14
DDR_A_MA11

DDR_A_MA7
DDR_A_MA6DDR_A_MA8

DDR_A_MA4
DDR_A_MA2
DDR_A_MA0

DDR_A_BS#1
DDR_A_RAS#
DDR_CS0_DIMMA#

DDR_A_ODT0
DDR_A_MA13

DDR_CS3_DIMMA#
DDR_A_D36

DDR_A_D37
DDR_A_DM4
DDR_A_D38

DDR_A_D39
DDR_A_D44

DDR_A_D45
DDR_A_DQS#5

DDR_A_DQS5
DDR_A_D46

DDR_A_D52

DDR_A_CLK2
DDR_A_CLK#2

DDR_A_DM6
DDR_A_D54

DDR_A_D60
DDR_A_D61

DDR_A_DQS#7
DDR_A_DQS7

DDR_A_D62
DDR_A_D63

R28 0_0402_5%

12
12

R25 0_0402_5%

DDR_A_CLK1 5
DDR_A_CLK#1 5

DDR_CKE1_DIMMA 5

DDR_A_BS#1 5
DDR_A_RAS# 5
DDR_CS0_DIMMA# 5

DDR_A_ODT0 5

DDR_CS3_DIMMA# 5

DDR_A_CLK2 5
DDR_A_CLK#2 5

3

2007-01-17 Add

1

C181

2

1000P_0402_50V7K~N

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

+1.8V+DIMM_VREF+1.8V+1.8V

1

C179

2

0.1U_0402_16V7K~N

1

C180

2

0.1U_0402_16V7K~N

R78

1K_0402_1%

1 2

R79

1K_0402_1%

1 2

2007/1/25 2008/01/25

+1.8V

0.1U_0402_16V7K~N

1

2

C95

+0.9V

+0.9V

0.1U_0402_16V7K~N

1

2

C75

Compal Secret Data

Deciphered Date

2

0.1U_0402_16V7K~N

1

2

0.1U_0402_16V7K~N

1

2

DDR_A_D[0..63]
DDR_A_DM[0..7]
DDR_A_DQS[0..7]
DDR_A_MA[0..15]
DDR_A_DQS#[0..7]

0.1U_0402_16V7K~N

C93

0.1U_0402_16V7K~N

C81

DDR_CKE1_DIMMA
DDR_A_MA7
DDR_A_MA14
DDR_A_MA15

DDR_A_CAS#
DDR_A_MA10
DDR_A_BS#0
DDR_A_MA1

DDR_A_MA2
DDR_A_BS#1
DDR_A_MA0
DDR_A_RAS#

DDR_A_MA9
DDR_A_MA5
DDR_A_MA3
DDR_A_MA8

DDR_A_MA11
DDR_A_MA6
DDR_A_MA4

DDR_A_ODT1
DDR_CS1_DIMMA#

DDR_A_WE#

DDR_CS0_DIMMA#
DDR_A_MA13
DDR_A_ODT0
DDR_CS3_DIMMA#

DDR_A_BS#2
DDR_A_MA12
DDR_CKE0_DIMMA
DDR_CS2_DIMMA#

DDR_A_D[0..63]5
DDR_A_DM[0..7]5

DDR_A_DQS[0..7]5
DDR_A_MA[0..15]5

DDR_A_DQS#[0..7]5

0.1U_0402_16V7K~N

0.1U_0402_16V7K~N

1

1

0.1U_0402_16V7K~N

2

2

C104

C103

0.1U_0402_16V7K~N

1

1

2

2

C98

C58

2

1

2

1

2

C71

C106

1

Layout Note:
Place one cap close to every 2 pullup
resistors terminated to +0.9V

0.1U_0402_16V7K~N

1

2

C94

0.1U_0402_16V7K~N

1

2

C72

47_0804_8P4R_5%

47_0804_8P4R_5%

47_0804_8P4R_5%

47_0804_8P4R_5%

47_0804_8P4R_5%

47_0804_8P4R_5%

Title

Size Document Number Rev

Custom

Date: Sheet

0.1U_0402_16V7K~N

0.1U_0402_16V7K~N

1

1

0.1U_0402_16V7K~N

47_0804_8P4R_5%

47_0804_8P4R_5%

2

2

C132

C80

Layout Note:
Place one cap close to every 2 pullup
resistors terminated to +0.9V

C110

+0.9V

+0.9V

330U_D2E_2.5VM

1

C47

+

2

@

0.1U_0402_16V7K~N

1

1

2

2

C51

RP14

18
27
36
45

RP5

18
27
36
45

RP6

18
27
36
45

RP9

18
27
36
45

RP10

18
27
36
45

RP1

18
27
36
45

RP2

18
27
36
45

RP13

18
27
36
45

DDR2 SODIMM-I Socket

LA-3611P

1

840Wednesday, April 11, 2007

0.4

of

5

4

3

2

1

DDR_B_D[0..63]
DDR_B_DM[0..7]
DDR_B_DQS[0..7]
DDR_B_MA[0..15]
DDR_B_DQS#[0..7]

0.1U_0402_16V7K~N

0.1U_0402_16V7K~N

1

2

C82

0.1U_0402_16V7K~N

0.1U_0402_16V7K~N

1

2

C65

DDR_CKE1_DIMMB
DDR_B_MA14
DDR_B_MA15
DDR_B_MA11

DDR_B_MA1
DDR_B_MA3
DDR_B_MA9
DDR_B_MA12

DDR_B_BS#0
DDR_B_MA10
DDR_B_WE#
DDR_B_MA5

DDR_B_MA2
DDR_B_BS#1
DDR_CS0_DIMMB#
DDR_B_RAS#

DDR_B_ODT0
DDR_B_MA13
DDR_CS3_DIMMB#

DDR_B_ODT1
DDR_CS1_DIMMB#
DDR_B_CAS#

DDR_B_MA7
DDR_B_MA0
DDR_B_MA6
DDR_B_MA4

DDR_B_BS#2
DDR_B_MA8
DDR_CKE0_DIMMB
DDR_CS2_DIMMB#

1

2

C59

1

2

C105

0.1U_0402_16V7K~N

1

Layout Note:
Place one cap close to every 2 pullup

2

C63

resistors terminated to +0.9V

0.1U_0402_16V7K~N

Layout Note:

1

Place one cap close to every 2 pullup
resistors terminated to +0.9V

2

C56

+0.9V

RP16

18
27
36

47_0804_8P4R_5%

47_0804_8P4R_5%

47_0804_8P4R_5%

47_0804_8P4R_5%

47_0804_8P4R_5%

47_0804_8P4R_5%

47_0804_8P4R_5%

47_0804_8P4R_5%

45

RP11

18
27
36
45

RP7

18
27
36
45

RP8

18
27
36
45

RP4

18
27
36
45

RP3

18
27
36
45

RP12

18
27
36
45

RP15

18
27
36
45

Title

DDR2 SODIMM-II Socket

Size Document Number Rev

Custom

LA-3611P

Date: Sheet

1

940Wednesday, April 11, 2007

0.4

of

0.1U_0402_16V7K~N

1

2

C97

0.1U_0402_16V7K~N

1

2

C57

Deciphered Date

DDR_B_D[0..63]5
DDR_B_DM[0..7]5

DDR_B_DQS[0..7]5
DDR_B_MA[0..15]5

DDR_B_DQS#[0..7]5

0.1U_0402_16V7K~N

0.1U_0402_16V7K~N

1

1

2

2

C64

C86

0.1U_0402_16V7K~N

0.1U_0402_16V7K~N

1

1

2

2

C66

C79

2

+DIMM_VREF+1.8V+1.8V

JDIM2

1

VREF

3

DDR_B_D0

D D

C C

DDR_CKE0_DIMMB5
DDR_CS2_DIMMB#5

DDR_B_BS#25

DDR_B_BS#05
DDR_B_WE#5

DDR_B_CAS#5
DDR_CS1_DIMMB#5

DDR_B_ODT15

B B

A A

SMB_CK_DAT18,13,16,27

SMB_CK_CLK18,13,16,27

DDR_B_D1
DDR_B_DQS#0

DDR_B_DQS0
DDR_B_D2

DDR_B_D3
DDR_B_D8

DDR_B_D9
DDR_B_DQS#1

DDR_B_DQS1
DDR_B_D10

DDR_B_D11

DDR_B_D16
DDR_B_D17

DDR_B_DQS#2
DDR_B_DQS2

DDR_B_D18 DDR_B_D22
DDR_B_D19

DDR_B_D24
DDR_B_D25

DDR_B_DM3

DDR_B_D26
DDR_B_D27

DDR_CKE0_DIMMB
DDR_CS2_DIMMB#

DDR_B_BS#2
DDR_B_MA12

DDR_B_MA9

DDR_B_MA5
DDR_B_MA3
DDR_B_MA1

DDR_B_MA10
DDR_B_BS#0
DDR_B_WE#

DDR_B_CAS#
DDR_CS1_DIMMB#

DDR_B_ODT1
DDR_B_D32

DDR_B_D33
DDR_B_DQS#4

DDR_B_DQS4
DDR_B_D34

DDR_B_D35
DDR_B_D40

DDR_B_D41
DDR_B_DM5
DDR_B_D42

DDR_B_D43 DDR_B_D47
DDR_B_D48

DDR_B_D49 DDR_B_D53

DDR_B_DQS#6
DDR_B_DQS6

DDR_B_D50
DDR_B_D51 DDR_B_D55

DDR_B_D56
DDR_B_D57

DDR_B_DM7
DDR_B_D58

DDR_B_D59
SMB_CK_DAT1

SMB_CK_CLK1

+3VS

5

VSS

5

DQ0

7

DQ1

9

VSS

11

DQS0#

13

DQS0

15

VSS

17

DQ2

19

DQ3

21

VSS

23

DQ8

25

DQ9

27

VSS

29

DQS1#

31

DQS1

33

VSS

35

DQ10

37

DQ11

39

VSS

41

VSS

43

DQ16

45

DQ17

47

VSS

49

DQS2#

51

DQS2

53

VSS

55

DQ18

57

DQ19

59

VSS

61

DQ24

63

DQ25

65

VSS

67

DM3

69

NC

71

VSS

73

DQ26

75

DQ27

77

VSS

79

CKE0

81

VDD

83

NC

85

BA2

87

VDD

89

A12

91

A9

93

A8

95

VDD

97

A5

99

A3

101

A1

103

VDD

105

A10/AP

107

BA0

109

WE#

111

VDD

113

CAS#

115

NC/S1#

117

VDD

119

NC/ODT1

121

VSS

123

DQ32

125

DQ33

127

VSS

129

DQS4#

131

DQS4

133

VSS

135

DQ34

137

DQ35

139

VSS

141

DQ40

143

DQ41

145

VSS

147

DM5

149

VSS

151

DQ42

153

DQ43

155

VSS

157

DQ48

159

DQ49

161

VSS

163

NC,TEST

165

VSS

167

DQS6#

169

DQS6

171

VSS

173

DQ50

175

DQ51

177

VSS

179

DQ56

181

DQ57

183

VSS

185

DM7

187

VSS

189

DQ58

191

DQ59

193

VSS

195

SDA

197

SCL

199

VDDSPD

P-TWO_A5652C-A0G16

CONN@

VSS
DQ4
DQ5
VSS
DM0
VSS
DQ6
DQ7
VSS

DQ12
DQ13

VSS
DM1
VSS

CK0

CK0#

VSS

DQ14
DQ15

VSS

VSS

DQ20
DQ21

VSS
DM2

VSS

DQ22
DQ23

VSS

DQ28
DQ29

VSS

DQS3#

DQS3

VSS

DQ30
DQ31

VSS

NC/CKE1

VDD

NC/A15
NC/A14

VDD

A11

VDD

VDD

BA1

RAS#

S0#
VDD

ODT0

NC/A13

VDD
VSS

DQ36
DQ37

VSS
DM4
VSS

DQ38
DQ39

VSS

DQ44
DQ45

VSS

DQS5#

DQS5

VSS

DQ46
DQ47

VSS

DQ52
DQ53

VSS

CK1

CK1#

VSS
DM6
VSS

DQ54
DQ55

VSS

DQ60
DQ61

VSS

DQS7#

DQS7

VSS

DQ62
DQ63

VSS
SAO

SA1

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

42
44
46
48
50

NC

52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92

A7

94

A6

96
98

A4

100

A2

102

A0

104
106
108
110
112
114
116
118
120

NC

122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200

4

DDR_B_D4
DDR_B_D5

DDR_B_DM0
DDR_B_D6

DDR_B_D7
DDR_B_D12

DDR_B_D13
DDR_B_DM1
DDR_B_CLK1

DDR_B_CLK#1
DDR_B_D14

DDR_B_D15

DDR_B_D20
DDR_B_D21

DDR_B_DM2

DDR_B_D23
DDR_B_D28

DDR_B_D29
DDR_B_DQS#3

DDR_B_DQS3
DDR_B_D30

DDR_B_D31
DDR_CKE1_DIMMB
DDR_B_MA15

DDR_B_MA14
DDR_B_MA11

DDR_B_MA7
DDR_B_MA6DDR_B_MA8

DDR_B_MA4
DDR_B_MA2
DDR_B_MA0

DDR_B_BS#1
DDR_B_RAS#
DDR_CS0_DIMMB#

DDR_B_ODT0
DDR_B_MA13

DDR_CS3_DIMMB#
DDR_B_D36

DDR_B_D37
DDR_B_DM4
DDR_B_D38

DDR_B_D39
DDR_B_D44

DDR_B_D45
DDR_B_DQS#5

DDR_B_DQS5
DDR_B_D46

DDR_B_D52

DDR_B_CLK2
DDR_B_CLK#2

DDR_B_DM6
DDR_B_D54

DDR_B_D60
DDR_B_D61

DDR_B_DQS#7
DDR_B_DQS7

DDR_B_D62
DDR_B_D63

R26 4.7K_0402_5%

1 2

R27 0_0402_5%

12

DDR_B_CLK1 5
DDR_B_CLK#1 5

DDR_CKE1_DIMMB 5

DDR_B_BS#1 5
DDR_B_RAS# 5
DDR_CS0_DIMMB# 5

DDR_B_ODT0 5

DDR_CS3_DIMMB# 5

DDR_B_CLK2 5
DDR_B_CLK#2 5

+3VS

1

C182

2

1000P_0402_50V7K~N

C142

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

+0.9V

0.1U_0402_16V7K~N

0.1U_0402_16V7K~N

330U_D2E_2.5VM

1

+

2

2007/1/25 2008/01/25

0.1U_0402_16V7K~N

+1.8V

+0.9V

1

2

1

2

C107

C76

0.1U_0402_16V7K~N

1

2

C112

1

2

C78

Compal Secret Data

5

D D

4

3

2

1

H_CADIP[0..15]4
H_CADIN[0..15]4

H_CLKOP1
H_CLKON1

H_CLKOP0
H_CLKON0

H_CTLOP0
H_CTLON0

H_CADOP[0..15]4

H_CADON[0..15]4

U690A

R19

HT_RXCAD15P

R18

HT_RXCAD15N

R21

HT_RXCAD14P

R22

HT_RXCAD14N

U22

HT_RXCAD13P

U21

HT_RXCAD13N

U18

HT_RXCAD12P

U19

HT_RXCAD12N

W19

HT_RXCAD11P

W20

HT_RXCAD11N

AC21

HT_RXCAD10P

AB22

HT_RXCAD10N

AB20

HT_RXCAD9P

AA20

HT_RXCAD9N

AA19

HT_RXCAD8P

Y19

HT_RXCAD8N

T24

HT_RXCAD7P

R25

HT_RXCAD7N

U25

HT_RXCAD6P

U24

HT_RXCAD6N

V23

HT_RXCAD5P

U23

HT_RXCAD5N

V24

HT_RXCAD4P

V25

HT_RXCAD4N

AA25

HT_RXCAD3P

AA24

HT_RXCAD3N

AB23

HT_RXCAD2P

AA23

HT_RXCAD2N

AB24

HT_RXCAD1P

AB25

HT_RXCAD1N

AC24

HT_RXCAD0P

AC25

HT_RXCAD0N

W21

HT_RXCLK1P

W22

HT_RXCLK1N

Y24

HT_RXCLK0P

W25

HT_RXCLK0N

P24

HT_RXCTLP

P25

HT_RXCTLN

A24

HT_RXCALP

C24

HT_RXCALN

216MQA6AVA11FG FCBGA 465P

U690B

G5

GFX_RX0P

G4

GFX_RX0N

J8

GFX_RX1P

J7

GFX_RX1N

J4

GFX_RX2P

J5

GFX_RX2N

L8

GFX_RX3P

L7

GFX_RX3N

L4

GFX_RX4P

L5

GFX_RX4N

M8

GFX_RX5P

M7

GFX_RX5N

M4

GFX_RX6P

M5

C C

PCIE_LAN_C_RX_P222
PCIE_LAN_C_RX_N222

PCIE_WLAN_C_RX_P125
PCIE_WLAN_C_RX_N125

SB_RX2P15
SB_RX2N15

SB_RX3P15

B B

SB_RX3N15

SB_RX0P15
SB_RX0N15

SB_RX1P15
SB_RX1N15

PCIE_LAN_C_RX_P2
PCIE_LAN_C_RX_N2

PCIE_WLAN_C_RX_P1
PCIE_WLAN_C_RX_N1

SB_RX2P
SB_RX2N

SB_RX3P
SB_RX3N

SB_RX0P
SB_RX0N

SB_RX1P
SB_RX1N

GFX_RX6N

P8

GFX_RX7P

P7

GFX_RX7N

P4

GFX_RX8P

P5

GFX_RX8N

R4

GFX_RX9P

R5

GFX_RX9N

R7

GFX_RX10P

R8

GFX_RX10N

U4

GFX_RX11P

U5

GFX_RX11N

W4

GFX_RX12P

W5

GFX_RX12N

Y4

GFX_RX13P

Y5

GFX_RX13N

V9

GFX_RX14P

W9

GFX_RX14N

AB7

GFX_RX15P

AB6

GFX_RX15N

Y7

GPP_RX2P

AA7

GPP_RX2N

AB9

GPP_RX3P

AA9

GPP_RX3N

W11

GPP_RX0P(SB_RX2P)

W12

GPP_RX0N(SB_RX2N)

AA11

GPP_RX1P(SB_RX3P)

AB11

GPP_RX1N(SB_RX3N)

W14

SB_RX0P

W15

SB_RX0N

AB12

SB_RX1P

AA12

SB_RX1N

AA14

PCE_ISET(NC)

AB14

PCE_TXISET(NC)

216MQA6AVA11FG FCBGA 465P

PART 2 OF 5

PCIE GFX I/F

PCIE I/F GPP

GPP_TX0P(SB_TX2P)

GPP_TX0N(SB_TX2N)

GPP_TX1P(SB_TX3P)
GPP_TX1N(SB_TX3N)

PCIE I/F SB

PCE_PCAL(PCE_CALRP)
PCE_NCAL(PCE_CALRN)

GFX_TX0P
GFX_TX0N
GFX_TX1P
GFX_TX1N
GFX_TX2P
GFX_TX2N
GFX_TX3P
GFX_TX3N
GFX_TX4P
GFX_TX4N
GFX_TX5P
GFX_TX5N
GFX_TX6P
GFX_TX6N
GFX_TX7P
GFX_TX7N
GFX_TX8P
GFX_TX8N
GFX_TX9P

GFX_TX9N
GFX_TX10P
GFX_TX10N
GFX_TX11P
GFX_TX11N
GFX_TX12P
GFX_TX12N
GFX_TX13P
GFX_TX13N
GFX_TX14P
GFX_TX14N
GFX_TX15P
GFX_TX15N

GPP_TX2P

GPP_TX2N

GPP_TX3P

GPP_TX3N

SB_TX0P
SB_TX0N

SB_TX1P
SB_TX1N

J1
H2
K2
K1
K3
L3
L1
L2
N2
N1
P2
P1
P3
R3
R1
R2
T2
U1
V2
V1
V3
W3
W1
W2
Y2
AA1
AA2
AB2
AB1
AC1
AE3
AE4

PCIE_LAN_TX_P2

AD4
AE5

AD5

PCIE_WLAN_TX_N1

AD6

SB_TX2P_C

AD8

SB_TX2N_C

AE8

SB_TX3P_C

AD7

SB_TX3N_C

AE7

SB_TX0P_C

AE9

SB_TX0N_C

AD10

SB_TX1P_C

AC8

SB_TX1N_C

AD9

R238 562_0402_1%

AD11

R237 2K_0402_1%

AE11

1 2
1 2

C415 0.1U_0402_16V7K~N
C416 0.1U_0402_16V7K~N

C413 0.1U_0402_16V7K~N
C414 0.1U_0402_16V7K~N

C417 0.1U_0402_16V7K~N
C418 0.1U_0402_16V7K~N

C119 0.1U_0402_16V7K~N
C120 0.1U_0402_16V7K~N

C411 0.1U_0402_16V7K~N

1 2

C412 0.1U_0402_16V7K~N

1 2

C117 0.1U_0402_16V7K~N

1 2

C118 0.1U_0402_16V7K~N

1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

+VDDA12_PKG2

PCIE_LAN_C_TX_P2
PCIE_LAN_C_TX_N2PCIE_LAN_TX_N2

PCIE_WLAN_C_TX_P1PCIE_WLAN_TX_P1
PCIE_WLAN_C_TX_N1

SB_TX2P
SB_TX2N

SB_TX3P
SB_TX3N

SB_TX0P
SB_TX0N

SB_TX1P
SB_TX1N

SB_TX2P 15
SB_TX2N 15

SB_TX3P 15
SB_TX3N 15

SB_TX0P 15
SB_TX0N 15

SB_TX1P 15
SB_TX1N 15

PCIE_LAN_C_TX_P2 22
PCIE_LAN_C_TX_N2 22

PCIE_WLAN_C_TX_P1 25
PCIE_WLAN_C_TX_N1 25

+VDDHT_PKG

H_CLKOP14

H_CLKON14

H_CLKOP04

H_CLKON04

H_CTLOP04
H_CTLON04

R282 49.9_0402_1%

1 2

R261 49.9_0402_1%

1 2

H_CADOP15
H_CADON15
H_CADOP14
H_CADON14
H_CADOP13
H_CADON13
H_CADOP12
H_CADON12
H_CADOP11
H_CADON11
H_CADOP10
H_CADON10
H_CADOP9
H_CADON9
H_CADOP8
H_CADON8

H_CADOP7
H_CADON7
H_CADOP6
H_CADON6
H_CADOP5
H_CADON5
H_CADOP4
H_CADON4
H_CADOP3
H_CADON3
H_CADOP2
H_CADON2
H_CADOP1
H_CADON1
H_CADOP0
H_CADON0

H_CADIP[0..15]
H_CADIN[0..15]

H_CADOP[0..15]

H_CADON[0..15]

PART 1 OF 5

HT_TXCAD15P
HT_TXCAD15N
HT_TXCAD14P
HT_TXCAD14N
HT_TXCAD13P
HT_TXCAD13N
HT_TXCAD12P
HT_TXCAD12N
HT_TXCAD11P
HT_TXCAD11N
HT_TXCAD10P
HT_TXCAD10N

HT_TXCAD9P
HT_TXCAD9N
HT_TXCAD8P
HT_TXCAD8N

HT_TXCAD7P
HT_TXCAD7N
HT_TXCAD6P
HT_TXCAD6N
HT_TXCAD5P
HT_TXCAD5N
HT_TXCAD4P
HT_TXCAD4N
HT_TXCAD3P
HT_TXCAD3N
HT_TXCAD2P
HT_TXCAD2N
HT_TXCAD1P
HT_TXCAD1N
HT_TXCAD0P
HT_TXCAD0N

HT_TXCLK1P
HT_TXCLK1N

HT_TXCLK0P
HT_TXCLK0N

HYPER TRANSPORT I/F

HT_TXCTLP
HT_TXCTLN

HT_TXCALP
HT_TXCALN

H_CADIP15

P21

H_CADIN15

P22

H_CADIP14

P18

H_CADIN14

P19

H_CADIP13

M22

H_CADIN13

M21

H_CADIP12

M18

H_CADIN12

M19

H_CADIP11

L18

H_CADIN11

L19

H_CADIP10

G22

H_CADIN10

G21

H_CADIP9

J20

H_CADIN9

J21

H_CADIP8

F21

H_CADIN8

F22

H_CADIP7

N24

H_CADIN7

N25

H_CADIP6

L25

H_CADIN6

M24

H_CADIP5

K25

H_CADIN5

K24

H_CADIP4

J23

H_CADIN4

K23

H_CADIP3

G25

H_CADIN3

H24

H_CADIP2

F25

H_CADIN2

F24

H_CADIP1

E23

H_CADIN1

F23

H_CADIP0

E24

H_CADIN0

E25

H_CLKIP1

L21

H_CLKIN1

L22

H_CLKIP0

J24

H_CLKIN0

J25

H_CTLIP0

N23

H_CTLIN0

P23

R260 100_0402_1%

C25

1 2

D24

H_CLKIP1 4
H_CLKIN1 4

H_CLKIP0 4
H_CLKIN0 4

H_CTLIP0 4

H_CTLIN0 4

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2007/1/25 2008/01/25

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

RS690MC HT / PCIE / DVI
LA-3611P

1

10 40Wednesday, April 11, 2007

0.4

of

Reserve for EMI, close to U690

NB_REFCLK

12

R63

@

33_0402_5%

2

C161

@

22P_0402_50V8J

1

HTREFCLK

12

R281

@

33_0402_5%

2

C474

@

22P_0402_50V8J

1

+1.8VS

+1.8VS

+3VS

R304

1 2

+3VS

12

R275
2K_0402_5%

NB_STRAP_DATA

12

1 2

4.7K_0402_5%

R276
2K_0402_5%

@

1 2

R57 150_0402_1%

1 2

R56 150_0402_1%

1 2

R55 150_0402_1%

+1.8VS

2006-12-30 Cap follow Bowfin2.1

L36

1 2

FBML10160808121LMT_0603

L12

1 2

FBML10160808121LMT_0603

+1.2V_HT

15mil

R273

4.7K_0402_5%

EDID_CLK_LCD

EDID_DAT_LCD

POWER PLAY
HI: 1.2V
LOW : 1.0V

VGA_CRT_R
VGA_CRT_G
VGA_CRT_B

L39

1 2

FBML10160808121LMT_0603

VGA_DDC_CLK14

1

C169

2.2U_0603_10V6K

2

15mil

1

C173
1U_0603_10V6K

2

L37

1 2

FBML10160808121LMT_0603

EDID_CLK_LCD14
EDID_DAT_LCD14

15mil

2006-12-30 Bowfin 2.1

VGA_DDC_CLK

15mil

EDID_CLK_LCD
EDID_DAT_LCD

BMREQ#15

2006-12-30 Cap follow Bowfin2.1

+3VS

L5

1 2

FBML10160808121LMT_0603

+1.8VS

15mil

1

C473

2.2U_0603_10V6K

2

R277 0_0402_5%

R62 10K_0402_5%@
R54 10K_0402_5%@
R279 10K_0402_5%@
R305 10K_0402_5%@
R278 10K_0402_5%@
R306 10K_0402_5%@

R274 0_0402_5%

+3VS

BMREQ# BMREQ#_NB

L38

1 2

FBML10160808121LMT_0603

VGA_CRT_R14
VGA_CRT_G14

VGA_CRT_B14
VGA_CRT_VSYNC14
VGA_CRT_HSYNC14

1 2

VGA_DDC_DATA14

1 2

2006-12-30 bowfin 2.1

R272

R280 715_0402_1%

NB_RST#15,19,22,25,26,27

NB_PWRGD26

ALLOW_LDTSTOP15

HTREFCLK13

NB_REFCLK13

NB_GFX_CLKP13

NB_GFX_CLKN13

SBLINKCLK13

SBLINKCLK#13

12
12
12
12
12
12

R303 4.7K_0402_5%
R302 4.7K_0402_5%

1 2

+3VS

10K_0402_5%

@

1 2

D16

2 1

RB751V_SOD323

1

C471
15P_0402_50V8D@

2

+AVDDI

1 2

12

12

@

+AVDD

1

C472

2.2U_0603_10V6K

2

+AVDDQ

VGA_CRT_R
VGA_CRT_G

VGA_CRT_B
VGA_CRT_VSYNC
VGA_CRT_HSYNC

VGA_DDC_CLK_NB
VGA_DDC_DATA

+NB_PLLVDD

+NB_HTPVDD

NB_RST#

NB_PWRGD
NB_LDTSTOP#

ALLOW_LDTSTOP

HTREFCLK

12

NB_REFCLK

NB_GFX_CLKP
NB_GFX_CLKN

SBLINKCLK

SBLINKCLK#

DFT_GPIO0
DFT_GPIO1
DFT_GPIO2
DFT_GPIO3
DFT_GPIO4
DFT_GPIO5

BMREQ#_NB

EDID_CLK_LCD_NB

NB_STRAP_DATA

15mil

1

C152

2.2U_0603_10V6K

2

R26210K_0402_5%

R25910K_0402_5%

U690C

B22
C22
G17
H17
A20
B20

A21
A22

C21
C20
D19

E19
G19

B21

A10
B10

B24
B25

C10
C11

C23
B23

B11
A11

AA15
AB15

C14

F19

C6

A5

B6
A6

C5

B5

C2

F2
E1

G1
G2

D6
D7
C8
C7

B8
A8

B2
A2
B4

B3

C3

A3

PART 3 OF 5

AVDD1
AVDD2
AVSSN1
AVSSN2
AVDDDI
AVSSDI

AVDDQ
AVSSQ

C
Y
COMP

RED
GREEN
BLUE
DACVSYNC
DACHSYNC

RSET
DACSCL

DACSDA
PLLVDD(PLLVDD18)

PLLVSS
HTPVDD

HTPVSS
SYSRESET#

POWERGOOD
LDTSTOP#
ALLOW_LDTSTOP

HTTSTCLK
HTREFCLK

TVCLKIN
OSCIN

OSCOUT(PLLVDD12)
GFX_CLKP

GFX_CLKN
SB_CLKP

SB_CLKN
DFT_GPIO0

DFT_GPIO1
DFT_GPIO2
DFT_GPIO3
DFT_GPIO4
DFT_GPIO5

BMREQ#
I2C_CLK
I2C_DATA
THERMALDIODE_P
THERMALDIODE_N

TMDS_HPD
DDC_DATA
TESTMODE
STRP_DATA

216MQA6AVA11FG FCBGA 465P

CRT/TVOUT

LVTM

LVDDR18A_1(LVDDR33_1)
LVDDR18A_2(LVDDR33_2)

PLL PWR

PMCLOCKs

DVO_D0(GPP_TX0P)
DVO_D1(GPP_TX0N)

DVO_D2(DEBUG6)

DVO_D3(GPP_RX0P)

DVO_D4(GPP_RX0N)

DVO_D5(DEBUG9)

DVO_D6(DEBUG10)
DVO_D7(GPP_TX1N)
DVO_D8(GPP_TX1P)
DVO_D9(GPP_RX1N)

DVO_D10(GPP_RX1P)

DVO

MIS.

DVO_D11(DEBUG15)

DVO_VSYNC(DEBUG0)

DVO_DE(DEBUG2)

DVO_HSYNC(DEBUG1)
DVO_IDCKP(DEBUG14)
DVO_IDCKN(DEBUG13)

LDT_STOP#6,15

TXOUT_L0P
TXOUT_L0N
TXOUT_L1P
TXOUT_L1N
TXOUT_L2P
TXOUT_L2N
TXOUT_L3P
TXOUT_L3N

TXOUT_U0P

TXOUT_U0N

TXOUT_U1P

TXOUT_U1N

TXOUT_U2P

TXOUT_U2N

TXOUT_U3P

TXOUT_U3N

TXCLK_LP
TXCLK_LN
TXCLK_UP
TXCLK_UN

LPVDD
LPVSS

LVDDR18D_1
LVDDR18D_2

LVSSR1
LVSSR3
LVSSR5
LVSSR6
LVSSR7
LVSSR8

LVSSR12
LVSSR13

LVDS_DIGON

LVDS_BLON
LVDS_BLEN

LVDSL0+

B14

LVDSL0-

B15

LVDSL1+

B13

LVDSL1-

A13

LVDSL2+

H14

LVDSL2-

G14
D17
E17

LVDSU0+

A15

LVDSU0-

B16

LVDSU1+

C17

LVDSU1-

C18

LVDSU2+

B17

LVDSU2-

A17
A18
B18

LVDSLC+

E15

LVDSLC-

D15

LVDSUC+

H15

LVDSUC-

G15
D14

E14
A12

B12
C12
C13

A16
A14
D12
C19
C15
C16

F14
F15

ENVDD_NB

E12

ENABLT_NB

G12
F12

PCIE_CARD_TX_P1

AD14

PCIE_CARD_TX_N1

AD15
AE15

PCIE_CARD_C_RX_P1

AD16

PCIE_CARD_C_RX_N1

AE16
AC17
AD18
AE19
AD19
AE20
AD20
AE21

AD13

SUS_STAT#

AC13
AE13
AE17
AD17

R239

470K_0402_5%

+1.8VS

Q44

3 1

MMBT3904_NL_SOT23

+LVDDR18D

+LVDDR33A

1 2

R84

1 2

10K_0402_5%

2

LVDSL0+ 14
LVDSL0- 14
LVDSL1+ 14
LVDSL1- 14
LVDSL2+ 14
LVDSL2- 14

LVDSU0+ 14
LVDSU0- 14
LVDSU1+ 14
LVDSU1- 14
LVDSU2+ 14
LVDSU2- 14

LVDSLC+ 14
LVDSLC- 14
LVDSUC+ 14
LVDSUC- 14

+LPVDD

0.1U_0402_16V7K~N

GND_LVSSR

R69 0_0402_5%

12

R68 0_0402_5%

12

C419 0.1U_0402_16V7K~N

1 2

C420 0.1U_0402_16V7K~N

1 2

+3VS

12

R70
10K_0402_5%

NB_LDTSTOP#

C163

+3VS

1

2

C171

4.7U_0805_6.3V6K~N

PCIE_CARD_C_TX_P1
PCIE_CARD_C_TX_N1

NB_PWRGD

L11

1

C170

2.2U_0603_10V6K

2

2

G

Q17

FBML10160808121LMT_0603

1

2

SSM3K7002FU_SC70-3

12

1

C172

2

0.1U_0402_16V7K~N

4.7U_0805_6.3V6K~N

L9

1 2

FBML10160808121LMT_0603

L10

1 2

FBML10160808121LMT_0603

ENVDD

ENVDD 14

ENABLT

ENABLT 14,26

PCIE_CARD_C_RX_P1 27
PCIE_CARD_C_RX_N1 27

+5VS

ENVDD_NB

R81

@

10K_0402_5%

1 2

NB_PWRGD5V#

13

D

ENABLT_NB

@

S

AP2301GN 1P SOT23

1

C162

2

GND_LVSSR

+1.8VS

+LVDDR33A

R71
0_0805_5%

15mil

+1.8VS

15mil

PCIE_CARD_C_TX_P1 27
PCIE_CARD_C_TX_N1 27

Q19
AP2301GN 1P SOT23

S

D

ENVDD

13

@

G

2

R83

@

G

2

ENABLT

13

D

S

@

Q18

R82

12

12

1K_0402_5%

12

1K_0402_5%

2006-09-27

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2007/1/25 2008/01/25

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

Date: Sheet

RS690MC VIDEO_IF/CLOCK GEN
LA-3611P

of

11 40Wednesday, April 11, 2007

0.4

5

+1.2V_HT

D D

0.2A

+1.8VS

0.3A

+3VS

C C

B B

C1511U_0402_6.3V6K

12

C1501U_0402_6.3V6K

12

15mil

+1.2V_HT

L3

1 2

FBMA-L11-322513-201LMA40T_1210

NB_VDDHT12

+

C407150U_D2_6.3VM

12

@

C422 22U_1206_6.3V6M

12

C122 1U_0402_6.3V6K

1 2

C124 1U_0402_6.3V6K

1 2

C123 1U_0402_6.3V6K

1 2

C131 1U_0402_6.3V6K

1 2

C421 1U_0402_6.3V6K

1 2

15mil

C1751U_0402_6.3V6K

12

C1641U_0402_6.3V6K

12

+1.8VS

2006-11-13 Follow ATI reference schematic

2006-10-03 ATI recommend

FBMA-L11-322513-201LMA40T_1210

L7

1 2

C1211U_0402_6.3V6K

12

C1301U_0402_6.3V6K

12

C1291U_0402_6.3V6K

12

+VDDHT_PKG
+VDDA12_PKG1
+VDDA12_PKG2

C42522U_1206_6.3V6M

12

C1571U_0402_6.3V6K

12

C1461U_0402_6.3V6K

12

C1271U_0402_6.3V6K

12

C1451U_0402_6.3V6K

12

C1161U_0402_6.3V6K

12

40mil

0.5A

NB_VDDA12_HT

120mil

NB_VDDA12

NB_VDDA12_HT

4

U690D

AA17
AB17
AB19
AC18
AC19
AC20
AD21
AD22
AD23
AD24
AE23
AE24
AE25

W17

Y17

J14
J15

AB3
AB4
AC3
AD2
AE1
AE2

U7

D11
E11

AC12
AD12
AE12

E7
F7
F9

G9

D22

M1

AC11

+VDDA12_PKG1

PART 4 OF 5

VDD_HT1
VDD_HT2
VDD_HT3
VDD_HT4
VDD_HT5
VDD_HT6
VDD_HT7
VDD_HT8
VDD_HT9
VDD_HT10
VDD_HT11
VDD_HT12
VDD_HT13
VDD_HT14
VDD_HT15

VDD18_1
VDD18_2

VDDA18_1(VDDA12_13)
VDDA18_2(VDDA12_14)
VDDA18_3(VDDA12_15)
VDDA18_4(VDDA12_16)
VDDA18_5(VDDA12_17)
VDDA18_6(VDDA12_18)
VDDA18_7(VDDA12_19)
VDDA18_8(VDDA12_20)W7VDDC_14

VDDR3_1
VDDR3_2

VDD_DVO1(VDDR_1)
VDD_DVO2(VDDR_2)
VDD_DVO3(VDDR_3)

VDDA12(VDDPLL_1)
VDDA12(VDDPLL_2)
VSSA12(VSSPLL_1)
VSSA12(VSSPLL_2)

VDDHT_PKG
VDDA12_PKG1
VDDA12_PKG2

216MQA6AVA11FG FCBGA 465P

1

2

follow Bowfin 2.1

C456

0.1U_0402_16V7K~N

+1.2V_HT

12

L4
FBML10160808121LMT_0603

NB_VDDA12

C1494.7U_0805_6.3V6K~N

1

2

C1481U_0402_6.3V6K

VDDA12_1
VDDA12_2
VDDA12_3
VDDA12_4
VDDA12_5
VDDA12_6
VDDA12_7
VDDA12_8

VDDA12_9
VDDA12_10
VDDA12_11
VDDA12_12

VDDC_1
VDDC_2
VDDC_3
VDDC_4
VDDC_5
VDDC_6
VDDC_7
VDDC_8

POWER

VDDC_9
VDDC_10
VDDC_11
VDDC_12
VDDC_13

VDDC_15
VDDC_16
VDDC_17
VDDC_18
VDDC_19
VDDC_20
VDDC_21
VDDC_22
VDDC_23
VDDC_24
VDDC_25
VDDC_26
VDDC_27
VDDC_28
VDDC_29
VDDC_30
VDDC_31
VDDC_32

1

2

3

B1
C1
D1
D2
D3
E2
E3
F4
E6
G7
L9
M9

A4
A7
A9
A19
B9
B19
C9
D9
D20
G20
H11
J11
J19
L11
L13
L15
L17
M12
M14
N11
N13
N15
P12
P14
P17
R11
R13
R15
U11
U12
U14
U15

2A

NB_VDDA12_HT

1

1

1

C1530.1U_0402_16V7K~N

C1350.1U_0402_16V7K~N

C1600.1U_0402_16V7K~N

2

2

2

300mil

1

C1340.1U_0402_16V7K~N

C1580.1U_0402_16V7K~N

2

C467 22U_1206_6.3V6M

1 2

+1.2V_NBCORE

5A

1

1

1

1

C1400.1U_0402_16V7K~N

C1590.1U_0402_16V7K~N

C1360.1U_0402_16V7K~N

C1650.1U_0402_16V7K~N

2

2

2

2

A25

F11

AE18

W23

AD25

W24

AC23

AC14
AC22

AE22

AE14

AC15

AC16

D23

E9
G11
Y23
P11
R24

M15

J22

G23

J12
L12
L14
L20

L23
M11
M20
M23
M25
N12
N14

L24
P13
P20
P15
R12
R14
R20

Y25
U20

H25
Y22
D25

G24

R23

C4

T23
T25

R17
H23
M17
A23

F17

D4
M13
H12

B7

C1471U_0402_6.3V6K

12

C1281U_0402_6.3V6K

12

C1391U_0402_6.3V6K

12

C1151U_0402_6.3V6K

12

1

1

1

C13322U_1206_6.3V6M

C14122U_1206_6.3V6M

2

2

2

2

U690E

VSS1

PAR 5 OF 5

VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23

VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42

VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57

VSS59
VSS60
VSS61
VSS62

216MQA6AVA11FG FCBGA 465P

GROUND

VSSA2
VSSA3
VSSA4
VSSA5
VSSA6
VSSA7
VSSA8

VSSA9
VSSA10
VSSA11

VSSA13
VSSA15

VSSA16
VSSA17
VSSA18
VSSA19
VSSA20
VSSA21
VSSA22

VSSA24
VSSA25
VSSA26
VSSA27
VSSA28

VSSA30
VSSA32

VSSA33
VSSA34
VSSA35
VSSA36
VSSA93
VSSA94
VSSA95
VSSA37
VSSA38
VSSA39
VSSA40
VSSA41
VSSA42
VSSA43
VSSA44
VSSA45
VSSA46
VSSA47
VSSA48
VSSA49
VSSA50
VSSA51

V12
V11
V14
F3
V15
A1
H1
G3
J2
H3

J6
F1

L6
M2
M6
J3
P6
T1
N3

R6
U2
T3
U3
U6

Y1
W6

AC2
Y3
Y9
Y11
Y12
Y14
AA3
R9
AD1
AC5
AC6
AC7
AD3
AC9
AC10
G6
Y15
AC4
P9
AE6
AE10
M3

1

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2007/1/25 2008/01/25

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

RS690MC Power/GND
LA-3611P

1

12 40Wednesday, April 11, 2007

0.4

of

A

B

C

D

E

F

G

H

12

C22010U_0805_6.3V6M

1 2

C219 0.1U_0402_16V7K~N

1 1

2 2

EXT CLK FREQUENCY SELECT TABLE(MHZ)

3 3

FS2

0 0 0
0 0 1

0 1 0
0 1 1
1 0 0
1 0 1

1 1 1

1 2

1 2

1 2

+3VS_CLK

C49310U_0805_6.3V6M

C4920.1U_0402_16V7K~N

R319 10K_0402_5%

CPUFS1

Hi-Z
X

180.00

220.00

100.00

133.33

200.00

L15

FBML10160808121LMT_0603

+3VS_CLK_VDD48

+3VS

12

L16

FBML10160808121LMT_0603

+3VS_CLK_VDDREF +3VS_CLK_VDD48

CLK_RESET

1 2

SRCCLK

HTTFS0 PCI

[2:1]

Hi-Z Hi-Z100.00 Reserved

100.00

100.00

100.00

36.56 73.12

100.00

66.66 33.33

100.00

66.66 33.33

100.00

66.66 33.33 Normal ATHLON64 operation

USB

48.00

X/6X/3

48.00

30.0060.00

48.00

48.00

48.00

48.00

48.00

+3VS

SMB_CK_CLK18,9,16,27
SMB_CK_DAT18,9,16,27

COMMENT

Reserved
Reserved
Reserved
Reserved
Reserved

L14
0_0805_5%

1

C176
10U_0805_6.3V6M

2

27P_0402_50V8J

27P_0402_50V8J

1 2

C487

14.31818MHz_20P_1BX14318BE1A

1 2

12

Y3

1 2

C481

SMB_CK_CLK1 SMB_CCK_CLK1
SMB_CK_DAT1

0.1U_0402_16V7K~N

1

1

C193

C190

2

2

22U_1206_6.3V6M

+3VS_CLK_VDDREF

XTALIN_CLK
XTALOUT_CLK

CLK_RESET

R321 33_0402_5%

R320 33_0402_5%

FS0
FS1
FS2

1 2

SMB_CCK_DAT1

1 2

1 2

R85 475_0603_1%

0.1U_0402_16V7K~N

1

C192

2

0.1U_0402_16V7K~N

CLKIREF

+3V_CLK (40 mils)

+3VS_CLK

1

1

C186

C188

2

2

0.1U_0402_16V7K~N

U25

54

VDDCPU

14

VDDSRC

23

VDDSRC

28

VDDSRC

44

VDDSRC

5

VDD48

39

VDDATIG

2

VDDREF

60

VDDHTT

53

GNDCPU

15

GNDSRC

22

GNDSRC

29

GNDSRC

45

GNDSRC

8

GND48

38

GNDATIG

1

GNDREF

58

GNDHTT

3

X1

4

X2

11

RESET_IN#

61

NC

9

SMBCLK

10

SMBDAT

48

IREF

ICS951462AGLFT_TSSOP64

12

12

R77

R299

2.2K_0402_5%

2.2K_0402_5%

12

12

R76

R298

@

@

2.2K_0402_5%

2.2K_0402_5%

0.1U_0402_16V7K~N

C189

+3VS_CLK +3VS_CLK

R295

R75

@

1

C191

2

0.1U_0402_16V7K~N

VDDA
GNDA

CPUCLK8T0
CPUCLK8C0

CPUCLK8T1

CPUCLK8C1

SRCCLKT6

SRCCLKC6
ATIGCLKT0
ATIGCLKC0
ATIGCLKT1
ATIGCLKC1
ATIGCLKT2
ATIGCLKC2
ATIGCLKT3
ATIGCLKC3

SRCCLKT5

SRCCLKC5

SRCCLKT4

SRCCLKC4

SRCCLKT3

SRCCLKC3

SRCCLKT2

SRCCLKC2

SRCCLKT0

SRCCLKC0

SRCCLKT1

SRCCLKC1

SRCCLKT7

SRCCLKC7

CLKREQA#

CLKREQB#

CLKREQC#

48MHz_1
48MHz_0

FS1/REF1
FS0/REF0
FS2/REF2

HTTCLK0

12

2.2K_0402_5%

12

2.2K_0402_5%

0.1U_0402_16V7K~N

1

1

C187

2

2

50
49

CPUCLK0H

56

CPUCLK0L

55
52
51

CLK_WCARD

16

CLK_WCARD#

17

CLK_GFX_CLKP

41

CLK_GFX_CLKN

40
37
36
35
34
30
31
18
19
20
21
24
25

CLK_CARD

26

CLK_CARD#

27

CLK_LAN

47

CLK_LAN#

46

SBLINKCLK_R

43

SBLINKCLK#_R

42

SBSRCCLK_R

12

SBSRCCLK#_R

13

CLKREQA#

57

CLKREQB#

32

CLKREQC#

33
7

CLK_USB

6

FS1

63

FS0

64

FS2

62

CLK_HTREFCLK

59

CLKREQA#
CLKREQB#
CLKREQC#

R292 47.5_0402_1%

1 2

R291 47.5_0402_1%

1 2

R322 33_0402_5%

1 2

R296 33_0402_5%
R297 33_0402_5%

R294 33_0402_5%

1 2

12

12

R293

12

R73

@

R311

10K_0402_5%

R312

@

2.2K_0402_5%

10K_0402_5%

12

2.2K_0402_5%

R283

R284

@

1 2

+3VS_CLK_VDDA

1

2

C178

0.1U_0402_16V7K~N

R316 33_0402_5%

1 2

R315 33_0402_5%

1 2

R286 33_0402_5%

1 2

R285 33_0402_5%

1 2

R314 33_0402_5%

1 2

R313 33_0402_5%

1 2

R290 33_0402_5%

1 2

R289 33_0402_5%

1 2

R288 33_0402_5%

1 2

R287 33_0402_5%

1 2

R318 33_0402_5%

1 2

R317 33_0402_5%

1 2

12

12

10K_0402_5%

12

2.2K_0402_5%

L13

1 2

FBML10160808121LMT_0603

1

C177
22U_1206_6.3V6M

2

CLK_PCIE_WCARD
CLK_PCIE_WCARD#

NB_GFX_CLKP
NB_GFX_CLKN

CLK_PCIE_CARD
CLK_PCIE_CARD#
CLK_PCIE_LAN
CLK_PCIE_LAN#

SBLINKCLK

SBLINKCLK#
SBSRCCLK
SBSRCCLK#

USBCLK_EXT

R74

51.1_0402_1%

HTREFCLK 11

12

+3VS+3VS

12

R269
261_0402_1%

CLKREQA# 25
CLKREQB# 27
CLKREQC#

USBCLK_EXT 16

NB_REFCLK 11

SB_OSC_INT 16

USBCLK_EXT
NB_REFCLK
SB_OSC_INT

CLK_PCIE_WCARD
CLK_PCIE_WCARD#

CLK_PCIE_CARD
CLK_PCIE_CARD#

CLK_PCIE_LAN
CLK_PCIE_LAN#

SBSRCCLK
SBSRCCLK#

SBLINKCLK
SBLINKCLK#

NB_GFX_CLKP
NB_GFX_CLKN

CPUCLK0_H 6

CPUCLK0_L 6

CLK_PCIE_WCARD 25
CLK_PCIE_WCARD# 25
NB_GFX_CLKP 11
NB_GFX_CLKN 11

CLK_PCIE_CARD 27
CLK_PCIE_CARD# 27
CLK_PCIE_LAN 22
CLK_PCIE_LAN# 22
SBLINKCLK 11
SBLINKCLK# 11
SBSRCCLK 15
SBSRCCLK# 15

C498 10P_0402_25V8K@

1 2

C469 10P_0402_25V8K@

1 2

C470 10P_0402_25V8K@

1 2

R328 49.9_0402_1%

1 2

R327 49.9_0402_1%

1 2

R326 49.9_0402_1%

1 2

R325 49.9_0402_1%

1 2

R268 49.9_0402_1%

1 2

R267 49.9_0402_1%

1 2

R330 49.9_0402_1%

1 2

R329 49.9_0402_1%

1 2

R266 49.9_0402_1%

1 2

R265 49.9_0402_1%

1 2

R264 49.9_0402_1%

1 2

R263 49.9_0402_1%

1 2

USBCLK_EXT

@

@

12

R117
33_0402_5%

2

C255
22P_0402_50V8J

1

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

C

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

D

2007/1/25 2008/01/25

E

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

F

Date: Sheet

G

Clock Generator
LA-3611P

0.4

of

13 40Wednesday, April 11, 2007

H

A

B

C

D

+5VS

F2

1.1A_6VDC_FUSE

W=40mils

21

2 1

RB411DT146 SOT23

E

+CRT_VCC

D1

C7

W=40mils

1

2

C347

8P_0402_50V8K

10P_0402_50V8J

R5

4.7K_0402_5%

S

2

G

1 3

D

S

Q4

LVDSLC+
LVDSLC-

LVDSL0+
LVDSL0-

LVDSL1+
LVDSL1-

LVDSL2+
LVDSL2-

DISPOFF#
DAC_BRIG

INVT_PWM

MSEN#26

1

2

CRT_GND

C346

R198

1 2

INVPWR_B+
INVPWR_B+

HSYNC_L

VSYNC_L

1

2

+3VS+CRT_VCC +3VS+CRT_VCC +3VS

4.7K_0402_5%

1 2

LVDSLC+ 11
LVDSLC- 11

LVDSL0+ 11
LVDSL0- 11

LVDSL1+ 11
LVDSL1- 11

LVDSL2+ 11
LVDSL2- 11

1

C348

2

10P_0402_50V8J

VGA_DDC_DATA 11

VGA_DDC_CLK 11

DAC_BRIG 26
INVT_PWM 26

CRT_GND

0.1U_0402_16V7K~N

VGA_DDC_DATA_C

C1

100P_0402_25V8K

1

VGA_DDC_CLK_C

C2

C3

1

2

C6
68P_0402_50V8K

2

100P_0402_25V8K

68P_0402_50V8K

CRT_GND

JCRT1

6

11

1
7

12

2
8

13

3
9

14

4
10
15

5

SUYIN_070549FR015S208CR

CONN@

R3
0_0805_5%

12

R190
0_0805_5%

12

17
16

1 1

VGA_CRT_R11

VGA_CRT_G11

+3VS

D11
RB751V_SOD323

21

D12
RB751V_SOD323@

21

VGA_CRT_HSYNC11

VGA_CRT_VSYNC11

BKOFF#26

ENABLT11,26

2 2

BKOFF#

VGA_CRT_B11

12

R201
1K_0402_5%

DISPOFF#

1 2

R196 39_0402_5%

VGA_CRT_VSYNC CRT_VSYNC D_CRT_VSYNC

1 2

R199 39_0402_5%

VGA_CRT_R

VGA_CRT_G

VGA_CRT_B

12

R193

150_0402_1%

1 2

C4 0.1U_0402_16V7K~N

CRT_HSYNC D_CRT_HSYNCVGA_CRT_HSYNC

+CRT_VCC

1 2

C5 0.1U_0402_16V7K~N

12

12

R195

R197

150_0402_1%

150_0402_1%

+CRT_VCC

1

5

P

OE#

A2Y

G

U13

74AHCT1G125GW_SOT353-5

3

1

5

P

OE#

A2Y

G

U14
74AHCT1G125GW_SOT353-5

3

1

1

C352

C353

4

4

2

2

8P_0402_50V8K

8P_0402_50V8K

R200 10K_0402_5%

LCD POWER CIRCUIT

+LCDVDD

12

13

D

3 3

SSM3K7002FU_SC70-3

ENVDD11

4 4

Q5

ENVDD

10K_0402_5%

S

R14

R206
100_0402_5%

2

G

2

G

12

+5VALW

R207
47K_0402_1%

1 2

13

D

S

Q7
BSS138_NL_SOT23

12

R208 1K_0402_1%

0.047U_0402_16V7K

C373

VGA_DDC_DATA_C

+3VS

W=60mils

S

AP2301GN 1P SOT23

G

Q6

2

1

2

1N4148_SOT23@

B+

F3

2.5A_32V

D

1 3

1

C363

4.7U_0805_6.3V6K~N

2

12

D13

21

0.1U_0603_50V4Z

W=60mils

+LCDVDD

+LCDVDD

1

C369

0.1U_0402_16V7K~N

2

INVPWR_B+

+3VS

1

C370

0.1U_0402_16V7K~N@

2

INVT_PWM EDID_DAT_LCD

1

C360

1U_0603_10V6K@

2

0.1U_0603_50V4Z

2

2

C359

C361

1

1

VGA_DDC_CLK_C

EDID_CLK_LCD11

EDID_DAT_LCD11

FCM2012C-800_0805

FCM2012C-800_0805

FCM2012C-800_0805

1

C351

2

8P_0402_50V8K

+LCDVDD

+3VS

LVDSUC+11

LVDSUC-11
LVDSU0+11

LVDSU0-11

LVDSU1+11

LVDSU1-11

LVDSU2+11

LVDSU2-11

L28

1 2

L29

1 2

L30

1 2

12

R1

EDID_CLK_LCD

LVDSUC+
LVDSUC-

LVDSU0+
LVDSU0-

LVDSU1+
LVDSU1-

LVDSU2+
LVDSU2-

CRT_R_L

CRT_G_L

CRT_B_L

1

C344

2

8P_0402_50V8K

R191 0_0603_5%

R192 0_0603_5%

R2

1 2

1 2

6.8K_0402_5%

6.8K_0402_5%

BSS138_NL_SOT23

JLCD1

1

1

3

3

5

5

7

7

9

9

11

11

13

13

15

15

17

17

19

19

21

21

23

23

25

25

27

27

29

29

31

31

33

33

35

35

37

37

39

39

CONN@

JST_BM40B-SRDS-G-TFCLFSN~N

1

C345

2

8P_0402_50V8K

1 2

1 2

R6

1 2

2.2K_0402_5%

2

G

1 3

D

Q3

BSS138_NL_SOT23

41

2

2

4

4

GND

6

6

8

8

10

10

12

12

14

14

16

16

18

18

20

20

22

22

24

24

26

26

28

28

30

30

32

32

34

34

36

36

38

38

40

40

GND

42

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2007/1/25 2008/01/25

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

D

Date: Sheet

CRT Conn.& LCD Conn.
LA-3611P

E

14 40Wednesday, April 11, 2007

0.4

of

5

4

3

2

1

AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31

CBE3#

IRDY#

STOP#
PERR#
SERR#
REQ0#
REQ1#
REQ2#

GNT0#
GNT1#
GNT2#

LOCK#

LAD0
LAD1
LAD2
LAD3

VBAT

U2
T2
U1
V2
W3
U3
V1
T1

AJ9

W7
Y1
W8
W5
AA5
Y3
AA6
AC5
AA7
AC3
AC7
AJ7
AD4
AB11
AE6
AC9
AA3
AJ4
AB1
AH4
AB2
AJ3
AB3
AH3
AC1
AH2
AC2
AH1
AD2
AG2
AD1
AG1
AB9
AF9
AJ5
AG3
AA2
AH6
AG5
AA1
AF7
Y2
AG8
AC11
AJ8
AE2
AG9
AH8
AH5
AD11
AF2
AH7
AB12
AG4
AG7
AF6

AD3
AF1
AF4
AF3

AG24
AG25
AH24
AH25
AF24
AJ24
AH26
W22
AF23

D3
F5

E1
D1

PCI_AD[0..31]

PCICLK0_R
PCICLK1_R
PCICLK2_R
PCICLK3_R
PCICLK4_R
PCICLK5_R
PCICLK6_R

PCI_AD0
PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD6
PCI_AD7
PCI_AD8
PCI_AD9
PCI_AD10
PCI_AD11
PCI_AD12
PCI_AD13
PCI_AD14
PCI_AD15
PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20
PCI_AD21
PCI_AD22
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30
PCI_AD31
PCI_CBE#0
PCI_CBE#1
PCI_CBE#2
PCI_CBE#3
PCI_FRAME#
PCI_DEVSEL#
PCI_IRDY#
PCI_TRDY#
PCI_PAR
PCI_STOP#
PCI_PERR#
PCI_SERR#
PCI_REQ#0

PCI_GNT#0

PM_CLKRUN#
LOCK#

PCI_PIRQE#
PCI_PIRQF#
PCI_PIRQG#
PCI_PIRQH#

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
LPC_FRAME#
LDRQ0#
LDRQ1#
BMREQ#
SIRQ

RTC_CLK
RTC_IRQ#

8.2K_0402_5%

R125

A_RST#

SBSRCCLK13

SB_RX0P10
SB_RX0N10
SB_RX1P10

D D

0.1A

C C

0.5A

B B

A A

SB_RX1N10
SB_RX2P10
SB_RX2N10
SB_RX3P10
SB_RX3N10

SB_TX0P10

SB_TX0N10

SB_TX1P10

SB_TX1N10

SB_TX2P10

SB_TX2N10

SB_TX3P10

SB_TX3N10

+1.2V_HT

+1.2V_HT

FBM-L11-321611-260-LMT_1206

1 2

15P_0402_50V8J

15P_0402_50V8J

+1.8VS

SB_RX0P
SB_RX0N
SB_RX1P
SB_RX1N
SB_RX2P
SB_RX2N
SB_RX3P
SB_RX3N

L17

1 2

FBML10160808121LMT_0603

L18

C560

1 2

C561

1 2

R425
20M_0603_5%

R102

12

1K_0402_5%

+PCIE_VDDR

1

C22722U_1206_6.3V6M

C2331U_0603_10V6K

2

12

12

R426

20M_0603_5%

CPU_PWRGD6

LDT_STOP#6,11
CPU_SIC_SB6
CPU_SID_SB6

ALLOW_LDTSTOP11

LDT_RST#6

2

1

SBSRCCLK#13

C500 0.1U_0402_16V7K
C499 0.1U_0402_16V7K
C502 0.1U_0402_16V7K
C501 0.1U_0402_16V7K
C504 0.1U_0402_16V7K
C503 0.1U_0402_16V7K
C505 0.1U_0402_16V7K
C506 0.1U_0402_16V7K

+PCIE_VDDR

+PCIE_PVDD

2

1

C2251U_0603_10V6K

C22210U_0805_6.3V6M

1

2

2

2

2

C2321U_0603_10V6K

1

Y5

4
1

32.768K_1TJS125BJ4A421P

C2260.1U_0402_16V7K~N

C5070.1U_0402_16V7K~N

C2231U_0603_10V6K

1

1

3

OUT

NC

2

IN

NC

1 2

R101 0_0402_5%

R103 0_0402_5%

ALLOW_LDTSTOP

LDT_RST#

R332
R331

R333 0_0402_5%

2

1

CPU_PWRGD_SB600

1 2

SBSRCCLK
SBSRCCLK#

SB_RX0P_C
SB_RX0N_C
SB_RX1P_C
SB_RX1N_C
SB_RX2P_C
SB_RX2N_C
SB_RX3P_C
SB_RX3N_C

SB_TX0P
SB_TX0N
SB_TX1P
SB_TX1N
SB_TX2P
SB_TX2N
SB_TX3P
SB_TX3N

562_0402_1%

2.05K_0402_1%

12

12
12

12

SB_32KHI

SB_32KH0

U600A

AG10

A_RST#

J24

PCIE_RCLKP

J25

PCIE_RCLKN

P29

PCIE_TX0P

P28

PCIE_TX0N

M29

PCIE_TX1P

M28

PCIE_TX1N

K29

PCIE_TX2P

K28

PCIE_TX2N

H29

PCIE_TX3P

H28

PCIE_TX3N

T25

PCIE_RX0P

T26

PCIE_RX0N

T22

PCIE_RX1P

T23

PCIE_RX1N

M25

PCIE_RX2P

M26

PCIE_RX2N

M22

PCIE_RX3P

M23

PCIE_RX3N

E29

PCIE_CALRP

E28

PCIE_CALRN

E27

PCIE_CALI

U29

PCIE_PVDD

U28

PCIE_PVSS

F27

PCIE_VDDR_1

F28

PCIE_VDDR_2

F29

PCIE_VDDR_3

G26

PCIE_VDDR_4

G27

PCIE_VDDR_5

G28

PCIE_VDDR_6

G29

PCIE_VDDR_7

J27

PCIE_VDDR_8

J29

PCIE_VDDR_9

L25

PCIE_VDDR_10

L26

PCIE_VDDR_11

L29

PCIE_VDDR_12

N29

PCIE_VDDR_13

D2

X1

C1

X2

AC26

CPU_PG/LDT_PG

W26

INTR/LINT0

W24

NMI/LINT1

W25

INIT#

AA24

SMI#

AA23

SLP#/LDT_STP#

AA22

IGNNE#/SIC

AA26

A20M#/SID

Y27

FERR#

AA25

STPCLK#/ALLOW_LDTSTP

AH9

CPU_STP#/DPSLP_3V#

B24

DPSLP_OD#/GPIO37

W23

DPRSLPVR

AC25

LDT_RST#/DPRSTP#/PROCHOT#

218S6ECLA13FG FCBGA 548P

SB600 SB 23x23mm

Part 1 of 4

PCI CLKS

SPDIF_OUT/PCICLK7/GPIO41

PCI EXPRESS INTERFACE

CBE0#/ROMA10

CBE2#/ROMWE#

DEVSEL#/ROMA0

PCI INTERFACE

TRDY#/ROMOE#

XTAL

LDRQ1#/GNT5#/GPIO68

LPC

BMREQ#/REQ5#/GPIO65

CPU

RTC_IRQ#/GPIO69

RTC

BATT1

PCICLK0
PCICLK1
PCICLK2
PCICLK3
PCICLK4
PCICLK5
PCICLK6

PCIRST#

AD0/ROMA18
AD1/ROMA17
AD2/ROMA16
AD3/ROMA15
AD4/ROMA14
AD5/ROMA13
AD6/ROMA12
AD7/ROMA11

AD8/ROMA9

AD9/ROMA8
AD10/ROMA7
AD11/ROMA6
AD12/ROMA5
AD13/ROMA4
AD14/ROMA3
AD15/ROMA2
AD16/ROMD0
AD17/ROMD1
AD18/ROMD2
AD19/ROMD3
AD20/ROMD4
AD21/ROMD5
AD22/ROMD6
AD23/ROMD7

CBE1#/ROMA1

FRAME#

PAR/ROMA19

REQ3#/GPIO70
REQ4#/GPIO71

GNT3#/GPIO72
GNT4#/GPIO73

CLKRUN#

INTE#/GPIO33
INTF#/GPIO34

INTG#/GPIO35

INTH#/GPIO36

LFRAME#

LDRQ0#

SERIRQ

RTCCLK

RTC_GND

ML1220 MAXELL LITHIUM RTC BATTERY

PCI_AD[0..31] 17,20

R384 22_0402_5%

1 2

R385 22_0402_5%

1 2

R383 22_0402_5%

1 2

R381 22_0402_5%

1 2

R368

1 2

33_0402_5%

R369

8.2K_0402_5%

1 2

PCI_CBE#0 20
PCI_CBE#1 20
PCI_CBE#2 20
PCI_CBE#3 20
PCI_FRAME# 20
PCI_DEVSEL# 20
PCI_IRDY# 20
PCI_TRDY# 20
PCI_PAR 20
PCI_STOP# 20
PCI_PERR# 20
PCI_SERR# 20
PCI_REQ#0 20

PCI_GNT#0 20

PM_CLKRUN# 20,26

PCI_PIRQE# 20
PCI_PIRQF# 20

PCI_PIRQG# 20

LPC_AD0 25,26
LPC_AD1 25,26
LPC_AD2 25,26
LPC_AD3 25,26
LPC_FRAME# 25,26

BMREQ# 11

SIRQ 20,26
RTC_CLK 17

RTC_IRQ# 17

+SB_VBAT

2

C290
1U_0603_10V6K

1

CLK_PCI_MINI
CLK_PCI_CB
CLK_PCI_EC

+

1

+

1

2

PCICLK0_R
PCICLK1_R
PCICLK2_R
PCICLK3_R

C558 10P_0402_25V8K@
C306 10P_0402_25V8K@
C307 10P_0402_25V8K@

NB_RST# 11,19,22,25,26,27

2

C269
10P_0402_25V8K

1

@

RTC_BAT_PWR

1 2

R432
0_0402_5%

C548

0.1U_0402_16V7K~N

1

3

PCICLK0_R 17
PCICLK1_R 17
PCICLK2_R
PCICLK3_R

1 2
1 2
1 2

D19
BAS40-04_SOT23

2

CHGRTC

CLK_PCI_EC 26
CLK_PCI_MINI

CLK_PCI_CB 20
CLK_PCI_SIO_DB 25
PCICLK4_R 17
PCICLK5_R
PCICLK6_R 17

PCI_RST#PCIRST#

A_RST#

PCI_RST# 20,25

+3VALW

C270 0.1U_0402_16V7K~N

5

P

I2O

@

G

74LVC1G125GW_SOT3535

3

1 2

R124 0_0402_5%

JBATT1

2

-

CONN@

+SB_VBAT

W=20mils

1 2

1

U6

4

OE#

MAXELL_1220G

R372
1K_0603_5%

1 2

CLR_CMOS 27

R136
33_0402_5%

1 2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2007/1/25 2008/01/25

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

SB600-PCI_EXP/PCI/LPC/RTC
LA-3611P

1

of

15 40Wednesday, April 11, 2007

0.4

5

4

3

2

1

Reserve for EMI, close to B23 pin

SB_OSC_INT

12

R106

@

33_0402_5%

D D

C C

B B

2

@

22P_0402_50V8J

1

+3VS

R336 10K_0402_5%

1 2

R341 2.2K_0402_5%

1 2

R335 2.2K_0402_5%

1 2

R139 10K_0402_5%

1 2

PWM_CTRL

SMB_CK_CLK1
SMB_CK_DAT1

2006-10-02 Configure unused GPIO to output

SB_HD_RST#

2007-01-15
Change SDIN to AZ_SDIN3

MDC_HD_SYNC23
MDC_HD_RST#23
MDC_HD_SDOUT23
MDC_HD_BITCLK23

HD_RST#23

EC_SWI#26

EC_SCI#26

SLP_S3#26
SLP_S5#26

PWRBTN_OUT#26

SB_PWRGD6,26

PCIE_WAKE#20,22,26,27
H_THERMTRIP#6

EC_RSMRST#26

SB_OSC_INT13

SB_SPKR24
SMB_CK_CLK18,9,13,27
SMB_CK_DAT18,9,13,27

HD_BITCLK23
HD_SDOUT23
HD_SDIN323
HD_SYNC23

AC97_SDOUT17

HD_SDIN023

TP53
TP55C234
TP56
TP57

EC_GA2026
KB_RST#26

2006-10-02 Configure unused GPIO to output

PCIE_WAKE#

2006-10-02 Configure unused GPIO to output

2006-10-02 Configure unused GPIO to output

R104 10K_0402_5%
R105 10K_0402_5%

EC_SMI#26

NC_PWR_EN#27

OVCUR#328

EC_LID_OUT#26

OVCUR#128
OVCUR#028

1 2
1 2

1 2
1 2

HD_SDIN0

1 2
1 2
1 2
1 2

SB_SUS_STAT

1 2
1 2

R42233_0402_5%
R38733_0402_5%

R13833_0402_5%
R15833_0402_5%

SB_HD_SYNC

R14633_0402_5%

SB_HD_RST#

R15933_0402_5%

SB_HD_SDOUT

R42333_0402_5%

SB_HD_BITCLK

R38633_0402_5%

EC_SWI#
EC_SCI#
SLP_S3#
SLP_S5#
PWRBTN_OUT#
SB_PWRGD

SB_TEST2
SB_TEST1

SB_TEST0
EC_GA20
KB_RST#

H_THERMTRIP#

EC_RSMRST#
SB_OSC_INT

PWM_CTRL

SB_SPKR
SMB_CK_CLK1
SMB_CK_DAT1

EC_SMI#

NC_PWR_EN#

OVCUR#3

EC_LID_OUT#

OVCUR#1
OVCUR#0

SB_HD_BITCLK

SB_HD_SDOUT

HD_SDIN3

SB_HD_SYNC

SB_HD_RST#

U600D

A3

PCI_PME#/GEVENT4#

B2

RI#/EXTEVNT0#

F7

SLP_S3#

A5

SLP_S5#

E3

PWR_BTN#

B5

PWR_GOOD

B3

SUS_STAT#

F9

TEST2

E9

TEST1

G9

TEST0

AF26

GA20IN

AG26

KBRST#

D7

LPC_PME#/GEVENT3#

C25

LPC_SMI#/EXTEVNT1#

D9

S3_STATE/GEVENT5#

F4

SYS_RESET#/GPM7#

E7

WAKE#/GEVENT8#

C2

BLINK/GPM6#

G7

SMBALERT#/THRMTRIP#/GEVENT2#

E2

RSMRST#

B23

14M_OSC

C28

SATA_IS0#/GPIO10

A26

ROM_CS#/GPIO1

B29

GHI#/SATA_IS1#/GPIO6

A23

WD_PWRGD/GPIO7

B27

SMARTVOLT/SATA_IS2#/GPIO4

D23

SHUTDOWN#/GPIO5

B26

SPKR/GPIO2

C27

SCL0/GPOC0#

B28

SDA0/GPOC1#

C3

SCL1/GPOC2#

F3

SDA1/GPOC3#

D26

DDC1_SCL/GPIO9

C26

DDC1_SDA/GPIO8

A27

SSMUXSEL/SATA_IS3#/GPIO0

A4

LLB#/GPIO66

C6

USB_OC9#/SLP_S2/GPM9#

C5

USB_OC8#/AZ_DOCK_RST#/GPM8#

C4

USB_OC7#/GEVENT7#

B4

USB_OC6#/GEVENT6#

B6

USB_OC5#/DDR3_RST#/GPM5#

A6

USB_OC4#/GPM4#

C8

USB_OC3#/GPM3#

C7

USB_OC2#/GPM2#

B8

USB_OC1#/GPM1#

A8

USB_OC0#/GPM0#

N2

AZ_BITCLK

M2

AZ_SDOUT

K2

AZ_SDIN3/GPIO46

L3

AZ_SYNC

K3

AZ_RST#

L1

AC_BITCLK/GPIO38

L2

AC_SDOUT/GPIO39

L4

ACZ_SDIN0/GPIO42

J2

ACZ_SDIN1/GPIO43

J4

ACZ_SDIN2/GPIO44

M3

AC_SYNC/GPIO40

L5

AC_RST#/GPIO45

E23

NC1

AC21

NC2

AD7

NC3

AE7

NC4

AA4

NC5

T4

NC6

D4

NC7

AB19

NC8

218S6ECLA13FG FCBGA 548P

SB600 SB 23x23mm

ACPI / WAKE UP EVENTS

OSC / RST

GPIO

USB OC

AC97 AZALIA

Part 4 of 4

USBCLK
USB_RCOMP
USB_ATEST1

USB_ATEST0

USB_HSDP9+

USB_HSDM9-

USB_HSDP8+

USB_HSDM8-

USB_HSDP7+

USB_HSDM7-

USB_HSDP6+

USB_HSDM6-

USB_HSDP5+

USB_HSDM5-

USB_HSDP4+

USB INTERFACE

USB_HSDM4-

USB_HSDP3+

USB_HSDM3-

USB_HSDP2+

USB_HSDM2-

USB_HSDP1+

USB_HSDM1-

USB_HSDP0+

USB_HSDM0-

AVDDTX_0
AVDDTX_1
AVDDTX_2
AVDDTX_3
AVDDTX_4
AVDDRX_0
AVDDRX_1
AVDDRX_2
AVDDRX_3
AVDDRX_4

AVDDC

AVSSC

AVSS_USB_1
AVSS_USB_2
AVSS_USB_3
AVSS_USB_4
AVSS_USB_5
AVSS_USB_6
AVSS_USB_7
AVSS_USB_8
AVSS_USB_9

AVSS_USB_10
AVSS_USB_11
AVSS_USB_12

USB PWR

AVSS_USB_13
AVSS_USB_14
AVSS_USB_15
AVSS_USB_16
AVSS_USB_17
AVSS_USB_18
AVSS_USB_19
AVSS_USB_20
AVSS_USB_21
AVSS_USB_22
AVSS_USB_23
AVSS_USB_24
AVSS_USB_25
AVSS_USB_26
AVSS_USB_27
AVSS_USB_28
AVSS_USB_29
AVSS_USB_30
AVSS_USB_31
AVSS_USB_32
AVSS_USB_33

USBCLK_EXT

A17
A14
A11

A10
H12

G12
E12

D12
E14

D14
G14

H14
D16

E16
D18

E18
G16

H16
G18

H18
D19

E19
G19

H19

+AVDDTX

B9
B11
B13
B16
B18
A9
B10
B12
B14
B17

+AVDDC

A12
A13
A16

C9
C10
C11
C12
C13
C14
C16
C17
C18
C19
C20
D11
D21
E11
E21
F11
F12
F14
F16
F18
F19
F21
G11
G21
H11
H21
J11
J12
J14
J16
J18
J19

USBCLK_EXT 13

1 2

USB20P8+ 25
USB20P8- 25

USB20P7+ 25
USB20P7- 25

USB20P6+ 27
USB20P6- 27

USB20P4+ 27
USB20P4- 27

USB20P3+ 28
USB20P3- 28

USB20P2+ 28
USB20P2- 28

USB20P1+ 28
USB20P1- 28

USB20P0+ 28
USB20P0- 28

+AVDDC

R34911.8K_0603_1%

1

1

1

C2530.1U_0402_16V7K~N

C2620.1U_0402_16V7K~N

2

C534 2.2U_0603_10V6K
C533 0.1U_0402_16V7K~N

1

C2630.1U_0402_16V7K~N

C2731U_0603_10V6K

2

2

2

KC FBM-L11-201209-221LMAT_0805

L44

1 2

1 2
1 2

+3VS

L27

1

1

C2741U_0603_10V6K

C2561U_0603_10V6K

2

2

1 2

1

KC FBM-L11-201209-221LMAT_0805

C25422U_1206_6.3V6M

2

+3VS

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2007/1/25 2008/01/25

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

SB600 USB/ACPI/AC97/GPIO
LA-3611P

1

of

16 40Wednesday, April 11, 2007

0.4

5

4

3

2

1

SATA_DTX_IRX_P0
SATA_DTX_IRX_N0

SATA_ITX_DRX_N0
SATA_ITX_DRX_P0

D D

R116 1K_0402_1%

12

L23

12

C520

12

L25

+1.2V_AVDD_SATA

1

C240

2

22U_1206_6.3V6M

Y4

1 2

1

C258

2

+3VS

SATA_LED#29

0.6A

+1.2V_HT

C C

2006-10-03 Change Bead 3A (ATI recommend)

25MHZ_12P_X8A025000FC1H-H

B B

+1.2V_HT

1 2

FBMA-L11-201209-221LMA30T

C525

12P_0402_50V8J~N

10P_0402_50V8J

0.1A

1 2

CHB1608U301_0603

1U_0402_6.3V6K

R126
10K_0402_5%

1

2

1U_0402_6.3V6K

12

R347
10M_0402_5%

12

C238

1U_0402_6.3V6K

SATA_X1

SATA_X2

+PLLVDD_ATA

1

C249

1U_0402_6.3V6K

2

1

C229

2

SATA_CAL
SATA_X1
SATA_X2

SATA_LED#
+PLLVDD_ATA

+XTLVDD_ATA

1

1

C248

C239

2

2

0.1U_0402_16V7K~N

0.1U_0402_16V7K~N

U600B

AH21

SATA_TX0+

AJ21

SATA_TX0-

AH20

SATA_RX0-

AJ20

SATA_RX0+

AH18

SATA_TX1+

AJ18

SATA_TX1-

AH17

SATA_RX1-

AJ17

SATA_RX1+

AH13

SATA_TX2+

AH14

SATA_TX2-

AH16

SATA_RX2-

AJ16

SATA_RX2+

AJ11

SATA_TX3+

AH11

SATA_TX3-

AH12

SATA_RX3-

AJ13

SATA_RX3+

AF12

SATA_CAL

AD16

SATA_X1

AD18

SATA_X2

AC12

SATA_ACT#/GPIO67

AD14

PLLVDD_SATA_1

AJ10

PLLVDD_SATA_2

AC16

XTLVDD_SATA

AE14

AVDD_SATA_1

AE16

AVDD_SATA_2

AE18

AVDD_SATA_3

AE19

AVDD_SATA_4

AF19

AVDD_SATA_5

AF21

AVDD_SATA_6

AG22

AVDD_SATA_7

AG23

AVDD_SATA_8

AH22

AVDD_SATA_9

AH23

AVDD_SATA_10

AJ12

AVDD_SATA_11

AJ14

AVDD_SATA_12

AJ19

AVDD_SATA_13

AJ22

AVDD_SATA_14

AJ23

AVDD_SATA_15

AB14

AVSS_SATA_1

AB16

AVSS_SATA_2

AB18

AVSS_SATA_3

AC14

AVSS_SATA_4

AC18

AVSS_SATA_5

AC19

AVSS_SATA_6

AD12

AVSS_SATA_7

AD19

AVSS_SATA_8

AD21

AVSS_SATA_9

AE12

AVSS_SATA_10

AE21

AVSS_SATA_11

AF11

AVSS_SATA_12

AF14

AVSS_SATA_13

AF16

AVSS_SATA_14

AF18

AVSS_SATA_15

AG11

AVSS_SATA_16

AG12

AVSS_SATA_17

AG13

AVSS_SATA_18

AG14

AVSS_SATA_19

AG16

AVSS_SATA_20

AG17

AVSS_SATA_21

AG18

AVSS_SATA_22

AG19

AVSS_SATA_23

AG20

AVSS_SATA_24

AG21

AVSS_SATA_25

AH10

AVSS_SATA_26

AH19

AVSS_SATA_27

218S6ECLA13FG FCBGA 548P

SB600 SB 23x23mm

Part 2 of 4

IDE_D0/GPIO15
IDE_D1/GPIO16
IDE_D2/GPIO17
IDE_D3/GPIO18
IDE_D4/GPIO19
IDE_D5/GPIO20
IDE_D6/GPIO21
IDE_D7/GPIO22

ATA 66/100

SERIAL ATA

IDE_D8/GPIO23

IDE_D9/GPIO24
IDE_D10/GPIO25
IDE_D11/GPIO26
IDE_D12/GPIO27
IDE_D13/GPIO28
IDE_D14/GPIO29
IDE_D15/GPIO30

SPI_DI/GPIO12

SPI_DO/GPIO11
SPI_CLK/GPIO47

SPI_HOLD#/GPIO31

SPI_CS#/GPIO32

LAN_RST#/GPIO13

SPI ROMHW MONITOR

ROM_RST#/GPIO14

FANOUT0/GPIO3

FANOUT1/GPIO48
FANOUT2/GPIO49

FANIN0/GPIO50

FANIN1/GPIO51

FANIN2/GPIO52

TEMPIN0/GPIO61
TEMPIN1/GPIO62
TEMPIN2/GPIO63

TEMPIN3/TALERT#/GPIO64

SERIAL ATA POWER

IDE_IORDY

IDE_IRQ

IDE_A0
IDE_A1
IDE_A2

IDE_DACK#

IDE_DRQ

IDE_IOR#

IDE_IOW#

IDE_CS1#
IDE_CS3#

TEMP_COMM

VIN0/GPIO53
VIN1/GPIO54
VIN2/GPIO55
VIN3/GPIO56
VIN4/GPIO57
VIN5/GPIO58
VIN6/GPIO59
VIN7/GPIO60

AVDD
AVSS

IDEIORDYA

AB29

IDEIRQA

AA28

IDESAA0

AA29

IDESAA1

AB27

IDESAA2

Y28

IDEDACK#A

AB28

IDEREQA

AC27

IDEIOR#A

AC29

IDEIOW#A

AC28

IDECS#A1

W28

IDECS#A3

W27

IDEDA0

AD28

IDEDA1

AD26

IDEDA2

AE29

IDEDA3

AF27

IDEDA4

AG29

IDEDA5

AH28

IDEDA6

AJ28

IDEDA7

AJ27

IDEDA8

AH27

IDEDA9

AG27

IDEDA10

AG28

IDEDA11

AF28

IDEDA12

AF29

IDEDA13

AE28

IDEDA14

AD25

IDEDA15

AD29

J3
J6
G3
G2
G6

C23
G5

M4
T3
V4

N3
P2
W4

P5
P7
P8
T8

EC_THERM#

T7
V5

L7
M8

2006-10-02 GPIO50-64 configure to output

V6
M6
P4
M7
V7

N1
M1

IDEIORDYA 19

IDEIRQA 19
IDESAA0 19
IDESAA1 19
IDESAA2 19
IDEDACK#A 19

IDEREQA 19
IDEIOR#A 19
IDEIOW#A 19
IDECS#A1 19
IDECS#A3 19
IDEDA[0..15] 19

+3VS

R137

10K_0402_5%

1 2

0.1U_0402_16V7K~N

2.2U_0603_10V6K

1

1

C286

2

2

2007-01-17 ATI recommend

C287

EC_THERM# 26

AC97_SDOUT16

RTC_IRQ#15

RTC_CLK15
PCICLK4_R15
PCICLK6_R15
PCICLK0_R15
PCICLK1_R15

DEBUG STRAPS

+3VS

SB600 HAS 15K INTERNAL PU FOR PCI_AD[28:23]

REQUIRED STRAPS

SB600 HAS 15K INTERNAL PD FOR AC_SDATA_OUT,
15K PU FOR RTC_CLK, EXTERNAL PU/PD IS
NOT REQUIRED; FOR SB460, EXTERNAL PU/PD ARE
REQUIRED

+3VS+3VS +3VS +3VS +3VS+3VALW +3VALW

12

R424

2.2K_0402_5%

12

R140
10K_0402_5%

@

@

AC_SDOUT

PULL
HIGH

PULL
LOW

USE
DEBUG
STRAPS

IGNORE
DEBUG
STRAPS

DEFAULT

PCI_AD27 PCI_AD25PCI_AD26 PCI_AD24

12

R377
10K_0402_5%

@

12

R150
10K_0402_5%

@

12

R147
10K_0402_5%

@

RTC_CLK

INTERNAL
RTC

DEFAULT

EXTERNAL
RTC

12

R144
10K_0402_5%

@

12

R145
10K_0402_5%

PCI_CLK4 PCI_CLK6

USE INT.
PLL48

USE EXT.
48MHZ

DEFAULT

12

R379
10K_0402_5%

12

R152
10K_0402_5%

@

12

@

12

PCICLK6_RPCICLK4_RAC97_SDOUT RTC_CLK PCICLK0_R

CPU IF=K8

DEFAULT

CPU IF=P4

PCI_AD[0..31]

R378
10K_0402_5%

@

R151
10K_0402_5%

@

12

R382
10K_0402_5%

12

12

PCICLK1_R

PCI_CLK1 PCI_CLK0

ROM TYPE:
H, H = PCI ROM
H, L = LPC I ROM
L, H = LPC II ROM
L, L = FWH ROM

NOTE: FOR SB460, PCICLK[8:7] ARE
CONNECTED TO SUBSTRATE
BALLS PCICLK[1:0]

+3VS+3VS+3VS+3VS

12

R380
10K_0402_5%

@

2.2K IF USED FOR SB600.
10K IF USED FOR SB460.

12

R153
10K_0402_5%

@

R154
10K_0402_5%

@

R155
10K_0402_5%

PCI_AD[0..31] 15,20

12

R157
10K_0402_5%

12

R156
10K_0402_5%

@

DEFAULT

PCI_AD25 PCI_AD24

USE IDE
PLL

DEFAULT

BYPASS IDE
PLL

Title

Size Document Number Rev

Custom

Date: Sheet

USE DEFAULT
PCIE STRAPS

DEFAULT

USE EEPROM
PCIE STRAPS

SB600 IDE/SATA/HW Strap
LA-3611P

1

of

17 40Wednesday, April 11, 2007

0.4

PULL
HIGH

PULL
LOW

2

PCI_AD27 PCI_AD26

USE PCI
PLL

DEFAULT

BYPASS
PCI PLL

USE ACPI
BCLK

DEFAULT

BYPASS
ACPI
BCLK

L24

+3VS

A A

1 2

CHB1608U301_0603

1U_0402_6.3V6K

5

C250

1

2

+XTLVDD_ATA

SATA_DTX_IRX_N0

SATA_DTX_IRX_P0 SATA_DTX_C_IRX_P0

SATA_ITX_DRX_N0

SATA_ITX_DRX_P0 SATA_ITX_C_DRX_P0

4

SATA_DTX_C_IRX_N0

12

C519 0.01U_0402_16V7K

12

C514 0.01U_0402_16V7K

SATA_ITX_C_DRX_N0

12

C579 0.01U_0402_16V7K

12

C578 0.01U_0402_16V7K

close to connector

SATA_DTX_C_IRX_N0 19

SATA_DTX_C_IRX_P0 19

SATA_ITX_C_DRX_N0 19

SATA_ITX_C_DRX_P0 19

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2007/1/25 2008/01/25

Compal Secret Data

Deciphered Date

0.1A

C513 150U_D2_6.3VM

C261 1U_0603_10V6K

1 2

C230 1U_0603_10V6K

1 2

C284 1U_0603_10V6K

1 2

C243 1U_0603_10V6K

1 2

C285 1U_0603_10V6K

1 2

C235 1U_0603_10V6K

1 2

2006-10-03 Change to 1uF (ATI recommend)

+3VALW_SB

C547 22U_1206_6.3V6M
C298 0.1U_0402_16V7K~N

C539 0.1U_0402_16V7K~N
C540 0.1U_0402_16V7K~N
C559 0.1U_0402_16V7K~N
C271 0.1U_0402_16V7K~N

+1.2VALW_SB

12

1 2
1 2
1 2
1 2
1 2

1

2

C29910U_0805_6.3V6M

C2880.1U_0402_16V7K~N

2

1

0.1A

+5VS

+3VS

FBML10160808121LMT_0603

+3VS

2

2

C2720.1U_0402_16V7K~N

C2890.1U_0402_16V7K~N

1

1

+1.8VS

R123
1K_0402_5%

1 2

D4
RB751V_SOD323

2 1

L22

1 2

+3VS

12

+

C241 22U_1206_6.3V6M
C252 1U_0603_10V6K

C260 1U_0603_10V6K
C242 1U_0603_10V6K
C259 1U_0603_10V6K
C251 1U_0603_10V6K

0.2A

L20

1 2

FBML10160808121LMT_0603

1U_0603_10V6K

12

C5224.7U_0805_6.3V6K~N

12

C5150.1U_0402_16V7K~N

0.6A

+1.2V_HT

1A

12

+3VALW_SB

12

+1.2VS_SB_VDD

0.1A

FBM-L11-321611-260-LMT_1206

1 2
1 2
1 2
1 2
1 2

+1.2V_HT

L26

12

R109 0_0805_5%

C521 1U_0603_10V6K

1 2

C244 1U_0603_10V6K

1 2

C526 1U_0603_10V6K

1 2

C245 1U_0603_10V6K

1 2

2006-10-03 Change to 1uF (ATI recommend)

1

C231

0.1U_0402_16V7K~N

2

2

C257

1

+SB_AVDDCK

+USBPHY

+SB_CPUPWR
+V5_VREF
+SB_AVDDCK
+SB_AVDDCK_1.2V

U600C

A25

SB600 SB 23x23mm

VDDQ_1

A28

VDDQ_2

C29

VDDQ_3

D24

VDDQ_4

L9

VDDQ_5

L21

VDDQ_6

M5

VDDQ_7

P3

VDDQ_8

P9

VDDQ_9

T5

VDDQ_10

V9

VDDQ_11

W2

VDDQ_12

W6

VDDQ_13

W21

VDDQ_14

W29

VDDQ_15

AA12

VDDQ_16

AA16

VDDQ_17

AA19

VDDQ_18

AC4

VDDQ_19

AC23

VDDQ_20

AD27

VDDQ_21

AE1

VDDQ_22

AE9

VDDQ_23

AE23

VDDQ_24

AH29

VDDQ_25

AJ2

VDDQ_26

AJ6

VDDQ_27

AJ26

VDDQ_28

M13

VDD_1

M17

VDD_2

N12

VDD_3

N15

VDD_4

N18

VDD_5

R13

VDD_6

R17

VDD_7

U12

VDD_8

U15

VDD_9

U18

VDD_10

V13

VDD_11

V17

VDD_12

A2

S5_3.3V_1

A7

S5_3.3V_2

F1

S5_3.3V_3

J5

S5_3.3V_4

J7

S5_3.3V_5

K1

S5_3.3V_6

G4

S5_1.2V_1

H1

S5_1.2V_2

H2

S5_1.2V_3

H3

S5_1.2V_4

A18

USB_PHY_1.2V_1

A19

USB_PHY_1.2V_2

B19

USB_PHY_1.2V_3

B20

USB_PHY_1.2V_4

B21

USB_PHY_1.2V_5

AA27

CPU_PWR

AE11

V5_VREF

A24

AVDDCK_3.3V

A22

AVDDCK_1.2V

B22

AVSSCK

V29

PCIE_VSS_42

V28

PCIE_VSS_41

V27

PCIE_VSS_40

V26

PCIE_VSS_39

V25

PCIE_VSS_38

V24

PCIE_VSS_37

V23

PCIE_VSS_36

V22

PCIE_VSS_35

U27

PCIE_VSS_34

T29

PCIE_VSS_33

T28

PCIE_VSS_32

T27

PCIE_VSS_31

T24

PCIE_VSS_30

T21

PCIE_VSS_29

P27

PCIE_VSS_28

218S6ECLA13FG FCBGA 548P

Part 3 of 4

POWER

VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8

VSS_9
VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47
VSS_48
VSS_49
VSS_50
VSS_51
VSS_52
VSS_53
VSS_54
VSS_55
VSS_56
VSS_57

PCIE_VSS_1
PCIE_VSS_2
PCIE_VSS_3
PCIE_VSS_4
PCIE_VSS_5
PCIE_VSS_6
PCIE_VSS_7
PCIE_VSS_8

PCIE_VSS_9
PCIE_VSS_10
PCIE_VSS_11
PCIE_VSS_12
PCIE_VSS_13
PCIE_VSS_14
PCIE_VSS_15
PCIE_VSS_16
PCIE_VSS_17
PCIE_VSS_18
PCIE_VSS_19
PCIE_VSS_20
PCIE_VSS_21
PCIE_VSS_22
PCIE_VSS_23
PCIE_VSS_24
PCIE_VSS_25
PCIE_VSS_26
PCIE_VSS_27

A20
A21
A29
B1
B7
B25
C21
C22
C24
D6
E24
F2
F23
G1
J1
J8
L6
L8
M9
M12
M15
M18
N13
N17
P1
P6
P21
R12
R15
R18
T6
T9
U13
U17
V3
V8
V12
V15
V18
V21
W1
W9
Y29
AA11
AA14
AA18
AC6
AC24
AD9
AD23
AE3
AE27
AG6
AJ1
AJ25
AJ29

D27
D28
D29
F26
G23
G24
G25
H27
J23
J26
J28
K27
L22
L23
L24
L27
L28
M21
M24
M27
N27
N28
P22
P23
P24
P25
P26

C541

4.7U_0805_6.3V6K~N

0.22U_0603_10V7K @

+3VALW TO +3VALW_SB

+3VALW

6
2

1

1

2

C563

4.7U_0805_6.3V6K~N

R370
0_0805_5%

Q47

D

S

45

SI3456BDV-T1-E3_TSOP6

G

3

0_0603_5%

1 2

R389

1

2

SSM3K7002FU_SC70-3

+1.2VALW

6
2

1

C308

1

2

@

+1.2VALW TO +1.2VALW_SB

D

12

1

2

13

D

Q50

S

SBPWR_EN26

R160
0_0805_5%

Q23

G

@

S

45

SI3456BDV-T1-E3_TSOP6

3

R388

1 2

10K_0603_1%

1

C562

0.22U_0603_10V7K

2

C550
1U_0603_10V6K

R390

100K_0603_5%

1 2

2

G

10K_0402_5%

12

Q48

SSM3K7002FU_SC70-3

+3VALW_SB

B+_BIAS

SBPWR_EN#

SBPWR_EN

R430

1

C301

4.7U_0805_6.3V6K~N@

2

100K_0603_5%

1 2

13

D

S

1

C549
1U_0603_10V6K

2

12

R161

2

G

+5VALW

1 2

13

D

2

G

S

B+_BIAS

SBPWR_EN#

R431
10K_0402_5%

Q49
SSM3K7002FU_SC70-3

+1.2VALW_SB

2

C300

0.1U_0402_16V7K~N

1

FBML10160808121LMT_0603

+1.2V_HT

L19

1 2

C2374.7U_0805_6.3V6K~N

C2360.1U_0402_16V7K~N

+SB_AVDDCK_1.2V

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2007/1/25 2008/01/25

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

Date: Sheet

SB600 Power/GND
LA-3611P

of

18 40Wednesday, April 11, 2007

0.4

12
12

5

4

3

2

1

JODD1

GND

2
4
6
8

10

ODD_ACT_LED#

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54

IDEDA8
IDEDA9
IDEDA10
IDEDA11
IDEDA12
IDEDA13
IDEDA14
IDEDA15
IDEREQA
IDEIOR#A

IDEDACK#A

PDIAG#

IDESAA2
IDECS#A3

1 2

R243
100K_0402_5%

@

R257 10K_0402_5%@

1 2

80mils

IDEREQA 17
IDEIOR#A 17

IDEDACK#A 17

IDESAA2 17

IDECS#A3 17

+5VS

+5VS

IDEDA[0..15] 17

+5VS

+5VS

1

C449

2

Close to ODD Conn

10U_0805_10V4Z~N

1U_0603_10V6K

1

C450

2

1

C440

2

0.1U_0402_16V7K~N

1

C441

2

1000P_0402_50V7K~N

ODD_ACT_LED#29

C183 47P_0402_50V8J

+5VS

12

NB_RST#
IDEDA7
IDEDA6
IDEDA5
IDEDA4
IDEDA3
IDEDA2
IDEDA1
IDEDA0

IDEIOW#A
IDEIORDYA
IDEIRQA
IDESAA1
IDESAA0
IDECS#A1

SD_CSEL

12

D D

+5VS

12

R256

100K_0402_5%

ODD_ACT_LED#

C C

NB_RST#11,15,22,25,26,27

IDEIOW#A17
IDEIORDYA17
IDEIRQA17

IDESAA117
IDESAA017

IDECS#A117

R242 470_0402_5%

If CDROM is Slave
then SD_CSEL= Floating

CDROM CONN

1

1

3

3

5

5

7

7

9

9
111112
131314
151516
171718
191920
212122
232324
252526
272728
292930
313132
333334
353536
373738
393940
414142
434344
454546
474748
494950
GND51GND

53

GND

SUYIN_800059MR050S119ZL

CONN@

else SD_CSEL= Low

+5VS

SATA HDD CONN

JSATA1

S1

SATA_DTX_C_IRX_P017

B B

SATA_DTX_C_IRX_N017
SATA_ITX_C_DRX_N017

SATA_ITX_C_DRX_P017

SATA_DTX_C_IRX_P0
SATA_DTX_C_IRX_N0

SATA_ITX_C_DRX_N0
SATA_ITX_C_DRX_P0

+3VS

+5VS

GND

S2

HTX+

S3

HTX-

S4

GND

S5

HRX-

S6

HRX+

S7

GND

NC

VCC3.3
VCC3.3
VCC3.3
GND
GND
GND
VCC5
VCC5
VCC5
GND
RESERVED
GND
VCC12
VCC12
VCC12

GND
GND
GND
GND

NC

P1
P2
P3
P4
P5
P6
P7
P8

P9
P10
P11
P12
P13
P14
P15

SUYIN_127043FR022G226ZL

CONN@

27
28

23
24
25
26

150U_D2_6.3VM

C543

1

+

2

+3VS

10U_0805_10V4Z~N

1

C565

2

1

C564

2

10U_0805_10V4Z~N

C311

@

0.1U_0402_16V7K~N

Close to SATA HDD

C295

0.1U_0402_16V7K~N

1

2

0.1U_0402_16V7K~N

1

C294

2

0.1U_0402_16V7K~N

1

C570

2

1

C277

2

1000P_0402_50V7K~N

1

C569

2

1000P_0402_50V7K~N

1

2

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2007/1/25 2008/01/25

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

HDD/CDROM
LA-3611P

1

0.4

of

19 40Wednesday, April 11, 2007

5

PCI_AD[0..31]15,17

D D

PCI_CBE#315
PCI_CBE#215
PCI_CBE#115
PCI_CBE#015

PCI_PAR15

PCI_FRAME#15
PCI_TRDY#15

C C

+3V

12

R362
100K_0402_5%

CBS_GRST#

1

C531
1U_0603_10V6K

2

R363

C532

CLK_PCI_CB

@

10_0402_5%

12

@

4.7P_0402_50V8C

CLK_PCI_CB_TERM

2

1

B B

A A

PCI_AD21

CLK_PCI_CB15

PCI_RST#15,25

PM_CLKRUN#15,26

+3V

+3V

5

PCI_IRDY#15
PCI_STOP#15
PCI_DEVSEL#15

1 2

PCI_PERR#15
PCI_SERR#15

PCI_REQ#015
PCI_GNT#015

SHIELD GND

R367 0_0402_5%@

1 2

R366 10K_0402_5%

1 2

PCI_PIRQE#15
PCI_PIRQF#15
PCI_PIRQG#15 CBS_CVS1 21

R356 10K_0402_5%
R364 10K_0402_5%

PCIE_WAKE#16,22,26,27

PCM_SPK#24

1 2
1 2

R357 0_0402_5%@

R360 10K_0402_5%
R361 100K_0402_5%

12

1 2

apply same length for set of TPA+,TPA-and TPB+,TPB-

Placement Near Card Bus Controller

PCI_AD31
PCI_AD30
PCI_AD29
PCI_AD28
PCI_AD27
PCI_AD26
PCI_AD25
PCI_AD24
PCI_AD23
PCI_AD22
PCI_AD21
PCI_AD20
PCI_AD19
PCI_AD18
PCI_AD17
PCI_AD16
PCI_AD15
PCI_AD14
PCI_AD13
PCI_AD12
PCI_AD11
PCI_AD10
PCI_AD9
PCI_AD8
PCI_AD7
PCI_AD6
PCI_AD5

T11

PCI_AD4

V11

PCI_AD3

W11

PCI_AD2

T12

PCI_AD1

V12

PCI_AD0

W12

PCI_PAR

PCI_FRAME#
PCI_TRDY#
PCI_IRDY#
PCI_STOP#
PCI_DEVSEL# CBS_CDEVSEL#
CBS_IDSEL

R365100_0402_5%

PCI_PERR#
PCI_SERR#

PCI_RST#
CBS_GRST#

SIRQ15,26

UDIO3
UDIO4

1 2

PCM_SPK#

IEEE1394_TPBIAS0

IEEE1394_TPAP0
IEEE1394_TPAN0
IEEE1394_TPBP0
IEEE1394_TPBN0

R393

R429

C571

56.2_0603_1%

12

56.2_0603_1%

12

Z3008

270P_0402_50V7K

2

1

U32A

M2

AD31

M1

AD30

N5

AD29

N4

AD28

N2

AD27

N1

AD26

P5

AD25

P4

AD24

R4

AD23

R2

AD22

R1

AD21

T2

AD20

T1

AD19

U2

AD18

U1

AD17

V1

AD16

T7

AD15

V7

AD14

W7

AD13

R8

AD12

T8

AD11

V8

AD10

W8

AD9

R9

AD8

V9

AD7

W9

AD6
AD5
AD4
AD3
AD2
AD1
AD0

P2

C/BE3#

W2

C/BE2#

W6

C/BE1#

T9

C/BE0#

V6

PAR

V3

FRAME#

W4

TRDY#

V4

IRDY#

V5

STOP#

T5

DEVSEL#

P1

IDSEL

W5

PERR#

T6

SERR#

M4

REQ#

M5

GNT#

K1

PCICLK

L4

PCIRST#

G2

GBRST#

L5

CLKRUN#

J2

INTA#

K4

INTB#

K2

INTC#

J4

UDIO0/SERIRQ#

H1

UDIO1

H2

UDIO2

H4

UDIO3

H5

UDIO4

G1

UDIO5

G4

RI_OUT#/PME#

F1

SPKROUT

F2

HWSPND#

F4

TEST

R5C841_CSP208~D

12

R392

12

R428

R427

1 2

4

R5C841

CSTSCHG/BVD1(STSCHG#/RI#)

0.01U_0402_16V7K

56.2_0603_1%
C567

1

2

56.2_0603_1%

5.1K_0603_1%

4

CAD31/CDATA10

CAD30/CDATA9
CAD29/CDATA1
CAD28/CDATA8
CAD27/CDATA0

CAD26/CADR0
CAD25/CADR1
CAD24/CADR2
CAD23/CADR3
CAD22/CADR4
CAD21/CADR5
CAD20/CADR6

CAD19/CADR25

CAD18/CADR7
CAD17/CADR24
CAD16/CADR17

CAD15/IOWR#

CAD14/CADR9

CAD13/IORD#

CAD12/CADR11

CAD10/CE2#

CAD9/CADR10
CAD8/CDATA15

CAD7/CDATA7
CAD6/CDATA13

CAD5/CDATA6
CAD4/CDATA12

CAD3/CDATA5
CAD2/CDATA11

CAD1/CDATA4

CAD0/CDATA3

CC/BE3#/REG#

CC/BE2#/CADR12

CC/BE1#/CADR8

CC/BE0#/CE1#

CPAR/CADR13

CFRAME#/CADR23

CTRDY#/CADR22

CIRDY#/CADR15

CSTOP#/CADR20

CDEVSEL#/CADR21

RESERVED/CADR19

CPERR#/CADR14

CSERR#/WAIT#

CREQ#/INPACK#

CCLKRUN#/WP(IOIS16#)

CCLK/CADR16

CINT#/RDY(IREQ#)

CRST#/RESET

CAUDIO/BVD2(SPKR#/LED)

CCD1#/CD1#
CCD2#/CD2#

RESERVED/CDATA14

RESERVED/CDATA2
RESERVED/CADR18

0.33U_0603_10V7K

C566

1

2

CAD11/OE#

CGNT#/WE#

CVS1/VS1#
CVS2/VS2#

CBS_CAD31

B19

CBS_CAD30

C18

CBS_CAD29

D19

CBS_CAD28

D18

CBS_CAD27

E19

CBS_CAD26

E16

CBS_CAD25

F18

CBS_CAD24

F15

CBS_CAD23

G18

CBS_CAD22

G15

CBS_CAD21

H18

CBS_CAD20

H15

CBS_CAD19

J18

CBS_CAD18

J16

CBS_CAD17

J15

CBS_CAD16

P16

CBS_CAD15

P19

CBS_CAD14

R19

CBS_CAD13

P18

CBS_CAD12

R18

CBS_CAD11

T19

CBS_CAD10

T18

CBS_CAD9

U19

CBS_CAD8

U18

CBS_CAD7

W17

CBS_CAD6

V17

CBS_CAD5

W16

CBS_CAD4

V16

CBS_CAD3

W15

CBS_CAD2

V15

CBS_CAD1

T15

CBS_CAD0

R14

CBS_CC/BE3#

F16

CBS_CC/BE2#

K18

CBS_CC/BE1#

P15

CBS_CC/BE0#

V19

CBS_CPAR

N15

CBS_CFRAME#

K16
L16

CBS_CIRDY#

K15

CBS_CSTOP#

M16
L18

CBS_CBLOCK#

N19

CBS_CPERR#

N18

CBS_CSERR#

G16

CBS_CREQ#

G19

CBS_CGNT#

M15

CBS_CSTSCHNG

E18

CBS_CCLKRUN#

A18

CBS_CCLK_INTERNAL

L19

CBS_CINT#

M18

CBS_CRST#

H19

F19

T14
D15
R16
H16

W18
C19
N16

4
3
2
1

SUYIN_020204FR004S506ZL
J139A1

CONN@

4
3
2
1

GND15GND26GND37GND4

CBS_CAUDIO

CBS_CCD1C#
CBS_CCD2C#
CBS_CVS1
CBS_CVS2

CBS_RSVD/D14
CBS_RSVD/D2
CBS_RSVD/A18

C585 0.01U_0402_16V7K

8

3

CBS_CAD[0..31] 21

C575

R5C841XI

12

15P_0402_50V8J

C576

12P_0402_50V8J~N

CBS_CC/BE3# 21
CBS_CC/BE2# 21
CBS_CC/BE1# 21
CBS_CC/BE0# 21

CBS_CPAR 21

CBS_CFRAME# 21
CBS_CTRDY# 21
CBS_CIRDY# 21
CBS_CSTOP# 21
CBS_CDEVSEL# 21
CBS_CBLOCK# 21
CBS_CPERR# 21

CBS_CSERR# 21
CBS_CREQ# 21

CBS_CGNT# 21

CBS_CSTSCHNG 21

CBS_CCLKRUN# 21

R435 22_0402_5%

1 2

12

CBS_CINT# 21

CBS_CRST# 21

CBS_CAUDIO 21

CBS_CVS2 21

CBS_RSVD/D14 21
CBS_RSVD/D2 21
CBS_RSVD/A18 21

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

X1

24.576MHz_16P_3XG-24576-43E1

1 2

R5C841XO

12

0.01U_0402_16V7K

C589

2

1

1 2

SDLED#_MSLED#_XDLED#

0_0402_5%

R434

1 2

270P_0402_50V7K

C582

2

1

2007/1/25 2008/01/25

C574 0.01U_0402_16V7K

1 2

10K_0603_1%

R436

VPPEN021
VPPEN121

VCC5EN#21
VCC3EN#21

+3V

1 2

R395
100K_0402_5%

CBS_CCLK 21

CBS_CCD2# 21
CBS_CCD1# 21

R433
0_0402_5%

1 2

270P_0402_50V7K

C577

2

1

Compal Secret Data

Deciphered Date

1 2

+3V_PHY

R5C841XI
R5C841XO

IEEE1394_TPAP0
IEEE1394_TPAN0

IEEE1394_TPBP0
IEEE1394_TPBN0

R391

0_0402_5%

IEEE1394_TPBIAS0

R375

1 2

0_0402_5%

2

R394

2

12

D11
A16

B16
A14

B12
A12

B13
A13

B10
A10

B11
A11

D12
D10

D13
B14

V14

W14

V13

W13

R13
T13

R7

100K_0402_5%

U32B

CPS
XI

XO
FIL0

TPAP0
TPAN0

TPBP0
TPBN0

TPAP1
TPAN1

TPBP1
TPBN1

TPBIAS0
TPBIAS1

VREF
REXT

USBDP
USBDM

VPPEN0
VPPEN1

VCC5EN#
VCC3EN#

REGEN#

R5C841_CSP208~D

R5C841

CARD_LED 29

1

MDIO00
MDIO01
MDIO02
MDIO03
MDIO04
MDIO05
MDIO06
MDIO07
MDIO08
MDIO09
MDIO10
MDIO11
MDIO12
MDIO13
MDIO14
MDIO15
MDIO16
MDIO17
MDIO18
MDIO19

B1
A2
A3
B3
B4
A5

SDLED#_MSLED#_XDLED#

B5
D5

R376

A6
B6

22_0402_5%

D6
E6
A7
B7
D7
E7
A8
B8
D8
E8

12

R359
0_0402_5%

12

SDDET#_XDDET0# 21
MSDET#_XDDET1# 21
XDCE# 21

SDWP#_XDRB# 21

SD_EN 21

XDWP 21

SDCMD_MSBS_XDWE# 21

SDCLK_MSCLK_XDRE# 21
SDDATA0_MSDATA0_XDDATA0 21
SDDATA1_MSDATA1_XDDATA1 21
SDDATA2_MSDATA2_XDDATA2 21
SDDATA3_MSDATA3_XDDATA3 21
XDDATA4 21
XDDATA5 21
XDDATA6 21
XDDATA7 21
XDCLE 21
XDALE 21

Function Seclect

UDIO3 UDIO4 VPPEN0 SD MS

0

00

00 1

01 0

101

010

10 1

11 0

11 1

*

Title

Size Document Number Rev

Date: Sheet

CardBus Controller(R5C841)

Wednesday, April 11, 2007

LA-3611P

XX

XX

EnableX

Enable EnableX

Enable X X

Enable EnableX

Enable Enable X

Enable Enable Enable

of

1

20 40

Enable

0.4

5

+3V

*as close as possible to VCC_3V pin

0.01U_0402_16V7K

10U_0805_6.3V6M

C545

1

2

C555

C568

0.01U_0402_16V7K

1

2

0.01U_0402_16V7K

1

2

C537

1

2

+3V

1

C530

2

C583

1

2

J3

1 2

SHORT PADS

J2

1 2

OPEN PADS

C587

+3VS

D D

*as close as possible to VCC_PCI pin

0.01U_0402_16V7K

10U_0805_6.3V6M

C572

1

C573

2

C546

C C

0.1U_0402_16V7K~N

C318

1

2

B B

VPPEN020
VPPEN120

VCC3EN#20
VCC5EN#20

SDDATA3_MSDATA3_XDDATA320
SDCMD_MSBS_XDWE#20

SDCLK_MSCLK_XDRE#20
SDDATA0_MSDATA0_XDDATA020

0.01U_0402_16V7K

C556

1

1

2

2

+3V

*as close as possible to VCC_RIN pin

0.1U_0402_16V7K~N

10U_0805_6.3V6M

C557

1

1

2

2

+5VALW

+5V

0.01U_0402_16V7K

0.01U_0402_16V7K

C536

1

2

*as close as possible to VCC_MD3V pin

10U_0805_6.3V6M

C535

1

2

0.01U_0402_16V7K

C584

1

2

@

SD_MS_XDDATA1

SD_MS_XDDATA2

1

2

0.01U_0402_16V7K

0.01U_0402_16V7K

C538

C317

+SD_VCC

0.01U_0402_16V7K

C586

1

2

+3V_PHY

0.01U_0402_16V7K

1

2

@

0.1U_0402_16V7K~N

1

2

R475 150_0402_1%
R477 150_0402_1%

R481 39_0402_5%
R484 150_0402_1%

R486 150_0402_1%
R488 150_0402_1%

1 2
1 2

1 2
1 2

1 2
1 2

U32C

F5

VCC_3V1

G5

VCC_3V2

J19

VCC_3V3

K19

VCC_3V4

W3

VCC_PCI3V1

R11

VCC_PCI3V2

R12

VCC_PCI3V3

A4

VCC_MD3V

R6

VCC_RIN1

E13

VCC_RIN2

L1

VCC_ROUT1

E14

VCC_ROUT2

E10

AVCC_PHY1

E11

AVCC_PHY2

A17

AVCC_PHY3

B17

AVCC_PHY4

A9

AGND1

B9

AGND2

D9

AGND3

D14

AGND4

A15

AGND5

B15

AGND6

J1

GND1

J5

GND2

K5

GND3

E9

GND4

R10

GND5

T10

GND6

V10

GND7

W10

GND8

L15

GND9

M19

GND10

R5C841_CSP208~D

U8

11

VCC3IN

13

VCC5IN

15

VCC5IN

3

EN0

4

EN1

2

VCC3_EN

1

VCC5_EN

5

FLG

16

GND

R5531V002-E2-FA_SSOP16~D

+SD_VCC

R494 22_0402_5%

SDCLK_MSCLK_XDRE#20
SDDATA3_MSDATA3_XDDATA320
MSDET#_XDDET1#20
SDDATA2_MSDATA2_XDDATA220

A A

SDDATA0_MSDATA0_XDDATA020
SDDATA1_MSDATA1_XDDATA120
SDCMD_MSBS_XDWE#20

SDDET#_XDDET0#20
SDWP#_XDRB#20

5

MSDET#_XDDET1#

SDCMD_MSBS_XDWE#

+3VS

SDDET#_XDDET0#

+3VS

SDWP#_XDRB#

1 2

R496 100_0402_5%

1 2

R498 100_0402_5%

1 2

R500 100_0402_5%

1 2

R501 100_0402_5%

1 2

R502 100_0402_5%

1 2

R503 100_0402_5%

1 2

R504 100K_0402_5%

1 2

R505 100K_0402_5%

1 2

4

R5C841

9

VCCOUT

14

VCCOUT

12

VCCOUT

8

VPPOUT

7

NC

6

NC

10

NC

JSD1

24

CD/D3

22

CMD

20

VSS

19

VDD

8

CLK

6

VSS

4

D0

3

D1

25

D2

18

VSS

17

VCC

16

SCLK

15

MS-D3

14

INS

13

MS-D2

12

MS-D0

11

MS-D1

10

BS

9

VSS

1

CD_SW

2

COMMDN

46

WP_SW

ALPS_SCDE2B0101_46P

4

1.5A

0.5A

+CBS_VPP

C327

1

2

3

JPC1

1

CBS_CAD0
CBS_CAD1
CBS_CAD3
CBS_CAD5

L2

NC1

C1

NC2

D1

NC3

E1

NC4

C2

NC5

D2

NC6

E2

NC7

E4

NC8

E12

NC9

CBS_CCLK20

22P_0402_50V8J @

L45

1 2

+3V

BLM21A601SPT_0805

+CBS_VCC+3V

1

1

0.01U_0402_16V7K

C319

C316

0.01U_0402_16V7K

0.1U_0402_16V7K~N
C326

1

2

10U_0805_6.3V6M

2

2

CBS_CCLK_E

12

R172

33_0402_5% @

2

C313

1

1

C588

C554

2

22U_1206_6.3V6M

SDDATA1_MSDATA1_XDDATA120

SDDATA2_MSDATA2_XDDATA220

CBS_CC/BE0#20

CBS_CC/BE1#20
CBS_CPAR20
CBS_CPERR#20
CBS_CGNT#20

CBS_CINT#20

+CBS_VCC

+CBS_VPP

CBS_CIRDY#20
CBS_CC/BE2#20

CBS_RSVD/D220
CBS_CCLKRUN#20

1

1

C580

2

2

0.1U_0402_16V7K~N

0.1U_0402_16V7K~N

2007-02-12 Protect Circuit for ALPS conn

SDDET#_XDDET0#

SDDET#_XDDET0#

JSD1 Pin3

R474 100_0402_5%

28

CD

R476 0_0402_5%

27

GND

R478 100_0402_5%

29

R/-B

R479 22_0402_5%

30

-RE

R480 100_0402_5%

31

-CE

R482 100_0402_5%

32

CLE

R483 100_0402_5%

33

ALE

R485 100_0402_5%

34

-WE

R487 100_0402_5%

35

-WP

36

GND

R489 100_0402_5%

37

D0

R490 100_0402_5%

38

D1

R491 100_0402_5%

39

D2

R492 100_0402_5%

40

D3

R493 100_0402_5%

41

D4

R495 100_0402_5%

42

D5

R497 100_0402_5%

43

D6

R499 100_0402_5%

44

D7

45

VCC

5

NC

7

NC

23

NC

21

NC

26

GND

JSD1 Pin1

1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2

1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2

Short (L)
Open (H) SD WP

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

SD UnWP

XDDET0#

SDWP#_XDRB# 20
SDCLK_MSCLK_XDRE# 20
XDCE# 20
XDCLE 20
XDALE 20
SDCMD_MSBS_XDWE# 20
XDWP 20

SDDATA0_MSDATA0_XDDATA0 20
SDDATA1_MSDATA1_XDDATA1 20
SDDATA2_MSDATA2_XDDATA2 20
SDDATA3_MSDATA3_XDDATA3 20
XDDATA4 20
XDDATA5 20
XDDATA6 20
XDDATA7 20

+XD_VCC

Issued Date

3

CBS_CAD7
CBS_CC/BE0#
CBS_CAD9 CBS_CAD10
CBS_CAD11
CBS_CAD12 CBS_CAD13
CBS_CAD14 CBS_CAD15
CBS_CC/BE1#
CBS_CPAR

CBS_CGNT#
CBS_CINT#

CBS_CIRDY#

CBS_CC/BE2#
CBS_CAD18 CBS_CAD19
CBS_CAD20
CBS_CAD21
CBS_CAD22
CBS_CAD23
CBS_CAD24
CBS_CAD25
CBS_CAD26
CBS_CAD27 CBS_CAD28
CBS_CAD29 CBS_CAD30
CBS_RSVD/D2
CBS_CCLKRUN#

+3V_PHY

1

1

C581

C553

2

2

1000P_0402_50V7K~N

1000P_0402_50V7K~N

U34

2

B

4

OE

SN74CBT1G384_SOT23-5

U35

2

B

4

OE

SN74CBT1G384_SOT23-5

+XD_VCC

XDCE#

+3VS

SDCMD_MSBS_XDWE#

2007/1/25 2008/01/25

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

11

11

12

12

13

13

14

14

15

15

16

16

17

17

18

18

19

19

20

20

21

21

22

22

23

23

24

24

25

25

26

26

27

27

28

28

29

29

30

30

31

31

32

32

33

33

34

34

69

GND

GND

70

GND

GND

71

GND

GND

72

GND

GND

73

GND

GND

74

GND

GND

75

GND

GND

76

GND

GND

77

GND

GND

78

GND

GND

FOX_WZ21131-HR-9F_RB

CONN@

+5VS

5

VCC

SD_MS_XDDATA1

1

A

3

GND

+5VS

5

VCC

SD_MS_XDDATA2

1

A

3

GND

SDCLK_MSCLK_XDRE#

12

R171

2.2K_0402_5%

12

@

R170
33K_0402_5%

Compal Secret Data

Deciphered Date

2

35

35

36

36

37

37

38

38

39

39

40

40

41

41

42

42

43

43

44

44

45

45

46

46

47

47

48

48

49

49

50

50

51

51

52

52

53

53

54

54

55

55

56

56

57

57

58

58

59

59

60

60

61

61

62

62

63

63

64

64

65

65

66

66

67

67

68

68

79
80
81
82
83
84
85
86
87
88

89

NC

90

NC

+3VS

@

@

12

R169
33K_0402_5%@

12

R168
33_0402_5%

2

C305
22P_0402_50V8J

1

2

CBS_CCD1#
CBS_CAD2
CBS_CAD4
CBS_CAD6
CBS_RSVD/D14
CBS_CAD8

CBS_CVS1

CBS_CAD16
CBS_RSVD/A18
CBS_CBLOCK#CBS_CPERR#
CBS_CSTOP#
CBS_CDEVSEL#

CBS_CTRDY#
CBS_CFRAME#
CBS_CAD17

CBS_CVS2
CBS_CRST#
CBS_CSERR#
CBS_CREQ#
CBS_CC/BE3#
CBS_CAUDIO
CBS_CSTSCHNG

CBS_CAD31
CBS_CCD2#

CBS_CRST#

SD_EN20

2

1

SD_EN

10K_0402_1%

12

R177

C315

1U_0603_10V6K

CBS_CAD31
CBS_CAD30

CBS_RSVD/D14 20

CBS_CVS1 20

CBS_RSVD/A18 20
CBS_CBLOCK# 20
CBS_CSTOP# 20
CBS_CDEVSEL# 20

+CBS_VCC

+CBS_VPP
CBS_CTRDY# 20
CBS_CFRAME# 20

CBS_CVS2 20
CBS_CRST# 20
CBS_CSERR# 20
CBS_CREQ# 20
CBS_CC/BE3# 20
CBS_CAUDIO 20
CBS_CSTSCHNG 20

CBS_CCD2# 20

C312

0.01U_0402_16V7K

@

+3VS

U10

3

VIN

4

VIN/CE

2

GND

RT9701-CB_SOT23-5

1

2

XDDET0#

MSDET#_XDDET1#

SDDET#_XDDET0#

Title

Size Document Number Rev

Date: Sheet

CBS_CAD29
CBS_CAD28
CBS_CAD27
CBS_CAD26
CBS_CAD25
CBS_CAD24
CBS_CAD23
CBS_CAD22
CBS_CAD21
CBS_CAD20
CBS_CAD19
CBS_CAD18
CBS_CAD17
CBS_CAD16
CBS_CAD15
CBS_CAD14
CBS_CAD13
CBS_CAD12
CBS_CAD11
CBS_CAD10
CBS_CAD9
CBS_CAD8
CBS_CAD7
CBS_CAD6
CBS_CAD5
CBS_CAD4
CBS_CAD3
CBS_CAD2
CBS_CAD1
CBS_CAD0

1

VOUT

5

VOUT

R178 0_0805_5%

1 2

D

S

G

@

Q26

2

AOS3401_SOT23

D7
RB751V_SOD323

2 1

2 1

D18
RB751V_SOD323

Compal Electronics, Inc.

1394 & Media Card

Wednesday, April 11, 2007

C323

+XD_VCC+SD_VCC

13

LA-3611P

1

+SD_VCC

1

2

0.01U_0402_16V7K

1

C314

2.2U_0603_10V6K

2

+3VS

12

1

CBS_CAD[0..31] 20CBS_CCD1# 20

1

C322

2

1U_0603_10V6K

R163
33K_0402_5%

XDDET0#

12

R173
150K_0402_5%

of

21 40

0.4

5

PCIE_LAN_C_RX_P210

PCIE_LAN_C_RX_N210

D D

1 2

R211 15K_0402_5%

15P_0402_50V8J

C C

C13 0.01U_0402_16V7K

1 2

C11 0.01U_0402_16V7K

1 2

B B

A A

PCIE_LAN_C_RX_P2
PCIE_LAN_C_RX_N2

power trace width=20mil

+3VS

12

R210
1K_0402_5%

1 2

2

25MHZ_12P_X8A025000FC1H-H

C375

1

R7
0_0805_5%

@

C12 0.01U_0402_16V7K

1 2

C10 0.01U_0402_16V7K

1 2

RJ45_TX3­RJ45_TX3+
RJ45_RX1­RJ45_TX2­RJ45_TX2+
RJ45_RX1+
RJ45_TX0­RJ45_TX0+

5

PCIE_LAN_C_TX_P210
PCIE_LAN_C_TX_N210

Y2

15P_0402_50V8J

1 2

C378 0.1U_0402_16V7K~N

1 2

C379 0.1U_0402_16V7K~N

1 2

CLK_PCIE_LAN13
CLK_PCIE_LAN#13

NB_RST#11,15,19,25,26,27

PCIE_WAKE#16,20,26,27

2

1

C374

V_DACLAN_AVDD18

V_DAC

V_DAC

12
11

10

1 2

R204 2.49K_0402_1%

MDIN3
MDIP3

MDIN2
MDIP2

V_DAC
MDIN1
MDIP1

V_DAC
MDIN0
MDIP0

JLAN1

NC
NC

8

PR4-

7

PR4+

6

PR2-

5

PR3-

4

PR3+

3

PR2+

2

PR1-

1

PR1+
NC

9

NC

TYCO_3-440470-4

RTL_LAN_TX_P2

RTL_LAN_TX_N2
PCIE_LAN_C_TX_P2
PCIE_LAN_C_TX_N2

CLK_PCIE_LAN
CLK_PCIE_LAN#
NB_RST#

LAN_CTRL18
LAN_CTRL15

RSET

ISOLATEB

LAN_XTAL1
LAN_XTAL2

LAN_GVDD

1 2

C25 0.1U_0402_10V7K~N

1 2

C15 1U_0402_6.3V6K

L33

LAN_EGND

12

0_0603_5%

T1

1

TCT1

MCT1

2

TD1+

MX1+

3

TD1-

MX1-

4

TCT2

MCT2

5

TD2+

MX2+

TD2-6MX2-

7

TCT3

MCT3

8

TD3+

MX3+

9

TD3-

MX3-

10

TCT4

MCT4

11

TD4+

MX4+

12

TD4-

MX4-

BOTH_GST5009-LF

16

SHLD2

15

SHLD1

14

SHLD2

13

SHLD1

4

U15

29

HSOP

30

HSON

23

HSIP

24

HSIN

26

REFCLK_P

27

REFCLK_N

20

PERSTB

1

VCTRL18

63

VCTRL15

64

RSET

19

LANWAKEB

36

ISOLATEB

60

CKXTAL1

61

CKXTAL2

62

GVDD

25

EGND

31

EGND

17

NC

18

NC

35

NC

34

NC

39

NC

40

NC

42

NC

50

NC

51

NC

65

GND

RTL8111B-GR_QFN64

24

RJ45_TX3-

23

RJ45_TX3+

22
21

RJ45_TX2-

20

RJ45_TX2+

19
18

RJ45_RX1-

17

RJ45_RX1+

16
15

RJ45_TX0-

14

RJ45_TX0+

13

4

EEDO

EDDI/AUX

EESK
EECS

LED3
LED2
LED1
LED0

MDIP0
MDIN0
MDIP1
MDIN1

MDIP2
MDIN2
MDIP3
MDIN3

VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15

VDD33
VDD33
VDD33

VDD33
AVDD33
AVDD33

AVDD18
AVDD18
AVDD18
AVDD18

EVDD18
EVDD18

75_1206_8P4R_5%

RP17

45
47
48
44

54
55
56
57

3
4
6
7

9
10
12
13

15
21
32
33
38
41
43
49
52
58

16
37
53
46

2
59

5
8
11
14

22
28

LAN_EEDO
LAN_EEDI
LAN_EECLK
LAN_EECS

LAN_EGND

18
27
36
45

LAN_DVDD15

3

3.6K_0402_5%

1 2

U16

4

DO

3

DI

2

SK

1

CS

AT93C46-10SU-2.7 SO 8P

SSM3K7002FU_SC70-3

+LAN_IO

GND

VCC

NC
NC

MDIP0
MDIN0
MDIP1
MDIN1

MDIP2
MDIN2
MDIP3
MDIN3

R209

1.5v & 1.8v output power trace width=40mil

LAN_AVDD33

1

C30

2

0.1U_0402_10V7K~N

C28 0.1U_0402_16V7K~N
C16 0.1U_0402_16V7K~N

1

2

LAN_AVDD18

LAN_EVDD18

1

C33

2

0.1U_0402_10V7K~N

C356
1000P_1206_2KV7K

12

+LAN_IO

5

R212

6

1 2

0_0402_5%

7

@

8

1U_0603_10V6K

B+_BIAS

1 2
13

D

Q38

S

FBML10160808121LMT_0603

1 2
1 2

R205 0_0805_5%

1 2

C376

4.7U_0805_6.3V6K~N

@

LAN_CTRL15

1 2

C357 0_0402_5%

1 2

C355 0_0402_5%

1 2

C354 0_0402_5%

1 2

C358 0_0402_5%

R213
470K_0402_5%

L2

12

LAN_AVDD18

1

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

1

C38

0.1U_0402_16V7K~N

+LAN_IO

2

+3VALW

1

C382

2

EN_WOL

2

G

+LAN_IO

+LAN_IO

3

Q35
2SB1188_SOT89

2

2007/1/25 2008/01/25

Q36

D

6

S

2
1

SI3456BDV-T1-E3_TSOP6

G

3

EN_WOL# 26

LAN_CTRL18

LAN_DVDD15_R

1

C371
22U_1206_6.3V6M

2

Compal Secret Data

L34

FBMA-L11-322513-201LMA40T_1210

1 2

45

+LAN_IO

3

1

2

L32

1 2

0_0805_5%

Deciphered Date

2

1

C608

@

2

22U_1206_6.3V6M

Q34
2SB1188_SOT89

1

C381

2

22U_1206_6.3V6M

LAN_AVDD18_R

1

C364

2

4.7U_0805_6.3V6K~N

1

C210.1U_0402_10V7K~N

2

+LAN_IO

1.5A

1

C377

2

1

C365
22U_1206_6.3V6M

2

1

C290.1U_0402_10V7K~N

2

1

1

C34

2

0.1U_0402_10V7K~N

L31

1 2

0_0603_5%

1

C390.1U_0402_10V7K~N

2

0.1U_0402_10V7K~N

LAN_DVDD15

1

1

C270.1U_0402_10V7K~N

C3800.1U_0402_10V7K~N

2

2

Title

Size Document Number Rev

Custom

Date: Sheet

1

2

1

C170.1U_0402_10V7K~N

2

1

1

C310.1U_0402_10V7K~N

C350.1U_0402_10V7K~N

2

2

LAN_AVDD18

1

C190.1U_0402_10V7K~N

2

1

C260.1U_0402_10V7K~N

2

1

C22

2

1

C180.1U_0402_10V7K~N

2

1

C320.1U_0402_10V7K~N

2

C37

0.1U_0402_10V7K~N

1

C3660.1U_0402_10V7K~N

2

Realtek 8100CL/RJ45
LA-3611P

1

0.1U_0402_10V7K~N

1

C200.1U_0402_10V7K~N

2

1

C360.1U_0402_10V7K~N

2

0.4

of

22 40Wednesday, April 11, 2007

A

B

C

D

E

F

G

H

MDC CONN.

MDC_HD_SDOUT

W=20 mil

1

C14

2

10P_0402_50V8J

MDC_HD_BITCLK

+3V

1

C23

2

4.7U_0805_10V4Z

0.1U_0402_16V7K~N

C24

@

MDC_ACZ_BITCLK_TERM

1 2

1

2

R9

@

10_0402_5%

1 2

MDC_ACZ_SDOUT_MDCTERM

1

2

R202

@

C362

@

10_0402_5%

10P_0402_50V8J

Adjustable Output

U23

4

VIN

2

SENSE or ADJ

DELAY

C155

1 1

4.7U_0805_10V4Z

+5VS

R67 10K_0402_5%

0.1U_0402_16V7K~N

1 2

ERROR7CNOISE

C156

8

SD

SI9182DH-AD-T1-E3_MSOP8~N

VOUT

GND

5
6
1
3

C154 0.01U_0402_16V7K

1 2

12

R270

23.7K_0402_1%

R271
10K_0603_1%

+VDDA+5VS

1

1

2

C167 4.7U_0805_10V4Z~N

2

HD_SDIN016

C168 0.1U_0402_16V7K~N

R203

1 2

33_0402_5%

MDC_HD_SDOUT

MDC_HD_SYNC

MDC_HD_RST#

MDC_HD_SDOUT16

MDC_HD_SYNC16
MDC_HD_RST#16

1 2

C367 10P_0402_50V8J@

1 2

C368 10P_0402_50V8J@

1 2

C372 10P_0402_50V8J@

MDC_HD_SDOUT
MDC_HD_SYNC

HD_SDIN0_MDC
MDC_HD_RST#

JMDC1

1

GND1

3

IAC_SDATA_OUT

5

GND2

7

IAC_SYNC

9

IAC_SDATA_IN

11

IAC_RESET#

RES0
RES1

3.3V
GND3
GND4

IAC_BITCLK

131314141515161617171818191920

2
4
6
8
10
12

20

ACES_88023-12001~N

Connector for MDC Rev1.5

Follow AK1s

MDC_HD_BITCLK16

MDC_POWER

MDC_HD_BITCLK

0_0603_5%

1 2

R8

+3VS

HD Audio Codec

20mil

DVDD11DVDD2

MONO_O

HP_OUT_L

HP_OUT_R

BIT_CLK

SDATA_IN

GPIO2

GPIO3

VREF

DCVOL

SENSE B

GPIO0
GPIO1

JDREF
AVSS1
AVSS2

0.1U_0402_16V7K~N

1

2

9

LINEL

35

LINER

36
37

HP_LOUT

39

HP_ROUT

41

6

SDIN_CODEC

8
2

3
29
30
28

10mil

27
32

10mil

31
33
34
43
44

40
26
42

1

C485

C491

2

0.1U_0402_16V7K~N

C483 1000P_0402_50V7K~N
C482 1000P_0402_50V7K~N

C496 1000P_0402_50V7K~N
C495 1000P_0402_50V7K~N

R308 0_0402_5%@

+MIC1_VREFO_L

+MIC1_VREFO_R

R307 10K_0402_1%

+AVDD_AC97

2 2

3 3

HD_RST#16
HD_SYNC16
HD_SDOUT16

L40

+VDDA

FBM-L11-160808-800LMT_0603

2

C478

1

@

10P_0402_25V8K

10P_0402_25V8K

1 2

10U_0805_10V4Z~N

MIC124
MIC224

MIC_JD24

HD_RST#

2

C479

1

@

@

10P_0402_25V8K

C184

C477 2.2U_0603_10V6K
C476 2.2U_0603_10V6K

HP_JD

R301 39.2K _0402_1%
R300 20K _0402_1%

2

EAPD24

R95

C486

0_0402_5%@

1

1 2

0.1U_0402_16V7K~N

1

C185

2

1 2
1 2

1

1

2

2

0.1U_0402_16V7K~N

C_MIC1

C_MIC2

12
12

R96

40mil

C490

12

0_0402_5%@

38

U4

AVDD125AVDD2

14

LINE2_L

15

LINE2_R

16

MIC2_L

17

MIC2_R

23

LINE1_L

24

LINE1_R

18

CD_L

20

CD_R

19

CD_GND

21

MIC1_L

22

MIC1_R

13

SENSE A

12

BEEP

11

RESET#

10

SYNC

5

SDATA_OUT

45

NC

46

NC

47

SPDIFI/EAPD

48

SPDIFO

4

DVSS1

7

DVSS2

ALC262-GR_LQFP48~N

LINE_OUT_L

LINE_OUT_R

LINE1_VREFO

MIC2_VREFO

MIC1_VREFO_L

MIC1_VREFO_R

LINE2_VREFO

DGND AGND

4 4

10_0402_5% @

R80

1 2

33_0402_5%

12

AC97_VREF

12

12

R309
20K_0402_1%

For EMI

0_0603_5%

1 2

R97

1

C497
10U_0805_6.3V6M

2

R90

CODEC_GPIO2

1 2

26

26

+VDDA

+3VS

1 2
1 2

10P_0402_25V8K

12

R310
0_0402_5%

@

1 2
1 2

1 2

C218

@

HD_BITCLK 16

HD_SDIN3 16

R80: ATI--33ohm, Realtek--22ohm

10mil

1

C484
10U_0805_6.3V6M

2

R86 6.8k_0603_5%
R87 6.8k_0603_5%

R93 0_0603_5%
R94 0_0603_5%

AMP_LEFT 24
AMP_RIGHT 24

HP_LEFT 24
HP_RIGHT 24

HD_RST#

CODEC_GPIO2

PLUG_IN24

D17

@

RB751V_SOD323

R346

1 2

1M_0402_5%

C518

10U_0805_6.3V6M

R340 0_0402_5%

PLUG_IN

21

1

2

12

R354

R355

1 2

1 2

100K_0402_5%

13

D

2

G

S

@

R345 0_0402_5%

+3VS +3VS

I2O

74LVC1G125GW_SOT3535

Reserved for TEST

R374 0_0805_5%
R240 0_0805_5%
R373 0_0805_5%
R258 0_0805_5%

GND AGND

100K_0402_5%

PLUG_IN#

Q45
SSM3K7002FU_SC70-3

12

5

1

P

OE#

G

U29

3

1 2
1 2
1 2
1 2

PLUG_IN# 24

HP_JD

13

D

Q46

2

SSM3K7002FU_SC70-3

G

S

EAPD Control for Vista

5

U28

2

4

P

B

1

A

G

NC7SZ08P5X_NL_SC70-5

3

R339 0_0402_5%

4

Y

12

@

1

C517

0.1U_0402_16V7K~N

2

EAPD 24

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

C

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

D

2007/1/25 2008/01/25

E

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

F

Date: Sheet

Compal Electronics, Inc.

Codec ALC262

LA-3611P

G

0.4

of

23 40Wednesday, April 11, 2007

H

A

W=40Mil

1

1

C137

0.1U_0402_16V7K~N

4 4

AMP_RIGHT23

AMP_LEFT23

3 3

EC_MUTE26

C451

0.47U_0603_16V7K

C443

0.47U_0603_16V7K

C452

0.47U_0603_16V7K

C442

0.47U_0603_16V7K

+3VS

12

R245
100K_0402_5%

13

D

2

G

S

EAPD23

1 2

AMP_R

1 2

1 2

AMP_L

1 2

Q43
SSM3K7002FU_SC70-3

EAPD

2

2

12

R251
20K_0402_1%

C453
10U_0805_10V4Z~N

7

RIN+

17

RIN-

9

LIN+

5

LIN-

19

SHUTDOWN

GND

21

D15

2 1

RB751V_SOD323

15

16

VDD

PVDD1

GND41GND311GND213GND1

20

Buzzer need to support ICH/PCM_SPK/Battery_low and WL_on/off

2 2

Buzzer

EC Beep

13

2

G

G

2

2

G

D

Q54

S

S

Q52

D

1 3

13

D

Q53
SSM3K7002FU_SC70-3

S

R450

BEEP#26

CardBus Beep

PCM_SPK#20

1 1

ICH Beep

SB_SPKR16

1 2

0_0402_5%

SSM3K7002FU_SC70-3

R449

1 2

0_0402_5%

AP2301GN 1P SOT23

R437

1 2

0_0402_5%

A

B

6

U2

PVDD2

2

GAIN0

3

GAIN1

18

ROUT+

14

ROUT-

4

LOUT+

8

LOUT-

12

NC

10

BYPASS

P3017THF TSSOP 20P

R246

1 2

2.7K_0402_5%

BUZR_OFF26

AP2301GN 1P SOT23

B

PLUG_IN

+5VS

+5VS

2

1

12

R456

RB751V_SOD323

R49 10K_0402_5%

1 2

R39 10K_0402_5%@

1 2

SPK_R1

SPK_R2

SPK_L1

SPK_L2

C143

0.47U_0603_16V7K

+3VS

56.2_0603_1%

12

R453

S

G

2

D

1 3

D20

2 1

56.2_0603_1%

Q55

BUZZER

R244 10K_0402_5%

1 2

R250 10K_0402_5%@

1 2

1 2

R43 0_0603_5%

1 2

R42 0_0603_5%

1 2

R40 0_0603_5%

1 2

R41 0_0603_5%

INTSPK_R1

INTSPK_R2

INTSPK_L1

INTSPK_L2

GAIN0 GAIN1 GAIN

00

0

*

1

0

1

1

2

C602

0.1U_0402_16V7K

1

BUR1

+

1
2

-

LET9040-03A_2P

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date

C

MIC223
MIC123

D

Speaker Connector

INTSPK_R1
INTSPK_R2
INTSPK_L1
INTSPK_L2

MICROPHONE IN JACK

R663K_0402_5%
R593K_0402_5%

12
12

1 2

L8 CHB2012U170_0805

1 2

L6 CHB2012U170_0805

C465

220P_0402_50V7K

JSPK1

1

1

2

2

3

3

G1

4

4

G2

ACES_88266-04001~N

+MIC1_VREFO_R
+MIC1_VREFO_L

MIC_JD23

MIC-2
MIC-1

1

C466

2

220P_0402_50V7K

E

5
6

FOX_JA6333L-B3S0-7F~N

5
4
3

6 7
2

1

2

1

JMIC1

10
9
8

HEADPHONE OUT JACK

FOX_JA6333L-B3S0-7F~N

5
4
3

6 7
2
1

2

C494
470P_0402_50V7K

1

+3VS

R371

5

1

2

JHP1

Reserve the 0 ohm resistor.

12

for voltage filtering

1 2

C544 1U_0603_10V6K

10

19

OUTR

SVDD

PVDD

OUTL

NC-4
NC-6

NC-8
NC-12
NC-16
NC-20

PGND

PVss

SVss

SGND

MAX4411ETP+T_TQFN20~N

2

7

17

C551
1U_0603_10V6K

10
9
8

HP_OUTR

11

HP_OUTL

9

4
6
8
12
16
20

Compal Electronics, Inc.

AMP/Audio Jack

E

24 40Wednesday, April 11, 2007

0.4

of

HP_R
HP_L

R88

PLUG_IN

1 2

L42 CHB2012U170_0805

1 2

L41 CHB2012U170_0805

12

12

R92
1K_0402_5%@

HPR
HPL

C489

470P_0402_50V7K

2

1

6dB

HP_OUTR
HP_OUTL

R91
R89

1 2

47_0402_5%

1 2

47_0402_5%

PLUG_IN23

1K_0402_5%@

10dB

15.6dB

21.6dB1

PLUG_IN#23

HP_RIGHT23

HP_LEFT23

2007/1/25 2008/01/25

C

Compal Secret Data

Deciphered Date

EAPD

+3VS

5

U31

2

P

B

Y

1

A

G

NC7SZ08P5X_NL_SC70-5

3

HP_INR HPINR

1 2

C524 2.2U_0603_10V6K

HP_INL HPINL

1 2

C523 2.2U_0603_10V6K

D

HP_MUTE#

4

HP_MUTE#

1 2
1 2

0_0603_5%

U30

14

SHDNR#

18

SHDNL#

R353

6.8K_0603_5%
R352

6.8K_0603_5%

1

2

15

INR

13

INL

1

C1P

3

C552
1U_0603_10V6K

C1N

Title

Size Document Number Rev

LA-3611P

Date: Sheet

A

2

C332

0.1U_0402_16V7K~N

1

1 1

2

C600

0.1U_0402_16V7K~N

1

2

C333

0.1U_0402_16V7K~N

1

2

C599

0.1U_0402_16V7K~N

1

+1.5VS

+3VS

2

1

B

+3VALW

1

C598

0.1U_0402_16V7K~N

C597
10U_0805_10V4Z~N

2

Placement Closed to JMINI1

C

2

C331

0.1U_0402_16V7K~N

1

2

C596

0.1U_0402_16V7K~N

1

2

C330

0.1U_0402_16V7K~N

1

2

C593

0.1U_0402_16V7K~N

1

D

+1.5VS +3VALW

1

C329
10U_0805_10V4Z~N

2

+3VS

1

C328
10U_0805_10V4Z~N

2

2

C594

0.1U_0402_16V7K~N

1

Placement Closed to JMINI2

2

C595

0.1U_0402_16V7K~N

1

E

Mini-Express Card (Reserve for debug or TV)

+3VALW

+1.5VS

JMINI1

1

1

3

3

5

5

7

7

9

9

11

11

13

13

15

PCI_RST#15,20

CLK_PCI_SIO_DB15

2 2

3 3

PCI_RST#
CLK_PCI_SIO_DB

R184 0_0402_5%

1 2

R183 0_0402_5%

1 2

15

17

17

19

19

21

21

23

23

25

25

27

27

29

29

31

31

33

33

35

35

37

37

39

39

41

41

43

43

45

45

47

47

49

49

51

51

53

GND1

FOX_AS0B226-S52N-7F~N

CONN@

GND2

2

2

4

4

6

6

8

8

10

10

12

12

14

14

16

16

18

18

20

20

22

22

24

24

26

26

28

28

30

30

32

32

34

34

36

36

38

38

40

40

42

42

44

44

46

46

48

48

50

50

52

52

54

+3VS

R447 0_0402_5%

1 2

R446 0_0402_5%

1 2

R445 0_0402_5%

1 2

R444 0_0402_5%

1 2

R443 0_0402_5%

1 2

USB20P7- 16
USB20P7+ 16

LPC_FRAME#

LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0

LPC_FRAME# 15,26

LPC_AD[0..3] 15,26

PCIE_WLAN_C_RX_N110
PCIE_WLAN_C_RX_P110

PCIE_WLAN_C_TX_N110

PCIE_WLAN_C_TX_P110

Wireless_BTN

Killer switch

+3VS

@

12

R455
100K_0402_5%

SW2
1BS003-1210L_3P

3

CLK_PCIE_WCARD#13

CLK_PCIE_WCARD13

11223

W_DISABLE#

CLKREQA#13

PCI_RST#
CLK_PCI_SIO_DB

R458 0_0402_5%
R457 0_0402_5%

Mini-Express Card

1 2

R467 0_0402_5%

R460 0_0402_5%

1 2

R459 0_0402_5%

1 2

LED_WLAN#

PCIE_C_RXN2
PCIE_C_RXP2

1 2
1 2

+3VS

1
3
5
7

9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51

53

JMINI2

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51

GND1

FOX_AS0B226-S52N-7F~N

CONN@

R452

1 2

10K_0402_5%

GND2

2

G

10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

2
4
6
8

R506 0_0402_5%@

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

54

1 2

13

D

Q59
SSM3K7002FU_SC70-3

S

+3VALW

LED_WLAN

BATT_CHG_LED#26

+1.5VS

+3VS

2

G

1 2
1 2
1 2
1 2
1 2

W_DISABLE#
NB_RST#

LED_WLAN#

13

D

S

R4420_0402_5%
R4410_0402_5%
R4400_0402_5%
R4390_0402_5%
R4380_0402_5%

NB_RST# 11,15,19,22,26,27

USB20P8- 16
USB20P8+ 16

WLAN LED

D21
12-21-BHC-ZL1M2RY-2C BLUE

Q58
SSM3K7002FU_SC70-3

D10
HT-110UY_AMBER

LPC_FRAME#

LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0

12

12

R472

1 2

200_0603_5%

R511

1 2

200_0603_5%@

1 2

390_0603_5%

+5VS

+3VS

+5VALW

R471

R454

1.5M_0402_5%

1 2

+3VS

1 2

R451 10K_0402_5%@

1 2

R180 10K_0402_5%

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

W_DISABLE#

LED_WLAN#

PWR_GREEN_LED#26

2007/1/25 2008/01/25

C

Compal Secret Data

Deciphered Date

D

BATT_LOW_LED#26

13

D

2

G

S

Title

Size Document Number Rev

Custom

Date: Sheet

D8

19-213UYC/S530-A3/TR8 0603 YELLOW

D9

HT-F194NB5-DT_BLUE_0603

Q57
SSM3K7002FU_SC70-3

MINICARD
LA-3611P

R470

1 2

21

390_0603_5%

21

E

R469

1 2

200_0603_5%

25 40Wednesday, April 11, 2007

0.4

of

5

L43

MBK1608800YZF 0603

CLK_PCI_EC

12

R113
10_0402_5%@

1

C247
15P_0402_50V8D@

2

PCIE_WAKE#16,20,22,27

Internet_BTN
ECO_BTN
DIMMER_BTN
SOFT_BTN

EC_SMB_DA1
EC_SMB_CK1

EC_SMB_DA2
EC_SMB_CK2

1 2

1 2

L21 MBK1608800YZF 0603

R108

RP19

1 8
2 7
3 6
4 5

10K_0804_8P4R_5%

NB_RST#

SW_CONFIG1
SW_CONFIG2
SW_RSV1
SW_RSV2

1 2

RP18

1 8
2 7
3 6
4 5

10K_0804_8P4R_5%

TP_DATA

1 2

TP_CLK

1 2

R343 4.7K_0402_5%
R342 4.7K_0402_5%

R110 4.7K_0402_5%
R107 4.7K_0402_5%

2

C246
1000P_0402_50V7K~N

@

1

R119 10K_0402_5%
R118 10K_0402_5%

5

2

C5110.1U_0402_16V7K~N

1

ECAGND

+3VALW

1 2

0_0402_5%

+3VALW

100K_0402_5%@

12
12

12
12

+EC_AVCC

1

C228
1000P_0402_50V7K~N

2

R334

1 2

47K_0402_5%

0.1U_0402_16V7K~N

EC_PME#

LID_SW#

EC_MUTE
E-Mail_BTN

MSEN#

R348

+3VALW

+5VS

+5VALW

+3VS

EC_RST#

2

C509

1

R112 10K_0402_5%

1 2

R344 10K_0402_5%

1 2

R111 10K_0402_5%

1 2

R128 10K_0402_5%

1 2

R338 10K_0402_5%

1 2

15P_0402_50V8J

+3VALW

R141

1 2

0_0805_5%

LPC_AD[0..3]15,25

+3VALW

PWRBTN_OUT#16

1

C265

2

32.768KHZ_1TJS125BJ4A421P

KSI[0..7]27

KSO[0..15]27

SW_CONFIG127
SW_CONFIG227

EC_SMB_CK137
EC_SMB_DA137
EC_SMB_CK26
EC_SMB_DA26

SLP_S3#16
SLP_S5#16

EC_SMI#16

LID_SW#28

SUSP#27,30

FAN_SPEED14

SCRLED#29

NUMLED#29

Y1

+3VALW

D D

C C

B B

A A

+3VALW_ECVCC

1

C528

2

0.1U_0402_16V7K~N

EC_GA2016

KB_RST#16

SIRQ15,20

CLK_PCI_EC15

NB_RST#11,15,19,22,25,27

EC_SCI#16

PM_CLKRUN#15,20

ON_OFF29

4

1

IN

OUT

NC3NC

2

4

0.1U_0402_16V7K~N

1

C527

2

1000P_0402_50V7K~N

KSI[0..7]

KSO[0..15]

SW_CONFIG1
SW_CONFIG2

EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2

EC_SMI#
LID_SW#

EC_PME#
FAN_SPEED1
EC_TX_P80DATA

EC_RX_P80CLK

CRY2
CRY1

CRY1

CRY2

1

C264
15P_0402_50V8J

2

4

1

2

EC_GA20

KB_RST#

LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0

NB_RST#
EC_SCI#

0.1U_0402_16V7K~N

C529

10
12

13
37
20
38

KSI0

55

KSI1

56

KSI2

57

KSI3

58

KSI4

59

KSI5

60

KSI6

61

KSI7

62

KSO0

39

KSO1

40

KSO2

41

KSO3

42

KSO4

43

KSO5

44

KSO6

45

KSO7

46

KSO8

47

KSO9

48

KSO10

49

KSO11

50

KSO12

51

KSO13

52

KSO14

53

KSO15

54
81
82

77
78
79
80

14
15
16
17
18
19
25
28
29
30
31
32
34
36

122
123

1
2
3
4
5
7
8

6

1

2

U5

1000P_0402_50V7K~N

1

C516

C510

2

GA20/GPIO00
KBRST#/GPIO01
SERIRQ#
LFRAME#
LAD3
LAD2
LAD1

LPC & MISC

LAD0
PCICLK

PCIRST#/GPIO05
ECRST#
SCI#/GPIO0E
CLKRUN#/GPIO1D

KSI0/GPIO30
KSI1/GPIO31
KSI2/GPIO32
KSI3/GPIO33
KSI4/GPIO34
KSI5/GPIO35
KSI6/GPIO36
KSI7/GPIO37
KSO0/GPIO20
KSO1/GPIO21
KSO2/GPIO22
KSO3/GPIO23
KSO4/GPIO24

Int. K/B

KSO5/GPIO25

Matrix

KSO6/GPIO26
KSO7/GPIO27
KSO8/GPIO28
KSO9/GPIO29
KSO10/GPIO2A
KSO11/GPIO2B
KSO12/GPIO2C
KSO13/GPIO2D
KSO14/GPIO2E
KSO15/GPIO2F
KSO16/GPIO48
KSO17/GPIO49

SCL1/GPIO44
SDA1/GPIO45
SCL2/GPIO46
SDA2/GPIO47

PM_SLP_S3#/GPIO04
PM_SLP_S5#/GPIO07
EC_SMI#/GPIO08
LID_SW#/GPIO0A
SUSP#/GPIO0B
PBTN_OUT#/GPIO0C
EC_PME#/GPIO0D
EC_THERM#/GPIO11
FAN_SPEED1/FANFB1/GPIO14
FANFB2/GPIO15
EC_TX/GPIO16
EC_RX/GPIO17
ON_OFF/GPIO18
PWR_LED#/GPIO19
NUMLED#/GPIO1A

XCLK1
XCLK0

SM Bus

3

+EC_AVCC

9

22

33

96

111

125

67

VCC

VCC

VCC

VCC

VCC

VCC

AVCC

INVT_PWM/PWM1/GPIO0F

BEEP#/PWM2/GPIO10

FANPWM1/GPIO12

ACOFF/FANPWM2/GPIO13

PWM Output

BATT_TEMP/AD0/GPIO38

BATT_OVP/AD1/GPIO39

ADP_I/AD2/GPIO3A

AD Input

DA Output

PS2 Interface

SPI Device Interface

SPI Flash ROM

GPIO

GPO

GPIO

GPI

GND

GND

GND

GND

GND

11

24

35

94

113

AD3/GPIO3B

AD4/GPIO42

SELIO2#/AD5/GPIO43

DAC_BRIG/DA0/GPIO3C

EN_DFAN1/DA1/GPIO3D

IREF/DA2/GPIO3E

DA3/GPIO3F

PSCLK1/GPIO4A
PSDAT1/GPIO4B
PSCLK2/GPIO4C

PSDAT2/GPIO4D

TP_CLK/PSCLK3/GPIO4E

TP_DATA/PSDAT3/GPIO4F

SDICS#/GPXOA00
SDICLK/GPXOA01

SDIDO/GPXOA02

SDIDI/GPXID0

SPICLK/GPIO58

CIR_RX/GPIO40

CIR_RLC_TX/GPIO41

FSTCHG/SELIO#/GPIO50

BATT_CHGI_LED#/GPIO52

CAPS_LED#/GPIO53

BATT_LOW_LED#/GPIO54

SUSP_LED#/GPIO55

SYSON/GPIO56

VR_ON/XCLK32K/GPIO57

AC_IN/GPIO59

EC_RSMRST#/GPXO03
EC_LID_OUT#/GPXO04

EC_ON/GPXO05

EC_SWI#/GPXO06

ICH_PWROK/GPXO06

BKOFF#/GPXO08

WL_OFF#/GPXO09

PM_SLP_S4#/GPXID1

ENBKL/GPXID2

AGND

KB926QFA1_LQFP128_14X14

69

ECAGND

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

SPIDI/RD#

SPIDO/WR#

SPICS#

GPXO10
GPXO11

GPXID3
GPXID4
GPXID5
GPXID6
GPXID7

V18R

21
23
26
27

C508 0.01U_0402_16V7K

1 2
63
64
65

AD_BID0

66
75
76

68
70
71
72

EC_MUTE

83
84
85
86

TP_CLK

87

TP_DATA

88

SPI_PD

97
98
99
109

FRD#SPI_SO

119

FWR#SPI_SI

120

SPI_CLK

126

FSEL#SPICS#

128

73

MSEN#

74
89

BATT_CHG_LED#

90
91
92
93
95
121
127

100
101
102
103

VLDT_EN

104
105

DIMMER_STATUS

106
107

BUZR_OFF

108

110

ENABLT

112
114

EC_THERM#

115
116

E-Mail_BTN

117

Internet_BTN

118
124

+3VALW

EC_TX_P80DATA
EC_RX_P80CLK

2007/1/25 2008/01/25

INVT_PWM 14
BEEP# 24
ECO_BTN 29
ACOFF 31,32LPC_FRAME#15,25

ECAGND

BATT_TEMP 37

BATT_OVP 32
ADP_I 32

LIGHT_SENSOR 29

DAC_BRIG 14
EN_DFAN1 4

IREF 32

EC_MUTE 24

USB_EN 28
ECO_GREEN_LED# 29
ECO_BLUE_LED# 29
TP_CLK 27
TP_DATA 27

R473 4.7K_0402_5%

1 2

EN_WOL# 22

SBPWR_EN 18
SOFT_BTN 29

R351 15_0402_5%

12

R350 15_0402_5%

12

R130 15_0402_5%

12

R120 15_0402_5%

12

GPLED 27

MSEN# 14
FSTCHG 32
BATT_CHG_LED# 25
CAPSLED# 29
BATT_LOW_LED# 25
PWR_GREEN_LED# 25
SYSON 27,30
VR_ON 36
ACIN 31

EC_RSMRST# 16
EC_LID_OUT# 16
EC_ON 29
EC_SWI# 16

VLDT_EN 30
BKOFF# 14

DIMMER_STATUS 29
BUZR_OFF 24

SW_RSV2 27

ENABLT 11,14
DIMMER_BTN 29
EC_THERM# 17

SW_RSV1 27
E-Mail_BTN 29
Internet_BTN 29

JECDB1

1

1

2

2

3

3

4

4

ACES_85205-0400

CONN@

Compal Secret Data

Deciphered Date

2

VLDT_EN

RS690M & SB600 PowerGD

2007-02-12 MUST PULL DOWN!!!

EC_SI_SPI_SO
EC_SO_SPI_SI
SPI_CLK_R
SPI_CS#

0.1U_0402_10V7K~N

2

C275
1U_0603_10V6K

+3VALW

12

R100
100K_0402_5%

R337
18K_0402_1%

1 2

+5VALW

C488

R358
0_0402_5%

1 2

0.1U_0402_16V7K~N

1 2

U26

8
7
6
5

AT24C16AN-10SU-2-7 SO 8P

R127

1 2

20K_0402_1%

1

2

Ra

Rb

EC_SMB_CK1
EC_SMB_DA1

SPI Flash (8Mb*1)

C221

1 2

10K_0402_5%

+3VALW

20mils

R99

1 2

SPI_CS#
SPI_CLK_R
EC_SO_SPI_SI EC_SI_SPI_SO

U27

8

VCC

3

W

7

HOLD

1

S

6

C

5

D

SST25LF080A_SO8-200mil

Title

Size Document Number Rev

Custom

Date: Sheet

1

0.47U_0603_16V7K@

2

NB_PWRGD 11

FOR Board ID

AD_BID0

1

C512

0.1U_0402_16V7K~N

2

A0

VCC

A1

WP
SCL

A2

SDA

GND

Reserve for EMI, close to SPI ROM

4

VSS

2

Q

C542

+5VALW

12

1
2
3
4

12

12

@

2

@

1

KB926&BIOS
LA-3611P

1

SB_PWRGD 6,16

R323
100K_0402_5%

R324
100K_0402_5%

SPI_CLK_R

R98
33_0402_5%

C224
22P_0402_50V8J

1

0.4

of

26 40Wednesday, April 11, 2007

KSO8

C209 100P_0402_25V8K@

KSI3

C198 100P_0402_25V8K@

KSO9

C208 100P_0402_25V8K@

KSI2

C199 100P_0402_25V8K@

KSI1

C200 100P_0402_25V8K@

KSO10

C207 100P_0402_25V8K@

KSO11

C206 100P_0402_25V8K@

KSI0

C201 100P_0402_25V8K@

KSO12

C205 100P_0402_25V8K@

KSO13

C204 100P_0402_25V8K@

KSO14

C203 100P_0402_25V8K@

KSO15

C202 100P_0402_25V8K@

INT_KBD CONN.

JKB1

KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15
KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7

26

G2

25

G1

24

24

23

23

22

22

21

21

20

20

19

19

18

18

17

17

16

16

15

15

14

14

13

13

12

12

11

11

10

10

9

9

8

8

7

7

6

6

5

5

4

4

3

3

2

2

1

1

ACES_85201-24051~N

CONN@

(Right)

(Left)

C334

0.01U_0402_16V7K

KSI7
KSI6
KSI5
KSO0
KSO1
KSO2
KSI4
KSO3
KSO4
KSO5
KSO6
KSO7

+5VS

1

2

C194 100P_0402_25V8K@
C195 100P_0402_25V8K@
C196 100P_0402_25V8K@
C217 100P_0402_25V8K@
C216 100P_0402_25V8K@
C215 100P_0402_25V8K@
C197 100P_0402_25V8K@
C214 100P_0402_25V8K@
C213 100P_0402_25V8K@
C212 100P_0402_25V8K@
C211 100P_0402_25V8K@
C210 100P_0402_25V8K@

TouchPad

TP_DATA26
TP_CLK26

Felica Conn

21

TP58

1A

+5VS_FP_FE

LEC

6

6

5

5

4

4

8

3

3

7

2

2

1

1

JFE1
JST_06FHJ-SM1-GB-TB(LF)(SN)~N

CONN@

ONOFF

SW1

ON

1
2
3
4
5
6 7

FHDS-06-T-V-T/R_12P

12
11
10
9
8

8
7

+5VS_FP_FE

1

C343
10U_0805_10V4Z~N

2

+5VS

F1 1.1A_6VDC_FUSE

R461 0_0402_5%

USB20P4-16

KSI[0..7]
KSO[0..15]

TP_DATA
TP_CLK

1

1

@

@

C339

C335100P_0402_25V8K

2

2

100P_0402_25V8K

GPLED26

+5VS_DIMMER

KSI[0..7] 26
KSO[0..15] 26

GPLED

JTP1

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

GND

10

GND

ACES_85201-0805N

CONN@

USB20P4+16

1 2

R462 0_0402_5%

1 2

USBP4_R­USBP4_R+

CLR_CMOS15
SW_CONFIG126
SW_CONFIG226

TP24

SW_RSV126
SW_RSV226

+1.5V_CARD

+3V_CARD_AUX

+3V_CARD +1.5V_CARD

JP2

1
USB20P6-16
USB20P6+16

SMB_CK_CLK18,9,13,16
SMB_CK_DAT18,9,13,16

PCIE_WAKE#16,20,22,26

CLKREQB#13

NC_PWR_EN#16

CLK_PCIE_CARD#13

CLK_PCIE_CARD13

PCIE_CARD_C_RX_N111
PCIE_CARD_C_RX_P111

PCIE_CARD_C_TX_N111
PCIE_CARD_C_TX_P111

NC_PWR_EN#

PCIE_CARD_C_RX_N1
PCIE_CARD_C_RX_P1

PCIE_CARD_C_TX_N1
PCIE_CARD_C_TX_P1

R114 0_0402_5%
R115 0_0402_5%

NC_CPUSB#

R121 0_0402_5%
R122 0_0402_5%

R133 0_0402_5%

PCIE_PERST#

R143 0_0402_5%
R510 0_0402_5%

1 2

1 2
1 2

12
12

12
12

USB20P6-_R
USB20P6+_R

NC_CPPE#

GND

2

USB_D-

3

USB_D+

4

CPUSB#

5

RSV

6

RSV

7

SMB_CLK

8

SMB_DATA

9

+1.5V

10

+1.5V

11

WAKE#

12

+3.3VAUX

13

PERST#

14

+3.3V

15

+3.3V

16

CLKREQ#

17

CPPE#

18

REFCLK-

19

REFCLK+

20

GND

21

PERn0

22

PERp0

23

GND

24

PETn0

25

PETp0

26

GND

27

GND

28

GND

29

GND
GND30GND

FOX_1CX41202-KH_26P

CONN@

GND

+3VALW

31
32

C2970.1U_0402_16V7K~N

NB_RST#11,15,19,22,25,26

SYSON26,30
SUSP#26,30

R134 100K_0402_5%@

1 2

R135 100K_0402_5%@

1 2

+3VALW

1

1

C2830.1U_0402_16V7K~N

2

2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

NB_RST#

NC_PWR_EN#
NC_CPUSB#

+1.5VS+3VS

1

C2790.1U_0402_16V7K~N

2

U7

12

1.5Vin

14

1.5Vin

2

3.3Vin

4

3.3Vin
AUX_IN17AUX_OUT

6

SYSRST#

20

SHDN#

1

STBY#

10

CPPE#

9

CPUSB#

18

RCLKEN

P2231NF_QFN20

2007/1/25 2008/01/25

11

1.5Vout

13

1.5Vout

3

3.3Vout

5

3.3Vout

15
19

OC#

8

PERST#

16

NC

7

GND

Compal Secret Data

1A 1.5A

1

1

C2780.1U_0402_16V7K~N

C2670.1U_0402_16V7K~N

2

2

PCIE_PERST#

Deciphered Date

+3V_CARD

1

1

C2810.1U_0402_16V7K~N

C2820.1U_0402_16V7K~N

2

2

1

C268

2

10U_0805_6.3V6M

+3V_CARD_AUX

1

C26610U_0805_6.3V6M

2

0.5A

1

1

C2960.1U_0402_16V7K~N

C2800.1U_0402_16V7K~N

2

2

Title

Size Document Number Rev

Custom

Date: Sheet

MDA/BT/KBD/TP Conn
LA-3611P

27 40Wednesday, April 11, 2007

0.4

of

A

iPOD Charge when system shutdown

+5VALW

U12

1

GND

2

1

1 1

USB_EN26

USB_EN

2

G

+5VALW

0.1U_0402_16V7K~N

2

R194
10K_0402_5%

1 2

USB_EN#

13

D

Q2
SSM3K7002FU_SC70-3

S

C350

3
4

USB_EN Hi=Enable, Low=Disable IPOD USB power

BIOS
MENU

S0

S3 S4 S5

ON

ON

ON

ON

AC

OFF

ON

OFF

2 2

DC

ON
OFF

ON

OFF OFF OFF

ON

OFF

ON

OFF

OFF

OFF OFF

OUT

IN

OUT
OUT

IN

OC#

EN#

G548B2P8U_MSOP8

B

+USB_AS

W=40mils

8
7
6
5

OVCUR#0 16

SSM3K7002FU_SC70-3

12

R4
470_0805_5%

13

D

Q1

USB_EN#

2

G

S

USB20P0-16
USB20P0+16

C

+USB_AS

+5VS

+3VS

USB20P0- USBP0-_SW
USB20P0+

U1

8

6
7

FSUSB31K8X_SSOP8~N

VCC
HSD-2D­HSD+

GND

OE#

1 2

NC

D+

R15

100K_0402_5%

1
3
5
4

J4

1 2

SHORT PADS

Q9
AP2301GN 1P SOT23

S

G

2

43K_0402_1%

USBP0+_SW

51K_0402_1%

SUSP

SSM3K7002FU_SC70-3

D

D

13

R10

R12

2

G

Q8

R11
75K_0402_1%

1 2

1 2

1 2

13

D

S

R13
51K_0402_1%

1 2

J5
SHORT PADS

1 2

3

2

L1

3

2

WCM-2012-670T_4P

4

4

1

1

4

CH4
CH11Vn2CH2

5

6

D2

Vp

NUP4301MR6T1_TSOP6

CH3

3

CON-USBP0­CON-USBP0+

E

+USB_AS

JUSB1

1

VCC

2

D-

3

D+

4

GND

5

GND1

6

GND2

7

GND3

8

GND4

SUYIN_020173MR004G533ZR

CONN@

OUT
OUT
OUT
OC#

OUT
OUT
OUT
OC#

8
7
6
5

8
7
6
5

+USB_BS

+USB_CS

W=40mils

W=40mils

B

OVCUR#1 16

SSM3K7002FU_SC70-3

OVCUR#3 16

SSM3K7002FU_SC70-3

12

R217
470_0805_5%

13

D

S

12

R463
470_0805_5%

13

D

S

SUSP

2

G

C349

150U_D2_6.3VM

SUSP

2

G

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

1

+

2

470P_0402_50V7K

C

+USB_AS

1

C9

2

470P_0402_50V7K

1

C8

2

2007/1/25 2008/01/25

Compal Secret Data

Deciphered Date

Q39

Q56

USB20P1-16
USB20P1+16

USB20P2-16
USB20P2+16

USB20P3-16
USB20P3+16

R464 0_0402_5%

LID_SW#26

D

+3VALW

1 2

+USB_BS

USB20P1­USB20P1+

USB20P2­USB20P2+

+USB_CS

USB20P3­USB20P3+

Compal Electronics, Inc.

Title

Size Document Number Rev

Wednesday, April 11, 2007

Date: Sheet

JUSB2

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

11

11

13

12

12

14

ACES_87213-1200G

CONN@

JUSB3

1

1

2

2

3

3

4

4

5

5

6

6

7

7

9

8

8

10

ACES_87213-0800G

CONN@

USB Port

LA-3611P

13
14

9
10

of

E

28 40

0.4

+5VS

U18

1

GND

2

IN

12

R215
100K_0402_5%

@

12

R466
100K_0402_5%

@

3

IN

4

EN#

G548B2P8U_MSOP8

U33

1

GND

2

IN

3

IN

4

EN#

G548B2P8U_MSOP8

1

C384

0.1U_0402_16V7K~N

SUSP30,35

SUSP30,35

2

+5VS

1

C603

0.1U_0402_16V7K~N

2

A

1 2

R216
0_0402_5%

1 2

R468
0_0402_5%

3 3

4 4

A

H6

H1
HOLEA@

1

H8
HOLEA@

1 1

2 2

3 3

1

H16
HOLEA@

1

H15
HOLEA@

1

H19
HOLEA@

1

H23
HOLEA@

1

H24
HOLEA@

1

H2
HOLEA@

1

H9
HOLEA@

1

H17
HOLEA@

1

H20
HOLEA@

1

H3
HOLEA@

1

H10
HOLEA@

1

H21
HOLEA@

1

H_S362D118

H_C114D114N

H4
HOLEA@

1

H11
HOLEA@

1

H_C216D144

H_C236D157

H22
HOLEA@

1

H5

HOLEA@

HOLEA@

1

1

H12

H13

HOLEA@

HOLEA@

1

1

H_C276D165 (CPU)

H7
HOLEA@

1

H14
HOLEA@

1

H_S354D118

EC_ON26

B

Power Button

PWR_ON-OFF_BTN#

+3VALW

1 2

EC_ON

SATA_LED#17

ODD_ACT_LED#19

CARD_LED20

CF8
SMD40M80

@

1

CF1
SMD40M80

@

1

FD3
FIDUCAL

@

1

1

DAN202U_SC70

R132

4.7K_0402_5%

1 2

R131
33K_0402_5%

DTC124EKAT146 NPN SOT23

SATA_LED#
ODD_ACT_LED#

CF10
SMD40M80

@

1

CF2
SMD40M80

@

1

FD2
FIDUCAL

@

1

2

Q20

@

@

@

+3VALW

1 2

D6

2
3

13

+5VS

5

2

B

1

A

3

+5VS

1 2
13

D

2

G

S

CF5

CF11

SMD40M80

SMD40M80

@

1

1

CF9

CF7

SMD40M80

SMD40M80

@

1

1

FD1

FD4

FIDUCAL

FIDUCAL

@

1

1

R142
100K_0402_5%

51ON#

2

C276
1000P_0402_50V7K~N

1

2

C383

0.1U_0402_16V7K~N

1

U17

P

IDE_ACT_LED#

4

Y

G

NC7SZ08P5X_NL_SC70-5

R214
10K_0402_5%

CARD_LED#

Q37
SSM3K7002FU_SC70-3

CF6
SMD40M80

@

1

FD5
FIDUCAL

@

1

ON_OFF 26
51ON# 31

2

G

C

CF4
SMD40M80

@

1

CF12
SMD40M80

@

1

FD6
FIDUCAL

@

1

12

D5
RLZ20A_LL34

CARD_LED_5V

13

D

Q60
SSM3K7002FU_SC70-3

S

CF3
SMD40M80

@

CF13
SMD40M80

@

CF15
SMD40M80

@

DIMMER_STATUS26

D

1

1

1

+5VS_DIMMER

PWR_ON-OFF_BTN#

2

C618

1

0.1U_0402_16V7K~N

E-Mail_BTN
Internet_BTN
ECO_BTN
DIMMER_BTN
SOFT_BTN
ECO_GREEN_LED#
ECO_BLUE_LED#

+5VS_DIMMER

LIGHT_SENSOR

E-Mail_BTN
Internet_BTN
SCRLED#
NUMLED#
CAPSLED#
CARD_LED#
IDE_ACT_LED#
PWR_ON-OFF_BTN#

+3VS

SCRLED#
NUMLED#
CAPSLED#
CARD_LED_5V
IDE_ACT_LED#

E-Mail_BTN26
Internet_BTN26
ECO_BTN26
DIMMER_BTN26
SOFT_BTN26

ECO_GREEN_LED#26
ECO_BLUE_LED#26

+5VS +5VS_DIMMER

1 2

DIMMER_STATUS

@

1 2

Q22
AP2301GN 1P SOT23

S

G

R149

10K_0402_5%

2

G

R148
100K_0402_5%

ECO_BTN
DIMMER_BTN
SOFT_BTN
ECO_GREEN_LED#
ECO_BLUE_LED#
LIGHT_SENSOR

D

13

2

2

1

1000P_0402_50V7K~N

13

D

Q21
SSM3K7002FU_SC70-3

S

C302 100P_0402_25V8K@

C304 100P_0402_25V8K@
C309 100P_0402_25V8K@
C310 100P_0402_25V8K@
C40 100P_0402_25V8K@

C617

LIGHT_SENSOR26

SCRLED#26
NUMLED#26
CAPSLED#26

E

JFN1

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

11

11

12

12

13

13

14

14

15

15

16

16

ACES_85201-16051

CONN@

JLED1

14

14

G2

13

13

G1

12

12

11

11

10

10

9

9

8

8

7

7

6

6

5

5

4

4

3

3

2

2

1

1

ACES_85202-1405L

CONN@

C292 100P_0402_25V8K@
C293 100P_0402_25V8K@C303 100P_0402_25V8K@
C42 100P_0402_25V8K@
C43 100P_0402_25V8K@
C44 100P_0402_25V8K@
C45 100P_0402_25V8K@
C46 100P_0402_25V8K@
C291 100P_0402_25V8K@

17

G17

18

G18

16
15

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2007/1/25 2008/01/25

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

D

Date: Sheet

PWR_OK/BTN
LA-3611P

E

0.4

of

29 40Wednesday, April 11, 2007

A

+5VALW TO +5V

+5V

1

C338
1U_0603_10V6K

2

@

45

SUSON

1

@

C337

4.7U_0805_10V4Z~N

2

+5VALW

Q33

@

D

6

S

1 1

2
1

G

1

C342
10U_0805_10V4Z~N

2

@

SI3456BDV-T1-E3_TSOP6

3

B

C

D

E

+1.2VALW TO +1.2V_NBCORE

+5VALW

1

2

8
7
6
5

+5VS

U11

1

S

D

2

S

D

3

S

D

4

G

D

AO4468 1N SO8

C336
10U_0805_10V4Z~N

+5VALW TO +5VS

1

C340

4.7U_0805_10V4Z~N

2

RUN_ON

SSM3K7002FU_SC70-3

1

C341
1U_0603_10V6K

2

Q32

100K_0603_5%

1 2

13

D

S

R188

G

B+_BIAS

SUSP

2

+1.2VALW +1.2V_NBCORE

U36

8
7
6
5

1

2

1.2VS_GATE

1

S

D

2

S

D

3

S

D

4

G

D

AO4468 1N SO8

C606
10U_0805_10V4Z~N

R508

1 2

0_0402_5%

NB_GATE

1

@

2

1

C604

4.7U_0805_10V4Z~N

2

R507

@

1 2

10K_0402_5%

C607

0.22U_0603_10V7K

1

C605
1U_0603_10V6K

2

RUN_ON_1.2

+3VALW TO +3V

+3V

45

SUSP

12

1

C591

4.7U_0805_10V4Z~N

2

R448

1 2

0_0402_5%

1

C601

0.22U_0603_10V7K

2

SSM3K7002FU_SC70-3

+5VALW

2

G

+3VALW

Q51

D

6

S

2
1

SI3456BDV-T1-E3_TSOP6

G

3

2 2

3 3

3V_GATE SUSON

1

C592
10U_0805_10V4Z~N

2

SUSP28,35 SYSON#6,35

SSM3K7002FU_SC70-3

R182

10K_0402_5%

12

R32
470_0805_5%

R189
10K_0402_5%

1 2

Q30

13

D

S

+1.2V_HT

12

R36
470_0805_5%

1

C590
1U_0603_10V6K

2

Q29

SYSON26,27SUSP#26,27

R187

1 2

100K_0603_5%

13

D

2

G

S

SSM3K7002FU_SC70-3

SYSON

R185

10K_0402_5%

SYSON#

12

B+_BIAS

SYSON#

2

G

+5VALW

+1.8V

R186
10K_0402_5%

1 2

Q31

13

D

S

12

R33
470_0805_5%

+1.8VS

+3VALW

8
7
6
5

1

2

+1.8V

8
7
6
5

1

2

0.22U_0603_10V7K

12

R72
470_0805_5%

AO4468 1N SO8

C325
10U_0805_10V4Z~N

AO4468 1N SO8

C480
10U_0805_10V4Z~N

+3VALW TO +3VS

U9

1

S

D

2

S

D

3

S

D
D

3VS_GATE

4

G

+1.8V TO +1.8VS

U24

1

S

D

2

S

D

3

S

D

4

G

D

C468

1.8VS_GATE

1

@

2

1

C321

4.7U_0805_10V4Z~N

2

1

2

1

C475

4.7U_0805_6.3V6K~N

2

@

1 2

1 2

+3V+0.9V

12

R175
470_0805_5%

+3VS

R174

1 2

0_0402_5%

C320

0.22U_0603_10V7K

+1.8VS

R64

0_0402_5%

R65
10K_0402_5%

1

C324
1U_0603_10V6K

2

RUN_ON

1

C174
1U_0603_10V6K

2

RUN_ON

+5VS

12

R179
470_0805_5%

+5V

12

R176
470_0805_5%

+1.2VALW TO +1.2V_HT

+1.2V_HT+1.2VALW

U22

8
7
6
5

1

2

+5VS+3VS

12

R37
470_0805_5%

1

S

D

2

S

D

3

S

D

4

G

D

AO4468 1N SO8

C454
10U_0805_10V4Z~N

0.22U_0603_10V7K

1.2VS_GATE

C455

+1.5VS

1

C138

4.7U_0805_10V4Z~N

2

R61

1 2

10K_0402_5%

1

2

12

R181
470_0805_5%

1

C144
1U_0603_10V6K

2

RUN_ON_1.2

D

Q15

S

VLDT_EN26

R60

100K_0603_5%

1 2

13

VLDT_EN#

2

G

SSM3K7002FU_SC70-3

VLDT_EN

10K_0402_5%

+5VALW

R53

2

G

10K_0402_5%

1 2

13

D

Q14

SSM3K7002FU_SC70-3

S

B+_BIAS

12

R52

DISCHG_0.9V

13

SYSON#

4 4

D

2

G

S

SSM3K7002FU_SC70-3

Q10

A

SUSP

2

G

SSM3K7002FU_SC70-3

DISCHG_1.2VHT

13

D

Q12

S

SYSON#

DISCHG_1.8V

13

D

Q11

2

G

S

SSM3K7002FU_SC70-3

B

DISCHG_1.8VS

13

D

SUSP

2

G

S

SSM3K7002FU_SC70-3

DISCHG_3V

13

SYSON#

Q16

D

Q24

2

G

S

SSM3K7002FU_SC70-3

DISCHG_3VS

13

D

2

G

S

SSM3K7002FU_SC70-3

Security Classification

SYSON#

Q27

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

DISCHG_5V

13

D

Q25

2

G

S

SSM3K7002FU_SC70-3

2007/1/25 2008/01/25

Compal Secret Data

DISCHG_5VS

13

D

SUSPSUSP

2

G

S

SSM3K7002FU_SC70-3

Deciphered Date

DISCHG_1.5VS

13

D

SUSP

Q13

SSM3K7002FU_SC70-3

D

Q28

2

G

S

Title

Size Document Number Rev

Custom

Date: Sheet

DC Interface
LA-3611P

E

0.4

of

30 40Wednesday, April 11, 2007

5

4

3

2

1

ADPIN

PL2

PC14

2

100P_0402_50V8J~N

12

12

+1.2VALWP

MCK4532800YAF_1812

12

PC15

1000P_0402_50V7K~N

VIN

13

PR109
200_0805_5%~N

PC72
1U_0805_25V4Z~N

+1.5VSP

+0.9VP

1 2

VIN

PD11
RLS4148_LLDS2

1 2
12

PR143
33_1206_5%~N

12

PC114

0.1U_0603_25V7K~N

PJP4
JUMP_43X118@

PJP1
JUMP_43X118@

PJP10
JUMP_43X118@

PJP9
JUMP_43X118@

12

PC30

100P_0402_50V8J~N

PD1

12

RLS4148_LLDS2

VS

2

112

2

112

2

112

2

112

4

PF2

10A_65VDC_451010

12

PC135

12

0.22U_1206_25V7K

G920AT24U_SOT89

3

OUT

2

2

2

2

2

21

1000P_0402_50V7K~N

JUMP_43X118

12

PC113

PU9

GND

PJP6

@

112

PQ45
TP0610K-T1-E3_SOT23-3

2

IN

1

+5VALW

+3VALW

+1.8V

12

2

PCN1

D D

C C

B B

A A

SINGA_2WA-8291T041

CHGRTC

1 2

560_0603_5%~N

1

2

3

4

BATT+

51ON#29

3.3V

PR113

+5VALWP

+3VALWP

+1.8VP

1

2

3

4

CH751H-40PT_SOD323-2

1 2

560_0603_5%~N

PR112

12

PD12

2 1

CHGRTCP

PR152

100K_0402_5%~N

PR153

22K_0402_5%

1 2

RTCVREF

12

PC74

PJP12
JUMP_43X118@

PJP13
JUMP_43X118@

PJP11
JUMP_43X118@

PJP8
JUMP_43X118@

PJP7
JUMP_43X118@

5

PC134

100P_0402_50V8J~N

4.7U_0805_6.3V6K~N

112

112

112

112

112

VIN

Max. typ. Min.

H-->L 18.234 17.841 17.449
L-->H 17.597 17.210 16.813

PC37

2200P_0402_50V7K~N

@

12

PC31

ACOFF26,32

1000P_0402_50V7K~N

PR59

1K_1206_5%~N

1 2

PR55

1K_1206_5%~N

1 2

PR51

1K_1206_5%~N

1 2

PR43

1K_1206_5%~N

1 2

VIN

12

PR71

82.5K_0402_1%~N
PR72

PR75

19.6K_0402_1%~N

22K_0402_1%~N

1 2

12

12

VL

12

PR68

1

12

RTCVREF

PC34
1000P_0402_50V7K~N

PC38

0.1U_0603_25V7K~N

PQ3

12

PR18

470K_0402_5%~N

470K_0402_5%~N

PQ7
DTC115EUA_SC70-3

TP0610K-T1-E3_SOT23-3

2

12

PR17
470K_0402_5%

13

PQ6

2

DTC115EUA_SC70-3

PC40

0.1U_0402_16V7K~N

12

32.3

100K_0402_1%~N

PD2

2
3

RB715F_SOT323-3

B+

13

MAINPWON33,37

ACON32

12

PR24

13

2

ACIN

1 2

N40N41
N35

7

0

Precharge detector
Min. typ. Max.

H-->L 14.589V 14.84V 15.243V

+1.5VS

L-->H 15.562V 15.97V 16.388V

56K_0402_5%~N@

1 2

PR70
1M_0402_1%~N

1 2

VS

8

3

P

+

2

-

G

4

PR65

10K_0402_5%~N

12

PR73

2.2M_0402_5%~N

VS

8

PU4B

5

P

+

6

-

G

LM393DR_SO8~N

4

PR76

34K_0402_1%~N

12

PR69

12

PC35

PU4A

0.01U_0402_25V7K~N

1

0

LM393DR_SO8~N

RTCVREF

3.3V

12

12

PC41

1000P_0402_50V7K~N

12

VIN

12

12

12

PRG++

13

D

S

PR77

66.5K_0402_1%~N

@

PR67
10K_0402_5%~N

PD17

MMPZ5229BPT_SC76

PR79
191K_0402_1%~N

SSM3K7002FU_SC70-3

G

PQ20

2

1 2

12

499K_0402_1%~N

13

PR63
1K_0402_5%~N

PACIN

PR64
10K_0402_5%~N

B+

12

12

PR74

PR80
47K_0402_5%~N

PQ19
DTC115EUA_SC70-3

2

ACIN 26

PACIN 32

PR78
499K_0402_1%~N

12

PC39

12

0.01U_0402_25V7K~N

PACIN 32

+5VALWP

BATT ONLY

+0.9V

Precharge detector
Min. typ. Max.

+1.2VALW

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

H-->L 6.138V 6.214V 6.359V
L-->H 7.196V 7.349V 7.505V

2007/1/25 2008/01/25

3

Compal Secret Data

Deciphered Date

Title

DCIN / Precharge

Size Document Number Rev

Custom

LA-3611P

2

Date: Sheet

1

31 40Wednesday, April 11, 2007

0.4

of

Vin Detector

A

P2

12

PR196
200K_0402_1%~N

12

PC140

0.1U_0603_25V7K~N

12

PQ63

13

D

G

S

28.2

SSM3K7002FU_SC70-3

FDS4435BZ_SO8

1

S

2

S

3

S

4

G

PQ52

FSTCHG26

0.01U_0402_25V7K~N

IREF26

8

D

7

D

6

D

5

D

VIN

6251VDD

PR212

1 2

143K_0402_1%~N

100K_0402_1%~N

PQ51

8

VIN

1 1

12

PR195
47K_0402_1%~N

2

13

D

2

G

2 2

S

PACIN31

ACON31

7
6
5

PQ56

2

13

PQ60
SSM3K7002FU_SC70-3

28.2

PACIN

1

S

D

2

S

D

3

S

D

4

G

D

FDS4435BZ_SO8

28.2

DTA144EUA_SC70-3

1 3

PQ58
DTC115EUA_SC70-3

28.2

150K_0402_1%~N

PD21

ACOFF#

1 2

1SS355_SOD323-2

28.2

1 2

PR211

3K_0402_1%~N

ACON

PR205

2

IREF=0.972*Icharge
IREF=0.6V~3.21V

ACLM=(1/0.02)(0.05*Vaclm/2.39+0.05)
where ACLM=1.05V, Iaclm=3.66A

B

P3 B+

1

PR239

200K_0402_1%~N

1 2

PR240

150K_0402_1%~N

10K_0402_1%

PC147

1 2

ADP_I26

12

PR215

2

G

1 2

PR200

1 2

100P_0402_50V8J~N

6251VREF

6251VREF

2

0.02_2512_1%

1 2

13

D

PQ72
SSM3K7002FU_SC70-3

PD24

S

CH751H-40PT_SOD323-2

PR198

47K_0402_1%~N

PC144

680P_0402_50V7K@

CSON

1 2

1 2

PC145 6800P_0402_25V7K~N

PR206
10K_0402_1%~N

1 2

PC148

PC149

1 2

0.1U_0402_16V7K~N

12.7K_0402_1%
PR213

1 2

PR216

11K_0402_1%

1 2

PR217

28.7K_0402_1% @

PR193

12

Iadp=0~3.95A(75W)

4
3

6251VDD

21
12

12

PC173

1 2

12

12

PR218

PR208

47K_0402_1%~N@

0_0402_5%~N@

PC141

2.2U_0603_6.3V6K~N

0.1U_0402_16V7K~N

PR207

1 2

100_0402_1%~N

6251VREF

1

2

3

4

5

6

7

8

9

10

11

12

PJP14

2

JUMP_43X118@

PQ55

TP0610K-T1-E3_SOT23-3

PU13

VDD

ACSET

EN

CELLS

ICOMP

VCOMP

ICM

VREF

CHLIM

ACLIM

VADJ

GND

ISL6251AHAZ-T_QSOP24

DCIN

ACPRN

CSON

CSOP

CSIN

CSIP

PHASE

UGATE

BOOT

VDDP

LGATE

PGND

24

23

22

21

20

19

18

17

16

15

14

13

112

VIN

28.2
2

C

BST_CHG

2.2_0603_5%~N

1 3

PC142

0.1U_0603_25V7K~N

1 2

1 2

20_0603_1%

PC143

0.047U_0603_16V7K~N

1 2

1 2

PR202

20_0603_1%

PR204 20_0603_1%

PC146

0.1U_0603_25V7K~N

1 2

LX_CHG

DH_CHG

PR210

1 2

6251VDDP

PC153

1 2

4.7U_0805_6.3V6K~N

Fosc=14100/Rt=14100/47=300KHz

CSIP

CSIN

12

4.7U_1206_25V6K~N

PJP15
PAD-OPEN1x1m

PR231

12

PR235

1 2

2.2_0603_5%

BST_CHGA

PD22

CH751H-40PT_SOD323-2

1 2

2 1

4.7_0603_5%
PR214

DL_CHG

PC137

CSON

CSOP

PC150

12

0.1U_0402_16V7K~N

6251VDD

12

12

PC138

4.7U_1206_25V6K~N

PC139

D

B++

12

4.7U_1206_25V6K~N

578

PQ61
SI4800BDY-T1-E3_SO8~N

3 6

241

PL14

16UH_D104C-919AS-160M_3.7A_20%

1 2

578

PQ64
SI4800BDY-T1-E3_SO8~N

3 6

241

C

CHG

2

ACOFF##

3 1

B

E

PR194

1 2

13

30K_0402_5%

PQ54
DTC115EUA_SC70-3

28.2

PR199

1 2

220K_0402_5%~N

12

PR203
47K_0402_5%~N

PQ62

2

PMBT3904_SOT23-3

28.2

1
2

PR209

0.02_2512_1%

PQ53

AO4407_SO8~N

1
2
3 6

4

12

PR197
150K_0402_5%

28.2

PR201

1 2

ACOFF#

100K_0402_5%~N

13

DTC115EUA_SC70-3

4
3

PC151

10U_1206_25V6M~N

PQ59

2

28.2

E

8
7

5

VIN

12

PD18

RLZ22B_LL34-2

PD19

1 2

28.2

12

10U_1206_25V6M~N

1SS355_SOD323-2

28.2

1 2

Charger

26,31

ACOFF

1SS355_SOD323-2

PD20

12

PC152

BATT+

3 3

12

PC32

0.01U_0402_25V7K~N

Compal Secret Data

BATT+

12

PR37
453K_0402_1%

12

PR44

499K_0402_1%

12

PR52

86.6K_0402_1%

Deciphered Date

Title

Size Document Number Rev

B

D

Date: Sheet

Compal Electronics, Inc.

PWR-Charger

LA-3611P

32 40Wednesday, April 11, 2007

E

0.4

of

6251VREF

12

PR241
100K_0402_1%

@

12

12

PR107

1 2

B+

100_0805_5%~N

+5VALW

PR108

470K_0402_5%

1 2

12

PD7

1SS355_SOD323-2

PR111

4 4

1 2

220K_0402_5%

12

PC75

PR110

1 2

0.1U_0603_25V7K~N

220K_0402_5%

A

PQ32

2

G

TP0610K-T1-E3_SOT23-3

13

2

13

D

S

32.8

SSM3K7002FU_SC70-3

PQ29

PC71

B+_BIAS

1 2

0.1U_0603_25V7K~N

B

PC174

CSON

0.01U_0402_25V7K

@

LI-4S :18V----BATT-OVP=1.498V

PR242

6251_EN

1

C

PQ73

2

B

2SC2411K_SOT23-3@

E

3

20K_0402_1%@

7

BATT_OVP26

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

VS

8

PU3B

5

P

+

0

6

-

G

LM358ADT_SO8~N

4

2007/1/25 2008/01/25

5

PL15

PF7

B+

D D

2 1

7A_24VDC_429007.WRML

MCK4532800YAF_1812

1 2

TDC=3.65A
OCP=6A

+3VALWP

PL17

1

12

+

PC166

2

PC165

C C

ripple current
[(19-3.3)*D]/(3.3UH*430K)
=1.92A

FB pin ripple around 14.24mV

3.3V MAX Delta I=1.92A IF ESR=25m ohm
Output ripple= 1.92*25=48mV
48*4.22/(10+4.22)=14.24mV

B B

OCP: 10uA*10.5K/(0.016*1.3)=5.05A

5.05A+1.92A/2=6A

330U_D3L_6.3VM_R25M

1000P_0402_50V7K~N

@

PR223

1 2

PR225

1 2

4.22K_0402_1%~N

3.3UH_SIL1045R-3R3PF_8.2A_30%

10K_0402_1%~N

12

3 6

241

3 6

241

VS

RLZ5.1B_LL34

VL

12

12

PC170

PR233

806K_0603_1%~N

12

PR234

0_0402_5%~N

MAINPWON31,37

0.047U_0603_16V7K~N

4

12

12

PC155

PC154

4.7U_1206_25V6K~N

4.7U_1206_25V6K~N

PQ66

578

SI4800BDY-T1-E3_SO8~N

PC160

0.1U_0402_16V7K~N

PQ68

578

SI4810BDY-T1-E3_SO8~N

PD23

1 2

PR230

1 2

100K_0402_1%

PR232

47K_0402_1%~N

EN3 MAX<6V, EN5 MAX<2XV

12

0.1U_0603_25V7K~N

PC162

12

12

1 2

3

+VCC_TPS51120

PR219

5.1_0603_5%

12

PC158

1U_0603_6.3V6M~N

PU14

22

VIN

20

V5FILT

9

0_0603_5%~N

1 2

DH_3V
LX_3V
DL_3V

FB3 TPS51120_CS2

PC168

PC169

2.2U_0805_25V6K

@

13

PR222

14
15
16
17

12
29

19
10

+3.3V_RTC_LDO

12

10U_0805_6.3V6M~N

EN5
VBST2
DRVH2
LL2
DRVL2
PGND2

8

VO2

6

VFB2
EN2

EN1
VREG3
EN3

32 QFN 5X5

TONSEL

PGOOD1
PGOOD2

SKIPSEL

PAD

32

33

PR228
0_0402_5%~N

1 2

12

21

VREG5

28

VBST1

27

DRVH1

26

LL1

25

DRVL1

24

PGND1

1

VO1

3

VFB1

2

COMP1

7

COMP2

23

CS1

18

CS2

4

VREF2

31
5

GND

30
11

TPS51120RHBR_QFN32_5X5~N

VL

PC159

PR220

0_0603_5%~N

1 2

DH_5V
LX_5V
DL_5V

FB5

TPS51120_CS1

12

10U_0805_6.3V6M~N

PC161

0.1U_0402_16V7K~N

1 2

1 2

PR237 0_0603_5%~N

1 2

PR238 0_0603_5%~N

2

B+++

12

12

PC157

PC156

4.7U_1206_25V6K~N

4.7U_1206_25V6K~N

12

PC167

1000P_0402_50V7K~N

578

578

PR226

15.4K_0402_1%

1 2

PQ65

SI4800BDY-T1-E3_SO8~N

3 6

241

3.3UH_SIL1045R-3R3PF_8.2A_30%

1 2

PL16

PQ67
SI4810BDY-T1-E3_SO8~N

3 6

241

+VCC_TPS51120

PR227

1 2

10.5K_0402_1%

TONSEL= VREF2, CH1/CH2 FREQ= 280K/430K

1

TDC=5.1A
OCP=9.4A

+5VALWP

12

PR221

PC163

10K_0402_1%~N

1 2

1000P_0402_50V7K~N

@

PR224

1 2

2.49K_0402_1%~N

PR229

0_0402_5%~N

1 2

ripple current
[(19-5)*D]/(3.3UH*280K)
=3.99A

FB pin ripple around 12mV
5V MAX Delta I=3.99A IF ESR=15m ohm
Output ripple= 3.99*15=59.85mV

59.85*2.49/(10+2.49)=11.93mV

OCP: 10uA*15.4K/(0.016*1.3)=7.4A

7.4A+3.99A/2=9.4A

1

+

2

PC164

330U_D3L_6.3VM_R25M

A A

Because EN1 and EN2 have 2uA sorce current,
the RC time will be change.

5

4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2007/1/25 2008/01/25

3

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

+3VALWP, +5VALWP

Size Document Number Rev

Date: Sheet

LA-3611P

Wednesday, April 11, 2007

1

of

33 40

0.4Custom

5

4

3

2

1

D D

12

PC64

4.7U_1206_25V6K~N

1

PD4

2

3

BST_1.2V-2

1 2

12

PR99

PC59

0_0603_5%~N

0.1U_0402_16V7K~N

LX_1.2V

PR101

1.65K_0402_1%~N

1 2

VSE_1.2V

PC62

12

0.1U_0402_16V7K~N

12

PC67

@

4.7U_1206_25V6K~N

12

PC58

PC128

12

0.01U_0402_25V7K~N

BST_1.2V-1

ISE_1.2V
DL_1.2V

12

PR171
121K_0402_1%~N

PR106

+5VALWP

1 2

10_0805_5%~N

12

PC66

2.2U_0603_6.3V6K~N

0.1U_0603_25V7K~N

14

PU8

12

SOFT1

6

BOOT1

5

UGATE1

4

PHASE1

7

ISEN1

2

LGATE1

3

PGND1

9

VOUT1

10

VSEN1

8

EN1

15

PG1

11

OCSET1

1

PR162

1 2

2.2_0603_5%~N

28

VIN

GND

SOFT2

VCC

BOOT2

UGATE2
PHASE2

ISEN2

LGATE2

PGND2

VOUT2
VSEN2

EN2

PG2/REF

OCSET2

DDR

ISL6227CAZ-T_SSOP28~N

13

12

PC61

0.1U_0603_25V7K~N

578

1 2

12

PR164
0_0402_5%~N

12

PR169

PQ28

PL13

PQ26

AO4704_SO8~N

+3VALWP

0_0402_5%~N @

SI4800BDY-T1-E3_SO8~N

TDC=7A
OCP=10A

+1.2VALWP

1

C C

+

2

PC125

220U_D2_4VY_R15M

PR165

3.74K_0402_1%

12

12

12

PR168

10K_0402_1%~N

1.8UH_SIL104R-1R8PF_9.5A_30%

PC123

0.01U_0402_25V7K~N

3 6

241

D/K8D/K7D/K6D/K

S/A1S/A3G

S/A

2

1 2

5

4

47K_0402_1%~N

CHP202UPT_SOT323-3

VOUT_1.2V

PR103

12

PC121

BST_1.8V-2

PC127

17

12

0.01U_0402_25V7K~N

BST_1.8V-1

23

1 2

PR100

0_0603_5%~N

DH_1.8VDH_1.2V

24

LX_1.8V

25

ISE_1.8V

22

DL_1.8V

27

26

VOUT_1.8V

20

VSE_1.8V

19
21
16

18

12

PR170
121K_0402_1%~N

B++++

12

PC65

@

2.2U_0603_6.3V6K~N

0.1U_0402_16V7K~N

PR102

1.4K_0402_1%

1 2

12

4.7U_1206_25V6K~N

12

PC60

0.1U_0402_16V7K~N

FBMA-L11-322513-151LMA50T_1210

PC63

4.7U_1206_25V6K~N

578

3 6

241

12

5

S/A

4

2

1 2

PR172 10K_0402_5%~N

PC126

PL6

12

12

PC68

0.1U_0603_25V7K~N

PQ27
SI4800BDY-T1-E3_SO8~N

PL12

1.8UH_SIL104R-1R8PF_9.5A_30%

1 2

PQ25
AO4704_SO8~N

D/K8D/K7D/K6D/K

S/A1S/A3G

PR104

0_0402_5%~N

+3V

PR105

0_0402_5%~N @

PF5

2 1

7A_24VDC_429007.WRML

12

12

PC122

0.01U_0402_25V7K~N

12

12

0.9V0.9V

12

B+

PR163

10.2K_0402_1%

PR166

10K_0402_1%

TDC=6A
OCP=9.1A

+1.8VP

1

+

2

PC124

220U_D2_4VY_R15M

B B

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2007/1/25 2008/01/25

Compal Secret Data

Deciphered Date

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

+1.2VALWP & +1.8VP

LA-3611P

Wednesday, April 11, 2007

1

34 40

0.4

of

5

4

3

2

1

+1.5VSP/+0.9VSP

+1.8V

D D

4.7U_0805_6.3V6K~N

PR88

0_0402_5%~N

SYSON#6,30

C C

1 2

0.1U_0402_16V7K~N @

PC49

PC54

1

PJP2

1

JUMP_43X118@

2

2

1.8V_0.9V

12

13

D

2

G

S

12

PR94

1K_0402_1%~N

PQ22

PR95

1K_0402_1%~N

SSM3K7002FU_SC70-3

12

12

12

PC50

0.1U_0402_16V7K~N

PU6

VIN1VCNTL

2

GND

3

VREF

4

VOUT

G2992F1U_SO8~N

+0.9VP

12

PC48

4.7U_0805_6.3V6K~N

6
5

NC

7

NC

8

NC

9

TP

+3VALWP

12

PC47
1U_0603_6.3V6M~N

4.7U_0805_6.3V6K~N

PR132

0_0402_5%~N

SUSP28,30

1 2

0.1U_0402_16V7K~N @

PC88

PC91

+1.8V

1

PJP3

1

JUMP_43X118@

2

2

1.8V_1.5V

12

13

D

2

G

S

12

PR133

200_0402_1%~N

PQ37

PR131

1K_0402_1%~N

SSM3K7002FU_SC70-3

12

12

12

PC89

0.1U_0402_16V7K~N

PU11

VIN1VCNTL

2

GND

3

VREF

4

VOUT

G2992F1U_SO8~N

+1.5VSP

12

PC90

4.7U_0805_6.3V6K~N

6
5

NC

7

NC

8

NC

9

TP

+3VALWP

12

PC92
1U_0603_6.3V6M~N

B B

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2007/1/25 2008/01/25

Compal Secret Data

Deciphered Date

Title

+1.5VSP/+0.9VP

Size Document Number Rev

Custom

LA-3611P

2

Date: Sheet

1

35 40Wednesday, April 11, 2007

0.4

of

5

4

3

2

1

B+

1

+

PC172

2

680P_0402_50V7K

+CPU_CORE

12

PR3

10_0402_5%~N

12

0_0402_5%~N
PR1

36 40Wednesday, April 11, 2007

of

PC93

100U_25V_M

0.4

3 5

241

5

PQ16

4

PR34 0_0402_5%

1 2

3 5

5

PQ18

4

SI4856DY-T1-E3_SO8

PR29

1 2

0_0402_5%~N

CPU_B+

PQ42
SI7686DP-T1-E3_SO8

5

D8D7D6D

PQ11

S1S2S3G

4

SI4856DY-T1-E3_SO8

PQ44

SI7686DP-T1-E3_SO8

241

5

D8D7D6D

PQ17

S1S2S3G

4

12

12

PC109

4.7U_1206_25V6K~N

D8D7D6D

@

S1S2S3G

SI4856DY-T1-E3_SO8

@

D8D7D6D

S1S2S3G

SI4856DY-T1-E3_SO8

2

12

12

PC112

PC111

PC105

4.7U_1206_25V6K~N

PR62

1 2

4.7_1206_5%~N

12

PC33

680P_0603_50V8J

CPU_B+

12

PC9

PR66

@

PC36

@

0.01U_0402_25V7K~N

2200P_0402_50V7K~N

0.36UH_PCMC104T-R36MN1R17_30A_20%

1 2

12

PR57

2 1

PD15

2200P_0402_50V7K~N

4.7_1206_5%~N

1 2

12

680P_0603_50V8J

SKS30-04AT-G_TSMA2

12

12

PC100

4.7U_1206_25V6K~N

4.22K_0402_1%~N

1 2

PC101

4.7U_1206_25V6K~N

PD14

PL7

MCK4532800YAF_1812

1 2

PL10

10KB_0603_ERTJ1VR103J

PR61

2.1K_0402_1%~N

1 2

1 2

PC29

0.22U_0603_16V7K~N

PH3

PF6

2 1

8A_125V_451008MRL

12

12

PC103

0.01U_0402_25V7K~N

PL9

0.36UH_PCMC104T-R36MN1R17_30A_20%

1 2

PR56

4.22K_0402_1%~N

1 2

SKS30-04AT-G_TSMA2

PR60

2.1K_0402_1%~N

1 2

PC28

0.22U_0603_16V7K~N

1 2

CSP2

LA-3611P

2 1

Title

Size Document Number Rev

Custom

Date: Sheet

PH2
10KB_0603_ERTJ1VR103J

1 2

+CPU_CORE

CPU_VDD_FB_H6

1

+5VS

+3VS

12

D D

VID06
VID16
VID26
VID36
VID46
VID56

VGATE

+3VS

C C

VR_ON26

PR28

0_0402_5%~N

1 2

1 2

EC_ADC

1 2

PC1

0.1U_0402_16V7K~N

REF

1 2

PR13

31.6K_0402_1%~N

169K_0603_1%~N

B B

CPU_PSI#6

PR14

PQ38

2

G

2

2

CPU_B+

12

13

200K_0402_1%~N

13

1

3

PR40 0_0402_5%~N
PR39 0_0402_5%~N

PR36 0_0402_5%~N
PR35 0_0402_5%~N
PR31 0_0402_5%~N

PR30 0_0402_5%~N

1 2

PR8 0_0402_5%~N@

1 2

PR42 100K_0402_1%~N

PR27

@

100K_0402_5%~N

PR12 10K_0402_1%~N

1 2

PR11

1 2

200K_0402_1%~N

D

SSM3K7002FU_SC70-3

S

12

PR23

200K_0402_1%~N

PQ10
FDV301N_NL_SOT23-3

PR22

2

PQ8

G

12

PR15

10K_0402_5%

@

12
12

12
12
12
12

TP AGND

PR139 71.5K_0402_1%~N

1 2

PC97 0.1U_0603_25V7K~N

+3VS

12

13

D

SSM3K7002FU_SC70-3

S

PR146 10_0402_5%

PC108

2.2U_0603_6.3V6K~N

1 2

VCC

J1 SHORT PADS

1 2

For EC ATE

VCC

12

PC99

150P_0402_50V8J~N

+

REF

PR21

0_0402_5%~N

12

12

PU2

19

VCC

31

D0

32

D1

33

D2

34

D3

35

D4

36

D5

1

PWRGD

17

PHASEGD

37

TWO-PH

38

SHDN

6

TIME

8

CCV

3

POUT

10

REF

7

TON

2

OFS

4

VRHOT

39

SKIP

EP

41

4700P_0603_50V7K~N

10_0402_5%~N

VDD

THRM

BST1

DH1

LX1
DL1

PGND1

CSP1
CSN1

GND

FB

CCI

BST2

DH2

LX2
DL2

PGND2

CSP2
CSN2

GNDS

12

MAX8774GTL+_TQFN40_6X6~N

12

PC102

12

PR25

PC110

1 2

2.2U_0603_6.3V6K~N

25
5
30
29
28
26
27
16
15
18
40

IC

11
9
20
21
22
24
23
13
14

12

12

2.2_0603_5%~N

1 2

DH1
LX1
DL1

PGND1

PR16

2.55K_0603_1%~N

FB

1 2

1 2

PC3 470P_0402_50V8J~N

DH2
LX2
DL2
PGND2
CSP2

PR26
100_0402_1%~N

PR187
0_0402_5%~N

12

PC104

0.01U_0402_25V7K~N

PR45

PC19

0.22U_0603_16V7K~N

PC94

4700P_0402_25V7K

1 2

PR4 20K_0402_1%~N

1 2

PR49

PC20

12

0_0603_5%~N

1 2

1 2

1 2

2.2_0603_5%~N

12

0.22U_0603_16V7K~N

PR148

PC25

@

PR2

100_0402_1%~N

PR151
0_0603_5%~N

1 2

PC24

@

4700P_0402_25V7K

12

4700P_0402_25V7K

1 2

CPU_VDD_FB_L6

PR144

0_0402_5%~N

AGND

1 2

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2007/1/25 2008/01/25

3

Compal Secret Data

Deciphered Date

5

4

3

2

1

D D

C C

B B

BATT+

PL1

MCK4532800YAF_1812

BATT+

1 2

12

PC21

0.01U_0402_25V7K~N

PJPB1 battery connector

SMART
Battery:

1.BAT+

2.BAT+

3.ID

4.B/I

5.TS

6.SMD

7.SMC

8.GND

9.GND

12

PC6
1000P_0402_50V7K~N

SUYIN_200275MR009G154ZL_RV

10

GND

11

GND

BATT++

PJP5

BATT+
BATT+

SMD

SMC
GND­GND-

BATT++

21

PF1
15A_65VDC_451015

1
2
3

ID

4

B/I

5

TS

6
7
8
9

1 2

PR10

100_0402_5%~N

1 2

PR9

100_0402_5%~N

PR135

1K_0402_5%~N

EC_SMB_DA1 26

EC_SMB_CK1 26

12

Place clsoe to EC pin

BATT_TEMP

1 2

PR173

1K_0402_5%~N

1 2

1 2

PR134

6.49K_0402_1%~N

PC43

1000P_0402_50V7K~N

BATT_TEMP 26

PC130

0.1U_0402_16V7K~N

@

CPU

+3VALWP

CPU

12

PH1 under CPU botten side :

CPU thermal protection at 85 degree C
Recovery at 70 degree C

VL VS

12

PR87

10.7K_0402_1%~N

PR83

61.9K_0402_1%~N

1 2

1 2

VL

PR84

150K_0402_1%~N

12

PH1
100K_0603_1%_TH11-4H104FT

150K_0402_1%~N

PR85

PR82

442K_0402_1%~N

1 2

12

12

8

3

+

2

-

4

PC42
1U_0603_6.3V6M~N

Battery Connect/OTP

PC115

0.1U_0603_25V7K~N

1 2

PU3A

PD25

P

1

1 2

0

G

1SS355_SOD323-2

LM358ADT_SO8~N

VL

PR81
150K_0402_1%~N

1 2

MAINPWON 31,33

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2007/1/25 2008/01/25

Compal Secret Data

Deciphered Date

Title

BATTERY CONN

Size Document Number Rev

Custom

LA-3611P

2

Date: Sheet

1

37 40Wednesday, April 11, 2007

0.4

of

5

4

3

2

1

Version Change List ( P. I. R. List )

Page 1

Request

Item Issue DescriptionDate

1

D D

2

3

4

5

6

C C

7

8

10

1

PWR-CHARGER 03/02 Compal

Owner

Compal

Compal

Compal

Compal

Compal

Compal

Compal

Compal

in order to slove battery plug in opposite make M/B damaged issue.

Add PR231 to 20ohm PR235 to 2.2 ohm
PC142 pin1 to GND,PC143 0.1uF to 0.047uF,
PR202 2.2ohm to 20ohm,PR204 18ohm
to 20 ohm

Solution Description Rev.Page# Title

0.1

0.1

0.1

0.2

0.3

0.3

0.3

0.3

0.4

11

12

13

B B

14

15

16

17

A A

Compal

Compal

Compal 0.4

Compal 0.5

Compal 0.5

Compal

Compal

0.4

0.4

0.6

Compal Electronics, Inc.

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

Next: PR238, PC202, PQ56, PD42, PJP21

5

4

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

EE-PIR

Size Document Number Rev

LA-3611P

Date: Sheet

Wednesday, April 11, 2007 4038

1

of

0.4

5

4

3

2

1

Version change list (P.I.R. List) Page 1 of 1 for HW

Reason for change Rev. PG# Modify ListFixed IssueItem

1

D D

Can't wake on LAN Isolate pin must pull high to +3VS R210 connect to +3VS22

2

3

4

Improve stable power for NB core Add U36(+1.2V_NBCORE Control circuit)30

ME/ID request Change Media Card Conn 21

5

0.3

0.3

0.3

0.3

260.3

25 Add R506 and R511WLAN LED abnormal Reverse LED_WLAN# signal

6

7

8

C C

9

10

NECP request only CPPE# of New Card connect to SB160.4

WLAN CARD

0.4 25WLAN LED always lighting if not install

ME and ID request 0.4 29 Change JLED1 connertor to 14pin

23NECP Audio Team request Change R270 to 23.7K ohm0.4

11

12

13

Add R473EC can't boot by SPI TP_SPI must pull down

New Card CPPE# and CPUSB# connect to U600.B4 (GEVENT6)0.3 16SB need check CPPE# and CPUSB# signalNew Card Can't Identified Issue

R180 pull high to +3VS

14

15

16

B B

17

18

19

20

21

22

23

24

A A

25

26

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2007/1/25 2008/01/25

Compal Secret Data

Deciphered Date

Title

PIR (HW)

Size Document Number Rev

Custom

LA-3611P

2

Date: Sheet

1

39 40Wednesday, April 11, 2007

0.4

of

5

4

3

2

1

ACIN

3VALW / 1.8VALW

32ms

+5/3/1.2VALW

ON/OFF#

D D

2ms

t<=10 ms

EC_ON

PWRBTN_OUT#

EC_RSMRST#

SYSON

t=330 ms

30ms

t=100 mst=109 ms

220ms

3V / 1.8V

<1ms

+5/3/1.8V
SLP_S3/S5#

C C

SUSP#

+5/3/1.8VS
VR_ON

100ms

130ms

3VS / 1.8VS

<1ms

20ms

+CPU_CORE

VLDT_EN

B B

+RS480_COREP/+1.2V_HT

NB_PWRGD

30ms

1ms

35ms

SB_PWRGD

CPU_PWRPG

A_RST#

70ms

48ms

2ms

PCI_RST#

A A

LDT_RST#

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2007/1/25 2008/01/25

3

Compal Secret Data

Deciphered Date

2ms

2

Title

Size Document Number Rev

Date: Sheet

Power Sequence

Wednesday, April 11, 2007

LA-3611P

1

of

40 40

Compal Electronics, Inc.

0.4