COMPAL LA-3591P Schematics

A

ZZZ

PCB

DA600004Q00

1 1

B

C

D

E

Compal Confidential

2 2

Tuesday, March 06, 2007

IGT10/11

Schematics Document

Mobile Merom uFCPGA with Intel
Crestline_GM/PM+ICH8-M core logic

3 3

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4 4

2006/08/04 2006/10/06

Compal Secret Data

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REV:0.2

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

Cover Sheet

IGT10/11 LA-3591P

of

148

0.2

A

B

C

D

E

A

Compal confidential

File Name : LA-3451P

B

C

D

E

1 1

LVDS

Mobile Merom

uFCPGA-478 CPU

Connector

Clock Gen.
ICS9LPRS355

page15

VGA BOARD

H_A#(3..35)
H_D#(0..63)

page4,5,6

FSB

667/800MHz

PCI-E X16

Intel Crestline GMCH

CRT & TV OUT

page16

2 2

LVDS
Connector

page17

LVDS I/F

PCBGA 1299

page7,8,9,10,11,12

DMI

C-Line

DDR2 -667

Dual Channel

DDR2-SO-DIMM X2

BANK 0, 1, 2, 3

page 13,14

MODEM

Ver 1.5

page 28

AMP&Audio Jack

AZALIA

PCI Express
Mini card Slot

3 3

page26

BCM5906
10/100 LAN

page23

IDSEL:PCI_AD22

1394+Card Reader

RICOH R5C833

RJ45 CONN

page24

page28

PCI-E BUS

3.3V / 33 MHz

page28

PCI_REQ0#
PCI_GNT0#

Card reader(XD/SD1394 Conn
MMC/MS/MS-Pro
HD SD)

Intel ICH8-M

PCI BUS

IDSEL:PCI_AD20

PCMCIA

ENE CB1410

page27

PCMCIA

page37 page33

CONN

page27

PCI_REQ2#
PCI_GNT2#

ENE KB926

mBGA-676

LPC BUS

EC

page19,20,21,22

SIO

LPC47N217

USB2.0

SATA
ATA100

Audio Codec
ALC 268

Finger printer

BlueTooth Conn

USB conn X3

SATA HDD
Connector

Int.KBD

BIOS

page32

page34

PATA CDROM
Connector

TP Board

Touch Pad

page36

USB Board

page30

page29

page36

page28

page31

page23

page23

4 4

FP Board

SW Board

SERIAL PORT

page35

Security Classification

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THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2006/08/04 2006/10/06

Compal Secret Data

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Title

Size Document Number Rev

Custom

D

Date: Sheet

Compal Electronics, Inc.

Block Diagram

IGT10/11 LA-3591P

248Tuesday, March 06, 2007

E

0.2

of

Voltage Rails

power
plane

State

O MEANS ON X MEANS OFF

+B
LDO3
LDO5

+5VALW
+3VALW

+1.8V

+5V

+0.9V

+5VS
+3VS
+2.5VS
+1.8VS
+1.5VS
+1.25VS
+VGA_CORE
+CPU_CORE
+VCCP

CLOCK

A

SKU ID Table

Vcc 3.3V +/- 5%

Board ID

0

*

1
2
3
4
5
6
7 NC

100K +/- 5%Ra

Rb V min

0

8.2K +/- 5%
18K +/- 5%
33K +/- 5%
56K +/- 5%
100K +/- 5%
200K +/- 5%

AD_BID

0 V

V typ

AD_BID

0 V 0 V

V

AD_BID

max

0.216 V 0.250 V 0.289 V

0.436 V

0.712 V

1.036 V

0.503 V

0.819 V

0.538 V

0.875 V

1.185 V 1.264 V

1.453 V 1.650 V 1.759 V

1.935 V

2.500 V

2.200 V

3.300 V

2.341 V

3.300 V

S0

S3

S5 S4/AC

S5 S4/ Battery only

S5 S4/AC & Battery
don't exist

O

O
O
O

X

O

O
O

X

O

XX
X

XXX

OO

X

X

O

O
O

X
X

SKU ID

*

0
1
2
3
4
5
6
7

MB ID(H)

MB ID(L)

IEL10
IDL11 IDL01
HDL10

HDL00
HDL20
HDL30IDL12

MB ID

O MEANS ON

X MEANS OFF

H
L

S3 : STR
S4 : STD

15"
14"

S5 : SOFT OFF

1 1

External PCI Devices

Device IDSEL# REQ#/GNT# Interrupts

1394 PIRQG/H

AD22

EC SM Bus1 address

Device

Smart Battery
EEPROM(24C16/02)

Address

0001 011X b
1010 000X b

0

EC SM Bus2 address

Device

ADM1032

Address

1001 100X b

BOM Structure USB PORT LIST

MARK FUNCTION

GIGA@

Address

100@
UMA@
VGA@

NC FOR ALL@
BCM5787
BCM5906
Internal 965GM
965PM + Ext VGA

PORT DEVICE

LEFT SIDE

0

WIRELESS

1

RIGHT SIDE

2

CMOS3
RIGHT SIDE

4

NEW CARD

5
6

RIGHT SIDE

7

BT(HDL20)
FINGER PRINTER

8
9 TV TUNER

ICH6 SM Bus address

Device

Clock Generator
( ICS954226)

DDRII DIMM0
DDRII DIMM1

Address

1101 001Xb
1010 000Xb
1010 010Xb

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

2006/08/04 2006/10/06

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

Notes List

IGT10/11 LA-3591P

of

348Tuesday, March 06, 2007

0.2

5

4

3

2

1

XDP Reserve

D D

H_A#[3..16](7)

H_ADSTB#0(7)

H_REQ#0(7)
H_REQ#1(7)
H_REQ#2(7)
H_REQ#3(7)
H_REQ#4(7)

H_A#[17..35](7)

C C

H_ADSTB#1(7)

H_A20M#(19)

H_FERR#(19)

H_IGNNE#(19)
H_STPCLK#(19)

H_INTR(19)

H_NMI(19)
H_SMI#(19)

B B

A A

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16

H_ADSTB#0
H_REQ#0

H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35
H_ADSTB#1

H_A20M#
H_FERR#
H_IGNNE#

H_STPCLK#
H_INTR
H_NMI
H_SMI#

H_CPU_PROCHOT# H_PROCHOT#

JP1A

J4

0

A[3]#

L5

A[4]#

L4

A[5]#

K5

A[6]#

M3

A[7]#

N2

A[8]#

J1

A[9]#

N3

A[10]#

P5

A[11]#

P2

A[12]#

L2

A[13]#

P4

A[14]#

P1

A[15]#

R1

A[16]#

M1

ADSTB[0]#

K3

REQ[0]#

H2

REQ[1]#

K2

REQ[2]#

J3

REQ[3]#

L1

REQ[4]#

Y2

A[17]#

U5

A[18]#

R3

1

A[19]#

W6

A[20]#

U4

A[21]#

Y5

A[22]#

U1

A[23]#

R4

A[24]#

T5

A[25]#

T3

A[26]#

W2

A[27]#

W5

A[28]#

Y4

A[29]#

U2

A[30]#

V4

A[31]#

W3

A[32]#

AA4

A[33]#

AB2

A[34]#

AA3

A[35]#

V1

ADSTB[1]#

A6

A20M#

A5

FERR#

C4

IGNNE#

D5

STPCLK#

C6

LINT0

B4

LINT1

A3

SMI#

M4

RSVD[01]

N5

RSVD[02]

T2

RSVD[03]

V3

RSVD[04]

B2

RSVD[05]

C3

RSVD[06]

D2

RSVD[07]

D22

RSVD[08]

D3

RSVD[09]

F6

RSVD[10]

Merom Ball-out Rev 1a

ADDR GROUP

ADDR GROUP

XDP/ITP SIGNALS

THERMAL

PROCHOT#

THERMDA
THERMDC

ICH

THERMTRIP#

H CLK

RESERVED

+VCCP

12

R15

56_0402_5%

B

2

E

3 1

C

Q1
MMBT3904_SOT23

ADS#
BNR#
BPRI#

DEFER#

DRDY#
DBSY#

BR0#

IERR#

INIT#

LOCK#

CONTROL

RESET#

RS[0]#
RS[1]#
RS[2]#

TRDY#

HIT#

HITM#

BPM[0]#
BPM[1]#
BPM[2]#
BPM[3]#

PRDY#
PREQ#

TCK
TDO

TMS

TRST#

DBR#

BCLK[0]
BCLK[1]

H_ADS#

H1

H_BNR#

E2

H_BPRI#

G5

H_DEFER#

H5

H_DRDY#

F21

H_DBSY#

E1

H_BR0#

F1

H_IERR#

D20

H_INIT#

B3

H_LOCK#

H4

H_RESET#

C1

H_RS#0

F3

H_RS#1

F4

H_RS#2

G3

H_TRDY#

G2

H_HIT#

G6

H_HITM#

E4

XDP_BPM#0

AD4

XDP_BPM#1

AD3

XDP_BPM#2

AD1

XDP_BPM#3

AC4

XDP_BPM#4

AC2

XDP_BPM#5

AC1

XDP_TCK

AC5

XDP_TDI

AA6

TDI

AB3
AB5
AB6
C20

D21
A24
B25

C7

A22
A21

XDP_TDO
XDP_TMS
XDP_TRST#

XDP_DBRESET#_R

H_CPU_PROCHOT#

H_THERMDA
H_THERMDC

H_THERMTRIP#

CLK_CPU_BCLK
CLK_CPU_BCLK#

H_ADS# (7)
H_BNR# (7)

H_BPRI# (7)

H_DEFER# (7)
H_DRDY# (7)
H_DBSY# (7)

H_BR0# (7)

H_INIT# (19)
H_LOCK# (7)
H_RESET# (7)

H_RS#0 (7)

H_RS#1 (7)

H_RS#2 (7)

H_TRDY# (7)

H_HIT# (7)
H_HITM# (7)

T1 PAD
T2 PAD
T3 PAD
T4 PAD
T5 PAD

1 2

R13 56_0402_5%

H_THERMDA, H_THERMDC routing together,
Trace width / Spacing = 10 / 10 mil

H_PROCHOT# (20,46)

R9

56_0402_5%

R616

0_0402_5%

12

H_THERMTRIP# (7,19)

CLK_CPU_BCLK (15)
CLK_CPU_BCLK# (15)

12

+VCCP

+VCCP

XDP_DBRESET# (20)

1
2
3
4

FAN_SPEED1(33)

U2

VEN
VIN
VO
VSET

G993P1UF_SOP8

U1

2

D+

3

D-

8

SCLK

7

SDATA

G781F_MSOP8

Address:100_1100

SA007810140

2006/09/05

C3

1 2

10U_0805_10V4Z

GND
GND
GND
GND

H_THERMDA

C2

H_THERMDC

1 2

+VCC_FAN1
EN_FAN1

2200P_0402_50V7K

EC_SMB_DA2

+5VS

EC_SMB_CK2(33)
EC_SMB_DA2(17,33)

EN_FAN1(33)

XDP_DBRESET#_R

XDP_TDI
XDP_TMS
XDP_TDO
XDP_BPM#5

XDP_TRST#
XDP_TCK

2006/09/19

+3VS

C1

1 2

0.1U_0402_16V4Z

1

VDD1

THERM_SCI#

6

ALERT#

THERM#

GND

THERM#EC_SMB_CK2

4
5

FAN1 Conn

8
7
6
5

2006/09/05

+3VS

12

R14
10K_0402_5%

1

C6
1000P_0402_50V7K

2

1 2

R1

R2 150_0402_1%

1 2

R3 39_0402_1%

1 2

R4 54.9_0402_1%@

1 2

R5 54.9_0402_1%

1 2

R7 56_0402_5%

1 2

R8 54.9_0402_1%

1 2

R10
10K_0402_5%

1 2

12

R11 0_0402_5%@

12

R1210K_0402_5%

+5VS

12

D1
1SS355_SOD323@

1N4148_SOT23@

1 2

C4

1 2

1000P_0402_50V7K

1 2

40mil

+VCC_FAN1

1K_0402_5%@

+3VS

Check : to sb

D2

10U_0805_10V4Z

C5

JP2

1
2
3

ACES_85205-03001

ME@

+3VS

+VCCP

EC_THERM# (20,33)

2006/09/19

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/08/04 2006/10/06

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

Compal Electronics, Inc.

Merom(1/3)-AGTL+/XDP

IGT10/11 LA-3591P

1

0.2

of

448Tuesday, March 06, 2007

5

4

3

2

1

H_D#[0..15](7)

D D

H_DSTBN#0(7)
H_DSTBP#0(7)

H_DINV#0(7)

H_D#[16..31](7)

H_DSTBN#1(7)

C C

H_DSTBP#1(7)

H_DINV#1(7)

R18 1K_0402_5%@

1 2

R19 1K_0402_5%@

1 2

C8 0.1U_0402_16V4Z@

1 2

CPU_BSEL0(15)
CPU_BSEL1(15)
CPU_BSEL2(15)

T12 PAD
T13 PAD

T14 PAD

H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_DSTBN#0
H_DSTBP#0
H_DINV#0

H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_DSTBN#1
H_DSTBP#1
H_DINV#1

+CPU_GTLREF

TEST1
TEST2
TEST3
TEST4
TEST5
TEST6

CPU_BSEL0 H_PWRGOOD
CPU_BSEL1
CPU_BSEL2

JP1B

E22

D[0]#

F24

D[1]#

E26

D[2]#

G22

D[3]#

F23

D[4]#

G25

D[5]#

E25

D[6]#

E23

D[7]#

K24

D[8]#

G24

D[9]#

J24

D[10]#

J23

D[11]#

H22

D[12]#

F26

D[13]#

K22

D[14]#

H23

D[15]#

J26

DSTBN[0]#

H26

DSTBP[0]#

H25

DINV[0]#

N22

D[16]#

K25

D[17]#

P26

D[18]#

R23

D[19]#

L23

D[20]#

M24

D[21]#

L22

D[22]#

M23

D[23]#

P25

D[24]#

P23

D[25]#

P22

D[26]#

T24

D[27]#

R24

D[28]#

L25

D[29]#

T25

D[30]#

N25

D[31]#

L26

DSTBN[1]#

M26

DSTBP[1]#

N24

DINV[1]#

AD26

GTLREF

C23

TEST1

D25

TEST2

C24

TEST3

AF26

TEST4

AF1

TEST5

A26

TEST6

B22

BSEL[0]

B23

BSEL[1]

C21

BSEL[2]

Merom Ball-out Rev 1a

DATA GRP 0

DATA GRP 1

MISC

D[32]#
D[33]#
D[34]#
D[35]#
D[36]#
D[37]#
D[38]#
D[39]#
D[40]#
D[41]#
D[42]#
D[43]#
D[44]#
D[45]#

DATA GRP 2DATA GRP 3

D[46]#

D[47]#
DSTBN[2]#
DSTBP[2]#

DINV[2]#

D[48]#

D[49]#

D[50]#

D[51]#

D[52]#

D[53]#

D[54]#

D[55]#

D[56]#

D[57]#

D[58]#

D[59]#

D[60]#

D[61]#

D[62]#

D[63]#
DSTBN[3]#
DSTBP[3]#

DINV[3]#
COMP[0]

COMP[1]
COMP[2]
COMP[3]

DPRSTP#

DPSLP#

DPWR#

PWRGOOD

SLP#

PSI#

Y22
AB24
V24
V26
V23
T22
U25
U23
Y25
W22
Y23
W24
W25
AA23
AA24
AB25
Y26
AA26
U22

AE24
AD24
AA21
AB22
AB21
AC26
AD20
AE22
AF23
AC25
AE21
AD21
AC22
AD23
AF22
AC23
AE25
AF24
AC20

R26
U26
AA1
Y1

E5
B5
D24
D6
D7
AE6

H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_DSTBN#2
H_DSTBP#2
H_DINV#2

H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
H_DSTBN#3
H_DSTBP#3
H_DINV#3

COMP0
COMP1
COMP2
COMP3

H_DPRSTP#
H_DPSLP#
H_DPWR#

H_CPUSLP#
H_PSI#

layout note: Route TEST3 & TEST5 traces on ground referenced layer to the TPs

CPU_BSEL CPU_BSEL2 CPU_BSEL1

166

200

B B

+CPU_GTLREF

01

+VCCP

0

12

R24
1K_0402_1%

12

R26
2K_0402_1%

1

CPU_BSEL0

1

0

H_D#[32..47] (7)

H_DSTBN#2 (7)
H_DSTBP#2 (7)
H_DINV#2 (7)
H_D#[48..63] (7)

H_DSTBN#3 (7)
H_DSTBP#3 (7)
H_DINV#3 (7)

H_DPRSTP# (7,19,46)

H_DPSLP# (19)
H_DPWR# (7)
H_PWRGOOD (19)

H_CPUSLP# (7)
H_PSI# (46)

12

R21

12

27.4_0402_1%

R22

54.9_0402_1%

12

R23

27.4_0402_1%

12

R20

54.9_0402_1%

Resistor placed within

0.5" of CPU pin.Trace
should be at least 25
mils away from any other
toggling signal.
COMP[0,2] trace width is
18 mils. COMP[1,3] trace
width is 4 mils.

JP1C

A7

VCC[001]

A9

VCC[002]

A10

VCC[003]

A12

VCC[004]

A13

VCC[005]

A15

VCC[006]

A17

VCC[007]

A18

VCC[008]

A20

VCC[009]

B7

VCC[010]

B9

VCC[011]

B10

VCC[012]

B12

VCC[013]

B14

VCC[014]

B15

VCC[015]

B17

VCC[016]

B18

VCC[017]

B20

VCC[018]

C9

VCC[019]

C10

VCC[020]

C12

VCC[021]

C13

VCC[022]

C15

VCC[023]

C17

VCC[024]

C18

VCC[025]

D9

VCC[026]

D10

VCC[027]

D12

VCC[028]

D14

VCC[029]

D15

VCC[030]

D17

VCC[031]

D18

VCC[032]

E7

VCC[033]

E9

VCC[034]

E10

VCC[035]

E12

VCC[036]

E13

VCC[037]

E15

VCC[038]

E17

VCC[039]

E18

VCC[040]

E20

VCC[041]

F7

VCC[042]

F9

VCC[043]

F10

VCC[044]

F12

VCC[045]

F14

VCC[046]

F15

VCC[047]

F17

VCC[048]

F18

VCC[049]

F20

VCC[050]

AA7

VCC[051]

AA9

VCC[052]

AA10

VCC[053]

AA12

VCC[054]

AA13

VCC[055]

AA15

VCC[056]

AA17

VCC[057]

AA18

VCC[058]

AA20

VCC[059]

AB9

VCC[060]

AC10

VCC[061]

AB10

VCC[062]

AB12

VCC[063]

AB14

VCC[064]

AB15

VCC[065]

AB17

VCC[066]

AB18

VCC[067]

Merom Ball-out Rev 1a

VCC[068]
VCC[069]
VCC[070]
VCC[071]
VCC[072]
VCC[073]
VCC[074]
VCC[075]
VCC[076]
VCC[077]
VCC[078]
VCC[079]
VCC[080]
VCC[081]
VCC[082]
VCC[083]
VCC[084]
VCC[085]
VCC[086]
VCC[087]
VCC[088]
VCC[089]
VCC[090]
VCC[091]
VCC[092]
VCC[093]
VCC[094]
VCC[095]
VCC[096]
VCC[097]
VCC[098]
VCC[099]
VCC[100]

VCCP[01]
VCCP[02]
VCCP[03]
VCCP[04]
VCCP[05]
VCCP[06]
VCCP[07]
VCCP[08]
VCCP[09]
VCCP[10]
VCCP[11]
VCCP[12]
VCCP[13]
VCCP[14]
VCCP[15]
VCCP[16]

VCCA[01]
VCCA[02]

VID[0]
VID[1]
VID[2]
VID[3]
VID[4]
VID[5]
VID[6]

VCCSENSE

VSSSENSE

+CPU_CORE+CPU_CORE

AB20
AB7
AC7
AC9
AC12
AC13
AC15
AC17
AC18
AD7
AD9
AD10
AD12
AD14
AD15
AD17
AD18
AE9
AE10
AE12
AE13
AE15
AE17
AE18
AE20
AF9
AF10
AF12
AF14
AF15
AF17
AF18
AF20

G21
V6
J6
K6
M6
J21
K21
M21
N21
N6
R21
R6
T21
T6
V21
W21

B26
C26

AD6
AF5
AE5
AF4
AE3
AF3
AE2

AF7

AE7

.

For testing purpose only

R16 0_0402_5%

12
12

R17 0_0402_5%

VCCSENSE

VSSSENSE

Length match within 25 mils.
The trace width/space/other is
20/7/25.

+CPU_CORE

1 2

1 2

R25
100_0402_1%

R27
100_0402_1%

+VCCP

1

+

C7

2

330U_V_2.5VK_R9

CPU_VID0 (46)
CPU_VID1 (46)
CPU_VID2 (46)
CPU_VID3 (46)
CPU_VID4 (46)
CPU_VID5 (46)
CPU_VID6 (46)

VCCSENSE (46)

VSSSENSE (46)

VCCSENSE

VSSSENSE

C9

1

C10

2

10U_0805_10V4Z

+1.5VS

1

2

0.01U_0402_16V7K

Near pin B26

Close to CPU pin AD26
within 500mils.

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/08/04 2006/10/06

Compal Secret Data

Deciphered Date

2

Close to CPU pin
within 500mils.

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

Merom(2/3)-AGTL+/PWR

IGT10/11 LA-3591P

1

of

548Tuesday, March 06, 2007

0.2

5

4

3

2

1

1

C50

0.1U_0402_16V4Z

2

+CPU_CORE

+CPU_CORE

+CPU_CORE

+CPU_CORE

+CPU_CORE

1

+

2

1

C11
10U_0805_6.3V6M

2

1

C19
10U_0805_6.3V6M

2

1

C27
10U_0805_6.3V6M

2

1

C35
10U_0805_6.3V6M

2

1

+

C43

C44

2

330U_D2E_2.5VM_R9

1

C51

0.1U_0402_16V4Z

2

1

C12
10U_0805_6.3V6M

2

1

C20
10U_0805_6.3V6M

2

1

C28
10U_0805_6.3V6M

2

1

C36
10U_0805_6.3V6M

2

1

+

C45

2

330U_D2E_2.5VM_R9

1

C52

0.1U_0402_16V4Z

2

1

C13
10U_0805_6.3V6M

2

1

C21
10U_0805_6.3V6M

2

1

C29
10U_0805_6.3V6M

2

1

C37
10U_0805_6.3V6M

2

1

+

C46

2

330U_D2E_2.5VM_R9

330U_D2E_2.5VM_R9

1

C53

0.1U_0402_16V4Z

2

1

2

1

2

1

2

1

2

1

+

C47

2

C14
10U_0805_6.3V6M

C22
10U_0805_6.3V6M

C30
10U_0805_6.3V6M

C38
10U_0805_6.3V6M

1

+

C48
330U_D2E_2.5VM_R9

2

1

C54

0.1U_0402_16V4Z

2

1

C15
10U_0805_6.3V6M

2

1

C23
10U_0805_6.3V6M

2

1

C31
10U_0805_6.3V6M

2

1

C39
10U_0805_6.3V6M

2

North Side Secondary

1

C55

0.1U_0402_16V4Z

2

1

C16
10U_0805_6.3V6M

2

1

C24
10U_0805_6.3V6M

2

1

C32
10U_0805_6.3V6M

2

1

C40
10U_0805_6.3V6M

2

1

2

1

2

1

2

1

2

ESR <= 1.5m ohm
Capacitor > 1980uF

Place these inside
socket cavity on L8
(North side
Secondary)

C17
10U_0805_6.3V6M

C25
10U_0805_6.3V6M

C33
10U_0805_6.3V6M

C41
10U_0805_6.3V6M

1

C18
10U_0805_6.3V6M

2

1

C26
10U_0805_6.3V6M

2

1

C34
10U_0805_6.3V6M

2

1

C42
10U_0805_6.3V6M

2

Mid Frequence Decoupling

D D

C C

B B

JP1D

A4
A8

A11
A14
A16
A19
A23
AF2

B6
B8

B11
B13
B16
B19
B21
B24

C5
C8

C11
C14
C16
C19

C2

C22
C25

D1
D4
D8

D11
D13
D16
D19
D23
D26

E3
E6
E8

E11
E14
E16
E19
E21
E24

F5
F8

F11
F13
F16
F19

F2

F22
F25

G4
G1

G23
G26

H3
H6

H21
H24

J2
J5

J22
J25

K1
K4

K23
K26

L3
L6

L21
L24

M2
M5

M22
M25

N1
N4

N23
N26

P3 A25

VSS[082]

VSS[001]
VSS[002]

VSS[083]

VSS[003]

VSS[084]

VSS[004]

VSS[085]

VSS[005]

VSS[086]

VSS[006]

VSS[087]

VSS[007]

VSS[088]

VSS[008]

VSS[089]

VSS[009]

VSS[090]

VSS[010]

VSS[091]

VSS[011]

VSS[092]

VSS[012]

VSS[093]

VSS[013]

VSS[094]

VSS[014]

VSS[095]

VSS[015]

VSS[096]

VSS[016]

VSS[097]

VSS[017]

VSS[098]

VSS[018]

VSS[099]

VSS[019]

VSS[100]

VSS[020]

VSS[101]

VSS[021]

VSS[102]

VSS[022]

VSS[103]

VSS[023]

VSS[104]

VSS[024]

VSS[105]

VSS[025]

VSS[106]

VSS[026]

VSS[107]

VSS[027]

VSS[108]

VSS[028]

VSS[109]

VSS[029]

VSS[110]

VSS[030]

VSS[111]
VSS[112]

VSS[031]

VSS[113]

VSS[032]

VSS[114]

VSS[033]

VSS[115]

VSS[034]

VSS[116]

VSS[035]

VSS[117]

VSS[036]

VSS[118]

VSS[037]

VSS[119]

VSS[038]

VSS[120]

VSS[039]

VSS[121]

VSS[040]

VSS[122]

VSS[041]

VSS[123]

VSS[042]

VSS[124]

VSS[043]

VSS[125]

VSS[044]

VSS[126]

VSS[045]

VSS[127]

VSS[046]

VSS[128]

VSS[047]

VSS[129]

VSS[048]

VSS[130]

VSS[049]

VSS[131]

VSS[050]

VSS[132]

VSS[051]

VSS[133]

VSS[052]

VSS[134]

VSS[053]

VSS[135]

VSS[054]

VSS[136]

VSS[055]

VSS[137]

VSS[056]

VSS[138]

VSS[057]

VSS[139]

VSS[058]

VSS[140]

VSS[059]

VSS[141]

VSS[060]

VSS[142]

VSS[061]

VSS[143]

VSS[062]

VSS[144]

VSS[063]

VSS[145]

VSS[064]

VSS[146]

VSS[065]

VSS[147]

VSS[066]

VSS[148]

VSS[067]

VSS[149]

VSS[068]

VSS[150]

VSS[069]
VSS[070]

VSS[151]

VSS[071]

VSS[152]

VSS[072]

VSS[153]

VSS[073]

VSS[154]

VSS[074]

VSS[155]

VSS[075]

VSS[156]

VSS[076]

VSS[157]

VSS[077]

VSS[158]

VSS[078]

VSS[159]

VSS[079]

VSS[160]

VSS[080]

VSS[161]

VSS[081] VSS[162]

VSS[163]

Merom Ball-out Rev 1a

P6
P21
P24
R2
R5
R22
R25
T1
T4
T23
T26
U3
U6
U21
U24
V2
V5
V22
V25
W1
W4
W23
W26
Y3
Y6
Y21
Y24
AA2
AA5
AA8
AA11
AA14
AA16
AA19
AA22
AA25
AB1
AB4
AB8
AB11
AB13
AB16
AB19
AB23
AB26
AC3
AC6
AC8
AC11
AC14
AC16
AC19
AC21
AC24
AD2
AD5
AD8
AD11
AD13
AD16
AD19
AD22
AD25
AE1
AE4
AE8
AE11
AE14
AE16
AE19
AE23
AE26
A2
AF6
AF8
AF11
AF13
AF16
AF19
AF21

AF25

.

220U_D2_4VM

Place these capacitors on L8
(North side,Secondary Layer)

Place these capacitors on L8
(North side,Secondary Layer)

Place these capacitors on L8
(Sorth side,Secondary Layer)

Place these capacitors on L8
(Sorth side,Secondary Layer)

South Side Secondary

330U_D2E_2.5VM_R9

+VCCP

1

+

C49

2

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/08/04 2006/10/06

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

Compal Electronics, Inc.

Merom(3/3)-GND&Bypass

IGT10/11 LA-3591P

1

0.2

of

648Tuesday, March 06, 2007

5

W10

AD12

AD9
AC9

AC7
AC14
AD11
AC11

AD7

AC6

AC5

AG3

AH8

AJ14

AE11
AH12

AH5

AH2
AH13

E2
G2
G7
M6

H7

H3
G4

F3

N8

H2

M10
N12

N9

H5

P13

K9
M2

Y8

V4
M3

J1

N5

N3
W6
W9

N2

Y7

Y9

P4
W3

N1

AE3

AB2
AB1

Y3

AE2

AJ9

AE9

AJ5
AJ6

AE7

AJ7
AJ2

AE5

AJ3

B3

C2
W1

W2

B6

E5

B9

A9

U3A

H_D#_0
H_D#_1
H_D#_2
H_D#_3
H_D#_4
H_D#_5
H_D#_6
H_D#_7
H_D#_8
H_D#_9
H_D#_10
H_D#_11
H_D#_12
H_D#_13
H_D#_14
H_D#_15
H_D#_16
H_D#_17
H_D#_18
H_D#_19
H_D#_20
H_D#_21
H_D#_22
H_D#_23
H_D#_24
H_D#_25
H_D#_26
H_D#_27
H_D#_28
H_D#_29
H_D#_30
H_D#_31
H_D#_32
H_D#_33
H_D#_34
H_D#_35
H_D#_36
H_D#_37
H_D#_38
H_D#_39
H_D#_40
H_D#_41
H_D#_42
H_D#_43
H_D#_44
H_D#_45
H_D#_46
H_D#_47
H_D#_48
H_D#_49
H_D#_50
H_D#_51
H_D#_52
H_D#_53
H_D#_54
H_D#_55
H_D#_56
H_D#_57
H_D#_58
H_D#_59
H_D#_60
H_D#_61
H_D#_62
H_D#_63

H_SWING
H_RCOMP

H_SCOMP
H_SCOMP#

H_CPURST#
H_CPUSLP#

H_AVREF
H_DVREF

CRESTLINE_1p0

UMA@

SA00000ZWA0

HOST

H_ADSTB#_0
H_ADSTB#_1

H_DEFER#

HPLL_CLK

HPLL_CLK#

H_DPWR#

H_DINV#_0
H_DINV#_1
H_DINV#_2
H_DINV#_3

H_DSTBN#_0
H_DSTBN#_1
H_DSTBN#_2
H_DSTBN#_3

H_DSTBP#_0
H_DSTBP#_1
H_DSTBP#_2
H_DSTBP#_3

H_REQ#_0
H_REQ#_1

H_REQ#_2
H_REQ#_3

H_REQ#_4

H_D#[0..63](5)

D D

C C

+VCCP

12

12

R34

R33

54.9_0402_1%

54.9_0402_1%

H_RESET#(4)

H_CPUSLP#(5)

B B

H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57

H_D#59
H_D#60
H_D#61
H_D#62
H_D#63

H_SWNG
H_RCOMP

H_SCOMP
H_SCOMP#

H_RESET#
H_CPUSLP#

H_VREF

layout note:
Route H_SCOMP and H_SCOMP# with trace width, spacing and impedance (55 ohm) same as FSB data traces

Layout Note:
H_RCOMP / H_VREF / H_SWNG

trace width and spacing is 10/20

+VCCP

R45

R51

12

221_0603_1%

H_SWNGH_VREF

12

1

C63

2

100_0402_1%

0.1U_0402_16V4Z

+VCCP

12

R44

1K_0402_1%

A A

0.1U_0402_16V4Z

12

1

C62

R49

2

2K_0402_1%

12

R50

24.9_0402_1%

H_RCOMP

Near B3 pinwithin 100 mils from NB

5

H_A#_3
H_A#_4
H_A#_5
H_A#_6
H_A#_7
H_A#_8

H_A#_9
H_A#_10
H_A#_11
H_A#_12
H_A#_13
H_A#_14
H_A#_15
H_A#_16
H_A#_17
H_A#_18
H_A#_19
H_A#_20
H_A#_21
H_A#_22
H_A#_23
H_A#_24
H_A#_25
H_A#_26
H_A#_27
H_A#_28
H_A#_29
H_A#_30
H_A#_31
H_A#_32
H_A#_33
H_A#_34
H_A#_35

H_ADS#

H_BNR#

H_BPRI#

H_BREQ#
H_DBSY#

H_DRDY#

H_HIT#
H_HITM#

H_LOCK#
H_TRDY#

H_RS#_0
H_RS#_1
H_RS#_2

+DDR_MCH_REF

4

H_A#3

J13

H_A#4

B11

H_A#5

C11

H_A#6

M11

H_A#7

C15

H_A#8

F16

H_A#9

L13

H_A#10

G17

H_A#11

C14

H_A#12

K16

H_A#13

B13

H_A#14

L16

H_A#15

J17

H_A#16

B14

H_A#17

K19

H_A#18

P15

H_A#19

R17

H_A#20

B16

H_A#21

H20

H_A#22

L19

H_A#23

D17

H_A#24

M17

H_A#25

N16

H_A#26

J19

H_A#27

B18

H_A#28

E19

H_A#29

B17

H_A#30

B15

H_A#31

E17

H_A#32

C18

H_A#33

A19

H_A#34

B19

H_A#35

N19

H_ADS#

G12

H_ADSTB#0

H17

H_ADSTB#1

G20

H_BNR#

C8

H_BPRI#

E8

H_BR0#

F12

H_DEFER#

D6

H_DBSY#

C10

CLK_MCH_BCLK

AM5

CLK_MCH_BCLK#

AM7

H_DPWR#

H8

H_DRDY#

K7

H_HIT#

E4

H_HITM#

C6

H_LOCK#

G10

H_TRDY#

B7

H_DINV#0

K5

H_DINV#1

L2

H_DINV#2

AD13

H_DINV#3

AE13

H_DSTBN#0H_D#58

M7

H_DSTBN#1

K3

H_DSTBN#2

AD2

H_DSTBN#3

AH11

H_DSTBP#0

L7

H_DSTBP#1

K2

H_DSTBP#2

AC2

H_DSTBP#3

AJ10

H_REQ#0

M14

H_REQ#1

E13

H_REQ#2

A11

H_REQ#3

H13

H_REQ#4

B12

H_RS#0

E12

H_RS#1

D7

H_RS#2

D8

ICH_POK(20,33)

VGATE(20,46)

PLT_RST#(17,18,20,23,25,26)

Layout Note:
V_DDR_MCH_REF
trace width and
spacing is 20/20.

4

H_A#[3..35] (4)

H_ADS# (4)
H_ADSTB#0 (4)
H_ADSTB#1 (4)
H_BNR# (4)
H_BPRI# (4)
H_BR0# (4)
H_DEFER# (4)
H_DBSY# (4)
CLK_MCH_BCLK (15)
CLK_MCH_BCLK# (15)
H_DPWR# (5)
H_DRDY# (4)
H_HIT# (4)
H_HITM# (4)
H_LOCK# (4)
H_TRDY# (4)

H_DINV#0 (5)
H_DINV#1 (5)
H_DINV#2 (5)
H_DINV#3 (5)

H_DSTBN#0 (5)
H_DSTBN#1 (5)
H_DSTBN#2 (5)
H_DSTBN#3 (5)

H_DSTBP#0 (5)
H_DSTBP#1 (5)
H_DSTBP#2 (5)
H_DSTBP#3 (5)

H_REQ#0 (4)
H_REQ#1 (4)
H_REQ#2 (4)
H_REQ#3 (4)
H_REQ#4 (4)

H_RS#0 (4)
H_RS#1 (4)
H_RS#2 (4)

R35 0_0402_5%
R36 0_0402_5%@

1 2

R37 100_0402_5%

+DDR_MCH_REF

1

C61

2

0.1U_0402_16V4Z

3

SMRCOMP_VOH

SMRCOMP_VOL

MCH_CLKSEL0(15)
MCH_CLKSEL1(15)
MCH_CLKSEL2(15)

Check : different from hdl00

12
12

PM_POK_R PM_POK_R

0309 add

PLT_RST#_R

+3VS

+1.8V

12

R42

1K_0402_1%

12

R43

1K_0402_1%

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

+1.8V

2

2

1

C56

2.2U_0603_10V6K

1

2

C58

2.2U_0603_10V6K

PM_BMBUSY#(20)

H_DPRSTP#(5,19,46)
PM_EXTTS#0(13)
PM_EXTTS#1(14)

H_THERMTRIP#(4,19)

DPRSLPVR(20,46)

R39 10K_0402_5%
R40 10K_0402_5%

1

C57

1

2

C59

CFG5(9)
CFG6
CFG7(9)
CFG8(9)

CFG9(9)
CFG10
CFG11
CFG12(9)
CFG13(9)

CFG16(9)
CFG18

CFG19(9)
CFG20(9)

1 2
1 2

0.01U_0402_25V7K

0.01U_0402_25V7K

DDR_A_MA14(13)
DDR_B_MA14(14)

12

R28
1K_0402_1%

12

R29

3.01K_0402_1%

NA lead free

12

R30
1K_0402_1%

PM_EXTTS#0
PM_EXTTS#1

2006/08/04 2006/10/06

MCH_CLKSEL0
MCH_CLKSEL1
MCH_CLKSEL2

CFG5
CFG6
CFG7

CFG9
CFG10
CFG11
CFG12
CFG13

CFG16
CFG18

CFG19
CFG20

PM_BMBUSY#
H_DPRSTP#
PM_EXTTS#0
PM_EXTTS#1

PLT_RST#_R
H_THERMTRIP#
DPRSLPVR

Compal Secret Data

U3B

P36

RSVD1

P37

RSVD2

R35

RSVD3

N35

RSVD4

AR12

RSVD5

AR13

RSVD6

AM12

RSVD7

AN13

RSVD8

J12

RSVD9

AR37

RSVD10

AM36

RSVD11

AL36

RSVD12

AM37

RSVD13

D20

RSVD14

H10

RSVD20

B51

RSVD21

BJ20

RSVD22

BK22

RSVD23

BF19

RSVD24

BH20

RSVD25

BK18

RSVD26

BJ18

RSVD27

BF23

RSVD28

BG23

RSVD29

BC23

RSVD30

BD24

RSVD31

BJ29

RSVD32

BE24

RSVD33

BH39

RSVD34

AW20

RSVD35

BK20

RSVD36

C48

RSVD37

D47

RSVD38

B44

RSVD39

C44

RSVD40

A35

RSVD41

B37

RSVD42

B36

RSVD43

B34

RSVD44

C34

RSVD45

P27

CFG_0

N27

CFG_1

N24

CFG_2

C21

CFG_3

C23

CFG_4

F23

CFG_5

N23

CFG_6

G23

CFG_7

J20

CFG_8

C20

CFG_9

R24

CFG_10

L23

CFG_11

J23

CFG_12

E23

CFG_13

E20

CFG_14

K23

CFG_15

M20

CFG_16

M24

CFG_17

L32

CFG_18

N33

CFG_19

L35

CFG_20

G41

PM_BM_BUSY#

L39

PM_DPRSTP#

L36

PM_EXT_TS#_0

J36

PM_EXT_TS#_1

AW49

PWROK

AV20

RSTIN#

N20

THERMTRIP#

G36

DPRSLPVR

BJ51

NC_1

BK51

NC_2

BK50

NC_3

BL50

NC_4

BL49

NC_5

BL3

NC_6

BL2

NC_7

BK1

NC_8

BJ1

NC_9

E1

NC_10

A5

NC_11

C51

NC_12

B50

NC_13

A50

NC_14

A49

NC_15

BK2 R32

NC_16 TEST_2

CRESTLINE_1p0

UMA@

SA00000ZWA0

2

DDR MUXINGCLKDMI

CFGRSVD

PM

GRAPHICS VIDME

NC

MISC

SM_CK_0
SM_CK_1
SM_CK_3
SM_CK_4

SM_CK#_0
SM_CK#_1
SM_CK#_3
SM_CK#_4

SM_CKE_0
SM_CKE_1
SM_CKE_3
SM_CKE_4

SM_CS#_0
SM_CS#_1
SM_CS#_2
SM_CS#_3

SM_ODT_0
SM_ODT_1
SM_ODT_2
SM_ODT_3

SM_RCOMP

SM_RCOMP#

SM_RCOMP_VOH
SM_RCOMP_VOL

SM_VREF_0
SM_VREF_1

DPLL_REF_CLK

DPLL_REF_CLK#

DPLL_REF_SSCLK

DPLL_REF_SSCLK#

PEG_CLK

PEG_CLK#

DMI_RXN_0
DMI_RXN_1
DMI_RXN_2
DMI_RXN_3

DMI_RXP_0
DMI_RXP_1
DMI_RXP_2
DMI_RXP_3

DMI_TXN_0
DMI_TXN_1
DMI_TXN_2
DMI_TXN_3

DMI_TXP_0
DMI_TXP_1
DMI_TXP_2
DMI_TXP_3

GFX_VID_0
GFX_VID_1
GFX_VID_2
GFX_VID_3

GFX_VR_EN

CL_CLK

CL_DATA

CL_PWROK

CL_RST#
CL_VREF

SDVO_CTRL_CLK

SDVO_CTRL_DATA

CLK_REQ#

ICH_SYNC#

TEST_1

Deciphered Date

2

1

For Crestline: 20ohm

M_CLK_DDR0

AV29

M_CLK_DDR1

BB23

M_CLK_DDR2

BA25

M_CLK_DDR3

AV23

M_CLK_DDR#0

AW30

M_CLK_DDR#1

BA23

M_CLK_DDR#2

AW25

M_CLK_DDR#3

AW23

DDR_CKE0_DIMMA

BE29

DDR_CKE1_DIMMA

AY32

DDR_CKE2_DIMMB

BD39

DDR_CKE3_DIMMB

BG37

DDR_CS0_DIMMA#

BG20

DDR_CS1_DIMMA#

BK16

DDR_CS2_DIMMB#

BG16

DDR_CS3_DIMMB#

BE13

M_ODT0

BH18

M_ODT1

BJ15

M_ODT2

BJ14

M_ODT3

BE16

SMRCOMP

BL15

SMRCOMP#

BK14

SMRCOMP_VOH

BK31

SMRCOMP_VOL

BL31
AR49

+DDR_MCH_REF

AW4

CLK_MCH_DREFCLK

B42

CLK_MCH_DREFCLK#

C42

MCH_SSCDREFCLK

H48

MCH_SSCDREFCLK#

H47

CLK_MCH_3GPLL

K44

CLK_MCH_3GPLL#

K45

DMI_TXN0

AN47

DMI_TXN1

AJ38

DMI_TXN2

AN42

DMI_TXN3

AN46

DMI_TXP0

AM47

DMI_TXP1

AJ39

DMI_TXP2

AN41

DMI_TXP3

AN45

DMI_RXN0

AJ46

DMI_RXN1

AJ41

DMI_RXN2

AM40

DMI_RXN3

AM44

DMI_RXP0

AJ47

DMI_RXP1

AJ42

DMI_RXP2

AM39

DMI_RXP3

AM43

E35
A39
C38
B39

GFX_VR_EN

E36

For AMT function

CL_CLK0

AM49

CL_DATA0

AK50

M_PWROK

AT43

CL_RST#

AN49

CL_VREF

AM50

H35
K36

CLKREQ_3GPLL#

G39

MCH_ICH_SYNC#

G40

A37

12

R46

20K_0402_5%

Title

CRESTLINE(1/6)-AGTL+/DMI/DDR2

Size Document Number Rev

Custom

IGT10/11 LA-3591P

Date: Sheet

For Calero: 80.6ohm

M_CLK_DDR0 (13)
M_CLK_DDR1 (13)
M_CLK_DDR2 (14)
M_CLK_DDR3 (14)

M_CLK_DDR#0 (13)
M_CLK_DDR#1 (13)
M_CLK_DDR#2 (14)
M_CLK_DDR#3 (14)

DDR_CKE0_DIMMA (13)
DDR_CKE1_DIMMA (13)
DDR_CKE2_DIMMB (14)
DDR_CKE3_DIMMB (14)

DDR_CS0_DIMMA# (13)
DDR_CS1_DIMMA# (13)
DDR_CS2_DIMMB# (14)
DDR_CS3_DIMMB# (14)

M_ODT0 (13)
M_ODT1 (13)
M_ODT2 (14)

T31 PAD

1 2

R622 0_0402_5%

T32 PAD

12

R47
0_0402_5%

M_ODT3 (14)

CLK_MCH_DREFCLK (15)
CLK_MCH_DREFCLK# (15)
MCH_SSCDREFCLK (15)
MCH_SSCDREFCLK# (15)

CLK_MCH_3GPLL (15)
CLK_MCH_3GPLL# (15)

DMI_TXN0 (20)
DMI_TXN1 (20)
DMI_TXN2 (20)
DMI_TXN3 (20)

DMI_TXP0 (20)
DMI_TXP1 (20)
DMI_TXP2 (20)
DMI_TXP3 (20)

DMI_RXN0 (20)
DMI_RXN1 (20)
DMI_RXN2 (20)
DMI_RXN3 (20)

DMI_RXP0 (20)
DMI_RXP1 (20)
DMI_RXP2 (20)
DMI_RXP3 (20)

CL_CLK0 (20)

CL_DATA0 (20)

ICH_POK

CL_RST# (20)

0.1U_0402_16V4Z

CLKREQ_3GPLL# (15)
MCH_ICH_SYNC# (20)

CLKREQ_3GPLL#

20_0402_1%

R31
R32 20_0402_1%

1

C60

2

Compal Electronics, Inc.

1

12
12

+1.25VS

R48

10K_0402_5%

748Tuesday, March 06, 2007

12

R38
1K_0402_1%

12

R41
392_0402_1%

+1.8V

+3VS

12

0.2

of

5

U3

965PM

VGA@

D D

DDR_A_D[0..63](13)

C C

B B

DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8

DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63

AR43
AW44

BA45

AY46
AR41
AR45

AT42
AW47

BB45

BF48
BG47

BJ45

BB47
BG50
BH49

BE45
AW43

BE44
BG42

BE40

BF44
BH45
BG40

BF40
AR40
AW40

AT39
AW36
AW41

AY41

AV38

AT38

AV13

AT13
AW11

AV11
AU15

AT11

BA13

BA11

BE10
BD10

BG10

AW9

AM8

AN10

AM9

AN11

BD8
AY9

BD7
BB9
BB5
AY7
AT5
AT7
AY6
BB7
AR5
AR8
AR9
AN3

AT9
AN9

U3D

SA_DQ_0
SA_DQ_1
SA_DQ_2
SA_DQ_3
SA_DQ_4
SA_DQ_5
SA_DQ_6
SA_DQ_7
SA_DQ_8
SA_DQ_9
SA_DQ_10
SA_DQ_11
SA_DQ_12
SA_DQ_13
SA_DQ_14
SA_DQ_15
SA_DQ_16
SA_DQ_17
SA_DQ_18
SA_DQ_19
SA_DQ_20
SA_DQ_21
SA_DQ_22
SA_DQ_23
SA_DQ_24
SA_DQ_25
SA_DQ_26
SA_DQ_27
SA_DQ_28
SA_DQ_29
SA_DQ_30
SA_DQ_31
SA_DQ_32
SA_DQ_33
SA_DQ_34
SA_DQ_35
SA_DQ_36
SA_DQ_37
SA_DQ_38
SA_DQ_39
SA_DQ_40
SA_DQ_41
SA_DQ_42
SA_DQ_43
SA_DQ_44
SA_DQ_45
SA_DQ_46
SA_DQ_47
SA_DQ_48
SA_DQ_49
SA_DQ_50
SA_DQ_51
SA_DQ_52
SA_DQ_53
SA_DQ_54
SA_DQ_55
SA_DQ_56
SA_DQ_57
SA_DQ_58
SA_DQ_59
SA_DQ_60
SA_DQ_61
SA_DQ_62
SA_DQ_63

CRESTLINE_1p0

UMA@

SA00000ZWA0

SA00001DJA0

DDR SYSTEM MEMORY A

SA_BS_0
SA_BS_1

SA_BS_2
SA_CAS#
SA_DM_0

SA_DM_1
SA_DM_2
SA_DM_3
SA_DM_4
SA_DM_5
SA_DM_6
SA_DM_7

SA_DQS_0
SA_DQS_1
SA_DQS_2
SA_DQS_3
SA_DQS_4
SA_DQS_5
SA_DQS_6

SA_DQS_7
SA_DQS#_0
SA_DQS#_1
SA_DQS#_2
SA_DQS#_3
SA_DQS#_4
SA_DQS#_5
SA_DQS#_6
SA_DQS#_7

SA_MA_0
SA_MA_1
SA_MA_2
SA_MA_3
SA_MA_4
SA_MA_5
SA_MA_6
SA_MA_7
SA_MA_8

SA_MA_9
SA_MA_10
SA_MA_11
SA_MA_12
SA_MA_13

SA_RAS#

SA_RCVEN#

SA_WE#

4

DDR_A_BS#0

BB19
BK19
BF29

BL17
AT45

BD44
BD42
AW38
AW13
BG8
AY5
AN6

AT46
BE48
BB43
BC37
BB16
BH6
BB2
AP3
AT47
BD47
BC41
BA37
BA16
BH7
BC1
AP2

BJ19
BD20
BK27
BH28
BL24
BK28
BJ27
BJ25
BL28
BA28
BC19
BE28
BG30
BJ16

BE18
AY20

BA19

DDR_A_BS#1
DDR_A_BS#2

DDR_A_CAS#
DDR_A_DM0

DDR_A_DM1
DDR_A_DM2
DDR_A_DM3
DDR_A_DM4
DDR_A_DM5
DDR_A_DM6
DDR_A_DM7

DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2

DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7
DDR_A_DQS#0
DDR_A_DQS#1
DDR_A_DQS#2
DDR_A_DQS#3
DDR_A_DQS#4
DDR_A_DQS#5
DDR_A_DQS#6
DDR_A_DQS#7

DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13

DDR_A_RAS#
SA_RCVEN#

DDR_A_WE#

DDR_A_BS#0 (13)
DDR_A_BS#1 (13)
DDR_A_BS#2 (13)

DDR_A_CAS# (13) DDR_B_CAS# (14)
DDR_A_DM[0..7] (13)

DDR_A_DQS[0..7] (13)

DDR_A_DQS#[0..7] (13)

DDR_A_MA[0..13] (13)

DDR_A_RAS# (13)

T16 PAD

DDR_A_WE# (13)

3

DDR_B_D[0..63](14)

DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8

DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18DDR_A_DQS3
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41

DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63

AP49
AR51
AW50
AW51
AN51
AN50

AV50

AV49

BA50

BB50

BA49

BE50

BA51

AY49

BF50

BF49

BJ50

BJ44

BJ43

BL43

BK47

BK49

BK43

BK42

BJ41

BL41

BJ37

BJ36

BK41

BJ40

BL35

BK37

BK13

BE11

BK11
BC11
BC13

BE12
BC12
BG12

BJ10

BK10

BG1
BC2
BK3
BE4
BD3

BA3
BB3
AR1
AT3
AY2
AY3
AU2
AT2

BL9
BK5
BL5
BK9

BJ8
BJ6
BF4
BH5

BJ2

2

U3E

SB_DQ_0
SB_DQ_1
SB_DQ_2
SB_DQ_3
SB_DQ_4
SB_DQ_5
SB_DQ_6
SB_DQ_7
SB_DQ_8
SB_DQ_9
SB_DQ_10
SB_DQ_11
SB_DQ_12
SB_DQ_13
SB_DQ_14
SB_DQ_15
SB_DQ_16
SB_DQ_17
SB_DQ_18
SB_DQ_19
SB_DQ_20
SB_DQ_21
SB_DQ_22
SB_DQ_23
SB_DQ_24
SB_DQ_25
SB_DQ_26
SB_DQ_27
SB_DQ_28
SB_DQ_29
SB_DQ_30
SB_DQ_31
SB_DQ_32
SB_DQ_33
SB_DQ_34
SB_DQ_35
SB_DQ_36
SB_DQ_37
SB_DQ_38
SB_DQ_39
SB_DQ_40
SB_DQ_41
SB_DQ_42
SB_DQ_43
SB_DQ_44
SB_DQ_45
SB_DQ_46
SB_DQ_47
SB_DQ_48
SB_DQ_49
SB_DQ_50
SB_DQ_51
SB_DQ_52
SB_DQ_53
SB_DQ_54
SB_DQ_55
SB_DQ_56
SB_DQ_57
SB_DQ_58
SB_DQ_59
SB_DQ_60
SB_DQ_61
SB_DQ_62
SB_DQ_63

CRESTLINE_1p0

UMA@

SA00000ZWA0

1

DDR_B_BS#0

AY17

SB_BS_0
SB_BS_1
SB_BS_2

SB_CAS#
SB_DM_0

SB_DM_1
SB_DM_2
SB_DM_3
SB_DM_4
SB_DM_5
SB_DM_6
SB_DM_7

SB_DQS_0
SB_DQS_1
SB_DQS_2
SB_DQS_3
SB_DQS_4
SB_DQS_5
SB_DQS_6

SB_DQS_7
SB_DQS#_0
SB_DQS#_1
SB_DQS#_2
SB_DQS#_3
SB_DQS#_4
SB_DQS#_5
SB_DQS#_6
SB_DQS#_7

SB_MA_0
SB_MA_1
SB_MA_2
SB_MA_3
SB_MA_4
SB_MA_5
SB_MA_6
SB_MA_7
SB_MA_8

SB_MA_9
SB_MA_10
SB_MA_11
SB_MA_12
SB_MA_13

SB_RAS#

SB_RCVEN#

SB_WE#

DDR SYSTEM MEMORY B

BG18
BG36

BE17
AR50

BD49
BK45
BL39
BH12
BJ7
BF3
AW2

AT50
BD50
BK46
BK39
BJ12
BL7
BE2
AV2
AU50
BC50
BL45
BK38
BK12
BK7
BF2
AV3

BC18
BG28
BG25
AW17
BF25
BE25
BA29
BC28
AY28
BD37
BG17
BE37
BA39
BG13

AV16
AY18

BC17

DDR_B_BS#1
DDR_B_BS#2

DDR_B_CAS#

DDR_B_DM0
DDR_B_DM1
DDR_B_DM2
DDR_B_DM3
DDR_B_DM4
DDR_B_DM5
DDR_B_DM6
DDR_B_DM7

DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4
DDR_B_DQS5
DDR_B_DQS6

DDR_B_DQS7
DDR_B_DQS#0
DDR_B_DQS#1
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS#4
DDR_B_DQS#5
DDR_B_DQS#6
DDR_B_DQS#7

DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8

DDR_B_MA9
DDR_B_MA10DDR_B_D42
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13

DDR_B_RAS#

SB_RCVEN#

DDR_B_WE#

DDR_B_BS#0 (14)
DDR_B_BS#1 (14)
DDR_B_BS#2 (14)

DDR_B_DM[0..7] (14)

DDR_B_DQS[0..7] (14)

DDR_B_DQS#[0..7] (14)

DDR_B_MA[0..13] (14)

DDR_B_RAS# (14)

T15 PAD

DDR_B_WE# (14)

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/08/04 2006/10/06

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

Compal Electronics, Inc.

CRESTLINE((2/6)-DDR2 A/B CH

IGT10/11 LA-3591P

848Tuesday, March 06, 2007

1

of

0.2

5

4

3

2

1

+3VS

12

+3VS

CRT_HSYNC
CRT_VSYNC

1 2
1 2

12

R53

2.2K_0402_5%

UMA@

R54 10K_0402_5%
R56 10K_0402_5%

EDID_CLK_LCD
EDID_DAT_LCD

GMCH_LVDDEN

R57 2.4K_0402_1%

LVDSAC­LVDSAC+

LVDSA0­LVDSA1-

LVDSA2-

LVDSA0+
LVDSA1+
LVDSA2+

TV_COMPS(16)
TV_LUMA(16)
TV_CRMA(16)

1 2

R60 2.2K_0402_5%

3VDDCCL(16)

3VDDCDA(16)

R66 39_0402_1%UMA@
R67 39_0402_1%UMA@

GMCH_ENBKL

1 2
1 2

12

LVDSAC-

LVDSAC+

LVDSA0-

LVDSA1-

LVDSA2-

LVDSA0+

LVDSA1+

LVDSA2+

TV_COMPS
TV_LUMA
TV_CRMA

CRT_B(16)
CRT_G(16)
CRT_R(16)

1 2
1 2

CRT_B
CRT_G
CRT_R

3VDDCCL
3VDDCDA
HSYNC_R

VSYNC_R

1.3K_0402_1%

For Crestline:1.3kohm
For Calero: 255ohm

3VDDCCL
3VDDCDA

2006/09/06

CFG[2:0] FSB Freq select

PEGCOMP trace width

U3C

J40

L_BKLT_CTRL

H39

L_BKLT_EN

E39

L_CTRL_CLK

E40

L_CTRL_DATA

C37

L_DDC_CLK

D35

L_DDC_DATA

K40

L_VDD_EN

L41

LVDS_IBG

L43

LVDS_VBG

N41

LVDS_VREFH

N40

LVDS_VREFL

D46

LVDSA_CLK#

C45

LVDSA_CLK

D44

LVDSB_CLK#

E42

LVDSB_CLK

G51

LVDSA_DATA#_0

E51

LVDSA_DATA#_1

F49

LVDSA_DATA#_2

G50

LVDSA_DATA_0

E50

LVDSA_DATA_1

F48

LVDSA_DATA_2

G44

LVDSB_DATA#_0

B47

LVDSB_DATA#_1

B45

LVDSB_DATA#_2

E44

LVDSB_DATA_0

A47

LVDSB_DATA_1

A45

LVDSB_DATA_2

E27

TVA_DAC

G27

TVB_DAC

K27

TVC_DAC

F27

TVA_RTN

J27

TVB_RTN

L27

TVC_RTN

M35

TV_DCONSEL_0

P33

TV_DCONSEL_1

H32

CRT_BLUE

G32

CRT_BLUE#

K29

CRT_GREEN

J29

CRT_GREEN#

F29

CRT_RED

E29

CRT_RED#

K33

CRT_DDC_CLK

G35

CRT_DDC_DATA

F33

CRT_HSYNC

C32

CRT_TVO_IREF

E33

CRT_VSYNC

12

R69

CRESTLINE_1p0

UMA@

SA00000ZWA0

LVDS

TV VGA

PEG_COMPI

PEG_COMPO

PEG_RX#_0
PEG_RX#_1
PEG_RX#_2
PEG_RX#_3
PEG_RX#_4
PEG_RX#_5
PEG_RX#_6
PEG_RX#_7
PEG_RX#_8

PEG_RX#_9
PEG_RX#_10
PEG_RX#_11
PEG_RX#_12
PEG_RX#_13
PEG_RX#_14
PEG_RX#_15

PEG_RX_0
PEG_RX_1
PEG_RX_2
PEG_RX_3
PEG_RX_4
PEG_RX_5
PEG_RX_6
PEG_RX_7
PEG_RX_8

PEG_RX_9
PEG_RX_10
PEG_RX_11
PEG_RX_12
PEG_RX_13
PEG_RX_14
PEG_RX_15

PEG_TX#_0
PEG_TX#_1
PEG_TX#_2
PEG_TX#_3
PEG_TX#_4
PEG_TX#_5
PEG_TX#_6
PEG_TX#_7
PEG_TX#_8
PEG_TX#_9

PEG_TX#_10

PCI-EXPRESS GRAPHICS

PEG_TX#_11
PEG_TX#_12
PEG_TX#_13
PEG_TX#_14
PEG_TX#_15

PEG_TX_0

PEG_TX_1

PEG_TX_2

PEG_TX_3

PEG_TX_4

PEG_TX_5

PEG_TX_6

PEG_TX_7

PEG_TX_8

PEG_TX_9
PEG_TX_10
PEG_TX_11
PEG_TX_12
PEG_TX_13
PEG_TX_14
PEG_TX_15

R598

0_0402_5%

VGA@

R61

0_0402_5%

VGA@

and spacing is 20/25 mils.

N43

PEGCOMP

M43

PEG_RXN0

J51

PEG_RXN1

L51

PEG_RXN2

N47

PEG_RXN3

T45

PEG_RXN4

T50

PEG_RXN5

U40

PEG_RXN6

Y44

PEG_RXN7

Y40

PEG_RXN8

AB51

PEG_RXN9

W49

PEG_RXN10

AD44

PEG_RXN11

AD40

PEG_RXN12

AG46

PEG_RXN13

AH49

PEG_RXN14

AG45

PEG_RXN15

AG41

PEG_RXP0

J50

PEG_RXP1

L50

PEG_RXP2

M47

PEG_RXP3

U44

PEG_RXP4

T49

PEG_RXP5

T41

PEG_RXP6

W45

PEG_RXP7

W41

PEG_RXP8

AB50

PEG_RXP9

Y48

PEG_RXP10

AC45

PEG_RXP11

AC41

PEG_RXP12

AH47

PEG_RXP13

AG49

PEG_RXP14

AH45

PEG_RXP15

AG42

PEG_TXN0

N45

PEG_TXN1

U39

PEG_TXN2

U47

PEG_TXN3

N51

PEG_TXN4

R50

PEG_TXN5

T42

PEG_TXN6

Y43

PEG_TXN7

W46

PEG_TXN8

W38

PEG_TXN9

AD39

PEG_TXN10

AC46

PEG_TXN11

AC49

PEG_TXN12

AC42

PEG_TXN13

AH39

PEG_TXN14

AE49

PEG_TXN15

AH44

PEG_TXP0

M45

PEG_TXP1

T38

PEG_TXP2

T46

PEG_TXP3

N50

PEG_TXP4

R51

PEG_TXP5

U43

PEG_TXP6

W42

PEG_TXP7

Y47

PEG_TXP8

Y39

PEG_TXP9

AC38

PEG_TXP10

AD47

PEG_TXP11

AC50

PEG_TXP12

AD43

PEG_TXP13

AG39

PEG_TXP14

AE50

PEG_TXP15

AH43

R58

0_0402_5%

VGA@

R62

0_0402_5%

VGA@

R55

24.9_0402_1%

1 2

C64 0.1U_0402_16V7KVGA@
C65 0.1U_0402_16V7KVGA@
C66 0.1U_0402_16V7KVGA@
C67 0.1U_0402_16V7KVGA@
C68 0.1U_0402_16V7KVGA@
C69 0.1U_0402_16V7KVGA@
C70 0.1U_0402_16V7KVGA@
C71 0.1U_0402_16V7KVGA@R59 150_0402_1%UMA@
C72 0.1U_0402_16V7KVGA@
C73 0.1U_0402_16V7KVGA@
C74 0.1U_0402_16V7KVGA@
C75 0.1U_0402_16V7KVGA@
C76 0.1U_0402_16V7KVGA@
C77 0.1U_0402_16V7KVGA@
C78 0.1U_0402_16V7KVGA@
C79 0.1U_0402_16V7KVGA@

C80 0.1U_0402_16V7KVGA@
C81 0.1U_0402_16V7KVGA@
C82 0.1U_0402_16V7KVGA@
C83 0.1U_0402_16V7KVGA@
C84 0.1U_0402_16V7KVGA@
C85 0.1U_0402_16V7KVGA@
C86 0.1U_0402_16V7KVGA@
C87 0.1U_0402_16V7KVGA@
C88 0.1U_0402_16V7KVGA@
C89 0.1U_0402_16V7KVGA@
C90 0.1U_0402_16V7KVGA@
C91 0.1U_0402_16V7KVGA@
C92 0.1U_0402_16V7KVGA@
C93 0.1U_0402_16V7KVGA@
C94 0.1U_0402_16V7KVGA@
C95 0.1U_0402_16V7KVGA@

R59

0_0402_5%

VGA@

R63

0_0402_5%

VGA@

+VCC_PEG

PEG_RXN[0..15] (17)

PEG_RXP[0..15] (17)

PEG_M_TXN0
PEG_M_TXN1
PEG_M_TXN2
PEG_M_TXN3
PEG_M_TXN4
PEG_M_TXN5
PEG_M_TXN6
PEG_M_TXN7
PEG_M_TXN8
PEG_M_TXN9
PEG_M_TXN10
PEG_M_TXN11
PEG_M_TXN12
PEG_M_TXN13
PEG_M_TXN14
PEG_M_TXN15

PEG_M_TXP0
PEG_M_TXP1
PEG_M_TXP2
PEG_M_TXP3
PEG_M_TXP4
PEG_M_TXP5
PEG_M_TXP6
PEG_M_TXP7
PEG_M_TXP8
PEG_M_TXP9
PEG_M_TXP10
PEG_M_TXP11
PEG_M_TXP12
PEG_M_TXP13
PEG_M_TXP14
PEG_M_TXP15

PEG_M_TXN[0..15] (17)

PEG_M_TXP[0..15] (17)

CFG5 (DMI select)

CFG7 (CPU Strap)

CFG8 (Low power PCIE)

(PCIE Graphics Lane Reversal)

CFG[13:12] (XOR/ALLZ)

CFG[15:14] Reserved

CFG16 (FSB Dynamic ODT)

SDVO_CTRLDATA

CFG19 (DMI Lane Reversal)

CFG20 (PCIE/SDVO concurrent)

R52

2.2K_0402_5%

UMA@

EDID_CLK_LCD(22)
EDID_DAT_LCD(22)

D D

For Crestline:2.4kohm
For Calero: 1.5Kohm

C C

EDID_CLK_LCD
EDID_DAT_LCD

GMCH_ENBKL(22)

GMCH_LVDDEN(22)

2006/09/13

1 2

R598 150_0402_1%UMA@

1 2

R58 150_0402_1%UMA@

1 2

2006/08/30

1 2

R61 150_0402_1%UMA@

1 2

R62 150_0402_1%UMA@

1 2

B B

A A

R63 150_0402_1%UMA@

TV_COMPS
TV_LUMA
TV_CRMA

+3VS

CRT_R
CRT_G
CRT_B

CRT_HSYNC(16)
CRT_VSYNC(16)

+3VS

R602 4.7K_0402_5%
R603 4.7K_0402_5%

Strap Pin Table

010 = FSB 800MHz
011 = FSB 667MHz
Others = Reserved

0 = DMI x 2
1 = DMI x 4

CFG6

CFG9

CFG[11:10]

CFG[18:17] Reserved

Reserved

0 = Reserved
1 = Mobile CPU

0 = Normal mode
1 = Low Power mode

0 = Reverse Lane
1 = Normal Operation

Reserved
00 = Reserved

01 = XOR Mode Enabled
10 = All Z Mode Enabled

11 = Normal Operation

0 = Disabled
1 = Enabled

0 = No SDVO Device Present
1 = SDVO Device Present

0 = Normal Operation

(Lane number in Order)

1 = Reverse Lane

0 = Only PCIE or SDVO is operational.
1 = PCIE/SDVO are operating simu.

CFG5(7)

CFG7(7)

CFG8(7)

CFG9(7)

CFG12(7)

CFG13(7)

CFG16(7)

CFG[17:3] have internal pull up
CFG[19:18] have internal pull down

CFG19(7)

CFG20(7)

*

*

*
*

(Default)

*

R64 4.02K_0402_1%@

1 2

R65 4.02K_0402_1%@

1 2

R68 4.02K_0402_1%@

1 2

R70 4.02K_0402_1%@

1 2

R71 4.02K_0402_1%@

1 2

R72 4.02K_0402_1%@

1 2

R73 4.02K_0402_1%@

1 2

R74 4.02K_0402_1%@

1 2

R75 4.02K_0402_1%@

1 2

*

*

*

*

+3VS

2006/09/18

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/08/04 2006/10/06

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

Compal Electronics, Inc.

CRESTLINE((3/6)-VGA/LVDS/ T V

IGT10/11 LA-3591P

948Tuesday, March 06, 2007

1

of

0.2

5

UMA@

UMA@

UMA@

1

2

1

2

1

2

L43

C145

C149

C163

+3VS_DAC_BG

12

0.1U_0402_16V4Z

1

C97

2

+3VS_DAC_CRT

0.1U_0402_16V4Z

1

C106

2

C123

R89

0_0603_5%

0316 add

0.1U_0402_16V4Z

1

2

UMA@

0.1U_0402_16V4Z

1

2

UMA@

0.1U_0402_16V4Z

1

2

UMA@

1

C98

2

UMA@

1

2

1

+

22U_0805_6.3V4Z

2

+1.25VS_A_SM_CK

12

C131

0_0603_5%

0_0603_5%

UMA@

0_0603_5%

UMA@

5

+3VS

BLM18PG121SN1D_0603

D D

+3VS

R80

1 2

0_0603_5%

UMA@

+1.25VS

C C

220U_D2_4VM_R15

+3VS_TVDACC

B B

0.022U_0402_16V7K

C144

UMA@

+3VS_TVDACA

0.022U_0402_16V7K

C148

UMA@

A A

+3VS_TVDACB

0.022U_0402_16V7K

C162

UMA@

0.022U_0402_16V7K

4.7U_0805_10V4Z

1

C99

2

0.022U_0402_16V7K

C107

UMA@

+3VS

0.1U_0402_16V4Z

R86

1 2

0_0805_5%

C124

1U_0402_6.3V4Z

C132

1

2

0317 change value

R93

12

UMA@

R97

12

R99

12

+3VS

1

2

R84

0_0603_5%

0317 change value

1

4.7U_0805_6.3V6K

2

22U_0805_6.3V4Z

1

2

+3VS

+3VS

+3VS

R76

0_0603_5%

C1190
10U_0805_6.3V6M

+1.8V_TXLVDS

+3VS_PEG_BG

12

C118

+1.25VS_A_SM

C125

1U_0603_10V4Z

C133

1

2

VCCSYNC

12

1

C96

2

+3VS_DAC_CRT

+1.25VS_DPLLA
+1.25VS_DPLLB

+1.25VS_HPLL
+1.25VS_MPLL

1000P_0402_50V7K
C115

1

+1.25VS_PEGPLL

2

1

2

1U_0603_10V4Z

0.1U_0402_16V4Z

C134

1

2

+1.5VS_TVDAC

+1.25VS_HPLL

+1.25VS_PEGPLL

+1.8V_LVDS

0.022U_0402_16V7K

UMA@

10U_0805_10V6K

UMA@

0.1U_0402_16V4Z

+3VS_DAC_BG

1

2

1

C126

2

+3VS_TVDACA
+3VS_TVDACB
+3VS_TVDACC

+1.5VS_QDAC

+1.5VS_QDAC

1

C146

2

+1.8V_LVDS

C160

1

2

20 mils

1

C147

2

UMA@

1U_0603_10V4Z

C161

AW18

AV19
AU19
AU18
AU17

AT22
AT21
AT19
AT18

AT17
AR17
AR16

BC29
BB29

0.1U_0402_16V4Z

0_0603_5%

UMA@

1

2

UMA@

4

U3H

J32

VCCSYNC

A33

VCCA_CRT_DAC_1

B33

VCCA_CRT_DAC_2

A30

VCCA_DAC_BG

B32

VSSA_DAC_BG

B49

VCCA_DPLLA

H49

VCCA_DPLLB

AL2

VCCA_HPLL

AM2

VCCA_MPLL

A41

VCCA_LVDS

B41

VSSA_LVDS

K50

VCCA_PEG_BG

K49

VSSA_PEG_BG

U51

VCCA_PEG_PLL

VCCA_SM_1
VCCA_SM_2
VCCA_SM_3
VCCA_SM_4
VCCA_SM_5

VCCA_SM_7
VCCA_SM_8
VCCA_SM_9
VCCA_SM_10
VCCA_SM_11
VCCA_SM_NCTF_1
VCCA_SM_NCTF_2

VCCA_SM_CK_1
VCCA_SM_CK_2

C25

VCCA_TVA_DAC_1

B25

VCCA_TVA_DAC_2

C27

VCCA_TVB_DAC_1

B27

VCCA_TVB_DAC_2

B28

VCCA_TVC_DAC_1

A28

VCCA_TVC_DAC_2

M32

VCCD_CRT

L29

VCCD_TVDAC

N28

VCCD_QDAC

AN2

VCCD_HPLL

U48

VCCD_PEG_PLL

J41

VCCD_LVDS_1

H42

VCCD_LVDS_2

CRESTLINE_1p0

UMA@

SA00000ZWA0

R96

0_0603_5%

UMA@

R100

4

3

+VCCP

330U_D2E_2.5VM_R7

U13

VTT_1

U12

VTT_2

U11

VTT_3

U9

VTT_4

U8

VTT_5

U7

VTT_6

U5

VTT_7

CRTPLLA PEGA SMTV

AXD

VCC_AXD_NCTF

POWER

AXF

VCC_SM_CK_1
VCC_SM_CK_2
VCC_SM_CK_3
VCC_SM_CK_4

SM CK

VCC_TX_LVDS

A CK A LVDS

PEG

VCC_RXR_DMI_1
VCC_RXR_DMI_2

DMI

D TV/CRTLVDS

+1.5VS

12

40 mils

1000P_0402_50V7K

C155

UMA@

12

+1.8V

U3

VTT_8

U2

VTT_9

U1

VTT_10

T13

VTT_11

T11

VTT_12

T10

VTT_13

T9

VTT

VTT_14

T7

VTT_15

T6

VTT_16

T5

VTT_17

T3

VTT_18

T2

VTT_19

R3

VTT_20

R2

VTT_21

R1

VTT_22

AT23

VCC_AXD_1

AU28

VCC_AXD_2

AU24

VCC_AXD_3

AT29

VCC_AXD_4

AT25

VCC_AXD_5

AT30

VCC_AXD_6

AR29

B23

VCC_AXF_1

B21

VCC_AXF_2

A21

VCC_AXF_3

AJ50

VCC_DMI

BK24
BK23
BJ24
BJ23

A43

C40

VCC_HV_1

B40

VCC_HV_2

HV

AD51

VCC_PEG_1

W50

VCC_PEG_2

W51

VCC_PEG_3

V49

VCC_PEG_4

V50

VCC_PEG_5

AH50
AH51

A7

VTTLF1

F2

VTTLF2

AH1

VTTLF3

VTTLF

C141

+1.8V_TXLVDS

1

220U_D2_4VM_R15

1

+

C154

UMA@

2

2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

+1.25VS_AXD

0.47U_0603_10V7K
C142

1

2

R98

0_0603_5%

UMA@

1

C104

2

C108

1U_0603_10V4Z

1

2

+V1.25VS_AXF

+1.25VS_DMI

+1.8V_SM_CK

+1.8V_TXLVDS

+VCC_PEG

20mils

0.47U_0603_10V7K
C143

1

2

12

3

4.7U_0805_10V4Z

1

+

C105

2

0316 add

0.47U_0603_10V7K

1

2

C116

C117

0.47U_0603_10V7K

1

2

+1.8V

C109

C135

2.2U_0805_16V4Z

4.7U_0805_10V4Z

1

1

C110

2

2

R83

1 2

10U_0805_10V6K

1

2

+3VS_HV

+1.25VS

0_0805_5%

0.1U_0402_16V4Z

1

2

2006/08/04 2006/10/06

Compal Secret Data

+1.25VS_DPLLB

0.1U_0402_16V4Z

+1.25VS_DMI

+1.25VS_PEGPLL

+1.25VS_DPLLA

+VCC_PEG

C1176

1

2

0316 add

Deciphered Date

C100

1

2

0.1U_0402_16V4Z

C114

1

2

0.1U_0402_16V4Z
C119

1

2

0.1U_0402_16V4Z

C127

1

2

10U_0805_10V4Z

C137

2

R78

1 2

10U_0805_10V4Z

0_0805_5%

1

C101

2

1 2

R81

0_0603_5%

BLM18PG121SN1D_0603

10U_0805_10V4Z

1

2

C128

1

2

220U_D2_4VM

1

C138

1

+

2

2

2

0316 add

+1.25VS

C120

R87

1 2

10U_0805_10V6K

0_0805_5%

0316 add

10U_0805_10V4Z

L1

04/10 stuff

2006/12/07

+1.25VS

+1.25VS

12

2006/12/07

+1.25VS

+VCCP

R90

12

0_0805_5%

+1.25VS

R92

@

12

0_0805_5%

04/10 no stuff

D3

2 1

+VCCP

CH751H-40PT_SOD323-2

+3VS

Title

Size Document Number Rev

Custom

Date: Sheet

22U_0805_6.3V4Z

1

C111

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

+VCCP_D

R94

10_0402_5%

+V1.25VS_AXF

+1.8V_SM_CK

+1.5VS_TVDAC

+1.25VS_HPLL

C129

+1.25VS_MPLL

C139

10U_0805_10V4Z

C102

1

2

22U_0805_6.3V4Z

1

C112

2

0.022U_0402_16V7K

1

C121

2

1

2

1

2

12

1

C122

2

1

C130
10U_0805_10V4Z

2

1

C140
10U_0805_10V4Z

2

R95

0_0402_5%

1U_0603_10V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

Compal Electronics, Inc.

CRESTLINE(4/6)-PWR

IGT10/11 LA-3591P

1

1 2

0_0603_5%

C103

1

2

R82

1 2

0_0805_5%

C113

1

2

R85

1 2

0_0805_5%

+1.25VS

L44

12

MBK2012121YZF_0805

+1.25VS

L45

12

MBK2012121YZF_0805

12

+3VS_HV

10 48Tuesday, March 06, 2007

1

+1.25VS

R79

+1.8V

+1.5VS

0.2

of

5

4

3

2

1

+VCCP

1

2

C170

C186

+VCCP

0.1U_0402_16V4Z

C171

1

2

10U_0805_10V4Z

C176

C177

1

2

0.1U_0402_16V4Z
C187

1

2

U3F

AB33

VCC_NCTF_1

AB36

VCC_NCTF_2

AB37

VCC_NCTF_3

AC33

VCC_NCTF_4

AC35

VCC_NCTF_5

AC36

VCC_NCTF_6

AD35

VCC_NCTF_7

AD36

VCC_NCTF_8

AF33

VCC_NCTF_9

AF36

VCC_NCTF_10

AH33

VCC_NCTF_11

AH35

VCC_NCTF_12

AH36

VCC_NCTF_13

AH37

VCC_NCTF_14

AJ33

VCC_NCTF_15

AJ35

VCC_NCTF_16

AK33

VCC_NCTF_17

AK35

VCC_NCTF_18

AK36

VCC_NCTF_19

AK37

VCC_NCTF_20

AD33

VCC_NCTF_21

AJ36

VCC_NCTF_22

AM35

VCC_NCTF_23

AL33

VCC_NCTF_24

AL35

VCC_NCTF_25

AA33

VCC_NCTF_26

AA35

VCC_NCTF_27

AA36

VCC_NCTF_28

AP35

VCC_NCTF_29

AP36

VCC_NCTF_30

AR35

VCC_NCTF_31

AR36

VCC_NCTF_32

Y32

VCC_NCTF_33

Y33

VCC_NCTF_34

Y35

VCC_NCTF_35

Y36

VCC_NCTF_36

Y37 A3

VCC_NCTF_37 VSS_SCB1

T30

VCC_NCTF_38

T34

VCC_NCTF_39

T35

VCC_NCTF_40

U29

VCC_NCTF_41

U31

VCC_NCTF_42

U32

VCC_NCTF_43

U33

VCC_NCTF_44

U35

VCC_NCTF_45

U36

VCC_NCTF_46

V32

VCC_NCTF_47

V33

VCC_NCTF_48

V36

VCC_NCTF_49

V37

VCC_NCTF_50

AL24

VCC_AXM_NCTF_1

AL26

VCC_AXM_NCTF_2

AL28

VCC_AXM_NCTF_3

AM26

VCC_AXM_NCTF_4

AM28

VCC_AXM_NCTF_5

AM29

VCC_AXM_NCTF_6

AM31

VCC_AXM_NCTF_7

AM32

VCC_AXM_NCTF_8

AM33

VCC_AXM_NCTF_9

AP29

VCC_AXM_NCTF_10

AP31

VCC_AXM_NCTF_11

AP32

VCC_AXM_NCTF_12

AP33

VCC_AXM_NCTF_13

AL29

VCC_AXM_NCTF_14

AL31

VCC_AXM_NCTF_15

AL32

VCC_AXM_NCTF_16

AR31

VCC_AXM_NCTF_17

AR32

VCC_AXM_NCTF_18

AR33

VCC_AXM_NCTF_19

CRESTLINE_1p0

UMA@

SA00000ZWA0

POWER

VSS_NCTF_1
VSS_NCTF_2
VSS_NCTF_3
VSS_NCTF_4
VSS_NCTF_5
VSS_NCTF_6
VSS_NCTF_7
VSS_NCTF_8

VSS_NCTF_9
VSS_NCTF_10
VSS_NCTF_11
VSS_NCTF_12
VSS_NCTF_13
VSS_NCTF_14
VSS_NCTF_15

VSS NCTF

VSS_NCTF_16
VSS_NCTF_17
VSS_NCTF_18
VSS_NCTF_19
VSS_NCTF_20
VSS_NCTF_21

VCC NCTF

VSS_SCB2
VSS_SCB3
VSS_SCB4
VSS_SCB5
VSS_SCB6

VSS SCBVCC AXM

VCC_AXM_1
VCC_AXM_2
VCC_AXM_3
VCC_AXM_4
VCC_AXM_5
VCC_AXM_6
VCC_AXM_7

VCC AXM NCTF

T27
T37
U24
U28
V31
V35
AA19
AB17
AB35
AD19
AD37
AF17
AF35
AK17
AM17
AM24
AP26
AP28
AR15
AR19
AR28

B2
C1
BL1
BL51
A51

AT33
AT31
AK29
AK24
AK23
AJ26
AJ23

+VCCP

330U_D2E_2.5VM_R7

+1.8V

C179

1U_0402_6.3V4Z

C172

10U_0805_10V4Z

1

C180

2

22U_0805_6.3V4Z

1

+

2

1

C181

2

10U_0805_10V4Z

C173

1

2

22U_0805_6.3V4Z

C174

1

2

+VCCP

0.1U_0402_16V4Z

1

C182

2

0.01U_0402_16V7K

1

2

R101

1 2

0_0603_5%

C175

2

1

D D

220U_D2_4VM_R15

C167

C C

B B

1

2

0.22U_0402_10V4Z

22U_0805_6.3V4Z

1

+

2

0.22U_0402_10V4Z
C183

1

2

0.22U_0402_10V4Z

C169

C168

1

C184

1

2

2

+VCCP

10U_0805_10V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
C185

1

1

2

2

1

2

0.22U_0402_10V4Z

AT35

AT34
AH28
AC32
AC31

AK32

AJ31

AJ28
AH32
AH31
AH29

AF32

AU32
AU33
AU35

AV33
AW33
AW35

AY35

BA32

BA33

BA35

BB33
BC32
BC33
BC35
BD32
BD35

BE32

BE33

BE35

BF33

BF34
BG32
BG33
BG35
BH32
BH34
BH35

BJ32

BJ33

BJ34

BK32

BK33

BK34

BK35

BL33
AU30

W13
W14

AA20

AA23

AA26

AA28

AB21

AB24

AB29
AC20
AC21
AC23
AC24
AC26
AC28
AC29
AD20
AD23
AD24
AD28

AF21

AF26

AA31
AH20
AH21
AH23
AH24
AH26
AD31

AJ20
AN14

R30

R20
T14

Y12

U3G

VCC_1
VCC_2
VCC_3
VCC_5
VCC_4
VCC_6
VCC_7
VCC_8
VCC_9
VCC_10
VCC_11
VCC_12

VCC_13

VCC_SM_1
VCC_SM_2
VCC_SM_3
VCC_SM_4
VCC_SM_5
VCC_SM_6
VCC_SM_7
VCC_SM_8
VCC_SM_9
VCC_SM_10
VCC_SM_11
VCC_SM_12
VCC_SM_13
VCC_SM_14
VCC_SM_15
VCC_SM_16
VCC_SM_17
VCC_SM_18
VCC_SM_19
VCC_SM_20
VCC_SM_21
VCC_SM_22
VCC_SM_23
VCC_SM_24
VCC_SM_25
VCC_SM_26
VCC_SM_27
VCC_SM_28
VCC_SM_29
VCC_SM_30
VCC_SM_31
VCC_SM_32
VCC_SM_33
VCC_SM_34
VCC_SM_35
VCC_SM_36

VCC_AXG_1
VCC_AXG_2
VCC_AXG_3
VCC_AXG_4
VCC_AXG_5
VCC_AXG_6
VCC_AXG_7
VCC_AXG_8
VCC_AXG_9
VCC_AXG_10
VCC_AXG_11
VCC_AXG_12
VCC_AXG_13
VCC_AXG_14
VCC_AXG_15
VCC_AXG_16
VCC_AXG_17
VCC_AXG_18
VCC_AXG_19
VCC_AXG_20
VCC_AXG_21
VCC_AXG_22
VCC_AXG_23
VCC_AXG_24
VCC_AXG_25
VCC_AXG_26
VCC_AXG_27
VCC_AXG_28
VCC_AXG_29
VCC_AXG_30
VCC_AXG_31
VCC_AXG_32
VCC_AXG_33
VCC_AXG_34

VCC CORE

POWER

VCC SMVCC GFX

VCC_AXG_NCTF_1
VCC_AXG_NCTF_2
VCC_AXG_NCTF_3
VCC_AXG_NCTF_4
VCC_AXG_NCTF_5
VCC_AXG_NCTF_6
VCC_AXG_NCTF_7
VCC_AXG_NCTF_8

VCC_AXG_NCTF_9
VCC_AXG_NCTF_10
VCC_AXG_NCTF_11
VCC_AXG_NCTF_12
VCC_AXG_NCTF_13
VCC_AXG_NCTF_14
VCC_AXG_NCTF_15
VCC_AXG_NCTF_16
VCC_AXG_NCTF_17
VCC_AXG_NCTF_18
VCC_AXG_NCTF_19
VCC_AXG_NCTF_20
VCC_AXG_NCTF_21
VCC_AXG_NCTF_22
VCC_AXG_NCTF_23
VCC_AXG_NCTF_24
VCC_AXG_NCTF_25
VCC_AXG_NCTF_26
VCC_AXG_NCTF_27
VCC_AXG_NCTF_28
VCC_AXG_NCTF_29
VCC_AXG_NCTF_30
VCC_AXG_NCTF_31
VCC_AXG_NCTF_32
VCC_AXG_NCTF_33
VCC_AXG_NCTF_34
VCC_AXG_NCTF_35
VCC_AXG_NCTF_36
VCC_AXG_NCTF_37
VCC_AXG_NCTF_38
VCC_AXG_NCTF_39
VCC_AXG_NCTF_40
VCC_AXG_NCTF_41
VCC_AXG_NCTF_42
VCC_AXG_NCTF_43
VCC_AXG_NCTF_44
VCC_AXG_NCTF_45
VCC_AXG_NCTF_46
VCC_AXG_NCTF_47
VCC_AXG_NCTF_48
VCC_AXG_NCTF_49
VCC_AXG_NCTF_50
VCC_AXG_NCTF_51
VCC_AXG_NCTF_52
VCC_AXG_NCTF_53
VCC_AXG_NCTF_54

VCC GFX NCTF

VCC_AXG_NCTF_55
VCC_AXG_NCTF_56
VCC_AXG_NCTF_57
VCC_AXG_NCTF_58
VCC_AXG_NCTF_59
VCC_AXG_NCTF_60
VCC_AXG_NCTF_61
VCC_AXG_NCTF_62
VCC_AXG_NCTF_63
VCC_AXG_NCTF_64
VCC_AXG_NCTF_65
VCC_AXG_NCTF_66
VCC_AXG_NCTF_67
VCC_AXG_NCTF_68
VCC_AXG_NCTF_69
VCC_AXG_NCTF_70
VCC_AXG_NCTF_71
VCC_AXG_NCTF_72
VCC_AXG_NCTF_73
VCC_AXG_NCTF_74
VCC_AXG_NCTF_75
VCC_AXG_NCTF_76
VCC_AXG_NCTF_77
VCC_AXG_NCTF_78
VCC_AXG_NCTF_79
VCC_AXG_NCTF_80
VCC_AXG_NCTF_81
VCC_AXG_NCTF_82
VCC_AXG_NCTF_83

VCC_SM_LF1
VCC_SM_LF2
VCC_SM_LF3
VCC_SM_LF4
VCC_SM_LF5
VCC_SM_LF6
VCC_SM_LF7

VCC SM LF

T17
T18
T19
T21
T22
T23
T25
U15
U16
U17
U19
U20
U21
U23
U26
V16
V17
V19
V20
V21
V23
V24
Y15
Y16
Y17
Y19
Y20
Y21
Y23
Y24
Y26
Y28
Y29
AA16
AA17
AB16
AB19
AC16
AC17
AC19
AD15
AD16
AD17
AF16
AF19
AH15
AH16
AH17
AH19
AJ16
AJ17
AJ19
AK16
AK19
AL16
AL17
AL19
AL20
AL21
AL23
AM15
AM16
AM19
AM20
AM21
AM23
AP15
AP16
AP17
AP19
AP20
AP21
AP23
AP24
AR20
AR21
AR23
AR24
AR26
V26
V28
V29
Y31

AW45
BC39
BE39
BD17
BD4
AW8
AT6

+VCCP

VCCSM_LF1
VCCSM_LF2
VCCSM_LF3
VCCSM_LF4
VCCSM_LF5
VCCSM_LF6
VCCSM_LF7

Check : power

0.1U_0402_16V4Z
C164

1

2

0.22U_0402_10V4Z

C189 0.1U_0402_16V4Z

C188 0.1U_0402_16V4Z

1

1

2

2

4.7U_0603_6.3V6K

C165

1

1

C166

2

2

C193 1U_0603_10V4Z

C191 0.22U_0603_10V7K

C190 0.22U_0603_10V7K

1

1

1

2

2

2

C194 1U_0603_10V4Z

C192 0.47U_0402_6.3V6K

1

1

2

2

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/08/04 2006/10/06

Compal Secret Data

Deciphered Date

CRESTLINE_1p0

UMA@

SA00000ZWA0

2

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

CRESTLINE((5/6)-PWR/GND

IGT10/11 LA-3591P

1

11 48Tuesday, March 06, 2007

of

0.2

5

U3I

A13

VSS_1

A15

VSS_2

A17

VSS_3

A24

VSS_4

AA21

VSS_5

AA24

VSS_6

AA29

VSS_7

AB20

D D

C C

B B

A A

AB23
AB26
AB28
AB31
AC10
AC13

AC39
AC43
AC47

AD21
AD26
AD29

AD41
AD45
AD49

AD50
AE10

AE14
AF20

AF23
AF24
AF31

AG38
AG43
AG47
AG50

AH40
AH41

AJ11
AJ13
AJ21
AJ24
AJ29
AJ32
AJ43
AJ45

AJ49
AK20
AK21
AK26
AK28
AK31
AK51

AM11
AM13

AM41
AM45

AN38
AN39
AN43

AP48
AP50
AR11

AR39
AR44
AR47

AT10
AT14
AT41
AT49

AU23
AU29

AU36
AU49
AU51
AV39
AV48

AW1

AW12
AW16

AC3

AD1

AD3

AD5
AD8

AE6

AG2

AH3

AH7
AH9

AM3
AM4

AN1

AN5
AN7
AP4

AR2

AR7

AU1

AU3

AL1

VSS_8
VSS_9
VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47
VSS_48
VSS_49
VSS_50
VSS_51
VSS_52
VSS_53
VSS_54
VSS_55
VSS_56
VSS_57
VSS_58
VSS_59
VSS_60
VSS_61
VSS_62
VSS_63
VSS_64
VSS_65
VSS_66
VSS_67
VSS_68
VSS_69
VSS_70
VSS_71
VSS_72
VSS_73
VSS_74
VSS_75
VSS_76
VSS_77
VSS_78
VSS_79
VSS_80
VSS_81
VSS_82
VSS_83
VSS_84
VSS_85
VSS_86
VSS_87
VSS_88
VSS_89
VSS_90
VSS_91
VSS_92
VSS_93
VSS_94
VSS_95
VSS_96
VSS_97
VSS_98
VSS_99

CRESTLINE_1p0

UMA@

SA00000ZWA0

VSS

VSS_100
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105
VSS_106
VSS_107
VSS_108
VSS_109
VSS_110
VSS_111
VSS_112
VSS_113
VSS_114
VSS_115
VSS_116
VSS_117
VSS_118
VSS_119
VSS_120
VSS_121
VSS_122
VSS_123
VSS_124
VSS_125
VSS_126
VSS_127
VSS_128
VSS_129
VSS_130
VSS_131
VSS_132
VSS_133
VSS_134
VSS_135
VSS_136
VSS_137
VSS_138
VSS_139
VSS_140
VSS_141
VSS_142
VSS_143
VSS_144
VSS_145
VSS_146
VSS_147
VSS_148
VSS_149
VSS_150
VSS_151
VSS_152
VSS_153
VSS_154
VSS_155
VSS_156
VSS_157
VSS_158
VSS_159
VSS_160
VSS_161
VSS_162
VSS_163
VSS_164
VSS_165
VSS_166
VSS_167
VSS_168
VSS_169
VSS_170
VSS_171
VSS_172
VSS_173
VSS_174
VSS_175
VSS_176
VSS_177
VSS_178
VSS_179
VSS_180
VSS_181
VSS_182
VSS_183
VSS_184
VSS_185
VSS_186
VSS_187
VSS_188
VSS_189
VSS_190
VSS_191
VSS_192
VSS_193
VSS_194
VSS_195
VSS_196
VSS_197
VSS_198

4

AW24
AW29
AW32
AW5
AW7
AY10
AY24
AY37
AY42
AY43
AY45
AY47
AY50
B10
B20
B24
B29
B30
B35
B38
B43
B46
B5
B8
BA1
BA17
BA18
BA2
BA24
BB12
BB25
BB40
BB44
BB49
BB8
BC16
BC24
BC25
BC36
BC40
BC51
BD13
BD2
BD28
BD45
BD48
BD5
BE1
BE19
BE23
BE30
BE42
BE51
BE8
BF12
BF16
BF36
BG19
BG2
BG24
BG29
BG39
BG48
BG5
BG51
BH17
BH30
BH44
BH46
BH8
BJ11
BJ13
BJ38
BJ4
BJ42
BJ46
BK15
BK17
BK25
BK29
BK36
BK40
BK44
BK6
BK8
BL11
BL13
BL19
BL22
BL37
BL47
C12
C16
C19
C28
C29
C33
C36
C41

3

U3J

C46
C50

C7
D13
D24

D3
D32
D39
D45
D49
E10
E16
E24
E28
E32
E47
F19
F36

F4
F40
F50

G1
G13
G16
G19
G24
G28
G29
G33
G42
G45
G48

G8
H24
H28

H4

H45

J11

J16

J2
J24
J28
J33
J35
J39

K12
K47

K8

L1

L17
L20
L24
L28

L3

L33

L49
M28
M42
M46
M49

M5

M50

M9
N11
N14
N17
N29
N32
N36
N39
N44
N49

N7

P19

P2

P23

P3
P50
R49
T39
T43
T47
U41
U45
U50

V2

V3

CRESTLINE_1p0

UMA@

SA00000ZWA0

VSS_199
VSS_200
VSS_201
VSS_202
VSS_203
VSS_204
VSS_205
VSS_206
VSS_207
VSS_208
VSS_209
VSS_210
VSS_211
VSS_212
VSS_213
VSS_214
VSS_215
VSS_216
VSS_217
VSS_218
VSS_219
VSS_220
VSS_221
VSS_222
VSS_223
VSS_224
VSS_225
VSS_226
VSS_227
VSS_228
VSS_229
VSS_230
VSS_231
VSS_232
VSS_233
VSS_234
VSS_235
VSS_236
VSS_237
VSS_238
VSS_239
VSS_240
VSS_241
VSS_242
VSS_243

VSS_245
VSS_246
VSS_247
VSS_248
VSS_249
VSS_250
VSS_251
VSS_252
VSS_253
VSS_254
VSS_255
VSS_256
VSS_257
VSS_258
VSS_259
VSS_260
VSS_261
VSS_262
VSS_263
VSS_264
VSS_265
VSS_266
VSS_267
VSS_268
VSS_269
VSS_270
VSS_271
VSS_272
VSS_273
VSS_274
VSS_275
VSS_276
VSS_277
VSS_278
VSS_279
VSS_280
VSS_281
VSS_282
VSS_283
VSS_284
VSS_285
VSS_286

VSS

VSS_287
VSS_288
VSS_289
VSS_290
VSS_291
VSS_292
VSS_293
VSS_294
VSS_295
VSS_296
VSS_297
VSS_298
VSS_299
VSS_300
VSS_301
VSS_302
VSS_303
VSS_304
VSS_305

VSS_306
VSS_307
VSS_308
VSS_309
VSS_310
VSS_311
VSS_312
VSS_313

W11
W39
W43
W47
W5
W7
Y13
Y2
Y41
Y45
Y49
Y5
Y50
Y11
P29
T29
T31
T33
R28

AA32
AB32
AD32
AF28
AF29
AT27
AV25
H50

2

1

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/08/04 2006/10/06

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

Compal Electronics, Inc.

CRESTLINE((6/6)-PWR/GND

IGT10/11 LA-3591P

1

12 48Tuesday, March 06, 2007

0.2

of

5

DDR_A_DQS#[0..7](8)

DDR_A_D[0..63](8)

DDR_A_DM[0..7](8)

DDR_A_DQS[0..7](8)

DDR_A_MA[0..13](8)

D D

Layout Note:
Place near JP41

+1.8V

2.2U_0805_16V4Z

2.2U_0805_16V4Z
C199

1

2

C C

B B

A A

Layout Note:
Place one cap close to every 2 pullup
resistors terminated to +0.9VS

+0.9VS

0.1U_0402_16V4Z

1

2

C208

DDR_A_CAS#
DDR_A_WE#

M_ODT1
DDR_CS1_DIMMA#

DDR_CKE1_DIMMA

DDR_A_MA10

DDR_A_MA3

DDR_A_BS#0

DDR_A_MA1
DDR_A_MA8

DDR_A_MA5

DDR_A_MA9
DDR_A_MA12

DDR_CKE0_DIMMA
DDR_A_BS#2

2.2U_0805_16V4Z

C200

C201

1

1

2

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

1

2

2

C209

RP21 56_0404_4P2R_5%

RP23 56_0404_4P2R_5%
R105
56_0402_5%

56_0404_4P2R_5%

RP30

56_0404_4P2R_5%

5

2

C210

C211

+0.9VS

1 4
2 3

1 4
2 3

1 2

RP26 56_0404_4P2R_5%

1 4
2 3

RP28

1 4
2 3

1 4
2 3

RP32 56_0404_4P2R_5%

1 4
2 3

1 4
2 3

RP3356_0404_4P2R_5%

2.2U_0805_16V4Z
C202

1

2

0.1U_0402_16V4Z

1

2

C212

1 4
2 3

1 4
2 3

1 4
2 3

1 4
2 3

RP27

RP29 56_0404_4P2R_5%

1 4
2 3

1 4
2 3

0.1U_0402_16V4Z

2.2U_0805_16V4Z
C203

1

1

2

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

2

2

C213

C214

RP22

56_0404_4P2R_5%

DDR_A_BS#1
DDR_A_RAS#

M_ODT0
DDR_A_MA13

RP24

56_0404_4P2R_5%

RP25

56_0404_4P2R_5%

DDR_CS0_DIMMA#
DDR_A_MA4

DDR_A_MA2
DDR_A_MA0

56_0404_4P2R_5%

DDR_A_MA7
DDR_A_MA6

DDR_A_MA11

DDR_A_MA14

RP3156_0404_4P2R_5%

C204

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

2

0.1U_0402_16V4Z

1

2

C215

C205

1

2

C216

0.1U_0402_16V4Z

0.1U_0402_16V4Z

4

+DDR_MCH_REF1(14)

0.1U_0402_16V4Z
C207

C206

1

1

2

2

0.1U_0402_16V4Z

1

1

2

2

C218

C217

Layout Note:
Place these resistor
closely JP3,all
trace length Max=1.5"

4

0.1U_0402_16V4Z

1

2

C219

1

+

C198
470U_D2_2.5VM_R15

2

0.1U_0402_16V4Z

1

2

C220

Layout Note:
+DDR_MCH_REF
trace width and
spacing is 20/20.

+1.8V

12

+DDR_MCH_REF1

1

C197

2

0.1U_0402_16V4Z

12

2006/08/31

EC_RX_P80_CLK EC_RX_P80_CLK_R

R102
1K_0402_1%

R103
1K_0402_1%

EC_RX_P80_CLK_R(14)

3

EC_TX_P80_DATA(14,33)

DDR_CKE0_DIMMA(7)

EC_RX_P80_CLK(14,33)

DDR_A_BS#2(8)

DDR_A_BS#0(8)

DDR_A_WE#(8)

DDR_A_CAS#(8)

DDR_CS1_DIMMA#(7)

M_ODT1(7)

1 2

R104 0_0402_5%

CLK_SMBDATA(14,15)

CLK_SMBCLK(14,15)

+1.8V

JP3

1

VREF

3

DDR_A_D4
DDR_A_D1

DDR_A_DQS#0
DDR_A_DQS0

DDR_A_D2
DDR_A_D3

DDR_A_D8
DDR_A_D14

DDR_A_DQS#1
DDR_A_DQS1

DDR_A_D9 DDR_A_D11
DDR_A_D15 DDR_A_D10

DDR_A_D16
DDR_A_D17

DDR_A_DQS#2
DDR_A_DQS2

DDR_A_D18
DDR_A_D19

DDR_A_DM3

DDR_A_D26
DDR_A_D27

DDR_CKE0_DIMMA

DDR_A_BS#2
DDR_A_MA12

DDR_A_MA9 DDR_A_MA7
DDR_A_MA8

DDR_A_MA5
DDR_A_MA3
DDR_A_MA1

DDR_A_MA10
DDR_A_BS#0
DDR_A_WE#

DDR_A_CAS#
DDR_CS1_DIMMA#

M_ODT1

DDR_A_D37
DDR_A_D36

DDR_A_DQS#4
DDR_A_DQS4

DDR_A_D38 DDR_A_D34
DDR_A_D32

DDR_A_D40
DDR_A_D44

DDR_A_DM5
DDR_A_D41

DDR_A_D46
DDR_A_D49

DDR_A_D48

DDR_A_DQS#6
DDR_A_DQS6

DDR_A_D50
DDR_A_D61 DDR_A_D57

DDR_A_D60
DDR_A_DM7
DDR_A_D59

DDR_A_D58
CLK_SMBDATA

CLK_SMBCLK

+3VS

1

C221

0.1U_0402_16V4Z

2

VSS

5

DQ0

7

DQ1

9

VSS

11

DQS0#

13

DQS0

15

VSS

17

DQ2

19

DQ3

21

VSS

23

DQ8

25

DQ9

27

VSS

29

DQS1#

31

DQS1

33

VSS

35

DQ10

37

DQ11

39

VSS

41

VSS

43

DQ16

45

DQ17

47

VSS

49

DQS2#

51

DQS2

53

VSS

55

DQ18

57

DQ19

59

VSS

61

DQ24

63

DQ25

65

VSS

67

DM3

69

NC

71

VSS

73

DQ26

75

DQ27

77

VSS

79

CKE0

81

VDD

83

NC

85

BA2

87

VDD

89

A12

91

A9

93

A8

95

VDD

97

A5

99

A3

101

A1

103

VDD

105

A10/AP

107

BA0

109

WE#

111

VDD

113

CAS#

115

NC/S1#

117

VDD

119

NC/ODT1

121

VSS

123

DQ32

125

DQ33

127

VSS

129

DQS4#

131

DQS4

133

VSS

135

DQ34

137

DQ35

139

VSS

141

DQ40

143

DQ41

145

VSS

147

DM5

149

VSS

151

DQ42

153

DQ43

155

VSS

157

DQ48

159

DQ49

161

VSS

163

NC,TEST

165

VSS

167

DQS6#

169

DQS6

171

VSS

173

DQ50

175

DQ51

177

VSS

179

DQ56

181

DQ57

183

VSS

185

DM7

187

VSS

189

DQ58

191

DQ59

193

VSS

195

SDA

197

SCL

199

VDDSPD

FOX_ASOA426-M2RN-7F

ME@

SO-DIMM A

VSS
DQ4
DQ5
VSS
DM0
VSS
DQ6
DQ7

VSS
DQ12
DQ13

VSS

DM1

VSS

CK0
CK0#

VSS
DQ14
DQ15

VSS

VSS
DQ20
DQ21

VSS

DM2

VSS
DQ22
DQ23

VSS
DQ28
DQ29

VSS

DQS3#

DQS3

VSS
DQ30
DQ31

VSS

NC/CKE1

VDD

NC/A15
NC/A14

VDD

VDD

VDD

RAS#

VDD

ODT0

NC/A13

VDD

VSS
DQ36
DQ37

VSS

DM4

VSS
DQ38
DQ39

VSS
DQ44
DQ45

VSS

DQS5#

DQS5

VSS
DQ46
DQ47

VSS
DQ52
DQ53

VSS

CK1
CK1#

VSS

DM6

VSS
DQ54
DQ55

VSS
DQ60
DQ61

VSS

DQS7#

DQS7

VSS
DQ62
DQ63

VSS

2

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

42
44
46
48
50

NC

52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90

A11

92

A7

94

A6

96
98

A4

100

A2

102

A0

104
106

BA1

108
110

S0#

112
114
116
118
120

NC

122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198

SA0

200

SA1

Top side

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/08/04 2006/10/06

Compal Secret Data

Deciphered Date

2

+1.8V

+DDR_MCH_REF1

DDR_A_D6
DDR_A_D0

DDR_A_DM0
DDR_A_D5

DDR_A_D7
DDR_A_D13

DDR_A_D12
DDR_A_DM1
M_CLK_DDR0

M_CLK_DDR#0

DDR_A_D20
DDR_A_D21

DDR_A_DM2
DDR_A_D23

DDR_A_D22
DDR_A_D28DDR_A_D29

DDR_A_D25DDR_A_D24
DDR_A_DQS#3

DDR_A_DQS3
DDR_A_D31

DDR_A_D30
DDR_CKE1_DIMMA

DDR_A_MA14
DDR_A_MA11
DDR_A_MA6
DDR_A_MA4

DDR_A_MA2
DDR_A_MA0

DDR_A_BS#1
DDR_A_RAS#
DDR_CS0_DIMMA#

M_ODT0
DDR_A_MA13

DDR_A_D33
DDR_A_D39

DDR_A_DM4
DDR_A_D35

DDR_A_D45
DDR_A_D43

DDR_A_DQS#5
DDR_A_DQS5

DDR_A_D47
DDR_A_D42

DDR_A_D52
DDR_A_D53

M_CLK_DDR1
M_CLK_DDR#1

DDR_A_DM6
DDR_A_D51DDR_A_D54

DDR_A_D55

DDR_A_D56
DDR_A_DQS#7

DDR_A_DQS7
DDR_A_D62

DDR_A_D63

12

R108

10K_0402_5%

1

2.2U_0805_16V4Z

0.1U_0402_16V4Z

C195

1

1

2

2

M_CLK_DDR0 (7)
M_CLK_DDR#0 (7)

PM_EXTTS#0 (7)

DDR_CKE1_DIMMA (7)

DDR_A_MA14 (7)

DDR_A_BS#1 (8)
DDR_A_RAS# (8)
DDR_CS0_DIMMA# (7)

M_ODT0 (7)

M_CLK_DDR1 (7)
M_CLK_DDR#1 (7)

12

R109

10K_0402_5%

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

DDRII-SODIMM SLOT1

IGT10/11 LA-3591P

+DDR_MCH_REF1 (14)

C196

1

13 48Tuesday, March 06, 2007

0.2

of

5

DDR_B_DQS#[0..7](8)

DDR_B_D[0..63](8)
DDR_B_DM[0..7](8)

DDR_B_DQS[0..7](8)

DDR_B_MA[0..13](8)

D D

C C

B B

A A

Layout Note:
Place near JP42

+1.8V

2.2U_0805_16V4Z

2.2U_0805_16V4Z

Layout Note:
Place one cap close to every 2 pullup
resistors terminated to +0.9VS

DDR_B_WE#
DDR_B_CAS#

M_ODT3

DDR_B_MA14

DDR_B_BS#0
DDR_B_MA10

DDR_B_MA1
DDR_B_MA3

DDR_B_MA9
DDR_B_MA5

DDR_CKE2_DIMMB
DDR_B_BS#2

DDR_B_MA8
DDR_B_MA12

C226

C225

1

1

2

2

0.1U_0402_16V4Z

R110

5

2.2U_0805_16V4Z

2.2U_0805_16V4Z

+0.9VS

1

2

C236

RP34 56_0404_4P2R_5%

1 4
2 3

1 4
2 3

RP36 56_0404_4P2R_5%

1 2

56_0402_5%

RP39 56_0404_4P2R_5%

1 4
2 3

RP41 56_0404_4P2R_5%

1 4
2 3

1 4
2 3

RP43 56_0404_4P2R_5%

RP45 56_0404_4P2R_5%

1 4
2 3

1 4
2 3

RP46 56_0404_4P2R_5%

C227

1

2

0.1U_0402_16V4Z

+0.9VS

C228

1

2

1

2

C238

RP35 56_0404_4P2R_5%

1 4
2 3

1 4
2 3

RP37 56_0404_4P2R_5%

RP38 56_0404_4P2R_5%

1 4
2 3

1 4
2 3

RP40 56_0404_4P2R_5%

RP42 56_0404_4P2R_5%

1 4
2 3

1 4
2 3

RP44 56_0404_4P2R_5%

2.2U_0805_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

C229

1

2

0.1U_0402_16V4Z

1

2

C239

DDR_B_MA13
M_ODT2

DDR_CS2_DIMMB#DDR_CS3_DIMMB#
DDR_B_RAS#

DDR_B_BS#1
DDR_B_MA0

DDR_B_MA4
DDR_B_MA2

DDR_B_MA7
DDR_B_MA6

DDR_B_MA11
DDR_CKE3_DIMMB

1

2

C240

0.1U_0402_16V4Z

C230

1

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

C231

1

2

0.1U_0402_16V4Z

1

1

2

2

C241

C242

4

0.1U_0402_16V4Z

C232

C233

1

1

2

2

0.1U_0402_16V4Z

1

2

C244

Layout Note:
Place these resistor
closely JP4,all
trace length Max=1.5"

4

0.1U_0402_16V4Z

1

2

C245

1

+

C224
470U_D2_2.5VM_R15

2

0.1U_0402_16V4Z

1

2

C246

3

+1.8V

JP4

1

VREF

3

DDR_B_D0
DDR_B_D1

DDR_B_DQS#0
DDR_B_DQS0

DDR_B_D2
DDR_B_D3

DDR_B_D8
DDR_B_D9

DDR_B_DQS#1
DDR_B_DQS1

DDR_B_D10
DDR_B_D11

DDR_B_D20
DDR_B_DQS#2

DDR_B_DQS2
DDR_B_D18

DDR_B_D19
DDR_B_D25

DDR_B_D28

EC_TX_P80_DATA(13,33)

DDR_CKE2_DIMMB(7)

EC_RX_P80_CLK(13,33)

DDR_B_BS#2(8)

DDR_B_BS#0(8)

DDR_B_WE#(8)

DDR_B_CAS#(8)

DDR_CS3_DIMMB#(7)

M_ODT3(7)

EC_RX_P80_CLK_R(13)

CLK_SMBDATA(13,15)

CLK_SMBCLK(13,15)

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

DDR_B_DM3

DDR_B_D30
DDR_B_D31

DDR_CKE2_DIMMB

DDR_B_BS#2
DDR_B_MA12

DDR_B_MA9
DDR_B_MA8

DDR_B_MA5
DDR_B_MA3
DDR_B_MA1

DDR_B_MA10
DDR_B_BS#0
DDR_B_WE#

DDR_B_CAS#
DDR_CS3_DIMMB#

M_ODT3
DDR_B_D32

DDR_B_D33
DDR_B_DQS#4

DDR_B_DQS4
DDR_B_D34

DDR_B_D35
DDR_B_D40

DDR_B_D41
DDR_B_DM5
DDR_B_D42

DDR_B_D43
DDR_B_D48

DDR_B_D49
EC_RX_P80_CLK_R
DDR_B_DQS#6

DDR_B_DQS6
DDR_B_D51

DDR_B_D50
DDR_B_D56

DDR_B_D61 DDR_B_D57
DDR_B_DM7
DDR_B_D58

DDR_B_D59
CLK_SMBDATA

CLK_SMBCLK

+3VS

1

C247

0.1U_0402_16V4Z

2006/08/04 2006/10/06

2

Compal Secret Data

VSS

5

DQ0

7

DQ1

9

VSS

11

DQS0#

13

DQS0

15

VSS

17

DQ2

19

DQ3

21

VSS

23

DQ8

25

DQ9

27

VSS

29

DQS1#

31

DQS1

33

VSS

35

DQ10

37

DQ11

39

VSS

41

VSS

43

DQ16

45

DQ17

47

VSS

49

DQS2#

51

DQS2

53

VSS

55

DQ18

57

DQ19

59

VSS

61

DQ24

63

DQ25

65

VSS

67

DM3

69

NC

71

VSS

73

DQ26

75

DQ27

77

VSS

79

CKE0

81

VDD

83

NC

85

BA2

87

VDD

89

A12

91

A9

93

A8

95

VDD

97

A5

99

A3

101

A1

103

VDD

105

A10/AP

107

BA0

109

WE#

111

VDD

113

CAS#

115

NC/S1#

117

VDD

119

NC/ODT1

121

VSS

123

DQ32

125

DQ33

127

VSS

129

DQS4#

131

DQS4

133

VSS

135

DQ34

137

DQ35

139

VSS

141

DQ40

143

DQ41

145

VSS

147

DM5

149

VSS

151

DQ42

153

DQ43

155

VSS

157

DQ48

159

DQ49

161

VSS

163

NC,TEST

165

VSS

167

DQS6#

169

DQS6

171

VSS

173

DQ50

175

DQ51

177

VSS

179

DQ56

181

DQ57

183

VSS

185

DM7

187

VSS

189

DQ58

191

DQ59

193

VSS

195

SDA

197

SCL

199

VDDSPD

P-TWO_A5692B-A0G16-P

ME@

SO-DIMM B

Deciphered Date

VSS
DQ4
DQ5
VSS
DM0
VSS
DQ6
DQ7

VSS
DQ12
DQ13

VSS

DM1

VSS

CK0
CK0#

VSS
DQ14
DQ15

VSS

VSS
DQ20
DQ21

VSS

DM2

VSS
DQ22
DQ23

VSS
DQ28
DQ29

VSS

DQS3#

DQS3

VSS
DQ30
DQ31

VSS

NC/CKE1

VDD

NC/A15
NC/A14

VDD

VDD

VDD

BA1

RAS#

VDD

ODT0

NC/A13

VDD

VSS
DQ36
DQ37

VSS

DM4

VSS
DQ38
DQ39

VSS
DQ44
DQ45

VSS

DQS5#

DQS5

VSS
DQ46
DQ47

VSS
DQ52
DQ53

VSS

CK1
CK1#

VSS

DM6

VSS
DQ54
DQ55

VSS
DQ60
DQ61

VSS

DQS7#

DQS7

VSS
DQ62
DQ63

VSS

SAO

SA1

2

+1.8V

+DDR_MCH_REF1

2

DDR_B_D4

4

DDR_B_D5

6
8

DDR_B_DM0

10
12

DDR_B_D6

14

DDR_B_D7

16
18

DDR_B_D12

20

DDR_B_D13

22
24

DDR_B_DM1

26
28

M_CLK_DDR2

30

M_CLK_DDR#2

32
34

DDR_B_D14

36

DDR_B_D15

38
40

42

DDR_B_D21DDR_B_D17

44

DDR_B_D16

46
48
50

NC

A11

A7
A6

A4
A2
A0

S0#

NC

2

52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200

DDR_B_DM2
DDR_B_D22

DDR_B_D23
DDR_B_D26

DDR_B_D24
DDR_B_DQS#3

DDR_B_DQS3
DDR_B_D29

DDR_B_D27
DDR_CKE3_DIMMB

DDR_B_MA14
DDR_B_MA11

DDR_B_MA7
DDR_B_MA6

DDR_B_MA4
DDR_B_MA2
DDR_B_MA0

DDR_B_BS#1
DDR_B_RAS#
DDR_CS2_DIMMB#

M_ODT2
DDR_B_MA13

DDR_B_D36
DDR_B_D37

DDR_B_DM4
DDR_B_D39

DDR_B_D38
DDR_B_D44

DDR_B_D45
DDR_B_DQS#5

DDR_B_DQS5
DDR_B_D46

DDR_B_D47
DDR_B_D52

DDR_B_D53
M_CLK_DDR3

M_CLK_DDR#3
DDR_B_DM6
DDR_B_D54

DDR_B_D55
DDR_B_D60

DDR_B_DQS#7
DDR_B_DQS7

DDR_B_D62
DDR_B_D63

1

2.2U_0805_16V4Z

1

C222

2

2006/12/07

M_CLK_DDR2 (7)
M_CLK_DDR#2 (7)

PM_EXTTS#1 (7)

DDR_CKE3_DIMMB (7)

DDR_B_MA14 (7)

DDR_B_BS#1 (8)
DDR_B_RAS# (8)
DDR_CS2_DIMMB# (7)

M_ODT2 (7)

2006/12/07

M_CLK_DDR3 (7)
M_CLK_DDR#3 (7)

R113

1 2

10K_0402_5%

12

10K_0402_5%

R114

Title

Size Document Number Rev

Date: Sheet

+3VS

Compal Electronics, Inc.

DDRII-SODIMM SLOT2

+DDR_MCH_REF1 (13)

0.1U_0402_16V4Z

1

C223

2

IGT10/11 LA-3591P

1

14 48Tuesday, March 06, 2007

0.2

of

5

PCI

SRC

CPU

CLKSEL1

1

1

FSLA

CLKSEL0

MHz

200

166

MHz

1000

100

MHz

33.30

33.3

KC FBM-L11-201209-221LMAT_0805

FSLC1FSLB

CLKSEL2

0

FSB Frequency Selet:

D D

CPU Driven

(Default)

*

Stuff

No Stuff

Stuff

667MHz

No Stuff

Stuff

800MHz

CPU_BSEL0(5)

C C

CPU_BSEL1(5)

B B

CPU_BSEL2(5)

C268 18P_0402_50V8J

A A

14.31818MHZ_16PF_DSX840GA

C269 18P_0402_50V8J

FSA

FSC

1 2

1 2

No Stuff

R120

2.2K_0402_5%

1 2

R124

0_0402_5%

1 2

R144

0_0402_5%

R159

2.2K_0402_5%

1 2

R162

0_0402_5%

Change cap from
27p to 18p

Routing the trace at least 10mil

R919 R940 R956

R914 R921 R930 R943 R954R949

R959 R930 R914

R919 R940 R956

R943R949

R959 R930 R921

R919 R940 R956

R943R949 R914

+VCCP

R119

@

56_0402_5%

1 2

1 2

12

R121

Y1

5

12

+VCCP

1 2

12

+VCCP

1 2

12

12

12

CLK_XTAL_OUT

1K_0402_5%

R126
1K_0402_5%@

R135
1K_0402_5%

1 2

R141

1K_0402_5%

R148
0_0402_5%@

R155
1K_0402_5%@

1 2

R160

1K_0402_5%

R165
0_0402_5%

CLK_XTAL_IN

FSB

@

@

R921

MCH_CLKSEL0 (7)

CLKSATAREQ#(20)

CLKREQ_3GPLL#(7)

CLK_PCI_1394(28)

CLK_PCI_LPC(33)

MCH_CLKSEL1 (7)

MCH_CLKSEL2 (7)

CLK_PCI_SIO(35)

CLK_PCI_CB(27)

CLK_PCI_ICH(18)

CLK_48M_ICH(20)

CLK_14M_ICH(20)
CLK_14M_SIO(35)

For ITP_EN, 0 =SRC8/SRC8#; 1 = ITP/ITP#
For 27_SEL, 0 = Enable DOT96 & SRC1,

1= Enable SRC0 & 27MHz

For PCI2_EN, 0 = Overclocking of CPU and SRC Allowed

1 = Overclocking of CPU and SRC NOT allowed

+3VS_CK505 +3VS_CK505 +3VS_CK505

R174
10K_0402_5%

@

1 2

ITP_EN 27_SEL

R178
10K_0402_5%

1 2

VGA@

+3VS

R175
10K_0402_5%

1 2

R179
10K_0402_5%

UMA@

1 2

4

+3VS_CK505

L36

1 2

L37

1 2

+1.25VS

KC FBM-L11-201209-221LMAT_0805

EMI

4

1 2

L46 FBM-L11-160808-601LMT_0603

1 2
1 2

1 2
1 2

1 2

1 2

1 2
1 2

1 2

PCI2_TME

1 2

1

C248
10U_0805_10V4Z

2

+1.25VS_CK505

SERP@
PCMCIA@

+1.25VS_CK505

R176
10K_0402_5%

R180
10K_0402_5%

@

R130475_0402_1%

12

R13433_0402_5% 832@
R13733_0402_5%

R13822_0402_5%
R14233_0402_5%

R14533_0402_5%

R15333_0402_5%

R15822_0402_5%
R67722_0402_5%

1

C249

0.1U_0402_16V4Z

2

+1.25VS_CK505

1

C255
10U_0805_10V4Z

2

+3VS_CK505

PCI_CLK1
PCI2_TME
PCI_CLK3

EMI

27_SEL

ITP_EN
CLK_XTAL_IN
CLK_XTAL_OUT

FSA

FSB

FSC

3

1

C250

0.1U_0402_16V4Z

2

1

C256

0.1U_0402_16V4Z

2

U5

2

VDD_PCI

9

VDD48

16

VDDPLL3

61

VDDREF

39

VDDSRC

55

VDDCPU

12

VDD96_IO

20

VDDPLL3_IO

26

VDDSRC_IO

36

VDDSRC_IO

49

VDDCPU_IO

1

PCI0/CR#_A

3

PCI1/CR#_B

4

PCI2/TME

5

PCI3

6

PCI4/27_Select

7

PCIF5/ITP_EN

60

X1

59

X2

10

USB_48MHZ/FSLA

57

FSLB/TEST MODE

62

REF0/FSLC/TEST_SEL

45

VDDSRC_IO

42

GNDSRC

8

GNDPCI

11

GND48

15

GND

19

GND

52

GNDCPU

23

GNDSRC

29

GNDSRC

58

GNDREF

* Internal Pull-Up Resistor
** Internal Pull-Down Resistor

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

1

2

SRC1/SE1/27MHz_NonSS

3

C251

0.1U_0402_16V4Z

1

C257

0.1U_0402_16V4Z

2

SRC1#/SE2/27MHz_SS

CK_PWRGD/PD#

SLG8SP510_TSSOP64

2006/08/04 2006/10/06

1

C252

0.1U_0402_16V4Z

2

1

1

C259

0.1U_0402_16V4Z

2

2

48

NC

CLK_SMBCLK

64

SCLK

CLK_SMBDATA

63

SDATA

38

PCI_STOP#

37

CPU_STOP#

CLK_CPU_BCLK

54

CPU0

CLK_CPU_BCLK#

53

CPU0#

CLK_MCH_BCLK

51

CPU1_F

CPU1#_F

SRC8/ITP

SRC8#/ITP#

SRC10#

SRC11/CR#_H

SRC11#/CR#_G

SRC7/CR#_F

SRC7#/CR#_E

SRC3/CR#_C

SRC3#/CR#_D

SRC2/SATA

SRC2#/SATA#

SRC0/DOT96

SRC0/DOT96#

SRC10

SRC9

SRC9#

SRC6

SRC6#

SRC4

SRC4#

CLK_MCH_BCLK#

50

CLK_PCIE_MCARD1

47

CLK_PCIE_MCARD1#

46

CLK_PCIE_NC1#

35

CLK_PCIE_NC1

34

CLKREQ#_H

33

CLKREQ_MCARD#R

32

CLK_PCIE_MCARD

30

CLK_PCIE_MCARD#

31

44

CLKREQ_LAN#R

43

CLK_PCIE_LAN

41

CLK_PCIE_LAN#

40

CLK_MCH_3GPLL

27

CLK_MCH_3GPLL#

28

CLK_PCIE_ICH

24

CLK_PCIE_ICH#

25

CLK_PCIE_SATA

21

CLK_PCIE_SATA#

22

R_SSCDREFCLK

17

R_SSCDREFCLK#

18

R_MCH_DREFCLK

13

R_MCH_DREFCLK#

14

56

ICS9LPRS365/SA00001GT00

Compal Secret Data

1

C253

0.1U_0402_16V4Z

2

C260

0.1U_0402_16V4Z

R139

R140

R150

R168 0_0402_5%UMA@
R169 0_0402_5%UMA@

R177 10K_0402_5%@

Deciphered Date

1 2
1 2

RP47

2 3
1 4

RP48

2 3
1 4

12

2

1

C254

0.1U_0402_16V4Z

2

1 2

R136 10K_0402_5%

475_0402_1%

12

475_0402_1%

12

1 2

R143 10K_0402_5%

475_0402_1%

12

1 2

R151 10K_0402_5%

UMA@

0_0404_4P2R_5%

0_0404_4P2R_5%

VGA@

2

1

+3VS

R116

2.2K_0402_5%

D

S

+3VS

1 3

2
2

1 3

D

Q2
2N7002_SOT23

G

G

S

Q3
2N7002_SOT23

ICH_SMBDATA(20,25,26)

ICH_SMBCLK(20,25,26)

CLK_SMBCLK (13,14)
CLK_SMBDATA (13,14)

H_STP_PCI# (20)
H_STP_CPU# (20)

CLK_CPU_BCLK (4)
CLK_CPU_BCLK# (4)

CLK_MCH_BCLK (7)
CLK_MCH_BCLK# (7)

CLK_PCIE_MCARD1 (26)
CLK_PCIE_MCARD1# (26)

CLK_PCIE_NC1# (25)
CLK_PCIE_NC1 (25)

+3VS

CLKREQ_NC1# (25)
CLKREQ_MCARD# (26)

+3VS

CLK_PCIE_MCARD (26)
CLK_PCIE_MCARD# (26)

CLKREQ_LAN# (23)

CLK_PCIE_LAN (23)
CLK_PCIE_LAN# (23)

CLK_MCH_3GPLL (7)
CLK_MCH_3GPLL# (7)

CLK_PCIE_ICH (20)
CLK_PCIE_ICH# (20)

CLK_PCIE_SATA (19)
CLK_PCIE_SATA# (19)

MCH_SSCDREFCLK (7)
MCH_SSCDREFCLK# (7)

CLK_MCH_DREFCLK (7)
CLK_MCH_DREFCLK# (7)

CLK_PCIE_VGA (17)
CLK_PCIE_VGA# (17)

CK_PWRGD (20)

+3VS_CK505

Place close to U41

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

Clock generator

IGT10/11 LA-3591P

1

R117

2.2K_0402_5%

CLK_SMBDATA

CLK_SMBCLK

15 48Tuesday, March 06, 2007

of

0.2

A

CRT CONNECTOR

1 1

2 2

3 3

CRT_R_R(17)

CRT_R(9)

CRT_G_R(17)

CRT_G(9)

CRT_B_R(17)

CRT_B(9)

CRT_HSYNC_R(17)

CRT_HSYNC(9)

CRT_VSYNC_R(17)

CRT_VSYNC(9)

1 2

R182 0_0402_5%UMA@

1 2

R184 0_0402_5%UMA@

1 2

R186 0_0402_5%UMA@

1 2

R192 0_0402_5%UMA@

1 2

R194 0_0402_5%UMA@

1 2

C280 0.1U_0402_16V4Z

0.1U_0402_16V4Z

CRT_VSYNC_R

B

CRT_R_R

CRT_G_R

CRT_B_R

12

R188

R187

150_0402_1%

+CRT_VCC

1

2 4

OE#

AY

GP

U6

SN74AHCT1G125GW_SOT353-5

3 5

1 2

C281

12

150_0402_1%

12

R189

+CRT_VCC

+3VS

1

C272

2

150_0402_1%

R190 10K_0402_5%

1

2 4

OE#

AY

GP

U7
SN74AHCT1G125GW_SOT353-5

3 5

D8

DAN217_SC59@

6P_0402_50V8K

2

C273

1

1

2

6P_0402_50V8K

12

D_CRT_HSYNCCRT_HSYNC_R

D_CRT_VSYNC

3

C274

1

2

D9

C

L2

1 2

FCM2012C-800_0805

L3

1 2

FCM2012C-800_0805

L4

1 2

FCM2012C-800_0805

6P_0402_50V8K

FCM1608C-121T_0603

1 2

1 2

FCM1608C-121T_0603

DAN217_SC59@

1

2

3

C275

@

1

2

L5

L6

Near to JP13

1

D5

DAN217_SC59

2

3

@

6P_0402_50V8K

C276

1

@

2

C282

D40

DAN217_SC59@

1

D6

DAN217_SC59

2

@

6P_0402_50V8K

HSYNC

1

2

1

2

3

3

C277

VSYNC

10P_0402_50V8J

@

C283

D7

DAN217_SC59

@

1

2

6P_0402_50V8K

1

2

D

+5VS +R_CRT_VCC +CRT_VCC

+3VS

DDCDATA(17)

DDCCLK(17)

3VDDCCL(9)

D4

2 1

CH491D_SC59

1

2

3

10P_0402_50V8J

3VDDCDA(9)

1.1A_6VDC_FUSE

0.1U_0402_16V4Z

CRT_R_L

CRT_G_L

CRT_B_L

1

C271
220P_0402_50V7K

2

+3VS

+3VS

F1

21

1

C270

2

1

C278

1

C279

2

2

68P_0402_50V8K

UMA@

1 2

R1950_0402_5%

VGA@

1 2

R609 4.7K_0402_5%

DDCDATA

VGA@

1 2

R610 4.7K_0402_5%

UMA@

1 2

R2000_0402_5%

CRT Conn.

11

12

13

14
10

15

DSUB_12_DATA
DSUB_15_CLK

68P_0402_50V8K

JP5

6
1

7
2

8
3

9

16

4

17

5

SUYIN_070549FR015S208CR

S

G

2

13

D

S

Q5
2N7002_SOT23

+3VS

G

2

13

D

Q4
2N7002_SOT23

E

+CRT_VCC

12

12

R197

4.7K_0402_5%

DSUB_12_DATA

R196

4.7K_0402_5%

DSUB_15_CLKDDCCLK

100P_0402_50V8J

1

2

TVOUT@

B

L35

1 2

FBM-11-160808-121T_0603

TVOUT@

L7

1 2

FBM-11-160808-121T_0603

TVOUT@

L8

1 2

FBM-11-160808-121T_0603

TVOUT@

C287

100P_0402_50V8J

1

C288

2

100P_0402_50V8J

TVOUT@

JP6

TV_CRMA_L

1

2

100P_0402_50V8J

TVOUT@

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C289

Issued Date

1

C647

2

100P_0402_50V8J

TVOUT@

C

2006/08/04 2006/10/06

TV_COMPS_L

TV_LUMA_L

Compal Secret Data

Deciphered Date

3
6
7
5
2
4
1
8
9

SUYIN_030107FR007SX08FU

ME@

(ECQ60)

D

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

CRT & TVout Connector

IGT10/11 LA-3591P

E

of

16 48Tuesday, March 06, 2007

0.2

12

R601

150_0402_1%

12

TVOUT@

TV_COMPS_R

TV_LUMA_R

TV_CRMA_R

1

2

150_0402_1%

TVOUT@

100P_0402_50V8J

C286

C646

TVOUT@

1

2

TV_COMPS_R(17)

TV_COMPS(9)

TV_LUMA_R(17)

TV_LUMA(9)

TV_CRMA_R(17)

TV_CRMA(9)

4 4

1 2

R600 0_0402_5%UMA@

1 2

R202 0_0402_5%UMA@

1 2

R204 0_0402_5%UMA@

R206

150_0402_1%

TVOUT@

12

R205

TVOUT@

TV-OUT Conn.

1. Y ground

2. C ground

3. Y (luminance+sync)

4. C (crominance)

A

5

4

3

2

1

PEG_M_TXP[0..15]
PEG_M_TXN[0..15]

PEG_RXP[0..15]
PEG_RXN[0..15]

PEG_M_TXP[0..15] (9)
PEG_M_TXN[0..15] (9)

PEG_RXP[0:15] (9)
PEG_RXN[0:15] (9)

MXM VGA BOARD Conn.

D D

KC FBMA-L11-321611-800LMA40T_1206

B+

C C

B B

L38

1 2

VGA@

PEG_RXN15
PEG_RXP15

PEG_RXN14
PEG_RXP14

PEG_RXN13
PEG_RXP13

PEG_RXN12
PEG_RXP12

PEG_RXN11
PEG_RXP11

PEG_RXN10
PEG_RXP10

PEG_RXN9
PEG_RXP9

PEG_RXN8
PEG_RXP8

PEG_RXN7
PEG_RXP7

PEG_RXN6
PEG_RXP6

PEG_RXN5
PEG_RXP5

PEG_RXN4
PEG_RXP4

PEG_RXN3
PEG_RXP3

PEG_RXN2
PEG_RXP2

B+_MXM

JP34A

1

PWR_SRC

3

PWR_SRC

5

PWR_SRC

7

PWR_SRC

9

PWR_SRC

11

PWR_SRC

13

PWR_SRC

15

PWR_SRC

17

GND

19

GND

21

GND

23

GND

25

PEX_RX15#

27

PEX_RX15

29

GND

31

PEX_RX14#

33

PEX_RX14

35

GND

37

PEX_RX13#

39

PEX_RX13

41

GND

43

PEX_RX12#

45

PEX_RX12

47

GND

49

PEX_RX11#

51

PEX_RX11

53

GND

55

PEX_RX10#

57

PEX_RX10

59

GND

61

PEX_RX9#

63

PEX_RX9

65

GND

67

PEX_RX8#

69

PEX_RX8

71

GND

73

PEX_RX7#

75

PEX_RX7

77

GND

79

PEX_RX6#

81

PEX_RX6

83

GND

85

PEX_RX5#

87

PEX_RX5

89

GND

91

PEX_RX4#

93

PEX_RX4

95

GND

97

PEX_RX3#

99

PEX_RX3

101

GND

103

PEX_RX2#

105

PEX_RX2

107

GND

ACES_88990-2D28_230P

ME@

1V8RUN
1V8RUN
1V8RUN
1V8RUN
1V8RUN
1V8RUN
1V8RUN

RUNPWROK

5VRUN

GND
GND
GND

PRSNT2#

PEX_TX15#

PEX_TX15

GND

PEX_TX14#

PEX_TX14

GND

PEX_TX13#

PEX_TX13

GND

PEX_TX12#

PEX_TX12

GND

PEX_TX11#

PEX_TX11

GND

PEX_TX10#

PEX_TX10

GND

PEX_TX9#

PEX_TX9

GND

PEX_TX8#

PEX_TX8

GND

PEX_TX7#

PEX_TX7

GND

PEX_TX6#

PEX_TX6

GND

PEX_TX5#

PEX_TX5

GND

PEX_TX4#

PEX_TX4

GND

PEX_TX3#

PEX_TX3

GND

PEX_TX2#

PEX_TX2

2
4
6
8
10
12
14

VGA_RUNPWROK

16
18
20
22
24

26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108

+1.8VS

+5VS

PEG_M_TXN15
PEG_M_TXP15

PEG_M_TXN14
PEG_M_TXP14

PEG_M_TXN13
PEG_M_TXP13

PEG_M_TXN12
PEG_M_TXP12

PEG_M_TXN11
PEG_M_TXP11

PEG_M_TXN10
PEG_M_TXP10

PEG_M_TXN9
PEG_M_TXP9

PEG_M_TXN8
PEG_M_TXP8

PEG_M_TXN7
PEG_M_TXP7

PEG_M_TXN6
PEG_M_TXP6

PEG_M_TXN5
PEG_M_TXP5

PEG_M_TXN4
PEG_M_TXP4

PEG_M_TXN3
PEG_M_TXP3

PEG_M_TXN2
PEG_M_TXP2

footprint update OK

R612

1 2

PEG_RXN1
PEG_RXP1

PEG_RXN0

0_0402_5%VGA@

SUSP# (25,28,29,33,35,38,44,45)

PLT_RST#(7,18,20,23,25,26)

CLK_PCIE_VGA#(15)

CLK_PCIE_VGA(15)

R237 0_0402_5%

1 2

VGA@

EC_SMB_DA2(4,33)

EC_SMB_CK2(4,33)

CRT_HSYNC_R(16)
CRT_VSYNC_R(16)

DDCCLK

DDCDATA

PEG_RXP0

CLK_PCIE_VGA#
CLK_PCIE_VGA

PLTRST_VGA#

R2120_0402_5% VGA@

12

R2100_0402_5% VGA@

12

CRT_HSYNC_R
CRT_VSYNC_R
DDCCLK
DDCDATA

JP34B

109

PEX_RX1#

111

PEX_RX1

113

GND

115

PEX_RX0#

117

PEX_RX0

119

GND

121

PEX_REFCLK#

123

PEX_REFCLK

125

CLK_REQ#

127

PEX_RST#

129

RSVD

131

RSVD

133

SMB_DAT

135

SMB_CLK

137

THERM#

139

VGA_HSYNC

141

VGA_VSYNC

143

DDCA_CLK

145

DDCA_DAT

147

IGP_UCLK#

149

IGP_UCLK

151

GND

153

RSVD

155

RSVD

157

RSVD

159

IGP_UTX2#

161

IGP_UTX2

163

GND

165

IGP_UTX1#

167

IGP_UTX1

169

GND

171

IGP_UTX0#

173

IGP_UTX0

175

GND

177

IGP_LCLK#/DVI_B_CLK#

179

IGP_LCLK/DVI_B_CLK

181

DVI_B_HPD/GND

183

RSVD

185

RSVD

187

GND

189

IGP_LTX2#/DVI_B_TX2#

191

IGP_LTX2/DVI_B_TX2

193

GND

195

IGP_LTX1#/DVI_B_TX1#

197

IGP_LTX1/DVI_B_TX1

199

GND

201

IGP_LTX0#/DVI_B_TX0#

203

IGP_LTX0/DVI_B_TX0

205

DVI_A_HPD

207

DVI_A_CLK#

209

DVI_A_CLK

211

GND

213

DVI_A_TX2#

215

DVI_A_TX2

217

GND

219

DVI_A_TX1#

221

DVI_A_TX1

223

GND

225

DVI_A_TX0#

227

DVI_A_TX0

229

GND

ACES_88990-2D28_230P

ME@

footprint update OK

PEX_TX1#

PEX_TX1

PEX_TX0#

PEX_TX0

PRSNT1#

TV_C/HDTV_Pr

TV_Y/HDTV_Y

TV_CVBS/HDTV_Pb

VGA_RED
VGA_GRN

VGA_BLU

LVDS_UCLK#

LVDS_UCLK

LVDS_UTX3#

LVDS_UTX3

LVDS_UTX2#

LVDS_UTX2

LVDS_UTX1#

LVDS_UTX1

LVDS_UTX0#

LVDS_UTX0

LVDS_LCLK#

LVDS_LCLK

LVDS_LTX3#

LVDS_LTX3

LVDS_LTX2#

LVDS_LTX2

LVDS_LTX1#

LVDS_LTX1

LVDS_LTX0#

LVDS_LTX0
DDCC_DAT

DDCC_CLK

LVDS_PPEN

LVDS_BL_BRGHT

LVDS_BLEN

DDCB_DAT

DDCB_CLK

2V5RUN
3V3RUN

3V3RUN
3V3RUN

GND

GND

GND
GND
GND
GND
GND
GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204
206
208
210
212
214
216
218
220
222
224
226
228
230

PEG_M_TXN1
PEG_M_TXP1

PEG_M_TXN0
PEG_M_TXP0

TV_CRMA_R
TV_LUMA_R
TV_COMPS_R
CRT_R_R
CRT_G_R
CRT_B_R

VGA_TXCLK­VGA_TXCLK+

VGA_TXOUT2­VGA_TXOUT2+

VGA_TXOUT1­VGA_TXOUT1+

VGA_TXOUT0­VGA_TXOUT0+

LCD_DATA
LCD_CLK
VGA_ENVDD

VGA_ENBKL

2006/10/14

+2.5VS

+3VS

TV_CRMA_R
TV_LUMA_R

TV_COMPS_R
CRT_R_R (16)
CRT_G_R (16)
CRT_B_R (16)

VGA_TXCLK- (22)
VGA_TXCLK+ (22)

VGA_TXOUT2- (22)
VGA_TXOUT2+ (22)

VGA_TXOUT1- (22)
VGA_TXOUT1+ (22)

VGA_TXOUT0- (22)
VGA_TXOUT0+ (22)

LCD_DATA (22)
LCD_CLK (22)
VGA_ENVDD (22)

VGA_ENBKL (22)

2006/09/13

+5VSB+ +1.8VS +2.5VS+3VS

2

C652

VGA@

1

A A

0.1U_0603_25V7K

5

C653

4.7U_0805_10V4ZVGA@

1

2

C654

2

VGA@

0.1U_0402_16V4Z

1

1

2

1

C656

2

VGA@

0.1U_0402_16V4Z

C655

4.7U_0805_10V4ZVGA@

4

1

C657

0.1U_0402_16V4Z

2

VGA@

1

C658

2

VGA@

0.1U_0402_16V4Z

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/08/04 2006/10/06

Compal Secret Data

Deciphered Date

2

Title

Size Document Number Rev

Custom
Date: Sheet

Compal Electronics, Inc.

MXM CONN

IGT10/11 LA-3591P

1

17 48Tuesday, March 06, 2007

of

0.2

5

+3VS

PCI_GNT3#

PCI_DEVSEL#
PCI_STOP#
PCI_TRDY#
PCI_FRAME#

PCI_PLOCK#
PCI_IRDY#
PCI_SERR#
PCI_PERR#

PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#
PCI_PIRQE#
PCI_PIRQF#
PCI_PIRQG#
PCI_PIRQH#

PCI_REQ0#
PCI_REQ1#
PCI_REQ2#
PCI_REQ3#

12

R277

@

1K_0402_5%

PCI_AD[0..31](27,28)

1 2

R256 8.2K_0402_5%

1 2
1 2
1 2

1 2
1 2
1 2
1 2

1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2

1 2
1 2
1 2
1 2

D D

C C

B B

R257 8.2K_0402_5%
R258 8.2K_0402_5%
R259 8.2K_0402_5%

R260 8.2K_0402_5%
R261 8.2K_0402_5%
R262 8.2K_0402_5%
R263 8.2K_0402_5%

+3VS

R264 8.2K_0402_5%
R265 8.2K_0402_5%
R266 8.2K_0402_5%
R268 8.2K_0402_5%
R269 8.2K_0402_5%
R270 8.2K_0402_5%
R271 8.2K_0402_5%
R272 8.2K_0402_5%

R273 8.2K_0402_5%
R274 8.2K_0402_5%
R275 8.2K_0402_5%
R276 8.2K_0402_5%

A16 swap override Strap

Low= A16 swap override Enble

PCI_GNT3#

A A

High= Default

Place closely pin B10

CLK_PCI_ICH

R283

10_0402_5%@

1 2
1

C296

8.2P_0402_50V@

2

*

4

PCI_AD0
PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD6
PCI_AD7
PCI_AD8
PCI_AD9
PCI_AD10
PCI_AD11
PCI_AD12
PCI_AD13
PCI_AD14
PCI_AD15
PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20
PCI_AD21
PCI_AD22
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30
PCI_AD31

PCI_PIRQA#
PCI_PIRQB#

PCI_PIRQC#(27)

PCI_PIRQC#
PCI_PIRQD#

Boot BIOS Strap

PCI_GNT0# SPI_CS#1

0

1

1

12

R280

1K_0402_5%@

1

0

1

3

U8B

D20

AD0

E19

AD1

D19

AD2

A20

AD3

D17

AD4

A21

AD5

A19

AD6

C19

AD7

A18

AD8

B16

AD9

A12

AD10

E16

AD11

A14

AD12

G16

AD13

A15

AD14

B6

AD15

C11

AD16

A9

AD17

D11

AD18

B12

AD19

C12

AD20

D10

AD21

C7

AD22

F13

AD23

E11

AD24

E13

AD25

E12

AD26

D8

AD27

A6

AD28

E8

AD29

D6

AD30

A3

AD31

Interrupt I/F

F9

PIRQA#

B5

PIRQB#

C5

PIRQC#

A10 B3

PIRQD# PIRQH#/GPIO5

ICH8M REV 1.0

SA00001JU30

PCI

REQ0#

GNT0#
REQ1#/GPIO50
GNT1#/GPIO51
REQ2#/GPIO52
GNT2#/GPIO53
REQ3#/GPIO54
GNT3#/GPIO55

C/BE0#
C/BE1#
C/BE2#
C/BE3#

IRDY#

PAR

PCIRST#

DEVSEL#

PERR#

PLOCK#

SERR#
STOP#
TRDY#

FRAME#

PLTRST#

PCICLK

PME#

PIRQE#/GPIO2
PIRQF#/GPIO3

PIRQG#/GPIO4

Boot BIOS Locatio n

SPI

PCI

LPC

*

SB_SPI_CS#1(20)

SB_SPI_CS#1PCI_GNT0#

12

PCI_REQ0#

A4

PCI_GNT0#

D7

PCI_REQ1#

E18

PCI_GNT1#

C18

PCI_REQ2#

B19

PCI_GNT2#

F18

PCI_REQ3#

A11

PCI_GNT3#

C10

PCI_CBE#0

C17

PCI_CBE#1

E15

PCI_CBE#2

F16

PCI_CBE#3

E17

PCI_IRDY#

C8

PCI_PAR

D9

PCI_PCIRST#

G6

PCI_DEVSEL#

D16

PCI_PERR#

A7

PCI_PLOCK#

B7

PCI_SERR#

F10

PCI_STOP#

C16

PCI_TRDY#

C9

PCI_FRAME#

A17

PCI_PLTRST#

AG24

CLK_PCI_ICH

B10

PCI_PME#

G7

1 2

R267 8.2K_0402_5%

PCI_PIRQE#

F8

PCI_PIRQF#

G11

PCI_PIRQG#

F12

PCI_PIRQH#

R281

1K_0402_5%@

PCI_REQ0# (28)
PCI_GNT0# (28)

PCI_REQ2# (27)
PCI_GNT2# (27)

PCI_CBE#0 (27,28)
PCI_CBE#1 (27,28)
PCI_CBE#2 (27,28)
PCI_CBE#3 (27,28)

PCI_IRDY# (27,28)
PCI_PAR (27,28)

PCI_DEVSEL# (27,28)
PCI_PERR# (27,28)

PCI_SERR# (27,28)
PCI_STOP# (27,28)
PCI_TRDY# (27,28)
PCI_FRAME# (27,28)

CLK_PCI_ICH (15)
PCI_PME# (33)

+3VALW

PCI_PIRQE# (27)
PCI_PIRQG# (28)

PCI_PIRQH# (28)

PCI_PCIRST#

PCI_PLTRST#

2

R279
0_0402_5%

R284
0_0402_5%

1

+3VALW

53

U9

1

PG

B

2

A

12

+3VALW

53

1

B

2

A

12

PCI_RST#

4

Y

TC7SH08FU_SSOP5@

U10

PG

PLT_RST#

4

Y

TC7SH08FU_SSOP5@

12

12

PCI_RST# (27,28,33,35)

R278
100K_0402_5%

PLT_RST# (7,17,20,23,25,26)

R282
100K_0402_5%

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/08/04 2006/10/06

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

2

Date: Sheet

Compal Electronics, Inc.

ICH8(1/4)-PCI/INT

IGT10/11 LA-3591P

18 48Tuesday, March 06, 2007

1

0.2

of

5

4

3

2

1

ICH8M Internal VR Enable Strap
(Internal VR for VccSus1.05, VccSus1.5, VccCL1.5)

LAN100_SLP

ICH_INTVRMEN

+RTCVCC

D D

R287 330K_0402_1%

1 2

R290 1M_0402_5%

1 2

R291 330K_0402_1%

1 2

C C

B B

Low = Internal VR Disabled
High = Internal VR Enabled (De fa ul t)

LAN100_SLP

SM_INTRUDER#

ICH_INTVRMEN

TO MDC

C297 15P_0402_50V8J

32.768KHZ_12.5P_1TJS125BJ2A251

C298 15P_0402_50V8J

+RTCVCC

+3VS

PSATA_ITX_DRX_N0(25)

PSATA_ITX_DRX_P0(25)

1 2

R293 20K_0402_5%

1U_0603_10V4Z

HDA_BITCLK_MDC(26)
HDA_SYNC_MDC(26)

HDA_RST_MDC#(26)

HDA_SDIN0(29)
HDA_SDIN1(26)

HDA_SDOUT_MDC(26)

Y2

2

NC

3

NC

2

C299

1

SATA_LED#

R30410K_0402_5%

12

PSATA_ITX_DRX_N0

PSATA_ITX_DRX_P0

ICH_RTCX1

1

IN

4

OUT

ICH_RTCX2

CLRP1

JOPEN

1 2

@

R296 24.9_0402_1%

EMI

PSATA_IRX_DTX_N0_C(25)
PSATA_IRX_DTX_P0_C(25)

1 2

1 2

1 2
1 2

1 2

1 2

1 2

SATA_LED#(37)

PSATA_ITX_DRX_N0_C

PSATA_ITX_DRX_P0_C

CLK_PCIE_SATA#(15)
CLK_PCIE_SATA(15)

+1.5VS

R298 47_0402_5%
R300 33_0402_5%

R301 33_0402_5%

R303 33_0402_5%

C301 3900P_0402_50V7K

C302 3900P_0402_50V7K

KILL_MDC#(26)
IDERST_CD#(25)

12

R288
10M_0402_5%

ICH_RTCRST#

ICH_INTVRMEN
LAN100_SLP

GLAN_COMP

HDA_BITCLK_R
HDA_SYNC_R

HDA_RST_R#

ICH_AC_SDIN0
ICH_AC_SDIN1

HDA_SDOUT_R

KILL_MDC#
IDERST_CD#

SATA_LED#

PSATA_IRX_DTX_N0_C
PSATA_IRX_DTX_P0_C
PSATA_ITX_DRX_N0_C
PSATA_ITX_DRX_P0_C

CLK_PCIE_SATA#
CLK_PCIE_SATA

R307

1 2

24.9_0402_1%

Within 500 mils

U8A

AG25

RTCX1

AF24

RTCX2

AF23

RTCRST#

AD22

INTRUDER#

AF25

INTVRMEN

AD21

LAN100_SLP

B24

GLAN_CLK

D22

LAN_RSTSYNC

C21

LAN_RXD0

B21

LAN_RXD1

C22

LAN_RXD2

D21

LAN_TXD0

E20

LAN_TXD1

C20

LAN_TXD2

AH21

GLAN_DOCK#/GPIO13

D25

GLAN_COMPI

C25

GLAN_COMPO

AJ16

HDA_BIT_CLK

AJ15

HDA_SYNC

AE14

HDA_RST#

AJ17

HDA_SDIN0

AH17

HDA_SDIN1

AH15

HDA_SDIN2

AD13

HDA_SDIN3

AE13

HDA_SDOUT

AE10

HDA_DOCK_EN#/GPIO33

AG14

HDA_DOCK_RST#/GPIO34

AF10

SATALED#

AF6

SATA0RXN

AF5

SATA0RXP

AH5

SATA0TXN

AH6

SATA0TXP

AG3

SATA1RXN

AG4

SATA1RXP

AJ4

SATA1TXN

AJ3

SATA1TXP

AF2

SATA2RXN

AF1

SATA2RXP

AE4

SATA2TXN

AE3

SATA2TXP

AB7

SATA_CLKN

AC6

SATA_CLKP

AG1

SATARBIAS#

AG2

SATARBIAS

ICH8M REV 1.0

FWH0/LAD0
FWH1/LAD1
FWH2/LAD2
FWH3/LAD3

FWH4/LFRAME#

LDRQ1#/GPIO23

RTCLAN / GLANIHDASATA

CPUPWRGD/GPIO49

THRMTRIP#

IDE LPCCPU

LDRQ0#

A20GATE

A20M#

DPRSTP#

DPSLP#

FERR#

IGNNE#

INIT#

INTR

RCIN#

SMI#

STPCLK#

DD10
DD11
DD12
DD13
DD14
DD15

DCS1#
DCS3#

DIOR#

DIOW#

DDACK#

IDEIRQ

IORDY

DDREQ

NMI

TP8
DD0

DD1
DD2
DD3
DD4
DD5
DD6
DD7
DD8
DD9

DA0
DA1
DA2

E5
F5
G8
F6

C4
G9

E6
AF13

AG26
AF26

AE26
AD24
AG29
AF27
AE24

AC20
AH14

AD23
AG28

AA24
AE27
AA23
V1

U2
V3
T1
V4
T5
AB2
T6
T3
R2
T4
V6
V5
U1
V2
U6

AA4
AA1
AB3

Y6
Y5

W4
W3
Y2
Y3
Y1
W5

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3

LPC_FRAME#
LPC_DRQ0#

GATEA20
H_A20M#

H_FERR#
H_PWRGOOD
H_IGNNE#
H_INIT#

H_INTR
KB_RST#

H_NMI
H_SMI#

H_STPCLK#
THRMTRIP_ICH#

PD_D0
PD_D1
PD_D2
PD_D3
PD_D4
PD_D5
PD_D6
PD_D7
PD_D8
PD_D9
PD_D10
PD_D11
PD_D12
PD_D13
PD_D14
PD_D15

PD_A0
PD_A1
PD_A2

PD_CS#1
PD_CS#3

PD_IOR#
PD_IOW#
PD_DACK#
PD_IRQ
PD_IORDY
PD_DREQ

LPC_AD[0..3] (33,35)

LPC_FRAME# (33,35)
LPC_DRQ#0 (35)

GATEA20 (33)
H_A20M# (4)

H_DPRSTP#H_DPRSTP_R#

12

R295 0_0402_5%

H_DPSLP# (5)

H_FERR# (4)

H_PWRGOOD (5)
H_IGNNE# (4)
H_INIT# (4)

H_INTR (4)

KB_RST# (33)

H_NMI (4)
H_SMI# (4)

H_STPCLK# (4)
1 2

PD_D[0..15] (25)

PD_A0 (25)
PD_A1 (25)
PD_A2 (25)

PD_CS#1 (25)
PD_CS#3 (25)

PD_IOR# (25)
PD_IOW# (25)
PD_DACK# (25)
PD_IRQ (25)
PD_IORDY (25)
PD_DREQ (25)

H_DPRSTP# (5,7,46)

R302 24_0402_1%

placed within 2" from ICH8M

GATEA20

KB_RST#

H_FERR#

H_DPRSTP#

H_DPSLP#SM_INTRUDER#

within 2" from R1557

+VCCP

12

R299
56_0402_5%

R305 4.7K_0402_5%

PD_IORDY
PD_IRQ

R306 8.2K_0402_5%

10K_0402_5%

10K_0402_5%

1 2
1 2

+3VS

R285

12

R286

12

+VCCP

R289

12

56_0402_5%

R292

@

12

56_0402_5%

R294

@

12

56_0402_5%

H_THERMTRIP# (4,7)

+3VS

XOR CHAIN ENTRANCE STRAP:RSVD

+3VS

R308

A A

HDA_SDOUT_AUDIO

12

1K_0402_5%@

5

TO CODEC

HDA_SDOUT_AUDIO(29)

HDA_SYNC_AUDIO(29)

HDA_RST_AUDIO#(29)

HDA_BITCLK_AUDIO(29)

Close to ICH

1 2

R309 33_0402_5%

1 2

R311 33_0402_5%

1 2

R312 33_0402_5%

EMI

1 2

R313 47_0402_5%

4

HDA_SDOUT_R

HDA_SYNC_R

HDA_RST_R#

HDA_BITCLK_R

+RTCVCC

R310

1 2

100_0603_1%

2

C303

0.1U_0402_16V4Z

1

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/08/04 2006/10/06

Compal Secret Data

Deciphered Date

2

BATT1.1

W=20mils

D12

21

RB751V_SOD323

BATT1

+-

1 2

ML1220T13RE

+CHGRTC

45@

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

ICH8(2/4)_LAN,HD,IDE,LPC

IGT10/11 LA-3591P

1

0.2

of

19 48Tuesday, March 06, 2007

5

SIRQ

+3VS

D D

+3VALW

C C

B B

+3VALW

A A

1 2

R314 10K_0402_5%

R315 8.2K_0402_5%

R319 10K_0402_5%

@

1 2

R324 8.2K_0402_5%

1 2

R325 10K_0402_5%

R326 10K_0402_5%

R623 100K_0402_5%

R331 10K_0402_5%

R334 10K_0402_5%

R335 10K_0402_5%

R336 10K_0402_5%

R340 10K_0402_5%

R342 10K_0402_5%

R343 1K_0402_5%

R345 8.2K_0402_5%

R347 100K_0402_5%

R348 1K_0402_5%@

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

CLK_ENABLE#(46)

PCI_CLKRUN#

VGA_THER_ALERT#

EC_THERM#

CLKSATAREQ#

H_PROCHOT#

GPIO6

GPIO39

GPIO48

LINKALERT#

CL_RST#

XDP_DBRESET#

EC_SWI#

ICH_PCIE_WAKE#

ICH_LOW_BAT#

12

DPRSLPVR

ICH_RSVD

12

MINI CARD2

WLAN

NEW CARD

LAN

RP13

USB_OC#6

18

CPUSB#

27

USB_OC#2

36

USB_OC#4

45

10K_1206_8P4R_5%

RP14

MINI_ON#

45

USB_OC#5

36

USB_OC#9

27

USB_OC#0

18

10K_1206_8P4R_5%

USB_OC#8

12

R361 10K_0402_5%
R362 10K_0402_5%

USB_OC#3

12

5

V

2

G

10K_0402_5%

H_STP_PCI#(15)
H_STP_CPU#(15)

+3VS

R349

1 2

R352 0_0402_5%@

13

D

S

PCIE_RXN1(26)

PCIE_RXN2(26)

PCIE_RXN3(25)

PCIE_RXN4(23)

+3VALW

R322

330_0402_5%@

1 2

Q9

RHU002N06_SOT323@

PCIE_RXP1(26)
PCIE_TXN1(26)
PCIE_TXP1(26)

PCIE_RXP2(26)
PCIE_TXN2(26)
PCIE_TXP2(26)

PCIE_RXP3(25)
PCIE_TXN3(25)
PCIE_TXP3(25)

PCIE_RXP4(23)
PCIE_TXN4(23)
PCIE_TXP4(23)

1 2

0320 add

+3VS

10K_0402_5%

ACIN(33,39)

R323
10K_0402_5%

1 2

R329

@

R328

10K_0402_5%

1 2

1 2

2006/12/07

H_PROCHOT#(4,46)

ACIN

CH751H-40_SC76

VRMPWRGD

SB_SPI_CS#1(18)

4

+3VALW

2.2K_0402_5%

ICH_SMBCLK(15,25,26)

ICH_SMBDATA(15,25,26)

EC_SWI#(33)

XDP_DBRESET#(4)
PM_BMBUSY#(7)

EC_LID_OUT#(33)

R332 0_0402_5%

PCI_CLKRUN#(27,28,33,35)

ICH_PCIE_WAKE#(23,25,26)

EC_THERM#(4,33)

VGATE(7,46)

D43

21

SB_INT_FLASH_SEL#

CLKSATAREQ#(15)

VGA_THER_ALERT#

MCH_ICH_SYNC#(7)

1 2

+3VS

R354 10K_0402_5%@

MINI1@

C3090.1U_0402_16V7K
C3100.1U_0402_16V7K

MINI1@
MINI2@

C3110.1U_0402_16V7K
C3120.1U_0402_16V7K

MINI2@

C3130.1U_0402_16V7K
C3140.1U_0402_16V7K

C3150.1U_0402_16V7K
C3160.1U_0402_16V7K

USB_OC#0(31)

MINI_ON#(26)

USB_OC#2(31)
USB_OC#4
USB_OC#6(31)

CPUSB#(25)

USB_OC#8

4

12

12

0316 change design

R317

R316

2.2K_0402_5%

ICH_SMBCLK
ICH_SMBDATA
LINKALERT#
ME__EC_CLK1
ME__EC_DATA1

EC_SWI#

T33

PAD

XDP_DBRESET#
PM_BMBUSY#

1 2

R330 0_0402_5%

H_STP_PCI#

SIRQ(27,28,33,35)

1 2

T19 PAD

H_PROCHOT#

T20PAD

SB_SPKR

R_STP_CPU#
PCI_CLKRUN#

ICH_PCIE_WAKE#

SIRQ
EC_THERM#

VRMPWRGD
SST_CTL

EC_SMI#
EC_SCI#

CLKSATAREQ#
GPIO39

GPIO48
SB_SPKR
MCH_ICH_SYNC#
ICH_RSVD

P27
P26
N29
N28

M27
M26

L29
L28

K27
K26

J29
J28

H27
H26
G29
G28

F27

F26
E29
E28

D27
D26
C29
C28

C23
B23
E22

D23

F21

AJ19
AG16
AG15
AE15
AF15
AG17
AD12

AJ18
AD14
AH18

12

R337 0_0402_5%

EC_SMI#(33)
EC_SCI#(33)

SB_SPKR(29)

PCIE_RXN1
PCIE_RXP1
PCIE_C_TXN1
PCIE_C_TXP1

PCIE_RXN2
PCIE_RXP2
PCIE_C_TXN2
PCIE_C_TXP2

PCIE_RXN3
PCIE_RXP3
PCIE_C_TXN3
PCIE_C_TXP3

PCIE_RXN4
PCIE_RXP4
PCIE_C_TXN4
PCIE_C_TXP4

SB_SPI_CS#1

USB_OC#0
MINI_ON#
USB_OC#2
USB_OC#3
USB_OC#4
USB_OC#5
USB_OC#6
CPUSB#
USB_OC#8
USB_OC#9

AJ26
AD19
AG21
AC17
AE19

AF17

F4

AD15
AG12
AG22
AE20

AG18
AH11
AE17

AF12
AC13

AJ20

AJ22

AJ8

GPIO6

AJ9

AH9
AE16
AC19

AG8
AH12
AE11
AG10
AH25
AD16
AG13

AF9

AJ11

AD10

AD9

AJ13
AJ21

low-->default
High -->No boot

U8D

PERN1
PERP1
PETN1
PETP1

PERN2
PERP2
PETN2
PETP2

PERN3
PERP3
PETN3
PETP3

PERN4
PERP4
PETN4
PETP4

PERN5
PERP5
PETN5
PETP5

PERN6/GLAN_RXN
PERP6/GLAN_RXP
PETN6/GLAN_TXN
PETP6/GLAN_TXP

SPI_CLK
SPI_CS0#
SPI_CS1#

SPI_MOSI
SPI_MISO

OC0#
OC1#/GPIO40
OC2#/GPIO41
OC3#/GPIO42
OC4#/GPIO43
OC5#/GPIO29
OC6#/GPIO30
OC7#/GPIO31
OC8#
OC9#

ICH8M REV 1.0

USB

U8C

SMBCLK
SMBDATA
LINKALERT#
SMLINK0
SMLINK1

RI#
SUS_STAT#/LPCPD#

SYS_RESET#
BMBUSY#/GPIO0
SMBALERT#/GPIO11
STP_PCI#/GPIO15

STP_CPU#/GPIO25
CLKRUN#/GPIO32
WAKE#

SERIRQ
THRM#

VRMPWRGD
TP7
TACH1/GPIO1

TACH2/GPIO6
TACH3/GPIO7
GPIO8
GPIO12
TACH0/GPIO17
GPIO18
GPIO20
SCLOCK/GPIO22
QRT_STATE0/GPIO27
QRT_STATE1/GPIO28
SATACLKREQ#/GPIO35
SLOAD/GPIO38
SDATAOUT0/GPIO39
SDATAOUT1/GPIO48

SPKR
MCH_SYNC#
TP3

ICH8M REV 1.0

3

SATA0GP/GPIO21
SATA1GP/GPIO19
SATA2GP/GPIO36

SATA

GPIO

SATA3GP/GPIO37

SMB

Clocks

S4_STATE#/GPIO26

SYS

GPIO

DPRSLPVR/GPIO16

PWRBTN#

LAN_RST#

Power MGTController Link

CK_PWRGD

CLPWROK

CL_DATA0

GPIO

MISC

CL_DATA1
CL_VREF0

CL_VREF1

MEM_LED/GPIO24
ME_EC_ALERT/GPIO10
EC_ME_ALERT/GPIO14

WOL_EN/GPIO9

CLK14

CLK48
SUSCLK
SLP_S3#

SLP_S4#
SLP_S5#

PWROK

BATLOW#

RSMRST#

SLP_M#

CL_CLK0
CL_CLK1

CL_RST#

+3VS

R318

8.2K_0402_5%

AJ12
AJ10
AF11
AG11

AG9
G5

D3
AG23

AF21
AD18

AH27
AE23
AJ14
AE21
C2
AH20
AG27
E1
E3
AJ25
F23

AE18
F22

AF19
D24

AH23
AJ23
AJ27

AJ24
AF22
AG19

1 2

CLK_14M_ICH
CLK_48M_ICH

ICH_SUSCLK
SLP_S3#

SLP_S4#
PM_SLP_S5#

ICH_POK
DPRSLPVR
ICH_LOW_BAT#
PBTN_OUT#

@

1 2

R3380_0402_5%

EC_RSMRST#R
CK_PWRGD_R CK_PWRGD

CL_CLK0

CL_DATA0

CL_VREF0_ICH
CL_VREF1_ICH

CL_RST#
EC_FLASH#

R341 0_0402_5%

1 2

R624 0_0402_5%

CLK_14M_ICH (15)
CLK_48M_ICH (15)

T18 PAD

SLP_S3# (33)
SLP_S4# (33)

PM_SLP_S5# (33)

ICH_POK (7,33)

DPRSLPVR (7,46)

PBTN_OUT# (33)

R680

12

8.2K_0402_5%

1 2

ICH_POKCLPWROK

CL_CLK0 (7)

CL_DATA0 (7)

CL_RST# (7)

EC_FLASH#

2

1 2

2006/09/20

DMI_RXN0

V27

DMI0RXN
DMI0RXP

DMI0TXN
DMI0TXP

DMI1RXN
DMI1RXP

DMI1TXN
DMI1TXP

DMI2RXN
DMI2RXP

DMI2TXN
DMI2TXP

DMI3RXN
DMI3RXP

DMI3TXN
DMI3TXP

PCI-Express

DMI_CLKN
DMI_CLKP

DMI_ZCOMP

DMI_IRCOMP

Direct Media Interface

USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4N

SPI

USBP4P
USBP5N
USBP5P
USBP6N
USBP6P
USBP7N
USBP7P
USBP8N
USBP8P
USBP9N
USBP9P

USBRBIAS#

USBRBIAS

V26
U29
U28

Y27
Y26
W29
W28

AB26
AB25
AA29
AA28

AD27
AD26
AC29
AC28

T26
T25

Y23
Y24

G3
G2
H5
H4
H2
H1
J3
J2
K5
K4
K2
K1
L3
L2
M5
M4
M2
M1
N3
N2

F2
F3

DMI_RXP0
DMI_TXN0
DMI_TXP0

DMI_RXN1
DMI_RXP1
DMI_TXN1
DMI_TXP1

DMI_RXN2
DMI_RXP2
DMI_TXN2
DMI_TXP2

DMI_RXN3
DMI_RXP3
DMI_TXN3
DMI_TXP3

CLK_PCIE_ICH#
CLK_PCIE_ICH

DMI_IRCOMP
USB20_N0

USB20_P0
USB20_N1
USB20_P1
USB20_N2
USB20_P2

USB20_N5
USB20_P5
USB20_N6
USB20_P6
USB20_N7
USB20_P7
USB20_N8
USB20_P8
USB20_N9
USB20_P9

USBRBIAS

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

DMI_RXN0 (7)
DMI_RXP0 (7)
DMI_TXN0 (7)
DMI_TXP0 (7)

DMI_RXN1 (7)
DMI_RXP1 (7)
DMI_TXN1 (7)
DMI_TXP1 (7)

DMI_RXN2 (7)
DMI_RXP2 (7)
DMI_TXN2 (7)
DMI_TXP2 (7)

DMI_RXN3 (7)
DMI_RXP3 (7)
DMI_TXN3 (7)
DMI_TXP3 (7)

CLK_PCIE_ICH# (15)
CLK_PCIE_ICH (15)

R359 24.9_0402_1%

1 2

1 2

R360 22.6_0402_1%

2006/08/04 2006/10/06

Within 500 mils

USB20_N0 (31)
USB20_P0 (31)
USB20_N1 (26)
USB20_P1 (26)
USB20_N2 (31)
USB20_P2 (31)

USB20_N5 (25)
USB20_P5 (25)
USB20_N6 (31)
USB20_P6 (31)
USB20_N7 (26)
USB20_P7 (26)
USB20_N8 (36)
USB20_P8 (36)
USB20_N9 (26)
USB20_P9 (26)

Within 500 mils

Compal Secret Data

Deciphered Date

+1.5VS

RSMRST circuit

EC_RSMRST#(33)

2

R333

10K_0402_5%

PLT_RST# (7,17,18,23,25,26)

2.2K_0402_5%@

0.1U_0402_16V4Z

1

2

0.1U_0402_16V4Z

1

2

BAV99DW-7_SOT363@

R357

1 2

CK_PWRGD (15)

C307

@

C308

@

D13B

R358

1 2

1

Place closely pin AG9Place closely pin G5

CLK_14M_ICHCLK_48M_ICH

12

R320

10_0402_5%@

1

C305

4.7P_0402_50V8C@

2

12

R321

10_0402_5%@

1

C306

4.7P_0402_50V8C@

2

2006/10/14
AUDY DEL
S4/S5

R344 3.24K_0402_1%@

12

R346
453_0402_1%

@

R351 3.24K_0402_1%@

12

5

2.2K_0402_5%@

1 2

1 2

R353
453_0402_1%

@

1 2

3

E

2

4

3

EC_RSMRST#R

R355

0_0402_5%

Q10

C

1

MMBT3906_SOT23@

B

2

R356 4.7K_0402_5%@

1

D13A
BAV99DW-7_SOT363

6

+3VS

+3VALW

EC_RSMRST#R

1 2

@

R339

1 2

10K_0402_5%

+3VALW

USB PORT LIST

PORT DEVICE

LEFT SIDE

0
1

WIRELESS

2

RIGHT SIDE
CMOS3
RIGHT SIDE

4
5

NEW CARD
RIGHT SIDE

6
7

BT(HDL20)
FINGER PRINTER

8
9 TV TUNER

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

ICH8(3/4)_PM,USB,GPIO

IGT10/11 LA-3591P

1

20 48Tuesday, March 06, 2007

of

0.2

5

KC FBM-L11-201209-221LMAT_0805

D D

KC FBM-L11-201209-221LMAT_0805

R365

100_0402_5%

R366

C C

10_0402_5%

+1.5VS

B B

0.1U_0402_16V4Z

A A

+1.5VS

+5VS +3VS

12

+3VALW+5VALW

12

1 2

CHB1608U301_0603

C350

L39

1 2
1 2

L40

21

D14
CH751H-40_SC76

20 mils

ICH_V5REF_RUN

1

C327

0.1U_0402_16V4Z

2

21

D15
CH751H-40_SC76

ICH_V5REF_SUS

20 mils

1

C334

0.1U_0402_16V4Z

2

R367

C339

+1.5VS

C347

0.1U_0402_16V4Z

+3VS

1

+1.5VS

2

220U_D2_4VM

5

C317

0.1U_0402_16V4Z

1

C321

2

1

1

C340

2

2

1U_0603_10V4Z

+1.5VS

1

0.1U_0402_16V4Z

2

CHB1608U301_0603

1 2

R368

C351

+RTCVCC

1

2

40 mils

1

+

C322

2

10U_0805_6.3V6M

10U_0805_6.3V6M

2.2U_0603_10V6K

1

C352

2

10U_0805_6.3V6M

1

C318

0.1U_0402_16V4Z

2

ICH_V5REF_RUN

10U_0805_6.3V6M

1

C323

2

1U_0603_10V4Z

+1.5VS

1U_0603_10V4Z

1

C348

2

T26PAD
T27PAD

1

+1.5VS

CHB1608U301_0603

2

20 mils

ICH_V5REF_SUS

1

C324

2

2.2U_0603_6.3V4Z

+1.5VS

1

C341

2

1

C343

2

+1.5VS

VCC_LAN1_05_INT_ICH_1
VCC_LAN1_05_INT_ICH_2

R369

1 2

1

2

4.7U_0805_10V4Z

C353

+3VS

AD25

AA25
AA26
AA27
AB27
AB28
AB29

W25

AC10

W23

D28
D29

G24
H23
H24

M24
M25
N23
N24
N25

R24
R25
R26
R27

U24
U25

AE7
AF7
AG7
AH7

AC1
AC2
AC3
AC4
AC5

AC9
AA5

AA6
G12

G17

AC7
AD7

G18

G20

A16

T7
G4

E25
E26
E27
F24
F25

J23
J24
K24
K25
L23
L24
L25

P24
P25

T23
T24
T27
T28
T29

V23
V24
V25

Y25
AJ6

AJ7

H7

D1
F1

L6
L7
M6
M7

F17

F19

A24
A26

A27
B26
B27
B28

B25

4

U8F

VCCRTC
V5REF[1]

V5REF[2]
V5REF_SUS
VCC1_5_B[01]

VCC1_5_B[02]
VCC1_5_B[03]
VCC1_5_B[04]
VCC1_5_B[05]
VCC1_5_B[06]
VCC1_5_B[07]
VCC1_5_B[08]
VCC1_5_B[09]
VCC1_5_B[10]
VCC1_5_B[11]
VCC1_5_B[12]
VCC1_5_B[13]
VCC1_5_B[14]
VCC1_5_B[15]
VCC1_5_B[16]
VCC1_5_B[17]
VCC1_5_B[18]
VCC1_5_B[19]
VCC1_5_B[20]
VCC1_5_B[21]
VCC1_5_B[22]
VCC1_5_B[23]
VCC1_5_B[24]
VCC1_5_B[25]
VCC1_5_B[26]
VCC1_5_B[27]
VCC1_5_B[28]
VCC1_5_B[29]
VCC1_5_B[30]
VCC1_5_B[31]
VCC1_5_B[32]
VCC1_5_B[33]
VCC1_5_B[34]
VCC1_5_B[35]
VCC1_5_B[36]
VCC1_5_B[37]
VCC1_5_B[38]
VCC1_5_B[39]
VCC1_5_B[40]
VCC1_5_B[41]
VCC1_5_B[42]
VCC1_5_B[43]
VCC1_5_B[44]
VCC1_5_B[45]
VCC1_5_B[46]

VCCSATAPLL
VCC1_5_A[01]

VCC1_5_A[02]
VCC1_5_A[03]
VCC1_5_A[04]
VCC1_5_A[05]

VCC1_5_A[06]
VCC1_5_A[07]
VCC1_5_A[08]
VCC1_5_A[09]
VCC1_5_A[10]

VCC1_5_A[11]
VCC1_5_A[12]

VCC1_5_A[13]
VCC1_5_A[14]

VCC1_5_A[15]
VCC1_5_A[16]
VCC1_5_A[17]

VCC1_5_A[18]
VCC1_5_A[19]

VCCUSBPLL
VCC1_5_A[20]

VCC1_5_A[21]
VCC1_5_A[22]
VCC1_5_A[23]
VCC1_5_A[24]

VCC1_5_A[25]
VCCLAN1_05[1]

VCCLAN1_05[2]
VCCLAN3_3[1]

VCCLAN3_3[2]
VCCGLANPLL
VCCGLAN1_5[1]

VCCGLAN1_5[2]
VCCGLAN1_5[3]
VCCGLAN1_5[4]
VCCGLAN1_5[5]

VCCGLAN3_3

ICH8M REV 1.0

4

CORE

VCCA3GP ATXARX

VCCP_COREVCCPSUSVCCPUSB

IDE

PCI

VCCSUSHDA

VCCSUS1_05[1]
VCCSUS1_05[2]

VCCSUS1_5[1]

VCCSUS1_5[2]
VCCSUS3_3[01]
VCCSUS3_3[02]

VCCSUS3_3[03]
VCCSUS3_3[04]
VCCSUS3_3[05]

USB CORE

VCCSUS3_3[06]
VCCSUS3_3[07]

VCCSUS3_3[08]
VCCSUS3_3[09]
VCCSUS3_3[10]
VCCSUS3_3[11]
VCCSUS3_3[12]
VCCSUS3_3[13]
VCCSUS3_3[14]
VCCSUS3_3[15]
VCCSUS3_3[16]
VCCSUS3_3[17]
VCCSUS3_3[18]
VCCSUS3_3[19]

GLAN POWER

VCCCL3_3[1]
VCCCL3_3[2]

VCC1_05[01]
VCC1_05[02]
VCC1_05[03]
VCC1_05[04]
VCC1_05[05]
VCC1_05[06]
VCC1_05[07]
VCC1_05[08]
VCC1_05[09]
VCC1_05[10]
VCC1_05[11]
VCC1_05[12]
VCC1_05[13]
VCC1_05[14]
VCC1_05[15]
VCC1_05[16]
VCC1_05[17]
VCC1_05[18]
VCC1_05[19]
VCC1_05[20]
VCC1_05[21]
VCC1_05[22]
VCC1_05[23]
VCC1_05[24]
VCC1_05[25]
VCC1_05[26]
VCC1_05[27]
VCC1_05[28]

VCCDMIPLL
VCC_DMI[1]

VCC_DMI[2]

V_CPU_IO[1]
V_CPU_IO[2]

VCC3_3[01]
VCC3_3[02]
VCC3_3[03]

VCC3_3[04]
VCC3_3[05]
VCC3_3[06]

VCC3_3[07]
VCC3_3[08]
VCC3_3[09]
VCC3_3[10]
VCC3_3[11]
VCC3_3[12]
VCC3_3[13]

VCC3_3[14]
VCC3_3[15]
VCC3_3[16]
VCC3_3[17]
VCC3_3[18]
VCC3_3[19]
VCC3_3[20]
VCC3_3[21]
VCC3_3[22]
VCC3_3[23]
VCC3_3[24]

VCCHDA

VCCCL1_05

VCCCL1_5

3

+VCCP

A13
B13
C13
C14
D14
E14
F14
G14
L11
L12
L14
L16
L17
L18
M11
M18
P11
P18
T11
T18
U11
U18
V11
V12
V14
V16
V17
V18

R29
AE28

AE29
AC23

AC24
AF29
AD2
AC8

AD8
AE8
AF8

AA3
U7
V7
W1
W6
W7
Y7

A8
B15
B18
B4
B9
C15
D13
D5
E10
E7
F11

AC12
AD11
J6

AF20

VCCSUS1_5_ICH_1

AC16

VCCSUS1_5_ICH_2

J7
C3
AC18

AC21
AC22
AG20
AH28

P6
P7
C1
N7
P1
P2
P3
P4
P5
R1
R3
R5
R6

VCCCL1_05_ICH

G22
A22
F20

G21

0.1U_0402_16V7K

1

C319

C335

+3VS

+3VS

0.1U_0402_16V4Z

T22 PAD
T23 PAD

0.1U_0402_16V4Z

1

2

0.1U_0402_16V4Z

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

1

C320 0.1U_0402_16V4Z

2

2

0.01U_0402_16V7K

1

C325

2

0.1U_0402_16V4Z

1

+3VS

2

1

2

+3VS

1

1

C336

C337

2

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

C344
T24 PAD
T25 PAD

1

1

C345

2

2

+3VALW

1

C349

4.7U_0603_6.3V6K

2

T28 PAD

C354
1U_0603_10V4Z@

3

R364

1 2

CHB1608U301_0603

1

C326 10U_0805_6.3V6M

2

+1.25VS

1

C328
22U_0805_6.3V4Z

2

0.1U_0402_16V4Z

+3VS

(SATA)

C333

1

C338

0.1U_0402_16V4Z

2

+3VALW

1

2

+3VALW

C346

0.1U_0402_16V4Z

2006/08/04 2006/10/06

+1.5VS

+3VS

(DMI)

1

C332

2

1

C342

2

Compal Secret Data

+VCCP

4.7U_0603_6.3V6M
C329

1

2

+3VS

Deciphered Date

0.1U_0402_16V4Z
C330

1

2

0.1U_0402_16V4Z

2

C331

1

2

2

U8E

A23

VSS[001]

A5

VSS[002]

AA2

VSS[003]

AA7

VSS[004]

A25

VSS[005]

AB1

VSS[006]

AB24

VSS[007]

AC11

VSS[008]

AC14

VSS[009]

AC25

VSS[010]

AC26

VSS[011]

AC27

VSS[012]

AD17

VSS[013]

AD20

VSS[014]

AD28

VSS[015]

AD29

VSS[016]

AD3

VSS[017]

AD4

VSS[018]

AD6

VSS[019]

AE1

VSS[020]

AE12

VSS[021]

AE2

VSS[022]

AE22

VSS[023]

AD1

VSS[024]

AE25

VSS[025]

AE5

VSS[026]

AE6

VSS[027]

AE9

VSS[028]

AF14

VSS[029]

AF16

VSS[030]

AF18

VSS[031]

AF3

VSS[032]

AF4

VSS[033]

AG5

VSS[034]

AG6

VSS[035]

AH10

VSS[036]

AH13

VSS[037]

AH16

VSS[038]

AH19

VSS[039]

AH2

VSS[040]

AF28

VSS[041]

AH22

VSS[042]

AH24

VSS[043]

AH26

VSS[044]

AH3

VSS[045]

AH4

VSS[046]

AH8

VSS[047]

AJ5

VSS[048]

B11

VSS[049]

B14

VSS[050]

B17

VSS[051]

B2

VSS[052]

B20

VSS[053]

B22

VSS[054]

B8

VSS[055]

C24

VSS[056]

C26

VSS[057]

C27

VSS[058]

C6

VSS[059]

D12

VSS[060]

D15

VSS[061]

D18

VSS[062]

D2

VSS[063]

D4

VSS[064]

E21

VSS[065]

E24

VSS[066]

E4

VSS[067]

E9

VSS[068]

F15

VSS[069]

E23

VSS[070]

F28

VSS[071]

F29

VSS[072]

F7

VSS[073]

G1

VSS[074]

E2

VSS[075]

G10

VSS[076]

G13

VSS[077]

G19

VSS[078]

G23

VSS[079]

G25

VSS[080]

G26

VSS[081]

G27

VSS[082]

H25

VSS[083]

H28

VSS[084]

H29

VSS[085]

H3

VSS[086]

H6

VSS[087]

J1

VSS[088]

J25

VSS[089]

J26

VSS[090]

J27

VSS[091]

J4

VSS[092]

J5

VSS[093]

K23

VSS[094]

K28

VSS[095]

K29

VSS[096]

K3

VSS[097]

K6

VSS[098]

ICH8M REV 1.0

Title

Size Document Number Rev

Custom

IGT10/11 LA-3591P

Date: Sheet

VSS_NCTF[01]
VSS_NCTF[02]
VSS_NCTF[03]
VSS_NCTF[04]
VSS_NCTF[05]
VSS_NCTF[06]
VSS_NCTF[07]
VSS_NCTF[08]
VSS_NCTF[09]
VSS_NCTF[10]
VSS_NCTF[11]
VSS_NCTF[12]

Compal Electronics, Inc.

ICH8(4/4)_POWER&GND

VSS[099]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
VSS[159]
VSS[160]
VSS[161]
VSS[162]
VSS[163]
VSS[164]
VSS[165]
VSS[166]
VSS[167]
VSS[168]
VSS[169]
VSS[170]
VSS[171]
VSS[172]
VSS[173]
VSS[174]
VSS[175]
VSS[176]
VSS[177]
VSS[178]
VSS[179]
VSS[180]
VSS[181]
VSS[182]
VSS[183]
VSS[184]

1

K7
L1
L13
L15
L26
L27
L4
L5
M12
M13
M14
M15
M16
M17
M23
M28
M29
M3
N1
N11
N12
N13
N14
N15
N16
N17
N18
N26
N27
N4
N5
N6
P12
P13
P14
P15
P16
P17
P23
P28
P29
R11
R12
R13
R14
R15
R16
R17
R18
R28
R4
T12
T13
T14
T15
T16
T17
T2
U12
U13
U14
U15
U16
U17
U23
U26
U27
U3
U5
V13
V15
V28
V29
W2
W26
W27
Y28
Y29
Y4
AB4
AB23
AB5
AB6
AD5
U4
W24

A1
A2
A28
A29
AH1
AH29
AJ1
AJ2
AJ28
AJ29
B1
B29

1

21 48Tuesday, March 06, 2007

0.2

of

5

+LCDVDD

12

R208

100_0402_1%

D D

VGA_ENBKL

R211

0_0402_5%

UMA@

R611

0_0402_5%

VGA@

R215

R216

GMCH_LVDDEN(9)

VGA_ENVDD(17)

C C

BKOFF#(33)

ENBKL(33)

GMCH_ENBKL(9)

VGA_ENBKL(17)

2N7002_SOT23

12

12

D10
CH751H-40_SC76

21

12

0_0402_5%UMA@

12

0_0402_5%VGA@

Q7

+LCDVDD_R

13

D

S

2

R213
100K_0402_5%

1 2

+3VS

1 2

+5VALW

1 2

2

G

13

R214

4.7K_0402_5%

DISPOFF#

R218
100K_0402_5%

UMA@

1 2

R209
100K_0402_5%

Q8
DTC124EK_SC59

4

C290

0.1U_0402_16V4Z

1

C293

0.047U_0402_16V4Z

2

+LCDVDD

1

2

Q6

D

1 3

AO3413_SOT23

G

1

2

C291

4.7U_0805_10V4Z

2

+3VS

S

+LCDVDD

C295

22U_0805_6.3V4Z

1

C292

4.7U_0603_6.3V6K

2

12

3

KC FBM-L11-201209-221LMAT_0805

KC FBM-L11-201209-221LMAT_0805

B+

L11KC FBM-L11-201209-221LMAT_0805

1 2

LCD_DATA(17)

LCD/PANEL BD. Conn.

L10

1 2

L9

1 2

DISPOFF#

TXOUT2+
TXOUT2-

TXOUT0­TXOUT0+

LCD_B+

JP8

1 2

12

3

3

4

5

6

5

7

7

8

9 10

910

11 12

11 12

13

13

14

15

16

15

17

18

17

19

19

20

21

22

21

23

23

24

25

25

26

27

28

27

29

30

29

31

GND1

32

GND2

ACES_88242-3001
ME@

2

DAC_BRIG

4

INVT_PWM

6
8

LCD_CLKLCD_DATA

14
16
18
20
22
24
26
28
30

TXCLK+
TXCLK-

TXOUT1­TXOUT1+

DAC_BRIG (33)
INVT_PWM (33)

LCD_CLK (17)

+3VS

1

C294

0.1U_0402_16V4Z

2

1

B B

UMA@

RP16

LCD_CLK EDID_CLK_LCD

LCD_DATA

TXOUT0­TXOUT0+

TXOUT1­TXOUT1+

TXOUT2­TXOUT2+

TXCLK­TXCLK+

A A

UMA@

5

0_0404_4P2R_5%UMA@

1 4
2 3

1 4
2 3

RP17 0_0404_4P2R_5%

UMA@
1 4
2 3

RP18 0_0404_4P2R_5%

UMA@
1 4
2 3

RP19 0_0404_4P2R_5%

UMA@
1 4
2 3

RP20 0_0404_4P2R_5%

EDID_DAT_LCD

EDID_CLK_LCD (9)

EDID_DAT_LCD (9)

LVDSA0­LVDSA0+

LVDSA1­LVDSA1+

LVDSA2­LVDSA2+

LVDSAC­LVDSAC+

4

VGA@

TXOUT0­TXOUT0+

TXOUT1­TXOUT1+

TXOUT2­TXOUT2+

TXCLK­TXCLK+

RP49

2 3
1 4

RP50

2 3
1 4

RP51

2 3
1 4

RP52

2 3
1 4

0_0404_4P2R_5%VGA@

0_0404_4P2R_5%VGA@

0_0404_4P2R_5%VGA@

0_0404_4P2R_5%VGA@

VGA_TXOUT0- (17)
VGA_TXOUT0+ (17)

VGA_TXOUT1- (17)
VGA_TXOUT1+ (17)

VGA_TXOUT2- (17)
VGA_TXOUT2+ (17)

VGA_TXCLK- (17)
VGA_TXCLK+ (17)

2006/12/06

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/08/04 2006/10/06

Compal Secret Data

Deciphered Date

2

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

LVDS CONN

IGT10/11 LA-3591P

1

of

22 48Tuesday, March 06, 2007

0.2

5

Layout Notice : Filter place as close
chip as possible.

+2.5V_LAN

D D

C C

B B

A A

L13

FBM-L11-160808-601LMT_0603

FBM-L11-160808-601LMT_0603

FBM-L11-160808-601LMT_0603

+1.2V_LAN

L16 FBM-L11-160808-601LMT_0603

4.7U_0603_6.3V6K

L17 FBM-L11-160808-601LMT_0603

L18 FBM-L11-160808-601LMT_0603

4.7U_0603_6.3V6K

L19 FBM-L11-160808-601LMT_0603

4.7U_0603_6.3V6K

Layout Notice : Place as close
chip as possible.

C406

12

0.1U_0402_16V4Z

L14

12

0.1U_0402_16V4Z

L15

12

4.7U_0603_6.3V6K

+2.5V_LAN

0.1U_0402_16V4Z

1

2

2

1

C408

22U_0805_6.3V6M

C370

C386

0.1U_0402_16V4Z

12

1

2

12

1

2

12

1

2

12

1

2

2

C407

1

2

1

21.6

2

C387

1

+LAN_BIASVDD

1

2

C391

C394

C400

C403

0.1U_0402_16V4Z

5

+XTALVDD

2

C388

0.1U_0402_16V4Z

1

C389

0.1U_0402_16V4Z

+AVDDL

2

C392

0.1U_0402_16V4Z

1

+GPHY_PLLVDD

2

C395

0.1U_0402_16V4Z

1

+PCIE_PLLVDD

2

C401

0.1U_0402_16V4Z

1

+PCIE_VDD

2

C404

0.1U_0402_16V4Z

1

+LAN_AVDD

2

1

(CLKREQ#) and (ENERGY_DET) are
only supported in BCM5787M

+3VALW

EN_WOL(33)

4

KC FBM-L11-201209-221LMAT_0805@

1 2

L12

S

4 5

CLK_PCIE_LAN#(15)

ICH_PCIE_WAKE#(20,25,26)

4

D

6
2

1

G

Q11

3

SI3445ADV-T1-E3_TSOP6

CLK_PCIE_LAN(15)
CLKREQ_LAN#(15)

+3VS
+3VS

+3V_LAN

PCIE_TXN4(20)
PCIE_TXP4(20)

PCIE_RXN4(20)

PCIE_RXP4(20)

PLT_RST#(7,17,18,20,25,26)

1 2

R388 4.7K_0402_5%@

1 2

R389 4.7K_0402_5%@

25MHZ_20PF_6X25000017

1

C409
27P_0402_50V8J

2

Layout Notice : Place as close
chip as possible.

C371

4.7U_0603_6.3V6K

0.1U_0402_16V7K

0.1U_0402_16V7K

+3V_LAN
+3V_LAN

+3V_LAN

Y3

LAN_XTALO

1 2

+3V_LAN

2

C372

1

0.1U_0402_16V4Z

1 2
1 2
1 2

+GPHY_PLLVDD

C398
C399

1 2

R385 4.7K_0402_5%@

1 2

R386 4.7K_0402_5%@

R387 0_0402_5%

LAN_WP
GPIO2

1 2

R390 0_0402_5%@

12

R391
200_0402_1%

1

C410

2

2

C374

C373

1

0.1U_0402_16V4Z

T40

PAD

PCIE_MRX_C_LTX_N4
PCIE_MRX_C_LTX_P4

1 2

XTALO

1

2

2006/12/07

R377 0_0402_5%@
R378 1K_0402_5%
R381 1K_0402_5%

XTALI

27P_0402_50V8J

3

2

1

0.1U_0402_16V4Z

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

U12

28

PCIE_REFCLK_N

29

PCIE_REFCLK_P

11

CLKREQ

3

LOW PWR

53

VMAIN_PRSNT

54

VAUX_PRSNT

59

ENERGY_DET

35

GPHY_PLLVDD

32

PCIE_RXD_N

31

PCIE_RXD_P

25

PCIE_TXD_N

26

PCIE_TXD_P

10

PERST

12

WAKE

58

SMB_CLK

57

SMB_DATA

4

GPIO_0(SERIAL_DO)

7

GPIO_1(SERIAL_DI)

8

GPIO_2

9

UART_MODE

21

XTALI

22

XTALO

16

REG_GND

24

PCIE_GND

100@

SA00001I000

3

U12

SA00001A200

5787M

GIGA@

LAN_TX0-

41

TRD0_N

LAN_TX0+

40

TRD0_P

LAN_RX1-

42

TRD1_N

LAN_RX1+

43

TRD1_P

LAN_TX2-

48

TRD2_N

LAN_TX2+

47

TRD2_P

LAN_TX3-

49

TRD3_N

LAN_TX3+

50

TRD3_P

R379 0_0402_5%

2

LINKLED

R380 0_0402_5%

1

SPD100LED
SPD1000LED
TRAFFICLED

SCLK(EECLK)

SO(EEDATA)

REGCTL12
REGCTL25

PCIE_PLLVDD

PCIE_VDD
PCIE_VDD

GND

69

RDAC

XTALVDD

VDDIO
VDDIO
VDDIO
VDDIO
VDDIO

VDDP
VDDP

VDDC
VDDC
VDDC
VDDC
VDDC
VDDC

BIASVDD

AVDD
AVDD
AVDD

AVDDL
AVDDL
AVDDL
AVDDL

SI

CS

R382 0_0402_5%

67
66

65
63
64
62

14
18
37

R384 1.24K_0402_1%

23
6
15
19
56
61

17
68

5
13
20
34
55
60

+LAN_BIASVDD

36
30
27
33

38
45
52

39
44
46
51

R392

4.7K_0402_5%

LAN_WP
LAN_CLK
LAN_DATA

2006/08/04 2006/10/06

LAN_TX0- (24)
LAN_TX0+ (24)
LAN_RX1- (24)
LAN_RX1+ (24)
LAN_TX2- (24)
LAN_TX2+ (24)
LAN_TX3- (24)
LAN_TX3+ (24)

1 2
1 2
1 2

LAN_CLK
SI
LAN_DATA
CS#

CTL12
CTL25

12

GIGA@

+XTALVDD

+3V_LAN

+2.5V_LAN

+1.2V_LAN

+PCIE_PLLVDD

+PCIE_VDD

+LAN_AVDD

+AVDDL

+3V_LAN

12

12

R393

4.7K_0402_5%

LAN_CLK

1 2

SI
CS#

1 2

Compal Secret Data

Deciphered Date

2

4.7U_0603_6.3V6K

LINKLED# (24)

ACTIVITY# (24)

R384

1K_0402_1%

100@

1 2

C411

0.1U_0402_16V4Z

U13

8

VCC

7

WP

6

SCL

5

SDA

AT24C02_SO8

R394 4.7K_0402_5%

GIGA@

12

R395 4.7K_0402_5%

GIGA@

R396 4.7K_0402_5%

2

Layout Notice : 1.2V filter. Place as close
chip as possible.

+1.2V_LAN

C376

1

A0

2

A1

3

NC

4

GND

2006/12/07

1

2

2

C382

1

1

0.1U_0402_16V4Z

+3V_LAN

0.1U_0402_16V4Z

0.1U_0402_16V4Z

C390 0.1U_0402_16V4Z
C393 4.7U_0805_10V4Z

MMJT9435T1G_SOT223

2 3

4

C396

1 2
1 2

1

2

+1.2V_LAN

1

2

C397

10U_0805_10V4Z

C378

2

2

C380

C379

1

1

0.1U_0402_16V4Z

0.1U_0402_16V4Z

Q12

1

2

1

C377

1

2

0.1U_0402_16V4Z

CTL12ENG_DET

2006/12/26

+3V_LAN

1 2

C402

0.1U_0402_16V4Z

1 2

C4054.7U_0603_6.3V6K

41

Q13

MBT35200MT1G_TSOP6

+2.5V_LAN

3

256

CTL25

Notice : 4.7u 6.3V capactor Thickness 1.25mm

Layout Notice : Filter place as close
chip as possible.

2006/12/27

Title

Size Document Number Rev

Custom

Date: Sheet

BCM5787MKML
IGT10/11 LA-3591P

1

0.2

of

23 48Tuesday, March 06, 2007

5

4

3

2

1

D D

5787 no need
external AC

0.1U_0402_16V4Z

@

C1165

2

1

termination

12

R637

12

49.9_0402_1%
R633

@

12

12

R638

49.9_0402_1%

100@

1

C1171

0.1U_0402_16V4Z

2

100@

49.9_0402_1%

49.9_0402_1%

2006/12/21

C C

B B

R632

@

49.9_0402_1%

LAN_TX3-(23)
LAN_TX3+(23)

LAN_TX2-(23)
LAN_TX2+(23)

LAN_RX1+(23)
LAN_RX1-(23)

LAN_TX0-(23)
LAN_TX0+(23)

49.9_0402_1%

100@

1

C1166

0.1U_0402_16V4Z

@

2

12

12

R634

R639

100@

R635

@

49.9_0402_1%

12

12

R640

49.9_0402_1%

100@

1

C1172

0.1U_0402_16V4Z

2

100@

LAN_TX3+

LAN_TX2­LAN_TX2+

LAN_RX1+
LAN_RX1-

LAN_TX0­LAN_TX0+

@

+2.5V_LAN +3V_LAN

12

R630
0_0603_5%

0.1U_0402_16V4Z

1

1

C1170

C1168

0.1U_0402_16V4Z

2

2

RJ45_MIDI3+
RJ45_MIDI3-

RJ45_MIDI2+
RJ45_MIDI2-

12

R631
0_0603_5%

@

2006/12/07

1
2
3

4
5
6 19

7
8
9

10
11
12

R644 0_0402_5%100@

1 2

R645 0_0402_5%100@

1 2

R646 0_0402_5%100@

1 2

R647 0_0402_5%100@

1 2

GbE Transformer: GST5009 (SP050005610)
10/100 Transformer : TST1284-LF (SP050001X10)

U14

TCT1
TD1+
TD1-

TCT2
TD2+
TD2- MX2-

TCT3
TD3+
TD3-

TCT4
TD4+
TD4-

0.5u_GST5009

100@

MCT1
MX1+

MX1-

MCT2

MX2+

MCT3
MX3+

MX3-

MCT4
MX4+

MX4-

24
23
22

21
20

18
17
16

15
14
13

R642

75_0402_1%

12

75_0402_1%

12

R648

R643
75_0402_1%

RJ45_TER3

RJ45_TER2

12

12

U14

GST5009

GIGA@

RJ45_MIDI3-LAN_TX3­RJ45_MIDI3+

RJ45_MIDI2­RJ45_MIDI2+

RJ45_MIDI1+
RJ45_MIDI1-

RJ45_MIDI0­RJ45_MIDI0+

R649
75_0402_1%

RJ45_GND

2006/12/07

+3V_LAN

ACTIVITY#(23)

LINKLED#(23)

+3V_LAN

300_0402_5%

R636

ACTIVITY#

LINKLED#

R641 300_0402_5%

RJ45_GND LANGND

12

RJ45_MIDI3­RJ45_MIDI3+
RJ45_MIDI1­RJ45_MIDI2­RJ45_MIDI2+
RJ45_MIDI1+
RJ45_MIDI0­RJ45_MIDI0+

12

JP11

12

Amber LED+

11

Amber LED-

8

PR4-

7

PR4+

6

PR2-

5

PR3-

4

PR3+

3

PR2+

2

PR1-

1

PR1+

10

Green LED-

9

Green LED+

TYCO_3-440470-4

ME@

1 2

C1173
1000P_1206_2KV7K

SHLD2
SHLD1

SHLD2
SHLD1

1

C1174

2

0.1U_0402_16V4Z

16
15

14
13

1

C1175

4.7U_0805_10V4Z

2

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/08/04 2006/10/06

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

Compal Electronics, Inc.

LAN CONN

IGT10/11 LA-3591P

1

0.2

of

24 48Tuesday, March 06, 2007

A

B

C

D

E

SATA HDD Conn.

JP9

1

PSATA_ITX_DRX_P0(19)
PSATA_ITX_DRX_N0(19)

PSATA_IRX_DTX_N0_C(19)
PSATA_IRX_DTX_P0_C(19)

1 1

PSATA_ITX_DRX_P0
PSATA_ITX_DRX_N0

C355
C356
3900P_0402_50V7K
3900P_0402_50V7K

+3VS

+5VS

PSATA_IRX_DTX_N0

12

PSATA_IRX_DTX_P0

12

1 2

R370
0_0805_5%@

+3VS_SATA

GND

2

HTX+

3

HTX-

4

GND

5

HRX-

6

HRX+

7

GND

8

VCC3.3

9

VCC3.3

10

VCC3.3

11

GND

12

GND

13

GND

14

VCC5

15

VCC5

16

VCC5

17

GND

18

RESERVED

19

GND

20

VCC12

21

VCC12

22

VCC12G1G2

SUYIN_127043FB022G345ZR_NR

ME@

(NEW)

Main SATA +5V Default

23
24

C357

22U_1206_6.3V6M

IDERST_CD#(19)
PLT_RST#(7,17,18,20,23,26)

R372 0_0402_5%@
R373 33_0402_5%

Change Library

2 2

+5VS

1

2

C368
1U_0603_10V4Z

ODD_LED#(37)

1

C369
10U_0805_10V4Z

2

10K_0402_5%

ODD_LED#

R374

+5VS +3VS

1

1

C358

2

2

1000P_0402_50V7K

1U_0603_10V4Z

1

1

C360

C361

2

2

0.1U_0402_16V4Z

22U_0805_6.3V4Z

Pleace near HD CONN

1 2

1 2
1 2

+3VS

12

PD_D7
PD_D6
PD_D5
PD_D4
PD_D3
PD_D2
PD_D1
PD_D0

+5VS

PD_IOW#
PD_IORDY
PD_IRQ
PD_A1
PD_A0
PD_CS#1

PRI_CSEL

R376
470_0402_5%

1 2

PD_IOW#(19)

PD_IORDY(19)

PD_IRQ(19)

PD_CS#1(19) PD_CS#3 (19)

3 4
5 6
7 8

9 10
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
29 30
31 32
33 34
35 36
37 38
39 40
41 42
43 44
45 46
47 48
49 50
53 54

OCTEK_CDR-50DY1G

ME@

1

C362

@

2

JP10

12
34
56
78
910
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
29 30
31 32
33 34
35 36
37 38
39 40
41 42
43 44
45 46
47 48
49 50
G1 G2

1

1

C363

@

1000P_0402_50V7K

C365

2

2

1U_0603_10V4Z@

Pleace near HD CONN

PD_D8
PD_D9
PD_D10
PD_D11
PD_D12
PD_D13
PD_D14
PD_D15
PD_DREQ
PD_IOR#

PD_DACK#
PDIAG#

PD_A2
PD_CS#3

12

C367 0.1U_0402_16V4Z

PD_D[0..15]
PD_A[0..2]

1

C366

2

0.1U_0402_16V4Z

@

PD_DREQ (19)
PD_IOR# (19)

PD_DACK# (19)

1 2

R375 100K_0402_5%

+5VS

+5VS

PD_D[0..15] (19)

PD_A[0..2] (19)

+1.5VS_PEC

4.7U_0805_10V4Z

3 3

EXPCARD@

12

C429 0.1U_0402_16V4Z

EXPCARD@

12

C430 0.1U_0402_16V4Z

EXPCARD@

12

C431 0.1U_0402_16V4Z

PLT_RST#(7,17,18,20,23,26)

SYSON(33,38,44)
SUSP#(17,28,29,33,35,38,44,45)

CPUSB#(20)

4 4

CPUSB#

Express Card Power Switch

+1.5VS

+3VS

+3VALW

PLT_RST#
SYSON
SUSP#

U16

12

1.5Vin

14

1.5Vin

2

3.3Vin

4

3.3Vin

17 15

AUX_IN AUX_OUT

6

SYSRST#

20

SHDN#

1

STBY#

10

CPPE#

9

CPUSB#

18

RCLKEN

R5538_QFN20

EXPCARD@

PERST#

1.5Vout

1.5Vout

3.3Vout

3.3Vout

OC#

GND

+1.5VS_PEC

11
13

+3VS_PEC

3
5

+3V_PEC

19
8
16

NC

7

0.1U_0402_16V4Z EXPCARD@

PERST#

0.1U_0402_16V4Z

0.1U_0402_16V4Z

C427

C432

C434

1

2

+3V_PEC

1

EXPCARD@

2

+3VS_PEC

1

EXPCARD@

2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

1

C428

2

1

2

4.7U_0805_10V4Z

1

C435

2

EXPCARD@

C433

EXPCARD@

4.7U_0805_10V4Z

EXPCARD@

C

USB20_N5(20)

USB20_P5(20)

ICH_PCIE_WAKE#(20,23,26)

2006/08/04 2006/10/06

Compal Secret Data

Deciphered Date

USB20_N5
USB20_P5

R417
0_0402_5%

0_0402_5% EXPCARD@

R415

1 2

R416

1 2

0_0402_5%

ICH_SMBCLK(15,20,26)

ICH_SMBDATA(15,20,26)

EXPCARD@

1 2

CLKREQ_NC1#(15)

CLK_PCIE_NC1#(15)

CLK_PCIE_NC1(15)

PCIE_RXN3(20)

PCIE_RXP3(20)
PCIE_TXN3(20)

PCIE_TXP3(20)

D

+1.5VS_PEC

+1.5VS_PEC
+3V_PEC
+3VS_PEC

USB5-

EXPCARD@

USB5+
CPUSB#

ICH_SMBCLK
ICH_SMBDATA

PCIE_PME#_R

PERST#

CLKREQ_NC1#
CPUSB#
CLK_PCIE_NC1#
CLK_PCIE_NC1

PCIE_RXN3
PCIE_RXP3

PCIE_TXN3
PCIE_TXP3

Compal Electronics, Inc.

Title

HD/CDROM/ EXP_CARD

Size Document Number Rev

IGT10/11 LA-3591P 0.2

Custom

Tuesday, March 06, 2007

Date: Sheet of

JP12

1

GND

2

USB_D-

3

USB_D+

4

CPUSB#

5

RSV

6

RSV

7

SMB_CLK

8

SMB_DATA

9

+1.5V

10

+1.5V

11

WAKE#

12

+3.3VAUX

13

PERST#

14

+3.3V

15

+3.3V

16

CLKREQ#

17

CPPE#

18

REFCLK-

19

REFCLK+

20

GND

21

PERn0

22

PERp0

23

GND

24

PETn0

25

PETp0

26

GND

27

GND

28

GND

FOX_1CH4110C

ME@

E

GND
GND

29
30

25 48

A

B

C

D

E

1 1

ICH_PCIE_WAKE#(20,23,25)

2 2

CLKREQ_MCARD#(15)

CLK_PCIE_MCARD#(15)
CLK_PCIE_MCARD(15)

BT_AVTIVE
WLAN_AVTIVE

PCIE_RXN2(20)
PCIE_RXP2(20)

PCIE_TXN2(20)
PCIE_TXP2(20)

Mini-Express Card(Slot 1-WLAN)

JP13

R418 0_0402_5%@
R420 0_0402_5%@

12
12

CLK_PCIE_MCARD#
CLK_PCIE_MCARD

1

1

3

3

5

5

7

7

9

9

11

11

13

13

15

15

17

17

19

19

21

21

23

23

25

25

27

27

29

29

31

31

33

33

35

35

37

37

39

39

41

41

43

43

45

45

47

47

49

49

51

51

53

GND1

FOX_AS0B226-S56N-7F

ME@

GND2

2

2

4

4

6

6

8

8

10

10

12

12

14

14

16

16

18

18

20

20

22

22

24

24

26

26

28

28

30

30

32

32

34

34

36

36

38

38

40

40

42

42

44

44

46

46

48

48

50

50

52

52

54

RF_OFF#

PLT_RST#

+3VALW_MINI +3VALW_MINI

ICH_SMBCLK
ICH_SMBDATA

PLT_RST# (7,17,18,20,23,25)

+3VALW_MINI

USB20_N1 (20)
USB20_P1 (20)

WIRELESS_LED# (37)

1

C436

2

ICH_SMBCLK (15,20,25)
ICH_SMBDATA (15,20,25)

C438

MINI2@

0.1U_0402_16V4Z

ICH_PCIE_WAKE#(20,23,25)
+3VS
+1.5VS

1

2

MINI2@

0.1U_0402_16V4Z

CLKREQ_MCARD1#

CLK_PCIE_MCARD1#(15)

CLK_PCIE_MCARD1(15)

Mini-Express Card(Slot 2-TV-Tuner)

JP14

BT_AVTIVE
WLAN_AVTIVE

PCIE_RXN1(20)

PCIE_RXP1(20)

PCIE_TXN1(20)

PCIE_TXP1(20)

R419 0_0402_5%@
R421 0_0402_5%@

CLK_PCIE_MCARD1#
CLK_PCIE_MCARD1

PCIE_RXN1
PCIE_RXP1

PCIE_TXN1
PCIE_TXP1

1
12
12

1

3

3

5

5

7

7

9

9

11

11

13

13

15

15

17

17

19

19

21

21

23

23

25

25

27

27

29

29

31

31

33

33

35

35

37

37

39

39

41

41

43

43

45

45

47

47

49

49

51

51

53

GND1

FOX_AS0B226-S56N-7F

ME@

GND2

2

2

4

4

6

6

8

8

10

10

12

12

14

14

16

16

18

18

20

20

22

22

24

24

26

26

28

28

30

30

32

32

34

34

36

36

38

38

40

40

42

42

44

44

46

46

48

48

50

50

52

52

54

PLT_RST#

ICH_SMBCLK

ICH_SMBDATA

MINI_ON#(20)

+3VALW_MINI

RF_OFF# (33)
PLT_RST# (7,17,18,20,23,25)

+3VALW_MINI

ICH_SMBCLK (15,20,25)
ICH_SMBDATA (15,20,25)

USB20_N9 (20)
USB20_P9 (20)

WIRELESS_LED# (37)

Q43
AO3413_SOT23

D

S

1 3

G

2

MINI_ON#

1

C437

C439

2

MINI1@

0.1U_0402_16V4Z

+3VALW

C1189

0.1U_0402_16V7K

+3VS
+1.5VS

1

2

MINI1@

0.1U_0402_16V4Z

2006/12/26

+5VS

BT MODULE CONN.

3 3

HDA_SDOUT_MDC(19)
HDA_SYNC_MDC(19)

HDA_SDIN1(19)

HDA_RST_MDC#(19)

KILL_MDC#(19)

R426

1 2

R427

DAP202U_SOT323

D16

2
3

AZ_SYNC
AZ_SDIN3

33_0402_5%

12

0_0402_5%@

1

+3VALW

12

R425
10K_0402_1%

MDC CONN.

JP15

1

GND1

3

IAC_SDATA_OUT

5

GND2

7

IAC_SYNC

9

IAC_SDATA_IN

11

IAC_RESET#

Connector for MDC Rev1.5

GND

GND

GND

1314151617

RES0
RES1

3.3V
GND3
GND4

IAC_BITCLK

GND

GND

GND

18

2
4
6
8
10
12

ACES_88018-124G

ME@

C440

1 2

1U_0603_10V4Z

+3VALW

12

10_0402_5%

@

1

C442
10P_0402_50V8J

@

2

R428

BT_OFF#(33)

HDA_BITCLK_MDC (19)

BTONLED(37)

EC_BT_LED#(33)

2006/12/26

4 4

12

13

2

BTONLED

R672 0_0402_5%

DTC124EK_SC59

R424
10K_0402_1%

RF_OFF2

12

Q16

Q14
DTC124EK_SC59

13

@

+3VS

Q15

S

AO3413_SOT23

USB20_P7(20)
USB20_N7(20)

BTON_LED

2

G

USB20_P7
USB20_N7
BT_AVTIVE
WLAN_AVTIVE

+3VS_BT2

D

13

2

C441

12

0.1U_0402_16V4Z
JP16

1

1

GND

2

2

3

3

4

4

5

5

6

6

7

7

8

8

GND

ACES_87213-0800G

ME@

9

10

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2006/08/04 2006/10/06

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

D

Date: Sheet

Compal Electronics, Inc.

Mini Card / MDC CONN

IGT10/11 LA-3591P

E

0.2

of

26 48Tuesday, March 06, 2007

A

1 1

PCI_AD[0..31](18,28)

PCI_CBE#[0..3](18,28)

12

1

2

2 2

+3VS

PCI_PIRQE#(18)
PCI_PIRQC#(18)

+3VS

1

C454

PCMCIA@

4.7U_0805_10V4Z

2

+3VS

1

C459

0.1U_0402_16V4Z

2

PCMCIA@

PCI_CLKRUN#(20,28,33,35)

40mil

0.1U_0402_16V4Z

PCMCIA@

A

3 3

MFUNC5[3:0] = (0 1 0 1)
MFUNC5[4] = 1

4 4

PCI_AD[0..31]
PCI_CBE#[0..3]

CLK_PCI_CB

R433

10_0402_5%@

C448

15P_0402_50V8J@

1 2

R435 10K_0402_5%PCMCIA@

R666 0_0402_5%

1 2

R667 0_0402_5%

1 2

@

+3VS

1 2

R438 43K_0402_5%

1 2

R614 10K_0402_5%

1 2

R615 10K_0402_5%

1 2

R620 10K_0402_5%

1

C455

PCMCIA@

0.1U_0402_16V4Z

2

1

1

C460

C461

2

2

0.1U_0402_16V4Z

PCMCIA@

R679

1 2

@

@

@

@

0_0402_5%

B

VPPD0
VPPD1
VCCD0#
VCCD1#

U18

PCI_AD31
PCI_AD30
PCI_AD29
PCI_AD28
PCI_AD27
PCI_AD26
PCI_AD25
PCI_AD24
PCI_AD23
PCI_AD22
PCI_AD21
PCI_AD20
PCI_AD19
PCI_AD18
PCI_AD17
PCI_AD16
PCI_AD15
PCI_AD14
PCI_AD13
PCI_AD12
PCI_AD11
PCI_AD10
PCI_AD9
PCI_AD8
PCI_AD7
PCI_AD6
PCI_AD5
PCI_AD4
PCI_AD3
PCI_AD2
PCI_AD1
PCI_AD0

PCI_CBE#3
PCI_CBE#2
PCI_CBE#1
PCI_CBE#0

1 2

R436 100_0402_5%PCMCIA@

PCI_PIRQ_CB

PAD
T42

5IN1_LED#

SDOC#

1

C463

2

B

PCI_RST#

PCI_REQ#2
CLK_PCI_CB

SD_PULLHIGH

SM_CD#

PCI_RST#

0.1U_0402_16V4Z

PCMCIA@

PCI_RST#(18,28,33,35)

PCI_FRAME#(18,28)

PCI_IRDY#(18,28)

PCI_TRDY#(18,28)

PCI_DEVSEL#(18,28)

PCI_STOP#(18,28)
PCI_PERR#(18,28)
PCI_SERR#(18,28)

PCI_PAR(18,28)

PCI_REQ2#(18)

PCI_GNT2#(18)

CLK_PCI_CB(15)

PCI_AD20

SIRQ(20,28,33,35)

@

SM_CD# S1_CD2#

5IN1_LED#

SDOC#

MFUNC2

+S1_VCC

1

C457

PCMCIA@

0.1U_0402_16V4Z

2

0.1U_0402_16V4Z

PCMCIA@

MFUNC2

1

C458

PCMCIA@

0.1U_0402_16V4Z

2

1

C464

2

0.1U_0402_16V4Z

PCMCIA@

C2

AD31

C1

AD30

D4

AD29

D2

AD28

D1

AD27

E4

AD26

E3

AD25

E2

AD24

F2

AD23

F1

AD22

G2

AD21

G3

AD20

H3

AD19

H4

AD18

J1

AD17

J2

AD16

N2

AD15

M3

AD14

N3

AD13

K4

AD12

M4

AD11

K5

AD10

L5

AD9

M5

AD8

K6

AD7

M6

AD6

N6

AD5

M7

AD4

N7

AD3

L7

AD2

K7

AD1

N8

AD0

E1

CBE3#

J3

CBE2#

N1

CBE1#

N5

CBE0#

G4

PCIRST#

J4

FRAME#

K1

IRDY#

K3

TRDY#

L1

DEVSEL#

L2

STOP#

L3

PERR#

M1

SERR#

M2

PAR

A1

PCIREQ#

B1

PCIGNT#

H1

PCICLK

L8

RIOUT#_PME#

L11

SUSPEND#

F4

IDSEL

K8

MFUNC0

N9

MFUNC1

K9

MFUNC2

N10

MFUNC3

L10

MFUNC4

N11

MFUNC5

M11

MFUNC6

J9

MFUNC7

M10

GRST#

E7

VCC_SD

E8

SDCD#

F8

SDWP/SMWPD#

G7

SDPWREN33#

H5

SDCLKI

F6

SDCLK/SMWE#

E5

SDCMD/SMALE

E6

SDDAT0/SMDATA7

F7

SDDAT1/SMDATA0

F5

SDDAT2/SMCLE

G6

SDDAT3/SMDATA4

G5

GND_SD

1

C465

2

C

+3VS+S1_VCC

G13

A7

N12

M12

N13

M13

VCCD1#

VCCD0#

VPPD0

VPPD1

VCCA1

VCCA2

B4

VCC10

C8

VCC9

PCI Interface

SD/MMC/MS/SM

GND1

GND2

GND3

GND4

GND5

GND6

D3H2L4M8K11

F12

CB1410 P/N: SA014100310

C

G1

K2

N4

F3

L6

L9

H11

D12

VCC2

VCC3

VCC4

VCC1

VCC5

VCC6

VCC7

VCC8

CAD31/D10

CAD30/D9
CAD29/D1
CAD28/D8
CAD27/D0
CAD26/A0
CAD25/A1
CAD24/A2
CAD23/A3
CAD22/A4
CAD21/A5
CAD20/A6

CAD19/A25

CAD18/A7
CAD17/A24
CAD16/A17

CAD15/IOWR#

CAD14/A9

CAD13/IORD#

CAD12/A11
CAD11/OE#

CAD10/CE2#

CAD9/A10

CAD8/D15

CAD7/D7

CAD6/D13

CAD5/D6

CAD4/D12

CAD3/D5

CAD2/D11

CAD1/D4
CAD0/D3

CCBE3#/REG#

CCBE2#/A12

CCBE1#/A8

CCBE0#/CE1#

CARDBUS

CRST#/RESET
CFRAME#/A23

CIRDY#/A15

CTRDY#/A22

CDEVSEL#/A21

CSTOP#/A20
CPERR#/A14

CSERR#/WAIT#

CPAR/A13

CREQ#/INPACK#

CGNT#/WE#

CSTSCHG/BVD1_STSCHG#

GND7

C10

CCLK/A16

CCLKRUN#/WP_IOIS16#

CBLOCK#/A19

CINT#/READY_IREQ#

SPKROUT

CAUDIO/BVD2_SPKR#

CCD2#/CD2#
CCD1#/CD1#

CVS2/VS2#

CVS1/VS1

CRSV3/D2
CRSV2/A18
CRSV1/D14

MSPWREN#/SMPWREN#

GND8

B6

MSINS#

MSBS/SMDATA1

MSCLK/SMRE#
MSDATA0/SMDATA2
MSDATA1/SMDATA6
MSDATA2/SMDATA5
MSDATA3/SMDATA3

SMBSY#

SMCD#
SMWP#

SMCE#

CB714_LFBGA169

PCMCIA@
SA014100310

D

S1_D10

B2

S1_D9

C3

S1_D1

B3

S1_D8

A3

S1_D0

C4

S1_A0

A6

S1_A1

D7

S1_A2

C7

S1_A3

A8

S1_A4

D8

S1_A5

A9

S1_A6

C9

S1_A25

A10

S1_A7

B10

S1_A24

D10

S1_A17

E12

S1_IOWR#

F10

S1_A9

E13

S1_IORD#

F13

S1_A11

F11

S1_OE#

G10

S1_CE2#

G11

S1_A10

G12

S1_D15

H12

S1_D7

H10

S1_D13

J11

S1_D6

J12

S1_D12

K13

S1_D5

J10

S1_D11

K10

S1_D4

K12

S1_D3

L13

S1_REG#

B7

S1_A12

A11

S1_A8

E11

S1_CE1#

H13

S1_RST

B9

S1_A23

B11

S1_A15

A12

S1_A22

A13

S1_A21

B13

S1_A20

C12

S1_A14

C13

S1_WAIT#

A5

S1_A13

D13

S1_INPACK#

B8

S1_WE#

C11
B12

S1_BVD1

C5

S1_WP

D5

S1_A19

D11

S1_RDY#

D6

PCM_SPK#

M9

S1_BVD2

B5

S1_CD2#

A4

S1_CD1#

L12

S1_VS2

D9

S1_VS1

C6

S1_D2

A2

S1_A18

E10

S1_D14

J13

H7
J8
H8
E9
G9
H9
G8
F9

H6
J7
J6
J5

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

D

IDSEL:AD20
(PIRQE#/B#,
GNT#2,
REQ#2)

1 2

R434 33_0402_5%PCMCIA@

PCM_SPK# (29)

2

C451
10P_0402_50V8KPCMCIA@

1

S1_CD1#

2

C456

10P_0402_50V8KPCMCIA@

1

E

F

PCMCIA Power Control

U17

9

12V

+5VS

W=40mil

1

C444
10U_0805_10V4ZPCMCIA@

2

1

C446
10U_0805_10V4ZPCMCIA@

2

S1_A[0..25]
S1_D[0..15]

S1_A16

S1_OE#
S1_WP
S1_RST
S1_CE1#
S1_CE2#

2006/08/04 2006/10/06

Compal Secret Data

E

1

C445

2

0.1U_0402_16V4Z

PCMCIA@

W=40mil

1

C447

2

0.1U_0402_16V4Z

PCMCIA@

+S1_VCC

1

C449

10U_0805_10V4Z

2

PCMCIA@

+S1_VPP

1

C452

2

10U_0805_10V4Z

PCMCIA@

1 2

R439 43K_0402_5%PCMCIA@
R440 43K_0402_5%PCMCIA@

1 2

R441 43K_0402_5%PCMCIA@

1 2

R442 43K_0402_5%PCMCIA@

1 2

R443 43K_0402_5%PCMCIA@

Deciphered Date

C453

12

+3VS

12

R432
10K_0402_5%

PCMCIA@

S1_A[0..25]
S1_D[0..15]

1

C450

2

1

2

5

5V

6

5V

3

3.3V

4

3.3V

0.1U_0402_16V4Z

PCMCIA@

0.1U_0402_16V4Z

PCMCIA@

+S1_VCC
+S1_VCC
+S1_VCC
+S1_VCC
+S1_VCC

F

VCCD0
VCCD1
VPPD0
VPPD1

GND

SHDN

CP2211FD3_SSOP16

7

16

PCMCIA@

G

+S1_VCC

40mil

13

VCC

12

VCC

11

VCC

VPP

10

VCCD0#

1

VCCD1#

2

VPPD0

15

VPPD1

14

8

OC

40mil

+S1_VPP

PCMCIA Socket

+S1_VCC
+S1_VCC

+S1_VPP
+S1_VPP

Title

PCMCIA_ENE CB1410

Size Document Number Rev

Custom

IGT10/11 LA-3591P

Date: Sheet

G

H

VCCD0#

1 2

R430 10K_0402_5%PCMCIA@

VCCD1#

1 2

R431 10K_0402_5%PCMCIA@

1

C443

0.1U_0402_16V4Z

2

PCMCIA@

JP17

GND
GND
GND
GND

(HDQ70)

ME@

(NEW)

69
70
71
72

S1_D3

S1_CD1#

S1_D4

S1_D11

S1_D5

S1_D12

S1_D6

S1_D13

S1_D7

S1_D14

S1_CE1#

S1_D15

S1_A10

S1_CE2#

S1_OE#
S1_VS1

S1_A11

S1_IORD#

S1_A9

S1_IOWR#

S1_A8
S1_A17
S1_A13
S1_A18
S1_A14
S1_A19

S1_WE#

S1_A20

S1_RDY#

S1_A21

S1_A16
S1_A22
S1_A15
S1_A23
S1_A12
S1_A24

S1_A7
S1_A25

S1_A6

S1_VS2

S1_A5

S1_RST

S1_A4

S1_WAIT#

S1_A3

S1_INPACK#

S1_A2

S1_REG#

S1_A1

S1_BVD2

S1_A0

S1_BVD1

S1_D0
S1_D8
S1_D1
S1_D9
S1_D2

S1_D10

S1_WP

S1_CD2#

1

GND

35

GND

2

DATA3

36

CD1#

3

DATA4

37

DATA11

4

DATA5

38

DATA12

5

DATA6

39

DATA13

6

DATA7

40

DATA14

7

CE1#

41

DATA15

8

ADD10

42

CE2#

9

OE#

43

VS1#

10

ADD11

44

IORD#

11

ADD9

45

IOWR#

12

ADD8

46

ADD17

13

ADD13

47

ADD18

14

ADD14

48

ADD19

15

WE#

49

ADD20

16

READY

50

ADD21

17

VCC

51

VCC

18

VPP

52

VPP

19

ADD16

53

ADD22

20

ADD15

54

ADD23

21

ADD12

55

ADD24

22

ADD7

56

ADD25

23

ADD6

57

VS2#

24

ADD5

58

RESET

25

ADD4

59

WAIT#

26

ADD3

60

INPACK#

27

ADD2

61

REG#

28

ADD1

62

BVD2

29

ADD0

63

BVD1

30

DATA0

64

DATA8

31

DATA1

65

DATA9

32

DATA2

66

DATA10

33

WP

67

CD2#

34

GND

68

GND

SANTA_130601-7_LT

4 IN 1 Socket

Compal Electronics, Inc.

27 48Tuesday, March 06, 2007

H

2006/06/08

0.2

of

5

1

C487

2

270P_0402_50V7K

R463

1 2

56.2_0402_1%

R466

1 2

56.2_0402_1%

U19

125

AD31

126

AD30

127

AD29

1

AD28

2

AD27

3

AD26

5

AD25

6

AD24

9

AD23

11

AD22

12

AD21

14

AD20

15

AD19

17

AD18

18

AD17

19

AD16

36

AD15

37

AD14

38

AD13

39

AD12

40

AD11

42

AD10

43

AD9

44

AD8

46

AD7

47

AD6

48

AD5

49

AD4

50

AD3

51

AD2

52

AD1

53

AD0

7

C/BE3#

21

C/BE2#

35

C/BE1#

45

C/BE0#

33

PAR

23

FRAME#

25

TRDY#

24

IRDY#

29

STOP#

26

DEVSEL#

8

IDSEL

30

PERR#

31

SERR#

124

REQ#

123

GNT#

121

PCICLK

119

PCIRST#

71

GBRST#

117

CLKRUN#

70

PME#

115

INTA#

116

INTB#

69

HWSPND#

66

TEST

111

AGND

107

AGND

103

AGND

102

AGND

99

AGND

97

NC

R5C832_TQFP128~D

@

12

Z3008

1 2

R467

1 2

SA00000FU30

832@

R460

5.1K_0402_1%

R464

56.2_0402_1%

2

1

56.2_0402_1%

PCI_AD[0..31](18,27)

D D

C C

B B

A A

U19

R5C833

833@
SA00001HX10

PCI_CBE#3(18,27)
PCI_CBE#2(18,27)
PCI_CBE#1(18,27)
PCI_CBE#0(18,27)

PCI_PAR(18,27)
PCI_FRAME#(18,27)
PCI_TRDY#(18,27)
PCI_IRDY#(18,27)

+3VS

+3VS

12

R465

832@

CBS_GRST#

1

C493
1U_0603_10V6K

2

832@

PCI_STOP#(18,27)
PCI_DEVSEL#(18,27)

PCI_PERR#(18,27)
PCI_SERR#(18,27)

PCI_REQ0#(18)
PCI_GNT0#(18)

CLK_PCI_1394(15)

PCI_RST#(18,27,33,35)

R449 10K_0402_5%@

1 2

R451 0_0402_5%832@

1 2

R5_PME#(33)
PCI_PIRQG#(18)
PCI_PIRQH#(18)

1 2

R453 10K_0402_5%

832@

1 2

R455 0_0402_5%@

100K_0402_5%

5

832@

PCI_AD22 CBS_IDSEL

1 2

R444 100_0402_5%

PCI_CLKRUN#(20,27,33,35)

SUSP#(17,25,29,33,35,38,44,45)

CLK_PCI_1394

12

R462

@

10_0402_5%

2

C492

1

@

4.7P_0402_50V8C

PCI_AD31
PCI_AD30
PCI_AD29
PCI_AD28
PCI_AD27
PCI_AD26
PCI_AD25
PCI_AD24
PCI_AD23
PCI_AD22
PCI_AD21
PCI_AD20
PCI_AD19
PCI_AD18
PCI_AD17
PCI_AD16
PCI_AD15
PCI_AD14
PCI_AD13
PCI_AD12
PCI_AD11
PCI_AD10
PCI_AD9
PCI_AD8
PCI_AD7
PCI_AD6
PCI_AD5
PCI_AD4
PCI_AD3
PCI_AD2
PCI_AD1
PCI_AD0

PCI_CBE#3
PCI_CBE#2
PCI_CBE#1
PCI_CBE#0

PCI_PAR
PCI_FRAME#
PCI_TRDY#
PCI_IRDY#
PCI_STOP#
PCI_DEVSEL#

PCI_PERR#
PCI_SERR#

PCI_REQ0#
PCI_GNT0#

CBS_GRST#

R5_PME#

832@

832@

IEEE1394_TPBN0
IEEE1394_TPBP0
IEEE1394_TPAN0
IEEE1394_TPAP0

832@

IEEE1394_TPBIAS0

R5C832

832@

832@

832@

2

832@

C495

C494

1

0.01U_0402_16V7K

4

VCC_PCI3V
VCC_PCI3V
VCC_PCI3V
VCC_PCI3V
VCC_PCI3V
VCC_PCI3V

VCC_RIN

VCC_ROUT
VCC_ROUT
VCC_ROUT
VCC_ROUT
VCC_ROUT

VCC_3V

VCC_MD3V

AVCC_PHY3V
AVCC_PHY3V
AVCC_PHY3V
AVCC_PHY3V

TPBIAS0

TPAP0
TPAN0

TPBP0
TPBN0

MDIO00
MDIO01
MDIO02
MDIO03
MDIO04
MDIO05
MDIO06
MDIO07
MDIO08
MDIO09
MDIO10
MDIO11
MDIO12
MDIO13
MDIO14
MDIO15
MDIO16
MDIO17
MDIO18
MDIO19

MSEN
XDEN

XI

XO

FIL0
REXT
VREF

UDIO0/SERIRQ#

UDIO1
UDIO2
UDIO3
UDIO4
UDIO5

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

SDPWR0_MSPWR_XDPWR

Layout Note: Shield GND for
IEEE1394_TPA and TPB

0.33U_0603_16V4Z

4

10
20
27
32
41
128

61
16

34
64
114
120

67
86

+3V_PHY

98
106
110
112

IEEE1394_TPBIAS0

113

IEEE1394_TPAP0

109

IEEE1394_TPAN0

108

IEEE1394_TPBP0

105

IEEE1394_TPBN0

104

SDCD#_XDCD0#

80

MSCD#_XDCD1

79

XD_CE#

78

SDWP#_XDRB#

77

SDPWR0_MSPWR_XDPWR

76

XDWP#

75
74

TP_MSEXTCK

73

SDCMD_MSBS

88

SDCLK_MSCLK

84

SDDATA0_MSDATA0

82

SDDATA1_MSDATA1

81

SDDATA2_MSDATA2

93

SDDATA3_MSDATA3

90

XDD4

91

XDD5

89

XDD6

92

XDD7

87

XDCLE

85

XDALE

83

MSEN

58

XDEN

55

R5C832XI

94

R5C832XO

95
96

101
100

SIRQ

72

TP_UDIO1

60

TP_UDIO2

56

UDIO3

65

UDIO4

59

UDIO5

57
4

13
22
28
54
62
63
68
118
122

R626

1 2

R627

1 2

+3VS

1

C491

2

832@

1

1

2

2

3

356

4

4

JP18

+3VS

0_0805_5%832@
0_0805_5%832@

U20

3

VIN

4

VIN/CE

2

GND

RT9701CB_SOT25

0.1U_0402_16V4Z

FOX_UV31413-4R1-TRME@

5
6

1

C466

2

832@

0.01U_0402_16V7K

SDCD#_XDCD0# (37)
MSCD#_XDCD1 (37)

SDWP#_XDRB# (37)

SDCMD_MSBS (37)

SDCLK_MSCLK
SDDATA0_MSDATA0 (37)
SDDATA1_MSDATA1 (37)
SDDATA2_MSDATA2 (37)
SDDATA3_MSDATA3 (37)

SIRQ (20,27,33,35)

VOUT
VOUT

832@

3

1

C467

10U_0805_10V4Z

2

832@

R625

0_0805_5%

1 2

1

1

C476

2

2

832@

0.01U_0402_16V7K

T34PAD

T35PAD

T36PAD
T37PAD
T38PAD
T39PAD

832@

1 2

C483

0.01U_0402_16V7K

T29PAD
T30PAD

Layout Note: Shield GND for
CBS_CCLK_INTERNAL and CBS_CCLK

2

1

40mil

+VCC_SD

1
5

12

1

C488

R461

2

1U_0603_10V4Z

832@

C489

150K_0402_5%

832@

3

2

+3VS

1

1

1

1

C472

+3VS

C477

10U_0805_10V4Z

832@

R452

C485

832@

832@

1 2

0.01U_0402_16V7K

+VCC_SD

1

2

832@

10U_1206_6.3V6M

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUST ODY OF THE COM PET ENT DIV ISIO N OF R& D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER TH IS S HEE T NO R T HE I NFO RMAT ION IT CON TAI NS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WIT HOU T PR IOR WRI TTE N C ONSE NT OF C OMP AL E LECT RON ICS , IN C.

C473

2

2

832@

832@

0.01U_0402_16V7K

+3VS

Layout Note: Place close to R5C 8 32
and Shield GND for SDCLK_MSCLK

15P_0603_50V8J

10K_0603_1%

15P_0603_50V8J

1

C490

2

832@

0.1U_0402_16V4Z

1

1

C474

2

0.47U_0603_16V4Z

0.01U_0402_16V7K

832@

L20

1 2

832@

BLM21A601SPT_0805

C484

1 2

832@

C486

1 2

832@

2006/08/04 2006/10/06

2

C475

2

0.47U_0603_16V4Z

1

2

22U_0805_6.3V6M

Layout Note: Place close to R5C83 2
and Shield GND for SD_CLK

R5C832XI

X1

832@

24.576MHz_16P_1BG24576CKIA

1 2

R5C832XO

Compal Secret Data

C468

832@

0.01U_0402_16V7K

1

832@

C478

2

832@

Deciphered Date

C471

10U_0805_10V4Z

2

832@

+3V_PHY

1

C479

2

0.1U_0402_16V4Z

2

C481

832@

1000P_0402_50V7K

SDDATA1_MSDATA1

SDDATA2_MSDATA2

+5VS

1 2

R458 10K_0402_5%@

SDCD#_XDCD0#

2N7002_SOT23

1

SD,MMC,MS,XD muti-function pin define

MDIO
PIN Name
MDIO00

SD Card
PIN Name
SDCD#

MMC Card
PIN Name
MMCCD#

MDIO01

MS Card
PIN Name

MSCD#
MDIO02
MDIO03
MDIO04
MDIO05
MDIO06
MDIO07
MDIO08
MDIO09 SDCCLK
MDIO10
MDIO11
MDIO12
MDIO13

SDWP#
SDPWR0
SDPWR1
SDLED#

SDCCMD

SDCDAT0
SDCDAT1
SDCDAT2
SDCDAT3

MMCPWR

MMCLED#

MMCCMD
MMCCLK
MMCDAT

MSWR

MSLED#

MSEXTCK

MSBS

MSCCLK

MSCDAT0

MSCDAT1

MSCDAT2

MSCDAT3
MDIO14
MDIO15
MDIO16
MDIO17
MDIO18
MDIO19

Function set pin define

Pull-up

R454 0_0402_5%

D

1 3

832@

G

2

13

D

2

G

S

Q20

@

Title

Size Document Number Rev

Custom
Date: Sheet

MSEN XDENUDIO3 UDIO4

Pull-upPull-up Enable

R445 10K_0402_5%

MSEN
UDIO3
UDIO4
UDIO5

XDEN

1 2

R446 10K_0402_5%

1 2

R447 10K_0402_5%

1 2

R448 100K_0402_5%

1 2

R450 10K_0402_5%

1 2

Solve MS Duo Adaptor short problem

12

Q17

@

2N7002_SOT23

S

R456 0_0402_5%

D

1 3

2

12

Q18

@

2N7002_SOT23

S

G

Compal Electronics, Inc.

1394+3 in 1 Card

IGT10/11 LA-3591P

Pull-up

832@
832@
832@
832@

832@

SD_MSDATA1

SD_MSDATA2

1

Function

SD,XD,MS,MMC Card

+3VS

SD_MSDATA1 (37)

SD_MSDATA2 (37)

28 48Tuesday, March 06, 2007

XD Card
PIN Name
XDCD0#

XDCD1#
XDCE#
XDR/B#
XDPWR
XDWP#
XDLED#

XDWE#
XDRE#
XDCDAT0
XDCDAT1
XDCDAT2
XDCDAT3
XDCDAT4
XDCDAT5
XDCDAT6
XDCDAT7
XDCLE
XDALE

of

0.2

A

L21

+VDDA

1 1

+MIC2_VREFO

ACES_88231-02001

1 2

FBM-L11-160808-800LMT_0603

10U_0805_10V4Z

Int MIC Conn.

1 2

R471 4.7K_0402_5%

GND
GND

ME@

MIC1

MIC1_L(30)
MIC1_R(30)

1
2

INT_MIC

1
2

C514
220P_0402_50V7K

3

MIC@

4

2

3

@

1

D48

MIC1_L MIC1_C_L

MIC@

12

SM05_SOT23

2006/12/07

2 2

SPK_SEL HIGH: HARMAN
LOW:
NO-BRAND

0.1U_0402_16V4Z

1

1

C496

C497

2

2

C510 100P_0402_50V8J
C513 1U_0402_6.3V4Z
C516 1U_0402_6.3V4Z
C517 100P_0402_50V8J

100P_0402_50V8J

1 2

C519

C524 2.2U_0603_6.3V4Z
C525 2.2U_0603_6.3V4Z

C527

C520

1 2
1 2

1 2

1 2

100P_0402_50V8J

C1163 100P_0402_50V8J
C522 100P_0402_50V8J
C1164 100P_0402_50V8J

100P_0402_50V8J

2006/09/04

2006/09/04

SENSE FOR Ext.
Mic.

MIC_SENSE(30)

R481

1 2

20K_0402_1%

1

C498

2

0.1U_0402_16V4Z

1 2
1 2
1 2
1 2

1 2
1 2
1 2

HDA_RST_AUDIO#(19)
HDA_SYNC_AUDIO(19)
HDA_SDOUT_AUDIO(19)

SENSE_A

680P_0402_50V7K

C499

100P_0402_50V8J

MIC2_L

MIC2_R

LINE1_C_L
LINE1_C_R

MIC1_C_RMIC1_R
MONO_IN

SENSE_A
SENSE_B

EAPD

T41

PAD

SENSE FOR Int. Mic.

3 3

R482

1 2

20K_0402_1%

MIC@

SENSE_B

SENSE FOR HP

HP_SENSE(30)

R487

39.2K_0402_1%

SENSE_A

12

B

HD Audio Codec

+AVDD_AC97

40mil

1

C500

2

25

38

U21

AVDD1

AVDD2

14

NC

15

NC

16

MIC2_L

17

MIC2_R

23

LINE1_L

24

LINE1_R

18

CD_L

20

CD_R

19

CD_GND

21

MIC1_L

22

MIC1_R

12

PCBEEP

11

RESET#

10

5
2

3
13
34

47
48

4

7

SYNC
SDATA_OUT
GPIO0

GPIO3
SENSE A
SENSE B

EAPD
SPDIFO
DVSS1

DVSS2

SA00001GD00

MIC1_VREFO_L

MIC1_VREFO_R

ALC268-GR_LQFP48

Sense Pin Impedance Codec Signals

SENSE A

SENSE B

+3VS_DVDD

20mil

1

DVDD

LINE_OUT_L
LINE_OUT_R

HP_OUT_L

HP_OUT_R

DMIC_CLK

BIT_CLK

SDATA_IN

MONO_OUT

LINE1_VREFO

GPIO1

MIC2_VREFO

VREF

JDREF

AVSS1
AVSS2

0.1U_0402_16V4Z

9

DVDD_IO

35
36
39
41
45

NC

46
43

NC

44

NC

6

8
37
29
31
28
32
30
27
40
33

NC

26
42

39.2K
20K
10K

5.1K

39.2K
20K
10K

5.1K

1

1

C502

C501

2

2

0.1U_0402_16V4Z

AMP_LEFT
AMP_RIGHT
AMP_LEFT_HP
AMP_RIGHT_HP

ICH_BITCLK_AUDIO

+MIC1_VREFO_L

10mil

+MIC1_VREFO_R

10mil

+MIC2_VREFO

10mil

ACZ_VREF
ACZ_JDREF

PORT-A (PIN 39, 41)
PORT-B (PIN 21, 22)
PORT-C (PIN 23, 24)
PORT-D (PIN 35, 36)
PORT-E (PIN 14, 15)
PORT-F (PIN 16, 17)
PORT-G (PIN 43, 44)
PORT-H (PIN 45, 46)

10U_0805_10V4Z

1

C503

2

680P_0402_50V7K

1 2

R476 22_0402_5%

1 2

R477 33_0402_5%

10mil

20K_0402_1%

12

R480

C

680P_0402_50V7K

C505

C504

2006/09/04

C529
100P_0402_50V8J

10U_0805_10V4Z

1

2

L22

1 2

FBM-L11-160808-800LMT_0603

1

C506

2

100P_0402_50V8J

AMP_LEFT (30)
AMP_RIGHT (30)
AMP_LEFT_HP (30)
AMP_RIGHT_HP (30)

HDA_BITCLK_AUDIO (19)

HDA_SDIN0 (19)

1

1

C530

2

C531

2

100P_0402_50V8J

Regulator for CODEC

KC FBM-L11-201209-221LMAT_0805

+3VS

EC Beep

BEEP#(33)

PCI Beep

SB_SPKR(20)

CardBus Beep

PCM_SPK#(27)

HDA_BITCLK_AUDIO

L23

1 2

C532

SUSP#(17,25,28,33,35,38,44,45)

4.7U_0805_10V4Z

1
1 2

2

C533

R676

@

0_0402_5%

D

C508

1U_0402_6.3V4Z

C515

1U_0402_6.3V4Z

C518

1U_0402_6.3V4Z

2

C521

0.01U_0402_16V7K

1

R478
10_0402_5%

@

C528
10P_0402_50V8J

@

12

0.1U_0402_16V4Z

0_0402_5%

12

R470

1 2

1 2

560_0402_5%

R473

1 2

1 2

560_0402_5%

R474

1 2

1 2

560_0402_5%

10K_0402_5%

Adjustable Output

U22

4

VIN

2

DELAY

7 1

ERROR CNOISE

8

R485

SD

SI9182DH-AD_MSOP8

SA091820030

VOUT

SENSE or ADJ

2006/12/07

GND

R475

5
6

3

12

+VDDA

C

2

B

E

D18

RB751V_SOD323

2 1

C535 0.1U_0402_16V4Z

12

12

1

3

E

R468
10K_0402_5%

1 2

C507 1U_0402_6.3V4Z

R469
10K_0402_5%

Q39
2SC2411K_SC59

C509

1 2

1U_0402_6.3V4Z

1 2

R472 2.4K_0402_1%

+VDDA

R483

69.8K_0603_1%

1 2

12

R484
24K _0402_1%

MONO_IN

+VDDA+5VS +5VS_VDDA

C534 4.7U_0805_10V4Z

1 2

R659 0_0603_5%

1 2

4 4

R660 0_0603_5%

2006/09/04

2006/10/20

A

B

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2006/08/04 2006/10/06

Compal Secret Data

Deciphered Date

D

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

ALC861 VD Codec

IGT10/11 LA-3591P

E

of

29 48Tuesday, March 06, 2007

0.2

A

APA2056 SPK/HP Amplifier

fo=1/(2*3.14*R*C)=106Hz

EC_EAPD

CH751H-40_SC76

V

8

9

10

(dB)

R=1.5K / C= 1uF

R494 1.5K_0402_1%

1 2

R495 1.5K_0402_1%

1 2

1 2

C542 1U_0402_6.3V4Z

1 2

C544 1U_0402_6.3V4Z

D51

V(low) V(high)

1 1

AMP_RIGHT(29)
AMP_LEFT(29)

AMP_RIGHT_HP(29)
AMP_LEFT_HP(29)

2 2

EC_EAPD(33)

APA2057 gain setting table

gain

3 3

+5VALW

+5VS_VDDA

L34 KC FBM-L11-201209-221LMAT_0805

21

L42

1 2

1 2

@

AMP_R

1 2

C543 1U_0402_6.3V4Z

AMP_L

1 2

C545 1U_0402_6.3V4Z

R498 100K_0402_5%

1 2

R499 100K_0402_5%

+5VS

1 2

AMP_RHPIN

1 2

C546 2.2U_0603_10V6K

AMP_LHPIN

1 2

C547 2.2U_0603_10V6K

EC_EAPD#

1 2

C548 0.47U_0402_6.3V6K

+5VALW

12

4.7K_0402_5%
R681

EC_EAPD#

R682

12K_0402_5%

1 2

C536

3.21 3.27

3.33 3.39

3.45 3.51

KC FBM-L11-201209-221LMAT_0805

W=40mil

1

C537

2

680P_0402_50V7K

0.1U_0402_16V4Z

AMPR
AMPL

C549 1U_0603_10V6K

C552 0.1U_0402_16V4Z

R496

1 2

0_0402_5%
R497

1 2

0_0402_5%

R500

1 2

39K_0402_5%

R501

1 2

39K_0402_5%

12

R502 47K_0402_5%

AMP_CP+
AMP_CP-

1 2

AMP_BIAS

1 2

C550 2.2U_0603_10V6K

12

for APA 2057
GAIN setting

B

2006/09/05

1

2

C539

C538

2

1

1U_0402_6.3V4Z

INR_A

3

INR_A

INL_A

5

INL_A

AMP_EN#
HP_EN

24

HP EN

INR_H

4

INR_H

INL_H

6

INL_H

26

AMP_BEEP

current
setting(3.48V)

/SD
BEEP

12

CP+

14

CP-

25

BIAS

IN_A Gain = 10dB (Internal Speaker)
IN_H Gain = 0dB (Headphone)

+3VALW

10U_0805_10V4Z

11

HVDD

CVDD

APA2056_TSSOP28

202819910

PVDD

PVDD

1

VDD

ROUT+

ROUT­LOUT+/AMP EN

LOUT-

HP_R

HP_L

CVSS

GND
PGND
PGND
CGND

VSS

C

MIC_SENSE(29)

0_0402_5%

R657

1 2

R658

1 2

0_0402_5%

INTSPK_L1
INTSPK_L2
INTSPK_R1
INTSPK_R2

MIC1_R

KC FBM-L11-160808-121LMT 0603

MIC1_L

KC FBM-L11-160808-121LMT 0603

MIC1_R(29)

U23

INTSPK_R1

22

INTSPK_R2

21

INTSPK_L1

827

INTSPK_L2
HP_R

17

HP_L

18

CVSS

15
16
2

1
23
7
13

C551
1U_0603_10V6K

2

MIC1_L(29)

HP_R
HP_L

D

12

10mil 10mil

R492

4.7K_0402_5%

L26

1 2

L27

1 2

L24
L25

C540

1

C541

2

220P_0402_50V7K

1

C553

2

D22SM05_SOT23

1

@

D21SM05_SOT23

1

@

1 2
1 2

HP_R_R

KC FBM-L11-160808-121LMT 0603

HP_L_R

KC FBM-L11-160808-121LMT 0603

L30 HLMA-160808-39NKT

1 2

L31 HLMA-160808-39NKT

1 2

L28 HLMA-160808-39NKT

1 2

L29 HLMA-160808-39NKT

1 2

+MIC1_VREFO_R+MIC1_VREFO_L

12

R493

4.7K_0402_5%

MIC1_R_1
MIC1_L_1

1

2

220P_0402_50V7K

HP_SENSE(29)

HPR
HPL

1

C554

2

10P_0402_50V8J

3
2

SPK_L1
SPK_L2
SPK_R1
SPK_R2

2
3

10P_0402_50V8J

3

@

1

D19

3

1

JP21

1
2
3
4
5
6

ACES_88231-04001

@

2

SM05_SOT23

2

D20

@

SM05_SOT23

1
2
3
4
G1
G1

E

MICROPHONE
IN JACK

ME@

SINGA_2SJ-S351-012

5
4
3

6
2
1

JP19

HEADPHONE

ME@

OUT JACK

SINGA_2SJ-S351-013

5
4
3

6
2
1

JP20

10
9

10
9

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2006/08/04 2006/10/06

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

D

Date: Sheet

Compal Electronics, Inc.

AMP & Audio Jack

IGT10/11 LA-3591P

E

0.2

of

30 48Tuesday, March 06, 2007

USB Port

+5VALW

C565 0.1U_0402_16V4Z

12

USB_ON#(33)

C568 0.1U_0402_16V4Z

USB_ON1#(33)

USB_ON#

+5VALW

12

USB_ON1#

2006/10/18

U24

1

GND

2

IN

3

IN

4

EN#

G545C1P1U_SO8

U25

1

GND

2

IN

3

IN

4

EN#

G545A1P1U_SO8

+USB_VCCA

OUT
OUT
OUT
FLG

OUT
OUT
OUT
FLG

8
7
6
5

+USB_VCCB

8
7
6
5

USB Port 1

1000P_0402_50V7K

1

+

C557

C555

150U_D_6.3VM

USB_OC#0 (20)

1

C566

1000P_0402_50V7K@

2

USB20_P2(20)

PSOT24C_SOT23@

For EMI

2

0.1U_0402_16V4Z

3

D23

1

+USB_VCCB

1

1

C558

2

2

2

JP23

1

VCC

2

D-

3

D+

4

GND

5

GND1

6

GND2

7

GND3

8

GND4

SUYIN_020173MR004G565ZR

ME@

USB Port 2

USB20_N6(20)USB20_N2(20)
USB20_P6(20)

C556

150U_D_6.3VM

PSOT24C_SOT23@

1000P_0402_50V7K

1

C561

+

2

0.1U_0402_16V4Z

For EMI

+USB_VCCC

1

1

C562

2

2

2

3

D24

1

JP24

1

VCC

2

D-

3

D+

4

GND

5

GND1

6

GND2

7

GND3

8

GND4

SUYIN_020173MR004G565ZR

ME@

USB Port 3

1

C573

1000P_0402_50V7K@

2

USB_OC#2 (20)

C574 0.1U_0402_16V4Z

12

USB_ON2#(33)

2006/10/18

+5VALW

USB_ON2#

U26

1

GND

2

IN

3

IN

4

EN#

G545A1P1U_SO8

OUT
OUT
OUT

FLG

+USB_VCCC

8
7
6
5

USB board

1000P_0402_50V7K

1

+

C569

C567

150U_D_6.3VM

USB_OC#6 (20)

1

C575

1000P_0402_50V7K@

2

USB20_N0(20)
USB20_P0(20)

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2

0.1U_0402_16V4Z

2006/08/04 2006/10/06

+USB_VCCA

1

1

C570

2

2

JP36

8

G2

567

56G1

4

4

3

3

2

2

1

1

ACES_87212-06G0

ME@

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

Bluetooth & USB CONN.

IGT10/11 LA-3591P

0.2

of

31 48Tuesday, March 06, 2007

5

4

3

2

1

Power BTN

D D

C C

INT_KBD CONN

KSI[0..7]

KSO[0..15]

(Right)

KSI1
KSI7
KSI6
KSO9
KSI4
KSI5
KSO0
KSI2
KSI3
KSO5
KSO1
KSI0
KSO2
KSO4
KSO7
KSO8
KSO6
KSO3
KSO12
KSO13
KSO14
KSO11
KSO10
KSO15

(Left)

KSI[0..7] (33)

KSO[0..15] (33)

JP26

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

ACES_85201-24051

ME@

KSI1
KSI7
KSI6
KSO9
KSI4
KSI5
KSO0
KSI2
KSI3
KSO5
KSO1
KSI0
KSO2
KSO4
KSO7
KSO8
KSO6

KSO3
KSO12
KSO13
KSO14
KSO11
KSO10
KSO15

C576 100P_0402_50V8J@

1 2

C577 100P_0402_50V8J@

1 2

C578 100P_0402_50V8J@

1 2

C579 100P_0402_50V8J@

1 2

C580 100P_0402_50V8J@

1 2

C581 100P_0402_50V8J@

1 2

C582 100P_0402_50V8J@

1 2

C583 100P_0402_50V8J@

1 2

C585 100P_0402_50V8J@

1 2

C586 100P_0402_50V8J@

1 2

C587 100P_0402_50V8J@

1 2

C588 100P_0402_50V8J@

1 2

C589 100P_0402_50V8J@

1 2

C590 100P_0402_50V8J@

1 2

C591 100P_0402_50V8J@

1 2

C592 100P_0402_50V8J@

1 2

C593 100P_0402_50V8J@

1 2

C594 100P_0402_50V8J@

1 2

C595 100P_0402_50V8J@

1 2

C596 100P_0402_50V8J@

1 2

C597 100P_0402_50V8J@

1 2

C598 100P_0402_50V8J@

1 2

C599 100P_0402_50V8J@

1 2

C600 100P_0402_50V8J@

1 2

ON/OFFBTN#(36)

TOP Side

12

J3 JOPEN@

12

J4 JOPEN@

Bottom Side

ON/OFFBTN#

EC_ON(33,41)

1

DAN202U_SC70

EC_ON

R613

10K_0402_5%

100K_0402_5%

D26

1 2

R507

2
3

+EC_DVCC

12

ON/OFF#

51_ON#

2

G

13

D

Q40

2N7002_SOT23

S

2006/12/07

1

2

C584

1000P_0402_50V7K

ON/OFF# (33)
51_ON# (33,39)

12

D27
RLZ20A_LL34

B B

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/08/04 2006/10/06

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

Compal Electronics, Inc.

KBD,ON/OFF,T/P,LED/B,DE BU G

IGT10/11 LA-3591P

1

of

32 48Tuesday, March 06, 2007

0.2

5

L32

+3VALW +EC_AVCC

D D

CLK_PCI_LPC(15)

R5_PME#(28)

C C

PCI_PME#(18)

SIO_PME#(35)

1 2

FBM-11-160808-601-T_0603

@

C610 22P_0402_50V8J

12

C601

0.1U_0402_16V4Z

1 2

L33 FBM-11-160808-601-T_0603

R510 10_0402_5%@

1 2

R516 0_0402_5%@

1 2

R518 0_0402_5%

@

1 2

R608 0_0402_5%

12

+3VALW

2

1

ECAGND

KB_RST#(19)

R515
10K_0402_5%

1 2

1

C602
1000P_0402_50V7K

2

+3VALW

R511 47K_0402_5%

0.1U_0402_16V4Z

EC_PME#

1 2

ECAGND (34)

RB751V_SOD323

2 1

D28

C611

+3VALW

0.1U_0402_16V4Z

2

1

C603

2006/09/11

+3VS

+EC_DVCC

AMP_MUTE_BTN#

1 2

R519 10K_0402_5%

USER_BTN#

1 2

R521 10K_0402_5%

1 2

R522 10K_0402_5%

KSO[0..15](32)

KSI[0..7](32)

EC_NOVO_BTN#

KSO[0..15]
KSI[0..7]

2006/10/31

D50

2

NOVO_BTN#(36)

B B

+5VALW

R530 4.7K_0402_5%
R531 4.7K_0402_5%

+3VS

R534 4.7K_0402_5%
R535 4.7K_0402_5%

A A

+3VALW

1

DAN202U_SC70

1 2
1 2

1 2
1 2

3

2006/12/28

EC_SMB_CK1
EC_SMB_DA1

EC_SMB_CK2

EC_SMB_DA2

EC DEBUG PORT

JP27

EC_TX_P80_DATA
EC_RX_P80_CLK

5

1
2
3
4

ACES_85205-0400

ME@

51_ON# (32,39)

EC_TX_P80_DATA(13,14)
EC_RX_P80_CLK(13,14)

1
2
3
4

1

2

0.1U_0402_16V4Z

PCI_CLKRUN#(20,27,28,35)

EC_THERM#(4,20)
FAN_SPEED1(4)

PWR_SUSP_LED#(36,37)

4

L41

1 2

C604

1

2

GATEA20(19)

SIRQ(20,27,28,35)

LPC_FRAME#(19,35)

LPC_AD3(19,35)
LPC_AD2(19,35)
LPC_AD1(19,35)
LPC_AD0(19,35)

PCI_RST#(18,27,28,35)

EC_SCI#(20)

EC_SMB_CK1(34,40)
EC_SMB_DA1(34,40)

EC_SMB_CK2(4)
EC_SMB_DA2(4,17)

SLP_S3#(20)
PM_SLP_S5#(20)

EC_SMI#(20)

LID_SWITCH#(36)

SUSP#(17,25,28,29,35,38,44,45)

PBTN_OUT#(20)

ON/OFF#(32)

NUM_LED#(37)

4

FBM-11-160808-601-T_0603

0.1U_0402_16V4Z

C605

0.1U_0402_16V4Z

1

2

EC_RST#

EC_SCI#

1 2

R513

0_0402_5% @

KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15
KSO16
KSO17

EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2

EC_PME#

EC_TX_P80_DATA
EC_RX_P80_CLK

XCLKI
XCLKO

C606

1

2

KB_RST#R

LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0

KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7

PM_SLP_S5#
EC_SMI#
LID_SWITCH#
SUSP#

PBTN_OUT#

3

+EC_DVCC

C607

1000P_0402_50V7K

C608

1000P_0402_50V7K

1

1

2

2

U27

1

GA20/GPIO00

2

KBRST#/GPIO01

3

SERIRQ#

4

LFRAME#

5

LAD3

7

LAD2

8

LAD1

10

LPC & MISC

LAD0

12

PCICLK

13

PCIRST#/GPIO05

37

ECRST#

20

SCI#/GPIO0E

38

CLKRUN#/GPIO1D

55

KSI0/GPIO30

56

KSI1/GPIO31

57

KSI2/GPIO32

58

KSI3/GPIO33

59

KSI4/GPIO34

60

KSI5/GPIO35

61

KSI6/GPIO36

62

KSI7/GPIO37

39

KSO0/GPIO20

40

KSO1/GPIO21

41

KSO2/GPIO22

42

KSO3/GPIO23

43

KSO4/GPIO24

44
45
46
47
48
49
50
51
52
53
54
81
82

77
78
79
80

6
14
15
16
17
18
19
25
28
29
30
31
32
34
36

122
123 124

KB926_LQFP128

SA00001J510

Int. K/B

KSO5/GPIO25
KSO6/GPIO26

Matrix

KSO7/GPIO27
KSO8/GPIO28
KSO9/GPIO29
KSO10/GPIO2A
KSO11/GPIO2B
KSO12/GPIO2C
KSO13/GPIO2D
KSO14/GPIO2E
KSO15/GPIO2F
KSO16/GPIO48
KSO17/GPIO49

SCL1/GPIO44
SDA1/GPIO45
SCL2/GPIO46
SDA2/GPIO47

PM_SLP_S3#/GPIO04
PM_SLP_S5#/GPIO07
EC_SMI#/GPIO08
LID_SW#/GPIO0A
SUSP#/GPIO0B
PBTN_OUT#/GPIO0C
EC_PME#/GPIO0D
EC_THERM#/GPIO11
FAN_SPEED1/FANFB1/GPIO14
FANFB2/GPIO15
EC_TX/GPIO16
EC_RX/GPIO17
ON_OFF/GPIO18
PWR_LED#/GPIO19
NUMLED#/GPIO1A

XCLK1
XCLK0 V18R

SM Bus

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

+EC_AVCC

9

22

33

96

111

125

VCC

VCC

VCC

VCC

VCC

VCC

INVT_PWM/PWM1/GPIO0F

ACOFF/FANPWM2/GPIO13

PWM Output

AD Input

DA Output

PS2 Interface

TP_DATA/PSDAT3/GPIO4F

SPI Device Interface

SPI Flash ROM

BATT_CHGI_LED#/GPIO52

GPIO

BATT_LOW_LED#/GPIO54

GPO

GPIO

GPI

GND

GND

GND

GND

GND

11

24

35

94

113

3

67

AVCC

BEEP#/PWM2/GPIO10

FANPWM1/GPIO12

BATT_TEMP/AD0/GPIO38

BATT_OVP/AD1/GPIO39

ADP_I/AD2/GPIO3A

SELIO2#/AD5/GPIO43

DAC_BRIG/DA0/GPIO3C

EN_DFAN1/DA1/GPIO3D

IREF/DA2/GPIO3E

PSCLK1/GPIO4A
PSDAT1/GPIO4B
PSCLK2/GPIO4C

PSDAT2/GPIO4D

TP_CLK/PSCLK3/GPIO4E

SDICS#/GPXOA00
SDICLK/GPXOA01

SDIDO/GPXOA02

SPICLK/GPIO58

CIR_RX/GPIO40

CIR_RLC_TX/GPIO41

FSTCHG/SELIO#/GPIO50

CAPS_LED#/GPIO53
SUSP_LED#/GPIO55

SYSON/GPIO56

VR_ON/XCLK32K/GPIO57

EC_RSMRST#/GPXO03
EC_LID_OUT#/GPXO04

EC_ON/GPXO05

EC_SWI#/GPXO06

ICH_PWROK/GPXO06

BKOFF#/GPXO08

WL_OFF#/GPXO09

PM_SLP_S4#/GPXID1

ENBKL/GPXID2

AGND

69

ECAGND

2006/08/04 2006/10/06

AD3/GPIO3B
AD4/GPIO42

DA3/GPIO3F

SDIDI/GPXID0

SPIDI/RD#

SPIDO/WR#

SPICS#

AC_IN/GPIO59

GPXO10
GPXO11

GPXID3
GPXID4
GPXID5
GPXID6
GPXID7

INVT_PWM

21

BEEP#

23

CHGSEL

26

ACOFF

27

BATT_TEMP

63

BATT_OVP

64
65
66
75
76

DAC_BRIG

68

EN_FAN1

70

IREF

71
72

83
84
85
86

TP_CLK

87

TP_DATA

88

R66510K_0402_5%

97

EN_WOL

98
99
109

FRD#SPI_SO

119

FWR#SPI_SI

120

SPI_CLK

126

FSEL#SPICS#

128

73
74
89
90
91
92
93
95
121
127

100
101

EC_ON

102
103

ICH_POK

104
105
106
107
108

110
112
114
115
116
117

EC_NOVO_BTN#

118

Compal Secret Data

Deciphered Date

12

INVT_PWM
BEEP# (29)
CHGSEL (41)
ACOFF (39,41)

12

C609 0.01U_0402_16V7K

BATT_OVP (41)

APS_X (34)

APS_Y (34)

ADP_I (41)

DAC_BRIG
EN_FAN1 (4)
IREF (41)

EC_EAPD (30)
USB_ON# (31)
USB_ON1# (31)
USB_ON2# (31)

TP_CLK (36)

TP_DATA (36)

2006/12/07

EN_WOL (23)

ITES_ST (34)

FRD#SPI_SO (34)
FWR#SPI_SI (34)

SPI_CLK (34)

FSEL#SPICS# (34)
BT_OFF# (26)
ALI/MH# (40,41)

FSTCHG (41)
CHARGE_LED0# (37)
CAPS_LED# (37)
CHARGE_LED1# (37)
EC_BT_LED# (26)
SYSON (25,38,44)
VR_ON (46)
ACIN (20,39)

EC_RSMRST# (20)
EC_LID_OUT# (20)
EC_ON (32,41)

ICH_POK (7,20)

BKOFF# (22)
RF_OFF# (26)

ITES_EN# (34)
SCROLL_LED# (37)

SLP_S4# (20)
ENBKL (22)

KILL_SW# (36)
AMP_MUTE_BTN# (36)

USER_BTN# (36)

2

ECAGND

BATT_TEMP (40)

2006/12/21

2006/12/07

2006/12/26

R533

0_0402_5%

12

2006/12/22

2

1

Analog Board ID definition,
Please see page 3.

+5VS

TP_CLK

1 2

4.7K_0402_5%

R524

TP_DATA

1 2

4.7K_0402_5%

R526

EC_SWI# (20)

XCLKO XCLKI

R532

1 2

20M_0603_5%@

C614

15P_0402_50V8J

X2 32.768KHZ_12.5P_1TJS125BJ2A251

Compal Electronics, Inc.

Title

ENE-KB925

Size Document Number Rev

Custom

IGT10/11 LA-3591P

Tuesday, March 06, 2007

Date: Sheet

1

IN

NC

2

1

C615

4

OUT

NC

3

15P_0402_50V8J

of

33 48

0.2

GND

+5VALW

12

R542
100K_0402_1%

1

A0

2

A1

3

A2

4

12

R545
100K_0402_1%

2006/10/14
DEL ISA
BIOS

SPI Flash (8Mb*1)

+EC_DVCC

20mils

1

C620

0.1U_0402_16V4Z

SPI_CLK_R

12

R618

10_0402_5%@

1

C1161
18P_0402_50V8J

@

2

FSEL#SPICS#
SPI_CLK

FSEL#SPICS#(33)

SPI_CLK(33)

FWR#SPI_SI(33)

2

12

R547 0_0402_5%

12

R548 33_0402_5%

12

R549 0_0402_5%

EMI

SPI_CS#

+EC_DVCC

ITES_ST(33)

SPI_SO

RB751V_SOD323D47

APS@

100K_0402_5%

SPI_CS#
SPI_CLK_R
SPI_SIFWR#SPI_SI SPI_SO

R652
10K_0402_5%

APS@

R655

U32

8

VCC

3

W

7

HOLD

1

S

6

C

5

D

SST25LF080A_SO8-200mil

JP29

1 2

12

3 4

34

5 6

56

7 8

78

E&T_2941-G08N-00E~D

ME@

+3VALW

1 2

21

12

@

VSS

ECAGND

4

2006/12/28

2

Q

+EC_DVCC

SPI_CLK_R
SPI_SI

+3VS_ITES

1

2

C1177

0.1U_0402_16V4Z

APS@

U40

ST

2

ST

14

Vs

15

Vs

3

COM

5

COM

6

COM

7

COM

ADXL322JCP-REEL_LFCSP16P_4*4

APS@

12

R550 0_0402_5%

+EC_AVCC

47K

2

10K

DTA114YKA_SC59
Q41

APS@

1 3

+3VS_ITES_R

R651
47_0402_5%

APS@

1 2

0.1U_0402_16V4Z

APS@

1

1

C1178

2

2

C1179

0.1U_0402_16V4Z

APS@

12

Xout

10

Yout

1

NC

4

NC

8

NC

9

NC

11

NC

13

NC

16

NC

ECAGND

R653 10K_0402_1%

X

Y

R654 10K_0402_1%

FRD#SPI_SO (33)

ITES_EN# (33)

ECAGND (33)

APS@

1 2
1 2

APS@

0.1U_0402_16V4Z

APS@

C1180

1

2

EC_SMB_CK1(33,40)
EC_SMB_DA1(33,40)

1

C1181

0.1U_0402_16V4Z

APS@

2

ECAGND

+5VALW

1 2

AT24C16AN-10SU-2.7_SO8

APS_X (33)
APS_Y (33)

C618

0.1U_0402_16V4Z

U30

8

VCC

7

WP

6

SCL

5

SDA

SA024160140

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2006/08/04 2006/10/06

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

BIOS & APS

IGT10/11 LA-3591P

of

34 48Tuesday, March 06, 2007

0.2

A

SUPER I/O SMsC LPC47N217

1 1

B

C

+3VS

D

E

F

G

H

I

J

10K_0402_5% @

2 2

R552

Base I/O Address

1 2

*

0 = 02Eh
1 = 04Eh

R554

1K_0402_5%SERP@

1 2

CTS#1
RI#1SIO_SYSOPT
DCD#1
DSR#1

RP15

1 8
2 7
3 6
4 5

4.7K_8P4R_1206_5%

SERP@

+3VS

2006/09/11

3 3

4 4

2006/09/11

5 5

6 6

7 7

8 8

LPC_AD[0..3](19,33)

VTR_PW

CLK_PCI_SIO(15)

A

LPC_AD[0..3]

LPC_AD0
LPC_AD2

LPC_AD3

R558

PCI_CLKRUN#
SIRQ

SERP@

1 2

CLK_14M_SIO

1 2

1 2

R556

LPC_FRAME#
LPC_DRQ#0

1 2

R664 0_0402_5%

10K_0402_5%SERP@

SIO_PD#
CLK_PCI_SIO

SIO_PME#

SIO_SYSOPT

10K_0402_5%SERP@

LPC_FRAME#(19,33)

LPC_DRQ#0(19)

PCI_RST#(18,27,28,33)

1 2

+3VS

PCI_CLKRUN#(20,27,28,33)

SIRQ(20,27,28,33)

R559

VTR_PW

SIO_PME#(33)

CLK_14M_SIO(15)

CLK_PCI_SIO CLK_PCI_DB

10K_0402_5%

+3VS

R555 10K_0402_5%SERP@

1 2

R661 0_0402_5%

Close to u33 pin

CLK_PCI_SIO

12

R604

10_0402_5%@

1

C649
18P_0402_50V8J

@

2

B

CLK_14M_SIO

12

R605
10_0402_5%@

1

C650
10P_0402_25V8K

@

2

U33

10

LAD0

12

LAD1

13

LAD2

14

LAD3

15

LFRAME#

16

LDRQ#

17

PCI_RESET#

18

LPCPD#

19

CLKRUN#

20

PCI_CLK

21

SER_IRQ

6

IO_PME#

9

CLK14

CLOCK

23

GPIO40

24

GPIO41

25

GPIO42

27

GPIO43

28

GPIO44

29

GPIO45

30
31
32
33
34
35
36
40

8
22
43
52 45

GPIO

GPIO46
GPIO47
GPIO10
GPIO11/SYSOPT
GPIO12/IO_SMI#
GPIO13/IRQIN1
GPIO14/IRQIN2
GPIO23

VSS
VSS

POWER

VSS
VSS VCC

LPC47N217_STQFP64

SERP@

SERIAL I/F

FIR

LPC I/F

IRMODE/IRRX3

PARALLEL I/F

RXD1

TXD1

DSR1#

RTS1#
CTS1#
DTR1#

RI1#

DCD1#

IRRX2
IRTX2

INIT#

SLCTIN#

SLCT

BUSY

ACK#

ERROR#

ALF#

STROBE#

VCC
VCC

VCC

PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7

VTR

PE

C

62
63
64
1
2
3
4
5

37
38
39

41
42
44
46
47
48
49
50
51
53
55
56
57
58
59
60
61

0_0805_5%

7
11
26

54

VTR_PW

RXD1
TXD1LPC_AD1
DSR#1
RTS#1
CTS#1
DTR#1
RI#1
DCD#1

+3VS

R607

SERP@

1 2

C651

1

C621

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

SERP@

D

VTR_PW

1 2

SERP@

SERP@

1

2

0.1U_0402_16V4Z

C622

0.1U_0402_16V4Z

VTR_PW

VTR_PW

2

SERP@

C624

0.1U_0402_16V4Z

1

28

2

1

SERP@

C1+

24

C1-

1

C2+

2

C2-

14

TIN1

13

TIN2

12

TIN3

19

ROUT1

18

ROUT2

17

ROUT3

16

ROUT4

15

ROUT5

20

ROUTB2

23

FORCEON

22

FORCEOFF#

SERP@

Compal Secret Data

0.1U_0603_25V7K

SERP@

C626

0.1U_0603_25V7K

SUSP#(17,25,28,29,33,38,43,44,45)

2

C628

1

DTR#1
RTS#1
TXD1
CTS#1

RXD1
DCD#1
DSR#1 RI#DSR#

2006/09/11

+3VS

1

1

C648

C623

2

2

4.7U_0805_10V4Z

SERP@

SERP@

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

E

2006/08/04 2006/10/06

F

40mil

26

VCC

TOUT1
TOUT2
TOUT3

RIN1
RIN2
RIN3
RIN4
RIN5

INVLD#

GND

MAX3243CAI_SSOP28

Deciphered Date

G

U34

27

V+

C625 0.1U_0402_16V4Z

3

V-

C627 0.1U_0402_16V4Z

9
10
11
4
5
6
7
8

21
25

12

SERP@

12

SERP@

DTR#
RTS#
TXD
CTS#
RI#RI#1 TXD_R

DCD#

R560 0_0402_5%

DCD#
DSR#
RXD
RTS#
TXD
CTS#RXD
DTR#

H

1 2

R561 0_0402_5%

1 2

R562 0_0402_5%

1 2

R563 0_0402_5%

1 2

R564 0_0402_5%

1 2

R565 0_0402_5%

1 2

R566 0_0402_5%

1 2

R567 0_0402_5%

1 2

+3VS

JP38

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

11

GND

12

GND

ACES_85201-1005N

@

Title

Size Document Number Rev

Custom

Date: Sheet

SERP@
SERP@
SERP@
SERP@
SERP@
SERP@
SERP@
SERP@

LPC DEBUG PORT

need to add R138(No
SIO sku , and Debug
port is used )

CLK_PCI_DB
LPC_AD0

LPC_AD1
LPC_AD2
LPC_AD3
LPC_FRAME#

PCI_RST#

Compal Electronics, Inc.

RS232_Serial Port

IGT10/11 LA-3591P

I

DCD#_R
DSR#_R
RXD_R
RTS#_R

CTS#_R
DTR#_R
RI#_R

SERIAL PORT

JP30

5
9
4
8
3
7
2

12

6

13

1

FOX_DZ10191-H2-HT

ME@

of

35 48Tuesday, March 06, 2007

J

0.2

5

4

3

2

1

Finger Print

D D

USB20_P8(20)
USB20_N8(20)

+3VS

4.7U_0603_6.3V6M

USB20_P8 USB20_P8_FP
USB20_N8

2

C629

@

1

2006/12/22

For EMI

1

D29
PSOT24C_SOT23

@

2

3

R669

1 2
1 2

R670 27.4_0402_1%

1

C630

0.1U_0402_10V6K

2

C1182 47P_0402_50V8J

USB20_P8_FP
USB20_N8_FP

27.4_0402_1%

USB20_N8_FP

1 2
1 2

C1183 47P_0402_50V8J

JP32

1

1

2

2

3

3

4

4

5

5

6

6

7

GND

8

GND

ACES_85201-06051

@

2006/12/07

T/P Board

JP31

GND
GND

ACES_85201-06051

1

1

2

2

3

3

4

4

5

5

6

6

7
8

ME@

+5VS

3

1

2

D42
PSOT24C_SOT23

@

TP_CLK (33)
TP_DATA (33)

Kill Switch

C C

PWR_SUSP_LED#(33,37)

SW Board

+5VALW

JP35

1 2

12

3 4

34

5 6

56

7 8

78

9 10

910

11 12

11 12

13 14

13 14

15 16

15 16

ACES_88018-1610

ME@

USER_BTN#
AMP_MUTE_BTN#

NOVO_BTN#
ON/OFFBTN#

USER_BTN# (33)
AMP_MUTE_BTN# (33)
NOVO_BTN# (33)
ON/OFFBTN# (32)

+3VS

KILLSW@

1 2

KILL_SW#(33)

R568 10K_0402_5%

KILL_SW#

SW3

3

5

3G1G2

4

2

2

1

1

1BS003-1211L_3P

KILLSW@

LID Switch

B B

+3VALW

12

R629

2

1

3

D44

@

PSOT24C_SOT23

100K_0402_5%

LID_SWITCH# (33)

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/08/04 2006/10/06

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

Compal Electronics, Inc.

FP/SW/TP

IGT10/11 LA-3591P

1

0.2

of

36 48Tuesday, March 06, 2007

Lid Switch

Change P/N : SN111000207

SW6

MPU-101-81_4P

1

2

5

3

4

A A

5

D D

SDCLK_MSCLK

12

R619
10_0402_5%@

1

C1162
10P_0402_25V8K

@

2

C C

Front LEDs

+5VS

D33

WIRELESS_LED#(26)

BTONLED(26)

B B

CHARGE_LED0#(33)

CHARGE_LED1#(33)

PWR_SUSP_LED#(33,36)

1 2

R576 300_0402_5%

1 2

R577 300_0402_5%

1 2

R581 300_0402_5%

1 2

R582 300_0402_5%

1 2

R650 300_0402_5%

CHARGE0

CHARGE1

21

D34

HT-191NB_BLUE_0603

21

HT-191UD_AMBER_0603

D41 HT-191NB_BLUE_0603

D45

D46 HT-191NB_BLUE_0603

21

21

HT-191UD_AMBER_0603

21

+5VALW

+5VALW

4

SDDATA0_MSDATA0(28)

SDDATA3_MSDATA3(28)

SDDATA1_MSDATA1(28)

SDDATA0_MSDATA0(28)
SDDATA3_MSDATA3(28)

SDDATA2_MSDATA2(28)

SD_MSDATA1(28)
SD_MSDATA2(28)

SDCLK_MSCLK
SDWP#_XDRB#(28)

SDCMD_MSBS(28)

SDCD#_XDCD0#(28)

+VCC_SD

MSCD#_XDCD1(28)

SDCMD_MSBS(28)

SWAP BY EC

SCROLL_LED#(33)

ODD_LED#(25)
SATA_LED#(19)

NUM_LED#(33)

CAPS_LED#(33)

SDDATA0_MSDATA0
SD_MSDATA1
SD_MSDATA2
SDDATA3_MSDATA3

SDWP#_XDRB#
SDCMD_MSBS
SDCD#_XDCD0#

SDDATA1_MSDATA1

MSCD#_XDCD1

SDDATA0_MSDATA0

SDCMD_MSBS
SDDATA3_MSDATA3
SDDATA2_MSDATA2

ODD_LED#

1

SATA_LED#

2

3

3 in 1 Card Reader

+VCC_SD

R572
22_0402_5%

R573 22_0402_5%

DRIVE_LED#

4

Y

SDCLKSDCLK_MSCLK

MSCLKSDCLK_MSCLK

D32

HT-191NB_BLUE_0603
D35

HT-191NB_BLUE_0603
D36

HT-191NB_BLUE_0603

1 2

R6280_0402_5%

1 2
1 2

1 2

R575 300_0402_5%

1 2

R578 300_0402_5%

1 2

R579 300_0402_5%

+5VS

53

U36

PG

B
A

TC7SH08FUF_SSOP5

JP33

6

VDD_SD

9

DAT0_SD

10

DAT1_SD

2

DAT2_SD

3

CD/DAT3_SD

7

CLK_SD

11

WP_SD

4

CMD_SD

1

CD_SD

5

VSS_SD

8

VSS_SD

19

VCC_MS

13

VCC_MS

14

SCLK_MS

16

INS_MS

18

SDIO_MS

20

BS_MS

15

RESERVED_MS

17

RESERVED_MS

21

VSS_MS

12

VSS_MS

22

GND

23

GND

PROCO_MDR019-C0-1202

@

+5VS

21

21

21

+5VS

1 2

D39

21

HT-191NB_BLUE_0603

R583
300_0402_5%

CF1

CF9

CF17

1

1

1

CF2

@

CF10

@

CF18

@

H1
HOLEA

1

H6
HOLEA

1

H11
HOLEA

1

H16
HOLEA

1

H23
HOLEA

1

H30
HOLEA

1

2

CF7

CF3

CF4

CF5

@

@

@

1

1

CF11

@

1

1

@

1

H2
HOLEA

H7
HOLEA

H12
HOLEA

H17
HOLEA

H26
HOLEA

H31
HOLEA

@

1

1

CF13

CF12

@

@

@

1

1

H3
HOLEA

1

1

H8
HOLEA

1

1

H13
HOLEA

1

1

H24
HOLEA

1

1

H27
HOLEA

1

1

H32
HOLEA

1

1

CF6

CF14

@

1

@

1

H4
HOLEA

H9
HOLEA

H14
HOLEA

H25
HOLEA

1

H28
HOLEA

1

CF15

1

1

1

1

1

H33
HOLEA

1

@

@

CF8

1

CF16

1

H5
HOLEA

H10
HOLEA

H15
HOLEA

H22
HOLEA

1

H29
HOLEA

1

@

@

1

1

1

H34
HOLEA

1

1

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/08/04 2006/10/06

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

Compal Electronics, Inc.

INDICATE LED

IGT10/11 LA-3591P

1

0.2

of

37 48Tuesday, March 06, 2007

A

=

1 1

2 2

SUSP

3 3

B

10U_0805_10V4Z

Q28

2N7002_SOT23

C633

1

2

+VSB

12

R585
22K_0402_5%

13

D

2

G

S

C

+5VALW to +5VS Transfer

+5VALW +5VS

U37

S

D

S

D

S

D

G

D

SI4800DY_SO8

1
2
3
4

8
7

1

6
5

2

RUNON

C636

0.1U_0603_25V7K

1

C634
10U_0805_10V4Z

2

D

0.1U_0402_16V4Z

1

C635

2

E

F

SUSP(45)

SUSP#(17,25,28,29,33,35,44,45)

10K_0402_5%

R678

SUSP

G

+5VALW

12

R586
10K_0402_5%

13

D

Q29

2

G

2N7002_SOT23

S

1 2

+1.5VSP

H

Q42
SI7326DN-T1-E3_PAK1212-8

+3VS_GATE

4

SYSON(25,33,44)

+1.5VS

1
2
35

LAN_LDO@

SYSON#

I

+5VALW

12

R584
47K_0402_5%

13

2

Q27

DTC124EK_SC59

J

+3VALW to +3VS Transfer

+3VALW

U38

8

S

D

7

+VSB

4 4

SUSP

10U_0805_10V4Z

12

R587
33K_0402_5%

13

D

Q30

2

G

2N7002_SOT23

S

C637

1

2

1

C640

0.1U_0603_25V7K

2

D

6

D

5

D

SI4800DY_SO8

+3VS_GATE

S
S
G

+3VS

1

C638
10U_0805_10V4Z

2

1 2

0.1U_0402_16V4Z

1

C639

2

RUNON

0_0402_5%@

R673

12K_0402_1%

LAN_LDO@

1 2

1
2
3
4

R591

5 5

+1.8V to +1.8VS Transfer

+1.8V

U39

S

D

S

D

S

D

G

D

SI4800DY_SO8

VGA@

1
2
3
4

R596

6 6

7 7

SUSP

+VSB

10U_0805_10V4Z

R595
47K_0402_5%

VGA@

1 2

13

D

Q37

2

G

2N7002_SOT23

S

VGA@

C641

VGA@

1

2

1

C644

0.1U_0603_25V7K

VGA@

2

6
5

8
7

8 8

A

B

C

+1.8VS

1

C642

VGA@

10U_0805_10V4Z

2

1 2

VGA@

0.1U_0402_16V4Z

1

C643

2

RUNON

0_0402_5%@

D

+5VS

12

R588
470_0402_5%

13

D

2

G

Q31

S

2N7002_SOT23

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

E

+1.8V

12

R592
470_0402_5%

13

D

S

2

G

Q34

2N7002_SOT23

+1.8VS

12

R589
470_0402_5%

VGA@

13

SYSON#SUSP

2006/08/04 2006/10/06

D

2

G

Q32

S

2N7002_SOT23

VGA@

Compal Secret Data

F

U41

7

8

SUSP

Deciphered Date

+5VALWP

POK

EN

12

C1184
1U_0603_6.3V6M

LAN_LDO@

6

5

VIN

4

VOUT

VCNTL

3

VOUT

2

FB

9

VIN

GND

LAN_LDO@

1

APL5912-KAC-TRL_SO8

+1.25VS

12

R597
470_0402_5%

13

D

S

G

SUSP

2

G

Q38
2N7002_SOT23

+1.5VSP_LAN

1

C1185
10U_0805_10V4Z

2

LAN_LDO@

1K_0402_1%

H

+1.2V_LAN

1

12

R674

+0.9VS

12

13

D

S

R590
470_0402_5%

12

C1187

LAN_LDO@

12

0.01U_0402_25V7K

R675

2K_0402_1%

LAN_LDO@

SUSP

2

G

Q33
2N7002_SOT23

Title

DC/DC Circuit

Size Document Number Rev

Custom

IGT10/11 LA-3591P

Date: Sheet

C1186
10U_0805_10V4Z

2

LAN_LDO@

LAN_LDO@

+2.5VS

12

R594
470_0402_5%

VGA@

13

D

S

SUSP

2

G

Q36
2N7002_SOT23

VGA@

+3VS

D

S

Compal Electronics, Inc.

I

12

R593
470_0402_5%

13

2

G

Q35
2N7002_SOT23

SUSP

0.2

of

38 48Tuesday, March 06, 2007

J

OCP==>8A
Vripple=

A

DC231000400

PJP1

1

1

6

G

5

G

4

G

3

G

1 1

2 2

SINGA_2DC-G213-B20

2

2

PR5
10K_0402_1%@

1 2

VIN

12

PR11

PR14
22K_0402_1%

84.5K_0402_1%

1 2

12

12

PR15

PC6

20K_0402_1%

1000P_0402_50V7K

12

PC7

0.1U_0402_16V7K

3
2

PR17
10K_0402_1%

PR9
1M_0402_1%

1 2

VS

84

PG

+

O

-

PU1A
LM393DG_SO8

12

ADPIN

12

PC5

0.01U_0402_25V7K@

1 2

1

RTCVREF

PC1

1000P_0402_50V7K

HCB4532KF-800T90_1812

3.3V

1 2

12

PC2

100P_0402_50V8J

VS

PL1

12

12

PR10

10K_0402_1%

PD3

RLZ4.3B_LL34

12

12

PR16

10K_0402_1%

B

12

PC3

PC4

100P_0402_50V8J

1000P_0402_50V7K

PR12
1K_0402_1%

1 2

PACIN

ACIN (20,33)

PACIN (41)

Vin Detector
High 18.764 17.901 17.063

Low 17.745 16.9 16.03

C

ACIN

VIN

12

PR1

10_1206_5%

@

12

PD1

RLZ24B_LL34

@

Precharge detector
Min. typ. Max.

H-->L 14.589V 14.84V 15.243V
L-->H 15.562V 15.97V 16.388V

PR2
1K_1206_5%

1 2

VIN

PD2
RLS4148_LLDS2

12

ACOFF(33,41)

PR3
1K_1206_5%

1 2

PR4
1K_1206_5%

1 2

PR8
1K_1206_5%

1 2

12

PR6

100K_0402_5%

13

2

BATT ONLY

H-->L 6.138V 6.214V 6.359V
L-->H 7.196V 7.349V 7.505V

12

PR7

100K_0402_5%

PQ2
DTC115EUA_SC70-3

2

Precharge detector
Min. typ. Max.

D

PQ1

TP0610K-T1-E3_SOT23-3

13

2

12

PR13

100K_0402_5%

13

PQ3
DTC115EUA_SC70-3

B+

VIN

VL

PD5

RLS4148_LLDS2

PR29
22K_0402_1%

1 2

+1.8V

+0.9VS

+2.5VS

12

12

12

PR26

PC10

100K_0402_5%

2

0.22U_1206_25V7K

PQ4

TP0610K-T1-E3_SOT23-3

+1.05VSP

1 2

(16A,800mils ,Via NO.= 24)

PAD-OPEN 3x3m

+1.8VP

1 2

(8A,320mils ,Via NO.= 16)

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

B

12

51_ON#(32,33)

PJ3

PAD-OPEN 3x3m

BATT+

CHGRTCP

3.3V

RTCVREF

PR23
560_0603_5%

1 2

3 3

+CHGRTC

1 2

PR24
560_0603_5%

PJ2
PAD-OPEN 3x3m

12

PC9

21

G920AT24U_SOT89-3
PU2

3

OUT

4.7U_0805_6.3V6K

+1.5VS+1.5VSP

GND

PR25
200_0805_5%

2

IN

1

+1.8VP

12

PC8

1U_0805_25V4Z

1 2

(7A,280mils ,Via NO.=14) (8A,320mils ,Via NO.= 16)

PJ5
PAD-OPEN 3x3m

+5VALWP

1 2

(6A,240mils ,Via NO.= 12)

4 4

+3VALWP

PJ7
PAD-OPEN 3x3m

1 2

(6A,240mils ,Via NO.=12)

PJ9
PAD-OPEN 3x3m

+1.25VSP +1.25VS

1 2

(6A,240mils ,Via NO.=12)

+5VALW

+3VALW

A

+0.9VSP

(2A,80mils ,Via NO.= 4)

+2.5VSP

(1A,40mils ,Via NO.= 2)

+VSBP +VSB

(0.3A,40mils ,Via NO.= 2)

PJ6
PAD-OPEN 3x3m

1 2

PJ8

1 2

12

JUMP_43X79

PJ10
PAD-OPEN 3x3m

1 2

1 2
12

12

PR21

PR20

68_1206_5%

13

12

PJ4
PAD-OPEN 3x3m

PJ15

PD4

RLS4148_LLDS2

VS

68_1206_5%

PC11

0.1U_0603_25V7K

12

PD6

MAINPWON(40,42)

ACON(41)

2
3

RB715F_SOT323-3

1

12

RTCVREF

+VCCP

+1.05VSP

(16A,800mils ,Via NO.= 24)

+1.8V

+1.5VSP +1.5VSP_LAN

(6A,240mils ,Via NO.=12)

2005/10/17 2006/10/17

PJ14
PAD-OPEN 3x3m

1 2

PJ16
PAD-OPEN 3x3m

1 2

Compal Secret Data

Deciphered Date

C

+VCCP

PR22

100K_0402_1%

PC13

0.1U_0603_25V7K

LM393DG_SO8

7

O

PU1B

PR30
34K_0402_1%

PR18

2.2M_0402_5%

VS

84

5

PG

+

6

-

12

12

@

12

12

PR19

499K_0402_1%

12

PR27

D

S

12

191K_0402_1%

PRG++

PQ5

13

RHU002N06_SOT323-3

2

G

13

Compal Electronics, Inc.

DCIN/DECTOR

PC14

1000P_0402_50V7K

PR32

66.5K_0402_1%

Title

Size Document Number Rev

B

Date: Sheet

PR31
47K_0402_5%

PQ6
DTC115EUA_SC70-3

2

D

12

PR28

499K_0402_1%

12

12

39 48Tuesday, March 06, 2007

PC12

0.01U_0402_25V7K

PACIN(41)

+5VALWP

of

0.2

A

DC040003L00

TYCO_1909383-1

9

GND

1 1

PJP2

@

7
6GND
5
4
3
2
1

BATT++

7

CNT1

68

CNT2

5

TS_A

4

EC_SMDA

3

EC_SMCA

2

GND

1

PR36

1 2

PR34

1 2

1K_0402_1%

1K_0402_1%

1 2

12

12

PR46

1K_0402_1%

PR40

PR44

6.49K_0402_1%

100_0402_1%

2 2

12

PR41

100_0402_1%

B

BATT++

PJ11
PAD-OPEN 3x3m

1 2

1 2

PR33

47K_0402_1%

+3VALWP

12

PC15

12

PC16

1000P_0402_50V7K

1000P_0402_50V7K

12

ALI/MH# (33,41)

+3VALWP

BATT_TEMP (33)

EC_SMB_DA1 (33,34)

PC17

0.01U_0603_50V7K

C

BATT+

PH1 under CPU botten side :

D

CPU thermal protection at 85 degree C
Recovery at 70 degree C

12

PC19

VL

12

12

1000P_0402_50V7K

PR38

10.7K_0402_1%

PR42

61.9K_0603_1%

1 2

TM_REF1

PH1

12

100K_0603_1%_TH11-4H104FT

12

PC20

1U_0603_6.3V6M

PC18

12

0.1U_0603_25V7K

3

+

2

-

PR43
150K_0402_1%

PR45

150K_0402_1%

VS

PR39

442K_0603_1%

1 2

84

PU5A

PG

1

0

LM358ADR_SO8

12

VL

PD18

1 2

1SS355TE-17_SOD323-2

VL

PR37

1 2

150K_0402_1%

MAINPWON (39,42)

EC_SMB_CK1 (33,34)

PQ7

TP0610K-T1-E3_SOT23-3

12

+VSBP

PC22

0.1U_0603_25V7K

B+

12

12

PC21

PR47

PR48

VL

22K_0402_1%

1 2

100K_0402_5%

0.22U_1206_25V7K

13

2

3 3

SPOK(42,43)

PR49

100K_0402_5%

1 2

1 2

PR50
0_0402_5%

13

D

G

PQ8
RHU002N06_SOT323-3

S

2

12

PC23

0.1U_0402_16V7K

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

B

2005/10/17 2006/10/17

Compal Secret Data

Deciphered Date

C

Title

Size Document Number Rev

B

Date: Sheet

Compal Electronics, Inc.

BATTERY CONN. / OTP

D

40 48Tuesday, March 06, 2007

of

0.1

A

65W, Iadapter=0~3.42A, Current sense=0.02ohm, PR69=39.2K, CP=3.079A
90W, Iadapter=0~4.74A, Current Sense=0.015ohm, PR69=28.7K, CP=4.263A

P2

PQ10

AO4407_SO8

VIN

1 1

12

PR53
47K_0402_1%

2

PQ17

13

D

RHU002N06_SOT323-3

2

G

S

2 2

3 3

PACIN(39)

ACOFF(33,39)

CP mode

Iinput=(1/0.02)(0.05*Vaclm/2.39+0.05)
where Vaclm=0.5535V, Iinput=3.079A
where Vaclm=0.6667V, Iinput=4.263A

8
7

5

2

13

1 3

PQ14
DTC115EUA_SC70-3

ADP_I = 19.9*Iadapter*Rsense

PR66

22K_0402_5%

PACIN

1 2

ACON

2

1
2
36

4

12

PC28

PQ12
DTA144EUA_SC70-3

0.1U_0603_25V7K

PR60

150K_0402_1%

2

G

13

Be careful the
IREF voltage!!

PQ21

DTC115EUA_SC70-3

CC=0.6~3.4A
VCHLM=0.24V~1.36V
IREF=0.972*Icharge
IREF=0.5832V~3.3V

BATT Type

2800mAH 4S pack

4 4

2800mAH 3S pack

Normal 4S LI-ON Cells

Normal 3S LI-ON Cells

Wake up charge while
no communication

Charging Voltage
(0x15)

17400mV

13050mV

16800mV

12600mV

- HIGH HIGH 12.60V

A

PQ11
AO4407_SO8

1
2
3 6

12

PR54 200K_0402_1%

6251VDD

12

ALI/MH#(33,40)

13

D

PQ19
RHU002N06_SOT323-3

S

IREF(33)ACON(39)

ALI/MH#

LOW

HIGH

LOW

HIGH

4

PC29

FSTCHG(33)

1 2

PR58

10K_0402_1%

2

PQ15

DTC115EUA_SC70-3

0.01U_0402_25V7K

PR68

143K_0402_1%

PR70

100K_0402_1%

6251VREF

PR74

100K_0402_1%@

CHGSEL(33)

CHGSEL

LOW

LOW

HIGH

HIGH

P3

8
7

5

TP0610K-T1-E3_SOT23-3

VIN

12

1 2

PR207

100K_0402_1%

5600P_0402_25V7K

13

PC38

1 2

ADP_I

12

12

12

PC44

12

1 2

10K_0402_1%

PD17

PR57

1 2

100P_0402_50V8J

0.01U_0402_25V7K

1SS355TE-17_SOD323-2

PC35

680P_0402_50V7K@

1 2

1 2

PC36 6800P_0402_25V7K

PR63
10K_0402_1%

1 2

0.1U_0402_16V7K

6251VREF

2

Charge Voltage

3S CC-CV MODE : 12.6V (CELLS=GND , ALI/MH#=3.3V)
4S CC-CV MODE : 16.8V (CELLS=VDD , ALI/MH#=0V)

CV mode

17.20V

12.90V

16.80V

12.60V

B

B+

PR51

12

PC39

PQ44

PC40

1 2

SI2301BDS-T1-E3_SOT23-3@

1
2

1 2

0.015_2512_1%

PR208 100K_0402_1%

2

1 2

6251VDD

12

PR59

PR64

1 2

100_0402_1%

6251VREF

PR69

28.7K_0402_1%

12

PR72
10K_0402_1%

13

1 2

PR73

274K_0402_1%@

PQ22

4
3

DCIN

13

PC31

CHGEN

100K_0402_1%

12

1

2.2U_0603_6.3V6K

2

3

4

5

6

7

8

9

10

11

13

PQ45 DTC115EUA_SC70-3

PU4

DCIN

ACPRN

CSON

CSOP

CSIN

CSIP

PHASE

UGATE

BOOT

VDDP

LGATE

PGNDGND

24

23

22

21

20

19

18

17

16

15

14

1312

VDD

ACSET

EN

CELLS

ICOMP

VCOMP

ICM

VREF

CHLIM

ACLIM

VADJ

ISL6251AHAZ-T_QSOP24

2

RB715F_SOT323-3

Add EPA function

DCIN

LX_CHG1

BST_CHG BST_CHGA

6251VDDP

DL_CHG

If this area float, Charge voltage is 4.2V/cell

BATT_OVP(33)

OVP voltage :

LI-3S :13.50V--BATT-OVP=1.5V
BATT-OVP=0.111*BATT+

Security Classifi c a t i o n

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

65W PQ10,PQ11,PQ9->FDS4435

PL2

FBMA-L11-322513-151LMA50T_1210

1 2

CSIN

CSIP

PD16

FSTCHG

2

1

SUSP#

3

12

PC161

0.1U_0603_25V7K

1 2

PC34

PR247

0.047U_0603_16V7K

1 2

1 2

PR61

20_0603_1%

PR62 20_0603_1%

PC37 0.1U_0603_25V7K

1 2

1 2

PR248 2.2_0603_1%

DH_CHG

PR67

1 2

2.2_0603_5%

PC45

1 2

4.7U_0805_6.3V6K

PR77

10K_0402_1%

1 2

12

PC47

@

0.01U_0402_25V7K

20_0603_1%

12

12

1SS355TE-17_SOD323-2

PC24

SUSP#(32,33)

PC41

12

0.1U_0603_25V7K

PD10

6251VDD

1 2

4.7_0603_5%
PR71

7

0

Compal Secret Data

Deciphered Date

10U_1206_25V6M

84

C

CHG_B+

12

PC25

10U_1206_25V6M

CSON

CSOPCSON

VS

PU5B

5

PG

+

6

-

LM358ADR_SO8

12

PC26

1 2

0_0402_5%

12

PC27

0.1U_0603_25V7K
2200P_0402_50V7K

PR227

BATT+

12

340K_0402_1%

12

499K_0402_1%

12

105K_0402_1%

12

DTC115EUA_SC70-3

876

5

DDD

D

PQ18

SI4800BDY-T1-E3_SO8

SSS

G

4

5

D

G

4

PR75

PR76

PR78

If charge current is small,
you can change to 16uH choke.

123

LX_CHG2

10UH_SIL1045RA-100PF_4.5A_30%

876

DDD

PQ20

SI4800BDY-T1-E3_SO8

SSS

123

12

0.01U_0402_25V7K

2007/05/182006/05/18

D

PQ9
AO4407_SO8

1
2
3 6

PR55

10K_0402_1%

PQ13

PL3

1 2

20K_0402_1%

PC48

PR210

8
7

5

4

PR52

47K_0402_1%

1 2

1 2

13

2

CHG

@

PR209 100K_0402_1%

1 2

Overshoot solution during CC<->CV

2

B

12

@

Title

Size Document Number Rev

Date: Sheet

VIN

PD7

1 2

1SS355TE-17_SOD323-2

PR56

1 2

200K_0402_1%

12

PC33

0.1U_0603_25V7K

4
3

6251VREF

PC162 0.01U_0402_25V7K@

CSON

CHGEN

PQ46
2SC2411K_SC59

@

13

D

RHU002N06_SOT323-3

S

PD9

1 2

1SS355TE-17_SOD323-2

1
2

PR65

0.02_2512_1%

1 2

1

C

E

3

Compal Electronics, I n c.

CHARGER

CHARGER

D

ACOFF (33,39)

PQ16

2

G

12

VIN

PACIN (39)

12

PC42

10U_1206_25V6M

41 48Tuesday, March 06, 2007

of

BATT+

PC43

10U_1206_25V6M

1.0

A

B

C

D

B+

PL4
HCB4532KF-800T90_1812

1 2

1 1

B+++

876

DDD

SSS

123

PC51

12

2200P_0402_50V7K

PC52

12

12

PC53

4.7U_1206_25V6K

4.7U_1206_25V6K

876

DDD

SSS

123

PL5

2 2

+5VALWP

1

+

PC62

2

150U_V_6.3VM_R18

10UH_SIL1045RA-100PF_4.5A_30%

1 2

PR90

1 2

10.5K_0402_1%

PR92

1 2

6.81K_0402_1%

VS

PZD1
RLZ5.1B_LL34

1 2

+5V Ipeak = 6.66A ~ 10A

3 3

5

D

PQ23

G

4

5HG

5

D

PQ25

G

4

DL5

PC49

1 2

0.1U_0402_16V7K

SI4800BDY-T1-E3_SO8

1 2

SI4810BDY-T1-E3_SO8

PR93
47K_0402_5%

1 2

PR83
0_0603_5%

PR96

1 2

LX5

100K_0402_5%

DH5

12

PC64

0.047U_0603_16V7K

PR79

0_0603_5%

1 2

PR99
47K_0402_5%

1 2

BST5A

1 2

@

1 2

12

12

PC67

PR91
0_0402_5%

8734_VREF

PR94

0_0402_5%

PR211
0_0402_5%

0.047U_0603_16V7K

2

3

CHP202UPT_SOT323-3

1

PD11

B+++

12

PR81

12

VL

12

PC60

4.7U_0805_6.3V6K

14

BST5

16

DH5

15

LX5

19

DL5

21

OUT5

9

FB5

1

N.C.

MAX8734AEEI+_QSOP28

6

SHDN#

4

ON5

3

ON3

8

REF

12

PC65

0.22U_0603_16V7K

4.7_1206_5%

PC58

1U_0805_25V4Z

20

18

V+

LD05

PU6

GND

23

PC66

12

PR82

4.7_1206_5%

@

PC61

12

0.1U_0603_25V7K

13

TON

LDO3

25

12

4.7U_0805_6.3V6K

1 2

PGOODSKIP#

PRO# VCC

10 17

1 2

VL

PR80

ILIM3

ILIM5
BST3

OUT3

PR97

47_0402_5%

DH3
DL3

FB3

0_0402_5%

12

LX3

VFB=2V

12

8734_VREF

PC59

1U_0805_16V7K

5

11
28

26
24
27
22

7
212

SPOK(40,43)

PC54

BST3BBST5B

0.1U_0402_16V7K

PR85

PR86

200K_0402_1%

1 2

200K_0402_1%

1 2

PR88

PR89

1 2

499K_0402_1%

499K_0402_1%

1 2

PR84

0_0603_5%

1 2

BST3A

1 2

PC50 0.1U_0402_16V7K

B+++

DH3

12

PC55

12

PC56

PC57

2200P_0402_50V7K

4.7U_1206_25V6K

PR87

0_0603_5%

1 2

12

4.7U_1206_25V6K

LX3

DL3

3HG

876

5

DDD

D

PQ24

SSS

G

123

4

SI4800BDY-T1-E3_SO8

876

5

DDD

D

PQ26

SSS

G

123

4

SI4810BDY-T1-E3_SO8

PL6

10UH_SIL1045RA-100PF_4.5A_30%

1 2

+3VALWP

PR95

1 2

6.49K_0402_1%

PR98

1 2

10K_0402_1%

1

+

PC63

2

150U_V_6.3VM_R18

+3.3V Ipeak = 6.66A ~ 10A

MAINPWON (39,40)

12

PC68

1U_0603_6.3V6M

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

B

2005/10/17 2006/10/17

Compal Secret Data

Deciphered Date

C

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

+5VALWP/+3VALWP

D

42 48Tuesday, March 06, 2007

of

0.1

5

PJ17

B+

D D

SPOK(40,42)

SUSP#(17,25,28,29,33,35,38,44,45)

C C

B B

SUSP#(17,25,28,29,33,35,38,44,45)

1U_0603_6.3V6M@

JUMP_43X118@

PR228

0_0402_5%@

1 2

PR218

0_0402_5%

1 2

+1.5VSP

PR224

0_0402_5%

1 2

PC177

12

12

12

PJ18

12

JUMP_43X79

@

12

PC174
10U_0805_6.3V6M

12

12

12

+5VALWP

PC163

10U_1206_25V6M

PC169

0.1U_0402_16V7K

@

12

PC173
1U_0603_6.3V6M

PU13

6

VCNTL

5

VIN

9

VIN

8

EN

7

POK

12

PC164

10U_1206_25V6M

3

VOUT

4

VOUT

2

FB

GND

APL5913-KAC-TRL_SO8

1

4

6269_1.5V

12

PC166

2.2U_0603_6.3V6K

12

PC170

22P_0402_50V8J

1.15K_0402_1%
PR225

4

5

PC172

6800P_0402_25V7K

12

0.01U_0402_25V7K

12

PR226

2K_0402_1%

6269_1.5V

PR214

10K_0402_1%

8

PU12

GND

VCC

EN

COMP

6

12

PR221

49.9K_0402_1%

12

12

PC176

12

2

PGOOD

FB

7

PR222

57.6K_0402_1%

12

PC175

1

PHASE

22U_1206_6.3V6M

PHASE_1.5V

16

FSET

9

12

BOOT_1.5V

15

UG

BOOT

PVCCVIN

PGND

ISEN

VO

ISL6268CAZ-T_SSOP16

10

12

+1.25VSP

PR212
0_0603_5%

1 2

1 2

PR213 0_0603_5%

+5VALWP

12

143

2.2U_0603_6.3V6K

13

LG

12

ISEN_1.5V

11

PC171

0.01U_0402_25V7K

OCP==>3A

3

1 2

PC82 0.1U_0402_16V7K

PR215
0_0603_5%

PR216

4.7_0603_5%

1 2

PC165

1 2

LG_1.5V

1 2

PR219

4.42K_0402_1%

6269_1.5V

2

876

5

DDD

D

PQ47

SSS

G

123

4

SI4800BDY-T1-E3_SO8

1.8UH_SIL104R-1R8PF_9.5A_30%
PL16

1 2

PR217

4.7_1206_5%

PC168
680P_0603_50V7K

PR220

2.26K_0402_1%

1 2

12

PR223

1.5K_0402_1%

876

5

DDD

D

1 2

PQ48

SSS

G

123

4

SI4810BDY-T1-E3_SO8

1 2

1

+

PC167

220U_D2E_4VM_R15M

2

+1.5VSP

+1.5VSP

1

OCP==>7A~~8.5A
Vripple==>40mV

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/10/17 2006/10/17

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

2

Date: Sheet

1.5VSP/1.25VSP

Tuesday, March 06, 2007

0.1

of

43 48

1

5

D D

4

3

2

1

4.7U_1206_25V6K

PR240

PL10

1 2

Discrete use 220u_4V_R15
UMA use 330u_2.5V_R15

12

PC188

0.01U_0402_25V7K

1 2

1 2

B+

12

1.82K_0402_1%

12

PR241

PR245
10K_0402_1%

+1.05V

+1.05VSP

1

+

PC113

2

1

+

PC158

2

220U_V_4VM_R15M

330U_D2_2.5VY_R15M@

HCB4532KF-800T90_1812

12

PR229

PC95

4.7U_0805_6.3V6K

876

5

DDD

SYSON25,29,31,33

SSS

123

876

DDD

SSS

123

D

G

4

DH_1.8V-2

5

D

PQ32
SI4810BDY-T1-E3_SO8

G

4

C C

B B

+1.8V

+1.8VP

1

+

PC98
220U_D2E_4VM_R15M

2

10K_0402_1%

PR235

10.5K_0402_1%

PR242

12

12

PL11

1 2

1.8UH_SIL104R-1R8PF_9.5A_30%

12

PC186

0.01U_0402_25V7K

PR238
0_0402_5%

1 2

PR116

0_0402_5%@

1 2

PQ31

SI4800BDY-T1-E3_SO8

LX_1.8V

12

PR129

4.7_1206_5%

12

PC102

680P_0603_50V7K

4.7U_1206_25V6K

PC180

PC185

0.1U_0402_16V7K

2K_0402_1%

1 2

PR127

0_0402_5%

4.7U_1206_25V6K

12

BST_1.8V-1

12

1 2

0_0603_5%

1 2

PR126

0_0603_5%
PR236

12

1

2

3

PC183

0.01U_0402_25V7K

PR231

ISE_1.8V
DL_1.8V

12

PC99

0.01U_0402_25V7K

@

0.1U_0603_25V7K
PD19

DAP202U_SOT323

12

12

PC96

0_1206_5%

12

PC181

BST_1.05V-1

PU14

12

12

SOFT1

6

BOOT1

5

UGATE1

4

PHASE1

7

ISEN1

2

LGATE1

3

PGND1

9

VOUT1

10

VSEN1

8

EN1

15 16

PG1 PG2/REF

11

OCSET1

12

PR246
124K_0402_1%

+5VALWP

14

VIN

GND

1

PR230

2.2_0603_5%

1 2

28

17

SOFT2

VCC

23

BOOT2

24

UGATE2

25

PHASE2

22

ISEN2

27

LGATE2

26

PGND2

20

VOUT2

19

VSEN2

21

EN2

18

OCSET2

DDR

ISL6227CAZ-T_SSOP28

13

12

PC182

2.2U_0805_10V6K

PC184

0.01U_0402_25V7K

12

BST_1.05V-2BST_1.8V-2

1 2

PR249
0_0603_5%

DH_1.05V-1 DH_1.05V-2DH_1.8V-1

1 2

0_0603_5%
PR237

2K_0402_1%

ISE_1.05V

1 2

12

PR243
124K_0402_1%

PC83

0.1U_0402_16V7K

12

PR142

SI4810BDY-T1-E3_SO8

DL_1.05V

1 2

PR147

0_0402_5%

12

PC118

0.1U_0402_16V7K

@

SUSP#
17,25,29,31,32,34,40

LX_1.5V

PQ34

VSE_1.05VVSE_1.8V

876

5

DDD

D

SSS

G

123

4

PQ33
SI4800BDY-T1-E3_SO8

876

5

DDD

D

SSS

G

123

4

1.8UH_SIL104R-1R8PF_9.5A_30%

12

PR141

4.7_1206_5%

12

PC116

680P_0603_50V7K

12

PC114

4.7U_1206_25V6K

PL12

1 2

12

PC115

0_0402_5%

PR244

0_0402_5%@

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/10/17 2006/10/17

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

2

Date: Sheet

1.8VP/1.05VSP

Tuesday, March 06, 2007

0.1

of

44 48

1

5

4

3

2

1

+3VS

12

PJ12

12

JUMP_43X79

PC122

+5VS

12

1U_0603_6.3V6M

1@

PU9

6

VCNTL

5

VIN

9

VIN

8

EN

7

POK

3

VOUT

4

VOUT

2

FB

GND

APL5913-KAC-TRL_SO8

1

1@

PR148

2.15K_0402_1%

1@

12

12

PR150

12

PC123

0.01U_0402_25V7K

1@

1K_0402_1%

1@

12

+2.5VSP

1@

PC124

22U_1206_6.3V6M

D D

12

PC121
10U_0805_6.3V6M

1@

PR149
0_0402_5%

1@

0.1U_0402_16V7K @

1 2

PC125

12

SUSP#(17,25,28,29,33,35,38,43,44)

C C

+1.8V

12

PJ13

12

JUMP_43X79

PU10

1 6

3
4

12

PC129
22U_1206_6.3V6M

VIN VCNTL

VREF
VOUT

APL5331KAC-TRL_SO8

+0.9VSP

52

NCGND

7

NC

8

NC

9

TP

2005/10/17 2006/10/17

Compal Secret Data

B B

PR152

0_0402_5%

0.1U_0402_16V7K@

1 2

PC130

SUSP(38)

A A

12

PC126
10U_0805_6.3V6M

13

2

G

12

PQ36

RHU002N06_SOT323-3

1K_0402_1%

D

S

12

PR151

12

PR153
1K_0402_1%

12

PC128

0.1U_0402_16V7K

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

+3VALWP

12

PC127
1U_0603_6.3V6M

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

2

Date: Sheet

+2.5VSP/0.9VSP

Tuesday, March 06, 2007

0.1

of

45 48

1

5

4

3

2

1

+5VS

DH1_CPU-2

876

DDD

SSS

123

876

SI4856DY-T1-E3_SO8

DDD

SSS

PQ42

123

CPU_B+

3 5

5

D

G

4

DL1__CPU

1 2

PR186
3K_0603_1%@

470P_0603_50V8J

5

D

G

4

DL2__CPU

PC132

PQ37
SI7686DP-T1-E3_SO8

241

876

SI4856DY-T1-E3_SO8

DDD

PQ39

SSS

123

PR177 0_0402_5%

1 2

1 2

PC147

PQ40
SI7686DP-T1-E3_SO8

NA

3 5

241

876

DDD

SI4856DY-T1-E3_SO8

SSS

PQ41

123

12

12

PC133

10U_1206_25V6M

10U_1206_25V6M

0.36H_ETQP4LR36WFC_24A_20%

12

4.7_1206_5%
PR167

PR165

2.1K_0402_1%

12

PC141

680P_0603_50V7K

PC145 0.022U_0402_16V7K

1 2

PR183 100_0402_1%

PC146
4700P_0402_25V7K

1 2

12

PR197

4.7_1206_5%

12

PC156

680P_0603_50V7K

12

PC134

10U_1206_25V6M

PC135

0.1U_0603_25V7K

12

12

PC136

2200P_0402_50V7K

PL14

12

3.48K_0402_1%

1 2

PR171

1 2

10KB_0603_5%_ERTJ1VR103J

1 2

PH2

1 2

PC143 0.22U_0603_16V7K

1 2

CPU_VCC_SENSE

12

PC150

PC151

10U_1206_25V6M

10U_1206_25V6M

0.36H_ETQP4LR36WFC_24A_20%

12

PR198

2.1K_0402_1%
PR199

3.48K_0402_1%

1 2

HCB4532KF-800T90_1812

1 2

1

+

PC137

2

220U_25V_M

+CPU_CORE

NTC

12

@

VCCSENSE(5)

PR170 10_0402_5%

CPU_B+

12

12

PC152

PC153

10U_1206_25V6M

12

0.1U_0603_25V7K

12

PL15

NTC

1 2

10KB_0603_5%_ERTJ1VR103J

PL13

PC154

PH3

1 2

2200P_0402_50V7K

PR154

12

D D

PR157

13K_0402_5%

NTC

100K_0402_5%

PR159

1 2

PR160 0_0402_5%
PR162 0_0402_5%
PR163 0_0402_5%
PR164 0_0402_5%
PR166 0_0402_5%
PR168 0_0402_5%
PR169 0_0402_5%

C C

PR173 499_0402_1%
PR174 0_0402_5%
PR176 0_0402_5%

DPRSLPVR(7,20)
H_DPRSTP#(5,7,19)

+3VS

CPU_VID0(5)
CPU_VID1(5)
CPU_VID2(5)
CPU_VID3(5)
CPU_VID4(5)
CPU_VID5(5)
CPU_VID6(5)

H_PSI#(5)

1 2

1 2

1 2

1 2

12
12
12
12
12
12

1 2

VCC

PR172 71.5K_0402_1%

1 2

12

12

PC14247P_0402_50V8J

PC144 0.22U_0603_16V7K

PR180

0_0402_5%
PR187

PR189

10K_0402_1%

1 2

PR190

10K_0402_1%@

PR184

0_0402_5%

VGATE(7,20)

CLK_ENABLE#(20)

VR_ON(33)

1 2

@

1 2

1 2

0_0402_5%

1 2

B B

H_PROCHOT#(4,20)

POUT

PR181

2K_0402_1%@

1 2

PR193 0_0402_5%

PC155

0.1U_0402_16V7K

1 2

PR192

@

56_0402_5%

1 2

1 2

PR195 10K_0402_1%

+3VS

12

5VS1

PR155
10_0402_5%

PC139
1U_0603_6.3V6M

1 2

PU11

19

Vcc

6

THRM

31 30

D0 BST1

32

D1

33

D2

34

D3

35

D4

36

D5

37

D6

7

TIME

9

CCV

39

DPRSLPVR

40

DPRSTP

3

PSI

2

PWRGD

1

CLKEN

38

SHDN

5

VRHOT

4

POUT

MAX8770GTL+_TQFN40

VSSSENSE(5)

12

0_1206_5%

PC138

2.2U_0603_6.3V6K

VDD
TON

DH1

LX1
DL1

PGND1

GND

CSP1

CSN1

FB

CCIREF

DH2

BST2

LX2
DL2

PGND2

CSP2

CSN2

GNDS

41

4700P_0402_25V7K

VSSSENSE

12

12

PR156

200K_0402_1%

1 2

25
8

29
28
26

0_0603_5%

BST1_CPU BSTM1_CPU

PR161

1 2

DH1__CPU-1
LX1__CPU
DL1__CPU

27
18

CSP1__CPU

17

CSN1_CPU

16

FB_CPU

12

CCI_CPU

1011

DH2_CPU-1

21

BST2_CPU

20

LX2_CPU

22

DL2__CPU

24
23

CSP2_CPU

14

CSN2__CPU

15
13

TP

PC148

1 2

PR191

100_0402_1%

10_0402_5%@

PR196

1 2

12

PC131

0.01U_0402_25V7K

0.22U_0603_16V7K

PR179

0_0603_5%

1 2

BSTM2_CPU

12

PC149

0.22U_0603_16V7K

PC140

1 2

2.2_0603_5%
PR158

1 2

SI4856DY-T1-E3_SO8

PR178 3K_0603_1%@

PR182 4.22K_0402_1%

1 2

NTC

PR185

3K_0603_1%@

1 2

PR188

20K_0402_1%

2.2_0603_5%
PR194

1 2

PQ38

5

D

G

4

1 2

1 2

DH2_CPU-2

5

D

G

4

+CPU_CORE

PR175
0_0402_5%

12

B+

1 2

A A

PR200 0_0402_5%

1 2

PC157 0.22U_0603_16V7K

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2005/10/17 2006/10/17

3

Compal Secret Data

Deciphered Date

Compal Electronics, I n c.

Title

Size Document Number Rev

Custom

2

Date: Sheet

+CPU_CORE

1

0.1

of

46 48Tuesday, March 06, 2007

5

4

3

page Reason for change Modify list

2

1

EVT

P39,P42,P43,P44,P46

D D

DVT

P46

P39

P40

P41

C C

P42

P43

B B

Shortage issue : needs to change another source SM010018210 Replace

Change SB578400080 to SB000008L80Shortage issue : needs to change another source

1.Inrush decrease

2.Change to Standard part

1.LM358A replace of LM393

2.Add Diode to anti reverse voltage

3.Modify component size

1.Add BATT-OVP function

2.Overshoot solution during CC<->CV

3.Change torlance

4.Change to Standard part

5. Add PR227 to anti reverse voltage

6. 65W change to Standard part

7.Add EPA Function

1.Change 5V/3.3V in SKIP mode

2.Change to Standard part

3.For EPA function

Update 1.5VSP/1.25VSP to Standard part

1.Change PC1/PC4 from 0.01U to 1000P

2. PR1/PD1 no function,Change PD5 from RB751V to RL4148;Add PC6

1.PU5A replace of PU3A

2.Add PD18 close to PU5A

3.Change PC15/PC16 from 0603 to 0402

1.Change PR78 value from 150K to 105K
2-1.Add PR209 ,PC162 ,PR210 ,PQ44 ,PC161 ,PQ45 ;Del PQ46/PC30
2-2.Del PD8 ; Add PD17

3. Cange torlance from 0 ohm 5% to 10Kohm 1% at PR57

4. PD10: Change CH751H to 1SS355TE ; original PU5B
to PU5A; Del PC46;Change PQ20 from SI4810 to SI4800

5. PR227 : currently use 0ohm. (In the future use 2.2ohm)

6. Change PQ9/P10/PQ11 to FDS4435; Change PR69 to 39.2K

7.Add PD16/PR57/PR208/PR207/PC161

1.Add PR211 (@ PR94)
2-1.Change PC62/PC63 from SGA20151360 to SF22001M300
2-2. Change PC49/PC50 from 0603_25V7K to 0402_16V7K
2-3. Change PL5/PL6 from 4.7UH to 10UH

3.Change PR95 from 6.81K to 6.49K

1-1.Reduce capacitor value from 22u_1206_6.3V6M to 10u_0805_6.3VM at PC174
1-2.Change from dual PWM IC to single PWM IC for 1.5VSP (PU12),
Del PU7,PC69,PC71,PC72,,PC74,PC75,PC76,PC77,PC78,PC79,PC80,PC81,PC82,PC83,PC84,
PC85,PC86,PC87,PC88,PC90,PC91,
PC93,PC94,PD12,PD13,PL7,PL8,PL9,PQ27,PQ28,PQ29,PQ30,
PR100,PR102,PR103,PR104,PR105,PR106,PR107,PR108,PR109,PR110,PR111,PR112,PR113,PR114
,PR115,PR116,PR117,PR118,PR119,PR120,PR121,PR122,PR123
Add Part:PC82,PC163,PC164,PC165,PC166,PC167,PC168,PC169PC170,PC171,PC172,PC173,PC174,
PC175,PC176,PC177,PJ17,PJ18,PL16,PQ47,PQ48,PR212,PR213,PR214,PR215,PR216,PR217,PR218,
PR219,PR220,PR221PR222,PR223,PR224,PR225,PR226,PR228
1-3.APL5913(PU13) replace of APL5912

P44

P45

P46

A A

5

Update 1.05VSP/1.8VP to Standard part

Update 2.5VSP/0.9VSP to Standard part

Update +CPU_CORE to Standard part

4

1-1.Change PC107/PC110/PC100 size from 0603 to 0402
1-2.Change PD14/PD15 from RB751 to 1SS355TE
1-3.Change PC158 size from R9M to R15M;Change PC98 from NEC to Panasonic
1-4.Add PC113

1-1.Change PC121 capacitor from 22u_1206_6.3V6M to (@ 10U_0805_6.3VM)
1-2. APL5913 replace of APL5912 at PU9
1-3.Change PC126 capacitor from 22u_1206_6.3V6M to 10U_0805_6.3VM
1-4. Add PR149
1-5.UMA part : Del total 2.5VSP circuit->PU9/PC122/PC121/PR148/PR150/PC123/PC124/PR149

1-1.Change PC132/PC133/PC134/PC150/PC151/PC152 size from 10u_1206_25VAK to 10u_1206_25V6M
1-2.Change PQ38/PQ39/PQ41/PQ42 from 8113 to SI4856
1-3.Change PR158/PR194 from 0ohm to 2.2ohm
1-4.Change PC137 to 3000hrs

Title

<Title>

Size Document Number Rev

<Doc> <RevCode>

Custom

3

2

Date: Sheet

of

47 48Tuesday, March 06, 2007

1

B-TEST

5

4

3

2

1

Modify listReason for changepage

P22

D D

P26

P30

P35

P36

enter sleep mode

DFX ISSUE

F/P DFX

ADD RP49- RP52DFX ISSUE

ADD R672LED control by EC

ADD L42Reduce "bo" sound when

Del SIO debug port

ADD C1182 C1183 R669
R670

C-TEST

page Reason for change Modify list

P10

C C

P35

P38

fixed tv out ripple ADD L43 C1190

fixed COM PORT function

fixed 1st ac plug in
then led flash

re connect 14M & mirror
jp30 connection

SUSP# pull low 1ok (add
r678)

B B

A A

Title

<Title>

Size Document Number Rev

<Doc> <RevCode>

Custom

5

4

3

2

Date: Sheet

48 48Tuesday, March 06, 2007

1

of