A
ZZZ1
PCB
1 1
B
C
D
E
Compal Confidential
2 2
IFTxx Schematics Document
Intel Merom Processor with Crestline + DDRII + ICH8M
(With nVIDIA MXM/B)
3 3
2006-11-01
REV: 0.1
4 4
Security Classification
Issued Date
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
A
B
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2006/08/18 2007/8/18
Compal Secret Data
Deciphered Date
Title
Size Document Number Rev
B
D
Date: Sheet
Compal Electronics, Inc.
Cover Page
IFTXX M/B LA-3541P Schematic
152Wednesday, November 01, 2006
E
0.1
of
A
B
C
D
E
Compal Confidential
Model Name : IFTXX
Fan Control
page 4
File Name : LA-3541P
1 1
CRT & TV-out
page 19
LCD Conn.
page 18
Video Processor
page 18
LVDS
LVDS
SDVO
Intel Merom Processor
uPGA-478 Package
H_A#(3..35)
FSB
667/800MHz
Intel Crestline
page 4,5,6
H_D#(0..63)
uFCBGA-1299
PCI-Express
MXM II VGA/B
page 17
2 2
PCI-Express
page 7,8,9,10,11,12,13
DMI
X4 mode
Intel ICH8-M
3.3V 48MHz
PCI BUS
R5C833
page 28
3.3V 33 MHz
3 in 1
socket
page 29
IDSEL:AD20
(PIRQC#,PIRQD#,
GNT#2, REQ#2)
New Card
Socket
page 33
3 3
MINI Card x3
WLAN,
3G/TV-Tuner
Robson
page 32
LAN(GbE)
BCM5787M/5906
page 30
RJ45
page 31
CardBus
ENE CB1410
page 26
PCMCIA
Socket
page 26
IDSEL:AD22
(PIRQG#,PIRQH#,
GNT#0, REQ#0)
Card Reader
Conn.
page 28
BGA-676
page 20,21,22,23
LPC BUS
Thermal Sensor
ADM1032
page 4
Memory BUS(DDRII)
Dual Channel
1.8V DDRII 533/667
USB conn x2
TO M/B
page 33
USB conn x2
TO I/O/B
USB
3.3V 24.576MHz/48Mhz
3.3V ATA-100
S-ATA
port 0
IDE
S-ATA HDD
Conn.
page 24
page 37 page 33 page 42
Clock Generator
ICS9LPRS365
page 16
200pin DDRII-SO-DIMM X2
BANK 0, 1, 2, 3
Bluetooth
page 14,15
CMOS Camera
Conn
HD Audio
CDROM
Conn.
page 24
MDC 1.5
Conn
page 42
HDA Codec
Audio AMP1394
ALC268
page 38
page 39
Finger Print
Conn
page 42
RTC CKT.
page 21
Power On/Off CKT.
page 37
Switch/B Conn.
page 35
Touch Pad
page 36
ENE KB925
page 34
Int.KBD
page 35
SUPER I/O
LPC47N217
page 41
TPM
page 29
DC/DC Int erface CKT.
page 43
I/O Conn.
G-Sensor
page 25
BIOS
page 36
SCREW
page 40
FRONT LCD /B.
Power Circuit DC/DC
4 4
CHARGER
page 44,45,47,48
49,50,51
page 46
A
LID SW
page 37
Security Classification
Issued Date
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
B
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2006/08/18 2007/8/18
Compal Secret Data
Deciphered Date
Title
Size Document Number Rev
B
D
Date: Sheet
Compal Electronics, Inc.
Block Diagrams
IFTXX M/B LA-3541P Schematic
252Wednesday, November 01, 2006
E
0
of
A
B
C
D
E
1 1
2 2
Voltage Rails
VIN
B+
+CPU_CORE
+1.05VS
+1.5VS
+1.8V
+2.5VS
+3VALW
+3VS
+5VALW
+5VS
STATE
Full ON
S1(Power On Suspend)
S3 (Suspend to RAM)
S4 (Suspend to Disk)
S5 (Soft OFF)
SIGNAL
DescriptionPower Plane
Adapter power supply (19V)
AC or battery power rail for power circuit.
Core voltage for CPU
0.9V switched power rail for DDR terminator+0.9VS
1.05V switched power rail
1.5V switched power rail
1.8V power rail for DDR
1.8V switched power rail+1.8VS
2.5V switched power rail
3.3V always on power rail
3.3V switched power rail
5V always on power rail
5V switched power rail
RTC power+RTCVCC
SLP_S3#SLP_S1#
SLP_S4#
SLP_S5#
HIGHHIGHHIGHHIGH
HIGH HIGH HIGH
LOW
HIGH
LOW
LOW
LOW LOW LOW
HIGH
HIGH
LOWLOWLOW
LOW
S3S1
N/A N/A N/A
OFFON
OFFON
ON1.25V switched power rail+1.25VS
ON
ON
OFF
ON
ON
OFF
ON
ON
OFF
ON
ON
OFF
ON OFF
ONONON
+VALW
+V +VS Clock
ON
ON
ON
ON
ON
ON
ON
OFF
ON
OFF
S5
N/AN/AN/A
OFF
OFF
OFFOFFON
OFFOFF
OFFOFFON
OFF
OFF
OFF
ON*ON
OFF
ON*
ON*ONVSB always on power rail+VSB
ON
ON
OFF
OFF
OFF
ONON
LOW
OFF
OFF
OFF
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.
External PCI Devices
DEVICE
1394+Cardreader G,H
EC SM Bus1 address
Device
Smart Battery
EEPROM(24C16/02)
IDSEL #
AD20
AD22
Address
1010 000X b
REQ/GNT #
2
PIRQ
C,DCARD BUS CB1410
0
EC SM Bus2 address
Device
ADI ADM1032
NVIDIA NB8X
Address
1001 100X b0001 011X b
3 3
BOARD ID Table
ID1
0(R744)
1(R741)
ID0
0(R745)
1(R742)0(R744)
0(R745)
TEST
A-TEST
B-TEST
C-TEST
ICH8M SM Bus address
Device
Clock Generator
(ICS9LPRS325AKLFT_MLF72)
DDR DIMM0
DDR DIMM1
Address
1101 001Xb
1010 000Xb
1010 010Xb
PANEL ID Table
R
Ra (R743)
4 4
A
Size
15W
14WRb (R740)
Security Classification
Issued Date
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
B
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2006/08/18 2007/8/18
Compal Secret Data
Deciphered Date
Title
Size Document Number Rev
B
D
Date: Sheet
Compal Electronics, Inc.
Notes List
IFTXX M/B LA-3541P Schematic
352Wednesday, November 01, 2006
E
0
of
5
4
3
2
1
H_A#[3..35]<7>
H_REQ#[0..4]<7>
H_RS#[0..2]<7>
D D
C C
B B
A A
H_A#[3..35]
H_REQ#[0..4]
H_RS#[0..2]
H_ADSTB#0<7>
H_ADSTB#1<7>
H_STPCLK#<21>
H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35
H_A20M#<21>
H_FERR#<21>
H_IGNNE#<21>
H_INTR<21>
H_NMI<21>
H_SMI#<21>
JP36A
J4
A[3]#
L5
A[4]#
L4
A[5]#
K5
A[6]#
M3
A[7]#
N2
A[8]#
J1
A[9]#
N3
A[10]#
P5
A[11]#
P2
A[12]#
L2
A[13]#
P4
A[14]#
P1
A[15]#
R1
A[16]#
M1
ADSTB[0]#
K3
REQ[0]#
H2
REQ[1]#
K2
REQ[2]#
J3
REQ[3]#
L1
REQ[4]#
Y2
A[17]#
U5
A[18]#
R3
A[19]#
W6
A[20]#
U4
A[21]#
Y5
A[22]#
U1
A[23]#
R4
A[24]#
T5
A[25]#
T3
A[26]#
W2
A[27]#
W5
A[28]#
Y4
A[29]#
U2
A[30]#
V4
A[31]#
W3
A[32]#
AA4
A[33]#
AB2
A[34]#
AA3
A[35]#
V1
ADSTB[1]#
A6
A20M#
A5
FERR#
C4
IGNNE#
D5
STPCLK#
C6
LINT0
B4
LINT1
A3
SMI#
M4
RSVD[01]
N5
RSVD[02]
T2
RSVD[03]
V3
RSVD[04]
B2
RSVD[05]
C3
RSVD[06]
D2
RSVD[07]
D22
RSVD[08]
D3
RSVD[09]
F6
RSVD[10]
Merom Ball-out Rev 1a
ADDR GROUP 0 ADDR GROUP 1
ICH
ADS#
BNR#
BPRI#
DEFER#
DRDY#
DBSY#
BR0#
IERR#
INIT#
LOCK#
CONTROL
RESET#
RS[0]#
RS[1]#
RS[2]#
TRDY#
HIT#
HITM#
BPM[0]#
BPM[1]#
BPM[2]#
BPM[3]#
PRDY#
PREQ#
TCK
TDO
TMS
TRST#
XDP/ITP SIGNALS
DBR#
THERMAL
PROCHOT#
THERMDA
THERMDC
THERMTRIP#
H CLK
BCLK[0]
BCLK[1]
RESERVED
conn@
H1
E2
G5
H5
F21
E1
F1
H_IERR#
D20
B3
H4
H_RESET#
C1
H_RS#0
F3
H_RS#1
F4
H_RS#2
G3
G2
G6
E4
AD4
AD3
AD1
AC4
AC2
H_PREQ#
AC1
ITP_TCK
AC5
ITP_TDI
AA6
TDI
AB3
ITP_TMS
AB5
ITP_TRST#
AB6
ITP_DBRESET#
C20
H_PROCHOT#
D21
THERMDA
A24
THERMDC
B25
C7
A22
A21
H_ADS# <7>
H_BNR# <7>
H_BPRI# <7>
H_DEFER# <7>
H_DRDY# <7>
H_DBSY# <7>
H_BR0# <7>
H_INIT# <21>
H_LOCK# <7>
H_RESET# <7>
H_TRDY# <7>
H_HIT# <7>
H_HITM# <7>
ITP_DBRESET# <22>
H_PROCHOT# <51>
H_THERMTRIP# <8,21>
CLK_CPU_BCLK <16>
CLK_CPU_BCLK# <16>
Checklist recommend 39 Ohm
CRB pull 75 Ohm
ADM1032
C688
2200P_0402_50V7K
Connect SB SYS_RESET# or just left NC
FAN1 Conn
H_THERMDA, H_THERMDC routing together,
Trace width / Spacing = 10 / 10 mil
+5VS
+VCC_FAN1
EN_FAN1<34>
EN_FAN1
FAN_SPEED1<34>
Place close to CPU within 500mil
1
2
THERMDA
THERMDC
U5
1
VEN
2
VIN
3
VO
4
VSET
G993P1UF_SOP8
H_PREQ#
H_IERR#
ITP_TMS
ITP_TDI
H_PROCHOT#
ITP_TCK
ITP_TRST#
+3VS
C28 10U_1206_16V4Z
1 2
+3VS
12
1
2
R559 56_0402_5%
1 2
R560 56_0402_5%
1 2
R562 56_0402_5%
1 2
R563 150_0402_1%
1 2
R565 56_0402_5%
1 2
R568 27.4_0402_1%
1 2
R569 680_0402_5%
1 2
C687
0.1U_0402_16V4Z
1 2
U38
1
VDD
2
D+
3
DTHERM#4GND
ADM1032ARMZ_MSOP8
F75383M_MSOP8
8
GND
7
GND
6
GND
5
GND
R44
10K_0402_5%
C31
1000P_0402_50V7K
40mil
+VCC_FAN1
SCLK
SDATA
ALERT#
8
7
6
5
+5VS
12
D4
1SS355_SOD323
@
1 2
10U_1206_16V4Z
1000P_0402_50V7K
D5
1N4148_SOT23@
C29
1 2
C30
1 2
ACES_85205-03001
+1.05VS
EC_SMB_CK2 <17,34>
EC_SMB_DA2 <17,34>
JP6
1
1
2
2
3
3
4
GND
5
GND
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SE CRET INFOR MATI ON. THIS SHEET MAY NOT BE TRANSF ERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2006/08/18 2007/8/18
3
Compal Secret Data
Deciphered Date
Title
Size Document Number Rev
B
2
Date: Sheet
Compal Electronics, Inc.
Merom (1/3)
IFTXX M/B LA-3541P Schematic
452Wednesday, November 01, 2006
1
0
of
5
4
3
2
1
H_D#[0..63]
H_D#0
PAD
PAD
PAD
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
GTL_REF
TEST1
TEST2
TEST3
TEST4
TEST5
TEST6
D D
H_DSTBN#0<7> H_DSTBN#2 <7>
H_DSTBP#0<7> H_DSTBP#2 <7>
H_DINV#0<7>
Close to CPU pin AD26
within 500mils.
C C
Width=20 mil
B B
layout note: Route TEST3 & TEST5 traces on ground referenced layer to the TPs
R549
1K_0402_1%
R556
2K_0402_1%
+1.05VS
1 2
1 2
H_DSTBN#1<7> H_DSTBN#3 <7>
H_DSTBP#1<7> H_DSTBP#3 <7>
H_DINV#1<7>
R551 1K_0402_5%@
R553 1K_0402_5%@
C684 0.1U_0402_16V4Z@
1 2
12
12
T19
T20
T21
CPU_BSEL0<16>
CPU_BSEL1<16>
CPU_BSEL2<16>
CPU_BSEL CPU_BSEL2 CPU_BSEL1
JP36B
E22
D[0]#
F24
D[1]#
E26
D[2]#
G22
D[3]#
F23
D[4]#
G25
D[5]#
E25
D[6]#
E23
D[7]#
K24
D[8]#
G24
D[9]#
J24
D[10]#
J23
D[11]#
H22
D[12]#
F26
D[13]#
K22
D[14]#
H23
D[15]#
J26
DSTBN[0]#
H26
DSTBP[0]#
H25
DINV[0]#
N22
D[16]#
K25
D[17]#
P26
D[18]#
R23
D[19]#
L23
D[20]#
M24
D[21]#
L22
D[22]#
M23
D[23]#
P25
D[24]#
P23
D[25]#
P22
D[26]#
T24
D[27]#
R24
D[28]#
L25
D[29]#
T25
D[30]#
N25
D[31]#
L26
DSTBN[1]#
M26
DSTBP[1]#
N24
DINV[1]#
AD26
GTLREF
C23
TEST1
D25
TEST2
C24
TEST3
AF26
TEST4
AF1
TEST5
A26
TEST6
B22
BSEL[0]
B23
BSEL[1]
C21
BSEL[2]
Merom Ball-out Rev 1a
conn@
CPU_BSEL0
DATA GRP 0
DATA GRP 1
MISC
D[32]#
D[33]#
D[34]#
D[35]#
D[36]#
D[37]#
D[38]#
D[39]#
D[40]#
D[41]#
D[42]#
D[43]#
D[44]#
D[45]#
DATA GRP 2DATA GRP 3
D[46]#
D[47]#
DSTBN[2]#
DSTBP[2]#
DINV[2]#
D[48]#
D[49]#
D[50]#
D[51]#
D[52]#
D[53]#
D[54]#
D[55]#
D[56]#
D[57]#
D[58]#
D[59]#
D[60]#
D[61]#
D[62]#
D[63]#
DSTBN[3]#
DSTBP[3]#
DINV[3]#
COMP[0]
COMP[1]
COMP[2]
COMP[3]
DPRSTP#
DPSLP#
DPWR#
PWRGOOD
SLP#
PSI#
Y22
AB24
V24
V26
V23
T22
U25
U23
Y25
W22
Y23
W24
W25
AA23
AA24
AB25
Y26
AA26
U22
AE24
AD24
AA21
AB22
AB21
AC26
AD20
AE22
AF23
AC25
AE21
AD21
AC22
AD23
AF22
AC23
AE25
AF24
AC20
R26
U26
AA1
Y1
E5
B5
D24
D6
D7
AE6
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
COMP0
COMP1
COMP2
COMP3
H_PWRGOOD
H_CPUSLP#
H_DINV#2 <7>
R550 27.4_0402_1%
R552 54.9_0402_1%
R554 27.4_0402_1%
R555 54.9_0402_1%
H_DINV#3 <7>
1 2
1 2
1 2
1 2
H_DPRSTP# <8,21,51>
H_DPSLP# <21>
H_DPWR# <7>
H_PWRGOOD <21>
H_CPUSLP# <7>
H_PSI# <51>
H_D#[0..63] <7>
Resistor placed within
0.5" of CPU pin.Trace
should be at least 25
mils away from any other
toggling signal.
COMP[0,2] trace width is
18 mils. COMP[1,3] trace
width is 4 mils.
+CPU_CORE
JP36C
A7
VCC[001]
A9
VCC[002]
A10
VCC[003]
A12
VCC[004]
A13
VCC[005]
A15
VCC[006]
A17
VCC[007]
A18
VCC[008]
A20
VCC[009]
B7
VCC[010]
B9
VCC[011]
B10
VCC[012]
B12
VCC[013]
B14
VCC[014]
B15
VCC[015]
B17
VCC[016]
B18
VCC[017]
B20
VCC[018]
C9
VCC[019]
C10
VCC[020]
C12
VCC[021]
C13
VCC[022]
C15
VCC[023]
C17
VCC[024]
C18
VCC[025]
D9
VCC[026]
D10
VCC[027]
D12
VCC[028]
D14
VCC[029]
D15
VCC[030]
D17
VCC[031]
D18
VCC[032]
E7
VCC[033]
E9
VCC[034]
E10
VCC[035]
E12
VCC[036]
E13
VCC[037]
E15
VCC[038]
E17
VCC[039]
E18
VCC[040]
E20
VCC[041]
F7
VCC[042]
F9
VCC[043]
F10
VCC[044]
F12
VCC[045]
F14
VCC[046]
F15
VCC[047]
F17
VCC[048]
F18
VCC[049]
F20
VCC[050]
AA7
VCC[051]
AA9
VCC[052]
AA10
VCC[053]
AA12
VCC[054]
AA13
VCC[055]
AA15
VCC[056]
AA17
VCC[057]
AA18
VCC[058]
AA20
VCC[059]
AB9
VCC[060]
AC10
VCC[061]
AB10
VCC[062]
AB12
VCC[063]
AB14
VCC[064]
AB15
VCC[065]
AB17
VCC[066]
AB18
VCC[067]
Merom Ball-out Rev 1a
conn@
VCC[068]
VCC[069]
VCC[070]
VCC[071]
VCC[072]
VCC[073]
VCC[074]
VCC[075]
VCC[076]
VCC[077]
VCC[078]
VCC[079]
VCC[080]
VCC[081]
VCC[082]
VCC[083]
VCC[084]
VCC[085]
VCC[086]
VCC[087]
VCC[088]
VCC[089]
VCC[090]
VCC[091]
VCC[092]
VCC[093]
VCC[094]
VCC[095]
VCC[096]
VCC[097]
VCC[098]
VCC[099]
VCC[100]
VCCP[01]
VCCP[02]
VCCP[03]
VCCP[04]
VCCP[05]
VCCP[06]
VCCP[07]
VCCP[08]
VCCP[09]
VCCP[10]
VCCP[11]
VCCP[12]
VCCP[13]
VCCP[14]
VCCP[15]
VCCP[16]
VCCA[01]
VCCA[02]
VID[0]
VID[1]
VID[2]
VID[3]
VID[4]
VID[5]
VID[6]
VCCSENSE
VSSSENSE
AB20
AB7
AC7
AC9
AC12
AC13
AC15
AC17
AC18
AD7
AD9
AD10
AD12
AD14
AD15
AD17
AD18
AE9
AE10
AE12
AE13
AE15
AE17
AE18
AE20
AF9
AF10
AF12
AF14
AF15
AF17
AF18
AF20
G21
V6
J6
K6
M6
J21
K21
M21
N21
N6
R21
R6
T21
T6
V21
W21
B26
C26
AD6
AF5
AE5
AF4
AE3
AF3
AE2
AF7
AE7
.
+CPU_CORE
VCCSENSE
VSSSENSE
Place this cap more close to
B26/C26 rather than 10UF
1
CPU_VID0 <51>
CPU_VID1 <51>
CPU_VID2 <51>
CPU_VID3 <51>
CPU_VID4 <51>
CPU_VID5 <51>
CPU_VID6 <51>
1 2
R557 100_0402_1%
R558 100_0402_1%
1 2
C686
2
0.01U_0402_16V7K
1
+
C677
330U_D2E_2.5VM_R9
2
20mils
VCCSENSE <51>
VSSSENSE <51>
+1.05VS
1
C685
10U_0805_10V4Z
2
+CPU_CORE
+1.5VS
166
200
01
0
1
1
0
Length match within 25 mils.
The trace width/space/other is
20/7/25.
Close to CPU pin
A A
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SE CRET INFOR MATI ON. THIS SHEET MAY NOT BE TRANSF ERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2006/08/18 2007/8/18
3
Compal Secret Data
Deciphered Date
2
within 500mils.
Title
Size Document Number Rev
B
IFTXX M/B LA-3541P Schematic
Date: Sheet
Compal Electronics, Inc.
Merom (2/3)
552Wednesday, November 01, 2006
1
0
of
5
4
3
2
1
+CPU_CORE
JP36D
A4
VSS[001]
A8
VSS[002]
A11
VSS[003]
A14
VSS[004]
A16
VSS[005]
A19
VSS[006]
D D
C C
B B
A23
VSS[007]
AF2
VSS[008]
B6
VSS[009]
B8
VSS[010]
B11
VSS[011]
B13
VSS[012]
B16
VSS[013]
B19
VSS[014]
B21
VSS[015]
B24
VSS[016]
C5
VSS[017]
C8
VSS[018]
C11
VSS[019]
C14
VSS[020]
C16
VSS[021]
C19
VSS[022]
C2
VSS[023]
C22
VSS[024]
C25
VSS[025]
D1
VSS[026]
D4
VSS[027]
D8
VSS[028]
D11
VSS[029]
D13
VSS[030]
D16
VSS[031]
D19
VSS[032]
D23
VSS[033]
D26
VSS[034]
E3
VSS[035]
E6
VSS[036]
E8
VSS[037]
E11
VSS[038]
E14
VSS[039]
E16
VSS[040]
E19
VSS[041]
E21
VSS[042]
E24
VSS[043]
F5
VSS[044]
F8
VSS[045]
F11
VSS[046]
F13
VSS[047]
F16
VSS[048]
F19
VSS[049]
F2
VSS[050]
F22
VSS[051]
F25
VSS[052]
G4
VSS[053]
G1
VSS[054]
G23
VSS[055]
G26
VSS[056]
H3
VSS[057]
H6
VSS[058]
H21
VSS[059]
H24
VSS[060]
J2
VSS[061]
J5
VSS[062]
J22
VSS[063]
J25
VSS[064]
K1
VSS[065]
K4
VSS[066]
K23
VSS[067]
K26
VSS[068]
L3
VSS[069]
L6
VSS[070]
L21
VSS[071]
L24
VSS[072]
M2
VSS[073]
M5
VSS[074]
M22
VSS[075]
M25
VSS[076]
N1
VSS[077]
N4
VSS[078]
N23
VSS[079]
N26
VSS[080]
VSS[081]P3VSS[162]
Merom Ball-out Rev 1a
conn@
VSS[082]
VSS[083]
VSS[084]
VSS[085]
VSS[086]
VSS[087]
VSS[088]
VSS[089]
VSS[090]
VSS[091]
VSS[092]
VSS[093]
VSS[094]
VSS[095]
VSS[096]
VSS[097]
VSS[098]
VSS[099]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
VSS[159]
VSS[160]
VSS[161]
VSS[163]
P6
P21
P24
R2
R5
R22
R25
T1
T4
T23
T26
U3
U6
U21
U24
V2
V5
V22
V25
W1
W4
W23
W26
Y3
Y6
Y21
Y24
AA2
AA5
AA8
AA11
AA14
AA16
AA19
AA22
AA25
AB1
AB4
AB8
AB11
AB13
AB16
AB19
AB23
AB26
AC3
AC6
AC8
AC11
AC14
AC16
AC19
AC21
AC24
AD2
AD5
AD8
AD11
AD13
AD16
AD19
AD22
AD25
AE1
AE4
AE8
AE11
AE14
AE16
AE19
AE23
AE26
A2
AF6
AF8
AF11
AF13
AF16
AF19
AF21
A25
AF25
.
1
+
C643
330U_D2E_2.5VM_R9
2
+CPU_CORE
1
C649
2
10U_0805_6.3V6M
+CPU_CORE
1
C657
2
10U_0805_6.3V6M
+CPU_CORE
1
C665
2
10U_0805_6.3V6M
+CPU_CORE
1
C671
2
10U_0805_6.3V6M
+CPU-CORE
Decoupling
SPCAP,Polymer
MLCC 0805 X5R
3 x 330uF(9mOhm/3) 3 x 330uF(9mOhm/3)
1
+
C644
2
330U_D2E_2.5VM_R9
South Side Seco ndary North Side Sec ondary
1
C650
10U_0805_6.3V6M
2
10U_0805_6.3V6M
1
+
C645
@
330U_D2E_2.5VM_R9
2
1
C651
10U_0805_6.3V6M
2
(Place these capacitors on South side,Secondary Layer)
10U_0805_6.3V6M
1
C658
2
1
C659
2
10U_0805_6.3V6M
10U_0805_6.3V6M
(Place these capacitors on North side,Secondary Layer)
10U_0805_6.3V6M
1
C666
2
1
C667
2
10U_0805_6.3V6M
10U_0805_6.3V6M
(Place these capacitors on South side,Primary Layer)
1
C673
2
10U_0805_6.3V6M
10U_0805_6.3V6M
10U_0805_6.3V6M
1
C672
2
(Place these capacitors on North side,Primary Layer)
C,uF ESR, mohm ESL,nH
6X330uF 9m ohm/6 1.8nH/6
32X22uF 3m ohm/32 0.6nH/32
32X10uF 3m ohm/32 0.6nH/32
+1.05VS
1
2
0.1U_0402_16V4Z
1
C678
0.1U_0402_16V4Z
2
C679
0.1U_0402_16V4Z
1
C680
2
1
2
1
2
1
2
1
2
0.1U_0402_16V4Z
+CPU_CORE
1
+
C646
330U_D2E_2.5VM_R9
2
330U_D2E_2.5VM_R9
C652
C660
C668
C674
1
C653
2
10U_0805_6.3V6M
1
C661
2
10U_0805_6.3V6M
1
C669
2
10U_0805_6.3V6M
1
C675
2
10U_0805_6.3V6M
1
C681
2
0.1U_0402_16V4Z
1
C647
2
10U_0805_6.3V6M
10U_0805_6.3V6M
10U_0805_6.3V6M
10U_0805_6.3V6M
1
C682
0.1U_0402_16V4Z
2
+
330U_D2E_2.5VM_R9
1
C654
2
10U_0805_6.3V6M
1
C662
2
10U_0805_6.3V6M
1
C670
2
10U_0805_6.3V6M
1
C676
2
10U_0805_6.3V6M
1
C683
2
C648
@
1
+
2
1
2
1
2
1
2
1
2
C655
C663
C700
C702
10U_0805_6.3V6M
10U_0805_6.3V6M
10U_0805_6.3V6M
10U_0805_6.3V6M
1
CRB no stuff. Reserved!
C656
2
1
C664
2
1
C701
2
1
C703
2
9/25 10U checked. OK for use!
A A
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SE CRET INFOR MATI ON. THIS SHEET MAY NOT BE TRANSF ERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2006/08/18 2007/8/18
3
Compal Secret Data
Deciphered Date
Title
Size Document Number Rev
B
2
Date: Sheet
Compal Electronics, Inc.
Merom (3/3)
IFTXX M/B LA-3541P Schematic
652Wednesday, November 01, 2006
1
0
of
5
4
3
2
1
H_A#[3..35] <4>
H_ADS# <4>
H_ADSTB#0 <4>
H_ADSTB#1 <4>
H_BNR# <4>
H_BPRI# <4>
H_BR0# <4>
H_DEFER# <4>
H_DBSY# <4>
CLK_MCH_BCLK <16>
CLK_MCH_BCLK# <16>
H_DPWR# <5>
H_DRDY# <4>
H_HIT# <4>
H_HITM# <4>
H_LOCK# <4>
H_TRDY# <4>
H_DINV#0 <5>
H_DINV#1 <5>
H_DINV#2 <5>
H_DINV#3 <5>
H_DSTBN#0 <5>
H_DSTBN#1 <5>
H_DSTBN#2 <5>
H_DSTBN#3 <5>
H_DSTBP#0 <5>
H_DSTBP#1 <5>
H_DSTBP#2 <5>
H_DSTBP#3 <5>
H_REQ#[0..4] <4>
H_RS#[0..2] <4>
U37
965GM
GM@
M10
N12
P13
W10
AD12
AE3
AD9
AC9
AC7
AC14
AD11
AC11
AB2
AD7
AB1
AC6
AE2
AC5
AG3
AJ9
AH8
AJ14
AE9
AE11
AH12
AJ5
AH5
AJ6
AE7
AJ7
AJ2
AE5
AJ3
AH2
AH13
E2
G2
G7
M6
H7
H3
G4
F3
N8
H2
N9
H5
K9
M2
Y8
V4
M3
J1
N5
N3
W6
W9
N2
Y7
Y9
P4
W3
N1
Y3
B3
C2
W1
W2
B6
E5
B9
A9
U37A
H_D#_0
H_D#_1
H_D#_2
H_D#_3
H_D#_4
H_D#_5
H_D#_6
H_D#_7
H_D#_8
H_D#_9
H_D#_10
H_D#_11
H_D#_12
H_D#_13
H_D#_14
H_D#_15
H_D#_16
H_D#_17
H_D#_18
H_D#_19
H_D#_20
H_D#_21
H_D#_22
H_D#_23
H_D#_24
H_D#_25
H_D#_26
H_D#_27
H_D#_28
H_D#_29
H_D#_30
H_D#_31
H_D#_32
H_D#_33
H_D#_34
H_D#_35
H_D#_36
H_D#_37
H_D#_38
H_D#_39
H_D#_40
H_D#_41
H_D#_42
H_D#_43
H_D#_44
H_D#_45
H_D#_46
H_D#_47
H_D#_48
H_D#_49
H_D#_50
H_D#_51
H_D#_52
H_D#_53
H_D#_54
H_D#_55
H_D#_56
H_D#_57
H_D#_58
H_D#_59
H_D#_60
H_D#_61
H_D#_62
H_D#_63
H_SWING
H_RCOMP
H_SCOMP
H_SCOMP#
H_CPURST#
H_CPUSLP#
H_AVREF
H_DVREF
CRESTLINE_1p0
PM@
HOST
H_A#_3
H_A#_4
H_A#_5
H_A#_6
H_A#_7
H_A#_8
H_A#_9
H_A#_10
H_A#_11
H_A#_12
H_A#_13
H_A#_14
H_A#_15
H_A#_16
H_A#_17
H_A#_18
H_A#_19
H_A#_20
H_A#_21
H_A#_22
H_A#_23
H_A#_24
H_A#_25
H_A#_26
H_A#_27
H_A#_28
H_A#_29
H_A#_30
H_A#_31
H_A#_32
H_A#_33
H_A#_34
H_A#_35
H_ADS#
H_ADSTB#_0
H_ADSTB#_1
H_BNR#
H_BPRI#
H_BREQ#
H_DEFER#
H_DBSY#
HPLL_CLK
HPLL_CLK#
H_DPWR#
H_DRDY#
H_HIT#
H_HITM#
H_LOCK#
H_TRDY#
H_DINV#_0
H_DINV#_1
H_DINV#_2
H_DINV#_3
H_DSTBN#_0
H_DSTBN#_1
H_DSTBN#_2
H_DSTBN#_3
H_DSTBP#_0
H_DSTBP#_1
H_DSTBP#_2
H_DSTBP#_3
H_REQ#_0
H_REQ#_1
H_REQ#_2
H_REQ#_3
H_REQ#_4
H_RS#_0
H_RS#_1
H_RS#_2
J13
B11
C11
M11
C15
F16
L13
G17
C14
K16
B13
L16
J17
B14
K19
P15
R17
B16
H20
L19
D17
M17
N16
J19
B18
E19
B17
B15
E17
C18
A19
B19
N19
G12
H17
G20
C8
E8
F12
D6
C10
AM5
AM7
H8
K7
E4
C6
G10
B7
K5
L2
AD13
AE13
M7
K3
AD2
AH11
L7
K2
AC2
AJ10
M14
E13
A11
H13
B12
E12
D7
D8
H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35
H_ADS#
H_ADSTB#0
H_ADSTB#1
H_BNR#
H_BPRI#
H_BR0#
H_DEFER#
H_DBSY#
CLK_MCH_BCLK
CLK_MCH_BCLK#
H_DPWR#
H_DRDY#
H_HIT#
H_HITM#
H_LOCK#
H_TRDY#
H_DINV#0
H_DINV#1
H_DINV#2
H_DINV#3
H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3
H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
H_RS#0
H_RS#1
H_RS#2
H_D#[0..63]<5>
D D
+1.05VS
12
R539
221_0402_1%
H_SWNG
C C
R540
100_0402_1%
1 2
1
C641
0.1U_0402_16V4Z
2
Near B3 pin
H_RCOMP
12
R541
24.9_0402_1%
layout note:
Route H_SCOMP and H_SCOMP# with
trace width, spacing and
impedance (55 ohm) same as FSB
data traces
B B
+1.05VS
R544
1K_0402_1%
1 2
12
R546
2K_0402_1%
54.9_0402_1%
R542
1
2
+1.05VS
1 2
H_RESET#<4>
H_CPUSLP#<5>
C642
0.1U_0402_16V4Z
R543
54.9_0402_1%
1 2
H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
H_SWNG
H_RCOMP
H_SCOMP
H_SCOMP#
H_RESET#
H_CPUSLP#
H_VREF
within 100mil to Ball A9,B9
A A
Layout Note:
H_RCOMP / H_VREF / H_SWNG
trace width and spacing is 10/20
5
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SE CRET INFOR MATI ON. THIS SHEET MAY NOT BE TRANSF ERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2006/08/18 2007/8/18
3
Compal Secret Data
Deciphered Date
Title
Size Document Number Rev
B
2
Date: Sheet
Compal Electronics, Inc.
Crestline (1/7)-GTL
IFTXX M/B LA-3541P Schematic
752Wednesday, November 01, 2006
1
0
of
5
D D
DDRA_SMA14<14>
DDRB_SMA14<14,15>
DDRA_SMA14
DDRB_SMA14
9/20 Modify NB symbol for Pin BJ29/BE24/C48/D47
C C
MCH_CLKSEL0<16>
MCH_CLKSEL1<16>
MCH_CLKSEL2<16>
B B
PM_BMBUSY#<22>
H_DPRSTP#<5,21,51>
PM_EXTTS#0<14>
PM_EXTTS#1<15>
PLT_RST#<20,22,29,30,41>
H_THERMTRIP#<4,21>
PM_DPRSLPVR<22,51>
PM_EXTTS#0
PM_EXTTS#1
R525 100_0402_5%
R527 0_0402_5%
1 2
MCH_CLKSEL0
MCH_CLKSEL1
MCH_CLKSEL2
MCH_CFG_5
MCH_CFG_9
MCH_CFG_12
MCH_CFG_13
MCH_CFG_16
MCH_CFG_19
MCH_CFG_20
GMCH_PWROK
MCH_RSTIN#
If THERMTRIP no used, left NC
Use VGATE for GMCH_PWROK
VGATE<22,51>
ICH_POK<22,34>
A A
VGATE
ICH_POK
1 2
R533 0_0402_5%@
1 2
R535 0_0402_5%
GMCH_PWROK
AR12
AR13
AM12
AN13
AR37
AM36
AL36
AM37
BJ20
BK22
BF19
BH20
BK18
BJ18
BF23
BG23
BC23
BD24
BJ29
BE24
BH39
AW20
BK20
AW49
AV20
BJ51
BK51
BK50
BL50
BL49
G23
M20
M24
G41
G36
BK1
BK2
4
P36
P37
R35
N35
J12
D20
H10
B51
C48
D47
B44
C44
A35
B37
B36
B34
C34
P27
N27
N24
C21
C23
F23
N23
J20
C20
R24
L23
J23
E23
E20
K23
L32
N33
L35
L39
L36
J36
N20
BL3
BL2
BJ1
E1
A5
C51
B50
A50
A49
U37B
RSVD1
RSVD2
RSVD3
RSVD4
RSVD5
RSVD6
RSVD7
RSVD8
RSVD9
RSVD10
RSVD11
RSVD12
RSVD13
RSVD14
RSVD20
RSVD21
RSVD22
RSVD23
RSVD24
RSVD25
RSVD26
RSVD27
RSVD28
RSVD29
RSVD30
RSVD31
SA_MA_14
SB_MA_14
RSVD34
RSVD35
RSVD36
LVDSA_DATA#_3
LVDSA_DATA_3
RSVD39
RSVD40
RSVD41
RSVD42
RSVD43
RSVD44
RSVD45
CFG_0
CFG_1
CFG_2
CFG_3
CFG_4
CFG_5
CFG_6
CFG_7
CFG_8
CFG_9
CFG_10
CFG_11
CFG_12
CFG_13
CFG_14
CFG_15
CFG_16
CFG_17
CFG_18
CFG_19
CFG_20
PM_BM_BUSY#
PM_DPRSTP#
PM_EXT_TS#_0
PM_EXT_TS#_1
PWROK
RSTIN#
THERMTRIP#
DPRSLPVR
NC_1
NC_2
NC_3
NC_4
NC_5
NC_6
NC_7
NC_8
NC_9
NC_10
NC_11
NC_12
NC_13
NC_14
NC_15
NC_16
CRESTLINE_1p0
PM@
DDR MUXINGCLK
DPLL_REF_SSCLK#
CFGRSVD
DMI
PM
GRAPHICS VID
ME
NC
SDVO_CTRL_DATA
MISC
SM_CK_0
SM_CK_1
SM_CK_3
SM_CK_4
SM_CK#_0
SM_CK#_1
SM_CK#_3
SM_CK#_4
SM_CKE_0
SM_CKE_1
SM_CKE_3
SM_CKE_4
SM_CS#_0
SM_CS#_1
SM_CS#_2
SM_CS#_3
SM_ODT_0
SM_ODT_1
SM_ODT_2
SM_ODT_3
SM_RCOMP
SM_RCOMP#
SM_RCOMP_VOH
SM_RCOMP_VOL
SM_VREF_0
SM_VREF_1
DPLL_REF_CLK
DPLL_REF_CLK#
DPLL_REF_SSCLK
PEG_CLK
PEG_CLK#
DMI_RXN_0
DMI_RXN_1
DMI_RXN_2
DMI_RXN_3
DMI_RXP_0
DMI_RXP_1
DMI_RXP_2
DMI_RXP_3
DMI_TXN_0
DMI_TXN_1
DMI_TXN_2
DMI_TXN_3
DMI_TXP_0
DMI_TXP_1
DMI_TXP_2
DMI_TXP_3
GFX_VID_0
GFX_VID_1
GFX_VID_2
GFX_VID_3
GFX_VR_EN
CL_CLK
CL_DATA
CL_PWROK
CL_RST#
CL_VREF
SDVO_CTRL_CLK
CLK_REQ#
ICH_SYNC#
TEST_1
TEST_2
AV29
BB23
BA25
AV23
AW30
BA23
AW25
AW23
BE29
AY32
BD39
BG37
BG20
BK16
BG16
BE13
BH18
BJ15
BJ14
BE16
BL15
BK14
BK31
BL31
AR49
AW4
B42
C42
H48
H47
K44
K45
AN47
AJ38
AN42
AN46
AM47
AJ39
AN41
AN45
AJ46
AJ41
AM40
AM44
AJ47
AJ42
AM39
AM43
E35
A39
C38
B39
E36
AM49
AK50
AT43
AN49
AM50
H35
K36
G39
G40
A37
R32
3
SMRCOMP
SMRCOMP#
SM_RCOMP_VOH
SM_RCOMP_VOL
CLK_DREF_96M
CLK_DREF_96M#
CLK_DREF_SSC
CLK_DREF_SSC#
CLK_MCH_3GPLL
CLK_MCH_3GPLL#
DMI_ITX_MRX_N0
DMI_ITX_MRX_N1
DMI_ITX_MRX_N2
DMI_ITX_MRX_N3
DMI_ITX_MRX_P0
DMI_ITX_MRX_P1
DMI_ITX_MRX_P2
DMI_ITX_MRX_P3
DMI_MTX_IRX_N0
DMI_MTX_IRX_N1
DMI_MTX_IRX_N2
DMI_MTX_IRX_N3
DMI_MTX_IRX_P0
DMI_MTX_IRX_P1
DMI_MTX_IRX_P2
DMI_MTX_IRX_P3
CL_VREF
SDVO_CTRL_CLK
SDVO_CTRL_DATA
MCH_CLKREQ#
MCH_TEST_1
MCH_TEST_2
DDRA_CLK0 <14>
DDRA_CLK1 <14>
DDRB_CLK0 <15>
DDRB_CLK1 <15>
DDRA_CLK0# <14>
DDRA_CLK1# <14>
DDRB_CLK0# <15>
DDRB_CLK1# <15>
DDRA_CKE0 <14>
DDRA_CKE1 <14>
DDRB_CKE0 <15>
DDRB_CKE1 <15>
DDRA_SCS0# <14>
DDRA_SCS1# <14>
DDRB_SCS0# <15>
DDRB_SCS1# <15>
DDRA_ODT0 <14>
DDRA_ODT1 <14>
DDRB_ODT0 <15>
DDRB_ODT1 <15>
R516 20_0402_1%
1 2
R517 20_0402_1%
1 2
SM_VREF
CLK_DREF_96M <16>
CLK_DREF_96M# <16>
CLK_DREF_SSC <16>
CLK_DREF_SSC# <16>
CLK_MCH_3GPLL <16>
CLK_MCH_3GPLL# <16>
DMI_ITX_MRX_N0 <22>
DMI_ITX_MRX_N1 <22>
DMI_ITX_MRX_N2 <22>
DMI_ITX_MRX_N3 <22>
DMI_ITX_MRX_P0 <22>
DMI_ITX_MRX_P1 <22>
DMI_ITX_MRX_P2 <22>
DMI_ITX_MRX_P3 <22>
DMI_MTX_IRX_N0 <22>
DMI_MTX_IRX_N1 <22>
DMI_MTX_IRX_N2 <22>
DMI_MTX_IRX_N3 <22>
DMI_MTX_IRX_P0 <22>
DMI_MTX_IRX_P1 <22>
DMI_MTX_IRX_P2 <22>
DMI_MTX_IRX_P3 <22>
CL_CLK0 <22>
CL_DATA0 <22>
CL_PWROK <22>
CL_RST# <22>
MCH_CLKREQ# <16>
MCH_ICH_SYNC# <22>
R537 0_0402_5%
R538 20K_0402_5%
20mil
+1.8V
1
C639
0.1U_0402_16V4Z
2
C640
1
0.1U_0402_16V4Z
2
2
Layout Note:
SM_VREF trace
width and spacing
is 20/20.
+1.8V
R518
1K_0402_1%
1 2
R520
1 2
+1.25VS
1 2
1 2
1K_0402_1%
R528
1K_0402_1%
R531
392_0402_1%
CFG[17:3] have internal pull up
CFG[19:18] have internal pull down
+1.8V
R513
1K_0402_1%
R514
3.01K_0402_1%
R515
1K_0402_1%
C635
2.2U_0805_10V6K
C637
2.2U_0805_10V6K
CFG[2:0]
CFG5
CFG9
CFG[13:12]
CFG16
CFG19
CFG20
(PCIE/SDVO select)
SDVO_CTRLDATA
MCH_CFG_5
MCH_CFG_9
MCH_CFG_12
MCH_CFG_13
MCH_CFG_16
MCH_CFG_19
MCH_CFG_20
PM_EXTTS#0
PM_EXTTS#1
MCH_CLKREQ#
SDVO_CTRL_CLK
SDVO_CTRL_DATA
1
SM_RCOMP_VOH
SM_RCOMP_VOH
C636
0.01U_0402_16V7K
SM_RCOMP_VOL
C638
0.01U_0402_16V7K
CLK_DREF_96M#
CLK_DREF_SSC#
CLK_DREF_96M
CLK_DREF_SSC
1 2
R574 0_0402_5%PM@
1 2
R575 0_0402_5%PM@
1 2
R576 0_0402_5%PM@
1 2
R577 0_0402_5%PM@
Strap Pin Table
011 = 667MT/s FSB
010 = 800MT/s FSB
0 = DMI x 2
1 = DMI x 4
0 = Lane Reversal Enable
1 = Normal Operation
00 = Reserved
01 = XOR Mode Enabled
10 = All Z Mode Enabled
11 = Normal Operation
0 = Dynamic ODT Disabled
1 = Dynamic ODT Enabled
0 = Normal Operation
1 = DMI Lane Reversal Enable
0 = Only PCIE or SDVO is operational.
1 = PCIE/SDVO are operating simu.
0 = No SDVO Device Present
1 = SDVO Device Present
*
(Default)
*
*
*
(Default)
R521 4.02K_0402_1%@
R522 4.02K_0402_1%@
R523 4.02K_0402_1%@
R524 4.02K_0402_1%@
R526 4.02K_0402_1%@
R529 4.02K_0402_1%@
R530 4.02K_0402_1%@
R532 10K_0402_5%
R534 10K_0402_5%
R536 10K_0402_5%
R578 0_0402_5%@
R579 0_0402_5%@
1 2
1 2
(Default)
(Default)
(Default)
*
(Default)
*
*
(Default)
+3VS
+3VS
+1.05VS
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2006/08/18 2007/8/18
3
Compal Secret Data
Deciphered Date
Title
Size Document Number Rev
Custom
2
Date: Sheet
Compal Electronics, Inc.
Crestline (2/7)-DMI/DDR
IFTXX M/B LA-3541P Schematic
852Wednesday, November 01, 2006
1
of
0
5
4
3
2
1
DDRB_SDQ[0..63]
DDRB_SDM[0..7]
DDRB_SMA[0..13]
DDRA_SBS0 <14>
DDRA_SBS1 <14>
DDRA_SBS2 <14>
DDRA_SCAS# <14>
DDRA_SDQS0 <14>
DDRA_SDQS1 <14>
DDRA_SDQS2 <14>
DDRA_SDQS3 <14>
DDRA_SDQS4 <14>
DDRA_SDQS5 <14>
DDRA_SDQS6 <14>
DDRA_SDQS7 <14>
DDRA_SDQS0# <14>
DDRA_SDQS1# <14>
DDRA_SDQS2# <14>
DDRA_SDQS3# <14>
DDRA_SDQS4# <14>
DDRA_SDQS5# <14>
DDRA_SDQS6# <14>
DDRA_SDQS7# <14>
DDRA_SRAS# <14>
PAD
T18
DDRA_SWE# <14>
DDRB_SDQ0
DDRB_SDQ1
DDRB_SDQ2
DDRB_SDQ3
DDRB_SDQ4
DDRB_SDQ5
DDRB_SDQ6
DDRB_SDQ7
DDRB_SDQ8
DDRB_SDQ9
DDRB_SDQ10
DDRB_SDQ11
DDRB_SDQ12
DDRB_SDQ13
DDRB_SDQ14
DDRB_SDQ15
DDRB_SDQ16
DDRB_SDQ17
DDRB_SDQ18
DDRB_SDQ19
DDRB_SDQ20
DDRB_SDQ21
DDRB_SDQ22
DDRB_SDQ23
DDRB_SDQ24
DDRB_SDQ25
DDRB_SDQ26
DDRB_SDQ27
DDRB_SDQ28
DDRB_SDQ29
DDRB_SDQ30
DDRB_SDQ31
DDRB_SDQ32
DDRB_SDQ33
DDRB_SDQ34
DDRB_SDQ35
DDRB_SDQ36
DDRB_SDQ37
DDRB_SDQ38
DDRB_SDQ39
DDRB_SDQ40
DDRB_SDQ41
DDRB_SDQ42
DDRB_SDQ43
DDRB_SDQ44
DDRB_SDQ45
DDRB_SDQ46
DDRB_SDQ47
DDRB_SDQ48
DDRB_SDQ49
DDRB_SDQ50
DDRB_SDQ51
DDRB_SDQ52
DDRB_SDQ53
DDRB_SDQ54
DDRB_SDQ55
DDRB_SDQ56
DDRB_SDQ57
DDRB_SDQ58
DDRB_SDQ59
DDRB_SDQ60
DDRB_SDQ61
DDRB_SDQ62
DDRB_SDQ63
AP49
AR51
AW50
AW51
AN51
AN50
AV50
AV49
BA50
BB50
BA49
BE50
BA51
AY49
BF50
BF49
BJ50
BJ44
BJ43
BL43
BK47
BK49
BK43
BK42
BJ41
BL41
BJ37
BJ36
BK41
BJ40
BL35
BK37
BK13
BE11
BK11
BC11
BC13
BE12
BC12
BG12
BJ10
BK5
BL5
BK9
BK10
BF4
BH5
BG1
BC2
BK3
BE4
BD3
BA3
BB3
AR1
AT3
AY2
AY3
AU2
AT2
BL9
BJ8
BJ6
BJ2
U37E
SB_DQ_0
SB_DQ_1
SB_DQ_2
SB_DQ_3
SB_DQ_4
SB_DQ_5
SB_DQ_6
SB_DQ_7
SB_DQ_8
SB_DQ_9
SB_DQ_10
SB_DQ_11
SB_DQ_12
SB_DQ_13
SB_DQ_14
SB_DQ_15
SB_DQ_16
SB_DQ_17
SB_DQ_18
SB_DQ_19
SB_DQ_20
SB_DQ_21
SB_DQ_22
SB_DQ_23
SB_DQ_24
SB_DQ_25
SB_DQ_26
SB_DQ_27
SB_DQ_28
SB_DQ_29
SB_DQ_30
SB_DQ_31
SB_DQ_32
SB_DQ_33
SB_DQ_34
SB_DQ_35
SB_DQ_36
SB_DQ_37
SB_DQ_38
SB_DQ_39
SB_DQ_40
SB_DQ_41
SB_DQ_42
SB_DQ_43
SB_DQ_44
SB_DQ_45
SB_DQ_46
SB_DQ_47
SB_DQ_48
SB_DQ_49
SB_DQ_50
SB_DQ_51
SB_DQ_52
SB_DQ_53
SB_DQ_54
SB_DQ_55
SB_DQ_56
SB_DQ_57
SB_DQ_58
SB_DQ_59
SB_DQ_60
SB_DQ_61
SB_DQ_62
SB_DQ_63
CRESTLINE_1p0
PM@
AY17
SB_BS_0
BG18
SB_BS_1
BG36
SB_BS_2
BE17
SB_CAS#
SB_DM_0
SB_DM_1
SB_DM_2
SB_DM_3
SB_DM_4
SB_DM_5
SB_DM_6
SB_DM_7
SB_DQS_0
SB_DQS_1
SB_DQS_2
SB_DQS_3
SB_DQS_4
SB_DQS_5
SB_DQS_6
SB_DQS_7
SB_DQS#_0
SB_DQS#_1
SB_DQS#_2
SB_DQS#_3
SB_DQS#_4
SB_DQS#_5
SB_DQS#_6
SB_DQS#_7
SB_MA_0
SB_MA_1
SB_MA_2
SB_MA_3
SB_MA_4
SB_MA_5
SB_MA_6
SB_MA_7
SB_MA_8
SB_MA_9
SB_MA_10
SB_MA_11
SB_MA_12
SB_MA_13
SB_RAS#
SB_RCVEN#
SB_WE#
DDR SYSTEM MEMORY B
AR50
BD49
BK45
BL39
BH12
BJ7
BF3
AW2
AT50
BD50
BK46
BK39
BJ12
BL7
BE2
AV2
AU50
BC50
BL45
BK38
BK12
BK7
BF2
AV3
BC18
BG28
BG25
AW17
BF25
BE25
BA29
BC28
AY28
BD37
BG17
BE37
BA39
BG13
AV16
AY18
BC17
DDRB_SDM0
DDRB_SDM1
DDRB_SDM2
DDRB_SDM3
DDRB_SDM4
DDRB_SDM5
DDRB_SDM6
DDRB_SDM7
DDRB_SDQS0
DDRB_SDQS1
DDRB_SDQS2
DDRB_SDQS3
DDRB_SDQS4
DDRB_SDQS5
DDRB_SDQS6
DDRB_SDQS7
DDRB_SDQS0#
DDRB_SDQS1#
DDRB_SDQS2#
DDRB_SDQS3#
DDRB_SDQS4#
DDRB_SDQS5#
DDRB_SDQS6#
DDRB_SDQS7#
DDRB_SMA0
DDRB_SMA1
DDRB_SMA2
DDRB_SMA3
DDRB_SMA4
DDRB_SMA5
DDRB_SMA6
DDRB_SMA7
DDRB_SMA8
DDRB_SMA9
DDRB_SMA10
DDRB_SMA11
DDRB_SMA12
DDRB_SMA13
SB_RCVEN#
DDRB_SBS0 <15>
DDRB_SBS1 <15>
DDRB_SBS2 <15>
DDRB_SCAS# <15>
DDRB_SDQS0 <15>
DDRB_SDQS1 <15>
DDRB_SDQS2 <15>
DDRB_SDQS3 <15>
DDRB_SDQS4 <15>
DDRB_SDQS5 <15>
DDRB_SDQS6 <15>
DDRB_SDQS7 <15>
DDRB_SDQS0# <15>
DDRB_SDQS1# <15>
DDRB_SDQS2# <15>
DDRB_SDQS3# <15>
DDRB_SDQS4# <15>
DDRB_SDQS5# <15>
DDRB_SDQS6# <15>
DDRB_SDQS7# <15>
DDRB_SRAS# <15>
PAD
T17
DDRB_SWE# <15>
AR43
AW44
BA45
AY46
AR41
AR45
AT42
AW47
BB45
BF48
BG47
BJ45
BB47
BG50
BH49
BE45
AW43
BE44
BG42
BE40
BF44
BH45
BG40
BF40
AR40
AW40
AT39
AW36
AW41
AY41
AV38
AT38
AV13
AT13
AW11
AV11
AU15
AT11
BA13
BA11
BE10
BD10
BD8
BG10
AW9
BD7
AR5
AR8
AR9
AN3
AM8
AN10
AN9
AM9
AN11
AY9
BB9
BB5
AY7
AT5
AT7
AY6
BB7
AT9
DDRA_SDQ[0..63]
DDRA_SDM[0..7]
DDRA_SMA[0..13]
U37D
SA_DQ_0
SA_DQ_1
SA_DQ_2
SA_DQ_3
SA_DQ_4
SA_DQ_5
SA_DQ_6
SA_DQ_7
SA_DQ_8
SA_DQ_9
SA_DQ_10
SA_DQ_11
SA_DQ_12
SA_DQ_13
SA_DQ_14
SA_DQ_15
SA_DQ_16
SA_DQ_17
SA_DQ_18
SA_DQ_19
SA_DQ_20
SA_DQ_21
SA_DQ_22
SA_DQ_23
SA_DQ_24
SA_DQ_25
SA_DQ_26
SA_DQ_27
SA_DQ_28
SA_DQ_29
SA_DQ_30
SA_DQ_31
SA_DQ_32
SA_DQ_33
SA_DQ_34
SA_DQ_35
SA_DQ_36
SA_DQ_37
SA_DQ_38
SA_DQ_39
SA_DQ_40
SA_DQ_41
SA_DQ_42
SA_DQ_43
SA_DQ_44
SA_DQ_45
SA_DQ_46
SA_DQ_47
SA_DQ_48
SA_DQ_49
SA_DQ_50
SA_DQ_51
SA_DQ_52
SA_DQ_53
SA_DQ_54
SA_DQ_55
SA_DQ_56
SA_DQ_57
SA_DQ_58
SA_DQ_59
SA_DQ_60
SA_DQ_61
SA_DQ_62
SA_DQ_63
CRESTLINE_1p0
PM@
DDRB_SDQ[0..63]< 15>
DDRB_SDM[0..7]<15>
DDRB_SMA[0..13]<15>
BB19
SA_BS_0
BK19
SA_BS_1
BF29
SA_BS_2
BL17
SA_CAS#
SA_DM_0
SA_DM_1
SA_DM_2
SA_DM_3
SA_DM_4
SA_DM_5
SA_DM_6
SA_DM_7
SA_DQS_0
SA_DQS_1
SA_DQS_2
SA_DQS_3
SA_DQS_4
SA_DQS_5
SA_DQS_6
SA_DQS_7
SA_DQS#_0
SA_DQS#_1
SA_DQS#_2
SA_DQS#_3
SA_DQS#_4
SA_DQS#_5
SA_DQS#_6
SA_DQS#_7
SA_MA_0
SA_MA_1
SA_MA_2
SA_MA_3
SA_MA_4
SA_MA_5
SA_MA_6
SA_MA_7
SA_MA_8
SA_MA_9
SA_MA_10
SA_MA_11
SA_MA_12
SA_MA_13
SA_RAS#
SA_RCVEN#
DDR SYSTEM MEMORY A
SA_WE#
AT45
BD44
BD42
AW38
AW13
BG8
AY5
AN6
AT46
BE48
BB43
BC37
BB16
BH6
BB2
AP3
AT47
BD47
BC41
BA37
BA16
BH7
BC1
AP2
BJ19
BD20
BK27
BH28
BL24
BK28
BJ27
BJ25
BL28
BA28
BC19
BE28
BG30
BJ16
BE18
AY20
BA19
DDRA_SDM0
DDRA_SDM1
DDRA_SDM2
DDRA_SDM3
DDRA_SDM4
DDRA_SDM5
DDRA_SDM6
DDRA_SDM7
DDRA_SDQS0
DDRA_SDQS1
DDRA_SDQS2
DDRA_SDQS3
DDRA_SDQS4
DDRA_SDQS5
DDRA_SDQS6
DDRA_SDQS7
DDRA_SDQS0#
DDRA_SDQS1#
DDRA_SDQS2#
DDRA_SDQS3#
DDRA_SDQS4#
DDRA_SDQS5#
DDRA_SDQS6#
DDRA_SDQS7#
DDRA_SMA0
DDRA_SMA1
DDRA_SMA2
DDRA_SMA3
DDRA_SMA4
DDRA_SMA5
DDRA_SMA6
DDRA_SMA7
DDRA_SMA8
DDRA_SMA9
DDRA_SMA10
DDRA_SMA11
DDRA_SMA12
DDRA_SMA13
SA_RCVEN#
DDRA_SDQ[0..63]< 14>
D D
C C
B B
DDRA_SDM[0..7]<14>
DDRA_SMA[0..13]<14>
DDRA_SDQ0
DDRA_SDQ1
DDRA_SDQ2
DDRA_SDQ3
DDRA_SDQ4
DDRA_SDQ5
DDRA_SDQ6
DDRA_SDQ7
DDRA_SDQ8
DDRA_SDQ9
DDRA_SDQ10
DDRA_SDQ11
DDRA_SDQ12
DDRA_SDQ13
DDRA_SDQ14
DDRA_SDQ15
DDRA_SDQ16
DDRA_SDQ17
DDRA_SDQ18
DDRA_SDQ19
DDRA_SDQ20
DDRA_SDQ21
DDRA_SDQ22
DDRA_SDQ23
DDRA_SDQ24
DDRA_SDQ25
DDRA_SDQ26
DDRA_SDQ27
DDRA_SDQ28
DDRA_SDQ29
DDRA_SDQ30
DDRA_SDQ31
DDRA_SDQ32
DDRA_SDQ33
DDRA_SDQ34
DDRA_SDQ35
DDRA_SDQ36
DDRA_SDQ37
DDRA_SDQ38
DDRA_SDQ39
DDRA_SDQ40
DDRA_SDQ41
DDRA_SDQ42
DDRA_SDQ43
DDRA_SDQ44
DDRA_SDQ45
DDRA_SDQ46
DDRA_SDQ47
DDRA_SDQ48
DDRA_SDQ49
DDRA_SDQ50
DDRA_SDQ51
DDRA_SDQ52
DDRA_SDQ53
DDRA_SDQ54
DDRA_SDQ55
DDRA_SDQ56
DDRA_SDQ57
DDRA_SDQ58
DDRA_SDQ59
DDRA_SDQ60
DDRA_SDQ61
DDRA_SDQ62
DDRA_SDQ63
A A
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SE CRET INFOR MATI ON. THIS SHEET MAY NOT BE TRANSF ERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2006/08/18 2007/8/18
3
Compal Secret Data
Deciphered Date
Title
Size Document Number Rev
B
2
Date: Sheet of
Compal Electronics, Inc.
Crestline ( 3/7)- DDRII
IFTXX M/B LA-3541P Schematic
952Wednesday, November 01, 2006
1
0
5
GMCH_ENBKL<18>
D D
CRB 2.37K_1% to GND
C C
GMCH_TV_COMPS<19>
GMCH_TV_LUMA<19>
GMCH_TV_CRMA<19>
R494
GM@
150_0402_1%
GMCH_LCD_CLK<18>
GMCH_LCD_DATA<18>
GMCH_ENVDD<18> PCIE_MTX_C_GRX_N[0..15] <17>
1 2
R493 2.4K_0402_1%GM@
GMCH_TZCLK-<18>
GMCH_TZCLK+<18>
GMCH_TXCLK-<18>
GMCH_TXCLK+<18>
GMCH_TZOUT0-<18>
GMCH_TZOUT1-<18>
GMCH_TZOUT2-<18>
GMCH_TZOUT0+<18>
GMCH_TZOUT1+<18>
GMCH_TZOUT2+<18>
GMCH_TXOUT0-<18>
GMCH_TXOUT1-<18>
GMCH_TXOUT2-<18>
GMCH_TXOUT0+<18>
GMCH_TXOUT1+<18>
GMCH_TXOUT2+<18>
R495
R496
GM@
150_0402_1%
1 2
1 2
GM@
150_0402_1%
1 2
Change to 0Ohm when use PM chip
GMCH_CRT_B<19>
GMCH_CRT_G<19>
GMCH_CRT_R<19>
B B
GMCH_CRT_HSYNC<19>
GMCH_CRT_VSYNC<19>
CRB 2.2K , Follow!
+3VS
R503 2.2K_0402_5%GM@
1 2
R504 2.2K_0402_5%GM@
1 2
R505 10K_0402_5%GM@
A A
1 2
R506 10K_0402_5%GM@
1 2
R509 2.2K_0402_5%GM@
R510 2.2K_0402_5%GM@
5
R497 150_0402_1%GM@
R498 150_0402_1%GM@
R499 150_0402_1%GM@
1 2
R718 39_0402_1%GM@
1 2
R719 39_0402_1%GM@
GMCH_LCD_CLK
GMCH_LCD_DATA
LCTLB_DATA
LCTLA_CLK
TV_DCONSEL_0
TV_DCONSEL_1
12
12
12
GMCH_CRT_CLK<19>
GMCH_CRT_DATA<19>
R500
0_0402_5%
PM@
1 2
R588 0_0402_5%GM@
R501
0_0402_5%
PM@
4
LBKLT_EN
LCTLA_CLK
LCTLB_DATA
GMCH_LCD_CLK
GMCH_LCD_DATA
LVDS_IBG
GMCH_TZCLKGMCH_TZCLK+
GMCH_TXCLKGMCH_TXCLK+
GMCH_TZOUT0GMCH_TZOUT1GMCH_TZOUT2-
GMCH_TZOUT0+
GMCH_TZOUT1+
GMCH_TZOUT2+
GMCH_TXOUT0GMCH_TXOUT1GMCH_TXOUT2-
GMCH_TXOUT0+
GMCH_TXOUT1+
GMCH_TXOUT2+
GMCH_TV_COMPS
GMCH_TV_LUMA
GMCH_TV_CRMA
TV_DCONSEL_0
TV_DCONSEL_1
GMCH_CRT_CLK
GMCH_CRT_DATA
CRT_IREF
R502
1.3K_0402_1%
1 2
R580 0_0402_5%PM@
1 2
R581 0_0402_5%PM@
1 2
R582 0_0402_5%PM@
1 2
R583 0_0402_5%PM@
1 2
R584 0_0402_5%PM@
1 2
R585 0_0402_5%PM@
1 2
R586 0_0402_5%PM@
1 2
R587 0_0402_5%PM@
1 2
4
U37C
J40
L_BKLT_CTRL
H39
L_BKLT_EN
E39
L_CTRL_CLK
E40
L_CTRL_DATA
C37
L_DDC_CLK
D35
L_DDC_DATA
K40
L_VDD_EN
L41
LVDS_IBG
L43
LVDS_VBG
N41
LVDS_VREFH
N40
LVDS_VREFL
D46
LVDSA_CLK#
C45
LVDSA_CLK
D44
LVDSB_CLK#
E42
LVDSB_CLK
G51
LVDSA_DATA#_0
E51
LVDSA_DATA#_1
F49
LVDSA_DATA#_2
G50
LVDSA_DATA_0
E50
LVDSA_DATA_1
F48
LVDSA_DATA_2
G44
LVDSB_DATA#_0
B47
LVDSB_DATA#_1
B45
LVDSB_DATA#_2
E44
LVDSB_DATA_0
A47
LVDSB_DATA_1
A45
LVDSB_DATA_2
E27
TVA_DAC
G27
TVB_DAC
K27
TVC_DAC
F27
TVA_RTN
J27
TVB_RTN
L27
TVC_RTN
M35
TV_DCONSEL_0
P33
TV_DCONSEL_1
H32
CRT_BLUE
G32
CRT_BLUE#
K29
CRT_GREEN
J29
CRT_GREEN#
F29
CRT_RED
E29
CRT_RED#
K33
CRT_DDC_CLK
G35
CRT_DDC_DATA
F33
CRT_HSYNC
C32
CRT_TVO_IREF
E33
CRT_VSYNC
CRESTLINE_1p0
PM@
3
PEG_COMP
PEG_COMPI
PEG_COMPO
PEG_RX#_0
PEG_RX#_1
PEG_RX#_2
PEG_RX#_3
PEG_RX#_4
PEG_RX#_5
PEG_RX#_6
PEG_RX#_7
PEG_RX#_8
LVDS
TV VGA
GMCH_LCD_CLK
GMCH_LCD_DATA
LCTLB_DATA
LCTLA_CLK
GMCH_CRT_CLK
GMCH_CRT_DATA
TV_DCONSEL_0
TV_DCONSEL_1
PEG_RX#_9
PEG_RX#_10
PEG_RX#_11
PEG_RX#_12
PEG_RX#_13
PEG_RX#_14
PEG_RX#_15
PEG_RX_10
PEG_RX_11
PEG_RX_12
PEG_RX_13
PEG_RX_14
PEG_RX_15
PEG_TX#_0
PEG_TX#_1
PEG_TX#_2
PEG_TX#_3
PEG_TX#_4
PEG_TX#_5
PEG_TX#_6
PEG_TX#_7
PEG_TX#_8
PEG_TX#_9
PEG_TX#_10
PCI-EXPRESS GRAPHICS
PEG_TX#_11
PEG_TX#_12
PEG_TX#_13
PEG_TX#_14
PEG_TX#_15
PEG_TX_10
PEG_TX_11
PEG_TX_12
PEG_TX_13
PEG_TX_14
PEG_TX_15
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SE CRET INFOR MATI ON. THIS SHEET MAY NOT BE TRANSF ERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
N43
M43
J51
L51
N47
T45
T50
U40
Y44
Y40
AB51
W49
AD44
AD40
AG46
AH49
AG45
AG41
J50
PEG_RX_0
L50
PEG_RX_1
M47
PEG_RX_2
U44
PEG_RX_3
T49
PEG_RX_4
T41
PEG_RX_5
W45
PEG_RX_6
W41
PEG_RX_7
AB50
PEG_RX_8
Y48
PEG_RX_9
AC45
AC41
AH47
AG49
AH45
AG42
N45
U39
U47
N51
R50
T42
Y43
W46
W38
AD39
AC46
AC49
AC42
AH39
AE49
AH44
M45
PEG_TX_0
T38
PEG_TX_1
T46
PEG_TX_2
N50
PEG_TX_3
R51
PEG_TX_4
U43
PEG_TX_5
W42
PEG_TX_6
Y47
PEG_TX_7
Y39
PEG_TX_8
AC38
PEG_TX_9
AD47
AC50
AD43
AG39
AE50
AH43
R589 0_0402_5%PM@
R590 0_0402_5%PM@
R591 0_0402_5%PM@
R592 0_0402_5%PM@
R593 0_0402_5%PM@
R594 0_0402_5%PM@
2006/08/18 2007/8/18
20/25mils
PCIE_GTX_C_MRX_N0
PCIE_GTX_C_MRX_N1
PCIE_GTX_C_MRX_N2
PCIE_GTX_C_MRX_N3
PCIE_GTX_C_MRX_N4
PCIE_GTX_C_MRX_N5
PCIE_GTX_C_MRX_N6
PCIE_GTX_C_MRX_N7
PCIE_GTX_C_MRX_N8
PCIE_GTX_C_MRX_N9
PCIE_GTX_C_MRX_N10
PCIE_GTX_C_MRX_N11
PCIE_GTX_C_MRX_N12
PCIE_GTX_C_MRX_N13
PCIE_GTX_C_MRX_N14
PCIE_GTX_C_MRX_N15
PCIE_GTX_C_MRX_P0
PCIE_GTX_C_MRX_P1
PCIE_GTX_C_MRX_P2
PCIE_GTX_C_MRX_P3
PCIE_GTX_C_MRX_P4
PCIE_GTX_C_MRX_P5
PCIE_GTX_C_MRX_P6
PCIE_GTX_C_MRX_P7
PCIE_GTX_C_MRX_P8
PCIE_GTX_C_MRX_P9
PCIE_GTX_C_MRX_P10
PCIE_GTX_C_MRX_P11
PCIE_GTX_C_MRX_P12
PCIE_GTX_C_MRX_P13
PCIE_GTX_C_MRX_P14
PCIE_GTX_C_MRX_P15
PCIE_MTX_GRX_N0
PCIE_MTX_GRX_N1
PCIE_MTX_GRX_N2
PCIE_MTX_GRX_N3
PCIE_MTX_GRX_N4 PCIE_MTX_C_GRX_N4
PCIE_MTX_GRX_N5
PCIE_MTX_GRX_N6
PCIE_MTX_GRX_N7
PCIE_MTX_GRX_N8
PCIE_MTX_GRX_N9
PCIE_MTX_GRX_N10
PCIE_MTX_GRX_N11
PCIE_MTX_GRX_N12
PCIE_MTX_GRX_N13
PCIE_MTX_GRX_N14
PCIE_MTX_GRX_N15
PCIE_MTX_GRX_P0
PCIE_MTX_GRX_P1
PCIE_MTX_GRX_P2
PCIE_MTX_GRX_P3
PCIE_MTX_GRX_P4
PCIE_MTX_GRX_P5
PCIE_MTX_GRX_P6
PCIE_MTX_GRX_P7
PCIE_MTX_GRX_P8
PCIE_MTX_GRX_P9
PCIE_MTX_GRX_P10
PCIE_MTX_GRX_P11
PCIE_MTX_GRX_P12
PCIE_MTX_GRX_P13
PCIE_MTX_GRX_P14
PCIE_MTX_GRX_P15
1 2
1 2
1 2
1 2
1 2
1 2
Compal Secret Data
Deciphered Date
1 2
R492 24.9_0402_1%
C604 0.1U_0402_10V7KPM@
1 2
C606 0.1U_0402_10V7KPM@
1 2
C608 0.1U_0402_10V7KPM@
1 2
C610 0.1U_0402_10V7KPM@
1 2
C612 0.1U_0402_10V7KPM@
1 2
C614 0.1U_0402_10V7KPM@
1 2
C616 0.1U_0402_10V7KPM@
1 2
C618 0.1U_0402_10V7KPM@
1 2
C620 0.1U_0402_10V7KPM@
1 2
C622 0.1U_0402_10V7KPM@
1 2
C624 0.1U_0402_10V7KPM@
1 2
C626 0.1U_0402_10V7KPM@
1 2
C628 0.1U_0402_10V7KPM@
1 2
C630 0.1U_0402_10V7KPM@
1 2
C632 0.1U_0402_10V7KPM@
1 2
C634 0.1U_0402_10V7KPM@
1 2
GMCH_CRT_B
GMCH_CRT_G
GMCH_CRT_R
GMCH_TV_COMPS
GMCH_TV_LUMA
GMCH_TV_CRMA
2
2
+1.05VS
PCIE_MTX_C_GRX_N[0..15]
PCIE_MTX_C_GRX_P[0..15]
PCIE_GTX_C_MRX_N[0..15]
PCIE_GTX_C_MRX_P[0..15]
C603 0.1U_0402_10V7KPM@
1 2
C605 0.1U_0402_10V7KPM@
1 2
C607 0.1U_0402_10V7KPM@
1 2
C609 0.1U_0402_10V7KPM@
1 2
C611 0.1U_0402_10V7KPM@
1 2
C613 0.1U_0402_10V7KPM@
1 2
C615 0.1U_0402_10V7KPM@
1 2
C617 0.1U_0402_10V7KPM@
1 2
C619 0.1U_0402_10V7KPM@
1 2
C621 0.1U_0402_10V7KPM@
1 2
C623 0.1U_0402_10V7KPM@
1 2
C625 0.1U_0402_10V7KPM@
1 2
C627 0.1U_0402_10V7KPM@
1 2
C629 0.1U_0402_10V7KPM@
1 2
C631 0.1U_0402_10V7KPM@
1 2
C633 0.1U_0402_10V7KPM@
1 2
1
PCIE_MTX_C_GRX_P[0..15] <17>
PCIE_GTX_C_MRX_N[0..15] <17>
PCIE_GTX_C_MRX_P[0..15] <17>
PCIE_MTX_C_GRX_N0
PCIE_MTX_C_GRX_N1
PCIE_MTX_C_GRX_N2
PCIE_MTX_C_GRX_N3
PCIE_MTX_C_GRX_N5
PCIE_MTX_C_GRX_N6
PCIE_MTX_C_GRX_N7
PCIE_MTX_C_GRX_N8
PCIE_MTX_C_GRX_N9
PCIE_MTX_C_GRX_N10
PCIE_MTX_C_GRX_N11
PCIE_MTX_C_GRX_N12
PCIE_MTX_C_GRX_N13
PCIE_MTX_C_GRX_N14
PCIE_MTX_C_GRX_N15
PCIE_MTX_C_GRX_P0
PCIE_MTX_C_GRX_P1
PCIE_MTX_C_GRX_P2
PCIE_MTX_C_GRX_P3
PCIE_MTX_C_GRX_P4
PCIE_MTX_C_GRX_P5
PCIE_MTX_C_GRX_P6
PCIE_MTX_C_GRX_P7
PCIE_MTX_C_GRX_P8
PCIE_MTX_C_GRX_P9
PCIE_MTX_C_GRX_P10
PCIE_MTX_C_GRX_P11
PCIE_MTX_C_GRX_P12
PCIE_MTX_C_GRX_P13
PCIE_MTX_C_GRX_P14
PCIE_MTX_C_GRX_P15
Title
Size Document Number Rev
B
Date: Sheet
Compal Electronics, Inc.
Crestline (4/7)-VGA/LVDS/TV
IFTXX M/B LA-3541P Schematic
10 52Wednesday, November 01, 2006
1
of
0
5
U37G
+1.05VS
D D
Replace 0 Ohm
by directly
connection
C C
B B
A A
+1.8V
+VCC_AXG
AT35
AT34
AH28
AC32
AC31
AK32
AJ31
AJ28
AH32
AH31
AH29
AF32
R30
AU32
AU33
AU35
AV33
AW33
AW35
AY35
BA32
BA33
BA35
BB33
BC32
BC33
BC35
BD32
BD35
BE32
BE33
BE35
BF33
BF34
BG32
BG33
BG35
BH32
BH34
BH35
BJ32
BJ33
BJ34
BK32
BK33
BK34
BK35
BL33
AU30
R20
W13
W14
Y12
AA20
AA23
AA26
AA28
AB21
AB24
AB29
AC20
AC21
AC23
AC24
AC26
AC28
AC29
AD20
AD23
AD24
AD28
AF21
AF26
AA31
AH20
AH21
AH23
AH24
AH26
AD31
AJ20
AN14
T14
VCC_1
VCC_2
VCC_3
VCC_5
VCC_4
VCC_6
VCC_7
VCC_8
VCC_9
VCC_10
VCC_11
VCC_12
VCC_13
VCC_SM_1
VCC_SM_2
VCC_SM_3
VCC_SM_4
VCC_SM_5
VCC_SM_6
VCC_SM_7
VCC_SM_8
VCC_SM_9
VCC_SM_10
VCC_SM_11
VCC_SM_12
VCC_SM_13
VCC_SM_14
VCC_SM_15
VCC_SM_16
VCC_SM_17
VCC_SM_18
VCC_SM_19
VCC_SM_20
VCC_SM_21
VCC_SM_22
VCC_SM_23
VCC_SM_24
VCC_SM_25
VCC_SM_26
VCC_SM_27
VCC_SM_28
VCC_SM_29
VCC_SM_30
VCC_SM_31
VCC_SM_32
VCC_SM_33
VCC_SM_34
VCC_SM_35
VCC_SM_36
VCC_AXG_1
VCC_AXG_2
VCC_AXG_3
VCC_AXG_4
VCC_AXG_5
VCC_AXG_6
VCC_AXG_7
VCC_AXG_8
VCC_AXG_9
VCC_AXG_10
VCC_AXG_11
VCC_AXG_12
VCC_AXG_13
VCC_AXG_14
VCC_AXG_15
VCC_AXG_16
VCC_AXG_17
VCC_AXG_18
VCC_AXG_19
VCC_AXG_20
VCC_AXG_21
VCC_AXG_22
VCC_AXG_23
VCC_AXG_24
VCC_AXG_25
VCC_AXG_26
VCC_AXG_27
VCC_AXG_28
VCC_AXG_29
VCC_AXG_30
VCC_AXG_31
VCC_AXG_32
VCC_AXG_33
VCC_AXG_34
VCC CORE
POWER
VCC SMVCC GFX
VCC_AXG_NCTF_1
VCC_AXG_NCTF_2
VCC_AXG_NCTF_3
VCC_AXG_NCTF_4
VCC_AXG_NCTF_5
VCC_AXG_NCTF_6
VCC_AXG_NCTF_7
VCC_AXG_NCTF_8
VCC_AXG_NCTF_9
VCC_AXG_NCTF_10
VCC_AXG_NCTF_11
VCC_AXG_NCTF_12
VCC_AXG_NCTF_13
VCC_AXG_NCTF_14
VCC_AXG_NCTF_15
VCC_AXG_NCTF_16
VCC_AXG_NCTF_17
VCC_AXG_NCTF_18
VCC_AXG_NCTF_19
VCC_AXG_NCTF_20
VCC_AXG_NCTF_21
VCC_AXG_NCTF_22
VCC_AXG_NCTF_23
VCC_AXG_NCTF_24
VCC_AXG_NCTF_25
VCC_AXG_NCTF_26
VCC_AXG_NCTF_27
VCC_AXG_NCTF_28
VCC_AXG_NCTF_29
VCC_AXG_NCTF_30
VCC_AXG_NCTF_31
VCC_AXG_NCTF_32
VCC_AXG_NCTF_33
VCC_AXG_NCTF_34
VCC_AXG_NCTF_35
VCC_AXG_NCTF_36
VCC_AXG_NCTF_37
VCC_AXG_NCTF_38
VCC_AXG_NCTF_39
VCC_AXG_NCTF_40
VCC_AXG_NCTF_41
VCC_AXG_NCTF_42
VCC_AXG_NCTF_43
VCC_AXG_NCTF_44
VCC_AXG_NCTF_45
VCC_AXG_NCTF_46
VCC_AXG_NCTF_47
VCC_AXG_NCTF_48
VCC_AXG_NCTF_49
VCC_AXG_NCTF_50
VCC_AXG_NCTF_51
VCC_AXG_NCTF_52
VCC_AXG_NCTF_53
VCC_AXG_NCTF_54
VCC GFX NCTF
VCC_AXG_NCTF_55
VCC_AXG_NCTF_56
VCC_AXG_NCTF_57
VCC_AXG_NCTF_58
VCC_AXG_NCTF_59
VCC_AXG_NCTF_60
VCC_AXG_NCTF_61
VCC_AXG_NCTF_62
VCC_AXG_NCTF_63
VCC_AXG_NCTF_64
VCC_AXG_NCTF_65
VCC_AXG_NCTF_66
VCC_AXG_NCTF_67
VCC_AXG_NCTF_68
VCC_AXG_NCTF_69
VCC_AXG_NCTF_70
VCC_AXG_NCTF_71
VCC_AXG_NCTF_72
VCC_AXG_NCTF_73
VCC_AXG_NCTF_74
VCC_AXG_NCTF_75
VCC_AXG_NCTF_76
VCC_AXG_NCTF_77
VCC_AXG_NCTF_78
VCC_AXG_NCTF_79
VCC_AXG_NCTF_80
VCC_AXG_NCTF_81
VCC_AXG_NCTF_82
VCC_AXG_NCTF_83
VCC SM LF
VCC_SM_LF1
VCC_SM_LF2
VCC_SM_LF3
VCC_SM_LF4
VCC_SM_LF5
VCC_SM_LF6
VCC_SM_LF7
4
9/18 modify from +1.05VS to +VCC_AXG
T17
T18
T19
T21
T22
T23
T25
U15
U16
U17
U19
U20
U21
U23
U26
V16
V17
V19
V20
V21
V23
V24
Y15
Y16
Y17
Y19
Y20
Y21
Y23
Y24
Y26
Y28
Y29
AA16
AA17
AB16
AB19
AC16
AC17
AC19
AD15
AD16
AD17
AF16
AF19
AH15
AH16
AH17
AH19
AJ16
AJ17
AJ19
AK16
AK19
AL16
AL17
AL19
AL20
AL21
AL23
AM15
AM16
AM19
AM20
AM21
AM23
AP15
AP16
AP17
AP19
AP20
AP21
AP23
AP24
AR20
AR21
AR23
AR24
AR26
V26
V28
V29
Y31
AW45
BC39
BE39
BD17
BD4
AW8
AT6
+VCC_AXG
VCC: 1573mA
+1.05VS
(220UF*1, 22UF*1, 0.22UF*2, 0.1UF*1)
1
+
C573
220U_D2_2VMR15
2
C578
330U_D2E_2.5VM
22U_0805_6.3V6M
VCC_SM: 3300mA
+1.8V
(330UF*1, 22UF*2, 0.1UF*1)
1
+
2
22U_0805_6.3V6M@
9/18 modify from +1.05VS to +VCC_AXG 9/18 Add for 965PM use
VCC_AXG: 7700mA
(330UF*2, 22UF*1, 10UF*1, 1U*1, 0.47U*1, 0.1UF*2)
1
C583
+
2
GM@
330U_D2E_2.5VM
+1.05VS
1
C597
0.22U_0603_16V7K
2
0.1U_0402_16V4Z
VCCSM_LF1
VCCSM_LF2
VCCSM_LF3
VCCSM_LF4
VCCSM_LF5
VCCSM_LF6
VCCSM_LF7
C596
0.1U_0402_16V4Z
+VCC_AXG
C582
330U_D2E_2.5VM
GM@
1
2
3
CRB 270uF , there is no 270u part.
9/19 change to 330u, 9/29 change to 220u
1
C574
0.22U_0603_16V7K
2
1
C579
22U_0805_6.3V6M
2
1
C584
+
22U_0805_6.3V6M
2
GM@
C590
22U_0805_6.3V6M
C575
0.22U_0603_16V7K
1
C580
2
4.7U_0805_10V4Z
C585
1
2
GM@
10U_0805_10V4Z
VCC_AXM: 540mA
(22UF*2, 0.22UF *2, 0.1UF*2)
1
C591
2
0.22U_0603_16V7K
C576
0.1U_0402_16V4Z
C692
1U_0603_10V4Z
C586
1
1U_0603_10V4Z
2
GM@
C592
0.22U_0603_16V7K
1
C577
2
C581
0.47U_0603_16V4Z
0.1U_0402_16V4Z
9/29 +1.05VS_AXM change to +1.05VS
+1.05VS +VCC_AXG
C598
0.22U_0603_16V7K
C599
J6
1 2
PAD-OPEN 3x3m
@
C600
0.47U_0603_16V4Z
C601
1U_0603_10V4Z
Follow DG 1.1
9/14 add fo r r eservation
0.1U_0402_16V4Z@
C587
GM@
C593
1
C690
2
1
2
C691
1U_0603_10V4Z
@
C588
1
0.1U_0402_16V4Z
2
GM@
1
C594
0.1U_0402_16V4Z
2
C589
GM@
0.1U_0402_16V4Z
C595
0.1U_0402_16V4Z
1005 This is for GM@
Remember open stencil at GM@
C602
1U_0603_10V4Z
2
U37F
+1.05VS
1
2
1
2
R609
0_0805_5%
PM@
+1.05VS
AB33
VCC_NCTF_1
AB36
VCC_NCTF_2
AB37
VCC_NCTF_3
AC33
VCC_NCTF_4
AC35
VCC_NCTF_5
AC36
VCC_NCTF_6
AD35
VCC_NCTF_7
AD36
VCC_NCTF_8
AF33
VCC_NCTF_9
AF36
VCC_NCTF_10
AH33
VCC_NCTF_11
AH35
VCC_NCTF_12
AH36
VCC_NCTF_13
AH37
VCC_NCTF_14
AJ33
VCC_NCTF_15
AJ35
VCC_NCTF_16
AK33
VCC_NCTF_17
AK35
VCC_NCTF_18
AK36
VCC_NCTF_19
AK37
VCC_NCTF_20
AD33
VCC_NCTF_21
AJ36
VCC_NCTF_22
AM35
VCC_NCTF_23
AL33
VCC_NCTF_24
AL35
VCC_NCTF_25
AA33
VCC_NCTF_26
AA35
VCC_NCTF_27
AA36
VCC_NCTF_28
AP35
VCC_NCTF_29
AP36
VCC_NCTF_30
AR35
VCC_NCTF_31
AR36
VCC_NCTF_32
Y32
VCC_NCTF_33
Y33
VCC_NCTF_34
Y35
VCC_NCTF_35
Y36
VCC_NCTF_36
Y37
VCC_NCTF_37
T30
VCC_NCTF_38
T34
VCC_NCTF_39
T35
VCC_NCTF_40
U29
VCC_NCTF_41
U31
VCC_NCTF_42
U32
VCC_NCTF_43
U33
VCC_NCTF_44
U35
VCC_NCTF_45
U36
VCC_NCTF_46
V32
VCC_NCTF_47
V33
VCC_NCTF_48
V36
VCC_NCTF_49
V37
VCC_NCTF_50
AL24
VCC_AXM_NCTF_1
AL26
VCC_AXM_NCTF_2
AL28
VCC_AXM_NCTF_3
AM26
VCC_AXM_NCTF_4
AM28
VCC_AXM_NCTF_5
AM29
VCC_AXM_NCTF_6
AM31
VCC_AXM_NCTF_7
AM32
VCC_AXM_NCTF_8
AM33
VCC_AXM_NCTF_9
AP29
VCC_AXM_NCTF_10
AP31
VCC_AXM_NCTF_11
AP32
VCC_AXM_NCTF_12
AP33
VCC_AXM_NCTF_13
AL29
VCC_AXM_NCTF_14
AL31
VCC_AXM_NCTF_15
AL32
VCC_AXM_NCTF_16
AR31
VCC_AXM_NCTF_17
AR32
VCC_AXM_NCTF_18
AR33
VCC_AXM_NCTF_19
CRESTLINE_1p0
PM@
VSS NCTF
VCC NCTF
POWER
VCC AXM NCTF
VSS_NCTF_1
VSS_NCTF_2
VSS_NCTF_3
VSS_NCTF_4
VSS_NCTF_5
VSS_NCTF_6
VSS_NCTF_7
VSS_NCTF_8
VSS_NCTF_9
VSS_NCTF_10
VSS_NCTF_11
VSS_NCTF_12
VSS_NCTF_13
VSS_NCTF_14
VSS_NCTF_15
VSS_NCTF_16
VSS_NCTF_17
VSS_NCTF_18
VSS_NCTF_19
VSS_NCTF_20
VSS_NCTF_21
VSS_SCB1
VSS_SCB2
VSS_SCB3
VSS_SCB4
VSS_SCB5
VSS_SCB6
VSS SCBVCC AXM
VCC_AXM_1
VCC_AXM_2
VCC_AXM_3
VCC_AXM_4
VCC_AXM_5
VCC_AXM_6
VCC_AXM_7
1
T27
T37
U24
U28
V31
V35
AA19
AB17
AB35
AD19
AD37
AF17
AF35
AK17
AM17
AM24
AP26
AP28
AR15
AR19
AR28
A3
B2
C1
BL1
BL51
A51
AT33
AT31
AK29
AK24
AK23
AJ26
AJ23
+1.05VS
9/29
+1.05VS_AXM
change to
+1.05VS
CRESTLINE_1p0
PM@
9/18 modify from +1.05VS to +VCC_AXG
5
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2006/08/18 2007/8/18
3
Compal Secret Data
Deciphered Date
Title
Size Document Number Rev
B
2
Date: Sheet
Compal Electronics, Inc.
Crestline (5/7)-VCC
IFTXX M/B LA-3541P Schematic
11 52Wednesday, November 01, 2006
of
1
0
5
VCCA_HPLL: 50mA
(22UF*1, 0.1UF*1)
L39
+1.25VS
D D
C C
VCC_SYNC: 10mA (0.1UF*1)
+3VS
1 2
MBK1608121YZF_0603
22U_0805_6.3V6M
VCCA_MPLL:150mA
(10UF*1, 0.1UF*1)
L41
1 2
MBK1608121YZF_0603
22U_0805_6.3V6M
R476 0_0402_5%
GM@
0.1U_0402_16V4Z
C511
R471
0.5_0603_1%
C522
C536
GM@
VCCA_CRT_DAC: 80mA (0.1UF*1, 0.022UF*1)
L46
+3VS
B B
1 2
MBK1608121YZF_0603
GM@
0.1U_0402_16V4Z
C546
GM@
VCCA_DAC_BG: 5mA (0.1UF*1, 0.022UF*1)
L49
MBK1608121YZF_0603
GM@
L52
MBK1608121YZF_0603
GM@
L53
+1.5VS
MBK1608121YZF_0603
1 2
C552
0.1U_0402_16V4Z
GM@
VCCA_TV_DAC: 40mA each DAC (0.1UF*1, 0.022UF*1 for each DAC)
1 2
1
C563
2
10U_0805_10V4Z
GM@
+1.5VS_TVDAC
1 2
1
C689
10U_0805_10V4Z
PM@
2
5
+3VS
+3VS
A A
1
2
1
2
+3VS_SYNC
1
R477
0_0402_5%
2
PM@
1
C547
2
GM@
1
C553
2
GM@
1
C564
GM@
0.1U_0402_16V4Z
2
+1.25VS_HPLL
1
C512
0.1U_0402_16V4Z
2
+1.25VS_MPLL
1
C520
0.1U_0402_16V4Z
2
+1.25VS
+3VS_CRTDAC
0.022U_0402_16V7K
+3VS_DACBG
0.022U_0402_16V7K
C565
C566
GM@
0.1U_0402_16V4Z
0.022U_0402_16V7K
GM@
+1.5VS
+1.25VS
+1.25VS
R481
0_0402_5%
PM@
R482
0_0402_5%
PM@
VCCA_DPLLA/B: 100mA
(470UF*1, 0.1UF*1)
L40
1 2
10U_FLC-453232-100K_0.25A_10%
470U_D2_2.5VMR12
VCCA_DPLLA/B: 100mA
(470UF*1, 0.1UF*1)
L42
1 2
10U_FLC-453232-100K_0.25A_10%
470U_D2_2.5VMR12
+1.25VS
12
C529
10U_0805_10V4Z
1 2
R475 0_0805_5%
R479 0_0603_5%
+1.5VS_TVDAC
0.1U_0402_16V4Z
VCCA_PEG_PLL: 100mA
(0.1UF*1)
1
2
L54
MBK1608121YZF_0603
GM@
C568
C567
GM@
0.1U_0402_16V4Z
0.022U_0402_16V7K
GM@
1 2
0.1U_0402_16V4Z
4
+1.25VS_DPLLA
1
+
C510
+1.8V_TX_LVDS
+3VS
0.1U_0402_16V4Z
L43
1 2
MBK1608121YZF_0603
R474 1_0603_5%
+1.25VS_A_SM_CK
C540
22U_0805_6.3V6M
0.1U_0402_16V4Z
2
1
+
C519
0.1U_0402_16V4Z
2
C525
1000P_0402_50V7K
GM@
1
C526
2
+1.25VS_A_PEGPLL
0.1U_0402_16V4Z
+1.25VS_A_SM
1
C532
22U_0805_6.3V6M
@
C533
2
22U_0805_6.3V6M
VCCA_SM_CK: 35mA
(22UF*1, 1UF*2, 0.1UF*1)
1
C541
2
@
1U_0603_10V4Z
VCCD_TVDAC / CRT: each 60mA (0.1UF*1, 0.022UF*1)
1
C548
C549
2
0.022U_0402_16V7K
VCCD_HPLL: 250mA (0.1UF*1)
+1.25VS
0.1U_0402_16V4Z
+3VS_A_TVDAC
1
C569
2
0.022U_0402_16V7K
GM@
VCCD_QDAC: 5mA
(0.1UF*1, 0.022UF*1)
1
C571
C572
0.022U_0402_16V7K
2
GM@
GM@
4
1
C513
2
+1.25VS_DPLLB
C521
1
2
VCCA_PEG_BG: 5mA
(0.1UF*1)
C530
VCCA_SM: 640mA
(22UF*21, 4.7UF*1, 1UF*1)
1
2
C542
1U_0603_10V4Z
+3VS_A_TVDAC
R572 0_0402_5%
GM@
1
C554
2
R485
0_0402_5%
PM@
+1.5VS_QDAC
+3VS_CRTDAC
+3VS_DACBG
1
2
VCCA_LVDS: 10mA
(0.1UF*1)
1
VCCA_PEG_PLL: 100mA
(0.1UF*1)
2
C534
4.7U_0805_10V4Z
1U_0603_10V4Z
C543
@
0.1U_0402_16V4Z
R573
0_0402_5%
PM@
+1.25VS_A_PEGPLL
C555
0.1U_0402_16V4Z
+1.8V
R483 0_0402_5%
R488
0_0402_5%
PM@
+3VS_SYNC
+1.25VS_DPLLA
+1.25VS_DPLLB
+1.25VS_HPLL
+1.25VS_MPLL
C535
1
2
VCCD_CRT
+1.5VS_TVDAC
+1.5VS_QDAC
1
2
GM@
10U_0805_10V4Z
VCCD_LVDS: 150mA
(10UF*1, 0.1UF*1)
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SE CRET INFOR MATI ON. THIS SHEET MAY NOT BE TRANSF ERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C561
@
J32
A33
B33
A30
B32
B49
H49
AL2
AM2
A41
B41
K50
K49
U51
AW18
AV19
AU19
AU18
AU17
AT22
AT21
AT19
AT18
AT17
AR17
AR16
BC29
BB29
C25
B25
C27
B27
B28
A28
M32
L29
N28
AN2
U48
J41
H42
+1.8V_LVDS
1
C562
2
GM@
1U_0603_10V4Z
3
U37H
VCCSYNC
VCCA_CRT_DAC_1
VCCA_CRT_DAC_2
VCCA_DAC_BG
VSSA_DAC_BG
VCCA_DPLLA
VCCA_DPLLB
VCCA_HPLL
VCCA_MPLL
VCCA_LVDS
VSSA_LVDS
VCCA_PEG_BG
VSSA_PEG_BG
VCCA_PEG_PLL
VCCA_SM_1
VCCA_SM_2
VCCA_SM_3
VCCA_SM_4
VCCA_SM_5
VCCA_SM_7
VCCA_SM_8
VCCA_SM_9
VCCA_SM_10
VCCA_SM_11
VCCA_SM_NCTF_1
VCCA_SM_NCTF_2
VCCA_SM_CK_1
VCCA_SM_CK_2
VCCA_TVA_DAC_1
VCCA_TVA_DAC_2
VCCA_TVB_DAC_1
VCCA_TVB_DAC_2
VCCA_TVC_DAC_1
VCCA_TVC_DAC_2
VCCD_CRT
VCCD_TVDAC
VCCD_QDAC
VCCD_HPLL
VCCD_PEG_PLL
VCCD_LVDS_1
VCCD_LVDS_2
CRESTLINE_1p0
PM@
2006/08/18 2007/8/18
3
R484
0_0402_5%
PM@
CRTPLLA PEGA SMTV
POWER
A CK A LVDS
D TV/CRTLVDS
Compal Secret Data
VCC_AXD_1
VCC_AXD_2
VCC_AXD_3
VCC_AXD_4
VCC_AXD_5
AXD
VCC_AXD_6
VCC_AXD_NCTF
VCC_AXF_1
VCC_AXF_2
VCC_AXF_3
AXF
VCC_SM_CK_1
VCC_SM_CK_2
VCC_SM_CK_3
VCC_SM_CK_4
SM CK
VCC_TX_LVDS
HV
VCC_PEG_1
VCC_PEG_2
VCC_PEG_3
VCC_PEG_4
PEG
VCC_PEG_5
VCC_RXR_DMI_1
VCC_RXR_DMI_2
DMI
+1.05VS +3VS
Deciphered Date
VTT_1
VTT_2
VTT_3
VTT_4
VTT_5
VTT_6
VTT_7
VTT_8
VTT_9
VTT_10
VTT_11
VTT_12
VTT_13
VTT
VTT_14
VTT_15
VTT_16
VTT_17
VTT_18
VTT_19
VTT_20
VTT_21
VTT_22
VCC_DMI
VCC_HV_1
VCC_HV_2
VTTLF1
VTTLF2
VTTLF3
VTTLF
0.47U_0603_16V4Z
D41
2 1
RB751V_SOD323
U13
U12
U11
U9
U8
U7
U5
U3
U2
U1
T13
T11
T10
T9
T7
T6
T5
T3
T2
R3
R2
R1
AT23
AU28
AU24
AT29
AT25
AT30
AR29
B23
B21
A21
AJ50
BK24
BK23
BJ24
BJ23
A43
C40
B40
AD51
W50
W51
V49
V50
AH50
AH51
A7
F2
AH1
2
+1.05VS
1
+
C514
330U_D2E_2.5VM
2
+1.25VS_AXD
C524
1U_0603_10V4Z
+1.8V_TX_LVDS: 100mA
(220UF*1, 1000PF*1)
VCC_HV: 100mA
VTTLF_CAP1
VTTLF_CAP2
VTTLF_CAP3
R486
1 2
10_0603_5%
C556
0.47U_0603_16V4Z
2
+3VS
220U_D2_2VMR15
GM@
C557
VTT: 850mA
(220UF*1, 4.7UF*21, 2.2UF*1, 0.47UF*1)
C515
4.7U_0805_10V4Z
VCC_AXD: 515mA
(22UF*1, 1UF*1)
1
C523
22U_0805_6.3V6M
2
VCC_AXF: 495mA
+1.25VS_AXF
(10UF*1, 1UF*1)
1
C527
10U_0805_10V4Z
2
1
C531
0.1U_0402_16V4Z
2
22U_0805_6.3V6M
+1.8V_TX_LVDS
1
+
C544
C545
2
GM@
1000P_0402_50V7K
+1.05VS_PEG
C550
220U_D2_2VMR15
R472 0_0603_5%
C537
C517
C516
4.7U_0805_10V4Z
R473 0_0603_5%
C528
1U_0603_10V4Z
+1.25VS
+1.8V_SM_CK
1
2
0.1U_0402_16V4Z
1
2
2.2U_0805_10V6K
VCC_DMI: 100mA (0.1UF*1)
VCC_SM_CK: 2 00mA (22UF*1, 0.1UF*1)
1
C538
2
L45
1 2
MBK1608121YZF_0603
GM@
R480
0_0402_5%
PM@
+1.05VS_P E G : 1 2 6 0 mA (220UF*1, 10UF*1)
1
2
+
C551
10U_0805_10V4Z
1
2
+1.05VS_DMI: 100mA (220UF*1, 10UF*1)
C558
0.47U_0603_16V4Z
1
C560
10U_0805_10V4Z
2
Title
Size Document Number Rev
B
Date: Sheet
+1.05VS_PEG
Compal Electronics, Inc.
Crestline (6/7)-VCC
IFTXX M/B LA-3541P Schematic
1
C518
0.47U_0603_16V4Z
+1.25VS
+1.25VS
1 2
L44
MBK1608121YZF_0603
R478
1_0603_5%
+1.8V
1 2
R720 0_0805_5%
0.1U_0402_16V4Z
+1.8V
1 2
C539
10U_0805_10V4Z
+1.05VS
+3VS
1
C570
2
Close to VCC_HV (pin C40/B40)
12 52Wednesday, November 01, 2006
1
0
of
5
U37I
A13
VSS_1
A15
VSS_2
A17
VSS_3
A24
VSS_4
AA21
VSS_5
AA24
VSS_6
AA29
VSS_7
AB20
VSS_8
AB23
VSS_9
AB26
VSS_10
D D
C C
B B
A A
AB28
VSS_11
AB31
VSS_12
AC10
VSS_13
AC13
VSS_14
AC3
VSS_15
AC39
VSS_16
AC43
VSS_17
AC47
VSS_18
AD1
VSS_19
AD21
VSS_20
AD26
VSS_21
AD29
VSS_22
AD3
VSS_23
AD41
VSS_24
AD45
VSS_25
AD49
VSS_26
AD5
VSS_27
AD50
VSS_28
AD8
VSS_29
AE10
VSS_30
AE14
VSS_31
AE6
VSS_32
AF20
VSS_33
AF23
VSS_34
AF24
VSS_35
AF31
VSS_36
AG2
VSS_37
AG38
VSS_38
AG43
VSS_39
AG47
VSS_40
AG50
VSS_41
AH3
VSS_42
AH40
VSS_43
AH41
VSS_44
AH7
VSS_45
AH9
VSS_46
AJ11
VSS_47
AJ13
VSS_48
AJ21
VSS_49
AJ24
VSS_50
AJ29
VSS_51
AJ32
VSS_52
AJ43
VSS_53
AJ45
VSS_54
AJ49
VSS_55
AK20
VSS_56
AK21
VSS_57
AK26
VSS_58
AK28
VSS_59
AK31
VSS_60
AK51
VSS_61
AL1
VSS_62
AM11
VSS_63
AM13
VSS_64
AM3
VSS_65
AM4
VSS_66
AM41
VSS_67
AM45
VSS_68
AN1
VSS_69
AN38
VSS_70
AN39
VSS_71
AN43
VSS_72
AN5
VSS_73
AN7
VSS_74
AP4
VSS_75
AP48
VSS_76
AP50
VSS_77
AR11
VSS_78
AR2
VSS_79
AR39
VSS_80
AR44
VSS_81
AR47
VSS_82
AR7
VSS_83
AT10
VSS_84
AT14
VSS_85
AT41
VSS_86
AT49
VSS_87
AU1
VSS_88
AU23
VSS_89
AU29
VSS_90
AU3
VSS_91
AU36
VSS_92
AU49
VSS_93
AU51
VSS_94
AV39
VSS_95
AV48
VSS_96
AW1
VSS_97
AW12
VSS_98
AW16
VSS_99
CRESTLINE_1p0
PM@
5
VSS
VSS_100
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105
VSS_106
VSS_107
VSS_108
VSS_109
VSS_110
VSS_111
VSS_112
VSS_113
VSS_114
VSS_115
VSS_116
VSS_117
VSS_118
VSS_119
VSS_120
VSS_121
VSS_122
VSS_123
VSS_124
VSS_125
VSS_126
VSS_127
VSS_128
VSS_129
VSS_130
VSS_131
VSS_132
VSS_133
VSS_134
VSS_135
VSS_136
VSS_137
VSS_138
VSS_139
VSS_140
VSS_141
VSS_142
VSS_143
VSS_144
VSS_145
VSS_146
VSS_147
VSS_148
VSS_149
VSS_150
VSS_151
VSS_152
VSS_153
VSS_154
VSS_155
VSS_156
VSS_157
VSS_158
VSS_159
VSS_160
VSS_161
VSS_162
VSS_163
VSS_164
VSS_165
VSS_166
VSS_167
VSS_168
VSS_169
VSS_170
VSS_171
VSS_172
VSS_173
VSS_174
VSS_175
VSS_176
VSS_177
VSS_178
VSS_179
VSS_180
VSS_181
VSS_182
VSS_183
VSS_184
VSS_185
VSS_186
VSS_187
VSS_188
VSS_189
VSS_190
VSS_191
VSS_192
VSS_193
VSS_194
VSS_195
VSS_196
VSS_197
VSS_198
AW24
AW29
AW32
AW5
AW7
AY10
AY24
AY37
AY42
AY43
AY45
AY47
AY50
B10
B20
B24
B29
B30
B35
B38
B43
B46
B5
B8
BA1
BA17
BA18
BA2
BA24
BB12
BB25
BB40
BB44
BB49
BB8
BC16
BC24
BC25
BC36
BC40
BC51
BD13
BD2
BD28
BD45
BD48
BD5
BE1
BE19
BE23
BE30
BE42
BE51
BE8
BF12
BF16
BF36
BG19
BG2
BG24
BG29
BG39
BG48
BG5
BG51
BH17
BH30
BH44
BH46
BH8
BJ11
BJ13
BJ38
BJ4
BJ42
BJ46
BK15
BK17
BK25
BK29
BK36
BK40
BK44
BK6
BK8
BL11
BL13
BL19
BL22
BL37
BL47
C12
C16
C19
C28
C29
C33
C36
C41
4
U37J
C46
VSS_199
C50
VSS_200
C7
VSS_201
D13
VSS_202
D24
VSS_203
D3
VSS_204
D32
VSS_205
D39
VSS_206
D45
VSS_207
D49
VSS_208
E10
VSS_209
E16
VSS_210
E24
VSS_211
E28
VSS_212
E32
VSS_213
E47
VSS_214
F19
VSS_215
F36
VSS_216
F4
VSS_217
F40
VSS_218
F50
VSS_219
G1
VSS_220
G13
VSS_221
G16
VSS_222
G19
VSS_223
G24
VSS_224
G28
VSS_225
G29
VSS_226
G33
VSS_227
G42
VSS_228
G45
VSS_229
G48
VSS_230
G8
VSS_231
H24
VSS_232
H28
VSS_233
H4
VSS_234
H45
VSS_235
J11
VSS_236
J16
VSS_237
J2
VSS_238
J24
VSS_239
J28
VSS_240
J33
VSS_241
J35
VSS_242
J39
VSS_243
K12
VSS_245
K47
VSS_246
K8
VSS_247
L1
VSS_248
L17
VSS_249
L20
VSS_250
L24
VSS_251
L28
VSS_252
L3
VSS_253
L33
VSS_254
L49
VSS_255
M28
VSS_256
M42
VSS_257
M46
VSS_258
M49
VSS_259
M5
VSS_260
M50
VSS_261
M9
VSS_262
N11
VSS_263
N14
VSS_264
N17
VSS_265
N29
VSS_266
N32
VSS_267
N36
VSS_268
N39
VSS_269
N44
VSS_270
N49
VSS_271
N7
VSS_272
P19
VSS_273
P2
VSS_274
P23
VSS_275
P3
VSS_276
P50
VSS_277
R49
VSS_278
T39
VSS_279
T43
VSS_280
T47
VSS_281
U41
VSS_282
U45
VSS_283
U50
VSS_284
V2
VSS_285
V3
VSS_286
CRESTLINE_1p0
PM@
VSS
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SE CRET INFOR MATI ON. THIS SHEET MAY NOT BE TRANSF ERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
W11
VSS_287
W39
VSS_288
W43
VSS_289
W47
VSS_290
W5
VSS_291
W7
VSS_292
Y13
VSS_293
Y2
VSS_294
Y41
VSS_295
Y45
VSS_296
Y49
VSS_297
Y5
VSS_298
Y50
VSS_299
Y11
VSS_300
P29
VSS_301
T29
VSS_302
T31
VSS_303
T33
VSS_304
R28
VSS_305
AA32
VSS_306
AB32
VSS_307
AD32
VSS_308
AF28
VSS_309
AF29
VSS_310
AT27
VSS_311
AV25
VSS_312
H50
VSS_313
2006/08/18 2007/8/18
3
Compal Secret Data
Deciphered Date
2
Title
Size Document Number Rev
B
2
Date: Sheet
Compal Electronics, Inc.
Crestline (7/7)-GND
IFTXX M/B LA-3541P Schematic
1
0
13 52Wednesday, November 01, 2006
1
of
5
4
3
2
1
+1.8V +1.8V
JP35
+DIMM_VREF
DDRA_SDQ0
DDRA_SDQ1
1
C509
0.1U_0402_16V4Z
2
DDRA_SDQS0#
DDRA_SDQS0
DDRA_SDQ2
DDRA_SDQ3
DDRA_SDQ8
DDRA_SDQ9
DDRA_SDQS1#
DDRA_SDQS1
DDRA_SDQ10
DDRA_SDQ11
DDRA_SDQ16
DDRA_SDQ17
DDRA_SDQS2#
DDRA_SDQS2
DDRA_SDQ18
DDRA_SDQ19
DDRA_SDQ24
DDRA_SDQ25
DDRA_SDM3
EC_TX_P80_DATA
DDRA_SDQ26
DDRA_SDQ27
DDRA_CKE0
EC_RX_P80_CLK
DDRA_SBS2
DDRA_SMA12
DDRA_SMA9
DDRA_SMA8
DDRA_SMA5
DDRA_SMA3
DDRA_SMA1
DDRA_SMA10
DDRA_SBS0
DDRA_SWE#
DDRA_SCAS#
DDRA_SCS1#
DDRA_ODT1
DDRA_SDQ32
DDRA_SDQ33
DDRA_SDQS4#
DDRA_SDQS4
DDRA_SDQ34
DDRA_SDQ35
DDRA_SDQ40
DDRA_SDQ41
DDRA_SDM5
DDRA_SDQ42
DDRA_SDQ43
DDRA_SDQ48
DDRA_SDQ49
EC_RX_P80_CLK_R
DDRA_SDQS6#
DDRA_SDQS6
DDRA_SDQ50
DDRA_SDQ51
DDRA_SDQ56
DDRA_SDQ57
DDRA_SDM7
DDRA_SDQ58
DDRA_SDQ59
D_CK_SDATA
D_CK_SCLK
+3VS
1
2
DIMM0 STD H:5.2mm (BOT)
DDRA_SDQS0#<9>
DDRA_SDQS0<9>
D D
DDRA_SDQS1#<9>
DDRA_SDQS1<9>
DDRA_SDQS2#<9>
DDRA_SDQS2<9>
EC_TX_P80_DATA<15,34>
C C
EC_RX_P80_CLK<15,34>
B B
EC_RX_P80_CLK
A A
DDRA_CKE0<8>
DDRA_SBS2<9>
DDRA_SBS0<9>
DDRA_SWE#<9>
DDRA_SCAS#<9>
DDRA_SCS1#<8>
DDRA_ODT1<8>
DDRA_SDQS4#<9>
DDRA_SDQS4<9>
R622 0_0402_5%
1 2
EC_RX_P80_CLK_R<15>
DDRA_SDQS6#<9>
DDRA_SDQS6<9>
D_CK_SDATA<15,16>
D_CK_SCLK<15,16>
+3VS
C508
2.2U_0805_10V6K
5
1
VREF
3
VSS
5
DQ0
7
DQ1
9
VSS
11
DQS0#
13
DQS0
15
VSS
17
DQ2
19
DQ3
21
VSS
23
DQ8
25
DQ9
27
VSS
29
DQS1#
31
DQS1
33
VSS
35
DQ10
37
DQ11
39
VSS
41
VSS
43
DQ16
45
DQ17
47
VSS
49
DQS2#
51
DQS2
53
VSS
55
DQ18
57
DQ19
59
VSS
61
DQ24
63
DQ25
65
VSS
67
DM3
69
NC
71
VSS
73
DQ26
75
DQ27
77
VSS
79
CKE0
81
VDD
83
NC
85
BA2
87
VDD
89
A12
91
A9
93
A8
95
VDD
97
A5
99
A3
101
A1
103
VDD
105
A10/AP
107
BA0
109
WE#
111
VDD
113
CAS#
115
NC/S1#
117
VDD
119
NC/ODT1
121
VSS
123
DQ32
125
DQ33
127
VSS
129
DQS4#
131
DQS4
133
VSS
135
DQ34
137
DQ35
139
VSS
141
DQ40
143
DQ41
145
VSS
147
DM5
149
VSS
151
DQ42
153
DQ43
155
VSS
157
DQ48
159
DQ49
161
VSS
163
NC,TEST
165
VSS
167
DQS6#
169
DQS6
171
VSS
173
DQ50
175
DQ51
177
VSS
179
DQ56
181
DQ57
183
VSS
185
DM7
187
VSS
189
DQ58
191
DQ59
193
VSS
195
SDA
197
SCL
199
VDDSPD
P-TWO_A5652C-A0G16
Change PCB F ootprint
DQ12
DQ13
CK0#
DQ14
DQ15
DQ20
DQ21
DQ22
DQ23
DQ28
DQ29
DQS3#
DQS3
DQ30
DQ31
NC/CKE1
NC/A15
NC/A14
RAS#
ODT0
NC/A13
DQ36
DQ37
DQ38
DQ39
DQ44
DQ45
DQS5#
DQS5
DQ46
DQ47
DQ52
DQ53
CK1#
DQ54
DQ55
DQ60
DQ61
DQS7#
DQS7
DQ62
DQ63
VSS
DQ4
DQ5
VSS
DM0
VSS
DQ6
DQ7
VSS
VSS
DM1
VSS
CK0
VSS
VSS
VSS
VSS
DM2
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDD
BA1
VDD
VDD
VSS
VSS
DM4
VSS
VSS
VSS
VSS
VSS
VSS
CK1
VSS
DM6
VSS
VSS
VSS
VSS
VSS
SAO
SA1
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
NC
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
A11
92
A7
94
A6
96
98
A4
100
A2
102
A0
104
106
108
110
S0#
112
114
116
118
120
NC
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
4
9/25 Change DIMM0 to SP070004Z00 (HBL50)
DDRA_SDQ4
DDRA_SDQ5
DDRA_SDM0
DDRA_SDQ6
DDRA_SDQ7
DDRA_SDQ12
DDRA_SDQ13
DDRA_SDM1
DDRA_SDQ14
DDRA_SDQ15
DDRA_SDQ20
DDRA_SDQ21
DDRA_SDM2
DDRA_SDQ22
DDRA_SDQ23
DDRA_SDQ28
DDRA_SDQ29
DDRA_SDQS3#
DDRA_SDQS3
DDRA_SDQ30
DDRA_SDQ31
DDRA_CKE1
DDRA_SMA14
DDRA_SMA11
DDRA_SMA7
DDRA_SMA6
DDRA_SMA4
DDRA_SMA2
DDRA_SMA0
DDRA_SBS1
DDRA_SRAS#
DDRA_SCS0#
DDRA_ODT0
DDRA_SMA13
DDRA_SDQ36
DDRA_SDQ37
DDRA_SDM4
DDRA_SDQ38
DDRA_SDQ39
DDRA_SDQ44
DDRA_SDQ45
DDRA_SDQS5#
DDRA_SDQS5
DDRA_SDQ46
DDRA_SDQ47
DDRA_SDQ52
DDRA_SDQ53
DDRA_SDM6
DDRA_SDQ54
DDRA_SDQ55
DDRA_SDQ60
DDRA_SDQ61
DDRA_SDQS7#
DDRA_SDQS7
DDRA_SDQ62
DDRA_SDQ63
R469 10K_0402_5%
1 2
R470 10K_0402_5%
1 2
DDRA_CLK0 <8>
DDRA_CLK0# <8>
R468 0_0402_5%
1 2
DDRA_SDQS3# <9>
DDRA_SDQS3 <9>
DDRA_CKE1 <8>
DDRA_SBS1 <9>
DDRA_SRAS# <9>
DDRA_SCS0# <8>
DDRA_ODT0 <8>
DDRA_SDQS5# <9>
DDRA_SDQS5 <9>
DDRA_CLK1 <8>
DDRA_CLK1# <8>
DDRA_SDQS7# <9>
DDRA_SDQS7 <9>
PM_EXTTS#0 <8>
DDRA_SMA14<8>
DDRB_SMA14<8,15>
Security Classification
Issued Date
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
+DIMM_VREF
1
2
95.10.5 modify
2006/08/18 2007/8/18
3
20mils
C483
0.1U_0402_16V4Z
DDRA_SMA[0..13]<9>
DDRA_SDQ[0..63]<9>
DDRA_SDM[0..7]<9>
DDRA_CKE0
DDRA_SBS2
DDRA_SMA12
DDRA_SMA9
DDRA_SMA8
DDRA_SMA5
DDRA_SMA3
DDRA_SMA1
DDRA_SMA10
DDRA_SBS0
DDRA_SWE#
DDRA_SCAS#
DDRA_SCS1#
DDRA_ODT1
DDRA_SMA11
DDRA_SMA14
DDRA_SMA6
DDRA_SMA7
DDRA_SMA2
DDRA_SMA4
DDRA_SBS1
DDRA_SMA0
DDRA_SCS0#
DDRA_SRAS#
DDRA_SMA13
DDRA_ODT0
DDRB_SMA14
DDRA_CKE1
1
C484
2.2U_0805_10V6K
2
DDRA_SMA[0..13]
DDRA_SDQ[0..63]
DDRA_SDM[0..7]
1 4
2 3
RP39 56_0404_4P2R_5%
1 4
2 3
RP40 56_0404_4P2R_5%
RP41 56_0404_4P2R_5%
RP42 56_0404_4P2R_5%
RP43 56_0404_4P2R_5%
RP44 56_0404_4P2R_5%
RP45 56_0404_4P2R_5%
RP46 56_0404_4P2R_5%
RP47 56_0404_4P2R_5%
RP48 56_0404_4P2R_5%
RP49 56_0404_4P2R_5%
RP50 56_0404_4P2R_5%
RP51 56_0404_4P2R_5%
R748 56_0402_5%
R749 56_0402_5%
Layout Note:
Place these resistor
closely JP35,all
trace length Max=1.5"
1 4
2 3
1 4
2 3
1 4
2 3
1 4
2 3
1 4
2 3
1 4
2 3
1 4
2 3
1 4
2 3
1 4
2 3
1 4
2 3
1 4
2 3
1 2
1 2
Compal Secret Data
Deciphered Date
R465
1K_0402_1%
R466
1K_0402_1%
+0.9VS
+1.8V
12
Layout Note:
Place near JP35
+DIMM_VREF
1
C487
2.2U_0805_10V6K
2
1
C492
0.1U_0402_16V4Z
2
1
C496
0.1U_0402_16V4Z
2
1
C501
0.1U_0402_16V4Z
2
1
C506
0.1U_0402_16V4Z
2
Date: Sheet
1
Title
Size Document Number Rev
B
C488
2.2U_0805_10V6K
2
1
C493
0.1U_0402_16V4Z
2
1
C497
0.1U_0402_16V4Z
2
1
C502
0.1U_0402_16V4Z
2
1
C507
0.1U_0402_16V4Z
2
IFTXX M/B LA-3541P Schematic
1
C489
2.2U_0805_10V6K
2
1
C494
0.1U_0402_16V4Z
2
1
C498
0.1U_0402_16V4Z
2
1
C503
0.1U_0402_16V4Z
2
Compal Electronics, Inc.
DDRII-SODIMM0
1
1
C490
2.2U_0805_10V6K
2
1
C499
0.1U_0402_16V4Z
2
1
C504
0.1U_0402_16V4Z
2
14 52Wednesday, November 01, 2006
0
of
12
1
C485
220P_0402_50V7K
2
@
+1.8V
1
C486
2.2U_0805_10V6K
2
+1.8V
1
C491
0.1U_0402_16V4Z
2
+0.9VS
1
C495
0.1U_0402_16V4Z
2
+0.9VS
1
C500
0.1U_0402_16V4Z
2
+0.9VS
1
C505
0.1U_0402_16V4Z
2
Layout Note:
Place one cap close to every 2 pullup
resistors terminated to +0.9VS
2
A
B
C
D
E
9/25 Change DIMM1 to SP070006F00
DQ4
DQ5
DM0
DQ6
DQ7
DQ12
DQ13
DM1
CK0#
DQ14
DQ15
DQ20
DQ21
DM2
DQ22
DQ23
DQ28
DQ29
DQS3
DQ30
DQ31
VDD
VDD
VDD
VDD
RAS#
VDD
ODT0
VDD
DQ36
DQ37
DM4
DQ38
DQ39
DQ44
DQ45
DQS5
DQ46
DQ47
DQ52
DQ53
CK1#
DM6
DQ54
DQ55
DQ60
DQ61
DQS7
DQ62
DQ63
SAO
VSS
VSS
VSS
VSS
VSS
VSS
CK0
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
BA1
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
CK1
VSS
VSS
VSS
VSS
VSS
VSS
SA1
+1.8V+1.8V
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
NC
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
A11
92
A7
94
A6
96
98
A4
100
A2
102
A0
104
106
108
110
S0#
112
114
116
118
120
NC
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
B
DDRB_SDQ4
DDRB_SDQ5
DDRB_SDM0
DDRB_SDQ6
DDRB_SDQ7
DDRB_SDQ12
DDRB_SDQ13
DDRB_SDM1
DDRB_SDQ14
DDRB_SDQ15
DDRB_SDQ20
DDRB_SDQ21DDRB_SDQ17
DDRB_SDM2
DDRB_SDQ22
DDRB_SDQ23
DDRB_SDQ28
DDRB_SDQ29
DDRB_SDQS3#
DDRB_SDQS3
DDRB_SDQ31
DDRB_CKE1
DDRB_SMA14
DDRB_SMA11
DDRB_SMA7
DDRB_SMA6
DDRB_SMA4
DDRB_SMA2
DDRB_SMA0
DDRB_SBS1
DDRB_SRAS#
DDRB_SCS0#
DDRB_ODT0
DDRB_SMA13
DDRB_SDQ36
DDRB_SDQ37
DDRB_SDM4
DDRB_SDQ38
DDRB_SDQ39
DDRB_SDQ44
DDRB_SDQ45
DDRB_SDQS5#
DDRB_SDQS5
DDRB_SDQ46
DDRB_SDQ47
DDRB_SDQ52
DDRB_SDQ53
DDRB_SDM6
DDRB_SDQ54
DDRB_SDQ55
DDRB_SDQ60
DDRB_SDQ61DDRB_SDQ57
DDRB_SDQS7#
DDRB_SDQS7
DDRB_SDQ62
DDRB_SDQ63
R463 10K_0402_5%
1 2
R464 10K_0402_5%
1 2
R462
0_0402_5%
1 2
DDRB_SMA[0..13]<9>
DDRB_SDQ[0..63]<9>
DDRB_SDM[0..7]<9>
DDRB_CLK0 <8>
DDRB_CLK0# <8>
PM_EXTTS#1 <8>
DDRB_SDQS3# <9>
DDRB_SDQS3 <9>
DDRB_CKE1 <8>
DDRB_SMA14 <8,14>
DDRB_SBS1 <9>
DDRB_SRAS# <9>
DDRB_SCS0# <8>
DDRB_ODT0 <8>
DDRB_SDQS5# <9>
DDRB_SDQS5 <9>
DDRB_CLK1 <8>
DDRB_CLK1# <8>
DDRB_SDQS7# <9>
DDRB_SDQS7 <9>
+3VS
Security Classification
Issued Date
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
DDRB_CLK0?
DDRB_CLK1?
C
DDRB_CKE0
DDRB_SBS2
DDRB_SMA12
DDRB_SMA9
DDRB_SMA8
DDRB_SMA5
DDRB_SMA3
DDRB_SMA1
DDRB_SMA10
DDRB_SBS0
DDRB_SWE#
DDRB_SCAS#
DDRB_SCS1#
DDRB_ODT1
DDRB_SMA11
DDRB_CKE1
DDRB_SMA6
DDRB_SMA7
DDRB_SMA2
DDRB_SMA4
DDRB_SBS1
DDRB_SMA0
DDRB_SCS0#
DDRB_SRAS#
DDRB_SMA13
DDRB_ODT0
Layout Note:
Place these resistor
closely JP35,all
trace length Max=1.5"
2006/08/18 2007/8/18
Compal Secret Data
Deciphered Date
DDRB_SMA[0..13]
DDRB_SDQ[0..63]
DDRB_SDM[0..7]
1 4
2 3
RP25 56_0404_4P2R_5%
1 4
2 3
RP26 56_0404_4P2R_5%
RP27 56_0404_4P2R_5%
RP28 56_0404_4P2R_5%
RP29 56_0404_4P2R_5%
RP30 56_0404_4P2R_5%
RP31 56_0404_4P2R_5%
RP32 56_0404_4P2R_5%
RP33 56_0404_4P2R_5%
RP34 56_0404_4P2R_5%
RP35 56_0404_4P2R_5%
RP36 56_0404_4P2R_5%
RP37 56_0404_4P2R_5%
1 4
2 3
1 4
2 3
1 4
2 3
1 4
2 3
1 4
2 3
1 4
2 3
1 4
2 3
1 4
2 3
1 4
2 3
1 4
2 3
1 4
2 3
+0.9VS
D
JP34
+DIMM_VREF
DDRB_SDQ0
DDRB_SDQ1
1 1
2 2
3 3
4 4
EC_TX_P80_DATA<14,34>
EC_RX_P80_CLK<14,34>
EC_RX_P80_CLK_R<14>
DDRB_SDQS0#<9>
DDRB_SDQS0<9>
DDRB_SDQS1#<9>
DDRB_SDQS1<9>
DDRB_SDQS2#<9>
DDRB_SDQS2<9>
DDRB_CKE0<8>
DDRB_SBS2<9>
DDRB_SBS0<9>
DDRB_SWE#<9>
DDRB_SCAS#<9>
DDRB_SCS1#<8>
DDRB_ODT1<8>
DDRB_SDQS4#<9>
DDRB_SDQS4<9>
DDRB_SDQS6#<9>
DDRB_SDQS6<9>
D_CK_SDATA<14,16>
D_CK_SCLK<14,16>
DDRB_SDQS0#
DDRB_SDQS0
DDRB_SDQ2
DDRB_SDQ3
DDRB_SDQ8
DDRB_SDQ9
DDRB_SDQS1#
DDRB_SDQS1
DDRB_SDQ10
DDRB_SDQ11
DDRB_SDQ16
DDRB_SDQS2#
DDRB_SDQS2
DDRB_SDQ18
DDRB_SDQ19
DDRB_SDQ24
DDRB_SDQ25
DDRB_SDM3
EC_TX_P80_DATA
DDRB_SDQ26 DDRB_SDQ30
DDRB_SDQ27
DDRB_CKE0
EC_RX_P80_CLK
DDRB_SBS2
DDRB_SMA12
DDRB_SMA9
DDRB_SMA8
DDRB_SMA5
DDRB_SMA3
DDRB_SMA1
DDRB_SMA10
DDRB_SBS0
DDRB_SWE#
DDRB_SCAS#
DDRB_SCS1#
DDRB_ODT1
DDRB_SDQ32
DDRB_SDQ33
DDRB_SDQS4#
DDRB_SDQS4
DDRB_SDQ34
DDRB_SDQ35
DDRB_SDQ40
DDRB_SDQ41
DDRB_SDM5
DDRB_SDQ42
DDRB_SDQ43
DDRB_SDQ48
DDRB_SDQ49
EC_RX_P80_CLK_R
DDRB_SDQS6#
DDRB_SDQS6
DDRB_SDQ50
DDRB_SDQ51
DDRB_SDQ56
DDRB_SDM7
DDRB_SDQ58
DDRB_SDQ59
D_CK_SDATA
D_CK_SCLK
+3VS
1
VREF
3
VSS
5
DQ0
7
DQ1
9
VSS
11
DQS0#
13
DQS0
15
VSS
17
DQ2
19
DQ3
21
VSS
23
DQ8
25
DQ9
27
VSS
29
DQS1#
31
DQS1
33
VSS
35
DQ10
37
DQ11
39
VSS
41
VSS
43
DQ16
45
DQ17
47
VSS
49
DQS2#
51
DQS2
53
VSS
55
DQ18
57
DQ19
59
VSS
61
DQ24
63
DQ25
65
VSS
67
DM3
69
NC
71
VSS
73
DQ26
75
DQ27
77
VSS
79
CKE0
81
VDD
83
NC
85
BA2
87
VDD
89
A12
91
A9
93
A8
95
VDD
97
A5
99
A3
101
A1
103
VDD
105
A10/AP
107
BA0
109
WE#
111
VDD
113
CAS#
115
NC/S1#
117
VDD
119
NC/ODT1
121
VSS
123
DQ32
125
DQ33
127
VSS
129
DQS4#
131
DQS4
133
VSS
135
DQ34
137
DQ35
139
VSS
141
DQ40
143
DQ41
145
VSS
147
DM5
149
VSS
151
DQ42
153
DQ43
155
VSS
157
DQ48
159
DQ49
161
VSS
163
NC,TEST
165
VSS
167
DQS6#
169
DQS6
171
VSS
173
DQ50
175
DQ51
177
VSS
179
DQ56
181
DQ57
183
VSS
185
DM7
187
VSS
189
DQ58
191
DQ59
193
VSS
195
SDA
197
SCL
199
VDDSPD
P-TWO_A5692A-A0G16-N
DQS3#
NC/CKE1
NC/A15
NC/A14
NC/A13
DQS5#
DQS7#
DIMM1 STD H:9.2mm (BOT)
A
+DIMM_VREF
1
C455
2.2U_0805_10V6K
2
Layout Note:
Place near JP34
+1.8V
1
C461
C462
2.2U_0805_10V6K
2
2.2U_0805_10V6K
+1.8V
1
C466
C467
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z
+0.9VS
1
C471
C470
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z
+0.9VS
1
C475
C476
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z
+0.9VS
1
C481
C480
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z
Layout Note:
Place one cap close to every 2 pullup
resistors terminated to +0.9VS
Title
Size Document Number Rev
B
Date: Sheet
1
C456
2
0.1U_0402_16V4Z
1
1
1
C465
2.2U_0805_10V6K
2
1
2
1
C474
2
0.1U_0402_16V4Z
1
C479
0.1U_0402_16V4Z
2
1
2
1
2
1
2
2
1
2
1
2
1
2
1
2
C463
2.2U_0805_10V6K
2
1
C468
2
0.1U_0402_16V4Z
1
C472
2
0.1U_0402_16V4Z
1
C477
0.1U_0402_16V4Z
2
1
C482
0.1U_0402_16V4Z
2
C464
2.2U_0805_10V6K
C469
0.1U_0402_16V4Z
C473
0.1U_0402_16V4Z
C478
0.1U_0402_16V4Z
Compal Electronics, Inc.
DDRII-SODIMM1
IFTXX M/B LA-3541P Schematic
15 52Wednesday, November 01, 2006
E
0
of
5
PCI
SRC
CPU
CLKSEL1
1
1
FSLA
CLKSEL0
MHz
200
166
MHz
1000
100
MHz
33.30
33.3
FSLC1FSLB
CLKSEL2
0
FSB Frequency Selet:
D D
CPU Driven
(Default)
*
667MHz
800MHz
CPU_BSEL0<5>
C C
CPU_BSEL1<5>
B B
CPU_BSEL2<5>
C451 27P_0402_50V8J
A A
14.31818MHZ_16PF_DSX840GA
C452 27P_0402_50V8J
Routing the t race at least 10mil
FSC
Stuff
No Stuff
Stuff
No Stuff
Stuff
No Stuff
FSA
R402
2.2K_0402_5%
1 2
R406
0_0402_5%
FSB
1 2
R427
0_0402_5%
R442
2.2K_0402_5%
1 2
R444
0_0402_5%
Y2
R401 R408 R417 R430 R447R438
R401 R417 R447
R408 R430 R438
R408 R417 R447
R401 R430 R438
+1.05VS
R401
56_0402_5%
@
1 2
1 2
12
+1.05VS
+1.05VS
12
R403
1K_0402_5%
12
R408
1K_0402_5%
@
R417
1K_0402_5%
@
1 2
1 2
R424
1K_0402_5%
12
R430
0_0402_5%
@
R438
1K_0402_5%
@
1 2
1 2
R443
1K_0402_5%
12
R447
0_0402_5%
@
MCH_CLKSEL0 <8>
MCH_CLKSEL1 <8>
MCH_CLKSEL2 <8>
For ITP_EN, 0 =SRC8/SRC8#; 1 = ITP/ITP#
For 27_SEL, 0 = Enable DOT96 & SRC1,
For PCI2_EN, 0 = Overclocking of CPU and SRC Allowed
+3VS +3VS +3VS
12
5
CLK_XTAL_IN
CLK_XTAL_OUT
R456
10K_0402_5%
@
1 2
ITP_EN 27_SEL
R459
10K_0402_5%
1 2
SATA_CLKREQ#<22>
MCH_CLKREQ#<8>
CLK_PCI_PCM<26>
CLK_PCI_1394<28>
CLK_PCI_TPM<29>
CLK_PCI_EC<34>
CLK_PCI_SIO<41>
CLK_PCI_DB<36>
CLK_PCI_ICH<20>
CLK_ICH_48M<22>
CLK_14M_SIO<36,41>
CLK_ICH_14M<22>
1= Enable SRC0 & 27MHz
1 = Overclocking of CPU and SRC NOT allowed
+3VS
R397 0_1206_5%
R457
10K_0402_5%
PM@
1 2
R460
10K_0402_5%
GM@
1 2
4
1 2
+1.25VS
4
+3VM_CK505
1
C430
10U_0805_10V4Z
2
1 2
R400 0_1206_5%
+1.25VM_CK505
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
+1.25VM_CK505
R458
10K_0402_5%
1 2
PCI2_TME
R461
10K_0402_5%
@
1 2
+1.25VM_CK505
R412475_0402_1%
R413475_0402_1%
R41622_0402_5%
R41822_0402_5%
R41922_0402_5%
R42022_0402_5%
R42222_0402_5%
R42522_0402_5%
R42633_0402_5%
CLK_XTAL_IN
CLK_XTAL_OUT
R43633_0402_5%
R59722_0402_5%
R44122_0402_5%
1
2
1
C431
0.1U_0402_16V4Z
2
1
C437
10U_0805_10V4Z
2
+3VM_CK505
PCI_CLK0
PCI_CLK1
PCI2_TME
PCI_CLK3
27_SEL
ITP_EN
FSA
FSB
FSC
C443
0.1U_0402_16V4Z
3
1
C432
0.1U_0402_16V4Z
2
1
C438
0.1U_0402_16V4Z
2
10/17 : Change P/N from SA0001GT00 to SA00001GT10
1
C433
0.1U_0402_16V4Z
2
1
C439
0.1U_0402_16V4Z
2
1
C434
0.1U_0402_16V4Z
2
1
C440
0.1U_0402_16V4Z
2
1
C435
0.1U_0402_16V4Z
2
1
C441
0.1U_0402_16V4Z
2
2
1
C436
0.1U_0402_16V4Z
2
1
C442
0.1U_0402_16V4Z
2
Need to update Symbol
U35
2
VDD_PCI
9
VDD48
16
VDDPLL3
61
VDDREF
39
VDDSRC
55
VDDCPU
12
VDD96_IO
20
VDDPLL3_IO
26
VDDSRC_IO
36
VDDSRC_IO
49
VDDCPU_IO
1
PCI0/CR#_A
3
PCI1/CR#_B
4
PCI2/TME
5
PCI3
6
PCI4/27_Select
7
PCIF5/ITP_EN
60
X1
59
X2
10
USB_48MHZ/FSLA
57
FSLB/TEST MODE
62
REF0/FSLC/TEST_SEL
45
VDDSRC_IO
42
GNDSRC
8
GNDPCI
11
GND48
15
GND
19
GND
52
GNDCPU
23
GNDSRC
29
GNDSRC
58
GNDREF
* Internal Pull-Up Resistor
** Internal Pull-Down Resistor
Security Classification
Issued Date
THIS SHEET OF EN GINEE RING D RAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
CPU_STOP#
SRC11/CR#_H
SRC11#/CR#_G
SRC7/CR#_F
SRC7#/CR#_E
SRC3/CR#_C
SRC3#/CR#_D
SRC2#/SATA#
SRC1/SE1/27MHz_NonSS
SRC1#/SE2/27MHz_SS
SRC0/DOT96
SRC0/DOT96#
CK_PWRGD/PD#
ICS9LPRS365
2006/08/04 2006/10/06
SCLK
SDATA
PCI_STOP#
CPU0
CPU0#
CPU1_F
CPU1#_F
SRC8/ITP
SRC8#/ITP#
SRC10#
SRC10
SRC9
SRC9#
SRC6
SRC6#
SRC4
SRC4#
SRC2/SATA
48
NC
D_CK_SCLK
64
D_CK_SDATA
63
PM_STP_PCI#
38
PM_STP_CPU#
37
CLK_CPU_BCLK
54
CLK_CPU_BCLK#
53
CLK_MCH_BCLK
51
CLK_MCH_BCLK#
50
CLK_PCIE_EXP
47
CLK_PCIE_EXP#
46
CLK_PCIE_LAN#
35
CLK_PCIE_LAN
34
CLK_PCIE_NAND
33
CLK_PCIE_NAND#
32
CLK_PCIE_3G
30
CLK_PCIE_3G#
31
R_CLKREQ#_F
44
R_CLKREQ#_E
43
CLK_PCIE_WLAN
41
CLK_PCIE_WLAN#
40
CLK_MCH_3GPLL
27
CLK_MCH_3GPLL#
28
CLK_PCIE_ICH
24
CLK_PCIE_ICH#
25
CLK_PCIE_SATA
21
CLK_PCIE_SATA#
22
CLK_PCIE0
17
CLK_PCIE0#
18
R_CLK_DOT
13
R_CLK_DOT#
14
CK_PWRGD
56
R432 475_0402_1%
R433 475_0402_1%
R450 0_0402_5%GM@
R451 0_0402_5%GM@
R713 0_0402_5%@
R714 0_0402_5%@
R452 0_0402_5%GM@
R453 0_0402_5%GM@
R454 0_0402_5%PM@
R455 0_0402_5%PM@
ICS9LPRS365/SA00001GT00
Compal Secret Data
Deciphered Date
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
R431 10K_0402_5%
1 2
R434 10K_0402_5%
1 2
2
1
+3VS
R398
2.2K_0402_5%
D
S
+3VS
1 3
2
2
1 3
D
Q39
2N7002_SOT23
G
G
S
Q40
2N7002_SOT23
C444
C445
C446
C447
C448
C449
C450
ICH_SMBDATA<22,32,33>
ICH_SMBCLK<22,32,33>
D_CK_SCLK <14,15>
D_CK_SDATA <14,15>
PM_STP_PCI# <22>
PM_STP_CPU# <22>
CLK_CPU_BCLK <4>
CLK_CPU_BCLK# <4>
CLK_MCH_BCLK <7>
CLK_MCH_BCLK# <7>
CLK_PCIE_EXP <33>
CLK_PCIE_EXP# <33>
CLK_PCIE_LAN# <30>
CLK_PCIE_LAN <30>
CLK_PCIE_NAND <32>
CLK_PCIE_NAND# <32>
CLK_PCIE_3G <32>
CLK_PCIE_3G# <32>
EXP_CLKREQ# <33>
WLAN_CLKREQ# <32>
CLK_PCIE_WLAN <32>
CLK_PCIE_WLAN# <32>
CLK_MCH_3GPLL <8>
CLK_MCH_3GPLL# <8>
CLK_PCIE_ICH <22>
CLK_PCIE_ICH# <22>
CLK_PCIE_SATA <21>
CLK_PCIE_SATA# <21>
CLK_DREF_SSC <8>
CLK_DREF_SSC# <8>
CLK_27M_VGA <17>
CLK_27M_VGA# <17>
CLK_DREF_96M <8>
CLK_DREF_96M# <8>
CLK_PCIE_VGA <17>
CLK_PCIE_VGA# <17>
CK_PWRGD <22>
+3VS
+3VS
Place close to U35
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
Clock generator
IXXXX LA-3XXXP
1
R399
2.2K_0402_5%
D_CK_SDATA
D_CK_SCLK
CLK_ICH_48M
12
5P_0402_50V8C@
CLK_ICH_14M
12
4.7P_0402_50V8C@
CLK_PCI_ICH
12
4.7P_0402_50V8C@
CLK_14M_SIO
12
4.7P_0402_50V8C@
CLK_PCI_PCM
12
4.7P_0402_50V8C@
CLK_PCI_EC
12
4.7P_0402_50V8C@
CLK_PCI_SIO
12
4.7P_0402_50V8C@
16 52Wednesday, November 01, 2006
0.1
of
5
4
3
2
1
PCIE_MTX_C_GRX_N[0..15]<10>
PCIE_MTX_C_GRX_P[0..15]<10>
PCIE_GTX_C_MRX_N[0..15]<10>
PCIE_GTX_C_MRX_P[0..15]<10>
D D
B+ +1.8VS
PCIE_GTX_C_MRX_N15
PCIE_GTX_C_MRX_P15
PCIE_GTX_C_MRX_N14
PCIE_GTX_C_MRX_P14
C C
B B
PCIE_GTX_C_MRX_N13
PCIE_GTX_C_MRX_P13
PCIE_GTX_C_MRX_N12
PCIE_GTX_C_MRX_P12
PCIE_GTX_C_MRX_N11
PCIE_GTX_C_MRX_P11
PCIE_GTX_C_MRX_N10
PCIE_GTX_C_MRX_P10
PCIE_GTX_C_MRX_N9
PCIE_GTX_C_MRX_P9
PCIE_GTX_C_MRX_N8
PCIE_GTX_C_MRX_P8
PCIE_GTX_C_MRX_N7
PCIE_GTX_C_MRX_P7
PCIE_GTX_C_MRX_N6
PCIE_GTX_C_MRX_P6
PCIE_GTX_C_MRX_N5
PCIE_GTX_C_MRX_P5
PCIE_GTX_C_MRX_N4
PCIE_GTX_C_MRX_P4
PCIE_GTX_C_MRX_N3
PCIE_GTX_C_MRX_P3
PCIE_GTX_C_MRX_N2
PCIE_GTX_C_MRX_P2
PCIE_MTX_C_GRX_N[0..15]
PCIE_MTX_C_GRX_P[0..15]
PCIE_GTX_C_MRX_N[0..15]
PCIE_GTX_C_MRX_P[0..15]
JP33A
1
PWR_SRC
3
PWR_SRC
5
PWR_SRC
7
PWR_SRC
9
PWR_SRC
11
PWR_SRC
13
PWR_SRC
15
PWR_SRC
17
GND
19
GND
21
GND
23
GND
25
PEX_RX15#
27
PEX_RX15
29
GND
31
PEX_RX14#
33
PEX_RX14
35
GND
37
PEX_RX13#
39
PEX_RX13
41
GND
43
PEX_RX12#
45
PEX_RX12
47
GND
49
PEX_RX11#
51
PEX_RX11
53
GND
55
PEX_RX10#
57
PEX_RX10
59
GND
61
PEX_RX9#
63
PEX_RX9
65
GND
67
PEX_RX8#
69
PEX_RX8
71
GND
73
PEX_RX7#
75
PEX_RX7
77
GND
79
PEX_RX6#
81
PEX_RX6
83
GND
85
PEX_RX5#
87
PEX_RX5
89
GND
91
PEX_RX4#
93
PEX_RX4
95
GND
97
PEX_RX3#
99
PEX_RX3
101
GND
103
PEX_RX2#
105
PEX_RX2
107
GND
ACES_88990-2D08
1V8RUN
1V8RUN
1V8RUN
1V8RUN
1V8RUN
1V8RUN
1V8RUN
RUNPWROK
5VRUN
GND
GND
GND
PRSNT2#
PEX_TX15#
PEX_TX15
GND
PEX_TX14#
PEX_TX14
GND
PEX_TX13#
PEX_TX13
GND
PEX_TX12#
PEX_TX12
GND
PEX_TX11#
PEX_TX11
GND
PEX_TX10#
PEX_TX10
GND
PEX_TX9#
PEX_TX9
GND
PEX_TX8#
PEX_TX8
GND
PEX_TX7#
PEX_TX7
GND
PEX_TX6#
PEX_TX6
GND
PEX_TX5#
PEX_TX5
GND
PEX_TX4#
PEX_TX4
GND
PEX_TX3#
PEX_TX3
GND
PEX_TX2#
PEX_TX2
9/13 modify this footprint from ACES_88990-2D08_230P to ACES_88990-2D28_230P
JP33B
PCIE_GTX_C_MRX_N1
PCIE_GTX_C_MRX_P1
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
SUSP# <28,33,34,41,43,48,49,50>
+5VS
PCIE_MTX_C_GRX_N15
PCIE_MTX_C_GRX_P15
PCIE_MTX_C_GRX_N14
PCIE_MTX_C_GRX_P14
PCIE_MTX_C_GRX_N13
PCIE_MTX_C_GRX_P13
PCIE_MTX_C_GRX_N12
PCIE_MTX_C_GRX_P12
PCIE_MTX_C_GRX_N11
PCIE_MTX_C_GRX_P11
PCIE_MTX_C_GRX_N10
PCIE_MTX_C_GRX_P10
PCIE_MTX_C_GRX_N9
PCIE_MTX_C_GRX_P9
PCIE_MTX_C_GRX_N8
PCIE_MTX_C_GRX_P8
PCIE_MTX_C_GRX_N7
PCIE_MTX_C_GRX_P7
PCIE_MTX_C_GRX_N6
PCIE_MTX_C_GRX_P6
PCIE_MTX_C_GRX_N5
PCIE_MTX_C_GRX_P5
PCIE_MTX_C_GRX_N4
PCIE_MTX_C_GRX_P4
PCIE_MTX_C_GRX_N3
PCIE_MTX_C_GRX_P3
PCIE_MTX_C_GRX_N2
PCIE_MTX_C_GRX_P2
CLK_PCIE_VGA#<16>
CLK_PCIE_VGA<16>
PLT_RST_BUF#<20,32>
EC_SMB_DA2<4,34>
EC_SMB_CK2<4,34>
VGA_CRT_HSYNC< 19>
VGA_CRT_VSYNC<19>
VGA_DDC_CLK<19>
VGA_DDC_DATA<19>
CLK_27M_VGA#<16>
CLK_27M_VGA<16>
PCIE_GTX_C_MRX_N0
PCIE_GTX_C_MRX_P0
CLK_PCIE_VGA#
CLK_PCIE_VGA
VGA_CRT_VSYNC
VGA_DDC_CLK
VGA_DDC_DATA
CLK_27M_VGA#
CLK_27M_VGA
109
PEX_RX1#
111
PEX_RX1
113
GND
115
PEX_RX0#
117
PEX_RX0
119
GND
121
PEX_REFCLK#
123
PEX_REFCLK
125
CLK_REQ#
127
PEX_RST#
129
RSVD
131
RSVD
133
SMB_DAT
135
SMB_CLK
137
THERM#
139
VGA_HSYNC
141
VGA_VSYNC
143
DDCA_CLK
145
DDCA_DAT
147
IGP_UCLK#
149
IGP_UCLK
151
GND
153
RSVD
155
RSVD
157
RSVD
159
IGP_UTX2#
161
IGP_UTX2
163
GND
165
IGP_UTX1#
167
IGP_UTX1
169
GND
171
IGP_UTX0#
173
IGP_UTX0
175
GND
177
IGP_LCLK#/DVI_B_CLK#
179
IGP_LCLK/DVI_B_CLK
181
DVI_B_HPD/GND
183
RSVD
185
RSVD
187
GND
189
IGP_LTX2#/DVI_B_TX2#
191
IGP_LTX2/DVI_B_TX2
193
GND
195
IGP_LTX1#/DVI_B_TX1#
197
IGP_LTX1/DVI_B_TX1
199
GND
201
IGP_LTX0#/DVI_B_TX0#
203
IGP_LTX0/DVI_B_TX0
205
DVI_A_HPD
207
DVI_A_CLK#
209
DVI_A_CLK
211
GND
213
DVI_A_TX2#
215
DVI_A_TX2
217
GND
219
DVI_A_TX1#
221
DVI_A_TX1
223
GND
225
DVI_A_TX0#
227
DVI_A_TX0
229
GND
ACES_88990-2D08
GND
PEX_TX1#
PEX_TX1
GND
PEX_TX0#
PEX_TX0
PRSNT1#
TV_C/HDTV_Pr
GND
TV_Y/HDTV_Y
TV_CVBS/HDTV_Pb
GND
GND
VGA_RED
GND
VGA_GRN
GND
VGA_BLU
GND
LVDS_UCLK#
LVDS_UCLK
GND
LVDS_UTX3#
LVDS_UTX3
GND
LVDS_UTX2#
LVDS_UTX2
GND
LVDS_UTX1#
LVDS_UTX1
GND
LVDS_UTX0#
LVDS_UTX0
GND
LVDS_LCLK#
LVDS_LCLK
GND
LVDS_LTX3#
LVDS_LTX3
GND
LVDS_LTX2#
LVDS_LTX2
GND
LVDS_LTX1#
LVDS_LTX1
GND
LVDS_LTX0#
LVDS_LTX0
GND
DDCC_DAT
DDCC_CLK
LVDS_PPEN
LVDS_BL_BRGHT
LVDS_BLEN
DDCB_DAT
DDCB_CLK
2V5RUN
GND
3V3RUN
3V3RUN
3V3RUN
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204
206
208
210
212
214
216
218
220
222
224
226
228
230
PCIE_MTX_C_GRX_N1
PCIE_MTX_C_GRX_P1
PCIE_MTX_C_GRX_N0
PCIE_MTX_C_GRX_P0
VGA_TV_CRMA
VGA_TV_LUMA
VGA_TV_COMPS
VGA_CRT_R
VGA_CRT_GVGA_CRT_HSYNC
VGA_CRT_B
TXCLK-
TXCLK+
TXOUT2TXOUT2+
TXOUT1TXOUT1+
TXOUT0TXOUT0+
TZCLKTZCLK+
TZOUT2TZOUT2+
TZOUT1TZOUT1+
TZOUT0TZOUT0+
I2CC_SDA
I2CC_SCL
ENVDD
VGA_ENBKL
+2.5VS
+3VS
VGA_TV_CRMA <19>
VGA_TV_LUMA <19>
VGA_TV_COMPS <19>
VGA_CRT_R <19>
VGA_CRT_G <19>
VGA_CRT_B <19>
TXCLK- <18>
TXCLK+ <18>
TXOUT2- <18>
TXOUT2+ <18>
TXOUT1- <18>
TXOUT1+ <18>
TXOUT0- <18>
TXOUT0+ <18>
TZCLK- <18>
TZCLK+ <18>
TZOUT2- <18>
TZOUT2+ <18>
TZOUT1- <18>
TZOUT1+ <18>
TZOUT0- <18>
TZOUT0+ <18>
I2CC_SDA <18>
I2CC_SCL <18>
ENVDD <18>
VGA_ENBKL <18>
+1.8VS +3VS +2.5VS +5VSB+
2
C423
0.1U_0603_25V7K
PM@
A A
1
4.7U_0805_10V4Z
5
C424
PM@
1
2
1
C425
0.1U_0402_16V4Z
2
PM@
4.7U_0805_10V4Z
C426
PM@
1
2
4
1
C427
0.1U_0402_16V4Z
2
PM@
1
C428
0.1U_0402_16V4Z
2
PM@
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SE CRET INFOR MATI ON. THIS SHEET MAY NOT BE TRANSF ERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
1
C429
0.1U_0402_16V4Z
2
PM@
2006/08/18 2007/8/18
3
Compal Secret Data
Deciphered Date
2
Title
Size Document Number Rev
Custom
Date: Sheet
Compal Electronics, Inc.
MXM Connector
IFTXX M/B LA-3541P Schematic
17 52Wednesday, November 01, 2006
1
of
0
5
4
3
2
1
LCD POWER CIRCUIT
+3VS
W=60mils
1
C410
4.7U_0805_10V4Z
112
3
5
7
9910
111112
13
15
17
19
21
23
25
27
29
GND1
GND2
+LCDVDD
4
6
8
14
16
18
20
22
24
26
28
30
2
1
C413
0.1U_0402_16V4Z
2
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
G
2
1 3
1
4.7U_0805_10V4Z
2
13
15
17
19
21
23
25
27
29
31
32
S
Q37
SI2301BDS_SOT23
D
C412
JP31
3
5
7
ACES_88242-3001
ME@
Follow HEL80's pin definition
W=60mils
TZOUT0TZOUT0+
TZOUT1-TXOUT1TZOUT1+
TZOUT2TZOUT2+
TZCLKTZCLK+
I2CC_SDA
I2CC_SCL
+3VS
TZOUT0- <17>
TZOUT0+ <17>
TZOUT1- <17>
TZOUT1+ <17>
TZOUT2- <17>
TZOUT2+ <17>
TZCLK- <17>
TZCLK+ <17>
I2CC_SDA <17>
I2CC_SCL <17>
R384
300_0603_5%
2
G
12
R389
+LCDVDD
+3VALW
12
R385
100K_0402_5%
Q38
2N7002_SOT23
TXOUT0-<17>
TXOUT0+<17>
TXOUT1-<17>
TXOUT1+<17>
TXOUT2-<17>
TXOUT2+<17>
TXCLK-<17>
TXCLK+<17>
12
(60 MIL)
+3VS
12
R386 1K_0402_5%
13
D
2
G
S
L55
FBMA-L11-201209-221LMA30T_0805
2
C411
0.047U_0402_16V7K
1
LCD/PANEL BD. Conn.
TXOUT0TXOUT0+
TXOUT1+
TXOUT2-
TXOUT2+
TXCLK-
TXCLK+
+LCDVDD_L
+LCDVDD
12
D D
13
D
Q36
2N7002_SOT23
R387 0_0402_5%
GMCH_ENVDD<10>
ENVDD<17>
C C
+3VS
1
C418
0.1U_0402_16V4Z
2
+LCDVDD_L
1
C419
10U_0805_10V4Z
2
1 2
R388 0_0402_5%
1 2
1
C420
0.1U_0402_16V4Z
2
S
GM@
PM@
100K_0402_5%
Except pin 29
B B
JEPICO Conn.
AD3_SMADID1<34>
AD2_SMADID0<34>
RDB_SMMRSB<34>
WRB_PWRSB<34>
A A
AD3_SMADID1
AD2_SMADID0
RDB_SMMRSB
WRB_PWRSB
JP50
1
1
2
2
3
3
4
4
5
GND1
6
GND2
ACES_88231-0400
ME@
Routing Diagram
MXMII Conn.
LVDS
LVDS Bus
Use Daisy chain to route
I2CC_SDA GMCH_LCD_DATA
TXOUT0+
TXOUT0TXOUT1+
TXOUT1TXOUT2+
TXOUT2TXCLK+
TXCLKTZOUT0+
TZOUT0TZOUT1+
TZOUT1TZOUT2+
TZOUT2TZCLK+
TZCLK-
1 4
2 3
RP12 0_0404_4P2R_5%GM@
1 4
2 3
RP13 0_0404_4P2R_5%GM@
1 4
2 3
RP14 0_0404_4P2R_5%GM@
1 4
2 3
RP15 0_0404_4P2R_5%GM@
1 4
2 3
RP16 0_0404_4P2R_5%GM@
1 4
2 3
RP17 0_0404_4P2R_5%GM@
1 4
2 3
RP18 0_0404_4P2R_5%GM@
1 4
2 3
RP19 0_0404_4P2R_5%GM@
1 4
2 3
RP20 0_0404_4P2R_5%GM@
GMCH_LCD_CLKI2CC_SCL
GMCH_TXOUT0+
GMCH_TXOUT0-
GMCH_TXOUT1+
GMCH_TXOUT1-
GMCH_TXOUT2+
GMCH_TXOUT2-
GMCH_TXCLK+
GMCH_TXCLK-
GMCH_TZOUT0+
GMCH_TZOUT0-
GMCH_TZOUT1+
GMCH_TZOUT1-
GMCH_TZOUT2+
GMCH_TZOUT2-
GMCH_TZCLK+
GMCH_TZCLK-
INVERTER Conn.
JP37
1
INVT_PWM<34>
DAC_BRIG<34>
+INVPWR_B+
0.1U_0603_50V4Z
GMCH_ENBKL<10>
VGA_ENBKL<17>
C421
DISPOFF#
BKOFF#<34>
+INVPWR_B+
L37
KC FBM-L11-201209-221LMAT_0805
L38
KC FBM-L11-201209-221LMAT_0805
1
C422
68P_0402_50V8K
2
@
BKOFF# DISPOFF#
2
3
4
5
6
7
MOLEX_53780-0790
ME@
D38
RB751V_SOD323
21
R610 0_0402_5%GM@
R611 0_0402_5%PM@
12
12
NBR
12
12
B+
GMCH_LCD_CLK <10>
GMCH_LCD_DATA <10>
GMCH_TXOUT0+ <10>
GMCH_TXOUT0- <10>
GMCH_TXOUT1+ <10>
GMCH_TXOUT1- <10>
GMCH_TXOUT2+ <10>
GMCH_TXOUT2- <10>
GMCH_TXCLK+ <10>
GMCH_TXCLK- <10>
GMCH_TZOUT0+ <10>
GMCH_TZOUT0- <10>
GMCH_TZOUT1+ <10>
GMCH_TZOUT1- <10>
GMCH_TZOUT2+ <10>
GMCH_TZOUT2- <10>
GMCH_TZCLK+ <10>
GMCH_TZCLK- <10>
DAC_BRIG
INVT_PWM
DISPOFF#
+3VS
12
R390
4.7K_0402_5%
R612
100K_0402_5%
1 2
1 2
C415 220P_0402_50V7K@
1 2
C416 220P_0402_50V7K@
1 2
C417 220P_0402_50V7K@
ENBKL
ENBKL <34>
Security Classification
Issued Date
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2006/08/18 2007/8/18
Compal Secret Data
Deciphered Date
Title
Size Document Number Rev
B
2
Date: Sheet
Compal Electronics, Inc.
LVDS & DVI Connector
IFTXX M/B LA-3541P Schematic
1
of
18 52Wednesday, November 01, 2006
0
A
B
C
D
E
2 1
2
+3VS
2
1 3
D
Q35
2N7002_SOT23
W=40mils
D31
1
C397
2
100P_0402_50V8J
1
D42
DAN217_SC59
@
3
G
S
2
G
1 3
D
F1
21
1.1A_6VDC_FUSE
C387
0.1U_0402_16V4Z
1
2
C399
68P_0402_50V8K
+3VS
12
R367
4.7K_0402_5%
R371 0_0402_5%GM@
R372 0_0402_5%GM@
S
R377
4.7K_0402_5%
1 2
+3VS
1
2
1
2
12
12
W=40mils
6
11
1
7
12
2
8
13
3
9
14
4
10
15
5
DSUB_12
DSUB_15
C402
68P_0402_50V8K
+CRT_VCC+R_CRT_VCC
JP29
16
17
SUYIN_7846S-15G2T-HI
ME@
VGA_DDC_DATA <17>
GMCH_CRT_DATA <10>
GMCH_CRT_CLK <10>
VGA_DDC_CLK <17>
CRT Connector
1 1
VGA_CRT_R<17>
GMCH_CRT_R<10>
VGA_CRT_G<17>
GMCH_CRT_G<10>
VGA_CRT_B<17>
GMCH_CRT_B<10>
2 2
1 2
R354 0_0402_5%GM@
1 2
R356 0_0402_5%GM@
1 2
R358 0_0402_5%GM@
Place closed to chipset
12
R359
150_0402_1%
VGA_CRT_HSYNC<17>
GMCH_CRT_HSYNC<10>
VGA_CRT_R
VGA_CRT_G CRT_G_1
VGA_CRT_B
12
12
R361
150_0402_1%
1 2
R364 0_0402_5%GM@
1
C389
C388
2
10P_0402_50V8J
10P_0402_50V8J
C398 0.1U_0402_16V4Z
VGA_CRT_HSYNC
1
2
1 2
C390
10P_0402_50V8J
R360
150_0402_1%
Place closed to chipset
VGA_CRT_VSYNC<17>
GMCH_CRT_VSYNC<10>
1 2
R366 0_0402_5%GM@
1 2
L26 FCM2012C-800_0805
1 2
L28 FCM2012C-800_0805
1 2
L30 FCM2012C-800_0805
1
2
+CRT_VCC
1
5
P
OE#
A2Y
G
SN74AHCT1G125DCKR_SC70-5
3
1 2
C403 0.1U_0402_16V4Z
VGA_CRT_ VSYNC
C391
22P_0402_50V8J
Update Footprint
U33
4
+CRT_VCC
CRT_R_1
CRT_B_1
1
C392
2
22P_0402_50V8J
5
1
U34
P
4
OE#
A2Y
G
SN74AHCT1G125DCKR_SC70-5
3
Update Footprint
1
1
C393
2
2
22P_0402_50V8J
R362 10K_0402_5%
1 2
R658 39_0402_1%
1 2
R659 39_0402_1%
1 2
L27 FCM2012C-800_0805
1 2
L29 FCM2012C-800_0805
1 2
L31 FCM2012C-800_0805
12
CRT_HSYNC_1
CRT_VSYNC_1
+3VS
C394
10P_0402_50V8J
D32
@
DAN217_SC59
1
2
D33
@
DAN217_SC59
1
2
3
1
C395
10P_0402_50V8J
2
1 2
L32 FCM1608C-121T_0603
1 2
L33 FCM1608C-121T_0603
Update Footprint
1
2
3
C409
6P_0402_50V8K
Update Footprint
D37
@
DAN217_SC59
1
2
3
TV_CRMA_1
TV_COMPS_1
TV_LUMA_1
1
2
JP30
3
6
7
5
2
4
1
8
9
SUYIN_030107FR007SX08FU
ME@
TV-OUT Conn.
3 3
VGA_TV_LUMA<17>
GMCH_TV_LUMA<10>
VGA_TV_CRMA<17>
GMCH_TV_CRMA<10>
VGA_TV_COMPS<17>
GMCH_TV_COMPS<10>
Place closed to chipset
1 2
R375 0_0402_5%GM@
1 2
R378 0_0402_5%GM@
1 2
R380 0_0402_5%GM@
12
R381
150_0402_1%
150_0402_1%
12
R382
150_0402_1%
VGA_TV_LUMA
VGA_TV_CRMA
VGA_TV_COMPS
12
R383
C404
6P_0402_50V8K
1
C405
2
6P_0402_50V8K
1
C406
2
6P_0402_50V8K
L34 FCM1608C-121T_0603
L35 FCM1608C-121T_0603
L36 FCM1608C-121T_0603
1
2
+3VS
1 2
1 2
1 2
C407
6P_0402_50V8K
D35
@
DAN217_SC59
1
2
1
2
3
C408
6P_0402_50V8K
D36
@
DAN217_SC59
1
2
1
2
3
10P_0402_50V8J
+3VS
4.7K_0402_5%
DSUB_12
DSUB_15
D34
@
DAN217_SC59
1
2
3
CRT_R_2
CRT_G_2
CRT_B_2
1
C396
10P_0402_50V8J
2
CRT_HSYNC_2
CRT_VSYNC_2
1
C400
2
DAN217_SC59
+CRT_VCC
R368
D43
@
12
+5VS
RB411DT146_SOT23-3
Update Footprint
1
C401
10P_0402_50V8J
2
1
2
3
12
R369
4.7K_0402_5%
Q34
2N7002_SOT23
4 4
Security Classification
Issued Date
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
A
B
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2006/08/18 2007/8/18
Compal Secret Data
Deciphered Date
Title
Size Document Number Rev
B
D
Date: Sheet
Compal Electronics, Inc.
CRT & TV-OUT Connector
IFTXX M/B LA-3541P Schematic
E
of
19 52Wednesday, November 01, 2006
0
5
4
3
2
1
+3VS
10/17 : Change P/N from SA000010G00 to SA00001JU10
R326 8.2K_0402_5%
1 2
R327 8.2K_0402_5%
1 2
D D
C C
R328 8.2K_0402_5%
R329 8.2K_0402_5%
R330 8.2K_0402_5%
R331 8.2K_0402_5%
R332 8.2K_0402_5%
R333 8.2K_0402_5%
+3VS
R334 8.2K_0402_5%
R335 8.2K_0402_5%
R336 8.2K_0402_5%
R337 8.2K_0402_5%
R338 8.2K_0402_5%
R340 8.2K_0402_5%
R341 8.2K_0402_5%
R342 8.2K_0402_5%
R343 8.2K_0402_5%
R344 8.2K_0402_5%
R345 8.2K_0402_5%
R346 8.2K_0402_5%
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
PCI_DEVSEL#
PCI_STOP#
PCI_TRDY#
PCI_FRAME#
PCI_PLOCK#
PCI_IRDY#
PCI_SERR#
PCI_PERR#
PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#
PCI_PIRQE#
PCI_PIRQF#
PCI_PIRQG#
PCI_PIRQH#
PCI_REQ#0
PCI_REQ#1
PCI_REQ#2
PCI_REQ#3
PCI_AD[0..31]<26,28>
PCI_PIRQC#<26>
PCI_AD0
PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD6
PCI_AD7
PCI_AD8
PCI_AD9
PCI_AD10
PCI_AD11
PCI_AD12
PCI_AD13
PCI_AD14
PCI_AD15
PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20
PCI_AD21
PCI_AD22
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30
PCI_AD31
PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#
A16 Swap Override Strap
R347 1K_0402_5%
1 2
R348 1K_0402_5%
1 2
B B
R350 1K_0402_5%
1 2
@
@
@
PCI_GNT#3
PCI_GNT#0
PCI_GNT#3
Low= A16 swap override Enable
High= Default*
Boot BIOS Strap
PCI_GNT#0 SPI_CS#1 Boot BIOS Loaction
0
11
A A
1 SPI
01
PCI
LPC*
10/17 : FootPrint : SA000010G00
BOM : SA00001JU10
U30B
D20
AD0
E19
D19
A20
D17
A21
A19
C19
A18
B16
A12
E16
A14
G16
A15
C11
D11
B12
C12
D10
F13
E11
E13
E12
A10
B6
A9
C7
D8
A6
E8
D6
A3
F9
B5
C5
PCI
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
Interrupt I/F
PIRQA#
PIRQB#
PIRQC#
PIRQD#
ICH8M REV 1.0
REQ0#
GNT0#
REQ1#/GPIO50
GNT1#/GPIO51
REQ2#/GPIO52
GNT2#/GPIO53
REQ3#/GPIO54
GNT3#/GPIO55
C/BE0#
C/BE1#
C/BE2#
C/BE3#
IRDY#
PAR
PCIRST#
DEVSEL#
PERR#
PLOCK#
SERR#
STOP#
TRDY#
FRAME#
PLTRST#
PCICLK
PME#
PIRQE#/GPIO2
PIRQF#/GPIO3
PIRQG#/GPIO4
PIRQH#/GPIO5
PCI_REQ#0
A4
PCI_GNT#0
D7
PCI_REQ#1
E18
C18
PCI_REQ#2
B19
PCI_GNT#2
F18
PCI_REQ#3
A11
PCI_GNT#3
C10
PCI_CBE#0
C17
PCI_CBE#1
E15
PCI_CBE#2
F16
PCI_CBE#3
E17
PCI_IRDY#
C8
PCI_PAR
D9
PCIRST#
G6
PCI_DEVSEL#
D16
PCI_PERR#
A7
PCI_PLOCK#
B7
PCI_SERR#
F10
PCI_STOP#
C16
PCI_TRDY#
C9
PCI_FRAME#
A17
PLT_RST#
AG24
CLK_PCI_ICH
B10
PCI_PME#
G7
PCI_PIRQE#
F8
PCI_PIRQF#
G11
PCI_PIRQG#
F12
PCI_PIRQH#
B3
PLT_RST#
R616 0_0402_5%
Update Footprint
PCIRST#
R617 0_0402_5%
+3V_AND1
5
2
P
B
1
A
G
3
1 2
+3V_AND2
5
2
P
B
1
A
G
3
1 2
PCI_REQ#0 <28>
PCI_GNT#0 <28>
PCI_REQ#2 <26>
PCI_GNT#2 <26>
PCI_CBE#0 <26,28>
PCI_CBE#1 <26,28>
PCI_CBE#2 <26,28>
PCI_CBE#3 <26,28>
PCI_IRDY# <26,28>
PCI_PAR <26,28>
PCI_DEVSEL# <26,28>
PCI_PERR# <26,28>
PCI_PLOCK#
PCI_SERR# <26,28>
PCI_STOP# <26,28>
PCI_TRDY# <26,28>
PCI_FRAME# <26,28>
PLT_RST# <8,22,29,30,41>
CLK_PCI_ICH <16>
PCI_PME# <34>
PCI_PIRQG# <28>
PCI_PIRQH# <28>
U31
NC7SZ08P5X_NL_SC70-5
@
4
Y
U32
NC7SZ08P5X_NL_SC70-5
Y
12
R349
100K_0402_5%
@
@
4
12
R352
100K_0402_5%
@
1 2
R618 0_0402_5%
1 2
R619 0_0402_5%@
1 2
R620 0_0402_5%
1 2
R621 0_0402_5%@
Place closely pin B10
CLK_PCI_ICH
R339
10_0402_5%
@
1 2
1
C386
10P_0402_50V8J
+3VS
+3VALW
PLT_RST_BUF# <17,32>SPI_CS#1 <22>
PCI_RST# <24,26,28,33,34,36,41>
+3VS
+3VALW
@
2
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SE CRET INFOR MATI ON. THIS SHEET MAY NOT BE TRANSF ERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2006/08/18 2007/8/18
3
Compal Secret Data
Deciphered Date
Title
Size Document Number Rev
2
Date: Sheet
Compal Electronics, Inc.
ICH8M(1/4)-PCI
IFTXX M/B LA-3541P Schematic
1
of
20 52Wednesday, November 01, 2006
0
5
+RTCVCC
1 2
R298 1M_0402_5%
1 2
R302 330K_0402_1%
D D
High = Internal VR Enable
1 2
R724 330K_0402_1%
12
R309
10K_0402_5%
SATA_LED#
+3VS
10/11 Circuit reserved for EMI
BIT_CLK
HDA_SYNC_AUDIO<38>
HDA_SYNC_MDC<42>
HDA_BITCLK_AUDIO<38>
HDA_BITCLK_MDC<42>
HDA_RST_AUDIO#<38>
HDA_RST_MDC#<42>
HDA_SDOUT_AUDIO<38>
HDA_SDOUT_MDC<42>
R763
1 2
10K_0402_5%@
R751
1 2
10K_0402_5%@
C C
+3VS
B B
SM_INTRUDER#
ICH_INTVRMEN
LAN100_SLP
Internal PU 15K, Can be reserved.
SB EDS-1 21762,2.0v1
U49
1
CLKIN
2
NC
8
NC
3
SS
ASM3P623S00BF-08TR_TSSOP8@
1 2
R315 33_0402_5%
1 2
R306 33_0402_5%
1 2
R313 33_0402_5%
1 2
R305 33_0402_5%
1 2
R316 33_0402_5%
1 2
R307 33_0402_5%
1 2
R317 33_0402_5%
1 2
R311 33_0402_5%
7
VDD
6
CLKOUT
5
SSON
4
GND
HDA_SYNC_ICH
HDA_BITCLK_ICH BIT_CLK
HDA_RST_ICH#
HDA_SDOUT_ICH
+3VS
1 2
R762 22_0402_5%@
1 2
R750 10K_0402_5%@
C758
1U_0603_10V4Z@
1 2
32.768KHZ_12.5P_MC-306
+RTCVCC
R297
20K_0402_5%
close to RAM door
HDA_BITCLK_ICH
+3VS
1 2
R752 0_0402_5%
4
C381
18P_0402_50V8J
12
3
2
1 2
J5 JOPEN@
1U_0603_10V4Z
1 2
+1.5VS
IDE_HRESET#<24>
SATA_DTX_C_IRX_N0<24>
SATA_DTX_C_IRX_P0<24>
CLK_PCIE_SATA#<16>
CLK_PCIE_SATA<16>
R318 24.9_0402_1%
X4
OUT
NC
IN
NC
C382
18P_0402_50V8J
12
12
C383
1 2
R304 24.9_0402_1%
HDA_SDIN0<38>
HDA_SDIN1<42>
SATA_LED#<35>
1 2
10mils width less than 500mils
ICH_RTCX1
4
1
ICH_RTCX2
ICH_RTCRST#
IDE_HRESET#
SATA_DTX_C_IRX_N0
SATA_DTX_C_IRX_P0
SATA_ITX_DRX_N0
SATA_ITX_DRX_P0
SATA_DTX_C_IRX_N1
SATA_DTX_C_IRX_P1
SATA_DTX_C_IRX_N2
SATA_DTX_C_IRX_P2
CLK_PCIE_SATA#
CLK_PCIE_SATA
12
R294
10M_0402_5%
SM_INTRUDER#
ICH_INTVRMEN
LAN100_SLP
BIT_CLK
HDA_SYNC_ICH
HDA_RST_ICH#
HDA_SDOUT_ICH
SATA_LED#
SATARBIAS
U30A
AG25
RTCX1
AF24
RTCX2
AF23
RTCRST#
AD22
INTRUDER#
AF25
INTVRMEN
AD21
LAN100_SLP
B24
GLAN_CLK
D22
LAN_RSTSYNC
C21
LAN_RXD0
B21
LAN_RXD1
C22
LAN_RXD2
D21
LAN_TXD0
E20
LAN_TXD1
C20
LAN_TXD2
AH21
GLAN_DOCK#/GPIO13
D25
GLAN_COMPI
C25
GLAN_COMPO
AJ16
HDA_BIT_CLK
AJ15
HDA_SYNC
AE14
HDA_RST#
AJ17
HDA_SDIN0
AH17
HDA_SDIN1
AH15
HDA_SDIN2
AD13
HDA_SDIN3
AE13
HDA_SDOUT
AE10
HDA_DOCK_EN#/GPIO33
AG14
HDA_DOCK_RST#/GPIO34
AF10
SATALED#
AF6
SATA0RXN
AF5
SATA0RXP
AH5
SATA0TXN
AH6
SATA0TXP
AG3
SATA1RXN
AG4
SATA1RXP
AJ4
SATA1TXN
AJ3
SATA1TXP
AF2
SATA2RXN
AF1
SATA2RXP
AE4
SATA2TXN
AE3
SATA2TXP
AB7
SATA_CLKN
AC6
SATA_CLKP
AG1
SATARBIAS#
AG2
SATARBIAS
ICH8M REV 1.0
3
FWH0/LAD0
FWH1/LAD1
FWH2/LAD2
FWH3/LAD3
FWH4/LFRAME#
LDRQ0#
LDRQ1#/GPIO23
RTCLAN / GLAN
LPCCPU
A20GATE
DPRSTP#
DPSLP#
FERR#
CPUPWRGD/GPIO49
IGNNE#
STPCLK#
THRMTRIP#
IHDA
IDE
SATA
DIOW#
DDACK#
IDEIRQ
DDREQ
A20M#
INIT#
INTR
RCIN#
NMI
SMI#
TP8
DD0
DD1
DD2
DD3
DD4
DD5
DD6
DD7
DD8
DD9
DD10
DD11
DD12
DD13
DD14
DD15
DA0
DA1
DA2
DCS1#
DCS3#
DIOR#
IORDY
E5
F5
G8
F6
C4
G9
E6
AF13
AG26
AF26
AE26
AD24
AG29
AF27
AE24
AC20
AH14
AD23
AG28
AA24
AE27
AA23
V1
U2
V3
T1
V4
T5
AB2
T6
T3
R2
T4
V6
V5
U1
V2
U6
AA4
AA1
AB3
Y6
Y5
W4
W3
Y2
Y3
Y1
W5
LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
LPC_FRAME#
LPC_DRQ0#
GATEA20
H_A20M#
R300 0_0402_5%
R301 0_0402_5%
H_FERR#
H_PWRGOOD
H_IGNNE#
H_INIT#
H_INTR
KB_RST#GLAN_COMP
H_NMI
H_SMI#
H_STPCLK#
THRMTRIP_ICH#
IDE_DD0
IDE_DD1
IDE_DD2
IDE_DD3
IDE_DD4
IDE_DD5
IDE_DD6
IDE_DD7
IDE_DD8
IDE_DD9
IDE_DD10
IDE_DD11
IDE_DD12
IDE_DD13
IDE_DD14
IDE_DD15
IDE_DA0
IDE_DA1
IDE_DA2
IDE_DCS1#
IDE_DCS3#
IDE_DIOR#
IDE_DIOW#
IDE_DDACK#
IDE_IRQ
IDE_DIORDY
IDE_DDREQ
2
LPC_AD0 <29,34,36,41>
LPC_AD1 <29,34,36,41>
LPC_AD2 <29,34,36,41>
LPC_AD3 <29,34,36,41>
LPC_FRAME# <29,34,36,41>
LPC_DRQ0# <36,41>
R299 10K_0402_5%
12
GATEA20 <34>
H_A20M# <4>
1 2
1 2
H_FERR# <4>
H_PWRGOOD <5>
H_IGNNE# <4>
H_INIT# <4>
H_INTR <4>
H_NMI <4>
H_SMI# <4>
H_STPCLK# <4>
R308 24.9_0402_1%
1 2
IDE_DD[0..15] <24>
IDE_DA[0..2] <24>
IDE_DCS1# <24>
IDE_DCS3# <24>
IDE_DIOR# <24>
IDE_DIOW# <24>
IDE_DDACK# <24>
IDE_IRQ <24>
IDE_DIORDY <24>
IDE_DDREQ <24>
+3VS
H_DPRSTP#DPRSTP#
H_DPSLP#D PSLP#
R303 10K_0402_5%
KB_RST# <34>
IDE_DIORDY
IDE_IRQ
H_DPRSTP#
R293 56_0402_5%@
H_DPSLP#
R295 56_0402_5%@
H_FERR#
R296 56_0402_5%
H_DPRSTP # <5,8,51>
H_DPSLP# <5>
12
H_THERMTRIP#
R310 56_0402_5%
+3VS
12
R312 4.7K_0402_5%
1 2
R314 8.2K_0402_5%
1 2
1
+1.05VS
12
12
12
H_THERMTRIP# <4,8>
+1.05VS
+3VS
SATA_ITX_DRX_N0
SATA_ITX_DRX_P0 SATA_ITX_C_DRX_P0
1 2
C384 3900P_0402_50V7K
1 2
C385 3900P_0402_50V7K
close ICH8
+3VS
R324
1K_0402_5%
A A
HDA_SDOUT_ICH
ICH_TP3<22>
5
@
R325
1K_0402_5%
@
SATA_ITX_C_DRX_N0
XOR Chain Entr ance Strap
HDA_SDOUTICH_TP3 Description
0
0
1
0
1
0
11
SATA_ITX_C_DRX_N0 <24>
SATA_ITX_C_DRX_P0 <24>
RSVD
Enter XOR Chain
Normal Operation
Set PCIE port config bit 1
4
RTC Battery
Change BATT1 P/N : SP093PA0200 (Panasonic)
1 2
R319 1K_0402_5%
1 2
R321 1K_0402_5%
1 2
R322 1K_0402_5%
1 2
R323
SATA_DTX_C_IRX_N1
SATA_DTX_C_IRX_P1
SATA_DTX_C_IRX_N2
SATA_DTX_C_IRX_P2
1K_0402_5%
SATA_RXn/p need tie to ground when SATA port no used
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SE CRET INFOR MATI ON. THIS SHEET MAY NOT BE TRANSF ERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2006/08/18 2007/8/18
3
Compal Secret Data
Deciphered Date
SP093MX0000 (MAXELL)
BATT1
-+
ML1220T13RE
45@
9/29 Checked. Same as HEL80's
2
12
+RTCBATT
9/29 mod ified to follow ISKAA
+RTC_BATT
R722
1 2
511_0603_1%
Title
Size Document Number Rev
B
Date: Sheet
D13
2
1
3
BAS40-04_SOT23
+CHGRTC
1
C96
0.1U_0402_16V4Z
2
Compal Electronics, Inc.
ICH8M(2/4)-LAN,IDELPC,RTC
IFTXX M/B LA-3541P Schematic
21 52Wednesday, November 01, 2006
1
+RTCVCC
0
of
5
+3VS
10K_0402_5%
R261
1 2
8.2K_0402_5%
R266
1 2
8.2K_0402_5%
R267
1 2
10K_0402_5%@
R613
1 2
+3VALW
R614
R629
R693
R712
R727
R269
R271
R273
R274
R276
R277
R278
R728
R286
R287
10K_0402_5%
1 2
10K_0402_5%
1 2
10K_0402_5%
1 2
10K_0402_5%
1 2
10K_0402_5%
1 2
10K_0402_5%
1 2
10K_0402_5%
1 2
10K_0402_5%
1 2
10K_0402_5%
1 2
10K_0402_5%
1 2
1K_0402_5%
1 2
8.2K_0402_5%
10K_0402_5%
1 2
100K_0402_5%
1 2
100K_0402_5%
1 2
D D
C C
Not in CRB,Keep!
B B
+3VALW
SERIRQ
PM_CLKRUN#
EC_THERM#
PM_STP_PCI#
PM_STP_CPU#
SATA_CLKREQ#
D_ACIN
OCP#
GPIO48
ICH_RI#
ICH_SMLINK0
ICH_SMLINK1
LINKALERT#
ITP_DBRESET#
ICH_PCIE_W AKE#
PM_BATLOW#
12
GPIO39
PM_DPRSLPVR
ICH_VGATE
RP2
USB_OC#2
45
USB_OC#1
36
USB_OC#4
27
USB_OC#5
18
10K_1206_8P4R_5%
1 2
R715 10K_0402_5%
1 2
R716 10K_0402_5%
1 2
R717 10K_0402_5%
R292 10K_0402_5%
1 2
CP_PE#
USB_OC#3
USB_OC#8
USB_OC#9
PM_STP_PCI#<16>
PM_STP_CPU#<16>
LAN
NEW Card
Robson
3G
WLAN
ICH_SMBCLK<16,32,33>
ICH_SMBDATA<16,32,33>
SUS_STAT#<29,41>
ITP_DBRESET#<4>
PM_BMBUSY#<8>
EC_LID_OUT#<34>
PM_STP_PCI#
PM_STP_CPU#
PM_CLKRUN#<28,29,34,41>
ICH_PCIE_WAKE#<30,32,33>
SERIRQ<26,28,29,34,36,41>
EC_THERM#<34>
VGATE<8,51>
ACIN<34,44>
D45 RB751V_SOD323@
EC_SMI#<34>
EC_SCI#<34>
SATA_CLKREQ#<16>
SB_SPKR<38>
MCH_ICH_SYNC#<8>
ICH_TP3<21>
PCIE_PTX_C_IRX_N2<30>
PCIE_PTX_C_IRX_P2<30>
PCIE_ITX_C_PRX_N2<30>
PCIE_ITX_C_PRX_P2<30>
PCIE_PTX_C_IRX_N3<33>
PCIE_PTX_C_IRX_P3<33>
PCIE_ITX_C_PRX_N3<33>
PCIE_ITX_C_PRX_P3<33>
PCIE_PTX_C_IRX_N4<32>
PCIE_PTX_C_IRX_P4<32>
PCIE_ITX_C_PRX_N4<32>
PCIE_ITX_C_PRX_P4<32>
PCIE_PTX_C_IRX_N5<32>
PCIE_PTX_C_IRX_P5<32>
PCIE_ITX_C_PRX_N5<32>
PCIE_ITX_C_PRX_P5<32>
PCIE_PTX_C_IRX_N6<32>
PCIE_PTX_C_IRX_P6<32>
PCIE_ITX_C_PRX_N6<32>
PCIE_ITX_C_PRX_P6<32>
Need to define PROJECT ID
A A
+3VS
+3VS
R281
R283
R694
R284
10K_0402_5%@
1 2
10K_0402_5%
1 2
10K_0402_5%@
1 2
10K_0402_5%
1 2
5
PROJECT_ID0
PROJECT_ID1
4
+3VALW
12
R262
2.2K_0402_5%
R627 0_0402_5%
R628 0_0402_5%@
R275 0_0402_5%
21
C370 0.1U_0402_10V7K
C371 0.1U_0402_10V7K
C373 0.1U_0402_10V7K
C374 0.1U_0402_10V7K
C375 0.1U_0402_10V7K
C376 0.1U_0402_10V7K
C377 0.1U_0402_10V7K
C378 0.1U_0402_10V7K
C379 0.1U_0402_10V7K
C380 0.1U_0402_10V7K
4
12
R263
2.2K_0402_5%
ICH_SMBCLK
ICH_SMBDATA
LINKALERT#
ICH_SMLINK0
ICH_SMLINK1
ICH_RI#
SUS_STAT#
ITP_DBRESET#
PM_BMBUSY#
EC_LID_OUT#
12
12
PM_CLKRUN#
ICH_PCIE_W AKE#
SERIRQ
EC_THERM#
12
PAD
T15
OCP#
D_ACIN
EC_SMI#
EC_SCI#
SATA_CLKREQ#
GPIO39
GPIO48
SB_SPKR
12
12
12
12
12
12
12
12
12
12
U30C
AJ26
SMBCLK
AD19
SMBDATA
AG21
LINKALERT#
AC17
SMLINK0
AE19
SMLINK1
AF17
RI#
F4
SUS_STAT#/LPCPD#
AD15
SYS_RESET#
AG12
BMBUSY#/GPIO0
AG22
SMBALERT#/GPIO11
AE20
STP_PCI#/GPIO15
AG18
STP_CPU#/GPIO25
AH11
CLKRUN#/GPIO32
AE17
WAKE#
AF12
SERIRQ
AC13
ICH_VGATE
THRM#
AJ20
VRMPWRGD
AJ22
TP7
AJ8
TACH1/GPIO1
AJ9
TACH2/GPIO6
AH9
TACH3/GPIO7
AE16
GPIO8
AC19
GPIO12
AG8
TACH0/GPIO17
AH12
GPIO18
AE11
GPIO20
AG10
SCLOCK/GPIO22
AH25
QRT_STATE0/GPIO27
AD16
QRT_STATE1/GPIO28
AG13
SATACLKREQ#/GPIO35
AF9
SLOAD/GPIO38
AJ11
SDATAOUT0/GPIO39
AD10
SDATAOUT1/GPIO48
AD9
SPKR
AJ13
MCH_SYNC#
AJ21
TP3
ICH8M REV 1.0
PCIE_PTX_C_IRX_N2
PCIE_PTX_C_IRX_P2
PCIE_ITX_PRX_N2
PCIE_ITX_PRX_P2
PCIE_PTX_C_IRX_N3
PCIE_PTX_C_IRX_P3
PCIE_ITX_PRX_N3
PCIE_ITX_PRX_P3
PCIE_PTX_C_IRX_N4
PCIE_PTX_C_IRX_P4
PCIE_ITX_PRX_N4
PCIE_ITX_PRX_P4
PCIE_PTX_C_IRX_N5
PCIE_PTX_C_IRX_P5
PCIE_ITX_PRX_N5
PCIE_ITX_PRX_P5
PCIE_PTX_C_IRX_N6
PCIE_PTX_C_IRX_P6
PCIE_ITX_PRX_N6
PCIE_ITX_PRX_P6
SPI not used, Left NC
SPI_CS#1<20>
USB_OC#0<33>
USB_OC#4<37>
USB_OC#5<37>
USB_OC#6<33>
CP_PE#<33>
USB_OC#0
USB_OC#1
USB_OC#2
USB_OC#3
USB_OC#4
USB_OC#5
USB_OC#6
CP_PE#
USB_OC#8
USB_OC#9
3
+3VS
PROJECT_ID1
SATA0GP/GPIO21
SATA1GP/GPIO19
SATA2GP/GPIO36
SATA
GPIO
SATA3GP/GPIO37
SMB
Clocks
S4_STATE#/GPIO26
SYS
GPIO
DPRSLPVR/GPIO16
Power MGTController Link
CK_PWRGD
GPIO
MEM_LED/GPIO24
ME_EC_ALERT/GPIO10
EC_ME_ALERT/GPIO14
WOL_EN/GPIO9
MISC
U30D
P27
PERN1
P26
PERP1
N29
PETN1
N28
PETP1
M27
PERN2
M26
PERP2
L29
PETN2
L28
PETP2
K27
PERN3
K26
PERP3
J29
PETN3
J28
PETP3
H27
PERN4
H26
PERP4
G29
PETN4
G28
PETP4
F27
PERN5
F26
PERP5
E29
PETN5
E28
PETP5
D27
PERN6/GLAN_RXN
D26
PERP6/GLAN_RXP
C29
PETN6/GLAN_TXN
C28
PETP6/GLAN_TXP
C23
SPI_CLK
B23
SPI_CS0#
E22
SPI_CS1#
D23
SPI_MOSI
F21
SPI_MISO
AJ19
OC0#
AG16
OC1#/GPIO40
AG15
OC2#/GPIO41
AE15
OC3#/GPIO42
AF15
OC4#/GPIO43
AG17
OC5#/GPIO29
AD12
OC6#/GPIO30
AJ18
OC7#/GPIO31
AD14
OC8#
AH18
OC9#
ICH8M REV 1.0
Security Classification
Issued Date
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
USB
3
AJ12
PROJECT_ID0
R268 10K_0402_5%
1 2
CLK_ICH_14M
CLK_ICH_48M
SUS_CLK
PM_SLP_S3#
SLP_S4#
SLP_S5#
ICH_POK
DPRSLPVR
R615 100_0402_1%
PM_BATLOW#
PBTN_OUT#
EC_RSMRST#R
CK_PWRGD
PM_SLP_M#
CL_VREF0_ICH
CL_VREF1_ICH
V27
V26
U29
U28
Y27
Y26
W29
W28
AB26
AB25
AA29
AA28
AD27
AD26
AC29
AC28
T26
T25
Y23
Y24
G3
G2
H5
H4
H2
H1
J3
J2
K5
K4
K2
K1
L3
L2
M5
M4
M2
M1
N3
N2
F2
F3
12
R695 0_0402_5%
R285 100K_0402_5%
1 2
DMI_MTX_IRX_N0
DMI_MTX_IRX_P0
DMI_ITX_MRX_N0
DMI_ITX_MRX_P0
DMI_MTX_IRX_N1
DMI_MTX_IRX_P1
DMI_ITX_MRX_N1
DMI_ITX_MRX_P1
DMI_MTX_IRX_N2
DMI_MTX_IRX_P2
DMI_ITX_MRX_N2
DMI_ITX_MRX_P2
DMI_MTX_IRX_N3
DMI_MTX_IRX_P3
DMI_ITX_MRX_N3
DMI_ITX_MRX_P3
CLK_PCIE_ICH#
CLK_PCIE_ICH
DMI_IRCOMP
USB20_N0
USB20_P0
USB20_N1
USB20_P1
USB20_N2
USB20_P2
USB20_N3
USB20_P3
USB20_N4
USB20_P4
USB20_N5
USB20_P5
USB20_N6
USB20_P6
USB20_N7
USB20_P7
USB20_N8 USB20_N8
USB20_P8
USB20_N9
USB20_P9
USBRBIAS
USBRBIAS
PAD
T14
12
ICH_POK
PAD
T16
R290 24.9_0402_1%
1 2
R291
22.6_0402_1%
1 2
CLK_ICH_14M <16>
CLK_ICH_48M <16>
PM_SLP_S3# <34>
ICH_POK <8,34>
PBTN_OUT# <34>
PLT_RST# <8,20,29,30,41>
CL_CLK0 <8>
CL_DATA0 <8>
CL_RST# <8>
DMI_MTX_IRX_N0 <8>
DMI_MTX_IRX_P0 <8>
DMI_ITX_MRX_N0 <8>
DMI_ITX_MRX_P0 <8>
DMI_MTX_IRX_N1 <8>
DMI_MTX_IRX_P1 <8>
DMI_ITX_MRX_N1 <8>
DMI_ITX_MRX_P1 <8>
DMI_MTX_IRX_N2 <8>
DMI_MTX_IRX_P2 <8>
DMI_ITX_MRX_N2 <8>
DMI_ITX_MRX_P2 <8>
DMI_MTX_IRX_N3 <8>
DMI_MTX_IRX_P3 <8>
DMI_ITX_MRX_N3 <8>
DMI_ITX_MRX_P3 <8>
CLK14
CLK48
SUSCLK
SLP_S3#
SLP_S4#
SLP_S5#
PWROK
BATLOW#
PWRBTN#
LAN_RST#
RSMRST#
CLPWROK
SLP_M#
CL_CLK0
CL_CLK1
CL_DATA0
CL_DATA1
CL_VREF0
CL_VREF1
CL_RST#
DMI0RXN
DMI0RXP
DMI0TXN
DMI0TXP
DMI1RXN
DMI1RXP
DMI1TXN
DMI1TXP
DMI2RXN
DMI2RXP
DMI2TXN
DMI2TXP
DMI3RXN
DMI3RXP
DMI3TXN
DMI3TXP
PCI-Express
DMI_CLKN
DMI_CLKP
DMI_ZCOMP
DMI_IRCOMP
Direct Media Interface
USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4N
SPI
USBP4P
USBP5N
USBP5P
USBP6N
USBP6P
USBP7N
USBP7P
USBP8N
USBP8P
USBP9N
USBP9P
USBRBIAS#
USBRBIAS
AJ10
AF11
AG11
AG9
G5
D3
AG23
AF21
AD18
AH27
AE23
AJ14
AE21
C2
AH20
AG27
E1
E3
AJ25
F23
AE18
F22
AF19
D24
AH23
AJ23
AJ27
AJ24
AF22
AG19
Within 500 mils
2006/08/18 2007/8/18
Compal Secret Data
Deciphered Date
2
PM_DPRSLPVR <8,51>
CK_PWRGD <16>
CL_PWROK <8>
CLK_PCIE_ICH# <16>
CLK_PCIE_ICH <16>
Within 500 mils
USB20_N0 <33>
USB20_P0 <33>
USB20_N1 <32>
USB20_P1 <32>
USB20_N2 <33>
USB20_P2 <33>
USB20_N3 <32>
USB20_P3 <32>
USB20_N4 <37>
USB20_P4 <37>
USB20_N5 <37>
USB20_P5 <37>
USB20_N6 <33>
USB20_P6 <33>
USB20_N7 <42>
USB20_P7 <42>
USB20_N9 <42>
USB20_P9 <42>
+1.5VS
USB
3G/TV
New Card
WLAN
USB
USB
USB
CAMERA
BT
FP
2
1
Place closely pin B2 Place closely pin AC1
4
12
R265
10_0402_5%
@
1
C368
10P_0402_50V8J
@
2
PM_SLP_S5#
C372
0.1U_0402_16V4Z
CLK_ICH_14M
CLK_ICH_48M
12
R264
10_0402_5%
@
1
C367
10P_0402_50V8J
@
2
+3VALW
5
SLP_S4#
SLP_S5#
ICH_POK
EC_RSMRST#R
+3VS +3VS
CL_VREF0_ICH CL_VREF1_ICH
1
C369
0.1U_0402_16V4Z
2
U9
1
P
B
Y
2
A
G
TC7SH08FUF_SSOP5
3
1 2
R270 10K_0402_5%
1 2
R272 10K_0402_5%
R279
3.24K_0402_1%
R282
453_0402_1%
RSMRST circuit
R633
0_0402_5%
1 2
Q45
C
1
3
2.2K_0402_5%@
4
5
3
USB20_N8_1
USB20_P8_1
USB20_P8_2
E
B
2
1
2
6
1
MMBT3906_SOT23@
R634 4.7K_0402_5%@
D44A
BAV99DW-7_SOT363
EC_RSMRST#<34>
BAV99DW-7_SOT363@
R636
2.2K_0402_5%@
USB20_P8
USB20_P8
USB20_N8 USB20_N8_2
Size Document Number Rev
Custom
Date: Sheet
D44B
1 2
R635
1 2
1 4
2 3
RP54
0_0404_4P2R_5%
15W@
1 4
2 3
RP55
0_0404_4P2R_5%
14W@
Title
Compal Electronics, Inc.
ICH8M(3/4)- USB, GPIO,PCIE
IFTXX M/B LA-3541P Schematic
PM_SLP_S5# <34>
1
2
EC_RSMRST#R
1 2
@
USB20_N8_1 <36>
USB20_P8_1 <36>
USB20_P8_2 <36>
USB20_N8_2 <36>
22 52Wednesday, November 01, 2006
R288
3.24K_0402_1%
R289
453_0402_1%
+3VALW
of
0
5
+5VS
+3VS
R253
100_0402_5%
D D
R255
10_0402_5%
+1.5VS
VCC1_5_B ~675mA
C C
21
1 2
2
C332
0.1U_0402_16V4Z
1
+3VALW+5VALW
21
1 2
2
1
L23
KC FBM-L11-201209-221LMAT_0805
+1.5VS
+RTCVCC
D29
RB751V_SOD323
+ICH_V5REF
Update Footprint
Update Footprint
D30
RB751V_SOD323
+ICH_V5REF_SUS
C335
0.1U_0402_16V4Z
+1.5VS_PCIE_ICH
12
1
+
C337
220U_D2_2VMR15
2
L24
1 2
MBK1608121YZF_0603
(10UF*1, 1UF*1)
close to AE7
1
C329
+ICH_V5REF
2
+ICH_V5REF_SUS
1mA
C328
0.1U_0402_16V4Z
1U_0603_10V4Z
(220UF*1, 22UF*2, 2.2UF*1)
1
C339
22U_0805_6.3V6M
2
1
2
C352
1U_0603_10V4Z
1
C340
2
2.2U_0805_10V6K
C345
1U_0603_10V4Z
C353
1U_0603_10V4Z
C338
22U_0805_6.3V6M
+1.5VS_SATAPLL_ICH
C344
10U_0805_10V4Z
+1.5VS
close to AC1
VCC1_5_A ~1.56A
B B
+3VS
VCCLAN3_3 ~18mA
+1.5VS
R260
1_0603_5%
VCCGLANPLL~23mA
A A
VCCGLAN1_5 ~80mA 1mA
VCCUSBPLL ~10mA
+1.5VS
0.1U_0402_16V4Z
1
+
C757
220U_D2_2VMR15
2
@
close to D1
1
C361
2
+VCC_GLANPLL_R +VCC_GLANPLL_ICH
(10UF*1, 1UF*1)
+1.5VS_PCIE_ICH
(220UF*1, 1UF*1)
5
C356
0.1U_0402_16V4Z
T10
T11
1 2
MBK1608121YZF_0603
L25
1
1
C357
2
2
0.1U_0402_16V4Z
close to F1
TP_VCCLAN1_05_ICH_1
PAD
TP_VCCLAN1_05_ICH_2
PAD
1
C364
10U_0805_10V4Z
2
2.2U_0805_10V6K
C366
4.7U_0805_10V4Z
C365
+3VS
AD25
1mA
A16
AA25
AA26
AA27
AB27
AB28
AB29
D28
D29
E25
E26
E27
F24
F25
G24
H23
H24
J23
J24
K24
K25
L23
L24
L25
M24
M25
N23
N24
N25
P24
P25
R24
R25
R26
R27
T23
T24
T27
T28
T29
U24
U25
V23
V24
V25
W25
Y25
AJ6
AE7
AF7
AG7
AH7
AJ7
AC1
AC2
AC3
AC4
AC5
AC10
AC9
AA5
AA6
G12
G17
AC7
AD7
M6
M7
W23
F17
G18
F19
G20
A24
A26
A27
B26
B27
B28
B25
U30F
VCCRTC
V5REF[1]
T7
V5REF[2]
G4
V5REF_SUS
VCC1_5_B[01]
VCC1_5_B[02]
VCC1_5_B[03]
VCC1_5_B[04]
VCC1_5_B[05]
VCC1_5_B[06]
VCC1_5_B[07]
VCC1_5_B[08]
VCC1_5_B[09]
VCC1_5_B[10]
VCC1_5_B[11]
VCC1_5_B[12]
VCC1_5_B[13]
VCC1_5_B[14]
VCC1_5_B[15]
VCC1_5_B[16]
VCC1_5_B[17]
VCC1_5_B[18]
VCC1_5_B[19]
VCC1_5_B[20]
VCC1_5_B[21]
VCC1_5_B[22]
VCC1_5_B[23]
VCC1_5_B[24]
VCC1_5_B[25]
VCC1_5_B[26]
VCC1_5_B[27]
VCC1_5_B[28]
VCC1_5_B[29]
VCC1_5_B[30]
VCC1_5_B[31]
VCC1_5_B[32]
VCC1_5_B[33]
VCC1_5_B[34]
VCC1_5_B[35]
VCC1_5_B[36]
VCC1_5_B[37]
VCC1_5_B[38]
VCC1_5_B[39]
VCC1_5_B[40]
VCC1_5_B[41]
VCC1_5_B[42]
VCC1_5_B[43]
VCC1_5_B[44]
VCC1_5_B[45]
VCC1_5_B[46]
VCCSATAPLL
VCC1_5_A[01]
VCC1_5_A[02]
VCC1_5_A[03]
VCC1_5_A[04]
VCC1_5_A[05]
VCC1_5_A[06]
VCC1_5_A[07]
VCC1_5_A[08]
VCC1_5_A[09]
VCC1_5_A[10]
VCC1_5_A[11]
VCC1_5_A[12]
VCC1_5_A[13]
VCC1_5_A[14]
VCC1_5_A[15]
VCC1_5_A[16]
H7
VCC1_5_A[17]
VCC1_5_A[18]
VCC1_5_A[19]
D1
VCCUSBPLL
F1
VCC1_5_A[20]
L6
VCC1_5_A[21]
L7
VCC1_5_A[22]
VCC1_5_A[23]
VCC1_5_A[24]
VCC1_5_A[25]
VCCLAN1_05[1]
VCCLAN1_05[2]
VCCLAN3_3[1]
VCCLAN3_3[2]
VCCGLANPLL
VCCGLAN1_5[1]
VCCGLAN1_5[2]
VCCGLAN1_5[3]
VCCGLAN1_5[4]
VCCGLAN1_5[5]
VCCGLAN3_3
ICH8M REV 1.0
4
VCC_DMI[1]
VCC_DMI[2]
VCC3_3[01]
VCC3_3[02]
VCC3_3[03]
VCC3_3[04]
VCC3_3[05]
VCC3_3[06]
VCC3_3[07]
VCC3_3[08]
VCC3_3[09]
VCC3_3[10]
VCC3_3[11]
VCC3_3[12]
VCC3_3[13]
VCC3_3[14]
VCC3_3[15]
VCC3_3[16]
VCC3_3[17]
VCC3_3[18]
VCC3_3[19]
VCC3_3[20]
VCC3_3[21]
VCC3_3[22]
VCC3_3[23]
VCC3_3[24]
VCCHDA
VCCCL1_05
VCCCL1_5
A13
B13
C13
C14
D14
E14
F14
G14
L11
L12
L14
L16
L17
L18
M11
M18
P11
P18
T11
T18
U11
U18
V11
V12
V14
V16
V17
V18
R29
AE28
AE29
AC23
AC24
AF29
AD2
AC8
AD8
AE8
AF8
AA3
U7
V7
W1
W6
W7
Y7
A8
B15
B18
B4
B9
C15
D13
D5
E10
E7
F11
AC12
AD11
J6
AF20
AC16
J7
C3
AC18
AC21
AC22
AG20
AH28
P6
P7
C1
N7
P1
P2
P3
P4
P5
R1
R3
R5
R6
G22
A22
F20
G21
0.1U_0402_16V4Z
0.1U_0402_16V4Z
close to AF29
0.1U_0402_16V4Z
TP_VCCSUS1_05_ICH_1
TP_VCCSUS1_05_ICH_2
TP_VCCSUS1_5_ICH_1
TP_VCCSUS1_5_ICH_2
VCCSUS3_3
TP_VCCCL1_05_ICH
+VCCCL1_5_INT_ICH
18mA
1
C330
0.1U_0402_16V4Z
2
+1.5VS_DMIPLL_ICH
C333
10U_0805_10V4Z
C341
4.7U_0805_10V4Z
0.1U_0402_16V4Z
1
C346
2
1
C349
2
0.1U_0402_16V4Z
VCCHDA~32mA
VCCSusHDA~32mA
C358
4.7U_0805_10V4Z
close to P6 close to AC18
+3VS
CORE
VCCA3GP ATXARX
VCCP_COREVCCPSUSVCCPUSB
IDE
PCI
VCCSUS1_05[1]
VCCSUS1_05[2]
VCCSUS1_5[1]
VCCSUS1_5[2]
VCCSUS3_3[01]
VCCSUS3_3[02]
VCCSUS3_3[03]
VCCSUS3_3[04]
VCCSUS3_3[05]
USB CORE
VCCSUS3_3[06]
VCCSUS3_3[07]
VCCSUS3_3[08]
VCCSUS3_3[09]
VCCSUS3_3[10]
VCCSUS3_3[11]
VCCSUS3_3[12]
VCCSUS3_3[13]
VCCSUS3_3[14]
VCCSUS3_3[15]
VCCSUS3_3[16]
VCCSUS3_3[17]
VCCSUS3_3[18]
VCCSUS3_3[19]
GLAN POWER
VCC1_05[01]
VCC1_05[02]
VCC1_05[03]
VCC1_05[04]
VCC1_05[05]
VCC1_05[06]
VCC1_05[07]
VCC1_05[08]
VCC1_05[09]
VCC1_05[10]
VCC1_05[11]
VCC1_05[12]
VCC1_05[13]
VCC1_05[14]
VCC1_05[15]
VCC1_05[16]
VCC1_05[17]
VCC1_05[18]
VCC1_05[19]
VCC1_05[20]
VCC1_05[21]
VCC1_05[22]
VCC1_05[23]
VCC1_05[24]
VCC1_05[25]
VCC1_05[26]
VCC1_05[27]
VCC1_05[28]
VCCDMIPLL
V_CPU_IO[1]
V_CPU_IO[2]
VCCSUSHDA
VCCCL3_3[1]
VCCCL3_3[2]
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
1
C331
2
1
C334
2
0.01U_0402_16V7K
1
C336
22U_0805_6.3V6M
2
1
C343
C342
0.1U_0402_16V4Z
2
close to AD2
1
C347
2
0.1U_0402_16V4Z
1
C351
C350
0.1U_0402_16V4Z
2
PAD
PAD
PAD
PAD
1
C359
2
0.1U_0402_16V4Z
PAD
T12
3
VCC1_05 ~1.13A
+1.05VS
(47UF*1, 0.047UF*1, 0.022UF*1)
+1.5VS_DMIPLL_R
L22
1 2
MBK1608121YZF_0603
(10UF*1, 0.01UF*1)
+1.25VS
R254 1_0603_5%
VCCDMIPLL~23mA
+1.5VS
(22UF*1, 0.1UF*1)
VCCDMI ~50mA
+1.05VS
1
2
C348
0.1U_0402_16V4Z
close to AA3
1
2
T6
T7
T8
T9
C360
0.1U_0402_16V4Z
V_CPU_IO ~1mA
(4.7UF*1, 0.1UF*2)
+3VS
1
VCC3_3 ~278mA
2
+3VS
1
2
C362
1U_0603_10V4Z
@
1
2
+VCCSUS_HDA_ICH
1 2
R637 0_0805_5%
VCCSus3_3~177mA
(0.1UF*1, 0.022UF*2)
+3VS
C354
0.1U_0402_16V4Z
1
C355
0.1U_0402_16V4Z
2
+3VALW
1
C363
0.1U_0402_16V4Z
2
@
Add for Audio low voltage mode
R259
0_0603_5%
(0.1UF*1)
2006/08/18 2007/8/18
3
Compal Secret Data
Deciphered Date
+3VALW
2
U30E
A23
VSS[001]
A5
VSS[002]
AA2
VSS[003]
AA7
VSS[004]
A25
VSS[005]
AB1
VSS[006]
AB24
VSS[007]
AC11
VSS[008]
AC14
VSS[009]
AC25
VSS[010]
AC26
VSS[011]
AC27
VSS[012]
AD17
VSS[013]
AD20
VSS[014]
AD28
VSS[015]
AD29
VSS[016]
AD3
VSS[017]
AD4
VSS[018]
AD6
VSS[019]
AE1
VSS[020]
AE12
VSS[021]
AE2
VSS[022]
AE22
VSS[023]
AD1
VSS[024]
AE25
VSS[025]
AE5
VSS[026]
AE6
VSS[027]
AE9
VSS[028]
AF14
VSS[029]
AF16
VSS[030]
AF18
VSS[031]
AF3
VSS[032]
AF4
VSS[033]
AG5
VSS[034]
AG6
VSS[035]
AH10
VSS[036]
AH13
VSS[037]
AH16
VSS[038]
AH19
VSS[039]
AH2
VSS[040]
AF28
VSS[041]
AH22
VSS[042]
AH24
VSS[043]
AH26
VSS[044]
AH3
VSS[045]
AH4
VSS[046]
AH8
VSS[047]
AJ5
VSS[048]
B11
VSS[049]
B14
VSS[050]
B17
VSS[051]
B2
VSS[052]
B20
VSS[053]
B22
VSS[054]
B8
VSS[055]
C24
VSS[056]
C26
VSS[057]
C27
VSS[058]
C6
VSS[059]
D12
VSS[060]
D15
VSS[061]
D18
VSS[062]
D2
VSS[063]
D4
VSS[064]
E21
VSS[065]
E24
VSS[066]
E4
VSS[067]
E9
VSS[068]
F15
VSS[069]
E23
VSS[070]
F28
VSS[071]
F29
VSS[072]
F7
VSS[073]
G1
VSS[074]
E2
VSS[075]
G10
VSS[076]
G13
VSS[077]
G19
VSS[078]
G23
VSS[079]
G25
VSS[080]
G26
VSS[081]
G27
VSS[082]
H25
VSS[083]
H28
VSS[084]
H29
VSS[085]
H3
VSS[086]
H6
VSS[087]
J1
VSS[088]
J25
VSS[089]
J26
VSS[090]
J27
VSS[091]
J4
VSS[092]
J5
VSS[093]
K23
VSS[094]
K28
VSS[095]
K29
VSS[096]
K3
VSS[097]
K6
VSS[098]
ICH8M REV 1.0
Title
Size Document Number Rev
Custom
ICL50/ICK70 M/B LA-3551P Schematic
2
Date: Sheet
VSS_NCTF[01]
VSS_NCTF[02]
VSS_NCTF[03]
VSS_NCTF[04]
VSS_NCTF[05]
VSS_NCTF[06]
VSS_NCTF[07]
VSS_NCTF[08]
VSS_NCTF[09]
VSS_NCTF[10]
VSS_NCTF[11]
VSS_NCTF[12]
Compal E lectronics, Inc.
IFTXX M/B LA-3541P Schematic
VSS[099]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
VSS[159]
VSS[160]
VSS[161]
VSS[162]
VSS[163]
VSS[164]
VSS[165]
VSS[166]
VSS[167]
VSS[168]
VSS[169]
VSS[170]
VSS[171]
VSS[172]
VSS[173]
VSS[174]
VSS[175]
VSS[176]
VSS[177]
VSS[178]
VSS[179]
VSS[180]
VSS[181]
VSS[182]
VSS[183]
VSS[184]
1
K7
L1
L13
L15
L26
L27
L4
L5
M12
M13
M14
M15
M16
M17
M23
M28
M29
M3
N1
N11
N12
N13
N14
N15
N16
N17
N18
N26
N27
N4
N5
N6
P12
P13
P14
P15
P16
P17
P23
P28
P29
R11
R12
R13
R14
R15
R16
R17
R18
R28
R4
T12
T13
T14
T15
T16
T17
T2
U12
U13
U14
U15
U16
U17
U23
U26
U27
U3
U5
V13
V15
V28
V29
W2
W26
W27
Y28
Y29
Y4
AB4
AB23
AB5
AB6
AD5
U4
W24
A1
A2
A28
A29
AH1
AH29
AJ1
AJ2
AJ28
AJ29
B1
B29
1
23 52Wednesday, November 01, 2006
0
of
A
B
C
D
E
F
G
H
14W ODD Conn.
Placea caps. near ODD CONN.
+5VS
14W@
0.1U_0402_16V4Z
1
1 1
2 2
3 3
4 4
1000P_0402_50V7K
15W@
2
1000P_0402_50V7K
14W@
IDE_CSEL
Grounding for Master (When use SATA HDD)
Open or Hi gh fo r Slave r (N ormal)
IDE_RST#
IDE_DD7
IDE_DD6
IDE_DD5
IDE_DD4
IDE_DD3
IDE_DD2
IDE_DD1
IDE_DD0
IDE_DIOW#
IDE_DIORDY
IDE_IRQ
IDE_DA1
IDE_DA0
IDE_DCS1#
IDE_LED#
IDE_CSEL R_IDE_CSEL
IDE_DD9
IDE_DD10
IDE_DD11
IDE_DD12
IDE_DD13
IDE_DD14
IDE_DD15
IDE_DDREQ
IDE_DIOR#
IDE_DDACK#
IDE_PDIAG#
IDE_DA2
IDE_DCS3#
+5VS_ODD
15W@
0.1U_0402_16V4Z
1
C731
C730
2
A
1
C315
C314
2
1U_0603_10V4Z
14W@
IDE_DIOW#<21>
IDE_DIORDY<21>
IDE_IRQ<21>
IDE_DCS1#<21>
+5VS +5VS
R251 475_0402_1%
+5VS +5VS_ODD
J7
1 2
PAD-OPEN 3x3m
R662 0_0402_5%15W@
R663 0_0402_5%15W@
R664 0_0402_5%15W@
R665 0_0402_5%15W@
R666 0_0402_5%15W@
R667 0_0402_5%15W@
R668 0_0402_5%15W@
R669 0_0402_5%15W@
R670 0_0402_5%15W@
R671 0_0402_5%15W@
R672 0_0402_5%15W@
R673 0_0402_5%15W@
R674 0_0402_5%15W@
R675 0_0402_5%15W@
R676 0_0402_5%15W@
R677 0_0402_5%15W@
R678 0_0402_5%15W@
R679 0_0402_5%15W@
R680 0_0402_5%15W@
R681 0_0402_5%15W@
R682 0_0402_5%15W@
R683 0_0402_5%15W@
R684 0_0402_5%15W@
R685 0_0402_5%15W@
R686 0_0402_5%15W@
R687 0_0402_5%15W@
R688 0_0402_5%15W@
R689 0_0402_5%15W@
R690 0_0402_5%15W@
R691 0_0402_5%15W@
R692 0_0402_5%15W@
1
2
@
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1
C732
2
1U_0603_10V4Z
15W@
1
C316
2
1 2
15W@
10U_0805_10V4Z
1
2
14W@
10U_0805_10V4Z
1
C317
2
10U_0805_10V4Z
14W@
IDE_RST#
IDE_DD7
IDE_DD6
IDE_DD5
IDE_DD4
IDE_DD2
IDE_DD1
IDE_DD0
IDE_DIOW#
IDE_DIORDY
IDE_IRQ
IDE_DA1
IDE_DA0
IDE_DCS1#
IDE_LED#
IDE_CSEL
Remember Short at 15W@
R_IDE_RST#
R_IDE_DD7
R_IDE_DD6
R_IDE_DD5
R_IDE_DD4
R_IDE_DD3
R_IDE_DD2
R_IDE_DD1
R_IDE_DD0
R_IDE_DIOW#
R_IDE_DIORDY
R_IDE_IRQ
R_IDE_DA1
R_IDE_DA0
R_IDE_DCS1#
R_IDE_LED#
R_IDE_DD8IDE_DD8
R_IDE_DD9
R_IDE_DD10
R_IDE_DD11
R_IDE_DD12
R_IDE_DD13
R_IDE_DD14
R_IDE_DD15
R_IDE_DDREQ
R_IDE_DIOR#
R_IDE_DDACK#
R_IDE_PDIAG#
R_IDE_DA2
R_IDE_DCS3#
1
C733
C734
2
10U_0805_10V4Z
15W@
B
1
C318
2
JP27
112
334
556
778
9910
111112
131314
151516
171718
191920
212122
232324
252526
272728
292930
313132
333334
353536
373738
393940
414142
434344
454546
474748
494950
OCTEK_CDR-50DY1G
14W@
(NEW)
+5VS
R252 100K_0402_5%
IDE_DD[0..15]<21>
IDE_DA[0..2]<21>
2
4
IDE_DD8
6
IDE_DD9
8
IDE_DD10
10
IDE_DD11
12
IDE_DD12
14
IDE_DD13IDE_DD3
16
IDE_DD14
18
IDE_DD15
20
IDE_DDREQ
22
IDE_DIOR#
24
26
IDE_DDACK#
28
30
IDE_PDIAG#
32
IDE_DA2
34
IDE_DCS3#
36
38
40
42
44
46
48
50
IDE_LED#
12
IDE_DD[0..15]
IDE_DA[0..2]
1 2
IDE_DDREQ <21>
IDE_DIOR# <21>
IDE_DDACK# <21>
R250
100K_0402_5%
IDE_DCS3# <21>
+5VS
15W ODD Conn.
JP41
2
112
4
R_IDE_RST#
R_IDE_DD7
R_IDE_DD6
R_IDE_DD5
R_IDE_DD4
R_IDE_DD3
R_IDE_DD2
R_IDE_DD1
R_IDE_DD0
R_IDE_DIOW#
R_IDE_DIORDY
R_IDE_IRQ
R_IDE_DA1
R_IDE_DA0
R_IDE_DCS1#
+5VS_ODD +5VS_ODD
R_IDE_LED#
R_IDE_CSEL
C
334
556
778
9910
111112
131314
151516
171718
191920
212122
232324
252526
272728
292930
313132
333334
353536
373738
393940
414142
434344
454546
474748
494950
OCTEK_CDR-50DY1G
15W@
R_IDE_DD8
6
R_IDE_DD9
8
R_IDE_DD10
10
R_IDE_DD11
12
R_IDE_DD12
14
R_IDE_DD13
16
R_IDE_DD14
18
R_IDE_DD15
20
R_IDE_DDREQ
22
R_IDE_DIOR#
24
26
R_IDE_DDACK#
28
30
R_IDE_PDIAG#
32
R_IDE_DA2
34
R_IDE_DCS3#
36
38
40
42
44
46
48
50
Security Classification
Issued Date
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
D
IDE_HRESET#<21>
PCI_RST#<20,26,28,33,34,36,41>
IDE_HRESET#
PCI_RST#
NC7SZ08P5X_NL_SC70-5
SATA HDD Conn.
+5VS +3VS
0.1U_0402_16V4Z
1
2
1000P_0402_50V7K
2006/08/18 2007/8/18
E
1
C323
2
SATA_DTX_C_IRX_N0<21>
SATA_DTX_C_IRX_P0<21>
Compal Secret Data
C324
1U_0603_10V4Z
Deciphered Date
1
C325
2
10U_0805_10V4Z
1
C326
2
SATA_DTX_C_IRX_N0
SATA_DTX_C_IRX_P0
F
1
C327
2
10U_0805_10V4Z
SATA_ITX_C_DRX_P0<21>
SATA_ITX_C_DRX_N0<21>
1 2
C320 3900P_0402_50V7K
1 2
C321 3900P_0402_50V7K
+3VS
C319
0.1U_0402_16V4Z
1 2
5
U29
2
P
B
1
A
G
3
IDE_RST#
4
Y
Update Footprint
1
C322
0.1U_0402_16V4Z
2
@
JP28
1
SATA_ITX_C_DRX_P0
SATA_ITX_C_DRX_N0
SATA_DTX_IRX_N0
SATA_DTX_IRX_P0
+3VS
+5VS
Title
Size Document Number Rev
B
Date: Sheet
Compal Electronics, Inc.
HDD & ODD Connector
IFTXX M/B LA-3541P Schematic
G
GND
2
A+
3
A-
4
GND
5
B-
6
B+
7
GND
8
V33
9
V33
10
V33
11
GND
12
GND
13
GND
14
V5
15
V5
16
V5
17
GND
18
Reserved
19
GND
20
V12
21
V12
22
V12
SUYIN_127043FB022S338ZR_RV
ME@
(NEW)
Change Library
0
of
24 52Wednesday, November 01, 2006
H
5
D D
4
3
2
1
Note : BOM structure HS@ is for Heng shan IFT10/11 this model
Q32
C752
SI2301BDS_SOT23
HS@
1 3
D
2
12
X
R247 10K_0402_1%
12
Y
R249 10K_0402_1%
10
1
4
8
9
11
13
16
S
G
R243
100K_0402_5%
HS@
HS@
1 2
1 2
HS@
0.1U_0402_16V4Z
1
C308
1U_0603_10V4Z
2
HS@
C312
HS@
1
2
+3VS_ITES
1
C309
0.1U_0402_16V4Z
2
HS@
C C
ITES_ST<34>
B B
D28 RB751V_SOD323
HS@
1
C310
1U_0603_10V4Z
2
HS@
21
1
C311
10U_0805_6.3V6M
2
HS@
+3VALW
12
R246
10K_0402_5%
HS@
12
R248
100K_0402_5%
@
ST
R245
+3VS_ITES_R
1 2
47_0402_5%HS@
U28
2
ST
14
Vs
15
Vs
3
COM
5
COM
6
COM
7
COM
ADXL322JCP-REEL_LFCSP16P_4*4
HS@
ITES_EN#<34>
1 2
0.1U_0402_16V4Z
HS@
Xout
Yout
NC
NC
NC
NC
NC
NC
NC
9/19 modifi ed from +EC_AVCC t o +3VALW
+3VALW
ITES_VSENSE_X <34>
ITES_VSENSE_Y <34>
1
C313
0.1U_0402_16V4Z
2
HS@
A A
Security Classification
Issued Date
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2006/08/05 2007/08/05
Compal Secret Data
Deciphered Date
Title
Size Document Number Rev
B
2
Date: Sheet
Compal Electronics, Inc.
CH7315A&HDMI Connector
LA-3541P
25 52Wednesday, November 01, 2006
1
0.1
of
A
1 1
PCI_AD[0..31]<20,28>
PCI_CBE#[0..3]<20,28>
12
1
2
2 2
+3VS
MS_PWREN#
3 3
+3VS
1
C716
PCMCIA@
4.7U_0805_10V4Z
2
+3VS
4 4
0.1U_0402_16V4Z
PCMCIA@
40mil
0.1U_0402_16V4Z
PCMCIA@
1
C721
2
A
PCI_AD[0..31]
PCI_CBE#[0..3]
CLK_PCI_PCM
R641
10_0402_5%@
C710
15P_0402_50V8J@
1 2
R643 10K_0402_5%PCMCIA@
R645
1 2
0_0402_5%
@
NEED CHECK
+3VS
1 2
R646 43K_0402_5%@
1 2
R647 10K_0402_5%@
1 2
R648 10K_0402_5%@
1
C717
PCMCIA@
0.1U_0402_16V4Z
2
1
1
C722
C723
2
2
0.1U_0402_16V4Z
PCMCIA@
+S1_VCC
0.1U_0402_16V4Z
PCMCIA@
B
VPPD0
VPPD1
VCCD0#
VCCD1#
U44
PCI_AD31
PCI_AD30
PCI_AD29
PCI_AD28
PCI_AD27
PCI_AD26
PCI_AD25
PCI_AD24
PCI_AD23
PCI_AD22
PCI_AD21
PCI_AD20
PCI_AD19
PCI_AD18
PCI_AD17
PCI_AD16
PCI_AD15
PCI_AD14
PCI_AD13
PCI_AD12
PCI_AD11
PCI_AD10
PCI_AD9
PCI_AD8
PCI_AD7
PCI_AD6
PCI_AD5
PCI_AD4
PCI_AD3
PCI_AD2
PCI_AD1
PCI_AD0
PCI_CBE#3
PCI_CBE#2
PCI_CBE#1
PCI_CBE#0
PCI_RST#<20,24,28,33,34,36,41>
PCI_FRAME#<20,28>
PCI_IRDY#<20,28>
PCI_TRDY#<20,28>
PCI_DEVSEL#<20,28>
PCI_STOP#<20,28>
PCI_PERR#<20,28>
PCI_SERR#<20,28>
PCI_PAR<20,28>
PCI_REQ#2<20>
PCI_GNT#2<20>
CLK_PCI_PCM<16>
PCI_AD20
PCI_PIRQC#<20>
SERIRQ<22,28,29,34,36,41>
SM_CD# S1_CD2#
5IN1_LED#
SDOC#
1
C719
PCMCIA@
0.1U_0402_16V4Z
2
1
C724
2
0.1U_0402_16V4Z
PCMCIA@
PCI_RST#
PCI_REQ#2
CLK_PCI_PCM
PCMCIA@
1 2
R644 100_0402_5%
SD_PULLHIGH
SM_CD#
5IN1_LED#
SDOC#
PCI_RST#
1
C720
PCMCIA@
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z
PCMCIA@
1
C725
2
B
1
C726
2
C2
AD31
C1
AD30
D4
AD29
D2
AD28
D1
AD27
E4
AD26
E3
AD25
E2
AD24
F2
AD23
F1
AD22
G2
AD21
G3
AD20
H3
AD19
H4
AD18
J1
AD17
J2
AD16
N2
AD15
M3
AD14
N3
AD13
K4
AD12
M4
AD11
K5
AD10
L5
AD9
M5
AD8
K6
AD7
M6
AD6
N6
AD5
M7
AD4
N7
AD3
L7
AD2
K7
AD1
N8
AD0
E1
CBE3#
J3
CBE2#
N1
CBE1#
N5
CBE0#
G4
PCIRST#
J4
FRAME#
K1
IRDY#
K3
TRDY#
L1
DEVSEL#
L2
STOP#
L3
PERR#
M1
SERR#
M2
PAR
A1
PCIREQ#
B1
PCIGNT#
H1
PCICLK
L8
RIOUT#_PME#
L11
SUSPEND#
F4
IDSEL
K8
MFUNC0
N9
MFUNC1
K9
MFUNC2
N10
MFUNC3
L10
MFUNC4
N11
MFUNC5
M11
MFUNC6
J9
MFUNC7
M10
GRST#
E7
VCC_SD
E8
SDCD#
F8
SDWP/SMWPD#
G7
SDPWREN33#
H5
SDCLKI
F6
SDCLK/SMWE#
E5
SDCMD/SMALE
E6
SDDAT0/SMDATA7
F7
SDDAT1/SMDATA0
F5
SDDAT2/SMCLE
G6
SDDAT3/SMDATA4
G5
GND_SD
CB1410BFB0 LFBGA 144P
PCMCIA@
1
C727
2
0.1U_0402_16V4Z
PCMCIA@
C
+3VS+S1_VCC
N12
N13
M13
VCCD0#
VCCD1#
M12
VPPD1
VPPD0
A7
VCCA2
G13
VCCA1
B4
VCC10
C8
VCC9
PCI Interface
SD/MMC/MS/SM
GND1D3GND2H2GND3L4GND4M8GND5
GND6
F12
K11
CB1410 P/N: SA014100310
C
D
G1
K2
N4
F3
L6
L9
H11
D12
VCC2
VCC3
VCC4
VCC1
VCC5
VCC6
VCC7
VCC8
B2
CAD31/D10
C3
CAD30/D9
B3
CAD29/D1
A3
CAD28/D8
C4
CAD27/D0
A6
CAD26/A0
D7
CAD25/A1
C7
CAD24/A2
A8
CAD23/A3
D8
CAD22/A4
A9
CAD21/A5
C9
CAD20/A6
A10
CAD19/A25
B10
CAD18/A7
D10
CAD17/A24
E12
CAD16/A17
CAD14/A9
CAD12/A11
CAD11/OE#
CAD9/A10
CAD8/D15
CAD7/D7
CAD6/D13
CAD5/D6
CAD4/D12
CAD3/D5
CAD2/D11
CAD1/D4
CAD0/D3
CCBE2#/A12
CCBE1#/A8
CIRDY#/A15
CPAR/A13
CGNT#/WE#
CCLK/A16
SPKROUT
CVS2/VS2#
CVS1/VS1
CRSV3/D2
CRSV2/A18
CRSV1/D14
MSINS#
SMBSY#
SMCD#
SMWP#
SMCE#
F10
E13
F13
F11
G10
G11
G12
H12
H10
J11
J12
K13
J10
K10
K12
L13
B7
A11
E11
H13
B9
B11
A12
A13
B13
C12
C13
A5
D13
B8
C11
B12
C5
D5
D11
D6
M9
B5
A4
L12
D9
C6
A2
E10
J13
H7
J8
H8
E9
G9
H9
G8
F9
H6
J7
J6
J5
D
CAD15/IOWR#
CAD13/IORD#
CAD10/CE2#
CCBE3#/REG#
CCBE0#/CE1#
CARDBUS
CRST#/RESET
CFRAME#/A23
CTRDY#/A22
CDEVSEL#/A21
CSTOP#/A20
CPERR#/A14
CSERR#/WAIT#
CREQ#/INPACK#
CSTSCHG/BVD1_STSCHG#
CCLKRUN#/WP_IOIS16#
CBLOCK#/A19
CINT#/READY_IREQ#
CAUDIO/BVD2_SPKR#
CCD2#/CD2#
CCD1#/CD1#
MSPWREN#/SMPWREN#
MSBS/SMDATA1
MSCLK/SMRE#
MSDATA0/SMDATA2
MSDATA1/SMDATA6
MSDATA2/SMDATA5
MSDATA3/SMDATA3
GND7
GND8
B6
C10
10/17 : FootPrint : SA007140B10
BOM : SA014100310
S1_D10
S1_D9
S1_D1
S1_D8
S1_D0
S1_A0
S1_A1
S1_A2
S1_A3
S1_A4
S1_A5
S1_A6
S1_A25
S1_A7
S1_A24
S1_A17
S1_IOWR#
S1_A9
S1_IORD#
S1_A11
S1_OE#
S1_CE2#
S1_A10
S1_D15
S1_D7
S1_D13
S1_D6
S1_D12
S1_D5
S1_D11
S1_D4
S1_D3
S1_REG#
S1_A12
S1_A8
S1_CE1#
S1_RST
S1_A23
S1_A15
S1_A22
S1_A21
S1_A20
S1_A14
S1_WAIT#
S1_A13
S1_INPACK#
S1_WE#
S1_BVD1
S1_WP
S1_A19
S1_RDY#
PCM_SPK#
S1_BVD2
S1_CD2#
S1_CD1#
S1_VS2
S1_VS1
S1_D2
S1_A18
S1_D14
Security Classification
Issued Date
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
IDSEL:AD20
(PIRQC#/D#,
GNT#2,
REQ#2)
1 2
R642 33_0402_5%
PCMCIA@
C713
10P_0402_50V8K
PCMCIA@
S1_CD1#
2
C718
10P_0402_50V8K
PCMCIA@
1
E
PCMCIA Power Control
+5VS
W=40mil
C707
W=40mil
C709
0.1U_0402_16V4Z
PCMCIA@
+S1_VCC
C711
PCMCIA@
+S1_VPP
C714
PCMCIA@
1 2
R649 43K_0402_5%PCMCIA@
R650 43K_0402_5%PCMCIA@
1 2
R651 43K_0402_5%PCMCIA@
1 2
R652 43K_0402_5%PCMCIA@
1 2
R653 43K_0402_5%PCMCIA@
Deciphered Date
1
0.1U_0402_16V4Z
2
PCMCIA@
1
2
1
2
1
2
12
+3VS
12
S1_A[0..25]
S1_D[0..15]
C712
C715
R640
10K_0402_5%
PCMCIA@
1
2
1
2
1
C706
10U_0805_10V4Z
10U_0805_10V4Z
S1_A16
PCM_SPK# <38>
2
1
2006/08/04 2006/10/06
E
2
PCMCIA@
1
C708
2
PCMCIA@
S1_A[0..25]
S1_D[0..15]
10U_0805_10V4Z
10U_0805_10V4Z
S1_OE#
S1_WP
S1_RST
S1_CE1#
S1_CE2#
Compal Secret Data
F
U43
9
12V
5
5V
6
5V
3
3.3V
4
3.3V
0.1U_0402_16V4Z
PCMCIA@
0.1U_0402_16V4Z
PCMCIA@
+S1_VCC
+S1_VCC
+S1_VCC
+S1_VCC
+S1_VCC
F
G
VCCD0
VCCD1
VPPD0
VPPD1
GND
SHDN
CP2211FD3_SSOP16
7
16
PCMCIA@
VCC
VCC
VCC
VPP
+S1_VCC
40mil
13
12
11
10
VCCD0#
1
VCCD1#
2
VPPD0
15
VPPD1
14
8
OC
40mil
+S1_VPP
1
C705
0.1U_0402_16V4Z
2
PCMCIA@
VCCD0#
VCCD1#
1 2
R638 10K_0402_5%PCMCIA@
1 2
R639 10K_0402_5%PCMCIA@
PCMCIA Socket
JP40
1
S1_D3
S1_D4
S1_D5
S1_D6
S1_D7
S1_CE1#
S1_A10
S1_OE#
S1_A11
S1_A9
S1_A8
S1_A13
S1_A14
S1_WE#
S1_RDY#
+S1_VPP +S1_VPP
S1_A16
S1_A15
S1_A12
S1_A7 S1_A25
S1_A6 S1_VS2
S1_A5 S1_RST
S1_A4 S1_WAIT#
S1_A3 S1_INPACK#
S1_A2 S1_REG#
S1_A1
S1_A0
S1_D0 S1_D8
S1_D1 S1_D9
S1_D2 S1_D10
Title
Size Document Number Rev
Custom
Date: Sheet
G
GND
2
D3
3
D4
4
D5
5
D6
6
D7
7
CE1#
8
A10
9
OE#
10
A11
11
A9
12
A8
13
A13
14
A14
15
WE#
16
IREQ#
17
VCC
18
VPP1
19
A16
20
A15
21
A12
22
A7
23
A6
24
A5
25
A4
26
A3
27
A2
28
A1
29
A0
30
D0
31
D1
32
D2
33
IOIS16#
34
GND
69
GND
70
GND
FOX_WZ21131-G2-8F_LT
PCMCIA@
Compal Electronics, Inc.
PCMCIA_ENE CB1410
IFTXX LA-3541P
GND
CD1#
CE2#
VS1#
IORD#
IOWR#
VCC
VPP2
VS2#
RESET
WAIT#
INPACK#
REG#
SPKR#
STSCHG#
CD2#
GND
GND
GND
35
36
37
D11
38
D12
39
D13
40
D14
41
D15
42
43
44
45
46
A17
47
A18
48
A19
49
A20
50
A21
51
52
53
A22
54
A23
55
A24
56
A25
57
58
59
60
61
62
63
64
D8
65
D9
66
D10
67
68
71
72
H
S1_CD1#
S1_D11
S1_D12
S1_D13
S1_D14
S1_D15
S1_CE2#
S1_VS1
S1_IORD#
S1_IOWR#
S1_A17
S1_A18
S1_A19
S1_A20
S1_A21
S1_A22
S1_A23
S1_A24
S1_BVD2
S1_BVD1
S1_CD2#S1_WP
26 52Wednesday, November 01, 2006
H
+S1_VCC+S1_VCC
0.1
of
5
D D
C C
4
3
2
1
B B
A A
Title
<Title>
Size Document Number Rev
<Doc> <RevCode>
A
of
5
4
3
Dat e: Sheet
2
27 52Wednesday, November 01, 2006
1
5
1
2
1 2
1 2
C276
270P_0402_50V7K
R226
56.2_0603_1%
R233
56.2_0603_1%
125
126
127
11
12
14
15
17
18
19
36
37
38
39
40
42
43
44
46
47
48
49
50
51
52
53
21
35
45
33
23
25
24
29
26
30
31
124
123
121
119
71
117
70
115
116
69
66
111
107
103
102
99
97
U23
AD31
AD30
AD29
1
AD28
2
AD27
3
AD26
5
AD25
6
AD24
9
AD23
AD22
AD21
AD20
AD19
AD18
AD17
AD16
AD15
AD14
AD13
AD12
AD11
AD10
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
7
C/BE3#
C/BE2#
C/BE1#
C/BE0#
PAR
FRAME#
TRDY#
IRDY#
STOP#
DEVSEL#
8
IDSEL
PERR#
SERR#
REQ#
GNT#
PCICLK
PCIRST#
GBRST#
CLKRUN#
PME#
INTA#
INTB#
HWSPND#
TEST
AGND
AGND
AGND
AGND
AGND
NC
R5C832_TQFP128~D
832@
12
R224
5.1K_0603_1%
Z3008
R227
1 2
56.2_0603_1%
R234
1 2
56.2_0603_1%
R5C832
2
1
PCI_AD[0..31]<20,26>
U23
D D
R5C833
833@
PCI_CBE#3<20,26>
PCI_CBE#2<20,26>
PCI_CBE#1<20,26>
PCI_CBE#0<20,26>
PCI_PAR<20,26>
PCI_FRAME#<20,26>
PCI_TRDY#<20,26>
PCI_IRDY#<20,26>
PCI_AD22 CBS_IDSEL
C C
1 2
R207 100_0402_5%
Layout Note: S h i e l d G ND for CLK_PCI_1394
PM_CLKRUN#<22,29,34,41>
SUSP#<17,33,34,41,43,48,49,50>
B B
PCI_STOP#<20,26>
PCI_DEVSEL#<20,26>
PCI_PERR#<20,26>
PCI_SERR#<20,26>
PCI_REQ#0<20>
PCI_GNT#0<20>
CLK_PCI_1394<16>
PCI_RST#<20,24,26,33,34,36,41>
R212 10K_0402_5%@
1 2
R214 0_0402_5%
1 2
R5_PME#<34>
PCI_PIRQG#<20>
PCI_PIRQH#<20>
1 2
+3VS
R216 10K_0402_5%@
1 2
R218 0_0402_5%
PCI_AD31
PCI_AD30
PCI_AD29
PCI_AD28
PCI_AD27
PCI_AD26
PCI_AD25
PCI_AD24
PCI_AD23
PCI_AD22
PCI_AD21
PCI_AD20
PCI_AD19
PCI_AD18
PCI_AD17
PCI_AD16
PCI_AD15
PCI_AD14
PCI_AD13
PCI_AD12
PCI_AD11
PCI_AD10
PCI_AD9
PCI_AD8
PCI_AD7
PCI_AD6
PCI_AD5
PCI_AD4
PCI_AD3
PCI_AD2
PCI_AD1
PCI_AD0
PCI_CBE#3
PCI_CBE#2
PCI_CBE#1
PCI_CBE#0
PCI_PAR
PCI_FRAME#
PCI_TRDY#
PCI_IRDY#
PCI_STOP#
PCI_DEVSEL#
PCI_PERR#
PCI_SERR#
PCI_REQ#0
PCI_GNT#0
CBS_GRST#
R5_PME#
Layout Not e: Place close to R5C832
CLK_PCI_1394
12
R225
10_0402_5%
@
2
C277
4.7P_0402_50V8C
1
@
A A
+3VS
12
R228
100K_0402_5%
CBS_GRST#
1
C278
1U_0603_10V6K
2
IEEE1394_TPBN0
IEEE1394_TPBP0
IEEE1394_TPAN0
IEEE1394_TPAP0
IEEE1394_TPBIAS0
C279
0.01U_0402_16V7K
2
1
4
AVCC_PHY3V
AVCC_PHY3V
AVCC_PHY3V
AVCC_PHY3V
UDIO0/SERIRQ#
C280
0.33U_0603_16V4Z
VCC_PCI3V
VCC_PCI3V
VCC_PCI3V
VCC_PCI3V
VCC_PCI3V
VCC_PCI3V
VCC_RIN
VCC_ROUT
VCC_ROUT
VCC_ROUT
VCC_ROUT
VCC_ROUT
VCC_3V
VCC_MD3V
TPBIAS0
TPAP0
TPAN0
TPBP0
TPBN0
MDIO00
MDIO01
MDIO02
MDIO03
MDIO04
MDIO05
MDIO06
MDIO07
MDIO08
MDIO09
MDIO10
MDIO11
MDIO12
MDIO13
MDIO14
MDIO15
MDIO16
MDIO17
MDIO18
MDIO19
MSEN
XDEN
REXT
VREF
UDIO1
UDIO2
UDIO3
UDIO4
UDIO5
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
10
20
27
32
41
128
61
16
34
64
114
120
67
86
98
106
110
112
113
109
108
105
104
80
79
78
77
76
75
74
73
88
84
82
81
93
90
91
89
92
87
85
83
58
55
94
XI
95
XO
96
FIL0
101
100
72
60
56
65
59
57
4
13
22
28
54
62
63
68
118
122
+3VS
+3V_PHY
IEEE1394_TPBIAS0
IEEE1394_TPAP0
IEEE1394_TPAN0
IEEE1394_TPBP0
IEEE1394_TPBN0
SDCD#_XDCD0#
MSCD#_XDCD1
SDWP#_XDRB#
SDPWR0_MSPW R _XDPW R
SDCMD_MSBS
SDCLK_MSCLK
SDDATA0_MSDATA0
SDDATA1_MSDATA1
SDDATA2_MSDATA2
SDDATA3_MSDATA3
MSEN
XDEN
R5C832XI
R5C832XO
SERIRQ
TP_UDIO1
TP_UDIO2
UDIO3
UDIO4
UDIO5
Layout Note: Shield GND for
CBS_CCLK_INTERNAL and CBS_CCLK
SDPWR0_MSPW R _XDPW R
L20
1
1
4
4
WCM2012F2SF-121T04_0805
@
R229 0_0402_5%
1 2
R230 0_0402_5%
1 2
R231 0_0402_5%
1 2
R232 0_0402_5%
1 2
L21
1
1
4
4
WCM2012F2SF-121T04_0805
@
2
2
3
3
2
2
3
3
3
1
1
C251
C252
2
2
10U_0805_4VAM
0.01U_0402_16V7K
1
1
C261
2
2
0.01U_0402_16V7K
SDCD#_XDCD0# <29>
MSCD#_XDCD1 <29>
SDWP#_XDRB# <29>
SDCMD_MSBS <29>
SDCLK_MSCLK <29>
SDDATA0_MSDATA0 <29>
SDDATA1_MSDATA1 <29>
SDDATA2_MSDATA2 <29>
SDDATA3_MSDATA3 <29>
Layout Note: C268,C270,R125 Place close to R5C832
and Shield GND for FIL0,REXT,VREF
1 2
C268
0.01U_0402_16V7K
SERIR Q <22, 2 6 , 2 9,34,36,41>
T4PAD
T5PAD
+3VS
1
C275
0.1U_0402_16V4Z
2
IEEE1394TPA+/- and IEEE1394TPB+/Same Wire Length
Layout Note: Shield GND for
IEEE1394_TPA and TPB
2
1
U48
3
VIN
VOUT
4
VIN/CE
VOUT
2
GND
RT9701-PB_SOT23-5
+3VS
C262
10U_0805_4VAM
C270
0.01U_0402_16V7K
1
5
1 2
1
2
R215
10K_0603_1%
C272
1U_0603_10V4Z
1
1
C258
C257
0.01U_0402_16V7K
+3VS
C259
2
2
0.01U_0402_16V7K
1 2
BLM21A601SPT_0805
Layout Not e: Place close to R5C832
and Shield GND for SDCLK_MSCLK
C269
1 2
15P_0603_50V8J
C271
1 2
15P_0603_50V8J
40mil
+VCC_3IN1
1
R656
100K_0402_5%
2
1 2
JP25
1
TPB-
GND
2
TPB+
GND
3
TPA-
GND
4
TPA+
GND
SUYIN_020115FB004S512ZL
ME@
+3VS
1
C260
2
0.47U_0603_16V4Z
0.47U_0603_16V4Z
L19
R5C832XI
X3
24.576MHz_16P_1BG24576CKIA
1 2
R5C832XO
1
C273
2
10U_1206_6.3V6M
5
6
7
8
2
1
1
C253
C254
2
2
0.1U_0402_16V4Z
0.01U_0402_16V7K
1
2
1
1
C263
C264
2
2
0.1U_0402_16V4Z
22U_0805_6.3V6M
Layout Not e: Place close to R5C832
and Shield GND for SD_CLK
1
C274
2
0.1U_0402_16V4Z
1
2
C265
C255
0.01U_0402_16V7K
+3V_PHY
1
C266
2
0.1U_0402_16V4Z
SDDATA1_MSDATA1
SDDATA2_MSDATA2
+5VS+VCC_3IN1
1
C256
2
1
2
1000P_0402_50V7K
1 2
R221 10K_0402_5%@
SDCD#_XDCD0#
10U_0805_4VAM
C267
1000P_0402_50V7K
2N7002_SOT23
1
SD,MMC,MS muti-function pin define
MDIO
PIN Name
MDIO00
SD Card
PIN Name
SDCD#
MMC Card
PIN Name
MMCCD#
MDIO01
MDIO02
MDIO03
MDIO04
MDIO05
MDIO06
SDWP#
SDPWR0
SDPWR1
SDLED#
MMCPWR
MMCLED#
MDIO07
MDIO08
SDCCMD
MDIO09 SDCCLK
MDIO10
MDIO11
MDIO12
MDIO13
SDCDAT0
SDCDAT1
SDCDAT2
SDCDAT3
MMCCMD
MMCCLK
MMCDAT
MDIO14
MDIO15
MDIO16
MDIO17
MDIO18
MDIO19
Function set pin define
Pull-up
R217 0_0402_5%
12
D
S
1 3
R219 0_0402_5%
Q27
G
2
@
2N7002_SOT23
13
D
Q30
2
2N7002_SOT23
G
@
S
1 3
Q28
@
MSEN XDENUDIO3 UDIO4
Pull-upPull-up Enable
Pull-low
MSEN
R208 10K_0402_5%
UDIO3
UDIO4
UDIO5
XDEN
D
1 2
R209 10K_0402_5%
1 2
R210 10K_0402_5%
1 2
R211 100K_0402_5%
1 2
R213 10K_0402_5%
1 2
Solve MS Duo Adaptor short problem
SD_MSDATA1
12
S
G
2
SD_MSDATA2
MS Card
PIN Name
MSCD#
MSWR
MSLED#
MSEXTCK
MSBS
MSCCLK
MSCDAT0
MSCDAT1
MSCDAT2
MSCDAT3
Function
SD,MS,MMC Card
+3VS
SD_MSDATA1 <29>
SD_MSDATA2 <29>
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETAR Y PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INF ORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITH OUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
3
2006/08/04 2006/10/06
Compal Secret Data
Deciphered Date
2
Title
Size Document Number Rev
Custom
Date: Sheet
Compal Electronics, Inc.
1394+3 in 1 Card
XXXXX LA-3541P
1
28 52Wednesday, November 01, 2006
of
0.1
5
4
3
2
1
3 in 1 Card Reader
D D
C C
+VCC_3IN1
SDDATA0_MSDATA0<28>
SD_MSDATA1<28>
SD_MSDATA2<28>
SDDATA3_MSDATA3<28>
SDCLK_MSCLK<28>
SDWP#_XDRB#<28>
SDCMD_MSBS<28>
SDCD#_XDCD0#<28>
SDDATA1_MSDATA1<28>
MSCD#_XDCD1<28>
SDDATA2_MSDATA2<28>
SDDATA0_MSDATA0
SD_MSDATA1
SD_MSDATA2
SDDATA3_MSDATA3
SDWP#_XDRB#
SDCMD_MSBS
SDCD#_XDCD0#
SDDATA1_MSDATA1
MSCD#_XDCD1
SDDATA0_MSDATA0
SDCMD_MSBS
SDDATA3_MSDATA3
SDDATA2_MSDATA2
R198 22_0402_5%
1 2
R199 22_0402_5%
1 2
SDCLKSDCLK_MSCLK
MSCLKSDCLK_MSCLK
JP24
6
VDD_SD
9
DAT0_SD
10
DAT1_SD
2
DAT2_SD
3
CD/DAT3_SD
7
CLK_SD
11
WP_SD
4
CMD_SD
1
CD_SD
5
VSS_SD
8
VSS_SD
19
VCC_MS
13
VCC_MS
14
SCLK_MS
16
INS_MS
18
SDIO_MS
20
BS_MS
15
RESERVED_MS
17
RESERVED_MS
21
VSS_MS
12
VSS_MS
22
GND
23
GND
PROCO_MDR019-C0-1202
ME@
For A30 TPM Conn. For C38
+3VALW
U22
LAD0
LAD1
LAD2
LAD3
LCLK
LFRAME#
LRESET#
SERIRQ
CLKRUN#
PP
+3VS
5
19
10
VSB
VDD24VDD
VDD
TESTB1/BADD
TPM
SLB 9635 TT 1.1
GND4GND11GND18GND
25
SUS_STAT#
28
LPCPD#
9
TPM_TEST1
8
TEST1
XTALO
XTALI
GPIO2
GPIO
SLB-9635-TT-1.2_TSSOP28
TPM@
TPM_XTALO
14
TPM_XTALI
13
2
6
1
NC
3
NC
12
NC
TPM_XTALI
TPM_XTALO
+3VS
12
0 = 02Eh
1 = 04Eh
*
SUS_STAT# <22,41>
R202 0_0402_5%
1 2
Base I/O Address
R201
4.7K_0402_5%
TPM@
12
R203
4.7K_0402_5%
@
12/9 Modified to @
C248
TPM@
18P_0402_50V8J
1 2
TPM@
R206
12
10M_0402_5%
X2
1
IN
4
OUT
32.768KHZ_12.5P_1TJS125BJ2A251TPM@
1 2
C250
TPM@
18P_0402_50V8J
2
NC
3
NC
Note: 4/17 Modified X1 pn to SJ100001U00
+3VS +3VS
SUS_STAT#
SERIRQ
TPM_TEST1
PLT_RST#
PM_CLKRUN#
+3VS
1
C739
10U_0805_10V4Z
2
JP47
1 2
3 4
5 6
7 8
9 10
11 12
13 14
15 16
17 18
19 20
ACES_88019-2000
ME@
LPC_AD0
LPC_AD1
LPC_FRAME#
CLK_PCI_TPM
LPC_AD2
LPC_AD3
Place this cap close to pin 6 and pin 9
TPM 1.2
LPC_AD0<21,34,36,41>
LPC_AD1<21,34,36,41>
LPC_AD2<21,34,36,41>
LPC_AD3<21,34,36,41>
B B
A A
+3VS
CLK_PCI_TPM<16>
LPC_FRAME#<21,34,36,41>
PLT_RST#<8,20,22,30,41>
SERIRQ<22,26,28,34,36,41>
PM_CLKRUN#<22,28,34,41>
1 2
R204 4.7K_0402_5%TPM@
LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
CLK_PCI_TPM
LPC_FRAME#
PLT_RST#
SERIRQ
PM_CLKRUN#
CLK_PCI_TPM
26
23
20
17
21
22
16
27
15
7
R205
10_0402_5%@
1 2
2
C249
15P_0402_50V8J@
1
Security Classification
Issued Date
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2006/08/04 2006/10/06
Compal Secret Data
Deciphered Date
Title
Size Document Number Rev
Custom
2
Date: Sheet
Compal Electronics, Inc.
INDICATE LED
XXXXX LA-3541P
1
29 52Wednesday, November 01, 2006
0.1
of
5
+3VALW
L11
KC FBM-L11-201209-221LMAT_0805
Layout Notice : Filter place as close
D D
chip as possible.
+2.5V_LAN
C C
B B
A A
L12
FBM-L11-160808-601LMT_0603
FBM-L11-160808-601LMT_0603
FBM-L11-160808-601LMT_0603
+1.2V_LAN
FBM-L11-160808-601LMT_0603
FBM-L11-160808-601LMT_0603
FBM-L11-160808-601LMT_0603
FBM-L11-160808-601LMT_0603
12
L13
12
0.1U_0402_16V4Z
L14
12
L15
4.7U_0805_6.3V6K
L16
4.7U_0805_6.3V6K
L17
4.7U_0805_6.3V6K
L18
4.7U_0805_6.3V6K
No CIS Symbol
+XTALVDD
2
C220
0.1U_0402_16V4Z
1
NA
2
C221
1
+LAN_BIASVDD
1
2
12
2
C229
1
12
2
C233
1
12
2
C237
1
12
1
C239
2
close to pins 38, 45, and 52
2
C222
0.1U_0402_16V4Z
1
C226
0.1U_0402_16V4Z
+AVDDL
2
C230
0.1U_0402_16V4Z
1
+GPHY_PLLVDD
2
C234
0.1U_0402_16V4Z
1
+PCIE_PLLVDD
2
C238
0.1U_0402_16V4Z
1
+PCIE_VDD
2
C240
0.1U_0402_16V4Z
1
27P_0402_50V8J
+LAN_AVDD
2
C223
0.1U_0402_16V4Z
1
(CLKREQ#) and (ENERGY_DET) are
only supported in BCM5787M
R192 200_0603_1%
Y1
1 2
25MHZ_20PF_6X25000017
2
C241
1
1 2
PCIE_ITX_C_PRX_N2<22>
PCIE_ITX_C_PRX_P2<22>
PCIE_PTX_C_IRX_N2<22>
PCIE_PTX_C_IRX_P2<22>
ICH_PCIE_WAKE#<22,32,33>
12
4
CLK_PCIE_LAN#<16>
CLK_PCIE_LAN<16>
R189 4.7K_0402_5%@
R190 4.7K_0402_5%@
2
C242
27P_0402_50V8J
1
Layout Notice : Place as close
chip as possible.
2
2
C202
C203
C204
1
1
4.7U_0805_10V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
R177 10K_0402_5%
1 2
+3VS
+3VS
+3V_LAN
0.1U_0402_10V7K
0.1U_0402_10V7K
PLT_RST#<8,20,22,29,41>
1 2
R179 1K_0402_5%
1 2
R180 1K_0402_5%
1 2
R183 1K_0402_5%
+GPHY_PLLVDD
C231
1 2
C232
1 2
Change R311,R312 from 4.7k to 47k
R186 47K_0402_5%@
+3V_LAN
+3V_LAN
1 2
1 2
XTALO
XTALI
1 2
R187 47K_0402_5%@
1 2
+3V_LAN
1 2
R188 0_0402_5%
1 2
R191 0_0402_5%@
+3V_LAN
2
2
C206
C205
1
1
0.1U_0402_16V4Z
0.1U_0402_16V4Z
PCIE_MRX_C_LTX_N2
PCIE_MRX_C_LTX_P2
LAN_WP
GPIO2
XTALI
XTALO
3
U20
28
PCIE_REFCLK_N
29
PCIE_REFCLK_P
11
CLKREQ
3
LOW PWR
53
VMAIN_PRSNT
54
VAUX_PRSNT
59
ENERGY_DET
35
GPHY_PLLVDD
32
PCIE_RXD_N
31
PCIE_RXD_P
25
PCIE_TXD_N
26
PCIE_TXD_P
10
PERST
12
WAKE
58
SMB_CLK
57
SMB_DATA
4
GPIO_0(SERIAL_DO)
7
GPIO_1(SERIAL_DI)
8
GPIO_2
9
UART_MODE
21
XTALI
22
XTALO
16
REG_GND
24
PCIE_GND
5906@
TRD0_N
TRD0_P
TRD1_N
TRD1_P
TRD2_N
TRD2_P
TRD3_N
TRD3_P
LINKLED
SPD100LED
SPD1000LED
TRAFFICLED
SCLK(EECLK)
SO(EEDATA)
REGCTL12
REGCTL25
RDAC
XTALVDD
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDP
VDDP
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
BIASVDD
PCIE_PLLVDD
PCIE_VDD
PCIE_VDD
AVDD
AVDD
AVDD
AVDDL
AVDDL
AVDDL
AVDDL
GND
69
U20
5787M
5787@
LAN_TX0-
41
LAN_TX0+
40
LAN_RX1-
42
LAN_RX1+
43
LAN_TX2-
48
LAN_TX2+
47
LAN_TX3-
49
LAN_TX3+
50
R181 0_0402_5%
2
R182 0_0402_5% @
1
R184 0_0402_5%@
67
66
65
63
SI
64
62
CS
14
18
37
R185 1K_0402_5%
23
6
15
19
56
61
17
68
5
13
20
34
55
60
+LAN_BIASVDD
36
30
27
33
38
45
52
39
44
46
51
1 2
1 2
1 2
LAN_CLK
SI
LAN_DATA
CS#
CTL12
CTL25
1 2
+XTALVDD
+3V_LAN
+2.5V_LAN
+1.2V_LAN
+PCIE_PLLVDD
+PCIE_VDD
+LAN_AVDD
+AVDDL
R193
4.7K_0402_5%
LAN_WP
LAN_CLK
LAN_DATA
LAN_TX0- <31>
LAN_TX0+ <31>
LAN_RX1- <31>
LAN_RX1+ <31>
LAN_TX2- <31>
LAN_TX2+ <31>
LAN_TX3- <31>
LAN_TX3+ <31>
9/14 change from
1.24K to 1K (By
broadcom James)
12
12
R194
4.7K_0402_5%
+3V_LAN
2
LINKLED# <31>
ACTIVITY# <31>
1 2
C243
0.1U_0402_16V4Z
U21
8
VCC
7
WP
6
SCL
5
SDA
AT24C02_SO8
Layout Notice : 1.2V filter. Place as close
chip as possible.
+1.2V_LAN
2
2
2
C210
C211
1
4.7U_0805_6.3V6K
C212
1
1
0.1U_0402_16V4Z
0.1U_0402_16V4Z
Add R346
CTL12
CTL25
Notice : 4.7u 6.3V
capactor Thickness
1.25mm
Layout Notice : Filter
place as close chip
as possible.
1
A0
2
A1
3
NC
4
GND
2
2
C215
C214
C213
1
1
0.1U_0402_16V4Z
0.1U_0402_16V4Z
+3V_LAN
12
R178
0.015_2512_1%
Q25
MMJT9435T1G_SOT223
1
2 3
4
0.1U_0402_16V4Z
+3V_LAN
41
Q26
MBT35200MT1G_TSOP6
3
C244
2
1
LAN_CLK
1 2
R195 4.7K_0402_5%
SI
R196 4.7K_0402_5%5787@
CS#
1 2
R197 4.7K_0402_5%5787@
1
2
1
0.1U_0402_16V4Z
C224 0.1U_0402_16V4Z
C225 4.7U_0805_10V4Z
C216
0.1U_0402_16V4Z
1 2
1 2
2
2
C217
C218
1
1
0.1U_0402_16V4Z
+1.2V_LAN
1
2
1 2
1 2
22U_0805_6.3V6M
2
1
+2.5V_LAN
C246
2
1
1
C228
10U_0805_10V4Z
2
0.1U_0402_16V4Z
C227
C235
0.1U_0402_16V4Z
C236
4.7U_0805_10V4Z
256
0.1U_0402_16V4Z
C245
12
2
2
C219
1
1
0.1U_0402_16V4Z
0.1U_0402_16V4Z
Security Classification
Issued Date
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2006/08/04 2006/10/06
Compal Secret Data
Deciphered Date
Title
Size Document Number Rev
Custom
2
Date: Sheet
BCM5787MKML
XXXXX LA-3541P
1
0.1
of
30 52Wednesday, November 01, 2006
5
+2.5V_LAN
4
3
2
1
Change L1 from SD013000080 to SM010005500
12
BLM18AG601SN1D_0603~D
C189 0.1U_0402_16V4Z
1 2
D D
L10
LAN_TX0+<30>
Change T2 from SP050002130 to SP050002140
T2
LAN_TX0+
1
TCT1
TD1+
1:1
2
MCT1
MX1+
24
23
MCT0
MDO0+
75_0402_5%
R163
12
LAN_TX0-
LAN_RX1+
LAN_RX1-
LAN_TX2+
LAN_TX2-
LAN_TX3+
LAN_TX3-
12
12
12
12
12
12
3
TD1-
4
TCT2
5
TD21+
6
TD2-
7
TCT3
8
TD3+
9
TD3-
10
TCT4
11
TD4+
12
TD4-
350u_24HST1041A-3-LF
5787@
LAN_TX0+
LAN_TX0-
TCT
TCT
LAN_RX1+
LAN_RX1-
C194
1 2
C196
1 2
C200
1 2
1:1
1:1
1:1
T3
1
RD+
2
RD-
3
CT
4
NC
5
NC
6
CT
7
TD+
TD-8TX-
350uH_NS0013LF
5906@
0.1U_0402_16V4Z@
0.1U_0402_16V4Z@
0.1U_0402_16V4Z
5906@
RX+
16
15
RX-
14
CT
13
NC
12
NC
11
CT
10
TX+
9
C190 0.1U_0402_16V4Z
1 2
C191 0.1U_0402_16V4Z
1 2
5787@
C192 0.1U_0402_16V4Z
1 2
5787@
C C
LAN_TX0-<30>
LAN_RX1+<30>
LAN_RX1-<30>
LAN_TX2+<30>
LAN_TX2-<30>
TCT
LAN_TX3+<30>
LAN_TX3-<30>
Change T1 from SP050001210 to SP050001210
B B
Change C468,C470,C473,C474,C475,C476 from 0.01uF to 0.1uF
LAN_TX3-
R168 49.9_0402_1%@
LAN_TX3+
R169 49.9_0402_1%@
LAN_TX2-
R171 49.9_0402_1%@
LAN_TX2+
R172 49.9_0402_1%@
LAN_RX1-
R173 49.9_0402_1%5906@
LAN_RX1+
R174 49.9_0402_1%5906@
MX1MCT2
MX2+
MX2MCT3
MX3+
MX3MCT4
MX4+
MX4-
MDO0+
MDO0-
MCT0
MCT1
MDO1+
MDO1-
MDO0-
22
MCT1
21
MDO1+
20
MDO1-
19
18
MDO2+
17
MDO2-
16
15
MDO3+
14
MDO3-
13
75_0402_5%
75_0402_5% 5787@
75_0402_5% 5787@
R164
12
R165
12
RJ45_PR
R166
12
Lan Conn.
12
ACTIVITY#<30>
ACTIVITY#
C193 68P_0402_50V8K
R167 300_0402_5%
LINKLED#<30>
1 2
LINKLED#
+3V_LAN
10mil
10mil
1 2
R170 300_0402_5%
+3V_LAN
12
C195 68P_0402_50V8K
RJ45_PR
MDO3MDO3+
MDO1MDO2MDO2+
MDO1+
MDO0MDO0+
JP23
12
Amber LED+
11
Amber LED-
8
PR4-
7
PR4+
6
PR2-
5
PR3-
4
PR3+
3
PR2+
2
PR1-
1
PR1+
10
Green LED-
9
Green LED+
TYCO_3-440470-4
ME@
C197
1 2
1000P_1206_2KV7K
C198
SHLD2
SHLD1
SHLD2
SHLD1
0.1U_0402_16V4Z
1
1
2
2
16
15
14
13
LANGND
C199
4.7U_0805_10V4Z
A A
LAN_TX0-
LAN_TX0+
R175 49.9_0402_1%5906@
R176 49.9_0402_1%5906@
12
12
near LAN controller
5
C201
1 2
0.1U_0402_16V4Z
5906@
4
Security Classification
Issued Date
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2006/08/04 2006/10/06
Compal Secret Data
Deciphered Date
2
Title
Size Document Number Rev
Custom
Date: Sheet
Compal Electronics, Inc.
LAN CONTROLLER
XXXXX LA-3541P
1
of
31 52Wednesday, November 01, 2006
0.1
A
B
C
D
E
NAND mini Card(Robson support)
+1.5VS+3VS
1
1 1
2 2
C175
0.01U_0402_16V7K
2
ROBSON@
+3VS
CLK_PCIE_NAND#<16>
CLK_PCIE_NAND<16>
PCIE_PTX_C_IRX_N4<22>
PCIE_PTX_C_IRX_P4<22>
PCIE_ITX_C_PRX_N4<22>
PCIE_ITX_C_PRX_P4<22>
1
C176
0.1U_0402_16V4Z
2
ROBSON@
ROBSON@
ROB_CLKREQ#
1 2
R660 10K_0402_5%
1
C177
4.7U_0805_10V4Z
2
ROBSON@
JP20
1
1
3
3
5
5
7
7
9
9
11
11
13
13
15
15
17
17
19
19
21
21
23
23
25
25
27
27
29
29
31
31
33
33
35
35
37
37
39
39
41
41
43
43
45
45
47
47
49
49
51
51
53
GND1
FOX_AS0B226-S56N-7F
ME@
GND2
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
1
2
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
C178
4.7U_0805_10V4Z
ROBSON@
+1.5VS
+3VS
1
C179
0.01U_0402_16V7K
2
ROBSON@
PLT_RST_BUF#
1
C180
0.1U_0402_16V4Z
2
ROBSON@
PLT_RST_BUF# <17,20>
Mini-Express Card for 3G Or TV Tuner
+3VS +3VALW
1
C169
4.7U_0805_10V4Z
2
ICH_PCIE_W AKE#<22,30,33>
+3VS
CLK_PCIE_3G#<16>
CLK_PCIE_3G<16>
PCIE_PTX_C_IRX_N5<22>
PCIE_PTX_C_IRX_P5<22>
PCIE_ITX_C_PRX_N5<22>
PCIE_ITX_C_PRX_P5<22>
2005/09/27 modified.
Base on OPTION GTM351E Datasheet Rev0.1
Vcc 3.3V +/- 8%
Peak Icc 2750mA
with max supply droop 50mA
Average Icc 1000mA
1
C170
0.1U_0402_16V4Z
2
ICH_PCIE_W AKE#
1 2
R661 10K_0402_5%
3G_CLKREQ#
+1.5VS
1
C171
4.7U_0805_10V4Z
2
JP19
1
1
3
3
5
5
7
7
9
9
11
11
13
13
15
15
17
17
19
19
21
21
23
23
25
25
27
27
29
29
31
31
33
33
35
35
37
37
39
39
41
41
43
43
45
45
47
47
49
49
51
51
53
GND1
GND2
FOX_AS0B226-S56N-7F
ME@
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
1
C172
0.1U_0402_16V4Z
2
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
(WWAN_LED#)
44
46
48
50
52
54
1
C173
0.1U_0402_16V4Z
2
MINI2_OFF#
PLT_RST_BUF#
ICH_SMBCLK
ICH_SMBDATA
10K_0402_5%
MINI2_OFF#
2N7002_SOT23
+3VALW
R737
Q50
1
C174
0.1U_0402_16V4Z
2
+3VS
12
13
D
S
+3VS
+1.5VS
USB20_N1 <22>
USB20_P1 <22>
3G_ON#
2
G
3G_ON# <34>
Mini-Express Card for WLAN
***
ICH_PCIE_WAKE#<22,30,33>
WLAN_ACTIVE<36>
BT_ACTIVE<36>
WLAN_CLKREQ#<16>
3 3
4 4
0.01U_0402_16V7K
CLK_PCIE_WLAN#<16>
CLK_PCIE_WLAN<16>
PCIE_PTX_C_IRX_N6<22>
PCIE_PTX_C_IRX_P6<22>
PCIE_ITX_C_PRX_N6<22>
PCIE_ITX_C_PRX_P6<22>
1
C181
2
C182
0.1U_0402_16V4Z
A
ICH_PCIE_W AKE#
WLAN_ACTIVE
BT_ACTIVE
WLAN_CLKREQ#
CLK_PCIE_WLAN#
CLK_PCIE_WLAN
1
4.7U_0805_10V4Z
2
+3VS +1.5VS
1
C183
2
JP22
1
1
3
3
5
5
7
7
9
9
11
11
13
13
15
15
17
17
19
19
21
21
23
23
25
25
27
27
29
29
31
31
33
33
35
35
37
37
39
39
41
41
43
43
45
45
47
47
49
49
51
51
53
GND1
FOX_AS0B226-S56N-7F
ME@
C184
0.01U_0402_16V7K
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
GND2
1
0.1U_0402_16V4Z
2
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
B
MINI_RF_OFF#
PLT_RST_BUF#
ICH_SMBCLK
ICH_SMBDATA
WLAN_LED#
R725
1 2
100K_0402_5%
1
C185
2
C186
4.7U_0805_10V4Z
+3VALW
ICH_SMBCLK <16,22,33>
ICH_SMBDATA <16,22,33>
USB20_N3 <22>
USB20_P3 <22>
WLAN_LED# <37,42>
+5VS
1
2
+1.5VS +3VS
MINI_RF_OFF#
2N7002_SOT23
+3VALW
1
C187
0.1U_0402_16V4Z
2
Security Classification
Issued Date
THIS SHEET OF EN GINEE RING D RAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2006/08/05 2007/08/05
R726
10K_0402_5%
Q49
+3VS
12
13
D
RF_ON#
2
G
S
Compal Secret Data
Deciphered Date
RF_ON# <34>
D
Kill SWITCH
+3VALW
2
D23
DAN217_SC59
14W@
11223
SW2
1BS003-1211L_3P
14W@
3
1
3
Title
Mini-Card/3G/FeliCa/FP
Size Document Number Rev
Date: Sheet
+3VALW
R162
100K_0402_5%
14W@
1 2
KILL_SW#
Compal Electronics, Inc.
LA-3541P
E
KILL_SW# <34,37>
of
32 52Wednesday, November 01, 2006
0.1
A
B
C
D
E
New Card Power Switch
U16
CP_USB#
CP_PE#
SUSP#
SYSON
PCI_RST#
5
6
21
18
19
14
15
4
3
2
1
C156
10U_0805_10V4Z
2
NEWCARD@
3.3Vin1
3.3Vin2
3.3Vaux_in
1.5Vin1
1.5Vin2
CPUSB#
CPPE#
STBY#
SHDN#
SYSRST#
GND
11
3.3Vout1
3.3Vout2
Aux_out
1.5Vout1
1.5Vout2
RCLKEN
PERST#
NC11NC210NC312NC413NC5
24
+3VS
NEWCARD@
NEWCARD@
1
C155
10U_0805_10V4Z
2
NEWCARD@
+3VALW
+1.5VS
1 1
R151 100K_0402_5%
+3VALW
+3VS +1.5VS+3VALW
1
C154
10U_0805_10V4Z
2
NEWCARD@
2 2
1 2
R152 100K_0402_5%
1 2
SUSP#<17,28,34,41,43,48,49,50>
SYSON<34,43,48>
PCI_RST#<20,24,26,28,34,36,41>
60mils
7
8
40mil
20
40mil
16
17
23
OC#
RCLKEN1
22
PERST1#
9
TPS2231PWPR_PWP24
NEWCARD@
Update Footprint
+3VS_CARD1
+3VALW_CARD1
+1.5VS_CARD1
+3VALW_CARD1 +3VS_CARD1 +1.5VS_CARD1
C147
10U_0805_10V4Z
NEWCARD@
10K_0402_5%
NEWCARD@
RCLKEN1
R154
2
G
1
2
+3VS
0.1U_0402_16V4Z
12
13
D
S
C148
NEWCARD@
10K_0402_5%
NEWCARD@
CLKREQ1#
Q21
2N7002_SOT23
NEWCARD@
1
10U_0805_10V4Z
2
NEWCARD@
+3VS +3VS
12
R153
1
C149
2
5
U17
2
B
Vcc
Y
1
A
G
NC7SZ32P5X_NL_SC70-5
3
NEWCARD@
Imax = 1.35A Imax = 0.75AImax = 0.275A
1
C150
0.1U_0402_16V4Z
NEWCARD@
1
C153
0.1U_0402_16V4Z
2
NEWCARD@
4
2
Update Footprint
10U_0805_10V4Z
1
C151
2
NEWCARD@
EXP_CLKREQ# <16>
C152
0.1U_0402_16V4Z
NEWCARD@
1
2
New Card Socket (Left/TOP)
JP15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
FOX_1CH4110C_LT
NEWCARD@
(NEW)
ICH_SMBDATA<16,22,32>
+1.5VS_CARD1
ICH_PCIE_WAKE#<22,30,32>
+3VALW_CARD1
+3VS_CARD1
CLK_PCIE_EXP#<16>
CLK_PCIE_EXP<16>
PCIE_PTX_C_IRX_N3<22>
PCIE_PTX_C_IRX_P3<22>
PCIE_ITX_C_PRX_N3<22>
PCIE_ITX_C_PRX_P3<22>
USB20_N2<22>
USB20_P2<22>
ICH_SMBCLK<16,22,32>
CP_PE#<22>
CP_USB#
PERST1#
CLKREQ1#
CP_PE#
GND
USB_DUSB_D+
CPUSB#
RSV
RSV
SMB_CLK
SMB_DATA
+1.5V
+1.5V
WAKE#
+3.3VAUX
PERST#
+3.3V
+3.3V
CLKREQ#
CPPE#
REFCLKREFCLK+
GND
PERn0
PERp0
GND
PETn0
PETp0
GND
GND
GND
USB CONN. 1
+USB_VCCA
1
+
C158
150U_D_6.3VM
2
USB20_N0<22>
USB20_P0<22>
3 3
1
2
D21
GND
I/O
PRTR5V0U2X_SOT143@
1
C160
470P_0402_50V7K
2
USB20_P0
4
VCC
3
I/O
+USB_VCCA
1
2
3
4
5
6
7
8
JP16
VCC
DD+
GND
GND1
GND2
GND3
GND4
SUYIN_020173MR004G565ZR
ME@
USB CONN. 2
+USB_VCCB+USB_VCCA
+USB_VCCB
USB20_P6 USB20_N6USB20_P0 USB20_N0
1
+
C159
150U_D_6.3VM
2
USB20_N6<22>
USB20_P6<22>
1
2
D22
1
GND
2
I/O
PRTR5V0U2X_SOT143@
W=80milsW=80mils
C161
470P_0402_50V7K
USB20_N6USB20_N0
USB20_P6
4
VCC
3
I/O
+USB_VCCB
1
2
3
4
5
6
7
8
JP17
VCC
DD+
GND
GND1
GND2
GND3
GND4
SUYIN_020173MR004G565ZR
ME@
SUYIN_020173MR004G533ZR_4P SUYIN_020173MR004G533ZR_4P
+3VALW
+5VALW
1
C157
4.7U_0805_10V4Z
USB1_ON#<34>
4 4
9/17 modified this block
2
U18
1
2
3
4
G528_SO8
GND
IN
IN
EN#
OUT
OUT
OUT
FLG
+USB_VCCA
8
7
6
5
R156
10K_0402_5%
1 2
1
C162
0.1U_0402_16V4Z
2
@
USB_OC#0 <22>
4.7U_0805_10V4Z
+5VALW
1
C694
2
USB2_ON#<34>
U40
1
2
3
4
G528_SO8
GND
IN
IN
EN#
OUT
OUT
OUT
FLG
+USB_VCCB
8
7
6
5
+3VALW
R157
10K_0402_5%
1 2
1
C163
0.1U_0402_16V4Z
2
@
USB_OC#6 <22>
Security Classification
Issued Date
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
A
B
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2006/08/18 2007/8/18
Compal Secret Data
Deciphered Date
Title
Size Document Number Rev
B
D
Date: Sheet
Compal Electronics, Inc.
NEW CARD & US B Connector
IFTXX M/B LA-3541P Schematic
E
0
of
33 52Wednesday, November 01, 2006
5
L8
+3VALW +EC_AVCC
D D
CLK_PCI_EC<16>
C C
R5_PME#<28>
PCI_PME#<20>
+3VALW
1 2
R136 100K_0402_1%
1 2
R138 100K_0402_1%
1 2
R139 10K_0402_5%@
+5VALW
B B
A A
1 2
R141 4.7K_0402_5%
1 2
R142 4.7K_0402_5%
R766 10K_0402_5%
R770 10K_0402_5%
R771 10K_0402_5%
+3VS
1 2
R145 4.7K_0402_5%
1 2
R146 4.7K_0402_5%
1 2
FBM-11-160808-601-T_0603
0.1U_0402_16V4Z
1 2
L9 FBM-11-160808-601-T_0603
22P_0402_50V8J@
+3VALW
R120 47K_0402_5%
1 2
R125 0_0402_5%@
1 2
R127 0_0402_5%
FRD#SPI_SO
FSEL#SPICS#
KSO17
EC_SMB_CK1
EC_SMB_DA1
DATA_GUEST
12
CLK_GUEST
12
ACK_GUEST
12
EC_SMB_CK2
EC_SMB_DA2
C142
100P_0402_50V8J@
EC DEBUG PORT
+3VALW
EC_TX_P80_DATA
EC_RX_P80_CLK
5
C131
C140
12
1 2
0.1U_0402_16V4Z
1
2
ACES_85205-0400
2
1
ECAGND
R119 10_0402_5%@
+3VALW
1
2
3
4
C141
R124
10K_0402_5%
1 2
EC_PME#
1
C143
100P_0402_50V8J@
2
JP14
1
2
3
4
ME@
1
C132
1000P_0402_50V7K
2
12
2
1
C133
0.1U_0402_16V4Z
PCI_RST#<20,24,26,28,33,36,41>
EC_SCI#<22>
PM_CLKRUN#<22,28,29,41>
3G_LED#<42>
ISP MODE SUPPORT
R126 4.7K_0402_5%
KSO[0..15]<35>
KSI[0..7]<35>
NOVO_BTN#<35>
EC_TX_P80_DATA<14,15>
EC_RX_P80_CLK<14,15>
CHARGE_LED0#<37,42>
CHARGE_LED1#<37,42>
KB925 should use Data code 06361 which has fixed bonding issue
KB925 pin 139 is used for XCLKO, Pin 140 NC
4
0.1U_0402_16V4Z
C134
0.1U_0402_16V4Z
1
1
2
2
GATEA20<21>
KB_RST#<21>
SERIRQ<22,26,28,29,36,41>
LPC_FRAME#<21,29,36,41>
LPC_AD3<21,29,36,41>
LPC_AD2<21,29,36,41>
LPC_AD1<21,29,36,41>
LPC_AD0<21,29,36,41>
R122 0_0402_5%@
R734 0_0402_5%
12
KSO[0..15]
KSI[0..7]
1 2
R133 0_0402_5%
EC_SMB_DA2<4,17>
EC_SMB_CK2<4,17>
EC_SMB_DA1<36,45>
EC_SMB_CK1<36,45>
PWR_LED#<35,37,42>
NUM_LED#<35>
CAPS_LED#<35>
SCROLL_LED#<35>
SYSON<33,43,48>
EC_RSMRST#<22>
BKOFF#<18>
PM_SLP_S3#<22>
EC_LID_OUT#<22>
PM_SLP_S5#<22>
EC_SMI#<22>
BT_ON#<36>
LID_SW#<37>
SUSP#<17,28,33,41,43,48,49,50>
PBTN_OUT#<22>
4
C135
1
2
1 2
1 2
KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7
KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15
KSO17
EC_TX_P80_DATA
EC_RX_P80_CLK
PWR_LED#
NUM_LED#
CHARGE_LED0#
CHARGE_LED1#
CAPS_LED#
SCROLL_LED#
SYSON
EC_RSMRST#
BKOFF#
PM_SLP_S3#
EC_LID_OUT#
PM_SLP_S5#
EC_SMI#
BT_ON#
LID_SW#
SUSP#
PBTN_OUT#
EC_PME#
XCLKI
C136
0.1U_0402_16V4Z
1
2
GATEA20
KB_RST#
SERIRQ
LPC_FRAME#
LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0
CLK_PCI_EC
PCI_RST#
EC_RST#
EC_SCI#
EC_SMB_DA2
EC_SMB_CK2
EC_SMB_DA1
EC_SMB_CK1
1
C146
0.1U_0402_16V4Z
2
@
+3VALW
C137
1000P_0402_50V7K
C138
1000P_0402_50V7K
1
1
2
2
U15
1
GA20/ GPIO00/GA20
2
KBRST#/GPIO01/KBRST#
3
SERIRQ
5
LPC_FRAME# / LFRAME#
6
LPC AD3/LAD3
9
LPC AD2/LAD2
10
LPC AD1/LAD1
12
LPC AD0/LAD0
14
CLK_PCI_EC/PCICLK
15
PCIRST#
42
EC RST#/ ECRST#
24
EC SCI#/SCI#/GPIO0E
44
PM_CLKRUN#/ CLKRUN#
63
KSI0/GPIO30
64
KSI1/GPIO31
65
KSI2/GPI032
66
KSI3/GPIO33
67
KSI4/GPIO34
68
KSI5/GPI035
69
KSI6/GPIO36
70
KSI7/GPIO37
47
KSO0/GPIO20
48
KSO1/GPIO21
49
KSO2/GPIO22
50
KSO3/GPIO23
51
KSO4/GPIO24
52
KSO5/GPIO25
53
KSO6/GPIO26
54
KSO7/GPIO27
55
KSO8/GPIO28
56
KSO9/GPIO29
57
KSO10/GPIO2A
58
KSO11/GPIO2B
59
KSO12/GPIO2C
60
KSO13/GPIO2D
61
KSO14/GPIO2E
62
KSO15/GPIO2F
89
EC URXD/KSO16/GPIO48
90
EC UTXD/KSO17/GPIO49
88
EC SMD2/ GPIO47/SDA2
87
EC SMC2/GPIO46/SCL2
86
EC SMD1/GPIO44/SDA1
85
EC SMC1/GPIO44/SCL1
34
PCM_SPK#/EMAIL_LED#/ GPIO16
35
SB_SPKR/PWR_SUSP_LED#/ GPIO17
38
PWRLED#/ GPIO19
40
NUMLED#/ GPIO1A
99
BATT CHGI LED#/ E51CS#
101
BATT LOW LED#/ E51MR0
100
CAPS LED#/ E51TMR1
102
ARROW LED#/ E51 INT0
104
SYSON/GPIO56/ E51 INT1
4
EC_RSMRST#/ GPIO02
7
BKOFF#/GPIO03
8
PM SLP S3#/GPIO04
16
EC LID OUT#/GPIO06
17
PM SLP S05#/ GPIO07
18
EC SMI#/GPIO08
19
EC SWI#/GPIO09
20
LID SW#/ GPIO0A
21
SUSP#/GPIO0B
22
PBTN_OUT#/GPIO0C
23
EC PME#/GPIO0D
140
XCLKO
138
XCLKI
XCLKO
10/17 : Change P/N from SA009100120 to SA00001HZ00
3
2
EC Request
+EC_AVCC
MB_ID
127
141
75
26
37
105
11
VCC/ EC VCC
Host
INTERFACE
key Matrix
scan
SM BUS
GND
129
139
10/17 : FootPrint : SA009100120
BOM : SA00001HZ00
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITT EN CON SENT O F COMPAL ELECTRONICS, INC.
BATTEMP/AD0/GPIO38
VCC
VCC
BATT OVP/AD1/GPIO39
AD BID0/AD3/GPIO3B
VCC / EC VCC
VCC / EC VCC
VCC / EC VCC
EC_AVCC / AVCC
DAC_BRIG/DA0/GPIO3D
PWR
EN DFAN1/DA1/GPIO3D
EN DFAN2/DA3/ GPIO3F
DA output or GPO
FAN/PWM
INVT_PWM/GPIO0F/PWM1
BEEP#/GPIO10/PWM2
OUT BEEP/GPIO12/PWM3
ACOFF/GPIO18/PWM4
FAN SPEED1/GPIO14/FANFB1
FAN SPEED2/GPIO15/FANFB2
PS2 interface
Data
BUS
Address
BUS
ECTHERM#/GPIO11
GND13GND28GND
GND
GND
103
AGND
KB925QFA1 LQFP 144P
39
77
ECAGND
3
ADP_I/AD2/GPIO3A
AD INtput or GPI
IREF2/DA2
PSCLK1
PSDAT1
PSCLK2
PSDAT2
PSCLK3
PSDAT3
ADB0/D0
ADB1/D1
ADB2/D2
ADB3/ D3
ADB4/D4
ADB5/D5
ADB6/D6
ADB7/D7
KBA0/A0
KBA1/A1
KBA2/A2
KBA3/A3
KBA4/A4
KBA5/A5
KBA6/A6
KBA7/A7
KBA8/A8
KBA9/A9
KBA10/A10
KBA11/A11
KBA12/A12
KBA13/A13
KBA14/A14
KBA15/A15
KBA16/A16
KBA17/A17
KBA18/A18
KBA19/A19
SELIO2#/ GPIO43
SELIO#/ GPIO50
FRD#/RD#
FWR#/WR#
FSEL#/SELMEM#
EC ON/ GPIO1B
AC IN/ GPIO1C
ONOFF/GPIO18
PCMRST#/GPIO1E
WL OFF#/GPIO1F
ALI/MH#/GPIO40
FSTCHG/GPIO41
VR ON/ GPIO42
GPIO57/GPIO57
GPIO58/GPIO58
GPIO59/GPIO59
2006/08/04 2006/10/06
BATT_TEMP
71
BATT_OVP
72
ITES_VSENSE_X
73
ITES_VSENSE_Y
74
DAC_BRIG
76
EN_FAN1
78
IREF
79
EC_MUTE#
80
INVT_PWM
25
BEEP#
27
30
ACOFF
31
FAN_SPEED1
32
EAPD
33
ITES_EN#
91
ITES_ST
92
CLK_GUEST
93
DATA_GUEST
94
TP_CLK
95
TP_DATA
96
MUTE_BTN#
125
WWW_USER_BTN#
126
MB_ID
128
EMAIL_BTN#
130
WOW_VIDEO_BTN#
131
WOW_AUDIO_BTN#
132
PHASE_ID1
133
PHASE_ID0
134
KBA0
111
112
113
114
AD3_SMADID1
115
AD2_SMADID0
116
RDB_SMMRSB
117
WRB_PWRSB
118
3G_ON#
119
USB1_ON#
120
MUTE_LED#
121
POWER_USB_LED#
122
USB2_ON#
123
USB3_ON#
124
USB4_ON#
110
CAMERA_ON#
109
MDC_ON#
108
CHGSEL
107
106
98
POWER_USB_BTN#
84
FSTCHG
97
FRD#SPI_SO
135
FWR#SPI_SI
136
FSEL#SPICS#
144
EC_ON
41
KILL_SW#
43
EC_THERM#
29
ON/OFF#
36
ICH_POK
45
RF_ON#
46
RCIRRX
81
ENBKL
82
SMART_CHARGE_BTN#
83
VR_ON
137
SPI_CLK
142
ACIN
143
Compal Secret Data
Deciphered Date
C139 0.01U_0402_16V7K
BATT_OVP <46>
DAC_BRIG <18>
EN_FAN1 <4>
IRE F <46>
EC_MUTE# <39>
INVT_PWM <18>
BEEP# <38>
ACK_GUEST <35>
ACOFF <44,46>
FAN_SPEED1 <4>
EAPD <38,39>
ITES_EN# <25>
ITES_ST <25>
CLK_GUEST <35>
DATA_GUEST <35>
TP_CLK <36>
TP_DATA <36>
MUTE_BTN# <35>
WWW_USER_BTN# <35>
EMAIL_BTN# <35>
WOW_VIDEO_BTN# <35>
WOW_AUDIO_BTN# <35>
AD3_SMADID1 <18>
AD2_SMADID0 <18>
RDB_SMMRSB <18>
WRB_PWRSB <18>
3G_ON# <32>
USB1_ON# <33>
MUTE_LED# <35>
POWER_USB_LED# <35>
USB2_ON# <33>
USB3_ON# <37>
USB4_ON# <37>
CAMERA_ON# <42>
MDC_ON# <42>
CHGSEL <46>
FSTCHG <46>
FRD#SPI_SO <36>
FWR#SPI_SI <36>
FSEL#SPICS# <36>
EC_ON <37>
KILL_SW# <32,37>
EC_THERM# <22>
ON/OFF# <37>
ICH_POK <8,22>
RF_ON# <32>
RCIRRX <37>
ENBKL <18>
VR_ON <51>
SPI_CLK <36>
ACIN <22,44>
EC request when no CIR.
RCIRRX
R747 10K_0402_5%
ECAGND
12
POWER_USB_BTN# <35>
SMART_CHARGE_BTN# <35>
12
2
+3VALW
12
R740
Rb
10K_0402_5%
14W@
12
R743
Ra
10K_0402_5%
15W@
BATT_TEMP <45>
ITES_VSENSE_X <25>
ITES_VSENSE_Y <25>
+3VALW
1
+3VALW +3VALW
12
R741
10K_0402_5%
PHASE_ID1 PHASE_ID0
@
12
R744
10K_0402_5%
12
R742
10K_0402_5%
@
12
R745
10K_0402_5%
ID1 ID0
00
A-Test
01
B-Test
10
C-Test
KB925 SPI STRAP PIN
KBA0ACK_GUEST
MUTE_BTN#
WWW_USER_BTN#
EMAIL_BTN#
WOW_VIDEO_BTN#
WOW_AUDIO_BTN#
NOVO_BTN#
SMART_CHARGE_BTN#
POWER_USB_BTN#
EC_MUTE#
Compal Ele ctronics, Inc.
Title
ENE-KB925
Size Document Number Rev
Custom
IEL10 LA-3451P
Wednesday, November 01, 2006
Date: Sheet
1 2
R129 4.7K_0402_5%
R128 10K_0402_5%
R130 10K_0402_5%
R134 10K_0402_5%
R698 10K_0402_5%
R699 10K_0402_5%
R731 10K_0402_5%
R732 10K_0402_5%
R733 10K_0402_5%
1 2
R131 10K_0402_5%@
TP_CLK
1 2
R135 4.7K_0402_5%
TP_DATA
1 2
R137 4.7K_0402_5%
XCLKO XCLKI
R143
1 2
20M_0603_5%@
C144
15P_0402_50V8J
1
IN
2
32.768KHZ_12.5P_1TJS125BJ2A251
X1
1
12
12
12
12
12
12
12
12
4
OUT
NC3NC
EC Request
C145
15P_0402_50V8J
of
34 52
+3VALW
+5VS
0.1
5
INT_KBD Conn.
4
3
2
1
For IFT10 For IFL90 For IFT00
KSI1
KSI7
D D
C C
KSI6
KSO9
KSI4
KSI5
KSO0
KSI2
KSI3
KSO5
KSO1
KSI0
KSO2
KSO4
KSO7
KSO8
KSO6
KSO3
KSO12
KSO13
KSO14
KSO11
KSO10
KSO15
JP13
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
20
21
21
22
22
23
23
24
24
25
G1
26
G2
ACES_85201-2405N
ME@
KSI1
KSI7
KSI6
KSO9
KSI4
KSI5
KSO0
KSI2
KSI3
KSO5
KSO1
KSI0
KSO2
KSO4
KSO7
KSO8
KSO6
KSO3
KSO12
KSO13
KSO14
KSO11
KSO10
KSO15
Switch Board Conn.
PWR_LED#<34,37,42>
MUTE_LED#<34>
POWER_USB_LED#<34>
+5VALW
+3VALW
B B
WWW_USER_BTN#<34>
A A
R764 0_0402_5%
R765 0_0402_5%@
EMAIL_BTN#<34>
DATA_GUEST<34>
CLK_GUEST<34>
MUTE_BTN#<34>
ACK_GUEST<34>
1 2
1 2
EMAIL_BTN#
D_NOVO_BTN#
DATA_GUEST
CLK_GUEST
ACK_GUEST
R758
0_0402_5%
VALUE@
5
SMART_CHARGE_BTN#<34>
SATA_LED#<21>
CAPS_LED#<34>
NUM_LED#<34>
SCROLL_LED#<34>
ON/OFFBTN#<37>
1 2
R706 0_0402_5%VALUE@
1 2
R707 0_0402_5%HS@
1 2
R757 0_0402_5%HIGH@
1 2
R758 0_0402_5%HS@
1 2
R759 0_0402_5%HIGH@
1 2
R760 0_0402_5%HS@
1 2
R761 0_0402_5%HIGH@
R760
0_0402_5%
VALUE@
+5VS
JP43
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
20
21
21
22
22
23
23
24
24
25
25
GND
GND
ACES_88502-2501
ME@
ON/OFFBTN#
PWR_LED#
PWR_LED#
MUTE_LED#
POWER_USB_LED#
D_POWER_USB_BTN#
SMART_CHARGE_BTN#
+VCC_LED
SATA_LED#
CAPS_LED#
NUM_LED#
SCROLL_LED#
ON/OFFBTN#
FUNCTION_BTN1#
FUNCTION_BTN2#
FUNCTION_BTN3#
FUNCTION_BTN1#
FUNCTION_BTN2#WW W_USER_BTN#
FUNCTION_BTN3#MUTE_BTN#
4
27
26
+5VALW
JP48
20
20
19
19
18
18
17
17
16
16
15
15
14
14
13
13
12
12
11
11
10
10
9
9
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
ACES_85201-2005
ME@
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
Issued Date
JP44
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
27
GND
26
GND
ACES_88502-2501
ME@
D_POWER_USB_BTN#
D_NOVO_BTN#
+3VALW
R729
100K_0402_5%
D50
1
DAN202U_SC70
D51
1
DAN202U_SC70
2006/08/18 2007/8/18
3
1 2
POWER_USB_BTN#
2
51_ON#
3
+3VALW
R730
100K_0402_5%
1 2
NOVO_BTN#
2
51_ON#
3
Compal Secret Data
KSI1
KSI7
KSI6
KSO9
KSI4
KSI5
KSO0
KSI2
KSI3
KSO5
KSO1
KSI0
KSO2
KSO4
KSO7
KSO8
KSO6
KSO3
KSO12
KSO13
KSO14
KSO11
KSO10
KSO15
Security Classification
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SE CRET INFOR MATI ON. THIS SHEET MAY NOT BE TRANSF ERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
KSI[0..7]
KSO[0..15]
KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7
KSO0
KSO1
KSO2
KSO3
Deciphered Date
C106 100P_0402_50V8J
C109 100P_0402_50V8J
C111 100P_0402_50V8J
C113 100P_0402_50V8J
C115 100P_0402_50V8J
C117 100P_0402_50V8J
C119 100P_0402_50V8J
C121 100P_0402_50V8J
C123 100P_0402_50V8J
C125 100P_0402_50V8J
C127 100P_0402_50V8J
C129 100P_0402_50V8J
KSI[0..7] <34>
KSO[0..15] <34>
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
POWER_USB_BTN# <34>
51_ON# <37,44>
NOVO_BTN# <34>
51_ON# <37,44>
2
KSO4
C107 100P_0402_50V8J
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15
1 2
C110 100P_0402_50V8J
1 2
C112 100P_0402_50V8J
1 2
C114 100P_0402_50V8J
1 2
C116 100P_0402_50V8J
1 2
C118 100P_0402_50V8J
1 2
C120 100P_0402_50V8J
1 2
C122 100P_0402_50V8J
1 2
C124 100P_0402_50V8J
1 2
C126 100P_0402_50V8J
1 2
C128 100P_0402_50V8J
1 2
C130 100P_0402_50V8J
1 2
Video Switch Board Conn.
+5VS
WOW_VIDEO_BTN#<34>
WOW _ A U DIO_ BTN#<34>
Title
Size Document Number Rev
B
Date: Sheet
WOW _VIDEO_BTN#
WOW _ A UDIO_BTN#
Compal Electronics, Inc.
EC ENE KB910L(Reserved)
IFTXX M/B LA-3541P Schematic
1
JP49
1
1
2
2
3
3
4
4
5
5
6
6
7
GND
8
GND
ACES_85201-06051
ME@
35 52Wednesday, November 01, 2006
of
0
EC_SMB_CK1<34,45>
EC_SMB_DA1<34,45>
+3VALW
+5VALW
C105 0.1U_0402_16V4Z
1 2
U12
8
VCC
7
WP
6
SCL
5
SDA
AT24C16AN-10SU-2-7_SO8
SPI_CS#
SPI_SO
A0
A1
A2
GND
JP38
112
334
556
778
E&T_2941-G08N-00E~D
ME@
+5VALW
12
R110
100K_0402_5%
1
2
3
4
12
R111
100K_0402_5%
2
4
SPI_CLK_R
6
SPI_SI
8
+3VALW
FSEL#SPICS#<34>
SPI_CLK<34>
FWR#SPI_SI<34>
0.1U_0402_16V4Z
FSEL#SPICS#
SPI_CLK
1
C103
2
<BOM Structure>
R107 15_0402_5%
R108 15_0402_5%
R109 15_0402_5%
8M SPI ROM
+3VALW
20mils
SPI_CS#
12
SPI_CLK_R TP_DATA
12
SPI_SIFWR#SPI_SI
12
U11
8
VCC
VSS
3
W
7
HOLD
1
S
6
C
5
Q
D
SST25LF080A_SO8-200mil
4
SPI_SO
2
R626 15_0402_5%
12
FRD#SPI_SO <34>
TP_CLK<34>
TP_DATA<34>
+5VS
To TP/B Conn.
TP_CLK
TP_DATA
+5VS
C104
0.1U_0402_16V4Z
JP12
1
1
2
2
3
3
4
4
5
5
6
6
7
GND
8
GND
ACES_85201-06051
2
1
TP_CLK
3
D19
@
PSOT24C_SOT23
Update Footprint
Bluetooth Conn.
Need to check BT pin definition again!
9/20 modified this block
+5VS
12
R595
10K_0402_5%
BT_LED#<37,42>
BT_ON#<34>
9/29 follow HEL80's
BT_LED#
2N7002_SOT23
13
D
Q43
2
G
S
0.1U_0402_16V4Z
1 2
R158 100K_0402_5%
15W@
12
R596
10K_0402_5%
C164
15W@
For 15W BT Conn. located at Right corner For 14W BT Conn. located at Left corner
USB20_P8_1<22>
USB20_N8_1<22>
WLAN_ACTIVE<32>
BT_ACTIVE<32>
2
C167
4.7U_0805_10V4Z
15W@
+BT_VCC
USB20_P8_1
USB20_N8_1
BTON_LED
WLAN_ACTIVE WLAN_ACTIVE
BT_ACTIVE
+3VALW
1
C165
W=40mils
1U_0603_10V4Z
2
15W@
C168
0.1U_0402_16V4Z
15W@
G
S
Q22
SI2301BDS_SOT23
15W@
D
1 3
1
2
+BT_VCC
JP42
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
GND1
10
GND2
MOLEX_53780-0870
ME@
USB20_P8_2<22>
USB20_N8_2<22>
BT_ON#<34>
9/29 follow HEL80's
USB20_P8_2
USB20_N8_2
BTON_LED
BT_ACTIVE
0.1U_0402_16V4Z
1 2
R755 100K_0402_5%
14W@
C759
14W@
+BT_VCC_1
2
4.7U_0805_10V4Z
14W@
10
+3VALW
G
C761
JP56
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
GND1
GND2
MOLEX_53780-0870
ME@
S
Q56
SI2301BDS_SOT23
14W@
D
W=40mils
1 3
1
2
1
C760
1U_0603_10V4Z
2
14W@
C762
0.1U_0402_16V4Z
14W@
+BT_VCC_1
FOR LPC DEBUG PORT
+3VS
JP57
1
1
2
3
4
5
6
7
8
9
10
GND
GND
ACES_85201-1005N
ME@
CLK_PCI_DB
2
3
LPC_AD0
4
LPC_AD1
5
LPC_AD2
6
LPC_AD3
7
LPC_FRAME#
8
9
PCI_RST#
10
11
12
1
C765
0.1U_0402_16V7K
2
@
FOR LPC SIO DEBUG PORT
JP54
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
+5VS
LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
LPC_FRAME#
LPC_DRQ0#
PCI_RST#
CLK_PCI_DB
SERIRQ
+3VS
CLK_14M_SIO <16,41>
LPC_DRQ0# <21,41>
SERIRQ <22,26,28,29,34,41>
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
ACES_85201-2005
ME@
CLK_PCI_DB <16>
LPC_AD0 <21,29,34,41>
LPC_AD1 <21,29,34,41>
LPC_AD2 <21,29,34,41>
LPC_AD3 <21,29,34,41>
LPC_FRAME# <21,29,34,41>
PCI_RST# <20,24,26,28,33,34,41>
R769 10K_0402_5%
12
Security Classification
Issued Date
THIS SHEET OF EN GINEE RING D RAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2006/08/18 2007/8/18
Compal Secret Data
Deciphered Date
Title
Size Document Number Rev
B
Date: Sheet
Compal Electronics, Inc.
BIOS, I/O Port & K/B Connector
IFTXX M/B LA-3541P Schematic
36 52Wednesday, November 01, 2006
of
0
A
ON/OFF switch
1 1
ON/OFFBTN#<35>
Power Button
2 2
TOP Side
J3 JOPEN@
J4 JOPEN@
Bottom Side
ON/OFFBTN#
EC_ON<34>
12
12
EC_ON
10K_0402_5%
1
DAN202U_SC70
R100
1 2
+3VALW
D14
2
3
2
G
Front LED Board
+5VALW+3VALW +5VS
PWR_LED#<34,35,42>
CHARGE_LED0#<34,42>
CHARGE_LED1#<34,42>
BT_LED#<36,42>
WLAN_LED#<32,42>
KILL_SW#<32,34>
RCIRRX<34>
3 3
PWR_LED#
CHARGE_LED0#
CHARGE_LED1#
BT_LED#
WLAN_LED#
KILL_SW#
LID_SW#
RCIRRX
10
11
12
13
14
15
16
17
18
R99
100K_0402_5%
1 2
ON/OFF#
51_ON#
2
C97
1000P_0402_50V7K
1
13
D
Q18
2N7002_SOT23
S
JP51
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
11
12
13
14
15
16
G1
G2
ACES_87213-1600G
ME@
B
C
D
E
A30 IO Conn. C38 IO Conn.
ON/OFF# <34>
51_ON# <35,44>
12
D16
RLZ20A_LL34
<BOM Structure>
USB20_P4 / USB20_N4 pair
For A30 IO Conn. For C38 IO Conn.
+USB_VCCC+USB_VCCD
JP52
1
1
2
USB20_N4<22>
USB20_P4<22>
USB20_N5<22>
USB20_P5<22>
USB20_N4
USB20_P4
USB20_N5
USB20_P5
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
G1
14
G2
E&T_3703-E12N-03R
ME@
Layout Notice:
+USB_VCCC
JP53
1
1
2
USB20_N4
USB20_P4
DCD#<41>
DSR#<41>
RXD<41>
RTS#<41>
TXD<41>
CTS#<41>
DTR#<41>
RI#<41>
DCD#
DSR#
RXD
RTS#
TXD
CTS#
DTR#
RI#
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
G1
18
G2
ACES_87213-1600G
ME@
To USB CONN. 3 To USB CONN. 4
1
+
C740
150U_D_6.3VM
2
W=80mils
1
C742
470P_0402_50V7K
2
+USB_VCCD+USB_VCCC
+USB_VCCD+USB_VCCC
1
+
C741
150U_D_6.3VM
2
W=80mils
1
C743
470P_0402_50V7K
2
Lid Switch
+5VALW
14W@
C728
14W@
+VCC_LID
1
2
+3VALW
4 4
1 2
R654 0_0402_5%
0.1U_0402_16V4Z
12/9 Change t o SA032120010
A
R655 100K_0402_5%
1 2
2
VDD
3
OUTPUT
GND
U45
1
A3212ELHLT-T_SOT23W-3
14W@
14W@
2
C729
10P_0402_50V8J
1
14W@
LID_SW# <34>
B
1
C744
4.7U_0805_10V4Z
USB3_ON#<34>
2
Security Classification
Issued Date
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
U46
1
GND
2
IN
3
IN
4
EN#
G528_SO8
2006/08/18 2007/8/18
+USB_VCCC
8
OUT
7
OUT
6
OUT
5
FLG
1
C746
0.1U_0402_16V4Z
2
@
Compal Secret Data
Deciphered Date
USB_OC#4 <22>
4.7U_0805_10V4Z
D
+5VALW
1
C745
2
USB4_ON#<34>
Title
Size Document Number Rev
B
Date: Sheet
U47
1
GND
2
IN
3
IN
4
EN#
G528_SO8
Compal Electronics, Inc.
Power OK, R eset and RTC Circuit, TP
IFTXX M/B LA-3541P Schematic
OUT
OUT
OUT
FLG
+USB_VCCD
8
7
6
5
E
1
C747
0.1U_0402_16V4Z
2
@
37 52Wednesday, November 01, 2006
USB_OC#5 <22>
0
of
5
L5
+VDDA
D D
C C
1 2
FBMA-L11-160808-800LMT_0603
10U_0805_10V4Z
9/19 Realtek suggest
change 100P to @.
change from 1u to 2.2u.
MIC2_L<39>
MIC2_R<39>
MIC1_L<39>
MIC1_R<39>
MIC1_L MIC1_C_L
0.1U_0402_16V4Z
1
1
C56
C55
2
2
C69 100P_0402_50V8J @
1 2
C72 2.2U_0402_6.3V6M
C74 2.2U_0402_6.3V6M
C75 100P_0402_50V8J @
1 2
C82 100P_0402_50V8J
1 2
1 2
1 2
1 2
HDA_SDOUT_AUDIO<21>
C83 100P_0402_50V8J @
C84 2.2U_0402_6.3V6M
C85 2.2U_0402_6.3V6M
C86 100P_0402_50V8J @
C87 100P_0402_50V8J @
1
C57
2
0.1U_0402_16V4Z
HDA_RST_AUDIO#<21>
HDA_SYNC_AUDIO<21>
680P_0402_50V7K
C58
MIC2_C_L
MIC2_C_R
MIC1_C_RMIC1_R
MONO_IN
SENSE_A
SENSE_B
EAPD<34,39>
SENSE FOR Ext. Mic.
MIC_SENSE<39>
B B
1 2
R86 20K_0402_1%
SENSE_A
DGND
SENSE FOR Solo Int. Mic.
1 2
R87 20K_0402_1%
SENSE FOR HP
A A
HP_SENSE<39>
5
SENSE_B
R93 39.2K_0402_1%
12
SENSE_A
SENSE A / B
4
HD Audio Codec
40mil
1
C59
100P_0402_50V8J
2
U7
14
NC
15
NC
16
MIC2_L
17
MIC2_R
23
LINE1_L
24
LINE1_R
18
CD_L
20
CD_R
19
CD_GND
21
MIC1_L
22
MIC1_R
12
PCBEEP
11
RESET#
10
SYNC
5
SDATA_OUT
2
GPIO0
3
GPIO3
13
SENSE A
34
SENSE B
47
EAPD
48
SPDIFO
4
DVSS1
7
DVSS2
ALC268-GR_LQFP48
+AVDD_AC97
AVDD125AVDD2
38
+3VS_DVDD
20mil
1
DVDD
LINE_OUT_L
LINE_OUT_R
HP_OUT_L
HP_OUT_R
DMIC_CLK
BIT_CLK
SDATA_IN
MONO_OUT
LINE1_VREFO
GPIO1
MIC1_VREFO_L
MIC1_VREFO_R
MIC2_VREFO
VREF
JDREF
AVSS1
AVSS2
0.1U_0402_16V4Z
9
DVDD_IO
35
36
39
41
45
NC
46
43
NC
44
NC
6
8
37
29
31
28
32
30
27
40
33
NC
26
42
1
C60
2
0.1U_0402_16V4Z
10P_0402_50V8J
AMP_LEFT
AMP_RIGHT
AMP_LEFT_HP
AMP_RIGHT_HP
HDA_BITCLK_AUDIO
SDIN0
10mil
10mil
10mil
ACZ_VREF
ACZ_JDREF
20K_0402_1%
AGND
Sense Pin Impedance Codec Signals
SENSE B
39.2K
20K
10K
5.1K
39.2K
20K
10K
5.1K
PORT-A (PIN 39, 41)
PORT-B (PIN 21, 22)
PORT-C (PIN 23, 24)
PORT-D (PIN 35, 36)
PORT-E (PIN 14, 15)
PORT-F (PIN 16, 17)
PORT-G (PIN 43, 44)
PORT-H (PIN 45, 46)
Moat Bridge
1 2
R94 0_0805_5%
1 2
R95 0_0805_5%
1 2
R96 0_0805_5%
1 2
R97 0_0805_5%
4
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SE CRET INFOR MATI ON. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
10U_0805_10V4Z
1
1
C61
C62
2
2
680P_0402_50V7K
1
C70
2
@
1 2
R82 33_0402_5%
+MIC1_VREFO_L
+MIC1_VREFO_R
+MIC2_VREFO
12
R84
1
2
C88
100P_0402_50V8J
@
Funnction
HP
MIC
LINE IN
LINE Out
HP
MIC
LINE IN
LINE Out
3
680P_0402_50V7K
C63
1
C71
10P_0402_50V8J
2
@
10mil
2006/08/05
3
L6
1 2
FBMA-L11-160808-800LMT_0603
1
C64
C65
100P_0402_50V8J
2
AMP_LEFT <39>
AMP_RIGHT <39>
AMP_LEFT_HP <39>
AMP_RIGHT_HP <39>
HDA_BITCLK_AUDIO <21>
HDA_SDIN0 <21>
1
C89
10U_0805_10V4Z
2
Compal Secret Data
2
+3VS
9/22 Update footprint, N eed to check
EC Beep
BEEP#<34>
PCI Beep
SB_SPKR<22>
CardBus Beep
1
C90
100P_0402_50V8J
2
PCM_SPK#<26>
MONO_IN_1
C736 470P_0402_50V8J
2
1
1 2
Regulator for CODEC
L7
1 2
FBMA-L11-160808-800LMT_0603
C92
4.7U_0805_10V4Z
0.1U_0402_16V4Z
Deciphered Date
2007/08/05
2
C67
1 2
1U_0402_6.3V4Z
C73
1 2
1U_0402_6.3V4Z
C77
1 2
1U_0402_6.3V4Z
C80
0.01U_0402_16V7K
+VDDA
R697
10K_0402_1%
Adjustable Output
U8
4
VIN
2
DELAY
ERROR7CNOISE
C93
8
SD
SI9182DH-AD_MSOP8
Title
Size Document Number Rev
Date: Sheet
R75
1 2
560_0402_5%
R77
1 2
560_0402_5%
R78
1 2
560_0402_5%
10K_0402_5%
12
R696
10K_0402_1%
12
13
D
S
9/26 modified
SENSE or ADJ
<Title>
Custom
Wednesday, November 01, 2006
1
+VDDA
12
R73
10K_0402_5%
C66
1 2
12
R80
1 2
C735
C737
2
G
Q48
2N7002_SOT23
5
VOUT
6
1
3
GND
12
R767
@
680P_0402_50V7K
@
680P_0402_50V7K
EAPD
C95
0.1U_0402_16V4Z
1U_0402_6.3V4Z
R74
10K_0402_5%
1
C
Q15
2
B
E
2SC2411K_SOT23
3
D12
RB751V_SOD323
9/19 Realtek suggest
2 1
Add bypass schematic.
MONO_IN_2
0_0402_5%@
HDA_BITCLK_AUDIO
C68
1U_0402_6.3V4Z
1 2
1 2
R76
2.4K_0402_5%
Need Update Footprint
1 2
12
AMPL
AMPR
1 2
1
2
+VDDA+5VS_VDDA
R88
30K_0402_1%
R89
10K_0402_1%
Compal Electronics, Inc.
HD Audio Codec ALC268
LA-3541P
1
38 52
of
MONO_INMONO_IN_1
MONO_IN_2 <39>
AMPL <39>
AMPR <39>
R85
10_0402_5%
@
C91
10P_0402_50V8J
@
+VDDA+5VS
C94
4.7U_0805_10V4Z
0.1
A
B
C
D
E
APA2056 SPK/HP Amplifier
+5VALW
W=40mil
1
C34
INR_A
INL_A
AMP_EN#
HP_EN
INR_H
INL_H
AMP_BEEP
C35
2
0.1U_0402_16V4Z
3
5
27
24
4
6
26
28
12
14
25
C33
AMPL<38>
1 1
fo=1/(2*3.14*R*C)=106Hz
R=1.5K / C= 1uF
AMP_RIGHT<38>
AMP_LEFT<38>
9/19 Realtek suggest
Change C43/C44 from 2.2uf to 4.7uf.
AMP_RIGHT_HP<38>
AMP_LEFT_HP<38>
MONO_IN_2<38>
2 2
9/5 If implement AMP BEEP, Swap C155 and R79.
AMPR<38>
R52 1.5K_0402_1%@
1 2
R53 1.5K_0402_1%@
1 2
1 2
C39 1U_0402_6.3V4Z
1 2
C41 1U_0402_6.3V4Z
1 2
C43 4.7U_0805_10V4Z
1 2
C44 4.7U_0805_10V4Z
R768
1 2
0_0402_5%
1 2
C40 1U_0402_6.3V4Z
AMP_L
1 2
C42 1U_0402_6.3V4Z
R56 100K_0402_5%
1 2
R57 100K_0402_5%
AMP_RHPIN
AMP_LHPIN
AMP_SD#
1 2
C45 0.47U_0402_6.3V6K
1 2
R58 39K_0402_5%
R59 39K_0402_5%
+5VS
AMPRAMP_R
AMPL
1 2
1 2
C46 1U_0402_6.3V4Z
C47 2.2U_0603_6.3V6K
C49 0.1U_0402_16V4Z
1 2
R54
1 2
0_0402_5%
R55
1 2
0_0402_5%
R60 0_0402_5%
AMP_CP+
AMP_CP-
12
680P_0402_50V7K
12
R79 change from 0 Ohm to 47K
9/5 ANPEC Suggest
Place 1U cap between pin 1 and 2
10
PVDD
1
VDD
ROUT+
ROUT-
LOUT+
LOUT-
HP_R
HP_L
CVSS
VSS
GND
PGND
PGND
CGND
U6
2
C36
1U_0402_6.3V4Z
1
22
21
8
9
17
18
15
16
2
23
7
13
CVSS
SPKR+
SPKR-
SPKL+
SPKL-
HP_R
HP_L
1
2
1
2
INR_A
INL_A
/AMP EN
HP EN
INR_H
INL_H
/SD
BEEP
CP+
CPBIAS
10U_0805_10V4Z
19
11
HVDD
CVDD
APA2056_TSSOP28
20
PVDD
IN_A Gain = 10dB (Internal Speaker)
IN_H Gain = 0dB (Headphone)
C48
1U_0402_6.3V4Z
+MIC1_VREFO_R+MIC1_VREFO_L
12
10mil 10mil
R50
4.7K_0402_5%
MIC_SENSE<38>
MIC1_R<38>
MIC1_L<38>
HP_SENSE<38>
MIC_SENSE
MIC1_R
MIC1_L
220P_0402_50V7K
HP_SENSE
HP_R
HP_LAMP_BIAS
R61
0_0402_5%
@
<BOM Structure>
1
C37
220P_0402_50V7K
2
12
12
R62
0_0402_5%
@
12
R51
4.7K_0402_5%
<BOM Structure>
1
C38
2
10P_0402_50V8J
MICROPHONE
IN JACK
JP55
1
1
2
2
3
3
4
1
1
C50
C51
10P_0402_50V8J
2
2
HEADPHONE
OUT JACK
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
ACES_87212-1200
ME@
EC_MUTE#<34>
EAPD<34,38>
3 3
EC_MUTE#
EAPD
R64 0_0402_5%
R65 0_0402_5%@
12
12
AMP_SD#
SINGLE INT MIC/DUAL INT MIC
D10
MIC_L1
GND
GND
MIC_R1
GND
GND
1
1
2
2
3
4
1
1
2
2
3
4
2 1
RB751V_SOD323
DUAL@
D11
2 1
RB751V_SOD323
+MIC2_VREFO
ACES_88231-02001
DUAL@
+MIC2_VREFO
4 4
ACES_88231-02001
1 2
R70 4.7K_0402_5%
MIC2_L
C52
R72 4.7K_0402_5%
1 2
MIC2_R
C54 220P_0402_50V7K
DUAL@
12
220P_0402_50V7K
DUAL@
12
12
R71
0_0402_5%
INT@
MIC2_L <38>
MIC2_R <38>
Security Classification
Issued Date
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
A
B
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
SPKL+
SPKLSPKR+
SPKR-
20mil
Compal Secret Data
R700 0_0603_5%
1 2
R701 0_0603_5%
1 2
R702 0_0603_5%
1 2
R703 0_0603_5%
1 2
Speaker Conn.
Deciphered Date
D
SPK_L1+
SPK_L1SPK_R1+
SPK_R1-
PSOT24C_SOT23
2007/08/052006/08/05
2
3
2
3
D46
1
Title
Size Document Number Rev
Custom
Date: Sheet
D47
PSOT24C_SOT23
1
Compal Electronics, Inc.
AMP/VR/Audio Jack/MIC
LA-3541P
JP9
1
1
2
2
3
3
4
4
5
G1
6
G1
E&T_3802-E04N-01R
ME@
E
0.1
of
39 52Wednesday, November 01, 2006
H1
HOLEA
1
H2
HOLEA
1
H3
HOLEA
1
H15
HOLEA
1
H17
HOLEA
1
H27
HOLEA
1
M4
HOLEA
1
H_O236X295D236X295N
H5
H4
HOLEA
HOLEA
1
1
H16
HOLEA
1
H18
H19
HOLEA
HOLEA
1
1
H28
H29
HOLEA
HOLEA
1
1
M6
M5
HOLEA
HOLEA
1
1
H_O122X220D122X220N
H_O122X220D122X220N
H6
HOLEA
1
H20
HOLEA
1
H30
HOLEA
1
95.10.5 add
H7
HOLEA
1
H21
HOLEA
1
H32
HOLEA
1
H8
HOLEA
1
H22
HOLEA
1
H33
HOLEA
1
H9
HOLEA
1
H23
HOLEA
1
H34
HOLEA
1
H10
HOLEA
1
H24
HOLEA
1
H11
HOLEA
1
H25
HOLEA
1
H12
HOLEA
1
H26
HOLEA
1
H13
HOLEA
1
H_C125BC220D122
H31
HOLEA
1
H14
HOLEA
1
95.10.5 add
FD1
CF1
CF11
FD6
FD3
FD2
@
@
1
@
1
@
1
CF2
CF23
1
1
CF3
@
1
1
@
1
FD5
FD4
@
CF4
@
@
1
@
1
CF5
1
1
CF8
CF7
CF6
@
@
1
1
1
CF9
CF10
@
@
@
1
@
1
1
@
@
Security Classification
Issued Date
THIS SHEET OF EN GINEE RING D RAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2006/08/18 2007/8/18
Compal Secret Data
Deciphered Date
Title
Size Document Number Rev
B
Date: Sheet
Compal Electronics, Inc.
FAN & Screw Hole
IFTXX M/B LA-3541P Schematic
of
40 52Wednesday, November 01, 2006
0
A
B
C
D
E
SIO_GPIO11
+3VS
1 2
1 2
R38
10K_0402_5%
@
R41
1K_0402_5%
217@
Base I/O Address
*
0 = 02Eh
1 = 04Eh
SUPER I/O SMsC LPC47N217
1 1
LPC_FRAME#<21,29,34,36>
R36 0_0402_5%217@
PLT_RST#<8,20,22,29,30>
2 2
+3VS
R32 10K_0402_5%217@
1 2
R33 10K_0402_5%@
1 2
R607 10K_0402_5%217@
1 2
SUS_STAT#
SIO_SMI#
SIO_PME#
1 2
R37 0_0402_5%@
1 2
LPC_DRQ0#<21,36>
SUS_STAT#<22,29>PCI_RST#<20,24,26,28,33,34,36>
PM_CLKRUN#<22,28,29,34>
CLK_PCI_SIO<16>
SERIRQ<22,26,28,29,34,36>
CLK_14M_SIO<16,36>
LPC_AD[0..3]<21,29,34,36>
10/19 : Change P/N from SA472170000 to SA472170010
LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
LPC_FRAME#
LPC_DRQ0#
SIO_RST#
SUS_STAT#
PM_CLKRUN#
CLK_PCI_SIO
SERIRQ
SIO_PME#
CLK_14M_SIO
SIO_GPIO11
SIO_SMI#
SIO_IRQ
LPC_AD[0..3]
U4
10
LAD0
12
LAD1
13
LAD2
14
LAD3
15
LFRAME#
16
LDRQ#
17
PCI_RESET#
18
LPCPD#
19
CLKRUN#
20
PCI_CLK
21
SER_IRQ
6
IO_PME#
9
CLK14
CLOCK
23
GPIO40
24
GPIO41
25
GPIO42
27
GPIO43
28
GPIO44
29
GPIO45
30
GPIO46
31
GPIO47
32
GPIO10
33
GPIO11/SYSOPT
34
GPIO12/IO_SMI#
35
GPIO13/IRQIN1
36
GPIO14/IRQIN2
40
GPIO23
8
VSS
22
VSS
43
VSS
52
VSS
LPC47N217_STQFP64
217@
LPC I/F
GPIO
POWER
RXD1
TXD1
DSR1#
RTS1#
CTS1#
DTR1#
RI1#
SERIAL I/F
DCD1#
IRRX2
FIR
IRTX2
IRMODE/IRRX3
INIT#
SLCTIN#
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
SLCT
PE
BUSY
PARALLEL I/F
ACK#
ERROR#
ALF#
STROBE#
VTR
VCC
VCC
VCC
VCC
RXD1
62
TXD1
63
DSR#1
64
RTS#1
1
CTS#1
2
DTR#1
3
RI#1
4
DCD#1
5
IRRX
37
38
39
41
42
44
46
47
48
49
50
51
53
55
56
57
58
59
60
61
7
11
26
45
54
C25
217@
1
2
0.1U_0402_16V4Z
RP56
10K_1206_8P4R_5%
217@
R756 10K_0402_5%217@
C24
217@
45
36
27
18
12
1
1
C763
217@
2
2
0.1U_0402_16V4Z
+3VS
+3VS
1
C764
217@
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
SIO_IRQ
R39 10K_0402_5%@
IRRX
R40 10K_0402_5%217@
3 3
4 4
Agilent IRRX unpop 10K
Vishay IRRX pop 10K
R42
10K_0402_5%
NOSIO@
1 2
1
C26
15P_0402_50V8J
NOSIO@
2
1 2
12
C695
0.1U_0402_16V4Z
217@
28
2
C696
0.1U_0402_16V4Z
217@
24
1
2
C697
0.1U_0402_16V4Z
217@
1
CLK_PCI_SIOCLK_14M_SIO
R43
10_0402_5%
@
1 2
1
C27
15P_0402_50V8J
2
@
DTR#1
RTS#1
TXD1
CTS#1
RI#1
RXD1
DCD#1
DSR#1
SUSP#<17,28,33,34,43,48,49,50>
14
13
12
19
18
17
16
15
20
23
22
Security Classification
Issued Date
9/18 modify th i s p ag e f o l l owing IGT1x
A
B
THIS SHEET OF EN GINEE RING D RAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
+3VS
2
1
U41
C1+
C1-
1
C2+
2
C2TIN1
TIN2
TIN3
ROUT1
ROUT2
ROUT3
ROUT4
ROUT5
ROUTB2
FORCEON
FORCEOFF#
MAX3243CAI_SSOP28
217@
C
26
27
VCC
V+
3
V-
9
TOUT1
10
TOUT2
11
TOUT3
4
RIN1
5
RIN2
6
RIN3
7
RIN4
8
RIN5
21
INVLD#
25
GND
2005/05/26 2006/07/26
12
C698 0.1U_0402_16V4Z217@
12
C699 0.1U_0402_16V4Z217@
DTR#
RTS#
TXD
CTS#
RI#
RXD
DCD#
DSR#
DTR# <37>
RTS# <37>
TXD <37>
CTS# <37>
RI# <37>
RXD <37>
DCD# <37>
DSR# <37>
Compal Secret Data
Deciphered Date
Title
Size Document Number Rev
D
Date: Sheet
Compal Electronics, Inc.
SUPER I/O LPC47N217
LA-3541P UMA
41 52Wednesday, November 01, 2006
E
0.2
of
MDC Conn.
JP2
1
GND1
HDA_SDOUT_MDC<21>
HDA_SYNC_MDC<21>
HDA_SDIN1<21>
HDA_RST_MDC#<21> HDA_BITCLK_MDC <21>
1 2
R25 33_0402_5%
3
IAC_SDATA_OUT
5
GND2
7
IAC_SYNC
9
IAC_SDATA_IN
11
IAC_RESET#
GND13GND14GND15GND16GND17GND
RES0
RES1
GND3
GND4
IAC_BITCLK
18
3.3V
2
4
20mil
6
8
10
12
1
2
C16
@
22P_0402_50V8J
+MDC_VCC
Connector for MDC Rev1.5
ACES_88018-124G
ME@
+3VALW
1
W=40mils
C749
1U_0603_10V4Z
2
C751
0.1U_0402_16V4Z
+MDC_VCC
MDC_ON#<34>
9/29 follow HEL80's
C748
0.1U_0402_16V4Z
1 2
R735 100K_0402_5%
4.7U_0805_10V4Z
2
C750
S
G
Q51
SI2301BDS_SOT23
D
1 3
1
2
LED
R28
14W@
+5VALW
+5VS
+5VALW
+5VALW
+5VS
+5VS
300_0402_5%
1 2
R27
14W@
300_0402_5%
1 2
R30
14W@
1 2
300_0402_5%
R31
14W@
1 2
300_0402_5%
R708
14W@
1 2
300_0402_5%
R709
14W@
1 2
300_0402_5%
2 1
HT-191NB_BLUE_0603
14W@
2 1
HT-191NB_BLUE_0603
HS@
4 3
2 1
Blue&Amber
4 3
2 1
LED1
LED2
LED3
HT-297DQ/GQ_AMB/YG_0603
14W@
LED4
HT-297DQ/GQ_AMB/YG_0603
14W@
Amber
YG
Blue
A
Amber
YG
Blue
A
PWR_LED# <34,35,37>
3G_LED# <34>
CHARGE_LED0# <34,37>
CHARGE_LED1# <34,37>
BT_LED# <36,37>
WLAN_LED# <32,37>
Camera Conn
CAMERA_ON#<34>
C753
0.1U_0402_16V4Z
1 2
R736 100K_0402_5%
4.7U_0805_10V4Z
+5VS
1
C754
W=40mils
1U_0603_10V4Z
2
C755
0.1U_0402_16V4Z
+5VS_CMOS
2
C693
S
G
Q52
SI2301BDS_SOT23
D
1 3
1
2
Finger Print board
For EMI
1
D3
PSOT24C_SOT23
@
2
USB20_P9<22>
USB20_N9<22>
Security Classification
Issued Date
THIS SHEET OF EN GINEE RING D RAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2006/08/18 2007/8/18
USB20_P9
USB20_N9
+3VS
T1 P AD
FPR_SW
@
4.7U_0805_10V4Z
Compal Secret Data
Deciphered Date
3
1
1
C19
C20
0.1U_0402_16V4Z
2
2
@
+5VS_CMOS
1
1
USB20_N7<22>
USB20_P7<22>
C17
4.7U_0805_10V4Z
USB20_N7
USB20_P7
2
@
C18
0.1U_0402_16V4Z
2
2
3
1
JP4
1
1
2
2
3
3
4
4
5
5
6
6
7
GND
8
GND
ACES_85201-06051
ME@
D1
@
PSOT24C_SOT23
Need to check pin definition
Title
Size Document Number Rev
B
Date: Sheet
Compal Electronics, Inc.
MDC/CIR & LED
IFTXX M/B LA-3541P Schematic
1
2
3
4
5
6
7
ACES_88266-05001
of
42 52Wednesday, November 01, 2006
ME@
JP3
1
2
3
4
5
GND1
GND2
0
A
B
C
D
E
C4
10U_0805_10V4Z
SUSP
2N7002_SOT23
1
2
Q3
+5VALW TO +5VS
+5VALW
U1
8
7
6
5
2
G
1
S
D
2
S
D
3
S
D
4
G
D
AO4468_SO8
5VS_GATE
13
D
S
+1.5VS +2.5VS +1.05VS +1.8V+0.9VS
+5VS
1
C1
10U_0805_10V4Z
2
1
C5
0.1U_0603_25V7K
2
1
C2
2
1U_0603_10V4Z
R12
470_0603_5%
@
1 2
13
D
S
SUSP
2
G
Q2
2N7002_SOT23
@
C8
10U_0805_10V4Z
+VSB
1
2
1 2
R738
47K_0402_5%
SUSP
2N7002_SOT23
+3VALW TO +3VS
+3VALW
8
7
6
5
1
C9
2
10U_0805_10V4Z
13
D
2
Q53
G
S
U2
D
D
D
G
D
AO4468_SO8
+1.8V to +1.8VS
1
C13
2
10U_0805_10V4Z
PM@
R19
33K_0402_5%
PM@
SUSP
Q7
2N7002_SOT23
PM@
+1.8V
1
2
SYSON<33,34,48>
2
G
U3
8
D
7
D
6
D
5
D
AO4468_SO8
PM@
1.8VS_GATE
13
D
S
R13
100K_0402_5%
S
S
S
G
SYSON
+3VS
1
S
2
S
3
S
C6
4
10U_0805_10V4Z
1
C756
0.1U_0603_25V7K
2
1
2
1
C7
2
1U_0603_10V4Z
+1.25VS
R17
470_0603_5%
@
1 2
13
D
Q5
S
2N7002_SOT23
@
C12
10U_0805_10V4Z
SUSP
2
G
PM@
+VSB
1
2
3
4
SYSON#
12
+1.8VS
C10
10U_0805_10V4Z
PM@
1
C14
0.1U_0603_25V7K
2
PM@
+5VALW
2
G
1
2
R11
100K_0402_5%
1 2
13
D
Q1
2N7002_SOT23
S
1
C11
2
1U_0603_10V4Z
PM@
R18
470_0603_5%
@
1 2
13
D
S
SUSP
2
G
Q6
2N7002_SOT23
@
1 1
1
C3
10U_0805_10V4Z
2
+VSB
R14
33K_0402_5%
2 2
3 3
R20
470_0603_5%
@
1 2
13
D
SUSP SUSP SUSP SUSP SYSON#
2
G
Q8
S
2N7002_SOT23
@
4 4
A
R21
470_0603_5%
@
1 2
13
D
S
2
G
Q9
2N7002_SOT23
@
B
R22
470_0603_5%
@
1 2
13
D
S
2
G
Q10
2N7002_SOT23
@
R23
470_0603_5%
@
1 2
13
D
2
G
Q11
S
2N7002_SOT23
@
Security Classification
Issued Date
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
D
S
C
R24
470_0603_5%
@
1 2
13
2
G
Q12
2N7002_SOT23
@
2006/08/18 2007/8/18
R739
470_0603_5%
@
1 2
13
D
SYSON#
2
G
Q54
S
2N7002_SOT23
@
Compal Secret Data
Deciphered Date
SUSP<50>
SUSP#<17,28,33,34,41,48,49,50>
D
SUSP
R16
100K_0402_5%
Title
Size Document Number Rev
B
Date: Sheet
+5VALW
R15
100K_0402_5%
1 2
13
D
Q4
2
2N7002_SOT23
G
S
12
Compal Electronics, Inc.
DC Interface
IFTXX M/B LA-3541P Schematic
43 52Wednesday, November 01, 2006
E
0
of
Loading...