Compal LA-3491P, 530, 550 Schematic

A

1 1

2 2

B

C

D

E

Compal confidential

Schematics Document

Mobile Yonah uFCPGA with Intel
Calistoga_GM+ ICH7-M core logic

3 3

2007-03-20

REV:0.5

4 4

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2006/10/26 2006/07/26

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

D

Date: Sheet

Compal Electronics, Inc.

Cover Sheet

LA-3491P

E

0.5

of

147Tuesday, March 20, 2007

A

Compal confidential

File Name : LA-3491P

B

C

D

E

Volga 2.0

1 1

Fan Control

page 4

Mobile Yonah/Merom

uFCPGA-478 CPU

Thermal Sensor
ADM1032AR

page 4page 4,5,6

Clock Generator

ICS9LP306BGLFT

page 15

FSB

H_A#(3..31)

CRT

page 16

Intel Calistoga MCH

LVDS Conn

page 17

2 2

533/667MHz

945GM

PCBGA 1466

page 7,8,9,10,11,12

H_D#(0..63)

DDR2 -400/533/667

Dual Channel

DDR2-SO-DIMM X2

BANK 0, 1, 2, 3

page 13,14

DMI

USB2.0

USB Conn x2

page 29

MODEM AMOM

PCI-E BUS

INTEL LAN

LED

3 3

page 31

RTC CKT.

page 19

82562V 10 /100

page 23

RJ45/11 CONN

page 23

Mini-Card
WLAN

page 25

CardBus Controller

CB-1410

PCI BUS

page 24

Intel ICH7-M

mBGA-652

page 18,19,20,21

SPI ROM
25LF080A

AC-LINK/Azalia

SATA

SPI

PATA Slave

page 31

Audio Conexant

CX20549-12

page 26

SATA HDD Connector

page 22

IDE ODD Connector

page 22

CX20548

page 27

AMP & Audio Jack
TPA6017A2

page 28

LPC BUS

Power OK CKT.

page 34

Slot 0

page 24

Power On/Off CKT.

page 31

4 4

DC/DC Int erface CKT.

page 33

Touch Pad CONN.

Power Circuit DC/DC

、

83940

Page 37 3

、、

A

B

SMSC KBC 1070

page 30

Int.KBD

page 30page 32

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2006/10/26 2006/07/26

Compal Secret Data

Deciphered Date

D

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

Block Diagram

LA-3491P

E

of

247Tuesday, March 20, 2007

0.5

5

4

3

2

1

Voltage Rails

Power Plane

VIN

D D

B+
+CPU_CORE
+VCCP
+0.9V
+1.5VS
+1.8V
+2.5VS
+3VALW

+5VALW
+5VS
+RTC_VCC

Description

Adapter power supply (18.5V)
AC or battery power rail for power circuit
Core voltage for CPU

1.05V power rail for Processor I/O and MCH/ICH core power

0.9V switched power rail for DDRII Vtt

1.5V switched power rail for PCI-E interface

1.8V power r ail for DDRII

3.3V always on power rail

3.3V switched power rail+3VS
5V always on power rail
5V switched power rail
RTC power ONON

S0-S1

S3

N/A

N/A

N/A
ON OFF
ON
ON

OFF
ON

OFF
ON

ON
ON OFF

ON

ON
ON OFF OFF

ON

ON
ON

OFF

ON

S5

N/A
N/AN/A
OFF
OFFOFF
OFF
OFF
OFF
OFF2.5V switched power rail for MCH video PLL
ON*

ON*
OFF

NOXDP@ : means just build when XDP function disable.
LP@ : means just build when Low power clock gen. install
BATT@ : mea n s n ee d b e mounted when 45 level assy or rework stage.
45@ : means need be mounted when 45 level assy or rework stage.
14@ : means need be mounted when 14.1"
WLAN@ : means need be m ounted when have wireless LED Function
WLAN14@ : means need be mounted when have wireless LED Function and 14"

XDP@ : mean s jus t b uil d w hen X DP fun cti on en abl e. When this tim e, docking PCI express will not work.
CONN@ : means ME parts

Symbol Note :

: means Digital Ground

: means Analog Ground

Debug@ : mean s M in i debug card use

Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.

C C

Calistoga 945GM R3 SA0000059L0
Calistoga 945GM R1 SA0000059A0
Calistoga 940GML R3 SA000011C10
Calistoga 940GML R1 SA000011C00

ICH7 R3 SA00000V1A0

ICH7 R1 SA00000V1F0

IAT50 945GM FF 46147932L01
IAT50 940GML DF 46147932L02
IAT50 940GML DF 46147932L03 (No WLAN)

B B

IAT60 945GM FF 46147932L21
IAT60 940GML DF 46147932L22

External PCI Devices

DEVICE

CARD BUS

PCI Device ID

D6

IDSEL #

AD22

REQ/GNT #

2

PIRQ

C

IAT60 940GML DF 46147932L23 (No WLAN)

I2C / SMBUS ADDRESSING

DEVICE

A A

DDR SO-DIMM 0
DDR SO-DIMM 1
CLOCK GENERATOR (EXT.)

5

HEX

A0

D2

ADDRESS

1 0 1 0 0 0 0 0
1 0 1 0 0 1 0 0A4
1 1 0 1 0 0 1 0

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

4

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/10/26 2006/07/26

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

2

Date: Sheet

Compal Electronics, Inc.

Notes List

LA-3491P

347Tuesday, March 20, 2007

1

0.5

of

5

4

3

2

1

H_A#[3..31]<7>

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8

D D

H_REQ#[0..4]<7>

H_ADSTB#0<7>

R15

1 2

+VCCP

E

3 1

Q2

MMBT3904_SOT23@

H_ADSTB#1<7>

CLK_CPU_BCLK<15>

CLK_CPU_BCLK#<15>

H_ADS#<7>
H_BNR#<7>

H_BPRI#<7>

H_BR0#<7>

H_DEFER#<7>

H_DRDY#<7>

H_HIT#<7>

H_HITM#<7>

H_LOCK#<7>

H_RESET#<7>

H_RS#[0..2]<7>

H_TRDY#<7>

XDP_DBRESET#<20>

H_DBSY#<7>

H_DPSLP#<19>

H_DPRSTP#<19,40>

H_DPWR#<7>

H_PWRGOOD<19>

H_CPUSLP#<7>

12

H_THERMTRIP#<7,19>

12

R18

56_0402_5%@

B

2

C

5

C C

R12

56_0402_5%

1 2

+VCCP

B B

H_PROCHOT#<40>

1 2

+VCCP

56_0402_5%

R16 1K_0402_5%@
R17 51_0402_5%

Follow datasheet 12/05

H_THERMDA, H_THERMDC routing together.
Trace width / Spacing = 10 / 10 mil

A A

H_PROCHOT# OCP#

H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

H_ADSTB#0
H_ADSTB#1

CLK_CPU_BCLK
CLK_CPU_BCLK#

H_ADS#
H_BNR#
H_BPRI#
H_BR0#
H_DEFER#
H_DRDY#
H_HIT#
H_HITM#
H_IERR#
H_LOCK#
H_RESET#

H_RS#0
H_RS#1
H_RS#2
H_TRDY#

XDP_BPM#0
XDP_BPM#1
XDP_BPM#2
XDP_BPM#3

XDP_DBRESET#

H_DBSY#
H_DPSLP#
H_DPRSTP#
H_DPWR#
XDP_BPM#4
XDP_BPM#5
H_PROCHOT#

H_PWRGOOD
H_CPUSLP#
XDP_TCK
XDP_TDI
XDP_TDO
TEST1
TEST2
XDP_TMS
XDP_TRST#

H_THERMDA
H_THERMDC
H_THERMTRIP#

OCP# <20,30,42>

JP1A

J4

A3#

L4

A4#

M3

A5#

K5

A6#

M1

A7#

N2

A8#

J1

A9#

N3

A10#

P5

A11#

P2

A12#

L1

A13#

P4

A14#

P1

A15#

R1

A16#

Y2

A17#

U5

A18#

R3

A19#

W6

A20#

U4

A21#

Y5

A22#

U2

A23#

R4

A24#

T5

ADDR GROUP

A25#

T3

A26#

W3

A27#

W5

A28#

Y4

A29#

W2

A30#

Y1

A31#

K3

REQ0#

H2

REQ1#

K2

REQ2#

J3

REQ3#

L5

REQ4#

L2

ADSTB0#

V4

ADSTB1#

A22

BCLK0

A21

H1

E2

G5

F1

H5

F21

G6

E4

D20

H4

B1

F3

F4
G3
G2

AD4
AD3
AD1
AC4

C20

E1

B5

E5

D24
AC2
AC1
D21

D6
D7

AC5
AA6
AB3
C26
D25
AB5
AB6

A24
A25

C7

HOST CLK

BCLK1

ADS#
BNR#
BPRI#
BR0#
DEFER#
DRDY#
HIT#

CONTROL

HITM#
IERR#
LOCK#
RESET#

RS0#
RS1#
RS2#
TRDY#

BPM0#
BPM1#
BPM2#
BPM3#

DBR#
DBSY#
DPSLP#
DPRSTP#
DPWR#
PRDY#
PREQ#
PROCHOT#

PWRGOOD
SLP#
TCK
TDI
TDO
TEST1
TEST2
TMS
TRST#

THERMAL

THERMDA

DIODE

THERMDC
THERMTRIP#

FOX_PZ47903-2741-42_YONAH

CONN@

H_DPSLP#

1 2

56_0402_5%@

H_DPRSTP#

1 2

56_0402_5%@

YONAH

DATA GROUP

MISC

LEGACY CPU

R19

R20

4

D10#
D11#
D12#
D13#
D14#
D15#
D16#
D17#
D18#
D19#
D20#
D21#
D22#
D23#
D24#
D25#
D26#
D27#
D28#
D29#
D30#
D31#
D32#
D33#
D34#
D35#
D36#
D37#
D38#
D39#
D40#
D41#
D42#
D43#
D44#
D45#
D46#
D47#
D48#
D49#
D50#
D51#
D52#
D53#
D54#
D55#
D56#
D57#
D58#
D59#
D60#
D61#
D62#
D63#

DINV0#
DINV1#
DINV2#
DINV3#

DSTBN0#
DSTBN1#
DSTBN2#
DSTBN3#
DSTBP0#
DSTBP1#
DSTBP2#
DSTBP3#

A20M#
FERR#

IGNNE#

INIT#
LINT0
LINT1

STPCLK#

SMI#

H_D#0

E22

D0#

H_D#1

F24

D1#

H_D#2

E26

D2#

H_D#3

H22

D3#

H_D#4

F23

D4#

H_D#5

G25

D5#

H_D#6

E25

D6#

H_D#7

E23

D7#

H_D#8

K24

D8#

H_D#9

G24

D9#

H_D#10

J24

H_D#11

J23

H_D#12

H26

H_D#13

F26

H_D#14

K22

H_D#15

H25

H_D#16

N22

H_D#17

K25

H_D#18

P26

H_D#19

R23

H_D#20

L25

H_D#21

L22

H_D#22

L23

H_D#23

M23

H_D#24

P25

H_D#25

P22

H_D#26

P23

H_D#27

T24

H_D#28

R24

H_D#29

L26

H_D#30

T25

H_D#31

N24

H_D#32

AA23

H_D#33

AB24

H_D#34

V24

H_D#35

V26

H_D#36

W25

H_D#37

U23

H_D#38

U25

H_D#39

U22

H_D#40

AB25

H_D#41

W22

H_D#42

Y23

H_D#43

AA26

H_D#44

Y26

H_D#45

Y22

H_D#46

AC26

H_D#47

AA24

H_D#48

AC22

H_D#49

AC23

H_D#50

AB22

H_D#51

AA21

H_D#52

AB21

H_D#53

AC25

H_D#54

AD20

H_D#55

AE22

H_D#56

AF23

H_D#57

AD24

H_D#58

AE21

H_D#59

AD21

H_D#60

AE25

H_D#61

AF25

H_D#62

AF22

H_D#63

AF26

H_DINV#0

J26

H_DINV#1

M26

H_DINV#2

V23

H_DINV#3

AC20

H_DSTBN#0

H23

H_DSTBN#1

M24

H_DSTBN#2

W24

H_DSTBN#3

AD23

H_DSTBP#0

G22

H_DSTBP#1

N25

H_DSTBP#2

Y25

H_DSTBP#3

AE24

H_A20M#

A6

H_FERR#

A5

H_IGNNE#

C4

H_INIT#

B3

H_INTR

C6

H_NMI

B4

H_STPCLK#

D5

H_SMI#

A3

H_D#[0..63] <7>

Change to same as
Chimay 4/6

OBSFN_C0
OBSFN_C1

OBSDATA_C0
OBSDATA_C1

OBSDATA_C2
OBSDATA_C3

OBSFN_D0
OBSFN_D1

OBSDATA_D0
OBSDATA_D1

OBSDATA_D2
OBSDATA_D3

ITPCLK/HOOK4

ITPCLK#/HOOK5

VCC_OBS_CD

RESET#/HOOK6

DBR#/HOOK7

SAMTE_BSH-030-01-L-D-ACONN@

XDP_BPM#5
XDP_BPM#4

XDP_BPM#3
XDP_BPM#2

XDP_BPM#1
XDP_BPM#0

R2200

XDP@

1K_0402_5%

H_PWRGOOD

C1455

XDP@

Removed at 5/30.(Follow
Chimay)

1 2

12

0.1U_0402_16V7K

H_PWRGOOD_R
XDP_HOOK1

XDP_TCK

ITP-XDP Connector

JP29

1

GND0

3

OBSFN_A0

5

OBSFN_A1

7

GND2

9

OBSDATA_A0

11

OBSDATA_A1

13

GND4

15

OBSDATA_A2

17

OBSDATA_A3

19

GND6

21

OBSFN_B0

23

OBSFN_B1

25

GND8

27

OBSDATA_B0

29

OBSDATA_B1

31

GND10

33

OBSDATA_B2

35

OBSDATA_B3

37

GND12

39

PWRGOOD/HOOK0

41

HOOK1

43

VCC_OBS_AB

45

HOOK2

47

HOOK3

49

GND14

51

SDA

53

SCL

55

TCK1

57

TCK0

59

GND16

Thermal Sensor ADM1032AR-2

+3VS

2

C2

0.1U_0402_16V4Z

C3

1 2

H_DINV#0 <7>
H_DINV#1 <7>
H_DINV#2 <7>
H_DINV#3 <7>

H_DSTBN#[0..3] <7>

H_DSTBP#[0..3] <7>

2200P_0402_50V7K

+3VS

R14

1 2

10K_0402_5%

PWM Fan Control circuit

H_A20M# <19>
H_FERR# <19>
H_IGNNE# <19>
H_INIT# <19>
H_INTR <19>
H_NMI <19>

H_STPCLK# <19>
H_SMI# <19>

FAN_PWM<30>

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/10/26 2006/07/26

Compal Secret Data

1

THERM#

2

Deciphered Date

H_THERMDA
H_THERMDC

+3VS

5

U2

P

INB

O

INA

G

TC7SH00FU_SSOP5

3

1

THERM#

CH751H-40_SC76

4

2

U1

1

VDD

2

D+

3

D­THERM#4GND

ADM1032AR-2_MSOP8

Address:1001_101

ICH_SMBDATA<13,14,15,20,25>

+5VS

D1

2

1

G

3

GND11

GND13

GND15
TRST#

GND17

ICH_SMBCLK<13,14,15,20,25>

4 5

GND1

GND3

GND5

GND7

GND9

TD0

TMS

2 1

6

D

S

TDI

XDP_DBRESET#_R

1 2

Change value in 5/02

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60

XDP_TDI
XDP_TMS
XDP_TDO
XDP_BPM#5
XDP_HOOK1
XDP_TRST#
XDP_TCK

CLK_CPU_XDP
CLK_CPU_XDP#

H_RESET#_R

XDP_TDO
XDP_TRST#
XDP_TDI
XDP_TMS
XDP_PRE

R2 54.9_0402_1%

1 2

R3 54.9_0402_1%

1 2

R4 54.9_0402_1%

1 2

R5 54.9_0402_1%

1 2

R2199 54.9_0402_1%@

1 2

R6 51_0402_1%

1 2

R7 54.9_0402_1%

1 2

This shall place near CPU

+VCCP+VCCP

R2201 1K_0402_1%

1 2

R2202 200_0402_1%

XDP@
XDP@

R2203
0_0402_5%

1 2

12

XDP@

Place R2203 w i t h i n 200ps (~1") to CPU

12

SCLK

SDATA

ALERT#

Q1
AO6402_TSOP6

ICH_SMBDATA

7

THERM_SCI#

6
5

ICH_SMBCLK
ICH_SMBDATA

1

C4

4.7U_0805_10V4Z

2

FAN

Title

Size Document Number Rev

Date: Sheet

ICH_SMBCLK

8

R13
10K_0402_5%

THERM_SCI# <20>

1

C5

0.1U_0402_16V4Z

2

12

ZD1

@

RLZ5.1B_LL34

ACES_85205-0200

Compal Electronics, Inc.

Yonah CPU in mFCPGA479

LA-3491P

1

R10

1K_0402_5%@

CLK_CPU_XDP <15>
CLK_CPU_XDP# <15>

H_RESET#
XDP_DBRESET#XDP_DBRESET#_R

JP3

1
2

CONN@

of

447Tuesday, March 20, 2007

+3VS

+VCCP

0.5

5

4

3

2

1

D D

V_CPU_GTLREF

Close to CPU pin AD26
within 500mils.

C C

B B

+VCCP

12

R21
1K_0402_1%

12

R24
2K_0402_1%

+VCC_CORE

R22
100_0402_1%

1 2

R23
100_0402_1%

1 2

VCCSENSE

VSSSENSE

Close to CPU pin
within 500mils.

CPU_BSEL CPU_BSEL2 CPU_BSEL1

133

166

00

0

12

12

R25

27.4_0402_1%

R26

54.9_0402_1%

R27

Length match within 25 mils
The trace width 18 mils space
7 mils

+1.5VS

1

C6

C7

2

0.01U_0402_16V7K

CPU_BSEL0

1

1

Resistor placed within

0.5" of CPU pin.Trace
should be at least 25
mils away from any
other toggling signal.

12

27.4_0402_1%

1

R28

12

54.9_0402_1%

1

2

10U_0805_10V4Z

VCCSENSE<40>
VSSSENSE<40>

H_PSI#<40>

CPU_VID0<40>
CPU_VID1<40>
CPU_VID2<40>
CPU_VID3<40>
CPU_VID4<40>
CPU_VID5<40>
CPU_VID6<40>

V_CPU_GTLREF

CPU_BSEL0<15>
CPU_BSEL1<15>
CPU_BSEL2<15>

+VCC_CORE

+VCCP

VCCSENSE
VSSSENSE

H_PSI#
CPU_VID0

CPU_VID1
CPU_VID2
CPU_VID3
CPU_VID4
CPU_VID5
CPU_VID6

CPU_BSEL0
CPU_BSEL1
CPU_BSEL2

COMP0
COMP1
COMP2
COMP3

JP1B

AF7

VCCSENSE

AE7

VSSSENSE

B26

VCCA

K6

VCCP

J6

VCCP

M6

VCCP

N6

VCCP

YONAH

VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP

PSI#
VID0

VID1
VID2
VID3
VID4
VID5
VID6

GTLREF
BSEL0

BSEL1
BSEL2

COMP0
COMP1
COMP2
COMP3

VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC

RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD

FOX_PZ47903-2741-42_YONAH

CONN@

W21

AD26

AB20
AA20
AF20
AE20
AB18
AB17
AA18
AA17
AD18
AD17
AC18
AC17
AF18
AF17

T6

R6

K21

J21
M21
N21
T21
R21
V21

V6

G21

AE6
AD6

AF5
AE5
AF4
AE3
AF2
AE2

B22
B23
C21

R26
U26

U1

V1

E7

D2

F6
D3
C1

AF1
D22
C23
C24
AA1
AA4
AB2
AA3

M4
N5

T2

V3

B2
C3

T22
B25

AB26

VSS

AA25

VSS

AD25

VSS

AE26

VSS

AB23

VSS

AC24

VSS

AF24

VSS

AE23

VSS

AA22

VSS

AD22

VSS

AC21

VSS

AF21

VSS

AB19

VSS

AA19

VSS

AD19

VSS

AC19

VSS

AF19

VSS

AE19

VSS

AB16

VSS

AA16

VSS

AD16

VSS

AC16

VSS

AF16

VSS

AE16

VSS

AB13

VSS

AA14

VSS

AD13

VSS

AC14

VSS

AF13

VSS

AE14

VSS

AB11

VSS

AA11

VSS

AD11

VSS

AC11

VSS

AF11

VSS

AE11

VSS

AB8

VSS

AA8

VSS

AD8

VSS

AC8

VSS

AF8

VSS

AE8

VSS

AA5

VSS

AD5

VSS

AC6

VSS

AF6

VSS

AB4

VSS

AC3

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

AF3
AE4
AB1
AA2
AD2
AE1
B6
C5
F5
E6
H6
J5
M5
L6
P6
R5
V5
U6
Y6
A4
D4
E3
H3
G4
K4
L3
P3
N4
T4
U3
Y3
W4
D1
C2
F2
G1

POWER, GROUNG, RESERVED SIGNALS AND NC

+VCC_CORE

JP1C

AE18

VCC

AE17

VCC

AB15

VCC

AA15

VCC

AD15

VCC

AC15

VCC

AF15

VCC

AE15

VCC

AB14

VCC

AA13

VCC

AD14

VCC

AC13

VCC

AF14

VCC

AE13

VCC

AB12

VCC

AA12

VCC

AD12

VCC

AC12

VCC

AF12

VCC

AE12

VCC

AB10

VCC

AB9

VCC

AA10

VCC

AA9

VCC

AD10

VCC

AD9

VCC

AC10

VCC

AC9

VCC

AF10

VCC

AF9

VCC

AE10

POWER, GROUND

VCC

AE9

VCC

AB7

VCC

AA7

VCC

AD7

VCC

AC7

VCC

B20

VCC

A20

VCC

F20

VCC

E20

VCC

B18

VCC

B17

VCC

A18

VCC

A17

VCC

D18

VCC

D17

VCC

C18

VCC

C17

VCC

F18

VCC

F17

VCC

E18

VCC

E17

VCC

B15

VCC

A15

VCC

D15

VCC

C15

VCC

F15

VCC

E15

VCC

B14

VCC

A13

VCC

D14

VCC

C13

VCC

F14

VCC

E13

VCC

B12

VCC

A12

VCC

D12

VCC

C12

VCC

F12

VCC

E12

VCC

B10

VCC

B9

VCC

A10

VCC

A9

VCC

D10

VCC

D9

VCC

C10

VCC

C9

VCC

F10

VCC

F9

VCC

E10

VCC

E9

VCC

B7

VCC

A7

VCC

F7

VCC

FOX_PZ47903-2741-42_YONAH

CONN@

YONAH

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

K1
J2
M2
N1
T1
R2
V2
W1
A26
D26
C25
F25
B24
A23
D23
E24
B21
C22
F22
E21
B19
A19
D19
C19
F19
E19
B16
A16
D16
C16
F16
E16
B13
A14
D13
C14
F13
E14
B11
A11
D11
C11
F11
E11
B8
A8
D8
C8
F8
E8
G26
K26
J25
M25
N26
T26
R25
V25
W26
H24
G23
K23
L24
P24
N23
T23
U24
Y24
W23
H21
J22
M22
L21
P21
R22
V22
U21
Y21

A A

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/10/26 2006/07/26

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

2

Date: Sheet

Compal Electronics, Inc.

Yonah CPU in mFCPGA479

LA-3491P

1

of

547Tuesday, March 20, 2007

0.5

5

4

3

2

1

D D

Place these capacitors on L8
(North side,Secondary Layer)

Place these capacitors on L8
(North side,Secondary Layer)

Place these capacitors on L8
(Sorth side,Secondary Layer)

C C

Place these capacitors on L8
(Sorth side,Secondary Layer)

+VCC_CORE

1

2

+VCC_CORE

1

2

+VCC_CORE

1

2

+VCC_CORE

1

2

C8
10U_0805_6.3V6M

C16
10U_0805_6.3V6M

C24
10U_0805_6.3V6M

C32
10U_0805_6.3V6M

1

C9
10U_0805_6.3V6M

2

1

C17
10U_0805_6.3V6M

2

1

C25
10U_0805_6.3V6M

2

1

C33
10U_0805_6.3V6M

2

1

C10
10U_0805_6.3V6M

2

1

C18
10U_0805_6.3V6M

2

1

C26
10U_0805_6.3V6M

2

1

C34
10U_0805_6.3V6M

2

1

C11
10U_0805_6.3V6M

2

1

C19
10U_0805_6.3V6M

2

1

C27
10U_0805_6.3V6M

2

1

C35
10U_0805_6.3V6M

2

1

C12
10U_0805_6.3V6M

2

1

C20
10U_0805_6.3V6M

2

1

C28
10U_0805_6.3V6M

2

1

C36
10U_0805_6.3V6M

2

1

C13
10U_0805_6.3V6M

2

1

C21
10U_0805_6.3V6M

2

1

C29
10U_0805_6.3V6M

2

1

C37
10U_0805_6.3V6M

2

1

C14
10U_0805_6.3V6M

2

1

C22
10U_0805_6.3V6M

2

1

C30
10U_0805_6.3V6M

2

1

C38
10U_0805_6.3V6M

2

1

C15
10U_0805_6.3V6M

2

1

C23
10U_0805_6.3V6M

2

1

C31
10U_0805_6.3V6M

2

1

C39
10U_0805_6.3V6M

2

Mid Frequence Decoupling

+VCC_CORE

330U_D2E_2.5VM_R7

1

+

C40

B B

330U_D2E_2.5VM_R7

C41

2

330U_D2E_2.5VM_R7@

1

1

+

+

C42

C43

2

2

330U_D2E_2.5VM_R7

1

+

2

330U_D2E_2.5VM_R7

1

+

C45

C44

2

330U_D2E_2.5VM_R7

1

+

2

ESR <= 1.5m ohm
Capacitor > 1980uF

02/26 Change C43 C44 C45 to

1.9mm height for PV build short
term solution

、、

+VCCP

1

+

C47

330U_D2E_2.5VM_R9

A A

2

5

1

C48

0.1U_0402_10V6K

2

1

C49

0.1U_0402_10V6K

2

1

2

4

C50

0.1U_0402_10V6K

1

C51

0.1U_0402_10V6K

2

1

C52

0.1U_0402_10V6K

2

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

1

C53

0.1U_0402_10V6K

2

3

2006/10/26 2006/07/26

Compal Secret Data

Deciphered Date

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

CPU Bypass capacitors

LA-3491P

647Tuesday, March 20, 2007

1

of

0.5

5

4

3

2

1

H_D#[0..63]<4>

D D

C C

H_XSCOMP/H_YSCOMP trace
width and spacing is 5/20.

B B

A A

12

R31

54.9_0402_1%

+VCCP

12

R32

54.9_0402_1%

R37

24.9_0402_1%

+VCCP

12

R48

12

R51

12

100_0402_1%

200_0402_1%

H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63

H_VREF
H_XRCOMP
H_XSCOMP
H_YRCOMP
H_YSCOMP
H_SWNG0
H_SWNG1

12

R38

24.9_0402_1%

Layout Note:
H_XRCOMP / H_YRCOMP / H_VREF / H_SWNG0 /
H_SWNG1 trace width and spacing is 18/20.

H_VREF

1

C57

2

0.1U_0402_16V4Z

5

K11
T10

W11

U11
T11

W9

W7

W6

AB7
AA9

W4
W3

W5
Y10
AB8

W2
AA4
AA7
AA2
AA6

AA10

AA1
AB4
AC9

AB11
AC11

AB3
AC2
AD1
AD9
AC1
AD7
AC6
AB5

AD10

AD4
AC8

J13
K13

W1

U3A

F1

HD0#

J1

HD1#

H1

HD2#

J6

HD3#

H3

HD4#

K2

HD5#

G1

HD6#

G2

HD7#

K9

HD8#

K1

HD9#

K7

HD10#

J8

HD11#

H4

HD12#

J3

HD13#
HD14#

G4

HD15#
HD16#
HD17#

T3

HD18#

U7

HD19#

U9

HD20#
HD21#
HD22#
HD23#

T1

HD24#

T8

HD25#

T4

HD26#
HD27#

U5

HD28#

T9

HD29#
HD30#

T5

HD31#
HD32#
HD33#
HD34#
HD35#

Y3

HD36#

Y7

HD37#
HD38#
HD39#
HD40#
HD41#
HD42#
HD43#
HD44#
HD45#
HD46#

Y8

HD47#
HD48#
HD49#
HD50#
HD51#
HD52#
HD53#
HD54#
HD55#
HD56#
HD57#
HD58#
HD59#
HD60#
HD61#
HD62#
HD63#

HVREF0
HVREF1

E1

HXRCOMP

E2

HXSCOMP

Y1

HYRCOMP

U1

HYSCOMP

E4

HXSWING
HYSWING

CALISTOGA_FCBGA1466~D

H9

HA3#

C9

HA4#

E11

HA5#

G11

HA6#

F11

HA7#

G12

HA8#

F9

HA9#

H11

HA10#

J12

HA11#

G14

HA12#

D9

HA13#

J14

HA14#

H13

HA15#

J15

HA16#

F14

HA17#

D12

HA18#

A11

HA19#

C11

HA20#

A12

HA21#

A13

HA22#

E13

HA23#

G13

HA24#

F12

HA25#

B12

HA26#

B14

HA27#

C12

HA28#

A14

HA29#

C14

HA30#

D14

HA31#

D8

HREQ#0

G8

HREQ#1

B8

HREQ#2

F8

HREQ#3

A8

HREQ#4

B9

HADSTB#0

C13

HADSTB#1

HCLKN
HCLKP

HDSTBN#0
HDSTBN#1
HDSTBN#2
HDSTBN#3
HDSTBP#0
HDSTBP#1
HDSTBP#2
HDSTBP#3

HDINV#0
HDINV#1
HDINV#2
HDINV#3

HCPURST#

HADS#

HTRDY#

HDPWR#

HDRDY#

HDEFER#

HHITM#

HHIT#

HLOCK#

HBREQ0#

HBNR#

HBPRI#

HDBSY#

HCPUSLP#

HRS0#
HRS1#
HRS2#

12

R46

12

R49

AG1
AG2

K4
T7
Y5
AC4
K3
T6
AA5
AC5

J7
W8
U3
AB10

B7
E8
E7
J9
H8
C3
D4
D3
B3
C7
C6
F6
A7
E3

B4
E6
D6

221_0603_1%

100_0402_1%

HOST

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

H_ADSTB#0
H_ADSTB#1

CLK_MCH_BCLK#
CLK_MCH_BCLK

H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3
H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3

H_DINV#0
H_DINV#1
H_DINV#2
H_DINV#3

H_RESET#
H_ADS#
H_TRDY#
H_DPWR#
H_DRDY#
H_DEFER#
H_HITM#
H_HIT#
H_LOCK#
H_BR0#
H_BNR#
H_BPRI#
H_DBSY#
H_CPUSLP#

H_RS#0
H_RS#1
H_RS#2

H_SWNG0

1

C55

2

0.1U_0402_16V4Z

4

+VCCP+VCCP

12

R47

12

R50

H_A#[3..31] <4>

H_REQ#[0..4] <4>

H_ADSTB#0 <4>
H_ADSTB#1 <4>

CLK_MCH_BCLK# <15>
CLK_MCH_BCLK <15>
H_DSTBN#[0..3] <4>

H_DSTBP#[0..3] <4>

H_DINV#0 <4>
H_DINV#1 <4>
H_DINV#2 <4>
H_DINV#3 <4>

H_RESET# <4>
H_ADS# <4>
H_TRDY# <4>
H_DPWR# <4>
H_DRDY# <4>
H_DEFER# <4>
H_HITM# <4>
H_HIT# <4>
H_LOCK# <4>
H_BR0# <4>
H_BNR# <4>
H_BPRI# <4>
H_DBSY# <4>
H_CPUSLP# <4>

H_RS#[0..2] <4>

221_0603_1%

H_SWNG1

1

C56

2

100_0402_1%

0.1U_0402_16V4Z

U3B

AE35

DMIRXN0

AF39

DMIRXN1

AG35

DMIRXN2

AH39

DMIRXN3

AC35

DMIRXP0

AE39

DMIRXP1

AF35

DMIRXP2

AG39

DMIRXP3

AE37

DMITXN0

AF41

DMITXN1

AG37

DMITXN2

AH41

DMITXN3

AC37

DMITXP0

AE41

DMITXP1

AF37

DMITXP2

AG41

DMITXP3

AY35

SM_CK0

AR1

SM_CK1

AW7

SM_CK2

AW40

SM_CK3

AW35

SM_CK0#

AT1

SM_CK1#

AY7

SM_CK2#

AY40

SM_CK3#

AU20

SM_CKE0

AT20

SM_CKE1

BA29

SM_CKE2

AY29

SM_CKE3

AW13

SM_CS0#

AW12

SM_CS1#

AY21

SM_CS2#

AW21

SM_CS3#

AL20

SM_OCDCOMP0

AF10

SM_OCDCOMP1

BA13

SM_ODT0

BA12

SM_ODT1

AY20

SM_ODT2

AU21

SM_ODT3

AV9

SM_RCOMPN

AT9

SM_RCOMPP

AK1

SM_VREF0

AK41

SM_VREF1

G28

PM_BMBUSY#

F25

PM_EXTTS0#

H26

PM_EXTTS1#

G6

PM_THERMTRIP#

AH33

PWROK

AH34

RSTIN#

K28

ICH_SYNC#

CALISTOGA_FCBGA1466~D

Layout Note:
Route as short
as possible

12

R42

R43

40.2_0402_1%

40.2_0402_1%

@

@

12

DMI

DDR MUXING

M_OCDOCMP0
M_OCDOCMP1

+1.8V

12

12

R41

12

R45

100_0402_1%

100_0402_1%

DMI_TXN0
DMI_TXN1
DMI_TXN2
DMI_TXN3

DMI_TXP0
DMI_TXP1
DMI_TXP2
DMI_TXP3

DMI_RXN0
DMI_RXN1
DMI_RXN2
DMI_RXN3

DMI_RXP0
DMI_RXP1
DMI_RXP2
DMI_RXP3

M_CLK_DDR0
M_CLK_DDR1
M_CLK_DDR2
M_CLK_DDR3

M_CLK_DDR#0
M_CLK_DDR#1
M_CLK_DDR#2
M_CLK_DDR#3

DDR_CKE0_DIMMA
DDR_CKE1_DIMMA
DDR_CKE2_DIMMB
DDR_CKE3_DIMMB

DDR_CS0_DIMMA#
DDR_CS1_DIMMA#
DDR_CS2_DIMMB#
DDR_CS3_DIMMB#

M_OCDOCMP0
M_OCDOCMP1

M_ODT0
M_ODT1
M_ODT2
M_ODT3

SMRCOMPN
SMRCOMPP

PM_BMBUSY#
DDR_THERM#
PM_EXTTS#1
H_THERMTRIP#
PWROK
PLTRST_R#

PWROK

DMI_TXN0<20>
DMI_TXN1<20>
DMI_TXN2<20>
DMI_TXN3<20>

DMI_TXP0<20>
DMI_TXP1<20>
DMI_TXP2<20>
DMI_TXP3<20>

DMI_RXN0<20>
DMI_RXN1<20>
DMI_RXN2<20>
DMI_RXN3<20>

DMI_RXP0<20>
DMI_RXP1<20>
DMI_RXP2<20>
DMI_RXP3<20>

M_CLK_DDR0<13>
M_CLK_DDR1<13>
M_CLK_DDR2<14>
M_CLK_DDR3<14>

M_CLK_DDR#0<13>
M_CLK_DDR#1<13>
M_CLK_DDR#2<14>
M_CLK_DDR#3<14>

DDR_CKE0_DIMMA<13>
DDR_CKE1_DIMMA<13>
DDR_CKE2_DIMMB<14>
DDR_CKE3_DIMMB<14>

DDR_CS0_DIMMA#<13>
DDR_CS1_DIMMA#<13>
DDR_CS2_DIMMB#<14>
DDR_CS3_DIMMB#<14>

+1.8V

R29 80.6_0402_1%
R30 80.6_0402_1%

PM_BMBUSY#<20>

DDR_THERM#<13,14>

DPRSLPVR<20,40>

VGATE_INTEL<20,40>

PM_POK<20,30>

V_DDR_MCH_REF<13,14>

R33 0_0402_5%

PLT_RST#<18,20,22,24,25,30,31>

R35 0_0402_5%@
R36 0_0402_5%

M_ODT0<13>
M_ODT1<13>
M_ODT2<14>
M_ODT3<14>

1 2
1 2

V_DDR_MCH_REF

1 2

H_THERMTRIP#<4,19>

R34 100_0402_1%

MCH_ICH_SYNC#<18>

1 2
1 2

Layout Note:
V_DDR_MCH_REF
trace width and
spacing is 20/20.

V_DDR_MCH_REF

1

C54

2

0.1U_0402_16V4Z

Stuff R42 & R43 for A1 Calistoga

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/10/26 2006/07/26

Compal Secret Data

Deciphered Date

2

CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8

CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG16

CFG

CFG17
CFG18
CFG19
CFG20

G_CLKP
G_CLKN

D_REF_CLKN
D_REF_CLKP

CLKNC

D_REF_SSCLKN
D_REF_SSCLKP

CLK_REQ#

NC0
NC1
NC2
NC3
NC4
NC5
NC6
NC7
NC8

NC9
NC10
NC11
NC12
NC13
NC14
NC15
NC16
NC17
NC18

RESERVED1
RESERVED2

PM

RESERVED3
RESERVED4
RESERVED5
RESERVED6
RESERVED7
RESERVED8

RESERVED9
RESERVED10
RESERVED11
RESERVED12
RESERVED13

RESERVED

DDR_THERM#

PM_EXTTS#1

Title

Size Document Number Rev

Date: Sheet

Description at page11.

MCH_CLKSEL0

K16

MCH_CLKSEL1

K18

MCH_CLKSEL2

J18

CFG3

F18

CFG4

E15

CFG5

F15

CFG6

E18

CFG7

D19

CFG8

D16

CFG9

G16

CFG10

E16

CFG11

D15

CFG12

G15

CFG13

K15

CFG14

C15

CFG15

H16

CFG16

G18

CFG17

H15

CFG18

J25

CFG19

K27

CFG20

J26

CLK_MCH_3GPLL

AG33

CLK_MCH_3GPLL#

AF33

CLK_MCH_REF#

A27

CLK_MCH_REF

A26

MCH_SSCDREFCLK#

C40

MCH_SSCDREFCLK

D41

GMCH_H32

H32

A3
A39
A4
A40
AW1
AW41
AY1
BA1
BA2
BA3
BA39
BA40
BA41
C1
AY41
B2
B41
C41
D1

T32
R32
F3
F7
AG11
AF11
H7
J19
A41
A34
D28
D27
A35

R39

10K_0402_5%

R40

10K_0402_5%@

R44

1 2

0_0402_5%

PAD
PAD

PAD
PAD
PAD

PAD
PAD

PAD

12

12

CLKREQC#GMCH_H32

MCH_CLKSEL0 <15>
MCH_CLKSEL1 <15>

MCH_CLKSEL2 <15>

T1
T2

CFG5 <11>

T3

CFG7 <11>

T4

CFG9 <11>

T5

CFG11 <11>

CFG12 <11>

CFG13 <11>

T6
T7

CFG16 <11>

T8

CFG18 <11>

CFG19 <11>

CFG20 <11>

CLK_MCH_3GPLL <15>

CLK_MCH_3GPLL# <15>

CLK_MCH_REF# <15>

CLK_MCH_REF <15>

MCH_SSCDREFCLK# <15>
MCH_SSCDREFCLK <15>

+3VS

CLKREQC# <15>

Compal Electronics, Inc.

Calistoga (1/6)

LA-3491P

747Tuesday, March 20, 2007

1

0.5

of

5

D D

4

3

2

1

DDR_A_BS#0<13>
DDR_A_BS#1<13>
DDR_A_BS#2<13>

DDR_A_DM[0..7]<13>

DDR_A_DQS[0..7]<13>

C C

DDR_A_DQS#[0..7]<13>

DDR_A_MA[0..13]<13>

B B

DDR_A_CAS#<13>
DDR_A_RAS#<13>

DDR_A_WE#<13>

T9 PAD

DDR_A_BS#0
DDR_A_BS#1
DDR_A_BS#2

DDR_A_DM0
DDR_A_DM1
DDR_A_DM2
DDR_A_DM3
DDR_A_DM4
DDR_A_DM5
DDR_A_DM6
DDR_A_DM7

DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7

DDR_A_DQS#0
DDR_A_DQS#1
DDR_A_DQS#2
DDR_A_DQS#3
DDR_A_DQS#4
DDR_A_DQS#5
DDR_A_DQS#6
DDR_A_DQS#7

DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5

DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11 DDR_B_MA11
DDR_A_MA12
DDR_A_MA13

DDR_A_CAS#
DDR_A_RAS#
DDR_A_WE#
SA_RCVENIN#
SA_RCVENOUT#

U3D

AU12

SA_BS0

AV14

SA_BS1

BA20

SA_BS2

AJ33

SA_DM0

AM35

SA_DM1

AL26

SA_DM2

AN22

SA_DM3

AM14

SA_DM4

AL9

SA_DM5

AR3

SA_DM6

AH4

SA_DM7

AK33

SA_DQS0

AT33

SA_DQS1

AN28

SA_DQS2

AM22

SA_DQS3

AN12

SA_DQS4

AN8

SA_DQS5

AP3

SA_DQS6

AG5

SA_DQS7

AK32

SA_DQS0#

AU33

SA_DQS1#

AN27

SA_DQS2#

AM21

SA_DQS3#

AM12

SA_DQS4#

AL8

SA_DQS5#

AN3

SA_DQS6#

AH5

SA_DQS7#

AY16

SA_MA0

AU14

SA_MA1

AW16

SA_MA2

BA16

SA_MA3

BA17

SA_MA4

AU16

SA_MA5

AV17

SA_MA6

AU17

SA_MA7

AW17

SA_MA8

AT16

SA_MA9

AU13

SA_MA10

AT17

SA_MA11

AV20

SA_MA12

AV12

SA_MA13

AY13

SA_CAS#

AW14

SA_RAS#

AY14

SA_WE#

AK23

SA_RCVENIN#

AK24

SA_RCVENOUT#

CALISTOGA_FCBGA1466~D

SA_DQ0
SA_DQ1
SA_DQ2
SA_DQ3
SA_DQ4
SA_DQ5
SA_DQ6
SA_DQ7
SA_DQ8

SA_DQ9
SA_DQ10
SA_DQ11
SA_DQ12
SA_DQ13
SA_DQ14
SA_DQ15
SA_DQ16
SA_DQ17
SA_DQ18
SA_DQ19
SA_DQ20
SA_DQ21
SA_DQ22
SA_DQ23
SA_DQ24
SA_DQ25
SA_DQ26
SA_DQ27
SA_DQ28
SA_DQ29
SA_DQ30
SA_DQ31
SA_DQ32
SA_DQ33
SA_DQ34
SA_DQ35
SA_DQ36
SA_DQ37
SA_DQ38
SA_DQ39

DDR SYS MEMORY A

SA_DQ40
SA_DQ41
SA_DQ42
SA_DQ43
SA_DQ44
SA_DQ45
SA_DQ46
SA_DQ47
SA_DQ48
SA_DQ49
SA_DQ50
SA_DQ51
SA_DQ52
SA_DQ53
SA_DQ54
SA_DQ55
SA_DQ56
SA_DQ57
SA_DQ58
SA_DQ59
SA_DQ60
SA_DQ61
SA_DQ62
SA_DQ63

AJ35
AJ34
AM31
AM33
AJ36
AK35
AJ32
AH31
AN35
AP33
AR31
AP31
AN38
AM36
AM34
AN33
AK26
AL27
AM26
AN24
AK28
AL28
AM24
AP26
AP23
AL22
AP21
AN20
AL23
AP24
AP20
AT21
AR12
AR14
AP13
AP12
AT13
AT12
AL14
AL12
AK9
AN7
AK8
AK7
AP9
AN9
AT5
AL5
AY2
AW2
AP1
AN2
AV2
AT3
AN1
AL2
AG7
AF9
AG4
AF6
AG9
AH6
AF4
AF8

DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63

DDR_A_D[0..63] <13> DDR_B_D[0..63] <14>

DDR_B_BS#0<14>
DDR_B_BS#1<14>
DDR_B_BS#2<14>

DDR_B_DM[0..7]<14>

DDR_B_DQS[0..7]<14>

DDR_B_DQS#[0..7]<14>

DDR_B_MA[0..13]<14>

DDR_B_CAS#<14>

DDR_B_RAS#<14>

DDR_B_WE#<14>

T10 PAD
T12 PADT11 PAD

DDR_B_BS#0
DDR_B_BS#1
DDR_B_BS#2

DDR_B_DM0
DDR_B_DM1
DDR_B_DM2
DDR_B_DM3
DDR_B_DM4
DDR_B_DM5
DDR_B_DM6
DDR_B_DM7

DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4
DDR_B_DQS5
DDR_B_DQS6
DDR_B_DQS7

DDR_B_DQS#0
DDR_B_DQS#1
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS#4
DDR_B_DQS#5
DDR_B_DQS#6
DDR_B_DQS#7

DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6DDR_A_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10

DDR_B_MA12
DDR_B_MA13

DDR_B_CAS#
DDR_B_RAS#
DDR_B_WE#
SB_RCVENIN#
SB_RCVENOUT#

U3E

AT24

SB_BS0

AV23

SB_BS1

AY28

SB_BS2

AK36

SB_DM0

AR38

SB_DM1

AT36

SB_DM2

BA31

SB_DM3

AL17

SB_DM4

AH8

SB_DM5

BA5

SB_DM6

AN4

SB_DM7

AM39

SB_DQS0

AT39

SB_DQS1

AU35

SB_DQS2

AR29

SB_DQS3

AR16

SB_DQS4

AR10

SB_DQS5

AR7

SB_DQS6

AN5

SB_DQS7

AM40

SB_DQS0#

AU39

SB_DQS1#

AT35

SB_DQS2#

AP29

SB_DQS3#

AP16

SB_DQS4#

AT10

SB_DQS5#

AT7

SB_DQS6#

AP5

SB_DQS7#

AY23

SB_MA0

AW24

SB_MA1

AY24

SB_MA2

AR28

SB_MA3

AT27

SB_MA4

AT28

SB_MA5

AU27

SB_MA6

AV28

SB_MA7

AV27

SB_MA8

AW27

SB_MA9

AV24

SB_MA10

BA27

SB_MA11

AY27

SB_MA12

AR23

SB_MA13

AR24

SB_CAS#

AU23

SB_RAS#

AR27

SB_WE#

AK16

SB_RCVENIN#

AK18

SB_RCVENOUT#

CALISTOGA_FCBGA1466~D

AK39

SB_DQ0

AJ37

SB_DQ1

AP39

SB_DQ2

AR41

SB_DQ3

AJ38

SB_DQ4

AK38

SB_DQ5

AN41

SB_DQ6

AP41

SB_DQ7

AT40

SB_DQ8

AV41

SB_DQ9

AU38

SB_DQ10

AV38

SB_DQ11

AP38

SB_DQ12

AR40

SB_DQ13

AW38

SB_DQ14

AY38

SB_DQ15

BA38

SB_DQ16

AV36

SB_DQ17

AR36

SB_DQ18

AP36

SB_DQ19

BA36

SB_DQ20

AU36

SB_DQ21

AP35

SB_DQ22

AP34

SB_DQ23

AY33

SB_DQ24

BA33

SB_DQ25

AT31

SB_DQ26

AU29

SB_DQ27

AU31

SB_DQ28

AW31

SB_DQ29

AV29

SB_DQ30

AW29

SB_DQ31

AM19

SB_DQ32

AL19

SB_DQ33

AP14

SB_DQ34

AN14

SB_DQ35

AN17

SB_DQ36

AM16

SB_DQ37

AP15

SB_DQ38

AL15

SB_DQ39
SB_DQ40
SB_DQ41
SB_DQ42
SB_DQ43
SB_DQ44
SB_DQ45
SB_DQ46
SB_DQ47
SB_DQ48
SB_DQ49
SB_DQ50
SB_DQ51
SB_DQ52
SB_DQ53
SB_DQ54
SB_DQ55
SB_DQ56
SB_DQ57
SB_DQ58
SB_DQ59
SB_DQ60
SB_DQ61
SB_DQ62
SB_DQ63

AJ11
AH10
AJ9
AN10
AK13
AH11
AK10
AJ8
BA10
AW10
BA4
AW4
AY10
AY9
AW5
AY5
AV4
AR5
AK4
AK3
AT4
AK5
AJ5
AJ3

DDR SYS MEMORY B

DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63

A A

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/10/26 2006/07/26

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

2

Date: Sheet

Compal Electronics, Inc.

Calistoga (2/6)

LA-3491P

847Tuesday, March 20, 2007

1

0.5

of

5

D D

LVDSA0+<17>
LVDSA1+<17>

LVDSA2+<17>
LVDSA0-<17>

LVDSA1-<17>

LVDSA2-<17>

LVDSB0+<17>
LVDSB1+<17>
LVDSB2+<17>

LVDSB0-<17>
LVDSB1-<17>
LVDSB2-<17>

LVDSAC+<17>
LVDSAC-<17>

LVDSBC+<17>

+3VS

LCD_CLK<17>

LCD_DAT<17>
ENAVDD<17>

1 2
1 2
1 2

CRT_SMBCLK<16>

CRT_SMBDAT<16>

CRT_BLU<16>
CRT_GRN<16>
CRT_RED<16>

LVDSBC-<17>

BKLT_CTL<17>
ENABLT<17,30>

R2211 10K_0402_5%
R2212 10K_0402_5%

R54 1.5K_0402_1%

+1.5VS

+1.5VS

VSYNC<16>
HSYNC<16>

R53

R55

10K_0402_5%

LCD_CLK
LCD_DAT

1 2

100K_0402_5%

+3VS

12

PACDN042_SOT23~D@

C C

B B

12

R56

ENABLT

10K_0402_5%

3

D2

1

+1.5VS
+1.5VS
+1.5VS

VSYNCHSYNC

2

R2172 0_0402_5%
R2173 0_0402_5%
R2174 0_0402_5%

1 2
1 2

LCD_CLK
LCD_DAT

ENAVDD

COMPS
LUMA

CRMA

1 2

R57
0_0603_5%

1 2

R2251

0_0402_5%

R58

255_0402_1%

4

LVDSA0+
LVDSA1+
LVDSA2+

LVDSA0­LVDSA1­LVDSA2-

LVDSB0+
LVDSB1+
LVDSB2+

LVDSB0­LVDSB1­LVDSB2-

LVDSAC+
LVDSAC­LVDSBC+
LVDSBC-

BKLT_CTL
ENABLT

VSYNC
HSYNC

CRT_IREF

12

3

PEGCOMP tr ace width

U3C

H27

SDVOCTRL_DATA

H28

SDVOCTRL_CLK

B37

LA_DATA0

B34

LA_DATA1

A36

LA_DATA2

C37

LA_DATA#0

B35

LA_DATA#1

A37

LA_DATA#2

F30

LB_DATA0

D29

LB_DATA1

F28

LB_DATA2

G30

LB_DATA#0

D30

LB_DATA#1

F29

LB_DATA#2

A32

LA_CLK

A33

LA_CLK#

E26

LB_CLK

E27

LB_CLK#

D32

LBKLT_CTL

J30

LBKLT_EN

H30

LCTLA_CLK

H29

LCTLB_DATA

G26

LDDC_CLK

G25

LDDC_DATA

F32

LIBG

12

LVDD_EN

B38

LIBG

C35

LVBG

C33

LVREFH

C32

LVREFL

A16

TVDAC_A

C18

TVDAC_B

A19

TVDAC_C

J20

TV_IREF

B16

TV_IRTNA

B18

TV_IRTNB

B19

TV_IRTNC

J29

TV_DCONSEL1

K30

TV_DCONSEL0

C26

DDCCLK

C25

DDCDATA

H23

VSYNC

G23

HSYNC

E23

BLUE

D23

BLUE#

C22

GREEN

B22

GREEN#

A21

RED

B21

RED#

J22

CRT_IREF

CALISTOGA_FCBGA1466~D

LVDS

TV CRT

and spacing is 18/25 mils.

PEGCOMP

D40

EXP_COMPI

EXP_RXN0
EXP_RXN1
EXP_RXN2
EXP_RXN3
EXP_RXN4
EXP_RXN5
EXP_RXN6
EXP_RXN7
EXP_RXN8

EXP_RXN9
EXP_RXN10
EXP_RXN11
EXP_RXN12
EXP_RXN13
EXP_RXN14
EXP_RXN15

EXP_RXP0

EXP_RXP1

EXP_RXP2

EXP_RXP3

EXP_RXP4

EXP_RXP5

EXP_RXP6

EXP_RXP7

EXP_RXP8

EXP_RXP9
EXP_RXP10
EXP_RXP11
EXP_RXP12
EXP_RXP13
EXP_RXP14
EXP_RXP15

EXP_TXN0

EXP_TXN1

EXP_TXN2

EXP_TXN3

EXP_TXN4

EXP_TXN5

EXP_TXN6

EXP_TXN7

EXP_TXN8

EXP_TXN9
EXP_TXN10
EXP_TXN11
EXP_TXN12
EXP_TXN13
EXP_TXN14
EXP_TXN15

EXP_TXP0

EXP_TXP1

EXP_TXP2

EXP_TXP3

EXP_TXP4

EXP_TXP5

EXP_TXP6

EXP_TXP7

EXP_TXP8

EXP_TXP9

EXP_TXP10
EXP_TXP11
EXP_TXP12
EXP_TXP13
EXP_TXP14
EXP_TXP15

D38
F34

G38
H34
J38
L34
M38
N34
P38
R34
T38
V34
W38
Y34
AA38
AB34
AC38

D34
F38
G34
H38
J34
L38
M34
N38
P34
R38
T34
V38
W34
Y38
AA34
AB38

F36
G40
H36
J40
L36
M40
N36
P40
R36
T40
V36
W40
Y36
AA40
AB36
AC40

D36
F40
G36
H40
J36
L40
M36
N40
P36
R40
T36
V40
W36
Y40
AA36
AB40

EXP_COMPO

PCI-EXPRESS GRAPHICS

R52

24.9_0402_1%

1 2

+1.5VS_PCIE

2

1

A A

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/10/26 2006/07/26

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

2

Date: Sheet

Compal Electronics, Inc.

Calistoga (3/6)

LA-3491P

947Tuesday, March 20, 2007

1

0.5

of

5

4

3

2

1

+1.5VS_DPLLA +1.5VS_DPLLB

Place close to Pin G41

+2.5VS

C59

D D

C C

1

C76

C77

2

4.7U_0805_10V4Z

B B

1

C91

2

1

0.22U_0603_10V7K

2

1

+

2

1

2

2.2U_0805_16V4Z

MCH_A6

1

C84

2

MCH_D2

C93

C94

0.22U_0603_10V7K

+1.5VS

+VCCP

C67

220U_D2_2VM_R9

0.47U_0603_10V7K

MCH_AB1

1

2

0.47U_0603_10V7K

U3H

AC14

VTT0

AB14

VTT1

W14

VTT2

V14

VTT3

T14

VTT4

R14

VTT5

P14

VTT6

N14

VTT7

M14

VTT8

L14

VTT9

AD13

VTT10

AC13

VTT11

AB13

VTT12

AA13

VTT13

Y13

VTT14

W13

VTT15

V13

VTT16

U13

VTT17

T13

VTT18

R13

VTT19

N13

VTT20

M13

VTT21

L13

VTT22

AB12

VTT23

AA12

VTT24

Y12

VTT25

W12

VTT26

V12

VTT27

U12

VTT28

T12

VTT29

R12

VTT30

P12

VTT31

N12

VTT32

M12

VTT33

L12

VTT34

R11

VTT35

P11

VTT36

N11

VTT37

M11

VTT38

R10

VTT39

P10

VTT40

N10

VTT41

M10

VTT42

P9

VTT43

N9

VTT44

M9

VTT45

R8

VTT46

P8

VTT47

N8

VTT48

M8

VTT49

P7

VTT50

N7

VTT51

M7

VTT52

R6

VTT53

P6

VTT54

M6

VTT55

A6

VTT56

R5

VTT57

P5

VTT58

N5

VTT59

M5

VTT60

P4

VTT61

N4

VTT62

M4

VTT63

R3

VTT64

P3

VTT65

N3

VTT66

M3

VTT67

R2

VTT68

P2

VTT69

M2

VTT70

D2

VTT71

AB1

VTT72

R1

VTT73

P1

VTT74

N1

VTT75

M1

VTT76

AG14

VCCAUX32

AF14

VCCAUX33

AE14

VCCAUX34

Y14

VCCAUX35

AF13

VCCAUX36

AE13

VCCAUX37

AF12

VCCAUX38

AE12

VCCAUX39

AD12

VCCAUX40

CALISTOGA_FCBGA1466~D

P O W E R

VCC_SYNC

VCCTX_LVDS0
VCCTX_LVDS1
VCCTX_LVDS2

VCC3G0
VCC3G1
VCC3G2
VCC3G3
VCC3G4
VCC3G5
VCC3G6

VCCA_3GPLL

VCCA_3GBG
VSSA_3GBG

VCCA_CRTDAC0
VCCA_CRTDAC1
VSSA_CRTDAC2

VCCA_DPLLA
VCCA_DPLLB

VCCA_HPLL

VCCA_LVDS
VSSA_LVDS

VCCA_MPLL

VCCA_TVBG

VSSA_TVBG

VCCA_TVDACA0
VCCA_TVDACA1
VCCA_TVDACB0
VCCA_TVDACB1
VCCA_TVDACC0
VCCA_TVDACC1

VCCD_HMPLL0
VCCD_HMPLL1

VCCD_LVDS0
VCCD_LVDS1
VCCD_LVDS2

VCCD_TVDAC

VCCDQ_TVDAC

VCCHV0
VCCHV1
VCCHV2

VCCAUX0
VCCAUX1
VCCAUX2
VCCAUX3
VCCAUX4
VCCAUX5
VCCAUX6
VCCAUX7
VCCAUX8

VCCAUX9
VCCAUX10
VCCAUX11
VCCAUX12
VCCAUX13
VCCAUX14
VCCAUX15
VCCAUX16
VCCAUX17
VCCAUX18
VCCAUX19
VCCAUX20
VCCAUX21
VCCAUX22
VCCAUX23
VCCAUX24
VCCAUX25
VCCAUX26
VCCAUX27
VCCAUX28
VCCAUX29
VCCAUX30
VCCAUX31

H22

B30
C30
A30

AB41
AJ41
L41
N41
R41
V41
Y41

AC33
G41
H41

E21
F21
G21

B26
C39
AF1

A38
B39

AF2
H20

G20

E19
F19
C20
D20
E20
F20

AH1
AH2

A28
B28
C28

D21
H19

A23
B23
B25

AK31
AF31
AE31
AC31
AL30
AK30
AJ30
AH30
AG30
AF30
AE30
AD30
AC30
AG29
AF29
AE29
AD29
AC29
AG28
AF28
AE28
AH22
AJ21
AH21
AJ20
AH20
AH19
P19
P16
AH15
P15
AH14

0.1U_0402_16V4Z

1 2

W=40 mils

+1.5VS_3GPLL
+2.5VS

MCH_CRTDAC

+1.5VS_DPLLA
+1.5VS_DPLLB
+1.5VS_HPLL

+2.5VS

+1.5VS_MPLL

+1.5VS

+1.5VS

+1.5VS

1

C92

2

1

2

C85

0.1U_0402_16V4Z

0.1U_0402_16V4Z

+2.5VS

10U_0805_6.3V6M

1

+

2

C64
220U_D2_2VM_R9

1

C74

2

R2221

12

0_0402_5%

R2222

12

0_0402_5%

R2223

12

0_0402_5%

R2224

12

0_0402_5%

R2225

12

0_0402_5%

+3VS

1

C86
10U_0805_6.3V6M

2

+1.5VS_PCIE

C65

1

2

1

2

2200P_0402_50V7K

+1.5VS

+1.5VS

C66

1

10U_0805_6.3V6M

2

L3

C75

0.1U_0402_16V4Z

12/28

R60

0_0805_5%

1 2

12

+1.5VS

BLM11A601S_0603

+2.5VS

1

2

+2.5VS

+1.5VS_DPLLA +1.5VS_DPLLB

C58

0.1U_0402_16V4Z

C62

0.1U_0402_16V4Z

1

2

L1

CHB1608U301_0603

1

330U_D2E_2.5VM

C60

+

2

12

PCI-E/MEM/PSB PLL decoupling

+1.5VS+1.5VS_3GPLL

3GPLL

R67

0_0805_5%

1

C88
10U_0805_6.3V6M

2

R65

0_0805_5%

12

12

C80

@

1

2

0.1U_0402_16V4Z

10_0402_5%@

R64

1 2

0.5_0805_1%

1

1

C79

C78

2

2

0.1U_0402_16V4Z
10U_0805_6.3V6M

+1.5VS_MPLL

45mA Max. 45mA Max.

1

C87

2

0.1U_0402_16V4Z

+1.5VS_HPLL

1

C89

2

+VCCP

R70

0.1U_0402_16V4Z

C63

1

2

R68

0_0805_5%

1

C90
10U_0805_6.3V6M

2

0.1U_0402_16V4Z

D3
CH751H-40_SOD323

@

1 2
12

+2.5VS +3VS

1 2

R59

0_1206_5%

L2
CHB1608U301_0603@

12

+1.5VS+1.5VS

1

+

@

330U_D2E_2.5VM

C61

2

12

+1.5VS+1.5VS

+1.5VS

D4
CH751H-40_SOD323

@

1 2
12

R71

10_0402_5%@

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETE NT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/10/26 2006/07/26

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

2

Date: Sheet

Compal Electronics, Inc.

Calistoga (4/6)

LA-3491P

10 47Tuesday, Ma rch 20, 2007

1

0.5

of

5

4

3

2

1

Strap Pin Table

CFG[3:17] have internal pull up

+VCCP

D D

1

C99

2

0.22U_0603_10V7K

10U_0805_6.3V6M

1

C106

C107

2

10U_0805_6.3V6M

C C

C115

B B

1

1

C101

C100

2

2

0.22U_0603_10V7K

C109

220U_D2_2VM_R9

0.22U_0603_10V7K

1

1

C108

2

2

1U_0603_10V4Z

1

1

C110

+

+

2

2

330U_D2E_2.5VM_R9

@

1

+

2

330U_D2E_2.5VM_R9

@

+VCCP

U3F

AD27

VCC_NCTF0

AC27

VCC_NCTF1

AB27

VCC_NCTF2

AA27

VCC_NCTF3

Y27

VCC_NCTF4

W27

VCC_NCTF5

V27

VCC_NCTF6

U27

VCC_NCTF7

T27

VCC_NCTF8

R27

VCC_NCTF9

AD26

VCC_NCTF10

AC26

VCC_NCTF11

AB26

VCC_NCTF12

AA26

VCC_NCTF13

Y26

VCC_NCTF14

W26

VCC_NCTF15

V26

VCC_NCTF16

U26

VCC_NCTF17

T26

VCC_NCTF18

R26

VCC_NCTF19

AD25

VCC_NCTF20

AC25

VCC_NCTF21

AB25

VCC_NCTF22

AA25

VCC_NCTF23

Y25

VCC_NCTF24

W25

VCC_NCTF25

V25

VCC_NCTF26

U25

VCC_NCTF27

T25

VCC_NCTF28

R25

VCC_NCTF29

AD24

VCC_NCTF30

AC24

VCC_NCTF31

AB24

VCC_NCTF32

AA24

VCC_NCTF33

Y24

VCC_NCTF34

W24

VCC_NCTF35

V24

VCC_NCTF36

U24

VCC_NCTF37

T24

VCC_NCTF38

R24

VCC_NCTF39

AD23

VCC_NCTF40

V23

VCC_NCTF41

U23

VCC_NCTF42

T23

VCC_NCTF43

R23

VCC_NCTF44

AD22

VCC_NCTF45

V22

VCC_NCTF46

U22

VCC_NCTF47

T22

VCC_NCTF48

R22

VCC_NCTF49

AD21

VCC_NCTF50

V21

VCC_NCTF51

U21

VCC_NCTF52

T21

VCC_NCTF53

R21

VCC_NCTF54

AD20

VCC_NCTF55

V20

VCC_NCTF56

U20

VCC_NCTF57

T20

VCC_NCTF58

R20

VCC_NCTF59

AD19

VCC_NCTF60

V19

VCC_NCTF61

U19

VCC_NCTF62

T19

VCC_NCTF63

AD18

VCC_NCTF64

AC18

VCC_NCTF65

AB18

VCC_NCTF66

AA18

VCC_NCTF67

Y18

VCC_NCTF68

W18

VCC_NCTF69

V18

VCC_NCTF70

U18

VCC_NCTF71

T18

VCC_NCTF72

M19

VCC100

L19

VCC101

N18

VCC102

M18

VCC103

L18

VCC104

P17

VCC105

N17

VCC106

M17

VCC107

N16

VCC108

M16

VCC109

L16

VCC110

CALISTOGA_FCBGA1466~D

VCCAUX_NCTF0
VCCAUX_NCTF1
VCCAUX_NCTF2
VCCAUX_NCTF3
VCCAUX_NCTF4
VCCAUX_NCTF5
VCCAUX_NCTF6
VCCAUX_NCTF7
VCCAUX_NCTF8

VCCAUX_NCTF9
VCCAUX_NCTF10
VCCAUX_NCTF11
VCCAUX_NCTF12
VCCAUX_NCTF13
VCCAUX_NCTF14
VCCAUX_NCTF15
VCCAUX_NCTF16
VCCAUX_NCTF17
VCCAUX_NCTF18
VCCAUX_NCTF19
VCCAUX_NCTF20
VCCAUX_NCTF21
VCCAUX_NCTF22
VCCAUX_NCTF23
VCCAUX_NCTF24
VCCAUX_NCTF25
VCCAUX_NCTF26
VCCAUX_NCTF27
VCCAUX_NCTF28
VCCAUX_NCTF29
VCCAUX_NCTF30
VCCAUX_NCTF31
VCCAUX_NCTF32
VCCAUX_NCTF33
VCCAUX_NCTF34
VCCAUX_NCTF35
VCCAUX_NCTF36

P O W E R

VCCAUX_NCTF37
VCCAUX_NCTF38
VCCAUX_NCTF39
VCCAUX_NCTF40
VCCAUX_NCTF41
VCCAUX_NCTF42
VCCAUX_NCTF43
VCCAUX_NCTF44
VCCAUX_NCTF45
VCCAUX_NCTF46
VCCAUX_NCTF47
VCCAUX_NCTF48
VCCAUX_NCTF49
VCCAUX_NCTF50
VCCAUX_NCTF51
VCCAUX_NCTF52
VCCAUX_NCTF53
VCCAUX_NCTF54
VCCAUX_NCTF55
VCCAUX_NCTF56
VCCAUX_NCTF57

VSS_NCTF0
VSS_NCTF1
VSS_NCTF2
VSS_NCTF3
VSS_NCTF4
VSS_NCTF5
VSS_NCTF6
VSS_NCTF7
VSS_NCTF8

VSS_NCTF9
VSS_NCTF10
VSS_NCTF11
VSS_NCTF12

VCC_SM100

VCC_SM101

VCC_SM102

VCC_SM103

VCC_SM104

VCC_SM105

VCC_SM106

VCC_SM107

AG27
AF27
AG26
AF26
AG25
AF25
AG24
AF24
AG23
AF23
AG22
AF22
AG21
AF21
AG20
AF20
AG19
AF19
R19
AG18
AF18
R18
AG17
AF17
AE17
AD17
AB17
AA17
W17
V17
T17
R17
AG16
AF16
AE16
AD16
AC16
AB16
AA16
Y16
W16
V16
U16
T16
R16
AG15
AF15
AE15
AD15
AC15
AB15
AA15
Y15
W15
V15
U15
T15
R15

AE27
AE26
AE25
AE24
AE23
AE22
AE21
AE20
AE19
AE18
AC17
Y17
U17

AR6
AP6
AN6
AL6
AK6
AJ6
AV1
AJ1

+1.5VS

VCCSM_LF2
VCCSM_LF1

C117

+1.8V

0.47U_0603_10V7K

1

1

C118

2

2

0.47U_0603_10V7K

Place near pin AV1 & AJ1

A A

+VCCP

U3G

AA33

VCC0

W33

VCC1

P33

VCC2

N33

VCC3

L33

VCC4

J33

VCC5

AA32

VCC6

Y32

VCC7

W32

VCC8

V32

VCC9

P32

VCC10

N32

VCC11

M32

VCC12

L32

VCC13

J32

VCC14

AA31

VCC15

W31

VCC16

V31

VCC17

T31

VCC18

R31

VCC19

P31

VCC20

N31

VCC21

M31

VCC22

AA30

VCC23

Y30

VCC24

W30

VCC25

V30

VCC26

U30

VCC27

T30

VCC28

R30

VCC29

P30

VCC30

N30

VCC31

M30

VCC32

L30

VCC33

AA29

VCC34

Y29

VCC35

W29

VCC36

V29

VCC37

U29

VCC38

R29

VCC39

P29

VCC40

M29

VCC41

L29

VCC42

AB28

VCC43

AA28

VCC44

Y28

VCC45

V28

VCC46

U28

VCC47

T28

VCC48

R28

VCC49

P28

VCC50

N28

VCC51

M28

VCC52

L28

VCC53

P27

VCC54

N27

VCC55

M27

VCC56

L27

VCC57

P26

VCC58

N26

VCC59

L26

VCC60

N25

VCC61

M25

VCC62

L25

VCC63

P24

VCC64

N24

VCC65

M24

VCC66

AB23

VCC67

AA23

VCC68

Y23

VCC69

P23

VCC70

N23

VCC71

M23

VCC72

L23

VCC73

AC22

VCC74

AB22

VCC75

Y22

VCC76

W22

VCC77

P22

VCC78

N22

VCC79

M22

VCC80

L22

VCC81

AC21

VCC82

AA21

VCC83

W21

VCC84

N21

VCC85

M21

VCC86

L21

VCC87

AC20

VCC88

AB20

VCC89

Y20

VCC90

W20

VCC91

P20

VCC92

N20

VCC93

M20

VCC94

L20

VCC95

AB19

VCC96

AA19

VCC97

Y19

VCC98

N19

VCC99

CALISTOGA_FCBGA1466~D

P O W E R

VCC_SM0
VCC_SM1
VCC_SM2
VCC_SM3
VCC_SM4
VCC_SM5
VCC_SM6
VCC_SM7
VCC_SM8

VCC_SM9
VCC_SM10
VCC_SM11
VCC_SM12
VCC_SM13
VCC_SM14
VCC_SM15
VCC_SM16
VCC_SM17
VCC_SM18
VCC_SM19
VCC_SM20
VCC_SM21
VCC_SM22
VCC_SM23
VCC_SM24
VCC_SM25
VCC_SM26
VCC_SM27
VCC_SM28
VCC_SM29
VCC_SM30
VCC_SM31
VCC_SM32
VCC_SM33
VCC_SM34
VCC_SM35
VCC_SM36
VCC_SM37
VCC_SM38
VCC_SM39
VCC_SM40
VCC_SM41
VCC_SM42
VCC_SM43
VCC_SM44
VCC_SM45
VCC_SM46
VCC_SM47
VCC_SM48
VCC_SM49
VCC_SM50
VCC_SM51
VCC_SM52
VCC_SM53
VCC_SM54
VCC_SM55
VCC_SM56
VCC_SM57
VCC_SM58
VCC_SM59
VCC_SM60
VCC_SM61
VCC_SM62
VCC_SM63
VCC_SM64
VCC_SM65
VCC_SM66
VCC_SM67
VCC_SM68
VCC_SM69
VCC_SM70
VCC_SM71
VCC_SM72
VCC_SM73
VCC_SM74
VCC_SM75
VCC_SM76
VCC_SM77
VCC_SM78
VCC_SM79
VCC_SM80
VCC_SM81
VCC_SM82
VCC_SM83
VCC_SM84
VCC_SM85
VCC_SM86
VCC_SM87
VCC_SM88
VCC_SM89
VCC_SM90
VCC_SM91
VCC_SM92
VCC_SM93
VCC_SM94
VCC_SM95
VCC_SM96
VCC_SM97
VCC_SM98
VCC_SM99

AU41
AT41
AM41
AU40
BA34
AY34
AW34
AV34
AU34
AT34
AR34
BA30
AY30
AW30
AV30
AU30
AT30
AR30
AP30
AN30
AM30
AM29
AL29
AK29
AJ29
AH29
AJ28
AH28
AJ27
AH27
BA26
AY26
AW26
AV26
AU26
AT26
AR26
AJ26
AH26
AJ25
AH25
AJ24
AH24
BA23
AJ23
BA22
AY22
AW22
AV22
AU22
AT22
AR22
AP22
AK22
AJ22
AK21
AK20
BA19
AY19
AW19
AV19
AU19
AT19
AR19
AP19
AK19
AJ19
AJ18
AJ17
AH17
AJ16
AH16
BA15
AY15
AW15
AV15
AU15
AT15
AR15
AJ15
AJ14
AJ13
AH13
AK12
AJ12
AH12
AG12
AK11
BA8
AY8
AW8
AV8
AT8
AR8
AP8
BA6
AY6
AW6
AV6
AT6

+1.8V

VCCSM_LF4
VCCSM_LF5

C97

Place near pin AT41 & AM41

C111

Place near pin BA23

C113

10U_0805_6.3V6M

C116

Place near pin BA15

1

C98

2

0.47U_0603_10V7K

1

C102

2

0.1U_0402_16V4Z

1

2

0.47U_0603_10V7K

1

C114

2

10U_0805_6.3V6M

1

2

0.47U_0603_10V7K

CFG[2:0]

1

2

0.47U_0603_10V7K

CFG5

CFG7

CFG9

CFG11

CFG[13:12]

+1.8V

CFG16

1

1

1

C103

C104

2

0.1U_0402_16V4Z

C105

2

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

CFG18

CFG19

SDVO_CTRLDATA

CFG20

(PCIE/SDVO select)

1

1

+

C112

2

220U_D2_4VM@

2

CFG[19:18] have internal pull down

011 = 667MT/s FSB
001 = 533MT/s FSB

0 = DMI x 2
1 = DMI x 4

0 = Reserved
1 = Mobile Yonah CPU

0 = Lane Reversal Enable
1 = Normal Operation

0 = Calistoga

(According to Intel Napa Schematic Checklist & CRB
Rev1.301 document 2.2Kohm pull-down resistor
request)

1 = Reserved

00 = Reserved
01 = XOR Mode Enabled
10 = All Z Mode Enabled
11 = Normal Operation

0 = Dynamic ODT Disabled
1 = Dynamic ODT Enabled (Default)

0 = 1.05V
1 = 1.5V

0 = Normal Operation
1 = DMI Lane Reversal Enable

0 = No SDVO Device Present

(Default)

(Default)

*

*

(Default)

*

(Default)

*

(Default)

*

*

1 = SDVO Device Present

0 = Only PCIE or SDVO is
operational.
1 = PCIE/SDVO are operating
simu.

CFG5<7>
CFG7<7>

CFG9<7>
CFG11<7>
CFG12<7>
CFG13<7>
CFG16<7>

CFG18<7>
CFG19<7>
CFG20<7>

R72 2.2K_0402_5%@
R73 2.2K_0402_5%@
R74 2.2K_0402_5%@
R75 2.2K_0402_5%@
R76 2.2K_0402_5%@
R77 2.2K_0402_5%@
R78 2.2K_0402_5%@

R79 1K_0402_5%@
R80 1K_0402_5%@
R81 1K_0402_5%@

*

1 2
1 2
1 2
1 2
1 2
1 2
1 2

1 2
1 2
1 2

(Default)

*

(Default)

*

(Default)

*

+3VS

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/10/26 2006/07/26

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

2

Date: Sheet

Compal Electronics, Inc.

Calistoga (5/6)

LA-3491P

11 47Tuesday, March 20, 2007

1

0.5

of

5

4

3

2

1

U3I

AC41

VSS0

AA41

VSS1

W41

VSS2

T41

VSS3

P41

VSS4

M41

D D

C C

B B

A A

VSS5

J41

VSS6

F41

VSS7

AV40

VSS8

AP40

VSS9

AN40

VSS10

AK40

VSS11

AJ40

VSS12

AH40

VSS13

AG40

VSS14

AF40

VSS15

AE40

VSS16

B40

VSS17

AY39

VSS18

AW39

VSS19

AV39

VSS20

AR39

VSS21

AN39

VSS22

AJ39

VSS23

AC39

VSS24

AB39

VSS25

AA39

VSS26

Y39

VSS27

W39

VSS28

V39

VSS29

T39

VSS30

R39

VSS31

P39

VSS32

N39

VSS33

M39

VSS34

L39

VSS35

J39

VSS36

H39

VSS37

G39

VSS38

F39

VSS39

D39

VSS40

AT38

VSS41

AM38

VSS42

AH38

VSS43

AG38

VSS44

AF38

VSS45

AE38

VSS46

C38

VSS47

AK37

VSS48

AH37

VSS49

AB37

VSS50

AA37

VSS51

Y37

VSS52

W37

VSS53

V37

VSS54

T37

VSS55

R37

VSS56

P37

VSS57

N37

VSS58

M37

VSS59

L37

VSS60

J37

VSS61

H37

VSS62

G37

VSS63

F37

VSS64

D37

VSS65

AY36

VSS66

AW36

VSS67

AN36

VSS68

AH36

VSS69

AG36

VSS70

AF36

VSS71

AE36

VSS72

AC36

VSS73

C36

VSS74

B36

VSS75

BA35

VSS76

AV35

VSS77

AR35

VSS78

AH35

VSS79

AB35

VSS80

AA35

VSS81

Y35

VSS82

W35

VSS83

V35

VSS84

T35

VSS85

R35

VSS86

P35

VSS87

N35

VSS88

M35

VSS89

L35

VSS90

J35

VSS91

H35

VSS92

G35

VSS93

F35

VSS94

D35

VSS95

AN34

VSS96

AK34

VSS97

AG34

VSS98

AF34

VSS99

CALISTOGA_FCBGA1466~D

P O W E R

VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS140
VSS141
VSS142
VSS143
VSS144
VSS145
VSS146
VSS147
VSS148
VSS149
VSS150
VSS151
VSS152
VSS153
VSS154
VSS155
VSS156
VSS157
VSS158
VSS159
VSS160
VSS161
VSS162
VSS163
VSS164
VSS165
VSS166
VSS167
VSS168
VSS169
VSS170
VSS171
VSS172
VSS173
VSS174
VSS175
VSS176
VSS177
VSS178
VSS179
VSS180
VSS181
VSS182
VSS183
VSS184
VSS185
VSS186
VSS187
VSS188
VSS189
VSS190
VSS191
VSS192
VSS193
VSS194
VSS195
VSS196
VSS197
VSS198
VSS199

AE34
AC34
C34
AW33
AV33
AR33
AE33
AB33
Y33
V33
T33
R33
M33
H33
G33
F33
D33
B33
AH32
AG32
AF32
AE32
AC32
AB32
G32
B32
AY31
AV31
AN31
AJ31
AG31
AB31
Y31
AB30
E30
AT29
AN29
AB29
T29
N29
K29
G29
E29
C29
B29
A29
BA28
AW28
AU28
AP28
AM28
AD28
AC28
W28
J28
E28
AP27
AM27
AK27
J27
G27
F27
C27
B27
AN26
M26
K26
F26
D26
AK25
P25
K25
H25
E25
D25
A25
BA24
AU24
AL24
AW23
AT23
AN23
AM23
AH23
AC23
W23
K23
J23
F23
C23
AA22
K22
G22
F22
E22
D22
A22
BA21
AV21
AR21

U3J

AN21

VSS200

AL21

VSS201

AB21

VSS202

Y21

VSS203

P21

VSS204

K21

VSS205

J21

VSS206

H21

VSS207

C21

VSS208

AW20

VSS209

AR20

VSS210

AM20

VSS211

AA20

VSS212

K20

VSS213

B20

VSS214

A20

VSS215

AN19

VSS216

AC19

VSS217

W19

VSS218

K19

VSS219

G19

VSS220

C19

VSS221

AH18

VSS222

P18

VSS223

H18

VSS224

D18

VSS225

A18

VSS226

AY17

VSS227

AR17

VSS228

AP17

VSS229

AM17

VSS230

AK17

VSS231

AV16

VSS232

AN16

VSS233

AL16

VSS234

J16

VSS235

F16

VSS236

C16

VSS237

AN15

VSS238

AM15

VSS239

AK15

VSS240

N15

VSS241

M15

VSS242

L15

VSS243

B15

VSS244

A15

VSS245

BA14

VSS246

AT14

VSS247

AK14

VSS248

AD14

VSS249

AA14

VSS250

U14

VSS251

K14

VSS252

H14

VSS253

E14

VSS254

AV13

VSS255

AR13

VSS256

AN13

VSS257

AM13

VSS258

AL13

VSS259

AG13

VSS260

P13

VSS261

F13

VSS262

D13

VSS265

B13

VSS264

AY12

VSS263

AC12

VSS266

K12

VSS267

H12

VSS268

E12

VSS269

AD11

VSS270

AA11

VSS271

Y11

VSS272

J11

VSS273

D11

VSS274

B11

VSS275

AV10

VSS276

AP10

VSS277

AL10

VSS278

AJ10

VSS279

CALISTOGA_FCBGA1466~D

P O W E R

VSS280
VSS281
VSS282
VSS283
VSS284
VSS285
VSS286
VSS287
VSS288
VSS289
VSS290
VSS292
VSS291
VSS293
VSS294
VSS295
VSS296
VSS297
VSS298
VSS299
VSS300
VSS301
VSS302
VSS303
VSS304
VSS305
VSS306
VSS307
VSS308
VSS309
VSS310
VSS311
VSS312
VSS313
VSS314
VSS315
VSS316
VSS317
VSS318
VSS319
VSS320
VSS321
VSS322
VSS323
VSS324
VSS325
VSS326
VSS327
VSS328
VSS329
VSS330
VSS331
VSS332
VSS333
VSS334
VSS335
VSS336
VSS337
VSS338
VSS339
VSS340
VSS341
VSS342
VSS343
VSS344
VSS345
VSS346
VSS347
VSS348
VSS349
VSS350
VSS351
VSS352
VSS353
VSS354
VSS355
VSS356
VSS357
VSS358
VSS359
VSS360

AG10
AC10
W10
U10
BA9
AW9
AR9
AH9
AB9
Y9
R9
G9
E9
A9
AG8
AD8
AA8
U8
K8
C8
BA7
AV7
AP7
AL7
AJ7
AH7
AF7
AC7
R7
G7
D7
AG6
AD6
AB6
Y6
U6
N6
K6
H6
B6
AV5
AF5
AD5
AY4
AR4
AP4
AL4
AJ4
Y4
U4
R4
J4
F4
C4
AY3
AW3
AV3
AL3
AH3
AG3
AF3
AD3
AC3
AA3
G3
AT2
AR2
AP2
AK2
AJ2
AD2
AB2
Y2
U2
T2
N2
J2
H2
F2
C2
AL1

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/10/26 2006/07/26

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

2

Date: Sheet

Compal Electronics, Inc.

Calistoga (6/6)

LA-3491P

12 47Tuesday, March 20, 2007

1

0.5

of

5

DDR_A_DQS#[0..7]<8>

DDR_A_D[0..63]<8>

DDR_A_DM[0..7]<8>
DDR_A_DQS[0..7]<8>
DDR_A_MA[0..13]<8>

D D

Layout Note:
Place near JP34

+1.8V

1

2

C133

2.2U_0805_16V4Z

1

2

0.1U_0402_16V4Z

1

2

+0.9V

2.2U_0805_16V4Z

0.1U_0402_16V4Z

C125

C124

1

1

2

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

2

2

C135

DDR_A_BS#2

14

DDR_CKE0_DIMMA

23

DDR_A_MA7

14

DDR_A_MA6

23

DDR_A_MA9

14

DDR_A_MA12

23

DDR_A_MA4

14

DDR_A_MA2

23

DDR_A_MA0

14

DDR_A_BS#1

23

M_ODT0

14

DDR_A_MA13

23

DDR_CKE1_DIMMA

14

DDR_A_MA11

23

C136

C134

RP2 56_0404_4P2R_5%

RP4 56_0404_4P2R_5%

RP6 56_0404_4P2R_5%

RP8 56_0404_4P2R_5%

RP10 56_0404_4P2R_5%

RP12 56_0404_4P2R_5%

RP13 56_0404_4P2R_5%

C126

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

2

0.1U_0402_16V4Z

1

2

C137

2.2U_0805_16V4Z
C121

1

2

C C

B B

A A

Layout Note:
Place one cap close to every 2 pullup
resistors terminated to +0.9V

+0.9V

0.1U_0402_16V4Z

1

2

C130

DDR_A_MA5
DDR_A_MA8

DDR_A_MA1
DDR_A_MA3

DDR_A_RAS#
DDR_CS0_DIMMA#

DDR_A_BS#0
DDR_A_MA10

DDR_A_CAS#
DDR_A_WE#

DDR_CS1_DIMMA#
M_ODT1

0.1U_0402_16V4Z

2.2U_0805_16V4Z

1

2

C131

5

C122

1

2

0.1U_0402_16V4Z

1

2

RP1

1 4
2 3

RP3

56_0404_4P2R_5%

1 4
2 3

RP5

56_0404_4P2R_5%

1 4
2 3

RP7

56_0404_4P2R_5%

1 4
2 3

RP9

56_0404_4P2R_5%

1 4
2 3

RP11

56_0404_4P2R_5%

2 3
1 4

56_0404_4P2R_5%

2.2U_0805_16V4Z

C132

C123

1

2

0.1U_0402_16V4Z

C127

1

2

C138

0.1U_0402_16V4Z
C128

1

2

0.1U_0402_16V4Z

1

2

C139

4

0.1U_0402_16V4Z
C129

1

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

2

2

C140

C141

Layout Note:
Place these resistor
closely JP34,all
trace length Max=1.5"

4

3

+1.8V

JP4

1

VREF

3

DDR_A_D0
DDR_A_D4

DDR_A_DQS#0
DDR_A_DQS0

DDR_A_D2
DDR_A_D3

DDR_A_D8
DDR_A_D14

DDR_A_DQS#1
DDR_A_DQS1

DDR_A_D10
DDR_A_D11

DDR_A_D21
DDR_A_D17

DDR_A_DQS#2
DDR_A_DQS2

DDR_A_D22
DDR_A_D19 DDR_A_D23

DDR_A_D25
DDR_A_D24

DDR_A_DM3

DDR_A_D27
DDR_A_D30

DDR_CKE0_DIMMA<7>

DDR_A_BS#2<8>

DDR_A_BS#0<8>

DDR_A_WE#<8>

DDR_A_CAS#<8>

DDR_CS1_DIMMA#<7>

1

2

C142

M_ODT1<7>

ICH_SMBDATA<4,14,15,20,25>

ICH_SMBCLK<4,14,15,20,25>

DDR_CKE0_DIMMA

DDR_A_BS#2
DDR_A_MA12

DDR_A_MA9 DDR_A_MA7
DDR_A_MA8

DDR_A_MA5
DDR_A_MA3
DDR_A_MA1

DDR_A_MA10
DDR_A_BS#0
DDR_A_WE#

DDR_A_CAS#
DDR_CS1_DIMMA#

M_ODT1
DDR_A_D35

DDR_A_D32
DDR_A_DQS#4

DDR_A_DQS4
DDR_A_D38

DDR_A_D33
DDR_A_D45

DDR_A_D41
DDR_A_DM5
DDR_A_D42

DDR_A_D43
DDR_A_D52

DDR_A_D53

DDR_A_DQS#6
DDR_A_DQS6

DDR_A_D55
DDR_A_D56

DDR_A_D61
DDR_A_DM7
DDR_A_D58

DDR_A_D59
ICH_SMBDATA

ICH_SMBCLK

+3VS

1

C143

0.1U_0402_16V4Z

2

VSS

5

DQ0

7

DQ1

9

VSS

11

DQS0#

13

DQS0

15

VSS

17

DQ2

19

DQ3

21

VSS

23

DQ8

25

DQ9

27

VSS

29

DQS1#

31

DQS1

33

VSS

35

DQ10

37

DQ11

39

VSS

41

VSS

43

DQ16

45

DQ17

47

VSS

49

DQS2#

51

DQS2

53

VSS

55

DQ18

57

DQ19

59

VSS

61

DQ24

63

DQ25

65

VSS

67

DM3

69

NC

71

VSS

73

DQ26

75

DQ27

77

VSS

79

CKE0

81

VDD

83

NC

85

BA2

87

VDD

89

A12

91

A9

93

A8

95

VDD

97

A5

99

A3

101

A1

103

VDD

105

A10/AP

107

BA0

109

WE#

111

VDD

113

CAS#

115

NC/S1#

117

VDD

119

NC/ODT1

121

VSS

123

DQ32

125

DQ33

127

VSS

129

DQS4#

131

DQS4

133

VSS

135

DQ34

137

DQ35

139

VSS

141

DQ40

143

DQ41

145

VSS

147

DM5

149

VSS

151

DQ42

153

DQ43

155

VSS

157

DQ48

159

DQ49

161

VSS

163

NC,TEST

165

VSS

167

DQS6#

169

DQS6

171

VSS

173

DQ50

175

DQ51

177

VSS

179

DQ56

181

DQ57

183

VSS

185

DM7

187

VSS

189

DQ58

191

DQ59

193

VSS

195

SDA

197

SCL

199

VDDSPD

FOX_ASOA426-M4R-TRCONN@

SO-DIMM A

REVERSE

DQ4
DQ5

DM0
DQ6

DQ7

DQ12
DQ13

DM1

CK0#

DQ14
DQ15

DQ20
DQ21

DM2

DQ22
DQ23

DQ28
DQ29

DQS3#

DQS3
DQ30

DQ31

NC/CKE1

VDD
NC/A15
NC/A14

VDD

VDD

VDD

RAS#

VDD

ODT0

NC/A13

VDD

DQ36
DQ37

DM4

DQ38
DQ39

DQ44
DQ45

DQS5#

DQS5
DQ46

DQ47
DQ52

DQ53

CK1#

DM6

DQ54
DQ55

DQ60
DQ61

DQS7#

DQS7
DQ62

DQ63

SAO

VSS

VSS
VSS

VSS

VSS
VSS

CK0
VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

A11

BA1
S0#

VSS

VSS
VSS

VSS

VSS

VSS

VSS

VSS
CK1

VSS
VSS

VSS

VSS

VSS

VSS
SA1

2

+1.8V

V_DDR_MCH_REF

2

DDR_A_D7

4

DDR_A_D1

6
8

DDR_A_DM0

10
12

DDR_A_D5

14

DDR_A_D6

16
18

DDR_A_D12

20

DDR_A_D13

22
24

DDR_A_DM1

26
28

M_CLK_DDR0

30

M_CLK_DDR#0

32
34

DDR_A_D9

36

DDR_A_D15

38
40

42

DDR_A_D20

44

DDR_A_D16

46
48
50

NC

A7
A6

A4
A2
A0

NC

52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200

DDR_A_DM2
DDR_A_D18

DDR_A_D29
DDR_A_D28

DDR_A_DQS#3
DDR_A_DQS3

DDR_A_D26
DDR_A_D31

DDR_CKE1_DIMMA

DDR_A_MA11
DDR_A_MA6
DDR_A_MA4

DDR_A_MA2
DDR_A_MA0

DDR_A_BS#1
DDR_A_RAS#
DDR_CS0_DIMMA#

M_ODT0
DDR_A_MA13

DDR_A_D36
DDR_A_D37

DDR_A_DM4
DDR_A_D39

DDR_A_D34
DDR_A_D40

DDR_A_D44
DDR_A_DQS#5

DDR_A_DQS5
DDR_A_D47

DDR_A_D46
DDR_A_D48

DDR_A_D49
M_CLK_DDR1

M_CLK_DDR#1
DDR_A_DM6
DDR_A_D50DDR_A_D51

DDR_A_D54
DDR_A_D60

DDR_A_D57
DDR_A_DQS#7

DDR_A_DQS7
DDR_A_D62

DDR_A_D63

12

R83

R82

10K_0402_5%

10K_0402_5%

12

2.2U_0805_16V4Z
C119

1

2

M_CLK_DDR0 <7>
M_CLK_DDR#0 <7>

DDR_THERM# <7,14>

DDR_CKE1_DIMMA <7>

DDR_A_BS#1 <8>
DDR_A_RAS# <8>
DDR_CS0_DIMMA# <7>

M_ODT0 <7>

M_CLK_DDR1 <7>
M_CLK_DDR#1 <7>

1

0.1U_0402_16V4Z

1

2

V_DDR_MCH_REF <7,14>

C120

BOT side

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/10/26 2006/07/26

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

2

Date: Sheet

Compal Electronics, Inc.

DDRII-SODIMM SLOT1

LA-3491P

13 47Tuesday, March 20, 2007

1

0.5

of

5

DDR_B_DQS#[0..7]<8>

DDR_B_D[0..63]<8>

DDR_B_DM[0..7]<8>
DDR_B_DQS[0..7]<8>
DDR_B_MA[0..13]<8>

D D

C C

B B

A A

Layout Note:
Place near JP34

+1.8V

2.2U_0805_16V4Z

2.2U_0805_16V4Z

0.1U_0402_16V4Z

1

2

1

2

C156

RP14

RP16

RP18

RP20

RP22

RP24

C147

0.1U_0402_16V4Z

1 4
2 3

1 4
2 3

1 4
2 3

1 4
2 3

1 4
2 3

2 3
1 4

5

2.2U_0805_16V4Z
C148

1

2

0.1U_0402_16V4Z

1

2

C157

56_0404_4P2R_5%

56_0404_4P2R_5%

56_0404_4P2R_5%

56_0404_4P2R_5%

56_0404_4P2R_5%

56_0404_4P2R_5%

C146

1

2

Layout Note:
Place one cap close to every 2 pullup
resistors terminated to +0.9V

+0.9V

0.1U_0402_16V4Z

1

2

C155

DDR_B_MA1
DDR_B_MA3

DDR_B_BS#0
DDR_B_MA10

DDR_B_MA0
DDR_B_BS#1

DDR_B_RAS#
DDR_CS2_DIMMB#

DDR_B_CAS#
DDR_B_WE#

DDR_CS3_DIMMB# M_ODT2
M_ODT3

2.2U_0805_16V4Z
C149

1

2

0.1U_0402_16V4Z

1

1

2

2

C158

C159

+0.9V

2.2U_0805_16V4Z
C150

1

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

2

C160

RP15 56_0404_4P2R_5%

14
23

RP17 56_0404_4P2R_5%

14
23

RP19 56_0404_4P2R_5%

14
23

RP21 56_0404_4P2R_5%

14
23

RP23 56_0404_4P2R_5%

14
23

RP25 56_0404_4P2R_5%

14
23

RP26

14
23

56_0404_4P2R_5%

0.1U_0402_16V4Z

0.1U_0402_16V4Z
C151

1

2

0.1U_0402_16V4Z

1

1

2

2

C161

C162

DDR_B_MA9
DDR_B_MA12

DDR_CKE3_DIMMB
DDR_B_MA11

DDR_B_MA5
DDR_B_MA8

DDR_B_MA7
DDR_B_MA6

DDR_B_MA4
DDR_B_MA2

DDR_B_MA13

DDR_B_BS#2
DDR_CKE2_DIMMB

0.1U_0402_16V4Z

C152

1

2

0.1U_0402_16V4Z

1

2

C163

0.1U_0402_16V4Z

C153

1

1

2

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

2

2

C165

C164

Layout Note:
Place these resistor
closely JP10,all
trace length Max=1.5"

4

4

C154

3

+1.8V

JP5

1

VREF

3

DDR_B_D0
DDR_B_D5

DDR_B_DQS#0
DDR_B_DQS0

DDR_B_D7
DDR_B_D3

DDR_B_D8
DDR_B_D9

DDR_B_DQS#1
DDR_B_DQS1

DDR_B_D10
DDR_B_D11

DDR_B_D20
DDR_B_DQS#2

DDR_B_DQS2
DDR_B_D22

DDR_B_D23
DDR_B_D24

DDR_B_D25
DDR_B_DM3

DDR_B_D30
DDR_B_D31

DDR_CKE2_DIMMB<7>

DDR_B_BS#2<8>

DDR_B_BS#0<8>

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

2

2

C166

C167

DDR_B_WE#<8>

DDR_B_CAS#<8>

DDR_CS3_DIMMB#<7>

M_ODT3<7>

ICH_SMBDATA<4,13,15,20,25>

ICH_SMBCLK<4,13,15,20,25>

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

DDR_CKE2_DIMMB

DDR_B_BS#2
DDR_B_MA12

DDR_B_MA9
DDR_B_MA8

DDR_B_MA5
DDR_B_MA3
DDR_B_MA1

DDR_B_MA10
DDR_B_BS#0
DDR_B_WE#

DDR_B_CAS#
DDR_CS3_DIMMB#

M_ODT3
DDR_B_D37

DDR_B_D36
DDR_B_DQS#4

DDR_B_DQS4
DDR_B_D35

DDR_B_D34
DDR_B_D40

DDR_B_D41
DDR_B_DM5
DDR_B_D42

DDR_B_D47
DDR_B_D48

DDR_B_D53

DDR_B_DQS#6
DDR_B_DQS6

DDR_B_D51
DDR_B_D50

DDR_B_D60
DDR_B_D61

DDR_B_DM7
DDR_B_D58

DDR_B_D59
ICH_SMBDATA

ICH_SMBCLK

+3VS

1

C168

0.1U_0402_16V4Z

2006/10/26 2006/07/26

2

Compal Secret Data

VSS

5

DQ0

7

DQ1

9

VSS

11

DQS0#

13

DQS0

15

VSS

17

DQ2

19

DQ3

21

VSS

23

DQ8

25

DQ9

27

VSS

29

DQS1#

31

DQS1

33

VSS

35

DQ10

37

DQ11

39

VSS

41

VSS

43

DQ16

45

DQ17

47

VSS

49

DQS2#

51

DQS2

53

VSS

55

DQ18

57

DQ19

59

VSS

61

DQ24

63

DQ25

65

VSS

67

DM3

69

NC

71

VSS

73

DQ26

75

DQ27

77

VSS

79

CKE0

81

VDD

83

NC

85

BA2

87

VDD

89

A12

91

A9

93

A8

95

VDD

97

A5

99

A3

101

A1

103

VDD

105

A10/AP

107

BA0

109

WE#

111

VDD

113

CAS#

115

NC/S1#

117

VDD

119

NC/ODT1

121

VSS

123

DQ32

125

DQ33

127

VSS

129

DQS4#

131

DQS4

133

VSS

135

DQ34

137

DQ35

139

VSS

141

DQ40

143

DQ41

145

VSS

147

DM5

149

VSS

151

DQ42

153

DQ43

155

VSS

157

DQ48

159

DQ49

161

VSS

163

NC,TEST

165

VSS

167

DQS6#

169

DQS6

171

VSS

173

DQ50

175

DQ51

177

VSS

179

DQ56

181

DQ57

183

VSS

185

DM7

187

VSS

189

DQ58

191

DQ59

193

VSS

195

SDA

197

SCL

199

VDDSPD

203

GND

FOX_ASOA426-M2RN-7F CONN@

SO-DIMM B
STANDARD

Bottom side

Deciphered Date

VSS
DQ4
DQ5
VSS
DM0
VSS
DQ6
DQ7

VSS
DQ12
DQ13

VSS

DM1

VSS

CK0

CK0#

VSS
DQ14
DQ15

VSS

VSS
DQ20
DQ21

VSS

DM2

VSS
DQ22
DQ23

VSS
DQ28
DQ29

VSS

DQS3#

DQS3

VSS
DQ30
DQ31

VSS

NC/CKE1

VDD

NC/A15
NC/A14

VDD

VDD

VDD
RAS#

VDD
ODT0

NC/A13

VDD

VSS
DQ36
DQ37

VSS

DM4

VSS
DQ38
DQ39

VSS
DQ44
DQ45

VSS

DQS5#

DQS5

VSS
DQ46
DQ47

VSS
DQ52
DQ53

VSS

CK1

CK1#

VSS

DM6

VSS
DQ54
DQ55

VSS
DQ60
DQ61

VSS

DQS7#

DQS7

VSS
DQ62
DQ63

VSS

GND

2

+1.8V

V_DDR_MCH_REF

2

DDR_B_D4

4

DDR_B_D1

6
8

DDR_B_DM0

10
12

DDR_B_D6

14

DDR_B_D2

16
18

DDR_B_D12

20

DDR_B_D13

22
24

DDR_B_DM1

26
28

M_CLK_DDR3

30

M_CLK_DDR#3

32
34

DDR_B_D14

36

DDR_B_D15

38
40

42

DDR_B_D16DDR_B_D21

44

DDR_B_D17

46
48
50

NC

A11

A7
A6

A4
A2

A0
BA1
S0#

NC

SA0
SA1

2

52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
204

DDR_B_DM2
DDR_B_D18

DDR_B_D19
DDR_B_D26

DDR_B_D28
DDR_B_DQS#3

DDR_B_DQS3
DDR_B_D29

DDR_B_D27
DDR_CKE3_DIMMB

DDR_B_MA11
DDR_B_MA7
DDR_B_MA6

DDR_B_MA4
DDR_B_MA2
DDR_B_MA0

DDR_B_BS#1
DDR_B_RAS#
DDR_CS2_DIMMB#

M_ODT2
DDR_B_MA13

DDR_B_D33
DDR_B_D32

DDR_B_DM4
DDR_B_D38

DDR_B_D39
DDR_B_D44

DDR_B_D45
DDR_B_DQS#5

DDR_B_DQS5
DDR_B_D43

DDR_B_D46
DDR_B_D49

DDR_B_D52
M_CLK_DDR2

M_CLK_DDR#2
DDR_B_DM6
DDR_B_D54

DDR_B_D55
DDR_B_D56

DDR_B_D57
DDR_B_DQS#7

DDR_B_DQS7
DDR_B_D62

DDR_B_D63

10K_0402_5%

12

R85

R84

1 2

10K_0402_5%

Title

Size Document Number Rev

Date: Sheet

0.1U_0402_16V4Z

2.2U_0805_16V4Z

M_CLK_DDR3 <7>
M_CLK_DDR#3 <7>

DDR_THERM# <7,13>

DDR_CKE3_DIMMB <7>

DDR_B_BS#1 <8>
DDR_B_RAS# <8>
DDR_CS2_DIMMB# <7>

M_ODT2 <7>

M_CLK_DDR2 <7>
M_CLK_DDR#2 <7>

1

1

C144

2

2

+3VS

Compal Electronics, Inc.

DDRII-SODIMM SLOT2

LA-3491P

1

V_DDR_MCH_REF <7,13>

C145

1

0.5

of

14 47Tuesday, March 20, 2007

5

PCI

SRC

CPU

CLKSEL1

0

1

8.2K_0402_5%

FSA

0_0402_5%

CLK_Ra

0_0402_5%

CLK_Rb

8.2K_0402_5%

0_0402_5%

CLK_Rc

FSLA

CLKSEL0

Stuff

No Stuff

Stuff

No Stuff

Stuff

No Stuff

R99

1 2

R103

FSB

1 2

R118

R129

1 2

R133

+VCCP

12

+VCCP

+VCCP

12

MHz

133

166

CLK_Ra

CLK_Rd

CLK_Rd

CLK_Ra

CLK_Rd

CLK_Ra
CLK_Re

R97

@

56_0402_5%

CLK_Rd

1 2

1 2

R100

1K_0402_5%

12

R105
1K_0402_5%

R112
1K_0402_5%

1 2

1 2

R116

1K_0402_5%

12

R120

@

0_0402_5%

CLK_Re

R125
1K_0402_5%

1 2

1 2

R130

1K_0402_5%

12

R136

@

0_0402_5%

CLK_Rf

MHz

1000

100

CLK_Rb

CLK_Re

CLK_Re

CLK_Rb

CLK_Rb
CLK_Rf

+3VS

R122 10K_0402_5%@

MCH_CLKSEL2 <7>

MHz

+3VS

33.31

33.3

+3VS

CLK_Rc

CLK_Rf

+3VS

CLK_Rf

CLK_Rc

CLK_Rc

MCH_CLKSEL0 <7>

+CK_VDD_DP

1

C190

0.1U_0402_16V4Z@

2

CLK_14M_ICH<20>

Must fine tune12/08

MCH_CLKSEL1 <7>

CLK_DEBUG_PORT<25>

CLK_33M_CBS<24>
CLK_33M_LPC<31>

12

CLK_MCH_REF<7>
CLK_MCH_REF#<7>

NOXDP@ : means just build when XDP function disable.
XDP@ : means just build when XDP function enable.

FSLC1FSLB

CLKSEL2

0

Table : ICS954306

D D

FSB Frequency Selet:

CPU Driven

(Default)

*

533MHz

667MHz

C C

CPU_BSEL0<5>

CPU_BSEL1<5>

B B

CLKREF1

CPU_BSEL2<5>

When this tim e, d ocking PCI express will not work.

+3VS

12

R142

10K_0402_5%@

A A

CLK_ENABLE#

R145

300_0402_5%

J1

NO SHORT PADS

12

12

5

LCD(Low)/SRC(High)
clock select

+3VS +3VS

12

R143
10K_0402_5%

PCI_ICH

12

R146

10K_0402_5%@

High:Pin18/19 = 100MHz

*

Low:Pin18/19 = 96MHz Low:Pin44/45 = CPUCLK2_ITP

4

1 2

R86 0_0805_5%

1 2

R87 0_0805_5%

R90

1 2

0_0805_5%

0.1U_0402_16V4Z

CLKIREF

R93

12

0_0402_5%@

0.1U_0402_16V4Z

CLK_48M_ICH<20>

H_STP_CPU#<20>

H_STP_PCI#<20>

CLK_ENABLE#<40>

CLK_PCI_ICH<18>

CLK_14M_KBC<30>

CLK_DEBUG_PORT PCI_MINI

CLK_PCI_EC<30>

PCI_EC

ICH_SMBDATA<4,13,14,20,25>

ICH_SMBCLK<4,13,14,20,25>

CLK_MCH_REF
CLK_MCH_REF#

Pin44/45 function select

High:Pin44/45 = CLKREQ

*

4

+CK_VDD_MAIN1

1

CLK_14M_ICH

C170
10U_0805_10V4Z

2

+CK_VDD_MAIN2

1

C177
10U_0805_10V4Z

2

+CK_VDD_DP

1

C181
10U_0805_10V4Z

2

+CK_VDD_DP

1

C188

2
1

C189

2

CLK_48M_ICH

H_STP_CPU#
H_STP_PCI#

CLK_ENABLE#
CLK_PCI_ICH PCI_ICH

CLK_14M_KBC

33_0402_5%DEBUG@

ICH_SMBDATA
ICH_SMBCLK

R101 33_0402_5%

R104 33_0402_5%

R107

R119 33_0402_5%
R121 33_0402_5%
R2171 33_0402_5%

12

R144
10K_0402_5%

PCI_MINI

12

R147

10K_0402_5%@

+CK_VDD_MAIN1

CK_VDD_48

CK_VDD_REF

12

12

910_0402_1%

R111

12

33_0402_5%

12

R114 33_0402_5%

R117

12

R220910K_0402_5%

12
12

12
12

R12724_0402_5%

12

R13124_0402_5%

12

3

1

C171

0.01U_0402_16V7K

2

1

C178

0.1U_0402_16V4Z

2

1

C172

0.01U_0402_16V7K

2

1

C179

0.1U_0402_16V4Z

2

12/05 ICS recommend

1

C182

0.1U_0402_16V4Z

2

FSA
FSB
CLKREF1

CLKIREF

CLKREF0

PCI_CLK3
PCI_EC

PCI_CBSCLK_33M_CBS
PCI_LPCCLK_33M_LPC

MCH_REF
MCH_REF#

1

C183

0.1U_0402_16V4Z

2

U4

16

VDD

10

VDD48

5

VDDPCI

24

VDDSRC

33

VDDSATA

41

VDDSRC

50

VDDCPU

55

VDDREF

11

FSLA/USB_48MHz

15

FSLB/TEST_MODE

59

FSLC/TEST_SEL/REF1

46

IREF

61

CPU_STOP#

8

PCI/SRC_STOP#

9

Vtt_PwrGd#/PD

7

**SEL_LCDCLK#/PCICLK_F1

60

REF0/PCICLK1

62

*REQ_SEL/PCICLK2

1

*SEL_PCI1/PCICLK3

2

**SEL_SATA1/PCICLK4

3

**SEL_SATA2/PCICLK5

6

PCICLK6

54

SDATA

53

SCLK

13

DOTT_96MHz

14

DOTC_96MHz

4

GND

12

GND

17

GND

58

GND

47

GNDCPU

25

GNDSRC

40

GNDSRC

32

GNDSATA

ICS9LP306_TSSOP64

* Internal Pull-Up Resistor
** Internal Pull-Down Resistor

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

1

C173

0.01U_0402_16V7K

2

R88

1 2

1_0805_1%

1 2

R89

2.2_0805_1%

1

C184

0.1U_0402_16V4Z

2

LCDCLK_SST/SRCCLKT0

LCDCLK_SSC/SRCCLKC0

SATA1/SRCCLKT4
SATA1/SRCCLKC4

SATA2/SRCCLKT5
SATA2/SRCCLKC5

*CPUCLKT2_ITP/CLKREQC#

*CPUCLKC2_ITP/CLKREQD#

2006/10/26 2006/07/26

3

CK_VDD_REF

CK_VDD_48

SATACLKT
SATACLKC

CPUCLKT0
CPUCLKC0

CPUCLKT1
CPUCLKC1

*CLKREQA#

SRCCLKT2
SRCCLKC2

*CLKREQB#

SRCCLKT1
SRCCLKC1

SRCCLKT3
SRCCLKC3

SRCCLKT6
SRCCLKC6

SRCCLKT8
SRCCLKC8

SRCCLKT7
SRCCLKC7

Place crystal within

1

C1469

0.1U_0402_16V4Z

2

CLK_XTAL_IN

57

X1

CLK_XTAL_OUT

56

X2

28
29

CPU_BCLK

52

CPU_BCLK#

51

MCH_BCLK

49

MCH_BCLK#

48

64
18

SSCDREFCLK#

19

22
23

PCIE_SATA

30

PCIE_SATA# CLK_PCIE_SATA#

31

63
20
21

26
27

PCIE_ICH

35

PCIE_ICH#

34

CPU_XDP

45

MCH_3GPLL

37

MCH_3GPLL#

36

43
42

CPU_XDP#

44

PCIE_MCARD

39
38

500 mils of CK410

C186 33P_0402_50V8J

12

Y1

14.31818MHZ_16P

C187 33P_0402_50V8J

R92 0_0402_5%LP@

1 2

R94 0_0402_5%LP@

1 2

1 2

R98 24_0402_5%

1 2

R102 24_0402_5%

1 2

R95 24_0402_5%

1 2

R96 24_0402_5%

T32

PAD

1 2

R106 24_0402_5%

1 2

R108 24_0402_5%

1 2

R113 24_0402_5%

1 2

R115 24_0402_5%

T33

PAD

1 2

R123 24_0402_5%

1 2

R124 24_0402_5%

NOXDP@

R128

1 2

R1133 24_0402_5%XDP@

1 2

R134 24_0402_5%

1 2

R135 24_0402_5%

0_0402_5%NOXDP@

R2227

1 2

R2206 24_0402_5%XDP@

1 2

R140 24_0402_5%

1 2

R141 24_0402_5%

Compal Secret Data

Deciphered Date

12

0_0402_5%

12

12

12

2

Routing the tr ace at least 10mil

CLK_CPU_BCLK
CLK_CPU_BCLK#

CLK_MCH_BCLK
CLK_MCH_BCLK#

MCH_SSCDREFCLKS S CDREFCLK
MCH_SSCDREFCLK#

CLK_PCIE_SATA

CLK_PCIE_ICH
CLK_PCIE_ICH#

R126 10K_0402_5%NOXDP@

12

CLKREQC#

CLK_CPU_XDP
CLK_MCH_3GPLL
CLK_MCH_3GPLL#

R2226 10K_0402_5%NOXDP@

CLKREQD#

CLK_CPU_XDP#
CLK_PCIE_MCARD
CLK_PCIE_MCARD#PCIE_MCARD#

2

CLK_CPU_BCLK <4>
CLK_CPU_BCLK# <4>

CLK_MCH_BCLK <7>
CLK_MCH_BCLK# <7>

CLK_PCIE_SATA <19>
CLK_PCIE_SATA# <19>

CLK_PCIE_ICH <20>
CLK_PCIE_ICH# <20>

CLKREQC# <7>

CLK_MCH_3GPLL <7>
CLK_MCH_3GPLL# <7>

12

CLK_PCIE_MCARD <25>
CLK_PCIE_MCARD# <25>

1

C169
C174
C175
C176
C180
C185
C1456
C1457

CLK_48M_ICH

12

5P_0402_50V8C@

CLK_14M_ICH

12

4.7P_0402_50V8C@

CLK_PCI_ICH

12

4.7P_0402_50V8C@

CLK_14M_KBC

12

4.7P_0402_50V8C@

CLK_PCI_EC

12

4.7P_0402_50V8C@

CLK_DEBUG_PORT

12

5P_0402_50V8C@

CLK_33M_LPC

12

4.7P_0402_50V8C@

CLK_33M_CBS

12

4.7P_0402_50V8C@

Place close to U4

12/25

Place near U4

Place these components
near each pin within 40
mils.

CLKREQD#

MCH_SSCDREFCLK <7>
MCH_SSCDREFCLK# <7>

+3VS

CLK_CPU_XDP <4>

12/25

+3VS

CLKREQD# <25>
CLK_CPU_XDP# <4>

Title

Size Document Number Rev

Date: Sheet

CLKREQC#

Compal Electronics, Inc.

Clock generator

LA-3491P

1 2
1 2

1

C191
1000P_0402_50V4Z@
C1461
1000P_0402_50V4Z@

12/25

15 47Tuesday, March 20, 2007

0.5

of