COMPAL LA-3361P Schematics

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1 1

B

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2 2

Compal confidential

Schematics Document

Mobile Dothan uFCPGA with Intel
Alviso_GM+ICH6-M core logic

3 3

2006-09-15

REV:1.0

4 4

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

www.laptopfix.vn

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

D

Size Document Number Rev
Custom

Date: Sheet

Compal Electronics, Inc.

Cover Sheet

LA-3361P

E

143Thursday, September 21, 2006

0.3

of

A

B

C

D

E

Compal confidential

File Name : LA-3361P

1 1

Fan Control

page 13

H_A#(3..31)

Mobile Dothan/Yonah
uFCPGA-478 CPU

page 4,5,6

FSB

400/533MHz

Thermal Sensor
ADM1032ARM

page 13

H_D#(0..63)

LVDS CONN

page 14

One Channel

DDR2 -400/533

Intel Alviso GMCH

CRT conn

2 2

page 15

PCBGA 1257

page 7,8,9,10,11

PCI-E(DMI)

One Channel

Clock Generator

ICS 954226

page 16

DDR2-SO-DIMM0

page 12

USB conn x2

page 28

USB conn x2
Option(15.4 Sub board connector)

page 19

LAN I/F

Intel ICH6-M

PCI BUS

INTEL LAN

82562V 10 /100

3 3

RJ45/11 CONN

page 22

page 22

Mini PCI
socket

page 24

CardBus Controller

CB-1410

page 23

Slot 0

page 23

RTC CKT.

page 18

Power On/Off CKT.

page 31

4 4

Touch Pad CONN.

page 29

DC/DC Interface CKT.

page 32

mBGA-609

page 17,18,19,20

LPC BUS

EC KB910L

page 29

Int.KBD

page 29

AC-LINK

IDEBUS

Flash ROM

SST39VF080-70

page 30

Audio Conexant

CX20468-31

IDE HDD
Connector

page 21

page 25

IDE ODD
Connector

Power Circuit DC/DC

33,34,35,36,37,38,39

A

B

www.laptopfix.vn

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

D

MODEM AMOM
CX20493-58

page 26

AMP & Audio Jack
TPA6211

page 21

Intel CPU debug conn
EC debug conn
SW debug conn

Switch Button list:
Power Botton
Lid Switch

LED Function List
Power LED
Caps Lock LED
Wireless LED
Charger LED

Title

Size Document Number Rev
Custom

Date: Sheet

page 27

Page 4
Page 29
Page 29

Page 30
Page 30

：

Page 28
Page 28
Page 28
Page 28

Compal Electronics, Inc.

Block Diagram

LA-3361P

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0.3

of

243Thursday, September 21, 2006

5

I2C / SMBUS ADDRESSING

4

3

2

1

External PCI Devices

Alviso 915GM SA00000K040
Alviso 910GML SA00000K100

D D

CARD BUS
Wireless LAN(MINI PCI)

IDSEL # PIRQREQ/GNT #DEVICE

AD22
AD20

2
0

C
E

、

F

BOM

@ : not install
45@ : 45 level
14@ : 14"(IAT00) install

WLAN@ : with WLAN (mini PCI) install

Power Managment table

AMOM@ : with AMOM install

Signal

C C

State

S0

S1

S3

+3VALW

+5VALW

ON

ON ON ON

ON ON

+1.8V

ON ON

+CPU_CORE
+VCCP(1.05V)
+5VS
+3VS
+2.5VS
+1.5VS
+1.8VS
+0.9VS

OFF

BATT@ : 45 level

SPI@ : SPI ROM install

conn@ : ME part

IAT00 14"

46144232L01 915GM
46144232L02 910GML W/O WLAN
46144232L03 910GML

S5 S4/AC

S5 S4/AC don't exist

ON OFF

OFF OFF OFF

OFF

IAT10 15.4"

46144232L11 910GML
46144232L12 915GM

B B

SMBUS Control Table

SOURCE

SMB_EC_CK1
SMB_EC_DA1

SMB_EC_CK2
SMB_EC_DA2

ICH_SMBCLK
ICH_SMBDATA
LCD_DDCCLK

LCD_DDCDATA
I2CC_SCL

I2CC_SDA

A A

KB910L

KB910L

ICH6-M

Alviso
GM-GP

NV44M

INVERTER BATT

5

SERIAL SENSOR
EEPROM

THERMAL
(CPU)

ADM1032

SODIMM CLK CHIP

4

www.laptopfix.vn

46144232L13 910GML W/O WLAN

MINI PCI

LCD

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

Title

Size Document Number Rev
Custom

2

Date: Sheet

Compal Electronics, Inc.

Design Note

LA-3361P

1

343Thursday, September 21, 2006

0.3

of

ZZZ1

5

4

3

2

1

H_A#[3..31]<7>

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7

LA3361P-Rev0.1

D D

H_REQ#[0..4]<7>

H_ADSTB#0<7>

C C

R37

+VCCP

B B

H_DPRSLP will change to
H_DPRSTP in future
collateral version.

1 2

56_0402_5%

CLK_ITP<16>
CLK_ITP#<16>

CLK_CPU_BCLK<16>
CLK_CPU_BCLK#<16>

H_RS#[0..2]<7>

XDP_DBRESET#<19>

H_PWRGOOD_R

H_PWRGOOD<18>

H_THERMTRIP#<7,18>

H_ADSTB#1<7>

H_ADS#<7>
H_BNR#<7>
H_BPRI#<7>
H_BR0#<7>
H_DEFER#<7>
H_DRDY#<7>
H_HIT#<7>
H_HITM#<7>

H_LOCK#<7>
H_RESET#<7>

H_TRDY#<7>

H_DBSY#<7>
H_DPSLP#<18>

H_DPRSLP#<18>

H_DPWR#<7>

R2009 1K_0402_5%

H_CPUSLP#<7,18>

H_THERMDA<13>
H_THERMDC<13>

H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

H_ADSTB#0
H_ADSTB#1

CLK_ITP
CLK_ITP#

CLK_CPU_BCLK
CLK_CPU_BCLK#

H_ADS#
H_BNR#
H_BPRI#
H_BR0#
H_DEFER#
H_DRDY#
H_HIT#
H_HITM#
H_IERR#
H_LOCK#
H_RESET#

1" ~ 6.5"

H_RS#0
H_RS#1
H_RS#2
H_TRDY#

XDP_BPM#0
XDP_BPM#1
XDP_BPM#2
XDP_BPM#3

XDP_DBRESET#

H_DBSY#
H_DPSLP#
H_DPRSLP#

XDP_BPM#4
XDP_BPM#5

H_PROCHOT#

12

H_CPUSLP#
XDP_TCK
XDP_TDI
XDP_TDO
TEST1
TEST2
XDP_TMS
XDP_TRST#

H_THERMDA
H_THERMDC

U15A

P4

A3#

U4

A4#

V3

A5#

R3

A6#

V2

A7#

W1

A8#

T4

A9#

W2

A10#

Y4

A11#

Y1

A12#

U1

A13#

AA3

A14#

Y3

A15#

AA2

A16#

AF4

A17#

AC4

A18#

AC7

A19#

AC3

A20#

AD3

A21#

AE4

A22#

AD2

A23#

AB4

A24#

AC6

ADDR GROUP

A25#

AD5

A26#

AE2

A27#

AD6

A28#

AF3

A29#

AE1

A30#

AF1

A31#

R2

REQ0#

P3

REQ1#

T2

REQ2#

P1

REQ3#

T1

REQ4#

U3

ADSTB0#

AE5

ADSTB1#

A16

ITP_CLK0

A15

ITP_CLK1

B15

BCLK0

B14

BCLK1

N2

ADS#

L1

BNR#

J3

BPRI#

N4

BR0#

L4

DEFER#

H2

DRDY#

K3

HIT#

K4

HITM#

A4

IERR#

J2

LOCK#

B11

RESET#

H1

RS0#

K1

RS1#

L2

RS2#

M3

TRDY#

C8

BPM0#

B8

BPM1#

A9

BPM2#

C9

BPM3#

A7

DBR#

M2

DBSY#

B7

DPSLP#

G1

DPRSTP#

C19

DPWR#

A10

PRDY#

B10

PREQ#

B17

PROCHOT#

E4

PWRGOOD

A6

SLP#

A13

TCK

C12

TDI

A12

TDO

C5

TEST1

F23

TEST2

C11

TMS

B13

TRST#

B18

THERMDA

A18

THERMDC

C17

THERMTRIP#

TYCO_1612365-1_Dothan

Dothan

DATA GROUP

HOST CLK

CONTROL GROUP

MISC

THERMAL
DIODE

LEGACY CPU

D10#
D11#
D12#
D13#
D14#
D15#
D16#
D17#
D18#
D19#
D20#
D21#
D22#
D23#
D24#
D25#
D26#
D27#
D28#
D29#
D30#
D31#
D32#
D33#
D34#
D35#
D36#
D37#
D38#
D39#
D40#
D41#
D42#
D43#
D44#
D45#
D46#
D47#
D48#
D49#
D50#
D51#
D52#
D53#
D54#
D55#
D56#
D57#
D58#
D59#
D60#
D61#
D62#
D63#

DINV0#
DINV1#
DINV2#
DINV3#

DSTBN0#
DSTBN1#
DSTBN2#
DSTBN3#
DSTBP0#
DSTBP1#
DSTBP2#
DSTBP3#

A20M#
FERR#

IGNNE#

INIT#
LINT0
LINT1

STPCLK#

SMI#

D0#
D1#
D2#
D3#
D4#
D5#
D6#
D7#
D8#
D9#

A25
A22
B21
A24
B26
A21
B20
C20
B24
D24
E24
C26
B23
E23
C25
H23
G25
L23
M26
H24
F25
G24
J23
M23
J25
L26
N24
M25
H26
N25
K25
Y26
AA24
T25
U23
V23
R24
R26
R23
AA23
U26
V24
U25
V26
Y23
AA26
Y25
AB25
AC23
AB24
AC20
AC22
AC25
AD23
AE22
AF23
AD24
AF20
AE21
AD21
AF25
AF22
AF26

D25
J26
T24
AD20

C23
K24
W25
AE24
C22
L24
W24
AE25

C2
D3
A3
B5
D1
D4

C6
B4

H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63

H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3
H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3

H_A20M#
H_FERR#
H_IGNNE#
H_INIT#
H_INTR
H_NMI

H_STPCLK#
H_SMI#

H_DINV#0 <7>
H_DINV#1 <7>
H_DINV#2 <7>
H_DINV#3 <7>

H_A20M# <18>
H_FERR# <18>
H_IGNNE# <18>
H_INIT# <18>
H_INTR <18>
H_NMI <18>

H_STPCLK# <18>
H_SMI# <18>

+VCCP +VCCP

H_D#0

A19

H_D#[0..63] <7>

XDP Connector

XDP_BPM#5
XDP_BPM#4

XDP_BPM#3
XDP_BPM#2

XDP_BPM#1
XDP_BPM#0

H_PWRGOOD_R
XDP_HOOK1

1

C1531

2

0.1U_0402_16V4Z

XDP_TCK

H_DSTBN#[0..3] <7>

H_DSTBP#[0..3] <7>

layout note: Change R2004 to 649 ohm if using XTP to ITP adapter

R1998

1 2

R1999 54.9_0402_1%

1 2

R2000 54.9_0402_1%

1 2

R2001 54.9_0402_1%

1 2

R2002 54.9_0402_1%

1 2

R2003 54.9_0402_1%@

1 2

R2004 51_0402_1%

1 2

R2005 54.9_0402_1%

1 2

CLK_ITP
CLK_ITP#

H_RESET#H_RESET#_R

R2006

XDP_DBRESET#XDP_DBRESET#_R

12

R2007

PROCHOT# <29>

JP48

1

GND0

3

OBSFN_A0

5

OBSFN_A1

7

GND2

9

OBSDATA_A0

11

OBSDATA_A1

13

GND4

15

OBSDATA_A2

17

OBSDATA_A3

19

GND6

21

OBSFN_B0

23

OBSFN_B1

25

GND8

27

OBSDATA_B0

29

OBSDATA_B1

31

GND10

33

OBSDATA_B2

35

OBSDATA_B3

37

GND12

39

PWRGOOD/HOOK0

41

HOOK1

43

VCC_OBS_AB

45

HOOK2

47

HOOK3

49

GND14

51

SDA

53

SCL

55

TCK1

57

TCK0

59

GND16

+VCCP

R253
56_0402_5%

ITPCLK#/HOOK5

RESET#/HOOK6

SAMTE_BSH-030-01-L-D-A CONN@

+VCCP

12

R32
200_0402_5%

1 2

GND1
OBSFN_C0
OBSFN_C1

GND3

OBSDATA_C0
OBSDATA_C1

GND5

OBSDATA_C2
OBSDATA_C3

GND7
OBSFN_D0
OBSFN_D1

GND9

OBSDATA_D0
OBSDATA_D1

GND11
OBSDATA_D2
OBSDATA_D3

GND13

ITPCLK/HOOK4

VCC_OBS_CD

DBR#/HOOK7

GND15

TD0

TRST#

TMS

GND17

12

R266
56_0402_5%

H_PROCHOT#

H_PWRGOOD

XDP_DBRESET#_R

04/10 no stuff

XDP_TDO
XDP_TRST#
XDP_TDI
XDP_TMS
XDP_PRE

XDP_TDI
XDP_TMS
XDP_TDO
XDP_BPM#5
XDP_HOOK1

XDP_TRST#
XDP_TCK

R2008 0_0402_5%

1 2

1K_0402_1%

1 2

200_0402_1%

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56

TDI

58
60

Place R2006 within 200ps (~1") to CPU

+3VS

12

R258
1K_0402_5%

1

C

Q29

2

B

2SC2411K_SOT23

E

3

Add pullups for PWRGOOD and THERMTRIP per INTEL

+3VS

1K_0402_5%@

+VCCP

A A

5

TEST2

TEST1

R251

1 2

1K_0402_5%@

R35

1 2

1K_0402_5%@

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

4

www.laptopfix.vn

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

Title

Size Document Number Rev
Custom

2

Date: Sheet

Compal Electronics, Inc.

Dothan Processor(1/2)

LA-3361P

1

443Thursday, September 21, 2006

0.3

of

5

4

3

2

1

R181

+1.5VS

D D

1

1

C340

0.01U_0402_16V7K

C C

+VCCP

12

R248
1K_0402_1%

B B

12

R247
2K_0402_1%

1

C626
1U_0603_10V4Z

2

1

C627
220P_0402_50V7K

2

Layout close CPU

Layout Note:
500 mil max length

Spacing 25mil

R249

27.4_0402_1%

20 mils

12

R250

54.9_0402_1%

5 mils (55 Ohm)

20 mils(27.4Ohm)

12

12

R41

27.4_0402_1%

Spacing 1:2

5 mils(55 Ohm)

12

R40

54.9_0402_1%

2

2

PSI#<37>

CPU_BSEL0<16>
CPU_BSEL1<16>

Resistor placed within

0.5" of CPU pin.Trace
should be at least 25
miles away from any
other toggling signal.

54.9_0402_1%@

54.9_0402_1%@

C341
10U_1206_6.3V6M

+CPU_CORE

CPU_VID0<37>
CPU_VID1<37>
CPU_VID2<37>
CPU_VID3<37>
CPU_VID4<37>
CPU_VID5<37>

V_CPU_GTLREF

1 2
1 2

R178

+VCCP

Spacing 25mil

CPU_BSEL0
CPU_BSEL1

T10 PAD
T7 PAD
T20 PAD
T12 PAD
T11 PAD

VCCSENSE
VSSSENSE

PSI#
CPU_VID0

CPU_VID1
CPU_VID2
CPU_VID3
CPU_VID4
CPU_VID5

COMP0
COMP1
COMP2
COMP3

U15B

AE7

VCCSENSE

AF6

VSSSENSE

F26

VCCA0

B1

VCCA1

N1

VCCA2

AC26

VCCA3

P23

VCCQ0

W4

VCCQ1

D10

VCCP

D12

VCCP

D14

VCCP

D16

VCCP

E11

VCCP

E13

VCCP

E15

VCCP

F10

VCCP

F12

VCCP

F14

VCCP

F16

VCCP

K6

VCCP

L5

VCCP

L21

VCCP

M6

VCCP

M22

VCCP

N5

VCCP

N21

VCCP

P6

VCCP

P22

VCCP

R5

VCCP

R21

VCCP

T6

VCCP

T22

VCCP

U21

VCCP

D6

VCC

D8

VCC

D18

VCC

D20

VCC

D22

VCC

E5

VCC

E7

VCC

E9

VCC

E17

VCC

E19

VCC

E21

VCC

F6

VCC

F8

VCC

F18

VCC

E1

PSI#

E2

VID0

F2

VID1

F3

VID2

G3

VID3

G4

VID4

H4

VID5

AD26

GTLREF

C16

BSEL0

C14

BSEL1

P25

COMP0

P26

COMP1

AB2

COMP2

AB1

COMP3

B2

RSVD

C3

RSVD

E26

RSVD

AF7

RSVD

AC1

RSVD

TYCO_1612365-1_Dothan

A2

VSS

A5

VSS

A8

VSS

A11

VSS

A14

VSS

A17

VSS

A20

VSS

A23

VSS

A26

VSS

B3

VSS

B6

VSS

B9

VSS

B12

Dothan

VSS

B16

VSS

B19

VSS

B22

VSS

B25

VSS

C1

VSS

C4

VSS

C7

VSS

C10

VSS

C13

VSS

C15

VSS

C18

VSS

C21

VSS

C24

VSS

D2

VSS

D5

VSS

D7

VSS

D9

VSS

D11

VSS

D13

VSS

D15

VSS

D17

VSS

D19

VSS

D21

VSS

D23

VSS

D26

VSS

E3

VSS

E6

VSS

E8

VSS

E10

VSS

E12

VSS

E14

VSS

E16

VSS

E18

VSS

E20

VSS

E22

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

E25
F1
F4
F5
F7
F9
F11
F13
F15
F17
F19
F21
F24
G2
G6
G22
G23
G26
H3
H5
H21
H25
J1
J4
J6
J22
J24
K2
K5
K21
K23
K26
L3
L6
L22
L25
M1

POWER, GROUNG, RESERVED SIGNALS AND NC

+CPU_CORE

U15C

F20

VCC

F22

VCC

G5

VCC

G21

VCC

H6

VCC

H22

VCC

J5

VCC

J21

VCC

K22

VCC

U5

VCC

V6

VCC

V22

VCC

W5

VCC

W21

VCC

Y6

VCC

Y22

VCC

AA5

VCC

AA7

VCC

AA9

VCC

AA11

VCC

AA13

VCC

AA15

VCC

AA17

VCC

AA19

VCC

AA21

VCC

AB6

VCC

AB8

VCC

AB10

VCC

AB12

VCC

AB14

VCC

AB16

VCC

AB18

VCC

AB20

VCC

AB22

VCC

AC9

VCC

AC11

VCC

AC13

VCC

AC15

VCC

AC17

VCC

AC19

VCC

AD8

VCC

AD10

VCC

AD12

VCC

AD14

VCC

AD16

VCC

AD18

VCC

AE9

VCC

AE11

VCC

AE13

VCC

AE15

VCC

AE17

VCC

AE19

VCC

AF8

VCC

AF10

VCC

AF12

VCC

AF14

VCC

AF16

VCC

AF18

VCC

M4

VSS

M5

VSS

M21

VSS

M24

VSS

N3

VSS

N6

VSS

N22

VSS

N23

VSS

N26

VSS

P2

VSS

P5

VSS

P21

VSS

P24

VSS

R1

VSS

R4

VSS

R6

VSS

R22

VSS

R25

VSS

T3

VSS

T5

VSS

T21

VSS

T23

VSS

TYCO_1612365-1_Dothan

Dothan

POWER, GROUND

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

T26
U2
U6
U22
U24
V1
V4
V5
V21
V25
W3
W6
W22
W23
W26
Y2
Y5
Y21
Y24
AA1
AA4
AA6
AA8
AA10
AA12
AA14
AA16
AA18
AA20
AA22
AA25
AB3
AB5
AB7
AB9
AB11
AB13
AB15
AB17
AB19
AB21
AB23
AB26
AC2
AC5
AC8
AC10
AC12
AC14
AC16
AC18
AC21
AC24
AD1
AD4
AD7
AD9
AD11
AD13
AD15
AD17
AD19
AD22
AD25
AE3
AE6
AE8
AE10
AE12
AE14
AE16
AE18
AE20
AE23
AE26
AF2
AF5
AF9
AF11
AF13
AF15
AF17
AF19
AF21
AF24

A A

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

www.laptopfix.vn

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

Size Document Number Rev
Custom

Date: Sheet

Compal Electronics, Inc.

Dothan Processor(2/2)

LA-3361P

1

543Thursday, September 21, 2006

0.3

of

5

4

3

2

1

+CPU_CORE

1

C84
10U_1206_6.3V6M

2

+CPU_CORE

1

2

+CPU_CORE

1

2

+CPU_CORE

1

2

C259
10U_1206_6.3V6M

C274
10U_1206_6.3V6M

C303
10U_1206_6.3V6M

D D

C C

1

C87
10U_1206_6.3V6M

2

1

C265
10U_1206_6.3V6M

2

1

C280
10U_1206_6.3V6M

2

1

C302
10U_1206_6.3V6M

2

1

C90
10U_1206_6.3V6M

2

1

C81
10U_1206_6.3V6M

2

1

C293
10U_1206_6.3V6M

2

1

C282
10U_1206_6.3V6M

2

1

C93
10U_1206_6.3V6M

2

1

C82
10U_1206_6.3V6M

2

1

C301
10U_1206_6.3V6M

2

1

C283
10U_1206_6.3V6M

2

1

C97
10U_1206_6.3V6M

2

1

C100
10U_1206_6.3V6M

2

1

C273
10U_1206_6.3V6M

2

1

C272
10U_1206_6.3V6M

2

+CPU_CORE

1

2

+CPU_CORE

1

2

+CPU_CORE

1

2

C99
10U_1206_6.3V6M

C101
10U_1206_6.3V6M

C279
10U_1206_6.3V6M

1

C83
10U_1206_6.3V6M

2

1

C102
10U_1206_6.3V6M

2

1

C292
10U_1206_6.3V6M

2

1

C86
10U_1206_6.3V6M

2

1

C98
10U_1206_6.3V6M

2

1

C300
10U_1206_6.3V6M

2

1

C89
10U_1206_6.3V6M

2

1

C260
10U_1206_6.3V6M

2

1

C257
10U_1206_6.3V6M

2

1

C92
10U_1206_6.3V6M

2

1

C267
10U_1206_6.3V6M

2

1

C256
10U_1206_6.3V6M

2

Near VCORE regulator.

+CPU_CORE

6/21

B B

+VCCP

1

C70

+

150U_D2_6.3VM

2

A A

1

C85

0.1U_0402_16V4Z

2

5

1

C88

0.1U_0402_16V4Z

2

1

C91

0.1U_0402_16V4Z

2

1

C96

0.1U_0402_16V4Z

2

4

www.laptopfix.vn

1

C103

0.1U_0402_16V4Z

2

1

C104

0.1U_0402_16V4Z

2

330U_D2E_2.5VM

1

+

C94

C286

2

330U_D2E_2.5VM

1

C78

0.1U_0402_16V4Z

2

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

1

+

330U_D2E_2.5VM

2

1

2

1

+

C95

2

C80

0.1U_0402_16V4Z

C285

1

+

2

330U_D2E_2.5VM@

1

2

ESR <= 3m ohm
Capacitor > 880 uF

1

C105

0.1U_0402_16V4Z

C79

0.1U_0402_16V4Z

2

2

Title

Size Document Number Rev
Custom

Date: Sheet

Compal Electronics, Inc.

Dothan Bypass

LA-3361P

1

643Thursday, September 21, 2006

of

0.3

5

4

3

2

1

H_VREF

U5A

G9

HA3#

C9

HA4#

E9

HA5#

B7

HA6#

A10

HA7#

F9

HA8#

D8

HA9#

B10

HA10#

E10

HA11#

G10

HA12#

D9

HA13#

E11

HA14#

F10

HA15#

G11

HA16#

G13

HA17#

C10

HA18#

C11

HA19#

D11

HA20#

C12

HA21#

B13

HA22#

A12

HA23#

F12

HA24#

G12

HA25#

E12

HA26#

C13

HA27#

B11

HA28#

D13

HA29#

A13

HA30#

F13

HA31#

A11

HPCREQ#

A7

HREQ#0

D7

HREQ#1

B8

HREQ#2

C7

HREQ#3

A8

HREQ#4

B9

HADSTB#0

E13

HADSTB#1

AB1

HCLKN

AB2

HCLKP

G4

HDSTBN#0

K1

HDSTBN#1

R3

HDSTBN#2

V3

HDSTBN#3

G5

HDSTBP#0

K2

HDSTBP#1

R2

HDSTBP#2

W4

HDSTBP#3

H8

HDINV#0

K3

HDINV#1

T7

HDINV#2

U5

HDINV#3

H10

HCPURST#

F8

HADS#

B5

HTRDY#

G6

HDPWR#

F7

HDRDY#

E6

HDEFER#

F6

HEDRDY#

D6

HHITM#

D4

HHIT#

B3

HLOCK#

E7

HBREQ0#

A5

HBNR#

D5

HBPRI#

C6

HDBSY#

G8

HCPUSLP#

A4

HRS0#

C5

HRS1#

B4

HRS2#

ALVISO_BGA1257

1

C237

2

0.1U_0402_16V4Z

Alviso

+VCCP

12

R156

100_0402_1%

12

R160

200_0402_1%

HOST

HXRCOMP
HXSCOMP
HYRCOMP
HYSCOMP

HXSWING
HYSWING

H_SWNG0

HD0#
HD1#
HD2#
HD3#
HD4#
HD5#
HD6#
HD7#
HD8#

HD9#
HD10#
HD11#
HD12#
HD13#
HD14#
HD15#
HD16#
HD17#
HD18#
HD19#
HD20#
HD21#
HD22#
HD23#
HD24#
HD25#
HD26#
HD27#
HD28#
HD29#
HD30#
HD31#
HD32#
HD33#
HD34#
HD35#
HD36#
HD37#
HD38#
HD39#
HD40#
HD41#
HD42#
HD43#
HD44#
HD45#
HD46#
HD47#
HD48#
HD49#
HD50#
HD51#
HD52#
HD53#
HD54#
HD55#
HD56#
HD57#
HD58#
HD59#
HD60#
HD61#
HD62#
HD63#

HVREF

C253

R163

12

12

R170

24.9_0402_1%

24.9_0402_1%

10/20 mils

R168

1

R167

2

0.1U_0402_16V4Z

H_D#[0..63] <4>

+VCCP

12

R164

54.9_0402_1%

54.9_0402_1%

+VCCP+VCCP

12

221_0603_1%

12

100_0402_1%

12

Layout Note:
Rote as short
as possible

V_DDR_MCH_REF<12>

U5B

CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8

CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG16
CFG17
CFG18
CFG19
CFG20

RSVD21
RSVD22

CFG/RSVD

RSVD23
RSVD24
RSVD25
RSVD26
RSVD27

BM_BUSY#

EXT_TS0#
EXT_TS1#

THRMTRIP#

PWROK

RSTIN#

PM

DREF_CLKN
DREF_CLKP

DREF_SSCLKP

CLK

DREF_SSCLKN

NC1
NC2
NC3
NC4
NC5
NC6
NC7
NC8
NC9

NC10

NC

NC11

2

G16
H13
G14
F16
F15
G15
E16
D17
J16
D15
E15
D14
E14
H12
C14
H15
J15
H14
G22
G23
D23
G25
G24
J17
A31
A30
D26
D25

J23
J21
H22
F5
AD30
AE29

A24
A23
D37
C37

AP37
AN37
AP36
AP2
AP1
AN1
B1
A2
B37
A36
A37

CFG0
MCH_CLKSEL1
MCH_CLKSEL0

PAD

T27

PAD

T28

CFG5
CFG6
CFG7

CFG9

CFG12
CFG13

CFG16
CFG18

CFG19

PM_EXTTS#0
PM_EXTTS#1

1 2
1 2

C252

DMI_TXN0
DMI_TXN1
DMI_TXN2
DMI_TXN3

DMI_TXP0
DMI_TXP1
DMI_TXP2
DMI_TXP3

DMI_RXN0
DMI_RXN1
DMI_RXN2
DMI_RXN3

DMI_RXP0
DMI_RXP1
DMI_RXP2
DMI_RXP3

M_CLK_DDR0
M_CLK_DDR1

M_CLK_DDR#0
M_CLK_DDR#1

DDR_CKE0_DIMMA
DDR_CKE1_DIMMA

DDR_CS0_DIMMA#
DDR_CS1_DIMMA#

M_OCDOCMP0
M_OCDOCMP1
M_ODT0
M_ODT1

SMRCOMPN
SMRCOMPP
V_DDR_MCH_REF

R174

10K_0402_1%

1

2

0.1U_0402_16V4Z

DMI_TXN0<19>
DMI_TXN1<19>
DMI_TXN2<19>
DMI_TXN3<19>

DMI_TXP0<19>
DMI_TXP1<19>
DMI_TXP2<19>
DMI_TXP3<19>

DMI_RXN0<19>
DMI_RXN1<19>
DMI_RXN2<19>
DMI_RXN3<19>

DMI_RXP0<19>
DMI_RXP1<19>
DMI_RXP2<19>
DMI_RXP3<19>

M_CLK_DDR0<12>
M_CLK_DDR1<12>

M_CLK_DDR#0<12>
M_CLK_DDR#1<12>

DDR_CKE0_DIMMA<12>
DDR_CKE1_DIMMA<12>

DDR_CS0_DIMMA#<12>
DDR_CS1_DIMMA#<12>

R13640.2_0402_1%@
R14740.2_0402_1%@

M_ODT0<12>
M_ODT1<12>

R159 80.6_0402_1%

V_DDR_MCH_REF

3

1 2
1 2

R157 80.6_0402_1%

1

C22

2

0.1U_0402_16V4Z

+1.8V

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

+1.8V

12

12

AA31

AB35
AC31
AD35

Y31
AA35
AB31

AC35

AA33
AB37

AC33
AD37

Y33
AA37
AB33

AC37

AM33

AL1
AE11
AJ34

AF6

AC10
AN33

AK1
AE10
AJ33

AF5

AD10

AP21

AM21
AH21

AK21

AN16
AM14
AH15
AG16

AF22
AF16
AP14
AL15

AM11
AN10

AK10
AK11
AF37

AD1
AE27
AE28

AF9
AF10

R172
10K_0402_1%

DMIRXN0
DMIRXN1
DMIRXN2
DMIRXN3

DMIRXP0
DMIRXP1
DMIRXP2
DMIRXP3

DMITXN0
DMITXN1
DMITXN2
DMITXN3

DMITXP0
DMITXP1
DMITXP2
DMITXP3

SM_CK0
SM_CK1
SM_CK2
SM_CK3
SM_CK4
SM_CK5

SM_CK0#
SM_CK1#
SM_CK2#
SM_CK3#
SM_CK4#
SM_CK5#

SM_CKE0
SM_CKE1
SM_CKE2
SM_CKE3

SM_CS0#
SM_CS1#
SM_CS2#
SM_CS3#

SM_OCDCOMP0
SM_OCDCOMP1
SM_ODT0
SM_ODT1
SM_ODT2
SM_ODT3

SMRCOMPN
SMRCOMPP
SMVREF0
SMVREF1
SMXSLEWIN
SMXSLEWOUT
SMYSLEWIN
SMYSLEWOUT

ALVISO_BGA1257

DMIDDR MUXING

MCH_CLKSEL1 <16>
MCH_CLKSEL0 <16>

CFG[17:3]: internal pull-up
CFG[19:18]: internal pull-down

CFG0

R149 10K_0402_5%

CFG0

R709 1K_0402_5%@

CFG5
CFG6
CFG7
CFG9
CFG12
CFG13
CFG16

CFG18
CFG19

6/07

Chage CFG18 and CFG19 to PU +2.5VS for SI

PM_BMBUSY# <19>

H_THERMTRIP# <4,18>
+VCCP_PWRGD <29>
PLTRST_MCH# <17,21,23>

DREFCLK# <16>
DREFCLK <16>
SSC_DREFCLK <16>
SSC_DREFCLK# <16>

CFG[2:0]

CFG5

CFG6

CFG7

CFG9

CFG[13:12]
CFG16

(FSB Dynamic
ODT)

CFG18
(VCC Select)

CFG19
(VTT Select)

Title

Size Document Number Rev
Custom

Date: Sheet

Compal Electronics, Inc.

1 2

R127 1K_0402_5%@

1 2

R124 1K_0402_5%

1 2

R117 1K_0402_5%@

1 2

R119 1K_0402_5%@

1 2

R710 1K_0402_5%@

1 2

R711 1K_0402_5%@

1 2

R712 1K_0402_5%@

1 2

R641 1K_0402_5%@

1 2

R642 1K_0402_5%@

1 2

R141

PM_EXTTS#0

PM_EXTTS#1

Refer to sheet 19 for FSB
frequency select

10K_0402_5%

R137

10K_0402_5%

Low = DMI x 2
High = DMI x 4
Low = DDR-II
High = DDR-I
Low = DT/Transportable CPU
High = Mobile CPU
Low = Reverse Lane
High = Normal Operation

00 = Reserved
01 = XOR Mode Enabled
10 = All Z Mode Enabled
11 = Normal Operation (Default)

Low = Disabled
High = Enabled
Low = 1.05V (Default)
High = 1.5V
Low = 1.05V (Default)
High = 1.2V

Alviso(1 of 5)

LA-3361P

1

+VCCP

12

+2.5VS

12

12

*

*

*

*

*

*

*

*

of

743Thursday, September 21, 2006

0.3

H_D#0

E4

H_D#1

E1

H_D#2

F4

H_D#3

H7

H_D#4

E2

H_D#5

F1

H_D#6

E3

H_D#7

D3

H_D#8

K7

H_D#9

F2

H_D#10

J7

H_D#11

J8

H_D#12

H6

H_D#13

F3

H_D#14

K8

H_D#15

H5

H_D#16

H1

H_D#17

H2

H_D#18

K5

H_D#19

K6

H_D#20

J4

H_D#21

G3

H_D#22

H3

H_D#23

J1

H_D#24

L5

H_D#25

K4

H_D#26

J5

H_D#27

P7

H_D#28

L7

H_D#29

J3

H_D#30

P5

H_D#31

L3

H_D#32

U7

H_D#33

V6

H_D#34

R6

H_D#35

R5

H_D#36

P3

H_D#37

T8

H_D#38

R7

H_D#39

R8

H_D#40

U8

H_D#41

R4

H_D#42

T4

H_D#43

T5

H_D#44

R1

H_D#45

T3

H_D#46

V8

H_D#47

U6

H_D#48

W6

H_D#49

U3

H_D#50

V5

H_D#51

W8

H_D#52

W7

H_D#53

U2

H_D#54

U1

H_D#55

Y5

H_D#56

Y2

H_D#57

V4

H_D#58

Y7

H_D#59

W1

H_D#60

W3

H_D#61

Y3

H_D#62

Y6

H_D#63

W2

H_VREF

J11

H_XRCOMP

C1

H_XSCOMP

C2

H_YRCOMP

T1

H_YSCOMP

L1

H_SWNG0

D1

H_SWNG1

P1

R165

12

R173

221_0603_1%

H_SWNG1

12

1

R169

100_0402_1%

C247

4

www.laptopfix.vn

2

0.1U_0402_16V4Z

H_A#[3..31]<4>

D D

T29 PAD

H_REQ#[0..4]<4>

H_ADSTB#0<4>
H_ADSTB#1<4>

C C

B B

CLK_MCH_BCLK#<16>
CLK_MCH_BCLK<16>

H_DSTBN#[0..3]<4>

H_DSTBP#[0..3]<4>

H_DINV#0<4>
H_DINV#1<4>
H_DINV#2<4>
H_DINV#3<4>

H_RESET#<4>
H_ADS#<4>

H_TRDY#<4>
H_DPWR#<4>
H_DRDY#<4>
H_DEFER#<4>

T30 PAD

H_HITM#<4>
H_HIT#<4>
H_LOCK#<4>

H_BR0#<4>
H_BNR#<4>
H_BPRI#<4>
H_DBSY#<4>

H_CPUSLP#<4,18>

H_RS#[0..2]<4>

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31

TP_H_PCREQ#

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
H_ADSTB#0
H_ADSTB#1

H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3
H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3

H_RESET#
H_ADS#

H_TRDY#
H_DRDY#

H_DEFER#
TP_H_EDRDY#
H_HITM#
H_HIT#
H_LOCK#
H_BR0#
H_BNR#
H_BPRI#
H_DBSY#

H_CPUSLP#

H_RS#0
H_RS#1
H_RS#2

PM-C0-SA0091501D0(R3)&SA0091501E0(R1)
GM-B1-SA0091500A0(R3)&SA009150070(R1)

100mil

A A

5

5

D D

4

3

2

1

DDR_A_BS#0<12>
DDR_A_BS#1<12>
DDR_A_BS#2<12>

DDR_A_DM[0..7]<12>

DDR_A_DQS[0..7]<12>

DDR_A_DQS#[0..7]<12>

C C

DDR_A_MA[0..13]<12>

DDR_A_CAS#<12>
DDR_A_RAS#<12>

T21 PAD~D
T22 PAD~D

B B

DDR_A_WE#<12>

DDR_A_BS#0
DDR_A_BS#1
DDR_A_BS#2

DDR_A_DM0
DDR_A_DM1
DDR_A_DM2
DDR_A_DM3
DDR_A_DM4
DDR_A_DM5
DDR_A_DM6
DDR_A_DM7

DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7

DDR_A_DQS#0
DDR_A_DQS#1
DDR_A_DQS#2
DDR_A_DQS#3
DDR_A_DQS#4
DDR_A_DQS#5
DDR_A_DQS#6
DDR_A_DQS#7

DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13

DDR_A_CAS#
DDR_A_RAS#

TP_MA_RCVENIN#

TP_MA_RCVENOUT#

DDR_A_WE#

AK15
AK16

AL21
AJ37

AP35

AL29

AP24

AK36
AP33
AN29
AP23

AK35
AP34
AN30
AN23

AL17
AP17
AP18

AM17

AN18

AM18

AL19
AP20

AM19

AL20

AM16

AN20

AM20
AM15

AN15
AP16
AF29
AF28
AP15

AP9
AP4

AD3

AM8
AM4

AE5

AN8
AM5
AH1
AE4

AJ2

AJ1

U5C

SA_BS0#
SA_BS1#
SA_BS2#

SA_DM0
SA_DM1
SA_DM2
SA_DM3
SA_DM4
SA_DM5
SA_DM6
SA_DM7

SA_DQS0
SA_DQS1
SA_DQS2
SA_DQS3
SA_DQS4
SA_DQS5
SA_DQS6
SA_DQS7

SA_DQS0#
SA_DQS1#
SA_DQS2#
SA_DQS3#
SA_DQS4#
SA_DQS5#
SA_DQS6#
SA_DQS7#

SA_MA0
SA_MA1
SA_MA2
SA_MA3
SA_MA4
SA_MA5
SA_MA6
SA_MA7
SA_MA8
SA_MA9
SA_MA10
SA_MA11
SA_MA12
SA_MA13

SA_CAS#
SA_RAS#
SA_RCVENIN#
SA_RCVENOUT#
SA_WE#

SADQ0
SADQ1
SADQ2
SADQ3
SADQ4
SADQ5
SADQ6
SADQ7
SADQ8

SADQ9
SADQ10
SADQ11
SADQ12
SADQ13
SADQ14
SADQ15
SADQ16
SADQ17
SADQ18
SADQ19
SADQ20
SADQ21
SADQ22
SADQ23
SADQ24
SADQ25
SADQ26
SADQ27
SADQ28
SADQ29
SADQ30
SADQ31
SADQ32
SADQ33
SADQ34
SADQ35
SADQ36
SADQ37
SADQ38
SADQ39
SADQ40
SADQ41
SADQ42
SADQ43

DDR MEMORY SYSTEM A

SADQ44
SADQ45
SADQ46
SADQ47
SADQ48
SADQ49
SADQ50
SADQ51
SADQ52
SADQ53
SADQ54
SADQ55
SADQ56
SADQ57
SADQ58
SADQ59
SADQ60
SADQ61
SADQ62
SADQ63

ALVISO_BGA1257

AH35
AL35
AL37
AH36
AJ35
AK37
AL34
AM36
AN35
AP32
AM31
AM34
AM35
AL32
AM32
AN31
AP31
AN28
AP28
AL30
AM30
AM28
AL28
AP27
AM27
AM23
AM22
AL23
AM24
AN22
AP22
AM9
AL9
AL6
AP7
AP11
AP10
AL7
AM7
AN5
AN6
AN3
AP3
AP6
AM6
AL4
AM3
AK2
AK3
AG2
AG1
AL3
AM2
AH3
AG3
AF3
AE3
AD6
AC4
AF2
AF1
AD4
AD5

DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63

DDR_A_D0

AG35

DDR_A_D[0..63] <12>

This Symbol as same
as Intel CRB
schematic, So Layout
Guide will show these
signals routed
differentially.

AJ15
AG17
AG21

AF32
AK34
AK27
AK24

AJ10

AK5
AE7
AB7

AF34
AK32

AJ28
AK23
AM10

AH6
AF8
AB4

AF35
AK33
AK28

AJ23

AL10

AH7
AF7
AB5

AH17
AK17
AH18

AJ18
AK18

AJ19
AK19
AH19

AJ20
AH20

AJ16
AG18
AG20
AG15

AH14
AK14
AF15
AF14
AH16

U5D

SB_BS0#
SB_BS1#
SB_BS2#

SB_DM0
SB_DM1
SB_DM2
SB_DM3
SB_DM4
SB_DM5
SB_DM6
SB_DM7

SB_DQS0
SB_DQS1
SB_DQS2
SB_DQS3
SB_DQS4
SB_DQS5
SB_DQS6
SB_DQS7

SB_DQS0#
SB_DQS1#
SB_DQS2#
SB_DQS3#
SB_DQS4#
SB_DQS5#
SB_DQS6#
SB_DQS7#

SB_MA0
SB_MA1
SB_MA2
SB_MA3
SB_MA4
SB_MA5
SB_MA6
SB_MA7
SB_MA8
SB_MA9
SB_MA10
SB_MA11
SB_MA12
SB_MA13

SB_CAS#
SB_RAS#
SB_RCVENIN#
SB_RCVENOUT#
SB_WE#

AE31

SBDQ0

AE32

SBDQ1

AG32

SBDQ2

AG36

SBDQ3

AE34

SBDQ4

AE33

SBDQ5

AF31

SBDQ6

AF30

SBDQ7

AH33

SBDQ8

AH32

SBDQ9

AK31

SBDQ10

AG30

SBDQ11

AG34

SBDQ12

AG33

SBDQ13

AH31

SBDQ14

AJ31

SBDQ15

AK30

SBDQ16

AJ30

SBDQ17

AH29

SBDQ18

AH28

SBDQ19

AK29

SBDQ20

AH30

SBDQ21

AH27

SBDQ22

AG28

SBDQ23

AF24

SBDQ24

AG23

SBDQ25

AJ22

SBDQ26

AK22

SBDQ27

AH24

SBDQ28

AH23

SBDQ29

AG22

SBDQ30

AJ21

SBDQ31

AG10

SBDQ32

AG9

SBDQ33

AG8

SBDQ34

AH8

SBDQ35

AH11

SBDQ36

AH10

SBDQ37

AJ9

SBDQ38

AK9

SBDQ39

AJ7

SBDQ40

AK6

SBDQ41

AJ4

SBDQ42
SBDQ43
SBDQ44
SBDQ45
SBDQ46
SBDQ47
SBDQ48
SBDQ49
SBDQ50
SBDQ51
SBDQ52
SBDQ53
SBDQ54
SBDQ55
SBDQ56
SBDQ57
SBDQ58
SBDQ59
SBDQ60
SBDQ61
SBDQ62
SBDQ63

AH5
AK8
AJ8
AJ5
AK4
AG5
AG4
AD8
AD9
AH4
AG6
AE8
AD7
AC5
AB8
AB6
AA8
AC8
AC7
AA4
AA5

DDR SYSTEM MEMORY B

ALVISO_BGA1257

A A

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

www.laptopfix.vn

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

Title

Size Document Number Rev
Custom

2

Date: Sheet

Compal Electronics, Inc.

Alviso(2 of 5)

LA-3361P

1

843Thursday, September 21, 2006

0.3

of

5

D D

4

3

2

1

R5 0_0402_5%@

1 2

CLK_MCH_3GPLL#<16>
CLK_MCH_3GPLL<16>

1 2

R334150_0402_1%

1 2

R335150_0402_1%

1 2

R336150_0402_1%

C C

B B

A A

TV Enable: R334,R335,R336 :75 ohm
TV Disable: R334,R335,R336 :150 ohm

CRT_BLU<15>
CRT_GRN<15>
CRT_RED<15>

+2.5VS

R133 2.2K_0402_5%
R140 2.2K_0402_5%

LCD_CLK
LCD_DAT

1 2
1 2

CRT_SMBCLK<15>
CRT_SMBDAT<15>

VSYNC<15>
HSYNC<15>

BIA<14>
BK_EN<14,29>

LCD_CLK<14>
LCD_DAT<14>
EN_LCDVDD<14>

12

R128 1.5K_0402_1%

LVDSAC-<14>
LVDSAC+<14>
LVDSBC-<14>
LVDSBC+<14>

LVDSA0-<14>
LVDSA1-<14>
LVDSA2-<14>

LVDSA0+<14>
LVDSA1+<14>
LVDSA2+<14>

LVDSB0-<14>
LVDSB1-<14>
LVDSB2-<14>

LVDSB0+<14>
LVDSB1+<14>
LVDSB2+<14>

08/09 Add B channel

T46 PAD

COMPS
LUMA
CRMA

CRT_SMBCLK
CRT_SMBDAT

255_0402_1%

BIA
BK_EN

LCD_CLK
LCD_DAT
EN_LCDVDD

LVDSAC­LVDSAC+
LVDSBC­LVDSBC+

LVDSA0­LVDSA1­LVDSA2-

LVDSA0+
LVDSA1+
LVDSA2+

LVDSB0­LVDSB1­LVDSB2-

LVDSB0+
LVDSB1+
LVDSB2+

R392

4.99K_0603_1%

1 2

R143

H24

SDVOCTRL_DATA

H25

SDVOCTRL_CLK

AB29

GCLKN

AC29

GCLKP

A15

TVDAC_A

C16

TVDAC_B

A17

TVDAC_C

J18

TV_REFSET

B15

12

B16
B17

E24
E23
E21
D21
C20
B20
A19
B19
H21
G21

J20

E25
F25
C23
C22
F23
F22
F26
C33
C31
F28
F27

B30
B29
C25
C24

B34
B33
B32

A34
A33
B31

C29
D28
C27

C28
D27
C26

TV_IRTNA
TV_IRTNB
TV_IRTNC

DDCCLK
DDCDATA
BLUE
BLUE#
GREEN
GREEN#
RED
RED#
VSYNC
HSYNC
REFSET

LBKLT_CTL
LBKLT_EN
LCTLA_CLK
LCTLB_DATA
LDDC_CLK
LDDC_DATA
LVDD_EN
LIBG
LVBG
LVREFH
LVREFL

LACLKN
LACLKP
LBCLKN
LBCLKP

LADATAN0
LADATAN1
LADATAN2

LADATAP0
LADATAP1
LADATAP2

LBDATAN0
LBDATAN1
LBDATAN2

LBDATAP0
LBDATAP1
LBDATAP2

EXP_RXN0/SDVO_TVCLKIN#

EXP_RXN1/SDVO_INT#

MISCTVVGALVDS

EXP_RXN2/SDVO_FLDSTALL#

EXP_RXP0/SDVO_TVCLKIN

EXP_RXP1/SDVO_INT

EXP_RXP2/SDVO_FLDSTALL

EXP_TXN0/SDVOB_RED#

EXP_TXN1/SDVOB_GREEN#

EXP_TXN2/SDVOB_BLUE#

EXP_TXN3/SDVOB_CLKN
EXP_TXN4/SDVOC_RED#

EXP_TXN5/SDVOC_GREEN#

EXP_TXN6/SDVOC_BLUE#

EXP_TXN7/SDVOC_CLKN

PCI - EXPRESS GRAPHICS

EXP_TXP0/SDVOB_RED

EXP_TXP1/SDVOB_GREEN

EXP_TXP2/SDVOB_BLUE
EXP_TXP3/SDVOB_CLKP

EXP_TXP4/SDVOC_RED

EXP_TXP5/SDVOC_GREEN

EXP_TXP6/SDVOC_BLUE
EXP_TXP7/SDVOC_CLKP

EXP_COMPI

EXP_ICOMPO

EXP_RXN3
EXP_RXN4
EXP_RXN5
EXP_RXN6
EXP_RXN7
EXP_RXN8

EXP_RXN9
EXP_RXN10
EXP_RXN11
EXP_RXN12
EXP_RXN13
EXP_RXN14
EXP_RXN15

EXP_RXP3

EXP_RXP4

EXP_RXP5

EXP_RXP6

EXP_RXP7

EXP_RXP8

EXP_RXP9
EXP_RXP10
EXP_RXP11
EXP_RXP12
EXP_RXP13
EXP_RXP14
EXP_RXP15

EXP_TXN8

EXP_TXN9
EXP_TXN10
EXP_TXN11
EXP_TXN12
EXP_TXN13
EXP_TXN14
EXP_TXN15

EXP_TXP8

EXP_TXP9

EXP_TXP10
EXP_TXP11
EXP_TXP12
EXP_TXP13
EXP_TXP14
EXP_TXP15

ALVISO_BGA1257

U5G

D36
D34

E30
F34
G30
H34
J30
K34
L30
M34
N30
P34
R30
T34
U30
V34
W30
Y34

D30
E34
F30
G34
H30
J34
K30
L34
M30
N34
P30
R34
T30
U34
V30
W34

E32
F36
G32
H36
J32
K36
L32
M36
N32
P36
R32
T36
U32
V36
W32
Y36

D32
E36
F32
G36
H32
J36
K32
L36
M32
N36
P32
R36
T32
U36
V32
W36

PEGCOMP

24.9_0402_1%

1 2

R125

+1.5VS_PCIE

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

www.laptopfix.vn

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

Size Document Number Rev
Custom

Date: Sheet

Compal Electronics, Inc.

Alviso(3 of 5)

LA-3361P

1

943Thursday, September 21, 2006

0.3

of

5

4

3

2

1

K13

VTT0

J13

VTT1

K12

VTT2

W11

VTT3

V11

VTT4

U11

VTT5

T11

VTT6

R11

VTT7

P11

POWER

VTT8

N11

VTT9

M11

D D

+VCCP

1

C217

C232

2

4.7U_0805_10V4Z

2.2U_0603_6.3V4Z

1

C65

C C

0.47U_0603_16V7K

2

1

1

C244

C245

2

2

0.47U_0603_16V7K

CHB1608U301_0603

+1.5VS

B B

1 2

L11
K11

W10

V10
U10
T10
R10
P10
N10

M10

K10

J10

1

Y9

W9

U9

2

R9

P9
N9
M9

L9

J9
N8
M8
N7
M7
N6
M6

A6
N5
M5
N4
M4
N3
M3
N2
M2

B2

V1
N1
M1
G1

1

C254

2

0.22U_0603_10V7K

0.22U_0603_10V7K

L6

C205

470U_D2_2.5VM

VTT10
VTT11
VTT12
VTT13
VTT14
VTT15
VTT16
VTT17
VTT18
VTT19
VTT20
VTT21
VTT22
VTT23
VTT24
VTT25
VTT26
VTT27
VTT28
VTT29
VTT30
VTT31
VTT32
VTT33
VTT34
VTT35
VTT36
VTT37
VTT38
VTT39
VTT40
VTT41
VTT42
VTT43
VTT44
VTT45
VTT46
VTT47
VTT48
VTT49
VTT50
VTT51

+1.5VS_DPLLA

1

C209

1

+

2

2

0.1U_0402_16V4Z

U5F

VCCSM0
VCCSM1
VCCSM2
VCCSM3
VCCSM4
VCCSM5
VCCSM6
VCCSM7
VCCSM8

VCCSM9
VCCSM10
VCCSM11
VCCSM12
VCCSM13
VCCSM14
VCCSM15
VCCSM16
VCCSM17
VCCSM18
VCCSM19
VCCSM20
VCCSM21
VCCSM22
VCCSM23
VCCSM24
VCCSM25
VCCSM26
VCCSM27
VCCSM28
VCCSM29
VCCSM30
VCCSM31
VCCSM32
VCCSM33
VCCSM34
VCCSM35
VCCSM36
VCCSM37
VCCSM38
VCCSM39
VCCSM40
VCCSM41
VCCSM42
VCCSM43
VCCSM44
VCCSM45
VCCSM46
VCCSM47
VCCSM48
VCCSM49
VCCSM50
VCCSM51
VCCSM52
VCCSM53
VCCSM54
VCCSM55
VCCSM56
VCCSM57
VCCSM58
VCCSM59
VCCSM60
VCCSM61
VCCSM62
VCCSM63
VCCSM64

ALVISO_BGA1257

V2.5_DDR_CAP1

AM37

V2.5_DDR_CAP2

AH37

V2.5_DDR_CAP5

AP29
AD28
AD27
AC27
AP26
AN26
AM26
AL26
AK26
AJ26
AH26
AG26
AF26
AE26
AP25
AN25
AM25
AL25
AK25
AJ25
AH25
AG25
AF25
AE25
AE24
AE23
AE22
AE21
AE20
AE19
AE18
AE17
AE16
AE15
AE14
AP13
AN13
AM13

Note: Place near chip.

AL13
AK13
AJ13
AH13
AG13
AF13
AE13
AP12
AN12
AM12
AL12
AK12
AJ12
AH12
AG12
AF12
AE12
AD11
AC11
AB11
AB10
AB9

V1.8_DDR_CAP6

AP8

V1.8_DDR_CAP4

AM1

V1.8_DDR_CAP3

AE1

C230

V2.5_DDR_CAP1
V2.5_DDR_CAP2
V2.5_DDR_CAP5

Note : All VCCSM pin
shorted internally.

V1.8_DDR_CAP6
V1.8_DDR_CAP4
V1.8_DDR_CAP3

C201

1

2

1

2

1

2

C248

1

2

+1.8V

10U_0805_6.3V6M

10U_0805_6.3V6M

C35

C236

1

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

C235

C211

2

2

1

1

C192

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z
C246

1

2

@

330U_D2E_2.5VM

1

+

2

0.1U_0402_16V4Z

1

C234

2

C24

C23

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

C239

1

2

+1.8V

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

C199

C198

2

2

1

C212

2

10U_0805_6.3V6M

+1.5VS

+1.5VS_DPLLA
+1.5VS_DPLLB

+1.5VS_HPLL
+1.5VS_MPLL

0.1U_0402_16V4Z

C202

+VCCP

0.1U_0402_16V4Z

1

2

T29
R29
N29

M29

K29
J29
V28

U28

T28

R28

P28
N28
M28

L28

K28

J28
H28
G28

V27
U27

T27
R27

P27
N27
M27

L27

K27

J27
H27

K26
H26

K25

J25

K24

K23

K22

K21
W20
U20

T20

K20

V19
U19

K19
W18

V18

T18

K18

K17
AC1

AC2

B23
C35
AA1
AA2

10U_0805_6.3V6M

10U_0805_6.3V6M

W=20 mils

VCC0
VCC1
VCC2
VCC3
VCC4
VCC5
VCC6
VCC7

POWER

VCC8
VCC9
VCC10
VCC11
VCC12
VCC13
VCC14
VCC15
VCC16
VCC17
VCC18
VCC19
VCC20
VCC21
VCC22
VCC23
VCC24
VCC25
VCC26
VCC27
VCC28
VCC29
VCC30
VCC31
VCC32
VCC33
VCC34
VCC35
VCC36
VCC37
VCC38
VCC39
VCC40
VCC41
VCC42
VCC43
VCC44
VCC45
VCC46
VCC47
VCC48

VCCD_HMPLL1
VCCD_HMPLL2
VCCA_DPLLA
VCCA_DPLLB
VCCA_HPLL
VCCA_MPLL

+VCCP

1

1

1

C543

C542

C544

2

2

2

0.1U_0402_16V4Z

VCCA_TVDACA0
VCCA_TVDACA1
VCCA_TVDACB0
VCCA_TVDACB1
VCCA_TVDACC0
VCCA_TVDACC1

VCCD_TVDAC

VCCDQ_TVDAC

VCCD_LVDS0
VCCD_LVDS1
VCCD_LVDS2

VCCTX_LVDS0
VCCTX_LVDS1
VCCTX_LVDS2

VCCA_3GPLL0
VCCA_3GPLL1
VCCA_3GPLL2

VCCA_CRTDAC0
VCCA_CRTDAC1

VSSA_CRTDAC

ALVISO_BGA1257

1

1

C545

C546

2

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

VCCA_TVBG
VSSA_TVBG

VCCA_LVDS

VCCHV0
VCCHV1
VCCHV2

VCCA_SM0
VCCA_SM1
VCCA_SM2
VCCA_SM3

VCC3G0
VCC3G1
VCC3G2
VCC3G3
VCC3G4
VCC3G5
VCC3G6

VCCA_3GBG
VSSA_3GBG

VCC_SYNC

U5E

F17
E17
D18
C18
F18
E18

H18
G18

D19
H17

B26
B25
A25

A35
B22

B21
A21

B28
A28
A27

AF20
AP19
AF19
AF18

AE37
W37
U37
R37
N37
L37
J37

Y29
Y28
Y27

F37
G37

H20
F19

E19
G19

+1.5VS

+2.5VS
+2.5VS

+2.5VS

4.7U_0805_10V4Z

1

C222

C44

2

0.1U_0402_16V4Z

+2.5VS_CRT_DAC

C221

0.1U_0402_16V4Z

C196

1

1

C195

0.1U_0402_16V4Z

2

2

1

+

2

1

100U_D2_6.3VM

+

2

C28

220U_D2_4VM

L21

1 2

CHB1608U301_0603

C220

0.022U_0402_16V7K

1

1

Route VSSA3GBG gnd from GMCH to

2

2

decoupling cap ground lead and
then connect to the gnd plane.

Route VSSACRTDAC gnd from GMCH to
decoupling cap ground lead and then
connect to the gnd plane.

+1.5VS_PCIE

1

1

C17

C16

C547

2

2

10U_0805_6.3V6M

0.22U_0603_10V7K

+2.5VS

1

+

C443
150U_D2_6.3VM

@

2

CRTDAC: Route caps within
250mil of Alviso. Route FB
within 3" of Alviso.

C249

10U_0805_6.3V6M

+1.5VS

1

2

0.1U_0402_16V4Z

1

2

1

2

C206

10U_0805_6.3V6M

VCCD_LVDS

1

C194

C193

2

0.1U_0402_16V4Z

0.5_0805_1%

1 2

1

2

10U_0805_6.3V6M

R13

BLM18PG600SN1_0603

BLM18PG600SN1_0603

BLM18PG600SN1_0603

3GRLL_R

CHB1608U301_0603

1

C20

0.1U_0402_16V4Z

2

@

1

C216

2

VCC_SYNC

C182

L2

0.1U_0402_16V4Z

0.01U_0402_16V7K

+2.5VS

C214

L7

L1

L3

+2.5VS

1

2

+2.5VS

1

C185

2

0.1U_0402_16V4Z

12

12

+1.5VS+1.5VS_3GPLL

12

1

C21

2

0.1U_0402_16V4Z

+2.5VS+2.5VS_3GBG

12

0.1U_0402_16V4Z

10U_0805_6.3V6M

1

1

C215

2

2

1

C38

2

10U_0805_6.3V6M

VCCHVVCCA_LVDS

+1.5VS

C18

0.1U_0402_16V4Z

1

C19

0.1U_0402_16V4Z

2

1

C40

2

0.1U_0402_16V4Z

+1.5VS+1.5VS_DDRDLL

1

C243

2

1

2

0.1U_0402_16V4Z

+1.5VS_DPLLB

L5

CHB1608U301_0603

+1.5VS

A A

1 2

C188

470U_D2_2.5VM

0.1U_0402_16V4Z

1

C186

1

+

2

2

5

+1.5VS

CHB1608U301_0603

1 2

470U_D2_2.5VM

+1.5VS_HPLL

L9

C73

0.1U_0402_16V4Z

1

C250

1

+

2

2

+1.5VS

CHB1608U301_0603

1 2

470U_D2_2.5VM

4

www.laptopfix.vn

+1.5VS_MPLL

L8

C145

1

1

+

C242

2

2

0.1U_0402_16V4Z

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

+VCCP

+2.5VS

D30

2 1

RB751V_SOD323

+VCCP_CRTDAC_D

2

R714

10_0805_1%

1 2

PJP13

2 1

PAD-SHORT 2x2m

+2.5VS_CRTDAC

Title

Size Document Number Rev
Custom

Date: Sheet

Compal Electronics, Inc.

Alviso(4 of 5)

LA-3361P

1

10 43Thursday, September 21, 2006

0.3

of

5

4

3

2

1

D D

C C

B B

A A

+VCCP

M12
N12

R12
U12
W12
M13

N13
R13
U13
W13

AA12
AA13

M14
N14

R14
U14
W14

AA14
AB14

M15
N15

R15
U15
W15

AA15
AB15

M16
N16

R16
U16
W16

AA16
AB16

R17

AA17
AB17
AA18
AB18
AA19
AB19
AA20
AB20

R21

AA21
AB21

AA22
AB22

AA23
AB23

AA24
AB24

AA25
AB25

AA26
AB26

W25
M26

N26
R26
U26
W26

L12

P12
T12
V12
L13

P13
T13
V13

Y12
Y13
L14

P14
T14
V14
Y14

L15

P15
T15
V15
Y15

L16

P16
T16
V16
Y16

Y17

Y21

Y22

Y23

Y24

Y25

Y26

V25
L26

P26
T26
V26

VTT_NCTF17
VTT_NCTF16
VTT_NCTF15
VTT_NCTF14
VTT_NCTF13
VTT_NCTF12
VTT_NCTF11
VTT_NCTF10
VTT_NCTF9
VTT_NCTF8
VTT_NCTF7
VTT_NCTF6
VTT_NCTF5
VTT_NCTF4
VTT_NCTF3
VTT_NCTF2
VTT_NCTF1
VTT_NCTF0

VSS_NCTF68
VSS_NCTF67
VSS_NCTF66
VSS_NCTF65
VSS_NCTF64
VSS_NCTF63
VSS_NCTF62
VSS_NCTF61
VSS_NCTF60
VSS_NCTF59
VSS_NCTF58
VSS_NCTF57
VSS_NCTF56
VSS_NCTF55
VSS_NCTF54
VSS_NCTF53
VSS_NCTF52
VSS_NCTF51
VSS_NCTF50
VSS_NCTF49
VSS_NCTF48
VSS_NCTF47
VSS_NCTF46
VSS_NCTF45
VSS_NCTF44
VSS_NCTF43
VSS_NCTF42
VSS_NCTF41
VSS_NCTF40
VSS_NCTF39
VSS_NCTF38
VSS_NCTF37
VSS_NCTF36
VSS_NCTF35
VSS_NCTF34
VSS_NCTF33
VSS_NCTF32
VSS_NCTF31
VSS_NCTF30
VSS_NCTF29
VSS_NCTF28
VSS_NCTF27
VSS_NCTF26
VSS_NCTF25
VSS_NCTF24
VSS_NCTF23
VSS_NCTF22
VSS_NCTF21
VSS_NCTF20
VSS_NCTF19
VSS_NCTF18
VSS_NCTF17
VSS_NCTF16
VSS_NCTF15
VSS_NCTF14
VSS_NCTF13
VSS_NCTF12
VSS_NCTF11
VSS_NCTF10
VSS_NCTF9
VSS_NCTF8
VSS_NCTF7
VSS_NCTF6
VSS_NCTF5
VSS_NCTF4
VSS_NCTF3
VSS_NCTF2
VSS_NCTF1
VSS_NCTF0

VCC_NCTF10
VCC_NCTF9
VCC_NCTF8
VCC_NCTF7
VCC_NCTF6
VCC_NCTF5
VCC_NCTF4
VCC_NCTF3
VCC_NCTF2
VCC_NCTF1
VCC_NCTF0

5

VCCSM_NCTF31
VCCSM_NCTF30
VCCSM_NCTF29
VCCSM_NCTF28
VCCSM_NCTF27
VCCSM_NCTF26
VCCSM_NCTF25
VCCSM_NCTF24
VCCSM_NCTF23
VCCSM_NCTF22
VCCSM_NCTF21
VCCSM_NCTF20
VCCSM_NCTF19
VCCSM_NCTF18
VCCSM_NCTF17
VCCSM_NCTF16
VCCSM_NCTF15
VCCSM_NCTF14
VCCSM_NCTF13
VCCSM_NCTF12
VCCSM_NCTF11
VCCSM_NCTF10

VCCSM_NCTF9
VCCSM_NCTF8
VCCSM_NCTF7
VCCSM_NCTF6
VCCSM_NCTF5
VCCSM_NCTF4
VCCSM_NCTF3
VCCSM_NCTF2
VCCSM_NCTF1
VCCSM_NCTF0

VCC_NCTF78
VCC_NCTF77
VCC_NCTF76
VCC_NCTF75
VCC_NCTF74
VCC_NCTF73
VCC_NCTF72
VCC_NCTF71
VCC_NCTF70

NCTF

VCC_NCTF69
VCC_NCTF68
VCC_NCTF67
VCC_NCTF66
VCC_NCTF65
VCC_NCTF64
VCC_NCTF63
VCC_NCTF62
VCC_NCTF61
VCC_NCTF60
VCC_NCTF59
VCC_NCTF58
VCC_NCTF57
VCC_NCTF56
VCC_NCTF55
VCC_NCTF54
VCC_NCTF53
VCC_NCTF52
VCC_NCTF51
VCC_NCTF50
VCC_NCTF49
VCC_NCTF48
VCC_NCTF47
VCC_NCTF46
VCC_NCTF45
VCC_NCTF44
VCC_NCTF43
VCC_NCTF42
VCC_NCTF41
VCC_NCTF40
VCC_NCTF39
VCC_NCTF38
VCC_NCTF37
VCC_NCTF36
VCC_NCTF35
VCC_NCTF34
VCC_NCTF33
VCC_NCTF32
VCC_NCTF31
VCC_NCTF30
VCC_NCTF29
VCC_NCTF28
VCC_NCTF27
VCC_NCTF26
VCC_NCTF25
VCC_NCTF24
VCC_NCTF23
VCC_NCTF22
VCC_NCTF21
VCC_NCTF20
VCC_NCTF19
VCC_NCTF18
VCC_NCTF17
VCC_NCTF16
VCC_NCTF15
VCC_NCTF14
VCC_NCTF13
VCC_NCTF12
VCC_NCTF11

ALVISO_BGA1257

U5H

+1.8V

AB12
AC12
AD12
AB13
AC13
AD13
AC14
AD14
AC15
AD15
AC16
AD16
AC17
AD17
AC18
AD18
AC19
AD19
AC20
AD20
AC21
AD21
AC22
AD22
AC23
AD23
AC24
AD24
AC25
AD25
AC26
AD26

L17

+VCCP
M17
N17

P17
T17
U17
V17
W17
L18
M18
N18
P18
R18
Y18
L19
M19
N19
P19
R19
Y19
L20
M20
N20
P20
R20
Y20
L21
M21
N21
P21
T21
U21
V21
W21
L22
M22
N22
P22
R22
T22
U22
V22
W22
L23
M23
N23
P23
R23
T23
U23
V23
W23
L24
M24
N24
P24
R24
T24
U24
V24
W24
L25
M25
N25
P25
R25
T25
U25

4

www.laptopfix.vn

AA10

AD2
AE2
AH2
AL2
AN2

AA3
AB3
AC3

AF4
AN4

AL5
AP5

AA6
AC6
AE6

AA7
AG7
AK7
AN7

AL8

AA9
AC9
AE9
AH9
AN9
D10

Y10

H11
Y11

Y1
D2

G2

J2
L2
P2
T2
V2

A3
C3

AJ3

C4
H4
L4
P4
U4
Y4

E5

W5

B6
J6
L6
P6
T6

AJ6

G7

V7

C8
E8
L8
P8
Y8

A9
H9
K9
T9
V9

L10

F11

VSS271
VSS270
VSS269
VSS268
VSS260
VSS259
VSS258
VSS257
VSS256
VSS255
VSS254
VSS253
VSS252
VSS251
VSS250
VSS249
VSS248
VSS247
VSS246
VSS245
VSS244
VSS243
VSS242
VSS241
VSS240
VSS239
VSS238
VSS237
VSS236
VSS235
VSS234
VSS233
VSS232
VSS231
VSS230
VSS229
VSS228
VSS227
VSS226
VSS225
VSS224
VSS223
VSS222
VSS221
VSS220
VSS219
VSS218
VSS217
VSS216
VSS215
VSS214
VSS213
VSS212
VSS211
VSS210
VSS209
VSS208
VSS207
VSS206
VSS205
VSS204
VSS203
VSS202
VSS201
VSS200
VSS199
VSS198
VSS197
VSS196

ALVISO_BGA1257

VSS

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

VSSALVDS

VSS195
VSS194
VSS193
VSS192
VSS191
VSS190
VSS189
VSS188
VSS187
VSS186
VSS185
VSS184
VSS183
VSS182
VSS181
VSS180
VSS179
VSS178
VSS177
VSS176
VSS175
VSS174
VSS173
VSS172
VSS171
VSS170
VSS169
VSS168
VSS167
VSS166
VSS165
VSS164
VSS163
VSS162
VSS161
VSS160
VSS159
VSS158
VSS157
VSS156
VSS155
VSS154
VSS153
VSS152
VSS151
VSS150
VSS149
VSS148
VSS147
VSS146
VSS145
VSS144
VSS143
VSS142
VSS141
VSS140
VSS139
VSS138
VSS137
VSS136
VSS135
VSS134
VSS133
VSS132
VSS131
VSS130

U5I

B36
AA11

AF11
AG11
AJ11
AL11
AN11
B12
D12
J12
A14
B14
F14
J14
K14
AG14
AJ14
AL14
AN14
C15
K15
A16
D16
H16
K16
AL16
C17
G17
AF17
AJ17
AN17
A18
B18
U18
AL18
C19
H19
J19
T19
W19
AG19
AN19
A20
D20
E20
F20
G20
V20
AK20
C21
F21
AF21
AN21
A22
D22
E22
J22
AH22
AL22
H23
AF23
B24
D24
F24
J24
AG24
AJ24

AL24

VSS267

AN24

VSS266

A26

VSS265

E26

VSS264

G26

VSS263

J26

VSS262

B27

VSS261

E27

VSS129

G27

VSS128

W27

VSS127

AA27

VSS126

AB27

VSS125
VSS124
VSS123
VSS122
VSS121
VSS120
VSS119
VSS118
VSS117
VSS116
VSS115
VSS114
VSS113
VSS112
VSS111
VSS110
VSS109
VSS108
VSS107
VSS106
VSS105
VSS104
VSS103
VSS102
VSS101
VSS100
VSS99
VSS98
VSS97
VSS96
VSS95
VSS94
VSS93
VSS92
VSS91
VSS90
VSS89
VSS88
VSS87
VSS86
VSS85
VSS84
VSS83
VSS82
VSS81
VSS80
VSS79
VSS78
VSS77
VSS76
VSS75
VSS74
VSS73
VSS72
VSS71
VSS70
VSS69
VSS68

VSS

Title

Size Document Number Rev
Custom

Date: Sheet

AF27
AG27

AJ27
AL27

AN27

E28

W28
AA28
AB28
AC28

A29
D29
E29
F29
G29
H29

L29
P29
U29
V29

W29
AA29
AD29
AG29

AJ29

AM29

C30

Y30
AA30
AB30
AC30
AE30
AP30

D31

E31

F31

G31

H31

J31

K31

L31

M31

N31

P31

R31

T31

U31

V31

W31
AD31
AG31

AL31

A32
C32

Y32
AA32
AB32

2

U5J

AC32

VSS67

AD32

VSS66

AJ32

VSS65

AN32

VSS64

D33

VSS63

E33

VSS62

F33

VSS61

G33

VSS60

H33

VSS59

J33

VSS58

K33

VSS57

L33

VSS56

M33

VSS55

N33

VSS54

P33

VSS53

R33

VSS52

T33

VSS51

U33

VSS50

V33

VSS49

W33

VSS48

AD33

VSS47

AF33

VSS46

AL33

VSS45

C34

VSS44

AA34

VSS43

AB34

VSS42

AC34

VSS41

AD34

VSS40

AH34

VSS39

AN34

VSS38

B35

VSS37

D35

VSS36

E35

VSS35

F35

VSS34

G35

VSS33

H35

VSS32

J35

VSS31

K35

VSS30

L35

VSS29

M35

VSS28

N35

VSS27

P35

VSS26

R35

VSS25

T35

VSS24

U35

VSS23

V35

VSS22

W35

VSS21

Y35

VSS20

AE35

VSS19

C36

VSS18

AA36

VSS17

AB36

VSS16

AC36

VSS15

AD36

VSS14

AE36

VSS13

AF36

VSS12

AJ36

VSS11

AL36

VSS10

AN36

VSS9

E37

VSS8

H37

VSS7

K37

VSS6

M37

VSS5

P37

VSS4

T37

VSS3

V37

VSS2

Y37

VSS1

AG37

VSS0

ALVISO_BGA1257

Compal Electronics, Inc.

Alviso(5 of 5)

LA-3361P

1

0.3

of

11 43Thursday, September 21, 2006

A

B

C

D

E

+1.8V

1 1

220P_0402_50V7K

2 2

3 3

4 4

C562

220P_0402_50V7K

+1.8V +1.8V

C566

+1.8V

C580

220P_0402_50V7K

+1.8V

1

2

1

2

1

2

0304 EMI

DDR_CKE0_DIMMA<7>

DDR_CS1_DIMMA#<7>

1

2

1

2

DDR_A_BS#2<8>

DDR_A_BS#0<8>
DDR_A_WE#<8>

DDR_A_CAS#<8>

CK_SDATA<16>
CK_SCLK<16>

A

C563
220P_0402_50V7K

C567

220P_0402_50V7K

M_ODT1<7>

DDR_A_D0
DDR_A_D1

DDR_A_DQS#0
DDR_A_DQS0

DDR_A_D2
DDR_A_D3

DDR_A_D8
DDR_A_D9

DDR_A_DQS#1
DDR_A_DQS1

DDR_A_D10
DDR_A_D11

DDR_A_D16
DDR_A_D17

DDR_A_DQS#2
DDR_A_DQS2

DDR_A_D18
DDR_A_D19

DDR_A_D24
DDR_A_D25

DDR_A_DM3

DDR_A_D26
DDR_A_D27

DDR_CKE0_DIMMA

DDR_A_BS#2
DDR_A_MA12
DDR_A_MA8
DDR_A_MA5

DDR_A_MA3
DDR_A_MA1

DDR_A_MA10
DDR_A_BS#0
DDR_A_WE#

DDR_A_CAS#
DDR_CS1_DIMMA#

M_ODT1
DDR_A_D32

DDR_A_D33
DDR_A_DQS#4

DDR_A_DQS4
DDR_A_D34

DDR_A_D35
DDR_A_D40

DDR_A_D41
DDR_A_DM5
DDR_A_D42

DDR_A_D43
DDR_A_D48

DDR_A_D49

DDR_A_DQS#6
DDR_A_DQS6

DDR_A_D50
DDR_A_D51

DDR_A_D56
DDR_A_D57

DDR_A_DM7
DDR_A_D58

DDR_A_D59
CK_SDATA

CK_SCLK

+3VS

1 2

C609

0.1U_0402_16V4Z

JP44

1

VREF

3

VSS

5

DQ0

7

DQ1

9

VSS

11

DQS0#

13

DQS0

15

VSS

17

DQ2

19

DQ3

21

VSS

23

DQ8

25

DQ9

27

VSS

29

DQS1#

31

DQS1

33

VSS

35

DQ10

37

DQ11

39

VSS

41

VSS

43

DQ16

45

DQ17

47

VSS

49

DQS2#

51

DQS2

53

VSS

55

DQ18

57

DQ19

59

VSS

61

DQ24

63

DQ25

65

VSS

67

DM3

69

NC

71

VSS

73

DQ26

75

DQ27

77

VSS

79

CKE0
VDD
NC
BA2
VDD
A12
A9
A8
VDD
A5
A3
A1
VDD
A10/AP
BA0
WE#
VDD
CAS#
NC/S1#
VDD
NC/ODT1
VSS
DQ32
DQ33
VSS
DQS4#
DQS4
VSS
DQ34
DQ35
VSS
DQ40
DQ41
VSS
DM5
VSS
DQ42
DQ43
VSS
DQ48
DQ49
VSS
NC,TEST
VSS
DQS6#
DQS6
VSS
DQ50
DQ51
VSS
DQ56
DQ57
VSS
DM7
VSS
DQ58
DQ59
VSS
SDA
SCL
VDDSPD

NC/CKE1

NC/A15
NC/A14

NC/A13

B

81
83
85
87
89
91
93
95
97

99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199

FOX_ASOA426-M4R-TR

CONN@

+1.8V+1.8V

2

DQ4
DQ5
VSS
DM0
VSS
DQ6
DQ7

VSS
DQ12
DQ13

VSS

DM1

VSS

CK0

CK0#

VSS
DQ14
DQ15

VSS

VSS
DQ20
DQ21

VSS

DM2

VSS
DQ22
DQ23

VSS
DQ28
DQ29

VSS

DQS3#

DQS3

VSS
DQ30
DQ31

VSS

VDD

VDD

VDD

VDD
RAS#

VDD
ODT0

VDD

VSS
DQ36
DQ37

VSS

DM4

VSS
DQ38
DQ39

VSS
DQ44
DQ45

VSS

DQS5#

DQS5

VSS
DQ46
DQ47

VSS
DQ52
DQ53

VSS

CK1

CK1#

VSS

DM6

VSS
DQ54
DQ55

VSS
DQ60
DQ61

VSS

DQS7#

DQS7

VSS
DQ62
DQ63

VSS

SAO

VSS

A11

BA1
S0#

SA1

4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

42
44
46
48
50

NC

52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92

A7

94

A6

96
98

A4

100

A2

102

A0

104
106
108
110
112
114
116
118
120

NC

122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200

DDR_A_D4
DDR_A_D5

DDR_A_DM0
DDR_A_D6

DDR_A_D7
DDR_A_D12

DDR_A_D13
DDR_A_DM1
M_CLK_DDR0

M_CLK_DDR#0
DDR_A_D14

DDR_A_D15

DDR_A_D20
DDR_A_D21

DDR_A_DM2
DDR_A_D22

DDR_A_D23
DDR_A_D28

DDR_A_D29
DDR_A_DQS#3

DDR_A_DQS3
DDR_A_D30

DDR_A_D31
DDR_CKE1_DIMMA

DDR_A_MA11
DDR_A_MA7DDR_A_MA9
DDR_A_MA6

DDR_A_MA4
DDR_A_MA2
DDR_A_MA0

DDR_A_BS#1
DDR_A_RAS#
DDR_CS0_DIMMA#

M_ODT0
DDR_A_MA13

DDR_A_D36
DDR_A_D37

DDR_A_DM4
DDR_A_D38

DDR_A_D39
DDR_A_D44

DDR_A_D45
DDR_A_DQS#5

DDR_A_DQS5
DDR_A_D46

DDR_A_D47
DDR_A_D52

DDR_A_D53
M_CLK_DDR1

M_CLK_DDR#1
DDR_A_DM6
DDR_A_D54

DDR_A_D55
DDR_A_D60

DDR_A_D61
DDR_A_DQS#7

DDR_A_DQS7
DDR_A_D62

DDR_A_D63

R666 10K_0402_5%

1 2

R668 10K_0402_5%

1 2

www.laptopfix.vn

V_DDR_MCH_REF

M_CLK_DDR0 <7>
M_CLK_DDR#0 <7>

DDR_CKE1_DIMMA <7>

DDR_A_BS#1 <8>
DDR_A_RAS# <8>
DDR_CS0_DIMMA# <7>

M_ODT0 <7>

M_CLK_DDR1 <7>
M_CLK_DDR#1 <7>

0.1U_0402_16V4Z

2.2U_0805_16V4Z

1

1

C564

2

2

+1.8V

10U_0805_10V4Z@

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

V_DDR_MCH_REF <7>

C565

10U_0805_10V4Z@

1

C573

2

+1.8V

1

C587

0.1U_0402_16V4Z

2

DDR_A_MA2
DDR_A_MA4

DDR_A_MA5
DDR_A_MA8

DDR_A_MA10
DDR_A_MA11

DDR_A_BS#0
DDR_A_BS#2

DDR_A_RAS#
DDR_CKE0_DIMMA

DDR_CKE1_DIMMA
M_ODT1

10U_0805_10V4Z@

1

C574

2

10U_0805_10V4Z@

+1.8V

+

+0.9VS

0.1U_0402_16V4Z

1

2

C596

R647 56_0402_5%
R648 56_0402_5%

R651 56_0402_5%
R652 56_0402_5%

R655 56_0402_5%
R656 56_0402_5%

R659 56_0402_5%
R660 56_0402_5%

R663 56_0402_5%
R664 56_0402_5%

R669 56_0402_5%
R670 56_0402_5%

1

1

C575

2

2

1

C585
150U_D2_6.3VM

2

1

C588

0.1U_0402_16V4Z

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

2

C597

Layout Note:
Place one cap close to every 2 pullup
resistors terminated to +0.9VS

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

C576

1

2

C598

10U_0805_10V4Z@

1

+

2

1

C577

2

C586
150U_D2_6.3VM

1

0.1U_0402_16V4Z

2

0.1U_0402_16V4Z

1

2

C599

+0.9VS

DDR_A_D[0..63]<8>

DDR_A_DM[0..7]<8>

DDR_A_DQS[0..7]<8>

DDR_A_MA[0..13]<8>

DDR_A_DQS#[0..7]<8>

10U_0805_10V4Z@

C589

0.1U_0402_16V4Z

1

1

C579

C578

2

2

10U_0805_10V4Z@

1

C590

0.1U_0402_16V4Z

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

1

2

2

C601

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

2

C602

D

C600

R645 56_0402_5%
R646 56_0402_5%

R649 56_0402_5%
R650 56_0402_5%

R653 56_0402_5%
R654 56_0402_5%

R657 56_0402_5%
R658 56_0402_5%

R661 56_0402_5%
R662 56_0402_5%

R665 56_0402_5%
R667 56_0402_5%

R671 56_0402_5%
R672 56_0402_5%

+1.8V

0.1U_0402_16V4Z

1

2

C603

DDR_A_D[0..63]
DDR_A_DM[0..7]
DDR_A_DQS[0..7]
DDR_A_MA[0..13]
DDR_A_DQS#[0..7]

C568

4.7U_0805_10V4Z

1

C591

0.1U_0402_16V4Z

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

2

C604

DDR_A_MA0
DDR_A_MA1

DDR_A_MA3
DDR_A_MA6

DDR_A_MA7
DDR_A_MA9

DDR_A_MA12
DDR_A_MA13

DDR_A_BS#1
DDR_A_WE#

DDR_A_CAS#

DDR_CS0_DIMMA#
DDR_CS1_DIMMA#

M_ODT0

Layout Note:
Place near DIMM

1

2

1

2

C569

0.1U_0402_16V4Z

1

2

1

2

0.1U_0402_16V4Z

C605

1

1

1

C570

C571

2

2

4.7U_0805_10V4Z

4.7U_0805_10V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

C582

C581

1

1

2

2

C592

0.1U_0402_16V4Z

1

2

C606

Title

Size Document Number Rev

Date: Sheet

1

0.1U_0402_16V4Z

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

2

2

C608

C607

Layout Note:
Place these resistor
closely DIMM0,all
trace length<750 mil

Layout Note:
Place these resistor
closely DIMM0,all
trace length
Max=1.3"

DDR2-SODIMM SLOT0

1

C572

2

2

4.7U_0805_10V4Z

4.7U_0805_10V4Z

0.1U_0402_16V4Z
C584

C583

1

2

1

C593

C594

0.1U_0402_16V4Z

2

Compal Electronics, Inc.

LA-3361P

E

1

C595

2

0.1U_0402_16V4Z

of

12 43Thursday, September 21, 2006

0.3

5

4

3

2

1

C

B

E3

1

2

2222 SYMBOL(SOT23-NEW)

D D

+3VS

2

C1449

0.1U_0402_16V4Z

H_THERMDA<4>

H_THERMDC<4>

C C

H_THERMDA SMB_EC_CK2

H_THERMDC

+3VS

1

C1450
2200P_0402_50V7K

2

R1919

1 2

10K_0402_5%

1

THERM#

SMB_EC_CK2<29>

SMB_EC_DA2<29>

U40

1

VDD

2

D+

3

D­THERM#4GND

ADM1032AR_SOP8

SCLK

SDATA

ALERT#

SMB_EC_CK2
SMB_EC_DA2

8
7
6
5

SMB_EC_DA2

PWM Fan Control circuit

+5VS

JP50

1
2

ACES_85205-0200

CONN@

2

Title

Size Document Number Rev
Custom

Date: Sheet

Compal Electronics, Inc.

Thermal sensor and Fan

LA-3361P

1

13 43Thursday, September 21, 2006

of

0.3

FAN

1

C1452

0.1U_0402_16V4Z

2

12

ZD1

@

RLZ5.1B_LL34

B B

10K_0402_5%@

+3VS

5

U41

1

FAN_PWM<29>

A A

5

4

www.laptopfix.vn

THERM#

INB

2

INA

P

G

TC7SH00FU_SSOP5

3

12

R2011

4

O

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

D38
RB751V_SOD323

2 1

6

2

1

D

Q48

G

3

3

SI3456DV-T1_TSOP6

S

4 5

1

C1451

4.7U_0805_10V4Z

2