Compal LA-3302P, Latitude D630 Schematic

A

B

COMPAL CONFIDENTIAL

C

D

E

1 1

PCB NO :
BOM P/N :

2 2

LA-3302P ( DAA00000K0L)
45144731L01

MODEL NAME :

IBQ00

M08 (DIS) Briscoe

uFCPGA Mobile Merom
Intel Crestline + ICH8M

2007-03-07

3 3

REV : 0.4 (X03)

@ : Nopop Component
1@ : Populate for G72MV
2@ : Populate for G86MV
45144731L01 pop for G86MV

45144XXXXX pop for G72MV

4 4

MB PCB

Part Number Description

DAA00000K0L

PCB ZGX LA-3302P
REV0 M/B DIS

A

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

B

C

D

DELL CONFIDENTIAL/PROPRIETARY

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

Cover Sheet

LA-3302P

166Wednesday, March 07, 2007

E

of

0.4

A

B

C

D

E

Block Diagram
Compal confidential
Model : IBQ01

FAN

1 1

+FAN1_VOUT

RGB

DVI

TV

page 18

LVDS CONN

+INV_PWR_SRC

+LCDVDD

page 19

Thermal

GUARDIAN III
EMC4001

+3.3V_SUS

CRT CONN

+5V_RUN

NV G86

+1.25V_GFX_PCIE
+GPU_CORE(1.1V)

page 51,52,53,54,55,56,57

page 20

page 18

PCI-E 16X

Pentium-M

Merom -4MB (Socket P)

+1.05V_VCCP
+VCC_CORE

H_A#(3..35) H_D#(0..63)

uFCPGA CPU

478pin

System Bus

FSB 800 MHz

page 7,8,9

INTEL

+1.25V_RUN
+1.5V_RUN
+1.8V_SUS
+1.05V_VCCP
+3.3V_RUN
+1.8V_RUN

Crestline

1299pin BGA

page 10,11,12,13,14,15

Memory BUS
(DDR2)

+1.8V_SUS 533 / 667MHz

USB[4]

CPU ITP Port

+1.05V_VCCP

Smart Card

OZ77CR6

+5V_RUN

page 31

Clock Generator

CK505

+3.3V_M

DDRII-DIMM X2

BANK 0, 1, 2, 3, 4 ,5 ,6 ,7 ,8

+0.9V_DDR_VTT
+1.8V_SUS

page6page 7

page 16,17

SLOT

2 2

PCI BUS

DOCKING
PORT

DOCK LPC BUS

PCI_PIRQA#
REQ#0
GNT#0

DOCKING
BUFFER

+5V_RUN

page 36 page 30

USB[8]

page 35

IDSEL:AD17
(PIRQD#,GNT#1,REQ#1)

CardBus

OZ711 LQFP

+3.3V_RUN

USB[6]

PCI Express BUS

Mini Card2

WLAN

3 3

+3.3V_WLAN

Mini Card 1

WWAN

+3.3V_RUN
+1.5V_RUN+1.5V_RUN

page 34page 34

USB[9]

PWR Sequence

page 42

ME & LED

page 43

DC IN

4 4

Battery IN

page 44

page 44

3V / 5V /15V

page 45

1.8V / 0.9V/1.25V

page 46

1.5V / 1.05V

page 47

Vccore

page 48

Charger

page 49

Battery Select

page 50

A

GIGA Enthernet
BCM5755M

+3.3V_LAN
+2.5V_LAN

+1.2V_LAN

RJ45

IO/B

page 28,29

B

(+3VRUN 33MHz)

IEEE1394

page 30

(+1.5V_RUN 100MHz)

DOCK LPC BUS

COM

+3.3V_SUS

page 37

Bluetooth

+3.3V_RUN

USB[7]

+3.3V_ALW

DMI

+1.5V_RUN
100MHz

+1.25V_RUN
+RTC_CELL
+3.3V_RUN
+3.3V_SUS
+1.5V_RUN
+1.05V_VCCP

+3VRUN
33MHz

SMSC SIO
ECE5028

page 38

ECE1077

+3.3V_ALW

page 37

Int.KBD &
Stick

page 40

Trough Cable

INTEL

ICH8-M

676pin BGA

page 21,22,23,24

page 21,22,23,24

LPC BUS

MEC5025

+RTC_CELL
+3.3V_ALW

page 40

Stick

Touch Pad

+5V_RUN

C

SPI

page 39

page 40

48MHz

SATA

S-HDD

+5V_HDD

SPI

ST M25P16

+3.3V_SUS

+3.3V_RUN

USB[5]

USB[2,3]

USB[0,1] SIDE

Azalia I/F

PATA

page 25 page 25 page 26

page 39

Biometric

page 40

REAR

USB Ports X2

+5V_SUS

page 32

USB Ports X2

+5V_SUS

IO/Board

SC_USB

D Moudle

+5V_MOD

AMP & INT.
Speaker

+5V_RUN +3.3V_RUN

Azalia Codec

STAC9205

+3.3V_RUN
+VDDA

INT MIC

+VDDA

page 27 page 27

page 27

DELL CONFIDENTIAL/PROPRIETARY

Title

Size Document Number Rev

D

Date: Sheet

USB2 : Rear Left as viewed from the back,
USB3 Rear Right as viewed from the back

USB0 : side pair top,
USB1 : side pair bottom

MDC

+3.3V_SUS

page 33

Cable

RJ11

IO/B

HeadPhone
& MIC Jack

Compal Electronics, Inc.

Block Diagram
LA-3302P

266Monday, February 26, 2007

E

0.4

of

5

4

3

2

1

POWER STATES

State

D D

S0 (Full ON) / M0

S3 (Suspend to RAM) / M1

S4 (Suspend to DISK) / M1 ON ON ON ONOFF

S5 (SOFT OFF) / M1 ON ON ON ONOFFLOW HIGH LOW HIGHLOW

S3 (Suspend to RAM) / M-OFF

S4 (Suspend to DISK) / M-OFF

S5 (SOFT OFF) / M-OFF

Signal

SLP

SLP

S3#

S4#

HIGH HIGH HIGH

HIGH

LOW HIGH HIGH HIGH ON ON ON ONOFF

LOW HIGH HIGH HIGHLOW

LOW HIGH HIGH HIGH LOW ON ONOFF OFF OFF

LOW LOW LOW LOW ON OFF OFF OFF OFF

LOW LOW LOW LOW LOW ON OFF OFF OFF OFF

SLP
S5#

HIGH

S4
STATE#

SLP
M#

HIGH

HIGH

ALWAYS
PLANE

ON

M
PLANE

ON

SUS

RUN

PLANE

PLANE

ON ON ON

CLOCKS

ICH8-M

USB PORT#

0
1
2
3
4
5
6
7

DESTINATION
Side Top
Side Bottom
Rear Left
Rear Right
Smart Card
Biometric
Card Bus
Bluetooth

C C

B B

PM TABLE

State

S0

S3

S5 S4/AC

S5 S4/AC don't exist

power
plane

+15V_ALW
+5V_ALW
+3.3V_ALW +1.8V_SUS
+3.3V_RTC_LDO

ON

ON

+5V_SUS
+3.3V_SUS

ON ON

ON

OFF

OFFOFF

+5V_RUN
+3.3V_RUN
+2.5V_RUN
+1.8V_RUN
+1.5V_RUN
+VCC_+1P2V_GPU_CORE
+0.9V_DDR_VTT
+GPU_CORE
+VCC_CORE
+1.05V_VCCP

OFFON

OFF

OFF

ON

ON

ON

+1.25V_M

+3.3V_M

(M-OFF)

ON

OFF

OFF

OFFOFF

+3.3V_M
+1.25V_M
+1.05V_M +1.05V_M

ECE 5028

PCI EXPRESS

Lane 1
Lane 2

MINI CARD-1 WWAN
MINI CARD-2 WLAN

8
9
1
2
3
4

DESTINATION

Docking
WWAN
None
None
None
None

PCI TABLE

Lane 3

PCI DEVICE IDSEL

OZ711

REQ#/GNT#

REQ#1 / GNT#1AD17 PIRQD

PIRQ

Lane 4
Lane 5
Lane 6

A A

AD24 REQ#0 / GNT#0

PIRQADocking

None
None
None
GIGA LAN

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

Index and Config.

LA-3302P

366Monday, February 26, 2007

1

0.4

of

5

4

3

2

1

RUN_ON

ADAPTER

D D

+PWR_SRC

FDS4435

(Q24)

ISL6236
(PU25)

M_ON

GFX_CORE_ON

+INV_PWR_SRC

+1.25V_M

+GPU_CORE

RUN_ON

MAX1510E

(PU26)

MAX1510E

(PU26)

+1.25V_RUN

+1.05V_M

BATTERY

RUN_ON

SI4810DY

(Q58)

+15V_ALW

+5V_RUNSI4810DY

(Q52)

M_ON

SI4800BDY

(Q67)

CHARGER

ISL6260

C C

SUS_ON

+5V_SUS

+3.3V_SUS

(PU11) (PU6)

RUNPWROK

+VCC_CORE

ISlL88550_AVDD

+1.8V_SUS +0.9V_DDR_VTT

ISL88550A

DDR_ON

ISL6236
(PU21)

1.05V_RUN_ON

1.5V_RUN_ON

ISL6236
(PU20)

+1.05V_VCCP +1.5V_RUN

ALWON

ALWON

+5V_ALW

+3.3V_ALW

ENAB_3VLAN

SI3456BDV

RUN_ON

(Q44)

RUN_ON

B B

MAX9789A

AUDIO_AVDD_ON

SI3456BDV

(Q54)

HDDC_EN#

SI3456SI3456BDV

(Q48)(Q56) (U37)

MODC_EN#

+3.3V_LAN

CTRL_18

+3.3V_RUN

CTRL_10

+3.3V_M

BCP69 BCP69

+5V_HDD

+5V_MOD

(Q45)

+VDDA

(Q46)

+1.8VRUN

A A

+1.8V_LAN +1.0V_LAN

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

Power Rail
LA-3302P

466Monday, February 26, 2007

1

0.4

of

5

AJ26

ICH_SMBCLK
ICH_SMBDATA

ICH8-M

D D

AD19

2.2K

2.2K

4

+3.3V_SUS

WWAN

SMBUS Address [TBD]

3

3032

C8C7

Intel LAN

SMBUS Address [TBD]

32 30

2N7002
2N7002

2N7002
2N7002

WLAN_SMBCLK
WLAN_SMBDATA

2.2K

2.2K

2

MEM_SCLK
MEM_SDATA

+3.3V_WLAN

WLAN

2.2K

2.2K

@ 0

+3.3V_RUN

197
195

DIMMA

197
195

DIMMB

CLK_SCLK@ 0

CLK_SDATA

1

SMBUS Address [TBD]

SMBUS Address [TBD]

SMBUS Address [TBD]

8.2K

8.2K

8

LCD_SMBCLK

7

C C

LCD_SMDATA

4.7K

4.7K

100

THRM_SMBCLK

99

THRM_SMBDAT

+3.3V_ALW

+3.3V_ALW

6

5
10
9
12
11

INVERTER
(JLVDS)

Charger

EMC4001

SMBUS Address [TBD]

SMBUS Address [TBD]

SMBUS Address [TBD]

2.2K

SBAT_SMBCLK

10

SBAT_SMBDAT

SIO

9

2.2K

2.2K

111

PBAT_SMBCLK
PBAT_SMBDAT

112

B B

2.2K

+3.3V_ALW

100 ohm
100 ohm

+3.3V_ALW

100 ohm
100 ohm

3

4

3
4

9

10

2'nd
BATTERY

BATTERY
CONN

CHARGER

SMBUS Address [TBD]

SMBUS Address [TBD]

SMBUS Address [TBD]

8.2K

+5V_ALW

6

5

DOCKING

SMBUS Address [TBD]

MEC 5025

6
5

8.2K

DOCK_SMB_CLK
DOCK_SMB_DAT

2.2K

2.2K

CKG_SMBDAT

12

CKG_SMBCLK

13

2N7002
2N7002

+3.3V_RUN

CLK_SDATA

CLK_SCLK

17

16

CLK GEN

SMBUS Address [TBD]

A A

Title

Size Document Number Rev

5

4

3

2

Date: Sheet

Compal Electronics, Inc.

SMBUS TOPOLOGY
LA-3302P

566Monday, February 26, 2007

1

0.4

of

5

+3.3V_RUN

R435

@

1 2

0_0402_5%~D

CKG_SMBDAT39

D D

+3.3V_RUN

CKG_SMBCLK39

FSC FSB FSA CPU

CLKSEL2 CLKSEL0CLKSEL1

1 3

1 3

1 2

R440

@

0_0402_5%~D

000

1

00

1

0

*

0

1

C C

1

1

11

0

11

00

1

0

1

0

1

R265

D

S

Q34
2N7002W-7-F_SOT323-3~D

G

2
2

G

Q35

2N7002W-7-F_SOT323-3~D

D

S

SRC

MHz

MHz

100

266

100

133

100

200

100

166

100

333

100

100

100

400

200 100 33.3

Table : ICS954305AK

CPU_BSEL CPU_BSEL2(FSC) CPU_BSEL1(FSB)

133

166

+3.3V_RUN

R290

B B

10K_0402_5%~D

1 2

PCI_PCM

+3.3V_RUN

12

R304
10K_0402_5%~D

PCI_ICH

0

0

CLK_NV_27M52

84.5_0402_1%~D

Populate R697,R833 for G72MV
Populate R286 for G86MV.
R833,R286 place overlap

PGMODE

ITP_EN

+3.3V_RUN +3.3V_RUN

12

R318
10K_0402_5%~D

A A

PCI_LOM

12

R319

@

10K_0402_5%~D

12

R329

@

10K_0402_5%~D

FSA

12

R391

@

10K_0402_5%~D

*

TME

*

FCTSEL1 PIN43 PIN44 PIN47 PIN48

0=UMA

*

0=UMA

1=DIS

12

12

R266

2.2K_0402_5%~D

2.2K_0402_5%~D

CLK_SDATA

CLK_SCLK

PCI
MHz

33.3

33.3

33.3

33.3

33.3

33.3

Place crystal within

33.3

500 mils of CK410

CLK_ICH_48M23

CLK_SMC_48M31
CPU_MCH_BSEL08,10
CPU_MCH_BSEL18,10

CPU_MCH_BSEL28,10

CLK_PCI_TPM28

0

1

R697

1@

0
1

0
1

Normal Operation

0

Trusted Mode Enabled

1

CLK_PCI_DOCK36

CLK_PCI_PCM30

CLK_PCI_502539

CLK_PCI_501838
CLK_ICH_14M23

CLK_SIO_14M38

CLK_NVSS_27M52

12

CLK_PCI_ICH21

CLK_PWRGD23

PIN 9
VTT_PWRGD#/PD
CKPWRGD/PD#

PIN 37
Pin 5/6 as SRC_10
Pin 5/6 as CPU_ITP

PIN 32

DOT96T DOT96C 96/100M_T 96/100M_C

27M_out 27M SSout SRCT0 SRCC0

1=Disc. GRFX down

5

+CK_VDD_48

1

C99

2

4.7U_0603_6.3V4Z~D

1

C708

2

3.3P_0402_50V8C~D

C483

27P_0402_50V8J~D

C484

33P_0402_50V8J~D

CLK_NVSS_27M

4

1

C471

2

0.1U_0402_16V4Z~D

1

C799

2

0.047U_0402_16V4Z~D

CLK_SMC_48MCLK_ICH_48M

1

2

X1

14.31818MHz_20P_1BX14318CC1A~D

12

12

12

CLK_ICH_48M
CLK_SMC_48M

CLK_PCI_TPM
CLK_PCI_DOCK

CLK_PCI_PCM
CLK_PCI_5025

CLK_PCI_5018
CLK_ICH_14M

CLK_SIO_14M
CLK_NV_27M

CLK_PCI_ICH

CLK_PWRGD

+3.3V_RUN

4

1 2

L28

BLM21PG600SN1D_0805~D

L87

0.047U_0402_16V4Z~D

0_0402_5%~D

1 2

R298

CLK_SCLK34

CLK_SDATA34

R271

12

12
12

12
12

12

+CK_VDD_MAIN2

1 2

BLM21PG600SN1D_0805~D

+CK_VDD_REF

1

C189

2

C774

3.3P_0402_50V8C~D

R273 15_0402_5%~D
R275 15_0402_5%~D

1 2

R309 2.2K_0402_5%~D

1 2

R314 8.2K_0402_5%~D

1 2

R277 33_0402_5%~D
R596 33_0402_5%~D

R280 33_0402_5%~D
R282 15_0402_5%~D

R333 15_0402_5%~D

1 2

R284 15_0402_5%~D

1 2

R285 15_0402_5%~D

1 2

R286 33_0402_5%~D 2@

1 2

R833 147_0402_1%~D1@

1 2

R287 33_0402_5%~D

1 2

R291 33_0402_5%~D

R295

@

10K_0402_5%~D

1 2

@

1 2

10K_0402_5%~D

R760

1 2
1 2

R758 2.2_0603_5%~D

+CK_VDD_MAIN+3.3V_RUN

1_0603_5%~D

CLK_XTAL_IN

CLK_XTAL_OUT

FSA

FSC

PCI_LOM
PCI_DOCK
PCI_PCM
PCI_SIO

CLKREF

DOT96

CLK_NVSS

PCI_ICH

PGMODE

CLK_SCLK

CLK_SDATA

3

+CK_VDD_MAIN

1

1

1

C474

C473

C472

2

10U_0805_10V4Z~D

1

C480

2

10U_0805_10V4Z~D

R759

1 2

2.2_0603_5%~D

U28

1
49
54
65

30
36

+CK_VDD_REF
+CK_VDD_48

12
18
40

20

19

41
45
23

34
33
32
27

22

43
44

37

39

9

16

17

4
15
21
31
35
42
68

73
74
75
76

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

2

2

1

2

VDD_SRC
VDD_SRC
VDD_SRC
VDD_SRC

VDD_PCI
VDD_PCI

VDD_CPU
VDD_REF
VDD_48

XTAL_IN

XTAL_OUT

USB_48MHz/FSLA
FSL_B/TEST_MODE
REF_0/FSL_C/TEST_SEL

PCICLK4/FCT_SEL
PCICLK3
PCICLK2/TME
PCICLK1

REF_1

DOT_96/27M
DOT_96#/27M_SS

PCICLK_F0/ITP_EN

CKPWRGD/PD#

PGMODE

SMBCLK

SMBDAT

VSS_SRC
VSS_CPU
VSS_REF
VSS_PCI
VSS_PCI
VSS_48
VSS_SRC

THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD

0.1U_0402_16V4Z~D

1

C481

2

0.1U_0402_16V4Z~D

SLG8LP550

C482

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

1

1

C475

2

2

0.1U_0402_16V4Z~D

+CK_VDD_A

VDD_A
VSS_A

PCI_STP#

CPU_STP#

CPU_1

CPU_1#

CPU_0

CPU_0#

CPU_ITP/SRC_10

CPU_ITP#/SRC_10#

SRC_9

SRC_9#

CLKREQ_9#

SRC_8

SRC_8#

CLKREQ_8#

SRC_7

SRC_7#

CLKREQ_7#

SRC_6

SRC_6#

CLKREQ_6#

SRC_5

SRC_5#

CLKREQ_5#

SRC_4

SRC_4#

CLKREQ_4#

SRC_3

SRC_3#

CLKREQ_3#

SRC_2

SRC_2#

CLKREQ_2#

SRC_1/SATA

SRC_1#/SATA#

CLKREQ_1#

LCD_CLK/SRC_0

LCD_CLK#/SRC_0#

SLG8LP550_QFN72~D

1

C476

2

0.1U_0402_16V4Z~D

7
8

25
24

11
10

14
13

6
5

3
2
72
70
69
71
66
67
38
63
64
62
60
61
29
58
59
57
55
56
28
52
53
26
50
51
46
47
48

C477

0.1U_0402_16V4Z~D

H_STP_PCI#
H_STP_CPU#

MCH_BCLK
MCH_BCLK#

CPU_BCLK
CPU_BCLK#

CPU_ITP
CPU_ITP#

PCIE_MINI1
PCIE_MINI1#

PCIE_MINI2
PCIE_MINI2#

PCIE_ICH
PCIE_ICH#

PCIE_LOM
PCIE_LOM#

PCIE_VGA
PCIE_VGA#

MCH_3GPLL
MCH_3GPLL#

PCIE_SATA
PCIE_SATA#

2

1

1

C478

2

2

4.7U_0603_6.3V4Z~D

1 2

R267 33_0402_5%~D

1 2

R268 33_0402_5%~D

1 2

R269 33_0402_5%~D

1 2

R270 33_0402_5%~D

1 2

R272 33_0402_5%~D

1 2

R274 33_0402_5%~D

1 2

R311 33_0402_5%~D

1 2

R313 33_0402_5%~D

1 2

R306 33_0402_5%~D

1 2

R307 33_0402_5%~D

1 2

R288 33_0402_5%~D

1 2

R289 33_0402_5%~D

1 2

R302 33_0402_5%~D

1 2

R303 33_0402_5%~D

1 2

R299 33_0402_5%~D

1 2

R168 33_0402_5%~D

1 2

R293 33_0402_5%~D

1 2

R294 33_0402_5%~D

1 2

R419 475_0402_1%~D

1 2

R279 33_0402_5%~D

1 2

R281 33_0402_5%~D

2

C479

0.047U_0402_16V4Z~D

1

+3.3V_RUN

CLK_MCH_BCLK
CLK_MCH_BCLK#

CLK_CPU_BCLK
CLK_CPU_BCLK#

CLK_CPU_ITP
CLK_CPU_ITP#

CLK_PCIE_MINI1
CLK_PCIE_MINI1#

CLK_PCIE_MINI2
CLK_PCIE_MINI2#

CLK_PCIE_ICH
CLK_PCIE_ICH#

CLK_PCIE_LOM
CLK_PCIE_LOM#

CLK_PCIE_VGA
CLK_PCIE_VGA#

CLK_MCH_3GPLL
CLK_MCH_3GPLL#

CLK_PCIE_SATA
CLK_PCIE_SATA#

MINI1CLK_REQ#
MINI2CLK_REQ#
CLK_3GPLLREQ#
SATA_CLKREQ#
LOM_CLKREQ#

H_STP_PCI# 23

H_STP_CPU# 23

CLK_MCH_BCLK 10
CLK_MCH_BCLK# 10

CLK_CPU_BCLK 7
CLK_CPU_BCLK# 7

CLK_CPU_ITP 7
CLK_CPU_ITP# 7

CLK_PCIE_MINI1 34

CLK_PCIE_MINI1# 34

MINI1CLK_REQ# 34

CLK_PCIE_MINI2 34
CLK_PCIE_MINI2# 34

MINI2CLK_REQ# 34

CLK_PCIE_ICH 23
CLK_PCIE_ICH# 23

CLK_PCIE_LOM 28

CLK_PCIE_LOM# 28

LOM_CLKREQ# 28

CLK_PCIE_VGA 52
CLK_PCIE_VGA# 52

CLK_MCH_3GPLL 10

CLK_MCH_3GPLL# 10

CLK_3GPLLREQ# 10

CLK_PCIE_SATA 22

CLK_PCIE_SATA# 22

SATA_CLKREQ# 23

1 2

R315 10K_0402_5%~D

1 2

R310 10K_0402_5%~D
R297 10K_0402_5%~D
R283 10K_0402_5%~D
R301 10K_0402_5%~D

1 2
1 2
1 2

CLK_ICH_14M

1

2

CLK_SIO_14M

1

2

CLK_PCI_TPM

1

2

CLK_PCI_DOCK

1

2

CLK_PCI_PCM

1

2

CLK_PCI_5025

1

2

CLK_PCI_5018

1

2

CLK_PCI_ICH

1

2

C775

3.3P_0402_50V8C~D

@

C776

3.3P_0402_50V8C~D

@

C777

3.3P_0402_50V8C~D

@

C778

3.3P_0402_50V8C~D

@

C779

3.3P_0402_50V8C~D

@

C780

3.3P_0402_50V8C~D

@

C781

3.3P_0402_50V8C~D

@

C785

3.3P_0402_50V8C~D

@

DELL CONFIDENTIAL/PROPRIETARY

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

Clock Generator
LA-3302P

1

666Thursday, March 01, 2007

0.4

of

5

4

3

2

1

H_A#[3..35]10

D D

H_ADSTB#010

H_REQ#010
H_REQ#110
H_REQ#210
H_REQ#310
H_REQ#410

C C

H_ADSTB#110

H_A20M#22

H_FERR#22

H_IGNNE#22
H_STPCLK#22

H_INTR22
H_NMI22
H_SMI#22

B B

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_ADSTB#0

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35
H_ADSTB#1

H_A20M#
H_FERR#
H_IGNNE#

H_STPCLK#
H_INTR
H_NMI
H_SMI#

JCPUA

J4

A[3]#

L5

A[4]#

L4

A[5]#

K5

A[6]#

M3

A[7]#

N2

A[8]#

J1

A[9]#

N3

A[10]#

P5

A[11]#

P2

A[12]#

L2

A[13]#

P4

A[14]#

P1

A[15]#

R1

A[16]#

M1

ADSTB[0]#

K3

REQ[0]#

H2

REQ[1]#

K2

REQ[2]#

J3

REQ[3]#

L1

REQ[4]#

Y2

A[17]#

U5

A[18]#

R3

A[19]#

W6

A[20]#

U4

A[21]#

Y5

A[22]#

U1

A[23]#

R4

A[24]#

T5

A[25]#

T3

A[26]#

W2

A[27]#

W5

A[28]#

Y4

A[29]#

U2

A[30]#

V4

A[31]#

W3

A[32]#

AA4

A[33]#

AB2

A[34]#

AA3

A[35]#

V1

ADSTB[1]#

A6

A20M#

A5

FERR#

C4

IGNNE#

D5

STPCLK#

C6

LINT0

B4

LINT1

A3

SMI#

M4

RSVD[01]

N5

RSVD[02]

T2

RSVD[03]

V3

RSVD[04]

B2

RSVD[05]

C3

RSVD[06]

D2

RSVD[07]

D22

RSVD[08]

D3

RSVD[09]

F6

RSVD[10]

TYCO_1-1674770-2_Merom~D

ADDR GROUP 0

ADDR GROUP 1

ICH

+1.05V_VCCP

DEFER#

DRDY#
DBSY#

LOCK#

RESET#

CONTROLXDP/ITP SIGNALS

TRDY#

BPM[0]#
BPM[1]#
BPM[2]#
BPM[3]#

PRDY#
PREQ#

THERMAL

PROCHOT#

THERMDA
THERMDC

THERMTRIP#

H CLK

BCLK[0]
BCLK[1]

RESERVED

ADS#
BNR#
BPRI#

BR0#

IERR#

INIT#

RS[0]#
RS[1]#
RS[2]#

HIT#

HITM#

TCK

TDI
TDO
TMS

TRST#

DBR#

R327

56_0402_5%~D

1 2

H1
E2
G5

H5
F21
E1

F1
D20

B3
H4
C1

F3
F4
G3
G2

G6
E4

AD4
AD3
AD1
AC4
AC2
AC1
AC5
AA6
AB3
AB5
AB6
C20

D21
A24
B25

C7

A22
A21

H_ADS#
H_BNR#
H_BPRI#

H_DEFER#
H_DRDY#
H_DBSY#

H_BR0#
H_IERR#

H_INIT#
H_LOCK#
H_RESET#

H_RS#0
H_RS#1
H_RS#2
H_TRDY#

H_HIT#
H_HITM#

ITP_BPM#0
ITP_BPM#1
ITP_BPM#2
ITP_BPM#3
ITP_BPM#4
ITP_BPM#5
ITP_TCK
ITP_TDI
ITP_TDO
ITP_TMS
ITP_TRST#

ITP_DBRESET#

H_THERMTRIP#
CLK_CPU_BCLK

CLK_CPU_BCLK#

H_THERMTRIP#

H_INIT# 22

H_LOCK# 10

H_RESET# 10
H_RS#0 10
H_RS#1 10
H_RS#2 10
H_TRDY# 10

T47 PAD~D
T48 PAD~D
T49 PAD~D
T50 PAD~D
T51 PAD~D
T52 PAD~D

ITP_DBRESET# 23,38

EC_CPU_PROCHOT#
H_THERMDA

H_THERMDC

1

2

H_ADS# 10

H_BNR# 10
H_BPRI# 10

H_DEFER# 10
H_DRDY# 10

H_DBSY# 10

H_BR0# 10

H_HIT# 10

H_HITM# 10

C417
2200P_0402_50V7K~D

H_THERMTRIP# 18

CLK_CPU_BCLK 6

CLK_CPU_BCLK# 6

R320

12

56_0402_5%~D

+1.05V_VCCP

H_RESET#

+1.05V_VCCP

12

R323
56_0402_5%~D

EC_CPU_PROCHOT# 39

H_THERMDA 18

H_THERMDC 18

H_THERMDA, H_THERMDC routing together,
Trace width / Spacing = 10 / 10 mil

R321

22.6_0402_1%~D

1 2

CLK_CPU_ITP6
CLK_CPU_ITP#6

+1.05V_VCCP

ITP_DBRESET#

CLK_CPU_ITP
CLK_CPU_ITP#

+1.05V_VCCP

+3.3V_SUS

+1.05V_VCCP

@

0.1U_0402_16V4Z~D

1

1

C486

C485

2

2

Place near JITP

R324

150_0402_5%~D

1 2

R325

51_0402_5%~D

R326

51_0402_1%~D

R328

39_0402_1%~D

R330

150_0402_5%~D

This shall place near CPU

R331

649_0402_1%~D

1 2

R332

27_0402_1%~D

JITP

28

VTT1

27

VTT0

26

VTAP

25

DBR#

24

DBA#

23

BPM0#

22

GND5

21

BPM1#

20

GND4

19

BPM2#

18

GND3

17

BPM3#

16

GND2

15

BPM4#

14

GND1

13

BPM5#

12

RESET#

11

FBO

10

GND0

9

BCLKP

8

BCLKN

7

TDO

6

NC2

5

TCK

4

NC1

3

TRST#

2

TMS

1

TDI

@

0.1U_0402_16V4Z~D

ITP_DBRESET#

ITP_TDO

H_RESET#

ITP_TMS

ITP_TDI

ITP_TRST#

ITP_TCK

29

30

GND6

GND7

JCPUD

A4

VSS[001]

A8

VSS[002]

A11

VSS[003]

A14

VSS[004]

A16

VSS[005]

A19

VSS[006]

A23

VSS[007]

AF2

VSS[008]

B6

VSS[009]

B8

VSS[010]

B11

VSS[011]

B13

VSS[012]

B16

VSS[013]

B19

VSS[014]

B21

VSS[015]

B24

VSS[016]

C5

VSS[017]

C8

VSS[018]

C11

VSS[019]

C14

VSS[020]

C16

VSS[021]

C19

VSS[022]

C2

VSS[023]

C22

VSS[024]

C25

VSS[025]

D1

MOLEX_52435-2891_28P~D@

VSS[026]

D4

VSS[027]

D8

VSS[028]

D11

VSS[029]

D13

VSS[030]

D16

VSS[031]

D19

VSS[032]

D23

VSS[033]

D26

VSS[034]

E3

VSS[035]

E6

VSS[036]

E8

VSS[037]

E11

VSS[038]

E14

VSS[039]

E16

VSS[040]

E19

VSS[041]

E21

VSS[042]

E24

VSS[043]

F5

VSS[044]

F8

VSS[045]

F11

VSS[046]

F13

VSS[047]

F16

VSS[048]

F19

VSS[049]

F2

VSS[050]

F22

VSS[051]

F25

VSS[052]

G4

VSS[053]

G1

VSS[054]

G23

VSS[055]

G26

VSS[056]

H3

VSS[057]

H6

VSS[058]

H21

VSS[059]

H24

VSS[060]

J2

VSS[061]

J5

VSS[062]

J22

VSS[063]

J25

VSS[064]

K1

VSS[065]

K4

VSS[066]

K23

VSS[067]

K26

VSS[068]

L3

VSS[069]

L6

VSS[070]

L21

VSS[071]

L24

VSS[072]

M2

VSS[073]

M5

VSS[074]

M22

VSS[075]

M25

VSS[076]

N1

VSS[077]

N4

VSS[078]

N23

VSS[079]

N26

VSS[080]

P3

VSS[081]

TYCO_1-1674770-2_Merom~D

VSS[082]
VSS[083]
VSS[084]
VSS[085]
VSS[086]
VSS[087]
VSS[088]
VSS[089]
VSS[090]
VSS[091]
VSS[092]
VSS[093]
VSS[094]
VSS[095]
VSS[096]
VSS[097]
VSS[098]
VSS[099]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
VSS[159]
VSS[160]
VSS[161]
VSS[162]
VSS[163]

P6
P21
P24
R2
R5
R22
R25
T1
T4
T23
T26
U3
U6
U21
U24
V2
V5
V22
V25
W1
W4
W23
W26
Y3
Y6
Y21
Y24
AA2
AA5
AA8
AA11
AA14
AA16
AA19
AA22
AA25
AB1
AB4
AB8
AB11
AB13
AB16
AB19
AB23
AB26
AC3
AC6
AC8
AC11
AC14
AC16
AC19
AC21
AC24
AD2
AD5
AD8
AD11
AD13
AD16
AD19
AD22
AD25
AE1
AE4
AE8
AE11
AE14
AE16
AE19
AE23
AE26
A2
AF6
AF8
AF11
AF13
AF16
AF19
AF21
A25
AF25

A A

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

Merom Processor(1/2)
LA-3302P

766Thursday, March 01, 2007

1

0.4

of

5

4

3

2

1

+VCC_CORE +VCC_CORE

D D

C C

B B

R335

@

1 2

1K_0402_5%~D

A A

H_D#[0..63]10

H_DSTBN#010
H_DSTBP#010

H_DINV#010

H_DSTBN#110
H_DSTBP#110

H_DINV#110

V_CPU_GTLREF

CPU_MCH_BSEL06,10
CPU_MCH_BSEL16,10
CPU_MCH_BSEL26,10

TEST1
TEST2
TEST4
TEST6

2

R394

C490

R336

@

1 2

1K_0402_5%~D

Place C490 close to the
CPU_TEST4 pin. Make sure
CPU_TEST4 routing is
reference to GND and away
from other noisy signal.

@

@

1

0_0402_5%~D

1 2

0.1U_0402_16V4Z~D

5

H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_DSTBN#0
H_DSTBP#0
H_DINV#0

H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_DSTBN#1
H_DSTBP#1
H_DINV#1

TEST1
TEST2
TEST3
TEST4
TEST5
TEST6

CPU_MCH_BSEL0
CPU_MCH_BSEL1
CPU_MCH_BSEL2

For the purpose of testability, route these signals
through a ground referenced Z0 = 55ohm trace that
ends in a via that is near a GND via and is
accessible through an oscilloscope connection.

FSB
533
667
800

JCPUB

E22

D[0]#

F24

D[1]#

E26

D[2]#

G22

D[3]#

F23

D[4]#

G25
E25
E23
K24
G24

J24

J23
H22
F26
K22
H23

J26
H26
H25

N22
K25
P26
R23

L23
M24

L22
M23
P25
P23
P22
T24
R24

L25
T25
N25

L26
M26
N24

AD26

C23
D25
C24

AF26

AF1
A26

B22
B23
C21

T30PAD~D
T31PAD~D

DATA GRP 0 DATA GRP 1

D[5]#
D[6]#
D[7]#
D[8]#
D[9]#
D[10]#
D[11]#
D[12]#
D[13]#
D[14]#
D[15]#
DSTBN[0]#
DSTBP[0]#
DINV[0]#

D[16]#
D[17]#
D[18]#
D[19]#
D[20]#
D[21]#
D[22]#
D[23]#
D[24]#
D[25]#
D[26]#
D[27]#
D[28]#
D[29]#
D[30]#
D[31]#
DSTBN[1]#
DSTBP[1]#
DINV[1]#

GTLREF

MISC

TSET1
TEST2
TEST3
TEST4
TEST5
TEST6

BSEL[0]
BSEL[1]
BSEL[2]

TYCO_1-1674770-2_Merom~D

TEST3
TEST5

DATA GRP 2DATA GRP 3

DSTBN[2]#
DSTBP[2]#

DINV[2]#

DSTBN[3]#
DSTBP[3]#

DINV[3]#

COMP[0]
COMP[1]
COMP[2]
COMP[3]

DPRSTP#

DPSLP#
DPWR#

PWRGOOD

BCLK BSEL2 BSEL1 BSEL0
133

001
166
200

100

D[32]#
D[33]#
D[34]#
D[35]#
D[36]#
D[37]#
D[38]#
D[39]#
D[40]#
D[41]#
D[42]#
D[43]#
D[44]#
D[45]#
D[46]#
D[47]#

D[48]#
D[49]#
D[50]#
D[51]#
D[52]#
D[53]#
D[54]#
D[55]#
D[56]#
D[57]#
D[58]#
D[59]#
D[60]#
D[61]#
D[62]#
D[63]#

SLP#

PSI#

4

Y22
AB24
V24
V26
V23
T22
U25
U23
Y25
W22
Y23
W24
W25
AA23
AA24
AB25
Y26
AA26
U22

AE24
AD24
AA21
AB22
AB21
AC26
AD20
AE22
AF23
AC25
AE21
AD21
AC22
AD23
AF22
AC23
AE25
AF24
AC20

R26
U26
AA1
Y1

E5
B5
D24
D6
D7
AE6

110

H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_DSTBN#2
H_DSTBP#2
H_DINV#2

H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
H_DSTBN#3
H_DSTBP#3
H_DINV#3

COMP0
COMP1
COMP2
COMP3

H_DPRSTP#
H_DPSLP#
H_DPWR#
H_PWRGOOD
H_CPUSLP#
H_PSI#

V_CPU_GTLREF

+1.05V_VCCP

12

R341
1K_0402_1%~D

12

R344
2K_0402_1%~D

H_DPRSTP# 10,22,48

H_DPSLP# 22

H_DPWR# 10

H_PWRGOOD 22

H_CPUSLP# 10

H_PSI# 48

Layout close CPU PIN AD26
55 ohm, 0.5 inch (max)

H_DSTBN#2 10
H_DSTBP#2 10

H_DINV#2 10

H_DSTBN#3 10
H_DSTBP#3 10

H_DINV#3 10

27.4_0402_1%~D

54.9_0402_1%~D

12

12

R338

R337

Resistor placed within 0.5" of
CPU pin.Trace should be at least
25 mils away from any other
toggling signal. COMP0, COMP2
trace should be 27.4 ohm.
COMP1, COMP3 should be 55
ohm.

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

12

R339

27.4_0402_1%~D

54.9_0402_1%~D

12

R340

JCPUC

A7

VCC[001]

A9

VCC[002]

A10

VCC[003]

A12

VCC[004]

A13

VCC[005]

A15

VCC[006]

A17

VCC[007]

A18

VCC[008]

A20

VCC[009]

B7

VCC[010]

B9

VCC[011]

B10

VCC[012]

B12

VCC[013]

B14

VCC[014]

B15

VCC[015]

B17

VCC[016]

B18

VCC[017]

B20

VCC[018]

C9

VCC[019]

C10

VCC[020]

C12

VCC[021]

C13

VCC[022]

C15

VCC[023]

C17

VCC[024]

C18

VCC[025]

D9

VCC[026]

D10

VCC[027]

D12

VCC[028]

D14

VCC[029]

D15

VCC[030]

D17

VCC[031]

D18

VCC[032]

E7

VCC[033]

E9

VCC[034]

E10

VCC[035]

E12

VCC[036]

E13

VCC[037]

E15

VCC[038]

E17

VCC[039]

E18

VCC[040]

E20

VCC[041]

F7

VCC[042]

F9

VCC[043]

F10

VCC[044]

F12

VCC[045]

F14

VCC[046]

F15

VCC[047]

F17

VCC[048]

F18

VCC[049]

F20

VCC[050]

AA7

VCC[051]

AA9

VCC[052]

AA10

VCC[053]

AA12

VCC[054]

AA13

VCC[055]

AA15

VCC[056]

AA17

VCC[057]

AA18

VCC[058]

AA20

VCC[059]

AB9

VCC[060]

AC10

VCC[061]

AB10

VCC[062]

AB12

VCC[063]

AB14

VCC[064]

AB15

VCC[065]

AB17

VCC[066]

AB18

VCC[067]

TYCO_1-1674770-2_Merom~D

2

AB20

VCC[068]

AB7

VCC[069]

AC7

VCC[070]

AC9

VCC[071]

AC12

VCC[072]

AC13

VCC[073]

AC15

VCC[074]

AC17

VCC[075]

AC18

VCC[076]

AD7

VCC[077]

AD9

VCC[078]

AD10

VCC[079]

AD12

VCC[080]

AD14

VCC[081]

AD15

VCC[082]

AD17

VCC[083]

AD18

VCC[084]

AE9

VCC[085]

AE10

VCC[086]

AE12

VCC[087]

AE13

VCC[088]

AE15

VCC[089]

AE17

VCC[090]

AE18

VCC[091]

AE20

VCC[092]

AF9

VCC[093]

AF10

VCC[094]

AF12

VCC[095]

AF14

VCC[096]

AF15

VCC[097]

AF17

VCC[098]

AF18

VCC[099]

AF20

VCC[100]

G21

VCCP[01]
VCCP[02]
VCCP[03]
VCCP[04]
VCCP[05]
VCCP[06]
VCCP[07]
VCCP[08]
VCCP[09]
VCCP[10]
VCCP[11]
VCCP[12]
VCCP[13]
VCCP[14]
VCCP[15]
VCCP[16]

VCCA[1]
VCCA[2]

VID[0]
VID[1]
VID[2]
VID[3]
VID[4]
VID[5]
VID[6]

VCCSENSE

VSSSENSE

V6
J6
K6
M6
J21
K21
M21
N21
N6
R21
R6
T21
T6
V21
W21

B26
C26

AD6
AF5
AE5
AF4
AE3
AF3
AE2

AF7

AE7

VCCSENSE

VSSSENSE

VID0
VID1
VID2
VID3
VID4
VID5
VID6

220U_D2_4VY_R15M~D

1

C487

+

2

Length match within 25 mils, Z0=27.4 ohm

Place R342 and R343 near CPU

+VCC_CORE

R342

R343

VCCSENSE

VSSSENSE

1 2

100_0402_1%~D

1 2

100_0402_1%~D

Route VCCSENSE and VSSSENSE trace at

27.4 ohms, 7 mils spaci n g and 1 inch (max)

DELL CONFIDENTIAL/PROPRIETARY

Title

Size Document Number Rev

Date: Sheet

+1.05V_VCCP

CRB was 270uF

10U_0805_10V4Z~D

0.01U_0402_16V7K~D

VID0 48
VID1 48
VID2 48
VID3 48
VID4 48
VID5 48
VID6 48

VCCSENSE 48

VSSSENSE 48

C488

1

2

Compal Electronics, Inc.

Merom Processor(2/2)
LA-3302P

1

+1.5V_RUN

C489

1

2

866Thursday, March 01, 2007

0.4

of

5

+VCC_CORE

Place these inside
socket cavity on L8
(North side
Secondary)

D D

Place these inside
socket cavity on L8
(Sorth side
Secondary)

Place these inside
socket cavity on L8
(North side
Primary)

Place these inside
socket cavity on L8
(Sorth side
Primary)

C C

1

2

+VCC_CORE

1

2

+VCC_CORE

1

2

+VCC_CORE

1

2

C329
10U_0805_4VAM~D

C222
10U_0805_4VAM~D

C363
10U_0805_4VAM~D

C364
10U_0805_4VAM~D

1

C330
10U_0805_4VAM~D

2

1

C223
10U_0805_4VAM~D

2

1

C64
10U_0805_4VAM~D

2

1

C50
10U_0805_4VAM~D

2

1

C331
10U_0805_4VAM~D

2

1

C224
10U_0805_4VAM~D

2

1

C65
10U_0805_4VAM~D

2

1

C51
10U_0805_4VAM~D

2

1

C332
10U_0805_4VAM~D

2

1

C225
10U_0805_4VAM~D

2

1

C66
10U_0805_4VAM~D

2

1

C52
10U_0805_4VAM~D

2

4

1

2

1

2

1

2

1

2

C333
10U_0805_4VAM~D

C227
10U_0805_4VAM~D

C67
10U_0805_4VAM~D

C53
10U_0805_4VAM~D

1

C334
10U_0805_4VAM~D

2

1

C226
10U_0805_4VAM~D

2

1

C68
10U_0805_4VAM~D

2

1

C54
10U_0805_4VAM~D

2

1

C335
10U_0805_4VAM~D

2

1

C228
10U_0805_4VAM~D

2

10uF 0805 X6S -> 85 degree C

3

1

C336
10U_0805_4VAM~D

2

1

C229
10U_0805_4VAM~D

2

1

C55
10U_0805_4VAM~D

2

1

C69
10U_0805_4VAM~D

2

1

C190
10U_0805_4VAM~D

2

1

C185
10U_0805_4VAM~D

2

2

1

High Frequence Decoupling

Near VCORE regulator.

+VCC_CORE +VCC_CORE

South Side Secondary

C177

B B

220U_X_2VM_R7M~D

1

1

+

+

C179

C178

2

2

@

220U_X_2VM_R7M~D

220U_X_2VM_R7M~D

1

1

+

+

C338

C366

2

2

@

220U_X_2VM_R7M~D

220U_X_2VM_R7M~D

1

+

2

North Side Secondary

1

+

C365

2

220U_X_2VM_R7M~D

ESR <= 1.5m ohm
Capacitor > 1980uF

1

C870

0.1U_0402_10V7K~D

2

@

1

C871

0.1U_0402_10V7K~D

2

@

1

C872

0.1U_0402_10V7K~D

2

@

1

C873

0.1U_0402_10V7K~D

2

@

BITs WI97837

+1.05V_VCCP

1

C312

0.1U_0402_10V7K~D

2

A A

1

C256

0.1U_0402_10V7K~D

2

1

C293

0.1U_0402_10V7K~D

2

1

C250

0.1U_0402_10V7K~D

2

1

C310

0.1U_0402_10V7K~D

2

1

C264

0.1U_0402_10V7K~D

2

Place these inside
socket cavity on L8
(North side
Secondary)

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

CPU Bypass

LA-3302P

966Monday, February 26, 2007

1

0.4

of

5

54.9_0402_1%~D

+1.05V_VCCP

12

R347

24.9_0402_1%~D

H_D#[0..63]8

12

R348

54.9_0402_1%~D

R350

H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63

H_SWNG
H_RCOMP

H_SCOMP
H_SCOMP#

H_RESET#7

H_CPUSLP#8

12

5

H_RESET#

H_CPUSLP#

H_VREF

H_VREF

2K_0402_1%~D

U29A

E2

H_D#_0

G2

H_D#_1

G7

H_D#_2

M6

H_D#_3

H7

H_D#_4

H3

H_D#_5

G4

H_D#_6

F3

H_D#_7

N8

H_D#_8

H2

H_D#_9

M10

H_D#_10

N12

H_D#_11

N9

H_D#_12

H5

H_D#_13

P13

H_D#_14

K9

H_D#_15

M2

H_D#_16

W10

H_D#_17

Y8

H_D#_18

V4

H_D#_19

M3

H_D#_20

J1

H_D#_21

N5

H_D#_22

N3

H_D#_23

W6

H_D#_24

W9

H_D#_25

N2

H_D#_26

Y7

H_D#_27

Y9

H_D#_28

P4

H_D#_29

W3

H_D#_30

N1

H_D#_31

AD12

H_D#_32

AE3

H_D#_33

AD9

H_D#_34

AC9

H_D#_35

AC7

H_D#_36

AC14

H_D#_37

AD11

H_D#_38

AC11

H_D#_39

AB2

H_D#_40

AD7

H_D#_41

AB1

H_D#_42

Y3

H_D#_43

AC6

H_D#_44

AE2

H_D#_45

AC5

H_D#_46

AG3

H_D#_47

AJ9

H_D#_48

AH8

H_D#_49

AJ14

H_D#_50

AE9

H_D#_51

AE11

H_D#_52

AH12

H_D#_53

AJ5

H_D#_54

AH5

H_D#_55

AJ6

H_D#_56

AE7

H_D#_57

AJ7

H_D#_58

AJ2

H_D#_59

AE5

H_D#_60

AJ3

H_D#_61

AH2

H_D#_62

AH13

H_D#_63

B3

H_SWING

C2

H_RCOMP

W1

H_SCOMP

W2

H_SCOMP#

B6

H_CPURST#

E5

H_CPUSLP#

B9

H_AVREF

A9

H_DVREF

LE88CLPM A0 QM21_FCBGA1299~D

12

R355
1K_0402_1%~D

0.1U_0402_16V4Z~D

12

1

R361

2

H_A#_10
H_A#_11
H_A#_12
H_A#_13
H_A#_14
H_A#_15
H_A#_16
H_A#_17
H_A#_18
H_A#_19
H_A#_20
H_A#_21
H_A#_22
H_A#_23
H_A#_24
H_A#_25
H_A#_26
H_A#_27
H_A#_28
H_A#_29
H_A#_30
H_A#_31
H_A#_32
H_A#_33
H_A#_34
H_A#_35

H_ADSTB#_0
H_ADSTB#_1

H_BPRI#

HOST

H_BREQ#

H_DEFER#

H_DBSY#

HPLL_CLK

HPLL_CLK#

H_DPWR#

H_DRDY#

H_HITM#

H_LOCK#

H_TRDY#

H_DINV#_0
H_DINV#_1
H_DINV#_2
H_DINV#_3

H_DSTBN#_0
H_DSTBN#_1
H_DSTBN#_2
H_DSTBN#_3

H_DSTBP#_0
H_DSTBP#_1
H_DSTBP#_2
H_DSTBP#_3

H_REQ#_0
H_REQ#_1
H_REQ#_2
H_REQ#_3
H_REQ#_4

H_RS#_0
H_RS#_1
H_RS#_2

+1.05V_VCCP+1.05V_VCCP

H_SWNG

100_0402_1%~D

C496

R362

D D

C C

B B

Layout Note:
H_RCOMP tr ace width
and spacing is 10/20

A A

H_A#_3
H_A#_4
H_A#_5
H_A#_6
H_A#_7
H_A#_8
H_A#_9

H_ADS#

H_BNR#

H_HIT#

12

R356
221_0402_1%~D

12

4

H_A#3

J13

H_A#4

B11

H_A#5

C11

H_A#6

M11

H_A#7

C15

H_A#8

F16

H_A#9

L13

H_A#10

G17

H_A#11

C14

H_A#12

K16

H_A#13

B13

H_A#14

L16

H_A#15

J17

H_A#16

B14

H_A#17

K19

H_A#18

P15

H_A#19

R17

H_A#20

B16

H_A#21

H20

H_A#22

L19

H_A#23

D17

H_A#24

M17

H_A#25

N16

H_A#26

J19

H_A#27

B18

H_A#28

E19

H_A#29

B17

H_A#30

B15

H_A#31

E17

H_A#32

C18

H_A#33

A19

H_A#34

B19

H_A#35

N19

H_ADS#

G12

H_ADSTB#0

H17

H_ADSTB#1

G20

H_BNR#

C8

H_BPRI#

E8

H_BR0#

F12

H_DEFER#

D6

H_DBSY#

C10

CLK_MCH_BCLK

AM5

CLK_MCH_BCLK#

AM7

H_DPWR#

H8

H_DRDY#

K7

H_HIT#

E4

H_HITM#

C6

H_LOCK#

G10

H_TRDY#

B7

H_DINV#0

K5

H_DINV#1

L2

H_DINV#2

AD13

H_DINV#3

AE13

H_DSTBN#0

M7

H_DSTBN#1

K3

H_DSTBN#2

AD2

H_DSTBN#3

AH11

H_DSTBP#0

L7

H_DSTBP#1

K2

H_DSTBP#2

AC2

H_DSTBP#3

AJ10

H_REQ#0

M14

H_REQ#1

E13

H_REQ#2

A11

H_REQ#3

H13

H_REQ#4

B12

H_RS#0

E12

H_RS#1

D7

H_RS#2

D8

+1.8V_SUS

R359

3.01K_0402_1%~D

0.1U_0402_16V4Z~D

1

C497

2

4

1K_0402_1%~D

R363

H_A#[3..35] 7

H_ADS# 7

H_ADSTB#0 7

H_ADSTB#1 7
H_BNR# 7
H_BPRI# 7
H_BR0# 7
H_DEFER# 7
H_DBSY# 7

CLK_MCH_BCLK 6

CLK_MCH_BCLK# 6
H_DPWR# 8
H_DRDY# 7

H_HIT# 7
H_HITM# 7
H_LOCK# 7

H_TRDY# 7

H_DINV#0 8
H_DINV#1 8
H_DINV#2 8
H_DINV#3 8

H_DSTBN#0 8
H_DSTBN#1 8
H_DSTBN#2 8
H_DSTBN#3 8

H_DSTBP#0 8
H_DSTBP#1 8
H_DSTBP#2 8
H_DSTBP#3 8

H_REQ#0 7
H_REQ#1 7
H_REQ#2 7
H_REQ#3 7
H_REQ#4 7

H_RS#0 7

H_RS#1 7

H_RS#2 7

12

R353
1K_0402_1%~D

SMRCOMP_VOH

1

12

12

C494

2

SMRCOMP_VOL

1

C498

2

+1.8V_SUS

V_DDR_MCH_REF

1K_0402_1%~D

392_0402_1~D

1

C495

2

2.2U_0603_6.3V6K~D

0.01U_0402_16V7K~D

1

C499

2

2.2U_0603_6.3V6K~D

0.01U_0402_16V7K~D

C491

+1.25V_RUN

R349

R351

3

M_ODT016
M_ODT116
M_ODT217
M_ODT317

T42PAD~D
T43PAD~D
T44PAD~D
T45PAD~D

T46PAD~D

M_CLK_DDR0
M_CLK_DDR1
M_CLK_DDR2
M_CLK_DDR3

M_CLK_DDR#0
M_CLK_DDR#1
M_CLK_DDR#2
M_CLK_DDR#3

DDR_CKE0_DIMMA
DDR_CKE1_DIMMA
DDR_CKE2_DIMMB
DDR_CKE3_DIMMB

DDR_CS0_DIMMA#
DDR_CS1_DIMMA#
DDR_CS2_DIMMB#
DDR_CS3_DIMMB#

M_ODT0
M_ODT1
M_ODT2
M_ODT3

SMRCOMP
SMRCOMP#

SMRCOMP_VOH
SMRCOMP_VOL

V_DDR_MCH_REF

CLK_MCH_3GPLL
CLK_MCH_3GPLL#

DMI_MRX_ITX_N0
DMI_MRX_ITX_N1
DMI_MRX_ITX_N2
DMI_MRX_ITX_N3

DMI_MRX_ITX_P0
DMI_MRX_ITX_P1
DMI_MRX_ITX_P2
DMI_MRX_ITX_P3

DMI_MTX_IRX_N0
DMI_MTX_IRX_N1
DMI_MTX_IRX_N2
DMI_MTX_IRX_N3

DMI_MTX_IRX_P0
DMI_MTX_IRX_P1
DMI_MTX_IRX_P2
DMI_MTX_IRX_P3

CL_CLK0
CL_DATA0
ICH_CL_PWROK
CL_RST0#
CL_VREF

CLK_3GPLLREQ#
MCH_ICH_SYNC#

R774 0_0402_5%~D

R357

20K_0402_5%~D

M_CLK_DDR016
M_CLK_DDR116
M_CLK_DDR217
M_CLK_DDR317

M_CLK_DDR#016
M_CLK_DDR#116
M_CLK_DDR#217
M_CLK_DDR#317

DDR_CKE0_DIMMA16
DDR_CKE1_DIMMA16
DDR_CKE2_DIMMB17
DDR_CKE3_DIMMB17

DDR_CS0_DIMMA#16
DDR_CS1_DIMMA#16
DDR_CS2_DIMMB#17
DDR_CS3_DIMMB#17

R345

20_0402_1%~D

1 2
1 2

R346

20_0402_1%~D

1

1

C492

2

2

CLK_MCH_3GPLL6

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

12

12

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

1

C493

0.1U_0402_16V4Z~D

2

3

CLK_MCH_3GPLL#6

DMI_MRX_ITX_N023
DMI_MRX_ITX_N123
DMI_MRX_ITX_N223
DMI_MRX_ITX_N323

DMI_MRX_ITX_P023
DMI_MRX_ITX_P123
DMI_MRX_ITX_P223
DMI_MRX_ITX_P323

DMI_MTX_IRX_N023
DMI_MTX_IRX_N123
DMI_MTX_IRX_N223
DMI_MTX_IRX_N323

DMI_MTX_IRX_P023
DMI_MTX_IRX_P123
DMI_MTX_IRX_P223
DMI_MTX_IRX_P323

CL_CLK023
CL_DATA023

ICH_CL_PWROK23,39

CL_RST0#23

CLK_3GPLLREQ#6
MCH_ICH_SYNC#23

AV29

SM_CK_0

BB23

SM_CK_1

BA25

SM_CK_3

AV23

SM_CK_4

AW30

SM_CK#_0

BA23

SM_CK#_1

AW25

SM_CK#_3

AW23

SM_CK#_4

BE29

SM_CKE_0

AY32

SM_CKE_1

BD39

SM_CKE_3

BG37

SM_CKE_4

BG20

SM_CS#_0

BK16

SM_CS#_1

BG16

SM_CS#_2

BE13

SM_CS#_3

BH18

SM_ODT_0

BJ15

SM_ODT_1

BJ14

SM_ODT_2

BE16

SM_ODT_3

BL15

SM_RCOMP

BK14

SM_RCOMP#

BK31

SM_RCOMP_VOH

BL31

SM_RCOMP_VOL

AR49

SM_VREF_0

AW4

SM_VREF_1

B42

DPLL_REF_CLK

C42

DPLL_REF_CLK#

H48

DPLL_REF_SSCLK

H47

DPLL_REF_SSCLK#

K44

PEG_CLK

K45

PEG_CLK#

AN47

DMI_RXN_0

AJ38

DMI_RXN_1

AN42

DMI_RXN_2

AN46

DMI_RXN_3

AM47

DMI_RXP_0

AJ39

DMI_RXP_1

AN41

DMI_RXP_2

AN45

DMI_RXP_3

AJ46

DMI_TXN_0

AJ41

DMI_TXN_1

AM40

DMI_TXN_2

AM44

DMI_TXN_3

AJ47

DMI_TXP_0

AJ42

DMI_TXP_1

AM39

DMI_TXP_2

AM43

DMI_TXP_3

E35

GFX_VID_0

A39

GFX_VID_1

C38

GFX_VID_2

B39

GFX_VID_3

E36

GFX_VR_EN

AM49

CL_CLK

AK50

CL_DATA

AT43

CL_PWROK

AN49

CL_RST#

AM50

CL_VREF

H35

SDVO_CTRL_CLK

K36

SDVO_CTRL_DATA

G39

CLK_REQ#

G40

ICH_SYNC#

A37

12
12

TEST_1

R32

TEST_2

THERMTRIP_MCH#

2

R358

56_0402_5%~D

2

1 2

U29B

RSVD1
RSVD2
RSVD3
RSVD4
RSVD5
RSVD6
RSVD7
RSVD8

RSVD9
RSVD10
RSVD11
RSVD12
RSVD13
RSVD14

RSVD CFG PM NC

DDR MUXINGCLKDMIGRAPHICS VIDMEMISC

LE88CLPM A0 QM21_FCBGA1299~D

RSVD20
RSVD21
RSVD22
RSVD23
RSVD24
RSVD25
RSVD26
RSVD27
RSVD28
RSVD29
RSVD30
RSVD31
RSVD32
RSVD33
RSVD34
RSVD35
RSVD36
RSVD37
RSVD38
RSVD39
RSVD40
RSVD41
RSVD42
RSVD43

CFG_10
CFG_11
CFG_12
CFG_13
CFG_14
CFG_15
CFG_16
CFG_17
CFG_18
CFG_19
CFG_20

PM_BM_BUSY#

PM_DPRSTP#
PM_EXT_TS#_0
PM_EXT_TS#_1

PWROK

THERMTRIP#

DPRSLPVR

+1.05V_VCCP

CFG_0
CFG_1
CFG_2
CFG_3
CFG_4
CFG_5
CFG_6
CFG_7
CFG_8
CFG_9

RSTIN#

NC_1
NC_2
NC_3
NC_4
NC_5
NC_6
NC_7
NC_8

NC_9
NC_10
NC_11
NC_12
NC_13
NC_14
NC_15
NC_16

1

P36
P37
R35
N35
AR12
AR13
AM12
AN13
J12
AR37
AM36
AL36
AM37
D20

H10
B51
BJ20
BK22
BF19
BH20
BK18
BJ18
BF23
BG23
BC23
BD24
BH39
AW20
BK20
C48
D47
B44
C44
A35
B37
B36
B34
C34

P27
N27
N24
C21
C23
F23
N23
G23
J20
C20
R24
L23
J23
E23
E20
K23
M20
M24
L32
N33
L35

G41
L39
L36
J36
AW49
AV20
N20
G36

BJ51
BK51
BK50
BL50
BL49
BL3
BL2
BK1
BJ1
E1
A5
C51
B50
A50
A49
BK2

100_0402_5%~D

CFG5

CFG9

CFG16

CFG19
CFG20

PM_BMBUSY#
H_DPRSTP#
PM_EXTTS#0
PM_EXTTS#1
ICH_PWRGD
PLTRST1#_R
THERMTRIP_MCH#
DPRSLPVR

R36

1 2

T63 PAD~D
T64 PAD~D

T65 PAD~D
T66 PAD~D
T67 PAD~D

T68 PAD~D
T69 PAD~D
T70 PAD~D
T71 PAD~D
T72 PAD~D
T73 PAD~D

T74 PAD~D
T75 PAD~D

0_0402_5%~D@

0_0402_5%~D

CPU_MCH_BSEL0 6,8
CPU_MCH_BSEL1 6,8
CPU_MCH_BSEL2 6,8

CFG5 12

CFG9 12

CFG16 12

CFG19 12
CFG20 12

PM_BMBUSY# 23
H_DPRSTP# 8,22,48

PM_EXTTS#0 16
PM_EXTTS#1 17

ICH_PWRGD 23,42

THERMTRIP_MCH# 18

DPRSLPVR 23,48

PM_EXTTS#0

PM_EXTTS#1

R589

12

R583

PLTRST1#PLTRST1#_R

12

+3.3V_RUN

R352

10K_0402_5%~D

12

R354

10K_0402_5%~D

12

SB_NB_PCIE_RST# 21

PLTRST1# 21

DELL CONFIDENTIAL/PROPRIETARY

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

Crestline(1 of 6)

LA-3302P

10 66Thursday, March 01, 2007

1

of

0.4

5

D D

4

3

2

1

DDR_A_BS016
DDR_A_BS116
DDR_A_BS216

DDR_A_DM[0..7]16

DDR_A_DQS[0..7]16

C C

DDR_A_DQS#[0..7]16

DDR_A_MA[0..14]16

B B

DDR_A_CAS#16
DDR_A_RAS#16
DDR_A_WE#16

DDR_A_BS0
DDR_A_BS1
DDR_A_BS2

DDR_A_DM0
DDR_A_DM1
DDR_A_DM2
DDR_A_DM3
DDR_A_DM4
DDR_A_DM5
DDR_A_DM6
DDR_A_DM7

DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7

DDR_A_DQS#0
DDR_A_DQS#1
DDR_A_DQS#2
DDR_A_DQS#3

DDR_A_DQS#4

DDR_A_DQS#5
DDR_A_DQS#6

DDR_A_DQS#7

DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA14 DDR_B_MA14

DDR_A_CAS#
DDR_A_RAS#

DDR_A_WE#

T10

BB19
BK19
BF29

AT45
BD44

BD42
AW38
AW13

AT46

BE48

BB43

BC37

BB16

AT47

BD47

BC41

BA37

BA16

BJ19
BD20
BK27
BH28

BL24
BK28

BJ27

BJ25

BL28
BA28
BC19
BE28
BG30

BJ16

BJ29

BL17
BE18
BA19

AY20

BG8
AY5
AN6

BH6
BB2
AP3

BH7
BC1
AP2

SA_BS_0
SA_BS_1
SA_BS_2

SA_DM_0
SA_DM_1
SA_DM_2
SA_DM_3
SA_DM_4
SA_DM_5
SA_DM_6
SA_DM_7

SA_DQS_0
SA_DQS_1
SA_DQS_2
SA_DQS_3
SA_DQS_4
SA_DQS_5
SA_DQS_6
SA_DQS_7

SA_DQS#_0
SA_DQS#_1
SA_DQS#_2
SA_DQS#_3
SA_DQS#_4
SA_DQS#_5
SA_DQS#_6
SA_DQS#_7

SA_MA_0
SA_MA_1
SA_MA_2
SA_MA_3
SA_MA_4
SA_MA_5
SA_MA_6
SA_MA_7
SA_MA_8
SA_MA_9
SA_MA_10
SA_MA_11
SA_MA_12
SA_MA_13
SA_MA_14

SA_CAS#
SA_RAS#
SA_WE#

SA_RCVEN#

DDR SYSTEM MEMORY A

LE88CLPM A0 QM21_FCBGA1299~D

U29D

SA_DQ_0
SA_DQ_1
SA_DQ_2
SA_DQ_3
SA_DQ_4
SA_DQ_5
SA_DQ_6
SA_DQ_7
SA_DQ_8

SA_DQ_9
SA_DQ_10
SA_DQ_11
SA_DQ_12
SA_DQ_13
SA_DQ_14
SA_DQ_15
SA_DQ_16
SA_DQ_17
SA_DQ_18
SA_DQ_19
SA_DQ_20
SA_DQ_21
SA_DQ_22
SA_DQ_23
SA_DQ_24
SA_DQ_25
SA_DQ_26
SA_DQ_27
SA_DQ_28
SA_DQ_29
SA_DQ_30
SA_DQ_31
SA_DQ_32
SA_DQ_33
SA_DQ_34
SA_DQ_35
SA_DQ_36
SA_DQ_37
SA_DQ_38
SA_DQ_39
SA_DQ_40
SA_DQ_41
SA_DQ_42
SA_DQ_43
SA_DQ_44
SA_DQ_45
SA_DQ_46
SA_DQ_47
SA_DQ_48
SA_DQ_49
SA_DQ_50
SA_DQ_51
SA_DQ_52
SA_DQ_53
SA_DQ_54
SA_DQ_55
SA_DQ_56
SA_DQ_57
SA_DQ_58
SA_DQ_59
SA_DQ_60
SA_DQ_61
SA_DQ_62
SA_DQ_63

DDR_A_D0

AR43

DDR_A_D1 DDR_B_BS1

AW44

DDR_A_D2

BA45

DDR_A_D3

AY46

DDR_A_D4

AR41

DDR_A_D5

AR45

DDR_A_D6

AT42

DDR_A_D7

AW47

DDR_A_D8

BB45

DDR_A_D9

BF48

DDR_A_D10

BG47

DDR_A_D11

BJ45

DDR_A_D12

BB47

DDR_A_D13

BG50

DDR_A_D14

BH49

DDR_A_D15

BE45

DDR_A_D16

AW43

DDR_A_D17

BE44

DDR_A_D18

BG42

DDR_A_D19

BE40

DDR_A_D20

BF44

DDR_A_D21

BH45

DDR_A_D22

BG40

DDR_A_D23

BF40

DDR_A_D24

AR40

DDR_A_D25

AW40

DDR_A_D26

AT39

DDR_A_D27

AW36

DDR_A_D28

AW41

DDR_A_D29

AY41

DDR_A_D30

AV38

DDR_A_D31

AT38

DDR_A_D32

AV13

DDR_A_D33

AT13

DDR_A_D34

AW11

DDR_A_D35

AV11

DDR_A_D36

AU15

DDR_A_D37

AT11

DDR_A_D38

BA13

DDR_A_D39

BA11

DDR_A_D40

BE10

DDR_A_D41

BD10

DDR_A_D42

BD8

DDR_A_D43

AY9

DDR_A_D44

BG10

DDR_A_D45

AW9

DDR_A_D46

BD7

DDR_A_D47

BB9

DDR_A_D48

BB5

DDR_A_D49

AY7

DDR_A_D50

AT5

DDR_A_D51

AT7

DDR_A_D52

AY6

DDR_A_D53

BB7

DDR_A_D54

AR5

DDR_A_D55

AR8

DDR_A_D56

AR9

DDR_A_D57

AN3

DDR_A_D58

AM8

DDR_A_D59

AN10

DDR_A_D60

AT9

DDR_A_D61

AN9

DDR_A_D62

AM9

DDR_A_D63

AN11

DDR_B_BS017
DDR_B_BS117
DDR_B_BS217

DDR_B_DM[0..7]17

DDR_B_DQS[0..7]17

DDR_B_DQS#[0..7]17

DDR_B_MA[0..14]17

DDR_B_CAS#17
DDR_B_RAS#17
DDR_B_WE#17

T11

DDR_B_BS0
DDR_B_BS2

DDR_B_DM0
DDR_B_DM1
DDR_B_DM2
DDR_B_DM3
DDR_B_DM4
DDR_B_DM5
DDR_B_DM6
DDR_B_DM7

DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4
DDR_B_DQS5
DDR_B_DQS6
DDR_B_DQS7

DDR_B_DQS#0
DDR_B_DQS#1
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS#4
DDR_B_DQS#5
DDR_B_DQS#6
DDR_B_DQS#7

DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13

DDR_B_CAS#
DDR_B_RAS#
DDR_B_WE#

SB_RCVEN#SA_RCVEN#

AY17
BG18
BG36

AR50
BD49
BK45

BL39

BH12

AW2

AT50
BD50
BK46
BK39

BJ12

AU50
BC50

BL45
BK38
BK12

BC18
BG28
BG25

AW17

BF25
BE25
BA29
BC28
AY28
BD37
BG17
BE37
BA39
BG13
BE24

BE17
AV16
BC17

AY18

BJ7
BF3

BL7
BE2
AV2

BK7
BF2
AV3

SB_BS_0
SB_BS_1
SB_BS_2

SB_DM_0
SB_DM_1
SB_DM_2
SB_DM_3
SB_DM_4
SB_DM_5
SB_DM_6
SB_DM_7

SB_DQS_0
SB_DQS_1
SB_DQS_2
SB_DQS_3
SB_DQS_4
SB_DQS_5
SB_DQS_6
SB_DQS_7

SB_DQS#_0
SB_DQS#_1
SB_DQS#_2
SB_DQS#_3
SB_DQS#_4
SB_DQS#_5
SB_DQS#_6
SB_DQS#_7

SB_MA_0
SB_MA_1
SB_MA_2
SB_MA_3
SB_MA_4
SB_MA_5
SB_MA_6
SB_MA_7
SB_MA_8
SB_MA_9
SB_MA_10
SB_MA_11
SB_MA_12
SB_MA_13
SB_MA_14

SB_CAS#
SB_RAS#
SB_WE#

SB_RCVEN#

DDR SYSTEM MEMORY B

LE88CLPM A0 QM21_FCBGA1299~D

U29E

SB_DQ_0
SB_DQ_1
SB_DQ_2
SB_DQ_3
SB_DQ_4
SB_DQ_5
SB_DQ_6
SB_DQ_7
SB_DQ_8

SB_DQ_9
SB_DQ_10
SB_DQ_11
SB_DQ_12
SB_DQ_13
SB_DQ_14
SB_DQ_15
SB_DQ_16
SB_DQ_17
SB_DQ_18
SB_DQ_19
SB_DQ_20
SB_DQ_21
SB_DQ_22
SB_DQ_23
SB_DQ_24
SB_DQ_25
SB_DQ_26
SB_DQ_27
SB_DQ_28
SB_DQ_29
SB_DQ_30
SB_DQ_31
SB_DQ_32
SB_DQ_33
SB_DQ_34
SB_DQ_35
SB_DQ_36
SB_DQ_37
SB_DQ_38
SB_DQ_39
SB_DQ_40
SB_DQ_41
SB_DQ_42
SB_DQ_43
SB_DQ_44
SB_DQ_45
SB_DQ_46
SB_DQ_47
SB_DQ_48
SB_DQ_49
SB_DQ_50
SB_DQ_51
SB_DQ_52
SB_DQ_53
SB_DQ_54
SB_DQ_55
SB_DQ_56
SB_DQ_57
SB_DQ_58
SB_DQ_59
SB_DQ_60
SB_DQ_61
SB_DQ_62
SB_DQ_63

AP49
AR51
AW50
AW51
AN51
AN50
AV50
AV49
BA50
BB50
BA49
BE50
BA51
AY49
BF50
BF49
BJ50
BJ44
BJ43
BL43
BK47
BK49
BK43
BK42
BJ41
BL41
BJ37
BJ36
BK41
BJ40
BL35
BK37
BK13
BE11
BK11
BC11
BC13
BE12
BC12
BG12
BJ10
BL9
BK5
BL5
BK9
BK10
BJ8
BJ6
BF4
BH5
BG1
BC2
BK3
BE4
BD3
BJ2
BA3
BB3
AR1
AT3
AY2
AY3
AU2
AT2

DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63

DDR_B_D[0..63] 17DDR_A_D[0..63] 16

A A

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

Crestline(2 of 6)

LA-3302P

11 66Thursday, March 01, 2007

1

0.4

of

5

4

+VCC_PEG

3

2

1

R366

U29C

J40

L_BKLT_CTRL

H39

L_BKLT_EN

E39

D D

C C

B B

A A

5

E40
C37
D35

K40

L41

L43
N41
N40

D46
C45
D44

E42
G51

E51

F49

G50

E50

F48

G44

B47

B45

E44

A47

A45

E27
G27

K27

F27

J27

L27
M35

P33

H32
G32

K29

J29

F29

E29

K33
G35

F33

E33
C32

L_CTRL_CLK
L_CTRL_DATA
L_DDC_CLK
L_DDC_DATA
L_VDD_EN

LVDS_IBG
LVDS_VBG
LVDS_VREFH
LVDS_VREFL

LVDSA_CLK#
LVDSA_CLK
LVDSB_CLK#
LVDSB_CLK

LVDSA_DATA#_0
LVDSA_DATA#_1
LVDSA_DATA#_2

LVDSA_DATA_0
LVDSA_DATA_1
LVDSA_DATA_2

LVDSB_DATA#_0
LVDSB_DATA#_1
LVDSB_DATA#_2

LVDSB_DATA_0
LVDSB_DATA_1
LVDSB_DATA_2

TVA_DAC
TVB_DAC
TVC_DAC

TVA_RTN
TVB_RTN
TVC_RTN

TV_DCONSEL_0
TV_DCONSEL_1

CRT_BLUE
CRT_BLUE#
CRT_GREEN
CRT_GREEN#
CRT_RED
CRT_RED#

CRT_DDC_CLK
CRT_DDC_DATA
CRT_HSYNC
CRT_VSYNC

CRT_TVO_IREF

LVDS TV VGA

LE88CLPM A0 QM21_FCBGA1299~D

PEG_COMPI

PEG_COMPO

PEG_RX#_0
PEG_RX#_1
PEG_RX#_2
PEG_RX#_3
PEG_RX#_4
PEG_RX#_5
PEG_RX#_6
PEG_RX#_7
PEG_RX#_8

PEG_RX#_9
PEG_RX#_10
PEG_RX#_11
PEG_RX#_12
PEG_RX#_13
PEG_RX#_14
PEG_RX#_15

PEG_RX_0
PEG_RX_1
PEG_RX_2
PEG_RX_3
PEG_RX_4
PEG_RX_5
PEG_RX_6
PEG_RX_7
PEG_RX_8

PEG_RX_9
PEG_RX_10
PEG_RX_11
PEG_RX_12
PEG_RX_13
PEG_RX_14
PEG_RX_15

PEG_TX#_0
PEG_TX#_1
PEG_TX#_2
PEG_TX#_3
PEG_TX#_4
PEG_TX#_5
PEG_TX#_6
PEG_TX#_7

PCI-EXPRESS GRAPHICS

PEG_TX#_8
PEG_TX#_9

PEG_TX#_10
PEG_TX#_11
PEG_TX#_12
PEG_TX#_13
PEG_TX#_14
PEG_TX#_15

PEG_TX_0

PEG_TX_1

PEG_TX_2

PEG_TX_3

PEG_TX_4

PEG_TX_5

PEG_TX_6

PEG_TX_7

PEG_TX_8

PEG_TX_9
PEG_TX_10
PEG_TX_11
PEG_TX_12
PEG_TX_13
PEG_TX_14
PEG_TX_15

4

PEGCOMP

N43
M43

J51
L51
N47
T45
T50
U40
Y44
Y40
AB51
W49
AD44
AD40
AG46
AH49
AG45
AG41

J50
L50
M47
U44
T49
T41
W45
W41
AB50
Y48
AC45
AC41
AH47
AG49
AH45
AG42

N45
U39
U47
N51
R50
T42
Y43
W46
W38
AD39
AC46
AC49
AC42
AH39
AE49
AH44

M45
T38
T46
N50
R51
U43
W42
Y47
Y39
AC38
AD47
AC50
AD43
AG39
AE50
AH43

24.9_0402_1%~D

1 2

PEG_MRX_GTX_N0
PEG_MRX_GTX_N1
PEG_MRX_GTX_N2
PEG_MRX_GTX_N3
PEG_MRX_GTX_N4
PEG_MRX_GTX_N5
PEG_MRX_GTX_N6
PEG_MRX_GTX_N7
PEG_MRX_GTX_N8
PEG_MRX_GTX_N9
PEG_MRX_GTX_N10
PEG_MRX_GTX_N11
PEG_MRX_GTX_N12
PEG_MRX_GTX_N13
PEG_MRX_GTX_N14
PEG_MRX_GTX_N15

PEG_MRX_GTX_P0
PEG_MRX_GTX_P1
PEG_MRX_GTX_P2
PEG_MRX_GTX_P3
PEG_MRX_GTX_P4
PEG_MRX_GTX_P5
PEG_MRX_GTX_P6
PEG_MRX_GTX_P7
PEG_MRX_GTX_P8
PEG_MRX_GTX_P9
PEG_MRX_GTX_P10
PEG_MRX_GTX_P11
PEG_MRX_GTX_P12
PEG_MRX_GTX_P13
PEG_MRX_GTX_P14
PEG_MRX_GTX_P15

PEG_MTX_GRX_C_N0
PEG_MTX_GRX_C_N1
PEG_MTX_GRX_C_N2
PEG_MTX_GRX_C_N3
PEG_MTX_GRX_C_N4
PEG_MTX_GRX_C_N5
PEG_MTX_GRX_C_N6
PEG_MTX_GRX_C_N7
PEG_MTX_GRX_C_N8
PEG_MTX_GRX_C_N9
PEG_MTX_GRX_C_N10
PEG_MTX_GRX_C_N11
PEG_MTX_GRX_C_N12
PEG_MTX_GRX_C_N13
PEG_MTX_GRX_C_N14
PEG_MTX_GRX_C_N15

PEG_MTX_GRX_C_P0
PEG_MTX_GRX_C_P1
PEG_MTX_GRX_C_P2
PEG_MTX_GRX_C_P3
PEG_MTX_GRX_C_P4
PEG_MTX_GRX_C_P5
PEG_MTX_GRX_C_P6
PEG_MTX_GRX_C_P7
PEG_MTX_GRX_C_P8
PEG_MTX_GRX_C_P9
PEG_MTX_GRX_C_P10
PEG_MTX_GRX_C_P11
PEG_MTX_GRX_C_P12
PEG_MTX_GRX_C_P13
PEG_MTX_GRX_C_P14
PEG_MTX_GRX_C_P15

CFG5 DMI X2 Select

PEG_MRX_GTX_N[0..15] 52

CFG16

CFG19

PEG_MRX_GTX_P[0..15] 52

CFG20

SDVO_CRTL_DATA

PEG_MTX_GRX_P[0..15]
PEG_MTX_GRX_N[0..15]

PEG_MTX_GRX_C_P0
PEG_MTX_GRX_C_N0

PEG_MTX_GRX_C_P1
PEG_MTX_GRX_C_N1

PEG_MTX_GRX_C_P2

PEG_MTX_GRX_C_P3
PEG_MTX_GRX_C_N3

PEG_MTX_GRX_C_P4 PEG_MTX_GRX_P4
PEG_MTX_GRX_C_N4

PEG_MTX_GRX_C_P5
PEG_MTX_GRX_C_N5

PEG_MTX_GRX_C_P6
PEG_MTX_GRX_C_N6

PEG_MTX_GRX_C_P7
PEG_MTX_GRX_C_N7

PEG_MTX_GRX_C_P8
PEG_MTX_GRX_C_N8

PEG_MTX_GRX_C_P9
PEG_MTX_GRX_C_N9

PEG_MTX_GRX_C_P10
PEG_MTX_GRX_C_N10

PEG_MTX_GRX_C_P11
PEG_MTX_GRX_C_N11

PEG_MTX_GRX_C_P12
PEG_MTX_GRX_C_N12

PEG_MTX_GRX_C_P13
PEG_MTX_GRX_C_N13

PEG_MTX_GRX_C_P14
PEG_MTX_GRX_C_N14

PEG_MTX_GRX_C_P15
PEG_MTX_GRX_C_N15

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

PEG_MTX_GRX_P[0..15] 52
PEG_MTX_GRX_N[0..15] 52

3

C500 0.1U_0402_10V7K~D

1 2

C501 0.1U_0402_10V7K~D

C502 0.1U_0402_10V7K~D

1 2

C504 0.1U_0402_10V7K~D

1 2

C506 0.1U_0402_10V7K~D

1 2

C508 0.1U_0402_10V7K~D

1 2

C510 0.1U_0402_10V7K~D

1 2

C512 0.1U_0402_10V7K~D

1 2

C514 0.1U_0402_10V7K~D

1 2

C516 0.1U_0402_10V7K~D

1 2

C518 0.1U_0402_10V7K~D

1 2

C520 0.1U_0402_10V7K~D

1 2

C522 0.1U_0402_10V7K~D

1 2

C524 0.1U_0402_10V7K~D

1 2

C526 0.1U_0402_10V7K~D

1 2

C528 0.1U_0402_10V7K~D

1 2

C530 0.1U_0402_10V7K~D

1 2

1 2

C503 0.1U_0402_10V7K~D

1 2

C505 0.1U_0402_10V7K~D

1 2

C507 0.1U_0402_10V7K~D

1 2

C509 0.1U_0402_10V7K~D

1 2

C511 0.1U_0402_10V7K~D

1 2

C513 0.1U_0402_10V7K~D

1 2

C515 0.1U_0402_10V7K~D

1 2

C517 0.1U_0402_10V7K~D

1 2

C519 0.1U_0402_10V7K~D

1 2

C521 0.1U_0402_10V7K~D

1 2

C523 0.1U_0402_10V7K~D

1 2

C525 0.1U_0402_10V7K~D

1 2

C527 0.1U_0402_10V7K~D

1 2

C529 0.1U_0402_10V7K~D

1 2

C531 0.1U_0402_10V7K~D

1 2

Strap Pin Table

PCI Express
Graphic Lane

FSB Dynamic

ODT

DMI Lane
Reversal

SDVO/PCIE
Concurrent
Operation

PEG_MTX_GRX_P0
PEG_MTX_GRX_N0

PEG_MTX_GRX_P1
PEG_MTX_GRX_N1

PEG_MTX_GRX_P2
PEG_MTX_GRX_N2PEG_MTX_GRX_C_N2

PEG_MTX_GRX_P3
PEG_MTX_GRX_N3

PEG_MTX_GRX_N4
PEG_MTX_GRX_P5

PEG_MTX_GRX_N5
PEG_MTX_GRX_P6

PEG_MTX_GRX_N6
PEG_MTX_GRX_P7

PEG_MTX_GRX_N7
PEG_MTX_GRX_P8

PEG_MTX_GRX_N8
PEG_MTX_GRX_P9

PEG_MTX_GRX_N9
PEG_MTX_GRX_P10

PEG_MTX_GRX_N10
PEG_MTX_GRX_P11

PEG_MTX_GRX_N11
PEG_MTX_GRX_P12

PEG_MTX_GRX_N12
PEG_MTX_GRX_P13

PEG_MTX_GRX_N13
PEG_MTX_GRX_P14

PEG_MTX_GRX_N14
PEG_MTX_GRX_P15

PEG_MTX_GRX_N15

Low = DMI x 2
High = DMI x 4 (Default)

Low = Reverse LaneCFG9
High = Normal O p e r a t i o n ( Default)

Low=Dynamic O D T Disable
High=Dynamic ODT Enable(default)

Low=Normal (default)
High=Lane Reversed

Low=Only SDVO or PCIEx1 is
operational (defaults)

High=SDVO and P C I E x 1 a r e o p e rating
simultaneously via PEG port

Low=No SDVO Device Present
(default)

High=SDVO Dev i ce Present

DELL CONFIDENTIAL/PROPRIETARY

Title

Size Document Number Rev

2

Date: Sheet

R365 4.02K_0402_1%~D@

CFG510

R368 4.02K_0402_1%~D@

CFG910

R372 4.02K_0402_1%~D@

CFG1610

CFG[3:17] have internal pullup

R373 4.02K_0402_1%~D@

CFG1910

R374 4.02K_0402_1%~D@

CFG2010

CFG[18:19] have internal pulldown

Compal Electronics, Inc.

Crestline(3 of 6)

LA-3302P

1 2

1 2

1 2

1 2

1 2

1

+3.3V_RUN

12 66Thursday, March 01, 2007

0.4

of

5

4

3

2

1

+1.05V_VCCP

CRB 270uF

220U_D2_4VY_R15M~D

1

C535

1

+

C537

2

2

D D

C C

B B

A A

+1.25V_RUN

+1.25V_RUN

+3.3V_RUN

4.7U_0603_6.3V6M~D

1

2

BLM18AG121SN1D_0603~D

1

2

0.1U_0402_16V4Z~D

1

2

C542

22U_0805_6.3V6M~D

C591

+VCC_RXR_DMI

0.47U_0402_10V4Z~D

2.2U_0603_6.3V6K~D

4.7U_0603_6.3V6M~D

C543

1

1

2

2

+1.25V_RUN_AXD

L33

12

1U_0603_10V4Z~D

C552

C551

1

2

+1.8V_SM_CK

1

2

0.1U_0402_16V4Z~D
C597

1

2

0.47U_0402_10V4Z~D
C577

C576

1

1

2

2

+1.25V_RUN

1U_0603_10V4Z~D

C589

Place caps close
to VCC_AXF (Pin
A21, B21, B23)

0.47U_0402_10V4Z~D

C544

+1.25V_RUN

+VCC_PEG

0.47U_0402_10V4Z~D
C578

1

2

5

10U_0805_4VAM~D

C590

AT23
AU28
AU24
AT29
AT25
AT30

AR29

AJ50

BK24
BK23

BJ24
BJ23

AD51

W50
W51

AH50
AH51

AH1

U13
U12
U11

T13
T11
T10

B23
B21
A21

A43

C40
B40

V49
V50

VTT_1
VTT_2
VTT_3

U9

VTT_4

U8

VTT_5

U7

VTT_6

U5

VTT_7

U3

VTT_8

U2

VTT_9

U1

VTT_10
VTT_11
VTT_12
VTT_13

T9

VTT_14

T7

VTT_15

T6

VTT_16

T5

VTT_17

T3

VTT_18

T2

VTT_19

R3

VTT_20

R2

VTT_21

R1

VTT_22

VCC_AXD_1
VCC_AXD_2
VCC_AXD_3
VCC_AXD_4
VCC_AXD_5
VCC_AXD_6

VCC_AXD_NCTF

VCC_AXF_1
VCC_AXF_2
VCC_AXF_3

VCC_DMI

VCC_SM_CK_1
VCC_SM_CK_2
VCC_SM_CK_3
VCC_SM_CK_4

VCC_TX_LVDS

VCC_HV_1
VCC_HV_2

VCC_PEG_1
VCC_PEG_2
VCC_PEG_3
VCC_PEG_4
VCC_PEG_5

VCC_RXR_DMI_1
VCC_RXR_DMI_2

A7

VTTLF1

F2

VTTLF2
VTTLF3

LE88CLPM A0 QM21_FCBGA1299~D

1

2

VTT

AXD

AXF

POWER

PEG

VTTLF

VCCA_CRT_DAC_1
VCCA_CRT_DAC_2

CRT

VCCA_DAC_BG
VSSA_DAC_BG

PLL

LVDS PEG

VCCA_PEG_BG
VSSA_PEG_BG

VCCA_PEG_PLL

SM

VCCA_SM_10
VCCA_SM_11

CLK

VCCA_SM_NCTF_1
VCCA_SM_NCTF_2

VCCA_SM_CK_1
VCCA_SM_CK_2

VCCA_TVA_DAC_1
VCCA_TVA_DAC_2

TV

VCCA_TVB_DAC_1
VCCA_TVB_DAC_2
VCCA_TVC_DAC_1
VCCA_TVC_DAC_2

TV/CRT

VCCD_TVDAC

DMI

VCCD_PEG_PLL

LVDS

VCCD_LVDS_1
VCCD_LVDS_2

+1.05V_VCCP

U29H

VCCSYNC

VCCA_DPLLA
VCCA_DPLLB

VCCA_HPLL

VCCA_MPLL

VCCA_LVDS
VSSA_LVDS

VCCA_SM_1
VCCA_SM_2
VCCA_SM_3
VCCA_SM_4
VCCA_SM_5
VCCA_SM_7
VCCA_SM_8
VCCA_SM_9

VCCD_CRT

VCCD_QDAC

VCCD_HPLL

2 1

D16

RB751V_SOD323~D

J32
A33

B33

A30
B32

B49
H49
AL2
AM2

A41
B41

K50
K49

U51

AW18
AV19
AU19
AU18
AU17
AT22
AT21
AT19
AT18
AT17
AR17
AR16

BC29
BB29

C25
B25
C27
B27
B28
A28

M32
L29

N28

AN2
U48

J41
H42

+1.25V_RUN_HPLL
+1.25V_RUN_MPLL

+VCCA_SM

+VCCA_SM_CK

1

2

1 2

R417

10_0603_5%~D

+1.25V_RUN_PEGPLL

4.7U_0603_6.3V6M~D

1U_0603_10V4Z~D

0.1U_0402_16V4Z~D

C563

+1.25V_RUN_PEGPLL

0.1U_0402_16V4Z~D

C554

BLM18AG121SN1D_0603~D

+3.3V_RUN

4

22U_0805_6.3V6M~D

C560

1

1

1U_0603_10V4Z~D

C594

C565

1

2

2

1

2

C642

L41

12

1

C561

2

1U_0603_10V4Z~D

C566

+1.25V_RUN

0.1U_0402_16V4Z~D

12

1

C559

2

2

22U_0805_6.3V6M~D

C564

1

1

2

2

+1.8V_SUS +1.8V_SM_CK

10U_0805_4VAM~D

+3.3V_RUN

1 2

22U_0805_6.3V6M~D

0_0805_5%~D

C562

1 2

1

2

1_0603_5%~D

12

0.1U_0402_16V4Z~D

1

C550

2

R406

R408

0_0603_5%~D

1

C582

2

10U_0805_4VAM~D

0.1U_0402_16V4Z~D

R416

+1.25V_RUN

1

+

2

1

2

C592

1

2

+VCC_PEG

1

1

+

2

2

+VCC_RXR_DMI

1

1

+

2

2

220U_D2_4VY_R15M~D

L35

BLM21PG221SN1D_0805~D

1 2

12

1_0402_5%~D

C549

R409

10U_0805_4VAM~D

C557

10U_0805_4VAM~D

220U_D2_4VY_R15M~D

C548

C556

C558

100U_D2E_6.3VM_R18M~D

+1.25V_RUN

C567

10U_0805_4VAM~D

0.1U_0402_16V4Z~D

+1.5V_RUN

C584

1

C583

2

0.022U_0402_16V7K~D

1

C593

2

22U_0805_6.3V6M~D

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

L32

BLM18PG181SN1_0603~D

BLM18PG181SN1_0603~D

0.1U_0402_16V4Z~D

12

L34

12

+1.25V_RUN_PEGPLL+1.25V_RUN

0.1U_0402_16V4Z~D

+1.25V_RUN_HPLL

C571

1

2

C568

1

2

+1.05V_VCCP

+1.05V_VCCP

BLM18AG121SN1D_0603~D

1

C572

2

22U_0805_6.3VAM~D

+1.25V_RUN

L37

12

1

C573

0.1U_0402_16V4Z~D

2

+1.25V_RUN_MPLL

45mA Max.45mA Max.

C574

0.1U_0402_16V4Z~D

1

2

BLM18AG121SN1D_0603~D

1

C575
22U_0805_6.3VAM~D

2

+1.25V_RUN

L38

12

DELL CONFIDENTIAL/PROPRIETARY

Title

Size Document Number Rev

2

Date: Sheet

Compal Electronics, Inc.

Crestline(4 of 6)

LA-3302P

13 66Monday, February 26, 2007

1

0.4

of

5

4

3

2

1

+1.05V_VCCP

+3.3V_RUN

+1.05V_VCCP

D D

22U_0805_6.3VAM~D

220U_D2_4VY_R15M~D

1

C602

+

2

Layout Note:
370 mils from edge

C C

Layout Note:
Inside GMCH cavity.

+1.05V_VCCP

22U_0805_6.3V6M~D

C615

1

2

B B

Layout Note: Place
close to GMCH edge.

0.1U_0402_10V7K~D

C618

1

2

0.22U_0402_10V4Z~D

C603

1

2

1

2

C604

1

1

2

2

0.22U_0402_10V4Z~D

0.1U_0402_10V7K~D

C613

C614

1

1

2

2

0.22U_0402_10V4Z~D

0.22U_0402_10V4Z~D
C617

C616

1

2

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

C619

C620

1

2

AB33
AB36
AB37
AC33
AC35
AC36
AD35
AD36
AF33
AF36
AH33
AH35
AH36
AH37

AJ33

AJ35
AK33
AK35
AK36
AK37
AD33

AJ36
AM35

AL33

AL35
AA33
AA35
AA36
AP35
AP36
AR35
AR36

AL24

AL26

AL28
AM26
AM28
AM29
AM31
AM32
AM33
AP29
AP31
AP32
AP33

AL29

AL31

AL32
AR31
AR32
AR33

Y32
Y33
Y35
Y36
Y37
T30
T34
T35
U29
U31
U32
U33
U35
U36
V32
V33
V36
V37

U29F

VCC_NCTF_1
VCC_NCTF_2
VCC_NCTF_3
VCC_NCTF_4
VCC_NCTF_5
VCC_NCTF_6
VCC_NCTF_7
VCC_NCTF_8
VCC_NCTF_9
VCC_NCTF_10
VCC_NCTF_11
VCC_NCTF_12
VCC_NCTF_13
VCC_NCTF_14
VCC_NCTF_15
VCC_NCTF_16
VCC_NCTF_17
VCC_NCTF_18
VCC_NCTF_19
VCC_NCTF_20
VCC_NCTF_21
VCC_NCTF_22
VCC_NCTF_23
VCC_NCTF_24
VCC_NCTF_25
VCC_NCTF_26
VCC_NCTF_27
VCC_NCTF_28
VCC_NCTF_29
VCC_NCTF_30
VCC_NCTF_31
VCC_NCTF_32
VCC_NCTF_33
VCC_NCTF_34
VCC_NCTF_35
VCC_NCTF_36
VCC_NCTF_37
VCC_NCTF_38
VCC_NCTF_39
VCC_NCTF_40
VCC_NCTF_41
VCC_NCTF_42
VCC_NCTF_43
VCC_NCTF_44
VCC_NCTF_45
VCC_NCTF_46
VCC_NCTF_47
VCC_NCTF_48
VCC_NCTF_49
VCC_NCTF_50

VCC_AXM_NCTF_1
VCC_AXM_NCTF_2
VCC_AXM_NCTF_3
VCC_AXM_NCTF_4
VCC_AXM_NCTF_5
VCC_AXM_NCTF_6
VCC_AXM_NCTF_7
VCC_AXM_NCTF_8
VCC_AXM_NCTF_9
VCC_AXM_NCTF_10
VCC_AXM_NCTF_11
VCC_AXM_NCTF_12
VCC_AXM_NCTF_13
VCC_AXM_NCTF_14
VCC_AXM_NCTF_15
VCC_AXM_NCTF_16
VCC_AXM_NCTF_17
VCC_AXM_NCTF_18
VCC_AXM_NCTF_19

POWER

LE88CLPM A0 QM21_FCBGA1299~D

VSS_NCTF_1
VSS_NCTF_2
VSS_NCTF_3
VSS_NCTF_4
VSS_NCTF_5
VSS_NCTF_6
VSS_NCTF_7
VSS_NCTF_8

VSS_NCTF_9
VSS_NCTF_10
VSS_NCTF_11
VSS_NCTF_12
VSS_NCTF_13
VSS_NCTF_14
VSS_NCTF_15
VSS_NCTF_16
VSS_NCTF_17
VSS_NCTF_18
VSS_NCTF_19
VSS_NCTF_20
VSS_NCTF_21

VSS_SCB1
VSS_SCB2
VSS_SCB3
VSS_SCB4
VSS_SCB5
VSS_SCB6

VCC_AXM_1
VCC_AXM_2
VCC_AXM_3
VCC_AXM_4
VCC_AXM_6
VCC_AXM_5
VCC_AXM_7

T27
T37
U24
U28
V31
V35
AA19
AB17
AB35
AD19
AD37
AF17
AF35
AK17
AM17
AM24
AP26
AP28
AR15
AR19
AR28

A3
B2
C1
BL1
BL51
A51

AT33
AT31
AK29
AK24
AK23
AJ26
AJ23

+1.05V_VCCP

R420

10_0603_5%~D

1 2

D17

2

1

3

BAT54CW_SOT323~D

+1.8V_SUS

0.1U_0402_10V7K~D

2

C608

1

Layout Note:
Place C901 where
LVDS and DDR2 taps.

330U_D2E_2.5VM~D

1

C605

+

2

Layout Note: Inside GMCH cavity.

+1.05V_VCCP

22U_0805_6.3V6M~D

22U_0805_6.3V6M~D

1

1

C606

C607

2

2

Layout Note:
Place on the edge

AT35
AT34
AH28
AC32
AC31
AK32

AJ31

AJ28
AH32
AH31
AH29
AF32

R30

AU32
AU33
AU35
AV33

AW33
AW35

AY35
BA32
BA33
BA35
BB33
BC32
BC33
BC35
BD32
BD35
BE32
BE33
BE35
BF33
BF34

BG32
BG33
BG35

BH32
BH34
BH35

BJ32

BJ33

BJ34
BK32
BK33
BK34
BK35

BL33
AU30

R20
W13

W14

AA20
AA23
AA26
AA28
AB21
AB24
AB29
AC20
AC21
AC23
AC24
AC26
AC28
AC29
AD20
AD23
AD24
AD28
AF21
AF26
AA31
AH20
AH21
AH23
AH24
AH26
AD31

AJ20
AN14

T14

Y12

U29G

VCC_1
VCC_2
VCC_3
VCC_4
VCC_5
VCC_6
VCC_7
VCC_8
VCC_9
VCC_10
VCC_11
VCC_12

VCC_13

VCC_SM_1
VCC_SM_2
VCC_SM_3
VCC_SM_4
VCC_SM_5
VCC_SM_6
VCC_SM_7
VCC_SM_8
VCC_SM_9
VCC_SM_10
VCC_SM_11
VCC_SM_12
VCC_SM_13
VCC_SM_14
VCC_SM_15
VCC_SM_16
VCC_SM_17
VCC_SM_18
VCC_SM_19
VCC_SM_20
VCC_SM_21
VCC_SM_22
VCC_SM_23
VCC_SM_24
VCC_SM_25
VCC_SM_26
VCC_SM_27
VCC_SM_28
VCC_SM_29
VCC_SM_30
VCC_SM_31
VCC_SM_32
VCC_SM_33
VCC_SM_34
VCC_SM_35
VCC_SM_36

VCC_AXG_1
VCC_AXG_2
VCC_AXG_3
VCC_AXG_4
VCC_AXG_5
VCC_AXG_6
VCC_AXG_7
VCC_AXG_8
VCC_AXG_9
VCC_AXG_10
VCC_AXG_11
VCC_AXG_12
VCC_AXG_13
VCC_AXG_14
VCC_AXG_15
VCC_AXG_16
VCC_AXG_17
VCC_AXG_18
VCC_AXG_19
VCC_AXG_20
VCC_AXG_21
VCC_AXG_22
VCC_AXG_23
VCC_AXG_24
VCC_AXG_25
VCC_AXG_26
VCC_AXG_27
VCC_AXG_28
VCC_AXG_29
VCC_AXG_30
VCC_AXG_31
VCC_AXG_32
VCC_AXG_33
VCC_AXG_34

VCC_AXG_NCTF_1
VCC_AXG_NCTF_2
VCC_AXG_NCTF_3

VCC CORE

POWER

VCC SM

VCC GFX

LE88CLPM A0 QM21_FCBGA1299~D

VCC_AXG_NCTF_4
VCC_AXG_NCTF_5
VCC_AXG_NCTF_6
VCC_AXG_NCTF_7
VCC_AXG_NCTF_8

VCC_AXG_NCTF_9
VCC_AXG_NCTF_10
VCC_AXG_NCTF_11
VCC_AXG_NCTF_12
VCC_AXG_NCTF_13
VCC_AXG_NCTF_14
VCC_AXG_NCTF_15
VCC_AXG_NCTF_16
VCC_AXG_NCTF_17
VCC_AXG_NCTF_18
VCC_AXG_NCTF_19
VCC_AXG_NCTF_20
VCC_AXG_NCTF_21
VCC_AXG_NCTF_22
VCC_AXG_NCTF_23
VCC_AXG_NCTF_24
VCC_AXG_NCTF_25
VCC_AXG_NCTF_26
VCC_AXG_NCTF_27
VCC_AXG_NCTF_28
VCC_AXG_NCTF_29
VCC_AXG_NCTF_30
VCC_AXG_NCTF_31
VCC_AXG_NCTF_32
VCC_AXG_NCTF_33
VCC_AXG_NCTF_34
VCC_AXG_NCTF_35
VCC_AXG_NCTF_36
VCC_AXG_NCTF_37
VCC_AXG_NCTF_38
VCC_AXG_NCTF_39
VCC_AXG_NCTF_40
VCC_AXG_NCTF_41
VCC_AXG_NCTF_42
VCC_AXG_NCTF_43
VCC_AXG_NCTF_44
VCC_AXG_NCTF_45
VCC_AXG_NCTF_46
VCC_AXG_NCTF_47
VCC_AXG_NCTF_48

VCC GFX NCTFVCC SM LF

VCC_AXG_NCTF_49
VCC_AXG_NCTF_50
VCC_AXG_NCTF_51
VCC_AXG_NCTF_52
VCC_AXG_NCTF_53
VCC_AXG_NCTF_54
VCC_AXG_NCTF_55
VCC_AXG_NCTF_56
VCC_AXG_NCTF_57
VCC_AXG_NCTF_58
VCC_AXG_NCTF_59
VCC_AXG_NCTF_60
VCC_AXG_NCTF_61
VCC_AXG_NCTF_62
VCC_AXG_NCTF_63
VCC_AXG_NCTF_64
VCC_AXG_NCTF_65
VCC_AXG_NCTF_66
VCC_AXG_NCTF_67
VCC_AXG_NCTF_68
VCC_AXG_NCTF_69
VCC_AXG_NCTF_70
VCC_AXG_NCTF_71
VCC_AXG_NCTF_72
VCC_AXG_NCTF_73
VCC_AXG_NCTF_74
VCC_AXG_NCTF_75
VCC_AXG_NCTF_76
VCC_AXG_NCTF_77
VCC_AXG_NCTF_78
VCC_AXG_NCTF_79
VCC_AXG_NCTF_80
VCC_AXG_NCTF_81
VCC_AXG_NCTF_82
VCC_AXG_NCTF_83

VCC_SM_LF1
VCC_SM_LF2
VCC_SM_LF3
VCC_SM_LF4
VCC_SM_LF5
VCC_SM_LF6
VCC_SM_LF7

T17
T18
T19
T21
T22
T23
T25
U15
U16
U17
U19
U20
U21
U23
U26
V16
V17
V19
V20
V21
V23
V24
Y15
Y16
Y17
Y19
Y20
Y21
Y23
Y24
Y26
Y28
Y29
AA16
AA17
AB16
AB19
AC16
AC17
AC19
AD15
AD16
AD17
AF16
AF19
AH15
AH16
AH17
AH19
AJ16
AJ17
AJ19
AK16
AK19
AL16
AL17
AL19
AL20
AL21
AL23
AM15
AM16
AM19
AM20
AM21
AM23
AP15
AP16
AP17
AP19
AP20
AP21
AP23
AP24
AR20
AR21
AR23
AR24
AR26
V26
V28
V29
Y31

VCCSM_LF1

AW45

VCCSM_LF2

BC39

VCCSM_LF3

BE39

VCCSM_LF4

BD17

VCCSM_LF5

BD4

VCCSM_LF6

AW8
AT6

VCCSM_LF7

0.22U_0402_10V4Z~D

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

C623

C622

C621

1

2

1

1

2

2

0.22U_0402_10V4Z~D

0.47U_0402_10V4Z~D

C624

1

1

2

2

1U_0402_6.3V4Z~D

1U_0402_6.3V4Z~D

C625

C627

C626

1

1

2

2

A A

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

Crestline(5 of 6)

LA-3302P

14 66Monday, February 26, 2007

1

0.4

of

5

U29I

A13

VSS_1

A15

VSS_2

A17

VSS_3

A24

VSS_4

AA21

VSS_5

AA24

VSS_6

AA29

VSS_7

AB20

VSS_8

AB23

D D

C C

B B

AB26
AB28
AB31
AC10
AC13

AC39
AC43
AC47

AD21
AD26
AD29

AD41
AD45
AD49

AD50
AE10

AE14
AF20

AF23
AF24
AF31

AG2
AG38
AG43
AG47
AG50

AH40
AH41

AJ11

AJ13

AJ21

AJ24

AJ29

AJ32

AJ43

AJ45

AJ49
AK20
AK21
AK26
AK28
AK31
AK51

AM11
AM13

AM3

AM4
AM41
AM45

AN38
AN39
AN43

AP48
AP50
AR11

AR39
AR44
AR47

AT10
AT14
AT41
AT49

AU23
AU29

AU36
AU49
AU51
AV39
AV48

AW1

AW12
AW16

VSS_9
VSS_10
VSS_11
VSS_12
VSS_13
VSS_14

AC3

VSS_15
VSS_16
VSS_17
VSS_18

AD1

VSS_19
VSS_20
VSS_21
VSS_22

AD3

VSS_23
VSS_24
VSS_25
VSS_26

AD5

VSS_27
VSS_28

AD8

VSS_29
VSS_30
VSS_31

AE6

VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41

AH3

VSS_42
VSS_43
VSS_44

AH7

VSS_45

AH9

VSS_46
VSS_47
VSS_48
VSS_49
VSS_50
VSS_51
VSS_52
VSS_53
VSS_54
VSS_55
VSS_56
VSS_57
VSS_58
VSS_59
VSS_60
VSS_61

AL1

VSS_62
VSS_63
VSS_64
VSS_65
VSS_66
VSS_67
VSS_68

AN1

VSS_69
VSS_70
VSS_71
VSS_72

AN5

VSS_73

AN7

VSS_74

AP4

VSS_75
VSS_76
VSS_77
VSS_78

AR2

VSS_79
VSS_80
VSS_81
VSS_82

AR7

VSS_83
VSS_84
VSS_85
VSS_86
VSS_87

AU1

VSS_88
VSS_89
VSS_90

AU3

VSS_91
VSS_92
VSS_93
VSS_94
VSS_95
VSS_96
VSS_97
VSS_98
VSS_99

VSS

LE88CLPM A0 QM21_FCBGA1299~D

VSS_100
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105
VSS_106
VSS_107
VSS_108
VSS_109
VSS_110
VSS_111
VSS_112
VSS_113
VSS_114
VSS_115
VSS_116
VSS_117
VSS_118
VSS_119
VSS_120
VSS_121
VSS_122
VSS_123
VSS_124
VSS_125
VSS_126
VSS_127
VSS_128
VSS_129
VSS_130
VSS_131
VSS_132
VSS_133
VSS_134
VSS_135
VSS_136
VSS_137
VSS_138
VSS_139
VSS_140
VSS_141
VSS_142
VSS_143
VSS_144
VSS_145
VSS_146
VSS_147
VSS_148
VSS_149
VSS_150
VSS_151
VSS_152
VSS_153
VSS_154
VSS_155
VSS_156
VSS_157
VSS_158
VSS_159
VSS_160
VSS_161
VSS_162
VSS_163
VSS_164
VSS_165
VSS_166
VSS_167
VSS_168
VSS_169
VSS_170
VSS_171
VSS_172
VSS_173
VSS_174
VSS_175
VSS_176
VSS_177
VSS_178
VSS_179
VSS_180
VSS_181
VSS_182
VSS_183
VSS_184
VSS_185
VSS_186
VSS_187
VSS_188
VSS_189
VSS_190
VSS_191
VSS_192
VSS_193
VSS_194
VSS_195
VSS_196
VSS_197
VSS_198

AW24
AW29
AW32
AW5
AW7
AY10
AY24
AY37
AY42
AY43
AY45
AY47
AY50
B10
B20
B24
B29
B30
B35
B38
B43
B46
B5
B8
BA1
BA17
BA18
BA2
BA24
BB12
BB25
BB40
BB44
BB49
BB8
BC16
BC24
BC25
BC36
BC40
BC51
BD13
BD2
BD28
BD45
BD48
BD5
BE1
BE19
BE23
BE30
BE42
BE51
BE8
BF12
BF16
BF36
BG19
BG2
BG24
BG29
BG39
BG48
BG5
BG51
BH17
BH30
BH44
BH46
BH8
BJ11
BJ13
BJ38
BJ4
BJ42
BJ46
BK15
BK17
BK25
BK29
BK36
BK40
BK44
BK6
BK8
BL11
BL13
BL19
BL22
BL37
BL47
C12
C16
C19
C28
C29
C33
C36
C41

4

U29J

C46

VSS_199

C50

VSS_200

C7

VSS_201

D13

VSS_202

D24

VSS_203

D3

VSS_204

D32

VSS_205

D39

VSS_206

D45

VSS_207

D49

VSS_208

E10

VSS_209

E16

VSS_210

E24

VSS_211

E28

VSS_212

E32

VSS_213

E47

VSS_214

F19

VSS_215

F36

VSS_216

F4

VSS_217

F40

VSS_218

F50

VSS_219

G1

VSS_220

G13

VSS_221

G16

VSS_222

G19

VSS_223

G24

VSS_224

G28

VSS_225

G29

VSS_226

G33

VSS_227

G42

VSS_228

G45

VSS_229

G48

VSS_230

G8

VSS_231

H24

VSS_232

H28

VSS_233

H4

VSS_234

H45

VSS_235

J11

VSS_236

J16

VSS_237

J2

VSS_238

J24

VSS_239

J28

VSS_240

J33

VSS_241

J35

VSS_242

J39

VSS_243

K12

VSS_245

K47

VSS_246

K8

VSS_247

L1

VSS_248

L17

VSS_249

L20

VSS_250

L24

VSS_251

L28

VSS_252

L3

VSS_253

L33

VSS_254

L49

VSS_255

M28

VSS_256

M42

VSS_257

M46

VSS_258

M49

VSS_259

M5

VSS_260

M50

VSS_261

M9

VSS_262

N11

VSS_263

N14

VSS_264

N17

VSS_265

N29

VSS_266

N32

VSS_267

N36

VSS_268

N39

VSS_269

N44

VSS_270

N49

VSS_271

N7

VSS_272

P19

VSS_273

P2

VSS_274

P23

VSS_275

P3

VSS_276

P50

VSS_277

R49

VSS_278

T39

VSS_279

T43

VSS_280

T47

VSS_281

U41

VSS_282

U45

VSS_283

U50

VSS_284

V2

VSS_285

V3

VSS_286

LE88CLPM A0 QM21_FCBGA1299~D

VSS

3

W11

VSS_287

W39

VSS_288

W43

VSS_289

W47

VSS_290

W5

VSS_291

W7

VSS_292

Y13

VSS_293

Y2

VSS_294

Y41

VSS_295

Y45

VSS_296

Y49

VSS_297

Y5

VSS_298

Y50

VSS_299

Y11

VSS_300

P29

VSS_301

T29

VSS_302

T31

VSS_303

T33

VSS_304

R28

VSS_305

AA32

VSS_306

AB32

VSS_307

AD32

VSS_308

AF28

VSS_309

AF29

VSS_310

AT27

VSS_311

AV25

VSS_312

H50

VSS_313

2

1

A A

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

Crestline(6 of 6)

LA-3302P

15 66Monday, February 26, 2007

1

0.4

of

5

DDR_A_DQS#[0..7]11

DDR_A_D[0..63]11
DDR_A_DM[0..7]11
DDR_A_DQS[0..7]11

DDR_A_MA[0..14]11

D D

+1.8V_SUS

2.2U_0603_6.3V6K~D

2.2U_0603_6.3V6K~D

1

2

1

2

C141

C119

RN6

RN12

RN5

RN11

RN10

RN8

RN13

C117

1

2

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

1

2

C104

2.2U_0603_6.3V6K~D

1

2

14
23

56_0404_4P2R_5%~D

14
23

56_0404_4P2R_5%~D

14
23

56_0404_4P2R_5%~D

14
23

56_0404_4P2R_5%~D

14
23

56_0404_4P2R_5%~D

14
23

56_0404_4P2R_5%~D

14
23

56_0404_4P2R_5%~D

2.2U_0603_6.3V6K~D

2.2U_0603_6.3V6K~D
C133

1

2

0.1U_0402_16V4Z~D

C130

1

2

C C

+0.9V_DDR_VTT

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

1

2

B B

A A

C136

DDR_A_MA1
DDR_A_MA3

56_0404_4P2R_5%~D

DDR_A_BS0
DDR_A_MA10

56_0404_4P2R_5%~D

DDR_A_RAS#
DDR_CS0_DIMMA#

56_0404_4P2R_5%~D

DDR_A_CAS#
DDR_A_WE#

56_0404_4P2R_5%~D

M_ODT1
DDR_CS1_DIMMA#

56_0404_4P2R_5%~D

DDR_CKE1_DIMMA

DDR_CKE0_DIMMA
DDR_A_BS2

56_0404_4P2R_5%~D

Layout Note:
Place one cap close to every 2 pullup
resistors terminated to +0.9V_DDR_VTT

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

1

1

2

2

C138

C137

1 4
2 3

1 4
2 3

1 4
2 3

1 4
2 3

1 4
2 3

R223
56_0402_5%~D

2 3
1 4

5

1

2

1

2

RN4

RN3

RN9

RN2

RN1

RN7

C132

0.1U_0402_16V4Z~D

C139

C437

1

2

0.1U_0402_16V4Z~D

C131

1

2

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

1

2

C140

+0.9V_DDR_VTT

12

C116

1

2

C118

0.1U_0402_16V4Z~D

1

2

C105

DDR_A_MA9
DDR_A_MA12

DDR_A_MA7
DDR_A_MA6

DDR_A_MA5
DDR_A_MA8

DDR_A_MA4
DDR_A_MA2

DDR_A_MA0
DDR_A_BS1

M_ODT0
DDR_A_MA13

DDR_A_MA14
DDR_A_MA11

0.1U_0402_16V4Z~D

Layout Note:
Place near JDIM1

0.1U_0402_16V4Z~D

1

1

2

2

C106

C107

4

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

1

1

2

2

C109

C108

Layout Note:
Place these resistor
closely DIMM0,all
trace length<750 mil

Layout Note:
Place these resistor
closely DIMM0,all
trace length
Max=1.3"

4

3

+1.8V_SUS +1.8V_SUS

ON TOP SIDE

JDIM2

1

VREF

3

2.2U_0603_6.3V6K~D
C115

VSS

5

DQ0

7

DQ1

9

VSS

11

DQS0#

13

DQS0

15

VSS

17

DQ2

19

DQ3

21

VSS

23

DQ8

25

DQ9

27

VSS

29

DQS1#

31

DQS1

33

VSS

35

DQ10

37

DQ11

39

VSS

41

VSS

43

DQ16

45

DQ17

47

VSS

49

DQS2#

51

DQS2

53

VSS

55

DQ18

57

DQ19

59

VSS

61

DQ24

63

DQ25

65

VSS

67

DM3

69

NC

71

VSS

73

DQ26

75

DQ27

77

VSS

79

CKE0

81

VDD

83

NC

85

BA2

87

VDD

89

A12

91

A9

93

A8

95

VDD

97

A5

99

A3

101

A1

103

VDD

105

A10/AP

107

BA0

109

WE#

111

VDD

113

CAS#

115

NC/S1#

117

VDD

119

NC/ODT1

121

VSS

123

DQ32

125

DQ33

127

VSS

129

DQS4#

131

DQS4

133

VSS

135

DQ34

137

DQ35

139

VSS

141

DQ40

143

DQ41

145

VSS

147

DM5

149

VSS

151

DQ42

153

DQ43

155

VSS

157

DQ48

159

DQ49

161

VSS

163

NC,TEST

165

VSS

167

DQS6#

169

DQS6

171

VSS

173

DQ50

175

DQ51

177

VSS

179

DQ56

181

DQ57

183

VSS

185

DM7

187

VSS

189

DQ58

191

DQ59

193

VSS

195

SDA

197

SCL

199

VDDSPD

201

GND

TYCO_1470815-2~D

RESERVE

DDR_A_D0
DDR_A_D5

DDR_A_DQS#0
DDR_A_DQS0

DDR_A_D3
DDR_A_D7

DDR_A_D13
DDR_A_D12

DDR_A_DQS#1
DDR_A_DQS1

DDR_A_D10

DDR_A_D17
DDR_A_D21

DDR_A_DQS#2
DDR_A_DQS2

DDR_A_D22
DDR_A_D23

DDR_A_D29

DDR_A_DM3

DDR_A_D27

DDR_A_D30

DDR_CKE0_DIMMA10

DDR_A_BS211

DDR_A_BS011
DDR_A_WE#11

DDR_A_CAS#11

DDR_CS1_DIMMA#10

M_ODT110

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

1

1

2

2

C110

C707

MEM_SDATA17,23
MEM_SCLK17,23

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

DDR_CKE0_DIMMA

DDR_A_BS2
DDR_A_MA12

DDR_A_MA9 DDR_A_MA7
DDR_A_MA8

DDR_A_MA5
DDR_A_MA3
DDR_A_MA1

DDR_A_MA10
DDR_A_BS0
DDR_A_WE#

DDR_A_CAS#
DDR_CS1_DIMMA#

M_ODT1
DDR_A_D33

DDR_A_D32
DDR_A_DQS#4

DDR_A_DQS4
DDR_A_D34

DDR_A_D39
DDR_A_D41

DDR_A_D40
DDR_A_DM5
DDR_A_D46

DDR_A_D43 DDR_A_D47
DDR_A_D49 DDR_A_D48

DDR_A_D52

DDR_A_DQS#6
DDR_A_DQS6

DDR_A_D51

DDR_A_D60
DDR_A_D56

DDR_A_DM7
DDR_A_D58

MEM_SDATA
MEM_SCLK

+3.3V_RUN

0.1U_0402_16V4Z~D
C113

1

1

2

2

NC/CKE1

DIMMA

2

VSS
DQ4
DQ5
VSS
DM0
VSS
DQ6
DQ7

VSS
DQ12
DQ13

VSS

DM1

VSS
CK0#

VSS
DQ14
DQ15

VSS

VSS
DQ20
DQ21

VSS

DM2

VSS
DQ22
DQ23

VSS
DQ28
DQ29

VSS

DQS3#

DQS3

VSS
DQ30
DQ31

VSS

VDD

NC/A15
NC/A14

VDD

VDD

VDD
RAS#

VDD
ODT0

NC/A13

VDD

VSS
DQ36
DQ37

VSS

DM4

VSS
DQ38
DQ39

VSS
DQ44
DQ45

VSS

DQS5#

DQS5

VSS
DQ46
DQ47

VSS
DQ52
DQ53

VSS
CK1#

VSS

DM6

VSS
DQ54
DQ55

VSS
DQ60
DQ61

VSS

DQS7#

DQS7

VSS
DQ62
DQ63

VSS

SAO

GND

2

1

V_DDR_MCH_REF

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30

CK0

32
34
36
38
40

42
44
46
48
50

NC

52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90

A11

92

A7

94

A6

96
98

A4

100

A2

102

A0

104
106

BA1

108
110

S0#

112
114
116
118
120

NC

122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164

CK1

166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200

SA1

202

DDR_A_D4
DDR_A_D6

DDR_A_DM0
DDR_A_D1

DDR_A_D2
DDR_A_D9

DDR_A_D8
DDR_A_DM1
M_CLK_DDR0

M_CLK_DDR#0
DDR_A_D15

DDR_A_D14DDR_A_D11

DDR_A_D20
DDR_A_D16

PM_EXTTS#0
DDR_A_DM2

DDR_A_D18
DDR_A_D19

DDR_A_D28
DDR_A_D24DDR_A_D25

DDR_A_DQS#3
DDR_A_DQS3

DDR_A_D26
DDR_A_D31

DDR_CKE1_DIMMA

DDR_A_MA14
DDR_A_MA11
DDR_A_MA6
DDR_A_MA4

DDR_A_MA2
DDR_A_MA0

DDR_A_BS1
DDR_A_RAS#
DDR_CS0_DIMMA#

M_ODT0
DDR_A_MA13

DDR_A_D36
DDR_A_D37

DDR_A_DM4
DDR_A_D35

DDR_A_D38
DDR_A_D44

DDR_A_D45
DDR_A_DQS#5

DDR_A_DQS5
DDR_A_D42

DDR_A_D53
M_CLK_DDR1

M_CLK_DDR#1
DDR_A_DM6
DDR_A_D50

DDR_A_D55DDR_A_D54
DDR_A_D61

DDR_A_D57
DDR_A_DQS#7

DDR_A_DQS7
DDR_A_D59DDR_A_D62

DDR_A_D63

R122 10K_0402_5%~D

1 2

R127 10K_0402_5%~D

1 2

V_DDR_MCH_REF

2.2U_0603_6.3V6K~D

1

C114

2

M_CLK_DDR0 10

M_CLK_DDR#0 10

PM_EXTTS#0 10

DDR_CKE1_DIMMA 10

DDR_A_BS1 11

DDR_A_RAS# 11
DDR_CS0_DIMMA# 10

M_ODT0 10

M_CLK_DDR1 10

M_CLK_DDR#1 10

0.1U_0402_16V4Z~D

1

C112

2

DELL CONFIDENTIAL/PROPRIETARY

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

DDRII-SODIMM SLOT1

LA-3302P

16 66Thursday, March 01, 2007

1

0.4

of

5

DDR_B_DQS#[0..7]11

DDR_B_D[0..63]11
DDR_B_DM[0..7]11
DDR_B_DQS[0..7]11

DDR_B_MA[0..14]11

D D

C C

B B

A A

+1.8V_SUS

+0.9V_DDR_VTT

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

1

2

C456

DDR_B_MA1
DDR_B_MA3

56_0404_4P2R_5%~D

DDR_B_BS0
DDR_B_MA10

56_0404_4P2R_5%~D

DDR_B_MA0
DDR_B_BS1

56_0404_4P2R_5%~D

DDR_B_RAS#
DDR_CS2_DIMMB#

56_0404_4P2R_5%~D

DDR_B_CAS#
DDR_B_WE#

56_0404_4P2R_5%~D

DDR_CKE3_DIMMB

DDR_CS3_DIMMB#
M_ODT3

56_0404_4P2R_5%~D

2.2U_0603_6.3V6K~D

1

2

0.1U_0402_16V4Z~D

C433

RN21

RN14

RN22

RN15

RN16

RN19

RN20

C412

1

2

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

1

2

C452

2.2U_0603_6.3V6K~D

1

2

C413

1

2

1

2

C451

DDR_B_MA9

14

DDR_B_MA12

23

56_0404_4P2R_5%~D

DDR_B_MA14

14

DDR_B_MA11

23

56_0404_4P2R_5%~D

DDR_B_MA5

14

DDR_B_MA8

23

56_0404_4P2R_5%~D

DDR_B_MA7

14

DDR_B_MA6

23

56_0404_4P2R_5%~D

DDR_B_MA4

14

DDR_B_MA2

23

56_0404_4P2R_5%~D

M_ODT2

14

DDR_B_MA13

23

56_0404_4P2R_5%~D

DDR_B_BS2

14

DDR_CKE2_DIMMB

23

56_0404_4P2R_5%~D

2.2U_0603_6.3V6K~D

2.2U_0603_6.3V6K~D

1

2

C455

1 4
2 3

1 4
2 3

1 4
2 3

1 4
2 3

1 4
2 3

R312
56_0402_5%~D

2 3
1 4

C440

C439

1

1

2

2

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D
C434

1

2

Layout Note:
Place one cap close to every 2 pullup
resistors terminated to +0.9V_DDR_VTT

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

1

1

2

2

C454

C453

+0.9V_DDR_VTT

RN23

RN24

RN17

RN18

RN25

12

RN26

5

2.2U_0603_6.3V6K~D

C438

1

2

0.1U_0402_16V4Z~D
C414

1

2

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

1

2

C450

Layout Note:
Place near JDIM2

C411

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

1

1

2

2

C410

C409

4

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

1

1

1

2

2

2

C408

Layout Note:
Place these resistor
closely DIMM0,all
trace length<750 mil

Layout Note:
Place these resistor
closely DIMM0,all
trace length
Max=1.3"

C406

C407

4

3

ON BOTTOM SIDE

DDR_B_D0
DDR_B_DQS#0

DDR_B_DQS0
DDR_B_D6

DDR_B_D7
DDR_B_D8

DDR_B_D9
DDR_B_DQS#1

DDR_B_DQS1
DDR_B_D14

DDR_B_D15

DDR_B_D16
DDR_B_D21

DDR_B_DQS#2
DDR_B_DQS2

DDR_B_D19
DDR_B_D18

DDR_B_D24 DDR_B_D28
DDR_B_D25

DDR_B_DM3

DDR_B_D26
DDR_B_D27

DDR_CKE2_DIMMB10

DDR_B_BS211

DDR_B_BS011
DDR_B_WE#11

DDR_B_CAS#11

DDR_CS3_DIMMB#10

1

2

C405

M_ODT310

MEM_SDATA16,23
MEM_SCLK16,23

DDR_CKE2_DIMMB

DDR_B_BS2
DDR_B_MA12

DDR_B_MA9
DDR_B_MA8

DDR_B_MA5
DDR_B_MA3
DDR_B_MA1

DDR_B_MA10
DDR_B_BS0
DDR_B_WE#

DDR_B_CAS#
DDR_CS3_DIMMB#

M_ODT3

DDR_B_D36
DDR_B_DQS#4

DDR_B_DQS4

DDR_B_D34
DDR_B_D40

DDR_B_D41
DDR_B_DM5

DDR_B_D42
DDR_B_D53

DDR_B_D49 DDR_B_D48

DDR_B_DQS#6
DDR_B_DQS6

DDR_B_D55
DDR_B_D50

DDR_B_D56
DDR_B_D60

DDR_B_DM7
DDR_B_D58

DDR_B_D59
MEM_SDATA

MEM_SCLK

+3.3V_RUN

0.1U_0402_16V4Z~D

2.2U_0603_6.3V6K~D

C431

1

1

2

2

C429

JDIM1

1

VREF

3

VSS

5

DQ0

7

DQ1

9

VSS

11

DQS0#

13

DQS0

15

VSS

17

DQ2

19

DQ3

21

VSS

23

DQ8

25

DQ9

27

VSS

29

DQS1#

31

DQS1

33

VSS

35

DQ10

37

DQ11

39

VSS

41

VSS

43

DQ16

45

DQ17

47

VSS

49

DQS2#

51

DQS2

53

VSS

55

DQ18

57

DQ19

59

VSS

61

DQ24

63

DQ25

65

VSS

67

DM3

69

NC

71

VSS

73

DQ26

75

DQ27

77

VSS

79

CKE0

81

VDD

83

NC

85

BA2

87

VDD

89

A12

91

A9

93

A8

95

VDD

97

A5

99

A3

101

A1

103

VDD

105

A10/AP

107

BA0

109

WE#

111

VDD

113

CAS#

115

NC/S1#

117

VDD

119

NC/ODT1

121

VSS

123

DQ32

125

DQ33

127

VSS

129

DQS4#

131

DQS4

133

VSS

135

DQ34

137

DQ35

139

VSS

141

DQ40

143

DQ41

145

VSS

147

DM5

149

VSS

151

DQ42

153

DQ43

155

VSS

157

DQ48

159

DQ49

161

VSS

163

NC,TEST

165

VSS

167

DQS6#

169

DQS6

171

VSS

173

DQ50

175

DQ51

177

VSS

179

DQ56

181

DQ57

183

VSS

185

DM7

187

VSS

189

DQ58

191

DQ59

193

VSS

195

SDA

197

SCL

199

VDDSPD

201

GND

TYCO_1565917-4~D

DIMMB

STANDARD

DQ4
DQ5

DM0
DQ6

DQ7

DQ12
DQ13

DM1

CK0#
DQ14

DQ15

DQ20
DQ21

DM2

DQ22
DQ23

DQ28
DQ29

DQS3#

DQS3

DQ30
DQ31

NC/CKE1

VDD
NC/A15
NC/A14

VDD

VDD

VDD

RAS#

VDD

ODT0

NC/A13

VDD

DQ36
DQ37

DM4

DQ38
DQ39

DQ44
DQ45

DQS5#

DQS5

DQ46
DQ47

DQ52
DQ53

CK1#

DM6

DQ54
DQ55

DQ60
DQ61

DQS7#

DQS7

DQ62
DQ63

SAO

GND

VSS

VSS
VSS

VSS

VSS
VSS

CK0
VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

BA1

VSS

VSS
VSS

VSS

VSS

VSS

VSS

VSS
CK1

VSS
VSS

VSS

VSS

VSS

VSS
SA1

NC

A11

A7
A6

A4
A2
A0

S0#

NC

2

+1.8V_SUS+1.8V_SUS V_DDR_MCH_REF

2

DDR_B_D5

4

DDR_B_D4DDR_B_D1

6
8

DDR_B_DM0

10
12

DDR_B_D2

14

DDR_B_D3

16
18

DDR_B_D13

20

DDR_B_D12

22
24

DDR_B_DM1

26
28

M_CLK_DDR2

30

M_CLK_DDR#2

32
34

DDR_B_D10

36

DDR_B_D11

38
40

42

DDR_B_D20

44

DDR_B_D17

46
48

PM_EXTTS#1

50

DDR_B_DM2

52
54

DDR_B_D22

56

DDR_B_D23

58
60
62

DDR_B_D29

64
66

DDR_B_DQS#3

68

DDR_B_DQS3

70
72

DDR_B_D30

74

DDR_B_D31

76
78

DDR_CKE3_DIMMB

80
82
84

DDR_B_MA14

86
88

DDR_B_MA11

90

DDR_B_MA7

92

DDR_B_MA6

94
96

DDR_B_MA4

98

DDR_B_MA2

100

DDR_B_MA0

102
104

DDR_B_BS1

106

DDR_B_RAS#

108

DDR_CS2_DIMMB#

110
112

M_ODT2

114

DDR_B_MA13

116
118
120
122

DDR_B_D33DDR_B_D32

124

DDR_B_D37

126
128

DDR_B_DM4

130
132

DDR_B_D38

134

DDR_B_D39DDR_B_D35

136
138

DDR_B_D44

140

DDR_B_D45

142
144

DDR_B_DQS#5

146

DDR_B_DQS5

148
150

DDR_B_D43DDR_B_D46

152

DDR_B_D47

154
156

DDR_B_D52

158
160
162

M_CLK_DDR3

164

M_CLK_DDR#3

166
168

DDR_B_DM6

170
172

DDR_B_D54

174

DDR_B_D51

176
178

DDR_B_D57

180

DDR_B_D61

182
184

DDR_B_DQS#7

186

DDR_B_DQS7

188
190

DDR_B_D62

192

DDR_B_D63

194
196
198
200

202

10K_0402_5%~D

12

M_CLK_DDR2 10

M_CLK_DDR#2 10

PM_EXTTS#1 10

DDR_CKE3_DIMMB 10

DDR_B_BS1 11

DDR_B_RAS# 11
DDR_CS2_DIMMB# 10

M_ODT2 10

M_CLK_DDR3 10

M_CLK_DDR#3 10

R243

10K_0402_5%~D

R241

V_DDR_MCH_REF

2.2U_0603_6.3V6K~D

1

C447

2

+3.3V_RUN

12

1

0.1U_0402_16V4Z~D

1

C436

2

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

DDRII-SODIMM SLOT2

LA-3302P

17 66Thursday, March 01, 2007

1

0.4

of

5

+3.3V_SUS

12

R423

8.2K_0402_5%~D

2

Q38

2

Q39

B

+3.3V_SUS

B

C

E

3 1

12

C

E

3 1

THERMATRIP1#

1

C628

0.1U_0402_16V4Z~D

2

R426

8.2K_0402_5%~D

THERMATRIP2#

1

C632

0.1U_0402_16V4Z~D

2

+1.05V_VCCP

R425

D D

H_THERMTRIP#7

THERMTRIP_MCH#10

2.2K_0402_5%~D

1 2

MMST3904-7-F_SOT323-3~D

+1.05V_VCCP

R427

2.2K_0402_5%~D

1 2

MMST3904-7-F_SOT323-3~D

Place under CPU

C C

C633

@

2200P_0402_50V7K~D

Place C633 close to the Q40 as possible

Place C636 close to the Guardian pins as possible

H_THERMDA7

470P_0402_50V7K~D

H_THERMDC7

+3.3V_SUS

0.1U_0402_16V4Z~D

12

R186

8.2K_0402_5%~D

+3.3V_SUS

B B

+3.3V_SUS

R196

@

1 2

10K_0402_5%~D

@

1 2

10K_0402_5%~D

A A

R194

MDC_RST_DIS#

SIO_GFX_PWR

+3.3V_RUN

THERMTRIP_VGA#52

5

R428

1 2

49.9_0603_1%~D

1

C639

2

C100

2200P_0402_50V7K~D

12

2

1

C636

1

C637

0.1U_0402_16V4Z~D

2

2

1

R187

2.2K_0402_5%~D

2@

THERM_B3

C

+3.3V_SUS

2

B

4

RB751S40T1_SOD523-2~D

E

3 1

+RTC_CELL

E

@

2

B

Q40
MMST3904-7-F_SOT323-3~D

1

2

12

R436
332K_0402_1%~D

12

R438
118K_0402_1%~D

12

R433

8.2K_0402_5%~D

THERMATRIP3#

C

Q76
MMST3904-7-F_SOT323-3~D

2@

3 1

4

D19

2 1

+3VSUS_THRM

1

C638

2

0.1U_0402_16V4Z~D

1

C630

2

22U_0805_6.3VAM~D

2200P_0402_50V7K~D

2

C634

1

SUSPWROK42
ICH_PWRGD#42

R437

1 2

1K_0402_5%~D

MDC_RST_DIS#33

AUDIO_AVDD_ON27

1

C203

0.1U_0402_16V4Z~D

2

2@

3

FAN1 Control and Tachometer

+3.3V_RUN

12

R424
10K_0402_5%~D

12

R414
0_0402_5%~D

+FAN1_VOUT
FAN1_TACH_FB

Place C634 close to the
Guardian pins as possible

THRM_SMBDAT39,49
THRM_SMBCLK39,49

REM_DIODE1_P
REM_DIODE1_N

1 2

R429 1K_0402_5%~D

1 2

R432 1K_0402_5%~D

THERMATRIP1#
THERMATRIP2#
THERMATRIP3#

MDC_RST_DIS#
SIO_GFX_PWR
5V_CAL_SIO#

AUDIO_AVDD_ON

FAN1_TACH 39

JFAN1

1

1

2

2

3

3

MOLEX_53398-0371~D

Discrete

VGA_THERMDP

1

C706
470P_0402_50V7K~D

3

2

U31

11

SMDATA

12

SMBCLK

38

DP1

37

DN1

41

DP2

40

DN2

35

3V_SUS

21

RTC_PWR3V

23

VSUS_PWRGD

16

3V_PWROK#

17

THERMTRIP1#

18

THERMTRIP2#

19

THERMTRIP3#

42

VSET

26

XEN

34

VSS

7

FAN_OUT

8

FAN_OUT

39

FAN_DAC1

10

GPIO1

13

GPIO2

14

GPIO3

15

GPIO4

22

GPIO5

36

GPIO6/FAN_DAC2

49

PAD_GND

VGA_THERMDN

Place Capacitor close to Guardian Chip

+FAN1_VOUT

SMBUS ADDRESS : 2F

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

VGA_THERMDP 53

VGA_THERMDN 53

VCP1
VCP2

ATF_INT#

POWER_SW#

ACAVAIL_CLR

THERMTRIP_SIO

SYS_SHDN#

LDO_SHDN#/ADDR

LDO_POK
LDO_SET
LDO_OUT

LDO_OUT

LDO_IN
LDO_IN

VDD_3V
VDD_5V

VDD_5V

EMC4001_QFN48~D

1

C645

2

10U_0805_10V4Z~D

DP3
DN3

DP4
DN4

DP5
DN5

43
46

45
44

48
47

2
1

20
3
4
25
24
27
33
28
32

31

30
29

9
5

6

1

C646

2

VCP2

VCP2
REM_DIODE3_P

REM_DIODE3_N
REM_DIODE4_P

REM_DIODE4_N
VGA_THERMDP

VGA_THERMDN

7.5K_0402_5%~D

LDO_SET

+3V_LDOIN

+5V_RUN

0.1U_0402_16V4Z~D

2

+5V_SUS

12

R771

2.21K_0603_1%~D

1

C750

2

2200P_0402_50V7K~D

PWR_MON 48

Place C649 close to the
Guardian pins as possible.

1

2

Diode circuit at DP 4/ DN 4 is used for skin temp
sensor (plac e d o p ti m a l l y between CPU, MCH and GPU).

1

2

ATF_INT#

ATF_INT# 38

POWER_SW# 39,40

ACAV_IN 39,49,50

R434

12

+3.3V_SUS

1

1

C640

2

2

1@

10U_0805_10V4Z~D

1

1

C643

2

2

1U_0603_10V4Z~D

1

1

C647

2

2

10U_0805_10V4Z~D

2

VSET=

R436+R438

VSET =

12

R772
10K_0603_1%_TSM1A103F34D3RZ~D

Q102

13

D

2N7002W-7-F_SOT323-3~D

2

G

S

C649
2200P_0402_50V7K~D

Q41 Place near the
bottom SODIMM

C418
2200P_0402_50V7K~D

C648

0.1U_0402_16V4Z~D

R96

10K_0402_5%~D

+2.5V_RUN

C641

0.1U_0402_16V4Z~D

@

R439

12

0_1210_5%~D

C644

0.1U_0402_16V4Z~D

+3.3V_RUN

DELL CONFIDENTIAL/PROPRIETARY

Title

Size Document Number Rev

Date: Sheet

1

R438

Tp-70

x 3.3V

=0.865V

=> Tp = 88.2 C

21

+3.3V_SUS

12

R773
10K_0402_5%~D

5V_CAL_SIO#

This thermistor circuit is located near
Top side DDR connector.

REM_DIODE3_N, REM_DIODE3_P routing together.
Trace width / Spacing = 10 / 10 mil

C

Q41

2

B

MMST3904-7-F_SOT323-3~D

E

3 1

C

Q19

2

B

MMST3904-7-F_SOT323-3~D

E

3 1

12

R430

10K_0402_5%~D

R431

@

10K_0402_5%~D

+3.3V_RUN

12

12

+3.3V_SUS

+3.3V_ALW

+RTC_CELL

THERMTRIP_SIO
THERM_STP# 45

2.5V_RUN_PWRGD 42

1

C650
2200P_0402_50V7K~D

2

@

Place C650
close to Q41

1

C904
2200P_0402_50V7K~D

2

@

C418 close to Guardian and
C904 close to diode Q19.

+2.5V_RUN

31.6K_0402_1%~D

@

12

R485

LDO_SET

Voltage margining
circuit for LDO output.
For Vmargin, stuff
Ra=31.6K and Rb=30K.
Rb=1K for production

1K_0402_1%~D

12

R441

Compal Electronics, Inc.

FAN & Thermal Sensor

LA-3302P

18 66Thursday, March 01, 2007

1

Ra

Rb

0.4

of

5

D D

JLVDS

45

MGND1

46

MGND2

47

MGND3

48

MGND4

49

MGND5

50

MGND6

51

MGND7

52

MGND8

53

MGND9

54

MGND10

55

MGND11

56

NC

57

C C

TXLCLKOUT-

NC

TXLCLKOUT+

PANEL_I2C_CLK

PANEL_I2C_DAT

PNL_SLFTST
LCDPWR_SRC
LCDPWR_SRC
LCDPWR_SRC

PBAT_SMBCLK
PBAT_SMBDAT

LAMP_START

IPEX_20330-044E-11F~D

TXUCLKUT-

TXUCLKUT+

GND1

TXUOUT2-

TXUOUT2+

GND2

TXUOUT1-

TXUOUT1+

GND3

TXUOUT0-

TXUOUT0+

GND4

GND5
TXLOUT2­TXLOUT2+

GND6
TXLOUT1­TXLOUT1+

GND7
TXLOUT0­TXLOUT0+

GND8

GND9

VEDID

GND10
LCDVDD1
LCDVDD2

GND11

FPBACK

GND12

GND13

+5V_ALWF

GND14

44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

LCD_BCLK­LCD_BCLK+

LCD_B2­LCD_B2+

LCD_B1­LCD_B1+

LCD_B0­LCD_B0+

LCD_ACLK­LCD_ACLK+

LCD_A2­LCD_A2+

LCD_A1­LCD_A1+

LCD_A0­LCD_A0+

LCD_DDCCLK
LCD_DDCDATA

LCD_TST

LAMP_STAT#

LCD_TST 38

4

LCD_BCLK- 53
LCD_BCLK+ 53

LCD_B2- 53
LCD_B2+ 53

LCD_B1- 53
LCD_B1+ 53

LCD_B0- 53
LCD_B0+ 53

LCD_ACLK- 53
LCD_ACLK+ 53

LCD_A2- 53
LCD_A2+ 53

LCD_A1- 53
LCD_A1+ 53

LCD_A0- 53
LCD_A0+ 53

LCD_DDCCLK 52
LCD_DDCDATA 52

0.1U_0402_16V4Z~D

LCD_SMBCLK 39
LCD_SMBDAT 39

T28 PAD~D

3

+LCDVDD

12

R26
470_0402_5%~D

13

D

Q9

S

D24

2N7002W-7-F_SOT323-3~D

LCD_VCC_TEST_EN39

1 2

R156 0_0402_5%~D@

ENVDD52

+3.3V_RUN

C45

1

1

2

2

+LCDVDD

C44

0.1U_0402_16V4Z~D

1

2

+3.3V_RUN

+5V_ALW

C176

0.1U_0402_16V4Z~D

12

R155
10K_0402_5%~D

3

2

BAT54CW_SOT323~D

1 2

R527

@

0_0402_5%~D

BIA_PWM 52

1

Populate R155 and de-pop R156
for discrete because it
doesn't support DPST

+15V_ALW

2

G

2

I

2

+15V_ALW

12

R23
100K_0402_5%~D

1

O

G

DDTC124EUA-7-F_SOT323-3~D

3

12

13

D

2

G

S

Q7

+LCDVDD

R24
100K_0402_5%~D

Q8

2N7002W-7-F_SOT323-3~D

SI3456BDV-T1-E3_TSOP6~D

4 5

1

C30

2

0.1U_0603_50V4Z~D

Q11

D

S

G

3

12

R25

@

100K_0402_5%~D

1

6
2

1

+3.3V_RUN

1

C42

2

0.1U_0402_16V4Z~D

+3.3V_RUN

2

B B

A A

1

2

+INV_PWR_SRC

C180

0.1U_0603_50V4Z~D

LCD_SMBCLK

LCD_SMBDAT

G

1 3

D

S

Q12

@

2N7002W-7-F_SOT323-3~D

+3.3V_RUN

2

G

1 3

D

S

Q13

@

2N7002W-7-F_SOT323-3~D

I2CH_SCL

I2CH_SDA

I2CH_SCL 52

I2CH_SDA 52

1

C427

2

1

2

0.1U_0603_50V4Z~D

40mil

1

C463

2

2200P_0402_50V7K~D

+PWR_SRC

12

C173

1000P_0402_50V7K~D

R154
200K_0402_5%~D

Q24

FDS4435BZ_SO8~D

1
2
3

R153

1 2

100K_0402_5%~D

RUN_ON37,39,41,42,51

4

D

1 3

2

8
7
6
5

S

G

40mil

Q25
2N7002W-7-F_SOT323-3~D

+INV_PWR_SRC

1

C174

0.1U_0603_50V4Z~D

2

FDS4435: P CHANNAL

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

Internal LVDS

LA-3302P

19 66Thursday, March 01, 2007

1

0.4

of

5

D D

4

3

2

1

D8

SDM10U45-7_SOD523-2~D

F3

@

+5V_RUN

21

12

0.12A_48V_NANOSMDC012F~D

12

R792
0_1206_5%~D

RED
DAT_DDC2

GREEN
JVGA_HS

BLUE
JVGA_VS

M_ID2#
CLK_DDC2

CRT_VCC

1

C151

2

0.01U_0402_16V7K~D

JCRT

6

11

1
7

12

2
8

13

14
10

15

SUYIN_070915FR015S201CU~D

16

17
3
9

4

5

D11
DA204U_SOT323~D

1

@

+3.3V_RUN

2

3

L11

CRT_RED36,52

CRT_GRN36,52

C C

CRT_BLU36,52

CRT_RED

CRT_GRN

CRT_BLU

R141

22P_0402_50V8J~D

1

C161

2

@

22P_0402_50V8J~D

1

C165

2

@

12

12

R142

150_0402_1%~D

150_0402_1%~D

12

R143

150_0402_1%~D

1

C162

2

@

Evaluate Package

DAT_DDC236,52
CLK_DDC236,52

SDM10U45-7_SOD523-2~D

+5V_RUN

B B

CRT_HSYNC52

CRT_VSYNC52

2 1

R60

1 2

30_0402_1%~D

R59

1 2

30_0402_1%~D

+5V_RUN_SYNC

D6

5

A2Y

3

SN74AHCT1G125GW_SC70-5~D

5

A2Y

3

R144

1K_0402_5%~D

1 2

1

U15

P

4

4

1 2

R146
10_0402_5%~D

1 2

R138

10_0402_5%~D

OE#

G

1

P

OE#

G

U14

SN74AHCT1G125GW_SC70-5~D

BLM18BB750SN1D_0603~D

1 2

BLM18BB750SN1D_0603~D

1 2

BLM18BB750SN1D_0603~D

1 2

22P_0402_50V8J~D

L1

BLM18AG121SN1D_0603~D

1 2

HSYNC_R 36

VSYNC_R 36

L2

BLM18AG121SN1D_0603~D

1 2

L10

L9

+5V_RUN_SYNC

12

R3

@

1K_0402_5%~D

1

C5

2

10P_0402_50V8J~D

1

C149
10P_0402_50V8J~D

2

@

12

@

R5

1K_0402_5%~D

1

C4

2

10P_0402_50V8J~D

R137

1 2

1

C719

2

@

10P_0402_50V8J~D

R2

2.2K_0402_5%~D

1 2

2.2K_0402_5%~D

1

C712

2

@

10P_0402_50V8J~D

0.1U_0402_16V4Z~D

2

1

C148
10P_0402_50V8J~D

2

@

T5 PAD~D

D10
DA204U_SOT323~D

1

@

3

1

C160

2

1

2

D9
DA204U_SOT323~D

1

@

2

3

C147
10P_0402_50V8J~D

@

A A

DA204U

K1

A2

DELL CONFIDENTIAL/PROPRIETARY

A1 K2

5

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

4

3

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

CRT

LA-3302P

20 66Thursday, March 01, 2007

1

0.4

of

5

+3.3V_RUN

D D

C C

B B

1 2

R442 8.2K_0402_5%~D

1 2

R443 8.2K_0402_5%~D

1 2

R444 8.2K_0402_5%~D

1 2

R445 8.2K_0402_5%~D

1 2

R446 8.2K_0402_5%~D

1 2

R447 8.2K_0402_5%~D

1 2

R448 8.2K_0402_5%~D

1 2

R449 8.2K_0402_5%~D

+3.3V_RUN

1 2

R450 8.2K_0402_5%~D

1 2

R451 8.2K_0402_5%~D

1 2

R452 8.2K_0402_5%~D

1 2

R453 8.2K_0402_5%~D

1 2

R454 8.2K_0402_5%~D

1 2

R458 8.2K_0402_5%~D

1 2

R459 8.2K_0402_5%~D

1 2

R461 20K_0402_5%~D

1 2

R460 20K_0402_5%~D

1 2

R601 20K_0402_5%~D

1 2

R631 20K_0402_5%~D

BIOS should not enable the internal
GPIO pull up resistor

PCI_DEVSEL#
PCI_STOP#
PCI_TRDY#
PCI_FRAME#

PCI_PLOCK#
PCI_IRDY#
PCI_SERR#
PCI_PERR#

PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#

ICH_GPIO2_PIRQE#

PCI_REQ0#
PCI_REQ1#

SB_LOM_PCIE_RST#
SB_WWAN_PCIE_RST#
SB_WLAN_PCIE_RST#
SB_NB_PCIE_RST#

PCI_AD[0..31]30,35

PCI_GNT3#

4

PCI_PIRQA#35

PCI_PIRQD#30

12

R477
1K_0402_5%~D

@

PCI_AD0
PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD6
PCI_AD7
PCI_AD8
PCI_AD9
PCI_AD10
PCI_AD11
PCI_AD12
PCI_AD13
PCI_AD14
PCI_AD15
PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20
PCI_AD21
PCI_AD22
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30
PCI_AD31

PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#

U32B

D20

AD0

E19

AD1

D19

AD2

A20

AD3

D17

AD4

A21

AD5

A19

AD6

C19

AD7

A18

AD8

B16

AD9

A12

AD10

E16

AD11

A14

AD12

G16

AD13

A15

AD14

B6

AD15

C11

AD16

A9

AD17

D11

AD18

B12

AD19

C12

AD20

D10

AD21

C7

AD22

F13

AD23

E11

AD24

E13

AD25

E12

AD26

D8

AD27

A6

AD28

E8

AD29

D6

AD30

A3

AD31

Interrupt I/F

F9

PIRQA#

B5

PIRQB#

C5

PIRQC#

A10

PIRQD#

PCI

ICH8M_BGA676~D

REQ0#

GNT0#
REQ1#/GPIO50
GNT1#/GPIO51
REQ2#/GPIO52
GNT2#/GPIO53
REQ3#/GPIO54
GNT3#/GPIO55

C/BE0#

C/BE1#

C/BE2#

C/BE3#

IRDY#

PAR

PCIRST#

DEVSEL#

PERR#

PLOCK#

SERR#

STOP#

TRDY#

FRAME#

PLTRST#

PCICLK

PME#

PIRQE#/GPIO2

PIRQF#/GPIO3
PIRQG#/GPIO4
PIRQH#/GPIO5

12

R462

1K_0402_5%~D

3

A4
D7
E18
C18
B19
F18
A11
C10

C17
E15
F16
E17

C8
D9
G6
D16
A7
B7
F10
C16
C9
A17

AG24
B10
G7

F8
G11
F12
B3

PCI_REQ0#
PCI_GNT0#
PCI_REQ1#
PCI_GNT1#

SB_WWAN_PCIE_RST#
SB_LOM_PCIE_RST#

PCI_GNT3#
PCI_C_BE0#

PCI_C_BE1#
PCI_C_BE2#
PCI_C_BE3#

PCI_IRDY#
PCI_PAR
PCI_PCIRST#
PCI_DEVSEL#
PCI_PERR#
PCI_PLOCK#
PCI_SERR#
PCI_STOP#
PCI_TRDY#
PCI_FRAME#

PCI_PLTRST#
CLK_PCI_ICH
ICH_PME#

ICH_GPIO2_PIRQE#
SB_WLAN_PCIE_RST#
SB_NB_PCIE_RST#

ICH_SPI_CS1#23

PCI_REQ0# 36

PCI_GNT0# 35,36

PCI_REQ1# 30

PCI_GNT1# 30
SB_WWAN_PCIE_RST# 34

T1 PAD~D

SB_LOM_PCIE_RST# 28

T2 PAD~D

PCI_C_BE0# 30,35
PCI_C_BE1# 30,35
PCI_C_BE2# 30,35
PCI_C_BE3# 30,35

PCI_ I RDY# 30,35,36
PCI_PAR 30,35

PCI_DEVSEL# 30,35
PCI_PERR# 30,35

PCI_PLOCK# 35

PCI_SERR# 30,35

PCI_STOP# 30,35
PCI_TRDY# 30,35

PCI_FRAME# 30,35,36

CLK_PCI_ICH 6

ICH_PME# 38

SB_WLAN_PCIE_RST# 34
SB_NB_PCIE_RST# 10

PCIE_MCARD2_DET# 34

ICH_SPI_CS1#PCI_GNT0#

12

R463

2

+3.3V_SUS

PCI_PCIRST#

PCI_PLTRST#

1K_0402_5%~D@

1
2

4
5

10

9

13
12

14

P

IN1

OUT

IN2

G

7

+3.3V_SUS

14

P

IN1

OUT

IN2

G

7

+3.3V_SUS

14

P

IN1

OUT

IN2

G

7

+3.3V_SUS

14

P

IN1

OUT

IN2

G

7

C651

0.1U_0402_16V4Z~D

U33A

PCI_RST#

3

74VHC08MTCX_NL_TSSOP14~D

U33B

PLTRST1#

6

74VHC08MTCX_NL_TSSOP14~D

U33C

PLTRST2#

8

74VHC08MTCX_NL_TSSOP14~D

U33D

PLTRST3#

11

74VHC08MTCX_NL_TSSOP14~D

1

PCI_RST# 30,31,35

PLTRST1# 10

PLTRST2# 38,39

PLTRST3# 28,34

Place closely pin U19.A9

CLK_PCI_ICH

A16 away override strap.

PCI_GNT3#

A A

Low = A16 swap override enabled.
High = Default.

Boot BIOS Strap

PCI_GNT0# SPI_CS1#

*

0

1

1

R464

10_0402_5%~D@

Boot BIOS Location

1

0

1

SPI

PCI

LPC

1 2

CLK_ICH_TERM

1

C652

8.2P_0402_50V8J~D@

2

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

ICH8(1/4)

LA-3302P

21 66Thursday, March 01, 2007

1

0.4

of

5

D D

+3.3V_RUN

32.768K_12.5P_1TJS125DJ4A420P~D

1 2

R490 8.2K_0402_5%~D

C C

ICH_AZ_CODEC_SDOUT26

ICH_AZ_CO D EC_SYNC26

ICH_AZ_CODEC_RST#26

ICH_AZ_CODEC_BITCLK26

B B

IDE_IRQ

1 2

1 2

1 2

R496

1 2

33_0402_5%~D

+RTC_CELL

ICH_AZ_SDOUT

ICH_AZ_SYNC

ICH_AZ_RST#

ICH_AZ_BITCLK

Close to U19

R493 33_0402_5%~D

R494 33_0402_5%~D

R495 33_0402_5%~D

1

C660

27P_0402_50V8J~D

2

1 2

R470 20K_0402_5%~D

1 2

R471 1M_0402_5%~D

1

1

CMOS_CLR @SHORT PADS~D

1 2

C655

1U_0603_10V4Z~D

ICH_AZ_MDC_BITCLK33
ICH_AZ_MDC_SYNC33

ICH_AZ_MDC_RST#33

ICH_AZ_CODEC_SDIN026

ICH_AZ_MDC_SDIN133

ICH_AZ_MDC_SDOUT33

PSATA_IRX_DTX_N0_C25
PSATA_IRX_DTX_P0_C25

PSATA_ITX_DRX_N025
PSATA_ITX_DRX_P025

XOR Chain Entrance Strap

A A

00

0

1

11

5

DescriptionICH RSVD HDA SDOUT

RSVD

1

Enter XOR Chain

0

Normal Operation (Default)

Set PCIE port config bit 1

Package

9.6X4.06 mm

15P_0402_50V8J~D

15P_0402_50V8J~D

2

2

SATA_ACT#_R43

CLK_PCIE_SATA#6
CLK_PCIE_SATA6

4

C653

12

Y4

C654

12

C656

27P_0402_50V8J~D

12

C658 3900P_0402_50V7K~D

12

C659 3900P_0402_50V7K~D

+3.3V_RUN

12

R385
1K_0402_5%~D

@

12

R386
1K_0402_5%~D

@

4

ICH_RTCX1

1 4

2 3

R469

1 2

0_0402_5%~D

+1.5V_RUN_PCIE_ICH

12

R481 33_0402_5%~D

1 2
1 2

R483 33_0402_5%~D

1 2

R484 33_0402_5%~D

1 2

R487 33_0402_5%~D

1 2

R491 24.9_0402_1%~D

Within 500 mils

ICH_AZ_SDOUT

12

R467
10M_0402_5%~D

ICH_RTCX2
ICH_RTCRST#
INTRUDER#
ICH_INTVRMEN

LAN100_SLP

24.9_0402_1%~D

1 2

ICH_AZ_BITCLK
ICH_AZ_SYNC

ICH_AZ_RST#
ICH_AZ_CODEC_SDIN0

ICH_AZ_MDC_SDIN1

ICH_AZ_SDOUT

SATA_ACT#_R
PSATA_IRX_DTX_N0_C

PSATA_IRX_DTX_P0_C
SATA_TX0-_N0
SATA_TX0+_P0

CLK_PCIE_SATA#
CLK_PCIE_SATA

ICH_RSVD 23

R480

3

+RTC_CELL +RTC_CELL

12

R472
332K_0402_1%~D

ICH_INTVRMEN

12

@

R478

0_0402_1%

ICH8M Internal VR Enable Strap
(Internal VR f or Vc cS us 1.05, VccSus1.5, VccCL1.5)

ICH_INTVRMEN

U32A

AG25

RTCX1

AF24

RTCX2

AF23

RTCRST#

AD22

INTRUDER#

AF25

INTVRMEN

AD21

LAN100_SLP

B24

GLAN_CLK

D22

LAN_RSTSYNC

C21

LAN_RXD0

B21

LAN_RXD1

C22

LAN_RXD2

D21

LAN_TXD_0

E20

LAN_TXD_1

C20

LAN_TXD_2

AH21

GLAN_DOCK#/GPIO13

D25

GLAN_COMPI

C25

GLAN_COMPO

AJ16

HDA_BIT_CLK

AJ15

HDA_SYNC

AE14

HDA_RST#

AJ17

HDA_SDIN0

AH17

HDA_SDIN1

AH15

HDA_SDIN2

AD13

HDA_SDIN3

AE13

HDA_SDOUT

AE10

HDA_DOCK_EN#/GPIO33

AG14

HDA_DOCK_RST#/GPIO34

AF10

SATALED#

AF6

SATA0RXN

AF5

SATA0RXP

AH5

SATA0TXN

AH6

SATA0TXP

AG3

SATA1RXN

AG4

SATA1RXP

AJ4

SATA1TXN

AJ3

SATA1TXP

AF2

SATA2RXN

AF1

SATA2RXP

AE4

SATA2TXN

AE3

SATA2TXP

AB7

SATA_CLKN

AC6

SATA_CLKP

AG1

SATARBIAS#

AG2

SATARBIAS

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

Low = Internal VR Disabled
High = Internal VR Enabled(Default)

E5

FWH0/LAD0

F5

FWH1/LAD1

G8

FWH2/LAD2

F6

FWH3/LAD3

RTC

LPCCPU

CPUPWRGD/GPIO49

LAN / GLAN

IHDA

IDE

SATA

FWH4/LFRAME#

LDRQ1#/GPIO23

ICH8M_BGA676~D

LDRQ0#

A20GATE

A20M#

DPRSTP#

DPSLP#

FERR#

IGNNE#

INIT#
INTR

RCIN#

SMI#

STPCLK#

THRMTRIP#

DD10
DD11
DD12
DD13
DD14
DD15

DCS1#
DCS3#

DIOR#

DIOW#

DDACK#

IDEIRQ

IORDY

DDREQ

NMI

TP8
DD0

DD1
DD2
DD3
DD4
DD5
DD6
DD7
DD8
DD9

DA0
DA1
DA2

C4
G9

E6
AF13

AG26
AF26

AE26
AD24
AG29
AF27
AE24

AC20
AH14

AD23
AG28

AA24
AE27
AA23
V1

U2
V3
T1
V4
T5
AB2
T6
T3
R2
T4
V6
V5
U1
V2
U6

AA4
AA1
AB3

Y6
Y5

W4
W3
Y2
Y3
Y1
W5

2

LPC_LAD0
LPC_LAD1
LPC_LAD2
LPC_LAD3

LPC_LFRAME#
LPC_LDRQ0#

LPC_LDRQ1#
SIO_A20GATE

H_A20M#
H_DPRSTP#

H_DPSLP#
H_FERR#
H_PWRGOOD
H_IGNNE#
H_INIT#

H_INTR
SIO_RCIN#

H_NMI
H_SMI#

H_STPCLK#
THRMTRIP_ICH#
ICH_TP8
IDE_DD0

IDE_DD1
IDE_DD2
IDE_DD3
IDE_DD4
IDE_DD5
IDE_DD6
IDE_DD7
IDE_DD8
IDE_DD9
IDE_DD10
IDE_DD11
IDE_DD12
IDE_DD13
IDE_DD14
IDE_DD15

IDE_DA0
IDE_DA1
IDE_DA2

IDE_DCS1#
IDE_DCS3#

IDE_DIOR#
IDE_DIOW#
IDE_DDACK#
IDE_IRQ
IDE_DIORDY
IDE_DDREQ

2

1

12

R475
332K_0402_1%~D

LAN100_SLP

R476

@

0_0402_5%~D

1 2

ICH8M LAN100 SLP Strap
(Internal VR f or Vc cL AN1.05 and VccCL1.05)

ICH_LAN100_SLP Low = Internal VR Disabled

LPC_LAD0 28,38,39
LPC_LAD1 28,38,39
LPC_LAD2 28,38,39
LPC_LAD3 28,38,39

LPC_LFRAME# 28,38,39
LPC_LDRQ0# 38

LPC_LDRQ1# 38

SIO_A20GATE 39
H_A20M# 7

H_FERR# 7
H_PWRGOOD 8
H_IGNNE# 7
H_INIT# 7

H_INTR 7
SIO_RCIN# 39

H_NMI 7
H_SMI# 7

H_STPCLK# 7

T12PAD~D

IDE_DD[0..15] 25

IDE_DA0 25
IDE_DA1 25
IDE_DA2 25

IDE_DCS1# 25
IDE_DCS3# 25

IDE_DIOR# 25
IDE_DIOW# 25
IDE_DDACK# 25

IDE_IRQ 25
IDE_DIORDY 25
IDE_DDREQ 25

High = Interna l V R Enabled(Default)

+1.05V_VCCP

12

12

R474

R473

@

@

+1.05V_VCCP

C470

0.1U_0402_16V4Z~D

56_0402_1%~D

12

R482
56_0402_5%~D

1

2

56_0402_1%~D

H_DPRSTP# 8,10,48
H_DPSLP# 8

SIO_A20GATE

SIO_RCIN#

H_FERR#

10K_0402_5%~D

10K_0402_5%~D

56_0402_5%~D

DELL CONFIDENTIAL/PROPRIETARY

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

ICH8(2/4)

LA-3302P

1

R465

R466

R468

+3.3V_RUN

12

12

+1.05V_VCCP

12

22 66Thursday, March 01, 2007

0.4

of

5

+3.3V_RUN

R411 2.2K_0402_5%~D@
R524 10K_0402_5%~D@
R497 10K_0402_5%~D
R504 10K_0402_5%~D

1 2

R523 10K_0402_5%~D

1 2

R528 10K_0402_5%~D

1 2

D D

R115 1K_0402_5%~D@

1 2
1 2

IMVP_PWRGD
MCH_ICH_SYNC#
RSV_THRM#

12

IRQ_SERIRQ

12

RSVD_GPIO39
RSVD_GPIO48
SPKR

No Reboot Strap

Low = Default

SPKR

+3.3V_SUS

1 2

R514 10K_0402_5%~D@

1 2

R503 10K_0402_5%~D

@

R502 10K_0402_5%~D

@

1 2

R506 10K_0402_5%~D

1 2

R516 10K_0402_5%~D

1 2

R521 1K_0402_5%~D

1 2

R498 2.2K_0402_5%~D

1 2

R499 2.2K_0402_5%~D

1 2

R690 8.2K_0402_5%~D

1 2

R807 10K_0402_5%~D

ICH_CL_RST1#
ICH_SMLINK0
ICH_SMLINK1

12

ICH_RI#
SIO_EXT_SCI#
ICH_PCIE_W AKE#
ICH_SMBCLK
ICH_SMBDATA
EC_ME_ALERT
LOM_ICH_SMBALERT#

High = No Reboot

+3.3V_SUS

SIO_EXT_SMI#

1 2

R509 10K_0402_5%~D

+3.3V_RUN

12

R505

8.2K_0402_5%~D

C C

CLKRUN#

12

R508
10_0402_5%~D

@

Option to " Disable "
clkrun. Pulling it
down
will keep the clks
running.

MiniWWAN (Mini Card 1)--->

MiniWLAN (Mini Card 2)--->

USB_OC0_1#

B B

USB_OC2_3#
USB_OC4#
USB_OC5#

USB_OC6#
USB_OC8#
USB_OC9#
USB_OC7#

RP1

4 5
3 6
2 7
1 8

10K_1206_8P4R_5%~D

RP2

4 5
3 6
2 7
1 8

10K_1206_8P4R_5%~D

GIGA LAN --->

+3.3V_RUN

A A

ICH_SMBDATA

+3.3V_RUN

ICH_SMBCLK

D

1 3

2
2

1 3

D

5

G

G

USB_IDE#25

SIO_EXT_WAKE#38

PCIE_MCARD1_DET#34

USB_MCARD1_DET#34

USB_MCARD2_DET#34

+3.3V_SUS

12

12

R99

R278

2.2K_0402_5%~D

2.2K_0402_5%~D

S

Q21
2N7002W-7-F_SOT323-3~D

S

Q27
2N7002W-7-F_SOT323-3~D

MEM_SDATA

MEM_SCLK

1

1

1

C874

47P_0402_50V8J~D

2

2

2

@

PCIE_IRX_WANTX_N134
PCIE_IRX_WANTX_P134
PCIE_ITX_WANRX_N1_C34
PCIE_ITX_WANRX_P1_C34

PCIE_IRX_WLANTX_N234
PCIE_IRX_WLANTX_P234
PCIE_ITX_WLANRX_N2_C34
PCIE_ITX_WLANRX_P2_C34

PCIE_RX6-/GLAN_RX-28
PCIE_RX6+/GLAN_RX+28
PCIE_TX6-/GLAN_TX-28
PCIE_TX6+/GLAN_TX+28

C875 47P_0402_50V8J~D

@

ICH_EC_SPI_CLK39

ICH_SPI_CS0#39
ICH_SPI_CS1#21

ICH_EC_SPI_DO39

ICH_EC_SPI_DIN39

C876 47P_0402_50V8J~D

@

MEM_SDATA 16,17

MEM_SCLK 16,17

1

2

C877 47P_0402_50V8J~D

C878 47P_0402_50V8J~D

@

@

0_0603_5%~D

1 2

1 2

R817 0_0603_5%~D
R819 0_0603_5%~D

1 2

1 2

R820 4.7K_0603_5%~D

1 2

R818 0_0603_5%~D

1

2

ICH_EC_SPI_CLK
ICH_SPI_CS0#
ICH_SPI_CS1#

ICH_EC_SPI_DO
ICH_EC_SPI_DIN

4

ICH_SMBCLK28,34

ICH_SMBDATA28,34

ITP_DBRESET#7,38

PM_BMBUSY#10

LOM_SMB_ALERT#28,39

R816

C664 0.1U_0402_10V7K~D

1 2

C666 0.1U_0402_10V7K~D

1 2

C667 0.1U_0402_10V7K~D

1 2

C668 0.1U_0402_10V7K~D

1 2

C669 0.1U_0402_10V7K~D

1 2

C670 0.1U_0402_10V7K~D

1 2

1 2

R793 0_0402_5%~D@

H_STP_PCI#6
H_STP_CPU#6

CLKRUN#30,38,39

ICH_PCIE_WAKE#38

IRQ_SERIRQ28,30,38,39

IMVP_PWRGD39,42,48

SIO_EXT_SMI#39

SIO_EXT_SCI#39

IDE_RST_MOD25

SATA_CLKREQ#6

PLTRST_DELAY#52

MCH_ICH_SYNC#10

ICH_RSVD22

R530 15_0402_5%~D

1 2

R531 15_0402_5%~D

1 2

R532 15_0402_5%~D

1 2

R763 15_0402_5%~D

1 2

USB_OC0_1#32
USB_OC2_3#32

4

LOM_ICH_SMBALERT#

T15PAD~D

T24PAD~D

T14PAD~D

SPKR26

PCIE_IRX_WANTX_N1
PCIE_IRX_WANTX_P1
PCIE_ITX_WANRX_N1
PCIE_ITX_WANRX_P1

PCIE_IRX_WLANTX_N2
PCIE_IRX_WLANTX_P2
PCIE_ITX_WLANRX_N2
PCIE_ITX_WLANRX_P2

PCIE_RX6-/GLAN_RX­PCIE_RX6+/GLAN_RX+
GLAN_TXN_C
GLAN_TXP_C

ICH_SMBCLK
ICH_SMBDATA
ICH_CL_RST1#
ICH_SMLINK0
ICH_SMLINK1

ICH_RI#

ITP_DBRESET#
PM_BMBUSY#

H_STP_PCI#
H_STP_CPU#

CLKRUN#
ICH_PCIE_W AKE#

IRQ_SERIRQ
RSV_THRM#

IMVP_PWRGD
ICH_TP7

SIO_EXT_SMI#
SIO_EXT_SCI#

RSVD_GPIO27
IDE_RST_MOD
SATA_CLKREQ#
PLTRST_DELAY#
RSVD_GPIO39
RSVD_GPIO48

SPKR
MCH_ICH_SYNC#
ICH_RSVD

USB_OC0_1#
USB_OC2_3#
USB_OC4#

USB_OC5#
USB_OC6#
USB_OC7#
USB_OC8#
USB_OC9#

U32C

AJ26

SMBCLK

AD19

SMBDATA

AG21

LINKALERT#

AC17

SMLINK0

AE19

SMLINK1

AF17

RI#

F4

SUS_STAT#/LPCPD#

AD15

SYS_RESET#

AG12

BMBUSY#/GPIO0

AG22

SMBALERT#/GPIO11

AE20

STP_PCI#/GPIO15

AG18

STP_CPU#/GPIO25

AH11

CLKRUN#/GPIO32

AE17

WAKE#

AF12

SERIRQ

AC13

THRM#

AJ20

VRMPWRGD

AJ22

TP7

AJ8

TACH1/GPIO1

AJ9

TACH2/GPIO6

AH9

TACH3/GPIO7

AE16

GPIO8

AC19

GPIO12

AG8

TACH0/GPIO17

AH12

GPIO18

AE11

GPIO20

AG10

SCLOCK/GPIO22

AH25

QRT_STATE0/GPIO27

AD16

QRT_STATE1/GPIO28

AG13

SATACLKREQ#/GPIO35

AF9

SLOAD/GPIO38

AJ11

SDATAOUT0/GPIO39

AD10

SDATAOUT1/GPIO48

AD9

SPKR

AJ13

MCH_SYNC#

AJ21

TP3

U32D

P27

PERN1

P26

PERP1

N29

PETN1

N28

PETP1

M27

PERN2

M26

PERP2

L29

PETN2

L28

PETP2

K27

PERN3

K26

PERP3

J29

PETN3

J28

PETP3

H27

PERN4

H26

PERP4

G29

PETN4

G28

PETP4

F27

PERN5

F26

PERP5

E29

PETN5

E28

PETP5

D27

PERN6/GLAN_RXN

D26

PERP6/GLAN_RXP

C29

PETN6/GLAN_TXN

C28

PETP6/GLAN_TXP

C23

SPI_CLK

B23

SPI_CS0#

E22

SPI_CS1#

D23

SPI_MOSI

F21

SPI_MISO

AJ19

OC0#

AG16

OC1#/GPIO40

AG15

OC2#/GPIO41

AE15

OC3#/GPIO42

AF15

OC4#/GPIO43

AG17

OC5#/GPIO29

AD12

OC6#/GPIO30

AJ18

OC7#/GPIO31

AD14

OC8#

AH18

OC9#

3

+3.3V_RUN

8.2K_0402_5%~D

12

R500

CLK14

CLK48
SUSCLK
SLP_S3#

SLP_S4#
SLP_S5#

PWROK

BATLOW#
PWRBTN#

LAN_RST#

RSMRST#

CLPWROK

SLP_M#

CL_CLK0
CL_CLK1

CL_DATA0
CL_DATA1

CL_VREF0
CL_VREF1

CL_RST#

V27
V26
U29
U28

Y27
Y26
W29
W28

AB26
AB25
AA29
AA28

AD27
AD26
AC29
AC28

T26
T25

Y23
Y24

G3
G2
H5
H4
H2
H1
J3
J2
K5
K4
K2
K1
L3
L2
M5
M4
M2
M1
N3
N2

F2
F3

AJ12
AJ10
AF11
AG11

AG9
G5

D3
AG23

AF21
AD18

AH27
AE23
AJ14
AE21
C2
AH20
AG27
E1
E3
AJ25
F23

AE18
F22

AF19
D24

AH23
AJ23
AJ27

AJ24
AF22
AG19

DMI_MTX_IRX_N0
DMI_MTX_IRX_P0
DMI_MRX_ITX_N0
DMI_MRX_ITX_P0

DMI_MTX_IRX_N1
DMI_MTX_IRX_P1
DMI_MRX_ITX_N1
DMI_MRX_ITX_P1

DMI_MTX_IRX_N2
DMI_MTX_IRX_P2
DMI_MRX_ITX_N2
DMI_MRX_ITX_P2

DMI_MTX_IRX_N3
DMI_MTX_IRX_P3
DMI_MRX_ITX_N3
DMI_MRX_ITX_P3

CLK_PCIE_ICH#
CLK_PCIE_ICH

DMI_IRCOMP
USBP0-

USBP0+
USBP1­USBP1+
USBP2­USBP2+
USBP3­USBP3+
USBP4­USBP4+
USBP5­USBP5+
USBP6­USBP6+
USBP7­USBP7+
USBP8­USBP8+
USBP9­USBP9+

USBRBIAS

CLK_ICH_14M
CLK_ICH_48M

ICH_SUSCLK
SIO_SLP_S3#
SIO_SLP_S5#

ICH_PWRGD
DPRSLPVR
ICH_BATLOW#

R518 8.2K_0402_5%~D

SIO_PWRBTN#
ICH_LAN_RST#
ICH_RSMRST#
CLK_PWRGD
ICH_CL_PWROK

CL_CLK0

CL_DATA0

CL_VREF0_ICH

CL_RST0#

EC_ME_ALERT

DMI_MTX_IRX_N0 10
DMI_MTX_IRX_P0 10
DMI_MRX_ITX_N0 10
DMI_MRX_ITX_P0 10

DMI_MTX_IRX_N1 10
DMI_MTX_IRX_P1 10
DMI_MRX_ITX_N1 10
DMI_MRX_ITX_P1 10

DMI_MTX_IRX_N2 10
DMI_MTX_IRX_P2 10
DMI_MRX_ITX_N2 10
DMI_MRX_ITX_P2 10

DMI_MTX_IRX_N3 10
DMI_MTX_IRX_P3 10
DMI_MRX_ITX_N3 10
DMI_MRX_ITX_P3 10

CLK_PCIE_ICH# 6
CLK_PCIE_ICH 6

USBP0- 32
USBP0+ 32
USBP1- 32

USBP1+ 32

USBP2- 32

USBP2+ 32

USBP3- 32

USBP3+ 32

USBP4- 31

USBP4+ 31

USBP5- 40

USBP5+ 40

USBP6- 30

USBP6+ 30

USBP7- 40

USBP7+ 40

USBP8- 36

USBP8+ 36

USBP9- 34

USBP9+ 34

1 2

R533 22.6_0402_1%~D

Within 500 mils

SATA0GP/GPIO21
SATA1GP/GPIO19
SATA2GP/GPIO36
SATA3GP/GPIO37

SMB

SATA

GPIO

clocks

S4_STATE#/GPIO26

DPRSLPVR/GPIO16

SYS / GPIOGPIOMISC

Power MGT

CK_PWRGD

MEM_LED/GPIO24
ME_EC_ALERT/GPIO10
EC_ME_ALERT/GPIO14

WOL_EN/GPIO9

Controller Link

ICH8M_BGA676~D

DMI0RXN
DMI0RXP

DMI0TXN
DMI0TXP

DMI1RXN
DMI1RXP

DMI1TXN
DMI1TXP

DMI2RXN
DMI2RXP

DMI2TXN
DMI2TXP

DMI3RXN
DMI3RXP

DMI3TXN
DMI3TXP

DMI_CLKN

PCI - Express

DMI_CLKP

Direct Media Interface

DMI_ZCOMP

DMI_IRCOMP

USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4N

SPI

USBP4P
USBP5N
USBP5P

ICH8M_BGA676~D

3

USBP6N
USBP6P
USBP7N
USBP7P
USBP8N
USBP8P
USBP9N
USBP9P

USBRBIAS#

USBRBIAS

USB

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

2

CLK_ICH_14M 6
CLK_ICH_48M 6

T13 PAD~D

SIO_SLP_S3# 39

SIO_SLP_S5# 39

ICH_PWRGD 10,42

DPRSLPVR 10,48

12

CL_CLK0 10

CL_DATA0 10

T86 PAD~D

Within 500 mils

R529 24.9_0402_1%~D

+3.3V_SUS

1 2

SIO_PWRBTN# 39

ICH_RSMRST# 39

CLK_PWRGD 6

ICH_CL_PWROK 10,39

CL_RST0# 10

----->Side Top

----->Side Bottom

----->Rear Left

----->Rear Right

----->Smart Card

----->Biometric

----->Card Bus

----->Blue Tooth

----->Dock

----->WWAN

2

ICH_CL_PWROK

ICH_LAN_RST#

DPRSLPVR

ICH_PWRGD

ICH_RSMRST#

1

1 2

R42 1M_0402_1%~D

1 2

R834 10K_0402_5%~D

1 2

R501 100K_0402_5%~D

1 2

R512 10K_0402_5%~D

1 2

R515 10K_0402_5%~D

Place closely pin U19.AC1

CLK_ICH_14M

12

R510

10_0402_5%~D@

1

C661

4.7P_0402_50V8C~D@

2

Place closely pin U19.B2

CLK_ICH_48M

12

R520

10_0402_5%~D@

1

C663

4.7P_0402_50V8C~D@

2

3.24K_0402_1%~D

CL_VREF0_ICH

1

+1.5V_RUN_PCIE_ICH

C662

2

DELL CONFIDENTIAL/PROPRIETARY

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

ICH8(3/4)

LA-3302P

1

R519

0.1U_0402_16V4Z~D

23 66Thursday, March 01, 2007

+3.3V_RUN

12

12

of

R522

453_0402_1%~D

0.4

5

4

3

2

1

+RTC_CELL

0.1U_0402_16V4Z~D

1U_0603_10V4Z~D

+3.3V_RUN+5V_RUN

21

12

R534

100_0402_5%~D

D D

R536

10_0402_5%~D

C C

B B

+3.3V_RUN

A A

D20
RB751V_SOD323~D

1

C675

0.1U_0402_16V4Z~D

2

+3.3V_SUS+5V_SUS

21

12

D21
RB751V_SOD323~D

1

C683

0.1U_0402_16V4Z~D

2

+1.5V_RUN

0_0603_5%~D

1 2

R538 0_0603_5%~D

Place Cap as close
to A24 as possible

ICH_V5REF_RUN

ICH_V5REF_SUS

R537

1 2

+1.5V_RUN

5

+1.5V_RUN

BLM21PG600SN1D_0805~D

10UH_LB2012T100MR_20%_0805~D

+VCCSATAPLLR

0.1U_0402_16V4Z~D

C703

1 2

1 2

1

2

1

2

1

2

1

2

C200

1

2

+1.5V_RUN_PCIE_ICH

L43

220U_D2_4VY_R15M~D

L45

C699

0.1U_0402_16V4Z~D

C700

0.1U_0402_16V4Z~D

C705

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

C671

1

2

+1.5V_RUN_PCIE_ICH

22U_0805_6.3V6M~D

1

+

2

1U_0603_10V4Z~D

C677

1

C676

2

+1.5V_RUN_SATAPLL

1U_0603_10V4Z~D

10U_0805_4VAM~D

C689

1

2

C696

+1.5V_RUN_PCIE_ICH

1

C709

4.7U_0603_6.3V6M~D

2

C672

1

2

22U_0805_6.3V6M~D

C678

1

2

C690

1

2

1

2

C697

1U_0603_10V4Z~D

+1.5V_RUN

TP_VCCLAN1.05_INT_ICH1

T21PAD~D

TP_VCCLAN1.05_INT_ICH2

T22PAD~D

+3.3V_RUN

4

ICH_V5REF_RUN

ICH_V5REF_SUS

2.2U_0603_6.3V6K~D
C679

1

2

1

2

AD25

AA25
AA26
AA27
AB27
AB28
AB29

AC10

D28
D29

G24
H23
H24

M24
M25
N23
N24
N25

R24
R25
R26
R27

U24
U25

W25

AE7
AF7
AG7
AH7

AC1
AC2
AC3
AC4
AC5

AC9
AA5

AA6
G12

G17

AC7
AD7

W23

G18

G20

A16

T7

G4

E25
E26
E27
F24
F25

J23
J24
K24
K25
L23
L24
L25

P24
P25

T23
T24
T27
T28
T29

V23
V24
V25

Y25
AJ6

AJ7

H7

D1

F1
L6

L7
M6
M7

F17

F19

A24
A26

A27
B26
B27
B28

B25

U32F

VCCRTC
V5REF[1]

V5REF[2]
V5REF_SUS
VCC1_5_B[01]

VCC1_5_B[02]
VCC1_5_B[03]
VCC1_5_B[04]
VCC1_5_B[05]
VCC1_5_B[06]
VCC1_5_B[07]
VCC1_5_B[08]
VCC1_5_B[09]
VCC1_5_B[10]
VCC1_5_B[11]
VCC1_5_B[12]
VCC1_5_B[13]
VCC1_5_B[14]
VCC1_5_B[15]
VCC1_5_B[16]
VCC1_5_B[17]
VCC1_5_B[18]
VCC1_5_B[19]
VCC1_5_B[20]
VCC1_5_B[21]
VCC1_5_B[22]
VCC1_5_B[23]
VCC1_5_B[24]
VCC1_5_B[25]
VCC1_5_B[26]
VCC1_5_B[27]
VCC1_5_B[28]
VCC1_5_B[29]
VCC1_5_B[30]
VCC1_5_B[31]
VCC1_5_B[32]
VCC1_5_B[33]
VCC1_5_B[34]
VCC1_5_B[35]
VCC1_5_B[36]
VCC1_5_B[37]
VCC1_5_B[38]
VCC1_5_B[39]
VCC1_5_B[40]
VCC1_5_B[41]
VCC1_5_B[42]
VCC1_5_B[43]
VCC1_5_B[44]
VCC1_5_B[45]
VCC1_5_B[46]

VCCSATAPLL
VCC1_5_A[01]

VCC1_5_A[02]
VCC1_5_A[03]
VCC1_5_A[04]
VCC1_5_A[05]

VCC1_5_A[06]
VCC1_5_A[07]
VCC1_5_A[08]
VCC1_5_A[09]
VCC1_5_A[10]

VCC1_5_A[11]
VCC1_5_A[12]

VCC1_5_A[13]
VCC1_5_A[14]

VCC1_5_A[15]
VCC1_5_A[16]
VCC1_5_A[17]

VCC1_5_A[18]
VCC1_5_A[19]

VCCUSBPLL
VCC1_5_A[20]

VCC1_5_A[21]
VCC1_5_A[22]
VCC1_5_A[23]
VCC1_5_A[24]

VCC1_5_A[25]
VCCLAN1_05[1]

VCCLAN1_05[2]
VCCLAN3_3[1]

VCCLAN3_3[2]
VCCGLANPLL
VCCGLAN1_5[1]

VCCGLAN1_5[2]
VCCGLAN1_5[3]
VCCGLAN1_5[4]
VCCGLAN1_5[5]

VCCGLAN3_3

VCCA3GP

ARX

USB COREATX

GLAN POWER

+1.05V_VCCP

VCCDMIPLL

VCC_DMI[1]
VCC_DMI[2]

VCC3_3[01]
VCC3_3[02]
VCC3_3[03]

VCC3_3[04]
VCC3_3[05]
VCC3_3[06]

VCC3_3[07]
VCC3_3[08]
VCC3_3[09]
VCC3_3[10]
VCC3_3[11]
VCC3_3[12]
VCC3_3[13]

VCC3_3[14]
VCC3_3[15]
VCC3_3[16]
VCC3_3[17]
VCC3_3[18]
VCC3_3[19]
VCC3_3[20]
VCC3_3[21]
VCC3_3[22]
VCC3_3[23]
VCC3_3[24]

VCCHDA

VCCCL1_05

VCCCL1_5

3

A13
B13
C13
C14
D14
E14
F14
G14
L11
L12
L14
L16
L17
L18
M11
M18
P11
P18
T11
T18
U11
U18
V11
V12
V14
V16
V17
V18

R29
AE28

AE29
AC23

AC24
AF29
AD2
AC8

AD8
AE8
AF8

+3.3V_RUN

AA3
U7
V7
W1
W6
W7
Y7

A8
B15
B18
B4
B9
C15
D13
D5
E10
E7
F11

AC12
AD11

TP_VCCSUS1.05_INT_ICH1

J6

TP_VCCSUS1.05_INT_ICH2

AF20

VCCSUS1_5_ICH_1

AC16

VCCSUS1_5_ICH_2

J7
C3
AC18

AC21
AC22
AG20
AH28

P6
P7
C1
N7
P1
P2
P3
P4
P5
R1
R3
R5
R6

VCCCL1_05_ICH

G22
A22
F20

G21

VCC1_05[01]
VCC1_05[02]
VCC1_05[03]
VCC1_05[04]
VCC1_05[05]
VCC1_05[06]
VCC1_05[07]
VCC1_05[08]
VCC1_05[09]
VCC1_05[10]
VCC1_05[11]
VCC1_05[12]
VCC1_05[13]
VCC1_05[14]
VCC1_05[15]
VCC1_05[16]

CORE

VCC1_05[17]
VCC1_05[18]
VCC1_05[19]
VCC1_05[20]
VCC1_05[21]
VCC1_05[22]
VCC1_05[23]
VCC1_05[24]
VCC1_05[25]
VCC1_05[26]
VCC1_05[27]
VCC1_05[28]

V_CPU_IO[1]
V_CPU_IO[2]

VCCP_CORE

IDEPCI

VCCSUSHDA

VCCSUS1_05[1]
VCCSUS1_05[2]

VCCSUS1_5[1]

VCCSUS1_5[2]
VCCSUS3_3[01]
VCCSUS3_3[02]

VCCSUS3_3[03]
VCCSUS3_3[04]
VCCSUS3_3[05]
VCCSUS3_3[06]

VCCPSUS

VCCSUS3_3[07]
VCCSUS3_3[08]
VCCSUS3_3[09]
VCCSUS3_3[10]
VCCSUS3_3[11]
VCCSUS3_3[12]
VCCSUS3_3[13]
VCCSUS3_3[14]
VCCSUS3_3[15]

VCCPUSB

VCCSUS3_3[16]
VCCSUS3_3[17]
VCCSUS3_3[18]
VCCSUS3_3[19]

VCCCL3_3[1]
VCCCL3_3[2]

ICH8M_BGA676~D

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

0.1U_0402_16V4Z~D

C673

1

2

1

C680

2

0.1U_0402_16V4Z~D

+3.3V_RUN

1

C691

0.1U_0402_16V4Z~D

2

0.1U_0402_16V4Z~D

1

C692

2

+3.3V_RUN

0.1U_0402_16V4Z~D

1

2

1

2

0.01U_0402_16V7K~D

C202

1

2

0.1U_0402_16V4Z~D

1

2

T19
T20

+3.3V_SUS

1

2

T23

C681

C693

0.1U_0402_16V4Z~D

+1.05V_VCCP

C674

L44

BLM18PG181SN1_0603~D

1 2

10U_0805_4VAM~D

22U_0805_6.3V6M~D

+1.25V_RUN

C682

1

2

+3.3V_RUN

0.1U_0402_16V4Z~D

1

C694

2

T17PAD~D
T18PAD~D

0.022U_0402_16V7K~D

0.022U_0402_16V7K~D

1

C701

2

C704

D34

2

3

MMBD4148-7-F_SOT23-3~D

R535
1_0603_1%~D

4.7U_0603_6.3V6M~D

C684

1

2

+3.3V_RUN

1

C688

2

0.1U_0402_16V4Z~D

+3.3V_RUN

1

C695

0.1U_0402_16V4Z~D

2

+3.3V_SUS

1

C698

0.1U_0402_16V4Z~D

2

+3.3V_SUS

1

C702

2

0.1U_0402_16V4Z~D

+1.5V_RUN

12

C685

1

2

2

1

+1.05V_VCCP

0.1U_0402_16V4Z~D

C686

1

2

1

2

R182

1 2

10_0805_5%~D

+3.3V_RUN

C687

0.1U_0402_16V4Z~D

+1.5V_RUN

AA2
AA7

AB1
AB24
AC11
AC14
AC25
AC26
AC27
AD17
AD20
AD28
AD29

AD3

AD4

AD6

AE1
AE12

AE2
AE22

AD1
AE25

AE5

AE6

AE9
AF14
AF16
AF18

AF3

AF4

AG5

AG6
AH10
AH13
AH16
AH19

AH2
AF28
AH22
AH24
AH26

AH3

AH4

AH8

C24

C26

C27

D12

D15

D18

G10

G13

G19

G23

G25

G26

G27

H25

H28

H29

U32E

A23

VSS[001]

A5

VSS[002]
VSS[003]
VSS[004]

A25

VSS[005]
VSS[006]
VSS[007]
VSS[008]
VSS[009]
VSS[010]
VSS[011]
VSS[012]
VSS[013]
VSS[014]
VSS[015]
VSS[016]
VSS[017]
VSS[018]
VSS[019]
VSS[020]
VSS[021]
VSS[022]
VSS[023]
VSS[024]
VSS[025]
VSS[026]
VSS[027]
VSS[028]
VSS[029]
VSS[030]
VSS[031]
VSS[032]
VSS[033]
VSS[034]
VSS[035]
VSS[036]
VSS[037]
VSS[038]
VSS[039]
VSS[040]
VSS[041]
VSS[042]
VSS[043]
VSS[044]
VSS[045]
VSS[046]
VSS[047]

AJ5

VSS[048]

B11

VSS[049]

B14

VSS[050]

B17

VSS[051]

B2

VSS[052]

B20

VSS[053]

B22

VSS[054]

B8

VSS[055]
VSS[056]
VSS[057]
VSS[058]

C6

VSS[059]
VSS[060]
VSS[061]
VSS[062]

D2

VSS[063]

D4

VSS[064]

E21

VSS[065]

E24

VSS[066]

E4

VSS[067]

E9

VSS[068]

F15

VSS[069]

E23

VSS[070]

F28

VSS[071]

F29

VSS[072]

F7

VSS[073]

G1

VSS[074]

E2

VSS[075]
VSS[076]
VSS[077]
VSS[078]
VSS[079]
VSS[080]
VSS[081]
VSS[082]
VSS[083]
VSS[084]
VSS[085]

H3

VSS[086]

H6

VSS[087]

J1

VSS[088]

J25

VSS[089]

J26

VSS[090]

J27

VSS[091]

J4

VSS[092]

J5

VSS[093]

K23

VSS[094]

K28

VSS[095]

K29

VSS[096]

K3

VSS[097]

K6

VSS[098]

VSS[099]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
VSS[159]
VSS[160]
VSS[161]
VSS[162]
VSS[163]
VSS[164]
VSS[165]
VSS[166]
VSS[167]
VSS[168]
VSS[169]
VSS[170]
VSS[171]
VSS[172]
VSS[173]
VSS[174]
VSS[175]
VSS[176]
VSS[177]
VSS[178]
VSS[179]
VSS[180]
VSS[181]
VSS[182]
VSS[183]
VSS[184]

VSS_NCTF[01]
VSS_NCTF[02]
VSS_NCTF[03]
VSS_NCTF[04]
VSS_NCTF[05]
VSS_NCTF[06]
VSS_NCTF[07]
VSS_NCTF[08]
VSS_NCTF[09]
VSS_NCTF[10]
VSS_NCTF[11]
VSS_NCTF[12]

ICH8M_BGA676~D

DELL CONFIDENTIAL/PROPRIETARY

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

ICH8(4/4)

LA-3302P

1

K7
L1
L13
L15
L26
L27
L4
L5
M12
M13
M14
M15
M16
M17
M23
M28
M29
M3
N1
N11
N12
N13
N14
N15
N16
N17
N18
N26
N27
N4
N5
N6
P12
P13
P14
P15
P16
P17
P23
P28
P29
R11
R12
R13
R14
R15
R16
R17
R18
R28
R4
T12
T13
T14
T15
T16
T17
T2
U12
U13
U14
U15
U16
U17
U23
U26
U27
U3
U5
V13
V15
V28
V29
W2
W26
W27
Y28
Y29
Y4
AB4
AB23
AB5
AB6
AD5
U4
W24

A1
A2
A28
A29
AH1
AH29
AJ1
AJ2
AJ28
AJ29
B1
B29

24 66Monday, February 26, 2007

0.4

of

5

1

2

D D

6

WF1F068N1A

C C

TOP VIEW

IDE_DD[0..15]22

IDE_RST_MOD23

USB_IDE#23

B B

A A

+3.3V_RUN

3

4

5

IDE_DD[0..15]

IDE_RST_MOD

R230

100K_0402_5%~D

1 2

+3.3V_ALW

IDE_DCS3#22

IDE_DA222
IDE_DA022
IDE_DA122

R205

470_0402_5%~D

1 2

IDE_DIOR#22
IDE_DIOW#22

R209

56_0402_5%~D

1 2

MODPRES#38

1 2

10K_0402_5%~D

R217

+5V_HDD +3.3V_RUN

C145

1000P_0402_50V7K~D

4

IDE_DCS3#
IDE_DA2
IDE_DA0
IDE_DA1

CSEL2
IDE_DIOR#
IDE_DIOW#
IDE_DD15

IDE_DD1
IDE_DD2
IDE_DD12
IDE_DD11

IDE_DD5
IDE_DD6
IDE_DD8
MOD_RST
USB_IDE#

MODPRES#

1

1

C469

2

2

0.1U_0402_16V4Z~D

Pleace near HD CONN

3

JMOD

72

G71G

1

8.3

G69G

1

3

3

5

5

7

7

9

9

11

11

13

13

15

15

17

17

19

19

21

21

23

23

25

25

27

27

29

29

31

31

33

33

IDE_DDACK#_R

35

35

37

37

39

39

41

41

43

43

45

45

47

47

49

49

51

51

53

53

55

55

57

57

59

59

61

61

63

63

65

65

67

67

TYCO_1770530-1~D

70

DASP#

PDIAG#

SC_USBP+
SC_USBP-

IDE_DCS1#

IDE_IRQ

1 2

R392 0_0402_5%~D

IDE_DIORDY

IDE_DDREQ
IDE_DD0
IDE_DD14
IDE_DD13

IDE_DD3
IDE_DD4
IDE_DD10
IDE_DD9

IDE_DD7

C60

10U_0805_10V4Z~D

IDE_DIORDY 22

2

2

4

4

6

6

8

8

10

10

12

12

14

14

16

16

18

18

20

20

22

22

24

24

26

26

28

28

30

30

32

32

34

34

36

36

38

38

40

40

42

42

44

44

46

46

48

48

50

50

52

52

54

54

56

56

58

58

60

60

62

62

64

64

66

66

68

68

1

C268

2

1

C262

2

0.1U_0402_16V4Z~D

SC_USBP+ 31
SC_USBP- 31

IDE_DCS1# 22

IDE_IRQ 22

IDE_DDACK# 22

IDE_DDREQ 22

+5V_MOD

1

2

0.1U_0402_16V4Z~D

R206

4.7K_0402_5%~D

+3.3V_RUN

12

PSATA_IRX_DTX_N0_C22
PSATA_IRX_DTX_P0_C22

close SATA connector

1

C465

10U_0805_10V4Z~D

C466

@

2

0.1U_0402_16V4Z~D

@

1

1

C464

@

2

2

0.1U_0402_10V7K~D

Pleace near HD CONN

2

MODC_EN38

100K_0402_5%~D

100K_0402_5%~D

HDDC_EN38

R692

100K_0402_5%~D

C461

3900P_0402_50V7K~D

C462

3900P_0402_50V7K~D

R618

100K_0402_5%~D

2

G

12

R691

+3.3V_ALW2

12

R626

2N7002W-7-F_SOT323-3~D

13

D

2

G

12

S

PSATA_ITX_DRX_P022

12
12

PSATA_ITX_DRX_N022

+3.3V_ALW2

12

2N7002W-7-F_SOT323-3~D

Q50

2

13

D

S

G

Q68
2N7002W-7-F_SOT323-3~D

HDD PWR

+15V_ALW

12

R627
100K_0402_5%~D

HDD_EN_5V

Q57

13

D

2

G

S

Q69
2N7002W-7-F_SOT323-3~D

+5V_HDD Source

PSATA_IRX_DTX_N0
PSATA_IRX_DTX_P0

+3.3V_RUN

MOD_EN

C812

+5V_ALW

3

1

2

0.1U_0603_50V4Z~D

+15V_ALW

12

R619
100K_0402_5%~D

2

13

D

S

+5VMOD Source

+5V_ALW

6

2

1

G

3

S

4 5

1

1

C818

C817

0.1U_0603_50V4Z~D

PSATA_ITX_DRX_P0
PSATA_ITX_DRX_N0

+5V_HDD

2

2

10U_0805_10V4Z~D

1

6

2

1

D

Q48

G

SI3456BDV-T1-E3_TSOP6~D

S

4 5

1

C813

2

10U_0805_10V4Z~D

D

Q56

SI3456BDV-T1-E3_TSOP6~D

+5V_HDD

12

R629

JSATA

1
2
3
4
5
6
7

8
9

10
11
12
13
14
15
16
17
18
19
20
21
22

TYCO_1775191-1_RV~D

12

PJP2003

1 2

PAD-OPEN 4x4m@

Open

100K_0402_5%~D

GND
RX+
RX­GND
TX­TX+
GND

3.3V

3.3V

3.3V
GND
GND
GND
5V
5V
5V
GND
Reserved
GND
12V
12V
12V

+5V_MOD

1

R622

2

100K_0402_5%~D

GND1
GND2

Main SATA +5V Default

C211

0.01U_0402_16V7K~D

+5V_RUN

23
24

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

DVD MODULE

LA-3302P

25 66Thursday, March 01, 2007

1

0.4

of

5

4

3

2

1

45

+VDDA

2

1

C710

D D

5

SPKR23
BEEP39

1

B

2

A

3

U34 place as close to CODEC as possible

C C

ICH_AZ_CODEC_BITCLK

12

R545
10_0402_5%~D

Close to Pin 6

1

C721
10P_0402_50V8J~D

B B

A A

2

ICH_AZ_CODEC_SDOUT

12

R479
47_0402_5%~D

@

Close to Pin 5

1

C782

0.1U_0402_16V4Z~D

2

@

0.1U_0402_16V4Z~D

2

U34

P

4

Y

G

74AHCT1G86GW_SOT353-5~D

20K_0402_5%~D

1 2

R540

10K_0402_5%~D

1

C714

2

0.1U_0402_16V4Z~D

ICH_AZ_CODEC_SDIN022

12

R541

C759

1000P_0402_50V7K~D

C711

0.1U_0402_10V6K~D

1 2

TRACE>15 mil

R821

100K_0402_5%~D

1 2

1

2

ICH_AZ_CODEC_BITCLK22

1 2

R544 33_0402_5%~D

ICH_AZ_CODEC_SDOUT22
ICH_AZ_CO D EC_SYNC22
ICH_AZ_CODEC_RST#22

AUD_EAPD27

AUD_SPDIF_OUT36

10K_0402_5%~D

AUD_PC_BEEPBEEP1 BEEP2

C715

1U_0603_10V4Z~D

R823

W=30 mil

1

1

C716

C172

2

2

@

10U_0805_10V4Z~D

0.1U_0402_16V4Z~D

ICH_AZ_CODEC_BITCLK
ICH_AC_SDIN0_R

ICH_AZ_CODEC_SDOUT

AUD_EAPD
AUD_SPDIF_OUT

12

single gate TTL

AUD_SENSE_A

12

+3.3V_RUN+3.3V_RUN

+VDDA

1

2

U35

1

DVDD_CORE

9

DVDD_CORE

40

DVDD_CORE/VPP

3

DVDD_IO

6

HDA_BIT_CLK

8

HDA_SDI_CODEC

5

HDA_SDO

10

HDA_SYNC

11

HDA_RST#

STAC9205

43

NC1

44

NC2

45

NC3

46

DMIC_CLK

2

VOL_UP/DMIC0/GPIO1

4

VOL_DN/DMIC1/GPIO2

47

SPDIF_ IN//GPIO0/EAPD

48

SPDIF _OUT

7

DVSS

26

AVSS1

42

AVSS2

49

Thermal PAD GND

QFN 7x7 & LQFP 9x9 colay footprint.

STAC9205X5NBEB1XR_QFN48_COMON~D

AVDD1
AVDD2

SENSE_A
SENSE_B

PORT_A_L
PORT_A_R

VREFOUT_A

PORT_B_L
PORT_B_R

VREFOUT_B

PORT_C_L
PORT_C_R

VREFOUT_C

PORT_D_L
PORT_D_R

PORT_E_L
PORT_E_R

VREFOUT_E/GPIO4

PORT_F_L
PORT_F_R

VREFOUT_F/GPIO3

CD_L

CD_GND

CD_R

PC_BEEP

MONO_OUT

CAP2

VREFFILT

25
38

13
34

39
41
37

21
22
28

23
24
29

35
36

14
15
31

16
17
30

18
19
20

12
32

33
27

1

2

AUD_SENSE_A
AUD_SENSE_B

AUD_LINE_OUT_L
AUD_LINE_OUT_R

DOCK_HP_MUTE#

AUD_PC_BEEP

1

C724

2

C726

10U_0805_10V4Z~D

1U_0603_10V4Z~D

1

2

1

1

C718

C717

2

2

@

10U_0805_10V4Z~D

0.1U_0402_16V4Z~D

AUD_HP_OUT_L 27
AUD_HP_OUT_R 27

AUD_EXT_MIC_L 27
AUD_EXT_MIC_R 27

VREFOUT

AUD_INT_MIC_IN 27

AUD_LINE_OUT_L 27
AUD_LINE_OUT_R 27

DOCK_HP_MUTE# 38

AUD_SPDIF_SHDN 38

C725

10U_0805_10V4Z~D

AUD_HP_NB_ SENSE

2N7002W-7-F_SOT323~D

Q74

R710

39.2K_0402_1%~D

13

D

2

G

S

AUD_SENSE_B

DOCK_HP_MUTE#

AUD_SPDIF_SHDN

5.11K_0402_1%~D

20K_0402_1%~D

12

R711

13

D

2

G

Q75

S

2N7002W-7-F_SOT323~D

10K_0402_5%~D

R546 10K_0402_5%~D

R547 10K_0402_5%~D

31

+VDDA

R542

12

1

C713

2

1000P_0402_50V7K~D

AUD_MIC_SWITCH 27AUD_HP_NB_SENSE27,38

R543

+VDDA

12

12

12

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.
Azalia (HD) Codec

LA-3302P

26 66Thursday, March 01, 2007

1

0.4

of

5

+VDDA

+VDDA

D D

C C

LM358DR2G_SOIC8~D

AUD_MIC_BIAS

Speaker Connector

INT_SPK_R1
INT_SPK_R2

U36A

1

O

15 mils trace

1

C740

2

@

100P_0402_50V8J~D

+5V_SPK+AMP

R571

Q43

+5V_SPK+AMP

1 2

13

2

G

13

2

G

5

12

D

S

D

S

B B

A A

For TPA6040A,pop
R714,depop R713

AUDIO_AVDD_ON AUD_AMP_MUTE#

1 2

R714

@

0_0402_5%~D

100K_0402_5%~D

AUD_SPK_ENABLE#

AUD_EAPD26

2N7002W-7-F_SOT323-3~D

NB_MUTE#38

12

R556
100K_0402_5%~D

3
2

1

2

100P_0402_50V8J~D

12

R712
100K_0402_5%~D

12

R559

100K_0402_5%~D

8

P

IN+

IN-

G

4

C741

@

R713
100K_0402_5%~D

Q42
2N7002W-7-F_SOT323-3~D

1

C732

2.2U_0805_10V6K~D

2

JSPK

1

1

2

2

MOLEX_53398-0271~D

AUD_LINE_OUT_L26

AUD_LINE_OUT_R26

AUD_HP_OUT_L26

AUD_HP_OUT_R26

AUD_HP_NB_ SENSE
NB_MUTE#

C77 0.033U_1206_50V7K~D

C748 0.033U_1206_50V7K~D

C749 1U_1206_25V7K~D

1 2

C751 1U_1206_25V7K~D

1 2

+5V_SPK+AMP

5

2

P

A

1

B

G

3

AUD_EAPD

10P_0402_50V8J~D

4

C729

2.2U_0805_10V6K~D

AUD_INT_MIC+32
AUD_INT_MIC-32

C737

2.2U_0805_10V6K~D

12

12

1

C906

C905

2

@

@

U40

4

Y

74AHCT1G08GW_SOT353-5~D

@

10_0402_5%~D

C232

@

R790

47P_0402_50V8J~D

47P_0402_50V8J~D

12

1

2

4

+VDDA

12

12

12

12

12

12

1

1

C907

2

2

@

47P_0402_50V8J~D

+5V_SPK+AMP

R553
1K_0402_5%~D

R558
1K_0402_5%~D

C731

0.1U_0402_10V6K~D

1 2
1 2

C736

0.1U_0402_10V6K~D

R566
1K_0402_5%~D

R568
1K_0402_5%~D

1

C96

2

@

47P_0402_50V8J~D

1

C753

2

10U_0805_10V4Z~D

3

R554

0_0402_5%~D

R560

10K_0402_5%~D

1 2
1 2

R563

10K_0402_5%~D

5
6

100K_0402_5%~D

Place Close to Audio Chip Place C lose to Audio Chip

1

C742

C743

2

1U_0603_10V4Z~D

SPKR_INL_C INT_SPK_R1

SPKR_INR_C

HP_INL_C

HP_INR_C

12

C752 1U_0603_10V4Z~D

AUD_SPK_ENABLE#

AUD_AMP_MUTE#

C754

1

1U_0603_10V4Z~D

2

12

1

R822

C755

2

1M_0402_1%~D

AUD_MIC_BIAS

1 2

+VDDA

U36B

8

LM358DR2G_SOIC8~D

P

IN+

7

1 2

O

IN-

G

4

1 2

R565

1

C783

2

1U_0603_10V4Z~D

C1P
C1N

1U_0603_10V4Z~D

C733

0.1U_0805_25V7K~D

1

2

U37

0.1U_0402_16V4Z~D

3

SPKR_INL

2

SPKR_INR

27

HP_INL

26

HP_INR

24

BIAS

23

SPKR_EN#

22

HP_EN

25

MUTE#

17

HPVDD

9

CPVDD

10

C1P

12

C1N

11

CPGND

C758

12

1U_0603_10V4Z~D

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

AUD_EXT_MIC_L26

AUD_EXT_MIC_R26

AUD_INT_MIC_IN 26

BLM21PG600SN1D_0805~D

8

30

VDD

MAX9789A

CPVSS13PVSS

GND

EP

5

14

28

33

MAX9789A_TQFN32~D

L51

1 2

+5V_SPK+AMP

18

PVDD1

PVDD2

OUTL+

OUTL-

OUTR+

OUTR-

GAIN1
GAIN2

REGEN

VOUT

PGND221PGND1

HPL

HPR

SET

5.1_0402_1%~D

5.1_0402_1%~D

+5V_RUN

1

2

6

7

20

19

16

15

31
32

4

29

SET

1

12

R584

For
TPA6040A,
pop
C304,depop
R584

R555

R557

AUD_MIC_SWITCH26

HP_SPK_L1 HP_SPK_L2

W=40mils

1

C745

C744

2

1U_0603_10V4Z~D

10U_0805_10V4Z~D

INT_SPK_R2

HP_SPK_L1

HP_SPK_R1

AUD_GAIN1
AUD_GAIN2

For TPA6040A, po p C301,depop R585

R585 0_0402_5%~D

1 2

1 2

C301

@

0.033U_1206_50V7K~D

1

C304

2

@

0_0402_5%~D

0.033U_1206_50V7K~D

2

VREFOUT

C728

1U_0603_10V6K~D

MIC_L1 MIC_L2

12

1 2

MIC_R1

12

1 2

C730

1U_0603_10V6K~D

+3.3V_RUN

12

R564

BLM18BD121SN1D_0603~D

BLM18BD121SN1D_0603~D

+5V_SPK+AMP

1

1

C747

C746

2

2

1U_0603_10V4Z~D

10U_0805_10V4Z~D

1

1

C756

C757

2

2

1U_0603_10V4Z~D

1U_0603_10V4Z~D

2

1 2

R580

0_0402_5%~D

R796 0_0402_5%~D

MIC_R2

R797 0_0402_5%~D

100K_0402_5%~D

L49

12
12

L50

1

C738

2

100P_0402_50V8J~D

AUDIO_AVDD_ON 18

+VDDA

MINIMAM 150 mA

1

C735

2

100P_0402_50V8J~D

+3.3V_RUN

12

12

1

12

Gain Setting

R569
100K_0402_5%~D

R572
100K_0402_5%~D@

1
2
6
3

4
5

7
8

1
2
6
3

4
5

7
8

VREFOUT_R

R551

4.7K_0402_5%~D

12

12

R561

@

20K_0402_1%~D

C739

100P_0402_50V8J~D

12

12

1

2

C727

1 2

10U_0805_10V4Z~D

12

R552

4.7K_0402_5%~D

L47

BLM18BD601SN1D_0603~D

12

12

L48

BLM18BD601SN1D_0603~D

12

R562

@

20K_0402_1%~D

100K_0402_5%~D

HP_SPK_R2HP_SPK_R1

AUD_HP_NB_SENSE26,38

AUD_GAIN1
AUD_GAIN2

C734

1

2

100P_0402_50V8J~D

R567

+5V_SPK+AMP

GAIN1 INPUTAV(inv)GAIN2

0

0

1

*

6dB

0

1

10dB

15.6dB

0

21.6dB

11

DELL CONFIDENTIAL/PROPRIETARY

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.
AMP and PHONE JACK

LA-3302P

1

JMIC

FOX_JA9033L-B1N6-7F~D

JAUDIO

FOX_JA9033L-B1N6-7F~D

12

R570
100K_0402_5%~D@

12

R573
100K_0402_5%~D

IMPEDANCE

82K ohm

66K ohm

45K ohm

26K ohm

27 66Wednesday, March 07, 2007

of

0.4

5

Layout Notice : Place as close

TPM_GPIO0
TPM_GPIO1
TPM_GPIO2

2

C862

1

C836

4.7U_0603_6.3V4Z~D

+3.3V_LAN

XTALO

XTALI

22P_0402_50V8J~D

2

1

chip as possible.

2

2

C838

C837

1

1

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

R415

4.7K_0402_5%~D

4.7K_0402_5%~D

12
12

R421

U38A

J8

LCLK

J7

LAD0

L10

LAD1

J5

LAD2

K9

LAD3

J9

LFRAME

M10

LRESET

H7

SERIRQ

G4

TPM_GPIO0

J3

TPM_GPIO1

H3

TPM_GPIO2/TPM_STATUS

J6

TPM_EN

H9

GPIO0

H11

GPIO1_SERIAL_DI

C5

GPIO2_SERIAL_DO

C4

EnergyDet

C8

SMB_CLK

C7

SMB_DATA

C9

SCLK

E10

SI

D9

SO

C10

CS

M2

NV_STRAP0

M1

NV_STRAP1

A9

LINKLED

B9

SPD100LED

A10

SPD1000LED

B8

TRAFFICLED

M9

XTALO

L9

XTALI

2

C839

C840

1

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

GPIO1_SERIAL_DI
LOM_LOW_PWR

BCM5755M

LPC/TPM

GPIO

SMBUS

SPI

LED

Clock

Layout Notice : No high
speed signal should be
routed near RDAC or on
adjacent layer to RDAC

2

1

+3.3V_ALW

Q44

SI3456BDV-T1-E3_TSOP6~D

2

2

C316

C309

1

1

D D

0.1U_0402_16V4Z~D

4.7U_0603_6.3V4Z~D

ENAB_3VLAN41

Place closely pin J8

33_0402_5%~D

22P_0402_50V8J~D

CLK_PCI_TPM6

LPC_LAD[0..3]22,38,39

C C

R646 10K_0402_5%~D

@

R648 10K_0402_5%~D

@

R649 10K_0402_5%~D

@

LOM_TPM_EN#38

LOM_SMB_ALERT#23,39

LOM_CABLE_DETECT38

R646, R648, R649 Reserved for
BCM5752 as back-up solution

+3.3V_LAN

B B

A A

LOM_CABLE_DETECT goes to an input on a system microcontroller that can
poll this signal periodically and can de-assert the LOM_LOW_PWR when
LOM_CABLE_DETECT signal is high. Connect to an EC GPIOC defined by the
GPIO mapping.

@

4.7K_0402_5%~D

LOM_SPD10LED_GRN#29

LOM_SPD100LED_ORG#29

25MHZ_18PF_1BX25000CK1D~D

2

C861

Need to ensure

1

crystal at least
300uW max power

22P_0402_50V8J~D

drive-level

D

6

S

45
2
1

CLK_PCI_TPM

R654

@

C854

LPC_LFRAME#22,38,39
PLTRST3#21,34
IRQ_SERIRQ23,30,38,39

R651 0_0402_5%~D

R653 4.7K_0402_5%~D@

LOM_LOW_PWR GPIO2_SERIAL_DO

R655

1 2

LOM_ACTLED_YEL#29

200_0402_1%~D

1 2

Y5

G

3

12

1

2

@

12
12
12
12

12

LOM_SMB_ALERT#
GPIO1_SERIAL_DI

1 2

R422
1K_0402_5%~D

ICH_SMBCLK23,34
ICH_SMBDATA23,34

LOM_SCLK
LOM_SI
LOM_SO
LOM_CS#
NV_STRAP0

LOM_SPD10LED_GRN#
LOM_SPD100LED_ORG#

LOM_ACTLED_YEL#

R659

12

5

CLK_PCI_TPM
LPC_LAD0

LPC_LAD1
LPC_LAD2
LPC_LAD3

LPC_LFRAME#
PLTRST3#
IRQ_SERIRQ

4

MMJT9435

C

2

B

1C4

+3.3V_LAN

R7, R9 are 1/2 W rating

Media

LOW_PWR

Super_Low_PWR

VMAINPRSNT

VAUXPRSNT

Control

PowerPCI-ETEST

REGSUP12
REGCTL12

REGSEN12
REGSUP25
REGCTL25

REGSEN25

Control

Regulator

PCIE_TXDN
PCIE_TXDP

PCIE_RXDN

PCIE_RXDP

REFCLK+

CLKREQ#

REFCLK_SEL

GPHY_TVCOI

Bias

BCM5755M_FBGA144~D

REGCTL_PNP12

@

0.047U_0402_16V4Z~D

B11

TRD3+

B12

TRD3-

C11

TRD2+

C12

TRD2-

D11

TRD1+

D12

TRD1-

E11

TRD0+

E12

TRD0-

H4
K5

G11
B6

K12
J11

J12
L12
M11

M12

M3
L3
L7
M7
A4

WAKE

L5

REFCLK-

M5
F2
B3
B1

PERST

B5

TCK

F3

TDI

B4

TDO

E3

TMS

D4

TRST

C6
J1

NC

M4

NC

A8

RDAC

4

GLAN_RXN_C
GLAN_RXP_C

E

3

1

1

C772

2

LAN_TX3+

LAN_TX3+ 29

LAN_TX3-

LAN_TX3- 29

LAN_TX2+

LAN_TX2+ 29

LAN_TX2-

LAN_TX2- 29

LAN_TX1+

LAN_TX1+ 29

LAN_TX1-

LAN_TX1- 29

LAN_TX0+

LAN_TX0+ 29

LAN_TX0-

LAN_TX0- 29

0_0402_5%~D@
R488

1 2

R650 1K_0402_5%~D
R652 1K_0402_5%~D

REGCTL_PNP12

REGCTL_PNP25

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

PCIE_WAKE#
CLK_PCIE_LOM#
CLK_PCIE_LOM

1 2

R656 0_0402_5%~D

1 2

R657 4.7K_0402_5%~D@

LOM_RST_R#

PHYTVCOI

R669

1 2

R658

@

4.7K_0402_5%~D

1 2

1 2

R666 0_0402_5%~D@

Monitor GPHY PLL Clk

1 2

R663

@

4.7K_0402_5%~D

1.13K_0402_1%~D

R663 Reserved for
BCM5752 as back-up
solution

+3.3V_LAN

12

R643

2_1210_5%~D

Q71
PBSS5540Z_SOT223-3~D

2 3

4

LOM_LOW_PWR 38

12
12

C851

1 2
1 2

C853

PCIE_WAKE# 34,38
CLK_PCIE_LOM# 6
CLK_PCIE_LOM 6

12
12

+3.3V_LAN

0.1U_0402_16V4Z~D

12

R644

2_1210_5%~D

1

C845

2

+3.3V_RUN
+3.3V_LAN

+3.3V_LAN

+1.2V_LAN
+3.3V_LAN

+2.5V_LAN

PCIE_RX6-/GLAN_RX- 23
PCIE_RX6+/GLAN_RX+ 23
PCIE_TX6-/GLAN_TX- 23
PCIE_TX6+/GLAN_TX+ 23

LOM_CLKREQ# 6

PLTRST3#

R5810_0402_5%~D

SB_LOM_PCIE_RST# 21

PLTRST3# 21,34

Place R666 as
close to the ASIC
as possible. Pad
is needed to
measure 125MHz
clock for
debugging

R5820_0402_5%~D @

3

4.7U_0603_6.3V4Z~D

1

1

C826

C827

2

2

+2.5V_LAN

+1.2V_LAN

0.1U_0402_16V4Z~D

10U_0805_10V4Z~D

1

C846

2

Logic High Voltage must
be 0.7V to 2.75V

R647

20K_0402_5%~D

12

12

R276
39K_0402_5%~D

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

L63

BK2125LM182-T_0805~D

0.1U_0402_16V4Z~D

L64

BK1608LM182-T_0603~D

0.1U_0402_16V4Z~D

L65

BK2125LM182-T_0805~D

0.1U_0402_16V4Z~D

LOM_SUPER_IDDQ 38

+3.3V_LAN

LOM_SI

0.1U_0402_16V4Z~D

C865

2

1

12

C849

12

C850

12

C852

MBT35200MT1G_TSOP6~D

REGCTL_PNP25

+XTALVDD

1

2

+BIASVDD

1

2

+AVDD

1

2

+1.2V_LAN

L66

BK1608LM182-T_0603~D

C855

4.7U_0603_6.3V4Z~D

L67

BK1608LM182-T_0603~D

C857

4.7U_0603_6.3V4Z~D

L68

BK1608LM182-T_0603~D

C859

4.7U_0603_6.3V4Z~D

L88

BK1608LM182-T_0603~D

C863

@

4.7U_0603_6.3V4Z~D

U44

8
7
6
5

M45PE20-VMN6TP_SO8~D

8
7
6
5

AT45BCM021B-SU_SO8~D

Q
VSS
VCC
W#

SO
GND
VCC
WP#

RESET#

@

SCK

RESET#

CS#

D
C

S#

U45

SI

1

C771

2

@

12

1

2

12

1

2

12

1

2

12

1

2

1
2
3
4

1
2
3
4

Q70

3

0.047U_0402_16V4Z~D

+2.5V_LAN

C847

+3.3V_LAN

R665

@

4.7K_0402_5%~D

LOM_SO
LOM_SCLK

LOM_CS#

1

2

1

2

1

2

1

2

2

+3.3V_LAN

41

256

0.1U_0402_16V4Z~D

1

C848

2

+AVDDL

C856

0.1U_0402_16V4Z~D

+GPHY_PLLVDD

C858

0.1U_0402_16V4Z~D

+PCIE_PLLVDD

C860

0.1U_0402_16V4Z~D

+PCIE_SDS_VDD

C864

@

0.1U_0402_16V4Z~D

12

12

R664

@

4.7K_0402_5%~D

2

0.1U_0402_16V4Z~D

1

2

0.1U_0402_16V4Z~D

1

C842

2

0.1U_0402_16V4Z~D

1

2

12

R670

@

4.7K_0402_5%~D

4.7U_0603_6.3V4Z~D

1

C824

C825

2

+2.5V_LAN

10U_0805_10V4Z~D

1

C843

2

+3.3V_LAN

+2.5V_LAN

+XTALVDD

+PCIE_SDS_VDD

+BIASVDD

+AVDDL

+AVDD

+PCIE_PLLVDD
+GPHY_PLLVDD

(Default)

Atmel AT45BCM021B

ST M45PE20

1

Layout Notice : 1.2V filter. Place as close
chip as possible.

+1.2V_LAN

C828

2

1

0.1U_0402_16V4Z~D

D10
G10

L11

H12

A12

F10
F11

A11
F12

G12

2

C829

1

0.1U_0402_16V4Z~D

U38B

D5

VDDC_0

D6

VDDC_1

D7

VDDC_2

D8

VDDC_3

H5

VDDC_4

H6

VDDC_5

H8

VDDC_6

J4

VDDC_7

Digial power

A3

VDDIO_0

C2

VDDIO_1
VDDIO_2

F1

VDDIO_3
VDDIO_4

J2

VDDIO_5

L1

VDDIO_6

A5

VDDP_0

G3

VDDP_1
VDDP_2

XTALVDD

K4

PCIE_SDSVDD

BIASVDD

AVDDL_0
AVDDL_1

AVDD_0
AVDD_1

K6

PCIE_PLLVDD
GPHY_PLLVDD

2

C830

C831

1

0.1U_0402_16V4Z~D

BCM5755M

BIAS

Analog
power

2

C832

1

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

GND

PLL

BCM5755M_FBGA144~D

+3.3V_LAN

2

C833

1

0.1U_0402_16V4Z~D

@

2

C834

1

0.1U_0402_16V4Z~D

VSS_0
VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8

VSS_9
VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20

DC_0
DC_1
DC_2
DC_3
DC_4
DC_5
DC_6
DC_7
DC_8

DC_9
DC_10
DC_11
DC_12
DC_13
DC_14
DC_15
DC_16
DC_17
DC_18
DC_19

NC_0

NC_1

NC_2

NC_3

NC_4

NC_5

NC_6

NC_7

NC_8

1 2

R661

4.7K_0402_5%~D

1

C629

2

@

4.7U_0603_6.3V4Z~D

+1.2V_LAN

Reserved for BCM5752
as back-up solution

NV_STRAP1 NV _STRAP0 SO CS#SI

00Auto-Sense Mode 0 0

0

00110

10

DELL CONFIDENTIAL/PROPRIETARY

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

BCM5755M

LA-3302P

28 66Thursday, March 01, 2007

1

2

2

C835

1

1

0.1U_0402_16V4Z~D

B2
B10
E4
E5
E6
E7
E8
E9
F4
F5
F6
F7
F8
F9
G5
G6
G7
G8
L2
L6
M6

A1
A6
A7
B7
C1
C3
D1
D2
D3
E1
G2
H2
K1
K2
K3
K7
K8
L4
L8
M8
A2
E2
G1
G9
H1
H10
J10
K10
K11

SCLK

00

11

1

0

0.4

of

5

4

3

2

1

0B1

VDD04VDD110VDD218VDD327VDD438VDD550VDD6

1B1
2B1

3B1
4B1

5B1
6B1

7B1

0LED1
1LED1
2LED1

0B2
1B2

2B2
3B2

4B2
5B2

6B2
7B2

0LED2
1LED2
2LED2

PI3L500-AZFEX_TQFN56~D

55

+3.3V_LAN

@

@

12

LAN ANALOG
SWITCH

SW_LAN_TX0-

48

SW_LAN_TX0+

47

SW_LAN_TX1-

43

SW_LAN_TX1+

42

SW_LAN_TX2-

37

SW_LAN_TX2+

36

SW_LAN_TX3-

32

SW_LAN_TX3+

31

LAN_LEDACT#

22

LINK_LED10#

23

LINK_LED100#

52

DOCK_LAN_TX0-

46

DOCK_LAN_TX0+

45

DOCK_LAN_TX1-

41

DOCK_LAN_TX1+

40

DOCK_LAN_TX2-

35

DOCK_LAN_TX2+

34

DOCK_LAN_TX3-

30

DOCK_LAN_TX3+

29

DOCK_LOM_ACTLED_YEL#

25

DOCK_LOM_SPD10LED_GRN#

26

DOCK_LOM_SPD100LED_ORG#

51

SW_LAN_TX0- 32
SW_LAN_TX0+ 32

SW_LAN_TX1- 32
SW_LAN_TX1+ 32

SW_LAN_TX2- 32
SW_LAN_TX2+ 32

SW_LAN_TX3- 32
SW_LAN_TX3+ 32

DOCK_LAN_TX0- 36
DOCK_LAN_TX0+ 36

DOCK_LAN_TX1- 36
DOCK_LAN_TX1+ 36

DOCK_LAN_TX2- 36
DOCK_LAN_TX2+ 36

DOCK_LAN_TX3- 36
DOCK_LAN_TX3+ 36

DOCK_LOM_ACTLED_YEL# 36
DOCK_LOM_SPD10LED_GRN# 36
DOCK_LOM_SPD100LED_ORG# 36

TO

DOCK

+3.3V_LAN

C866 0.1U_0402_16V4Z~D@

1 2

C867 0.1U_0402_16V4Z~D@

1 2

C868 0.1U_0402_16V4Z~D@

1 2

C869 0.1U_0402_16V4Z~D@

D D

C C

1 2

R671 49.9_0402_1%~D@

1 2

R672 49.9_0402_1%~D@

1 2

R673 49.9_0402_1%~D@

1 2

R674 49.9_0402_1%~D@

1 2

R675 49.9_0402_1%~D@

1 2

R676 49.9_0402_1%~D@

1 2

R677 49.9_0402_1%~D@

1 2

R678 49.9_0402_1%~D@

1 2

Layout Notice : Place
terminatio n a s close as
ASIC as possible

The resistors need at
least 1/16W

LAN_TX0­LAN_TX0+
LAN_TX1­LAN_TX1+
LAN_TX2­LAN_TX2+
LAN_TX3­LAN_TX3+

LAN_TX0-28
LAN_TX0+28

LAN_TX1-28
LAN_TX1+28

LAN_TX2-28
LAN_TX2+28

LAN_TX3-28
LAN_TX3+28

Layout Notice : Place bead as
close PI3L500 as possible

LAN_TX0- LAN_TX0-R

L69 36NH_0603CS-360EJTS_5%_0603~D

LAN_TX0+

L70 36NH_0603CS-360EJTS_5%_0603~D

LAN_TX1-

L71 36NH_0603CS-360EJTS_5%_0603~D
L72 36NH_0603CS-360EJTS_5%_0603~D

LAN_TX2-

L73 36NH_0603CS-360EJTS_5%_0603~D

LAN_TX2+

L74 36NH_0603CS-360EJTS_5%_0603~D

LAN_TX3-

L75 36NH_0603CS-360EJTS_5%_0603~D

LAN_TX3+ LAN_TX3+R

L76 36NH_0603CS-360EJTS_5%_0603~D

DOCKED

DOCKED36,38

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

LOM_ACTLED_YEL#28
LOM_SPD10LED_GRN#28
LOM_SPD100LED_ORG#28

FROM NIC DOCKED

LAN_TX0+R

LAN_TX1-R
LAN_TX1+RLAN_TX1+

LAN_TX2-R
LAN_TX2+R

LAN_TX3-R

1: TO DOCK
0: TO RJ45

11
12

14
15

17

19
20
54

57

56

U46

2

A0

3

A1

7

A2

8

A3

A4
A5

A6
A7

SEL

LED0
LED1
LED2

5

NC
PAD_GND

GND01GND16GND29GND313GND416GND521GND624GND728GND833GND939GND1044GND1149GND1253GND13

@

12

12

R680

10K_0402_5%~D

R682

1 2

150_0402_5%~D

R683

1 2

110_0402_5%~D

R684

1 2

200_0402_5%~D

R681

10K_0402_5%~D

10K_0402_5%~D

LED_10_GRN_R#

LED_100_ORG_R#

LAN_ACTLED_YEL_R# 32

LED_10_GRN_R# 32

LED_100_ORG_R# 32

R679

LOM_ACTLED_YEL#
LOM_SPD10LED_GRN#
LOM_SPD100LED_ORG#

B B

LAN_LEDACT# LAN_ACTLED_YEL_R#

LINK_LED10#

LINK_LED100#

A A

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.
LAN TRANSFOMER

LA-3302P

29 66Thursday, March 01, 2007

1

0.4

of

8

D D

C C

B B

A A

+3.3V_RUN

+3.3V_RUN

BLM18AG121SN1D_0603~D

8

1

C794

C795

2

4.7U_0603_6.3V4Z~D

L60

1 2

C802

Place closely pin 45

CLK_PCI_PCM

R610

10_0402_5%~D

@

PCI_AD17

C808

@

100_0402_5%~D

1 2

4.7P_0402_50V8C~D

0.1U_0402_16V4Z~D

4.7U_0603_6.3V4Z~D

R615

PCI_DEVSEL#21,35
PCI_FRAME#21,35,36
PCI_IRDY#21,35,36
PCI_TRDY#21,35
PCI_STOP#21,35
PCI_PAR21,35

7

1

C796

2

1

C803

2

12

1

2

CLK_PCI_PCM6

PCI_REQ1#21

PCI_GNT1#21
PCI_RST#21,31,35

SYS_PME#35,38

IRQ_SERIRQ23,28,38,39

1

C800

2

0.1U_0402_16V4Z~D

1

C804

2

0.1U_0402_16V4Z~D

PCI_AD[0..31]21,35

7

1

2

0.1U_0402_16V4Z~D

1

2

0.1U_0402_16V4Z~D

PCI_C_BE3#21,35
PCI_C_BE2#21,35
PCI_C_BE1#21,35
PCI_C_BE0#21,35

1

C801

2

0.1U_0402_16V4Z~D

CBS_IDSEL
CLK_PCI_PCM
PCI_DEVSEL#
PCI_FRAME#
PCI_IRDY#
PCI_TRDY#
PCI_STOP#
PCI_PAR
PCI_REQ1#
PCI_GNT1#
PCI_RST#

IRQ_SERIRQ

PCI_AD31
PCI_AD30
PCI_AD29
PCI_AD28
PCI_AD27
PCI_AD26
PCI_AD25
PCI_AD24
PCI_AD23
PCI_AD22
PCI_AD21
PCI_AD20
PCI_AD19
PCI_AD18
PCI_AD17
PCI_AD16
PCI_AD15
PCI_AD14
PCI_AD13
PCI_AD12
PCI_AD11
PCI_AD10
PCI_AD9
PCI_AD8
PCI_AD7
PCI_AD6
PCI_AD5
PCI_AD4
PCI_AD3
PCI_AD2
PCI_AD1
PCI_AD0

PCI_C_BE3#
PCI_C_BE2#
PCI_C_BE1#
PCI_C_BE0#

Ground pin 129 exposed die pad, dimension

5.72mm x 5.72mm, should connect to PCB solder
pad of same dimension

11
97

26
56

65
68
73

19
20
21
22
23
24
25
27
29
30
31
32
34
35
36
37
47
48
49
50
51
52
53
54
57
58
59
60
61
62
63
64

28
38
46
55

9
45
42
39
40
41
43
44
17
18

5

7

6

6

1

C797

2

4.7U_0603_6.3V4Z~D

CORE_3.3
CORE_3.3

PCI_VCC
PCI_VCC

CORE_3.3A
CORE_3.3A
CORE_3.3A

AD31
AD30
AD29
AD28
AD27
AD26
AD25
AD24
AD23
AD22
AD21
AD20
AD19
AD18
AD17
AD16
AD15
AD14
AD13
AD12
AD11
AD10
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0

C/BE3#
C/BE2#
C/BE1#
C/BE0#

IDSEL
PCI_CLK
DEVSEL#
FRAME#
IRDY#
TRDY#
STOP#
PAR
REQ#
GNT#
PCI_RST#
PME#
SERIRQ

6

+OZ1.8V_RUN

1

C798

2

0.1U_0402_16V4Z~D

82

8

CORE_1.816CORE_1.8

OZ711EZ1

GND33GND

GND

OZ711EZ1TN C_E-LQFP128_16X16~D

108

129

EPSI

R602 33_0402_5%~D

U42

REF

XI

XO

BIAS

TPA+

TPA-

TPB+

TPB-

CAD31
CAD30
CAD29
CAD28
CAD27
CAD26
CAD25
CAD24
CAD23
CAD22
CAD21
CAD20
CAD19
CAD18
CAD17
CAD16
CAD15
CAD14
CAD13
CAD12
CAD11
CAD10

CAD9
CAD8
CAD7
CAD6
CAD5
CAD4
CAD3
CAD2
CAD1
CAD0

CCLK

CFRAME#

CIRDY#

CTRDY#

CDEVSEL#

CSTOP#

CPAR
CPERR#
CSERR#

CREQ#
CGNT#

CINT#

CBLOCK#

CCLKRUN#

CRST#

R2_D2
R2_D14
R2_A18

CVS1

CVS2
CCD1#
CCD2#

CSTSCHG

CC/BE3#
CC/BE2#
CC/BE1#
CC/BE0#

5

72
74

75
71

70
69
67
66

3
1
128
127
126
125
124
122
120
118
116
115
114
113
112
96
94
93
92
91
90
89
88
87
84
83
81
80
79
78
77
76

106
110
109
107
105
103
98
100
119
121
102
104
101
4
117
2
85
99
12
15
10
14

13
123

111
95
86

5

4

CLK_PCI_PCM

PCI_PERR#21,35

PCI_SERR#21,35

CLKRUN#23,38,39

PCI_PIRQD#21

12P_0402_50V8J~D

R603

5.9K_0402_1%~D

1 2

1 2

R114 0_0402_5%~D

CBS_CAD31
CBS_CAD30
CBS_CAD29
CBS_CAD28
CBS_CAD27
CBS_CAD26
CBS_CAD25
CBS_CAD24
CBS_CAD23
CBS_CAD22
CBS_CAD21
CBS_CAD20
CBS_CAD19
CBS_CAD18
CBS_CAD17
CBS_CAD16
CBS_CAD15
CBS_CAD14
CBS_CAD13
CBS_CAD12
CBS_CAD11
CBS_CAD10
CBS_CAD9
CBS_CAD8
CBS_CAD7
CBS_CAD6
CBS_CAD5
CBS_CAD4
CBS_CAD3
CBS_CAD2
CBS_CAD1
CBS_CAD0

R614 0_0402_5%~D

CBS_CFRAME#

CBS_CIRDY#

CBS_CTRDY#

CBS_CDEVSEL#

CBS_CSTOP#

CBS_CPAR
CBS_CPERR#
CBS_CSERR#

CBS_CREQ#
CBS_CGNT#

CBS_CINT#

CBS_CBLOCK#

CBS_CCLKRUN#

CBS_CRST#

CBS_RSVD/D2
CBS_RSVD/D14
CBS_RSVD/A18

CBS_CVS1

CBS_CVS2
CBS_CCD1#
CBS_CCD2#

CBS_CSTSCHNG

CBS_CC/BE3#
CBS_CC/BE2#
CBS_CC/BE1#
CBS_CC/BE0#

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

1 2

X2 24.576MHz_16P_1BG24576CKIA~D

1 2

1 2

TPBIAS0

12P_0402_50V8J~D

TPA0+

TPA0­TPB0+

TPB0-

CBS_CCLK

4

PCI_PERR#
PCI_SERR#
PCI_RST#
CLKRUN#
PCI_PIRQD#

C806

C823

56.2_0402_1%~D

R607

C807

1U_0603_10V4Z~D

+CBS_VCC +CBS_VCC

56.2_0402_1%~D

12

12

R608

R609

5.11K_0402_1%~D

2

1

R613

1

C809

2

0.1U_0402_16V4Z~D

2
7
8

10

6
3
9

19

1

20

56.2_0402_1%~D

12

12

C805

1

1 2

2

CBS_CAD0
CBS_CAD1
CBS_CAD3
CBS_CAD5
CBS_CAD7
CBS_CC/BE0#

CBS_CAD9
CBS_CAD11
CBS_CAD12

CBS_CAD14
CBS_CC/BE1#
CBS_CPAR

CBS_CPERR#
CBS_CGNT#
CBS_CINT#

CBS_CCLK
CBS_CIRDY#
CBS_CC/BE2#
CBS_CAD18
CBS_CAD20

CBS_CAD21
CBS_CAD22
CBS_CAD23
CBS_CAD24

CBS_CAD25
CBS_CAD26
CBS_CAD27

CBS_CAD29
CBS_RSVD/D2
CBS_CCLKRUN#

U41

CLK
PERR#
SERR#
RST#
CLKRUN#
INTA#
SKT_LED

1.8VOUT
EPSI

GND

OZ2532SN_SSOP20~D

R642

56.2_0402_1%~D

270P_0402_50V7K~D

3

+5V_RUN +3.3V_RUN

1

1

2

4.7U_0603_6.3V4Z~D

+3.3V
+3.3V

VCC/VPP
VCC/VPP

USB_A0
USB_B0
USB_A1
USB_B1

C791

2

0.1U_0402_16V4Z~D

16

+5V

15

+5V

18
17

5
4

USBP6-

14

CBS_CAD15

13

USBP6+

12

CBS_CAD13

11

R604

0_0402_5%~D

1 2

R606

0_0402_5%~D

1 2

L61 DLW 21SN121SQ2_0805~D@

4

4

1

1

4

4

1

1

L62 DLW 21SN121SQ2_0805~D@

R611

0_0402_5%~D

1 2

R612

0_0402_5%~D

1 2

C790

Layout Note: Place close to 1394 connector

JCBUS

1

GND1

2

A_CAD0

3

A_CAD1

4

A_CAD3

5

A_CAD5

6

A_CAD7

7

A_PCI_C/BE0#

8

GND2

9

A_CAD9

10

A_CAD11

11

A_CAD12

12

GND3

13

A_CAD14

14

A_PCI_C/BE1#

15

A_CPAR

16

GND4

17

A_CPERR#

18

A_CGNT#

19

A_CINT#

20

+AVCC0

21

+AVPP0

22

A_CCLK

23

A_CIRDY

24

A_PCI_C/BE2#

25

A_CAD18

26

A_CAD20

27

GND5

28

A_CAD21

29

A_CAD22

30

A_CAD23

31

A_CAD24

32

GND6

33

A_CAD25

34

A_CAD26

35

A_CAD27

36

GND7

37

A_CAD29

38

CB_A_D2

39

A_CCLKRUN#

40

GND8

TYCO_1734648-1~D

3

A_PCI_C/BE3#

C792

3

2
3

2

GND9

A_CCD1#

A_CAD2
A_CAD4
A_CAD6

CB_A_D14

A_CAD8

GND10

A_CAD10

A_CVS1

A_CAD13

GND11
A_CAD15
A_CAD16

CB_A_A18

GND12

A_CBLOCK#

A_CSTOP#

A_CDEVSEL#

+AVCC1
+AVPP1

A_CTRDY#

A_CFRAME#

A_CAD17
A_CAD19

A_CVS2

GND13
A_CRST#

A_CSERR#

A_CREQ#

GND14

A_CAUDIO

A_CSTSCHG

A_CAD28

GND15
A_CAD30
A_CAD31
A_CCD2#

GND16

0.1U_0402_16V4Z~D

2

1

2

3

2
3

2

1

2

4.7U_0603_6.3V4Z~D

+CBS_VCC

41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80

C793

USBP6- 23
USBP6+ 23

TPA0_D+

TPA0_D­TPB0_D+

TPB0_D-

CBS_CCD1#
CBS_CAD2
CBS_CAD4
CBS_CAD6
CBS_RSVD/D14
CBS_CAD8

CBS_CAD10
CBS_CVS1
CBS_CAD13

CBS_CAD15
CBS_CAD16
CBS_RSVD/A18

CBS_CBLOCK#
CBS_CSTOP#
CBS_CDEVSEL#

CBS_CTRDY#
CBS_CFRAME#
CBS_CAD17
CBS_CAD19
CBS_CVS2

CBS_CRST#
CBS_CSERR#
CBS_CREQ#
CBS_CC/BE3#

CBS_CSTSCHNG
CBS_CAD28

CBS_CAD30
CBS_CAD31
CBS_CCD2#

J1394

4

TPA+

3

TPA-

2

TPB+

1

TPB-

1

GND
GND
GND
GND

TYCO_2-1775815-2~D

1

C810

2

0.1U_0402_16V4Z~D

DELL CONFIDENTIAL/PROPRIETARY

Title

Cardbus and 1394 OZ711EZ1 Controller

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

LA-3302P

2

30 66Thursday, March 01, 2007

1

5
6
7
8

0.4

of

8

7

6

5

4

3

2

1

D D

TYPE A (5V), B (3V), AB (5V/3V)
& USB SMARTCARDS ARE SUPPORTED.

USB SMARTCARD READER.

+5V_RUN

1

1

C443

C428

2

2

USBP4­USBP4+

PCI_RST#21,30,35

4.7U_0603_6.3V4Z~D

PCI_RST#

CLK_SMC_48M

R259

4.7K_0402_5%~D

+3.3V_RUN

12

R252

R296

1.5K_0402_1%~D

CLK_SMC_48M6

12

15K_0402_5%~D

C C

USBP4-23

USBP4+23
SC_USBP-25
SC_USBP+25

T40PAD~D
T41PAD~D

12

R255

15K_0402_5%~D

12

12

R251

R264

15K_0402_5%~D

15K_0402_5%~D

+3.3V_RUN

1

1

C441

C435

2

2

0.1U_0402_16V4Z~D

12

U26

8
5

28
17

16
19
18

12
14

15

3
4

MD0

32

1
2

4.7U_0603_6.3V4Z~D

3.3VCC
VCC5V_IN0

VCC5V_IN1
UPD-

UPD+
DPD­DPD+

RST#
RFIO0

RFIO1
XI/48M_IN

XO
MODE0/LED#

MODE1
MODE2

0.1U_0402_16V4Z~D

VR_CPR0
VR_CPR1

3V_CPR

EGATED-

EGATED+

SC_VCC

SC_RST#

SC_CLK

SC_C4

SC_IO

SC_DET#

NC1
NC2
NC3

GND0
GND1
GND2

OZ77CR6LN_QFN32~D

C425

1U_0603_10V4Z~D

6

1 2
10
29

1 2

C305 1U_0603_10V4Z~D

21
20

27
24
23
22
25
13

7
30
31

9
11
26

1

1

C442

SCCD­SCCD+

+SC_PWR
SC_RST#
SC_CLK
SC_C4 SCCD+
SC_IO
SC_DET#

0.1U_0402_16V4Z~D

C446

2

2

4.7U_0603_6.3V4Z~D

SC_DET# 38

R125 220_0402_5%~D
R126 33_0402_5%~D
R260 220_0402_5%~D

R130 220_0402_5%~D

1

12

R263

2

10K_0402_5%~D

12
12
12

12

C448

R256

0.1U_0402_16V4Z~D

12

12

R257

15K_0402_5%~D

15K_0402_5%~D

1

12

C129

R129

2

1U_0603_10V4Z~D

+SC_PWR

47K_0402_5%~D

SCCD-

1

C91

2

0.1U_0402_16V4Z~D

JSC

12

GND

11

GND

10

10

9

9

8

8

7

7

6

6

5

5

4

4

3

3

2

2

1

1

MOLEX_52207-1085~D

B B

Place closely pin 3

CLK_SMC_48M

12

@

R258

10_0402_5%~D

@

1

C432

4.7P_0402_50V8C~D

A A

2

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

8

7

6

5

4

3

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.
Smart Card OZ77CR6

LA-3302P

2

31 66Thursday, March 01, 2007

1

0.4

of

5

FUSE4

@

L0603

1 2

FUSE1

@

PAD-OPEN 4x4m

USB_BACK_EN#38

1

C170
10U_0805_10V4Z~D

@

2

@

@

PAD-OPEN 4x4m

USB_SIDE_EN#38

1

C1
10U_0805_10V4Z~D

@

2

LF453

1 2

PJP4

FUSE5
L0603

1 2

FUSE2
LF453

1 2

PJP3

12

USB_BACK_EN#

12

USB_SIDE_EN#

D D

0.1U_0402_16V4Z~D

C C

0.1U_0402_16V4Z~D

C169

C2

+5V_ALW

1

2

+5V_ALW

1

2

4

U4

1

GND

2

IN

3

EN1#

4

EN2#

TPS2062DR_SO8~D

U1

1

GND

2

IN

3

EN1#

4

EN2#

TPS2062DR_SO8~D

OC1#
OUT1
OUT2
OC2#

OC1#
OUT1
OUT2
OC2#

+USB_BACK_PWR

8
7
6
5

+USB_SIDE_PWR

8
7
6
5

USB_OC2_3#

USB_OC0_1#

USB_OC2_3# 23

USB_OC0_1# 23

3

+USB_SIDE_PWR

1

C3

2

0.1U_0402_16V4Z~D

USBP0-23
USBP0+23

USBP1-23

USBP1+23
BREATH_GREEN_LED43
BATT_GREEN_LED43
BATT_AMBER_LED43
R_BT_ACT43
R_MPCI_ACT43

AUD_INT_MIC+27
AUD_INT_MIC-27

USBP0­USBP0+

USBP1­USBP1+
BREATH_GREEN_LED
BATT_GREEN_LED
BATT_AMBER_LED
R_BT_ACT
R_MPCI_ACT

2

JIO

112
334
556
778
9910

11

11

13

13
151516
171718
191920
212122
232324
252526

27

27

29

29

31

GND

GND

32

GND

GND

33

GND

GND

TYCO_3-1775014-0~D

1

LAN_ACTLED_YEL_R#

2
4

SW_LAN_TX0+

6

SW_LAN_TX0-

8

SW_LAN_TX1+

10

SW_LAN_TX1-

12

12

14

14

28
30

16
18
20
22
24
26
28
30

34
35
36

SW_LAN_TX2+
SW_LAN_TX2­SW_LAN_TX3+
SW_LAN_TX3-

LED_10_GRN_R#
LED_100_ORG_R#
HDD_LED

+3.3V_LAN

+2.5V_LAN

LAN_ACTLED_YEL_R# 29

SW_LAN_TX0+ 29
SW_LAN_TX0- 29
SW_LAN_TX1+ 29
SW_LAN_TX1- 29

SW_LAN_TX2+ 29
SW_LAN_TX2- 29
SW_LAN_TX3+ 29
SW_LAN_TX3- 29

LED_10_GRN_R# 29
LED_100_ORG_R# 29
HDD_LED 43

USBP0+

USBP1-

U2

@

1

D1+

2

GND

3

D2-

IP4220CZ6_SO6~D

+USB_SIDE_PWR +USB_BACK_PWR

USBP3-

USBP2+

VCC

USBP1+

4

D2+

5

USBP0-

6

D1-

U16

@

1

D1+

2

GND

3

D2-

IP4220CZ6_SO6~D

D2+
VCC

USBP2-

4
5

USBP3+

6

D1-

Place ESD diodes as close as USB connector.

B B

USBP2-23

USBP2+23

USBP3-23

USBP3+23

L12 DLW 21SN900SQ2_0805~D@

4

1

4

1

4

1

L13 DLW21SN900SQ2_0805~D@

4

1

R149

0_0402_5%~D

1 2

R147

0_0402_5%~D

1 2

R148

0_0402_5%~D

1 2

R150

0_0402_5%~D

1 2

3

3

2

2

3

3

2

2

USBP2_D-

USBP2_D+

USBP3_D-

USBP3_D+

+USB_BACK_PWR

1

+

C168

2

150U_D2_6.3VM~D

1

C9

2

USBP3_D-

0.1U_0402_16V4Z~D

C8

0.1U_0402_16V4Z~D

USBP3_D+

USBP2_D­USBP2_D+

1

2

JUSB1

1

A_VCC

2

A_D-

3

A_D+

4

A_GND

5

B_VCC

6

B_D-

7

B_D+

8

B_GND

9

G1

10

G2

11

G3

12

G4

FOX_UB9112C-SB201-4F~D

Rear USB Port

A A

Rear USB Ports

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.
USB 2.0 Port

LA-3302P

32 66Thursday, March 01, 2007

1

0.4

of

5

D D

C C

4

ICH_AZ_MDC_RST#22

+5V_SUS

MDC_RST_DIS#18

12

R239
10K_0402_5%~D

3

@

0_0402_5%~D

1 2

1 3

R235

D

S

Q31
BSS138W-7-F_SOT323~D

G

2

ICH_RST_MDC_R#

12

R233
100K_0402_5%~D

2

1

New MDC connector.

1

GND

3

IAC_SDATA0

5

GND

7

IAC_SYNC

9

IAC_SDATAIN

11 12

IAC_RESET#

IAC_BITCLK

RES
RES

3.3V
GND
GND

2
4
6
8
10

B B

JMDC

1

ICH_AZ_MDC_SDOUT22
ICH_AZ_MDC_SYNC22

1 2

ICH_AZ_MDC_SDIN122

A A

R128

33_0402_5%~D

ICH_AZ_MDC_SDOUT
ICH_AZ_MDC_SYNC

MDC_SDIN
ICH_RST_MDC_R#

GND1

3

IAC_SDATA_OUT

5

GND2

7

IAC_SYNC

9

IAC_SDATA_IN

11

IAC_RESET#

GND13GND14GND15GND16GND17GND

2

RES0

4

RES1

6

3.3V

8

GND3

10

GND4

12

IAC_BITCLK

TYCO_1-1775149-2~D

18

Connector for MDC Rev1.5

W=20 mil

ICH_AZ_MDC_BITCLK

+3.3V_SUS

1

C126

2

4.7U_0603_6.3V4Z~D

ICH_AZ_MDC_BITCLK22

1

C125

2

0.1U_0402_16V4Z~D

ICH_AZ_MDC_SDOUT
ICH_AZ_MDC_BITCLK

C128

10P_0402_50V8J~D

R123

R124

1 2

10_0402_5%~D

1 2

10_0402_5%~D@

MDC_AC_BITCLK_TERM

ICH_AC_SDOUT_MDCTERM

1

1

C127
10P_0402_50V8J~D

2

2

@

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.
BT PORT and MDC

LA-3302P

33 66Thursday, March 01, 2007

1

0.4

of

5

4

3

2

1

L8 DLW21SN900SQ2_0805~D

USBP9-23

USBP9+23

D D

R18

@

1 2

0_0402_5%~D

WLAN_RADIO_DIS#38

RB751S40T1_SOD523-2~D

JCLIP2

1

GND1

2

GND2

3

GND3

4

GND4

TYCO_1775837-1~D

C C

1

1

4

4

0_0402_5%~D

1 2

0_0402_5%~D

1 2

21

D1

WLAN_3V_ENABLE39

2

@

2

3

3

R120

R121

2N7002W-7-F_SOT323-3~D

12

R786

100K_0402_5%~D

R785

Q96

2

G

Mini-Card Latch

SB_WLAN_PCIE_RST#21

SB_WLAN_PCIE_RST#

Mini WLAN

+3.3V_WLAN

PCIE_WAKE#28,38
COEX2_WLAN_ACTIVE40
COEX1_BT_ACTIVE40

MINI2CLK_REQ#6
CLK_PCIE_MINI2#6

CLK_PCIE_MINI26

HOST_DEBUG_RX39

8051_TX39

PCIE_IRX_WLANTX_N223
PCIE_IRX_WLANTX_P223

B B

A A

+1.5V_RUN

1

C34

2

0.047U_0402_16V4Z~D

PCIE_ITX_WLANRX_N2_C23
PCIE_ITX_WLANRX_P2_C23

PCIE_MCARD1_DET#23

1

C15

2

0.047U_0402_16V4Z~D

R91 0_0402_5%~D
R27 0_0402_5%~D

+3.3V_WLAN

1

C16

2

@

0.1U_0402_16V4Z~D

5

1 2

R548

100K_0402_5%~D

+3.3V_RUN

1 2
1 2

HOST_DEBUG_RX
8051_TX

PCIE_IRX_WLANTX_N2
PCIE_IRX_WLANTX_P2

PCIE_ITX_WLANRX_N2_C
PCIE_ITX_WLANRX_P2_C

1

1

2

C41

2

0.047U_0402_16V4Z~D

C166

0.047U_0402_16V4Z~D

11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51

53

1

C36

2

JMINI2

1

1

3

3

5

5

7

7

9

9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51

GND1

TYCO_1775838-1~D

0.1U_0402_16V4Z~D

+3.3V_WLAN

2

2

4

4

6

6

8

8

10

10

12

12

14

14

16

16

18

18

20

20

22

22

24

24

26

26

28

28

30

30

32

32

34

34

36

36

38

38

40

40

42

42

44

44

46

46

48

48

50

50

52

52

54

GND2

1

1

C164

2

2

0.1U_0402_16V4Z~D

12

100K_0402_5%~D

13

D

S

R599

@

0_0402_5%~D

+1.5V_RUN

WLAN_PLTRST3#_R

WLAN_SMBCLK

WLAN_SMBDATA

1

C163

2

4.7U_0603_6.3V4Z~D

4

USBP9_D-

USBP9_D+

+3.3V_ALW+PW R_SRC

12

R784

100K_0402_5%~D

13

D

2

Q95

G

S

12

R783

200K_0402_5%~D

12

HOST_DEBUG_TX
WLAN_RADIO_DIS#_R

WLAN_SMBCLK
WLAN_SMBDATA

R549 100K_0402_5%~D

1 2

8051_RX
LED_WLAN_OUT#

1 2

R11 0_0402_5%~D@

12

R640

2.2K_0402_5%~D

+

C283
330U_D2E_6.3VM_R25~D

D

6
2

1

G

3

12

2N7002W-7-F_SOT323-3~D

PLTRST3#

12

R600

0_0402_5%~D

+3.3V_RUN

12

R645

2.2K_0402_5%~D

G

S

Q46

@

2N7002W-7-F_SOT323-3~D

+3.3V_WLAN

S

45

Q94

SI3456BDV-T1-E3_TSOP6~D

1

C270
4700P_0402_25V7K~D

R782

2

470K_0402_5%~D

HOST_DEBUG_TX 39

PLTRST3# 21,28

USB_MCARD1_DET# 23

8051_RX 39
LED_WLAN_OUT# 43
BT_ACTIVE 40,43

+3.3V_WLAN

Q45

@

G

2

2N7002W-7-F_SOT323-3~D

13

D

S

R660

1 2

0_0402_5%~D @

2

13

D

1 2

R662

@

0_0402_5%~D

JCLIP1

1

GND1

2

GND2

3

GND3

4

GND4

TYCO_1775837-1~D

Mini-Card Latch

PCIE_IRX_WANTX_N1
PCIE_IRX_WANTX_P1

PCIE_ITX_WANRX_N1_C
PCIE_ITX_WANRX_P1_C

PCIE_MCARD2_DET#

1 2

R550 100K_0402_5%~D

+SIM_PWR

UIM_RESET
UIM_CLK

C459

1U_0603_10V4Z~D

PCIE_WAKE#

MINI1CLK_REQ#
CLK_PCIE_MINI1#

CLK_PCIE_MINI1

1
2
3

7

1

SUYIN_254020MA006G502ZL~D

2

PWR
Rail

+3.3V

+3.3Vaux

+1.5V

PCIE_WAKE#28,38

MINI1CLK_REQ#6
CLK_PCIE_MINI1#6

CLK_PCIE_MINI16

PCIE_IRX_WANTX_N123
PCIE_IRX_WANTX_P123

PCIE_ITX_WANRX_N1_C23
PCIE_ITX_WANRX_P1_C23

PCIE_MCARD2_DET#21

+3.3V_RUN

ICH_SMBCLK 23,28

CLK_SCLK 6

ICH_SMBDATA 23,28

CLK_SDATA 6

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

JSIM

VCC
RST
CLK

NC

+3.3V_RUN

1

2

Voltage
Tolerance

+-9%

+-9%

+-5%

C449

0.047U_0402_16V4Z~D

SB_WWAN_PCIE_RST#21

Mini WWAN

JMINI1

1

1

3

3

5

5

7

7

9

9

11

11

13

13

15

15

17

17

19

19

21

21

23

23

25

25

27

27

29

29

31

31

33

33

35

35

37

37

39

39

41

41

43

43

45

45

47

47

49

49

51

51

53

GND1

TYCO_1775838-1~D

4

GND

5

VPP

6

I/O

8

NC

1

C416

2

0.047U_0402_16V4Z~D

Primary Power Aux Power

Peak Normal Normal

1000 750

330

500

GND2

1

2

2

2
4
6

8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

C444

SB_WWAN_PCIE_RST#

+3.3V_RUN+3.3V_RUN

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

54

UIM_VPP
UIM_DATA

1

2

33P_0402_50V8J~D

UIM_DATA
UIM_CLK
UIM_RESETWLAN_RADIO_DIS#_R
UIM_VPP

WWAN_RADIO_DIS#

+3.3V_RUN

ICH_SMBCLK
ICH_SMBDATA

USBP9_D­USBP9_D+

UIM_RESET

UIM_CLK

C123

1

C111

C773

2

33P_0402_50V8J~D

22U_0805_6.3VAM~D

250 (Wake enable)

250

5 (Not wake enable)

375

NA

R598

@

0_0402_5%~D

12

+1.5V_RUN
+SIM_PWR

T16 PAD~D

1

C124

2

33P_0402_50V8J~D

1

+

2

33P_0402_50V8J~D

C445

1

2

330U_D2E_6.3VM_R25~D

12

R597

0_0402_5%~D

12

R574
100K_0402_5%~D

U53

1

2

3

SRV05-4.TCT_SOT23-6~D

PLTRST3#WWAN_PLTRST3#_R

+3.3V_RUN

6

5

4

1

2

WWAN_RADIO_DIS# 38
PLTRST3# 21,28

ICH_SMBCLK 23,28
ICH_SMBDATA 23,28

USB_MCARD2_DET# 23

UIM_VPP

+SIM_PWR

UIM_DATA

1

C460

C122

2

33P_0402_50V8J~D

33P_0402_50V8J~D

+1.5V_RUN

C121

33P_0402_50V8J~D

DELL CONFIDENTIAL/PROPRIETARY

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

Mini Card

LA-3302P

34 66Thursday, March 01, 2007

1

of

1

1

C120

2

2

0.047U_0402_16V4Z~D

0.4

5

4

3

2

1

+5V_RUN

D D

C C

PCI_AD[0..31]21,30

B B

A A

PCI_PIRQA#21

PCI_RST#21,30,31
PCI_C_BE3#21,30

PCI_C_BE2#21,30
PCI_C_BE1#21,30
PCI_C_BE0#21,30
PCI_IRDY#21,30,36
PCI_FRAME#21,30,36

PCI_TRDY#21,30
PCI_STOP#21,30
PCI_PLOCK#21
PCI_DEVSEL#21,30
PCI_PERR#21,30
PCI_SERR#21,30
PCI_PAR21,30

D2

RB751S40T1_SOD523-2~D

2 1

QUIETE#

QUIETE#

PCI_PIRQA#

PCI_GNT0#21,36
SYS_PME#30,38

PCI_GNT0#
PCI_RST#
SYS_PME#
PCI_C_BE3#
PCI_C_BE2#
PCI_C_BE1#
PCI_C_BE0#
PCI_IRDY#
PCI_FRAME#

PCI_TRDY#
PCI_STOP#
PCI_PLOCK#
PCI_DEVSEL#
PCI_PERR#
PCI_SERR#
PCI_PAR
PCI_AD24

PCI_AD31
PCI_AD30
PCI_AD29
PCI_AD28
PCI_AD27
PCI_AD26
PCI_AD25
PCI_AD24

PCI_AD23
PCI_AD22
PCI_AD21
PCI_AD20
PCI_AD19
PCI_AD18
PCI_AD17
PCI_AD16

PCI_AD15
PCI_AD14
PCI_AD13
PCI_AD12
PCI_AD11
PCI_AD10
PCI_AD8
PCI_AD9

PCI_AD7
PCI_AD6
PCI_AD5
PCI_AD4
PCI_AD3
PCI_AD2
PCI_AD1
PCI_AD0

+VCC_QBUFD

D3

RB751S40T1_SOD523-2~D

2 1

R19

1K_0402_5%~D

U19

1

NC1

2

A1

3

A2

4

A3

5

A4

6

A5

7

A6

8

A7

9

A8

10

GND1

11

NC2

12

A9

13

A10

14

A11

15

A12

16

A13

17

A14

18

A15

19

A16

20

GND2

21

NC3

22

A17

23

A18

24

A19

25

A20

26

A21

27

A22

28

A23

29

A24

30

GND3

31

NC4

32

A25

33

A26

34

A27

35

A28

36

A29

37

A30

38

A31

39

A32

40

GND4

PI5C34X2245BE_BQSOP80~D

U18

47

OE1
OE235VCC2

2

A0

3

A1

4

A2

5

A3

6

A4

7

A5

8

A6

9

A7

10

A8

11

A9

14

A10

15

A11

16

A12

17

A13

18

A14

19

A15

20

A16

21

A17

22

A18

23

A19

1

NC1

13

NC2

PI5C162861BE_BQSOP48~D

VCC4

OE1#

VCC3

OE2#

VCC2

OE3#

VCC1

OE4#

VCC1

GND1
GND2

+VCC_QBUF

12

80
79
78

B1

77

B2

76

B3

75

B4

74

B5

73

B6

72

B7

71

B8

70
69
68

B9

67

B10

66

B11

65

B12

64

B13

63

B14

62

B15

61

B16

60
59
58

B17

57

B18

56

B19

55

B20

54

B21

53

B22

52

B23

51

B24

50
49
48

B25

47

B26

46

B27

45

B28

44

B29

43

B30

42

B31

41

B32

36
48

46

B0

45

B1

44

B2

43

B3

42

B4

41

B5

40

B6

39

B7

38

B8

37

B9

34

B10

33

B11

32

B12

31

B13

30

B14

29

B15

28

B16

27

B17

26

B18

25

B19

12
24

1

2

C29

0.1U_0402_16V4Z~D

1 2

C31

0.047U_0402_16V4Z~D

1 2

C26

0.1U_0402_16V4Z~D

1 2

1

C28

C32

2

0.1U_0402_16V4Z~D

DOCK_AD31
DOCK_AD30
DOCK_AD29
DOCK_AD28
DOCK_AD27
DOCK_AD26
DOCK_AD25
DOCK_AD24

DOCK_AD23
DOCK_AD22
DOCK_AD21
DOCK_AD20
DOCK_AD19
DOCK_AD18
DOCK_AD17
DOCK_AD16

DOCK_AD15
DOCK_AD14
DOCK_AD13
DOCK_AD12
DOCK_AD11
DOCK_AD10
DOCK_AD8
DOCK_AD9

DOCK_AD7
DOCK_AD6
DOCK_AD5
DOCK_AD4
DOCK_AD3
DOCK_AD2
DOCK_AD1
DOCK_AD0

DOCK_PIRQA#
DOCK_GNT0#
DOCK_PCIRST#
DOCK_SPME#
DOCK_C_BE3#
DOCK_C_BE2#
DOCK_C_BE1#
DOCK_C_BE0#
DOCK_IRDY#
DOCK_FRAME#

DOCK_TRDY#
DOCK_STOP#
DOCK_LOCK#
DOCK_DEVSEL#
DOCK_PERR#
DOCK_SERR#
DOCK_PAR
DOCK_PCI_IDSEL

1

C33

2

0.1U_0402_16V4Z~D

0.047U_0402_16V4Z~D

DOCK_AD[0..31] 36

+3.3V_RUN

1

C35

4

0.1U_0402_16V4Z~D

2

QUIETE#

DOCK_PIRQA# 36
DOCK_GNT0# 36
DOCK_PCIRST# 36
DOCK_SPME# 36
DOCK_C_BE3# 36
DOCK_C_BE2# 36
DOCK_C_BE1# 36
DOCK_C_BE0# 36
DOCK_IRDY# 36
DOCK_FRAME# 36

DOCK_TRDY# 36
DOCK_STOP# 36
DOCK_LOCK# 36
DOCK_DEVSEL# 36
DOCK_PERR# 36
DOCK_SERR# 36
DOCK_PAR 36
DOCK_PCI_IDSEL 36

R22
100K_0402_5%~D

1 2

DOCK_PCI_EN#36
QBUFEN#38

DOCK_PCI_EN#
QBUFEN#

5

1

P

INB

2

INA

G

3

U5

O

TC7SH32FU_SSOP5~D

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.
DOCKING BUFFER

LA-3302P

35 66Thursday, March 01, 2007

1

0.4

of

5

4

3

2

1

+DC_IN

R12 150_0402_1%~D
R13 150_0402_1%~D
R14 150_0402_1%~D

PWR_SRC

LA-3302P

+DC_IN

2

1

1 2
1 2
1 2

1

1

C13

C14

2

0.1U_0603_50V4Z~D
1000P_0402_50V7K~D

no power dock

self powe r dock

36 66Thursday, March 01, 2007

0.4

of

R8

1 2

100K_0402_5%~D

2

+DOCK_PW R_SRC

2

C20

1

0.1U_0603_50V4Z~D

Q6

FDS4435BZ_SO8~D

8
7

1

6

2

5

3

4

12

R17
100K_0402_5%~D

Z3307

13

D

Q2

2

2N7002W-7-F_SOT323-3~D

G

S

DOCK_AD0
DOCK_AD1
DOCK_AD2
DOCK_AD3
DOCK_AD4
DOCK_AD5
DOCK_AD6
DOCK_AD7
DOCK_AD8
DOCK_AD9
DOCK_AD10
DOCK_AD11
DOCK_AD12
DOCK_AD13
DOCK_AD14
DOCK_AD15
DOCK_AD16
DOCK_AD17
DOCK_AD18
DOCK_AD19
DOCK_AD20
DOCK_AD21
DOCK_AD22
DOCK_AD23
DOCK_AD24
DOCK_AD25
DOCK_AD26
DOCK_AD27
DOCK_AD28
DOCK_AD29
DOCK_AD30
DOCK_AD31

JDOCKC

P1

P1

P2

P2

P3

P3

P4

P4

MH1

MH1

MH5

SHLD1

MH6

SHLD2

MH9

SHLD5

MH10

SHLD6

MH13

MH13

MH15

MH15

TYCO_2-1612415-1~D

+DOCK_PW R_SRC

1

C18
1000P_0402_50V7K~D

2

MH2
SHLD3
SHLD4
SHLD7
SHLD8

MH14
MH16

P5
P6
P7
P8

TV_C
TV_CVBS
TV_Y

P5
P6
P7
P8

MH2
MH7
MH8
MH11
MH12

MH14
MH16

DOCK_AD[0..31] 35

NB

DELL CONFIDENTIAL/PROPRIETARY

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.
DOCKING CONN

DOCK_PWR_EN38

JDOCKB

137

S137

138

S138

139

S139

140

S140

141

S141

142

S142

143

S143

144

S144

145

S145

146

S146

147

S147

148

S148

149

S149

150

S150

151

S151

152

S152

153

S153

154

S154

155

S155

156

S156

157

S157

158

S158

159

S159

160

S160

161

S161

162

S162

163

S163

164

S164

165

S165

166

S166

167

S167

168

S168

169

S169

170

S170

171

S171

172

S172

173

S173

174

S174

175

S175

176

S176

177

S177

178

S178

179

S179

180

S180

181

S181

182

S182

183

S183

184

S184

185

S185

186

S186

187

S187

188

S188

189

S189

190

S190

193

S193

194

S194

195

S195

196

S196

204

M204

TYCO_2-1612415-1~D

2

3

205

S205

206

S206

207

S207

208

S208

209

S209

210

S210

211

S211

212

S212

213

S213

214

S214

215

S215

216

S216

217

S217

218

S218

220

S220

222

S222

223

S223

224

S224

225

S225

226

S226

227

S227

228

S228

229

S229

230

S230

231

S231

232

S232

233

S233

234

S234

235

S235

236

S236

237

S237

238

S238

239

S239

240

S240

241

S241

242

S242

243

S243

244

S244

245

S245

246

S246

247

S247

248

S248

250

S250

252

S252

253

S253

254

S254

255

S255

256

S256

257

S257

258

S258

259

S259

+3.3V_ALW

0.47U_0805_25V7K~D

R4
100K_0402_5%~D

1 2

13

Q3

DDTC144EUA-7-F_SOT323-3~D

DOCK_PWR_EN

HSYNC_R
VSYNC_R

D_LAD0
DOCK_SMB_ALERT#

DOCK_AD2
DOCK_AD5
DOCK_AD6

DOCK_AD12
DOCK_AD13
DOCK_C_BE1#

DOCK_PERR#
DOCK_STOP#
DOCK_TRDY#

DOCK_AD17
DOCK_AD18
DOCK_AD21

DOCK_C_BE3#
DOCK_AD25
DOCK_AD26

PCI_REQ0#
DOCK_PCIRST#

TV_CVBS
TV_Y

R_PIDEACT

+PWR_SRC

C150

0.1U_0402_10V7K~D

AUD_SPDIF_OUT

10_0402_5%~D

@

10P_0402_50V8J~D

2

C11

1

DOCKED 29,38

U13

3

74AHC1G08GW_SOT353-5~D

2

G

IN2

O

1

IN1

P

5

12

1 2

R7

0_0402_5%~D@

DAT_DDC2 20,52

CLK_DDC2 20,52

HSYNC_R 20

VSYNC_R 20

D_CLKRUN# 38

DOCK_SMB_ALERT# 39

DOCK_C_BE1# 35

DOCK_PERR# 35
DOCK_STOP# 35
DOCK_TRDY# 35

DOCK_C_BE3# 35

PCI_REQ0# 21

DOCK_PCIRST# 35

DOCK_LOM_ACTLED_YEL# 29
R_PIDEACT 43

12

R791

@

1

C267

2

R10
200K_0402_5%~D

1 2

G_DOC_PWRSRC

Z3308

4

+3.3V_SUS

JDOCKA

1

S1

2

S2

DVI_CLK-53

DVI_CLK+53

DVI_TX4-

D D

DOCK_PSID44

CLK_PCI_DOCK6

DOCK_PIRQA#35

DOCK_SMB_CLK39

DOCK_SMB_DAT39

C C

B B

A A

CLK_DOCK39
DAT_DOCK39

CLK_PCI_DOCK

12

@

R20
10_0402_5%~D

1

@

C25

4.7P_0402_50V8C~D

2

DVI_TX4+

DVI_TX3+
DVI_TX3-

DVI_TX5+
DVI_TX5-

DVI_TX2+53

DVI_TX2-53

DVI_TX1+53

DVI_TX1-53

DVI_TX0+53

DVI_TX0-53

DOCK_AD31

PCI_GNT0#21,35

TV_C52

TV_Y52

TV_CVBS52

CRT_RED20,52

CRT_GRN20,52

CRT_BLU20,52

5

3
4
5
6
7
8

9
10
11
12
13

15
17

18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43

45
47

48
49
50
51
52
53
54
55

PCI_GNT0#

PCI_IRDY#21,30,35

PCI_FRAME#21,30,35

S3
S4
S5
S6
S7
S8
S9
S10
S11
S12
S13

S15
S17

S18
S19
S20
S21
S22
S23
S24
S25
S26
S27
S28
S29
S30
S31
S32
S33
S34
S35
S36
S37
S38
S39
S40
S41
S42
S43

S45
S47

S48
S49
S50
S51
S52
S53
S54
S55

TYCO_2-1612415-1~D

69

S69

70

S70

71

S71

72

S72

73

S73

74

S74

75

S75

76

S76

77

S77

78

S78

79

S79

80

S80

81

S81

82

S82

83

S83

84

S84

85

S85

86

S86

87

S87

88

S88

89

S89

90

S90

91

S91

92

S92

93

S93

94

S94

95

S95

96

S96

97

S97

98

S98

99

S99

100

S100

101

S101

102

S102

103

S103

104

S104

105

S105

106

S106

107

S107

108

S108

109

S109

110

S110

111

S111

112

S112

113

S113

114

S114

115

S115

116

S116

117

S117

118

S118

119

S119

120

S120

121

S121

122

S122

125

S125

126

S126

127

S127

128

S128

136

M136

+3.3V_RUN

1

C37

0.1U_0402_16V4Z~D

2

1

5

P

NC

4

A2Y

G

U6

NC7SZ04P5X_NL_SC70-5~D

3

PCI_IRDY#
PCI_FRAME#

TV_C

TV_Y

TV_CVBS

CRT_RED

CRT_GRN

CRT_BLU

CRT_RED

DOCK_AD8
DOCK_C_BE0#

DOCK_AD14
DOCK_AD15

DOCK_AD19
DOCK_AD20

DOCK_AD27
DOCK_AD28
DOCK_AD30

USBP8­USBP8+

+3.3V_RUN

5

1

IN1

2

IN2

3

D_SERIRQ 38
DOCK_PCI_IDSEL 35

D_DLRQ1# 38 D_LAD0 38
D_LFRAME# 38

DVI_SCLK 52
DVI_SDATA 52
DVI_DETECT 52

DOCK_C_BE0# 35

DOCK_DEVSEL# 35
DOCK_IRDY# 35

DOCK_GNT0# 35

USBP8- 23

USBP8+ 23

DOCK_SMB_PME# 38

CLK_KBD 39
DAT_KBD 39

+2.5V_LAN

0.01U_0402_16V7K~D

0.01U_0402_16V7K~D

DOCK_LAN_TX3- 29
DOCK_LAN_TX3+ 29
DOCK_LAN_TX2- 29
DOCK_LAN_TX2+ 29

DOCK_RING

C23

1 2

C24

1 2

DOCK_LOM_SPD10LED_GRN#29
DOCK_LOM_SPD100LED_ORG#29

D_LAD138
D_LAD238
D_LAD338

DOCK_PAR35
DOCK_SERR#35
DOCK_LOCK#35

DOCK_FRAME#35

DOCK_C_BE2#35

DOCK_SPME#35

DOCK_PCI_EN#35
AUD_SPDIF_OUT26

C21

0.01U_0402_16V7K~D

12

C22

0.01U_0402_16V7K~D

12

DOCK_LAN_TX1-29
DOCK_LAN_TX1+29
DOCK_LAN_TX0-29
DOCK_LAN_TX0+29

PLACE TERMINATIONS CLOSE TO DOCK CONNECTOR

+3.3V_RUN

1

C40

0.1U_0402_16V4Z~D

2

Z3305

C38

1 2

0.1U_0402_16V4Z~D

U7

P

Z3306

4

O

G

74AHC1G08GW_SOT353-5~D

DOCK_RING
DOCK_TIP

4

5

1

P

IN1

2

IN2

G

3

U8

DOCK_OWNS_PCI

4

O

74AHC1G08GW_SOT353-5~D

JWIRE

1

1

2

2

3

3

4

4

MOLEX_53398-0471~D

DOCK_DET# DOCK_DET#
CRT_GRN

CRT_BLU
D_LAD1

D_LAD2
D_LAD3

DOCK_AD1
DOCK_AD0

DOCK_AD3
DOCK_AD4
DOCK_AD7

DOCK_AD9
DOCK_AD10
DOCK_AD11

DOCK_C_BE2#
DOCK_AD16

DOCK_AD22
DOCK_AD23
DOCK_AD24

DOCK_AD29

TV_C

DOCK_OWNS_PCI

DOCK_TIP

+5V_ALW

R16
100K_0402_5%~D

1 2

DOCK_DET#

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

+3.3V_SUS

4

3

2

1

26

VCC

INVALID#

1

C167

0.1U_0402_16V4Z~D

2

27

V+

3

V-

9

T1OUT

10

T2OUT

11

T3OUT

4

R1IN

5

R2IN

6

R3IN

7

R4IN

8

R5IN

21
25

GND

3243V+
3243V-

TXD0#
RTS0
DTR0
DCD0
RI0
RXD0#
CTS0
DSR0

C10

0.47U_0402_10V4Z~D

1 2

C7

0.47U_0402_10V4Z~D

1 2

1

2

+3.3V_ALW

R131

@

100K_0402_5%~D

BC_A_DAT39
BC_A_CLK39
BC_A_INT#39

C175

0.1U_0402_16V4Z~D

12

1

C171

2

0.1U_0402_16V4Z~D

BC_A_DAT
BC_A_CLK
BC_A_INT#

R28

1K_0402_5%~D

+3.3V_ALW

12

30
10

39

37
38

34
35
36

40
41

U39

VCC1
VCC1

NC3

NC1
NC2

BC_DATA
BC_CLK
BC_INT#

TEST_PIN
GND_PAD

ECE1077

ECE1077-FZG_QFN40~D

KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8

KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15

KSO16/GPIO_0
KSO17/GPIO_1
KSO18/GPIO_2
KSO19/GPIO_3
KSO20/GPIO_4
KSO21/GPIO_5
KSO22/GPIO_6

KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7

DCD0
DSR0
RXD0#
RTS0
TXD0#
CTS0
DTR0
RI0

1

1

1

1

C153

C152

2

2

2

KSO0

9

KSO1

11

KSO2

12

KSO3

13

KSO4

14

KSO5

15

KSO6

16

KSO7

17

KSO8

18

KSO9

19

KSO10

20

KSO11

21

KSO12

22

KSO13

23

KSO14

24

KSO15

25

KSO16

26

KSO17

27
28
29
31
32
33

KSI0

1

KSI1

2

KSI2

3

KSI3

4

KSI4

5

KSI5

6

KSI6

7

KSI7

8

270P_0402_50V7K~D

270P_0402_50V7K~D

KSO[0..17] 40

KYBD_DET# 40

KSI[0..7] 40

1

1

C154

C155

2

2

270P_0402_50V7K~D

270P_0402_50V7K~D

1

1

C157

C156

270P_0402_50V7K~D

C158

2

270P_0402_50V7K~D

C159

2

2

270P_0402_50V7K~D

270P_0402_50V7K~D

JSIO

1

DCD0

6

DSR0

2

RXD0#

7

RTS0F

3

TXD0F#

8

CTS0

4

DTR0F

9

RI0

5

GND0

10

GND1

11

GND2

SUYIN_070921MR009S203BR~D

D D

C12

0.1U_0402_10V7K~D

C6

0.1U_0402_10V7K~D

1 2

C C

B B

1 2

TXD038
RTS0#38
DTR0#38
DCD0#38

RI0#38
RXD038
CTS0#38
DSR0#38

+3.3V_SUS

RUN_ON19,39,41,42,51

3243C1+

3243C1­3243C2+

3243C2­TXD0
RTS0#
DTR0#
DCD0#
RI0#
RXD0
CTS0#
DSR0#

U3

28

C1+

24

C1-

1

C2+

2

C2-

14

T1IN

13

T2IN

12

T3IN

19

R1OUT

18

R2OUT

17

R3OUT

16

R4OUT

15

R5OUT

20

R2OUTB

23

FORCEON

22

FORCEOFF#

MAX3243ECUI+T_TSSOP28~D

A A

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

Serial & FIR

LA-3302P

37 66Thursday, March 01, 2007

1

0.4

of

5

4

3

2

1

+3.3V_ALW

1 2

R248 10K_0402_5%~D

1 2

R247 10K_0402_5%~D

+3.3V_RUN

1 2

D D

C C

B B

R1 100K_0402_5%~D

Place closely pin 64

CLK_SIO_14M

R246

10_0402_5%~D

C415

4.7P_0402_50V8C~D

ITP_DBRESET#7,23

+3.3V_ALW

R220

100K_0402_5%~D

VGA_IDENTIFY

1 = Discrete Gfx

0 = UMA

12

R237

100K_0402_5%~D

IMVP6_PROCHOT#

12

@

1

2

@

12

PANEL_BKEN

SYS_PME#

PCIE_WAKE#

10K_0402_5%~D

RI0#37

1 2

R806 0_0402_5%~D@

+3.3V_ALW

R250

+5V_ALW

+3.3V_SUS

12

5V_3V_1.8V_1.25V_RUN_PWRGD42

1 2

R245 10K_0402_5%~D

PBAT_PRES#44
SBAT_PRES#44,50

CHG_PBATT50
CHG_SBATT50
PBAT_DSCHG50

SYS_PME#30,35

PCIE_WAKE#28,34
USB_BACK_EN#32

WIRELESS_ON/OFF#43

BT_RADIO_DIS#40

USB_SIDE_EN#32

DOCK_PWR_EN36
ADAPT_TRIP_SET49

PSID_DISABLE#44
PANEL_BKEN52

DOCKED29,36

DOCK_SMB_PME#36

NB_MUTE#27
AUD_SPDIF_SHDN26

DOCK_HP_MUTE#26

AUD_HP_NB_SENSE26,27

1.05V_RUN_ON47
GFX_CORE_ON51

MODPRES#25

IMVP6_PROCHOT#48

LOM_LOW_PWR28

SC_DET#31

LED_MASK#43
GFX_DEVID252

SIO_EXT_WAKE#23

ICH_PME#21

ICH_PCIE_W AKE#23

WLAN_RADIO_DIS#34

WWAN_RADIO_DIS#34

LOM_CABLE_DETECT28

LOM_TPM_EN#28

LOM_SUPER_IDDQ28

ATF_INT#18

BC_DAT39

BC_CLK39

DOCK_SMB_PME#

BC_INT#39

RXD037
TXD037

RTS0#37

DSR0#37

CTS0#37

DTR0#37

DCD0#37

QBUFEN#35

ADAPT_OC49

HDDC_EN25
MODC_EN25

R242 0_0402_5%~D

PBAT_PRES#
SBAT_PRES#
CHG_PBATT
CHG_SBATT

SYS_PME#
PCIE_WAKE#
USB_BACK_EN#

WIRELESS_ON/OFF#
BT_RADIO_DIS#

BC_INT#
BC_DAT
BC_CLK

RXD0
TXD0
RTS0#
DSR0#
CTS0#
DTR0#
RI0#
DCD0#

USB_SIDE_EN#
QBUFEN#

DOCK_PWR_EN
ADAPT_OC
ADAPT_TRIP_SET
ITP_DBRESET#_R
PSID_DISABLE#
PANEL_BKEN
DOCKED
DOCK_SMB_PME#
NB_MUTE#

AUD_SPDIF_SHDN
DOCK_HP_MUTE#
AUD_HP_NB_ SENSE

LID_CL_SIO#

1.05V_RUN_ON
GFX_CORE_ON

MODPRES#
HDDC_EN

MODC_EN

LOM_LOW_PWR
SC_DET#
LED_MASK#

1 2

ICH_PME#
ICH_PCIE_W AKE#
WLAN_RADIO_DIS#

WWAN_RADIO_DIS#

1 2

R308 0_0402_5%~D

LOM_TPM_EN#
LOM_SUPER_IDDQ
VGA_IDENTIFY
CHIPSET_ID

R112

10K_0402_5%~D

BID1
BID0
ATF_INT#

U25

97

GPIOA[0]

98

GPIOA[1]

99

GPIOA[2]

100

GPIOA[3]

101

GPIOA[4]

102

GPIOA[5]

103

GPIOA[6]

104

GPIOA[7]

24

GPIOH[0]

25

GPIOH[1]

26

GPIOH[4]

27

GPIOH[5]

58

BC_INT#

59

BC_DAT

60

BC_CLK

1

GPIOE[0]/RXD

2

GPIOE[1]/TXD

3

GPIOE[2]/RTS#

4

GPIOE[3]/DSR#

5

GPIOE[4]/CTS#

84

GPIOE[5]/DTR#

83

GPIOE[6]/RI#

6

GPIOE[7]/DCD#

65

GPIOB[0]/INIT#

66

GPIOB[1]/SLCTIN#

67

GPIOC[2]/SCLT

68

GPIOC[3]/PE

69

GPIOC[4]/BUSY

70

GPIOC[5]/ACK#

71

GPIOC[6]/ERROR#

73

GPIOC[7]/ALF#

74

GPIOD[0]/STROBE#

75

GPIOC[1]/PD7

76

GPIOC[0]/PD6

77

GPIOB[7]/PD5

78

GPIOB[6]/PD4

79

GPIOB[5]/PD3

80

GPIOB[4]/PD2

81

GPIOB[3]/PD1

82

GPIOB[2]/PD0

61

GPIOD[1]

62

GPIOD[2]

63

GPIOD[3]/VBUS_DET

28

GPIOD[4]/OCS1_N

29

GPIOD[5]/OCS2_N

30

GPIOD[6]/OCS3_N

31

GPIOD[7]/OCS4_N

32

GPIOH[6]

33

GPIOH[7]

88

GPIOG[0]

89

GPIOG[1]

90

GPIOG[2]

91

GPIOG[3]

92

GPIOG[4]

93

GPIOG[5]

94

GPIOG[6]

95

GPIOG[7]

106

SYSOPT1/GPIOH[2]

107

SYSOPT0/GPIOH[3]

109

GPIOF[7]

110

GPIOF[6]

111

GPIOF[5]

112

GPIOF[4]

113

IRTX

12

114

IRRX

115

GPIOF[3]/IRMODE/IRRX3B

116

GPIOF[2]/IRTX2

117

GPIOF[1]/IRRX2

118

GPIOF[0]/IRMODE/IRRX3A

ECE5028-NU_VTQFP128_14X14~D

+3.3V_ALW

34

57

85

108

VCC1

VCC1

VCC1

VCC1

ECE5028-NU

(ECE5018)

USB

GPIO

TEST

CLK

LPC

DLPC

VCC1(VDDA33)

GPIOJ[7](VDDA33)

GPIOK[4](VDDA33)

GPIOI[1](VCC1)

GPIOJ[2](USBDP0)
GPIOJ[3](USBDN0)
GPIOJ[6](USBDP1)
GPIOJ[5](USBDN1)
GPIOK[0](USBDP2)

GPIOK[1](USBDN2)

GPIOK[3](USBDP3)

GPIOK[2](USBDN3)

GPIOK[5](USBDP4)

GPIOK[6](USBDN4)

GPIOI[6](VDDA33PLL)
GPIOI[5](VDDA18PLL)

GPIOI[2](VDD18)

CAP_LDO

GPIOJ[0](RBIAS)

TEST_PIN

GPIOI[7](ATEST)

GPIOI[4](XTAL1/CLKIN)

GPIOI[3](XTAL2)

LAD0
LAD1
LAD2
LAD3

LFRAME#

LRESET#

PCICLK

CLKRUN#

LDRQ0#
LDRQ1#

SER_IRQ

CLKI (14.318 MHz)

VSS

DLAD0
DLAD1
DLAD2
DLAD3

DLFRAME#

DCLK_RUN#

DLDRQ1#

DSER_IRQ

PWRGD

OUT65

GPIOJ[4](VSS)

VSS

GPIOK[7](VSS)

VSS
VSS
VSS
VSS
VSS

GPIOJ[1](VSS)

1

C101

0.1U_0402_16V4Z~D

2

8
14
20

119
9

10
13
12
15
16
19
18
21
22

125
124
120
86
127

TEST_PIN is a No Connect

35

126
123

122

1

2

LPC_LAD0
LPC_LAD1
LPC_LAD2
LPC_LAD3
LPC_LFRAME#
PLTRST2#
CLK_PCI_5018
CLKRUN#
LPC_LDRQ0#
LPC_LDRQ1#
IRQ_SERIRQ

CLK_SIO_14M

D_LAD0
D_LAD1
D_LAD2
D_LAD3
D_LFRAME#
D_CLKRUN#
D_DLRQ1#
D_SERIRQ

RUNPWROK
LCD_TST

C421

4.7U_0603_6.3V4Z~D

54
52
49
47
42
41
56
37
46
44
39

64
96
55

53
50
48
43
38
45
40

7
105

11
17
23
36
51
72
87
121
128

RBIAS

12

R227

@

1 2

R72

@

10K_0402_5%~D

1

C401

2

@

0.1U_0402_16V4Z~D

1

2

Route RBIAS and its
return to pin 128 very
short.

12K_0402_1%~D

1

C97

2

@

4.7U_0603_6.3V4Z~D

1

C420

0.1U_0402_10V7K~D

2

C98

0.1U_0402_16V4Z~D

SIO_VDDA

1

2

@

REG_EN

LPC_LAD[0..3] 22,28,39

LPC_LFRAME# 22,28,39
PLTRST2# 21,39
CLK_PCI_5018 6

CLKRUN# 23,30,39

LPC_LDRQ0# 22

LPC_LDRQ1# 22

IRQ_SERIRQ 23,28,30,39

CLK_SIO_14M 6

D_LAD0 36

D_LAD1 36

D_LAD2 36

D_LAD3 36

D_LFRAME# 36

D_CLKRUN# 36

D_DLRQ1# 36

D_SERIRQ 36

RUNPWR OK 39,42,48,54

LCD_TST 19

1

C92

2

@

4.7U_0603_6.3V4Z~D

1

C90

2

0.1U_0402_16V4Z~D

+3.3V_ALW

12

1

C94

2

@

0.1U_0402_16V4Z~D

R221

@

10K_0402_5%~D

1

C403

0.1U_0402_16V4Z~D

2

R814

1 2

0_0603_5%~D

1

1

C93

C88

2

2

@

0.1U_0402_16V4Z~D

4.7U_0603_6.3V4Z~D

+3.3V_ALW

LID_CL_SIO# LID_CL#

C89

@

4.7U_0603_6.3V4Z~D

D_CLKRUN#
D_SERIRQ
D_DLRQ1#

12

R95
1M_0402_5%~D

10_0402_5%~D

1

C84

0.047U_0402_16V4Z~D

2

1

C95

0.1U_0402_16V4Z~D

2

+3.3V_ALW

R231 100K_0402_5%~D
R232 100K_0402_5%~D
R234 100K_0402_5%~D

R94

12

Place closely pin 56

CLK_PCI_5018

R240

10_0402_5%~D

4.7P_0402_50V8C~D

C402

12
12
12

12

@

1

2

@

+3.3V_RUN

LID_CL# 40

R238

R107

A A

R108

BID0
BID1
CHIPSET_ID

5

R106 10K_0402_5%~D@

1 2

R109 10K_0402_5%~D@

1 2

R236 10K_0402_5%~D

1 2

1 2

1 2

1 2

10K_0402_5%~D

10K_0402_5%~D

10K_0402_5%~D

@

REV BID1
X00

X01 0 1
X02 01
X03 1 1

4

BID0

00

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

2

DELL CONFIDENTIAL/PROPRIETARY

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.
ECE5028

LA-3302P

38 66Thursday, March 01, 2007

1

of

0.4

5

+3.3V_ALW

SNIFFER_GREEN#

1 2

R77 100K_0402_5%~D@
R104 100K_0402_5%~D@
R105 2.2K_0402_5%~D
R111 2.2K_0402_5%~D
R401 100K_0402_5%~D

D D

R795
0_0402_5%~D

+5V_RUN

R88 4.7K_0402_5%~D

R87 4.7K_0402_5%~D

R86 4.7K_0402_5%~D

R85 4.7K_0402_5%~D

C C

Molex_53261

JDEBUG

@

Place closely pin 58

4.7P_0402_50V8C~D

B B

SNIFFER_YELLOW#

1 2

CKG_SMBDAT

1 2

CKG_SMBCLK

1 2

BC_DAT

1 2

ATI_ Intel_IDENTIFY

12

1 2

1 2

1 2

1 2

CLK_KBD

DAT_KBD

CLK_DOCK

DAT_DOCK

5

5

4

4

3

3

2

2

1

1

R1752 no stuff when doing
flash recovery

CLK_PCI_5025

R83

10_0402_5%~D

@

C81

@

+3.3V_ALW

12

12

R395

R100

1M_0402_5%~D

8051_RX

8051_TX 8051_TX

1 2

R101 0_0402_5%~D

12

1

2

12

R90

10K_0402_5%~D

10K_0402_5%~D

DEBUG_ENABLE#

R387 2.7K_0402_5%~D
R388 1M_0402_5%~D
R389 2.7K_0402_5%~D

1 2

R526 100K_0402_5%~D

1 2

R788 2.7K_0402_5%~D

1 2

R789 2.7K_0402_5%~D@

32 KHz Clock

12
12
12

1.8V_SUS_PWRGD46

EC_CPU_PROCHOT#7

ICH_CL_PWROK10,23

ICH_RSMRST#23

ALW_PWRGD_3V_5V45,46

SNIFFER_GREEN#43

ICH_EC_S PI_CLK23
ICH_EC_SPI_DIN23
ICH_EC_SPI_DO23

SIO_PWRBTN#23

SNIFFER_YELLOW#43

MEC5004_XTAL2

SUS_ON

M_ON
RUN_ON
DDR_ON
AUX_ON
AC_OFF

T36PAD~D

T33PAD~D
T34PAD~D

T35PAD~D

R214 0_0402_5%~D

12

CKG_SMBDAT
CKG_SMBCLK
ATI_ Intel_IDENTIFY

3.3V_M_PWRGD

1.8V_SUS_PWRGD
EC_CPU_PROCHOT#

ICH_CL_PWROK
ICH_RSMRST#

M_ON
SIO_SLP_M#
DDR_ON
TP_DET#
ALW_PWRGD_3V _5V
SIO_SLP_S3#
SIO_SLP_S5#

3.3V_RUN_ON
AUX_ON

SUS_ON
RUN_ON
AC_OFF

1.05V_1.25V_M_PWRGD
BC_A_INT#
BC_A_DAT
BC_A_CLK

SIO_A20GATE
SNIFFER_GREEN#

CLK_TP_SIO
DAT_TP_SIO
CLK_KBD
DAT_KBD
CLK_DOCK
DAT_DOCK
8051_RX

PLTRST2#
CLK_PCI_5025
LPC_LFRAME#
LPC_LAD0
LPC_LAD1
LPC_LAD2
LPC_LAD3
CLKRUN#
IRQ_SERIRQ

ICH_EC_ S PI _CLK
ICH_EC_SPI_DIN
ICH_EC_SPI_DO

EC_FLASH_SPI_CLK
EC_FLASH_SPI_DIN
EC_FLASH_SPI_DO

SIO_PWRBTN#
SNIFFER_YELLOW#

BC_CLK
BC_DAT
BC_INT#

MEC5004_XTAL1

MEC5004_XOSEL

R213
10K_0402_5%~D

CKG_SMBDAT6
CKG_SMBCLK6

DDR_ON46
TP_DET#40

SIO_SLP_S3#23
SIO_SLP_S5#23

3.3V_RUN_ON41
AUX_ON41

SUS_ON41,42
RUN_ON19,37,41,42,51

AC_OFF44

BC_A_INT#37
BC_A_DAT37
BC_A_CLK37

SIO_A20GATE22

CLK_TP_SIO40
DAT_TP_SIO40
CLK_KBD36
DAT_KBD36
CLK_DOCK36
DAT_DOCK36

8051_RX34
8051_TX34

PLTRST2#21,38

CLK_PCI_50256

LPC_LFRAME#22,28,38

LPC_LAD022,28,38
LPC_LAD122,28,38
LPC_LAD222,28,38

LPC_LAD322,28,38
CLKRUN#23,30,38
IRQ_SERIRQ2 3 , 28,30, 38

BC_CLK38

BC_DAT38
BC_INT#38

Same as Laguna

MEC5004_XTAL1

Y1

32.768K_12.5P_1TJS125DJ4A420P~D

MEC5004_XTAL2

C379

33P_0402_50V8J~D

14
23

1

2

1

C385

2

22P_0402_50V8J~D

Net & Part AMT Intel Non-AMT Broacom

3.3V_M_PWRGD
CH_RSMRST#
M_ON

A A

SIO_SLP_M#

1.05V_1.25V_M_PWRGD
R238
LOM_SUPER_IDDQ
LOM_LOW_PWR
LOM_CABLE_DETECT

5

+RTC_CELL

12

4

1 2

R70

0_0402_5%~D

BLM18AG121SN1D_0603~D

1

2

U22

12

KSO17/GPIOA1/AB1H_DATA

13

KSO16/GPIOA0/AB1H_CLK

14

GPIO5/KSO15

15

GPIO4/KSO14

16

KSO13/GPIO18

17

KSO12/OUT8

18

KSO11/GPIOC7

19

KSO10/GPIOC6

20

KSO9/GPIOC5

23

KSO8/GPIOC4

24

KSO7/GPIO3

25

KSO6/GPIO2

27

KSO5/GPIO1

28

KSO4/GPIO0

29

KSO3/GPIOC3

30

KSO2/GPIOC2

31

KSO1/GPIOC1

32

KSO0/GPIOC0

33

KSI7/GPIO19

34

KSI6/GPIO17

35

KSI5/GPIO10

36

KSI4/GPIO9

37

KSI3/GPIO8

38

KSI2/GPIO7/BC_A_INT#

39

KSI1/GPIO6/BC_A_DAT

40

KSI0/SGPIO30/BC_A_CLK

92

SGPIO34/A20M

50

OUT5/KBRST

75

GPIO94/IMCLK

76

GPIO95/IMDAT

77

KCLK

78

KDAT

79

GPIOA6/EMCLK

80

GPIOA7/EMDAT

81

GPIO20/PS2CLK/8051RX

82

GPIO21/PS2DAT/8051TX

57

LRESET#

58

PCICLK

59

LFRAME#

60

LAD0

61

LAD1

62

LAD2

63

LAD3

64

CLKRUN#

56

SER_IRQ

102

HSTCLK

105

HSTDATAIN

107

HSTDATAOUT

103

FLCLK

106

FLDATAIN

108

FLDATAOUT

109

GPIO80

110

GPIO81

87

BC_CLK

86

BC_DAT

85

BC_INT#

122

XTAL1

124

XTAL2

123

XOSEL

L24

Pin15 of 5025
Pin23 of 5025
Pin24 of 5025
Pin25 of 5025
Pin37 of 5025
Pin24 of 5025
NC
NC
NC

4

C75

0.1U_0402_16V4Z~D

AGND

VSS26VSS51VSS74VSS88VSS

125
12

+3.3V_ALW

121

116

VCC0

VCC121VCC144VCC165VCC183VCC1

VR_CAP22VSS_PLL

113

1

C74

2

4.7U_0603_6.3V4Z~D

NC
NC
NC
NC
NC
NC
Refer to UMA
Refer to UMA
Refer to UMA

1

C83

0.1U_0402_16V4Z~D

2

POWER_ SW_IN2#/GPIO23
POWER_ SW_IN1#/GPIO22

SGPIO45/MSDATA/SPDOUT2

SYSOPT0/SGPIO32/LPC_TX
SYSOPT1/SGPIO33/LPC_RX

101

ALWON

POWER_ SW_IN0#

ACAV_IN

BGPO0/GPIOA5

AB1B_CLK/GPIOA4

AB1B_DATA/GPIOA2

AB1A_CLK

AB1A_DATA

GPIO11/AB2_DATA

GPIO12/AB2_CLK

GPIO13/AB1G_DATA

GPIO14/AB1G_CLK

GPIO87/AB1C_DATA

GPIO86/AB1C_CLK

GPIO85/AB1D_DATA

GPIO84/AB1D_CLK

GPIO93/AB1F_DATA

GPIO92/AB1F_CLK

GPIO91/AB1E_DATA

GPIO90/AB1E_CLK

GPIO82/FAN_TACH3
GPIO16/FAN_TACH2
GPIO15/FAN_TACH1

OUT2/PWM3

OUT9/PWM2
OUT11/PWM1
OUT10/PWM0

nEC_SCI/SPDIN2

SGPIO44/MSCLK/SPCLK2

SGPIO46/SPDIN1

SGPIO47/SPDOUT1

SGPIO31/TIN1/SPCLK1

SGPIO40
SGPIO41
SGPIO42
SGPIO43

SGPIO35

SGPIO36 (SFPI_EN)

SGPIO37

GPIO96/TOUT1

OUT7/nSMI
nPWR_LED

nBAT_LED

nFWP

GPIOA3/WINDMON

GPIO83/32KHZ_OUT

PWRGD

nRESET_OUT/OUT6

TEST_PIN

VCC_PLL

MEC5025-NU_VTQFP128~D

104

C80

1 2

12

0.1U_0402_16V4Z~D

1 2

L3

BLM18AG121SN1D_0603~D

3

1

C79

0.1U_0402_16V4Z~D

2

120
119
126
127
128
118

8
7
6
5
93
94
95
96
111
112
9
10
97
98
99
100

43
42
41

48

R176 0_0402_5%~D

47
46
45

66
55
54
69
68
67

70
71

91
90
89
4

1
2
3

52
11

115
114

84
73
117
49
53

MEC_TEST_PIN

72

L6
BLM18AG121SN1D_0603~D

FWP#

Flash write protect bottom 4K
of internal bootblock flash

3

1

C76
10U_0805_10V4Z~D

2

ALWON
SNIFFER_PWR_SW#
POWER_SW_IN1#
POWER_SW_IN#
ACAV_IN
SNIFFER_RTC_GPO

LCD_SMBCLK
LCD_SMBDAT
DOCK_SMB_CLK
DOCK_SMB_DAT

1.8V_RUN_ON
LCD_VCC_TEST_EN

PBAT_SMBDAT
PBAT_SMBCLK
SBAT_SMBDAT
SBAT_SMBCLK

1.5V_RUN_ON

1.25V_RUN_ON
THRM_SMBDAT
THRM_SMBCLK

IMVP_PWRGD
FAN1_TACH

1 2

BREATH_LED
SIO_EXT_SCI#

PS_ID
SIO_RCIN#
BEEP

1.25V_GFX_PCIE_ON
DEBUG_ENABLE#

HOST_DEBUG_TX
HOST_DEBUG_RX

NUM_LED#
SIO_SPI_CS#

LOM_SMB_ALERT#
SFPI_EN
DOCK_SMB_ALERT#

0.9V_DDR_VTT_ON
SIO_EXT_SMI#

BAT2_LED#
BAT1_LED#

FWP#

RUNPWROK
RESET_OUT#

12

Populate
for flash

R222

corruption
issue.

0_0402_5%~D

+3.3V_ALW

+3.3V_ALW

12

R92
100K_0402_5%~D

low=write protected

12

R93

@

100K_0402_5%~D

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

1

C82

0.1U_0402_16V4Z~D

2

ALWON 45
SNIFFER_PWR_SW# 43

ACAV_IN 18,49,50

T37 PAD~D

LCD_SMBCLK 19
LCD_SMBDAT 19
DOCK_SMB_CLK 36
DOCK_SMB_DAT 36

1.8V_RUN_ON 41

LCD_VCC_TEST_EN 19

T87 PAD~D
T88 PAD~D

PBAT_SMBDAT 44

PBAT_SMBCLK 44

SBAT_SMBDAT 44

SBAT_SMBCLK 44

1.5V_RUN_ON 47

1.25V_RUN_ON 51
THRM_SMBDAT 18 , 4 9
THRM_SMBCLK 18,49

IMVP_PWRGD 23,42,48

FAN1_TACH 18
IMVP_VR_ON 48

WLAN_3V_ENABLE 34

3.3V_SUS_ON 41

BREATH_LED 43

SIO_EXT_SCI# 23

PS_ID 44

SIO_RCIN# 22

BEEP 26

1.25V_GFX_PCIE_ON 54

HOST_DEBUG_TX 34
HOST_DEBUG_RX 34

CAP_LED# 43
SCRL_LED# 43
NUM_LED# 43

LOM_SMB_ALERT# 23,28

DOCK_SMB_ALERT# 36

0.9V_DDR_VTT_ON 46

SIO_EXT_SMI# 23
BAT2_LED# 43
BAT1_LED# 43

RUNPWROK 38,42,48,54
RESET_OUT# 42

T39 PAD~D

1

2

Bat2 = Amber LED
Bat1 = Green LED

20mA drive pins

2

C369

0.1U_0402_16V4Z~D

+3.3V_ALW

C146

@

0.1U_0402_16V4Z~D

1 2

5

U30

SIO_SPI_CS#

ICH_SPI_CS0#23

Layout Note:
Place R84 within 500 mils from SPI flash.

Place R32 & R33 within 500 mils of the
MEC5025.

SPI_CS0#
EC_FLASH_SPI_DIN

R84 place close to
Flash ROM

1
2

1 2

R84

15_0402_5%~D

@

P

IN1

4

O

IN2

G

74AHC1G08GW_SOT353-5~D

3

1 2

R397

0_0402_5%~D

+3.3V_SUS

12

R219
10K_0402_5%~D

+RTC_CELL

POWER_SW_IN# POWER_SW#

C368

1U_0603_10V4Z~D

R396

@

15_0402_5%~D

1 2

U23

1

CS#

2

SO

HOLD#

3

WP#

4

GND

M25P16-VMW6TP_SO8~D

Flash ROM

200 MIL SO8

DELL CONFIDENTIAL/PROPRIETARY

Title

Size Do c um e n t N u mb er Re v

2

Date: Sheet

1

12

R211
100K_0402_5%~D

R210

10K_0402_5%~D

1 2

1

2

POWER_SW_IN1#

DOCK_SMB_DAT
DOCK_SMB_CLK

DOCK_SMB_ALERT#
LCD_SMBCLK
LCD_SMBDAT
THRM_SMBDAT
THRM_SMBCLK
SBAT_SMBDAT
SBAT_SMBCLK
PBAT_SMBDAT
PBAT_SMBCLK
HOST_DEBUG_RX

LOM_SMB_ALERT#

SPI_CS0#

VCC

SCLK

SI

R69 100K_0402_5%~D

EC_FLASH_PAD
@SHORT PADS~D

R76

SFPI_EN

1K_0402_5%~D

1=Flash Recovery Enabled
0=Flash Recovery Disabled

C398

1 2

0.1U_0402_16V4Z~D

12

R218

10K_0402_5%~D

8

15_0402_5%~D

7
6
5

1 2

1 2

R399
15_0402_5%~D

R67 8.2K_0402_5%~D
R66 8.2K_0402_5%~D

R794 10K_0402_5%~D
R161 8.2K_0402_5%~D
R162 8.2K_0402_5%~D
R64 4.7K_0402_5%~D
R65 4.7K_0402_5%~D
R75 2.2K_0402_5%~D
R81 2.2K_0402_5%~D
R62 2.2K_0402_5%~D
R63 2.2K_0402_5%~D
R400 1M_0402_5%~D

R730 4.7K_0402_5%~D

12

R398

Compal Electronics, Inc.
EMC5025

LA-3302P

1

POWER_SW# 18,40

12

12
12

12
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2

1 2

+3.3V_ALW

1

1

2

2

12

EC_FLASH_SPI _CLK
EC_FLASH_SPI_DO

R398, R399, place
close to M5025

39 66Thursday, March 01, 2007

+RTC_CELL

+5V_ALW

+3.3V_ALW

+3.3V_LAN

R80
1K_0402_5%~D

of

0.4

5

4

3

2

1

Touch PAD

JTPAD

2

112

COEX1_BT_ACTIVE34

USBP7-23
USBP7+23

+3.3V_RUN

TP_DET#39

+3.3V_ALW

1

C426

2

0.1U_0402_16V4Z~D

L4

@

DLW21SN900SQ2_0805~D

4

4

1

1

R407

0_0402_5%~D

1 2

R410

0_0402_5%~D

1 2

1

1

2

2

100P_0402_50V8J~D

100P_0402_50V8J~D

100P_0402_50V8J~D

@

@

@

C397

C380

C393

C419

USBP5-23

USBP5+23

1

2

100P_0402_50V8J~D

@

C394

1

2

33P_0402_50V8J~D

1

2

100P_0402_50V8J~D

@

C384

COEX2_WLAN_ACTIVE

LID_CL#38

1

1

1

2

2

2

100P_0402_50V8J~D

100P_0402_50V8J~D

@

@

C390

C386

COEX2_WLAN_ACTIVE34

100P_0402_50V8J~D

12

R249

10K_0402_5%~D

1

1

2

2

100P_0402_50V8J~D

100P_0402_50V8J~D

@

@

C383

C395

D D

KSO[0..17]37

KSI[0..7]37

C C

B B

POWER_SW#18,39
R_NUM_LED#43
R_CAP_LED#43
R_SCRL_LED#43

+3.3V_ALW

A A

KSO17
KSO16
KSO15
KSO14
KSO13
KSO12
KSO11
KSO10
KSO9
KSO8
KSO7
KSO6
KSO5
KSO4
KSO3
KSO2
KSO1
KSO0

KSI7
KSI6
KSI5
KSI4
KSI3
KSI2
KSI1
KSI0

KSO10
KSO11
KSO9
KSO14
KSO13
KSO15
KSO16
KSO12
KSO0
KSO2
KSO1
KSO3
KSO8
KSO6
KSO7
KSO4
KSO5
KSI0
KSI3
KSI1
KSI5
KSI2
KSI4
KSI6
KSI7
POWER_SW#
R_NUM_LED#
R_CAP_LED#
R_SCRL_LED#
KSO17

1

2

@

C387

100P_0402_50V8J~D

1

1

1

2

2

2

100P_0402_50V8J~D

100P_0402_50V8J~D

@

@

@

C392

C381

C382

USBP7­USBP7+

USBP5_D­USBP5_D+

1

1

C424

C423

2

2

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

USBP5_D-

3

3

USBP5_D+

2

2

KYBD_DET#37

1

1

2

100P_0402_50V8J~D

@

C371

1

1

1

2

100P_0402_50V8J~D

@

C372

1

2

2

2

2

100P_0402_50V8J~D

100P_0402_50V8J~D

100P_0402_50V8J~D

100P_0402_50V8J~D

@

@

@

@

C374

C378

C389

C376

334
556

7

8

7

9

10

9

11

12

11

13

14

13

15

16

15

17

18

17

19

20

19

21

22

21

23

24

23

25

26

25

27

28

27

29

30

29
G131G2

FOX_HT1315F-P2~D

+3.3V_ALW

12

1

1

2

2

100P_0402_50V8J~D

@

@

C396

C373

4
6
8
10
12
14
16
18
20
22
24
26
28
30
32

R575
100K_0402_5%~D

KYBD_DET#

1

1

2

2

100P_0402_50V8J~D

100P_0402_50V8J~D

@

@

C377

C391

BT_RADIO_DIS#
COEX3

SP_GND
SP_X
SP_Y
SP_V+

TP_CLK
TP_DATA

1

2

1

2

100P_0402_50V8J~D

100P_0402_50V8J~D

@

C375

C210

1

2

0.047U_0402_16V4Z~D

@

C388

1

2

100P_0402_50V8J~D

C430

0.1U_0402_16V4Z~D

1

2

100P_0402_50V8J~D

@

C78

BT_ACTIVE 34,43

12

R119

10K_0402_5%~D

+5V_RUN

SP_GND

SP_X
SP_V+
SP_Y

JKYBRD

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

11

11

12

12

13

13

14

14

15

15

16

16

17

17

18

18

19

19

20

20

21

21

22

22

23

23

24

24

25

25

26

26

27

27

28

28

29

29

30

30

GND

31

31

GND

32

32

33

33

34

34

FOX_GS12403-0001K-8F~D

T4 PAD~D

TP_DATA
TP_CLK

35

35

36

36

37

37

38

38

39

39

40

40

41
42

1

2

+3.3V_RUN

D37

@

DA204U_SOT323~D

BLM18AG601SN1D_0603~D

1

1

C86

2

2

10P_0402_50V8J~D

SP_GND

SP_X
SP_V+
SP_Y

BT_RADIO_DIS# 38

C103

100P_0402_50V8J~D

1

2

3

L25

1 2
1 2

L26
BLM18AG601SN1D_0603~D

C87

10P_0402_50V8J~D

+3.3V_RUN

FAN

Part Number Description

D40

@

3

DA204U_SOT323~D

DAT_TP_SIO 39
CLK_TP_SIO 39

Speak

Part Number Description

1

C102

0.1U_0402_16V4Z~D

2

1

2

12

1

2

1

D38

@

2

3

DA204U_SOT323~D

+5V_RUN

12

R228

4.7K_0402_5%~D

1

C400

2

10P_0402_50V8J~D

D39

@

3

R229

4.7K_0402_5%~D

DAT_TP_SIO
CLK_TP_SIO

C399

10P_0402_50V8J~D

1

2

DA204U_SOT323~D

FAN SET DAQ20 DC5V AB7405HB-HB3 ADDA

DC28A000800

SPK PACK ZJX 2.0W 4 OHM FG

PK230003Q0L

SM CARD BODY

Part Number Description

SP070007V0L

PCMCIA BODY

Part Number Description

DC000001Q0L

MDC wire set cable

Part Number Description

DC02000CS0L

T/P wire set cable

Part Number Description

DC02000840L

LVDS cable

Part Number Description

DC020003Y0L

LVDS cable

Part Number Description

DC02000870L

RTC BATT

Part Number Description

GC20323MX00

S SOCKET TYCO 1770551-1
10P H5.9 SMART

PCMCIA TYCO
1759096-1

H-CONN SET ZGX
MB-MDC

H-CONN SET ZJX
MB-B/T-TP-FP

H-CONN SET ZJX MB-LCD
14 WXGA+(-1ch)

H-CONN SET ZJX
MB-LCD 14 WXGA+(-2ch)

BATT CR2032 3V
220MAH MAXELL

Power Switch

POWER_SW#

C367

@

100P_0402_50V8J~D

1

2

PWR_SW

@SHORT PADS~D

112

2

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.
INT KB

LA-3302P

40 66Thursday, March 01, 2007

1

0.4

of

5

DC/DC Interface

+3.3V_ALW2

12

R621
100K_0402_5%~D

D D

SUS_ON39,42

C C

SUS_ON

RUN_ON19,37,39,42,51

13

D

Q51

2

2N7002W-7-F_SOT323-3~D

G

S

+3.3V_ALW2

12

R623
100K_0402_5%~D

RUN_ON_5V#

2N7002W-7-F_SOT323-3~D

13

D

2

G

Q55

S

2N7002W-7-F_SOT323-3~D

SUS_ON_5V#

2

2

Q53

+15V_ALW

G

+15V_ALW

G

12

R617
100K_0402_5%~D

SUS_ENABLE

13

D

Q49

S

2N7002W-7-F_SOT323-3~D

12

R624
100K_0402_5%~D

13

D

S

C815

4700P_0402_25V7K~D

RUN_ENABLE

1

2

4

6
2

1

+5V_ALW

Q52
SI4810BDY-T1-E3_SO8~D

8
7

5

Q80
SI3456BDV-T1-E3_TSOP6~D

D

+5V_ALW

1

C142

2

@

4700P_0402_25V7K~D

S

45

G

3

4

+5VSUS Source

+5V_SUS

1

C143

2

10U_0805_10V4Z~D

+5VRUN Source

+5V_RUN
1
2
36

1

C814

2

10U_0805_10V4Z~D

12

R762
20K_0402_5%~D

12

R625
20K_0402_5%~D

3

3.3V_SUS_ON39

2

+3.3V_ALW2

G

12

R765
100K_0402_5%~D

13

D

S

2

SUS_ON_3.3V#

Q87
2N7002W-7-F_SOT323-3~D

+15V_ALW

2

G

12

R764
100K_0402_5%~D

13

D

S

Q88
2N7002W-7-F_SOT323-3~D

+3.3V_ALW

8
7

5

1

Q47
SI4810BDY-T1-E3_SO8~D

+3VSUS Source

1
2
36

4

1

C195
4700P_0402_25V7K~D

2

@

C811

10U_0805_10V4Z~D

1

2

+3.3V_SUS

12

R620

20K_0402_5%~D

+1.8V_RUN Source

+15V_ALW

+3.3V_ALW2

12

R637
100K_0402_5%~D

13

D

Q65

1.8V_RUN_ON39

2

G

S

2N7002W-7-F_SOT323-3~D

12

R632

13

D

2

G

S

Q60
2N7002W-7-F_SOT323-3~D

100K_0402_5%~D

D35

@

RB751V_SOD323~D

1 2

R305

0_0402_5%~D

Q54

SI4336DY-T1-E3_SO8~D

8
7

5

21

4

1

2

+1.8V_RUN+1.8V_SUS

1
2
36

1

C816

2

10U_0805_10V4Z~D

C194

0.047U_0402_16V4Z~D

12

R628

20K_0402_5%~D

+3.3V_ALW

+PWR_SRC+PWR_SRC

12

12

R699
100K_0402_5%~D

N21917830

13

D

AUX_ON39

2N7002W-7-F_SOT323-3~D

B B

A A

2

G

Q73

R701

S

200K_0402_5%~D

R698
100K_0402_5%~D

13

D

2

G

12

Q72

S

2N7002W-7-F_SOT323-3~D

12

1

2

C208

R700

4700P_0402_25V7K~D

ENAB_3VLAN 28

470K_0402_5%~D

3.3V_RUN_ON39

+3.3V_ALW2

2

G

12

R766
100K_0402_5%~D

13

D

S

Q90
2N7002W-7-F_SOT323-3~D

Discharg Circuit

75_0603_5%~D

Q91

2N7002W-7-F_SOT323-3~D

12

R118

@

13

D

2

G

S

@

1K_0402_5%~D

Q92

2N7002W-7-F_SOT323-3~D

12

R117

@

1K_0402_5%~D

13

D

2

Q93

G

S

@

2N7002W-7-F_SOT323-3~D

RUN_ON_5V#

2

G

SUS_ON_3.3V#

12

R151

@

13

D

2

G

S

@

+15V_ALW

12

R641
100K_0402_5%~D

13

D

2

G

S

Q89
2N7002W-7-F_SOT323-3~D

D36

@

RB751V_SOD323~D

1 2

R413

0_0402_5%~D

Discharg Circuit

1K_0402_5%~D

Q61

2N7002W-7-F_SOT323-3~D

12

R634

@

1K_0402_5%~D

13

D

2

G

2

G

Q62

S

@

2N7002W-7-F_SOT323-3~D

12

R633

@

13

D

S

@

21

+1.5V_RUN +0.9V_DDR_VTT+3.3V_RUN+5V_RUN

1K_0402_5%~D

Q63

2N7002W-7-F_SOT323-3~D

12

R636

@

13

D

2

G

S

@

12

R635

@

13

D

S

@

+3.3V_RUN Source

Q10

@

SI4810DY-T1-E3_SO8~D

8
7

5

Q58

SI4336DY-T1-E3_SO8~D

8
7

5

+1.8V_RUN

12

@

1K_0402_5%~D

13

D

2

G

Q64

S

2N7002W-7-F_SOT323-3~D

4

4

1

C144
470P_0402_50V7K~D

2

@

R729

1K_0402_5%~D

2

Q81

@

2N7002W-7-F_SOT323-3~D

1
2
36

+3.3V_RUN

1
2
36

+1.25V_RUN+1.8V_SUS +5V_SUS +3.3V_SUS

G

C819

10U_0805_10V4Z~D

12

13

D

S

12

1

R630

2

20K_0402_5%~D

R113

@

1K_0402_5%~D

Q30

@

2N7002W-7-F_SOT323-3~D

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.
POWER CONTROL

LA-3302P

41 66Thursday, March 01, 2007

1

0.4

of

5

D D

+5V_RUN

1

2

+1.8V_RUN

1

2

+3.3V_RUN

C C

1

2

D25

2 1

RB751V_SOD323~D

C46

0.1U_0402_16V4Z~D

D26

2 1

RB751V_SOD323~D

C47

0.1U_0402_16V4Z~D

D27

2 1

RB751V_SOD323~D

C49

0.1U_0402_16V4Z~D

12

R68

12

R616

12

R82

1

2

200K_0402_5%~D

1

2

200K_0402_5%~D

1

2

200K_0402_5%~D

R334

10K_0402_5%~D

1 2

C17
2200P_0402_50V7K~D

R364

10K_0402_5%~D

1 2

C19
2200P_0402_50V7K~D

R367

10K_0402_5%~D

1 2

C27
2200P_0402_50V7K~D

+5V_ALW

E

3

Q77

B

MMBT3906WT1G_SC70-3~D

2

C

1

+1.8V_SUS

E

3

Q78

B

MMBT3906WT1G_SC70-3~D

2

C

1

+3.3V_ALW

E

3

Q79

B

MMBT3906WT1G_SC70-3~D

2

C

1

R133

4.7K_0402_5%~D

1 2

R134

4.7K_0402_5%~D

1 2

R164

4.7K_0402_5%~D

1 2

4

1.25V_RUN_PWRGD51

2.5V_RUN_PWRGD18

1.5V_RUN_PWRGD47

1.05V_RUN_PWRGD47

GFX_CORE_PWRGD51

C

Q84

2

B

MMST3904-7-F_SOT323-3~D

E

3 1

C

Q85

2

B

MMST3904-7-F_SOT323-3~D

E

3 1

C

Q86

2

B

MMST3904-7-F_SOT323-3~D

E

3 1

1 2

R486 0_0402_5%~D

R216 0_0402_5%~D@

R207 0_0402_5%~D

R208 0_0402_5%~D

R185 0_0402_5%~D

12

12

12

12

5V_3V_1.8V_1.25V_RUN_PWRGD 38

3

+3.3V_SUS

12

R132
20K_0402_5%~D

3VRUNRC

1

C134

0.01U_0402_16V7K~D

2

+3.3V_ALW

C135

0.1U_0402_16V4Z~D

1 2

8

U12A

P

7

A1Y

G

74LVC3G14DC_VSSOP8~D

4

IMVP_PWRGD23,39,48

RESET_OUT#39

+3.3V_ALW

8

U12B

P

A6Y

G

74LVC3G14DC_VSSOP8~D

4

RUN_ON19,37,39,41,51

SUS_ON39,41

74VHC08MTCX_NL_TSSOP14~D

IMVP_PWRGD
RESET_OUT#

74VHC08MTCX_NL_TSSOP14~D

U27B

2

+3.3V_ALW

4

IN1

5

IN2

1 2

R418
0_0402_5%~D

14

P
OUT

G

7

2

6

U27C

+3.3V_ALW

14

1

IN1

2

IN2

7

+3.3V_ALW

14

10

IN1

9

IN2

7

ICH_PWRGD

C458

0.1U_0402_16V4Z~D

1 2

U27A
74VHC08MTCX_NL_TSSOP14~D

P

3

OUT
G

13
12

P

8

OUT
G

R79

100K_0402_5%~D

2

G

+3.3V_SUS

+3.3V_ALW

8

U12C

P

A3Y

G

74LVC3G14DC_VSSOP8~D

4

+3.3V_ALW

14

U27D

P

IN1

11

OUT

IN2

G

74VHC08MTCX_NL_TSSOP14~D

7

12

ICH_PWRGD#

13

D

Q17
2N7002W-7-F_SOT323-3~D

S

5

RUNPWROK

ICH_PWRGD# 18

ICH_PWRGD 10,23

1

RUNPWR OK 38,39,48,54

SUSPWROK 18

B B

A A

+3.3V_SUS

1

C457

0.1U_0402_16V4Z~D

2

+5V_SUS

1

C199

0.1U_0402_16V4Z~D

2

D23

RB751V_SOD323~D

2 1

D31

RB751V_SOD323~D

2 1

R159

10K_0402_5%~D

R139

R158

200K_0402_5%~D

200K_0402_5%~D

1 2

1

C422

2

2200P_0402_50V7K~D

10K_0402_5%~D

1 2

1

C404

2

2200P_0402_50V7K~D

R160

12

12

E

3

B

Q20

2

MMBT3906WT1G_SC70-3~D

C

1

12

R135

200K_0402_5%~D

+5V_ALW

E

3

B

Q26

2

MMBT3906WT1G_SC70-3~D

C

1

12

R157

200K_0402_5%~D

D32

2 1

RB751V_SOD323~D

D33

RB751V_SOD323~D

2 1

+3.3V_ALW+3.3V_ALW

A6Y

12

R136
200K_0402_5%~D

C186

0.1U_0402_16V4Z~D

1 2

8

U48B

P

2

G

74LVC3G14DC_VSSOP8~D

4

3.3V_5V_SUS_PWRGD

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.
Power Good

LA-3302P

42 66Thursday, March 01, 2007

1

0.4

of

5

H1

H_C146B217D91

1

H10

@H_C236B315D110

1

D D

H20

@H_C217B276D98

1

C C

B B

A A

H2
H_C146B217D91

1

H11
@H_C315B236D118

1

H26

@H_C472D376

1

This circuit is
only needed if the
platform has the
SNIFFER.

SATA_ACT#_R22

LED_MASK#38

+COINCELL

12

R21
1K_0402_5%~D

Z4012

3

2

D13

1

BAT54CW_SOT323~D

SNIFFER_YELLOW#39

SNIFFER_GREEN#39

1

2

H3

@H_C315D110

1

H12
@H_C315D118

1

H27

@H_C472D431X376

1

+3.3V_RUN

12

R78
10K_0402_5%~D

+3.3V_ALW

12

COIN RTC Battery

+COINCELL

+RTC_CELL

C370
1U_0603_10V4Z~D

+3.3V_SUS

2

1 3

+3.3V_SUS

2

1 3

5

H5

H4

@H_C236B315D110

H_C256B63D47

1

H13

@H_C315D118

1

H28

@H_O115X31D115X31N

1

R140
0_0402_5%~D @

1 2

S

G

R97
10K_0402_5%~D

@

COINCELL

Q32
PDTA114EU_SC70-3~D

Q33
PDTA114EU_SC70-3~D

1

H14

@H_C291B236D118

1

H29

@H_O115X31D115X31N

1

D

13

Q23

BSS138W-7-F_SOT323~D

2

JCOIN

1

1

2

2

MOLEX_53398-0271~D

1 2

R261 220_0402_5%~D

1 2

R262 220_0402_5%~D

H6

@H_C236B256D110

1

H15
@H_C295D118

1

SATA_ACT#

SNIFFER_Y
SNIFFER_G

@H_O115X31D115X31N

+3.3V_RUN

H7
@H_C236B315D110

1

H16
@H_C217B276D98

1

H30

1

12

R181
100K_0402_5%~D

@

1 2

R179
0_0402_5%~D

4

H8

@H_C217B276D98

1

H17
@H_C217B276D98

D14

Y

3
2

G

12-22AUYSYGC/530-A2/TR8_G/Y~D

4

H18

@H_C217D91

1

1

+3.3V_RUN

2

1 3

LED_WLAN_OUT#34

WIRELESS_ON/OFF#38

SNIFFER_PWR_SW#39

1

H9

@H_C236B315D110

1

H19

@H_C217D91

1

Q22
PDTA114EU_SC70-3~D

R145

330_0402_5%~D

1 2

47K_0402_5%~D

1 2

R639

10K_0402_5%~D

R180

3

EMI CLIP

CLIP4
EMI_CLIP

1

GND

CLIP6
EMI_CLIP

1

GND

CLIP1
EMI_CLIP

1

GND

HDD_LED 32

R_PIDEACT 36

+3.3V_WLAN

+3.3V_RUN

12

R638

E

3

B

Q5

2

MMBT3906WT1G_SC70-3~D

C

1

R15

1 2

150_0402_5%~D

+3.3V_RUN+RTC_CELL

12

12

R102
100K_0402_5%~D

100K_0402_5%~D

JSNIFF

6

4

4

3

3

2

2

1

1

5

1

1

BT_ACTIVE34,40

LED_MASK#38

R_MPCI_ACT

6

5

1BS008-13130-7F_4P~D

CLIP3
EMI_CLIP

GND

CLIP2
EMI_CLIP

GND

BT_ACTIVE

R_MPCI_ACT 32

R74

10K_0402_5%~D

1 2

E

3

B

2

1

BAT1_LED#39

BAT2_LED#39

2

FIDUCIAL MARK~D

FIDUCIAL MARK~D

FIDUCIAL MARK~D

FIDUCIAL MARK~D

CAP_LED#39

NUM_LED#39

SCRL_LED#39

13

D

2

G

Q29
BSS138W-7-F_SOT323~D

S

Q18
MMBT3906WT1G_SC70-3~D

C

BREATH_LED39

BAT1_LED#

BAT2_LED#

Fiducial Mark

FIDUCIAL MARK~D

FIDUCIAL MARK~D

FIDUCIAL MARK~D

FIDUCIAL MARK~D

R226

330_0402_5%~D

R224

330_0402_5%~D

R225

330_0402_5%~D

Q28
PDTA114EU_SC70-3~D

1 3

R212
1K_0402_5%~D

1 2

+3.3V_SUS+3.3V_RTC_LDO

+3.3V_ALW

2

+3.3V_ALW

2

FD2

1

FD11

1

FD9

1

FD18

1

12

12

12

5

1

U43

P

NC

A2Y

G

NC7SZ04P5X_NL_SC70-5~D

3

Q1
PDTA114EU_SC70-3~D

1 3

Q4
PDTA114EU_SC70-3~D

1 3

FD1

1

FD13

1

FD22

1

FD17

1

+5V_RUN

2

R_BT_ACT

4

FD5

1

FIDUCIAL MARK~D

FD14

1

FIDUCIAL MARK~D

FD24

1

FIDUCIAL MARK~D

FD3

1

FIDUCIAL MARK~D

R_CAP_LED#

R_NUM_LED#

R_SCRL_LED#

R_BT_ACT 32

R71

100_0402_5%~D

1 2

R6

1 2

220_0402_5%~D

R9

1 2

220_0402_5%~D

FIDUCIAL MARK~D

FIDUCIAL MARK~D

1

FIDUCIAL MARK~D

1

FIDUCIAL MARK~D

BATT_GREEN_LED

BATT_AMBER_LED

1

FD10

1

FD25

1

FD20

FD4

R_CAP_LED# 40

R_NUM_LED# 40

R_SCRL_LED# 40

BREATH_GREEN_LED 32

FD12

1

FIDUCIAL MARK~D

FD15

1

FIDUCIAL MARK~D

FD19

1

FIDUCIAL MARK~D

FD6

1

FIDUCIAL MARK~D

BATT_GREEN_LED 32

BATT_AMBER_LED 32

FD23

1

FIDUCIAL MARK~D

FD21

1

FIDUCIAL MARK~D

FD16

1

FIDUCIAL MARK~D

FD8

1

FIDUCIAL MARK~D

FD7

1

FIDUCIAL MARK~D

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

2

Title

Size Do c um e n t N u mb er Re v

Date: Sheet

Compal Electronics, Inc.
PAD and Standoff

LA-3302P

1

43 66Thursday, March 01, 2007

0.4

of

5

4

3

2

1

+3.3V_ALW

ESD Diodes

3

2

3

D D

PC231

Secondary Battery Connector

PJP1

BATT1+
BATT2+

12

2200P_0402_50V7K~D

SMB_DAT

BATT_PRES#

SYSPRES#

BATT_VOLT

10

GND

11

GND

TYCO_1734077-1~D

SMB_CLK

BATT1­BATT2-

1
2
3
4
5
6
7
8
9

Z4301
Z4302
Z4303

PD42

DA204U_SOT323~D @

PR301

100_0402_5%~D

1 2

+3.3V_ALW

1

PR302

100_0402_5%~D

1 2

PD43

DA204U_SOT323~D @

1

PR303

100_0402_5%~D

1 2

PD44
DA204U_SOT323~D @

100_0402_5%~D

1

PR304

1 2

2

3

PD45

1

DA204U_SOT323~D @

SBAT_SMBCLK 39
SBAT_SMBDAT 3 9

SBAT_ALARM#

FBMA-L18-453215-900LMA90T_1812~D

PC230

0.1U_0603_25V7K~D

12

PL32

1 2

PJP60

1 2

PAD-OPEN 4x4m

SBATT+

+3.3V_ALW

12

PR300

10K_0402_5%~D

SBAT_PRES# 38,50

2

3

2

ESD Diodes

2

3

2

3

PD10

1

DA204U_SOT323~D @

PR21

100_0402_5%~D

1 2

1

100_0402_5%~D

1 2

C C

PC10

Primary Battery Connector

PBATT1

SMB_CLK

BATT_PRES#

SYSPRES#

BATT_VOLT

10

GND

11

GND

SUYIN_2 00277MR009G 506ZR ~D

SMB_DAT

12

2200P_0402_50V7K~D

BATT1+
BATT2+

BATT1­BATT2-

1
2
3
4
5
6
7
8
9

Z4304
Z4305
Z4306

PD9

DA204U_SOT323~D @

PR20

100_0402_5%~D

1 2

PR22

3

PD11

100_0402_5%~D

2

1

DA204U_SOT323~D @

PR23

1 2

2

3

PD12

1

DA204U_SOT323~D @

PBAT_SMBCLK 39
PBAT_SMBDAT 3 9

PBAT_ALARM#

PC9

PL6

FBMA-L18-453215-900LMA90T_1812~D

1 2

PJP61

1 2

12

PAD-OPEN 4x4m

0.1U_0603_25V7K~D

PBATT+

+3.3V_ALW

12

PR19

10K_0402_1%~D

PBAT_PRES# 38

+5V_ALW

2

PR184

1 2

3

PD2

DA204U_SOT323~D

1

+5V_ALW

B B

PR346

@

1 2

0_0402_5%~D

GPIO Input from EC

Z-series AC Adaptor
Connctor

PJPDC1
TYCO_1566065-2~D

9

GND_4

8

GND_3

7

GND_2

6

GND_1

A A

MH1

MH2

Low_PWR

DC+_1
DC+_2

DC-_1
DC-_2

1
2
3
4
5

1

@

2

5

PL1

BLM18BD102SN1D_0603~D

FBCA-K5 B -302340-L1-T_1812~D

1 2

+DCIN_JACK

-DCIN_JACK

1 2

FBCA-K5 B -302340-L1-T_1812~D

PD59

VZ0603M260APT_0603

12

PL2

1

PD58

@

2

VZ0603M260APT_0603

PC397

@

PL34

AC_OFF39

@

IMD2AT- 108_SC74-6~D

IMD2AT- 108_S C 74-6~D

12

12

@

0.1U_0603_25V7K~D

5

PQ100A

+DC_IN

1
2

1 2

0.47U_0805_25V7k

3 6

12

PR11

240K_0402_5%~D

4

+DC_IN

PQ100B

PC2

@

43

2

PR495

0_0402_5%~D

16

PQ3

FDS6679AZ_SO8~D

4

12

PR13

47K_0402_1%~D

DOCK_PSID36

DC_IN+ Source

8
7

5

12

PC4

PC3

0.1U_0603_25V7K~D

THESE CAPS MUST BE
NEXT TO JCHG

2

3

+DC_IN_SS

12

0.1U_0603_25V7K~D

12

12

PC5

PR12

0.1U_0603_25V7K~D

1

PC6

2

4.7K_0805_5%
10U_1206_25V6M~D

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONF IDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVIS ION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INF ORMATION IT CONT AINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WR ITT EN CO NSE NT OF COMPAL ELECTRONICS, INC.

3

@

1

PD53
SM24_SOT23

PR6

PR10

1 2

100K_0402_1%~D

1 2

15K_0402_1%~D

1 3

2

B

D

S

PQ1

G

2

FDV301N_SOT23~D

C

PQ2
MMST3904-7-F_SOT323~D

E

3 1

2

33_0402_5%~D

+3.3V_ALW

PR2

1 2

2.2K_0402_5%~D

PS_ID 39

2

PSID_DISABLE# 38

12

PR7

10K_0402_1%~D

1 2

PR299

10K_0402_5%~D @

@

PD41

+5V_ALW

DA204U_SOT323~D

3

1

DELL CONFIDENTIAL/PROPRIETARY

Title

Size Do c um e n t N u mb er Re v

Date: Sheet

Compal Electronics, Inc.

+DCIN
LA-3302P

1

44 66Thursday, March 01, 2007

0.0

of

5

4

3

2

1

+3.3V_ALWP/ +5V_ALWP/ +5V_ALW2 / +15V_ALWP

PL36

THERM_STP#18

ALWON39

+DC1_PWR_SRC

8

PQ82

1

PQ84

123

12

PR379

PR380

PC286

1 2

PR500

PR376

@

10_0603_5%~D

32
31
30
29
28

EN_3V_5VEN _3V_ 5V

27

+3.3V_ALW_UGATE

26

+3.3V_ALW_PHASE

25

PR387

1_0603_5%~D

1 2

PJP34

1 2

PAD-OPEN1x1m

+5V_VCC1

12

12

PC283

1U_0603_10V6K~D

12

0_0402_5%~D

GNDA_3V5V

PR499

PR382

267K_0402_1%

1 2

PR517 0_0402_5%~D

12

POK2

12

PC288

0.1U_0603_25V7K~D

+3.3V_ALW_LGATE

PR501

@

0_0402_5%~D

GNDA_3V5V

GNDA_3V5V

1

1

12

12

2

2

PC275

PC274

0.1U_0805_50V7K

2200P_0402_50V7K~D

12

12

PC385

@

0.1U_0402_10V7K~D

+3.3V_ALWP

+3.3V_ALWP

PR390

PR391

@

1 2

1 2

100K_0402_1%~D

100K_0402_1%~D

POK2

12

PR393

POK1

0_0402_5%~D

5

PQ83

D

BSC079N03S G_PG-TDSON-8~D

4

G

S3S

S

2

1

3.0U_HMP1362-3R0-R_17A~D

786

5

PQ85
FDS6676AS_NL_SO8~D

4

123

ALW_PWRGD_3V_5V 39,46

PL37

PC277

PC276

10U_1206_25V6M~D

10U_1206_25V6M~D

3.3 Volt +/-5%
Thermal Design Current:9.0A
Peak current: 12.9A
OCP min:15.79A

+3.3V_ALWP

12

12

PR385

0_0402_5%~D

12

PR389

@

0_0402_5%~D

GNDA_3V5V

PC292

0.1U_0402_10V7K~D

1

12

+

PC290

2

330U_D3L_6.3VM_R25~D

PJP63

1 2

PR375

0_0805_5%

1 2

PC285

GNDA_3V5V

+5V_ALWP

POK1

GNDA_3V5V

PR386

1_0603_5%~D

+5V_ALW_LGATE

PC293

0.1U_0603_25V7K~D

1

1 2

PC295

0.1U_0603_25V7K~D

1

1 2

12

PC296

0.1U_0603_25V7K~D

+5V_ALW2

12

0.1U_0603_25V7K~D

9

BYP

10

OUT1

11

FB1

12

ILIM1

13

POK1

14

EN1

15

UGATE1

16

PHASE1

33

+5V_ALW_BOOT

3

PR397

200K_0402_1%~D

PAD-OPEN1x1m

EN_3V_5V

5

7

4

8

3

6

VIN

LDO

VREF3

EN_LDO

LDOREFIN

PU20

ISL6236IRZA_Q FN 32~D

BOOT117LGATE118PVCC19SECFB20GND21PGND22LGATE223BOOT2

PAD

GNDA_3V5V

PC403

+5V_ALW2

PD57

1

BAT54CW_SOT323~D

2

12

PR398

1 2

39.2K_0402_1%~D

GNDA_3V5V

PC282

4.7U_0805_6.3V6K

0_0402_5%~D@

1 2

0_0402_5%~D

1 2

0.1U_0603_25V7K~D

1 2

@

0_0402_5%~D

1

REF

TON2VCC

REFIN2

ILIM2
OUT2
SKIP#
POK2

EN2
UGATE2
PHASE2

24

+3.3V_ALW_BOOT

12

GNDA_3V5V

1U_0603_10V6K~D

PR374

1

1

12

12

PC279

PC278

2200P_0402_50V7K~D

D6D5D7D

G

S

S

S

3

2

786

5

0.1U_0805_50V7K

4

4

PR392

2K_0402_5%~D

PR395

0_0402_5%~D

12

12

2

2

PC281

PC280

10U_1206_25V6M~D

10U_1206_25V6M~D

12

PC386

@

0.1U_0402_10V7K~D

GNDA_3V5V

PR394

1 2

200K_0402_5%

+15V_ALW

PAD-OPEN1x1m

0_0805_5%

PC284

0.1U_0603_25V7K~D

GNDA_3V5V

PR383

150K_0402_1%~D

1 2

+5V_ALW_UGATE

+5V_ALW_PHASE

PC287

+5V_ALWP

2
3

12

S SCH DIO BAT54SW-7-F SOT323-3

PC294

2

0.1U_0603_25V7K~D

3

S SCH DIO BAT54SW-7-F SOT323-3

PJP35

+15V_ALWP

12

1 2

+3.3V_ALW2

12

12

0.1U_0603_25V7K~D

PD55

PD56

1 2

DELL CONFIDENTIAL/PROPRIETARY

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONF IDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVIS ION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INF ORMATION IT CONT AINS

4

3

2

Title

Size Do c um e n t N u mb er Re v

Date: Sheet

Compal Electronics, Inc.

DC/DC +3V/ +5V
LA-3302P

1

45 66Thursday, March 01, 2007

0.0

of

D D

C C

B B

A A

+PWR_SRC

5 Volt +/-5%
Thermal Design Current:6.2A
Peck current: 8.8A
OCP min: 10.52A

+5V_ALWP

1

+

PC289

PC291

2

0.1U_0402_10V7K~D

330U_D3L_6.3VM_R25~D

+5V_ALWP

+3.3V_ALWP

12

PJP33

1 2

PAD-OPE N 4x4m

PR384

@

0_0402_5%~D

PR388

0_0402_5%~D

GNDA_3V5V

PJP36

1 2

PAD-OPE N 4x4m

PJP37

1 2

PAD-OPE N 4x4m

5

4.7U_HMU1356-4R7-R_10A~D

1 2

1 2

FDS6676AS_NL_SO8~D

+5V_ALW

+3.3V_ALW

FDS8880_NL_SO8~D

1 2

5

4

3

2

1

D D

PC58

2200P_0402_50V7K~D

PQ34

PQ11

ISL88550_AVDD

12

+DDR_PWR_SRC

8

D6D5D7D

S

S

S

3

2

1

786

123

4

G

5

4

PC68

0.22U_0603_10V7K~D

1 2

PC155

0.22U_0402_6.3V 5K~D

PJP32

12

PAD-OPEN 4x4m

1 2

PC72

0.1U_0402_10V7K~D

GNDA_DDR

PR470

27.4K_0402_1%

@

PC401

@

1 2

1000P_0402_50V7K~D

12

PR471

17.4K_0402_1%~D

@

1

PC56

PC55

2

10U_1206_25V6M~D

10U_1206_25V6M~D

3

1 2

PL14

1.4UH_HMU1350-1R4PF_15A_20%~D

12

1

12

PC57

2

0.1U_0603_25V7K~D

FDS8880_NL_SO8~D

+1.8VSUSP_L

FDS6676AS_NL_SO8~D

PR348

0_0402_5%~D

1 2

+PWR_SRC

1.8 Volt +/-5%
Thermal Design Current:7.6A
Peck current: 10.9A
OCP min: 11.09A

C C

+1.8V_SUSP

1

1

+

+

PC71

PC70

2

2

330U_D2E_2.5VM_R15~D

330U_D2E_2.5VM_R15~D

B B

+1.8VSUSP/ +0.9V_DDR_VTT

PR193, PD20 are only used with the second-source MAX8632.

21

PD20

RB751V-40_SOD323~D

@

PR73

12

1_0603_5%~D

ISL88550_FB

0_0402_5%~D @

12

GNDA_DDR

PR84

ISL88550_REF

PR200

1 2

100K_0402_1%~D

1 2

12

ISL88550_DH

ISL88550_LX

DDR2 Termination

+5V_ALW

ALW_PWRGD_3V_5V39,45

12

PC62

4.7U_0805_6.3V6K

PU6

20

BST

18

DH

19

LX

21

DL

23

PGND1

16

VOUT

15

FB

1

TON

3

REF

ISL88550_ILIM

PR202
100K_0402_1%~D

PR193

10_1206_5%~D

PR505
0_0402_5%~D

PR506

0_0402_5%~D

1 2

1 2

GNDA_DDR

2

22

VDD

OVP/ UVP

ISL88550A_TQFN28~D

SKIP

ILIM

4

25

PR518

0_0402_5%~D

1 2

GNDA_DDR

12

@

28

TP0

GND

24

12

GNDA_DDR

ISL88550_AVDD

26

17

VIN

AVDD

5

POK1

6

POK2

27

SHDN

7

STBY

13

VTTI

14

REFIN

11

PGND2

12

VTT

9

VTTS

10

VTTR

SS

GND

8

29

12

PC66

1000P_0402_50V7K~D

@

GNDA_DDR

PC63

1U_0603_10V6K~D

ISL88550_REFI N

12

12

+3.3V_ALW

PR194

20K_0402_5%~D

PR204

20_0603_1%~D

PC77

0.1U_0402_10V7K~D

GNDA_DDR

PC64
1U_0603_10V6K~D

1 2

12

PR195

1 2

100K_0402_1%~D

DDR_ON 39

+1.8V_SUSP

GNDA_DDR

1

PC146
10U_0805_6.3V6M~D

2

PJP59

PAD-OPEN1x1m

1.8V_SUS_PWRGD 39

PR212

0_0402_5%~D

12

+1.8V_SUSP

1

PC153

PC154

2

10U_0805_6.3V6M~D

10U_0805_6.3V6M~D

V_DDR_MCH_REF

12

1

PC157

2

10U_0805_6.3V6M~D

@

0.9V_DDR_VTT_ON 39

+0.9V_DDR_VTTP

1

Design current 0.7A for +0.9V_DDR_VTTP
Peak current 1A for +0.9V_DDR_VTTP

2

PJP9
PAD-OPE N 4x4m

1 2

PJP10
PAD-OPE N 4x4m

+1.8V_SUSP

A A

+0.9V_DDR_VTTP

1 2

PJP11

1 2

PAD-OPE N 4x4m

5

+1.8V_SUS

+0.9V_DDR_VTT

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD

4

PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

2

Title

Size Do c um e n t N u mb er Re v

Date: Sheet

Compal Electronics, Inc.

+1.8VSUSP/ +0 . 9V_DDR_VT
LA-3302P

1

46 66Thursday, March 01, 2007

0.0

of

5

4

3

2

1

+DC2_PWR_SRC

PJP38

12

PC313

10U_1206_6.3V7K

GNDA_1P5V_1P05V

1 2

PAD-OPEN 4x4m

PC389

1 2

0.1U_0402_10V7K~D

PJP40

1 2

PAD-OPEN 4x4m

PJP43

1 2

PAD-OPEN 4x4m

1

12

12

2

PC299

PC297

10U_1206_25V6M~D

PR409

1 2

0_0402_5%~D

@

PR410

0_0402_5%~D

1 2

@

PC300

0.1U_0603_25V7K~D
2200P_0402_50V7K~D

3.3UH_MPL73-3R3_6A_20%~D

+5V_VCC2

GNDA_1P5V_1P05V

PL40

578

PQ87

12

SI4800BDY-T1_SO8~D

3 6

241

8

D6D5D7D

G

PQ89

S

S

S

3

2

1

SI4810BDY-T1-E3_SO8~D

4

GNDA_1P5V_1P05V

1 2

100K_0402_1%~D

GNDA_1P5V_1P05V

PR408

PR497

0_0402_5%~D

12

1 2

PC404

0.1U_0402_10V7K~D

@

+5V_ALW

1.5V_UGATE

1.5V_PHASE

1 2

9

BYP

10

OUT1

11

FB1

12

ILIM1

13

POK1

EN1 EN2

14

EN1

15

UGATE1

16

PHASE1

PC314

0.1U_0603_25V7K~D
PR411

1_0603_5%~D

1 2

PC317

33

GNDA_1P5V_1P05V

1.5V_LGATE

PR413

@

10_0603_5%~D

12

1U_0603_10V6K~D

PR399

0_0805_5%

1 2

4

8

7

6

5

VIN

LDO

VREF3

LDOREFIN

PU21

ISL6236IRZA_QFN32~D

BOOT117LGATE118PVCC19SECFB20GND21PGND22LGATE223BOOT2

PAD

+5V_VCC2

12

PC316

PR401

0_0402_5%~D

PC306

0.1U_0603_25V7K~D

REF

1 2

1 2

PR405

0_0402_5%~D@

1 2

PR504

0_0402_5%~D@

2

3

1

REF

VCC

TON

EN_LDO

REFIN2

ILIM2

OUT2

SKIP#

POK2

EN2

UGATE2

PHASE2

24

1_0603_5%~D

1 2

GNDA_1P5V_1P05V

12

1U_0603_10V6K~D

GNDA_1P5V_1P05V

PR400

0_0805_5%

1 2

1 2

PC305

0.1U_0603_25V7K~D

12

GNDA_1P5V_1P05V

REFIN2_1_05

32
31

1 2

PR407 249K_0402_1%~D

30

PR519 0_0402_5%~D

29
28
27
26

1.05V_PHASE

25

PC315

0.1U_0603_25V7K~D

PR412

1.05V_LGATE

GNDA_1P5V_1P05V

+3.3V_RTC_LDO

12

PR496

1 2

PC308

0.01U_0402_25V7K~D

12

POK2POK1

1.05V_UGATE

1 2

PJP41

PAD-OPEN1x1m

OK to Short if CAD
System can Support

PR503

@

0_0402_5%~D

0_0402_5%~D

GNDA_1P5V_1P05V

12

PC387

0.1U_0402_10V7K~D

@

GNDA_1P5V_1P05V

GNDA_1P5V_1P05V

12

1

1

2

2

PC302

PC301

10U_1206_25V6M~D

12

@

POK2

POK1

8

D6D5D7D

4

PR415

100K_0402_1%~D

PQ86

G

S

S

S

3

2

1

578

3 6

241

+3.3V_SUS

12

PR416

1 2

100K_0402_1%~D

@

+1.05V_VCCP_P +1.05V_VCCP

PL39

1UH_MPLC0730L1R0_11A_20%~D

SI4800BDY-T1-E3_SO8~D

1 2

PQ88

FDS6690AS_NL_SO8~D

1.05V_RUN_PWRGD 42

1.5V_RUN_PWRGD 42

PC303

10U_1206_25V6M~D

1.05 Volt +/-5%
Thermal Design Current: 4.2A
Peack current: 6.1A
OCP min: 9.61A

EN1

0_0402_5%~D

EN2

1 2

PJP39

1 2

PAD-OPEN 4x4m

PJP42

1 2

PAD-OPEN 4x4m

0.1U_0603_25V7K~D

PR478

12

12

PC304

2200P_0402_50V7K~D

+1.05V_VCCP_P

1

1

PC310

2

330U_D2E_2.5VM_R9

+

PC309

330U_D2E_2.5VM_R9

1.5V_RUN_ON 39

1.05V_RUN_ON 38

12

+

PC311

PC388

2

1 2

0.1U_0402_10V7K~D

10U_1206_6.3V7K

+PWR_SRC

D D

1.5 Volt +/-5%
Thermal Design Current: 1.9A
Maximum current: 2.7A
OCP min: 3.04A

C C

+1.5V_RUN_P

1

+

PC312

2

330U_D2E_2.5VM_R9

B B

+1.5V_RUN_P +1.5V_RUN

A A

DELL CONFIDENTIAL/PROPRIETARY

+1.5V_RUN / +1.05V_VCCP / +3.3V_ALW / +3.3V_RTC_LDO

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

THIS SHEET OF EN GINEE RING D RAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

4

3

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

+1.5V_RUN / +1.05V_VCCP

LA-3302P

1

47 66Thursday, March 01, 2007

0.0

of

8

7

6

5

4

3

2

1

+CPU_PWR_SRC

H H

PQ42

PQ50

2

PQ57

2

8

D5D6D7D

G4S3S2S

1

IRF7821TRPBF_SO8~D

PHASE1

3

D

PQ56

G

S

FDS7088SN3_SO8~D

1

@

8

D5D6D7D

G4S3S2S

1

IRF7821TRPBF_SO8~D

3

D

2

IRF7821TRPBF_SO8~D

G

PQ60

G

S

FDS7088SN3_SO8~D

1

@

8

D5D6D7D

G4S3S2S

1

3

D

PQ61

S

FDS7088SN3_SO8~D

1

PC248

@

3

+CPU_PWR_SRC

PR228
10_0603_5%~D

12

PC180

0.01U_0402_25V7K~D

GNDA_VCORE

19

20

VSS

VDD

13K_0402_5%~D

4

VR_TT#

3

RBIAS

5

NTC

6

SOFT

VID0
VID1
VID2
VID3
VID4
VID5
VID6

DPRSTP#
DPRSLPVR

1

PSI#

2

PMON
CLK_EN#
VR_ON
VSEN
RTN

VDIFF

FB

9

COMP

8

VW
GND

DROOP

14

PR267

PC201

12

330P_0402_50V7K~D

PC411

4700P_0402_25V7K~D

1 2

+3.3V_RUN

1 2

39

40

18

VIN

3V3

PGOOD

PWM1

ISEN1

PU11

PWM2

ISEN2

ISL6260CCRZ_QFN40~D

FCCM

PWM3

ISEN3

OCSET

VSUM

DFB15VO

16

VO

PR268

1K_0402_1%~D

12

12

PC412

@

4700P_0402_25V7K~D

GNDA_VCORE

PR234

1.91K_0603_1%~D

27

23

26

22

24

25

21

7

17

12

PR263

4.53K_0402_1%~D
PC191

0.33U_0603_10V7K

12

2

PC260

1

@

VSUM

2

1

1

2

PC229

0.01U_0402_16V7K~D

0.1U_0402_16V7K~D

6

IMVP_PWRGD 23,39,42

PR508

@

226K_0402_1%~D

12

PR260

11.5K_0402_1%~D

12

12

PR261

PC215

1 2

2.43K_0402_1%~D

0.033U_0402_16V7K~D

12

PH2

S THERM_ 6.8K +-5% TSM1A682J4302RE 0603

12

PR480

@

0_0402_5%~D

PR266

15K_0402_1%~D

GNDA_VCORE

12

1

2

PC392

@

0.1U_0402_16V7K~D

G G

+5V_ALW

PR233

1 2

10_0603_5%~D

PC182

1U_0603_10V6K~D

GNDA_VCORE

IMVP6_PROCHOT#38

PH1

12

12
12
12
12

12

CLK_ENABLE#

PR509 0_0402_5%~D

12

12

12

12

PR287

0_0603_5%~D

12

PR487

0_0402_5%~D

12

PR259

PC197

12

12

PR264

12

12

12

12

PR516

PC413

GNDA_VCORE

7

PR290

0_0603_5%~D

12

1K_0402_1%~D

12

0.01U_0402_16V7K~D

12

PR485

@

28
29
30
31
32
33
34

37
36

38
35
12
13

11

10

41

GNDA_VCORE

10.5K_0402_1%

12

@

F F

E E

GNDA_VCORE

H_DPRSTP#8,10,22

DPRSLPVR10,23

H_PSI#8

D D

PWR_MON18

PC391

1U_0603_10V6K~D

GNDA_VCORE

RUNPWROK38,39,42,54

IMVP_VR_ON39

10KB_0603_1%_ERTJ1VG103FA~D

C C

B B

@

A A

GNDA_VCORE

0_0402_5%~D

2200P_0402_50V7K~D

0.015U_0402_16V7K~D

VID08
VID18
VID28
VID38
VID48
VID58
VID68

PR252

10K_0402_5%~D

1 2

PH3

@

PR486

4.99K_0402_1%@

VSSSENSE8

PR257

332_0402_1%~D

220P_0402_50V8J~D

12

PR481

0_0402_5%~D

8

PR238

147K_0402_1%~D

12

PR284

@

12

PC409

@

12

PC187

12

0_0402_5%~D
0_0402_5%~D
0_0402_5%~D

0_0402_5%~D

12

PR254 0_0402_5%~D@

12

12

GNDA_VCORE

12

680P_0402_50V7K~D

1 2

PC250

1500P_0402_50V7K~D
PC195

1 2

@

470KB_0402_5%_NCP15WM474J03RB~D

PR239

PR240

0_0402_5%~D

12

PR241

PR242

0_0402_5%~D

12

PR243

PR244

0_0402_5%~D

12

PR245

0_0402_5%~D

@

0_0402_5%~D

1 2

PC190

PR248

PR249

499_0402_1%~D

12

PR479

12

12

VCCSENSE8

PC213 1000P_0402_50V7K~D

PC214 1000P_0402_50V7K~D

PR512
0_0402_5%~D

PR258

1.69K_0402_1%~D

82.5K_0402_1%~D

1000P_0402_50V7K~D

6.34K_0402_1%~D

+5V_ALW

12

PC178

1U_0603_10V6K~D

12

PR482

@

5

12

12

PWR_MON 18

30K_0402_5%~D

PU10

5

VCC

6

FCCM

2

PWM

3

GND

ISL6208CRZ-T_QFN8~D

+5V_ALW

PC241

1U_0603_10V6K~D

5

VCC

6

FCCM

2

PWM

3

GND

ISL6208CRZ-T_QFN8~D

+5V_ALW

PC196

PU13

5

VCC

1U_0603_10V6K~D

6

FCCM

2

PWM

3

GND

ISL6208CRZ-T_QFN8~D

PU16

PR229

0_0603_5%~D

1

BOOT
UGATE
PHASE
LGATE

UGATE

BOOT
UGATE
PHASE
LGATE

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONF IDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVIS ION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INF ORMATION IT CONT AINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WR ITT EN CO NSE NT OF COMPAL ELECTRONICS, INC.

BOOT

PHASE
LGATE

8
7
4

PR328
0_0603_5%~D

1
8
7
4

PR262

0_0603_5%~D

1
8
7
4

UGATE1

UGATE3

0.22U_0603_10V7K~D

12

1 2

LGATE1

0.22U_0603_10V7K~D

12

1 2

UGATE2

LGATE2

PC198

0.22U_0603_10V7K~D

12

1 2

LGATE3

4

PC179

PC242

12

PC249

0.1U_0603_25V7K~D

12

PC246

1500P_0603_25V7K~D

PC247

1500P_0603_25V7K~D

12

1500P_0603_25V7K~D

1 2

VSUM

12

PC239

PC240

0.1U_0603_25V7K~D

PHASE2

12

0.45UH_ET QP4LR45XFC_25A_20%~D

PHASE3

1 2

VSUM

12

12

PC223

0.1U_0603_25V7K~D

10K_0402_1%~D

1 2

PR231

7.68K_0805_1%~D

12

2200P_0402_50V7K~D

+CPU_PWR_SRC

10K_0402_1%~D

1 2

PR270

7.68K_0805_1%~D

PC176

PC224

10U_1206_25V6M~D

2200P_0402_50V7K~D

PL29

0.45UH_ETQP4LR45XFC_25A_20%~D

4
3

PR230

0.22U_0603_10V7K~D

+CPU_PWR_SRC

12

12

PC177

PC271

10U_1206_25V6M~D

10U_1206_25V6M~D

0.45UH_ET QP4LR45XFC_25A_20%~D

4
3

PR330

10K_0402_1%~D

1 2

PR331

7.68K_0805_1%~D

1 2

VSUM

12

12

10U_1206_25V6M~D

PR269

1
2

PC227

PC193

0.1U_0603_25V7K~D

10U_1206_25V6M~D
PL31

4
3

0.22U_0603_10V7K~D

PC272

FBMA-L18-453215-900LMA90T_1812~D

1

12

12

PC380

PC270

2

100U_25V_M~D

10U_1206_25V6M~D

1
2

PC181

PL33

12

PC200

1 2

12

12

VO

1
2

PC243

0.22U_0603_10V7K~D

12

12

PC228

2200P_0402_50V7K~D

PR271
10_0402_1%~D

1 2

12

12

PR515
0_0402_5%~D

VO

DELL CONFIDENTIAL/PROPRIETARY

Title

Size Do c um e n t N u mb er Re v

Date: Sheet

2

PL47

@

1 2

PJP30

1 2

+

PAD-OPEN 4x4m

PJP31

1 2

PAD-OPEN 4x4m

Iccmax=44A
I_TDC=35A
OCP=65A, Intel spec=50A

+VCC_CORE

PR232
10_0402_1%~D

PR513
0_0402_5%~D

+VCC_CORE

PR329
10_0402_1%~D

1 2

12

PR514
0_0402_5%~D

VO

+VCC_CORE

Compal Electronics, Inc.

+VCORE
LA-3302P

48 66Thursday, March 01, 2007

1

+PWR_SRC

of

0.0

5

4

3

2

1

+DC_IN discharge path

+SDC_IN

PR138

0.01_2512_1%~D

+DC_IN_SS

D D

1

PC99

2

10U_1206_25V6M~D

PR142
215K_0402_1%

1 2

1
2

4
3

PC383

1 2

0.22U_0402_6.3V6K

12

10_0402_1%~D

PR472

PJP62

1 2

PAD-OPEN 4x4m

12

12

PC128

PC127

@

@

0.1U_0603_25V7K~D

2200P_0402_50V7K~D

CHAGER_SRC

ISL88731_VDDP

12

12

0.01U_0402_25V7K~D

12

57.6K_0402_1%~D

12

13K_0402_1%

PC393

12

GNDA_CHG

105_0402_1%~D

4

1U_0805_25V4Z~D

GNDA_CHG

PC122

@

1U_0603_10V6K~D

12

0.01U_0402_25V7K~D

PR143

49.9K_0402_1%~D

12

0.01U_0402_25V7K~D

GNDA_CHG

Vin Detector
High 17.9 V
Low 17.24 V

PC110

12

0.1U_0402_10V7K~D

THRM_SMBCLK18,39

THRM_SMBDAT18,39

5

C C

B B

A A

ACAV_IN18,39,50

+5V_ALW

ADAPT_TRIP_SET38

PR149

10K_0402_1%~D

PR341

15.8K_0402_1%~D

PC221

GNDA_CHG

12

12

PR150

@

16.2K_0402_1%~D

ISL88731_ICM

12

@

PR148

12

PC118

PC121

0.1U_0402_10V7K~D

PR361

1 2

8.45K_0402_1%~D

@

33.2K_0402_1%~D

1 2

PR146

1 2

0_0402_5%~D

12

12

PC212

@

0.01U_0402_25V7K~D

ISL88731_VREF

12

PC254

0.1U_0402_16V7K~D

PC119

PR362

PR363

PR364

2.2K_0402_5%~D

12

0.01U_0402_25V7K~D

PR475

GNDA_CHG GNDA_CHG

GNDA_CHG

PC102

12

ISL88731_ICM

ISL88731_VREF

12

PC255

100P_0402_50V8K

GNDA_CHG GNDA_CHG GNDA_CHG GNDA_CHG

GNDA_CHG

12

12

PC120

@

0.1U_0402_10V7K~D

1M_0402_1%~D

1 2

2

IN-

3

IN+

12

PC256

100P_0402_50V8K

+5V_ALW

PU8

22

DCIN

2

ACIN

13

ACOK

11

VDDSMB

10

SCL

9

SDA

14

NC

8

ICM

6

VCOMP

5

NC

4

ICOMP

3

VREF

7

NC

12

GND

29

GND

PR365

GNDA_CHG

4

G

O

P

8

1

28

NC

CSSP

ISL88731_TQFN28~D

PU19A
LM393DR_SO8~D

1

12

PC258

PC257

100P_0402_50V8K

0.01U_0402_25V7K~D

THIS SHEET OF EN GINEE RING D RAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

27

26

VCC

CSSN

BOOT

VDDP

UGATE
PHASE

LGATE

PGND

CSOP

CSON

VFB

NC

12

GNDA_CHG G N DA_CHG GNDA_CHG

PR275

0_0603_5%~D

25

1 2

PC203

ISL88731_VDDP

21

24
23

1

2

20

19
18

17
15
16

+5V_ALW +3.3V_ALW

12

PR366

100K_0402_1%~D

12

PC259

@

10P_0402_50V8J~D

3

0.1U_0603_25V7K~D

PR360

12

0_0603_1%~D

PC253

@

220P_0402_50V7K~D

1 2

PR368

0_0603_5%~D

PR367

100K_0402_5%~D

2

G

PQ81
RHU002N06_SOT323

12

12

13

D

S

1U_0603_10V6K~D

1 2

PD40

1U_0603_10V6K~D

@

2 1

RB751V_SOD323~D

+VCHGR

PC202

1 2

PR274
33_0603_1%~D

PC204

1 2

GNDA_CHG

12

PR474

@

GNDA_CHG GN DA_CHG

GNDA_CHG

@

1 2

PAD-OPEN1x1m

ADAPT_OC 38

1K_0402_5%~D

PC267

PJP65

5
6

12

3300PF_0402_50V7K~D

+5V_ALW

IN+
IN-

578

3 6

8

P

G

4

241

O

PQ75

SI4800BDY-T1_SO8~D

+VCHGR_B

578

3 6

241

7

PU19B
LM393DR_SO8~D

2

578

PQ79

SI4800BDY-T1_SO8~D

3 6

241

PL20

+VCHGR_L

5.6U_HMU1356-5R6_8.8A_20%~D

PQ76
SI4810BDY_SO8~D

12

Maximum charging current is 6.24A

1

10U_1206_25V6M~D

1

2

2

PC106

10U_1206_25V6M~D

+VCHGR

1

12

PC112

0.1U_0603_25V7K~D

1

2

2

PC113

PC114

10U_1206_25V6M~D

10U_1206_25V6M~D

PC379

10U_1206_25V6M~D

PD54

@

PR373

@

1K_0603_1%~D

1

2

12

PC103

2200P_0402_50V7K~D

0.01_2512_1%~D

12

10_0402_1%~D

PR473

0.22U_0402_6.3V6K

1
2

PC104

PR145

PC384

1 2

12

PC105

0.1U_0603_25V7K~D

4
3

DELL CONFIDENTIAL/PROPRIETARY

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

Charger
LA-3302P

49 66Thursday, March 01, 2007

1

of

+5V_ALW

21

1SS355_SOD323~D

12

0.0

5

4

3

2

1

+DC_IN discharge path

PQ62

SI4835BDY-T1-E3_SO8~D

8

D D

PQ65

8
7

+VCHGR

CHG_SBAT_N

13

D

PQ67

CHG_SBATT38

C C

CHG_PBATT38

2

G

2

G

+VCHGR

RHU002N06_SOT323

S

S

RHU002N06_SOT323
PQ68

D

1 3

CHG_PBAT_N

6
5

PR309

10K_0402_5%~D

PR312

10K_0402_5%~D

5
7

8

CHG_SBAT

1

D2

S2

CHG_SBATT_N

2

G2

D2

3

S1

D1

4

D1

G1

FDS4935BZ_SO8~D

100K_0402_5%~D

12

0.1U_0603_25V7K~D

CHG_SBATT_N

0.1U_0603_25V7K~D

1 2

100K_0402_5%~D

12

PQ71

4

SI4835BDY-T1-E3_SO8~D

PR310

PC234

1 2

PC235

PR313

36
2
1

12

CHG_PBATT_N

12

CHG_PBAT

ACAV_IN18,39,49

PQ72

4

SI4835BDY-T1-E3_SO8~D

3 6
2
1

PBATT+

5
7

8

SBATT+

@

100K_0402_5%~D

+SDC_IN

2

PR308

G

12

PQ69

SI4835BDY-T1-E3_SO8~D

1
2
3 6

4

13

D

PQ63
RHU002N06_SOT323

S

8
7

5

PR305

10K_0402_5%~D

2

G

2
3

1 2
13

D

S

PD48

RB715F_SOT323

7
5

PR306

10K_0402_5%~D

PQ64
RHU002N06_SOT323

2 1

SI4835BDY-T1-E3_SO8~D

8
7

5

SBAT_G

1

B540C~D

2 1

SI4835BDY-T1-E3_SO8~D

8
7

5

12

PD47

B540C~D

PQ66

PR311

PD49

PQ70

4

4

1 2

33K_0402_5%~D

4

1
2
36

PR307

100K_0402_5%~D

12

1
2
36

1
2
36

+PWR_SRC

12

PC233

PC232

2200P_0402_50V7K~D

+PWR_SRC

+

PC382

2

100U_25V_M~D

0.1U_0603_25V7K~D

1

12

1

+

PC381

2

100U_25V_M~D

PR316

12

47K_0402_1%~D

PR314

PR315

470K_0402_5%~D

B B

PR319

SBATT+

PR321

147K_0402_1%~D

1 2

PBATT+

PC236

1 2

+3.3V_ALW

PU15

5

TC7SH32FU_SSOP5~D

2

A A

PBAT_DSCHG38

SBAT_PRES#38,44

5

P

I0

O

1

I1

G

3

@

4

PQ74

RHU002N06_SOT323

0.1U_0603_25V7K~D

13

D

2

G

S

PR323

1 2

IN+
IN-

8

P

G

4

PC237

0.1U_0603_25V7K~D

7

O

LM393DR_SO8~D
PU14B

1 2

1

RB715F_SOT323

PD51

2
3

42.2K_0402_1%~D
PR324

10K_0402_5%~D

1 2

1 2

PR325

100K_0402_5%~D

PR326

1 2

32.4K_0402_1%~D

5
6

+3.3V_ALW

4

47K_0402_1%~D

1 2

PR322

100K_0402_5%~D

1 2

+3.3V_ALW

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

1 2

PBATT+

8

3

IN+

2

IN-

4

3

470K_0402_5%~D

PU14A
LM393DR_SO8~D

P

1

O

G

PR320

1 2

12

470K_0402_5%~D

PR317

10K_0402_5%~D

2

G

12

13

D

PQ73
RHU002N06_SOT323

S

PD50

2
3

RB715F_SOT323

2

PBAT_G

1

PR318

1 2

33K_0402_5%~D

DELL CONFIDENTIAL/PROPRIETARY

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

Selector
LA-3302P

50 66Thursday, March 01, 2007

1

0.0

of

5

4

3

2

1

GPU_COREP/ +1.25V_RUN

PJP51

PC399

@

1000P_0402_50V7K~D

1 2

PAD-OPEN 4x4m

PL45

12

PJP54

1 2

PAD-OPEN 4x4m

PJP55

1 2

PAD-OPEN 4x4m

1

1

2

2

PC410

10U_1206_25V6M~D

PQ96

5

FDS6982AS_NL_SO8~D

12

D16D1

3
7
8

1.25V_RUN_ON39

G1

S1
D2
D2

G2

S2

1

PC351

PC349

10U_1206_25V6M~D

4

2

GNDA_1P25V_GPU_CORE

+3.3V_ALW

12

12

12

PC352

0.1U_0603_25V7K~D
2200P_0402_50V7K~D

12

PC407

@

0.1U_0402_10V7K~D

PR484
100K_0402_1%~D

GNDA_1P25V_GPU_CORE

GNDA_1P25V_GPU_CORE

PR453

205K_0402_1%~D

1 2

PC368

1 2

PR460

0.1U_0603_25V7K~D
1_0603_5%~D

1 2

PJP52

12

PAD-OPEN1x1m

PR443

0_0805_5%

PR442

0_0805_5%

1 2

1 2

PC357

0.1U_0603_25V7K~D

8

7

LDO

9

LDOREFIN

BYP

10

OUT1

11

FB1

12

ILIM1

13

POK1

ISL6236IRZA_QFN32~D

14

EN1

15

UGATE1

16

PHASE1

BOOT117LGATE118PVCC19SECFB20GND21PGND22LGATE223BOOT2

PAD

33

GNDA_1P25V_GPU_CORE

+5V_ALW

PC373

1U_0603_10V6K~D

GFX_CORE_ON38

RUN_ON19,37,39,41,42

1 2

+5V_VCC4

PR444

0_0402_5%~D

@

1 2

VGA_ISL6236_REF

GNDA_1P25V_GPU_CORE

2

4

6

5

3

1

VIN

REF

VCC

TON

VREF3

EN_LDO

REFIN2

PU25

UGATE2

PHASE2

24

1_0603_5%~D

GNDA_1P25V_GPU_CORE

PR464

@

10_0603_5%~D

12

PR466
0_0402_5%~D

1 2

PR467
0_0402_5%~D @

1 2

PR445

0_0402_5%~D

1 2

1 2

ILIM2

OUT2

SKIP#

POK2

EN2

PR459

1 2

+5V_VCC4

12

GNDA_1P25V_GPU_CORE

PR448
0_0402_5%~D @

32
31
30
29

PR520 0_0402_5%~D

28
27
26
25

PC369

0.1U_0603_25V7K~D

12

PC372

1U_0603_10V6K~D

12

2@

196K_0402_1%~D

1@

205K_0402_1%~D

1 2

1 2

PC362

PR522

PR451

0.1U_0603_25V7K~D

12

12

12

PC360

PR446

1 2

13.7K_0402_1%~D
1000P_0402_50V7K~D

PR521

PR449

1 2

1 2

1@

2@

13.7K_0402_1%~D

18.7K_0402_1%~D

GNDA_1P25V_GPU_CORE

12

PC408

@

0.1U_0402_10V7K~D

Table 1

4

4

version

G86(1.15V)

1

2

PC353

10U_1206_25V6M~D

8

PQ95

D6D5D7D

FDS8880_NL_SO8~D

G

S

S

S

PL46

3

2

1

0.82UH_MPL73-R82_13A_20%~D

786

5

PQ97

123

FDS6676AS_NL_SO8~D

BOM structure

1

2

PC354

PC355

10U_1206_25V6M~D

12

PC365

330U_D2E_2.5VM_R9~D

GFX_CORE_PWRGD 42

1.25V_RUN_PWRGD 42

2@

1@G72(1.0V)

12

0.1U_0603_25V7K~D

1

+

PC367

2

0.1U_0402_10V7K~D

12

PC356

2200P_0402_50V7K~D

+GPU_COREP

1

12

+

PC402

2

330U_D2E_2.5VM_R9~D

PR457

10K_0402_1%~D@

location

PR449,PR522

PR521,PR451

GPU_CORE
Thermal Design Current:7.7A
Peak current: 11A

PR447

@

PC370

1 2

@

OCP min: 12.23A

1 2

196K_0402_1%~D

@

1 2

BSS138W-7-F_SOT323~D

13

D

12

S

100P_0402_50V8K

PR452
0_0402_1%~D

PQ98

@

2

G

PR461

1 2

@

100K_0402_1%~D

PR458

@

16.9K_0402_1%~D

12

PC371

@

0.01U_0402_25V7K~D

+3.3V_RUN

PR454

PR455

10K_0402_1%~D@

10K_0402_1%~D@

1 2

1 2

12

13

D

2

G

S

PQ99

@

BSS138W-7-F_SOT323~D

GNDA_1P25V_GPU_CORE

GFX_CORE_CNTRL 52

+PWR_SRC

D D

1.25 Volt +/-5%
Thermal Design Current:2.1A
Peak current: 3A
OCP min: 6.31A

+1.25V_RUNP

3.3UH_MPL73-3R3_6A_20%~D

C C

1

+

PC363

2

220U_D2E_2.5VM_R15~D

B B

12

PC364

0.1U_0402_10V7K~D
PR456

8.45K_0402_1%

PR463

10.7K_0402_1%

GNDA_1P25V_GPU_CORE

+GPU_COREP +GPU_CORE

A A

+1.25V_RUNP +1.25V_RUN

PJP56

1 2

PAD-OPEN 4x4m

5

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

4

3

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

PWR_NVG72 +VDD_CORE
LA-3302P

51 66Thursday, March 01, 2007

1

0.0

of

5

PEG_MTX_GRX_P0
PEG_MTX_GRX_N0
PEG_MTX_GRX_P1
PEG_MTX_GRX_N1
PEG_MTX_GRX_P2
PEG_MTX_GRX_N2

PEG_MTX_GRX_P[0..15]12
PEG_MTX_GRX_N[0..15]12

D D

C C

B B

PEG_MRX_GTX_P[0..15]12
PEG_MRX_GTX_N[0..15]12

PEG_MRX_GTX_P0
PEG_MRX_GTX_N0

PEG_MRX_GTX_P1
PEG_MRX_GTX_N1

PEG_MRX_GTX_P2
PEG_MRX_GTX_N2

PEG_MRX_GTX_P3
PEG_MRX_GTX_N3

PEG_MRX_GTX_P4
PEG_MRX_GTX_N4

PEG_MRX_GTX_P5
PEG_MRX_GTX_N5

PEG_MRX_GTX_P6
PEG_MRX_GTX_N6

PEG_MRX_GTX_P7
PEG_MRX_GTX_N7

PEG_MRX_GTX_P8
PEG_MRX_GTX_N8

PEG_MRX_GTX_P9
PEG_MRX_GTX_N9

PEG_MRX_GTX_P10
PEG_MRX_GTX_N10

PEG_MRX_GTX_P11
PEG_MRX_GTX_N11

PEG_MRX_GTX_P12
PEG_MRX_GTX_N12

PEG_MRX_GTX_P13
PEG_MRX_GTX_N13

PEG_MRX_GTX_P14
PEG_MRX_GTX_N14

PEG_MRX_GTX_P15
PEG_MRX_GTX_N15

PEG_MTX_GRX_P[0..15]
PEG_MTX_GRX_N[0..15]
PEG_MRX_GTX_P[0..15]
PEG_MRX_GTX_N[0..15]

PEG_MRX_GTX_C_P0

C3490.1U_0402_10V7K~D

12

12

C3460.1U_0402_10V7K~D

12

C3590.1U_0402_10V7K~D

12

C3520.1U_0402_10V7K~D

12

C3560.1U_0402_10V7K~D

12

C3450.1U_0402_10V7K~D

12

C3550.1U_0402_10V7K~D

12

C3200.1U_0402_10V7K~D

12

C3570.1U_0402_10V7K~D

12

C3410.1U_0402_10V7K~D

12

C3470.1U_0402_10V7K~D

12

C3190.1U_0402_10V7K~D

12

C3390.1U_0402_10V7K~D

12

C3230.1U_0402_10V7K~D

12

C3400.1U_0402_10V7K~D

12

C3220.1U_0402_10V7K~D

12

C3500.1U_0402_10V7K~D

PLTRST_DELAY#23

CLK_NV_27M6

For G8x use. CLK_NV_27M is 3.3V Level.
For G7x use. CLK_NV_27M is 1.2V Level

XTALOUTBUFF57

XTALSSIN57

CLK_NVSS_27M6

1 2

R525 10K_0402_5%~D

C3620.1U_0402_10V7K~D

12

C3540.1U_0402_10V7K~D

12

C3600.1U_0402_10V7K~D

12

C3480.1U_0402_10V7K~D

12

C3580.1U_0402_10V7K~D

12

C3210.1U_0402_10V7K~D

12

C3610.1U_0402_10V7K~D

12

C3440.1U_0402_10V7K~D

12

C3530.1U_0402_10V7K~D

12

C3250.1U_0402_10V7K~D

12

C3430.1U_0402_10V7K~D

12

C3270.1U_0402_10V7K~D

12

C3420.1U_0402_10V7K~D

12

C3260.1U_0402_10V7K~D

12

C3510.1U_0402_10V7K~D

12

PLTRST_DELAY#

PEG_MRX_GTX_C_N0
PEG_MRX_GTX_C_P1

PEG_MRX_GTX_C_N1
PEG_MRX_GTX_C_P2

PEG_MRX_GTX_C_N2
PEG_MRX_GTX_C_P3

PEG_MRX_GTX_C_N3
PEG_MRX_GTX_C_P4

PEG_MRX_GTX_C_N4
PEG_MRX_GTX_C_P5

PEG_MRX_GTX_C_N5
PEG_MRX_GTX_C_P6

PEG_MRX_GTX_C_N6
PEG_MRX_GTX_C_P7

PEG_MRX_GTX_C_N7
PEG_MRX_GTX_C_P8

PEG_MRX_GTX_C_N8
PEG_MRX_GTX_C_P9

PEG_MRX_GTX_C_N9
PEG_MRX_GTX_C_P10

PEG_MRX_GTX_C_N10
PEG_MRX_GTX_C_P11

PEG_MRX_GTX_C_N11
PEG_MRX_GTX_C_P12

PEG_MRX_GTX_C_N12
PEG_MRX_GTX_C_P13

PEG_MRX_GTX_C_N13
PEG_MRX_GTX_C_P14

PEG_MRX_GTX_C_N14
PEG_MRX_GTX_C_P15

PEG_MRX_GTX_C_N15

CLK_PCIE_VGA6
CLK_PCIE_VGA#6

XTALOUTBUFF

1 2

0_0402_5%~D

1 2

R165 0_0402_5%~D@

PEG_MTX_GRX_P3
PEG_MTX_GRX_N3
PEG_MTX_GRX_P4
PEG_MTX_GRX_N4
PEG_MTX_GRX_P5
PEG_MTX_GRX_N5
PEG_MTX_GRX_P6
PEG_MTX_GRX_N6
PEG_MTX_GRX_P7
PEG_MTX_GRX_N7
PEG_MTX_GRX_P8
PEG_MTX_GRX_N8
PEG_MTX_GRX_P9
PEG_MTX_GRX_N9
PEG_MTX_GRX_P10
PEG_MTX_GRX_N10
PEG_MTX_GRX_P11
PEG_MTX_GRX_N11
PEG_MTX_GRX_P12
PEG_MTX_GRX_N12
PEG_MTX_GRX_P13
PEG_MTX_GRX_N13
PEG_MTX_GRX_P14
PEG_MTX_GRX_N14
PEG_MTX_GRX_P15
PEG_MTX_GRX_N15

PEG_MRX_GTX_C_P0
PEG_MRX_GTX_C_N0
PEG_MRX_GTX_C_P1
PEG_MRX_GTX_C_N1
PEG_MRX_GTX_C_P2
PEG_MRX_GTX_C_N2
PEG_MRX_GTX_C_P3
PEG_MRX_GTX_C_N3
PEG_MRX_GTX_C_P4
PEG_MRX_GTX_C_N4
PEG_MRX_GTX_C_P5
PEG_MRX_GTX_C_N5
PEG_MRX_GTX_C_P6
PEG_MRX_GTX_C_N6
PEG_MRX_GTX_C_P7
PEG_MRX_GTX_C_N7
PEG_MRX_GTX_C_P8
PEG_MRX_GTX_C_N8
PEG_MRX_GTX_C_P9
PEG_MRX_GTX_C_N9
PEG_MRX_GTX_C_P10
PEG_MRX_GTX_C_N10
PEG_MRX_GTX_C_P11
PEG_MRX_GTX_C_N11
PEG_MRX_GTX_C_P12
PEG_MRX_GTX_C_N12
PEG_MRX_GTX_C_P13
PEG_MRX_GTX_C_N13
PEG_MRX_GTX_C_P14
PEG_MRX_GTX_C_N14
PEG_MRX_GTX_C_P15
PEG_MRX_GTX_C_N15

CLK_PCIE_VGA
CLK_PCIE_VGA#

1 2

R755 0_0402_5%~D

R166

XTALSSIN_R

4

AF1
AG2
AG3
AG4

AF4

AF5
AG6
AG7

AF7

AF8
AG9

AG10
AF10
AF11
AG12
AG13
AG15
AG16
AF16
AF17
AG18
AG19
AF19
AF20
AG21
AG22
AF22
AF23
AG24
AG25
AG26
AF27

AD5
AD6

AE6

AE7
AD7
AC7

AE9

AE10
AD10
AC10
AE12
AE13
AD13
AC13
AC15
AD15
AE15
AE16
AC18
AD18
AE18
AE19
AC21
AD21
AE21
AE22
AD22
AD23
AF25
AE25
AE24
AD24

AE3

AE4
AC6

B1

C2
C3

C1

U10A

PEX_RX0
PEX_RX0_N
PEX_RX1
PEX_RX1_N
PEX_RX2
PEX_RX2_N
PEX_RX3
PEX_RX3_N
PEX_RX4
PEX_RX4_N
PEX_RX5
PEX_RX5_N
PEX_RX6
PEX_RX6_N
PEX_RX7
PEX_RX7_N
PEX_RX8
PEX_RX8_N
PEX_RX9
PEX_RX9_N
PEX_RX10
PEX_RX10_N
PEX_RX11
PEX_RX11_N
PEX_RX12
PEX_RX12_N
PEX_RX13
PEX_RX13_N
PEX_RX14
PEX_RX14_N
PEX_RX15
PEX_RX15_N

PEX_TX0
PEX_TX0_N
PEX_TX1
PEX_TX1_N
PEX_TX2
PEX_TX2_N
PEX_TX3
PEX_TX3_N
PEX_TX4
PEX_TX4_N
PEX_TX5
PEX_TX5_N
PEX_TX6
PEX_TX6_N
PEX_TX7
PEX_TX7_N
PEX_TX8
PEX_TX8_N
PEX_TX9
PEX_TX9_N
PEX_TX10
PEX_TX10_N
PEX_TX11
PEX_TX11_N
PEX_TX12
PEX_TX12_N
PEX_TX13
PEX_TX13_N
PEX_TX14
PEX_TX14_N
PEX_TX15
PEX_TX15_N

PEX_REFCLK
PEX_REFCLK_N

PEX_RST_N

XTALIN

XTALOUT
XTALOUTBUFF

XTALSSIN

G86-620-A2_BGA533~D

Part 1 of 5

DVO / GPIO

MIOB_CLKOUT

MIOB_CLKOUT_N

PCI EXPRESS

DACA_GREEN

DACsI2C

DACB_GREEN

IFPAB_VPROBE

IFPCD_VPROBE

CLK

JTAG_TRST_N

TEST

PEX_TSTCLK_OUT

PEX_TSTCLK_OUT_N

GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8

GPIO9
GPIO10
GPIO11
GPIO12

MIOBD0
MIOBD1
MIOBD2
MIOBD3
MIOBD4
MIOBD5
MIOBD6
MIOBD7
MIOBD8

MIOBD9
MIOBD10
MIOBD11

MIOB_HSYNC
MIOB_VSYNC

MIOB_DE

MIOB_CTL3

MIOB_CLKIN

MIOB_VREF

DACA_HSYNC
DACA_VSYNC

DACA_RED

DACA_BLUE

DACA_IDUMP

DACA_RSET
DACA_VREF

DACB_HSYNC
DACB_VSYNC

DACB_RED

DACB_BLUE

DACB_IDUMP

DACB_RSET
DACB_VREF

I2CA_SCL
I2CA_SDA
I2CB_SCL
I2CB_SDA
I2CC_SCL

I2CC_SDA

I2CH_SCL

I2CH_SDA

JTAG_TCK

JTAG_TDI
JTAG_TDO
JTAG_TMS

TESTMODE

3

DVI_DETECT

A9
D9

BIA_PWM

A10

ENVDD

B10

PANEL_BKEN

C10

GFX_CORE_CNTRL

C12
B12
A12
A13
B13
B15
A15
B16

G2
G3
J2
J1
K4
K1
M2
M1
N1
N2
N3
R3

G4
F1
G1
F2

R2
K2
K3

J4

AD4
AC4
AE1
AD2
AD1
U9
AD3

AB4

E6
F5
F4
D5
E4
L9
D6

E7

D10
E10
F9
F10
E9
D8
C7
B7

N6
M5

AE27
AD27
AE26
AD26
AD25
D7

AF13
AF14

R756

2@

0_0402_5%~D

1 2

GPIO10_SW_VREF

1 2

R787
2K_0402_5%~D

RAM_CFG0
RAM_CFG1

PCI_DEVID2
PCI_DEVID0
PCI_DEVID1

RAM_CFG2
RAM_CFG3

PCI_DEVID3

1 2

R48 2K_0402_5%~D @

BAR2_SIZE
PCI_DEVID4

1 2

R58

10K_0402_5%~D

CRT_HSYNC
CRT_VSYNC
CRT_RED
CRT_BLU
CRT_GRN

R204 124_0402_1%~D

1 2

DACAVREF

1 2

C299 0.01U_0402_16V7K~D

TV_C
TV_CVBS
TV_Y

DACB_RSET
DACBVREF

R171 124_0402_1%~D
C217 0.01U_0402_16V7K~D

CRTDDCCLK
CRTDDCDAT
DVI_SCLK
DVI_SDATA
LCD_DDCCLK
LCD_DDCDATA
I2CH_SCL
I2CH_SDA

T8 P AD
T9 P AD

T76 PAD~D
T77 PAD~D
T78 PAD~D

12

12

R203
10K_0402_5%~D

R173

10K_0402_5%~D

R103

1 2

2K_0402_5%~D

DVI_DETECT 36
BIA_PWM 19

ENVDD 19
PANEL_BKEN 38
GFX_CORE_CNTRL 51

THERMTRIP_VGA# 18

GPIO10_SW_VREF 53,56

RAM_CFG0 57
RAM_CFG1 57

T25 PAD~D

PCI_DEVID0 57
PCI_DEVID1 57

T26 PAD~D

PCI_IOBAR 57
RAM_CFG2 57
RAM_CFG3 57

T27 PAD~D

PCI_DEVID3 57

+3.3V_RUN

BAR2_SIZE 57
PCI_DEVID4 57

CRT_HSYNC 20
CRT_VSYNC 20
CRT_RED 20,36
CRT_BLU 20,36
CRT_GRN 20,36

TV_C 36
TV_CVBS 36
TV_Y 36

1 2
1 2

DVI_SCLK 36
DVI_SDATA 36
LCD_DDCCLK 19
LCD_DDCDATA 19

I2CH_SCL 19
I2CH_SDA 19

1 2

R215 0_0402_5%~D@

GFX_DEVID2 38
PCI_DEVID2 57

Reserved for GFx debug

<---CRT
<---DVI
<---SVIDEO

12

2

1 3

D

R37

G

2.2K_0402_5%~D

Q36

S

2N7002W-7-F_SOT323-3~D

2

2

1 3

D

G

S

+3.3V_RUN

Q37
2N7002W-7-F_SOT323-3~D

LCD_DDCCLK
LCD_DDCDATA
DVI_SCLK
DVI_SDATA

I2CH_SCL
I2CH_SDA

TV_C

TV_CVBS

TV_Y

CRT_RED

CRT_BLU

CRT_GRN

DAT_DDC220,36CLK_DDC220,36

1 2

R169 2.2K_0402_5%~D

1 2

R167 2.2K_0402_5%~D

1 2

R170 2.2K_0402_5%~D

1 2

R175 2.2K_0402_5%~D

1 2

R163 10K_0402_5%~D

1 2

R30 10K_0402_5%~D

1 2

R776 150_0402_5%~D

1 2

R777 150_0402_5%~D

1 2

R778 150_0402_5%~D

1 2

R779 150_0402_5%~D

1 2

R780 150_0402_5%~D

1 2

R781 150_0402_5%~D

DAT_DDC2CRTDDCCLKCLK_DDC2

+3.3V_RUN+3.3V_RUN

12

1

R38

2.2K_0402_5%~D

CRTDDCDAT

A A

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

NVG86 PCIE,GPIO,CLK

LA-3302P

52 66Thursday, March 01, 2007

1

0.4

of

5

4

3

2

1

FBAD[0:63]

FBAA[0:11]

FBBA[2:5]

DQMA#[0:7]

D D

FBAD0
FBAD1
FBAD2
FBAD3
FBAD4
FBAD5
FBAD6
FBAD7
FBAD8
FBAD9
FBAD10
FBAD11
FBAD12
FBAD13
FBAD14
FBAD15
FBAD16
FBAD17
FBAD18
FBAD19
FBAD20
FBAD21
FBAD22
FBAD23
FBAD24
FBAD25
FBAD26

C C

B B

FBAD27
FBAD28
FBAD29
FBAD30
FBAD31
FBAD32
FBAD33
FBAD34
FBAD35
FBAD36
FBAD37
FBAD38
FBAD39
FBAD40
FBAD41
FBAD42
FBAD43
FBAD44
FBAD45
FBAD46
FBAD47
FBAD48
FBAD49
FBAD50
FBAD51
FBAD52
FBAD53
FBAD54
FBAD55
FBAD56
FBAD57
FBAD58
FBAD59
FBAD60
FBAD61
FBAD62
FBAD63

U10B

A26

FBAD0

C24

FBAD1

B24

FBAD2

A24

FBAD3

C22

FBAD4

A25

FBAD5

B25

FBAD6

D23

FBAD7

G22

FBAD8

J23

FBAD9

E24

FBAD10

F23

FBAD11

J24

FBAD12

F24

FBAD13

G23

FBAD14

H24

FBAD15

D16

FBAD16

E16

FBAD17

D17

FBAD18

F18

FBAD19

E19

FBAD20

E18

FBAD21

D20

FBAD22

D19

FBAD23

A18

FBAD24

B18

FBAD25

A19

FBAD26

B19

FBAD27

D18

FBAD28

C19

FBAD29

C16

FBAD30

C18

FBAD31

N26

FBAD32

N25

FBAD33

R25

FBAD34

R26

FBAD35

R27

FBAD36

T25

FBAD37

T27

FBAD38

T26

FBAD39

AB23

FBAD40

Y24

FBAD41

AB24

FBAD42

AB22

FBAD43

AC24

FBAD44

AC22

FBAD45

AA23

FBAD46

AA22

FBAD47

T24

FBAD48

T23

FBAD49

R24

FBAD50

R23

FBAD51

R22

FBAD52

T22

FBAD53

N23

FBAD54

P24

FBAD55

AA24

FBAD56

AA27

FBAD57

AA26

FBAD58

AB25

FBAD59

AB26

FBAD60

AB27

FBAD61

AA25

FBAD62

W25

FBAD63

G86-620-A2_BGA533~D

Part 2 of 5

MEMORY INTERFACE

FBA_CMD0
FBA_CMD1
FBA_CMD2
FBA_CMD3
FBA_CMD4
FBA_CMD5
FBA_CMD6
FBA_CMD7
FBA_CMD8

FBA_CMD9
FBA_CMD10
FBA_CMD11
FBA_CMD12
FBA_CMD13
FBA_CMD14
FBA_CMD15
FBA_CMD16
FBA_CMD17
FBA_CMD18
FBA_CMD19
FBA_CMD20
FBA_CMD21
FBA_CMD22
FBA_CMD23
FBA_CMD24
FBA_CMD25
FBA_CMD26

FBADQM0
FBADQM1
FBADQM2
FBADQM3
FBADQM4
FBADQM5
FBADQM6
FBADQM7

FBADQS_RN0
FBADQS_RN1
FBADQS_RN2
FBADQS_RN3
FBADQS_RN4
FBADQS_RN5
FBADQS_RN6
FBADQS_RN7

FBADQS_WP0
FBADQS_WP1
FBADQS_WP2
FBADQS_WP3
FBADQS_WP4
FBADQS_WP5
FBADQS_WP6
FBADQS_WP7

FB_VREF

FBA_CLK0

FBA_CLK0_N

FBA_CLK1

FBA_CLK1_N

FBA_REFCLK

FBA_REFCLK_N

FBA_DEBUG

FBAD[0:63] 56

FBAA[0:11] 56

FBBA[2:5] 56

DQMA#[0:7] 56

G27
D25
F26
F25
G25
J25
J27
M26
C27
C25
D24
N27
G24
J26
M27
C26
M25
D26
D27
K26
K25
K24
F27
K27
G26
B27
N24

D21
F22
F20
A21
V27
W22
V22
V24

A22
E22
F21
B21
V26
W23
V23
W27

B22
D22
E21
C21
V25
W24
U24
W26

A16
L24

K23
M22
N22
M23
M24
K22

FBAA4
FBARAS#
FBAA5
FBA_BA1
FBBA2
FBBA4
FBBA3
FBACS1#
FBACS0#
FBAA11
FBACAS#
FBAWE#
FBA_BA0
FBBA5

FBA_RST#
FBAA7
FBAA10
FBA_CKE
FBAA0
FBAA9
FBAA6
FBAA2
FBAA8
FBAA3
FBAA1

DQMA#0
DQMA#1
DQMA#2
DQMA#3
DQMA#4
DQMA#5
DQMA#6
DQMA#7

DQSA_RN0
DQSA_RN1
DQSA_RN2
DQSA_RN3
DQSA_RN4
DQSA_RN5
DQSA_RN6
DQSA_RN7

DQSA_WP0
DQSA_WP1
DQSA_WP2
DQSA_WP3
DQSA_WP4
DQSA_WP5
DQSA_WP6
DQSA_WP7

FBA_VREF

CLKA0
CLKA0#
CLKA1
CLKA1#

T6 PAD

10mil

CLKA0 56
CLKA0# 56
CLKA1 56
CLKA1# 56

GPIO10_SW_VREF52,56

FBARAS# 56
FBA_BA1 56

FBACS1# 56
FBACS0# 56

FBACAS# 56
FBAWE# 56
FBA_BA0 56

FBA_RST# 56

LCD_ACLK+

1

C39

@

3.3P_0402_50V8C

2

LCD_ACLK­LCD_BCLK+

1

C43

@

3.3P_0402_50V8C~D

2

LCD_BCLK-

Keep stub for caps
as small as possible

FBA_CKE 56

12

R190
10K_0402_5%~D

DQSA_WP[0:7]
DQSA_RN[0:7]

Populate R828 for G86
Populate R605 for G72.
R828,R605 place overlap

12

12

R605

1@

909_0402_1%~D

R828

2@

487_0402_1%~D

GPU_SW_VREF

13

D

Q59

2

2N7002W-7-F_SOT323-3~D

G

S

LCD_ACLK+19
LCD_ACLK-19
LCD_A0+19
LCD_A0-19
LCD_A1+19
LCD_A1-19
LCD_A2+19
LCD_A2-19

LCD_BCLK+19
LCD_BCLK-19
LCD_B0+19
LCD_B0-19
LCD_B1+19
LCD_B1-19
LCD_B2+19
LCD_B2-19

DVI_CLK+36
DVI_CLK-36
DVI_TX0+36
DVI_TX0-36
DVI_TX1+36
DVI_TX1-36
DVI_TX2+36
DVI_TX2-36

DQSA_WP[0:7] 56
DQSA_RN[0:7] 56

C48

0.022U_0402_16V7K~D

1

2

10mil

1K_0402_5%~D

+1.8V_RUN

12

R29
511_0402_1%~D

12

R31

1.18K_0402_1%~D

LCD_ACLK+
LCD_ACLK­LCD_A0+
LCD_A0­LCD_A1+
LCD_A1­LCD_A2+
LCD_A2-

LCD_BCLK+
LCD_BCLK­LCD_B0+
LCD_B0­LCD_B1+
LCD_B1­LCD_B2+
LCD_B2-

R200

DVI_CLK+
DVI_CLK­DVI_TX0+
DVI_TX0­DVI_TX1+
DVI_TX1­DVI_TX2+
DVI_TX2-

R50

U10C

T4

IFPA_TXC

U4

IFPA_TXC_N

N4

IFPA_TXD0

N5

IFPA_TXD0_N

R5

IFPA_TXD1

R4

IFPA_TXD1_N

T5

IFPA_TXD2

T6

IFPA_TXD2_N

R6

IFPA_TXD3

P6

IFPA_TXD3_N

W5

IFPB_TXC

W6

IFPB_TXC_N

W3

IFPB_TXD4

W2

IFPB_TXD4_N

AA2

IFPB_TXD5

AA3

IFPB_TXD5_N

AB1

IFPB_TXD6

AA1

IFPB_TXD6_N

AB3

IFPB_TXD7

AB2

IFPB_TXD7_N

U6

12

1K_0402_5%~D

IFPAB_RSET

V1

IFPC_TXC

W1

IFPC_TXC_N

T1

IFPC_TXD0

R1

IFPC_TXD0_N

T3

IFPC_TXD1

T2

IFPC_TXD1_N

V2

IFPC_TXD2

V3

IFPC_TXD2_N

J3

IFPCD_RSET

12

Part 3 of 5

LVDS/TMDS

LCD_A0+
LCD_A1+
LCD_A2+
LCD_B0+
LCD_B1+
LCD_B2+

NC

GENERAL

SERIAL

G86-620-A2_BGA533~D

DVI_CLK+
DVI_CLK­DVI_TX0+

DVI_TX0-

DVI_TX1+

DVI_TX1­DVI_TX2+
DVI_TX2-

1 2

C181 3.3P_0402_50V8C~D@

1 2

C192 3.3P_0402_50V8C~D@

1 2

C193 3.3P_0402_50V8C~D@

1 2

C196 3.3P_0402_50V8C~D@

1 2

C207 3.3P_0402_50V8C~D@

1 2

C209 3.3P_0402_50V8C~D@

MIO_A_D0
MIO_A_D1
MIO_A_D2
MIO_A_D3
MIO_A_D4
MIO_A_D5
MIO_A_D6
MIO_A_D7
MIO_A_D8
MIO_A_D9

MIO_A_D10

MIO_A_HSYNC

NC_0
NC_1
NC_2
NC_3

BUFRST_N

STEREO

SWAPRDY

THERMDN
THERMDP

ROM_SCLK

ROM_SI

ROM_SO

ROMCS_N

R202 49.9_0402_1%~D
R201 49.9_0402_1%~D
R192 49.9_0402_1%~D
R191 49.9_0402_1%~D
R193 49.9_0402_1%~D
R188 49.9_0402_1%~D
R197 49.9_0402_1%~D
R195 49.9_0402_1%~D

LCD_A0­LCD_A1­LCD_A2­LCD_B0­LCD_B1­LCD_B2-

A2
B3
A3
D4
A4
B4
B6
P4
C6
G5
V4

C4

D12
E12
F12
C13

A6

F7
A7

C9
B9

D2
F3
D3
D1

PEX_PLL_EN_TERM100
SUB_VENDOR

3GIO_ADR_0
3GIO_ADR_1

3GIO_ADR_2

MIOA_HSYNC

10K_0402_5%~D

VGA_THERMDN
VGA_THERMDP

+IFPC_IOVDD

12
12
12
12
12
12
12
12

T79 PAD~D
T80 PAD~D
T81 PAD~D
T82 PAD~D

T83 PAD~D

T84 PAD~D
T85 PAD~D

T90 PAD~D

+3.3V_RUN

R34

12

1 2

C58 0.01U_0402_16V7K~D

1 2

C56 0.01U_0402_16V7K~D

1 2

C286 0.01U_0402_16V7K~D

1 2

C276 0.01U_0402_16V7K~D

PEX_PLL_EN_TERM100 57
SUB_VENDOR 57

3GIO_ADR_0 57
3GIO_ADR_1 57

3GIO_ADR_2 57

VGA_THERMDN 18
VGA_THERMDP 18

Keep stub for
caps as small
as possible

A A

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

NVG86 Memory Interface

LA-3302P

53 66Thursday, March 01, 2007

1

0.4

of

5

+1.25V_GFX_PCIE

+2.5V_RUN

1 @

BLM18AG121SN1D_0603~D

D D

+1.25V_GFX_PCIE

BLM18AG121SN1D_0603~D

1 2

+1.25V_GFX_PCIE

1@

BLM18AG121SN1D_0603~D

Populate C251, C255 for G86

C C

and G72 solution per Nvidia

+1.25V_GFX_PCIE

2@

BLM18AG121SN1D_0603~D

For G8x use. NC for G7x

B B

A A

L53

2@

BLM18AG121SN1D_0603~D

1 2
1 2

L16

C233

L14

1

C188

2

4.7U_0603_6.3V4Z~D

12

L17

C251

1 2

L27

1.25V_GFX_PCIE_ON39

1

2

6.6

2.2U_0603_6.3V6K~D

+FBA_PLLAVDD

1

C197

2

0.1U_0402_10V7K~D

+G72_PLLVDD

1

2

0.1U_0402_10V7K~D

+FBA_PLLVDD

1

C314

2

2@

+1.8V_RUN

1

2

+1.8V_RUN

1

2

5

+2.5V_RUN for G7x
+1.25V_GFX_PCIE for G8x.

+PLLVDD

40mA

1

1

C219

C220

1

2

4.7U_0603_6.3V4Z~D

4.7U_0603_6.3V4Z~D

4.7U_0603_6.3V4Z~D

4700P_0402_25V7K~D

C201

1

2

C289

C303

1000P_0402_50V7K~D

C255

2

2

G

1

2

4.7U_0603_6.3V4Z~D

C315

2@

0.1U_0402_10V7K~D

1

2

1

2

+3.3V_ALW2

2

470P_0402_50V7K~D

1

C252

2

0.1U_0402_10V7K~D

1

C277

2

0.1U_0402_10V7K~D

12

R300

@

100K_0402_5%~D

13

D

Q99

S

@

2N7002W-7-F_SOT323-3~D

+GPU_CORE

C218

C249

0.1U_0402_10V7K~D

C213

0.1U_0402_10V7K~D

1

C61

2

10U_0805_4VAM~D

1

C57

2

10U_0805_4VAM~D

1

C187

2

10U_0805_4VAM~D

+3.3V_RUN

1

1

C236

2

2

0.1U_0402_10V7K~D

1U_0603_10V4Z~D

1

1

C265

2

2

0.022U_0402_16V7K~D

1

1

C212

2

2

0.1U_0402_10V7K~D

+15V_ALW

12

R292

@

13

D

2

G

S

Q98

@

2N7002W-7-F_SOT323-3~D

C259

C221

C240

0.022U_0402_16V7K~D

C230

0.1U_0402_10V7K~D

100K_0402_5%~D

1

2

0.1U_0402_10V7K~D

1

C238

2

0.1U_0402_10V7K~D

1

C261

2

0.1U_0402_10V7K~D

1

C274

2

0.1U_0402_16V4Z~D

1

2

0.1U_0402_10V7K~D

1

2

0.022U_0402_16V7K~D

1

2

0.1U_0402_10V7K~D

+1.25V_RUN

C280

C214

4

1

1

C258

C260

2

2

2200P_0402_50V7K~D

0.022U_0402_16V7K~D

1

C248

C246

2

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

1

C271

C247

2

0.1U_0402_10V7K~D

2200P_0402_50V7K~D

1

C272

C273

2

220P_0402_50V7K~D

0.022U_0402_16V7K~D

1

1

C215

C234

2

2

0.1U_0402_10V7K~D
4700P_0402_25V7K~D

1

1

C269

2

2

0.022U_0402_16V7K~D

1

1

C244

2

2

0.022U_0402_16V7K~D

Q97

@

SI4810DY-T1-E3_SO8~D

8
7

5

4

12

1

C85

2

@

470P_0402_50V7K~D

4

1

1

C245

2

2

0.022U_0402_16V7K~D

1

1

C281

2

2

0.022U_0402_16V7K~D

1

2

1

C237

2

4700P_0402_25V7K~D

1

C263

2

4700P_0402_25V7K~D

4700P_0402_25V7K~D

1

C257

2

4700P_0402_25V7K~D

0.022U_0402_16V7K~D

1 2

1
2
36

R244
470K_0402_5%~D

@

+G72_PLLVDD

1

C216

2

4700P_0402_25V7K~D

C254

1

C266

C235

2

4700P_0402_25V7K~D

PJP2

PAD-OPEN 4x4m

+1.25V_GFX_PCIE

1

C205

2

10U_0805_4VAM~D

+1.25V_RUN

1

C206

2

W13
W15
W16

W10
W11
W12

W19

10U_1206_6.3V7K~D

J9
J10
J11
L12
L13
L15
L16

M9
M11
M12
M13
M14
M15
M16
M17

N9
N11
N17

R9
R11
R17

T9
T11
T12
T13
T14
T15
T16
T17
U12
U13
U15
U16

W9

F13
F14

J12
J13
J15
J16

E15
F15
F16

J17
J18

L19
N19
R19
U19

F17
F19

J19

J22

L22
M19
P22
T19
U22
Y22

U10D

VDD_0
VDD_1
VDD_2
VDD_3
VDD_4
VDD_5
VDD_6
VDD_7
VDD_8
VDD_9
VDD_10
VDD_11
VDD_12
VDD_13
VDD_14
NV_PLLAVDD
VDD_16
VDD_17
VDD_18
VDD_19
VDD_20
VDD_21
VDD_22
VDD_23
VDD_24
VDD_25
VDD_26
VDD_27
VDD_28
VDD_29
VDD_30
VDD_31
VDD_32
VDD_33
VDD_34
VDD_35

VDD_LP_0
VDD_LP_1
VDD_LP_2
VDD_LP_3

VDD33_0
VDD33_1
VDD33_2
VDD33_3
VDD33_4
VDD33_5

FBVTT_0
FBVTT_1
FBVTT_2
FBVTT_3
FBVTT_4
FBVTT_5
FBVTT_6
FBVTT_7
FBVTT_8
FBVTT_9

FBVDDQ_0
FBVDDQ_1
FBVDDQ_2
FBVDDQ_3
FBVDDQ_4
FBVDDQ_5
FBVDDQ_6
FBVDDQ_7
FBVDDQ_8
FBVDDQ_9

3

1808mA

IFPA_IOVDD
IFPB_IOVDD

IFPC_IOVDD

DACA_VDD
DACB_VDD

PLLVDD

CLAMP

3

W17
W18
AB10
AB11
AB14
AB15
AB20
AB21
AA4
AB5
AB6
AB7
AB8
AB9
AB12
AB13
AB16
AB17
AB18
AB19
AC9
AC11
AC12
AC16
AC17
AC19
AC20

Y6
AA5

K5
K6
L6

J5

F6
G6
J6

W4
Y4
L4

40mA

V5

40mA

M4
AE2

F8

H4
D13
D14
D15

D11

13

D

2

G

S

C292

+PEX_PLLAVDD
+PEX_PLLDVDD

+MIOBCAL_PD_VDDQ

1

2

+IFPAB_IOVDD
+IFPC_IOVDD

+IFPAB_PLLVDD
+IFPCD_PLLVDD
+DACA_VDD

+DACB_VDD

+PLLVDD
+FBA_PLLAVDD
+FBA_PLLVDD

R35

45.3_0402_1%~D2@

R825

60.4_0402_1%~D 1@

Populate R825 for G72MV
Populate R35 for G86MV.
R825,R35 place overlap

2

G

1 2

R61

10K_0402_5%~D
Q15

2N7002W-7-F_SOT323-3~D

C291

1

C278

2

0.022U_0402_16V7K~D

180mA
20mA

C239

0.1U_0402_10V7K~D

70mA
140mA

12

12

+3.3V_RUN

13

D

Q14
SI1303DL-T1-E3_SOT323-3~D

S

PEX_IOVDD_0

Part 4 of 5

PEX_IOVDD_1
PEX_IOVDD_2
PEX_IOVDD_3
PEX_IOVDD_4
PEX_IOVDD_5
PEX_IOVDD_6

PEX_IOVDD_7
PEX_IOVDDQ_0
PEX_IOVDDQ_1
PEX_IOVDDQ_2
PEX_IOVDDQ_3
PEX_IOVDDQ_4
PEX_IOVDDQ_5
PEX_IOVDDQ_6
PEX_IOVDDQ_7
PEX_IOVDDQ_8
PEX_IOVDDQ_9

PEX_IOVDDQ_10
PEX_IOVDDQ_11
PEX_IOVDDQ_12
PEX_IOVDDQ_13
PEX_IOVDDQ_14
PEX_IOVDDQ_15
PEX_IOVDDQ_16
PEX_IOVDDQ_17
PEX_IOVDDQ_18

PEX_PLLAVDD
PEX_PLLDVDD

POWER

MIOB_VDDQ_0
MIOB_VDDQ_1
MIOB_VDDQ_2

MIOBCAL_PD_VDDQ

MIO_A_VDDQ_0
MIO_A_VDDQ_1
MIO_A_VDDQ_2

IFPAB_PLLVDD

IFPCD_PLLVDD

FBA_PLLAVDD

FBA_PLLVDD

FBCAL_PD_VDDQ

G86-620-A2_BGA533~D

RUNPWROK38,39,42,48

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

1

1

C279

2

2

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

1

1

C295

2

2

0.1U_0402_10V7K~D

0.022U_0402_16V7K~D

T7
PAD

+3.3V_RUN

C317

+1.8V_RUN

L18

BLM18AG121SN1D_0603~D

C300

1

2

470P_0402_50V7K~D

12

2

1

C306

2

0.1U_0402_10V7K~D

1

C296

2

0.1U_0402_10V7K~D

1

C243

0.1U_0402_10V7K~D

2

C324

4.7U_0603_6.3V4Z~D

C302

470P_0402_50V7K~D

C294

470P_0402_50V7K~D

1

C241

2

2

C298

0.1U_0402_10V7K~D

1

2

0.1U_0402_10V7K~D

+3.3V_RUN

1

2

1

2

1

2

0.1U_0402_16V4Z~D

C72

1

2

4.7U_0603_6.3V4Z~D

1

C288

2

0.1U_0402_10V7K~D

1 2

BLM18AG121SN1D_0603~D

1

C311

2

4700P_0402_25V7K~D

1

C308

2

4.7U_0603_6.3V4Z~D

1

C307

2

4.7U_0603_6.3V4Z~D

+IFPC_IOVDD

1

1

C242

2

2

470P_0402_50V7K~D

1

+1.25V_GFX_PCIE

1

2

L23

C290

C253

C59

1

C337

2

C71

4.7U_0603_6.3V4Z~D

1

2

4700P_0402_25V7K~D

1

2

4700P_0402_25V7K~D

4.7U_0603_6.3V4Z~D

10U_0805_10V4Z~D

1

1

C73

2

2

10U_0805_10V4Z~D

1@

BLM18AG121SN1D_0603~D

1 2

1 2

BLM18AG121SN1D_0603~D

+2.5V_RUN for G7x
+1.8V_RUN for G8x.

1 2

BLM18AG121SN1D_0603~D

2@

1 2

BLM18AG121SN1D_0603~D

+2.5V_RUN for G7x
+1.8V_RUN for G8x.

+3.3V_RUN

BLM18AG121SN1D_0603~D

C275

+1.8V_RUN

2@

1@

L54

1

C285

2

L21

L55

L20

L22

BLM18AG121SN1D_0603~D

12

C318

L15

12

C204

+PEX_PLLAVDD

1

2

0.01U_0402_16V7K~D

C63

0.01U_0402_16V7K~D

+2.5V_RUN

+1.8V_RUN

+2.5V_RUN

+1.8V_RUN

1

2

4700P_0402_25V7K~D

1

2

4700P_0402_25V7K~D

1

C62

2

0.1U_0402_10V7K~D

1

2

1U_0603_10V4Z~D

1

C328

2

1

C191

2

DELL CONFIDENTIAL/PROPRIETARY

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

NVG86 Power

LA-3302P

1

+1.25V_GFX_PCIE

L5

10NH_LQG15HS10NJ02D_5%_0402~D

1

2

2.2U_0603_6.3V6K~D

2.2U_0603_6.3V6K~D

C70

4.7U_0603_6.3V4Z~D

+DACA_VDD

1

C313

2

470P_0402_50V7K~D

+DACB_VDD

1

C198

2

470P_0402_50V7K~D

54 66Thursday, March 01, 2007

12

of

0.4

5

D D

T89PAD~D

C C

B B

4

U10E

B2

GND_0

B5

GND_1

B8

GND_2

B11

GND_3

B14

GND_4

B17

GND_5

B20

GND_6

B23

GND_7

B26

GND_8

E2

GND_9

E5

GND_10

E8

GND_11

E11

GND_12

E14

GND_13

E17

GND_14

E20

GND_15

E23

GND_16

E26

GND_17

F11

GND_18

H2

GND_19

H6

GND_20

H23

GND_21

H26

GND_22

J14

GND_23

K9

GND_24

K19

GND_25

L2

GND_26

L5

GND_27

L11

GND_28

L14

GND_29

L17

GND_30

L23

GND_31

L26

GND_32

N12

GND_33

N13

GND_34

N14

GND_35

N15

GND_36

N16

GND_37

P2

GND_38

P5

GND_39

P9

GND_40

P11

GND_41

P12

GND_42

P13

GND_43

P14

GND_44

P15

GND_45

P16

GND_46

P17

GND_47

P19

GND_48

P23

GND_49

P26

GND_50

R12

GND_51

R13

GND_52

R14

GND_53

R15

GND_54

R16

GND_55

U2

GND_56

U5

GND_57

U11

GND_58

U14

GND_59

Part 5 of 5

GND

FBCAL_TERM_GND

G86-620-A2_BGA533~D

IFPAB_PLLGND

IFPCD_PLLGND

MIOBCAL_PU_GND

PEX_PLLGND

FBA_PLLGND

FBCAL_PU_GND

GND_60
GND_61
GND_62
GND_63
GND_64
GND_65
GND_66
GND_67
GND_68
GND_69
GND_70
GND_71
GND_72
GND_73
GND_74
GND_75
GND_76
GND_77
GND_78
GND_79
GND_80
GND_81
GND_82
GND_83
GND_84
GND_85
GND_86
GND_87
GND_88
GND_89
GND_90
GND_91
GND_92
GND_93
GND_94

PLLGND

U17
U23
U26
V9
V19
W14
Y2
Y5
Y23
Y26
AC2
AC8
AC14
AC23
AC26
AD8
AD9
AD11
AD12
AD14
AD16
AD17
AD19
AD20
AC5
AF2
AF3
AF6
AF9
AF12
AF15
AF18
AF21
AF24
AF26

V6
M6

M3
AA6
H5

C15

E13
H22

3

12

12

R757

12

R174

2@

40.2_0402_1%~D

24.9_0402_1%~D

Populate R824 for G72MV

R824

Populate R174 for G86.

1@

R174,R824 place overlap

40.2_0402_1%~D

2

1

A A

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

NVG86 Ground

LA-3302P

55 66Thursday, March 01, 2007

1

0.4

of

5

R829,R830 for G86
R402,R403 for G72MV.
R829,R402 and R830,R403 place overlap

D D

2

G

Q66

2N7002W-7-F_SOT323-3~D

VREF_SW_A1 VREF_SW_A2

C C

Populate R827 for G86
Populate R172 for G72MV.

R172,R827 place overlap
and close to U49

B B

+1.8V_RUN

GPIO10_SW_VREF 52,53 GPIO10_SW_VREF 52,53

+1.8V_RUN +1.8V_RUN

12

R829

2@

487_0402_1%~D

VREF_SW_A1

13

D

S

R403

1@

909_0402_1%~D

1 2
1 2

R830

2@

487_0402_1%~D

12

R827

2@

243_0402_1%~D

1 2

R402

1@

909_0402_1%~D

1 2

+1.8V_RUN +1.8V_RUN

12

R744

12

CLKA0#

12

R172

1@

120_0402_5%~D

CLKA0

511_0402_1%~D

R746

R737

FBA_BA053
FBA_BA153

511_0402_1%~D

12

1

C908

R742

2

1.18K_0402_1%~D

0.1U_0402_10V7K~D

1

C910

2

1.18K_0402_1%~D

FBARAS#53
FBACAS#53
FBAWE#53
FBACS0#53

0.1U_0402_10V7K~D

FBA_CKE53
CLKA053
CLKA0#53 CLKA1#53

1 2

R748 240_0402_5%~D

FBA_RST#53
FBACS1#53

R752

FBAA0
FBAA1
FBAA2
FBAA3
FBAA4
FBAA5
FBAA6
FBAA7
FBAA8
FBAA9
FBAA10
FBAA11
FBA_BA0
FBA_BA1

DQMA#0
DQMA#1
DQMA#2
DQMA#3

DQSA_WP0
DQSA_WP1
DQSA_WP2
DQSA_WP3

10mil

FBA_VREF0

10mil

FBA_VREF2

FBARAS#
FBACAS# FBAD27
FBAWE#
FBACS0#

FBA_CKE
CLKA0
CLKA0#

DQSA_RN0
DQSA_RN1
DQSA_RN2
DQSA_RN3

+1.8V_RUN

FBA_RST#
FBACS1#

12

10K_0402_5%~D

Place below decoupling caps close U11 VDD Pins

1

C916

2

+1.8V_RUN

4.7U_0603_6.3V6M~D

1

C917

2

1

1

1

C918

C920

C919

2

0.1U_0402_10V7K~D

2

2

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

0.01U_0402_16V7K~D

1

C921

2

1

1

1

C923

C924

C922

2

2

2

100P_0402_50V8J~D

470P_0402_50V7K~D

0.01U_0402_16V7K~D

1000P_0402_50V7K~D

Place below decoupling caps close U11 VDDQ Pins

1

1

C934

2

A A

4.7U_0603_6.3V6M~D

1

C952

2

1000P_0402_50V7K~D

1

1

C935

2

4.7U_0603_6.3V6M~D

1

C953

2

1000P_0402_50V7K~D

1

C936

C937

C938

2

1

C954

2

2

2

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

1

1

C955

C956

2

2

470P_0402_50V7K~D

470P_0402_50V7K~D

470P_0402_50V7K~D

5

1

1

C939

2

0.01U_0402_16V7K~D

1

C957

2

100P_0402_50V8J~D

1

1

C941

C942

C940

2

2

2

0.01U_0402_16V7K~D

0.01U_0402_16V7K~D

0.01U_0402_16V7K~D

1

1

C958

C959

2

2

100P_0402_50V8J~D

100P_0402_50V8J~D

U49

VSSQB1VSSQB4VSSQB9VSSQ

K4

A0

H2

A1

K3

A2

M4

A3

K9

A4

H11

A5

K10

A6

L9

A7

K11

A8/AP

M9

A9

K2

A10

L4

A11

G4

BA0

G9

BA1

E3

DM0

E10

DM1

N10

DM2

N3

DM3

D2

WDQS0

D11

WDQS1

P11

WDQS2

P2

WDQS3

H1

VREF

H12

VREF

J2

RFU1

J3

RFU2

H3

RAS#

F4

CAS#

H9

WE#

F9

CS#

H4

CKE

J11

CK

J10

CK#

A4

ZQ

A9

MF

D3

RDQS0

D10

RDQS1

P10

RDQS2

P3

RDQS3

A2

VDD

A11

VDD

F1

VDD

F12

VDD

M1

VDD

M12

VDD

V2

VDD

V11

VDD

V4

SEN

V9

RESET

H10

BA2

J1

VSSA

J12

VSSA

+1.8V_RUN

Place below decoupling caps close U14 VDD Pins

+1.8V_RUN

Place below decoupling caps close U14 VDDQ Pins

1

C925

2

1

C943

2

1

C960

2

B12

D12

VSSQD1VSSQD4VSSQD9VSSQ

1

C926

2

0.1U_0402_10V7K~D

4.7U_0603_6.3V6M~D

1

C944

2

4.7U_0603_6.3V6M~D

4.7U_0603_6.3V6M~D

1

C961

2

1000P_0402_50V7K~D

1000P_0402_50V7K~D

4

VSSQG2VSSQ

VSSA3VSS

A10

1

C927

2

1

C945

2

1

C962

2

4

G11

L11

P12

VSSQL2VSSQ

VSSQP1VSSQP4VSSQP9VSSQ

VSSG1VSS

VSSL1VSS

VSSV3VSS

K4J52324QE-BC14_FBGA136~D

L12

V10

G12

1

1

C928

C929

2

2

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

1

1

C947

C946

2

2

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

1

1

C964

C963

2

2

470P_0402_50V7K~D

470P_0402_50V7K~D

VSSQT1VSSQT4VSSQT9VSSQ

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8

DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

VDDA
VDDA

1

C930

2

0.01U_0402_16V7K~D

0.01U_0402_16V7K~D

1

C948

2

0.1U_0402_10V7K~D

0.01U_0402_16V7K~D

1

C965

2

100P_0402_50V8J~D

470P_0402_50V7K~D

3

VREF=VDDQ x Rb/(Ra+Rb)
VREF=0.7 x VDDQ for G86 trun on, 0.4x VDDQ when trun off
VREF=0.7 x VDDQ for G72MV trun on, 0.5x VDDQ when trun off

T12

FBAD4

B2

FBAD7

B3

FBAD1

C2

FBAD3

C3

FBAD2

E2

FBAD5

F3

FBAD0

F2

FBAD6

G3

FBAD9

B11

FBAD12

B10

FBAD15

C11

FBAD8

C10

FBAD11

E11

FBAD10

F10

FBAD13

F11

FBAD14

G10

FBAD17

M11

FBAD23

L10

FBAD20

N11

FBAD22

M10

FBAD19

R11

FBAD18

R10

FBAD16

T11

FBAD21

T10

FBAD31

M2

FBAD30

L3

FBAD26

N2

FBAD24

M3

FBAD25

R2

FBAD29

R3
T2

FBAD28

T3

A1
A12
C1
C4
C9
C12
E1
E4
E9
E12
J4
J9
N1
N4
N9
N12
R1
R4
R9
R12
V1
V12

FBA_VDDA0

K1

FBA_VDDA1

K12

C912 0.047U_0402_16V4Z~D

1 2

C914 0.047U_0402_16V4Z~D

1 2

1

1

1

C931

C933

C932

2

2

2

470P_0402_50V7K~D

1000P_0402_50V7K~D

1

1

1

C949

C950

C951

2

2

2

0.01U_0402_16V7K~D

0.01U_0402_16V7K~D

1

1

C967

C966

2

2

100P_0402_50V8J~D

100P_0402_50V8J~D

R831,R832 for G86
R404,R405 for G72MV.
R831,R404 and R832,R405 place overlap

R831

2@

487_0402_1%~D

1 2

R404

1@

909_0402_1%~D

+1.8V_RUN

100P_0402_50V8J~D

0.01U_0402_16V7K~D

VREF_SW_A2

13

D

2

G

S

Q67

2N7002W-7-F_SOT323-3~D

1@

909_0402_1%~D

1 2

R832

2@

487_0402_1%~D

L83 BLM18PG181SN1_0603~D

12
12

L85 BLM18PG181SN1_0603~D

1 2

511_0402_1%~D

12

R745

R405

1 2

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

12

R747

1.18K_0402_1%~D

+1.8V_RUN

12

R826

2@

243_0402_1%~D

Populate R826 for G86
Populate R177 for G72MV.

R177,R826 place overlap
and close to U50

3

12

R743

1.18K_0402_1%~D

1

C911

2

+1.8V_RUN

CLKA1#

12

R177

1@

120_0402_5%~D

CLKA1

511_0402_1%~D

12

R738

1

C909

2

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

CLKA153

12

R749

240_0402_5%~D

FBAD[0:63]
FBAA[0:11]
FBBA[2:5]
DQSA_WP[0:7]
DQSA_RN[0:7]
DQMA#[0:7]

+1.8V_RUN

FBBA4
FBBA5
FBAA6
FBAA9
FBAA0
FBAA1
FBBA2
FBAA11
FBAA10
FBBA3
FBAA8
FBAA7
FBA_BA1
FBA_BA0

DQMA#4
DQMA#7
DQMA#5 FBAD45
DQMA#6

DQSA_WP4
DQSA_WP7
DQSA_WP5
DQSA_WP6

10mil

FBA_VREF1

10mil

FBA_VREF3

FBACS1#
FBACS0#
FBA_CKE
FBACAS#

FBAWE#
CLKA1
CLKA1#

DQSA_RN4
DQSA_RN7
DQSA_RN5
DQSA_RN6

FBA_RST#
FBARAS#

FBAD[0:63] 53

FBAA[0:11] 53

FBBA[2:5] 53

DQSA_WP[0:7] 53
DQSA_RN[0:7] 53
DQMA#[0:7] 53

2

B12

D12

G11

L11

P12

U50

VSSQB1VSSQB4VSSQB9VSSQ

VSSQD1VSSQD4VSSQD9VSSQ

VSSQG2VSSQ

VSSQL2VSSQ

VSSA3VSS

A10

VSSG1VSS

G12

VSSQP1VSSQP4VSSQP9VSSQ

VSSL1VSS

L12

K4

A0

H2

A1

K3

A2

M4

A3

K9

A4

H11

A5

K10

A6

L9

A7

K11

A8/AP

M9

A9

K2

A10

L4

A11

G4

BA0

G9

BA1

E3

DM0

E10

DM1

N10

DM2

N3

DM3

D2

WDQS0

D11

WDQS1

P11

WDQS2

P2

WDQS3

H1

VREF

H12

VREF

J2

RFU1

J3

RFU2

H3

RAS#

F4

CAS#

H9

WE#

F9

CS#

H4

CKE

J11

CK

J10

CK#

A4

ZQ

A9

MF

D3

RDQS0

D10

RDQS1

P10

RDQS2

P3

RDQS3

A2

VDD

A11

VDD

F1

VDD

F12

VDD

M1

VDD

M12

VDD

V2

VDD

V11

VDD

V4

SEN

V9

RESET

H10

BA2

J1

VSSA

J12

VSSA

T12

VSSQT1VSSQT4VSSQT9VSSQ

B2

DQ0

B3

DQ1

C2

DQ2

C3

DQ3

E2

DQ4

F3

DQ5

F2

DQ6

G3

DQ7

B11

DQ8

B10

DQ9

C11

DQ10

C10

DQ11

E11

DQ12

F10

DQ13

F11

DQ14

G10

DQ15

M11

DQ16

L10

DQ17

N11

DQ18

M10

DQ19

R11

DQ20

R10

DQ21

T11

DQ22

T10

DQ23

M2

DQ24

L3

DQ25

N2

DQ26

M3

DQ27

R2

DQ28

R3

DQ29

T2

DQ30

T3

DQ31

A1

VDDQ

A12

VDDQ

C1

VDDQ

C4

VDDQ

C9

VDDQ

C12

VDDQ

E1

VDDQ

E4

VDDQ

E9

VDDQ

E12

VDDQ

J4

VDDQ

J9

VDDQ

N1

VDDQ

N4

VDDQ

N9

VDDQ

N12

VDDQ

R1

VDDQ

R4

VDDQ

R9

VDDQ

R12

VDDQ

V1

VDDQ

V12

VDDQ

VDDA
VDDA

VSSV3VSS

K4J52324QE-BC14_FBGA136~D

V10

K1
K12

C913 0.047U_0402_16V4Z~D
C915 0.047U_0402_16V4Z~D

1 2
1 2

FBA_VDDA2
FBA_VDDA3

FBAD33
FBAD32
FBAD34
FBAD35
FBAD38
FBAD37
FBAD36
FBAD39
FBAD56
FBAD63
FBAD59
FBAD62
FBAD60
FBAD61
FBAD58
FBAD57

FBAD47
FBAD44
FBAD43
FBAD46
FBAD41
FBAD40
FBAD42
FBAD54
FBAD52
FBAD51
FBAD55
FBAD50
FBAD53
FBAD49
FBAD48

+1.8V_RUN

L84 BLM18PG181SN1_0603~D

L86 BLM18PG181SN1_0603~D

Change to 220ohm/100MHzChange to 220ohm/100MHz

1

FBAA4

FBAA5

FBBA2

FBBA4

FBBA3

FBBA5

FBAA2

FBAA3

12
12

R732

1 2

121_0402_1%~D

R733

1 2

121_0402_1%~D

R734

1 2

121_0402_1%~D

R735

1 2

121_0402_1%~D

R736

1 2

121_0402_1%~D

R739

1 2

121_0402_1%~D

R740

1 2

121_0402_1%~D

R741

1 2

121_0402_1%~D

+1.8V_RUN

+1.8V_RUN

DELL CONFIDENTIAL/PROPRIETARY

Title

Size Document Number Rev

2

Date: Sheet

Compal Electronics, Inc.

NVG86 External DDR

LA-3302P

56 66Thursday, March 01, 2007

1

0.4

of

5

4

3

2

1

G72MV STRAPS

+3.3V_RUN

D D

RAM_CFG052
RAM_CFG152
RAM_CFG252

RAM_CFG352
SUB_VENDOR53
3GIO_ADR_053
3GIO_ADR_153
3GIO_ADR_253

BAR2_SIZE52
PCI_IOBAR52

PEX_PLL_EN_TERM10053
PCI_DEVID452
PCI_DEVID352
PCI_DEVID252
PCI_DEVID152
PCI_DEVID052

C C

RAM_CFG0
RAM_CFG1
RAM_CFG2
RAM_CFG3
SUB_VENDOR
3GIO_ADR_0
3GIO_ADR_1
3GIO_ADR_2

BAR2_SIZE
PCI_IOBAR
PEX_PLL_EN_TERM100
PCI_DEVID4
PCI_DEVID3
PCI_DEVID2
PCI_DEVID1
PCI_DEVID0

R798 0_0402_5%~D
R799 0_0402_5%~D
R800 0_0402_5%~D
R801 0_0402_5%~D

R802 0_0402_5%~D

R805 0_0402_5%~D

12
12
12
12

12

12

12

R46

2K_0402_5%~D

12

R47

@

10K_0402_5%~D

12

12

R44

@

2K_0402_5%~D

12

R45

@

10K_0402_5%~D

12

R53

R54

@

2K_0402_5%~D

12

R55

R56

10K_0402_5%~D

2K_0402_5%~D

12

12

R40

2K_0402_5%~D

10K_0402_5%~D

12

12

R33

@

2K_0402_5%~D

12

12

R32

R184

R371

@

2K_0402_5%~D

@

@

2K_0402_5%~D

2K_0402_5%~D

12

R370

@

2K_0402_5%~D

12

12

R360

@

2K_0402_5%~D

12

R43

R57

2@

2K_0402_5%~D

2K_0402_5%~D

12

12

R49

1@

2K_0402_5%~D

12

R52

R51

2K_0402_5%~D

2K_0402_5%~D

Device ID strapping

DEVID3 DEVID2 DEVID1 DEVID0

G72GLM

G72M

G72MV

1

1

1

0

0

1

G86MV 1 101

B B

0

0

0

0

1

1

XTALOUTBUFF52

12

R189

XTALSSIN52

10K_0402_5%~D

0_0402_5%~D

STRAPS PIN DESCRIPTION

MIOBD10 Parallel=00, SERIAL AT25F=01 DEFAULT,

ROM_TYPE[1:0]

SUB_VENDOR0MIOAD1

MIOB_VSYNC

Serial SST45VF=10, LPC=11
VBIOS on card (pull high)

VBIOS with system BIOS (pull down)

PEX_PLL_TERM MIOAD0

For GDDR1

MIOBD0

RAM_CFG[3:0]

MIOBD1
MIOBD8
MIOBD9

For GDDR3

+3.3V_RUN

12

R198

8
7
6
5

10K_0402_5%~D

R183

U21

1
2
3

12

XIN/CLKIN

XOUT

VSS

VDD

D_C

PD#

ModOUT4REFCLK

P1819GF-08SR_SO8~D

8Mx32 DDR monolithic (64bit)
300MHz, 1.8V

8Mx32 DDR monolithic (32bit)
300MHz, 1.8V

8Mx32 DDR (Samsung K4D55323QF-GC)
300MHz, 1.8V

4Mx32 DDR generic (64bit)

1.8V I/O

4Mx32 DDR generic (32bit)

1.8V I/O

Infineon 16Mx32
500MHz, 1.8V

Hynix 16Mx32
500MHz, 1.8V

Samsung 16Mx32
500MHz, 1.8V

+3VL

12

R199

10K_0402_5%~D

1

C297

2

10U_0805_10V4Z~D

1

C282

2

Value

01

0

0001

1001

0010

0100

1100

0001

0010

0011

L19

BLM18AG121SN1D_0603~D

1 2

0.1U_0402_10V7K~D

*

+3.3V_RUN

S0

-1.75% (DOWN)

A A

±0.875% (CENTER)01

S0 Internal pull up

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

NVG86 Spread Spectrum & Strapping

LA-3302P

57 66Thursday, March 01, 2007

1

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Version Change List ( P. I. R. List )

3

2

1

Item Issue DescriptionDate

D D

38 08/2/2006 Pop R108, depop R106Compal BID change to X01 X011

18 08/10/2006 Compal Change SOT23 package to SOT323 package Change Q102, Q59 to SOT323 package X012

73 08/21/2006 Compal BITS issue WI86517 (S5 state back driver issue) Change R324 pin1 connect from +3.3V_ALW to +3.3V_SUS

HW

HW

HW

Owner

4 41 08/21/2006 Compal Bits issue WI84312 (Derating issue) Change R151 from 30 ohm to 75 ohmHW

235

6

39 08/21/2006 Compal Bits issue WI86511HW Add R401 (100K) for signal BC_DAT pull up to +3.3V_ALW X01

Bits issue WI86509Compal08/21/2006

Populate R761 and change value from 100k to 10k.
Change R761 pin1 connect from +3.3V_ALW to +3.3V_SUS

7 37 08/21/2006 Compal Bits issue WI86512

8 23 HW 08/21/2006 Compal Bits issue WI86516

C C

10

08/21/20069

08/21/2006 Compal Bits issue WI8653238,39 HW

Bits issue WI86518Compal X01HW38,39

R509 PU for SIO_EXT_SMI# change from +3.3V_ALW to
+3.3V_SUS to prevent backdrive through the ICH in S4/S5
Swap PSID GPIO from ECE5018 pin 71 with MEC5025
ITP_DBRESET# pin 55
Swap BEEP (ECE5018 GPIOB[6]) with PLTRST_DELAY#
(MEC5025 SGPIO46)

Bits issue WI86752Compal08/21/2006

12 21 HW X01

08/30/2006 Compal Bits issue WI86530

Bits issue WI86529Compal09/7/2006

14 39 HW

09/7/2006 Compal

Bits issue WI86376. Due to increase in number of
payloads the BIOS is carrying

Move SB_NB_PCIE_RST# to GPIO4/PIRQG# pinF12 per M08
design
Move SB_WLAN_PCIE_RST# to GPIO3/PIRQF# U32 pin G11 per
M08 direction, add test point T1 on pin F18
Change U23 from ( ST M25P80 8M bit ) to ( MXIC
MX25L1605AM2C 16M bit )

09/7/2006 Compal15 54 Bits issue WI87262. Add depopulated soft start capacitor Add C85 (470PF_0402) across R244 X01HW

Change Q5 to MMBT3906WT1G, R15 to 150 ohm. Add R638 on

HW X01

B B

09/11/200616 43 Compal Bits issue WI90535

LED_WLAN_OUT# pull up to +3.3V_WLAN. Add R639 (10K ohm)
in series on LED_WLAN_OUT#

09/14/200617 7 Compal Briscoe ESD/EMI Improvement Requests on PT Remove ITP port and just keep ITP test point HW X01

Solution Description Rev.Page# Title

X01

X01

X01HW

X01Change R131 to no-stuff and from 4.7k to 100k per SMSC HW

X01

X01

X01Change pull-up rail for R773 from +5V_SUS to +3.3V_SUSHW1811

X01HW2113

X01

Request

18 09/14/200634 HW Compal Bits issue WI90713 No stuff C16 X01

19 09/14/200643 HW Compal Bits issue WI90712 Remove R73, R178, C192, and C193 X01

20 43 HW 09/14/2006 Compal Bits issue WI90705

Add SMBus isolation circuit for WLAN,
R640,R645,R660,R662,Q45,Q46

X01

21 34 HW 09/14/2006 Compal Bits issue WI90696 JMINI1 connect to +3.3V_RUN. Removed C427 X01

22 12 HW 09/14/2006 Compal Shunt caps on LVDS for improving WWAN Add C181,C192,C193,C196,C207,C209 cross LVDS signals X01

23 27 HW 09/14/2006 Compal Bits issue WI90516 Remove C759 from mic amp bias circuit X01

24 26 HW 09/14/2006 Compal Bits issue WI90487 Populate R541to cut BEEP level in half X01

A A

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

Changed-List History

LA-3302P

58 66Monday, February 26, 2007

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0.4

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Version Change List ( P. I. R. List )

3

2

1

Item Issue DescriptionDate

D D

29 41 HW 09/14/2006

30 37,39 HW 09/14/2006 X01Compal Bits issue WI89379

18,52 09/14/2006

43 09/14/2006 Compal Bits issue WI89637 Populate EMI Clips Clip1, Clip2, Clip3, Clip4, Clip6 X0126

HW

HW23 09/14/2006 Compal Bits issue WI89409

25 HW 09/14/2006 Compal28 Bits issue WI89407

Owner

Compal Bits issue WI90207 X0125 HW

Compal Bits issue WI89394 X01

Connect THERMTRIP_VGA# from U10 pinB13 to U10 pin A13.
Populate R186 for THERMTRIP_VGA# pull up

No stuff R516, add R690 (8.2K ohm) for pull up ICH8 pin
AF22 to +3.3V_SUS
Add Q68, Q69, R691, R692 for HDDC_EN and MODC_EN
circuits
Change connect R765 pin1, R623 pin1, R621 pin1, R766
pin1, R637 pin1, R300 pin1 from +5V_ALW to +5V_ALW2
Change R387,R389 from 1M to 2.7K. Add R778,R779 for
AUX_ON,AC_OFF

Change R730 from 100K to 4.7K ohm31 39 HW 09/15/2006 X01Compal Bits issue WI92249

32 57 Remove R39HW 09/15/2006 Compal

C C

33 53,55 HW

09/18/2006 Compal Bits issue WI92289 X01

Bits issue WI92188. The MIO_A_D0 signal has an internal
pull-down in the GPU

U10 (NV86) pin F11,F12 connect to test point T89,T90
for testing and debug

34 23 HW 09/18/2006 Compal PLTRST_DELAY# move from ECE5018 GPOB[6] to ICH8 GPIO38 Bits issue WI92296 X01

35 34 Bits issue WI92287,WI90716 R660 and R662 connected to CLK_SCLK and CLK_SDATA. X01HW 09/18/2006 Compal

36

57,37,
22,33,
28,19,
20

Compal09/18/2006

EMI solutions HW

Populate SSCG U21,R189,R198,R199,L19,C297,C282,R166.
depopR165. Populate RS232 C152,153,154,155,156,
157,158,159. Resume ICH_AZ_MDC_BITCLK C656,R123,C128.
Add R790,R791,C232, C267. Change L63,L65 from 0603size
to 0805size. Add C309,C316 for LOM. Add C427,C463 for
LVDS. Add fuse F3, R792 for CRT. Populate C660, R545 (10
ohm),C721 (10P)

37 23,36 HW Bits issue WI92298

38 23 HW

B B

Bits issue WI92299

Move SIO_EXT_SCI# from to ICH8 GPIO11/SMBALERT# pin AG22
to GPO12 pin AC19. Remove D22 and R761 and net DOCK_DET#
ICH8 Pin AG22 tie to LOM_ICH_SMBALERT#. Add R793 (0 ohm)
series on LOM_ICH_SMBALERT# and LOM_SMB_ALERT#. Change
R730 pull up rail from +3.3V_ALW to +3.3V_LAN. Add R807
pull up to +3.3V_SUS for LOM_ICH_SMBALERT#

39

40

41

42

43

44

39 HW Bits issue WI9230109/18/2006 Compal

38,39

39,42 HW 09/18/2006

Compal09/18/2006HW39 Add R795 (10K ohm) pull down for MEC5025 pin 14 X01Bits issue WI92312

Compal29 HW 09/19/2006

27 CompalHW 09/19/2006 Bits issue WI90510 Add R796,R797 (0ohm) between L47/L48 and C728/C730 X01

Move ALW_PWRGD_3V_5V from MEC5025 pin 18 to MEC5025
pin 29. Remove 3.3V_5V_SUS_PWRGD from MEC5025 pin 29
Swap DOCK_SMB_PME and DOCK_SMB_ALERT# from MEC5025 pin3
and ECE5028 pin76
Removed 3.3V_LAN_PWRGD from MEC5025 KSO15/GPIO5.
Remove U52,Q83,D29,R89,R98,R381,C784,C182,C183,C184

Populate R671~R678 and C866~C869. Change L69~L76 from
24NH to 36NH inductor

Solution Description Rev.Page# Title

X0127

X01

X01

X01

X0109/18/2006 Compal

X0109/18/2006 Compal

X01

X01HW 09/18/2006 Compal Bits issue WI92305

X01Compal Bits issue WI92308

X01EMI issue

Request

45

A A

57 HW Compal09/20/2006 EMI request Add R798~R803 for strap damping X01

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

Changed-List History

LA-3302P

59 66Monday, February 26, 2007

1

0.4

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5

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Version Change List ( P. I. R. List )

3

2

1

Item Issue DescriptionDate

D D

48 38 09/20/2006 Compal

49 33 X0109/21/2006 Compal

50 34 09/21/2006 Compal X01

51 Bits issue WI93403 C484 change to 33pF, C861/C862 change to 22pF 6 09/25/2006 Compal X01

18 09/20/2006 Compal46 HW Bits issue WI92860 Depop Q39 and R427 X01

28 09/20/2006 Compal47

HW Bits issue WI92858

HW Bits issue WI92857 Add no-stuff series 0-ohm for ITP_DBRESET# on ECE5028 X01

HW Bits issue WI93157 Remove R586 and make JMDC pin2 NC

HW Bits issue WI93158 Depop Q45, Q46

HW

Owner

Change R669 to from 1.15K to 1.13K. Depop C771 & C772.
Change C861 and C862 to 22pF

No Populate C866-C869/R671-R67852 HW Bits issue DF86424

53

C C

54

55

56

57

58

32 HW Bits issue DF94094 Add FUSE4,FUSE509/27/2006 Compal X01

9 HW Bits issue WI9492309/28/2006 Compal C329,C330 chagne back to 10 0805 X6S X01

18 HW 10/05/2006 Compal Bits issue WI94892 Populate R771, C750, R772, Q102, R773 X01

Bits issue WI95910Compal10/05/2006HW30 X01

38,23
27,6

HW

10/05/2006 Compal Bits issue WI95932

Add D37-D40 for stick point signalsEMI requestHW40 X01Compal09/26/2006

Change R603 from 6.2k to 5.9k.
Change C805 from 820pF to 270pF

No stuff R227, R221, C89, C93, C97, c401, C92, r72, C90,
C94. No stuff C775-C781, C785. No stuff R514 (no iAMT).
Populate R515.

59

36 HW Dell10/14/2006 Bits issue WI97539

Bits issue WI97837Dell10/17/2006HW960

B B

61 X02

23 HW 10/18/2006 Dell

Bits issue WI98222 (Change for ASF2.0 due to ICH8M errata ) 1. No stuff R502, R503

Added signal DOCK_DET# to JDOCKBpin137, pin205 and
Q3pin2
Add 0.1 uf (0402) caps on +Vcc_Core to Gnd. Four
total, bottom of board. (C870 ~ C873)

2. Connect the pad of R503.2 to the pad of R498.2

3. Connect the pad of R502.1 to the pad of R499.2

Board ID Changed to X02Dell10/24/2006HW Populated R106, R107. Depopulated R108, R109.3862

Solution Description Rev.Page# Title

X01

X0129 09/26/2006 Compal

X01

X02

X02

X02

Request

Dell10/24/2006HW The DevID for G86 on Briscoe needs to be updated to 10113862 X02

63 23 HW 11/16/2006 Dell Bits issue WI104573 X02

Bits issue WI98660

Add R816,C874 for USB_IDE#. R817,C875 for SIO_EXT_WAKE#.
R819,C876 for PCIE_MCARD1_DET#. R820,C878 for
USB_MCARD1_DET#. R818,C877 for USB_MCARD2_DET#. Remove
net RSVD_GPIO6 and R513

64 6,23,34

HW 11/16/2006 Dell Bits issue WI103311

Change R309 from 8.2K to 2.2K. No stuff R820.
No stuff R550

X02

65 39 HW 11/18/2006 X02Change C379 from 22pF to 33pF per KDS X'tal reportDell Bits issue WI103986

66 HW Bits issue WI105207 X0325,41 11/20/2006 Compal

A A

Change net name from +5V_ALW2 to +3.3V_ALW2 at R618.1,
R626.1, R623.1, R621.1, R766.1, R765.1, R637.1, R300.

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

Changed-List History

LA-3302P

60 66Monday, February 26, 2007

1

0.4

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Version Change List ( P. I. R. List )

3

2

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Item Issue DescriptionDate

D D

Owner

Dell11/21/2006HW2867 X02Bits issue WI105200

Change L64,L66,L67,L68 from BLM18AG601SN1D to
BK1608LM182. Change R668 to L88 BK1608LM182.Change L63,
L65 from BLM21AG601SN1D to BK2125LM182.

Depop R697,change R286 to 0 ohm.Pop L53,depop L16.Pop
L27,C314,C315.Depop L20,L21,pop L54,L55.Depop L17.
Change R794 pin1 from +5V_ALW to +3.3V_ALW.
Change R245 pin1 from +3.3V_ALW to +5V_ALW
Add 100kohm resistor R721 between U35 pin 40 and
+3.3V_RUN and 1000pF cap C759
Please populate R820 with a 4.7k-ohm resistor. Move
signal PCIE_MCARD2_DET# from ICH8m GPIO20 pinAE11 to

69

Dell11/21/2006HW6,54,57 X02

38,39 HW 11/21/2006 Dell

Bits issue WI10571268

26 HW 11/21/2006 Dell

21,23,34 HW X02

12/1/2006 Dell71 Bits issue WI106999

PIRQH#/GPIO5 pinB3. Delete R457 and net
ICH_GPIO5_PIRQH#. Populate R550

41 HW Populate C208 72 12/1/2006 Dell Bits issue WI107466. +2.5V_LAN in-rush current test fai. X02

73 6 HW 12/5/2006 Change R286 from 0 ohm to 33 ohmsDell Bits issue WI107881 X02

C C

74 27 HW 12/6/2006 Dell Bits issue WI107896 Change R554 from 10K to 0 ohm X02

75 36,38 HW 12/6/2006 Dell Bits issue WI108259. Per M08 GPIO map rev A15 Change list Change net DOCK_SMB_PME to DOCK_SMB_PME# X02

HW

Bits issue WI108223Dell12/6/2006976 X02

Change C177,C179,C178,C366,C338,C365 to
EEFSX0D221E7 220uF

HW Bits issue WI109622. Per NB8M PUN document Change R35 from 60.4 ohm to 40.2 ohm77 52 12/12/2006 Dell X02

HW78 55 12/13/2006 Bits issue WI109627 Change R174 from 40.2 ohm to 30 ohmDell X02

79 HW39 12/14/2006 Dell Bits issue WI110179

HW2780 Bits issue WI110158Dell12/15/2006 X02

81 26 X02

B B

HW 12/18/2006 Dell Bits issue WI110749

82 Bits issue WI111288Dell12/20/2006HW29 X02

83 12/25/2006 Dell Change AC Coupling Cap SPEC for PCIE

12,23
28

HW

84 1/5/2007 Dell54,55 HW Bits issue WI113179

Add EC_FLASH_PAD pin1 connect to +3.3V_ALW,pin2 connect
to R76 pin1 and R80 pin1
Add R822 (1M_0402) from Pin 10 (C1P) pin of MAX9789A
to ground
Add R823 (10K_0402) to ground on pin 47 of STAC9205
(U37)
Change R683 from 150ohms to 110 ohms, R684from
150ohms to 200ohms
Change C500~C531,C664,C666~C670,C851,C853 from 0.1uF Y5V
to 0.1uF X7R
Change R174 to 24.9 ohm for G86, Add R824 40.2 ohm for
G72. Change R35 to 45.3 ohm G86, add R825 60.4 ohm for
G72MV

85 56 HW 1/5/2007 Dell Bits issue WI113180 Add R826,R827 243 ohm for G86 X03

Solution Description Rev.Page# Title

X02Bits issue WI105754

X0270 Bits issue WI105758. Updates for potential Back Drive

X02

X02

X03

Request

86 53,56 HW 1/5/2007 Dell Bits issue WI113227 Add R828,R829,R830,R831,R832 487 ohm for G86 X03

87 38 HW 1/5/2007 Dell Chagne Board ID to X03 Populate R108, de-pop R106 X03

Dell1/8/2007HW688 X03Change U10 value to G86-620-A2. Add R833=147 ohm with

A A

Bits issue WI113588

R697 use 1@ for G72. R286=33 ohm use 2@ for G86.
Change R48 note to "Reserved for GFx debug".

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

Changed-List History

LA-3302P

61 66Monday, February 26, 2007

1

0.4

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5

4

Version Change List ( P. I. R. List )

3

2

1

Item Issue DescriptionDate

D D

89 1/26/2007 Dell Bits issue WI115658. M08 GPIO map rev A16 change X03Change ECE5028 GPIOF4 from BID2 to CHIPSET_ID.38 HW

Owner

90 X0323 2/12/2007 Dell Bits issue WI121957 Add R834 (1M_0402_1%) for ICH_LAN_RST#HW

Bits issue WI121438Dell2/12/20072791 Change R565 from 10K to 100k ohmHW

Bits issue DF11681392 41 2/12/2007 DellHW Depop C194, changed C815 from 4700pF to 2200pF

93 54 2/14/2007 Dell Modify pop option symbol for G72M/G86M power beadHW L53,L27,L55,L54, with 2@, L16,L17,L21, L20, with 1@

94 57 2/14/2007 Dell Modify NV strap tableHW Change GDDR3 table from 500 MHz to 700 MHz

95 18 2/26/2007HW Dell Bits issue WI124164 populate C640 = 10uF for G72MV. Add 1@ for C640

96 54 57 HW 2/26/2007 Dell Bits issue WI124408

C C

Add note "Populate C251, C255 for G86 and G72 solution
per Nvidia". Add 2@ for C314, C315, R805 and R57. Add
1@ for R49.

97 54 HW 2/27/2007 Dell Bits issue WI123608 Change C233 from X5R to X7R

98 23 HW 2/27/2007 Dell Bits issue WI125173. Per Intel's latest recommendation Change R834 from 1M to 10K X03

99 54 HW 2/28/2007 Dell Bits issue WI123608 Change C233 back to X5R X03

100 18 52 HW 2/28/2007 Dell

Bits issue WI124613. Need to connect THERMTRIP_VGA to the
thermal sensor for G86

Add 2@ for R756, R187, Q76, C203 X03

101 18 HW 3/1/2007 Dell Bits issue WI125873. Populate circuit for THERMTRIP_MCH# Populate R427 and Q39 X03

102 27 HW 3/7/2007 Dell Bits issue WI127300 Change U40 from 74AHC1G08 to 74AHCT1G08 X03

Solution Description Rev.Page# Titl e

X03

X03

X03

X03

X03

X03

X03

Request

B B

A A

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

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2

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Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

Changed-List History

LA-3302P

62 66Wednesday, March 07, 2007

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Item Issue DescriptionDate

D D

C C

10

B B

11

12

48/50

1 0.1

2PWR

3PWR

4PWR

5

6

7

8

9

45 change to correct parts for 15ALW

48

44

44 PWR

46

45

47

49

51

47

44

Title

PWR

PWR

PWR

PWR

PWR

PWR

PWR

PWR

9/14

9/14

9/14

9/14

9/14

9/14

9/14

9/14

9/14

9/14

9/14

9/14

Owner

Elick

DELL

DELL

DELL

DELL

DELL

DELL

DELL

DELL

DELL

DELL

DELL

change the AL CAP to 2000hr

change to PSL of DELL

change to PSL of DELL

change to PSL of DELL

BITS-WI89364
The 0.9V_DDR_VTT_PWRGD net is not used at
the MEC5025.
The 0.9V_DDR_VTT_PWRGD net should be no
connect at the MEC5025 pin 73.

BITS-WI91011
change to correct current limits

following DELL rule

BITS-WI91289
be compliant with the reference schematic.

BITS-WI91295
Implement changes to 1.25V_RUN and
GPU Core regulators

BITS-WI91372
following DELL rule

BITS-WI91682
DC IN schematic changes.

change PC380 from SF10004M08L to SF000000S8L.
change PC381 from SF10004M08L to SF000000S8L.
change PC382 from SF10004M08L to SF000000S8L.

change PD55 from SCSB717F08L to SCS00001U8L.
change PD56 from SCSB717F08L to SCS00001U8L.

change PH2 from SL20000030L to SL200000F8L

change PL1 from SM01001680L to SM010008U0L.

change PL2 from SM01001418L to SM010009C8L.
change PL34 from SM01001418L to SM010009C8L.

remove PR437, PR438, PR441, PQ93 and PQ94.

Change PR383 from 124K(SD03412438L) to 150K(SD03415038L).
Change PR382 from 187K(SD03418738L) to 226K(SD03422638L).

Depopulate PR415 and PR416 resistors.BITS-WI91278

Change PR274 from 4.7 ohm(SD000006T8L) to 33 ohm(SD014330A8L).
Populate PR373 and PD54.

Add PC410 10uF, 1206, 25V at the input rail (+PWR_SRC) of
the 1.25V_RUN regulator.
Change PR460 from 0 ohm(SD01300008L) to 1 ohm(SD013100B8L).
Change PR459 from 0 ohm (SD01300008L) to 1 ohm(SD013100B8L).
Change PR449 ground connection from AGND to PGND.

Change PR408 from 75K(SD03475028L) to 82.5K(SD00000278L).

Change PL1 from SM01001680L to SM010008U0L.
Change PQ100 from SI2301BDS(SB923010020) to
PQ100A depopulated IMD2A(SB000009N8L).
Change PQ101 from SI2301BDS(SB923010020) to
PQ100B depopulated IMD2A(SB000009N8L).
Change PR12 from 10K,0603(SD01310028L) to 4.7K,0805(SD00247018L).

Solution Description Rev.Page#

0.1

0.1

0.1

0.1

0.1

0.1

0.1

0.1

0.1

0.1

0.1

Request

13

14

A A

15

45 PWR 9/ 14 DELL BITS-WI90985

45

51

PWR BITS-WI90988

PWR 9/15 DELL

9/14 DELL

following DELL rule

Change PQ83 from FDS8880 to
BSC079N03SG PPAK

BITS-WI92173
correct the current limit on
GPU CORE regulator

Change PC285 pin 2 pad connection
from PGND to AGND.

Change PQ83 from SB000004U8L to SB000004D8L.

Change PR451 from 140K(SD03414038L) to 182K(SD03418238L)

0.1

0.1

0.1

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Changed-List History 1

Size Document Number Rev

Date: Sheet

LA-3302P

1

63 66Monday, February 26, 2007

of

0.6

5

4

Version Change List ( P. I. R. List )

3

2

1

Item Issue DescriptionDate

D D

16 PWR

17

18

19

C C

20

21

22

B B

23

51 9/15 DELL BITS-WI92161

46

46

48

51

51

44

48/50

PWR

PWR

PWR

PWR

PWR

PWR

PWR

9/15 DELL

9/18 DELL

9/18 DELL

9/18 DELL

9/20 El ick change GPU_CORE voltage change PR446 from 10k to 13.7k(SD03413728L) 0.1

9/21 DELL

9/21 DELL

Owner

correct the current limit on

1.25V_RUN regulator.

BITS-WI91932
correct the current limit on

1.8V output

BITS-WI92459
follow BITS of DELL

BITS-WI92462
improve transients at load dump.
and reduce jittering.

BITS-WI87245
PWRGD signals are reversed coming from the
wrong side of the IC.

BITS-WI91682
change PL1 from BK1608HM to BLM18BD102SN1D.

BITS-WI87563
change populate PC380 from 25CE100AX
to 25CE100LS
change PC381 from 25CE100AX to 25CE100LS
change PC382 from 25CE100AX to 25CE100LS

Change PR453 from 140K(SD03414038L) to 205K (SD03420538L) 0.1

Change PR202 from 61.9K(SD03461928L) to 100K (SD03410038L) 0.1

change PR193 to be populate.
change PR506 to be populate.
change PR505 to be depopulate.

Add depopulate PR516(SD03410018L) and depopulate PC413(SE076103K8L)
between pin 9 of PU11 and AGND.
Add depopulated PC411(SE075472K8L),4700pF between pin 14 of PU11 and AGND .
Add depopulated PC412(SE075472K8L),4700pF between pin 15 of PU11 and AGND

Change the node name at pin 13 of PU25 from GFX_CORE_PWRGD to

1.25V_RUN_PWRGD.
Change the node name at pin 28 of PU25 from 1.25V_RUN_PWRGD to
GFX_CORE_PWRGD .
Remove +3.3V_RUN node connected to pin 2 of PR462.
Remove +3.3V_ALW node connected to pin 1 of PR483.
Remove +3.3V_ALW node connected to pin 1 of PR450.
Remove totally PR462 pad, PR483, PR450.

change PL1 from SM010008U0L to SM010007C8L. 0 . 1

change populate PC380 from SF000000S8L to SF000000T8L.
change PC381 from SF000000S8L to SF000000T8L.
change PC382 from SF000000S8L to SF000000T8L.

Solution Description Rev.Page# Titl e

0.1

0.1

0.1

0.1

Request

24

25

26

27

A A

28 48 PWR 10 /27

49

49

49

49

PWR

PWR

PWR

PWR

9/29

9/29

9/29

9/29

DELL

DELL

DELL

DELL

DELL

match Maxim's response time of ICM input
to comparator.

ICM is voltage source and does not
need this component.

Increase BW from 20kHz to 25kHz while
maintaining 80degrees phase margin.

following DELL rule

Add bead to connect +PWR_SRC to
+CPU_PWR_SRC

change PR361 from 0 Ohm (SD02800008L) to 8.45K (SD00000068L).
change PC254 from 0.01uF 25V (SE068103K8L) to 0.1uF 16V (SE076104K8L).

depopulate PR150.

change PR148 from 4.7K (SD03447018L) to 10K (SD03410028L).

depopulate PD54 and PR373

Add PL47(SM01002078L) to parallel PJP30.

0.1

0.1

0.1

0.1

0.2

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Changed-List History 2

Size Document Number Rev

Date: Sheet

LA-3302P

64 66Monday, February 26, 2007

1

of

0.6

5

4

Version Change List ( P. I. R. List )

3

2

1

Item Issue DescriptionDate

D D

C C

34

45,46,
47,51

30 49

31 45

32 49

33 48

51

PWR

PWR

PWR

PWR

PWR

PWR

10/27 DE LL

11/20 DE LL

12/06 DELL

12/06 DELL

01/04 ELICK EMI CLK issue

Owner

DELL10/2729

BITS-WI99895
This is to add an optional ultrasonic mode
in case the regulators experience an
audible noise.

BITS: WI102600
Change PR148 from 10K_0402_1% to 2.2K_0402
_5%

BITS-WI105406
Add node name +3.3V_ALW2 for the trace
connected to the pin 5 (VREF3) of PU20.
Populate PC285 with 0.1uF cap.

BITS-WI106278
make sure that PC113, PC114 and PC379 are
X5R/X7R caps, need to stuff PC379.

BITS-WI108229
Change PC187 from 10nF to 15nF.
Change PR258 from 2.21K to 1.69K.
Populate PR516 with 1K resistor.
Populate C413 with 0.01uF.

Add PR517 0 ohm 0402(SD02800008L) between pin 29 of PU20 and AGND .
Add PR519 0 ohm 0402(SD02800008L) between pin 29 of PU21 and AGND .
Add PR520 0 ohm 0402(SD02800008L) between pin 29 of PU25 and AGND .
Add PR518 0 ohm 0402(SD02800008L) between pin 26 of PU6 and AGND .

change PR148 from 10k 0402 1%(SD03410028L) to 2.2k 0402 5%(SD02822018L) 0 .3

Add node name +3.3V_ALW2 between pin5 of PU20 and PC285.
Populate PC285.

change PC379 is populated. 0.3

change PR187 from 10nF(SE076103K8L) to 15nF(SE076153K8L).
change PR258 from 2.21K(SD03422118L) to 1.69K(SD00000JB8L).
populate PC413.
populate PR516.

Add PL3 to parallel PJP54.
add PC414 to connect between GPU_CORE to GND.
add PC415 to connect between GPU_CORE to GND.

Solution Description Rev.Page# Titl e

0.2

0.3

0.3

0.3

Request

change PR138 from SD021100D8L to SD021100D3L(S RES 1W .01 +-1% 2512

B B

35 49 PWR 01/25 EL ICK change to new part number for PSL

change bead to 9A 1812 in DC-IN.36 44 PWR 01/26 ELICK 0.4

BITS-WI119950

37 45/47/51 PWR 02/05 DE LL

38 49 PWR 02/06 DELL

A A

39 4 9 P WR 02/12 DELL delete 1206 resistor on +VCHGR

Increase current limits for 3.3V, 1.5V
and GPU_CORE regulators.

additional 1206 resistor on +VCHGR for
Maxim solution.

not to implement for Maxim solution.

FOR M08 PROJECTS)
change PR145 from SD021100D8L to SD021100D3L(S RES 1W .01 +-1% 2512
FOR M08 PROJECTS)

change PL2 from SM010009C8L(TAIYO FBMJ4516HS720NT 1806)
to SM01000BI0L(KC FBCA-K5B-302340-L1-T 1812 ).
change PL32 from SM010009C8L(TAIYO FBMJ4516HS720NT 1806)
to SM01000BI0L(KC FBCA-K5B-302340-L1-T 1812 ).

change PR382 from 226K to 267k (SD02822018L).
Change PR408 from 82.5K to 100K(SD03410038L).
Change PR451 from 182K to 205K(SD03420538L) .

add an unpopulation PR522 (1.8K 1206 1%(SD00000JN8L))between
+VCHGR to PGND.

delete an unpopulate PR520 (1.8K 1206 1%(SD00000JN8L))between
+VCHGR to PGND.

0.4

0.4

0.4

0.4

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Changed-List History 2

Size Document Number Rev

Date: Sheet

LA-3302P

65 66Monday, February 26, 2007

1

of

0.6

5

4

Version Change List ( P. I. R. List )

3

2

1

Item Issue DescriptionDate

D D

40 51 PWR 02 /26 DELL

C C

Owner

BITS-WI123151
GPU Core Voltage for G86MV is staying at

1.15V all the time

Nostuff: PR447, PR457, PC370, PR452, PQ98, PR461, PC371, PR458, PQ99,
PR454, PR455.
Change 2@PR449 from 20.5K to 18.7K 0402 1%(SD03418728L )
Add 2@PR522 = 196K, 0402. <-- This would be a 2@ resistor added in
parallel to the existing PR451

Solution Description Rev.Page# Titl e

0.4

Request

B B

A A

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Changed-List History 2

Size Document Number Rev

Date: Sheet

LA-3302P

66 66Thursday, March 01, 2007

1

of

0.6