Compal LA-3301P, Latitude D630 Schematic

A

B

COMPAL CONFIDENTIAL

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E

1 1

PCB NO :
BOM P/N :

2 2

LA-3301P (DA80000771L)
45144631L01

MODEL NAME :

IBQ00

M08 (UMA) Briscoe

uFCPGA Mobile Merom
Intel Crestline + ICH8M

2007-03-07

3 3

REV : 1.0 (A00)

DAZ P/N:DAZZGX0010L

MB PCB

Part Number Description

PCB1

LS-3301P REV1 LED/B
PCB1

4 4

LS-3302P I/O Board

DA80000771L

IBQ00
LS-3301P REV1
LED/B

IBQ00
LS-3302P REV1
IO/B

PCB ZGX LA-3301P
REV1 M/B UMA

BOM NO. 45144631L01
PCB P/N: DA80000771L

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

A

B

C

D

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

Cover Sheet
LA-3301P

158Wednesday, March 07, 2007

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Block Diagram
Compal confidential
Model : IBQ00

FAN

1 1

+FAN1_VOUT

page 18

RGB

DVI

TV

Thermal

GUARDIAN III
EMC4001

+3.3V_SUS

CRT CONN

+5V_RUN

LVDS CONN

on M/B Board

DVI Bridge
SI1362A

page 18

page 20

page 19

page 51

RGB

LVDS
DVO

Pentium-M

Merom -4MB (Socket P)

+1.05V_VCCP
+VCC_CORE

H_A#(3..35) H_D#(0..63)

uFCPGA CPU

478pin

System Bus

FSB 800 MHz

page 7,8,9

INTEL

+1.25V_RUN
+1.5V_RUN
+1.8V_SUS
+1.05V_VCCP
+3.3V_RUN
+1.8V_RUN

Crestline

1299pin BGA

page 10,11,12,13,14,15

Memory BUS
(DDR2)

+1.8V_SUS 533 / 667MHz

USB[4]

CPU ITP Port

+1.05V_VCCP

Smart Card

OZ77CR6

+5V_RUN

page 31

Clock Generator

CK505

+3.3V_RUN

DDRII-DIMM X2

BANK 0, 1, 2, 3, 4 ,5 ,6 ,7 ,8

+0.9V_DDR_VTT
+1.8V_SUS

page6page 7

page 16,17

SLOT

2 2

PCI BUS

DOCKING
PORT

DOCK LPC BUS

PCI_PIRQA#
REQ#0
GNT#0

DOCKING
BUFFER

+5V_RUN

page 36 page 30

USB[8]

page 35

IDSEL:AD17
(PIRQD#,GNT#1,REQ#1)

CardBus

OZ711 LQFP

+3.3V_RUN

USB[6]

PCI Express BUS

Mini Card2

WLAN

3 3

+3.3V_WLAN

Mini Card 1

WWAN

+3.3V_RUN
+1.5V_RUN+1.5V_RUN

page 34page 34

USB[9]

PWR Sequence

page 42

ME & LED

page 43

DC IN

4 4

Battery IN

page 44

page 44

3V / 5V /15V

page 45

1.8V / 0.9V/1.25V

page 46

1.5V / 1.05V

page 47

Vccore

page 48

Charger

page 49

Battery Select

page 50

A

GIGA Enthernet
BCM5755M

+3.3V_LAN
+2.5V_LAN

+1.2V_LAN

RJ45

IO/B

page 28,29

B

+3VRUN 33MHz

IEEE1394

page 30

(+1.5V_RUN 100MHz)

DOCK LPC BUS

COM

+3.3V_SUS

page 37

Bluetooth

+3.3V_RUN

USB[7]

+3.3V_ALW

DMI

+1.5V_RUN
100MHz

+1.25V_RUN
+RTC_CELL
+3.3V_RUN
+3.3V_SUS
+1.5V_RUN
+1.05V_VCCP

+3VRUN
33MHz

SMSC SIO
ECE5028

page 38

ECE1077

+3.3V_ALW

page 37

Int.KBD &
Stick

page 40

Trough Cable

INTEL

ICH8-M

676pin BGA

page 21,22,23,24

page 21,22,23,24

LPC BUS

MEC5025

+RTC_CELL
+3.3V_ALW

page 40

Stick

Touch Pad

+5V_RUN

C

SPI

page 39

page 40

48MHz

SATA

S-HDD

+5V_HDD

SPI

ST M25P16

+3.3V_SUS

+3.3V_RUN

USB[5]

USB[2,3]

USB[0,1] SIDE

Azalia I/F

PATA

page 25 page 25 page 26

page 39

Biometric

page 40

REAR

SC_USB

D Moudle

+5V_MOD

+5V_RUN

D

USB Ports X2

+5V_SUS

page 32

USB Ports X2

+5V_SUS

IO/Board

Azalia Codec

STAC9205

+3.3V_RUN
+VDDA

AMP & INT.
Speaker

page 27 page 27

INT MIC

+VDDA

page 27

DELL CONFIDENTIAL/PROPRIETARY

Title

Size Document Number Rev

Date: Sheet

USB2 : Rear Left as viewed from the back,
USB3 Rear Right as viewed from the back

USB0 : side pair top,
USB1 : side pair bottom

MDC

+3.3V_SUS

page 33

Cable

RJ11

IO/B

HeadPhone
& MIC Jack

+3.3V_RUN

Compal Electronics, Inc.

Block Diagram
LA-3301P

258Wednesday, February 14, 2007

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2

1

POWER STATES

State

D D

S0 (Full ON) / M0

S3 (Suspend to RAM) / M1

S4 (Suspend to DISK) / M1 ON ON ON ONOFF

S5 (SOFT OFF) / M1 ON ON ON ONOFFLOW HIGH LOW HIGHLOW

S3 (Suspend to RAM) / M-OFF

S4 (Suspend to DISK) / M-OFF

S5 (SOFT OFF) / M-OFF

Signal

SLP

SLP

S3#

S4#

HIGH HIGH HIGH

HIGH

LOW HIGH HIGH HIGH ON ON ON ONOFF

LOW HIGH HIGH HIGHLOW

LOW HIGH HIGH HIGH LOW ON ONOFF OFF OFF

LOW LOW LOW LOW ON OFF OFF OFF OFF

LOW LOW LOW LOW LOW ON OFF OFF OFF OFF

SLP
S5#

HIGH

S4
STATE#

SLP
M#

HIGH

HIGH

ALWAYS
PLANE

ON

M
PLANE

ON

SUS

RUN

PLANE

PLANE

ON ON ON

CLOCKS

ICH8-M

USB PORT#

0
1
2
3
4
5
6
7

DESTINATION
Side Top
Side Bottom
Rear Left
Rear Right
Smart Card
Biometric
Card Bus
Bluetooth

C C

B B

PM TABLE

State

S0

S3

S5 S4/AC

S5 S4/AC don't exist

power
plane

+15V_ALW
+5V_ALW
+3.3V_ALW
+3.3V_RTC_LDO

ON

ON

+5V_SUS
+3.3V_SUS
+1.8V_SUS

ON ON

ON

OFF

OFFOFF

+5V_RUN
+3.3V_RUN
+2.5V_RUN
+1.8V_RUN
+1.5V_RUN
+0.9V_DDR_VTT
+VCC_CORE
+1.05V_VCCP
+1.25V_RUN

OFFON

OFF

OFF

ECE 5028

PCI EXPRESS

Lane 1
Lane 2

MINI CARD-1 WWAN
MINI CARD-2 WLAN

8
9
1
2
3
4

DESTINATION

Docking
WWAN
None
None
None
None

PCI TABLE

Lane 3

PCI DEVICE

OZ711

IDSEL

REQ#/GNT#

REQ#1 / GNT#1AD17 PIRQD

PIRQ

Lane 4
Lane 5
Lane 6

A A

AD24 REQ#0 / GNT#0

PIRQADocking

None
None
None
GIGA LAN

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

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2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

Index and Config.

LA-3301P

358Wednesday, February 14, 2007

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RUN_ON

FDS4435

(Q24)

+INV_PWR_SRC

ADAPTER

D D

+15V_ALW

SI4810DY

RUN_ON

SI4810DY

(Q58)

+3.3V_RUN

(Q52)

+5V_RUN

BATTERY

CHARGER

+PWR_SRC

ISL6260
(PU11) (PU22)

RUNPWROK

+VCC_CORE

DDR_ON

+1.8V_SUS

ISL6236

+1.25V_RUN

M_ON

ISL6236
(PU21)

1.05V_RUN_ON

+1.05V_VCCP

1.5V_RUN_ON

+1.5V_RUN

ISL6236
(PU20)

ALWON

ALWON

ENAB_3VLAN

+5V_ALW

+3.3V_ALW

RUN_ON

SI3456BDV

C C

SUS_ON

0.9V_DDR_VTT_ON

RUN_ON

(Q69)

+3.3V_LAN

+5V_SUS

+3.3V_SUS

TPS51100

(PU24)

SI3456BDV

(Q54)

REGCTL_PNP25

B B

BCP69 MMJT9435T1G

(Q70)

SI3456SI3456BDV

HDDC_EN#

+5V_HDD

A A

(Q48)(Q56)

MODC_EN#

+5V_MOD

MAX9789A

(U37)

AUDIO_AVDD_ON

+VDDA

+0.9V_DDR_VTT

+1.8VRUN

+2.5V_LAN +1.2V_LAN

REGCTL_PNP12

(Q71)

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

Power Rail
LA-3301P

458Wednesday, February 14, 2007

1

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5

AJ26

ICH_SMBCLK
ICH_SMBDATA

ICH8-M

D D

AD19

2.2K

2.2K

4

+3.3V_SUS

WWAN

SMBUS Address [TBD]

3

3032

C8C7

Intel LAN

SMBUS Address [TBD]

32 30

2N7002
2N7002

2N7002
2N7002

WLAN_SMBCLK
WLAN_SMBDATA

2.2K

2.2K

2

MEM_SCLK

MEM_SDATA

+3.3V_WLAN

WLAN

2.2K

2.2K

@ 0

+3.3V_RUN

197
195

DIMMA

197
195

DIMMB

CLK_SCLK@ 0

CLK_SDATA

1

SMBUS Address [TBD]

SMBUS Address [TBD]

SMBUS Address [TBD]

8.2K

8.2K

8

LCD_SMBCLK

7

C C

LCD_SMDATA

4.7K

4.7K

100

THRM_SMBCLK

99

THRM_SMBDAT

+3.3V_ALW

+3.3V_ALW

6

5
10
9
12
11

INVERTER
(JLVDS)

Charger

EMC4001

SMBUS Address [TBD]

SMBUS Address [TBD]

SMBUS Address [TBD]

2.2K

SBAT_SMBCLK

10

SBAT_SMBDAT

SIO

9

2.2K

2.2K

111

PBAT_SMBCLK
PBAT_SMBDAT

112

B B

2.2K

+3.3V_ALW

100 ohm
100 ohm

+3.3V_ALW

100 ohm
100 ohm

3

4

3
4

9

10

2'nd
BATTERY

BATTERY
CONN

CHARGER

SMBUS Address [TBD]

SMBUS Address [TBD]

SMBUS Address [TBD]

8.2K

+5V_ALW

6

5

DOCKING

SMBUS Address [TBD]

MEC 5025

6
5

8.2K

DOCK_SMB_CLK
DOCK_SMB_DAT

2.2K

2.2K

CKG_SMBDAT

12

CKG_SMBCLK

13

2N7002
2N7002

+3.3V_RUN

CLK_SDATA

CLK_SCLK

17

16

CLK GEN

SMBUS Address [TBD]

A A

Title

Size Document Number Rev

5

4

3

2

Date: Sheet

Compal Electronics, Inc.

SMBUS TOPOLOGY
LA-3301P

558Wednesday, February 14, 2007

1

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5

Non-iAMT

+3.3V_RUN

R435

@

1 2

0_0402_5%~D

D

CKG_SMBDAT39

D D

+3.3V_RUN

CKG_SMBCLK39

FSC FSB FSA CPU

CLKSEL2 CLKSEL0CLKSEL1

000

00

*

0

11

1

0

1

1

C C

0

1

1

11

1 3

1 3

D

1 2

R440

@

0_0402_5%~D

MHz

266

1

133

0

200

166

00

333

1

100

0

400

200 100 33.3

1

Table : ICS954305AK

CPU_BSEL CPU_BSEL2(FSC) CPU_BSEL1(FSB)

133

166

+3.3V_RUN

R290

B B

10K_0402_5%~D

1 2

PCI_PCM

0

0

S

Q34
2N7002W-7-F_SOT323-3~D

G

2
2

G

Q35

2N7002W-7-F_SOT323-3~D

S

SRC
MHz

100

100

100

100

100

100

100

0

1

R265

PCI
MHz

33.3

33.3

33.3

33.3

33.3

33.3

33.3

12

2.2K_0402_5%~D

12

R266

2.2K_0402_5%~D

CLK_SDATA

CLK_SCLK

Place crystal within
500 mils of CK410

CLK_ICH_48M23

CLK_SMC_48M31
CPU_MCH_BSEL08,10
CPU_MCH_BSEL18,10

CPU_MCH_BSEL28,10

CLK_PCI_TPM28

CLK_PCI_DOCK36

CLK_PCI_PCM30

CLK_PCI_502539

CLK_PCI_501838
CLK_ICH_14M23
CLK_SIO_14M38
MCH_DREFCLK10
MCH_DREFCLK#10

CLK_PWRGD23

CLK_PCI_ICH21

Non-iAMT

+3.3V_RUN

12

R304
10K_0402_5%~D

PCI_ICH

+3.3V_RUN

12

R318
10K_0402_5%~D

A A

@

PCI_LOM

12

R319

10K_0402_5%~D

Non-iAMT

+3.3V_RUN

12

R329

@

10K_0402_5%~D

FSA

12

R391

@

10K_0402_5%~D

0=UMA
1=Disc. GRFX down

5

PGMODE

ITP_EN

*

*

FCTSEL1 PIN43 PIN44 PIN47 PIN48

0=UMA

*

1=DIS

PIN 9

0

VTT_PWRGD#/PD

1

CKPWRGD/PD#

PIN 37

0

Pin 5/6 as SRC_10

1

Pin 5/6 as CPU_ITP

PIN 32

TME

0

Normal Operation

1

Trusted Mode Enabled

DOT96T DOT96C 96/100M_T 96/100M_C

27M_out 27M SSout SRCT0 SRCC0

27P_0402_50V8J~D

4

+CK_VDD_48

1

C99

2

4.7U_0603_6.3V4Z~D

1

C708

2

3.3P_0402_50V8C~D

C483

C484

33P_0402_50V8J~D

CLK_ICH_48M
CLK_SMC_48M

CLK_PCI_TPM
CLK_PCI_DOCK

CLK_PCI_PCM
CLK_PCI_5025

CLK_PCI_5018
CLK_ICH_14M
CLK_SIO_14M
MCH_DREFCLK
MCH_DREFCLK#

4

1 2

L28

BLM21PG600SN1D_0805~D

1

C471

2

0.1U_0402_16V4Z~D

1

C799

2

0.047U_0402_16V4Z~D

X1

14.31818MHz_20P_1BX14318CC1A~D

12

12

12

CLK_PCI_ICH

CLK_PWRGD

+3.3V_RUN

1 2

L87

BLM21PG600SN1D_0805~D

+CK_VDD_REF

1

C189

2

CLK_SMC_48MCLK_ICH_48M

1

C774

2

3.3P_0402_50V8C~D

0_0402_5%~D

1 2

R273 15_0402_5%~D

1 2

R275 15_0402_5%~D

1 2

R309 2.2K_0402_5%~D

1 2

R314 8.2K_0402_5%~D

R277 33_0402_5%~D
R596 33_0402_5%~D

R280 33_0402_5%~D
R282 15_0402_5%~D

1 2

R333 15_0402_5%~D

1 2

R284 15_0402_5%~D

1 2

R285 15_0402_5%~D

1 2

R286 33_0402_5%~D

1 2

R287 33_0402_5%~D

R291 33_0402_5%~D

R295

@

10K_0402_5%~D

1 2

R298

@

1 2

10K_0402_5%~D

CLK_SDATA34

Non-iAMT

+CK_VDD_MAIN2

0.047U_0402_16V7K~D

R271

12

12
12

12
12

12

CLK_SCLK34

R760

1 2
1 2

R758 2.2_0603_5%~D

+CK_VDD_MAIN+3.3V_RUN

1_0603_5%~D

3

+CK_VDD_MAIN

1

1

1

1

C475

C474

C473

C472

2

2

1

2

+CK_VDD_REF
+CK_VDD_48

CLK_XTAL_IN

CLK_XTAL_OUT

FSA

FSC

PCI_LOM
PCI_DOCK
PCI_PCM
PCI_SIO

CLKREF

DOT96
DOT96#

PCI_ICH

PGMODE

CLK_SCLK

CLK_SDATA

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

10U_0805_10V4Z~D

1

C480

2

10U_0805_10V4Z~D

R759

1 2

2.2_0603_5%~D

U28

1

VDD_SRC

49

VDD_SRC

54

VDD_SRC

65

VDD_SRC

30

VDD_PCI

36

VDD_PCI

12

VDD_CPU

18

VDD_REF

40

VDD_48

20

XTAL_IN

19

XTAL_OUT

41

USB_48MHz/FSLA

45

FSL_B/TEST_MODE

23

REF_0/FSL_C/TEST_SEL

34

PCICLK4/FCT_SEL

33

PCICLK3

32

PCICLK2/TME

27

PCICLK1

22

REF_1

43

DOT_96/27M

44

DOT_96#/27M_SS

37

PCICLK_F0/ITP_EN

39

CKPWRGD/PD#

9

PGMODE

16

SMBCLK

17

SMBDAT

4

VSS_SRC

15

VSS_CPU

21

VSS_REF

31

VSS_PCI

35

VSS_PCI

42

VSS_48

68

VSS_SRC

73

THRM_PAD

74

THRM_PAD

75

THRM_PAD

76

THRM_PAD

0.1U_0402_16V4Z~D

C481

0.1U_0402_16V4Z~D

2

2

1

2

0.1U_0402_16V4Z~D

C482

0.1U_0402_16V4Z~D

SLG8LP550

CPU_ITP/SRC_10

CPU_ITP#/SRC_10#

LCD_CLK/SRC_0

LCD_CLK#/SRC_0#

SLG8LP550_QFN72~D

0.1U_0402_16V4Z~D

+CK_VDD_A

PCI_STP#

CPU_STP#

CLKREQ_9#

CLKREQ_8#

CLKREQ_7#

CLKREQ_6#

CLKREQ_5#

CLKREQ_4#

CLKREQ_3#

CLKREQ_2#

SRC_1/SATA

SRC_1#/SATA#

CLKREQ_1#

1

2

VDD_A
VSS_A

CPU_1

CPU_1#

CPU_0

CPU_0#

SRC_9

SRC_9#

SRC_8

SRC_8#

SRC_7

SRC_7#

SRC_6

SRC_6#

SRC_5

SRC_5#

SRC_4

SRC_4#

SRC_3

SRC_3#

SRC_2

SRC_2#

1

C477

C476

2

0.1U_0402_16V4Z~D

7
8

H_STP_PCI#

25

H_STP_CPU#

24

MCH_BCLK

11

MCH_BCLK#

10

CPU_BCLK

14

CPU_BCLK#

13

CPU_ITP

6

CPU_ITP#

5

PCIE_MINI1

3

PCIE_MINI1#

2
72

PCIE_MINI2

70

PCIE_MINI2#

69
71

PCIE_ICH

66

PCIE_ICH#

67
38

PCIE_LOM

63

PCIE_LOM#

64
62
60
61
29
58
59
57

MCH_3GPLL

55
56
28
52
53
26

PCIE_SATA CLK_PCIE_SATA

50

PCIE_SATA#

51
46

DOT96_SSC

47

DOT96_SSC#

48

2

0.1U_0402_16V4Z~D

1

C478

2

R267 33_0402_5%~D
R268 33_0402_5%~D

R269 33_0402_5%~D
R270 33_0402_5%~D

R272 33_0402_5%~D
R274 33_0402_5%~D

R311 33_0402_5%~D
R313 33_0402_5%~D

R306 33_0402_5%~D
R307 33_0402_5%~D

R288 33_0402_5%~D
R289 33_0402_5%~D

R299 33_0402_5%~D
R168 33_0402_5%~D

R293 33_0402_5%~D
R294 33_0402_5%~D
R419 475_0402_1%~D

R279 33_0402_5%~D
R281 33_0402_5%~D

R316 33_0402_5%~D
R317 33_0402_5%~D

2

1

2

4.7U_0603_6.3V4Z~D

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2
1 2

1 2
1 2

1 2
1 2

C479

0.047U_0402_16V4Z~D

1

+3.3V_RUN

MINI1CLK_REQ#
MINI2CLK_REQ#
CLK_3GPLLREQ#
SATA_CLKREQ#
LOM_CLKREQ#

CLK_MCH_BCLK
CLK_MCH_BCLK#

CLK_CPU_BCLK
CLK_CPU_BCLK#

CLK_CPU_ITP
CLK_CPU_ITP#

CLK_PCIE_MINI1
CLK_PCIE_MINI1#

CLK_PCIE_MINI2
CLK_PCIE_MINI2#

CLK_PCIE_ICH
CLK_PCIE_ICH#

CLK_PCIE_LOM
CLK_PCIE_LOM#

CLK_MCH_3GPLL
CLK_MCH_3GPLL#MCH_3GPLL#

CLK_PCIE_SATA#

1 2

R315 10K_0402_5%~D

1 2

R310 10K_0402_5%~D

1 2

R297 10K_0402_5%~D

1 2

R283 10K_0402_5%~D

1 2

R301 10K_0402_5%~D

H_STP_PCI# 23

H_STP_CPU# 23

CLK_MCH_BCLK 10
CLK_MCH_BCLK# 10

CLK_CPU_BCLK 7
CLK_CPU_BCLK# 7

CLK_CPU_ITP 7
CLK_CPU_ITP# 7

CLK_PCIE_MINI1 34

CLK_PCIE_MINI1# 34

MINI1CLK_REQ# 34

CLK_PCIE_MINI2 34
CLK_PCIE_MINI2# 34

MINI2CLK_REQ# 34

CLK_PCIE_ICH 23
CLK_PCIE_ICH# 23

CLK_PCIE_LOM 28

CLK_PCIE_LOM# 28
LOM_CLKREQ# 28

CLK_MCH_3GPLL 10

CLK_MCH_3GPLL# 10

CLK_3GPLLREQ# 10

CLK_PCIE_SATA 22

CLK_PCIE_SATA# 22

SATA_CLKREQ# 23
DREF_SSCLK 10
DREF_SSCLK# 10

CLK_ICH_14M

1

2

CLK_SIO_14M

1

2

CLK_PCI_TPM

1

2

CLK_PCI_DOCK

1

2

CLK_PCI_PCM

1

2

CLK_PCI_5025

1

2

CLK_PCI_5018

1

2

CLK_PCI_ICH

1

2

DELL CONFIDENTIAL/PROPRIETARY

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

Clock Generator
LA-3301P

1

C775

3.3P_0402_50V8C~D

@

C776

3.3P_0402_50V8C~D

@

C777

3.3P_0402_50V8C~D

@

C778

3.3P_0402_50V8C~D

@

C779

3.3P_0402_50V8C~D

@

C780

3.3P_0402_50V8C~D

@

C781

3.3P_0402_50V8C~D

@

C785

3.3P_0402_50V8C~D

@

658Monday, February 26, 2007

of

1.0

5

4

3

2

1

H_A#[3..35]10

D D

H_ADSTB#010

H_REQ#010
H_REQ#110
H_REQ#210
H_REQ#310
H_REQ#410

C C

H_ADSTB#110

H_A20M#22

H_FERR#22

H_IGNNE#22
H_STPCLK#22

H_INTR22
H_NMI22
H_SMI#22

B B

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_ADSTB#0

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35
H_ADSTB#1

H_A20M#
H_FERR#
H_IGNNE#

H_STPCLK#
H_INTR
H_NMI
H_SMI#

JCPUA

J4

A[3]#

L5

A[4]#

L4

A[5]#

K5

A[6]#

M3

A[7]#

N2

A[8]#

J1

A[9]#

N3

A[10]#

P5

A[11]#

P2

A[12]#

L2

A[13]#

P4

A[14]#

P1

A[15]#

R1

A[16]#

M1

ADSTB[0]#

K3

REQ[0]#

H2

REQ[1]#

K2

REQ[2]#

J3

REQ[3]#

L1

REQ[4]#

Y2

A[17]#

U5

A[18]#

R3

A[19]#

W6

A[20]#

U4

A[21]#

Y5

A[22]#

U1

A[23]#

R4

A[24]#

T5

A[25]#

T3

A[26]#

W2

A[27]#

W5

A[28]#

Y4

A[29]#

U2

A[30]#

V4

A[31]#

W3

A[32]#

AA4

A[33]#

AB2

A[34]#

AA3

A[35]#

V1

ADSTB[1]#

A6

A20M#

A5

FERR#

C4

IGNNE#

D5

STPCLK#

C6

LINT0

B4

LINT1

A3

SMI#

M4

RSVD[01]

N5

RSVD[02]

T2

RSVD[03]

V3

RSVD[04]

B2

RSVD[05]

C3

RSVD[06]

D2

RSVD[07]

D22

RSVD[08]

D3

RSVD[09]

F6

RSVD[10]

TYCO_1-1674770-2_Merom~D

ADDR GROUP 0

ADDR GROUP 1

ICH

+1.05V_VCCP

DEFER#

DRDY#
DBSY#

LOCK#

RESET#

CONTROLXDP/ITP SIGNALS

RS[0]#
RS[1]#
RS[2]#
TRDY#

BPM[0]#
BPM[1]#
BPM[2]#
BPM[3]#

PRDY#
PREQ#

TRST#

THERMAL

PROCHOT#

THERMDA
THERMDC

THERMTRIP#

H CLK

BCLK[0]
BCLK[1]

RESERVED

ADS#
BNR#
BPRI#

BR0#

IERR#

INIT#

HIT#

HITM#

TCK

TDI
TDO
TMS

DBR#

R327

56_0402_5%~D

1 2

H1
E2
G5

H5
F21
E1

F1
D20

B3
H4
C1

F3
F4
G3
G2

G6
E4

AD4
AD3
AD1
AC4
AC2
AC1
AC5
AA6
AB3
AB5
AB6
C20

D21
A24
B25

C7

A22
A21

H_ADS#
H_BNR#
H_BPRI#

H_DEFER#
H_DRDY#
H_DBSY#

H_BR0#
H_IERR#

H_INIT#
H_LOCK#
H_RESET#

H_RS#0
H_RS#1
H_RS#2
H_TRDY#

H_HIT#
H_HITM#

ITP_BPM#0
ITP_BPM#1
ITP_BPM#2
ITP_BPM#3
ITP_BPM#4
ITP_BPM#5
ITP_TCK
ITP_TDI
ITP_TDO
ITP_TMS
ITP_TRST#

ITP_DBRESET#

H_THERMTRIP#
CLK_CPU_BCLK

CLK_CPU_BCLK#

H_THERMTRIP#

H_INIT# 22

H_LOCK# 10

H_RESET# 10
H_RS#0 10
H_RS#1 10
H_RS#2 10
H_TRDY# 10

T47 PAD~D
T48 PAD~D
T49 PAD~D
T50 PAD~D
T51 PAD~D
T52 PAD~D

ITP_DBRESET# 23,38

EC_CPU_PROCHOT#
H_THERMDA

H_THERMDC

1

2

H_ADS# 10

H_BNR# 10
H_BPRI# 10

H_DEFER# 10
H_DRDY# 10

H_DBSY# 10

H_BR0# 10

H_HIT# 10

H_HITM# 10

C417
2200P_0402_50V7K~D

H_THERMTRIP# 18

CLK_CPU_BCLK 6

CLK_CPU_BCLK# 6

R320

12

56_0402_5%~D

+1.05V_VCCP

H_RESET#

+1.05V_VCCP

12

R323
56_0402_5%~D

EC_CPU_PROCHOT# 39

H_THERMDA 18

H_THERMDC 18

H_THERMDA, H_THERMDC routing together,
Trace width / Spacing = 10 / 10 mil

R321

22.6_0402_1%~D

1 2

CLK_CPU_ITP6
CLK_CPU_ITP#6

+1.05V_VCCP

ITP_DBRESET#

CLK_CPU_ITP
CLK_CPU_ITP#

+1.05V_VCCP

+3.3V_SUS

+1.05V_VCCP

@

0.1U_0402_16V4Z~D

1

1

C486

C485

2

2

Place near JITP

R324

150_0402_5%~D

1 2

R325

51_0402_5%~D

R326

51_0402_1%~D

R328

39_0402_1%~D

R330

150_0402_5%~D

This shall place near CPU

R331

649_0402_1%~D

1 2

R332

27_0402_1%~D

JITP

28

VTT1

27

VTT0

26

VTAP

25

DBR#

24

DBA#

23

BPM0#

22

GND5

21

BPM1#

20

GND4

19

BPM2#

18

GND3

17

BPM3#

16

GND2

15

BPM4#

14

GND1

13

BPM5#

12

RESET#

11

FBO

10

GND0

9

BCLKP

8

BCLKN

7

TDO

6

NC2

5

TCK

4

NC1

3

TRST#

2

TMS

1

TDI

@

0.1U_0402_16V4Z~D

ITP_DBRESET#

ITP_TDO

H_RESET#

ITP_TMS

ITP_TDI

ITP_TRST#

ITP_TCK

29

30

GND6

GND7

JCPUD

A4

VSS[001]

A8

VSS[002]

A11

VSS[003]

A14

VSS[004]

A16

VSS[005]

A19

VSS[006]

A23

VSS[007]

AF2

VSS[008]

B6

VSS[009]

B8

VSS[010]

B11

VSS[011]

B13

VSS[012]

B16

VSS[013]

B19

VSS[014]

B21

VSS[015]

B24

VSS[016]

C5

VSS[017]

C8

VSS[018]

C11

VSS[019]

C14

VSS[020]

C16

VSS[021]

C19

VSS[022]

C2

VSS[023]

C22

VSS[024]

C25

VSS[025]

D1

MOLEX_52435-2891_28P~D@

VSS[026]

D4

VSS[027]

D8

VSS[028]

D11

VSS[029]

D13

VSS[030]

D16

VSS[031]

D19

VSS[032]

D23

VSS[033]

D26

VSS[034]

E3

VSS[035]

E6

VSS[036]

E8

VSS[037]

E11

VSS[038]

E14

VSS[039]

E16

VSS[040]

E19

VSS[041]

E21

VSS[042]

E24

VSS[043]

F5

VSS[044]

F8

VSS[045]

F11

VSS[046]

F13

VSS[047]

F16

VSS[048]

F19

VSS[049]

F2

VSS[050]

F22

VSS[051]

F25

VSS[052]

G4

VSS[053]

G1

VSS[054]

G23

VSS[055]

G26

VSS[056]

H3

VSS[057]

H6

VSS[058]

H21

VSS[059]

H24

VSS[060]

J2

VSS[061]

J5

VSS[062]

J22

VSS[063]

J25

VSS[064]

K1

VSS[065]

K4

VSS[066]

K23

VSS[067]

K26

VSS[068]

L3

VSS[069]

L6

VSS[070]

L21

VSS[071]

L24

VSS[072]

M2

VSS[073]

M5

VSS[074]

M22

VSS[075]

M25

VSS[076]

N1

VSS[077]

N4

VSS[078]

N23

VSS[079]

N26

VSS[080]

P3

VSS[081]

TYCO_1-1674770-2_Merom~D

VSS[082]
VSS[083]
VSS[084]
VSS[085]
VSS[086]
VSS[087]
VSS[088]
VSS[089]
VSS[090]
VSS[091]
VSS[092]
VSS[093]
VSS[094]
VSS[095]
VSS[096]
VSS[097]
VSS[098]
VSS[099]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
VSS[159]
VSS[160]
VSS[161]
VSS[162]
VSS[163]

P6
P21
P24
R2
R5
R22
R25
T1
T4
T23
T26
U3
U6
U21
U24
V2
V5
V22
V25
W1
W4
W23
W26
Y3
Y6
Y21
Y24
AA2
AA5
AA8
AA11
AA14
AA16
AA19
AA22
AA25
AB1
AB4
AB8
AB11
AB13
AB16
AB19
AB23
AB26
AC3
AC6
AC8
AC11
AC14
AC16
AC19
AC21
AC24
AD2
AD5
AD8
AD11
AD13
AD16
AD19
AD22
AD25
AE1
AE4
AE8
AE11
AE14
AE16
AE19
AE23
AE26
A2
AF6
AF8
AF11
AF13
AF16
AF19
AF21
A25
AF25

A A

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

Merom Processor(1/2)

LA-3301P

758Monday, February 26, 2007

1

1.0

of

5

4

3

2

1

+VCC_CORE +VCC_CORE

D D

C C

B B

R335

@

1K_0402_5%~D

A A

H_D#[0..63]10

H_DSTBN#010
H_DSTBP#010

H_DINV#010

H_DSTBN#110
H_DSTBP#110

H_DINV#110

V_CPU_GTLREF

CPU_MCH_BSEL06,10
CPU_MCH_BSEL16,10
CPU_MCH_BSEL26,10

2

R336

@

1 2

1 2

1K_0402_5%~D

Place C close to the
CPU_TEST4 pin. Make sure
CPU_TEST4 routing is
reference to GND and away
from other noisy signal.

R394

C490

@

@

1

0_0402_5%~D

0.1U_0402_16V4Z~D

5

H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_DSTBN#0
H_DSTBP#0
H_DINV#0

H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_DSTBN#1
H_DSTBP#1
H_DINV#1

TEST1
TEST3

TEST4
TEST5
TEST6

CPU_MCH_BSEL0
CPU_MCH_BSEL1
CPU_MCH_BSEL2

TEST1
TEST2
TEST4
TEST6 TEST3

1 2

E22
F24
E26
G22
F23
G25
E25
E23
K24
G24

J24

J23
H22
F26
K22
H23

J26
H26
H25

N22
K25
P26
R23

L23
M24

L22
M23
P25
P23
P22
T24
R24

L25
T25
N25

L26
M26
N24

AD26

C23
D25
C24

AF26

AF1
A26

B22
B23
C21

T30PAD~D
T31PAD~D

For the purpose of testability, route these signals
through a ground referenced Z0 = 55ohm trace that
ends in a via that is near a GND via and is
accessible through an oscilloscope connection.

FSB

BCLK BSEL2 BSEL1 BSEL0

533

133

667

166

800

200

JCPUB

D[0]#
D[1]#
D[2]#
D[3]#
D[4]#

DATA GRP 0 DATA GRP 1

D[5]#
D[6]#
D[7]#
D[8]#
D[9]#
D[10]#
D[11]#
D[12]#
D[13]#
D[14]#
D[15]#
DSTBN[0]#
DSTBP[0]#
DINV[0]#

D[16]#
D[17]#
D[18]#
D[19]#
D[20]#
D[21]#
D[22]#
D[23]#
D[24]#
D[25]#
D[26]#
D[27]#
D[28]#
D[29]#
D[30]#
D[31]#
DSTBN[1]#
DSTBP[1]#
DINV[1]#

GTLREF
TSET1

TEST2
TEST3
TEST4
TEST5
TEST6

BSEL[0]
BSEL[1]
BSEL[2]

TEST5

DATA GRP 2DATA GRP 3

DSTBN[2]#
DSTBP[2]#

DINV[2]#

DSTBN[3]#
DSTBP[3]#

DINV[3]#

COMP[0]

MISC

COMP[1]
COMP[2]
COMP[3]

DPRSTP#

DPSLP#
DPWR#

PWRGOOD

TYCO_1-1674770-2_Merom~D

001

100

D[32]#
D[33]#
D[34]#
D[35]#
D[36]#
D[37]#
D[38]#
D[39]#
D[40]#
D[41]#
D[42]#
D[43]#
D[44]#
D[45]#
D[46]#
D[47]#

D[48]#
D[49]#
D[50]#
D[51]#
D[52]#
D[53]#
D[54]#
D[55]#
D[56]#
D[57]#
D[58]#
D[59]#
D[60]#
D[61]#
D[62]#
D[63]#

SLP#

PSI#

4

H_D#32

Y22

H_D#33

AB24

H_D#34

V24

H_D#35

V26

H_D#36

V23

H_D#37

T22

H_D#38

U25

H_D#39

U23

H_D#40

Y25

H_D#41

W22

H_D#42

Y23

H_D#43

W24

H_D#44

W25

H_D#45

AA23

H_D#46

AA24

H_D#47

AB25

H_DSTBN#2

Y26

H_DSTBP#2

AA26

H_DINV#2

U22

H_D#48

AE24

H_D#49

AD24

H_D#50

AA21

H_D#51

AB22

H_D#52

AB21

H_D#53

AC26

H_D#54

AD20

H_D#55

AE22

H_D#56

AF23

H_D#57

AC25

H_D#58

AE21

H_D#59

AD21

H_D#60

AC22

H_D#61

AD23

H_D#62

AF22

H_D#63

AC23

H_DSTBN#3

AE25

H_DSTBP#3

AF24

H_DINV#3

AC20

COMP0

R26

COMP1

U26

COMP2

AA1

COMP3

Y1

H_DPRSTP#

E5

H_DPSLP#

B5

H_DPWR#

D24

H_PWRGOOD

D6

H_CPUSLP#

D7

H_PSI#

AE6

110

+1.05V_VCCP

V_CPU_GTLREF

Layout close CPU PIN AD26
55 ohm, 0.5 inch (max)

H_DSTBN#2 10
H_DSTBP#2 10

H_DINV#2 10

H_DSTBN#3 10
H_DSTBP#3 10

H_DINV#3 10

H_DPRSTP# 10,22,48

H_DPSLP# 22

H_DPWR# 10

H_PWRGOOD 22

H_CPUSLP# 10

H_PSI# 48

12

R341
1K_0402_1%~D

12

R344
2K_0402_1%~D

54.9_0402_1%~D

12

R337

R338

Resistor placed within 0.5" of
CPU pin.Trace should be at least
25 mils away from any other
toggling signal. COMP0, COMP2
trace should be 27.4 ohm.
COMP1, COMP3 should be 55
ohm.

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

54.9_0402_1%~D

27.4_0402_1%~D

12

R339

27.4_0402_1%~D

12

12

R340

JCPUC

A7

VCC[001]

A9

VCC[002]

A10

VCC[003]

A12

VCC[004]

A13

VCC[005]

A15

VCC[006]

A17

VCC[007]

A18

VCC[008]

A20

VCC[009]

B7

VCC[010]

B9

VCC[011]

B10

VCC[012]

B12

VCC[013]

B14

VCC[014]

B15

VCC[015]

B17

VCC[016]

B18

VCC[017]

B20

VCC[018]

C9

VCC[019]

C10

VCC[020]

C12

VCC[021]

C13

VCC[022]

C15

VCC[023]

C17

VCC[024]

C18

VCC[025]

D9

VCC[026]

D10

VCC[027]

D12

VCC[028]

D14

VCC[029]

D15

VCC[030]

D17

VCC[031]

D18

VCC[032]

E7

VCC[033]

E9

VCC[034]

E10

VCC[035]

E12

VCC[036]

E13

VCC[037]

E15

VCC[038]

E17

VCC[039]

E18

VCC[040]

E20

VCC[041]

F7

VCC[042]

F9

VCC[043]

F10

VCC[044]

F12

VCC[045]

F14

VCC[046]

F15

VCC[047]

F17

VCC[048]

F18

VCC[049]

F20

VCC[050]

AA7

VCC[051]

AA9

VCC[052]

AA10

VCC[053]

AA12

VCC[054]

AA13

VCC[055]

AA15

VCC[056]

AA17

VCC[057]

AA18

VCC[058]

AA20

VCC[059]

AB9

VCC[060]

AC10

VCC[061]

AB10

VCC[062]

AB12

VCC[063]

AB14

VCC[064]

AB15

VCC[065]

AB17

VCC[066]

AB18

VCC[067]

TYCO_1-1674770-2_Merom~D

2

AB20

VCC[068]

AB7

VCC[069]

AC7

VCC[070]

AC9

VCC[071]

AC12

VCC[072]

AC13

VCC[073]

AC15

VCC[074]

AC17

VCC[075]

AC18

VCC[076]

AD7

VCC[077]

AD9

VCC[078]

AD10

VCC[079]

AD12

VCC[080]

AD14

VCC[081]

AD15

VCC[082]

AD17

VCC[083]

AD18

VCC[084]

AE9

VCC[085]

AE10

VCC[086]

AE12

VCC[087]

AE13

VCC[088]

AE15

VCC[089]

AE17

VCC[090]

AE18

VCC[091]

AE20

VCC[092]

AF9

VCC[093]

AF10

VCC[094]

AF12

VCC[095]

AF14

VCC[096]

AF15

VCC[097]

AF17

VCC[098]

AF18

VCC[099]

AF20

VCC[100]

G21

VCCP[01]
VCCP[02]
VCCP[03]
VCCP[04]
VCCP[05]
VCCP[06]
VCCP[07]
VCCP[08]
VCCP[09]
VCCP[10]
VCCP[11]
VCCP[12]
VCCP[13]
VCCP[14]
VCCP[15]
VCCP[16]

VCCA[1]
VCCA[2]

VID[0]
VID[1]
VID[2]
VID[3]
VID[4]
VID[5]
VID[6]

VCCSENSE

VSSSENSE

V6
J6
K6
M6
J21
K21
M21
N21
N6
R21
R6
T21
T6
V21
W21

B26
C26

AD6
AF5
AE5
AF4
AE3
AF3
AE2

AF7

AE7

VCCSENSE

VSSSENSE

VID0
VID1
VID2
VID3
VID4
VID5TEST2
VID6

220U_D2_4VY_R15M~D

1

+

2

C487

VID0 48
VID1 48
VID2 48
VID3 48
VID4 48
VID5 48
VID6 48

VCCSENSE 48

VSSSENSE 48

Length mat c h within 25 mils Z0=27.4 ohm

Place R342 and R343 near CPU

+VCC_CORE

Route VCCSENSE and VSSSENSE trace at

27.4 ohms, 7 mils spaci n g and 1 inch (max)

R342

1 2

100_0402_1%~D

R343

1 2

100_0402_1%~D

VCCSENSE

VSSSENSE

DELL CONFIDENTIAL/PROPRIETARY

Title

Size Document Number Rev

Date: Sheet

+1.05V_VCCP

CRB was 270uF

0.01U_0402_16V7K~D

10U_0805_10V4Z~D

C488

C489

1

1

2

2

Compal Electronics, Inc.

Merom Processor(2/2)
LA-3301P

1

+1.5V_RUN

858Monday, February 26, 2007

1.0

of

5

+VCC_CORE

Place these inside
socket cavity on L8
(North side
Secondary)

D D

Place these inside
socket cavity on L8
(Sorth side
Secondary)

Place these inside
socket cavity on L8
(North side
Primary)

Place these inside
socket cavity on L8
(Sorth side
Primary)

C C

1

2

+VCC_CORE

1

2

+VCC_CORE

1

2

+VCC_CORE

1

2

C329
10U_0805_4VAM~D

C222
10U_0805_4VAM~D

C363
10U_0805_4VAM~D

C364
10U_0805_4VAM~D

1

C330
10U_0805_4VAM~D

2

1

C223
10U_0805_4VAM~D

2

1

C64
10U_0805_4VAM~D

2

1

C50
10U_0805_4VAM~D

2

1

C331
10U_0805_4VAM~D

2

1

C224
10U_0805_4VAM~D

2

1

C65
10U_0805_4VAM~D

2

1

C51
10U_0805_4VAM~D

2

1

C332
10U_0805_4VAM~D

2

1

C225
10U_0805_4VAM~D

2

1

C66
10U_0805_4VAM~D

2

1

C52
10U_0805_4VAM~D

2

4

1

2

1

2

1

2

1

2

C333
10U_0805_4VAM~D

C227
10U_0805_4VAM~D

C67
10U_0805_4VAM~D

C53
10U_0805_4VAM~D

1

C334
10U_0805_4VAM~D

2

1

C226
10U_0805_4VAM~D

2

1

C68
10U_0805_4VAM~D

2

1

C54
10U_0805_4VAM~D

2

1

C335
10U_0805_4VAM~D

2

1

C228
10U_0805_4VAM~D

2

10uF 0805 X6S -> 85 degree C

3

1

C336
10U_0805_4VAM~D

2

1

C229
10U_0805_4VAM~D

2

1

C55
10U_0805_4VAM~D

2

1

C69
10U_0805_4VAM~D

2

1

C190
10U_0805_4VAM~D

2

1

C185
10U_0805_4VAM~D

2

2

1

High Frequence Decoupling

Near VCORE regulator.

+VCC_CORE

+VCC_CORE

1

C870

0.1U_0402_10V7K~D

2

@

BITs WI97840

1

+

C365

2

1

C293

0.1U_0402_10V7K~D

2

North Side Secondary

1

+

2

220U_X_2VM_R7M~D

1

2

C250

0.1U_0402_10V7K~D

ESR <= 1.5m ohm
Capacitor > 1980uF

1

C310

0.1U_0402_10V7K~D

2

1

C264

0.1U_0402_10V7K~D

2

Place these inside
socket cavity on L8
(North side
Secondary)

South Side Secondary

C177

B B

A A

220U_X_2VM_R7M~D

1

+

2

+1.05V_VCCP

1

2

1

+

C178

C179

2

@

220U_X_2VM_R7M~D

C312

0.1U_0402_10V7K~D

220U_X_2VM_R7M~D

1

+

2

1

2

1

+

C338

C366

2

@

220U_X_2VM_R7M~D

C256

0.1U_0402_10V7K~D

220U_X_2VM_R7M~D

1

C871

0.1U_0402_10V7K~D

2

@

1

C872

0.1U_0402_10V7K~D

2

@

1

C873

0.1U_0402_10V7K~D

2

@

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

CPU Bypass

LA-3301P

958Wednesday, February 14, 2007

1

1.0

of

5

54.9_0402_1%~D

+1.05V_VCCP

12

R347

24.9_0402_1%~D

H_D#[0..63]8

12

R348

54.9_0402_1%~D

R350

H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63

H_SWNG
H_RCOMP

H_SCOMP
H_SCOMP#

H_RESET#7

H_CPUSLP#8

12

5

H_RESET#

H_CPUSLP#

H_VREF

H_VREF

2K_0402_1%~D

U29A

E2

H_D#_0

G2

H_D#_1

G7

H_D#_2

M6

H_D#_3

H7

H_D#_4

H3

H_D#_5

G4

H_D#_6

F3

H_D#_7

N8

H_D#_8

H2

H_D#_9

M10

H_D#_10

N12

H_D#_11

N9

H_D#_12

H5

H_D#_13

P13

H_D#_14

K9

H_D#_15

M2

H_D#_16

W10

H_D#_17

Y8

H_D#_18

V4

H_D#_19

M3

H_D#_20

J1

H_D#_21

N5

H_D#_22

N3

H_D#_23

W6

H_D#_24

W9

H_D#_25

N2

H_D#_26

Y7

H_D#_27

Y9

H_D#_28

P4

H_D#_29

W3

H_D#_30

N1

H_D#_31

AD12

H_D#_32

AE3

H_D#_33

AD9

H_D#_34

AC9

H_D#_35

AC7

H_D#_36

AC14

H_D#_37

AD11

H_D#_38

AC11

H_D#_39

AB2

H_D#_40

AD7

H_D#_41

AB1

H_D#_42

Y3

H_D#_43

AC6

H_D#_44

AE2

H_D#_45

AC5

H_D#_46

AG3

H_D#_47

AJ9

H_D#_48

AH8

H_D#_49

AJ14

H_D#_50

AE9

H_D#_51

AE11

H_D#_52

AH12

H_D#_53

AJ5

H_D#_54

AH5

H_D#_55

AJ6

H_D#_56

AE7

H_D#_57

AJ7

H_D#_58

AJ2

H_D#_59

AE5

H_D#_60

AJ3

H_D#_61

AH2

H_D#_62

AH13

H_D#_63

B3

H_SWING

C2

H_RCOMP

W1

H_SCOMP

W2

H_SCOMP#

B6

H_CPURST#

E5

H_CPUSLP#

B9

H_AVREF

A9

H_DVREF

LE88CLGM A0 QM20_FCBGA1299~D

12

R355
1K_0402_1%~D

0.1U_0402_16V4Z~D

12

1

R361

2

H_ADSTB#_0
H_ADSTB#_1

HOST

H_BREQ#

H_DEFER#

H_DBSY#

HPLL_CLK

HPLL_CLK#

H_DPWR#

H_DRDY#

H_HITM#

H_LOCK#

H_TRDY#

H_DINV#_0
H_DINV#_1
H_DINV#_2
H_DINV#_3

H_DSTBN#_0
H_DSTBN#_1
H_DSTBN#_2
H_DSTBN#_3

H_DSTBP#_0
H_DSTBP#_1
H_DSTBP#_2
H_DSTBP#_3

H_REQ#_0
H_REQ#_1
H_REQ#_2
H_REQ#_3
H_REQ#_4

H_RS#_0
H_RS#_1
H_RS#_2

+1.05V_VCCP+1.05V_VCCP

H_SWNG

100_0402_1%~D

C496

R362

D D

C C

B B

Layout Note:
H_RCOMP tr ace width
and spacing is 10/20

A A

H_A#_3
H_A#_4
H_A#_5
H_A#_6
H_A#_7
H_A#_8

H_A#_9
H_A#_10
H_A#_11
H_A#_12
H_A#_13
H_A#_14
H_A#_15
H_A#_16
H_A#_17
H_A#_18
H_A#_19
H_A#_20
H_A#_21
H_A#_22
H_A#_23
H_A#_24
H_A#_25
H_A#_26
H_A#_27
H_A#_28
H_A#_29
H_A#_30
H_A#_31
H_A#_32
H_A#_33
H_A#_34
H_A#_35

H_ADS#

H_BNR#

H_BPRI#

H_HIT#

12

R356
221_0402_1%~D

12

4

H_A#3

J13

H_A#4

B11

H_A#5

C11

H_A#6

M11

H_A#7

C15

H_A#8

F16

H_A#9

L13

H_A#10

G17

H_A#11

C14

H_A#12

K16

H_A#13

B13

H_A#14

L16

H_A#15

J17

H_A#16

B14

H_A#17

K19

H_A#18

P15

H_A#19

R17

H_A#20

B16

H_A#21

H20

H_A#22

L19

H_A#23

D17

H_A#24

M17

H_A#25

N16

H_A#26

J19

H_A#27

B18

H_A#28

E19

H_A#29

B17

H_A#30

B15

H_A#31

E17

H_A#32

C18

H_A#33

A19

H_A#34

B19

H_A#35

N19

H_ADS#

G12

H_ADSTB#0

H17

H_ADSTB#1

G20

H_BNR#

C8

H_BPRI#

E8

H_BR0#

F12

H_DEFER#

D6

H_DBSY#

C10

CLK_MCH_BCLK

AM5

CLK_MCH_BCLK#

AM7

H_DPWR#

H8

H_DRDY#

K7

H_HIT#

E4

H_HITM#

C6

H_LOCK#

G10

H_TRDY#

B7

H_DINV#0

K5

H_DINV#1

L2

H_DINV#2

AD13

H_DINV#3

AE13

H_DSTBN#0

M7

H_DSTBN#1

K3

H_DSTBN#2

AD2

H_DSTBN#3

AH11

H_DSTBP#0

L7

H_DSTBP#1

K2

H_DSTBP#2

AC2

H_DSTBP#3

AJ10

H_REQ#0

M14

H_REQ#1

E13

H_REQ#2

A11

H_REQ#3

H13

H_REQ#4

B12

H_RS#0

E12

H_RS#1

D7

H_RS#2

D8

+1.8V_SUS

R359

3.01K_0402_1%~D

0.1U_0402_16V4Z~D

1

C497

2

4

1K_0402_1%~D

R363

H_A#[3..35] 7

H_ADS# 7

H_ADSTB#0 7

H_ADSTB#1 7
H_BNR# 7
H_BPRI# 7
H_BR0# 7
H_DEFER# 7
H_DBSY# 7

CLK_MCH_BCLK 6

CLK_MCH_BCLK# 6
H_DPWR# 8
H_DRDY# 7

H_HIT# 7
H_HITM# 7
H_LOCK# 7

H_TRDY# 7

H_DINV#0 8
H_DINV#1 8
H_DINV#2 8
H_DINV#3 8

H_DSTBN#0 8
H_DSTBN#1 8
H_DSTBN#2 8
H_DSTBN#3 8

H_DSTBP#0 8
H_DSTBP#1 8
H_DSTBP#2 8
H_DSTBP#3 8

H_REQ#0 7
H_REQ#1 7
H_REQ#2 7
H_REQ#3 7
H_REQ#4 7

H_RS#0 7

H_RS#1 7

H_RS#2 7

12

R353
1K_0402_1%~D

SMRCOMP_VOH

1

12

12

C494

2

SMRCOMP_VOL

1

C498

2

+1.8V_SUS

V_DDR_MCH_REF

1K_0402_1%~D

392_0402_1~D

1

C495

2

2.2U_0603_6.3V6K~D

0.01U_0402_16V7K~D

1

C499

2

2.2U_0603_6.3V6K~D

0.01U_0402_16V7K~D

C491

+1.25V_RUN

R349

R351

3

M_ODT016
M_ODT116
M_ODT217
M_ODT317

T42PAD~D
T43PAD~D
T44PAD~D
T45PAD~D

T46PAD~D

M_CLK_DDR0
M_CLK_DDR1
M_CLK_DDR2
M_CLK_DDR3

M_CLK_DDR#0
M_CLK_DDR#1
M_CLK_DDR#2
M_CLK_DDR#3

DDR_CKE0_DIMMA
DDR_CKE1_DIMMA
DDR_CKE2_DIMMB
DDR_CKE3_DIMMB

DDR_CS0_DIMMA#
DDR_CS1_DIMMA#
DDR_CS2_DIMMB#
DDR_CS3_DIMMB#

M_ODT0
M_ODT1
M_ODT2
M_ODT3

SMRCOMP
SMRCOMP#

SMRCOMP_VOH
SMRCOMP_VOL

V_DDR_MCH_REF

MCH_DREFCLK
MCH_DREFCLK#
DREF_SSCLK
DREF_SSCLK#

CLK_MCH_3GPLL
CLK_MCH_3GPLL#

DMI_MRX_ITX_N0
DMI_MRX_ITX_N1
DMI_MRX_ITX_N2
DMI_MRX_ITX_N3

DMI_MRX_ITX_P0
DMI_MRX_ITX_P1
DMI_MRX_ITX_P2
DMI_MRX_ITX_P3

DMI_MTX_IRX_N0
DMI_MTX_IRX_N1
DMI_MTX_IRX_N2
DMI_MTX_IRX_N3

DMI_MTX_IRX_P0
DMI_MTX_IRX_P1
DMI_MTX_IRX_P2
DMI_MTX_IRX_P3

CL_CLK0
CL_DATA0
ICH_CL_PWROK
ICH_CL_RST0#
CL_VREF

SDVO_CTRLCLK
SDVO_CTRLDATA
CLK_3GPLLREQ#
MCH_ICH_SYNC#

R774 0_0402_5%~D

R357

20K_0402_5%~D

M_CLK_DDR016
M_CLK_DDR116
M_CLK_DDR217
M_CLK_DDR317

M_CLK_DDR#016
M_CLK_DDR#116
M_CLK_DDR#217
M_CLK_DDR#317

DDR_CKE0_DIMMA16
DDR_CKE1_DIMMA16
DDR_CKE2_DIMMB17
DDR_CKE3_DIMMB17

DDR_CS0_DIMMA#16
DDR_CS1_DIMMA#16
DDR_CS2_DIMMB#17
DDR_CS3_DIMMB#17

R345

20_0402_1%~D

1 2
1 2

R346

20_0402_1%~D

1

1

C492

2

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

12

12

1

2

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

MCH_DREFCLK6

MCH_DREFCLK#6

2

DREF_SSCLK#6

CLK_MCH_3GPLL6
CLK_MCH_3GPLL#6

DMI_MRX_ITX_N023
DMI_MRX_ITX_N123
DMI_MRX_ITX_N223
DMI_MRX_ITX_N323

DMI_MRX_ITX_P023
DMI_MRX_ITX_P123
DMI_MRX_ITX_P223
DMI_MRX_ITX_P323

DMI_MTX_IRX_N023
DMI_MTX_IRX_N123
DMI_MTX_IRX_N223
DMI_MTX_IRX_N323

DMI_MTX_IRX_P023
DMI_MTX_IRX_P123
DMI_MTX_IRX_P223
DMI_MTX_IRX_P323

CL_CLK023
CL_DATA023

ICH_CL_PWROK23,39

ICH_CL_RST0#23

C493

0.1U_0402_16V4Z~D

SDVO_CTRLCLK51
SDVO_CTRLDATA51

CLK_3GPLLREQ#6
MCH_ICH_SYNC#23

3

DREF_SSCLK6

AV29

SM_CK_0

BB23

SM_CK_1

BA25

SM_CK_3

AV23

SM_CK_4

AW30

SM_CK#_0

BA23

SM_CK#_1

AW25

SM_CK#_3

AW23

SM_CK#_4

BE29

SM_CKE_0

AY32

SM_CKE_1

BD39

SM_CKE_3

BG37

SM_CKE_4

BG20

SM_CS#_0

BK16

SM_CS#_1

BG16

SM_CS#_2

BE13

SM_CS#_3

BH18

SM_ODT_0

BJ15

SM_ODT_1

BJ14

SM_ODT_2

BE16

SM_ODT_3

BL15

SM_RCOMP

BK14

SM_RCOMP#

BK31

SM_RCOMP_VOH

BL31

SM_RCOMP_VOL

AR49

SM_VREF_0

AW4

SM_VREF_1

B42

DPLL_REF_CLK

C42

DPLL_REF_CLK#

H48

DPLL_REF_SSCLK

H47

DPLL_REF_SSCLK#

K44

PEG_CLK

K45

PEG_CLK#

AN47

DMI_RXN_0

AJ38

DMI_RXN_1

AN42

DMI_RXN_2

AN46

DMI_RXN_3

AM47

DMI_RXP_0

AJ39

DMI_RXP_1

AN41

DMI_RXP_2

AN45

DMI_RXP_3

AJ46

DMI_TXN_0

AJ41

DMI_TXN_1

AM40

DMI_TXN_2

AM44

DMI_TXN_3

AJ47

DMI_TXP_0

AJ42

DMI_TXP_1

AM39

DMI_TXP_2

AM43

DMI_TXP_3

E35

GFX_VID_0

A39

GFX_VID_1

C38

GFX_VID_2

B39

GFX_VID_3

E36

GFX_VR_EN

AM49

CL_CLK

AK50

CL_DATA

AT43

CL_PWROK

AN49

CL_RST#

AM50

CL_VREF

H35

SDVO_CTRL_CLK

K36

SDVO_CTRL_DATA

G39

CLK_REQ#

G40

ICH_SYNC#

A37

12
12

TEST_1

R32

TEST_2

LE88CLGM A0 QM20_FCBGA1299~D

THERMTRIP_MCH#

R358

1 2

56_0402_5%~D

2

2

RSVD CFG PM NC

DDR MUXINGCLKDMIGRAPHICS VIDMEMISC

+1.05V_VCCP

1

U29B

P36

RSVD1

P37

RSVD2

R35

RSVD3

N35

RSVD4

AR12

RSVD5

AR13

RSVD6

AM12

RSVD7

AN13

RSVD8

J12

RSVD9

AR37

RSVD10

AM36

RSVD11

AL36

RSVD12

AM37

RSVD13

D20

RSVD14

H10

RSVD20

B51

RSVD21

BJ20

RSVD22

BK22

RSVD23

BF19

RSVD24

BH20

RSVD25

BK18

RSVD26

BJ18

RSVD27

BF23

RSVD28

BG23

RSVD29

BC23

RSVD30

BD24

RSVD31

BH39

RSVD32

AW20

RSVD33

BK20

RSVD34

C48

RSVD35

D47

RSVD36

B44

RSVD37

C44

RSVD38

A35

RSVD39

B37

RSVD40

B36

RSVD41

B34

RSVD42

C34

RSVD43

CFG_0
CFG_1
CFG_2
CFG_3
CFG_4
CFG_5
CFG_6
CFG_7
CFG_8

CFG_9
CFG_10
CFG_11
CFG_12
CFG_13
CFG_14
CFG_15
CFG_16
CFG_17
CFG_18
CFG_19
CFG_20

PM_BM_BUSY#

PM_DPRSTP#
PM_EXT_TS#_0
PM_EXT_TS#_1

PWROK

RSTIN#

THERMTRIP#

DPRSLPVR

NC_1
NC_2
NC_3
NC_4
NC_5
NC_6
NC_7
NC_8

NC_9
NC_10
NC_11
NC_12
NC_13
NC_14
NC_15
NC_16

P27
N27
N24
C21
C23
F23
N23
G23
J20
C20
R24
L23
J23
E23
E20
K23
M20
M24
L32
N33
L35

G41
L39
L36
J36
AW49
AV20
N20
G36

BJ51
BK51
BK50
BL50
BL49
BL3
BL2
BK1
BJ1
E1
A5
C51
B50
A50
A49
BK2

R36

100_0402_5%~D

1 2

CFG5

CFG9

CFG16

CFG19
CFG20

PM_BMBUSY#
H_DPRSTP#
PM_EXTTS#0
PM_EXTTS#1
ICH_PWRGD
PLTRST1#_R
THERMTRIP_MCH#
DPRSLPVR

T63 PAD~D
T64 PAD~D

T65 PAD~D
T66 PAD~D
T67 PAD~D

T68 PAD~D
T69 PAD~D
T70 PAD~D
T71 PAD~D
T72 PAD~D
T73 PAD~D

T74 PAD~D
T75 PAD~D

R589

0_0402_5%~D@

R583

0_0402_5%~D

CPU_MCH_BSEL0 6,8
CPU_MCH_BSEL1 6,8
CPU_MCH_BSEL2 6,8

CFG5 12

CFG9 12

CFG16 12

CFG19 12
CFG20 12

PM_BMBUSY# 23
H_DPRSTP# 8,22,48

PM_EXTTS#0 16
PM_EXTTS#1 17

ICH_PWRGD 23,42

THERMTRIP_MCH# 18

DPRSLPVR 23,48

PM_EXTTS#0

PM_EXTTS#1

12

PLTRST1#PLTRST1#_R

12

DELL CONFIDENTIAL/PROPRIETARY

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

Crestline(1 of 6)

LA-3301P

1

+3.3V_RUN

R352

10K_0402_5%~D

12

R354

10K_0402_5%~D

12

SB_NB_PCIE_RST# 21

PLTRST1# 21,51

10 58Monday, February 26, 2007

of

1.0

5

D D

4

3

2

1

DDR_B_D[0..63] 17DDR_A_D[0..63] 16

SB_DQ_10
SB_DQ_11
SB_DQ_12
SB_DQ_13
SB_DQ_14
SB_DQ_15
SB_DQ_16
SB_DQ_17
SB_DQ_18
SB_DQ_19
SB_DQ_20
SB_DQ_21
SB_DQ_22
SB_DQ_23
SB_DQ_24
SB_DQ_25
SB_DQ_26
SB_DQ_27
SB_DQ_28
SB_DQ_29
SB_DQ_30
SB_DQ_31
SB_DQ_32
SB_DQ_33
SB_DQ_34
SB_DQ_35
SB_DQ_36
SB_DQ_37
SB_DQ_38
SB_DQ_39
SB_DQ_40
SB_DQ_41
SB_DQ_42
SB_DQ_43
SB_DQ_44
SB_DQ_45
SB_DQ_46
SB_DQ_47
SB_DQ_48
SB_DQ_49
SB_DQ_50
SB_DQ_51
SB_DQ_52
SB_DQ_53
SB_DQ_54
SB_DQ_55
SB_DQ_56
SB_DQ_57
SB_DQ_58
SB_DQ_59
SB_DQ_60
SB_DQ_61
SB_DQ_62
SB_DQ_63

U29E

SB_DQ_0
SB_DQ_1
SB_DQ_2
SB_DQ_3
SB_DQ_4
SB_DQ_5
SB_DQ_6
SB_DQ_7
SB_DQ_8
SB_DQ_9

AP49
AR51
AW50
AW51
AN51
AN50
AV50
AV49
BA50
BB50
BA49
BE50
BA51
AY49
BF50
BF49
BJ50
BJ44
BJ43
BL43
BK47
BK49
BK43
BK42
BJ41
BL41
BJ37
BJ36
BK41
BJ40
BL35
BK37
BK13
BE11
BK11
BC11
BC13
BE12
BC12
BG12
BJ10
BL9
BK5
BL5
BK9
BK10
BJ8
BJ6
BF4
BH5
BG1
BC2
BK3
BE4
BD3
BJ2
BA3
BB3
AR1
AT3
AY2
AY3
AU2
AT2

DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63

DDR_A_BS016
DDR_A_BS116
DDR_A_BS216

DDR_A_DM[0..7]16

DDR_A_DQS[0..7]16

C C

DDR_A_DQS#[0..7]16

DDR_A_MA[0..14]16

B B

DDR_A_CAS#16
DDR_A_RAS#16
DDR_A_WE#16

DDR_A_BS0
DDR_A_BS1
DDR_A_BS2

DDR_A_DM0
DDR_A_DM1
DDR_A_DM2
DDR_A_DM3
DDR_A_DM4
DDR_A_DM5
DDR_A_DM6
DDR_A_DM7

DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7

DDR_A_DQS#0
DDR_A_DQS#1
DDR_A_DQS#2
DDR_A_DQS#3

DDR_A_DQS#4

DDR_A_DQS#5
DDR_A_DQS#6

DDR_A_DQS#7

DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA14 DDR_B_MA14

DDR_A_CAS#
DDR_A_RAS#

DDR_A_WE#

T10

BB19

SA_BS_0

BK19

SA_BS_1

BF29

SA_BS_2

AT45

SA_DM_0

BD44

SA_DM_1

BD42

SA_DM_2

AW38

SA_DM_3

AW13

SA_DM_4

BG8

SA_DM_5

AY5

SA_DM_6

AN6

SA_DM_7

AT46

SA_DQS_0

BE48

SA_DQS_1

BB43

SA_DQS_2

BC37

SA_DQS_3

BB16

SA_DQS_4

BH6

SA_DQS_5

BB2

SA_DQS_6

AP3

SA_DQS_7

AT47

SA_DQS#_0

BD47

SA_DQS#_1

BC41

SA_DQS#_2

BA37

SA_DQS#_3

BA16

SA_DQS#_4

BH7

SA_DQS#_5

BC1

SA_DQS#_6

AP2

SA_DQS#_7

BJ19

SA_MA_0

BD20

SA_MA_1

BK27

SA_MA_2

BH28

SA_MA_3

BL24

SA_MA_4

BK28

SA_MA_5

BJ27

SA_MA_6

BJ25

SA_MA_7

BL28

SA_MA_8

BA28

SA_MA_9

BC19

SA_MA_10

BE28

SA_MA_11

BG30

SA_MA_12

BJ16

SA_MA_13

BJ29

SA_MA_14

BL17

SA_CAS#

BE18

SA_RAS#

BA19

SA_WE#

AY20

SA_RCVEN#

LE88CLGM A0 QM20_FCBGA1299~D

DDR SYSTEM MEMORY A

SA_DQ_0
SA_DQ_1
SA_DQ_2
SA_DQ_3
SA_DQ_4
SA_DQ_5
SA_DQ_6
SA_DQ_7
SA_DQ_8

SA_DQ_9
SA_DQ_10
SA_DQ_11
SA_DQ_12
SA_DQ_13
SA_DQ_14
SA_DQ_15
SA_DQ_16
SA_DQ_17
SA_DQ_18
SA_DQ_19
SA_DQ_20
SA_DQ_21
SA_DQ_22
SA_DQ_23
SA_DQ_24
SA_DQ_25
SA_DQ_26
SA_DQ_27
SA_DQ_28
SA_DQ_29
SA_DQ_30
SA_DQ_31
SA_DQ_32
SA_DQ_33
SA_DQ_34
SA_DQ_35
SA_DQ_36
SA_DQ_37
SA_DQ_38
SA_DQ_39
SA_DQ_40
SA_DQ_41
SA_DQ_42
SA_DQ_43
SA_DQ_44
SA_DQ_45
SA_DQ_46
SA_DQ_47
SA_DQ_48
SA_DQ_49
SA_DQ_50
SA_DQ_51
SA_DQ_52
SA_DQ_53
SA_DQ_54
SA_DQ_55
SA_DQ_56
SA_DQ_57
SA_DQ_58
SA_DQ_59
SA_DQ_60
SA_DQ_61
SA_DQ_62
SA_DQ_63

U29D

AR43
AW44
BA45
AY46
AR41
AR45
AT42
AW47
BB45
BF48
BG47
BJ45
BB47
BG50
BH49
BE45
AW43
BE44
BG42
BE40
BF44
BH45
BG40
BF40
AR40
AW40
AT39
AW36
AW41
AY41
AV38
AT38
AV13
AT13
AW11
AV11
AU15
AT11
BA13
BA11
BE10
BD10
BD8
AY9
BG10
AW9
BD7
BB9
BB5
AY7
AT5
AT7
AY6
BB7
AR5
AR8
AR9
AN3
AM8
AN10
AT9
AN9
AM9
AN11

DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63

DDR_B_BS017
DDR_B_BS117
DDR_B_BS217

DDR_B_DM[0..7]17

DDR_B_DQS[0..7]17

DDR_B_DQS#[0..7]17

DDR_B_MA[0..14]17

DDR_B_CAS#17
DDR_B_RAS#17
DDR_B_WE#17

DDR_B_BS0
DDR_B_BS1
DDR_B_BS2

DDR_B_DM0
DDR_B_DM1
DDR_B_DM2
DDR_B_DM3
DDR_B_DM4
DDR_B_DM5
DDR_B_DM6
DDR_B_DM7

DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4
DDR_B_DQS5
DDR_B_DQS6
DDR_B_DQS7

DDR_B_DQS#0
DDR_B_DQS#1
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS#4
DDR_B_DQS#5
DDR_B_DQS#6
DDR_B_DQS#7

DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13

DDR_B_CAS#
DDR_B_RAS#
DDR_B_WE#

SB_RCVEN#SA_RCVEN#

T11

AY17

SB_BS_0

BG18

SB_BS_1

BG36

SB_BS_2

AR50

SB_DM_0

BD49

SB_DM_1

BK45

SB_DM_2

BL39

SB_DM_3

BH12

SB_DM_4

BJ7

SB_DM_5

BF3

SB_DM_6

AW2

SB_DM_7

AT50

SB_DQS_0

BD50

SB_DQS_1

BK46

SB_DQS_2

BK39

SB_DQS_3

BJ12

SB_DQS_4

BL7

SB_DQS_5

BE2

SB_DQS_6

AV2

SB_DQS_7

AU50

SB_DQS#_0

BC50

SB_DQS#_1

BL45

SB_DQS#_2

BK38

SB_DQS#_3

BK12

SB_DQS#_4

BK7

SB_DQS#_5

BF2

SB_DQS#_6

AV3

SB_DQS#_7

BC18

SB_MA_0

BG28

SB_MA_1

BG25

SB_MA_2

AW17

SB_MA_3

BF25

SB_MA_4

BE25

SB_MA_5

BA29

SB_MA_6

BC28

SB_MA_7

AY28

SB_MA_8

BD37

SB_MA_9

BG17

SB_MA_10

BE37

SB_MA_11

BA39

SB_MA_12

BG13

SB_MA_13

BE24

SB_MA_14

BE17

SB_CAS#

AV16

SB_RAS#

BC17

SB_WE#

AY18

SB_RCVEN#

LE88CLGM A0 QM20_FCBGA1299~D

DDR SYSTEM MEMORY B

A A

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

Crestline(2 of 6)

LA-3301P

11 58Monday, February 26, 2007

1

1.0

of

5

4

3

2

1

Strap Pin Table

DMI X2 Select

PCI Express
Graphic Lane

FSB Dynamic

ODT

DMI Lane
Reversal

SDVO/PCIE
Concurrent
Operation

Low = DMI x 2
High = DMI x 4 (Default)

Low = Reverse LaneCFG9
High = Normal O p e r a t i o n ( Default)

Low=Dynamic O D T Disable
High=Dynamic ODT Enable(default)

Low=Normal (default)
High=Lane Reversed

Low=Only SDVO or PCIEx1 is
operational (defaults)

High=SDVO and P C I E x 1 a r e o p e rating
simultaneously via PEG port

Low=No SDVO Device Present

High=SDVO Device Present (default)

R383

2.2K_0402_5%~D

G_CLK_DDC2

G_DAT_DDC2

+3.3V_RUN

2

NO CONNECT FOR DISCRETE

12

12

R384

2.2K_0402_5%~D
Q36

D

S

13

G

+3.3V_RUN

2

G

2

Q37

13

D

S

CLK_DDC2

DAT_DDC2

R365 4.02K_0402_1%~D@

CFG510

CFG910

CFG1610

1 2

R368 4.02K_0402_1%~D@

1 2

R372 4.02K_0402_1%~D@

1 2

CFG[3:17] have internal pullup

R373 4.02K_0402_1%~D@

CFG1910

CFG2010

1 2

R374 4.02K_0402_1%~D @

1 2

CFG[18:19] have internal pulldown

BSS138_SOT23~D

BSS138_SOT23~D

CLK_DDC2 20,36

DAT_DDC2 20,36

DELL CONFIDENTIAL/PROPRIETARY

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

Crestline(3 of 6)

LA-3301P

12 58Monday, February 26, 2007

1

+3.3V_RUN

1.0

of

BIA_PWM19

D D

R369 = 2.4k ohm value is
recommended per Intel

C C

TV_CVBS36
TV_Y36
TV_C36

CRT_BLU20,36
CRT_GRN20,36
CRT_RED20,36

B B

R378

R379

1 2

1 2

150_0402_1%~D

150_0402_1%~D

+3.3V_RUN

A A

1 2

R41 2.2K_0402_5%~D

1 2

R110 2.2K_0402_5%~D

PANEL_BKEN38

LCD_DDCCLK19
LCD_DDCDATA19

ENVDD19

1 2

R369

3.3K_0402_1%~D

LCD_A0-19
LCD_A1-19
LCD_A2-19

LCD_A0+19
LCD_A1+19
LCD_A2+19

LCD_B0-19
LCD_B1-19
LCD_B2-19

LCD_B0+19
LCD_B1+19
LCD_B2+19

12

12

R377

R376

150_0402_1%~D

CRT_HSYNC20
CRT_VSYNC20

R382 1.3K_0402_1%~D

Trace CRT_IREF should be at
least 20 miles away from any
other toggling signal.

LCD_DDCCLK

LCD_DDCDATA

5

R375

R380

12

150_0402_1%~D

1 2

150_0402_1%~D

BIA_PWM
PANEL_BKEN

LCD_DDCCLK
LCD_DDCDATA
ENVDD

L_IBG

LCD_ACLK-_C
LCD_ACLK+_C
LCD_BCLK-_C
LCD_BCLK+_C

TV_CVBS
TV_Y
TV_C

150_0402_1%~D

G_CLK_DDC2
G_DAT_DDC2
CRT_HSYNC
CRT_VSYNC

CRT_IREF

12

LCD_A0+
LCD_A1+
LCD_A2+
LCD_B0+
LCD_B1+
LCD_B2+

J40

H39

E39

E40
C37
D35

K40

L41

L43
N41
N40

D46
C45
D44

E42
G51

E51

F49

G50

E50

F48

G44

B47

B45

E44

A47

A45

E27
G27

K27

F27

J27

L27
M35

P33

H32
G32

K29

J29

F29

E29

K33
G35

F33

E33
C32

L_BKLT_CTRL
L_BKLT_EN
L_CTRL_CLK
L_CTRL_DATA
L_DDC_CLK
L_DDC_DATA
L_VDD_EN

LVDS_IBG
LVDS_VBG
LVDS_VREFH
LVDS_VREFL

LVDSA_CLK#
LVDSA_CLK
LVDSB_CLK#
LVDSB_CLK

LVDSA_DATA#_0
LVDSA_DATA#_1
LVDSA_DATA#_2

LVDSA_DATA_0
LVDSA_DATA_1
LVDSA_DATA_2

LVDSB_DATA#_0
LVDSB_DATA#_1
LVDSB_DATA#_2

LVDSB_DATA_0
LVDSB_DATA_1
LVDSB_DATA_2

TVA_DAC
TVB_DAC
TVC_DAC

TVA_RTN
TVB_RTN
TVC_RTN

TV_DCONSEL_0
TV_DCONSEL_1

CRT_BLUE
CRT_BLUE#
CRT_GREEN
CRT_GREEN#
CRT_RED
CRT_RED#

CRT_DDC_CLK
CRT_DDC_DATA
CRT_HSYNC
CRT_VSYNC

CRT_TVO_IREF

C181 3.3P_0402_50V8C~D@
C192 3.3P_0402_50V8C~D@
C193 3.3P_0402_50V8C~D@
C196 3.3P_0402_50V8C~D@
C207 3.3P_0402_50V8C~D@
C209 3.3P_0402_50V8C~D@

U29C

LVDS TV VGA

LE88CLGM A0 QM20_FCBGA1299~D

LCD_A0-

1 2

LCD_A1-

1 2

LCD_A2-

1 2

LCD_B0-

1 2

LCD_B1-

1 2

LCD_B2-

1 2

Keep stub for
caps as small
as possible

PEGCOMP

PEG_RX#_0
PEG_RX#_1
PEG_RX#_2
PEG_RX#_3
PEG_RX#_4
PEG_RX#_5
PEG_RX#_6
PEG_RX#_7
PEG_RX#_8
PEG_RX#_9

PEG_RX_0
PEG_RX_1
PEG_RX_2
PEG_RX_3
PEG_RX_4
PEG_RX_5
PEG_RX_6
PEG_RX_7
PEG_RX_8

PEG_RX_9
PEG_RX_10
PEG_RX_11
PEG_RX_12
PEG_RX_13
PEG_RX_14
PEG_RX_15

PEG_TX#_0
PEG_TX#_1
PEG_TX#_2
PEG_TX#_3
PEG_TX#_4
PEG_TX#_5
PEG_TX#_6
PEG_TX#_7
PEG_TX#_8
PEG_TX#_9

PEG_TX_0

PEG_TX_1

PEG_TX_2

PEG_TX_3

PEG_TX_4

PEG_TX_5

PEG_TX_6

PEG_TX_7

PEG_TX_8

PEG_TX_9
PEG_TX_10
PEG_TX_11
PEG_TX_12
PEG_TX_13
PEG_TX_14
PEG_TX_15

LCD_ACLK-_C

3.3P_0402_50V8C~D

LCD_ACLK+_C

LCD_BCLK-_C

3.3P_0402_50V8C~D

LCD_BCLK+_C

N43
M43

J51
L51
N47
T45
T50
U40
Y44
Y40
AB51
W49
AD44
AD40
AG46
AH49
AG45
AG41

J50
L50
M47
U44
T49
T41
W45
W41
AB50
Y48
AC45
AC41
AH47
AG49
AH45
AG42

N45
U39
U47
N51
R50
T42
Y43
W46
W38
AD39
AC46
AC49
AC42
AH39
AE49
AH44

M45
T38
T46
N50
R51
U43
W42
Y47
Y39
AC38
AD47
AC50
AD43
AG39
AE50
AH43

@

C39

C43

@

PEG_COMPI

PEG_COMPO

PEG_RX#_10
PEG_RX#_11
PEG_RX#_12
PEG_RX#_13
PEG_RX#_14
PEG_RX#_15

PCI-EXPRESS GRAPHICS

PEG_TX#_10
PEG_TX#_11
PEG_TX#_12
PEG_TX#_13
PEG_TX#_14
PEG_TX#_15

4

R366

24.9_0402_1%~D

1 2

SDVOB_RED-_C
SDVOB_GREEN-_C
SDVOB_BLUE-_C
SDVOB_CLK-_C

SDVOB_RED+_C
SDVOB_GREEN+_C
SDVOB_BLUE+_C
SDVOB_CLK+_C

12

1

@

0_0402_5%~D

2

12

1

R687

@

0_0402_5%~D

2

+VCC_PEG

SDVOB_INT- 51

SDVOB_INT+ 51

C500 0.1U_0402_10V7K~D

1 2

C501 0.1U_0402_10V7K~D

1 2

C502 0.1U_0402_10V7K~D

1 2

C503 0.1U_0402_10V7K~D

1 2

C504 0.1U_0402_10V7K~D

1 2

C505 0.1U_0402_10V7K~D

1 2

C506 0.1U_0402_10V7K~D

1 2

C507 0.1U_0402_10V7K~D

1 2

R686

0_0402_5%~D

1 2

R667

1 2

R685
0_0402_5%~D

R689

0_0402_5%~D

1 2

1 2

R688

0_0402_5%~D

LCD_ACLK- 19

LCD_ACLK+ 19

LCD_BCLK- 19

LCD_BCLK+ 19

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

CFG5

CFG16

CFG19

CFG20

SDVO_CRTL_DATA

SDVOB_RED- 51
SDVOB_GREEN- 51
SDVOB_BLUE- 51
SDVOB_CLK- 51

SDVOB_RED+ 51
SDVOB_GREEN+ 51
SDVOB_BLUE+ 51
SDVOB_CLK+ 51

5

+1.05V_VCCP

CRB 270uF

220U_D2_4VY_R15M~D

1

C535

1

+

C537

2

2

D D

C C

B B

A A

4.7U_0603_6.3V6M~D

C542

1

2

+1.25V_RUN

BLM18AG121SN1D_0603~D

22U_0805_6.3V6M~D

1

2

+1.25V_RUN

0.1U_0402_16V4Z~D
C591

+3.3V_RUN

+VCC_RXR_DMI

0.47U_0402_10V4Z~D

1

2

+1.8V_RUN

+1.8V_SUS

+1.25V_RUN

1U_0603_10V4Z~D

C589

1

2

Place caps close
to VCC_AXF (Pin
A21, B21, B23)

4.7U_0603_6.3V6M~D

C543

1

1

2

2

L33

1U_0603_10V4Z~D

C551

1

2

1

2

+VCC_TX_LVDS

0.1U_0402_16V4Z~D
C597

1

2

0.47U_0402_10V4Z~D
C577

C576

1

2

0_0603_5%~D

1 2
1 2

0_0603_5%~D

10U_0805_4VAM~D

1

C590

2

2.2U_0603_6.3V6K~D

+1.25V_RUN_AXD

12

C552

+1.8V_SM_CK

1

2

0.47U_0402_10V4Z~D

C544

+1.25V_RUN

+VCC_PEG

0.47U_0402_10V4Z~D
C578

R579

@

R578

5

U13

VTT_1

U12

VTT_2

U11

VTT_3

U9

VTT_4

U8

VTT_5

U7

VTT_6

U5

VTT_7

U3

VTT_8

U2

VTT_9

U1

VTT_10

T13

VTT_11

T11

VTT_12

T10

VTT_13

T9

VTT_14

T7

VTT_15

T6

VTT_16

T5

VTT_17

T3

VTT_18

T2

VTT_19

R3

VTT_20

R2

VTT_21

R1

VTT_22

AT23

VCC_AXD_1

AU28

VCC_AXD_2

AU24

VCC_AXD_3

AT29

VCC_AXD_4

AT25

VCC_AXD_5

AT30

VCC_AXD_6

AR29

VCC_AXD_NCTF

B23

VCC_AXF_1

B21

VCC_AXF_2

A21

VCC_AXF_3

AJ50

VCC_DMI

BK24

VCC_SM_CK_1

BK23

VCC_SM_CK_2

BJ24

VCC_SM_CK_3

BJ23

VCC_SM_CK_4

A43

VCC_TX_LVDS

C40

VCC_HV_1

B40

VCC_HV_2

AD51

VCC_PEG_1

W50

VCC_PEG_2

W51

VCC_PEG_3

V49

VCC_PEG_4

V50

VCC_PEG_5

AH50

VCC_RXR_DMI_1

AH51

VCC_RXR_DMI_2

A7

VTTLF1

F2

VTTLF2

AH1

VTTLF3

LE88CLGM A0 QM20_FCBGA1299~D

+VCC_TX_LVDS_R

BLM18AG121SN1D_0603~D

AXD

POWER

VTTLF

L42

VTT

AXF

PEG

VCCA_CRT_DAC_1
VCCA_CRT_DAC_2

CRT

VCCA_DAC_BG
VSSA_DAC_BG

VCCA_DPLLA

PLL

VCCA_DPLLB

LVDS PEG

VCCA_PEG_BG
VSSA_PEG_BG

VCCA_PEG_PLL

SM

VCCA_SM_10
VCCA_SM_11

CLK

VCCA_SM_NCTF_1
VCCA_SM_NCTF_2

VCCA_SM_CK_1
VCCA_SM_CK_2

VCCA_TVA_DAC_1
VCCA_TVA_DAC_2

TV

VCCA_TVB_DAC_1
VCCA_TVB_DAC_2
VCCA_TVC_DAC_1
VCCA_TVC_DAC_2

TV/CRT

VCCD_TVDAC

DMI

VCCD_PEG_PLL

LVDS

VCCD_LVDS_1
VCCD_LVDS_2

+VCC_TX_LVDS

12

1000P_0402_50V7K~D

1

C596

2

U29H

VCCSYNC

VCCA_HPLL

VCCA_MPLL

VCCA_LVDS
VSSA_LVDS

VCCA_SM_1
VCCA_SM_2
VCCA_SM_3
VCCA_SM_4
VCCA_SM_5
VCCA_SM_7
VCCA_SM_8
VCCA_SM_9

VCCD_CRT

VCCD_QDAC

VCCD_HPLL

220U_D2_4VY_R15M~D

1

+

C595

2

J32
A33

B33

A30
B32

B49
H49
AL2
AM2

A41
B41

K50
K49

U51

AW18
AV19
AU19
AU18
AU17
AT22
AT21
AT19
AT18
AT17
AR17
AR16

BC29
BB29

C25
B25
C27
B27
B28
A28

M32
L29

N28

AN2
U48

J41
H42

4

1

2

+3.3V_CRT_DAC

+3.3V_RUN_DAC_BG

+1.25V_RUN_DPLLA
+1.25V_RUN_DPLLB
+1.25V_RUN_HPLL
+1.25V_RUN_MPLL

+1.25V_RUN_PEGPLL

+1.25V_RUN_A_SM

+1.25V_RUN_SM_CK

+3.3V_RUN_TVDACA
+3.3V_RUN_TVDACB
+3.3V_RUN_TVDACC

+1.5V_RUN_TVDAC
+1.5V_RUN_QDAC

1

2

1U_0603_10V4Z~D

1

C581

2

4

+3.3V_RUN

C532

0.1U_0402_16V4Z~D

1 2

0.1U_0402_16V4Z~D

3

C536

22n_0805_25V

12

1

2

L41

C561

22U_0805_6.3V6M~D

C564

1

2

C642

+3.3V_RUN

1 2

22U_0805_6.3V6M~D

0_0805_5%~D

C562

1U_0603_10V4Z~D

1

2

0.1U_0402_16V4Z~D

12

1 2

10_0603_5%~D

1

2

1

2

R406

C565

12

R417

1

C723

2

@

0.022U_0402_16V7K~D

+VCC_TX_LVDS

4.7U_0603_6.3V6M~D

1U_0603_10V4Z~D

+1.25V_RUN_PEGPLL

0.1U_0402_16V4Z~D

C554

@

0_0603_5%~D

0_0603_5%~D

22U_0805_6.3V6M~D

C560

1

C559

2

R116

R152

BLM18AG121SN1D_0603~D

1

1

2

2

0.1U_0402_16V4Z~D

C563

1

2

+1.25V_RUN

12

+1.8V_RUN

12

+1.8V_SUS

+1.8V_SUS +1.8V_SM_CK

C594

10U_0805_4VAM~D

+1.05V_VCCP

2 1

D16

RB751V_SOD323~D

+3.3V_RUN

L31

C541

+VCC_TX_LVDS

0.1U_0402_16V4Z~D

C550

+1.25V_RUN

1U_0603_10V4Z~D

C566

1

2

1

2

1_0603_5%~D

R416

+3.3V_RUN

12

1

C547

2

1

+

C558

2

1 2

0_0603_5%~D

1

C722

2

0.022U_0402_16V7K~D

+1.5V_RUN_TVDAC

0.1U_0402_16V4Z~D
C592

1

2

BLM18PG181SN1_0603~D

1

2

+1.5V_RUN_QDAC

3

+3.3V_RUN_DAC_BG +3.3V_RUN

1 2

3

C533

22n_0805_25V

L29

BLM18PG181SN1_0603~D

1

2

12

C538

0.1U_0402_16V4Z~D

C533,C534,C536,C545,C553,C579 are being
replaced by 0-ohm 0805 resistor

+VCC_PEG

220U_D2_4VY_R15M~D

C548

1000P_0402_50V7K~D

C556

+1.25V_RUN

100U_D2E_6.3VM_R18M~D

R408

C569

1U_0603_10V4Z~D

1

2

C567

10U_0805_4VAM~D

R815

100_0603_5%~D

1 2

1

C570

2

0.1U_0402_16V4Z~D

1

C720

2

@

0.022U_0402_16V7K~D

C593

22U_0805_6.3VAM~D

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

1

1

+

2

2

+VCC_RXR_DMI

1

1

+

2

2

220U_D2_4VY_R15M~D

L35

BLM21PG221SN1D_0805~D

1 2

12

1_0402_5%~D

1 2

22n_0805_25V

3

C579

10U_0805_4VAM~D

C549

C557

10U_0805_4VAM~D

R409

+1.5V_RUN

0.1U_0402_16V4Z~D

1

2

L32

BLM18PG181SN1_0603~D

L34

BLM18PG181SN1_0603~D

+1.25V_RUN_PEGPLL+1.25V_RUN

+1.25V_RUN_HPLL

C571

0.1U_0402_16V4Z~D

C584

40mA Max.

C587

0.1U_0402_16V4Z~D

12

+1.05V_VCCP

12

+1.05V_VCCP

0.1U_0402_16V4Z~D
C568

1

2

L37

BLM18AG121SN1D_0603~D

1

1

C572

2

2

22U_0805_6.3VAM~D

L39

10U_MLZ2012E100PTAIN_60mA_25%_0805~D

1

1

+

C585
470U_D2_2.5VM_R15~D

2

2

2

+1.25V_RUN

12

1

2

12

2

Non-iAMT

C573

0.1U_0402_16V4Z~D

1

L30

C540

+1.25V_RUN

12

+1.25V_RUN+1.25V_RUN

12

+3.3V_RUN+3.3V_RUN_TVDAC

12

+3.3V_RUN_TVDACA

1 2

C534

+3.3V_RUN_TVDACB

1 2

C545

+3.3V_RUN_TVDACC

1 2

C553

45mA Max.45mA Max.

0.1U_0402_16V4Z~D

40mA Max.

0.1U_0402_16V4Z~D

3

22n_0805_25V

3

22n_0805_25V

3

22n_0805_25V

+1.25V_RUN_MPLL

C574

+1.25V_RUN_DPLLB+1.25V_RUN_DPLLA

C588

1

2

1

2

1

2

1

2

1

2

BLM18PG181SN1_0603~D

1

10U_0805_10V4Z~D

C539

2

0.1U_0402_16V4Z~D

C546

0.1U_0402_16V4Z~D

C555

0.1U_0402_16V4Z~D

L38

BLM18AG121SN1D_0603~D

1

C575
22U_0805_6.3VAM~D

2

L40

10U_MLZ2012E100PTAIN_60mA_25%_0805~D

1

+

C586
470U_D2_2.5VM_R15~D

2

DELL CONFIDENTIAL/PROPRIETARY

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

Crestline(4 of 6)

LA-3301P

13 58Wednesday, March 07, 2007

1

1.0

of

5

4

3

2

1

+3.3V_RUN

+1.05V_VCCP

D D

220U_D2_4VY_R15M~D

Layout Note:
370 mils from edge

C C

B B

Layout Note:
Place close to GMCH edge.

1

C602

+

2

Layout Note:
Inside GMCH cavity.

+1.05V_VCCP

22U_0805_6.3V6M~D

C615

1

2

0.1U_0402_10V7K~D

C618

1

2

0.22U_0402_10V4Z~D

22U_0805_6.3VAM~D

C603

1

2

1

2

C604

1

1

2

2

0.22U_0402_10V4Z~D

0.1U_0402_10V7K~D
C614

C613

1

1

2

2

0.22U_0402_10V4Z~D

0.22U_0402_10V4Z~D

C616

C617

1

2

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

C619

C620

1

2

AB33
AB36
AB37
AC33
AC35
AC36
AD35
AD36
AF33
AF36
AH33
AH35
AH36
AH37

AJ33

AJ35
AK33
AK35
AK36
AK37
AD33

AJ36

AM35

AL33

AL35
AA33
AA35
AA36
AP35
AP36
AR35
AR36

AL24

AL26

AL28

AM26
AM28
AM29
AM31
AM32
AM33

AP29
AP31
AP32
AP33

AL29

AL31

AL32
AR31
AR32
AR33

Y32
Y33
Y35
Y36
Y37
T30
T34

T35
U29
U31
U32
U33
U35
U36

V32

V33

V36

V37

U29F

VCC_NCTF_1
VCC_NCTF_2
VCC_NCTF_3
VCC_NCTF_4
VCC_NCTF_5
VCC_NCTF_6
VCC_NCTF_7
VCC_NCTF_8
VCC_NCTF_9
VCC_NCTF_10
VCC_NCTF_11
VCC_NCTF_12
VCC_NCTF_13
VCC_NCTF_14
VCC_NCTF_15
VCC_NCTF_16
VCC_NCTF_17
VCC_NCTF_18
VCC_NCTF_19
VCC_NCTF_20
VCC_NCTF_21
VCC_NCTF_22
VCC_NCTF_23
VCC_NCTF_24
VCC_NCTF_25
VCC_NCTF_26
VCC_NCTF_27
VCC_NCTF_28
VCC_NCTF_29
VCC_NCTF_30
VCC_NCTF_31
VCC_NCTF_32
VCC_NCTF_33
VCC_NCTF_34
VCC_NCTF_35
VCC_NCTF_36
VCC_NCTF_37
VCC_NCTF_38
VCC_NCTF_39
VCC_NCTF_40
VCC_NCTF_41
VCC_NCTF_42
VCC_NCTF_43
VCC_NCTF_44
VCC_NCTF_45
VCC_NCTF_46
VCC_NCTF_47
VCC_NCTF_48
VCC_NCTF_49
VCC_NCTF_50

VCC_AXM_NCTF_1
VCC_AXM_NCTF_2
VCC_AXM_NCTF_3
VCC_AXM_NCTF_4
VCC_AXM_NCTF_5
VCC_AXM_NCTF_6
VCC_AXM_NCTF_7
VCC_AXM_NCTF_8
VCC_AXM_NCTF_9
VCC_AXM_NCTF_10
VCC_AXM_NCTF_11
VCC_AXM_NCTF_12
VCC_AXM_NCTF_13
VCC_AXM_NCTF_14
VCC_AXM_NCTF_15
VCC_AXM_NCTF_16
VCC_AXM_NCTF_17
VCC_AXM_NCTF_18
VCC_AXM_NCTF_19

POWER

LE88CLGM A0 QM20_FCBGA1299~D

VSS_NCTF_1
VSS_NCTF_2
VSS_NCTF_3
VSS_NCTF_4
VSS_NCTF_5
VSS_NCTF_6
VSS_NCTF_7
VSS_NCTF_8

VSS_NCTF_9
VSS_NCTF_10
VSS_NCTF_11
VSS_NCTF_12
VSS_NCTF_13
VSS_NCTF_14
VSS_NCTF_15
VSS_NCTF_16
VSS_NCTF_17
VSS_NCTF_18
VSS_NCTF_19
VSS_NCTF_20
VSS_NCTF_21

VSS_SCB1
VSS_SCB2
VSS_SCB3
VSS_SCB4
VSS_SCB5
VSS_SCB6

VCC_AXM_1
VCC_AXM_2
VCC_AXM_3
VCC_AXM_4
VCC_AXM_6
VCC_AXM_5
VCC_AXM_7

R420

10_0603_5%~D

1 2

T27
T37
U24
U28
V31
V35
AA19
AB17
AB35
AD19
AD37
AF17
AF35
AK17
AM17
AM24
AP26
AP28
AR15
AR19
AR28

A3
B2
C1
BL1
BL51
A51

+1.05V_VCCP

AT33
AT31
AK29
AK24
AK23
AJ26
AJ23

D17

2

1

3

BAT54CW_SOT323~D

+1.8V_SUS

0.1U_0402_10V7K~D

2

C608

1

Layout Note:
Place C901 where
LVDS and DDR2 taps.

330U_D2E_2.5VM~D

1

C605

+

2

Layout Note: Inside GMCH cavity.

+1.05V_VCCP+1.05V_VCCP

22U_0805_6.3V6M~D

22U_0805_6.3V6M~D

1

1

C606

C607

2

2

Layout Note:
Place on the edge

+1.05V_VCCP

AT35
AT34
AH28
AC32
AC31
AK32

AJ31

AJ28
AH32
AH31
AH29
AF32

R30

AU32
AU33
AU35
AV33

AW33
AW35

AY35
BA32
BA33
BA35
BB33
BC32
BC33
BC35
BD32
BD35
BE32
BE33
BE35
BF33
BF34

BG32
BG33
BG35

BH32
BH34
BH35

BJ32

BJ33

BJ34
BK32
BK33
BK34
BK35

BL33
AU30

R20
W13

W14

AA20
AA23
AA26
AA28
AB21
AB24
AB29
AC20
AC21
AC23
AC24
AC26
AC28
AC29
AD20
AD23
AD24
AD28
AF21
AF26
AA31
AH20
AH21
AH23
AH24
AH26
AD31

AJ20
AN14

T14

Y12

VCC_1
VCC_2
VCC_3
VCC_4
VCC_5
VCC_6
VCC_7
VCC_8
VCC_9
VCC_10
VCC_11
VCC_12

VCC_13

VCC_SM_1
VCC_SM_2
VCC_SM_3
VCC_SM_4
VCC_SM_5
VCC_SM_6
VCC_SM_7
VCC_SM_8
VCC_SM_9
VCC_SM_10
VCC_SM_11
VCC_SM_12
VCC_SM_13
VCC_SM_14
VCC_SM_15
VCC_SM_16
VCC_SM_17
VCC_SM_18
VCC_SM_19
VCC_SM_20
VCC_SM_21
VCC_SM_22
VCC_SM_23
VCC_SM_24
VCC_SM_25
VCC_SM_26
VCC_SM_27
VCC_SM_28
VCC_SM_29
VCC_SM_30
VCC_SM_31
VCC_SM_32
VCC_SM_33
VCC_SM_34
VCC_SM_35
VCC_SM_36

VCC_AXG_1
VCC_AXG_2
VCC_AXG_3
VCC_AXG_4
VCC_AXG_5
VCC_AXG_6
VCC_AXG_7
VCC_AXG_8
VCC_AXG_9
VCC_AXG_10
VCC_AXG_11
VCC_AXG_12
VCC_AXG_13
VCC_AXG_14
VCC_AXG_15
VCC_AXG_16
VCC_AXG_17
VCC_AXG_18
VCC_AXG_19
VCC_AXG_20
VCC_AXG_21
VCC_AXG_22
VCC_AXG_23
VCC_AXG_24
VCC_AXG_25
VCC_AXG_26
VCC_AXG_27
VCC_AXG_28
VCC_AXG_29
VCC_AXG_30
VCC_AXG_31
VCC_AXG_32
VCC_AXG_33
VCC_AXG_34

U29G

VCC_AXG_NCTF_1
VCC_AXG_NCTF_2
VCC_AXG_NCTF_3

VCC CORE

POWER

VCC SM

VCC GFX

LE88CLGM A0 QM20_FCBGA1299~D

VCC_AXG_NCTF_4
VCC_AXG_NCTF_5
VCC_AXG_NCTF_6
VCC_AXG_NCTF_7
VCC_AXG_NCTF_8

VCC_AXG_NCTF_9
VCC_AXG_NCTF_10
VCC_AXG_NCTF_11
VCC_AXG_NCTF_12
VCC_AXG_NCTF_13
VCC_AXG_NCTF_14
VCC_AXG_NCTF_15
VCC_AXG_NCTF_16
VCC_AXG_NCTF_17
VCC_AXG_NCTF_18
VCC_AXG_NCTF_19
VCC_AXG_NCTF_20
VCC_AXG_NCTF_21
VCC_AXG_NCTF_22
VCC_AXG_NCTF_23
VCC_AXG_NCTF_24
VCC_AXG_NCTF_25
VCC_AXG_NCTF_26
VCC_AXG_NCTF_27
VCC_AXG_NCTF_28
VCC_AXG_NCTF_29
VCC_AXG_NCTF_30
VCC_AXG_NCTF_31
VCC_AXG_NCTF_32
VCC_AXG_NCTF_33
VCC_AXG_NCTF_34
VCC_AXG_NCTF_35
VCC_AXG_NCTF_36
VCC_AXG_NCTF_37
VCC_AXG_NCTF_38
VCC_AXG_NCTF_39
VCC_AXG_NCTF_40
VCC_AXG_NCTF_41
VCC_AXG_NCTF_42
VCC_AXG_NCTF_43
VCC_AXG_NCTF_44
VCC_AXG_NCTF_45
VCC_AXG_NCTF_46
VCC_AXG_NCTF_47
VCC_AXG_NCTF_48

VCC GFX NCTFVCC SM LF

VCC_AXG_NCTF_49
VCC_AXG_NCTF_50
VCC_AXG_NCTF_51
VCC_AXG_NCTF_52
VCC_AXG_NCTF_53
VCC_AXG_NCTF_54
VCC_AXG_NCTF_55
VCC_AXG_NCTF_56
VCC_AXG_NCTF_57
VCC_AXG_NCTF_58
VCC_AXG_NCTF_59
VCC_AXG_NCTF_60
VCC_AXG_NCTF_61
VCC_AXG_NCTF_62
VCC_AXG_NCTF_63
VCC_AXG_NCTF_64
VCC_AXG_NCTF_65
VCC_AXG_NCTF_66
VCC_AXG_NCTF_67
VCC_AXG_NCTF_68
VCC_AXG_NCTF_69
VCC_AXG_NCTF_70
VCC_AXG_NCTF_71
VCC_AXG_NCTF_72
VCC_AXG_NCTF_73
VCC_AXG_NCTF_74
VCC_AXG_NCTF_75
VCC_AXG_NCTF_76
VCC_AXG_NCTF_77
VCC_AXG_NCTF_78
VCC_AXG_NCTF_79
VCC_AXG_NCTF_80
VCC_AXG_NCTF_81
VCC_AXG_NCTF_82
VCC_AXG_NCTF_83

VCC_SM_LF1
VCC_SM_LF2
VCC_SM_LF3
VCC_SM_LF4
VCC_SM_LF5
VCC_SM_LF6
VCC_SM_LF7

T17
T18
T19
T21
T22
T23
T25
U15
U16
U17
U19
U20
U21
U23
U26
V16
V17
V19
V20
V21
V23
V24
Y15
Y16
Y17
Y19
Y20
Y21
Y23
Y24
Y26
Y28
Y29
AA16
AA17
AB16
AB19
AC16
AC17
AC19
AD15
AD16
AD17
AF16
AF19
AH15
AH16
AH17
AH19
AJ16
AJ17
AJ19
AK16
AK19
AL16
AL17
AL19
AL20
AL21
AL23
AM15
AM16
AM19
AM20
AM21
AM23
AP15
AP16
AP17
AP19
AP20
AP21
AP23
AP24
AR20
AR21
AR23
AR24
AR26
V26
V28
V29
Y31

AW45
BC39
BE39
BD17
BD4
AW8
AT6

+1.05V_VCCP

VCCSM_LF1
VCCSM_LF2
VCCSM_LF3
VCCSM_LF4
VCCSM_LF5
VCCSM_LF6
VCCSM_LF7

220U_D2_4VY_R15M~D

220U_D2_4VY_R15M~D

1

C599

+

2

0.1U_0402_10V7K~D

C610

1

1

2

2

0.22U_0402_10V4Z~D

C623

C622

1

1

2

2

Layout Note:
370 mils from edge.

C611

0.22U_0402_10V4Z~D

1

C598

+

2

1U_0603_10V4Z~D

0.47U_0402_10V4Z~D

C609

1

2

Layout Note: Inside GMCH
cavity for VCC_AXG.

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

C621

1

2

0.1U_0402_10V7K~D

10U_0805_10V4Z~D

22U_0805_6.3VAM~D

C612

1

1

1

C600

C601

2

2

2

0.47U_0402_10V4Z~D

C624

1

1

2

2

1U_0402_6.3V4Z~D

1U_0402_6.3V4Z~D

C627

C626

C625

1

1

2

2

A A

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

Crestline(5 of 6)

LA-3301P

14 58Wednesday, February 28, 2007

1

1.0

of

5

U29I

A13

VSS_1

A15

VSS_2

A17

VSS_3

A24

VSS_4

AA21

VSS_5

AA24

VSS_6

AA29

VSS_7

AB20

VSS_8

AB23

D D

C C

B B

AB26
AB28
AB31
AC10
AC13

AC39
AC43
AC47

AD21
AD26
AD29

AD41
AD45
AD49

AD50
AE10

AE14
AF20

AF23
AF24
AF31

AG2
AG38
AG43
AG47
AG50

AH40
AH41

AJ11
AJ13
AJ21
AJ24
AJ29
AJ32
AJ43
AJ45

AJ49
AK20
AK21
AK26
AK28
AK31
AK51

AM11
AM13

AM3

AM4
AM41
AM45

AN38
AN39
AN43

AP48
AP50
AR11

AR39
AR44
AR47

AT10
AT14
AT41
AT49

AU23
AU29

AU36
AU49
AU51
AV39
AV48

AW1
AW12
AW16

VSS_9
VSS_10
VSS_11
VSS_12
VSS_13
VSS_14

AC3

VSS_15
VSS_16
VSS_17
VSS_18

AD1

VSS_19
VSS_20
VSS_21
VSS_22

AD3

VSS_23
VSS_24
VSS_25
VSS_26

AD5

VSS_27
VSS_28

AD8

VSS_29
VSS_30
VSS_31

AE6

VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41

AH3

VSS_42
VSS_43
VSS_44

AH7

VSS_45

AH9

VSS_46
VSS_47
VSS_48
VSS_49
VSS_50
VSS_51
VSS_52
VSS_53
VSS_54
VSS_55
VSS_56
VSS_57
VSS_58
VSS_59
VSS_60
VSS_61

AL1

VSS_62
VSS_63
VSS_64
VSS_65
VSS_66
VSS_67
VSS_68

AN1

VSS_69
VSS_70
VSS_71
VSS_72

AN5

VSS_73

AN7

VSS_74

AP4

VSS_75
VSS_76
VSS_77
VSS_78

AR2

VSS_79
VSS_80
VSS_81
VSS_82

AR7

VSS_83
VSS_84
VSS_85
VSS_86
VSS_87

AU1

VSS_88
VSS_89
VSS_90

AU3

VSS_91
VSS_92
VSS_93
VSS_94
VSS_95
VSS_96
VSS_97
VSS_98
VSS_99

VSS

LE88CLGM A0 QM20_FCBGA1299~D

VSS_100
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105
VSS_106
VSS_107
VSS_108
VSS_109
VSS_110
VSS_111
VSS_112
VSS_113
VSS_114
VSS_115
VSS_116
VSS_117
VSS_118
VSS_119
VSS_120
VSS_121
VSS_122
VSS_123
VSS_124
VSS_125
VSS_126
VSS_127
VSS_128
VSS_129
VSS_130
VSS_131
VSS_132
VSS_133
VSS_134
VSS_135
VSS_136
VSS_137
VSS_138
VSS_139
VSS_140
VSS_141
VSS_142
VSS_143
VSS_144
VSS_145
VSS_146
VSS_147
VSS_148
VSS_149
VSS_150
VSS_151
VSS_152
VSS_153
VSS_154
VSS_155
VSS_156
VSS_157
VSS_158
VSS_159
VSS_160
VSS_161
VSS_162
VSS_163
VSS_164
VSS_165
VSS_166
VSS_167
VSS_168
VSS_169
VSS_170
VSS_171
VSS_172
VSS_173
VSS_174
VSS_175
VSS_176
VSS_177
VSS_178
VSS_179
VSS_180
VSS_181
VSS_182
VSS_183
VSS_184
VSS_185
VSS_186
VSS_187
VSS_188
VSS_189
VSS_190
VSS_191
VSS_192
VSS_193
VSS_194
VSS_195
VSS_196
VSS_197
VSS_198

AW24
AW29
AW32
AW5
AW7
AY10
AY24
AY37
AY42
AY43
AY45
AY47
AY50
B10
B20
B24
B29
B30
B35
B38
B43
B46
B5
B8
BA1
BA17
BA18
BA2
BA24
BB12
BB25
BB40
BB44
BB49
BB8
BC16
BC24
BC25
BC36
BC40
BC51
BD13
BD2
BD28
BD45
BD48
BD5
BE1
BE19
BE23
BE30
BE42
BE51
BE8
BF12
BF16
BF36
BG19
BG2
BG24
BG29
BG39
BG48
BG5
BG51
BH17
BH30
BH44
BH46
BH8
BJ11
BJ13
BJ38
BJ4
BJ42
BJ46
BK15
BK17
BK25
BK29
BK36
BK40
BK44
BK6
BK8
BL11
BL13
BL19
BL22
BL37
BL47
C12
C16
C19
C28
C29
C33
C36
C41

4

C46
C50

C7
D13
D24

D3
D32
D39
D45
D49
E10
E16
E24
E28
E32
E47
F19
F36

F4
F40
F50

G1
G13
G16
G19
G24
G28
G29
G33
G42
G45
G48

G8
H24
H28

H4
H45
J11
J16

J2
J24
J28
J33
J35
J39

K12
K47

K8

L1
L17
L20
L24
L28

L3
L33
L49

M28
M42
M46
M49

M5

M50

M9
N11
N14
N17
N29
N32
N36
N39
N44
N49

N7

P19

P2

P23

P3

P50

R49

T39
T43

T47
U41
U45
U50

V2
V3

U29J

VSS_199
VSS_200
VSS_201
VSS_202
VSS_203
VSS_204
VSS_205
VSS_206
VSS_207
VSS_208
VSS_209
VSS_210
VSS_211
VSS_212
VSS_213
VSS_214
VSS_215
VSS_216
VSS_217
VSS_218
VSS_219
VSS_220
VSS_221
VSS_222
VSS_223
VSS_224
VSS_225
VSS_226
VSS_227
VSS_228
VSS_229
VSS_230
VSS_231
VSS_232
VSS_233
VSS_234
VSS_235
VSS_236
VSS_237
VSS_238
VSS_239
VSS_240
VSS_241
VSS_242
VSS_243

VSS_245
VSS_246
VSS_247
VSS_248
VSS_249
VSS_250
VSS_251
VSS_252
VSS_253
VSS_254
VSS_255
VSS_256
VSS_257
VSS_258
VSS_259
VSS_260
VSS_261
VSS_262
VSS_263
VSS_264
VSS_265
VSS_266
VSS_267
VSS_268
VSS_269
VSS_270
VSS_271
VSS_272
VSS_273
VSS_274
VSS_275
VSS_276
VSS_277
VSS_278
VSS_279
VSS_280
VSS_281
VSS_282
VSS_283
VSS_284
VSS_285
VSS_286

LE88CLGM A0 QM20_FCBGA1299~D

VSS

3

W11

VSS_287

W39

VSS_288

W43

VSS_289

W47

VSS_290

W5

VSS_291

W7

VSS_292

Y13

VSS_293

Y2

VSS_294

Y41

VSS_295

Y45

VSS_296

Y49

VSS_297

Y5

VSS_298

Y50

VSS_299

Y11

VSS_300

P29

VSS_301

T29

VSS_302

T31

VSS_303

T33

VSS_304

R28

VSS_305

AA32

VSS_306

AB32

VSS_307

AD32

VSS_308

AF28

VSS_309

AF29

VSS_310

AT27

VSS_311

AV25

VSS_312

H50

VSS_313

2

1

A A

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

Crestline(6 of 6)

LA-3301P

15 58Wednesday, February 14, 2007

1

1.0

of

5

DDR_A_DQS#[0..7]11

DDR_A_D[0..63]11
DDR_A_DM[0..7]11
DDR_A_DQS[0..7]11

DDR_A_MA[0..14]11

D D

+1.8V_SUS

2.2U_0603_6.3V6K~D

2.2U_0603_6.3V6K~D
C133

1

2

0.1U_0402_16V4Z~D

C C

+0.9V_DDR_VTT

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

B B

A A

1

1

2

2

C137

C136

DDR_A_MA1
DDR_A_MA3

56_0404_4P2R_5%~D

DDR_A_BS0
DDR_A_MA10

56_0404_4P2R_5%~D

DDR_A_RAS#
DDR_CS0_DIMMA#

56_0404_4P2R_5%~D

DDR_A_CAS#
DDR_A_WE#

56_0404_4P2R_5%~D

M_ODT1
DDR_CS1_DIMMA#

56_0404_4P2R_5%~D

DDR_CKE1_DIMMA

DDR_CKE0_DIMMA
DDR_A_BS2

56_0404_4P2R_5%~D

0.1U_0402_16V4Z~D

1

2

C138

5

2.2U_0603_6.3V6K~D

C132

C437

1

1

2

2

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D
C131

C130

1

1

2

2

Layout Note:
Place one cap close to every 2 pullup
resistors terminated to +0.9V_DDR_VTT

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

1

1

2

2

C139

C140

+0.9V_DDR_VTT

RN4

1 4
2 3

RN3

1 4
2 3

RN9

1 4
2 3

RN2

1 4
2 3

RN1

1 4
2 3

12

R223
56_0402_5%~D

RN7

2 3
1 4

2.2U_0603_6.3V6K~D

1

2

1

2

C141

C119

RN6

RN12

RN5

RN11

RN10

RN8

RN13

C117

1

2

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

1

2

C104

2.2U_0603_6.3V6K~D

1

2

14
23

56_0404_4P2R_5%~D

14
23

56_0404_4P2R_5%~D

14
23

56_0404_4P2R_5%~D

14
23

56_0404_4P2R_5%~D

14
23

56_0404_4P2R_5%~D

14
23

56_0404_4P2R_5%~D

14
23

56_0404_4P2R_5%~D

C116

1

2

C118

0.1U_0402_16V4Z~D

1

2

C105

DDR_A_MA9
DDR_A_MA12

DDR_A_MA7
DDR_A_MA6

DDR_A_MA5
DDR_A_MA8

DDR_A_MA4
DDR_A_MA2

DDR_A_MA0
DDR_A_BS1

M_ODT0
DDR_A_MA13

DDR_A_MA14
DDR_A_MA11

0.1U_0402_16V4Z~D

Layout Note:
Place near JDIM1

0.1U_0402_16V4Z~D

1

1

2

2

C107

C106

4

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

1

1

2

2

C109

C108

Layout Note:
Place these resistor
closely DIMM0,all
trace length<750 mil

Layout Note:
Place these resistor
closely DIMM0,all
trace length
Max=1.3"

4

3

+1.8V_SUS +1.8V_SUS

ON TOP SIDE

JDIM2

1

VREF

3

2.2U_0603_6.3V6K~D
C115

VSS

5

DQ0

7

DQ1

9

VSS

11

DQS0#

13

DQS0

15

VSS

17

DQ2

19

DQ3

21

VSS

23

DQ8

25

DQ9

27

VSS

29

DQS1#

31

DQS1

33

VSS

35

DQ10

37

DQ11

39

VSS

41

VSS

43

DQ16

45

DQ17

47

VSS

49

DQS2#

51

DQS2

53

VSS

55

DQ18

57

DQ19

59

VSS

61

DQ24

63

DQ25

65

VSS

67

DM3

69

NC

71

VSS

73

DQ26

75

DQ27

77

VSS

79

CKE0

81

VDD

83

NC

85

BA2

87

VDD

89

A12

91

A9

93

A8

95

VDD

97

A5

99

A3

101

A1

103

VDD

105

A10/AP

107

BA0

109

WE#

111

VDD

113

CAS#

115

NC/S1#

117

VDD

119

NC/ODT1

121

VSS

123

DQ32

125

DQ33

127

VSS

129

DQS4#

131

DQS4

133

VSS

135

DQ34

137

DQ35

139

VSS

141

DQ40

143

DQ41

145

VSS

147

DM5

149

VSS

151

DQ42

153

DQ43

155

VSS

157

DQ48

159

DQ49

161

VSS

163

NC,TEST

165

VSS

167

DQS6#

169

DQS6

171

VSS

173

DQ50

175

DQ51

177

VSS

179

DQ56

181

DQ57

183

VSS

185

DM7

187

VSS

189

DQ58

191

DQ59

193

VSS

195

SDA

197

SCL

199

VDDSPD

201

GND

TYCO_1470815-2~D

RESERVE

DDR_A_D0
DDR_A_D5

DDR_A_DQS#0
DDR_A_DQS0

DDR_A_D3
DDR_A_D7

DDR_A_D13
DDR_A_D12

DDR_A_DQS#1
DDR_A_DQS1

DDR_A_D10

DDR_A_D17
DDR_A_D21

DDR_A_DQS#2
DDR_A_DQS2

DDR_A_D22
DDR_A_D23

DDR_A_D29

DDR_A_DM3

DDR_A_D27

DDR_A_D30

DDR_CKE0_DIMMA10

DDR_A_BS211

DDR_A_BS011
DDR_A_WE#11

DDR_A_CAS#11

DDR_CS1_DIMMA#10

M_ODT110

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

1

1

2

2

C707

C110

MEM_SDATA17,23
MEM_SCLK17,23

Non-iAMT

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

DDR_CKE0_DIMMA

DDR_A_BS2
DDR_A_MA12

DDR_A_MA9 DDR_A_MA7
DDR_A_MA8

DDR_A_MA5
DDR_A_MA3
DDR_A_MA1

DDR_A_MA10
DDR_A_BS0
DDR_A_WE#

DDR_A_CAS#
DDR_CS1_DIMMA#

M_ODT1
DDR_A_D33

DDR_A_D32
DDR_A_DQS#4

DDR_A_DQS4
DDR_A_D34

DDR_A_D39
DDR_A_D41

DDR_A_D40
DDR_A_DM5
DDR_A_D46

DDR_A_D43 DDR_A_D47
DDR_A_D49 DDR_A_D48

DDR_A_D52

DDR_A_DQS#6
DDR_A_DQS6

DDR_A_D51

DDR_A_D60
DDR_A_D56

DDR_A_DM7
DDR_A_D58

MEM_SDATA
MEM_SCLK

+3.3V_RUN

0.1U_0402_16V4Z~D
C113

1

1

2

2

NC/CKE1

DIMMA

2

VSS
DQ4
DQ5
VSS
DM0
VSS
DQ6
DQ7

VSS
DQ12
DQ13

VSS

DM1

VSS

CK0#

VSS
DQ14
DQ15

VSS

VSS
DQ20
DQ21

VSS

DM2

VSS
DQ22
DQ23

VSS
DQ28
DQ29

VSS

DQS3#

DQS3

VSS
DQ30
DQ31

VSS

VDD

NC/A15
NC/A14

VDD

VDD

VDD

RAS#

VDD
ODT0

NC/A13

VDD

VSS
DQ36
DQ37

VSS

DM4

VSS
DQ38
DQ39

VSS
DQ44
DQ45

VSS

DQS5#

DQS5

VSS
DQ46
DQ47

VSS
DQ52
DQ53

VSS

CK1#

VSS

DM6

VSS
DQ54
DQ55

VSS
DQ60
DQ61

VSS

DQS7#

DQS7

VSS
DQ62
DQ63

VSS

SAO

GND

2

1

V_DDR_MCH_REF

2

DDR_A_D4

4

DDR_A_D6

6
8

DDR_A_DM0

10
12

DDR_A_D1

14

DDR_A_D2

16
18

DDR_A_D9

20

DDR_A_D8

22
24

DDR_A_DM1

26
28

M_CLK_DDR0

30

CK0

NC

A11

A7
A6

A4
A2

A0
BA1
S0#

NC

CK1

SA1

M_CLK_DDR#0

32
34

DDR_A_D15

36

DDR_A_D14DDR_A_D11

38
40

42

DDR_A_D20

44

DDR_A_D16

46
48

PM_EXTTS#0

50

DDR_A_DM2

52
54

DDR_A_D18

56

DDR_A_D19

58
60

DDR_A_D28

62

DDR_A_D24DDR_A_D25

64
66

DDR_A_DQS#3

68

DDR_A_DQS3

70
72

DDR_A_D26

74

DDR_A_D31

76
78

DDR_CKE1_DIMMA

80
82
84

DDR_A_MA14

86
88

DDR_A_MA11

90
92

DDR_A_MA6

94
96

DDR_A_MA4

98

DDR_A_MA2

100

DDR_A_MA0

102
104

DDR_A_BS1

106

DDR_A_RAS#

108

DDR_CS0_DIMMA#

110
112

M_ODT0

114

DDR_A_MA13

116
118
120
122

DDR_A_D36

124

DDR_A_D37

126
128

DDR_A_DM4

130
132

DDR_A_D35

134

DDR_A_D38

136
138

DDR_A_D44

140

DDR_A_D45

142
144

DDR_A_DQS#5

146

DDR_A_DQS5

148
150

DDR_A_D42

152
154
156
158

DDR_A_D53

160
162

M_CLK_DDR1

164

M_CLK_DDR#1

166
168

DDR_A_DM6

170
172

DDR_A_D50

174

DDR_A_D55DDR_A_D54

176
178

DDR_A_D61

180

DDR_A_D57

182
184

DDR_A_DQS#7

186

DDR_A_DQS7

188
190

DDR_A_D59DDR_A_D62

192

DDR_A_D63

194
196

R122 10K_0402_5%~D

198
200

202

1 2

R127 10K_0402_5%~D

1 2

V_DDR_MCH_REF

2.2U_0603_6.3V6K~D

1

C114

2

M_CLK_DDR0 10

M_CLK_DDR#0 10

PM_EXTTS#0 10

DDR_CKE1_DIMMA 10

DDR_A_BS1 11

DDR_A_RAS# 11
DDR_CS0_DIMMA# 10

M_ODT0 10

M_CLK_DDR1 10

M_CLK_DDR#1 10

0.1U_0402_16V4Z~D

1

C112

2

DELL CONFIDENTIAL/PROPRIETARY

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

DDRII-SODIMM SLOT1

LA-3301P

16 58Monday, February 26, 2007

1

1.0

of

5

DDR_B_DQS#[0..7]11

DDR_B_D[0..63]11
DDR_B_DM[0..7]11
DDR_B_DQS[0..7]11

DDR_B_MA[0..14]11

D D

C C

B B

A A

+1.8V_SUS

+0.9V_DDR_VTT

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

1

2

C456

DDR_B_MA1
DDR_B_MA3

56_0404_4P2R_5%~D

DDR_B_BS0
DDR_B_MA10

56_0404_4P2R_5%~D

DDR_B_MA0
DDR_B_BS1

56_0404_4P2R_5%~D

DDR_B_RAS#
DDR_CS2_DIMMB#

56_0404_4P2R_5%~D

DDR_B_CAS#
DDR_B_WE#

56_0404_4P2R_5%~D

DDR_CKE3_DIMMB

DDR_CS3_DIMMB#
M_ODT3

56_0404_4P2R_5%~D

2.2U_0603_6.3V6K~D
C439

1

2

0.1U_0402_16V4Z~D

C434

1

2

Layout Note:
Place one cap close to every 2 pullup
resistors terminated to +0.9V_DDR_VTT

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

1

1

2

2

C454

C455

+0.9V_DDR_VTT

RN23

1 4
2 3

RN24

1 4
2 3

RN17

1 4
2 3

RN18

1 4
2 3

RN25

1 4
2 3

12

R312
56_0402_5%~D

RN26

2 3
1 4

5

C412

C440

1

2

0.1U_0402_16V4Z~D

1

2

0.1U_0402_16V4Z~D

1

2

C453

C433

RN21

RN14

RN22

RN15

RN16

RN19

RN20

1

2

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

1

2

C452

1

2

C413

1

2

1

2

C451

DDR_B_MA9

14

DDR_B_MA12

23

56_0404_4P2R_5%~D

DDR_B_MA14

14

DDR_B_MA11

23

56_0404_4P2R_5%~D

DDR_B_MA5

14

DDR_B_MA8

23

56_0404_4P2R_5%~D

DDR_B_MA7

14

DDR_B_MA6

23

56_0404_4P2R_5%~D

DDR_B_MA4

14

DDR_B_MA2

23

56_0404_4P2R_5%~D

M_ODT2

14

DDR_B_MA13

23

56_0404_4P2R_5%~D

DDR_B_BS2

14

DDR_CKE2_DIMMB

23

56_0404_4P2R_5%~D

2.2U_0603_6.3V6K~D

2.2U_0603_6.3V6K~D

2.2U_0603_6.3V6K~D

2.2U_0603_6.3V6K~D

C438

1

2

0.1U_0402_16V4Z~D
C414

1

2

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

1

2

C450

Layout Note:
Place near JDIM2

C411

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

1

1

2

2

C410

C409

4

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

1

2

C408

Layout Note:
Place these resistor
closely DIMM0,all
trace length<750 mil

Layout Note:
Place these resistor
closely DIMM0,all
trace length
Max=1.3"

0.1U_0402_16V4Z~D

1

1

2

2

C406

C407

4

3

ON BOTTOM SIDE

DDR_B_D0
DDR_B_DQS#0

DDR_B_DQS0
DDR_B_D6

DDR_B_D7
DDR_B_D8

DDR_B_D9
DDR_B_DQS#1

DDR_B_DQS1
DDR_B_D14

DDR_B_D15

DDR_B_D16
DDR_B_D21

DDR_B_DQS#2
DDR_B_DQS2

DDR_B_D19
DDR_B_D18

DDR_B_D24 DDR_B_D28
DDR_B_D25

DDR_B_DM3

DDR_B_D26
DDR_B_D27

DDR_CKE2_DIMMB10

DDR_B_BS211

DDR_B_BS011
DDR_B_WE#11

DDR_B_CAS#11

DDR_CS3_DIMMB#10

1

2

C405

M_ODT310

MEM_SDATA16,23
MEM_SCLK16,23

Non-iAMT

DDR_CKE2_DIMMB

DDR_B_BS2
DDR_B_MA12

DDR_B_MA9
DDR_B_MA8

DDR_B_MA5
DDR_B_MA3
DDR_B_MA1

DDR_B_MA10
DDR_B_BS0
DDR_B_WE#

DDR_B_CAS#
DDR_CS3_DIMMB#

M_ODT3

DDR_B_D36
DDR_B_DQS#4

DDR_B_DQS4

DDR_B_D34
DDR_B_D40

DDR_B_D41
DDR_B_DM5

DDR_B_D42
DDR_B_D53

DDR_B_D49 DDR_B_D48

DDR_B_DQS#6
DDR_B_DQS6

DDR_B_D55
DDR_B_D50

DDR_B_D56
DDR_B_D60

DDR_B_DM7
DDR_B_D58

DDR_B_D59
MEM_SDATA

MEM_SCLK

+3.3V_RUN

2.2U_0603_6.3V6K~D

0.1U_0402_16V4Z~D

C431

1

1

2

2

C429

JDIM1

1

VREF

3

VSS

5

DQ0

7

DQ1

9

VSS

11

DQS0#

13

DQS0

15

VSS

17

DQ2

19

DQ3

21

VSS

23

DQ8

25

DQ9

27

VSS

29

DQS1#

31

DQS1

33

VSS

35

DQ10

37

DQ11

39

VSS

41

VSS

43

DQ16

45

DQ17

47

VSS

49

DQS2#

51

DQS2

53

VSS

55

DQ18

57

DQ19

59

VSS

61

DQ24

63

DQ25

65

VSS

67

DM3

69

NC

71

VSS

73

DQ26

75

DQ27

77

VSS

79

CKE0

81

VDD

83

NC

85

BA2

87

VDD

89

A12

91

A9

93

A8

95

VDD

97

A5

99

A3

101

A1

103

VDD

105

A10/AP

107

BA0

109

WE#

111

VDD

113

CAS#

115

NC/S1#

117

VDD

119

NC/ODT1

121

VSS

123

DQ32

125

DQ33

127

VSS

129

DQS4#

131

DQS4

133

VSS

135

DQ34

137

DQ35

139

VSS

141

DQ40

143

DQ41

145

VSS

147

DM5

149

VSS

151

DQ42

153

DQ43

155

VSS

157

DQ48

159

DQ49

161

VSS

163

NC,TEST

165

VSS

167

DQS6#

169

DQS6

171

VSS

173

DQ50

175

DQ51

177

VSS

179

DQ56

181

DQ57

183

VSS

185

DM7

187

VSS

189

DQ58

191

DQ59

193

VSS

195

SDA

197

SCL

199

VDDSPD

201

GND

TYCO_1565917-4~D

DIMMB

STANDARD

DQ4
DQ5

DM0
DQ6

DQ7

DQ12
DQ13

DM1

CK0#
DQ14

DQ15

DQ20
DQ21

DM2

DQ22
DQ23

DQ28
DQ29

DQS3#

DQS3

DQ30
DQ31

NC/CKE1

VDD
NC/A15
NC/A14

VDD

VDD

VDD

RAS#

VDD

ODT0

NC/A13

VDD

DQ36
DQ37

DM4

DQ38
DQ39

DQ44
DQ45

DQS5#

DQS5

DQ46
DQ47

DQ52
DQ53

CK1#

DM6

DQ54
DQ55

DQ60
DQ61

DQS7#

DQS7

DQ62
DQ63

SAO

GND

VSS

VSS
VSS

VSS

VSS
VSS

CK0
VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

BA1

VSS

VSS
VSS

VSS

VSS

VSS

VSS

VSS
CK1

VSS
VSS

VSS

VSS

VSS

VSS
SA1

NC

A11

A7
A6

A4
A2
A0

S0#

NC

2

+1.8V_SUS+1.8V_SUS V_DDR_MCH_REF

2

DDR_B_D5

4

DDR_B_D4DDR_B_D1

6
8

DDR_B_DM0

10
12

DDR_B_D2

14

DDR_B_D3

16
18

DDR_B_D13

20

DDR_B_D12

22
24

DDR_B_DM1

26
28

M_CLK_DDR2

30

M_CLK_DDR#2

32
34

DDR_B_D10

36

DDR_B_D11

38
40

42

DDR_B_D20

44

DDR_B_D17

46
48

PM_EXTTS#1

50

DDR_B_DM2

52
54

DDR_B_D22

56

DDR_B_D23

58
60
62

DDR_B_D29

64
66

DDR_B_DQS#3

68

DDR_B_DQS3

70
72

DDR_B_D30

74

DDR_B_D31

76
78

DDR_CKE3_DIMMB

80
82
84

DDR_B_MA14

86
88

DDR_B_MA11

90

DDR_B_MA7

92

DDR_B_MA6

94
96

DDR_B_MA4

98

DDR_B_MA2

100

DDR_B_MA0

102
104

DDR_B_BS1

106

DDR_B_RAS#

108

DDR_CS2_DIMMB#

110
112

M_ODT2

114

DDR_B_MA13

116
118
120
122

DDR_B_D33DDR_B_D32

124

DDR_B_D37

126
128

DDR_B_DM4

130
132

DDR_B_D38

134

DDR_B_D39DDR_B_D35

136
138

DDR_B_D44

140

DDR_B_D45

142
144

DDR_B_DQS#5

146

DDR_B_DQS5

148
150

DDR_B_D43DDR_B_D46

152

DDR_B_D47

154
156

DDR_B_D52

158
160
162

M_CLK_DDR3

164

M_CLK_DDR#3

166
168

DDR_B_DM6

170
172

DDR_B_D54

174

DDR_B_D51

176
178

DDR_B_D57

180

DDR_B_D61

182
184

DDR_B_DQS#7

186

DDR_B_DQS7

188
190

DDR_B_D62

192

DDR_B_D63

194
196
198
200

202

10K_0402_5%~D

12

M_CLK_DDR2 10

M_CLK_DDR#2 10

DDR_CKE3_DIMMB 10

DDR_B_BS1 11

DDR_B_RAS# 11
DDR_CS2_DIMMB# 10

M_ODT2 10

M_CLK_DDR3 10

M_CLK_DDR#3 10

R243

10K_0402_5%~D

R241

V_DDR_MCH_REF

2.2U_0603_6.3V6K~D

1

C447

2

PM_EXTTS#1 10

+3.3V_RUN

12

1

0.1U_0402_16V4Z~D

1

C436

2

Non-iAMT

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

DDRII-SODIMM SLOT2

LA-3301P

17 58Monday, February 26, 2007

1

1.0

of

5

+3.3V_SUS

12

R423

8.2K_0402_5%~D

2

Q38

2

Q39

B

+3.3V_SUS

B

C

E

3 1

12

C

E

3 1

THERMATRIP1#

1

C628

0.1U_0402_16V4Z~D

2

R426

8.2K_0402_5%~D

THERMATRIP2#

1

C632

0.1U_0402_16V4Z~D

2

+1.05V_VCCP

R425

D D

H_THERMTRIP#7

THERMTRIP_MCH#10

2.2K_0402_5%~D

1 2

MMST3904-7-F_SOT323-3~D

+1.05V_VCCP

R427

2.2K_0402_5%~D

1 2

MMST3904-7-F_SOT323-3~D

Place under CPU

C C

C633

@

2200P_0402_50V7K~D

Place C633 close to the Q40 as possible

Place C636 close to the Guardian pins as possible

H_THERMDA7

470P_0402_50V7K~D

H_THERMDC7

+3.3V_SUS

B B

+3.3V_SUS

R196

@

1 2

10K_0402_5%~D

@

1 2

10K_0402_5%~D

A A

R194

MDC_RST_DIS#

SIO_GFX_PWR

5

+3.3V_SUS

0.1U_0402_16V4Z~D

R428

1 2

49.9_0603_1%~D

1

C639

2

C100

2200P_0402_50V7K~D

2

1

C636

1

C637

0.1U_0402_16V4Z~D

2

2

1

+3.3V_SUS

12

C

R433

8.2K_0402_5%~D

THERMATRIP3#

4

RB751S40T1_SOD523-2~D

2

B

E

Q40

3 1

MMST3904-7-F_SOT323-3~D

1

2

+RTC_CELL

12

R436
332K_0402_1%~D

12

R438
118K_0402_1%~D

4

D19

@

+3VSUS_THRM

1

C638

2

0.1U_0402_16V4Z~D

1

C203

0.1U_0402_16V4Z~D

2

@

1

C630

2

2 1

2200P_0402_50V7K~D

2

C634

1

SUSPWROK42
ICH_PWRGD#42

R437

1 2

1K_0402_5%~D

MDC_RST_DIS#33

AUDIO_AVDD_ON27

3

FAN1 Control and Tachometer

+3.3V_RUN

12

R424
10K_0402_5%~D

12

R414
0_0402_5%~D

+FAN1_VOUT

22U_0805_6.3VAM~D

Place C634 close to the
Guardian pins as possible

FAN1_TACH_FB

THRM_SMBDAT39,49
THRM_SMBCLK39,49

REM_DIODE1_N

1 2

R429 1K_0402_5%~D

1 2

R432 1K_0402_5%~D

THERMATRIP1#
THERMATRIP2#
THERMATRIP3#

+FAN1_VOUT

MDC_RST_DIS#
SIO_GFX_PWR
5V_CAL_SIO#

AUDIO_AVDD_ON

FAN1_TACH 39

11
12

38
37

41
40

35
21
23
16
17
18
19
42
26
34

7
8

39

10
13
14
15
22
36
49

SMBUS ADDRESS : 2F

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

JFAN1

1

1

2

2

3

3

MOLEX_53398-0371~D

U31

SMDATA
SMBCLK

DP1
DN1

DP2
DN2

3V_SUS
RTC_PWR3V
VSUS_PWRGD
3V_PWROK#
THERMTRIP1#
THERMTRIP2#
THERMTRIP3#
VSET
XEN
VSS
FAN_OUT

FAN_OUT
FAN_DAC1

GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6/FAN_DAC2
PAD_GND

VCP1
VCP2

ATF_INT#

POWER_SW#

ACAVAIL_CLR

THERMTRIP_SIO

SYS_SHDN#

LDO_SHDN#/ADDR

LDO_POK
LDO_SET
LDO_OUT

LDO_OUT

LDO_IN
LDO_IN

VDD_3V
VDD_5V

VDD_5V

EMC4001_QFN48~D

1

C645

2

10U_0805_10V4Z~D

DP3
DN3

DP4
DN4

DP5
DN5

43
46

45
44

48
47

2
1

20
3
4
25
24
27
33
28
32

31

30
29

9
5

6

1

C646

2

VCP2

VCP2
REM_DIODE3_PREM_DIODE1_P

REM_DIODE3_N
REM_DIODE4_P

REM_DIODE4_N

7.5K_0402_5%~D

LDO_SET

+3V_LDOIN

+5V_RUN

0.1U_0402_16V4Z~D

2

VSET=

VSET =

+5V_SUS

12

R771

2.21K_0603_1%~D

1

C750

2

2200P_0402_50V7K~D

PWR_MON 48

Place cap close to the
Guardian pins as possible.

1

C649
2200P_0402_50V7K~D

2

1

C418

2

2200P_0402_50V7K~D

ATF_INT#

ATF_INT# 38

POWER_SW# 39,40

ACAV_IN 39,49,50

R434

12

+3.3V_SUS

1

1

10U_0805_10V4Z~D

1U_0603_10V4Z~D

10U_0805_10V4Z~D

2

1

2

1

2

@

0.1U_0402_16V4Z~D

2

1

C644

0.1U_0402_16V4Z~D

2

1

C648

0.1U_0402_16V4Z~D

2

C640

@

C643

C647

2

1

R438

x 3.3V

=0.865V

R436+R438

Tp-70

=> Tp = 88.2 C

21

12

R772
10K_0603_1%_TSM1A103F34D3RZ~D

Q102

13

D

2N7002W-7-F_SOT323-3~D

2

G

S

This thermistor circuit is located near
Top side DDR connector.

REM_DIODE3_N, REM_DIODE3_P routing together.
Trace width / Spacing = 10 / 10 mil

C

Q41

2

B

MMST3904-7-F_SOT323-3~D

E

2

B

E

R96
10K_0402_5%~D

10K_0402_5%~D

R431

@

+2.5V_RUN

R439

12

+3.3V_RUN

3 1

C

Q19
MMST3904-7-F_SOT323-3~D

3 1

12

R430

10K_0402_5%~D

+3.3V_RUN

Q41 Place near the
bottom SODIMM

C641

0_1210_5%~D

+3.3V_SUS

12

R773
10K_0402_5%~D

5V_CAL_SIO#

1

C650
2200P_0402_50V7K~D

2

@

Place C650
close to Q41

1

C904

@

2200P_0402_50V7K~D

2

Diode circui t at DP4/DN4 is
used for skin temp sensor
(placed optim ally between

+3.3V_SUS

CPU, MCH and MEM).

12

+3.3V_ALW

THERMTRIP_SIO
THERM_STP# 45

12

+RTC_CELL

2.5V_RUN_PWRGD 42

LDO_SET

Voltage margining
circuit for LDO output.
For Vmargin, stuff
Ra=31.6K and Rb=30K.
Rb=1K for production

DELL CONFIDENTIAL/PROPRIETARY

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

FAN & Thermal Sensor

LA-3301P

1

+2.5V_RUN

12

12

18 58Wednesday, March 07, 2007

31.6K_0402_1%~D

@

R485

Ra

1K_0402_1%~D

R441

Rb

1.0

of