Compal LA-3301P, Latitude D630 Schematic

A

B

COMPAL CONFIDENTIAL

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E

1 1

PCB NO :
BOM P/N :

2 2

LA-3301P (DA80000771L)
45144631L01

MODEL NAME :

IBQ00

M08 (UMA) Briscoe

uFCPGA Mobile Merom
Intel Crestline + ICH8M

2007-03-07

3 3

REV : 1.0 (A00)

DAZ P/N:DAZZGX0010L

MB PCB

Part Number Description

PCB1

LS-3301P REV1 LED/B
PCB1

4 4

LS-3302P I/O Board

DA80000771L

IBQ00
LS-3301P REV1
LED/B

IBQ00
LS-3302P REV1
IO/B

PCB ZGX LA-3301P
REV1 M/B UMA

BOM NO. 45144631L01
PCB P/N: DA80000771L

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

A

B

C

D

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

Cover Sheet
LA-3301P

158Wednesday, March 07, 2007

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Block Diagram
Compal confidential
Model : IBQ00

FAN

1 1

+FAN1_VOUT

page 18

RGB

DVI

TV

Thermal

GUARDIAN III
EMC4001

+3.3V_SUS

CRT CONN

+5V_RUN

LVDS CONN

on M/B Board

DVI Bridge
SI1362A

page 18

page 20

page 19

page 51

RGB

LVDS
DVO

Pentium-M

Merom -4MB (Socket P)

+1.05V_VCCP
+VCC_CORE

H_A#(3..35) H_D#(0..63)

uFCPGA CPU

478pin

System Bus

FSB 800 MHz

page 7,8,9

INTEL

+1.25V_RUN
+1.5V_RUN
+1.8V_SUS
+1.05V_VCCP
+3.3V_RUN
+1.8V_RUN

Crestline

1299pin BGA

page 10,11,12,13,14,15

Memory BUS
(DDR2)

+1.8V_SUS 533 / 667MHz

USB[4]

CPU ITP Port

+1.05V_VCCP

Smart Card

OZ77CR6

+5V_RUN

page 31

Clock Generator

CK505

+3.3V_RUN

DDRII-DIMM X2

BANK 0, 1, 2, 3, 4 ,5 ,6 ,7 ,8

+0.9V_DDR_VTT
+1.8V_SUS

page6page 7

page 16,17

SLOT

2 2

PCI BUS

DOCKING
PORT

DOCK LPC BUS

PCI_PIRQA#
REQ#0
GNT#0

DOCKING
BUFFER

+5V_RUN

page 36 page 30

USB[8]

page 35

IDSEL:AD17
(PIRQD#,GNT#1,REQ#1)

CardBus

OZ711 LQFP

+3.3V_RUN

USB[6]

PCI Express BUS

Mini Card2

WLAN

3 3

+3.3V_WLAN

Mini Card 1

WWAN

+3.3V_RUN
+1.5V_RUN+1.5V_RUN

page 34page 34

USB[9]

PWR Sequence

page 42

ME & LED

page 43

DC IN

4 4

Battery IN

page 44

page 44

3V / 5V /15V

page 45

1.8V / 0.9V/1.25V

page 46

1.5V / 1.05V

page 47

Vccore

page 48

Charger

page 49

Battery Select

page 50

A

GIGA Enthernet
BCM5755M

+3.3V_LAN
+2.5V_LAN

+1.2V_LAN

RJ45

IO/B

page 28,29

B

+3VRUN 33MHz

IEEE1394

page 30

(+1.5V_RUN 100MHz)

DOCK LPC BUS

COM

+3.3V_SUS

page 37

Bluetooth

+3.3V_RUN

USB[7]

+3.3V_ALW

DMI

+1.5V_RUN
100MHz

+1.25V_RUN
+RTC_CELL
+3.3V_RUN
+3.3V_SUS
+1.5V_RUN
+1.05V_VCCP

+3VRUN
33MHz

SMSC SIO
ECE5028

page 38

ECE1077

+3.3V_ALW

page 37

Int.KBD &
Stick

page 40

Trough Cable

INTEL

ICH8-M

676pin BGA

page 21,22,23,24

page 21,22,23,24

LPC BUS

MEC5025

+RTC_CELL
+3.3V_ALW

page 40

Stick

Touch Pad

+5V_RUN

C

SPI

page 39

page 40

48MHz

SATA

S-HDD

+5V_HDD

SPI

ST M25P16

+3.3V_SUS

+3.3V_RUN

USB[5]

USB[2,3]

USB[0,1] SIDE

Azalia I/F

PATA

page 25 page 25 page 26

page 39

Biometric

page 40

REAR

SC_USB

D Moudle

+5V_MOD

+5V_RUN

D

USB Ports X2

+5V_SUS

page 32

USB Ports X2

+5V_SUS

IO/Board

Azalia Codec

STAC9205

+3.3V_RUN
+VDDA

AMP & INT.
Speaker

page 27 page 27

INT MIC

+VDDA

page 27

DELL CONFIDENTIAL/PROPRIETARY

Title

Size Document Number Rev

Date: Sheet

USB2 : Rear Left as viewed from the back,
USB3 Rear Right as viewed from the back

USB0 : side pair top,
USB1 : side pair bottom

MDC

+3.3V_SUS

page 33

Cable

RJ11

IO/B

HeadPhone
& MIC Jack

+3.3V_RUN

Compal Electronics, Inc.

Block Diagram
LA-3301P

258Wednesday, February 14, 2007

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2

1

POWER STATES

State

D D

S0 (Full ON) / M0

S3 (Suspend to RAM) / M1

S4 (Suspend to DISK) / M1 ON ON ON ONOFF

S5 (SOFT OFF) / M1 ON ON ON ONOFFLOW HIGH LOW HIGHLOW

S3 (Suspend to RAM) / M-OFF

S4 (Suspend to DISK) / M-OFF

S5 (SOFT OFF) / M-OFF

Signal

SLP

SLP

S3#

S4#

HIGH HIGH HIGH

HIGH

LOW HIGH HIGH HIGH ON ON ON ONOFF

LOW HIGH HIGH HIGHLOW

LOW HIGH HIGH HIGH LOW ON ONOFF OFF OFF

LOW LOW LOW LOW ON OFF OFF OFF OFF

LOW LOW LOW LOW LOW ON OFF OFF OFF OFF

SLP
S5#

HIGH

S4
STATE#

SLP
M#

HIGH

HIGH

ALWAYS
PLANE

ON

M
PLANE

ON

SUS

RUN

PLANE

PLANE

ON ON ON

CLOCKS

ICH8-M

USB PORT#

0
1
2
3
4
5
6
7

DESTINATION
Side Top
Side Bottom
Rear Left
Rear Right
Smart Card
Biometric
Card Bus
Bluetooth

C C

B B

PM TABLE

State

S0

S3

S5 S4/AC

S5 S4/AC don't exist

power
plane

+15V_ALW
+5V_ALW
+3.3V_ALW
+3.3V_RTC_LDO

ON

ON

+5V_SUS
+3.3V_SUS
+1.8V_SUS

ON ON

ON

OFF

OFFOFF

+5V_RUN
+3.3V_RUN
+2.5V_RUN
+1.8V_RUN
+1.5V_RUN
+0.9V_DDR_VTT
+VCC_CORE
+1.05V_VCCP
+1.25V_RUN

OFFON

OFF

OFF

ECE 5028

PCI EXPRESS

Lane 1
Lane 2

MINI CARD-1 WWAN
MINI CARD-2 WLAN

8
9
1
2
3
4

DESTINATION

Docking
WWAN
None
None
None
None

PCI TABLE

Lane 3

PCI DEVICE

OZ711

IDSEL

REQ#/GNT#

REQ#1 / GNT#1AD17 PIRQD

PIRQ

Lane 4
Lane 5
Lane 6

A A

AD24 REQ#0 / GNT#0

PIRQADocking

None
None
None
GIGA LAN

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

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2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

Index and Config.

LA-3301P

358Wednesday, February 14, 2007

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RUN_ON

FDS4435

(Q24)

+INV_PWR_SRC

ADAPTER

D D

+15V_ALW

SI4810DY

RUN_ON

SI4810DY

(Q58)

+3.3V_RUN

(Q52)

+5V_RUN

BATTERY

CHARGER

+PWR_SRC

ISL6260
(PU11) (PU22)

RUNPWROK

+VCC_CORE

DDR_ON

+1.8V_SUS

ISL6236

+1.25V_RUN

M_ON

ISL6236
(PU21)

1.05V_RUN_ON

+1.05V_VCCP

1.5V_RUN_ON

+1.5V_RUN

ISL6236
(PU20)

ALWON

ALWON

ENAB_3VLAN

+5V_ALW

+3.3V_ALW

RUN_ON

SI3456BDV

C C

SUS_ON

0.9V_DDR_VTT_ON

RUN_ON

(Q69)

+3.3V_LAN

+5V_SUS

+3.3V_SUS

TPS51100

(PU24)

SI3456BDV

(Q54)

REGCTL_PNP25

B B

BCP69 MMJT9435T1G

(Q70)

SI3456SI3456BDV

HDDC_EN#

+5V_HDD

A A

(Q48)(Q56)

MODC_EN#

+5V_MOD

MAX9789A

(U37)

AUDIO_AVDD_ON

+VDDA

+0.9V_DDR_VTT

+1.8VRUN

+2.5V_LAN +1.2V_LAN

REGCTL_PNP12

(Q71)

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

Power Rail
LA-3301P

458Wednesday, February 14, 2007

1

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5

AJ26

ICH_SMBCLK
ICH_SMBDATA

ICH8-M

D D

AD19

2.2K

2.2K

4

+3.3V_SUS

WWAN

SMBUS Address [TBD]

3

3032

C8C7

Intel LAN

SMBUS Address [TBD]

32 30

2N7002
2N7002

2N7002
2N7002

WLAN_SMBCLK
WLAN_SMBDATA

2.2K

2.2K

2

MEM_SCLK

MEM_SDATA

+3.3V_WLAN

WLAN

2.2K

2.2K

@ 0

+3.3V_RUN

197
195

DIMMA

197
195

DIMMB

CLK_SCLK@ 0

CLK_SDATA

1

SMBUS Address [TBD]

SMBUS Address [TBD]

SMBUS Address [TBD]

8.2K

8.2K

8

LCD_SMBCLK

7

C C

LCD_SMDATA

4.7K

4.7K

100

THRM_SMBCLK

99

THRM_SMBDAT

+3.3V_ALW

+3.3V_ALW

6

5
10
9
12
11

INVERTER
(JLVDS)

Charger

EMC4001

SMBUS Address [TBD]

SMBUS Address [TBD]

SMBUS Address [TBD]

2.2K

SBAT_SMBCLK

10

SBAT_SMBDAT

SIO

9

2.2K

2.2K

111

PBAT_SMBCLK
PBAT_SMBDAT

112

B B

2.2K

+3.3V_ALW

100 ohm
100 ohm

+3.3V_ALW

100 ohm
100 ohm

3

4

3
4

9

10

2'nd
BATTERY

BATTERY
CONN

CHARGER

SMBUS Address [TBD]

SMBUS Address [TBD]

SMBUS Address [TBD]

8.2K

+5V_ALW

6

5

DOCKING

SMBUS Address [TBD]

MEC 5025

6
5

8.2K

DOCK_SMB_CLK
DOCK_SMB_DAT

2.2K

2.2K

CKG_SMBDAT

12

CKG_SMBCLK

13

2N7002
2N7002

+3.3V_RUN

CLK_SDATA

CLK_SCLK

17

16

CLK GEN

SMBUS Address [TBD]

A A

Title

Size Document Number Rev

5

4

3

2

Date: Sheet

Compal Electronics, Inc.

SMBUS TOPOLOGY
LA-3301P

558Wednesday, February 14, 2007

1

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5

Non-iAMT

+3.3V_RUN

R435

@

1 2

0_0402_5%~D

D

CKG_SMBDAT39

D D

+3.3V_RUN

CKG_SMBCLK39

FSC FSB FSA CPU

CLKSEL2 CLKSEL0CLKSEL1

000

00

*

0

11

1

0

1

1

C C

0

1

1

11

1 3

1 3

D

1 2

R440

@

0_0402_5%~D

MHz

266

1

133

0

200

166

00

333

1

100

0

400

200 100 33.3

1

Table : ICS954305AK

CPU_BSEL CPU_BSEL2(FSC) CPU_BSEL1(FSB)

133

166

+3.3V_RUN

R290

B B

10K_0402_5%~D

1 2

PCI_PCM

0

0

S

Q34
2N7002W-7-F_SOT323-3~D

G

2
2

G

Q35

2N7002W-7-F_SOT323-3~D

S

SRC
MHz

100

100

100

100

100

100

100

0

1

R265

PCI
MHz

33.3

33.3

33.3

33.3

33.3

33.3

33.3

12

2.2K_0402_5%~D

12

R266

2.2K_0402_5%~D

CLK_SDATA

CLK_SCLK

Place crystal within
500 mils of CK410

CLK_ICH_48M23

CLK_SMC_48M31
CPU_MCH_BSEL08,10
CPU_MCH_BSEL18,10

CPU_MCH_BSEL28,10

CLK_PCI_TPM28

CLK_PCI_DOCK36

CLK_PCI_PCM30

CLK_PCI_502539

CLK_PCI_501838
CLK_ICH_14M23
CLK_SIO_14M38
MCH_DREFCLK10
MCH_DREFCLK#10

CLK_PWRGD23

CLK_PCI_ICH21

Non-iAMT

+3.3V_RUN

12

R304
10K_0402_5%~D

PCI_ICH

+3.3V_RUN

12

R318
10K_0402_5%~D

A A

@

PCI_LOM

12

R319

10K_0402_5%~D

Non-iAMT

+3.3V_RUN

12

R329

@

10K_0402_5%~D

FSA

12

R391

@

10K_0402_5%~D

0=UMA
1=Disc. GRFX down

5

PGMODE

ITP_EN

*

*

FCTSEL1 PIN43 PIN44 PIN47 PIN48

0=UMA

*

1=DIS

PIN 9

0

VTT_PWRGD#/PD

1

CKPWRGD/PD#

PIN 37

0

Pin 5/6 as SRC_10

1

Pin 5/6 as CPU_ITP

PIN 32

TME

0

Normal Operation

1

Trusted Mode Enabled

DOT96T DOT96C 96/100M_T 96/100M_C

27M_out 27M SSout SRCT0 SRCC0

27P_0402_50V8J~D

4

+CK_VDD_48

1

C99

2

4.7U_0603_6.3V4Z~D

1

C708

2

3.3P_0402_50V8C~D

C483

C484

33P_0402_50V8J~D

CLK_ICH_48M
CLK_SMC_48M

CLK_PCI_TPM
CLK_PCI_DOCK

CLK_PCI_PCM
CLK_PCI_5025

CLK_PCI_5018
CLK_ICH_14M
CLK_SIO_14M
MCH_DREFCLK
MCH_DREFCLK#

4

1 2

L28

BLM21PG600SN1D_0805~D

1

C471

2

0.1U_0402_16V4Z~D

1

C799

2

0.047U_0402_16V4Z~D

X1

14.31818MHz_20P_1BX14318CC1A~D

12

12

12

CLK_PCI_ICH

CLK_PWRGD

+3.3V_RUN

1 2

L87

BLM21PG600SN1D_0805~D

+CK_VDD_REF

1

C189

2

CLK_SMC_48MCLK_ICH_48M

1

C774

2

3.3P_0402_50V8C~D

0_0402_5%~D

1 2

R273 15_0402_5%~D

1 2

R275 15_0402_5%~D

1 2

R309 2.2K_0402_5%~D

1 2

R314 8.2K_0402_5%~D

R277 33_0402_5%~D
R596 33_0402_5%~D

R280 33_0402_5%~D
R282 15_0402_5%~D

1 2

R333 15_0402_5%~D

1 2

R284 15_0402_5%~D

1 2

R285 15_0402_5%~D

1 2

R286 33_0402_5%~D

1 2

R287 33_0402_5%~D

R291 33_0402_5%~D

R295

@

10K_0402_5%~D

1 2

R298

@

1 2

10K_0402_5%~D

CLK_SDATA34

Non-iAMT

+CK_VDD_MAIN2

0.047U_0402_16V7K~D

R271

12

12
12

12
12

12

CLK_SCLK34

R760

1 2
1 2

R758 2.2_0603_5%~D

+CK_VDD_MAIN+3.3V_RUN

1_0603_5%~D

3

+CK_VDD_MAIN

1

1

1

1

C475

C474

C473

C472

2

2

1

2

+CK_VDD_REF
+CK_VDD_48

CLK_XTAL_IN

CLK_XTAL_OUT

FSA

FSC

PCI_LOM
PCI_DOCK
PCI_PCM
PCI_SIO

CLKREF

DOT96
DOT96#

PCI_ICH

PGMODE

CLK_SCLK

CLK_SDATA

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

10U_0805_10V4Z~D

1

C480

2

10U_0805_10V4Z~D

R759

1 2

2.2_0603_5%~D

U28

1

VDD_SRC

49

VDD_SRC

54

VDD_SRC

65

VDD_SRC

30

VDD_PCI

36

VDD_PCI

12

VDD_CPU

18

VDD_REF

40

VDD_48

20

XTAL_IN

19

XTAL_OUT

41

USB_48MHz/FSLA

45

FSL_B/TEST_MODE

23

REF_0/FSL_C/TEST_SEL

34

PCICLK4/FCT_SEL

33

PCICLK3

32

PCICLK2/TME

27

PCICLK1

22

REF_1

43

DOT_96/27M

44

DOT_96#/27M_SS

37

PCICLK_F0/ITP_EN

39

CKPWRGD/PD#

9

PGMODE

16

SMBCLK

17

SMBDAT

4

VSS_SRC

15

VSS_CPU

21

VSS_REF

31

VSS_PCI

35

VSS_PCI

42

VSS_48

68

VSS_SRC

73

THRM_PAD

74

THRM_PAD

75

THRM_PAD

76

THRM_PAD

0.1U_0402_16V4Z~D

C481

0.1U_0402_16V4Z~D

2

2

1

2

0.1U_0402_16V4Z~D

C482

0.1U_0402_16V4Z~D

SLG8LP550

CPU_ITP/SRC_10

CPU_ITP#/SRC_10#

LCD_CLK/SRC_0

LCD_CLK#/SRC_0#

SLG8LP550_QFN72~D

0.1U_0402_16V4Z~D

+CK_VDD_A

PCI_STP#

CPU_STP#

CLKREQ_9#

CLKREQ_8#

CLKREQ_7#

CLKREQ_6#

CLKREQ_5#

CLKREQ_4#

CLKREQ_3#

CLKREQ_2#

SRC_1/SATA

SRC_1#/SATA#

CLKREQ_1#

1

2

VDD_A
VSS_A

CPU_1

CPU_1#

CPU_0

CPU_0#

SRC_9

SRC_9#

SRC_8

SRC_8#

SRC_7

SRC_7#

SRC_6

SRC_6#

SRC_5

SRC_5#

SRC_4

SRC_4#

SRC_3

SRC_3#

SRC_2

SRC_2#

1

C477

C476

2

0.1U_0402_16V4Z~D

7
8

H_STP_PCI#

25

H_STP_CPU#

24

MCH_BCLK

11

MCH_BCLK#

10

CPU_BCLK

14

CPU_BCLK#

13

CPU_ITP

6

CPU_ITP#

5

PCIE_MINI1

3

PCIE_MINI1#

2
72

PCIE_MINI2

70

PCIE_MINI2#

69
71

PCIE_ICH

66

PCIE_ICH#

67
38

PCIE_LOM

63

PCIE_LOM#

64
62
60
61
29
58
59
57

MCH_3GPLL

55
56
28
52
53
26

PCIE_SATA CLK_PCIE_SATA

50

PCIE_SATA#

51
46

DOT96_SSC

47

DOT96_SSC#

48

2

0.1U_0402_16V4Z~D

1

C478

2

R267 33_0402_5%~D
R268 33_0402_5%~D

R269 33_0402_5%~D
R270 33_0402_5%~D

R272 33_0402_5%~D
R274 33_0402_5%~D

R311 33_0402_5%~D
R313 33_0402_5%~D

R306 33_0402_5%~D
R307 33_0402_5%~D

R288 33_0402_5%~D
R289 33_0402_5%~D

R299 33_0402_5%~D
R168 33_0402_5%~D

R293 33_0402_5%~D
R294 33_0402_5%~D
R419 475_0402_1%~D

R279 33_0402_5%~D
R281 33_0402_5%~D

R316 33_0402_5%~D
R317 33_0402_5%~D

2

1

2

4.7U_0603_6.3V4Z~D

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2
1 2

1 2
1 2

1 2
1 2

C479

0.047U_0402_16V4Z~D

1

+3.3V_RUN

MINI1CLK_REQ#
MINI2CLK_REQ#
CLK_3GPLLREQ#
SATA_CLKREQ#
LOM_CLKREQ#

CLK_MCH_BCLK
CLK_MCH_BCLK#

CLK_CPU_BCLK
CLK_CPU_BCLK#

CLK_CPU_ITP
CLK_CPU_ITP#

CLK_PCIE_MINI1
CLK_PCIE_MINI1#

CLK_PCIE_MINI2
CLK_PCIE_MINI2#

CLK_PCIE_ICH
CLK_PCIE_ICH#

CLK_PCIE_LOM
CLK_PCIE_LOM#

CLK_MCH_3GPLL
CLK_MCH_3GPLL#MCH_3GPLL#

CLK_PCIE_SATA#

1 2

R315 10K_0402_5%~D

1 2

R310 10K_0402_5%~D

1 2

R297 10K_0402_5%~D

1 2

R283 10K_0402_5%~D

1 2

R301 10K_0402_5%~D

H_STP_PCI# 23

H_STP_CPU# 23

CLK_MCH_BCLK 10
CLK_MCH_BCLK# 10

CLK_CPU_BCLK 7
CLK_CPU_BCLK# 7

CLK_CPU_ITP 7
CLK_CPU_ITP# 7

CLK_PCIE_MINI1 34

CLK_PCIE_MINI1# 34

MINI1CLK_REQ# 34

CLK_PCIE_MINI2 34
CLK_PCIE_MINI2# 34

MINI2CLK_REQ# 34

CLK_PCIE_ICH 23
CLK_PCIE_ICH# 23

CLK_PCIE_LOM 28

CLK_PCIE_LOM# 28
LOM_CLKREQ# 28

CLK_MCH_3GPLL 10

CLK_MCH_3GPLL# 10

CLK_3GPLLREQ# 10

CLK_PCIE_SATA 22

CLK_PCIE_SATA# 22

SATA_CLKREQ# 23
DREF_SSCLK 10
DREF_SSCLK# 10

CLK_ICH_14M

1

2

CLK_SIO_14M

1

2

CLK_PCI_TPM

1

2

CLK_PCI_DOCK

1

2

CLK_PCI_PCM

1

2

CLK_PCI_5025

1

2

CLK_PCI_5018

1

2

CLK_PCI_ICH

1

2

DELL CONFIDENTIAL/PROPRIETARY

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

Clock Generator
LA-3301P

1

C775

3.3P_0402_50V8C~D

@

C776

3.3P_0402_50V8C~D

@

C777

3.3P_0402_50V8C~D

@

C778

3.3P_0402_50V8C~D

@

C779

3.3P_0402_50V8C~D

@

C780

3.3P_0402_50V8C~D

@

C781

3.3P_0402_50V8C~D

@

C785

3.3P_0402_50V8C~D

@

658Monday, February 26, 2007

of

1.0

5

4

3

2

1

H_A#[3..35]10

D D

H_ADSTB#010

H_REQ#010
H_REQ#110
H_REQ#210
H_REQ#310
H_REQ#410

C C

H_ADSTB#110

H_A20M#22

H_FERR#22

H_IGNNE#22
H_STPCLK#22

H_INTR22
H_NMI22
H_SMI#22

B B

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_ADSTB#0

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35
H_ADSTB#1

H_A20M#
H_FERR#
H_IGNNE#

H_STPCLK#
H_INTR
H_NMI
H_SMI#

JCPUA

J4

A[3]#

L5

A[4]#

L4

A[5]#

K5

A[6]#

M3

A[7]#

N2

A[8]#

J1

A[9]#

N3

A[10]#

P5

A[11]#

P2

A[12]#

L2

A[13]#

P4

A[14]#

P1

A[15]#

R1

A[16]#

M1

ADSTB[0]#

K3

REQ[0]#

H2

REQ[1]#

K2

REQ[2]#

J3

REQ[3]#

L1

REQ[4]#

Y2

A[17]#

U5

A[18]#

R3

A[19]#

W6

A[20]#

U4

A[21]#

Y5

A[22]#

U1

A[23]#

R4

A[24]#

T5

A[25]#

T3

A[26]#

W2

A[27]#

W5

A[28]#

Y4

A[29]#

U2

A[30]#

V4

A[31]#

W3

A[32]#

AA4

A[33]#

AB2

A[34]#

AA3

A[35]#

V1

ADSTB[1]#

A6

A20M#

A5

FERR#

C4

IGNNE#

D5

STPCLK#

C6

LINT0

B4

LINT1

A3

SMI#

M4

RSVD[01]

N5

RSVD[02]

T2

RSVD[03]

V3

RSVD[04]

B2

RSVD[05]

C3

RSVD[06]

D2

RSVD[07]

D22

RSVD[08]

D3

RSVD[09]

F6

RSVD[10]

TYCO_1-1674770-2_Merom~D

ADDR GROUP 0

ADDR GROUP 1

ICH

+1.05V_VCCP

DEFER#

DRDY#
DBSY#

LOCK#

RESET#

CONTROLXDP/ITP SIGNALS

RS[0]#
RS[1]#
RS[2]#
TRDY#

BPM[0]#
BPM[1]#
BPM[2]#
BPM[3]#

PRDY#
PREQ#

TRST#

THERMAL

PROCHOT#

THERMDA
THERMDC

THERMTRIP#

H CLK

BCLK[0]
BCLK[1]

RESERVED

ADS#
BNR#
BPRI#

BR0#

IERR#

INIT#

HIT#

HITM#

TCK

TDI
TDO
TMS

DBR#

R327

56_0402_5%~D

1 2

H1
E2
G5

H5
F21
E1

F1
D20

B3
H4
C1

F3
F4
G3
G2

G6
E4

AD4
AD3
AD1
AC4
AC2
AC1
AC5
AA6
AB3
AB5
AB6
C20

D21
A24
B25

C7

A22
A21

H_ADS#
H_BNR#
H_BPRI#

H_DEFER#
H_DRDY#
H_DBSY#

H_BR0#
H_IERR#

H_INIT#
H_LOCK#
H_RESET#

H_RS#0
H_RS#1
H_RS#2
H_TRDY#

H_HIT#
H_HITM#

ITP_BPM#0
ITP_BPM#1
ITP_BPM#2
ITP_BPM#3
ITP_BPM#4
ITP_BPM#5
ITP_TCK
ITP_TDI
ITP_TDO
ITP_TMS
ITP_TRST#

ITP_DBRESET#

H_THERMTRIP#
CLK_CPU_BCLK

CLK_CPU_BCLK#

H_THERMTRIP#

H_INIT# 22

H_LOCK# 10

H_RESET# 10
H_RS#0 10
H_RS#1 10
H_RS#2 10
H_TRDY# 10

T47 PAD~D
T48 PAD~D
T49 PAD~D
T50 PAD~D
T51 PAD~D
T52 PAD~D

ITP_DBRESET# 23,38

EC_CPU_PROCHOT#
H_THERMDA

H_THERMDC

1

2

H_ADS# 10

H_BNR# 10
H_BPRI# 10

H_DEFER# 10
H_DRDY# 10

H_DBSY# 10

H_BR0# 10

H_HIT# 10

H_HITM# 10

C417
2200P_0402_50V7K~D

H_THERMTRIP# 18

CLK_CPU_BCLK 6

CLK_CPU_BCLK# 6

R320

12

56_0402_5%~D

+1.05V_VCCP

H_RESET#

+1.05V_VCCP

12

R323
56_0402_5%~D

EC_CPU_PROCHOT# 39

H_THERMDA 18

H_THERMDC 18

H_THERMDA, H_THERMDC routing together,
Trace width / Spacing = 10 / 10 mil

R321

22.6_0402_1%~D

1 2

CLK_CPU_ITP6
CLK_CPU_ITP#6

+1.05V_VCCP

ITP_DBRESET#

CLK_CPU_ITP
CLK_CPU_ITP#

+1.05V_VCCP

+3.3V_SUS

+1.05V_VCCP

@

0.1U_0402_16V4Z~D

1

1

C486

C485

2

2

Place near JITP

R324

150_0402_5%~D

1 2

R325

51_0402_5%~D

R326

51_0402_1%~D

R328

39_0402_1%~D

R330

150_0402_5%~D

This shall place near CPU

R331

649_0402_1%~D

1 2

R332

27_0402_1%~D

JITP

28

VTT1

27

VTT0

26

VTAP

25

DBR#

24

DBA#

23

BPM0#

22

GND5

21

BPM1#

20

GND4

19

BPM2#

18

GND3

17

BPM3#

16

GND2

15

BPM4#

14

GND1

13

BPM5#

12

RESET#

11

FBO

10

GND0

9

BCLKP

8

BCLKN

7

TDO

6

NC2

5

TCK

4

NC1

3

TRST#

2

TMS

1

TDI

@

0.1U_0402_16V4Z~D

ITP_DBRESET#

ITP_TDO

H_RESET#

ITP_TMS

ITP_TDI

ITP_TRST#

ITP_TCK

29

30

GND6

GND7

JCPUD

A4

VSS[001]

A8

VSS[002]

A11

VSS[003]

A14

VSS[004]

A16

VSS[005]

A19

VSS[006]

A23

VSS[007]

AF2

VSS[008]

B6

VSS[009]

B8

VSS[010]

B11

VSS[011]

B13

VSS[012]

B16

VSS[013]

B19

VSS[014]

B21

VSS[015]

B24

VSS[016]

C5

VSS[017]

C8

VSS[018]

C11

VSS[019]

C14

VSS[020]

C16

VSS[021]

C19

VSS[022]

C2

VSS[023]

C22

VSS[024]

C25

VSS[025]

D1

MOLEX_52435-2891_28P~D@

VSS[026]

D4

VSS[027]

D8

VSS[028]

D11

VSS[029]

D13

VSS[030]

D16

VSS[031]

D19

VSS[032]

D23

VSS[033]

D26

VSS[034]

E3

VSS[035]

E6

VSS[036]

E8

VSS[037]

E11

VSS[038]

E14

VSS[039]

E16

VSS[040]

E19

VSS[041]

E21

VSS[042]

E24

VSS[043]

F5

VSS[044]

F8

VSS[045]

F11

VSS[046]

F13

VSS[047]

F16

VSS[048]

F19

VSS[049]

F2

VSS[050]

F22

VSS[051]

F25

VSS[052]

G4

VSS[053]

G1

VSS[054]

G23

VSS[055]

G26

VSS[056]

H3

VSS[057]

H6

VSS[058]

H21

VSS[059]

H24

VSS[060]

J2

VSS[061]

J5

VSS[062]

J22

VSS[063]

J25

VSS[064]

K1

VSS[065]

K4

VSS[066]

K23

VSS[067]

K26

VSS[068]

L3

VSS[069]

L6

VSS[070]

L21

VSS[071]

L24

VSS[072]

M2

VSS[073]

M5

VSS[074]

M22

VSS[075]

M25

VSS[076]

N1

VSS[077]

N4

VSS[078]

N23

VSS[079]

N26

VSS[080]

P3

VSS[081]

TYCO_1-1674770-2_Merom~D

VSS[082]
VSS[083]
VSS[084]
VSS[085]
VSS[086]
VSS[087]
VSS[088]
VSS[089]
VSS[090]
VSS[091]
VSS[092]
VSS[093]
VSS[094]
VSS[095]
VSS[096]
VSS[097]
VSS[098]
VSS[099]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
VSS[159]
VSS[160]
VSS[161]
VSS[162]
VSS[163]

P6
P21
P24
R2
R5
R22
R25
T1
T4
T23
T26
U3
U6
U21
U24
V2
V5
V22
V25
W1
W4
W23
W26
Y3
Y6
Y21
Y24
AA2
AA5
AA8
AA11
AA14
AA16
AA19
AA22
AA25
AB1
AB4
AB8
AB11
AB13
AB16
AB19
AB23
AB26
AC3
AC6
AC8
AC11
AC14
AC16
AC19
AC21
AC24
AD2
AD5
AD8
AD11
AD13
AD16
AD19
AD22
AD25
AE1
AE4
AE8
AE11
AE14
AE16
AE19
AE23
AE26
A2
AF6
AF8
AF11
AF13
AF16
AF19
AF21
A25
AF25

A A

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

Merom Processor(1/2)

LA-3301P

758Monday, February 26, 2007

1

1.0

of

5

4

3

2

1

+VCC_CORE +VCC_CORE

D D

C C

B B

R335

@

1K_0402_5%~D

A A

H_D#[0..63]10

H_DSTBN#010
H_DSTBP#010

H_DINV#010

H_DSTBN#110
H_DSTBP#110

H_DINV#110

V_CPU_GTLREF

CPU_MCH_BSEL06,10
CPU_MCH_BSEL16,10
CPU_MCH_BSEL26,10

2

R336

@

1 2

1 2

1K_0402_5%~D

Place C close to the
CPU_TEST4 pin. Make sure
CPU_TEST4 routing is
reference to GND and away
from other noisy signal.

R394

C490

@

@

1

0_0402_5%~D

0.1U_0402_16V4Z~D

5

H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_DSTBN#0
H_DSTBP#0
H_DINV#0

H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_DSTBN#1
H_DSTBP#1
H_DINV#1

TEST1
TEST3

TEST4
TEST5
TEST6

CPU_MCH_BSEL0
CPU_MCH_BSEL1
CPU_MCH_BSEL2

TEST1
TEST2
TEST4
TEST6 TEST3

1 2

E22
F24
E26
G22
F23
G25
E25
E23
K24
G24

J24

J23
H22
F26
K22
H23

J26
H26
H25

N22
K25
P26
R23

L23
M24

L22
M23
P25
P23
P22
T24
R24

L25
T25
N25

L26
M26
N24

AD26

C23
D25
C24

AF26

AF1
A26

B22
B23
C21

T30PAD~D
T31PAD~D

For the purpose of testability, route these signals
through a ground referenced Z0 = 55ohm trace that
ends in a via that is near a GND via and is
accessible through an oscilloscope connection.

FSB

BCLK BSEL2 BSEL1 BSEL0

533

133

667

166

800

200

JCPUB

D[0]#
D[1]#
D[2]#
D[3]#
D[4]#

DATA GRP 0 DATA GRP 1

D[5]#
D[6]#
D[7]#
D[8]#
D[9]#
D[10]#
D[11]#
D[12]#
D[13]#
D[14]#
D[15]#
DSTBN[0]#
DSTBP[0]#
DINV[0]#

D[16]#
D[17]#
D[18]#
D[19]#
D[20]#
D[21]#
D[22]#
D[23]#
D[24]#
D[25]#
D[26]#
D[27]#
D[28]#
D[29]#
D[30]#
D[31]#
DSTBN[1]#
DSTBP[1]#
DINV[1]#

GTLREF
TSET1

TEST2
TEST3
TEST4
TEST5
TEST6

BSEL[0]
BSEL[1]
BSEL[2]

TEST5

DATA GRP 2DATA GRP 3

DSTBN[2]#
DSTBP[2]#

DINV[2]#

DSTBN[3]#
DSTBP[3]#

DINV[3]#

COMP[0]

MISC

COMP[1]
COMP[2]
COMP[3]

DPRSTP#

DPSLP#
DPWR#

PWRGOOD

TYCO_1-1674770-2_Merom~D

001

100

D[32]#
D[33]#
D[34]#
D[35]#
D[36]#
D[37]#
D[38]#
D[39]#
D[40]#
D[41]#
D[42]#
D[43]#
D[44]#
D[45]#
D[46]#
D[47]#

D[48]#
D[49]#
D[50]#
D[51]#
D[52]#
D[53]#
D[54]#
D[55]#
D[56]#
D[57]#
D[58]#
D[59]#
D[60]#
D[61]#
D[62]#
D[63]#

SLP#

PSI#

4

H_D#32

Y22

H_D#33

AB24

H_D#34

V24

H_D#35

V26

H_D#36

V23

H_D#37

T22

H_D#38

U25

H_D#39

U23

H_D#40

Y25

H_D#41

W22

H_D#42

Y23

H_D#43

W24

H_D#44

W25

H_D#45

AA23

H_D#46

AA24

H_D#47

AB25

H_DSTBN#2

Y26

H_DSTBP#2

AA26

H_DINV#2

U22

H_D#48

AE24

H_D#49

AD24

H_D#50

AA21

H_D#51

AB22

H_D#52

AB21

H_D#53

AC26

H_D#54

AD20

H_D#55

AE22

H_D#56

AF23

H_D#57

AC25

H_D#58

AE21

H_D#59

AD21

H_D#60

AC22

H_D#61

AD23

H_D#62

AF22

H_D#63

AC23

H_DSTBN#3

AE25

H_DSTBP#3

AF24

H_DINV#3

AC20

COMP0

R26

COMP1

U26

COMP2

AA1

COMP3

Y1

H_DPRSTP#

E5

H_DPSLP#

B5

H_DPWR#

D24

H_PWRGOOD

D6

H_CPUSLP#

D7

H_PSI#

AE6

110

+1.05V_VCCP

V_CPU_GTLREF

Layout close CPU PIN AD26
55 ohm, 0.5 inch (max)

H_DSTBN#2 10
H_DSTBP#2 10

H_DINV#2 10

H_DSTBN#3 10
H_DSTBP#3 10

H_DINV#3 10

H_DPRSTP# 10,22,48

H_DPSLP# 22

H_DPWR# 10

H_PWRGOOD 22

H_CPUSLP# 10

H_PSI# 48

12

R341
1K_0402_1%~D

12

R344
2K_0402_1%~D

54.9_0402_1%~D

12

R337

R338

Resistor placed within 0.5" of
CPU pin.Trace should be at least
25 mils away from any other
toggling signal. COMP0, COMP2
trace should be 27.4 ohm.
COMP1, COMP3 should be 55
ohm.

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

54.9_0402_1%~D

27.4_0402_1%~D

12

R339

27.4_0402_1%~D

12

12

R340

JCPUC

A7

VCC[001]

A9

VCC[002]

A10

VCC[003]

A12

VCC[004]

A13

VCC[005]

A15

VCC[006]

A17

VCC[007]

A18

VCC[008]

A20

VCC[009]

B7

VCC[010]

B9

VCC[011]

B10

VCC[012]

B12

VCC[013]

B14

VCC[014]

B15

VCC[015]

B17

VCC[016]

B18

VCC[017]

B20

VCC[018]

C9

VCC[019]

C10

VCC[020]

C12

VCC[021]

C13

VCC[022]

C15

VCC[023]

C17

VCC[024]

C18

VCC[025]

D9

VCC[026]

D10

VCC[027]

D12

VCC[028]

D14

VCC[029]

D15

VCC[030]

D17

VCC[031]

D18

VCC[032]

E7

VCC[033]

E9

VCC[034]

E10

VCC[035]

E12

VCC[036]

E13

VCC[037]

E15

VCC[038]

E17

VCC[039]

E18

VCC[040]

E20

VCC[041]

F7

VCC[042]

F9

VCC[043]

F10

VCC[044]

F12

VCC[045]

F14

VCC[046]

F15

VCC[047]

F17

VCC[048]

F18

VCC[049]

F20

VCC[050]

AA7

VCC[051]

AA9

VCC[052]

AA10

VCC[053]

AA12

VCC[054]

AA13

VCC[055]

AA15

VCC[056]

AA17

VCC[057]

AA18

VCC[058]

AA20

VCC[059]

AB9

VCC[060]

AC10

VCC[061]

AB10

VCC[062]

AB12

VCC[063]

AB14

VCC[064]

AB15

VCC[065]

AB17

VCC[066]

AB18

VCC[067]

TYCO_1-1674770-2_Merom~D

2

AB20

VCC[068]

AB7

VCC[069]

AC7

VCC[070]

AC9

VCC[071]

AC12

VCC[072]

AC13

VCC[073]

AC15

VCC[074]

AC17

VCC[075]

AC18

VCC[076]

AD7

VCC[077]

AD9

VCC[078]

AD10

VCC[079]

AD12

VCC[080]

AD14

VCC[081]

AD15

VCC[082]

AD17

VCC[083]

AD18

VCC[084]

AE9

VCC[085]

AE10

VCC[086]

AE12

VCC[087]

AE13

VCC[088]

AE15

VCC[089]

AE17

VCC[090]

AE18

VCC[091]

AE20

VCC[092]

AF9

VCC[093]

AF10

VCC[094]

AF12

VCC[095]

AF14

VCC[096]

AF15

VCC[097]

AF17

VCC[098]

AF18

VCC[099]

AF20

VCC[100]

G21

VCCP[01]
VCCP[02]
VCCP[03]
VCCP[04]
VCCP[05]
VCCP[06]
VCCP[07]
VCCP[08]
VCCP[09]
VCCP[10]
VCCP[11]
VCCP[12]
VCCP[13]
VCCP[14]
VCCP[15]
VCCP[16]

VCCA[1]
VCCA[2]

VID[0]
VID[1]
VID[2]
VID[3]
VID[4]
VID[5]
VID[6]

VCCSENSE

VSSSENSE

V6
J6
K6
M6
J21
K21
M21
N21
N6
R21
R6
T21
T6
V21
W21

B26
C26

AD6
AF5
AE5
AF4
AE3
AF3
AE2

AF7

AE7

VCCSENSE

VSSSENSE

VID0
VID1
VID2
VID3
VID4
VID5TEST2
VID6

220U_D2_4VY_R15M~D

1

+

2

C487

VID0 48
VID1 48
VID2 48
VID3 48
VID4 48
VID5 48
VID6 48

VCCSENSE 48

VSSSENSE 48

Length mat c h within 25 mils Z0=27.4 ohm

Place R342 and R343 near CPU

+VCC_CORE

Route VCCSENSE and VSSSENSE trace at

27.4 ohms, 7 mils spaci n g and 1 inch (max)

R342

1 2

100_0402_1%~D

R343

1 2

100_0402_1%~D

VCCSENSE

VSSSENSE

DELL CONFIDENTIAL/PROPRIETARY

Title

Size Document Number Rev

Date: Sheet

+1.05V_VCCP

CRB was 270uF

0.01U_0402_16V7K~D

10U_0805_10V4Z~D

C488

C489

1

1

2

2

Compal Electronics, Inc.

Merom Processor(2/2)
LA-3301P

1

+1.5V_RUN

858Monday, February 26, 2007

1.0

of

5

+VCC_CORE

Place these inside
socket cavity on L8
(North side
Secondary)

D D

Place these inside
socket cavity on L8
(Sorth side
Secondary)

Place these inside
socket cavity on L8
(North side
Primary)

Place these inside
socket cavity on L8
(Sorth side
Primary)

C C

1

2

+VCC_CORE

1

2

+VCC_CORE

1

2

+VCC_CORE

1

2

C329
10U_0805_4VAM~D

C222
10U_0805_4VAM~D

C363
10U_0805_4VAM~D

C364
10U_0805_4VAM~D

1

C330
10U_0805_4VAM~D

2

1

C223
10U_0805_4VAM~D

2

1

C64
10U_0805_4VAM~D

2

1

C50
10U_0805_4VAM~D

2

1

C331
10U_0805_4VAM~D

2

1

C224
10U_0805_4VAM~D

2

1

C65
10U_0805_4VAM~D

2

1

C51
10U_0805_4VAM~D

2

1

C332
10U_0805_4VAM~D

2

1

C225
10U_0805_4VAM~D

2

1

C66
10U_0805_4VAM~D

2

1

C52
10U_0805_4VAM~D

2

4

1

2

1

2

1

2

1

2

C333
10U_0805_4VAM~D

C227
10U_0805_4VAM~D

C67
10U_0805_4VAM~D

C53
10U_0805_4VAM~D

1

C334
10U_0805_4VAM~D

2

1

C226
10U_0805_4VAM~D

2

1

C68
10U_0805_4VAM~D

2

1

C54
10U_0805_4VAM~D

2

1

C335
10U_0805_4VAM~D

2

1

C228
10U_0805_4VAM~D

2

10uF 0805 X6S -> 85 degree C

3

1

C336
10U_0805_4VAM~D

2

1

C229
10U_0805_4VAM~D

2

1

C55
10U_0805_4VAM~D

2

1

C69
10U_0805_4VAM~D

2

1

C190
10U_0805_4VAM~D

2

1

C185
10U_0805_4VAM~D

2

2

1

High Frequence Decoupling

Near VCORE regulator.

+VCC_CORE

+VCC_CORE

1

C870

0.1U_0402_10V7K~D

2

@

BITs WI97840

1

+

C365

2

1

C293

0.1U_0402_10V7K~D

2

North Side Secondary

1

+

2

220U_X_2VM_R7M~D

1

2

C250

0.1U_0402_10V7K~D

ESR <= 1.5m ohm
Capacitor > 1980uF

1

C310

0.1U_0402_10V7K~D

2

1

C264

0.1U_0402_10V7K~D

2

Place these inside
socket cavity on L8
(North side
Secondary)

South Side Secondary

C177

B B

A A

220U_X_2VM_R7M~D

1

+

2

+1.05V_VCCP

1

2

1

+

C178

C179

2

@

220U_X_2VM_R7M~D

C312

0.1U_0402_10V7K~D

220U_X_2VM_R7M~D

1

+

2

1

2

1

+

C338

C366

2

@

220U_X_2VM_R7M~D

C256

0.1U_0402_10V7K~D

220U_X_2VM_R7M~D

1

C871

0.1U_0402_10V7K~D

2

@

1

C872

0.1U_0402_10V7K~D

2

@

1

C873

0.1U_0402_10V7K~D

2

@

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

CPU Bypass

LA-3301P

958Wednesday, February 14, 2007

1

1.0

of

5

54.9_0402_1%~D

+1.05V_VCCP

12

R347

24.9_0402_1%~D

H_D#[0..63]8

12

R348

54.9_0402_1%~D

R350

H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63

H_SWNG
H_RCOMP

H_SCOMP
H_SCOMP#

H_RESET#7

H_CPUSLP#8

12

5

H_RESET#

H_CPUSLP#

H_VREF

H_VREF

2K_0402_1%~D

U29A

E2

H_D#_0

G2

H_D#_1

G7

H_D#_2

M6

H_D#_3

H7

H_D#_4

H3

H_D#_5

G4

H_D#_6

F3

H_D#_7

N8

H_D#_8

H2

H_D#_9

M10

H_D#_10

N12

H_D#_11

N9

H_D#_12

H5

H_D#_13

P13

H_D#_14

K9

H_D#_15

M2

H_D#_16

W10

H_D#_17

Y8

H_D#_18

V4

H_D#_19

M3

H_D#_20

J1

H_D#_21

N5

H_D#_22

N3

H_D#_23

W6

H_D#_24

W9

H_D#_25

N2

H_D#_26

Y7

H_D#_27

Y9

H_D#_28

P4

H_D#_29

W3

H_D#_30

N1

H_D#_31

AD12

H_D#_32

AE3

H_D#_33

AD9

H_D#_34

AC9

H_D#_35

AC7

H_D#_36

AC14

H_D#_37

AD11

H_D#_38

AC11

H_D#_39

AB2

H_D#_40

AD7

H_D#_41

AB1

H_D#_42

Y3

H_D#_43

AC6

H_D#_44

AE2

H_D#_45

AC5

H_D#_46

AG3

H_D#_47

AJ9

H_D#_48

AH8

H_D#_49

AJ14

H_D#_50

AE9

H_D#_51

AE11

H_D#_52

AH12

H_D#_53

AJ5

H_D#_54

AH5

H_D#_55

AJ6

H_D#_56

AE7

H_D#_57

AJ7

H_D#_58

AJ2

H_D#_59

AE5

H_D#_60

AJ3

H_D#_61

AH2

H_D#_62

AH13

H_D#_63

B3

H_SWING

C2

H_RCOMP

W1

H_SCOMP

W2

H_SCOMP#

B6

H_CPURST#

E5

H_CPUSLP#

B9

H_AVREF

A9

H_DVREF

LE88CLGM A0 QM20_FCBGA1299~D

12

R355
1K_0402_1%~D

0.1U_0402_16V4Z~D

12

1

R361

2

H_ADSTB#_0
H_ADSTB#_1

HOST

H_BREQ#

H_DEFER#

H_DBSY#

HPLL_CLK

HPLL_CLK#

H_DPWR#

H_DRDY#

H_HITM#

H_LOCK#

H_TRDY#

H_DINV#_0
H_DINV#_1
H_DINV#_2
H_DINV#_3

H_DSTBN#_0
H_DSTBN#_1
H_DSTBN#_2
H_DSTBN#_3

H_DSTBP#_0
H_DSTBP#_1
H_DSTBP#_2
H_DSTBP#_3

H_REQ#_0
H_REQ#_1
H_REQ#_2
H_REQ#_3
H_REQ#_4

H_RS#_0
H_RS#_1
H_RS#_2

+1.05V_VCCP+1.05V_VCCP

H_SWNG

100_0402_1%~D

C496

R362

D D

C C

B B

Layout Note:
H_RCOMP tr ace width
and spacing is 10/20

A A

H_A#_3
H_A#_4
H_A#_5
H_A#_6
H_A#_7
H_A#_8

H_A#_9
H_A#_10
H_A#_11
H_A#_12
H_A#_13
H_A#_14
H_A#_15
H_A#_16
H_A#_17
H_A#_18
H_A#_19
H_A#_20
H_A#_21
H_A#_22
H_A#_23
H_A#_24
H_A#_25
H_A#_26
H_A#_27
H_A#_28
H_A#_29
H_A#_30
H_A#_31
H_A#_32
H_A#_33
H_A#_34
H_A#_35

H_ADS#

H_BNR#

H_BPRI#

H_HIT#

12

R356
221_0402_1%~D

12

4

H_A#3

J13

H_A#4

B11

H_A#5

C11

H_A#6

M11

H_A#7

C15

H_A#8

F16

H_A#9

L13

H_A#10

G17

H_A#11

C14

H_A#12

K16

H_A#13

B13

H_A#14

L16

H_A#15

J17

H_A#16

B14

H_A#17

K19

H_A#18

P15

H_A#19

R17

H_A#20

B16

H_A#21

H20

H_A#22

L19

H_A#23

D17

H_A#24

M17

H_A#25

N16

H_A#26

J19

H_A#27

B18

H_A#28

E19

H_A#29

B17

H_A#30

B15

H_A#31

E17

H_A#32

C18

H_A#33

A19

H_A#34

B19

H_A#35

N19

H_ADS#

G12

H_ADSTB#0

H17

H_ADSTB#1

G20

H_BNR#

C8

H_BPRI#

E8

H_BR0#

F12

H_DEFER#

D6

H_DBSY#

C10

CLK_MCH_BCLK

AM5

CLK_MCH_BCLK#

AM7

H_DPWR#

H8

H_DRDY#

K7

H_HIT#

E4

H_HITM#

C6

H_LOCK#

G10

H_TRDY#

B7

H_DINV#0

K5

H_DINV#1

L2

H_DINV#2

AD13

H_DINV#3

AE13

H_DSTBN#0

M7

H_DSTBN#1

K3

H_DSTBN#2

AD2

H_DSTBN#3

AH11

H_DSTBP#0

L7

H_DSTBP#1

K2

H_DSTBP#2

AC2

H_DSTBP#3

AJ10

H_REQ#0

M14

H_REQ#1

E13

H_REQ#2

A11

H_REQ#3

H13

H_REQ#4

B12

H_RS#0

E12

H_RS#1

D7

H_RS#2

D8

+1.8V_SUS

R359

3.01K_0402_1%~D

0.1U_0402_16V4Z~D

1

C497

2

4

1K_0402_1%~D

R363

H_A#[3..35] 7

H_ADS# 7

H_ADSTB#0 7

H_ADSTB#1 7
H_BNR# 7
H_BPRI# 7
H_BR0# 7
H_DEFER# 7
H_DBSY# 7

CLK_MCH_BCLK 6

CLK_MCH_BCLK# 6
H_DPWR# 8
H_DRDY# 7

H_HIT# 7
H_HITM# 7
H_LOCK# 7

H_TRDY# 7

H_DINV#0 8
H_DINV#1 8
H_DINV#2 8
H_DINV#3 8

H_DSTBN#0 8
H_DSTBN#1 8
H_DSTBN#2 8
H_DSTBN#3 8

H_DSTBP#0 8
H_DSTBP#1 8
H_DSTBP#2 8
H_DSTBP#3 8

H_REQ#0 7
H_REQ#1 7
H_REQ#2 7
H_REQ#3 7
H_REQ#4 7

H_RS#0 7

H_RS#1 7

H_RS#2 7

12

R353
1K_0402_1%~D

SMRCOMP_VOH

1

12

12

C494

2

SMRCOMP_VOL

1

C498

2

+1.8V_SUS

V_DDR_MCH_REF

1K_0402_1%~D

392_0402_1~D

1

C495

2

2.2U_0603_6.3V6K~D

0.01U_0402_16V7K~D

1

C499

2

2.2U_0603_6.3V6K~D

0.01U_0402_16V7K~D

C491

+1.25V_RUN

R349

R351

3

M_ODT016
M_ODT116
M_ODT217
M_ODT317

T42PAD~D
T43PAD~D
T44PAD~D
T45PAD~D

T46PAD~D

M_CLK_DDR0
M_CLK_DDR1
M_CLK_DDR2
M_CLK_DDR3

M_CLK_DDR#0
M_CLK_DDR#1
M_CLK_DDR#2
M_CLK_DDR#3

DDR_CKE0_DIMMA
DDR_CKE1_DIMMA
DDR_CKE2_DIMMB
DDR_CKE3_DIMMB

DDR_CS0_DIMMA#
DDR_CS1_DIMMA#
DDR_CS2_DIMMB#
DDR_CS3_DIMMB#

M_ODT0
M_ODT1
M_ODT2
M_ODT3

SMRCOMP
SMRCOMP#

SMRCOMP_VOH
SMRCOMP_VOL

V_DDR_MCH_REF

MCH_DREFCLK
MCH_DREFCLK#
DREF_SSCLK
DREF_SSCLK#

CLK_MCH_3GPLL
CLK_MCH_3GPLL#

DMI_MRX_ITX_N0
DMI_MRX_ITX_N1
DMI_MRX_ITX_N2
DMI_MRX_ITX_N3

DMI_MRX_ITX_P0
DMI_MRX_ITX_P1
DMI_MRX_ITX_P2
DMI_MRX_ITX_P3

DMI_MTX_IRX_N0
DMI_MTX_IRX_N1
DMI_MTX_IRX_N2
DMI_MTX_IRX_N3

DMI_MTX_IRX_P0
DMI_MTX_IRX_P1
DMI_MTX_IRX_P2
DMI_MTX_IRX_P3

CL_CLK0
CL_DATA0
ICH_CL_PWROK
ICH_CL_RST0#
CL_VREF

SDVO_CTRLCLK
SDVO_CTRLDATA
CLK_3GPLLREQ#
MCH_ICH_SYNC#

R774 0_0402_5%~D

R357

20K_0402_5%~D

M_CLK_DDR016
M_CLK_DDR116
M_CLK_DDR217
M_CLK_DDR317

M_CLK_DDR#016
M_CLK_DDR#116
M_CLK_DDR#217
M_CLK_DDR#317

DDR_CKE0_DIMMA16
DDR_CKE1_DIMMA16
DDR_CKE2_DIMMB17
DDR_CKE3_DIMMB17

DDR_CS0_DIMMA#16
DDR_CS1_DIMMA#16
DDR_CS2_DIMMB#17
DDR_CS3_DIMMB#17

R345

20_0402_1%~D

1 2
1 2

R346

20_0402_1%~D

1

1

C492

2

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

12

12

1

2

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

MCH_DREFCLK6

MCH_DREFCLK#6

2

DREF_SSCLK#6

CLK_MCH_3GPLL6
CLK_MCH_3GPLL#6

DMI_MRX_ITX_N023
DMI_MRX_ITX_N123
DMI_MRX_ITX_N223
DMI_MRX_ITX_N323

DMI_MRX_ITX_P023
DMI_MRX_ITX_P123
DMI_MRX_ITX_P223
DMI_MRX_ITX_P323

DMI_MTX_IRX_N023
DMI_MTX_IRX_N123
DMI_MTX_IRX_N223
DMI_MTX_IRX_N323

DMI_MTX_IRX_P023
DMI_MTX_IRX_P123
DMI_MTX_IRX_P223
DMI_MTX_IRX_P323

CL_CLK023
CL_DATA023

ICH_CL_PWROK23,39

ICH_CL_RST0#23

C493

0.1U_0402_16V4Z~D

SDVO_CTRLCLK51
SDVO_CTRLDATA51

CLK_3GPLLREQ#6
MCH_ICH_SYNC#23

3

DREF_SSCLK6

AV29

SM_CK_0

BB23

SM_CK_1

BA25

SM_CK_3

AV23

SM_CK_4

AW30

SM_CK#_0

BA23

SM_CK#_1

AW25

SM_CK#_3

AW23

SM_CK#_4

BE29

SM_CKE_0

AY32

SM_CKE_1

BD39

SM_CKE_3

BG37

SM_CKE_4

BG20

SM_CS#_0

BK16

SM_CS#_1

BG16

SM_CS#_2

BE13

SM_CS#_3

BH18

SM_ODT_0

BJ15

SM_ODT_1

BJ14

SM_ODT_2

BE16

SM_ODT_3

BL15

SM_RCOMP

BK14

SM_RCOMP#

BK31

SM_RCOMP_VOH

BL31

SM_RCOMP_VOL

AR49

SM_VREF_0

AW4

SM_VREF_1

B42

DPLL_REF_CLK

C42

DPLL_REF_CLK#

H48

DPLL_REF_SSCLK

H47

DPLL_REF_SSCLK#

K44

PEG_CLK

K45

PEG_CLK#

AN47

DMI_RXN_0

AJ38

DMI_RXN_1

AN42

DMI_RXN_2

AN46

DMI_RXN_3

AM47

DMI_RXP_0

AJ39

DMI_RXP_1

AN41

DMI_RXP_2

AN45

DMI_RXP_3

AJ46

DMI_TXN_0

AJ41

DMI_TXN_1

AM40

DMI_TXN_2

AM44

DMI_TXN_3

AJ47

DMI_TXP_0

AJ42

DMI_TXP_1

AM39

DMI_TXP_2

AM43

DMI_TXP_3

E35

GFX_VID_0

A39

GFX_VID_1

C38

GFX_VID_2

B39

GFX_VID_3

E36

GFX_VR_EN

AM49

CL_CLK

AK50

CL_DATA

AT43

CL_PWROK

AN49

CL_RST#

AM50

CL_VREF

H35

SDVO_CTRL_CLK

K36

SDVO_CTRL_DATA

G39

CLK_REQ#

G40

ICH_SYNC#

A37

12
12

TEST_1

R32

TEST_2

LE88CLGM A0 QM20_FCBGA1299~D

THERMTRIP_MCH#

R358

1 2

56_0402_5%~D

2

2

RSVD CFG PM NC

DDR MUXINGCLKDMIGRAPHICS VIDMEMISC

+1.05V_VCCP

1

U29B

P36

RSVD1

P37

RSVD2

R35

RSVD3

N35

RSVD4

AR12

RSVD5

AR13

RSVD6

AM12

RSVD7

AN13

RSVD8

J12

RSVD9

AR37

RSVD10

AM36

RSVD11

AL36

RSVD12

AM37

RSVD13

D20

RSVD14

H10

RSVD20

B51

RSVD21

BJ20

RSVD22

BK22

RSVD23

BF19

RSVD24

BH20

RSVD25

BK18

RSVD26

BJ18

RSVD27

BF23

RSVD28

BG23

RSVD29

BC23

RSVD30

BD24

RSVD31

BH39

RSVD32

AW20

RSVD33

BK20

RSVD34

C48

RSVD35

D47

RSVD36

B44

RSVD37

C44

RSVD38

A35

RSVD39

B37

RSVD40

B36

RSVD41

B34

RSVD42

C34

RSVD43

CFG_0
CFG_1
CFG_2
CFG_3
CFG_4
CFG_5
CFG_6
CFG_7
CFG_8

CFG_9
CFG_10
CFG_11
CFG_12
CFG_13
CFG_14
CFG_15
CFG_16
CFG_17
CFG_18
CFG_19
CFG_20

PM_BM_BUSY#

PM_DPRSTP#
PM_EXT_TS#_0
PM_EXT_TS#_1

PWROK

RSTIN#

THERMTRIP#

DPRSLPVR

NC_1
NC_2
NC_3
NC_4
NC_5
NC_6
NC_7
NC_8

NC_9
NC_10
NC_11
NC_12
NC_13
NC_14
NC_15
NC_16

P27
N27
N24
C21
C23
F23
N23
G23
J20
C20
R24
L23
J23
E23
E20
K23
M20
M24
L32
N33
L35

G41
L39
L36
J36
AW49
AV20
N20
G36

BJ51
BK51
BK50
BL50
BL49
BL3
BL2
BK1
BJ1
E1
A5
C51
B50
A50
A49
BK2

R36

100_0402_5%~D

1 2

CFG5

CFG9

CFG16

CFG19
CFG20

PM_BMBUSY#
H_DPRSTP#
PM_EXTTS#0
PM_EXTTS#1
ICH_PWRGD
PLTRST1#_R
THERMTRIP_MCH#
DPRSLPVR

T63 PAD~D
T64 PAD~D

T65 PAD~D
T66 PAD~D
T67 PAD~D

T68 PAD~D
T69 PAD~D
T70 PAD~D
T71 PAD~D
T72 PAD~D
T73 PAD~D

T74 PAD~D
T75 PAD~D

R589

0_0402_5%~D@

R583

0_0402_5%~D

CPU_MCH_BSEL0 6,8
CPU_MCH_BSEL1 6,8
CPU_MCH_BSEL2 6,8

CFG5 12

CFG9 12

CFG16 12

CFG19 12
CFG20 12

PM_BMBUSY# 23
H_DPRSTP# 8,22,48

PM_EXTTS#0 16
PM_EXTTS#1 17

ICH_PWRGD 23,42

THERMTRIP_MCH# 18

DPRSLPVR 23,48

PM_EXTTS#0

PM_EXTTS#1

12

PLTRST1#PLTRST1#_R

12

DELL CONFIDENTIAL/PROPRIETARY

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

Crestline(1 of 6)

LA-3301P

1

+3.3V_RUN

R352

10K_0402_5%~D

12

R354

10K_0402_5%~D

12

SB_NB_PCIE_RST# 21

PLTRST1# 21,51

10 58Monday, February 26, 2007

of

1.0

5

D D

4

3

2

1

DDR_B_D[0..63] 17DDR_A_D[0..63] 16

SB_DQ_10
SB_DQ_11
SB_DQ_12
SB_DQ_13
SB_DQ_14
SB_DQ_15
SB_DQ_16
SB_DQ_17
SB_DQ_18
SB_DQ_19
SB_DQ_20
SB_DQ_21
SB_DQ_22
SB_DQ_23
SB_DQ_24
SB_DQ_25
SB_DQ_26
SB_DQ_27
SB_DQ_28
SB_DQ_29
SB_DQ_30
SB_DQ_31
SB_DQ_32
SB_DQ_33
SB_DQ_34
SB_DQ_35
SB_DQ_36
SB_DQ_37
SB_DQ_38
SB_DQ_39
SB_DQ_40
SB_DQ_41
SB_DQ_42
SB_DQ_43
SB_DQ_44
SB_DQ_45
SB_DQ_46
SB_DQ_47
SB_DQ_48
SB_DQ_49
SB_DQ_50
SB_DQ_51
SB_DQ_52
SB_DQ_53
SB_DQ_54
SB_DQ_55
SB_DQ_56
SB_DQ_57
SB_DQ_58
SB_DQ_59
SB_DQ_60
SB_DQ_61
SB_DQ_62
SB_DQ_63

U29E

SB_DQ_0
SB_DQ_1
SB_DQ_2
SB_DQ_3
SB_DQ_4
SB_DQ_5
SB_DQ_6
SB_DQ_7
SB_DQ_8
SB_DQ_9

AP49
AR51
AW50
AW51
AN51
AN50
AV50
AV49
BA50
BB50
BA49
BE50
BA51
AY49
BF50
BF49
BJ50
BJ44
BJ43
BL43
BK47
BK49
BK43
BK42
BJ41
BL41
BJ37
BJ36
BK41
BJ40
BL35
BK37
BK13
BE11
BK11
BC11
BC13
BE12
BC12
BG12
BJ10
BL9
BK5
BL5
BK9
BK10
BJ8
BJ6
BF4
BH5
BG1
BC2
BK3
BE4
BD3
BJ2
BA3
BB3
AR1
AT3
AY2
AY3
AU2
AT2

DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63

DDR_A_BS016
DDR_A_BS116
DDR_A_BS216

DDR_A_DM[0..7]16

DDR_A_DQS[0..7]16

C C

DDR_A_DQS#[0..7]16

DDR_A_MA[0..14]16

B B

DDR_A_CAS#16
DDR_A_RAS#16
DDR_A_WE#16

DDR_A_BS0
DDR_A_BS1
DDR_A_BS2

DDR_A_DM0
DDR_A_DM1
DDR_A_DM2
DDR_A_DM3
DDR_A_DM4
DDR_A_DM5
DDR_A_DM6
DDR_A_DM7

DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7

DDR_A_DQS#0
DDR_A_DQS#1
DDR_A_DQS#2
DDR_A_DQS#3

DDR_A_DQS#4

DDR_A_DQS#5
DDR_A_DQS#6

DDR_A_DQS#7

DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA14 DDR_B_MA14

DDR_A_CAS#
DDR_A_RAS#

DDR_A_WE#

T10

BB19

SA_BS_0

BK19

SA_BS_1

BF29

SA_BS_2

AT45

SA_DM_0

BD44

SA_DM_1

BD42

SA_DM_2

AW38

SA_DM_3

AW13

SA_DM_4

BG8

SA_DM_5

AY5

SA_DM_6

AN6

SA_DM_7

AT46

SA_DQS_0

BE48

SA_DQS_1

BB43

SA_DQS_2

BC37

SA_DQS_3

BB16

SA_DQS_4

BH6

SA_DQS_5

BB2

SA_DQS_6

AP3

SA_DQS_7

AT47

SA_DQS#_0

BD47

SA_DQS#_1

BC41

SA_DQS#_2

BA37

SA_DQS#_3

BA16

SA_DQS#_4

BH7

SA_DQS#_5

BC1

SA_DQS#_6

AP2

SA_DQS#_7

BJ19

SA_MA_0

BD20

SA_MA_1

BK27

SA_MA_2

BH28

SA_MA_3

BL24

SA_MA_4

BK28

SA_MA_5

BJ27

SA_MA_6

BJ25

SA_MA_7

BL28

SA_MA_8

BA28

SA_MA_9

BC19

SA_MA_10

BE28

SA_MA_11

BG30

SA_MA_12

BJ16

SA_MA_13

BJ29

SA_MA_14

BL17

SA_CAS#

BE18

SA_RAS#

BA19

SA_WE#

AY20

SA_RCVEN#

LE88CLGM A0 QM20_FCBGA1299~D

DDR SYSTEM MEMORY A

SA_DQ_0
SA_DQ_1
SA_DQ_2
SA_DQ_3
SA_DQ_4
SA_DQ_5
SA_DQ_6
SA_DQ_7
SA_DQ_8

SA_DQ_9
SA_DQ_10
SA_DQ_11
SA_DQ_12
SA_DQ_13
SA_DQ_14
SA_DQ_15
SA_DQ_16
SA_DQ_17
SA_DQ_18
SA_DQ_19
SA_DQ_20
SA_DQ_21
SA_DQ_22
SA_DQ_23
SA_DQ_24
SA_DQ_25
SA_DQ_26
SA_DQ_27
SA_DQ_28
SA_DQ_29
SA_DQ_30
SA_DQ_31
SA_DQ_32
SA_DQ_33
SA_DQ_34
SA_DQ_35
SA_DQ_36
SA_DQ_37
SA_DQ_38
SA_DQ_39
SA_DQ_40
SA_DQ_41
SA_DQ_42
SA_DQ_43
SA_DQ_44
SA_DQ_45
SA_DQ_46
SA_DQ_47
SA_DQ_48
SA_DQ_49
SA_DQ_50
SA_DQ_51
SA_DQ_52
SA_DQ_53
SA_DQ_54
SA_DQ_55
SA_DQ_56
SA_DQ_57
SA_DQ_58
SA_DQ_59
SA_DQ_60
SA_DQ_61
SA_DQ_62
SA_DQ_63

U29D

AR43
AW44
BA45
AY46
AR41
AR45
AT42
AW47
BB45
BF48
BG47
BJ45
BB47
BG50
BH49
BE45
AW43
BE44
BG42
BE40
BF44
BH45
BG40
BF40
AR40
AW40
AT39
AW36
AW41
AY41
AV38
AT38
AV13
AT13
AW11
AV11
AU15
AT11
BA13
BA11
BE10
BD10
BD8
AY9
BG10
AW9
BD7
BB9
BB5
AY7
AT5
AT7
AY6
BB7
AR5
AR8
AR9
AN3
AM8
AN10
AT9
AN9
AM9
AN11

DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63

DDR_B_BS017
DDR_B_BS117
DDR_B_BS217

DDR_B_DM[0..7]17

DDR_B_DQS[0..7]17

DDR_B_DQS#[0..7]17

DDR_B_MA[0..14]17

DDR_B_CAS#17
DDR_B_RAS#17
DDR_B_WE#17

DDR_B_BS0
DDR_B_BS1
DDR_B_BS2

DDR_B_DM0
DDR_B_DM1
DDR_B_DM2
DDR_B_DM3
DDR_B_DM4
DDR_B_DM5
DDR_B_DM6
DDR_B_DM7

DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4
DDR_B_DQS5
DDR_B_DQS6
DDR_B_DQS7

DDR_B_DQS#0
DDR_B_DQS#1
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS#4
DDR_B_DQS#5
DDR_B_DQS#6
DDR_B_DQS#7

DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13

DDR_B_CAS#
DDR_B_RAS#
DDR_B_WE#

SB_RCVEN#SA_RCVEN#

T11

AY17

SB_BS_0

BG18

SB_BS_1

BG36

SB_BS_2

AR50

SB_DM_0

BD49

SB_DM_1

BK45

SB_DM_2

BL39

SB_DM_3

BH12

SB_DM_4

BJ7

SB_DM_5

BF3

SB_DM_6

AW2

SB_DM_7

AT50

SB_DQS_0

BD50

SB_DQS_1

BK46

SB_DQS_2

BK39

SB_DQS_3

BJ12

SB_DQS_4

BL7

SB_DQS_5

BE2

SB_DQS_6

AV2

SB_DQS_7

AU50

SB_DQS#_0

BC50

SB_DQS#_1

BL45

SB_DQS#_2

BK38

SB_DQS#_3

BK12

SB_DQS#_4

BK7

SB_DQS#_5

BF2

SB_DQS#_6

AV3

SB_DQS#_7

BC18

SB_MA_0

BG28

SB_MA_1

BG25

SB_MA_2

AW17

SB_MA_3

BF25

SB_MA_4

BE25

SB_MA_5

BA29

SB_MA_6

BC28

SB_MA_7

AY28

SB_MA_8

BD37

SB_MA_9

BG17

SB_MA_10

BE37

SB_MA_11

BA39

SB_MA_12

BG13

SB_MA_13

BE24

SB_MA_14

BE17

SB_CAS#

AV16

SB_RAS#

BC17

SB_WE#

AY18

SB_RCVEN#

LE88CLGM A0 QM20_FCBGA1299~D

DDR SYSTEM MEMORY B

A A

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

Crestline(2 of 6)

LA-3301P

11 58Monday, February 26, 2007

1

1.0

of

5

4

3

2

1

Strap Pin Table

DMI X2 Select

PCI Express
Graphic Lane

FSB Dynamic

ODT

DMI Lane
Reversal

SDVO/PCIE
Concurrent
Operation

Low = DMI x 2
High = DMI x 4 (Default)

Low = Reverse LaneCFG9
High = Normal O p e r a t i o n ( Default)

Low=Dynamic O D T Disable
High=Dynamic ODT Enable(default)

Low=Normal (default)
High=Lane Reversed

Low=Only SDVO or PCIEx1 is
operational (defaults)

High=SDVO and P C I E x 1 a r e o p e rating
simultaneously via PEG port

Low=No SDVO Device Present

High=SDVO Device Present (default)

R383

2.2K_0402_5%~D

G_CLK_DDC2

G_DAT_DDC2

+3.3V_RUN

2

NO CONNECT FOR DISCRETE

12

12

R384

2.2K_0402_5%~D
Q36

D

S

13

G

+3.3V_RUN

2

G

2

Q37

13

D

S

CLK_DDC2

DAT_DDC2

R365 4.02K_0402_1%~D@

CFG510

CFG910

CFG1610

1 2

R368 4.02K_0402_1%~D@

1 2

R372 4.02K_0402_1%~D@

1 2

CFG[3:17] have internal pullup

R373 4.02K_0402_1%~D@

CFG1910

CFG2010

1 2

R374 4.02K_0402_1%~D @

1 2

CFG[18:19] have internal pulldown

BSS138_SOT23~D

BSS138_SOT23~D

CLK_DDC2 20,36

DAT_DDC2 20,36

DELL CONFIDENTIAL/PROPRIETARY

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

Crestline(3 of 6)

LA-3301P

12 58Monday, February 26, 2007

1

+3.3V_RUN

1.0

of

BIA_PWM19

D D

R369 = 2.4k ohm value is
recommended per Intel

C C

TV_CVBS36
TV_Y36
TV_C36

CRT_BLU20,36
CRT_GRN20,36
CRT_RED20,36

B B

R378

R379

1 2

1 2

150_0402_1%~D

150_0402_1%~D

+3.3V_RUN

A A

1 2

R41 2.2K_0402_5%~D

1 2

R110 2.2K_0402_5%~D

PANEL_BKEN38

LCD_DDCCLK19
LCD_DDCDATA19

ENVDD19

1 2

R369

3.3K_0402_1%~D

LCD_A0-19
LCD_A1-19
LCD_A2-19

LCD_A0+19
LCD_A1+19
LCD_A2+19

LCD_B0-19
LCD_B1-19
LCD_B2-19

LCD_B0+19
LCD_B1+19
LCD_B2+19

12

12

R377

R376

150_0402_1%~D

CRT_HSYNC20
CRT_VSYNC20

R382 1.3K_0402_1%~D

Trace CRT_IREF should be at
least 20 miles away from any
other toggling signal.

LCD_DDCCLK

LCD_DDCDATA

5

R375

R380

12

150_0402_1%~D

1 2

150_0402_1%~D

BIA_PWM
PANEL_BKEN

LCD_DDCCLK
LCD_DDCDATA
ENVDD

L_IBG

LCD_ACLK-_C
LCD_ACLK+_C
LCD_BCLK-_C
LCD_BCLK+_C

TV_CVBS
TV_Y
TV_C

150_0402_1%~D

G_CLK_DDC2
G_DAT_DDC2
CRT_HSYNC
CRT_VSYNC

CRT_IREF

12

LCD_A0+
LCD_A1+
LCD_A2+
LCD_B0+
LCD_B1+
LCD_B2+

J40

H39

E39

E40
C37
D35

K40

L41

L43
N41
N40

D46
C45
D44

E42
G51

E51

F49

G50

E50

F48

G44

B47

B45

E44

A47

A45

E27
G27

K27

F27

J27

L27
M35

P33

H32
G32

K29

J29

F29

E29

K33
G35

F33

E33
C32

L_BKLT_CTRL
L_BKLT_EN
L_CTRL_CLK
L_CTRL_DATA
L_DDC_CLK
L_DDC_DATA
L_VDD_EN

LVDS_IBG
LVDS_VBG
LVDS_VREFH
LVDS_VREFL

LVDSA_CLK#
LVDSA_CLK
LVDSB_CLK#
LVDSB_CLK

LVDSA_DATA#_0
LVDSA_DATA#_1
LVDSA_DATA#_2

LVDSA_DATA_0
LVDSA_DATA_1
LVDSA_DATA_2

LVDSB_DATA#_0
LVDSB_DATA#_1
LVDSB_DATA#_2

LVDSB_DATA_0
LVDSB_DATA_1
LVDSB_DATA_2

TVA_DAC
TVB_DAC
TVC_DAC

TVA_RTN
TVB_RTN
TVC_RTN

TV_DCONSEL_0
TV_DCONSEL_1

CRT_BLUE
CRT_BLUE#
CRT_GREEN
CRT_GREEN#
CRT_RED
CRT_RED#

CRT_DDC_CLK
CRT_DDC_DATA
CRT_HSYNC
CRT_VSYNC

CRT_TVO_IREF

C181 3.3P_0402_50V8C~D@
C192 3.3P_0402_50V8C~D@
C193 3.3P_0402_50V8C~D@
C196 3.3P_0402_50V8C~D@
C207 3.3P_0402_50V8C~D@
C209 3.3P_0402_50V8C~D@

U29C

LVDS TV VGA

LE88CLGM A0 QM20_FCBGA1299~D

LCD_A0-

1 2

LCD_A1-

1 2

LCD_A2-

1 2

LCD_B0-

1 2

LCD_B1-

1 2

LCD_B2-

1 2

Keep stub for
caps as small
as possible

PEGCOMP

PEG_RX#_0
PEG_RX#_1
PEG_RX#_2
PEG_RX#_3
PEG_RX#_4
PEG_RX#_5
PEG_RX#_6
PEG_RX#_7
PEG_RX#_8
PEG_RX#_9

PEG_RX_0
PEG_RX_1
PEG_RX_2
PEG_RX_3
PEG_RX_4
PEG_RX_5
PEG_RX_6
PEG_RX_7
PEG_RX_8

PEG_RX_9
PEG_RX_10
PEG_RX_11
PEG_RX_12
PEG_RX_13
PEG_RX_14
PEG_RX_15

PEG_TX#_0
PEG_TX#_1
PEG_TX#_2
PEG_TX#_3
PEG_TX#_4
PEG_TX#_5
PEG_TX#_6
PEG_TX#_7
PEG_TX#_8
PEG_TX#_9

PEG_TX_0

PEG_TX_1

PEG_TX_2

PEG_TX_3

PEG_TX_4

PEG_TX_5

PEG_TX_6

PEG_TX_7

PEG_TX_8

PEG_TX_9
PEG_TX_10
PEG_TX_11
PEG_TX_12
PEG_TX_13
PEG_TX_14
PEG_TX_15

LCD_ACLK-_C

3.3P_0402_50V8C~D

LCD_ACLK+_C

LCD_BCLK-_C

3.3P_0402_50V8C~D

LCD_BCLK+_C

N43
M43

J51
L51
N47
T45
T50
U40
Y44
Y40
AB51
W49
AD44
AD40
AG46
AH49
AG45
AG41

J50
L50
M47
U44
T49
T41
W45
W41
AB50
Y48
AC45
AC41
AH47
AG49
AH45
AG42

N45
U39
U47
N51
R50
T42
Y43
W46
W38
AD39
AC46
AC49
AC42
AH39
AE49
AH44

M45
T38
T46
N50
R51
U43
W42
Y47
Y39
AC38
AD47
AC50
AD43
AG39
AE50
AH43

@

C39

C43

@

PEG_COMPI

PEG_COMPO

PEG_RX#_10
PEG_RX#_11
PEG_RX#_12
PEG_RX#_13
PEG_RX#_14
PEG_RX#_15

PCI-EXPRESS GRAPHICS

PEG_TX#_10
PEG_TX#_11
PEG_TX#_12
PEG_TX#_13
PEG_TX#_14
PEG_TX#_15

4

R366

24.9_0402_1%~D

1 2

SDVOB_RED-_C
SDVOB_GREEN-_C
SDVOB_BLUE-_C
SDVOB_CLK-_C

SDVOB_RED+_C
SDVOB_GREEN+_C
SDVOB_BLUE+_C
SDVOB_CLK+_C

12

1

@

0_0402_5%~D

2

12

1

R687

@

0_0402_5%~D

2

+VCC_PEG

SDVOB_INT- 51

SDVOB_INT+ 51

C500 0.1U_0402_10V7K~D

1 2

C501 0.1U_0402_10V7K~D

1 2

C502 0.1U_0402_10V7K~D

1 2

C503 0.1U_0402_10V7K~D

1 2

C504 0.1U_0402_10V7K~D

1 2

C505 0.1U_0402_10V7K~D

1 2

C506 0.1U_0402_10V7K~D

1 2

C507 0.1U_0402_10V7K~D

1 2

R686

0_0402_5%~D

1 2

R667

1 2

R685
0_0402_5%~D

R689

0_0402_5%~D

1 2

1 2

R688

0_0402_5%~D

LCD_ACLK- 19

LCD_ACLK+ 19

LCD_BCLK- 19

LCD_BCLK+ 19

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

CFG5

CFG16

CFG19

CFG20

SDVO_CRTL_DATA

SDVOB_RED- 51
SDVOB_GREEN- 51
SDVOB_BLUE- 51
SDVOB_CLK- 51

SDVOB_RED+ 51
SDVOB_GREEN+ 51
SDVOB_BLUE+ 51
SDVOB_CLK+ 51

5

+1.05V_VCCP

CRB 270uF

220U_D2_4VY_R15M~D

1

C535

1

+

C537

2

2

D D

C C

B B

A A

4.7U_0603_6.3V6M~D

C542

1

2

+1.25V_RUN

BLM18AG121SN1D_0603~D

22U_0805_6.3V6M~D

1

2

+1.25V_RUN

0.1U_0402_16V4Z~D
C591

+3.3V_RUN

+VCC_RXR_DMI

0.47U_0402_10V4Z~D

1

2

+1.8V_RUN

+1.8V_SUS

+1.25V_RUN

1U_0603_10V4Z~D

C589

1

2

Place caps close
to VCC_AXF (Pin
A21, B21, B23)

4.7U_0603_6.3V6M~D

C543

1

1

2

2

L33

1U_0603_10V4Z~D

C551

1

2

1

2

+VCC_TX_LVDS

0.1U_0402_16V4Z~D
C597

1

2

0.47U_0402_10V4Z~D
C577

C576

1

2

0_0603_5%~D

1 2
1 2

0_0603_5%~D

10U_0805_4VAM~D

1

C590

2

2.2U_0603_6.3V6K~D

+1.25V_RUN_AXD

12

C552

+1.8V_SM_CK

1

2

0.47U_0402_10V4Z~D

C544

+1.25V_RUN

+VCC_PEG

0.47U_0402_10V4Z~D
C578

R579

@

R578

5

U13

VTT_1

U12

VTT_2

U11

VTT_3

U9

VTT_4

U8

VTT_5

U7

VTT_6

U5

VTT_7

U3

VTT_8

U2

VTT_9

U1

VTT_10

T13

VTT_11

T11

VTT_12

T10

VTT_13

T9

VTT_14

T7

VTT_15

T6

VTT_16

T5

VTT_17

T3

VTT_18

T2

VTT_19

R3

VTT_20

R2

VTT_21

R1

VTT_22

AT23

VCC_AXD_1

AU28

VCC_AXD_2

AU24

VCC_AXD_3

AT29

VCC_AXD_4

AT25

VCC_AXD_5

AT30

VCC_AXD_6

AR29

VCC_AXD_NCTF

B23

VCC_AXF_1

B21

VCC_AXF_2

A21

VCC_AXF_3

AJ50

VCC_DMI

BK24

VCC_SM_CK_1

BK23

VCC_SM_CK_2

BJ24

VCC_SM_CK_3

BJ23

VCC_SM_CK_4

A43

VCC_TX_LVDS

C40

VCC_HV_1

B40

VCC_HV_2

AD51

VCC_PEG_1

W50

VCC_PEG_2

W51

VCC_PEG_3

V49

VCC_PEG_4

V50

VCC_PEG_5

AH50

VCC_RXR_DMI_1

AH51

VCC_RXR_DMI_2

A7

VTTLF1

F2

VTTLF2

AH1

VTTLF3

LE88CLGM A0 QM20_FCBGA1299~D

+VCC_TX_LVDS_R

BLM18AG121SN1D_0603~D

AXD

POWER

VTTLF

L42

VTT

AXF

PEG

VCCA_CRT_DAC_1
VCCA_CRT_DAC_2

CRT

VCCA_DAC_BG
VSSA_DAC_BG

VCCA_DPLLA

PLL

VCCA_DPLLB

LVDS PEG

VCCA_PEG_BG
VSSA_PEG_BG

VCCA_PEG_PLL

SM

VCCA_SM_10
VCCA_SM_11

CLK

VCCA_SM_NCTF_1
VCCA_SM_NCTF_2

VCCA_SM_CK_1
VCCA_SM_CK_2

VCCA_TVA_DAC_1
VCCA_TVA_DAC_2

TV

VCCA_TVB_DAC_1
VCCA_TVB_DAC_2
VCCA_TVC_DAC_1
VCCA_TVC_DAC_2

TV/CRT

VCCD_TVDAC

DMI

VCCD_PEG_PLL

LVDS

VCCD_LVDS_1
VCCD_LVDS_2

+VCC_TX_LVDS

12

1000P_0402_50V7K~D

1

C596

2

U29H

VCCSYNC

VCCA_HPLL

VCCA_MPLL

VCCA_LVDS
VSSA_LVDS

VCCA_SM_1
VCCA_SM_2
VCCA_SM_3
VCCA_SM_4
VCCA_SM_5
VCCA_SM_7
VCCA_SM_8
VCCA_SM_9

VCCD_CRT

VCCD_QDAC

VCCD_HPLL

220U_D2_4VY_R15M~D

1

+

C595

2

J32
A33

B33

A30
B32

B49
H49
AL2
AM2

A41
B41

K50
K49

U51

AW18
AV19
AU19
AU18
AU17
AT22
AT21
AT19
AT18
AT17
AR17
AR16

BC29
BB29

C25
B25
C27
B27
B28
A28

M32
L29

N28

AN2
U48

J41
H42

4

1

2

+3.3V_CRT_DAC

+3.3V_RUN_DAC_BG

+1.25V_RUN_DPLLA
+1.25V_RUN_DPLLB
+1.25V_RUN_HPLL
+1.25V_RUN_MPLL

+1.25V_RUN_PEGPLL

+1.25V_RUN_A_SM

+1.25V_RUN_SM_CK

+3.3V_RUN_TVDACA
+3.3V_RUN_TVDACB
+3.3V_RUN_TVDACC

+1.5V_RUN_TVDAC
+1.5V_RUN_QDAC

1

2

1U_0603_10V4Z~D

1

C581

2

4

+3.3V_RUN

C532

0.1U_0402_16V4Z~D

1 2

0.1U_0402_16V4Z~D

3

C536

22n_0805_25V

12

1

2

L41

C561

22U_0805_6.3V6M~D

C564

1

2

C642

+3.3V_RUN

1 2

22U_0805_6.3V6M~D

0_0805_5%~D

C562

1U_0603_10V4Z~D

1

2

0.1U_0402_16V4Z~D

12

1 2

10_0603_5%~D

1

2

1

2

R406

C565

12

R417

1

C723

2

@

0.022U_0402_16V7K~D

+VCC_TX_LVDS

4.7U_0603_6.3V6M~D

1U_0603_10V4Z~D

+1.25V_RUN_PEGPLL

0.1U_0402_16V4Z~D

C554

@

0_0603_5%~D

0_0603_5%~D

22U_0805_6.3V6M~D

C560

1

C559

2

R116

R152

BLM18AG121SN1D_0603~D

1

1

2

2

0.1U_0402_16V4Z~D

C563

1

2

+1.25V_RUN

12

+1.8V_RUN

12

+1.8V_SUS

+1.8V_SUS +1.8V_SM_CK

C594

10U_0805_4VAM~D

+1.05V_VCCP

2 1

D16

RB751V_SOD323~D

+3.3V_RUN

L31

C541

+VCC_TX_LVDS

0.1U_0402_16V4Z~D

C550

+1.25V_RUN

1U_0603_10V4Z~D

C566

1

2

1

2

1_0603_5%~D

R416

+3.3V_RUN

12

1

C547

2

1

+

C558

2

1 2

0_0603_5%~D

1

C722

2

0.022U_0402_16V7K~D

+1.5V_RUN_TVDAC

0.1U_0402_16V4Z~D
C592

1

2

BLM18PG181SN1_0603~D

1

2

+1.5V_RUN_QDAC

3

+3.3V_RUN_DAC_BG +3.3V_RUN

1 2

3

C533

22n_0805_25V

L29

BLM18PG181SN1_0603~D

1

2

12

C538

0.1U_0402_16V4Z~D

C533,C534,C536,C545,C553,C579 are being
replaced by 0-ohm 0805 resistor

+VCC_PEG

220U_D2_4VY_R15M~D

C548

1000P_0402_50V7K~D

C556

+1.25V_RUN

100U_D2E_6.3VM_R18M~D

R408

C569

1U_0603_10V4Z~D

1

2

C567

10U_0805_4VAM~D

R815

100_0603_5%~D

1 2

1

C570

2

0.1U_0402_16V4Z~D

1

C720

2

@

0.022U_0402_16V7K~D

C593

22U_0805_6.3VAM~D

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

1

1

+

2

2

+VCC_RXR_DMI

1

1

+

2

2

220U_D2_4VY_R15M~D

L35

BLM21PG221SN1D_0805~D

1 2

12

1_0402_5%~D

1 2

22n_0805_25V

3

C579

10U_0805_4VAM~D

C549

C557

10U_0805_4VAM~D

R409

+1.5V_RUN

0.1U_0402_16V4Z~D

1

2

L32

BLM18PG181SN1_0603~D

L34

BLM18PG181SN1_0603~D

+1.25V_RUN_PEGPLL+1.25V_RUN

+1.25V_RUN_HPLL

C571

0.1U_0402_16V4Z~D

C584

40mA Max.

C587

0.1U_0402_16V4Z~D

12

+1.05V_VCCP

12

+1.05V_VCCP

0.1U_0402_16V4Z~D
C568

1

2

L37

BLM18AG121SN1D_0603~D

1

1

C572

2

2

22U_0805_6.3VAM~D

L39

10U_MLZ2012E100PTAIN_60mA_25%_0805~D

1

1

+

C585
470U_D2_2.5VM_R15~D

2

2

2

+1.25V_RUN

12

1

2

12

2

Non-iAMT

C573

0.1U_0402_16V4Z~D

1

L30

C540

+1.25V_RUN

12

+1.25V_RUN+1.25V_RUN

12

+3.3V_RUN+3.3V_RUN_TVDAC

12

+3.3V_RUN_TVDACA

1 2

C534

+3.3V_RUN_TVDACB

1 2

C545

+3.3V_RUN_TVDACC

1 2

C553

45mA Max.45mA Max.

0.1U_0402_16V4Z~D

40mA Max.

0.1U_0402_16V4Z~D

3

22n_0805_25V

3

22n_0805_25V

3

22n_0805_25V

+1.25V_RUN_MPLL

C574

+1.25V_RUN_DPLLB+1.25V_RUN_DPLLA

C588

1

2

1

2

1

2

1

2

1

2

BLM18PG181SN1_0603~D

1

10U_0805_10V4Z~D

C539

2

0.1U_0402_16V4Z~D

C546

0.1U_0402_16V4Z~D

C555

0.1U_0402_16V4Z~D

L38

BLM18AG121SN1D_0603~D

1

C575
22U_0805_6.3VAM~D

2

L40

10U_MLZ2012E100PTAIN_60mA_25%_0805~D

1

+

C586
470U_D2_2.5VM_R15~D

2

DELL CONFIDENTIAL/PROPRIETARY

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

Crestline(4 of 6)

LA-3301P

13 58Wednesday, March 07, 2007

1

1.0

of

5

4

3

2

1

+3.3V_RUN

+1.05V_VCCP

D D

220U_D2_4VY_R15M~D

Layout Note:
370 mils from edge

C C

B B

Layout Note:
Place close to GMCH edge.

1

C602

+

2

Layout Note:
Inside GMCH cavity.

+1.05V_VCCP

22U_0805_6.3V6M~D

C615

1

2

0.1U_0402_10V7K~D

C618

1

2

0.22U_0402_10V4Z~D

22U_0805_6.3VAM~D

C603

1

2

1

2

C604

1

1

2

2

0.22U_0402_10V4Z~D

0.1U_0402_10V7K~D
C614

C613

1

1

2

2

0.22U_0402_10V4Z~D

0.22U_0402_10V4Z~D

C616

C617

1

2

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

C619

C620

1

2

AB33
AB36
AB37
AC33
AC35
AC36
AD35
AD36
AF33
AF36
AH33
AH35
AH36
AH37

AJ33

AJ35
AK33
AK35
AK36
AK37
AD33

AJ36

AM35

AL33

AL35
AA33
AA35
AA36
AP35
AP36
AR35
AR36

AL24

AL26

AL28

AM26
AM28
AM29
AM31
AM32
AM33

AP29
AP31
AP32
AP33

AL29

AL31

AL32
AR31
AR32
AR33

Y32
Y33
Y35
Y36
Y37
T30
T34

T35
U29
U31
U32
U33
U35
U36

V32

V33

V36

V37

U29F

VCC_NCTF_1
VCC_NCTF_2
VCC_NCTF_3
VCC_NCTF_4
VCC_NCTF_5
VCC_NCTF_6
VCC_NCTF_7
VCC_NCTF_8
VCC_NCTF_9
VCC_NCTF_10
VCC_NCTF_11
VCC_NCTF_12
VCC_NCTF_13
VCC_NCTF_14
VCC_NCTF_15
VCC_NCTF_16
VCC_NCTF_17
VCC_NCTF_18
VCC_NCTF_19
VCC_NCTF_20
VCC_NCTF_21
VCC_NCTF_22
VCC_NCTF_23
VCC_NCTF_24
VCC_NCTF_25
VCC_NCTF_26
VCC_NCTF_27
VCC_NCTF_28
VCC_NCTF_29
VCC_NCTF_30
VCC_NCTF_31
VCC_NCTF_32
VCC_NCTF_33
VCC_NCTF_34
VCC_NCTF_35
VCC_NCTF_36
VCC_NCTF_37
VCC_NCTF_38
VCC_NCTF_39
VCC_NCTF_40
VCC_NCTF_41
VCC_NCTF_42
VCC_NCTF_43
VCC_NCTF_44
VCC_NCTF_45
VCC_NCTF_46
VCC_NCTF_47
VCC_NCTF_48
VCC_NCTF_49
VCC_NCTF_50

VCC_AXM_NCTF_1
VCC_AXM_NCTF_2
VCC_AXM_NCTF_3
VCC_AXM_NCTF_4
VCC_AXM_NCTF_5
VCC_AXM_NCTF_6
VCC_AXM_NCTF_7
VCC_AXM_NCTF_8
VCC_AXM_NCTF_9
VCC_AXM_NCTF_10
VCC_AXM_NCTF_11
VCC_AXM_NCTF_12
VCC_AXM_NCTF_13
VCC_AXM_NCTF_14
VCC_AXM_NCTF_15
VCC_AXM_NCTF_16
VCC_AXM_NCTF_17
VCC_AXM_NCTF_18
VCC_AXM_NCTF_19

POWER

LE88CLGM A0 QM20_FCBGA1299~D

VSS_NCTF_1
VSS_NCTF_2
VSS_NCTF_3
VSS_NCTF_4
VSS_NCTF_5
VSS_NCTF_6
VSS_NCTF_7
VSS_NCTF_8

VSS_NCTF_9
VSS_NCTF_10
VSS_NCTF_11
VSS_NCTF_12
VSS_NCTF_13
VSS_NCTF_14
VSS_NCTF_15
VSS_NCTF_16
VSS_NCTF_17
VSS_NCTF_18
VSS_NCTF_19
VSS_NCTF_20
VSS_NCTF_21

VSS_SCB1
VSS_SCB2
VSS_SCB3
VSS_SCB4
VSS_SCB5
VSS_SCB6

VCC_AXM_1
VCC_AXM_2
VCC_AXM_3
VCC_AXM_4
VCC_AXM_6
VCC_AXM_5
VCC_AXM_7

R420

10_0603_5%~D

1 2

T27
T37
U24
U28
V31
V35
AA19
AB17
AB35
AD19
AD37
AF17
AF35
AK17
AM17
AM24
AP26
AP28
AR15
AR19
AR28

A3
B2
C1
BL1
BL51
A51

+1.05V_VCCP

AT33
AT31
AK29
AK24
AK23
AJ26
AJ23

D17

2

1

3

BAT54CW_SOT323~D

+1.8V_SUS

0.1U_0402_10V7K~D

2

C608

1

Layout Note:
Place C901 where
LVDS and DDR2 taps.

330U_D2E_2.5VM~D

1

C605

+

2

Layout Note: Inside GMCH cavity.

+1.05V_VCCP+1.05V_VCCP

22U_0805_6.3V6M~D

22U_0805_6.3V6M~D

1

1

C606

C607

2

2

Layout Note:
Place on the edge

+1.05V_VCCP

AT35
AT34
AH28
AC32
AC31
AK32

AJ31

AJ28
AH32
AH31
AH29
AF32

R30

AU32
AU33
AU35
AV33

AW33
AW35

AY35
BA32
BA33
BA35
BB33
BC32
BC33
BC35
BD32
BD35
BE32
BE33
BE35
BF33
BF34

BG32
BG33
BG35

BH32
BH34
BH35

BJ32

BJ33

BJ34
BK32
BK33
BK34
BK35

BL33
AU30

R20
W13

W14

AA20
AA23
AA26
AA28
AB21
AB24
AB29
AC20
AC21
AC23
AC24
AC26
AC28
AC29
AD20
AD23
AD24
AD28
AF21
AF26
AA31
AH20
AH21
AH23
AH24
AH26
AD31

AJ20
AN14

T14

Y12

VCC_1
VCC_2
VCC_3
VCC_4
VCC_5
VCC_6
VCC_7
VCC_8
VCC_9
VCC_10
VCC_11
VCC_12

VCC_13

VCC_SM_1
VCC_SM_2
VCC_SM_3
VCC_SM_4
VCC_SM_5
VCC_SM_6
VCC_SM_7
VCC_SM_8
VCC_SM_9
VCC_SM_10
VCC_SM_11
VCC_SM_12
VCC_SM_13
VCC_SM_14
VCC_SM_15
VCC_SM_16
VCC_SM_17
VCC_SM_18
VCC_SM_19
VCC_SM_20
VCC_SM_21
VCC_SM_22
VCC_SM_23
VCC_SM_24
VCC_SM_25
VCC_SM_26
VCC_SM_27
VCC_SM_28
VCC_SM_29
VCC_SM_30
VCC_SM_31
VCC_SM_32
VCC_SM_33
VCC_SM_34
VCC_SM_35
VCC_SM_36

VCC_AXG_1
VCC_AXG_2
VCC_AXG_3
VCC_AXG_4
VCC_AXG_5
VCC_AXG_6
VCC_AXG_7
VCC_AXG_8
VCC_AXG_9
VCC_AXG_10
VCC_AXG_11
VCC_AXG_12
VCC_AXG_13
VCC_AXG_14
VCC_AXG_15
VCC_AXG_16
VCC_AXG_17
VCC_AXG_18
VCC_AXG_19
VCC_AXG_20
VCC_AXG_21
VCC_AXG_22
VCC_AXG_23
VCC_AXG_24
VCC_AXG_25
VCC_AXG_26
VCC_AXG_27
VCC_AXG_28
VCC_AXG_29
VCC_AXG_30
VCC_AXG_31
VCC_AXG_32
VCC_AXG_33
VCC_AXG_34

U29G

VCC_AXG_NCTF_1
VCC_AXG_NCTF_2
VCC_AXG_NCTF_3

VCC CORE

POWER

VCC SM

VCC GFX

LE88CLGM A0 QM20_FCBGA1299~D

VCC_AXG_NCTF_4
VCC_AXG_NCTF_5
VCC_AXG_NCTF_6
VCC_AXG_NCTF_7
VCC_AXG_NCTF_8

VCC_AXG_NCTF_9
VCC_AXG_NCTF_10
VCC_AXG_NCTF_11
VCC_AXG_NCTF_12
VCC_AXG_NCTF_13
VCC_AXG_NCTF_14
VCC_AXG_NCTF_15
VCC_AXG_NCTF_16
VCC_AXG_NCTF_17
VCC_AXG_NCTF_18
VCC_AXG_NCTF_19
VCC_AXG_NCTF_20
VCC_AXG_NCTF_21
VCC_AXG_NCTF_22
VCC_AXG_NCTF_23
VCC_AXG_NCTF_24
VCC_AXG_NCTF_25
VCC_AXG_NCTF_26
VCC_AXG_NCTF_27
VCC_AXG_NCTF_28
VCC_AXG_NCTF_29
VCC_AXG_NCTF_30
VCC_AXG_NCTF_31
VCC_AXG_NCTF_32
VCC_AXG_NCTF_33
VCC_AXG_NCTF_34
VCC_AXG_NCTF_35
VCC_AXG_NCTF_36
VCC_AXG_NCTF_37
VCC_AXG_NCTF_38
VCC_AXG_NCTF_39
VCC_AXG_NCTF_40
VCC_AXG_NCTF_41
VCC_AXG_NCTF_42
VCC_AXG_NCTF_43
VCC_AXG_NCTF_44
VCC_AXG_NCTF_45
VCC_AXG_NCTF_46
VCC_AXG_NCTF_47
VCC_AXG_NCTF_48

VCC GFX NCTFVCC SM LF

VCC_AXG_NCTF_49
VCC_AXG_NCTF_50
VCC_AXG_NCTF_51
VCC_AXG_NCTF_52
VCC_AXG_NCTF_53
VCC_AXG_NCTF_54
VCC_AXG_NCTF_55
VCC_AXG_NCTF_56
VCC_AXG_NCTF_57
VCC_AXG_NCTF_58
VCC_AXG_NCTF_59
VCC_AXG_NCTF_60
VCC_AXG_NCTF_61
VCC_AXG_NCTF_62
VCC_AXG_NCTF_63
VCC_AXG_NCTF_64
VCC_AXG_NCTF_65
VCC_AXG_NCTF_66
VCC_AXG_NCTF_67
VCC_AXG_NCTF_68
VCC_AXG_NCTF_69
VCC_AXG_NCTF_70
VCC_AXG_NCTF_71
VCC_AXG_NCTF_72
VCC_AXG_NCTF_73
VCC_AXG_NCTF_74
VCC_AXG_NCTF_75
VCC_AXG_NCTF_76
VCC_AXG_NCTF_77
VCC_AXG_NCTF_78
VCC_AXG_NCTF_79
VCC_AXG_NCTF_80
VCC_AXG_NCTF_81
VCC_AXG_NCTF_82
VCC_AXG_NCTF_83

VCC_SM_LF1
VCC_SM_LF2
VCC_SM_LF3
VCC_SM_LF4
VCC_SM_LF5
VCC_SM_LF6
VCC_SM_LF7

T17
T18
T19
T21
T22
T23
T25
U15
U16
U17
U19
U20
U21
U23
U26
V16
V17
V19
V20
V21
V23
V24
Y15
Y16
Y17
Y19
Y20
Y21
Y23
Y24
Y26
Y28
Y29
AA16
AA17
AB16
AB19
AC16
AC17
AC19
AD15
AD16
AD17
AF16
AF19
AH15
AH16
AH17
AH19
AJ16
AJ17
AJ19
AK16
AK19
AL16
AL17
AL19
AL20
AL21
AL23
AM15
AM16
AM19
AM20
AM21
AM23
AP15
AP16
AP17
AP19
AP20
AP21
AP23
AP24
AR20
AR21
AR23
AR24
AR26
V26
V28
V29
Y31

AW45
BC39
BE39
BD17
BD4
AW8
AT6

+1.05V_VCCP

VCCSM_LF1
VCCSM_LF2
VCCSM_LF3
VCCSM_LF4
VCCSM_LF5
VCCSM_LF6
VCCSM_LF7

220U_D2_4VY_R15M~D

220U_D2_4VY_R15M~D

1

C599

+

2

0.1U_0402_10V7K~D

C610

1

1

2

2

0.22U_0402_10V4Z~D

C623

C622

1

1

2

2

Layout Note:
370 mils from edge.

C611

0.22U_0402_10V4Z~D

1

C598

+

2

1U_0603_10V4Z~D

0.47U_0402_10V4Z~D

C609

1

2

Layout Note: Inside GMCH
cavity for VCC_AXG.

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

C621

1

2

0.1U_0402_10V7K~D

10U_0805_10V4Z~D

22U_0805_6.3VAM~D

C612

1

1

1

C600

C601

2

2

2

0.47U_0402_10V4Z~D

C624

1

1

2

2

1U_0402_6.3V4Z~D

1U_0402_6.3V4Z~D

C627

C626

C625

1

1

2

2

A A

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

Crestline(5 of 6)

LA-3301P

14 58Wednesday, February 28, 2007

1

1.0

of

5

U29I

A13

VSS_1

A15

VSS_2

A17

VSS_3

A24

VSS_4

AA21

VSS_5

AA24

VSS_6

AA29

VSS_7

AB20

VSS_8

AB23

D D

C C

B B

AB26
AB28
AB31
AC10
AC13

AC39
AC43
AC47

AD21
AD26
AD29

AD41
AD45
AD49

AD50
AE10

AE14
AF20

AF23
AF24
AF31

AG2
AG38
AG43
AG47
AG50

AH40
AH41

AJ11
AJ13
AJ21
AJ24
AJ29
AJ32
AJ43
AJ45

AJ49
AK20
AK21
AK26
AK28
AK31
AK51

AM11
AM13

AM3

AM4
AM41
AM45

AN38
AN39
AN43

AP48
AP50
AR11

AR39
AR44
AR47

AT10
AT14
AT41
AT49

AU23
AU29

AU36
AU49
AU51
AV39
AV48

AW1
AW12
AW16

VSS_9
VSS_10
VSS_11
VSS_12
VSS_13
VSS_14

AC3

VSS_15
VSS_16
VSS_17
VSS_18

AD1

VSS_19
VSS_20
VSS_21
VSS_22

AD3

VSS_23
VSS_24
VSS_25
VSS_26

AD5

VSS_27
VSS_28

AD8

VSS_29
VSS_30
VSS_31

AE6

VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41

AH3

VSS_42
VSS_43
VSS_44

AH7

VSS_45

AH9

VSS_46
VSS_47
VSS_48
VSS_49
VSS_50
VSS_51
VSS_52
VSS_53
VSS_54
VSS_55
VSS_56
VSS_57
VSS_58
VSS_59
VSS_60
VSS_61

AL1

VSS_62
VSS_63
VSS_64
VSS_65
VSS_66
VSS_67
VSS_68

AN1

VSS_69
VSS_70
VSS_71
VSS_72

AN5

VSS_73

AN7

VSS_74

AP4

VSS_75
VSS_76
VSS_77
VSS_78

AR2

VSS_79
VSS_80
VSS_81
VSS_82

AR7

VSS_83
VSS_84
VSS_85
VSS_86
VSS_87

AU1

VSS_88
VSS_89
VSS_90

AU3

VSS_91
VSS_92
VSS_93
VSS_94
VSS_95
VSS_96
VSS_97
VSS_98
VSS_99

VSS

LE88CLGM A0 QM20_FCBGA1299~D

VSS_100
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105
VSS_106
VSS_107
VSS_108
VSS_109
VSS_110
VSS_111
VSS_112
VSS_113
VSS_114
VSS_115
VSS_116
VSS_117
VSS_118
VSS_119
VSS_120
VSS_121
VSS_122
VSS_123
VSS_124
VSS_125
VSS_126
VSS_127
VSS_128
VSS_129
VSS_130
VSS_131
VSS_132
VSS_133
VSS_134
VSS_135
VSS_136
VSS_137
VSS_138
VSS_139
VSS_140
VSS_141
VSS_142
VSS_143
VSS_144
VSS_145
VSS_146
VSS_147
VSS_148
VSS_149
VSS_150
VSS_151
VSS_152
VSS_153
VSS_154
VSS_155
VSS_156
VSS_157
VSS_158
VSS_159
VSS_160
VSS_161
VSS_162
VSS_163
VSS_164
VSS_165
VSS_166
VSS_167
VSS_168
VSS_169
VSS_170
VSS_171
VSS_172
VSS_173
VSS_174
VSS_175
VSS_176
VSS_177
VSS_178
VSS_179
VSS_180
VSS_181
VSS_182
VSS_183
VSS_184
VSS_185
VSS_186
VSS_187
VSS_188
VSS_189
VSS_190
VSS_191
VSS_192
VSS_193
VSS_194
VSS_195
VSS_196
VSS_197
VSS_198

AW24
AW29
AW32
AW5
AW7
AY10
AY24
AY37
AY42
AY43
AY45
AY47
AY50
B10
B20
B24
B29
B30
B35
B38
B43
B46
B5
B8
BA1
BA17
BA18
BA2
BA24
BB12
BB25
BB40
BB44
BB49
BB8
BC16
BC24
BC25
BC36
BC40
BC51
BD13
BD2
BD28
BD45
BD48
BD5
BE1
BE19
BE23
BE30
BE42
BE51
BE8
BF12
BF16
BF36
BG19
BG2
BG24
BG29
BG39
BG48
BG5
BG51
BH17
BH30
BH44
BH46
BH8
BJ11
BJ13
BJ38
BJ4
BJ42
BJ46
BK15
BK17
BK25
BK29
BK36
BK40
BK44
BK6
BK8
BL11
BL13
BL19
BL22
BL37
BL47
C12
C16
C19
C28
C29
C33
C36
C41

4

C46
C50

C7
D13
D24

D3
D32
D39
D45
D49
E10
E16
E24
E28
E32
E47
F19
F36

F4
F40
F50

G1
G13
G16
G19
G24
G28
G29
G33
G42
G45
G48

G8
H24
H28

H4
H45
J11
J16

J2
J24
J28
J33
J35
J39

K12
K47

K8

L1
L17
L20
L24
L28

L3
L33
L49

M28
M42
M46
M49

M5

M50

M9
N11
N14
N17
N29
N32
N36
N39
N44
N49

N7

P19

P2

P23

P3

P50

R49

T39
T43

T47
U41
U45
U50

V2
V3

U29J

VSS_199
VSS_200
VSS_201
VSS_202
VSS_203
VSS_204
VSS_205
VSS_206
VSS_207
VSS_208
VSS_209
VSS_210
VSS_211
VSS_212
VSS_213
VSS_214
VSS_215
VSS_216
VSS_217
VSS_218
VSS_219
VSS_220
VSS_221
VSS_222
VSS_223
VSS_224
VSS_225
VSS_226
VSS_227
VSS_228
VSS_229
VSS_230
VSS_231
VSS_232
VSS_233
VSS_234
VSS_235
VSS_236
VSS_237
VSS_238
VSS_239
VSS_240
VSS_241
VSS_242
VSS_243

VSS_245
VSS_246
VSS_247
VSS_248
VSS_249
VSS_250
VSS_251
VSS_252
VSS_253
VSS_254
VSS_255
VSS_256
VSS_257
VSS_258
VSS_259
VSS_260
VSS_261
VSS_262
VSS_263
VSS_264
VSS_265
VSS_266
VSS_267
VSS_268
VSS_269
VSS_270
VSS_271
VSS_272
VSS_273
VSS_274
VSS_275
VSS_276
VSS_277
VSS_278
VSS_279
VSS_280
VSS_281
VSS_282
VSS_283
VSS_284
VSS_285
VSS_286

LE88CLGM A0 QM20_FCBGA1299~D

VSS

3

W11

VSS_287

W39

VSS_288

W43

VSS_289

W47

VSS_290

W5

VSS_291

W7

VSS_292

Y13

VSS_293

Y2

VSS_294

Y41

VSS_295

Y45

VSS_296

Y49

VSS_297

Y5

VSS_298

Y50

VSS_299

Y11

VSS_300

P29

VSS_301

T29

VSS_302

T31

VSS_303

T33

VSS_304

R28

VSS_305

AA32

VSS_306

AB32

VSS_307

AD32

VSS_308

AF28

VSS_309

AF29

VSS_310

AT27

VSS_311

AV25

VSS_312

H50

VSS_313

2

1

A A

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

Crestline(6 of 6)

LA-3301P

15 58Wednesday, February 14, 2007

1

1.0

of

5

DDR_A_DQS#[0..7]11

DDR_A_D[0..63]11
DDR_A_DM[0..7]11
DDR_A_DQS[0..7]11

DDR_A_MA[0..14]11

D D

+1.8V_SUS

2.2U_0603_6.3V6K~D

2.2U_0603_6.3V6K~D
C133

1

2

0.1U_0402_16V4Z~D

C C

+0.9V_DDR_VTT

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

B B

A A

1

1

2

2

C137

C136

DDR_A_MA1
DDR_A_MA3

56_0404_4P2R_5%~D

DDR_A_BS0
DDR_A_MA10

56_0404_4P2R_5%~D

DDR_A_RAS#
DDR_CS0_DIMMA#

56_0404_4P2R_5%~D

DDR_A_CAS#
DDR_A_WE#

56_0404_4P2R_5%~D

M_ODT1
DDR_CS1_DIMMA#

56_0404_4P2R_5%~D

DDR_CKE1_DIMMA

DDR_CKE0_DIMMA
DDR_A_BS2

56_0404_4P2R_5%~D

0.1U_0402_16V4Z~D

1

2

C138

5

2.2U_0603_6.3V6K~D

C132

C437

1

1

2

2

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D
C131

C130

1

1

2

2

Layout Note:
Place one cap close to every 2 pullup
resistors terminated to +0.9V_DDR_VTT

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

1

1

2

2

C139

C140

+0.9V_DDR_VTT

RN4

1 4
2 3

RN3

1 4
2 3

RN9

1 4
2 3

RN2

1 4
2 3

RN1

1 4
2 3

12

R223
56_0402_5%~D

RN7

2 3
1 4

2.2U_0603_6.3V6K~D

1

2

1

2

C141

C119

RN6

RN12

RN5

RN11

RN10

RN8

RN13

C117

1

2

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

1

2

C104

2.2U_0603_6.3V6K~D

1

2

14
23

56_0404_4P2R_5%~D

14
23

56_0404_4P2R_5%~D

14
23

56_0404_4P2R_5%~D

14
23

56_0404_4P2R_5%~D

14
23

56_0404_4P2R_5%~D

14
23

56_0404_4P2R_5%~D

14
23

56_0404_4P2R_5%~D

C116

1

2

C118

0.1U_0402_16V4Z~D

1

2

C105

DDR_A_MA9
DDR_A_MA12

DDR_A_MA7
DDR_A_MA6

DDR_A_MA5
DDR_A_MA8

DDR_A_MA4
DDR_A_MA2

DDR_A_MA0
DDR_A_BS1

M_ODT0
DDR_A_MA13

DDR_A_MA14
DDR_A_MA11

0.1U_0402_16V4Z~D

Layout Note:
Place near JDIM1

0.1U_0402_16V4Z~D

1

1

2

2

C107

C106

4

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

1

1

2

2

C109

C108

Layout Note:
Place these resistor
closely DIMM0,all
trace length<750 mil

Layout Note:
Place these resistor
closely DIMM0,all
trace length
Max=1.3"

4

3

+1.8V_SUS +1.8V_SUS

ON TOP SIDE

JDIM2

1

VREF

3

2.2U_0603_6.3V6K~D
C115

VSS

5

DQ0

7

DQ1

9

VSS

11

DQS0#

13

DQS0

15

VSS

17

DQ2

19

DQ3

21

VSS

23

DQ8

25

DQ9

27

VSS

29

DQS1#

31

DQS1

33

VSS

35

DQ10

37

DQ11

39

VSS

41

VSS

43

DQ16

45

DQ17

47

VSS

49

DQS2#

51

DQS2

53

VSS

55

DQ18

57

DQ19

59

VSS

61

DQ24

63

DQ25

65

VSS

67

DM3

69

NC

71

VSS

73

DQ26

75

DQ27

77

VSS

79

CKE0

81

VDD

83

NC

85

BA2

87

VDD

89

A12

91

A9

93

A8

95

VDD

97

A5

99

A3

101

A1

103

VDD

105

A10/AP

107

BA0

109

WE#

111

VDD

113

CAS#

115

NC/S1#

117

VDD

119

NC/ODT1

121

VSS

123

DQ32

125

DQ33

127

VSS

129

DQS4#

131

DQS4

133

VSS

135

DQ34

137

DQ35

139

VSS

141

DQ40

143

DQ41

145

VSS

147

DM5

149

VSS

151

DQ42

153

DQ43

155

VSS

157

DQ48

159

DQ49

161

VSS

163

NC,TEST

165

VSS

167

DQS6#

169

DQS6

171

VSS

173

DQ50

175

DQ51

177

VSS

179

DQ56

181

DQ57

183

VSS

185

DM7

187

VSS

189

DQ58

191

DQ59

193

VSS

195

SDA

197

SCL

199

VDDSPD

201

GND

TYCO_1470815-2~D

RESERVE

DDR_A_D0
DDR_A_D5

DDR_A_DQS#0
DDR_A_DQS0

DDR_A_D3
DDR_A_D7

DDR_A_D13
DDR_A_D12

DDR_A_DQS#1
DDR_A_DQS1

DDR_A_D10

DDR_A_D17
DDR_A_D21

DDR_A_DQS#2
DDR_A_DQS2

DDR_A_D22
DDR_A_D23

DDR_A_D29

DDR_A_DM3

DDR_A_D27

DDR_A_D30

DDR_CKE0_DIMMA10

DDR_A_BS211

DDR_A_BS011
DDR_A_WE#11

DDR_A_CAS#11

DDR_CS1_DIMMA#10

M_ODT110

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

1

1

2

2

C707

C110

MEM_SDATA17,23
MEM_SCLK17,23

Non-iAMT

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

DDR_CKE0_DIMMA

DDR_A_BS2
DDR_A_MA12

DDR_A_MA9 DDR_A_MA7
DDR_A_MA8

DDR_A_MA5
DDR_A_MA3
DDR_A_MA1

DDR_A_MA10
DDR_A_BS0
DDR_A_WE#

DDR_A_CAS#
DDR_CS1_DIMMA#

M_ODT1
DDR_A_D33

DDR_A_D32
DDR_A_DQS#4

DDR_A_DQS4
DDR_A_D34

DDR_A_D39
DDR_A_D41

DDR_A_D40
DDR_A_DM5
DDR_A_D46

DDR_A_D43 DDR_A_D47
DDR_A_D49 DDR_A_D48

DDR_A_D52

DDR_A_DQS#6
DDR_A_DQS6

DDR_A_D51

DDR_A_D60
DDR_A_D56

DDR_A_DM7
DDR_A_D58

MEM_SDATA
MEM_SCLK

+3.3V_RUN

0.1U_0402_16V4Z~D
C113

1

1

2

2

NC/CKE1

DIMMA

2

VSS
DQ4
DQ5
VSS
DM0
VSS
DQ6
DQ7

VSS
DQ12
DQ13

VSS

DM1

VSS

CK0#

VSS
DQ14
DQ15

VSS

VSS
DQ20
DQ21

VSS

DM2

VSS
DQ22
DQ23

VSS
DQ28
DQ29

VSS

DQS3#

DQS3

VSS
DQ30
DQ31

VSS

VDD

NC/A15
NC/A14

VDD

VDD

VDD

RAS#

VDD
ODT0

NC/A13

VDD

VSS
DQ36
DQ37

VSS

DM4

VSS
DQ38
DQ39

VSS
DQ44
DQ45

VSS

DQS5#

DQS5

VSS
DQ46
DQ47

VSS
DQ52
DQ53

VSS

CK1#

VSS

DM6

VSS
DQ54
DQ55

VSS
DQ60
DQ61

VSS

DQS7#

DQS7

VSS
DQ62
DQ63

VSS

SAO

GND

2

1

V_DDR_MCH_REF

2

DDR_A_D4

4

DDR_A_D6

6
8

DDR_A_DM0

10
12

DDR_A_D1

14

DDR_A_D2

16
18

DDR_A_D9

20

DDR_A_D8

22
24

DDR_A_DM1

26
28

M_CLK_DDR0

30

CK0

NC

A11

A7
A6

A4
A2

A0
BA1
S0#

NC

CK1

SA1

M_CLK_DDR#0

32
34

DDR_A_D15

36

DDR_A_D14DDR_A_D11

38
40

42

DDR_A_D20

44

DDR_A_D16

46
48

PM_EXTTS#0

50

DDR_A_DM2

52
54

DDR_A_D18

56

DDR_A_D19

58
60

DDR_A_D28

62

DDR_A_D24DDR_A_D25

64
66

DDR_A_DQS#3

68

DDR_A_DQS3

70
72

DDR_A_D26

74

DDR_A_D31

76
78

DDR_CKE1_DIMMA

80
82
84

DDR_A_MA14

86
88

DDR_A_MA11

90
92

DDR_A_MA6

94
96

DDR_A_MA4

98

DDR_A_MA2

100

DDR_A_MA0

102
104

DDR_A_BS1

106

DDR_A_RAS#

108

DDR_CS0_DIMMA#

110
112

M_ODT0

114

DDR_A_MA13

116
118
120
122

DDR_A_D36

124

DDR_A_D37

126
128

DDR_A_DM4

130
132

DDR_A_D35

134

DDR_A_D38

136
138

DDR_A_D44

140

DDR_A_D45

142
144

DDR_A_DQS#5

146

DDR_A_DQS5

148
150

DDR_A_D42

152
154
156
158

DDR_A_D53

160
162

M_CLK_DDR1

164

M_CLK_DDR#1

166
168

DDR_A_DM6

170
172

DDR_A_D50

174

DDR_A_D55DDR_A_D54

176
178

DDR_A_D61

180

DDR_A_D57

182
184

DDR_A_DQS#7

186

DDR_A_DQS7

188
190

DDR_A_D59DDR_A_D62

192

DDR_A_D63

194
196

R122 10K_0402_5%~D

198
200

202

1 2

R127 10K_0402_5%~D

1 2

V_DDR_MCH_REF

2.2U_0603_6.3V6K~D

1

C114

2

M_CLK_DDR0 10

M_CLK_DDR#0 10

PM_EXTTS#0 10

DDR_CKE1_DIMMA 10

DDR_A_BS1 11

DDR_A_RAS# 11
DDR_CS0_DIMMA# 10

M_ODT0 10

M_CLK_DDR1 10

M_CLK_DDR#1 10

0.1U_0402_16V4Z~D

1

C112

2

DELL CONFIDENTIAL/PROPRIETARY

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

DDRII-SODIMM SLOT1

LA-3301P

16 58Monday, February 26, 2007

1

1.0

of

5

DDR_B_DQS#[0..7]11

DDR_B_D[0..63]11
DDR_B_DM[0..7]11
DDR_B_DQS[0..7]11

DDR_B_MA[0..14]11

D D

C C

B B

A A

+1.8V_SUS

+0.9V_DDR_VTT

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

1

2

C456

DDR_B_MA1
DDR_B_MA3

56_0404_4P2R_5%~D

DDR_B_BS0
DDR_B_MA10

56_0404_4P2R_5%~D

DDR_B_MA0
DDR_B_BS1

56_0404_4P2R_5%~D

DDR_B_RAS#
DDR_CS2_DIMMB#

56_0404_4P2R_5%~D

DDR_B_CAS#
DDR_B_WE#

56_0404_4P2R_5%~D

DDR_CKE3_DIMMB

DDR_CS3_DIMMB#
M_ODT3

56_0404_4P2R_5%~D

2.2U_0603_6.3V6K~D
C439

1

2

0.1U_0402_16V4Z~D

C434

1

2

Layout Note:
Place one cap close to every 2 pullup
resistors terminated to +0.9V_DDR_VTT

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

1

1

2

2

C454

C455

+0.9V_DDR_VTT

RN23

1 4
2 3

RN24

1 4
2 3

RN17

1 4
2 3

RN18

1 4
2 3

RN25

1 4
2 3

12

R312
56_0402_5%~D

RN26

2 3
1 4

5

C412

C440

1

2

0.1U_0402_16V4Z~D

1

2

0.1U_0402_16V4Z~D

1

2

C453

C433

RN21

RN14

RN22

RN15

RN16

RN19

RN20

1

2

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

1

2

C452

1

2

C413

1

2

1

2

C451

DDR_B_MA9

14

DDR_B_MA12

23

56_0404_4P2R_5%~D

DDR_B_MA14

14

DDR_B_MA11

23

56_0404_4P2R_5%~D

DDR_B_MA5

14

DDR_B_MA8

23

56_0404_4P2R_5%~D

DDR_B_MA7

14

DDR_B_MA6

23

56_0404_4P2R_5%~D

DDR_B_MA4

14

DDR_B_MA2

23

56_0404_4P2R_5%~D

M_ODT2

14

DDR_B_MA13

23

56_0404_4P2R_5%~D

DDR_B_BS2

14

DDR_CKE2_DIMMB

23

56_0404_4P2R_5%~D

2.2U_0603_6.3V6K~D

2.2U_0603_6.3V6K~D

2.2U_0603_6.3V6K~D

2.2U_0603_6.3V6K~D

C438

1

2

0.1U_0402_16V4Z~D
C414

1

2

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

1

2

C450

Layout Note:
Place near JDIM2

C411

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

1

1

2

2

C410

C409

4

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

1

2

C408

Layout Note:
Place these resistor
closely DIMM0,all
trace length<750 mil

Layout Note:
Place these resistor
closely DIMM0,all
trace length
Max=1.3"

0.1U_0402_16V4Z~D

1

1

2

2

C406

C407

4

3

ON BOTTOM SIDE

DDR_B_D0
DDR_B_DQS#0

DDR_B_DQS0
DDR_B_D6

DDR_B_D7
DDR_B_D8

DDR_B_D9
DDR_B_DQS#1

DDR_B_DQS1
DDR_B_D14

DDR_B_D15

DDR_B_D16
DDR_B_D21

DDR_B_DQS#2
DDR_B_DQS2

DDR_B_D19
DDR_B_D18

DDR_B_D24 DDR_B_D28
DDR_B_D25

DDR_B_DM3

DDR_B_D26
DDR_B_D27

DDR_CKE2_DIMMB10

DDR_B_BS211

DDR_B_BS011
DDR_B_WE#11

DDR_B_CAS#11

DDR_CS3_DIMMB#10

1

2

C405

M_ODT310

MEM_SDATA16,23
MEM_SCLK16,23

Non-iAMT

DDR_CKE2_DIMMB

DDR_B_BS2
DDR_B_MA12

DDR_B_MA9
DDR_B_MA8

DDR_B_MA5
DDR_B_MA3
DDR_B_MA1

DDR_B_MA10
DDR_B_BS0
DDR_B_WE#

DDR_B_CAS#
DDR_CS3_DIMMB#

M_ODT3

DDR_B_D36
DDR_B_DQS#4

DDR_B_DQS4

DDR_B_D34
DDR_B_D40

DDR_B_D41
DDR_B_DM5

DDR_B_D42
DDR_B_D53

DDR_B_D49 DDR_B_D48

DDR_B_DQS#6
DDR_B_DQS6

DDR_B_D55
DDR_B_D50

DDR_B_D56
DDR_B_D60

DDR_B_DM7
DDR_B_D58

DDR_B_D59
MEM_SDATA

MEM_SCLK

+3.3V_RUN

2.2U_0603_6.3V6K~D

0.1U_0402_16V4Z~D

C431

1

1

2

2

C429

JDIM1

1

VREF

3

VSS

5

DQ0

7

DQ1

9

VSS

11

DQS0#

13

DQS0

15

VSS

17

DQ2

19

DQ3

21

VSS

23

DQ8

25

DQ9

27

VSS

29

DQS1#

31

DQS1

33

VSS

35

DQ10

37

DQ11

39

VSS

41

VSS

43

DQ16

45

DQ17

47

VSS

49

DQS2#

51

DQS2

53

VSS

55

DQ18

57

DQ19

59

VSS

61

DQ24

63

DQ25

65

VSS

67

DM3

69

NC

71

VSS

73

DQ26

75

DQ27

77

VSS

79

CKE0

81

VDD

83

NC

85

BA2

87

VDD

89

A12

91

A9

93

A8

95

VDD

97

A5

99

A3

101

A1

103

VDD

105

A10/AP

107

BA0

109

WE#

111

VDD

113

CAS#

115

NC/S1#

117

VDD

119

NC/ODT1

121

VSS

123

DQ32

125

DQ33

127

VSS

129

DQS4#

131

DQS4

133

VSS

135

DQ34

137

DQ35

139

VSS

141

DQ40

143

DQ41

145

VSS

147

DM5

149

VSS

151

DQ42

153

DQ43

155

VSS

157

DQ48

159

DQ49

161

VSS

163

NC,TEST

165

VSS

167

DQS6#

169

DQS6

171

VSS

173

DQ50

175

DQ51

177

VSS

179

DQ56

181

DQ57

183

VSS

185

DM7

187

VSS

189

DQ58

191

DQ59

193

VSS

195

SDA

197

SCL

199

VDDSPD

201

GND

TYCO_1565917-4~D

DIMMB

STANDARD

DQ4
DQ5

DM0
DQ6

DQ7

DQ12
DQ13

DM1

CK0#
DQ14

DQ15

DQ20
DQ21

DM2

DQ22
DQ23

DQ28
DQ29

DQS3#

DQS3

DQ30
DQ31

NC/CKE1

VDD
NC/A15
NC/A14

VDD

VDD

VDD

RAS#

VDD

ODT0

NC/A13

VDD

DQ36
DQ37

DM4

DQ38
DQ39

DQ44
DQ45

DQS5#

DQS5

DQ46
DQ47

DQ52
DQ53

CK1#

DM6

DQ54
DQ55

DQ60
DQ61

DQS7#

DQS7

DQ62
DQ63

SAO

GND

VSS

VSS
VSS

VSS

VSS
VSS

CK0
VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

BA1

VSS

VSS
VSS

VSS

VSS

VSS

VSS

VSS
CK1

VSS
VSS

VSS

VSS

VSS

VSS
SA1

NC

A11

A7
A6

A4
A2
A0

S0#

NC

2

+1.8V_SUS+1.8V_SUS V_DDR_MCH_REF

2

DDR_B_D5

4

DDR_B_D4DDR_B_D1

6
8

DDR_B_DM0

10
12

DDR_B_D2

14

DDR_B_D3

16
18

DDR_B_D13

20

DDR_B_D12

22
24

DDR_B_DM1

26
28

M_CLK_DDR2

30

M_CLK_DDR#2

32
34

DDR_B_D10

36

DDR_B_D11

38
40

42

DDR_B_D20

44

DDR_B_D17

46
48

PM_EXTTS#1

50

DDR_B_DM2

52
54

DDR_B_D22

56

DDR_B_D23

58
60
62

DDR_B_D29

64
66

DDR_B_DQS#3

68

DDR_B_DQS3

70
72

DDR_B_D30

74

DDR_B_D31

76
78

DDR_CKE3_DIMMB

80
82
84

DDR_B_MA14

86
88

DDR_B_MA11

90

DDR_B_MA7

92

DDR_B_MA6

94
96

DDR_B_MA4

98

DDR_B_MA2

100

DDR_B_MA0

102
104

DDR_B_BS1

106

DDR_B_RAS#

108

DDR_CS2_DIMMB#

110
112

M_ODT2

114

DDR_B_MA13

116
118
120
122

DDR_B_D33DDR_B_D32

124

DDR_B_D37

126
128

DDR_B_DM4

130
132

DDR_B_D38

134

DDR_B_D39DDR_B_D35

136
138

DDR_B_D44

140

DDR_B_D45

142
144

DDR_B_DQS#5

146

DDR_B_DQS5

148
150

DDR_B_D43DDR_B_D46

152

DDR_B_D47

154
156

DDR_B_D52

158
160
162

M_CLK_DDR3

164

M_CLK_DDR#3

166
168

DDR_B_DM6

170
172

DDR_B_D54

174

DDR_B_D51

176
178

DDR_B_D57

180

DDR_B_D61

182
184

DDR_B_DQS#7

186

DDR_B_DQS7

188
190

DDR_B_D62

192

DDR_B_D63

194
196
198
200

202

10K_0402_5%~D

12

M_CLK_DDR2 10

M_CLK_DDR#2 10

DDR_CKE3_DIMMB 10

DDR_B_BS1 11

DDR_B_RAS# 11
DDR_CS2_DIMMB# 10

M_ODT2 10

M_CLK_DDR3 10

M_CLK_DDR#3 10

R243

10K_0402_5%~D

R241

V_DDR_MCH_REF

2.2U_0603_6.3V6K~D

1

C447

2

PM_EXTTS#1 10

+3.3V_RUN

12

1

0.1U_0402_16V4Z~D

1

C436

2

Non-iAMT

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

DDRII-SODIMM SLOT2

LA-3301P

17 58Monday, February 26, 2007

1

1.0

of

5

+3.3V_SUS

12

R423

8.2K_0402_5%~D

2

Q38

2

Q39

B

+3.3V_SUS

B

C

E

3 1

12

C

E

3 1

THERMATRIP1#

1

C628

0.1U_0402_16V4Z~D

2

R426

8.2K_0402_5%~D

THERMATRIP2#

1

C632

0.1U_0402_16V4Z~D

2

+1.05V_VCCP

R425

D D

H_THERMTRIP#7

THERMTRIP_MCH#10

2.2K_0402_5%~D

1 2

MMST3904-7-F_SOT323-3~D

+1.05V_VCCP

R427

2.2K_0402_5%~D

1 2

MMST3904-7-F_SOT323-3~D

Place under CPU

C C

C633

@

2200P_0402_50V7K~D

Place C633 close to the Q40 as possible

Place C636 close to the Guardian pins as possible

H_THERMDA7

470P_0402_50V7K~D

H_THERMDC7

+3.3V_SUS

B B

+3.3V_SUS

R196

@

1 2

10K_0402_5%~D

@

1 2

10K_0402_5%~D

A A

R194

MDC_RST_DIS#

SIO_GFX_PWR

5

+3.3V_SUS

0.1U_0402_16V4Z~D

R428

1 2

49.9_0603_1%~D

1

C639

2

C100

2200P_0402_50V7K~D

2

1

C636

1

C637

0.1U_0402_16V4Z~D

2

2

1

+3.3V_SUS

12

C

R433

8.2K_0402_5%~D

THERMATRIP3#

4

RB751S40T1_SOD523-2~D

2

B

E

Q40

3 1

MMST3904-7-F_SOT323-3~D

1

2

+RTC_CELL

12

R436
332K_0402_1%~D

12

R438
118K_0402_1%~D

4

D19

@

+3VSUS_THRM

1

C638

2

0.1U_0402_16V4Z~D

1

C203

0.1U_0402_16V4Z~D

2

@

1

C630

2

2 1

2200P_0402_50V7K~D

2

C634

1

SUSPWROK42
ICH_PWRGD#42

R437

1 2

1K_0402_5%~D

MDC_RST_DIS#33

AUDIO_AVDD_ON27

3

FAN1 Control and Tachometer

+3.3V_RUN

12

R424
10K_0402_5%~D

12

R414
0_0402_5%~D

+FAN1_VOUT

22U_0805_6.3VAM~D

Place C634 close to the
Guardian pins as possible

FAN1_TACH_FB

THRM_SMBDAT39,49
THRM_SMBCLK39,49

REM_DIODE1_N

1 2

R429 1K_0402_5%~D

1 2

R432 1K_0402_5%~D

THERMATRIP1#
THERMATRIP2#
THERMATRIP3#

+FAN1_VOUT

MDC_RST_DIS#
SIO_GFX_PWR
5V_CAL_SIO#

AUDIO_AVDD_ON

FAN1_TACH 39

11
12

38
37

41
40

35
21
23
16
17
18
19
42
26
34

7
8

39

10
13
14
15
22
36
49

SMBUS ADDRESS : 2F

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

JFAN1

1

1

2

2

3

3

MOLEX_53398-0371~D

U31

SMDATA
SMBCLK

DP1
DN1

DP2
DN2

3V_SUS
RTC_PWR3V
VSUS_PWRGD
3V_PWROK#
THERMTRIP1#
THERMTRIP2#
THERMTRIP3#
VSET
XEN
VSS
FAN_OUT

FAN_OUT
FAN_DAC1

GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6/FAN_DAC2
PAD_GND

VCP1
VCP2

ATF_INT#

POWER_SW#

ACAVAIL_CLR

THERMTRIP_SIO

SYS_SHDN#

LDO_SHDN#/ADDR

LDO_POK
LDO_SET
LDO_OUT

LDO_OUT

LDO_IN
LDO_IN

VDD_3V
VDD_5V

VDD_5V

EMC4001_QFN48~D

1

C645

2

10U_0805_10V4Z~D

DP3
DN3

DP4
DN4

DP5
DN5

43
46

45
44

48
47

2
1

20
3
4
25
24
27
33
28
32

31

30
29

9
5

6

1

C646

2

VCP2

VCP2
REM_DIODE3_PREM_DIODE1_P

REM_DIODE3_N
REM_DIODE4_P

REM_DIODE4_N

7.5K_0402_5%~D

LDO_SET

+3V_LDOIN

+5V_RUN

0.1U_0402_16V4Z~D

2

VSET=

VSET =

+5V_SUS

12

R771

2.21K_0603_1%~D

1

C750

2

2200P_0402_50V7K~D

PWR_MON 48

Place cap close to the
Guardian pins as possible.

1

C649
2200P_0402_50V7K~D

2

1

C418

2

2200P_0402_50V7K~D

ATF_INT#

ATF_INT# 38

POWER_SW# 39,40

ACAV_IN 39,49,50

R434

12

+3.3V_SUS

1

1

10U_0805_10V4Z~D

1U_0603_10V4Z~D

10U_0805_10V4Z~D

2

1

2

1

2

@

0.1U_0402_16V4Z~D

2

1

C644

0.1U_0402_16V4Z~D

2

1

C648

0.1U_0402_16V4Z~D

2

C640

@

C643

C647

2

1

R438

x 3.3V

=0.865V

R436+R438

Tp-70

=> Tp = 88.2 C

21

12

R772
10K_0603_1%_TSM1A103F34D3RZ~D

Q102

13

D

2N7002W-7-F_SOT323-3~D

2

G

S

This thermistor circuit is located near
Top side DDR connector.

REM_DIODE3_N, REM_DIODE3_P routing together.
Trace width / Spacing = 10 / 10 mil

C

Q41

2

B

MMST3904-7-F_SOT323-3~D

E

2

B

E

R96
10K_0402_5%~D

10K_0402_5%~D

R431

@

+2.5V_RUN

R439

12

+3.3V_RUN

3 1

C

Q19
MMST3904-7-F_SOT323-3~D

3 1

12

R430

10K_0402_5%~D

+3.3V_RUN

Q41 Place near the
bottom SODIMM

C641

0_1210_5%~D

+3.3V_SUS

12

R773
10K_0402_5%~D

5V_CAL_SIO#

1

C650
2200P_0402_50V7K~D

2

@

Place C650
close to Q41

1

C904

@

2200P_0402_50V7K~D

2

Diode circui t at DP4/DN4 is
used for skin temp sensor
(placed optim ally between

+3.3V_SUS

CPU, MCH and MEM).

12

+3.3V_ALW

THERMTRIP_SIO
THERM_STP# 45

12

+RTC_CELL

2.5V_RUN_PWRGD 42

LDO_SET

Voltage margining
circuit for LDO output.
For Vmargin, stuff
Ra=31.6K and Rb=30K.
Rb=1K for production

DELL CONFIDENTIAL/PROPRIETARY

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

FAN & Thermal Sensor

LA-3301P

1

+2.5V_RUN

12

12

18 58Wednesday, March 07, 2007

31.6K_0402_1%~D

@

R485

Ra

1K_0402_1%~D

R441

Rb

1.0

of

5

D D

JLVDS

45

MGND1

46

MGND2

47

MGND3

48

MGND4

49

MGND5

50

MGND6

51

MGND7

52

MGND8

53

MGND9

54

MGND10

55

MGND11

56

NC

57

C C

TXLCLKOUT-

NC

TXLCLKOUT+

PANEL_I2C_CLK

PANEL_I2C_DAT

PNL_SLFTST
LCDPWR_SRC
LCDPWR_SRC
LCDPWR_SRC

PBAT_SMBCLK

PBAT_SMBDAT

LAMP_START

IPEX_20330-044E-11F~D

TXUCLKUT-

TXUCLKUT+

GND1

TXUOUT2-

TXUOUT2+

GND2

TXUOUT1-

TXUOUT1+

GND3

TXUOUT0-

TXUOUT0+

GND4

GND5
TXLOUT2­TXLOUT2+

GND6
TXLOUT1­TXLOUT1+

GND7
TXLOUT0­TXLOUT0+

GND8

GND9

VEDID

GND10
LCDVDD1
LCDVDD2

GND11

FPBACK

GND12

GND13

+5V_ALWF

GND14

44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

LCD_BCLK­LCD_BCLK+

LCD_B2­LCD_B2+

LCD_B1­LCD_B1+

LCD_B0­LCD_B0+

LCD_ACLK­LCD_ACLK+

LCD_A2­LCD_A2+

LCD_A1­LCD_A1+

LCD_A0­LCD_A0+

R808 0_0603_5%~D

1 2

R809 0_0603_5%~D

1 2

LCD_TST

R810 0_0603_5%~D
R811 0_0603_5%~D

LAMP_STAT#

1 2
1 2

LCD_TST 38

4

LCD_BCLK- 12
LCD_BCLK+ 12

LCD_B2- 12
LCD_B2+ 12

LCD_B1- 12
LCD_B1+ 12

LCD_B0- 12
LCD_B0+ 12

LCD_ACLK- 12
LCD_ACLK+ 12

LCD_A2- 12
LCD_A2+ 12

LCD_A1- 12
LCD_A1+ 12

LCD_A0- 12
LCD_A0+ 12

0.1U_0402_16V4Z~D

T28 PAD~D

LCD_DDCCLK 12
LCD_DDCDATA 12

C45

1

1

C44

2

2

LCD_SMBCLK 39
LCD_SMBDAT 39

+3.3V_RUN

+LCDVDD

0.1U_0402_16V4Z~D

1

C176

0.1U_0402_16V4Z~D

2

+3.3V_RUN

+5V_ALW

3

LCD_VCC_TEST_EN39

ENVDD12

12

R155

@

10K_0402_5%~D

1 2

R156 0_0402_5%~D

Populate R156 for DPST,
implementation only.

BIA_PWM 12

+LCDVDD

Q9

D24

3

2N7002W-7-F_SOT323-3~D

1

2

BAT54CW_SOT323~D

1 2

R527

@

0_0402_5%~D

12

13

D

S

R26
470_0402_5%~D

2

G

2

+15V_ALW

12

R23
100K_0402_5%~D

1

O

I

G

DDTC124EUA-7-F_SOT323-3~D

3

2

Q11

SI3456BDV-T1-E3_TSOP6~D

12

R24
100K_0402_5%~D

13

D

Q8

S

+LCDVDD

2N7002W-7-F_SOT323-3~D

1

C30

2

+15V_ALW

2

G

Q7

4 5

0.1U_0603_50V4Z~D

D

S

G

3

12

R25

@

100K_0402_5%~D

6
2

1

+3.3V_RUN

1

C42

2

1

0.1U_0402_16V4Z~D

FDS4435BZ_SO8~D

1
2
3

R153

1 2

100K_0402_5%~D

RUN_ON37,39,41,42

Q24

4

D

1 3

2

8
7
6
5

S

G

40mil

Q25
2N7002W-7-F_SOT323-3~D

1

2

0.1U_0603_50V4Z~D

40mil

1

C463

2

2200P_0402_50V7K~D

+PWR_SRC

12

C173

1000P_0402_50V7K~D

R154
200K_0402_5%~D

Populate R155 for platform

B B

A A

1

2

+INV_PWR_SRC

C180

0.1U_0603_50V4Z~D

without DPST support. No
Stuff for Discrete DSPT
support due to back up
plan.

1

C427

2

+INV_PWR_SRC

1

C174

0.1U_0603_50V4Z~D

2

FDS4435: P CHANNAL

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

Internal LVDS

LA-3301P

19 58Wednesday, February 28, 2007

1

1.0

of

5

D D

4

3

2

1

D8

SDM10U45-7_SOD523-2~D

F3

@

0.12A_48V_NANOSMDC012F~D

+5V_RUN

21

12

12

R792
0_1206_5%~D

RED
DAT_DDC2

GREEN
JVGA_HS

BLUE
JVGA_VS

M_ID2#
CLK_DDC2

CRT_VCC

1

C151

2

0.01U_0402_16V7K~D

JCRT

6

11

1
7

12

2
8

13

14
10

15

SUYIN_070915FR015S201CU~D

16

17
3
9

4

5

D11
DA204U_SOT323~D

1

@

+3.3V_RUN

2

3

L11

CRT_RED12,36

CRT_GRN12,36

C C

CRT_BLU12,36

CRT_RED

CRT_GRN

CRT_BLU

R141

22P_0402_50V8J~D

1

C161

2

@

22P_0402_50V8J~D

1

C165

2

@

12

12

12

R143

R142

150_0402_1%~D

150_0402_1%~D

150_0402_1%~D

1

C162

2

@

Evaluate Package

DAT_DDC212,36
CLK_DDC212,36

+5V_RUN

B B

CRT_HSYNC12

CRT_VSYNC12

D6

SDM10U45-7_SOD523-2~D

2 1

R60

1 2

30_0402_1%~D

R59

1 2

30_0402_1%~D

+5V_RUN_SYNC

1

5

U15

P

4

OE#

A2Y

G

3

SN74AHCT1G125GW_SC70-5~D

1

5

P

4

OE#

A2Y

G

U14

3

SN74AHCT1G125GW_SC70-5~D

R144

1K_0402_5%~D

1 2

1 2

R146
10_0402_5%~D

1 2

R138

10_0402_5%~D

BLM18BB750SN1D_0603~D

1 2

BLM18BB750SN1D_0603~D

1 2

BLM18BB750SN1D_0603~D

1 2

22P_0402_50V8J~D

L1

BLM18AG121SN1D_0603~D

1 2

HSYNC_R 36

VSYNC_R 36

L2

BLM18AG121SN1D_0603~D

1 2

L10

L9

+5V_RUN_SYNC

12

R3

@

1K_0402_5%~D

1

C5

2

10P_0402_50V8J~D

1

C149
10P_0402_50V8J~D

2

@

12

@

R5

1K_0402_5%~D

1

C4

2

10P_0402_50V8J~D

R137

1 2

1

C719

2

@

10P_0402_50V8J~D

R2

2.2K_0402_5%~D

1 2

2.2K_0402_5%~D

1

C712

2

@

10P_0402_50V8J~D

0.1U_0402_16V4Z~D

2

1

C148
10P_0402_50V8J~D

2

@

T5 PAD~D

D10
DA204U_SOT323~D

1

@

3

1

C160

2

1

2

D9
DA204U_SOT323~D

1

@

2

3

C147
10P_0402_50V8J~D

@

A A

DA204U

K1

A2

DELL CONFIDENTIAL/PROPRIETARY

A1 K2

5

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

4

3

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

CRT

LA-3301P

20 58Monday, February 26, 2007

1

1.0

of

5

+3.3V_RUN

D D

C C

B B

1 2

R442 8.2K_0402_5%~D

1 2

R443 8.2K_0402_5%~D

1 2

R444 8.2K_0402_5%~D

1 2

R445 8.2K_0402_5%~D

1 2

R446 8.2K_0402_5%~D

1 2

R447 8.2K_0402_5%~D

1 2

R448 8.2K_0402_5%~D

1 2

R449 8.2K_0402_5%~D

+3.3V_RUN

1 2

R450 8.2K_0402_5%~D

1 2

R451 8.2K_0402_5%~D

1 2

R452 8.2K_0402_5%~D

1 2

R453 8.2K_0402_5%~D

1 2

R454 8.2K_0402_5%~D

1 2

R458 8.2K_0402_5%~D

1 2

R459 8.2K_0402_5%~D

1 2

R461 20K_0402_5%~D

1 2

R460 20K_0402_5%~D

1 2

R601 20K_0402_5%~D

1 2

R631 20K_0402_5%~D

BIOS should not enable the internal
GPIO pull up resistor

PCI_DEVSEL#
PCI_STOP#
PCI_TRDY#
PCI_FRAME#

PCI_PLOCK#
PCI_IRDY#
PCI_SERR#
PCI_PERR#

PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#

ICH_GPIO2_PIRQE#

PCI_REQ0#
PCI_REQ1#

SB_LOM_PCIE_RST#
SB_WWAN_PCIE_RST#
SB_WLAN_PCIE_RST#
SB_NB_PCIE_RST#

PCI_AD[0..31]30,35

PCI_GNT3#

4

PCI_PIRQA#35

PCI_PIRQD#30

12

R477
1K_0402_5%~D

@

PCI_AD0
PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD6
PCI_AD7
PCI_AD8
PCI_AD9
PCI_AD10
PCI_AD11
PCI_AD12
PCI_AD13
PCI_AD14
PCI_AD15
PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20
PCI_AD21
PCI_AD22
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30
PCI_AD31

PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#

U32B

D20

AD0

E19

AD1

D19

AD2

A20

AD3

D17

AD4

A21

AD5

A19

AD6

C19

AD7

A18

AD8

B16

AD9

A12

AD10

E16

AD11

A14

AD12

G16

AD13

A15

AD14

B6

AD15

C11

AD16

A9

AD17

D11

AD18

B12

AD19

C12

AD20

D10

AD21

C7

AD22

F13

AD23

E11

AD24

E13

AD25

E12

AD26

D8

AD27

A6

AD28

E8

AD29

D6

AD30

A3

AD31

Interrupt I/F

F9

PIRQA#

B5

PIRQB#

C5

PIRQC#

A10

PIRQD#

PCI

ICH8M_BGA676~D

PCI_GNT0#

REQ0#

GNT0#
REQ1#/GPIO50
GNT1#/GPIO51
REQ2#/GPIO52
GNT2#/GPIO53
REQ3#/GPIO54
GNT3#/GPIO55

C/BE0#

C/BE1#

C/BE2#

C/BE3#

IRDY#

PAR

PCIRST#

DEVSEL#

PERR#

PLOCK#

SERR#

STOP#

TRDY#

FRAME#

PLTRST#

PCICLK

PME#

PIRQE#/GPIO2

PIRQF#/GPIO3
PIRQG#/GPIO4
PIRQH#/GPIO5

12

R462

1K_0402_5%~D

3

A4
D7
E18
C18
B19
F18
A11
C10

C17
E15
F16
E17

C8
D9
G6
D16
A7
B7
F10
C16
C9
A17

AG24
B10
G7

F8
G11
F12
B3

PCI_REQ0#
PCI_GNT0#
PCI_REQ1#
PCI_GNT1#

SB_WWAN_PCIE_RST#

SB_LOM_PCIE_RST#
PCI_GNT3#

PCI_C_BE0#
PCI_C_BE1#
PCI_C_BE2#
PCI_C_BE3#

PCI_IRDY#
PCI_PAR
PCI_PCIRST#
PCI_DEVSEL#
PCI_PERR#
PCI_PLOCK#
PCI_SERR#
PCI_STOP#
PCI_TRDY#
PCI_FRAME#

PCI_PLTRST#
CLK_PCI_ICH
ICH_PME#

ICH_GPIO2_PIRQE#
SB_WLAN_PCIE_RST#
SB_NB_PCIE_RST#

ICH_SPI_CS1#23

PCI_REQ0# 36

PCI_GNT0# 35,36

PCI_REQ1# 30

PCI_GNT1# 30
SB_WWAN_PCIE_RST# 34

T1 PAD~D

SB_LOM_PCIE_RST# 28

T2 PAD~D

PCI_C_BE0# 30,35
PCI_C_BE1# 30,35
PCI_C_BE2# 30,35
PCI_C_BE3# 30,35

PCI_PLOCK# 35

PCI_SERR# 30,35

PCI_FRAME# 30,35,36

CLK_PCI_ICH 6

ICH_PME# 38

SB_WLAN_PCIE_RST# 34
SB_NB_PCIE_RST# 10

PCIE_MCARD2_DET# 34

ICH_SPI_CS1#

PCI_ I RDY# 30,35,36
PCI_PAR 30,35

PCI_DEVSEL# 30,35
PCI_PERR# 30,35

PCI_STOP# 30,35
PCI_TRDY# 30,35

12

R463

1K_0402_5%~D@

2

PCI_PCIRST#

PCI_PLTRST#

+3.3V_SUS

14

U33A

1

P

IN1

OUT

2

IN2

G

74VHC08MTCX_NL_TSSOP14~D

7

+3.3V_SUS

14

U33B

4

P

IN1

OUT

5

IN2

G

74VHC08MTCX_NL_TSSOP14~D

7

+3.3V_SUS

14

U33C

10

P

IN1

OUT

9

IN2

G

74VHC08MTCX_NL_TSSOP14~D

7

+3.3V_SUS

14

U33D

13

P

IN1

OUT

12

IN2

G

74VHC08MTCX_NL_TSSOP14~D

7

C651

0.1U_0402_16V4Z~D

PCI_RST#

3

PLTRST1#

6

PLTRST2#

8

PLTRST3#

11

1

PCI_RST# 30,31,35

PLTRST1# 10,51

PLTRST2# 38,39

PLTRST3# 28,34

Place closely pin U19.A9

CLK_PCI_ICH

A16 away override strap.

PCI_GNT3#

A A

Low = A16 swap override enabled.
High = Default.

Boot BIOS Strap

PCI_GNT0# SPI_CS1#

*

0

1

1

R464

10_0402_5%~D@

Boot BIOS Location

1

0

1

SPI

PCI

LPC

1 2

CLK_ICH_TERM

1

C652

8.2P_0402_50V8J~D@

2

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

ICH8(1/4)

LA-3301P

21 58Monday, February 26, 2007

1

1.0

of

5

D D

+3.3V_RUN

27P_0402_50V8J~D

IDE_IRQ

Close to U19

1 2

R493 33_0402_5%~D

1 2

R494 33_0402_5%~D

1 2

R495 33_0402_5%~D

R496

1 2

33_0402_5%~D

1

C660

2

ICH_AZ_SDOUT

ICH_AZ_SYNC

ICH_AZ_RST#

ICH_AZ_BITCLK

1 2

R490 8.2K_0402_5%~D

C C

ICH_AZ_CODEC_SDOUT26

ICH_AZ_CODEC_SYNC26

ICH_AZ_CODEC_RST#26

ICH_AZ_CODEC_BITCLK26

B B

32.768K_12.5P_1TJS125DJ4A420P~D

+RTC_CELL

ICH_AZ_MDC_BITCLK33
ICH_AZ_MDC_SYNC33

ICH_AZ_MDC_RST#33

ICH_AZ_CODEC_SDIN026

ICH_AZ_MDC_SDIN133

ICH_AZ_MDC_SDOUT33

PSATA_IRX_DTX_N0_C25
PSATA_IRX_DTX_P0_C25

PSATA_ITX_DRX_N025
PSATA_ITX_DRX_P025

XOR Chain Entrance Strap

DescriptionICH RSVD HDA SDOUT

A A

00

0

1

1

0

11

5

RSVD

Enter XOR Chain

Normal Operation (Default)

Set PCIE port config bit 1

4

Package

9.6X4.06 mm

C653

15P_0402_50V8J~D

12

C654

15P_0402_50V8J~D

12
1 2

R470 20K_0402_5%~D

1 2

R471 1M_0402_5%~D

1

1

CMOS_CLR @SHORT PADS~D

1U_0603_10V4Z~D

SATA_ACT#_R43

C658 3900P_0402_50V7K~D
C659 3900P_0402_50V7K~D

CLK_PCIE_SATA#6
CLK_PCIE_SATA6

4

C655

1 2

+3.3V_RUN

Y4

C656

27P_0402_50V8J~D

12
12

12

12

1 4

2

2

12

R385
1K_0402_5%~D

@

ICH_AZ_SDOUT

R386
1K_0402_5%~D

@

ICH_RTCX1

12

R467

2 3

1 2

0_0402_5%~D

R481 33_0402_5%~D

1 2
1 2

R483 33_0402_5%~D

1 2

R484 33_0402_5%~D

1 2

R487 33_0402_5%~D

1 2

R491 24.9_0402_1%~D

Within 500 mils

10M_0402_5%~D

R469

+1.5V_RUN_PCIE_ICH

ICH_AZ_BITCLK
ICH_AZ_SYNC

ICH_AZ_RST#
ICH_AZ_CODEC_SDIN0

ICH_AZ_MDC_SDIN1

ICH_AZ_SDOUT

SATA_ACT#_R
PSATA_IRX_DTX_N0_C

PSATA_IRX_DTX_P0_C
SATA_TX0-_N0
SATA_TX0+_P0

CLK_PCIE_SATA#
CLK_PCIE_SATA

ICH_RSVD 23

ICH_RTCX2
ICH_RTCRST#
INTRUDER#
ICH_INTVRMEN

LAN100_SLP

24.9_0402_1%~D

1 2

3

+RTC_CELL +RTC_CELL

12

R472
332K_0402_1%~D

ICH_INTVRMEN LAN100_SLP

12

@

R478

0_0402_1%

ICH8M Internal VR Enable Strap
(Internal VR f or Vc cS us 1.05, VccSus1.5, VccCL1.5)

ICH_INTVRMEN

U32A

AG25

RTCX1

AF24

RTCX2

AF23

RTCRST#

AD22

INTRUDER#

AF25

INTVRMEN

AD21

LAN100_SLP

B24

GLAN_CLK

D22

LAN_RSTSYNC

C21

LAN_RXD0

B21

LAN_RXD1

C22

LAN_RXD2

D21

LAN_TXD_0

E20

LAN_TXD_1

C20

R480

LAN_TXD_2

AH21

GLAN_DOCK#/GPIO13

D25

GLAN_COMPI

C25

GLAN_COMPO

AJ16

HDA_BIT_CLK

AJ15

HDA_SYNC

AE14

HDA_RST#

AJ17

HDA_SDIN0

AH17

HDA_SDIN1

AH15

HDA_SDIN2

AD13

HDA_SDIN3

AE13

HDA_SDOUT

AE10

HDA_DOCK_EN#/GPIO33

AG14

HDA_DOCK_RST#/GPIO34

AF10

SATALED#

AF6

SATA0RXN

AF5

SATA0RXP

AH5

SATA0TXN

AH6

SATA0TXP

AG3

SATA1RXN

AG4

SATA1RXP

AJ4

SATA1TXN

AJ3

SATA1TXP

AF2

SATA2RXN

AF1

SATA2RXP

AE4

SATA2TXN

AE3

SATA2TXP

AB7

SATA_CLKN

AC6

SATA_CLKP

AG1

SATARBIAS#

AG2

SATARBIAS

Low = Internal VR Disabled
High = Internal VR Enabled(Default)

E5

FWH0/LAD0

F5

FWH1/LAD1

G8

FWH2/LAD2

F6

FWH3/LAD3

RTC

LPCCPU

CPUPWRGD/GPIO49

LAN / GLAN

IHDA

IDE

SATA

FWH4/LFRAME#

LDRQ1#/GPIO23

ICH8M_BGA676~D

LDRQ0#

A20GATE

A20M#

DPRSTP#

DPSLP#

FERR#

IGNNE#

INIT#
INTR

RCIN#

SMI#

STPCLK#

THRMTRIP#

DD10
DD11
DD12
DD13
DD14
DD15

DCS1#
DCS3#

DIOR#

DIOW#

DDACK#

IDEIRQ

IORDY

DDREQ

NMI

TP8
DD0

DD1
DD2
DD3
DD4
DD5
DD6
DD7
DD8
DD9

DA0
DA1
DA2

C4
G9

E6
AF13

AG26
AF26

AE26
AD24
AG29
AF27
AE24

AC20
AH14

AD23
AG28

AA24
AE27
AA23
V1

U2
V3
T1
V4
T5
AB2
T6
T3
R2
T4
V6
V5
U1
V2
U6

AA4
AA1
AB3

Y6
Y5

W4
W3
Y2
Y3
Y1
W5

2

LPC_LAD0
LPC_LAD1
LPC_LAD2
LPC_LAD3

LPC_LFRAME#
LPC_LDRQ0#

LPC_LDRQ1#
SIO_A20GATE

H_A20M#
H_DPRSTP#

H_DPSLP#
H_FERR#
H_PWRGOOD
H_IGNNE#
H_INIT#

H_INTR
SIO_RCIN#

H_NMI
H_SMI#

H_STPCLK#
THRMTRIP_ICH#
ICH_TP8
IDE_DD0

IDE_DD1
IDE_DD2
IDE_DD3
IDE_DD4
IDE_DD5
IDE_DD6
IDE_DD7
IDE_DD8
IDE_DD9
IDE_DD10
IDE_DD11
IDE_DD12
IDE_DD13
IDE_DD14
IDE_DD15

IDE_DA0
IDE_DA1
IDE_DA2

IDE_DCS1#
IDE_DCS3#

IDE_DIOR#
IDE_DIOW#
IDE_DDACK#
IDE_IRQ
IDE_DIORDY
IDE_DDREQ

1

12

R475
332K_0402_1%~D

R476

@

0_0402_5%~D

1 2

ICH8M LAN100 SLP Strap
(Internal VR f or Vc cL AN1.05 and VccCL1.05)

ICH_LAN100_SLP Low = Internal VR Disabled

LPC_LAD0 28,38,39
LPC_LAD1 28,38,39
LPC_LAD2 28,38,39
LPC_LAD3 28,38,39

LPC_LFRAME# 28,38,39
LPC_LDRQ0# 38

LPC_LDRQ1# 38

SIO_A20GATE 39
H_A20M# 7

H_FERR# 7
H_PWRGOOD 8
H_IGNNE# 7
H_INIT# 7

H_INTR 7
SIO_RCIN# 39

H_NMI 7
H_SMI# 7

H_STPCLK# 7

T12PAD~D

IDE_DD[0..15] 25

IDE_DA0 25
IDE_DA1 25
IDE_DA2 25

IDE_DCS1# 25
IDE_DCS3# 25

IDE_DIOR# 25
IDE_DIOW# 25
IDE_DDACK# 25

IDE_IRQ 25
IDE_DIORDY 25
IDE_DDREQ 25

High = Interna l V R Enabled(Default)

+1.05V_VCCP

12

12

R474

R473

@

@

56_0402_1%~D

+1.05V_VCCP

C470

12

1

2

0.1U_0402_16V4Z~D

56_0402_1%~D

R482
56_0402_5%~D

SIO_A20GATE

SIO_RCIN#

H_DPRSTP# 8,10,48
H_DPSLP# 8

R465

10K_0402_5%~D

R466

10K_0402_5%~D

H_FERR#

R468

56_0402_5%~D

+3.3V_RUN

12

12

+1.05V_VCCP

12

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

ICH8(2/4)

LA-3301P

22 58Monday, February 26, 2007

1

1.0

of

5

+3.3V_RUN

R411 2.2K_0402_5%~D@

1 2

R524 10K_0402_5%~D@
R497 10K_0402_5%~D
R504 10K_0402_5%~D

1 2

R517 10K_0402_5%~D

1 2

R523 10K_0402_5%~D

D D

1 2

R528 10K_0402_5%~D

1 2

R115 1K_0402_5%~D@

1 2

12
12

IMVP_PWRGD
MCH_ICH_SYNC#
RSV_THRM#
IRQ_SERIRQ
RSVD_GPIO38
RSVD_GPIO39
RSVD_GPIO48
SPKR

No Reboot Strap

Low = Default

SPKR

+3.3V_SUS

1 2

R514 10K_0402_5%~D@

1 2

R503 10K_0402_5%~D

@

R502 10K_0402_5%~D

@

1 2

R506 10K_0402_5%~D

1 2

R516 10K_0402_5%~D

1 2

R521 1K_0402_5%~D

1 2

R498 2.2K_0402_5%~D

1 2

R499 2.2K_0402_5%~D

1 2

R690 8.2K_0402_5%~D

1 2

R807 10K_0402_5%~D

ICH_CL_RST1#
ICH_SMLINK0
ICH_SMLINK1

12

ICH_RI#
SIO_EXT_SCI#
ICH_PCIE_W AKE#
ICH_SMBCLK
ICH_SMBDATA
EC_ME_ALERT
LOM_ICH_SMBALERT#

High = No Reboot

Filters are to supress

+3.3V_SUS

SIO_EXT_SMI#

1 2

R509 10K_0402_5%~D

+3.3V_RUN

12

R505

8.2K_0402_5%~D

C C

CLKRUN#

Option to " Disable "

12

clkrun. Pulling it
down

R508

will keep the clks

@

running.

10_0402_5%~D

SIO_EXT_WAKE#38

PCIE_MCARD1_DET#34

USB_MCARD1_DET#34

USB_MCARD2_DET#34

MiniWWAN (Mini Card 1)--->

+3.3V_SUS

MiniWLAN (Mini Card 2)--->

1 2

R702 10K_0402_5%~D

1 2

R703 10K_0402_5%~D

1 2

B B

R704 10K_0402_5%~D

1 2

R705 10K_0402_5%~D

1 2

R706 10K_0402_5%~D

1 2

R707 10K_0402_5%~D

1 2

R708 10K_0402_5%~D

1 2

R709 10K_0402_5%~D

A A

+3.3V_RUN

USB_OC2_3#
USB_OC4#
USB_OC0_1#
USB_OC5#

USB_OC6#
USB_OC8#
USB_OC9#
USB_OC7#

ICH_SMBDATA

ICH_SMBCLK

GIGA LAN --->

+3.3V_RUN

D

S

1 3

Q21
2N7002W-7-F_SOT323-3~D

G

2
2

G

1 3

D

S

Q27
2N7002W-7-F_SOT323-3~D

5

14MHz noise sourced
from the ICH

USB_IDE#25

C874

@

PCIE_IRX_WANTX_N134
PCIE_IRX_WANTX_P134
PCIE_ITX_WANRX_N1_C34

PCIE_ITX_WANRX_P1_C34
PCIE_IRX_WLANTX_N234
PCIE_IRX_WLANTX_P234
PCIE_ITX_WLANRX_N2_C34

PCIE_ITX_WLANRX_P2_C34

12

12

R99

R278

2.2K_0402_5%~D

2.2K_0402_5%~D

1

47P_0402_50V8J~D

2

C875 47P_0402_50V8J~D

@

PCIE_RX6-/GLAN_RX-28

PCIE_RX6+/GLAN_RX+28
PCIE_TX6-/GLAN_TX-28
PCIE_TX6+/GLAN_TX+28

ICH_EC_SPI_CLK39

ICH_EC_SPI_DO39
ICH_EC_SPI_DIN39

MEM_SDATA

MEM_SCLK

1

1

2

2

C876 47P_0402_50V8J~D

@

@

ICH_SPI_CS0#39
ICH_SPI_CS1#21

Non-iAMT

MEM_SDATA 16,17

MEM_SCLK 16,17

R817 0_0603_5%~D
R819 0_0603_5%~D

R820 4.7K_0603_5%~D
R818 0_0603_5%~D

1

1

2

2

C878 47P_0402_50V8J~D

C877 47P_0402_50V8J~D

@

ICH_EC_SPI_CLK
ICH_SPI_CS0#
ICH_SPI_CS1#

ICH_EC_SPI_DO
ICH_EC_SPI_DIN

0_0603_5%~D

1 2
1 2

1 2
1 2

1 2

4

ICH_SMBCLK28,34

ICH_SMBDATA28,34

ITP_DBRESET#7,38

PM_BMBUSY#10

LOM_SMB_ALERT#28,39

R816

C664 0.1U_0402_10V7K~D

1 2

C666 0.1U_0402_10V7K~D

1 2

C667 0.1U_0402_10V7K~D

1 2

C668 0.1U_0402_10V7K~D

1 2

C669 0.1U_0402_10V7K~D

1 2

C670 0.1U_0402_10V7K~D

1 2

1 2

R793 0_0402_5%~D@

H_STP_PCI#6
H_STP_CPU#6

CLKRUN#30,38,39

ICH_PCIE_WAKE#38

IRQ_SERIRQ28,30,38,39

IMVP_PWRGD39,42,48

SIO_EXT_SMI#39

SIO_EXT_SCI#39

IDE_RST_MOD25

SATA_CLKREQ#6

MCH_ICH_SYNC#10

ICH_RSVD22

R530 15_0402_5%~D

1 2

R531 15_0402_5%~D

1 2

R532 15_0402_5%~D

1 2

R763 15_0402_5%~D

1 2

USB_OC0_1#32
USB_OC2_3#32

4

LOM_ICH_SMBALERT#

T15PAD~D

T24PAD~D

T3PAD~D
T14PAD~D

SPKR26

PCIE_IRX_WANTX_N1
PCIE_IRX_WANTX_P1
PCIE_ITX_WANRX_N1
PCIE_ITX_WANRX_P1

PCIE_IRX_WLANTX_N2
PCIE_IRX_WLANTX_P2
PCIE_ITX_WLANRX_N2
PCIE_ITX_WLANRX_P2

PCIE_RX6-/GLAN_RX­PCIE_RX6+/GLAN_RX+
GLAN_TXN_C
GLAN_TXP_C

ICH_SMBCLK
ICH_SMBDATA
ICH_CL_RST1#
ICH_SMLINK0
ICH_SMLINK1

ICH_RI#

ITP_DBRESET#
PM_BMBUSY#

H_STP_PCI#
H_STP_CPU#

CLKRUN#
ICH_PCIE_W AKE#

IRQ_SERIRQ
RSV_THRM#

IMVP_PWRGD
ICH_TP7

SIO_EXT_SMI#

SIO_EXT_SCI#

RSVD_GPIO27
IDE_RST_MOD

SATA_CLKREQ#

RSVD_GPIO38
RSVD_GPIO39
RSVD_GPIO48

SPKR
MCH_ICH_SYNC#
ICH_RSVD

USB_OC0_1#
USB_OC2_3#
USB_OC4#

USB_OC5#
USB_OC6#
USB_OC7#
USB_OC8#
USB_OC9#

U32C

AJ26

SMBCLK

AD19

SMBDATA

AG21

LINKALERT#

AC17

SMLINK0

AE19

SMLINK1

AF17

RI#

F4

SUS_STAT#/LPCPD#

AD15

SYS_RESET#

AG12

BMBUSY#/GPIO0

AG22

SMBALERT#/GPIO11

AE20

STP_PCI#/GPIO15

AG18

STP_CPU#/GPIO25

AH11

CLKRUN#/GPIO32

AE17

WAKE#

AF12

SERIRQ

AC13

THRM#

AJ20

VRMPWRGD

AJ22

TP7

AJ8

TACH1/GPIO1

AJ9

TACH2/GPIO6

AH9

TACH3/GPIO7

AE16

GPIO8

AC19

GPIO12

AG8

TACH0/GPIO17

AH12

GPIO18

AE11

GPIO20

AG10

SCLOCK/GPIO22

AH25

QRT_STATE0/GPIO27

AD16

QRT_STATE1/GPIO28

AG13

SATACLKREQ#/GPIO35

AF9

SLOAD/GPIO38

AJ11

SDATAOUT0/GPIO39

AD10

SDATAOUT1/GPIO48

AD9

SPKR

AJ13

MCH_SYNC#

AJ21

TP3

U32D

P27

PERN1

P26

PERP1

N29

PETN1

N28

PETP1

M27

PERN2

M26

PERP2

L29

PETN2

L28

PETP2

K27

PERN3

K26

PERP3

J29

PETN3

J28

PETP3

H27

PERN4

H26

PERP4

G29

PETN4

G28

PETP4

F27

PERN5

F26

PERP5

E29

PETN5

E28

PETP5

D27

PERN6/GLAN_RXN

D26

PERP6/GLAN_RXP

C29

PETN6/GLAN_TXN

C28

PETP6/GLAN_TXP

C23

SPI_CLK

B23

SPI_CS0#

E22

SPI_CS1#

D23

SPI_MOSI

F21

SPI_MISO

AJ19

OC0#

AG16

OC1#/GPIO40

AG15

OC2#/GPIO41

AE15

OC3#/GPIO42

AF15

OC4#/GPIO43

AG17

OC5#/GPIO29

AD12

OC6#/GPIO30

AJ18

OC7#/GPIO31

AD14

OC8#

AH18

OC9#

3

+3.3V_RUN

8.2K_0402_5%~D

12

R500

SATA0GP

CLK14

CLK48
SUSCLK
SLP_S3#

SLP_S4#
SLP_S5#

PWROK

BATLOW#
PWRBTN#

LAN_RST#

RSMRST#

CLPWROK

SLP_M#

CL_CLK0
CL_CLK1

CL_DATA0
CL_DATA1

CL_VREF0
CL_VREF1

CL_RST#

V27
V26
U29
U28

Y27
Y26
W29
W28

AB26
AB25
AA29
AA28

AD27
AD26
AC29
AC28

T26
T25

Y23
Y24

G3
G2
H5
H4
H2
H1
J3
J2
K5
K4
K2
K1
L3
L2
M5
M4
M2
M1
N3
N2

F2
F3

AJ12
AJ10
AF11
AG11

AG9
G5

D3
AG23

AF21
AD18

AH27
AE23
AJ14
AE21
C2
AH20
AG27
E1
E3
AJ25
F23

AE18
F22

AF19
D24

AH23
AJ23
AJ27

AJ24
AF22
AG19

DMI_MTX_IRX_N0
DMI_MTX_IRX_P0
DMI_MRX_ITX_N0
DMI_MRX_ITX_P0

DMI_MTX_IRX_N1
DMI_MTX_IRX_P1
DMI_MRX_ITX_N1
DMI_MRX_ITX_P1

DMI_MTX_IRX_N2
DMI_MTX_IRX_P2
DMI_MRX_ITX_N2
DMI_MRX_ITX_P2

DMI_MTX_IRX_N3
DMI_MTX_IRX_P3
DMI_MRX_ITX_N3
DMI_MRX_ITX_P3

CLK_PCIE_ICH#
CLK_PCIE_ICH

DMI_IRCOMP
USBP0-

USBP0+
USBP1­USBP1+
USBP2­USBP2+
USBP3­USBP3+
USBP4­USBP4+
USBP5­USBP5+
USBP6­USBP6+
USBP7­USBP7+
USBP8­USBP8+
USBP9­USBP9+

USBRBIAS

CLK_ICH_14M
CLK_ICH_48M

ICH_SUSCLK
SIO_SLP_S3#
SIO_SLP_S5#

ICH_PWRGD
DPRSLPVR
ICH_BATLOW#

R518 8.2K_0402_5%~D

SIO_PWRBTN#
ICH_LAN_RST#
ICH_RSMRST#
CLK_PWRGD
ICH_CL_PWROK

CL_CLK0

CL_DATA0

CL_VREF0_ICH

ICH_CL_RST0#

EC_ME_ALERT

DMI_MTX_IRX_N0 10
DMI_MTX_IRX_P0 10
DMI_MRX_ITX_N0 10
DMI_MRX_ITX_P0 10

DMI_MTX_IRX_N1 10
DMI_MTX_IRX_P1 10
DMI_MRX_ITX_N1 10
DMI_MRX_ITX_P1 10

DMI_MTX_IRX_N2 10
DMI_MTX_IRX_P2 10
DMI_MRX_ITX_N2 10
DMI_MRX_ITX_P2 10

DMI_MTX_IRX_N3 10
DMI_MTX_IRX_P3 10
DMI_MRX_ITX_N3 10
DMI_MRX_ITX_P3 10

CLK_PCIE_ICH# 6
CLK_PCIE_ICH 6

USBP0- 32
USBP0+ 32
USBP1- 32

USBP1+ 32

USBP2- 32

USBP2+ 32

USBP3- 32

USBP3+ 32

USBP4- 31

USBP4+ 31

USBP5- 40

USBP5+ 40

USBP6- 30

USBP6+ 30

USBP7- 40

USBP7+ 40

USBP8- 36

USBP8+ 36

USBP9- 34

USBP9+ 34

1 2

R533 22.6_0402_1%~D

Within 500 mils

SATA0GP/GPIO21
SATA1GP/GPIO19
SATA2GP/GPIO36
SATA3GP/GPIO37

SMB

SATA

GPIO

clocks

S4_STATE#/GPIO26

DPRSLPVR/GPIO16

SYS / GPIOGPIOMISC

Power MGT

CK_PWRGD

MEM_LED/GPIO24
ME_EC_ALERT/GPIO10
EC_ME_ALERT/GPIO14

WOL_EN/GPIO9

Controller Link

ICH8M_BGA676~D

DMI0RXN
DMI0RXP
DMI0TXN

DMI0TXP

DMI1RXN
DMI1RXP
DMI1TXN

DMI1TXP

DMI2RXN
DMI2RXP
DMI2TXN

DMI2TXP

DMI3RXN
DMI3RXP
DMI3TXN

DMI3TXP

DMI_CLKN

PCI - Express

DMI_CLKP

Direct Media Interface

DMI_ZCOMP

DMI_IRCOMP

USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4N

SPI

USBP4P
USBP5N
USBP5P

ICH8M_BGA676~D

3

USBP6N
USBP6P
USBP7N
USBP7P
USBP8N
USBP8P
USBP9N
USBP9P

USBRBIAS#

USBRBIAS

USB

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

2

CLK_ICH_14M 6
CLK_ICH_48M 6

T13 PAD~D

SIO_SLP_S3# 39

SIO_SLP_S5# 39

ICH_PWRGD 10,42

DPRSLPVR 10,48

12

SIO_PWRBTN# 39

ICH_RSMRST# 39

CLK_PWRGD 6
ICH_CL_PWROK 10,39

CL_CLK0 10

CL_DATA0 10

T86 PAD~D

ICH_CL_RST0# 10

Within 500 mils

R529 24.9_0402_1%~D

1 2

----->Side Top

----->Side Bottom

----->Rear Left

----->Rear Right

----->Smart Card

----->Biometric

----->Card Bus

----->Blue Tooth

----->Dock

----->WWAN

2

+3.3V_SUS

1

ICH_CL_PWROK

ICH_LAN_RST#

DPRSLPVR

ICH_PWRGD

ICH_RSMRST#

1 2

R42 1M_0402_1%~D

1 2

R834 10K_0402_5%~D

1 2

R501 100K_0402_5%~D

1 2

R512 10K_0402_5%~D

1 2

R515 10K_0402_5%~D

Place closely pin U19.AC1

CLK_ICH_14M

12

R510

10_0402_5%~D@

Non-iAMT

1

C661

4.7P_0402_50V8C~D@

2

Place closely pin U19.B2

CLK_ICH_48M

12

R520

10_0402_5%~D@

1

C663

4.7P_0402_50V8C~D@

2

Non-iAMT

3.24K_0402_1%~D

CL_VREF0_ICH

+1.5V_RUN_PCIE_ICH

+3.3V_RUN

R519

1

C662

2

0.1U_0402_16V4Z~D

DELL CONFIDENTIAL/PROPRIETARY

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

ICH8(3/4)

LA-3301P

1

12

12

R522

453_0402_1%~D

23 58Friday, March 02, 2007

1.0

of

5

4

3

2

1

+RTC_CELL

1U_0603_10V4Z~D

+3.3V_RUN+5V_RUN

21

12

12

+1.5V_RUN

D20
RB751V_SOD323~D

ICH_V5REF_RUN

1

C675

0.1U_0402_16V4Z~D

2

+3.3V_SUS+5V_SUS

21

D21
RB751V_SOD323~D

ICH_V5REF_SUS

1

C683

0.1U_0402_16V4Z~D

2

R537

1 2

0_0603_5%~D

Non-iAMT

+VCCSATAPLLR

0.1U_0402_16V4Z~D

+1.5V_RUN

1 2

BLM21PG600SN1D_0805~D

10UH_LB2012T100MR_20%_0805~D

1 2

1

2

1

2

1

C703

2

R534

100_0402_5%~D

D D

R536

10_0402_5%~D

C C

B B

Non-iAMT

+3.3V_RUN

C200

1

2

+1.5V_RUN_PCIE_ICH

L43

220U_D2_4VY_R15M~D

L45

C699

0.1U_0402_16V4Z~D

C700

0.1U_0402_16V4Z~D

Non-iAMT

+1.5V_RUN

Place Cap as close

A A

to A24 as possible

5

1

C705

2

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

C671

1

2

+1.5V_RUN_PCIE_ICH

22U_0805_6.3V6M~D

1

+

2

1U_0603_10V4Z~D

C677

1

C676

2

+1.5V_RUN_SATAPLL

1U_0603_10V4Z~D

10U_0805_4VAM~D

C689

1

2

C696

+1.5V_RUN_PCIE_ICH

1

C709

4.7U_0603_6.3V6M~D

2

C672

1

2

22U_0805_6.3V6M~D

C678

1

2

C690

1

2

1

2

C697

1U_0603_10V4Z~D

+1.5V_RUN

TP_VCCLAN1.05_INT_ICH1

T21PAD~D

TP_VCCLAN1.05_INT_ICH2

T22PAD~D

+3.3V_RUN

4

ICH_V5REF_RUN

ICH_V5REF_SUS

2.2U_0603_6.3V6K~D
C679

1

2

1

2

AD25

AA25
AA26
AA27
AB27
AB28
AB29

W25

AC10

W23

D28
D29

G24
H23
H24

M24
M25
N23
N24
N25

R24
R25
R26
R27

U24
U25

AE7
AF7
AG7
AH7

AC1
AC2
AC3
AC4
AC5

AC9
AA5

AA6
G12

G17

AC7
AD7

G18

G20

A16

T7

G4

E25
E26
E27
F24
F25

J23
J24
K24
K25
L23
L24
L25

P24
P25

T23
T24
T27
T28
T29

V23
V24
V25

Y25
AJ6

AJ7

H7

D1

F1
L6

L7
M6
M7

F17

F19

A24
A26

A27
B26
B27
B28

B25

U32F

VCCRTC
V5REF[1]

V5REF[2]
V5REF_SUS
VCC1_5_B[01]

VCC1_5_B[02]
VCC1_5_B[03]
VCC1_5_B[04]
VCC1_5_B[05]
VCC1_5_B[06]
VCC1_5_B[07]
VCC1_5_B[08]
VCC1_5_B[09]
VCC1_5_B[10]
VCC1_5_B[11]
VCC1_5_B[12]
VCC1_5_B[13]
VCC1_5_B[14]
VCC1_5_B[15]
VCC1_5_B[16]
VCC1_5_B[17]
VCC1_5_B[18]
VCC1_5_B[19]
VCC1_5_B[20]
VCC1_5_B[21]
VCC1_5_B[22]
VCC1_5_B[23]
VCC1_5_B[24]
VCC1_5_B[25]
VCC1_5_B[26]
VCC1_5_B[27]
VCC1_5_B[28]
VCC1_5_B[29]
VCC1_5_B[30]
VCC1_5_B[31]
VCC1_5_B[32]
VCC1_5_B[33]
VCC1_5_B[34]
VCC1_5_B[35]
VCC1_5_B[36]
VCC1_5_B[37]
VCC1_5_B[38]
VCC1_5_B[39]
VCC1_5_B[40]
VCC1_5_B[41]
VCC1_5_B[42]
VCC1_5_B[43]
VCC1_5_B[44]
VCC1_5_B[45]
VCC1_5_B[46]

VCCSATAPLL
VCC1_5_A[01]

VCC1_5_A[02]
VCC1_5_A[03]
VCC1_5_A[04]
VCC1_5_A[05]

VCC1_5_A[06]
VCC1_5_A[07]
VCC1_5_A[08]
VCC1_5_A[09]
VCC1_5_A[10]

VCC1_5_A[11]
VCC1_5_A[12]

VCC1_5_A[13]
VCC1_5_A[14]

VCC1_5_A[15]
VCC1_5_A[16]
VCC1_5_A[17]

VCC1_5_A[18]
VCC1_5_A[19]

VCCUSBPLL
VCC1_5_A[20]

VCC1_5_A[21]
VCC1_5_A[22]
VCC1_5_A[23]
VCC1_5_A[24]

VCC1_5_A[25]
VCCLAN1_05[1]

VCCLAN1_05[2]
VCCLAN3_3[1]

VCCLAN3_3[2]
VCCGLANPLL
VCCGLAN1_5[1]

VCCGLAN1_5[2]
VCCGLAN1_5[3]
VCCGLAN1_5[4]
VCCGLAN1_5[5]

VCCGLAN3_3

VCCA3GP

ARX

USB COREATX

GLAN POWER

+1.05V_VCCP

VCCDMIPLL

VCC_DMI[1]
VCC_DMI[2]

VCC3_3[01]
VCC3_3[02]
VCC3_3[03]

VCC3_3[04]
VCC3_3[05]
VCC3_3[06]

VCC3_3[07]
VCC3_3[08]
VCC3_3[09]
VCC3_3[10]
VCC3_3[11]
VCC3_3[12]
VCC3_3[13]

VCC3_3[14]
VCC3_3[15]
VCC3_3[16]
VCC3_3[17]
VCC3_3[18]
VCC3_3[19]
VCC3_3[20]
VCC3_3[21]
VCC3_3[22]
VCC3_3[23]
VCC3_3[24]

VCCHDA

VCCCL1_05

VCCCL1_5

3

A13
B13
C13
C14
D14
E14
F14
G14
L11
L12
L14
L16
L17
L18
M11
M18
P11
P18
T11
T18
U11
U18
V11
V12
V14
V16
V17
V18

R29
AE28

AE29
AC23

AC24
AF29
AD2
AC8

AD8
AE8
AF8

AA3
U7
V7
W1
W6
W7
Y7

A8
B15
B18
B4
B9
C15
D13
D5
E10
E7
F11

AC12
AD11
J6

AF20
AC16
J7
C3
AC18

AC21
AC22
AG20
AH28

P6
P7
C1
N7
P1
P2
P3
P4
P5
R1
R3
R5
R6

G22
A22
F20

G21

VCC1_05[01]
VCC1_05[02]
VCC1_05[03]
VCC1_05[04]
VCC1_05[05]
VCC1_05[06]
VCC1_05[07]
VCC1_05[08]
VCC1_05[09]
VCC1_05[10]
VCC1_05[11]
VCC1_05[12]
VCC1_05[13]
VCC1_05[14]
VCC1_05[15]
VCC1_05[16]

CORE

VCC1_05[17]
VCC1_05[18]
VCC1_05[19]
VCC1_05[20]
VCC1_05[21]
VCC1_05[22]
VCC1_05[23]
VCC1_05[24]
VCC1_05[25]
VCC1_05[26]
VCC1_05[27]
VCC1_05[28]

V_CPU_IO[1]
V_CPU_IO[2]

VCCP_CORE

IDEPCI

VCCSUSHDA

VCCSUS1_05[1]
VCCSUS1_05[2]

VCCSUS1_5[1]

VCCSUS1_5[2]
VCCSUS3_3[01]
VCCSUS3_3[02]

VCCSUS3_3[03]
VCCSUS3_3[04]
VCCSUS3_3[05]
VCCSUS3_3[06]

VCCPSUS

VCCSUS3_3[07]
VCCSUS3_3[08]
VCCSUS3_3[09]
VCCSUS3_3[10]
VCCSUS3_3[11]
VCCSUS3_3[12]
VCCSUS3_3[13]
VCCSUS3_3[14]
VCCSUS3_3[15]

VCCPUSB

VCCSUS3_3[16]
VCCSUS3_3[17]
VCCSUS3_3[18]
VCCSUS3_3[19]

VCCCL3_3[1]
VCCCL3_3[2]

ICH8M_BGA676~D

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

C673

1

2

1

C680

2

0.01U_0402_16V7K~D

0.1U_0402_16V4Z~D

1

2

+3.3V_RUN

+3.3V_RUN

1

C691

0.1U_0402_16V4Z~D

2

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

1

C692

2

TP_VCCSUS1.05_INT_ICH1
TP_VCCSUS1.05_INT_ICH2

VCCSUS1_5_ICH_1
VCCSUS1_5_ICH_2

VCCCL1_05_ICH

+3.3V_RUN

Non-iAMT

T19
T20

T23

C674

1

2

BLM18PG181SN1_0603~D

1 2

1

C681

2

10U_0805_4VAM~D

22U_0805_6.3V6M~D

C202

1

2

+3.3V_RUN

0.1U_0402_16V4Z~D

1

1

C693

2

2

T17PAD~D
T18PAD~D

+3.3V_SUS

0.1U_0402_16V4Z~D

1

C704

2

+1.05V_VCCP

L44

+1.25V_RUN

C682

C694

0.022U_0402_16V7K~D

D4

2

3

MMBD4148-7-F_SOT23-3~D

R535
1_0603_1%~D

4.7U_0603_6.3V6M~D

0.1U_0402_16V4Z~D

C684

1

2

+3.3V_RUN

1

C688

2

0.1U_0402_16V4Z~D

+3.3V_RUN

1

C695

0.1U_0402_16V4Z~D

2

Non-iAMT

+3.3V_SUS

1

C698

0.1U_0402_16V4Z~D

2

+3.3V_SUS

0.022U_0402_16V7K~D

1

1

C701

C702

2

2

Non-iAMT

1

+1.5V_RUN

12

C685

1

2

2

1 2

10_0805_5%~D

+1.05V_VCCP

0.1U_0402_16V4Z~D

C686

1

2

1

2

R182

+3.3V_RUN

C687

0.1U_0402_16V4Z~D

+1.5V_RUN

AB24
AC11
AC14
AC25
AC26
AC27
AD17
AD20
AD28
AD29

AE12
AE22
AE25

AF14
AF16
AF18

AH10
AH13
AH16
AH19

AF28
AH22
AH24
AH26

AA2
AA7

AB1

AD3
AD4
AD6
AE1

AE2
AD1
AE5

AE6
AE9

AF3
AF4
AG5
AG6

AH2

AH3
AH4
AH8

C24
C26
C27

D12
D15
D18

G10
G13
G19
G23
G25
G26
G27
H25
H28
H29

U32E

A23

VSS[001]

A5

VSS[002]
VSS[003]
VSS[004]

A25

VSS[005]
VSS[006]
VSS[007]
VSS[008]
VSS[009]
VSS[010]
VSS[011]
VSS[012]
VSS[013]
VSS[014]
VSS[015]
VSS[016]
VSS[017]
VSS[018]
VSS[019]
VSS[020]
VSS[021]
VSS[022]
VSS[023]
VSS[024]
VSS[025]
VSS[026]
VSS[027]
VSS[028]
VSS[029]
VSS[030]
VSS[031]
VSS[032]
VSS[033]
VSS[034]
VSS[035]
VSS[036]
VSS[037]
VSS[038]
VSS[039]
VSS[040]
VSS[041]
VSS[042]
VSS[043]
VSS[044]
VSS[045]
VSS[046]
VSS[047]

AJ5

VSS[048]

B11

VSS[049]

B14

VSS[050]

B17

VSS[051]

B2

VSS[052]

B20

VSS[053]

B22

VSS[054]

B8

VSS[055]
VSS[056]
VSS[057]
VSS[058]

C6

VSS[059]
VSS[060]
VSS[061]
VSS[062]

D2

VSS[063]

D4

VSS[064]

E21

VSS[065]

E24

VSS[066]

E4

VSS[067]

E9

VSS[068]

F15

VSS[069]

E23

VSS[070]

F28

VSS[071]

F29

VSS[072]

F7

VSS[073]

G1

VSS[074]

E2

VSS[075]
VSS[076]
VSS[077]
VSS[078]
VSS[079]
VSS[080]
VSS[081]
VSS[082]
VSS[083]
VSS[084]
VSS[085]

H3

VSS[086]

H6

VSS[087]

J1

VSS[088]

J25

VSS[089]

J26

VSS[090]

J27

VSS[091]

J4

VSS[092]

J5

VSS[093]

K23

VSS[094]

K28

VSS[095]

K29

VSS[096]

K3

VSS[097]

K6

VSS[098]

VSS_NCTF[01]
VSS_NCTF[02]
VSS_NCTF[03]
VSS_NCTF[04]
VSS_NCTF[05]
VSS_NCTF[06]
VSS_NCTF[07]
VSS_NCTF[08]
VSS_NCTF[09]
VSS_NCTF[10]
VSS_NCTF[11]
VSS_NCTF[12]

ICH8M_BGA676~D

DELL CONFIDENTIAL/PROPRIETARY

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

ICH8(4/4)

LA-3301P

1

VSS[099]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
VSS[159]
VSS[160]
VSS[161]
VSS[162]
VSS[163]
VSS[164]
VSS[165]
VSS[166]
VSS[167]
VSS[168]
VSS[169]
VSS[170]
VSS[171]
VSS[172]
VSS[173]
VSS[174]
VSS[175]
VSS[176]
VSS[177]
VSS[178]
VSS[179]
VSS[180]
VSS[181]
VSS[182]
VSS[183]
VSS[184]

K7
L1
L13
L15
L26
L27
L4
L5
M12
M13
M14
M15
M16
M17
M23
M28
M29
M3
N1
N11
N12
N13
N14
N15
N16
N17
N18
N26
N27
N4
N5
N6
P12
P13
P14
P15
P16
P17
P23
P28
P29
R11
R12
R13
R14
R15
R16
R17
R18
R28
R4
T12
T13
T14
T15
T16
T17
T2
U12
U13
U14
U15
U16
U17
U23
U26
U27
U3
U5
V13
V15
V28
V29
W2
W26
W27
Y28
Y29
Y4
AB4
AB23
AB5
AB6
AD5
U4
W24

A1
A2
A28
A29
AH1
AH29
AJ1
AJ2
AJ28
AJ29
B1
B29

24 58Wednesday, February 14, 2007

1.0

of

5

1

2

D D

6

WF1F068N1A

C C

TOP VIEW

IDE_DD[0..15]22

IDE_RST_MOD23

USB_IDE#23

B B

A A

+3.3V_RUN

3

4

5

IDE_DD[0..15]

IDE_RST_MOD

R230

100K_0402_5%~D

1 2

+3.3V_ALW

IDE_DCS3#22

IDE_DA222
IDE_DA022
IDE_DA122

R205

470_0402_5%~D

1 2

IDE_DIOR#22
IDE_DIOW#22

R209

56_0402_5%~D

1 2

MODPRES#38

1 2

10K_0402_5%~D

R217

+5V_HDD +3.3V_RUN

C145

1000P_0402_50V7K~D

4

IDE_DCS3#
IDE_DA2
IDE_DA0
IDE_DA1

CSEL2
IDE_DIOR#
IDE_DIOW#
IDE_DD15

IDE_DD1
IDE_DD2
IDE_DD12
IDE_DD11

IDE_DD5
IDE_DD6
IDE_DD8
MOD_RST
USB_IDE#

MODPRES#

1

1

C469

2

2

0.1U_0402_16V4Z~D

Pleace near HD CONN

3

JMOD

72

G71G

1

8.3

G69G

1

3

3

5

5

7

7

9

9

11

11

13

13

15

15

17

17

19

19

21

21

23

23

25

25

27

27

29

29

31

31

33

33

IDE_DDACK#_R

35

35

37

37

39

39

41

41

43

43

45

45

47

47

49

49

51

51

53

53

55

55

57

57

59

59

61

61

63

63

65

65

67

67

TYCO_1770530-1~D

70

DASP#

PDIAG#

SC_USBP+
SC_USBP-

IDE_DCS1#

IDE_IRQ

1 2

R392 0_0402_5%~D

IDE_DIORDY

IDE_DDREQ
IDE_DD0
IDE_DD14
IDE_DD13

IDE_DD3
IDE_DD4
IDE_DD10
IDE_DD9

IDE_DD7

C60

10U_0805_10V4Z~D

IDE_DIORDY 22

2

2

4

4

6

6

8

8

10

10

12

12

14

14

16

16

18

18

20

20

22

22

24

24

26

26

28

28

30

30

32

32

34

34

36

36

38

38

40

40

42

42

44

44

46

46

48

48

50

50

52

52

54

54

56

56

58

58

60

60

62

62

64

64

66

66

68

68

1

C268

2

+5V_MOD

1

C262

2

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

SC_USBP+ 31
SC_USBP- 31

IDE_DCS1# 22

IDE_IRQ 22

IDE_DDACK# 22

4.7K_0402_5%~D

IDE_DDREQ 22

1

2

+3.3V_RUN

12

R206

PSATA_IRX_DTX_N0_C22
PSATA_IRX_DTX_P0_C22

close SATA connector

1

1

C465

10U_0805_10V4Z~D

C466

@

2

@

1

C464

@

2

2

0.1U_0402_16V4Z~D

0.1U_0402_10V7K~D

Pleace near HD CONN

2

MODC_EN38

100K_0402_5%~D

100K_0402_5%~D

HDDC_EN38

R692

100K_0402_5%~D

C461

3900P_0402_50V7K~D

C462

3900P_0402_50V7K~D

R618

100K_0402_5%~D

2

G

12

R691

+3.3V_ALW2

12

R626

2N7002W-7-F_SOT323-3~D

13

D

2

G

12

S

PSATA_ITX_DRX_P022
PSATA_ITX_DRX_N022

12
12

+3.3V_ALW2

12

2N7002W-7-F_SOT323-3~D

Q50

2

13

D

S

G

Q68
2N7002W-7-F_SOT323-3~D

HDD PWR

+15V_ALW

12

R627
100K_0402_5%~D

HDD_EN_5V

Q57

13

D

2

G

S

Q69
2N7002W-7-F_SOT323-3~D

+5V_HDD Source

PSATA_IRX_DTX_N0
PSATA_IRX_DTX_P0

+3.3V_RUN

MOD_EN

C812

+5V_ALW

3

1

2

0.1U_0603_50V4Z~D

+15V_ALW

12

R619
100K_0402_5%~D

2

13

D

S

+5VMOD Source

+5V_ALW

6

2

1

G

3

S

4 5

1

C817

0.1U_0603_50V4Z~D

PSATA_ITX_DRX_P0
PSATA_ITX_DRX_N0

+5V_HDD

1

C818

2

2

10U_0805_10V4Z~D

1

6

2

1

D

Q48

G

SI3456BDV-T1-E3_TSOP6~D

S

4 5

1

C813

2

10U_0805_10V4Z~D

D

Q56

SI3456BDV-T1-E3_TSOP6~D

+5V_HDD

12

R629

JSATA

1
2
3
4
5
6
7

8
9

10
11
12
13
14
15
16
17
18
19
20
21
22

TYCO_1775191-1_RV~D

12

PJP2003

1 2

PAD-OPEN 4x4m@

Open

100K_0402_5%~D

GND
RX+
RX­GND
TX­TX+
GND

3.3V

3.3V

3.3V
GND
GND
GND
5V
5V
5V
GND
Reserved
GND
12V
12V
12V

+5V_MOD

1

R622

2

100K_0402_5%~D

GND1
GND2

Main SATA +5V Default

C211

0.01U_0402_16V7K~D

+5V_RUN

23
24

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

DVD MODULE

LA-3301P

25 58Monday, February 26, 2007

1

1.0

of

5

4

3

2

1

45

+VDDA

2

1

C710

D D

5

SPKR23
BEEP39

1

B

2

A

3

U34 place as close to CODEC as possible

C C

ICH_AZ_CODEC_BITCLK

12

R545
10_0402_5%~D

Close to Pin 6

1

C721
10P_0402_50V8J~D

B B

A A

2

ICH_AZ_CODEC_SDOUT

12

R479
47_0402_5%~D

@

Close to Pin 5

1

C782

0.1U_0402_16V4Z~D

2

@

0.1U_0402_16V4Z~D

2

U34

P

4

Y

G

74AHCT1G86GW_SOT353-5~D

20K_0402_5%~D

1 2

R540

10K_0402_5%~D

+3.3V_RUN

1

C714

2

0.1U_0402_16V4Z~D

ICH_AZ_CODEC_SDIN022

12

R541

C759

1000P_0402_50V7K~D

C711

0.1U_0402_10V6K~D

1 2

TRACE>15 mil

R821

100K_0402_5%~D

1 2

1

2

ICH_AZ_CODEC_BITCLK22

1 2

R544 33_0402_5%~D

ICH_AZ_CODEC_SDOUT22
ICH_AZ_CO D EC_SYNC22
ICH_AZ_CODEC_RST#22

AUD_EAPD27

AUD_SPDIF_OUT36

10K_0402_5%~D

AUD_PC_BEEPBEEP1 BEEP2

C715

1U_0603_10V4Z~D

R823

W=30 mil

1

1

C172

C716

2

2

@

10U_0805_10V4Z~D

0.1U_0402_16V4Z~D

ICH_AZ_CODEC_BITCLK
ICH_AC_SDIN0_R

ICH_AZ_CODEC_SDOUT

AUD_EAPD
AUD_SPDIF_OUT

12

1

2

+3.3V_RUN

U35

1

DVDD_CORE

9

DVDD_CORE

40

DVDD_CORE/VPP

3

DVDD_IO

6

HDA_BIT_CLK

8

HDA_SDI_CODEC

5

HDA_SDO

10

HDA_SYNC

11

HDA_RST#

43

NC1

44

NC2

45

NC3

46

DMIC_CLK

2

VOL_UP/DMIC0/GPIO1

4

VOL_DN/DMIC1/GPIO2

47

SPDIF_ IN//GPIO0/EAPD

48

SPDIF _OUT

7

DVSS

26

AVSS1

42

AVSS2

49

Thermal PAD GND

QFN 7x7 & LQFP 9x9 colay footprint.

STAC9205X5NBEB1XR_QFN48_COMON~D

STAC9205

VREFOUT_E/GPIO4

VREFOUT_F/GPIO3

AVDD1
AVDD2

SENSE_A
SENSE_B

PORT_A_L
PORT_A_R

VREFOUT_A

PORT_B_L
PORT_B_R

VREFOUT_B

PORT_C_L
PORT_C_R

VREFOUT_C

PORT_D_L
PORT_D_R

PORT_E_L
PORT_E_R

PORT_F_L
PORT_F_R

CD_L

CD_GND

CD_R

PC_BEEP

MONO_OUT

CAP2

VREFFILT

25
38

13
34

39
41
37

21
22
28

23
24
29

35
36

14
15
31

16
17
30

18
19
20

12
32

33
27

+VDDA

AUD_SENSE_A
AUD_SENSE_B

1

2

1

1

C726

C717

2

2

1U_0603_10V4Z~D

AUD_LINE_OUT_L
AUD_LINE_OUT_R

DOCK_HP_MUTE#

AUD_PC_BEEP

1

C724

C725

2

10U_0805_10V4Z~D

10U_0805_10V4Z~D

1

C718

2

@

10U_0805_10V6K~D

0.1U_0402_10V7K~D

AUD_SPDIF_SHDN 38

AUD_HP_OUT_L 27
AUD_HP_OUT_R 27

AUD_EXT_MIC_L 27
AUD_EXT_MIC_R 27

VREFOUT

AUD_INT_MIC_IN 27

AUD_LINE_OUT_L 27
AUD_LINE_OUT_R 27

DOCK_HP_MUTE# 38

AUD_SENSE_A

AUD_HP_NB_ SENSE

2N7002W-7-F_SOT323~D

Q74

R710

39.2K_0402_1%~D

2

G

single gate TTL

12

12

13

13

D

D

Q75

S

S

2N7002W-7-F_SOT323~D

AUD_SENSE_B

DOCK_HP_MUTE#

AUD_SPDIF_SHDN

5.11K_0402_1%~D

20K_0402_1%~D

R711

2

G

10K_0402_5%~D

31

+VDDA

R542

12

1

C713

2

1000P_0402_50V7K~D

AUD_MIC_SWITCH 27AUD_HP_NB_SENSE27,38

R543

R546 10K_0402_5%~D

R547 10K_0402_5%~D

+VDDA

12

12

12

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.
Azalia (HD) Codec

LA-3301P

26 58Monday, February 26, 2007

1

1.0

of

5

+VDDA

+VDDA

D D

C C

LM358DR2G_SOIC8~D

AUD_MIC_BIAS

Speaker Connector

INT_SPK_R1
INT_SPK_R2

U36A

1

O

15 mils trace

1

C740

2

@

100P_0402_50V8J~D

+5V_SPK+AMP

R571

Q43

12

+5V_SPK+AMP

1 2

13

2

G

13

2

G

5

R713
100K_0402_5%~D

AUD_AMP_MUTE#

D

S

D

S

B B

For TPA6040A,pop
R714,depop R713

AUDIO_AVDD_ON

A A

1 2

R714

@

0_0402_5%~D

100K_0402_5%~D

ADU_SPK_ENABLE#

AUD_EAPD26

2N7002W-7-F_SOT323-3~D

NB_MUTE#38

12

R556
100K_0402_5%~D

3
2

1

2

100P_0402_50V8J~D

12

R712
100K_0402_5%~D

12

R559

100K_0402_5%~D

8

P

IN+

IN-

G

4

C741

@

Q42
2N7002W-7-F_SOT323-3~D

1

C732

2.2U_0805_10V6K~D

2

JSPK

1

1

2

2

MOLEX_53398-0271~D

AUD_LINE_OUT_L26

AUD_LINE_OUT_R26

AUD_HP_OUT_L26

AUD_HP_OUT_R26

AUD_HP_NB_ SENSE
NB_MUTE#

C77 0.033U_1206_50V7K~D

C748 0.033U_1206_50V7K~D

C749 1U_1206_25V7K~D

C751 1U_1206_25V7K~D

+5V_SPK+AMP

5

2

P

A

1

B

G

3

AUD_EAPD

10_0402_5%~D

@

10P_0402_50V8J~D

4

C729

2.2U_0805_10V6K~D

AUD_INT_MIC+32
AUD_INT_MIC-32

C737

2.2U_0805_10V6K~D

12

12

1 2

1 2

1

C905

C906

2

@

U40

Y

74AHCT1G08GW_SOT353-5~D

R790

@

C232

@

47P_0402_50V8J~D

4

47P_0402_50V8J~D

12

1

2

4

+VDDA

12

12

1

C907

2

@

47P_0402_50V8J~D

+5V_SPK+AMP

12

R553
1K_0402_5%~D

12

R558
1K_0402_5%~D

C731

0.1U_0402_10V6K~D

1 2
1 2

C736

0.1U_0402_10V6K~D

12

R566
1K_0402_5%~D

12

R568
1K_0402_5%~D

1

1

C96

2

2

@

47P_0402_50V8J~D

1

2

3

R554

0_0402_5%~D

R560

10K_0402_5%~D

1 2
1 2

R563

10K_0402_5%~D

5
6

100K_0402_5%~D

Place Close to Audio Chip Place C lose to Audio Chip

1

C742

C743

2

1U_0603_10V4Z~D

SPKR_INL_C INT_SPK_R1

SPKR_INR_C

HP_INL_C

HP_INR_C

12

C752 1U_0603_10V4Z~D

ADU_SPK_ENABLE#

AUD_AMP_MUTE#

C754

1

1U_0603_10V4Z~D

C753

2

10U_0805_10V4Z~D

12

1

R822

C755

2

1M_0402_1%~D

AUD_MIC_BIAS

1 2

+VDDA

U36B

8

LM358DR2G_SOIC8~D

P

IN+

7

1 2

O

IN-

G

4

1 2

R565

1

C783

2

1U_0603_10V4Z~D

C1P
C1N

1U_0603_10V4Z~D

C733

0.1U_0805_25V7K~D

1

2

U37

0.1U_0402_16V4Z~D

3

SPKR_INL

2

SPKR_INR

27

HP_INL

26

HP_INR

24

BIAS

23

SPKR_EN#

22

HP_EN

25

MUTE#

17

HPVDD

9

CPVDD

10

C1P

12

C1N

11

CPGND

C758

12

1U_0603_10V4Z~D

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

AUD_EXT_MIC_L26

AUD_EXT_MIC_R26

AUD_INT_MIC_IN 26

BLM21PG600SN1D_0805~D

8

30

VDD

MAX9789A

CPVSS13PVSS

GND

EP

5

14

28

33

L51

1 2

+5V_SPK+AMP

18

PVDD1

PVDD2

OUTL+

OUTL-

OUTR+

OUTR-

GAIN1
GAIN2

REGEN

VOUT

PGND221PGND1

MAX9789A_TQFN32~D

HPL

HPR

SET

5.1_0402_1%~D

5.1_0402_1%~D

+5V_RUN

1

2

6

7

20

19

16

15

31
32

REGEN

4

29

1

R584

For
TPA6040A,
pop
C304,depop
R584

AUD_MIC_SWITCH26

W=40mils

C744

INT_SPK_R2

HP_SPK_L1

HP_SPK_R1

AUD_GAIN1
AUD_GAIN2

SET

12

2

VREFOUT_R

R580

R796 0_0402_5%~D

R797 0_0402_5%~D

12

R551

4.7K_0402_5%~D

12

12

12

R561

@

20K_0402_1%~D

1

1

C738

C739

2

2

100P_0402_50V8J~D

100P_0402_50V8J~D

*

12

R552

12

MIC_L2

MIC_R2

R564

100K_0402_5%~D

L49

L50

10U_0805_10V4Z~D

AUDIO_AVDD_ON 18

+VDDA

C757

1U_0603_10V4Z~D

2

1 2

0_0402_5%~D

12
12

MINIMAM 150 mA

VREFOUT

R555

R557

1

C745

2

1U_0603_10V4Z~D

For TPA6040A, po p C301,depop R585

R585 0_0402_5%~D

1 2

1 2

C301

@

0.033U_1206_50V7K~D

1

2

@

0_0402_5%~D

C728

1U_0603_10V6K~D

MIC_L1

1 2

12

MIC_R1

1 2

12

C730

1U_0603_10V6K~D

+3.3V_RUN

12

BLM18BD121SN1D_0603~D

HP_SPK_L1 HP_SPK_L2

BLM18BD121SN1D_0603~D

+5V_SPK+AMP

1

1

C746

C747

2

2

1U_0603_10V4Z~D

10U_0805_10V4Z~D

1

1

C756

2

2

1U_0603_10V4Z~D

C304

0.033U_1206_50V7K~D

1

C735

2

100P_0402_50V8J~D

+3.3V_RUN

12

12

1

12

Gain Setting

R569
100K_0402_5%~D

R572
100K_0402_5%~D@

6dB

10dB

15.6dB

21.6dB

JMIC

1
2
6
3

4
5

7
8

FOX_JA9033L-B1N6-7F~D

JAUDIO

1
2
6
3

4
5

7
8

FOX_JA9033L-B1N6-7F~D

12

R570
100K_0402_5%~D@

12

R573
100K_0402_5%~D

IMPEDANCE

82K ohm

66K ohm

45K ohm

26K ohm

C727

1 2

10U_0805_10V4Z~D

4.7K_0402_5%~D

L47

BLM18BD601SN1D_0603~D

12

12

L48

BLM18BD601SN1D_0603~D

1

20K_0402_1%~D

AUD_HP_NB_SENSE26,38

C734

2

100P_0402_50V8J~D

100K_0402_5%~D

HP_SPK_R2HP_SPK_R1

AUD_GAIN1
AUD_GAIN2

R562

@

GAIN1 INPUTAV(inv)GAIN2

0

0

1

0

1

0

11

R567

+5V_SPK+AMP

DELL CONFIDENTIAL/PROPRIETARY

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.
AMP and PHONE JACK

LA-3301P

27 58Wednesday, March 07, 2007

1

of

1.0

5

Layout Notice : Place as close

+3.3V_LAN

TPM_GPIO0
TPM_GPIO1
TPM_GPIO2

2

C862

1

chip as possible.

2

C836

C837

1

4.7U_0603_6.3V4Z~D

R415

4.7K_0402_5%~D

R421

4.7K_0402_5%~D

XTALO

XTALI

22P_0402_50V8J~D

2

2

C838

1

1

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

GPIO1_SERIAL_DI

12

LOM_LOW_PWR

12

U38A

J8

LCLK

J7

LAD0

L10

LAD1

J5

LAD2

K9

LAD3

J9

LFRAME

M10

LRESET

H7

SERIRQ

G4

TPM_GPIO0

J3

TPM_GPIO1

H3

TPM_GPIO2/TPM_STATUS

J6

TPM_EN

H9

GPIO0

H11

GPIO1_SERIAL_DI

C5

GPIO2_SERIAL_DO

C4

EnergyDet

C8

SMB_CLK

C7

SMB_DATA

C9

SCLK

E10

SI

D9

SO

C10

CS

M2

NV_STRAP0

M1

NV_STRAP1

A9

LINKLED

B9

SPD100LED

A10

SPD1000LED

B8

TRAFFICLED

M9

XTALO

L9

XTALI

2

2

C840

C839

1

1

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

BCM5755M

LPC/TPM

GPIO

SMBUS

SPI

LED

Clock

Layout Notice : No high
speed signal should be
routed near RDAC or on
adjacent layer to RDAC

+3.3V_ALW

Q44

2

C309

C316

1

D D

0.1U_0402_16V4Z~D

4.7U_0603_6.3V4Z~D

C C

@
@
@

LOM_TPM_EN#38

LOM_SMB_ALERT#23,39

LOM_CABLE_DETECT38

R646, R648, R649 Reserved for
BCM5752 as back-up solution

B B

A A

+3.3V_LAN

2

C861

1

LOM_CABLE_DETECT goes to an input on a system microcontroller that can
poll this signal periodically and can de-assert the LOM_LOW_PWR when
LOM_CABLE_DETECT signal is high. Connect to an EC GPIOC defined by the
GPIO mapping.

SI3456BDV-T1-E3_TSOP6~D

2

1

ENAB_3VLAN41

Place closely pin J8

33_0402_5%~D

22P_0402_50V8J~D

CLK_PCI_TPM6

LPC_LAD[0..3]22,38,39

R646 10K_0402_5%~D
R648 10K_0402_5%~D
R649 10K_0402_5%~D

@

4.7K_0402_5%~D

LOM_SPD10LED_GRN#29

LOM_SPD100LED_ORG#29

25MHZ_18PF_1BX25000CK1D~D

Need to ensure
crystal at least
300uW max power

22P_0402_50V8J~D

drive-level

D

6

S

45
2
1

CLK_PCI_TPM

R654

@

C854

LPC_LFRAME#22,38,39
PLTRST3#21,34

IRQ_SERIRQ23,30,38,39

R651 0_0402_5%~D

R653 4.7K_0402_5%~D@

LOM_LOW_PWR GPIO2_SERIAL_DO

R655

1 2

LOM_ACTLED_YEL#29

200_0402_1%~D

1 2

Y5

G

3

12

1

2

@

12
12
12
12

12

LOM_SMB_ALERT#
GPIO1_SERIAL_DI

1 2

R422
1K_0402_5%~D

ICH_SMBCLK23,34
ICH_SMBDATA23,34

LOM_SCLK
LOM_SI
LOM_SO
LOM_CS#
NV_STRAP0

R659

12

5

CLK_PCI_TPM
LPC_LAD0

LPC_LAD1
LPC_LAD2
LPC_LAD3

LPC_LFRAME#
PLTRST3#
IRQ_SERIRQ

LOM_SPD10LED_GRN#
LOM_SPD100LED_ORG#

LOM_ACTLED_YEL#

4

MMJT9435

C

2

B

1C4

+3.3V_LAN

R7, R9 are 1/2 W rating

Media

LOW_PWR

Super_Low_PWR

VMAINPRSNT

VAUXPRSNT

Control

PowerPCI-ETEST

REGSUP12
REGCTL12

REGSEN12
REGSUP25
REGCTL25

REGSEN25

Control

Regulator

PCIE_TXDN
PCIE_TXDP
PCIE_RXDN
PCIE_RXDP

REFCLK+

CLKREQ#

REFCLK_SEL

GPHY_TVCOI

Bias

BCM5755M_FBGA144~D

REGCTL_PNP12

@

0.047U_0402_16V4Z~D

B11

TRD3+

B12

TRD3-

C11

TRD2+

C12

TRD2-

D11

TRD1+

D12

TRD1-

E11

TRD0+

E12

TRD0-

H4
K5

G11
B6

K12
J11

J12
L12
M11

M12

M3
L3
L7
M7
A4

WAKE

L5

REFCLK-

M5
F2
B3
B1

PERST

B5

TCK

F3

TDI

B4

TDO

E3

TMS

D4

TRST

C6
J1

NC

M4

NC

A8

RDAC

4

GLAN_RXN_C
GLAN_RXP_C

E

3

1

1

C772

2

LAN_TX3+

LAN_TX3+ 29

LAN_TX3-

LAN_TX3- 29

LAN_TX2+

LAN_TX2+ 29

LAN_TX2-

LAN_TX2- 29

LAN_TX1+

LAN_TX1+ 29

LAN_TX1-

LAN_TX1- 29

LAN_TX0+

LAN_TX0+ 29

LAN_TX0-

LAN_TX0- 29

0_0402_5%~D@
R488

1 2

R650 1K_0402_5%~D
R652 1K_0402_5%~D

REGCTL_PNP12

REGCTL_PNP25

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

PCIE_WAKE#
CLK_PCIE_LOM#
CLK_PCIE_LOM

1 2

R656 0_0402_5%~D

1 2

R657 4.7K_0402_5%~D@

R658

@

4.7K_0402_5%~D

1 2

PHYTVCOI

1 2

R666 0_0402_5%~D@

Monitor GPHY PLL Clk

1 2

R663

@

4.7K_0402_5%~D

R669

1 2

1.13K_0402_1%~D

+3.3V_LAN

12

R643

2_1210_5%~D

Q71
PBSS5540Z_SOT223-3~D

2 3

4

LOM_LOW_PWR 38

12
12

C851

1 2
1 2

C853

PCIE_WAKE# 34,38
CLK_PCIE_LOM# 6
CLK_PCIE_LOM 6

12
12

+3.3V_LAN

0.1U_0402_16V4Z~D

12

R644

2_1210_5%~D

1

C845

2

+3.3V_RUN
+3.3V_LAN

+3.3V_LAN

+1.2V_LAN
+3.3V_LAN

+2.5V_LAN

PCIE_RX6-/GLAN_RX- 23
PCIE_RX6+/GLAN_RX+ 23
PCIE_TX6-/GLAN_TX- 23
PCIE_TX6+/GLAN_TX+ 23

LOM_CLKREQ# 6

PLTRST3#LOM_RST_R#

R5810_0402_5%~D

SB_LOM_PCIE_RST# 21

PLTRST3# 21,34

Place R666 as
close to the ASIC
as possible. Pad
is needed to
measure 125MHz
clock for
debugging

R5820_0402_5%~D @

3

4.7U_0603_6.3V4Z~D

1

1

C826

C827

2

2

+2.5V_LAN

+1.2V_LAN

0.1U_0402_16V4Z~D

10U_0805_10V4Z~D

1

C846

2

Logic High Voltage must
be 0.7V to 2.75V

R647

20K_0402_5%~D

12

12

R276
39K_0402_5%~D

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

L63

BK2125LM182-T_0805~D

BK1608LM182-T_0603~D

LOM_SUPER_IDDQ 38

+3.3V_LAN

0.1U_0402_16V4Z~D

12

1000P_0402_50V7K~D

L64

12

47P_0402_50V8J~D

L65

12

BK2125LM182-T_0805~D

47P_0402_50V8J~D

LOM_SI

C865

2

1

C849

C850

C852

MBT35200MT1G_TSOP6~D

REGCTL_PNP25

+XTALVDD

1

2

+BIASVDD

1

2

+AVDD

1

2

+1.2V_LAN

L66

BK1608LM182-T_0603~D

C855

4.7U_0603_6.3V4Z~D

L67

BK1608LM182-T_0603~D

C857

4.7U_0603_6.3V4Z~D

L68

BK1608LM182-T_0603~D

C859

4.7U_0603_6.3V4Z~D

L88

BK1608LM182-T_0603~D

C863

4.7U_0603_6.3V4Z~D

U44

8
7
6
5

M45PE20-VMN6TP_SO8~D

8
7
6
5

AT45BCM021B-SU_SO8~D

Q
VSS
VCC
W#

SO
GND
VCC
WP#

RESET#

@

SCK

RESET#

D
C

S#

U45

SI

CS#

1

C771

2

@

12

1

2

12

1

2

12

1

2

12

1

2

1
2
3
4

1
2
3
4

Q70

3

0.047U_0402_16V4Z~D

+2.5V_LAN

C847

+3.3V_LAN

R665

@

4.7K_0402_5%~D

LOM_SO
LOM_SCLK

LOM_CS#

1

2

1

2

1

2

1

2

2

+3.3V_LAN

41

256

0.1U_0402_16V4Z~D

1

C848

2

+AVDDL

C856
47P_0402_50V8J~D

+GPHY_PLLVDD

C858
47P_0402_50V8J~D

+PCIE_PLLVDD

C860

0.1U_0402_16V4Z~D

+PCIE_SDS_VDD

C864

0.1U_0402_16V4Z~D

12

12

R664

@

4.7K_0402_5%~D

2

0.1U_0402_16V4Z~D

1

2

0.1U_0402_16V4Z~D

1

C842

2

0.1U_0402_16V4Z~D

1

2

12

R670

@

4.7K_0402_5%~D

4.7U_0603_6.3V4Z~D

1

C824

C825

2

+2.5V_LAN

10U_0805_10V4Z~D

1

C843

2

+3.3V_LAN

+2.5V_LAN

+XTALVDD

+PCIE_SDS_VDD

+BIASVDD

+AVDDL

+AVDD

+PCIE_PLLVDD

+GPHY_PLLVDD

(Default)

Atmel AT45BCM021B

ST M45PE20

1

Layout Notice : 1.2V filter. Place as close
chip as possible.

+1.2V_LAN

2

C830

C831

1

0.1U_0402_16V4Z~D

BCM5755M

BIAS

Analog
power

2

C832

1

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

GND

PLL

BCM5755M_FBGA144~D

+3.3V_LAN

2

C833

1

0.1U_0402_16V4Z~D

@

2

C834

1

0.1U_0402_16V4Z~D

VSS_0
VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8

VSS_9
VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20

DC_0
DC_1
DC_2
DC_3
DC_4
DC_5
DC_6
DC_7
DC_8

DC_9
DC_10
DC_11
DC_12
DC_13
DC_14
DC_15
DC_16
DC_17
DC_18
DC_19

NC_0

NC_1

NC_2

NC_3

NC_4

NC_5

NC_6

NC_7

NC_8

1 2

R661

4.7K_0402_5%~D

1

C629

2

@

4.7U_0603_6.3V4Z~D

+1.2V_LAN

Reserved for BCM5752
as back-up solution

C828

2

1

0.1U_0402_16V4Z~D

D10
G10

L11

H12

A12

F10
F11

A11
F12

G12

2

C829

1

0.1U_0402_16V4Z~D

U38B

D5

VDDC_0

D6

VDDC_1

D7

VDDC_2

D8

VDDC_3

H5

VDDC_4

H6

VDDC_5

H8

VDDC_6

J4

VDDC_7

Digial power

A3

VDDIO_0

C2

VDDIO_1
VDDIO_2

F1

VDDIO_3
VDDIO_4

J2

VDDIO_5

L1

VDDIO_6

A5

VDDP_0

G3

VDDP_1
VDDP_2

XTALVDD

K4

PCIE_SDSVDD

BIASVDD

AVDDL_0
AVDDL_1

AVDD_0
AVDD_1

K6

PCIE_PLLVDD
GPHY_PLLVDD

NV_STRAP1 NV _STRAP0 SO CS#SI

00Auto-Sense Mode 0 0

0

00110

10

DELL CONFIDENTIAL/PROPRIETARY

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

BCM5755M

LA-3301P

28 58Monday, February 26, 2007

1

2

2

C835

1

1

0.1U_0402_16V4Z~D

B2
B10
E4
E5
E6
E7
E8
E9
F4
F5
F6
F7
F8
F9
G5
G6
G7
G8
L2
L6
M6

A1
A6
A7
B7
C1
C3
D1
D2
D3
E1
G2
H2
K1
K2
K3
K7
K8
L4
L8
M8
A2
E2
G1
G9
H1
H10
J10
K10
K11

SCLK

00

11

1

0

1.0

of

5

4

3

2

1

0B1

VDD04VDD110VDD218VDD327VDD438VDD550VDD6

1B1
2B1

3B1
4B1

5B1
6B1

7B1

0LED1
1LED1
2LED1

0B2
1B2

2B2
3B2

4B2
5B2

6B2
7B2

0LED2
1LED2
2LED2

PI3L500-AZFEX_TQFN56~D

55

+3.3V_LAN

@

@

12

LAN ANALOG
SWITCH

SW_LAN_TX0-

48

SW_LAN_TX0+

47

SW_LAN_TX1-

43

SW_LAN_TX1+

42

SW_LAN_TX2-

37

SW_LAN_TX2+

36

SW_LAN_TX3-

32

SW_LAN_TX3+

31

LAN_LEDACT#

22

LINK_LED10#

23

LINK_LED100#

52

DOCK_LAN_TX0-

46

DOCK_LAN_TX0+

45

DOCK_LAN_TX1-

41

DOCK_LAN_TX1+

40

DOCK_LAN_TX2-

35

DOCK_LAN_TX2+

34

DOCK_LAN_TX3-

30

DOCK_LAN_TX3+

29

DOCK_LOM_ACTLED_YEL#

25

DOCK_LOM_SPD10LED_GRN#

26

DOCK_LOM_SPD100LED_ORG#

51

SW_LAN_TX0- 32
SW_LAN_TX0+ 32

SW_LAN_TX1- 32
SW_LAN_TX1+ 32

SW_LAN_TX2- 32
SW_LAN_TX2+ 32

SW_LAN_TX3- 32
SW_LAN_TX3+ 32

DOCK_LAN_TX0- 36
DOCK_LAN_TX0+ 36

DOCK_LAN_TX1- 36
DOCK_LAN_TX1+ 36

DOCK_LAN_TX2- 36
DOCK_LAN_TX2+ 36

DOCK_LAN_TX3- 36
DOCK_LAN_TX3+ 36

DOCK_LOM_ACTLED_YEL# 36
DOCK_LOM_SPD10LED_GRN# 36
DOCK_LOM_SPD100LED_ORG# 36

TO

DOCK

+3.3V_LAN

C866 0.1U_0402_16V4Z~D@

1 2

C867 0.1U_0402_16V4Z~D @

1 2

C868 0.1U_0402_16V4Z~D@

1 2

C869 0.1U_0402_16V4Z~D@

D D

C C

1 2

R671 49.9_0402_1%~D @

1 2

R672 49.9_0402_1%~D@

1 2

R673 49.9_0402_1%~D@

1 2

R674 49.9_0402_1%~D@

1 2

R675 49.9_0402_1%~D@

1 2

R676 49.9_0402_1%~D@

1 2

R677 49.9_0402_1%~D@

1 2

R678 49.9_0402_1%~D@

1 2

Layout Notice : Place
terminatio n a s close as
ASIC as possible

The resistors need at
least 1/16W

LAN_TX0­LAN_TX0+
LAN_TX1­LAN_TX1+
LAN_TX2­LAN_TX2+
LAN_TX3­LAN_TX3+

LAN_TX0-28
LAN_TX0+28

LAN_TX1-28
LAN_TX1+28

LAN_TX2-28
LAN_TX2+28

LAN_TX3-28
LAN_TX3+28

Layout Notice : Place bead as
close PI3L500 as possible

LAN_TX0- LAN_TX0-R

L69 36NH_0603CS-360EJTS_5%_0603~D

LAN_TX0+ LAN_TX0+R

L70 36NH_0603CS-360EJTS_5%_0603~D

LAN_TX1- LAN_TX1-R

L71 36NH_0603CS-360EJTS_5%_0603~D

LAN_TX1+ LAN_TX1+R

L72 36NH_0603CS-360EJTS_5%_0603~D

LAN_TX2- LAN_TX2-R

L73 36NH_0603CS-360EJTS_5%_0603~D

LAN_TX2+ LAN_TX2+R

L74 36NH_0603CS-360EJTS_5%_0603~D

LAN_TX3- LAN_TX3-R

L75 36NH_0603CS-360EJTS_5%_0603~D

LAN_TX3+ LAN_TX3+R

L76 36NH_0603CS-360EJTS_5%_0603~D

DOCKED

DOCKED36,38

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

LOM_ACTLED_YEL#28
LOM_SPD10LED_GRN#28
LOM_SPD100LED_ORG#28

FROM NIC DOCKED

1: TO DOCK
0: TO RJ45

11
12

14
15

17

19
20
54

57

56

U46

2

A0

3

A1

7

A2

8

A3

A4
A5

A6
A7

SEL

LED0
LED1
LED2

5

NC
PAD_GND

GND01GND16GND29GND313GND416GND521GND624GND728GND833GND939GND1044GND1149GND1253GND13

@

12

12

R680

10K_0402_5%~D

R682

1 2

150_0402_5%~D

R683

1 2

110_0402_5%~D

R684

1 2

200_0402_5%~D

R681

10K_0402_5%~D

10K_0402_5%~D

LED_10_GRN_R#

LED_100_ORG_R#

LAN_ACTLED_YEL_R# 32

LED_10_GRN_R# 32

LED_100_ORG_R# 32

R679

LOM_ACTLED_YEL#
LOM_SPD10LED_GRN#
LOM_SPD100LED_ORG#

B B

LAN_LEDACT# LAN_ACTLED_YEL_R#

LINK_LED10#

LINK_LED100#

A A

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.
LAN TRANSFOMER

LA-3301P

29 58Monday, February 26, 2007

1

1.0

of

8

D D

C C

B B

A A

+3.3V_RUN

+3.3V_RUN

BLM18AG121SN1D_0603~D

8

1

C795

C794

2

4.7U_0603_6.3V4Z~D

L60

1 2

C802

Place closely pin 45

CLK_PCI_PCM

R610

10_0402_5%~D

PCI_AD17

C808

100_0402_5%~D

1 2

4.7P_0402_50V8C~D

0.1U_0402_16V4Z~D

4.7U_0603_6.3V4Z~D

@

@

R615

PCI_DEVSEL#21,35
PCI_FRAME#21,35,36
PCI_IRDY#21,35,36
PCI_TRDY#21,35
PCI_STOP#21,35
PCI_PAR21,35

7

1

C796

2

1

C803

2

12

1

2

CLK_PCI_PCM6

PCI_REQ1#21

PCI_GNT1#21
PCI_RST#21,31,35

SYS_PME#35,38

IRQ_SERIRQ23,28,38,39

1

1

C800

2

0.1U_0402_16V4Z~D

1

C804

2

0.1U_0402_16V4Z~D

PCI_AD[0..31]21,35

7

2

0.1U_0402_16V4Z~D

1

2

0.1U_0402_16V4Z~D

PCI_C_BE3#21,35
PCI_C_BE2#21,35
PCI_C_BE1#21,35
PCI_C_BE0#21,35

1

C801

2

0.1U_0402_16V4Z~D

CBS_IDSEL
CLK_PCI_PCM
PCI_DEVSEL#
PCI_FRAME#
PCI_IRDY#
PCI_TRDY#
PCI_STOP#
PCI_PAR
PCI_REQ1#
PCI_GNT1#
PCI_RST#

IRQ_SERIRQ

PCI_AD31
PCI_AD30
PCI_AD29
PCI_AD28
PCI_AD27
PCI_AD26
PCI_AD25
PCI_AD24
PCI_AD23
PCI_AD22
PCI_AD21
PCI_AD20
PCI_AD19
PCI_AD18
PCI_AD17
PCI_AD16
PCI_AD15
PCI_AD14
PCI_AD13
PCI_AD12
PCI_AD11
PCI_AD10
PCI_AD9
PCI_AD8
PCI_AD7
PCI_AD6
PCI_AD5
PCI_AD4
PCI_AD3
PCI_AD2
PCI_AD1
PCI_AD0

PCI_C_BE3#
PCI_C_BE2#
PCI_C_BE1#
PCI_C_BE0#

6

+OZ1.8V_RUN

1

1

C798

C797

2

2

0.1U_0402_16V4Z~D

4.7U_0603_6.3V4Z~D

11

CORE_3.3

97

CORE_3.3

26

PCI_VCC

56

PCI_VCC

65

CORE_3.3A

68

CORE_3.3A

73

CORE_3.3A

19

AD31

20

AD30

21

AD29

22

AD28

23

AD27

24

AD26

25

AD25

27

AD24

29

AD23

30

AD22

31

AD21

32

AD20

34

AD19

35

AD18

36

AD17

37

AD16

47

AD15

48

AD14

49

AD13

50

AD12

51

AD11

52

AD10

53

AD9

54

AD8

57

AD7

58

AD6

59

AD5

60

AD4

61

AD3

62

AD2

63

AD1

64

AD0

28

C/BE3#

38

C/BE2#

46

C/BE1#

55

C/BE0#

9

IDSEL

45

PCI_CLK

42

DEVSEL#

39

FRAME#

40

IRDY#

41

TRDY#

43

STOP#

44

PAR

17

REQ#

18

GNT#

5

PCI_RST#

7

PME#

6

SERIRQ

GND33GND

Ground pin 129 exposed die pad, dimension

5.72mm x 5.72mm, should connect to PCB solder
pad of same dimension

6

82

8

EPSI

CORE_1.816CORE_1.8

OZ711EZ1

GND

OZ711EZ1TN C_E-LQFP128_16X16~D

108

129

CFRAME#

CDEVSEL#

CBLOCK#

CCLKRUN#

CSTSCHG

5

R602 33_0402_5%~D

U42

72

REF

74

XI

75

XO

71

BIAS

70

TPA+

69

TPA-

67

TPB+

66

TPB-

3

CAD31

1

CAD30

128

CAD29

127

CAD28

126

CAD27

125

CAD26

124

CAD25

122

CAD24

120

CAD23

118

CAD22

116

CAD21

115

CAD20

114

CAD19

113

CAD18

112

CAD17

96

CAD16

94

CAD15

93

CAD14

92

CAD13

91

CAD12

90

CAD11

89

CAD10

88

CAD9

87

CAD8

84

CAD7

83

CAD6

81

CAD5

80

CAD4

79

CAD3

78

CAD2

77

CAD1

76

CAD0

106

CCLK

110
109

CIRDY#

107

CTRDY#

105
103

CSTOP#

98

CPAR

100

CPERR#

119

CSERR#

121

CREQ#

102

CGNT#

104

CINT#

101
4
117

CRST#

2

R2_D2

85

R2_D14

99

R2_A18

12

CVS1

15

CVS2

10

CCD1#

14

CCD2#

13
123

CC/BE3#

111

CC/BE2#

95

CC/BE1#

86

CC/BE0#

5

R603

5.9K_0402_1%~D

1 2

1 2

R114 0_0402_5%~D

CBS_CAD31
CBS_CAD30
CBS_CAD29
CBS_CAD28
CBS_CAD27
CBS_CAD26
CBS_CAD25
CBS_CAD24
CBS_CAD23
CBS_CAD22
CBS_CAD21
CBS_CAD20
CBS_CAD19
CBS_CAD18
CBS_CAD17
CBS_CAD16
CBS_CAD15
CBS_CAD14
CBS_CAD13
CBS_CAD12
CBS_CAD11
CBS_CAD10
CBS_CAD9
CBS_CAD8
CBS_CAD7
CBS_CAD6
CBS_CAD5
CBS_CAD4
CBS_CAD3
CBS_CAD2
CBS_CAD1
CBS_CAD0

R614 0_0402_5%~D

CBS_CFRAME#

CBS_CIRDY#

CBS_CTRDY#

CBS_CDEVSEL#

CBS_CSTOP#

CBS_CPAR
CBS_CPERR#
CBS_CSERR#

CBS_CREQ#
CBS_CGNT#

CBS_CINT#

CBS_CBLOCK#

CBS_CCLKRUN#

CBS_CRST#

CBS_RSVD/D2
CBS_RSVD/D14
CBS_RSVD/A18

CBS_CVS1

CBS_CVS2
CBS_CCD1#
CBS_CCD2#

CBS_CSTSCHNG

CBS_CC/BE3#
CBS_CC/BE2#
CBS_CC/BE1#
CBS_CC/BE0#

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

4

PCI_PERR#21,35

PCI_SERR#21,35

CLKRUN#23,38,39

PCI_PIRQD#21

C806

12P_0402_50V8J~D

1 2

X2 24.576MHz_16P_1BG24576CKIA~D

TPBIAS0

1 2

CBS_CCLK

4

C823

1 2

12P_0402_50V8J~D

TPA0+

TPA0­TPB0+

TPB0-

3

+5V_RUN +3.3V_RUN

1

1

C790

CLK_PCI_PCM
PCI_PERR#
PCI_SERR#
PCI_RST#
CLKRUN#
PCI_PIRQD#

56.2_0402_1%~D

R607

C807

1U_0603_10V4Z~D

+CBS_VCC +CBS_VCC

56.2_0402_1%~D

12

12

2

1

R609

R608

5.11K_0402_1%~D
R613

1

C809

2

0.1U_0402_16V4Z~D

2
7
8

10

6
3
9

19

1

20

56.2_0402_1%~D

12

12

C805

1

1 2

2

CBS_CAD0
CBS_CAD1
CBS_CAD3
CBS_CAD5
CBS_CAD7
CBS_CC/BE0#

CBS_CAD9
CBS_CAD11
CBS_CAD12

CBS_CAD14
CBS_CC/BE1#
CBS_CPAR

CBS_CPERR#
CBS_CGNT#
CBS_CINT#

CBS_CCLK
CBS_CIRDY#
CBS_CC/BE2#
CBS_CAD18
CBS_CAD20

CBS_CAD21
CBS_CAD22
CBS_CAD23
CBS_CAD24

CBS_CAD25
CBS_CAD26
CBS_CAD27

CBS_CAD29
CBS_RSVD/D2
CBS_CCLKRUN#

U41

CLK
PERR#
SERR#
RST#
CLKRUN#
INTA#
SKT_LED

1.8VOUT
EPSI

GND

OZ2532SN_SSOP20~D

R642

56.2_0402_1%~D

270P_0402_50V7K~D

C791

2

2

+3.3V
+3.3V

0.1U_0402_16V4Z~D

16

+5V

15

+5V

18
17

5
4

USBP6-

14

CBS_CAD15

13

USBP6+

12

CBS_CAD13

11

R604

0_0402_5%~D

1 2

R606

0_0402_5%~D

1 2

L61 DLW 21SN121SQ2_0805~D@

4

4

1

1

4

4

1

1

L62 DLW 21SN121SQ2_0805~D@

R611

0_0402_5%~D

1 2

R612

0_0402_5%~D

1 2

4.7U_0603_6.3V4Z~D

VCC/VPP
VCC/VPP

USB_A0
USB_B0
USB_A1
USB_B1

Layout Note: Place close to 1394 connector

JCBUS

1

GND1

2

A_CAD0

3

A_CAD1

4

A_CAD3

5

A_CAD5

6

A_CAD7

7

A_PCI_C/BE0#

8

GND2

9

A_CAD9

10

A_CAD11

11

A_CAD12

12

GND3

13

A_CAD14

14

A_PCI_C/BE1#

15

A_CPAR

16

GND4

17

A_CPERR#

18

A_CGNT#

19

A_CINT#

20

+AVCC0

21

+AVPP0

22

A_CCLK

23

A_CIRDY

24

A_PCI_C/BE2#

25

A_CAD18

26

A_CAD20

27

GND5

28

A_CAD21

29

A_CAD22

30

A_CAD23

31

A_CAD24

32

GND6

33

A_CAD25

34

A_CAD26

35

A_CAD27

36

GND7

37

A_CAD29

38

CB_A_D2

39

A_CCLKRUN#

40

GND8

TYCO_1734648-1~D

C792

3

2
3

2

GND9

A_CCD1#

A_CAD2
A_CAD4
A_CAD6

CB_A_D14

A_CAD8

GND10

A_CAD10

A_CVS1

A_CAD13

GND11
A_CAD15
A_CAD16

CB_A_A18

GND12

A_CBLOCK#

A_CSTOP#

A_CDEVSEL#

+AVCC1
+AVPP1

A_CTRDY#

A_CFRAME#

A_CAD17
A_CAD19

A_CVS2

GND13
A_CRST#

A_CSERR#

A_CREQ#

A_PCI_C/BE3#

GND14

A_CAUDIO

A_CSTSCHG

A_CAD28

GND15
A_CAD30
A_CAD31
A_CCD2#

GND16

0.1U_0402_16V4Z~D

2

1

2

3

2
3

2

1

2

4.7U_0603_6.3V4Z~D

+CBS_VCC

41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80

C793

USBP6- 23
USBP6+ 23

TPA0_D+

TPA0_D­TPB0_D+

TPB0_D-

CBS_CCD1#
CBS_CAD2
CBS_CAD4
CBS_CAD6
CBS_RSVD/D14
CBS_CAD8

CBS_CAD10
CBS_CVS1
CBS_CAD13

CBS_CAD15
CBS_CAD16
CBS_RSVD/A18

CBS_CBLOCK#
CBS_CSTOP#
CBS_CDEVSEL#

CBS_CTRDY#
CBS_CFRAME#
CBS_CAD17
CBS_CAD19
CBS_CVS2

CBS_CRST#
CBS_CSERR#
CBS_CREQ#
CBS_CC/BE3#

CBS_CSTSCHNG
CBS_CAD28

CBS_CAD30
CBS_CAD31
CBS_CCD2#

J1394

4

TPA+

3

TPA-

2

TPB+

1

TPB-

1

5

GND

6

GND

7

GND

8

GND

TYCO_2-1775815-2~D

1

C810

2

0.1U_0402_16V4Z~D

DELL CONFIDENTIAL/PROPRIETARY

Title

Cardbus and 1394 OZ711EZ1 Controller

Size Document Number Rev

3

Date: Sheet

Compal Electronics, Inc.

LA-3301P

2

30 58Monday, February 26, 2007

of

1

1.0

8

7

6

5

4

3

2

1

D D

TYPE A (5V), B (3V), AB (5V/3V)
& USB SMARTCARDS ARE SUPPORTED.

USB SMARTCARD READER.

+5V_RUN

1

1

C428

C443

2

2

+3.3V_RUN

12

R252

R296

1.5K_0402_1%~D

USBP4­USBP4+

PCI_RST#21,30,35

CLK_SMC_48M6

12

15K_0402_5%~D

C C

USBP4-23

USBP4+23
SC_USBP-25
SC_USBP+25

T40PAD~D
T41PAD~D

12

R255

15K_0402_5%~D

12

12

R251

R264

15K_0402_5%~D

15K_0402_5%~D

4.7U_0603_6.3V4Z~D

PCI_RST#

CLK_SMC_48M

R259

4.7K_0402_5%~D

+3.3V_RUN

1

1

C441

C435

2

2

0.1U_0402_16V4Z~D

12

U26

8
5

28
17

16
19
18

12
14

15

3
4

MD0

32

1
2

4.7U_0603_6.3V4Z~D

3.3VCC
VCC5V_IN0

VCC5V_IN1
UPD-

UPD+
DPD­DPD+

RST#
RFIO0

RFIO1
XI/48M_IN

XO
MODE0/LED#

MODE1
MODE2

0.1U_0402_16V4Z~D

VR_CPR0
VR_CPR1

3V_CPR

EGATED-

EGATED+

SC_VCC

SC_RST#

SC_CLK

SC_C4

SC_IO

SC_DET#

NC1
NC2
NC3

GND0
GND1
GND2

OZ77CR6LN_QFN32~D

C425

1U_0603_10V4Z~D

6

1 2
10
29

1 2

C305 1U_0603_10V4Z~D

21
20

27
24
23
22
25
13

7
30
31

9
11
26

1

1

C442

SCCD­SCCD+

+SC_PWR
SC_RST#
SC_CLK
SC_C4 SCCD+
SC_IO
SC_DET#

0.1U_0402_16V4Z~D

C446

2

2

4.7U_0603_6.3V4Z~D

SC_DET# 38

R125 220_0402_5%~D
R126 33_0402_5%~D
R260 220_0402_5%~D

R130 220_0402_5%~D

1

12

R263

2

10K_0402_5%~D

12
12
12

12

C448

R256

0.1U_0402_16V4Z~D

12

12

R257

15K_0402_5%~D

15K_0402_5%~D

1

12

C129

R129

2

1U_0603_10V4Z~D

+SC_PWR

47K_0402_5%~D

SCCD-

1

C91

2

0.1U_0402_16V4Z~D

JSC

12

GND

11

GND

10

10

9

9

8

8

7

7

6

6

5

5

4

4

3

3

2

2

1

1

MOLEX_52207-1085~D

B B

Place closely pin 3

CLK_SMC_48M

12

@

R258

10_0402_5%~D

@

1

C432

4.7P_0402_50V8C~D

A A

2

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

8

7

6

5

4

3

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.
Smart Card OZ77CR6

LA-3301P

2

31 58Monday, February 26, 2007

1

1.0

of

5

FUSE4

@

D D

+5V_ALW

1

C169

0.1U_0402_16V4Z~D

C C

0.1U_0402_16V4Z~D

C2

2

+5V_ALW

1

2

@

PAD-OPEN1x1m

1 2

USB_BACK_EN#38

1

C170
10U_0805_10V4Z~D

@

2

@

@

PAD-OPEN1x1m

1 2

USB_SIDE_EN#38

1

C1
10U_0805_10V4Z~D

@

2

L0603

1 2

FUSE1
LF453

1 2

PJP4

FUSE5
L0603

1 2

FUSE2
LF453

1 2

PJP3

USB_BACK_EN#

USB_SIDE_EN#

U4

1

GND

2

IN

3

EN1#

4

EN2#

TPS2062DR_SO8~D

U1

1

GND

2

IN

3

EN1#

4

EN2#

TPS2062DR_SO8~D

4

OC1#
OUT1
OUT2
OC2#

OC1#
OUT1
OUT2
OC2#

+USB_BACK_PWR

8
7
6
5

+USB_SIDE_PWR

8
7
6
5

USB_OC2_3#

USB_OC0_1#

USB_OC2_3# 23

USB_OC0_1# 23

3

+USB_SIDE_PWR

1

C3

2

0.1U_0402_16V4Z~D

USBP0+

USBP1-

USBP0­USBP0+

USBP1­USBP1+
BREATH_GREEN_LED
BATT_GREEN_LED
BATT_AMBER_LED
R_BT_ACT
R_MPCI_ACT

U2

@

1

D1+

2

GND

3

D2-

IP4220CZ6_SO6~D

D2+

VCC

D1-

USBP0-23
USBP0+23

USBP1-23

USBP1+23
BREATH_GREEN_LED43
BATT_GREEN_LED43
BATT_AMBER_LED43
R_BT_ACT43
R_MPCI_ACT43

AUD_INT_MIC+27
AUD_INT_MIC-27

2

JIO

112
334
556
778
9910

11

12

11

13

14

13
151516
171718
191920
212122
232324
252526

27

27

28

29

29

30

31

GND

GND

32

GND

GND

33

GND

GND

TYCO_3-1775014-0~D

+USB_SIDE_PWR +USB_BACK_PWR

USBP1+

4
5

USBP0-

6

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30

34
35
36

LAN_ACTLED_YEL_R#
SW_LAN_TX0+

SW_LAN_TX0­SW_LAN_TX1+
SW_LAN_TX1-

SW_LAN_TX2+
SW_LAN_TX2­SW_LAN_TX3+
SW_LAN_TX3-

LED_10_GRN_R#
LED_100_ORG_R#
HDD_LED

+3.3V_LAN

+2.5V_LAN

USBP3-

USBP2+

LAN_ACTLED_YEL_R# 29

LED_10_GRN_R# 29
LED_100_ORG_R# 29
HDD_LED 43

U16

@

1

D1+

2

GND

3

D2-

IP4220CZ6_SO6~D

SW_LAN_TX0+ 29
SW_LAN_TX0- 29
SW_LAN_TX1+ 29
SW_LAN_TX1- 29

SW_LAN_TX2+ 29
SW_LAN_TX2- 29
SW_LAN_TX3+ 29
SW_LAN_TX3- 29

VCC

1

USBP2-

4

D2+

5

USBP3+

6

D1-

Place ESD diodes as close as USB connector.

B B

USBP2-23

USBP2+23

USBP3-23

USBP3+23

A A

L12 DLW21SN900SQ2_0805~D@

4

1

4

1

4

1

1 2

1 2

L13 DLW 21SN900SQ2_0805~D@

4

1

1 2

1 2

3

3

2

2

R149

0_0402_5%~D

R147

0_0402_5%~D

3

3

2

2

R148

0_0402_5%~D

R150

0_0402_5%~D

USBP2_D-

USBP2_D+

USBP3_D-

USBP3_D+

USB Port

+USB_BACK_PWR

1

+

C168

2

150U_D2_6.3VM~D

1

C9

2

USBP3_D-

0.1U_0402_16V4Z~D

C8

0.1U_0402_16V4Z~D

USBP3_D+

USBP2_D­USBP2_D+

1

2

JUSB1

1

A_VCC

2

A_D-

3

A_D+

4

A_GND

5

B_VCC

6

B_D-

7

B_D+

8

B_GND

9

G1

10

G2

11

G3

12

G4

FOX_UB9112C-SB201-4F~D

Rear USB Ports

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.
USB 2.0 Port

LA-3301P

32 58Monday, February 26, 2007

1

1.0

of

5

D D

C C

4

ICH_AZ_MDC_RST#22

+5V_SUS

MDC_RST_DIS#18

12

R239
10K_0402_5%~D

3

@

0_0402_5%~D

1 2

1 3

R235

D

S

Q31
BSS138W-7-F_SOT323~D

G

2

ICH_RST_MDC_R#

12

R233
100K_0402_5%~D

2

1

New MDC connector.

1

GND

3

IAC_SDATA0

5

GND

7

IAC_SYNC

9

IAC_SDATAIN

11 12

IAC_RESET#

IAC_BITCLK

RES
RES

3.3V
GND
GND

2
4
6
8
10

B B

JMDC

1

ICH_AZ_MDC_SDOUT22
ICH_AZ_MDC_SYNC22

1 2

ICH_AZ_MDC_SDIN122

A A

R128

33_0402_5%~D

ICH_AZ_MDC_SDOUT
ICH_AZ_MDC_SYNC

MDC_SDIN
ICH_RST_MDC_R#

GND1

3

IAC_SDATA_OUT

5

GND2

7

IAC_SYNC

9

IAC_SDATA_IN

11

IAC_RESET#

GND13GND14GND15GND16GND17GND

2

RES0

4

RES1

6

3.3V

8

GND3

10

GND4

12

IAC_BITCLK

TYCO_1-1775149-2~D

18

Connector for MDC Rev1.5

W=20 mil

ICH_AZ_MDC_BITCLK

+3.3V_SUS

1

C126

2

4.7U_0603_6.3V4Z~D

ICH_AZ_MDC_BITCLK22

1

C125

2

0.1U_0402_16V4Z~D

ICH_AZ_MDC_SDOUT
ICH_AZ_MDC_BITCLK

C128

10P_0402_50V8J~D

R123

R124

1 2

1 2

10_0402_5%~D

10_0402_5%~D@

MDC_AC_BITCLK_TERM

ICH_AC_SDOUT_MDCTERM

1

1

C127
10P_0402_50V8J~D

2

2

@

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.
BT PORT and MDC

LA-3301P

33 58Monday, February 26, 2007

1

1.0

of

5

4

3

2

1

L8 DLW21SN900SQ2_0805~D

WLAN_RADIO_DIS#_R

21

WLAN_3V_ENABLE39

1

4

1

4

1 2

1 2

USBP9-23

USBP9+23

D D

R18

@

1 2

0_0402_5%~D

WLAN_RADIO_DIS#38

JCLIP2

1

GND1

2

GND2

3

GND3

4

GND4

TYCO_1775837-1~D

C C

D1
RB751S40T1_SOD523-2~D

2

@

2

3

3

R120

0_0402_5%~D

R121

0_0402_5%~D

2N7002W-7-F_SOT323-3~D

R786

100K_0402_5%~D

12

+PWR_SRC

R785

Q96

2

G

Mini-Card Latch

SB_WLAN_PCIE_RST#21

SB_WLAN_PCIE_RST#

Mini WLAN

+3.3V_WLAN

PCIE_WAKE#28,38
COEX2_WLAN_ACTIVE40
COEX1_BT_ACTIVE40

MINI2CLK_REQ#6
CLK_PCIE_MINI2#6

CLK_PCIE_MINI26

HOST_DEBUG_RX39

8051_TX39

PCIE_IRX_WLANTX_N223
PCIE_IRX_WLANTX_P223

B B

A A

PCIE_ITX_WLANRX_N2_C23
PCIE_ITX_WLANRX_P2_C23

PCIE_MCARD1_DET#23

+1.5V_RUN

1

C34

2

0.047U_0402_16V4Z~D

+3.3V_RUN

1

C15

2

0.047U_0402_16V4Z~D

R91 0_0402_5%~D

1 2

R27 0_0402_5%~D

1 2

HOST_DEBUG_RX
8051_TX

PCIE_IRX_WLANTX_N2
PCIE_IRX_WLANTX_P2

PCIE_ITX_WLANRX_N2_C
PCIE_ITX_WLANRX_P2_C

1 2

R548

100K_0402_5%~D

+3.3V_WLAN

1

1

@

C16

2

2

0.1U_0402_16V4Z~D

5

1

C41

2

0.047U_0402_16V4Z~D

C166

0.047U_0402_16V4Z~D

JMINI2

1

1

3

3

5

5

7

7

9

9

11

11

13

13

15

15

17

17

19

19

21

21

23

23

25

25

27

27

29

29

31

31

33

33

35

35

37

37

39

39

41

41

43

43

45

45

47

47

49

49

51

51

53

GND1

TYCO_1775838-1~D

1

C36

2

+3.3V_WLAN

2

2

4

4

6

6

8

8

10

10

12

12

14

14

16

16

18

18

20

20

22

22

24

24

26

26

28

28

30

30

32

32

34

34

36

36

38

38

40

40

42

42

44

44

46

46

48

48

50

50

52

52

54

GND2

1

C164

2

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

12

100K_0402_5%~D

13

D

S

@

0_0402_5%~D

+1.5V_RUN

WLAN_PLTRST3#_R

1

C163

2

4.7U_0603_6.3V4Z~D

4

USBP9_D-

USBP9_D+

+3.3V_ALW

12

R784

100K_0402_5%~D

13

D

2

Q95

G

S

12

R783

200K_0402_5%~D

R599

12

HOST_DEBUG_TX
WLAN_RADIO_DIS#_R

0_0402_5%~D

WLAN_SMBCLK
WLAN_SMBDATA

R549 100K_0402_5%~D

1 2

8051_RX
LED_WLAN_OUT#

1 2

R11 0_0402_5%~D@

R640

WLAN_SMBCLK

WLAN_SMBDATA

1

+

C283
330U_D2E_6.3VM_R25~D

2

6
2

1

2N7002W-7-F_SOT323-3~D

R600

12

2.2K_0402_5%~D

D

G

12

R645

2.2K_0402_5%~D

+3.3V_WLAN

S

45

Q94

SI3456BDV-T1-E3_TSOP6~D

3

1

12

PLTRST3#

C270
4700P_0402_25V7K~D

R782

2

470K_0402_5%~D

HOST_DEBUG_TX 39

PLTRST3# 21,28

+3.3V_RUN

USB_MCARD1_DET# 23

8051_RX 39
LED_WLAN_OUT# 43
BT_ACTIVE 40,43

+3.3V_WLAN

12

G

2

S

1 2

0_0402_5%~D @

G

2

13

D

S

Q46

@

2N7002W-7-F_SOT323-3~D

1 2

@

0_0402_5%~D

Q45

@

2N7002W-7-F_SOT323-3~D

13

D

R660

R662

JCLIP1

1

GND1

2

GND2

3

GND3

4

GND4

TYCO_1775837-1~D

Mini-Card Latch

PCIE_IRX_WANTX_N1
PCIE_IRX_WANTX_P1

PCIE_ITX_WANRX_N1_C
PCIE_ITX_WANRX_P1_C

PCIE_MCARD2_DET#

1 2

R550 100K_0402_5%~D

+SIM_PWR

1

C459

2

1U_0603_10V4Z~D

PCIE_WAKE#

MINI1CLK_REQ#
CLK_PCIE_MINI1#

CLK_PCIE_MINI1

JSIM

1

VCC

2

RST

3

CLK

7

NC

SUYIN_254020MA006G502ZL~D

PWR
Rail

+3.3V

+3.3Vaux

+1.5V

PCIE_WAKE#28,38

MINI1CLK_REQ#6
CLK_PCIE_MINI1#6

CLK_PCIE_MINI16

PCIE_IRX_WANTX_N123
PCIE_IRX_WANTX_P123

PCIE_ITX_WANRX_N1_C23
PCIE_ITX_WANRX_P1_C23

PCIE_MCARD2_DET#21

+3.3V_RUN

UIM_RESET
UIM_CLK

ICH_SMBCLK 23,28

CLK_SCLK 6

ICH_SMBDATA 23,28

CLK_SDATA 6

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

SB_WWAN_PCIE_RST#21

Mini WWAN

GND

VPP

I/O
NC

+3.3V_RUN

1

C449

2

0.047U_0402_16V4Z~D

Voltage
Tolerance

+-9%

+-9%

+-5%

JMINI1

1

1

3

3

5

5

7

7

9

9

11

11

13

13

15

15

17

17

19

19

21

21

23

23

25

25

27

27

29

29

31

31

33

33

35

35

37

37

39

39

41

41

43

43

45

45

47

47

49

49

51

51

53

GND1

TYCO_1775838-1~D

4
5
6

8

1

C416

2

0.047U_0402_16V4Z~D

SB_WWAN_PCIE_RST#

+3.3V_RUN+3. 3 V _RUN

2

2

4

4

6

6

8

8

10

10

12

12

14

14

16

16

18

18

20

20

22

22

24

24

26

26

28

28

30

30

32

32

34

34

36

36

38

38

40

40

42

42

44

44

46

46

48

48

50

50

52

52

54

GND2

UIM_VPP
UIM_DATA

1

1

2

C444

2

33P_0402_50V8J~D

Primary Power Aux Power

Peak Normal Normal

1000 750

330

500

2

0_0402_5%~D

UIM_DATA
UIM_CLK
UIM_RESET
UIM_VPP

WWAN_RADIO_DIS#
PLTRST3#_R

+3.3V_RUN

ICH_SMBCLK
ICH_SMBDATA

USBP9_D­USBP9_D+

T16 PAD~D

UIM_RESET

UIM_CLK

1

C123

C124

2

33P_0402_50V8J~D

1

C111

C773

2

33P_0402_50V8J~D

22U_0805_6.3VAM~D

250 (Wake enable)

250

5 (Not wake enable)

375

NA

R598

@

12

+1.5V_RUN
+SIM_PWR

R597

33P_0402_50V8J~D

1

2

3

1

2

1

+

C445

2

330U_D2E_6.3VM_R25~D

0_0402_5%~D

12

R574
100K_0402_5%~D

U53

SRV05-4.TCT_SOT23-6~D

12

6

5

4

PLTRST3#

+3.3V_RUN

UIM_VPP

UIM_DATA

1

C460

2

WWAN_RADIO_DIS# 38
PLTRST3# 21,28

ICH_SMBCLK 23,28
ICH_SMBDATA 23,28

USB_MCARD2_DET# 23

+SIM_PWR

1

C122

2

33P_0402_50V8J~D

33P_0402_50V8J~D

+1.5V_RUN

C121

33P_0402_50V8J~D

DELL CONFIDENTIAL/PROPRIETARY

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

Mini Card

LA-3301P

34 58Monday, February 26, 2007

1

of

1

1

C120

2

2

0.047U_0402_16V4Z~D

1.0

5

4

3

2

1

+5V_RUN

D D

C C

PCI_AD[0..31]21,30

B B

A A

PCI_PIRQA#21

PCI_RST#21,30,31
PCI_C_BE3#21,30

PCI_C_BE2#21,30
PCI_C_BE1#21,30
PCI_C_BE0#21,30
PCI_IRDY#21,30,36
PCI_FRAME#21,30,36

PCI_TRDY#21,30
PCI_STOP#21,30
PCI_PLOCK#21
PCI_DEVSEL#21,30
PCI_PERR#21,30
PCI_SERR#21,30
PCI_PAR21,30

D2

RB751S40T1_SOD523-2~D

2 1

PCI_GNT0#21,36
SYS_PME#30,38

+VCC_QBUFD

QUIETE#

PCI_AD31
PCI_AD30
PCI_AD29
PCI_AD28
PCI_AD27
PCI_AD26
PCI_AD25
PCI_AD24

PCI_AD23
PCI_AD22
PCI_AD21
PCI_AD20
PCI_AD19
PCI_AD18
PCI_AD17
PCI_AD16

PCI_AD15
PCI_AD14
PCI_AD13
PCI_AD12
PCI_AD11
PCI_AD10
PCI_AD8
PCI_AD9

PCI_AD7
PCI_AD6
PCI_AD5
PCI_AD4
PCI_AD3
PCI_AD2
PCI_AD1
PCI_AD0

QUIETE#

PCI_PIRQA#
PCI_GNT0#
PCI_RST#
SYS_PME#
PCI_C_BE3#
PCI_C_BE2#
PCI_C_BE1#
PCI_C_BE0#
PCI_IRDY#
PCI_FRAME#

PCI_TRDY#
PCI_STOP#
PCI_PLOCK#
PCI_DEVSEL#
PCI_PERR#
PCI_SERR#
PCI_PAR
PCI_AD24

D3

RB751S40T1_SOD523-2~D

2 1

1K_0402_5%~D

U19

1

NC1

2

A1

3

A2

4

A3

5

A4

6

A5

7

A6

8

A7

9

A8

10

GND1

11

NC2

12

A9

13

A10

14

A11

15

A12

16

A13

17

A14

18

A15

19

A16

20

GND2

21

NC3

22

A17

23

A18

24

A19

25

A20

26

A21

27

A22

28

A23

29

A24

30

GND3

31

NC4

32

A25

33

A26

34

A27

35

A28

36

A29

37

A30

38

A31

39

A32

40

GND4

PI5C34X2245BE_BQSOP80~D

U18

47

OE1
OE235VCC2

2

A0

3

A1

4

A2

5

A3

6

A4

7

A5

8

A6

9

A7

10

A8

11

A9

14

A10

15

A11

16

A12

17

A13

18

A14

19

A15

20

A16

21

A17

22

A18

23

A19

1

NC1

13

NC2

PI5C162861BE_BQSOP48~D

+VCC_QBUF

12

R19

80

VCC4

79

OE1#

78

B1

77

B2

76

B3

75

B4

74

B5

73

B6

72

B7

71

B8

70

VCC3

69

OE2#

68

B9

67

B10

66

B11

65

B12

64

B13

63

B14

62

B15

61

B16

60

VCC2

59

OE3#

58

B17

57

B18

56

B19

55

B20

54

B21

53

B22

52

B23

51

B24

50

VCC1

49

OE4#

48

B25

47

B26

46

B27

45

B28

44

B29

43

B30

42

B31

41

B32

36

VCC1

48
46

B0

45

B1

44

B2

43

B3

42

B4

41

B5

40

B6

39

B7

38

B8

37

B9

34

B10

33

B11

32

B12

31

B13

30

B14

29

B15

28

B16

27

B17

26

B18

25

B19

12

GND1

24

GND2

1

C28

2

0.1U_0402_16V4Z~D

C29

0.1U_0402_16V4Z~D

1 2

DOCK_AD31
DOCK_AD30
DOCK_AD29
DOCK_AD28
DOCK_AD27
DOCK_AD26
DOCK_AD25
DOCK_AD24

DOCK_AD23
DOCK_AD22
DOCK_AD21
DOCK_AD20
DOCK_AD19
DOCK_AD18
DOCK_AD17
DOCK_AD16

DOCK_AD15
DOCK_AD14
DOCK_AD13
DOCK_AD12
DOCK_AD11
DOCK_AD10
DOCK_AD8
DOCK_AD9

DOCK_AD7
DOCK_AD6
DOCK_AD5
DOCK_AD4
DOCK_AD3
DOCK_AD2
DOCK_AD1
DOCK_AD0

C31

0.047U_0402_16V4Z~D

1 2

C26

0.1U_0402_16V4Z~D

1 2

DOCK_PIRQA#
DOCK_GNT0#
DOCK_PCIRST#
DOCK_SPME#
DOCK_C_BE3#
DOCK_C_BE2#
DOCK_C_BE1#
DOCK_C_BE0#
DOCK_IRDY#
DOCK_FRAME#

DOCK_TRDY#
DOCK_STOP#
DOCK_LOCK#
DOCK_DEVSEL#
DOCK_PERR#
DOCK_SERR#
DOCK_PAR
DOCK_PCI_IDSEL

1

1

C33

C32

2

2

0.1U_0402_16V4Z~D

0.047U_0402_16V4Z~D

DOCK_AD[0..31] 36

+3.3V_RUN

1

C35

4

0.1U_0402_16V4Z~D

2

QUIETE#

DOCK_PIRQA# 36
DOCK_GNT0# 36
DOCK_PCIRST# 36
DOCK_SPME# 36
DOCK_C_BE3# 36
DOCK_C_BE2# 36
DOCK_C_BE1# 36
DOCK_C_BE0# 36
DOCK_IRDY# 36
DOCK_FRAME# 36

DOCK_TRDY# 36
DOCK_STOP# 36
DOCK_LOCK# 36
DOCK_DEVSEL# 36
DOCK_PERR# 36
DOCK_SERR# 36
DOCK_PAR 36
DOCK_PCI_IDSEL 36

R22
100K_0402_5%~D

1 2

DOCK_PCI_EN#36
QBUFEN#38

DOCK_PCI_EN#
QBUFEN#

5

1

P

INB

2

INA

G

3

U5

O

TC7SH32FU_SSOP5~D

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.
DOCKING BUFFER

LA-3301P

35 58Monday, February 26, 2007

1

1.0

of

5

4

3

2

1

+DOCK_PW R_SRC

2

C20

1

0.1U_0603_50V4Z~D

Q6

FDS4435BZ_SO8~D

8
7

1

6

2

5

3

4

12

R17
100K_0402_5%~D

Z3307

13

D

Q2

2

2N7002W-7-F_SOT323-3~D

G

S

DOCK_AD0
DOCK_AD1
DOCK_AD2
DOCK_AD3
DOCK_AD4
DOCK_AD5
DOCK_AD6
DOCK_AD7
DOCK_AD8
DOCK_AD9
DOCK_AD10
DOCK_AD11
DOCK_AD12
DOCK_AD13
DOCK_AD14
DOCK_AD15
DOCK_AD16
DOCK_AD17
DOCK_AD18
DOCK_AD19
DOCK_AD20
DOCK_AD21
DOCK_AD22
DOCK_AD23
DOCK_AD24
DOCK_AD25
DOCK_AD26
DOCK_AD27
DOCK_AD28
DOCK_AD29
DOCK_AD30
DOCK_AD31

JDOCKC

P1

P1

P2

P2

P3

P3

P4

P4

MH1

MH1

MH5

SHLD1

MH6

SHLD2

MH9

SHLD5

MH10

SHLD6

MH13

MH13

MH15

MH15

TYCO_2-1612415-1~D

+DOCK_PW R_SRC

1

C18
1000P_0402_50V7K~D

2

MH2
SHLD3
SHLD4
SHLD7
SHLD8

MH14
MH16

P5
P6
P7
P8

TV_C
TV_CVBS
TV_Y

P5
P6
P7
P8

MH2
MH7
MH8
MH11
MH12

MH14
MH16

DOCK_AD[0..31] 35

NB

DELL CONFIDENTIAL/PROPRIETARY

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.
DOCKING CONN

DOCK_PWR_EN38

JDOCKB

137

S137

138

S138

139

S139

140

S140

141

S141

142

S142

143

S143

144

S144

145

S145

146

S146

147

S147

148

S148

149

S149

150

S150

151

S151

152

S152

153

S153

154

S154

155

S155

156

S156

157

S157

158

S158

159

S159

160

S160

161

S161

162

S162

163

S163

164

S164

165

S165

166

S166

167

S167

168

S168

169

S169

170

S170

171

S171

172

S172

173

S173

174

S174

175

S175

176

S176

177

S177

178

S178

179

S179

180

S180

181

S181

182

S182

183

S183

184

S184

185

S185

186

S186

187

S187

188

S188

189

S189

190

S190

193

S193

194

S194

195

S195

196

S196

204

M204

TYCO_2-1612415-1~D

2

3

205

S205

206

S206

207

S207

208

S208

209

S209

210

S210

211

S211

212

S212

213

S213

214

S214

215

S215

216

S216

217

S217

218

S218

220

S220

222

S222

223

S223

224

S224

225

S225

226

S226

227

S227

228

S228

229

S229

230

S230

231

S231

232

S232

233

S233

234

S234

235

S235

236

S236

237

S237

238

S238

239

S239

240

S240

241

S241

242

S242

243

S243

244

S244

245

S245

246

S246

247

S247

248

S248

250

S250

252

S252

253

S253

254

S254

255

S255

256

S256

257

S257

258

S258

259

S259

+3.3V_ALW

0.47U_0805_25V7K~D

R4
100K_0402_5%~D

1 2

13

Q3

DDTC144EUA-7-F_SOT323-3~D

DOCK_PWR_EN

HSYNC_R
VSYNC_R

D_LAD0
DOCK_SMB_ALERT#

DOCK_AD2
DOCK_AD5
DOCK_AD6

DOCK_AD12
DOCK_AD13
DOCK_C_BE1#

DOCK_PERR#
DOCK_STOP#
DOCK_TRDY#

DOCK_AD17
DOCK_AD18
DOCK_AD21

DOCK_C_BE3#
DOCK_AD25
DOCK_AD26

PCI_REQ0#
DOCK_PCIRST#

TV_CVBS
TV_Y

R_PIDEACT

+PWR_SRC

2
1

C150

12

0.1U_0402_10V7K~D

AUD_SPDIF_OUT

10P_0402_50V8J~D

2

C11

1

DOCKED 29,38

U13

3

74AHC1G08GW_SOT353-5~D

G

IN2

O

IN1

P

5

1 2

R7

0_0402_5%~D@

DAT_DDC2 12,20

CLK_DDC2 12,20

HSYNC_R 20

VSYNC_R 20

D_CLKRUN# 38

DOCK_SMB_ALERT# 39

DOCK_C_BE1# 35

DOCK_PERR# 35
DOCK_STOP# 35
DOCK_TRDY# 35

DOCK_C_BE3# 35

PCI_REQ0# 21

DOCK_PCIRST# 35

DOCK_LOM_ACTLED_YEL# 29
R_PIDEACT 43

12

R791

@

10_0402_5%~D

1

C267

@

2

R10
200K_0402_5%~D

1 2

G_DOC_PWRSRC

Z3308

4

+3.3V_SUS

R8

1 2

100K_0402_5%~D

2

JDOCKA

1

S1

2

S2

DVI_CLK-51

DVI_CLK+51

DVI_TX4-

D D

DOCK_PSID44

CLK_PCI_DOCK6

DOCK_PIRQA#35

DOCK_SMB_CLK39

DOCK_SMB_DAT39

C C

B B

A A

CLK_DOCK39
DAT_DOCK39

CLK_PCI_DOCK

12

@

R20
10_0402_5%~D

1

@

C25

4.7P_0402_50V8C~D

2

DVI_TX4+

DVI_TX3+
DVI_TX3-

DVI_TX5+
DVI_TX5-

DVI_TX2+51

DVI_TX2-51

DVI_TX1+51

DVI_TX1-51

DVI_TX0+51

DVI_TX0-51

DOCK_AD31

PCI_GNT0#21,35

TV_C12

TV_Y12

TV_CVBS12

CRT_RED12,20

CRT_GRN12,20

CRT_BLU12,20

5

3
4
5
6
7
8

9
10
11
12
13

15
17

18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43

45
47

48
49
50
51
52
53
54
55

PCI_GNT0#

PCI_IRDY#21,30,35

PCI_FRAME#21,30,35

S3
S4
S5
S6
S7
S8
S9
S10
S11
S12
S13

S15
S17

S18
S19
S20
S21
S22
S23
S24
S25
S26
S27
S28
S29
S30
S31
S32
S33
S34
S35
S36
S37
S38
S39
S40
S41
S42
S43

S45
S47

S48
S49
S50
S51
S52
S53
S54
S55

TYCO_2-1612415-1~D

69

S69

70

S70

71

S71

72

S72

73

S73

74

S74

75

S75

76

S76

77

S77

78

S78

79

S79

80

S80

81

S81

82

S82

83

S83

84

S84

85

S85

86

S86

87

S87

88

S88

89

S89

90

S90

91

S91

92

S92

93

S93

94

S94

95

S95

96

S96

97

S97

98

S98

99

S99

100

S100

101

S101

102

S102

103

S103

104

S104

105

S105

106

S106

107

S107

108

S108

109

S109

110

S110

111

S111

112

S112

113

S113

114

S114

115

S115

116

S116

117

S117

118

S118

119

S119

120

S120

121

S121

122

S122

125

S125

126

S126

127

S127

128

S128

136

M136

+3.3V_RUN

1

C37

0.1U_0402_16V4Z~D

2

1

5

P

NC

4

A2Y

G

U6

NC7SZ04P5X_NL_SC70-5~D

3

PCI_IRDY#
PCI_FRAME#

TV_C

TV_Y

TV_CVBS

CRT_RED

CRT_GRN

CRT_BLU

CRT_RED

DOCK_AD8
DOCK_C_BE0#

DOCK_AD14
DOCK_AD15

DOCK_AD19
DOCK_AD20

DOCK_AD27
DOCK_AD28
DOCK_AD30

USBP8­USBP8+

+3.3V_RUN

5

1

IN1

2

IN2

3

D_SERIRQ 38
DOCK_PCI_IDSEL 35

D_DLRQ1# 38 D_LAD0 38
D_LFRAME# 38

DVI_SCLK 51
DVI_SDATA 51
DVI_DETECT 51

DOCK_C_BE0# 35

DOCK_DEVSEL# 35
DOCK_IRDY# 35

DOCK_GNT0# 35

USBP8- 23

USBP8+ 23

DOCK_SMB_PME# 38

CLK_KBD 39
DAT_KBD 39

+2.5V_LAN

0.01U_0402_16V7K~D

0.01U_0402_16V7K~D

DOCK_LAN_TX3- 29
DOCK_LAN_TX3+ 29
DOCK_LAN_TX2- 29
DOCK_LAN_TX2+ 29

DOCK_RING

C23

1 2

C24

1 2

DOCK_LOM_SPD10LED_GRN#29
DOCK_LOM_SPD100LED_ORG#29

D_LAD138
D_LAD238
D_LAD338

DOCK_PAR35
DOCK_SERR#35
DOCK_LOCK#35

DOCK_FRAME#35

DOCK_C_BE2#35

DOCK_SPME#35

DOCK_PCI_EN#35

AUD_SPDIF_OUT26

C21

0.01U_0402_16V7K~D

12

C22

0.01U_0402_16V7K~D

12

DOCK_LAN_TX1-29
DOCK_LAN_TX1+29
DOCK_LAN_TX0-29
DOCK_LAN_TX0+29

PLACE TERMINATIONS CLOSE TO DOCK CONNECTOR

+3.3V_RUN

1

C40

0.1U_0402_16V4Z~D

2

Z3305

C38

1 2

0.1U_0402_16V4Z~D

U7

P

Z3306

4

O

G

74AHC1G08GW_SOT353-5~D

DOCK_RING
DOCK_TIP

4

5

1

P

IN1

2

IN2

G

3

U8

DOCK_OWNS_PCI

4

O

74AHC1G08GW_SOT353-5~D

JWIRE

1

1

2

2

3

3

4

4

MOLEX_53398-0471~D

DOCK_DET# DOCK_DET#
CRT_GRN

CRT_BLU
D_LAD1

D_LAD2
D_LAD3

DOCK_AD1
DOCK_AD0

DOCK_AD3
DOCK_AD4
DOCK_AD7

DOCK_AD9
DOCK_AD10
DOCK_AD11

DOCK_C_BE2#
DOCK_AD16

DOCK_AD22
DOCK_AD23
DOCK_AD24

DOCK_AD29

TV_C

DOCK_OWNS_PCI

DOCK_TIP

+5V_ALW

R16
100K_0402_5%~D

1 2

DOCK_DET#

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

+DC_IN

R12 150_0402_1%~D
R13 150_0402_1%~D
R14 150_0402_1%~D

PWR_SRC

LA-3301P

+DC_IN

2

1

1 2
1 2
1 2

1

1

C14

C13

2

0.1U_0603_50V4Z~D
1000P_0402_50V7K~D

no power dock

self powe r dock

36 58Tuesday, Fe b r u a r y 27, 2007

1.0

of

5

+3.3V_SUS

4

3

2

1

26

VCC

INVALID#

1

C167

0.1U_0402_16V4Z~D

2

27

V+

3

V-

9

T1OUT

10

T2OUT

11

T3OUT

4

R1IN

5

R2IN

6

R3IN

7

R4IN

8

R5IN

21
25

GND

3243V+
3243V-

TXD0#
RTS0
DTR0
DCD0
RI0
RXD0#
CTS0
DSR0

C10

0.47U_0402_10V4Z~D

1 2

C7

0.47U_0402_10V4Z~D

1 2

1

2

+3.3V_ALW

R131

@

100K_0402_5%~D

BC_A_DAT39
BC_A_CLK39
BC_A_INT#39

C175

0.1U_0402_16V4Z~D

12

1

C171

2

0.1U_0402_16V4Z~D

BC_A_DAT
BC_A_CLK
BC_A_INT#

R28

1K_0402_5%~D

+3.3V_ALW

12

30
10

39

37
38

34
35
36

40
41

U39

VCC1
VCC1

NC3

NC1
NC2

BC_DATA
BC_CLK
BC_INT#

TEST_PIN
GND_PAD

ECE1077

ECE1077-FZG_QFN40~D

KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8

KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15

KSO16/GPIO_0
KSO17/GPIO_1
KSO18/GPIO_2
KSO19/GPIO_3
KSO20/GPIO_4
KSO21/GPIO_5
KSO22/GPIO_6

KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7

DCD0
DSR0
RXD0#
RTS0
TXD0#
CTS0
DTR0
RI0

1

1

1

1

C153

C152

2

2

KSO0

9

KSO1

11

KSO2

12

KSO3

13

KSO4

14

KSO5

15

KSO6

16

KSO7

17

KSO8

18

KSO9

19

KSO10

20

KSO11

21

KSO12

22

KSO13

23

KSO14

24

KSO15

25

KSO16

26

KSO17

27
28
29
31
32
33

KSI0

1

KSI1

2

KSI2

3

KSI3

4

KSI4

5

KSI5

6

KSI6

7

KSI7

8

2

270P_0402_50V7K~D

270P_0402_50V7K~D

KSO[0..17] 40

KYBD_DET# 40

KSI[0..7] 40

1

1

C154

C155

C156

2

2

270P_0402_50V7K~D

2

270P_0402_50V7K~D

270P_0402_50V7K~D

1

1

C159

C158

C157

2

2

270P_0402_50V7K~D

270P_0402_50V7K~D

270P_0402_50V7K~D

JSIO

1

DCD0

6

DSR0

2

RXD0#

7

RTS0F

3

TXD0F#

8

CTS0

4

DTR0F

9

RI0

5

GND0

10

GND1

11

GND2

SUYIN_070921MR009S203BR~D

D D

C12

0.1U_0402_10V7K~D

C6

0.1U_0402_10V7K~D

1 2

C C

B B

1 2

TXD038
RTS0#38
DTR0#38
DCD0#38

RI0#38
RXD038
CTS0#38
DSR0#38

+3.3V_SUS

RUN_ON19,39,41,42

3243C1+

3243C1­3243C2+

3243C2­TXD0
RTS0#
DTR0#
DCD0#
RI0#
RXD0
CTS0#
DSR0#

U3

28

C1+

24

C1-

1

C2+

2

C2-

14

T1IN

13

T2IN

12

T3IN

19

R1OUT

18

R2OUT

17

R3OUT

16

R4OUT

15

R5OUT

20

R2OUTB

23

FORCEON

22

FORCEOFF#

MAX3243ECUI+T_TSSOP28~D

A A

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

Serial & FIR

LA-3301P

37 58Monday, February 26, 2007

1

1.0

of

5

4

3

2

1

+3.3V_ALW

@

@

R220

12

12

1

2

ITP_DBRESET#7,23

12

SYS_PME#

PCIE_WAKE#

IMVP6_PROCHOT#

PANEL_BKEN

10K_0402_5%~D

RI0#37

R250

1 2

R806 0_0402_5%~D@

+3.3V_ALW

+3.3V_SUS

12

5V_3V_1.8V_1.25V_RUN_PWRGD42

+5V_ALW

R245 10K_0402_5%~D

USB_BACK_EN#32

WIRELESS_ON/OFF#43

DOCK_PWR_EN36
ADAPT_TRIP_SET49

PSID_DISABLE#44

DOCK_SMB_PME#36

AUD_SPDIF_SHDN26

DOCK_HP_MUTE#26

AUD_HP_NB_SENSE26,27

IMVP6_PROCHOT#48

LOM_LOW_PWR28

SIO_EXT_WAKE#23

ICH_PCIE_W AKE#23

WLAN_RADIO_DIS#34

WWAN_RADIO_DIS#34

LOM_CABLE_DETECT28

LOM_SUPER_IDDQ28

1 2

PBAT_PRES#44
SBAT_PRES#44,50

CHG_PBATT50
CHG_SBATT50

PBAT_DSCHG50

SYS_PME#30,35

PCIE_WAKE#28,34

BT_RADIO_DIS#40

BC_INT#39

BC_DAT39

BC_CLK39

USB_SIDE_EN#32

QBUFEN#35

ADAPT_OC49

PANEL_BKEN12

DOCKED29,36

NB_MUTE#27

1.05V_RUN_ON47

MODPRES#25

HDDC_EN25
MODC_EN25

SC_DET#31

LED_MASK#43

ICH_PME#21

LOM_TPM_EN#28

ATF_INT#18

DOCK_SMB_PME#

PBAT_PRES#
SBAT_PRES#
CHG_PBATT
CHG_SBATT

SYS_PME#
PCIE_WAKE#
USB_BACK_EN#

WIRELESS_ON/OFF#
BT_RADIO_DIS#

BC_INT#
BC_DAT
BC_CLK

RXD037

TXD037

RTS0#37

DSR0#37

CTS0#37

DTR0#37

DCD0#37

RXD0
TXD0
RTS0#
DSR0#
CTS0#
DTR0#
RI0#
DCD0#

USB_SIDE_EN#
QBUFEN#

DOCK_PWR_EN
ADAPT_OC
ADAPT_TRIP_SET
ITP_DBRESET#_R
PSID_DISABLE#
PANEL_BKEN
DOCKED
DOCK_SMB_PME#
NB_MUTE#

AUD_SPDIF_SHDN
DOCK_HP_MUTE#
AUD_HP_NB_ SENSE

LID_CL_SIO#

1.05V_RUN_ON

MODPRES#
HDDC_EN

MODC_EN

LOM_LOW_PWR
LED_MASK#

R242 0_0402_5%~D

1 2

ICH_PME#
ICH_PCIE_W AKE#
WLAN_RADIO_DIS#

WWAN_RADIO_DIS#

1 2

R308 0_0402_5%~D

LOM_TPM_EN#
LOM_SUPER_IDDQ
VGA_IDENTIFY
CHIPSET_ID

R112

10K_0402_5%~D

BID1
BID0
ATF_INT#

U25

97

GPIOA[0]

98

GPIOA[1]

99

GPIOA[2]

100

GPIOA[3]

101

GPIOA[4]

102

GPIOA[5]

103

GPIOA[6]

104

GPIOA[7]

24

GPIOH[0]

25

GPIOH[1]

26

GPIOH[4]

27

GPIOH[5]

58

BC_INT#

59

BC_DAT

60

BC_CLK

1

GPIOE[0]/RXD

2

GPIOE[1]/TXD

3

GPIOE[2]/RTS#

4

GPIOE[3]/DSR#

5

GPIOE[4]/CTS#

84

GPIOE[5]/DTR#

83

GPIOE[6]/RI#

6

GPIOE[7]/DCD#

65

GPIOB[0]/INIT#

66

GPIOB[1]/SLCTIN#

67

GPIOC[2]/SCLT

68

GPIOC[3]/PE

69

GPIOC[4]/BUSY

70

GPIOC[5]/ACK#

71

GPIOC[6]/ERROR#

73

GPIOC[7]/ALF#

74

GPIOD[0]/STROBE#

75

GPIOC[1]/PD7

76

GPIOC[0]/PD6

77

GPIOB[7]/PD5

78

GPIOB[6]/PD4

79

GPIOB[5]/PD3

80

GPIOB[4]/PD2

81

GPIOB[3]/PD1

82

GPIOB[2]/PD0

61

GPIOD[1]

62

GPIOD[2]

63

GPIOD[3]/VBUS_DET

28

GPIOD[4]/OCS1_N

29

GPIOD[5]/OCS2_N

30

GPIOD[6]/OCS3_N

31

GPIOD[7]/OCS4_N

32

GPIOH[6]

33

GPIOH[7]

88

GPIOG[0]

89

GPIOG[1]

90

GPIOG[2]

91

GPIOG[3]

92

GPIOG[4]

93

GPIOG[5]

94

GPIOG[6]

95

GPIOG[7]

106

SYSOPT1/GPIOH[2]

107

SYSOPT0/GPIOH[3]

109

GPIOF[7]

110

GPIOF[6]

111

GPIOF[5]

112

GPIOF[4]

113

IRTX

12

114

IRRX

115

GPIOF[3]/IRMODE/IRRX3B

116

GPIOF[2]/IRTX2

117

GPIOF[1]/IRRX2

118

GPIOF[0]/IRMODE/IRRX3A

ECE5028-NU_VTQFP128_14X14~D

1 2

R248 10K_0402_5%~D

1 2

R247 10K_0402_5%~D

+3.3V_RUN

D D

Place closely pin 64

C C

B B

1 2

R1 100K_0402_5%~D

R237

100K_0402_5%~D

CLK_SIO_14M

R246

10_0402_5%~D

C415

4.7P_0402_50V8C~D

VGA_IDENTIFY SC_DET#

100K_0402_5%~D

1 = Discrete Gfx
0 = UMA

+3.3V_ALW

34

57

85

108

VCC1

VCC1

VCC1

VCC1

ECE5028-NU

(ECE5018)

USB

GPIO

TEST

CLK

LPC

DLPC

VCC1(VDDA33)

GPIOJ[7](VDDA33)

GPIOK[4](VDDA33)

GPIOI[1](VCC1)

GPIOJ[2](USBDP0)
GPIOJ[3](USBDN0)
GPIOJ[6](USBDP1)
GPIOJ[5](USBDN1)
GPIOK[0](USBDP2)

GPIOK[1](USBDN2)

GPIOK[3](USBDP3)

GPIOK[2](USBDN3)

GPIOK[5](USBDP4)

GPIOK[6](USBDN4)

GPIOI[6](VDDA33PLL)
GPIOI[5](VDDA18PLL)

GPIOI[2](VDD18)

CAP_LDO

GPIOJ[0](RBIAS)

TEST_PIN

GPIOI[7](ATEST)

GPIOI[4](XTAL1/CLKIN)

GPIOI[3](XTAL2)

LAD0
LAD1
LAD2
LAD3

LFRAME#

LRESET#

PCICLK

CLKRUN#

LDRQ0#
LDRQ1#

SER_IRQ

CLKI (14.318 MHz)

VSS

DLAD0
DLAD1
DLAD2
DLAD3

DLFRAME#

DCLK_RUN#

DLDRQ1#

DSER_IRQ

PWRGD

OUT65

GPIOJ[4](VSS)

VSS

GPIOK[7](VSS)

VSS
VSS
VSS
VSS
VSS

GPIOJ[1](VSS)

1

C101

0.1U_0402_16V4Z~D

2

8
14
20

119
9

10
13
12
15
16
19
18
21
22

125
124
120
86
127

TEST_PIN is a No Connect

35

126
123

122

1

2

LPC_LAD0
LPC_LAD1
LPC_LAD2
LPC_LAD3
LPC_LFRAME#
PLTRST2#
CLK_PCI_5018
CLKRUN#
LPC_LDRQ0#
LPC_LDRQ1#
IRQ_SERIRQ

CLK_SIO_14M

D_LAD0
D_LAD1
D_LAD2
D_LAD3
D_LFRAME#
D_CLKRUN#
D_DLRQ1#
D_SERIRQ

RUNPWROK
LCD_TST

C421

4.7U_0603_6.3V4Z~D

54
52
49
47
42
41
56
37
46
44
39

64
96
55

53
50
48
43
38
45
40

7
105

11
17
23
36
51
72
87
121
128

RBIAS

12

R227

@

1 2

R72

@

10K_0402_5%~D

1

C401

2

@

0.1U_0402_16V4Z~D

1

2

Route RBIAS and its
return to pin 128 very
short.

12K_0402_1%~D

1

C97

2

@

4.7U_0603_6.3V4Z~D

1

C420

0.1U_0402_10V7K~D

2

C98

0.1U_0402_16V4Z~D

SIO_VDDA

1

2

REG_EN

LPC_LAD[0..3] 22,28,39

LPC_LFRAME# 22,28,39
PLTRST2# 21,39
CLK_PCI_5018 6

CLKRUN# 23,30,39

LPC_LDRQ0# 22

LPC_LDRQ1# 22

IRQ_SERIRQ 23,28,30,39

CLK_SIO_14M 6

D_LAD0 36

D_LAD1 36

D_LAD2 36

D_LAD3 36

D_LFRAME# 36

D_CLKRUN# 36

D_DLRQ1# 36

D_SERIRQ 36

RUNPWR OK 39,42,48

LCD_TST 19

1

C92

2

@

4.7U_0603_6.3V4Z~D

C90

@

0.1U_0402_16V4Z~D

+3.3V_ALW

12

1

1

C94

2

2

0.1U_0402_16V4Z~D

R221

@

10K_0402_5%~D

C88

@

1

2

0.1U_0402_16V4Z~D

C403

0.1U_0402_16V4Z~D

1

1

C93

2

2

@

4.7U_0603_6.3V4Z~D

+3.3V_ALW

LID_CL_SIO#

1

2

+3.3V_ALW

R814

1 2

0_0603_5%~D

C89

@

4.7U_0603_6.3V4Z~D

D_CLKRUN#
D_SERIRQ
D_DLRQ1#

12

R95
1M_0402_5%~D

R94

10_0402_5%~D

1

C84

0.047U_0402_16V4Z~D

2

C95

0.1U_0402_16V4Z~D

LID_CL#

CLK_PCI_5018

R240

10_0402_5%~D

C402

12
12
12

@

@

R231 100K_0402_5%~D
R232 100K_0402_5%~D
R234 100K_0402_5%~D

12

Place closely pin 56

4.7P_0402_50V8C~D

+3.3V_RUN

LID_CL# 40

12

1

2

R238

R107

A A

R108

BID0
BID1
CHIPSET_ID

@

R106 10K_0402_5%~D

1 2

R109 10K_0402_5%~D

1 2

R236 10K_0402_5%~D

1 2

1 2

1 2

1 2

10K_0402_5%~D

10K_0402_5%~D

10K_0402_5%~D

@

@

REV BID1
X00

X01 0 1
X02 01
X03 1 1
A00 0 0

5

4

BID0

00

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

2

DELL CONFIDENTIAL/PROPRIETARY

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.
ECE5028

LA-3301P

38 58Monday, February 26, 2007

1

of

1.0

5

+3.3V_ALW

SNIFFER_GREEN#

1 2

R77 100K_0402_5%~D@

SNIFFER_YELLOW#

1 2

R104 100K_0402_5%~D@

CKG_SMBDAT

1 2

R105 2.2K_0402_5%~D

CKG_SMBCLK

1 2

R111 2.2K_0402_5%~D

BC_DAT

1 2

D D

C C

B B

R401 100K_0402_5%~D

R795
0_0402_5%~D

+5V_RUN

1 2

R88 4.7K_0402_5%~D

1 2

R87 4.7K_0402_5%~D

1 2

R86 4.7K_0402_5%~D

1 2

R85 4.7K_0402_5%~D

5

5

4

4

3

3

Molex_53261

@

Place closely pin 58

2

2

JDEBUG

1

1

R1752 no stuff when doing
flash recovery

CLK_PCI_5025

R83

10_0402_5%~D

C81

4.7P_0402_50V8C~D

ATI_ Intel_IDENTIFY

12

CLK_KBD

DAT_KBD

CLK_DOCK

DAT_DOCK

+3.3V_ALW

8051_RX

8051_TX

1 2

R101 0_0402_5%~D

12

@

1

2

@

12

12

R395

R100

10K_0402_5%~D

1M_0402_5%~D

12

R90

10K_0402_5%~D

DEBUG_ENABLE#

R387 2.7K_0402_5%~D
R388 1M_0402_5%~D
R389 2.7K_0402_5%~D

1 2

R526 100K_0402_5%~D

1 2

R788 2.7K_0402_5%~D

1 2

R789 2.7K_0402_5%~D@

32 KHz Clock

1.8V_SUS_PWRGD46
EC_CPU_PROCHOT#7

ICH_CL_PWROK10,23

ALW_PWRGD_3V_5V45

SNIFFER_GREEN#43

ICH_EC_S PI_CLK23
ICH_EC_SPI_DIN23
ICH_EC_SPI_DO23

SNIFFER_YELLOW#43

SUS_ON

12
12

RUN_ON

12

DDR_ON
AUX_ON
AC_OFF

CKG_SMBDAT6
CKG_SMBCLK6

ICH_RSMRST#23

DDR_ON46
TP_DET#40

SIO_SLP_S3#23
SIO_SLP_S5#23

3.3V_RUN_ON41
AUX_ON41

SUS_ON41,42
RUN_ON19 , 37,41, 42

AC_OFF44

BC_A_INT#37
BC_A_DAT37
BC_A_CLK37

SIO_A20GATE22

CLK_TP_SIO40
DAT_TP_SIO40
CLK_KBD36
DAT_KBD36
CLK_DOCK36
DAT_DOCK36

8051_RX34

8051_TX34

PLTRST2#21,38

CLK_PCI_50256
LPC_LFRAME#22,28,38
LPC_LAD022,28,38
LPC_LAD122,28,38
LPC_LAD222,28,38
LPC_LAD322,28,38
CLKRUN#23,30,38
IRQ_SERIRQ2 3 , 28,30, 38

SIO_PWRBTN#23

BC_CLK38

BC_DAT38

BC_INT#38

MEC5004_XTAL2

M_ON

CKG_SMBDAT
CKG_SMBCLK
ATI_ Intel_IDENTIFY

3.3V_M_PWRGD

T36PAD~D

1.8V_SUS_PWRGD
EC_CPU_PROCHOT#

ICH_CL_PWROK
ICH_RSMRST#

M_ON

T33PAD~D

SIO_SLP_M#

T34PAD~D

DDR_ON
TP_DET#
ALW_PWRGD_3V _5V
SIO_SLP_S3#
SIO_SLP_S5# LCD_SMBCLK

3.3V_RUN_ON
AUX_ON

SUS_ON

RUN_ON
AC_OFF

1.05V_1.25V_M_PWRGD

T35PAD~D

BC_A_INT#
BC_A_DAT
BC_A_CLK

SIO_A20GATE
SNIFFER_GREEN#

CLK_TP_SIO

DAT_TP_SIO
CLK_KBD
DAT_KBD
CLK_DOCK
DAT_DOCK

PLTRST2#
CLK_PCI_5025
LPC_LFRAME#
LPC_LAD0
LPC_LAD1
LPC_LAD2
LPC_LAD3
CLKRUN#
IRQ_SERIRQ

ICH_EC_ S PI _CLK

ICH_EC_SPI_DIN
ICH_EC_SPI_DO

EC_FLASH_SPI_CLK
EC_FLASH_SPI_DIN
EC_FLASH_SPI_DO

SIO_PWRBTN#

SNIFFER_YELLOW#

BC_CLK
BC_DAT
BC_INT#

MEC5004_XTAL1

R214 0_0402_5%~D

MEC5004_XOSEL

12

R213
10K_0402_5%~D

Same as Laguna

MEC5004_XTAL1

Y1

32.768K_12.5P_1TJS125DJ4A420P~D

MEC5004_XTAL2

C379

33P_0402_50V8J~D

14
23

1

2

1

C385

2

22P_0402_50V8J~D

Net & Part AMT Intel Non-AMT Broacom

3.3V_M_PWRGD
CH_RSMRST#
M_ON

A A

SIO_SLP_M#

1.05V_1.25V_M_PWRGD
R238
LOM_SUPER_IDDQ
LOM_LOW_PWR
LOM_CABLE_DETECT

5

+RTC_CELL

12

4

1 2

R70

0_0402_5%~D

BLM18AG121SN1D_0603~D

1

2

U22

12

KSO17/GPIOA1/AB1H_DATA

13

KSO16/GPIOA0/AB1H_CLK

14

GPIO5/KSO15

15

GPIO4/KSO14

16

KSO13/GPIO18

17

KSO12/OUT8

18

KSO11/GPIOC7

19

KSO10/GPIOC6

20

KSO9/GPIOC5

23

KSO8/GPIOC4

24

KSO7/GPIO3

25

KSO6/GPIO2

27

KSO5/GPIO1

28

KSO4/GPIO0

29

KSO3/GPIOC3

30

KSO2/GPIOC2

31

KSO1/GPIOC1

32

KSO0/GPIOC0

33

KSI7/GPIO19

34

KSI6/GPIO17

35

KSI5/GPIO10

36

KSI4/GPIO9

37

KSI3/GPIO8

38

KSI2/GPIO7/BC_A_INT#

39

KSI1/GPIO6/BC_A_DAT

40

KSI0/SGPIO30/BC_A_CLK

92

SGPIO34/A20M

50

OUT5/KBRST

75

GPIO94/IMCLK

76

GPIO95/IMDAT

77

KCLK

78

KDAT

79

GPIOA6/EMCLK

80

GPIOA7/EMDAT

81

GPIO20/PS2CLK/8051RX

82

GPIO21/PS2DAT/8051TX

57

LRESET#

58

PCICLK

59

LFRAME#

60

LAD0

61

LAD1

62

LAD2

63

LAD3

64

CLKRUN#

56

SER_IRQ

102

HSTCLK

105

HSTDATAIN

107

HSTDATAOUT

103

FLCLK

106

FLDATAIN

108

FLDATAOUT

109

GPIO80

110

GPIO81

87

BC_CLK

86

BC_DAT

85

BC_INT#

122

XTAL1

124

XTAL2

123

XOSEL

L24

Pin15 of 5025
Pin23 of 5025
Pin24 of 5025
Pin25 of 5025
Pin37 of 5025
Pin24 of 5025
NC
NC
NC

4

C75

0.1U_0402_16V4Z~D

AGND

VSS26VSS51VSS74VSS88VSS

125
12

+3.3V_ALW

121

116

VCC0

VCC121VCC144VCC165VCC183VCC1

VR_CAP22VSS_PLL

113

1

C74

2

NC
NC
NC
NC
NC
NC
Refer to UMA
Refer to UMA
Refer to UMA

1

C83

0.1U_0402_16V4Z~D

2

POWER_ SW_IN2#/GPIO23
POWER_ SW_IN1#/GPIO22

POWER_ SW_IN0#

BGPO0/GPIOA5

AB1B_CLK/GPIOA4

AB1B_DATA/GPIOA2

AB1A_CLK

AB1A_DATA

GPIO11/AB2_DATA

GPIO12/AB2_CLK

GPIO13/AB1G_DATA

GPIO14/AB1G_CLK

GPIO87/AB1C_DATA

GPIO86/AB1C_CLK

GPIO85/AB1D_DATA

GPIO84/AB1D_CLK

GPIO93/AB1F_DATA

GPIO92/AB1F_CLK

GPIO91/AB1E_DATA

GPIO90/AB1E_CLK

GPIO82/FAN_TACH3
GPIO16/FAN_TACH2
GPIO15/FAN_TACH1

OUT2/PWM3

OUT9/PWM2
OUT11/PWM1
OUT10/PWM0

nEC_SCI/SPDIN2

SGPIO45/MSDATA/SPDOUT2

SGPIO44/MSCLK/SPCLK2

SGPIO46/SPDIN1

SGPIO47/SPDOUT1

SGPIO31/TIN1/SPCLK1

SYSOPT0/SGPIO32/LPC_TX
SYSOPT1/SGPIO33/LPC_RX

SGPIO36 (SFPI_EN)

GPIO96/TOUT1

OUT7/nSMI
nPWR_LED

nBAT_LED

GPIOA3/WINDMON

GPIO83/32KHZ_OUT

nRESET_OUT/OUT6

VCC_PLL

MEC5025-NU_VTQFP128~D

101

104

C80

12

0.1U_0402_16V4Z~D

1 2

L3

4.7U_0603_6.3V4Z~D
BLM18AG121SN1D_0603~D

3

ALWON

ACAV_IN

SGPIO40
SGPIO41
SGPIO42
SGPIO43

SGPIO35
SGPIO37

nFWP

PWRGD

TEST_PIN

1 2

L6
BLM18AG121SN1D_0603~D

3

1

C79

0.1U_0402_16V4Z~D

2

120
119
126
127
128
118

8
7
6
5
93
94
95
96
111
112
9
10
97
98
99
100

43
42
41

48

R176 0_0402_5%~D

47
46
45

66
55
54
69

RSV_1.25V_GFX_PCIE_ON

68
67

70
71

91
90
89
4

1
2
3

52
11

115
114

84
73
117
49
53
72

1

C76
10U_0805_10V4Z~D

2

ALWON
SNIFFER_PWR_SW#
POWER_SW_IN1#
POWER_SW_IN#
ACAV_IN
SNIFFER_RTC_GPO

LCD_SMBCLK
LCD_SMBDAT
DOCK_SMB_CLK
DOCK_SMB_DAT

LCD_VCC_TEST_EN

PBAT_SMBDAT
PBAT_SMBCLK
SBAT_SMBDAT
SBAT_SMBCLK

1.5V_RUN_ON

1.25V_RUN_ON

IMVP_PWRGD
FAN1_TACH

1 2

BREATH_LED
SIO_EXT_SCI#

PS_ID
SIO_RCIN#
BEEP

DEBUG_ENABLE#
HOST_DEBUG_TX

HOST_DEBUG_RX
CAP_LED#

SCRL_LED#
NUM_LED#
SIO_SPI_CS#

LOM_SMB_ALERT#
SFPI_EN
DOCK_SMB_ALERT#

0.9V_DDR_VTT_ON
SIO_EXT_SMI#

BAT2_LED#
BAT1_LED#

FWP#

RUNPWROK
RESET_OUT#
MEC_TEST_PIN

+3.3V_ALW

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

ALWON 45
SNIFFER_PWR_SW# 43

ACAV_IN 18,49,50

BREATH_LED 43

CAP_LED# 43
SCRL_LED# 43
NUM_LED# 43

DOCK_SMB_ALERT# 36

SIO_EXT_SMI# 23
BAT2_LED# 43
BAT1_LED# 43

RUNPWROK 38,42,48
RESET_OUT# 42

12

Populate
for flash

R222

corruption
issue.

0_0402_5%~D

FWP#

Flash write protect bottom 4K
of internal bootblock flash

1

C82

0.1U_0402_16V4Z~D

2

T37 PAD~D

LCD_SMBCLK 19
LCD_SMBDAT 19
DOCK_SMB_CLK 36
DOCK_SMB_DAT 36

LCD_VCC_TEST_EN 19

T87 PAD~D
T88 PAD~D

PBAT_SMBDAT 44

PBAT_SMBCLK 44

SBAT_SMBDAT 44

SBAT_SMBCLK 44

1.5V_RUN_ON 47

1.25V_RUN_ON 46
THRM_SMBDAT 18 , 4 9
THRM_SMBCLK 18,49

IMVP_PWRGD 23,42,48

FAN1_TACH 18
IMVP_VR_ON 48

WLAN_3V_ENABLE 34

3.3V_SUS_ON 41

SIO_EXT_SCI# 23

PS_ID 44

SIO_RCIN# 22

BEEP 26

T38 PAD~D

HOST_DEBUG_TX 34
HOST_DEBUG_RX 34

LOM_SMB_ALERT# 23,28

0.9V_DDR_VTT_ON 46

T39 PAD~D

+3.3V_ALW

12

R92
100K_0402_5%~D

@

low=write protected

12

R93

100K_0402_5%~D

1

2

Bat2 = Amber LED
Bat1 = Green LED

20mA drive pins

2

C369

0.1U_0402_16V4Z~D

SIO_SPI_CS#

ICH_SPI_CS0#23

SPI_CS0#
EC_FLASH_SPI_DIN

2

+RTC_CELL

12

R211
100K_0402_5%~D

POWER_SW_IN# POWER_SW#

+3.3V_ALW

C146

@

0.1U_0402_16V4Z~D

1 2

5

U30

@

1

IN1

2

IN2

15_0402_5%~D

P

4

1 2

O

G

74AHC1G08GW_SOT353-5~D

3

1 2

R397

0_0402_5%~D

10K_0402_5%~D

1 2

1

C368

2

1U_0603_10V4Z~D

R396

@

SPI_CS0#

Non-iAMT

+3.3V_SUS

12

R219
10K_0402_5%~D

U23

1

CS#

VCC

1 2

R84

15_0402_5%~D

Non-iAMT Non-iAMT

2

SO

HOLD#

3

WP#

SCLK

4

GND

M25P16-VMW6TP_SO8~D

Flash ROM

200 MIL SO8

Layout Note:
Place R84 within 500 mils from SPI flash.

Place R398 & R399 within 500 mils of the
MEC5025.

1

R210

POWER_SW_IN1#

R69 100K_0402_5%~D

DOCK_SMB_DAT
DOCK_SMB_CLK

DOCK_SMB_ALERT#

LCD_SMBDAT
THRM_SMBDAT
THRM_SMBCLK
SBAT_SMBDAT
SBAT_SMBCLK
PBAT_SMBDAT
PBAT_SMBCLK
HOST_DEBUG_RX

LOM_SMB_ALERT#

EC_FLASH_PAD
@SHORT PADS~D

R76

SFPI_EN

1K_0402_5%~D

1=Flash Recovery Enabled
0=Flash Recovery Disabled

+3.3V_SUS

12

8
7
6
5

SI

POWER_SW# 18,40

12

12

R67 8.2K_0402_5%~D

12

R66 8.2K_0402_5%~D

12

R794 10K_0402_5%~D

1 2

R161 8.2K_0402_5%~D

1 2

R162 8.2K_0402_5%~D

1 2

R64 4.7K_0402_5%~D

1 2

R65 4.7K_0402_5%~D

1 2

R75 2.2K_0402_5%~D

1 2

R81 2.2K_0402_5%~D

1 2

R62 2.2K_0402_5%~D

1 2

R63 2.2K_0402_5%~D

1 2

R400 1M_0402_5%~D

1 2

R730 4.7K_0402_5%~D

+3.3V_ALW

12

C398

1 2

0.1U_0402_16V4Z~D
R218

10K_0402_5%~D

R398

15_0402_5%~D

1 2
1 2

R399

15_0402_5%~D

DELL CONFIDENTIAL/PROPRIETARY

Title

Size Do c um e n t N u mb er Re v

Date: Sheet

Compal Electronics, Inc.
EMC5025

LA-3301P

1

+RTC_CELL

+5V_ALW

+3.3V_ALW

+3.3V_LAN

1

1

2

2

12

R80
1K_0402_5%~D

EC_FLASH_SPI _CLK
EC_FLASH_SPI_DO

39 58Thursday, March 01, 2007

of

1.0

5

4

3

2

1

Touch PAD

JTPAD

2

112

COEX1_BT_ACTIVE34

USBP7-23
USBP7+23

C419

USBP5-23

USBP5+23

1

2

100P_0402_50V8J~D

@

C394

1

2

33P_0402_50V8J~D

1

2

100P_0402_50V8J~D

@

C384

COEX2_WLAN_ACTIVE

LID_CL#38

DLW21SN900SQ2_0805~D

4

1

1

1

1

2

2

2

@

C390

100P_0402_50V8J~D

@

C386

100P_0402_50V8J~D

@

C397

100P_0402_50V8J~D

L4

@

4

1

1

2

C426

0.1U_0402_16V4Z~D

R407

0_0402_5%~D

1 2

R410

0_0402_5%~D

1 2

100P_0402_50V8J~D

@

C393

COEX2_WLAN_ACTIVE34

100P_0402_50V8J~D

12

R249

10K_0402_5%~D

1

1

2

2

100P_0402_50V8J~D

100P_0402_50V8J~D

@

@

C395

C383

D D

KSO[0..17]37

KSI[0..7]37

C C

B B

POWER_SW#18,39
R_NUM_LED#43
R_CAP_LED#43
R_SCRL_LED#43

+3.3V_ALW

KSO17
KSO16
KSO15
KSO14
KSO13
KSO12
KSO11
KSO10
KSO9
KSO8
KSO7
KSO6
KSO5
KSO4
KSO3
KSO2
KSO1
KSO0

KSI7
KSI6
KSI5
KSI4
KSI3
KSI2
KSI1
KSI0

KSO10

KSO11

KSO9
KSO14
KSO13
KSO15
KSO16
KSO12
KSO0
KSO2
KSO1
KSO3
KSO8
KSO6
KSO7
KSO4
KSO5
KSI0
KSI3
KSI1
KSI5
KSI2
KSI4
KSI6
KSI7
POWER_SW#
R_NUM_LED#
R_CAP_LED#
R_SCRL_LED#
KSO17

1

2

@

C387

100P_0402_50V8J~D

1

1

1

2

2

2

100P_0402_50V8J~D

100P_0402_50V8J~D

@

@

@

C392

C381

C382

+3.3V_RUN

TP_DET#39

+3.3V_ALW

1

2

1

2

100P_0402_50V8J~D

@

C380

USBP7­USBP7+

USBP5_D­USBP5_D+

1

1

C424

C423

2

2

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

USBP5_D-

3

3

USBP5_D+

2

2

KYBD_DET#37

1

1

1

2

2

2

@

C371

100P_0402_50V8J~D

@

C372

100P_0402_50V8J~D

@

C389

100P_0402_50V8J~D

1

1

1

2

2

2

@

C378

100P_0402_50V8J~D

@

C376

100P_0402_50V8J~D

@

C374

100P_0402_50V8J~D

334
556

7

8

7

9

10

9

11

12

11

13

14

13

15

16

15

17

18

17

19

20

19

21

22

21

23

24

23

25

26

25

27

28

27

29

30

29
G131G2

FOX_HT1315F-P2~D

+3.3V_ALW

12

1

1

2

2

100P_0402_50V8J~D

@

@

C396

C373

4
6
8
10
12
14
16
18
20
22
24
26
28
30
32

R575
100K_0402_5%~D

KYBD_DET#

1

1

2

2

100P_0402_50V8J~D

100P_0402_50V8J~D

@

@

C377

C391

BT_RADIO_DIS#
COEX3

SP_GND
SP_X
SP_Y
SP_V+

TP_CLK
TP_DATA

1

2

1

2

100P_0402_50V8J~D

100P_0402_50V8J~D

@

C375

T4 PAD~D

BT_ACTIVE 34,43

12

R119

10K_0402_5%~D

+5V_RUN

1

C430

C210

2

0.047U_0402_16V4Z~D

1

1

2

2

100P_0402_50V8J~D

100P_0402_50V8J~D

@

@

C78

C388

0.1U_0402_16V4Z~D

JKYBRD

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

11

11

12

12

13

13

14

14

15

15

16

16

17

17

18

18

19

19

20

20

21

21

22

22

23

23

24

24

25

25

26

26

27

27

28

28

29

29

30

30

31

31

32

32

33

33

34

34

FOX_GS12403-0001K-8F~D

SP_GND

SP_X
SP_V+
SP_Y

35
36
37
38
39
40

GND
GND

+3.3V_RUN

DA204U_SOT323~D

TP_DATA
TP_CLK

35
36

SP_GND

37
38
39
40

41
42

SP_X
SP_V+
SP_Y

1

2

BT_RADIO_DIS# 38

1

C103

2

100P_0402_50V8J~D

1

D37

@

2

BLM18AG601SN1D_0603~D

1 2
1 2

L26
BLM18AG601SN1D_0603~D

1

C87

C86

2

10P_0402_50V8J~D

10P_0402_50V8J~D

+3.3V_RUN

1

C102

0.1U_0402_16V4Z~D

2

FAN

Part Number Description

Speak

Part Number Description

1

2

3

L25

1

D38

@

3

2

DA204U_SOT323~D

+5V_RUN

12

12

R228

4.7K_0402_5%~D

1

1

C400

2

2

10P_0402_50V8J~D

D39

@

3

R229

4.7K_0402_5%~D

DAT_TP_SIO
CLK_TP_SIO

C399

DA204U_SOT323~D

10P_0402_50V8J~D

1

D40

@

2

3

DA204U_SOT323~D

DAT_TP_SIO 39
CLK_TP_SIO 39

FAN SET DAQ20 DC5V AB7405HB-HB3 ADDA

DC28A000800

SPK PACK ZJX 2.0W 4 OHM FG

PK230003Q0L

SM CARD BODY

Part Number Description

SP070007V0L

PCMCIA BODY

Part Number Description

DC000001Q0L

MDC wire set cable

Part Number Description

DC02000CS0L

T/P wire set cable

Part Number Description

DC02000840L

LVDS cable

Part Number Description

DC020003Y0L

LVDS cable

Part Number Description

DC02000870L

RTC BATT

Part Number Description

GC20323MX00

S SOCKET TYCO 1770551-1
10P H5.9 SMART

PCMCIA TYCO
1759096-1

H-CONN SET ZGX
MB-MDC

H-CONN SET ZJX
MB-B/T-TP-FP

H-CONN SET ZJX MB-LCD
14 WXGA+(-1ch)

H-CONN SET ZJX
MB-LCD 14 WXGA+(-2ch)

BATT CR2032 3V
220MAH MAXELL

Power Switch

POWER_SW#

C367

@

100P_0402_50V8J~D

1

2

PWR_SW

@SHORT PADS~D

112

2

A A

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.
INT KB

LA-3301P

40 58Monday, February 26, 2007

1

1.0

of

5

4

3

2

1

DC/DC Interface

+3.3V_ALW2

2

Q53

G

+15V_ALW

12

R624
100K_0402_5%~D

13

D

S

+3.3V_ALW2 +5V_ALW

D D

RUN_ON_5V#

RUN_ON19,37,39,42

12

R623
100K_0402_5%~D

2N7002W-7-F_SOT323-3~D

13

D

2

G

Q55

S

2N7002W-7-F_SOT323-3~D

Q52

SI4810BDY-T1-E3_SO8~D

8
7

5

4

1

C815

2

2200P_0402_50V7K~D

1
2
36

C814

+5VRUN Source

+5V_RUN

12

1

R625
20K_0402_5%~D

2

10U_0805_10V4Z~D

3.3V_SUS_ON39

2

G

12

R765
100K_0402_5%~D

13

D

S

Q87
2N7002W-7-F_SOT323-3~D

+15V_ALW

2

G

12

R764
100K_0402_5%~D

13

D

S

Q88
2N7002W-7-F_SOT323-3~D

+3.3V_ALW

8
7

5

Q47

SI4810BDY-T1-E3_SO8~D

+3VSUS Source

1
2
36

4

1

C195
4700P_0402_25V7K~D

2

@

C811

10U_0805_10V4Z~D

+3.3V_SUS

12

1

R620

2

20K_0402_5%~D

+1.8V_RUN Source

Q54

SI4336DY-T1-E3_SO8~D

8
7

C C

+15V_ALW

+3.3V_ALW2

12

R621
100K_0402_5%~D

SUS_ON_5V#

13

B B

SUS_ON39,42

D

2

G

S

Q51
2N7002W-7-F_SOT323-3~D

2

G

12

R617
100K_0402_5%~D

13

D

S

Q49
2N7002W-7-F_SOT323-3~D

5

D35

@

21

RB751V_SOD323~D

1 2

R305

0_0402_5%~D

+5V_ALW

SI3456BDV-T1-E3_TSOP6~D

SUS_ENABLE

4

1

C194

0.047U_0402_16V4Z~D

2

@

Q80

D

6
2

1

G

3

1

2

1
2
36

S

45

C142

@

+1.8V_RUN+1.8V_SUS

12

1

C816

2

10U_0805_10V4Z~D

+5VSUS Source

+5V_SUS

12

1

2

C143

10U_0805_10V4Z~D

4700P_0402_25V7K~D

+3.3V_RUN Source

+3.3V_ALW

R628

20K_0402_5%~D

+15V_ALW

12

R641
100K_0402_5%~D

13

D

2

G

S

Q89

2N7002W-7-F_SOT323-3~D

D36

@

RB751V_SOD323~D

21

1 2

R413

0_0402_5%~D

R762

+3.3V_ALW2

12

R766
100K_0402_5%~D

13

D

Q90

3.3V_RUN_ON39

20K_0402_5%~D

2

G

S

2N7002W-7-F_SOT323-3~D

Q10

@

SI4810DY-T1-E3_SO8~D

8
7

5

4

Q58

SI4336DY-T1-E3_SO8~D

8
7

5

4

1

C144
470P_0402_50V7K~D

2

@

1
2
36

+3.3V_RUN

1
2
36

C819

10U_0805_10V4Z~D

12

1

R630

2

20K_0402_5%~D

Discharg Circuit

+1.5V_RUN +0.9V_DDR_VTT+3.3V_RUN+5V_RUN +1.8V_RUN +1.25V_RUN+1.8V_SUS +5V_SUS +3.3V_SUS

1K_0402_5%~D

2

G

Q64

2N7002W-7-F_SOT323-3~D

LA-3301P

12

R729

@

13

D

S

@

1

12

R633

@

13

D

2

G

S

@

1K_0402_5%~D

Q61

2N7002W-7-F_SOT323-3~D

12

R634

@

13

D

2

G

S

@

1K_0402_5%~D

Q62

2N7002W-7-F_SOT323-3~D

12

R635

@

13

D

2

G

S

@

DELL CONFIDENTIAL/PROPRIETARY

Title

Size Document Number Rev

2

Date: Sheet

1K_0402_5%~D

Q92

2N7002W-7-F_SOT323-3~D

12

R117

@

1K_0402_5%~D

13

D

2

Q93

G

S

@

RUN_ON_5V#SUS_ON_5V#

2N7002W-7-F_SOT323-3~D

12

R151

@

13

+PWR_SRC+PWR_SRC

12

12

R699
100K_0402_5%~D

A A

AUX_ON39

2N7002W-7-F_SOT323-3~D

5

N21917830

13

D

2

G

Q73

R701

S

200K_0402_5%~D

R698
100K_0402_5%~D

ENAB_3VLAN 28

13

D

2

G

12

1

C208

Q72

2N7002W-7-F_SOT323-3~D

4700P_0402_25V7K~D

2

S

12

R700
470K_0402_5%~D

4

D

2

G

S

@

12

R118

@

75_0603_5%~D

13

D

2

Q91

G

S

@

2N7002W-7-F_SOT323-3~D

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

1K_0402_5%~D

Q63

2N7002W-7-F_SOT323-3~D

12

R636

@

13

D

2

G

S

@

Compal Electronics, Inc.
POWER CONTROL

1K_0402_5%~D

Q81

2N7002W-7-F_SOT323-3~D

12

R113

@

1K_0402_5%~D

13

D

2

Q30

G

S

@

2N7002W-7-F_SOT323-3~D

41 58Monday, February 26, 2007

1.0

of

5

Non-iAMT

D D

+5V_RUN

1

2

+1.8V_RUN

1

2

+3.3V_RUN

1

C C

2

B B

A A

D25

2 1

RB751V_SOD323~D

C46

0.1U_0402_16V4Z~D

D26

2 1

RB751V_SOD323~D

C47

0.1U_0402_16V4Z~D

D27

2 1

RB751V_SOD323~D

C49

0.1U_0402_16V4Z~D

+3.3V_SUS

RB751V_SOD323~D

2 1

1

C457

0.1U_0402_16V4Z~D

2

+5V_SUS

RB751V_SOD323~D

2 1

1

C199

0.1U_0402_16V4Z~D

2

12

R68

12

R616

12

R82

D23

12

R139

D31

12

R158

1

2

200K_0402_5%~D

1

2

200K_0402_5%~D

1

2

200K_0402_5%~D

1

2

200K_0402_5%~D

1

2

200K_0402_5%~D

R334

10K_0402_5%~D

1 2

C17
2200P_0402_50V7K~D

R364

10K_0402_5%~D

1 2

C19
2200P_0402_50V7K~D

R367

10K_0402_5%~D

1 2

C27
2200P_0402_50V7K~D

R159

10K_0402_5%~D

1 2

C422

2200P_0402_50V7K~D

R160

10K_0402_5%~D

1 2

C404

2200P_0402_50V7K~D

+5V_ALW

E

3

Q77

B

MMBT3906WT1G_SC70-3~D

2

C

1

+1.8V_SUS

E

3

Q78

B

MMBT3906WT1G_SC70-3~D

2

C

1

+3.3V_ALW

E

3

Q79

B

MMBT3906WT1G_SC70-3~D

2

C

1

E

3

B

Q20

2

MMBT3906WT1G_SC70-3~D

C

1

12

R135

+5V_ALW

E

3

B

Q26

2

MMBT3906WT1G_SC70-3~D

C

1

12

R157

R133

4.7K_0402_5%~D

1 2

R134

4.7K_0402_5%~D

1 2

R164

4.7K_0402_5%~D

1 2

D32

2 1

RB751V_SOD323~D

200K_0402_5%~D

D33

RB751V_SOD323~D

2 1

200K_0402_5%~D

4

1.25V_RUN_PWRGD46

2.5V_RUN_PWRGD18

1.5V_RUN_PWRGD47

1.05V_RUN_PWRGD47

C

Q84

2

B

MMST3904-7-F_SOT323-3~D

E

3 1

C

Q85

2

B

MMST3904-7-F_SOT323-3~D

E

3 1

C

Q86

2

B

MMST3904-7-F_SOT323-3~D

E

3 1

+3.3V_ALW+3.3V_ALW

A1Y

12

R136
200K_0402_5%~D

1 2

R486 0_0402_5%~D

R216 0_0402_5%~D@

R207 0_0402_5%~D

R208 0_0402_5%~D

C186

0.1U_0402_16V4Z~D

1 2

8

U48A

P

7

G

74LVC3G14DC_VSSOP8~D

4

3

12

12

12

5V_3V_1.8V_1.25V_RUN_PWRGD 38

+3.3V_SUS

12

1

2

IMVP_PWRGD23,39,48

RESET_OUT#39

3.3V_5V_SUS_PWRGD

+3.3V_ALW

R132
20K_0402_5%~D

3VRUNRC

C134

0.01U_0402_16V7K~D

IMVP_PWRGD
RESET_OUT#

C135

0.1U_0402_16V4Z~D

1 2

8

U12A

P

7

A1Y

G

74LVC3G14DC_VSSOP8~D

4

+3.3V_ALW

4

IN1

5

IN2

+3.3V_ALW

A6Y

RUN_ON19,37,39,41

SUS_ON39,41

100K_0402_5%~D

14

U27B

P

6

OUT

G

74VHC08MTCX_NL_TSSOP14~D

7

8

U12B

P

2

G

74LVC3G14DC_VSSOP8~D

4

+3.3V_SUS

12

R79

13

D

2

G

S

2

1 2

R418
0_0402_5%~D

10

ICH_PWRGD#

Q17
2N7002W-7-F_SOT323-3~D

ICH_PWRGD# 18

ICH_PWRGD 10,23

+3.3V_ALW

1 2

14

U27A
74VHC08MTCX_NL_TSSOP14~D

1

P

IN1

OUT

2

IN2

G

7

+3.3V_ALW

14

U27C

P

IN1

OUT

9

IN2

G

74VHC08MTCX_NL_TSSOP14~D

7

+3.3V_RTC_LDO

C458

0.1U_0402_16V4Z~D

3

13
12

8

+COINCELL

Z4012

2

D13

1

BAT54CW_SOT323~D

+3.3V_ALW

8

U12C

P

5

A3Y

G

74LVC3G14DC_VSSOP8~D

4

+3.3V_ALW

14

U27D

P

IN1

11

OUT

IN2

G

74VHC08MTCX_NL_TSSOP14~D

7

COIN RTC Battery

12

R21
1K_0402_5%~D

3

+RTC_CELL

1

C370
1U_0603_10V4Z~D

2

RUNPWROK

+COINCELL

1

RUNPWR OK 38,39,48

SUSPWROK 18

JCOIN

COINCELL

1
2

MOLEX_53398-0271~D

1
2

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.
Power Good

LA-3301P

42 58Monday, February 26, 2007

1

1.0

of

H26

1

1

LED_MASK#38

5

H3

@H_C315D110

1

H12
@H_C315D118

1

H27

@H_C472D431X376

1

SATA_ACT#_R SATA_ACT#

+3.3V_ALW

H1

H_C146B217D91

1

H10

@H_C236B315D110

1

D D

H20

@H_C217B276D98

1

C C

H2
H_C146B217D91

1

H11
@H_C315B236D118

@H_C472D376

This circuit is
only needed if the
platform has the
SNIFFER.

SATA_ACT#_R22

H5

H4

H_C256B63D47

@H_C236B315D110

1

H13

@H_C315D118

1

H28

@H_O115X31D115X31N

1

+3.3V_RUN

12

R78
10K_0402_5%~D

12

R97
10K_0402_5%~D

@

1

H14

@H_C291B236D118

1

H29

@H_O115X31D115X31N

R140
0_0402_5%~D @

1 2

D

S

13

Q23

G

BSS138W-7-F_SOT323~D

2

H6

@H_C236B256D110

H15
@H_C295D118

1

1

1

H7
@H_C236B315D110

H16
@H_C217B276D98

1

H30

@H_O115X31D115X31N

1

1

+3.3V_RUN

12

4

@H_C217B276D98

H17
@H_C217B276D98

1

R181
100K_0402_5%~D

@

1 2

R179
0_0402_5%~D

CLIP4
EMI_CLIP

CLIP6
EMI_CLIP

CLIP1
EMI_CLIP

3

EMI CLIP

1

GND

1

GND

1

GND

CLIP5
EMI_CLIP

1

GND

CLIP3
EMI_CLIP

1

GND

CLIP2
EMI_CLIP

1

GND

R74

10K_0402_5%~D

BT_ACTIVE

BT_ACTIVE34,40

LED_MASK#38

1 2

E

3

B

2

1

2

@H_C236B315D110

H18

@H_C217D91

1

+3.3V_RUN

1 3

H9

1

H19

@H_C217D91

1

Q22
PDTA114EU_SC70-3~D

R145

330_0402_5%~D

1 2

HDD_LED 32

R_PIDEACT 36

H8

1

2

FIDUCIAL MARK~D

FIDUCIAL MARK~D

FIDUCIAL MARK~D

CAP_LED#39

NUM_LED#39

SCRL_LED#39

13

D

2

G

Q29
BSS138W-7-F_SOT323~D

S

Q18
MMBT3906WT1G_SC70-3~D

C

1

1

FD20

FD4

FD10

FD25

1

1

FIDUCIAL MARK~D

1

FIDUCIAL MARK~D

1

FIDUCIAL MARK~D

1

FIDUCIAL MARK~D

R_CAP_LED# 40

R_NUM_LED# 40

R_SCRL_LED# 40

FD12

FD15

FD19

FD6

FD21

1

FIDUCIAL MARK~D

FD16

1

FIDUCIAL MARK~D

FD8

1

FIDUCIAL MARK~D

FD7

1

FIDUCIAL MARK~D

Fiducial Mark

FIDUCIAL MARK~D

FIDUCIAL MARK~D

FIDUCIAL MARK~D

FIDUCIAL MARK~D

R226

330_0402_5%~D

R224

330_0402_5%~D

R225

330_0402_5%~D

Q28
PDTA114EU_SC70-3~D

1 3

R212
1K_0402_5%~D

1 2

FD2

1

FD11

1

FD9

1

FD18

1

12

12

12

FD1

1

FD13

1

FD17

1

+5V_RUN

2

R_BT_ACT

FD5

1

FIDUCIAL MARK~D

FD14

1

FIDUCIAL MARK~D

FD3

1

FIDUCIAL MARK~D

R_CAP_LED#

R_NUM_LED#

R_SCRL_LED#

R_BT_ACT 32

FIDUCIAL MARK~D

FIDUCIAL MARK~D

1

FIDUCIAL MARK~D

1

FIDUCIAL MARK~D

+3.3V_SUS

5

1

U43

P

2

2

NC

A2Y

G

NC7SZ04P5X_NL_SC70-5~D

3

+3.3V_ALW

Q1
PDTA114EU_SC70-3~D

1 3

+3.3V_ALW

Q4
PDTA114EU_SC70-3~D

1 3

+3.3V_WLAN

+3.3V_RUN

12

R638

47K_0402_5%~D

B B

+3.3V_SUS

Q32

1 3

+3.3V_SUS

1 3

PDTA114EU_SC70-3~D

Q33
PDTA114EU_SC70-3~D

SNIFFER_YELLOW#39

A A

SNIFFER_GREEN#39

SNIFFER_YELLOW#

SNIFFER_GREEN#

5

2

2

LED_WLAN_OUT#34

1 2

R261 220_0402_5%~D

1 2

R262 220_0402_5%~D

4

SNIFFER_Y
SNIFFER_G

1 2

R639

10K_0402_5%~D

WIRELESS_ON/OFF#38

SNIFFER_PWR_SW#39

D14

Y

3
2

G

12-22AUYSYGC/530-A2/TR8_G/Y~D

1

12

R180

100K_0402_5%~D

E

3

B

Q5

2

MMBT3906WT1G_SC70-3~D

C

1

1 2

+3.3V_RUN+RTC_CELL

12

R102
100K_0402_5%~D

R15

150_0402_5%~D

3

R_MPCI_ACT

JSNIFF

R_MPCI_ACT 32

6

6

4

4

3

3

2

2

1

1

5

1BS008-13130-7F_4P~D

5

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

BAT1_LED#39

BAT2_LED#39

BREATH_LED39

BAT1_LED#

BAT2_LED#

2

R71

100_0402_5%~D

1 2

4

R6

1 2

R9

1 2

220_0402_5%~D

220_0402_5%~D

BREATH_GREEN_LED 32

BATT_GREEN_LED

BATT_AMBER_LED

BATT_GREEN_LED 32

BATT_AMBER_LED 32

DELL CONFIDENTIAL/PROPRIETARY

Title

Size Do c um e n t N u mb er Re v

Date: Sheet

Compal Electronics, Inc.
PAD and Standoff

LA-3301P

1

43 58Monday, February 26, 2007

1.0

of

5

4

3

2

1

+3.3V_ALW

ESD Diodes

3

0.1U_0603_25V7K~D

12

1 2

1 2

PAD-OPEN 4x4m

PL32

PJP60

D D

PC231

Secondary Battery Connector

PJP1

BATT1+
BATT2+

12

2200P_0402_50V7K~D

BATT_PRES#

SYSPRES#

BATT_VOLT

10

GND

11

GND

TYCO_1734077-1~D

SMB_CLK

SMB_DAT

BATT1­BATT2-

1
2
3
4
5
6
7
8
9

Z4301
Z4302
Z4303

PD42

DA204U_SOT323~D @

PR301

100_0402_5%~D

1 2

+3.3V_ALW

1

PR302

100_0402_5%~D

1 2

PD43

DA204U_SOT323~D @

1

PR303

100_0402_5%~D

1 2

PD44
DA204U_SOT323~D @

100_0402_5%~D

1

PR304

1 2

PD45

1

DA204U_SOT323~D @

SBAT_SMBCLK 39
SBAT_SMBDAT 3 9

SBAT_ALARM#

FBMA-L18-453215-900LMA90T_1812~D

PC230

SBATT+

+3.3V_ALW

12

PR300

10K_0402_5%~D

SBAT_PRES# 3 8, 50

2

3

2

3

2

3

2

ESD Diodes

2

3

2

3

2

3

PD11

1

PR22

100_0402_5%~D

1 2

1

DA204U_SOT323~D @

PR23

100_0402_5%~D

1 2

PD10

1

DA204U_SOT323~D @

PR21

100_0402_5%~D

1 2

C C

PC10

Primary Battery Connector

PBATT1

SMB_CLK

12

2200P_0402_50V7K~D

SMB_DAT

BATT_PRES#

SYSPRES#

BATT_VOLT

10

GND

11

GND

SUYIN_2 00277MR009G 506ZR ~D

BATT1+
BATT2+

BATT1­BATT2-

1
2
3
4
5
6
7
8
9

Z4304
Z4305
Z4306

PD9

DA204U_SOT323~D @

PR20

100_0402_5%~D

1 2

2

3

PD12

1

DA204U_SOT323~D @

PBAT_SMBCLK 39
PBAT_SMBDAT 3 9

PBAT_ALARM#

PC9

PL6

FBMA-L18-453215-900LMA90T_1812~D

1 2

PJP61

1 2

12

PAD-OPEN 4x4m

0.1U_0603_25V7K~D

PBATT+

+3.3V_ALW

12

PR19

10K_0402_1%~D

PBAT_PRES# 38

+5V_ALW

2

PR184

1 2

3

PD2

DA204U_SOT323~D

1

+5V_ALW

B B

PR346

@

1 2

0_0402_5%~D

GPIO Input from EC

Z-series AC Adaptor
Connctor

PJPDC1
TYCO_1566065-2~D

9

GND_4

8

GND_3

7

GND_2

6

GND_1

A A

MH1

MH2

Low_PWR

DC+_1
DC+_2

DC-_1
DC-_2

1
2
3
4
5

1

@

2

5

BLM18BD102SN1D_0603~D

FBMJ4516HS720NT 1806~D

+DCIN_JACK

-DCIN_JACK

1 2

FBMJ4516HS720NT 1806~D

PD59

VZ0603M260APT_0603

PL1

12

PL2

1 2

1

PD58

@

2

VZ0603M260APT_0603

PL34

AC_OFF39

12

PC397

0.1U_0603_25V7K~D

@

PQ100B

IMD2AT- 108_S C 74-6~D

12

2

PR495

0_0402_5%~D

@

16

@

5

+DC_IN

+DC_IN

PC2

1 2

@

43

0.47U_0805_25V7K~D

PQ100A
IMD2AT- 108_S C 74-6~D

1
2
3 6

12

PR11

240K_0402_5%~D

4

PQ3

FDS6679AZ_SO8~D

4

12

PR13

47K_0402_1%~D

DOCK_PSID36

DC_IN+ Source

8
7

5

12

PC4

PC3

0.1U_0603_25V7K~D

THESE CAPS MUST BE
NEXT TO JCHG

2

3

+DC_IN_SS

12

0.1U_0603_25V7K~D

12

12

PC5

PR12

0.1U_0603_25V7K~D

12

PC6

4.7K_0805_5%~D
10U_1206_25V6M~D

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONF IDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVIS ION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INF ORMATION IT CONT AINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WR ITT EN CO NSE NT OF COMPAL ELECTRONICS, INC.

3

@

1

PD53
SM24_SOT23

PR6

PR10

1 2

100K_0402_1%~D

1 2

15K_0402_1%~D

1 3

2

B

D

S

PQ1

G

2

FDV301N_SOT23~D

C

PQ2
MMST3904-7-F_SOT323~D

E

3 1

2

33_0402_5%~D

+3.3V_ALW

PR2

1 2

2.2K_0402_5%~D

PS_ID 39

2

PSID_DISABLE# 38

12

PR7

10K_0402_1%~D

1 2

PR299

10K_0402_5%~D @

@

+5V_ALW

PD41

DA204U_SOT323~D

3

1

DELL CONFIDENTIAL/PROPRIETARY

Title

Size Do c um e n t N u mb er Re v

Date: Sheet

Compal Electronics, Inc.

+DCIN
LA-3301P

1

44 58Monday, February 26, 2007

0.0

of

5

4

3

2

1

+3.3V_ALWP/ +5V_ALWP/ +5V_ALW2 / +15V_ALWP

PL36

+DC1_PWR_SRC

12

PR379

PR380

PC286

1 2

PR500

PR376

@

10_0603_5%~D

32
31
30
29
28

EN_3V_5VEN _3V_ 5V

27

+3.3V_ALW_UGATE

26

+3.3V_ALW_PHASE

25

PR387

1_0603_5%~D

1 2

PJP34

1 2

PAD-OPEN1x1m

+5V_VCC1

12

12

PC283

1U_0603_10V6K~D

GNDA_3V5V

PR382

267K_0402_1%~D

1 2

PR517 0_0402_5%~D

12

POK2

12

PC288

+3.3V_ALW_LGATE

12

0_0402_5%~D
PR499

@

0.1U_0603_25V7K~D

PR501

12

0_0402_5%~D

GNDA_3V5V

GNDA_3V5V

POK2

POK1

@

12

PC385

0.1U_0402_10V7K~D

+3.3V_ALWP

PR391

12

12

12

12

PC274

PC275

PC276

PL37

PC277

10U_1206_25V6M~D

10U_1206_25V6M~D

3.3 Volt +/-5%
Thermal Design Current: 8.6A
Peak current: 12.3A
OCP min:13.08A

+3.3V_ALWP

12

12

PR385

0_0402_5%~D

12

PR389

@

0_0402_5%~D

GNDA_3V5V

PC292

0.1U_0402_10V7K~D

1

12

+

PC290

2

330U_D3L_6.3VM_R25~D

0.1U_0805_50V7K

2200P_0402_50V7K~D

5

PQ83

D

BSC079N03S G_PG-TDSON-8~D

4

G

S3S

S

2

1

3.0U_HMP1362-3R0-R_17A~D

786

5

PQ85
FDS6676AS_NL_SO8~D

4

123

+3.3V_ALWP

PR390

@

1 2

1 2

100K_0402_1%~D

100K_0402_1%~D

12

PR393

0_0402_5%~D

ALW_PWRGD_3V_5V 39

PJP63

1 2

PR375

0_0805_5%

1 2

GNDA_3V5V

+5V_ALWP

POK1

GNDA_3V5V

PR386

1_0603_5%~D

+5V_ALW_LGATE

PC293

0.1U_0603_25V7K~D

1

1 2

PC295

0.1U_0603_25V7K~D

1 2

1

12

PC296

0.1U_0603_25V7K~D

+5V_ALW2

12

PC285

0.1U_0603_25V7K~D

9

BYP

10

OUT1

11

FB1

12

ILIM1

13

POK1

14

EN1

15

UGATE1

16

PHASE1

33

+5V_ALW_BOOT

3

PR397

200K_0402_1%~D

PAD-OPEN1x1m

EN_3V_5V

5

7

4

8

3

6

VIN

LDO

VREF3

EN_LDO

LDOREFIN

PU20

ISL6236IRZA_Q FN 32~D

BOOT117LGATE118PVCC19SECFB20GND21PGND22LGATE223BOOT2

PAD

GNDA_3V5V

PC403

+5V_ALW2

PD57

1

BAT54CW_SOT323~D

2

12

PR398

1 2

39.2K_0402_1%~D

GNDA_3V5V

PC282

4.7U_0805_6.3V6K

0_0402_5%~D@

1 2

0_0402_5%~D

1 2

0.1U_0603_25V7K~D

@

1 2

0_0402_5%~D

1

REF

TON2VCC

REFIN2

ILIM2

OUT2

SKIP#

POK2

EN2
UGATE2
PHASE2

24

+3.3V_ALW_BOOT

12

GNDA_3V5V

1U_0603_10V6K~D

PR374

0_0805_5%

PC284

GNDA_3V5V

+5V_ALW_UGATE

+5V_ALW_PHASE

+5V_ALWP

12

BAT54SW-7-F_S OT323-3~D

0.1U_0603_25V7K~D

BAT54SW-7-F_S OT323-3~D

PJP35

+15V_ALWP

12

1 2

+3.3V_ALW2

12

0.1U_0603_25V7K~D

PR383
150K_0402_1%~D

1 2

12

PC287

0.1U_0603_25V7K~D

1 2

2
3

PD55

2
3

PD56

12

PC278

2200P_0402_50V7K~D

8

PQ82

D6D5D7D

4

G

S

S

S

3

2

1

786

5

PQ84

ALWON39

THERM_STP#18

123

4

PR392

2K_0402_5%~D

PR395

0_0402_5%~D

12

12

PC280

PC279

0.1U_0805_50V7K

12

12

PC281

10U_1206_25V6M~D

12

PC386

@

0.1U_0402_10V7K~D

+15V_ALW

(100mA,20mils ,Via NO.=1)

12

10U_1206_25V6M~D

PR394

200K_0402_5%

GNDA_3V5V

PC294

1 2

PAD-OPEN1x1m

DELL CONFIDENTIAL/PROPRIETARY

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONF IDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVIS ION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INF ORMATION IT CONT AINS

4

3

2

Title

Size Do c um e n t N u mb er Re v

Date: Sheet

Compal Electronics, Inc.

DC/DC +3V/ +5V
LA-3301P

1

45 58Monday, February 26, 2007

0.0

of

D D

C C

B B

A A

+PWR_SRC

5 Volt +/-5%
Thermal Design Current:6.2A
Peck current: 8.8A
OCP min: 9.05A

+5V_ALWP

1

+

PC289

2

330U_D3L_6.3VM_R25~D

+5V_ALWP

+3.3V_ALWP

12

PC291

0.1U_0402_10V7K~D

1 2

PAD-OPE N 4x4m

1 2

PAD-OPE N 4x4m

PJP33

1 2

PAD-OPE N 4x4m

PR384

@

0_0402_5%~D

1 2

PR388

0_0402_5%~D

1 2

GNDA_3V5V

PJP36

PJP37

5

FDS8880_NL_SO8~D

4.7U_HMU1356-4R7-R_10A~D

1 2

FDS6676AS_NL_SO8~D

+5V_ALW

+3.3V_ALW

5

4

3

2

1

1.8V/1.25V/0.9V VTT

PJP44

+PWR_SRC

D D

1.8 Volt +/-5%
Thermal Design Current: 5.7A
Peak current: 8.1A

1 2

PAD-OPEN 4x4m

12

PC318

10U_1206_25V6M~D

12

PC319

PC320

0.1U_0603_25V7K~D

10U_1206_25V6M~D

Place these CAPs
close to FETs

FDS8880_NL_SO8~D

12

12

PC321

2200P_0402_50V7K~D

8

PQ90

OCP min:8.6A

+1.8V_SUSP

1 2

FDS6676AS_NL_SO8~D

12

GNDA_DC2

+5V_ALW

PC348

1 2

10U_0805_6.3V6M~D

PL42

3

10

2
1
7
9

12

PC410

0.1U_0603_25V7K~D

C C

1

1

+

PC332

PC331

2

330U_D2E_2.5VM_R15~D

330U_D2E_2.5VM_R15~D

B B

+1.8V_SUS

0.9V_DDR_VTT_ON39

A A

+1.8V_SUSP

+0.9V_P

12

+

PC333

2

0.1U_0402_10V7K~D

DDR_ON39

PJP48

1 2

PAD-OPEN 4x4m

PJP49

1 2

PAD-OPEN 4x4m

PJP50

2 1

PAD-OPEN 2x2m~D

5

PAD-OPEN 2x2m~D

1.4UH_HMU1350-1R4PF_15A_20%~D

12

PC401

PR428

@

27.4K_0603_1%~D

1000P_0402_50V7K~D

12

PR433

17.4K_0402_1%~D

PJP47

2 1

+1.8V_SUS

+0.9V_DDR_VTT

S

1

PQ92

123

PJP45

12

PAD-OPEN1x1m

PU24

VIN
VLDOIN
VDDQSNS
S3
S5

TPS51100DGQRG4_MSOP10~D

D6D5D7D

S

S

3

2

786

VTTSNS
VTTREF

PGND

GND

G

5

VTT

BP

+1P8V_1P23V_PWRSRC

4

4

1.8V_SUS_PWRGD39

V_DDR_MCH_REF

3
5
6
4

8
11

PC345

GND

4

12

12

PC324

PC325

0.1U_0603_25V7K~D

10U_1206_25V6M~D

2200P_0402_50V7K~D

1.25 Volt +/-5%
Thermal Design Current: 1A
Peak current: 1.4A
OCP min:1.72A

3.3UH_MPL73-3R3_6A_20%~D

PL43

1.25V_RUN_PWRGD 42

1.25V_RUN_ON 39

1 2

PAD-OPEN 4x4m

12

12

PJP66

+1.25V_RUNP

1

+

PC334

2

220U_D2E_2.5VM_R15~D

12

PC335

0.1U_0402_10V7K~D

+0.9V_P

DDR_ON39

12

PC405

@

0.1U_0402_10V7K~D

+3.3V_ALW

PR434

1 2

20K_0402_5%~D

GNDA_DC2

PR426

130K_0402_1%~D

GNDA_DC2

1 2

1 2

1.8V_UGATE

PR427

0_0402_5%~D

0.9 Volt +/-5%

PC337

0.1U_0603_25V7K~D

+5V_ALW

1 2

PC338

1.8V_PHASE

1U_0603_10V6K~D

PR430

0_0603_5%~D

1 2

@

10_0603_5%~D

12

PR432

10
11
12
13
14
15
16

9

1.8V_LGATE

Thermal Design Current: 0.7A

BYP
OUT1
FB1
ILIM1
POK1

ISL6236IRZA_QFN32~D

EN1
UGATE1
PHASE1

PAD

33

GNDA_DC2

+5V_VCC3

12

12

PC339

1U_0603_10V6K~D

GNDA_DC2GNDA_DC2

PR418

0_0805_5%

1 2

+5V_VCC3

PR420

0_0402_5%~D

@

3

4

8

7

6

5

VIN

LDO

VREF3

EN_LDO

LDOREFIN

PU22

BOOT117LGATE118PVCC19SECFB20GND21PGND22LGATE223BOOT2

GNDA_DC2

1 2

1 2

0_0402_5%~D

1 2

1

2

REF

VCC

TON

UGATE2
PHASE2

24

1.25V_LGATE

PR419

@

PC326

PR421

PR423

@

0_0402_5%~D

REFIN2

ILIM2

OUT2

SKIP#

POK2

EN2

PR429

1_0603_5%~D

1 2

0_0805_5%

1 2

1 2

0.1U_0603_25V7K~D

VGA_ISL6236_REF

12

GNDA_DC2

32
31
30
29
28
27

1.25V_UGATE

26

1.25V_PHASE

25

PC336

0.1U_0603_25V7K~D

PC329

0.1U_0603_25V7K~D

PR425

51.1K_0402_1%~D

1 2

PR518

1 2

0_0402_5%~D

1 2

GNDA_DC2

@

PC406

0.1U_0402_10V7K~D

12

PC322

PC323

10U_1206_25V6M~D

Place these CAPs
close to FETs

PR422

10K_0402_1%~D

1 2

PR424

1 2

12

16.9K_0402_1%~D

GNDA_DC2

+3.3V_SUS

+3.3V_ALW

4

G1

2

G2

PQ91

5

FDS6982AS_NL_SO8~D

D16D1

3

S1

7

D2

8

D2

S2

1

PR431

@

100K_0402_1%~D

12

PR484

100K_0402_1%~D

12

+1.25V_RUNP +1.25V_RUN

Peak current: 1A

PC343

PC342

1 2

1 2

1 2

10U_0805_6.3V6M~D

10U_0805_6.3V6M~D

1U_0603_10V6K~D

PGND and GND sholud be tied
together at o n e p oi nt near the GND Pin

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

P47-PWR_1.25V/1.8V/LDO Vtt 0.9V

LA-3301P

46 58Monday, February 26, 2007

1

of

0.0

5

4

3

2

1

+DC2_PWR_SRC

PJP38

12

PC313

10U_1206_6.3V7K

GNDA_1P5V_1P05V

1 2

PAD-OPEN 4x4m

PC389

1 2

0.1U_0402_10V7K~D

PJP40

1 2

PAD-OPEN 4x4m

PJP43

1 2

PAD-OPEN 4x4m

12

PC297

PC299

10U_1206_25V6M~D

PR409

1 2

0_0402_5%~D

@

PR410

0_0402_5%~D

1 2

@

12

12

PC300

0.1U_0603_25V7K~D
2200P_0402_50V7K~D

3.3UH_MPL73-3R3_6A_20%~D

PL40

PR399

1 2

0_0805_5%~D

+5V_VCC2

GNDA_1P5V_1P05V

578

PQ87

12

SI4800BDY-T1_SO8~D

3 6

241

8

D6D5D7D

G

PQ89

S

S

S

3

2

1

SI4810BDY-T1-E3_SO8~D

4

GNDA_1P5V_1P05V

1 2

100K_0402_1%~D

GNDA_1P5V_1P05V

PR408

PR497

0_0402_5%~D

12

1 2

PC404

0.1U_0402_10V7K~D

@

+5V_ALW

10
11
12
13

EN1 EN2

14

1.5V_UGATE

15

1.5V_PHASE

16

PC314

1 2

GNDA_1P5V_1P05V

0.1U_0603_25V7K~D
PR411

1_0603_5%~D

1 2

12

PC317

1U_0603_10V6K~D

9

BYP
OUT1
FB1
ILIM1
POK1
EN1
UGATE1
PHASE1

PAD

33

1.5V_LGATE

PR413

@

10_0603_5%~D

8

7

6

5

VIN

LDO

VREF3

LDOREFIN

PU21

ISL6236IRZA_QFN32~D

BOOT117LGATE118PVCC19SECFB20GND21PGND22LGATE223BOOT2

12

PC316

4

+5V_VCC2

PR401

0_0402_5%~D

PC306

0.1U_0603_25V7K~D

REF

1 2

1 2

PR405

0_0402_5%~D@

1 2

PR504

0_0402_5%~D@

2

3

1

REF

VCC

TON

EN_LDO

REFIN2

ILIM2

OUT2

SKIP#

POK2

EN2
UGATE2
PHASE2

24

1_0603_5%~D

1 2

GNDA_1P5V_1P05V

1.05V_LGATE

12

1U_0603_10V6K~D

GNDA_1P5V_1P05V

PR400

1 2

0_0805_5%~D

1 2

PC305

0.1U_0603_25V7K~D

12

GNDA_1P5V_1P05V

REFIN2_1_05

32
31

1 2

PR407 249K_0402_1%~D

30

PR519 0_0402_5%~D

29

POK2POK1

28
27

1.05V_UGATE

26

1.05V_PHASE

25

PC315

0.1U_0603_25V7K~D

PR412

GNDA_1P5V_1P05V

+3.3V_RTC_LDO

12

PR496

1 2

PC308

0.01U_0402_25V7K~D

12

1 2

PJP41

PAD-OPEN1x1m

OK to Short if CAD
System can Support

@

0_0402_5%~D

0_0402_5%~D

12

PC387

0.1U_0402_10V7K~D

@

GNDA_1P5V_1P05V

GNDA_1P5V_1P05V

12

12

PR503

GNDA_1P5V_1P05V

@

POK2

POK1

12

12

PC301

PC302

10U_1206_25V6M~D

PC303

10U_1206_25V6M~D

12

12

PC304

0.1U_0603_25V7K~D
2200P_0402_50V7K~D

1.05 Volt +/-5%

5

D8D7D6D

PQ86

S1S2S3G

4

SI4682DY-T1-E3_SO8~D

0.88UH_MPC1040LR88_17A_20%~D

1 2

578

12

PR415

100K_0402_1%~D

PQ88

3 6

241

SI4362DY-T1-E3_SO8~D

+3.3V_SUS

PR416

@

1 2

100K_0402_1%~D

+1.05V_VCCP_P +1.05V_VCCP

Thermal Design Current: 10.8A
Peack current: 15.3A
OCP min: 16.4A

PL39

PC310

330U_D2E_2.5VM_R9

EN1

PR478

0_0402_5%~D

EN2

1 2

1.05V_RUN_PWRGD 42

1.5V_RUN_PWRGD 42

PJP39

1 2

PAD-OPEN 4x4m

PJP42

1 2

PAD-OPEN 4x4m

1

+

PC309

2

330U_D2E_2.5VM_R9

1.5V_RUN_ON 39

1.05V_RUN_ON 38

1

+

2

+1.05V_VCCP_P

12

PC311

10U_1206_6.3V7K

PC388

1 2

0.1U_0402_10V7K~D

+PWR_SRC

D D

1.5 Volt +/-5%
Thermal Design Current: 2A
Peak current: 2.8A
OCP min: 2.83A

C C

+1.5V_RUN_P

1

+

PC312

2

330U_D2E_2.5VM_R9

B B

+1.5V_RUN_P +1.5V_RUN

A A

DELL CONFIDENTIAL/PROPRIETARY

+1.5V_RUN / +1.05V_VCCP / +3.3V_ALW / +3.3V_RTC_LDO

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

THIS SHEET OF EN GINEE RING D RAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

4

3

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

+1.5V_RUN / +1.05V_VCCP

LA-3301P

1

47 58Monday, February 26, 2007

0.0

of

8

7

6

5

4

3

2

1

+CPU_PWR_SRC

H H

PQ42

PQ50

2

PQ57

2

8

D5D6D7D

G4S3S2S

1

IRF7821TRPBF_SO8~D

PHASE1

3

D

PQ56

G

S

FDS7088SN3_SO8~D

1

@

8

D5D6D7D

G4S3S2S

1

IRF7821TRPBF_SO8~D

3

D

2

IRF7821TRPBF_SO8~D

G

PQ60

G

S

FDS7088SN3_SO8~D

1

@

8

D5D6D7D

G4S3S2S

1

3

D

PQ61

S

FDS7088SN3_SO8~D

1

PC248

@

3

+CPU_PWR_SRC

PR228
10_0603_5%~D

12

PC180

0.01U_0402_25V7K~D

GNDA_VCORE

19

20

VSS

VDD

13K_0402_5%~D

4

VR_TT#

3

RBIAS

5

NTC

6

SOFT

PU11

VID0
VID1
VID2
VID3
VID4
VID5
VID6

DPRSTP#
DPRSLPVR

1

PSI#

2

PMON
CLK_EN#
VR_ON
VSEN
RTN

VDIFF

FB

9

COMP

8

VW
GND

DROOP

14

PR267

12

PC201

12

330P_0402_50V7K~D

PC411

4700P_0402_25V7K~D

1 2

+3.3V_RUN

PR234

1.91K_0603_1%~D

1 2

39

40

18

VIN

3V3

PGOOD

27

PWM1

23

ISEN1

26

PWM2

22

ISEN2

ISL6260CCRZ_QFN40~D

24

FCCM

25

PWM3

21

ISEN3

7

OCSET

17

VSUM

DFB15VO

16

PR263

4.53K_0402_1%~D

VO

PR268

1K_0402_1%~D

12

12

PC412

@

4700P_0402_25V7K~D

GNDA_VCORE

12

PC191

2

1

@

VSUM

2

1

0.33U_0603_10V7K

PC229

0.01U_0402_16V7K~D

PC260

0.1U_0402_16V7K~D

6

IMVP_PWRGD 23,39,42

PR508

@

226K_0402_1%~D

PR260

11.5K_0402_1%~D

PR261

PC215

1 2

2.43K_0402_1%~D

0.033U_0402_16V7K~D

1

12

2

PH2

12

GNDA_VCORE

12

12

12

PR480

@

0_0402_5%~D

12

PR266

15K_0402_1%~D

6.8KB_0603_5%_ERTJ1VR682J~D

1

2

PC392

@

0.1U_0402_16V7K~D

G G

+5V_ALW

PR233

1 2

10_0603_5%~D

PC182

1U_0603_10V6K~D

GNDA_VCORE

IMVP6_PROCHOT#38

PH1

12

12
12
12
12

12

CLK_ENABLE#

PR509 0_0402_5%~D

12

12

12

12

PR287

0_0603_5%~D

12

PR487

0_0402_5%~D

12

PR259

PC197

12

12

12

12

12

12

PR516

PC413

GNDA_VCORE

7

PR290

0_0603_5%~D

12

1K_0402_1%~D

1

2

0.01U_0402_16V7K~D

12

PR485

@

28
29
30
31
32
33
34

37
36

38
35
12
13

11

10

41

GNDA_VCORE

10.5K_0402_1%

12

@

F F

E E

GNDA_VCORE

H_DPRSTP#8,10,22

DPRSLPVR10,23

H_PSI#8

D D

PWR_MON18

PC391

1U_0603_10V6K~D

GNDA_VCORE

RUNPWROK38,39,42

IMVP_VR_ON39

10KB_0603_1%_ERTJ1VG103FA~D

C C

B B

@

A A

GNDA_VCORE

0_0402_5%~D

2200P_0402_50V7K~D

0.015U_0402_16V7K~D

VID08
VID18
VID28
VID38
VID48
VID58
VID68

PR252

10K_0402_5%~D

1 2

12

PH3

@

PR486

12

4.99K_0402_1%@

VSSSENSE8

PR257

332_0402_1%~D

220P_0402_50V8J~D

12

PR481

0_0402_5%~D

8

PR238

147K_0402_1%~D

12

PR284

@

12

PC409

@

12

PC187

12

PR240

0_0402_5%~D

PR242

0_0402_5%~D

PR244

0_0402_5%~D

0_0402_5%~D

12

@

0_0402_5%~D

PR254 0_0402_5%~D@

GNDA_VCORE

1 2

12

PC190

680P_0402_50V7K~D

1 2

PC250

1500P_0402_50V7K~D
PC195

1 2

@

470KB_0402_5%_NCP15WM474J03RB~D

PR239

0_0402_5%~D

12

PR241

0_0402_5%~D

12

PR243

0_0402_5%~D

12

PR245

0_0402_5%~D

PR248

PR249

499_0402_1%~D

12

PR479

12

12

VCCSENSE8

PC213 1000P_0402_50V7K~D

PC214 1000P_0402_50V7K~D

PR512
0_0402_5%~D

PR258

1.69K_0402_1%~D

82.5K_0402_1%~D

1000P_0402_50V7K~D

PR264

6.34K_0402_1%~D

+5V_ALW

12

PC178

1U_0603_10V6K~D

12

PR482

@

5

12

12

PWR_MON 18

30K_0402_5%~D

PU10

5

VCC

6

FCCM

2

PWM

3

GND

ISL6208CRZ-T_QFN8~D

+5V_ALW

PC241

1U_0603_10V6K~D

5

VCC

6

FCCM

2

PWM

3

GND

ISL6208CRZ-T_QFN8~D

+5V_ALW

PC196

PU13

5

VCC

1U_0603_10V6K~D

6

FCCM

2

PWM

3

GND

ISL6208CRZ-T_QFN8~D

PU16

PR229

0_0603_5%~D

1

BOOT
UGATE
PHASE
LGATE

UGATE

BOOT
UGATE
PHASE
LGATE

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONF IDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVIS ION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INF ORMATION IT CONT AINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WR ITT EN CO NSE NT OF COMPAL ELECTRONICS, INC.

BOOT

PHASE
LGATE

8
7
4

PR328
0_0603_5%~D

1
8
7
4

PR262

0_0603_5%~D

1
8
7
4

UGATE1

UGATE3

0.22U_0603_10V7K~D

1 2

12

LGATE1

0.22U_0603_10V7K~D

12

1 2

UGATE2

LGATE2

PC198

0.22U_0603_10V7K~D

1 2

12

LGATE3

4

PC179

PC242

12

12

12

PC249

PC223

0.1U_0603_25V7K~D

0.1U_0603_25V7K~D

10K_0402_1%~D

12

PC246

1500P_0603_25V7K~D

12

PC247

1500P_0603_25V7K~D

PHASE3

12

1500P_0603_25V7K~D

1 2

PR231

7.68K_0805_1%~D

1 2

VSUM

12

12

PC239

PC240

0.1U_0603_25V7K~D
2200P_0402_50V7K~D

PHASE2

+CPU_PWR_SRC

0.45UH_ET QP4LR45XFC_25A_20%~D

10K_0402_1%~D

1 2

PR270

7.68K_0805_1%~D

1 2

VSUM

PC176

PC224

2200P_0402_50V7K~D

PL29

0.45UH_ETQP4LR45XFC_25A_20%~D

4
3

PR230

0.22U_0603_10V7K~D

+CPU_PWR_SRC

12

PC271

PC177

10U_1206_25V6M~D

0.45UH_ET QP4LR45XFC_25A_20%~D

PR330

10K_0402_1%~D

1 2

PR331

7.68K_0805_1%~D

1 2

VSUM

12

12

PC272

PC193

10U_1206_25V6M~D

10U_1206_25V6M~D

PL31

1
2

PR269

0.22U_0603_10V7K~D

FBMA-L18-453215-900LMA90T_1812~D

12

12

PC380

PC270

10U_1206_25V6M~D

10U_1206_25V6M~D

1
2

PC181

12

12

10U_1206_25V6M~D

PL33

1

4
3

2

PC243

0.22U_0603_10V7K~D

12

12

12

PC227

PC228

0.1U_0603_25V7K~D
2200P_0402_50V7K~D

4
3

PC200

1 2

12

12

VO

DELL CONFIDENTIAL/PROPRIETARY

Title

Size Do c um e n t N u mb er Re v

Date: Sheet

2

PL44

@

1 2

PJP30

1 2

1

+

PAD-OPEN 4x4m

PJP31

2

100U_25V_M~D

1 2

PAD-OPEN 4x4m

Iccmax=44A
I_TDC=35A
OCP=65A, Intel spec=50A

+VCC_CORE

PR232
10_0402_1%~D

1 2

12

PR513
0_0402_5%~D

VO

+VCC_CORE

PR329
10_0402_1%~D

1 2

12

PR514
0_0402_5%~D

VO

+VCC_CORE

PR271
10_0402_1%~D

PR515
0_0402_5%~D

Compal Electronics, Inc.

+VCORE
LA-3301P

+PWR_SRC

48 58Monday, February 26, 2007

1

0.0

of

5

+DC_IN discharge path

4

3

2

1

0.01_2512_1%~D

4
3

12

10_0402_1%~D

PR472

PC383

1 2

0.22U_0402_6.3V6K

27

28

NC

CSSP

ISL88731_TQFN28~D

PC258

0.01U_0402_25V7K~D

THIS SHEET OF EN GINEE RING D RAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

26

VCC

CSSN

BOOT

VDDP

UGATE
PHASE

LGATE

PGND

CSOP

CSON

VFB

NC

12

GNDA_CHG G N DA_CHG GNDA_CHG

PR275
0_0603_5%~D

25

1 2

ISL88731_VDDP

21

24

PR360

23

0_0603_1%~D

12

@

220P_0402_50V7K~D

20

19
18

17
15
16

+5V_ALW +3.3V_ALW

12

PR366

100K_0402_1%~D

12

PC259

@

10P_0402_50V8J~D

3

PU8

22

DCIN

2

ACIN

13

ACOK

11

VDDSMB

10

SCL

9

SDA

14

NC

8

ICM

6

VCOMP

5

NC

4

ICOMP

3

VREF

7

NC

12

GND

29

GND

PR365

GNDA_CHG

4

G

O

P

8

1
2

1

PU19A
LM393DR_SO8~D

1

12

PC257

100P_0402_50V8K

+DC_IN_SS

D D

C C

B B

A A

0.01U_0402_25V7K~D

GNDA_CHG

Vin Detector
High 17.9 V
Low 17.24 V

12

PC99
10U_1206_25V6M~D

PR143

49.9K_0402_1%~D

12

PC110

12

THRM_SMBCLK18,39

THRM_SMBDAT18,39

PR142
215K_0402_1%

1 2

5

ISL88731_VDDP

PR149

ACAV_IN18,39,50

PR341

+5V_ALW

PC221

0.1U_0402_10V7K~D

GNDA_CHG

ADAPT_TRIP_SET38

12

10K_0402_1%~D

12

15.8K_0402_1%~D

@

12

12

PR150

16.2K_0402_1%~D

ISL88731_ICM

12

PC121

@

0.1U_0402_10V7K~D

1 2

8.45K_0402_5%~D

@

33.2K_0402_1%~D

1 2

PR146

1 2

0_0402_5%~D

12

12

PR148

PC212

2.2K_0402_5%~D

@

12

0.01U_0402_25V7K~D

PC118

0.01U_0402_25V7K~D

ISL88731_VREF

PR361

PR475

12

PC254

0.1U_0402_25V7K~D

GNDA_CHG GN DA_CHG

GNDA_CHG

PC102

1U_0805_25V4Z~D

12

GNDA_CHG

12

PC119

0.01U_0402_25V7K~D

@

12

PR362

57.6K_0402_1%~D

12

PR363

12

13K_0402_1%

PC393

12

0.01U_0402_25V7K~D

GNDA_CHG G NDA_CHG GNDA_CHG GNDA_CHG

PR364

GNDA_CHG

105_0402_1%~D

4

ISL88731_ICM

ISL88731_VREF

12

PC122

1U_0603_10V6K~D

PC255

100P_0402_50V8K

GNDA_CHG

12

12

PC120

@

0.1U_0402_10V7K~D

1M_0402_1%~D

1 2

2

IN-

3

IN+

12

PC256

100P_0402_50V8K

+5V_ALW

PJP62

1 2

PAD-OPEN 4x4m

12

PC203

@

0.1U_0603_25V7K~D

12

PC253

CHG_LGATE

PR368

1 2

0_0603_5%~D

12

PR367

100K_0402_5%~D

13

D

2

G

S

PQ81
RHU002N06_SOT323

@

PC202

1U_0603_10V6K~D

1 2

PR274
33_0603_1%~D

1 2

PD40

PC204

1U_0603_10V6K~D

2 1

RB751V_SOD323~D

1 2

CHG_UGATE

+VCHGR

PR474

@

12

12

PC127

PC128

@

0.1U_0603_25V7K~D

2200P_0402_50V7K~D

GNDA_CHG

@

1 2

GNDA_CHG

12

GNDA_CHG GN DA_CHG

PAD-OPEN1x1m

ADAPT_OC 38

1K_0402_5%~D

+SDC_IN

PR138

PC267

PJP65

5
6

12

3300PF_0402_50V7K~D

+5V_ALW

IN+
IN-

578

3 6

8

P

G

4

O

CHAGER_SRC

241

4

PQ75

SI4800BDY-T1_SO8~D

+VCHGR_B

8

D6D5D7D

G

S

S

S

3

2

1

7

PU19B
LM393DR_SO8~D

2

578

PQ79

SI4800BDY-T1_SO8~D

3 6

241

PL20

+VCHGR_L

5.6U_HMU1356-5R6_8.8A_20%~D

PQ76

SI4810BDY-T1-E3_SO8~D

12

Maximum charging current is 6.24A

10U_1206_25V6M~D

12

12

PC106

10U_1206_25V6M~D

+VCHGR

12

PC112

0.1U_0603_25V7K~D

12

12

PC114

PC113

10U_1206_25V6M~D

10U_1206_25V6M~D

PC379

10U_1206_25V6M~D

PD54

@

PR373

@

1K_0603_1%~D

12

PC103

2200P_0402_50V7K~D

12

10_0402_1%~D

PR473

12

12

PC104

0.1U_0603_25V7K~D

PR145

0.01_2512_1%~D

1
2

PC384

0.22U_0402_6.3V6K

1 2

PC105

4
3

DELL CONFIDENTIAL/PROPRIETARY

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

Charger
LA-3301P

49 58Monday, February 26, 2007

1

of

+5V_ALW

21

1SS355_SOD323~D

12

0.0

5

4

3

2

1

+DC_IN discharge path

PQ62

SI4835BDY-T1-E3_SO8~D

8

D D

PQ65

8
7

+VCHGR

CHG_SBAT_N

13

D

PQ67

CHG_SBATT38

C C

CHG_PBATT38

2

G

G

2

+VCHGR

RHU002N06_SOT323

S

S

RHU002N06_SOT323
PQ68

D

1 3

CHG_PBAT_N

6
5

PR309

10K_0402_5%~D

PR312

10K_0402_5%~D

5
7

8

CHG_SBAT

1

D2

S2

CHG_SBATT_N

2

G2

D2

3

S1

D1

4

D1

G1

FDS4935BZ_SO8~D

100K_0402_5%~D

12

0.1U_0603_25V7K~D

CHG_SBATT_N

0.1U_0603_25V7K~D

1 2

100K_0402_5%~D

12

PQ71

4

SI4835BDY-T1-E3_SO8~D

PR310

PC234

1 2

PC235

PR313

36
2
1

12

CHG_PBATT_N

12

CHG_PBAT

ACAV_IN18,39,49

PQ72

4

SI4835BDY-T1-E3_SO8~D

3 6
2
1

PBATT+

5
7

8

SBATT+

@

100K_0402_5%~D

+SDC_IN

2

PR308

G

12

PQ69

SI4835BDY-T1-E3_SO8~D

1
2
3 6

4

13

D

PQ63
RHU002N06_SOT323

S

8
7

5

PR305

10K_0402_5%~D

2

G

2
3

1 2
13

D

S

PD48

RB715F_SOT323

7
5

PR306

10K_0402_5%~D

PQ64
RHU002N06_SOT323

2 1

SI4835BDY-T1-E3_SO8~D

8
7

5

SBAT_G

1

B540C~D

2 1

SI4835BDY-T1-E3_SO8~D

8
7

5

12

PD47

B540C~D

PQ66

PR311

PD49

PQ70

4

4

1 2

33K_0402_5%~D

4

1
2
36

PR307

100K_0402_5%~D

1
2
36

1
2
36

12

+PWR_SRC

12

PC232

PC233

2200P_0402_50V7K~D

+PWR_SRC

1

12

+

PC382

2

100U_25V_M~D

0.1U_0603_25V7K~D

1

+

PC381

2

100U_25V_M~D

PR316

12

47K_0402_1%~D

PR314

PR315

470K_0402_5%~D

B B

PR319

SBATT+

PR321

1 2

8

P

G

4

PC237

0.1U_0603_25V7K~D

7

O

LM393DR_SO8~D
PU14B

147K_0402_1%~D

1 2

PD51

1

RB715F_SOT323

2
3

PBATT+

PC236

1 2

+3.3V_ALW

PU15

5

TC7SH32FU_SSOP5~D

2

A A

PBAT_DSCHG38

SBAT_PRES#38,44

5

P

I0

O

1

I1

G

3

@

4

RHU002N06_SOT323

2

PQ74

0.1U_0603_25V7K~D

13

D

G

S

PR323

1 2

42.2K_0402_1%~D
PR324

10K_0402_5%~D

1 2

1 2

PR325

100K_0402_5%~D

PR326

1 2

32.4K_0402_1%~D

+3.3V_ALW

4

5

IN+

6

IN-

47K_0402_1%~D

1 2

PR322

100K_0402_5%~D

1 2

+3.3V_ALW

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

1 2

PBATT+

8

3

IN+

2

IN-

4

3

470K_0402_5%~D

PU14A
LM393DR_SO8~D

P

1

O

G

PR320

1 2

12

470K_0402_5%~D

PR317

10K_0402_5%~D

2

G

12

13

D

PQ73
RHU002N06_SOT323

S

PD50

2
3

RB715F_SOT323

2

PBAT_G

1

PR318

1 2

33K_0402_5%~D

DELL CONFIDENTIAL/PROPRIETARY

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

Selector
LA-3301P

50 58Wednesday, February 28, 2007

1

0.0

of

5

4

3

2

1

D D

L77

C C

+1.8V_RUN

B B

DVI_SCLK
DVI_SDATA

R253

5.23K_0402_1%~D

SDVO_CTRLCLK

A A

SDVO_CTRLDATA

16.5K_0402_1%~D

R812

5

12

12

12

+3.3V_RUN

+5V_RUN

12

R719

2.2K_0402_5%~D

12

R254

5.23K_0402_1%~D

12

R813

16.5K_0402_1%~D

+3.3V_RUN

BLM18PG181SN1_0603~D

R720

2.2K_0402_5%~D

SDVO_CTRLCLK, SDVO_CTRLDATA
level is 2.5V

BLM18PG181SN1_0603~D

L81

12

+VCC

1

C990
10U_0805_10V4Z~D

2

12

SDVOB_INT+12
SDVOB_INT-12

SDVOB_RED+12
SDVOB_RED-12

SDVOB_GREEN+12
SDVOB_GREEN-12

SDVOB_BLUE+12
SDVOB_BLUE-12

+AVCC

DVI_DETECT36

4

+AVCC

1

C975

2

10U_0805_10V4Z~D

+3.3V_RUN

1

C991

0.1U_0402_16V4Z~D

2

SDVOB_CLK+12
SDVOB_CLK-12

+AVCC

1

1

2

C977

C976

2

@

@

100P_0402_50V8J~D

1000P_0402_50V7K~D

1

C980

0.1U_0402_16V4Z~D

2

1

C992

0.1U_0402_16V4Z~D

2

C994 0.1U_0402_10V7K~D

1 2
1 2

C999 0.1U_0402_10V7K~D

PLTRST1#10,21

12

R721 220_0402_5%~D

1 2

R412
0_0402_5%~D

1K_0402_5%~D

1

C978

2

0.1U_0402_16V4Z~D

1

C993

0.1U_0402_16V4Z~D

2

INT+
INT-

SDVOB_RED+
SDVOB_RED-

SDVOB_GREEN+
SDVOB_GREEN-

SDVOB_BLUE+
SDVOB_BLUE-

+VSWING

12

R724

2

C979

0.1U_0402_16V4Z~D

1

1

C981
10U_0805_10V4Z~D

2

U47

32
33

37
38

40
41

43
44

46
47

2

25
35

30
29

SDI+
SDI-

SDR+
SDR-

SDG+
SDG-

SDB+
SDB-

SDC+
SDC-

RESET#
EXT_SWING

EXT_RES
TEST

HTPLG

DVI_TX2-

DVI_TX2+

DVI_TX1-

DVI_TX1+

DVI_TX0-

DVI_TX0+
DVI_CLK-

DVI_CLK+

34

28

VCC10VCC

VCC

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

1

AVCC15AVCC21SVCC36SVCC

OVCC

PGND2

GND

GND31SGND39SGND

AGND18AGND

7

27

24

42

48

SPVCC

SPGND

AGND

3

12

45

C968

12

0.1U_0402_16V4Z~D

C969

12

0.1U_0402_16V4Z~D

C970

12

0.1U_0402_16V4Z~D

C971

12

0.1U_0402_16V4Z~D

1

C972

0.1U_0402_16V4Z~D

2

1

1

C982

2

2

10U_0805_10V4Z~D

26

11

13

TXC-

PVCC2

PVCC1

14

TXC+

16

TX0-

17

TX0+

19

TX1-

20

TX1+

22

TX2-

23

TX2+

9

SDADDC

8

SCLDDC

5

SDSCL

4

SDSDA

6

A1

SII1362ACTU_LQFP48~D

C983

@

1000P_0402_50V7K~D

DVI_CLK­DVI_CLK+

DVI_TX0­DVI_TX0+

DVI_TX1­DVI_TX1+

DVI_TX2­DVI_TX2+

2

1

1 2

1 2

1 2

1 2

+SVCC

C973

0.1U_0402_16V4Z~D

+SPVCC

1

1

C984

C985

2

2

@

100P_0402_50V8J~D

0.1U_0402_16V4Z~D

DVI_SDATA 36

DVI_SCLK 36

SDVO_CTRLCLK 10

SDVO_CTRLDATA 10

1 2

R722 1K_0402_5%~D@

R723

1K_0402_5%~D

1 2

R715
110_0402_1%~D

R716
110_0402_1%~D

R717
110_0402_1%~D

R718
110_0402_1%~D

L78
BLM18PG181SN1_0603~D

1

C974
10U_0805_10V4Z~D

2

L79
BLM18PG181SN1_0603~D

+PVCC1

1

1

C986

2

2

@

10U_0805_10V4Z~D

+PVCC2

1

1

C995

2

2

@

10U_0805_10V4Z~D

+3.3V_RUN

A1 LOW: Address = 0x70

HIGH: Address = 0x72

2

DVI_TX2- 36

DVI_TX2+ 36

DVI_TX1- 36

DVI_TX1+ 36

DVI_TX0- 36

DVI_TX0+ 36
DVI_CLK- 36

DVI_CLK+ 36

12

1

C987

2

100P_0402_50V8J~D

1

C996

2

100P_0402_50V8J~D

12

C988

@

1000P_0402_50V7K~D

C997

@

1000P_0402_50V7K~D

+1.8V_RUN

+3.3V_RUN

L80
BLM18PG181SN1_0603~D

1

C989

0.1U_0402_16V4Z~D

2

L82
BLM18PG181SN1_0603~D

1

C998

2

12

12

0.1U_0402_16V4Z~D

DELL CONFIDENTIAL/PROPRIETARY

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

Internal LVDS

LA-3301P

51 58Monday, February 26, 2007

1

1.0

of

5

4

Version Change List ( P. I. R. List )

3

2

1

Item Issue DescriptionDate

D D

08/2/200638 HW Compal BID change to X01 Pop R108, depop R106 X01

Owner

HW18 X01Change Q102, to SOT323 packageChange SOT23 package to SOT323 packageCompal08/10/20062

73 08/21/2006 Compal BITS issue WI86517 (S5 state back driver issue) Change R324 pin1 connect from +3.3V_ALW to +3.3V_SUS

4 08/21/2006 Compal Bits issue WI84312 (Derating issue) Change R151 from 30 ohm to 75 ohm

41

5 23 08/21/2006 Compal Bits issue WI86509

6 12 08/21/2006 Compal Bits issue WI86510

739

HW

HW

HW X01

HW X01

Populate R761 and change value from 100k to 10k.
Change R761 pin1 connect from +3.3V_ALW to +3.3V_SUS
Remove R390, R393. Connect LCTLA_CLK and LCTLB_DATA to
GND

08/21/2006 Compal Bits issue WI86511 Add R401 (100K) for signal BC_DAT pull up to +3.3V_ALWHW X01

8 Bits issue WI86512Compal08/21/200637

C C

9 23 08/21/2006 Compal Bits issue WI86516

10 08/21/2006 Compal Bits issue WI86518

11 08/21/2006

12 X01Change pull-up rail for R773 from +5V_SUS to +3.3V_SUSHW18

13 21 HW

14 21 HW X01

15 39 HW X01

HW X01

HW X0138,39

Compal Bits issue WI86531 Move BEEP (ECE5018 GPIOB[6]) to SGPIO46 of MEC502538,39 HW X01

Bits issue WI86752Compal08/21/2006

08/30/2006 Compal Bits issue WI86530

09/7/2006 Compal Bits issue WI86529

09/7/2006 Compal

Bits issue WI86376. Due to increase in number of
payloads the BIOS is carrying

R509 PU for SIO_EXT_SMI# change from +3.3V_ALW to
+3.3V_SUS to prevent backdrive through the ICH in S4/S5
Swap PSID GPIO from ECE5018 pin 71 with MEC5025
ITP_DBRESET#/HDT_RESET# pin 55

Move SB_NB_PCIE_RST# to GPIO4/PIRQG# pinF12 per M08
design, add R631 (20K ohm) for pull down
Move SB_WLAN_PCIE_RST# to GPIO3/PIRQF# U32 pin G11 per
M08 direction, add test point T1 on pin F18
Change U23 from ( ST M25P80 8M bit ) to ) MXIC
MX25L1605AM2C 16M bit )
Change Q5 to MMBT3906WT1G, R15 to 150 ohm. Add R638 on

16 43 Compal Bits issue WI90535 X01HW

B B

09/11/2006

LED_WLAN_OUT# pull up to +3.3V_WLAN. Add R639 (10K ohm)
in series on LED_WLAN_OUT#

09/14/2006 Remove ITP port and just keep ITP test point 17 7 Compal Briscoe ESD/EMI Improvement Requests on PT X01HW

Solution Description Rev.Page#1Title

X01

X01

X01Change R131 to no-stuff and from 4.7k to 100k per SMSC HW

X01

Request

18 43 HW 09/14/2006 X01Remove R73, R178, C192, and C193Compal Bits issue WI90709

19 34 HW 09/14/2006 X01

Compal Bits issue WI90705

Add SMBus isolation circuit for WLAN,
R640,R645,R660,R662,Q45,Q46

20 34 HW 09/14/2006 JMINI1 connect to +3.3V_RUN. Removed C427 X01Compal Bits issue WI90691

21 12 HW 09/14/2006 X01

Compal Shunt caps on LVDS for improving WWAN

Add C181,C192,C193,C196,C207,C209,R667,R685,R686,
R687,R688 cross LVDS signals

22 27 HW 09/14/2006 Compal Bits issue WI90516 Remove C759 from mic amp bias circuit X01

2623 Populate R541to cut BEEP level in halfBits issue WI9048709/14/2006 CompalHW X01

24 43 09/14/2006 Compal Bits issue WI89631

A A

HW X01

populate EMI Clips Clip1, Clip2, Clip3, Clip4, Clip5,
Clip6

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

Changed-List History

LA-3301P

52 58Wednesday, February 14, 2007

1

1.0

of

5

4

Version Change List ( P. I. R. List )

3

2

1

Item Issue DescriptionDate

D D

26 09/14/2006 Compal Bits issue WI89407 X01

25 HW

27 41 HW 09/14/2006

28 37,39 HW 09/14/2006

09/14/200623 HW Compal Bits issue WI89409

Owner

No stuff R516, add R690 (8.2K ohm) for pull up ICH8 pin
AF22 to +3.3V_SUS
Add Q68, Q69, R691, R692 for HDDC_EN and MODC_EN
circuits

Compal Bits issue WI89394 X01

Compal Bits issue WI89379 X01

Change connect R765 pin1, R623 pin1, R621 pin1, R766
pin1 from +5V_ALW to +5V_ALW2
Change R387,R389 from 1M to 2.7K. Add R778,R779 for
AUX_ON,AC_OFF

09/15/20063429

Change R730 from 100K to 4.7K ohm3930 X01Bits issue WI92249Compal09/15/2006HW

31 34 Bits issue WI92288,WI90714 X01HW 09/15/2006 Compal

32

C C

33,28,
19,20

HW 09/15/2006 Compal

EMI solutions Populate RS232 C152,153,154,155,156,157,158,159. Resume

R660 and R662 connected to CLK_SCLK and CLK_SDATA.

ICH_AZ_MDC_BITCLK C656,R123,C128. Add R790,R791,C232,
C267. Change L63,L65 from 0603size to 0805size. Add
C309,C316 for LOM. Add C427,C463 for LVDS. Add fuse F3,
R792 for CRT. Populate C660, R545 (10 ohm),C721 (10P)

33 23,36 HW Bits issue WI92298

Move SIO_EXT_SCI# from to ICH8 GPIO11/SMBALERT# pin AG22
to GPO12 pin AC19. Remove D22 and R761 and net DOCK_DET#
ICH8 Pin AG22 tie to LOM_ICH_SMBALERT#. Add R793 (0 ohm)
series on LOM_ICH_SMBALERT# and LOM_SMB_ALERT#. Change

2334

35

36 X01

37 X01

B B

38

39 HW 09/18/2006 Compal Bits issue WI92301

09/18/2006HW38,39 Bits issue WI92305Compal

39,42 HW 09/18/2006 Compal Bits issue WI92308

Compal39 HW 09/18/2006 X01Add R795 (0 ohm) pull down for MEC5025 pin 14Bits issue WI92312

Compal2939 X01

40

41

HW Compal6 09/20/2006 Bits issue WI93162

CompalHW27 X01Add R796,R797 (0ohm) between L47/L48 and C728/C730Bits issue WI9051009/19/2006

Compal09/20/20062842

43 38 X0109/20/2006 Compal

44 WWAN noise issue

19 09/20/2006 Compal X01

HW Bits issue WI92857 Add no-stuff series 0-ohm for ITP_DBRESET# on ECE5028

HW

Bits issue WI9229909/18/2006HW Compal

EMI issue09/19/2006HW

Bits issue WI92858HW

R730 pull up rail from +3.3V_ALW to +3.3V_LAN. Add R807
pull up to +3.3V_SUS for LOM_ICH_SMBALERT#

Move ALW_PWRGD_3V_5V from MEC5025 pin 18 to MEC5025
pin 29. Remove 3.3V_5V_SUS_PWRGD from MEC5025 pin 29
Swap DOCK_SMB_PME and DOCK_SMB_ALERT# from MEC5025 pin3
and ECE5028 pin76
Removed 3.3V_LAN_PWRGD from MEC5025 KSO15/GPIO5.
Remove U52,Q83,D29,R89,R98,R381,C784,C182,C183,C184

Populate R671~R678 and C866~C869. Change L69~L76 from
24NH to 36NH inductor

NC JITP pin 1,2,3,5,7,11,12,13,15,17,19,21,23. Add test
point T47~T52 for ITP_BPM#0~ITP_BPM#5. Remove R322
Change R669 to from 1.15K to 1.13K. Depop C771 & C772.
Change C861 and C862 to 22pF

Add R808,R809,R810,R811 series for LCD_DDCCLK,
LCD_DDCDATA, LCD_SMBCLK, LCD_SMBDAT

Remove R586 and make JMDC pin2 NCBits issue WI93157HW

A A

Solution Description Rev.Page#25Title

X01

X01No stuff C16Bits issue WI90698CompalHW

X0137,22,

X0109/18/2006 Compal

X01

X01

X01

X01

X01Compal09/21/20063345

Request

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

Changed-List History

LA-3301P

53 58Wednesday, February 14, 2007

1

1.0

of

5

4

Version Change List ( P. I. R. List )

3

2

1

Item Issue DescriptionDate

D D

47 HW Bits issue WI93586

51 09/22/2006 Compal X01

HW46 Bits issue WI93158 Depop Q45, Q4634 09/21/2006 Compal X01

Owner

Add R812,R813 (9.09K ohm) and chagne R253,R254 to 2.94K
ohm for SDVO_CTRLCLK /DAT voltage divider

HW C484 change to 33pF, C861/C862 change to 22pF Bits issue WI9340348

49 HW Bits issue DF86424 No Populate C866-C869/R671-R678

50 HW EMI request Add D37-D40 for stick point signals

51

52

53

C C

54 10/05/2006

56 9 X02

29 09/26/2006 Compal X01

40 09/26/2006 Compal X01

32 HW EMI request Add FUSE4,FUSE509/27/2006 Compal X01

18 HW Bits issue WI94892 Populate R771, C750, R772, Q102, R77310/05/2006 Compal X01

30 HW 10/05/2006 Compal Bits issue WI95910

38,23
12,27,6

HW Compal Bits issue WI95932

HW55 Dell10/14/2006 Bits issue WI97539

HW 10/17/2006 Dell Bits issue WI97840

HW 10/18/2006 Dell Bits issue WI98222 (Change for ASF2.0 due to ICH8M errata )2357

Change R603 from 6.2k to 5.9k.
Change C805 from 820pF to 270pF
No stuff R227, R221, C89, C93, C97, c401, C92, r72,
C90, C88. Change R369 to 3.3K 1%. No stuff C775-C781,
C785. No stuff R514 (no iAMT). Populate R515.

Added signal DOCK_DET# to JDOCKBpin137, pin205 and
Q3pin2
Add 0.1 uf (0402) caps on +Vcc_Core to Gnd. Four
total, bottom of board. (C870 ~ C873)

1. No stuff R502, R503

2. Connect the pad of R503.2 to the pad of R498.2

3. Connect the pad of R502.1 to the pad of R499.2

Board ID Changed to X02Dell10/24/2006HW3858 Populated R106, R107. Depopulated R108, R109. X02

HW 10/27/2006 Dell Bits issue WI100037. Intel CRT noise issue59 13

HW 10/30/2006 Dell60 23 Bits issue WI100049 X02

B B

Change L36 to 100 ohm resistor and change C722 to 22nF.
Replace C569 with a 0603 1uF cap
Add R816,C874 for USB_IDE#. R817,C875 for SIO_EXT_WAKE#.
R819,C876 for PCIE_MCARD1_DET#. R820,C878 for
USB_MCARD1_DET#. R818,C877 for USB_MCARD2_DET#. Remove
net RSVD_GPIO6 and R513

61 51 HW 11/2/2006 Dell Bits issue WI100826

62 28 HW 11/7/2006 Dell Bits issue WI102451

Change Change R812, R813 from 9.09K_1% to 13.7K_1%.
Change R253, R254 from 2.94K_1% to 4.32K_1%
Change L64,L66,L67,L68 from BLM18AG601SN1D to
BK1608LM182. Change R668 to L88 BK1608LM182.Change L63,
L65 from BLM21AG601SN1D to BK2125LM182. Chagne
C850,C852,C856,C858 to 47pF caps. Change C849 to 1000pF.
Populate C863, C864

63 6,23,34 HW 11/8/2006 Dell

64 2

HW 11/8/2006 Dell Correct Block diagram Correct block diagram X02

Bits issue WI103311

Change R309 from 8.2K to 2.2K. No stuff R820.
No stuff R550

Solution Description Rev.Page# Titl e

X01Compal09/25/20066

X01

X01

X0236

X02

X02

X02

X02

X02

Request

65 39

A A

HW 11/14/2006 Dell Bits issue WI103986 Change C379 from 22pF to 33pF per KDS X'tal report X02

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

Changed-List History

LA-3301P

54 58Wednesday, February 14, 2007

1

1.0

of

5

4

Version Change List ( P. I. R. List )

3

2

1

Item Issue DescriptionDate

D D

HW89 Bits issue WI125145.DPST enablement for UMA Populate R156 (0_0402_5%)19 2/28/2007 Compal A00

Owner

90 HW Bits issue WI125577 Populate R92. Depop R9339 3/1/2007 Compal A00

91 HW Bits issue WI125883 Add note "C533,C534,C536,C545,C553,C579 are being

13 3/1/2007 Compal A00

replaced by 0-ohm 0805 resistor" on page 13

92 HW Bits issue WI12729718 3/7/2007 Compal Populate R441 A00

93 27 HW A00Change U40 from 74AHC1G08 to 74AHCT1G083/7/2007 Dell Bits issue WI127300

C C

Solution Description Rev.Page# Titl e

Request

B B

A A

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

Changed-List History

LA-3301P

55 58Wednesday, March 07, 2007

1

1.0

of

5

4

Version Change List ( P. I. R. List )

3

2

1

Item Issue DescriptionDate

D D

69 Bits issue WI100826

70 Bits issue WI106999

25,41 11/20/2006 Compal X03

HW66 Bits issue WI105207

38,39 HW 11/21/2006 Dell

51 HW 12/1/2006 Dell X03

21,23,34

HW 12/1/2006 Dell X03

Owner

Change net name from +5V_ALW2 to +3.3V_ALW2 at R618.1,
R626.1, R623.1, R621.1, R766.1, R765.1

Bits issue WI105754

Dell11/21/2006HW26 X03

Bits issue WI105758. Updates for potential Back Drive 68

Change R794 pin1 from +5V_ALW to +3.3V_ALW.
Change R245 pin1 from +3.3V_ALW to +5V_ALW
Add 100kohm resistor R721 between U35 pin 40 and
+3.3V_RUN and 1000pF cap C759
Change R253, R254 from 2.94K_1% to 5.23K_1%.
Change R812, R813 from 9.09K_1% to 16.5K_1%
Please populate R820 with a 4.7k-ohm resistor. Move
signal PCIE_MCARD2_DET# from ICH8m GPIO20 pinAE11 to
PIRQH#/GPIO5 pinB3. Delete R457 and net
ICH_GPIO5_PIRQH#. Populate R550

41 HW Populate C208

12/1/2006 Dell X0371 Bits issue WI107466. +2.5V_LAN in-rush current test fai.

72 27 HW 12/6/2006 Dell Bits issue WI107896 Change R554 from 10K to 0 ohm X03

C C

HW 12/6/2006 Dell74 9 Bits issue WI108223

Dell12/6/2006HW36,3873 X03Change net DOCK_SMB_PME to DOCK_SMB_PME#Bits issue WI108259. Per M08 GPIO map rev A15 Change list

Change C177,C179,C178,C366,C338,C365 to
EEFSX0D221E7 220uF

HW75 38 12/11/2006 Dell Change Board ID from X02 to X03 Populate R108, Depop R106 X03

Bits issue WI110179Dell12/14/2006HW3976 X03

77 27 HW 12/15/2006 Dell Bits issue WI110158

Add EC_FLASH_PAD pin1 connect to +3.3V_ALW,pin2 connect
to R76 pin1 and R80 pin1
Add R822 (1M_0402) from Pin 10 (C1P) pin of MAX9789A
to ground

78 13,14 HW 12/15/2006 Dell Bits issue WI109712 Change C544,C560,C615,C551,C564,C593 to X6S SPEC X03

79 26 HW 12/18/2006 Dell Bits issue WI110749

80 29 HW 12/20/2006 Dell Bits issue WI111288

B B

12,23
28

Dell12/25/200681 X03

Change AC Coupling Cap SPEC for PCIEHW

Add R823 (10K_0402) to ground on pin 47 of STAC9205
(U37)
Change R683 from 150ohms to 110 ohms, R684from
150ohms to 200ohms
Change C500~C507,C664,C666~C670,C851,C853,C994,C999
from 0.1uF Y5V to 0.1uF X7R

Dell82 1/26/2007 Bits issue WI115658. M08 GPIO map rev A16 change Change ECE5028 GPIOF4 from BID2 to CHIPSET_ID. A0038 HW

Solution Description Rev.Page# Titl e

X0367

X03

X03

X03

X03

Request

83 1/26/2007 Dell Change BID to from X03 to A00 A00Depop R107,R108. Populate R106,R10938 HW

84 2/12/2007 Dell Bits issue WI121957 A0023 HW Add R834 (1M_0402_1%) for ICH_LAN_RST#

85 27 2/12/2007 Dell Bits issue WI121438 A00HW Change R565 from 10K to 100k ohm

A00Bits issue DF116813Dell2/12/20074186 Depop C194, changed C815 from 4700pF to 2200pFHW

13 2/27/2007 Dell Bits issue WI109712. Because can't find 2nd source A0087 HW Change C560 and (C615, C551, C564) Back to X5R

23 2/27/2007 Dell88 HW Bits issue WI125173. Per Intel's latest recommendation Change R834 from 1M to 10K A00

A A

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

Changed-List History

LA-3301P

55 58Wednesday, February 28, 2007

1

1.0

of

5

4

Version Change List ( P. I. R. List )

3

2

1

Item Issue DescriptionDate

D D

C C

10

B B

11

48/50 Elick change the AL CAP to 2000hr

1 0.1

2PWR

3PWR

4PWR

5

6

7

45

48

44

44 PWR

46 remove PR437, PR438, PR441, PQ93 and PQ94.

45 PWR DELL

8

9

45 PWR DELL

47

47 PWR 9/14 DELL

Title

PWR

9/14

9/14

9/14

9/14

9/14

9/14

9/14

9/14

9/14

Owner

DELL

DELL

DELL

DELL

DELLPWR

DELLPWR45

BITS-WI91007
change to correct part for 15ALW.

change to PSL of DELL

change to PSL of DELL

change to PSL of DELL

BITS-WI89364
The 0.9V_DDR_VTT_PWRGD net is not used at
the MEC5025.
The 0.9V_DDR_VTT_PWRGD net should be no
connect at the MEC5025 pin 73.

BITS-WI90985
following DELL rule

BITS-WI90999
Change PQ83 from FDS8880 to
BSC079N03SG PPAK

BITS-WI91012
change to correct current limits

BITS-WI91287
following DELL rule

BITS-WI91288
Change PQ86 from SI4392DY to SI4682DY.

change PC380 from SF10004M08L to SF000000S8L.
change PC381 from SF10004M08L to SF000000S8L.
change PC382 from SF10004M08L to SF000000S8L.

change PD55 from SCSB717F08L to SCS00001U8L.
change PD56 from SCSB717F08L to SCS00001U8L.

change PH2 from SL20000030L to SL200000F8L

change PL1 from SM01001680L to SM010008U0L.

change PL2 from SM01001418L to SM010009C8L.
change PL34 from SM01001418L to SM010009C8L.

Change PC285 pin 2 pad connection
from PGND to AGND.

Change PQ83 from SB000004U8L to SB000004D8L.

Change PR383 from 124k(SD03412438L) to
150K(SD03415038L).
Change PR382 from 187k(SD03418738L) to
226K(SD03422638L).

Depopulate PR415 and PR416 resistors.DELL9/14PWR

change PQ86 from SB54392008L to SB000006N0L

Solution Description Rev.Page#

0.1

0.1

0.1

0.1

0.1

0.1

0.1

0.1

0.1

0.1

Request

12

13

14

46 PWR 9/14 DELL

15

A A

DELL9/14PWR49

DELL9/14PWR47

DELL9/14PWR44

BITS-WI91291
be compliant with the reference schematic.

BITS-WI91374
following DELL rule

BITS-WI91672
Change in 1.25V_RUN_PWRGD circuit.

BITS-WI91689
DC IN schematic changes.

Change PR274 from 4.7 ohm(SD000006T8L) to 33 ohm(SD014330A8L).
Populate PR373 and PD54.

Change PR408 from 75K(SD03475028L) to 82.5K(SD00000278L).

Change the node name connected to pin 2 of PR431from +3.3V_ALW
to +3.3V_SUS.
Depopulate PR431.

Change PL1 from SM01001680L to SM010008U0L.
Change PQ100 from SI2301BDS(SB923010020) to
PQ100A depopulated IMD2A(SB000009N8L).
Change PQ101 from SI2301BDS(SB923010020) to
PQ100B depopulated IMD2A(SB000009N8L).
Change PR12 from 10K,0603(SD01310028L) to 4.7K,0805(SD00247018L).

0.1

0.1

0.1

0.1

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Changed-List History 1

Size Document Number Rev

Date: Sheet

LA-3301P

1

56 58Wednesday, February 28, 2007

of

0.6

5

4

Version Change List ( P. I. R. List )

3

2

1

Item Issue DescriptionDate

D D

16 PWR

17 PWR

18 PWR

19

C C

20

21

46 9/15 DELL BITS-WI92156

46 9/15 DELL

46 9/15 DELL

48

44

48/50

PWR

PWR

PWR

9/18 DELL

9/21 DELL

9/21 DELL

Owner

correct the current limit on 1.25V
output

BITS-WI91655
Add 0.1uF connected to the pins 1 and 2
of PU24

BITS-WI91929
correct the current limit on 1.8V
output

BITS-WI92465
improve transients at load dump.
and reduce jittering.

BITS-WI91689
change PL1 from BK1608HM to BLM18BD102SN1D.

BITS-WI87563
change populate PC380 from 25CE100AX
to 25CE100LS
change PC381 from 25CE100AX to 25CE100LS
change PC382 from 25CE100AX to 25CE100LS

change PR425 from 39.2K(SD03439228L) to 51.1K (SD03451128L)

Add PC410(SE042104K8L). One pad connected to the pins 1 and 2 of PU24 .
The other pad is connected to PGND.

change PR426 from 110K(SD03411038L) to 130K (SD03413038L) 0.1

Add depopulate PR516(SD03410018L) and depopulate PC413(SE076103K8L)
between pin 9 of PU11 and AGND.
Add depopulated PC411(SE075472K8L),4700pF between pin 14 of PU11 and AGND .
Add depopulated PC412(SE075472K8L),4700pF between pin 15 of PU11 and AGND

change PL1 from SM010008U0L to SM010007C8L.

change populate PC380 from SF000000S8L to SF000000T8L.
change PC381 from SF000000S8L to SF000000T8L.
change PC382 from SF000000S8L to SF000000T8L.

Solution Description Rev.Page# Titl e

0.1

0.1

0.1

0.1

0.1

Request

22

B B

23

24

25

26

27

A A

28

49

49

49

49

48

45,46,47

PWR

PWR

PWR

PWR

PWR

PWR

PWR

5

9/29

9/29

9/29

9/29

DELL

DELL

DELL

DELL

10/27 DE LL

10/3146

DELL BITS-WI100140

match Maxim's response time of ICM input
to comparator.

ICM is voltage source and does not
need this component.

Increase BW from 20kHz to 25kHz while
maintaining 80degrees phase margin.

following DELL rule depopulate PD54 and PR373 0. 1

Add bead to connect +PWR_SRC to
+CPU_PWR_SRC

BITS-WI99902
This is to add an optional ultrasonic mode
in case the regulators experience an audible
noise.

Change PR429 from 0 ohm to 1 ohm

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

4

3

change PR361 from 0 Ohm (SD02800008L) to 8.45K (SD00000068L).
change PC254 from 0.01uF 25V (SE068103K8L) to 0.1uF 16V (SE076104K8L).

0.1

depopulate PR150. 0.1

change PR148 from 4.7K (SD03447018L) to 10K (SD03410028L). 0.1

Add PL44(SM01002078L) to parallel PJP30.10/27 DELL

Add PR517(SD02800008L) between pin 29 of PU20 and AGND .
Add PR518(SD02800008L) between pin 29 of PU22 and AGND .
Add PR519(SD02800008L) between pin 29 of PU21 and AGND .

change PR429 from 0 Ohm (SD01300008L ) to 1 Ohm(SD013100B8L).

0.2

0.2

0.2

DELL CONFIDENTIAL/PROPRIETARY

Title

Changed-List History 2

Size Document Number Rev

2

Date: Sheet

LA-3301P

Wednesday, February 28, 2007

of

1

62 62

0.6

5

4

Version Change List ( P. I. R. List )

3

2

1

Item Issue DescriptionDate

D D

30 45 PWR 11/20 DELL

31 4 9 PWR 12/06 DELL

C C

32 4 8 PWR 12/06 DELL

33 49 PWR 01/25 ELICK change to new part number for PSL

34

45/47 PWR 02/05 DELL

Owner

DELL29 49 PWR 11/16

BITS: WI102613
Change PR148 from 10K_0402_1% to 2.2K_0402
_5%

BITS-WI105401
Add node name +3.3V_ALW2 for the trace
connected to the pin 5 (VREF3) of PU20.
Populate PC285 with 0.1uF cap.

BITS-WI106278
make sure that PC113, PC114 and PC379 are
X5R/X75 caps, need to stuff PC379.

BITS-WI108223
Change PC187 from 10nF to 15nF.
Change PR258 from 2.21K to 1.69K.
Populate PR516 with 1K resistor.
Populate C413 with 0.01uF.

BITS-WI119945
Increase current limits for 3.3V and 1.5V
regulators.

change PR148 from 10K 0402 1% (SD03410028L ) to 2.2k 0402 5%(SD02822018L) 0. 3

Add node name +3.3V_ALW2 between pin5 of PU20 and PC285.
Populate PC285.

change PC379 is populated. 0.3

change PR187 from 10nF(SE076103K8L) to 15nF(SE076153K8L).
change PR258 from 2.21K(SD03422118L) to 1.69K(SD00000JB8L).
populate PC413.
populate PR516.

change PR138 from SD021100D8L to SD021100D3L(S RES 1W .01 +-1% 2512
FOR M08 PROJECTS)
change PR145 from SD021100D8L to SD021100D3L(S RES 1W .01 +-1% 2512
FOR M08 PROJECTS)

change PR382 from 226K to 267k (SD02822018L).
Change PR408 from 82.5K to 100K(SD03410038L).

Solution Description Rev.Page# Titl e

0.3

0.3

0.4

0.4

Request

delete
not to

35

B B

36

A A

49 PWR 02/12 DELL delete 1206 resistor on +VCHGR

DELL02 /06PWR49

additional 1206 resistor on +VCHGR for
Maxim solution.

not to implement for Maxim solution.

add an unpopulation PR520 (1.8K 1206 1%(SD00000JN8L))between
+VCHGR to PGND.

delete an unpopulate PR520 (1.8K 1206 1%(SD00000JN8L))between
+VCHGR to PGND.

0.4

0.4

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Changed-List History 3

Size Document Number Rev

Date: Sheet

LA-3301P

58 58Wednesday, February 28, 2007

1

of

0.6