Compal LA-3281P Schematics

A

1 1

2 2

B

C

D

E

Schematics Document

Compal confidential

Mobile Yonah uFCPGA with Intel

3 3

4 4

A

Calistoga_GM/PM+ICH7-M core logic

星期三七月

B

, 12, 2

REV:0.3

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2005/10/06 2006/10/06

006

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

D

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, M/B LA-3281

401429

E

B

of

147

A

B

C

D

E

Compal confidential

File Name : LA-3281P

ZZZ1

14W_PCB

1 1

HDL20 PCB panelization Data for DVT

PCB Function

MB Audio/USB SW board CRT board TP board

FP Board

LED board

2 2

3 3

LA3281P LS3251P LS3102P LS3253P LS3104P LS3255P LS3256P

DVT build revisionPCB Number

0.2

1.0

0.1

1.0

0.1

0.2

RTL8100CL 10/100M LAN

RJ45 CONN

page27

SUB Board

*RJ45 CONN *RJ11 CONN *MIC IN JACK *HP OUT JACK *LED

page27

page32,36

CRT & TV OUT

page17

LVDS Connector

page16

3.3V / 33 MHz

1394+Card Reader

RICOH R5C832

1394 Conn

page26 page25

*1394 CONN *DC JACK *TVOUT CONN *USB CONN *SWITCH

page26

Card reader(XD SD/MMC/MS)

page26

LVDS I/F

PCI BUS

CardBus

ENE CB1410

page24

Slot 0

uFCBGA-479/uFCPGA-478 CPU

Intel Calistoga GMCH

Touch Pad

*SWITCH

Mobile Yonah

H_A#(3..31) H_D#(0..63)

FSB

533/667MHz

PCBGA 1466

page7,8,9,10,11,12

DMI

Intel ICH7-M

mBGA-652

page19,20,21,22

LPC BUS

EC ENE KB910L

page32

page33

page4,5,6

Int.KBD

BIOS

page32

page34

DDR2 -667

Dual Channel

AZALIA USB2.0 PCI-E SATA ATA100

Clock Gen. ICS9LPR325AKLFT

DDR2-SO-DIMM X2

BANK 0, 1, 2, 3

page 13,14

MODEM

Ver 1.5

page 28

AMP&Audio Jack

page30

Audio Codec ALC 861VD

page29

Finger printer

page36

CMOS Camera

page36

BlueTooth Conn

page28

USB conn X4

page31

PCI Express Mini card Slot

page28

SATA HDD Connector

page23

page15

4 4

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2005/10/06 2006/10/06

Compal Secret Data

Deciphered Date

D

PATA CDROM Connector

Title

Size Document Number Rev

Custom

401429

星期三七月

Date: Sheet

page23

Compal Electronics, Inc.

SCHEMATIC, M/B LA-3281

06

247, 12, 20

E

of

B

Voltage Rails

power plane

State

S0

S1

S3

S5 S4/AC

S5 S4/ Battery only

S5 S4/AC & Battery don't exist

+B LDO3 LDO5

+5VALW +3VALW

O

X

XX X

+5V

O

XX

X

+5VS +3VS +2.5VS +1.8VS +1.5VS+1.8V +1.2VS +VGA_CORE +0.9VS +CPU_CORE +VCCP

OO

X

A

SKU ID Table

Vcc 3.3V +/- 5%

Board ID

0

*

1 2 3 4 5 6 7 NC

SKU ID

0 1 2 3 4

*

5 6 7

H L

100K +/- 5%Ra

Rb V min

0

8.2K +/- 5% 18K +/- 5% 33K +/- 5% 56K +/- 5% 100K +/- 5% 200K +/- 5%

15" 14"

AD_BID

0 V

Vtyp

AD_BID

0 V 0 V

0.216 V 0.250 V 0.289 V

0.436 V

0.712 V

1.036 V

0.503 V

0.819 V

1.185 V 1.264 V

1.453 V 1.650 V 1.759 V

1.935 V

2.500 V

MB ID(H)

HDL10

2.200 V

3.300 V

MB ID(L)

HDL00 HDL20 HDL30IDL12

MB ID

V

AD_BID

0.538 V

0.875 V

2.341 V

3.300 V

max

O MEANS ON

X MEANS OFF

S3 : STR S4 : STD S5 : SOFT OFF

1 1

External PCI Devices

Device IDSEL # REQ # / GN T # Interrupts

1394 PIRQG/H LAN

CardBus

AD22 AD17 AD20

EC SM Bus1 address

Device

Smart Battery EEPROM(24C16/02)

Address

0001 011X b 1010 000X b

0

3PIRQF

2

PIRQA

EC SM Bus2 address

Device

ADM1032

Address

1001 100X b

BOM Structure USB PORT LIST

MARK FUNCTION

GIGA@ 10/100@

NC FOR ALL@ 8110SBL(SCL)Giga LAN 8100CL 10/100Mb LAN

UMA@

Internal 945GM

VGA@

External G7xM

PORT

0 1 2 3 4 5 6 7

DEVICE

LEFT SIDE BT(HDL00/10) RIGHT SIDE CMOS RIGHT SIDE FINGER PRINTER RIGHT SIDE BT(HDL20)

ICH6 SM Bus address

Device

Clock Generator ( ICS954226)

DDRII DIMM0 DDRII DIMM1

Address

1101 001Xb 1010 000Xb 1010 010Xb

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

2005/10/06 2006/10/06

Compal Secret Data

Deciphered Date

Title

Size Document Number Re v

Custom

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, M/B LA-3281

401429

星期三七月

of

347, 12, 2006

B

5

H_A#[3..31]<7>

H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8

D D

H_REQ#[0..4]<7>

H_ADSTB#0<7>

C C

R84

56_0402_5%

1 2

+VCCP

B B

H_PROCHOT#<45>

1 2

+VCCP

68_0402_5%

H_THERMDA, H_THERMDC routing together. Trace width / Spacing = 10 / 10 mil

A A

H_PROCHOT# OCP#

H_ADSTB#1<7>

CLK_CPU_BCLK<15>

CLK_CPU_BCLK#<15>

H_ADS#<7> H_BNR#<7>

H_BPRI#<7>

H_BR0#<7>

H_DEFER#<7>

H_DRDY#<7>

H_HIT#<7>

H_HITM#<7>

H_LOCK#<7>

H_RESET#<7>

H_RS#[0..2]<7>

H_TRDY#<7>

ITP_DBRESET#<21>

H_DBSY#<7>

H_DPSLP#<20>

H_DPRSTP#<20,45>

H_DPWR#<7>

R83

H_PWRGOOD<20>

H_CPUSLP#<7,20>

R71 1K_0402_5%@

1 2

R74 51_0402_5%

1 2

H_THERMTRIP#<7,20>

+VCCP

12

R73

56_0402_5%@

CBE

123

Q4

PMBT3904_SOT23@

5

H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16 H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31

H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4

H_ADSTB#0 H_ADSTB#1

CLK_CPU_BCLK CLK_CPU_BCLK#

H_ADS# H_BNR# H_BPRI# H_BR0# H_DEFER# H_DRDY# H_HIT# H_HITM# H_IERR# H_LOCK# H_RESET#

H_RS#0 H_RS#1 H_RS#2 H_TRDY#

ITP_DBRESET#

H_DBSY# H_DPSLP# H_DPRSTP# H_DPWR# ITP_BPM#4 ITP_BPM#5 H_PROCHOT#

H_PWRGOOD H_CPUSLP# ITP_TCK ITP_TDI ITP_TDO TEST1 TEST2 ITP_TMS ITP_TRST#

H_THERMDA H_THERMDC H_THERMTRIP#

OCP# <21>

ITP_BPM#0 ITP_BPM#1 ITP_BPM#2 ITP_BPM#3

JP1A

J4

A3#

L4

A4#

M3

A5#

K5

A6#

M1

A7#

N2

A8#

J1

A9#

N3

A10#

P5

A11#

P2

A12#

L1

A13#

P4

A14#

P1

A15#

R1

A16#

Y2

A17#

U5

A18#

R3

A19#

W6

A20#

U4

A21#

Y5

A22#

U2

A23#

R4

A24#

T5

ADDR GROUP

A25#

T3

A26#

W3

A27#

W5

A28#

Y4

A29#

W2

A30#

Y1

A31#

K3

REQ0#

H2

REQ1#

K2

REQ2#

J3

REQ3#

L5

REQ4#

L2

ADSTB0#

V4

ADSTB1#

A22

BCLK0

A21

H1

E2

G5

F1

H5

F21

G6

E4

D20

H4

B1

F3

F4 G3 G2

AD4 AD3 AD1 AC4

C20

E1

B5

E5

D24 AC2 AC1 D21

D6 D7

AC5 AA6 AB3 C26 D25 AB5 AB6

A24 A25

C7

HOST CLK

BCLK1

ADS# BNR# BPRI# BR0# DEFER# DRDY# HIT#

CONTROL

HITM# IERR# LOCK# RESET#

RS0# RS1# RS2# TRDY#

BPM0# BPM1# BPM2# BPM3#

DBR# DBSY# DPSLP# DPRSTP# DPWR# PRDY# PREQ# PROCHOT#

PWRGOOD SLP# TCK TDI TDO TEST1 TEST2 TMS TRST#

THERMAL

THERMDA

DIODE

THERMDC THERMTRIP#

TYCO_1-1674770-2_Yonah~D

ME@

H_DPSLP#

H_DPRSTP#

YONAH

MISC

R100

1 2

56_0402_5%@

R99

1 2

56_0402_5%@

4

DATA GROUP

LEGACY CPU

+VCCP

4

D10# D11# D12# D13# D14# D15# D16# D17# D18# D19# D20# D21# D22# D23# D24# D25# D26# D27# D28# D29# D30# D31# D32# D33# D34# D35# D36# D37# D38# D39# D40# D41# D42# D43# D44# D45# D46# D47# D48# D49# D50# D51# D52# D53# D54# D55# D56# D57# D58# D59# D60# D61# D62# D63#

DINV0# DINV1# DINV2# DINV3#

DSTBN0# DSTBN1# DSTBN2# DSTBN3# DSTBP0# DSTBP1# DSTBP2# DSTBP3#

A20M# FERR#

IGNNE#

INIT# LINT0 LINT1

STPCLK#

SMI#

3

This shall place near CPU

H_D#[0..63] <7>

H_D#0

E22

D0#

H_D#1

F24

D1#

H_D#2

E26

D2#

H_D#3

H22

D3#

H_D#4

F23

D4#

H_D#5

G25

D5#

H_D#6

E25

D6#

H_D#7

E23

D7#

H_D#8

K24

D8#

H_D#9

G24

D9#

H_D#10

J24

H_D#11

J23 H26 F26 K22 H25 N22 K25 P26 R23 L25 L22 L23 M23 P25 P22 P23 T24 R24 L26 T25 N24 AA23 AB24 V24 V26 W25 U23 U25 U22 AB25 W22 Y23 AA26 Y26 Y22 AC26 AA24 AC22 AC23 AB22 AA21 AB21 AC25 AD20 AE22 AF23 AD24 AE21 AD21 AE25 AF25 AF22 AF26

J26 M26 V23 AC20

H23 M24 W24 AD23 G22 N25 Y25 AE24

A6 A5 C4 B3 C6 B4

D5 A3

H_D#12 H_D#13 H_D#14 H_D#15 H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31 H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63

H_DINV#0 H_DINV#1 H_DINV#2 H_DINV#3

H_DSTBN#0 H_DSTBN#1 H_DSTBN#2 H_DSTBN#3 H_DSTBP#0 H_DSTBP#1 H_DSTBP#2 H_DSTBP#3

H_A20M# H_FERR# H_IGNNE# H_INIT# H_INTR H_NMI

H_STPCLK# H_SMI#

H_DINV#0 <7> H_DINV#1 <7> H_DINV#2 <7> H_DINV#3 <7>

H_DSTBN#[0..3] <7>

H_DSTBP#[0..3] <7>

H_A20M# <20> H_FERR# <20> H_IGNNE# <20> H_INIT# <20> H_INTR <20> H_NMI <20>

H_STPCLK# <20> H_SMI# <20>

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DIS CLOSE D TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

ITP_DBRESET#

R85 200_0402_5%@

1 2

2005/10/06 2006/10/06

ITP_TDI ITP_TMS ITP_TDO ITP_BPM#5 ITP_TRST# ITP_TCK

ITP_BPM#0 ITP_BPM#1 ITP_BPM#2 ITP_BPM#3 ITP_BPM#4

C311

1 2

EC_SMB_CK2<33> EC_SMB_DA2<33>

EN_FAN1<33>

Compal Secret Data

Deciphered Date

2

R98 56_0402_5%

1 2

R97 56_0402_1%

1 2

R101 56_0402_5%

1 2

R103 56_0402_5%

1 2

R95 56_0402_5%

1 2

R96 56_0402_5%

1 2

T13

PAD

T17

PAD

T18

PAD

T20

PAD

T16

PAD

T19

PAD

+VSB

+IN

-IN

+IN

-IN

2

8

P

OUT

U15A

G

LM358A_SO8

4

OUT

U15B LM358A_SO8

U16

2

D+

3

D-

8

SCLK

7

SDATA

G781F_SOP8

Address:100_1100

FAN1_ON

1

1 2

R218 100K_0402_5%

7

H_THERMDA H_THERMDC

2200P_0402_50V7K

EC_SMB_CK2 EC_SMB_DA2

C309

12

0.1U_0603_25V7K

3 2

12

R219 150K_0402_5%

5 6

+VCCP

VDD1

ALERT#

THERM#

1N4148_SOD80

1

+3VS

1 6 4 5

GND

+5VS

6

2

1

G

3

S

4 5

12

D11

Title

Size Document Number Rev

Custom

Date: Sheet

12

C310 0.1U_0402_16V4Z

THERM#

1 2

C303 10U_1206_16V4Z

D

Q19 SI3456BDV-T1-E3_TSOP6

FAN1

1

2

FAN_SPEED1<33>

@

1000P_0402_50V7K

C307

1000P_0402_50V7K

12

+3VS

R22610K_0402_5%

+3VS

R222 10K_0402_5%

1 2

1

2

C305 10U_0805_10V4Z

C308

ACES_85205-0300

1

2

Compal Electronics, Inc.

SCHEMATIC, M/B LA-3281

401429

星期三七月

1

447, 12, 2006

JP2

1 2 3

B

of

5

4

3

2

1

D D

+CPU_GTLREF

Close to CPU pin AD26 within 500mils.

C C

B B

+VCCP

12

R69 1K_0402_1%

12

R62 2K_0402_1%

+CPU_CORE

R93 100_0402_1%

1 2

R94 100_0402_1%

1 2

VCCSENSE

VSSENSE

Close to CPU pin within 500mils.

CPU_BSEL CPU_BSEL2 CPU_BSEL1

133

166

00

0

12

R72

R70

27.4_0402_1%

R102

54.9_0402_1%

Length match within 25 mils The trace width 18 mils space 7 mils

+1.5VS

1

C122

C132

2

0.01U_0402_16V7K

10U_0805_10V4Z

CPU_BSEL0

1

12

R104

54.9_0402_1%

27.4_0402_1%

1

Resistor placed within

0.5" of CPU pin.Trace should be at least 25 mils away from any other toggling signal.

1

2

CPU_VID0<45> CPU_VID1<45> CPU_VID2<45> CPU_VID3<45> CPU_VID4<45> CPU_VID5<45> CPU_VID6<45>

+CPU_GTLREF

CPU_BSEL0<15> CPU_BSEL1<15> CPU_BSEL2<15>

VCCSENSE<45> VSSENSE<45>

H_PSI#<45>

+VCCP

+CPU_CORE

VCCSENSE VSSENSE

H_PSI# CPU_VID0

CPU_VID1 CPU_VID2 CPU_VID3 CPU_VID4 CPU_VID5 CPU_VID6

CPU_BSEL0 CPU_BSEL1 CPU_BSEL2

COMP0 COMP1 COMP2 COMP3

JP1B

AF7

VCCSENSE

AE7

VSSSENSE

B26

VCCA

K6

VCCP

J6

VCCP

M6

VCCP

N6

VCCP

T6

VCCP

R6

VCCP

K21

VCCP

J21

VCCP

M21

VCCP

N21

VCCP

T21

VCCP

R21

VCCP

V21

VCCP

W21

VCCP

V6

VCCP

G21

VCCP

AE6

PSI#

AD6

VID0

AF5

VID1

AE5

VID2

AF4

VID3

AE3

VID4

AF2

VID5

AE2

VID6

AD26

GTLREF

B22

BSEL0

B23

BSEL1

C21

BSEL2

R26

COMP0

U26

COMP1

U1

COMP2

V1

COMP3

E7

VCC

AB20

VCC

AA20

VCC

AF20

VCC

AE20

VCC

AB18

VCC

AB17

VCC

AA18

VCC

AA17

VCC

AD18

VCC

AD17

VCC

AC18

VCC

AC17

VCC

AF18

VCC

AF17

VCC

D2

RSVD

F6

RSVD

D3

RSVD

C1

RSVD

AF1

RSVD

D22

RSVD

C23

RSVD

C24

RSVD

AA1

RSVD

AA4

RSVD

AB2

RSVD

AA3

RSVD

M4

RSVD

N5

RSVD

T2

RSVD

V3

RSVD

B2

RSVD

C3

RSVD

T22

RSVD

B25

RSVD

TYCO_1-1674770-2_Yonah~D

ME@

YONAH

POWER, GROUNG, RESERVED SIGNALS AND NC

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

AB26 AA25 AD25 AE26 AB23 AC24 AF24 AE23 AA22 AD22 AC21 AF21 AB19 AA19 AD19 AC19 AF19 AE19 AB16 AA16 AD16 AC16 AF16 AE16 AB13 AA14 AD13 AC14 AF13 AE14 AB11 AA11 AD11 AC11 AF11 AE11 AB8 AA8 AD8 AC8 AF8 AE8 AA5 AD5 AC6 AF6 AB4 AC3 AF3 AE4 AB1 AA2 AD2 AE1 B6 C5 F5 E6 H6 J5 M5 L6 P6 R5 V5 U6 Y6 A4 D4 E3 H3 G4 K4 L3 P3 N4 T4 U3 Y3 W4 D1 C2 F2 G1

+CPU_CORE

JP1C

AE18

VCC

AE17

VCC

AB15

VCC

AA15

VCC

AD15

VCC

AC15

VCC

AF15

VCC

AE15

VCC

AB14

VCC

AA13

VCC

AD14

VCC

AC13

VCC

AF14

VCC

AE13

VCC

AB12

VCC

AA12

VCC

AD12

VCC

AC12

VCC

AF12

VCC

AE12

VCC

AB10

VCC

AB9

VCC

AA10

VCC

AA9

VCC

AD10

VCC

AD9

VCC

AC10

VCC

AC9

VCC

AF10

VCC

AF9

VCC

AE10

VCC

AE9

VCC

AB7

VCC

AA7

VCC

AD7

VCC

AC7

VCC

B20

VCC

A20

VCC

F20

VCC

E20

VCC

B18

VCC

B17

VCC

A18

VCC

A17

VCC

D18

VCC

D17

VCC

C18

VCC

C17

VCC

F18

VCC

F17

VCC

E18

VCC

E17

VCC

B15

VCC

A15

VCC

D15

VCC

C15

VCC

F15

VCC

E15

VCC

B14

VCC

A13

VCC

D14

VCC

C13

VCC

F14

VCC

E13

VCC

B12

VCC

A12

VCC

D12

VCC

C12

VCC

F12

VCC

E12

VCC

B10

VCC

B9

VCC

A10

VCC

A9

VCC

D10

VCC

D9

VCC

C10

VCC

C9

VCC

F10

VCC

F9

VCC

E10

VCC

E9

VCC

B7

VCC

A7

VCC

F7

VCC

TYCO_1-1674770-2_Yonah~D

ME@

YONAH

POWER, GROUND

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

K1 J2 M2 N1 T1 R2 V2 W1 A26 D26 C25 F25 B24 A23 D23 E24 B21 C22 F22 E21 B19 A19 D19 C19 F19 E19 B16 A16 D16 C16 F16 E16 B13 A14 D13 C14 F13 E14 B11 A11 D11 C11 F11 E11 B8 A8 D8 C8 F8 E8 G26 K26 J25 M25 N26 T26 R25 V25 W26 H24 G23 K23 L24 P24 N23 T23 U24 Y24 W23 H21 J22 M22 L21 P21 R22 V22 U21 Y21

A A

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DIS CLOSE D TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/10/06 2006/10/06

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet of

Compal Electronics, Inc.

SCHEMATIC, M/B LA-3281

401429

星期三七月

547, 12, 2006

1

B

5

4

3

2

1

D D

Place these capacitors on L8 (North side,Secondary Layer)

Place these capacitors on L8 (Sorth side,Secondary Layer)

C C

Place these capacitors on L8 (Sorth side,Secondary Layer)

+CPU_CORE

1

2

+CPU_CORE

1

2

+CPU_CORE

1

2

+CPU_CORE

1

2

C318 10U_0805_6.3V6M

C325 10U_0805_6.3V6M

C183 10U_0805_6.3V6M

C150 10U_0805_6.3V6M

1

C326 10U_0805_6.3V6M

2

1

C186 10U_0805_6.3V6M

2

1

C170 10U_0805_6.3V6M

2

1

C165 10U_0805_6.3V6M

2

1

C151 10U_0805_6.3V6M

2

1

C341 10U_0805_6.3V6M

2

1

C334 10U_0805_6.3V6M

2

1

C345 10U_0805_6.3V6M

2

1

C171 10U_0805_6.3V6M

2

1

C178 10U_0805_6.3V6M

2

1

C319 10U_0805_6.3V6M

2

1

C173 10U_0805_6.3V6M

2

1

C346 10U_0805_6.3V6M

2

1

C316 10U_0805_6.3V6M

2

1

C172 10U_0805_6.3V6M

2

1

C179 10U_0805_6.3V6M

2

1

C169 10U_0805_6.3V6M

2

1

C185 10U_0805_6.3V6M

2

1

C333 10U_0805_6.3V6M

2

1

C177 10U_0805_6.3V6M

2

1

C187 10U_0805_6.3V6M

2

1

C166 10U_0805_6.3V6M

2

1

C181 10U_0805_6.3V6M

2

1

C317 10U_0805_6.3V6M

2

1

C184 10U_0805_6.3V6M

2

1

C342 10U_0805_6.3V6M

2

1

C176 10U_0805_6.3V6M

2

1

C182 10U_0805_6.3V6M

2

Mid Frequence Decoupling

+CPU_CORE

1

South Side Secondary

B B

+

C180

C324

2

330U_V_2.5VK_R9

1

+

C175

@

2

@

2

330U_V_2.5VK_R9

1

+

C339

C320

2

330U_V_2.5VK_R9

1

+

C343

2

330U_V_2.5VK_R9

North Side Secondary

ESR <= 1.5m ohm Capacitor > 1980uF

+VCCP

1

+

C109

220U_D2_4VM

A A

5

2

1

C190

0.1U_0402_16V4Z

2

1

C136

0.1U_0402_16V4Z

2

4

1

C138

0.1U_0402_16V4Z

2

1

C137

0.1U_0402_16V4Z

2

1

C189

0.1U_0402_16V4Z

2

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DIS CLOSE D TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

1

C188

0.1U_0402_16V4Z

2

3

Place these inside socket cavity on L8 (North side Secondary)

2005/10/06 2006/10/06

Compal Secret Data

Deciphered Date

2

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, M/B LA-3281

401429

星期三七月

647, 12, 2006

1

of

B

5

4

U14

3

2

1

H_D#[0..63]<4>

D D

C C

+VCCP

12

R26

R27

54.9_0402_1%

B B

12

R23

24.9_0402_1%

+VCCP

12

A A

R30

100_0402_1%

12

R36

200_0402_1%

H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31 H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63

+H_VREF H_XRCOMP H_XSCOMP H_YRCOMP H_YSCOMP +H_SWNG0 +H_SWNG1

12

R20

24.9_0402_1%

Layout Note: H_XRCOMP / H_YRCOMP / H_VREF / H_SWNG0 / H_SWNG1 trace width and spacing is 10/20.

+H_VREF

1

C26

2

0.1U_0402_16V4Z

5

U14A

F1

HD0#

J1

HD1#

H1

HD2#

J6

HD3#

H3

HD4#

K2

HD5#

G1

HD6#

G2

HD7#

K9

HD8#

K1

HD9#

K7

HD10#

J8

HD11#

H4

HD12#

J3

HD13#

K11

HD14#

G4

HD15#

T10

HD16#

W11

HD17#

T3

HD18#

U7

HD19#

U9

HD20#

U11

HD21#

T11

HD22#

W9

HD23#

T1

HD24#

T8

HD25#

T4

HD26#

W7

HD27#

U5

HD28#

T9

HD29#

W6

HD30#

T5

HD31#

AB7

HD32#

AA9

HD33#

W4

HD34#

W3

HD35#

Y3

HD36#

Y7

HD37#

W5

HD38#

Y10

HD39#

AB8

HD40#

W2

HD41#

AA4

HD42#

AA7

HD43#

AA2

HD44#

AA6

HD45#

AA10

HD46#

Y8

HD47#

AA1

HD48#

AB4

HD49#

AC9

HD50#

AB11

HD51#

AC11

HD52#

AB3

HD53#

AC2

HD54#

AD1

HD55#

AD9

HD56#

AC1

HD57#

AD7

HD58#

AC6

HD59#

AB5

HD60#

AD10

HD61#

AD4

HD62#

AC8

HD63#

J13

HVREF0

K13

HVREF1

E1

HXRCOMP

E2

HXSCOMP

Y1

HYRCOMP

U1

HYSCOMP

E4

HXSWING

W1

HYSWING

CALISTOGA_FCBGA1466~D

UMA@

HOST

HA3# HA4# HA5# HA6# HA7# HA8#

HA9# HA10# HA11# HA12# HA13# HA14# HA15# HA16# HA17# HA18# HA19# HA20# HA21# HA22# HA23# HA24# HA25# HA26# HA27# HA28# HA29# HA30# HA31#

HREQ#0 HREQ#1 HREQ#2 HREQ#3 HREQ#4

HADSTB#0 HADSTB#1

HCLKN HCLKP

HDSTBN#0 HDSTBN#1 HDSTBN#2 HDSTBN#3 HDSTBP#0 HDSTBP#1 HDSTBP#2 HDSTBP#3

HDINV#0 HDINV#1 HDINV#2 HDINV#3

HCPURST#

HADS#

HTRDY#

HDPWR#

HDRDY#

HDEFER#

HHITM#

HHIT#

HLOCK#

HBREQ0#

HBNR#

HBPRI#

HDBSY#

HCPUSLP#

HRS0# HRS1# HRS2#

12

R22

12

R24

221_0603_1%

100_0402_1%

H9 C9 E11 G11 F11 G12 F9 H11 J12 G14 D9 J14 H13 J15 F14 D12 A11 C11 A12 A13 E13 G13 F12 B12 B14 C12 A14 C14 D14

D8 G8 B8 F8 A8

B9 C13

AG1 AG2

K4 T7 Y5 AC4 K3 T6 AA5 AC5

J7 W8 U3 AB10

B7 E8 E7 J9 H8 C3 D4 D3 B3 C7 C6 F6 A7 E3

B4 E6 D6

+H_SWNG0

1

2

4

H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16 H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31

H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4

H_ADSTB#0 H_ADSTB#1

CLK_MCH_BCLK# CLK_MCH_BCLK

H_DSTBN#0 H_DSTBN#1 H_DSTBN#2 H_DSTBN#3 H_DSTBP#0 H_DSTBP#1 H_DSTBP#2 H_DSTBP#3

H_DINV#0 H_DINV#1 H_DINV#2 H_DINV#3

H_RESET# H_ADS# H_TRDY# H_DPWR# H_DRDY# H_DEFER# H_HITM# H_HIT# H_LOCK# H_BR0# H_BNR# H_BPRI# H_DBSY# H_CPUSLP#

H_RS#0 H_RS#1 H_RS#2

C19

0.1U_0402_16V4Z

+VCCP+VCCP

12

R18

221_0603_1%

12

R19

100_0402_1%

H_A#[3..31] <4>

H_REQ#[0..4] <4>

H_ADSTB#0 <4> H_ADSTB#1 <4>

CLK_MCH_BCLK# <15> CLK_MCH_BCLK <15> H_DSTBN#[0..3] <4>

H_DSTBP#[0..3] <4>

H_DINV#0 <4> H_DINV#1 <4> H_DINV#2 <4> H_DINV#3 <4>

H_RESET# <4> H_ADS# <4> H_TRDY# <4> H_DPWR# <4> H_DRDY# <4> H_DEFER# <4> H_HITM# <4> H_HIT# <4> H_LOCK# <4> H_BR0# <4> H_BNR# <4> H_BPRI# <4> H_DBSY# <4> H_CPUSLP# <4,20>

H_RS#[0..2] <4>

+H_SWNG1

1

2

0.1U_0402_16V4Z

PM

VGA@

DMI_TXN0<21> DMI_TXN1<21> DMI_TXN2<21> DMI_TXN3<21>

DMI_TXP0<21> DMI_TXP1<21> DMI_TXP2<21> DMI_TXP3<21>

DMI_RXN0<21> DMI_RXN1<21> DMI_RXN2<21> DMI_RXN3<21>

DMI_RXP0<21> DMI_RXP1<21> DMI_RXP2<21> DMI_RXP3<21>

M_CLK_DDR0<13> M_CLK_DDR1<13> M_CLK_DDR2<14> M_CLK_DDR3<14>

M_CLK_DDR#0<13> M_CLK_DDR#1<13> M_CLK_DDR#2<14> M_CLK_DDR#3<14>

DDR_CKE0_DIMMA<13> DDR_CKE1_DIMMA<13> DDR_CKE2_DIMMB<14> DDR_CKE3_DIMMB<14>

DDR_CS0_DIMMA#<13> DDR_CS1_DIMMA#<13> DDR_CS2_DIMMB#<14> DDR_CS3_DIMMB#<14>

+1.8V

R29 80.6_0402_1% R28 80.6_0402_1%

R88

DPRSLPVR<21,45>

C11

0_0402_5%

PLT_RST#<19,23,28>

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

M_ODT0<13> M_ODT1<13> M_ODT2<14> M_ODT3<14>

1 2 1 2

+DDR_MCH_REF

PM_BMBUSY#<21> PM_EXTTS#0<13,14>

12

H_THERMTRIP#<4,20>

ICH_POK<21,33>

R55 100_0402_1%

MCH_ICH_SYNC#<19>

Layout Note: +DDR_MCH_REF trace width and spacing is 20/20.

+DDR_MCH_REF PM_EXTTS#1

C16

0.1U_0402_16V4Z

2005/10/06 2006/10/06

1

2

DMI_TXN0 DMI_TXN1 DMI_TXN2 DMI_TXN3

DMI_TXP0 DMI_TXP1 DMI_TXP2 DMI_TXP3

DMI_RXN0 DMI_RXN1 DMI_RXN2 DMI_RXN3

DMI_RXP0 DMI_RXP1 DMI_RXP2 DMI_RXP3

M_CLK_DDR0 M_CLK_DDR1 M_CLK_DDR2 M_CLK_DDR3

M_CLK_DDR#0 M_CLK_DDR#1 M_CLK_DDR#2 M_CLK_DDR#3

DDR_CKE0_DIMMA DDR_CKE1_DIMMA DDR_CKE2_DIMMB DDR_CKE3_DIMMB

DDR_CS0_DIMMA# DDR_CS1_DIMMA# DDR_CS2_DIMMB# DDR_CS3_DIMMB#

M_OCDOCMP0 M_OCDOCMP1

M_ODT0 M_ODT1 M_ODT2 M_ODT3

SMRCOMPN SMRCOMPP

PM_BMBUSY# PM_E XTTS#0 PM_E XTTS#1 H_THERMTRIP# ICH_POK PLTRST_R#

12

+1.8V

12

R25

12

R21

Compal Secret Data

100_0402_1%

U14B

AE35

DMIRXN0

AF39

DMIRXN1

AG35

DMIRXN2

AH39

DMIRXN3

AC35

DMIRXP0

AE39

DMIRXP1

AF35

DMIRXP2

AG39

DMIRXP3

AE37

DMITXN0

AF41

DMITXN1

AG37

DMITXN2

AH41

DMITXN3

AC37

DMITXP0

AE41

DMITXP1

AF37

DMITXP2

AG41

DMITXP3

AY35

SM_CK0

AR1

SM_CK1

AW7

SM_CK2

AW40

SM_CK3

AW35

SM_CK0#

AT1

SM_CK1#

AY7

SM_CK2#

AY40

SM_CK3#

AU20

SM_CKE0

AT20

SM_CKE1

BA29

SM_CKE2

AY29

SM_CKE3

AW13

SM_CS0#

AW12

SM_CS1#

AY21

SM_CS2#

AW21

SM_CS3#

AL20

SM_OCDCOMP0

AF10

SM_OCDCOMP1

BA13

SM_ODT0

BA12

SM_ODT1

AY20

SM_ODT2

AU21

SM_ODT3

AV9

SM_RCOMPN

AT9

SM_RCOMPP

AK1

SM_VREF0

AK41

SM_VREF1

G28

PM_BMBUSY#

F25

PM_EXTTS0#

H26

PM_EXTTS1#

G6

PM_THERMTRIP#

AH33

PWROK

AH34

RSTIN#

K28

ICH_SYNC#

CALISTOGA_FCBGA1466~D

UMA@

Deciphered Date

CFG0 CFG1 CFG2 CFG3 CFG4 CFG5 CFG6

DMI

DDR MUXING

PM

2

CFG7 CFG8

CFG9 CFG10 CFG11 CFG12 CFG13 CFG14 CFG15 CFG16

CFG

CFG17 CFG18 CFG19 CFG20

G_CLKP G_CLKN

D_REF_CLKN

D_REF_CLKP

CLKNC

D_REF_SSCLKN D_REF_SSCLKP

CLK_REQ#

NC0 NC1 NC2 NC3 NC4 NC5 NC6 NC7 NC8

NC9 NC10 NC11 NC12 NC13 NC14 NC15 NC16 NC17 NC18

RESERVED1 RESERVED2 RESERVED3 RESERVED4 RESERVED5 RESERVED6 RESERVED7 RESERVED8

RESERVED9 RESERVED10 RESERVED11 RESERVED12 RESERVED13

RESERVED

Title

Size Document Number Rev

Custom

Date: Sheet

Description at page15.

MCH_CLKSEL0

K16

MCH_CLKSEL1

K18

MCH_CLKSEL2

J18

CFG3

F18

CFG4

E15

CFG5

F15

CFG6

E18

CFG7

D19

CFG8

D16

CFG9

G16

CFG10

E16

CFG11

D15

CFG12

G15

CFG13

K15

CFG14

C15

CFG15

H16

CFG16

G18

CFG17

H15

CFG18

J25

CFG19

K27

CFG20

J26

CLK_MCH_3GPLL

AG33

CLK_MCH_3GPLL#

AF33

CLK_MCH_DREFCLK#

A27

CLK_MCH_DREFCLK

A26

MCH_SSCDREFCLK#

C40

MCH_SSCDREFCLK

D41

MCH_CLKREQ#

H32

A3 A39 A4 A40 AW1 AW41 AY1 BA1 BA2 BA3 BA39 BA40 BA41 C1 AY41 B2 B41 C41 D1

T32 R32 F3 F7 AG11 AF11 H7 J19 A41 A34 D28 D27 A35

M_OCDOCMP0

M_OCDOCMP1

PM_EXTTS#0

PAD PAD

PAD PAD PAD

PAD PAD

PAD

MCH_CLKSEL0 <15> MCH_CLKSEL1 <15>

MCH_CLKSEL2 <15>

T9 T3

CFG5 <11>

T10

CFG7 <11>

T7

CFG9 <11>

T5

CFG11 <11>

CFG12 <11>

CFG13 <11>

T2 T8

CFG16 <11>

T1

CFG18 <11>

CFG19 <11>

CFG20 <11>

CLK_MCH_3GPLL <15> CLK_MCH_3GPLL# <15>

CLK_MCH_DREFCLK# <15> CLK_MCH_DREFCLK <15>

CLK_MCH_SSCDREFCLK# <15> CLK_MCH_SSCDREFCLK <15>

MCH_CLKREQ# <15>

R46

10K_0402_5%

R49

10K_0402_5%@

R45

40.2_0402_1%@

R31

40.2_0402_1%@

Compal Electronics, Inc.

SCHEMATIC, M/B LA-3281

401429

星期三七月

06

1

+3VS

12

B

of

747, 12, 20

5

D D

4

3

2

1

DDR_A_BS#0<13> DDR_A_BS#1<13> DDR_A_BS#2<13>

DDR_A_DM[0..7]<13>

DDR_A_DQS[0..7]<13>

C C

DDR_A_DQS#[0..7]<13>

DDR_A_MA[0..13]<13>

B B

DDR_A_CAS#<13> DDR_A_RAS#<13>

DDR_A_WE#<13>

T6 P AD T12 PAD

DDR_A_BS#0 DDR_A_BS#1 DDR_A_BS#2

DDR_A_DM0 DDR_A_DM1 DDR_A_DM2 DDR_A_DM3 DDR_A_DM4 DDR_A_DM5 DDR_A_DM6 DDR_A_DM7

DDR_A_DQS0 DDR_A_DQS1 DDR_A_DQS2 DDR_A_DQS3 DDR_A_DQS4 DDR_A_DQS5 DDR_A_DQS6 DDR_A_DQS7

DDR_A_DQS#0 DDR_A_DQS#1 DDR_A_DQS#2 DDR_A_DQS#3 DDR_A_DQS#4 DDR_A_DQS#5 DDR_A_DQS#6 DDR_A_DQS#7

DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5

DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_B_MA11 DDR_A_MA12 DDR_A_MA13

DDR_A_CAS# DDR_A_RAS# DDR_A_WE# SA_RCVENIN# SA_RCVENOUT#

check layout check layout

U14D

AU12

SA_BS0

AV14

SA_BS1

BA20

SA_BS2

AJ33

SA_DM0

AM35

SA_DM1

AL26

SA_DM2

AN22

SA_DM3

AM14

SA_DM4

AL9

SA_DM5

AR3

SA_DM6

AH4

SA_DM7

AK33

SA_DQS0

AT33

SA_DQS1

AN28

SA_DQS2

AM22

SA_DQS3

AN12

SA_DQS4

AN8

SA_DQS5

AP3

SA_DQS6

AG5

SA_DQS7

AK32

SA_DQS0#

AU33

SA_DQS1#

AN27

SA_DQS2#

AM21

SA_DQS3#

AM12

SA_DQS4#

AL8

SA_DQS5#

AN3

SA_DQS6#

AH5

SA_DQS7#

AY16

SA_MA0

AU14

SA_MA1

AW16

SA_MA2

BA16

SA_MA3

BA17

SA_MA4

AU16

SA_MA5

AV17

SA_MA6

AU17

SA_MA7

AW17

SA_MA8

AT16

SA_MA9

AU13

SA_MA10

AT17

SA_MA11

AV20

SA_MA12

AV12

SA_MA13

AY13

SA_CAS#

AW14

SA_RAS#

AY14

SA_WE#

AK23

SA_RCVENIN#

AK24

SA_RCVENOUT#

CALISTOGA_FCBGA1466~D

UMA@

SA_DQ0 SA_DQ1 SA_DQ2 SA_DQ3 SA_DQ4 SA_DQ5 SA_DQ6 SA_DQ7 SA_DQ8

SA_DQ9 SA_DQ10 SA_DQ11 SA_DQ12 SA_DQ13 SA_DQ14 SA_DQ15 SA_DQ16 SA_DQ17 SA_DQ18 SA_DQ19 SA_DQ20 SA_DQ21 SA_DQ22 SA_DQ23 SA_DQ24 SA_DQ25 SA_DQ26 SA_DQ27 SA_DQ28 SA_DQ29 SA_DQ30 SA_DQ31 SA_DQ32 SA_DQ33 SA_DQ34 SA_DQ35 SA_DQ36 SA_DQ37 SA_DQ38 SA_DQ39

DDR SYS MEMORY A

SA_DQ40 SA_DQ41 SA_DQ42 SA_DQ43 SA_DQ44 SA_DQ45 SA_DQ46 SA_DQ47 SA_DQ48 SA_DQ49 SA_DQ50 SA_DQ51 SA_DQ52 SA_DQ53 SA_DQ54 SA_DQ55 SA_DQ56 SA_DQ57 SA_DQ58 SA_DQ59 SA_DQ60 SA_DQ61 SA_DQ62 SA_DQ63

AJ35 AJ34 AM31 AM33 AJ36 AK35 AJ32 AH31 AN35 AP33 AR31 AP31 AN38 AM36 AM34 AN33 AK26 AL27 AM26 AN24 AK28 AL28 AM24 AP26 AP23 AL22 AP21 AN20 AL23 AP24 AP20 AT21 AR12 AR14 AP13 AP12 AT13 AT12 AL14 AL12 AK9 AN7 AK8 AK7 AP9 AN9 AT5 AL5 AY2 AW2 AP1 AN2 AV2 AT3 AN1 AL2 AG7 AF9 AG4 AF6 AG9 AH6 AF4 AF8

DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15 DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63

DDR_A_D[0..63] <13> DDR_B_D[0..63] <14>

DDR_B_BS#0<14> DDR_B_BS#1<14> DDR_B_BS#2<14>

DDR_B_DM[0..7]<14>

DDR_B_DQS[0..7]<14>

DDR_B_DQS#[0..7]<14>

DDR_B_MA[0..13]<14>

DDR_B_CAS#<14>

DDR_B_RAS#<14>

DDR_B_WE#<14>

T4 PAD T11 PAD

DDR_B_BS#0 DDR_B_BS#1 DDR_B_BS#2

DDR_B_DM0 DDR_B_DM1 DDR_B_DM2 DDR_B_DM3 DDR_B_DM4 DDR_B_DM5 DDR_B_DM6 DDR_B_DM7

DDR_B_DQS0 DDR_B_DQS1 DDR_B_DQS2 DDR_B_DQS3 DDR_B_DQS4 DDR_B_DQS5 DDR_B_DQS6 DDR_B_DQS7

DDR_B_DQS#0 DDR_B_DQS#1 DDR_B_DQS#2 DDR_B_DQS#3 DDR_B_DQS#4 DDR_B_DQS#5 DDR_B_DQS#6 DDR_B_DQS#7

DDR_B_MA0 DDR_B_MA1 DDR_B_MA2 DDR_B_MA3 DDR_B_MA4 DDR_B_MA5 DDR_B_MA6DDR_A_MA6 DDR_B_MA7 DDR_B_MA8 DDR_B_MA9 DDR_B_MA10

DDR_B_MA12 DDR_B_MA13

DDR_B_CAS# DDR_B_RAS# DDR_B_WE# SB_RCVENIN# SB_RCVENOUT#

U14E

AT24

SB_BS0

AV23

SB_BS1

AY28

SB_BS2

AK36

SB_DM0

AR38

SB_DM1

AT36

SB_DM2

BA31

SB_DM3

AL17

SB_DM4

AH8

SB_DM5

BA5

SB_DM6

AN4

SB_DM7

AM39

SB_DQS0

AT39

SB_DQS1

AU35

SB_DQS2

AR29

SB_DQS3

AR16

SB_DQS4

AR10

SB_DQS5

AR7

SB_DQS6

AN5

SB_DQS7

AM40

SB_DQS0#

AU39

SB_DQS1#

AT35

SB_DQS2#

AP29

SB_DQS3#

AP16

SB_DQS4#

AT10

SB_DQS5#

AT7

SB_DQS6#

AP5

SB_DQS7#

AY23

SB_MA0

AW24

SB_MA1

AY24

SB_MA2

AR28

SB_MA3

AT27

SB_MA4

AT28

SB_MA5

AU27

SB_MA6

AV28

SB_MA7

AV27

SB_MA8

AW27

SB_MA9

AV24

SB_MA10

BA27

SB_MA11

AY27

SB_MA12

AR23

SB_MA13

AR24

SB_CAS#

AU23

SB_RAS#

AR27

SB_WE#

AK16

SB_RCVENIN#

AK18

SB_RCVENOUT#

CALISTOGA_FCBGA1466~D

UMA@

SB_DQ0 SB_DQ1 SB_DQ2 SB_DQ3 SB_DQ4 SB_DQ5 SB_DQ6 SB_DQ7 SB_DQ8

SB_DQ9 SB_DQ10 SB_DQ11 SB_DQ12 SB_DQ13 SB_DQ14 SB_DQ15 SB_DQ16 SB_DQ17 SB_DQ18 SB_DQ19 SB_DQ20 SB_DQ21 SB_DQ22 SB_DQ23 SB_DQ24 SB_DQ25 SB_DQ26 SB_DQ27 SB_DQ28 SB_DQ29 SB_DQ30 SB_DQ31 SB_DQ32 SB_DQ33 SB_DQ34 SB_DQ35 SB_DQ36 SB_DQ37 SB_DQ38 SB_DQ39

DDR SYS MEMORY B

SB_DQ40 SB_DQ41 SB_DQ42 SB_DQ43 SB_DQ44 SB_DQ45 SB_DQ46 SB_DQ47 SB_DQ48 SB_DQ49 SB_DQ50 SB_DQ51 SB_DQ52 SB_DQ53 SB_DQ54 SB_DQ55 SB_DQ56 SB_DQ57 SB_DQ58 SB_DQ59 SB_DQ60 SB_DQ61 SB_DQ62 SB_DQ63

AJ37 AP39 AR41 AJ38 AK38 AN41 AP41 AT40 AV41 AU38 AV38 AP38 AR40 AW38 AY38 BA38 AV36 AR36 AP36 BA36 AU36 AP35 AP34 AY33 BA33 AT31 AU29 AU31 AW31 AV29 AW29 AM19 AL19 AP14 AN14 AN17 AM16 AP15 AL15 AJ11 AH10 AJ9 AN10 AK13 AH11 AK10 AJ8 BA10 AW10 BA4 AW4 AY10 AY9 AW5 AY5 AV4 AR5 AK4 AK3 AT4 AK5 AJ5 AJ3

DDR_B_D1 DDR_B_D2 DDR_B_D3 DDR_B_D4 DDR_B_D5 DDR_B_D6 DDR_B_D7 DDR_B_D8 DDR_B_D9 DDR_B_D10 DDR_B_D11 DDR_B_D12 DDR_B_D13 DDR_B_D14 DDR_B_D15 DDR_B_D16 DDR_B_D17 DDR_B_D18 DDR_B_D19 DDR_B_D20 DDR_B_D21 DDR_B_D22 DDR_B_D23 DDR_B_D24 DDR_B_D25 DDR_B_D26 DDR_B_D27 DDR_B_D28 DDR_B_D29 DDR_B_D30 DDR_B_D31 DDR_B_D32 DDR_B_D33 DDR_B_D34 DDR_B_D35 DDR_B_D36 DDR_B_D37 DDR_B_D38 DDR_B_D39 DDR_B_D40 DDR_B_D41 DDR_B_D42 DDR_B_D43 DDR_B_D44 DDR_B_D45 DDR_B_D46 DDR_B_D47 DDR_B_D48 DDR_B_D49 DDR_B_D50 DDR_B_D51 DDR_B_D52 DDR_B_D53 DDR_B_D54 DDR_B_D55 DDR_B_D56 DDR_B_D57 DDR_B_D58 DDR_B_D59 DDR_B_D60 DDR_B_D61 DDR_B_D62 DDR_B_D63

DDR_B_D0

AK39

A A

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/10/06 2006/10/06

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, M/B LA-3281

401429

星期三七月

06

1

B

of

847, 12, 20

5

D D

LVDSA0+<37> LVDSA1+<37> LVDSA2+<37>

LVDSA0-<37> LVDSA1-<37>

LVDSA2-<37>

LVDSB0+<37> LVDSB1+<37> LVDSB2+<37>

LVDSB0-<37> LVDSB1-<37> LVDSB2-<37>

LVDSAC+<37>

LVDSAC-<37> LVDSBC+<37> LVDSBC-<37>

C C

TV_COMPS

12

R207 150_0603_1%UMA@ R208 150_0603_1%UMA@ R209 150_0603_1%UMA@

B B

12 12

R210 150_0603_1%UMA@ R211 150_0603_1%UMA@ R212 150_0603_1%UMA@

TV_LUMA TV_CRMA

12 12 12

CRT_R CRT_G CRT_B

+2.5VS +3VS

GMCH_ENBKL<16>

GMCH_LVDDEN<16>

TV_COMPS<17> TV_LUMA<17> TV_CRMA<17>

TV_COMPS TV_LUMA TV_CRMA

3VDDCCL<17>

3VDDCDA<17>

CRT_VSYNC<17> CRT_HSYNC<17>

CRT_B<17> CRT_G<17> CRT_R<17>

4

LVDSA0+ LVDSA1+ LVDSA2+

LVDSA0LVDSA1LVDSA2-

LVDSB0+ LVDSB1+ LVDSB2+

LVDSB0LVDSB1LVDSB2-

LVDSAC+ LVDSACLVDSBC+ LVDSBC-

GMCH_ENBKL

LDDC_CLK LDDC_DATA

GMCH_LVDDEN

12

R53 1.5K_0402_1%

R42

12

4.99K_0402_1%

3VDDCCL 3VDDCDA

CRT_VSYNC CRT_HSYNC CRT_B

CRT_G CRT_R

R47

12

255_0402_1%

U14C

H27

SDVOCTRL_DATA

H28

SDVOCTRL_CLK

B37

LA_DATA0

B34

LA_DATA1

A36

LA_DATA2

C37

LA_DATA#0

B35

LA_DATA#1

A37

LA_DATA#2

F30

LB_DATA0

D29

LB_DATA1

F28

LB_DATA2

G30

LB_DATA#0

D30

LB_DATA#1

F29

LB_DATA#2

A32

LA_CLK

A33

LA_CLK#

E26

LB_CLK

E27

LB_CLK#

D32

LBKLT_CTL

J30

LBKLT_EN

H30

LCTLA_CLK

H29

LCTLB_DATA

G26

LDDC_CLK

G25

LDDC_DATA

F32

LVDD_EN

B38

LIBG

C35

LVBG

C33

LVREFH

C32

LVREFL

A16

TVDAC_A

C18

TVDAC_B

A19

TVDAC_C

J20

TV_IREF

B16

TV_IRTNA

B18

TV_IRTNB

B19

TV_IRTNC

J29

TV_DCONSEL1

K30

TV_DCONSEL0

C26

DDCCLK

C25

DDCDATA

H23

VSYNC

G23

HSYNC

E23

BLUE

D23

BLUE#

C22

GREEN

B22

GREEN#

A21

RED

B21

RED#

J22

CRT_IREF

CALISTOGA_FCBGA1466~D

UMA@

3

+1.5VS_PCIE

R54

PEGCOMP

D40

EXP_COMPI

EXP_RXN0 EXP_RXN1 EXP_RXN2 EXP_RXN3 EXP_RXN4 EXP_RXN5 EXP_RXN6 EXP_RXN7 EXP_RXN8

EXP_RXN9 EXP_RXN10 EXP_RXN11 EXP_RXN12 EXP_RXN13 EXP_RXN14 EXP_RXN15

EXP_RXP0

EXP_RXP1

EXP_RXP2

EXP_RXP3

EXP_RXP4

EXP_RXP5

EXP_RXP6

EXP_RXP7

EXP_RXP8

EXP_RXP9 EXP_RXP10 EXP_RXP11 EXP_RXP12 EXP_RXP13 EXP_RXP14 EXP_RXP15

EXP_TXN0

EXP_TXN1

EXP_TXN2

EXP_TXN3

EXP_TXN4

EXP_TXN5

EXP_TXN6

EXP_TXN7

EXP_TXN8

EXP_TXN9 EXP_TXN10 EXP_TXN11 EXP_TXN12 EXP_TXN13 EXP_TXN14 EXP_TXN15

EXP_TXP0

EXP_TXP1

EXP_TXP2

EXP_TXP3

EXP_TXP4

EXP_TXP5

EXP_TXP6

EXP_TXP7

EXP_TXP8

EXP_TXP9

EXP_TXP10 EXP_TXP11 EXP_TXP12 EXP_TXP13 EXP_TXP14 EXP_TXP15

D38 F34

G38 H34 J38 L34 M38 N34 P38 R34 T38 V34 W38 Y34 AA38 AB34 AC38

D34 F38 G34 H38 J34 L38 M34 N38 P34 R38 T34 V38 W34 Y38 AA34 AB38

F36 G40 H36 J40 L36 M40 N36 P40 R36 T40 V36 W40 Y36 AA40 AB36 AC40

D36 F40 G36 H40 J36 L40 M36 N40 P36 R40 T36 V40 W36 Y40 AA36 AB40

PEG_RXN0 PEG_RXN1 PEG_RXN2 PEG_RXN3 PEG_RXN4 PEG_RXN5 PEG_RXN6 PEG_RXN7 PEG_RXN8 PEG_RXN9 PEG_RXN10 PEG_RXN11 PEG_RXN12 PEG_RXN13 PEG_RXN14 PEG_RXN15

PEG_RXP0 PEG_RXP1 PEG_RXP2 PEG_RXP3 PEG_RXP4 PEG_RXP5 PEG_RXP6 PEG_RXP7 PEG_RXP8 PEG_RXP9 PEG_RXP10 PEG_RXP11 PEG_RXP12 PEG_RXP13 PEG_RXP14 PEG_RXP15

PEG_TXN0 PEG_TXN1 PEG_TXN2 PEG_TXN3 PEG_TXN4 PEG_TXN5 PEG_TXN6 PEG_TXN7 PEG_TXN8 PEG_TXN9 PEG_TXN10 PEG_TXN11 PEG_TXN12 PEG_TXN13 PEG_TXN14 PEG_TXN15

PEG_TXP0 PEG_TXP1 PEG_TXP2 PEG_TXP3 PEG_TXP4 PEG_TXP5 PEG_TXP6 PEG_TXP7 PEG_TXP8 PEG_TXP9 PEG_TXP10 PEG_TXP11 PEG_TXP12 PEG_TXP13 PEG_TXP14 PEG_TXP15

EXP_COMPO

LVDS

TV CRT

PCI-EXPRESS GRAPHICS

24.9_0402_1%

1 2

C153 0.1U_0402_16V4ZVGA@ C124 0.1U_0402_16V4ZVGA@ C142 0.1U_0402_16V4ZVGA@ C115 0.1U_0402_16V4ZVGA@ C155 0.1U_0402_16V4ZVGA@ C126 0.1U_0402_16V4ZVGA@ C148 0.1U_0402_16V4ZVGA@ C117 0.1U_0402_16V4ZVGA@ C157 0.1U_0402_16V4ZVGA@ C128 0.1U_0402_16V4ZVGA@ C140 0.1U_0402_16V4ZVGA@ C119 0.1U_0402_16V4ZVGA@ C159 0.1U_0402_16V4ZVGA@ C130 0.1U_0402_16V4ZVGA@ C144 0.1U_0402_16V4ZVGA@ C121 0.1U_0402_16V4ZVGA@

C152 0.1U_0402_16V4ZVGA@ C123 0.1U_0402_16V4ZVGA@ C141 0.1U_0402_16V4ZVGA@ C114 0.1U_0402_16V4ZVGA@ C154 0.1U_0402_16V4ZVGA@ C125 0.1U_0402_16V4ZVGA@ C147 0.1U_0402_16V4ZVGA@ C116 0.1U_0402_16V4ZVGA@ C156 0.1U_0402_16V4ZVGA@ C127 0.1U_0402_16V4ZVGA@ C139 0.1U_0402_16V4ZVGA@ C118 0.1U_0402_16V4ZVGA@ C158 0.1U_0402_16V4ZVGA@ C129 0.1U_0402_16V4ZVGA@ C143 0.1U_0402_16V4ZVGA@ C120 0.1U_0402_16V4ZVGA@

PEG_RXN[0..15] <18>

PEG_RXP[0..15] <18>

PEG_M_TXN0 PEG_M_TXN1 PEG_M_TXN2 PEG_M_TXN3 PEG_M_TXN4 PEG_M_TXN5 PEG_M_TXN6 PEG_M_TXN7 PEG_M_TXN8 PEG_M_TXN9 PEG_M_TXN10 PEG_M_TXN11 PEG_M_TXN12 PEG_M_TXN13 PEG_M_TXN14 PEG_M_TXN15

PEG_M_TXP0 PEG_M_TXP1 PEG_M_TXP2 PEG_M_TXP3 PEG_M_TXP4 PEG_M_TXP5 PEG_M_TXP6 PEG_M_TXP7 PEG_M_TXP8 PEG_M_TXP9 PEG_M_TXP10 PEG_M_TXP11 PEG_M_TXP12 PEG_M_TXP13 PEG_M_TXP14 PEG_M_TXP15

2

PEG_M_TXN[0..15] <18>

PEG_M_TXP[0..15] <18>

1

12

R215

UMA@

2.2K_0402_5%

LDDC_CLK

A A

LDDC_DATA EDI D _ D A T _LCD

5

+2.5VS

R216

2.2K_0402_5%

Q18

BSS138_SOT23

UMA@

Q17

BSS138_SOT23

UMA@

2.2K_0402_5%

S

12

D

13

D

UMA@

12

EDID_CLK_LCD

4

R217

2.2K_0402_5%

UMA@

EDID_CLK_LCD <37>

EDID_DAT_LCD <37>

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/10/06 2006/10/06

Compal Secret Data

Deciphered Date

2

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, M/B LA-3281

401429

星期三七月

06

1

of

947, 12, 20

B

R214

G

2

G

2

5

+VCCP

21

D D

C C

B B

A A

D13

CH751H-40_SC76@

12

+2.5VS

R221

10_0402_5%@

+1.5VS

21

D12

12

+3VS

R220

10_0402_5%@

1

C50

C24

2

4.7U_0805_10V4Z

1

C94

2

1

0.22U_0603_10V7K

2

C91

2.2U_0805_16V4Z

C12

220U_D2_4VM

1

2

1

2

0.22U_0603_10V7K

+1.5VS

1

+

2

MCH_A6

C296

0.47U_0603_10V7K

MCH_D2

C10

0.47U_0603_10V7K

+VCCP

MCH_AB1

1

2

U14H

AC14

VTT0

AB14

VTT1

W14

VTT2

V14

VTT3

T14

VTT4

R14

VTT5

P14

VTT6

N14

VTT7

M14

VTT8

L14

VTT9

AD13

VTT10

AC13

VTT11

AB13

VTT12

AA13

VTT13

Y13

VTT14

W13

VTT15

V13

VTT16

U13

VTT17

T13

VTT18

R13

VTT19

N13

VTT20

M13

VTT21

L13

VTT22

AB12

VTT23

AA12

VTT24

Y12

VTT25

W12

VTT26

V12

VTT27

U12

VTT28

T12

VTT29

R12

VTT30

P12

VTT31

N12

VTT32

M12

VTT33

L12

VTT34

R11

VTT35

P11

VTT36

N11

VTT37

M11

VTT38

R10

VTT39

P10

VTT40

N10

VTT41

M10

VTT42

P9

VTT43

N9

VTT44

M9

VTT45

R8

VTT46

P8

VTT47

N8

VTT48

M8

VTT49

P7

VTT50

N7

VTT51

M7

VTT52

R6

VTT53

P6

VTT54

M6

VTT55

A6

VTT56

R5

VTT57

P5

VTT58

N5

VTT59

M5

VTT60

P4

VTT61

N4

VTT62

M4

VTT63

R3

VTT64

P3

VTT65

N3

VTT66

M3

VTT67

R2

VTT68

P2

VTT69

M2

VTT70

D2

VTT71

AB1

VTT72

R1

VTT73

P1

VTT74

N1

VTT75

M1

VTT76

AG14

VCCAUX32

AF14

VCCAUX33

AE14

VCCAUX34

Y14

VCCAUX35

AF13

VCCAUX36

AE13

VCCAUX37

AF12

VCCAUX38

AE12

VCCAUX39

AD12

VCCAUX40

CALISTOGA_FCBGA1466~D

UMA@

P O W E R

4

VCCA_CRTDAC0 VCCA_CRTDAC1 VSSA_CRTDAC2

VCCA_TVDACA0 VCCA_TVDACA1 VCCA_TVDACB0 VCCA_TVDACB1 VCCA_TVDACC0 VCCA_TVDACC1

VCCDQ_TVDAC

VCC_SYNC

VCCTX_LVDS0 VCCTX_LVDS1 VCCTX_LVDS2

VCC3G0 VCC3G1 VCC3G2 VCC3G3 VCC3G4 VCC3G5 VCC3G6

VCCA_3GPLL

VCCA_3GBG VSSA_3GBG

VCCA_DPLLA VCCA_DPLLB

VCCA_HPLL

VCCA_LVDS

VSSA_LVDS

VCCA_MPLL VCCA_TVBG

VSSA_TVBG

VCCD_HMPLL0 VCCD_HMPLL1

VCCD_LVDS0 VCCD_LVDS1 VCCD_LVDS2

VCCD_TVDAC

VCCHV0 VCCHV1 VCCHV2

VCCAUX0 VCCAUX1 VCCAUX2 VCCAUX3 VCCAUX4 VCCAUX5 VCCAUX6 VCCAUX7 VCCAUX8

VCCAUX9 VCCAUX10 VCCAUX11 VCCAUX12 VCCAUX13 VCCAUX14 VCCAUX15 VCCAUX16 VCCAUX17 VCCAUX18 VCCAUX19 VCCAUX20 VCCAUX21 VCCAUX22 VCCAUX23 VCCAUX24 VCCAUX25 VCCAUX26 VCCAUX27 VCCAUX28 VCCAUX29 VCCAUX30 VCCAUX31

H22

B30 C30 A30

AB41 AJ41 L41 N41 R41 V41 Y41

AC33 G41 H41

E21 F21 G21

B26 C39 AF1

A38 B39

AF2 H20

G20

E19 F19 C20 D20 E20 F20

AH1 AH2

A28 B28 C28

D21 H19

A23 B23 B25

AK31 AF31 AE31 AC31 AL30 AK30 AJ30 AH30 AG30 AF30 AE30 AD30 AC30 AG29 AF29 AE29 AD29 AC29 AG28 AF28 AE28 AH22 AJ21 AH21 AJ20 AH20 AH19 P19 P16 AH15 P15 AH14

+2.5VS

1 2

C306

0.1U_0402_16V4Z

+2.5VS

W=40 mils

+1.5VS_3GPLL +2.5VS

+2.5VS_CRTDAC

+1.5VS_DPLLA +1.5VS_DPLLB +1.5VS_HPLL

+2.5VS

+1.5VS_MPLL +3VS_TVBG

+3VS_TVDACA +3VS_TVDACA +3VS_TVDACA

+1.5VS

+1.5VS_TVDAC

1

2

C302

0.1U_0402_16V4Z

+1.5VS

1

C299

2

C108

C298

0.1U_0402_16V4Z

10U_1206_6.3V6M

+1.5VS_PCIE

1

+

2

220U_D2_4VM

1

2

+3VS

1

2

3

1

C107

C105

2

10U_1206_6.3V6M

L4 FBM-11-160808-601-T_0603

1 2

1

C72

C71

2

2200P_0402_50V7K

R57

0_0805_5%

12

+1.5VS

10U_1206_6.3V6M

+2.5VS

CRTDAC: Route caps within 250mil of Alviso. Route FB within 3" of Calistoga

0.1U_0402_16V4Z

+2.5VS

1

C102

C304

2

0.01U_0402_16V7K

close pin A38

R205

0_0805_5%

1

C49

2

C63

0.1U_0402_16V4Z

2200P_0402_50V7K

close pin G41

1

2

0.1U_0402_16V4Z

+3VS+3VS_TVBG

12

+2.5VS

2

1

C99

2

0.1U_0402_16V4Z

+1.5VS_DPLLA +1.5VS_DPLLB

0.1U_0402_16V4Z

L16

1 2

FBM-L10-160808-301-T_0603

330U_D2E_2.5VM

UMA@

1

C82

C300

1

+

2

1

C55

2

2200P_0402_50V7K

C54

PCI-E/MEM/PSB PLL decoupling

R56 0_0603_5%

1

C98

C97

2

0.1U_0402_16V4Z

10U_1206_6.3V6M

+1.5VS_MPLL

45mA Max. 45mA Max.

C13

R16 0_0603_5%

1

C8

2

0.1U_0402_16V4Z

10U_1206_6.3V6M

1

L5

1 2

FBM-L10-160808-301-T_0603

0.1U_0402_16V4Z

330U_D2E_2.5VM

UMA@

1

C101

C100

1

+

2

1

C297

2

0.1U_0402_16V4Z

12

2200P_0402_50V7K

+1.5VS+1.5VS_3GPLL

C104

@

+1.5VS_TVDAC +1.5VS

1

C67

2

0.1U_0402_16V4Z

C58

0.1U_0402_16V4Z

1

2

0.1U_0402_16V4Z

1

2

1

C37

2

2200P_0402_50V7K

+1.5VS_HPLL

1

C14

2

0.1U_0402_16V4Z

1

C45

2

2200P_0402_50V7K

R213 0_0603_5%

1

C9

2

C46

0.1U_0402_16V4Z

12

R17 0_0603_5%

10U_1206_6.3V6M

0_0603_5%

C301

@

0.1U_0402_16V4Z

R206

+1.5VS+1.5VS

+3VS+3VS_TVDACA+3VS_TVDACA+3VS_TVDACA

12

1

2

12

+1.5VS+1.5VS

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMAT ION IT CON TAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/10/06 2006/10/06

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, M / B LA-3281

401429

期三七月

1

B

of

10 47¬P , 12, 2006

5

4

3

2

1

Strap Pin Table

CFG[3:17] have internal pull up

+VCCP

D D

1

C69

2

0.22U_0603_10V7K

1

C48

2

10U_1206_6.3V6M

C C

B B

1

C61

C25

2

0.22U_0603_10V7K

1

C95

C31

2

1U_0603_10V4Z

10U_1206_6.3V6M

1

+

220U_D2_4VM

C18

2

1

+

C79

220U_D2_4VM@

2

+VCCP

U14F

AD27

VCC_NCTF0

AC27

VCC_NCTF1

AB27

VCC_NCTF2

AA27

VCC_NCTF3

Y27

VCC_NCTF4

W27

VCC_NCTF5

V27

VCC_NCTF6

U27

VCC_NCTF7

T27

VCC_NCTF8

R27

VCC_NCTF9

AD26

VCC_NCTF10

AC26

VCC_NCTF11

AB26

VCC_NCTF12

AA26

VCC_NCTF13

Y26

VCC_NCTF14

W26

VCC_NCTF15

V26

VCC_NCTF16

U26

VCC_NCTF17

T26

VCC_NCTF18

R26

VCC_NCTF19

AD25

VCC_NCTF20

AC25

VCC_NCTF21

AB25

VCC_NCTF22

AA25

VCC_NCTF23

Y25

VCC_NCTF24

W25

VCC_NCTF25

V25

VCC_NCTF26

U25

VCC_NCTF27

T25

VCC_NCTF28

R25

VCC_NCTF29

AD24

VCC_NCTF30

AC24

VCC_NCTF31

AB24

VCC_NCTF32

AA24

VCC_NCTF33

Y24

VCC_NCTF34

W24

VCC_NCTF35

V24

VCC_NCTF36

U24

VCC_NCTF37

T24

VCC_NCTF38

R24

VCC_NCTF39

AD23

VCC_NCTF40

V23

VCC_NCTF41

U23

VCC_NCTF42

T23

VCC_NCTF43

R23

VCC_NCTF44

AD22

VCC_NCTF45

V22

VCC_NCTF46

U22

VCC_NCTF47

T22

VCC_NCTF48

R22

VCC_NCTF49

AD21

VCC_NCTF50

V21

VCC_NCTF51

U21

VCC_NCTF52

T21

VCC_NCTF53

R21

VCC_NCTF54

AD20

VCC_NCTF55

V20

VCC_NCTF56

U20

VCC_NCTF57

T20

VCC_NCTF58

R20

VCC_NCTF59

AD19

VCC_NCTF60

V19

VCC_NCTF61

U19

VCC_NCTF62

T19

VCC_NCTF63

AD18

VCC_NCTF64

AC18

VCC_NCTF65

AB18

VCC_NCTF66

AA18

VCC_NCTF67

Y18

VCC_NCTF68

W18

VCC_NCTF69

V18

VCC_NCTF70

U18

VCC_NCTF71

T18

VCC_NCTF72

M19

VCC100

L19

VCC101

N18

VCC102

M18

VCC103

L18

VCC104

P17

VCC105

N17

VCC106

M17

VCC107

N16

VCC108

M16

VCC109

L16

VCC110

CALISTOGA_FCBGA1466~D

UMA@

VCCAUX_NCTF0 VCCAUX_NCTF1 VCCAUX_NCTF2 VCCAUX_NCTF3 VCCAUX_NCTF4 VCCAUX_NCTF5 VCCAUX_NCTF6 VCCAUX_NCTF7 VCCAUX_NCTF8

VCCAUX_NCTF9 VCCAUX_NCTF10 VCCAUX_NCTF11 VCCAUX_NCTF12 VCCAUX_NCTF13 VCCAUX_NCTF14 VCCAUX_NCTF15 VCCAUX_NCTF16 VCCAUX_NCTF17 VCCAUX_NCTF18 VCCAUX_NCTF19 VCCAUX_NCTF20 VCCAUX_NCTF21 VCCAUX_NCTF22 VCCAUX_NCTF23 VCCAUX_NCTF24 VCCAUX_NCTF25 VCCAUX_NCTF26 VCCAUX_NCTF27 VCCAUX_NCTF28 VCCAUX_NCTF29 VCCAUX_NCTF30 VCCAUX_NCTF31 VCCAUX_NCTF32 VCCAUX_NCTF33 VCCAUX_NCTF34 VCCAUX_NCTF35 VCCAUX_NCTF36

P O W E R

VCCAUX_NCTF37 VCCAUX_NCTF38 VCCAUX_NCTF39 VCCAUX_NCTF40 VCCAUX_NCTF41 VCCAUX_NCTF42 VCCAUX_NCTF43 VCCAUX_NCTF44 VCCAUX_NCTF45 VCCAUX_NCTF46 VCCAUX_NCTF47 VCCAUX_NCTF48 VCCAUX_NCTF49 VCCAUX_NCTF50 VCCAUX_NCTF51 VCCAUX_NCTF52 VCCAUX_NCTF53 VCCAUX_NCTF54 VCCAUX_NCTF55 VCCAUX_NCTF56 VCCAUX_NCTF57

VSS_NCTF0 VSS_NCTF1 VSS_NCTF2 VSS_NCTF3 VSS_NCTF4 VSS_NCTF5 VSS_NCTF6 VSS_NCTF7 VSS_NCTF8

VSS_NCTF9 VSS_NCTF10 VSS_NCTF11 VSS_NCTF12

VCC_SM100

VCC_SM101

VCC_SM102

VCC_SM103

VCC_SM104

VCC_SM105

VCC_SM106

VCC_SM107

AG27 AF27 AG26 AF26 AG25 AF25 AG24 AF24 AG23 AF23 AG22 AF22 AG21 AF21 AG20 AF20 AG19 AF19 R19 AG18 AF18 R18 AG17 AF17 AE17 AD17 AB17 AA17 W17 V17 T17 R17 AG16 AF16 AE16 AD16 AC16 AB16 AA16 Y16 W16 V16 U16 T16 R16 AG15 AF15 AE15 AD15 AC15 AB15 AA15 Y15 W15 V15 U15 T15 R15

AE27 AE26 AE25 AE24 AE23 AE22 AE21 AE20 AE19 AE18 AC17 Y17 U17

AR6 AP6 AN6 AL6 AK6 AJ6 AV1 AJ1

+1.5VS

+1.8V

1

C17

C15

2

0.47U_0603_10V7K

Place near pin AV1 & AJ1

A A

+VCCP

AA33

W33

AA32

W32

AA31

W31

AA30

W30

AA29

W29

AB28 AA28

AB23 AA23

AC22 AB22

W22

AC21 AA21

W21

AC20 AB20

W20

AB19 AA19

U14G

VCC0 VCC1

P33

VCC2

N33

VCC3

L33

VCC4

J33

VCC5 VCC6

Y32

VCC7 VCC8

V32

VCC9

P32

VCC10

N32

VCC11

M32

VCC12

L32

VCC13

J32

VCC14 VCC15 VCC16

V31

VCC17

T31

VCC18

R31

VCC19

P31

VCC20

N31

VCC21

M31

VCC22 VCC23

Y30

VCC24 VCC25

V30

VCC26

U30

VCC27

T30

VCC28

R30

VCC29

P30

VCC30

N30

VCC31

M30

VCC32

L30 Y29

V29 U29 R29

P29 M29

L29

Y28

V28 U28

T28 R28

P28 N28 M28

L28

P27 N27 M27

L27

P26 N26

L26 N25 M25

L25

P24 N24 M24

Y23

P23 N23 M23

L23

Y22

P22 N22 M22

L22

N21 M21

L21

Y20

P20 N20 M20

L20

Y19 N19

P O W E R

VCC33 VCC34 VCC35 VCC36 VCC37 VCC38 VCC39 VCC40 VCC41 VCC42 VCC43 VCC44 VCC45 VCC46 VCC47 VCC48 VCC49 VCC50 VCC51 VCC52 VCC53 VCC54 VCC55 VCC56 VCC57 VCC58 VCC59 VCC60 VCC61 VCC62 VCC63 VCC64 VCC65 VCC66 VCC67 VCC68 VCC69 VCC70 VCC71 VCC72 VCC73 VCC74 VCC75 VCC76 VCC77 VCC78 VCC79 VCC80 VCC81 VCC82 VCC83 VCC84 VCC85 VCC86 VCC87 VCC88 VCC89 VCC90 VCC91 VCC92 VCC93 VCC94 VCC95 VCC96 VCC97 VCC98 VCC99

CALISTOGA_FCBGA1466~D

UMA@

VCC_SM0 VCC_SM1 VCC_SM2 VCC_SM3 VCC_SM4 VCC_SM5 VCC_SM6 VCC_SM7 VCC_SM8

VCC_SM9 VCC_SM10 VCC_SM11 VCC_SM12 VCC_SM13 VCC_SM14 VCC_SM15 VCC_SM16 VCC_SM17 VCC_SM18 VCC_SM19 VCC_SM20 VCC_SM21 VCC_SM22 VCC_SM23 VCC_SM24 VCC_SM25 VCC_SM26 VCC_SM27 VCC_SM28 VCC_SM29 VCC_SM30 VCC_SM31 VCC_SM32 VCC_SM33 VCC_SM34 VCC_SM35 VCC_SM36 VCC_SM37 VCC_SM38 VCC_SM39 VCC_SM40 VCC_SM41 VCC_SM42 VCC_SM43 VCC_SM44 VCC_SM45 VCC_SM46 VCC_SM47 VCC_SM48 VCC_SM49 VCC_SM50 VCC_SM51 VCC_SM52 VCC_SM53 VCC_SM54 VCC_SM55 VCC_SM56 VCC_SM57 VCC_SM58 VCC_SM59 VCC_SM60 VCC_SM61 VCC_SM62 VCC_SM63 VCC_SM64 VCC_SM65 VCC_SM66 VCC_SM67 VCC_SM68 VCC_SM69 VCC_SM70 VCC_SM71 VCC_SM72 VCC_SM73 VCC_SM74 VCC_SM75 VCC_SM76 VCC_SM77 VCC_SM78 VCC_SM79 VCC_SM80 VCC_SM81 VCC_SM82 VCC_SM83 VCC_SM84 VCC_SM85 VCC_SM86 VCC_SM87 VCC_SM88 VCC_SM89 VCC_SM90 VCC_SM91 VCC_SM92 VCC_SM93 VCC_SM94 VCC_SM95 VCC_SM96 VCC_SM97 VCC_SM98 VCC_SM99

AU41 AT41 AM41 AU40 BA34 AY34 AW34 AV34 AU34 AT34 AR34 BA30 AY30 AW30 AV30 AU30 AT30 AR30 AP30 AN30 AM30 AM29 AL29 AK29 AJ29 AH29 AJ28 AH28 AJ27 AH27 BA26 AY26 AW26 AV26 AU26 AT26 AR26 AJ26 AH26 AJ25 AH25 AJ24 AH24 BA23 AJ23 BA22 AY22 AW22 AV22 AU22 AT22 AR22 AP22 AK22 AJ22 AK21 AK20 BA19 AY19 AW19 AV19 AU19 AT19 AR19 AP19 AK19 AJ19 AJ18 AJ17 AH17 AJ16 AH16 BA15 AY15 AW15 AV15 AU15 AT15 AR15 AJ15 AJ14 AJ13 AH13 AK12 AJ12 AH12 AG12 AK11 BA8 AY8 AW8 AV8 AT8 AR8 AP8 BA6 AY6 AW6 AV6 AT6

+1.8V

MCH_AT41 MCH_AM41

1

C106

C103

2

0.47U_0603_10V7K

Place near pin AT41 & AM41

1

C21

C20

2

0.1U_0402_16V4Z

1

C27

2

0.47U_0603_10V7K

Place near pin BA23

1

C78

C44

C93

2

10U_1206_6.3V6M

1

2

0.47U_0603_10V7K

Place near pin BA15

CFG[2:0]

CFG5

CFG7

CFG9

CFG6

PSB 4X CLK Enable 1 = Calistoga

CFG[13:12]

CFG16

0.1U_0402_16V4Z

CFG10 CFG18

CFG19

SDVO_CTRLDATA

1

C86

C47

2

0.1U_0402_16V4Z

CFG20

(PCIE/SDVO select)

1

+

C59

2

220U_D2_4M_R45@

CFG[19:18] have internal pull down

011 = 667MT/s FSB 001 = 533MT/s FSB

0 = DMI x 2 1 = DMI x 4

0 = Reserved 1 = Mobile Yonah CPU

0 = Lane Reversal Enable 1 = Normal Operation

(Default)

*

(Default)

*

(Default)

0 = Reserved

*

00 = Reserved 01 = XOR Mode Enabled 10 = All Z Mode Enabled 11 = Normal Operation

0 = Dynamic ODT Disabled 1 = Dynamic ODT Enabled (Default)

10 = 1.05V 01 = 1.5V

0 = Normal Operation 1 = DMI Lane Reversal Enable

0 = No SDVO Device Present

*

(Default)

1 = SDVO Device Present

0 = Only PCIE or SDVO is operational. 1 = PCIE/SDVO are operating simu.

R32 2.2K_0402_5%@

CFG5<7>

R40 2.2K_0402_5%@

CFG7<7>

R37 2.2K_0402_5%@

CFG9<7> CFG11<7> CFG12<7> CFG13<7> CFG16<7>

CFG18<7> CFG19<7> CFG20<7>

R35 2.2K_0402_5%@ R34 2.2K_0402_5%@ R38 2.2K_0402_5%@ R33 2.2K_0402_5%@

R48 1K_0402_5%@ R50 1K_0402_5%@ R51 1K_0402_5%@

*

1 2 1 2 1 2 1 2 1 2 1 2 1 2

1 2 1 2 1 2

*

(Default)

*

(Default)

*

(Default)

*

+3VS

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/10/06 2006/10/06

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, M/B LA-3281

401429

星期三七月

06

1

B

of

11 47, 12, 20

5

4

3

2

1

U14I

AC41

VSS0

AA41

VSS1

W41

VSS2

T41

VSS3

P41

VSS4

M41

D D

C C

B B

A A

VSS5

J41

VSS6

F41

VSS7

AV40

VSS8

AP40

VSS9

AN40

VSS10

AK40

VSS11

AJ40

VSS12

AH40

VSS13

AG40

VSS14

AF40

VSS15

AE40

VSS16

B40

VSS17

AY39

VSS18

AW39

VSS19

AV39

VSS20

AR39

VSS21

AN39

VSS22

AJ39

VSS23

AC39

VSS24

AB39

VSS25

AA39

VSS26

Y39

VSS27

W39

VSS28

V39

VSS29

T39

VSS30

R39

VSS31

P39

VSS32

N39

VSS33

M39

VSS34

L39

VSS35

J39

VSS36

H39

VSS37

G39

VSS38

F39

VSS39

D39

VSS40

AT38

VSS41

AM38

VSS42

AH38

VSS43

AG38

VSS44

AF38

VSS45

AE38

VSS46

C38

VSS47

AK37

VSS48

AH37

VSS49

AB37

VSS50

AA37

VSS51

Y37

VSS52

W37

VSS53

V37

VSS54

T37

VSS55

R37

VSS56

P37

VSS57

N37

VSS58

M37

VSS59

L37

VSS60

J37

VSS61

H37

VSS62

G37

VSS63

F37

VSS64

D37

VSS65

AY36

VSS66

AW36

VSS67

AN36

VSS68

AH36

VSS69

AG36

VSS70

AF36

VSS71

AE36

VSS72

AC36

VSS73

C36

VSS74

B36

VSS75

BA35

VSS76

AV35

VSS77

AR35

VSS78

AH35

VSS79

AB35

VSS80

AA35

VSS81

Y35

VSS82

W35

VSS83

V35

VSS84

T35

VSS85

R35

VSS86

P35

VSS87

N35

VSS88

M35

VSS89

L35

VSS90

J35

VSS91

H35

VSS92

G35

VSS93

F35

VSS94

D35

VSS95

AN34

VSS96

AK34

VSS97

AG34

VSS98

AF34

VSS99

CALISTOGA_FCBGA1466~D

UMA@

P O W E R

VSS100 VSS101 VSS102 VSS103 VSS104 VSS105 VSS106 VSS107 VSS108 VSS109 VSS110 VSS111 VSS112 VSS113 VSS114 VSS115 VSS116 VSS117 VSS118 VSS119 VSS120 VSS121 VSS122 VSS123 VSS124 VSS125 VSS126 VSS127 VSS128 VSS129 VSS130 VSS131 VSS132 VSS133 VSS134 VSS135 VSS136 VSS137 VSS138 VSS139 VSS140 VSS141 VSS142 VSS143 VSS144 VSS145 VSS146 VSS147 VSS148 VSS149 VSS150 VSS151 VSS152 VSS153 VSS154 VSS155 VSS156 VSS157 VSS158 VSS159 VSS160 VSS161 VSS162 VSS163 VSS164 VSS165 VSS166 VSS167 VSS168 VSS169 VSS170 VSS171 VSS172 VSS173 VSS174 VSS175 VSS176 VSS177 VSS178 VSS179 VSS180 VSS181 VSS182 VSS183 VSS184 VSS185 VSS186 VSS187 VSS188 VSS189 VSS190 VSS191 VSS192 VSS193 VSS194 VSS195 VSS196 VSS197 VSS198 VSS199

AE34 AC34 C34 AW33 AV33 AR33 AE33 AB33 Y33 V33 T33 R33 M33 H33 G33 F33 D33 B33 AH32 AG32 AF32 AE32 AC32 AB32 G32 B32 AY31 AV31 AN31 AJ31 AG31 AB31 Y31 AB30 E30 AT29 AN29 AB29 T29 N29 K29 G29 E29 C29 B29 A29 BA28 AW28 AU28 AP28 AM28 AD28 AC28 W28 J28 E28 AP27 AM27 AK27 J27 G27 F27 C27 B27 AN26 M26 K26 F26 D26 AK25 P25 K25 H25 E25 D25 A25 BA24 AU24 AL24 AW23 AT23 AN23 AM23 AH23 AC23 W23 K23 J23 F23 C23 AA22 K22 G22 F22 E22 D22 A22 BA21 AV21 AR21

U14J

AN21

VSS200

AL21

VSS201

AB21

VSS202

Y21

VSS203

P21

VSS204

K21

VSS205

J21

VSS206

H21

VSS207

C21

VSS208

AW20

VSS209

AR20

VSS210

AM20

VSS211

AA20

VSS212

K20

VSS213

B20

VSS214

A20

VSS215

AN19

VSS216

AC19

VSS217

W19

VSS218

K19

VSS219

G19

VSS220

C19

VSS221

AH18

VSS222

P18

VSS223

H18

VSS224

D18

VSS225

A18

VSS226

AY17

VSS227

AR17

VSS228

AP17

VSS229

AM17

VSS230

AK17

VSS231

AV16

VSS232

AN16

VSS233

AL16

VSS234

J16

VSS235

F16

VSS236

C16

VSS237

AN15

VSS238

AM15

VSS239

AK15

VSS240

N15

VSS241

M15

VSS242

L15

VSS243

B15

VSS244

A15

VSS245

BA14

VSS246

AT14

VSS247

AK14

VSS248

AD14

VSS249

AA14

VSS250

U14

VSS251

K14

VSS252

H14

VSS253

E14

VSS254

AV13

VSS255

AR13

VSS256

AN13

VSS257

AM13

VSS258

AL13

VSS259

AG13

VSS260

P13

VSS261

F13

VSS262

D13

VSS265

B13

VSS264

AY12

VSS263

AC12

VSS266

K12

VSS267

H12

VSS268

E12

VSS269

AD11

VSS270

AA11

VSS271

Y11

VSS272

J11

VSS273

D11

VSS274

B11

VSS275

AV10

VSS276

AP10

VSS277

AL10

VSS278

AJ10

VSS279

CALISTOGA_FCBGA1466~D

UMA@

P O W E R

VSS280 VSS281 VSS282 VSS283 VSS284 VSS285 VSS286 VSS287 VSS288 VSS289 VSS290 VSS292 VSS291 VSS293 VSS294 VSS295 VSS296 VSS297 VSS298 VSS299 VSS300 VSS301 VSS302 VSS303 VSS304 VSS305 VSS306 VSS307 VSS308 VSS309 VSS310 VSS311 VSS312 VSS313 VSS314 VSS315 VSS316 VSS317 VSS318 VSS319 VSS320 VSS321 VSS322 VSS323 VSS324 VSS325 VSS326 VSS327 VSS328 VSS329 VSS330 VSS331 VSS332 VSS333 VSS334 VSS335 VSS336 VSS337 VSS338 VSS339 VSS340 VSS341 VSS342 VSS343 VSS344 VSS345 VSS346 VSS347 VSS348 VSS349 VSS350 VSS351 VSS352 VSS353 VSS354 VSS355 VSS356 VSS357 VSS358 VSS359 VSS360

AG10 AC10 W10 U10 BA9 AW9 AR9 AH9 AB9 Y9 R9 G9 E9 A9 AG8 AD8 AA8 U8 K8 C8 BA7 AV7 AP7 AL7 AJ7 AH7 AF7 AC7 R7 G7 D7 AG6 AD6 AB6 Y6 U6 N6 K6 H6 B6 AV5 AF5 AD5 AY4 AR4 AP4 AL4 AJ4 Y4 U4 R4 J4 F4 C4 AY3 AW3 AV3 AL3 AH3 AG3 AF3 AD3 AC3 AA3 G3 AT2 AR2 AP2 AK2 AJ2 AD2 AB2 Y2 U2 T2 N2 J2 H2 F2 C2 AL1

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/10/06 2006/10/06

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, M/B LA-3281

401429

星期三七月

06

1

B

of

12 47, 12, 20

5

DDR_A_DQS#[0..7]<8>

DDR_A_D[0..63]<8>

DDR_A_DM[0..7]<8> DDR_A_DQS[0..7]<8> DDR_A_MA[0..13]<8>

D D

Layout Note: Place near JP41

+1.8V

0.1U_0402_16V4Z

2.2U_0805_16V4Z

C89

C87

1

2

C C

Layout Note: Place one cap close to every 2 pullup resistors terminated to +0.9VS

+0.9VS

0.1U_0402_16V4Z

B B

DDR_A_WE# DDR_A_CAS# DDR_CS1_DIMMA# M_ODT1

DDR_A_BS#0 DDR_A_MA10

DDR_A_MA1 DDR_A_MA3 DDR_A_MA5

A A

DDR_A_MA8

DDR_A_MA9 DDR_A_MA12 DDR_A_BS#2 DDR_CKE0_DIMMA

1

2

C74

0.1U_0402_16V4Z

1

2

C66

1 8 2 7 3 6 4 5

56_0804_8P4R_5%

56_0402_5%

R39

1 2

R43

1 2

4 5 3 6 2 7 1 8

56_0804_8P4R_5%

4 5 3 6 2 7 1 8

56_0804_8P4R_5%

5

2.2U_0805_16V4Z

1

2

0.1U_0402_16V4Z

1

2

C60

RP1

56_0402_5%

RP7

RP10

2.2U_0805_16V4Z

C28

1

2

0.1U_0402_16V4Z

1

2

C51

+0.9VS

56_0804_8P4R_5%

1

2

RP2

RP6

C92

C42

RP9

2.2U_0805_16V4Z C30

1

2

0.1U_0402_16V4Z

1

2

C34

DDR_A_RAS#

18

DDR_CS0_DIMMA#

27

M_ODT0

36

DDR_A_MA13

45

DDR_A_BS#1

45

DDR_A_MA0

36

DDR_A_MA2

27

DDR_A_MA4

18

DDR_A_MA6

45

DDR_A_MA7

36

DDR_A_MA11

27

DDR_CKE1_DIMMA

18

0.1U_0402_16V4Z

C85

1

2

0.1U_0402_16V4Z

1

2

C53

C40

0.1U_0402_16V4Z

C57

0.1U_0402_16V4Z

1

2

C64

4

+DDR_MCH_REF1<14>

0.1U_0402_16V4Z C83

C43

1

2

0.1U_0402_16V4Z

1

2

C77

C39

Layout Note: Place these resistor closely JP41,all trace length Max=1.5"

4

3

Layout Note: +DDR_MCH_REF trace width and spacing is 20/20.

+1.8V

12

R86

+DDR_MCH_REF1

1

C149

2

0.1U_0402_16V4Z

1

2

C33

C70

100_0402_1%

12

R87

100_0402_1%

EC_P80_DATA<14,33>

DDR_CKE0_DIMMA<7>

EC_P80_CLK<14,33>

DDR_A_BS#2<8>

DDR_A_BS#0<8>

DDR_A_WE#<8>

DDR_A_CAS#<8>

DDR_CS1_DIMMA#<7>

M_ODT1<7>

CLK_SMBDATA<14,15>

CLK_SMBCLK<14,15>

DDR_A_D4 DDR_A_D1

DDR_A_DQS#0 DDR_A_DQS0

DDR_A_D2 DDR_A_D3

DDR_A_D8 DDR_A_D14

DDR_A_DQS#1 DDR_A_DQS1

DDR_A_D9 DDR_A_D11 DDR_A_D15 DDR_A_D10

DDR_A_D16 DDR_A_D17

DDR_A_DQS#2 DDR_A_DQS2

DDR_A_D18 DDR_A_D19

DDR_A_DM3

EC_P80_DATA

DDR_A_D26 DDR_A_D27

DDR_CKE0_DIMMA

EC_P80_CLK

DDR_A_BS#2 DDR_A_MA12

DDR_A_MA9 DDR_A_MA7 DDR_A_MA8

DDR_A_MA5 DDR_A_MA3 DDR_A_MA1

DDR_A_MA10 DDR_A_BS#0 DDR_A_WE#

DDR_A_CAS# DDR_CS1_DIMMA#

M_ODT1 DDR_A_D37

DDR_A_D36 DDR_A_DQS#4

DDR_A_DQS4 DDR_A_D35

DDR_A_D32 DDR_A_D40

DDR_A_D44 DDR_A_DM5 DDR_A_D41

DDR_A_D46 DDR_A_D49

DDR_A_D48

DDR_A_DQS#6 DDR_A_DQS6

DDR_A_D50 DDR_A_D61 DDR_A_D57

DDR_A_D60 DDR_A_DM7 DDR_A_D59

DDR_A_D58 CLK_SMBDATA

CLK_SMBCLK

0.1U_0402_16V4Z

+3VS

C7

+1.8V

1

2

JP3

1

VREF

3

VSS

5

DQ0

7

DQ1

9

VSS

11

DQS0#

13

DQS0

15

VSS

17

DQ2

19

DQ3

21

VSS

23

DQ8

25

DQ9

27

VSS

29

DQS1#

31

DQS1

33

VSS

35

DQ10

37

DQ11

39

VSS

41

VSS

43

DQ16

45

DQ17

47

VSS

49

DQS2#

51

DQS2

53

VSS

55

DQ18

57

DQ19

59

VSS

61

DQ24

63

DQ25

65

VSS

67

DM3

69

NC

71

VSS

73

DQ26

75

DQ27

77

VSS

79

CKE0

81

VDD

83

NC

85

BA2

87

VDD

89

A12

91

A9

93

A8

95

VDD

97

A5

99

A3

101

A1

103

VDD

105

A10/AP

107

BA0

109

WE#

111

VDD

113

CAS#

115

NC/S1#

117

VDD

119

NC/ODT1

121

VSS

123

DQ32

125

DQ33

127

VSS

129

DQS4#

131

DQS4

133

VSS

135

DQ34

137

DQ35

139

VSS

141

DQ40

143

DQ41

145

VSS

147

DM5

149

VSS

151

DQ42

153

DQ43

155

VSS

157

DQ48

159

DQ49

161

VSS

163

NC,TEST

165

VSS

167

DQS6#

169

DQS6

171

VSS

173

DQ50

175

DQ51

177

VSS

179

DQ56

181

DQ57

183

VSS

185

DM7

187

VSS

189

DQ58

191

DQ59

193

VSS

195

SDA

197

SCL

199

VDDSPD

FOX_ASOA426-M2RN-7F

ME@

SO-DIMM A

DQ4 DQ5

DM0 DQ6

DQ7

DQ12 DQ13

DM1

CK0#

DQ14 DQ15

DQ20 DQ21

DM2

DQ22 DQ23

DQ28 DQ29

DQS3#

DQS3 DQ30

DQ31

NC/CKE1

VDD NC/A15 NC/A14

VDD

RAS#

VDD

ODT0

NC/A13

VDD

DQ36 DQ37

DM4

DQ38 DQ39

DQ44 DQ45

DQS5#

DQS5 DQ46

DQ47 DQ52

DQ53

CK1#

DM6

DQ54 DQ55

DQ60 DQ61

DQS7#

DQS7 DQ62

DQ63

VSS

VSS VSS

VSS

VSS VSS

CK0 VSS

VSS

A11

BA1 S0#

VSS

VSS VSS

VSS

VSS CK1

VSS VSS

VSS

VSS SA0 SA1

2

+1.8V

+DDR_MCH_REF1

2

DDR_A_D6

4

DDR_A_D0

6 8

DDR_A_DM0

10 12

DDR_A_D5

14

DDR_A_D7

16 18

DDR_A_D13

20

DDR_A_D12

22 24

DDR_A_DM1

26 28

M_CLK_DDR0

30

M_CLK_DDR#0

32 34 36 38 40

42

DDR_A_D20

44

DDR_A_D21

46 48 50

NC

A7 A6

A4 A2 A0

NC

DDR_A_DM2

52 54

DDR_A_D23

56

DDR_A_D22

58 60

DDR_A_D28DDR_A_D29

62

DDR_A_D25DDR_A_D24

64 66

DDR_A_DQS#3

68

DDR_A_DQS3

70 72

DDR_A_D31

74

DDR_A_D30

76 78

DDR_CKE1_DIMMA

80 82 84 86 88

DDR_A_MA11

90 92

DDR_A_MA6

94 96

DDR_A_MA4

98

DDR_A_MA2

100

DDR_A_MA0

102 104

DDR_A_BS#1

106

DDR_A_RAS#

108

DDR_CS0_DIMMA#

110 112

M_ODT0

114

DDR_A_MA13

116 118 120 122

DDR_A_D39

124

DDR_A_D38

126 128

DDR_A_DM4

130 132

DDR_A_D34

134

DDR_A_D33

136 138

DDR_A_D45

140

DDR_A_D43

142 144

DDR_A_DQS#5

146

DDR_A_DQS5

148 150

DDR_A_D47

152

DDR_A_D42

154 156

DDR_A_D52

158

DDR_A_D53

160 162

M_CLK_DDR1

164

M_CLK_DDR#1

166 168

DDR_A_DM6

170 172

DDR_A_D51DDR_A_D54

174

DDR_A_D55

176 178 180

DDR_A_D56

182 184

DDR_A_DQS#7

186

DDR_A_DQS7

188 190

DDR_A_D62

192

DDR_A_D63

194 196 198 200

12

R13

R15

10K_0402_5%

2.2U_0805_16V4Z C145

1

2

M_CLK_DDR0 <7> M_CLK_DDR#0 <7>

PM_EXTTS#0 <7,14>

DDR_CKE1_DIMMA <7>

DDR_A_BS#1 <8> DDR_A_RAS# <8> DDR_CS0_DIMMA# <7>

M_ODT0 <7>

M_CLK_DDR1 <7> M_CLK_DDR#1 <7>

1

0.1U_0402_16V4Z

1

2

+DDR_MCH_REF1 <14>

C134

Top side

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DIS CLOSE D TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/10/06 2006/10/06

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, M/B LA-3281

401429

星期三七月

1

B

of

13 47, 12, 2006

5

DDR_B_DQS#[0..7]<8>

DDR_B_D[0..63]<8>

DDR_B_DM[0..7]<8> DDR_B_DQS[0..7]<8> DDR_B_MA[0..13]<8>

D D

C C

B B

A A

Layout Note: Place near JP42

+1.8V

2.2U_0805_16V4Z

1

2

0.1U_0402_16V4Z

1

2

C80

56_0804_8P4R_5%

R44 R41

56_0804_8P4R_5%

2.2U_0805_16V4Z

C23

0.1U_0402_16V4Z

1

2

C76

RP3

1 2

56_0402_5%

1 2

RP8

RP12

5

C90

1

2

0.1U_0402_16V4Z

18 27 36 45

45 36 27 18

18 27 36 45

2.2U_0805_16V4Z C29

1

2

Layout Note: Place one cap close to every 2 pullup resistors terminated to +0.9VS

+0.9VS

0.1U_0402_16V4Z

1

2

C73

DDR_B_CAS# DDR_B_WE#

M_ODT3

DDR_B_BS#0 DDR_B_MA10

DDR_B_MA1 DDR_B_MA3 DDR_B_MA5 DDR_B_MA9

DDR_CKE2_DIMMB DDR_B_BS#2 DDR_B_MA12 DDR_B_MA8

2.2U_0805_16V4Z

1

2

0.1U_0402_16V4Z

1

2

C35

+0.9VS

56_0804_8P4R_5%

2.2U_0805_16V4Z

C96

0.1U_0402_16V4Z

1

2

C41

RP4

4 5 3 6 2 7 1 8

56_0804_8P4R_5%

RP5

4 5 3 6 2 7 1 8

RP11

4 5 3 6 2 7 1 8

56_0804_8P4R_5%

0.1U_0402_16V4Z

C22

1

2

0.1U_0402_16V4Z

1

2

C56

DDR_B_MA13 M_ODT2 DDR_CS2_DIMMB#DDR_CS3_DIMMB# DDR_B_RAS#

DDR_B_BS#1 DDR_B_MA0 DDR_B_MA2 DDR_B_MA4

DDR_B_MA7 DDR_B_MA11 DDR_B_MA6 DDR_CKE3_DIMMB

0.1U_0402_16V4Z

C68

C75

1

2

0.1U_0402_16V4Z

1

2

C81

1

2

C62

C52

0.1U_0402_16V4Z

C88

1

2

0.1U_0402_16V4Z

1

2

C65

C84

Layout Note: Place these resistor closely JP42,all trace length Max=1.5"

4

C32

EC_P80_DATA<13,33>

EC_P80_CLK<13,33>

0.1U_0402_16V4Z

1

2

C36

C38

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

4

MAY BE USED BY OR DIS CLOSE D TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

+1.8V

JP4

1

VREF

3

DDR_B_D0 DDR_B_D1

DDR_B_DQS#0 DDR_B_DQS0

DDR_B_D2 DDR_B_D3

DDR_B_D8 DDR_B_D9

DDR_B_DQS#1 DDR_B_DQS1

DDR_B_D10 DDR_B_D11

DDR_B_D20 DDR_B_DQS#2

DDR_B_DQS2 DDR_B_D18

DDR_B_D19 DDR_B_D28

DDR_B_DM3

EC_P80_DATA

DDR_B_D30 DDR_B_D31

DDR_CKE2_DIMMB<7>

DDR_B_BS#2<8>

DDR_B_BS#0<8> DDR_B_WE#<8>

DDR_B_CAS#<8>

DDR_CS3_DIMMB#<7>

M_ODT3<7>

CLK_SMBDATA<13,15>

CLK_SMBCLK<13,15>

3

DDR_CKE2_DIMMB

EC_P80_CLK

DDR_B_BS#2 DDR_B_MA12

DDR_B_MA9 DDR_B_MA8

DDR_B_MA5 DDR_B_MA3 DDR_B_MA1

DDR_B_MA10 DDR_B_BS#0 DDR_B_WE#

DDR_B_CAS# DDR_CS3_DIMMB#

M_ODT3 DDR_B_D32

DDR_B_D33 DDR_B_DQS#4

DDR_B_DQS4 DDR_B_D34

DDR_B_D35 DDR_B_D40

DDR_B_D41 DDR_B_DM5 DDR_B_D42

DDR_B_D43 DDR_B_D48

DDR_B_D49

DDR_B_DQS#6 DDR_B_DQS6

DDR_B_D51 DDR_B_D50

DDR_B_D56 DDR_B_D61 DDR_B_D57

DDR_B_DM7 DDR_B_D59

DDR_B_D58 CLK_SMBDATA

CLK_SMBCLK

+3VS

1

C6

0.1U_0402_16V4Z

2005/10/06 2006/10/06

2

Compal Secret Data

VSS

5

DQ0

7

DQ1

9

VSS

11

DQS0#

13

DQS0

15

VSS

17

DQ2

19

DQ3

21

VSS

23

DQ8

25

DQ9

27

VSS

29

DQS1#

31

DQS1

33

VSS

35

DQ10

37

DQ11

39

VSS

41

VSS

43

DQ16

45

DQ17

47

VSS

49

DQS2#

51

DQS2

53

VSS

55

DQ18

57

DQ19

59

VSS

61

DQ24

63

DQ25

65

VSS

67

DM3

69

NC

71

VSS

73

DQ26

75

DQ27

77

VSS

79

CKE0

81

VDD

83

NC

85

BA2

87

VDD

89

A12

91

A9

93

A8

95

VDD

97

A5

99

A3

101

A1

103

VDD

105

A10/AP

107

BA0

109

WE#

111

VDD

113

CAS#

115

NC/S1#

117

VDD

119

NC/ODT1

121

VSS

123

DQ32

125

DQ33

127

VSS

129

DQS4#

131

DQS4

133

VSS

135

DQ34

137

DQ35

139

VSS

141

DQ40

143

DQ41

145

VSS

147

DM5

149

VSS

151

DQ42

153

DQ43

155

VSS

157

DQ48

159

DQ49

161

VSS

163

NC,TEST

165

VSS

167

DQS6#

169

DQS6

171

VSS

173

DQ50

175

DQ51

177

VSS

179

DQ56

181

DQ57

183

VSS

185

DM7

187

VSS

189

DQ58

191

DQ59

193

VSS

195

SDA

197

SCL

199

VDDSPD

P-TWO_A5692B-A0G16-P

ME@

SO-DIMM B

Deciphered Date

DQ4 DQ5

DM0 DQ6

DQ7

DQ12 DQ13

DM1

CK0# DQ14

DQ15

DQ20 DQ21

DM2

DQ22 DQ23

DQ28 DQ29

DQS3#

DQS3

DQ30 DQ31

NC/CKE1

VDD NC/A15 NC/A14

VDD

RAS#

VDD

ODT0

NC/A13

VDD

DQ36 DQ37

DM4

DQ38 DQ39

DQ44 DQ45

DQS5#

DQS5

DQ46 DQ47

DQ52 DQ53

CK1#

DM6

DQ54 DQ55

DQ60 DQ61

DQS7#

DQS7

DQ62 DQ63

SAO

VSS

VSS VSS

VSS

VSS VSS

CK0 VSS

VSS

A11

BA1 S0#

VSS

VSS VSS

VSS

VSS CK1

VSS VSS

VSS

VSS SA1

2

+1.8V

+DDR_MCH_REF1

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40

42 44 46 48 50

NC

52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92

A7

94

A6

96 98

A4

100

A2

102

A0

104 106 108 110 112 114 116 118 120

NC

122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200

2

DDR_B_D5 DDR_B_D4

DDR_B_DM0 DDR_B_D6

DDR_B_D7 DDR_B_D12

DDR_B_D13 DDR_B_DM1 M_CLK_DDR3

M_CLK_DDR#3 DDR_B_D14

DDR_B_D15

DDR_B_D21DDR_B_D17 DDR_B_D16

DDR_B_DM2 DDR_B_D22

DDR_B_D23 DDR_B_D26

DDR_B_D24DDR_B_D25 DDR_B_DQS#3

DDR_B_DQS3 DDR_B_D29

DDR_B_D27 DDR_CKE3_DIMMB

DDR_B_MA11 DDR_B_MA7 DDR_B_MA6

DDR_B_MA4 DDR_B_MA2 DDR_B_MA0

DDR_B_BS#1 DDR_B_RAS# DDR_CS2_DIMMB#

M_ODT2 DDR_B_MA13

DDR_B_D36 DDR_B_D37

DDR_B_DM4 DDR_B_D39

DDR_B_D38 DDR_B_D44

DDR_B_D45 DDR_B_DQS#5

DDR_B_DQS5 DDR_B_D46

DDR_B_D47 DDR_B_D52

DDR_B_D53 M_CLK_DDR2

M_CLK_DDR#2 DDR_B_DM6 DDR_B_D54

DDR_B_D55 DDR_B_D60

DDR_B_DQS#7 DDR_B_DQS7

DDR_B_D62 DDR_B_D63

10K_0402_5%

12

R14

2.2U_0805_16V4Z

0.1U_0402_16V4Z

1

C146

2

M_CLK_DDR3 <7> M_CLK_DDR#3 <7>

PM_EXTTS#0 <7,13>

DDR_CKE3_DIMMB <7>

DDR_B_BS#1 <8> DDR_B_RAS# <8> DDR_CS2_DIMMB# <7>

M_ODT2 <7>

M_CLK_DDR2 <7> M_CLK_DDR#2 <7>

R12

1 2

10K_0402_5%

Title

Size Document Number Rev

Date: Sheet of

+3VS

Compal Electronics, Inc.

SCHEMATIC, M/B LA-3281

401429

星期三七月

1

+DDR_MCH_REF1 <13>

C135

1

14 47, 12, 2006

B

5

PCI

SRC

CPU

CLKSEL1

0

1

FSLA

CLKSEL0

Stuff

No Stuff

Stuff

No Stuff

Stuff

No Stuff

MHz

133

166

CLK_Ra

CLK_Rd

CLK_Ra

CLK_Rd

CLK_Ra

MHz

1000

100

CLK_Rb

CLK_Re

CLK_Rb

CLK_Rf

CLK_Rb

MHz

33.31

33.3

CLK_Rc

CLK_Rf

CLK_Rc

ICH_SMBDATA<21,28>

ICH_SMBCLK<21,28>

FSLC1FSLB

CLKSEL2

0

Table : ICS954306

D D

FSB Frequency Selet:

CPU Driven

(Default)

*

533MHz

667MHz

CLK_Re

+VCCP

R349

@

12

+VCCP

12

FCTSEL1 (PIN34)

0

1

5

56_0402_5%

CLK_Rd

1 2

1K_0402_5%

12

R323 1K_0402_5%@

R123 1K_0402_5%@

1 2

1K_0402_5%

12

@

0_0402_5%

CLK_Re

+VCCP

1 2

12

R326

R122

R120

R383 1K_0402_5%@

1 2

R407

1K_0402_5%

R390

@

0_0402_5%

CLK_Rf

PIN43

27Mout

MCH_CLKSEL0 <7>

MCH_CLKSEL1 <7>

MCH_CLKSEL2 <7>

12

R363

10K_0402_5%@

CLK_ENABLE#

12

R352

10K_0402_5%@

CLK_PCI_1394<26>

CLK_PCI_PCM<24>

CLK_14M_CODEC

+3VS

12

R368

12

R367

CLK_14M_SIO<32>

10K_0402_5%

PCI_ICH

10K_0402_5%@

CLK_MCH_DREFCLK<7>

CLK_MCH_DREFCLK#<7>

PIN47PIN44

96/100M_TDOT96CDOT96T

96/100M_C

SRCT027MSSout

R353

8.2K_0402_5%

CPU_BSEL0<5>

CPU_BSEL1<5>

CPU_BSEL2<5>

+3VS

12

CLKREF1

R374

10K_0402_5%@

PCI_MINI

R373 10K_0402_5%

FSA

1 2

R332

0_0402_5%

CLK_Ra

FSB

1 2

R121

0_0402_5%

CLK_Rb

R396

8.2K_0402_5%

1 2

R397

0_0402_5%

CLK_Rc

PCI_MINI = FCTSEL1

C C

B B

A A

+3VS

CLK_48M_ICH<21>

CLK_14M_ICH<21>

CLK_PCI_LPC<33>

CLK_PCI_LAN<27> CLK_PCI_DB<32>

CLK_MCH_DREFCLK CLK_MCH_DREFCLK#

CLK_PCI_ICH<19>

CLK_ENABLE#<45>

CLK_SMBCLK<13,14>

CLK_SMBDATA<13,14>

+3VS

12

R382

12

R389 10K_0402_5%

PIN48

SRCC0

4

2.2K_0402_5% Q29 2N7002_SOT23

D

1 3

G

2

G

1 3

D

2N7002_SOT23

Q28

PCI6 PCI5ITP

10K_0402_5%@

PCI_LAN

4

+3VS

R428

S

C452 0.1U_0402_16V4Z C422 0.1U_0402_16V4Z

CLK_48M_ICH

CLK_14M_ICH

CLK_PCI_ICH

CLK_ENABLE#

CLK_SMBCLK

CLK_SMBDATA

1 2

R362 33_0402_5%UMA@

1 2

R361 33_0402_5%UMA@

1 2

R430 0_0402_5%

+3VS+3VS

12

R406

10K_0402_5%@

CLK_CODEC

12

R405 10K_0402_5%

R412 33_0402_5%

PCI_PME=SEL_PCI6

PCI_LAN

0 1 PCICLK6

R419

2.2K_0402_5%

CLK_SMBDATA

CLK_SMBCLK

1 2 1 2

CLK_XTAL_IN

CLK_XTAL_OUT

R364

33_0402_5%

12 12 12 12

12 12

12

MCH_DREFCLK MCH_DREFCLK#

R372

33_0402_5%

PIN27

CLKREQ5

+CK_VDD_MAIN1

+CK_VDD_REF +CK_VDD_48

FSA

12

FSB CLKREF1

12

PCI_MINI

R38133_0402_5%

PCI_EC

R38733_0402_5%

PCI_PCM

R38833_0402_5%

PCI_LAN

R40415_0402_5% R39515_0402_5%

CLK_CODEC

R41515_0402_5% R14515_0402_5%

PCI_ICH

12

CLKIREF

3

+CK_VDD_MAIN1

1 2

+3VS

R429 0_0805_5%

1 2

+3VS

R331 0_0805_5%

U29

1

VDDSRC

49

VDDSRC

54

VDDSRC

65

VDDSRC

30

VDDPCI

36

VDDPCI

12

VDDCPU

18

VDDREF

40

VDD48

20

X1

19

X2

41

USB_48MHz/FSLA

45

FSLB/TEST_MODE/24Mhz

23

REF0/FSLC/TEST_SEL

34

PCICLK4/FCTSEL1

33

SEL_48M/PCICLK3

32

SEL_24M/PCICLK2

27

SEL_PCI6/PCICLK1

22

SEL_PCI5/REF1

43

DOTT_96MHz/27MHz_Nonspread

44

DOTC_96MHz/27MHz_spread

37

ITP_EN/PCICLK_F0

39

VTT_PWRGD#/PD

16

SMBCLK

17

SMBDAT

9

GND

4

GNDSRC

15

GNDCPU

21

GNDREF

31

GNDPCI

35

GNDPCI

42

GND48

68

GNDSRC

73

GND

ICS9LPR325AKLFT_MLF72

1

C227 10U_0805_10V4Z

2

+CK_VDD_MAIN2

1

C413 10U_0805_10V4Z

2

CPUCLKT2_ITP/SRCCLKT10LP CPUCLKC2_ITP/SRCCLKC10LP

LCD100/96/SRC0_TLP

LCD100/96/SRC0_CLP

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DIS CLOSE D TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

1

C218

0.1U_0402_16V4Z

2

1

C458

0.1U_0402_16V4Z

2

VDDA

GNDA

PCI_SRC_STOP#

CPU_STOP#

CPUCLKT1LP CPUCLKC1LP

CPUCLKT0LP CPUCLKC0LP

SRCCLKT9LP SRCCLKC9LP

CLKREQ9# SRCCLKT8LP SRCCLKC8LP

CLKREQ8# SRCCLKT7LP SRCCLKC7LP

CLKREQ7#/48Mhz_1

SRCCLKT6LP SRCCLKC6LP

CLKREQ6# SRCCLKT5LP SRCCLKC5LP

CLKREQ5#/PCICLK6

SRCCLKT4LP SRCCLKC4LP

CLKREQ4# SRCCLKT3LP SRCCLKC3LP

CLKREQ3#/PCICLK5

SRCCLKT2LP SRCCLKC2LP

CLKREQ2# SRCCLKT1LP SRCCLKC1LP

CLKREQ1#

2005/10/06 2006/10/06

1

C219

0.1U_0402_16V4Z

2

1

C457

0.1U_0402_16V4Z

2

1

C450

7

0.1U_0402_16V4Z

2

8

25 24

11 10

14 13

6 5

3 2 72 70 69 71 66 67 38 63 64 62 60 61 29 58 59 57 55 56 28 52 53 26 50 51 46 47 48

H_STP_PCI# H_STP_CPU#

MCH_BCLK

1 2

R424 0_0402_5%

MCH_BCLK#

1 2

R423 0_0402_5%

1 2

R426 0_0402_5%

1 2

R425 0_0402_5%

PCIE_SATA

1 2

R414 0_0402_5%

PCIE_SATA#

1 2

R417 0_0402_5%

MCH_3GPLL

1 2

R399 0_0402_5%

MCH_3GPLL#

1 2

R410 0_0402_5% R394 0_0402_5%

1 2

R386 0_0402_5%

PCIE_ICH#

1 2

R393 0_0402_5%

1 2

R356 0_0402_5%

PCIE_MCARD#

1 2

R355 0_0402_5%

PCIE_VGA CLK_PCIE_VGA

1 2

R358 0_0402_5%VGA@

1 2

R357 0_0402_5%VGA@

SSCDREFCLK

1 2

R360 0_0402_5%UMA@

SSCDREFCLK#

1 2

R359 0_0402_5%UMA@

Compal Secret Data

Deciphered Date

2

1

C432

0.1U_0402_16V4Z

2

1 2

R330

1_0805_1%

1 2

R427

2.2_0805_1%

L17

1 2

FBM-L10-160808-301-T_0603

1

C451 10U_0805_10V4Z

2

1 2

R865 0_0402_5%

CLK_MCH_BCLK CLK_MCH_BCLK#

CLK_CPU_BCLKCPU_BCLK CLK_CPU_BCLK#CPU_BCLK#

CLK_PCIE_SATA CLK_PCIE_SATA#

CLK_MCH_3GPLL CLK_MCH_3GPLL# MCH_CLKREQ#CLKREQ5#

12

CLK_PCIE_ICHPCIE_ICH CLK_PCIE_ICH#

CLK_PCIE_MCARDPCIE_MCARD CLK_PCIE_MCARD# CLKREQ_MCARD#

CLK_PCIE_VGA#PCIE_VGA#

CLK_MCH_SSCDREFCLK CLK_MCH_SS CDREF CLK#

2

1

2

+CK_VDD_REF

+CK_VDD_48

+3VS

H_STP_PCI# <21> H_STP_CPU# <21>

SATAREQ#

C222

0.1U_0402_16V4Z

Place crystal within 500 mils of CK410

CLK_MCH_BCLK <7> CLK_MCH_BCLK# <7>

CLK_CPU_BCLK <4> CLK_CPU_BCLK# <4>

CLK_PCIE_SATA <20> CLK_PCIE_SATA# <20> SATAREQ# <21>

CLK_MCH_3GPLL <7> CLK_MCH_3GPLL# <7> MCH_CLKREQ# <7> CLK_PCIE_ICH <21> CLK_PCIE_ICH# <21>

CLK_PCIE_MCARD <28> CLK_PCIE_MCARD# <28> CLKREQ_MCARD# <28> CLK_PCIE_VGA <18> CLK_PCIE_VGA# <18>

CLK_MCH_SSCDREFCLK <7> CLK_MCH_SSCDREFCLK# <7>

Title

Size Document Number Rev

Date: Sheet

1

C233

0.1U_0402_16V4Z

2

1

C449

0.1U_0402_16V4Z

2

CLK_XTAL_IN CLK_XTAL_OUT

Place near U4

Place these components near each pin within 40 mils.

CLK_CPU_BCLK CLK_CPU_BCLK#

CLK_MCH_BCLK CLK_MCH_BCLK#

CLK_MCH_SSCDREFCLK CLK_MCH_SSCDREFCLK#

CLK_PCIE_MCARD

CLK_PCIE_MCARD# CLK_MCH_3GPLL CLK_MCH_3GPLL# CLK_PCIE_VGA CLK_PCIE_VGA#

CLK_PCIE_ICH

CLK_PCIE_ICH# CLK_MCH_DREFCLK CLK_MCH_DREFCLK#

CLK_PCIE_SATA

CLK_PCIE_SATA#

SATAREQ#

CLKREQ_MCARD#

Compal Electronics, Inc.

SCHEMATIC, M/B LA-3281

401429

星期三七月

1

C446 33P_0402_50V8J

12

Y2

14.31818MHZ_20P_6X1430004201

12

C448 33P_0402_50V8J

1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2

12 12

12

of

15 47, 12, 2006

R434 49.9_0402_1%@ R433 49.9_0402_1%@

R432 49.9_0402_1%@ R431 49.9_0402_1%@

R345 49.9_0402_1%@ R344 49.9_0402_1%@ R341 49.9_0402_1%@ R340 49.9_0402_1%@ R398 49.9_0402_1%@ R409 49.9_0402_1%@ R343 49.9_0402_1%@ R342 49.9_0402_1%@ R385 49.9_0402_1%@ R392 49.9_0402_1%@ R347 49.9_0402_1%@ R346 49.9_0402_1%@ R413 49.9_0402_1%@ R416 49.9_0402_1%@

R366 10K_0402_5%@

R140 10K_0402_5%@

1

+3VS

B

A

1 1

B

C

D

E

F

G

H

+LCDVDD +5VALW

S

AO3413_SOT23

G

2

+3VS

1

2

C290

4.7U_0805_10V4Z

1

C291

2

R202

4.7K_0402_5%

DISPOFF#

+LCDVDD

1

C288

2

0.1U_0402_16V4Z

DISPOFF#

Q14

D

1 3

1

C289

4.7U_0805_10V4Z

2

12

R196

100_0402_1%

13

2N7002_SOT23

GMCH_LVDDEN<9>

2 2

MBV2012301YZF_0805

L14

1 2

L15 0_0805_5%@

1 2

3 3

INVPWR_B+B+

INVT_PWM<33> DAC_BRIG<33>

0.1U_0603_50V4Z

470P_0402_50V8J

INVPWR_B+

C294

12

C295

DISPOFF#

JP40

1 2 3 4 5 6 7

MOLEX_53780-0790

ENBKL<33>

GMCH_ENBKL<9>

G7X_ENBKL<18>

R203

BKOFF#<33>

R52

0_0402_5%UMA@

R89

0_0402_5%VGA@

D

Q15

S

12

0_0402_5%UMA@

12

2

G

R204

1 2

R201 100K_0402_5%

1 2

13

Q16 DTC124EK_SC59

D9 CH751H-40_SC76

21

D10 CH751H-40_SC76@

21

100K_0402_5%UMA@

0.047U_0402_16V4Z

+3VS

1 2

4 4

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

C

MAY BE USED BY OR DIS CLOSE D TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

D

2005/10/06 2006/10/06

E

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

F

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, M/B LA-3281

401429

星期三七月

G

B

of

16 47, 12, 2006

H

A

B

C

D

E

TV-OUT Conn.

CARD_LUMA<18>

CARD_CRMA<18>

1 1

CARD_COMP<18>

TV_LUMA<9> TV_CRMA<9>

TV_COMPS<9>

R60 0_0402_5%VGA@

R59 0_0402_5%VGA@

R61 0_0402_5%VGA@

R224 0_0402_5%UMA@ R225 0_0402_5%UMA@ R223 0_0402_5%UMA@

12

12 12 12

R4

@

150_0603_1%

12

R5

R3

150_0603_1%

@

150_0603_1%

LUMA <36>

CRMA <36>

COMP <36>

Pop when with internal graphics

CRT Conn.

VGA@

CARD_VGA_R<18>

CARD_VGA_G<18>

CARD_VGA_B<18>

2 2

CRT_R<9>

CRT_G<9>

CRT_B<9>

12

R64 0_0402_5%

VGA@

12

R66 0_0402_5%

VGA@

12

R68 0_0402_5%

UMA@

12

R63 0_0402_5%

UMA@

12

R65 0_0402_5%

UMA@

12

R67 0_0402_5%

Pop when with internal graphics

VGA@

CARD_DDCDATA<18>

CARD_DDCCLK<18>

3 3

3VDDCDA<9>

3VDDCCL<9>

CARD_HSYNC<18>

CARD_VSYNC<18>

CRT_HSYNC<9>

CRT_VSYNC<9>

R80 0_0402_5% R79 0_0402_5%VGA@

R76 0_0402_5%

R75 0_0402_5%

12 12

UMA@

1 2

UMA@

1 2

VGA@

12

R82 0_0402_5%

VGA@

12

R81 0_0402_5%

UMA@

1 2

R78 39_0402_5%

UMA@

1 2

R77 39_0402_5%

DDCDA

DDCCL

HSYNC

VSYNC

Pop when with internal graphics

4 4

R197

0_0402_5%

VGA@

R9

2.2K_0402_5%

R

G

B

R6

@

12

R198

0_0402_5%

UMA@

+3VS

12

G

2

S

R2 0_0402_5%@

+5VS

1

0.1U_0402_16V4Z C5

2

+5VS

1

C4

2

0.1U_0402_16V4Z

12

R7

150_0603_1%

@

12

Q1

2N7002_SOT23

13

D

12

R8

150_0603_1%

@

+3VS+3VS +2.5VS

12

R199 0_0402_5%

UMA@

12

R10

2.2K_0402_5%

R11 0_0402_5%@

5

A2Y

3

5

A2Y

3

S

P

G

P

G

L1 0_0603_5%

L2 0_0603_5%

L3 0_0603_5%

R200 0_0402_5%

VGA@

+3VS

G

2

Q2

2N7002_SOT23

13

D

12

1

U1

4

OE#

74AHCT1G125GW_SOT353-5

1

U2

4

OE#

74AHCT1G125GW_SOT353-5

1 2

12

R1 1K_0402_5%

RED <36>

GREEN <36>

1

C3

2

82P_0402_50V8J

@

C2

C1

@

2

82P_0402_50V8J

@

1

BLUE <36>

VGA_DDC_DAT <36>

VGA_DDC_CLK <36>

JVGA_HS <36>

JVGA_VS <36>

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DIS CLOSE D TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2005/10/06 2006/10/06

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

D

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, M/B LA-3281

401429

星期三七月

17 47, 12, 2006

E

B

of

5

4

3

2

1

D D

MAX. 4.06A @ 1.8V MAX. 130mA @ 2.5V MAX. 655mA @ 3.3V

PEG_M_TXP[0..15] PEG_M_TXN[0..15]

JP7

1

PEG_M_TXP1 PEG_M_TXN1

PEG_M_TXP3 PEG_M_TXN3

PEG_M_TXP5 PEG_M_TXN5

PEG_M_TXP7

C C

B B

PEG_M_TXN7 PEG_M_TXP9

PEG_M_TXN9 PEG_M_TXP11

PEG_M_TXN11 PEG_M_TXP13

PEG_M_TXN13 PEG_M_TXP15

PEG_M_TXN15

+2.5VS

+3VS +5VS

+1.5VS

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

ACES_88363-08001

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

PEG_RXP1

PEG_RXN1

PEG_RXP3

PEG_RXN3

PEG_RXP5 PEG_RXN5

PEG_RXP7 PEG_RXN7

PEG_RXP9 PEG_RXN9

PEG_RXP11 PEG_RXN11

PEG_RXP13 PEG_RXN13

PEG_RXP15 PEG_RXN15

+1.8VS

B+

CARD_DDCCLK<17> CARD_DDCDATA<17>

CLK_PCIE_VGA<15>

CLK_PCIE_VGA#<15>

CARD_VSYNC<17> CARD_HSYNC<17>

CARD_VGA_R<17> CARD_VGA_G<17>

CARD_VGA_B<17>

PEG_M_TXP0 PEG_M_TXN0

PEG_M_TXP2 PEG_M_TXN2

PEG_M_TXP4 PEG_M_TXN4

PEG_M_TXP6 PEG_M_TXN6

PEG_M_TXP8 PEG_M_TXN8

PEG_M_TXP10 PEG_M_TXN10

PEG_M_TXP12 PEG_M_TXN12

PEG_M_TXP14 PEG_M_TXN14

JP8

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

ACES_88363-08001

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

PEG_RXP0

PEG_RXN0

PEG_RXP2

PEG_RXN2

PEG_RXP4

PEG_RXN4

PEG_RXP6

PEG_RXN6

PEG_RXP8

PEG_RXN8

PEG_RXP10 PEG_RXN10

PEG_RXP12 PEG_RXN12

PEG_RXP14 PEG_RXN14

SUSP#

G7X_THER_ALERT#

SUSP# <24,26,33,34,35,43,44> G7X_THER_ALERT# <21>

G7X_ENBKL <16>

PLTRST_VGA# <19>

CARD_COMP <17> CARD_LUMA <17> CARD_CRMA <17>

PEG_RXP[0..15] PEG_RXN[0..15]

2

1

VGA@

PEG_M_TXP[0..15] <9> PEG_M_TXN[0..15] <9>

PEG_RXP[0:15] <9> PEG_RXN[0:15] <9>

2

C244

C240

1

0.1U_0402_16V4Z

VGA@

+3VS

1

C111

C110

2

0.047U_0402_16V4Z

VGA@

0.047U_0402_16V4Z

+2.5VS+5VS

2

1

2

C113

C112

1

0.1U_0402_16V4Z

VGA@

A A

Title

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DIS CLOSE D T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

Size Document Number Rev Custom

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, M/B LA-3281

401429

星期三七月

1

B

of

18 47, 12, 2006

5

4

3

2

1

D D

C C

B B

+3VS

R271 8.2K_0402_5%

1 2

R268 8.2K_0402_5%

1 2

R269 8.2K_0402_5%

1 2

R263 8.2K_0402_5%

1 2

R273 8.2K_0402_5%

1 2

R287 8.2K_0402_5%

1 2

R274 8.2K_0402_5%

1 2

R276 8.2K_0402_5%

1 2

R272 8.2K_0402_5%

1 2

R270 8.2K_0402_5%

1 2

+3VS

R298 8.2K_0402_5%

1 2

R300 8.2K_0402_5%

1 2

R294 8.2K_0402_5%

1 2

R291 8.2K_0402_5%

1 2

R283 8.2K_0402_5%

1 2

R290 8.2K_0402_5%

1 2

R279 8.2K_0402_5%

1 2

R284 8.2K_0402_5%

1 2

R286 8.2K_0402_5%

1 2

R264 8.2K_0402_5%

1 2

R261 8.2K_0402_5%

1 2

R282 8.2K_0402_5%

1 2

PCI_DEVSEL# PCI_STOP# PCI_TRDY# PCI_FRAME# PCI_PLOCK# PCI_IRDY# PCI_SERR# PCI_PERR# PCI_REQ4# PCI_REQ3#

PCI_PIRQA# PCI_PIRQB# PCI_PIRQC# PCI_PIRQD# PCI_PIRQE# PCI_PIRQF# PCI_PIRQG# PCI_PIRQH# PCI_REQ0# PCI_REQ1# PCI_REQ2# PCI_REQ5#

PCI_AD[0..31]<24,26,27,32>

PCI_PIRQA#<24> PCI_PIRQB#

PCI_AD0 PCI_AD1 PCI_AD2 PCI_AD3 PCI_AD4 PCI_AD5 PCI_AD6 PCI_AD7 PCI_AD8 PCI_AD9 PCI_AD10 PCI_AD11 PCI_AD12 PCI_AD13 PCI_AD14 PCI_AD15 PCI_AD16 PCI_AD17 PCI_AD18 PCI_AD19 PCI_AD20 PCI_AD21 PCI_AD22 PCI_AD23 PCI_AD24 PCI_AD25 PCI_AD26 PCI_AD27 PCI_AD28 PCI_AD29 PCI_AD30 PCI_AD31

PCI_PIRQA# PCI_PIRQB# PCI_PIRQC# PCI_PIRQD#

U3B

E18

AD0

C18

AD1

A16

AD2

F18

AD3

E16

AD4

A18

AD5

E17

AD6

A17

AD7

A15

AD8

C14

AD9

E14

AD10

D14

AD11

B12

AD12

C13

AD13

G15

AD14

G13

AD15

E12

AD16

C11

AD17

D11

AD18

A11

AD19

A10

AD20

F11

AD21

F10

AD22

E9

AD23

D9

AD24

B9

AD25

A8

AD26

A6

AD27

C7

AD28

B6

AD29

E6

AD30

D6

AD31

Interrupt I/F

A3

PIRQA#

B4

PIRQB#

C5

PIRQC#

B5

PIRQD#

AE5

RSVD[1]

AD5

RSVD[2]

AG4

RSVD[3]

AH4

RSVD[4]

AD9

RSVD[5]

ICH7_BGA652~D

PCI

REQ4# / GPIO22 GNT4# / GPIO48

GPIO1 / REQ5#

GPIO17 / GNT5#

GPIO2 / PIRQE# GPIO3 / PIRQF# GPIO4 / PIRQG# GPIO5 / PIRQH#

MISC

MCH_SYNC#

REQ0# GNT0# REQ1# GNT1# REQ2# GNT2# REQ3# GNT3#

C/BE0# C/BE1# C/BE2# C/BE3#

IRDY#

PAR

PCIRST#

DEVSEL#

PERR#

PLOCK#

SERR# STOP# TRDY#

FRAME#

PLTRST#

PCICLK

PME#

RSVD[6] RSVD[7] RSVD[8] RSVD[9]

D7 E7 C16 D16 C17 D17 E13 F13 A13 A14 C8 D8

B15 C12 D12 C15

A7 E10 B18 A12 C9 E11 B10 F15 F14 F16

C26 A9 B19

G8 F7 F8 G7

AE9 AG8 AH8 F21 AH20

PCI_REQ0# PCI_GNT0# PCI_REQ1#

PCI_REQ2# PCI_GNT2# PCI_REQ3# PCI_GNT3# PCI_REQ4#

PCI_REQ5#

PCI_CBE#0 PCI_CBE#1 PCI_CBE#2 PCI_CBE#3

PCI_IRDY# PCI_PAR PCI_PCIRST# PCI_DEVSEL# PCI_PERR# PCI_PLOCK# PCI_SERR# PCI_STOP# PCI_TRDY# PCI_FRAME#

PCI_PLTRST# CLK_PCI_ICH PCI_PME#

PCI_PIRQE# PCI_PIRQF# PCI_PIRQG# PCI_PIRQH#

PCI_REQ0# <26> PCI_GNT0# <26>

PCI_REQ2# <24> PCI_GNT2# <24> PCI_REQ3# <27> PCI_GNT3# <27>

PCI_CBE#0 <24,26,27,32> PCI_CBE#1 <24,26,27,32> PCI_CBE#2 <24,26,27,32> PCI_CBE#3 <24,26,27,32>

PCI_IRDY# <24,26,27> PCI_PAR <24,26,27>

PCI_DEVSEL# <24,26,27> PCI_PERR# <24,26,27>

PCI_SERR# <24,26,27> PCI_STOP# <24,26,27> PCI_T RDY# <24,26,27,32> PCI_FRAME# <24,26,27,32>

CLK_PCI_ICH <15> PCI_PME# <33>

PCI_PIRQE# PCI_PIRQF# <27> PCI_PIRQG# <26> PCI_PIRQH# <26>

MCH_ICH_SYNC# <7>

PCI_PCIRST#

PCI_PLTRST#

+3VS

5

1

B

2

A

3

R235 0_0402_5%@

12

+3VS

5

1

B

2

A

3

12

R257 0_0402_5%@

Place clos ely pin A9

CLK_PCI_ICH

R277

10_0402_5%@

C364

8.2P_0402_50V@

U21

P

G

P

G

PCI_RST#

4

Y

TC7SH08FUF_SSOP5

U18

PLT_RST#

4

Y

TC7SH08FUF_SSOP5

1 2 1

2

PCI_RST# <21,24,25,26,27,32,33>

R236

12

0_0402_5%

PLT_RST# <7,23,28>

PLTRST_VGA# <18>

A A

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DIS CLOSE D TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/10/06 2006/10/06

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

2

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, M/B LA-3281

星期三七月

401429

19 47, 12, 2006

1

B

of

5

C195

18P_0402_50V8J

32.768KHZ_12.5P_1TJS125BJ2A251

C196

D D

+RTCVCC

12

R288 1M_0402_5%

SM_INTRUDER#

+RTCVCC

12

R296 332K_0402_1%

C C

B B

ICH_INTVRMEN

+RTCVCC

R293 20K_0402_5%

1U_0603_10V4Z

+3VS

PSATA_ITX_DRX_N0<23>

PSATA_ITX_DRX_P0<23>

1 2

J1

C392

1 2

ICH_BITCLK_MDC<28> ICH_SYNC_MDC<28>

ICH_RST_MDC#<28>

ICH_AC_SDIN0<29> ICH_AC_SDIN1<28>

ICH_SDOUT_MDC<28>

18P_0402_50V8J

21

3MM

Close to U7

ICH_AC_SDOUT_R

ICH_SDOUT_AUDIO<29>

ICH_SYNC_AUDIO<29>

A A

ICH_RST_AUDIO#<29>

ICH_BITCLK_AUDIO<29>

5

1 2

R299 33_0402_5%

1 2

R280 33_0402_5%

1 2

R313 33_0402_5%

1 2

R312 33_0402_5%

1

C390

@

27P_0402_50V8J

2

ICH_AC_SYNC_R

ICH_AC_RST_R#

ICH_AC_BITCLK_R

4

12

Y1

2

NC

3

OUT

NC

12

C389

@

10P_0402_25V8K

R2664.7K_0402_5%

12

R2658.2K_0402_5%

12

R25910K_0402_5%

12

PSATA_ITX_DRX_N0

PSATA_ITX_DRX_P0

4

ICH_RTCX1

1

IN

4

ICH_RTCX2

R310

12

1 2

10_0402_5%@

SATA_LED#<37>

PSATA_IRX_DTX_N0_C<23> PSATA_IRX_DTX_P0_C<23>

CLK_PCIE_SATA#<15> CLK_PCIE_SATA<15>

PD_IORDY PD_IRQ SATA_LED#

1 2

C387 3900P_0402_50V7K

1 2

C388 3900P_0402_50V7K

12

R109

10M_0402_5%

R311 33_0402_5%

1 2

R281 33_0402_5%

1 2

R314 33_0402_5%

1 2

R315 33_0402_5%

PD_IORDY<23>

PD_IRQ<23>

PD_DACK#<23>

PD_IOW#<23> PD_IOR#<23>

PSATA_ITX_DRX_N0_C

PSATA_ITX_DRX_P0_C

3

U3A

RTXC1 RTCX2

RTCRST# INTVRMEN

INTRUDER#

EE_CS EE_SHCLK EE_DOUT EE_DIN

LAN_CLK LAN_RSTSYNC LAN_RXD0

LAN_RXD1 LAN_RXD2

LAN_TXD0 LAN_TXD1 LAN_TXD2

ACZ_BCLK ACZ_SYNC

ACZ_RST# ACZ_SDIN0

ACZ_SDIN1 ACZ_SDIN2

ACZ_SDOUT

SATALED#

SATA0RXN SATA0RXP SATA0TXN SATA0TXP

SATA2RXN SATA2RXP SATA2TXN SATA2TXP

SATA_CLKN SATA_CLKP

SATARBIASN SATARBIASP

IORDY IDEIRQ DDACK# DIOW# DIOR#

ICH7_BGA652~D

3

RTC

GPIO49 / CPUPWRGD

LPCCPU

LDRQ1# / GPIO23

LFRAME#

LAN

A20GATE

CPUSLP#

TP1 / DPRSTP#

TP2 / DPSLP#

INIT3_3V#

AC-97/AZALIA

STPCLK#

THERMTRIP#

SATA

IDE

LAD0 LAD1 LAD2 LAD3

LDRQ0#

A20M#

FERR#

IGNNE#

INIT# INTR

RCIN#

SMI#

DCS1# DCS3#

DD10 DD11 DD12 DD13 DD14 DD15

DDREQ

2005/10/06 2006/10/06

AB1

AF18

AG2

AG6

AH10 AG10

AG16 AH16 AF16 AH15 AF15

AB2 AA3

W4

Y5

W1

Y1 Y2

W3

V3 U3 U5

V4 T5

U7 V6 V7

U1 R6

R5 T2

T3 T1

T4

AF3 AE3

AH2 AF7

AE7 AH6 AF1

AE1

ICH_RTCRST# ICH_INTVRMEN

SM_INTRUDER#

ICH_AC_BITCLK_R ICH_AC_SYNC_R

ICH_AC_RST_R# ICH_AC_SDIN0

ICH_AC_SDIN1

ICH_AC_SDOUT_R

SATA_LED#

PSATA_IRX_DTX_N0_C PSATA_IRX_DTX_P0_C PSATA_ITX_DRX_N0_C PSATA_ITX_DRX_P0_C

CLK_PCIE_SATA# CLK_PCIE_SATA

R275

1 2

24.9_0402_1%

PD_IORDY PD_IRQ PD_DACK# PD_IOW# PD_IOR#

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DIS CLOSE D TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

NMI

DA0 DA1 DA2

DD0 DD1 DD2 DD3 DD4 DD5 DD6 DD7 DD8 DD9

AA6 AB5 AC4 Y6

AC3 AA5

AB3

AE22 AH28

AG27 AF24

AH25 AG26 AG24 AG22

AG21 AF22 AF25

AG23 AF23

AH24 AH22 AF26

AH17 AE17 AF17

AE16 AD16

AB15 AE14 AG13 AF13 AD14 AC13 AD12 AC12 AE12 AF12 AB13 AC14 AF14 AH13 AH14 AC15

AE15

LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3

LPC_DRQ0#

LPC_FRAME#

GATEA20 H_A20M#

H_CPUSLP_R# DPRSLP#

H_DPSLP# H_FERR# H_PWRGOOD H_IGNNE# H_INIT#

H_INTR

KB_RST# H_SMI#

H_NMI H_STPCLK# THRMTRIP_ICH#

PD_A0 PD_A1 PD_A2

PD_CS#1 PD_CS#3

PD_D0 PD_D1 PD_D2 PD_D3 PD_D4 PD_D5 PD_D6 PD_D7 PD_D8 PD_D9 PD_D10 PD_D11 PD_D12 PD_D13 PD_D14 PD_D15

PD_DREQ

PD_D[0..15]

Compal Secret Data

Deciphered Date

2

LPC_AD[0..3] <32,33>

LPC_DRQ#0 <32>

LPC_FRAME# <32,33>

R250 10K_0402_5%

12

GATEA20 <33> H_A20M# <4>

R233 0_0402_5% @

12

R243 0_0402_5%

12

H_DPSLP# <4> H_FERR# <4> H_PWRGOOD <4> H_IGNNE# <4> H_INIT# <4>

H_INTR <4>

KB_RST# <33> H_SMI# <4>

H_NMI <4> H_STPCLK# <4>

PD_A0 <23> PD_A1 <23> PD_A2 <23>

PD_CS#1 <23> PD_CS#3 <23>

PD_DREQ <23>

PD_D[0..15] <23>

12

R251 10K_0402_5%

12

R237

1 2

24.9_0402_1%

+RTCVCC

1 2

100_0603_1%

2

C203

0.1U_0402_16V4Z

1

2

56_0402_5% R234

R114

+3VS

H_CPUSLP# <4,7> H_DPRSTP# <4,45>

+VCCP

+3VS

D3

RB751V_SOD323

1

+VCCP

12

R245 56_0402_5%

H_THERMTRIP# <4,7>

BATT1.1

BATT1

+-

W=20mils

Title

Size Document Number Rev

Custom

Date: Sheet

1 2

+CHGRTC

ML1220T13RE

45@

21

Compal Electronics, Inc.

SCHEMATIC, M/B LA-3281

401429

星期三七月

1

of

20 47, 12, 2006

B

5

+3VS

10K_0402_5%

1 2

8.2K_0402_5%

1 2

10K_0402_5%

1 2

10K_0402_5%

1 2

150_0402_5%

1 2

10K_0402_5%

1 2

10K_0402_5%

1 2

10K_0402_5%

1 2

1K_0402_5%

1 2

8.2K_0402_5% 10K_0402_5%

1 2

10K_0402_5%

1 2

SIRQ

PCI_CLKRUN#

G7X_THER_ALERT#

LINKALERT#

ITP_DBRESET#

OCP#

SPI_MISO

SPI_CS#

ICH_PCIE_W AKE#

ICH_LOW_BAT#

12

WL_ON

SPI_MOSI

R239

10K_0402_5%

R253

R258

D D

C C

R254

+3VALW

R242

R248

R246

R304

R285

R255

R252 R240

R292

1 2

R241 10K_0402_5%

1 2

4

3

2

1

Place clos ely pin B2 Plac e c losely pin AC1

+3VALW+3VALW

12

R256

1 2

SB_SPKR<29>

H_STP_PCI#<15>

VGATE<45>

EC_SMI#<33>

R247

2.2K_0402_5%

R232

8.2K_0402_5%

T41PAD

OCP#<4>

IDERST_CD#

SIRQ<24,26,32,33>

ICH_SMBCLK ICH_SMBDATA LINKALERT# ICH_SMLINK0 ICH_SMLINK1

ICH_RI# SB_SPKR

SUS_STAT# ITP_DBRESET#

PM_BMBUSY# OCP# H_STP_PCI#

H_STP_CPU#

PCI_CLKRUN#

ICH_PCIE_W AKE#

SIRQ EC_THERM#

VGATE

G7X_THER_ALERT#

EC_SMI#

2.2K_0402_5%

ICH_SMBCLK<15,28>

ICH_SMBDATA<15,28>

+3VALW

ITP_DBRESET#<4>

PM_BMBUSY#<7>

IDERST_CD#<23>

H_STP_CPU#<15>

PCI_CLKRUN#<24,26,27,33>

ICH_PCIE_W AKE#<28>

EC_THERM#<33>

G7X_THER_ALERT#<18>

U3C

C22

SMBCLK

B22

SMBDATA

A26

LINKALERT#

B25

SMLINK0

A25

SMLINK1

A28

RI#

A19

SPKR

A27

SUS_STAT#

A22

SYS_RST#

AB18

GPIO0 / BM_BUSY#

B23

GPIO11 / SMBALERT#

AC20

GPIO18 / STPPCI#

AF21

GPIO20 / STPCPU#

A21

GPIO26

B21

GPIO27

E23

GPIO28

AG18

GPIO32 / CLKRUN#

AC19

GPIO33 / AZ_DOCK_EN#

U2

GPIO34 / AZ_DOCK_RST#

F20

WAKE#

AH21

SERIRQ

AF20

THRM#

AD22

VRMPWRGD

AC21

GPIO6

AC18

GPIO7

E21

GPIO8

ICH7_BGA652~D

GPIO21 / SATA0GP

SMB

GPIO19 / SATA1GP GPIO36 / SATA2GP GPIO37 / SATA3GP

SATA

GPIO

SYS

Clocks

GPIO

GPIO16 / DPRSLPVR

TP0 / BATLOW#

POWER MGT

GPIO

GPIO35 / SATAREQ#

Need update symbol

CLK14 CLK48

SUSCLK SLP_S3#

SLP_S4# SLP_S5#

PWROK

PWRBTN#

LAN_RST#

RSMRST#

GPIO9 GPIO10 GPIO12 GPIO13 GPIO14 GPIO15 GPIO24 GPIO25

GPIO38 GPIO39

AF19 AH18 AH19 AE19

CLK_14M_ICH

AC1

CLK_48M_ICH

B2

ICH_SUSCLK

C20

SLP_S3#

B24

SLP_S4#

D23

SLP_S5#

F22

ICH_POK

AA4 AC22

R90 100_0402_5%

ICH_LOW_BAT#

C21

PBTN_OUT#

C23

PCI_RST#

C19

EC_RSMRST#

Y4

R297 10K_0402_5%

EC_SCI#

E20 A20 F19

EC_LID_OUT#

E19 R4

CPUSB#

E22

WL_ON

R3

EC_FLASH#

D20

SATAREQ#

AD21 AD20

KILL_MDC#

AE20

1 2

100_0402_5%

1 2

SB_INT_FLASH_SEL

R260

CLK_14M_ICH <15> CLK_48M_ICH <15>

T44 PAD

SLP_S3# <33>

ICH_POK <7,33>

1 2

DPRSLPVR

PBTN_OUT# <33> PCI_RST# <19,24,25,26,27,32,33> EC_RSMRST# <33>

EC_SCI# <33> ACIN <33,39>

EC_LID_OUT# <33>

T42 PAD

EC_FLASH# <34> SATAREQ# <15>

KILL_MDC# <28>

12

R305

1

C384

2

SLP_S4#

SLP_S5#

R295 10K_0402_5%

DPRSLPVR <7,45>

CLK_48M_ICH

10_0402_5%@

4.7P_0402_50V8C@

+3VALW

5

1

P

B

2

A

G

3

U37

PM_SLP_S5#

4

Y

TC7SH08FUF_SSOP5

DPRSLPVR

12

1

2

R91

100K_0402_5%

CLK_14M_ICH

R308

10_0402_5%@

C391

4.7P_0402_50V8C@

PM_SLP_S5# <33>

12

U3D

F26

PERn1

F25

PERp1

E28

PETn1

E27

PCIE_RXN2<28>

PCIE_RXP2<28> PCIE_TXN2<28> PCIE_TXP2<28>

B B

USB_OC#0<31> USB_OC#2<37> USB_OC#4<37> USB_OC#6<37>

A A

PCIE_RXN2 PCIE_RXP2 PCIE_C_TXN2

C3280.1U_0402_16V4Z

12

PCIE_C_TXP2

C3290.1U_0402_16V4Z

12

SPI_CS#

SPI_MOSI SPI_MISO

USB_OC#0 USB_OC#1 USB_OC#2 USB_OC#3 USB_OC#4 USB_OC#5 USB_OC#6 USB_OC#7

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DIS CLOSE D TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

H26 H25 G28 G27

K26 K25 J28 J27

M26 M25

L28 L27

P26 P25 N28 N27

T25 T24 R28 R27

R2

P6 P1

P5 P2

D3 C4 D5 D4

E5

C3

A2 B3

ICH7_BGA652~D

3

PETp1 PERn2

PERp2 PETn2 PETp2

PERn3 PERp3 PETn3 PETp3

PERn4 PERp4 PETn4 PETp4

PERn5 PERp5 PETn5 PETp5

PERn6 PERp6 PETn6 PETp6

SPI_CLK SPI_CS# SPI_ARB

SPI_MOSI SPI_MISO

OC0# OC1# OC2# OC3# OC4# OC5# / GPIO29 OC6# / GPIO30 OC7# / GPIO31

2005/10/06 2006/10/06

PCI-EXPRESS

SPI

USB

DMI0RXN DMI0RXP DMI0TXN

DMI0TXP

DMI1RXN DMI1RXP DMI1TXN

DMI1TXP

DMI2RXN DMI2RXP DMI2TXN

DMI2TXP

DMI3RXN DMI3RXP DMI3TXN

DMI3TXP

DMI_CLKN DMI_CLKP

DIRECT MEDIA INTERFACE

DMI_ZCOMP

DMI_IRCOMP

USBP0N USBP0P USBP1N USBP1P USBP2N USBP2P USBP3N USBP3P USBP4N USBP4P USBP5N USBP5P USBP6N USBP6P USBP7N USBP7P

USBRBIAS#

USBRBIAS

Compal Secret Data

V26 V25 U28 U27

Y26 Y25 W28 W27

AB26 AB25 AA28 AA27

AD25 AD24 AC28 AC27

AE28 AE27

C25 D25

F1 F2 G4 G3 H1 H2 J4 J3 K1 K2 L4 L5 M1 M2 N4 N3

D2 D1

Deciphered Date

DMI_RXN0 DMI_RXP0 DMI_TXN0 DMI_TXP0

DMI_RXN1 DMI_RXP1 DMI_TXN1 DMI_TXP1

DMI_RXN2 DMI_RXP2 DMI_TXN2 DMI_TXP2

DMI_RXN3 DMI_RXP3 DMI_TXN3 DMI_TXP3

CLK_PCIE_ICH# CLK_PCIE_ICH

DMI_IRCOMP USB20_N0

USB20_P0 USB20_N1 USB20_P1 USB20_N2 USB20_P2 USB20_N3 USB20_P3 USB20_N4 USB20_P4 USB20_N5 USB20_P5 USB20_N6 USB20_P6 USB20_N7 USB20_P7

USBRBIAS

DMI_RXN0 <7> DMI_RXP0 <7> DMI_TXN0 <7> DMI_TXP0 <7>

DMI_RXN1 <7> DMI_RXP1 <7> DMI_TXN1 <7> DMI_TXP1 <7>

DMI_RXN2 <7> DMI_RXP2 <7> DMI_TXN2 <7> DMI_TXP2 <7>

DMI_RXN3 <7> DMI_RXP3 <7> DMI_TXN3 <7> DMI_TXP3 <7>

CLK_PCIE_ICH# <15> CLK_PCIE_ICH <15>

R238 24.9_0402_1%

1 2

USB20_N0 <31> USB20_P0 <31> USB20_N1 <28> USB20_P1 <28> USB20_N2 <37> USB20_P2 <37> USB20_N3 <36> USB20_P3 <36> USB20_N4 <37> USB20_P4 <37> USB20_N5 <36> USB20_P5 <36> USB20_N6 <37> USB20_P6 <37> USB20_N7 <28> USB20_P7 <28>

R307 22.6_0402_1%

1 2

Within 500 mils

2

Within 500 mils

+1.5VS

Title

Size Document Number Rev

Custom

Date: Sheet

USB_OC#4 USB_OC#2 USB_OC#3 USB_OC#1

USB_OC#0 USB_OC#5 USB_OC#6 USB_OC#7

RP15

4 5 3 6 2 7 1 8

10K_1206_8P4R_5%

RP16

4 5 3 6 2 7 1 8

10K_1206_8P4R_5%

Compal Electronics, Inc.

SCHEMATIC, M/B LA-3281

401429

星期三七月

1

+3VALW

21 47, 12, 2006

B

of

5

4

3

2

1

ICH_V5REF_RUN

C330

10U_0805_10V4Z

+3VS

+1.5VS

C366

0.1U_0402_16V4Z

+1.5VS

1

+

C335

C327

2

220U_D2_4VM

0.1U_0402_16V4Z

+1.5VS_DMIPLL

1

C338

2

0.01U_0402_16V7K

1

C355

2

0.1U_0402_16V4Z

1

2

1

2

Place closely pin D28,T28,AD28.

Place close ly pin AG5.

Place close ly pin AG9.

+3VS

D D

100_0402_5%

10_0402_5%

C C

B B

A A

R278

R289

12

+3VS+5VS

21

D15 CH751H-40_SC76

1

C362

0.1U_0402_16V4Z

2

+3VALW+5VALW

21

D16 CH751H-40_SC76

1

C371

0.1U_0402_16V4Z

2

ICH_V5REF_RUN

ICH_V5REF_SUS

+1.5VS

1

C361

0.1U_0402_16V4Z

2

Place closely pin AG28 within 100mlis.

R229

1 2

0.5_0805_1%

0.1U_0402_16V4Z

+1.5VS_DMIPLLR

+1.5VS

+3VALW

C372

1 2

0_0805_5%

1

C375

2

1

2

R230

0.1U_0402_16V4Z

1

C332

C340

2

0.1U_0402_16V4Z

C352

0.1U_0402_16V4Z

+1.5VS

C373

0.1U_0402_16V4Z

+1.5VS

C365

1U_0603_10V4Z

T47 P AD T45 P AD

1 2

R497 0_0402_5%

ICH_V5REF_SUS

1

2

+3VS

1

2

+1.5VS_DMIPLL

1

2

1

2

ICH_AA2 ICH_Y7

G10

AD17

F6

AA22 AA23 AB22 AB23 AC23 AC24 AC25 AC26 AD26 AD27 AD28

D26 D27 D28 E24 E25 E26 F23 F24 G22 G23 H22 H23 J22 J23 K22 K23 L22

L23 M22 M23 N22 N23

P22

P23 R22 R23 R24 R25 R26

T22

T23

T26

T27

T28 U22 U23

V22

V23 W22 W23

Y22

Y23

B27

AG28

AB7 AC6 AC7 AD6 AE6 AF5 AF6 AG5 AH5

AD2

AH11 AB10

AB9

AC10 AD10 AE10 AF10

AF9 AG9 AH9

E3

C1

AA2

Y7 V5

V1 W2 W7

1

C349

0.1U_0402_16V4Z

2

U3F

V5REF[1] V5REF[2] V5REF_Sus Vcc1_5_B[1]

Vcc1_5_B[2] Vcc1_5_B[3] Vcc1_5_B[4] Vcc1_5_B[5] Vcc1_5_B[6] Vcc1_5_B[7] Vcc1_5_B[8] Vcc1_5_B[9] Vcc1_5_B[10] Vcc1_5_B[11] Vcc1_5_B[12] Vcc1_5_B[13] Vcc1_5_B[14] Vcc1_5_B[15] Vcc1_5_B[16] Vcc1_5_B[17] Vcc1_5_B[18] Vcc1_5_B[19] Vcc1_5_B[20] Vcc1_5_B[21] Vcc1_5_B[22] Vcc1_5_B[23] Vcc1_5_B[24] Vcc1_5_B[25] Vcc1_5_B[26] Vcc1_5_B[27] Vcc1_5_B[28] Vcc1_5_B[29] Vcc1_5_B[30] Vcc1_5_B[31] Vcc1_5_B[32] Vcc1_5_B[33] Vcc1_5_B[34] Vcc1_5_B[35] Vcc1_5_B[36] Vcc1_5_B[37] Vcc1_5_B[38] Vcc1_5_B[39] Vcc1_5_B[40] Vcc1_5_B[41] Vcc1_5_B[42] Vcc1_5_B[43] Vcc1_5_B[44] Vcc1_5_B[45] Vcc1_5_B[46] Vcc1_5_B[47] Vcc1_5_B[48] Vcc1_5_B[49] Vcc1_5_B[50] Vcc1_5_B[51] Vcc1_5_B[52] Vcc1_5_B[53]

Vcc3_3[1] VccDMIPLL Vcc1_5_A[1]

Vcc1_5_A[2] Vcc1_5_A[3] Vcc1_5_A[4] Vcc1_5_A[5] Vcc1_5_A[6] Vcc1_5_A[7] Vcc1_5_A[8] Vcc1_5_A[9]

VccSATAPLL Vcc3_3[2] Vcc1_5_A[10]

Vcc1_5_A[11] Vcc1_5_A[12] Vcc1_5_A[13] Vcc1_5_A[14] Vcc1_5_A[15] Vcc1_5_A[16] Vcc1_5_A[17] Vcc1_5_A[18]

VccSus3_3[19] VccUSBPLL VccSus1_05/VccLAN1_05[1]

VccSus1_05/VccLAN1_05[2] VccSus3_3/VccLAN3_3[1]

VccSus3_3/VccLAN3_3[2] VccSus3_3/VccLAN3_3[3] VccSus3_3/VccLAN3_3[4]

ICH7_BGA652~D

Vcc1_05[1] Vcc1_05[2] Vcc1_05[3] Vcc1_05[4] Vcc1_05[5] Vcc1_05[6] Vcc1_05[7] Vcc1_05[8]

Vcc1_05[9] Vcc1_05[10] Vcc1_05[11] Vcc1_05[12] Vcc1_05[13] Vcc1_05[14] Vcc1_05[15] Vcc1_05[16] Vcc1_05[17] Vcc1_05[18] Vcc1_05[19] Vcc1_05[20]

Vcc3_3 / VccHDA

VccSus3_3/VccSusHDA

V_CPU_IO[1] V_CPU_IO[2] V_CPU_IO[3]

Vcc3_3[3] Vcc3_3[4] Vcc3_3[5] Vcc3_3[6] Vcc3_3[7] Vcc3_3[8]

Vcc3_3[9] Vcc3_3[10] Vcc3_3[11]

Vcc3_3[12] Vcc3_3[13] Vcc3_3[14] Vcc3_3[15] Vcc3_3[16] Vcc3_3[17] Vcc3_3[18] Vcc3_3[19] Vcc3_3[20] Vcc3_3[21]

VccRTC VccSus3_3[1] VccSus3_3[2]

VccSus3_3[3] VccSus3_3[4] VccSus3_3[5] VccSus3_3[6]

VccSus3_3[7] VccSus3_3[8] VccSus3_3[9]

VccSus3_3[10] VccSus3_3[11] VccSus3_3[12] VccSus3_3[13] VccSus3_3[14] VccSus3_3[15] VccSus3_3[16] VccSus3_3[17] VccSus3_3[18]

Vcc1_5_A[19] Vcc1_5_A[20]

Vcc1_5_A[21] Vcc1_5_A[22] Vcc1_5_A[23]

Vcc1_5_A[24] Vcc1_5_A[25]

VccSus1_05[1] VccSus1_05[2]

VccSus1_05[3]

Vcc1_5_A[26] Vcc1_5_A[27] Vcc1_5_A[28] Vcc1_5_A[29] Vcc1_5_A[30]

L11 L12 L14 L16 L17 L18 M11 M18 P11 P18 T11 T18 U11 U18 V11 V12 V14 V16 V17 V18

U6 R7 AE23

AE26 AH26

AA7 AB12 AB20 AC16 AD13 AD18 AG12 AG15 AG19

A5 B13 B16 B7 C10 D15 F9 G11 G12 G16

W5 P7 A24

C24 D19 D22 G19

K3 K4 K5 K6 L1 L2 L3 L6 L7 M6 M7 N7

AB17 AC17

T7 F17 G17

AB8 AC8

K7 C28

G20 A1

H6 H7 J6 J7

+VCCP

0.1U_0402_16V4Z

1

C357

C363

2

1U_0603_10V4Z

1

C368

2

0.1U_0402_16V4Z

1

C386

0.1U_0402_16V4Z

2

1

C367

0.1U_0402_16V4Z

2

+1.5VS

1 2

C348 0.1U_0402_16V4Z

ICH_K7 ICH_C28

ICH_G20

+1.5VS

1

C360

0.1U_0402_16V4Z

2

1

2

+3VALW

+3VS

1

C359

0.1U_0402_16V4Z

2

1

C350

2

0.1U_0402_16V4Z

1

C376

0.1U_0402_16V4Z

2

1

C377

0.1U_0402_16V4Z

2

1

+

C351 220U_D2_4VM

2

C337

0.1U_0402_16V4Z

T46PAD T15PAD

T43PAD

+VCCP

+3VS

+3VALW

C354

1 2

0.1U_0402_16V4Z

1 2

C353

0.1U_0402_16V4Z

1 2

C358

4.7U_0805_10V4Z

C369

0.1U_0402_16V4Z

U3E

A4

VSS[0]

A23

VSS[1]

B1

VSS[2]

B8

VSS[3]

B11

VSS[4]

B14

VSS[5]

B17

VSS[6]

B20

VSS[7]

B26

VSS[8]

B28

VSS[9]

C2

VSS[10]

C6

VSS[11]

C27

VSS[12]

D10

VSS[13]

D13

VSS[14]

D18

VSS[15]

D21

VSS[16]

D24

VSS[17]

E1

VSS[18]

E2

VSS[19]

E4

VSS[21]

E8

VSS[22]

+3VS

1

C356

0.1U_0402_16V4Z

2

+RTCVCC

1

C370

2

0.1U_0402_16V4Z

E15

F3 F4

F5 F12 F27 F28

G1 G2 G5 G6

G9 G14 G18 G21 G24 G25 G26

H3

H4

H5

H24 H27 H28

J1 J2

J5 J24 J25 J26

K24 K27 K28 L13 L15 L24 L25 L26

M3 M4

M5 M12 M13 M14 M15 M16 M17 M24 M27 M28

N1

N2

N5

N6

N11 N12 N13 N14 N15 N16 N17 N18 N24 N25 N26

P3

P4 P12 P13 P14 P15 P16 P17 P24 P27

ICH7_BGA652~D

VSS[23] VSS[24] VSS[25] VSS[26] VSS[27] VSS[28] VSS[29] VSS[30] VSS[31] VSS[32] VSS[33] VSS[34] VSS[35] VSS[36] VSS[37] VSS[38] VSS[39] VSS[40] VSS[41] VSS[42] VSS[43] VSS[44] VSS[45] VSS[46] VSS[47] VSS[48] VSS[49] VSS[50] VSS[51] VSS[52] VSS[53] VSS[54] VSS[55] VSS[56] VSS[57] VSS[58] VSS[59] VSS[60] VSS[61] VSS[62] VSS[63] VSS[64] VSS[65] VSS[66] VSS[67] VSS[68] VSS[69] VSS[70] VSS[71] VSS[72] VSS[73] VSS[74] VSS[75] VSS[76] VSS[77] VSS[78] VSS[79] VSS[80] VSS[81] VSS[82] VSS[83] VSS[84] VSS[85] VSS[86] VSS[87] VSS[88] VSS[89] VSS[90] VSS[91] VSS[92] VSS[93] VSS[94] VSS[95] VSS[96] VSS[97]

VSS[98]

VSS[99] VSS[100] VSS[101] VSS[102] VSS[103] VSS[104] VSS[105] VSS[106] VSS[107] VSS[108] VSS[109] VSS[110] VSS[111] VSS[112] VSS[113] VSS[114] VSS[115] VSS[116] VSS[117] VSS[118] VSS[119] VSS[120] VSS[121] VSS[122] VSS[123] VSS[124] VSS[125] VSS[126] VSS[127] VSS[128] VSS[129] VSS[130] VSS[131] VSS[132] VSS[133] VSS[134] VSS[135] VSS[136] VSS[137] VSS[138] VSS[139] VSS[140] VSS[141] VSS[142] VSS[143] VSS[144] VSS[145] VSS[146] VSS[147] VSS[148] VSS[149] VSS[150] VSS[151] VSS[152] VSS[153] VSS[154] VSS[155] VSS[156] VSS[157] VSS[158] VSS[159] VSS[160] VSS[161] VSS[162] VSS[163] VSS[164] VSS[165] VSS[166] VSS[167] VSS[168] VSS[169] VSS[170] VSS[171] VSS[172] VSS[173] VSS[174] VSS[175] VSS[176] VSS[177] VSS[178] VSS[179] VSS[180] VSS[181] VSS[182] VSS[183] VSS[184] VSS[185] VSS[186] VSS[187] VSS[188] VSS[189] VSS[190] VSS[191] VSS[192] VSS[193] VSS[194]

P28 R1 R11 R12 R13 R14 R15 R16 R17 R18 T6 T12 T13 T14 T15 T16 T17 U4 U12 U13 U14 U15 U16 U17 U24 U25 U26 V2 V13 V15 V24 V27 V28 W6 W24 W25 W26 Y3 Y24 Y27 Y28 AA1 AA24 AA25 AA26 AB4 AB6 AB11 AB14 AB16 AB19 AB21 AB24 AB27 AB28 AC2 AC5 AC9 AC11 AD1 AD3 AD4 AD7 AD8 AD11 AD15 AD19 AD23 AE2 AE4 AE8 AE11 AE13 AE18 AE21 AE24 AE25 AF2 AF4 AF8 AF11 AF27 AF28 AG1 AG3 AG7 AG11 AG14 AG17 AG20 AG25 AH1 AH3 AH7 AH12 AH23 AH27

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/10/06 2006/10/06

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet of

Compal Electronics, Inc.

SCHEMATIC, M/B LA-3281

401429

星期三七月

06

1

22 47, 12, 20

B

5

4

3

2

1

D D

PSATA_ITX_DRX_P0<20> PSATA_ITX_DRX_N0<20>

PSATA_IRX_DTX_N0_C<20>

PSATA_IRX_DTX_P0_C<20>

+3VS

+5VS

C C

IDERST_CD#<21> PLT_RST#<7,19,28>

B B

ODD_LED#<37>

12

C230 3900P_0402_50V7K

12

C234 3900P_0402_50V7K

1 2

R151 0_0805_5%@

1 2

R170 0_0805_5%

R262 0_0402_5%@

1 2

R267 33_0402_5%

1 2

+3VS

12

R249

10K_0402_5%

ODD_LED#

PSATA_ITX_DRX_P0 PSATA_ITX_DRX_N0

PSATA_IRX_DTX_N0

PSATA_IRX_DTX_P0

INT_CD_L<29> INT_CD_R <29>

CD_AGND<29>

+5VS

PD_IOW# PD_IORDY PD_IRQ PD_A1 PD_A0 PD_CS#1

PRI_CSEL

R231 470_0402_5%

1 2

PD_IOW#<20>

PD_IORDY<20>

PD_IRQ<20>

PD_CS#1<20> PD_CS#3 <20>

JP9

1

GND

2

A+

3

A-

4

GND

5

B-

6

B+

7

GND

8

V33

9

V33

10

V33

11

GND

12

GND

13

GND

14

V5

15

V5

16

V5

17

GND

18

Reserved

19

GND

20

V12

21

V12

22

V12

ALLTO_C16630-122A4-L_RV

Main SATA +5V Default

PD_D[0..15] PD_A[0..2]

JP10

112 334

PD_D7 PD_D6 PD_D5 PD_D4 PD_D3 PD_D2 PD_D1 PD_D0

556 778 9910 111112 131314 151516 171718 191920 212122 232324 252526 272728 292930 313132 333334 353536 373738 393940 414142 434344 454546 474748 494950

OCTEK_CDR-50DY1G

ME@

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50

PD_D[0..15] <20>

PD_A[0..2] <20>

PD_D8 PD_D9 PD_D10 PD_D11 PD_D12 PD_D13 PD_D14 PD_D15 PD_DREQ PD_IOR#

PD_DACK# PDIAG#

PD_A2 PD_CS#3

12

C347 0.1U_0402_16V4Z

1

C266

C257

2

22U_1206_6.3V6M

PD_DREQ <20> PD_IOR# <20>

PD_DACK# <20>

1 2

R244 100K_0402_5%

+5VS

+5VS +3VS

0.1U_0402_16V4Z

1

2

1000P_0402_50V7K

Pleace near HD CONN

C256

2

+5VS

1

C271

2

1U_0603_10V4Z

1

C258

2

0.1U_0402_16V4Z

1

C246

C252

2

22U_1206_6.3V6M

1000P_0402_50V7K

@

+5VS

0.1U_0402_16V4Z@

1

2

C247

2

Pleace near HD CONN

1

C344 1U_0603_10V4Z

2

1

2

1

C251

2

1U_0603_10V4Z@

C336 10U_0805_10V4Z

1

C245

2

0.1U_0402_16V4Z

@

A A

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DIS CLOSE D TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/10/06 2006/10/06

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, M/B LA-3281

401429

星期三七月

23 47, 12, 2006

1

B

of

A

B

C

D

E

CARD_S1_A[0..25]

CARD_S1_D[0..15] PCI_AD[0..31]

Power on RESET#

CLK_PCI_PCM

12

1

2

>1ms

Reset# Here

>1ms

SUSP#<18,26,33,34,35,43,44>

1 2

+3VS

R318 10K_0402_5%

21

D17 RB751V_SOD323@

Note: MF0 -- MF6 must refer the data sheet for design.

4 4

VCC

CLK

SUSPEND#

PCIRST#

3 3

Entry S3

SUSPEND#

PCIRST#

SUSPEND# will gate the PCIRST# or GRST#, so need S3 wake up function, SUSPEND# must be LOW ahead the PCIRST# about 1ms.

2 2

R379

33_0402_5%@

C429

10P_0402_25V8K

1 1

@

CARD_S1_A[0..25] <25> CARD_S1_D[0..15] <25> PCI_AD[0..31] <19,26,27,32>

PCI_CBE#3<19,26,27,32> PCI_CBE#2<19,26,27,32> PCI_CBE#1<19,26,27,32> PCI_CBE#0<19,26,27,32>

PCI_RST#<19,21,25,26,27,32,33>

PCI_FRAME#<19,26,27,32>

PCI_IRDY#<19,26,27>

PCI_TRDY#<19,26,27,32>

PCI_DEVSEL#<19,26,27>

PCI_STOP#<19,26,27> PCI_PERR#<19,26,27> PCI_SERR#<19,26,27>

PCI_PAR<19,26,27>

PCI_REQ2#<19>

PCI_GNT2#<19>

CLK_PCI_PCM<15>

CB_PME#<33>

PCI_AD20

1 2

R408 100_0402_5%

PCI_PIRQA#<19>

SIRQ<21,26,32,33>

PCI_CLKRUN#<21,26,27,33>

PCI_RST#<19,21,25,26,27,32,33>

PCI_CBE#3 PCI_CBE#2 PCI_CBE#1 PCI_CBE#0

CLK_PCI_PCM

PCI_PIRQA#

4.7U_0805_10V4Z

VPPD0<25>

VPPD1<25> VCCD0#<25> VCCD1#<25>

PCI_AD31 PCI_AD30 PCI_AD29 PCI_AD28 PCI_AD27 PCI_AD26 PCI_AD25 PCI_AD24 PCI_AD23 PCI_AD22 PCI_AD21 PCI_AD20 PCI_AD19 PCI_AD18 PCI_AD17 PCI_AD16 PCI_AD15 PCI_AD14 PCI_AD13 PCI_AD12 PCI_AD11 PCI_AD10 PCI_AD9 PCI_AD8 PCI_AD7 PCI_AD6 PCI_AD5 PCI_AD4 PCI_AD3 PCI_AD2 PCI_AD1 PCI_AD0

PCI_RST#

PCI_PCM_ID

C400

U28

3

AD31

4

AD30

5

AD29

7

AD28

8

AD27

9

AD26

10

AD25

11

AD24

15

AD23

16

AD22

17

AD21

19

AD20

23

AD19

24

AD18

25

AD17

26

AD16

38

AD15

39

AD14

40

AD13

41

AD12

43

AD11

45

AD10

46

AD9

47

AD8

49

AD7

51

AD6

52

AD5

53

AD4

54

AD3

55

AD2

56

AD1

57

AD0

12

C/BE3#

27

C/BE2#

37

C/BE1#

48

C/BE0#

20

RST#

28

FRAME#

29

IRDY#

31

TRDY#

32

DEVSEL#

33

STOP#

34

PERR#

35

SERR#

36

PAR

1

REQ#

2

GNT#

21

PCLK

59

RI_OUT#/PME#

70

SUSPEND#

13

IDSEL

60

MFUNC0

61

MFUNC1

64

MFUNC2

65

MFUNC3

67

MFUNC4

68

MFUNC5

69

MFUNC6

66

VCC/GRST#

1

C402

0.1U_0402_16V4Z

2

72

74

VPPD071VPPD1

VCCD0#73VCCD1#

PQFP 144

22.2 X 22.2 X 1.60

GND1

GND2

6

22

+3VS

44

GND3

42

58

18

VCCP1

VCCP0

GND4

GND5

GND6

78

94

+S1_VCC

1

C456

0.1U_0402_16V4Z

2

138

90

126

VCC1

VCCSK1

VCCSK0

GND7

GND8

114

130

86

102

122

VCC4

VCC3

VCC2

RSVD/D14

RSVD/A18

RSVD/D2

84

100

143

1

C436

0.1U_0402_16V4Z

2

+3VS

0.1U_0402_16V4Z

14

30

50

63

VCCI

VCC7

VCC6

VCC5

CAD31/D10

CAD30/D9 CAD29/D1 CAD28/D8 CAD27/D0

CAD26/A0 CAD25/A1 CAD24/A2 CAD23/A3 CAD22/A4 CAD21/A5 CAD20/A6

CAD19/A25

CAD18/A7 CAD17/A24 CAD16/A17

CAD15/IOWR#

CAD14/A9

CAD13/IORD#

CAD12/A11

CAD11/OE#

CAD10/CE2#

CAD9/A10

CAD8/D15

CAD7/D7

CAD6/D13

CAD5/D6

CAD4/D12

CAD3/D5

CAD2/D11

CAD1/D4 CAD0/D3

CC/BE3#/REG#

CC/BE2#/A12

CC/BE1#/A8

CC/BE0#/CE1# CRST#/RESET

CFRAME#/A23

CIRDY#/A15

CTRDY#/A22

CDEVSEL#/A21

CSTOP#/A20 CPERR#/A14

CSERR#/WAIT#

CPAR/A13

CREQ#/INPACK#

CGNT#/WE#

CCLK/A16

CSTSCHG/BVD1

CCLKRUN#/WP

CBLOCK#/A19

CINT#/READY

SPKOUT

CAUDIO/BVD2

CCD2#/CD2# CCD1#/CD1#

CVS2/VS2# CVS1/VS1#

CB1410_LQFP144

1 2

C403

144 142 141 140 139 129 128 127 124 121 120 118 116 115 113 98 96 97 93 95 92 91 89 87 85 82 83 80 81 77 79 76

125 112 99 88

119 111 110 109 107 105 104 133 101 123 106 108

135 136

103 132 62

134 137

75 117 131

0.1U_0402_16V4Z

CARD_S1_D10 CARD_S1_D9 CARD_S1_D1 CARD_S1_D8 CARD_S1_D0 CARD_S1_A0 CARD_S1_A1 CARD_S1_A2 CARD_S1_A3 CARD_S1_A4 CARD_S1_A5 CARD_S1_A6 CARD_S1_A25 CARD_S1_A7 CARD_S1_A24 CARD_S1_A17 CARD_S1_IOWR# CARD_S1_A9 CARD_S1_IORD# CARD_S1_A11 CARD_S1_OE# CARD_S1_CE2# CARD_S1_A10 CARD_S1_D15 CARD_S1_D7 CARD_S1_D13 CARD_S1_D6 CARD_S1_D12 CARD_S1_D5 CARD_S1_D11 CARD_S1_D4 CARD_S1_D3

CARD_S1_REG# CARD_S1_A12 CARD_S1_A8 CARD_S1_CE1#

CARD_S1_RST CARD_S1_A23 CARD_S1_A15 CARD_S1_A22 CARD_S1_A21 CARD_S1_A20 CARD_S1_A14 CARD_S1_WAIT# CARD_S1_A13 CARD_S1_INPACK# CARD_S1_WE# CARD_A16_CLK

CARD_S1_BVD1 CARD_S1_WP

CARD_S1_A19 CARD_S1_RDY# PCM_SPK#

CARD_S1_BVD2 CARD_S1_CD2#

CARD_S1_CD1# CARD_S1_VS2 CARD_S1_VS1

CARD_S1_D2 CARD_S1_A18 CARD_S1_D14

+3VS

C438

0.1U_0402_16V4Z

1

2

1

2

C421

0.1U_0402_16V4Z

C455

1

2

1

2

C445

0.1U_0402_16V4Z

C431

0.1U_0402_16V4Z

1

2

1

2

C404

0.1U_0402_16V4Z

ENE CB1410 just have one vcc plane internal, if want S3 wake-up function(PME#),then at S3 status must keep all Vcc +3V. That is different with TI 1410 and O2-Micro 6912, just keep the VCCI pin +3V, the other vcc can use +3VS.

CARD_S1_IOWR# <25> CARD_S1_IORD# <25> CARD_S1_OE# <25>

CARD_S1_CE2# <25>

CARD_S1_REG# <25>

CARD_S1_CE1# <25> CARD_S1_RST <25>

CARD_S1_WAIT# <25> CARD_S1_INPACK# <25>

CARD_S1_WE# <25>

1 2

R420 33_0402_5%

CARD_S1_BVD1 <25> CARD_S1_WP <25>

CARD_S1_RDY# <25> PCM_SPK# <29>

CARD_S1_BVD2 <25> CARD_S1_CD2# <25>

CARD_S1_CD1# <25> CARD_S1_VS2 <25> CARD_S1_VS1 <25>

CARD_S1_OE# CARD_S1_CE2# CARD_S1_CE1# CARD_S1_RST

CARD_S1_A16

R806 43K_0402_5%@

1 2

R807 43K_0402_5%@

1 2

R808 43K_0402_5%@

1 2

R809 43K_0402_5%@

1 2

C454

0.1U_0402_16V4Z

1

2

+S1_VCC

Security Classification

Issued Date

PROPRIETARY NOTE

A

B

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLO SED TO ANY THI RD PART Y WITHO UT P RIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2005/10/06 2006/10/06

C

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

SCHEMATIC, M/B LA-3281

Size Document Number Rev

Custom

401429

星期三

, 12, 2006

D

Date: Sheet

七月

E

of

24 47

B

A

B

C

D

E

PCMCIA Power Controller

CARD_S1_A[0..25]<24>

+S1_VCC

U5

1 1

+5VS

1

C193

2

+3VS

10U_1206_10V4Z

0.1U_0402_16V4Z

1

C194 10U_1206_10V4Z

2

2 2

0.1U_0402_16V4Z

C198

C197

1

2

1

2

+5VS

+3VS

9

12V

5

5V

6

5V

3

3.3V

4

3.3V GND

7

VCC VCC VCC

VPP

VCCD0 VCCD1

VPPD0 VPPD1

OC

SHDN

CP-2211_SSOP16

16

13 12 11

10

1 2 15 14

8

PCI_RST#

1

C210

0.1U_0402_16V4Z

2

+S1_VPP

1

C209

0.1U_0402_16V4Z

2

VCCD0# <24> VCCD1# <24> VPPD0 <24> VPPD1 <24>

PCI_RST# <19,21,24,26,27,32,33>

CARD_S1_D[0..15]<24>

+S1_VPP

1

C241

2

0.01U_0402_16V7K

CARD_S1_CE1#<24>

CARD_S1_OE#<24>

CARD_S1_WE#<24>

CARD_S1_RDY#<24>

CARD_S1_WP<24>

1

2

CARD_S1_A[0..25] CARD_S1_D[0..15]

CARD_S1_D3 CARD_S1_D4 CARD_S1_D5 CARD_S1_D6 CARD_S1_D7 CARD_S1_CE1# CARD_S1_A10 CARD_S1_OE# CARD_S1_A11 CARD_S1_A9 CARD_S1_A8 CARD_S1_A13 CARD_S1_A14 CARD_S1_WE#

+S1_VCC +S1_VCC +S1_VPP

C215

4.7U_0805_10V4Z

CARD_S1_RDY#

CARD_S1_A16 CARD_S1_A15 CARD_S1_A12 CARD_S1_A7 CARD_S1_A6 CARD_S1_A5 CARD_S1_A4 CARD_S1_A3 CARD_S1_A2 CARD_S1_A1 CARD_S1_A0 CARD_S1_D0 CARD_S1_D1 CARD_S1_D2

CARD_S1_WP

2

C243 1U_0805_25V4Z

1

JP11

1

GND D3 D4 D5 D6 D7 CE1# A10 OE# A11 A9 A8 A13 A14 WE# IREQ# VCC VPP1 A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 D0 D1 D2 IOIS16# GND

GND GND GND GND GND GND GND GND

GND GND

ME@

GND

CD1#

CE2#

VS1#

IORD#

IOWR#

VCC

VPP2

VS2#

RESET

WAIT#

INPACK#

REG#

SPKR#

STSCHG#

CD2#

GND GND

GND GND GND GND GND GND GND

GND GND

D11 D12 D13 D14 D15

A17 A18 A19 A20 A21

A22 A23 A24 A25

D10

D8 D9

2 3 4 5 6 7 8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34

69 70 71 72 73 74 75 76

87 88

FOX_WZ21131-G2-P4_LT

35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68

77 78 79 80 81 82 83 84

89 90

C603

1 2

470P_0402_50V8J

CARD_S1_CD1# CARD_S1_D11 CARD_S1_D12 CARD_S1_D13 CARD_S1_D14 CARD_S1_D15 CARD_S1_CE2# CARD_S1_VS1

CARD_S1_IORD#

CARD_S1_IOWR#

CARD_S1_A17 CARD_S1_A18 CARD_S1_A19 CARD_S1_A20 CARD_S1_A21

CARD_S1_A22 CARD_S1_A23 CARD_S1_A24 CARD_S1_A25 CARD_S1_VS2 CARD_S1_RST

CARD_S1_WAIT#

CARD_S1_INPACK#

CARD_S1_REG# CARD_S1_BVD2 CARD_S1_BVD1

CARD_S1_D8 CARD_S1_D9

CARD_S1_D10

CARD_S1_CD2#

C604

1 2

470P_0402_50V8J

C239

0.1U_0402_16V4Z

+S1_VPP

+S1_VCC

1

2

10U_1206_10V4Z

CARD_S1_CD1# <24>

CARD_S1_CE2# <24> CARD_S1_VS1 <24> CARD_S1_IORD# <24> CARD_S1_IOWR# <24>

CARD_S1_VS2 <24> CARD_S1_RST <24> CARD_S1_WAIT# <24> CARD_S1_INPACK# <24> CARD_S1_REG# <24> CARD_S1_BVD2 <24> CARD_S1_BVD1 <24>

CARD_S1_CD2# <24>

1

C216

2

C238

2

0.01U_0402_16V7K

3 3

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLO SED TO ANY THI RD PART Y WITHO UT P RIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2005/10/06 2006/10/06

C

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

SCHEMATIC, M/B LA-3281

Size Document Number Rev

Custom

401429

星期三

, 12, 2006

D

Date: Sheet

七月

E

of

25 47

B

5

PCI_AD[0..31]<19,24,27,32>

D D

PCI_CBE#3<19,24,27,32> PCI_CBE#2<19,24,27,32> PCI_CBE#1<19,24,27,32> PCI_CBE#0<19,24,27,32>

PCI_PAR<19,24,27> PCI_FRAME#<19,24,27,32>

C C

PCI_AD22 CBS_IDSEL

1 2

R455 100_0402_5%

PCI_CLKRUN#<21 , 24,27,33>

SUSP#<18,24,33,34,35,43,44>

B B

PCI_TRDY#<19,24,27,32> PCI_IRDY#<19,24,27> PCI_STOP#<19,24,27> PCI_DEVSEL#<19,24,27>

PCI_PERR#<19,24,27> PCI_SERR#<19,24,27>

PCI_REQ0#<19>

PCI_GNT0#<19>

CLK_PCI_1394<15>

PCI_RST#<19,21,24,25,27,32,33>

R436 10K_0402_5%@

1 2

R435 0_0402_5%

1 2

R5_PME#<33> PCI_PIRQG#<19> PCI_PIRQH#<19>

1 2

+3VS

R464 10K_0402_5%

1 2

R463 0_0402_5%@

PCI_AD31 PCI_AD30 PCI_AD29 PCI_AD28 PCI_AD27 PCI_AD26 PCI_AD25 PCI_AD24 PCI_AD23 PCI_AD22 PCI_AD21 PCI_AD20 PCI_AD19 PCI_AD18 PCI_AD17 PCI_AD16 PCI_AD15 PCI_AD14 PCI_AD13 PCI_AD12 PCI_AD11 PCI_AD10 PCI_AD9 PCI_AD8 PCI_AD7 PCI_AD6 PCI_AD5 PCI_AD4 PCI_AD3 PCI_AD2 PCI_AD1 PCI_AD0

PCI_CBE#3 PCI_CBE#2 PCI_CBE#1 PCI_CBE#0

PCI_PAR PCI_FRAME# PCI_TRDY# PCI_IRDY# PCI_STOP# PCI_DEVSEL#

PCI_PERR# PCI_SERR#

PCI_REQ0# PCI_GNT0#

CBS_GRST#

R5_PME#

U34

125

AD31

126

AD30

127

AD29

1

AD28

2

AD27

3

AD26

5

AD25

6

AD24

9

AD23

11

AD22

12

AD21

14

AD20

15

AD19

17

AD18

18

AD17

19

AD16

36

AD15

37

AD14

38

AD13

39

AD12

40

AD11

42

AD10

43

AD9

44

AD8

46

AD7

47

AD6

48

AD5

49

AD4

50

AD3

51

AD2

52

AD1

53

AD0

7

C/BE3#

21

C/BE2#

35

C/BE1#

45

C/BE0#

33

PAR

23

FRAME#

25

TRDY#

24

IRDY#

29

STOP#

26

DEVSEL#

8

IDSEL

30

PERR#

31

SERR#

124

REQ#

123

GNT#

121

PCICLK

119

PCIRST#

71

GBRST#

117

CLKRUN#

70

PME#

115

INTA#

116

INTB#

69

HWSPND#

66

TEST

111

AGND

107

AGND

103

AGND

102

AGND

99

AGND

97

NC

R5C832_TQFP128~D

R5C832

Layout Note: Place close to R5C832

1

2

CLK_PCI_1394

12

R444

@

10_0402_5%

2

A A

C463

1

@

4.7P_0402_50V8C

+3VS

12

R462

CBS_GRST#

1

C493 1U_0603_10V6K

2

1 2

IEEE1394_TPBN0 IEEE1394_TPBP0

100K_0402_5%

5

IEEE1394_TPAN0 IEEE1394_TPAP0

IEEE1394_TPBIAS0

1 2

12

C453

R439

R437

R421

270P_0402_50V7K

56.2_0603_1%

5.1K_0603_1%

Z3008

R440

1 2

56.2_0603_1%

2

R438

1 2

1

56.2_0603_1%

4

VCC_PCI3V VCC_PCI3V VCC_PCI3V VCC_PCI3V VCC_PCI3V VCC_PCI3V

VCC_RIN

VCC_ROUT VCC_ROUT VCC_ROUT VCC_ROUT VCC_ROUT

VCC_3V

VCC_MD3V

AVCC_PHY3V AVCC_PHY3V AVCC_PHY3V AVCC_PHY3V

TPBIAS0

TPAP0 TPAN0

TPBP0 TPBN0

MDIO00 MDIO01 MDIO02 MDIO03 MDIO04 MDIO05 MDIO06 MDIO07 MDIO08 MDIO09 MDIO10 MDIO11 MDIO12 MDIO13 MDIO14 MDIO15 MDIO16 MDIO17 MDIO18 MDIO19

MSEN

XDEN

REXT VREF

UDIO0/SERIRQ#

UDIO1 UDIO2 UDIO3 UDIO4 UDIO5

GND GND GND GND GND GND GND GND GND GND

10 20 27 32 41 128

61 16

34 64 114 120

67 86 98

106 110 112

113 109

108 105

104 80

79 78 77 76 75 74 73 88 84 82 81 93 90 91 89 92 87 85 83

58 55

94

XI

95

XO

96

FIL0

101 100

72 60 56 65 59 57

4 13 22 28 54 62 63 68 118 122

+3VS

+3V_PHY

IEEE1394_TPBIAS0 IEEE1394_TPAP0

IEEE1394_TPAN0 IEEE1394_TPBP0

IEEE1394_TPBN0 SDCD#_XDCD0#

MSCD#_XDCD1 XD_CE# SDWP#_XDRB# SDPWR0_MSPW R _XDPW R XDWP# 3IN1_LED# TP_MSEXTCK SDCMD_MSBS SDCLK_MSCLK SDDATA0_MSDATA0 SDDATA1_MSDATA1 SDDATA2_MSDATA2 SDDATA3_MSDATA3 XDD4 XDD5 XDD6 XDD7 XDCLE XDALE

MSEN XDEN

R5C832XI R5C832XO

SIRQ TP_UDIO1 TP_UDIO2 UDIO3 UDIO4 UDIO5

1

C468

2

0.01U_0402_16V7K

SDCD#_XDCD0# <37> MSCD#_XDCD1 <37>

XD_CE# <37>

SDWP#_XDRB# <37>

XDWP# <37>

3IN1_LED# <37>

SDCMD_MSBS <37>

SDCLK_MSCLK <37> SDDATA0_MSDATA0 <37> SDDATA1_MSDATA1 <37> SDDATA2_MSDATA2 <37> SDDATA3_MSDATA3 <37>

XDD4 <37>

XDD5 <37>

XDD6 <37>

XDD7 <37>

XDCLE <37> XDALE <37>

1 2

C471

SIRQ <21,24,32,33>

T49PAD T48PAD

C506

40mil

VOUT VOUT

1 5

+VCC_4IN1

C517

+3VS

SDPWR0_MSPW R _XDPW R

1

2

1 2 3 4

SUYIN_020115FB004S512ZL

Layout Note: Shield GND for

2

IEEE1394_TPA and TPB

C462

C459

1

0.33U_0603_16V4Z

0.01U_0402_16V7K

4

ME@

JP13

TPBTPB+ TPATPA+

C494

0.1U_0402_16V4Z

U35

3

VIN

4

VIN/CE

2

GND

RT9701CB_SOT25

GND GND GND GND

5 6 7 8

3

10U_0805_4VAM

+3VS

1

C505

C486

2

10U_0805_4VAM

0.01U_0402_16V7K

2

R441

C461

1

1 2

0.01U_0402_16V7K

Layout Note: Shield GND for CBS_CCLK_INTERNAL and CBS_CCLK

+VCC_4IN1

12

1

2

1U_0603_10V4Z

1

R483

C521

2

150K_0402_5%

10U_1206_6.3V6M

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONF IDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFOR MATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

1

C460

2

+3VS

15P_0603_50V8J

1

C491

2

0.47U_0603_16V4Z

0.01U_0402_16V7K

L18

1 2

BLM21A601SPT_0805

C481

1 2

C473

1 2

1

2

1 2

1

C464

2

0.01U_0402_16V7K

Layout Not e: Place close to R 5C832 and Shield GND for SDCLK_MSCLK

10K_0603_1%

1

C437

2

0.1U_0402_16V4Z

2005/10/06 2006/10/06

2

+3VS

1

C515

C507

2

C516

0.47U_0603_16V4Z

R5C832XI

X2

24.576MHz_16P_1BG24576CKIA

R5C832XO

2

0.01U_0402_16V7K

1

C470

C465

2

0.1U_0402_16V4Z

22U_0805_6.3V6M

Layout Note: Place close to R5C832 and Shield GND f o r S D_CLK

Compal Secret Data

Deciphered Date

2

0.1U_0402_16V4Z

1

2

1

C489

2

1

C469

2

0.1U_0402_16V4Z

SD,MMC,MS,XD muti-function pin define

MDIO PIN Name MDIO00

MDIO01 MDIO02 MDIO03

1

C522

2

0.01U_0402_16V7K

MDIO04 MDIO05 MDIO06 MDIO07

10U_0805_4VAM

MDIO08 MDIO09 SDCCLK MDIO10

+3V_PHY

MDIO11 MDIO12 MDIO13 MDIO14

1

C466

2

1000P_0402_50V7K

MDIO15 MDIO16

C467

MDIO17

1000P_0402_50V7K

MDIO18 MDIO19

Function set pin define

Pull-up

R490 0_0402_5%

SDDATA1_MSDATA1

SDDATA2_MSDATA2

+VCC_4IN1

+5VS

1 2

R456 10K_0402_5%@

1 2

R452 10K_0402_5%@

SDCD#_XDCD0# XDCD#

Q34

@

2N7002_SOT23

MSCD#_XDCD1 SDCD#_XDCD0#

1

SD Card PIN Name SDCD#

MMC Card PIN Name MMCCD#

MS Card PIN Name

MSCD#

SDWP# SDPWR0

MMCPWR

MSWR SDPWR1 SDLED#

MMCLED#

MSLED#

MSEXTCK

Pull-up

1 2 1 2 1 2 1 2

1 2

SD_MSDATA1

SD_MSDATA2

D

S

Q31

@

2N7002_SOT23

G

2

13

D

S

Q32

@

2N7002_SOT23

XDCD# <37>

1

MSBS

MSCCLK

MSCDAT0

MSCDAT1

MSCDAT2

MSCDAT3

Function

SD,XD,MS,MMC Card

+VCC_4IN1_XD

SDCCMD

MMCCMD MMCCLK

SDCDAT0

MMCDAT SDCDAT1 SDCDAT2 SDCDAT3

MSEN XDENUDIO3 UDIO4

Pull-upPull-up Enable

MSEN

R474 10K_0402_5%

UDIO3

R468 10K_0402_5%

UDIO4

R475 10K_0402_5%

UDIO5

R473 100K_0402_5%

XDEN

R472 10K_0402_5%

Solve MS Duo Adaptor short problem

12

Q33

@

D

S

2N7002_SOT23

1 3

R491 0_0402_5%

G

2

13

D

2

G

S

D22

2 3

DAN202U_SC70

Title

Size Document Number Re v

Custom

Date: Sheet of

12

Q35

@

2N7002_SOT23

D

S

1 3

1 2

R453 0_0805_5%

G

2

1 3

2

G

XDCD#

1

Compal Electronics, Inc.

SCHEMATIC, M/B LA-3281

401429

星期三七月

12, 2006

XD Card PIN Name XDCD0#

XDCD1# XDCE# XDR/B# XDPWR XDWP# XDLED#

XDWE# XDRE# XDCDAT0 XDCDAT1 XDCDAT2 XDCDAT3 XDCDAT4 XDCDAT5 XDCDAT6 XDCDAT7 XDCLE XDALE

+3VS

SD_MSDATA1 <37>

SD_MSDATA2 <37>

26 47,

B

5

U24

8100CL

100@

D D

C C

B B

A A

R403

5.6K_0603_1%

100@

PCI_AD[0..31]<19,24,26,32>

PCI_CBE#0<19,24,26,32> PCI_CBE#1<19,24,26,32> PCI_CBE#2<19,24,26,32> PCI_CBE#3<19,24,26,32>

PCI_AD17 LAN_IDSEL

PCI_PAR<19,24,26>

PCI_FRAME#<19,24,26,32>

PCI_IRDY#<19,24,26>

PCI_TRDY#<19,24,26,32>

PCI_DEVSEL#<19,24,26>

PCI_STOP#<19,24,26>

PCI_PERR#<19,24,26> PCI_SERR#<19,24,26>

PCI_REQ3#<19>

PCI_GNT3#<19>

PCI_PIRQF#<19>

LAN_PME#<33>

PCI_RST#19,21,24,25,26,32,33>

CLK_PCI_LAN<15>

PCI_CLKRUN#<21,24,26,33>

CLK_PCI_LAN

12

R316

10_0402_5%

@

1

C397 10P_0402_50V8J

@

2

PCI_AD[0..31]

PCI_AD0 PCI_AD1 PCI_AD2 PCI_AD3 PCI_AD4 PCI_AD5 PCI_AD6 PCI_AD7 PCI_AD8 PCI_AD9 PCI_AD10 PCI_AD11 PCI_AD12 PCI_AD13 PCI_AD14 PCI_AD15 PCI_AD16 PCI_AD17 PCI_AD18 PCI_AD19 PCI_AD20 PCI_AD21 PCI_AD22 PCI_AD23 PCI_AD24 PCI_AD25 PCI_AD26 PCI_AD27 PCI_AD28 PCI_AD29 PCI_AD30 PCI_AD31

PCI_CBE#0 PCI_CBE#1 PCI_CBE#2 PCI_CBE#3

1 2

R302 100_0402_5%

CLK_PCI_LAN

5

CTRL25

R498

0_0603_5%

C385

12

1U_0603_10V4Z

1

Q27

2SB1188_SC62

U24

104

AD0

103

AD1

102

AD2

98

AD3

97

AD4

96

AD5

95

AD6

93

AD7

90

AD8

89

AD9

87

AD10

86

AD11

85

AD12

83

AD13

82

AD14

79

AD15

59

AD16

58

AD17

57

AD18

55

AD19

53

AD20

50

AD21

49

AD22

47

AD23

43

AD24

42

AD25

40

AD26

39

AD27

37

AD28

36

AD29

34

AD30

33

AD31

92

C/BE#0

77

C/BE#1

60

C/BE#2

44

C/BE#3

46

IDSEL

76

PAR

61

FRAME#

63

IRDY#

67

TRDY#

68

DEVSEL#

69

STOP#

70

PERR#

75

SERR#

30

REQ#

29

GNT#

25

INTA#

31

PME#

27

RST#

28

CLK

65

CLKRUN#

4

GND/VSS

17

GND/VSS

128

GND/VSS

21

GND/VSSPST

38

GND/VSSPST

51

GND/VSSPST

66

GND/VSSPST

81

GND/VSSPST

91

GND/VSSPST

101

GND/VSSPST

119

GND/VSSPST

35

GND

52

GND

80

GND

100

GND

RTL8110SBL_LQFP128

GIGA@

+3VALW

PCI I/F

+3VS

12

2 3

C433

22U_A_4VM

TXD+/MDI0+

RXIN+/MDI1+

RXIN-/MDI1-

NC/SMBCLK

NC/SMBDATA

NC/HSDAC+

LAN I/F

Power

12

R499 0_0603_5%

@

+2.5V_LAN

1

+

2

EEDO

AUX/EEDI

EESK EECS

LED0 LED1 LED2

NC/LED3

TXD-/MDI0-

NC/MDI2+

NC/MDI2-

NC/MDI3+

NC/MDI3-

LWAKE

ISOLATE#

RTSET

NC/M66EN NC/AVDDH

AVDDH

NC/HG

NC/LG2

VDD12A

NC/VSS NC/VSS

NC/GND NC/GND NC/GND NC/GND NC/GND NC/GND

CTRL25 CTRL12

VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33

AVDDL AVDDL AVDDL AVDDL

VDD12 VDD12 VDD12 VDD12

NC/VDD12 NC/VDD12 NC/VDD12 NC/VDD12 NC/VDD12

+3V_LAN

1

2

X1 X2

NC

108 109 111 106

117 115 114 113

1 2 5 6

14 15 18 19

121 122

105 23 127 72 74

88 10

120 11

123 124 126

9 13

22 48 62 73 112 118

8 125 26

41 56 71 84 94 107

3 7 20 16

32 54 78 99

24 45 64 110 116

12

C393

4

CTRL12

0.1U_0402_16V4Z

R400 3.6K_0402_5%

LAN_EEDO LAN_EEDI LAN_EECLK LAN_EECS

ACTIVITY# LINK_10_100#

TXD+/MDI0+ TXD-/MDI0RXIN+/MDI1+ RXIN-/MDI1-

NC/MDI2+ NC/MDI2NC/MDI3+ NC/MDI3-

LAN_X1 LAN_X2

ISOLATE#

RTSET

5.6K for 8100CL

2.49K for 8110S(B)

+AVDDH

0_0402_5%

12

R354

GIGA@

DVDD_A

0.1U_0402_16V4Z

CTRL25 CTRL12

1

C394

0.1U_0402_16V4Z

2

1

C409

0.1U_0402_16V4Z

2

1

C405

0.1U_0402_16V4Z

2

GIGA@

V_12P

1

C414

0.1U_0402_16V4Z

2

4

1

2

C380

1

R350 R351

+3V_LAN

2SB1188_SC62GIGA@

1

Q21

2 3

+

GIGA@

C374

22U_A_4VM

1 2

U31

4

DO

3

DI

2

SK

1

CS

R319 1K_0402_5%

1 2

R317 15K_0402_5%

1 2

R403 2.49K_0603_1%

1 2

0.1U_0402_16V4ZGIGA@

1

2

1 2

R301

0_0402_5%GIGA@

C378

0.1U_0402_16V4ZGIGA@

1

2

1

2

1

2

0.1U_0402_16V4ZGIGA@

1 2

0_0402_5%100@

1 2

0_0402_5%GIGA@

GND

NC NC

VCC

GIGA@

1

C441

C420

0.1U_0402_16V4ZGIGA@

2

+1.2V_LAN

C381

0.1U_0402_16V4Z

C425

0.1U_0402_16V4Z

C427

0.1U_0402_16V4Z

2

C383

1

+2.5V_LAN

5 6 7 8

AT93C46-10SU-2.7_SO8

R418 0_0805_5%GIGA@

1 2

GIGA@

0.1U_0402_16V4Z

+AVDDH

+1.2V_LAN

1

C379

2

+3V_LAN

1

2

25MHZ_16P_XSL025000FK1H

1

C442

27P_0402_50V8J

2

+3VS

1

C406

0.1U_0402_16V4Z

2

1

C428

0.1U_0402_16V4Z

2

1

C395

0.1U_0402_16V4Z

2

C439

GIGA@

1

3

0.1U_0402_16V4ZGIGA@

C410 0.1U_0402_16V4Z

+3V_LAN

Y3

LAN_X2LAN_X1

12

1

C443 27P_0402_50V8J

2

C398

C396

+3V_LAN

1

C440

0.1U_0402_16V4Z

2

AVDDL

+DVDD

1

C382

0.1U_0402_16V4Z

2

C444

1

0.1U_0402_16V4Z

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DIS CLOSE D TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C418

C408

1 2

+3V_LAN

1

C423

0.1U_0402_16V4Z

2

R422

1 2

R376

1 2

R303

1 2

R306

100@

+1.2V_LAN

2

C407

0.1U_0402_16V4ZGIGA@

1

2005/10/06 2006/10/06

3

0_0603_5%

GIGA@

0.01U_0402_16V7K

12

GIGA@

0.01U_0402_16V7K

12

GIGA@

0.01U_0402_16V7K

12

GIGA@

0.01U_0402_16V7K

12

1 2

+2.5V_LAN

12

R815

0.1U_0402_16V4Z

C401

0_0805_5%100@ 0_0805_5%GIGA@

0_0805_5%GIGA@

0_0805_5%

Compal Secret Data

TXD-/MDI0-

RXIN+/MDI1+

RXIN-/MDI1-

NC/MDI2+ NC/MDI2- MDO2-

NC/MDI3+ NC/MDI3-

TXD+/MDI0+ TXD-/MDI0-

RXIN+/MDI1+

RXIN-/MDI1-

+3V_LAN

+2.5V_LAN +1.2V_LAN

+2.5V_LAN

Deciphered Date

U23

12

TD4-

11

TD4+

10

TCT4

9

TD3-

8

TD3+

7

TCT3 TD2-6MX2-

5

TD2+

4

TCT2

3

TD1-

2

TD1+

1

TCT1

U22

TD-8TX-

7

TD+

6

CT

3

CT

2

RD-

1

RD+

NS0013_16P

100@

2

MX4MX4+ MCT4

MX3MX3+ MCT3

MX2+ MCT2

MX1MX1+ MCT1

0.5u_24HST1041A-2GIGA@

TX+

CT

RXRX+

ACTIVITY#

LINK_10_100#

13 14 15

16 17 18

19 20 21

22 23 24

9 10 11

14 15 16

1

Lan Conn.

12

C525 68P_0402_50V8K @

1 2

R327 300_0402_5% @

+3VALW

1 2

R328 300_0402_5% @

+3VALW

C526 68P_0402_50V8K @

RJ45_PR LANGND

MDO0+TXD+/MDI0+ MDO0-

MDO1+ MDO1MCT1

MDO2+

MDO3+ MDO3-

MDO0+ MDO0MCT0

MCT1 MDO1+ MDO1-

10mil

MDO3MDO3+ MDO1MDO2MDO2+ MDO1+ MDO0MDO0+

10mil

12

75_0402_5%GIGA@

RXIN+/MDI1+

10

12 11

C399

1 2

1000P_1206_2KV7K

75_0402_5%

49.9_0402_1%GIGA@

NC/MDI3+ NC/MDI3-

49.9_0402_1%GIGA@

NC/MDI2+ NC/MDI2-

49.9_0402_1%GIGA@

49.9_0402_1%

TXD+/MDI0+

TXD-/MDI0-

49.9_0402_1%

RXIN-/MDI1-

49.9_0402_1%

JP41

Green LED-

9

Green LED+

1

PR4-

2

PR4+

3

PR2-

4

PR3-

5

PR3+

6

PR2+

7

PR1-

8

PR1+ Yellow LEDYellow LED+

FOX_JM74113-P2101-7F

ME@

0.1U_0402_16V4Z

1

C191

2

RJ45_PRMCT0

R348

12

R325

12

R320

12

R322

12

R324

12 12

R321

R333

12 12

R329

R380

12 12

R375

R369

12 12

R365

SHLD2 SHLD1

1

C192

4.7U_0805_10V4Z

2

C412

12

0.01U_0402_16V7KGIGA@

C415

12

0.01U_0402_16V7KGIGA@

C430

12

0.01U_0402_16V7K

C424

12

0.01U_0402_16V7K

near LAN controller

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, M/B LA-3281

401429

星期三七月

1

14 13

B

of

27 47, 12, 2006

A

B

C

D

E

Mini-Express Card(Slot 1-WLAN)

1 1

JP16

ICH_PCIE_WAKE#<21>

2 2

CLKREQ_MCARD#<15>

CLK_PCIE_MCARD#<15> CLK_PCIE_MCARD<15>

BT_AVTIVE WLAN_AVTIVE

PCIE_RXN2<21> PCIE_RXP2<21>

PCIE_TXN2<21> PCIE_TXP2<21>

R479 0_0402_5%@ R480 0_0402_5%@

12 12

CLK_PCIE_MCARD# CLK_PCIE_MCARD

1

3

5

7

9

11

13

15

17

19

21

23

25

27

29

31

33

35

37

39

41

43

45

47

49

51

53

GND1

FOX_AS0B226-S56N-7F

GND2

2

4

6

8

10

12

14

16

18

20

22

24

26

28

30

32

34

36

38

40

42

44

46

48

50

52

54

PLT_RST#

ICH_SMBCLK

ICH_SMBDATA

WIRELESS_LED#

+3VALW

RF_OFF# <33> PLT_RST# <7,19,23>

ICH_SMBCLK <15,21> ICH_SMBDATA <15,21>

WIRELESS_LED# <37>

1

C498

2

+3VS +1.5VS

1

C499

2

0.1U_0402_16V4Z

ICH_SDOUT_MDC<20> ICH_SYNC_MDC<20>

ICH_AC_SDIN1<20>

ICH_RST_MDC#<20>

KILL_MDC#<21>

R107

1 2

R496

DAP202U_SOT323

D23

2 3

AZ_SYNC AZ_SDIN3

33_0402_5%

12

0_0402_5%@

1

+3VALW

12

R495 10K_0402_1%

MDC CONN.

JP17

1

GND1

3

IAC_SDATA_OUT

5

GND2

7

IAC_SYNC

9

IAC_SDATA_IN

11

IAC_RESET#

Connector for MDC Rev1.5

IAC_BITCLK

GND13GND14GND15GND16GND17GND

RES0 RES1

GND3 GND4

18

2 4 6

3.3V

8 10 12

ACES_88018-124G

C495

1 2

1U_0805_25V4Z

+3VALW

12

10_0402_5%

@

1

C649 10P_0402_50V8J

@

2

ICH_BITCLK_MDC <20>

R861

+5VS

12

13

2

BTONLED

Q23

DTC124EK_SC59

HDL00@

R108 10K_0402_1%

3 3

RF_OFF#<33>

BTONLED<37>

4 4

A

BT MODULE CONN (HDL00@)

RF_OFF

Q9 DTC124EK_SC59

HDL00@

13

2

12

BT MODULE CONN

AO3413_SOT23

USB20_N1<21> USB20_P1<21>

R309 10K_0402_5%

B

+3VS

Q22

D

S

13

G

2

USB20_N1

USB20_P1 BTON_LED BT_AVTIVE WLAN_AVTIVE

RF_OFF#<33>

+3VS_BT

C164

12

0.1U_0402_16V4Z

JP38

1

2

3

4

5

6

7

8

9

GND1

10

GND2

MOLEX_53780-0870

ME@

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DIS CLOSE D TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

BTONLED<37>

2005/10/06 2006/10/06

C

+5VS

12

13

2

BTONLED

DTC124EK_SC59

Compal Secret Data

R801 10K_0402_1%

RF_OFF2

Q708

BT MODULE CONN 2 (HDL20@)

Q705 DTC124EK_SC59

13

Deciphered Date

2

12

R810 10K_0402_5%

D

+3VS

AO3413_SOT23

USB20_N7<21> USB20_P7<21>

Q706

S

BTON_LED2 BT_AVTIVE WLAN_AVTIVE

+3VS_BT2

D

13

G

2

USB20_N7 USB20_P7

Title

Size Document Number Rev

Custom

Date: Sheet

C600

12

0.1U_0402_16V4Z

JP51

1

2

3

4

5

6

7

8

9

GND1

10

GND2

MOLEX_53780-0870

ME@

Compal Electronics, Inc.

SCHEMATIC, M/B LA-3281

401429

星期三七月

28 47, 12, 2006

E

of

B

A

+VDDA

12

R153 10K_0402_1%

C255

12

2

B

12

1U_0603_10V4Z

R159 10K_0402_1%

1 2

1

C

Q12 2SC2411K_SC59

E

3

D4

RB751V_SOD323

2 1

R158 20K_0402_5%

C477

C472

C263

1

2

1

2

1U_0603_10V4Z

BEEP#<33>

1 1

0.1U_0402_10V6K@

PCM_SPK#<24>

0.1U_0402_10V6K@

SB_SPKR<21>

12

1 2

1U_0603_10V4Z

C253

1 2

12

1U_0603_10V4Z

C254

1 2

12

10K_0402_5%@

R168

560_0402_5%

R160

560_0402_5%

R161

560_0402_5%

R171

B

C487 1U_0603_10V4Z

MONO_IN1 MONO_IN

12

R167

1 2

10K_0402_5%

C

C490

10U_0805_10V4Z

+5VS +5VAMP

L22

1 2

KC FBM-L11-201209-221LMAT_0805

L21

1 2

KC FBM-L11-201209-221LMAT_0805

1

2

60mil

1

2

C482 10U_1206_16V4Z

D

U33

4

VIN

2

SENSE or ADJ

DELAY ERROR7CNOISE

8

SD

SI9182DH-AD_MSOP8

28.7K for Module Design (VDDA = 4.702)

AC97 Codec

VOUT

GND

5 6 1 3

1

C476

2

0.1U_0402_16V4Z

40mil

(output = 250 mA)

R449 150K_0603_1%

1 2 12

R450 51K_0603_1%

1

C478 10U_0805_10V4Z

2

E

+VDDA

4.85V

+VDDC

9

DVDD11DVDD2

NC NC

VREF

JDREF

NC

AVSS1 AVSS2

1

@

C627

0.1U_0402_16V4Z

2

35 36 39 41 45 46 43 44

6

8 37 29 31 28 32 30 27 40 33 26

42

20mil

1

C605

2

0.1U_0402_16V4Z

HD_LINE_OUTL

SDATA_IN

10mil 10mil 10mil

C623 10U_0805_10V4Z

1 2

R832 47_0402_5%

1 2

VC@

GNDA

1000P_0402_50V7K

D

1

C606

2

0.1U_0402_16V4Z

C611 4.7U_0805_10V4Z C612 4.7U_0805_10V4Z

HD_LINE_OUTL HD_LINE_OUTR

R826 33_0402_5%

1 2

+MIC1_VREFO_L +AUD_VREF +MIC2_VREFO

2

C625

1

VC@

C628

@

1U_0603_10V4Z

C607 10U_0805_10V4Z

L23

CD_AGND

CD_AGND<23>

2 2

R831

VD@

R834

VD@

3 3

R817

20K_0402_5%

R832

VD@

12

CD_GNA

12

R818 20K_0402_5%

GNDA

INT_CD_L<23>

INT_CD_R<23>

JACK_PLUG_MIC<37>

GNDA

+VDDA

HP_L<30>

HP_R<30>

R821 20K_0402_5% R822 20K_0402_5% R823 20K_0402_5% R824 20K_0402_5%

JACK_PLUG<37>

1 2

FBM-L10-160808-301-T_0603

INT_MIC<30,37>

12 12 12 12

CD_R_L

CD_R_R

CD_GNA

MIC<30>

ICH_RST_AUDIO#<20> ICH_SYNC_AUDIO<20> ICH_SDOUT_AUDIO<20>

R830 20K_0402_1%

1 2

R833 39.2K_0402_1%

1 2

10U_0805_10V4Z

C617 1U_0402_6.3V4Z C618 1U_0402_6.3V4Z C620 1U_0603_10V4Z

MIC

EMI request add one pcs 0216

1 2

R835 0_0603_5%

1 2

R836 0_0603_5%

4 4

1 2

R837 0_0603_5%

1 2

R838 0_0603_5%

0.1U_0402_16V4Z

1

C608

1 2 1 2 1 2

C621 1U_0603_10V4Z C622 1U_0603_10V4Z

EAPD<30,33>

C609

2

GNDA

12

C6131U_0603_10V4Z

12

C6141U_0603_10V4Z

1 2 1 2

R827 0_0402_5%

1 2

EAPD

R829 0_0402_5%@

1 2

R868 0_0402_5%@

1 2

C6241000P_0402_50V7K

1 2

VC@

1 2

R862 0_0603_5%

1

C610

0.1U_0402_16V4Z

2

CD_RC_L CD_RC_R CD_GNDA C_MIC

1 2

VC@

40mil

MONO_IN

R83147_0402_5%

Security Classification

GND GNDA

A

B

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DIS CLOSE D TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

+AVDD_AC97

38

U39

AVDD125AVDD2

14

LINE2_L

15

LINE2_R

16

MIC2_L

17

MIC2_R

23

LINE1_L

24

LINE1_R

18

CD_L

20

CD_R

19

CD_GND

21

MIC1_L

22

MIC1_R

12

PCBEEP

11

RESET#

10

SYNC

5

SDATA_OUT

2

GPIO0

3

GPIO1

13

SENSE A

34

SENSE B

47

EAPD

48

SPDIFO

4

DVSS1

7

DVSS2

@

1U_0603_10V4Z

2005/10/06 2006/10/06

FRONT_OUT_R

SIDESURR_OUT_L

SIDESURR_OUT_R

MIC1_VREFO_L MIC1_VREFO_R

ALC861-VD-GR_LQFP48

1

C626

2

Compal Secret Data

FRONT_OUT_L

SURR_OUT_L SURR_OUT_R

CEN_OUT LFE_OUT

BIT_CLK

SDATA_IN

LINE2_VREFO

MIC2_VREFO

GNDA

Deciphered Date

R816

1 2

FBM-L10-160808-301-T_0603

1 2 1 2

1 2

C615 1000P_0402_50V7K@

1 2

C616 1000P_0402_50V7K @

1 2

R863 33_0402_5%

12

R834

4.99K_0402_1%

VC@

10mil

1

2

1

2

GNDA

Title

Size Document Number Rev

Custom

Date: Sheet

+3VS

LINE_OUTL LINE_OUTRHD_LINE_OUTR

C619 22P_0402_50V8J

1 2

ICH_BITCLK_AUDIO

SDATA_IN

C629

@

0.1U_0402_16V4Z

GNDA

ICH_AC_SDIN0

10K_0402_5%

1U_0603_10V4Z

LINE_OUTL <30> LINE_OUTR <30>

R828

+MIC1_VREFO_L+MIC2_VREFO +AUD_VREF

1

C630

@

2

ICH_BITCLK_AUDIO <20>

ICH_AC_SDIN0 <20>

GNDA

Compal Electronics, Inc.

SCHEMATIC, M/B LA-3281

401429

星期三七月

E

1

@

C631

0.1U_0402_16V4Z

2

of

29 47, 12, 2006

B

A

B

C

D

E

Boot ACPI Driver Entry

SPKL-OSPKLSPKR-O SPKL+O SPKR+O

L28

1 2

EAPD

EC_Mute

+MIC1_VREFO_L

R849

3K_0402_5%

FBM-11-160808-601-T_0603

C638

47P_0402_50V8J

1 2

R864 0_0402_5%@

Q709 DTC124EK_SC59

@

+5VAMP

0.1U_0402_16V4Z

1

C632

2

VOL_AMP VOLMAX BTL# LIN RIN

1

C637

4.7U_0805_10V4Z

2

W=40mil

1

C633

4.7U_0805_10V4Z

2

10 15

7 8

13

6 3

4

MUTE_AMP

MUTE

10K_0402_5%

U40

VDD

MUTE

SHUTDOWN#

VDD

LOUT-

VOLUME

ROUT-

VOLMAX

LOUT+

SE/BTL#

ROUT+ LINRIN-

BYPASS

APA2068KAI-TRL_SOP16

GND GND

+3VS

R840

@

1 2

MUTE_AMP

1

AMP_OFF# MUTE#

2 9

SPKR-

16

SPKL+

11

SPKR+

14

5 12

R841 10K_0402_5%

1 2

R843 0_0402_5%

1 2

L24 0_0603_5%

1 2

L25 0_0603_5%

1 2

L26 0_0603_5%

1 2

L27 0_0603_5%

1 2

MIC<29> EXT_MIC <37> INT_MIC <29,37>

+5VAMP

12

R839

LINE_OUTL<29>

LINE_OUTR<29>

10K_0402_5%

@

12

R842 0_0402_5%

EC_MUTE#<33>

VOLMAX

LINE_OUTL LINE_OUTR

EAPD<29,33>

1 2

C635 0_0603_5%

1 2

C636 0_0603_5%

R850

1 2 1 2

0_0402_5% 0_0402_5%@

R851

VOL_AMP<33>

LEFT_2

R845 10K_0402_5%

RIGHT_2

R846 10K_0402_5%

MUTE#

2

1 2

R844 0_0402_5%

1 2 1 2

+3VS

12

R847 10K_0402_5%

@

13

1 1

2 2

EC_Mute Sequence

3Sec

SPKL+O SPKL-O SPKR+O SPKR-O

1

C163

47P_0402_50V8J@

12

1

2

47P_0402_50V8J@

2

1

2

C162

47P_0402_50V8J@

1

C168

2

+MIC2_VREFO

12

R848 3K_0402_5%

1

C639 47P_0402_50V8J

2

GNDAGNDA

S3

HDL00/10

HDL20EC_Mute#

JP20

1 2 3 4

1

C167 47P_0402_50V8J@

2

ACES_85204-0400

ME@

INT MICEXT MIC

3 3

+3VS

12

R855

0_0402_5%

MUTE#

R858

1 2

HP_R<29> HP_L<29>

4 4

A

@

0_0402_5%

HP_INR

1 2

C645 1U_0603_10V4Z

HP_INL

1 2

C646 1U_0603_10V4Z

1

C647 1U_0603_10V4Z

2

14 18

15 13

1 3

+3VS

Reserve the 0 ohm resistor.

12

for voltage filtering

R853

0_0603_5%

U41

SHDNR# SHDNL#

INR INL

C1P C1N

C641 1U_0603_10V4Z

10

19

SVDD

PVDD

PGND

PVss

SVss

2

5

7

1

C648 1U_0603_10V4Z

2

1 2

OUTR

OUTL

NC-4 NC-6

NC-8 NC-12 NC-16 NC-20

SGND

MAX4411ETP+T_TQFN20~N

17

B

C640

HP_R

HP_L

HP_OUTR

11

HP_OUTL

9

4 6 8 12 16 20

+

1 2

@

330U_V_6.3VM_R25 C642

+

1 2

@

330U_V_6.3VM_R25

HP_OUTR

HP_OUTL

JACK_PLUG HP_OUTR

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DIS CLOSE D TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

R852 47_0402_5%

1 2

R854 47_0402_5%

1 2

1K_0402_5%

2005/10/06 2006/10/06

Compal Secret Data

HP_CL+

HP_CR+

12

R856

Deciphered Date

1 2

L29 FBMA-L11-160808-121LMT_0603

1 2

L30 FBMA-L11-160808-121LMT_0603

12

R857

1K_0402_5%

MUTE

D

47P_0402_50V8J

1

C643

2

1 2

R859 1K_0402_5%@

1 2

R860 1K_0402_5%@

PL

PR

1

C644 47P_0402_50V8J

2

Title

Size Document Number Rev

Custom

Date: Sheet

1

C

Q710

2

B

2SC2411K_SC59

E

@

3

1

C

Q711

2

B

2SC2411K_SC59

E

@

3

Compal Electronics, Inc.

SCHEMATIC, M/B LA-3281

401429

星期三七月

E

PL <37>

JACK_PLUG <29,37>

PR <37>

of

30 47, 12, 2006

B

HEADPHONE

C411 0.1U_0402_16V4Z

USB_ON#<33,37>

12

+5VALW

USB_ON#

1

2

C322 10P_0402_50V8J

@

+USB_VCCA

1

C160

C534

2

0.1U_0402_16V4Z JP21

1 2 3 4

5 6 7 8

SUYIN_020173MR004G565ZR

ME@

VCC DD+ GND

GND1 GND2 GND3 GND4

1

C535

0.1U_0402_16V4Z

2

USB Port

1000P_0402_50V7K

1

+

C161

150U_D_6.3VM

2

10P_0402_50V8J@

C174

C321

2

0.1U_0402_16V4Z

1

2

OUT OUT OUT

G528_SO8

+USB_VCCA

FLG

8 7 6 5

1

C417

1000P_0402_50V7K@

2

USB_OC#0 <21>

USB20_N0<21> USB20_P0<21>

PSOT24C_SOT23@

D14

For EMI

3

1

U25

1

GND

2

IN

3

IN

4

EN#

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DIS CLOSE D T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2005/10/06 2006/10/06

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, M/B LA-3281

401429

星期三七月

31 47, 12, 2006

of

B

5

D D

C C

B B

INT_KBD CONN.( TYPE "D" KB)

KSI[0..7]

KSO[0..16]

KSI1 KSI7 KSI6 KSO9 KSI4 KSI5 KSO0 KSI2 KSI3 KSO5 KSO1 KSI0 KSO2 KSO4 KSO7 KSO8 KSO6

KSO3 KSO12 KSO13 KSO14 KSO11 KSO10 KSO15

KSI[0..7] <33>

KSO[0..16] <33>

JP26

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

ACES_85202-2405

KSI1 KSI7 KSI6 KSO9 KSI4 KSI5 KSO0 KSI2 KSI3 KSO5 KSO1 KSI0 KSO2 KSO4 KSO7 KSO8 KSO6

KSO3 KSO12 KSO13 KSO14 KSO11 KSO10 KSO15

C650 100P_0402_50V8J@

1 2

C651 100P_0402_50V8J@

1 2

C652 100P_0402_50V8J@

1 2

C653 100P_0402_50V8J@

1 2

C654 100P_0402_50V8J@

1 2

C655 100P_0402_50V8J@

1 2

C656 100P_0402_50V8J@

1 2

C657 100P_0402_50V8J@

1 2

C658 100P_0402_50V8J@

1 2

C659 100P_0402_50V8J@

1 2

C660 100P_0402_50V8J@

1 2

C661 100P_0402_50V8J@

1 2

C662 100P_0402_50V8J@

1 2

C663 100P_0402_50V8J@

1 2

C664 100P_0402_50V8J@

1 2

C665 100P_0402_50V8J@

1 2

C666 100P_0402_50V8J@

1 2

C667 100P_0402_50V8J@

1 2

C668 100P_0402_50V8J@

1 2

C669 100P_0402_50V8J@

1 2

C670 100P_0402_50V8J@

1 2

C671 100P_0402_50V8J@

1 2

C672 100P_0402_50V8J@

1 2

C673 100P_0402_50V8J@

1 2

4

ON/OFFBTN#<37>

3

1 2

ON/OFFBTN#

INSTANT_ON#<37>

@

SW3

5

6

SW1

5

6

EC_ON<33>

3 4

SMT1-05_4P

3 4

SMT1-05_4P

EC_ON

INSTANT_ON#

SW4

1 2

6

+3VALW

12

R113

4.7K_0402_5%

R804 33K_0402_5%

13

D

2

G

Q707

S

2N7002_SOT23

3 4

SMT1-05_4P@

5

1 2

100K_0402_5%

D2

1

DAN202U_SC70

2

100K_0402_5%

D31

1

DAN202U_SC70@

2

Power BTN

+3VALW

12

R118

2 3

Q10 DTC124EK_SC59

13

+3VALW

12

R805

@

2 3

ON/OFF

51ON#

INST_ON# 51ON#

1

2

C205

1000P_0402_50V7K

INST_ON# <33>

ON/OFF# <33> 51ON# <39>

12

D1 RLZ20A_LL34

1

JP33

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

+5VS

LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3 LPC_FRAME# LPC_DRQ#0 PCI_RST#

SIRQ

5

+3VS

CLK_14M_SIO <15>

LPC_FRAME# <20,33> LPC_DRQ#0 <20>

PCI_RST# <19,21,24,25,26,27,33> CLK_PCI_DB <15>

SIRQ <21,24,26,33>

LPC_AD[0..3]

FOR LPC SIO DEBUG PORT

LPC_AD[0..3] <20,33>

R391

10K_0402_5%

12

4

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16 17 18 19 20

A A

ACES_85201-2005

JP43

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

ACES_85201-2005

PCI_CBE#0 PCI_AD6 PCI_AD4 PCI_AD2 PCI_AD0 PCI_AD1 PCI_AD3 PCI_AD5 PCI_AD7 PCI_AD8 PCI_CBE#1 PCI_CBE#2 PCI_CBE#3

PCI_AD9

PCI_CBE#0 <19,24,26,27> PCI_AD6 <19,24,26,27> PCI_AD4 <19,24,26,27> PCI_AD2 <19,24,26,27> PCI_AD0 <19,24,26,27> PCI_AD1 <19,24,26,27> PCI_AD3 <19,24,26,27> PCI_AD5 <19,24,26,27> PCI_AD7 <19,24,26,27> PCI_AD8 <19,24,26,27> PCI_CBE#1 <19,24,26,27> PCI_CBE#2 <19,24,26,27> PCI_CBE#3 <19,24,26,27>

CLK_PCI_DB <15>

+5VS

PCI_RST# <19,21,24,25,26,27,33> PCI_FRAME# <19,24,26,27> PCI_TRDY# <19,24,26,27> PCI_AD9 <19,24,26,27>

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DIS CLOSE D TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

FOR PORT 80 DEBUG PORT EC DEBUG PORT

2005/10/06 2006/10/06

Compal Secret Data

Deciphered Date

2

JP22

+5VALW EC_TX<33> EC_RX<33>

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, M/B LA-3281

401429

星期三七月

1

2

3

4

ACES_85205-0400

ME@

1

P80_DATA P80_CLK

of

32 47, 12, 2006

B

5

L6

+3VALW +EC_AVCC

D D

CLK_PCI_LPC<15>

C C

B B

A A

CB_PME#<24> R5_PME#<26> LAN_PME#<27> PCI_PME#<19>

1 2

FBM-11-160808-601-T_0603

0.1U_0402_16V4Z

1 2

L7 FBM-11-160808-601-T_0603

12

R143 10_0402_5%@

C232

22P_0402_50V8J@

1 2

R131 0_0402_5%@

1 2

R141 0_0402_5%@

1 2

R138 0_0402_5%

1 2

R127 0_0402_5%

+3VS

RP13

1 8 2 7 3 6 4 5

+3VALW

+5VALW

+3VS

10K_1206_8P4R_5%

RP14

1 8 2 7 3 6 4 5

100K_1206_8P4R_5%

1 2

R130 4.7K_0402_5%

1 2

R133 4.7K_0402_5%

1 2

R135 4.7K_0402_5%

1 2

R139 4.7K_0402_5%

SYSON#<35>

5

2

C211

1

12

AMP_MUTE# VOL_UP# VOL_DOWN# MEDIA#

FRD# FSEL#

EC_SMB_CK1 EC_SMB_DA1

EC_SMB_CK2 EC_SMB_DA2

100P_0402_50V8J@

+3VALW

1

C212 1000P_0402_50V7K

2

ECAGND

1 2

+3VALW

R112 47K_0402_5%

0.1U_0402_16V4Z

+3VALW

R134 10K_0402_5%

1 2

EC_PME#

KSO[0..15]<32>

KSI[0..7]<32>

1

C226

1 2

R869 10K_0402_5%

C223

100P_0402_50V8J@

2

INST_ON#<32>

SYSON# USB_ON#

EC_GPIO4A

1 2

R866 0_0402_5%@

1 2

R867 0_0402_5%

C200

C231

0.1U_0402_16V4Z

2

1

R401 0_0402_5%@

C447

0.1U_0402_16V4Z

1

2

GATEA20<20>

LPC_FRAME#<20,32>

PCI_RST#<19,21,24,25,26,27,32>

EC_SCI#<21>

PCI_CLKRUN#<21,24,26,27>

KSO[0..15] KSI[0..7]

EC_SMB_DA2<4> EC_SMB_CK2<4>

EC_SMB_DA1<34,40> EC_SMB_CK1<34,40>

EC_TX<32>

EC_RX<32> PWR_LED#<37> NUM_LED#<37>

CHARGE_LED0#<37> CHARGE_LED1#<37>

CAPS_LED#<37>

SUSP_LED#<37>

SYSON<35,43>

EC_RSMRST#<21> BKOFF#<16>

SLP_S3#<21>

EC_LID_OUT#<21>

PM_SLP_S5#<21>

EC_SMI#<21>

1 2

LID_SWITCH#<36>

SUSP#<18,24,26,34,35,43,44>

PBTN_OUT#<21>

4

1

2

KB_RST#<20>

SIRQ<21,24,26,32>

LPC_AD3<20,32> LPC_AD2<20,32> LPC_AD1<20,32> LPC_AD0<20,32>

4

EC_GPIO4A

C248

0.1U_0402_16V4Z

1

2

R336

1 2

0_0402_5%@

KSI0 KSI1 KSI2 KSI3 KSI4 KSI5 KSI6 KSI7

KSO0 KSO1 KSO2 KSO3 KSO4 KSO5 KSO6 KSO7 KSO8 KSO9 KSO10 KSO11 KSO12 KSO13 KSO14 KSO15 KSO16 EC_GPIO4A

EC_SMB_DA2 EC_SMB_CK2 EC_SMB_DA1 EC_SMB_CK1

CHARGE_LED0# CHARGE_LED1# CAPS_LED#

SYSON

BKOFF# EC_LID_OUT#

PM_SLP_S5# EC_SMI#

LID_SWITCH# SUSP#

PBTN_OUT#

EC_PME#

CRY1 CRY2

USB_ON# <31,37>

C220

0.1U_0402_16V4Z

1

2

LPC_AD3 LPC_AD2 LPC_AD1 LPC_AD0

EC_RST# EC_SCI#

EC_TX EC_RX

SUSP_LED#

+3VALW

C201

1000P_0402_50V7K

C237

1000P_0402_50V7K

1

2

U6

1

GA20/ GPIO00/GA20

2

KBRST#/GPIO01/KBRST#

3

SERIRQ

5

LPC_FRAME# / LFRAME#

6

LPC AD3/LAD3

9

LPC AD2/LAD2

10

LPC AD1/LAD1

12

LPC AD0/LAD0

14

CLK_PCI_EC/PCICLK

15

PCIRST#

42

EC RST#/ ECRST#

24

EC SCI#/SCI#/GPIO0E

44

PM_CLKRUN#/ CLKRUN#

63

KSI0/GPIO30

64

KSI1/GPIO31

65

KSI2/GPI032

66

KSI3/GPIO33

67

KSI4/GPIO34

68

KSI5/GPI035

69

KSI6/GPIO36

70

KSI7/GPIO37

47

KSO0/GPIO20

48

KSO1/GPIO21

49

KSO2/GPIO22

50

KSO3/GPIO23

51

KSO4/GPIO24

52

KSO5/GPIO25

53

KSO6/GPIO26

54

KSO7/GPIO27

55

KSO8/GPIO28

56

KSO9/GPIO29

57

KSO10/GPIO2A

58

KSO11/GPIO2B

59

KSO12/GPIO2C

60

KSO13/GPIO2D

61

KSO14/GPIO2E

62

KSO15/GPIO2F

89

EC URXD/KSO16/GPIO48

90

EC UTXD/KSO17/GPIO49

88

EC SMD2/ GPIO47/SDA2

87

EC SMC2/GPIO46/SCL2

86

EC SMD1/GPIO44/SDA1

85

EC SMC1/GPIO44/SCL1

34

PCM_SPK#/EMAIL_LED#/ GPIO16

35

SB_SPKR/PWR_SUSP_LED#/ GPIO17

38

PWRLED#/ GPIO19

40

NUMLED#/ GPIO1A

99

BATT CHGI LED#/ E51CS#

101

BATT LOW LED#/ E51MR0

100

CAPS LED#/ E51TMR1

102

ARROW LED#/ E51 INT0

104

SYSON/GPIO56/ E51 INT1

4

EC_RSMRST#/ GPIO02

7

BKOFF#/GPIO03

8

PM SLP S3#/GPIO04

16

EC LID OUT#/GPIO06

17

PM SLP S05#/ GPIO07

18

EC SMI#/GPIO08

19

EC SWI#/GPIO09

20

LID SW#/ GPIO0A

21

SUSP#/GPIO0B

22

PBTN_OUT#/GPIO0C

23

EC PME#/GPIO0D

140

XCLKO

138

XCLKI

3

+EC_AVCC

26

105

11

VCC/ EC VCC

Host

INTERFACE

key Matrix

scan

GND

139

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

75

127

141

BATTEMP/AD0/GPIO38

VCC

BATT OVP/AD1/GPIO39

VCC / EC VCC

VCC / EC VCC37VCC / EC VCC

EC_AVCC / AVCC

DAC_BRIG/DA0/GPIO3D

PWR

EN DFAN1/DA1/GPIO3D

EN DFAN2/DA3/ GPIO3F

FAN/PWM

INVT_PWM/GPIO0F/PWM1

BEEP#/GPIO10/PWM2

OUT BEEP/GPIO12/PWM3

ACOFF/GPIO18/PWM4 FAN SPEED1/GPIO14/FANFB1 FAN SPEED2/GPIO15/FANFB2

PS2 interface

Data BUS

Address

BUS

SM BUS

GND13GND28GND39GND

GND

77

103

129

ECAGND

3

BATT_TEMP

71

BATT_OVP

72

ADP_ID

IREF2/DA2

PSCLK1 PSDAT1 PSCLK2 PSDAT2 PSCLK3 PSDAT3

ADB0/D0 ADB1/D1 ADB2/D2

ADB3/ D3

ADB4/D4 ADB5/D5 ADB6/D6 ADB7/D7 KBA0/A0 KBA1/A1 KBA2/A2 KBA3/A3 KBA4/A4 KBA5/A5 KBA6/A6 KBA7/A7 KBA8/A8

KBA9/A9 KBA10/A10 KBA11/A11 KBA12/A12 KBA13/A13 KBA14/A14 KBA15/A15 KBA16/A16 KBA17/A17 KBA18/A18 KBA19/A19

FRD#/RD#

FWR#/WR#

KB910L_LQFP144

73

SKU_ID

74

DAC_BRIG

76

EN_FAN1

78

IREF

79

1 2

80

R486 0_0402_5%

INVT_PWM

25

BEEP#

27

AMP_MUTE#

30

ACOFF

31

FAN_SPEED1

32

MB_ID

33

EC_P80_CLK

91

EC_P80_DATA

92 93 94

TP_CLK

95

TP_DATA

96

ADB0

125

ADB1

126

ADB2

128

ADB3

130

ADB4

131

ADB5

132

ADB6

133

ADB7

134

KBA0

111

KBA1

112

KBA2

113

KBA3

114

KBA4

115

KBA5

116

KBA6

117

KBA7

118

KBA8

119

KBA9

120

KBA10

121

KBA11

122

KBA12

123

KBA13

124

KBA14

110

KBA15

109

KBA16

108

KBA17

107

KBA18

106

KBA19

98 84

MEDIA#

97

FRD#

135

FWR#

136

FSEL#

144

EC_ON

41 43

EC_THERM#

29 36

ICH_POK

45 46

81

FSTCHG

82

VR_ON

83

VOL_UP#

137

VOL_DOWN#

142

KILL_SW#

143

Compal Secret Data

Deciphered Date

ADP_I/AD2/GPIO3A

AD BID0/AD3/GPIO3B

AD INtput or GPI

DA output or GPO

SELIO2#/ GPIO43

SELIO#/ GPIO50

FSEL#/SELMEM#

EC ON/ GPIO1B

AC IN/ GPIO1C

ECTHERM#/GPIO11

ONOFF/GPIO18

PCMRST#/GPIO1E

WL OFF#/GPIO1F

ALI/MH#/GPIO40

FSTCHG/GPIO41

VR ON/ GPIO42 GPIO57/GPIO57 GPIO58/GPIO58 GPIO59/GPIO59

AGND

2005/10/06 2006/10/06

BATT_OVP <41>

ADP_ID <39>

DAC_BRIG <16> EN_FAN1 <4> IREF <41>

INVT_PWM <16> BEEP# <29>

AMP_MUTE# <37> ACOFF <39,41> FAN_SPEED1 <4>

EC_P80_CLK <13,14> EC_P80_DATA <13,14>

EAPD <29,30>

TP_CLK <37>

ENBKL <16> MEDIA# <37> FRD# <34> FWR# <34>

FSEL# <34>

EC_ON <32> ACIN <21,39> EC_THERM# <21> ON/OFF# <32> ICH_POK <7,21>

RF_OFF# <28>

EC_MUTE# <30> FSTCHG <41> VR_ON <45> VOL_UP# <37> VOL_DOWN# <37> KILL_SW# <36,37>

2

12

C202 0.01U_0402_16V7K

VOL_AMP <30>

TP_DATA <37>

KBA[0..19]<34>

ADB[0..7]<34>

2

ECAGND

BATT_TEMP <40>

KBA[0..19] ADB[0..7]

1

Analog Board ID definition, Please see page 3.

100K_0402_1%

1

56K_0402_5%

2

100K_0402_1%

0_0402_5%

+3VALW

OUT

NC3NC

33 47

R119

R115

R125

15W@

R126

14W@

+5VS

1

C249

2

+3VALW

1 2

+3VALW

1 2

+3VS

10P_0402_50V8J

of

+3VALW

R492

100K_0402_1%

@

ADP_ID SKU_ID

1

C524

0.1U_0402_16V4Z

Title

Size Document Number Rev

Custom

Date: Sheet

2

@

Compal Electronics, Inc.

SCHEMATIC, M/B LA-3281

401429

,

星期三

12, 2006

七月

1 2

C208

R493

0_0402_5%

@

1 2

0.1U_0402_16V4Z

MB_ID

EC_P80_CLK EC_P80_DATA EC_MUTE#

C250

1 2

R402 4.7K_0402_5%@

1 2

R411 4.7K_0402_5%@

1 2

R128 10K_0402_5%@

TP_CLK

1 2

4.7K_0402_5%

R142

TP_DATA

1 2

4.7K_0402_5%

R146

KBA1

1 2

R147 1K_0402_5% @

KBA4

1 2

R148 1K_0402_5%@

KBA5

1 2

R149 1K_0402_5%@

CRY1 CRY2

R150

1 2

20M_0603_5%@

1

4

IN

2

10P_0402_50V8J

2

X1 32.768KHZ_12.5P_1TJS125BJ2A251

1

Ra

Rb

Ra

Rb

B

GND

+5VALW

12

R116 100K_0402_1%

1

A0

2

A1

3

A2

4

12

R117 100K_0402_1%

R337 100K_0402_5%@

1 2

FSEL# <33>

FWE#

C501

1 2

0.1U_0402_16V4Z

4

+3VALW

O

U32

5

TC7SH32FU_SSOP5

2

P

I0

1

I1

G

3

+3VALW

12

R442 100K_0402_1%

2

G

1 3

D

Q30 2N7002_SOT23

+5VALW

EC_SMB_CK1<33,40> EC_SMB_DA1<33,40>

SUSP# <18,24,26,33,35,43,44>

S

EC_FLASH# <21>

FWR# <33>

INT_FSEL#

R339

1 2

22_0402_5%@

C199

0.1U_0402_16V4Z

1 2

U4

8

VCC

7

WP

6

SCL

5

SDA

AT24C16AN-10SU-2.7_SO8~N

+3VALW

U26

5

TC7SH32FU_SSOP5

@

2

P

I0

4

O

1

I1

G

3

1 2

R338 0_0402_5%

INT_FLASH_EN# FSEL#

Reserve R177, if U12A is single gate.

KBA[0..19]<33>

ADB[0..7]<33>

KBA[0..19] ADB[0..7]

1MB Flash ROM

1 2

+3VALW

1

C416

0.1U_0402_16V4Z

2

+3VALW

KBA0 KBA1 KBA2 KBA3 KBA4 KBA5 KBA6 KBA7 KBA8 KBA9 KBA10 KBA11 KBA12 KBA13 KBA14 KBA15 KBA16 KBA17 KBA18 KBA19

INT_FSEL#

FRD#<33>

FRD# FWE#

U30

21

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19

CE# OE# WE#

VCC0 VCC1

RP#

READY/BUSY#

NC0 NC1

GND0 GND1

D0 D1 D2 D3 D4 D5 D6 D7

NC

20 19 18 17 16 15 14

8 7

36

6 5 4 3 2

1 40 13 37

22 24

9

SST39VF080-70-4C-EIE_TSOP40~N

31 30

ADB0

25

ADB1

26

ADB2

27

ADB3

28

ADB4

32

ADB5

33

ADB6

34

ADB7

35

RESET#

10 11 12 29 38

23 39

R443 100K_0402_1%

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DIS CLOSE D T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2005/10/06 2006/10/06

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, M/B LA-3281

401429

星期三七月

34 47, 12, 2006

of

B

A

1 1

2 2

B

C

D

SUSP

Q26

2N7002_SOT23

2

G

+VSB

12

R384 22K_0402_5%

13

D

S

E

C435

10U_0805_10V4Z

+5VALW to +5VS Transfer

+5VALW +5VS

U27

1

2

RUNON

1

C434

0.1U_0603_25V7K

2

8 7 6 5

S

D

S

D

S

D

G

D

SI4800DY_SO8

1 2 3 4

F

1

C426 10U_0805_10V4Z

2

0.1U_0402_16V4Z

1

C419

2

G

H

I

+5VALW

12

R92 47K_0402_5%

SYSON#<33>

SYSON<33,43>

SUSP<44>

SUSP#<18,24,26,33,34,43,44>

SYSON#

2

G

SUSP

2

G

+5VALW

13

D

S

12

13

D

S

Q6 2N7002_SOT23

R334 10K_0402_5%

Q24 2N7002_SOT23

J

3 3

+3VALW to +3VS Transfer

+3VALW

U7

8

S

D

7

+VSB

2

G

10U_0805_10V4Z

12

R136 33K_0402_5%

13

D

S

4 4

SUSP

Q11

2N7002_SOT23

C236

1

2

1

C224

0.1U_0603_25V7K

2

D

6

D

5

D

SI4800DY_SO8

S S G

5 5

+3VS

1

C229 10U_0805_10V4Z

2

1 2

0.1U_0402_16V4Z

1

C225

2

RUNON

0_0402_5%@

12

R335 470_0402_5%

13

D

S

SUSP

2

G

Q25 2N7002_SOT23

+1.8VS

12

13

D

S

R58 470_0402_5%

SUSP

2

G

Q3 2N7002_SOT23

+0.9VS+5VS

12

13

D

S

R106 470_0402_5%

2

G

Q8 2N7002_SOT23

SUSP

1 2 3 4

R132

+1.8V to +1.8VS Transfer

+1.8V

U17

8 7

6 6

7 7

2N7002_SOT23

SUSP

2

G

Q20

VGA@

+VSB

1 2

13

D

S

10U_0805_10V4Z

R227 47K_0402_5%

VGA@

8 8

A

B

C

D

1

C313

VGA@

1

2

6 5

2

C312

0.1U_0603_25V7K

VGA@

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DIS CLOSE D TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

E

1

S

D

2

S

D

3

S

D

4

G

D

SI4800DY_SO8

VGA@

R129

2005/10/06 2006/10/06

F

+1.8VS

1

C131

VGA@

10U_0805_10V4Z

2

1 2

VGA@

0.1U_0402_16V4Z

1

C133

2

RUNON

0_0402_5%@

Compal Secret Data

Deciphered Date

G

12

R228 470_0402_5%

13

D

S

H

2

G

Q5 2N7002_SOT23

+3VS

12

R731 470_0402_5%

13

D

SUSP

2

G

Q704

S

2N7002_SOT23

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, M/B LA-3281

401429

星期三七月

06

I

+2.5VS+1.8V

12

13

D

S

R105 470_0402_5%

SUSPSYSON#

2

G

Q7 2N7002_SOT23

35 47, 12, 20

B

of

J

5

4

3

2

1

D D

VGA I/O PORT Connector

VGA_DDC_DAT<17> VGA_DDC_CLK<17>

JVGA_HS<17> JVGA_VS<17>

RED<17> GREEN<17> BLUE<17>

C C

VGA_DDC_DAT VGA_DDC_CLK JVGA_HS JVGA_VS

RED GREEN BLUE

JP6

112 334 556 778 9910

11

13

13 151516

17

19

ACES_87216-2012

ME@

2 4 6 8 10 12

12

14

16 18

18

20

CRMA LUMA COMP

+3VS +5VS

CRMA <17> LUMA <17> COMP <17>

USB20_N3<21> USB20_P3<21>

CMOS Camera Conn

1

2

C292

@

2

4.7U_0603_6.3V6M

USB20_N3 USB20_P3

1

R488 0_0603_5% R489 0_0603_5%

12 12

+5VS

C293

0.1U_0402_10V6K JP42

1

2

3

4

5

6

GND1

7

GND2

ACES_88266-05001

ME@

Finger Print board

For EMI

1

D21 PSOT24C_SOT23

LID Switch (HDL00@)

+3VALW

B B

1 2

R195 0_0402_5%

C286

0.1U_0402_16V4Z

2

VDD

1

OUTPUT

2

GND

U13

1

A3212ELHLT-T_SOT23W-3

R193 47K_0402_5%

1 2

3

1

2

+3VALW

D19

21

RB751V_SOD323

C287 10P_0402_25V8K

12

R481 100K_0402_5%

LID_SWITCH# <33>

USB20_P5<21> USB20_N5<21>

+3VS

4.7U_0603_6.3V6M

C315

@

USB20_P5 USB20_N5

2

1

2

1

C314

0.1U_0402_10V6K

2

3

@

JP37

4

3

2

1

ACES_85201-0405

Kill Switch

LID Switch 2 (HDL20@)

+3VALW

A A

5

1 2

R800 0_0402_5%

C601

0.1U_0402_16V4Z

2

VDD

1

OUTPUT

GND

2

U38

1

A3212ELHLT-T_SOT23W-3

R802 47K_0402_5%

1 2

3

1

2

4

+3VALW

D30

21

RB751V_SOD323

C602 10P_0402_25V8K

12

R803 100K_0402_5%

LID_SWITCH# <33>

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DIS CLOSE D TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/10/06 2006/10/06

Compal Secret Data

Deciphered Date

+3VS

1 2

KILL_SW#<33,37>

R188 10K_0402_5%@

KILL_SW#

2

SW2

3

2

1

1BS003-1211L_3P@

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

SCHEMATIC, M/B LA-3281

401429

星期三七月

36 47, 12, 2006

1

B

5

4

3

2

1

4 in 1 Card Reader

+VCC_4IN1_XD +VCC_4IN1

SDDATA0_MSDATA0<26> SDDATA1_MSDATA1<26> SDDATA2_MSDATA2<26> SDDATA3_MSDATA3<26>

D D

C C

XDD4<26> XDD5<26> XDD6<26> XDD7<26>

SDCMD_MSBS<26>

XDWP#<26> XDALE<26> XDCD#<26>

SDWP#_XDRB#<26>

XD_CE#<26> XDCLE<26>

SDDATA0_MSDATA0 SDDATA1_MSDATA1 SDDATA2_MSDATA2 SDDATA3_MSDATA3 XDD4 XDD5 XDD6 XDD7

SDCMD_MSBS XDWP# XDALE

SDWP#_XDRB# SDCLK_MSCLK XD_CE# XDCLE

3IN1_LED#<26>

INST ON & LED

INT_MIC<29,30>

WIRELESS_LED#<28> BTONLED<28> SUSP_LED#<33> CHARGE_LED0#<33> CHARGE_LED1#<33>

KILL_SW#<33,36>

B B

WIRELESS_LED#<28>

BTONLED<28>

SUSP_LED#

SUSP_LED#<33>

CHARGE_LED0#<33>

CHARGE_LED1#<33>

A A

+3VS

+3VALW

ACES_85202-1205

Front LEDs (HDL00@)

12

R190 200_0402_5%

12

R194 200_0402_5%

12

R191 200_0402_5%

1 2

R192 200_0402_5%

1 2

R189 200_0402_5%

CHARGE0

CHARGE1

JP12

41

XD-VCC

33

XD-D0

34

XD-D1

35

XD-D2

36

XD-D3

37

XD-D4

38

XD-D5

39

XD-D6

40

XD-D7

30

XD-WE

31

XD-WP

29

XD-ALE

23

XD-CD

25

XD-R/B

26

XD-RE

27

XD-CE

28

XD-CLE

32

XD-GND

24

XD-GND

18

N.C.

42

N.C.

45

SHIELD GND

46

SHIELD GND

TAITW_R012-210-LR

JP50

12 11 10 9 8 7 6 5 4 3 2 1

ME@

D6

HT-110UYG-CT_YEL/GRN

HT-210UD/UYG_AMB/GRN

21

D7

21

D8

21

HT-110UYG-CT_YEL/GRN

D5

2

3

4 IN 1 CONN

12

R476 200_0402_5%

+3VS

+3VALW

1

SD-VCC MS-VCC

SD_CLK SD-DAT0 SD-DAT1 SD-DAT2 SD-DAT3

SD-CMD

SD-CD-SW

SD-CD-COM

SD-WP-SW

SD-WP-COM

MS-SCLK MS-DATA0 MS-DATA1 MS-DATA2 MS-DATA3

MS-INS

MS-BS SD-GND SD-GND

MS-GND MS-GND

HT-110UYG-CT_YEL/GRN

15 9

16 19 20 11 12 13 21 22 43 44

8 4 3 5 7 6 2 14 17 1 10

D18

R461 22_0402_5%

1 2

SDDATA0_MSDATA0 SD_MSDATA1 SD_MSDATA2 SDDATA3_MSDATA3 SDCMD_MSBS SDCD#_XDCD0#

SDWP#_XDRB#

R460 22_0402_5%

MSCLK

1 2

SDDATA0_MSDATA0 SDDATA1_MSDATA1 SDDATA2_MSDATA2 SDDATA3_MSDATA3 MSCD#_XDCD1 SDCMD_MSBS

21

AMP_MUTE#<33> VOL_UP#<33>

VOL_DOWN#<33>

MEDIA#<33>

ON/OFFBTN#<32>

PWR_LED#<33>

INSTANT_ON#<32>

NUM_LED#<33> CAPS_LED#<33>

ODD_LED#<23> SATA_LED#<20>

T/P Board

ACES_85201-0605

SDCLK_MSCLKSDCLK

SDDATA0_MSDATA0 <26> SD_MSDATA1 <26> SD_MSDATA2 <26> SDDATA3_MSDATA3 <26> SDCMD_MSBS <26> SDCD#_XDCD0# <26>

SDWP#_XDRB# <26>

+3VS

SDCLK_MSCLKXDCD#

SDDATA0_MSDATA0 <26> SDDATA1_MSDATA1 <26> SDDATA2_MSDATA2 <26> SDDATA3_MSDATA3 <26> MSCD#_XDCD1 <26> SDCMD_MSBS <26>

SDCLK_MSCLK <26>

PWR ON/OFF SW & LED

+3VS+3VALW

JP29

1

2

3

4

5

6

7

8

9

10

11

12

13

14

ACES_85202-1405

ME@

U20

DRIVE_LED#

4

Y

TC7SH08FUF_SSOP5

TP_DATA <33> TP_CLK <33>

JP28

ODD_LED# SATA_LED#

1 2 3 4 5 6

ON/OFFBTN# DRIVE_LED#

+3VS

1

B

2

A

+5VS

5

P

G

3

PR JACK_PLUG PL

12

USB_ON#

12

USB_ON#

(60 MIL)

LVDSAC+

LVDSACLVDSA2+

LVDSA1+

LVDSA1-

LVDSA0+

LVDSA0-

+5VALW

INT_MIC

+LCDVDD +3VS

LVDSAC+<9> LVDSAC-<9>

LVDSA2+<9>

LVDSA2-<9>

LVDSA1+<9> LVDSA1-<9>

LVDSA0+<9> LVDSA0-<9>

C527

1 2

470P_0402_50V8J C528

1 2

470P_0402_50V8J C529

1 2

470P_0402_50V8J

C483 0.1U_0402_16V4Z

USB_ON#<31,33>

C276 0.1U_0402_16V4Z

USB_ON#<31,33>

UMA LCD/PANEL Conn.

JP5

2

112

4

334

6

556

8

778

10

9910

12

111112

14

131314

16

151516

18

171718

20

191920

22

212122

24

232324

26

252526

28

272728

30

292930

32

GND31GND

ME@

ACES_88107-30001

Audio Jack/USB Conn.

OUT OUT OUT

G528_SO8

OUT OUT OUT

G528_SO8

USB20_N2 USB20_P2

USB20_P4 USB20_N4

USB20_P6 USB20_N6

PR JACK_PLUG PL

JACK_PLUG_MIC EXT_MIC

1 2 1 2 1 2 1 2

1 2

WM-64PCY_2P

8 7 6 5

FLG

8 7 6 5

FLG

0.1U_0402_25V4K

MIC1

@

+USB_VCCB

+USB_VCCC

USB20_N2<21> USB20_P2<21>

USB20_P4<21> USB20_N4<21>

+USB_VCCC USB20_P6<21> USB20_N6<21>

PR<30>

JACK_PLUG<29>

PL<30>

+AUD_VREF

JACK_PLUG_MIC<29>

EXT_MIC<30>

U9

1

GND

2

IN

3

IN

4

EN#

U10

1

GND

2

IN

3

IN

4

EN#

C530 C531 C532 C533

1

C500

1000P_0402_50V7K@

2

1 2

R172 0_0402_5%

1

C273

1000P_0402_50V7K@

2

EDID_CLK_LCD EDID_DAT_LCD

LVDSBC+

LVDSBCLVDSB2+

LVDSB2-LVDSA2-

LVDSB1+

LVDSB1-

LVDSB0+

LVDSB0-

+USB_VCCB

JP27

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

ACES_87213-2000

ME@

USB_OC#2 <21> USB_OC#4 <21>

USB_OC#6 <21>

EDID_CLK_LCD <9> EDID_DAT_LCD <9>

LVDSBC+ <9>

LVDSBC- <9>

LVDSB2+ <9>

LVDSB2- <9>

LVDSB1+ <9>

LVDSB1- <9>

LVDSB0+ <9>

LVDSB0- <9>

SLPCHARGEBTWL MIC1KILL

5

4

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DIS CLOSE D TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/10/06 2006/10/06

Compal Secret Data

Deciphered Date

2

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, M/B LA-3281

401429

星期三七月

37 47, 12, 2006

1

of

B

A

B

C

D

E

F

G

H

I

J

1 1

2 2

3 3

4 4

5 5

6 6

7 7

1

CF6

CF7

FM3

H1 HOLEA

1

H11 HOLEA

1

H21 HOLEA

1

8 8

A

B

C

D

CF9

CF8

FM1

H2 HOLEA

1

H12 HOLEA

1

H22 HOLEA

1

CF11

CF13

FM4

H3 HOLEA

1

H13 HOLEA

1

H23 HOLEA

1

CF10

CF14

FM2

H4 HOLEA

1

H14 HOLEA

1

H24 HOLEA

1

CF2

H6 HOLEA

1

CF1

H7 HOLEA

1

H17 HOLEA

1

H25 HOLEA

1

CF12

H5 HOLEA

1

H15 HOLEA

1

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DIS CLOSE D TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

E

CF3

H9 HOLEA

1

H19 HOLEA

1

H27 HOLEA

1

CF5

H10 HOLEA

1

H20 HOLEA

1

H28 HOLEA

1

Compal Secret Data

Deciphered Date

G

CF4

1

H8 HOLEA

1

H18 HOLEA

1

H26 HOLEA

1

2005/10/06 2006/10/06

F

Title

Size Document Number Rev

Custom

H

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, M/B LA-3281

401429

星期三七月

06

I

38 47, 12, 20

B

of

J

A

PR213 10K_0402_1%@

+3VALWP

1 2

VIN

12

PR10

12

PR14

PC5

0.047U_0402_16V7K

RTCVREF

12

PC11

PJ1 PAD-OPEN 3x3m

21

@

82.5K_0402_1%

24.9K_0402_1%

4.7U_0805_6.3V6K

PJP1

JST_B5B-EH-A(LF)(SN)@

1

2

1 1

2 2

2

3

4

5

12

3.3V

3 3

PR21 560_0603_5%

1 2

+CHGRTC

PR22 560_0603_5%

1 2

PR279 0_0402_5%

PF1 12A_65V_451012MRL

2 1

PR12 215K_0402_1%

1 2

12

PU2 G920AT24U_SOT89

3

OUT

GND

1

+1.5VS+1.5VSP

PC6

0.1U_0402_16V7K

IN

+1.8VP

ADPIN

12

PR175 10K_0402_1%

1 2

3 2

PR16 10K_0402_1%

2

12

PC1

560P_0402_50V7K

PR5 1M_0402_1%

1 2

VS

8

P

+

-

G

4

PR23 200_0805_5%

12

PC154

PC185

680P_0603_50VK

0.1U_0402_16V7K

PL2 FBMA-L18-453215-900LMA90T_1812

1 2

12

PC2

100P_0402_50V8J

PC131

0.01U_0402_25V7K

1 2

PU1A

1

O

LM393DT_SO8

12

RTCVREF

3.3V

BATT+

CHGRTCP

12

PC10

1U_0805_25V4Z

51ON#<32>

PJ2

PAD-OPEN 3x3m

1 2

21

PD20

@

V-PORT-0603-220 M-V05_0603

12

PC3

100P_0402_50V8J

VIN

12

PR9

10K_0805_5%

12

PD3

RLZ4.3B_LL34

PD5 RLS4148_LLDS2

12

PR27 22K_0402_1%

1 2

+1.8V

PR26

(6A,240mils ,Via NO.=12) (6A,240mils ,Via NO.= 12)

PJ3 PAD-OPEN 3x3m

+5VALWP

1 2

(5A,200mils ,Via NO.= 10)

4 4

+3VALWP

PJ6 PAD-OPEN 3x3m

1 2

+5VALW

+3VALW

+0.9VSP

(0.3A,40mils ,Via NO.= 2)

+2.5VSP

PJ4 PAD-OPEN 3x3m

1 2

PJ11 PAD-OPEN 3x3m

1 2

+0.9VS

+2.5VS

(4.5A,180mils ,Via NO.= 9)

PJ7 PAD-OPEN 3x3m

+1.05VSP

1 2

(5A,200mils ,Via NO.= 10)

+VCCP

+VSBP +VSB

A

(0.3A,40mils ,Via NO.= 2)

PJ8 PAD-OPEN 3x3m

1 2

PC4

560P_0402_50V7K

12

PR15

12

100K_0402_5%

B

ADP_ID <33>

PR11 10K_0402_5%

1 2

PACIN

10K_0402_1%

PQ4 TP0610K-T1-E3_SOT23

PC12

0.22U_1206_25V7K

B

C

ACIN

Precharge detector Min. typ. Max.

H-->L 13.843V 14.247V 14.636V

VIN

12

PR1

10_1206_5%

12

PD1

RLZ24B_LL34

ACIN <21,33>

PACIN <41>

L-->H 14.936V 15.381V 15.814V

PR2 1K_1206_5%

1 2

VS

PD2 RLS4148_LLDS2

12

ACOFF<33,41>

PR3 1K_1206_5%

1 2

PR4 1K_1206_5%

1 2

PR8 1K_1206_5%

1 2

DTC115EUA_SC70

Vin Detector

High 18.135 17.5660 17.011 Low 14.866 14.355 14.063

VIN

PD4

RLS4148_LLDS2

1 2 12

VS

MAINPWON<40,42>

PR20

PR276

33_1206_5%

13

2

33_1206_5%

12

PC13

0.1U_0603_25V7K

ACON<41>

PRECHG<41>

Security Classification

Issued Date

THIS SHEET OF EN GINEE RING DR AWING IS THE P ROPRIE TARY P ROPER TY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SEC RET INFOR MATIO N. T HIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY O R DISCL OSED T O ANY TH IRD PAR TY WIT HOUT P RIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2005/10/06 2006/10/06

PD6 RB715F_SOT323

2 3

PR271 200K_0402_1%

12

Compal Secret Data

VL

1

RTCVREF

Deciphered Date

C

12

PR19

100K_0402_1%

PU1B LM393DT_SO8

12

PC8

0.1U_0603_25V7K

7

O

PR17

2.2M_0402_5%

PR28 34K_0402_1%

D

BATT ONLY

Precharge detector

Min. typ. Max. H-->L 6.138V 6.214V 6.359V L-->H 7.196V 7.349V 7.505V

PQ1 TP0610K-T1-E3_SOT23

13

12

PR6

PR7

100K_0402_5%

13

2

PQ2

DTC115EUA_SC70

12

VS

8

5

P

+

6

-

G

4

12

PC9

1000P_0402_50V7K

12

D

S

12

PR30

@

66.5K_0402_1%

Title

Size Document Number Rev

B

Date: Sheet

星期三

2

12

PR13

100K_0402_5%

13

2

PQ3

12

PR24

205K_0402_1%

PRG++

PQ5 RHU002N06_SOT323

13

2

G

PR29 47K_0402_5%

13

PQ6 DTC115EUA_SC70

2

Compal Electronics, Inc.

SCHEMATIC, M/B LA-3281

12, 2006

七月

401429

D

B+

12

PR18

499K_0402_1%

12

PC7

PR25

499K_0402_1%

0.01U_0402_25V7K

12

39 47,

PACIN <41>

+5VALWP

B

of

A

B

C

D

12

PC14

+3VALWP

1000P_0603_50V7K

BATT++

PL3 FBMA-L18-453215-900LMA90T_1812

1 2

12

PC15

1000P_0603_50V7K

ALI/MH#

BATT_TEMP <33>

EC_SMB_DA1 <33,34> EC_SMB_CK1 <33,34>

BATT+

12

PC16

0.01U_0402_25V7K

PH1 under CPU botten side :

CPU thermal protection at 85 degree C Recovery at 70 degree C

VL

12

PR33

1 2

12

PC18

1000P_0402_50V7K

8.66K_0402_1% PR37

47K_0603_1%

TM_REF1

PH1

12

100K_0603_1%_TH11-4H104FT

12

PC17

PC19

1U_0603_6.3V6M

12

0.1U_0603_25V7K

3 2

PR39 150K_0402_1%

VS

8

P

+

-

G

4

PR34 442K_0603_1%

1 2

1

O

PU3A LM393DT_SO8

12

VL

PR32

1 2

150K_0402_1%

MAINPWON <39,42>

PR40

PR177 1K_0402_1%

1 2

12

PF2 12A_65V_451012MRL

2 1

PR176

1K_0402_1%

PR36

6.49K_0402_1%

1 2

PR178 47K_0402_5%

1 2

+3VALWP

PJP2

@

ALLTO_C103D6-10701-L

1

2 3 4

1 1

5 6 7

BATT_S1

1

ALI/NIMH#

2

AB/I

3

TS_A

4

EC_SMDA

5

EC_SMCA

6 7

12

PR31

PR35

100_0402_1%

12

PR38

1K_0402_1%

2 2

150K_0402_1%

PQ7 TP0610K-T1-E3_SOT23

B+

12

PC20

PR42

VL

22K_0402_1%

1 2

PR41

100K_0402_5%

0.22U_1206_25V7K

13

2

+VSBP

12

PC21

0.1U_0603_25V7K

5 6

VS

8

P

+

-

G

4

7

O

PU3B LM393DT_SO8

3 3

SPOK<42>

PR43

1 2

100K_0402_5%

1 2

PR44 0_0402_5%

13

D

2

G

PQ8

PC22

S

RHU002N06_SOT323

12

0.1U_0402_16V7K

4 4

Security Classification

Issued Date

THIS SHEET OF EN GINEE RING DR AWING IS THE P ROPRIE TARY P ROPER TY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SEC RET INFOR MATIO N. T HIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

MAY BE USED BY O R DISCL OSED T O ANY TH IRD PAR TY WIT HOUT P RIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

B

2005/10/06 2006/10/06

Compal Secret Data

Deciphered Date

C

Title

Size Document Number Rev

B

Date: Sheet

Compal Electronics, Inc. SCHEMATIC, M/B LA-3281

星期三

401429

12, 2006

七月

D

of

40 47,

B

A

B

C

D

E

Fosc=14100/Rt=14100/47=300KHz

PQ9

AO4407_SO8

8

VIN

1 1

12

PR47

47K_0402_5%

DTA144EUA_SC70

2

13

D

2

2 2

G

ACOFF#

S

PQ16 RHU002N06_SOT323

PD12 RLS4148_LLDS2

1 2

7 5

PQ12

47K

2

47K

13

PQ15 DTC115EUA_SC70

4

1 3

2

G

P2

1 2 36

12

PC27

0.1U_0603_25V7K

12

PR55

150K_0402_1%

IREF <33>

13

D

PQ17

S

RHU002N06_SOT323

12

PR46

200K_0402_1%

PR60 133K_0402_1%

PQ10 AO4407_SO8

1 2 3 6

4

PR51

MB39A126

12

1 2

10K_0402_1%

1 2

12

PR53

PC31

10K_0402_1%

0.01U_0402_25V7K

12

PR63

8 7

5

PC28 4700P_0402_25V7K

1 2

12

PR54

30K_0402_1%

12

PC33

0.22U_0603_16V7K

12

100K_0402_1%

MB39A126

PC39

0.01U_0402_25V7K

PR57 1K_0402_1%

1 2

CP=3.125A

1 2

PR45

0.02_2512_1%

PR52 100K_0402_1%

PC34 2200P_0402_50V7K

1 2

12

PR61 10K_0402_1%

12

PR65

0_0402_5%

B+

PU4 MB39A126PFV-ER_SSOP24

1

-INC2

2

OUTC2

3

+INE2

4

-INE2

5

ACOK

6

VREF

7

ACIN

8

-INE1

9

+INE1

10

12

OUTC1

11

SEL

12

-INC1

+INC2

GND

VCC

OUT

XACOK

-INE3

FB123

CTL

+INC1

CS

VH

RT

PL4 FBMA-L11-322513-201LMA40T_1210

1 2

24

23

PC32

0.1U_0603_25V7K

1 2

PR58

56.2K_0402_1%

1 2

PR62 33K_0402_1%

MB39A126

1 2

PC40 10P_0402_50V8J

CS

1 2

22

21

20

19

18

17

16

15

14

13

P2

12

PR49

0_0603_5%

PC30

0.1U_0603_25V7K

PC35 1500P_0603_50V7K

1 2

PC29

0.22U_0603_16V7K

1 2

12

VIN

12

@

PR59

PR278 0_0402_5%

1 2

12

PR64

@

PQ11 AO4407_SO8

1 2

CHG_B+

12

PC23

4.7U_1206_25V6K

578

47K_0402_5%

ACON

47K_0402_5%

12

PC24

4.7U_1206_25V6K

36

241

LXCHRG

12

PC25

0.1U_0603_25V7K

PQ13 AO4407_SO8

PL5 10U_LF919AS-100M-P3_4.5A_20%

1 2

12

PD11

PD10

EC31QS04

12

PC26

2200P_0402_50V7K

3 6

PR48 47K_0402_1%

1 2

PR50

10K_0402_1%

1 2

ACOFF#

13

ACOFF

2

PQ14 DTC115EUA_SC70

1 2

PR56

0.02_2512_1%

4

VIN

ACOFF <33,39>

PJ12 PAD-OPEN 3x3m

1 2

PQ39 AO4407_SO8

8

7

5

12

PR273

10K_0402_1%

47K

2

47K

1 3

PQ41

DTA144EUA_SC70

12

PC36

10U_1206_25VAK

4

PR272 100K_0402_1%

1 2

13

PQ40 DTC115EUA_SC70

12

PC37

10U_1206_25VAK

Charger

1 2 36

BATT+

2

PRECHG <39>

PC38

10U_1206_25VAK

BATT+

PR66 22K_0402_1%

PACIN<39>

ACON<39>

3 3

4 4

1 2

A

IREF=0.574~2.56V

FSTCHG<33>

2

+3VALWP

12

PR67

13

PQ19 DTC115EUA_SC70

1

0

B

47K_0402_5%

VS

PU12A

8

LM358DR_SO8

P

+

-

G

4

2

3 2

CS

13

PQ18 DTC115EUA_SC70

PC41 47P_0402_50V8J

1 2

LI-3S :13.5V----BATT-OVP=1.5V BATT-OVP=0.1112*BATT+

BATT+

VS

12

PR277 10K_0402_1%

BATT_OVP<33>

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DIS CLOSE D TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

12

2005/10/06 2006/10/06

8

5

P

+

7

0

6

-

G

PU12B

4

LM358DR_SO8

Compal Secret Data

Deciphered Date

12

PR68

340K_0402_1%

12

PC42

PR69

0.01U_0402_25V7K 499K_0402_1%

12

PR72

105K_0402_1%

12

PC43

D

CC=2.746A

(100K/(100K+133K))*2.56V=1.0985V

1.098/(20*0.02)=2.746A

CP Point=3.125A

5V*(10K/(30K+10K))=1.25V

1.25V/(20*0.02)=3.125A

Charge voltage 3S CC-CV MODE : 12.6V SEL is L

0.01U_0402_25V7K

Title

Size Document Number Rev

B

Date: Sheet

Compal Electronics, Inc. SCHEMATIC, M/B LA-3281

401429

星期三七月

E

B

of

41 47, 12, 2006

A

B+

PL6 FBMA-L11-322513-201LMA40T_1210

5

PQ21

4

5HG

5

PC45

0.1U_0603_25V7K

1 2

SI4800BDY-T1-E3_SO8

1 2

PR78 0_0603_5%

DH5

LX5

1 2

PJ13

1 1

MAX8743_B+

JUMP_43X79

112

B+++

2

12

PC47

PC48

2200P_0402_50V7K

10U_1206_25VAK

D8D7D6D

S1S2S3G

D8D7D6D

PQ29

S1S2S3G

4

SI4810BDY-T1-E3_SO8

DL5

2 2

+5VALWP

1

+

PC56

PC186

2

150U_V_6.3VM_R18

@

150U_V_6.3VM_R18

+5V Ipeak = 6.66A ~ 10A

3 3

PL7

1 2

4.7UH_PCMC063T-4R7MN_5.5A_20%

PR85

1 2

10.2K_0402_1%

@

PR87

0_0402_5%

1 2

VS

PZD1 RLZ5.1B_LL34

1 2

PR88 47K_0402_5%

1 2

12

PR91

1 2

100K_0402_5%

PC57

0.047U_0603_16V7K

B

PR74

0_0603_5%

1 2

PR94 47K_0402_5%

1 2

BST5A

1 2

0_0402_5%

1 2

12

PC61

PC54

PR86 0_0402_5%

2VREF_1999

PR89

12

2

3

PD13

1

CHP202UPT_SOT323-3

MAX8743_B+

12

PR76

12

VL

12

4.7U_0805_6.3V6K

14

BST5

16

DH5

15

LX5

19

DL5

21

OUT5

9

FB5

1

N.C.

MAX8734AEEI+_QSOP28

6

SHDN#

4

ON5

3

ON3

12

SKIP#

8

REF

PC59

0.22U_0603_16V7K

18

C

PC46

BST3BBST5B

VL

12

PR75

PR77

1 2

4.7_1206_5%

@

PC52

PC55

1U_0805_25V4Z

12

0.1U_0603_25V7K

13

17

20

V+

TON

LD05

VCC

PU6

PGOOD

GND

PRO#

LDO3

23

10

25

12

PC60

PR92

4.7U_0805_6.3V6K

1 2

47_0402_5%

ILIM3

ILIM5 BST3

DH3

DL3 LX3

OUT3

FB3

0_0402_5%

12

2VREF_1999

PC53

1U_0805_16V7K

5

11 28

26 24 27 22

7 2

PC49

0.1U_0402_16V7K

PR81

PR80

1 2

SPOK<40>

200K_0402_1%

PR83

PR84

1 2

365K_0402_1%

215K_0402_1%

0.1U_0603_25V7K

1 2

MAX8743_B+

PR79

0_0603_5%

1 2

BST3A

PJ14 JUMP_43X79

112

DH3

2

12

PC51

PC50

2200P_0402_50V7K

10U_1206_25VAK

3HG

LX3

PR82

0_0603_5%

1 2

DL3

1 2

D

5

D8D7D6D

PQ20

S1S2S3G

4

SI4800BDY-T1-E3_SO8

5

D8D7D6D

PQ30

S1S2S3G

4

SI4810BDY-T1-E3_SO8

PL8

1 2

+3VALWP

4.7UH_PCMC063T-4R7MN_5.5A_20%

PR90

3.57K_0402_1%@

PR93

0_0402_5%

1

+

PC58

2

150U_V_6.3VM_R18

+3.3V Ipeak = 6.66A ~ 10A

0.047U_0603_16V7K

MAINPWON <39,40>

12

PC62

1U_0603_6.3V6M

4 4

Security Classification

Issued Date

THIS SHEET OF EN GINEE RING DR AWING IS THE P ROPRIE TARY P ROPER TY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SEC RET INFOR MATIO N. T HIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

MAY BE USED BY O R DISCL OSED T O ANY TH IRD PAR TY WIT HOUT P RIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

B

2005/10/06 2006/10/06

Compal Secret Data

Deciphered Date

C

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, M/B LA-3281

星期三

12, 2006

七月

D

401429

of

42 47,

B

5

D D

PR266

0_0402_5%

SYSON<33,35>

C C

B B

SUSP#<18,24,26,33,34,35,44>

12

PR103

24K_0402_1%

@

PC184

0.01U_0402_25V7K

@

0_0402_5%

PC72

1 2

0.022U_0402_16V7K

PR179 100K_0402_1%

PR101

12

PC73

12

0.1U_0603_25V7K

75K_0402_1%

1.8VSET

PR106

4

+5VALWP

PR99

PR100

1 2

22_0402_1%

1K_0402_1%

12

PC74

100K_0402_1%

PC75

1U_0603_6.3V6M

0.01U_0402_25V7K

PR105

1 2

DREF

1 2

PR104

1.05SET

PR172

1 2

150K_0402_1%

1 2

61.9K_0402_1%

12

PC132

0.1U_0402_16V7K

1.8VSET

12

PC65

1000P_0402_50V7K

PU7

25

GNDA

1

ON/SKIP2

2

VIN

3

VREF

4

TSET

5

VDDA

6

ON/SKIP1

OZ813LN_QFN24

12

PC77

1000P_0402_50V7K

24

21

23

22

CS2P

CS2N

VSET2

VSET17CS1N8CS1P9PGD110LX111HDR1

@

1 2

12

+3VALWP

20

PGD2

PR263

PR264

@

3

PR262

0_0402_5%@

1 2

PR269 0_0402_5%

1 2

+3VALWP

12

PR261

@

1.8VS2N

1.8VS2P

DH_1.8V_1 DH_1.8V_2 LX_1.8V

12

19

LX2

HDR2

BST2

LDR2 VDDP GDNP

LDR1

BST1

12

PC67

BST_1.8V

18 17 16 15 14 13

BST_1.05V

12

RB751V-40TE17_SOD323-2

PC76

0.1U_0603_25V7K

DL_1.8V

DH_1.05V_1

0_0402_5%

LX1.05V

1.05VS1P

12

1.05VS1N DL_1.05V

DH_1.05V_2

1K_0402_1%

D8D7D6D

1K_0402_1%

SI4810BDY-T1-E3_SO8

RB751V-40TE17_SOD323-2

1 2

12

PC71 1U_0805_16V7K

1 2

PR270

0_0402_5%

PD17

PQ23

PD16

+5VALWP

5

4

5

4

D8D7D6D

S1S2S3G

D8D7D6D

S1S2S3G

D8D7D6D

S1S2S3G

PQ24

PQ31

2

PJ15 JUMP_43X79

OZ813_B+

2

112

PF5 7A_24VDC_429007.WRML@

2 1

5

PQ22

4

SI4800BDY-T1-E3_SO8

5

4

12

PC156

2.2U_0603_6.3V6K

12

SI4800BDY-T1-E3_SO8

SI4810BDY-T1-E3_SO8

12

PC63

10U_1206_25VAK

PL10

3.3UH_PCMC063T-3R3MN_6A_20%

1 2

PR97

100K_0402_1%

1 2

+5VALWP

PF6 7A_24VDC_429007.WRML@

3.3UH_PCMC063T-3R3MN_6A_20%

100K_0402_1%

1 2

PC79

10U_1206_25VAK

1.8VS2P

1.8VS2N

PJ18 JUMP_43X79

112

2 1

1 2

PR108

1.05VS1P

1.05VS1N

1 2

PC68 6800P_0402_25V7K

12

2

PL11

1 2

5600P_0402_25V7K

12

PR98 22K_0402_1%

1 2

PC69

PR109

29.4K_0402_1% PC80

PC81

PL9 FBMA-L11-322513-201LMA40T_1210

12

PR95

51_0402_1%

12

PC70

22P_0402_50V8J

4700P_0402_25V7K

OZ813_B+

12

PR107

51_0402_1%

12

PC82

4700P_0402_25V7K

1 2

1

+

PC66

2

1

+

PC78

2

220U_D2_4VM_R15

+1.8VP

+1.05VSP

B+

OCP=6A

1

A A

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DIS CLOSE D TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/10/06 2006/10/06

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

2

Date: Sheet

SCHEMATIC, M /B LA-3281

T, 12, 2006

401429

星

薑七月

1

43 47

B

of

5

PJ16 JUMP_43X79

2

112

D D

C C

PL12

1 2

B+

FBMA-L11-322513-201LMA40T_1210

SUSP#<18,24,26,33,34,35,43>

7A_24VDC_429007.WRML @

PF7

2 1

PR114

1 2

47K_0402_5%

12

PC83

10U_1206_25VAK

12

PC89

0.01U_0402_25V7K

4

6269_VCC

12

PC87

2.2U_0603_6.3V6K

PR113

1 2

0_0402_5%

PR265

10K_0402_1%

1 2

1

2

3

4

PU8

VIN

VCC

FCCM

EN

16

17

15

GND

PGOOD

COMP5FB6FSET

PHASE

7

PHASE_VCCPP

BOOT_VCCPP

13

14

UG

BOOT

PVCC

PGND

ISEN

VO

8

3

PR110

1 2

0_0603_5%

12

11

LG

10

9

UG_VCCPP

1 2

PC85 0.1U_0402_16V7K

12

PR111

4.7_0603_5%

@

PR112

1 2

4.7_0603_5%

1 2

2.2U_0603_6.3V6K

LG_VCCPP

ISEN_VCCPP

1 2

PR115

8.66K_0402_1%

ISL6269CRZ-T_QFN16

+5VS

PC86

6269_VCC

2

5

PQ26

D8D7D6D

S1S2S3G

SI4800BDY-T1-E3_SO8

4

PL13

3.3UH_PCMC063T-3R3MN_6A_20%

5

PQ27

D8D7D6D

SI4810BDY-T1-E3_SO8

S1S2S3G

4

1 2

1

+

PC88 220U_D2_4VM_R15

2

1

OCP=6A

+1.5VSP

12

PC91

22P_0402_50V8J

B B

+5VS

12

PC93

1U_0603_6.3V6M

6

PU10

7

PR121

33K_0402_1%

SUSP#,26,33,34,35,43>

A A

1 2

PC100

0.01U_0402_25V7K

5

POK

8

EN

12

5

VIN

4

VOUT

VCNTL

3

VOUT

2

FB

9

VIN

GND

1

APL5912-KAC-TRL_SO8

+3VS

1

PJ10

1

JUMP_43X79

2

12

PC96 22U_1206_6.3V6M

2.15K_0402_1%

PR122

12

PR125

1K_0402_1%

4

12

PC99

0.01U_0402_25V7K

PC97

12

PR116

49.9K_0402_1%

12

PC92 6800P_0402_25V7K

3K_0402_1%

+2.5VSP

1

12

+

PC98

150U_D_6.3VM@

2

22U_1206_6.3V6M

12

PC90

PR117

57.6K_0402_1%

12

PR119

0.01U_0402_25V7K

PR118

1 2

4.53K_0402_1%

+1.8VP

1

PJ9

1

JUMP_43X118

2

12

PC94

22U_1206_6.3V6M

PR123

SUSP<35>

100K_0402_1%

0.1U_0402_16V7K

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DIS CLOSE D TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

RHU002N06_SOT323

13

PQ28

2

12

G

12

PC103

2005/10/06 2006/10/06

Compal Secret Data

1K_0402_1%

D

S

12

PR120

12

PR124 1K_0402_1%

Deciphered Date

12

PC101

0.1U_0402_16V7K

2

PU9

2 3 4

APL5331KAC-TRL_SO8

+0.9VSP

12

PC102 22U_1206_6.3V6M

VIN1VCNTL GND VREF VOUT

6 5

NC

7

NC

8

NC

9

TP

Title

Size Document Number Rev

Custom

Date: Sheet

+3VALWP

12

PC95 1U_0603_6.3V6M

Compal Electronics, Inc.

SCHEMATIC, M /B LA-3281

T, 12, 2006

401429

1

星

薑七月

of

44 47

B

5

D D

PR217

NTC

100K_0402_5%

PR218

PR241

1 2

1 2 1 2 1 2

10K_0402_1%

12 12 12 12 12 12

PR253 0_0402_5%@

1 2

PR219 0_0402_5% PR221 0_0402_5% PR222 0_0402_5% PR223 0_0402_5% PR225 0_0402_5% PR227 0_0402_5% PR228 0_0402_5%

C C

B B

A A

CLK_ENABLE#<15>

PR233 499_0402_1% PR234 0_0402_5%

VGATE<21>

VR_ON<33>

PR236 0_0402_5%

PR244 0_0402_5%

1 2

PR247 0_0402_5%

1 2

PR249 0_0402_5%

1 2

CPU_VID0<5> CPU_VID1<5> CPU_VID2<5> CPU_VID3<5> CPU_VID4<5> CPU_VID5<5> CPU_VID6<5>

DPRSLPVR<7,21> H_DPRSTP#<4,20>

H_PSI#<5>

+3VS

PR240

1 2

2K_0402_1%

PR250

1 2

10K_0402_5%

@

H_PROCHOT#<4>

1 2

13K_0402_5%

PR232 71.5K_0402_1%

1 2

PC170 0.22U_0603_16V7K

+3VS

12

PR252

56_0402_5%

PR254 10K_0402_5%

1 2

PC181

1 2

4

+5VS

PR214

12

PR215 10_0402_5%

VCC

12 12

PC168470P_0402_50V8J

0.1U_0402_16V7K

5VS1

PC165 1U_0603_6.3V6M

1 2

PU11

19

Vcc

6

THRM

31

D0

32

D1

33

D2

34

D3

35

D4

36

D5

37

D6

7

TIME

9

CCV

11

REF

39

DPRSLPVR

40

DPRSTP

3

PSI

2

PWRGD

1

CLKEN

38

SHDN

5

VRHOT

4

POUT

MAX8770GTL+_TQFN40

VSSENSE<5>

12

0_1206_5%

PC164

2.2U_0603_6.3V6K

VDD TON

BST1

DH1

LX1

DL1

PGND1

GND

CSP1

CSN1

FB

CCI

DH2

BST2

LX2

DL2

PGND2

CSP2

CSN2

GNDS

VSSENSE

12

PR216

1 2

200K_0402_5%

25 8 30 29 28 26 27 18 17 16 12 10 21 20 22 24 23 14 15 13

PC174

4700P_0402_25V7K

PR251

100_0402_5%

PR255

10_0402_5%

PR220

2.2_0402_5%

BST1_CPU BSTM1_CPU

1 2

DH1__CPU LX1__CPU DL1__CPU

CSP1__CPU CSN1_CPU FB_CPU CCI_CPU DH2_CPU BST2_CPU LX2_CPU DL2__CPU

CSP2_CPU CSN2__CPU

1 2

12

PC157

0.01U_0402_25V7K

12

PR274 0_0402_5%

1 2

PC175

PC189

180P_0402_50V8J

3

0.22U_0603_16V7K PC166

1 2

PR239

1 2

2.2_0402_5%

BSTM2_CPU

12

0.22U_0603_16V7K

PC190

1 2

180P_0402_50V8J

1 2

PR275 0_0402_5%

1 2

PC188

180P_0402_50V8J

1 2

NTC

PR248 20K_0402_1%

PC187

1 2

180P_0402_50V8J

PR238 @3K_0603_1%

1 2

PR242 3.65K_0402_1%

1 2

PR245 3K_0603_1%@

1 2

578

3 6

578

3 6

241

PQ37

IRF8113PBF_SO8

CPU_B+

PQ33

IRF8113PBF_SO8

DL1__CPU

PR246 3K_0603_1%@

1 2

DL2__CPU

PQ32

3 5

241

578

3 6

241

PR237 0_0402_5%

1 2

PC173 470P_0402_50V8J

1 2

29.6

PQ35

3 5

241

578

PQ36

3 6

241

PR260 0_0402_5%

1 2

2

PJ17 PAD-OPEN 3x3m

1 2

2 1

PF8

12

PC159

10U_1206_25VAK

SI7682DP-T1-E3_SO8

12

PQ34

12

IRF8113PBF_SO8

1 2

SI7682DP-T1-E3_SO8

12

IRF8113PBF_SO8

12

PC161

PC160

10U_1206_25VAK

PR224

6.8_1206_5%

PC167

PC172

PR256

6.8_1206_5%

PC182

PC162

0.1U_0603_25V7K

10U_1206_25VAK

PL15

P_0.36H_ETQP4LR36WFC_24A_20%

PR226

PR230

2.1K_0603_1%

1 2

3.48K_0402_1%

1 2

10KB_0603_5%_ERTJ1VR103J

PC169

0.22U_0603_16V7K

470P_0603_50V7K

4700P_0402_25V7K

470P_0603_50V7K

1 2

PC171 @0.022U_0402_16V7K

1 2

PR243 100_0402_5%

1 2

PC176

12

PR257

2.1K_0603_1%

7A_24VDC_429007.WRML @

12

PC163

2200P_0402_50V7K

12

NTC

PR231

1 2

CPU_VCC_SENSE

12

PC177

10U_1206_25VAK

P_0.36H_ETQP4LR36WFC_24A_20%

PR258

3.48K_0402_1%

1 2

PC183 0.22U_0603_16V7K

PR229

10_0402_5%

12

PC179

PC178

10U_1206_25VAK

0.1U_0603_25V7K

12

PL16

PR259

10KB_0603_5%_ERTJ1VR103J

1 2

1

PL14 FBM-L11-322513-201LMAT_1210

12

1

+

PC158

2

+CPU_CORE

12

VCCSENSE<5>

PR235

1 2

100_0402_5%

CPU_B+

12

PC180

2200P_0402_50V7K

NTC

B+

100U_25V_M

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2005/10/06 2006/10/06

3

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, M/B LA-3281

星期

三七月

, 12, 2006

401429

B

of

45 47

1

A

B

C

D

E

Version change list (P.I.R. List) Page 1 of 1

Rev. PG# Modify List B.Ver# PhaseFixed IssueItem

1 1

1 A void leakage voltage and current to effect BATT_OVP signal 0 .1 41 1.add PR277

2 A dd power consumption 0.1 41 1.Change external control signal to ACON

2.Add PR278

3 For EMI request 0.1 39 1.add PR279

4 Change recovery value is in order to adaptor voltage too low issue 0 .1 39 1It .changed value of PR24 that 499k_0402 to 205k_0402

2 2

It is order to reduce CPU core voltage inflence

5

3 3

4 4

0.2 45 Add pc187,pc188,pc189,pc190

Compal Electronics, Inc.

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SEC RET INFOR MATI ON. T HIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

D

SCHEMATIC, M/B LA-3281

Size D ocument Number Rev

401429

Date: Sheet of

星期三

12, 2006

七月

46 47,

E

B

A

B

C

D

E

Version change list (P.I.R. List) Page 1 of 1

Rev. PG# Modify List B.Ver# PhaseFixed Issue/Reason for changeItem

A Test

1 1

1

Copy schematic from HDL00

2 28Add 2nd BT connector

3

Add 2nd LID switch 0.1

Remove Front LEDs from MB

0.1

Add JP51,C60,Q706,Q705,Q708,R801,R810

36

Add U38,D30,R800,R802,R803,C601,C602

370.1 Del D6,D7,D8,D5,R190,R194,R191,R192,R1894

B Test

29/300.2Change audio solution from AD1986A to ALC8615

2 2

Add Front LEDs to MB(Reverse HDL00 Design) Add D6,D7,D8,D5,R190,R194,R191,R192,R189

0.2 376

C Test

Sloving ICS pin 50, 51 no clock issue 150.3 Add R865 to U29.8 and grounded7

8

9 EMI solution 0.3 16 1. change L14 from 0 ohm to bead 300 ohm

3 3

wake up on USB when AC-IN. 0.3 31, 33, 37 1. Add R866, R867

2. change EC pin 90 from KSO17 to EC_GPIO4A

3. connect R866, R867 pin2 together, and net name is USB_ON#.

4. change syson# to USB_ON#, and control U9, U10 and U25.

2. change C295 from 0.8pF to 470pF

10

11

12

13

14

4 4

Compal Electronics, Inc.

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SEC RET INFOR MATI ON. T HIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

D

SCHEMATIC, M/B LA-3281

Size D ocument Number Rev

401429

Date: Sheet of

星期三

12, 2006

七月

47 47,

E

B