COMPAL LA-3271P Schematics

A

1 1

B

C

D

E

2 2

Compal Confidential

Schematics Document

945GM+ICH7

2006 / 08 / 18

3 3

Rev:0.4

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2005/12/1 2006/12/01

Compal Secret Data

Deciphered Date

Title

Cover Sheet

Size Document Number Rev

Custom

LA-3271P

D

Date: Sheet

E

142Monday, August 21, 2006

0.4

of

A

B

C

D

E

Compal confidential

Project Code: ANRIAL3000(IAL30)
File Name : LA-3271P

1 1

Thermal Sensor
ADM1032ARM

page 4 page 13

Clock Generator
ICS9LPR310

CRT

page 14

LCD CONN

page 14

YONAH CPU

page 4,5,6

533/667MHZ

Calistoga GMCH

PCBGA1466

page 9,10,11,12

2.5GHz(1.2V)

Bandwidth 500MB

DMI

DDR-2 DDR2-SO-DIMM X2

page 7,8

Daul Channel DDR-2

2 2

PCI EXPRESS

ICH7-M

Broadcom

BCM5787

page 22

Mini Card

page 23

PCI BUS

BGA652

page 15,16,17,18

USB 2.0

USB 2.0

HD-Interface

RJ45 CONN

page 23

CradBus Controller

R5C811

page 20,21

LPC BUS

SATA

USB conn x 4

page 29

Finger print

page 28

Audio CKT
ALC262

page 24

MDC Conn.

page 24

AMP & Audio Jack

RJ11 Conn

SATA HDD Conn.

page 19

page 25

PATA

3 3

CDROM Conn.

page 19

Slot 0

page 21

ENE KB910L

page 26

Power On/Off CKT.

page 30

Touch Pad

DC/DC Interface CKT.

page 32

4 4

Power Circuit DC/DC

page 33~41

A

RTC CKT.

page 16

Power OK CKT.

page 30

Issued Date

page 27

2005/12/1 2006/12/01

C

CONN.

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Int. KBD

page 27

BIOS

page 27

Compal Secret Data

Deciphered Date

TPM Conn

page 26

FINGERPRINT Conn

page 28

Title

Block Diagrams

Size Document Number Rev

Custom

LA-3271P

D

Date: Sheet

E

242Monday, August 21, 2006

0.4

of

A

Voltage Rails

Power Plane Description

VIN

1 1

2 2

B+
+5VALW
+3VALW
+RTCVCC RTC power
+5V 5V power rail ON OFFON
+3V
+1.8V
+5VS
+3VS
+2.5VS 2.5V switched power rail
+1.5VS
+0.9VS 0.9V switched power rail for DDR terminator
+CPU_CORE
+VCCP

Adapter power supply (19V)
AC or battery power rail for power circuit.
5V always on power rail

3.3V always on power rail

3.3V power rail

1.8V power rail for DDR
5V switched power rail

3.3V switched power rail

1.5V switched power rail

Core voltage for CPU

1.05V power rail

B

S1 S3 S4/ S5

ON ON ON

ON
ON
ON ONON

ON
ON

ON
ON OFF OFF
ON OFF OFF
ON OFF
ON OFF
ON OFF

ONONON
ON ON
ON ON

OFF

ON

OFF

ON

OFFON

OFF
OFF

OFF

OFF

OFF

OFF

C

SIGNAL

STATE

Full ON

S1(Power On Suspend)

S3 (Suspend to RAM)

SLP_S1# SLP_S3#

HIGH HIGH HIGH HIGH

LOW

LOW

LOW

S4 (Suspend to Disk)

S5 (Soft OFF)

LOW LOW LOW LOW

Board ID Table for AD channel

Vcc 3.3V +/- 5%

Board ID

0
1
2
3
4
5
6
7 NC

100K +/- 5%Ra / Rc

Rb / Rd V min

0

8.2K +/- 5%
18K +/- 5%
33K +/- 5%
56K +/- 5%
100K +/- 5%
200K +/- 5%

AD_BID

0 V

0.216 V 0.250 V 0.289 V

0.436 V

0.712 V

1.036 V

1.453 V 1.650 V 1.759 V

1.935 V

2.500 V

D

SLP_S4# SLP_S5# +VALW +V +VS Clock

ON

ON

ON

OFF

OFF

V

AD_BID

ON ON

ON

OFF

OFF

OFF

max

LOW

OFF

OFF

OFF

HIGH

LOWLOWLOW

HIGHHIGHHIGH

HIGH

HIGH

V typ

AD_BID

ON

ON

ON

ON

ON

0 V 0 V

0.503 V

0.819 V

0.538 V

0.875 V

1.185 V 1.264 V

2.200 V

3.300 V

2.341 V

3.300 V

E

External PCI Devices

Device IDSEL# REQ#/GNT# Interrupts

CardBus
Mini-PCI

AD21
AD22

0
1

PIRQE/PIRQF/PIRQG
PIRQF/PIRQG

BOARD ID Table

Board ID

0
1
2

PCB Revision

0.1

0.2

BTO Item BOM Structure

BTO Option Table

3
4
5
6
7

EC SM Bus1 address

3 3

Device

Smart Battery
EEPROM(24C16/02)

(24C04)

Address Address

1010 000X b?
1011 000Xb?

EC SM Bus2 address

Device

ADM1032

1001 110X b?0001 011X b?

ICH7 SM Bus address

Device

Clock Generator
(ICS ICS9LPR310)

DDRII DIMM0
DDRII DIMM2

4 4

Address

1101 001Xb?

1001 000Xb?
1001 010Xb?

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2005/12/1 2006/12/01

Compal Secret Data

Deciphered Date

Title

Notes

Size Document Number Rev

Custom

LA-3271P

D

Date: Sheet

E

342Monday, August 21, 2006

0.4

of

5

H_A#[3..31]9

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11

D D

H_REQ#[0..4]9

H_ADSTB#09
H_ADSTB#19

C C

1 2

+VCCP

B B

H_THERMDA, H_THERMDC routing together.
Trace width / Spacing = 10 / 10 mil

A A

CLK_CPU_BCLK#13

R87

56_0402_5%

H_RS#[0..2]9

R73 1K_0402_5%@

1 2

R79 51_0402_5%

1 2

+VCCP

CLK_CPU_BCLK13

H_DEFER#9

H_RESET#9

ITP_DBRESET#17

H_DPSLP#16

H_DPRSTP#16,37

H_DPWR#9

H_PWRGOOD16

H_CPUSLP#9,16

H_THERMTRIP#9,16

R392

54.9_0402_1%

1 2

5

H_ADS#9
H_BNR#9
H_BPRI#9

H_BR0#9

H_DRDY#9

H_HIT#9

H_HITM#9

H_LOCK#9

H_TRDY#9

H_DBSY#9

H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

H_ADSTB#0
H_ADSTB#1

CLK_CPU_BCLK
CLK_CPU_BCLK#

H_ADS#
H_BNR#
H_BPRI#
H_BR0#
H_DEFER#
H_DRDY#
H_HIT#
H_HITM#
H_IERR#
H_LOCK#
H_RESET# H_D#58

H_RS#0
H_RS#1
H_RS#2
H_TRDY#

ITP_BPM#0
ITP_BPM#1
ITP_BPM#2
ITP_BPM#3

ITP_DBRESET#

H_DBSY#
H_DPSLP#
H_DPRSTP#
H_DPWR#
ITP_BPM#4
ITP_BPM#5
H_PROCHOT#

H_PWRGOOD
H_CPUSLP#
ITP_TCK
ITP_TDI
ITP_TDO
TEST1
TEST2
ITP_TMS
ITP_TRST#

H_THERMDA
H_THERMDC
H_THERMTRIP#

H_RESET#

JP2A

J4

A3#

L4

A4#

M3

A5#

K5

A6#

M1

A7#

N2

A8#

J1

A9#

N3

A10#

P5

A11#

P2

A12#

L1

A13#

P4

A14#

P1

A15#

R1

A16#

Y2

A17#

U5

A18#

R3

A19#

W6

A20#

U4

A21#

Y5

A22#

U2

A23#

R4

A24#

T5

ADDR GROUP

A25#

T3

A26#

W3

A27#

W5

A28#

Y4

A29#

W2

A30#

Y1

A31#

K3

REQ0#

H2

REQ1#

K2

REQ2#

J3

REQ3#

L5

REQ4#

L2

ADSTB0#

V4

ADSTB1#

A22

BCLK0

A21

H1

E2

G5

F1

H5

F21

G6

E4

D20

H4

B1

F3

F4
G3
G2

AD4
AD3
AD1
AC4

C20

E1

B5

E5

D24
AC2
AC1
D21

D6
D7

AC5
AA6
AB3
C26
D25
AB5
AB6

A24
A25

C7

HOST CLK

BCLK1

ADS#
BNR#
BPRI#
BR0#
DEFER#
DRDY#
HIT#

CONTROL

HITM#
IERR#
LOCK#
RESET#

RS0#
RS1#
RS2#
TRDY#

BPM0#
BPM1#
BPM2#
BPM3#

DBR#
DBSY#
DPSLP#
DPRSTP#
DPWR#
PRDY#
PREQ#
PROCHOT#

PWRGOOD
SLP#
TCK
TDI
TDO
TEST1
TEST2
TMS
TRST#

THERMAL

THERMDA

DIODE

THERMDC
THERMTRIP#

FOX_PZ47823-2743-41_YONAH

YONAH

MISC

H_DPSLP#

H_DPRSTP#

4

DATA GROUP

LEGACY CPU

+VCCP

R143

1 2

56_0402_5%@

R145

1 2

56_0402_5%@

4

D10#
D11#
D12#
D13#
D14#
D15#
D16#
D17#
D18#
D19#
D20#
D21#
D22#
D23#
D24#
D25#
D26#
D27#
D28#
D29#
D30#
D31#
D32#
D33#
D34#
D35#
D36#
D37#
D38#
D39#
D40#
D41#
D42#
D43#
D44#
D45#
D46#
D47#
D48#
D49#
D50#
D51#
D52#
D53#
D54#
D55#
D56#
D57#
D58#
D59#
D60#
D61#
D62#
D63#

DINV0#
DINV1#
DINV2#
DINV3#

DSTBN0#
DSTBN1#
DSTBN2#
DSTBN3#
DSTBP0#
DSTBP1#
DSTBP2#
DSTBP3#

A20M#
FERR#

IGNNE#

INIT#
LINT0
LINT1

STPCLK#

SMI#

3

H_D#[0..63] 9

H_D#0

E22

D0#

H_D#1

F24

D1#

H_D#2

E26

D2#

H_D#3

H22

D3#

H_D#4

F23

D4#

H_D#5

G25

D5#

H_D#6

E25

D6#

H_D#7

E23

D7#

H_D#8

K24

D8#

H_D#9

G24

D9#

H_D#10

J24

H_D#11

J23

H_D#12

H26

H_D#13

F26

H_D#14

K22

H_D#15

H25

H_D#16

N22

H_D#17

K25

H_D#18

P26

H_D#19

R23

H_D#20

L25

H_D#21

L22

H_D#22

L23

H_D#23

M23

H_D#24

P25

H_D#25

P22

H_D#26

P23

H_D#27

T24

H_D#28

R24

H_D#29

L26

H_D#30

T25

H_D#31

N24

H_D#32

AA23

H_D#33

AB24

H_D#34

V24

H_D#35

V26

H_D#36

W25

H_D#37

U23

H_D#38

U25

H_D#39

U22

H_D#40

AB25

H_D#41

W22

H_D#42

Y23

H_D#43

AA26

H_D#44

Y26

H_D#45

Y22

H_D#46

AC26

H_D#47

AA24

H_D#48

AC22

H_D#49

AC23

H_D#50

AB22

H_D#51

AA21

H_D#52

AB21

H_D#53

AC25

H_D#54

AD20

H_D#55

AE22

H_D#56

AF23

H_D#57

AD24
AE21

H_D#59

AD21

H_D#60

AE25

H_D#61

AF25

H_D#62

AF22

H_D#63

AF26

H_DINV#0

J26
M26
V23
AC20

H23
M24
W24
AD23
G22
N25
Y25
AE24

A6
A5
C4
B3
C6
B4

D5
A3

H_DINV#1
H_DINV#2
H_DINV#3

H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3
H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3

H_A20M#
H_FERR#
H_IGNNE#
H_INIT#
H_INTR
H_NMI

H_STPCLK#
H_SMI#

H_DINV#0 9
H_DINV#1 9
H_DINV#2 9
H_DINV#3 9

H_DSTBN#[0..3] 9

H_DSTBP#[0..3] 9

H_A20M# 16
H_FERR# 16
H_IGNNE# 16
H_INIT# 16
H_INTR 16
H_NMI 16

H_STPCLK# 16
H_SMI# 16

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

ITP_DBRESET#

R91 200_0402_5%@

1 2

ITP_BPM#0
ITP_BPM#1
ITP_BPM#2
ITP_BPM#3
ITP_BPM#4

EC_SMB_CK210,26
EC_SMB_DA210,26

KH3-ORG.

R78

100K_0402_5%

EN_DFAN126

1 2

100K_0402_5%

+VCCP

H_THERMTRIP#

2005/12/1 2006/12/01

Compal Secret Data

FAN1VREF

FAN1_VFB

1

C137

2

1U_0603_10V4Z

R353

1 2

150K_0402_5%

+CPU_CORE

12

R398

1 2

C413

@

0.1U_0402_10V6K~N

Deciphered Date

1 2

R393
56_0402_5%

2

PAD
PAD

PAD
PAD
PAD
PAD

H_THERMDA

2200P_0402_50V7K

H_THERMDC

B+_BIAS

8

U24A

3

P

+IN

OUT

2

-IN

G

4

LM358DR2G_SO8~N

C389

2200P_0402_50V7K

1 2

R351

100K_0402_5%

1

C

Q35

2

B

PMBT3904_SOT23

E

3

2

T11

ITP_TDI

T12

ITP_TMS

T14
T15

ITP_TDO

T13
T16

ITP_BPM#5
ITP_TRST#
ITP_TCK

1

C388

2

EC_SMB_CK2
EC_SMB_DA2

SMBus Address: 1001110X (b)

1

C379

2

1U_0805_10V4Z

FAN1_ON

1

12

D10

RB751V_SOD323

2 1

MAINPWON 32,34,38

1

This shall place near CPU

R138 56_0402_5%

1 2

R137 56_0402_1%

1 2

R142 56_0402_5%

1 2

R141 56_0402_5%

1 2

R135 56_0402_5%

1 2

R134 56_0402_5%

1 2

+3VS

from EFL50

2
3
8
7

1

G

3

1

C383

0.1U_0402_16V4Z

2

U25

VDD1

D+

ALERT#

D-

THERM#

SCLK

GND

SDATA

ADM1032ARMZ MSOP 8P

+5VS

FAN1 Control and Tachometer

R350
0_1206_5%

1 2

10K_0402_5%

6

2

D

Q32

S

SI3456DV-T1_TSOP6

4 5

FAN1_POWER

1

1

2

C132

2

C135

22U_1206_10V4Z

+3V

C

Title

Size Document Number Rev

Custom

LA-3271P

Date: Sheet

+VCCP

Thermal Sensor
ADM1032

12

R348

10K_0402_5%@

1
6

THERM#

4
5

+3VS

12

R70

C133

0.01U_0402_16V7K

JFAN1

1
2
3

4

G

5

G

MOLEX_53398-0371~N

FAN1

1 2

YONAH

FAN_SPEED1 26

H_PROCHOT#

1

2

1

1000P_0402_50V7K~N

12

R93

Level shifter

@

330_0603_5%

H_PROCHOT_SIO#

2

B

R88 56_0402_5%@

E

Q15

@

3 1

MMBT3904_SOT23

1 2

R92 56_0402_5%

H_PROCHOT#

Compal Electronics, Inc.

+VCCP

+VCCP

442Monday, August 21, 2006

0.4

of

A

B

C

D

E

+VCCP

12

V_CPU_GTLREF

4 4

R77
1K_0402_1%

12

R72
2K_0402_1%

Close to CPU pin AD26
within 0.5 inch

CPU_BSEL CPU_BSEL2 CPU_BSEL1

133

166

3 3

2 2

00

0

+CPU_CORE

Close to CPU pin
within 500mils.

CPU_BSEL0

1

R368
100_0402_1%

1 2

R389
100_0402_1%

1 2

1

1

12

R84

27.4_0402_1%

VCCSENSE

VSSSENSE

12

R83

54.9_0402_1%

R394

27.4_0402_1%

Length match within 25 mils
The trace width 18 mils space
7 mils

+1.5VS

1

1

C140

12

0.01U_0402_16V7K

Resistor placed within

12

0.5" of CPU pin.Trace

should be at least 25

mils away from any

R395

other toggling signal.

54.9_0402_1%

2

2

VCCSENSE37
VSSSENSE37

C134
10U_0805_10V4Z~N

H_PSI#37

CPU_VID037
CPU_VID137
CPU_VID237
CPU_VID337
CPU_VID437
CPU_VID537
CPU_VID637

V_CPU_GTLREF

CPU_BSEL013
CPU_BSEL113
CPU_BSEL213

+CPU_CORE

+VCCP

VCCSENSE
VSSSENSE

H_PSI#
CPU_VID0

CPU_VID1
CPU_VID2
CPU_VID3
CPU_VID4
CPU_VID5
CPU_VID6

CPU_BSEL0
CPU_BSEL1
CPU_BSEL2

COMP0
COMP1
COMP2
COMP3

JP2B

AF7

VCCSENSE

AE7

VSSSENSE

B26

VCCA

K6

VCCP

J6

VCCP

M6

VCCP

N6

VCCP

YONAH

VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP

PSI#
VID0

VID1
VID2
VID3
VID4
VID5
VID6

GTLREF
BSEL0

BSEL1
BSEL2

COMP0
COMP1
COMP2
COMP3

VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC

RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD

FOX_PZ47823-2743-41_YONAH

W21

AD6

AD26

AB20
AA20

AF20
AE20
AB18
AB17
AA18
AA17
AD18
AD17
AC18
AC17

AF18

AF17

K21
M21

N21
R21

V21

G21

AE6

AF5
AE5
AF4
AE3
AF2
AE2

B22
B23
C21

R26
U26

AF1
D22
C23
C24
AA1
AA4
AB2
AA3

B25

T6
R6

J21

T21

V6

U1
V1

E7

D2
F6
D3
C1

M4
N5
T2

V3
B2

C3

T22

AB26

VSS

AA25

VSS

AD25

VSS

AE26

VSS

AB23

VSS

AC24

VSS

AF24

VSS

AE23

VSS

AA22

VSS

AD22

VSS

AC21

VSS

AF21

VSS

AB19

VSS

AA19

VSS

AD19

VSS

AC19

VSS

AF19

VSS

AE19

VSS

AB16

VSS

AA16

VSS

AD16

VSS

AC16

VSS

AF16

VSS

AE16

VSS

AB13

VSS

AA14

VSS

AD13

VSS

AC14

VSS

AF13

VSS

AE14

VSS

AB11

VSS

AA11

VSS

AD11

VSS

AC11

VSS

AF11

VSS

AE11

VSS

AB8

VSS

AA8

VSS

AD8

VSS

AC8

VSS

AF8

VSS

AE8

VSS

AA5

VSS

AD5

VSS

AC6

VSS

AF6

VSS

AB4

VSS

AC3

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

AF3
AE4
AB1
AA2
AD2
AE1
B6
C5
F5
E6
H6
J5
M5
L6
P6
R5
V5
U6
Y6
A4
D4
E3
H3
G4
K4
L3
P3
N4
T4
U3
Y3
W4
D1
C2
F2
G1

POWER, GROUNG, RESERVED SIGNALS AND NC

+CPU_CORE

JP2C

AE18

VCC

AE17

VCC

AB15

VCC

AA15

VCC

AD15

VCC

AC15

VCC

AF15

VCC

AE15

VCC

AB14

VCC

AA13

VCC

AD14

VCC

AC13

VCC

AF14

VCC

AE13

VCC

AB12

VCC

AA12

VCC

AD12

VCC

AC12

VCC

AF12

VCC

AE12

VCC

AB10

VCC

AB9

VCC

AA10

VCC

AA9

VCC

AD10

VCC

AD9

VCC

AC10

VCC

AC9

VCC

AF10

VCC

AF9

VCC

AE10

AE9
AB7
AA7
AD7
AC7

D18
D17
C18
C17

D15
C15

D14
C13

D12
C12

D10
C10

B20
A20
F20
E20
B18
B17
A18
A17

F18
F17
E18
E17
B15
A15

F15
E15
B14
A13

F14
E13
B12
A12

F12
E12
B10

A10

F10
E10

POWER, GROUND

VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC

B9

VCC
VCC

A9

VCC
VCC

D9

VCC
VCC

C9

VCC
VCC

F9

VCC
VCC

E9

VCC

B7

VCC

A7

VCC

F7

VCC

FOX_PZ47823-2743-41_YONAH

YONAH

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

K1
J2
M2
N1
T1
R2
V2
W1
A26
D26
C25
F25
B24
A23
D23
E24
B21
C22
F22
E21
B19
A19
D19
C19
F19
E19
B16
A16
D16
C16
F16
E16
B13
A14
D13
C14
F13
E14
B11
A11
D11
C11
F11
E11
B8
A8
D8
C8
F8
E8
G26
K26
J25
M25
N26
T26
R25
V25
W26
H24
G23
K23
L24
P24
N23
T23
U24
Y24
W23
H21
J22
M22
L21
P21
R22
V22
U21
Y21

1 1

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2005/12/1 2006/12/01

C

Compal Secret Data

Deciphered Date

Title

AMD CPU DDRII MEMORY I/F

Size Document Number Rev

Custom

LA-3271P

D

Date: Sheet

542Monday, August 21, 2006

E

0.4

of

5

D D

4

3

2

1

+CPU_CORE

1

proadlizer 1200uF

C C

South Side Secondary

C171

+VCCP

1

+

2

B B

330U_D2E_2.5VM_R9

@

2

+

C167
1200P_PFAF250E128MNTTE_2.5VM

3 4

1

C174

0.1U_0402_16V4Z

2

+CPU_CORE

1

+

C399

2

330U_D2E_2.5VM_R9

7mOhm
PS CAP

1

C175

0.1U_0402_16V4Z

2

C161

@

330U_D2E_2.5VM_R9

7mOhm
PS CAP

1

+

2

C397

@

330U_D2E_2.5VM_R9

7mOhm
PS CAP

1

C173

0.1U_0402_16V4Z

2

1

1

7mOhm
PS CAP

1

2

1

+

C168

2

@

330U_D2E_2.5VM_R9

7mOhm
PS CAP

C150

0.1U_0402_16V4Z

C400

330U_D2E_2.5VM_R9

+

2

7mOhm
PS CAP

C394

@

330U_D2E_2.5VM_R9

1

C152

0.1U_0402_16V4Z

2

+

North Side Secondary

2

1

C151

0.1U_0402_16V4Z

2

1

+

2

Mid Frequence Decoupling

ESR <= 1.5m ohm
Capacitor > 1980uF

Place these inside
socket cavity on L8
(North side
Secondary)

330U ?

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/12/1 2006/12/01

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

Compal Electronics, Inc.

ATHLON64 CTRL & DEBUG

LA-3271P

1

642Monday, August 21, 2006

0.4

of

5

DDR_A_DQS#[0..7]10

DDR_A_D[0..63]10

DDR_A_DM[0..7]10
DDR_A_DQS[0..7]10
DDR_A_MA[0..13]10

D D

Layout Note:
Place near JP41

+1.8V

0.1U_0402_16V4Z

0.1U_0402_16V4Z

C119

1

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

2

2

C103

C106

DDR_CKE0_DIMMA
DDR_A_BS#2

DDR_A_MA11
DDR_A_MA7

DDR_A_MA12
DDR_A_MA9

DDR_A_MA2
DDR_A_MA4

DDR_A_MA0
DDR_A_BS#1

M_ODT0
DDR_A_MA13

DDR_A_MA6
DDR_CKE1_DIMMA

0.1U_0402_16V4Z

C89

1

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

2

C117

1

2

C76

2.2U_0603_6.3V6K

+0.9VS

C105

1

2

0.1U_0402_16V4Z

1

2

C94

2.2U_0603_6.3V6K
C125

1

2

0.1U_0402_16V4Z

1

2

C88

RP26 56_0404_4P2R_5%

14
23

RP21 56_0404_4P2R_5%

14
23

RP22 56_0404_4P2R_5%

14
23

RP17 56_0404_4P2R_5%

14
23

RP13 56_0404_4P2R_5%

14
23

RP4 56_0404_4P2R_5%

14
23

RP25 56_0404_4P2R_5%

14
23

2.2U_0603_6.3V6K

0.1U_0402_16V4Z

1

2

1

2

C62

RP18

RP14

RP9

RP10

RP6

RP2

2.2U_0603_6.3V6K

C77

1

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

2

C75

1 4
2 3

56_0404_4P2R_5%

1 4
2 3

56_0404_4P2R_5%

1 4
2 3

56_0404_4P2R_5%

1 4
2 3

56_0404_4P2R_5%

1 4
2 3

56_0404_4P2R_5%

2 3
1 4

56_0404_4P2R_5%

5

C83

2.2U_0603_6.3V6K
C124

1

2

C C

Layout Note:
Place one cap close to every 2 pullup
resistors terminated to +0.9VS

+0.9VS

0.1U_0402_16V4Z

1

2

C139

B B

DDR_A_MA5
DDR_A_MA8

DDR_A_MA3
DDR_A_MA1

DDR_A_RAS#
DDR_CS0_DIMMA#

DDR_A_MA10
DDR_A_BS#0

DDR_A_WE#
DDR_A_CAS#

A A

DDR_CS1_DIMMA#
M_ODT1

0.1U_0402_16V4Z

C99

1

1

2

2

0.1U_0402_16V4Z

1

1

2

2

C110

C126

Layout Note:
Place these resistor
closely JP41,all
trace length Max=1.5"

4

C93

DDR_CKE0_DIMMA9

DDR_A_BS#210

DDR_A_BS#010

DDR_A_WE#10

DDR_A_CAS#10

C130

DDR_CS1_DIMMA#9

M_ODT19

CLK_SMBDATA8,13

CLK_SMBCLK8,13

+3VS

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

2

2

C122

DDR_A_D4
DDR_A_D1

DDR_A_DQS#0
DDR_A_DQS0

DDR_A_D2
DDR_A_D3

DDR_A_D8
DDR_A_D14

DDR_A_DQS#1
DDR_A_DQS1

DDR_A_D9

DDR_A_D16
DDR_A_D17

DDR_A_DQS#2
DDR_A_DQS2

DDR_A_D18
DDR_A_D19

DDR_A_D29
DDR_A_D24

DDR_A_DM3

DDR_A_D26
DDR_A_D27

DDR_CKE0_DIMMA

DDR_A_BS#2
DDR_A_MA12
DDR_A_MA8
DDR_A_MA5

DDR_A_MA3
DDR_A_MA1

DDR_A_MA10
DDR_A_BS#0

DDR_A_CAS#
DDR_CS1_DIMMA#

M_ODT1
DDR_A_D37

DDR_A_D36
DDR_A_DQS#4

DDR_A_DQS4
DDR_A_D35

DDR_A_D34
DDR_A_D40

DDR_A_D44
DDR_A_DM5
DDR_A_D41

DDR_A_D46
DDR_A_D49

DDR_A_D48

DDR_A_DQS#6
DDR_A_DQS6

DDR_A_D54
DDR_A_D50

DDR_A_D61
DDR_A_D60

DDR_A_DM7
DDR_A_D59

DDR_A_D58
CLK_SMBDATA

CLK_SMBCLK

1

C39

2

3

+1.8V

1

C42

2.2U_0603_6.3V6K

2

JDIM1

1

VREF

3

VSS

5

DQ0

7

DQ1

9

VSS

11

DQS0#

13

DQS0

15

VSS

17

DQ2

19

DQ3

21

VSS

23

DQ8

25

DQ9

27

VSS

29

DQS1#

31

DQS1

33

VSS

35

DQ10

37

DQ11

39

VSS

41

VSS

43

DQ16

45

DQ17

47

VSS

49

DQS2#

51

DQS2

53

VSS

55

DQ18

57

DQ19

59

VSS

61

DQ24

63

DQ25

65

VSS

67

DM3

69

NC

71

VSS

73

DQ26

75

DQ27

77

VSS

79

CKE0

81

VDD

83

NC

85

BA2

87

VDD

89

A12

91

A9

93

A8

95

VDD

97

A5

99

A3

101

A1

103

VDD

105

A10/AP

107

BA0

109

WE#

111

VDD

113

CAS#

115

NC/S1#

117

VDD

119

NC/ODT1

121

VSS

123

DQ32

125

DQ33

127

VSS

129

DQS4#

131

DQS4

133

VSS

135

DQ34

137

DQ35

139

VSS

141

DQ40

143

DQ41

145

VSS

147

DM5

149

VSS

151

DQ42

153

DQ43

155

VSS

157

DQ48

159

DQ49

161

VSS

163

NC,TEST

165

VSS

167

DQS6#

169

DQS6

171

VSS

173

DQ50

175

DQ51

177

VSS

179

DQ56

181

DQ57

183

VSS

185

DM7

187

VSS

189

DQ58

191

DQ59

193

VSS

195

SDA

197

SCL

199

VDDSPD

P-TWO_A5692C-A0G16

SO-DIMM A

REVERSE

DQ12
DQ13

CK0#

DQ14
DQ15

DQ20
DQ21

DQ22
DQ23

DQ28
DQ29

DQS3#

DQS3
DQ30

DQ31

NC/CKE1

NC/A15
NC/A14

RAS#

ODT0

NC/A13

DQ36
DQ37

DQ38
DQ39

DQ44
DQ45

DQS5#

DQS5
DQ46

DQ47
DQ52

DQ53

CK1#

DQ54
DQ55

DQ60
DQ61

DQS7#

DQS7
DQ62

DQ63

VSS
DQ4
DQ5
VSS
DM0
VSS
DQ6
DQ7
VSS

VSS
DM1
VSS
CK0

VSS

VSS

VSS

VSS
DM2

VSS

VSS

VSS

VSS

VSS
VDD

VDD

VDD

VDD
BA1

VDD

VDD
VSS

VSS
DM4
VSS

VSS

VSS

VSS

VSS

VSS
CK1

VSS
DM6
VSS

VSS

VSS

VSS

VSS
SAO
SA1

2

+1.8V

V_DDR_MCH_REF

2

DDR_A_D6

4

DDR_A_D0

6
8

DDR_A_DM0

10
12

DDR_A_D5

14

DDR_A_D7

16
18

DDR_A_D13

20

DDR_A_D12

22
24

DDR_A_DM1

26
28

M_CLK_DDR0

30

M_CLK_DDR#0

32
34

DDR_A_D11

36

DDR_A_D10DDR_A_D15

38
40

42

DDR_A_D20

44

DDR_A_D21

46
48
50

NC

A11

A7
A6

A4
A2
A0

S0#

NC

52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200

DDR_A_DM2
DDR_A_D23

DDR_A_D22
DDR_A_D28

DDR_A_D25
DDR_A_DQS#3

DDR_A_DQS3
DDR_A_D31

DDR_A_D30
DDR_CKE1_DIMMA

DDR_A_MA11
DDR_A_MA7DDR_A_MA9
DDR_A_MA6

DDR_A_MA4
DDR_A_MA2
DDR_A_MA0

DDR_A_BS#1
DDR_A_RAS#
DDR_CS0_DIMMA#DDR_A_WE#

M_ODT0
DDR_A_MA13

DDR_A_D32
DDR_A_D33

DDR_A_DM4
DDR_A_D39

DDR_A_D38
DDR_A_D45

DDR_A_D43
DDR_A_DQS#5

DDR_A_DQS5
DDR_A_D47

DDR_A_D42
DDR_A_D52

DDR_A_D53
M_CLK_DDR1

M_CLK_DDR#1
DDR_A_DM6
DDR_A_D51

DDR_A_D55
DDR_A_D57

DDR_A_D56
DDR_A_DQS#7

DDR_A_DQS7
DDR_A_D62

DDR_A_D63

12

R34

10K_0402_5%

Close to VREF pins of SO-DIMM

2.2U_0805_16V4Z

M_CLK_DDR0 9
M_CLK_DDR#0 9

R89 0_0402_5%

DDR_CKE1_DIMMA 9

DDR_A_BS#1 10
DDR_A_RAS# 10
DDR_CS0_DIMMA# 9

M_ODT0 9

M_CLK_DDR1 9
M_CLK_DDR#1 9

12

R35

10K_0402_5%

0.1U_0402_16V4Z

C159

1

2

C166

1

2

Close to connect

12

PM_EXTTS#0 8,9

1

V_DDR_MCH_REF 8,9

V_DDR_MCH_REF

1

C156

2

@

0.1U_0402_16V4Z

+1.8V

12

R113

100_0402_1%@

12

R114

100_0402_1%@

Top side

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2005/12/1 2006/12/01

3

Compal Secret Data

Deciphered Date

Title

DDR2 SO-DIMM I

Size Document Number Rev

Custom

LA-3271P

2

Date: Sheet

742Monday, August 21, 2006

1

0.4

of

5

DDR_B_DQS#[0..7]10

DDR_B_D[0..63]10

DDR_B_DM[0..7]10
DDR_B_DQS[0..7]10
DDR_B_MA[0..13]10

D D

Layout Note:
Place near JP42

+1.8V

2.2U_0603_6.3V6K

2.2U_0603_6.3V6K

C121

C82

1

1

2

2

C C

Layout Note:
Place one cap close to every 2 pullup
resistors terminated to +0.9VS

+0.9VS

1

2

C107

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

2

C91

RP16

RP11

RP12

RP8

RP7

RP3

0.1U_0402_16V4Z

B B

DDR_B_MA1
DDR_B_MA3

DDR_B_MA10
DDR_B_BS#0

DDR_B_MA0
DDR_B_BS#1

DDR_B_RAS#
DDR_CS2_DIMMB#

DDR_B_CAS#
DDR_B_WE#

A A

DDR_CS3_DIMMB#
M_ODT3

2.2U_0603_6.3V6K
C128

1

2

0.1U_0402_16V4Z

1

2

C95

1 4
2 3

56_0404_4P2R_5%

1 4
2 3

56_0404_4P2R_5%

1 4
2 3

56_0404_4P2R_5%

1 4
2 3

56_0404_4P2R_5%

1 4
2 3

56_0404_4P2R_5%

2 3
1 4

56_0404_4P2R_5%

5

1

2

C80

2.2U_0603_6.3V6K

+0.9VS

C102

1

2

0.1U_0402_16V4Z

1

2

C79

2.2U_0603_6.3V6K
C84

1

2

0.1U_0402_16V4Z

1

2

C68

RP23 56_0404_4P2R_5%

14
23

RP24 56_0404_4P2R_5%

14
23

RP20 56_0404_4P2R_5%

14
23

RP19 56_0404_4P2R_5%

14
23

RP15 56_0404_4P2R_5%

14
23

RP5 56_0404_4P2R_5%

14
23

RP27

14
23

56_0404_4P2R_5%

0.1U_0402_16V4Z
C115

1

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

2

2

C67

DDR_B_MA12
DDR_B_MA9

DDR_CKE3_DIMMB
DDR_B_MA11

DDR_B_MA5
DDR_B_MA8

DDR_B_MA7
DDR_B_MA6

DDR_B_MA4
DDR_B_MA2

DDR_B_MA13
M_ODT2

DDR_CKE2_DIMMB
DDR_B_BS#2

0.1U_0402_16V4Z

C129

0.1U_0402_16V4Z

C100

1

2

0.1U_0402_16V4Z

1

2

C123

0.1U_0402_16V4Z

C90

1

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

2

C127

Layout Note:
Place these resistor
closely JP42,all
trace length Max=1.5"

4

C92

1

2

DDR_CKE2_DIMMB9

DDR_B_BS#210

DDR_B_BS#010

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

2

C108

1

1

2

2

C104

C118

DDR_B_WE#10

DDR_B_CAS#10

DDR_CS3_DIMMB#9

M_ODT39

CLK_SMBDATA7,13

CLK_SMBCLK7,13

0.1U_0402_16V4Z

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

+1.8V

JDIM2

1

VREF

3

DDR_B_D0
DDR_B_D1

DDR_B_DQS#0
DDR_B_DQS0

DDR_B_D2
DDR_B_D3

DDR_B_D8
DDR_B_D9

DDR_B_DQS#1
DDR_B_DQS1

DDR_B_D10
DDR_B_D11

DDR_B_D17
DDR_B_D20

DDR_B_DQS#2
DDR_B_DQS2

DDR_B_D18
DDR_B_D19

DDR_B_D28
DDR_B_D25

DDR_B_DM3

DDR_B_D30
DDR_B_D31

DDR_CKE2_DIMMB

DDR_B_BS#2
DDR_B_MA12

DDR_B_MA9
DDR_B_MA8

DDR_B_MA5
DDR_B_MA3
DDR_B_MA1

DDR_B_MA10
DDR_B_BS#0
DDR_B_WE#

DDR_B_CAS#
DDR_CS3_DIMMB#

M_ODT3
DDR_B_D32

DDR_B_D33
DDR_B_DQS#4

DDR_B_DQS4
DDR_B_D34

DDR_B_D35
DDR_B_D40

DDR_B_D41
DDR_B_DM5
DDR_B_D42

DDR_B_D43
DDR_B_D48

DDR_B_D49

DDR_B_DQS#6
DDR_B_DQS6

DDR_B_D51
DDR_B_D50

DDR_B_D56
DDR_B_D61 DDR_B_D57

DDR_B_DM7
DDR_B_D59

DDR_B_D58
CLK_SMBDATA

CLK_SMBCLK

+3VS

1

2

1

C43

2.2U_0603_6.3V6K

2

C38

2005/12/1 2006/12/01

3

VSS

5

DQ0

7

DQ1

9

VSS

11

DQS0#

13

DQS0

15

VSS

17

DQ2

19

DQ3

21

VSS

23

DQ8

25

DQ9

27

VSS

29

DQS1#

31

DQS1

33

VSS

35

DQ10

37

DQ11

39

VSS

41

VSS

43

DQ16

45

DQ17

47

VSS

49

DQS2#

51

DQS2

53

VSS

55

DQ18

57

DQ19

59

VSS

61

DQ24

63

DQ25

65

VSS

67

DM3

69

NC

71

VSS

73

DQ26

75

DQ27

77

VSS

79

CKE0

81

VDD

83

NC

85

BA2

87

VDD

89

A12

91

A9

93

A8

95

VDD

97

A5

99

A3

101

A1

103

VDD

105

A10/AP

107

BA0

109

WE#

111

VDD

113

CAS#

115

NC/S1#

117

VDD

119

NC/ODT1

121

VSS

123

DQ32

125

DQ33

127

VSS

129

DQS4#

131

DQS4

133

VSS

135

DQ34

137

DQ35

139

VSS

141

DQ40

143

DQ41

145

VSS

147

DM5

149

VSS

151

DQ42

153

DQ43

155

VSS

157

DQ48

159

DQ49

161

VSS

163

NC,TEST

165

VSS

167

DQS6#

169

DQS6

171

VSS

173

DQ50

175

DQ51

177

VSS

179

DQ56

181

DQ57

183

VSS

185

DM7

187

VSS

189

DQ58

191

DQ59

193

VSS

195

SDA

197

SCL

199

VDDSPD

P-TWO_A5652C-A0G16

SO-DIMM B

CONN@

STANDARD

Bottom side

Compal Secret Data

Deciphered Date

DQ12
DQ13

CK0#

DQ14
DQ15

DQ20
DQ21

DQ22
DQ23

DQ28
DQ29

DQS3#

DQS3
DQ30

DQ31

NC/CKE1

NC/A15
NC/A14

RAS#

ODT0

NC/A13

DQ36
DQ37

DQ38
DQ39

DQ44
DQ45

DQS5#

DQS5
DQ46

DQ47
DQ52

DQ53

CK1#

DQ54
DQ55

DQ60
DQ61

DQS7#

DQS7
DQ62

DQ63

VSS
DQ4
DQ5
VSS
DM0
VSS
DQ6
DQ7
VSS

VSS
DM1
VSS
CK0

VSS

VSS

VSS

VSS
DM2

VSS

VSS

VSS

VSS

VSS
VDD

VDD

VDD

VDD
BA1

VDD

VDD
VSS

VSS
DM4
VSS

VSS

VSS

VSS

VSS

VSS
CK1

VSS
DM6
VSS

VSS

VSS

VSS

VSS
SAO
SA1

NC

A11

A7
A6

A4
A2
A0

S0#

NC

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200

2

+1.8V

V_DDR_MCH_REF

DDR_B_D5
DDR_B_D4

DDR_B_DM0
DDR_B_D6

DDR_B_D7
DDR_B_D12

DDR_B_D13
DDR_B_DM1
M_CLK_DDR3

M_CLK_DDR#3
DDR_B_D14

DDR_B_D15

DDR_B_D21
DDR_B_D16

DDR_B_DM2
DDR_B_D22

DDR_B_D23
DDR_B_D26

DDR_B_D24
DDR_B_DQS#3

DDR_B_DQS3
DDR_B_D29

DDR_B_D27
DDR_CKE3_DIMMB

DDR_B_MA11
DDR_B_MA7
DDR_B_MA6

DDR_B_MA4
DDR_B_MA2
DDR_B_MA0

DDR_B_BS#1
DDR_B_RAS#
DDR_CS2_DIMMB#

M_ODT2
DDR_B_MA13

DDR_B_D36
DDR_B_D37

DDR_B_DM4
DDR_B_D39

DDR_B_D38
DDR_B_D44

DDR_B_D45
DDR_B_DQS#5

DDR_B_DQS5
DDR_B_D46

DDR_B_D47
DDR_B_D52

DDR_B_D53
M_CLK_DDR2

M_CLK_DDR#2
DDR_B_DM6
DDR_B_D54

DDR_B_D55
DDR_B_D60

DDR_B_DQS#7
DDR_B_DQS7

DDR_B_D62
DDR_B_D63

2

1

Close to VREF pins of SO-DIMM

2.2U_0805_16V4Z

0.1U_0402_16V4Z

1

1

C149

C155

2

2

M_CLK_DDR3 9
M_CLK_DDR#3 9

12

R90 0_0402_5%

DDR_CKE3_DIMMB 9

DDR_B_BS#1 10
DDR_B_RAS# 10
DDR_CS2_DIMMB# 9

M_ODT2 9

M_CLK_DDR2 9
M_CLK_DDR#2 9

R31

1 2

10K_0402_5%

12

10K_0402_5%

R32

Title

DDR2 SO-DIMM II

Size Document Number Rev

Custom

LA-3271P

Date: Sheet

PM_EXTTS#0 7,9

+3VS

V_DDR_MCH_REF 7,9

1

0.4

of

842Monday, August 21, 2006

5

H_D#[0..63]4

D D

C C

+VCCP

12

12

R335

54.9_0402_1%

+VCCP

R51

R53

12

R336

24.9_0402_1%

12

100_0402_1%

12

200_0402_1%

R38

54.9_0402_1%

B B

A A

H_D#0
H_D#1
H_D#2
H_D#3
H_D#4 CFG3
H_D#5 CFG4
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63

H_VREF
H_XRCOMP
H_XSCOMP
H_YRCOMP
H_YSCOMP
H_SWNG0
H_SWNG1

12

R41

24.9_0402_1%

Layout Note:
H_XRCOMP / H_YRCOMP / H_VREF / H_SWNG0 /
H_SWNG1 trace width and spacing is 10/20.

H_VREF

1

C57

2

0.1U_0402_16V4Z

5

K11
T10

W11

U11
T11

AB7
AA9

Y10
AB8

AA4
AA7
AA2
AA6

AA10

AA1
AB4

AC9
AB11
AC11

AB3

AC2

AD1

AD9

AC1

AD7

AC6

AB5
AD10

AD4

AC8

J13

K13

U23A

F1

HD0#

J1

HD1#

H1

HD2#

J6

HD3#

H3

HD4#

K2

HD5#

G1

HD6#

G2

HD7#

K9

HD8#

K1

HD9#

K7

HD10#

J8

HD11#

H4

HD12#

J3

HD13#
HD14#

G4

HD15#
HD16#
HD17#

T3

HD18#

U7

HD19#

U9

HD20#
HD21#
HD22#

W9

HD23#

T1

HD24#

T8

HD25#

T4

HD26#

W7

HD27#

U5

HD28#

T9

HD29#

W6

HD30#

T5

HD31#
HD32#
HD33#

W4

HD34#

W3

HD35#

Y3

HD36#

Y7

HD37#

W5

HD38#
HD39#
HD40#

W2

HD41#
HD42#
HD43#
HD44#
HD45#
HD46#

Y8

HD47#
HD48#
HD49#
HD50#
HD51#
HD52#
HD53#
HD54#
HD55#
HD56#
HD57#
HD58#
HD59#
HD60#
HD61#
HD62#
HD63#

HVREF0
HVREF1

E1

HXRCOMP

E2

HXSCOMP

Y1

HYRCOMP

U1

HYSCOMP

E4

HXSWING

W1

HYSWING

CALISTOGA_FCBGA1466~D

<BOM Structure>

H9

HA3#

C9

HA4#

E11

HA5#

G11

HA6#

F11

HA7#

G12

HA8#

F9

HA9#

H11

HA10#

J12

HA11#

G14

HA12#

D9

HA13#

J14

HA14#

H13

HA15#

J15

HA16#

F14

HA17#

D12

HA18#

A11

HA19#

C11

HA20#

A12

HA21#

A13

HA22#

E13

HA23#

G13

HA24#

F12

HA25#

B12

HA26#

B14

HA27#

C12

HA28#

A14

HA29#

C14

HA30#

D14

HA31#

D8

HREQ#0

G8

HREQ#1

B8

HREQ#2

F8

HREQ#3

A8

HREQ#4

B9

HADSTB#0

C13

HADSTB#1

HCLKN
HCLKP

HDSTBN#0
HDSTBN#1
HDSTBN#2
HDSTBN#3
HDSTBP#0
HDSTBP#1
HDSTBP#2
HDSTBP#3

HDINV#0
HDINV#1
HDINV#2
HDINV#3

HCPURST#

HADS#

HTRDY#

HDPWR#

HDRDY#

HDEFER#

HHITM#

HHIT#

HLOCK#

HBREQ0#

HBNR#

HBPRI#

HDBSY#

HCPUSLP#

HRS0#
HRS1#
HRS2#

12

R43

12

R45

AG1
AG2

K4
T7
Y5
AC4
K3
T6
AA5
AC5

J7
W8
U3
AB10

B7
E8
E7
J9
H8
C3
D4
D3
B3
C7
C6
F6
A7
E3

B4
E6
D6

221_0603_1%

100_0402_1%

HOST

4

+VCCP+VCCP

R33

R42

H_A#[3..31] 4

H_REQ#[0..4] 4

H_ADSTB#0 4
H_ADSTB#1 4

CLK_MCH_BCLK# 13
CLK_MCH_BCLK 13
H_DSTBN#[0..3] 4

H_DSTBP#[0..3] 4

H_DINV#0 4
H_DINV#1 4
H_DINV#2 4
H_DINV#3 4

H_RESET# 4
H_ADS# 4
H_TRDY# 4
H_DPWR# 4
H_DRDY# 4
H_DEFER# 4
H_HITM# 4
H_HIT# 4
H_LOCK# 4
H_BR0# 4
H_BNR# 4
H_BPRI# 4
H_DBSY# 4
H_CPUSLP# 4,16

H_RS#[0..2] 4

12

221_0603_1%

12

100_0402_1%

H_SWNG1

1

2

+1.8V

R47 80.6_0402_1%
R46 80.6_0402_1%

PLT_RST#15,17,22,23,26

V_DDR_MCH_REF7,8

C44

0.1U_0402_16V4Z

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4 DDR_CKE1_DIMMA

H_ADSTB#0
H_ADSTB#1

CLK_MCH_BCLK#
CLK_MCH_BCLK

H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3
H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3

H_DINV#0
H_DINV#1
H_DINV#2
H_DINV#3

H_RESET#
H_ADS#
H_TRDY#
H_DPWR#
H_DRDY#
H_DEFER#
H_HITM#
H_HIT#
H_LOCK#
H_BR0#
H_BNR#
H_BPRI#
H_DBSY#
H_CPUSLP#

H_RS#0
H_RS#1
H_RS#2

H_SWNG0

1

C52

2

0.1U_0402_16V4Z

3

1

2

DMI_TXN0
DMI_TXN1
DMI_TXN2
DMI_TXN3

DMI_TXP0
DMI_TXP1
DMI_TXP2
DMI_TXP3

DMI_RXN0
DMI_RXN1
DMI_RXN2
DMI_RXN3

DMI_RXP0
DMI_RXP1
DMI_RXP2
DMI_RXP3

M_CLK_DDR1
M_CLK_DDR2
M_CLK_DDR3

M_CLK_DDR#0
M_CLK_DDR#1
M_CLK_DDR#2

M_CLK_DDR#3
DDR_CKE0_DIMMA
DDR_CKE2_DIMMB

DDR_CKE3_DIMMB

DDR_CS0_DIMMA#
DDR_CS1_DIMMA#
DDR_CS2_DIMMB#
DDR_CS3_DIMMB#

M_OCDOCMP0

M_OCDOCMP1

M_ODT0

M_ODT1

M_ODT2

M_ODT3

SMRCOMPN

SMRCOMPP

PM_BMBUSY#
PM_EXTTS#0
PM_EXTTS#1
H_THERMTRIP#
NB_PWRGD
PLTRST_R#

12

+1.8V

DMI_TXN017
DMI_TXN117
DMI_TXN217
DMI_TXN317

DMI_TXP017
DMI_TXP117
DMI_TXP217
DMI_TXP317

DMI_RXN017
DMI_RXN117
DMI_RXN217
DMI_RXN317

DMI_RXP017
DMI_RXP117
DMI_RXP217
DMI_RXP317

M_CLK_DDR07
M_CLK_DDR17
M_CLK_DDR28
M_CLK_DDR38

M_CLK_DDR#07
M_CLK_DDR#17
M_CLK_DDR#28
M_CLK_DDR#38

DDR_CKE0_DIMMA7
DDR_CKE1_DIMMA7
DDR_CKE2_DIMMB8
DDR_CKE3_DIMMB8

DDR_CS0_DIMMA#7
DDR_CS1_DIMMA#7
DDR_CS2_DIMMB#8
DDR_CS3_DIMMB#8

M_ODT07
M_ODT17
M_ODT28
M_ODT38

1 2
1 2

V_DDR_MCH_REF

PM_BMBUSY#17
PM_EXTTS#07,8
PM_EXTTS#1

H_THERMTRIP#4,16

NB_PWRGD15

R76 100_0402_1%

MCH_ICH_SYNC#15

Layout Note:
V_DDR_MCH_REF
trace width and
spacing is 20/20.

V_DDR_MCH_REF

C47

0.1U_0402_16V4Z

Stuff R286 & R281 for A1 Calistoga

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

U23B

AE35

DMIRXN0

AF39

DMIRXN1

AG35

DMIRXN2

AH39

DMIRXN3

AC35

DMIRXP0

AE39

DMIRXP1

AF35
AG39

AE37
AF41
AG37
AH41

AC37
AE41
AF37
AG41

AY35

AR1

AW7

AW40
AW35

AT1
AY7

AY40
AU20

AT20
BA29
AY29

AW13
AW12

AY21

AW21

AL20

AF10
BA13

BA12
AY20
AU21

AV9
AT9

AK1

AK41

G28

F25

H26

G6
AH33
AH34

K28

12

R40
100_0402_1%

12

R44
100_0402_1%

2005/12/1 2006/12/01

DMI

DMIRXP2
DMIRXP3

DMITXN0
DMITXN1
DMITXN2
DMITXN3

DMITXP0
DMITXP1
DMITXP2
DMITXP3

SM_CK0
SM_CK1
SM_CK2
SM_CK3

SM_CK0#
SM_CK1#
SM_CK2#
SM_CK3#

SM_CKE0
SM_CKE1
SM_CKE2
SM_CKE3

SM_CS0#
SM_CS1#
SM_CS2#
SM_CS3#

SM_OCDCOMP0
SM_OCDCOMP1

SM_ODT0
SM_ODT1
SM_ODT2
SM_ODT3

SM_RCOMPN
SM_RCOMPP

SM_VREF0
SM_VREF1

PM_BMBUSY#
PM_EXTTS0#
PM_EXTTS1#
PM_THERMTRIP#
PWROK
RSTIN#

ICH_SYNC#

CALISTOGA_FCBGA1466~D

<BOM Structure>

DDR MUXING

Layout Note:
Route as short
as possible

12

R59

40.2_0402_1%

@

Compal Secret Data

Deciphered Date

PM

R50

@

CFG

CLKNC

D_REF_SSCLKN
D_REF_SSCLKP

RESERVED

M_OCDOCMP0
M_OCDOCMP1

12

40.2_0402_1%

2

D_REF_CLKN
D_REF_CLKP

CLK_REQ#

RESERVED1
RESERVED2
RESERVED3
RESERVED4
RESERVED5
RESERVED6
RESERVED7
RESERVED8

RESERVED9
RESERVED10
RESERVED11
RESERVED12
RESERVED13

CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8

CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG16
CFG17
CFG18
CFG19
CFG20

G_CLKP
G_CLKN

NC0
NC1
NC2
NC3
NC4
NC5
NC6
NC7
NC8

NC9
NC10
NC11
NC12
NC13
NC14
NC15
NC16
NC17
NC18

R65

@

0_0402_5%

1 2

Description at page13.

MCH_CLKSEL0

K16

MCH_CLKSEL1

K18

MCH_CLKSEL2

J18
F18
E15

CFG5

F15

CFG6

E18

CFG7

D19

CFG8

D16

CFG9

G16

CFG10

E16

CFG11

D15

CFG12

G15

CFG13

K15

CFG14

C15

CFG15

H16

CFG16

G18

CFG17

H15

CFG18

J25

CFG19

K27

CFG20

J26

CLK_MCH_3GPLL

AG33

CLK_MCH_3GPLL#M_CLK_DDR0

AF33

CLK_MCH_DREFCLK#

A27

CLK_MCH_DREFCLK

A26

MCH_SSCDREFCLK#

C40

MCH_SSCDREFCLK

D41

CLKREQA#

H32

A3
A39
A4
A40
AW1
AW41
AY1
BA1
BA2
BA3
BA39
BA40
BA41
C1
AY41
B2
B41
C41
D1

T32
R32
F3
F7
AG11
AF11
H7
J19
A41
A34
D28
D27
A35

PM_EXTTS#0

PM_EXTTS#1

DPRSLPVR 17,37

Title

Size Document Number Rev

Custom

Date: Sheet

PAD
PAD
PAD
PAD

PAD
PAD

R67

10K_0402_5%

R66

@

10K_0402_5%

MCH_CLKSEL0 13
MCH_CLKSEL1 13
MCH_CLKSEL2 13
CFG3 12

T2

CFG5 12

T1

CFG7 12

T4

CFG9 12

T3

CFG11 12
CFG12 12

CFG13 12

T5
T7

CFG16 12

CFG17 12

CFG18 12

CFG19 12

CFG20 12

12

12

CLK_MCH_3GPLL 13
CLK_MCH_3GPLL# 13

CLK_MCH_DREFCLK# 13
CLK_MCH_DREFCLK 13

MCH_SSCDREFCLK# 13
MCH_SSCDREFCLK 13

CLKREQA# 13

+3VS

Calistoga(1)
LA-3271P

1

0.4

of

1

942Monday, August 21, 2006

DDR_A_BS#07
DDR_A_BS#17
DDR_A_BS#27

DDR_A_DM[0..7]7

DDR_A_DQS[0..7]7

DDR_A_DQS#[0..7]7

DDR_A_MA[0..13]7

DDR_A_CAS#7
DDR_A_RAS#7

DDR_A_WE#7

T9 PAD
T10 PAD

DDR_A_BS#0
DDR_A_BS#1
DDR_A_BS#2

DDR_A_DM0
DDR_A_DM1
DDR_A_DM2
DDR_A_DM3
DDR_A_DM4
DDR_A_DM5
DDR_A_DM6
DDR_A_DM7

DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7

DDR_A_DQS#0
DDR_A_DQS#1
DDR_A_DQS#2
DDR_A_DQS#3
DDR_A_DQS#4
DDR_A_DQS#5
DDR_A_DQS#6
DDR_A_DQS#7

DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13

DDR_A_CAS#
DDR_A_RAS#
DDR_A_WE#
SA_RCVENIN# SB_RCVENIN#
SA_RCVENOUT#

check layout check layout

U23D

AU12

SA_BS0

AV14

SA_BS1

BA20

SA_BS2

AJ33

SA_DM0

AM35

SA_DM1

AL26

SA_DM2

AN22

SA_DM3

AM14

SA_DM4

AL9

SA_DM5

AR3

SA_DM6

AH4

SA_DM7

AK33

SA_DQS0

AT33

SA_DQS1

AN28

SA_DQS2

AM22

SA_DQS3

AN12

SA_DQS4

AN8

SA_DQS5

AP3

SA_DQS6

AG5

SA_DQS7

AK32

SA_DQS0#

AU33

SA_DQS1#

AN27

SA_DQS2#

AM21

SA_DQS3#

AM12

SA_DQS4#

AL8

SA_DQS5#

AN3

SA_DQS6#

AH5

SA_DQS7#

AY16

SA_MA0

AU14

SA_MA1

AW16

SA_MA2

BA16

SA_MA3

BA17

SA_MA4

AU16

SA_MA5

AV17

SA_MA6

AU17

SA_MA7

AW17

SA_MA8

AT16

SA_MA9

AU13

SA_MA10

AT17

SA_MA11

AV20

SA_MA12

AV12

SA_MA13

AY13

SA_CAS#

AW14

SA_RAS#

AY14

SA_WE#

AK23

SA_RCVENIN#

AK24

SA_RCVENOUT#

CALISTOGA_FCBGA1466~D

<BOM Structure>

SA_DQ0
SA_DQ1
SA_DQ2
SA_DQ3
SA_DQ4
SA_DQ5
SA_DQ6
SA_DQ7
SA_DQ8

SA_DQ9
SA_DQ10
SA_DQ11
SA_DQ12
SA_DQ13
SA_DQ14
SA_DQ15
SA_DQ16
SA_DQ17
SA_DQ18
SA_DQ19
SA_DQ20
SA_DQ21
SA_DQ22
SA_DQ23
SA_DQ24
SA_DQ25
SA_DQ26
SA_DQ27
SA_DQ28
SA_DQ29
SA_DQ30
SA_DQ31
SA_DQ32
SA_DQ33
SA_DQ34
SA_DQ35
SA_DQ36
SA_DQ37
SA_DQ38
SA_DQ39

DDR SYS MEMORY A

SA_DQ40
SA_DQ41
SA_DQ42
SA_DQ43
SA_DQ44
SA_DQ45
SA_DQ46
SA_DQ47
SA_DQ48
SA_DQ49
SA_DQ50
SA_DQ51
SA_DQ52
SA_DQ53
SA_DQ54
SA_DQ55
SA_DQ56
SA_DQ57
SA_DQ58
SA_DQ59
SA_DQ60
SA_DQ61
SA_DQ62
SA_DQ63

AJ34
AM31
AM33
AJ36
AK35
AJ32
AH31
AN35
AP33
AR31
AP31
AN38
AM36
AM34
AN33
AK26
AL27
AM26
AN24
AK28
AL28
AM24
AP26
AP23
AL22
AP21
AN20
AL23
AP24
AP20
AT21
AR12
AR14
AP13
AP12
AT13
AT12
AL14
AL12
AK9
AN7
AK8
AK7
AP9
AN9
AT5
AL5
AY2
AW2
AP1
AN2
AV2
AT3
AN1
AL2
AG7
AF9
AG4
AF6
AG9
AH6
AF4
AF8

DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63

DDR_A_D0

AJ35

DDR_A_D[0..63] 7 DDR_B_D[0..63] 8

DDR_B_BS#08
DDR_B_BS#18
DDR_B_BS#28

DDR_B_DM[0..7]8

DDR_B_DQS[0..7]8

DDR_B_DQS#[0..7]8

DDR_B_MA[0..13]8

DDR_B_CAS#8
DDR_B_RAS#8

DDR_B_WE#8

T6 PAD
T8 PAD

DDR_B_BS#0
DDR_B_BS#1
DDR_B_BS#2

DDR_B_DM0
DDR_B_DM1
DDR_B_DM2
DDR_B_DM3
DDR_B_DM4
DDR_B_DM5
DDR_B_DM6
DDR_B_DM7

DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4
DDR_B_DQS5
DDR_B_DQS6
DDR_B_DQS7

DDR_B_DQS#0
DDR_B_DQS#1
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS#4
DDR_B_DQS#5
DDR_B_DQS#6
DDR_B_DQS#7

DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13

DDR_B_CAS#
DDR_B_RAS#
DDR_B_WE#

SB_RCVENOUT#

U23E

AT24

SB_BS0

AV23

SB_BS1

AY28

SB_BS2

AK36

SB_DM0

AR38

SB_DM1

AT36

SB_DM2

BA31

SB_DM3

AL17

SB_DM4

AH8

SB_DM5

BA5

SB_DM6

AN4

SB_DM7

AM39

SB_DQS0

AT39

SB_DQS1

AU35

SB_DQS2

AR29

SB_DQS3

AR16

SB_DQS4

AR10

SB_DQS5

AR7

SB_DQS6

AN5

SB_DQS7

AM40

SB_DQS0#

AU39

SB_DQS1#

AT35

SB_DQS2#

AP29

SB_DQS3#

AP16

SB_DQS4#

AT10

SB_DQS5#

AT7

SB_DQS6#

AP5

SB_DQS7#

AY23

SB_MA0

AW24

SB_MA1

AY24

SB_MA2

AR28

SB_MA3

AT27

SB_MA4

AT28

SB_MA5

AU27

SB_MA6

AV28

SB_MA7

AV27

SB_MA8

AW27

SB_MA9

AV24

SB_MA10

BA27

SB_MA11

AY27

SB_MA12

AR23

SB_MA13

AR24

SB_CAS#

AU23

SB_RAS#

AR27

SB_WE#

AK16

SB_RCVENIN#

AK18

SB_RCVENOUT#

CALISTOGA_FCBGA1466~D

<BOM Structure>

SB_DQ0
SB_DQ1
SB_DQ2
SB_DQ3
SB_DQ4
SB_DQ5
SB_DQ6
SB_DQ7
SB_DQ8

SB_DQ9
SB_DQ10
SB_DQ11
SB_DQ12
SB_DQ13
SB_DQ14
SB_DQ15
SB_DQ16
SB_DQ17
SB_DQ18
SB_DQ19
SB_DQ20
SB_DQ21
SB_DQ22
SB_DQ23
SB_DQ24
SB_DQ25
SB_DQ26
SB_DQ27
SB_DQ28
SB_DQ29
SB_DQ30
SB_DQ31
SB_DQ32
SB_DQ33
SB_DQ34
SB_DQ35
SB_DQ36
SB_DQ37
SB_DQ38
SB_DQ39

DDR SYS MEMORY B

SB_DQ40
SB_DQ41
SB_DQ42
SB_DQ43
SB_DQ44
SB_DQ45
SB_DQ46
SB_DQ47
SB_DQ48
SB_DQ49
SB_DQ50
SB_DQ51
SB_DQ52
SB_DQ53
SB_DQ54
SB_DQ55
SB_DQ56
SB_DQ57
SB_DQ58
SB_DQ59
SB_DQ60
SB_DQ61
SB_DQ62
SB_DQ63

AJ37
AP39
AR41
AJ38
AK38
AN41
AP41
AT40
AV41
AU38
AV38
AP38
AR40
AW38
AY38
BA38
AV36
AR36
AP36
BA36
AU36
AP35
AP34
AY33
BA33
AT31
AU29
AU31
AW31
AV29
AW29
AM19
AL19
AP14
AN14
AN17
AM16
AP15
AL15
AJ11
AH10
AJ9
AN10
AK13
AH11
AK10
AJ8
BA10
AW10
BA4
AW4
AY10
AY9
AW5
AY5
AV4
AR5
AK4
AK3
AT4
AK5
AJ5
AJ3

DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63

DDR_B_D0

AK39

DDR Thermal Sensor

EC_SMB_DA24,26
EC_SMB_CK24,26

SMB_EC_DA2
SMB_EC_CK2

+5VS

1

C391

0.1U_0402_16V4Z@

U26

1

SDA

2

SCL

3

OS#

4

GND

LM75CIMMX-5_MSOP8@

VCC

8
7

A0

6

A1

5

A2

2

1 2

R355 1K_0402_5%@

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2005/12/1 2006/12/01

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

Date: Sheet

Calistoga(2)
LA-3271P

of

10 42Monday, August 21, 2006

0.4

5

U23C

H27

SDVOCTRL_DATA

H28

SDVOCTRL_CLK

1 2

0_0603_5%

1 2

150_0402_1%

LCTLA_CLK

LCTLB_DATA

LVDSA0+
LVDSA1+
LVDSA2+

LVDSA0­LVDSA1­LVDSA2-

LVDSB0+
LVDSB1+
LVDSB2+

LVDSB0­LVDSB1­LVDSB2-

LVDSAC+
LVDSAC­LVDSBC+
LVDSBC-

GMCH_ENBKL

EDID_CLK_LCD
EDID_DAT_LCD

GMCH_LVDDEN

R71 1.5K_0402_1%

R339

R64

255_0402_1%

LCTLA_CLK
LCTLB_DATA

3VDDCCL
3VDDCDA

CRT_VSYNC
CRT_HSYNC
CRT_B

CRT_G
CRT_R

LVDSA0+14
LVDSA1+14
LVDSA2+14

LVDSA0-14
LVDSA1-14

LVDSA2-14

LVDSBC+14
LVDSBC-14

BIA_PWM14

GMCH_ENBKL14,26

EDID_CLK_LCD14
EDID_DAT_LCD14

GMCH_LVDDEN14

+1.5VS

CRT_VSYNC14
CRT_HSYNC14

R56

R62

1 2

1 2

150_0402_1%

1 2

R86 10K_0402_5% @

1 2

R85 10K_0402_5%@

1 2

R69 100K_0402_1%

1 2

R346 100K_0402_5%

LVDSB0+14
LVDSB1+14
LVDSB2+14

LVDSB0-14
LVDSB1-14
LVDSB2-14

LVDSAC+14
LVDSAC-14

3VDDCCL14
3VDDCDA14

R60

150_0402_1%

D D

C C

CRT_B14
CRT_G14
CRT_R14

+3VS

B B

GMCH_ENBKL

GMCH_LVDDEN

A A

BIA_PWM

12

12

B37

LA_DATA0

B34

LA_DATA1

A36

LA_DATA2

C37

LA_DATA#0

B35

LA_DATA#1

A37

LA_DATA#2

F30

LB_DATA0

D29

LB_DATA1

F28

LB_DATA2

G30

LB_DATA#0

D30

LB_DATA#1

F29

LB_DATA#2

A32

LA_CLK

A33

LA_CLK#

E26

LB_CLK

E27

LB_CLK#

D32

LBKLT_CTL

J30

LBKLT_EN

H30

LCTLA_CLK

H29

LCTLB_DATA

G26

LDDC_CLK

G25

LDDC_DATA

F32

LVDD_EN

B38

LIBG

C35

LVBG

C33

LVREFH

C32

LVREFL

A16

TVDAC_A

C18

TVDAC_B

A19

TVDAC_C

J20

TV_IREF

B16

TV_IRTNA

B18

TV_IRTNB

B19

TV_IRTNC

J29

TV_DCONSEL1

K30

TV_DCONSEL0

C26

DDCCLK

C25

DDCDATA

H23

VSYNC

G23

HSYNC

E23

BLUE

D23

BLUE#

C22

GREEN

B22

GREEN#

A21

RED

B21

RED#

J22

CRT_IREF

CALISTOGA_FCBGA1466~D

LVDS

TV CRT

4

D40

EXP_COMPI

D38

EXP_COMPO

F34

EXP_RXN0

G38

EXP_RXN1

H34

EXP_RXN2

J38

EXP_RXN3

L34

EXP_RXN4

M38

EXP_RXN5

N34

EXP_RXN6

P38

EXP_RXN7

R34

EXP_RXN8

T38

EXP_RXN9

V34

EXP_RXN10

W38

EXP_RXN11

Y34

EXP_RXN12

AA38

EXP_RXN13

AB34

EXP_RXN14

AC38

EXP_RXN15

D34

EXP_RXP0

F38

EXP_RXP1

G34

EXP_RXP2

H38

EXP_RXP3

J34

EXP_RXP4

L38

EXP_RXP5

M34

EXP_RXP6

N38

EXP_RXP7

P34

EXP_RXP8

R38

EXP_RXP9

T34

EXP_RXP10

V38

EXP_RXP11

W34

EXP_RXP12

Y38

EXP_RXP13

AA34

EXP_RXP14

AB38

EXP_RXP15

F36

EXP_TXN0

G40

EXP_TXN1

H36

EXP_TXN2

J40

EXP_TXN3

L36

EXP_TXN4

M40

EXP_TXN5

N36

EXP_TXN6

P40

EXP_TXN7

R36

EXP_TXN8

PCI-EXPRESS GRAPHICS

EXP_TXN9
EXP_TXN10
EXP_TXN11
EXP_TXN12
EXP_TXN13
EXP_TXN14
EXP_TXN15

EXP_TXP0

EXP_TXP1

EXP_TXP2

EXP_TXP3

EXP_TXP4

EXP_TXP5

EXP_TXP6

EXP_TXP7

EXP_TXP8

EXP_TXP9
EXP_TXP10
EXP_TXP11
EXP_TXP12
EXP_TXP13
EXP_TXP14
EXP_TXP15

T40
V36
W40
Y36
AA40
AB36
AC40

D36
F40
G36
H40
J36
L40
M36
N40
P36
R40
T36
V40
W36
Y40
AA36
AB40

PEGCOMP

1 2

+1.5VS_PCIE

R74

24.9_0402_1%

U23I

AC41
AA41

W41

T41
P41

M41

J41

F41
AV40
AP40
AN40
AK40

AJ40

AH40

AG40

AF40
AE40

B40

AY39

AW39

AV39
AR39
AN39

AJ39
AC39
AB39
AA39

Y39

W39

V39
T39
R39
P39
N39

M39

L39

J39
H39
G39

F39
D39

AT38

AM38

AH38

AG38

AF38
AE38

C38

AK37
AH37
AB37
AA37

Y37

W37

V37
T37
R37
P37
N37

M37

L37

J37
H37
G37

F37
D37

AY36

AW36

AN36
AH36

AG36

AF36
AE36
AC36

C36
B36

BA35
AV35
AR35
AH35
AB35
AA35

Y35

W35

V35
T35
R35
P35
N35

M35

L35

J35
H35
G35

F35
D35

AN34
AK34

AG34

AF34

CALISTOGA_FCBGA1466~D

<BOM Structure>

VSS0
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65
VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77
VSS78
VSS79
VSS80
VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS97
VSS98
VSS99

P O W E R

VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS140
VSS141
VSS142
VSS143
VSS144
VSS145
VSS146
VSS147
VSS148
VSS149
VSS150
VSS151
VSS152
VSS153
VSS154
VSS155
VSS156
VSS157
VSS158
VSS159
VSS160
VSS161
VSS162
VSS163
VSS164
VSS165
VSS166
VSS167
VSS168
VSS169
VSS170
VSS171
VSS172
VSS173
VSS174
VSS175
VSS176
VSS177
VSS178
VSS179
VSS180
VSS181
VSS182
VSS183
VSS184
VSS185
VSS186
VSS187
VSS188
VSS189
VSS190
VSS191
VSS192
VSS193
VSS194
VSS195
VSS196
VSS197
VSS198
VSS199

AE34
AC34
C34
AW33
AV33
AR33
AE33
AB33
Y33
V33
T33
R33
M33
H33
G33
F33
D33
B33
AH32
AG32
AF32
AE32
AC32
AB32
G32
B32
AY31
AV31
AN31
AJ31
AG31
AB31
Y31
AB30
E30
AT29
AN29
AB29
T29
N29
K29
G29
E29
C29
B29
A29
BA28
AW28
AU28
AP28
AM28
AD28
AC28
W28
J28
E28
AP27
AM27
AK27
J27
G27
F27
C27
B27
AN26
M26
K26
F26
D26
AK25
P25
K25
H25
E25
D25
A25
BA24
AU24
AL24
AW23
AT23
AN23
AM23
AH23
AC23
W23
K23
J23
F23
C23
AA22
K22
G22
F22
E22
D22
A22
BA21
AV21
AR21

3

U23J

AN21

VSS200

AL21

VSS201

AB21

VSS202

Y21

VSS203

P21

VSS204

K21

VSS205

J21

VSS206

H21

VSS207

C21

VSS208

AW20

VSS209

AR20

VSS210

AM20

VSS211

AA20

VSS212

K20

VSS213

B20

VSS214

A20

VSS215

AN19

VSS216

AC19

VSS217

W19

VSS218

K19

VSS219

G19

VSS220

C19

VSS221

AH18

VSS222

P18

VSS223

H18

VSS224

D18

VSS225

A18

VSS226

AY17

VSS227

AR17

VSS228

AP17

VSS229

AM17

VSS230

AK17

VSS231

AV16

VSS232

AN16

VSS233

AL16

VSS234

J16

VSS235

F16

VSS236

C16

VSS237

AN15

VSS238

AM15

VSS239

AK15

VSS240

N15

VSS241

M15

VSS242

L15

VSS243

B15

VSS244

A15

VSS245

BA14

VSS246

AT14

VSS247

AK14

VSS248

AD14

VSS249

AA14

VSS250

U14

VSS251

K14

VSS252

H14

VSS253

E14

VSS254

AV13

VSS255

AR13

VSS256

AN13

VSS257

AM13

VSS258

AL13

VSS259

AG13

VSS260

P13

VSS261

F13

VSS262

D13

VSS265

B13

VSS264

AY12

VSS263

AC12

VSS266

K12

VSS267

H12

VSS268

E12

VSS269

AD11

VSS270

AA11

VSS271

Y11

VSS272

J11

VSS273

D11

VSS274

B11

VSS275

AV10

VSS276

AP10

VSS277

AL10

VSS278

AJ10

VSS279

CALISTOGA_FCBGA1466~D

<BOM Structure>

P O W E R

VSS280
VSS281
VSS282
VSS283
VSS284
VSS285
VSS286
VSS287
VSS288
VSS289
VSS290
VSS292
VSS291
VSS293
VSS294
VSS295
VSS296
VSS297
VSS298
VSS299
VSS300
VSS301
VSS302
VSS303
VSS304
VSS305
VSS306
VSS307
VSS308
VSS309
VSS310
VSS311
VSS312
VSS313
VSS314
VSS315
VSS316
VSS317
VSS318
VSS319
VSS320
VSS321
VSS322
VSS323
VSS324
VSS325
VSS326
VSS327
VSS328
VSS329
VSS330
VSS331
VSS332
VSS333
VSS334
VSS335
VSS336
VSS337
VSS338
VSS339
VSS340
VSS341
VSS342
VSS343
VSS344
VSS345
VSS346
VSS347
VSS348
VSS349
VSS350
VSS351
VSS352
VSS353
VSS354
VSS355
VSS356
VSS357
VSS358
VSS359
VSS360

AG10
AC10
W10
U10
BA9
AW9
AR9
AH9
AB9
Y9
R9
G9
E9
A9
AG8
AD8
AA8
U8
K8
C8
BA7
AV7
AP7
AL7
AJ7
AH7
AF7
AC7
R7
G7
D7
AG6
AD6
AB6
Y6
U6
N6
K6
H6
B6
AV5
AF5
AD5
AY4
AR4
AP4
AL4
AJ4
Y4
U4
R4
J4
F4
C4
AY3
AW3
AV3
AL3
AH3
AG3
AF3
AD3
AC3
AA3
G3
AT2
AR2
AP2
AK2
AJ2
AD2
AB2
Y2
U2
T2
N2
J2
H2
F2
C2
AL1

2

1

C71

2

0.22U_0603_10V7K

1

C101

2

10U_1206_6.3V6M

C113

0.22U_0603_10V7K

C65

10U_1206_6.3V6M

1

2

1

2

C111

C96

+VCCP

+VCCP

1

C63

2

0.22U_0603_10V7K

1

C85

2

1U_0603_10V4Z

1

+

220U_D2_4VM

2

1

+

220U_D2_4VM@

2

U23F

AD27

VCC_NCTF0

AC27

VCC_NCTF1

AB27

VCC_NCTF2

AA27

VCC_NCTF3

Y27

VCC_NCTF4

W27

VCC_NCTF5

V27

VCC_NCTF6

U27

VCC_NCTF7

T27

VCC_NCTF8

R27

VCC_NCTF9

AD26

VCC_NCTF10

AC26

VCC_NCTF11

AB26

VCC_NCTF12

AA26

VCC_NCTF13

Y26

VCC_NCTF14

W26

VCC_NCTF15

V26

VCC_NCTF16

U26

VCC_NCTF17

T26

VCC_NCTF18

R26

VCC_NCTF19

AD25

VCC_NCTF20

AC25

VCC_NCTF21

AB25

VCC_NCTF22

AA25

VCC_NCTF23

Y25

VCC_NCTF24

W25

VCC_NCTF25

V25

VCC_NCTF26

U25

VCC_NCTF27

T25

VCC_NCTF28

R25

VCC_NCTF29

AD24

VCC_NCTF30

AC24

VCC_NCTF31

AB24

VCC_NCTF32

AA24

VCC_NCTF33

Y24

VCC_NCTF34

W24

VCC_NCTF35

V24

VCC_NCTF36

U24

VCC_NCTF37

T24

VCC_NCTF38

R24

VCC_NCTF39

AD23

VCC_NCTF40

V23

VCC_NCTF41

U23

VCC_NCTF42

T23

VCC_NCTF43

R23

VCC_NCTF44

AD22

VCC_NCTF45

V22

VCC_NCTF46

U22

VCC_NCTF47

T22

VCC_NCTF48

R22

VCC_NCTF49

AD21

VCC_NCTF50

V21

VCC_NCTF51

U21

VCC_NCTF52

T21

VCC_NCTF53

R21

VCC_NCTF54

AD20

VCC_NCTF55

V20

VCC_NCTF56

U20

VCC_NCTF57

T20

VCC_NCTF58

R20

VCC_NCTF59

AD19

VCC_NCTF60

V19

VCC_NCTF61

U19

VCC_NCTF62

T19

VCC_NCTF63

AD18

VCC_NCTF64

AC18

VCC_NCTF65

AB18

VCC_NCTF66

AA18

VCC_NCTF67

Y18

VCC_NCTF68

W18

VCC_NCTF69

V18

VCC_NCTF70

U18

VCC_NCTF71

T18

VCC_NCTF72

M19

VCC100

L19

VCC101

N18

VCC102

M18

VCC103

L18

VCC104

P17

VCC105

N17

VCC106

M17

VCC107

N16

VCC108

M16

VCC109

L16

VCC110

CALISTOGA_FCBGA1466~D

<BOM Structure>

1

VCCAUX_NCTF0
VCCAUX_NCTF1
VCCAUX_NCTF2
VCCAUX_NCTF3
VCCAUX_NCTF4
VCCAUX_NCTF5
VCCAUX_NCTF6
VCCAUX_NCTF7
VCCAUX_NCTF8

VCCAUX_NCTF9
VCCAUX_NCTF10
VCCAUX_NCTF11
VCCAUX_NCTF12
VCCAUX_NCTF13
VCCAUX_NCTF14
VCCAUX_NCTF15
VCCAUX_NCTF16
VCCAUX_NCTF17
VCCAUX_NCTF18
VCCAUX_NCTF19
VCCAUX_NCTF20
VCCAUX_NCTF21
VCCAUX_NCTF22
VCCAUX_NCTF23
VCCAUX_NCTF24
VCCAUX_NCTF25
VCCAUX_NCTF26
VCCAUX_NCTF27
VCCAUX_NCTF28
VCCAUX_NCTF29
VCCAUX_NCTF30
VCCAUX_NCTF31
VCCAUX_NCTF32
VCCAUX_NCTF33
VCCAUX_NCTF34
VCCAUX_NCTF35
VCCAUX_NCTF36

P O W E R

VCCAUX_NCTF37
VCCAUX_NCTF38
VCCAUX_NCTF39
VCCAUX_NCTF40
VCCAUX_NCTF41
VCCAUX_NCTF42
VCCAUX_NCTF43
VCCAUX_NCTF44
VCCAUX_NCTF45
VCCAUX_NCTF46
VCCAUX_NCTF47
VCCAUX_NCTF48
VCCAUX_NCTF49
VCCAUX_NCTF50
VCCAUX_NCTF51
VCCAUX_NCTF52
VCCAUX_NCTF53
VCCAUX_NCTF54
VCCAUX_NCTF55
VCCAUX_NCTF56
VCCAUX_NCTF57

VSS_NCTF0
VSS_NCTF1
VSS_NCTF2
VSS_NCTF3
VSS_NCTF4
VSS_NCTF5
VSS_NCTF6
VSS_NCTF7
VSS_NCTF8

VSS_NCTF9
VSS_NCTF10
VSS_NCTF11
VSS_NCTF12

VCC_SM100
VCC_SM101
VCC_SM102
VCC_SM103
VCC_SM104
VCC_SM105
VCC_SM106
VCC_SM107

AG27
AF27
AG26
AF26
AG25
AF25
AG24
AF24
AG23
AF23
AG22
AF22
AG21
AF21
AG20
AF20
AG19
AF19
R19
AG18
AF18
R18
AG17
AF17
AE17
AD17
AB17
AA17
W17
V17
T17
R17
AG16
AF16
AE16
AD16
AC16
AB16
AA16
Y16
W16
V16
U16
T16
R16
AG15
AF15
AE15
AD15
AC15
AB15
AA15
Y15
W15
V15
U15
T15
R15

AE27
AE26
AE25
AE24
AE23
AE22
AE21
AE20
AE19
AE18
AC17
Y17
U17

AR6
AP6
AN6
AL6
AK6
AJ6
AV1
AJ1

C51

+1.5VS

1

C50

2

0.47U_0603_10V7K

0.47U_0603_10V7K

+1.8V

1

2

Place near pin AV1 & AJ1

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/12/1 2006/12/01

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

Calistoga(3)
LA-3271P

1

0.4

of

11 42Monday, August 21, 2006

5

AC14
AB14

W14

V14
T14
R14
P14
N14

M14

L14
AD13
AC13
AB13
AA13

Y13

W13

V13

U13

T13

R13

N13

M13

L13
AB12
AA12

Y12

W12

V12

U12

T12

R12

P12

N12

M12

L12

R11

P11

1

N11

M11

R10

2

P10

N10

M10

P9
N9
M9
R8
P8
N8
M8
P7
N7
M7
R6
P6
M6
A6
R5
P5
N5
M5
P4
N4
M4
R3

0.47U_0603_10V7K

P3
N3
M3
R2
P2
M2
D2

AB1

R1
P1
N1
M1

1

C49

2

AG14
AF14
AE14

Y14
AF13
AE13
AF12
AE12
AD12

+1.5VS

21

D20

@

CH751H-40_SC76

12

R34510_0402_5%

@

U23H

VTT0
VTT1
VTT2
VTT3
VTT4
VTT5
VTT6
VTT7
VTT8
VTT9
VTT10
VTT11
VTT12
VTT13
VTT14
VTT15
VTT16
VTT17
VTT18
VTT19
VTT20
VTT21
VTT22
VTT23
VTT24
VTT25
VTT26
VTT27
VTT28
VTT29
VTT30
VTT31
VTT32

P O W E R

VTT33
VTT34
VTT35
VTT36
VTT37
VTT38
VTT39
VTT40
VTT41
VTT42
VTT43
VTT44
VTT45
VTT46
VTT47
VTT48
VTT49
VTT50
VTT51
VTT52
VTT53
VTT54
VTT55
VTT56
VTT57
VTT58
VTT59
VTT60
VTT61
VTT62
VTT63
VTT64
VTT65
VTT66
VTT67
VTT68
VTT69
VTT70
VTT71
VTT72
VTT73
VTT74
VTT75
VTT76

VCCAUX32
VCCAUX33
VCCAUX34
VCCAUX35
VCCAUX36
VCCAUX37
VCCAUX38
VCCAUX39
VCCAUX40

CALISTOGA_FCBGA1466~D

<BOM Structure>

+2.5VS

1

C138

2

0.1U_0402_16V4Z

close pin G41

5

VCC_SYNC

VCCTX_LVDS0
VCCTX_LVDS1
VCCTX_LVDS2

VCC3G0
VCC3G1
VCC3G2
VCC3G3
VCC3G4
VCC3G5
VCC3G6

VCCA_3GPLL

VCCA_3GBG

VSSA_3GBG

VCCA_CRTDAC0
VCCA_CRTDAC1
VSSA_CRTDAC2

VCCA_DPLLA
VCCA_DPLLB

VCCA_HPLL

VCCA_LVDS
VSSA_LVDS

VCCA_MPLL
VCCA_TVBG

VSSA_TVBG

VCCA_TVDACA0
VCCA_TVDACA1
VCCA_TVDACB0
VCCA_TVDACB1
VCCA_TVDACC0
VCCA_TVDACC1

VCCD_HMPLL0
VCCD_HMPLL1

VCCD_LVDS0
VCCD_LVDS1
VCCD_LVDS2

VCCD_TVDAC

VCCDQ_TVDAC

VCCHV0
VCCHV1
VCCHV2

VCCAUX0
VCCAUX1
VCCAUX2
VCCAUX3
VCCAUX4
VCCAUX5
VCCAUX6
VCCAUX7
VCCAUX8

VCCAUX9
VCCAUX10
VCCAUX11
VCCAUX12
VCCAUX13
VCCAUX14
VCCAUX15
VCCAUX16
VCCAUX17
VCCAUX18
VCCAUX19
VCCAUX20
VCCAUX21
VCCAUX22
VCCAUX23
VCCAUX24
VCCAUX25
VCCAUX26
VCCAUX27
VCCAUX28
VCCAUX29
VCCAUX30
VCCAUX31

+2.5VS

1

C376

2

0.01U_0402_16V7K

close pin A38

+VCCP

D D

C C

B B

A A

C48

1

C58

2

4.7U_0805_10V4Z

MCH_A6

1

2

1

C56

2

1

0.22U_0603_10V7K
C46

2

+1.5VS

+VCCP

21

D9

@

CH751H-40_SC76

12

+2.5VS +3VS

R6310_0402_5%

@

1

+

220U_D2_4VM

2

C59

2.2U_0805_16V4Z

C54

MCH_D2

MCH_AB1

0.22U_0603_10V7K

0.47U_0603_10V7K

H22

B30
C30
A30

AB41
AJ41
L41
N41
R41
V41
Y41

AC33
G41
H41

E21
F21
G21

B26
C39
AF1

A38
B39

AF2
H20

G20

E19
F19
C20
D20
E20
F20

AH1
AH2

A28
B28
C28

D21
H19

A23
B23
B25

AK31
AF31
AE31
AC31
AL30
AK30
AJ30
AH30
AG30
AF30
AE30
AD30
AC30
AG29
AF29
AE29
AD29
AC29
AG28
AF28
AE28
AH22
AJ21
AH21
AJ20
AH20
AH19
P19
P16
AH15
P15
AH14

1

C377

2

0.1U_0402_16V4Z

+2.5VS

1 2

C81

0.1U_0402_16V4Z

+2.5VS

W=40 mils

1

C386

2

+1.5VS_3GPLL
+2.5VS

+2.5VS_CRTDAC

+1.5VS_DPLLA
+1.5VS_DPLLB
+1.5VS_HPLL

+2.5VS

+1.5VS_MPLL
+3VS_TVBG

VSSA_TVBG

+3VS_TVDACA
+3VS_TVDACB
+3VS_TVDACC

+1.5VS

+1.5VS_TVDAC
+1.5VS_QTVDAC

1

2

C369

0.1U_0402_16V4Z

10U_0805_6.3V6M

+1.5VS

1

2

+2.5VS

1

C116

2

4.7U_0603_6.3V6M

close pin B30/C30/A30

+1.5VS_PCIE

1

+

C384

2

220U_D2_4VM

1

2

C61

+3VS

1

2

C368

C112

0.1U_0402_16V4Z

1

C114

2

0.1U_0402_16V4Z

4

R352

0_0805_5%

1

C385

2

10U_0805_6.3V6M

10U_0805_6.3V6M

L19 BLM11A601S_0603

1 2

1

1

C382

C381

2

2

0.1U_0402_16V4Z

CRTDAC: Route caps within

0.022U_0402_16V7K~N

250mil of Alviso. Route FB
within 3" of Calistoga

R54

0_0805_5%

1

2

C66

0.1U_0402_16V4Z

0.022U_0402_16V7K~N

+1.5VS

1

1

C375

C374

2

2

10U_0805_4VAM

0.01U_0402_16V7K

4

12

+3VS+3VS_TVBG

12

+1.5VS

+2.5VS

1

2

+1.5VS_DPLLA

0.1U_0402_16V4Z

1

C74

2

0.022U_0402_16V7K~N

CHB1608U301_0603

470U_D2_2.5VM

1

C87

1

+

C97

2

2

0_0805_5%

1

1

2

2

C78

C73

0.1U_0402_16V4Z

0.022U_0402_16V7K~N

+3VS+3VS_TVDACC

R341

12

0_0805_5%

C367

0.1U_0402_16V4Z

L2

R342

12

+3VS+3VS_TVDACB

12

+1.5VS_DPLLB

0.1U_0402_16V4Z

1

C372

2

+1.5VS

+1.5VS

12

L3

CHB1608U301_0603

470U_D2_2.5VM

1

C141

C131

1

+

2

2

+3VS+3VS_TVDACA

R344

12

0_0805_5%

1

C373

2

0.1U_0402_16V4Z

0.022U_0402_16V7K~N

PCI-E/MEM/PSB PLL decoupling

+1.5VS_TVDAC +1.5VS

0_0603_5%
R343

1

1

C370

2

2

0.1U_0402_16V4Z

0.022U_0402_16V7K~N

R75
0_0603_5%

1

1

C147

C120

2

2

0.1U_0402_16V4Z

10U_1206_6.3V6M

+1.5VS_MPLL

45mA Max.

1

2

0.1U_0402_16V4Z
C53

12

C371

+1.5VS+1.5VS_3GPLL

12

45mA Max.

1

C143

2

0.1U_0402_16V4Z

R37
0_0603_5%

1

2

C40

22U_0805_6.3V6M

+1.5VS_QTVDAC +1.5VS

R340
0_0603_5%

12

1

1

C70

C64

2

0.022U_0402_16V7K~N

R36
0_0603_5%

1

1

0.1U_0402_16V4Z

C41

2

2

C45

C366

0.1U_0402_16V4Z

22U_0805_6.3V6M

2

0.1U_0402_16V4Z

+1.5VS_HPLL

12

+1.5VS

1

2

12

3

+VCCP +1.8V

+1.5VS

3

U23G

AA33

VCC0

W33

VCC1

P33

VCC2

N33

VCC3

L33

VCC4

J33

VCC5

AA32

VCC6

Y32

VCC7

W32

VCC8

V32

VCC9

P32

VCC10

N32

VCC11

M32

VCC12

L32

VCC13

J32

VCC14

AA31

VCC15

W31

VCC16

V31

VCC17

T31

VCC18

R31

VCC19

P31

VCC20

N31

VCC21

M31

VCC22

AA30

VCC23

Y30

VCC24

W30

VCC25

V30

VCC26

U30

VCC27

T30

VCC28

R30

VCC29

P30

VCC30

N30

VCC31

M30

VCC32

L30

AA29

Y29

W29

V29
U29
R29
P29

M29

L29
AB28
AA28

Y28

V28

U28

T28

R28

P28

N28

M28

L28

P27

N27

M27

L27

P26

N26

L26

N25

M25

L25

P24

N24

M24
AB23
AA23

Y23
P23
N23

M23

L23
AC22
AB22

Y22

W22

P22

N22

M22

L22
AC21
AA21

W21

N21

M21

L21
AC20
AB20

Y20

W20

P20

N20

M20

L20
AB19
AA19

Y19

N19

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

P O W E R

VCC33
VCC34
VCC35
VCC36
VCC37
VCC38
VCC39
VCC40
VCC41
VCC42
VCC43
VCC44
VCC45
VCC46
VCC47
VCC48
VCC49
VCC50
VCC51
VCC52
VCC53
VCC54
VCC55
VCC56
VCC57
VCC58
VCC59
VCC60
VCC61
VCC62
VCC63
VCC64
VCC65
VCC66
VCC67
VCC68
VCC69
VCC70
VCC71
VCC72
VCC73
VCC74
VCC75
VCC76
VCC77
VCC78
VCC79
VCC80
VCC81
VCC82
VCC83
VCC84
VCC85
VCC86
VCC87
VCC88
VCC89
VCC90
VCC91
VCC92
VCC93
VCC94
VCC95
VCC96
VCC97
VCC98
VCC99

CALISTOGA_FCBGA1466~D

<BOM Structure>

2005/12/1 2006/12/01

VCC_SM0
VCC_SM1
VCC_SM2
VCC_SM3
VCC_SM4
VCC_SM5
VCC_SM6
VCC_SM7
VCC_SM8

VCC_SM9
VCC_SM10
VCC_SM11
VCC_SM12
VCC_SM13
VCC_SM14
VCC_SM15
VCC_SM16
VCC_SM17
VCC_SM18
VCC_SM19
VCC_SM20
VCC_SM21
VCC_SM22
VCC_SM23
VCC_SM24
VCC_SM25
VCC_SM26
VCC_SM27
VCC_SM28
VCC_SM29
VCC_SM30
VCC_SM31
VCC_SM32
VCC_SM33
VCC_SM34
VCC_SM35
VCC_SM36
VCC_SM37
VCC_SM38
VCC_SM39
VCC_SM40
VCC_SM41
VCC_SM42
VCC_SM43
VCC_SM44
VCC_SM45
VCC_SM46
VCC_SM47
VCC_SM48
VCC_SM49
VCC_SM50
VCC_SM51
VCC_SM52
VCC_SM53
VCC_SM54
VCC_SM55
VCC_SM56
VCC_SM57
VCC_SM58
VCC_SM59
VCC_SM60
VCC_SM61
VCC_SM62
VCC_SM63
VCC_SM64
VCC_SM65
VCC_SM66
VCC_SM67
VCC_SM68
VCC_SM69
VCC_SM70
VCC_SM71
VCC_SM72
VCC_SM73
VCC_SM74
VCC_SM75
VCC_SM76
VCC_SM77
VCC_SM78
VCC_SM79
VCC_SM80
VCC_SM81
VCC_SM82
VCC_SM83
VCC_SM84
VCC_SM85
VCC_SM86
VCC_SM87
VCC_SM88
VCC_SM89
VCC_SM90
VCC_SM91
VCC_SM92
VCC_SM93
VCC_SM94
VCC_SM95
VCC_SM96
VCC_SM97
VCC_SM98
VCC_SM99

AU41
AT41
AM41
AU40
BA34
AY34
AW34
AV34
AU34
AT34
AR34
BA30
AY30
AW30
AV30
AU30
AT30
AR30
AP30
AN30
AM30
AM29
AL29
AK29
AJ29
AH29
AJ28
AH28
AJ27
AH27
BA26
AY26
AW26
AV26
AU26
AT26
AR26
AJ26
AH26
AJ25
AH25
AJ24
AH24
BA23
AJ23
BA22
AY22
AW22
AV22
AU22
AT22
AR22
AP22
AK22
AJ22
AK21
AK20
BA19
AY19
AW19
AV19
AU19
AT19
AR19
AP19
AK19
AJ19
AJ18
AJ17
AH17
AJ16
AH16
BA15
AY15
AW15
AV15
AU15
AT15
AR15
AJ15
AJ14
AJ13
AH13
AK12
AJ12
AH12
AG12
AK11
BA8
AY8
AW8
AV8
AT8
AR8
AP8
BA6
AY6
AW6
AV6
AT6

Compal Secret Data

2

MCH_AT41
MCH_AM41

1

C142

C136

2

0.47U_0603_10V7K

Place near pin AT41
& AM41

1

1

2

2

0.1U_0402_16V4Z

C98

C72

0.1U_0402_16V4Z

C109

1

C86

2

0.47U_0603_10V7K

Place near pin BA23

1

1

C365

C380

2

2

10U_1206_6.3V6M

10U_1206_6.3V6M

1

C60

2

0.47U_0603_10V7K

Place near pin BA15

Deciphered Date

2

0.47U_0603_10V7K

1

2

C494

1

2

1

2

0.1U_0402_16V4Z

C55

0.1U_0402_16V4Z

1

1

C495

2

2

10U_1206_6.3V6M

10U_1206_6.3V6M

@

Strap Pin Table

CFG[3:17] have internal pull up
CFG[19:18] have internal pull down

011 = 667MT/s FSB

CFG[2:0]

CFG5

CFG7

CFG9

CFG6

PSB 4X CLK Enable 1 = Calistoga

CFG[13:12]

CFG16

CFG10 CFG18

CFG19

SDVO_CTRLDATA

CFG20

(PCIE/SDVO select)

1

1

+

C378

C496

2

2

10U_1206_6.3V6M

@

330U_D2E_2.5VM_R9

R48 2.2K_0402_5% @

CFG39

CFG179

CFG59
CFG79

CFG99
CFG119
CFG129

CFG139
CFG169

CFG189
CFG199
CFG209

1 2

R95 2.2K_0402_5%@

1 2

R101 2.2K_0402_5%@

1 2

R97 2.2K_0402_5%@

1 2

R100 2.2K_0402_5%@

1 2

R103 2.2K_0402_5%@

1 2

R94 2.2K_0402_5%@

1 2

R102 2.2K_0402_5%@

1 2

R96 2.2K_0402_5%@

1 2

R80 1K_0402_5%@
R82 1K_0402_5% @
R81 1K_0402_5%@

Title

Size Document Number Rev

Custom

Date: Sheet

001 = 533MT/s FSB
0 = DMI x 2

1 = DMI x 4
0 = Reserved

1 = Mobile Yonah CPU
0 = Lane Reversal Enable

1 = Normal Operation

0 = Reserved

00 = Reserved
01 = XOR Mode Enabled
10 = All Z Mode Enabled
11 = Normal Operation

0 = Dynamic ODT Disabled
1 = Dynamic ODT Enabled (Default)

10 = 1.05V
01 = 1.5V

0 = Normal Operation
1 = DMI Lane Reversal Enable

0 = No SDVO Device Present

1 = SDVO Device Present

0 = Only PCIE or SDVO is
operational.
1 = PCIE/SDVO are operating
simu.

1 2
1 2
1 2

Compal Electronics, Inc.

LA-3271P

1

*

(Default)

+3VS

Calistoga(4)

1

(Default)

*

*

(Default)

(Default)

*

(Default)

*

(Default)

(Default)

*

*

(Default)

*

12 42Monday, August 21, 2006

*

*

0.4

of

A

+CK_VDD_MAIN1

1 2

+3VS

R146 0_0805_5%

1 2

+3VS

+3VS

+VCCP

R410

8.2K_0402_5%

CLKREF1

Q34

2N7002_SOT23

R158 0_0805_5%

R159

1 2

0_0805_5%

R150

1 2

0_0805_5%@

R130

8.2K_0402_5%

FSA

1 2

R128
0_0402_5%

CLK_Ra

FSB

12

1 2

R411
0_0402_5%

CLK_Rb

R412

8.2K_0402_5%

1 2

R430 0_0402_5%

CLK_Rc

1 2

R127 0_0402_5%

10/18

13

D

2

G

@

S

A

1 1

CPU_BSEL05

2 2

FSB_G

CPU_BSEL15

3 3

CPU_BSEL25

CLK_EN#37

4 4

VGATE5,17,26,37

+CK_VDD_MAIN2

+VCCP

1 2

12

12

@

+VCCP

1 2

12

+VCCP

1 2

12

@

12

+3VS

12

R126
10K_0402_5%

CLK_ENABLE#

+3VS

R360
2K_0402_1%

1 2

CLK_ENABLE#

12

R359
300_0402_5%

12

J1
NO SHORT PADS

1

C213
10U_0805_10V4Z

2

1

C215
10U_0805_10V4Z

2

+CK_VDD_XDP

1

C211
10U_0805_10V4Z

2

R133

56_0402_5%

CLK_Rd

1 2

R132 1K_0402_5%

R131
1K_0402_5%

@

R428
1K_0402_5%

1 2

R423
1K_0402_5%

R425

@

0_0402_5%

CLK_Re

R429
1K_0402_5%

@
1 2

R426

1K_0402_5%

R424

0_0402_5%

CLK_Rf

@

1

C209

0.1U_0402_16V4Z

2

1

C220

0.1U_0402_16V4Z

2

5/20

1

C226

0.1U_0402_16V4Z

2

MCH_CLKSEL0 9

MCH_CLKSEL1 9

MCH_CLKSEL2 9

B

1

C212

0.1U_0402_16V4Z

2

1

C216

0.1U_0402_16V4Z

2

1

C208

0.1U_0402_16V4Z

2

0.1U_0402_16V4Z@

DOT96 & LCDCLK select

High:Pin14/15 = DOT96

*

pin17/18 = LCDCLK

FSLC1FSLB

CLKSEL1

CLKSEL2

0

0

1

B

+3VS

+CK_VDD_XDP

C224

12

R140
10K_0402_5%

SELDOT

12

R136
10K_0402_5%

FSLA

CLKSEL0

1

2

1

2

12

R164

0_0402_5%@

1

2

@

CPU
MHz

133

166

C223

0.1U_0402_16V4Z

R157

1 2

1_0805_1%

1 2

R144

2.2_0805_1%

C225

0.1U_0402_16V4Z

CLKIREF

SRC
MHz

1000

100

C

CK_VDD_REF

CK_VDD_48

Place crystal within
500 mils of CK410

PCI
MHz

33.31

33.3

C

+3VS

D

R882

@

0_0402_5%

1 2

D

ICH_SMBDATA17,23

ICH_SMBCLK17,23

12

1

C230

R171
0_0805_5%

0.1U_0402_16V4Z

2

CLK_PCIE_LAN_EN17

CLK_48M_ICH17

CLK_14M_ICH17

CLK_ENABLE#

CLK_PCI_ICH15

CLK_PCI_EC26
CLK_PCI_SIO_DB26
CLK_PCI_CB20

CLK_PCI_FWH27

CLK_PCI_TPM26

CLK_DEBUG_PORT23

CLK_MCH_DREFCLK9

CLK_MCH_DREFCLK#9

C417 33P_0402_50V8J

14.31818MHZ_20P_6X1430004201
C416 33P_0402_50V8J

H_STP_CPU#17

H_STP_PCI#17

CLK_PCI_ICH
CLK_PCI_EC
CLK_PCI_SIO_DB CLKREF0
CLK_PCI_CB

CLK_MCH_DREFCLK
CLK_MCH_DREFCLK#

1 3

2

+3VS

2

1 3

D

1 2

R885

@

0_0402_5%

C210 0.1U_0402_16V4Z

C221 0.1U_0402_16V4Z

1 2

Y3

1 2

CLK_PCIE_LAN_EN
CLK_48M_ICH

CLK_14M_ICH

1 2

H_STP_CPU#
H_STP_PCI#
CLK_ENABLE#

R376 33_0402_5%
R388 33_0402_5%
R405 33_0402_5%@
R402 33_0402_5%

R396 33_0402_5%

1 2

R390 0_0402_5%

CLK_SMBDATA7,8

CLK_SMBCLK7,8

1 2

R375 24_0402_5%

1 2

R374 24_0402_5%

+3VS

2.2K_0402_5%

S

Q21

2N7002_SOT23

G

G

Q20

2N7002_SOT23

S

+CK_VDD_MAIN1

+CK_VDD_XDP

CK_VDD_48

12

CK_VDD_REF

12

CLK_XTAL_IN

12

CLK_XTAL_OUT

R387 12_0402_5% @

12
12

R369 33_0402_5%

12

R408 33_0402_5%

R1564.7K_0402_1%

12
12
12
12

12

R39133_0402_5%

12

CLK_SMBDATA
CLK_SMBCLK

MCH_DREFCLK

MCH_DREFCLK#

R165

FSA
FSB_G

CLKREF1

CLKIREF

PCI_ICH
SELDOT

PCI_CLK3

PCI_TPM

E

R166

2.2K_0402_5%

CLK_SMBDATA

CLK_SMBCLK

U28

1

VDDPCI

7

VDDPCI

50

VDDCPU

28

VDDPCIEX

42

VDDPCIEX

11

VDD48

56

VDDREF

45

VDDA

46

GNDA

58

X1

57

X2

12

FSLA/USB_48MHz

60

FSLB/REF0

61

FSLC/REF1

47

VREF

62

CPU_STOP#

63

PCI/PCIEX_STOP#

10

Vtt_PwrGd#/PD

8

PCICLK_F0

9

*SELDOT/PCICLK_F1

64

PCICLK0_2x

3

PCICLK1_2x

4

PCICLK2_2x

5

PCICLK3

55

SDATA

54

SCLK

14

DOT96T_LP/27FIX

15

DOT96C_LP/27FIX

2

GND

6

GND

13

GND

21

GND

29

GND

37

GND

53

GND

59

GND

* Pull-Up or Down Strap Pin

ICS9LPR310_TSSOP64

PCIeC0_LP/LCDCLKC_LP

SATACLKT_LP
SATACLKC_LP

CPUCLKT0_LP
CPUCLKC0_LP

CPUCLKT1_LP
CPUCLKC1_LP

PCIeT0_LP/LCDCLKT_LP

*PEREQ1#

PCIeT6_LP
PCIeC6_LP

*PEREQ2#
PCIeT1_LP
PCIeC1_LP
PCIeT8_LP
PCIeC8_LP

*PEREQ3#
PCIeT2_LP
PCIeC2_LP
PCIeT4_LP
PCIeC4_LP

*PEREQ4#
PCIeT3_LP
PCIeC3_LP
PCIeT5_LP
PCIeC5_LP
PCIeT7_LP
PCIeC7_LP

F

PCIE_SATA

26
27

52
51

49
48

17
18

16

39
38

34
19
20
44
43

32
22
23
30
31

33
24
25
36
35
41
40

1 2

R371 24_0402_5%

PCIE_SATA#

1 2

R370 24_0402_5%

CPU_BCLK

1 2

R420 24_0402_5%

CPU_BCLK#

1 2

R419 24_0402_5%

MCH_BCLK

1 2

R418 24_0402_5%

MCH_BCLK#

1 2

R417 24_0402_5%

SSCDREFCLK

1 2

R386 24_0402_5%

SSCDREFCLK#

1 2

R385 24_0402_5%

MCH_3GPLL

1 2

R416 24_0402_5%

MCH_3GPLL# CLK_MCH_3GPLL#

1 2

R415 24_0402_5%

R422 10K_0402_5%
R413 10K_0402_5%@

CLKREQB#

R421 10K_0402_5%@

1 2

R384 24_0402_5%

PCIE_ICH#

1 2

R383 24_0402_5%

R399 0_0402_5%@

1 2

R397 24_0402_5%@

1 2

R382 24_0402_5%

1 2

R381 24_0402_5%

R409 0_0402_5%@

PCIE_MCARD

1 2

R380 24_0402_5%

PCIE_MCARD#

1 2

R379 24_0402_5%

MCH_SSCDREFCLK
MCH_SSCDREFCLK#

CLKREQA#

12

12
12

R400 10K_0402_5%

12

R406 10K_0402_5%

CLKREQD#CPU_XDP#

12

CLK_PCIE_SATA
CLK_PCIE_SATA#

CLK_CPU_BCLK
CLK_CPU_BCLK#

CLK_MCH_BCLK
CLK_MCH_BCLK#

R139 10K_0402_5%

CLK_MCH_3GPLL

CPPE#

CLK_PCIE_ICHPCIE_ICH
CLK_PCIE_ICH#

CLKREQC#
SATACLKREQ#CPU_XDP
CLK_PCIE_LANPCIE_LOM
CLK_PCIE_LAN#PCIE_LOM#

12

CLK_PCIE_MCARD
CLK_PCIE_MCARD#

G

CLKREQA#

1 2

C205

1000P_0402_50V7K@

CLKREQB#

1 2

C419

1000P_0402_50V7K@

CPU_XDP

1 2

C412

1000P_0402_50V7K@

CPU_XDP#

1 2

C218

1000P_0402_50V7K

Place near U62

CLK_PCIE_SATA 16
CLK_PCIE_SATA# 16

CLK_CPU_BCLK 4
CLK_CPU_BCLK# 4

CLK_MCH_BCLK 9
CLK_MCH_BCLK# 9

MCH_SSCDREFCLK 9
MCH_SSCDREFCLK# 9

12

+3VS

12

+3VS

CLKREQA# 9

CLK_MCH_3GPLL 9
CLK_MCH_3GPLL# 9

CPPE# 15
CLK_PCIE_ICH_EN 17

CLK_PCIE_ICH 17
CLK_PCIE_ICH# 17

+3VS

CLKREQC# 22

CLK_PCIE_LAN 22
CLK_PCIE_LAN# 22

+3VS
CLKREQD# 23
CLK_PCIE_MCARD 23
CLK_PCIE_MCARD# 23

SATACLKREQ#

12

R403 10K_0402_5%

12

R404 10K_0402_5%@

H

SATACLKREQ# 17

+3VS

NOXDP@ : means just build when XDP function disable.
XDP@ : means just build when XDP function enable.

When this time, docking PCI express will not work.

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

D

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

E

2005/12/1 2006/12/01

Compal Secret Data

Deciphered Date

F

Title

Size Document Number Rev

Custom

Date: Sheet of

G

Clock Generator
LA-3271P

13 42Monday, August 21, 2006

H

0.4

A

1 1

CRT_R11

CRT_G11

CRT_B11

CRT_HSYNC11

2 2

12

C36

R68

10_0402_5%@

+3VS

CRT_VSYNC11

1

2

12

12

R15

4.7K_0402_5%

DISPOFF#

LCD POWER CIRCUIT

R14

G

BIA_PWM11

1U_0603_10V4Z@

A

+5VALW

R30100K_0402_5%

1 2

100_0603_1%

2

R25 10K_0402_5%

Q9
BSS138_NL_SOT23

13

D

2

G

12

S

BIA_PWM INVT_PWM

21

21

0.047U_0402_16V7K

D6

@

RB751V_SOD323
D7

RB751V_SOD323

+LCDVDD

1 2
13

D

Q6

2N7002LT1G_SOT23

3 3

GMCH_LVDDEN11

+3VS

1

C37

0.1U_0402_16V4Z@

2

BKOFF#26

GMCH_ENBKL11,26

4 4

D8

1N4148_SOT23@

10K_0402_5%

12

1

2

S

R26

BKOFF#

INVT_PWM

C35

1 2

R309 39_0402_5%

CRT_VSYNC CRT_VSYNC_B

G

2

4.7U_0805_10V4Z

B+

EDID_CLK_LCD11

EDID_DAT_LCD11

B

CRT_R

CRT_G

CRT_B

1 2

C314 0.1U_0402_16V4Z

W=60mils

+3VS

S

SI2301BDS-T1-E3 1P SOT23
Q5

7.3

D

1 3

+LCDVDD

1

C33

0.1U_0402_16V4Z

2

R320

F4

0_0805_5%

21

2.5A_32V

0.1U_0603_50V4Z

B

12

12

R303

150_0402_1%

CRT_HSYNC_BCRT_HSYNC

1

C30

2

INVPWR_B+

12

2

1

+3VS

1 2

R302

150_0402_1%

+CRT_VCC

5

P

A2Y

G

3

1 2

C313 0.1U_0402_16V4Z

0.1U_0603_50V4Z

2

C355

C356

1

12

R327

1 2

R308 39_0402_5%

W=60mils

+LCDVDD

0_0402_5%

1 2

R326

R324 0_0402_5%

MSEN#26

1

12

C316

@

R301

150_0402_1%

1

OE#

U18

74AHCT1G125GW_SOT353-5

2

22P_0402_50V8J

4

+CRT_VCC

原本為

VGA_DDC_DATA_C

VGA_DDC_CLK_C

12

R325

10K_0402_5%

10K_0402_5%

EDID_CLK

EDID_DAT

C

D1

DAN217_SC59@

+3VS

L10

L9

L8

For EMI

12

R2

1 2

BSS138_NL_SOT23

AMBER_LED#
BATT_LED1#
GREEN_LED#

EDID_CLK
EDID_DAT

LVDSBC+
LVDSBC-

LVDSB0+
LVDSB0-

LVDSB1+
LVDSB1-

LVDSB2+
LVDSB2-

C

CRT_R_L

CRT_G_L

CRT_B_L

1

2

10P_0402_50V8J

R4

1 2

2K_0402_5%

2.2K_0402_5%

2

G

1 3

D

Q1

BSS138_NL_SOT23

1
3
5
7

9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39

CONN@

JST_BM40B-SRDS-G-TFCLFSN~N

2005/12/1 2006/12/01

1 2

BK2125LL121-T_0805

1 2

BK2125LL121-T_0805

1 2

BK2125LL121-T_0805

1

C317

@

22P_0402_50V8J

C318

1

2

@

2

22P_0402_50V8J

R307 10K_0402_5%

D_CRT_HSYNC

1

5

P

D_CRT_VSYNC

4

OE#

A2Y

G

U17
74AHCT1G125GW_SOT353-5

3

4.7K

R3

1 2

2K_0402_5%

+LCDVDD

+3VS

LVDSBC+11

LVDSBC-11

LVDSB0+11
LVDSB0-11

LVDSB1+11

LVDSB1-11

LVDSB2+11

LVDSB2-11

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

1

2

C310

10P_0402_50V8J

R5

S

2

1 3

D

Q2

JLCD1

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39

D2

DAN217_SC59@

3

2

1

C309

2

R297

1 2

MBK1608301YZF_0603

1 2

MBK1608301YZF_0603

R296

+3VS+CRT_VCC +3VS+CRT_VCC +3VS

R6

1 2

2.2K_0402_5%

G

S

41

2

2

4

4

GND

6

6

8

8

10

10

12

12

14

14

16

16

18

18

20

20

22

22

24

24

26

26

28

28

30

30

32

32

34

34

36

36

38

38

40

40

GND

42

3

原本為

1 2

2.2K_0402_5%

LVDSAC+
LVDSAC-

LVDSA0+
LVDSA0-

LVDSA1+
LVDSA1-

LVDSA2+
LVDSA2-

DISPOFF#
DAC_BRIG

INVT_PWM

1

2

3

1

C312

10P_0402_50V8J

2

CRT_GND

1

2

10K

3VDDCDA 11

3VDDCCL 11

LVDSA0+ 11

LVDSA0- 11

LVDSA1+ 11

LVDSA1- 11

LVDSA2+ 11
LVDSA2- 11

INVPWR_B+
INVPWR_B+

1

Compal Secret Data

Deciphered Date

D3

DAN217_SC59@

HSYNC_L

VSYNC_L

C311

15P_0402_50V8J

2

C354

0.1U_0402_10V6K

1

LVDSAC+ 11
LVDSAC- 11

D

+5VS

1.1A_6VDC_FUSE

1

C308

2

15P_0402_50V8J

+5VALW

DAC_BRIG 26
INVT_PWM 26

D

E

W=40mils

21

C3

C307

100P_0402_50V8J

D4

2 1

RB411DT146 SOT23

0.1U_0402_16V4Z

DDC_MD2

1

2

1

100P_0402_50V8J

C1

2

PWR_GREEN_LED#26,29

PWR_AMBER_LED#26,29

BATT_FULL_LED#26,29

1

C2

2

VGA_DDC_DATA_C

VGA_DDC_CLK_C

1

100P_0402_50V8J

C4

2

Title

Size Document Number Rev

Custom

Date: Sheet

F1

1

2

+CRT_VCC

W=40mils

1

C550

2

@

R18
330_0603_5%

1 2

R23
330_0603_5%

1 2

R29
330_0603_5%

1 2

R295
0_0805_5%

R1
0_0805_5%

1 2

1 2

1 2

0.1U_0402_16V4Z

6

11

1
7

12

2
8

13

3
9

14

4
10
15

5

SUYIN_070549FR015S208CR

R17

330_0603_5%

R19

1K_0603_5%

R22

1K_0603_5%

CRT_GND

CRT_GND

100P_0402_50V8J

GREEN_LED#

Battery low LED Color:Amber

AMBER_LED#

Battery low LED Color:Amber

BATT_LED1#

Battery low LED Color:Amber

TV_OUT/CRT CONN
LA-3271P

JCRT1

12

12

R16

1 2

1M_0603_1%

R20

1 2

1M_0603_1%

R24

1 2

1M_0603_1%

17
16

C

Q4

2

B

MMBT3904_NL_SOT23

E

3 1

C

Q7

2

B

MMBT3904_NL_SOT23

E

3 1

C

Q10

2

B

MMBT3904_NL_SOT23

E

3 1

0.4

of

E

14 42Monday, August 21, 2006

+3VS

5

4

3

2

1

VGATE13,17,26,37

PCI_DEVSEL#
PCI_STOP#
PCI_TRDY#
PCI_FRAME#
PCI_PLOCK#
PCI_IRDY#
PCI_SERR#
PCI_PERR#
PCI_REQ4#
PCI_REQ3#

PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#
PCI_PIRQE#
PCI_PIRQF#
PCI_PIRQG#
PCI_PIRQH#
PCI_REQ0#
PCI_REQ1#
PCI_REQ2#
PCI_REQ5#

+3VS

PCI_AD[0..31]20

PCI_PIRQA#
PCI_PIRQB#

PCI_PIRQD#

12

R161
100K_0402_5%@

14

U9A

P

1

12

SN74LVC14APWR_TSSOP14~N@
R168

1M_0402_5%@

2

O

I

G

7

SN74LVC14APWR_TSSOP14~N@

14

U9B

P

3

O

I

G

7

PCI_AD0
PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD6
PCI_AD7
PCI_AD8
PCI_AD9
PCI_AD10
PCI_AD11
PCI_AD12
PCI_AD13
PCI_AD14
PCI_AD15
PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20
PCI_AD21
PCI_AD22
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30
PCI_AD31

PCI_PIRQA#

PCI_PIRQB# PCI_PIRQF#
PCI_PIRQC#
PCI_PIRQD#

4

R185

1 2

330K_0402_5%@

0.47U_0603_10V7K@

U34B

E18

AD0

C18

AD1

A16

F18
E16
A18
E17
A17
A15
C14
E14
D14
B12
C13
G15
G13
E12
C11
D11
A11
A10

F11

F10

AE5
AD5
AG4
AH4
AD9

E9
D9
B9
A8
A6
C7
B6
E6
D6

A3
B4
C5
B5

PCI

AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31

Interrupt I/F

PIRQA#
PIRQB#
PIRQC#
PIRQD#

MISC

RSVD[1]
RSVD[2]
RSVD[3]
RSVD[4]
RSVD[5]

ICH7_BGA652~D

1

C232

2

REQ0#
GNT0#
REQ1#
GNT1#
REQ2#
GNT2#
REQ3#

GNT3#
REQ4# / GPIO22
GNT4# / GPIO48

GPIO1 / REQ5#

GPIO17 / GNT5#

C/BE0#

C/BE1#

C/BE2#

C/BE3#

IRDY#

PCIRST#

DEVSEL#

PERR#

PLOCK#

SERR#

STOP#

TRDY#

FRAME#

PLTRST#

PCICLK

GPIO2 / PIRQE#
GPIO3 / PIRQF#
GPIO4 / PIRQG#
GPIO5 / PIRQH#

RSVD[6]
RSVD[7]
RSVD[8]
RSVD[9]

MCH_SYNC#

14

P

5

I

G

7

SN74LVC14APWR_TSSOP14~N@

PAR

PME#

U9C

O

PCI_REQ0#

D7
E7

PCI_REQ1#

C16
D16

PCI_REQ2#

C17
D17

PCI_REQ3#

E13
F13

PCI_REQ4#

A13
A14

PCI_REQ5#

C8
D8

PCI_CBE#0

B15

PCI_CBE#1

C12

PCI_CBE#2

D12

PCI_CBE#3

C15

PCI_IRDY#

A7

PCI_PAR

E10

PCI_PCIRST#

B18

PCI_DEVSEL#

A12

PCI_PERR#

C9

PCI_PLOCK#

E11

PCI_SERR#

B10

PCI_STOP#

F15

PCI_TRDY#

F14

PCI_FRAME#

F16

PCI_PLTRST#

C26

CLK_PCI_ICH

A9
B19

PCI_PIRQE#

G8
F7

PCI_PIRQG#

F8

PCI_PIRQH#

G7

AE9
AG8
AH8
F21
AH20

+3VS

9

6

I

14

U9D

P

G

SN74LVC14APWR_TSSOP14~N@

7

C219 0.1U_0402_16V4Z@

8

O

PCI_REQ0# 20
PCI_GNT0# 20

PCI_REQ2#
PCI_REQ3#

R2810_0402_5%

CPPE#

12

PCI_CBE#0 20
PCI_CBE#1 20
PCI_CBE#2 20
PCI_CBE#3 20,22

PCI_IRDY# 20
PCI_PAR 20

PCI_DEVSEL# 20,22
PCI_PERR# 20

PCI_SERR# 20
PCI_STOP# 20
PCI_TRDY# 20
PCI_FRAME# 20

CLK_PCI_ICH 13
EC_PME# 26

PCI_PIRQE# 20
PCI_PIRQF# 20
PCI_PIRQG# 20PCI_PIRQC#
PCI_PIRQH#

MCH_ICH_SYNC# 9

R163 0_0402_5%@

12

CPPE# 13

ICH_POK 17,26

PCI_PCIRST#

PCI_PLTRST#

+3VS

5

U14

1

P

B

2

A

G

R267
0_0402_5%

3

12

+3VS

5

U16

1

P

B

2

A

G

3

R274
0_0402_5%

12

Place closely pin A9

CLK_PCI_ICH

R499

10_0402_5% @

8.2P_0402_50V8D@

C477

1 2

1

2

PCI_RST#

4

Y

TC7SH08FU_SSOP5@

PLT_RST#

4

Y

TC7SH08FU_SSOP5@

PCI_RST# 20,23

PLT_RST# 9,17,22,23,26

R277 8.2K_0402_5%

1 2

R285 8.2K_0402_5%

1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2

1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2

R284 8.2K_0402_5%

D D

C C

B B

R262 8.2K_0402_5%
R289 8.2K_0402_5%
R288 8.2K_0402_5%
R283 8.2K_0402_5%
R275 8.2K_0402_5%
R290 8.2K_0402_5%
R276 8.2K_0402_5%

+3VS

R257 8.2K_0402_5%
R258 8.2K_0402_5%
R256 8.2K_0402_5%
R255 8.2K_0402_5%
R249 8.2K_0402_5%
R250 8.2K_0402_5%
R246 8.2K_0402_5%
R247 8.2K_0402_5%
R252 8.2K_0402_5%
R264 8.2K_0402_5%
R248 8.2K_0402_5%
R282 8.2K_0402_5%

Issued Date

NB_PWRGD 9

ICH_POK 17,26

2005/12/1 2006/12/01

3

Deciphered Date

2

Compal Secret Data

Title

Size Document Number Rev

Custom

Date: Sheet

ICH7-PCI_EXP/PCI/LPC/RTC
LA-3271P

of

15 42Monday, August 21, 2006

1

0.4

A A

R193 0_0402_5%

12

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

C445

15P_0402_50V8J

12

+RTCVCC

12

R212
1M_0402_5%

D D

SM_INTRUDER#

32.768KHZ_12.5P_1TJS125BJ2A251

2
3

C446

15P_0402_50V8J

12

Y4

IN

NC

OUT

NC

RTC Battery

-+

2

-

+

+RTCBATT+RTCBATT

1

+RTCBATT

Place J1 close

+RTCVCC

to DDR-SODIMM

12

R211
332K_0402_1%

C C

B B

ICH_INTVRMEN

+3VS

+3VS

JRTC1
MAXELL_1220G

+RTCVCC

BAT

R585
0_0603_5%

12

PUT JOPEN1 NEAR TO RAM DOOR

SATA_LED#

R42710K_0402_5%

12

IDE_DIORDY

R4364.7K_0402_5%

12

IDE_IRQ

R4378.2K_0402_5%

12

3

1
4

ACZ_BITCLK24

ACZ_SYNC24

ACZ_SDIN024
ACZ_SDIN124

ACZ_SDOUT24

+RTCVCC

1

ACZ_RST#24

SATA_LED#29

PSATA_IRX_DTX_N0_C19
PSATA_IRX_DTX_P0_C19

4

ICH_RTCX1

ICH_RTCX2

CLR_CMOS23

D23
BAS40-04_SOT23

2

CHB1608U301_0603

CLK_PCIE_SATA#13
CLK_PCIE_SATA13

IDE_DDACK#19

12

R460

10M_0402_5%

R213

1 2

20K_0402_5%

1U_0603_10V6K

L21

1 2

R217
39_0402_5%

SATA_LED#

IDE_DIORDY19

IDE_IRQ19

IDE_DIOW#19
IDE_DIOR#19

ICH_RTCRST#

C252

CHGRTC

1 2
1 2

1 2

ACZ_SDIN0
ACZ_SDIN1

1 2

PSATA_IRX_DTX_N0_C
PSATA_IRX_DTX_P0_C
PSATA_ITX_DRX_N0_C
PSATA_ITX_DRX_P0_C

CLK_PCIE_SATA#
CLK_PCIE_SATA

ICH_INTVRMEN
SM_INTRUDER#

1

2

R21439_0402_5%

ICH_ACZ_BITCLK
ICH_ACZSYNC_

R22939_0402_5%

ACZRST#

R22239_0402_5%

ICH_ACZSDOUT_

R439

1 2

24.9_0402_1%

IDE_DIORDY
IDE_IRQ
IDE_DDACK#
IDE_DIOW#
IDE_DIOR#

AB1
AB2

AA3

W4

W1

W3

AF18

AF3
AE3
AG2
AH2

AF7
AE7
AG6
AH6

AF1
AE1

AH10
AG10

AG16
AH16

AF16

AH15

AF15

Y5

Y1
Y2

V3
U3
U5

V4
T5

U7
V6
V7

U1
R6

R5
T2

T3
T1

T4

U34A

RTXC1
RTCX2

RTCRST#
INTVRMEN

INTRUDER#

EE_CS
EE_SHCLK
EE_DOUT
EE_DIN

LAN_CLK
LAN_RSTSYNC
LAN_RXD0

LAN_RXD1
LAN_RXD2

LAN_TXD0
LAN_TXD1
LAN_TXD2

ACZ_BCLK
ACZ_SYNC

ACZ_RST#
ACZ_SDIN0

ACZ_SDIN1
ACZ_SDIN2

ACZ_SDOUT

SATALED#

SATA0RXN
SATA0RXP
SATA0TXN
SATA0TXP

SATA2RXN
SATA2RXP
SATA2TXN
SATA2TXP

SATA_CLKN
SATA_CLKP

SATARBIASN
SATARBIASP

IORDY
IDEIRQ
DDACK#
DIOW#
DIOR#

ICH7_BGA652~D

3

RTC

LAN

GPIO49 / CPUPWRGD

IDE

LAD0
LAD1
LAD2
LAD3

LDRQ0#

LPCCPU

LDRQ1# / GPIO23

LFRAME#

A20GATE

A20M#

CPUSLP#

TP1 / DPRSTP#

TP2 / DPSLP#

FERR#

IGNNE#

INIT3_3V#

INIT#
INTR

AC-97/AZALIA

RCIN#

SMI#

STPCLK#

THERMTRIP#

DA0
DA1
DA2

DCS1#
DCS3#

SATA

DD0
DD1
DD2
DD3
DD4
DD5
DD6
DD7
DD8

DD9
DD10
DD11
DD12
DD13
DD14
DD15

DDREQ

NMI

AA6
AB5
AC4
Y6

AC3
AA5

AB3

AE22
AH28

AG27
AF24

AH25
AG26
AG24
AG22

AG21
AF22
AF25

AG23
AF23

AH24
AH22
AF26

AH17
AE17
AF17

AE16
AD16

AB15
AE14
AG13
AF13
AD14
AC13
AD12
AC12
AE12
AF12
AB13
AC14
AF14
AH13
AH14
AC15

AE15

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3

R208

LPC_FRAME#

GATEA20
H_A20M#

H_CPUSLP_R#
DPRSLP#

H_DPSLP#
H_FERR#
H_PWRGOOD
H_IGNNE#
H_INIT#

H_INTR

KB_RST#
H_SMI#

H_NMI
H_STPCLK#
THRMTRIP_ICH#

IDE_DA0
IDE_DA1
IDE_DA2

IDE_DCS1#
IDE_DCS3#

IDE_DD0
IDE_DD1
IDE_DD2
IDE_DD3
IDE_DD4
IDE_DD5
IDE_DD6
IDE_DD7
IDE_DD8
IDE_DD9
IDE_DD10
IDE_DD11
IDE_DD12
IDE_DD13
IDE_DD14
IDE_DD15

IDE_DDREQ

LPC_DRQ0#

12

0_0402_5%@

LPC_AD[0..3] 23,26

LPC_FRAME# 23,26

R431 10K_0402_5%

12

GATEA20 26
H_A20M# 4

R180 0_0402_5%@

12

R176 0_0402_5%

12

H_DPSLP# 4

12

H_FERR# 4
H_PWRGOOD 4
H_IGNNE# 4
H_INIT# 4

H_INTR 4

R175 10K_0402_5%

12

KB_RST# 26
H_SMI# 4

H_NMI 4
H_STPCLK# 4

IDE_DA0 19
IDE_DA1 19
IDE_DA2 19

IDE_DCS1# 19
IDE_DCS3# 19

IDE_DD[0..15]

IDE_DDREQ 19

2

LPC_DRQ#0 26

56_0402_5%
R191

IDE_DD[0..15] 19

+3VS

H_CPUSLP# 4,9
H_DPRSTP# 4,37

+VCCP

+VCCP

+3VS

12

R181

56_0402_5%

1

H_DPRSTP# daisy:

ICH7-M --> Yonah --> IMVP6

R184

1 2

24.9_0402_1%

@

H_THERMTRIP# 4,9

ICH_ACZSYNC_

R23039_0402_5%

ACZRST#

R22339_0402_5%

ICH_ACZSDOUT_

R21839_0402_5%

ICH_ACZ_BITCLK

R21539_0402_5%

Compal Secret Data

Deciphered Date

ML1220 MAXELL LITHIUM RTC BATTERY

2

C260

1

1 2
1 2
1 2
1 2

10P_0402_25V8K@

PSATA_ITX_DRX_N019

PSATA_ITX_DRX_P019

A A

PSATA_ITX_DRX_N0

PSATA_ITX_DRX_P0

C436 3900P_0402_50V7K

C431 3900P_0402_50V7K

close ICH7

1 2

1 2

PSATA_ITX_DRX_N0_C

PSATA_ITX_DRX_P0_C

MDC_ACZ_SYNC24

MDC_ACZ_RST#24

MDC_ACZ_SDOUT24

MDC_ACZ_BITCLK24

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2005/12/1 2006/12/01

3

BATT1

Title

Size Document Number Rev

Custom

2

Date: Sheet

ICH7-USB/ACPI/AC97/GPIO
LA-3271P

of

16 42Monday, August 21, 2006

1

0.4

5

+3VS

+3V_SB

10K_0402_5%

1 2

8.2K_0402_5%

1 2

8.2K_0402_5%

R237
0_0402_5%

1 2

10K_0402_5%

1 2

10K_0402_5%@

1 2

10K_0402_5%

1 2

10K_0402_5%

1 2

10K_0402_5%

1 2

10K_0402_5%

1 2

SERIRQ

PCI_CLKRUN#
EC_THERM#

12

SYS_RST#

SMBALERT#

SPI_MISO

SPI_CS#

WL_ON

SPI_MOSI

R498

10K_0402_5%

+3V_SB

R271

R272

R251

1 2

10K_0402_5%

1 2

8.2K_0402_5%

1 2

R273

R497
10K_0402_5%

1 2

1K_0402_5%

10K_0402_5%

1 2

LINKALERT#

ICH_LOW_BAT#

12

ICH_PCIE_WAKE#

SMBALERT#

PCIE_RXN122
PCIE_RXP122
PCIE_TXN122

PCIE_TXP122

PCIE_RXN223
PCIE_RXP223
PCIE_TXN223

PCIE_TXP223

R205

R433

D D

C C

B B

A A

R195

+3V +3V_SB

R241
0_0402_5%

@

1 2

R244

R231

R238

R232

R245

R242

4

3

2

1

Place closely pin B2 Place closely pin AC1

+3V_SB

12

12

R269

R268

R263

1 2

8.2K_0402_5%

SB_SPKR25

R500 0_0402_5%

H_STP_PCI#13

SW_RSV223

EC_SWI#26

SW_RSV323

SERIRQ20,23,26

VGATE13,15,26,37

EC_SMI#26

1 2
1 2

1 2
1 2

USB_OC#0
USB_OC#1
USB_OC#2

USB_OC#428
USB_OC#528
USB_OC#628
USB_OC#328

2.2K_0402_5%

T29PAD

1 2

C4700.1U_0402_16V7K~N
C4710.1U_0402_16V7K~N

C4630.1U_0402_16V7K~N
C4660.1U_0402_16V7K~N

T21PAD

T23PAD
T22PAD

ICH_SMBCLK
ICH_SMBDATA
LINKALERT#
ICH_SMLINK0
ICH_SMLINK1

ICH_RI#
SB_SPKR

SUS_STAT#

SYS_RST#
PM_BMBUSY#
SMBALERT#
H_STP_PCI#

H_STP_CPU#

SW_RSV2

PCI_CLKRUN#
SW_RSV3

ICH_PCIE_WAKE#

SERIRQ
EC_THERM#

VGATE

PASSWORD#

EC_SMI#

PCIE_RXN1
PCIE_RXP1
PCIE_C_TXN1
PCIE_C_TXP1

PCIE_RXN2
PCIE_RXP2
PCIE_C_TXN2
PCIE_C_TXP2

SPI_CS#

SPI_MOSI
SPI_MISO

USB_OC#0

USB_OC#1

USB_OC#2

USB_OC#7

USB_OC#4

USB_OC#5

USB_OC#6

USB_OC#3

2.2K_0402_5%

ICH_SMBCLK13,23

ICH_SMBDATA13,23

+3V_SB

ITP_DBRESET#4

PM_BMBUSY#9

H_STP_CPU#13

CLK_PCIE_LAN_EN13

PCI_CLKRUN#20,26

IDE_RESET#19

ICH_PCIE_WAKE#23

EC_THERM#26

CLK_PCIE_ICH_EN13

PASSWORD#23

U34C

C22

SMBCLK

B22

SMBDATA

A26

LINKALERT#

B25

SMLINK0

A25

SMLINK1

A28

RI#

A19

SPKR

A27

SUS_STAT#

A22

SYS_RST#

AB18

GPIO0 / BM_BUSY#

B23

GPIO11 / SMBALERT#

AC20

GPIO18 / STPPCI#

AF21

GPIO20 / STPCPU#

A21

GPIO26

B21

GPIO27

E23

GPIO28

AG18

GPIO32 / CLKRUN#

AC19

GPIO33 / AZ_DOCK_EN#

U2

GPIO34 / AZ_DOCK_RST#

F20

WAKE#

AH21

SERIRQ

AF20

THRM#

AD22

VRMPWRGD

AC21

GPIO6

AC18

GPIO7

E21

GPIO8

ICH7_BGA652~D

U34D

F26

PERn1

F25

PERp1

E28

PETn1

E27

PETp1

H26

PERn2

H25

PERp2

G28

PETn2

G27

PETp2

K26

PERn3

K25

PERp3

J28

PETn3

J27

PETp3

M26

PERn4

M25

PERp4

L28

PETn4

L27

PETp4

P26

PERn5

P25

PERp5

N28

PETn5

N27

PETp5

T25

PERn6

T24

PERp6

R28

PETn6

R27

PETp6

R2

SPI_CLK

P6

SPI_CS#

P1

SPI_ARB

P5

SPI_MOSI

P2

SPI_MISO

D3

OC0#

C4

OC1#

D5

OC2#

D4

OC3#

E5

OC4#

C3

OC5# / GPIO29

A2

OC6# / GPIO30

B3

OC7# / GPIO31

ICH7_BGA652~D

GPIO21 / SATA0GP

SMB

GPIO19 / SATA1GP
GPIO36 / SATA2GP
GPIO37 / SATA3GP

SATA

GPIO

SYS

GPIO

GPIO

Clocks

POWER MGT

SUSCLK
SLP_S3#

SLP_S4#
SLP_S5#

GPIO16 / DPRSLPVR

TP0 / BATLOW#

PWRBTN#

LAN_RST#

RSMRST#

GPIO35 / SATAREQ#

Need update symbol

V26

DMI0RXN

V25

DMI0RXP

U28

DMI0TXN

U27

DMI0TXP

Y26

DMI1RXN

Y25

DMI1RXP

W28

DMI1TXN

W27

DMI1TXP

PCI-EXPRESS

DIRECT MEDIA INTERFACE

DMI_ZCOMP

DMI_IRCOMP

SPI

USB

DMI2RXN
DMI2RXP

DMI2TXN
DMI2TXP

DMI3RXN
DMI3RXP

DMI3TXN
DMI3TXP

DMI_CLKN
DMI_CLKP

USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4N
USBP4P
USBP5N
USBP5P
USBP6N
USBP6P
USBP7N
USBP7P

USBRBIAS#

USBRBIAS

AB26
AB25
AA28
AA27

AD25
AD24
AC28
AC27

AE28
AE27

C25
D25

F1
F2
G4
G3
H1
H2
J4
J3
K1
K2
L4
L5
M1
M2
N4
N3

D2
D1

CLK14
CLK48

PWROK

GPIO9
GPIO10
GPIO12
GPIO13
GPIO14
GPIO15
GPIO24
GPIO25

GPIO38
GPIO39

DMI_RXN0
DMI_RXP0
DMI_TXN0
DMI_TXP0

DMI_RXN1
DMI_RXP1
DMI_TXN1
DMI_TXP1

DMI_RXN2
DMI_RXP2
DMI_TXN2
DMI_TXP2

DMI_RXN3
DMI_RXP3
DMI_TXN3
DMI_TXP3

CLK_PCIE_ICH#
CLK_PCIE_ICH

DMI_IRCOMP
USB20_N0

USB20_P0
USB20_N1
USB20_P1
USB20_N2
USB20_P2

USB20_N4
USB20_P4
USB20_N5
USB20_P5
USB20_N6
USB20_P6
USB20_N3
USB20_P3

USBRBIAS

1 2

T27 PAD

EC_FLASH#

12
12
12
12

CLK_14M_ICH 13
CLK_48M_ICH 13

T30 PAD

SLP_S3# 26
SLP_S4#

ICH_POK 15,26
DPRSLPVR 9,37

EC_RSMRST# 26

EC_SCI# 26

EC_LID_OUT# 26

EC_FLASH# 27
SATACLKREQ# 13

PBTN_OUT# 26

R179 8.2K_0402_5%

AF19

R434 8.2K_0402_5%

AH18

R432 8.2K_0402_5%

AH19

R178 8.2K_0402_5%

AE19

CLK_14M_ICH

AC1

CLK_48M_ICH

B2

ICH_SUSCLK

C20

SLP_S3#

B24

SLP_S4#

D23

SLP_S5#_S

F22

ICH_POK

AA4

DPRSLPVR

AC22

ICH_LOW_BAT#

C21

PBTN_OUT#

C23

PLT_RST#

C19

EC_RSMRST#

Y4

R187 10K_0402_5%

EC_SCI#

E20
A20
F19

EC_LID_OUT#

E19
R4
E22

WL_ON

R3
D20
AD21

VREDET1

AD20

VREDET2

AE20

Double BR ID, need take off

DMI_RXN0 9
DMI_RXP0 9
DMI_TXN0 9
DMI_TXP0 9

DMI_RXN1 9
DMI_RXP1 9
DMI_TXN1 9
DMI_TXP1 9

DMI_RXN2 9
DMI_RXP2 9
DMI_TXN2 9
DMI_TXP2 9

DMI_RXN3 9
DMI_RXP3 9
DMI_TXN3 9
DMI_TXP3 9

CLK_PCIE_ICH# 13
CLK_PCIE_ICH 13

R254 24.9_0402_1%

1 2

R485 22.6_0402_1%

1 2

USB20_N0 23
USB20_P0 23
USB20_N1 27
USB20_P1 27
USB20_N2 28
USB20_P2 28

USB20_N4 28
USB20_P4 28
USB20_N5 28
USB20_P5 28
USB20_N6 28
USB20_P6 28
USB20_N3 28
USB20_P3 28

Within 500 mils

Within 500 mils

+3VS
+3VS
+3VS
+3VS

1 2

PLT_RST# 9,15,22,23,26

ACIN 26,32,34

1 2
1 2

+1.5VS

R186
10K_0402_5%

R563
0_0402_5%
0_0402_5%

12

R496

1

C478

2

R583

USB_OC#6
USB_OC#7
USB_OC#5
USB_OC#1

10_0402_5%@

4.7P_0402_50V8C@

SLP_S4#
SLP_S5#_S

GOLAN_ALPS# 23

GOLAN_ALPS 23

VREDET1 VREDET2

M/B ID

MP1 (Rev0.3)
IRT (Rev1.0)
MP (Rev1.0)
MP (Rev2.0)

R495

4 5
3 6
2 7
1 8

10K_1206_8P4R_5%

USB_OC#2
USB_OC#0
USB_OC#3
USB_OC#4

RP31

4 5
3 6
2 7
1 8

10K_1206_8P4R_5%

CLK_14M_ICHCLK_48M_ICH

12

R455

10_0402_5% @

1

C442

4.7P_0402_50V8C@

2

+LDO3

+3V_SB

R574

R575

0_0402_5%

1 2

5

U13

2

P

B

1

A

G

NC7SZ08P5X_NL_SC70-5

3

+3V_SB

DPRSLPVR

R266
10K_0402_5%

@

1 2

PBTN_OUT#

+3VS

R183
10K_0402_5%

@

1 2

R197
10K_0402_5%

1 2

GPIO38

0
01
10
11

+3V_SB

+3V_SB

1 2

Y

0_0402_5%

@

4

100K_0402_5%@

R182
10K_0402_5%

1 2

R196

@

10K_0402_5%

1 2

GPIO39

R190

SLP_S5# 26

12

0

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/12/1 2006/12/01

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

ICH7-IDE/SATA
LA-3271P

1

0.4

of

17 42Monday, August 21, 2006

100_0402_5%

R524

@

10_0402_5%

+3V

R188

+5V

12

12

R265

10_0402_5%

+3VS+5VS

21

D14
CH751H-40_SC76

ICH_V5REF_RUN

1

C246

0.1U_0402_16V4Z

2

12

+3V_SB+5VALW

+1.5VS

PJP14
JUMP_43X118@

112

PJP15
JUMP_43X118@

112

21

1

2

D15
CH751H-40_SC76

ICH_V5REF_SUS

C288

0.1U_0402_16V4Z

Place closely pin AG28 within 100mlis.

R456

1 2

0.5_0805_1%

0.1U_0402_16V4Z

2

2

+1.5VS_DMIPLLR

+1.5VS

+3V_SB

C247

C289

+3V_SB+3VALW

R452

1 2

0_0805_5%

10U_0805_10V4Z~N

+3VS

1

2

0.1U_0402_16V4Z

1

2

0.1U_0402_16V4Z

C433

+1.5VS

+1.5VS

1

+

C249

2

+1.5VS_DMIPLL

1

C425

2

1

2

C292

0.1U_0402_16V4Z

1

C248

C266

2

220U_D2_4VM

0.1U_0402_16V4Z

Place closely pin
D28,T28,AD28.

0.1U_0402_16V4Z

1

+1.5VS

2

0.1U_0402_16V4Z

0.01U_0402_16V7K

Place closely pin AG5.

+1.5VS

C236

1U_0603_10V4Z

0.1U_0402_16V4Z

Place closely pin AG9.

1

2

T18 PAD
T19 PAD

+3V_SB

ICH_V5REF_RUN

ICH_V5REF_SUS

1

1

C291

2

2

0.1U_0402_16V4Z

+3VS

1

C293

2

+1.5VS_DMIPLL

1

C238

2

1

C241

2

1 2

R226 0_0805_5%

ICH_AA2
ICH_Y7

G10

AD17

F6

AA22
AA23
AB22
AB23
AC23
AC24
AC25
AC26
AD26
AD27
AD28

D26
D27
D28

E24
E25
E26
F23

F24
G22
G23
H22
H23

J22

J23
K22
K23
L22
L23

M22
M23
N22
N23

P22
P23

R22
R23
R24
R25
R26

T22
T23
T26
T27
T28

U22
U23

V22
V23

W22
W23

Y22
Y23

B27

AG28

AB7
AC6
AC7
AD6
AE6
AF5
AF6
AG5
AH5

AD2
AH11
AB10

AB9
AC10
AD10
AE10
AF10

AF9

AG9

AH9

E3
C1

AA2

Y7
V5

V1
W2
W7

1

C258

0.1U_0402_16V4Z

2

U34F

V5REF[1]
V5REF[2]
V5REF_Sus
Vcc1_5_B[1]

Vcc1_5_B[2]
Vcc1_5_B[3]
Vcc1_5_B[4]
Vcc1_5_B[5]
Vcc1_5_B[6]
Vcc1_5_B[7]
Vcc1_5_B[8]
Vcc1_5_B[9]
Vcc1_5_B[10]
Vcc1_5_B[11]
Vcc1_5_B[12]
Vcc1_5_B[13]
Vcc1_5_B[14]
Vcc1_5_B[15]
Vcc1_5_B[16]
Vcc1_5_B[17]
Vcc1_5_B[18]
Vcc1_5_B[19]
Vcc1_5_B[20]
Vcc1_5_B[21]
Vcc1_5_B[22]
Vcc1_5_B[23]
Vcc1_5_B[24]
Vcc1_5_B[25]
Vcc1_5_B[26]
Vcc1_5_B[27]
Vcc1_5_B[28]
Vcc1_5_B[29]
Vcc1_5_B[30]
Vcc1_5_B[31]
Vcc1_5_B[32]
Vcc1_5_B[33]
Vcc1_5_B[34]
Vcc1_5_B[35]
Vcc1_5_B[36]
Vcc1_5_B[37]
Vcc1_5_B[38]
Vcc1_5_B[39]
Vcc1_5_B[40]
Vcc1_5_B[41]
Vcc1_5_B[42]
Vcc1_5_B[43]
Vcc1_5_B[44]
Vcc1_5_B[45]
Vcc1_5_B[46]
Vcc1_5_B[47]
Vcc1_5_B[48]
Vcc1_5_B[49]
Vcc1_5_B[50]
Vcc1_5_B[51]
Vcc1_5_B[52]
Vcc1_5_B[53]

Vcc3_3[1]
VccDMIPLL
Vcc1_5_A[1]

Vcc1_5_A[2]
Vcc1_5_A[3]
Vcc1_5_A[4]
Vcc1_5_A[5]
Vcc1_5_A[6]
Vcc1_5_A[7]
Vcc1_5_A[8]
Vcc1_5_A[9]

VccSATAPLL
Vcc3_3[2]
Vcc1_5_A[10]

Vcc1_5_A[11]
Vcc1_5_A[12]
Vcc1_5_A[13]
Vcc1_5_A[14]
Vcc1_5_A[15]
Vcc1_5_A[16]
Vcc1_5_A[17]
Vcc1_5_A[18]

VccSus3_3[19]
VccUSBPLL
VccSus1_05/VccLAN1_05[1]

VccSus1_05/VccLAN1_05[2]
VccSus3_3/VccLAN3_3[1]

VccSus3_3/VccLAN3_3[2]
VccSus3_3/VccLAN3_3[3]
VccSus3_3/VccLAN3_3[4]

ICH7_BGA652~D

+VCCP

L11

Vcc1_05[1]

L12

Vcc1_05[2]

L14

Vcc1_05[3]

L16

Vcc1_05[4]

L17

Vcc1_05[5]

L18

Vcc1_05[6]

M11

Vcc1_05[7]

M18

Vcc1_05[8]

P11

Vcc1_05[9]

P18

Vcc1_05[10]

T11

Vcc1_05[11]

T18

Vcc1_05[12]

U11

Vcc1_05[13]

U18

Vcc1_05[14]

V11

Vcc1_05[15]

V12

Vcc1_05[16]

V14

Vcc1_05[17]

V16

Vcc1_05[18]

V17

Vcc1_05[19]

V18

Vcc1_05[20]

Vcc3_3[3]
Vcc3_3[4]
Vcc3_3[5]
Vcc3_3[6]
Vcc3_3[7]
Vcc3_3[8]

Vcc3_3[9]
Vcc3_3[10]
Vcc3_3[11]

Vcc3_3[12]
Vcc3_3[13]
Vcc3_3[14]
Vcc3_3[15]
Vcc3_3[16]
Vcc3_3[17]
Vcc3_3[18]
Vcc3_3[19]
Vcc3_3[20]
Vcc3_3[21]

VccRTC

U6
R7
AE23

AE26
AH26

AA7
AB12
AB20
AC16
AD13
AD18
AG12
AG15
AG19

A5
B13
B16
B7
C10
D15
F9
G11
G12
G16

W5
P7
A24

C24
D19
D22
G19

K3
K4
K5
K6
L1
L2
L3
L6
L7
M6
M7
N7

AB17
AC17

T7
F17
G17

AB8
AC8

K7
C28

G20
A1

H6
H7
J6
J7

Vcc3_3 / VccHDA

VccSus3_3/VccSusHDA

V_CPU_IO[1]
V_CPU_IO[2]
V_CPU_IO[3]

VccSus3_3[1]
VccSus3_3[2]

VccSus3_3[3]
VccSus3_3[4]
VccSus3_3[5]
VccSus3_3[6]

VccSus3_3[7]
VccSus3_3[8]

VccSus3_3[9]
VccSus3_3[10]
VccSus3_3[11]
VccSus3_3[12]
VccSus3_3[13]
VccSus3_3[14]
VccSus3_3[15]
VccSus3_3[16]
VccSus3_3[17]
VccSus3_3[18]

Vcc1_5_A[19]
Vcc1_5_A[20]

Vcc1_5_A[21]
Vcc1_5_A[22]
Vcc1_5_A[23]

Vcc1_5_A[24]

Vcc1_5_A[25]
VccSus1_05[1]
VccSus1_05[2]

VccSus1_05[3]

Vcc1_5_A[26]

Vcc1_5_A[27]

Vcc1_5_A[28]

Vcc1_5_A[29]

Vcc1_5_A[30]

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

0.1U_0402_16V4Z

1

1

1

C279

C272

2

1U_0603_10V4Z

1

C290

2

1

C274

2

0.1U_0402_16V4Z

1

C280

0.1U_0402_16V4Z

2

1 2

C286 0.1U_0402_16V4Z

ICH_K7
ICH_C28

ICH_G20

1

C295

0.1U_0402_16V4Z

2

2005/12/1 2006/12/01

2

1

C253

0.1U_0402_16V4Z

2

1

C297

2

0.1U_0402_16V4Z

1

2

+1.5VS

+1.5VS

+

C262
220U_D2_4VM

2

+3V_SB

+3VS

+3VS

1

C285

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1 2

R512

0_0805_5%

C298

0.1U_0402_16V4Z

1 2

R513

1

2

C277

0.1U_0402_16V4Z

T24PAD
T32PAD

T26PAD

0_0805_5%

Compal Secret Data

Deciphered Date

+VCCP

0.1U_0402_16V4Z

0.1U_0402_16V4Z

4.7U_0805_10V4Z

+3V_SB

C244

1 2

1 2

C245

1 2

C234

+3V_SB

C259

1

2

1

2

0.1U_0402_16V4Z

+3VS

C264

0.1U_0402_16V4Z

+RTCVCC

1

C261

2

0.1U_0402_16V4Z

U34E

A4

VSS[0]

A23

VSS[1]

B1

VSS[2]

B8

VSS[3]

B11

VSS[4]

B14

VSS[5]

B17

VSS[6]

B20

VSS[7]

B26

VSS[8]

B28

VSS[9]

C2

VSS[10]

C6

VSS[11]

C27

VSS[12]

D10

VSS[13]

D13

VSS[14]

D18

VSS[15]

D21

VSS[16]

D24

VSS[17]

E1

VSS[18]

E2

VSS[19]

E4

VSS[21]

E8

VSS[22]

E15

VSS[23]

F3

VSS[24]

F4

VSS[25]

F5

VSS[26]

F12

VSS[27]

F27

VSS[28]

F28

VSS[29]

G1

VSS[30]

G2

VSS[31]

G5

VSS[32]

G6

VSS[33]

G9

VSS[34]

G14

VSS[35]

G18

VSS[36]

G21

VSS[37]

G24

VSS[38]

G25

VSS[39]

G26

VSS[40]

H3

VSS[41]

H4

VSS[42]

H5

VSS[43]

H24

VSS[44]

H27

VSS[45]

H28

VSS[46]

J1

VSS[47]

J2

VSS[48]

J5

VSS[49]

J24

VSS[50]

J25

VSS[51]

J26

VSS[52]

K24

VSS[53]

K27

VSS[54]

K28

VSS[55]

L13

VSS[56]

L15

VSS[57]

L24

VSS[58]

L25

VSS[59]

L26

VSS[60]

M3

VSS[61]

M4

VSS[62]

M5

VSS[63]

M12

VSS[64]

M13

VSS[65]

M14

VSS[66]

M15

VSS[67]

M16

VSS[68]

M17

VSS[69]

M24

VSS[70]

M27

VSS[71]

M28

VSS[72]

N1

VSS[73]

N2

VSS[74]

N5

VSS[75]

N6

VSS[76]

N11

VSS[77]

N12

VSS[78]

N13

VSS[79]

N14

VSS[80]

N15

VSS[81]

N16

VSS[82]

N17

VSS[83]

N18

VSS[84]

N24

VSS[85]

N25

VSS[86]

N26

VSS[87]

P3

VSS[88]

P4

VSS[89]

P12

VSS[90]

P13

VSS[91]

P14

VSS[92]

P15

VSS[93]

P16

VSS[94]

P17

VSS[95]

P24

VSS[96]

P27

VSS[97]

ICH7_BGA652~D

Title

Size Document Number Rev

Custom

Date: Sheet

ICH7-Power/GND
LA-3271P

VSS[98]

VSS[99]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
VSS[159]
VSS[160]
VSS[161]
VSS[162]
VSS[163]
VSS[164]
VSS[165]
VSS[166]
VSS[167]
VSS[168]
VSS[169]
VSS[170]
VSS[171]
VSS[172]
VSS[173]
VSS[174]
VSS[175]
VSS[176]
VSS[177]
VSS[178]
VSS[179]
VSS[180]
VSS[181]
VSS[182]
VSS[183]
VSS[184]
VSS[185]
VSS[186]
VSS[187]
VSS[188]
VSS[189]
VSS[190]
VSS[191]
VSS[192]
VSS[193]
VSS[194]

P28
R1
R11
R12
R13
R14
R15
R16
R17
R18
T6
T12
T13
T14
T15
T16
T17
U4
U12
U13
U14
U15
U16
U17
U24
U25
U26
V2
V13
V15
V24
V27
V28
W6
W24
W25
W26
Y3
Y24
Y27
Y28
AA1
AA24
AA25
AA26
AB4
AB6
AB11
AB14
AB16
AB19
AB21
AB24
AB27
AB28
AC2
AC5
AC9
AC11
AD1
AD3
AD4
AD7
AD8
AD11
AD15
AD19
AD23
AE2
AE4
AE8
AE11
AE13
AE18
AE21
AE24
AE25
AF2
AF4
AF8
AF11
AF27
AF28
AG1
AG3
AG7
AG11
AG14
AG17
AG20
AG25
AH1
AH3
AH7
AH12
AH23
AH27

of

18 42Monday, August 21, 2006

0.4

5

4

3

2

1

JODD1

GND

2
4
6
8

10

ODD_ACT_LED#

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54

IDE_DD8
IDE_DD9
IDE_DD10
IDE_DD11
IDE_DD12
IDE_DD13
IDE_DD14
IDE_DD15

PDIAG#

1 2

R347
100K_0402_5%

@

R112 10K_0402_5%@

1 2

80mils

IDE_DDREQ 16
IDE_DIOR# 16

IDE_DDACK# 16

IDE_DA2 16

+5VS

+5VS

IDE_DD[0..15] 16

+5VS

+5VS

10U_0805_10V4Z

1

C387

2

1U_0603_10V4Z

Close to ODD Conn

1

C392

2

0.1U_0402_16V4Z

1

C390

2

1

C148

2

1000P_0402_50V7K~N

+3VS

12

R358

10K_0402_5%

RB751V_SOD323

+5VS

12

ODD_ACT_LED#

D22

21

If CDROM is Slave
then SD_CSEL= Floating

D D

C C

IDE_RESET#17

100K_0402_5%

R356

C169 47P_0402_50V8J

12

IDE_DD7
IDE_DD6
IDE_DD5
IDE_DD4
IDE_DD3
IDE_DD2
IDE_DD1
IDE_DD0

IDE_DIOW#16

IDE_DIORDY16

IDE_IRQ16
IDE_DA116
IDE_DA016

IDE_DCS1#16 IDE_DCS3# 16

+5VS

SD_CSEL

12

R349 470_0402_5%

ODD_ACT_LED#29

CDROM CONN

1

1

3

3

5

5

7

7

9

9
111112
131314
151516
171718
191920
212122
232324
252526
272728
292930
313132
333334
353536
373738
393940
414142
434344
454546
474748
494950
GND51GND

53

GND

SUYIN_800059MR050S119ZL

CONN@

else SD_CSEL= Low

+5VS

SATA HDD CONN

JSATA1

S1

PSATA_ITX_DRX_P016

B B

PSATA_ITX_DRX_N016

PSATA_IRX_DTX_N0_C16
PSATA_IRX_DTX_P0_C16

Pin swap

PSATA_IRX_DTX_P0
PSATA_IRX_DTX_N0

C460 3900P_0402_50V7K

12
12

C458 3900P_0402_50V7K

+3VS

+5VS

GND

S2

HTX+

S3

HTX-

S4

GND

S5

HRX-

S6

HRX+

S7

GND

NC

VCC3.3
VCC3.3
VCC3.3
GND
GND
GND
VCC5
VCC5
VCC5
GND
RESERVED
GND
VCC12
VCC12
VCC12

GND
GND
GND
GND

NC

P1
P2
P3
P4
P5
P6
P7
P8

P9
P10
P11
P12
P13
P14
P15

SUYIN_127043FR022G226ZL

CONN@

27
28

23
24
25
26

C420

150U_D2_6.3VM

1

+

2

+3VS

10U_0805_10V4Z

1

C452

2

10U_0805_10V4Z

1

C423

2

0.1U_0402_16V4Z

1

C444

2

0.1U_0402_16V4Z

Close to SATA HDD

1

C430

2

0.1U_0402_16V4Z

C447

0.1U_0402_16V4Z

C432

1

2

1

C427

2

1000P_0402_50V7K~N

1

C441

2

1000P_0402_50V7K~N

1

2

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/12/1 2006/12/01

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

HDD/CDROM
LA-3271P

1

0.4

of

19 42Monday, August 21, 2006

5

PCI_AD[0..31]15

D D

R5C811 & R5C841
PULL DOWN :Disable media card function

R204 10K_0402_5%

1 2

R201 10K_0402_5%

1 2

C C

+3V

12

R441
100K_0402_5%

CBS_GRST#

1

C434
1U_0603_10V4Z

2

R449

C435

CLK_PCI_CB

@

10_0402_5%

12

@

4.7P_0402_50V8C

CLK_PCI_CB_TERM

2

1

B B

A A

PCI_AD21

CLK_PCI_CB13

PCI_RST#15,23

PCI_CLKRUN#17,26

+3V

+3V

5

UDIO3
UDIO4

PCI_CBE#315,22
PCI_CBE#215
PCI_CBE#115
PCI_CBE#015

PCI_PAR15

PCI_FRAME#15
PCI_TRDY#15
PCI_IRDY#15
PCI_STOP#15
PCI_DEVSEL#15,22

1 2

PCI_PERR#15
PCI_SERR#15

PCI_REQ0#15
PCI_GNT0#15

SHIELD GND

R198 0_0402_5%@

1 2

R199 10K_0402_5%

1 2

PCI_PIRQE#15
PCI_PIRQF#15
PCI_PIRQG#15 CBS_CVS1 21

WLANPME#26

PCM_SPK#25

1 2
1 2

1 2

SERIRQ

12

SERIRQ17,23,26

R203 10K_0402_5%@
R202 10K_0402_5%@

R450 10K_0402_5%
R446 100K_0402_5%

PCI_AD31
PCI_AD30
PCI_AD29
PCI_AD28
PCI_AD27
PCI_AD26
PCI_AD25
PCI_AD24
PCI_AD23
PCI_AD22
PCI_AD21
PCI_AD20
PCI_AD19
PCI_AD18
PCI_AD17
PCI_AD16
PCI_AD15
PCI_AD14
PCI_AD13
PCI_AD12
PCI_AD11
PCI_AD10
PCI_AD9
PCI_AD8
PCI_AD7
PCI_AD6
PCI_AD5
PCI_AD4
PCI_AD3

W11

PCI_AD2
PCI_AD1
PCI_AD0

W12

PCI_PAR

PCI_FRAME#
PCI_TRDY#
PCI_IRDY#
PCI_STOP#
PCI_DEVSEL# CBS_CDEVSEL#
CBS_IDSEL

R448100_0402_5%

PCI_PERR#
PCI_SERR#

PCI_RST#
CBS_GRST#

UDIO3
UDIO4

PCM_SPK#

IEEE1394_TPBIAS0

IEEE1394_TPAP0
IEEE1394_TPAN0
IEEE1394_TPBP0
IEEE1394_TPBN0

@

R518

@

R519

@

C547

56.2_0603_1%

12

56.2_0603_1%

12

Z3008

270P_0402_50V7K

2

1

4

U33A

M2

AD31

M1

AD30

N5

AD29

N4

AD28

N2

AD27

N1

AD26

P5

AD25

P4

AD24

R4

AD23

R2

AD22

R1

AD21

T2

AD20

T1

AD19

U2

AD18

U1

AD17

V1

AD16

T7

AD15

V7

AD14

W7

AD13

R8

AD12

T8

AD11

V8

AD10

W8

AD9

R9

AD8

V9

AD7

W9

AD6

T11

AD5

V11

AD4
AD3

T12

AD2

V12

AD1
AD0

P2

C/BE3#

W2

C/BE2#

W6

C/BE1#

T9

C/BE0#

V6

PAR

V3

FRAME#

W4

TRDY#

V4

IRDY#

V5

STOP#

T5

DEVSEL#

P1

IDSEL

W5

PERR#

T6

SERR#

M4

REQ#

M5

GNT#

K1

PCICLK

L4

PCIRST#

G2

GBRST#

L5

CLKRUN#

J2

INTA#

K4

INTB#

K2

INTC#

J4

UDIO0/SERIRQ#

H1

UDIO1

H2

UDIO2

H4

UDIO3

H5

UDIO4

G1

UDIO5

G4

RI_OUT#/PME#

F1

SPKROUT

F2

HWSPND#

F4

TEST

R5C841_CSP208~D

CAD31/CDATA10

CAD30/CDATA9
CAD29/CDATA1

R5C841

CSTSCHG/BVD1(STSCHG#/RI#)

CAD28/CDATA8
CAD27/CDATA0

CAD26/CADR0
CAD25/CADR1
CAD24/CADR2
CAD23/CADR3
CAD22/CADR4
CAD21/CADR5
CAD20/CADR6

CAD19/CADR25

CAD18/CADR7
CAD17/CADR24
CAD16/CADR17

CAD15/IOWR#

CAD14/CADR9

CAD13/IORD#

CAD12/CADR11

CAD9/CADR10
CAD8/CDATA15

CAD7/CDATA7
CAD6/CDATA13

CAD5/CDATA6
CAD4/CDATA12

CAD3/CDATA5
CAD2/CDATA11

CAD1/CDATA4

CAD0/CDATA3

CC/BE3#/REG#

CC/BE2#/CADR12

CC/BE1#/CADR8

CC/BE0#/CE1#

CPAR/CADR13

CFRAME#/CADR23

CTRDY#/CADR22

CIRDY#/CADR15

CSTOP#/CADR20

CDEVSEL#/CADR21

RESERVED/CADR19

CPERR#/CADR14

CSERR#/WAIT#

CREQ#/INPACK#

CCLKRUN#/WP(IOIS16#)

CCLK/CADR16

CINT#/RDY(IREQ#)

CRST#/RESET

CAUDIO/BVD2(SPKR#/LED)

RESERVED/CDATA14

RESERVED/CDATA2
RESERVED/CADR18

CAD11/OE#

CAD10/CE2#

CGNT#/WE#

CCD1#/CD1#
CCD2#/CD2#

CVS1/VS1#
CVS2/VS2#

CBS_CAD31

B19

CBS_CAD30

C18

CBS_CAD29

D19

CBS_CAD28

D18

CBS_CAD27

E19

CBS_CAD26

E16

CBS_CAD25

F18

CBS_CAD24

F15

CBS_CAD23

G18

CBS_CAD22

G15

CBS_CAD21

H18

CBS_CAD20

H15

CBS_CAD19

J18

CBS_CAD18

J16

CBS_CAD17

J15

CBS_CAD16

P16

CBS_CAD15

P19

CBS_CAD14

R19

CBS_CAD13

P18

CBS_CAD12

R18

CBS_CAD11

T19

CBS_CAD10

T18

CBS_CAD9

U19

CBS_CAD8

U18

CBS_CAD7

W17

CBS_CAD6

V17

CBS_CAD5

W16

CBS_CAD4

V16

CBS_CAD3

W15

CBS_CAD2

V15

CBS_CAD1

T15

CBS_CAD0

R14

CBS_CC/BE3#

F16

CBS_CC/BE2#

K18

CBS_CC/BE1#

P15

CBS_CC/BE0#

V19

CBS_CPAR

N15

CBS_CFRAME#

K16
L16

CBS_CIRDY#

K15

CBS_CSTOP#

M16
L18

CBS_CBLOCK#

N19

CBS_CPERR#

N18

CBS_CSERR#

G16

CBS_CREQ#

G19

CBS_CGNT#

M15

CBS_CSTSCHNG

E18

CBS_CCLKRUN#

A18

CBS_CCLK_INTERNAL

L19

CBS_CINT#

M18

CBS_CRST#

H19

CBS_CAUDIO

F19

CBS_CCD1C#

T14

CBS_CCD2C#

D15

CBS_CVS1

R16

CBS_CVS2

H16

CBS_RSVD/D14

W18

CBS_RSVD/D2

C19

CBS_RSVD/A18

N16

apply same length for set of TPA+,TPA-and TPB+,TPB-

0.33U_0603_10V7K

0.01U_0402_16V7K

56.2_0603_1%

@

@

12

R520

56.2_0603_1%

@

12

R517

5.1K_0603_1%

@

R521

1 2

Placement Near Card Bus Controller

@

1

1

C535

C531

2

2

8

4

4

3

3

2

GND15GND26GND37GND4

2

1

1

SUYIN_020204FR004S506ZL
J139A1

CONN@

4

3

R480 22_0402_5%

1 2

C283 0.01U_0402_16V7K

CBS_CAUDIO 21

CBS_CAD[0..31] 21

[1]

C465

@

22P_0402_50V8J

C464

@

22P_0402_50V8J

CBS_CC/BE3# 21
CBS_CC/BE2# 21
CBS_CC/BE1# 21
CBS_CC/BE0# 21

CBS_CPAR 21

CBS_CFRAME# 21
CBS_CTRDY# 21
CBS_CIRDY# 21
CBS_CSTOP# 21
CBS_CDEVSEL# 21
CBS_CBLOCK# 21
CBS_CPERR# 21

CBS_CSERR# 21
CBS_CREQ# 21

CBS_CGNT# 21

CBS_CSTSCHNG 21

CBS_CCLKRUN# 21

12

CBS_CINT# 21

CBS_CRST# 21

CBS_CVS2 21

CBS_RSVD/D14 21
CBS_RSVD/D2 21
CBS_RSVD/A18 21

R5C841XI

12

X1

@

24.576MHz_16P_3XG-24576-43E1

1 2

R5C841XO

12

0.01U_0402_16V7K

[1]

C457

2

1

1 2

0_0402_5%

R481

1 2

270P_0402_50V7K

C467

2

1

10K_0603_1%

R474

CBS_CCLK 21

R234
0_0402_5%

1 2

270P_0402_50V7K

C275

2

1

[1]

VCC5EN#21
VCC3EN#21

C271 0.01U_0402_16V7K

1 2

1 2

VPPEN021
VPPEN121

1 2

R224
100K_0402_5%

CBS_CCD2# 21
CBS_CCD1# 21

+3V_PHY

R5C841XI
R5C841XO

IEEE1394_TPAP0
IEEE1394_TPAN0

IEEE1394_TPBP0
IEEE1394_TPBN0

[1]

R468

0_0402_5%

IEEE1394_TPBIAS0

[1]

2

R216

12

D11
A16

B16
A14

B12
A12

B13
A13

B10
A10

B11
A11

D12
D10

D13
B14

V14

W14

V13

W13

R13
T13

R7

100K_0402_5%

[1]

[1] For R5C811, these parts are NOT installed.

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/12/1 2006/12/01

Compal Secret Data

Deciphered Date

2

U33B

CPS

R5C841

XI
XO
FIL0

TPAP0
TPAN0

TPBP0
TPBN0

TPAP1
TPAN1

TPBP1
TPBN1

TPBIAS0
TPBIAS1

VREF
REXT

USBDP
USBDM

VPPEN0
VPPEN1

VCC5EN#
VCC3EN#

REGEN#

R5C841_CSP208~D

1

B1

MDIO00

A2

MDIO01

A3

MDIO02

B3

MDIO03

B4

MDIO04

A5

MDIO05

B5

MDIO06
MDIO07
MDIO08
MDIO09
MDIO10
MDIO11
MDIO12
MDIO13
MDIO14
MDIO15
MDIO16
MDIO17
MDIO18
MDIO19

D5
A6
B6
D6
E6
A7
B7
D7
E7
A8
B8
D8
E8

1 2

R210 0_0402_5%

@

Function Seclect

UDIO3 UDIO4 VPPEN0 SD MS

0

*

00

00 1

01 0

101

010

10 1

11 0

11 1

Title

Size Document Number Rev

Date: Sheet

CardBus Controller(R5C841)

Monday, August 21, 2006

LA-3271P

XX

XX

EnableX

Enable EnableX

Enable X X

Enable EnableX

Enable Enable X

Enable Enable Enable

of

1

20 42

Enable

0.4

5

+3V

*as close as possible to VCC_3V pin

10U_0805_10V4Z

0.01U_0402_16V7K

C287

C282

C254

1

1

2

2

+3VS

D D

*as close as possible to VCC_PCI pin

10U_0805_10V4Z

C242

C267

1

2

C263

C C

B B

VPPEN020
VPPEN120

VCC3EN#20
VCC5EN#20

A A

0.01U_0402_16V7K

C302

0.01U_0402_16V7K

+3V

C250

1

1

2

2

C440

1

2

0.1U_0402_16V4Z

0.01U_0402_16V7K

C270

C256

1

1

1

2

2

2

1U_0603_10V4Z

0.1U_0402_16V4Z

+5V

1

0.1U_0402_16V4Z

2

C475

1

2

0.01U_0402_16V7K

C268

1

2

+3V

*as close as possible to VCC_RIN pin

10U_0805_10V4Z

C269

2

1

0.01U_0402_16V7K

1

2

0.01U_0402_16V7K

+3V_PHY

0.01U_0402_16V7K

C284

1

2

R219 0_0402_5%

1 2

R221 0_0402_5%

1 2

R236 0_0402_5%

1 2

R239 0_0402_5%

1 2

0.01U_0402_16V7K

C257

1

2

*as close as possible to VCC_MD3V pin

10U_0805_10V4Z

C251

1

2

0.01U_0402_16V7K

[1]

0.01U_0402_16V7K

C276

C243

1

1

2

2

U35

11

VCC3IN

VCCOUT
VCCOUT

13
15

3
4

2
1

5

16

VCCOUT

VCC5IN
VCC5IN

EN0

VPPOUT

EN1

VCC3_EN
VCC5_EN

FLG
GND

R5531V002-E2-FA_SSOP16~D

NC
NC
NC

U33C

F5

G5

J19

K19

W3
R11
R12

A4

R6

E13

L1

E14

E10
E11
A17
B17

A9
B9

D9
D14
A15
B15

J1
J5
K5
E9

R10

T10

V10

W10

L15

M19

R5C841_CSP208~D

9
14
12

+CBS_VPP

8

C483

7
6
10

VCC_3V1
VCC_3V2
VCC_3V3
VCC_3V4

VCC_PCI3V1
VCC_PCI3V2
VCC_PCI3V3

VCC_MD3V

VCC_RIN1
VCC_RIN2

VCC_ROUT1
VCC_ROUT2

AVCC_PHY1
AVCC_PHY2
AVCC_PHY3
AVCC_PHY4

AGND1
AGND2
AGND3
AGND4
AGND5
AGND6

GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8
GND9
GND10

1

2

0.1U_0402_16V4Z
C482

1

2

4

R5C841

+CBS_VCC+3V

0.01U_0402_16V7K

C484

1

2

0.01U_0402_16V7K

NC1
NC2
NC3
NC4
NC5
NC6
NC7
NC8
NC9

3

CBS_CAD13 CBS_CAD13_L

CBS_CAD15 CBS_CAD15_L

L2
C1
D1
E1
C2
D2
E2
E4
E12

1.on top or bottom layer

2.no via hole

3.90 Ohm compliant with USB platform

BLM21A601SPT_0805@

BLM21A601SPT_0805@

L24

1 2

L25

1 2

R484

1 2

R490

1 2

0_0402_5%

0_0402_5%

2

L26

1 2

+3V

BLM21A601SPT_0805

C476

1

+3V_PHY

1

2

22U_1206_10V4Z

C487

1

1

2

0.1U_0402_16V4Z

C480

1

1

C486

C485

2

2

2

0.1U_0402_16V4Z
1000P_0402_50V7K~N

1000P_0402_50V7K~N

[1]

USB Signals for Epress Card

JPC1

CBS_CAD0
CBS_CAD1
CBS_CAD3
CBS_CAD5
CBS_CAD7

CBS_CC/BE0#20

1

C479

2

10U_0805_10V4Z

CBS_CCLK20

@

CBS_CC/BE1#20
CBS_CPAR20
CBS_CPERR#20
CBS_CGNT#20

CBS_CINT#20

+CBS_VCC

+CBS_VPP +CBS_VPP

CBS_CCLK_E

CBS_CIRDY#20

12

CBS_CC/BE2#20

R472

@

2

33_0402_5%

C455
22P_0402_50V8J

1

CBS_RSVD/D220
CBS_CCLKRUN#20

CBS_CC/BE0#
CBS_CAD9
CBS_CAD11

CBS_CC/BE1#
CBS_CPAR
CBS_CPERR# CBS_CBLOCK#
CBS_CGNT#
CBS_CINT#

CBS_CIRDY#
CBS_CC/BE2#

CBS_CAD20
CBS_CAD21
CBS_CAD22
CBS_CAD23
CBS_CAD24
CBS_CAD25
CBS_CAD26

CBS_RSVD/D2
CBS_CCLKRUN#

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34

69
70
71
72
73
74
75
76
77
78

FOX_WZ21131-HR-9F_RB

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

CONN@

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

35

35

36

36

37

37

38

38

39

39

40

40

41

41

42

42

43

43

44

44

45

45

46

46

47

47

48

48

49

49

50

50

51

51

52

52

53

53

54

54

55

55

56

56

57

57

58

58

59

59

60

60

61

61

62

62

63

63

64

64

65

65

66

66

67

67

68

68

79
80
81
82
83
84
85
86
87
88

89

NC

90

NC

CBS_CCD1#
CBS_CAD2
CBS_CAD4
CBS_CAD6
CBS_RSVD/D14
CBS_CAD8
CBS_CAD10
CBS_CVS1
CBS_CAD13_LCBS_CAD12
CBS_CAD15_LCBS_CAD14
CBS_CAD16
CBS_RSVD/A18

CBS_CSTOP#
CBS_CDEVSEL#

CBS_CTRDY#
CBS_CFRAME#
CBS_CAD17
CBS_CAD19CBS_CAD18
CBS_CVS2
CBS_CRST#
CBS_CSERR#
CBS_CREQ#
CBS_CC/BE3#
CBS_CAUDIO
CBS_CSTSCHNG
CBS_CAD28CBS_CAD27
CBS_CAD30CBS_CAD29
CBS_CAD31
CBS_CCD2#

CBS_CRST#

CBS_CCD1# 20

CBS_RSVD/D14 20

CBS_CVS1 20

CBS_RSVD/A18 20
CBS_CBLOCK# 20
CBS_CSTOP# 20
CBS_CDEVSEL# 20

+CBS_VCC

CBS_CTRDY# 20
CBS_CFRAME# 20

CBS_CVS2 20
CBS_CRST# 20
CBS_CSERR# 20
CBS_CREQ# 20
CBS_CC/BE3# 20
CBS_CAUDIO 20
CBS_CSTSCHNG 20

CBS_CCD2# 20

2

C278

0.01U_0402_16V7K

1

CBS_CAD31
CBS_CAD30
CBS_CAD29
CBS_CAD28
CBS_CAD27
CBS_CAD26
CBS_CAD25
CBS_CAD24
CBS_CAD23
CBS_CAD22
CBS_CAD21
CBS_CAD20
CBS_CAD19
CBS_CAD18
CBS_CAD17
CBS_CAD16
CBS_CAD15
CBS_CAD14
CBS_CAD13
CBS_CAD12
CBS_CAD11
CBS_CAD10
CBS_CAD9
CBS_CAD8
CBS_CAD7
CBS_CAD6
CBS_CAD5
CBS_CAD4
CBS_CAD3
CBS_CAD2
CBS_CAD1
CBS_CAD0

CBS_CAD[0..31] 20

[1] For R5C811, these parts are NOT installed.

JSD1 Pin3

JSD1 Pin1

5

Short (L)

4

SD UnWP
SD WPOpen (H)

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/12/1 2006/12/01

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

2

Date: Sheet

Compal Electronics, Inc.

1394 & Media Card

Monday, August 21, 2006

LA-3271P

1

21 42

0.4

of

5

4

3

2

1

Layout Notice : 3.3V filter. Place as close

Layout Notice : Filter place as close
chip as possible.

+2.5VLAN

D D

C C

L14 FBM-L11-160808-601LMT_0603

L13 FBM-L11-160808-601LMT_0603

L15 FBM-L11-160808-601LMT_0603

+1.2VLAN

L1 FBM-L11-160808-601LMT_0603

4.7U_0805_6.3V6K

L18 FBM-L11-160808-601LMT_0603

4.7U_0805_6.3V6K

L17 FBM-L11-160808-601LMT_0603

4.7U_0805_6.3V6K

L12 FBM-L11-160808-601LMT_0603

4.7U_0805_6.3V6K

0.1U_0402_16V4Z

0.1U_0402_16V4Z

12

C21

12

C343

12

C345

12

C331

12

C340

12

C333

12

2

1

2

1

2

1

1

2

XTALVDD

2

1

2

C319

1

0.1U_0402_16V4Z

+LAN_BIASVDD

1

C341

0.1U_0402_16V4Z

2

AVDDL

2

C15

0.1U_0402_16V4Z

1

GPHY_PLLVDD

2

C344

0.1U_0402_16V4Z

1

PCIE_PLLVDD

2

C347

0.1U_0402_16V4Z

1

PCIE_VDD

2

C334

0.1U_0402_16V4Z

1

2

1

2

C332

0.1U_0402_16V4Z

1

+3VALW

+LAN_AVDD

close to each of the pins 38, 45, and 52

D

6
2

1

G

EN_WOL30

3

(CLKREQ#) and (ENERGY_DET) are
only supported in BCM5787M

L16

Q28

FBM-L11-321611-260-LMT_1206

S

+3V_LAN

45

SI3456BDV-T1-E3_TSOP6

PCI_DEVSEL#15,20

CLKREQC#13

1 2

PCI_CBE#315,20

No CIS Symbol

@

4.7K_0402_5%

Layout Notice : Place as close
chip as possible.

B B

A A

+2.5VLAN

0.1U_0402_16V4Z

C335

22U_1206_10V4Z

C328

2

2

1

1

Close to Q12

C322

R10

0.1U_0402_16V4Z

2

1

C20

0_0402_5%

GPIO1

R8

@

200_0603_1%

Y2

1 2

25MHZ_16P_XSL025000FK1H

2

1

27P_0402_50V8J

+3VLAN

R9
0_0402_5%

1 2

0.1U_0402_16V4Z

12

C19

2

1

12

5751_SI

AT45DB011B-SU_SO8~N

@

4.7K_0402_5%

XTALO

XTALI

2

C16

1

27P_0402_50V8J

U2

8

SO

7

GND

6

RESET#

VCC

5

WP#

R884,R864 stuff if U61 is installed

5

4

Layout Notice : Place as close
chip as possible.

C342

4.7U_0805_10V4Z

PCI_DEVSEL#

1 2

R7

@

CLKREQC#

1 2

R401

@

R304 1K_0402_5%

+3VS

R305 1K_0402_5%

+3VLAN

R306 0_0402_5%@

PCIE_TXN117
PCIE_TXP117

PCIE_RXN117

PCIE_RXP117

PLT_RST#9,15,17,23,26

PCIE_PME#26

SMBus to support ASF

1 2

R313

1 2

R314

SCK
CS#

SCLK
5751_SI
CS#

GPIO1

GPIO2

5751_SO

1

SI

SCLK

2
3

+3VLAN

CS#

4

1 2

R332 4.7K_0402_5%@
R318 4.7K_0402_5%

1 2

R300 4.7K_0402_5%@

2

C326

1

0.1U_0402_16V4Z

CLK_PCIE_LAN#13

CLK_PCIE_LAN13

LAN_LOW_PWR26

1 2
1 2

1 2

+3VLAN

12

12

R311

@

4.7K_0402_5%

12

2

C13

C339

1

0.1U_0402_16V4Z

0_0402_5%
0_0402_5%

GPHY_PLLVDD

C17

0.1U_0402_16V7K~N

C18

0.1U_0402_16V7K~N

LAN_SMBCLK23
LAN_SMBDATA23

1 2

SPROM_WP

1 2

R312

@

4.7K_0402_5%

+3VLAN

2

2

C9

1

1

0.1U_0402_16V4Z

0.1U_0402_16V4Z

U1

28
29
11

3

CBE#1

53
54

CBE#3

59
35
32

R310
0_0402_5%

R315
0_0402_5%

XTALI
XTALO

GPIO1
GPIO2

31
25
26

10
12

58
57

4
7
8
9

21
22

16
24

PCIE_MRX_C_LTX_N0

12

PCIE_MRX_C_LTX_P0

12

@

R331

@

0_0402_5%

1 2

@

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

chip as possible.

PCIE_REFCLK_N
PCIE_REFCLK_P
CLKREQ

LOW PWR
VMAIN_PRSNT
VAUX_PRSNT

ENERGY_DET
GPHY_PLLVDD
PCIE_RXD_N
PCIE_RXD_P
PCIE_TXD_N
PCIE_TXD_P

PERST
WAKE

SMB_CLK
SMB_DATA

GPIO_0(SERIAL_DO)
GPIO_1(SERIAL_DI)
GPIO_2
UART_MODE

XTALI
XTALO

REG_GND
PCIE_GND

SCLK

1 2

5751_SO

1 2

3

+3VS +1.2VLAN

2

2

2

0.1U_0402_16V4Z

RDAC

VDDIO
VDDIO
VDDIO
VDDIO
VDDIO

VDDP
VDDP

VDDC
VDDC
VDDC
VDDC
VDDC
VDDC

AVDD
AVDD
AVDD

AVDDL
AVDDL
AVDDL
AVDDL

C323

1

SI

CS

1

0.1U_0402_16V4Z

LAN_TX0-

41

LAN_TX0+

40

LAN_RX1-

42

LAN_RX1+

43

LAN_TX2-

48

LAN_TX2+

47

LAN_TX3-

49

LAN_TX3+

50

2
1
67
66

65
63
64
62

14

CTL25

R316

18

R317

37

1.24K_0402_1%

23

XTALVDD

6
15
19
56
61

17

+2.5VLAN

68
5

+1.2VLAN

13
20
34
55
60

+LAN_BIASVDD

36
30

PCIE_PLLVDD

27

PCIE_VDD

33
38

45
52

39
44
46
51

R323

@

1K_0402_5%

SPROM_WP
SPROM_CLK
SPROM_CS

Compal Secret Data

LAN_TX0- 23
LAN_TX0+ 23
LAN_RX1- 23
LAN_RX1+ 23
LAN_TX2- 23
LAN_TX2+ 23
LAN_TX3- 23
LAN_TX3+ 23

SCLK
5751_SI
5751_SO
CS#

0_0402_5%

1 2

12

+3VLAN

+LAN_AVDD

AVDDL

1K_0402_5%

12

R322

@

Deciphered Date

12

REGCTL_PNPREGCTL

+3VLAN

12

R321
1K_0402_5%

@

1 2

C360

0.1U_0402_16V4Z

U20

8

VCC

7

WP

6

SCL

5

SDA

AT24C256_SO8@

C329

C327

1

4.7U_0805_10V4Z

TRD0_N
TRD0_P
TRD1_N
TRD1_P
TRD2_N
TRD2_P
TRD3_N
TRD3_P

LINKLED

SPD100LED
SPD1000LED
TRAFFICLED

SCLK(EECLK)

SO(EEDATA)

REGCTL12
REGCTL25

XTALVDD

BIASVDD

PCIE_PLLVDD

PCIE_VDD
PCIE_VDD

GND

69

R330 0_0402_5%@
R328 0_0402_5%@

2005/12/1 2006/12/01

Layout Notice : 1.2V filter. Place as close
chip as possible.

2

C14

C330

1

0.1U_0402_16V4Z

4.7U_0805_6.3V6K

REGCTL_PNP

@

1

A0

2

A1

3

NC

4

GND

2

2

1

C338

Q30

1

2

C12

1

0.1U_0402_16V4Z

+3VLAN

2 3

0.1U_0402_16V4Z

CTL25

2

2

C7

1

1

0.1U_0402_16V4Z

0.1U_0402_16V4Z

C357 0.1U_0402_16V4Z

1 2

C358 4.7U_0805_10V4Z

1 2

MMJT9435T1G_SOT223

4

C361

+3VLAN

+2.5VLAN

2

2

C324

C325

0.1U_0402_16V4Z

C346

1

1

0.1U_0402_16V4Z

Place closed to L14 & K14

+1.2VLAN

1

1

C359
10U_0805_10V4Z

2

2

1 2

C353

0.1U_0402_16V4Z

1 2

C352

4.7U_0805_10V4Z

41

Q29

MBT35200MT1G_TSOP6

3

256

+REGOUT25

2

C337

1

0.1U_0402_16V4Z

0.1U_0402_16V4Z

Notice : 4.7u 6.3V capactor Thickness 1.25mm

Layout Notice : Filter place as close
chip as possible.

Title

Size Document Number Rev

Custom

Date: Sheet

BCM5787MKML
LA-3271P

1

2

2

C336

1

1

0.1U_0402_16V4Z

0.4

of

22 42Monday, August 21, 2006

A

V_DAC

+2.5VLAN

R319 FBM-L11-160808-601LMT_0603

12

1. ES2 by rework form 0805 to 0603

2. Part name will modify in next phase

SHLD4
SHLD3

SHLD2
SHLD1

T31

1

TCT1

2

TD1+

3

TD1-

4

TCT2

5

TD2+
TD2-6MX2-

7

TCT3

8

TD3+

9

TD3-

10

TCT4

11

TD4+

12

TD4-

BOTH_GST5009-LF

16
15

14
13

24

MCT1
MX1+

MX1-

MCT2
MX2+

MCT3
MX3+

MX3-

MCT4
MX4+

MX4-

RJ45_TX3-

23

RJ45_TX3+

22
21

RJ45_TX2-

20

RJ45_TX2+

19
18

RJ45_RX1-

17

RJ45_RX1+

16
15

RJ45_TX0-

14

RJ45_TX0+

13

Layout Note
24HST1041A-3 pls close to conn.

ICH_SMBDATA13,17

ICH_SMBCLK13,17

Wireless_BTN

+3VS

12

R294

@

100K_0402_5%

0.1U_0402_16V4Z

C348

1 2

LAN_TX3-22

1 1

2 2

3 3

C349 0.1U_0402_16V4Z

C350 0.1U_0402_16V4Z

C351 0.1U_0402_16V4Z

LAN_TX3+22

1 2

LAN_TX2-22
LAN_TX2+22

1 2

LAN_RX1-22
LAN_RX1+22

1 2

LAN_TX0-22
LAN_TX0+22

RJ45_TX3­RJ45_TX3+
RJ45_RX1­RJ45_TX2­RJ45_TX2+
RJ45_RX1+
RJ45_TX0­RJ45_TX0+

All 49.9 ohm + 0.1 uF

V_DAC
LAN_TX3­LAN_TX3+

V_DAC
LAN_TX2­LAN_TX2+

V_DAC
LAN_RX1­LAN_RX1+

V_DAC

JLAN1

12

Amber LED+

11

Amber LED-

8

PR4-

7

PR4+

6

PR2-

5

PR3-

4

PR3+

3

PR2+

2

PR1-

1

PR1+

10

Green LED-

9

Green LED+

TYCO_1566735-1

1 2

R559 0_0402_5%

1 2

R557 0_0402_5%

1 2

R556 0_0402_5%

1 2

R558 0_0402_5%

LAN_TX0­LAN_TX0+

termination components close
to BCM5751M

R293

R170 10K_0402_5%

+3VS

R515 10K_0402_5%@

+3VS

R516 10K_0402_5%@

CLR_CMOS16
SW_CONFIG126
SW_CONFIG226

PASSWORD#17

4 4

FINGERPRINT#26

SW_RSV126
SW_RSV217
SW_RSV317

1 2
1 2

SW_RSV2
SW_RSV3

PASSWORD#
FINGERPRINT#
SW_RSV1
SW_RSV2
SW_RSV3

A

SW2

1
2
3
4
5
6
7
8 9

HPS608-E_16P

PASSWORD#

1 2

+3VS

1.5M_0402_5%

1 2

ONOFF

ON

16
15
14
13
12
11
10

WLAN_ACT

B

RP1

1 8
2 7
3 6
4 5

75_1206_8P4R_5%

2N7002_SOT23

+3VS

2N7002_SOT23

Killer switch

SW1

1BS003-1211L_3P

11223

+3VS

12

10K_0402_5%

13

D

2

G

S

B

+3VLAN

1 2

R469 0_0402_5%

Q38

S

G

2

G

2

Q37

S

1 2

R464

3

WLAN_OFF#

R270

WLAN_LINK
WLAN_ACT#

74HCT08PW_TSSOP14
Q23
2N7002LT1G_SOT23

C8
1000P_1206_2KV7K

12

R28

10K_0402_5%

@

@

D

13

@

13

D

0_0402_5%

WLAN_OFF# 26

12

1
2

R27

10K_0402_5%

@

+3VS

I0
I1

12

LAN_SDATA

LAN_SCLK

GOLAN_ALPS17

14

U39A

P

O

G

7

C

JDBD1

CLK_DEBUG_PORT13

PCI_RST#15,20

E51_TXD26

SERIRQ17,20,26

LPC_FRAME#16,26

LAN_SMBDATA 22

CLK_DEBUG_PORT13

LAN_SMBCLK 22

SERIRQ

PCIE_RXN217
PCIE_RXP217

+3VALW

ICH_PCIE_WAKE#17

LPC_AD0
LPC_AD2

LPC_AD3
LPC_AD1

E51_TXD26

1

CLK_PCI_SIO

2

LPC_AD0

3

LPC_AD2

4

PCIRST

5

ES1_TXD/LPC_DRQ1

6

+3VALW

7

E51_RXD/SERIRQ

8

LPC_AD3

9

LPC_AD1

10

LPC_FRAME

ACES_85201-0805N

@

WLAN_ACT MINI_PIN3

CLKREQD#13

CLK_PCIE_MCARD#13

CLK_PCIE_MCARD13

PLT_RST#

PCIE_RXN2
PCIE_RXP2

PCIE_TXN217
PCIE_TXP217

+3VALW

NUMLED#26,29

CAPSLED#26,29

R172 0_0402_5%

R189 0_0402_5% @

1 2

R206 0_0402_5%

R458 0_0402_5%

1 2
1 2

R461 0_0402_5%

PCIE_TXN2
PCIE_TXP2

R227 0_0402_5%
R235 0_0402_5%
R240 0_0402_5%
R243 0_0402_5%

1 2

1 2

1 2
1 2
1 2
1 2

For DEBUG

PCIE_C_RXN2
PCIE_C_RXP2

GOLAN_ALPS#

0

GOLAN

1

+3VS

U37

5

1
2

4
5

C

TC7SH08FU_SSOP5

P

B

Y

A

G

3

+3VS

14

U39B

P

I0

O

I1

G

74HCT08PW_TSSOP14

7

D26 CH751H-40_SC76

DIP_WLAN_LED

4

2 1

2 1

DIP_WLAN_LED

6

D27 CH751H-40_SC76

2005/12/1 2006/12/01

WLAN_LINK#

3

GOLAN_ALPS#17

WLAN_LED

1 2

R510 0_0402_5%

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

ALPS

# WLAN detect by BIOS and program GOLAN_ALPS# to control WLAN LED

+3VS

12

R511

10K_0402_5%

DIP_WLAN_LED
WLAN_OFF#

GOLAN_ALPS#17

WLAN_LINK#26

1 2

R509 0_0402_5%

1 2

R506 0_0402_5%

WLAN_LINK#

Compal Secret Data

Deciphered Date

D

Mini-Express Card

+3VALW

JMINI1

1

1

3

3

5

5

7

7

9

9

11

11

13

13

15

15

17

17

19

19

21

21

23

23

25

25

27

27

29

29

31

31

33

33

35

35

37

37

39

39

41

41

43

43

45

45

47

47

49

49

51

51

53

GND1

GND2

FOX_AS0B226-S52N-7F~N

@

10

+3VS

14

U39D

12

P

I0

O

13

I1

G

74HCT08PW_TSSOP14

7

D

+3VS

2
4
6

8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

+3VS

9

I0
I1

DIP_WLAN_LINK#

11

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

54

14

U39C

P

8

O

G

74HCT08PW_TSSOP14

7

+1.5VS

E

1

C462

10U_1206_16V4Z

2

1

C281

10U_1206_16V4Z

2

+3VALW

1

C443
10U_1206_16V4Z

2

LPC_AD[0..3] 16,26

WLAN_OFF#
WLAN_LINK

+1.5VS

+3VS

C422

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1 2

R440 0_0402_5%

1 2

R443 0_0402_5%

1 2

R445 0_0402_5%

1 2

R451 0_0402_5%

1 2

R453 0_0402_5%

ICH_SMBCLK 13,17
ICH_SMBDATA 13,17

USB20_N0
USB20_P0

WLAN_LINK

MINI_PIN46

R233 0_0402_5%

2

C265

0.1U_0402_16V4Z

1

2

C233

0.1U_0402_16V4Z

1

0.1U_0402_16V4Z

LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0

WLAN_OFF# 26
PLT_RST# 9,15,17,22,26

USB20_N0 17
USB20_P0 17

WLAN_LINK 26

1 2

WLAN_ACT

+3VS

R207 10K_0402_5%@
R228 10K_0402_5%

2

C235

1

2

1

2

C255

1

LPC_FRAME# 16,26

1 2
1 2

D1 Pin3 Open PAST & MASK layer

WLAN LED

D17
12-21-BHC-ZL1M2RY-2C GREEN

12

1 2

13

D

Q26

2

G

2N7002LT1G_SOT23

S

@

10K_0402_5%

1 2

Title

Size Document Number Rev

Custom

Date: Sheet

D16 HT-110UY_AMBER

13

D

Q27

2

2N7002LT1G_SOT23

G

S

R528

GOLD LAN & LAN CONN

LA-3271P

200_0603_5%

12

1 2

390_0603_5%

E

R292

R291

23 42Monday, August 21, 2006

+5VS

of

0.4

A

B

C

D

E

F

G

H

MDC CONN.

MDC_ACZ_SDOUT

W=20 mil

1

C240

2

10P_0402_50V8J

MDC_ACZ_BITCLK

+3V

1

C237

2

4.7U_0805_10V4Z

0.1U_0402_16V4Z

C239

@

1 2

MDC_ACZ_BITCLK_TERM

1

2

R200

@

10_0402_5%

1 2

MDC_ACZ_SDOUT_MDCTERM

1

2

R465

@

C453

@

10_0402_5%

10P_0402_50V8J

Adjustable Output

U27

4

VIN

2

SENSE or ADJ

DELAY
ERROR7CNOISE

C165

C160

1 1

4.7U_0805_10V4Z

+5VS

1 2

R115 10K_0402_5%

8

0.1U_0402_16V4Z

SD

SI9182DH-AD-T1-E3_MSOP8~N

VOUT

GND

5
6
1
3

C164 0.01U_0402_16V7K

1 2

12

R120

30.1K_0402_1%

R119
10K_0603_1%

+VDDA+5VS

1

2

ACZ_SDIN116

C398 4.7U_0805_10V4Z

C401 0.1U_0402_16V4Z

1 2

33_0402_5%

MDC_ACZ_SDOUT

MDC_ACZ_SYNC

MDC_ACZ_RST#

R466

MDC_ACZ_SDOUT16

MDC_ACZ_SYNC16

MDC_ACZ_RST#16

1 2

C449 10P_0402_50V8J@

1 2

C450 10P_0402_50V8J@

1 2

C451 10P_0402_50V8J@

AC97_SDIN1_MDC

2006-01-27 change connector

JMDC1

1

GND1

3

IAC_SDATA_OUT

5

GND2

7

IAC_SYNC

9

IAC_SDATA_IN

11

IAC_RESET#

GND13GND14GND15GND16GND17GND

RES0
RES1

GND3
GND4

IAC_BITCLK

18

2
4
6

3.3V

8
10
12

ACES_88018-124G

Connector for MDC Rev1.5

check Azalia MDC Module

MDC_ACZ_BITCLK16

R194

MDC_POWER

MDC_ACZ_BITCLK

0_0603_5%

1 2

HD Audio Codec

20mil

+AVDD_AC97

L20

+VDDA

2 2

3 3

ACZ_RST#16

ACZ_SYNC16

ACZ_SDOUT16

1 2

FBM-L11-160808-800LMT_0603

10U_1206_16V4Z

MIC125
MIC225

MIC_JD25

2

2

C405

C402

1

1

@

@

@

10P_0402_25V8K

10P_0402_25V8K

10P_0402_25V8K

C408

HP_JD

2

1

0.1U_0402_16V4Z

1

C202

C404

2

1 2

C170 1U_0603_10V6K

1 2

C176 1U_0603_10V6K

R121 39.2K _0402_1%

1 2

R118

EAPD25

R378

0_0402_5%@

1 2

1

2

0.1U_0402_16V4Z

C_MIC1
C_MIC2

12

20K_0402_1%

R377

1

2

40mil

C403

12

0_0402_5%@

38

U5

AVDD125AVDD2

14

LINE2_L

15

LINE2_R

16

MIC2_L

17

MIC2_R

23

LINE1_L

24

LINE1_R

18

CD_L

20

CD_R

19

CD_GND

21

MIC1_L

22

MIC1_R

13

SENSE A

12

BEEP

11

RESET#

10

SYNC

5

SDATA_OUT

45

NC

46

NC

47

SPDIFI/EAPD

48

SPDIFO

4

DVSS1

7

DVSS2

ALC262-GR_LQFP48~N

LINE_OUT_L
LINE_OUT_R

LINE1_VREFO

MIC2_VREFO

MIC1_VREFO_L

MIC1_VREFO_R

LINE2_VREFO

DGND AGND

DVDD11DVDD2

MONO_O

HP_OUT_L

HP_OUT_R

BIT_CLK

SDATA_IN

GPIO2

GPIO3

VREF

DCVOL

SENSE B

GPIO0
GPIO1

JDREF
AVSS1
AVSS2

0.1U_0402_16V4Z

9

35
36
37
39
41

6
8
2

3
29
30
28
27
32

31
33
34
43
44

40
26
42

1

1

C201

C406

2

2

0.1U_0402_16V4Z

C409 1000P_0402_50V7K~N

C407 1000P_0402_50V7K~N

LINEL
LINER

C411 1000P_0402_50V7K~N

C204 1000P_0402_50V7K~N

HP_LOUT
HP_ROUT

@

ACZ_BITCLK_CODEC

R366 0_0402_5%

AC97_SDIN0_CODEC

R361

R367 0_0402_5%@

10mil

10mil

+MIC1_VREFO_L

+MIC1_VREFO_R

R124 10K_0402_5%

1 2
1 2

12

AC97_VREF

+VDDA

12

12

R373
20K_0402_1%

For EMI

0_0603_5%

1 2

R125

1

C203
10U_1206_16V4Z

2

10_0402_5% @

0_0402_5%

CODEC_GPIO2

1 2

26

26

R365

R364
0_0402_5%

@

+3VS

1 2

R362 6.8K_0603_5%

1 2

R363 6.8K_0603_5%

1 2

R129 0_0603_5%

10P_0402_25V8K

1 2

R372 0_0603_5%

1 2

12

C410

ACZ_BITCLK 16

ACZ_SDIN0 16

10mil

1

C178
10U_0805_10V4Z

2

AMP_LEFT 25
AMP_RIGHT 25

HP_LEFT 25
HP_RIGHT 25

@

ACZ_RST#

1 2

10U_0805_10V4Z

R148 0_0402_5%

CODEC_GPIO2

Reserved for EMI

D11

RB751V_SOD323

R149

1M_0402_5%

C214

R117

100K_0402_5%

PLUG_IN25

2N7002LT1G_SOT23

21

12

R147 0_0402_5% @

1

2

12

+3VS +3VS

5

1

P

OE#

I2O

G

U6

3

74LVC1G125GW_SOT3535

Reserved for TEST

C157.2C160.2

12

4 4

R580 0_0402_5%

GND AGND

+3VS

R116

100K_0402_5%

1 2

1 2

2N7002LT1G_SOT23

13

D

2

G

Q18

S

2

G

Q17

13

D

S

2

C549

0.01U_0402_16V7K

1

EAPD Control for Vista

5

U7

2

4

GND AGND

P

B

1

A

G

NC7SZ08P5X_NL_SC70-5

3

R153 0_0402_5%

1 2

R354 0_0805_5%

1 2

R174 0_0805_5%

1 2

R160 0_0805_5%

1 2

R173 0_0805_5%

4

Y

12

@

HP_JD

1

C217

0.1U_0402_16V4Z

2

EAPD 25

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

C

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

D

2005/12/1 2006/12/01

E

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

F

Date: Sheet

Compal Electronics, Inc.

Codec ALC262

LA-3271P

G

0.4

of

24 42Monday, August 21, 2006

H

A

W=40Mil

1

1

C393

0.1U_0402_16V4Z

4 4

AMP_RIGHT24

AMP_LEFT24

3 3

EC_MUTE26

C153

0.47U_0603_16V4Z

C395

0.47U_0603_16V4Z

C154

0.47U_0603_16V4Z

C396

0.47U_0603_16V4Z

+3VS

12

R98
100K_0402_5%

13

D

Q16

2

2N7002LT1G_SOT23

G

S

2

C548

0.01U_0402_16V7K

1

EAPD24

1 2

1 2

1 2

1 2

AMP_R

AMP_L

EAPD

2

12

R357
10K_0402_5%

C157
10U_0805_10V4Z

2

7

RIN+

17

RIN-

9

LIN+

5

LIN-

19

SHUTDOWN

D21 CH751H-40_SC76

2 1

+5VS

15

16

VDD

PVDD1

GND41GND311GND213GND1

P3017THF B0 TSSOP 20P

20

Buzzer need to support ICH/PCM_SPK/Battery_low and WL_on/off

2 2

BUZR_OFF26

1 1

ICH Beep CardBus Beep

1 2

R503
0_0402_5%

A

13

D

2

G

S

2N7002LT1G_SOT23

Q49

EC Beep

BEEP 26SB_SPKR17

56_0603_1%

RB751V_SOD323

1 2

R502
0_0402_5%

6

PVDD2

BYPASS

R99

R560

ROUT+

ROUT-

LOUT+

B

U4

2

GAIN0

3

GAIN1

18

14

4

8

LOUT-

12

NC

10

1 2

2.7K_0402_5%

+3VS

12

S

G

Q45

2

SI2301BDS-T1-E3 1P SOT23

D

1 3

D35

2 1

13

D

Q47

2

G

S

2N7002LT1G_SOT23

B

+5VS

R110 10K_0402_5%
R108 10K_0402_5%@

2

C158

0.47U_0603_16V4Z

1

PLUG_IN

56_0603_1%

2

12

C481

R555

0.1U_0402_16V4Z

1

BUZZER

SI2301BDS-T1-E3 1P SOT23

1 2
1 2

SPK_R1

SPK_R2

SPK_L1

SPK_L2

BUR1

+

1
2

-

LET9040-03A_2P

Q43

R109 10K_0402_5%

1 2

R111 10K_0402_5%@

1 2

1 2

R107 0_0603_5%

1 2

R106 0_0603_5%

1 2

R104 0_0603_5%

1 2

R105 0_0603_5%

INTSPK_R1

INTSPK_R2

INTSPK_L1

INTSPK_L2

GAIN0 GAIN1 GAIN

00

0

1

0

1

*

1

S

G

12

2

R505

0_0402_5%

D

1 3

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

PCM_SPK# 20

C

6dB

10dB

15.6dB

21.6dB1

D

Speaker Connector

MICROPHONE IN JACK

MIC224
MIC124

1 2

L5 CHB2012U170_0805

1 2

L4 CHB2012U170_0805

HEADPHONE OUT JACK

HP_OUTR
HP_OUTL

PLUG_IN

2N7002LT1G_SOT23

HP_RIGHT24
HP_LEFT24

2005/12/1 2006/12/01

R154 47_0402_5%

1 2

R155 47_0402_5%

1 2

+3VS

R192

100K_0402_5%

1 2

13

D

Q33

2

G

S

1 2

C228 2.2U_0603_6.3V4Z

1 2

C227 2.2U_0603_6.3V4Z

Compal Secret Data

Deciphered Date

EAPD

PLUG_IN24

HP_R
HP_L

12

12

R152

1K_0402_5%@

+3VS

5

U10

2

P

B

Y

1

A

G

NC7SZ08P5X_NL_SC70-5

3

HP_MUTE#

R169 6.8K_0603_5%

HP_INR HPINR

1 2

HP_INL HPINL

1 2

R162 6.8K_0603_5%

D

INTSPK_R1
INTSPK_R2
INTSPK_L1
INTSPK_L2

R1233K_0402_5%
R1223K_0402_5%

12
12

220P_0402_50V7K

1 2

L6 CHB2012U170_0805

1 2

L7 CHB2012U170_0805

R151
1K_0402_5%@

4

1

2

C162

PLUG_IN

HP_MUTE#

C229
1U_0603_10V4Z

1
2
3
4
5
6

MIC_JD24

MIC-2
MIC-1

470P_0402_50V7K

14
18

15
13

E

JSPK1

1
2
3
4
G1
G2

MOLEX_53398-0471~N

FOX_JA6333L-B3S0-7F~N

+MIC1_VREFO_R
+MIC1_VREFO_L

1

1

C163

2

2

220P_0402_50V7K

HPR
HPL

C207

+3VS

R177

0_0603_5%

U8

SHDNR#
SHDNL#

INR
INL

1

C1P

3

C1N

5

1

2

Title

Size Document Number Rev

Date: Sheet

5
4
3

6 7
2
1

JMIC1

FOX_JA6333L-B3S0-7F~N

5
4
3

6 7
2
1

2

2

C206
470P_0402_50V7K

1

1

Reserve the 0 ohm resistor.

12

for voltage filtering

1 2

C231 1U_0603_10V4Z

10

19

SVDD

PVDD

PGND

PVss

SVss

SGND

2

7

17

C222
1U_0603_10V4Z

JHP1

HP_OUTR

11

OUTR
OUTL

NC-4
NC-6

NC-8
NC-12
NC-16
NC-20

MAX4411ETP+T_TQFN20~N

HP_OUTL

9

4
6
8
12
16
20

Compal Electronics, Inc.

AMP/Audio Jack

LA-3271P

E

10
9
8

25 42Monday, August 21, 2006

10
9
8

0.4

of

5

+LDO3

+3VALW

R463
10K_0402_5%

R566

10K_0402_5%

@

1 2

1 2

EC_PME#

D24CH751H-40_SC76

WLANPME#20 KB_RST#16

D D

PCIE_PME#22

1 8

TP_DATA

2 7

TP_CLK

3 6
4 5

10K_0804_8P4R_5%

Ra

Rb

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20

RP29

1 8
2 7
3 6
4 5

10K_0804_8P4R_5%

+3VALW

12

100K_0402_5%

R444

12

R447

33K_0402_5%

E-Mail_BTN
Internet_BTN

EC_MUTE

1
2
3
4
5
6

LPC_AD0

7

LPC_AD1

8

LPC_AD2

9

LPC_AD3

10

LPC_FRAME#

11

LPC_DRQ#0

12
13
14

CLK_PCI_SIO_DBR

15
16
17
18
19
20

C C

LID_SW#
FRD#
FSEL#

M/B rev:0.1; 0.2; 0.3; 1.0
Voltage:0.0; 0.4; 0.8; 1.0

B B

JLPC1

A A

ACES_85201-2005

CONN@

21
21

D25CH751H-40_SC76

+LDO3

+3VALW

+LDO3

@

12

R576

+5VS

+3VALW

12

R577

0_0402_5%

EC_SMB_DA1
EC_SMB_CK1
EC_SMB_DA2

0_0402_5%

EC_SMB_CK2

0.1U_0402_16V4Z

RP30

FOR Board ID

2006-01-27 change Brd ID

AD_BID0

1

C437

0.1U_0402_16V4Z

2

+3VALW

R45710K_0402_5%

1 2

R475

1 2

10K_0402_5%

1 2

R58110K_0402_5%

FOR LPC SIO DEBUG PORT

+5VS

SERIRQ

+3VS

LPC_DRQ#0 16
PLT_RST# 9,15,17,22,23

5

+LDO3

EC_PME# 15

R564 47K_0402_5%@

1 2

R438

1 2

47K_0402_5%

C424

08/17: modify

R462 4.7K_0402_5%
R459 4.7K_0402_5%
R470 4.7K_0402_5%
R467 4.7K_0402_5%

2

C456
1000P_0402_50V7K~N

@

1

R578 10K_0402_5%@

E-Mail_BTN
Internet_BTN

R579 10K_0402_5%@

1 2

R479

22_0402_5%@

+3VALW

EC_RST#

2

1

1 2
1 2

10K_0402_5%@

R491

1 2

0_0805_5%

@

R561

1 2

0_0805_5%

LPC_AD[0..3]16,23

LPC_FRAME#16,23

12
12
12
12

PWR_GREEN_LED#14,29

BATT_FULL_LED#14,29

PWR_AMBER_LED#14,29

R477

12

KSO[0..15]27

BKOFF#14
SLP_S3#17

SLP_S5#17

EC_SMI#17
EC_SWI#17

1

2

0.1U_0402_16V4Z

GATEA2016

SERIRQ17,20,23

CLK_PCI_EC13

PLT_RST#9,15,17,22,23

EC_SCI#17

PCI_CLKRUN#17,20

KSI[0..7]27

+5VALW

SW_CONFIG123
SW_CONFIG223

EC_SMB_DA24,10
EC_SMB_CK24,10
EC_SMB_DA127,38
EC_SMB_CK127,38

LAN_LOW_PWR22

NUMLED#23,29

CAPSLED#23,29

SCRLED#29

SYSON30,35

EC_RSMRST#17

EC_LID_OUT#17

LID_SW#27
SUSP#27,30,35,36

PBTN_OUT#17

+LDO3

CLK_PCI_SIO_DB 13

0.1U_0402_16V4Z

C461

SERIRQ

KSI[0..7]

KSO[0..15]

BATT_FULL_LED#

EC_SMI#
LID_SW#

EC_PME#

4

1

C448

2

EC_GA20
KB_RST#

CLK_PCI_EC

SW_CONFIG1
SW_CONFIG2

EC_SMB_DA2
EC_SMB_CK2
EC_SMB_DA1
EC_SMB_CK1

E51_TXD

CRY1
CRY2

4

LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0

PLT_RST#

EC_SCI#

0.1U_0402_16V4Z

1

C426

2

1000P_0402_50V7K~N

1

GA20/ GPIO00/GA20

2

KBRST#/GPIO01/KBRST#

3

SERIRQ

5

LPC_FRAME# / LFRAME#

6

LPC AD3/LAD3

9

LPC AD2/LAD2

10

LPC AD1/LAD1

12

LPC AD0/LAD0

14

CLK_PCI_EC/PCICLK

15

PCIRST#

42

EC RST#/ ECRST#

24

EC SCI#/SCI#/GPIO0E

44

PM_CLKRUN#/ CLKRUN#

KSI0

63

KSI0/GPIO30

KSI1

64

KSI1/GPIO31

KSI2

65

KSI2/GPI032

KSI3

66

KSI3/GPIO33

KSI4

67

KSI4/GPIO34

KSI5

68

KSI5/GPI035

KSI6

69

KSI6/GPIO36

KSI7

70

KSI7/GPIO37

KSO0

47

KSO0/GPIO20

KSO1

48

KSO1/GPIO21

KSO2

49

KSO2/GPIO22

KSO3

50

KSO3/GPIO23

KSO4

51

KSO4/GPIO24

KSO5

52

KSO5/GPIO25

KSO6

53

KSO6/GPIO26

KSO7

54

KSO7/GPIO27

KSO8

55

KSO8/GPIO28

KSO9

56

KSO9/GPIO29

KSO10

57

KSO10/GPIO2A

KSO11

58

KSO11/GPIO2B

KSO12

59

KSO12/GPIO2C

KSO13

60

KSO13/GPIO2D

KSO14

61

KSO14/GPIO2E

KSO15

62

KSO15/GPIO2F

89

EC URXD/KSO16/GPIO48

90

EC UTXD/KSO17/GPIO49

88

EC SMD2/ GPIO47/SDA2

87

EC SMC2/GPIO46/SCL2

86

EC SMD1/GPIO44/SDA1

85

EC SMC1/GPIO44/SCL1

34

PCM_SPK#/EMAIL_LED#/ GPIO16

35

SB_SPKR/PWR_SUSP_LED#/ GPIO17

38

PWRLED#/ GPIO19

40

NUMLED#/ GPIO1A

99

BATT CHGI LED#/ E51CS#

101

BATT LOW LED#/ E51MR0

100

CAPS LED#/ E51TMR1

102

ARROW LED#/ E51 INT0

104

SYSON/GPIO56/ E51 INT1

4

EC_RSMRST#/ GPIO02

7

BKOFF#/GPIO03

8

PM SLP S3#/GPIO04

16

EC LID OUT#/GPIO06

17

PM SLP S05#/ GPIO07

18

EC SMI#/GPIO08

19

EC SWI#/GPIO09

20

LID SW#/ GPIO0A

21

SUSP#/GPIO0B

22

PBTN_OUT#/GPIO0C

23

EC PME#/GPIO0D

140

XCLKO

138

XCLKI

E51_TXD23

3

+EC_AVCC

11

127

141

26

105

VCC

VCC

VCC/ EC VCC

VCC / EC VCC

VCC / EC VCC37VCC / EC VCC

PWR

FAN/PWM

INVT_PWM/GPIO0F/PWM1

FAN SPEED1/GPIO14/FANFB1
FAN SPEED2/GPIO15/FANFB2

PS2 interface

Address

SM BUS

GND13GND28GND

GND

GND

GND

39

103

129

139

JECDB1

1

1

2

2

3

3

4

4

ACES_85205-0400

CONN@

75

BATTEMP/AD0/GPIO38

BATT OVP/AD1/GPIO39

AD BID0/AD3/GPIO3B

EC_AVCC / AVCC

DAC_BRIG/DA0/GPIO3D

EN DFAN1/DA1/GPIO3D

EN DFAN2/DA3/ GPIO3F

DA output or GPO

BEEP#/GPIO10/PWM2

OUT BEEP/GPIO12/PWM3

ACOFF/GPIO18/PWM4

Data
BUS

BUS

ECTHERM#/GPIO11

AGND

77

C468

1000P_0402_50V7K~N

1

C469

2

Host

INTERFACE

key Matrix

scan

+3VALW

E51_TXD

1

2

U32

+3VALW +EC_AVCC

+LDO3

71
72

IREF2/DA2

PSCLK1
PSDAT1
PSCLK2
PSDAT2
PSCLK3
PSDAT3

ADB0/D0
ADB1/D1
ADB2/D2

ADB3/ D3

ADB4/D4
ADB5/D5
ADB6/D6
ADB7/D7

KBA0/A0
KBA1/A1
KBA2/A2
KBA3/A3
KBA4/A4
KBA5/A5
KBA6/A6
KBA7/A7
KBA8/A8

KBA9/A9
KBA10/A10
KBA11/A11
KBA12/A12
KBA13/A13
KBA14/A14
KBA15/A15
KBA16/A16
KBA17/A17
KBA18/A18
KBA19/A19

FRD#/RD#

FWR#/WR#

73
74

76
78
79
80

25
27
30
31
32
33

91
92
93
94
95
96

125
126
128
130
131
132
133
134
111
112
113
114
115
116
117
118
119
120
121
122
123
124
110
109
108
107
106
98

84
97
135
136
144

41
43
29
36
45
46

81
82
83
137
142
143

KB910L_LQFP144

10P_0402_50V8J

ADP_I/AD2/GPIO3A

AD INtput or GPI

SELIO2#/ GPIO43

SELIO#/ GPIO50

FSEL#/SELMEM#

EC ON/ GPIO1B

AC IN/ GPIO1C

ONOFF/GPIO18

PCMRST#/GPIO1E

WL OFF#/GPIO1F

ALI/MH#/GPIO40

FSTCHG/GPIO41

VR ON/ GPIO42
GPIO57/GPIO57
GPIO58/GPIO58
GPIO59/GPIO59

ECAGND

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

L22 MBK1608800YZF 0603

1 2

R562 0_0603_5%@

1 2

R209 0_0402_5%

FAN_SPEED1
FINGERPRINT# FINGERPRINT#

EC_MUTE

BUZR_OFF

TP_CLK

TP_DATA

EC_THERM#

12

0.1U_0402_16V4Z

1 2

L23 MBK1608800YZF 0603

C428

1 2

0.01U_0402_16V7K

BATT_TEMP 38

BATT_OVP 33

AD_BID0

E-Mail_BTN
Internet_BTN

ADP_I 33

DAC_BRIG 14
EN_DFAN1 4
IREF 33

INVT_PWM 14
BEEP 25

SW_RSV1 23

ACOFF 32,33

FAN_SPEED1 4

FINGERPRINT# 23

AMH/LI# 38

EC_MUTE 25

BUZR_OFF 25
TP_CLK 27
TP_DATA 27

ADB0
ADB1
ADB2
ADB3
ADB4
ADB5
ADB6
ADB7
KBA0
KBA1
KBA2
KBA3
KBA4
KBA5
KBA6
KBA7
KBA8

KBA9
KBA10
KBA11
KBA12
KBA13
KBA14
KBA15
KBA16
KBA17
KBA18
KBA19

1

C473

2

32.768K 20PPM Q13MC30610003

EN_WOL# 30

2005/12/1 2006/12/01

1

2

1

R483 20M_0603_5%@

C438

C439

1000P_0402_50V7K~N

2

ECAGND

ECAGND

ICH_POK 15,17

ADB[0..7]

KBA[0..19]

E-Mail_BTN 29

Internet_BTN 29
FRD# 27
FWR# 27
FSEL# 27

EC_ON 29,34
ACIN 17,32,34
EC_THERM# 17
ON_OFF 29
WLAN_LINK# 23
WLAN_OFF# 23

GMCH_ENBKL 11,14

FSTCHG 33

VR_ON 37

MSEN# 14

WLAN_LINK 23

VGATE 13,15,17,37

1 2

4

1

Y1

IN

OUT

NC3NC

2

1

2

Compal Secret Data

Deciphered Date

2

ADB[0..7] 27

KBA[0..19] 27

LC2A KH3

KBSEL0# SW_CONFIG1

KBSEL1# SW_CONFIG2

FINGERPRINT#

CRY1

CRY2

12

0_0603_5%

R482

C472
10P_0402_50V8J

2

SW_CONFIG1
SW_CONFIG2
SW_RSV1

12mA

KBA0
KBA1
KBA2
KBA3
KBA4
KBA5

PLT_RST#

+3VS

12

1

2

R473
10_0402_5%@

C459
15P_0402_50V8D@

SW_RSV1

RP28

1 8
2 7
3 6
4 5

10K_0804_8P4R_5%

SW_RSV2

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3 PCI_CLKRUN#

+3VS
+3V

JTPM1

2
4
6
8
10
12
14
16
18
20

NAIS_AXK5S20045J~N

0.5A per each pin

Title

Size Document Number Rev

Custom

Date: Sheet

CLK_PCI_EC

1
3
5
7

9
11
13
15
17
19

R493 10K_0402_5%@
R494 10K_0402_5% @
R486 10K_0402_5%@
R487 10K_0402_5%@
R488 10K_0402_5%@
R489 10K_0402_5%@

1 2
1 2
1 2
1 2
1 2
1 2

1 2

LPC_FRAME#
SERIRQ

1

R471

100K_0402_5%@

PLT_RST# 9,15,17,22,23

CLK_PCI_TPM 13

12

R225
10_0402_5%@

1

C273
22P_0402_25V8K

@

2

KB910L/LIT SW
LA-3271P

1

+3VALW

26 42Monday, August 21, 2006

0.4

of

KSO8

C187 100P_0402_25V8K

KSI3

C197 100P_0402_25V8K

KSO9

C186 100P_0402_25V8K

KSI2

C180 100P_0402_25V8K

KSI1

C181 100P_0402_25V8K

KSO10

C185 100P_0402_25V8K

KSO11

C184 100P_0402_25V8K

KSI0

C198 100P_0402_25V8K

KSO12

C200 100P_0402_25V8K

KSO13

C183 100P_0402_25V8K

KSO14

C199 100P_0402_25V8K

KSO15

C182 100P_0402_25V8K

KSI7

C172 100P_0402_25V8K

KSI6

C177 100P_0402_25V8K

KSI5

C196 100P_0402_25V8K

KSO0

C195 100P_0402_25V8K

KSO1

C194 100P_0402_25V8K

KSO2

C193 100P_0402_25V8K

KSI4

C179 100P_0402_25V8K

KSO3

C192 100P_0402_25V8K

KSO4

C191 100P_0402_25V8K

KSO5

C190 100P_0402_25V8K

KSO6

C189 100P_0402_25V8K

KSO7

C188 100P_0402_25V8K

Felica Conn

KSI[0..7]
KSO[0..15]

KSI[0..7] 26
KSO[0..15] 26

+5VS

F3 1.1A_6VDC_FUSE @

USB20_N117
USB20_P117

TP1

21

+5VS_FP_FE
USB20_N1
USB20_P1

LEC

JFE1

1
2
3
4

8

5

G

7

6 G

JST_06FHJ-SM1-GB-TB(LF)(SN)~N

CONN@

INT_KBD CONN.

(Right)

(Left)

KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15
KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7

JKB1

24
23
22
21
20

25

19

G

26

18

G
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

ACES_85201-2405

CONN@

C146

0.01U_0402_16V7K

1M Byte BIOS ROM

VCC0
VCC1

RP#

NC0
NC1

GND0
GND1

D0
D1
D2
D3
D4
D5
D6
D7

NC

KBA[0..19]
ADB[0..7]

31
30

25
26
27
28
32
33
34
35

10
11
12
29
38

23
39

BIOS_RST#

KBA[0..19]26

KBA0
KBA1
KBA2
KBA3
KBA4

KBA6
KBA7
KBA8
KBA9
KBA10
KBA11
KBA12
KBA13
KBA14
KBA15
KBA16
KBA17
KBA18
KBA19

FSEL#26
FRD#26
FWE# FWR# 26

CLK_PCI_FWH13

+3VALW

FSEL#
FRD#
FWE#

1 2

R261

@

0_0402_5%

1 2

R260 10K_0402_5% @

U36

21

A0

20

A1

19

A2

18

A3

17

A4

16

A5

15

A6

14

A7

8

A8

7

A9

36

A10

6

A11

5

A12

4

A13

3

A14

2

A15

1

A16

READY/BUSY#

40

A17

13

A18

37

A19

22

CE#

24

OE#

9

WE#

SST39VF080-70-4C-EIE_TSOP40~N

FWE#

+5VS

1

2

ADB0
ADB1KBA5
ADB2
ADB3
ADB4
ADB5
ADB6
ADB7

1

C493

0.1U_0402_16V4Z

2

TO M/B

TP_DATA26
TP_CLK26

+3VALW

1 2

R492 10K_0402_5%

12

R51410K_0402_5% @

@

+LDO3

@

12

R569

R570

0_0402_5%

1

C474

0.1U_0402_16V4Z

2

R571 10K_0402_5% @

12

+3VALW

TP_CLK

C144100P_0402_25V8K

12

1

@

2

0_0402_5%

+LDO3

+3VALW

@

C145100P_0402_25V8K

TP_DATA

1

2

LID_SW#26

KBA14
KBA13
KBA12
KBA11
KBA10

KBA9
KBA8
KBA7
KBA6
KBA5
KBA4
KBA3
KBA2
KBA1
KBA0

BIOS_RST#

2006-01-27 change connector

+3VALW

LID_SW#

Debug Tool

JP1

1 2
3 4
5 6
7 8
9 10
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
29 30
31 32
33 34

SUYIN_127212FA034G200ZX@

JTP1

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

GND

10

GND

ACES_85201-0805N

+5VALW

C429 0.1U_0402_16V4Z

8
7

+LDO3

0_0402_5%

R565

@
2
1

12

6
5

+3VALW

100K_0402_5%

EC_SMB_CK126,38
EC_SMB_DA126,38ADB[0..7]26

+3VALW

FSEL#
FRD#
FWE#
ADB7
ADB6
ADB5
ADB4
ADB3
ADB2
ADB1
ADB0
KBA19
KBA18
KBA17
KBA16
KBA15 FWE#

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2005/12/1 2006/12/01

Compal Secret Data

+LDO3

12

@

R567

0_0402_5%

C454

1 2

0.1U_0402_16V4Z

4

O

Deciphered Date

+3VALW

12

R568

5

U31

P

I0
I1

G

TC7SH32FU(TE85L) SSOP 5P

3

1 2

U30

VCC
WP
SCL
SDA

AT24C16AN-10SU-2-7 SO 8P

12

R454
100K_0402_5%

GND

A0
A1
A2

1
2
3
4

1 3

D

Q36
2N7002LT1G_SOT23

+5VS_FP_FE

1

C306
10U_0805_10V4Z

2

+5VALW

12

R442
100K_0402_5%

12

R435
100K_0402_5%

G

S

SUSP# 26,30,35,36

EC_FLASH# 17

MDA/BT/KBD/TP Conn
LA-3271P

of

27 42Monday, August 21, 2006

2

Title

Size Document Number Rev

Custom

Date: Sheet

0.4

A

B

C

D

E

+USB_AS

1 2

W=40mils

USB_OC#4 17

W=40mils

USB_OC#6

12

R329
470_0805_5%

13

D

2

G

Q31

S

2N7002LT1G_SOT23

USB_OC#6 17

SUSP

12

R49
470_0805_5%

13

D

2

G

Q12

S

2N7002LT1G_SOT23

SUSP

USB20_N417

USB20_P417

150U_D2_6.3VM

C315

USB20_N4

USB20_P4

1

+

2

470P_0402_50V7K

R298

1 2

0_0402_5%

3

3

2

2

WCM2012F2S-900T04_0805

R299

1 2

0_0402_5%

@

+USB_AS

C321

1

2

1

2

@

L11

4

4

1

1

470P_0402_50V7K
C320

4

5

Vp

CH4
CH11Vn2CH2

USB20_N4C
USB20_P4C

6

D18
NUP4301MR6T1_TSOP6

CH3

3

USB20_N217
USB20_P217

+5VS

1 1

2 2

SUSP30,36

SUSP30,36

1

C363

0.1U_0402_16V4Z

2

+5VS

1

C69

0.1U_0402_16V4Z

2

1 2

R333
0_0402_5%

1 2

R58
0_0402_5%

12

R334
100K_0402_5%

@

12

R57
100K_0402_5%

@

U21

1

GND

2

IN

3

IN

4

EN#

G548_MSOP8

U3

1

GND

2

IN

3

IN

4

EN#

G548_MSOP8

OUT
OUT
OUT
OC#

OUT
OUT
OUT
OC#

8
7
6
5

8
7
6
5

USB_OC#4

+USB_BS

R52
0_0402_5%

+USB_AS

+5VS

JUSB1

1

VCC

2

D-

3

D+

4

GND

5

GND1

6

GND2

7

GND3

8

GND4

SUYIN_020173MR004G533ZR

FINGERPRINT

F2 1.1A_6VDC_FUSE

+5VS_FP

21

USB20_N2
USB20_P2

JFP1

1

1

2

2

3

3

4

4

JST_BM04B-SRSS~N

2006-01-27 change connector

JUSB2

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

11

11

12

12

13

13

14

14

15

15

16

16

ACES_87213-1600

@

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

USB Port

Monday, August 21, 2006

LA-3271P

E

28 42

0.4

of

USB20_N6
USB20_P6

+USB_CS +USB_BS

USB20_N5
USB20_P5

USB20_N3
USB20_P3

D

3 3

+5VS

1

C364

0.1U_0402_16V4Z

2

SUSP30,36

4 4

1 2

R338
0_0402_5%

A

12

R337
100K_0402_5%

@

U22

1

GND

2

IN

3

IN

4

EN#

G548_MSOP8

OUT
OUT
OUT

OC#

8
7
6
5

+USB_CS

W=40mils

1 2

R523
0_0402_5%

1 2

R522
0_0402_5%

B

USB_OC#3

USB_OC#5

USB_OC#3 17

USB_OC#5 17

12

R39
470_0805_5%

13

D

2

G

Q11

S

2N7002LT1G_SOT23

USB20_N617
USB20_P617

USB20_N517
USB20_P517

USB20_N317

SUSP

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2005/12/1 2006/12/01

USB20_P317

Compal Secret Data

Deciphered Date

A

1 1

B

C

D

E

note:T1 minimum 15ms,T2 minimum 33ms/maximum 500ms,
SUSP# goes to low after SB_PWRGD goes to low for power
down.

VLDT_EN

+LDO3

+3VALW

Power Button

R572

R11

1 2

D5

100K_0402_5%

PWR_ON-OFF_BTN#

2 2

EC_ON26,34

3 3

EC_ON

+LDO3

4.7K_0402_5%

1 2

+3VALW

@

R573

DAN202U_SC70

R13

4.7K_0402_5%

1 2

1 2

R12
33K_0402_5%

DTC124EKAT146 NPN SOT23

SATA_LED#16

ODD_ACT_LED#19

2

1

3

13

2

Q3

SATA_LED#
ODD_ACT_LED#

@

100K_0402_5%

1 2

51ON#

2

C34
1000P_0402_50V7K~N

1

+5VS

1

B

2

A

ON_OFF 26
51ON# 32

12

2

C362

0.1U_0402_16V4Z

1

5

U19

P

IDE_ACT_LED#

4

Y

G

TC7SH08FU_SSOP5

3

D19
RLZ20A_LL34

SCRLED#26
NUMLED#23,26
CAPSLED#23,26

E-Mail_BTN26
Internet_BTN26

PWR_GREEN_LED#14,26

PWR_AMBER_LED#14,26

BATT_FULL_LED#14,26

NB_PWRGD

SB_PWRGD

SUSP#

+1.8VS

PWR_GREEN_LED#
PWR_AMBER_LED#
BATT_FULL_LED#

SCRLED#
NUMLED#
CAPSLED#

E-Mail_BTN
Internet_BTN

T1

T2

E-Mail_BTN

Internet_BTN

+5VS +5VALW

E-Mail_BTN
Internet_BTN
SCRLED#
NUMLED#
CAPSLED#
IDE_ACT_LED#
PWR_ON-OFF_BTN#
PWR_GREEN_LED#
PWR_AMBER_LED#
BATT_FULL_LED#

JFN1

1 2
3 4
5 6
7 8
9 10
11 12
13 14
15 16
17 18

19 20

SUYIN_80030A-020G2T

CONN@

C22 100P_0402_25V8K@
C23 100P_0402_25V8K@
C24 100P_0402_25V8K@
C25 100P_0402_25V8K@
C32 100P_0402_25V8K@
C26 100P_0402_25V8K@
C27 100P_0402_25V8K@
C28 100P_0402_25V8K@
C31 100P_0402_25V8K@
C29 100P_0402_25V8K@

SCRLED#
NUMLED#
CAPSLED#
IDE_ACT_LED#

PWR_ON-OFF_BTN#
PWR_GREEN_LED#
PWR_AMBER_LED#
BATT_FULL_LED#

+5VS

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2005/12/1 2006/12/01

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

D

Date: Sheet

PWR_OK/BTN
LA-3271P

E

0.4

of

29 42Monday, August 21, 2006

A

B

C

D

E

+5VALW TO +5V

+5V

+5VALW

U38

8

S

D

7

S

1 1

D

6

S

D

5

G

D

SI4800DY-T1-E3 1N SO8

1

C490
10U_1206_16V4Z

2

1

C492
10U_1206_16V4Z

2

1
2
3

5V_GATE SUSON

4

12

C488

0.1U_0603_25V7K~N

@

0_0603_5%

1 2

R501

1

C491
1U_0805_25V4Z

2

R504

100K_0603_5%

1 2

13

D

2

G

Q40

S

2N7002LT1G_SOT23

B+_BIAS

SYSON#

+5VALW

8
7
6
5

SI4800DY-T1-E3 1N SO8

1

C296

4.7U_0805_10V4Z

2

+3VALW TO +3V

+3V

1

2

10K_0603_1%

1 2

R286

C305

0.22U_0603_10V7K

C301
1U_0805_25V4Z

SUSON RUN_ON

R287

100K_0603_5%

1 2

B+_BIAS

+3VALW

8
7
6
5

SI4800DY-T1-E3 1N SO8

1

C421
10U_1206_16V4Z

2

1
2
3
4

3V_GATE

1

C304
10U_1206_16V4Z

2

1

2

+3VALW

U11

8

S

D

7

S

D

6

S

D

5

G

D

2 2

SI4800DY-T1-E3 1N SO8

1

C303
10U_1206_16V4Z

2

+5VALW TO +5VS

+5VS

U12

1

S

D

2

S

D

3

S

D

4

G

D

1

2

5VS_GATE

12

C299

4.7U_0805_10V4Z

0_0603_5%

1 2

R259

C294

0.1U_0603_25V7K~N

@

1

C300
1U_0805_25V4Z

2

RUN_ON

R253

100K_0603_5%

1 2

13

D

2

G

Q22

S

2N7002LT1G_SOT23

SUSP

B+_BIAS

SUSP28,36

SUSP#26,27,35,36

SUSP

R280
10K_0402_5%

1 2

2

G

+5VALW

R279
10K_0402_5%

1 2

13

D

Q25
2N7002LT1G_SOT23

S

+3VALW TO +3VS

+3VS

1

C418

1
2
3
4

2

3VS_GATE

10U_1206_16V4Z

1

2

U29

S

D

S

D

S

D

G

D

1

C414
1U_0805_25V4Z

2

10K_0603_1%

1 2

R414

C415

0.22U_0603_10V7K

R407

100K_0603_5%

1 2

B+_BIAS

SYSON#

SYSON26,35

SYSON

SYSON#

R476
10K_0402_5%

1 2

2

G

+5VALW

R478
10K_0402_5%

1 2

13

D

Q39
2N7002LT1G_SOT23

S

3 3

+1.8V

12

R61
470_0805_5%

13

D

SYSON# SYSON# SYSON#

2

G

Q14

S

2N7002LT1G_SOT23

4 4

12

R55
470_0805_5%

13

D

S

2

G

Q13

2N7002LT1G_SOT23

+1.5VS

12

R525
470_0805_5%

13

D

2

G

Q44

S

2N7002LT1G_SOT23

SUSP

+3V+0.9VS

12

13

D

S

R508
470_0805_5%

2

G

Q42

2N7002LT1G_SOT23

12

R278
470_0805_5%

13

D

2

G

Q24

S

2N7002LT1G_SOT23

+5V

12

13

D

S

R507
470_0805_5%

SYSON#

2

G

Q41

2N7002LT1G_SOT23

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

+5VS+3VS

12

R21
470_0805_5%

13

D

S

Q8

EN_WOL22

SUSPSUSP

2

G

2N7002LT1G_SOT23

2005/12/1 2006/12/01

Compal Secret Data

Deciphered Date

B+_BIAS

1 2
13

D

S

R167
470K_0402_5%

Q19

2

2N7002_SOT23

G

D

EN_WOL# 26

Title

Size Document Number Rev

Custom

Date: Sheet

DC Interface
LA-3271P

E

of

30 42Monday, August 21, 2006

0.4

5

H1
HOLEA@

1

H38

H2

HOLEA@

HOLEA@

D D

1

1

H15
HOLEA@

1

H_R453X394D118

H37
HOLEA@

H_S315D118

1

H_O156X65D126X35

CF6
SMD40M80

@

1

CF8
SMD40M80

@

1

FD3
FIDUCAL

@

1

4

CF9
SMD40M80

@

1

CF14
SMD40M80

@

1

FD2
FIDUCAL

@

1

CF11
SMD40M80

@

1

CF5
SMD40M80

@

1

FD1
FIDUCAL

@

1

CF3
SMD40M80

@

1

CF7
SMD40M80

@

1

FD4
FIDUCAL

@

1

CF4
SMD40M80

@

1

CF13
SMD40M80

@

1

FD5
FIDUCAL

@

1

CF2
SMD40M80

@

1

CF10
SMD40M80

@

1

FD6
FIDUCAL

@

1

CF1
SMD40M80

@

CF12
SMD40M80

@

3

1

1

2

1

H17

H10

HOLEA@

HOLEA@

H_O197X114D118X35

1

1

H25
HOLEA@

1

H21
HOLEA@

1

H18
HOLEA@

1

H14
HOLEA@

1

H7
HOLEA@

H_O65X276D35X236

1

H26
HOLEA@

1

H_C276D126

H_C128D98

H28
HOLEA@

1

M1
HOLEA@

H_O134X118D55X39

H11
HOLEA@

1

H13

C C

HOLEA@

H_S394D126

1

M2
HOLEA@

H_O130X157D130X157N H_O177X122D177X122NH_C130D130N

1

H8
HOLEA@

1

H4
HOLEA@

1

B B

H12
HOLEA@

1

H6
HOLEA@

1

H9
HOLEA@

H_O65X148D35X118

1

H35

H36

H29
HOLEA@

1

1

H16
HOLEA@

1

M4
HOLEA@

1

HOLEA@

HOLEA@

1

H_O118X134D39X55

H_C122D122N

H3
HOLEA@

1

H_S394D118

1

M3
HOLEA@

1

H20
HOLEA@

1

H_O187X65D157X35

H19
HOLEA@

1

H_O65X172D35X142

PCB

LA-3271P REV 0.3 M/B

H5
HOLEA@

H_O148X190D118X157

1

A A

H32

H33

HOLEA@

HOLEA@

1

H_C276D126 MDC

5

1

H22

HOLEA@

HOLEA@

1

1

H31
HOLEA@

1

H30

HOLEA@

HOLEA@

1

H_C335D165

1

H34
H_c157D118

For TPM

1

@

H24
HOLEA@

H_C236D126H_C236D157

1

4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/12/1 2006/12/01

Compal Secret Data

Deciphered Date

2

Title

Size Document Number Rev

Custom

Date: Sheet

Screws
LA-3271P

of

1

31 42Monday, August 21, 2006

0.4

H23

H27

5

4

3

2

1

ADPIN

PF1

10A_65VDC_451010

12

G920AT24U_SOT89

3

OUT

2

2

2

2

2

21

12

12

PC2

100P_0402_50V8J~N

PJP1
JUMP_43X118@

112

TP0610K-T1-E3_SOT23

12

PC9

0.22U_1206_25V7K

PU2

IN

GND

1

+5VALW

+3VALW

+1.8V

PR16

2

33_1206_5%

PQ2

13

2

12

PR23
200_0805_5%

2

12

PC14
1U_0805_25V4Z

+1.5VSP

+0.9VSP

+VCCPP

+2.5VSP

PCN1

1

D D

C C

B B

CHGRTC

A A

1

2

2

3

3

4

4

SINGA_2WA-8291T041

PD4

RB751V_SOD323

CHGRTCP

PR19

100K_0402_5%

PR21

22K_0402_5%

1 2

RTCVREF

12

BATT+

51ON#30

3.3V

PR26

1 2

560_0603_5%

PR27

1 2

560_0603_5%

12

PC15

4.7U_0805_6.3V6K~N

PJP2

+5VALWP

+3VALWP +VCCP

+1.8VP

JUMP_43X118@

112

PJP4
JUMP_43X118@

112

PJP6
JUMP_43X118@

112

PJP8
JUMP_43X118@

112

PJP10
JUMP_43X118@

112

5

PL1

FBMA-L18-453215-900LMA90T_1812

1 2

PC3

1000P_0402_50V7K~N

VIN

PD3

RLS4148_LLDS2

VIN

1 2
12

12

PC10

0.1U_0603_25V7K~N

PC4

100P_0402_50V8J~N

PD1

RLS4148_LLDS2

VS

PJP3
JUMP_43X118@

112

PJP5
JUMP_43X118@

112

PJP7
JUMP_43X118@

112

PJP9
JUMP_43X118@

112

PJP11
JUMP_43X118@

112

12

12

2

2

2

2

2

4

VIN

Max. typ. Min.

H-->L 18.234 17.841 17.449
L-->H 17.597 17.210 16.813

PC1

2200P_0402_50V7K~N

@

12

PC5

12

100K_0402_1%

PD5

2
3

RB715F_SOT323

VIN

12

12

PR9

19.6K_0402_1%~N

PR3

82.5K_0402_1%~N
PR7

22K_0402_1%

1 2

12

PC8
1000P_0402_50V7K~N

VL

12

PR22

1

12

PC12

0.1U_0603_25V7K~N

RTCVREF

1000P_0402_50V7K~N

ACOFF27,34

PR6

1K_1206_5%

1 2

PR8

1K_1206_5%

1 2

PR11

1K_1206_5%

1 2

PR14

1K_1206_5%

1 2

DTC115EUA_SC70

PQ3

2

12

PR12

470K_0402_5%

13

DTC115EUA_SC70

12

PR13

470K_0402_5%

PQ1

TP0610K-T1-E3_SOT23

2

12

13

PQ4

2

13

PR17
470K_0402_5%

ACIN

B+

PC7

0.1U_0402_16V7K~N

MAINPWON35,39

ACON34

1 2

N40N41
N35

7

O

Precharge detector
Min. typ. Max.

H-->L 14.589V 14.84V 15.243V

+1.5VS

L-->H 15.562V 15.97V 16.388V

1 2

PR2
1M_0402_1%~N

1 2

VS

8

3

+

2

-

4

PR15

10K_0402_5%

12

PR18

2.2M_0402_5%

VS

8

PU1B

P

+

-

G

LM393DR_SO8

4

PR28

34K_0402_1%

PR1

56K_0402_5%@

12

PC6

PU1A

P

1

O

G

LM393DR_SO8

12

5
6

12

12

0.01U_0402_25V7K~N

RLZ4.3B_LL34

RTCVREF

3.3V

PC13

1000P_0402_50V7K~N

12

PR30

66.5K_0402_1%

@

PD2

D

S

VIN

12

PR4
10K_0402_5%

12

12

PR24
191K_0402_1%

PRG++

RHU002N06_SOT323

PQ5

13

2

G

PR5
1K_0402_5%

1 2

PACIN

12

PR10
10K_0402_5%

PR25

499K_0402_1%

PR29
47K_0402_5%

13

B+

12

PR20
499K_0402_1%

12

12

PQ6
DTC115EUA_SC70

2

ACIN 27,35

PACIN 34

12

PC11

0.01U_0402_25V7K~N

PACIN 34

+5VALWP

BATT ONLY

+0.9VS

Precharge detector

Min. typ. Max.
H-->L 6.138V 6.214V 6.359V
L-->H 7.196V 7.349V 7.505V

+2.5VS

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/12/1 2006/12/01

Compal Secret Data

Deciphered Date

2

Title

DCIN / Precharge

Size Document Number Rev

LA-3271P 0.4

Custom

Date: Sheet

1

of

32 42Monday, August 21, 2006

Vin Detector

A

B

C

D

E

RLZ22B_LL34

1SS355_SOD323

E

27,33

ACOFF

1 2

PD18

1 2

@

12

PC32

4.7U_1206_25V6K~N

Charger

PD16

PR192

1 2

1SS355_SOD323

@

1 3

12

PC141

0.1U_0603_25V7K~N

BATT+

of

33 42Monday, August 21, 2006

220K_0402_5%~N

2

D

@

BATT+

PACIN

PQ47

G

S

@

2N7002-7-F_SOT23-3

0.4

P2

PQ8

PQ7

AO4407_SO8

8

2

13

PR48

22K_0402_5%

1 2

2

7
5

PQ10

47K

47K

PQ11
DTC115EUA_SC70

+3VALWP

12

13

1 3

PR50
47K_0402_5%

PQ17
DTC115EUA_SC70

VIN

1 1

12

PQ14

2

G

ACOFF#

PACIN33

DTA144EUA_SC70

2

13

D

S

ACON33

RHU002N06_SOT323

PD8

1 2

RLS4148_LLDS2

PR33
47K_0402_5%

2 2

3 3

FSTCHG27

1
2
36

4

PR37

PQ15 RHU002N06_SOT323

2

G

2

PC21

12

150K_0402_5%

13

D

S

12

0.1U_0603_25V7K~N

13

12

0.1U_0402_16V7K~N

CS

PQ16
DTC115EUA_SC70

CP Point=3.646A
5V*(10K/(35.7k+10k))=1.094V

AO4407_SO8

1
2
3 6

IREF27

12

4

0.1U_0603_25V7K~N

12

PR39

10K_0402_1%

1 2

143K_0402_1%~N

100K_0402_1%

PR32
200K_0402_1%

PC25

IREF=1.0288*Icharge
IREF=0.6V~3.21V

8
7

5

PC140

1 2

@

ADP_I

12

PR38

35.7K_0402_1%

12

PC27

0.1U_0402_16V7K~N

PR45

12

PR49

1500P_0402_50V7K~N

1000P_0402_50V7K~N

12

PC34

0.1U_0402_16V7K~N

P3

PR36

100K_0402_1%

PR40

PC24

1 2

1 2

10K_0402_5%

PC28

PR43

1 2

1 2

1K_0402_5%

PR46 10K_0402_5%

1.094V/(20*0.015)=3.646A

PR57

1 2

B+

100_0805_5%~N

+5VALW

PR58

470K_0402_5%

1 2

12

PR62

4 4

1 2

12

PC39

0.1U_0603_25V7K~N

220K_0402_5%

PR63

1 2

PD10

1SS355_SOD323

220K_0402_5%

2

G

A

PQ20

TP0610K-T1-E3_SOT23

13

2

13

D

PQ23
2N7002-7-F_SOT23-3

S

PC38

1 2

12

PD9

RLZ18B_LL34-2

0.1U_0805_25V7M~N

B+_BIAS

LI-4S :18V----BATT-OVP=1.498V
Ni-8S :16V----BATT-OVP=1.496V

B

Iadp=0~3.95A(75W)

PR31

0.015_2512_1%

4
3

PU3

1

12

S

1 2

2

3

4

FB8

5

6

FB7

7

8

9

10

11

12

MB3887PFV-ERE1_SSOP24

PR51

46.4K_0603_0.1%

PQ18

D

2N7002-7-F_SOT23-3

13

G

2

12

PC36

0.1U_0402_16V7K~N

1
2

-INC2

OUTC2

+INE2

-INE2

FB2

VREF

FB1

-INE1

+INE1

OUTC1

OUTD

-INC1

12

B+

PL2

FBMA-L18-453215-900LMA90T_1812

1 2

24

+INC2

23

GND

CS

22

CS

21

VCC(o)

20

OUT

VH

VCC

RT

-INE3

FB3

CTL

+INC1

1 2

13

100K_0402_5%

PC26

19

1 2

0.1U_0603_25V7K

18

17

1 2

PR44
68K_0402_5%~N

16

PR47

FB9

15

1 2

47K_0402_5%~N

14

13

PR53

1 2

200K_0603_0.1%

PR55

VL

PQ19
DTC115EUA_SC70

2

0.1U_0603_25V7K

1500P_0402_50V7K~N

CTL pin = 0 >
>Charger Shutdown.

MH/LI# 39

7

BATT_OVP27

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

Fosc=14100/Rt=14100/47=300KHz

12

12

12

PC18

PC17

PC16

4.7U_1206_25V6K~N

PC22

0.022U_0402_16V7K~N

1 2

PC23

1 2

0.1U_0603_25V7K

PC29

1 2

PC33

1 2

ACON 33

4.7U_1206_25V6K~N

0_0603_5%~N

PR41

4.7U_1206_25V6K~N

HG7DH7

12

4.2V

VS

12

PC35

8

0

4

0.01U_0402_25V7K~N

PU4B

5

P

+

6

-

G

LM358ADR_SO8

2005/12/1 2006/12/01

12

PC19

PC20

0.1U_0603_25V7K~N

PR52

12

113K_0603_0.1%

BATT+

12

PR54
340K_0402_1%

12

PR56

499K_0402_1%

PR59

12

634K_0402_1%

12

PR61

86.6K_0402_1%

Compal Secret Data

Deciphered Date

12

2200P_0402_50V7K~N

PD6

EC31QS04

13

D

S

578

36

PQ22
2N7002-7-F_SOT23-3

G

CHG_B+

241

ACOFF##

PQ12
AO4407_SO8

ACOFF#

PQ46

MMBT3904_SOT23

LXCHRG

12

1 2

2

PL3

10U_LF919AS-100M-P3_4.5A_20%

1 2

12

PD7

EC31QS04

8

PU4A

3

P

+

1

0

2

-

G

LM358ADR_SO8

4

PC37

0.01U_0402_25V7K~N

13

D

2

C

2

B

E

3 1

PR60

1 2

100K_0402_5%

2

PQ21

DTC115EUA_SC70

PQ9

1
2
3 6

PR190

1 2

13

30K_0402_5%

PQ45

DTC115EUA_SC70

PR187

1 2

220K_0402_5%~N

12

PR34
47K_0402_5%

PR42

4
3

0.02_2512_1%

AO4407_SO8

1
2

4

ACOFF#

8
7

5

12

PR188
150K_0402_5%

PR35

1 2

100K_0402_5%

13

DTC115EUA_SC70

PC30

4.7U_1206_25V6K~N

PQ13

12

VIN

PD17

PD15

2

1SS355_SOD323

PC31

4.7U_1206_25V6K~N

12

1 2

12

Charge voltage
4S CC-CV MODE : 16.8V(Li-Ion)
8S CC-CV MODE : 14.4V(Ni-MH)

VL

MH/LI# 39

Title

Size Document Number Rev

B

Date: Sheet

Compal Electronics, Inc.

PWR-Charger

5

4

3

2

1

+3.3VALWP/+5VALWP

12

PC42

4.7U_1206_25V6K~N
2200P_0402_50V7K~N

12

PL5

MAINPWON33,39

B+++

12

VS

12

D8D7D6D

S1S2S3G

D8D7D6D

S1S2S3G

PD12

RLZ5.1B_LL34

PR78

1 2

47K_0402_5%

PR80

5

PQ25

SI4800BDY-T1-E3_SO8

4

1 2

5

PQ27
SI4810BDY-T1-E3_SO8

4

DL_5V

12

100K_0402_5%

PR87

0_0402_5%

PR68

0_0603_5%~N

ACIN27,33

12

PC54

1U_1206_25V7K @

12

PC58

0.047U_0603_16V7K~N

PR65

1 2

0_0805_5%@

DH_5V

PC51

0.1U_0603_25V7K~N

1 2

PR77

10K_0402_5%

@

VL

12

PR85

806K_0603_1%

12

12

PQ28

RHU002N06_SOT323

DAP202U_SOT323

PR67

0_0805_5%

VL

12

PC49

4.7U_0805_6.3V6K~N

PR71 0_0603_5%~N

PR186

1 2

0_0402_5%

12

@

PR185
0_0402_5%

2VREF_8734

@

13

D

2

G

S

+LDO5

12

12

LX_5V

FB5

LDO3P

PQ29

D D

FBMA-L18-453215-900LMA90T_1812

C C

B B

PL4

B+

PF2

10A_65VDC_451010

2 1

12

PC40

4.7UH_SIL104R-4R7PF_5.7A_30%

+5VALWP

1

+

PC53

2

150U_V_6.3VM_R18

12

PC41

4.7U_1206_25V6K~N

PR76

10.2K_0402_1%@

1 2

PR81

0_0402_5%

1 2

BST_5V

PC56

1 2

@

D

S

PD11

@

12

13

2

1

VS

12

PR191

0_1206_5%

12

PC47

4.7U_1206_25V6K~N

PU5

14

BST5

16

DH5

15

LX5

19

DL5

21

OUT5

9

FB5

1

N.C.

6

SHDN#

4

ON5

3

ON3

12

SKIP#

8

REF

0.22U_0603_16V7K~N

PR88
100K_0402_5%

@

ACIN

2

G

3

PR66

18

B+++

12

0_1206_5%

20

V+

LD05

GND

23

@

D

S

PQ30

1 2

PC50

12

0.1U_0603_25V7K~N

13

17

TON

VCC

PGOOD

PRO#

LDO3

10

25

LDO3P

12

PC57

4.7U_0805_6.3V6K~N

13

2

G

VL

12

PC46

47_0402_5%

PC48

1 2

1U_0603_10V6K~N

5

11
28

26
24
27
22

7
2

1 2

1 2

PR84

@

0_0805_5%

0.1U_0402_16V7K~N

ILIM3

ILIM5

FB3

PR82

0_0402_5%

PR64

ILIM3

ILIM5
BST3

DH3

DL3

LX3

OUT3

FB3

MAX8734AEEI+_QSOP28

EC_ON 27,30

2VREF_8734

PR69

1 2

330K_0402_1%

PR72

1 2

499K_0402_1%

BST_3V
DH_3V

PR70

1 2

200K_0402_1%

PR73

1 2

499K_0402_1%

PR75

0_0603_5%~N

+LDO3

PR86

1 2

0_0805_5%@

0.1U_0603_25V7K~N

12

LX_3V

PC52

B+++

12

PC43

4.7U_1206_25V6K~N

0_0603_5%~N

12

12

PC44

4.7U_1206_25V6K~N

PR74

12

PC45

2200P_0402_50V7K~N

1 2

DL_3V

LX_3V

1 2

1 2

5

4

5

4

PR79

3.57K_0402_1%@

PR83

0_0402_5%

PQ24

D8D7D6D

SI4800BDY-T1-E3_SO8

S1S2S3G

D8D7D6D

PQ26

S1S2S3G

SI4810BDY-T1-E3_SO8

12

PL6

1

+

PC55

2

4.7UH_SIL104R-4R7PF_5.7A_30%

+3VALWP

150U_V_6.3VM_R18

A A

RHU002N06_SOT323

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

RHU002N06_SOT323

2005/12/1 2006/12/01

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

2

Date: Sheet

+5V/+3V

LA-3271P

Monday, August 21, 2006

1

34 42

of

0.4

5

D D

4

3

2

1

B++++

FBMA-L11-322513-151LMA50T_1210

12

PC60

4.7U_1206_25V6K~N

1

2

3

BST_1.5V-2

1 2

12

PR91

PC70

0_0603_5%~N

0.1U_0603_25V7K~N

LX_1.5V

PR94

1.15K_0402_1%

1 2

VSE_1.5V

12

PC76

12

PC61

@

4.7U_1206_25V6K~N

12

PC65

PC68

12

0.01U_0402_25V7K~N

BST_1.5V-1

DH_1.5VDH_1.5V

ISE_1.5V
DL_1.5V

12

PR105
105K_0402_1%

2.2U_0805_10V6K

PU6

12

SOFT1

6

BOOT1

5

UGATE1

4

PHASE1

7

ISEN1

2

LGATE1

3

PGND1

9

VOUT1

10

VSEN1

8

EN1

15

PG1

11

OCSET1

PR89

+5VALWP

1 2

10_0805_5%

12

PC67

1 2

PR90

2.2_0603_5%

0.1U_0603_25V7K~N

28

14

VIN

GND

1

SOFT2

VCC

BOOT2

UGATE2
PHASE2

ISEN2

LGATE2

PGND2

VOUT2
VSEN2

EN2

PG2/REF

OCSET2

DDR

ISL6227CAZ-T_SSOP28

13

17

0.01U_0402_25V7K~N

23

24
25

22
27

26

20
19
21
16

18

12

PC59

0.1U_0603_25V7K~N

RB717F_SOT323-3

PQ33
AO4704_SO8

VOUT_1.5V

PR99

1 2

0_0402_5%

PD14

RB751V_SOD323 @

1 2

0.1U_0402_16V7K~N@

PD13

PQ32

SI4800BDY-T1-E3_SO8

C C

+1.5VSP

1

PC72

2

220U_D2_4VM_R15

PR97

6.81K_0402_1%

1.8UH_SIL104R-1R8PF_9.5A_30%

+

12

12

12

PR102

B B

10K_0402_1%

PC73

0.01U_0402_25V7K~N

1 2

12

PR93
0_0402_5%

12

PR104

PL8

0_0402_5% @

5

D8D7D6D

S1S2S3G

4

5

D/K8D/K7D/K6D/K

S/A1S/A3G

S/A

4

2

SUSP# SYSON

12

BST_1.8V-2

PC69

BST_1.8V-1

ISE_1.8V
DL_1.8V

PC66

2.2U_0805_10V6K

12

1 2

PR92

0_0603_5%~N

DH_1.8V
LX_1.8V

1 2

VOUT_1.8V
VSE_1.8V

12

PR106
75K_0402_1%

12

PC62

@

4.7U_1206_25V6K~N

0.1U_0603_25V7K~N

PR95

1.65K_0402_1%

12

PC63

4.7U_1206_25V6K~N

12

PC71

1 2

PR100 10K_0402_5%

12

PC77

0.1U_0402_16V7K~N@

5

4

5

4

PL7

12

PC64

0.1U_0603_25V7K~N

D8D7D6D

PQ31

SI4800BDY-T1-E3_SO8

S1S2S3G

PL9

1.8UH_SIL104R-1R8PF_9.5A_30%

1 2

PQ34

D/K8D/K7D/K6D/K

AO4704_SO8

S/A1S/A3G

S/A

2

12

PR96

0_0402_5%

PR103

0_0402_5% @

PF3

2 1

7A_24VDC_429007.WRML

12

12

PC75

0.01U_0402_25V7K~N

12

12

PR98

0.9V0.9V

12

PR101

B+

+1.8VP

PC74

220U_D2_4VM_R15

10.2K_0402_1%

10K_0402_1%

1

+

2

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/12/1 2006/12/01

Compal Secret Data

Deciphered Date

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

+1.8V/+1.5V

Monday, August 21, 2006

1

35 42

0.4

of

5

PL10

FBMA-L18-453215-900LMA90T_1812

PF4

2 1

B+

D D

7A_24VDC_429007.WRML

SUSP#32,33,34,40

C C

B B

PR121

+3VALW

SUSP#

0_0402_5%

PR124

12K_0402_1%

PC97

1U_0603_6.3V6M~N

12

12

12

PC91

4.7U_0805_6.3V6K

12

1 2

1 2

PR189

1 2

0_0402_5%

PU9

1

IN

4

BYP

3

SHDN

G914E_SOT23-5

PC94

0.01U_0402_25V7K~N

OUT

GND

12

PC78

12

5

2

4

10U_1206_25V6M~N

PC85

0.1U_0402_16V7K~N

+2.5VSP

12

12

PC79

10U_1206_25V6M~N

0.01U_0603_50V7K@

6269_VCC

12

PC83

2.2U_0603_6.3V6K

PC92

4.7U_0805_6.3V6K

PR109

0_0603_5%~N

1 2

PC81

12

PR113

1 2

0_0402_5%

12

PC87

PGD_IN

22P_0402_50V8J

PU7

1

VIN

2

VCC

3

FCCM

4

EN

12

12

+5VS

1 2

17

16

GND

PGOOD

COMP5FB6FSET

PR116

49.9K_0402_1%

PC88
6800P_0402_25V7K

3

PR107
10K_0402_5%

14

15

PHASE

7

12

PR117

57.6K_0402_1%

12

PR119
3K_0402_1%

PHASE_VCCPP

BOOT_VCCPP

13

UG

BOOT

PVCC

PGND

ISEN

VO

8

12

PC86

0.01U_0402_25V7K~N

SUSP24,34

PR108

1 2

2.2_0603_5%

12

11

LG

10

9

UG_VCCPP

1 2

PC80 0.1U_0603_25V7K

12

PR110

4.7_0603_5%

@

PR111

1 2

4.7_0603_5%

1 2

2.2U_0603_6.3V6K

LG_VCCPP

ISEN_VCCPP

1 2

11.5K_0402_1%

ISL6269CRZ-T_QFN16

PR118

1 2

2.26K_0402_1%

10U_1206_25V6M~N

PR122

0_0402_5%

1 2

PC96

0.1U_0402_16V7K~N @

+5VS

6269_VCC

PC82

PR114

PC89

2N7002-7-F_SOT23-3

12

+1.8V

PQ37

2

5

PQ35

D8D7D6D

S1S2S3G

SI4800BDY-T1-E3_SO8

4

PR112
10K_0402_5%

@

1 2

5

4

1

PJP12

1

JUMP_43X118@

2

2

12

13

D

2

G

S

PR120

1K_0402_1%

PR123

12

12

1K_0402_1%

12

PC93

0.1U_0402_16V7K~N

PL11
1UH_SIL1035-1R0PF_9A_20%

1 2

PQ36

D8D7D6D

SI4810BDY-T1-E3_SO8

S1S2S3G

PU8

VIN1VCNTL

2

GND

3

VREF

4

VOUT

G2992F1U_SO8

+0.9VSP

12

PC95
10U_1206_25V6M~N

1

+

6
5

NC

7

NC

8

NC

9

TP

PC84
220U_D2_4VM_R15

2

+VCCPP

+3VALW

12

PC90
1U_0603_6.3V6M~N

1

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/12/1 2006/12/01

Compal Secret Data

Deciphered Date

Title

+VCCPP/+2.5VSP/0.9VSP

Size Document Number Rev

LA-3271P 0.4

Custom

2

Date: Sheet

1

of

36 42Monday, August 21, 2006

5

PC98

5600P_0402_25V7K

D D

DPRSLPVR21

H_DPRSTP#6,20

CLK_EN#17

PR130 0_0402_5%

12

PC107

1.91K_0402_1%

1U_0603_10V6K~N

PC126 0.022U_0603_25V7K

12

PC127

0.022U_0603_25V7K

@

12

1 2

PR162 1K_0402_1%

0.22U_0603_16V7K

1 2

12

12

1 2

PR159 0_0402_5%

+3VS

+3VS

PR133

499_0402_1%

VGATE19,21,32

H_PSI#7

C C

PR141 4.22K_0402_1%@

PGD_IN

VR_TT#

1 2

PR140 147K_0402_1%

1 2

PH1

1 2

100K_0603_1%_TH11-4H104FT@

1 2

PC1140.015U_0402_16V7K@

PR142 11.5K_0402_1%

1 2

PC117

1000P_0402_50V7K~N

1 2

PR145 4.42K_0402_1%

1 2

1 2

PC118 47P_0402_50V8J~N

PR151 82.5K_0402_1%

1 2

B B

VCCSENSE7

+CPU_CORE

A A

1 2

PC123 390P_0402_50V7K

3.4K_0402_1%

1 2

PR153

PR155 1.82K_0402_1%

PR156 0_0402_5%

1 2

PR157 20_0402_5%

VSSSENSE7

5

1 2

1 2

PR132

1 2

PR139 0_0402_5%

1 2

PC1150.068U_0603_50V7K~N

1 2

PC120 0.022U_0402_16V7K~N

12

PC124 470P_0402_50V7K

1 2

PR160

20_0402_5%

VCC_PRM

@

PR126 0_0402_5%

1 2

PR127 0_0402_5%

1 2

PR128 0_0402_5%

1 2

49

GND

1

PGOOD

2

PSI#

3

PGD_IN

4

RBIAS

5

VR_TT#

6

NTC

7

SOFT

8

OCSET

9

VW

10

COMP

11

FB

12

FB2

PR152
0_0402_5%@

1 2

PC129 180P_0402_50V8J

1 2

1 2

PR163 3.57K_0402_1%

PC131

4

7

7

7

32

12

CPU_VID47CPU_VID3

48

47

3V3

CLK_EN#

CPU_VID6

VR_ON

12

12

PR129

0_0402_5%

45

46

44

43

VR_ON

DPRSTP#

DPRSLPVR

ISL6262CRZ-T_QFN48

CPU_VID5

12

PR178 0_0402_5%

12

12

PR179 0_0402_5%

PR180 0_0402_5%

CPU_VID27CPU_VID17CPU_VID0

12

12

PR182 0_0402_5%

PR181 0_0402_5%

VDIFF13VSEN14RTN15DROOP16DFB17VO18VSUM19VIN20GND21VDD22ISEN223ISEN1

12

PC122
1U_0603_6.3V6M~N

PR154

1 2

12

10_0603_5%~N

PC125

0.1U_0603_25V7K

12

PC128

0.022U_0603_25V7K

12

4

VSUM

PC130 0.068U_0603_50V7K~N

1 2

PC132 0.22U_0603_10V7K

12

12

PR161

12

PR158

PH2
10KB_0603_ERTJ1VR103J

11K_0402_1%

1 2

3

+5VS

7

12

12

PC105

PC104

PC103

12

0.01U_0402_25V7K~N

PR184 0_0402_5%

PR183 0_0402_5%

VID037VID138VID239VID340VID441VID542VID6

36

BOOT1

35

UGATE1

34

PHASE1

33

PGND1

32

LGATE1

31

PVCC

30

LGATE2

29

PGND2

28

PHASE2

27

UGATE2

26

BOOT2

25

NC

PU10

24

ISEN1
ISEN2

1 2

PR150 1_0603_5%

2.61K_0402_1%

BOOT_CPU1

UGATE_CPU1
PHASE_CPU1

BOOT_CPU2

2.2_0603_5%

+5VS

+CPU_B+

2.2_0603_5%

LGATE_CPU1

LGATE_CPU2

PHASE_CPU2

UGATE_CPU2

PR143

1 2

1 2

1U_0603_6.3V6M~N

PC108

0.22U_0603_10V7K

PR131

1 2

PC116

1 2

0.22U_0603_10V7K

IRF8113PBF_SO8

IRF8113PBF_SO8

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2005/12/1 2006/12/01

3

PR125
1_0603_5%

1 2

12

12

PC106

1U_0603_6.3V6M~N

0.01U_0402_25V7K~N

578

PQ39

3 6

241

578

PQ42

3 6

241

Compal Secret Data

Deciphered Date

3 5

241

578

3 6

241

IRF8113PBF_SO8

3 5

241

578

3 6

241

PQ38
SI7840DP-T1-E3_SO8

PQ40

PQ43
IRF8113PBF_SO8

2

12

PC100

10U_1206_25V6M~N

12

PR134

4.7_1206_5%~N

12

@

PC109

680P_0603_50V8J

@

PQ41
SI7840DP-T1-E3_SO8

12

PR144

4.7_1206_5%~N

@

12

PC119
680P_0603_50V8J

@

2

1

+CPU_B+

FBMA-L18-453215-900LMA90T_1812

1

12

PC101

@

10U_1206_25V6M~N

PC111

10U_1206_25V6M~N

12

+

PC102

P_0.36H_ETQP4LR36WFC_24A_20%

12

PR135

3.65K_1206_1%

VSUM

12

12

PR147

VSUM

2

10U_1206_25V6M~N

12

PL13

PR136

PR138 0_0402_5%@

10K_0402_1%

1 2

PC110

1 2

ISEN1

0.22U_0603_16V7K

12

PC112

10U_1206_25V6M~N

P_0.36H_ETQP4LR36WFC_24A_20%

12

PR146

3.65K_1206_1%

10K_0402_1%

PR149 0_0402_5%@

1 2

PC121

1 2

0.22U_0603_16V7K

ISEN2

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Monday, August 21, 2006

Date: Sheet

1 2

PC99

220U_25V_M~N

12

12

PC113

@

10U_1206_25V6M~N

12

PL14

+CPU_CORE

LA-3271P

PL12

12

PR137

1_0402_5%

VCC_PRM

+CPU_B+

12

PR148
1_0402_5%

VCC_PRM

PF5

2 1

8A_125V_451008MRL

1

+CPU_CORE

37 42

of

B+

0.4

5

D D

4

3

2

1

BATT+

PL15

FBMA-L18-453215-900LMA90T_1812

BATT+

1 2

12

PC134

0.01U_0402_25V7K~N

PJPB1 battery connector

SMART
Battery:

C C

B B

1.BAT+

2.BAT+

3.ID

4.B/I

5.TS

6.SMD

7.SMC

8.GND

9.GND

BATT++

12

PC133
1000P_0402_50V7K~N

SUYIN_200275MR009G154ZL_RV

PJP13

BATT+
BATT+

ID

B/I

TS

SMD

GND
GND

SMC
GND­GND-

10
11

BATT++

MH/LI#

+3VALWP

1 2

1 2

PR169

100_0402_5%

1 2

PR170

100_0402_5%

PR164
47K_0402_5%~N

PR166

1K_0402_5%

@

12

MH/LI# 34

AMH/LI#

PR167

1K_0402_5%

EC_SMB_DA1 27,28

EC_SMB_CK1 27,28

12

Place clsoe to EC pin

BATT_TEMP

1 2

PR165

1K_0402_5%

1 2

1 2

PR168

6.49K_0402_1%

PC135

0.1U_0402_16V7K~N

@

CPU

12

PC138

0.22U_0603_16V7K~N

BATT_TEMP 27

CPU

+3VALWP

PH1 under CPU botten side :

CPU thermal protection at 90 +-3 degree C
Recovery at 50 +-3 degree C

VL VS

12

PR173
0_0402_5%

PR174

200K_0402_1%

1 2

VL

PC136

0.1U_0402_16V7K~N@

1 2

PR175

100K_0402_1%

100K_0402_1%

12

PR177

12

PH3
100K_0603_1%_TH11-4H104FT

12

12

PR176
20K_0402_1%

PR171

499K_0402_1%

1 2

12

PC139
1000P_0402_50V7K~N

8

3

+

2

-

4

21

PF6
15A_65VDC_451015

1
2
3
4
5
6
7
8
9

Battery Connect/OTP

PC137

0.1U_0603_25V7K~N

1 2

VL

PR172
499K_0402_1%

PU11A

P

G

LM393DR_SO8

1 2

1

O

MAINPWON33,35

13

D

2

G

PQ44

S

RHU002N06_SOT323

5
6

8

+

-

4

PU11B

P

7

O

G

LM393DR_SO8

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/12/1 2006/12/01

Compal Secret Data

Deciphered Date

Title

BATTERY CONN

Size Document Number Rev

LA-3271P 0.4

Custom

2

Date: Sheet

1

of

38 42Monday, August 21, 2006

5

4

3

2

1

Version Change List ( P. I. R. List )

Page 1

Request

Item Issue DescriptionDate

1

D D

2

3

4

5

6

C C

7

8

10

33 PWR-Charger Apr. 7 Compal add VIN OVP funtion 0.2

34 +3VALWP/+5VALWP Apr. 27 Compal Chang low noise skip mode to skip mode for decrease power consumption. add PR185 0 ohm 0.2

38

34 +3VALWP/+5VALWP Aug. 11 Compal slove can not power on under adapter mode after add LD03 power plane add PR191 0 ohm connect to VS NET 0.4

33 PWR-Charger Aug. 7 Compal decrease inrush current when PQ8 turn on

BATTERY CONN Apr. 27 Compal Change EC confirm battery type method from battery ID pin to SMBUS.

PWR-VCCPP/2.5V/0.9V CompalJuly. 17 add RC delay time resister for HW request add PR189 0 ohm36

Owner

PR34 47K , PR35 100K , PR187 220K , PR188 4.7K
PQ45 PQ13 SB301150000(DTC115EUA) , PQ46 SB339045100 (PMBT3904) ,
PD15 PD16 SC1SS355003 (1SS355) , PD17 SC4LZ22B006 (RLZ22B)

PR166 non-POP

ADD PC139 0.1U

Solution Description Rev.Page# Title

0.2

0.3

11

12

13

B B

14

15

16

17

A A

Compal Electronics, Inc.

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

Next: PR238, PC202, PQ56, PD42, PJP21

5

4

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

PW-PIR

Size Document Number Rev

LA-3271P

Date: Sheet

Monday, August 21, 2006 4239

1

of

0.4

5

4

3

2

1

Version Change List ( P. I. R. List )

Page 1/1

Request

Item Issue DescriptionDate

1

D D

2

3

4

5

6

7

8

9

10

11

12

C C

13

14

15

16

17

18

19

20

21

22

B B

23

24

25

26

27

28 23 Mini card & LAN CONN NECJun. 13th For both INTEL GOLAN and ALPS WLAN LED function OK. 0.3Modify circuit and use 2 DIP Switch to control.

29 26 EC KB910L/REED SW/TPM1.2

31

32

A A

CRT Conn.& LCD Conn.14

EC KB910L/REED SW/TPM1.2

26

27 KB / TouchPad / BIOS/Felica Apr. 2nd COMPAL Feloca can't detect. Swap pin 2& 3 (pin2->D-; pin3->D+) 0.2

Clock Generator13 COMPALApr. 2nd Cardbus can't detect. Add cardbud CLK. 0.2

13 Clock Generator Apr. 2nd COMPAL CPU_CLK 266MHZ issue. Take off R894 0.2

22 Apr. 2ndBCM5787M-GLAN COMPAL LAN can't detect . Swap VMIN(pin53) & VAUX(pin54) power plan 0.2

22 BCM5787M-GLAN Apr. 2nd COMPAL EEPROM can't detect . Change R868 to 0 ohm 0.2

13 Clock Generator Apr. 2nd COMPAL +3VS leakage issue Add D15, D19.

19 HDD/CDROM Apr. 2nd COMPAL HD can't detect SATA TX & RX pin swap 0.2

20 CardBus/R5C841/R5C811(1/2) Apr. 2nd COMPAL cardbus of device manager show "!" UDIO3 & 4 change to GND for HW select 0.2

6 Yonah bypass Apr. 2nd COMPAL Use 2 330U for Decoupling Take off C677 & C680 0.2

28 USB Conn/FINGERPRINT Apr .20th COMPAL Fingerprint can;t be detect Swap Fingerprint signal for correct pin define 0.2

26 EC KB910L/REED SW/TPM1.2 COMPAL +5VS leakageApr. 20th Chaneg EC_MUTE pull high to +3VS 0.2

Clock Generator13 May. 4th COMPAL Dubug code '28' issue Take off D12 & D13, mount Q20, Q21

26 EC KB910L/REED SW/TPM1.2 May. 17th +3VS leakage issue Modify EC_MUTE pull high to +3VALW

28 USB Conn/FINGERPRINT May. 17th

CRT Conn.& LCD Conn.14

30 Power CTRL/ RESET CKT May. 17th COMPAL For +1.5VS discharge Add +1.5VS discharge circuit. (Q44) 0.3

18 ICH7-M(4/4)_POWER&GND May. 17th COMPAL For SB +3VALW modify to +3V reserve by jump select for power consumption save

Clock Generator13 COMPAL

4 Yonah(1/2)-GTL/ITP-XDP May. 23th NEC For FAN power issue prevent Modify R350 PAD size to 1206 for Fuse.

14 CRT Conn.& LCD Conn. COMPAL H_SYNC, V_SYNC over/under shoot issue

14 CRT Conn.& LCD Conn. Jun. 1st COMPAL Fine tune LCDVDD discharge time. Modify R14 to 300 ohm, R30 to 100K ohm, R25 to 10K.

CRT Conn.& LCD Conn.1430 COMPAL

25

23

23 Mini card & LAN CONN Aug. 10th NEC For both INTEL GOLAN and ALPS WLAN LED control by software Add U39

Mar. 28th 0.2

Mar. 28th COMPAL Add ICH_POK & GMCH_ENBKL to pin 80& 81 Add ICH_POK & GMCH_ENBKL to pin 80& 81 0.2

Apr. 27thBCM5787M-GLAN22 Material change for same typeNEC

May. 17th EMI For EMI request Change L8, L9, L10 form FCM2012C-800 to BK2125LL121-T 0.3

May. 17th For CLK SPEC define Modify R381, R382 form 0 to 24ohm 0.3

Jun. 6thAMP./ Audio Jack25 For PCMCIA-Modem card dial tone too samll issue.COMPAL Modify Buzzer circuit.

Aug. 10th

Aug. 10th

Aug. 10th

Aug. 10th COMPALMini card & LAN CONN

Owner

COMPAL

COMPAL14 CRT Conn.& LCD Conn. White screen when boot.Apr. 2nd 0.2Use NB to control LCD backlight

COMPAL

COMPAL

NEC

COMPAL For S5 power consumption

Add LVDS-EDID CLK&DAT pull high Add pull high to +3VS for EDID_CLK & EDID_DAT

Change L15 to CHB1608U301 0.2

Change R319 to LAN vender suggestion oneApr. 27thMini card & LAN CONN23

For USB port 5 OC protect 0.3Add USB_OC#5 to U22

in S5.

Change R319 to CHB1608U301 0.2

Add PJP15 & PJP15 for +3VALW and +3V select for SB. 0.3

Add R526 & R527.May. 28th

Added LDO3 power plan

For V/H sync delay Del R526 & R527.Change C308 C311

Add C548 & C549.For EMI requestAMP./ Audio Jack COMPAL

For LAN immunity

Change R556,R557,R558,R559 to 0ohm

Solution Description Rev.Page# Title

0.2

0.3

0.3

0.3

0.3

0.3

0.3

Compal Electronics, Inc.

Title

EE PIR-1

Size Document Number Rev

LA-3271P

Date: Sheet

5

4

3

2

Monday, August 21, 2006 4240

1

0.4

of

5

4

3

2

1

AK1 Power block

RTC Charger

D D

Battery OVP

Vin Detector

Page 32

Input

DC IN

C C

CHARGER

Switch

Turn Off

Page 33

Page 33

+CHGRTC

B+

Page 32

CPU OTP

Page 38

Turn Off

+3VALWP: OCP:6A OVP:107%~115%
+5VALWP: OCP:8A OVP:107%~115%
(MAX8734A)

Page 34

Always

CC:0.6A~3.3A
CV:16.8V
(MB3887)

Page 33

+3VALW

+2.5VSP
Thermal protection: 150 degree C
(G914E)

Page 36

SUSP#

Battery

B B

CPU CORE

+1.8VP: OCP:11.7A OVP:110%~115%
+1.5VSP: OCP:6A OVP:110%~115%
(ISL6227)

+1.8V

+0.9VSP
Thermal protection: 160 degree C
(G2992F)

Page 35

Page 36

+1.8VP:SYSON

+1.5VSP:SUSP#

SUSP

VR_ON

OCP:54A
OVP:2V
(ISL6262)

Page 37

+VCCP:OCP:12A OVP:115%

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

(ISL6269)

3

2005/12/1 2006/12/01

Compal Secret Data

Deciphered Date

2

Page 36

SUSP#

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, M/B LA-3271P

1

0.4

of

41 42Monday, August 21, 2006

5

4

3

2

1

ACIN/BATT-IN

D D

ON/OFF

EC_ON

PWRBTN_OUT#

t1=10ms

SYSON

+5/3.3/1.8V

C C

RSMRST#

t2=120ms

t3=40ms

SLP_S5/4/3#

SUSP#

t4=100ms

t5=100ms

+5/3.3/1.8/0.9VS

+VCCP

B B

VR_ON#

+CPU_CORE

VGATE

ICHPWROK

t6=30ms

t7=70ms

PCI_RST#/PLT_RST#

A A

CPU_RST#

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Compal Secret Data

2005/12/1 2006/12/01

2

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

Power Sequence

Monday, August 21, 2006

1

LA-3271P

42 42

0.4

of