COMPAL LA-3271P Schematics

A

1 1

B

C

D

E

2 2

Compal Confidential

Schematics Document

945GM+ICH7

2006 / 08 / 18

3 3

Rev:0.4

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2005/12/1 2006/12/01

Compal Secret Data

Deciphered Date

Title

Cover Sheet

Size Document Number Rev

Custom

LA-3271P

D

Date: Sheet

E

142Monday, August 21, 2006

0.4

of

A

B

C

D

E

Compal confidential

Project Code: ANRIAL3000(IAL30)
File Name : LA-3271P

1 1

Thermal Sensor
ADM1032ARM

page 4 page 13

Clock Generator
ICS9LPR310

CRT

page 14

LCD CONN

page 14

YONAH CPU

page 4,5,6

533/667MHZ

Calistoga GMCH

PCBGA1466

page 9,10,11,12

2.5GHz(1.2V)

Bandwidth 500MB

DMI

DDR-2 DDR2-SO-DIMM X2

page 7,8

Daul Channel DDR-2

2 2

PCI EXPRESS

ICH7-M

Broadcom

BCM5787

page 22

Mini Card

page 23

PCI BUS

BGA652

page 15,16,17,18

USB 2.0

USB 2.0

HD-Interface

RJ45 CONN

page 23

CradBus Controller

R5C811

page 20,21

LPC BUS

SATA

USB conn x 4

page 29

Finger print

page 28

Audio CKT
ALC262

page 24

MDC Conn.

page 24

AMP & Audio Jack

RJ11 Conn

SATA HDD Conn.

page 19

page 25

PATA

3 3

CDROM Conn.

page 19

Slot 0

page 21

ENE KB910L

page 26

Power On/Off CKT.

page 30

Touch Pad

DC/DC Interface CKT.

page 32

4 4

Power Circuit DC/DC

page 33~41

A

RTC CKT.

page 16

Power OK CKT.

page 30

Issued Date

page 27

2005/12/1 2006/12/01

C

CONN.

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Int. KBD

page 27

BIOS

page 27

Compal Secret Data

Deciphered Date

TPM Conn

page 26

FINGERPRINT Conn

page 28

Title

Block Diagrams

Size Document Number Rev

Custom

LA-3271P

D

Date: Sheet

E

242Monday, August 21, 2006

0.4

of

A

Voltage Rails

Power Plane Description

VIN

1 1

2 2

B+
+5VALW
+3VALW
+RTCVCC RTC power
+5V 5V power rail ON OFFON
+3V
+1.8V
+5VS
+3VS
+2.5VS 2.5V switched power rail
+1.5VS
+0.9VS 0.9V switched power rail for DDR terminator
+CPU_CORE
+VCCP

Adapter power supply (19V)
AC or battery power rail for power circuit.
5V always on power rail

3.3V always on power rail

3.3V power rail

1.8V power rail for DDR
5V switched power rail

3.3V switched power rail

1.5V switched power rail

Core voltage for CPU

1.05V power rail

B

S1 S3 S4/ S5

ON ON ON

ON
ON
ON ONON

ON
ON

ON
ON OFF OFF
ON OFF OFF
ON OFF
ON OFF
ON OFF

ONONON
ON ON
ON ON

OFF

ON

OFF

ON

OFFON

OFF
OFF

OFF

OFF

OFF

OFF

C

SIGNAL

STATE

Full ON

S1(Power On Suspend)

S3 (Suspend to RAM)

SLP_S1# SLP_S3#

HIGH HIGH HIGH HIGH

LOW

LOW

LOW

S4 (Suspend to Disk)

S5 (Soft OFF)

LOW LOW LOW LOW

Board ID Table for AD channel

Vcc 3.3V +/- 5%

Board ID

0
1
2
3
4
5
6
7 NC

100K +/- 5%Ra / Rc

Rb / Rd V min

0

8.2K +/- 5%
18K +/- 5%
33K +/- 5%
56K +/- 5%
100K +/- 5%
200K +/- 5%

AD_BID

0 V

0.216 V 0.250 V 0.289 V

0.436 V

0.712 V

1.036 V

1.453 V 1.650 V 1.759 V

1.935 V

2.500 V

D

SLP_S4# SLP_S5# +VALW +V +VS Clock

ON

ON

ON

OFF

OFF

V

AD_BID

ON ON

ON

OFF

OFF

OFF

max

LOW

OFF

OFF

OFF

HIGH

LOWLOWLOW

HIGHHIGHHIGH

HIGH

HIGH

V typ

AD_BID

ON

ON

ON

ON

ON

0 V 0 V

0.503 V

0.819 V

0.538 V

0.875 V

1.185 V 1.264 V

2.200 V

3.300 V

2.341 V

3.300 V

E

External PCI Devices

Device IDSEL# REQ#/GNT# Interrupts

CardBus
Mini-PCI

AD21
AD22

0
1

PIRQE/PIRQF/PIRQG
PIRQF/PIRQG

BOARD ID Table

Board ID

0
1
2

PCB Revision

0.1

0.2

BTO Item BOM Structure

BTO Option Table

3
4
5
6
7

EC SM Bus1 address

3 3

Device

Smart Battery
EEPROM(24C16/02)

(24C04)

Address Address

1010 000X b?
1011 000Xb?

EC SM Bus2 address

Device

ADM1032

1001 110X b?0001 011X b?

ICH7 SM Bus address

Device

Clock Generator
(ICS ICS9LPR310)

DDRII DIMM0
DDRII DIMM2

4 4

Address

1101 001Xb?

1001 000Xb?
1001 010Xb?

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2005/12/1 2006/12/01

Compal Secret Data

Deciphered Date

Title

Notes

Size Document Number Rev

Custom

LA-3271P

D

Date: Sheet

E

342Monday, August 21, 2006

0.4

of

5

H_A#[3..31]9

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11

D D

H_REQ#[0..4]9

H_ADSTB#09
H_ADSTB#19

C C

1 2

+VCCP

B B

H_THERMDA, H_THERMDC routing together.
Trace width / Spacing = 10 / 10 mil

A A

CLK_CPU_BCLK#13

R87

56_0402_5%

H_RS#[0..2]9

R73 1K_0402_5%@

1 2

R79 51_0402_5%

1 2

+VCCP

CLK_CPU_BCLK13

H_DEFER#9

H_RESET#9

ITP_DBRESET#17

H_DPSLP#16

H_DPRSTP#16,37

H_DPWR#9

H_PWRGOOD16

H_CPUSLP#9,16

H_THERMTRIP#9,16

R392

54.9_0402_1%

1 2

5

H_ADS#9
H_BNR#9
H_BPRI#9

H_BR0#9

H_DRDY#9

H_HIT#9

H_HITM#9

H_LOCK#9

H_TRDY#9

H_DBSY#9

H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

H_ADSTB#0
H_ADSTB#1

CLK_CPU_BCLK
CLK_CPU_BCLK#

H_ADS#
H_BNR#
H_BPRI#
H_BR0#
H_DEFER#
H_DRDY#
H_HIT#
H_HITM#
H_IERR#
H_LOCK#
H_RESET# H_D#58

H_RS#0
H_RS#1
H_RS#2
H_TRDY#

ITP_BPM#0
ITP_BPM#1
ITP_BPM#2
ITP_BPM#3

ITP_DBRESET#

H_DBSY#
H_DPSLP#
H_DPRSTP#
H_DPWR#
ITP_BPM#4
ITP_BPM#5
H_PROCHOT#

H_PWRGOOD
H_CPUSLP#
ITP_TCK
ITP_TDI
ITP_TDO
TEST1
TEST2
ITP_TMS
ITP_TRST#

H_THERMDA
H_THERMDC
H_THERMTRIP#

H_RESET#

JP2A

J4

A3#

L4

A4#

M3

A5#

K5

A6#

M1

A7#

N2

A8#

J1

A9#

N3

A10#

P5

A11#

P2

A12#

L1

A13#

P4

A14#

P1

A15#

R1

A16#

Y2

A17#

U5

A18#

R3

A19#

W6

A20#

U4

A21#

Y5

A22#

U2

A23#

R4

A24#

T5

ADDR GROUP

A25#

T3

A26#

W3

A27#

W5

A28#

Y4

A29#

W2

A30#

Y1

A31#

K3

REQ0#

H2

REQ1#

K2

REQ2#

J3

REQ3#

L5

REQ4#

L2

ADSTB0#

V4

ADSTB1#

A22

BCLK0

A21

H1

E2

G5

F1

H5

F21

G6

E4

D20

H4

B1

F3

F4
G3
G2

AD4
AD3
AD1
AC4

C20

E1

B5

E5

D24
AC2
AC1
D21

D6
D7

AC5
AA6
AB3
C26
D25
AB5
AB6

A24
A25

C7

HOST CLK

BCLK1

ADS#
BNR#
BPRI#
BR0#
DEFER#
DRDY#
HIT#

CONTROL

HITM#
IERR#
LOCK#
RESET#

RS0#
RS1#
RS2#
TRDY#

BPM0#
BPM1#
BPM2#
BPM3#

DBR#
DBSY#
DPSLP#
DPRSTP#
DPWR#
PRDY#
PREQ#
PROCHOT#

PWRGOOD
SLP#
TCK
TDI
TDO
TEST1
TEST2
TMS
TRST#

THERMAL

THERMDA

DIODE

THERMDC
THERMTRIP#

FOX_PZ47823-2743-41_YONAH

YONAH

MISC

H_DPSLP#

H_DPRSTP#

4

DATA GROUP

LEGACY CPU

+VCCP

R143

1 2

56_0402_5%@

R145

1 2

56_0402_5%@

4

D10#
D11#
D12#
D13#
D14#
D15#
D16#
D17#
D18#
D19#
D20#
D21#
D22#
D23#
D24#
D25#
D26#
D27#
D28#
D29#
D30#
D31#
D32#
D33#
D34#
D35#
D36#
D37#
D38#
D39#
D40#
D41#
D42#
D43#
D44#
D45#
D46#
D47#
D48#
D49#
D50#
D51#
D52#
D53#
D54#
D55#
D56#
D57#
D58#
D59#
D60#
D61#
D62#
D63#

DINV0#
DINV1#
DINV2#
DINV3#

DSTBN0#
DSTBN1#
DSTBN2#
DSTBN3#
DSTBP0#
DSTBP1#
DSTBP2#
DSTBP3#

A20M#
FERR#

IGNNE#

INIT#
LINT0
LINT1

STPCLK#

SMI#

3

H_D#[0..63] 9

H_D#0

E22

D0#

H_D#1

F24

D1#

H_D#2

E26

D2#

H_D#3

H22

D3#

H_D#4

F23

D4#

H_D#5

G25

D5#

H_D#6

E25

D6#

H_D#7

E23

D7#

H_D#8

K24

D8#

H_D#9

G24

D9#

H_D#10

J24

H_D#11

J23

H_D#12

H26

H_D#13

F26

H_D#14

K22

H_D#15

H25

H_D#16

N22

H_D#17

K25

H_D#18

P26

H_D#19

R23

H_D#20

L25

H_D#21

L22

H_D#22

L23

H_D#23

M23

H_D#24

P25

H_D#25

P22

H_D#26

P23

H_D#27

T24

H_D#28

R24

H_D#29

L26

H_D#30

T25

H_D#31

N24

H_D#32

AA23

H_D#33

AB24

H_D#34

V24

H_D#35

V26

H_D#36

W25

H_D#37

U23

H_D#38

U25

H_D#39

U22

H_D#40

AB25

H_D#41

W22

H_D#42

Y23

H_D#43

AA26

H_D#44

Y26

H_D#45

Y22

H_D#46

AC26

H_D#47

AA24

H_D#48

AC22

H_D#49

AC23

H_D#50

AB22

H_D#51

AA21

H_D#52

AB21

H_D#53

AC25

H_D#54

AD20

H_D#55

AE22

H_D#56

AF23

H_D#57

AD24
AE21

H_D#59

AD21

H_D#60

AE25

H_D#61

AF25

H_D#62

AF22

H_D#63

AF26

H_DINV#0

J26
M26
V23
AC20

H23
M24
W24
AD23
G22
N25
Y25
AE24

A6
A5
C4
B3
C6
B4

D5
A3

H_DINV#1
H_DINV#2
H_DINV#3

H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3
H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3

H_A20M#
H_FERR#
H_IGNNE#
H_INIT#
H_INTR
H_NMI

H_STPCLK#
H_SMI#

H_DINV#0 9
H_DINV#1 9
H_DINV#2 9
H_DINV#3 9

H_DSTBN#[0..3] 9

H_DSTBP#[0..3] 9

H_A20M# 16
H_FERR# 16
H_IGNNE# 16
H_INIT# 16
H_INTR 16
H_NMI 16

H_STPCLK# 16
H_SMI# 16

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

ITP_DBRESET#

R91 200_0402_5%@

1 2

ITP_BPM#0
ITP_BPM#1
ITP_BPM#2
ITP_BPM#3
ITP_BPM#4

EC_SMB_CK210,26
EC_SMB_DA210,26

KH3-ORG.

R78

100K_0402_5%

EN_DFAN126

1 2

100K_0402_5%

+VCCP

H_THERMTRIP#

2005/12/1 2006/12/01

Compal Secret Data

FAN1VREF

FAN1_VFB

1

C137

2

1U_0603_10V4Z

R353

1 2

150K_0402_5%

+CPU_CORE

12

R398

1 2

C413

@

0.1U_0402_10V6K~N

Deciphered Date

1 2

R393
56_0402_5%

2

PAD
PAD

PAD
PAD
PAD
PAD

H_THERMDA

2200P_0402_50V7K

H_THERMDC

B+_BIAS

8

U24A

3

P

+IN

OUT

2

-IN

G

4

LM358DR2G_SO8~N

C389

2200P_0402_50V7K

1 2

R351

100K_0402_5%

1

C

Q35

2

B

PMBT3904_SOT23

E

3

2

T11

ITP_TDI

T12

ITP_TMS

T14
T15

ITP_TDO

T13
T16

ITP_BPM#5
ITP_TRST#
ITP_TCK

1

C388

2

EC_SMB_CK2
EC_SMB_DA2

SMBus Address: 1001110X (b)

1

C379

2

1U_0805_10V4Z

FAN1_ON

1

12

D10

RB751V_SOD323

2 1

MAINPWON 32,34,38

1

This shall place near CPU

R138 56_0402_5%

1 2

R137 56_0402_1%

1 2

R142 56_0402_5%

1 2

R141 56_0402_5%

1 2

R135 56_0402_5%

1 2

R134 56_0402_5%

1 2

+3VS

from EFL50

2
3
8
7

1

G

3

1

C383

0.1U_0402_16V4Z

2

U25

VDD1

D+

ALERT#

D-

THERM#

SCLK

GND

SDATA

ADM1032ARMZ MSOP 8P

+5VS

FAN1 Control and Tachometer

R350
0_1206_5%

1 2

10K_0402_5%

6

2

D

Q32

S

SI3456DV-T1_TSOP6

4 5

FAN1_POWER

1

1

2

C132

2

C135

22U_1206_10V4Z

+3V

C

Title

Size Document Number Rev

Custom

LA-3271P

Date: Sheet

+VCCP

Thermal Sensor
ADM1032

12

R348

10K_0402_5%@

1
6

THERM#

4
5

+3VS

12

R70

C133

0.01U_0402_16V7K

JFAN1

1
2
3

4

G

5

G

MOLEX_53398-0371~N

FAN1

1 2

YONAH

FAN_SPEED1 26

H_PROCHOT#

1

2

1

1000P_0402_50V7K~N

12

R93

Level shifter

@

330_0603_5%

H_PROCHOT_SIO#

2

B

R88 56_0402_5%@

E

Q15

@

3 1

MMBT3904_SOT23

1 2

R92 56_0402_5%

H_PROCHOT#

Compal Electronics, Inc.

+VCCP

+VCCP

442Monday, August 21, 2006

0.4

of

A

B

C

D

E

+VCCP

12

V_CPU_GTLREF

4 4

R77
1K_0402_1%

12

R72
2K_0402_1%

Close to CPU pin AD26
within 0.5 inch

CPU_BSEL CPU_BSEL2 CPU_BSEL1

133

166

3 3

2 2

00

0

+CPU_CORE

Close to CPU pin
within 500mils.

CPU_BSEL0

1

R368
100_0402_1%

1 2

R389
100_0402_1%

1 2

1

1

12

R84

27.4_0402_1%

VCCSENSE

VSSSENSE

12

R83

54.9_0402_1%

R394

27.4_0402_1%

Length match within 25 mils
The trace width 18 mils space
7 mils

+1.5VS

1

1

C140

12

0.01U_0402_16V7K

Resistor placed within

12

0.5" of CPU pin.Trace

should be at least 25

mils away from any

R395

other toggling signal.

54.9_0402_1%

2

2

VCCSENSE37
VSSSENSE37

C134
10U_0805_10V4Z~N

H_PSI#37

CPU_VID037
CPU_VID137
CPU_VID237
CPU_VID337
CPU_VID437
CPU_VID537
CPU_VID637

V_CPU_GTLREF

CPU_BSEL013
CPU_BSEL113
CPU_BSEL213

+CPU_CORE

+VCCP

VCCSENSE
VSSSENSE

H_PSI#
CPU_VID0

CPU_VID1
CPU_VID2
CPU_VID3
CPU_VID4
CPU_VID5
CPU_VID6

CPU_BSEL0
CPU_BSEL1
CPU_BSEL2

COMP0
COMP1
COMP2
COMP3

JP2B

AF7

VCCSENSE

AE7

VSSSENSE

B26

VCCA

K6

VCCP

J6

VCCP

M6

VCCP

N6

VCCP

YONAH

VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP

PSI#
VID0

VID1
VID2
VID3
VID4
VID5
VID6

GTLREF
BSEL0

BSEL1
BSEL2

COMP0
COMP1
COMP2
COMP3

VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC

RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD

FOX_PZ47823-2743-41_YONAH

W21

AD6

AD26

AB20
AA20

AF20
AE20
AB18
AB17
AA18
AA17
AD18
AD17
AC18
AC17

AF18

AF17

K21
M21

N21
R21

V21

G21

AE6

AF5
AE5
AF4
AE3
AF2
AE2

B22
B23
C21

R26
U26

AF1
D22
C23
C24
AA1
AA4
AB2
AA3

B25

T6
R6

J21

T21

V6

U1
V1

E7

D2
F6
D3
C1

M4
N5
T2

V3
B2

C3

T22

AB26

VSS

AA25

VSS

AD25

VSS

AE26

VSS

AB23

VSS

AC24

VSS

AF24

VSS

AE23

VSS

AA22

VSS

AD22

VSS

AC21

VSS

AF21

VSS

AB19

VSS

AA19

VSS

AD19

VSS

AC19

VSS

AF19

VSS

AE19

VSS

AB16

VSS

AA16

VSS

AD16

VSS

AC16

VSS

AF16

VSS

AE16

VSS

AB13

VSS

AA14

VSS

AD13

VSS

AC14

VSS

AF13

VSS

AE14

VSS

AB11

VSS

AA11

VSS

AD11

VSS

AC11

VSS

AF11

VSS

AE11

VSS

AB8

VSS

AA8

VSS

AD8

VSS

AC8

VSS

AF8

VSS

AE8

VSS

AA5

VSS

AD5

VSS

AC6

VSS

AF6

VSS

AB4

VSS

AC3

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

AF3
AE4
AB1
AA2
AD2
AE1
B6
C5
F5
E6
H6
J5
M5
L6
P6
R5
V5
U6
Y6
A4
D4
E3
H3
G4
K4
L3
P3
N4
T4
U3
Y3
W4
D1
C2
F2
G1

POWER, GROUNG, RESERVED SIGNALS AND NC

+CPU_CORE

JP2C

AE18

VCC

AE17

VCC

AB15

VCC

AA15

VCC

AD15

VCC

AC15

VCC

AF15

VCC

AE15

VCC

AB14

VCC

AA13

VCC

AD14

VCC

AC13

VCC

AF14

VCC

AE13

VCC

AB12

VCC

AA12

VCC

AD12

VCC

AC12

VCC

AF12

VCC

AE12

VCC

AB10

VCC

AB9

VCC

AA10

VCC

AA9

VCC

AD10

VCC

AD9

VCC

AC10

VCC

AC9

VCC

AF10

VCC

AF9

VCC

AE10

AE9
AB7
AA7
AD7
AC7

D18
D17
C18
C17

D15
C15

D14
C13

D12
C12

D10
C10

B20
A20
F20
E20
B18
B17
A18
A17

F18
F17
E18
E17
B15
A15

F15
E15
B14
A13

F14
E13
B12
A12

F12
E12
B10

A10

F10
E10

POWER, GROUND

VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC

B9

VCC
VCC

A9

VCC
VCC

D9

VCC
VCC

C9

VCC
VCC

F9

VCC
VCC

E9

VCC

B7

VCC

A7

VCC

F7

VCC

FOX_PZ47823-2743-41_YONAH

YONAH

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

K1
J2
M2
N1
T1
R2
V2
W1
A26
D26
C25
F25
B24
A23
D23
E24
B21
C22
F22
E21
B19
A19
D19
C19
F19
E19
B16
A16
D16
C16
F16
E16
B13
A14
D13
C14
F13
E14
B11
A11
D11
C11
F11
E11
B8
A8
D8
C8
F8
E8
G26
K26
J25
M25
N26
T26
R25
V25
W26
H24
G23
K23
L24
P24
N23
T23
U24
Y24
W23
H21
J22
M22
L21
P21
R22
V22
U21
Y21

1 1

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2005/12/1 2006/12/01

C

Compal Secret Data

Deciphered Date

Title

AMD CPU DDRII MEMORY I/F

Size Document Number Rev

Custom

LA-3271P

D

Date: Sheet

542Monday, August 21, 2006

E

0.4

of

5

D D

4

3

2

1

+CPU_CORE

1

proadlizer 1200uF

C C

South Side Secondary

C171

+VCCP

1

+

2

B B

330U_D2E_2.5VM_R9

@

2

+

C167
1200P_PFAF250E128MNTTE_2.5VM

3 4

1

C174

0.1U_0402_16V4Z

2

+CPU_CORE

1

+

C399

2

330U_D2E_2.5VM_R9

7mOhm
PS CAP

1

C175

0.1U_0402_16V4Z

2

C161

@

330U_D2E_2.5VM_R9

7mOhm
PS CAP

1

+

2

C397

@

330U_D2E_2.5VM_R9

7mOhm
PS CAP

1

C173

0.1U_0402_16V4Z

2

1

1

7mOhm
PS CAP

1

2

1

+

C168

2

@

330U_D2E_2.5VM_R9

7mOhm
PS CAP

C150

0.1U_0402_16V4Z

C400

330U_D2E_2.5VM_R9

+

2

7mOhm
PS CAP

C394

@

330U_D2E_2.5VM_R9

1

C152

0.1U_0402_16V4Z

2

+

North Side Secondary

2

1

C151

0.1U_0402_16V4Z

2

1

+

2

Mid Frequence Decoupling

ESR <= 1.5m ohm
Capacitor > 1980uF

Place these inside
socket cavity on L8
(North side
Secondary)

330U ?

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/12/1 2006/12/01

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

Compal Electronics, Inc.

ATHLON64 CTRL & DEBUG

LA-3271P

1

642Monday, August 21, 2006

0.4

of

5

DDR_A_DQS#[0..7]10

DDR_A_D[0..63]10

DDR_A_DM[0..7]10
DDR_A_DQS[0..7]10
DDR_A_MA[0..13]10

D D

Layout Note:
Place near JP41

+1.8V

0.1U_0402_16V4Z

0.1U_0402_16V4Z

C119

1

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

2

2

C103

C106

DDR_CKE0_DIMMA
DDR_A_BS#2

DDR_A_MA11
DDR_A_MA7

DDR_A_MA12
DDR_A_MA9

DDR_A_MA2
DDR_A_MA4

DDR_A_MA0
DDR_A_BS#1

M_ODT0
DDR_A_MA13

DDR_A_MA6
DDR_CKE1_DIMMA

0.1U_0402_16V4Z

C89

1

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

2

C117

1

2

C76

2.2U_0603_6.3V6K

+0.9VS

C105

1

2

0.1U_0402_16V4Z

1

2

C94

2.2U_0603_6.3V6K
C125

1

2

0.1U_0402_16V4Z

1

2

C88

RP26 56_0404_4P2R_5%

14
23

RP21 56_0404_4P2R_5%

14
23

RP22 56_0404_4P2R_5%

14
23

RP17 56_0404_4P2R_5%

14
23

RP13 56_0404_4P2R_5%

14
23

RP4 56_0404_4P2R_5%

14
23

RP25 56_0404_4P2R_5%

14
23

2.2U_0603_6.3V6K

0.1U_0402_16V4Z

1

2

1

2

C62

RP18

RP14

RP9

RP10

RP6

RP2

2.2U_0603_6.3V6K

C77

1

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

2

C75

1 4
2 3

56_0404_4P2R_5%

1 4
2 3

56_0404_4P2R_5%

1 4
2 3

56_0404_4P2R_5%

1 4
2 3

56_0404_4P2R_5%

1 4
2 3

56_0404_4P2R_5%

2 3
1 4

56_0404_4P2R_5%

5

C83

2.2U_0603_6.3V6K
C124

1

2

C C

Layout Note:
Place one cap close to every 2 pullup
resistors terminated to +0.9VS

+0.9VS

0.1U_0402_16V4Z

1

2

C139

B B

DDR_A_MA5
DDR_A_MA8

DDR_A_MA3
DDR_A_MA1

DDR_A_RAS#
DDR_CS0_DIMMA#

DDR_A_MA10
DDR_A_BS#0

DDR_A_WE#
DDR_A_CAS#

A A

DDR_CS1_DIMMA#
M_ODT1

0.1U_0402_16V4Z

C99

1

1

2

2

0.1U_0402_16V4Z

1

1

2

2

C110

C126

Layout Note:
Place these resistor
closely JP41,all
trace length Max=1.5"

4

C93

DDR_CKE0_DIMMA9

DDR_A_BS#210

DDR_A_BS#010

DDR_A_WE#10

DDR_A_CAS#10

C130

DDR_CS1_DIMMA#9

M_ODT19

CLK_SMBDATA8,13

CLK_SMBCLK8,13

+3VS

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

2

2

C122

DDR_A_D4
DDR_A_D1

DDR_A_DQS#0
DDR_A_DQS0

DDR_A_D2
DDR_A_D3

DDR_A_D8
DDR_A_D14

DDR_A_DQS#1
DDR_A_DQS1

DDR_A_D9

DDR_A_D16
DDR_A_D17

DDR_A_DQS#2
DDR_A_DQS2

DDR_A_D18
DDR_A_D19

DDR_A_D29
DDR_A_D24

DDR_A_DM3

DDR_A_D26
DDR_A_D27

DDR_CKE0_DIMMA

DDR_A_BS#2
DDR_A_MA12
DDR_A_MA8
DDR_A_MA5

DDR_A_MA3
DDR_A_MA1

DDR_A_MA10
DDR_A_BS#0

DDR_A_CAS#
DDR_CS1_DIMMA#

M_ODT1
DDR_A_D37

DDR_A_D36
DDR_A_DQS#4

DDR_A_DQS4
DDR_A_D35

DDR_A_D34
DDR_A_D40

DDR_A_D44
DDR_A_DM5
DDR_A_D41

DDR_A_D46
DDR_A_D49

DDR_A_D48

DDR_A_DQS#6
DDR_A_DQS6

DDR_A_D54
DDR_A_D50

DDR_A_D61
DDR_A_D60

DDR_A_DM7
DDR_A_D59

DDR_A_D58
CLK_SMBDATA

CLK_SMBCLK

1

C39

2

3

+1.8V

1

C42

2.2U_0603_6.3V6K

2

JDIM1

1

VREF

3

VSS

5

DQ0

7

DQ1

9

VSS

11

DQS0#

13

DQS0

15

VSS

17

DQ2

19

DQ3

21

VSS

23

DQ8

25

DQ9

27

VSS

29

DQS1#

31

DQS1

33

VSS

35

DQ10

37

DQ11

39

VSS

41

VSS

43

DQ16

45

DQ17

47

VSS

49

DQS2#

51

DQS2

53

VSS

55

DQ18

57

DQ19

59

VSS

61

DQ24

63

DQ25

65

VSS

67

DM3

69

NC

71

VSS

73

DQ26

75

DQ27

77

VSS

79

CKE0

81

VDD

83

NC

85

BA2

87

VDD

89

A12

91

A9

93

A8

95

VDD

97

A5

99

A3

101

A1

103

VDD

105

A10/AP

107

BA0

109

WE#

111

VDD

113

CAS#

115

NC/S1#

117

VDD

119

NC/ODT1

121

VSS

123

DQ32

125

DQ33

127

VSS

129

DQS4#

131

DQS4

133

VSS

135

DQ34

137

DQ35

139

VSS

141

DQ40

143

DQ41

145

VSS

147

DM5

149

VSS

151

DQ42

153

DQ43

155

VSS

157

DQ48

159

DQ49

161

VSS

163

NC,TEST

165

VSS

167

DQS6#

169

DQS6

171

VSS

173

DQ50

175

DQ51

177

VSS

179

DQ56

181

DQ57

183

VSS

185

DM7

187

VSS

189

DQ58

191

DQ59

193

VSS

195

SDA

197

SCL

199

VDDSPD

P-TWO_A5692C-A0G16

SO-DIMM A

REVERSE

DQ12
DQ13

CK0#

DQ14
DQ15

DQ20
DQ21

DQ22
DQ23

DQ28
DQ29

DQS3#

DQS3
DQ30

DQ31

NC/CKE1

NC/A15
NC/A14

RAS#

ODT0

NC/A13

DQ36
DQ37

DQ38
DQ39

DQ44
DQ45

DQS5#

DQS5
DQ46

DQ47
DQ52

DQ53

CK1#

DQ54
DQ55

DQ60
DQ61

DQS7#

DQS7
DQ62

DQ63

VSS
DQ4
DQ5
VSS
DM0
VSS
DQ6
DQ7
VSS

VSS
DM1
VSS
CK0

VSS

VSS

VSS

VSS
DM2

VSS

VSS

VSS

VSS

VSS
VDD

VDD

VDD

VDD
BA1

VDD

VDD
VSS

VSS
DM4
VSS

VSS

VSS

VSS

VSS

VSS
CK1

VSS
DM6
VSS

VSS

VSS

VSS

VSS
SAO
SA1

2

+1.8V

V_DDR_MCH_REF

2

DDR_A_D6

4

DDR_A_D0

6
8

DDR_A_DM0

10
12

DDR_A_D5

14

DDR_A_D7

16
18

DDR_A_D13

20

DDR_A_D12

22
24

DDR_A_DM1

26
28

M_CLK_DDR0

30

M_CLK_DDR#0

32
34

DDR_A_D11

36

DDR_A_D10DDR_A_D15

38
40

42

DDR_A_D20

44

DDR_A_D21

46
48
50

NC

A11

A7
A6

A4
A2
A0

S0#

NC

52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200

DDR_A_DM2
DDR_A_D23

DDR_A_D22
DDR_A_D28

DDR_A_D25
DDR_A_DQS#3

DDR_A_DQS3
DDR_A_D31

DDR_A_D30
DDR_CKE1_DIMMA

DDR_A_MA11
DDR_A_MA7DDR_A_MA9
DDR_A_MA6

DDR_A_MA4
DDR_A_MA2
DDR_A_MA0

DDR_A_BS#1
DDR_A_RAS#
DDR_CS0_DIMMA#DDR_A_WE#

M_ODT0
DDR_A_MA13

DDR_A_D32
DDR_A_D33

DDR_A_DM4
DDR_A_D39

DDR_A_D38
DDR_A_D45

DDR_A_D43
DDR_A_DQS#5

DDR_A_DQS5
DDR_A_D47

DDR_A_D42
DDR_A_D52

DDR_A_D53
M_CLK_DDR1

M_CLK_DDR#1
DDR_A_DM6
DDR_A_D51

DDR_A_D55
DDR_A_D57

DDR_A_D56
DDR_A_DQS#7

DDR_A_DQS7
DDR_A_D62

DDR_A_D63

12

R34

10K_0402_5%

Close to VREF pins of SO-DIMM

2.2U_0805_16V4Z

M_CLK_DDR0 9
M_CLK_DDR#0 9

R89 0_0402_5%

DDR_CKE1_DIMMA 9

DDR_A_BS#1 10
DDR_A_RAS# 10
DDR_CS0_DIMMA# 9

M_ODT0 9

M_CLK_DDR1 9
M_CLK_DDR#1 9

12

R35

10K_0402_5%

0.1U_0402_16V4Z

C159

1

2

C166

1

2

Close to connect

12

PM_EXTTS#0 8,9

1

V_DDR_MCH_REF 8,9

V_DDR_MCH_REF

1

C156

2

@

0.1U_0402_16V4Z

+1.8V

12

R113

100_0402_1%@

12

R114

100_0402_1%@

Top side

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2005/12/1 2006/12/01

3

Compal Secret Data

Deciphered Date

Title

DDR2 SO-DIMM I

Size Document Number Rev

Custom

LA-3271P

2

Date: Sheet

742Monday, August 21, 2006

1

0.4

of

5

DDR_B_DQS#[0..7]10

DDR_B_D[0..63]10

DDR_B_DM[0..7]10
DDR_B_DQS[0..7]10
DDR_B_MA[0..13]10

D D

Layout Note:
Place near JP42

+1.8V

2.2U_0603_6.3V6K

2.2U_0603_6.3V6K

C121

C82

1

1

2

2

C C

Layout Note:
Place one cap close to every 2 pullup
resistors terminated to +0.9VS

+0.9VS

1

2

C107

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

2

C91

RP16

RP11

RP12

RP8

RP7

RP3

0.1U_0402_16V4Z

B B

DDR_B_MA1
DDR_B_MA3

DDR_B_MA10
DDR_B_BS#0

DDR_B_MA0
DDR_B_BS#1

DDR_B_RAS#
DDR_CS2_DIMMB#

DDR_B_CAS#
DDR_B_WE#

A A

DDR_CS3_DIMMB#
M_ODT3

2.2U_0603_6.3V6K
C128

1

2

0.1U_0402_16V4Z

1

2

C95

1 4
2 3

56_0404_4P2R_5%

1 4
2 3

56_0404_4P2R_5%

1 4
2 3

56_0404_4P2R_5%

1 4
2 3

56_0404_4P2R_5%

1 4
2 3

56_0404_4P2R_5%

2 3
1 4

56_0404_4P2R_5%

5

1

2

C80

2.2U_0603_6.3V6K

+0.9VS

C102

1

2

0.1U_0402_16V4Z

1

2

C79

2.2U_0603_6.3V6K
C84

1

2

0.1U_0402_16V4Z

1

2

C68

RP23 56_0404_4P2R_5%

14
23

RP24 56_0404_4P2R_5%

14
23

RP20 56_0404_4P2R_5%

14
23

RP19 56_0404_4P2R_5%

14
23

RP15 56_0404_4P2R_5%

14
23

RP5 56_0404_4P2R_5%

14
23

RP27

14
23

56_0404_4P2R_5%

0.1U_0402_16V4Z
C115

1

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

2

2

C67

DDR_B_MA12
DDR_B_MA9

DDR_CKE3_DIMMB
DDR_B_MA11

DDR_B_MA5
DDR_B_MA8

DDR_B_MA7
DDR_B_MA6

DDR_B_MA4
DDR_B_MA2

DDR_B_MA13
M_ODT2

DDR_CKE2_DIMMB
DDR_B_BS#2

0.1U_0402_16V4Z

C129

0.1U_0402_16V4Z

C100

1

2

0.1U_0402_16V4Z

1

2

C123

0.1U_0402_16V4Z

C90

1

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

2

C127

Layout Note:
Place these resistor
closely JP42,all
trace length Max=1.5"

4

C92

1

2

DDR_CKE2_DIMMB9

DDR_B_BS#210

DDR_B_BS#010

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

2

C108

1

1

2

2

C104

C118

DDR_B_WE#10

DDR_B_CAS#10

DDR_CS3_DIMMB#9

M_ODT39

CLK_SMBDATA7,13

CLK_SMBCLK7,13

0.1U_0402_16V4Z

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

+1.8V

JDIM2

1

VREF

3

DDR_B_D0
DDR_B_D1

DDR_B_DQS#0
DDR_B_DQS0

DDR_B_D2
DDR_B_D3

DDR_B_D8
DDR_B_D9

DDR_B_DQS#1
DDR_B_DQS1

DDR_B_D10
DDR_B_D11

DDR_B_D17
DDR_B_D20

DDR_B_DQS#2
DDR_B_DQS2

DDR_B_D18
DDR_B_D19

DDR_B_D28
DDR_B_D25

DDR_B_DM3

DDR_B_D30
DDR_B_D31

DDR_CKE2_DIMMB

DDR_B_BS#2
DDR_B_MA12

DDR_B_MA9
DDR_B_MA8

DDR_B_MA5
DDR_B_MA3
DDR_B_MA1

DDR_B_MA10
DDR_B_BS#0
DDR_B_WE#

DDR_B_CAS#
DDR_CS3_DIMMB#

M_ODT3
DDR_B_D32

DDR_B_D33
DDR_B_DQS#4

DDR_B_DQS4
DDR_B_D34

DDR_B_D35
DDR_B_D40

DDR_B_D41
DDR_B_DM5
DDR_B_D42

DDR_B_D43
DDR_B_D48

DDR_B_D49

DDR_B_DQS#6
DDR_B_DQS6

DDR_B_D51
DDR_B_D50

DDR_B_D56
DDR_B_D61 DDR_B_D57

DDR_B_DM7
DDR_B_D59

DDR_B_D58
CLK_SMBDATA

CLK_SMBCLK

+3VS

1

2

1

C43

2.2U_0603_6.3V6K

2

C38

2005/12/1 2006/12/01

3

VSS

5

DQ0

7

DQ1

9

VSS

11

DQS0#

13

DQS0

15

VSS

17

DQ2

19

DQ3

21

VSS

23

DQ8

25

DQ9

27

VSS

29

DQS1#

31

DQS1

33

VSS

35

DQ10

37

DQ11

39

VSS

41

VSS

43

DQ16

45

DQ17

47

VSS

49

DQS2#

51

DQS2

53

VSS

55

DQ18

57

DQ19

59

VSS

61

DQ24

63

DQ25

65

VSS

67

DM3

69

NC

71

VSS

73

DQ26

75

DQ27

77

VSS

79

CKE0

81

VDD

83

NC

85

BA2

87

VDD

89

A12

91

A9

93

A8

95

VDD

97

A5

99

A3

101

A1

103

VDD

105

A10/AP

107

BA0

109

WE#

111

VDD

113

CAS#

115

NC/S1#

117

VDD

119

NC/ODT1

121

VSS

123

DQ32

125

DQ33

127

VSS

129

DQS4#

131

DQS4

133

VSS

135

DQ34

137

DQ35

139

VSS

141

DQ40

143

DQ41

145

VSS

147

DM5

149

VSS

151

DQ42

153

DQ43

155

VSS

157

DQ48

159

DQ49

161

VSS

163

NC,TEST

165

VSS

167

DQS6#

169

DQS6

171

VSS

173

DQ50

175

DQ51

177

VSS

179

DQ56

181

DQ57

183

VSS

185

DM7

187

VSS

189

DQ58

191

DQ59

193

VSS

195

SDA

197

SCL

199

VDDSPD

P-TWO_A5652C-A0G16

SO-DIMM B

CONN@

STANDARD

Bottom side

Compal Secret Data

Deciphered Date

DQ12
DQ13

CK0#

DQ14
DQ15

DQ20
DQ21

DQ22
DQ23

DQ28
DQ29

DQS3#

DQS3
DQ30

DQ31

NC/CKE1

NC/A15
NC/A14

RAS#

ODT0

NC/A13

DQ36
DQ37

DQ38
DQ39

DQ44
DQ45

DQS5#

DQS5
DQ46

DQ47
DQ52

DQ53

CK1#

DQ54
DQ55

DQ60
DQ61

DQS7#

DQS7
DQ62

DQ63

VSS
DQ4
DQ5
VSS
DM0
VSS
DQ6
DQ7
VSS

VSS
DM1
VSS
CK0

VSS

VSS

VSS

VSS
DM2

VSS

VSS

VSS

VSS

VSS
VDD

VDD

VDD

VDD
BA1

VDD

VDD
VSS

VSS
DM4
VSS

VSS

VSS

VSS

VSS

VSS
CK1

VSS
DM6
VSS

VSS

VSS

VSS

VSS
SAO
SA1

NC

A11

A7
A6

A4
A2
A0

S0#

NC

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200

2

+1.8V

V_DDR_MCH_REF

DDR_B_D5
DDR_B_D4

DDR_B_DM0
DDR_B_D6

DDR_B_D7
DDR_B_D12

DDR_B_D13
DDR_B_DM1
M_CLK_DDR3

M_CLK_DDR#3
DDR_B_D14

DDR_B_D15

DDR_B_D21
DDR_B_D16

DDR_B_DM2
DDR_B_D22

DDR_B_D23
DDR_B_D26

DDR_B_D24
DDR_B_DQS#3

DDR_B_DQS3
DDR_B_D29

DDR_B_D27
DDR_CKE3_DIMMB

DDR_B_MA11
DDR_B_MA7
DDR_B_MA6

DDR_B_MA4
DDR_B_MA2
DDR_B_MA0

DDR_B_BS#1
DDR_B_RAS#
DDR_CS2_DIMMB#

M_ODT2
DDR_B_MA13

DDR_B_D36
DDR_B_D37

DDR_B_DM4
DDR_B_D39

DDR_B_D38
DDR_B_D44

DDR_B_D45
DDR_B_DQS#5

DDR_B_DQS5
DDR_B_D46

DDR_B_D47
DDR_B_D52

DDR_B_D53
M_CLK_DDR2

M_CLK_DDR#2
DDR_B_DM6
DDR_B_D54

DDR_B_D55
DDR_B_D60

DDR_B_DQS#7
DDR_B_DQS7

DDR_B_D62
DDR_B_D63

2

1

Close to VREF pins of SO-DIMM

2.2U_0805_16V4Z

0.1U_0402_16V4Z

1

1

C149

C155

2

2

M_CLK_DDR3 9
M_CLK_DDR#3 9

12

R90 0_0402_5%

DDR_CKE3_DIMMB 9

DDR_B_BS#1 10
DDR_B_RAS# 10
DDR_CS2_DIMMB# 9

M_ODT2 9

M_CLK_DDR2 9
M_CLK_DDR#2 9

R31

1 2

10K_0402_5%

12

10K_0402_5%

R32

Title

DDR2 SO-DIMM II

Size Document Number Rev

Custom

LA-3271P

Date: Sheet

PM_EXTTS#0 7,9

+3VS

V_DDR_MCH_REF 7,9

1

0.4

of

842Monday, August 21, 2006

5

H_D#[0..63]4

D D

C C

+VCCP

12

12

R335

54.9_0402_1%

+VCCP

R51

R53

12

R336

24.9_0402_1%

12

100_0402_1%

12

200_0402_1%

R38

54.9_0402_1%

B B

A A

H_D#0
H_D#1
H_D#2
H_D#3
H_D#4 CFG3
H_D#5 CFG4
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63

H_VREF
H_XRCOMP
H_XSCOMP
H_YRCOMP
H_YSCOMP
H_SWNG0
H_SWNG1

12

R41

24.9_0402_1%

Layout Note:
H_XRCOMP / H_YRCOMP / H_VREF / H_SWNG0 /
H_SWNG1 trace width and spacing is 10/20.

H_VREF

1

C57

2

0.1U_0402_16V4Z

5

K11
T10

W11

U11
T11

AB7
AA9

Y10
AB8

AA4
AA7
AA2
AA6

AA10

AA1
AB4

AC9
AB11
AC11

AB3

AC2

AD1

AD9

AC1

AD7

AC6

AB5
AD10

AD4

AC8

J13

K13

U23A

F1

HD0#

J1

HD1#

H1

HD2#

J6

HD3#

H3

HD4#

K2

HD5#

G1

HD6#

G2

HD7#

K9

HD8#

K1

HD9#

K7

HD10#

J8

HD11#

H4

HD12#

J3

HD13#
HD14#

G4

HD15#
HD16#
HD17#

T3

HD18#

U7

HD19#

U9

HD20#
HD21#
HD22#

W9

HD23#

T1

HD24#

T8

HD25#

T4

HD26#

W7

HD27#

U5

HD28#

T9

HD29#

W6

HD30#

T5

HD31#
HD32#
HD33#

W4

HD34#

W3

HD35#

Y3

HD36#

Y7

HD37#

W5

HD38#
HD39#
HD40#

W2

HD41#
HD42#
HD43#
HD44#
HD45#
HD46#

Y8

HD47#
HD48#
HD49#
HD50#
HD51#
HD52#
HD53#
HD54#
HD55#
HD56#
HD57#
HD58#
HD59#
HD60#
HD61#
HD62#
HD63#

HVREF0
HVREF1

E1

HXRCOMP

E2

HXSCOMP

Y1

HYRCOMP

U1

HYSCOMP

E4

HXSWING

W1

HYSWING

CALISTOGA_FCBGA1466~D

<BOM Structure>

H9

HA3#

C9

HA4#

E11

HA5#

G11

HA6#

F11

HA7#

G12

HA8#

F9

HA9#

H11

HA10#

J12

HA11#

G14

HA12#

D9

HA13#

J14

HA14#

H13

HA15#

J15

HA16#

F14

HA17#

D12

HA18#

A11

HA19#

C11

HA20#

A12

HA21#

A13

HA22#

E13

HA23#

G13

HA24#

F12

HA25#

B12

HA26#

B14

HA27#

C12

HA28#

A14

HA29#

C14

HA30#

D14

HA31#

D8

HREQ#0

G8

HREQ#1

B8

HREQ#2

F8

HREQ#3

A8

HREQ#4

B9

HADSTB#0

C13

HADSTB#1

HCLKN
HCLKP

HDSTBN#0
HDSTBN#1
HDSTBN#2
HDSTBN#3
HDSTBP#0
HDSTBP#1
HDSTBP#2
HDSTBP#3

HDINV#0
HDINV#1
HDINV#2
HDINV#3

HCPURST#

HADS#

HTRDY#

HDPWR#

HDRDY#

HDEFER#

HHITM#

HHIT#

HLOCK#

HBREQ0#

HBNR#

HBPRI#

HDBSY#

HCPUSLP#

HRS0#
HRS1#
HRS2#

12

R43

12

R45

AG1
AG2

K4
T7
Y5
AC4
K3
T6
AA5
AC5

J7
W8
U3
AB10

B7
E8
E7
J9
H8
C3
D4
D3
B3
C7
C6
F6
A7
E3

B4
E6
D6

221_0603_1%

100_0402_1%

HOST

4

+VCCP+VCCP

R33

R42

H_A#[3..31] 4

H_REQ#[0..4] 4

H_ADSTB#0 4
H_ADSTB#1 4

CLK_MCH_BCLK# 13
CLK_MCH_BCLK 13
H_DSTBN#[0..3] 4

H_DSTBP#[0..3] 4

H_DINV#0 4
H_DINV#1 4
H_DINV#2 4
H_DINV#3 4

H_RESET# 4
H_ADS# 4
H_TRDY# 4
H_DPWR# 4
H_DRDY# 4
H_DEFER# 4
H_HITM# 4
H_HIT# 4
H_LOCK# 4
H_BR0# 4
H_BNR# 4
H_BPRI# 4
H_DBSY# 4
H_CPUSLP# 4,16

H_RS#[0..2] 4

12

221_0603_1%

12

100_0402_1%

H_SWNG1

1

2

+1.8V

R47 80.6_0402_1%
R46 80.6_0402_1%

PLT_RST#15,17,22,23,26

V_DDR_MCH_REF7,8

C44

0.1U_0402_16V4Z

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4 DDR_CKE1_DIMMA

H_ADSTB#0
H_ADSTB#1

CLK_MCH_BCLK#
CLK_MCH_BCLK

H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3
H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3

H_DINV#0
H_DINV#1
H_DINV#2
H_DINV#3

H_RESET#
H_ADS#
H_TRDY#
H_DPWR#
H_DRDY#
H_DEFER#
H_HITM#
H_HIT#
H_LOCK#
H_BR0#
H_BNR#
H_BPRI#
H_DBSY#
H_CPUSLP#

H_RS#0
H_RS#1
H_RS#2

H_SWNG0

1

C52

2

0.1U_0402_16V4Z

3

1

2

DMI_TXN0
DMI_TXN1
DMI_TXN2
DMI_TXN3

DMI_TXP0
DMI_TXP1
DMI_TXP2
DMI_TXP3

DMI_RXN0
DMI_RXN1
DMI_RXN2
DMI_RXN3

DMI_RXP0
DMI_RXP1
DMI_RXP2
DMI_RXP3

M_CLK_DDR1
M_CLK_DDR2
M_CLK_DDR3

M_CLK_DDR#0
M_CLK_DDR#1
M_CLK_DDR#2

M_CLK_DDR#3
DDR_CKE0_DIMMA
DDR_CKE2_DIMMB

DDR_CKE3_DIMMB

DDR_CS0_DIMMA#
DDR_CS1_DIMMA#
DDR_CS2_DIMMB#
DDR_CS3_DIMMB#

M_OCDOCMP0

M_OCDOCMP1

M_ODT0

M_ODT1

M_ODT2

M_ODT3

SMRCOMPN

SMRCOMPP

PM_BMBUSY#
PM_EXTTS#0
PM_EXTTS#1
H_THERMTRIP#
NB_PWRGD
PLTRST_R#

12

+1.8V

DMI_TXN017
DMI_TXN117
DMI_TXN217
DMI_TXN317

DMI_TXP017
DMI_TXP117
DMI_TXP217
DMI_TXP317

DMI_RXN017
DMI_RXN117
DMI_RXN217
DMI_RXN317

DMI_RXP017
DMI_RXP117
DMI_RXP217
DMI_RXP317

M_CLK_DDR07
M_CLK_DDR17
M_CLK_DDR28
M_CLK_DDR38

M_CLK_DDR#07
M_CLK_DDR#17
M_CLK_DDR#28
M_CLK_DDR#38

DDR_CKE0_DIMMA7
DDR_CKE1_DIMMA7
DDR_CKE2_DIMMB8
DDR_CKE3_DIMMB8

DDR_CS0_DIMMA#7
DDR_CS1_DIMMA#7
DDR_CS2_DIMMB#8
DDR_CS3_DIMMB#8

M_ODT07
M_ODT17
M_ODT28
M_ODT38

1 2
1 2

V_DDR_MCH_REF

PM_BMBUSY#17
PM_EXTTS#07,8
PM_EXTTS#1

H_THERMTRIP#4,16

NB_PWRGD15

R76 100_0402_1%

MCH_ICH_SYNC#15

Layout Note:
V_DDR_MCH_REF
trace width and
spacing is 20/20.

V_DDR_MCH_REF

C47

0.1U_0402_16V4Z

Stuff R286 & R281 for A1 Calistoga

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

U23B

AE35

DMIRXN0

AF39

DMIRXN1

AG35

DMIRXN2

AH39

DMIRXN3

AC35

DMIRXP0

AE39

DMIRXP1

AF35
AG39

AE37
AF41
AG37
AH41

AC37
AE41
AF37
AG41

AY35

AR1

AW7

AW40
AW35

AT1
AY7

AY40
AU20

AT20
BA29
AY29

AW13
AW12

AY21

AW21

AL20

AF10
BA13

BA12
AY20
AU21

AV9
AT9

AK1

AK41

G28

F25

H26

G6
AH33
AH34

K28

12

R40
100_0402_1%

12

R44
100_0402_1%

2005/12/1 2006/12/01

DMI

DMIRXP2
DMIRXP3

DMITXN0
DMITXN1
DMITXN2
DMITXN3

DMITXP0
DMITXP1
DMITXP2
DMITXP3

SM_CK0
SM_CK1
SM_CK2
SM_CK3

SM_CK0#
SM_CK1#
SM_CK2#
SM_CK3#

SM_CKE0
SM_CKE1
SM_CKE2
SM_CKE3

SM_CS0#
SM_CS1#
SM_CS2#
SM_CS3#

SM_OCDCOMP0
SM_OCDCOMP1

SM_ODT0
SM_ODT1
SM_ODT2
SM_ODT3

SM_RCOMPN
SM_RCOMPP

SM_VREF0
SM_VREF1

PM_BMBUSY#
PM_EXTTS0#
PM_EXTTS1#
PM_THERMTRIP#
PWROK
RSTIN#

ICH_SYNC#

CALISTOGA_FCBGA1466~D

<BOM Structure>

DDR MUXING

Layout Note:
Route as short
as possible

12

R59

40.2_0402_1%

@

Compal Secret Data

Deciphered Date

PM

R50

@

CFG

CLKNC

D_REF_SSCLKN
D_REF_SSCLKP

RESERVED

M_OCDOCMP0
M_OCDOCMP1

12

40.2_0402_1%

2

D_REF_CLKN
D_REF_CLKP

CLK_REQ#

RESERVED1
RESERVED2
RESERVED3
RESERVED4
RESERVED5
RESERVED6
RESERVED7
RESERVED8

RESERVED9
RESERVED10
RESERVED11
RESERVED12
RESERVED13

CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8

CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG16
CFG17
CFG18
CFG19
CFG20

G_CLKP
G_CLKN

NC0
NC1
NC2
NC3
NC4
NC5
NC6
NC7
NC8

NC9
NC10
NC11
NC12
NC13
NC14
NC15
NC16
NC17
NC18

R65

@

0_0402_5%

1 2

Description at page13.

MCH_CLKSEL0

K16

MCH_CLKSEL1

K18

MCH_CLKSEL2

J18
F18
E15

CFG5

F15

CFG6

E18

CFG7

D19

CFG8

D16

CFG9

G16

CFG10

E16

CFG11

D15

CFG12

G15

CFG13

K15

CFG14

C15

CFG15

H16

CFG16

G18

CFG17

H15

CFG18

J25

CFG19

K27

CFG20

J26

CLK_MCH_3GPLL

AG33

CLK_MCH_3GPLL#M_CLK_DDR0

AF33

CLK_MCH_DREFCLK#

A27

CLK_MCH_DREFCLK

A26

MCH_SSCDREFCLK#

C40

MCH_SSCDREFCLK

D41

CLKREQA#

H32

A3
A39
A4
A40
AW1
AW41
AY1
BA1
BA2
BA3
BA39
BA40
BA41
C1
AY41
B2
B41
C41
D1

T32
R32
F3
F7
AG11
AF11
H7
J19
A41
A34
D28
D27
A35

PM_EXTTS#0

PM_EXTTS#1

DPRSLPVR 17,37

Title

Size Document Number Rev

Custom

Date: Sheet

PAD
PAD
PAD
PAD

PAD
PAD

R67

10K_0402_5%

R66

@

10K_0402_5%

MCH_CLKSEL0 13
MCH_CLKSEL1 13
MCH_CLKSEL2 13
CFG3 12

T2

CFG5 12

T1

CFG7 12

T4

CFG9 12

T3

CFG11 12
CFG12 12

CFG13 12

T5
T7

CFG16 12

CFG17 12

CFG18 12

CFG19 12

CFG20 12

12

12

CLK_MCH_3GPLL 13
CLK_MCH_3GPLL# 13

CLK_MCH_DREFCLK# 13
CLK_MCH_DREFCLK 13

MCH_SSCDREFCLK# 13
MCH_SSCDREFCLK 13

CLKREQA# 13

+3VS

Calistoga(1)
LA-3271P

1

0.4

of

1

942Monday, August 21, 2006

DDR_A_BS#07
DDR_A_BS#17
DDR_A_BS#27

DDR_A_DM[0..7]7

DDR_A_DQS[0..7]7

DDR_A_DQS#[0..7]7

DDR_A_MA[0..13]7

DDR_A_CAS#7
DDR_A_RAS#7

DDR_A_WE#7

T9 PAD
T10 PAD

DDR_A_BS#0
DDR_A_BS#1
DDR_A_BS#2

DDR_A_DM0
DDR_A_DM1
DDR_A_DM2
DDR_A_DM3
DDR_A_DM4
DDR_A_DM5
DDR_A_DM6
DDR_A_DM7

DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7

DDR_A_DQS#0
DDR_A_DQS#1
DDR_A_DQS#2
DDR_A_DQS#3
DDR_A_DQS#4
DDR_A_DQS#5
DDR_A_DQS#6
DDR_A_DQS#7

DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13

DDR_A_CAS#
DDR_A_RAS#
DDR_A_WE#
SA_RCVENIN# SB_RCVENIN#
SA_RCVENOUT#

check layout check layout

U23D

AU12

SA_BS0

AV14

SA_BS1

BA20

SA_BS2

AJ33

SA_DM0

AM35

SA_DM1

AL26

SA_DM2

AN22

SA_DM3

AM14

SA_DM4

AL9

SA_DM5

AR3

SA_DM6

AH4

SA_DM7

AK33

SA_DQS0

AT33

SA_DQS1

AN28

SA_DQS2

AM22

SA_DQS3

AN12

SA_DQS4

AN8

SA_DQS5

AP3

SA_DQS6

AG5

SA_DQS7

AK32

SA_DQS0#

AU33

SA_DQS1#

AN27

SA_DQS2#

AM21

SA_DQS3#

AM12

SA_DQS4#

AL8

SA_DQS5#

AN3

SA_DQS6#

AH5

SA_DQS7#

AY16

SA_MA0

AU14

SA_MA1

AW16

SA_MA2

BA16

SA_MA3

BA17

SA_MA4

AU16

SA_MA5

AV17

SA_MA6

AU17

SA_MA7

AW17

SA_MA8

AT16

SA_MA9

AU13

SA_MA10

AT17

SA_MA11

AV20

SA_MA12

AV12

SA_MA13

AY13

SA_CAS#

AW14

SA_RAS#

AY14

SA_WE#

AK23

SA_RCVENIN#

AK24

SA_RCVENOUT#

CALISTOGA_FCBGA1466~D

<BOM Structure>

SA_DQ0
SA_DQ1
SA_DQ2
SA_DQ3
SA_DQ4
SA_DQ5
SA_DQ6
SA_DQ7
SA_DQ8

SA_DQ9
SA_DQ10
SA_DQ11
SA_DQ12
SA_DQ13
SA_DQ14
SA_DQ15
SA_DQ16
SA_DQ17
SA_DQ18
SA_DQ19
SA_DQ20
SA_DQ21
SA_DQ22
SA_DQ23
SA_DQ24
SA_DQ25
SA_DQ26
SA_DQ27
SA_DQ28
SA_DQ29
SA_DQ30
SA_DQ31
SA_DQ32
SA_DQ33
SA_DQ34
SA_DQ35
SA_DQ36
SA_DQ37
SA_DQ38
SA_DQ39

DDR SYS MEMORY A

SA_DQ40
SA_DQ41
SA_DQ42
SA_DQ43
SA_DQ44
SA_DQ45
SA_DQ46
SA_DQ47
SA_DQ48
SA_DQ49
SA_DQ50
SA_DQ51
SA_DQ52
SA_DQ53
SA_DQ54
SA_DQ55
SA_DQ56
SA_DQ57
SA_DQ58
SA_DQ59
SA_DQ60
SA_DQ61
SA_DQ62
SA_DQ63

AJ34
AM31
AM33
AJ36
AK35
AJ32
AH31
AN35
AP33
AR31
AP31
AN38
AM36
AM34
AN33
AK26
AL27
AM26
AN24
AK28
AL28
AM24
AP26
AP23
AL22
AP21
AN20
AL23
AP24
AP20
AT21
AR12
AR14
AP13
AP12
AT13
AT12
AL14
AL12
AK9
AN7
AK8
AK7
AP9
AN9
AT5
AL5
AY2
AW2
AP1
AN2
AV2
AT3
AN1
AL2
AG7
AF9
AG4
AF6
AG9
AH6
AF4
AF8

DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63

DDR_A_D0

AJ35

DDR_A_D[0..63] 7 DDR_B_D[0..63] 8

DDR_B_BS#08
DDR_B_BS#18
DDR_B_BS#28

DDR_B_DM[0..7]8

DDR_B_DQS[0..7]8

DDR_B_DQS#[0..7]8

DDR_B_MA[0..13]8

DDR_B_CAS#8
DDR_B_RAS#8

DDR_B_WE#8

T6 PAD
T8 PAD

DDR_B_BS#0
DDR_B_BS#1
DDR_B_BS#2

DDR_B_DM0
DDR_B_DM1
DDR_B_DM2
DDR_B_DM3
DDR_B_DM4
DDR_B_DM5
DDR_B_DM6
DDR_B_DM7

DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4
DDR_B_DQS5
DDR_B_DQS6
DDR_B_DQS7

DDR_B_DQS#0
DDR_B_DQS#1
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS#4
DDR_B_DQS#5
DDR_B_DQS#6
DDR_B_DQS#7

DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13

DDR_B_CAS#
DDR_B_RAS#
DDR_B_WE#

SB_RCVENOUT#

U23E

AT24

SB_BS0

AV23

SB_BS1

AY28

SB_BS2

AK36

SB_DM0

AR38

SB_DM1

AT36

SB_DM2

BA31

SB_DM3

AL17

SB_DM4

AH8

SB_DM5

BA5

SB_DM6

AN4

SB_DM7

AM39

SB_DQS0

AT39

SB_DQS1

AU35

SB_DQS2

AR29

SB_DQS3

AR16

SB_DQS4

AR10

SB_DQS5

AR7

SB_DQS6

AN5

SB_DQS7

AM40

SB_DQS0#

AU39

SB_DQS1#

AT35

SB_DQS2#

AP29

SB_DQS3#

AP16

SB_DQS4#

AT10

SB_DQS5#

AT7

SB_DQS6#

AP5

SB_DQS7#

AY23

SB_MA0

AW24

SB_MA1

AY24

SB_MA2

AR28

SB_MA3

AT27

SB_MA4

AT28

SB_MA5

AU27

SB_MA6

AV28

SB_MA7

AV27

SB_MA8

AW27

SB_MA9

AV24

SB_MA10

BA27

SB_MA11

AY27

SB_MA12

AR23

SB_MA13

AR24

SB_CAS#

AU23

SB_RAS#

AR27

SB_WE#

AK16

SB_RCVENIN#

AK18

SB_RCVENOUT#

CALISTOGA_FCBGA1466~D

<BOM Structure>

SB_DQ0
SB_DQ1
SB_DQ2
SB_DQ3
SB_DQ4
SB_DQ5
SB_DQ6
SB_DQ7
SB_DQ8

SB_DQ9
SB_DQ10
SB_DQ11
SB_DQ12
SB_DQ13
SB_DQ14
SB_DQ15
SB_DQ16
SB_DQ17
SB_DQ18
SB_DQ19
SB_DQ20
SB_DQ21
SB_DQ22
SB_DQ23
SB_DQ24
SB_DQ25
SB_DQ26
SB_DQ27
SB_DQ28
SB_DQ29
SB_DQ30
SB_DQ31
SB_DQ32
SB_DQ33
SB_DQ34
SB_DQ35
SB_DQ36
SB_DQ37
SB_DQ38
SB_DQ39

DDR SYS MEMORY B

SB_DQ40
SB_DQ41
SB_DQ42
SB_DQ43
SB_DQ44
SB_DQ45
SB_DQ46
SB_DQ47
SB_DQ48
SB_DQ49
SB_DQ50
SB_DQ51
SB_DQ52
SB_DQ53
SB_DQ54
SB_DQ55
SB_DQ56
SB_DQ57
SB_DQ58
SB_DQ59
SB_DQ60
SB_DQ61
SB_DQ62
SB_DQ63

AJ37
AP39
AR41
AJ38
AK38
AN41
AP41
AT40
AV41
AU38
AV38
AP38
AR40
AW38
AY38
BA38
AV36
AR36
AP36
BA36
AU36
AP35
AP34
AY33
BA33
AT31
AU29
AU31
AW31
AV29
AW29
AM19
AL19
AP14
AN14
AN17
AM16
AP15
AL15
AJ11
AH10
AJ9
AN10
AK13
AH11
AK10
AJ8
BA10
AW10
BA4
AW4
AY10
AY9
AW5
AY5
AV4
AR5
AK4
AK3
AT4
AK5
AJ5
AJ3

DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63

DDR_B_D0

AK39

DDR Thermal Sensor

EC_SMB_DA24,26
EC_SMB_CK24,26

SMB_EC_DA2
SMB_EC_CK2

+5VS

1

C391

0.1U_0402_16V4Z@

U26

1

SDA

2

SCL

3

OS#

4

GND

LM75CIMMX-5_MSOP8@

VCC

8
7

A0

6

A1

5

A2

2

1 2

R355 1K_0402_5%@

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2005/12/1 2006/12/01

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

Date: Sheet

Calistoga(2)
LA-3271P

of

10 42Monday, August 21, 2006

0.4

5

U23C

H27

SDVOCTRL_DATA

H28

SDVOCTRL_CLK

1 2

0_0603_5%

1 2

150_0402_1%

LCTLA_CLK

LCTLB_DATA

LVDSA0+
LVDSA1+
LVDSA2+

LVDSA0­LVDSA1­LVDSA2-

LVDSB0+
LVDSB1+
LVDSB2+

LVDSB0­LVDSB1­LVDSB2-

LVDSAC+
LVDSAC­LVDSBC+
LVDSBC-

GMCH_ENBKL

EDID_CLK_LCD
EDID_DAT_LCD

GMCH_LVDDEN

R71 1.5K_0402_1%

R339

R64

255_0402_1%

LCTLA_CLK
LCTLB_DATA

3VDDCCL
3VDDCDA

CRT_VSYNC
CRT_HSYNC
CRT_B

CRT_G
CRT_R

LVDSA0+14
LVDSA1+14
LVDSA2+14

LVDSA0-14
LVDSA1-14

LVDSA2-14

LVDSBC+14
LVDSBC-14

BIA_PWM14

GMCH_ENBKL14,26

EDID_CLK_LCD14
EDID_DAT_LCD14

GMCH_LVDDEN14

+1.5VS

CRT_VSYNC14
CRT_HSYNC14

R56

R62

1 2

1 2

150_0402_1%

1 2

R86 10K_0402_5% @

1 2

R85 10K_0402_5%@

1 2

R69 100K_0402_1%

1 2

R346 100K_0402_5%

LVDSB0+14
LVDSB1+14
LVDSB2+14

LVDSB0-14
LVDSB1-14
LVDSB2-14

LVDSAC+14
LVDSAC-14

3VDDCCL14
3VDDCDA14

R60

150_0402_1%

D D

C C

CRT_B14
CRT_G14
CRT_R14

+3VS

B B

GMCH_ENBKL

GMCH_LVDDEN

A A

BIA_PWM

12

12

B37

LA_DATA0

B34

LA_DATA1

A36

LA_DATA2

C37

LA_DATA#0

B35

LA_DATA#1

A37

LA_DATA#2

F30

LB_DATA0

D29

LB_DATA1

F28

LB_DATA2

G30

LB_DATA#0

D30

LB_DATA#1

F29

LB_DATA#2

A32

LA_CLK

A33

LA_CLK#

E26

LB_CLK

E27

LB_CLK#

D32

LBKLT_CTL

J30

LBKLT_EN

H30

LCTLA_CLK

H29

LCTLB_DATA

G26

LDDC_CLK

G25

LDDC_DATA

F32

LVDD_EN

B38

LIBG

C35

LVBG

C33

LVREFH

C32

LVREFL

A16

TVDAC_A

C18

TVDAC_B

A19

TVDAC_C

J20

TV_IREF

B16

TV_IRTNA

B18

TV_IRTNB

B19

TV_IRTNC

J29

TV_DCONSEL1

K30

TV_DCONSEL0

C26

DDCCLK

C25

DDCDATA

H23

VSYNC

G23

HSYNC

E23

BLUE

D23

BLUE#

C22

GREEN

B22

GREEN#

A21

RED

B21

RED#

J22

CRT_IREF

CALISTOGA_FCBGA1466~D

LVDS

TV CRT

4

D40

EXP_COMPI

D38

EXP_COMPO

F34

EXP_RXN0

G38

EXP_RXN1

H34

EXP_RXN2

J38

EXP_RXN3

L34

EXP_RXN4

M38

EXP_RXN5

N34

EXP_RXN6

P38

EXP_RXN7

R34

EXP_RXN8

T38

EXP_RXN9

V34

EXP_RXN10

W38

EXP_RXN11

Y34

EXP_RXN12

AA38

EXP_RXN13

AB34

EXP_RXN14

AC38

EXP_RXN15

D34

EXP_RXP0

F38

EXP_RXP1

G34

EXP_RXP2

H38

EXP_RXP3

J34

EXP_RXP4

L38

EXP_RXP5

M34

EXP_RXP6

N38

EXP_RXP7

P34

EXP_RXP8

R38

EXP_RXP9

T34

EXP_RXP10

V38

EXP_RXP11

W34

EXP_RXP12

Y38

EXP_RXP13

AA34

EXP_RXP14

AB38

EXP_RXP15

F36

EXP_TXN0

G40

EXP_TXN1

H36

EXP_TXN2

J40

EXP_TXN3

L36

EXP_TXN4

M40

EXP_TXN5

N36

EXP_TXN6

P40

EXP_TXN7

R36

EXP_TXN8

PCI-EXPRESS GRAPHICS

EXP_TXN9
EXP_TXN10
EXP_TXN11
EXP_TXN12
EXP_TXN13
EXP_TXN14
EXP_TXN15

EXP_TXP0

EXP_TXP1

EXP_TXP2

EXP_TXP3

EXP_TXP4

EXP_TXP5

EXP_TXP6

EXP_TXP7

EXP_TXP8

EXP_TXP9
EXP_TXP10
EXP_TXP11
EXP_TXP12
EXP_TXP13
EXP_TXP14
EXP_TXP15

T40
V36
W40
Y36
AA40
AB36
AC40

D36
F40
G36
H40
J36
L40
M36
N40
P36
R40
T36
V40
W36
Y40
AA36
AB40

PEGCOMP

1 2

+1.5VS_PCIE

R74

24.9_0402_1%

U23I

AC41
AA41

W41

T41
P41

M41

J41

F41
AV40
AP40
AN40
AK40

AJ40

AH40

AG40

AF40
AE40

B40

AY39

AW39

AV39
AR39
AN39

AJ39
AC39
AB39
AA39

Y39

W39

V39
T39
R39
P39
N39

M39

L39

J39
H39
G39

F39
D39

AT38

AM38

AH38

AG38

AF38
AE38

C38

AK37
AH37
AB37
AA37

Y37

W37

V37
T37
R37
P37
N37

M37

L37

J37
H37
G37

F37
D37

AY36

AW36

AN36
AH36

AG36

AF36
AE36
AC36

C36
B36

BA35
AV35
AR35
AH35
AB35
AA35

Y35

W35

V35
T35
R35
P35
N35

M35

L35

J35
H35
G35

F35
D35

AN34
AK34

AG34

AF34

CALISTOGA_FCBGA1466~D

<BOM Structure>

VSS0
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65
VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77
VSS78
VSS79
VSS80
VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS97
VSS98
VSS99

P O W E R

VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS140
VSS141
VSS142
VSS143
VSS144
VSS145
VSS146
VSS147
VSS148
VSS149
VSS150
VSS151
VSS152
VSS153
VSS154
VSS155
VSS156
VSS157
VSS158
VSS159
VSS160
VSS161
VSS162
VSS163
VSS164
VSS165
VSS166
VSS167
VSS168
VSS169
VSS170
VSS171
VSS172
VSS173
VSS174
VSS175
VSS176
VSS177
VSS178
VSS179
VSS180
VSS181
VSS182
VSS183
VSS184
VSS185
VSS186
VSS187
VSS188
VSS189
VSS190
VSS191
VSS192
VSS193
VSS194
VSS195
VSS196
VSS197
VSS198
VSS199

AE34
AC34
C34
AW33
AV33
AR33
AE33
AB33
Y33
V33
T33
R33
M33
H33
G33
F33
D33
B33
AH32
AG32
AF32
AE32
AC32
AB32
G32
B32
AY31
AV31
AN31
AJ31
AG31
AB31
Y31
AB30
E30
AT29
AN29
AB29
T29
N29
K29
G29
E29
C29
B29
A29
BA28
AW28
AU28
AP28
AM28
AD28
AC28
W28
J28
E28
AP27
AM27
AK27
J27
G27
F27
C27
B27
AN26
M26
K26
F26
D26
AK25
P25
K25
H25
E25
D25
A25
BA24
AU24
AL24
AW23
AT23
AN23
AM23
AH23
AC23
W23
K23
J23
F23
C23
AA22
K22
G22
F22
E22
D22
A22
BA21
AV21
AR21

3

U23J

AN21

VSS200

AL21

VSS201

AB21

VSS202

Y21

VSS203

P21

VSS204

K21

VSS205

J21

VSS206

H21

VSS207

C21

VSS208

AW20

VSS209

AR20

VSS210

AM20

VSS211

AA20

VSS212

K20

VSS213

B20

VSS214

A20

VSS215

AN19

VSS216

AC19

VSS217

W19

VSS218

K19

VSS219

G19

VSS220

C19

VSS221

AH18

VSS222

P18

VSS223

H18

VSS224

D18

VSS225

A18

VSS226

AY17

VSS227

AR17

VSS228

AP17

VSS229

AM17

VSS230

AK17

VSS231

AV16

VSS232

AN16

VSS233

AL16

VSS234

J16

VSS235

F16

VSS236

C16

VSS237

AN15

VSS238

AM15

VSS239

AK15

VSS240

N15

VSS241

M15

VSS242

L15

VSS243

B15

VSS244

A15

VSS245

BA14

VSS246

AT14

VSS247

AK14

VSS248

AD14

VSS249

AA14

VSS250

U14

VSS251

K14

VSS252

H14

VSS253

E14

VSS254

AV13

VSS255

AR13

VSS256

AN13

VSS257

AM13

VSS258

AL13

VSS259

AG13

VSS260

P13

VSS261

F13

VSS262

D13

VSS265

B13

VSS264

AY12

VSS263

AC12

VSS266

K12

VSS267

H12

VSS268

E12

VSS269

AD11

VSS270

AA11

VSS271

Y11

VSS272

J11

VSS273

D11

VSS274

B11

VSS275

AV10

VSS276

AP10

VSS277

AL10

VSS278

AJ10

VSS279

CALISTOGA_FCBGA1466~D

<BOM Structure>

P O W E R

VSS280
VSS281
VSS282
VSS283
VSS284
VSS285
VSS286
VSS287
VSS288
VSS289
VSS290
VSS292
VSS291
VSS293
VSS294
VSS295
VSS296
VSS297
VSS298
VSS299
VSS300
VSS301
VSS302
VSS303
VSS304
VSS305
VSS306
VSS307
VSS308
VSS309
VSS310
VSS311
VSS312
VSS313
VSS314
VSS315
VSS316
VSS317
VSS318
VSS319
VSS320
VSS321
VSS322
VSS323
VSS324
VSS325
VSS326
VSS327
VSS328
VSS329
VSS330
VSS331
VSS332
VSS333
VSS334
VSS335
VSS336
VSS337
VSS338
VSS339
VSS340
VSS341
VSS342
VSS343
VSS344
VSS345
VSS346
VSS347
VSS348
VSS349
VSS350
VSS351
VSS352
VSS353
VSS354
VSS355
VSS356
VSS357
VSS358
VSS359
VSS360

AG10
AC10
W10
U10
BA9
AW9
AR9
AH9
AB9
Y9
R9
G9
E9
A9
AG8
AD8
AA8
U8
K8
C8
BA7
AV7
AP7
AL7
AJ7
AH7
AF7
AC7
R7
G7
D7
AG6
AD6
AB6
Y6
U6
N6
K6
H6
B6
AV5
AF5
AD5
AY4
AR4
AP4
AL4
AJ4
Y4
U4
R4
J4
F4
C4
AY3
AW3
AV3
AL3
AH3
AG3
AF3
AD3
AC3
AA3
G3
AT2
AR2
AP2
AK2
AJ2
AD2
AB2
Y2
U2
T2
N2
J2
H2
F2
C2
AL1

2

1

C71

2

0.22U_0603_10V7K

1

C101

2

10U_1206_6.3V6M

C113

0.22U_0603_10V7K

C65

10U_1206_6.3V6M

1

2

1

2

C111

C96

+VCCP

+VCCP

1

C63

2

0.22U_0603_10V7K

1

C85

2

1U_0603_10V4Z

1

+

220U_D2_4VM

2

1

+

220U_D2_4VM@

2

U23F

AD27

VCC_NCTF0

AC27

VCC_NCTF1

AB27

VCC_NCTF2

AA27

VCC_NCTF3

Y27

VCC_NCTF4

W27

VCC_NCTF5

V27

VCC_NCTF6

U27

VCC_NCTF7

T27

VCC_NCTF8

R27

VCC_NCTF9

AD26

VCC_NCTF10

AC26

VCC_NCTF11

AB26

VCC_NCTF12

AA26

VCC_NCTF13

Y26

VCC_NCTF14

W26

VCC_NCTF15

V26

VCC_NCTF16

U26

VCC_NCTF17

T26

VCC_NCTF18

R26

VCC_NCTF19

AD25

VCC_NCTF20

AC25

VCC_NCTF21

AB25

VCC_NCTF22

AA25

VCC_NCTF23

Y25

VCC_NCTF24

W25

VCC_NCTF25

V25

VCC_NCTF26

U25

VCC_NCTF27

T25

VCC_NCTF28

R25

VCC_NCTF29

AD24

VCC_NCTF30

AC24

VCC_NCTF31

AB24

VCC_NCTF32

AA24

VCC_NCTF33

Y24

VCC_NCTF34

W24

VCC_NCTF35

V24

VCC_NCTF36

U24

VCC_NCTF37

T24

VCC_NCTF38

R24

VCC_NCTF39

AD23

VCC_NCTF40

V23

VCC_NCTF41

U23

VCC_NCTF42

T23

VCC_NCTF43

R23

VCC_NCTF44

AD22

VCC_NCTF45

V22

VCC_NCTF46

U22

VCC_NCTF47

T22

VCC_NCTF48

R22

VCC_NCTF49

AD21

VCC_NCTF50

V21

VCC_NCTF51

U21

VCC_NCTF52

T21

VCC_NCTF53

R21

VCC_NCTF54

AD20

VCC_NCTF55

V20

VCC_NCTF56

U20

VCC_NCTF57

T20

VCC_NCTF58

R20

VCC_NCTF59

AD19

VCC_NCTF60

V19

VCC_NCTF61

U19

VCC_NCTF62

T19

VCC_NCTF63

AD18

VCC_NCTF64

AC18

VCC_NCTF65

AB18

VCC_NCTF66

AA18

VCC_NCTF67

Y18

VCC_NCTF68

W18

VCC_NCTF69

V18

VCC_NCTF70

U18

VCC_NCTF71

T18

VCC_NCTF72

M19

VCC100

L19

VCC101

N18

VCC102

M18

VCC103

L18

VCC104

P17

VCC105

N17

VCC106

M17

VCC107

N16

VCC108

M16

VCC109

L16

VCC110

CALISTOGA_FCBGA1466~D

<BOM Structure>

1

VCCAUX_NCTF0
VCCAUX_NCTF1
VCCAUX_NCTF2
VCCAUX_NCTF3
VCCAUX_NCTF4
VCCAUX_NCTF5
VCCAUX_NCTF6
VCCAUX_NCTF7
VCCAUX_NCTF8

VCCAUX_NCTF9
VCCAUX_NCTF10
VCCAUX_NCTF11
VCCAUX_NCTF12
VCCAUX_NCTF13
VCCAUX_NCTF14
VCCAUX_NCTF15
VCCAUX_NCTF16
VCCAUX_NCTF17
VCCAUX_NCTF18
VCCAUX_NCTF19
VCCAUX_NCTF20
VCCAUX_NCTF21
VCCAUX_NCTF22
VCCAUX_NCTF23
VCCAUX_NCTF24
VCCAUX_NCTF25
VCCAUX_NCTF26
VCCAUX_NCTF27
VCCAUX_NCTF28
VCCAUX_NCTF29
VCCAUX_NCTF30
VCCAUX_NCTF31
VCCAUX_NCTF32
VCCAUX_NCTF33
VCCAUX_NCTF34
VCCAUX_NCTF35
VCCAUX_NCTF36

P O W E R

VCCAUX_NCTF37
VCCAUX_NCTF38
VCCAUX_NCTF39
VCCAUX_NCTF40
VCCAUX_NCTF41
VCCAUX_NCTF42
VCCAUX_NCTF43
VCCAUX_NCTF44
VCCAUX_NCTF45
VCCAUX_NCTF46
VCCAUX_NCTF47
VCCAUX_NCTF48
VCCAUX_NCTF49
VCCAUX_NCTF50
VCCAUX_NCTF51
VCCAUX_NCTF52
VCCAUX_NCTF53
VCCAUX_NCTF54
VCCAUX_NCTF55
VCCAUX_NCTF56
VCCAUX_NCTF57

VSS_NCTF0
VSS_NCTF1
VSS_NCTF2
VSS_NCTF3
VSS_NCTF4
VSS_NCTF5
VSS_NCTF6
VSS_NCTF7
VSS_NCTF8

VSS_NCTF9
VSS_NCTF10
VSS_NCTF11
VSS_NCTF12

VCC_SM100
VCC_SM101
VCC_SM102
VCC_SM103
VCC_SM104
VCC_SM105
VCC_SM106
VCC_SM107

AG27
AF27
AG26
AF26
AG25
AF25
AG24
AF24
AG23
AF23
AG22
AF22
AG21
AF21
AG20
AF20
AG19
AF19
R19
AG18
AF18
R18
AG17
AF17
AE17
AD17
AB17
AA17
W17
V17
T17
R17
AG16
AF16
AE16
AD16
AC16
AB16
AA16
Y16
W16
V16
U16
T16
R16
AG15
AF15
AE15
AD15
AC15
AB15
AA15
Y15
W15
V15
U15
T15
R15

AE27
AE26
AE25
AE24
AE23
AE22
AE21
AE20
AE19
AE18
AC17
Y17
U17

AR6
AP6
AN6
AL6
AK6
AJ6
AV1
AJ1

C51

+1.5VS

1

C50

2

0.47U_0603_10V7K

0.47U_0603_10V7K

+1.8V

1

2

Place near pin AV1 & AJ1

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/12/1 2006/12/01

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

Calistoga(3)
LA-3271P

1

0.4

of

11 42Monday, August 21, 2006

5

AC14
AB14

W14

V14
T14
R14
P14
N14

M14

L14
AD13
AC13
AB13
AA13

Y13

W13

V13

U13

T13

R13

N13

M13

L13
AB12
AA12

Y12

W12

V12

U12

T12

R12

P12

N12

M12

L12

R11

P11

1

N11

M11

R10

2

P10

N10

M10

P9
N9
M9
R8
P8
N8
M8
P7
N7
M7
R6
P6
M6
A6
R5
P5
N5
M5
P4
N4
M4
R3

0.47U_0603_10V7K

P3
N3
M3
R2
P2
M2
D2

AB1

R1
P1
N1
M1

1

C49

2

AG14
AF14
AE14

Y14
AF13
AE13
AF12
AE12
AD12

+1.5VS

21

D20

@

CH751H-40_SC76

12

R34510_0402_5%

@

U23H

VTT0
VTT1
VTT2
VTT3
VTT4
VTT5
VTT6
VTT7
VTT8
VTT9
VTT10
VTT11
VTT12
VTT13
VTT14
VTT15
VTT16
VTT17
VTT18
VTT19
VTT20
VTT21
VTT22
VTT23
VTT24
VTT25
VTT26
VTT27
VTT28
VTT29
VTT30
VTT31
VTT32

P O W E R

VTT33
VTT34
VTT35
VTT36
VTT37
VTT38
VTT39
VTT40
VTT41
VTT42
VTT43
VTT44
VTT45
VTT46
VTT47
VTT48
VTT49
VTT50
VTT51
VTT52
VTT53
VTT54
VTT55
VTT56
VTT57
VTT58
VTT59
VTT60
VTT61
VTT62
VTT63
VTT64
VTT65
VTT66
VTT67
VTT68
VTT69
VTT70
VTT71
VTT72
VTT73
VTT74
VTT75
VTT76

VCCAUX32
VCCAUX33
VCCAUX34
VCCAUX35
VCCAUX36
VCCAUX37
VCCAUX38
VCCAUX39
VCCAUX40

CALISTOGA_FCBGA1466~D

<BOM Structure>

+2.5VS

1

C138

2

0.1U_0402_16V4Z

close pin G41

5

VCC_SYNC

VCCTX_LVDS0
VCCTX_LVDS1
VCCTX_LVDS2

VCC3G0
VCC3G1
VCC3G2
VCC3G3
VCC3G4
VCC3G5
VCC3G6

VCCA_3GPLL

VCCA_3GBG

VSSA_3GBG

VCCA_CRTDAC0
VCCA_CRTDAC1
VSSA_CRTDAC2

VCCA_DPLLA
VCCA_DPLLB

VCCA_HPLL

VCCA_LVDS
VSSA_LVDS

VCCA_MPLL
VCCA_TVBG

VSSA_TVBG

VCCA_TVDACA0
VCCA_TVDACA1
VCCA_TVDACB0
VCCA_TVDACB1
VCCA_TVDACC0
VCCA_TVDACC1

VCCD_HMPLL0
VCCD_HMPLL1

VCCD_LVDS0
VCCD_LVDS1
VCCD_LVDS2

VCCD_TVDAC

VCCDQ_TVDAC

VCCHV0
VCCHV1
VCCHV2

VCCAUX0
VCCAUX1
VCCAUX2
VCCAUX3
VCCAUX4
VCCAUX5
VCCAUX6
VCCAUX7
VCCAUX8

VCCAUX9
VCCAUX10
VCCAUX11
VCCAUX12
VCCAUX13
VCCAUX14
VCCAUX15
VCCAUX16
VCCAUX17
VCCAUX18
VCCAUX19
VCCAUX20
VCCAUX21
VCCAUX22
VCCAUX23
VCCAUX24
VCCAUX25
VCCAUX26
VCCAUX27
VCCAUX28
VCCAUX29
VCCAUX30
VCCAUX31

+2.5VS

1

C376

2

0.01U_0402_16V7K

close pin A38

+VCCP

D D

C C

B B

A A

C48

1

C58

2

4.7U_0805_10V4Z

MCH_A6

1

2

1

C56

2

1

0.22U_0603_10V7K
C46

2

+1.5VS

+VCCP

21

D9

@

CH751H-40_SC76

12

+2.5VS +3VS

R6310_0402_5%

@

1

+

220U_D2_4VM

2

C59

2.2U_0805_16V4Z

C54

MCH_D2

MCH_AB1

0.22U_0603_10V7K

0.47U_0603_10V7K

H22

B30
C30
A30

AB41
AJ41
L41
N41
R41
V41
Y41

AC33
G41
H41

E21
F21
G21

B26
C39
AF1

A38
B39

AF2
H20

G20

E19
F19
C20
D20
E20
F20

AH1
AH2

A28
B28
C28

D21
H19

A23
B23
B25

AK31
AF31
AE31
AC31
AL30
AK30
AJ30
AH30
AG30
AF30
AE30
AD30
AC30
AG29
AF29
AE29
AD29
AC29
AG28
AF28
AE28
AH22
AJ21
AH21
AJ20
AH20
AH19
P19
P16
AH15
P15
AH14

1

C377

2

0.1U_0402_16V4Z

+2.5VS

1 2

C81

0.1U_0402_16V4Z

+2.5VS

W=40 mils

1

C386

2

+1.5VS_3GPLL
+2.5VS

+2.5VS_CRTDAC

+1.5VS_DPLLA
+1.5VS_DPLLB
+1.5VS_HPLL

+2.5VS

+1.5VS_MPLL
+3VS_TVBG

VSSA_TVBG

+3VS_TVDACA
+3VS_TVDACB
+3VS_TVDACC

+1.5VS

+1.5VS_TVDAC
+1.5VS_QTVDAC

1

2

C369

0.1U_0402_16V4Z

10U_0805_6.3V6M

+1.5VS

1

2

+2.5VS

1

C116

2

4.7U_0603_6.3V6M

close pin B30/C30/A30

+1.5VS_PCIE

1

+

C384

2

220U_D2_4VM

1

2

C61

+3VS

1

2

C368

C112

0.1U_0402_16V4Z

1

C114

2

0.1U_0402_16V4Z

4

R352

0_0805_5%

1

C385

2

10U_0805_6.3V6M

10U_0805_6.3V6M

L19 BLM11A601S_0603

1 2

1

1

C382

C381

2

2

0.1U_0402_16V4Z

CRTDAC: Route caps within

0.022U_0402_16V7K~N

250mil of Alviso. Route FB
within 3" of Calistoga

R54

0_0805_5%

1

2

C66

0.1U_0402_16V4Z

0.022U_0402_16V7K~N

+1.5VS

1

1

C375

C374

2

2

10U_0805_4VAM

0.01U_0402_16V7K

4

12

+3VS+3VS_TVBG

12

+1.5VS

+2.5VS

1

2

+1.5VS_DPLLA

0.1U_0402_16V4Z

1

C74

2

0.022U_0402_16V7K~N

CHB1608U301_0603

470U_D2_2.5VM

1

C87

1

+

C97

2

2

0_0805_5%

1

1

2

2

C78

C73

0.1U_0402_16V4Z

0.022U_0402_16V7K~N

+3VS+3VS_TVDACC

R341

12

0_0805_5%

C367

0.1U_0402_16V4Z

L2

R342

12

+3VS+3VS_TVDACB

12

+1.5VS_DPLLB

0.1U_0402_16V4Z

1

C372

2

+1.5VS

+1.5VS

12

L3

CHB1608U301_0603

470U_D2_2.5VM

1

C141

C131

1

+

2

2

+3VS+3VS_TVDACA

R344

12

0_0805_5%

1

C373

2

0.1U_0402_16V4Z

0.022U_0402_16V7K~N

PCI-E/MEM/PSB PLL decoupling

+1.5VS_TVDAC +1.5VS

0_0603_5%
R343

1

1

C370

2

2

0.1U_0402_16V4Z

0.022U_0402_16V7K~N

R75
0_0603_5%

1

1

C147

C120

2

2

0.1U_0402_16V4Z

10U_1206_6.3V6M

+1.5VS_MPLL

45mA Max.

1

2

0.1U_0402_16V4Z
C53

12

C371

+1.5VS+1.5VS_3GPLL

12

45mA Max.

1

C143

2

0.1U_0402_16V4Z

R37
0_0603_5%

1

2

C40

22U_0805_6.3V6M

+1.5VS_QTVDAC +1.5VS

R340
0_0603_5%

12

1

1

C70

C64

2

0.022U_0402_16V7K~N

R36
0_0603_5%

1

1

0.1U_0402_16V4Z

C41

2

2

C45

C366

0.1U_0402_16V4Z

22U_0805_6.3V6M

2

0.1U_0402_16V4Z

+1.5VS_HPLL

12

+1.5VS

1

2

12

3

+VCCP +1.8V

+1.5VS

3

U23G

AA33

VCC0

W33

VCC1

P33

VCC2

N33

VCC3

L33

VCC4

J33

VCC5

AA32

VCC6

Y32

VCC7

W32

VCC8

V32

VCC9

P32

VCC10

N32

VCC11

M32

VCC12

L32

VCC13

J32

VCC14

AA31

VCC15

W31

VCC16

V31

VCC17

T31

VCC18

R31

VCC19

P31

VCC20

N31

VCC21

M31

VCC22

AA30

VCC23

Y30

VCC24

W30

VCC25

V30

VCC26

U30

VCC27

T30

VCC28

R30

VCC29

P30

VCC30

N30

VCC31

M30

VCC32

L30

AA29

Y29

W29

V29
U29
R29
P29

M29

L29
AB28
AA28

Y28

V28

U28

T28

R28

P28

N28

M28

L28

P27

N27

M27

L27

P26

N26

L26

N25

M25

L25

P24

N24

M24
AB23
AA23

Y23
P23
N23

M23

L23
AC22
AB22

Y22

W22

P22

N22

M22

L22
AC21
AA21

W21

N21

M21

L21
AC20
AB20

Y20

W20

P20

N20

M20

L20
AB19
AA19

Y19

N19

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

P O W E R

VCC33
VCC34
VCC35
VCC36
VCC37
VCC38
VCC39
VCC40
VCC41
VCC42
VCC43
VCC44
VCC45
VCC46
VCC47
VCC48
VCC49
VCC50
VCC51
VCC52
VCC53
VCC54
VCC55
VCC56
VCC57
VCC58
VCC59
VCC60
VCC61
VCC62
VCC63
VCC64
VCC65
VCC66
VCC67
VCC68
VCC69
VCC70
VCC71
VCC72
VCC73
VCC74
VCC75
VCC76
VCC77
VCC78
VCC79
VCC80
VCC81
VCC82
VCC83
VCC84
VCC85
VCC86
VCC87
VCC88
VCC89
VCC90
VCC91
VCC92
VCC93
VCC94
VCC95
VCC96
VCC97
VCC98
VCC99

CALISTOGA_FCBGA1466~D

<BOM Structure>

2005/12/1 2006/12/01

VCC_SM0
VCC_SM1
VCC_SM2
VCC_SM3
VCC_SM4
VCC_SM5
VCC_SM6
VCC_SM7
VCC_SM8

VCC_SM9
VCC_SM10
VCC_SM11
VCC_SM12
VCC_SM13
VCC_SM14
VCC_SM15
VCC_SM16
VCC_SM17
VCC_SM18
VCC_SM19
VCC_SM20
VCC_SM21
VCC_SM22
VCC_SM23
VCC_SM24
VCC_SM25
VCC_SM26
VCC_SM27
VCC_SM28
VCC_SM29
VCC_SM30
VCC_SM31
VCC_SM32
VCC_SM33
VCC_SM34
VCC_SM35
VCC_SM36
VCC_SM37
VCC_SM38
VCC_SM39
VCC_SM40
VCC_SM41
VCC_SM42
VCC_SM43
VCC_SM44
VCC_SM45
VCC_SM46
VCC_SM47
VCC_SM48
VCC_SM49
VCC_SM50
VCC_SM51
VCC_SM52
VCC_SM53
VCC_SM54
VCC_SM55
VCC_SM56
VCC_SM57
VCC_SM58
VCC_SM59
VCC_SM60
VCC_SM61
VCC_SM62
VCC_SM63
VCC_SM64
VCC_SM65
VCC_SM66
VCC_SM67
VCC_SM68
VCC_SM69
VCC_SM70
VCC_SM71
VCC_SM72
VCC_SM73
VCC_SM74
VCC_SM75
VCC_SM76
VCC_SM77
VCC_SM78
VCC_SM79
VCC_SM80
VCC_SM81
VCC_SM82
VCC_SM83
VCC_SM84
VCC_SM85
VCC_SM86
VCC_SM87
VCC_SM88
VCC_SM89
VCC_SM90
VCC_SM91
VCC_SM92
VCC_SM93
VCC_SM94
VCC_SM95
VCC_SM96
VCC_SM97
VCC_SM98
VCC_SM99

AU41
AT41
AM41
AU40
BA34
AY34
AW34
AV34
AU34
AT34
AR34
BA30
AY30
AW30
AV30
AU30
AT30
AR30
AP30
AN30
AM30
AM29
AL29
AK29
AJ29
AH29
AJ28
AH28
AJ27
AH27
BA26
AY26
AW26
AV26
AU26
AT26
AR26
AJ26
AH26
AJ25
AH25
AJ24
AH24
BA23
AJ23
BA22
AY22
AW22
AV22
AU22
AT22
AR22
AP22
AK22
AJ22
AK21
AK20
BA19
AY19
AW19
AV19
AU19
AT19
AR19
AP19
AK19
AJ19
AJ18
AJ17
AH17
AJ16
AH16
BA15
AY15
AW15
AV15
AU15
AT15
AR15
AJ15
AJ14
AJ13
AH13
AK12
AJ12
AH12
AG12
AK11
BA8
AY8
AW8
AV8
AT8
AR8
AP8
BA6
AY6
AW6
AV6
AT6

Compal Secret Data

2

MCH_AT41
MCH_AM41

1

C142

C136

2

0.47U_0603_10V7K

Place near pin AT41
& AM41

1

1

2

2

0.1U_0402_16V4Z

C98

C72

0.1U_0402_16V4Z

C109

1

C86

2

0.47U_0603_10V7K

Place near pin BA23

1

1

C365

C380

2

2

10U_1206_6.3V6M

10U_1206_6.3V6M

1

C60

2

0.47U_0603_10V7K

Place near pin BA15

Deciphered Date

2

0.47U_0603_10V7K

1

2

C494

1

2

1

2

0.1U_0402_16V4Z

C55

0.1U_0402_16V4Z

1

1

C495

2

2

10U_1206_6.3V6M

10U_1206_6.3V6M

@

Strap Pin Table

CFG[3:17] have internal pull up
CFG[19:18] have internal pull down

011 = 667MT/s FSB

CFG[2:0]

CFG5

CFG7

CFG9

CFG6

PSB 4X CLK Enable 1 = Calistoga

CFG[13:12]

CFG16

CFG10 CFG18

CFG19

SDVO_CTRLDATA

CFG20

(PCIE/SDVO select)

1

1

+

C378

C496

2

2

10U_1206_6.3V6M

@

330U_D2E_2.5VM_R9

R48 2.2K_0402_5% @

CFG39

CFG179

CFG59
CFG79

CFG99
CFG119
CFG129

CFG139
CFG169

CFG189
CFG199
CFG209

1 2

R95 2.2K_0402_5%@

1 2

R101 2.2K_0402_5%@

1 2

R97 2.2K_0402_5%@

1 2

R100 2.2K_0402_5%@

1 2

R103 2.2K_0402_5%@

1 2

R94 2.2K_0402_5%@

1 2

R102 2.2K_0402_5%@

1 2

R96 2.2K_0402_5%@

1 2

R80 1K_0402_5%@
R82 1K_0402_5% @
R81 1K_0402_5%@

Title

Size Document Number Rev

Custom

Date: Sheet

001 = 533MT/s FSB
0 = DMI x 2

1 = DMI x 4
0 = Reserved

1 = Mobile Yonah CPU
0 = Lane Reversal Enable

1 = Normal Operation

0 = Reserved

00 = Reserved
01 = XOR Mode Enabled
10 = All Z Mode Enabled
11 = Normal Operation

0 = Dynamic ODT Disabled
1 = Dynamic ODT Enabled (Default)

10 = 1.05V
01 = 1.5V

0 = Normal Operation
1 = DMI Lane Reversal Enable

0 = No SDVO Device Present

1 = SDVO Device Present

0 = Only PCIE or SDVO is
operational.
1 = PCIE/SDVO are operating
simu.

1 2
1 2
1 2

Compal Electronics, Inc.

LA-3271P

1

*

(Default)

+3VS

Calistoga(4)

1

(Default)

*

*

(Default)

(Default)

*

(Default)

*

(Default)

(Default)

*

*

(Default)

*

12 42Monday, August 21, 2006

*

*

0.4

of

A

+CK_VDD_MAIN1

1 2

+3VS

R146 0_0805_5%

1 2

+3VS

+3VS

+VCCP

R410

8.2K_0402_5%

CLKREF1

Q34

2N7002_SOT23

R158 0_0805_5%

R159

1 2

0_0805_5%

R150

1 2

0_0805_5%@

R130

8.2K_0402_5%

FSA

1 2

R128
0_0402_5%

CLK_Ra

FSB

12

1 2

R411
0_0402_5%

CLK_Rb

R412

8.2K_0402_5%

1 2

R430 0_0402_5%

CLK_Rc

1 2

R127 0_0402_5%

10/18

13

D

2

G

@

S

A

1 1

CPU_BSEL05

2 2

FSB_G

CPU_BSEL15

3 3

CPU_BSEL25

CLK_EN#37

4 4

VGATE5,17,26,37

+CK_VDD_MAIN2

+VCCP

1 2

12

12

@

+VCCP

1 2

12

+VCCP

1 2

12

@

12

+3VS

12

R126
10K_0402_5%

CLK_ENABLE#

+3VS

R360
2K_0402_1%

1 2

CLK_ENABLE#

12

R359
300_0402_5%

12

J1
NO SHORT PADS

1

C213
10U_0805_10V4Z

2

1

C215
10U_0805_10V4Z

2

+CK_VDD_XDP

1

C211
10U_0805_10V4Z

2

R133

56_0402_5%

CLK_Rd

1 2

R132 1K_0402_5%

R131
1K_0402_5%

@

R428
1K_0402_5%

1 2

R423
1K_0402_5%

R425

@

0_0402_5%

CLK_Re

R429
1K_0402_5%

@
1 2

R426

1K_0402_5%

R424

0_0402_5%

CLK_Rf

@

1

C209

0.1U_0402_16V4Z

2

1

C220

0.1U_0402_16V4Z

2

5/20

1

C226

0.1U_0402_16V4Z

2

MCH_CLKSEL0 9

MCH_CLKSEL1 9

MCH_CLKSEL2 9

B

1

C212

0.1U_0402_16V4Z

2

1

C216

0.1U_0402_16V4Z

2

1

C208

0.1U_0402_16V4Z

2

0.1U_0402_16V4Z@

DOT96 & LCDCLK select

High:Pin14/15 = DOT96

*

pin17/18 = LCDCLK

FSLC1FSLB

CLKSEL1

CLKSEL2

0

0

1

B

+3VS

+CK_VDD_XDP

C224

12

R140
10K_0402_5%

SELDOT

12

R136
10K_0402_5%

FSLA

CLKSEL0

1

2

1

2

12

R164

0_0402_5%@

1

2

@

CPU
MHz

133

166

C223

0.1U_0402_16V4Z

R157

1 2

1_0805_1%

1 2

R144

2.2_0805_1%

C225

0.1U_0402_16V4Z

CLKIREF

SRC
MHz

1000

100

C

CK_VDD_REF

CK_VDD_48

Place crystal within
500 mils of CK410

PCI
MHz

33.31

33.3

C

+3VS

D

R882

@

0_0402_5%

1 2

D

ICH_SMBDATA17,23

ICH_SMBCLK17,23

12

1

C230

R171
0_0805_5%

0.1U_0402_16V4Z

2

CLK_PCIE_LAN_EN17

CLK_48M_ICH17

CLK_14M_ICH17

CLK_ENABLE#

CLK_PCI_ICH15

CLK_PCI_EC26
CLK_PCI_SIO_DB26
CLK_PCI_CB20

CLK_PCI_FWH27

CLK_PCI_TPM26

CLK_DEBUG_PORT23

CLK_MCH_DREFCLK9

CLK_MCH_DREFCLK#9

C417 33P_0402_50V8J

14.31818MHZ_20P_6X1430004201
C416 33P_0402_50V8J

H_STP_CPU#17

H_STP_PCI#17

CLK_PCI_ICH
CLK_PCI_EC
CLK_PCI_SIO_DB CLKREF0
CLK_PCI_CB

CLK_MCH_DREFCLK
CLK_MCH_DREFCLK#

1 3

2

+3VS

2

1 3

D

1 2

R885

@

0_0402_5%

C210 0.1U_0402_16V4Z

C221 0.1U_0402_16V4Z

1 2

Y3

1 2

CLK_PCIE_LAN_EN
CLK_48M_ICH

CLK_14M_ICH

1 2

H_STP_CPU#
H_STP_PCI#
CLK_ENABLE#

R376 33_0402_5%
R388 33_0402_5%
R405 33_0402_5%@
R402 33_0402_5%

R396 33_0402_5%

1 2

R390 0_0402_5%

CLK_SMBDATA7,8

CLK_SMBCLK7,8

1 2

R375 24_0402_5%

1 2

R374 24_0402_5%

+3VS

2.2K_0402_5%

S

Q21

2N7002_SOT23

G

G

Q20

2N7002_SOT23

S

+CK_VDD_MAIN1

+CK_VDD_XDP

CK_VDD_48

12

CK_VDD_REF

12

CLK_XTAL_IN

12

CLK_XTAL_OUT

R387 12_0402_5% @

12
12

R369 33_0402_5%

12

R408 33_0402_5%

R1564.7K_0402_1%

12
12
12
12

12

R39133_0402_5%

12

CLK_SMBDATA
CLK_SMBCLK

MCH_DREFCLK

MCH_DREFCLK#

R165

FSA
FSB_G

CLKREF1

CLKIREF

PCI_ICH
SELDOT

PCI_CLK3

PCI_TPM

E

R166

2.2K_0402_5%

CLK_SMBDATA

CLK_SMBCLK

U28

1

VDDPCI

7

VDDPCI

50

VDDCPU

28

VDDPCIEX

42

VDDPCIEX

11

VDD48

56

VDDREF

45

VDDA

46

GNDA

58

X1

57

X2

12

FSLA/USB_48MHz

60

FSLB/REF0

61

FSLC/REF1

47

VREF

62

CPU_STOP#

63

PCI/PCIEX_STOP#

10

Vtt_PwrGd#/PD

8

PCICLK_F0

9

*SELDOT/PCICLK_F1

64

PCICLK0_2x

3

PCICLK1_2x

4

PCICLK2_2x

5

PCICLK3

55

SDATA

54

SCLK

14

DOT96T_LP/27FIX

15

DOT96C_LP/27FIX

2

GND

6

GND

13

GND

21

GND

29

GND

37

GND

53

GND

59

GND

* Pull-Up or Down Strap Pin

ICS9LPR310_TSSOP64

PCIeC0_LP/LCDCLKC_LP

SATACLKT_LP
SATACLKC_LP

CPUCLKT0_LP
CPUCLKC0_LP

CPUCLKT1_LP
CPUCLKC1_LP

PCIeT0_LP/LCDCLKT_LP

*PEREQ1#

PCIeT6_LP
PCIeC6_LP

*PEREQ2#
PCIeT1_LP
PCIeC1_LP
PCIeT8_LP
PCIeC8_LP

*PEREQ3#
PCIeT2_LP
PCIeC2_LP
PCIeT4_LP
PCIeC4_LP

*PEREQ4#
PCIeT3_LP
PCIeC3_LP
PCIeT5_LP
PCIeC5_LP
PCIeT7_LP
PCIeC7_LP

F

PCIE_SATA

26
27

52
51

49
48

17
18

16

39
38

34
19
20
44
43

32
22
23
30
31

33
24
25
36
35
41
40

1 2

R371 24_0402_5%

PCIE_SATA#

1 2

R370 24_0402_5%

CPU_BCLK

1 2

R420 24_0402_5%

CPU_BCLK#

1 2

R419 24_0402_5%

MCH_BCLK

1 2

R418 24_0402_5%

MCH_BCLK#

1 2

R417 24_0402_5%

SSCDREFCLK

1 2

R386 24_0402_5%

SSCDREFCLK#

1 2

R385 24_0402_5%

MCH_3GPLL

1 2

R416 24_0402_5%

MCH_3GPLL# CLK_MCH_3GPLL#

1 2

R415 24_0402_5%

R422 10K_0402_5%
R413 10K_0402_5%@

CLKREQB#

R421 10K_0402_5%@

1 2

R384 24_0402_5%

PCIE_ICH#

1 2

R383 24_0402_5%

R399 0_0402_5%@

1 2

R397 24_0402_5%@

1 2

R382 24_0402_5%

1 2

R381 24_0402_5%

R409 0_0402_5%@

PCIE_MCARD

1 2

R380 24_0402_5%

PCIE_MCARD#

1 2

R379 24_0402_5%

MCH_SSCDREFCLK
MCH_SSCDREFCLK#

CLKREQA#

12

12
12

R400 10K_0402_5%

12

R406 10K_0402_5%

CLKREQD#CPU_XDP#

12

CLK_PCIE_SATA
CLK_PCIE_SATA#

CLK_CPU_BCLK
CLK_CPU_BCLK#

CLK_MCH_BCLK
CLK_MCH_BCLK#

R139 10K_0402_5%

CLK_MCH_3GPLL

CPPE#

CLK_PCIE_ICHPCIE_ICH
CLK_PCIE_ICH#

CLKREQC#
SATACLKREQ#CPU_XDP
CLK_PCIE_LANPCIE_LOM
CLK_PCIE_LAN#PCIE_LOM#

12

CLK_PCIE_MCARD
CLK_PCIE_MCARD#

G

CLKREQA#

1 2

C205

1000P_0402_50V7K@

CLKREQB#

1 2

C419

1000P_0402_50V7K@

CPU_XDP

1 2

C412

1000P_0402_50V7K@

CPU_XDP#

1 2

C218

1000P_0402_50V7K

Place near U62

CLK_PCIE_SATA 16
CLK_PCIE_SATA# 16

CLK_CPU_BCLK 4
CLK_CPU_BCLK# 4

CLK_MCH_BCLK 9
CLK_MCH_BCLK# 9

MCH_SSCDREFCLK 9
MCH_SSCDREFCLK# 9

12

+3VS

12

+3VS

CLKREQA# 9

CLK_MCH_3GPLL 9
CLK_MCH_3GPLL# 9

CPPE# 15
CLK_PCIE_ICH_EN 17

CLK_PCIE_ICH 17
CLK_PCIE_ICH# 17

+3VS

CLKREQC# 22

CLK_PCIE_LAN 22
CLK_PCIE_LAN# 22

+3VS
CLKREQD# 23
CLK_PCIE_MCARD 23
CLK_PCIE_MCARD# 23

SATACLKREQ#

12

R403 10K_0402_5%

12

R404 10K_0402_5%@

H

SATACLKREQ# 17

+3VS

NOXDP@ : means just build when XDP function disable.
XDP@ : means just build when XDP function enable.

When this time, docking PCI express will not work.

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

D

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

E

2005/12/1 2006/12/01

Compal Secret Data

Deciphered Date

F

Title

Size Document Number Rev

Custom

Date: Sheet of

G

Clock Generator
LA-3271P

13 42Monday, August 21, 2006

H

0.4