COMPAL LA-3262P Schematics

1 1

2 2

Compal confidential

Schematics Document

Mobile Merom uFCPGA with Intel Crestline + ICH8-M core logic

3 3

IBT00 LA-3262P Discrete VGA (M64)

2007-08-02

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2006/09/25 2006/09/25

REV:1A

Compal Secret Data

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Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

Cover Sheet

LA3262P_DIS__M64

157Tuesday, August 21, 2007

Compal confidential

File Name : LA-3262P

Chimay Discrete

1 1

Thermal Sensor ADM1032ARMZ

Fan conn

CRT & TV OUT

P16

LVDS Panel Interface

P17

DVI (Docking)

2 2

P33

ATI M64S

P18, 19, 20, 21, 22, 23

PCIE

Intel Crestline MCH

DMI X4

PCI-E BUS

10/100/1000 LAN

Mini-Card

Intel 82566MM

P29

RJ45/11 CONN

3 3

P30

LED

P30

CardBus Controller & PCMCIA conn

Ricoh R5C853

P31

Slot 0/Smart Card

1394 port

P34

6in1 Slot

PCI

daughter board

RTC CKT.

P19

Mobile Merom

uFCPGA-478 CPU

H_A#(3..35) H_D#(0..63)

FCBGA 1299

(PM)

P7, 8, 9, 10, 11, 12

Intel ICH8-M

mBGA-676

P4, 5, 6

FSB

667/800MHz 1.05V

C-Link

USB2.0

Azalia

SATA Master

P24, 25, 26, 27

PATA Slave

SPI

SPI ROM & Debug port 16Mb*2 or 32Mb*1

LPC BUS

DDR2 667MHz 1.8V

Dual Channel

P36

DDR2-SO-DIMM X2

BANK 0, 1, 2, 3

P13, 14

USB conn x2 (Docking)

FingerPrinter AES1610 USBx1

USB conn x3

BT Conn

Mini-Card WWAN

P25P25

Audio CKT

AD1981HD

P32

SATA HDD Connector

P28

Multi-bay II Connector

P28

P33

P34

P28

CK505

Clock Generator ICS 9LPRS355

P15

daughter board

MDC

P38

AMP & Audio Jack

MAX9710

P33

Docking CONN.

*RJ-45(LED*2) *RJ-11(Pass Through) *CRT *COMPOSITE Video Out *TVOUT *DVI *LINE IN

P33

*LINE OUT

Power OK CKT.

P35

4 4

Power On/Off CKT.

P32

TPM1.2 SLB9635TT

P36

Touch Pad CONN.

P38 P38

SMSC KBC 1070

P37

Int.KBD

SMSC Super I/O

LPC47N217

COM1 LPT ( Docking ) ( Docking )

P33 P33

P35

*PCI-E x2 *Serial Port *Parallel Port *PS/2 x2 *USB x2 *DC JACK

DC/DC Interface CKT.

P34

TrackPoint CONN.

P38

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2006/09/25 2006/09/25

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

Block Diagram

LA3262P_DIS__M64

257Tuesday, August 21, 2007

Voltage Rails

power plane

State

S3/M1

S5 S4/AC

S5 S4/ Battery only

S5 S4/AC & Battery don't exist

1 1

PCI Devices

EXTERNAL

CARD BUS & 1394

DMA Channel DMA0 DMA1 DMA2 DMA3 DMA4 DMA5 DMA6 DMA7

USB PORT#

O MEANS ON X MEANS OFF

+B LDO3 LDO5

O O O O

Destination 0 1 2 3 4 5 6 7 8 9

Walk-up0 (Right side)

Fingerprint

Reserve

WWAN

Walk-up1 (Left Side)

Walk-up2 (Left Side)

Bluetooth

Reserve

Docking

+5VS +3VS +2.5VS +1.8VS

+5VALW +3VALW

O O O

+1.8V

+5V

+0.9V

+1.5VS +1.25VS +VGA_CORE +CPU_CORE +VCCP

O O

X XX X

XXX

IDSEL# REQ/GNT# PIRQ AD22 2 C,D,E,G

Device MODEM / LAN ECP FLOPPY DISK AUDIO (Cascade) Unused Unused Unused

+3VM +1.05VM

+1.25VM

O O O

X X

CLOCK

O O O

X X

IRQ

0 1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16

21 22

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Device

System Timer

Keyboard

N/A

Serial port (COM2),LAN/Modem

Serial port (COM1)

Audio/VGA

Floppy

Parallel port

System CMOS/Real-time clock

Microsoft ACPI

N/A,Momem,LAN

Mass strorage control/ PCI simple communication control

synactic PS2 port GlidePAD

Numeric Data Process

Primary IDE interface,HDD

Secondary IDE innterface,CD-ROM

Mobile Intel Crestline Express Chipset Family Microsoft UAA Bus Driver for High Definition Audio Intel 82801H (ICH8 Family) PCI Express Root Port -27D0 Broadcom NetXtreme Gigabit Ethernet

Intel 82801H (ICH8 Family)PCI Express Root Port - 27D2 Broadcom 802.11b/g WLAN Intel 82801H (ICH8 Family)USB Universal Host Controll Intel 82801H (ICH8 Family)USB Universal Host Controll Ricoh R5C853 Cardbus Control Ricoh R5C853 Integrates FlashMedia Control Ricoh R5C853 Gemcore based SmartCard Control Intel 82801H (ICH8 Family)PCI Express Root Port - 27D6 Intel 82801H (ICH8 Family)USB Universal Host Controll

Intel 82801H (ICH8 Family)USB Universal Host Controll Intel 82801H (ICH8 Family)USB2 Enhanced Host Controll

Intel 82801H (ICH8 Family)USB Universal Host Controll

SDA Standard Compliant SD Host Controller

HP Mobile Data Protection Sensor

Compal Secret Data

2006/09/25 2006/09/25

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

Notes List

LA3262P_DIS__M64

357Tuesday, August 21, 2007

D D

H_A#[3..16]<7>

H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16

H_NMI<25> H_SMI#<25>

R1255

56_0402_5%@

Q85

Q85 MMBT3904_SOT23

MMBT3904_SOT23

H_ADSTB#0 H_REQ#0

H_REQ#1 H_REQ#2

H_REQ#4

H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 H_A#32 H_A#33 H_A#34 H_A#35 H_ADSTB#1

H_A20M# H_FERR# H_IGNNE#

H_STPCLK# H_INTR H_NMI H_SMI#

OCP# <26,50>

H_ADSTB#0<7>

H_REQ#0<7> H_REQ#1<7> H_REQ#2<7> H_REQ#3<7> H_REQ#4<7>

C C

B B

A A

H_A#[17..35]<7>

H_ADSTB#1<7>

H_A20M#<25>

H_FERR#<25>

H_IGNNE#<25> H_STPCLK#<25>

H_INTR<25>

+VCCP

H_PROCHOT# OCP#

3 1

JP12A

A[3]#

A[4]#

A[5]#

A[6]#

A[7]#

A[8]#

A[9]#

A[10]#

A[11]#

A[12]#

A[13]#

A[14]#

A[15]#

A[16]#

ADSTB[0]#

REQ[0]#

REQ[1]#

REQ[2]#

REQ[3]#

REQ[4]#

A[17]#

A[18]#

A[19]#

A[20]#

A[21]#

A[22]#

A[23]#

A[24]#

A[25]#

A[26]#

A[27]#

A[28]#

A[29]#

A[30]#

A[31]#

A[32]#

AA4

A[33]#

AB2

A[34]#

AA3

A[35]#

ADSTB[1]#

A20M#

FERR#

IGNNE#

STPCLK#

LINT0

LINT1

SMI#

RSVD[01]

RSVD[02]

RSVD[03]

RSVD[04]

RSVD[05]

RSVD[06]

RSVD[07]

D22

RSVD[08]

RSVD[09]

RSVD[10]

Merom Ball-out Rev 1a

ADDR GROUP 0 ADDR GROUP 1

ADS# BNR# BPRI#

DEFER#

DRDY#

DBSY#

BR0#

IERR#

INIT#

LOCK#

CONTROL

RESET#

RS[0]# RS[1]# RS[2]#

TRDY#

HIT#

HITM#

BPM[0]# BPM[1]# BPM[2]# BPM[3]#

PRDY# PREQ#

TCK

TDI TDO TMS

TRST#

XDP/ITP SIGNALS

DBR#

THERMAL

PROCHOT#

THERMDA THERMDC

ICH

THERMTRIP#

H CLK

BCLK[0] BCLK[1]

RESERVED

conn@

H1 E2 G5

H5 F21 E1

F1 D20

B3 H4 C1

F3 F4 G3 G2

G6 E4

AD4 AD3 AD1 AC4 AC2 AC1 AC5 AA6 AB3 AB5 AB6 C20

D21

H_THERMDA_R

A24 B25

A22 A21

H_ADS#H_A#3 H_BNR# H_BPRI#

H_DEFER# H_DRDY# H_DBSY#

H_BR0# H_IERR#

H_INIT# H_LOCK# H_RESET#

H_RS#0 H_RS#1 H_RS#2 H_TRDY#H_REQ#3

H_HIT# H_HITM#

XDP_BPM#0 XDP_BPM#1 XDP_BPM#2 XDP_BPM#3 XDP_BPM#4 XDP_BPM#5 XDP_TCK XDP_TDI XDP_TDO XDP_TMS XDP_TRST#

XDP_DBRESET#

H_PROCHOT#

H_THERMTRIP#

CLK_CPU_BCLK CLK_CPU_BCLK#

H_ADS# <7> H_BNR# <7>

H_BPRI# <7>

H_DEFER# <7> H_DRDY# <7> H_DBSY# <7>

H_BR0# <7>

H_INIT# <25> H_LOCK# <7> H_RESET# <7>

H_RS#0 <7>

H_RS#1 <7>

H_RS#2 <7>

H_TRDY# <7>

H_HIT# <7> H_HITM# <7>

XDP_DBRESET# <26>

68_0402_5%

R23 0_0402_5%

1 2

R34 0_0402_5%

1 2

CLK_CPU_BCLK <15> CLK_CPU_BCLK# <15>

H_THERMDA, H_THERMDC routing together, Trace width / Spacing = 10 / 10 mil

R172

56_0402_5%

For Merom, R23 and R34 are 0ohm For Penryn, R23 and R34 are 100ohm.

H_THERMDA H_THERMDCH_THERMDC_R

H_PROCHOT# <49>

+VCCP

R410

H_THERMTRIP# <7,23,25>

11/20 Penryn support to add R23,R34

+VCCP

XDP Connector

XDP_BPM#5 XDP_BPM#4

XDP_BPM#3 XDP_BPM#2

XDP_BPM#1 XDP_BPM#0

C1099

H_PWRGOOD_R XDP_HOOK1

XDP_TCK

H_PWRGOOD_R<5>

+VCCP +VCCP

0.1U_0402_16V4Z

layout note: Change R237 to 649 ohm if using XTP to ITP adapter

JP51

GND0

OBSFN_A0

OBSFN_A1

GND2

OBSDATA_A0

OBSDATA_A1

GND4

OBSDATA_A2

OBSDATA_A3

GND6

OBSFN_B0

OBSFN_B1

GND8

OBSDATA_B0

OBSDATA_B1

GND10

OBSDATA_B2

OBSDATA_B3

GND12

PWRGOOD/HOOK0

HOOK1

VCC_OBS_AB

HOOK2

HOOK3

GND14

SDA

SCL

TCK1

TCK0

GND16

Thermal Sensor ADM1032ARMZ

0.1U_0402_16V4Z

C264

1 2

2200P_0402_50V7K

1 2

+3VS

10K_0402_5%

10K_0402_5% R229

R229

THERM#_VGA<23>

1 2

0_0402_5%

R228

SAMTE_BSH-030-01-L-D-A conn@

+3VS

C273

H_THERMDA H_THERMDC

THERM#

GND1 OBSFN_C0 OBSFN_C1

GND3

OBSDATA_C0 OBSDATA_C1

GND5

OBSDATA_C2 OBSDATA_C3

GND7 OBSFN_D0 OBSFN_D1

GND9

OBSDATA_D0 OBSDATA_D1

GND11 OBSDATA_D2 OBSDATA_D3

GND13

ITPCLK/HOOK4

ITPCLK#/HOOK5

VCC_OBS_CD

RESET#/HOOK6

DBR#/HOOK7

GND15

TD0

TRST#

TDI

TMS

GND17

U16

VDD

D+

DTHERM#4GND

ADM1032ARMZ-2REEL_MSOP8

Address:100_1100

R243

XDP_DBRESET#_R

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60

XDP_TDI XDP_TMS XDP_TDO XDP_BPM#5 XDP_HOOK1

XDP_TRST# XDP_TCK

CLK_CPU_XDP CLK_CPU_XDP#

XDP_TDO XDP_TRST# XDP_TDI XDP_TMS XDP_PRE

1K_0402_1%

1 2

200_0402_1%

R1433 0_0402_5%R1433 0_0402_5%

1 2

R243

1K_0402_5%@

1 2

R143 54.9_0402_1%

1 2

R236 54.9_0402_1%

1 2

R1670 54.9_0402_1%

1 2

R241 54.9_0402_1%

1 2

R1430 54.9_0402_1%@ R1430 54.9_0402_1%@

1 2

R237 51_0402_1%

1 2

R239 54.9_0402_1%

1 2

H_RESET#H_RESET#_R

R1431

XDP_DBRESET#XDP_DBRESET#_R

R1432

1K_0402_5%@

Place R1431 within 200ps (~1") to CPU

R227

R227 10K_0402_5%

ICH_SM_CLK ICH_SM_DA

10K_0402_5%

1 2

THERM_SCI# <23,26>

SCLK

SDATA

ALERT#

ICH_SM_CLK

ICH_SM_DA

THERM_SCI#

6 5

ICH_SM_CLK<19,23,26,31>

ICH_SM_DA<19,23,26,31>

0802 (R1A) add for VGA thermal function

PWM Fan Control circuit

0308 change design

+3VS

conn@

U24

FAN_PWM<37>

THERM#

1 2

0_0402_5%

R230

1 2

+3VS

R232

R232 10K_0402_5%

10K_0402_5%

INB

INA

TC7SH00FU_SSOP5

+5VS

conn@

JP8

ACES_85204-03001

+3VS

+VCCP

CLK_CPU_XDP <15> CLK_CPU_XDP# <15>

4 5

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2006/09/25 2006/09/25

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

Merom(1/3)-AGTL+/XDP

LA3262P_DIS__M64

457Tuesday, August 21, 2007

H_D#[0..15]<7>

D D

H_DSTBN#0<7> H_DSTBP#0<7>

H_DINV#0<7>

H_D#[16..31]<7>

C C

H_DSTBN#1<7> H_DSTBP#1<7>

H_DINV#1<7>

R1264 1K_0402_5%@R1264 1K_0402_5%@

1 2

R1265 1K_0402_5%@R1265 1K_0402_5%@

1 2

C1101 0.1U_0402_16V4Z@C1101 0.1U_0402_16V4Z@

1 2

CPU_BSEL0<15> CPU_BSEL1<15> CPU_BSEL2<15>

T1T1 T2T2

T3T3

H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 H_DSTBN#0 H_DSTBP#0 H_DINV#0

H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31 H_DSTBN#1 H_DSTBP#1 H_DINV#1 H_DINV#3

V_CPU_GTLREF

TEST1 TEST2 TEST3 TEST4 TEST5 TEST6

CPU_BSEL0 H_PWRGOOD CPU_BSEL1 CPU_BSEL2

JP12B

E22

D[0]#

F24

D[1]#

E26

D[2]#

G22

D[3]#

F23

D[4]#

G25

D[5]#

E25

D[6]#

E23

D[7]#

K24

D[8]#

G24

D[9]#

J24

D[10]#

J23

D[11]#

H22

D[12]#

F26

D[13]#

K22

D[14]#

H23

D[15]#

J26

DSTBN[0]#

H26

DSTBP[0]#

H25

DINV[0]#

N22

D[16]#

K25

D[17]#

P26

D[18]#

R23

D[19]#

L23

D[20]#

M24

D[21]#

L22

D[22]#

M23

D[23]#

P25

D[24]#

P23

D[25]#

P22

D[26]#

T24

D[27]#

R24

D[28]#

L25

D[29]#

T25

D[30]#

N25

D[31]#

L26

DSTBN[1]#

M26

DSTBP[1]#

N24

DINV[1]#

AD26

GTLREF

C23

TEST1

D25

TEST2

C24

TEST3

AF26

TEST4

AF1

TEST5

A26

TEST6

B22

BSEL[0]

B23

BSEL[1]

C21

BSEL[2]

Merom Ball-out Rev 1a

conn@

DATA GRP 1

MISC

DATA GRP 0

D[32]# D[33]# D[34]# D[35]# D[36]# D[37]# D[38]# D[39]# D[40]# D[41]# D[42]# D[43]# D[44]# D[45]#

DATA GRP 2DATA GRP 3

D[46]#

D[47]# DSTBN[2]# DSTBP[2]#

DINV[2]#

D[48]#

D[49]#

D[50]#

D[51]#

D[52]#

D[53]#

D[54]#

D[55]#

D[56]#

D[57]#

D[58]#

D[59]#

D[60]#

D[61]#

D[62]#

D[63]# DSTBN[3]# DSTBP[3]#

DINV[3]# COMP[0]

COMP[1] COMP[2] COMP[3]

DPRSTP#

DPSLP# DPWR#

PWRGOOD

SLP#

PSI#

Y22 AB24 V24 V26 V23 T22 U25 U23 Y25 W22 Y23 W24 W25 AA23 AA24 AB25 Y26 AA26 U22

AE24 AD24 AA21 AB22 AB21 AC26 AD20 AE22 AF23 AC25 AE21 AD21 AC22 AD23 AF22 AC23 AE25 AF24 AC20

R26 U26 AA1 Y1

E5 B5 D24 D6 D7 AE6

H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 H_DSTBN#2 H_DSTBP#2 H_DINV#2

H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63 H_DSTBN#3 H_DSTBP#3

COMP0 COMP1 COMP2 COMP3

H_DPRSTP# H_DPSLP# H_DPWR#

H_CPUSLP# H_PSI#

R1436

1K_0402_5%

H_PWRGOOD_R

layout note: Route TEST3 & TEST5 traces on ground referenced layer to the TPs

CPU_BSEL CPU_BSEL2 CPU_BSEL1

166

B B

200

CPU_BSEL0

H_D#[32..47] <7>

H_DSTBN#2 <7> H_DSTBP#2 <7> H_DINV#2 <7> H_D#[48..63] <7>

H_DSTBN#3 <7> H_DSTBP#3 <7> H_DINV#3 <7>

H_DPRSTP# <7,25,49>

H_DPSLP# <25> H_DPWR# <7> H_PWRGOOD <25>

H_CPUSLP# <7> H_PSI# <49>

H_PWRGOOD_R <4>

R245

54.9_0402_1%

R244

27.4_0402_1%

R355

R1220

54.9_0402_1%

27.4_0402_1%

Resistor placed within

0.5" of CPU pin.Trace should be at least 25 mils away from any other toggling signal. COMP[0,2] trace width is 18 mils. COMP[1,3] trace width is 4 mils.

+VCC_CORE +VCC_CORE

JP12C

VCC[001]

VCC[002]

A10

VCC[003]

A12

VCC[004]

A13

VCC[005]

A15

VCC[006]

A17

VCC[007]

A18

VCC[008]

A20

VCC[009]

VCC[010]

VCC[011]

B10

VCC[012]

B12

VCC[013]

B14

VCC[014]

B15

VCC[015]

B17

VCC[016]

B18

VCC[017]

B20

VCC[018]

VCC[019]

C10

VCC[020]

C12

VCC[021]

C13

VCC[022]

C15

VCC[023]

C17

VCC[024]

C18

VCC[025]

VCC[026]

D10

VCC[027]

D12

VCC[028]

D14

VCC[029]

D15

VCC[030]

D17

VCC[031]

D18

VCC[032]

VCC[033]

VCC[034]

E10

VCC[035]

E12

VCC[036]

E13

VCC[037]

E15

VCC[038]

E17

VCC[039]

E18

VCC[040]

E20

VCC[041]

VCC[042]

VCC[043]

F10

VCC[044]

F12

VCC[045]

F14

VCC[046]

F15

VCC[047]

F17

VCC[048]

F18

VCC[049]

F20

VCC[050]

AA7

VCC[051]

AA9

VCC[052]

AA10

VCC[053]

AA12

VCC[054]

AA13

VCC[055]

AA15

VCC[056]

AA17

VCC[057]

AA18

VCC[058]

AA20

VCC[059]

AB9

VCC[060]

AC10

VCC[061]

AB10

VCC[062]

AB12

VCC[063]

AB14

VCC[064]

AB15

VCC[065]

AB17

VCC[066]

AB18

VCC[067]

Merom Ball-out Rev 1a

conn@

VCC[068] VCC[069] VCC[070] VCC[071] VCC[072] VCC[073] VCC[074] VCC[075] VCC[076] VCC[077] VCC[078] VCC[079] VCC[080] VCC[081] VCC[082] VCC[083] VCC[084] VCC[085] VCC[086] VCC[087] VCC[088] VCC[089] VCC[090] VCC[091] VCC[092] VCC[093] VCC[094] VCC[095] VCC[096] VCC[097] VCC[098] VCC[099] VCC[100]

VCCP[01] VCCP[02] VCCP[03] VCCP[04] VCCP[05] VCCP[06] VCCP[07] VCCP[08] VCCP[09] VCCP[10] VCCP[11] VCCP[12] VCCP[13] VCCP[14] VCCP[15] VCCP[16]

VCCA[01] VCCA[02]

VID[0] VID[1] VID[2] VID[3] VID[4] VID[5] VID[6]

VCCSENSE

VSSSENSE

AB20 AB7 AC7 AC9 AC12 AC13 AC15 AC17 AC18 AD7 AD9 AD10 AD12 AD14 AD15 AD17 AD18 AE9 AE10 AE12 AE13 AE15 AE17 AE18 AE20 AF9 AF10 AF12 AF14 AF15 AF17 AF18 AF20

R1434 0_0402_5%

G21 V6

R1435 0_0402_5%

J6 K6 M6 J21 K21 M21 N21 N6 R21 R6 T21 T6 V21 W21

B26 C26

AD6 AF5 AE5 AF4 AE3 AF3 AE2

VCCSENSE

AF7

VSSSENSE

AE7

Length match within 25 mils.

+VCCP

12 12

C1100

CPU_VID0 <49> CPU_VID1 <49> CPU_VID2 <49> CPU_VID3 <49> CPU_VID4 <49> CPU_VID5 <49> CPU_VID6 <49>

VCCSENSE <49>

VSSSENSE <49>

330U_D2E_2.5VM_R15

0228 change value

C520

C531

10U_0805_10V4Z

Near pin B26

+1.5VS

0.01U_0402_16V7K

The trace width/space/other is 20/7/25.

+VCC_CORE

1 2

R1269

R1269 100_0402_1%

100_0402_1%

R1270

R1270 100_0402_1%

100_0402_1%

VCCSENSE

VSSSENSE

V_CPU_GTLREF

+VCCP

R1268

R1268 1K_0402_1%

1K_0402_1%

R1271

R1271 2K_0402_1%

2K_0402_1%

Close to CPU pin AD26 within 500mils.

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2006/09/25 2006/09/25

Compal Secret Data

Deciphered Date

Close to CPU pin within 500mils.

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

Merom(2/3)-AGTL+/PWR

LA3262P_DIS__M64

557Tuesday, August 21, 2007

Place these capacitors on L8

D D

C C

B B

JP12D

VSS[001]

VSS[002]

A11

VSS[003]

A14

VSS[004]

A16

VSS[005]

A19

VSS[006]

A23

VSS[007]

AF2

VSS[008]

VSS[009]

VSS[010]

B11

VSS[011]

B13

VSS[012]

B16

VSS[013]

B19

VSS[014]

B21

VSS[015]

B24

VSS[016]

VSS[017]

VSS[018]

C11

VSS[019]

C14

VSS[020]

C16

VSS[021]

C19

VSS[022]

VSS[023]

C22

VSS[024]

C25

VSS[025]

VSS[026]

VSS[027]

VSS[028]

D11

VSS[029]

D13

VSS[030]

D16

VSS[031]

D19

VSS[032]

D23

VSS[033]

D26

VSS[034]

VSS[035]

VSS[036]

VSS[037]

E11

VSS[038]

E14

VSS[039]

E16

VSS[040]

E19

VSS[041]

E21

VSS[042]

E24

VSS[043]

VSS[044]

VSS[045]

F11

VSS[046]

F13

VSS[047]

F16

VSS[048]

F19

VSS[049]

VSS[050]

F22

VSS[051]

F25

VSS[052]

VSS[053]

VSS[054]

G23

VSS[055]

G26

VSS[056]

VSS[057]

VSS[058]

H21

VSS[059]

H24

VSS[060]

VSS[061]

VSS[062]

J22

VSS[063]

J25

VSS[064]

VSS[065]

VSS[066]

K23

VSS[067]

K26

VSS[068]

VSS[069]

VSS[070]

L21

VSS[071]

L24

VSS[072]

VSS[073]

VSS[074]

M22

VSS[075]

M25

VSS[076]

VSS[077]

VSS[078]

N23

VSS[079]

N26

VSS[080] VSS[081]P3VSS[162]

Merom Ball-out Rev 1a

conn@

VSS[082] VSS[083] VSS[084] VSS[085] VSS[086] VSS[087] VSS[088] VSS[089] VSS[090] VSS[091] VSS[092] VSS[093] VSS[094] VSS[095] VSS[096] VSS[097] VSS[098] VSS[099] VSS[100] VSS[101] VSS[102] VSS[103] VSS[104] VSS[105] VSS[106] VSS[107] VSS[108] VSS[109] VSS[110] VSS[111] VSS[112] VSS[113] VSS[114] VSS[115] VSS[116] VSS[117] VSS[118] VSS[119] VSS[120] VSS[121] VSS[122] VSS[123] VSS[124] VSS[125] VSS[126] VSS[127] VSS[128] VSS[129] VSS[130] VSS[131] VSS[132] VSS[133] VSS[134] VSS[135] VSS[136] VSS[137] VSS[138] VSS[139] VSS[140] VSS[141] VSS[142] VSS[143] VSS[144] VSS[145] VSS[146] VSS[147] VSS[148] VSS[149] VSS[150] VSS[151] VSS[152] VSS[153] VSS[154] VSS[155] VSS[156] VSS[157] VSS[158] VSS[159] VSS[160] VSS[161]

VSS[163]

P6 P21 P24 R2 R5 R22 R25 T1 T4 T23 T26 U3 U6 U21 U24 V2 V5 V22 V25 W1 W4 W23 W26 Y3 Y6 Y21 Y24 AA2 AA5 AA8 AA11 AA14 AA16 AA19 AA22 AA25 AB1 AB4 AB8 AB11 AB13 AB16 AB19 AB23 AB26 AC3 AC6 AC8 AC11 AC14 AC16 AC19 AC21 AC24 AD2 AD5 AD8 AD11 AD13 AD16 AD19 AD22 AD25 AE1 AE4 AE8 AE11 AE14 AE16 AE19 AE23 AE26 A2 AF6 AF8 AF11 AF13 AF16 AF19 AF21 A25 AF25

(North side,Secondary Layer)

Place these capacitors on L8 (North side,Secondary Layer)

Place these capacitors on L8 (Sorth side,Secondary Layer)

330U_D2E_2.5VM_R7

+VCCP

C940

0.1U_0402_10V6K

+VCC_CORE

C931

+VCC_CORE

C899

C899 10U_0805_6.3V6M

10U_0805_6.3V6M

+VCC_CORE

C907

C907 10U_0805_6.3V6M

10U_0805_6.3V6M

+VCC_CORE

C915

C915 10U_0805_6.3V6M

10U_0805_6.3V6M

+VCC_CORE

C923

C923 10U_0805_6.3V6M

10U_0805_6.3V6M

Near CPU CORE regulator

330U_D2E_2.5VM_R7

C933

C932

330U_D2E_2.5VM_R7

C941

0.1U_0402_10V6K

C900

C900 10U_0805_6.3V6M

10U_0805_6.3V6M

C908

C908 10U_0805_6.3V6M

10U_0805_6.3V6M

C916

C916 10U_0805_6.3V6M

10U_0805_6.3V6M

C924

C924 10U_0805_6.3V6M

10U_0805_6.3V6M

C935

330U_D2E_2.5VM_R7

C942

0.1U_0402_10V6K

C901

C901 10U_0805_6.3V6M

10U_0805_6.3V6M

C909

C909 10U_0805_6.3V6M

10U_0805_6.3V6M

C917

C917 10U_0805_6.3V6M

10U_0805_6.3V6M

C925

C925 10U_0805_6.3V6M

10U_0805_6.3V6M

330U_D2E_2.5VM_R7

C936

C937

330U_D2E_2.5VM_R7

C943

0.1U_0402_10V6K

C902

C902 10U_0805_6.3V6M

10U_0805_6.3V6M

C910

C910 10U_0805_6.3V6M

10U_0805_6.3V6M

C918

C918 10U_0805_6.3V6M

10U_0805_6.3V6M

C926

C926 10U_0805_6.3V6M

10U_0805_6.3V6M

ESR <= 1.5m ohm Capacitor > 1980uF

C944

0.1U_0402_10V6K

C903

C903 10U_0805_6.3V6M

10U_0805_6.3V6M

C911

C911 10U_0805_6.3V6M

10U_0805_6.3V6M

C919

C919 10U_0805_6.3V6M

10U_0805_6.3V6M

C927

C927 10U_0805_6.3V6M

10U_0805_6.3V6M

Place these inside socket cavity on L8 (North side Secondary)

C945

0.1U_0402_10V6K

C904

C904 10U_0805_6.3V6M

10U_0805_6.3V6M

C912

C912 10U_0805_6.3V6M

10U_0805_6.3V6M

C920

C920 10U_0805_6.3V6M

10U_0805_6.3V6M

C928

C928 10U_0805_6.3V6M

10U_0805_6.3V6M

C905

C905 10U_0805_6.3V6M

10U_0805_6.3V6M

C913

C913 10U_0805_6.3V6M

10U_0805_6.3V6M

C921

C921 10U_0805_6.3V6M

10U_0805_6.3V6M

C929

C929 10U_0805_6.3V6M

10U_0805_6.3V6M

C906

C906 10U_0805_6.3V6M

10U_0805_6.3V6M

C914

C914 10U_0805_6.3V6M

10U_0805_6.3V6M

C922

C922 10U_0805_6.3V6M

10U_0805_6.3V6M

C930

C930 10U_0805_6.3V6M

10U_0805_6.3V6M

Mid Frequence Decoupling

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2006/09/25 2006/09/25

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

Merom(3/3)-GND&Bypass

LA3262P_DIS__M64

657Tuesday, August 21, 2007

U15A

M10

W10

AD12

AC14 AD11 AC11

AG3

AJ14

AE11 AH12

AH13

G2 G7 M6 H7 H3 G4

F3 N8 H2

N12

N9 H5

P13

K9 M2

V4 M3

J1 N5 N3 W6 W9 N2

P4 W3 N1

AE3 AD9 AC9 AC7

AB2 AD7 AB1

AC6 AE2 AC5

AJ9 AH8

AE9

AJ5 AH5 AJ6 AE7 AJ7 AJ2 AE5 AJ3 AH2

B3 C2

W1 W2

U15A

H_D#_0 H_D#_1 H_D#_2 H_D#_3 H_D#_4 H_D#_5 H_D#_6 H_D#_7 H_D#_8 H_D#_9 H_D#_10 H_D#_11 H_D#_12 H_D#_13 H_D#_14 H_D#_15 H_D#_16 H_D#_17 H_D#_18 H_D#_19 H_D#_20 H_D#_21 H_D#_22 H_D#_23 H_D#_24 H_D#_25 H_D#_26 H_D#_27 H_D#_28 H_D#_29 H_D#_30 H_D#_31 H_D#_32 H_D#_33 H_D#_34 H_D#_35 H_D#_36 H_D#_37 H_D#_38 H_D#_39 H_D#_40 H_D#_41 H_D#_42 H_D#_43 H_D#_44 H_D#_45 H_D#_46 H_D#_47 H_D#_48 H_D#_49 H_D#_50 H_D#_51 H_D#_52 H_D#_53 H_D#_54 H_D#_55 H_D#_56 H_D#_57 H_D#_58 H_D#_59 H_D#_60 H_D#_61 H_D#_62 H_D#_63

H_SWING H_RCOMP

H_SCOMP H_SCOMP#

H_CPURST# H_CPUSLP#

H_AVREF H_DVREF

CRESTLINE_1p0

HOST

H_ADSTB#_0 H_ADSTB#_1

H_DEFER#

HPLL_CLK

HPLL_CLK#

H_DPWR#

H_DINV#_0 H_DINV#_1 H_DINV#_2 H_DINV#_3

H_DSTBN#_0 H_DSTBN#_1 H_DSTBN#_2 H_DSTBN#_3

H_DSTBP#_0 H_DSTBP#_1 H_DSTBP#_2 H_DSTBP#_3

H_REQ#_0 H_REQ#_1

H_REQ#_2 H_REQ#_3

H_REQ#_4

H_D#[0..63]<5>

D D

C C

+VCCP

R1196

R1197

54.9_0402_1%

H_RESET#<4>

H_CPUSLP#<5>

B B

H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31 H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57

H_D#59 H_D#60 H_D#61 H_D#62 H_D#63

H_SWNG H_RCOMP

H_SCOMP H_SCOMP#

H_RESET# H_CPUSLP#

H_VREF

layout note:

Route H_SCOMP and H_SCOMP# with trace width, spacing and impedance (55 ohm) same as FSB data traces

Layout Note: H_RCOMP / H_VREF / H_SWNG

trace width and spacing is 10/20

+VCCP

R1206

R1210

221_0603_1%

100_0402_1%

H_SWNGH_VREF

C896

0.1U_0402_16V4Z

+VCCP

1K_0402_1%

R1208

0.1U_0402_16V4Z

A A

R1212

C60

2K_0402_1%

R1199

24.9_0402_1%

H_RCOMP

Near B3 pinwithin 100 mils from NB

H_A#_3 H_A#_4 H_A#_5 H_A#_6 H_A#_7 H_A#_8

H_A#_9 H_A#_10 H_A#_11 H_A#_12 H_A#_13 H_A#_14 H_A#_15 H_A#_16 H_A#_17 H_A#_18 H_A#_19 H_A#_20 H_A#_21 H_A#_22 H_A#_23 H_A#_24 H_A#_25 H_A#_26 H_A#_27 H_A#_28 H_A#_29 H_A#_30 H_A#_31 H_A#_32 H_A#_33 H_A#_34 H_A#_35

H_ADS#

H_BNR#

H_BPRI#

H_BREQ# H_DBSY#

H_DRDY#

H_HIT# H_HITM#

H_LOCK# H_TRDY#

H_RS#_0 H_RS#_1 H_RS#_2

J13 B11 C11 M11 C15 F16 L13 G17 C14 K16 B13 L16 J17 B14 K19 P15 R17 B16 H20 L19 D17 M17 N16 J19 B18 E19 B17 B15 E17 C18 A19 B19 N19

G12 H17 G20 C8 E8 F12 D6 C10 AM5 AM7 H8 K7 E4 C6 G10 B7

K5 L2 AD13 AE13

M7 K3 AD2 AH11

L7 K2 AC2 AJ10

M14 E13 A11 H13 B12

E12 D7 D8

V_DDR_MCH_REF<13,14,48>

H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16 H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 H_A#32 H_A#33 H_A#34 H_A#35

H_ADS# H_ADSTB#0 H_ADSTB#1 H_BNR# H_BPRI# H_BR0# H_DEFER# H_DBSY# CLK_MCH_BCLK CLK_MCH_BCLK# H_DPWR# H_DRDY# H_HIT# H_HITM# H_LOCK# H_TRDY#

H_DINV#0 H_DINV#1 H_DINV#2 H_DINV#3

H_DSTBN#0H_D#58 H_DSTBN#1 H_DSTBN#2 H_DSTBN#3

H_DSTBP#0 H_DSTBP#1 H_DSTBP#2 H_DSTBP#3

H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4

H_RS#0 H_RS#1 H_RS#2

VGATE<26,37>

Layout Note: V_DDR_MCH_REF trace width and spacing is 20/20.

H_A#[3..35] <4>

H_ADS# <4> H_ADSTB#0 <4> H_ADSTB#1 <4> H_BNR# <4> H_BPRI# <4> H_BR0# <4> H_DEFER# <4> H_DBSY# <4> CLK_MCH_BCLK <15> CLK_MCH_BCLK# <15> H_DPWR# <5> H_DRDY# <4> H_HIT# <4> H_HITM# <4> H_LOCK# <4> H_TRDY# <4>

H_DINV#0 <5> H_DINV#1 <5> H_DINV#2 <5> H_DINV#3 <5>

H_DSTBN#0 <5> H_DSTBN#1 <5> H_DSTBN#2 <5> H_DSTBN#3 <5>

H_DSTBP#0 <5> H_DSTBP#1 <5> H_DSTBP#2 <5> H_DSTBP#3 <5>

H_REQ#0 <4> H_REQ#1 <4> H_REQ#2 <4> H_REQ#3 <4> H_REQ#4 <4>

H_RS#0 <4> H_RS#1 <4> H_RS#2 <4>

R1484 0_0402_5%R1484 0_0402_5%

V_DDR_MCH_REF

C895

0.1U_0402_16V4Z

C1103

C1105

R1439

10K_0402_5%

R1440

10K_0402_5%

R1441

10K_0402_5%

CFG5<9> CFG7<9>

CFG8<9> CFG9<9>

CFG12<9> CFG13<9>

T109T109 T110T110

CFG16<9>

T111T111

T112T112

CFG19<9> CFG20<9>

H_DPRSTP#<5,25,49> PM_EXTTS#0<13> PM_EXTTS#1<14>

1 2

DPRSLPVR<26,49>

+1.8V

0.01U_0402_25V7K

R1439

T104T104 T105T105

T106T106

T107T107 T108T108

0_0402_5%

R1437

R1437 1K_0402_1%

1K_0402_1%

R31

3.01K_0402_1%

R1438

R1438 1K_0402_1%

1K_0402_1%

DDR_A_MA14<13> DDR_B_MA14<14>

+3VS

MCH_CLKSEL0 MCH_CLKSEL1 MCH_CLKSEL2 CFG3 CFG4 CFG5 CFG6 CFG7 CFG8 CFG9 CFG10 CFG11 CFG12 CFG13 CFG14 CFG15 CFG16 CFG17 CFG18 CFG19 CFG20

PM_BMBUSY# H_DPRSTP# PM_EXTTS#0 PM_EXTTS#1 PM_POK_R PLT_RST#_R THERM_TRIP# DPRSLPVR

2.2U_0603_6.3V4Z

C1102

SMRCOMP_VOH

SMRCOMP_VOL

PM_EXTTS#0

PM_EXTTS#1

CLKREQ#_B DMI_TXN0

C1102

C1104

2.2U_0603_6.3V4Z

MCH_CLKSEL0<15> MCH_CLKSEL1<15> MCH_CLKSEL2<15>

PM_BMBUSY#<26>

0904 add

H_THERMTRIP#<4,23,25>

PM_POK_R

11/20 Add R2 for Intel ES2 chipset

2007,0125 change

+1.8V

R1201

1K_0402_1%@

R1204

1K_0402_1%

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

THERM_TRIP#

C1626

0.1U_0402_16V4Z

R1446

100_0402_5%

2006/09/25 2006/09/25

U15B

P36

RSVD1

P37

RSVD2

R35

RSVD3

N35

RSVD4

AR12

RSVD5

AR13

RSVD6

AM12

RSVD7

AN13

RSVD8

J12

RSVD9

AR37

RSVD10

AM36

RSVD11

AL36

RSVD12

AM37

RSVD13

D20

RSVD14

H10

RSVD20

B51

RSVD21

BJ20

RSVD22

BK22

RSVD23

BF19

RSVD24

BH20

RSVD25

BK18

RSVD26

BJ18

RSVD27

BF23

RSVD28

BG23

RSVD29

BC23

RSVD30

BD24

RSVD31

BJ29

RSVD32

BE24

RSVD33

BH39

RSVD34

AW20

RSVD35

BK20

RSVD36

C48

RSVD37

D47

RSVD38

B44

RSVD39

C44

RSVD40

A35

RSVD41

B37

RSVD42

B36

RSVD43

B34

RSVD44

C34

RSVD45

P27

CFG_0

N27

CFG_1

N24

CFG_2

C21

CFG_3

C23

CFG_4

F23

CFG_5

N23

CFG_6

G23

CFG_7

J20

CFG_8

C20

CFG_9

R24

CFG_10

L23

CFG_11

J23

CFG_12

E23

CFG_13

E20

CFG_14

K23

CFG_15

M20

CFG_16

M24

CFG_17

L32

CFG_18

N33

CFG_19

L35

CFG_20

G41

PM_BM_BUSY#

L39

PM_DPRSTP#

L36

PM_EXT_TS#_0

J36

PM_EXT_TS#_1

AW49

PWROK

AV20

RSTIN#

N20

THERMTRIP#

G36

DPRSLPVR

BJ51

NC_1

BK51

NC_2

BK50

NC_3

BL50

NC_4

BL49

NC_5

BL3

NC_6

BL2

NC_7

BK1

NC_8

BJ1

NC_9

NC_10

NC_11

C51

NC_12

B50

NC_13

A50

NC_14

A49

NC_15

BK2

NC_16

CRESTLINE_1p0

R1446

PLT_RST#PLT_RST#_R

Compal Secret Data

Deciphered Date

DDR MUXINGCLK

CFGRSVD

DMI

GRAPHICS VID

MISC

PLT_RST# <24,28,36>

SM_CK_0 SM_CK_1 SM_CK_3 SM_CK_4

SM_CK#_0 SM_CK#_1 SM_CK#_3 SM_CK#_4

SM_CKE_0 SM_CKE_1 SM_CKE_3 SM_CKE_4

SM_CS#_0 SM_CS#_1 SM_CS#_2 SM_CS#_3

SM_ODT_0 SM_ODT_1 SM_ODT_2 SM_ODT_3

SM_RCOMP

SM_RCOMP#

SM_RCOMP_VOH

SM_RCOMP_VOL

SM_VREF_0 SM_VREF_1

DPLL_REF_CLK

DPLL_REF_CLK#

DPLL_REF_SSCLK

DPLL_REF_SSCLK#

PEG_CLK

PEG_CLK#

DMI_RXN_0 DMI_RXN_1 DMI_RXN_2 DMI_RXN_3

DMI_RXP_0 DMI_RXP_1 DMI_RXP_2 DMI_RXP_3

DMI_TXN_0 DMI_TXN_1 DMI_TXN_2 DMI_TXN_3

DMI_TXP_0 DMI_TXP_1 DMI_TXP_2 DMI_TXP_3

GFX_VID_0 GFX_VID_1 GFX_VID_2 GFX_VID_3

GFX_VR_EN

CL_DATA

CL_PWROK

CL_RST# CL_VREF

SDVO_CTRL_CLK

SDVO_CTRL_DATA

CLK_REQ#

ICH_SYNC#

CL_CLK

TEST_1 TEST_2

For Crestline: 20ohm

M_CLK_DDR0

AV29

M_CLK_DDR1

BB23

M_CLK_DDR2

BA25

M_CLK_DDR3

AV23

M_CLK_DDR#0

AW30

M_CLK_DDR#1

BA23

M_CLK_DDR#2

AW25

M_CLK_DDR#3

AW23

DDR_CKE0_DIMMA

BE29

DDR_CKE1_DIMMA

AY32

DDR_CKE2_DIMMB

BD39

DDR_CKE3_DIMMB

BG37

DDR_CS0_DIMMA#

BG20

DDR_CS1_DIMMA#

BK16

DDR_CS2_DIMMB#

BG16

DDR_CS3_DIMMB#

BE13

M_ODT0

BH18

M_ODT1

BJ15

M_ODT2

BJ14

M_ODT3

BE16

SMRCOMP

BL15

SMRCOMP#

BK14

SMRCOMP_VOH

BK31

SMRCOMP_VOL

BL31 AR49

V_DDR_MCH_REF

AW4

B42 C42 H48 H47

CLK_MCH_3GPLL

K44

CLK_MCH_3GPLL#

K45

AN47

DMI_TXN1

AJ38

DMI_TXN2

AN42

DMI_TXN3

AN46

DMI_TXP0

AM47

DMI_TXP1

AJ39

DMI_TXP2

AN41

DMI_TXP3

AN45

DMI_RXN0

AJ46

DMI_RXN1

AJ41

DMI_RXN2

AM40

DMI_RXN3

AM44

DMI_RXP0

AJ47

DMI_RXP1

AJ42

DMI_RXP2

AM39

DMI_RXP3

AM43

E35 A39 C38 B39 E36

CL_CLK0

AM49

CL_DATA0

AK50

M_PWROK

AT43

CL_RST#

AN49

CL_VREF CL_VREF

AM50

H35 K36

CLKREQ#_B

G39

MCH_ICH_SYNC#

G40

A37 R32

R1444

20K_0402_5%

Title

CRESTLINE(1/6)-AGTL+/DMI/DDR2

Size Document Number Rev

Custom

LA3262P_DIS__M64

Date: Sheet

For Calero: 80.6ohm

M_CLK_DDR0 <13> M_CLK_DDR1 <13> M_CLK_DDR2 <14> M_CLK_DDR3 <14>

M_CLK_DDR#0 <13> M_CLK_DDR#1 <13> M_CLK_DDR#2 <14> M_CLK_DDR#3 <14>

DDR_CKE0_DIMMA <13> DDR_CKE1_DIMMA <13> DDR_CKE2_DIMMB <14> DDR_CKE3_DIMMB <14>

DDR_CS0_DIMMA# <13> DDR_CS1_DIMMA# <13> DDR_CS2_DIMMB# <14> DDR_CS3_DIMMB# <14>

M_ODT0 <13> M_ODT1 <13> M_ODT2 <14> M_ODT3 <14>

CLK_MCH_3GPLL <15> CLK_MCH_3GPLL# <15>

DMI_TXN0 <26> DMI_TXN1 <26> DMI_TXN2 <26> DMI_TXN3 <26>

DMI_TXP0 <26> DMI_TXP1 <26> DMI_TXP2 <26> DMI_TXP3 <26>

DMI_RXN0 <26> DMI_RXN1 <26> DMI_RXN2 <26> DMI_RXN3 <26>

DMI_RXP0 <26> DMI_RXP1 <26> DMI_RXP2 <26> DMI_RXP3 <26>

CL_CLK0 <26> CL_DATA0 <26> M_PWROK <26,41> CL_RST# <26>

0.1U_0402_16V4Z

CLKREQ#_B <15> MCH_ICH_SYNC# <26>

R1445

R1445 0_0402_5%

0_0402_5%

Compal Electronics, Inc.

20_0402_1%

R1194

R1194 R1195 20_0402_1%

R1195 20_0402_1%

C1106

+1.25VM_AXD

757Tuesday, August 21, 2007

12 12

R1442

R1442 1K_0402_1%

1K_0402_1%

R1443

R1443 392_0402_1%

392_0402_1%

+1.8V

D D

DDR_A_D[0..63]<13>

C C

B B

DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8

DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15 DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63

AR43

AW44

BA45 AY46 AR41 AR45 AT42

AW47

BB45 BF48 BG47

BJ45 BB47 BG50 BH49 BE45

AW43

BE44 BG42 BE40 BF44 BH45 BG40 BF40 AR40

AW40

AT39

AW36 AW41

AY41 AV38 AT38 AV13 AT13

AW11

AV11 AU15 AT11 BA13 BA11 BE10 BD10

BG10

AW9

AM8

AN10

AN9 AM9

AN11

BD8 AY9

BD7 BB9 BB5 AY7 AT5 AT7 AY6 BB7 AR5 AR8 AR9 AN3

AT9

U15D

SA_DQ_0 SA_DQ_1 SA_DQ_2 SA_DQ_3 SA_DQ_4 SA_DQ_5 SA_DQ_6 SA_DQ_7 SA_DQ_8 SA_DQ_9 SA_DQ_10 SA_DQ_11 SA_DQ_12 SA_DQ_13 SA_DQ_14 SA_DQ_15 SA_DQ_16 SA_DQ_17 SA_DQ_18 SA_DQ_19 SA_DQ_20 SA_DQ_21 SA_DQ_22 SA_DQ_23 SA_DQ_24 SA_DQ_25 SA_DQ_26 SA_DQ_27 SA_DQ_28 SA_DQ_29 SA_DQ_30 SA_DQ_31 SA_DQ_32 SA_DQ_33 SA_DQ_34 SA_DQ_35 SA_DQ_36 SA_DQ_37 SA_DQ_38 SA_DQ_39 SA_DQ_40 SA_DQ_41 SA_DQ_42 SA_DQ_43 SA_DQ_44 SA_DQ_45 SA_DQ_46 SA_DQ_47 SA_DQ_48 SA_DQ_49 SA_DQ_50 SA_DQ_51 SA_DQ_52 SA_DQ_53 SA_DQ_54 SA_DQ_55 SA_DQ_56 SA_DQ_57 SA_DQ_58 SA_DQ_59 SA_DQ_60 SA_DQ_61 SA_DQ_62 SA_DQ_63

CRESTLINE_1p0

DDR SYSTEM MEMORY A

SA_BS_0 SA_BS_1 SA_BS_2

SA_CAS#

SA_DM_0 SA_DM_1 SA_DM_2 SA_DM_3 SA_DM_4 SA_DM_5 SA_DM_6 SA_DM_7

SA_DQS_0 SA_DQS_1 SA_DQS_2 SA_DQS_3 SA_DQS_4 SA_DQS_5 SA_DQS_6

SA_DQS_7 SA_DQS#_0 SA_DQS#_1 SA_DQS#_2 SA_DQS#_3 SA_DQS#_4 SA_DQS#_5 SA_DQS#_6 SA_DQS#_7

SA_MA_0 SA_MA_1 SA_MA_2 SA_MA_3 SA_MA_4 SA_MA_5 SA_MA_6 SA_MA_7 SA_MA_8

SA_MA_9 SA_MA_10 SA_MA_11 SA_MA_12 SA_MA_13

SA_RAS#

SA_RCVEN#

SA_WE#

DDR_A_BS0

BB19 BK19 BF29

BL17 AT45

BD44 BD42 AW38 AW13 BG8 AY5 AN6

AT46 BE48 BB43 BC37 BB16 BH6 BB2 AP3 AT47 BD47 BC41 BA37 BA16 BH7 BC1 AP2

BJ19 BD20 BK27 BH28 BL24 BK28 BJ27 BJ25 BL28 BA28 BC19 BE28 BG30 BJ16

BE18 AY20

BA19

DDR_A_BS1 DDR_A_BS2

DDR_A_CAS# DDR_A_DM0

DDR_A_DM1 DDR_A_DM2 DDR_A_DM3 DDR_A_DM4 DDR_A_DM5 DDR_A_DM6 DDR_A_DM7

DDR_A_DQS0 DDR_A_DQS1 DDR_A_DQS2

DDR_A_DQS4 DDR_A_DQS5 DDR_A_DQS6 DDR_A_DQS7 DDR_A_DQS#0 DDR_A_DQS#1 DDR_A_DQS#2 DDR_A_DQS#3 DDR_A_DQS#4 DDR_A_DQS#5 DDR_A_DQS#6 DDR_A_DQS#7

DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13

DDR_A_RAS# SA_RCVEN#

DDR_A_WE#

DDR_A_BS0 <13> DDR_A_BS1 <13> DDR_A_BS2 <13>

DDR_A_CAS# <13> DDR_B_CAS# <14> DDR_A_DM[0..7] <13>

DDR_A_DQS[0..7] <13>

DDR_A_DQS#[0..7] <13>

DDR_A_MA[0..13] <13>

DDR_A_RAS# <13>

T5T5

DDR_A_WE# <13>

DDR_B_D[0..63]<14>

DDR_B_D0 DDR_B_D1 DDR_B_D2 DDR_B_D3 DDR_B_D4 DDR_B_D5 DDR_B_D6 DDR_B_D7 DDR_B_D8

DDR_B_D9 DDR_B_D10 DDR_B_D11 DDR_B_D12 DDR_B_D13 DDR_B_D14 DDR_B_D15 DDR_B_D16 DDR_B_D17 DDR_B_D18DDR_A_DQS3 DDR_B_D19 DDR_B_D20 DDR_B_D21 DDR_B_D22 DDR_B_D23 DDR_B_D24 DDR_B_D25 DDR_B_D26 DDR_B_D27 DDR_B_D28 DDR_B_D29 DDR_B_D30 DDR_B_D31 DDR_B_D32 DDR_B_D33 DDR_B_D34 DDR_B_D35 DDR_B_D36 DDR_B_D37 DDR_B_D38 DDR_B_D39 DDR_B_D40 DDR_B_D41

DDR_B_D43 DDR_B_D44 DDR_B_D45 DDR_B_D46 DDR_B_D47 DDR_B_D48 DDR_B_D49 DDR_B_D50 DDR_B_D51 DDR_B_D52 DDR_B_D53 DDR_B_D54 DDR_B_D55 DDR_B_D56 DDR_B_D57 DDR_B_D58 DDR_B_D59 DDR_B_D60 DDR_B_D61 DDR_B_D62 DDR_B_D63

AP49

AR51 AW50 AW51

AN51

AN50

AV50

AV49

BA50

BB50

BA49

BE50

BA51

AY49

BF50

BF49

BJ50 BJ44 BJ43

BL43 BK47 BK49 BK43 BK42

BJ41

BL41

BJ37

BJ36 BK41

BJ40

BL35 BK37 BK13 BE11 BK11 BC11 BC13 BE12 BC12 BG12

BJ10

BK10

BK5 BK9

BF4 BH5 BG1 BC2 BK3 BE4 BD3

BA3 BB3 AR1 AT3 AY2 AY3 AU2 AT2

BL9 BL5

BJ8 BJ6

BJ2

U15E

SB_DQ_0 SB_DQ_1 SB_DQ_2 SB_DQ_3 SB_DQ_4 SB_DQ_5 SB_DQ_6 SB_DQ_7 SB_DQ_8 SB_DQ_9 SB_DQ_10 SB_DQ_11 SB_DQ_12 SB_DQ_13 SB_DQ_14 SB_DQ_15 SB_DQ_16 SB_DQ_17 SB_DQ_18 SB_DQ_19 SB_DQ_20 SB_DQ_21 SB_DQ_22 SB_DQ_23 SB_DQ_24 SB_DQ_25 SB_DQ_26 SB_DQ_27 SB_DQ_28 SB_DQ_29 SB_DQ_30 SB_DQ_31 SB_DQ_32 SB_DQ_33 SB_DQ_34 SB_DQ_35 SB_DQ_36 SB_DQ_37 SB_DQ_38 SB_DQ_39 SB_DQ_40 SB_DQ_41 SB_DQ_42 SB_DQ_43 SB_DQ_44 SB_DQ_45 SB_DQ_46 SB_DQ_47 SB_DQ_48 SB_DQ_49 SB_DQ_50 SB_DQ_51 SB_DQ_52 SB_DQ_53 SB_DQ_54 SB_DQ_55 SB_DQ_56 SB_DQ_57 SB_DQ_58 SB_DQ_59 SB_DQ_60 SB_DQ_61 SB_DQ_62 SB_DQ_63

CRESTLINE_1p0

DDR_B_BS0

AY17

SB_BS_0 SB_BS_1 SB_BS_2

SB_CAS#

SB_DM_0 SB_DM_1 SB_DM_2 SB_DM_3 SB_DM_4 SB_DM_5 SB_DM_6 SB_DM_7

SB_DQS_0 SB_DQS_1 SB_DQS_2 SB_DQS_3 SB_DQS_4 SB_DQS_5 SB_DQS_6

SB_DQS_7 SB_DQS#_0 SB_DQS#_1 SB_DQS#_2 SB_DQS#_3 SB_DQS#_4 SB_DQS#_5 SB_DQS#_6 SB_DQS#_7

SB_MA_0 SB_MA_1 SB_MA_2 SB_MA_3 SB_MA_4 SB_MA_5 SB_MA_6 SB_MA_7 SB_MA_8

SB_MA_9 SB_MA_10 SB_MA_11 SB_MA_12 SB_MA_13

SB_RAS#

SB_RCVEN#

SB_WE#

DDR SYSTEM MEMORY B

BG18 BG36

BE17 AR50

BD49 BK45 BL39 BH12 BJ7 BF3 AW2

AT50 BD50 BK46 BK39 BJ12 BL7 BE2 AV2 AU50 BC50 BL45 BK38 BK12 BK7 BF2 AV3

BC18 BG28 BG25 AW17 BF25 BE25 BA29 BC28 AY28 BD37 BG17 BE37 BA39 BG13

AV16 AY18

BC17

DDR_B_BS1 DDR_B_BS2

DDR_B_CAS#

DDR_B_DM0 DDR_B_DM1 DDR_B_DM2 DDR_B_DM3 DDR_B_DM4 DDR_B_DM5 DDR_B_DM6 DDR_B_DM7

DDR_B_DQS0 DDR_B_DQS1 DDR_B_DQS2 DDR_B_DQS3 DDR_B_DQS4 DDR_B_DQS5 DDR_B_DQS6

DDR_B_DQS7 DDR_B_DQS#0 DDR_B_DQS#1 DDR_B_DQS#2 DDR_B_DQS#3 DDR_B_DQS#4 DDR_B_DQS#5 DDR_B_DQS#6 DDR_B_DQS#7

DDR_B_MA0 DDR_B_MA1 DDR_B_MA2 DDR_B_MA3 DDR_B_MA4 DDR_B_MA5 DDR_B_MA6 DDR_B_MA7 DDR_B_MA8

DDR_B_MA9 DDR_B_MA10DDR_B_D42 DDR_B_MA11 DDR_B_MA12 DDR_B_MA13

DDR_B_RAS#

SB_RCVEN#

DDR_B_WE#

DDR_B_BS0 <14> DDR_B_BS1 <14> DDR_B_BS2 <14>

DDR_B_DM[0..7] <14>

DDR_B_DQS[0..7] <14>

DDR_B_DQS#[0..7] <14>

DDR_B_MA[0..13] <14>

DDR_B_RAS# <14>

T4T4

DDR_B_WE# <14>

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2006/09/25 2006/09/25

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

CRESTLINE((2/6)-DDR2 A/B CH

LA3262P_DIS__M64

857Tuesday, August 21, 2007

U15C

J40

L_BKLT_CTRL

H39

L_BKLT_EN

E39

L_CTRL_CLK

E40

L_CTRL_DATA

C37

L_DDC_CLK

D35

L_DDC_DATA

K40

L_VDD_EN

L41

LVDS_IBG

L43

D D

C C

B B

N41 N40 D46 C45 D44

E42

G51

E51 F49

G50

E50 F48

G44

B47 B45

E44 A47 A45

E27

G27

K27 F27

J27

L27

M35

P33

H32 G32

K29

J29 F29 E29

K33

G35

F33

C32

E33

CRESTLINE_1p0

LVDS_VBG LVDS_VREFH LVDS_VREFL LVDSA_CLK# LVDSA_CLK LVDSB_CLK# LVDSB_CLK

LVDSA_DATA#_0 LVDSA_DATA#_1 LVDSA_DATA#_2

LVDSA_DATA_0 LVDSA_DATA_1 LVDSA_DATA_2

LVDSB_DATA#_0 LVDSB_DATA#_1 LVDSB_DATA#_2

LVDSB_DATA_0 LVDSB_DATA_1 LVDSB_DATA_2

TVA_DAC TVB_DAC TVC_DAC

TVA_RTN TVB_RTN TVC_RTN

TV_DCONSEL_0 TV_DCONSEL_1

CRT_BLUE CRT_BLUE# CRT_GREEN CRT_GREEN# CRT_RED CRT_RED#

CRT_DDC_CLK CRT_DDC_DATA CRT_HSYNC CRT_TVO_IREF CRT_VSYNC

LVDS

TV VGA

PEG_COMPI

PEG_COMPO

PEG_RX#_0 PEG_RX#_1 PEG_RX#_2 PEG_RX#_3 PEG_RX#_4 PEG_RX#_5 PEG_RX#_6 PEG_RX#_7 PEG_RX#_8

PEG_RX#_9 PEG_RX#_10 PEG_RX#_11 PEG_RX#_12 PEG_RX#_13 PEG_RX#_14 PEG_RX#_15

PEG_RX_0 PEG_RX_1 PEG_RX_2 PEG_RX_3 PEG_RX_4 PEG_RX_5 PEG_RX_6 PEG_RX_7 PEG_RX_8

PEG_RX_9 PEG_RX_10 PEG_RX_11 PEG_RX_12 PEG_RX_13 PEG_RX_14 PEG_RX_15

PEG_TX#_0 PEG_TX#_1 PEG_TX#_2 PEG_TX#_3 PEG_TX#_4 PEG_TX#_5 PEG_TX#_6 PEG_TX#_7 PEG_TX#_8 PEG_TX#_9

PEG_TX#_10

PCI-EXPRESS GRAPHICS

PEG_TX#_11 PEG_TX#_12 PEG_TX#_13 PEG_TX#_14 PEG_TX#_15

PEG_TX_0

PEG_TX_1

PEG_TX_2

PEG_TX_3

PEG_TX_4

PEG_TX_5

PEG_TX_6

PEG_TX_7

PEG_TX_8

PEG_TX_9 PEG_TX_10 PEG_TX_11 PEG_TX_12 PEG_TX_13 PEG_TX_14 PEG_TX_15

N43 M43

J51 L51 N47 T45 T50 U40 Y44 Y40 AB51 W49 AD44 AD40 AG46 AH49 AG45 AG41

J50 L50 M47 U44 T49 T41 W45 W41 AB50 Y48 AC45 AC41 AH47 AG49 AH45 AG42

N45 U39 U47 N51 R50 T42 Y43 W46 W38 AD39 AC46 AC49 AC42 AH39 AE49 AH44

M45 T38 T46 N50 R51 U43 W42 Y47 Y39 AC38 AD47 AC50 AD43 AG39 AE50 AH43

PEGCOMP

PEG_TXN0 PEG_TXN1 PEG_TXN2 PEG_TXN3 PEG_TXN4 PEG_TXN5 PEG_TXN6 PEG_TXN7 PEG_TXN8 PEG_TXN9 PEG_TXN10 PEG_TXN11 PEG_TXN12 PEG_TXN13 PEG_TXN14 PEG_TXN15

PEG_TXP0 PEG_TXP1 PEG_TXP2 PEG_TXP3 PEG_TXP4 PEG_TXP5 PEG_TXP6 PEG_TXP7 PEG_TXP8 PEG_TXP9 PEG_TXP10 PEG_TXP11 PEG_TXP12 PEG_TXP13 PEG_TXP14

R1176

24.9_0402_1%

1 2

PEG_RXN0 PEG_RXN1 PEG_RXN2 PEG_RXN3 PEG_RXN4 PEG_RXN5 PEG_RXN6 PEG_RXN7 PEG_RXN8 PEG_RXN9 PEG_RXN10 PEG_RXN11 PEG_RXN12 PEG_RXN13 PEG_RXN14 PEG_RXN15

PEG_RXP0 PEG_RXP1 PEG_RXP2 PEG_RXP3 PEG_RXP4 PEG_RXP5 PEG_RXP6 PEG_RXP7 PEG_RXP8 PEG_RXP9 PEG_RXP10 PEG_RXP11 PEG_RXP12 PEG_RXP13 PEG_RXP14 PEG_RXP15

C1058 0.1U_0402_16V4ZC1058 0.1U_0402_16V4Z C1059 0.1U_0402_16V4ZC1059 0.1U_0402_16V4Z C1060 0.1U_0402_16V4ZC1060 0.1U_0402_16V4Z C1559 0.1U_0402_16V4ZC1559 0.1U_0402_16V4Z C1562 0.1U_0402_16V4Z

C1562 0.1U_0402_16V4Z C1563 0.1U_0402_16V4Z

C1563 0.1U_0402_16V4Z C1560 0.1U_0402_16V4Z

C1560 0.1U_0402_16V4Z C1561 0.1U_0402_16V4Z

C1561 0.1U_0402_16V4Z C1564 0.1U_0402_16V4Z

C1564 0.1U_0402_16V4Z C1361 0.1U_0402_16V4Z

C1361 0.1U_0402_16V4Z C1362 0.1U_0402_16V4Z

C1362 0.1U_0402_16V4Z C1363 0.1U_0402_16V4Z

C1363 0.1U_0402_16V4Z C1364 0.1U_0402_16V4Z

C1364 0.1U_0402_16V4Z C1365 0.1U_0402_16V4Z

C1365 0.1U_0402_16V4Z C1366 0.1U_0402_16V4Z

C1366 0.1U_0402_16V4Z C1367 0.1U_0402_16V4Z

C1367 0.1U_0402_16V4Z C1062 0.1U_0402_16V4ZC1062 0.1U_0402_16V4Z

C1063 0.1U_0402_16V4ZC1063 0.1U_0402_16V4Z C1066 0.1U_0402_16V4ZC1066 0.1U_0402_16V4Z C1067 0.1U_0402_16V4ZC1067 0.1U_0402_16V4Z C1368 0.1U_0402_16V4Z

C1368 0.1U_0402_16V4Z C1369 0.1U_0402_16V4Z

C1369 0.1U_0402_16V4Z C1370 0.1U_0402_16V4Z

C1370 0.1U_0402_16V4Z C1371 0.1U_0402_16V4Z

C1371 0.1U_0402_16V4Z C1372 0.1U_0402_16V4Z

C1372 0.1U_0402_16V4Z C1373 0.1U_0402_16V4Z

C1373 0.1U_0402_16V4Z C1374 0.1U_0402_16V4Z

C1374 0.1U_0402_16V4Z C1375 0.1U_0402_16V4Z

C1375 0.1U_0402_16V4Z C1376 0.1U_0402_16V4Z

C1376 0.1U_0402_16V4Z C1377 0.1U_0402_16V4Z

C1377 0.1U_0402_16V4Z C1378 0.1U_0402_16V4Z

C1378 0.1U_0402_16V4Z C1379 0.1U_0402_16V4Z

C1379 0.1U_0402_16V4Z

1 2 1 2 1 2 1 2

+VCCP

PEG_RXN[0..15] <18>

PEG_RXP[0..15] <18>

PEGCOMP trace width and spacing is 20/25 mils.

PEG_M_TXN0 PEG_M_TXN1 PEG_M_TXN2 PEG_M_TXN3 PEG_M_TXN4 PEG_M_TXN5 PEG_M_TXN6 PEG_M_TXN7 PEG_M_TXN8 PEG_M_TXN9 PEG_M_TXN10 PEG_M_TXN11 PEG_M_TXN12 PEG_M_TXN13 PEG_M_TXN14 PEG_M_TXN15

PEG_M_TXP0 PEG_M_TXP1 PEG_M_TXP2 PEG_M_TXP3 PEG_M_TXP4 PEG_M_TXP5 PEG_M_TXP6 PEG_M_TXP7 PEG_M_TXP8 PEG_M_TXP9 PEG_M_TXP10 PEG_M_TXP11 PEG_M_TXP12 PEG_M_TXP13 PEG_M_TXP14 PEG_M_TXP15

PEG_M_TXN[0..15] <18>

PEG_M_TXP[0..15] <18>

CFG[2:0] FSB Freq select

CFG7 (CPU Strap)

CFG8 (Low power PCIE)

(PCIE Graphics Lane Reversal)

CFG[13:12] (XOR/ALLZ)

CFG16 (FSB Dynamic ODT)

SDVO_CTRLDATA

CFG19 (DMI Lane Reversal)

CFG20 (PCIE/SDVO concurrent)

J37

CFG5PEG_TXP15

2 1

PAD-NO SHORT 2x2m

Strap Pin Table

CFG5 (DMI select)

CFG6

CFG9

CFG[11:10]

010 = FSB 800MHz 011 = FSB 667MHz Others = Reserved

0 = DMI x 2 1 = DMI x 4

Reserved

0 = Reserved 1 = Mobile CPU

0 = Normal mode 1 = Low Power mode

0 = Reverse Lane 1 = Normal Operation

Reserved 00 = Reserved

01 = XOR Mode Enabled 10 = All Z Mode Enabled 11 = Normal Operation

(Default)

ReservedCFG[15:14]

0 = Disabled 1 = Enabled

ReservedCFG[18:17]

0 = No SDVO Device Present 1 = SDVO Device Present

0 = Normal Operation

(Lane number in Order)

1 = Reverse Lane

0 = Only PCIE or SDVO is operational. 1 = PCIE/SDVO are operating simu.

R1151 4.02K_0402_1%@R1151 4.02K_0402_1%@

CFG5<7>

CFG7<7>

CFG8<7>

CFG9<7>

CFG12<7>

CFG13<7>

CFG16<7>

1 2

R1152 4.02K_0402_1%@R1152 4.02K_0402_1%@

1 2

R1451 4.02K_0402_1%@R1451 4.02K_0402_1%@

1 2

R1153 4.02K_0402_1%@R1153 4.02K_0402_1%@

1 2

R1155 4.02K_0402_1%@R1155 4.02K_0402_1%@

1 2

R1156 4.02K_0402_1%@R1156 4.02K_0402_1%@

1 2

R1157 4.02K_0402_1%@R1157 4.02K_0402_1%@

1 2

CFG[17:3] have internal pull up CFG[19:18] have internal pull down

+3VS

R1159 4.02K_0402_1%@R1159 4.02K_0402_1%@

CFG19<7>

CFG20<7>

A A

1 2

R1160 4.02K_0402_1%@R1160 4.02K_0402_1%@

1 2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2006/09/25 2006/09/25

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

CRESTLINE((3/6)-VGA/LVDS/TV

LA3262P_DIS__M64

957Tuesday, August 21, 2007

1 2

0_0603_5%

R1458

R1460

R1455

+1.25VM

+1.25VS

+1.8V

+1.5VS

22U_0805_6.3VAM

C1230

+1.5VS_TVDAC

10U_0603_6.3V6M

C1607

+1.25VM_HPLL

0.1U_0402_16V4Z

+V1.25VS_AXF

10U_0603_6.3V6M

+1.8V_SM_CK

22U_0805_6.3VAM

C1124

C1134

+3VS_HV

C1111

C1115

0.022U_0402_16V7K

C1125

1U_0603_10V4Z

C1112

1 2

0.1U_0402_16V4Z

0.1U_0402_16V4Z 0_0805_5%

0_0805_5%

C1116

1 2

0.1U_0402_16V4Z

0.1U_0402_16V4Z 0_0805_5%

0_0805_5%

R1464

MBK2012121YZF_0805

C1135

C1135 22U_0805_6.3VAM

22U_0805_6.3VAM

+1.25VS_PEGPLL

C1123

10U_0603_6.3V6M

+VCC_PEG

+1.25VM_MPLL

0.1U_0402_16V4Z

+1.25VS_DMI

220U_D2_4VM_R15

C1227

C1139

+VCCP

1 2

0.1U_0402_16V4Z

0.1U_0402_16V4Z R1457

R1457

0_0603_5%

C1117

+1.25VS

L77

MBK2012221YZF_0805

MBK2012221YZF_0805 R1468

R1468 1_0402_5%

1_0402_5%

0904 change

10U_0603_6.3V6M

C1138

100NH_LQW18ANR10J00D_5%_0805

R1466

MBK2012121YZF_0805

C1140

22U_0805_6.3VAM

D12

2 1

CH751H-40PT_SOD323-2

+3VS

+1.25VS

R1465

0_0805_5%

R1467

1 2

+1.25VM

+VCCP_D

+VCCP

+1.25VS

(link CIS)

R1469

10_0402_5%

0_0402_5%

0_0402_5% R1470

R1470

U15H

J32

VCCSYNC

A33

VCCA_CRT_DAC_1

B33

VCCA_CRT_DAC_2

D D

+1.25VM_HPLL +1.25VM_MPLL

+3VS_PEG_BG

R1459

0_0603_5%

0.1U_0402_16V4Z

R1461

1 2

0_0805_5%

C1127

1U_0402_6.3V4Z

C1130

+1.25VM_HPLL

C1121

0.1U_0402_16V4Z

+1.25VM_A_SM

0317 change value

C1128

4.7U_0603_6.3V6M

1U_0603_10V4Z

22U_0805_6.3VAM

C1131

C1608

0.1U_0402_16V4Z

+1.25VS_PEGPLL

1U_0603_10V4Z

0.1U_0402_16V4Z

C1132

+1.5VS_TVDAC

+1.25VS_PEGPLL

0.1U_0402_16V4Z

C1606

C1122

C1129

+3VS

+1.25VM

C C

150U_D_6.3VM

B B

C1126

R1462

0_0603_5%

22U_0805_6.3VAM

+1.25VM_A_SM_CK

C1226

20 mils

A30

VCCA_DAC_BG

B32

VSSA_DAC_BG

B49

VCCA_DPLLA

H49

VCCA_DPLLB

AL2

VCCA_HPLL

AM2

VCCA_MPLL

A41

VCCA_LVDS

B41

VSSA_LVDS

K50

VCCA_PEG_BG

K49

VSSA_PEG_BG

U51

VCCA_PEG_PLL

AW18

VCCA_SM_1

AV19

VCCA_SM_2

AU19

VCCA_SM_3

AU18

VCCA_SM_4

AU17

VCCA_SM_5

AT22

VCCA_SM_7

AT21

VCCA_SM_8

AT19

VCCA_SM_9

AT18

VCCA_SM_10

AT17

VCCA_SM_11

AR17

VCCA_SM_NCTF_1

AR16

VCCA_SM_NCTF_2

BC29

VCCA_SM_CK_1

BB29

VCCA_SM_CK_2

C25

VCCA_TVA_DAC_1

B25

VCCA_TVA_DAC_2

C27

VCCA_TVB_DAC_1

B27

VCCA_TVB_DAC_2

B28

VCCA_TVC_DAC_1

A28

VCCA_TVC_DAC_2

M32

VCCD_CRT

L29

VCCD_TVDAC

N28

VCCD_QDAC

AN2

VCCD_HPLL

U48

VCCD_PEG_PLL

J41

VCCD_LVDS_1

H42

VCCD_LVDS_2

CRESTLINE_1p0

CRTPLLA PEGA SMTV

POWER

A CK A LVDS

D TV/CRTLVDS

VTT_10 VTT_11 VTT_12 VTT_13

VTT

VTT_14 VTT_15 VTT_16 VTT_17 VTT_18 VTT_19 VTT_20 VTT_21 VTT_22

VCC_AXD_1 VCC_AXD_2 VCC_AXD_3 VCC_AXD_4 VCC_AXD_5

AXD

VCC_AXD_6

VCC_AXD_NCTF

VCC_AXF_1 VCC_AXF_2 VCC_AXF_3

AXF

VCC_DMI

VCC_SM_CK_1 VCC_SM_CK_2 VCC_SM_CK_3 VCC_SM_CK_4

SM CK

VCC_TX_LVDS

VCC_HV_1 VCC_HV_2

VCC_PEG_1 VCC_PEG_2 VCC_PEG_3 VCC_PEG_4

PEG

VCC_PEG_5

VCC_RXR_DMI_1 VCC_RXR_DMI_2

DMI

VTTLF1 VTTLF2 VTTLF3

VTTLF

VTT_1 VTT_2 VTT_3 VTT_4 VTT_5 VTT_6 VTT_7 VTT_8 VTT_9

U13 U12 U11 U9 U8 U7 U5 U3 U2 U1 T13 T11 T10 T9 T7 T6 T5 T3 T2 R3 R2 R1

AT23 AU28 AU24 AT29 AT25 AT30

AR29

B23 B21 A21

AJ50

BK24 BK23 BJ24 BJ23

A43

C40 B40

AD51 W50 W51 V49 V50

AH50 AH51

A7 F2 AH1

+VCCP

330U_D2E_2.5VM_R15

C830

+1.25VM_AXD

250mA

+V1.25VS_AXF

+1.8V_SM_CK

+VCC_DMI

0.47U_0402_10V4Z~D

0.47U_0402_10V4Z~D C1142

C1142

C1141

C849

1U_0402_6.3V4Z

C1119

+1.25VS_DMI

+VCC_PEG

20mils

0.47U_0402_10V4Z~D

0.47U_0402_10V4Z~D C1143

C1143

0.47U_0603_10V7K

C836

C1120

0.47U_0402_10V4Z~D

4.7U_0603_6.3V6M

C838

4.7U_0603_6.3V6M

R1671

1 2

0_0805_5%

10U_0603_6.3V6M

C837

+3VS_HV

C1136

2.2U_0603_6.3V4Z

0.1U_0402_16V4Z

+1.25VM

0904 change

L94

1 2

R84

+1.25VS

(link CIS)

+VCCP

C1614

10U_0603_6.3V6M

+VCC_DMI

C1615

10U_0603_6.3V6M

1 2

100NH_LQW18ANR10J00D_5%_0805

0_0805_5%

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2006/09/25 2006/09/25

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

CRESTLINE(4/6)-PWR

LA3262P_DIS__M64

10 57Tuesday, August 21, 2007

+VCCP

C798

C1160

1 2

0.1U_0402_16V4Z

10U_0603_6.3V6M

C1154

R1711

@R1711

C797

C1155

0.1U_0402_16V4Z

0.1U_0402_16V4Z C1161

C1161

CRACK_GPIO28

+VCCP

U15F

AB33

VCC_NCTF_1

AB36

VCC_NCTF_2

AB37

VCC_NCTF_3

AC33

VCC_NCTF_4

AC35

VCC_NCTF_5

AC36

VCC_NCTF_6

AD35

VCC_NCTF_7

AD36

VCC_NCTF_8

AF33

VCC_NCTF_9

AF36

VCC_NCTF_10

AH33

VCC_NCTF_11

AH35

VCC_NCTF_12

AH36

VCC_NCTF_13

AH37

VCC_NCTF_14

AJ33

VCC_NCTF_15

AJ35

VCC_NCTF_16

AK33

VCC_NCTF_17

AK35

VCC_NCTF_18

AK36

VCC_NCTF_19

AK37

VCC_NCTF_20

AD33

VCC_NCTF_21

AJ36

VCC_NCTF_22

AM35

VCC_NCTF_23

AL33

VCC_NCTF_24

AL35

VCC_NCTF_25

AA33

VCC_NCTF_26

AA35

VCC_NCTF_27

AA36

VCC_NCTF_28

AP35

VCC_NCTF_29

AP36

VCC_NCTF_30

AR35

VCC_NCTF_31

AR36

VCC_NCTF_32

Y32

VCC_NCTF_33

Y33

VCC_NCTF_34

Y35

VCC_NCTF_35

Y36

VCC_NCTF_36

Y37

VCC_NCTF_37

T30

VCC_NCTF_38

T34

VCC_NCTF_39

T35

VCC_NCTF_40

U29

VCC_NCTF_41

U31

VCC_NCTF_42

U32

VCC_NCTF_43

U33

VCC_NCTF_44

U35

VCC_NCTF_45

U36

VCC_NCTF_46

V32

VCC_NCTF_47

V33

VCC_NCTF_48

V36

VCC_NCTF_49

V37

VCC_NCTF_50

AL24

VCC_AXM_NCTF_1

AL26

VCC_AXM_NCTF_2

AL28

VCC_AXM_NCTF_3

AM26

VCC_AXM_NCTF_4

AM28

VCC_AXM_NCTF_5

AM29

VCC_AXM_NCTF_6

AM31

VCC_AXM_NCTF_7

AM32

VCC_AXM_NCTF_8

AM33

VCC_AXM_NCTF_9

AP29

VCC_AXM_NCTF_10

AP31

VCC_AXM_NCTF_11

AP32

VCC_AXM_NCTF_12

AP33

VCC_AXM_NCTF_13

AL29

VCC_AXM_NCTF_14

AL31

VCC_AXM_NCTF_15

AL32

VCC_AXM_NCTF_16

AR31

VCC_AXM_NCTF_17

AR32

VCC_AXM_NCTF_18

AR33

VCC_AXM_NCTF_19

CRESTLINE_1p0

+3VS

1 2

100K_0402_5%

MCHGND2

Q121

RHU002N06_SOT323

VCC NCTF

POWER

VCC AXM NCTF

R1709

@R1709

CRACK_GPIO28

VSS_NCTF_1 VSS_NCTF_2 VSS_NCTF_3 VSS_NCTF_4 VSS_NCTF_5 VSS_NCTF_6 VSS_NCTF_7 VSS_NCTF_8

VSS_NCTF_9 VSS_NCTF_10 VSS_NCTF_11 VSS_NCTF_12 VSS_NCTF_13 VSS_NCTF_14 VSS_NCTF_15

VSS NCTF

VSS_NCTF_16 VSS_NCTF_17 VSS_NCTF_18 VSS_NCTF_19 VSS_NCTF_20 VSS_NCTF_21

VSS_SCB1 VSS_SCB2 VSS_SCB3 VSS_SCB4 VSS_SCB5 VSS_SCB6

VSS SCBVCC AXM

VCC_AXM_1 VCC_AXM_2 VCC_AXM_3 VCC_AXM_4 VCC_AXM_5 VCC_AXM_6 VCC_AXM_7

100K_0402_5%

MCHGND5MCHGND6

T27 T37 U24 U28 V31 V35 AA19 AB17 AB35 AD19 AD37 AF17 AF35 AK17 AM17 AM24 AP26 AP28 AR15 AR19 AR28

MCHGND1

MCHGND2

MCHGND3

MCHGND4

BL1

MCHGND5

BL51

MCHGND6

A51

AT33 AT31 AK29 AK24 AK23 AJ26 AJ23

R1703

@R1703

1 2

RHU002N06_SOT323

Q119

R112

R112 R132

R132 R133

R133 R122

R122 R113

R113 R111

R111

+3VL

R1702

CRACK_GPIO28

1 2 13

100K_0402_5%

R1475

1 2

0_0603_5%

330U_D2E_2.5VM_R15

+1.8V

0_0402_5%

0_0402_5% 0_0402_5%

0_0402_5%

1 2 1 2 1 2 1 2 1 2 1 2

+1.05VM

CRACK_GPIO28 <27,37>

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

22U_0805_6.3VAM

C808

2006/09/25 2006/09/25

22U_0805_6.3VAM

C809

0.01U_0402_16V7K

C810

C794

Compal Secret Data

Deciphered Date

D D

22U_0805_6.3VAM

0.22U_0402_10V4Z

220U_D2_4VM_R15

C806

C C

B B

0.22U_0402_10V4Z

0.22U_0402_10V4Z C1157

C1157

+3VS +3VS

A A

100K_0402_5%

R1701

@R1701

Q118

RHU002N06_SOT323

CRACK_GPIO28

1 2

0.22U_0402_10V4Z

C803

C796

+1.05VM

10U_0603_6.3V6M

0.1U_0402_16V4Z

0.22U_0402_10V4Z

0.22U_0402_10V4Z C1159

C1159

C1158

04/10 monitor NB crack

MCHGND4

RHU002N06_SOT323

0.1U_0402_16V4Z

+3VS

100K_0402_5%

Q123

AT35 AT34 AH28 AC32 AC31 AK32

AJ31

AJ28 AH32 AH31 AH29 AF32

AU32 AU33 AU35 AV33

AW33 AW35

AY35 BA32 BA33 BA35 BB33 BC32 BC33 BC35 BD32 BD35 BE32 BE33 BE35 BF33 BF34 BG32 BG33 BG35 BH32 BH34 BH35

BJ32

BJ33

BJ34 BK32 BK33 BK34 BK35

BL33 AU30

W13

W14 AA20

AA23 AA26 AA28 AB21 AB24 AB29 AC20 AC21 AC23 AC24 AC26 AC28 AC29 AD20 AD23 AD24 AD28 AF21 AF26 AA31 AH20 AH21 AH23 AH24 AH26 AD31

AJ20 AN14

R30

R20

T14

Y12

U15G

VCC_1 VCC_2 VCC_3 VCC_5 VCC_4 VCC_6 VCC_7 VCC_8 VCC_9 VCC_10 VCC_11 VCC_12

VCC_13

VCC_SM_1 VCC_SM_2 VCC_SM_3 VCC_SM_4 VCC_SM_5 VCC_SM_6 VCC_SM_7 VCC_SM_8 VCC_SM_9 VCC_SM_10 VCC_SM_11 VCC_SM_12 VCC_SM_13 VCC_SM_14 VCC_SM_15 VCC_SM_16 VCC_SM_17 VCC_SM_18 VCC_SM_19 VCC_SM_20 VCC_SM_21 VCC_SM_22 VCC_SM_23 VCC_SM_24 VCC_SM_25 VCC_SM_26 VCC_SM_27 VCC_SM_28 VCC_SM_29 VCC_SM_30 VCC_SM_31 VCC_SM_32 VCC_SM_33 VCC_SM_34 VCC_SM_35 VCC_SM_36

VCC_AXG_1 VCC_AXG_2 VCC_AXG_3 VCC_AXG_4 VCC_AXG_5 VCC_AXG_6 VCC_AXG_7 VCC_AXG_8 VCC_AXG_9 VCC_AXG_10 VCC_AXG_11 VCC_AXG_12 VCC_AXG_13 VCC_AXG_14 VCC_AXG_15 VCC_AXG_16 VCC_AXG_17 VCC_AXG_18 VCC_AXG_19 VCC_AXG_20 VCC_AXG_21 VCC_AXG_22 VCC_AXG_23 VCC_AXG_24 VCC_AXG_25 VCC_AXG_26 VCC_AXG_27 VCC_AXG_28 VCC_AXG_29 VCC_AXG_30 VCC_AXG_31 VCC_AXG_32 VCC_AXG_33 VCC_AXG_34

CRESTLINE_1p0

VCC CORE

POWER

VCC SMVCC GFX

VCC_AXG_NCTF_1 VCC_AXG_NCTF_2 VCC_AXG_NCTF_3 VCC_AXG_NCTF_4 VCC_AXG_NCTF_5 VCC_AXG_NCTF_6 VCC_AXG_NCTF_7 VCC_AXG_NCTF_8

VCC_AXG_NCTF_9 VCC_AXG_NCTF_10 VCC_AXG_NCTF_11 VCC_AXG_NCTF_12 VCC_AXG_NCTF_13 VCC_AXG_NCTF_14 VCC_AXG_NCTF_15 VCC_AXG_NCTF_16 VCC_AXG_NCTF_17 VCC_AXG_NCTF_18 VCC_AXG_NCTF_19 VCC_AXG_NCTF_20 VCC_AXG_NCTF_21 VCC_AXG_NCTF_22 VCC_AXG_NCTF_23 VCC_AXG_NCTF_24 VCC_AXG_NCTF_25 VCC_AXG_NCTF_26 VCC_AXG_NCTF_27 VCC_AXG_NCTF_28 VCC_AXG_NCTF_29 VCC_AXG_NCTF_30 VCC_AXG_NCTF_31 VCC_AXG_NCTF_32 VCC_AXG_NCTF_33 VCC_AXG_NCTF_34 VCC_AXG_NCTF_35 VCC_AXG_NCTF_36 VCC_AXG_NCTF_37 VCC_AXG_NCTF_38 VCC_AXG_NCTF_39 VCC_AXG_NCTF_40 VCC_AXG_NCTF_41 VCC_AXG_NCTF_42 VCC_AXG_NCTF_43 VCC_AXG_NCTF_44 VCC_AXG_NCTF_45 VCC_AXG_NCTF_46 VCC_AXG_NCTF_47 VCC_AXG_NCTF_48 VCC_AXG_NCTF_49 VCC_AXG_NCTF_50 VCC_AXG_NCTF_51 VCC_AXG_NCTF_52 VCC_AXG_NCTF_53 VCC_AXG_NCTF_54

VCC GFX NCTF

VCC_AXG_NCTF_55 VCC_AXG_NCTF_56 VCC_AXG_NCTF_57 VCC_AXG_NCTF_58 VCC_AXG_NCTF_59 VCC_AXG_NCTF_60 VCC_AXG_NCTF_61 VCC_AXG_NCTF_62 VCC_AXG_NCTF_63 VCC_AXG_NCTF_64 VCC_AXG_NCTF_65 VCC_AXG_NCTF_66 VCC_AXG_NCTF_67 VCC_AXG_NCTF_68 VCC_AXG_NCTF_69 VCC_AXG_NCTF_70 VCC_AXG_NCTF_71 VCC_AXG_NCTF_72 VCC_AXG_NCTF_73 VCC_AXG_NCTF_74 VCC_AXG_NCTF_75 VCC_AXG_NCTF_76 VCC_AXG_NCTF_77 VCC_AXG_NCTF_78 VCC_AXG_NCTF_79 VCC_AXG_NCTF_80 VCC_AXG_NCTF_81 VCC_AXG_NCTF_82 VCC_AXG_NCTF_83

VCC_SM_LF1 VCC_SM_LF2 VCC_SM_LF3 VCC_SM_LF4 VCC_SM_LF5 VCC_SM_LF6 VCC_SM_LF7

VCC SM LF

Title

Size Document Number Rev

Custom

Date: Sheet

T17 T18 T19 T21 T22 T23 T25 U15 U16 U17 U19 U20 U21 U23 U26 V16 V17 V19 V20 V21 V23 V24 Y15 Y16 Y17 Y19 Y20 Y21 Y23 Y24 Y26 Y28 Y29 AA16 AA17 AB16 AB19 AC16 AC17 AC19 AD15 AD16 AD17 AF16 AF19 AH15 AH16 AH17 AH19 AJ16 AJ17 AJ19 AK16 AK19 AL16 AL17 AL19 AL20 AL21 AL23 AM15 AM16 AM19 AM20 AM21 AM23 AP15 AP16 AP17 AP19 AP20 AP21 AP23 AP24 AR20 AR21 AR23 AR24 AR26 V26 V28 V29 Y31

VCCSM_LF1

AW45

VCCSM_LF2

BC39

VCCSM_LF3

BE39

VCCSM_LF4

BD17 BD4 AW8 AT6

LA3262P_DIS__M64

VCCSM_LF5 VCCSM_LF6 VCCSM_LF7

Compal Electronics, Inc.

CRESTLINE((5/6)-PWR/GND

C1162 0.1U_0402_16V4Z C1162 0.1U_0402_16V4Z

C1318 0.22U_0603_10V7K C1318 0.22U_0603_10V7K

C1163 0.1U_0402_16V4Z C1163 0.1U_0402_16V4Z

C795 0.22U_0603_10V7K C795 0.22U_0603_10V7K

C813 1U_0603_10V4Z C813 1U_0603_10V4Z

C814 1U_0603_10V4Z C814 1U_0603_10V4Z

C1164 0.47U_0402_10V4Z~D C1164 0.47U_0402_10V4Z~D

11 57Tuesday, August 21, 2007

U15I

A13

VSS_1

A15

VSS_2

A17

VSS_3

A24

VSS_4

AA21

VSS_5

AA24

VSS_6

AA29

VSS_7

AB20

D D

C C

B B

A A

AB23 AB26 AB28

AB31 AC10 AC13

AC39 AC43 AC47

AD21 AD26 AD29

AD41 AD45 AD49

AD50

AE10

AE14

AF20

AF23

AF24

AF31

AG2 AG38 AG43 AG47 AG50

AH40 AH41

AJ11 AJ13 AJ21 AJ24 AJ29 AJ32 AJ43 AJ45 AJ49 AK20 AK21 AK26 AK28 AK31 AK51

AM11 AM13

AM3

AM4 AM41 AM45

AN38 AN39 AN43

AP48 AP50

AR11 AR39

AR44 AR47

AT10 AT14 AT41 AT49

AU23 AU29

AU36 AU49 AU51

AV39 AV48

AW1 AW12 AW16

AC3

AD1

AD3

AD5 AD8

AE6

AH3

AH7 AH9

AL1

AN1

AN5 AN7 AP4

AR2

AR7

AU1

AU3

VSS_8 VSS_9 VSS_10 VSS_11 VSS_12 VSS_13 VSS_14 VSS_15 VSS_16 VSS_17 VSS_18 VSS_19 VSS_20 VSS_21 VSS_22 VSS_23 VSS_24 VSS_25 VSS_26 VSS_27 VSS_28 VSS_29 VSS_30 VSS_31 VSS_32 VSS_33 VSS_34 VSS_35 VSS_36 VSS_37 VSS_38 VSS_39 VSS_40 VSS_41 VSS_42 VSS_43 VSS_44 VSS_45 VSS_46 VSS_47 VSS_48 VSS_49 VSS_50 VSS_51 VSS_52 VSS_53 VSS_54 VSS_55 VSS_56 VSS_57 VSS_58 VSS_59 VSS_60 VSS_61 VSS_62 VSS_63 VSS_64 VSS_65 VSS_66 VSS_67 VSS_68 VSS_69 VSS_70 VSS_71 VSS_72 VSS_73 VSS_74 VSS_75 VSS_76 VSS_77 VSS_78 VSS_79 VSS_80 VSS_81 VSS_82 VSS_83 VSS_84 VSS_85 VSS_86 VSS_87 VSS_88 VSS_89 VSS_90 VSS_91 VSS_92 VSS_93 VSS_94 VSS_95 VSS_96 VSS_97 VSS_98 VSS_99

CRESTLINE_1p0

VSS

VSS_100 VSS_101 VSS_102 VSS_103 VSS_104 VSS_105 VSS_106 VSS_107 VSS_108 VSS_109 VSS_110 VSS_111 VSS_112 VSS_113 VSS_114 VSS_115 VSS_116 VSS_117 VSS_118 VSS_119 VSS_120 VSS_121 VSS_122 VSS_123 VSS_124 VSS_125 VSS_126 VSS_127 VSS_128 VSS_129 VSS_130 VSS_131 VSS_132 VSS_133 VSS_134 VSS_135 VSS_136 VSS_137 VSS_138 VSS_139 VSS_140 VSS_141 VSS_142 VSS_143 VSS_144 VSS_145 VSS_146 VSS_147 VSS_148 VSS_149 VSS_150 VSS_151 VSS_152 VSS_153 VSS_154 VSS_155 VSS_156 VSS_157 VSS_158 VSS_159 VSS_160 VSS_161 VSS_162 VSS_163 VSS_164 VSS_165 VSS_166 VSS_167 VSS_168 VSS_169 VSS_170 VSS_171 VSS_172 VSS_173 VSS_174 VSS_175 VSS_176 VSS_177 VSS_178 VSS_179 VSS_180 VSS_181 VSS_182 VSS_183 VSS_184 VSS_185 VSS_186 VSS_187 VSS_188 VSS_189 VSS_190 VSS_191 VSS_192 VSS_193 VSS_194 VSS_195 VSS_196 VSS_197 VSS_198

AW24 AW29 AW32 AW5 AW7 AY10 AY24 AY37 AY42 AY43 AY45 AY47 AY50 B10 B20 B24 B29 B30 B35 B38 B43 B46 B5 B8 BA1 BA17 BA18 BA2 BA24 BB12 BB25 BB40 BB44 BB49 BB8 BC16 BC24 BC25 BC36 BC40 BC51 BD13 BD2 BD28 BD45 BD48 BD5 BE1 BE19 BE23 BE30 BE42 BE51 BE8 BF12 BF16 BF36 BG19 BG2 BG24 BG29 BG39 BG48 BG5 BG51 BH17 BH30 BH44 BH46 BH8 BJ11 BJ13 BJ38 BJ4 BJ42 BJ46 BK15 BK17 BK25 BK29 BK36 BK40 BK44 BK6 BK8 BL11 BL13 BL19 BL22 BL37 BL47 C12 C16 C19 C28 C29 C33 C36 C41

U15J

C46 C50

C7 D13 D24

D3 D32 D39 D45 D49 E10 E16 E24 E28 E32 E47 F19 F36

F4 F40 F50

G1 G13 G16 G19 G24 G28 G29 G33 G42 G45 G48

G8 H24 H28

H4 H45

J11 J16

J2 J24 J28 J33 J35 J39

K12 K47

L1 L17 L20 L24 L28

L3 L33 L49

M28 M42 M46 M49

M50

M9 N11 N14 N17 N29 N32 N36 N39 N44 N49

N7 P19

P23

P3 P50 R49 T39 T43 T47 U41 U45 U50

CRESTLINE_1p0

VSS_199 VSS_200 VSS_201 VSS_202 VSS_203 VSS_204 VSS_205 VSS_206 VSS_207 VSS_208 VSS_209 VSS_210 VSS_211 VSS_212 VSS_213 VSS_214 VSS_215 VSS_216 VSS_217 VSS_218 VSS_219 VSS_220 VSS_221 VSS_222 VSS_223 VSS_224 VSS_225 VSS_226 VSS_227 VSS_228 VSS_229 VSS_230 VSS_231 VSS_232 VSS_233 VSS_234 VSS_235 VSS_236 VSS_237 VSS_238 VSS_239 VSS_240 VSS_241 VSS_242 VSS_243

VSS_245 VSS_246 VSS_247 VSS_248 VSS_249 VSS_250 VSS_251 VSS_252 VSS_253 VSS_254 VSS_255 VSS_256 VSS_257 VSS_258 VSS_259 VSS_260 VSS_261 VSS_262 VSS_263 VSS_264 VSS_265 VSS_266 VSS_267 VSS_268 VSS_269 VSS_270 VSS_271 VSS_272 VSS_273 VSS_274 VSS_275 VSS_276 VSS_277 VSS_278 VSS_279 VSS_280 VSS_281 VSS_282 VSS_283 VSS_284 VSS_285 VSS_286

VSS

VSS_287 VSS_288 VSS_289 VSS_290 VSS_291 VSS_292 VSS_293 VSS_294 VSS_295 VSS_296 VSS_297 VSS_298 VSS_299 VSS_300 VSS_301 VSS_302 VSS_303 VSS_304 VSS_305

VSS_306 VSS_307 VSS_308 VSS_309 VSS_310 VSS_311 VSS_312 VSS_313

W11 W39 W43 W47 W5 W7 Y13 Y2 Y41 Y45 Y49 Y5 Y50 Y11 P29 T29 T31 T33 R28

AA32 AB32 AD32 AF28 AF29 AT27 AV25 H50

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2006/09/25 2006/09/25

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

CRESTLINE((6/6)-PWR/GND

LA3262P_DIS__M64

12 57Tuesday, August 21, 2007

DDR_A_DQS#[0..7]<8>

DDR_A_D[0..63]<8>

DDR_A_DM[0..7]<8>

DDR_A_DQS[0..7]<8>

DDR_A_MA[0..14]<7,8>

D D

Layout Note: Place near JP34

+1.8V

2.2U_0805_16V4Z

2.2U_0805_16V4Z C473

C473

0.1U_0402_16V4Z

C250

56_0404_4P2R_5%

2.2U_0805_16V4Z C491

C491

0.1U_0402_16V4Z

C257

C272

+0.9V

RP22 56_0404_4P2R_5%RP22 56_0404_4P2R_5%

RP26 56_0404_4P2R_5%RP26 56_0404_4P2R_5%

RP25 56_0404_4P2R_5%RP25 56_0404_4P2R_5%

RP28 56_0404_4P2R_5%RP28 56_0404_4P2R_5%

RP30 56_0404_4P2R_5%RP30 56_0404_4P2R_5%

RP34 56_0404_4P2R_5%RP34 56_0404_4P2R_5%

RP24 56_0404_4P2R_5%RP24 56_0404_4P2R_5%

2.2U_0805_16V4Z

0.1U_0402_16V4Z

C279

14 23

0.1U_0402_16V4Z

0.1U_0402_16V4Z C255

C255

C465

0.1U_0402_16V4Z

C281

DDR_A_BS#2 DDR_CKE0_DIMMA

DDR_A_MA7 DDR_A_MA6

DDR_A_MA9 DDR_A_MA12

DDR_A_MA4 DDR_A_MA2

DDR_A_MA0 DDR_A_BS#1

M_ODT0 DDR_A_MA13

DDR_CKE1_DIMMA DDR_A_MA14

0.1U_0402_16V4Z

C274

0.1U_0402_16V4Z

2.2U_0805_16V4Z

C C

B B

A A

Layout Note: Place one cap close to every 2 pullup resistors terminated to +0.9VS

+0.9V

0.1U_0402_16V4Z

DDR_A_MA5 DDR_A_MA8

DDR_A_MA1 DDR_A_MA3

DDR_A_RAS# DDR_CS0_DIMMA#

DDR_A_BS#0 DDR_A_MA10

DDR_A_CAS# DDR_A_WE#

DDR_CS1_DIMMA# M_ODT1

DDR_A_MA11

C458

C229

0.1U_0402_16V4Z

C239

RP27

RP29

RP32

RP31

RP33

RP35

R1903 56_0402_5%

C498

0.1U_0402_16V4Z

1 4 2 3

2 3 1 4

1 2

C242

C268

0.1U_0402_16V4Z

0.1U_0402_16V4Z C280

C280

0.1U_0402_16V4Z

C252

0.1U_0402_16V4Z

0.1U_0402_16V4Z C235

C235

0.1U_0402_16V4Z

C241

C234

Layout Note: Place these resistor closely JP34,all trace length Max=1.5"

+1.8V

JP34

VREF

DDR_A_D4 DDR_A_D1

DDR_A_DQS#0 DDR_A_DQS0

DDR_A_D2 DDR_A_D3

DDR_A_D8 DDR_A_D14

DDR_A_DQS#1 DDR_A_DQS1

DDR_A_D9 DDR_A_D11 DDR_A_D15 DDR_A_D10

DDR_A_D16 DDR_A_D17

DDR_A_DQS#2 DDR_A_DQS2

DDR_A_D18 DDR_A_D19

DDR_A_DM3

DDR_A_D26 DDR_A_D27

DDR_CKE0_DIMMA<7>

DDR_A_BS2<8>

DDR_A_BS0<8>

DDR_A_WE#<8>

DDR_A_CAS#<8>

0.1U_0402_16V4Z

C227

DDR_CS1_DIMMA#<7>

M_ODT1<7>

ICH_SMBDATA<14,15,26>

ICH_SMBCLK<14,15,26>

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

DDR_CKE0_DIMMA

DDR_A_BS#2 DDR_A_MA12

DDR_A_MA9 DDR_A_MA7 DDR_A_MA8

DDR_A_MA5 DDR_A_MA3 DDR_A_MA1

DDR_A_MA10 DDR_A_BS#0 DDR_A_WE#

DDR_A_CAS# DDR_CS1_DIMMA#

M_ODT1 DDR_A_D37

DDR_A_D36 DDR_A_DQS#4

DDR_A_DQS4 DDR_A_D35

DDR_A_D32 DDR_A_D40

DDR_A_D44 DDR_A_DM5 DDR_A_D41

DDR_A_D46 DDR_A_D49

DDR_A_D48

DDR_A_DQS#6 DDR_A_DQS6

DDR_A_D50 DDR_A_D61 DDR_A_D57

DDR_A_D60 DDR_A_DM7 DDR_A_D59

DDR_A_D58 ICH_SMBDATA

ICH_SMBCLK

+3VM

2.2U_0603_6.3V4Z

2006/09/25 2006/09/25

C311

C308

Compal Secret Data

11 13 15 17 19 21 23 25 27 29 31 33 35 37 39

41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97

99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 203

0.1U_0402_16V4Z

Deciphered Date

VSS DQ0 DQ1 VSS DQS0# DQS0 VSS DQ2 DQ3 VSS DQ8 DQ9 VSS DQS1# DQS1 VSS DQ10 DQ11 VSS

VSS DQ16 DQ17 VSS DQS2# DQS2 VSS DQ18 DQ19 VSS DQ24 DQ25 VSS DM3 NC VSS DQ26 DQ27 VSS CKE0 VDD NC BA2 VDD A12 A9 A8 VDD A5 A3 A1 VDD A10/AP BA0 WE# VDD CAS# NC/S1# VDD NC/ODT1 VSS DQ32 DQ33 VSS DQS4# DQS4 VSS DQ34 DQ35 VSS DQ40 DQ41 VSS DM5 VSS DQ42 DQ43 VSS DQ48 DQ49 VSS NC,TEST VSS DQS6# DQS6 VSS DQ50 DQ51 VSS DQ56 DQ57 VSS DM7 VSS DQ58 DQ59 VSS SDA SCL VDDSPD GND

FOX_ASOA426-M4R-TRconn@

SO-DIMM A

REVERSE

Top side

VSS DQ4 DQ5 VSS DM0 VSS DQ6 DQ7

VSS DQ12 DQ13

VSS

DM1

VSS

CK0

CK0#

VSS DQ14 DQ15

VSS

VSS DQ20 DQ21

VSS

DM2

VSS DQ22 DQ23

VSS DQ28 DQ29

VSS

DQS3#

DQS3

VSS DQ30 DQ31

VSS

NC/CKE1

VDD

NC/A15 NC/A14

VDD

BA1

RAS#

VDD ODT0

NC/A13

VDD

VSS DQ36 DQ37

VSS

DM4

VSS DQ38 DQ39

VSS DQ44 DQ45

VSS

DQS5#

DQS5

VSS DQ46 DQ47

VSS DQ52 DQ53

VSS

CK1

CK1#

VSS

DM6

VSS DQ54 DQ55

VSS DQ60 DQ61

VSS

DQS7#

DQS7

VSS DQ62 DQ63

VSS

SAO

SA1

GND

+1.8V

V_DDR_MCH_REF

DDR_A_D6

DDR_A_D0

6 8

DDR_A_DM0

10 12

DDR_A_D5

DDR_A_D7

16 18

DDR_A_D13

DDR_A_D12

22 24

DDR_A_DM1

26 28

M_CLK_DDR0

M_CLK_DDR#0

32 34 36 38 40

DDR_A_D20

DDR_A_D21

46 48 50

A11

A7 A6

A4 A2 A0

S0#

52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 204

DDR_A_DM2 DDR_A_D23

DDR_A_D22 DDR_A_D28DDR_A_D29

DDR_A_D25DDR_A_D24 DDR_A_DQS#3

DDR_A_DQS3 DDR_A_D31

DDR_A_D30 DDR_CKE1_DIMMA

DDR_A_MA14 DDR_A_MA11 DDR_A_MA6 DDR_A_MA4

DDR_A_MA2 DDR_A_MA0

DDR_A_BS#1 DDR_A_RAS# DDR_CS0_DIMMA#

M_ODT0 DDR_A_MA13

DDR_A_D39 DDR_A_D38

DDR_A_DM4 DDR_A_D34

DDR_A_D33 DDR_A_D45

DDR_A_D43 DDR_A_DQS#5

DDR_A_DQS5 DDR_A_D47

DDR_A_D42 DDR_A_D52

DDR_A_D53 M_CLK_DDR1

M_CLK_DDR#1 DDR_A_DM6 DDR_A_D51DDR_A_D54

DDR_A_D55

DDR_A_D56 DDR_A_DQS#7

DDR_A_DQS7 DDR_A_D62

DDR_A_D63

R455

R453

10K_0402_5%

2.2U_0805_16V4Z

2.2U_0805_16V4Z C363

C363

M_CLK_DDR0 <7> M_CLK_DDR#0 <7>

PM_EXTTS#0 <7>

DDR_CKE1_DIMMA <7>

DDR_A_BS1 <8> DDR_A_RAS# <8> DDR_CS0_DIMMA# <7>

M_ODT0 <7>

M_CLK_DDR1 <7> M_CLK_DDR#1 <7>

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

Date: Sheet of

Compal Electronics, Inc.

DDRII-SODIMM SLOT1

LA3262P_DIS__M64

C362

V_DDR_MCH_REF <7,14,48>

13 57Tuesday, August 21, 2007

0.1U_0402_16V4Z

DDR_B_DQS#[0..7]<8>

DDR_B_D[0..63]<8> DDR_B_DM[0..7]<8>

DDR_B_DQS[0..7]<8>

DDR_B_MA[0..14]<7,8>

D D

C C

B B

A A

Layout Note: Place near JP10

+1.8V

2.2U_0805_16V4Z

2.2U_0805_16V4Z C236

C236

Layout Note: Place one cap close to every 2 pullup resistors terminated to +0.9VS

+0.9V

0.1U_0402_16V4Z

C176

DDR_B_MA1 DDR_B_MA3

DDR_B_BS#0 DDR_B_MA10

DDR_B_MA0 DDR_B_BS#1

DDR_B_RAS# DDR_CS2_DIMMB#

DDR_B_CAS# DDR_B_WE#

DDR_CS3_DIMMB# M_ODT2 M_ODT3

DDR_CKE3_DIMMB

0.1U_0402_16V4Z

C265

0.1U_0402_16V4Z

C179

RP14

1 4 2 3

RP17

56_0404_4P2R_5%

1 4 2 3

RP16

56_0404_4P2R_5%

1 4 2 3

RP18

56_0404_4P2R_5%

1 4 2 3

RP19

56_0404_4P2R_5%

1 4 2 3

RP23

56_0404_4P2R_5%

2 3 1 4

56_0404_4P2R_5%

1 2

R1743

56_0402_5%

2.2U_0805_16V4Z

2.2U_0805_16V4Z C247

C247

0.1U_0402_16V4Z

C186

C159

0.1U_0402_16V4Z

C213

C197

+0.9V

RP10 56_0404_4P2R_5%RP10 56_0404_4P2R_5%

RP11 56_0404_4P2R_5%RP11 56_0404_4P2R_5%

RP12 56_0404_4P2R_5%RP12 56_0404_4P2R_5%

RP13 56_0404_4P2R_5%RP13 56_0404_4P2R_5%

RP15 56_0404_4P2R_5%RP15 56_0404_4P2R_5%

RP21 56_0404_4P2R_5%RP21 56_0404_4P2R_5%

RP9

56_0404_4P2R_5%

2.2U_0805_16V4Z C164

C164

0.1U_0402_16V4Z

C220

14 23

0.1U_0402_16V4Z

0.1U_0402_16V4Z C166

C166

0.1U_0402_16V4Z

C183

C210

DDR_B_MA9 DDR_B_MA12

DDR_B_MA14 DDR_B_MA11

DDR_B_MA5 DDR_B_MA8

DDR_B_MA7 DDR_B_MA6

DDR_B_MA4 DDR_B_MA2

DDR_B_MA13

DDR_B_BS#2 DDR_CKE2_DIMMB

0.1U_0402_16V4Z

C219

0.1U_0402_16V4Z

C199

0.1U_0402_16V4Z

C188

0.1U_0402_16V4Z

C173

Layout Note: Place these resistor closely JP10,all trace length Max=1.5"

C218

C161

0.1U_0402_16V4Z

C177

C163

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

+1.8V

JP10

VREF

11 13 15 17 19 21 23 25 27 29 31 33 35 37 39

41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97

conn@

0.1U_0402_16V4Z

Deciphered Date

5 7 9

VSS DQ0 DQ1 VSS DQS0# DQS0 VSS DQ2 DQ3 VSS DQ8 DQ9 VSS DQS1# DQS1 VSS DQ10 DQ11 VSS

FOX_ASOA426-M4R-TR

SO-DIMM B STANDARD

Bottom side

DDR_B_D0 DDR_B_D1

DDR_B_DQS#0 DDR_B_DQS0

DDR_B_D2 DDR_B_D3

DDR_B_D8 DDR_B_D9

DDR_B_DQS#1 DDR_B_DQS1

DDR_B_D10 DDR_B_D11

DDR_B_D20 DDR_B_DQS#2

DDR_B_DQS2 DDR_B_D18

DDR_B_D19 DDR_B_D28

DDR_B_DM3

DDR_B_D30 DDR_B_D31

DDR_CKE2_DIMMB<7>

DDR_B_BS2<8>

DDR_B_BS0<8> DDR_B_WE#<8>

DDR_B_CAS#<8>

DDR_CS3_DIMMB#<7>

M_ODT3<7>

ICH_SMBDATA<13,15,26>

ICH_SMBCLK<13,15,26>

+3VM

DDR_CKE2_DIMMB

DDR_B_BS#2 DDR_B_MA12

DDR_B_MA9 DDR_B_MA8

DDR_B_MA5 DDR_B_MA3 DDR_B_MA1

DDR_B_MA10 DDR_B_BS#0 DDR_B_WE#

DDR_B_CAS# DDR_CS3_DIMMB#

M_ODT3 DDR_B_D32

DDR_B_D33 DDR_B_DQS#4

DDR_B_DQS4 DDR_B_D34

DDR_B_D35 DDR_B_D40

DDR_B_D41 DDR_B_DM5 DDR_B_D42

DDR_B_D43 DDR_B_D48

DDR_B_D49

DDR_B_DQS#6 DDR_B_DQS6

DDR_B_D51 DDR_B_D50

DDR_B_D56 DDR_B_D61 DDR_B_D57

DDR_B_DM7 DDR_B_D59

DDR_B_D58 ICH_SMBDATA

ICH_SMBCLK

C312

2.2U_0603_6.3V4Z

2006/09/25 2006/09/25

C301

Compal Secret Data

DQ12 DQ13

CK0#

DQ14 DQ15

DQ20 DQ21

DQ22 DQ23

DQ28 DQ29

DQS3#

DQS3 DQ30

DQ31

NC/CKE1

NC/A15 NC/A14

RAS#

ODT0

NC/A13

DQ36 DQ37

DQ38 DQ39

DQ44 DQ45

DQS5#

DQS5 DQ46

DQ47 DQ52

DQ53

CK1#

DQ54 DQ55

DQ60 DQ61

DQS7#

DQS7 DQ62

DQ63

GND

VSS DQ4 DQ5 VSS DM0 VSS DQ6 DQ7 VSS

VSS DM1 VSS CK0

VSS

VSS DM2

VSS

VSS VDD

VDD

VDD VSS

VSS DM4 VSS

VSS

VSS CK1

VSS DM6 VSS

VSS

VSS SAO

+1.8V

V_DDR_MCH_REF

DDR_B_D5

DDR_B_D4

6 8

DDR_B_DM0

10 12

DDR_B_D6

DDR_B_D7

16 18

DDR_B_D12

DDR_B_D13

22 24

DDR_B_DM1

26 28

M_CLK_DDR3

M_CLK_DDR#3

32 34

DDR_B_D14

DDR_B_D15

38 40

DDR_B_D21DDR_B_D17

DDR_B_D16

46 48 50

A11

A7 A6

A4 A2

A0 BA1 S0#

SA1

DDR_B_DM2

52 54

DDR_B_D22

DDR_B_D23

58 60

DDR_B_D26

DDR_B_D24DDR_B_D25

64 66

DDR_B_DQS#3

DDR_B_DQS3

70 72

DDR_B_D29

DDR_B_D27

76 78

DDR_CKE3_DIMMB

80 82 84

DDR_B_MA14

86 88

DDR_B_MA11

DDR_B_MA7

DDR_B_MA6

94 96

DDR_B_MA4

DDR_B_MA2

100

DDR_B_MA0

102 104

DDR_B_BS#1

106

DDR_B_RAS#

108

DDR_CS2_DIMMB#

110 112

M_ODT2

114

DDR_B_MA13

116 118 120 122

DDR_B_D36

124

DDR_B_D37

126 128

DDR_B_DM4

130 132

DDR_B_D39

134

DDR_B_D38

136 138

DDR_B_D44

140

DDR_B_D45

142 144

DDR_B_DQS#5

146

DDR_B_DQS5

148 150

DDR_B_D46

152

DDR_B_D47

154 156

DDR_B_D52

158

DDR_B_D53

160 162

M_CLK_DDR2

164

M_CLK_DDR#2

166 168

DDR_B_DM6

170 172

DDR_B_D54

174

DDR_B_D55

176 178

DDR_B_D60

180 182 184

DDR_B_DQS#7

186

DDR_B_DQS7

188 190

DDR_B_D62

192

DDR_B_D63

194 196 198 200 204

R257

1 2

10K_0402_5%

R254

Title

Size Document Number Rev

Date: Sheet

Date: Sheet of

0.1U_0402_16V4Z

2.2U_0805_16V4Z

M_CLK_DDR3 <7> M_CLK_DDR#3 <7>

PM_EXTTS#1 <7>

DDR_CKE3_DIMMB <7>

DDR_B_BS1 <8> DDR_B_RAS# <8> DDR_CS2_DIMMB# <7>

M_ODT2 <7>

M_CLK_DDR2 <7> M_CLK_DDR#2 <7>

C89

+3VM

Compal Electronics, Inc.

DDRII-SODIMM SLOT2

LA3262P_DIS__M64

V_DDR_MCH_REF <7,13,48>

C90

14 57Tuesday, August 21, 2007

PCI

SRC

CPU

CLKSEL1

FSLA

CLKSEL0

MHz

200

166

MHz

1000

100

MHz

33.30

33.3

+3VM

1 2

R1066 0_1206_5%

FSLC1FSLB

CLKSEL2

FSB Frequency Selet:

D D

CPU Driven

(Default)

Stuff

No Stuff

Stuff

667MHz

No Stuff

Stuff

800MHz

CPU_BSEL0<5>

C C

CPU_BSEL1<5>

B B

CPU_BSEL2<5>

A A

18P_0402_50V8J

FSC

14.31818MHZ_16P

C509

No Stuff

2.2K_0402_5%

FSA

0_0402_5%

10K_0402_5%

0_0402_5%

R1078

0_0402_5%

1 2

R1107

R1130

1 2

R1135

Routing the trace at least 10mil

R1107 R1135 R1083

R1074 R1086 R1098 R1113 R1139

R1139 R1135R1135 R1139

R1083

R1107 R1098

R1113

R1074R1086

R1128

R1135 R1139

R1083

R1086

R1098

R1128

R1113

+VCCP

MCH_CLKSEL0 <7>

MCH_CLKSEL1 <7>

MCH_CLKSEL2 <7>

For ITP_EN, 0 =SRC8/SRC8#; 1 = ITP/ITP# For 27_SEL, 0 = Enable DOT96 & SRC1,

1 2

R1083

FSB

+VCCP

R1074

1 2

R1079

1K_0402_5%

R1086

R1086 1K_0402_5%@

1K_0402_5%@

R1098

R1098 1K_0402_5%@

1K_0402_5%@

1 2

R1105

1K_0402_5%

R1113

@R1113

0_0402_5%

R1128

R1128 1K_0402_5%@

1K_0402_5%@

1 2

R1131

1K_0402_5%

R1139

@R1139

0_0402_5%

R1107

R1074

56_0402_5%

For PCI2_TME, 0 = Overclocking of CPU and SRC Allowed

CLK_XTAL_OUT

CLK_XTAL_IN

C505

C505 18P_0402_50V8J

18P_0402_50V8J

+3VS +3VS +3VS

1 2

ITP_EN 27_SEL

1 2

R1128

1111 Add CLRP4,CLRP5 for 667/800 FSB select SHORT CLRP5, NO SHORT CLRP4 -- FSB 800 SHORT CLRP4, NO SHORT CLRP5 -- FSB 667

CLKSATAREQ#<26>

CLK_DEBUG_PORT<31,36>

CLK_PCI_SIO<35> CLK_PCI_TCG<36> CLK_PCI_EC<37>

CLK_PCI_PCM<31>

CLK_PCI_ICH<24>

CLK_48M_ICH<26>

CLK_14M_ICH<26> CLK_14M_SIO<35> CLK_14M_KBC<37>

1= Enable SRC0 & 27MHz

1 = Overclocking of CPU and SRC NOT allowed

R1245

R1245 10K_0402_5%

10K_0402_5%

R1247

R1247 10K_0402_5%

10K_0402_5%

+3VM_CK505

CLKREQ#_B<7>

1 2

R1690

R1690 10K_0402_5%

10K_0402_5%

R1691

@ R1691

10K_0402_5%

C1165

C1165 10U_0603_6.3V6M

10U_0603_6.3V6M

R1077 33_0402_5%

1 2

C1166

0.1U_0402_16V4Z

R1068 0_1206_5%R1068 0_1206_5%

1 2

+1.25VM

C1172 10U_0603_6.3V6M

10U_0603_6.3V6M

+1.25VM_CK505

R1692475_0402_1%

1 2 1 2

R1693 475_0402_1%

1 2 1 2 1 2

1 2

PCI2_TME

1 2

1 2 1 2 1 2

1 2

R1108

R1108 10K_0402_5%

10K_0402_5%

R1246

R1246 10K_0402_5%

10K_0402_5%

R109722_0402_5%

R111412_0402_5%

R114012_0402_5%

R114012_0402_5% R111012_0402_5%

R111012_0402_5% R114112_0402_5%

R114112_0402_5% R111722_0402_5%

R111722_0402_5%

R108733_0402_1%

R108733_0402_1% R108833_0402_1%

R108833_0402_1% R108933_0402_1%

R108933_0402_1%

+1.25VM_CK505

C1167

0.1U_0402_16V4Z

C1173

C1172 2

+3VM_CK505

PCI_CLK1 PCI2_TME PCI_CLK3 27_SEL ITP_EN

CLK_XTAL_IN CLK_XTAL_OUT

FSA

FSB

FSC

C1168

0.1U_0402_16V4Z

Place close to U7

0.1U_0402_16V4Z

16 61

39 55

12 20 26

36 49

60 59

11 15 19 52 23 29 58

C1174

0.1U_0402_16V4Z

VDD_PCI

VDD48 VDDPLL3 VDDREF

VDDSRC VDDCPU

VDD96_IO VDDPLL3_IO VDDSRC_IO

VDDSRC_IO VDDCPU_IO

PCI0/CR#_A

PCI1/CR#_B

PCI2/TME

PCI3

PCI4/27_Select

PCIF5/ITP_EN

X1 X2

USB_48MHZ/FSLA

FSLB/TEST MODE

REF0/FSLC/TEST_SEL

VDDSRC_IO

GNDSRC

GNDPCI GND48 GND GND GNDCPU GNDSRC GNDSRC GNDREF

* Internal Pull-Up Resistor

* Internal Pull-Up Resistor ** Internal Pull-Down Resistor

** Internal Pull-Down Resistor

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C1169

0.1U_0402_16V4Z

10U_0603_6.3V6M

C1353

0.1U_0402_16V4Z

SRC1/SE1/27MHz_NonSS

SRC1#/SE2/27MHz_SS

CK_PWRGD/PD#

ICS9LPRS355AKLFT_TSSOP64

2006/09/25 2006/09/25

0.1U_0402_16V4Z

C1354

SCLK

SDATA

PCI_STOP#

CPU_STOP#

CPU0

CPU0#

CPU1_F

CPU1#_F

SRC8/ITP

SRC8#/ITP#

SRC10#

SRC10

SRC11/CR#_H

SRC11#/CR#_G

SRC9

SRC9#

SRC7/CR#_F

SRC7#/CR#_E

SRC6

SRC6#

SRC4

SRC4#

SRC3/CR#_C

SRC3#/CR#_D

SRC2/SATA

SRC2#/SATA#

SRC0/DOT96

SRC0/DOT96#

C1170

0.1U_0402_16V4Z

+1.25VM_CK505

C1355

64 63

38 37

54 53

51 50

47 46

35 34

33 32

30 31

44 43

41 40

27 28

24 25

21 22

17 18

13 14

Compal Secret Data

C1171

0.1U_0402_16V4Z

R1033 0_0402_5%@ R1033 0_0402_5%@

R_CPU_XDP

R1447

R_CPU_XDP#

R1448

R1448 R1143

@R1143

R1695

CLKREQ#_H R_CLKREQ#_G

R_CLKREQ#_F CLKREQ#_F R_CLKREQ#_E CLKREQ#_E

R_27MHz R_27MSSC

R1694

R1686 0_0402_5%

R1686 0_0402_5% R1687 0_0402_5%R1687 0_0402_5%

Deciphered Date

1 2 1 2 1 2 1 2

R1900 475_0402_1%

R1901 475_0402_1%@R1901 475_0402_1%@

1 2 1 2

12 12

0_0402_5%

0_0402_5% 0_0402_5%

0_0402_5%

1 2

R149 10K_0402_5%

R149 10K_0402_5% 475_0402_1%

475_0402_1% 475_0402_1%

475_0402_1% R150 10K_0402_5%

R150 10K_0402_5%

1 2

11/20 For EMI request to install R1687

C353

C353 C357

C357 C372

C372 C373

C373 C374

C374 C375

C375 C376

C376 C378

C378 C379

C379 C380

C380

ICH_SMBCLK <13,14,26> ICH_SMBDATA <13,14,26>

H_STP_PCI# <26> H_STP_CPU# <26>

CLK_CPU_BCLK <4> CLK_CPU_BCLK# <4>

CLK_MCH_BCLK <7> CLK_MCH_BCLK# <7>

CLK_CPU_XDP <4> CLK_PCIE_Rob <31> CLK_PCIE_Rob# <31> CLK_CPU_XDP# <4>

CLK_PCIE_DOCK# <39> CLK_PCIE_DOCK <39>

+3VS

CPPE# <39>

CLKREQ#_G <31>

+3VS

CLK_PCIE_MCARD <31> CLK_PCIE_MCARD# <31>

1 2

R1899 10K_0402_5%

R1902 10K_0402_5%@R1902 10K_0402_5%@

1 2

CLK_PCIE_VGA <18> CLK_PCIE_VGA# <18>

CLK_MCH_3GPLL <7> CLK_MCH_3GPLL# <7>

CLK_PCIE_ICH <26>

CLK_PCIE_ICH# <26>

CLK_PCIE_SATA <25> CLK_PCIE_SATA# <25>

27M_CLK <19> 27M_SSC <19>

CK_PWRGD <26>

+3VS

Title

Size Document Number Rev

Date: Sheet

CLK_48M_ICH

5P_0402_50V8C

CLK_14M_ICH

4.7P_0402_50V8C

CLK_PCI_ICH

4.7P_0402_50V8C

CLK_14M_KBC

4.7P_0402_50V8C

CLK_14M_SIO

4.7P_0402_50V8C

CLK_PCI_EC

4.7P_0402_50V8C

CLK_PCI_TCG

4.7P_0402_50V8C

CLK_PCI_PCM

4.7P_0402_50V8C

CLK_PCI_SIO

4.7P_0402_50V8C

CLK_DEBUG_PORT

5P_0402_50V8C

CLKREQ#_F CLKREQ#_E <19,31>

Compal Electronics, Inc.

Clock generator

LA3262P_DIS__M64

15 57Tuesday, August 21, 2007

CRT Connector

1 1

+5VS

0.1U_0402_16V4Z

2 2

C359

M_HSYNC<19>

M_VSYNC<19>

SN74AHCT1G125GW_SOT353-5

U33

U33 SN74AHCT1G125GW_SOT353-5

SN74AHCT1G125GW_SOT353-5

OE#

A2Y

L_BLUE<39>

L_GREEN<39>

L_RED<39>

0315 add

+5VS

HSYNC_G_A

VSYNC_G_A

OE#

A2Y

U54

C323

18P_0402_50V8J

150_0402_1%

R545

1 2

0_0603_5%

R546

1 2

0_0603_5%

C322

18P_0402_50V8J

Place close to docking connector

layout note: D_HSYNC & D_VSYNC should be routed to docking connector then to VGA connector

R174

150_0402_1%

R173

@R173

R171

2007,0125 change

D_VSYNC

150_0402_1%

D_HSYNC

+CRTVDD+RCRT_VCC+5VS

1.1A_6VDC_FUSE

2007,0125 change

R542 BK1608LL560-T_0603 R542 BK1608LL560-T_0603

1 2

R543 BK1608LL560-T_0603 R543 BK1608LL560-T_0603

1 2

C314

39P_0402_50V8C

D_HSYNC <39>

D_VSYNC <39>

R544 BK1608LL560-T_0603 R544 BK1608LL560-T_0603

1 2

C310

39P_0402_50V8C

C317

18P_0402_50V8J

0315 add

C318

C316

18P_0402_50V8J

D_DDCDATA<39>

D_DDCCLK<39>

C313

39P_0402_50V8C

RED_R

GREEN_R

BLUE_R

D18

2 1

CH491D_SC59

0.1U_0402_16V4Z

C315

2.2K_0402_5%

W=40mils

1 7

2 8

3 9

4 10 15

SUYIN_070912FR015S207CR

conn@

+CRTVDD +CRTVDD

R162

D_DDCDATA

D_DDCCLK

JP2

16 17

R183

2.2K_0402_5%

BLUE_R GREEN_R RED_R

Q46

1 3

RHU002N06_SOT323

1 3

Q52

RHU002N06_SOT323

DAN217_SC59

+3VS

1 2

2.2K_0402_5%

R1921 2.2K_0402_5%R1921 2.2K_0402_5%

R1922

D20

D19

DAN217_SC59

Place close to JP2

DAN217_SC59@

+CRTVDD

Place close to docking connector

DDC1_DATA <19>

DDC1_CLK <19>

TV-Out Connector

0_0603_5%

LUMA<19,39> CRMA<19,39>

COMP<19,39>

R185

@R185

R187

@R187

5.6P_0402_50V8D

C333

150_0402_1%

C355

5.6P_0402_50V8D

5.6P_0402_50V8D C354

C354

3 3

0315 add

R184

@R184

150_0402_1%

0_0603_5%

R547

1 2

0_0603_5%

R548

1 2

0_0603_5%

R549

1 2

5.6P_0402_50V8D

Place close to JP1

DAN217_SC59

@D3

DAN217_SC59

@D5

TV_LUMA TV_CRMA TV_COMP

DAN217_SC59

@D1

SUYIN_33007SR-07T1-C

+3VS

JP1

1 2 3 4 5 6 7

conn@

Close to JP1

layout note: TV-out signals should be routed to JP30 then to JP1

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2006/09/25 2006/09/25

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

CRT & TVout Connector

LA3262P_DIS__M64

16 57Tuesday, August 21, 2007

B+_LCD

0802 (R1A) change for preventing 1206 Cap crack

LVDS CONN

JP35

D D

C C

42 43 44 45 46

41 42 43 44 45 46

ACES_88316-4000

conn@

40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

9 8 7 6 5 4 3 2 1

40 39 38 37 36 35 34 33 32 31 30 29 28

BKLT_PWM

27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1

C586 4.7U_0805_25V6K C586 4.7U_0805_25V6K

1 2 1 2

C587 68P_0402_50V8JC587 68P_0402_50V8J

1 2

C1629 4.7U_0805_25V6KC1629 4.7U_0805_25V6K

L62 KC FBM-L11-201209-221LMA30T_1210L62 KC FBM-L11-201209-221LMA30T_1210

+3VS

LCDVDD

+5VS_INV

TXCLK_U+ <19> TXCLK_U- <19>

TXOUT_U2+ <19> TXOUT_U2- <19>

TXOUT_U1+ <19> TXOUT_U1- <19>

TXOUT_U0+ <19> TXOUT_U0- <19>

TXOUT_L0- <19> TXOUT_L0+ <19>

TXOUT_L1- <19> TXOUT_L1+ <19>

TXOUT_L2- <19> TXOUT_L2+ <19>

TXCLK_L- <19> TXCLK_L+ <19>

ALS_EN <26>

DDC2_CLK <19> DDC2_DATA <19>

LCD POWER CIRCUIT

LCDVDD

R19

100_0402_1%

B+

RHU002N06_SOT323

VGA_ENAVDD<19>

100K_0402_1%

+3VALW

+3VS

LID_SW#<26,38> OPT_BL_ENA<19>

R502

Q6 DTC124EK_SC59

0_0402_5%

1 2

0_0402_5%@

1 2

LID_SW#

DTC124EK_SC59

1 2

R1728

R1729

R474

1 2

47K_0402_5%

+3V_U43

R501

1 2

100K_0402_1%

C29

0.1U_0402_16V4Z

+5VS

47K

U43A

U43A SN74LVC08APW_TSSOP14

SN74LVC08APW_TSSOP14

100K_0402_5%

R360

1 2

AO3413_SOT23

1 3

E_STAR

C31

4.7U_0805_10V4Z

Q53

Q53 DTA114YKA_SC59

DTA114YKA_SC59

10K

Q36

Q36 BSS138_SOT23

BSS138_SOT23

0.1U_0402_16V7K

E_STAR <41>

R12

1 2

1M_0402_5%

C28

1 2

+5VS_INV

+3VALWLCDVDD

C20

4.7U_0805_10V4Z@

B B

BLON_PWM<19>

R102 0_0402_5%R102 0_0402_5%

1 2

BKLT_PWM

Support 3V inverter

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2006/09/25 2006/09/25

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

LCD CONN.

LA3262P_DIS__M64

17 57Tuesday, August 21, 2007

D D

PEG_M_TXP0 PEG_M_TXN0

PEG_M_TXP1 PEG_M_TXN1

PEG_M_TXP2 PEG_M_TXN2

PEG_M_TXP3 PEG_M_TXN3

PEG_M_TXP4 PEG_M_TXN4

PEG_M_TXP5 PEG_M_TXN5

PEG_M_TXP6

VGA_RST#<24>

PEG_M_TXN6

PEG_M_TXP7 PEG_M_TXN7

PEG_M_TXP8 PEG_M_TXN8

PEG_M_TXP9 PEG_M_TXN9

PEG_M_TXP10 PEG_M_TXN10

PEG_M_TXP11 PEG_M_TXN11

PEG_M_TXP12 PEG_M_TXN12

PEG_M_TXP13 PEG_M_TXN13

PEG_M_TXP14 PEG_M_TXN14

PEG_M_TXP15 PEG_M_TXN15

CLK_PCIE_VGA CLK_PCIE_VGA#

C C

B B

U80A

AC30

PCIE_RX0P

AC31

PCIE_RX0N

AC29

PCIE_RX1P

AB29

PCIE_RX1N

AB31

PCIE_RX2P

AB30

PCIE_RX2N

AA31

PCIE_RX3P

AA30

PCIE_RX3N

W30

PCIE_RX4P

W31

PCIE_RX4N

W29

PCIE_RX5P

V29

PCIE_RX5N

V31

PCIE_RX6P

V30

PCIE_RX6N

U31

PCIE_RX7P

U30

PCIE_RX7N

P30

PCIE_RX8P

P31

PCIE_RX8N

P29

PCIE_RX9P

N29

PCIE_RX9N

N31

PCIE_RX10P

N30

PCIE_RX10N

M31

PCIE_RX11P

M30

PCIE_RX11N

K30

PCIE_RX12P

K31

PCIE_RX12N

K29

PCIE_RX13P

J29

PCIE_RX13N

J31

PCIE_RX14P

J30

PCIE_RX14N

H31

PCIE_RX15P

H30

PCIE_RX15N

Clock

AD29

PCIE_REFCLKP

AD30

PCIE_REFCLKN

AC28

RSVD

AC27

RSVD

AG25

PERSTB

216PTAKA13FG M62-S_BGA632

PART 1 OF 6

P C

C I

E X

X P

P R

R E

E S

S S

I N

N T

T E

E R

R F

F A

A C

C E

PCIE_TX0P PCIE_TX0N

PCIE_TX1P PCIE_TX1N

PCIE_TX2P PCIE_TX2N

PCIE_TX3P PCIE_TX3N

PCIE_TX4P PCIE_TX4N

PCIE_TX5P PCIE_TX5N

PCIE_TX6P PCIE_TX6N

PCIE_TX7P PCIE_TX7N

PCIE_TX8P PCIE_TX8N

PCIE_TX9P PCIE_TX9N

PCIE_TX10P PCIE_TX10N

PCIE_TX11P PCIE_TX11N

PCIE_TX12P PCIE_TX12N

PCIE_TX13P PCIE_TX13N

PCIE_TX14P PCIE_TX14N

PCIE_TX15P PCIE_TX15N

Calibration

PCIE_CALRN PCIE_CALRP

PCIE_CALI

PEG_M_RXP0

AA28

PEG_M_RXN0

AA27

PEG_M_RXP1

AA25

PEG_M_RXN1

AA24

PEG_M_RXP2

Y28

PEG_M_RXN2

Y27

PEG_M_RXP3

Y25

PEG_M_RXN3

Y24

PEG_M_RXP4

V28

PEG_M_RXN4

V27

PEG_M_RXP5

V25

PEG_M_RXN5

V24

PEG_M_RXP6

T28

PEG_M_RXN6

T27

PEG_M_RXP7

T25

PEG_M_RXN7

T24

PEG_M_RXP8

P28

PEG_M_RXN8

P27

PEG_M_RXP9

P25

PEG_M_RXN9

P24

PEG_M_RXP10

M28

PEG_M_RXN10

M27

PEG_M_RXP11

M25

PEG_M_RXN11

M24

PEG_M_RXP12

L28

PEG_M_RXN12

L27

PEG_M_RXP13

L25

PEG_M_RXN13

L24

PEG_M_RXP14

J28

PEG_M_RXN14

J27

PEG_M_RXP15

G28

PEG_M_RXN15

G27

AF25 AE25 AE23

R1904 2K_0402_1%R1904 2K_0402_1% R1887 562_0402_1%R1887 562_0402_1% R1737

R1737

1 2 1 2 1 2

C1380 0.1U_0402_16V4ZC1380 0.1U_0402_16V4Z C1381 0.1U_0402_16V4ZC1381 0.1U_0402_16V4Z

C1382 0.1U_0402_16V4ZC1382 0.1U_0402_16V4Z C1383 0.1U_0402_16V4ZC1383 0.1U_0402_16V4Z

C1384 0.1U_0402_16V4ZC1384 0.1U_0402_16V4Z C1385 0.1U_0402_16V4ZC1385 0.1U_0402_16V4Z

C1386 0.1U_0402_16V4ZC1386 0.1U_0402_16V4Z C1387 0.1U_0402_16V4ZC1387 0.1U_0402_16V4Z

C1388 0.1U_0402_16V4ZC1388 0.1U_0402_16V4Z C1389 0.1U_0402_16V4ZC1389 0.1U_0402_16V4Z

C1390 0.1U_0402_16V4ZC1390 0.1U_0402_16V4Z C1391 0.1U_0402_16V4ZC1391 0.1U_0402_16V4Z

C1392 0.1U_0402_16V4ZC1392 0.1U_0402_16V4Z C1393 0.1U_0402_16V4ZC1393 0.1U_0402_16V4Z

C1394 0.1U_0402_16V4ZC1394 0.1U_0402_16V4Z C1395 0.1U_0402_16V4ZC1395 0.1U_0402_16V4Z

C1396 0.1U_0402_16V4ZC1396 0.1U_0402_16V4Z C1397 0.1U_0402_16V4ZC1397 0.1U_0402_16V4Z

C1398 0.1U_0402_16V4ZC1398 0.1U_0402_16V4Z C1399 0.1U_0402_16V4ZC1399 0.1U_0402_16V4Z

C1400 0.1U_0402_16V4ZC1400 0.1U_0402_16V4Z C1401 0.1U_0402_16V4ZC1401 0.1U_0402_16V4Z

C1402 0.1U_0402_16V4ZC1402 0.1U_0402_16V4Z C1403 0.1U_0402_16V4ZC1403 0.1U_0402_16V4Z

C1404 0.1U_0402_16V4ZC1404 0.1U_0402_16V4Z C1405 0.1U_0402_16V4ZC1405 0.1U_0402_16V4Z

C1406 0.1U_0402_16V4ZC1406 0.1U_0402_16V4Z C1407 0.1U_0402_16V4ZC1407 0.1U_0402_16V4Z

C1408 0.1U_0402_16V4ZC1408 0.1U_0402_16V4Z C1409 0.1U_0402_16V4ZC1409 0.1U_0402_16V4Z

C1410 0.1U_0402_16V4ZC1410 0.1U_0402_16V4Z C1411 0.1U_0402_16V4ZC1411 0.1U_0402_16V4Z

PCIE_1.2V

1.47K_0402_1%

M62: R1737-->1.47k ohm 1% M72: R1887-->10k ohm 1%

M62: R1887-->562 ohm 1% M72: R1887-->1.27k ohm 1%

PEG_RXP0 PEG_RXN0

PEG_RXP1 PEG_RXN1

PEG_RXP2 PEG_RXN2

PEG_RXP3 PEG_RXN3

PEG_RXP4 PEG_RXN4

PEG_RXP5 PEG_RXN5

PEG_RXP6 PEG_RXN6

PEG_RXP7 PEG_RXN7

PEG_RXP8 PEG_RXN8

PEG_RXP9 PEG_RXN9

PEG_RXP10 PEG_RXN10

PEG_RXP11 PEG_RXN11

PEG_RXP12 PEG_RXN12

PEG_RXP13 PEG_RXN13

PEG_RXP14 PEG_RXN14

PEG_RXP15 PEG_RXN15

CLK_PCIE_VGA<15> CLK_PCIE_VGA#<15>

PEG_RXP[0..15]<9> PEG_RXN[0..15]<9> PEG_M_TXP[0..15]<9> PEG_M_TXN[0..15]<9>

PEG_RXP[0..15] PEG_RXN[0..15] PEG_M_TXP[0..15] PEG_M_TXN[0..15]

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2006/09/25 2006/09/25

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

M62-S PCIE interface

LA3262P_DIS__M64

18 57Tuesday, August 21, 2007

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