COMPAL LA-3262P Schematics

A

1 1

2 2

B

C

D

E

Compal confidential

Schematics Document

Mobile Merom uFCPGA with Intel Crestline + ICH8-M core logic

3 3

IBT00 LA-3262P Discrete VGA (M64)

2007-08-02

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2006/09/25 2006/09/25

REV:1A

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

D

Date: Sheet

Compal Electronics, Inc.

Cover Sheet

LA3262P_DIS__M64

E

1A

of

157Tuesday, August 21, 2007

A

Compal confidential

File Name : LA-3262P

B

C

Chimay Discrete

D

E

1 1

Thermal Sensor ADM1032ARMZ

P4

Fan conn

P4

CRT & TV OUT

P16

LVDS Panel Interface

P17

DVI (Docking)

2 2

P33

ATI M64S

P18, 19, 20, 21, 22, 23

PCIE

Intel Crestline MCH

DMI X4

PCI-E BUS

10/100/1000 LAN

Mini-Card

Intel 82566MM

P29

RJ45/11 CONN

3 3

P30

LED

P30

CardBus Controller & PCMCIA conn

Ricoh R5C853

P31

Slot 0/Smart Card

1394 port

P34

6in1 Slot

PCI

daughter board

RTC CKT.

P19

Mobile Merom

uFCPGA-478 CPU

H_A#(3..35) H_D#(0..63)

FCBGA 1299

(PM)

P7, 8, 9, 10, 11, 12

Intel ICH8-M

mBGA-676

P4, 5, 6

FSB

667/800MHz 1.05V

C-Link

USB2.0

Azalia

SATA Master

P24, 25, 26, 27

PATA Slave

SPI

SPI ROM & Debug port 16Mb*2 or 32Mb*1

LPC BUS

DDR2 667MHz 1.8V

Dual Channel

P36

DDR2-SO-DIMM X2

BANK 0, 1, 2, 3

P13, 14

USB conn x2 (Docking)

FingerPrinter AES1610 USBx1

USB conn x3

BT Conn

Mini-Card WWAN

P25P25

Audio CKT

AD1981HD

P32

SATA HDD Connector

P28

Multi-bay II Connector

P28

P33

P34

P28

CK505

Clock Generator ICS 9LPRS355

P15

daughter board

MDC

P38

AMP & Audio Jack

MAX9710

P33

Docking CONN.

*RJ-45(LED*2) *RJ-11(Pass Through) *CRT *COMPOSITE Video Out *TVOUT *DVI *LINE IN

P33

*LINE OUT

Power OK CKT.

P35

4 4

Power On/Off CKT.

P32

TPM1.2 SLB9635TT

P36

Touch Pad CONN.

P38 P38

SMSC KBC 1070

P37

Int.KBD

SMSC Super I/O

LPC47N217

COM1 LPT ( Docking ) ( Docking )

P33 P33

P35

*PCI-E x2 *Serial Port *Parallel Port *PS/2 x2 *USB x2 *DC JACK

DC/DC Interface CKT.

P34

A

TrackPoint CONN.

B

P38

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2006/09/25 2006/09/25

Compal Secret Data

Deciphered Date

D

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

Block Diagram

LA3262P_DIS__M64

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257Tuesday, August 21, 2007

1A

A

Voltage Rails

power plane

State

S0

S3/M1

S3

S5 S4/AC

S5 S4/ Battery only

S5 S4/AC & Battery don't exist

1 1

PCI Devices

EXTERNAL

CARD BUS & 1394

DMA Channel DMA0 DMA1 DMA2 DMA3 DMA4 DMA5 DMA6 DMA7

USB PORT#

O MEANS ON X MEANS OFF

+B LDO3 LDO5

O

O O O O

X

Destination 0 1 2 3 4 5 6 7 8 9

Walk-up0 (Right side)

Fingerprint

Reserve

WWAN

Walk-up1 (Left Side)

Walk-up2 (Left Side)

Bluetooth

Reserve

Docking

+5VS +3VS +2.5VS +1.8VS

+5VALW +3VALW

O

O O O

X

+1.8V

+5V

+0.9V

+1.5VS +1.25VS +VGA_CORE +CPU_CORE +VCCP

OO

O O

X

X XX X

X

XXX

IDSEL# REQ/GNT# PIRQ AD22 2 C,D,E,G

Device MODEM / LAN ECP FLOPPY DISK AUDIO (Cascade) Unused Unused Unused

+3VM +1.05VM

+1.25VM

O

O O O

X X

CLOCK

O

O O O

X X

IRQ

0 1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16

17

18

19

20

21 22

23

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

Device

System Timer

Keyboard

N/A

Serial port (COM2),LAN/Modem

Serial port (COM1)

Audio/VGA

Floppy

Parallel port

System CMOS/Real-time clock

Microsoft ACPI

N/A,Momem,LAN

Mass strorage control/ PCI simple communication control

synactic PS2 port GlidePAD

Numeric Data Process

Primary IDE interface,HDD

Secondary IDE innterface,CD-ROM

Mobile Intel Crestline Express Chipset Family Microsoft UAA Bus Driver for High Definition Audio Intel 82801H (ICH8 Family) PCI Express Root Port -27D0 Broadcom NetXtreme Gigabit Ethernet

Intel 82801H (ICH8 Family)PCI Express Root Port - 27D2 Broadcom 802.11b/g WLAN Intel 82801H (ICH8 Family)USB Universal Host Controll Intel 82801H (ICH8 Family)USB Universal Host Controll Ricoh R5C853 Cardbus Control Ricoh R5C853 Integrates FlashMedia Control Ricoh R5C853 Gemcore based SmartCard Control Intel 82801H (ICH8 Family)PCI Express Root Port - 27D6 Intel 82801H (ICH8 Family)USB Universal Host Controll

Intel 82801H (ICH8 Family)USB Universal Host Controll Intel 82801H (ICH8 Family)USB2 Enhanced Host Controll

Intel 82801H (ICH8 Family)USB Universal Host Controll

SDA Standard Compliant SD Host Controller

HP Mobile Data Protection Sensor

Compal Secret Data

2006/09/25 2006/09/25

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

Notes List

LA3262P_DIS__M64

357Tuesday, August 21, 2007

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1A

5

D D

H_A#[3..16]<7>

H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16

H_NMI<25> H_SMI#<25>

12

R1255

56_0402_5%@

B

2

C

Q85

Q85 MMBT3904_SOT23

MMBT3904_SOT23

H_ADSTB#0 H_REQ#0

H_REQ#1 H_REQ#2

H_REQ#4

H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 H_A#32 H_A#33 H_A#34 H_A#35 H_ADSTB#1

H_A20M# H_FERR# H_IGNNE#

H_STPCLK# H_INTR H_NMI H_SMI#

OCP# <26,50>

H_ADSTB#0<7>

H_REQ#0<7> H_REQ#1<7> H_REQ#2<7> H_REQ#3<7> H_REQ#4<7>

C C

B B

A A

H_A#[17..35]<7>

H_ADSTB#1<7>

H_A20M#<25>

H_FERR#<25>

H_IGNNE#<25> H_STPCLK#<25>

H_INTR<25>

+VCCP

E

H_PROCHOT# OCP#

E

3 1

@

JP12A

J4

A[3]#

L5

A[4]#

L4

A[5]#

K5

A[6]#

M3

A[7]#

N2

A[8]#

J1

A[9]#

N3

A[10]#

P5

A[11]#

P2

A[12]#

L2

A[13]#

P4

A[14]#

P1

A[15]#

R1

A[16]#

M1

ADSTB[0]#

K3

REQ[0]#

H2

REQ[1]#

K2

REQ[2]#

J3

REQ[3]#

L1

REQ[4]#

Y2

A[17]#

U5

A[18]#

R3

A[19]#

W6

A[20]#

U4

A[21]#

Y5

A[22]#

U1

A[23]#

R4

A[24]#

T5

A[25]#

T3

A[26]#

W2

A[27]#

W5

A[28]#

Y4

A[29]#

U2

A[30]#

V4

A[31]#

W3

A[32]#

AA4

A[33]#

AB2

A[34]#

AA3

A[35]#

V1

ADSTB[1]#

A6

A20M#

A5

FERR#

C4

IGNNE#

D5

STPCLK#

C6

LINT0

B4

LINT1

A3

SMI#

M4

RSVD[01]

N5

RSVD[02]

T2

RSVD[03]

V3

RSVD[04]

B2

RSVD[05]

C3

RSVD[06]

D2

RSVD[07]

D22

RSVD[08]

D3

RSVD[09]

F6

RSVD[10]

Merom Ball-out Rev 1a

ADDR GROUP 0 ADDR GROUP 1

ADS# BNR# BPRI#

DEFER#

DRDY#

DBSY#

BR0#

IERR#

INIT#

LOCK#

CONTROL

RESET#

RS[0]# RS[1]# RS[2]#

TRDY#

HIT#

HITM#

BPM[0]# BPM[1]# BPM[2]# BPM[3]#

PRDY# PREQ#

TCK

TDI TDO TMS

TRST#

XDP/ITP SIGNALS

DBR#

THERMAL

PROCHOT#

THERMDA THERMDC

ICH

THERMTRIP#

H CLK

BCLK[0] BCLK[1]

RESERVED

conn@

H1 E2 G5

H5 F21 E1

F1 D20

B3 H4 C1

F3 F4 G3 G2

G6 E4

AD4 AD3 AD1 AC4 AC2 AC1 AC5 AA6 AB3 AB5 AB6 C20

D21

H_THERMDA_R

A24 B25

C7

A22 A21

4

H_ADS#H_A#3 H_BNR# H_BPRI#

H_DEFER# H_DRDY# H_DBSY#

H_BR0# H_IERR#

H_INIT# H_LOCK# H_RESET#

H_RS#0 H_RS#1 H_RS#2 H_TRDY#H_REQ#3

H_HIT# H_HITM#

XDP_BPM#0 XDP_BPM#1 XDP_BPM#2 XDP_BPM#3 XDP_BPM#4 XDP_BPM#5 XDP_TCK XDP_TDI XDP_TDO XDP_TMS XDP_TRST#

XDP_DBRESET#

H_PROCHOT#

H_THERMTRIP#

CLK_CPU_BCLK CLK_CPU_BCLK#

H_ADS# <7> H_BNR# <7>

H_BPRI# <7>

H_DEFER# <7> H_DRDY# <7> H_DBSY# <7>

H_BR0# <7>

H_INIT# <25> H_LOCK# <7> H_RESET# <7>

H_RS#0 <7>

H_RS#1 <7>

H_RS#2 <7>

H_TRDY# <7>

H_HIT# <7> H_HITM# <7>

XDP_DBRESET# <26>

68_0402_5%

R23 0_0402_5%

1 2

R34 0_0402_5%

1 2

CLK_CPU_BCLK <15> CLK_CPU_BCLK# <15>

H_THERMDA, H_THERMDC routing together, Trace width / Spacing = 10 / 10 mil

R172

56_0402_5%

12

For Merom, R23 and R34 are 0ohm For Penryn, R23 and R34 are 100ohm.

12

H_THERMDA H_THERMDCH_THERMDC_R

H_PROCHOT# <49>

+VCCP

R410

H_THERMTRIP# <7,23,25>

11/20 Penryn support to add R23,R34

+VCCP

3

XDP Connector

XDP_BPM#5 XDP_BPM#4

XDP_BPM#3 XDP_BPM#2

XDP_BPM#1 XDP_BPM#0

C1099

H_PWRGOOD_R XDP_HOOK1

XDP_TCK

H_PWRGOOD_R<5>

+VCCP +VCCP

1

2

0.1U_0402_16V4Z

layout note: Change R237 to 649 ohm if using XTP to ITP adapter

JP51

1

GND0

3

OBSFN_A0

5

OBSFN_A1

7

GND2

9

OBSDATA_A0

11

OBSDATA_A1

13

GND4

15

OBSDATA_A2

17

OBSDATA_A3

19

GND6

21

OBSFN_B0

23

OBSFN_B1

25

GND8

27

OBSDATA_B0

29

OBSDATA_B1

31

GND10

33

OBSDATA_B2

35

OBSDATA_B3

37

GND12

39

PWRGOOD/HOOK0

41

HOOK1

43

VCC_OBS_AB

45

HOOK2

47

HOOK3

49

GND14

51

SDA

53

SCL

55

TCK1

57

TCK0

59

GND16

Thermal Sensor ADM1032ARMZ

0.1U_0402_16V4Z

C264

1 2

2200P_0402_50V7K

1 2

+3VS

10K_0402_5%

10K_0402_5% R229

R229

THERM#_VGA<23>

1 2

0_0402_5%

@

R228

2

SAMTE_BSH-030-01-L-D-A conn@

+3VS

C273

H_THERMDA H_THERMDC

THERM#

GND1 OBSFN_C0 OBSFN_C1

GND3

OBSDATA_C0 OBSDATA_C1

GND5

OBSDATA_C2 OBSDATA_C3

GND7 OBSFN_D0 OBSFN_D1

GND9

OBSDATA_D0 OBSDATA_D1

GND11 OBSDATA_D2 OBSDATA_D3

GND13

ITPCLK/HOOK4

ITPCLK#/HOOK5

VCC_OBS_CD

RESET#/HOOK6

DBR#/HOOK7

GND15

TD0

TRST#

TDI

TMS

GND17

2

1

U16

1

VDD

2

D+

3

DTHERM#4GND

ADM1032ARMZ-2REEL_MSOP8

Address:100_1100

1

R243

XDP_DBRESET#_R

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60

XDP_TDI XDP_TMS XDP_TDO XDP_BPM#5 XDP_HOOK1

XDP_TRST# XDP_TCK

CLK_CPU_XDP CLK_CPU_XDP#

XDP_TDO XDP_TRST# XDP_TDI XDP_TMS XDP_PRE

1K_0402_1%

1 2

200_0402_1%

R1433 0_0402_5%R1433 0_0402_5%

1 2

R243

1K_0402_5%@

1 2

R143 54.9_0402_1%

1 2

R236 54.9_0402_1%

1 2

R1670 54.9_0402_1%

1 2

R241 54.9_0402_1%

1 2

R1430 54.9_0402_1%@ R1430 54.9_0402_1%@

1 2

R237 51_0402_1%

1 2

R239 54.9_0402_1%

1 2

H_RESET#H_RESET#_R

R1431

XDP_DBRESET#XDP_DBRESET#_R

12

R1432

1K_0402_5%@

Place R1431 within 200ps (~1") to CPU

R227

R227 10K_0402_5%

ICH_SM_CLK ICH_SM_DA

10K_0402_5%

1 2

THERM_SCI# <23,26>

SCLK

SDATA

ALERT#

ICH_SM_CLK

8

ICH_SM_DA

7

THERM_SCI#

6 5

ICH_SM_CLK<19,23,26,31>

ICH_SM_DA<19,23,26,31>

0802 (R1A) add for VGA thermal function

PWM Fan Control circuit

0308 change design

+3VS

conn@

5

U24

1

FAN_PWM<37>

THERM#

1 2

0_0402_5%

R230

1 2

+3VS

R232

R232 10K_0402_5%

10K_0402_5%

@

INB

2

INA

P

4

O

G

TC7SH00FU_SSOP5

3

+5VS

conn@

JP8

1

2

G1

3

G2

ACES_85204-03001

+3VS

+VCCP

CLK_CPU_XDP <15> CLK_CPU_XDP# <15>

4 5

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/09/25 2006/09/25

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

Merom(1/3)-AGTL+/XDP

LA3262P_DIS__M64

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1A

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457Tuesday, August 21, 2007

5

4

3

2

1

H_D#[0..15]<7>

D D

H_DSTBN#0<7> H_DSTBP#0<7>

H_DINV#0<7>

H_D#[16..31]<7>

C C

H_DSTBN#1<7> H_DSTBP#1<7>

H_DINV#1<7>

R1264 1K_0402_5%@R1264 1K_0402_5%@

1 2

R1265 1K_0402_5%@R1265 1K_0402_5%@

1 2

C1101 0.1U_0402_16V4Z@C1101 0.1U_0402_16V4Z@

1 2

CPU_BSEL0<15> CPU_BSEL1<15> CPU_BSEL2<15>

T1T1 T2T2

T3T3

H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 H_DSTBN#0 H_DSTBP#0 H_DINV#0

H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31 H_DSTBN#1 H_DSTBP#1 H_DINV#1 H_DINV#3

V_CPU_GTLREF

TEST1 TEST2 TEST3 TEST4 TEST5 TEST6

CPU_BSEL0 H_PWRGOOD CPU_BSEL1 CPU_BSEL2

JP12B

E22

D[0]#

F24

D[1]#

E26

D[2]#

G22

D[3]#

F23

D[4]#

G25

D[5]#

E25

D[6]#

E23

D[7]#

K24

D[8]#

G24

D[9]#

J24

D[10]#

J23

D[11]#

H22

D[12]#

F26

D[13]#

K22

D[14]#

H23

D[15]#

J26

DSTBN[0]#

H26

DSTBP[0]#

H25

DINV[0]#

N22

D[16]#

K25

D[17]#

P26

D[18]#

R23

D[19]#

L23

D[20]#

M24

D[21]#

L22

D[22]#

M23

D[23]#

P25

D[24]#

P23

D[25]#

P22

D[26]#

T24

D[27]#

R24

D[28]#

L25

D[29]#

T25

D[30]#

N25

D[31]#

L26

DSTBN[1]#

M26

DSTBP[1]#

N24

DINV[1]#

AD26

GTLREF

C23

TEST1

D25

TEST2

C24

TEST3

AF26

TEST4

AF1

TEST5

A26

TEST6

B22

BSEL[0]

B23

BSEL[1]

C21

BSEL[2]

Merom Ball-out Rev 1a

conn@

DATA GRP 1

MISC

DATA GRP 0

D[32]# D[33]# D[34]# D[35]# D[36]# D[37]# D[38]# D[39]# D[40]# D[41]# D[42]# D[43]# D[44]# D[45]#

DATA GRP 2DATA GRP 3

D[46]#

D[47]# DSTBN[2]# DSTBP[2]#

DINV[2]#

D[48]#

D[49]#

D[50]#

D[51]#

D[52]#

D[53]#

D[54]#

D[55]#

D[56]#

D[57]#

D[58]#

D[59]#

D[60]#

D[61]#

D[62]#

D[63]# DSTBN[3]# DSTBP[3]#

DINV[3]# COMP[0]

COMP[1] COMP[2] COMP[3]

DPRSTP#

DPSLP# DPWR#

PWRGOOD

SLP#

PSI#

Y22 AB24 V24 V26 V23 T22 U25 U23 Y25 W22 Y23 W24 W25 AA23 AA24 AB25 Y26 AA26 U22

AE24 AD24 AA21 AB22 AB21 AC26 AD20 AE22 AF23 AC25 AE21 AD21 AC22 AD23 AF22 AC23 AE25 AF24 AC20

R26 U26 AA1 Y1

E5 B5 D24 D6 D7 AE6

H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 H_DSTBN#2 H_DSTBP#2 H_DINV#2

H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63 H_DSTBN#3 H_DSTBP#3

COMP0 COMP1 COMP2 COMP3

H_DPRSTP# H_DPSLP# H_DPWR#

H_CPUSLP# H_PSI#

R1436

1K_0402_5%

H_PWRGOOD_R

12

layout note: Route TEST3 & TEST5 traces on ground referenced layer to the TPs

CPU_BSEL CPU_BSEL2 CPU_BSEL1

166

B B

200

01

0

1

CPU_BSEL0

1

0

H_D#[32..47] <7>

H_DSTBN#2 <7> H_DSTBP#2 <7> H_DINV#2 <7> H_D#[48..63] <7>

H_DSTBN#3 <7> H_DSTBP#3 <7> H_DINV#3 <7>

H_DPRSTP# <7,25,49>

H_DPSLP# <25> H_DPWR# <7> H_PWRGOOD <25>

H_CPUSLP# <7> H_PSI# <49>

H_PWRGOOD_R <4>

12

R245

54.9_0402_1%

12

R244

27.4_0402_1%

12

R355

R1220

54.9_0402_1%

27.4_0402_1%

Resistor placed within

0.5" of CPU pin.Trace should be at least 25 mils away from any other toggling signal. COMP[0,2] trace width is 18 mils. COMP[1,3] trace width is 4 mils.

+VCC_CORE +VCC_CORE

JP12C

A7

VCC[001]

A9

VCC[002]

A10

VCC[003]

A12

VCC[004]

A13

VCC[005]

A15

VCC[006]

A17

VCC[007]

A18

VCC[008]

A20

VCC[009]

B7

VCC[010]

B9

VCC[011]

B10

VCC[012]

B12

VCC[013]

B14

VCC[014]

B15

VCC[015]

B17

VCC[016]

B18

VCC[017]

B20

VCC[018]

C9

VCC[019]

C10

VCC[020]

C12

VCC[021]

C13

VCC[022]

C15

VCC[023]

C17

VCC[024]

C18

VCC[025]

D9

VCC[026]

D10

VCC[027]

D12

VCC[028]

D14

VCC[029]

D15

VCC[030]

D17

VCC[031]

D18

VCC[032]

E7

VCC[033]

E9

VCC[034]

E10

VCC[035]

E12

VCC[036]

E13

VCC[037]

E15

VCC[038]

E17

VCC[039]

E18

VCC[040]

E20

VCC[041]

F7

VCC[042]

F9

VCC[043]

F10

VCC[044]

F12

VCC[045]

F14

VCC[046]

F15

VCC[047]

F17

VCC[048]

F18

VCC[049]

F20

VCC[050]

AA7

VCC[051]

AA9

VCC[052]

AA10

VCC[053]

AA12

VCC[054]

AA13

VCC[055]

AA15

VCC[056]

AA17

VCC[057]

AA18

VCC[058]

AA20

VCC[059]

AB9

VCC[060]

AC10

VCC[061]

AB10

VCC[062]

AB12

VCC[063]

AB14

VCC[064]

AB15

VCC[065]

AB17

VCC[066]

AB18

VCC[067]

Merom Ball-out Rev 1a

conn@

VCC[068] VCC[069] VCC[070] VCC[071] VCC[072] VCC[073] VCC[074] VCC[075] VCC[076] VCC[077] VCC[078] VCC[079] VCC[080] VCC[081] VCC[082] VCC[083] VCC[084] VCC[085] VCC[086] VCC[087] VCC[088] VCC[089] VCC[090] VCC[091] VCC[092] VCC[093] VCC[094] VCC[095] VCC[096] VCC[097] VCC[098] VCC[099] VCC[100]

VCCP[01] VCCP[02] VCCP[03] VCCP[04] VCCP[05] VCCP[06] VCCP[07] VCCP[08] VCCP[09] VCCP[10] VCCP[11] VCCP[12] VCCP[13] VCCP[14] VCCP[15] VCCP[16]

VCCA[01] VCCA[02]

VID[0] VID[1] VID[2] VID[3] VID[4] VID[5] VID[6]

VCCSENSE

VSSSENSE

AB20 AB7 AC7 AC9 AC12 AC13 AC15 AC17 AC18 AD7 AD9 AD10 AD12 AD14 AD15 AD17 AD18 AE9 AE10 AE12 AE13 AE15 AE17 AE18 AE20 AF9 AF10 AF12 AF14 AF15 AF17 AF18 AF20

R1434 0_0402_5%

G21 V6

R1435 0_0402_5%

J6 K6 M6 J21 K21 M21 N21 N6 R21 R6 T21 T6 V21 W21

B26 C26

AD6 AF5 AE5 AF4 AE3 AF3 AE2

VCCSENSE

AF7

VSSSENSE

AE7

.

Length match within 25 mils.

+VCCP

12 12

C1100

CPU_VID0 <49> CPU_VID1 <49> CPU_VID2 <49> CPU_VID3 <49> CPU_VID4 <49> CPU_VID5 <49> CPU_VID6 <49>

VCCSENSE <49>

VSSSENSE <49>

1

+

330U_D2E_2.5VM_R15

2

0228 change value

1

C520

C531

2

10U_0805_10V4Z

Near pin B26

+1.5VS

0.01U_0402_16V7K

The trace width/space/other is 20/7/25.

+VCC_CORE

1 2

R1269

R1269 100_0402_1%

100_0402_1%

R1270

R1270 100_0402_1%

100_0402_1%

VCCSENSE

VSSSENSE

V_CPU_GTLREF

+VCCP

12

R1268

R1268 1K_0402_1%

1K_0402_1%

12

R1271

R1271 2K_0402_1%

2K_0402_1%

Close to CPU pin AD26 within 500mils.

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/09/25 2006/09/25

Compal Secret Data

Deciphered Date

2

Close to CPU pin within 500mils.

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

Merom(2/3)-AGTL+/PWR

LA3262P_DIS__M64

1

of

557Tuesday, August 21, 2007

1A

5

Place these capacitors on L8

D D

C C

B B

JP12D

A4

VSS[001]

A8

VSS[002]

A11

VSS[003]

A14

VSS[004]

A16

VSS[005]

A19

VSS[006]

A23

VSS[007]

AF2

VSS[008]

B6

VSS[009]

B8

VSS[010]

B11

VSS[011]

B13

VSS[012]

B16

VSS[013]

B19

VSS[014]

B21

VSS[015]

B24

VSS[016]

C5

VSS[017]

C8

VSS[018]

C11

VSS[019]

C14

VSS[020]

C16

VSS[021]

C19

VSS[022]

C2

VSS[023]

C22

VSS[024]

C25

VSS[025]

D1

VSS[026]

D4

VSS[027]

D8

VSS[028]

D11

VSS[029]

D13

VSS[030]

D16

VSS[031]

D19

VSS[032]

D23

VSS[033]

D26

VSS[034]

E3

VSS[035]

E6

VSS[036]

E8

VSS[037]

E11

VSS[038]

E14

VSS[039]

E16

VSS[040]

E19

VSS[041]

E21

VSS[042]

E24

VSS[043]

F5

VSS[044]

F8

VSS[045]

F11

VSS[046]

F13

VSS[047]

F16

VSS[048]

F19

VSS[049]

F2

VSS[050]

F22

VSS[051]

F25

VSS[052]

G4

VSS[053]

G1

VSS[054]

G23

VSS[055]

G26

VSS[056]

H3

VSS[057]

H6

VSS[058]

H21

VSS[059]

H24

VSS[060]

J2

VSS[061]

J5

VSS[062]

J22

VSS[063]

J25

VSS[064]

K1

VSS[065]

K4

VSS[066]

K23

VSS[067]

K26

VSS[068]

L3

VSS[069]

L6

VSS[070]

L21

VSS[071]

L24

VSS[072]

M2

VSS[073]

M5

VSS[074]

M22

VSS[075]

M25

VSS[076]

N1

VSS[077]

N4

VSS[078]

N23

VSS[079]

N26

VSS[080] VSS[081]P3VSS[162]

Merom Ball-out Rev 1a

conn@

VSS[082] VSS[083] VSS[084] VSS[085] VSS[086] VSS[087] VSS[088] VSS[089] VSS[090] VSS[091] VSS[092] VSS[093] VSS[094] VSS[095] VSS[096] VSS[097] VSS[098] VSS[099] VSS[100] VSS[101] VSS[102] VSS[103] VSS[104] VSS[105] VSS[106] VSS[107] VSS[108] VSS[109] VSS[110] VSS[111] VSS[112] VSS[113] VSS[114] VSS[115] VSS[116] VSS[117] VSS[118] VSS[119] VSS[120] VSS[121] VSS[122] VSS[123] VSS[124] VSS[125] VSS[126] VSS[127] VSS[128] VSS[129] VSS[130] VSS[131] VSS[132] VSS[133] VSS[134] VSS[135] VSS[136] VSS[137] VSS[138] VSS[139] VSS[140] VSS[141] VSS[142] VSS[143] VSS[144] VSS[145] VSS[146] VSS[147] VSS[148] VSS[149] VSS[150] VSS[151] VSS[152] VSS[153] VSS[154] VSS[155] VSS[156] VSS[157] VSS[158] VSS[159] VSS[160] VSS[161]

VSS[163]

P6 P21 P24 R2 R5 R22 R25 T1 T4 T23 T26 U3 U6 U21 U24 V2 V5 V22 V25 W1 W4 W23 W26 Y3 Y6 Y21 Y24 AA2 AA5 AA8 AA11 AA14 AA16 AA19 AA22 AA25 AB1 AB4 AB8 AB11 AB13 AB16 AB19 AB23 AB26 AC3 AC6 AC8 AC11 AC14 AC16 AC19 AC21 AC24 AD2 AD5 AD8 AD11 AD13 AD16 AD19 AD22 AD25 AE1 AE4 AE8 AE11 AE14 AE16 AE19 AE23 AE26 A2 AF6 AF8 AF11 AF13 AF16 AF19 AF21 A25 AF25

.

(North side,Secondary Layer)

Place these capacitors on L8 (North side,Secondary Layer)

Place these capacitors on L8 (Sorth side,Secondary Layer)

330U_D2E_2.5VM_R7

+VCCP

1

C940

0.1U_0402_10V6K

2

4

+VCC_CORE

1

+

C931

2

+VCC_CORE

1

C899

C899 10U_0805_6.3V6M

10U_0805_6.3V6M

2

+VCC_CORE

1

C907

C907 10U_0805_6.3V6M

10U_0805_6.3V6M

2

+VCC_CORE

1

C915

C915 10U_0805_6.3V6M

10U_0805_6.3V6M

2

+VCC_CORE

1

C923

C923 10U_0805_6.3V6M

10U_0805_6.3V6M

2

Near CPU CORE regulator

330U_D2E_2.5VM_R7

1

+

C933

C932

2

330U_D2E_2.5VM_R7

1

C941

0.1U_0402_10V6K

2

1

C900

C900 10U_0805_6.3V6M

10U_0805_6.3V6M

2

1

C908

C908 10U_0805_6.3V6M

10U_0805_6.3V6M

2

1

C916

C916 10U_0805_6.3V6M

10U_0805_6.3V6M

2

1

C924

C924 10U_0805_6.3V6M

10U_0805_6.3V6M

2

1

+

C935

2

330U_D2E_2.5VM_R7

1

C942

0.1U_0402_10V6K

2

1

+

2

1

C901

C901 10U_0805_6.3V6M

10U_0805_6.3V6M

2

1

C909

C909 10U_0805_6.3V6M

10U_0805_6.3V6M

2

1

C917

C917 10U_0805_6.3V6M

10U_0805_6.3V6M

2

1

C925

C925 10U_0805_6.3V6M

10U_0805_6.3V6M

2

330U_D2E_2.5VM_R7

1

@

C936

+

C937

2

330U_D2E_2.5VM_R7

1

C943

0.1U_0402_10V6K

2

@

3

1

C902

C902 10U_0805_6.3V6M

10U_0805_6.3V6M

2

1

C910

C910 10U_0805_6.3V6M

10U_0805_6.3V6M

2

1

C918

C918 10U_0805_6.3V6M

10U_0805_6.3V6M

2

1

C926

C926 10U_0805_6.3V6M

10U_0805_6.3V6M

2

ESR <= 1.5m ohm Capacitor > 1980uF

1

+

2

1

C944

0.1U_0402_10V6K

2

1

C903

C903 10U_0805_6.3V6M

10U_0805_6.3V6M

2

1

C911

C911 10U_0805_6.3V6M

10U_0805_6.3V6M

2

1

C919

C919 10U_0805_6.3V6M

10U_0805_6.3V6M

2

1

C927

C927 10U_0805_6.3V6M

10U_0805_6.3V6M

2

Place these inside socket cavity on L8 (North side Secondary)

1

C945

0.1U_0402_10V6K

2

1

C904

C904 10U_0805_6.3V6M

10U_0805_6.3V6M

2

1

C912

C912 10U_0805_6.3V6M

10U_0805_6.3V6M

2

1

C920

C920 10U_0805_6.3V6M

10U_0805_6.3V6M

2

1

C928

C928 10U_0805_6.3V6M

10U_0805_6.3V6M

2

1

C905

C905 10U_0805_6.3V6M

10U_0805_6.3V6M

2

1

C913

C913 10U_0805_6.3V6M

10U_0805_6.3V6M

2

1

C921

C921 10U_0805_6.3V6M

10U_0805_6.3V6M

2

1

C929

C929 10U_0805_6.3V6M

10U_0805_6.3V6M

2

1

C906

C906 10U_0805_6.3V6M

10U_0805_6.3V6M

2

1

C914

C914 10U_0805_6.3V6M

10U_0805_6.3V6M

2

1

C922

C922 10U_0805_6.3V6M

10U_0805_6.3V6M

2

1

C930

C930 10U_0805_6.3V6M

10U_0805_6.3V6M

2

1

Mid Frequence Decoupling

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/09/25 2006/09/25

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

Merom(3/3)-GND&Bypass

LA3262P_DIS__M64

1

1A

of

657Tuesday, August 21, 2007

5

U15A

M10

W10

AD12

AC14 AD11 AC11

AG3

AJ14

AE11 AH12

AH13

E2

G2 G7 M6 H7 H3 G4

F3 N8 H2

N12

N9 H5

P13

K9 M2

Y8

V4 M3

J1 N5 N3 W6 W9 N2

Y7

Y9

P4 W3 N1

AE3 AD9 AC9 AC7

AB2 AD7 AB1

Y3

AC6 AE2 AC5

AJ9 AH8

AE9

AJ5 AH5 AJ6 AE7 AJ7 AJ2 AE5 AJ3 AH2

B3 C2

W1 W2

B6

E5

B9

A9

U15A

H_D#_0 H_D#_1 H_D#_2 H_D#_3 H_D#_4 H_D#_5 H_D#_6 H_D#_7 H_D#_8 H_D#_9 H_D#_10 H_D#_11 H_D#_12 H_D#_13 H_D#_14 H_D#_15 H_D#_16 H_D#_17 H_D#_18 H_D#_19 H_D#_20 H_D#_21 H_D#_22 H_D#_23 H_D#_24 H_D#_25 H_D#_26 H_D#_27 H_D#_28 H_D#_29 H_D#_30 H_D#_31 H_D#_32 H_D#_33 H_D#_34 H_D#_35 H_D#_36 H_D#_37 H_D#_38 H_D#_39 H_D#_40 H_D#_41 H_D#_42 H_D#_43 H_D#_44 H_D#_45 H_D#_46 H_D#_47 H_D#_48 H_D#_49 H_D#_50 H_D#_51 H_D#_52 H_D#_53 H_D#_54 H_D#_55 H_D#_56 H_D#_57 H_D#_58 H_D#_59 H_D#_60 H_D#_61 H_D#_62 H_D#_63

H_SWING H_RCOMP

H_SCOMP H_SCOMP#

H_CPURST# H_CPUSLP#

H_AVREF H_DVREF

CRESTLINE_1p0

HOST

H_ADSTB#_0 H_ADSTB#_1

H_DEFER#

HPLL_CLK

HPLL_CLK#

H_DPWR#

H_DINV#_0 H_DINV#_1 H_DINV#_2 H_DINV#_3

H_DSTBN#_0 H_DSTBN#_1 H_DSTBN#_2 H_DSTBN#_3

H_DSTBP#_0 H_DSTBP#_1 H_DSTBP#_2 H_DSTBP#_3

H_REQ#_0 H_REQ#_1

H_REQ#_2 H_REQ#_3

H_REQ#_4

H_D#[0..63]<5>

D D

C C

+VCCP

12

R1196

R1197

54.9_0402_1%

H_RESET#<4>

H_CPUSLP#<5>

B B

H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31 H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57

H_D#59 H_D#60 H_D#61 H_D#62 H_D#63

H_SWNG H_RCOMP

H_SCOMP H_SCOMP#

H_RESET# H_CPUSLP#

H_VREF

layout note:

Route H_SCOMP and H_SCOMP# with trace width, spacing and impedance (55 ohm) same as FSB data traces

Layout Note: H_RCOMP / H_VREF / H_SWNG

trace width and spacing is 10/20

+VCCP

R1206

R1210

12

221_0603_1%

12

100_0402_1%

H_SWNGH_VREF

1

C896

2

0.1U_0402_16V4Z

+VCCP

12

1K_0402_1%

R1208

0.1U_0402_16V4Z

12

A A

R1212

C60

2K_0402_1%

1

2

12

R1199

24.9_0402_1%

H_RCOMP

Near B3 pinwithin 100 mils from NB

5

H_A#_3 H_A#_4 H_A#_5 H_A#_6 H_A#_7 H_A#_8

H_A#_9 H_A#_10 H_A#_11 H_A#_12 H_A#_13 H_A#_14 H_A#_15 H_A#_16 H_A#_17 H_A#_18 H_A#_19 H_A#_20 H_A#_21 H_A#_22 H_A#_23 H_A#_24 H_A#_25 H_A#_26 H_A#_27 H_A#_28 H_A#_29 H_A#_30 H_A#_31 H_A#_32 H_A#_33 H_A#_34 H_A#_35

H_ADS#

H_BNR#

H_BPRI#

H_BREQ# H_DBSY#

H_DRDY#

H_HIT# H_HITM#

H_LOCK# H_TRDY#

H_RS#_0 H_RS#_1 H_RS#_2

J13 B11 C11 M11 C15 F16 L13 G17 C14 K16 B13 L16 J17 B14 K19 P15 R17 B16 H20 L19 D17 M17 N16 J19 B18 E19 B17 B15 E17 C18 A19 B19 N19

G12 H17 G20 C8 E8 F12 D6 C10 AM5 AM7 H8 K7 E4 C6 G10 B7

K5 L2 AD13 AE13

M7 K3 AD2 AH11

L7 K2 AC2 AJ10

M14 E13 A11 H13 B12

E12 D7 D8

4

V_DDR_MCH_REF<13,14,48>

4

H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16 H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 H_A#32 H_A#33 H_A#34 H_A#35

H_ADS# H_ADSTB#0 H_ADSTB#1 H_BNR# H_BPRI# H_BR0# H_DEFER# H_DBSY# CLK_MCH_BCLK CLK_MCH_BCLK# H_DPWR# H_DRDY# H_HIT# H_HITM# H_LOCK# H_TRDY#

H_DINV#0 H_DINV#1 H_DINV#2 H_DINV#3

H_DSTBN#0H_D#58 H_DSTBN#1 H_DSTBN#2 H_DSTBN#3

H_DSTBP#0 H_DSTBP#1 H_DSTBP#2 H_DSTBP#3

H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4

H_RS#0 H_RS#1 H_RS#2

VGATE<26,37>

Layout Note: V_DDR_MCH_REF trace width and spacing is 20/20.

H_A#[3..35] <4>

H_ADS# <4> H_ADSTB#0 <4> H_ADSTB#1 <4> H_BNR# <4> H_BPRI# <4> H_BR0# <4> H_DEFER# <4> H_DBSY# <4> CLK_MCH_BCLK <15> CLK_MCH_BCLK# <15> H_DPWR# <5> H_DRDY# <4> H_HIT# <4> H_HITM# <4> H_LOCK# <4> H_TRDY# <4>

H_DINV#0 <5> H_DINV#1 <5> H_DINV#2 <5> H_DINV#3 <5>

H_DSTBN#0 <5> H_DSTBN#1 <5> H_DSTBN#2 <5> H_DSTBN#3 <5>

H_DSTBP#0 <5> H_DSTBP#1 <5> H_DSTBP#2 <5> H_DSTBP#3 <5>

H_REQ#0 <4> H_REQ#1 <4> H_REQ#2 <4> H_REQ#3 <4> H_REQ#4 <4>

H_RS#0 <4> H_RS#1 <4> H_RS#2 <4>

12

R1484 0_0402_5%R1484 0_0402_5%

V_DDR_MCH_REF

1

C895

2

0.1U_0402_16V4Z

3

2

1

C1103

1

2

C1105

R1439

10K_0402_5%

R1440

10K_0402_5%

R1441

<>

10K_0402_5%

CFG5<9> CFG7<9>

CFG8<9> CFG9<9>

CFG12<9> CFG13<9>

T109T109 T110T110

CFG16<9>

T111T111

T112T112

CFG19<9> CFG20<9>

H_DPRSTP#<5,25,49> PM_EXTTS#0<13> PM_EXTTS#1<14>

1 2

DPRSLPVR<26,49>

+1.8V

2

1

0.01U_0402_25V7K

1

2

0.01U_0402_25V7K

R1439

12

T104T104 T105T105

T106T106

T107T107 T108T108

0_0402_5%

12

R1437

R1437 1K_0402_1%

1K_0402_1%

12

R31

3.01K_0402_1%

12

R1438

R1438 1K_0402_1%

1K_0402_1%

DDR_A_MA14<13> DDR_B_MA14<14>

+3VS

R2

MCH_CLKSEL0 MCH_CLKSEL1 MCH_CLKSEL2 CFG3 CFG4 CFG5 CFG6 CFG7 CFG8 CFG9 CFG10 CFG11 CFG12 CFG13 CFG14 CFG15 CFG16 CFG17 CFG18 CFG19 CFG20

PM_BMBUSY# H_DPRSTP# PM_EXTTS#0 PM_EXTTS#1 PM_POK_R PLT_RST#_R THERM_TRIP# DPRSLPVR

2.2U_0603_6.3V4Z

C1102

SMRCOMP_VOH

SMRCOMP_VOL

PM_EXTTS#0

PM_EXTTS#1

CLKREQ#_B DMI_TXN0

C1102

C1104

2.2U_0603_6.3V4Z

MCH_CLKSEL0<15> MCH_CLKSEL1<15> MCH_CLKSEL2<15>

PM_BMBUSY#<26>

0904 add

H_THERMTRIP#<4,23,25>

PM_POK_R

11/20 Add R2 for Intel ES2 chipset

2007,0125 change

+1.8V

12

R1201

1K_0402_1%@

12

R1204

1K_0402_1%

@

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

THERM_TRIP#

1

2

C1626

0.1U_0402_16V4Z

@

R1446

100_0402_5%

2006/09/25 2006/09/25

U15B

P36

RSVD1

P37

RSVD2

R35

RSVD3

N35

RSVD4

AR12

RSVD5

AR13

RSVD6

AM12

RSVD7

AN13

RSVD8

J12

RSVD9

AR37

RSVD10

AM36

RSVD11

AL36

RSVD12

AM37

RSVD13

D20

RSVD14

H10

RSVD20

B51

RSVD21

BJ20

RSVD22

BK22

RSVD23

BF19

RSVD24

BH20

RSVD25

BK18

RSVD26

BJ18

RSVD27

BF23

RSVD28

BG23

RSVD29

BC23

RSVD30

BD24

RSVD31

BJ29

RSVD32

BE24

RSVD33

BH39

RSVD34

AW20

RSVD35

BK20

RSVD36

C48

RSVD37

D47

RSVD38

B44

RSVD39

C44

RSVD40

A35

RSVD41

B37

RSVD42

B36

RSVD43

B34

RSVD44

C34

RSVD45

P27

CFG_0

N27

CFG_1

N24

CFG_2

C21

CFG_3

C23

CFG_4

F23

CFG_5

N23

CFG_6

G23

CFG_7

J20

CFG_8

C20

CFG_9

R24

CFG_10

L23

CFG_11

J23

CFG_12

E23

CFG_13

E20

CFG_14

K23

CFG_15

M20

CFG_16

M24

CFG_17

L32

CFG_18

N33

CFG_19

L35

CFG_20

G41

PM_BM_BUSY#

L39

PM_DPRSTP#

L36

PM_EXT_TS#_0

J36

PM_EXT_TS#_1

AW49

PWROK

AV20

RSTIN#

N20

THERMTRIP#

G36

DPRSLPVR

BJ51

NC_1

BK51

NC_2

BK50

NC_3

BL50

NC_4

BL49

NC_5

BL3

NC_6

BL2

NC_7

BK1

NC_8

BJ1

NC_9

E1

NC_10

A5

NC_11

C51

NC_12

B50

NC_13

A50

NC_14

A49

NC_15

BK2

NC_16

CRESTLINE_1p0

R1446

PLT_RST#PLT_RST#_R

12

Compal Secret Data

Deciphered Date

2

DDR MUXINGCLK

CFGRSVD

DMI

PM

GRAPHICS VID

ME

NC

MISC

PLT_RST# <24,28,36>

2

SM_CK_0 SM_CK_1 SM_CK_3 SM_CK_4

SM_CK#_0 SM_CK#_1 SM_CK#_3 SM_CK#_4

SM_CKE_0 SM_CKE_1 SM_CKE_3 SM_CKE_4

SM_CS#_0 SM_CS#_1 SM_CS#_2 SM_CS#_3

SM_ODT_0 SM_ODT_1 SM_ODT_2 SM_ODT_3

SM_RCOMP

SM_RCOMP#

SM_RCOMP_VOH

SM_RCOMP_VOL

SM_VREF_0 SM_VREF_1

DPLL_REF_CLK

DPLL_REF_CLK#

DPLL_REF_SSCLK

DPLL_REF_SSCLK#

PEG_CLK

PEG_CLK#

DMI_RXN_0 DMI_RXN_1 DMI_RXN_2 DMI_RXN_3

DMI_RXP_0 DMI_RXP_1 DMI_RXP_2 DMI_RXP_3

DMI_TXN_0 DMI_TXN_1 DMI_TXN_2 DMI_TXN_3

DMI_TXP_0 DMI_TXP_1 DMI_TXP_2 DMI_TXP_3

GFX_VID_0 GFX_VID_1 GFX_VID_2 GFX_VID_3

GFX_VR_EN

CL_DATA

CL_PWROK

CL_RST# CL_VREF

SDVO_CTRL_CLK

SDVO_CTRL_DATA

CLK_REQ#

ICH_SYNC#

CL_CLK

TEST_1 TEST_2

1

For Crestline: 20ohm

M_CLK_DDR0

AV29

M_CLK_DDR1

BB23

M_CLK_DDR2

BA25

M_CLK_DDR3

AV23

M_CLK_DDR#0

AW30

M_CLK_DDR#1

BA23

M_CLK_DDR#2

AW25

M_CLK_DDR#3

AW23

DDR_CKE0_DIMMA

BE29

DDR_CKE1_DIMMA

AY32

DDR_CKE2_DIMMB

BD39

DDR_CKE3_DIMMB

BG37

DDR_CS0_DIMMA#

BG20

DDR_CS1_DIMMA#

BK16

DDR_CS2_DIMMB#

BG16

DDR_CS3_DIMMB#

BE13

M_ODT0

BH18

M_ODT1

BJ15

M_ODT2

BJ14

M_ODT3

BE16

SMRCOMP

BL15

SMRCOMP#

BK14

SMRCOMP_VOH

BK31

SMRCOMP_VOL

BL31 AR49

V_DDR_MCH_REF

AW4

B42 C42 H48 H47

CLK_MCH_3GPLL

K44

CLK_MCH_3GPLL#

K45

AN47

DMI_TXN1

AJ38

DMI_TXN2

AN42

DMI_TXN3

AN46

DMI_TXP0

AM47

DMI_TXP1

AJ39

DMI_TXP2

AN41

DMI_TXP3

AN45

DMI_RXN0

AJ46

DMI_RXN1

AJ41

DMI_RXN2

AM40

DMI_RXN3

AM44

DMI_RXP0

AJ47

DMI_RXP1

AJ42

DMI_RXP2

AM39

DMI_RXP3

AM43

E35 A39 C38 B39 E36

CL_CLK0

AM49

CL_DATA0

AK50

M_PWROK

AT43

CL_RST#

AN49

CL_VREF CL_VREF

AM50

H35 K36

CLKREQ#_B

G39

MCH_ICH_SYNC#

G40

A37 R32

12

R1444

20K_0402_5%

Title

CRESTLINE(1/6)-AGTL+/DMI/DDR2

Size Document Number Rev

Custom

LA3262P_DIS__M64

Date: Sheet

For Calero: 80.6ohm

M_CLK_DDR0 <13> M_CLK_DDR1 <13> M_CLK_DDR2 <14> M_CLK_DDR3 <14>

M_CLK_DDR#0 <13> M_CLK_DDR#1 <13> M_CLK_DDR#2 <14> M_CLK_DDR#3 <14>

DDR_CKE0_DIMMA <13> DDR_CKE1_DIMMA <13> DDR_CKE2_DIMMB <14> DDR_CKE3_DIMMB <14>

DDR_CS0_DIMMA# <13> DDR_CS1_DIMMA# <13> DDR_CS2_DIMMB# <14> DDR_CS3_DIMMB# <14>

M_ODT0 <13> M_ODT1 <13> M_ODT2 <14> M_ODT3 <14>

CLK_MCH_3GPLL <15> CLK_MCH_3GPLL# <15>

DMI_TXN0 <26> DMI_TXN1 <26> DMI_TXN2 <26> DMI_TXN3 <26>

DMI_TXP0 <26> DMI_TXP1 <26> DMI_TXP2 <26> DMI_TXP3 <26>

DMI_RXN0 <26> DMI_RXN1 <26> DMI_RXN2 <26> DMI_RXN3 <26>

DMI_RXP0 <26> DMI_RXP1 <26> DMI_RXP2 <26> DMI_RXP3 <26>

CL_CLK0 <26> CL_DATA0 <26> M_PWROK <26,41> CL_RST# <26>

0.1U_0402_16V4Z

CLKREQ#_B <15> MCH_ICH_SYNC# <26>

12

R1445

R1445 0_0402_5%

0_0402_5%

Compal Electronics, Inc.

20_0402_1%

R1194

R1194 R1195 20_0402_1%

R1195 20_0402_1%

C1106

1

+1.25VM_AXD

1

2

757Tuesday, August 21, 2007

12 12

12

R1442

R1442 1K_0402_1%

1K_0402_1%

12

R1443

R1443 392_0402_1%

392_0402_1%

+1.8V

1A

of

5

D D

DDR_A_D[0..63]<13>

C C

B B

DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8

DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15 DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63

AR43

AW44

BA45 AY46 AR41 AR45 AT42

AW47

BB45 BF48 BG47

BJ45 BB47 BG50 BH49 BE45

AW43

BE44 BG42 BE40 BF44 BH45 BG40 BF40 AR40

AW40

AT39

AW36 AW41

AY41 AV38 AT38 AV13 AT13

AW11

AV11 AU15 AT11 BA13 BA11 BE10 BD10

BG10

AW9

AM8

AN10

AN9 AM9

AN11

BD8 AY9

BD7 BB9 BB5 AY7 AT5 AT7 AY6 BB7 AR5 AR8 AR9 AN3

AT9

U15D

SA_DQ_0 SA_DQ_1 SA_DQ_2 SA_DQ_3 SA_DQ_4 SA_DQ_5 SA_DQ_6 SA_DQ_7 SA_DQ_8 SA_DQ_9 SA_DQ_10 SA_DQ_11 SA_DQ_12 SA_DQ_13 SA_DQ_14 SA_DQ_15 SA_DQ_16 SA_DQ_17 SA_DQ_18 SA_DQ_19 SA_DQ_20 SA_DQ_21 SA_DQ_22 SA_DQ_23 SA_DQ_24 SA_DQ_25 SA_DQ_26 SA_DQ_27 SA_DQ_28 SA_DQ_29 SA_DQ_30 SA_DQ_31 SA_DQ_32 SA_DQ_33 SA_DQ_34 SA_DQ_35 SA_DQ_36 SA_DQ_37 SA_DQ_38 SA_DQ_39 SA_DQ_40 SA_DQ_41 SA_DQ_42 SA_DQ_43 SA_DQ_44 SA_DQ_45 SA_DQ_46 SA_DQ_47 SA_DQ_48 SA_DQ_49 SA_DQ_50 SA_DQ_51 SA_DQ_52 SA_DQ_53 SA_DQ_54 SA_DQ_55 SA_DQ_56 SA_DQ_57 SA_DQ_58 SA_DQ_59 SA_DQ_60 SA_DQ_61 SA_DQ_62 SA_DQ_63

CRESTLINE_1p0

DDR SYSTEM MEMORY A

SA_BS_0 SA_BS_1 SA_BS_2

SA_CAS#

SA_DM_0 SA_DM_1 SA_DM_2 SA_DM_3 SA_DM_4 SA_DM_5 SA_DM_6 SA_DM_7

SA_DQS_0 SA_DQS_1 SA_DQS_2 SA_DQS_3 SA_DQS_4 SA_DQS_5 SA_DQS_6

SA_DQS_7 SA_DQS#_0 SA_DQS#_1 SA_DQS#_2 SA_DQS#_3 SA_DQS#_4 SA_DQS#_5 SA_DQS#_6 SA_DQS#_7

SA_MA_0 SA_MA_1 SA_MA_2 SA_MA_3 SA_MA_4 SA_MA_5 SA_MA_6 SA_MA_7 SA_MA_8

SA_MA_9 SA_MA_10 SA_MA_11 SA_MA_12 SA_MA_13

SA_RAS#

SA_RCVEN#

SA_WE#

4

DDR_A_BS0

BB19 BK19 BF29

BL17 AT45

BD44 BD42 AW38 AW13 BG8 AY5 AN6

AT46 BE48 BB43 BC37 BB16 BH6 BB2 AP3 AT47 BD47 BC41 BA37 BA16 BH7 BC1 AP2

BJ19 BD20 BK27 BH28 BL24 BK28 BJ27 BJ25 BL28 BA28 BC19 BE28 BG30 BJ16

BE18 AY20

BA19

DDR_A_BS1 DDR_A_BS2

DDR_A_CAS# DDR_A_DM0

DDR_A_DM1 DDR_A_DM2 DDR_A_DM3 DDR_A_DM4 DDR_A_DM5 DDR_A_DM6 DDR_A_DM7

DDR_A_DQS0 DDR_A_DQS1 DDR_A_DQS2

DDR_A_DQS4 DDR_A_DQS5 DDR_A_DQS6 DDR_A_DQS7 DDR_A_DQS#0 DDR_A_DQS#1 DDR_A_DQS#2 DDR_A_DQS#3 DDR_A_DQS#4 DDR_A_DQS#5 DDR_A_DQS#6 DDR_A_DQS#7

DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13

DDR_A_RAS# SA_RCVEN#

DDR_A_WE#

DDR_A_BS0 <13> DDR_A_BS1 <13> DDR_A_BS2 <13>

DDR_A_CAS# <13> DDR_B_CAS# <14> DDR_A_DM[0..7] <13>

DDR_A_DQS[0..7] <13>

DDR_A_DQS#[0..7] <13>

DDR_A_MA[0..13] <13>

DDR_A_RAS# <13>

T5T5

DDR_A_WE# <13>

3

DDR_B_D[0..63]<14>

DDR_B_D0 DDR_B_D1 DDR_B_D2 DDR_B_D3 DDR_B_D4 DDR_B_D5 DDR_B_D6 DDR_B_D7 DDR_B_D8

DDR_B_D9 DDR_B_D10 DDR_B_D11 DDR_B_D12 DDR_B_D13 DDR_B_D14 DDR_B_D15 DDR_B_D16 DDR_B_D17 DDR_B_D18DDR_A_DQS3 DDR_B_D19 DDR_B_D20 DDR_B_D21 DDR_B_D22 DDR_B_D23 DDR_B_D24 DDR_B_D25 DDR_B_D26 DDR_B_D27 DDR_B_D28 DDR_B_D29 DDR_B_D30 DDR_B_D31 DDR_B_D32 DDR_B_D33 DDR_B_D34 DDR_B_D35 DDR_B_D36 DDR_B_D37 DDR_B_D38 DDR_B_D39 DDR_B_D40 DDR_B_D41

DDR_B_D43 DDR_B_D44 DDR_B_D45 DDR_B_D46 DDR_B_D47 DDR_B_D48 DDR_B_D49 DDR_B_D50 DDR_B_D51 DDR_B_D52 DDR_B_D53 DDR_B_D54 DDR_B_D55 DDR_B_D56 DDR_B_D57 DDR_B_D58 DDR_B_D59 DDR_B_D60 DDR_B_D61 DDR_B_D62 DDR_B_D63

AP49

AR51 AW50 AW51

AN51

AN50

AV50

AV49

BA50

BB50

BA49

BE50

BA51

AY49

BF50

BF49

BJ50 BJ44 BJ43

BL43 BK47 BK49 BK43 BK42

BJ41

BL41

BJ37

BJ36 BK41

BJ40

BL35 BK37 BK13 BE11 BK11 BC11 BC13 BE12 BC12 BG12

BJ10

BK10

BK5 BK9

BF4 BH5 BG1 BC2 BK3 BE4 BD3

BA3 BB3 AR1 AT3 AY2 AY3 AU2 AT2

BL9 BL5

BJ8 BJ6

BJ2

2

U15E

SB_DQ_0 SB_DQ_1 SB_DQ_2 SB_DQ_3 SB_DQ_4 SB_DQ_5 SB_DQ_6 SB_DQ_7 SB_DQ_8 SB_DQ_9 SB_DQ_10 SB_DQ_11 SB_DQ_12 SB_DQ_13 SB_DQ_14 SB_DQ_15 SB_DQ_16 SB_DQ_17 SB_DQ_18 SB_DQ_19 SB_DQ_20 SB_DQ_21 SB_DQ_22 SB_DQ_23 SB_DQ_24 SB_DQ_25 SB_DQ_26 SB_DQ_27 SB_DQ_28 SB_DQ_29 SB_DQ_30 SB_DQ_31 SB_DQ_32 SB_DQ_33 SB_DQ_34 SB_DQ_35 SB_DQ_36 SB_DQ_37 SB_DQ_38 SB_DQ_39 SB_DQ_40 SB_DQ_41 SB_DQ_42 SB_DQ_43 SB_DQ_44 SB_DQ_45 SB_DQ_46 SB_DQ_47 SB_DQ_48 SB_DQ_49 SB_DQ_50 SB_DQ_51 SB_DQ_52 SB_DQ_53 SB_DQ_54 SB_DQ_55 SB_DQ_56 SB_DQ_57 SB_DQ_58 SB_DQ_59 SB_DQ_60 SB_DQ_61 SB_DQ_62 SB_DQ_63

CRESTLINE_1p0

1

DDR_B_BS0

AY17

SB_BS_0 SB_BS_1 SB_BS_2

SB_CAS#

SB_DM_0 SB_DM_1 SB_DM_2 SB_DM_3 SB_DM_4 SB_DM_5 SB_DM_6 SB_DM_7

SB_DQS_0 SB_DQS_1 SB_DQS_2 SB_DQS_3 SB_DQS_4 SB_DQS_5 SB_DQS_6

SB_DQS_7 SB_DQS#_0 SB_DQS#_1 SB_DQS#_2 SB_DQS#_3 SB_DQS#_4 SB_DQS#_5 SB_DQS#_6 SB_DQS#_7

SB_MA_0 SB_MA_1 SB_MA_2 SB_MA_3 SB_MA_4 SB_MA_5 SB_MA_6 SB_MA_7 SB_MA_8

SB_MA_9 SB_MA_10 SB_MA_11 SB_MA_12 SB_MA_13

SB_RAS#

SB_RCVEN#

SB_WE#

DDR SYSTEM MEMORY B

BG18 BG36

BE17 AR50

BD49 BK45 BL39 BH12 BJ7 BF3 AW2

AT50 BD50 BK46 BK39 BJ12 BL7 BE2 AV2 AU50 BC50 BL45 BK38 BK12 BK7 BF2 AV3

BC18 BG28 BG25 AW17 BF25 BE25 BA29 BC28 AY28 BD37 BG17 BE37 BA39 BG13

AV16 AY18

BC17

DDR_B_BS1 DDR_B_BS2

DDR_B_CAS#

DDR_B_DM0 DDR_B_DM1 DDR_B_DM2 DDR_B_DM3 DDR_B_DM4 DDR_B_DM5 DDR_B_DM6 DDR_B_DM7

DDR_B_DQS0 DDR_B_DQS1 DDR_B_DQS2 DDR_B_DQS3 DDR_B_DQS4 DDR_B_DQS5 DDR_B_DQS6

DDR_B_DQS7 DDR_B_DQS#0 DDR_B_DQS#1 DDR_B_DQS#2 DDR_B_DQS#3 DDR_B_DQS#4 DDR_B_DQS#5 DDR_B_DQS#6 DDR_B_DQS#7

DDR_B_MA0 DDR_B_MA1 DDR_B_MA2 DDR_B_MA3 DDR_B_MA4 DDR_B_MA5 DDR_B_MA6 DDR_B_MA7 DDR_B_MA8

DDR_B_MA9 DDR_B_MA10DDR_B_D42 DDR_B_MA11 DDR_B_MA12 DDR_B_MA13

DDR_B_RAS#

SB_RCVEN#

DDR_B_WE#

DDR_B_BS0 <14> DDR_B_BS1 <14> DDR_B_BS2 <14>

DDR_B_DM[0..7] <14>

DDR_B_DQS[0..7] <14>

DDR_B_DQS#[0..7] <14>

DDR_B_MA[0..13] <14>

DDR_B_RAS# <14>

T4T4

DDR_B_WE# <14>

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/09/25 2006/09/25

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

CRESTLINE((2/6)-DDR2 A/B CH

LA3262P_DIS__M64

1

of

857Tuesday, August 21, 2007

1A

5

4

3

2

1

U15C

J40

L_BKLT_CTRL

H39

L_BKLT_EN

E39

L_CTRL_CLK

E40

L_CTRL_DATA

C37

L_DDC_CLK

D35

L_DDC_DATA

K40

L_VDD_EN

L41

LVDS_IBG

L43

D D

C C

B B

N41 N40 D46 C45 D44

E42

G51

E51 F49

G50

E50 F48

G44

B47 B45

E44 A47 A45

E27

G27

K27 F27

J27

L27

M35

P33

H32 G32

K29

J29 F29 E29

K33

G35

F33

C32

E33

CRESTLINE_1p0

LVDS_VBG LVDS_VREFH LVDS_VREFL LVDSA_CLK# LVDSA_CLK LVDSB_CLK# LVDSB_CLK

LVDSA_DATA#_0 LVDSA_DATA#_1 LVDSA_DATA#_2

LVDSA_DATA_0 LVDSA_DATA_1 LVDSA_DATA_2

LVDSB_DATA#_0 LVDSB_DATA#_1 LVDSB_DATA#_2

LVDSB_DATA_0 LVDSB_DATA_1 LVDSB_DATA_2

TVA_DAC TVB_DAC TVC_DAC

TVA_RTN TVB_RTN TVC_RTN

TV_DCONSEL_0 TV_DCONSEL_1

CRT_BLUE CRT_BLUE# CRT_GREEN CRT_GREEN# CRT_RED CRT_RED#

CRT_DDC_CLK CRT_DDC_DATA CRT_HSYNC CRT_TVO_IREF CRT_VSYNC

LVDS

TV VGA

PEG_COMPI

PEG_COMPO

PEG_RX#_0 PEG_RX#_1 PEG_RX#_2 PEG_RX#_3 PEG_RX#_4 PEG_RX#_5 PEG_RX#_6 PEG_RX#_7 PEG_RX#_8

PEG_RX#_9 PEG_RX#_10 PEG_RX#_11 PEG_RX#_12 PEG_RX#_13 PEG_RX#_14 PEG_RX#_15

PEG_RX_0 PEG_RX_1 PEG_RX_2 PEG_RX_3 PEG_RX_4 PEG_RX_5 PEG_RX_6 PEG_RX_7 PEG_RX_8

PEG_RX_9 PEG_RX_10 PEG_RX_11 PEG_RX_12 PEG_RX_13 PEG_RX_14 PEG_RX_15

PEG_TX#_0 PEG_TX#_1 PEG_TX#_2 PEG_TX#_3 PEG_TX#_4 PEG_TX#_5 PEG_TX#_6 PEG_TX#_7 PEG_TX#_8 PEG_TX#_9

PEG_TX#_10

PCI-EXPRESS GRAPHICS

PEG_TX#_11 PEG_TX#_12 PEG_TX#_13 PEG_TX#_14 PEG_TX#_15

PEG_TX_0

PEG_TX_1

PEG_TX_2

PEG_TX_3

PEG_TX_4

PEG_TX_5

PEG_TX_6

PEG_TX_7

PEG_TX_8

PEG_TX_9 PEG_TX_10 PEG_TX_11 PEG_TX_12 PEG_TX_13 PEG_TX_14 PEG_TX_15

N43 M43

J51 L51 N47 T45 T50 U40 Y44 Y40 AB51 W49 AD44 AD40 AG46 AH49 AG45 AG41

J50 L50 M47 U44 T49 T41 W45 W41 AB50 Y48 AC45 AC41 AH47 AG49 AH45 AG42

N45 U39 U47 N51 R50 T42 Y43 W46 W38 AD39 AC46 AC49 AC42 AH39 AE49 AH44

M45 T38 T46 N50 R51 U43 W42 Y47 Y39 AC38 AD47 AC50 AD43 AG39 AE50 AH43

PEGCOMP

PEG_TXN0 PEG_TXN1 PEG_TXN2 PEG_TXN3 PEG_TXN4 PEG_TXN5 PEG_TXN6 PEG_TXN7 PEG_TXN8 PEG_TXN9 PEG_TXN10 PEG_TXN11 PEG_TXN12 PEG_TXN13 PEG_TXN14 PEG_TXN15

PEG_TXP0 PEG_TXP1 PEG_TXP2 PEG_TXP3 PEG_TXP4 PEG_TXP5 PEG_TXP6 PEG_TXP7 PEG_TXP8 PEG_TXP9 PEG_TXP10 PEG_TXP11 PEG_TXP12 PEG_TXP13 PEG_TXP14

R1176

24.9_0402_1%

1 2

PEG_RXN0 PEG_RXN1 PEG_RXN2 PEG_RXN3 PEG_RXN4 PEG_RXN5 PEG_RXN6 PEG_RXN7 PEG_RXN8 PEG_RXN9 PEG_RXN10 PEG_RXN11 PEG_RXN12 PEG_RXN13 PEG_RXN14 PEG_RXN15

PEG_RXP0 PEG_RXP1 PEG_RXP2 PEG_RXP3 PEG_RXP4 PEG_RXP5 PEG_RXP6 PEG_RXP7 PEG_RXP8 PEG_RXP9 PEG_RXP10 PEG_RXP11 PEG_RXP12 PEG_RXP13 PEG_RXP14 PEG_RXP15

C1058 0.1U_0402_16V4ZC1058 0.1U_0402_16V4Z C1059 0.1U_0402_16V4ZC1059 0.1U_0402_16V4Z C1060 0.1U_0402_16V4ZC1060 0.1U_0402_16V4Z C1559 0.1U_0402_16V4ZC1559 0.1U_0402_16V4Z C1562 0.1U_0402_16V4Z

C1562 0.1U_0402_16V4Z C1563 0.1U_0402_16V4Z

C1563 0.1U_0402_16V4Z C1560 0.1U_0402_16V4Z

C1560 0.1U_0402_16V4Z C1561 0.1U_0402_16V4Z

C1561 0.1U_0402_16V4Z C1564 0.1U_0402_16V4Z

C1564 0.1U_0402_16V4Z C1361 0.1U_0402_16V4Z

C1361 0.1U_0402_16V4Z C1362 0.1U_0402_16V4Z

C1362 0.1U_0402_16V4Z C1363 0.1U_0402_16V4Z

C1363 0.1U_0402_16V4Z C1364 0.1U_0402_16V4Z

C1364 0.1U_0402_16V4Z C1365 0.1U_0402_16V4Z

C1365 0.1U_0402_16V4Z C1366 0.1U_0402_16V4Z

C1366 0.1U_0402_16V4Z C1367 0.1U_0402_16V4Z

C1367 0.1U_0402_16V4Z C1062 0.1U_0402_16V4ZC1062 0.1U_0402_16V4Z

C1063 0.1U_0402_16V4ZC1063 0.1U_0402_16V4Z C1066 0.1U_0402_16V4ZC1066 0.1U_0402_16V4Z C1067 0.1U_0402_16V4ZC1067 0.1U_0402_16V4Z C1368 0.1U_0402_16V4Z

C1368 0.1U_0402_16V4Z C1369 0.1U_0402_16V4Z

C1369 0.1U_0402_16V4Z C1370 0.1U_0402_16V4Z

C1370 0.1U_0402_16V4Z C1371 0.1U_0402_16V4Z

C1371 0.1U_0402_16V4Z C1372 0.1U_0402_16V4Z

C1372 0.1U_0402_16V4Z C1373 0.1U_0402_16V4Z

C1373 0.1U_0402_16V4Z C1374 0.1U_0402_16V4Z

C1374 0.1U_0402_16V4Z C1375 0.1U_0402_16V4Z

C1375 0.1U_0402_16V4Z C1376 0.1U_0402_16V4Z

C1376 0.1U_0402_16V4Z C1377 0.1U_0402_16V4Z

C1377 0.1U_0402_16V4Z C1378 0.1U_0402_16V4Z

C1378 0.1U_0402_16V4Z C1379 0.1U_0402_16V4Z

C1379 0.1U_0402_16V4Z

1 2 1 2 1 2 1 2

+VCCP

PEG_RXN[0..15] <18>

PEG_RXP[0..15] <18>

PEGCOMP trace width and spacing is 20/25 mils.

PEG_M_TXN0 PEG_M_TXN1 PEG_M_TXN2 PEG_M_TXN3 PEG_M_TXN4 PEG_M_TXN5 PEG_M_TXN6 PEG_M_TXN7 PEG_M_TXN8 PEG_M_TXN9 PEG_M_TXN10 PEG_M_TXN11 PEG_M_TXN12 PEG_M_TXN13 PEG_M_TXN14 PEG_M_TXN15

PEG_M_TXP0 PEG_M_TXP1 PEG_M_TXP2 PEG_M_TXP3 PEG_M_TXP4 PEG_M_TXP5 PEG_M_TXP6 PEG_M_TXP7 PEG_M_TXP8 PEG_M_TXP9 PEG_M_TXP10 PEG_M_TXP11 PEG_M_TXP12 PEG_M_TXP13 PEG_M_TXP14 PEG_M_TXP15

PEG_M_TXN[0..15] <18>

PEG_M_TXP[0..15] <18>

CFG[2:0] FSB Freq select

CFG7 (CPU Strap)

CFG8 (Low power PCIE)

(PCIE Graphics Lane Reversal)

CFG[13:12] (XOR/ALLZ)

CFG16 (FSB Dynamic ODT)

SDVO_CTRLDATA

CFG19 (DMI Lane Reversal)

CFG20 (PCIE/SDVO concurrent)

J37

CFG5PEG_TXP15

2 1

PAD-NO SHORT 2x2m

Strap Pin Table

CFG5 (DMI select)

CFG6

CFG9

CFG[11:10]

010 = FSB 800MHz 011 = FSB 667MHz Others = Reserved

0 = DMI x 2 1 = DMI x 4

*

Reserved

0 = Reserved 1 = Mobile CPU

*

0 = Normal mode 1 = Low Power mode

*

0 = Reverse Lane 1 = Normal Operation

*

Reserved 00 = Reserved

01 = XOR Mode Enabled 10 = All Z Mode Enabled 11 = Normal Operation

(Default)

ReservedCFG[15:14]

0 = Disabled 1 = Enabled

*

ReservedCFG[18:17]

0 = No SDVO Device Present 1 = SDVO Device Present

0 = Normal Operation

(Lane number in Order)

*

1 = Reverse Lane

0 = Only PCIE or SDVO is operational. 1 = PCIE/SDVO are operating simu.

R1151 4.02K_0402_1%@R1151 4.02K_0402_1%@

CFG5<7>

CFG7<7>

CFG8<7>

CFG9<7>

CFG12<7>

CFG13<7>

CFG16<7>

1 2

R1152 4.02K_0402_1%@R1152 4.02K_0402_1%@

1 2

R1451 4.02K_0402_1%@R1451 4.02K_0402_1%@

1 2

R1153 4.02K_0402_1%@R1153 4.02K_0402_1%@

1 2

R1155 4.02K_0402_1%@R1155 4.02K_0402_1%@

1 2

R1156 4.02K_0402_1%@R1156 4.02K_0402_1%@

1 2

R1157 4.02K_0402_1%@R1157 4.02K_0402_1%@

1 2

*

CFG[17:3] have internal pull up CFG[19:18] have internal pull down

+3VS

R1159 4.02K_0402_1%@R1159 4.02K_0402_1%@

CFG19<7>

CFG20<7>

A A

1 2

R1160 4.02K_0402_1%@R1160 4.02K_0402_1%@

1 2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/09/25 2006/09/25

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

CRESTLINE((3/6)-VGA/LVDS/TV

LA3262P_DIS__M64

1

of

957Tuesday, August 21, 2007

1A

5

4

3

2

1

1 2

0_0603_5%

R1458

R1460

12

R1455

+1.25VM

+1.25VS

+1.8V

+1.5VS

22U_0805_6.3VAM

1

C1230

2

+1.5VS_TVDAC

10U_0603_6.3V6M

C1607

1

2

+1.25VM_HPLL

0.1U_0402_16V4Z

+V1.25VS_AXF

10U_0603_6.3V6M

1

2

+1.8V_SM_CK

22U_0805_6.3VAM

1

2

1

C1124

2

1

C1134

2

+3VS_HV

C1111

C1115

0.022U_0402_16V7K

1

C1125

2

1

2

1U_0603_10V4Z

C1112

1

2

1 2

0.1U_0402_16V4Z

0.1U_0402_16V4Z 0_0805_5%

0_0805_5%

C1116

1

2

1 2

0.1U_0402_16V4Z

0.1U_0402_16V4Z 0_0805_5%

0_0805_5%

R1464

MBK2012121YZF_0805

C1135

C1135 22U_0805_6.3VAM

22U_0805_6.3VAM

+1.25VS_PEGPLL

C1123

10U_0603_6.3V6M

+VCC_PEG

+1.25VM_MPLL

0.1U_0402_16V4Z

+1.25VS_DMI

1

2

12

1

2

220U_D2_4VM_R15

1

C1227

+

2

1

2

C1139

+VCCP

1 2

0.1U_0402_16V4Z

0.1U_0402_16V4Z R1457

R1457

0_0603_5%

C1117

+1.25VS

L77

12

MBK2012221YZF_0805

MBK2012221YZF_0805 R1468

R1468 1_0402_5%

1_0402_5%

0904 change

10U_0603_6.3V6M

C1138

1

2

100NH_LQW18ANR10J00D_5%_0805

R1466

MBK2012121YZF_0805

1

C1140

2

22U_0805_6.3VAM

D12

2 1

CH751H-40PT_SOD323-2

+3VS

+1.25VS

@

R1465

0_0805_5%

R1467

1 2

+1.25VM

12

+VCCP_D

+VCCP

12

+1.25VS

(link CIS)

R1469

10_0402_5%

0_0402_5%

0_0402_5% R1470

R1470

12

U15H

J32

VCCSYNC

A33

VCCA_CRT_DAC_1

B33

VCCA_CRT_DAC_2

D D

+1.25VM_HPLL +1.25VM_MPLL

+3VS_PEG_BG

R1459

0_0603_5%

0.1U_0402_16V4Z

R1461

1 2

0_0805_5%

C1127

1U_0402_6.3V4Z

C1130

1

2

+1.25VM_HPLL

12

1

C1121

2

0.1U_0402_16V4Z

+1.25VM_A_SM

0317 change value

1

C1128

4.7U_0603_6.3V6M

2

1U_0603_10V4Z

22U_0805_6.3VAM

C1131

1

2

C1608

0.1U_0402_16V4Z

+1.25VS_PEGPLL

1

2

1U_0603_10V4Z

0.1U_0402_16V4Z

C1132

1

2

+1.5VS_TVDAC

1

+1.25VS_PEGPLL

2

0.1U_0402_16V4Z

C1606

C1122

1

2

1

2

C1129

+3VS

+1.25VM

C C

150U_D_6.3VM

B B

C1126

R1462

0_0603_5%

1

+

22U_0805_6.3VAM

2

+1.25VM_A_SM_CK

12

C1226

20 mils

1

2

A30

VCCA_DAC_BG

B32

VSSA_DAC_BG

B49

VCCA_DPLLA

H49

VCCA_DPLLB

AL2

VCCA_HPLL

AM2

VCCA_MPLL

A41

VCCA_LVDS

B41

VSSA_LVDS

K50

VCCA_PEG_BG

K49

VSSA_PEG_BG

U51

VCCA_PEG_PLL

AW18

VCCA_SM_1

AV19

VCCA_SM_2

AU19

VCCA_SM_3

AU18

VCCA_SM_4

AU17

VCCA_SM_5

AT22

VCCA_SM_7

AT21

VCCA_SM_8

AT19

VCCA_SM_9

AT18

VCCA_SM_10

AT17

VCCA_SM_11

AR17

VCCA_SM_NCTF_1

AR16

VCCA_SM_NCTF_2

BC29

VCCA_SM_CK_1

BB29

VCCA_SM_CK_2

C25

VCCA_TVA_DAC_1

B25

VCCA_TVA_DAC_2

C27

VCCA_TVB_DAC_1

B27

VCCA_TVB_DAC_2

B28

VCCA_TVC_DAC_1

A28

VCCA_TVC_DAC_2

M32

VCCD_CRT

L29

VCCD_TVDAC

N28

VCCD_QDAC

AN2

VCCD_HPLL

U48

VCCD_PEG_PLL

J41

VCCD_LVDS_1

H42

VCCD_LVDS_2

CRESTLINE_1p0

CRTPLLA PEGA SMTV

POWER

A CK A LVDS

D TV/CRTLVDS

VTT_10 VTT_11 VTT_12 VTT_13

VTT

VTT_14 VTT_15 VTT_16 VTT_17 VTT_18 VTT_19 VTT_20 VTT_21 VTT_22

VCC_AXD_1 VCC_AXD_2 VCC_AXD_3 VCC_AXD_4 VCC_AXD_5

AXD

VCC_AXD_6

VCC_AXD_NCTF

VCC_AXF_1 VCC_AXF_2 VCC_AXF_3

AXF

VCC_DMI

VCC_SM_CK_1 VCC_SM_CK_2 VCC_SM_CK_3 VCC_SM_CK_4

SM CK

VCC_TX_LVDS

VCC_HV_1 VCC_HV_2

HV

VCC_PEG_1 VCC_PEG_2 VCC_PEG_3 VCC_PEG_4

PEG

VCC_PEG_5

VCC_RXR_DMI_1 VCC_RXR_DMI_2

DMI

VTTLF1 VTTLF2 VTTLF3

VTTLF

VTT_1 VTT_2 VTT_3 VTT_4 VTT_5 VTT_6 VTT_7 VTT_8 VTT_9

U13 U12 U11 U9 U8 U7 U5 U3 U2 U1 T13 T11 T10 T9 T7 T6 T5 T3 T2 R3 R2 R1

AT23 AU28 AU24 AT29 AT25 AT30

AR29

B23 B21 A21

AJ50

BK24 BK23 BJ24 BJ23

A43

C40 B40

AD51 W50 W51 V49 V50

AH50 AH51

A7 F2 AH1

+VCCP

330U_D2E_2.5VM_R15

C830

+1.25VM_AXD

250mA

+V1.25VS_AXF

+1.8V_SM_CK

+VCC_DMI

0.47U_0402_10V4Z~D

0.47U_0402_10V4Z~D C1142

C1142

C1141

1

2

1

+

2

1

C849

2

1U_0402_6.3V4Z

C1119

1

2

+1.25VS_DMI

+VCC_PEG

20mils

0.47U_0402_10V4Z~D

0.47U_0402_10V4Z~D C1143

C1143

1

2

0.47U_0603_10V7K

C836

C1120

1

2

0.47U_0402_10V4Z~D

1

2

4.7U_0603_6.3V6M

1

C838

2

4.7U_0603_6.3V6M

1

2

R1671

1 2

0_0805_5%

10U_0603_6.3V6M

C837

+3VS_HV

C1136

2.2U_0603_6.3V4Z

1

2

0.1U_0402_16V4Z

1

2

+1.25VM

0904 change

L94

1 2

R84

+1.25VS

(link CIS)

+VCCP

C1614

10U_0603_6.3V6M

+VCC_DMI

1

C1615

2

10U_0603_6.3V6M

@

1 2

100NH_LQW18ANR10J00D_5%_0805

1

2

0_0805_5%

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/09/25 2006/09/25

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

CRESTLINE(4/6)-PWR

LA3262P_DIS__M64

1

1A

of

10 57Tuesday, August 21, 2007

5

4

3

2

1

+VCCP

C798

1

2

C1160

1 2

0.1U_0402_16V4Z

10U_0603_6.3V6M

C1154

1

2

R1711

@R1711

@

2

G

C797

1

2

C1155

1

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z C1161

C1161

CRACK_GPIO28

13

D

S

+VCCP

U15F

AB33

VCC_NCTF_1

AB36

VCC_NCTF_2

AB37

VCC_NCTF_3

AC33

VCC_NCTF_4

AC35

VCC_NCTF_5

AC36

VCC_NCTF_6

AD35

VCC_NCTF_7

AD36

VCC_NCTF_8

AF33

VCC_NCTF_9

AF36

VCC_NCTF_10

AH33

VCC_NCTF_11

AH35

VCC_NCTF_12

AH36

VCC_NCTF_13

AH37

VCC_NCTF_14

AJ33

VCC_NCTF_15

AJ35

VCC_NCTF_16

AK33

VCC_NCTF_17

AK35

VCC_NCTF_18

AK36

VCC_NCTF_19

AK37

VCC_NCTF_20

AD33

VCC_NCTF_21

AJ36

VCC_NCTF_22

AM35

VCC_NCTF_23

AL33

VCC_NCTF_24

AL35

VCC_NCTF_25

AA33

VCC_NCTF_26

AA35

VCC_NCTF_27

AA36

VCC_NCTF_28

AP35

VCC_NCTF_29

AP36

VCC_NCTF_30

AR35

VCC_NCTF_31

AR36

VCC_NCTF_32

Y32

VCC_NCTF_33

Y33

VCC_NCTF_34

Y35

VCC_NCTF_35

Y36

VCC_NCTF_36

Y37

VCC_NCTF_37

T30

VCC_NCTF_38

T34

VCC_NCTF_39

T35

VCC_NCTF_40

U29

VCC_NCTF_41

U31

VCC_NCTF_42

U32

VCC_NCTF_43

U33

VCC_NCTF_44

U35

VCC_NCTF_45

U36

VCC_NCTF_46

V32

VCC_NCTF_47

V33

VCC_NCTF_48

V36

VCC_NCTF_49

V37

VCC_NCTF_50

AL24

VCC_AXM_NCTF_1

AL26

VCC_AXM_NCTF_2

AL28

VCC_AXM_NCTF_3

AM26

VCC_AXM_NCTF_4

AM28

VCC_AXM_NCTF_5

AM29

VCC_AXM_NCTF_6

AM31

VCC_AXM_NCTF_7

AM32

VCC_AXM_NCTF_8

AM33

VCC_AXM_NCTF_9

AP29

VCC_AXM_NCTF_10

AP31

VCC_AXM_NCTF_11

AP32

VCC_AXM_NCTF_12

AP33

VCC_AXM_NCTF_13

AL29

VCC_AXM_NCTF_14

AL31

VCC_AXM_NCTF_15

AL32

VCC_AXM_NCTF_16

AR31

VCC_AXM_NCTF_17

AR32

VCC_AXM_NCTF_18

AR33

VCC_AXM_NCTF_19

CRESTLINE_1p0

+3VS

1 2

100K_0402_5%

MCHGND2

Q121

@

Q121

@

RHU002N06_SOT323

VCC NCTF

POWER

VCC AXM NCTF

R1709

@R1709

@

CRACK_GPIO28

13

D

2

G

S

4

VSS_NCTF_1 VSS_NCTF_2 VSS_NCTF_3 VSS_NCTF_4 VSS_NCTF_5 VSS_NCTF_6 VSS_NCTF_7 VSS_NCTF_8

VSS_NCTF_9 VSS_NCTF_10 VSS_NCTF_11 VSS_NCTF_12 VSS_NCTF_13 VSS_NCTF_14 VSS_NCTF_15

VSS NCTF

VSS_NCTF_16 VSS_NCTF_17 VSS_NCTF_18 VSS_NCTF_19 VSS_NCTF_20 VSS_NCTF_21

VSS_SCB1 VSS_SCB2 VSS_SCB3 VSS_SCB4 VSS_SCB5 VSS_SCB6

VSS SCBVCC AXM

VCC_AXM_1 VCC_AXM_2 VCC_AXM_3 VCC_AXM_4 VCC_AXM_5 VCC_AXM_6 VCC_AXM_7

100K_0402_5%

MCHGND5MCHGND6

T27 T37 U24 U28 V31 V35 AA19 AB17 AB35 AD19 AD37 AF17 AF35 AK17 AM17 AM24 AP26 AP28 AR15 AR19 AR28

MCHGND1

A3

MCHGND2

B2

MCHGND3

C1

MCHGND4

BL1

MCHGND5

BL51

MCHGND6

A51

AT33 AT31 AK29 AK24 AK23 AJ26 AJ23

R1703

@R1703

@

1 2

2

G

RHU002N06_SOT323

G

@

Q119

R112

R112 R132

R132 R133

R133 R122

R122 R113

R113 R111

R111

+3VL

R1702

CRACK_GPIO28

1 2 13

D

100K_0402_5%

S

R1475

1 2

0_0603_5%

330U_D2E_2.5VM_R15

+1.8V

0_0402_5%

0_0402_5% 0_0402_5%

0_0402_5%

1 2 1 2 1 2 1 2 1 2 1 2

+1.05VM

CRACK_GPIO28 <27,37>

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

22U_0805_6.3VAM

1

+

C808

2

2006/09/25 2006/09/25

22U_0805_6.3VAM

C809

1

2

0.01U_0402_16V7K

C810

C794

1

2

1

Compal Secret Data

Deciphered Date

D D

22U_0805_6.3VAM

0.22U_0402_10V4Z

220U_D2_4VM_R15

1

C806

+

2

C C

B B

0.22U_0402_10V4Z

0.22U_0402_10V4Z C1157

C1157

1

2

+3VS +3VS

A A

100K_0402_5%

R1701

@R1701

@

Q118

@

Q118

@

RHU002N06_SOT323

CRACK_GPIO28

13

D

1 2

2

G

S

0.22U_0402_10V4Z

C803

C796

1

2

+1.05VM

10U_0603_6.3V6M

0.1U_0402_16V4Z

0.22U_0402_10V4Z

0.22U_0402_10V4Z C1159

C1159

C1158

1

2

04/10 monitor NB crack

MCHGND4

@

RHU002N06_SOT323

5

1

2

0.1U_0402_16V4Z

+3VS

100K_0402_5%

Q123

AT35 AT34 AH28 AC32 AC31 AK32

AJ31

AJ28 AH32 AH31 AH29 AF32

AU32 AU33 AU35 AV33

AW33 AW35

AY35 BA32 BA33 BA35 BB33 BC32 BC33 BC35 BD32 BD35 BE32 BE33 BE35 BF33 BF34 BG32 BG33 BG35 BH32 BH34 BH35

BJ32

BJ33

BJ34 BK32 BK33 BK34 BK35

BL33 AU30

W13

W14 AA20

AA23 AA26 AA28 AB21 AB24 AB29 AC20 AC21 AC23 AC24 AC26 AC28 AC29 AD20 AD23 AD24 AD28 AF21 AF26 AA31 AH20 AH21 AH23 AH24 AH26 AD31

AJ20 AN14

R30

R20

T14

Y12

U15G

VCC_1 VCC_2 VCC_3 VCC_5 VCC_4 VCC_6 VCC_7 VCC_8 VCC_9 VCC_10 VCC_11 VCC_12

VCC_13

VCC_SM_1 VCC_SM_2 VCC_SM_3 VCC_SM_4 VCC_SM_5 VCC_SM_6 VCC_SM_7 VCC_SM_8 VCC_SM_9 VCC_SM_10 VCC_SM_11 VCC_SM_12 VCC_SM_13 VCC_SM_14 VCC_SM_15 VCC_SM_16 VCC_SM_17 VCC_SM_18 VCC_SM_19 VCC_SM_20 VCC_SM_21 VCC_SM_22 VCC_SM_23 VCC_SM_24 VCC_SM_25 VCC_SM_26 VCC_SM_27 VCC_SM_28 VCC_SM_29 VCC_SM_30 VCC_SM_31 VCC_SM_32 VCC_SM_33 VCC_SM_34 VCC_SM_35 VCC_SM_36

VCC_AXG_1 VCC_AXG_2 VCC_AXG_3 VCC_AXG_4 VCC_AXG_5 VCC_AXG_6 VCC_AXG_7 VCC_AXG_8 VCC_AXG_9 VCC_AXG_10 VCC_AXG_11 VCC_AXG_12 VCC_AXG_13 VCC_AXG_14 VCC_AXG_15 VCC_AXG_16 VCC_AXG_17 VCC_AXG_18 VCC_AXG_19 VCC_AXG_20 VCC_AXG_21 VCC_AXG_22 VCC_AXG_23 VCC_AXG_24 VCC_AXG_25 VCC_AXG_26 VCC_AXG_27 VCC_AXG_28 VCC_AXG_29 VCC_AXG_30 VCC_AXG_31 VCC_AXG_32 VCC_AXG_33 VCC_AXG_34

CRESTLINE_1p0

2

VCC CORE

POWER

VCC SMVCC GFX

VCC_AXG_NCTF_1 VCC_AXG_NCTF_2 VCC_AXG_NCTF_3 VCC_AXG_NCTF_4 VCC_AXG_NCTF_5 VCC_AXG_NCTF_6 VCC_AXG_NCTF_7 VCC_AXG_NCTF_8

VCC_AXG_NCTF_9 VCC_AXG_NCTF_10 VCC_AXG_NCTF_11 VCC_AXG_NCTF_12 VCC_AXG_NCTF_13 VCC_AXG_NCTF_14 VCC_AXG_NCTF_15 VCC_AXG_NCTF_16 VCC_AXG_NCTF_17 VCC_AXG_NCTF_18 VCC_AXG_NCTF_19 VCC_AXG_NCTF_20 VCC_AXG_NCTF_21 VCC_AXG_NCTF_22 VCC_AXG_NCTF_23 VCC_AXG_NCTF_24 VCC_AXG_NCTF_25 VCC_AXG_NCTF_26 VCC_AXG_NCTF_27 VCC_AXG_NCTF_28 VCC_AXG_NCTF_29 VCC_AXG_NCTF_30 VCC_AXG_NCTF_31 VCC_AXG_NCTF_32 VCC_AXG_NCTF_33 VCC_AXG_NCTF_34 VCC_AXG_NCTF_35 VCC_AXG_NCTF_36 VCC_AXG_NCTF_37 VCC_AXG_NCTF_38 VCC_AXG_NCTF_39 VCC_AXG_NCTF_40 VCC_AXG_NCTF_41 VCC_AXG_NCTF_42 VCC_AXG_NCTF_43 VCC_AXG_NCTF_44 VCC_AXG_NCTF_45 VCC_AXG_NCTF_46 VCC_AXG_NCTF_47 VCC_AXG_NCTF_48 VCC_AXG_NCTF_49 VCC_AXG_NCTF_50 VCC_AXG_NCTF_51 VCC_AXG_NCTF_52 VCC_AXG_NCTF_53 VCC_AXG_NCTF_54

VCC GFX NCTF

VCC_AXG_NCTF_55 VCC_AXG_NCTF_56 VCC_AXG_NCTF_57 VCC_AXG_NCTF_58 VCC_AXG_NCTF_59 VCC_AXG_NCTF_60 VCC_AXG_NCTF_61 VCC_AXG_NCTF_62 VCC_AXG_NCTF_63 VCC_AXG_NCTF_64 VCC_AXG_NCTF_65 VCC_AXG_NCTF_66 VCC_AXG_NCTF_67 VCC_AXG_NCTF_68 VCC_AXG_NCTF_69 VCC_AXG_NCTF_70 VCC_AXG_NCTF_71 VCC_AXG_NCTF_72 VCC_AXG_NCTF_73 VCC_AXG_NCTF_74 VCC_AXG_NCTF_75 VCC_AXG_NCTF_76 VCC_AXG_NCTF_77 VCC_AXG_NCTF_78 VCC_AXG_NCTF_79 VCC_AXG_NCTF_80 VCC_AXG_NCTF_81 VCC_AXG_NCTF_82 VCC_AXG_NCTF_83

VCC_SM_LF1 VCC_SM_LF2 VCC_SM_LF3 VCC_SM_LF4 VCC_SM_LF5 VCC_SM_LF6 VCC_SM_LF7

VCC SM LF

Title

Size Document Number Rev

Custom

Date: Sheet

T17 T18 T19 T21 T22 T23 T25 U15 U16 U17 U19 U20 U21 U23 U26 V16 V17 V19 V20 V21 V23 V24 Y15 Y16 Y17 Y19 Y20 Y21 Y23 Y24 Y26 Y28 Y29 AA16 AA17 AB16 AB19 AC16 AC17 AC19 AD15 AD16 AD17 AF16 AF19 AH15 AH16 AH17 AH19 AJ16 AJ17 AJ19 AK16 AK19 AL16 AL17 AL19 AL20 AL21 AL23 AM15 AM16 AM19 AM20 AM21 AM23 AP15 AP16 AP17 AP19 AP20 AP21 AP23 AP24 AR20 AR21 AR23 AR24 AR26 V26 V28 V29 Y31

VCCSM_LF1

AW45

VCCSM_LF2

BC39

VCCSM_LF3

BE39

VCCSM_LF4

BD17 BD4 AW8 AT6

LA3262P_DIS__M64

VCCSM_LF5 VCCSM_LF6 VCCSM_LF7

Compal Electronics, Inc.

CRESTLINE((5/6)-PWR/GND

C1162 0.1U_0402_16V4Z C1162 0.1U_0402_16V4Z

C1318 0.22U_0603_10V7K C1318 0.22U_0603_10V7K

C1163 0.1U_0402_16V4Z C1163 0.1U_0402_16V4Z

1

2

C795 0.22U_0603_10V7K C795 0.22U_0603_10V7K

1

2

1

C813 1U_0603_10V4Z C813 1U_0603_10V4Z

C814 1U_0603_10V4Z C814 1U_0603_10V4Z

C1164 0.47U_0402_10V4Z~D C1164 0.47U_0402_10V4Z~D

1

2

1A

of

11 57Tuesday, August 21, 2007

5

U15I

A13

VSS_1

A15

VSS_2

A17

VSS_3

A24

VSS_4

AA21

VSS_5

AA24

VSS_6

AA29

VSS_7

AB20

D D

C C

B B

A A

AB23 AB26 AB28

AB31 AC10 AC13

AC39 AC43 AC47

AD21 AD26 AD29

AD41 AD45 AD49

AD50

AE10

AE14

AF20

AF23

AF24

AF31

AG2 AG38 AG43 AG47 AG50

AH40 AH41

AJ11 AJ13 AJ21 AJ24 AJ29 AJ32 AJ43 AJ45 AJ49 AK20 AK21 AK26 AK28 AK31 AK51

AM11 AM13

AM3

AM4 AM41 AM45

AN38 AN39 AN43

AP48 AP50

AR11 AR39

AR44 AR47

AT10 AT14 AT41 AT49

AU23 AU29

AU36 AU49 AU51

AV39 AV48

AW1 AW12 AW16

AC3

AD1

AD3

AD5 AD8

AE6

AH3

AH7 AH9

AL1

AN1

AN5 AN7 AP4

AR2

AR7

AU1

AU3

VSS_8 VSS_9 VSS_10 VSS_11 VSS_12 VSS_13 VSS_14 VSS_15 VSS_16 VSS_17 VSS_18 VSS_19 VSS_20 VSS_21 VSS_22 VSS_23 VSS_24 VSS_25 VSS_26 VSS_27 VSS_28 VSS_29 VSS_30 VSS_31 VSS_32 VSS_33 VSS_34 VSS_35 VSS_36 VSS_37 VSS_38 VSS_39 VSS_40 VSS_41 VSS_42 VSS_43 VSS_44 VSS_45 VSS_46 VSS_47 VSS_48 VSS_49 VSS_50 VSS_51 VSS_52 VSS_53 VSS_54 VSS_55 VSS_56 VSS_57 VSS_58 VSS_59 VSS_60 VSS_61 VSS_62 VSS_63 VSS_64 VSS_65 VSS_66 VSS_67 VSS_68 VSS_69 VSS_70 VSS_71 VSS_72 VSS_73 VSS_74 VSS_75 VSS_76 VSS_77 VSS_78 VSS_79 VSS_80 VSS_81 VSS_82 VSS_83 VSS_84 VSS_85 VSS_86 VSS_87 VSS_88 VSS_89 VSS_90 VSS_91 VSS_92 VSS_93 VSS_94 VSS_95 VSS_96 VSS_97 VSS_98 VSS_99

CRESTLINE_1p0

VSS

VSS_100 VSS_101 VSS_102 VSS_103 VSS_104 VSS_105 VSS_106 VSS_107 VSS_108 VSS_109 VSS_110 VSS_111 VSS_112 VSS_113 VSS_114 VSS_115 VSS_116 VSS_117 VSS_118 VSS_119 VSS_120 VSS_121 VSS_122 VSS_123 VSS_124 VSS_125 VSS_126 VSS_127 VSS_128 VSS_129 VSS_130 VSS_131 VSS_132 VSS_133 VSS_134 VSS_135 VSS_136 VSS_137 VSS_138 VSS_139 VSS_140 VSS_141 VSS_142 VSS_143 VSS_144 VSS_145 VSS_146 VSS_147 VSS_148 VSS_149 VSS_150 VSS_151 VSS_152 VSS_153 VSS_154 VSS_155 VSS_156 VSS_157 VSS_158 VSS_159 VSS_160 VSS_161 VSS_162 VSS_163 VSS_164 VSS_165 VSS_166 VSS_167 VSS_168 VSS_169 VSS_170 VSS_171 VSS_172 VSS_173 VSS_174 VSS_175 VSS_176 VSS_177 VSS_178 VSS_179 VSS_180 VSS_181 VSS_182 VSS_183 VSS_184 VSS_185 VSS_186 VSS_187 VSS_188 VSS_189 VSS_190 VSS_191 VSS_192 VSS_193 VSS_194 VSS_195 VSS_196 VSS_197 VSS_198

4

AW24 AW29 AW32 AW5 AW7 AY10 AY24 AY37 AY42 AY43 AY45 AY47 AY50 B10 B20 B24 B29 B30 B35 B38 B43 B46 B5 B8 BA1 BA17 BA18 BA2 BA24 BB12 BB25 BB40 BB44 BB49 BB8 BC16 BC24 BC25 BC36 BC40 BC51 BD13 BD2 BD28 BD45 BD48 BD5 BE1 BE19 BE23 BE30 BE42 BE51 BE8 BF12 BF16 BF36 BG19 BG2 BG24 BG29 BG39 BG48 BG5 BG51 BH17 BH30 BH44 BH46 BH8 BJ11 BJ13 BJ38 BJ4 BJ42 BJ46 BK15 BK17 BK25 BK29 BK36 BK40 BK44 BK6 BK8 BL11 BL13 BL19 BL22 BL37 BL47 C12 C16 C19 C28 C29 C33 C36 C41

3

U15J

C46 C50

C7 D13 D24

D3 D32 D39 D45 D49 E10 E16 E24 E28 E32 E47 F19 F36

F4 F40 F50

G1 G13 G16 G19 G24 G28 G29 G33 G42 G45 G48

G8 H24 H28

H4 H45

J11 J16

J2 J24 J28 J33 J35 J39

K12 K47

K8

L1 L17 L20 L24 L28

L3 L33 L49

M28 M42 M46 M49

M5

M50

M9 N11 N14 N17 N29 N32 N36 N39 N44 N49

N7 P19

P2

P23

P3 P50 R49 T39 T43 T47 U41 U45 U50

V2

V3

CRESTLINE_1p0

VSS_199 VSS_200 VSS_201 VSS_202 VSS_203 VSS_204 VSS_205 VSS_206 VSS_207 VSS_208 VSS_209 VSS_210 VSS_211 VSS_212 VSS_213 VSS_214 VSS_215 VSS_216 VSS_217 VSS_218 VSS_219 VSS_220 VSS_221 VSS_222 VSS_223 VSS_224 VSS_225 VSS_226 VSS_227 VSS_228 VSS_229 VSS_230 VSS_231 VSS_232 VSS_233 VSS_234 VSS_235 VSS_236 VSS_237 VSS_238 VSS_239 VSS_240 VSS_241 VSS_242 VSS_243

VSS_245 VSS_246 VSS_247 VSS_248 VSS_249 VSS_250 VSS_251 VSS_252 VSS_253 VSS_254 VSS_255 VSS_256 VSS_257 VSS_258 VSS_259 VSS_260 VSS_261 VSS_262 VSS_263 VSS_264 VSS_265 VSS_266 VSS_267 VSS_268 VSS_269 VSS_270 VSS_271 VSS_272 VSS_273 VSS_274 VSS_275 VSS_276 VSS_277 VSS_278 VSS_279 VSS_280 VSS_281 VSS_282 VSS_283 VSS_284 VSS_285 VSS_286

VSS

VSS_287 VSS_288 VSS_289 VSS_290 VSS_291 VSS_292 VSS_293 VSS_294 VSS_295 VSS_296 VSS_297 VSS_298 VSS_299 VSS_300 VSS_301 VSS_302 VSS_303 VSS_304 VSS_305

VSS_306 VSS_307 VSS_308 VSS_309 VSS_310 VSS_311 VSS_312 VSS_313

W11 W39 W43 W47 W5 W7 Y13 Y2 Y41 Y45 Y49 Y5 Y50 Y11 P29 T29 T31 T33 R28

AA32 AB32 AD32 AF28 AF29 AT27 AV25 H50

2

1

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/09/25 2006/09/25

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

CRESTLINE((6/6)-PWR/GND

LA3262P_DIS__M64

1

1A

of

12 57Tuesday, August 21, 2007

5

DDR_A_DQS#[0..7]<8>

DDR_A_D[0..63]<8>

DDR_A_DM[0..7]<8>

DDR_A_DQS[0..7]<8>

DDR_A_MA[0..14]<7,8>

D D

Layout Note: Place near JP34

+1.8V

2.2U_0805_16V4Z

2.2U_0805_16V4Z C473

C473

1

2

0.1U_0402_16V4Z

1

2

C250

56_0404_4P2R_5%

2.2U_0805_16V4Z C491

C491

1

2

0.1U_0402_16V4Z

1

2

C257

C272

+0.9V

RP22 56_0404_4P2R_5%RP22 56_0404_4P2R_5%

RP26 56_0404_4P2R_5%RP26 56_0404_4P2R_5%

RP25 56_0404_4P2R_5%RP25 56_0404_4P2R_5%

RP28 56_0404_4P2R_5%RP28 56_0404_4P2R_5%

RP30 56_0404_4P2R_5%RP30 56_0404_4P2R_5%

RP34 56_0404_4P2R_5%RP34 56_0404_4P2R_5%

RP24 56_0404_4P2R_5%RP24 56_0404_4P2R_5%

2.2U_0805_16V4Z

1

2

0.1U_0402_16V4Z

1

2

C279

14 23

0.1U_0402_16V4Z

0.1U_0402_16V4Z C255

C255

C465

1

2

0.1U_0402_16V4Z

1

2

C281

DDR_A_BS#2 DDR_CKE0_DIMMA

DDR_A_MA7 DDR_A_MA6

DDR_A_MA9 DDR_A_MA12

DDR_A_MA4 DDR_A_MA2

DDR_A_MA0 DDR_A_BS#1

M_ODT0 DDR_A_MA13

DDR_CKE1_DIMMA DDR_A_MA14

1

2

0.1U_0402_16V4Z

C274

1

2

0.1U_0402_16V4Z

2.2U_0805_16V4Z

C C

B B

A A

Layout Note: Place one cap close to every 2 pullup resistors terminated to +0.9VS

+0.9V

0.1U_0402_16V4Z

DDR_A_MA5 DDR_A_MA8

DDR_A_MA1 DDR_A_MA3

DDR_A_RAS# DDR_CS0_DIMMA#

DDR_A_BS#0 DDR_A_MA10

DDR_A_CAS# DDR_A_WE#

DDR_CS1_DIMMA# M_ODT1

DDR_A_MA11

C458

1

2

1

2

C229

1

2

0.1U_0402_16V4Z

1

2

C239

RP27

RP29

RP32

RP31

RP33

RP35

R1903 56_0402_5%

5

C498

0.1U_0402_16V4Z

1 4 2 3

2 3 1 4

1 2

C242

1

2

C268

0.1U_0402_16V4Z

0.1U_0402_16V4Z C280

C280

1

2

0.1U_0402_16V4Z

1

2

C252

4

0.1U_0402_16V4Z

0.1U_0402_16V4Z C235

C235

1

2

0.1U_0402_16V4Z

1

2

C241

C234

Layout Note: Place these resistor closely JP34,all trace length Max=1.5"

4

3

+1.8V

JP34

1

VREF

3

DDR_A_D4 DDR_A_D1

DDR_A_DQS#0 DDR_A_DQS0

DDR_A_D2 DDR_A_D3

DDR_A_D8 DDR_A_D14

DDR_A_DQS#1 DDR_A_DQS1

DDR_A_D9 DDR_A_D11 DDR_A_D15 DDR_A_D10

DDR_A_D16 DDR_A_D17

DDR_A_DQS#2 DDR_A_DQS2

DDR_A_D18 DDR_A_D19

DDR_A_DM3

DDR_A_D26 DDR_A_D27

DDR_CKE0_DIMMA<7>

DDR_A_BS2<8>

DDR_A_BS0<8>

DDR_A_WE#<8>

DDR_A_CAS#<8>

0.1U_0402_16V4Z

1

2

C227

DDR_CS1_DIMMA#<7>

M_ODT1<7>

ICH_SMBDATA<14,15,26>

ICH_SMBCLK<14,15,26>

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

DDR_CKE0_DIMMA

DDR_A_BS#2 DDR_A_MA12

DDR_A_MA9 DDR_A_MA7 DDR_A_MA8

DDR_A_MA5 DDR_A_MA3 DDR_A_MA1

DDR_A_MA10 DDR_A_BS#0 DDR_A_WE#

DDR_A_CAS# DDR_CS1_DIMMA#

M_ODT1 DDR_A_D37

DDR_A_D36 DDR_A_DQS#4

DDR_A_DQS4 DDR_A_D35

DDR_A_D32 DDR_A_D40

DDR_A_D44 DDR_A_DM5 DDR_A_D41

DDR_A_D46 DDR_A_D49

DDR_A_D48

DDR_A_DQS#6 DDR_A_DQS6

DDR_A_D50 DDR_A_D61 DDR_A_D57

DDR_A_D60 DDR_A_DM7 DDR_A_D59

DDR_A_D58 ICH_SMBDATA

ICH_SMBCLK

+3VM

1

2

2.2U_0603_6.3V4Z

2006/09/25 2006/09/25

C311

C308

1

2

Compal Secret Data

5

7

9

11 13 15 17 19 21 23 25 27 29 31 33 35 37 39

41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97

99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 203

0.1U_0402_16V4Z

Deciphered Date

VSS DQ0 DQ1 VSS DQS0# DQS0 VSS DQ2 DQ3 VSS DQ8 DQ9 VSS DQS1# DQS1 VSS DQ10 DQ11 VSS

VSS DQ16 DQ17 VSS DQS2# DQS2 VSS DQ18 DQ19 VSS DQ24 DQ25 VSS DM3 NC VSS DQ26 DQ27 VSS CKE0 VDD NC BA2 VDD A12 A9 A8 VDD A5 A3 A1 VDD A10/AP BA0 WE# VDD CAS# NC/S1# VDD NC/ODT1 VSS DQ32 DQ33 VSS DQS4# DQS4 VSS DQ34 DQ35 VSS DQ40 DQ41 VSS DM5 VSS DQ42 DQ43 VSS DQ48 DQ49 VSS NC,TEST VSS DQS6# DQS6 VSS DQ50 DQ51 VSS DQ56 DQ57 VSS DM7 VSS DQ58 DQ59 VSS SDA SCL VDDSPD GND

FOX_ASOA426-M4R-TRconn@

SO-DIMM A

REVERSE

Top side

VSS DQ4 DQ5 VSS DM0 VSS DQ6 DQ7

VSS DQ12 DQ13

VSS

DM1

VSS

CK0

CK0#

VSS DQ14 DQ15

VSS

VSS DQ20 DQ21

VSS

DM2

VSS DQ22 DQ23

VSS DQ28 DQ29

VSS

DQS3#

DQS3

VSS DQ30 DQ31

VSS

NC/CKE1

VDD

NC/A15 NC/A14

VDD

BA1

RAS#

VDD ODT0

NC/A13

VDD

VSS DQ36 DQ37

VSS

DM4

VSS DQ38 DQ39

VSS DQ44 DQ45

VSS

DQS5#

DQS5

VSS DQ46 DQ47

VSS DQ52 DQ53

VSS

CK1

CK1#

VSS

DM6

VSS DQ54 DQ55

VSS DQ60 DQ61

VSS

DQS7#

DQS7

VSS DQ62 DQ63

VSS

SAO

SA1

GND

2

+1.8V

V_DDR_MCH_REF

2

DDR_A_D6

4

DDR_A_D0

6 8

DDR_A_DM0

10 12

DDR_A_D5

14

DDR_A_D7

16 18

DDR_A_D13

20

DDR_A_D12

22 24

DDR_A_DM1

26 28

M_CLK_DDR0

30

M_CLK_DDR#0

32 34 36 38 40

42

DDR_A_D20

44

DDR_A_D21

46 48 50

NC

A11

A7 A6

A4 A2 A0

S0#

NC

2

52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 204

DDR_A_DM2 DDR_A_D23

DDR_A_D22 DDR_A_D28DDR_A_D29

DDR_A_D25DDR_A_D24 DDR_A_DQS#3

DDR_A_DQS3 DDR_A_D31

DDR_A_D30 DDR_CKE1_DIMMA

DDR_A_MA14 DDR_A_MA11 DDR_A_MA6 DDR_A_MA4

DDR_A_MA2 DDR_A_MA0

DDR_A_BS#1 DDR_A_RAS# DDR_CS0_DIMMA#

M_ODT0 DDR_A_MA13

DDR_A_D39 DDR_A_D38

DDR_A_DM4 DDR_A_D34

DDR_A_D33 DDR_A_D45

DDR_A_D43 DDR_A_DQS#5

DDR_A_DQS5 DDR_A_D47

DDR_A_D42 DDR_A_D52

DDR_A_D53 M_CLK_DDR1

M_CLK_DDR#1 DDR_A_DM6 DDR_A_D51DDR_A_D54

DDR_A_D55

DDR_A_D56 DDR_A_DQS#7

DDR_A_DQS7 DDR_A_D62

DDR_A_D63

12

R455

R453

10K_0402_5%

12

2.2U_0805_16V4Z

2.2U_0805_16V4Z C363

C363

1

2

M_CLK_DDR0 <7> M_CLK_DDR#0 <7>

PM_EXTTS#0 <7>

DDR_CKE1_DIMMA <7>

DDR_A_BS1 <8> DDR_A_RAS# <8> DDR_CS0_DIMMA# <7>

M_ODT0 <7>

M_CLK_DDR1 <7> M_CLK_DDR#1 <7>

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

Date: Sheet of

Compal Electronics, Inc.

DDRII-SODIMM SLOT1

LA3262P_DIS__M64

1

C362

1

V_DDR_MCH_REF <7,14,48>

of

13 57Tuesday, August 21, 2007

1A

0.1U_0402_16V4Z

1

2

5

DDR_B_DQS#[0..7]<8>

DDR_B_D[0..63]<8> DDR_B_DM[0..7]<8>

DDR_B_DQS[0..7]<8>

DDR_B_MA[0..14]<7,8>

D D

C C

B B

A A

Layout Note: Place near JP10

+1.8V

2.2U_0805_16V4Z

2.2U_0805_16V4Z C236

C236

1

2

Layout Note: Place one cap close to every 2 pullup resistors terminated to +0.9VS

+0.9V

0.1U_0402_16V4Z

1

2

C176

DDR_B_MA1 DDR_B_MA3

DDR_B_BS#0 DDR_B_MA10

DDR_B_MA0 DDR_B_BS#1

DDR_B_RAS# DDR_CS2_DIMMB#

DDR_B_CAS# DDR_B_WE#

DDR_CS3_DIMMB# M_ODT2 M_ODT3

DDR_CKE3_DIMMB

0.1U_0402_16V4Z

C265

1

2

0.1U_0402_16V4Z

1

2

C179

RP14

1 4 2 3

RP17

56_0404_4P2R_5%

1 4 2 3

RP16

56_0404_4P2R_5%

1 4 2 3

RP18

56_0404_4P2R_5%

1 4 2 3

RP19

56_0404_4P2R_5%

1 4 2 3

RP23

56_0404_4P2R_5%

2 3 1 4

56_0404_4P2R_5%

1 2

R1743

56_0402_5%

5

2.2U_0805_16V4Z

2.2U_0805_16V4Z C247

C247

1

2

0.1U_0402_16V4Z

1

2

C186

C159

1

2

0.1U_0402_16V4Z

1

2

C213

C197

+0.9V

RP10 56_0404_4P2R_5%RP10 56_0404_4P2R_5%

RP11 56_0404_4P2R_5%RP11 56_0404_4P2R_5%

RP12 56_0404_4P2R_5%RP12 56_0404_4P2R_5%

RP13 56_0404_4P2R_5%RP13 56_0404_4P2R_5%

RP15 56_0404_4P2R_5%RP15 56_0404_4P2R_5%

RP21 56_0404_4P2R_5%RP21 56_0404_4P2R_5%

RP9

56_0404_4P2R_5%

2.2U_0805_16V4Z C164

C164

1

2

0.1U_0402_16V4Z

1

2

C220

14 23

0.1U_0402_16V4Z

0.1U_0402_16V4Z C166

C166

1

2

0.1U_0402_16V4Z

1

2

C183

C210

DDR_B_MA9 DDR_B_MA12

DDR_B_MA14 DDR_B_MA11

DDR_B_MA5 DDR_B_MA8

DDR_B_MA7 DDR_B_MA6

DDR_B_MA4 DDR_B_MA2

DDR_B_MA13

DDR_B_BS#2 DDR_CKE2_DIMMB

0.1U_0402_16V4Z

C219

1

2

0.1U_0402_16V4Z

1

2

C199

0.1U_0402_16V4Z

C188

1

2

0.1U_0402_16V4Z

1

2

C173

Layout Note: Place these resistor closely JP10,all trace length Max=1.5"

C218

4

C161

0.1U_0402_16V4Z

1

2

C177

C163

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

+1.8V

JP10

1

VREF

3

11 13 15 17 19 21 23 25 27 29 31 33 35 37 39

41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97

99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 203

conn@

0.1U_0402_16V4Z

Deciphered Date

5 7 9

VSS DQ0 DQ1 VSS DQS0# DQS0 VSS DQ2 DQ3 VSS DQ8 DQ9 VSS DQS1# DQS1 VSS DQ10 DQ11 VSS

VSS DQ16 DQ17 VSS DQS2# DQS2 VSS DQ18 DQ19 VSS DQ24 DQ25 VSS DM3 NC VSS DQ26 DQ27 VSS CKE0 VDD NC BA2 VDD A12 A9 A8 VDD A5 A3 A1 VDD A10/AP BA0 WE# VDD CAS# NC/S1# VDD NC/ODT1 VSS DQ32 DQ33 VSS DQS4# DQS4 VSS DQ34 DQ35 VSS DQ40 DQ41 VSS DM5 VSS DQ42 DQ43 VSS DQ48 DQ49 VSS NC,TEST VSS DQS6# DQS6 VSS DQ50 DQ51 VSS DQ56 DQ57 VSS DM7 VSS DQ58 DQ59 VSS SDA SCL VDDSPD GND

FOX_ASOA426-M4R-TR

SO-DIMM B STANDARD

Bottom side

DDR_B_D0 DDR_B_D1

DDR_B_DQS#0 DDR_B_DQS0

DDR_B_D2 DDR_B_D3

DDR_B_D8 DDR_B_D9

DDR_B_DQS#1 DDR_B_DQS1

DDR_B_D10 DDR_B_D11

DDR_B_D20 DDR_B_DQS#2

DDR_B_DQS2 DDR_B_D18

DDR_B_D19 DDR_B_D28

DDR_B_DM3

DDR_B_D30 DDR_B_D31

DDR_CKE2_DIMMB<7>

DDR_B_BS2<8>

DDR_B_BS0<8> DDR_B_WE#<8>

DDR_B_CAS#<8>

DDR_CS3_DIMMB#<7>

M_ODT3<7>

ICH_SMBDATA<13,15,26>

ICH_SMBCLK<13,15,26>

+3VM

3

DDR_CKE2_DIMMB

DDR_B_BS#2 DDR_B_MA12

DDR_B_MA9 DDR_B_MA8

DDR_B_MA5 DDR_B_MA3 DDR_B_MA1

DDR_B_MA10 DDR_B_BS#0 DDR_B_WE#

DDR_B_CAS# DDR_CS3_DIMMB#

M_ODT3 DDR_B_D32

DDR_B_D33 DDR_B_DQS#4

DDR_B_DQS4 DDR_B_D34

DDR_B_D35 DDR_B_D40

DDR_B_D41 DDR_B_DM5 DDR_B_D42

DDR_B_D43 DDR_B_D48

DDR_B_D49

DDR_B_DQS#6 DDR_B_DQS6

DDR_B_D51 DDR_B_D50

DDR_B_D56 DDR_B_D61 DDR_B_D57

DDR_B_DM7 DDR_B_D59

DDR_B_D58 ICH_SMBDATA

ICH_SMBCLK

1

C312

2

2.2U_0603_6.3V4Z

2006/09/25 2006/09/25

1

C301

2

Compal Secret Data

DQ12 DQ13

CK0#

DQ14 DQ15

DQ20 DQ21

DQ22 DQ23

DQ28 DQ29

DQS3#

DQS3 DQ30

DQ31

NC/CKE1

NC/A15 NC/A14

RAS#

ODT0

NC/A13

DQ36 DQ37

DQ38 DQ39

DQ44 DQ45

DQS5#

DQS5 DQ46

DQ47 DQ52

DQ53

CK1#

DQ54 DQ55

DQ60 DQ61

DQS7#

DQS7 DQ62

DQ63

GND

VSS DQ4 DQ5 VSS DM0 VSS DQ6 DQ7 VSS

VSS DM1 VSS CK0

VSS

VSS DM2

VSS

VSS VDD

VDD

VDD VSS

VSS DM4 VSS

VSS

VSS CK1

VSS DM6 VSS

VSS

VSS SAO

2

+1.8V

V_DDR_MCH_REF

2

DDR_B_D5

4

DDR_B_D4

6 8

DDR_B_DM0

10 12

DDR_B_D6

14

DDR_B_D7

16 18

DDR_B_D12

20

DDR_B_D13

22 24

DDR_B_DM1

26 28

M_CLK_DDR3

30

M_CLK_DDR#3

32 34

DDR_B_D14

36

DDR_B_D15

38 40

42

DDR_B_D21DDR_B_D17

44

DDR_B_D16

46 48 50

NC

A11

A7 A6

A4 A2

A0 BA1 S0#

NC

SA1

2

DDR_B_DM2

52 54

DDR_B_D22

56

DDR_B_D23

58 60

DDR_B_D26

62

DDR_B_D24DDR_B_D25

64 66

DDR_B_DQS#3

68

DDR_B_DQS3

70 72

DDR_B_D29

74

DDR_B_D27

76 78

DDR_CKE3_DIMMB

80 82 84

DDR_B_MA14

86 88

DDR_B_MA11

90

DDR_B_MA7

92

DDR_B_MA6

94 96

DDR_B_MA4

98

DDR_B_MA2

100

DDR_B_MA0

102 104

DDR_B_BS#1

106

DDR_B_RAS#

108

DDR_CS2_DIMMB#

110 112

M_ODT2

114

DDR_B_MA13

116 118 120 122

DDR_B_D36

124

DDR_B_D37

126 128

DDR_B_DM4

130 132

DDR_B_D39

134

DDR_B_D38

136 138

DDR_B_D44

140

DDR_B_D45

142 144

DDR_B_DQS#5

146

DDR_B_DQS5

148 150

DDR_B_D46

152

DDR_B_D47

154 156

DDR_B_D52

158

DDR_B_D53

160 162

M_CLK_DDR2

164

M_CLK_DDR#2

166 168

DDR_B_DM6

170 172

DDR_B_D54

174

DDR_B_D55

176 178

DDR_B_D60

180 182 184

DDR_B_DQS#7

186

DDR_B_DQS7

188 190

DDR_B_D62

192

DDR_B_D63

194 196 198 200 204

R257

1 2

10K_0402_5%

12

10K_0402_5%

R254

Title

Size Document Number Rev

Date: Sheet

Date: Sheet of

0.1U_0402_16V4Z

2.2U_0805_16V4Z

M_CLK_DDR3 <7> M_CLK_DDR#3 <7>

PM_EXTTS#1 <7>

DDR_CKE3_DIMMB <7>

DDR_B_BS1 <8> DDR_B_RAS# <8> DDR_CS2_DIMMB# <7>

M_ODT2 <7>

M_CLK_DDR2 <7> M_CLK_DDR#2 <7>

1

C89

2

+3VM

Compal Electronics, Inc.

DDRII-SODIMM SLOT2

LA3262P_DIS__M64

1

V_DDR_MCH_REF <7,13,48>

C90

1

1A

14 57Tuesday, August 21, 2007

1A

of

5

PCI

SRC

CPU

CLKSEL1

1

FSLA

CLKSEL0

MHz

200

166

MHz

1000

100

MHz

33.30

33.3

+3VM

1 2

R1066 0_1206_5%

FSLC1FSLB

CLKSEL2

0

FSB Frequency Selet:

D D

CPU Driven

(Default)

*

Stuff

No Stuff

Stuff

667MHz

No Stuff

Stuff

800MHz

CPU_BSEL0<5>

C C

CPU_BSEL1<5>

B B

CPU_BSEL2<5>

A A

18P_0402_50V8J

FSC

14.31818MHZ_16P

2

C509

1

No Stuff

2.2K_0402_5%

FSA

0_0402_5%

10K_0402_5%

0_0402_5%

Y6

R1078

0_0402_5%

1 2

R1107

R1130

1 2

R1135

Routing the trace at least 10mil

R1107 R1135 R1083

R1074 R1086 R1098 R1113 R1139

R1139 R1135R1135 R1139

R1083

R1107 R1098

R1113

R1074R1086

R1128

R1135 R1139

R1083

R1086

R1098

R1128

R1113

+VCCP

MCH_CLKSEL0 <7>

MCH_CLKSEL1 <7>

MCH_CLKSEL2 <7>

For ITP_EN, 0 =SRC8/SRC8#; 1 = ITP/ITP# For 27_SEL, 0 = Enable DOT96 & SRC1,

1 2

R1083

FSB

12

+VCCP

R1074

@

1 2

R1079

1K_0402_5%

12

R1086

R1086 1K_0402_5%@

1K_0402_5%@

R1098

R1098 1K_0402_5%@

1K_0402_5%@

1 2

R1105

1K_0402_5%

12

R1113

@R1113

@

0_0402_5%

R1128

R1128 1K_0402_5%@

1K_0402_5%@

1 2

R1131

1K_0402_5%

12

R1139

@R1139

@

0_0402_5%

R1107

R1074

56_0402_5%

For PCI2_TME, 0 = Overclocking of CPU and SRC Allowed

CLK_XTAL_OUT

CLK_XTAL_IN

12

2

C505

C505 18P_0402_50V8J

18P_0402_50V8J

1

5

+3VS +3VS +3VS

@

1 2

ITP_EN 27_SEL

1 2

R1128

1111 Add CLRP4,CLRP5 for 667/800 FSB select SHORT CLRP5, NO SHORT CLRP4 -- FSB 800 SHORT CLRP4, NO SHORT CLRP5 -- FSB 667

CLKSATAREQ#<26>

CLK_DEBUG_PORT<31,36>

CLK_PCI_SIO<35> CLK_PCI_TCG<36> CLK_PCI_EC<37>

CLK_PCI_PCM<31>

CLK_PCI_ICH<24>

CLK_48M_ICH<26>

CLK_14M_ICH<26> CLK_14M_SIO<35> CLK_14M_KBC<37>

1= Enable SRC0 & 27MHz

1 = Overclocking of CPU and SRC NOT allowed

R1245

R1245 10K_0402_5%

10K_0402_5%

R1247

R1247 10K_0402_5%

10K_0402_5%

+3VM_CK505

CLKREQ#_B<7>

1 2

1

2

R1690

R1690 10K_0402_5%

10K_0402_5%

R1691

@ R1691

@

10K_0402_5%

4

C1165

C1165 10U_0603_6.3V6M

10U_0603_6.3V6M

R1077 33_0402_5%

1 2

4

1

C1166

0.1U_0402_16V4Z

2

R1068 0_1206_5%R1068 0_1206_5%

1 2

+1.25VM

C1172 10U_0603_6.3V6M

10U_0603_6.3V6M

+1.25VM_CK505

R1692475_0402_1%

1 2 1 2

R1693 475_0402_1%

1 2 1 2 1 2

1 2

PCI2_TME

1 2

1 2 1 2 1 2

1 2

R1108

R1108 10K_0402_5%

10K_0402_5%

R1246

R1246 10K_0402_5%

10K_0402_5%

@

R109722_0402_5%

12

R111412_0402_5%

12

R114012_0402_5%

R114012_0402_5% R111012_0402_5%

R111012_0402_5% R114112_0402_5%

R114112_0402_5% R111722_0402_5%

R111722_0402_5%

R108733_0402_1%

R108733_0402_1% R108833_0402_1%

R108833_0402_1% R108933_0402_1%

R108933_0402_1%

+1.25VM_CK505

1

C1167

0.1U_0402_16V4Z

2

1

C1173

C1172 2

+3VM_CK505

PCI_CLK1 PCI2_TME PCI_CLK3 27_SEL ITP_EN

CLK_XTAL_IN CLK_XTAL_OUT

FSA

FSB

FSC

3

1

C1168

0.1U_0402_16V4Z

2

Place close to U7

0.1U_0402_16V4Z

16 61

39 55

12 20 26

36 49

60 59

10

57

62

45

42

11 15 19 52 23 29 58

1

C1174

2

0.1U_0402_16V4Z

U7

2

VDD_PCI

9

VDD48 VDDPLL3 VDDREF

VDDSRC VDDCPU

VDD96_IO VDDPLL3_IO VDDSRC_IO

VDDSRC_IO VDDCPU_IO

1

PCI0/CR#_A

3

PCI1/CR#_B

4

PCI2/TME

5

PCI3

6

PCI4/27_Select

7

PCIF5/ITP_EN

X1 X2

USB_48MHZ/FSLA

FSLB/TEST MODE

REF0/FSLC/TEST_SEL

VDDSRC_IO

GNDSRC

8

GNDPCI GND48 GND GND GNDCPU GNDSRC GNDSRC GNDREF

* Internal Pull-Up Resistor

* Internal Pull-Up Resistor ** Internal Pull-Down Resistor

** Internal Pull-Down Resistor

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

1

C1169

0.1U_0402_16V4Z

2

10U_0603_6.3V6M

1

C1353

2

0.1U_0402_16V4Z

SRC1/SE1/27MHz_NonSS

SRC1#/SE2/27MHz_SS

CK_PWRGD/PD#

ICS9LPRS355AKLFT_TSSOP64

2006/09/25 2006/09/25

0.1U_0402_16V4Z

1

C1354

2

SCLK

SDATA

PCI_STOP#

CPU_STOP#

CPU0

CPU0#

CPU1_F

CPU1#_F

SRC8/ITP

SRC8#/ITP#

SRC10#

SRC10

SRC11/CR#_H

SRC11#/CR#_G

SRC9

SRC9#

SRC7/CR#_F

SRC7#/CR#_E

SRC6

SRC6#

SRC4

SRC4#

SRC3/CR#_C

SRC3#/CR#_D

SRC2/SATA

SRC2#/SATA#

SRC0/DOT96

SRC0/DOT96#

1

C1170

0.1U_0402_16V4Z

2

+1.25VM_CK505

1

C1355

2

48

NC

64 63

38 37

54 53

51 50

47 46

35 34

33 32

30 31

44 43

41 40

27 28

24 25

21 22

17 18

13 14

56

Compal Secret Data

1

C1171

0.1U_0402_16V4Z

2

R1033 0_0402_5%@ R1033 0_0402_5%@

R_CPU_XDP

R1447

R_CPU_XDP#

R1448

R1448 R1143

@R1143

@

R1695

CLKREQ#_H R_CLKREQ#_G

R_CLKREQ#_F CLKREQ#_F R_CLKREQ#_E CLKREQ#_E

R_27MHz R_27MSSC

R1694

R1686 0_0402_5%

R1686 0_0402_5% R1687 0_0402_5%R1687 0_0402_5%

Deciphered Date

2

1 2 1 2 1 2 1 2

R1900 475_0402_1%

R1901 475_0402_1%@R1901 475_0402_1%@

1 2 1 2

12 12

0_0402_5%

0_0402_5% 0_0402_5%

0_0402_5%

1 2

R149 10K_0402_5%

R149 10K_0402_5% 475_0402_1%

475_0402_1% 475_0402_1%

475_0402_1% R150 10K_0402_5%

R150 10K_0402_5%

1 2

11/20 For EMI request to install R1687

2

1

C353

C353 C357

C357 C372

C372 C373

C373 C374

C374 C375

C375 C376

C376 C378

C378 C379

C379 C380

C380

ICH_SMBCLK <13,14,26> ICH_SMBDATA <13,14,26>

H_STP_PCI# <26> H_STP_CPU# <26>

CLK_CPU_BCLK <4> CLK_CPU_BCLK# <4>

CLK_MCH_BCLK <7> CLK_MCH_BCLK# <7>

CLK_CPU_XDP <4> CLK_PCIE_Rob <31> CLK_PCIE_Rob# <31> CLK_CPU_XDP# <4>

CLK_PCIE_DOCK# <39> CLK_PCIE_DOCK <39>

+3VS

CPPE# <39>

CLKREQ#_G <31>

+3VS

CLK_PCIE_MCARD <31> CLK_PCIE_MCARD# <31>

1 2

R1899 10K_0402_5%

R1902 10K_0402_5%@R1902 10K_0402_5%@

1 2

CLK_PCIE_VGA <18> CLK_PCIE_VGA# <18>

CLK_MCH_3GPLL <7> CLK_MCH_3GPLL# <7>

CLK_PCIE_ICH <26>

CLK_PCIE_ICH# <26>

CLK_PCIE_SATA <25> CLK_PCIE_SATA# <25>

27M_CLK <19> 27M_SSC <19>

CK_PWRGD <26>

+3VS

Title

Size Document Number Rev

Date: Sheet

CLK_48M_ICH

12

5P_0402_50V8C

CLK_14M_ICH

12

4.7P_0402_50V8C

CLK_PCI_ICH

12

4.7P_0402_50V8C

CLK_14M_KBC

12

4.7P_0402_50V8C

CLK_14M_SIO

12

4.7P_0402_50V8C

CLK_PCI_EC

12

4.7P_0402_50V8C

CLK_PCI_TCG

12

4.7P_0402_50V8C

CLK_PCI_PCM

12

4.7P_0402_50V8C

CLK_PCI_SIO

12

4.7P_0402_50V8C

CLK_DEBUG_PORT

12

5P_0402_50V8C

CLKREQ#_F CLKREQ#_E <19,31>

Compal Electronics, Inc.

Clock generator

LA3262P_DIS__M64

15 57Tuesday, August 21, 2007

1

1A

of

A

CRT Connector

1 1

+5VS

0.1U_0402_16V4Z

2 2

1

C359

2

M_HSYNC<19>

M_VSYNC<19>

SN74AHCT1G125GW_SOT353-5

1

5

U33

U33 SN74AHCT1G125GW_SOT353-5

SN74AHCT1G125GW_SOT353-5

P

OE#

A2Y

G

3

L_BLUE<39>

L_GREEN<39>

L_RED<39>

0315 add

+5VS

HSYNC_G_A

4

1

5

P

VSYNC_G_A

4

OE#

A2Y

G

U54

@

3

C323

18P_0402_50V8J

150_0402_1%

@

R545

1 2

0_0603_5%

R546

1 2

0_0603_5%

1

C322

2

@

18P_0402_50V8J

Place close to docking connector

layout note: D_HSYNC & D_VSYNC should be routed to docking connector then to VGA connector

B

12

@

R174

150_0402_1%

R173

@R173

@

12

R171

2007,0125 change

D_VSYNC

150_0402_1%

D_HSYNC

C

+CRTVDD+RCRT_VCC+5VS

F1

1.1A_6VDC_FUSE

2007,0125 change

R542 BK1608LL560-T_0603 R542 BK1608LL560-T_0603

1 2

R543 BK1608LL560-T_0603 R543 BK1608LL560-T_0603

1 2

C314

39P_0402_50V8C

1

2

D_HSYNC <39>

D_VSYNC <39>

R544 BK1608LL560-T_0603 R544 BK1608LL560-T_0603

1 2

@

C310

39P_0402_50V8C

1

C317

2

18P_0402_50V8J

0315 add

1

C318

C316

@

2

18P_0402_50V8J

@

D_DDCDATA<39>

D_DDCCLK<39>

C313

39P_0402_50V8C

1

2

RED_R

GREEN_R

BLUE_R

D18

21

2 1

CH491D_SC59

0.1U_0402_16V4Z

C315

2.2K_0402_5%

W=40mils

1

2

6

11

1 7

12

2 8

13

3 9

14

4 10 15

5

SUYIN_070912FR015S207CR

conn@

+CRTVDD +CRTVDD

12

R162

D_DDCDATA

D_DDCCLK

JP2

16 17

12

R183

2.2K_0402_5%

D

BLUE_R GREEN_R RED_R

2

G

Q46

1 3

D

S

D

S

RHU002N06_SOT323

1 3

D

Q52

RHU002N06_SOT323

E

1

D4

DAN217_SC59

@

2

3

2

+3VS

1 2

2.2K_0402_5%

R1921 2.2K_0402_5%R1921 2.2K_0402_5%

2

G

S

1

R1922

3

D20

D19

DAN217_SC59

@

2

Place close to JP2

DAN217_SC59@

+CRTVDD

3

Place close to docking connector

DDC1_DATA <19>

DDC1_CLK <19>

TV-Out Connector

0_0603_5%

LUMA<19,39> CRMA<19,39>

COMP<19,39>

12

R185

@R185

@

12

R187

@R187

@

1

2

5.6P_0402_50V8D

C333

150_0402_1%

1

@

2

C355

5.6P_0402_50V8D

5.6P_0402_50V8D C354

C354

3 3

0315 add

R184

@R184

@

150_0402_1%

0_0603_5%

R547

1 2

0_0603_5%

R548

1 2

0_0603_5%

R549

1 2

1

@

2

5.6P_0402_50V8D

Place close to JP1

DAN217_SC59

D3

@D3

@

DAN217_SC59

1

2

3

@D5

@

D5

TV_LUMA TV_CRMA TV_COMP

DAN217_SC59

@D1

@

1

2

3

SUYIN_33007SR-07T1-C

+3VS

D1

1

2

3

JP1

1 2 3 4 5 6 7

conn@

Close to JP1

layout note: TV-out signals should be routed to JP30 then to JP1

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2006/09/25 2006/09/25

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

D

Date: Sheet

Compal Electronics, Inc.

CRT & TVout Connector

LA3262P_DIS__M64

16 57Tuesday, August 21, 2007

E

1A

of

5

B+_LCD

0802 (R1A) change for preventing 1206 Cap crack

LVDS CONN

JP35

41

D D

C C

42 43 44 45 46

41 42 43 44 45 46

ACES_88316-4000

conn@

40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

9 8 7 6 5 4 3 2 1

40 39 38 37 36 35 34 33 32 31 30 29 28

BKLT_PWM

27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1

C586 4.7U_0805_25V6K C586 4.7U_0805_25V6K

1 2 1 2

C587 68P_0402_50V8JC587 68P_0402_50V8J

1 2

C1629 4.7U_0805_25V6KC1629 4.7U_0805_25V6K

L62 KC FBM-L11-201209-221LMA30T_1210L62 KC FBM-L11-201209-221LMA30T_1210

+3VS

LCDVDD

+5VS_INV

TXCLK_U+ <19> TXCLK_U- <19>

TXOUT_U2+ <19> TXOUT_U2- <19>

TXOUT_U1+ <19> TXOUT_U1- <19>

TXOUT_U0+ <19> TXOUT_U0- <19>

TXOUT_L0- <19> TXOUT_L0+ <19>

TXOUT_L1- <19> TXOUT_L1+ <19>

TXOUT_L2- <19> TXOUT_L2+ <19>

TXCLK_L- <19> TXCLK_L+ <19>

4

12

ALS_EN <26>

DDC2_CLK <19> DDC2_DATA <19>

3

LCD POWER CIRCUIT

LCDVDD

12

R19

100_0402_1%

B+

RHU002N06_SOT323

VGA_ENAVDD<19>

100K_0402_1%

+3VALW

+3VS

LID_SW#<26,38> OPT_BL_ENA<19>

Q5

R502

13

D

2

G

S

13

Q6

Q6 DTC124EK_SC59

0_0402_5%

1 2

0_0402_5%@

1 2

LID_SW#

DTC124EK_SC59

2

1 2

R1728

R1729

R474

1 2

47K_0402_5%

+3V_U43

1

A

2

B

R501

1 2

100K_0402_1%

14

P

G

7

2

1

C29

2

0.1U_0402_16V4Z

+5VS

47K

U43A

U43A SN74LVC08APW_TSSOP14

SN74LVC08APW_TSSOP14

3

O

100K_0402_5%

R360

2

1 2

Q8

AO3413_SOT23

D

1 3

G

2

E_STAR

1

C31

2

4.7U_0805_10V4Z

Q53

Q53 DTA114YKA_SC59

DTA114YKA_SC59

10K

2

13

D

Q36

Q36 BSS138_SOT23

BSS138_SOT23

G

S

0.1U_0402_16V7K

E_STAR <41>

13

R12

1 2

1M_0402_5%

C28

1 2

+5VS_INV

1

+3VALWLCDVDD

1

C20

4.7U_0805_10V4Z@

2

B B

BLON_PWM<19>

R102 0_0402_5%R102 0_0402_5%

1 2

BKLT_PWM

Support 3V inverter

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/09/25 2006/09/25

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

LCD CONN.

LA3262P_DIS__M64

17 57Tuesday, August 21, 2007

1

1A

of

5

4

3

2

1

D D

PEG_M_TXP0 PEG_M_TXN0

PEG_M_TXP1 PEG_M_TXN1

PEG_M_TXP2 PEG_M_TXN2

PEG_M_TXP3 PEG_M_TXN3

PEG_M_TXP4 PEG_M_TXN4

PEG_M_TXP5 PEG_M_TXN5

PEG_M_TXP6

VGA_RST#<24>

PEG_M_TXN6

PEG_M_TXP7 PEG_M_TXN7

PEG_M_TXP8 PEG_M_TXN8

PEG_M_TXP9 PEG_M_TXN9

PEG_M_TXP10 PEG_M_TXN10

PEG_M_TXP11 PEG_M_TXN11

PEG_M_TXP12 PEG_M_TXN12

PEG_M_TXP13 PEG_M_TXN13

PEG_M_TXP14 PEG_M_TXN14

PEG_M_TXP15 PEG_M_TXN15

CLK_PCIE_VGA CLK_PCIE_VGA#

C C

B B

U80A

AC30

PCIE_RX0P

AC31

PCIE_RX0N

AC29

PCIE_RX1P

AB29

PCIE_RX1N

AB31

PCIE_RX2P

AB30

PCIE_RX2N

AA31

PCIE_RX3P

AA30

PCIE_RX3N

W30

PCIE_RX4P

W31

PCIE_RX4N

W29

PCIE_RX5P

V29

PCIE_RX5N

V31

PCIE_RX6P

V30

PCIE_RX6N

U31

PCIE_RX7P

U30

PCIE_RX7N

P30

PCIE_RX8P

P31

PCIE_RX8N

P29

PCIE_RX9P

N29

PCIE_RX9N

N31

PCIE_RX10P

N30

PCIE_RX10N

M31

PCIE_RX11P

M30

PCIE_RX11N

K30

PCIE_RX12P

K31

PCIE_RX12N

K29

PCIE_RX13P

J29

PCIE_RX13N

J31

PCIE_RX14P

J30

PCIE_RX14N

H31

PCIE_RX15P

H30

PCIE_RX15N

Clock

AD29

PCIE_REFCLKP

AD30

PCIE_REFCLKN

AC28

RSVD

AC27

RSVD

AG25

PERSTB

216PTAKA13FG M62-S_BGA632

PART 1 OF 6

P

P C

C I

I

-

E

E X

X P

P R

R E

E S

S S

S

I

I N

N T

T E

E R

R F

F A

A C

C E

E

PCIE_TX0P PCIE_TX0N

PCIE_TX1P PCIE_TX1N

PCIE_TX2P PCIE_TX2N

PCIE_TX3P PCIE_TX3N

PCIE_TX4P PCIE_TX4N

PCIE_TX5P PCIE_TX5N

PCIE_TX6P PCIE_TX6N

PCIE_TX7P PCIE_TX7N

PCIE_TX8P PCIE_TX8N

PCIE_TX9P PCIE_TX9N

PCIE_TX10P PCIE_TX10N

PCIE_TX11P PCIE_TX11N

PCIE_TX12P PCIE_TX12N

PCIE_TX13P PCIE_TX13N

PCIE_TX14P PCIE_TX14N

PCIE_TX15P PCIE_TX15N

Calibration

PCIE_CALRN PCIE_CALRP

PCIE_CALI

PEG_M_RXP0

AA28

PEG_M_RXN0

AA27

PEG_M_RXP1

AA25

PEG_M_RXN1

AA24

PEG_M_RXP2

Y28

PEG_M_RXN2

Y27

PEG_M_RXP3

Y25

PEG_M_RXN3

Y24

PEG_M_RXP4

V28

PEG_M_RXN4

V27

PEG_M_RXP5

V25

PEG_M_RXN5

V24

PEG_M_RXP6

T28

PEG_M_RXN6

T27

PEG_M_RXP7

T25

PEG_M_RXN7

T24

PEG_M_RXP8

P28

PEG_M_RXN8

P27

PEG_M_RXP9

P25

PEG_M_RXN9

P24

PEG_M_RXP10

M28

PEG_M_RXN10

M27

PEG_M_RXP11

M25

PEG_M_RXN11

M24

PEG_M_RXP12

L28

PEG_M_RXN12

L27

PEG_M_RXP13

L25

PEG_M_RXN13

L24

PEG_M_RXP14

J28

PEG_M_RXN14

J27

PEG_M_RXP15

G28

PEG_M_RXN15

G27

AF25 AE25 AE23

R1904 2K_0402_1%R1904 2K_0402_1% R1887 562_0402_1%R1887 562_0402_1% R1737

R1737

1 2 1 2 1 2

C1380 0.1U_0402_16V4ZC1380 0.1U_0402_16V4Z C1381 0.1U_0402_16V4ZC1381 0.1U_0402_16V4Z

C1382 0.1U_0402_16V4ZC1382 0.1U_0402_16V4Z C1383 0.1U_0402_16V4ZC1383 0.1U_0402_16V4Z

C1384 0.1U_0402_16V4ZC1384 0.1U_0402_16V4Z C1385 0.1U_0402_16V4ZC1385 0.1U_0402_16V4Z

C1386 0.1U_0402_16V4ZC1386 0.1U_0402_16V4Z C1387 0.1U_0402_16V4ZC1387 0.1U_0402_16V4Z

C1388 0.1U_0402_16V4ZC1388 0.1U_0402_16V4Z C1389 0.1U_0402_16V4ZC1389 0.1U_0402_16V4Z

C1390 0.1U_0402_16V4ZC1390 0.1U_0402_16V4Z C1391 0.1U_0402_16V4ZC1391 0.1U_0402_16V4Z

C1392 0.1U_0402_16V4ZC1392 0.1U_0402_16V4Z C1393 0.1U_0402_16V4ZC1393 0.1U_0402_16V4Z

C1394 0.1U_0402_16V4ZC1394 0.1U_0402_16V4Z C1395 0.1U_0402_16V4ZC1395 0.1U_0402_16V4Z

C1396 0.1U_0402_16V4ZC1396 0.1U_0402_16V4Z C1397 0.1U_0402_16V4ZC1397 0.1U_0402_16V4Z

C1398 0.1U_0402_16V4ZC1398 0.1U_0402_16V4Z C1399 0.1U_0402_16V4ZC1399 0.1U_0402_16V4Z

C1400 0.1U_0402_16V4ZC1400 0.1U_0402_16V4Z C1401 0.1U_0402_16V4ZC1401 0.1U_0402_16V4Z

C1402 0.1U_0402_16V4ZC1402 0.1U_0402_16V4Z C1403 0.1U_0402_16V4ZC1403 0.1U_0402_16V4Z

C1404 0.1U_0402_16V4ZC1404 0.1U_0402_16V4Z C1405 0.1U_0402_16V4ZC1405 0.1U_0402_16V4Z

C1406 0.1U_0402_16V4ZC1406 0.1U_0402_16V4Z C1407 0.1U_0402_16V4ZC1407 0.1U_0402_16V4Z

C1408 0.1U_0402_16V4ZC1408 0.1U_0402_16V4Z C1409 0.1U_0402_16V4ZC1409 0.1U_0402_16V4Z

C1410 0.1U_0402_16V4ZC1410 0.1U_0402_16V4Z C1411 0.1U_0402_16V4ZC1411 0.1U_0402_16V4Z

PCIE_1.2V

1.47K_0402_1%

M62: R1737-->1.47k ohm 1% M72: R1887-->10k ohm 1%

M62: R1887-->562 ohm 1% M72: R1887-->1.27k ohm 1%

PEG_RXP0 PEG_RXN0

PEG_RXP1 PEG_RXN1

PEG_RXP2 PEG_RXN2

PEG_RXP3 PEG_RXN3

PEG_RXP4 PEG_RXN4

PEG_RXP5 PEG_RXN5

PEG_RXP6 PEG_RXN6

PEG_RXP7 PEG_RXN7

PEG_RXP8 PEG_RXN8

PEG_RXP9 PEG_RXN9

PEG_RXP10 PEG_RXN10

PEG_RXP11 PEG_RXN11

PEG_RXP12 PEG_RXN12

PEG_RXP13 PEG_RXN13

PEG_RXP14 PEG_RXN14

PEG_RXP15 PEG_RXN15

CLK_PCIE_VGA<15> CLK_PCIE_VGA#<15>

PEG_RXP[0..15]<9> PEG_RXN[0..15]<9> PEG_M_TXP[0..15]<9> PEG_M_TXN[0..15]<9>

PEG_RXP[0..15] PEG_RXN[0..15] PEG_M_TXP[0..15] PEG_M_TXN[0..15]

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/09/25 2006/09/25

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

M62-S PCIE interface

LA3262P_DIS__M64

18 57Tuesday, August 21, 2007

1

1A

of

5

Close to U80

BLM18PG121SN1D_0603

L93

VGA_VCORE

D D

L93

Close to U80

BLM18PG121SN1D_0603

L87

+2.5VS

C C

PCIE_1.2V

+3VS

B B

Place those components as close as U80 within 500 mils.

A A

L87

170mA, 20mils

12

R1760

R1760 499_0402_1%

499_0402_1%

12

R1769

R1769 499_0402_1%

499_0402_1%

18P_0402_50V8J

10U_0603_6.3V6M

BLM18PG121SN1D_0603

R1797

R1797 C1428

C1428

1U_0402_6.3V4Z

BLM18PG121SN1D_0603

R1891

OPT_BL_ENA<17>

VGA_VREF

1

2

M62S: R1769-->499 ohm 1% M72S: R1769-->249 ohm 1%

XIN XOUT

C1565

@C1565

@

Close to U80 AJ31 and AJ30 pins

1U_0402_6.3V4Z

12

1

C1450

C1437

2

0.1U_0402_16V4Z

1

C1584

2

12

1

C6

2

0.1U_0402_16V4Z

12

1

C1435

2

1U_0402_6.3V4Z

C2

0.1U_0402_16V4Z

C1585

10U_0603_4V6M

12

R1449 Close to C1565

1

18P_0402_50V8J

18P_0402_50V8J C1566

C1566

2

5

1

2

1

2

10U_0603_6.3V6M

1

2

1

2

+3VS

27M_CLK<15>

@

MPVDD

1

C10

2

0.1U_0402_16V4Z

DDC2_DATA<17>

+DPLL_PVDD

C1427

C1427 1U_0402_6.3V4Z

1U_0402_6.3V4Z

PCIE_PVDD

1

C9

2

DPLL_VDDC

C1436

C1436 1U_0402_6.3V4Z

1U_0402_6.3V4Z

R1787 10K_0402_5%@R1787 10K_0402_5%@

CLKREQ#_E<15,31>

DDC2_CLK<17>

12

110_0402_1%

1 2

R1449

R1450

82_0402_5%

1K_0402_5%

+3VS

PAD

T97

R1791

12

R1752 2.2K_0402_5%R1752 2.2K_0402_5%

R1755 2.2K_0402_5%R1755 2.2K_0402_5%

T113PADT113PAD

GPIO11<23>

T114PADT114PAD

GPIO13<23> POW_SW<51>

27M_SSC<15>

12

M62S: R1450-->330 ohm 1% > ~ 1.1V

1 2 1 2

T88 PADT88 PAD T89 PADT89 PAD T90 PADT90 PAD T91 PADT91 PAD

T92 PADT92 PAD

VRAM_ID0<23> VRAM_ID1<23> VRAM_ID2<23> VRAM_ID3<23>

GPIO0<23> GPIO1<23>

GPIO4 GPIO5<23> GPIO6<23>

XIN XOUT

T115PADT115PAD

T98 PADT98 PAD T99 PADT99 PAD T100PADT100PAD T101PADT101PAD

T102PADT102PAD T103PADT103PAD

+DPLL_PVDD

PCIE_PVDD

MPVDD

DPLL_VDDC

VGA_VREF

4

U80B

AH7

VID_0

AG9

VID_1

AF9

VID_2

AJ7

VID_3

AG7

VID_4

AF7

VID_5

AH6

VID_6

AG6

VID_7

AL6

VHAD_0

AK6

VHAD_1

AK5

VPHCTL

AJ4

VPCLK0

AJ5

VIPCLK

AL5

PSYNC

AD9

DVALID

AA4

SDA

AA5

SCL

AK4

DVPCNTL_MVP_0

AL3

DVPCNTL_MVP_1

V2

DVPCNTL_0

V1

DVPCNTL_1

W3

DVPCNTL_2

W1

DVPCLK

Y1

DVPDATA_0

Y2

DVPDATA_1

Y3

DVPDATA_2

AA2

DVPDATA_3

AA3

DVPDATA_4

AB1

DVPDATA_5

AB2

DVPDATA_6

AB3

DVPDATA_7

AC1

DVPDATA_8

AC3

DVPDATA_9

AD1

DVPDATA_10

AD2

DVPDATA_11

AD3

DVPDATA_12

AF3

DVPDATA_13

AG3

DVPDATA_14

AH3

DVPDATA_15

AG1

DVPDATA_16

AH2

DVPDATA_17

AH1

DVPDATA_18

AJ3

DVPDATA_19

AJ1

DVPDATA_20

AJ2

DVPDATA_21

AK2

DVPDATA_22

AK3

DVPDATA_23

Y4

GPIO_0

V3

GPIO_1

V4

GPIO_2

V5

GPIO_3

U3

GPIO_4

U2

GPIO_5

T4

GPIO_6

T5

GPIO_7_BLON

T7

GPIO_8_ROMSO

T8

GPIO_9_ROMSI

R1

GPIO_10_ROMSCK

R2

GPIO_11

R3

GPIO_12

P1

GPIO_13

P3

GPIO_14_HPD2

N1

GPIO_15_PWRCNTL_0

N2

GPIO_16_SSIN

P4

GPIO_17_THERMAL_INT

P7

GPIO_18_HPD3

P8

GPIO_19_CTF

P5

GPIO_20_PWRCNTL_1

V7

GPIO_21_BB_EN

N3

GPIO_22_ROMCSB

Y5

GPIO_23_CLKREQB

M4

GPIO_24_TRST

M5

GPIO_25_TDI

M7

GPIO_26_TCK

M8

GPIO_27_TMS

L8

GPIO_28_TDO

Y8

GENERICA

Y7

GENERICB

V8

GENERICC

AC11

VREFG

AH12

DPLL_PVDD

AG12

DPLL_PVSS

AH31

PCIE_PVDD

AH30

PCIE_PVSS

A9

MPVDD

B9

MPVSS

AJ31

XTALIN

AJ30

XTALOUT

AE12

DPLL_VDDC

AD11

NC_10

216PTAKA13FG M62-S_BGA632

4

General

General Purpose

Purpose I/O

I/O

PLL &

PLL & XTAL

XTAL

PART 2 OF 6

V

V I

I D

D E

E O

O

VIP / I2C

&

M

M U

U L

L T

T I

I M

M E

E D

D I

I A

A

VIP Host/External TMDS

Integrated

Integrated TMDS

TMDS

TPVDD

TXVDDR_1 TXVDDR_2 TXVDDR_3 TXVDDR_4

TXVSSR_1 TXVSSR_2 TXVSSR_3 TXVSSR_4 TXVSSR_5 TXVSSR_6

DAC / CRT

HSYNC VSYNC

AVSSQ VDD1DI VSS1DI

DAC2 (TV/CRT2)

V2SYNC H2SYNC

A2VDDQ

A2VSSQ

VDD2DI VSS2DI

DDC1DATA

DDC1CLK

Monitor

Monitor Interface

Interface

DDC2DATA

DDC2CLK

DDC3DATA

DDC3CLK

TS_FDO

Thermal

DMINUS TESTEN

Test

PLLTEST

TXCM TXCP

TX0M

TX0P

TX1M

TX1P

TX2M

TX2P

TPVSS

NC_5 NC_6

NC_7 NC_8

NC_9

RSET AVDD

COMP

A2VDD

R2SET

HPD1

DPLUS

R2B

G2B

B2B

3

20070719 change for DVI high resolution issue

1

2

1 2

VGA_CRMA VGA_LUMA VGA_COMP

1

C1422

1U_0402_6.3V4Z

2

1 2

4.7K_0402_5%

VGA_THERMDA VGA_THERMDC

12

Issued Date

1 2

+TXVDDR

C1552

C1552 1U_0402_6.3V4Z

1U_0402_6.3V4Z

3

AK9 AL9

AJ9 AJ10

AL10 AK10

AL11 AK11

AL7 AK7

AJ12

+TXVDDR

AJ13 AK13 AL13

AJ8 AH9 AH11 AJ11 AK12 AL12

AE11 AF11

AK8 AL8

AG11

VGA_RED

AL28

R

AK28

RB

VGA_GRN

AL27

G

AK27

GB

VGA_BLU

AL26

B

AK26

BB

AK29 AK30

AJ28

R1775 470_0402_1%

AL29

AH28 AJ27 AJ26

AL17

R2

AK17 AL15

G2

AK15 AL14

B2

AK14 AJ17

C

AJ15

Y

AJ14 AE16

AF16 AH14

AH16 AG16 AF18 AE18 AG14

R1793 715_0402_1%

AA8 AJ29

AH29

R1796

AC5 AC4

R1799

4.7K_0402_5%

AF4 AH4

AE14 AE5

AE4 AH26

R1800 1K_0402_5%

AD12

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

1

2

C1414

0.1U_0402_16V4Z

M_HSYNC <16> M_VSYNC <16>

VDDDI_25

1

C1421

1U_0402_6.3V4Z

2

+A2VDD

1

2

DVI_DETECT <39>

DDC1_DATA <16>

DDC1_CLK <16>

12

+3VS

DVI_DAT <39> DVI_CLK <39>

12

+3VS

ICH_SM_DA <4,23,26,31>

ICH_SM_CLK <4,23,26,31>

VGA_THERMDA <23>

VGA_THERMDC <23>

R1740100_0402_1%

DVI_CLK- <39> DVI_CLK+ <39>

R1742100_0402_1%

DVI_TX0- <39> DVI_TX0+ <39>

R1745100_0402_1%

DVI_TX1- <39> DVI_TX1+ <39>

R1746100_0402_1%

DVI_TX2- <39> DVI_TX2+ <39>

1U_0402_6.3V4Z

C1415

+TPVDD

1

Closed to U80

2

Note: CRT / TV-out should route to JP30 first then to the

+AVDD

1

C1418

C1418 1U_0402_6.3V4Z

1U_0402_6.3V4Z

2

JP1 & JP2 on system side.

CRT Termination/EMI Filter

VGA_RED

VGA_GRN

VGA_BLU

R1764

12

75_0402_1%

R1763

12

Note: TV-out should route to JP30 first then to the JP1 & JP2 on system side.

TV-Out Termination/EMI Filter

VDDDI_25

1U_0402_6.3V4Z

1U_0402_6.3V4Z C1426

C1426

DVI

thermal

Compal Secret Data

2006/09/25 2006/09/25

Compal Secret Data

VGA_COMP

VGA_LUMA

VGA_CRMA

75_0402_1%

R1778

Deciphered Date

75_0402_1%

12

R1779

2

+LVDDR

1U_0402_6.3V4Z

+LPVDD

C1416

1U_0402_6.3V4Z

L28

1 2

HLC0603CSCC39NJT_0603

L35

1 2

HLC0603CSCC39NJT_0603

L27

1 2

HLC0603CSCC39NJT_0603

75_0402_1%

12

R1765

75_0402_1%

1

12

2

C238

5.6P_0402_50V8D

R1780

2

+LVDDR

1

C1412

2

+LPVDD

1

C1417

2

100N_0402_50V7M

C193

22P_0402_50V8J

1

2

C7

5.6P_0402_50V8D

U80F

PART 6 OF 6

AF20

LVDDR_1

AG20

LVDDR_2

AJ18

LVDDC_1

AH20

LVDDC_2

AF23

LVSSR_1

AF21

LVSSR_2

AL18

LVSSR_3

AJ22

LVSSR_4

AJ25

LVSSR_5

AK18

LVSSR_6

AK23

LVSSR_7

AK25

LVSSR_8

AJ21

LVSSR_9

AL23

LVSSR_10

AL25

LVSSR_11

AG18

LPVDD

AH18

LPVSS

216PTAKA13FG M62-S_BGA632

Control

TXCLK_UP

TXCLK_UN TXOUT_U0P TXOUT_U0N TXOUT_U1P TXOUT_U1N TXOUT_U2P TXOUT_U2N TXOUT_U3P TXOUT_U3N

TXCLK_LP

TXCLK_LN

LVDS channel

TXOUT_L0P TXOUT_L0N TXOUT_L1P TXOUT_L1N TXOUT_L2P TXOUT_L2N TXOUT_L3P TXOUT_L3N

VARY_BL

DIGON

AA7 AC6

AD21 AE21 AJ24 AJ23 AK24 AL24 AG21 AH21 AG23 AH23

AL19 AK19 AJ20 AJ19 AK20 AL20 AK21 AL21 AK22 AL22

1

10K_0402_5%

1 2

R1905

0906 change

Place Closed to U80

L31

C_RED_L

C_GRN_L

C_BLU_L

1

C237

2

22P_0402_50V8J

HLC0603CSCCR11JT_0603

1

C232

C232 22P_0402_50V8J

22P_0402_50V8J

2

L31

1 2

L34

1 2

L26

1 2

10P_0402_50V8J

C195

@C195

@

1

2

@C244

@

10P_0402_50V8J

1

@C245

@

2

10P_0402_50V8J

C244

C245

Place close to U80

L38

1 2

CHB1608U301_0603

CHB1608U301_0603 L37

L37

1 2

CHB1608U301_0603

CHB1608U301_0603 L17

L17

1 2

CHB1608U301_0603

C251

5.6P_0402_50V8D

Title

M62-S CRT/LVDS/TV-OUT

Size Document Number Rev

Date: Sheet

5.6P_0402_50V8D

Compal Electronics, Inc.

LA3262P_DIS__M64

1

2

C243

C8

5.6P_0402_50V8D

1

C253

2

5.6P_0402_50V8D

1

COMP <16,39>

LUMA <16,39>

CRMA <16,39>

0314 change design

19 57Tuesday, August 21, 2007

BLON_PWM <17> VGA_ENAVDD <17>

TXCLK_U+ <17> TXCLK_U- <17> TXOUT_U0+ <17> TXOUT_U0- <17> TXOUT_U1+ <17> TXOUT_U1- <17> TXOUT_U2+ <17> TXOUT_U2- <17>

TXCLK_L+ <17> TXCLK_L- <17> TXOUT_L0+ <17> TXOUT_L0- <17> TXOUT_L1+ <17> TXOUT_L1- <17> TXOUT_L2+ <17> TXOUT_L2- <17>

RED <39>

GREEN <39>

BLUE <39>

1A

of

5

MDB[63..32]<22> MDB[31..0]<22>

D D

C C

VDD_MEM18

12

R1801

40.2_0402_1%

C1429

1

12

R1802

100_0402_1%

B B

2

0.1U_0402_16V4Z

R1806

40.2_0402_1%

VDD_MEM18

12

MDB[63..32] MDB[31..0]

VDD_MEM18_REFD VDD_MEM18_REFS

4.7K_0402_5%

R1803

12

MDB0 MDB1 MDB2 MDB3 MDB4 MDB5 MDB6 MDB7 MDB8 MDB9 MDB10 MDB11 MDB12 MDB13 MDB14 MDB15 MDB16 MDB17 MDB18 MDB19 MDB20 MDB21 MDB22 MDB23 MDB24 MDB25 MDB26 MDB27 MDB28 MDB29 MDB30 MDB31 MDB32 MDB33 MDB34 MDB35 MDB36 MDB37 MDB38 MDB39 MDB40 MDB41 MDB42 MDB43 MDB44 MDB45 MDB46 MDB47 MDB48 MDB49 MDB50 MDB51 MDB52 MDB53 MDB54 MDB55 MDB56 MDB57 MDB58 MDB59 MDB60 MDB61 MDB62 MDB63

12

R1805

4.7K_0402_5%

4

U80C

E29 E30 E31 D31 C29 B29 B30 A29 E26 D26 E25 D25 G23 G21 E21 D21 C28 B28 B27 A27 C25 A25 C24 B24 C23 B23 A23 B22 C20 B20 A20 C19

C8 C7

B7 A7 A5

C4

B4 A3

G9

E9 D9 G7 G5

F5 G4

F4

B3

B2 C2 C1

E3

F3

F2

F1 G2 G1 H3 H2

K2

L3

L2

L1

F30 F31

L5

L7

J7

216PTAKA13FG M62-S_BGA632

12

R1807

243_0402_1%

DQ_0 DQ_1 DQ_2 DQ_3 DQ_4 DQ_5 DQ_6 DQ_7 DQ_8 DQ_9 DQ_10 DQ_11 DQ_12 DQ_13 DQ_14 DQ_15 DQ_16 DQ_17 DQ_18 DQ_19 DQ_20 DQ_21 DQ_22 DQ_23 DQ_24 DQ_25 DQ_26 DQ_27 DQ_28 DQ_29 DQ_30 DQ_31 DQ_32 DQ_33 DQ_34 DQ_35 DQ_36 DQ_37 DQ_38 DQ_39 DQ_40 DQ_41 DQ_42 DQ_43 DQ_44 DQ_45 DQ_46 DQ_47 DQ_48 DQ_49 DQ_50 DQ_51 DQ_52 DQ_53 DQ_54 DQ_55 DQ_56 DQ_57 DQ_58 DQ_59 DQ_60 DQ_61 DQ_62 DQ_63

MVREFD MVREFS

TEST_MCLK TEST_YCLK MEMTEST

Part 3 of 6

MEMORY INTERFACE

A

MEMORY INTERFACE

A

write strobe read strobe

MA_0 MA_1 MA_2 MA_3 MA_4 MA_5 MA_6 MA_7 MA_8

MA_9 MA_10 MA_11

MA_A12 MA_BA0 MA_BA1 MA_BA2

DQMB_0 DQMB_1 DQMB_2 DQMB_3 DQMB_4 DQMB_5 DQMB_6 DQMB_7

QS_0 QS_1 QS_2 QS_3 QS_4 QS_5 QS_6 QS_7

QS_0B QS_1B QS_2B QS_3B QS_4B QS_5B QS_6B QS_7B

ODT0

ODT1

CLK0 CLK1

CLK0B CLK1B

RAS0B RAS1B

CAS0B CAS1B

CS0B_0 CS0B_1

CS1B_0 CS1B_1

CKE0 CKE1

WE0b

WE1b

DRAM_RST

B14 A14 B13 E14 B17 A17 C15 G16 E16 C14 A12 B12 B15 C12 D14 G14

D30 G25 C26 C21 C5 D6 D2 K3

C30 D23 B26 B21 B6 E7 E2 J2

C31 E23 A26 A21 A6 D7 E1 J1

E20 C11

A18 A11

B18 B11

G20 D12

D20 E12

E18 G18

G11 E11

D18 G12

D16 C10

J5

4.7K_0402_5%

R1804

MAB0 MAB1 MAB2 MAB3 MAB4 MAB5 MAB6 MAB7 MAB8 MAB9 MAB10 MAB11

BA0 BA1 BA2

DQMB0 DQMB1 DQMB2 DQMB3 DQMB4 DQMB5 DQMB6 DQMB7

RDQS0 RDQS1 RDQS2 RDQS3 RDQS4 RDQS5 RDQS6 RDQS7

WDQS0 WDQS1 WDQS2 WDQS3 WDQS4 WDQS5 WDQS6 WDQS7

ODT0 ODT1

CLKA0 CLKA1

CLKA0# CLKA1#

RASA0# RASA1#

CASA0# CASA1#

CSA0_0#

CSA1_0#

CKEA0 CKEA1

WEA0# WEA1#

12

3

0904 Add

MAB[11..0] <22>

BA[2..0] <22>

DQMB[3..0] <22>

DQMB[7..4] <22>

RDQS[3..0] <22>

RDQS[7..4] <22>

WDQS[3..0] <22>

WDQS[7..4] <22>

ODT0 ODT1

CLKA0 <22> CLKA1 <22>

CLKA0# <22> CLKA1# <22>

RASA0# <22> RASA1# <22>

CASA0# <22> CASA1# <22>

CSA0_0# <22>

CSA1_0# <22>

CKEA0 <22> CKEA1 <22>

WEA0# <22> WEA1# <22>

DRAM_RST# <22>

2

1

12

R1808

100_0402_1%

A A

5

1

2

C1430

0.1U_0402_16V4Z

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/09/25 2006/09/25

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

M62-S MEM

LA3262P_DIS__M64

20 57Tuesday, August 21, 2007

1

1A

of

5

U80E

AA26

PCIE_VSS_1

AA29

PCIE_VSS_2

AC26

PCIE_VSS_3

AD31

PCIE_VSS_4

AE29

PCIE_VSS_5

AE30

PCIE_VSS_6

AE31

PCIE_VSS_7

F28

PCIE_VSS_8

G26

D D

C C

B B

PCIE_VSS_9

G29

PCIE_VSS_10

G30

PCIE_VSS_11

G31

PCIE_VSS_12

H29

PCIE_VSS_13

J25

PCIE_VSS_14

J26

PCIE_VSS_15

L26

PCIE_VSS_16

L29

PCIE_VSS_17

L30

PCIE_VSS_18

L31

PCIE_VSS_19

M26

PCIE_VSS_20

M29

PCIE_VSS_21

P26

PCIE_VSS_22

R29

PCIE_VSS_23

R30

PCIE_VSS_24

R31

PCIE_VSS_25

T26

PCIE_VSS_26

U29

PCIE_VSS_27

V26

PCIE_VSS_28

Y26

PCIE_VSS_29

Y29

PCIE_VSS_30

Y30

PCIE_VSS_31

Y31

PCIE_VSS_32

A13

VSS_1

A2

VSS_2

C18

VSS_3

A24

VSS_4

A30

VSS_5

AA1

VSS_6

AA11

VSS_7

AA14

VSS_8

AA17

VSS_9

AA20

VSS_10

AA6

VSS_11

AC2

VSS_12

AC7

VSS_13

AE3

VSS_15

AL4

VSS_16

AD14

VSS_17

AF12

VSS_18

AF14

VSS_19

AD16

VSS_20

AD18

VSS_21

AE6

VSS_22

AG2

VSS_23

AE9

VSS_24

AH25

VSS_25

AK1

VSS_26

AK31

VSS_27

AJ6

VSS_28

AL2

VSS_29

AL30

VSS_30

B1

VSS_31

C13

VSS_32

216PTAKA13FG M62-S_BGA632

Part 5 of 6

PCI-Express GND

CORE GND

VSS_33 VSS_34 VSS_35 VSS_36 VSS_37 VSS_38 VSS_39 VSS_40 VSS_41 VSS_42 VSS_43 VSS_44 VSS_45 VSS_46 VSS_47 VSS_48 VSS_49 VSS_50 VSS_51 VSS_52 VSS_53 VSS_54 VSS_55 VSS_56 VSS_57 VSS_58 VSS_59 VSS_60 VSS_61 VSS_62 VSS_63 VSS_64 VSS_65 VSS_66 VSS_67 VSS_68 VSS_69 VSS_70 VSS_71 VSS_72 VSS_73 VSS_74 VSS_75 VSS_76 VSS_77 VSS_78 VSS_79 VSS_80 VSS_81 VSS_82 VSS_83 VSS_84 VSS_85 VSS_86 VSS_87 VSS_88 VSS_89 VSS_90 VSS_91 VSS_92 VSS_93 VSS_94 VSS_95 VSS_96 VSS_97 VSS_98

VSS_99 VSS_100 VSS_101 VSS_102

B25 J8 B5 D11 C17 C22 C27 D29 C3 C6 D3 D28 F29 D4 F11 F12 F14 F16 F18 F20 F21 F23 F25 F7 F9 G3 G6 H23 J3 J4 J6 K1 L12 L15 L18 L21 L6 M11 M14 M17 M20 M6 P12 P15 P18 P21 P6 AC21 R14 R17 R20 T6 U1 U12 U15 U18 U21 AE20 V14 V17 V20 P2 V6 W2 Y12 Y15 Y18 Y21 Y6 M9

0904 change power rail

PWR_GD<26,31,37,40,41,49,50>

VDD_MEM18

+2.5VS

M62_VDDR

VDD_MEM18

SI2301BDS_SOT23

@ R1897

@

0_0402_5%

20K_0402_5%

0.1U_0402_16V4Z

4

1 2

R1809 0_0603_5%

0906 add 10uF

10U_0603_6.3V6M

2 1

PAD-OPEN 2x2m

2 1

@PAD-OPEN 2x2m

1 3

R1897

12

R1898

C1605

VDD_MEM18

10U_0603_6.3V6M

1U_0402_6.3V4Z

1

C1462

2

PJP17

PJP18

Q130

D

G

2

13

D

2

G

S

2

1

C1431

2

10U_0603_6.3V6M

1

C1438

2

1U_0402_6.3V4Z

1

C1446

2

1U_0402_6.3V4Z

1

C12

1U_0402_6.3V4Z

2

1

C1463

2

1U_0402_6.3V4Z

10U_0603_6.3V6M

1

C1476

2

1U_0402_6.3V4Z

S

R1813

R1813 100K_0402_5%

100K_0402_5%

1 2

Q129

RHU002N06_SOT323

10U_0603_6.3V6M

1

C1432

2

10U_0603_6.3V6M

1U_0402_6.3V4Z

1

C1439

2

1U_0402_6.3V4Z

1

C1447

2

1U_0402_6.3V4Z

VDD_CT

1

C1456

2

1U_0402_6.3V4Z

1

C1464

C1465

2

1U_0402_6.3V4Z

1

C1478

C1477

2

+3VS

10U_0603_6.3V6M

1

C1433

2

1U_0402_6.3V4Z

1

C1440

2

1U_0402_6.3V4Z

1

C1448

2

1

C1480

0.1U_0402_16V4Z

2

3

1

C1434

2

1

C1441

2

1

C1449

2

110mA

150mA

VDD_MEM_CLK0 VDD_MEM_CLK1

1.1A

U80D

A15

VDDR1_1

A22

VDDR1_2

A28

VDDR1_3

A4

VDDR1_4

A8

VDDR1_5

B8

VDDR1_6

C9

VDDR1_7

D1

VDDR1_8

H1

VDDR1_9

H11

VDDR1_10

H12

VDDR1_11

H14

VDDR1_12

H16

VDDR1_13

H18

VDDR1_14

H20

VDDR1_15

H21

VDDR1_16

B31

VDDR1_17

M1

VDDR1_18

J11

VDD_CT_1

J20

VDD_CT_2

J21

VDD_CT_3

L9

VDD_CT_4

AA9

VDD_CT_5

Y9

VDD_CT_6

V9

VDD_CT_7

T9

VDD_CT_8

AC18

VDDR3_1

AC16

VDDR3_2

AC14

VDDR3_3

AC12

VDDR3_4

AF1

VDDR4_1

AF2

VDDR4_2

AE1

VDDR5_1

AE2

VDDR5_2

M2

NC_1

M3

NC_2

L4

NC_3

AE7

NC_4

A10

VDDRH_1

A19

VDDRH_2

B10

VSSRH_1

B19

VSSRH_2

V11

BBN_1

U11

BBN_2

R11

BBP_1

P11

BBP_2

216PTAKA13FG M62-S_BGA632

PLACE ALL CAPS ON THIS PAGE CLOSE TO ASIC

PART 4 OF 6

I/O Internal

Memory

I/O

Clock

Memory

I/O

Clock

Memory I/O

PCI-Express

P

P O

O W

W E

E R

R

Back Bias

PCIE_VDDR_1 PCIE_VDDR_2 PCIE_VDDR_3 PCIE_VDDR_4 PCIE_VDDR_5 PCIE_VDDR_6 PCIE_VDDR_7 PCIE_VDDR_8

PCIE_VDDC_1 PCIE_VDDC_2 PCIE_VDDC_3 PCIE_VDDC_4 PCIE_VDDC_5 PCIE_VDDC_6 PCIE_VDDC_7 PCIE_VDDC_8

PCIE_VDDC_9 PCIE_VDDC_10 PCIE_VDDC_11 PCIE_VDDC_12

VDDC_1 VDDC_2 VDDC_3 VDDC_4 VDDC_5 VDDC_6 VDDC_7 VDDC_8

VDDC_9 VDDC_10 VDDC_11 VDDC_12 VDDC_13 VDDC_14 VDDC_15 VDDC_16

Core

VDDC_17 VDDC_18 VDDC_19 VDDC_20 VDDC_21 VDDC_22 VDDC_23 VDDC_24 VDDC_25 VDDC_26 VDDC_27 VDDC_28 VDDC_29 VDDC_30 VDDC_31 VDDC_32 VDDC_33

VDDCI_1 VDDCI_2 VDDCI_3 VDDCI_4

2

AF30 AF31 AF29 AF27 AF28 AG29 AG30 AG31

AA23 AC24 AC25 AE26 AE27 AE28 L23 M23 P23 T23 V23 Y23

L11 L14 L17 L20 M12 M15 M18 M21 AC20 P14 P17 P20 R12 R15 R18 R21 AD20 U14 U17 U20 V12 V15 V18 V21 Y11 Y14 Y17 Y20 AA12 AA15 AA18 AA21 P9

J12 J14 J16 J18

VDDCI

1U_0402_6.3V4Z

1

C1442

2

10U_0603_6.3V6M

VGA_VCORE

1

2

10U_0603_6.3V6M

1

2

10U_0603_6.3V6M

1

2

10U_0603_6.3V6M

1

2

10U_0603_6.3V6M

1U_0402_6.3V4Z

1

2

C1451

C1457

C1466

C1471

C1481

1

C1443

2

1U_0402_6.3V4Z

1

C1452

2

1U_0402_6.3V4Z

1

C1458

2

1U_0402_6.3V4Z

1

C1467

2

1U_0402_6.3V4Z

1

C1472

2

1

C1482

2

0.1U_0402_16V4Z

PCIE_VDDC

1

C1444

2

VGA_VCORE

1

C1453

2

1U_0402_6.3V4Z

1

C1459

2

1U_0402_6.3V4Z

1

C1468

2

1U_0402_6.3V4Z

1

C1473

2

1U_0402_6.3V4Z

1

C1483

2

1

C1445

0.1U_0402_16V4Z

2

1U_0402_6.3V4Z

10U_0603_6.3V6M

1.54A

L80

1

C1454

2

1

C1460

2

1

C1469

2

1

C1474

2

L81

1

CHB1608U301_0603

C1484

2

1

12

0_0805_5%

PAD-OPEN 4x4m

PJP19

1 2

12

PCIE_1.2V

1.5A

VDD_CORE

VDD_MEM18 VDD_MEM_CLK0

A A

5

1 2

R1879

1U_0402_6.3V4Z

0_0603_5%

1 2

R1880

1U_0402_6.3V4Z

0_0603_5%

C1553

C1557

4

1

C1555

2

10U_0603_6.3V6M

VDD_MEM_CLK1

1

C1558

2

1.1A

1

2

1.1A

1

2

10U_0603_6.3V6M

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/09/25 2006/09/25

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

M62-S POWER

LA3262P_DIS__M64

1

of

21 57Tuesday, August 21, 2007

of

21 57Tuesday, August 21, 2007

of

21 57Tuesday, August 21, 2007

1A

5

4

3

2

1

DDR3 VRAM: 8Mx32/16Mx32 FBGA_136P 2 pcs

B12

D12

L11

P12

VSSQT1VSSQT4VSSQT9VSSQ

DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8

DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VDD

VDDU2VDD

U11

0.1U_0402_16V4Z

1

C1507

2

0.1U_0402_16V4Z

1

2

T12

C1508

B12

D12

L11

P12

U82

MAB0 MAB1 MAB2 MAB3 MAB4 MAB5 MAB6 MAB7 MAB8 MAB9 MAB10 MAB11

DQMB6 DQMB4 DQMB5 DQMB7

RASA1# CASA1#

WEA1#

CSA1_0#

CKEA1

CLKA1

CLKA1#

BA0 BA1 BA2

RDQS6 RDQS4 RDQS5 RDQS7 WDQS6 WDQS4 WDQS5 WDQS7

0.1U_0402_16V4Z

3

U82

K4

A0

H2

A1

K3

A2

M4

A3

K9

A4

H11

A5

K10

A6

L9

A7

K11

A8/AP

M9

A9

K2

A10

L4

A11

E3

DM0

E10

DM1

N10

DM2

N3

DM3

H1

VREF

H12

VREF

J2

NC

H3

RAS#

F4

CAS#

H9

WE#

F9

CS#

H4

CKE

J11

CK

J10

CK#

G4

BA0

G9

BA1

H10

BA2

A4

ZQ

A9

MF

J3

RFU

U4

SEN

U9

RES

D3

RDQS0

D10

RDQS1

P10

RDQS2

P3

RDQS3

D2

WDQS0

D11

WDQS1

P11

WDQS2

P2

WDQS3

VDD_MEM18

C1493

VDD_MEM18

1

C1511

2

VSSQB1VSSQB4VSSQB9VSSQ

1

2

3

MDB24

B2

MDB25

B3

MDB26

C2

MDB27

C3

MDB28

E2

MDB29

F3

MDB30

F2

MDB31

G3

MDB8

B11

MDB9

B10

MDB10

C11

MDB11

C10

MDB12

E11

MDB13

F10

MDB14

F11

MDB15

G10

MDB16

M11

MDB17

L10

MDB18

N11

MDB19

M10

MDB20

R11

MDB21

R10

MDB22

T11

MDB23

T10

MDB0

M2

MDB1

L3

MDB2

N2

MDB3

M3

MDB4

R2

MDB5

R3

MDB6

T2

MDB7

T3 E1

A1 A12 C1 C4 C9 C12 E4 E9 E12 J4 J9 N1 N4 N9 N12 R1 R4 R9 R12 U1 U12 A2 A11 F1 F12 K1 K12 M1 M12

1

2

4

MDB[31..24] <20>

1

MDB[15..8] <20>

MDB[23..16] <20>

2

MDB[7..0] <20>

0

VDD_MEM18

0904 Add

MAB[11..0]<20>

DQMB[7..4]<20>

VREFB

RASA1#<20> CASA1#<20>

WEA1#<20>

CSA1_0#<20>

CKEA1<20>

CLKA1<20> CLKA1#<20> BA[2..0]<20>

R1830

DRAM_RST#<20>DRAM_RST#<20>

RDQS[7..4]<20>

1 2

243_0402_1%

WDQS[7..4]<20>

R1830

ZQ02

HY5RS573225AFP-16_FBGA_136P

VRAM@

Place close to U82

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

G11

VSSQD1VSSQD4VSSQD9VSSQ

VSSQL2VSSQ

VSSQP1VSSQP4VSSQP9VSSQ

VSSQG2VSSQ

VSSG1VSS

VSSJ1VSS

VSSL1VSS

VSSA3VSS

A10

1U_0402_6.3V4Z

C1512

2006/09/25 2006/09/25

J12

L12

G12

1

C1494

2

1U_0402_6.3V4Z

1

2

0.1U_0402_16V4Z

VSSU3VSS

U10

0.01U_0402_16V7K

C1496

C1513

T12

VSSQT1VSSQT4VSSQT9VSSQ

B2

DQ0

B3

DQ1

C2

DQ2

C3

DQ3

E2

DQ4

F3

DQ5

F2

DQ6

G3

DQ7

B11

DQ8

B10

DQ9

C11

DQ10

C10

DQ11

E11

DQ12

F10

DQ13

F11

DQ14

G10

DQ15

M11

DQ16

L10

DQ17

N11

DQ18

M10

DQ19

R11

DQ20

R10

DQ21

T11

DQ22

T10

DQ23

M2

DQ24

L3

DQ25

N2

DQ26

M3

DQ27

R2

DQ28

R3

DQ29

T2

DQ30

T3

DQ31

E1

VDDQ

A1

VDDQ

A12

VDDQ

C1

VDDQ

C4

VDDQ

C9

VDDQ

C12

VDDQ

E4

VDDQ

E9

VDDQ

E12

VDDQ

J4

VDDQ

J9

VDDQ

N1

VDDQ

N4

VDDQ

N9

VDDQ

N12

VDDQ

R1

VDDQ

R4

VDDQ

R9

VDDQ

R12

VDDQ

U1

VDDQ

U12

VDDQ

A2

VDD

A11

VDD

F1

VDD

F12

VDD

K1

VDD

K12

VDD

M1

VDD

M12

VDD

VDDU2VDD

U11

0.1U_0402_16V4Z

1

C1497

2

10U_0603_6.3V6M

1

2

Compal Secret Data

1

C1515

2

Deciphered Date

MDB48 MDB49 MDB50 MDB51 MDB52 MDB53 MDB54 MDB55 MDB32 MDB33 MDB34 MDB35 MDB36 MDB37 MDB38 MDB39 MDB40 MDB41 MDB42 MDB43 MDB44 MDB45 MDB46 MDB47 MDB56 MDB57 MDB58 MDB59 MDB60 MDB61 MDB62 MDB63

C1498

VDD_MEM18

1

C1499

2

0.1U_0402_16V4Z

2

6

MDB[55..48] <20>

4

MDB[39..32] <20>

5

MDB[47..40] <20>

7

MDB[63..56] <20>

1

2

VSSA3VSS

A10

VSSQD1VSSQD4VSSQD9VSSQ

0904 Add

VSSG1VSS

VSSJ1VSS

J12

G12

G11

VSSQG2VSSQ

VSSL1VSS

L12

VSSQL2VSSQ

VSSU3VSS

U10

VSSQP1VSSQP4VSSQP9VSSQ

U81

DQMB3 DQMB1 DQMB2 DQMB0

VREFA

BA2 CSA0_0# CKEA0 CASA0#

WEA0#

CLKA0

CLKA0#

BA1

BA0 RASA0#

RDQS3 RDQS1 RDQS2 RDQS0 WDQS3 WDQS1 WDQS2 WDQS0

MAB4 MAB5 MAB6 MAB9 MAB0 MAB1 MAB2 MAB11 MAB10 MAB3 MAB8 MAB7

ZQ01

U81

VSSQB1VSSQB4VSSQB9VSSQ

K4

A0

H2

A1

K3

A2

M4

A3

K9

A4

H11

A5

K10

A6

L9

A7

K11

A8/AP

M9

A9

K2

A10

L4

A11

E3

DM0

E10

DM1

N10

DM2

N3

DM3

H1

VREF

H12

VREF

J2

NC

H3

RAS#

F4

CAS#

H9

WE#

F9

CS#

H4

CKE

J11

CK

J10

CK#

G4

BA0

G9

BA1

H10

BA2

A4

ZQ

A9

MF

J3

RFU

U4

SEN

U9

RES

D3

RDQS0

D10

RDQS1

P10

RDQS2

P3

RDQS3

D2

WDQS0

D11

WDQS1

P11

WDQS2

P2

WDQS3

D D

MAB[11..0]<20>

DQMB[3..0]<20>

C C

BA2<20>

CSA0_0#<20>

CKEA0<20>

CASA0#<20>

WEA0#<20>

CLKA0<20>

CLKA0#<20> BA1<20>

BA0<20>

RASA0#<20>

VDD_MEM18

RDQS[3..0]<20>

B B

WDQS[3..0]<20>

243_0402_1%

R1881

1 2 1 2

R13 1K_0402_5%

HY5RS573225AFP-16_FBGA_136P

VRAM@

Place close to U81

1U_0402_6.3V4Z

C1502

5

1U_0402_6.3V4Z

1

C1503

2

C1516

0.1U_0402_16V4Z

1

C1504

2

1000P_0402_50V7K

1U_0402_6.3V4Z

1

C1517

2

1

2

1

2

1

C1506

2

10U_0603_6.3V6M

0.1U_0402_16V4Z

1

C1519

2

C1520

10U_0603_6.3V6M

VDD_MEM18

0.1U_0402_16V4Z

A A

0.1U_0402_16V4Z

VDD_MEM18

Place VREF divider and CAP close to memory

Title

Size Document Number Rev

Date: Sheet

VDD_MEM18

12

R1816

2.37K_0402_1%

10mil

12

R1817

5.49K_0402_1%

VDD_MEM18

12

R1819

12

R1823

5.49K_0402_1%

RASA0#

RASA1#

CASA0#

CASA1#

WEA0#

WEA1#

CSA0_0#

CSA1_0#

CKEA0

CKEA1

CLKA0

CLKA0#

CLKA1

CLKA1#

Compal Electronics, Inc.

M62-S VRAM

LA3262P_DIS__M64

VREFB

C1489

1

0.1U_0402_16V4Z

2

2.37K_0402_1%

10mil

VREFA

C1490

1

0.1U_0402_16V4Z

2

R1818 121_0402_1%

1 2

R1820 121_0402_1%

1 2

R1821 121_0402_1%

1 2

R1822 121_0402_1%

1 2

R1824 121_0402_1%

1 2

R1825 121_0402_1%

1 2

R1826 121_0402_1%

1 2

R1827 121_0402_1%

1 2

R1828 121_0402_1%

1 2

R1829 121_0402_1%

1 2

R1831 60.4_0402_1%

1 2

R1834 60.4_0402_1%

1 2

R1835 60.4_0402_1%

1 2

R1836 60.4_0402_1%

1 2

22 57Tuesday, August 21, 2007

1

22 57Tuesday, August 21, 2007

VDD_MEM18

1A

of

+3VS

R1853 10K_0402_5%R1853 10K_0402_5%

D D

C C

10K_0402_5%

ZZZ5

Samsung VRAM group

Samsung@

5

R184410K_0402_5% R184410K_0402_5%

12

R184710K_0402_5% R184710K_0402_5%

12

R185510K_0402_5%@ R185510K_0402_5%@

12

R185710K_0402_5%@ R185710K_0402_5%@

12

R185910K_0402_5% R185910K_0402_5%

12

R186910K_0402_5% @ R186910K_0402_5% @

12

R187010K_0402_5% @ R187010K_0402_5% @

12

R1871

HYN@ R1871

HYN@

12

R1872

128M@R1872

128M@

12

1 2

R1883 10K_0402_5%

1 2

R1884 10K_0402_5%

1 2

R1885 10K_0402_5%

SAM@

1 2

R1886 10K_0402_5%

64M@

ZZZ4

Hynix VRAM group

Hynix@

GPIO0 <19>

GPIO1 <19>

GPIO5 <19>

GPIO6 <19>

GPIO11 <19>

GPIO13 <19>

VRAM_ID0 <19>

VRAM_ID1 <19>

VRAM_ID2 <19>

VRAM_ID3 <19>

4

STRAPS

TX_PWRS_ENB

TX_DEEMPH_EN

DEBUG_ACCESS

PLL_IBIAS_RD

ROMIDCFG[3:0]

GPIO0

GPIO1

GPIO4

GPIO[6:5]

GPIO [9,13,12,11]

internal pull down

VRAM_ID[0:3]

DVPDATA (20,21,22,23)

Closed to U80

VDD_MEM18

1

C1594

10U_0603_6.3V6M

2

DESCRIPTION OF RECOMMENDED SETTING

FULL SWING

internal pull down

Transmitter De-emphasis Enable

internal pull down

Strap to set the debug muxes to bring out DEBUG signals even if registers are inaccessible

internal pull down

Bias Currentfor the PCIE PHY PLL

No ROM , with 128M frame buffer

No ROM , with 64M frame buffer

Samsung 8Mx32 1.8V

Samsung 16Mx32 1.8V

Hynix 8Mx32 1.8V

Hynix 16Mx32 1.8V

1

C1595

0.1U_0402_16V4Z

2

3

2

1

RECOMMENDED

1

Closed to U80

1

BLM18PG121SN1D_0603

0

GPIO6-->0 GPIO5-->1

0 0 0 X

0 1 0 X

VRAM_ID 0, 1, 2, 3

0 0 0 0

0 0 0 1

0 0 1 0

0 0 1 1

+2.5VS

BLM18PG121SN1D_0603

12

L89

C1586

10U_0603_6.3V6M

L82

C1569

10U_0603_6.3V6M

L83

12

C1572

10U_0603_6.3V6M

L84

12

C1575

10U_0603_6.3V6M

12

L85

C1578

10U_0603_6.3V6M

L86

12

C1581

10U_0603_6.3V6M

12

1

2

1

2

1

2

1

2

1

2

1

2

1

C1592

2

1U_0402_6.3V4Z

1

2

C1570

0.1U_0402_16V4Z

1

C1580

0.001U_0402_50V7M

2

110mA,20mils

VDDDI_25

280mA, 20mils

+LVDDR

+LPVDD

20mA, 10mils

+TPVDD

60mA, 10mils

+TXVDDR

100mA, 20 mils

+AVDD

100mA, 20mils

VGA Thermal Sensor ADM1032ARMZ

B B

H_THERMTRIP#<4,7,25>

A A

RHU002N06_SOT323

Closed to U80

VGA_THERMDA<19>

VGA_THERMDC<19>

+3VS

Q31

5

R1894 10K_0402_5%R1894 10K_0402_5%

1 2

R1906 0_0402_5%@ R1906 0_0402_5%@

1 2

13

D

2

G

S

0.1U_0402_16V4Z

C1600

1 2

2200P_0402_50V7K

+3VS

10K_0402_5%

1 2 13

D

RHU002N06_SOT323

S

+3VS

2

C1599

1

U84

1

VDD D+

ALERT#

DTHERM#4GND

SCLK

SDATA

ICH_SM_CLK<4,19,26,31>

ICH_SM_DA<4,19,26,31>

VGA_THERMDC THERM_SCI#

THERM#_VGA

R1896

2 3

ADM1032ARMZ REEL_MSOP8

0802 (R1A) add for VGA thermal function

2

G

Q30

THERM#_VGA <4>

8 7 6 5

4

ICH_SM_CLK ICH_SM_DAVGA_THERMDA

R1893

R1893 10K_0402_5%

10K_0402_5%

1 2

ICH_SM_CLK ICH_SM_DA

THERM_SCI# <4,26>

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/09/25 2006/09/25

Compal Secret Data

Deciphered Date

2

BLM18PG121SN1D_0603

12

L88

10U_0603_6.3V6M

Title

Size Document Number Rev

Date: Sheet

1

C1588

2

Compal Electronics, Inc.

M62-S Filters / Strap

LA3262P_DIS__M64

+A2VDD

120mA, 20mils

23 57Tuesday, August 21, 2007

1

23 57Tuesday, August 21, 2007

1A

of

5

+3VS

PCI_GNT3#

PCI_DEVSEL# PCI_STOP# PCI_TRDY# PCI_FRAME# PCI_PLOCK# PCI_IRDY# PCI_SERR# PCI_PERR# MBAY_DET# MDC_DIS

PCI_PIRQA# PCI_PIRQB# PCI_PIRQC# PCI_PIRQD# PCI_PIRQE# PCI_PIRQG# PIRQH# PCI_REQ0# PCI_REQ1# PCI_REQ2# PCI_REQ3#

12

R1534

@

1K_0402_5%

PCI_AD[0..31]<31>

1 2

R1514 8.2K_0402_5%

1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2

1 2 1 2 1 2 1 2 1 2 1 2

1 2 1 2 1 2 1 2

12

R1515 8.2K_0402_5%

R1515 8.2K_0402_5% R1516 8.2K_0402_5%

D D

C C

B B

R1516 8.2K_0402_5% R1517 8.2K_0402_5%

R1517 8.2K_0402_5% R1518 8.2K_0402_5%

R1518 8.2K_0402_5% R1519 8.2K_0402_5%

R1519 8.2K_0402_5% R1520 8.2K_0402_5%

R1520 8.2K_0402_5% R1521 8.2K_0402_5%

R1521 8.2K_0402_5% R1585 10K_0402_5%

R1585 10K_0402_5% R1748 10K_0402_5%

R1748 10K_0402_5%

+3VS

R1522 8.2K_0402_5%

R1522 8.2K_0402_5% R1523 8.2K_0402_5%

R1523 8.2K_0402_5% R1524 8.2K_0402_5%

R1524 8.2K_0402_5% R1525 8.2K_0402_5%

R1525 8.2K_0402_5% R1526 8.2K_0402_5%

R1526 8.2K_0402_5% R10 8.2K_0402_5%

R10 8.2K_0402_5% R189 8.2K_0402_5%

R189 8.2K_0402_5% R1530 8.2K_0402_5%

R1530 8.2K_0402_5% R1531 8.2K_0402_5%

R1531 8.2K_0402_5% R1532 8.2K_0402_5%

R1532 8.2K_0402_5% R1533 8.2K_0402_5%

R1533 8.2K_0402_5%

A16 swap override Strap

Low= A16 swap override Enble

PCI_GNT3#

A A

High= Default

Place closely pin B10

CLK_PCI_ICH

R1537

10_0402_5% @

1 2 1

C1177

8.2P_0402_50V@

2

*

4

PCI_AD0 PCI_AD1 PCI_AD2 PCI_AD3 PCI_AD4 PCI_AD5 PCI_AD6 PCI_AD7 PCI_AD8 PCI_AD9 PCI_AD10 PCI_AD11 PCI_AD12 PCI_AD13 PCI_AD14 PCI_AD15 PCI_AD16 PCI_AD17 PCI_AD18 PCI_AD19 PCI_AD20 PCI_AD21 PCI_AD22 PCI_AD23 PCI_AD24 PCI_AD25 PCI_AD26 PCI_AD27 PCI_AD28 PCI_AD29 PCI_AD30 PCI_AD31

PCI_PIRQA# PCI_PIRQB#

PCI_PIRQC#<31> PCI_PIRQD#<31>

PCI_PIRQC# PCI_PIRQD#

Boot BIOS Strap

PCI_GNT0# SPI_CS#1

R1535

1

0

1

0

1

12

21

1K_0402_5%

J35

J35 PAD-NO SHORT 2x2m

PAD-NO SHORT 2x2m

U26B

D20

AD0

E19 D19 A20 D17 A21 A19 C19 A18 B16 A12 E16 A14 G16 A15

B6

C11

A9 D11 B12 C12 D10

C7 F13 E11 E13 E12

D8

A6 E8

D6

A3

F9 B5

C5 A10

PCI

AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31

Interrupt I/F

PIRQA# PIRQB# PIRQC# PIRQD#

ICH8M REV 1.0

REQ1#/GPIO50 GNT1#/GPIO51 REQ2#/GPIO52 GNT2#/GPIO53 REQ3#/GPIO54 GNT3#/GPIO55

PIRQE#/GPIO2

PIRQF#/GPIO3 PIRQG#/GPIO4 PIRQH#/GPIO5

Boot BIOS Location

SPI

*

PCI

LPC

SPI_CS1#_R<26>

SPI_CS1#_RPCI_GNT0#

REQ0# GNT0#

C/BE0# C/BE1# C/BE2# C/BE3#

IRDY#

PAR

PCIRST#

DEVSEL#

PERR#

PLOCK#

SERR# STOP# TRDY#

FRAME#

PLTRST#

PCICLK

PME#

3

12

A4 D7 E18 C18 B19 F18 A11 C10

C17 E15 F16 E17

C8 D9 G6 D16 A7 B7 F10 C16 C9 A17

AG24 B10 G7

F8 G11 F12 B3

R1536

@

1K_0402_5%

PCI_REQ0# PCI_GNT0# PCI_REQ1#

PCI_REQ2# PCI_GNT2# PCI_REQ3# PCI_GNT3#

PCI_CBE#0 PCI_CBE#1 PCI_CBE#2 PCI_CBE#3

PCI_IRDY# PCI_PAR PCI_PCIRST# PCI_DEVSEL# PCI_PERR# PCI_PLOCK# PCI_SERR# PCI_STOP# PCI_TRDY# PCI_FRAME#

PCI_PLTRST# CLK_PCI_ICH PCI_PME#

8.2K_0402_5%

PCI_PIRQE# MBAY_DET#

PIRQH#

0_0402_5%

R1527

1 2

R188

12

MDC_DIS PCI_REQ2# <31> PCI_GNT2# <31>

PCI_CBE#0 <31> PCI_CBE#1 <31> PCI_CBE#2 <31> PCI_CBE#3 <31>

PCI_IRDY# <31> PCI_PAR <31>

PCI_DEVSEL# <31> PCI_PERR# <31>

PCI_SERR# <31,37> PCI_STOP# <31> PCI_TRDY# <31> PCI_FRAME# <31>

PCI_PLTRST# <31> CLK_PCI_ICH <15> PCI_PME#

+3VALW

PCI_PIRQE# <31> MBAY_DET# <28> PCI_PIRQG# <31> ACCEL_INT <31>

0301 change

0601 change

PCI_PCIRST#

PCI_PLTRST#

2

VGA_RST#<18>

R1051

R1051 0_0402_5%

0_0402_5%

R1057

R1057 0_0402_5%

0_0402_5%

1

+3V_U43

14

VGARST#

4

P

A

6

O

+3VALW

5

U56

1

P

B

4

Y

2

A

G

TC7SH08FU_SSOP5@

3

12

+3VALW

5

U59

1

P

B

PLT_RST#

4

Y

2

A

G

TC7SH08FU_SSOP5@

3

12

PLT_RST#

5

B

G

U43B

7

SN74LVC08APW_TSSOP14

PCI_RST#

12

R192

R192 100K_0402_5%

100K_0402_5%

12

R191

R191 100K_0402_5%

100K_0402_5%

VGARST# <26>

PLT_RST# <7,28,36>

PCI_RST# <28,31>

PLT_RST# <7,28,36>

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/09/25 2006/09/25

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

ICH8(1/4)-PCI/INT

LA3262P_DIS__M64

24 57Tuesday, August 21, 2007

1

1A

of

5

+RTCVCC

D D

R1540 330K_0402_1%

LAN100_SLP

1 2

R1542 1M_0402_5%

SM_INTRUDER#

1 2

R1543 330K_0402_1%

ICH_INTVRMEN

1 2

+RTCVCC

11/20 For RTC Accuracy fail to change

R1733

1 2

10M_0402_5%

1

C528

15P_0402_50V8J

C C

+3VS

R1560

R1560 10K_0402_5%

10K_0402_5%

HDA_BITCLK

R1561

R1561 10_0402_5%

10_0402_5%

@

1 2

1

B B

2

C1181

10P_0402_25V8K

@

R90

10K_0402_5%

MB2_LED#<28>

2

Y4

1 4 2 3

32.768KHZ_12.5P_MC-146

IDE_LED#

12

+5VS

12

SATA_LED#

MB2_LED#

ICH_RTCX1

ICH_RTCX2

1

C516

15P_0402_50V8J

2

+3VS

12

R88

R88 10K_0402_5%

10K_0402_5%

IDE_LED#

21

D15 CH751H-40_SC76D15 CH751H-40_SC76

21

D16 CH751H-40_SC76D16 CH751H-40_SC76

SHORT PADS

CLRP2

GREEN_BATLED#<31,37>

R1545

1 2

20K_0402_5%

C1178

1U_0603_10V4Z

HDA_BITCLK_MDC<38>

HDA_BITCLK_CODEC<32>

HDA_SYNC_CODEC<32>

HDA_SYNC_MDC<38>

HDA_RST#_CODEC<32>

HDA_RST#_MDC<32,38>

HDA_SDIN0<32> HDA_SDIN1<38>

HDA_SDOUT_MDC<38>

HDA_SDOUT_CODEC<32>

12

1

2

+3VS

3

2007,0125 change

IDE_LED# <31>

2

1 2

1

ENERGY_DET<30>

CHP202U_SC70

Q144

SATA_RXN0_C<28> SATA_RXP0_C<28>

4

CLRP1

CLRP1 SHORT PADS

SHORT PADS

GLAN_CLK<29>

LAN_RSTSYNC<29>

LAN_RXD0<29> LAN_RXD1<29> LAN_RXD2<29>

LAN_TXD0<29> LAN_TXD1<29> LAN_TXD2<29>

+1.5VS

1K_0402_5%

SATA_TXN0<28> SATA_TXP0<28>

R1549 24.9_0402_1%

1 2

R1551

33_0402_5%

33_0402_5% 33_0402_5%

33_0402_5%

R1550

R1550 R1553 33_0402_5%

R1553 33_0402_5% R1554 33_0402_5%

R1554 33_0402_5% R1555 33_0402_5%

R1555 33_0402_5% R1556 33_0402_5%

R1556 33_0402_5%

R1558 33_0402_5%

R1558 33_0402_5% R1559 33_0402_5%

R1559 33_0402_5%

1 2

R1935

SATA_TXN0 SATA_TXP0

CLK_PCIE_SATA#<15> CLK_PCIE_SATA<15>

R1551

1 2 1 2 1 2 1 2 1 2 1 2

1 2 1 2

T38PAD T38PAD

3900P_0402_50V7K

C1179

1 2

C1180

1 2

3900P_0402_50V7K

CLK_PCIE_SATA# CLK_PCIE_SATA

1 2

24.9_0402_1%

Within 500 mils

ICH_RTCX1 ICH_RTCX2

ICH_RTCRST# SM_INTRUDER# ICH_INTVRMEN

LAN100_SLP GLAN_CLK LAN_RSTSYNC LAN_RXD0

LAN_RXD1 LAN_RXD2

LAN_TXD0 LAN_TXD1 LAN_TXD2

GLAN_COMP HDA_BITCLK

HDA_SYNC HDARST#

HDA_SDIN0 HDA_SDIN1

HDA_SDOUT

SATA_LED#

SATA_TXN0_C SATA_TXP0_C

R1564

3

U26A

AG25

RTCX1

AF24

RTCX2

AF23

RTCRST#

AD22

INTRUDER#

AF25

INTVRMEN

AD21

LAN100_SLP

B24

GLAN_CLK

D22

LAN_RSTSYNC

C21

LAN_RXD0

B21

LAN_RXD1

C22

LAN_RXD2

D21

LAN_TXD0

E20

LAN_TXD1

C20

LAN_TXD2

AH21

GLAN_DOCK#/GPIO13

D25

GLAN_COMPI

C25

GLAN_COMPO

AJ16

HDA_BIT_CLK

AJ15

HDA_SYNC

AE14

HDA_RST#

AJ17

HDA_SDIN0

AH17

HDA_SDIN1

AH15

HDA_SDIN2

AD13

HDA_SDIN3

AE13

HDA_SDOUT

AE10

HDA_DOCK_EN#/GPIO33

AG14

HDA_DOCK_RST#/GPIO34

AF10

SATALED#

AF6

SATA0RXN

AF5

SATA0RXP

AH5

SATA0TXN

AH6

SATA0TXP

AG3

SATA1RXN

AG4

SATA1RXP

AJ4

SATA1TXN

AJ3

SATA1TXP

AF2

SATA2RXN

AF1

SATA2RXP

AE4

SATA2TXN

AE3

SATA2TXP

AB7

SATA_CLKN

AC6

SATA_CLKP

AG1

SATARBIAS#

AG2

SATARBIAS

ICH8M REV 1.0

FWH0/LAD0 FWH1/LAD1 FWH2/LAD2 FWH3/LAD3

FWH4/LFRAME#

LDRQ0#

LDRQ1#/GPIO23

RTCLAN / GLAN

LPCCPU

RTCLAN / GLAN

LPCCPU

A20GATE

A20M#

DPRSTP#

DPSLP#

FERR#

CPUPWRGD/GPIO49

IGNNE#

RCIN#

STPCLK#

THRMTRIP#

IHDA

IDE

SATA

DCS1# DCS3#

DIOR#

DIOW#

DDACK#

IDEIRQ

IORDY

DDREQ

W=20mils

2

C665

C665 1U_0603_10V4Z

1U_0603_10V4Z

1

INIT#

INTR

NMI

SMI#

TP8

DD0 DD1 DD2 DD3 DD4 DD5 DD6 DD7 DD8

DD9 DD10 DD11 DD12 DD13 DD14 DD15

DA0

DA1

DA2

1 2

0_0402_5%

R981

E5 F5 G8 F6

C4 G9

E6 AF13

AG26 AF26

AE26 AD24 AG29 AF27 AE24

AC20 AH14

AD23 AG28

AA24 AE27 AA23 V1

U2 V3 T1 V4 T5 AB2 T6 T3 R2 T4 V6 V5 U1 V2 U6

AA4 AA1 AB3

Y6 Y5

W4 W3 Y2 Y3 Y1 W5

LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3

LPC_FRAME# LPC_DRQ0#

GATEA20 H_A20M#

H_FERR# H_PWRGOOD H_IGNNE# H_INIT#

H_INTR KB_RST#

H_NMI H_SMI#

H_STPCLK# THRMTRIP_ICH#

PD_D0 PD_D1 PD_D2 PD_D3 PD_D4 PD_D5 PD_D6 PD_D7 PD_D8 PD_D9 PD_D10 PD_D11 PD_D12 PD_D13 PD_D14 PD_D15

PD_A0 PD_A1 PD_A2

PD_CS1# PD_CS3#

PD_IOR#

PD_IOW#

PD_DACK# PD_IORDY#

PD_DREQ#

W=20mils

DAN202U_SC70

PD_IRQ

1

2

LPC_AD[0..3] <35,36,37>

LPC_FRAME# <35,36,37> LPC_DRQ#0 <35>

GATEA20 <37> H_A20M# <4>

R1548 0_0402_5%

H_FERR# <4>

KB_RST# <37>

PD_A0 <28> PD_A1 <28> PD_A2 <28>

PD_CS1# <28> PD_CS3# <28>

PD_IOR# <28>

PD_IOW# <28>

PD_DACK# <28>

PD_IRQ <28>

PD_IORDY# <28>

PD_DREQ# <28>

D14

2 3

W=20mils

T39 PADT39 PAD

H_DPRSTP#H_DPRSTP_R#

12

H_DPSLP# <5>

H_PWRGOOD <5> H_IGNNE# <4> H_INIT# <4>

H_INTR <4>

H_NMI <4> H_SMI# <4>

H_STPCLK# <4> 1 2

PD_D[0..15] <28>

+3VL+RTCVCC

BATT1.1

R976

1 2

1K_0402_5%

H_DPRSTP# <5,7,49>

R1557 24_0402_1%

placed within 2" from ICH8M

PD_IORDY#

JP42

JP42 ACES_85205-0200

ACES_85205-0200

1

2

+

W=20mils

conn@

-

GATEA20

KB_RST#

H_DPRSTP#

H_DPSLP#

PD_IRQ

10K_0402_5%

H_FERR#

within 2" from R1557

+VCCP

12

R1552

R1552 56_0402_5%

56_0402_5%

R1562 4.7K_0402_5% R1562 4.7K_0402_5%

1 2

R1563 8.2K_0402_5% R1563 8.2K_0402_5%

1 2

BATT1

CR2032 RTC BATTERY

1

+3VS

R1538

12

R1539

12

+VCCP

R1541

12

56_0402_5%

R1544

@R1544

@

12

56_0402_5%

R1546

@R1546

@

12

56_0402_5%

H_THERMTRIP# <4,7,23>

+3VS

A A

XOR CHAIN ENTRANCE STRAP:RSVD

+3VS

R1567

R1567 1K_0402_5%

1K_0402_5%

@

12

5

HDA_SDOUT_CODEC

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/09/25 2006/09/25

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

ICH8(2/4)_LAN,HD,IDE,LPC

LA3262P_DIS__M64

1

1A

of

25 57Tuesday, August 21, 2007

OCP#

LID_SW#

ICH_RI#

USB_OC#6 USB_OC#1 USB_OC#2 USB_OC#4

RP5510K_1206_8P4R_5% RP5510K_1206_8P4R_5%

USB_OC#7 USB_OC#8 USB_OC#9 USB_OC#0

RP5610K_1206_8P4R_5% RP5610K_1206_8P4R_5%

WXMIT_OFF#

+3VALW

R1007

5

10K_0402_5%

10K_0402_5% 10K_0402_5%

10K_0402_5%

+3VALW

ME_EC_CLK1<37>

ME_EC_DATA1<37>

10K_0402_5% @

10K_0402_5% @ 10K_0402_5% @

10K_0402_5% @

+3VM

H_STP_PCI#<15> H_STP_CPU#<15>

R1581

R1581 R1580

R1580

12 12

11/20 solve auto-turn on

11/20 For detect CPU and system power saving

LAN_PHYPC<29>

SPI_CS1#

Cap_RST#_SB<38>

CLKSATAREQ#<15>

DOCK_ID<39>

+3VS

8.2K_0402_5%

+3VALW

SLP_S3#<29,32,33,37,39,40,47,48,49,50,51,52>

+3VM_LAN

LED_LINK_LAN#<29,30,39>

1

IN1

2

IN2

11/06 follow UMA SI-2 design change

2007,0125 change

+3VM

12

2.2K_0402_5%

2.2K_0402_5% R204

R204

R2062.2K_0402_5% R2062.2K_0402_5%

+3VS

12

R2072.2K_0402_5% R2072.2K_0402_5%

+5VS

12

D57

5

D

S

D

S

G

2

+3VM

12

2.2K_0402_5%

2.2K_0402_5% R205

R205

Q26 RHU002N06_SOT323

D

S

D

S

G

2

+3VS

12

R1008

R1008 10K_0402_5%

10K_0402_5%

ISO_PREP#

21

CH751H-40_SC76

Q24

Q24 RHU002N06_SOT323

RHU002N06_SOT323

13

D

S

D

S

13

Q25

G

RHU002N06_SOT323

2

ICH_SMB_DATA

13

D

S

D

S

ICH_SMB_CLK

13

G

Q29

2

RHU002N06_SOT323

ICH_SMB_DATA <31>

+3VALW

R1573

R1573 R1572

R1572

12 12

XDP_DBRESET#<4> PM_BMBUSY#<7>

LED_LINK_LAN#<29,30,39>

R179 0_0402_5%R179 0_0402_5%

PM_CLKRUN#<31,35,36,37>

ICH_PCIE_WAKE#<31>

THERM_SCI#<4,23>

VGATE<7,37>

1 2

12

R19270_0402_5% R19270_0402_5%

VGARST#<24>

1 2

R1632

IDE_RESET#<28>

MCH_ICH_SYNC#<7>

ICH_RSVD

+3VALW

U92SN74AHC1G08DCKR_SC70 U92SN74AHC1G08DCKR_SC70

5

P

4

O

G

3

2

13

D

S

D

S

Q143

HDD_HALTLED

+3VS

SIRQ

1 2

R1576 10K_0402_5%

PM_CLKRUN#

1 2

R1578 8.2K_0402_5%

GPIO39

1 2

R1579 10K_0402_5%

THERM_SCI#

1 2

R1582 8.2K_0402_5%@ R1582 8.2K_0402_5%@

CLKSATAREQ#

1 2

R1600 10K_0402_5%

GPIO37

1 2

R1595 8.2K_0402_5%

GPIO18

1 2

D D

+3VALW

C C

B B

A A

R1601 8.2K_0402_5%

VGARST#

1 2

R1602 8.2K_0402_5%

GPIO20

1 2

R1617 8.2K_0402_5%

IDE_RESET#

1 2

R11 8.2K_0402_5%

NPCI_RST#

1 2

R3 8.2K_0402_5%

MB_PWR

1 2

R6 8.2K_0402_5%

ALS_EN#

1 2

R16 8.2K_0402_5%

PM_BMBUSY#

1 2

R9 8.2K_0402_5%

1 2

R1590 10K_0402_5%

LINKALERT#

1 2

R1587 10K_0402_5%@ R1587 10K_0402_5%@

1 2

R1593 10K_0402_5%

ICH_LOW_BAT#

12

R1594 8.2K_0402_5%

ICH_PCIE_WAKE#

1 2

R1584 1K_0402_5%

1 2

R1597 10K_0402_5%

LAN_PHYPC

1 2

R1603 10K_0402_5%

XDP_DBRESET#

1 2

R1589 1K_0402_5%

S4_STATE#

1 2

R1631 10K_0402_5%

XMIT_OFF

12

R1608 10K_0402_5%

USB_OC#5

12

R1609 10K_0402_5% R1609 10K_0402_5%

45 36 27 18

12

R1944 10K_0402_5% R1944 10K_0402_5%

R1604 100K_0402_5%R1604 100K_0402_5%

DPRSLPVR

1 2

ICH_RSVD

12

R1568 1K_0402_5%@R1568 1K_0402_5%@

HDD_HALTLED

1 2

R15 8.2K_0402_5%

0316 change design

ICH_SMBDATA<13,14,15>

ICH_SMBCLK<13,14,15> ICH_SMB_CLK <31>

ICH_SM_DA<4,19,23,31>

ICH_SM_CLK<4,19,23,31>

2007,0125 change

10K_0402_5%

PREP#<30,32,39>

4

1 2

+3VALW

1 2

SMB

SYS

GPIO

SYS

GPIO

MISC

low-->default High -->No boot

C7100.1U_0402_16V4Z

12

C7110.1U_0402_16V4Z

12

C7080.1U_0402_16V4Z C7080.1U_0402_16V4Z

12

C7090.1U_0402_16V4Z C7090.1U_0402_16V4Z

12

C16090.1U_0402_16V4Z C16090.1U_0402_16V4Z

12

C16100.1U_0402_16V4Z C16100.1U_0402_16V4Z

12

C11860.1U_0402_16V4Z C11860.1U_0402_16V4Z

12

C11870.1U_0402_16V4Z C11870.1U_0402_16V4Z

12

SPI_CLK_R

R160515_0402_5%

SPI_CS0#_R

R160615_0402_5%

SPI_CS1#_R

R160715_0402_5%

SPI_SI_R

R16400_0402_5%

12

SPI_SO_R

R16410_0402_5%

12

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

GPIO11_SB

GPIO18 GPIO20

GPIO38 GPIO39

1 2

R1723 10K_0402_5% @R1723 10K_0402_5% @

1 2

R159910K_0402_5% R159910K_0402_5%

VCC_IDL<41>

U26C

AJ26

SMBCLK

AD19

SMBDATA

AG21

LINKALERT#

AC17

SMLINK0

AE19

SMLINK1

AF17

RI#

F4

SUS_STAT#/LPCPD#

AD15

SYS_RESET#

AG12

BMBUSY#/GPIO0

AG22

SMBALERT#/GPIO11

AE20

STP_PCI#/GPIO15

AG18

STP_CPU#/GPIO25

AH11

CLKRUN#/GPIO32

AE17

WAKE#

AF12

SERIRQ

AC13

THRM#

AJ20

VRMPWRGD

AJ22

TP7

AJ8

TACH1/GPIO1

AJ9

TACH2/GPIO6

AH9

TACH3/GPIO7

AE16

GPIO8

AC19

GPIO12

AG8

TACH0/GPIO17

AH12

GPIO18

AE11

GPIO20

AG10

SCLOCK/GPIO22

AH25

QRT_STATE0/GPIO27

AD16

QRT_STATE1/GPIO28

AG13

SATACLKREQ#/GPIO35

AF9

SLOAD/GPIO38

AJ11

SDATAOUT0/GPIO39

AD10

SDATAOUT1/GPIO48

AD9

SPKR

AJ13

MCH_SYNC#

AJ21

TP3

ICH8M REV 1.0

SB_SPKR

R352

CB_IN#

1 2 1 2 1 2

1 2

0_0402_5%

+3VALW

R1570 2.2K_0402_5%R1570 2.2K_0402_5% R1571 2.2K_0402_5%

R1571 2.2K_0402_5%

ICH_SMB_CLK

1 2

ICH_SMB_DATA

1 2

CL_RST#1<31>

LPC_PD#<36>

12

SIRQ<31,35,36,37>

1 2

R145 0_0402_5%@R145 0_0402_5%@

OCP#<4,50>

RUNSCI_EC#<37>

ISO_PREP#<39> LID_SW#<17,38>

R3490_0402_5% @R3490_0402_5% @

12

0_0402_5%@

SB_SPKR<32>

12

R1928

10K_0402_5%

GPIO11_SB

RHU002N06_SOT323

WLAN

Robson

Dock

GLAN Right side

GPIO29<37>

13

D

2

G

S

LINKALERT# ME_EC_CLK1 ME_EC_DATA1

ICH_RI#

XDP_DBRESET#

PM_BMBUSY#

R1727

@R1727

@

1 2

0_0402_5%

H_STP_PCI# R_STP_CPU#

ICH_PCIE_WAKE#

SIRQ THERM_SCI#

VRMPWRGD SST_CTL

T15PAD T15PAD

OCP# RUNSCI_EC# ISO_PREP#

LAN_PHYPC_R ALS_EN#

T48PAD T48PAD

Cap_RST#_SB

R1591

IDE_RESET# SB_SPKR MCH_ICH_SYNC#

ICH_RSVD

+3VS

PCIE_RXN2<31> PCIE_RXP2<31> PCIE_TXN2<31> PCIE_TXP2<31>

PCIE_RXN4<31> PCIE_RXP4<31> PCIE_TXN4<31> PCIE_TXP4<31>

PCIE_RXN5<39> PCIE_RXP5<39> PCIE_TXN5<39> PCIE_TXP5<39>

GLAN_RXN<29> GLAN_RXP<29> GLAN_TXN<29>

GLAN_TXP<29>

SPI_CLK<36> SPI_CS0#<36> SPI_CS1#<36>

SPI_CS1#_R<24>

SPI_SI<36> SPI_SO<36>

BT_OFF<34>

WXMIT_OFF#<31>

0_0402_5%

1 2

R161

HDD_HALTLED# <31>

Q114

Q114 RHU002N06_SOT323

RHU002N06_SOT323

4

3

R192910K_0402_5% R192910K_0402_5%

LAN_PHYPC_R

R19300_0402_5%@ R19300_0402_5%@

SATA0GP/GPIO21 SATA1GP/GPIO19 SATA2GP/GPIO36

SATA

GPIO

SATA

GPIO

SATA3GP/GPIO37

CLK14

Clocks

Power MGTController Link

ME_EC_ALERT/GPIO10 EC_ME_ALERT/GPIO14

PCIE_RXN2 PCIE_RXP2 PCIE_C_TXN2 PCIE_C_TXP2

PCIE_RXN4 PCIE_RXP4 PCIE_C_TXN4 PCIE_C_TXP4

PCIE_RXN5 PCIE_RXP5 PCIE_C_TXN5 PCIE_C_TXP5

GLAN_RXN GLAN_RXP GLAN_TXN_C GLAN_TXP_C

USB_OC#0 USB_OC#1 USB_OC#2 WXMIT_OFF# USB_OC#4 USB_OC#5 USB_OC#6 USB_OC#7 USB_OC#8 USB_OC#9

CLK48 SUSCLK SLP_S3#

SLP_S4# SLP_S5#

S4_STATE#/GPIO26

PWROK

DPRSLPVR/GPIO16

BATLOW# PWRBTN#

LAN_RST#

RSMRST#

CK_PWRGD

CLPWROK

SLP_M#

CL_CLK0 CL_CLK1

CL_DATA0 CL_DATA1

CL_VREF0 CL_VREF1

CL_RST#

MEM_LED/GPIO24

WOL_EN/GPIO9

U26D

P27

PERN1

P26

PERP1

N29

PETN1

N28

PETP1

M27

PERN2

M26

PERP2

L29

PETN2

L28

PETP2

K27

PERN3

K26

PERP3

J29

PETN3

J28

PETP3

H27

PERN4

H26

PERP4

G29

PETN4

G28

PETP4

F27

PERN5

F26

PERP5

E29

PETN5

E28

PETP5

D27

PERN6/GLAN_RXN

D26

PERP6/GLAN_RXP

C29

PETN6/GLAN_TXN

C28

PETP6/GLAN_TXP

C23

SPI_CLK

B23

SPI_CS0#

E22

SPI_CS1#

D23

SPI_MOSI

F21

SPI_MISO

AJ19

OC0#

AG16

OC1#/GPIO40

AG15

OC2#/GPIO41

AE15

OC3#/GPIO42

AF15

OC4#/GPIO43

AG17

OC5#/GPIO29

AD12

OC6#/GPIO30

AJ18

OC7#/GPIO31

AD14

OC8#

AH18

OC9#

ICH8M REV 1.0

3

2

11/20 For detect CPU and system power saving

AJ12

HDD_HALTLED

AJ10 AF11

GPIO37

AG11

CLK_14M_ICH

AG9

CLK_48M_ICH

G5

ICH_SUSCLK

D3 AG23

AF21 AD18

AH27 AE23 AJ14 AE21 C2 AH20 AG27 E1 E3 AJ25 F23

AE18 F22

AF19 D24

AH23 AJ23 AJ27

AJ24 AF22 AG19

0612 Change GPIO pin assignment

SLP_S3# <29,32,33,37,39,40,47,48,49,50,51,52> SLP_S4# <40,48> SLP_S5# <40,48>

S4_STATE#

PM_PWROK DPRSLPVR ICH_LOW_BAT# ON/OFFBTN#

R1722

1 2

0_0402_5%

EC_RMRST#

R1586 100_0402_5%

CK_PWRGD_R

R148 0_0402_5%R148 0_0402_5%

M_PWROK PM_SLP_M#

CL_VREF0_ICH CL_VREF1_ICH

XMIT_OFF CB_IN#

1 2

R1738

R1738 0_0402_5%

0_0402_5%

DMI0RXN DMI0RXP DMI0TXN

DMI1RXN DMI1RXP DMI1TXN

DMI2RXN DMI2RXP DMI2TXN

DMI3RXN DMI3RXP DMI3TXN

PCI-Express

DMI_CLKN DMI_CLKP

DMI_ZCOMP

DMI_IRCOMP

Direct Media Interface

SPI

USB

USBRBIAS#

USBRBIAS

MB_PWR <28>

NPCI_RST# <35,37>

CLK_14M_ICH <15> CLK_48M_ICH <15>

T14 PADT14 PAD

S4_STATE# <34>

PM_PWROK <37> DPRSLPVR <7,49>

2 1

D22CH751H-40PT_SOD323-2 D22CH751H-40PT_SOD323-2

ON/OFFBTN# <38> LAN_RST# <41>

PM_RSMRST#

1 2

DMI0TXP

DMI1TXP

DMI2TXP

DMI3TXP

USBP0N USBP0P USBP1N USBP1P USBP2N USBP2P USBP3N USBP3P USBP4N USBP4P USBP5N USBP5P USBP6N USBP6P USBP7N USBP7P USBP8N USBP8P USBP9N USBP9P

CK_PWRGD

1 2

M_PWROK <7,41>

PM_SLP_M# <37,40,47,48,52>

CL_CLK0 <7> CL_CLK1 <31>

CL_DATA0 <7> CL_DATA1 <31>

CL_RST# <7>

XMIT_OFF <31>

AMT ADP_PRES <37> LAN_WOL_EN <40>

V27 V26 U29 U28

Y27 Y26 W29 W28

AB26 AB25 AA29 AA28

AD27 AD26 AC29 AC28

T26 T25

DMI_IRCOMP

Y23 Y24

G3 G2 H5 H4 H2 H1 J3 J2 K5 K4 K2 K1 L3 L2 M5 M4 M2 M1 N3 N2

USBRBIAS

F2 F3

1 2

1

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z C1185

C1185

DMI_RXN0 DMI_RXP0 DMI_TXN0 DMI_TXP0

DMI_RXN1 DMI_RXP1 DMI_TXN1 DMI_TXP1

DMI_RXN2 DMI_RXP2 DMI_TXN2 DMI_TXP2

DMI_RXN3 DMI_RXP3 DMI_TXN3 DMI_TXP3

CLK_PCIE_ICH# CLK_PCIE_ICH

R1016

24.9_0402_1%

USB20_N0 USB20_P0 USB20_N1 USB20_P1

USB20_N4 USB20_P4 USB20_N5 USB20_P5 USB20_N6 USB20_P6 USB20_N7 USB20_P7 USB20_N8 USB20_P8 USB20_N9 USB20_P9

R1019 22.6_0402_1%

R1583

10K_0402_5%

1 2

R1630

100K_0402_5%

CK_PWRGD <15>

1 2

12

C1184

R1592

R1592 453_0402_1%

453_0402_1%

1

2

453_0402_1%

J36

2 1

PAD-SHORT 2x2m

DMI_RXN0 <7> DMI_RXP0 <7> DMI_TXN0 <7> DMI_TXP0 <7>

DMI_RXN1 <7> DMI_RXP1 <7> DMI_TXN1 <7> DMI_TXP1 <7>

DMI_RXN2 <7> DMI_RXP2 <7> DMI_TXN2 <7> DMI_TXP2 <7>

DMI_RXN3 <7> DMI_RXP3 <7> DMI_TXN3 <7> DMI_TXP3 <7>

1 2

USB20_N0 <34> USB20_P0 <34> USB20_N1 <36> USB20_P1 <36>

USB20_N4 <34> USB20_P4 <34> USB20_N5 <34> USB20_P5 <34> USB20_N6 <34> USB20_P6 <34> USB20_N7 <39> USB20_P7 <39> USB20_N8 <31> USB20_P8 <31> USB20_N9 <39> USB20_P9 <39>

1 2

Within 500 mils

Compal Secret Data

2006/09/25 2006/09/25

Compal Secret Data

Deciphered Date

2

LOW_BAT# <37>

+3VL

R15883.24K_0402_1% R15883.24K_0402_1%

+3VM

1 2

12

R1596

3.24K_0402_1%

R1598

CABLE_DETECT <30>

CLK_PCIE_ICH# <15> CLK_PCIE_ICH <15>

+1.5VS

Within 500 mils

Fingerprint

Left side Left side Bluetooth Dock1 WWAN Dock2

1

10K_0402_5%

R1767

2

G

Q20

0.22U_0402_10V4Z

+3VS

12

1 2 13

D

S

10K_0402_5%

R434

@R434

@

1

2

C1620

@C1620

@

ALS_EN#

1 2

12

1 2

@

R1757

R1757 100K_0402_5%

100K_0402_5%

+3VS

2

G

R433

330_0402_5%

1 2 13

D

S

RHU002N06_SOT323

0904 change

PWR_GD<21,31,37,40,41,49,50>

CLK_EN#<49>

RHU002N06_SOT323

+3VALW

Place closely pin AG9Place closely pin G5

CLK_48M_ICH CLK_14M_ICH

12

R1574

10_0402_5%@

1

C1182

4.7P_0402_50V8C@

2

R1569 10K_0402_5%

PM_RSMRST#

RSMRST circuit

0619 change

RSMRST_EC<37>

R1909

2.2K_0402_5%@

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

LA3262P_DIS__M64

1 2

R1908

BAV99DW-7_SOT363@

ICH8(3/4)_PM,USB,GPIO

D68B

1 2

R1751

1 2

5

2.2K_0402_5%@

1 2

4

3

1

12

1

2

0_0402_5%

E

B

1

2

6

C

R1575

C1183

123

MMBT3906_SOT23@

MMBT3906_SOT23@ Q137

Q137 D68A

BAV99DW-7_SOT363

CK_PWRGD

R1470_0402_5%@ R1470_0402_5%@

VRMPWRGD

R1460_0402_5% R1460_0402_5%

ALS_EN <17>

Q45

10_0402_5%@

4.7P_0402_50V8C@

PM_RSMRST#

@D68A

@

of

26 57Tuesday, August 21, 2007

1A

5

R1372

D D

+5VS +3VS

12

R1610

100_0402_5%

C C

10_0402_5%

B B

A A

+3VALW+5VALW

12

R1611

+1.5VS

CHB1608U301_0603

0.1U_0402_16V4Z

1 2

C1223

1 2

+1.5VS

CHB1608U301_0603

21

D55

D55 CH751H-40_SC76

CH751H-40_SC76

20 mils

ICH_V5REF_RUN

1

C1190

0.47U_0402_6.3V6K

2

21

D56

D56 CH751H-40_SC76

CH751H-40_SC76

ICH_V5REF_SUS

20 mils

1

C1200

0.1U_0402_16V4Z

2

R1366

+1.5VS

C1219

0.1U_0402_16V4Z

+3VM

1

+1.5VS

2

R1372

C1211

1 2

5

1

2

C1194

220U_D2_4VM

C1212

1U_0603_10V4Z

1

2

CHB1608U301_0603

R1365

C1224

+RTCVCC

1

C1188

2

0.1U_0402_16V4Z

40 mils

1

+

C1195

2

10U_0805_10V4Z

1

2

10U_0805_10V4Z

+1.5VS

0.1U_0402_16V4Z

1

2

2.2U_0603_6.3V4Z

10U_0805_10V4Z

1

C1189

2

0.1U_0402_16V4Z

ICH_V5REF_RUN

10U_0805_10V4Z

1

C1196

2

1U_0603_10V4Z

+1.5VS

1U_0603_10V4Z

C1220

1

+1.5VS

C1225

2

20 mils

ICH_V5REF_SUS

1

C1197

2

2.2U_0603_6.3V4Z

+1.5VS

C1213

C1216

1

2

VCC_LAN1_05_INT_ICH_1

T30T30

VCC_LAN1_05_INT_ICH_2

T31T31

R1371

1 2

CHB1608U301_0603

1

2

1

2

+1.5VS

4.7U_0805_10V4Z

1

C1228

2

+3VS

AD25

AA25 AA26 AA27 AB27 AB28 AB29

M24 M25

W25

AG7

AC10

W23

A16

T7

G4

D28 D29 E25 E26 E27 F24 F25 G24 H23 H24

J23

J24 K24 K25 L23 L24 L25

N23 N24 N25 P24 P25 R24 R25 R26 R27 T23 T24 T27 T28 T29 U24 U25 V23 V24 V25

Y25 AJ6 AE7

AF7 AH7

AJ7 AC1

AC2 AC3 AC4 AC5

AC9 AA5

AA6 G12

G17

H7

AC7 AD7

D1

F1 L6

L7 M6 M7

F17 G18

F19 G20

A24 A26

A27 B26 B27 B28

B25

4

U26F

VCCRTC V5REF[1]

V5REF[2] V5REF_SUS VCC1_5_B[01]

VCC1_5_B[02] VCC1_5_B[03] VCC1_5_B[04] VCC1_5_B[05] VCC1_5_B[06] VCC1_5_B[07] VCC1_5_B[08] VCC1_5_B[09] VCC1_5_B[10] VCC1_5_B[11] VCC1_5_B[12] VCC1_5_B[13] VCC1_5_B[14] VCC1_5_B[15] VCC1_5_B[16] VCC1_5_B[17] VCC1_5_B[18] VCC1_5_B[19] VCC1_5_B[20] VCC1_5_B[21] VCC1_5_B[22] VCC1_5_B[23] VCC1_5_B[24] VCC1_5_B[25] VCC1_5_B[26] VCC1_5_B[27] VCC1_5_B[28] VCC1_5_B[29] VCC1_5_B[30] VCC1_5_B[31] VCC1_5_B[32] VCC1_5_B[33] VCC1_5_B[34] VCC1_5_B[35] VCC1_5_B[36] VCC1_5_B[37] VCC1_5_B[38] VCC1_5_B[39] VCC1_5_B[40] VCC1_5_B[41] VCC1_5_B[42] VCC1_5_B[43] VCC1_5_B[44] VCC1_5_B[45] VCC1_5_B[46]

VCCSATAPLL VCC1_5_A[01]

VCC1_5_A[02] VCC1_5_A[03] VCC1_5_A[04] VCC1_5_A[05]

VCC1_5_A[06] VCC1_5_A[07] VCC1_5_A[08] VCC1_5_A[09] VCC1_5_A[10]

VCC1_5_A[11] VCC1_5_A[12]

VCC1_5_A[13] VCC1_5_A[14]

VCC1_5_A[15] VCC1_5_A[16] VCC1_5_A[17]

VCC1_5_A[18] VCC1_5_A[19]

VCCUSBPLL VCC1_5_A[20]

VCC1_5_A[21] VCC1_5_A[22] VCC1_5_A[23] VCC1_5_A[24]

VCC1_5_A[25] VCCLAN1_05[1]

VCCLAN1_05[2] VCCLAN3_3[1]

VCCLAN3_3[2] VCCGLANPLL VCCGLAN1_5[1]

VCCGLAN1_5[2] VCCGLAN1_5[3] VCCGLAN1_5[4] VCCGLAN1_5[5]

VCCGLAN3_3

ICH8M REV 1.0

4

VCC1_05[01] VCC1_05[02] VCC1_05[03] VCC1_05[04] VCC1_05[05] VCC1_05[06] VCC1_05[07] VCC1_05[08] VCC1_05[09] VCC1_05[10] VCC1_05[11] VCC1_05[12] VCC1_05[13] VCC1_05[14] VCC1_05[15] VCC1_05[16]

CORE

VCC1_05[17] VCC1_05[18] VCC1_05[19] VCC1_05[20] VCC1_05[21] VCC1_05[22] VCC1_05[23] VCC1_05[24] VCC1_05[25] VCC1_05[26] VCC1_05[27] VCC1_05[28]

VCCA3GP ATXARX

V_CPU_IO[1] V_CPU_IO[2]

VCCP_COREVCCPSUSVCCPUSB

IDE

PCI

VCCSUSHDA

VCCSUS1_05[1] VCCSUS1_05[2]

VCCSUS1_5[1]

VCCSUS1_5[2] VCCSUS3_3[01] VCCSUS3_3[02]

VCCSUS3_3[03] VCCSUS3_3[04] VCCSUS3_3[05]

USB CORE

VCCSUS3_3[06] VCCSUS3_3[07]

VCCSUS3_3[08] VCCSUS3_3[09] VCCSUS3_3[10] VCCSUS3_3[11] VCCSUS3_3[12] VCCSUS3_3[13] VCCSUS3_3[14] VCCSUS3_3[15] VCCSUS3_3[16] VCCSUS3_3[17] VCCSUS3_3[18] VCCSUS3_3[19]

GLAN POWER

VCCCL3_3[1] VCCCL3_3[2]

VCCDMIPLL VCC_DMI[1]

VCC_DMI[2]

VCC3_3[01] VCC3_3[02] VCC3_3[03]

VCC3_3[04] VCC3_3[05] VCC3_3[06]

VCC3_3[07] VCC3_3[08] VCC3_3[09] VCC3_3[10] VCC3_3[11] VCC3_3[12] VCC3_3[13]

VCC3_3[14] VCC3_3[15] VCC3_3[16] VCC3_3[17] VCC3_3[18] VCC3_3[19] VCC3_3[20] VCC3_3[21] VCC3_3[22] VCC3_3[23] VCC3_3[24]

VCCHDA

VCCCL1_05

VCCCL1_5

3

+VCCP

0.1U_0402_16V4Z

A13 B13 C13 C14 D14 E14 F14 G14 L11 L12 L14 L16 L17 L18 M11 M18 P11 P18 T11 T18 U11 U18 V11 V12 V14 V16 V17 V18

R29 AE28

AE29 AC23

AC24 AF29 AD2 AC8

AD8 AE8 AF8

AA3 U7 V7 W1 W6 W7 Y7

A8 B15 B18 B4 B9 C15 D13 D5 E10 E7 F11

AC12 AD11 J6

AF20

VCCSUS1_5_ICH_1

AC16

VCCSUS1_5_ICH_2

J7

0.1U_0402_16V4Z

C3 AC18

AC21 AC22 AG20 AH28

P6 P7 C1 N7 P1 P2 P3 P4 P5 R1 R3 R5 R6

VCCCL1_05_ICH

G22 A22 F20

G21

0.1U_0402_16V4Z

1

C1193 0.1U_0402_16V4Z

2

0.01U_0402_16V7K

1

C1198

2

0.1U_0402_16V4Z

+3VS

1

2

0.1U_0402_16V4Z

1

C1208

C1209

2

0.1U_0402_16V4Z

C1215

+3VALW

1

C1217

2

+3VALW

1

C1222

4.7U_0603_6.3V6M

2

T19T19

C1229

@

3

1

2

CHB1608U301_0603

R1370

1 2

1

C1199 10U_0805_10V4Z

2

+1.25VS

22U_0805_6.3VAM

C1201

1

2

0.1U_0402_16V4Z

+3VS

(SATA)

1

2

C1206

+3VS

1

C1210

2

0.1U_0402_16V4Z

+3VALW

1

2

0.1U_0402_16V4Z

1

C1218

2

+3VS

100K_0402_5%

1 2

Q124

@

Q124

@

RHU002N06_SOT323

2006/09/25 2006/09/25

@

R1716

2

G

+1.5VS

+3VS

1

C1205

2

1

C1214

2

13

D

S

+VCCP

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M C1202

C1202

(DMI)

Compal Secret Data

1

2

+3VS

1 2

100K_0402_5%

Q125

@

Q125

@

RHU002N06_SOT323

Deciphered Date

0.1U_0402_16V4Z

R1717

2

@

G

0.1U_0402_16V4Z

C1203

1

2

13

D

S

C1192

+3VS

0.1U_0402_16V4Z

0.1U_0402_16V4Z C1207

C1207

0.1U_0402_16V4Z

T28T28

T29T29 T17T17 T18T18

1U_0603_10V4Z

1

+3VM

2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2

C1204

1

C1204

2

+3VS+3VS

R1718

@R1718

@

1 2

100K_0402_5%

2

G

Q126

@

Q126

@

RHU002N06_SOT323

2

U26E

A23

VSS[001]

A5

VSS[002]

AA2

VSS[003]

AA7

VSS[004]

A25

VSS[005]

AB1

VSS[006]

AB24

VSS[007]

AC11

VSS[008]

AC14

VSS[009]

AC25

VSS[010]

AC26

VSS[011]

AC27

VSS[012]

AD17

VSS[013]

AD20

VSS[014]

AD28

VSS[015]

AD29

VSS[016]

AD3

VSS[017]

AD4

VSS[018]

AD6

VSS[019]

AE1

VSS[020]

AE12

VSS[021]

AE2

VSS[022]

AE22

VSS[023]

AD1

VSS[024]

AE25

VSS[025]

AE5

VSS[026]

AE6

VSS[027]

AE9

VSS[028]

AF14

VSS[029]

AF16

VSS[030]

AF18

VSS[031]

AF3

VSS[032]

AF4

VSS[033]

AG5

VSS[034]

AG6

VSS[035]

AH10

VSS[036]

AH13

VSS[037]

AH16

VSS[038]

AH19

VSS[039]

AH2

VSS[040]

AF28

VSS[041]

AH22

VSS[042]

AH24

VSS[043]

AH26

VSS[044]

AH3

VSS[045]

AH4

VSS[046]

AH8

VSS[047]

AJ5

VSS[048]

B11

VSS[049]

B14

VSS[050]

B17

VSS[051]

B2

VSS[052]

B20

VSS[053]

B22

VSS[054]

B8

VSS[055]

C24

VSS[056]

C26

VSS[057]

C27

VSS[058]

C6

VSS[059]

D12

VSS[060]

D15

VSS[061]

D18

VSS[062]

D2

VSS[063]

D4

VSS[064]

E21

VSS[065]

E24

VSS[066]

E4

VSS[067]

E9

VSS[068]

F15

VSS[069]

E23

VSS[070]

F28

VSS[071]

F29

VSS[072]

F7

VSS[073]

G1

VSS[074]

E2

VSS[075]

G10

VSS[076]

G13

VSS[077]

G19

VSS[078]

G23

VSS[079]

G25

VSS[080]

G26

VSS[081]

G27

VSS[082]

H25

VSS[083]

H28

VSS[084]

H29

VSS[085]

H3

VSS[086]

H6

VSS[087]

J1

VSS[088]

J25

VSS[089]

J26

VSS[090]

J27

VSS[091]

J4

VSS[092]

J5

VSS[093]

K23

VSS[094]

K28

VSS[095]

K29

VSS[096]

K3

VSS[097]

K6

VSS[098]

ICH8M REV 1.0

CRACK_GPIO28CRACK_GPIO28 CRACK_GPIO28

13

D

S

Title

Size Document Number Rev

Custom

LA3262P_DIS__M64

Date: Sheet

VSS_NCTF[01] VSS_NCTF[02] VSS_NCTF[03] VSS_NCTF[04] VSS_NCTF[05] VSS_NCTF[06] VSS_NCTF[07] VSS_NCTF[08] VSS_NCTF[09] VSS_NCTF[10] VSS_NCTF[11] VSS_NCTF[12]

R1719

@R1719

@

100K_0402_5%

ICHGND1ICHGND2ICHGND4ICHGND3

@

RHU002N06_SOT323

Compal Electronics, Inc.

ICH8(4/4)_POWER&GND

VSS[099] VSS[100] VSS[101] VSS[102] VSS[103] VSS[104] VSS[105] VSS[106] VSS[107] VSS[108] VSS[109] VSS[110] VSS[111] VSS[112] VSS[113] VSS[114] VSS[115] VSS[116] VSS[117] VSS[118] VSS[119] VSS[120] VSS[121] VSS[122] VSS[123] VSS[124] VSS[125] VSS[126] VSS[127] VSS[128] VSS[129] VSS[130] VSS[131] VSS[132] VSS[133] VSS[134] VSS[135] VSS[136] VSS[137] VSS[138] VSS[139] VSS[140] VSS[141] VSS[142] VSS[143] VSS[144] VSS[145] VSS[146] VSS[147] VSS[148] VSS[149] VSS[150] VSS[151] VSS[152] VSS[153] VSS[154] VSS[155] VSS[156] VSS[157] VSS[158] VSS[159] VSS[160] VSS[161] VSS[162] VSS[163] VSS[164] VSS[165] VSS[166] VSS[167] VSS[168] VSS[169] VSS[170] VSS[171] VSS[172] VSS[173] VSS[174] VSS[175] VSS[176] VSS[177] VSS[178] VSS[179] VSS[180] VSS[181] VSS[182] VSS[183] VSS[184]

+3VS

Q127

1

K7 L1 L13 L15 L26 L27 L4 L5 M12 M13 M14 M15 M16 M17 M23 M28 M29 M3 N1 N11 N12 N13 N14 N15 N16 N17 N18 N26 N27 N4 N5 N6 P12 P13 P14 P15 P16 P17 P23 P28 P29 R11 R12 R13 R14 R15 R16 R17 R18 R28 R4 T12 T13 T14 T15 T16 T17 T2 U12 U13 U14 U15 U16 U17 U23 U26 U27 U3 U5 V13 V15 V28 V29 W2 W26 W27 Y28 Y29 Y4 AB4 AB23 AB5 AB6 AD5 U4 W24

ICHGND1

A1 A2 A28 A29 AH1 AH29 AJ1 AJ2 AJ28 AJ29 B1 B29

+3VL

1 2 13

D

1 2

100K_0402_5%

2

G

S

1

1 2

R138 0_0402_5%R138 0_0402_5%

ICHGND2

1 2

R152 0_0402_5%R152 0_0402_5%

ICHGND3

R153 0_0402_5%R153 0_0402_5%

ICHGND4

R137 0_0402_5%R137 0_0402_5%

R1715

CRACK_GPIO28 <11,37>

27 57Tuesday, August 21, 2007

1 2

of

1A

5

JP45

conn@JP45

conn@

S1

GND

S2

RX+

S3

RX-

S4

GND

TX-

TX+

26

GND

3.3V

3.3V GND GND GND

5V 5V 5V

GND

Rsv

GND

12V 12V 12V

boss23boss24GND25GND

OCTEK_SAT-22DD1G

D D

C C

B B

SATA_RXN0

S5

SATA_RXP0

S6 S7

P1 P2 P3 P4 P5 P6 P7 P8

10U_0805_10V4Z

P9 P10 P11 P12 P13 P14 P15

1

C1232

2

0.1U_0402_16V4Z

SATA_TXP0 <25>

SATA_TXN0 <25>

1 2 1 2

close SATA connector

0.1U_0402_16V4Z

1

C1233

C1236

C1234

2

1000P_0402_50V7K

C4743900P_0402_50V7K C4743900P_0402_50V7K C4753900P_0402_50V7K C4753900P_0402_50V7K

SATA_RXN0_C <25> SATA_RXP0_C <25>

1

C1235

C1235 1U_0402_6.3V4Z

1U_0402_6.3V4Z

2

4

+5VS

3

+3V_U43

IDE_RESET#<26>

PLT_RST_B#

R1036 0_0402_5% R1036 0_0402_5%

PCI_RST#<24,31>

R1037 0_0402_5%@R1037 0_0402_5%@

12

1 2

C641 0.1U_0402_16V4ZC641 0.1U_0402_16V4Z

14

9

P

A

10

B

G

7

SN74LVC08APW_TSSOP14

MBAY_DET#<24>

MB_PWR<26>

RHU002N06_SOT323

+3V_U43

8

O

U43C

4.7K_0402_5%

0.1U_0402_16V4Z

470K_0402_5%

Q38

R301

2

RR72

C628

R83

G

2

12

33_0402_5%

+3VS

12

MBAY_DET#

1

2

+5VS

12

13

D

S

ODD_RST#

1 2

RHU002N06_SOT323

conn@

55 56 57 58

JAE_WM2M054JKB

10U_0805_10V4Z

220K_0402_5%

220K_0402_5% R93

R93

2

G

Q39

Multi Bay II connector

JP5

1

2

3

4

ODD_RST#

5

PD_D8

6

PD_D7

7

PD_D9

8

PD_D6

9

PD_D10

10

PD_D5

11

PD_D11

12

PD_D4

13

PD_D12

14

PD_D3

15

PD_D13

16

PD_D2

17

PD_D14

18

PD_D1

19

PD_D15

20

PD_D0

21

PD_DREQ

22

23

GND GND GND GND

+5VS

1

C640

2

1

C633

0.1U_0402_16V4Z

2

+5VS_MB

12

R98

R98 100_0402_5%

100_0402_5%

13

D

S

23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54

PD_IOR#

24

PD_IOW#

25 26

PD_IORDY

27

PD_DACK#

28

PD_IRQ

29 30

PD_A1

31 32

PD_A0

33

PD_A2

34

PD_CS#1

35

PD_CS#3

36

MB2_LED#

37 38 39 40 41 42 43 44

MBAY_DET#

45 46 47 48 49 50 51 52 53 54

12

R1032

0_0402_5%

Q92

Q92 AO4407_SO8

AO4407_SO8

1 2 3 6

4

Place close to JP29

ZZZ2

+5VS_MB

8 7

5

C624

10U_0805_10V4Z

+5VS_MB

1

C626

0.1U_0402_16V4Z

2

1

PD_D[0..15] <25>

PD_DREQ# <25> PD_IOR# <25>

PD_IOW# <25> PD_IORDY# <25>

PD_DACK# <25> PD_IRQ <25>

PD_A1 <25> PD_A0 <25>

PD_A2 <25> PD_CS1# <25> PD_CS3# <25> MB2_LED# <25>

+5VS_MB

1

2

1

C627

0.1U_0402_16V4Z

2

1

C625

0.1U_0402_16V4Z

2

ZZZ3

14

12

PLT_RST#<7,24,36>

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

SN74LVC08APW_TSSOP14

2006/09/25 2006/09/25

P

A

11

O

13

B

G

U43D

7

Compal Secret Data

Deciphered Date

PLT_RST_B#

2

PLT_RST_B# <31,35,36>

Title

Size Document Number Rev

Custom

Date: Sheet

Audio-wire

Compal Electronics, Inc.

HDD & CDROM

LA3262P_DIS__M64

1

PCB-MB

28 57Tuesday, August 21, 2007

1A

of

5

4

3

2

1

11/20 Enable ACBS (power management for NIC)

+3VM

1000P_0402_50V7K

R1613

1M_0402_5%

D D

LAN_PHYPC<26>

ADP_PRES<37,44,45,46,50>

RHU002N06_SOT323

SLP_S3#<26,32,33,37,39,40,47,48,49,50,51,52>

C C

GLAN_CLK<25>

LAN_RSTSYNC<25>

LAN_TXD0<25> LAN_TXD1<25> LAN_TXD2<25>

LAN_RXD0<25> LAN_RXD1<25> LAN_RXD2<25>

GLAN_RXP<26> GLAN_RXN<26>

GLAN_TXP<26>

R16161.4K_0402_1% R16161.4K_0402_1%

1 2

B B

1 2

R1622 649_0402_5%@ R1622 649_0402_5%@

1 2

R1623 619_0402_5%@ R1623 619_0402_5%@

A A

Y9

1 2

2

C1263

25MHZ_20P_1BG25000CK1A

25MHZ_20P_1BG25000CK1A 27P_0402_50V8J

27P_0402_50V8J

1

GLAN_TXN<26>

LED_LINK_LAN#<26,30,39> LED_ACT_LAN#<30,39>

LAN_MDI0P<30>

LAN_MDI0N<30>

LAN_MDI1P<30>

LAN_MDI1N<30>

LAN_MDI2P<30>

LAN_MDI2N<30>

LAN_MDI3P<30>

LAN_MDI3N<30>

LAN_KBIAS_P

LAN_KBIAS_N

XTAL1

XTAL2_R XTAL2

2

C1264

C1264 27P_0402_50V8J

27P_0402_50V8J

1

5

1M_0402_5%

2

G

Q104

@

Q104

@

Q105

@

Q105

@

RHU002N06_SOT323

near U74

R1615 33_0402_5%R1615 33_0402_5%

1 2

LAN_TXD0 LAN_TXD1 LAN_TXD2

LAN_RXD0 LAN_RXD1 LAN_RXD2

C490 0.1U_0402_16V4Z

1 2 1 2

C1319 0.1U_0402_16V4Z

LED_LINK_LAN# LED_ACT_LAN#

LAN_MDI0N

1 2

R1621 0_0402_5%@ R1621 0_0402_5%@

closed to E6 pin

R1625 1.4K_0603_1%R1625 1.4K_0603_1%

1 2

R1936

R1936 30_0402_5%

30_0402_5%

2007,0125 change

1 2

13

D

2

G

S

13

D

S

13

D

2

G

S

GLANCLK

GLAN_RXP_C GLAN_RXN_C

GLAN_TXP GLAN_TXN

LAN_KBIAS_P LAN_KBIAS_N

LAN_MDI0P

LAN_MDI1P LAN_MDI1N

LAN_MDI2P LAN_MDI2N

LAN_MDI3P LAN_MDI3N

IEEE_TEST_P IEEE_TEST_N

12

1 2

R1627 100_0402_5%

100K_0402_5%

100K_0402_5% Q103

Q103 BSS138_SOT23

BSS138_SOT23

R1612 0_1206_5% @R1612 0_1206_5% @

S

2

C1243

1

R1614

U74

E2

JKCLK-JCLK

E3

JRSTSYNC

D1

JTXD0

F3

JTXD1

F1

JTXD2

D3

JRXD0

D2

JRXD1

C1

JRXD2

H2

GLAN_TXP-NC

J2

GLAN_TXN-NC

J4

GLAN_RXP-NC

H4

GLAN_RXN-NC

G7

KBIAS_P-RBIAS100

H7

KBIAS_N-RBIAS10

A4

LED0-LINK_UP_N

B4

LED1-ACT_LED_N

A5

LED2-SPEED_LED_N

B8

MDI_PLUS[0]-TDP

B9

MDI_MINUS[0]-TDN

D9

MDI_PLUS[1]-RDP

D8

MDI_MINUS[1]-RDN

F9

MDI_PLUS[2]-NC

F8

MDI_MINUS[2]-NC

H8

MDI_PLUS[3]-NC

H9

MDI_MINUS[3]-NC

A7

IEEE_TEST_P-NC

B7

IEEE_TEST_N-NC

J6

RSVD_J6-NC

J7

RSVD_J7-NC

E7

RBIAS_P-NC

E6

RBIAS_N-NC

B5

RSVD_B5-NC

A6

RSVD_A6-ADV10/LAN_DIS_N

C5

RSVD_C5-NC

B6

TEST_EN

RU82566DM B0 Q870 BGA 81P

1 2

G

SI2301BDS_SOT23

2

12

R1730

R1730 0_0402_5%

0_0402_5%

T68 PADT68 PAD T70 PADT70 PAD

+3VM_LAN

1

C1242

4.7U_0603_6.3V6M

2

XTAL1 XTAL2

LCI

GLCI

MDI

1 2

R1634 200_0402_5%@ R1634 200_0402_5%@

40 mils

+3VM_LAN

H6

XTAL2-X2H5XTAL1-X1

JTAG

JTAG_TCK-ISOL_TCKG1JTAG_TDI-ISOL_TIH1JTAG_TDO-TOUTG3JTAG_TMS-ISOL_EXEC

G2

VSSA[17]-NC VSSA[16]-NC

VSSA[15]-VSSA2

VSSA[14]-VSS

VSSA[13]-NC VSSA[12]-VSS VSSA[11]-VSS VSSA[10]-VSS VSSA[09]-VSS VSSA[08]-VSS VSSA[07]-VSS VSSA[06]-VSS VSSA[05]-VSS VSSA[04]-VSS

VSSA[03]-VSSR

VSSA[02]-NC VSSA[01]-VSS

VSS[04]-VSS VSS[03]-VSSP

VSS[02]-VSS

VSS[01]-NC

VDD1P0[03]-VCCA

VDD1P0[02]-VCCT

VDD1P0[01]-VCCR

VCCF1P0-VCC

VCCFC1P0-VCC

VCC3P3[02]-VCCP

VCC3P3[01]-VCC

VCC1P8[04]-NC VCC1P8[03]-NC VCC1P8[02]-NC VCC1P8[01]-NC

VCC1P0-VCCA2

VCC[02] VCC[01]

V1P0_OUT-NC

CTRL_10-NC

CTRL_18-NC

THERM_D_P-NC THERM_D_N-NC

R1629 200_0402_5%@ R1629 200_0402_5%@

1 2

PAD

PAD PAD

PAD

2

C1245

4.7U_0603_6.3V6M

J9 J8 J5 J3 J1 G9 G8 G6 F6 E9 D6 C9 C8 C7 C6 A9 A8 F4 E1 C4 A1

F7 E8 D7

E5

H3 F2

B3

G5 F5 D5 C2

G4 E4

D4 B1

C3 B2

A2 A3

+3VM_LAN

T69

T69 T71

T71

+V1.0_LAN_M

+3.3V_LAN

+1.8VM_LAN

1 2

+V1.0_LAN_M

V1P_OUT

LAN_CTRL_10 LAN_CTRL_18

LAN_THERM_D_P LAN_THERM_D_N

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

R1618

1 2

0_0603_5%

R1619

1 2

C1611

R1620 0_0603_5%R1620 0_0603_5%

1 2

1U_0402_6.3V4Z

12

R1734

12

C1612

1 2

R1628 0_0603_5%@ R1628 0_0603_5%@

3

+3VM_LAN

+1.8VM

V1P_OUT

0_0402_5%

+V1.0M_LAN

1U_0402_6.3V4Z

+V1.0_LAN_M

2006/09/25 2006/09/25

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M C1356

C1356

Compal Secret Data

Deciphered Date

C1245

C1244

1

0.1U_0402_16V4Z

4.7U_0603_6.3V6M

2

C1250

C1249

1

0.1U_0402_16V4Z

+3VM_LAN

0.1U_0402_16V4Z

2

C1254

1

LAN_CTRL_18

+3VM_LAN +V1.0M_LAN

0.1U_0402_16V4Z

2

1

LAN_CTRL_10

0.1U_0402_16V4Z

2

C1246

1

0.1U_0402_16V4Z

2

C1251

1

2

C1255

1

C1258

BCP69_SOT223

2

C1357

1

C1360

2

C1247

1

470P_0402_50V7K

20 mils

2

C1252

1

470P_0402_50V7K

Q106

BCP69_SOT223

3

1

2

0.1U_0402_16V4Z

10N_0603_50V7K

Q128

3

1

2

0.1U_0402_16V4Z

10N_0603_50V7K

20 mils

+1.8VM_LAN

2

470P_0402_50V7K

C1248

1

+V1.0_LAN_M

2

470P_0402_50V7K

C1253

1

+1.8VM

4 2

C1256

4 2

1

2

C1257

C1257 10U_0805_10V4Z

10U_0805_10V4Z

2

1

2

1

10U_0805_10V4Z

1

2

C1359

C1358

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

Intel 82566 Nineveh

LA3262P_DIS__M64

1

1A

of

29 57Tuesday, August 21, 2007

of

29 57Tuesday, August 21, 2007

of

29 57Tuesday, August 21, 2007

D

13

Q102

4

5

T66

LAN_MDI0N

+1.8VM

LAN_MDI0P

TRM_CT

12

C330

0.1U_0402_16V4Z

D D

C327

0.1U_0402_16V4Z

C328

0.1U_0402_16V4Z

C329

0.1U_0402_16V4Z

C C

LAN_MDI1N

LAN_MDI1P TRM_CT

12

LAN_MDI2N

LAN_MDI2P TRM_CT

12

LAN_MDI3N

LAN_MDI3P TRM_CT

12

T66

12

TD4-

11

TD4+

10

TCT4

9

TD3-

8

TD3+

7

TCT3

6

TD2-

5

TD21+

4

TCT2

3

TD1-

2

TD1+

1

TCT1

24HST1041A-3_24P

C560.1U_0402_16V4Z

1 2

C540.1U_0402_16V4Z

1 2

C500.1U_0402_16V4Z

1 2

C490.1U_0402_16V4Z

1 2

Layout Notice : Place termination as close as Intel 82566 as possible

1:1

R50 49.9_0402_1%

1 2

R63 49.9_0402_1%

1 2

R45 49.9_0402_1%

1 2

R48 49.9_0402_1%

1 2

R42 49.9_0402_1%R42 49.9_0402_1%

1 2

R44 49.9_0402_1%R44 49.9_0402_1%

1 2

R40 49.9_0402_1%R40 49.9_0402_1%

1 2

R41 49.9_0402_1%R41 49.9_0402_1%

1 2

MX4+ MCT4

MX3+ MCT3

MX2+ MCT2

MX1+ MCT1

MX4-

MX3-

MX2-

MX1-

13

14 15 16

17 18 19

20 21 22

23 24

Note: MDO[3..0]+/- signals should route to JP4 first then to JP30.

R266 300_0402_5%R266 300_0402_5%

MDO3-<39> MDO3+<39> MDO1-<39> MDO2-<39> MDO2+<39> MDO1+<39> MDO0-<39> MDO0+<39>

R265 300_0402_5%R265 300_0402_5%

C1625

@C1625

@

+3VM_LAN_LED

1

2

+3VM_LAN_LED

1

C1624

@C1624

@

2

LED_ACT_LAN#<29,39>

330P_0402_50V7K

B B

LED_LINK_LAN#<26,29,39>

330P_0402_50V7K

12

LED_ACT_LAN#

MDO3MDO3+ MDO1MDO2MDO2+ MDO1+ MDO0MDO0+

12

LED_LINK_LAN#

4

MDO0-

MDO0+ MCT0

R269

75_0402_1%

MDO1-

MDO1+ MCT1

R270

75_0402_1%

MDO2-

MDO2+ MCT2

R271

75_0402_1%

MDO3-

MDO3+ MCT3

R272

75_0402_1%

JP4

13

Yellow LED+

14

Yellow LED-

8

PR4-

7

PR4+

6

PR2-

5

PR3-

4

PR3+

3

PR2+

2

PR1-

1

PR1+

11

Green LED+

12

Green LED-

FOX_JM36113-P1122-7F

conn@

RJ-45 CONN.

12

LAN_MDI0N <29> LAN_MDI0P <29> LAN_MDI1N <29> LAN_MDI1P <29> LAN_MDI2N <29> LAN_MDI2P <29> LAN_MDI3N <29> LAN_MDI3P <29>

SHLD1

DETECT PIN1

DETCET PIN2

SHLD1

1000P_1808_3KV7K

C320

1 2

1000P_1808_3KV7K

16 9

10 15

1

2

C344

1 2

CABLE_DETECT <26>

C579

0.1U_0402_16V4Z

3

LAN ENERGY DET

02/27 change

C1266 0.01U_0402_16V7KC1266 0.01U_0402_16V7K

LAN_MDI0P

LAN_MDI1P

C1267 0.01U_0402_16V7KC1267 0.01U_0402_16V7K

CAP closed to LAN_MDIO bus

MDO3- MDO1-

MDO2+

MDO2-

R55

1 2

12

10K_0402_5%

R69

12

1 2

10K_0402_5%

D73

@D73

@

1 5

2

APL5301-18BC-TRL_SOT23-5

D74

@D74

@

1 5

2

APL5301-18BC-TRL_SOT23-5

100K_0402_5%

43

MDO1+MDO3+

43

12

MDO0+

MDO0-

R1638

10P_0402_50V8J

1

C1268

2

100K_0402_5%

12

2

200K_0402_5%

R1635

ED_ACT ED_VREF

R1639

1.87K_0402_1%

12

R1636

@ R1636

@

1 3

+3VM

IN+ IN-

1.5K_0402_5%

12

R1637

5

2

U75

P

4

1 2

O

G

LMV331IDCKRG4_SC70-5~D

R51 0_0402_5%

1

C1265

0.1U_0402_16V4Z

2

1

ENERGY_DET <25>

2

G

S

G

20 mils

D

13

Q60

Q60 AO3413_SOT23

AO3413_SOT23

2

13

D

S

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/09/25 2006/09/25

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

Magnetic & RJ45/RJ11

LA3262P_DIS__M64

1

30 57Tuesday, August 21, 2007

1A

of

+3VM_LAN +3VM_LAN_LED

12

R525

A A

5

R525

100K_0402_5%

PREP#<26,32,39>

Q61

RHU002N06_SOT323

A

B/B connector with PCI / LED / FIR / SC interface

JP13

XTPA0-<34> XTPA0+<34>

CLK_PCIE_Rob#<15> CLK_PCIE_Rob<15>

PCIE_RXN4<26>

PCIE_RXP4<26>

1 1

CLK_PCI_PCM<15>

HDD_HALTLED#<26> +3VL

+1.5VS

+3VS +5VS

WL_BLUE_LED#<36,38> GREEN_BATLED#<25,37> AMBER_BATLED#<37> LED_STB#<37,38,39> IDE_LED#<25>

2 2

PM_CLKRUN#<26,35,36,37>

PCIE_RXN4 PCIE_RXP4

PCIE_TXN4<26>

PCIE_TXP4<26>

PCI_CBE#3<24>

PCI_CBE#2<24> PCI_IRDY#<24>

PCI_SERR#<24,37> PCI_PERR#<24>

PCI_CBE#1<24>

R37 0_0402_5%

R36 0_0402_5%

XTPA0-

XTPA0+

CLK_PCIE_Rob# CLK_PCIE_Rob

12 12

PCIE_TXN4 PCIE_TXP4

CLK_PCI_PCM PCI_AD31 PCI_AD29 PCI_AD27 PCI_AD25 PCI_CBE#3 PCI_AD23 PCI_AD21 PCI_AD19 PCI_AD17 PCI_CBE#2 PCI_IRDY# PM_CLKRUN# PCI_SERR# PCI_PERR# PCI_CBE#1 PCI_AD14 PCI_AD12 PCI_AD10 PCI_AD8 PCI_AD7 PCI_AD5 PCI_AD3 PCI_AD1

HDD_HALTLED# WL_BLUE_LED#

GREEN_BATLED# AMBER_BATLED# LED_STB# IDE_LED#

NF_RXN NF_RXP

0731 Install R1383 and no install R1382, do not support wake on WWAN card

0811 Isolate SLOT power from SYSTEM power.

Mini-Express Card--WWAN

+3VALW

1

C959

3 3

2

0.1U_0402_16V4Z

+3VS_WWAN

1 2

R1071 0_0603_5%R1071 0_0603_5%

1 2

R1073 0_0603_5%R1073 0_0603_5%

0821 Change +3VS to +3VS_WWAN

0811 Pins 37 and 43 connect to GND and remove +1.5VS

4 4

JP46

112 334 556 778 9910 111112 131314 151516 171718 191920 212122 232324 252526 272728 292930 313132 333334 353536 373738 393940 414142 434344 454546 474748 494950 515152

GND153GND2

MOLEX 67910-0002 52P

conn@

+3VS

R82

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52

54

1 2

0_1206_5%

WW_LED#

R82

M_WXMIT_OFF#

56

DIP155DIP2

WXMIT_OFF#<26>

JP13

1

3

5

7

7 9910 111112 131314 151516 171718 191920 212122 232324 252526 272728 292930 313132 333334 353536 373738 393940 414142 434344 454546 474748 494950 515152 535354 555556 575758 595960 616162 636364 656566 676768 696970 717172 737374 757576 777778 797980 818182 838384 858586 878788 898990

91

93

95

97

99

101

GND

ACES_88394-1A71

+3VS_WWAN

UIM_PWR UIM_DATA UIM_CLK UIM_RST UIM_VPP

1 2

R1382 0_0402_5% @R1382 0_0402_5% @

1 2

R1383 0_0402_5%R1383 0_0402_5%

USB20_N8 <26> USB20_P8 <26>

WW_LED# <36>

D66

21

CH751H-40_SC76

2

4

6

8

10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92

92

94

96

98

100

102

GND

0.01U_0402_16V7K

1

C295

2

M_WXMIT_OFF#

+3VALW +3VS_WWAN

B

XTPB0XTPB0+

PCI_PIRQG# PCI_PIRQD# PCI_REQ2# PCI_PLTRST# CLKREQ#_E PCI_PIRQE# PCI_PIRQC# PCI_RST# PCI_GNT2# SIRQ PWR_GD PCI_AD30 PCI_AD28 PCI_AD26 PCI_AD24 PCM_SPK PCI_AD22 PCI_AD20 PCI_PAR PCI_AD18 PCI_AD16 PCI_FRAME# PCI_TRDY# PCI_STOP# PCI_DEVSEL# PCI_AD15

PCI_AD13 PCI_AD11 PCI_AD9 PCI_CBE#0 PCI_AD6 PCI_AD4 PCI_AD2 PCI_AD0

IRRX IRTXOUT IRMODE

SC_CD# SC_CLK

SC_RST SC_DATA

PCI_AD[0..31]

1

C540

2

0.1U_0402_16V4Z

1 2

UIM_PWR

XTPB0- <34> XTPB0+ <34>

PCI_PIRQG# <24> PCI_PIRQD# <24>

PCI_REQ2# <24>

PCI_PLTRST# <24>

CLKREQ#_E <15,19> PCI_PIRQE# <24> PCI_PIRQC# <24>

PCI_RST# <24,28>

PCI_GNT2# <24> SIRQ <26,35,36,37> PWR_GD <21,26,37,40,41,49,50>

PCM_SPK <32>

PCI_PAR <24>

PCI_FRAME# <24> PCI_TRDY# <24> PCI_STOP# <24> PCI_DEVSEL# <24>

PCI_CBE#0 <24>

IRRX <35> IRTXOUT <35> IRMODE <35>

SC_CD# <34> SC_CLK <34>

SC_RST <34> SC_DATA <34>

+3VS_WWAN

4.7U_0805_10V4Z

1

C544

2

U72

1

CH1

CH4

2

Vn

Vp

CH23CH3

S DIO(BR) NUP4301MR6T1 TSOP-6

JP50

4

GND

5

VPP

6

I/O

7

DET

R1923

@ R1923

@

10K_0402_5%

TAITW_PMPAT6-06GLBS7N14N0

0915 Change 1394 signals

0622 change to support AMT

+3VS

+SC_PWR

PCI_AD[0..31] <24>

6 5 4

1

VCC

2

RST

UIM_CLKUIM_DATA

3

CLK

4.7U_0805_10V4Z

8

GND

9

GND

+3VS

UIM_PWR UIM_RSTUIM_VPP

C554

1

2

C

DAN217_SC59

D13

@D13

@

1

C960

2

0.1U_0402_16V4Z

2007,0125 change

0811 Reserve for SIM card does not meet rise time and a pull-up resistor is needed.

Mini-Express Card---WLAN

0.01U_0402_16V7K

0.1U_0402_16V4Z

1

C538

2

4.7U_0805_10V4Z

ICH_PCIE_WAKE#<26>

CLK_PCIE_MCARD#<15>

CLK_PCIE_MCARD<15>

CLK_DEBUG_PORT<15,36>

0821 Change +3VS to +3VS_WLAN

+3VS_WLAN

1

C542

2

CH_DATA<34>

CH_CLK<34>

CLKREQ#_G<15>

PCIE_RXN2<26> PCIE_RXP2<26>

PCIE_TXP2<26>

CL_CLK1<26> CL_DATA1<26> CL_RST#1<26>

0627 PIN37,43 connected to GND PIN39,41 connected to +3VS

0811 No install R1418,R1358,R1359,R1360 0906 Remove debug resistors

ACCELEROMETER

ACCEL_INT<24>

+3VS

3 2

ICH_SM_DA<4,19,23,26>

+3VS_ACL_IO +3VS_ACL

ICH_SM_CLK<4,19,23,26>

+3VS_ACL

0619 Follow ST Demo circuit

0.01U_0402_16V7K

1

C293

2

ICH_PCIE_WAKE# CH_DATA CH_CLK

1 2

CLK_PCIE_MCARD# CLK_PCIE_MCARD

0906 Remove debug resistors

PCIE_RXP2

PCIE_TXN2 PCIE_TXP2

0313 change design

0_0402_5%

R1336 0_0402_5%R1336 0_0402_5%

R1348 0_0402_5%R1348 0_0402_5%

1 2 1 2

R1349 0_0402_5%R1349 0_0402_5%

R197 0_0402_5%R197 0_0402_5% R195 0_0402_5%R195 0_0402_5% R194 0_0402_5%R194 0_0402_5%

10K_0402_5%

R1359

R1391

12 12 12

XMIT_OFF<26>

+3VS +3VS_ACL

1 2

2 1

CH751H-40_SC76

U64

1

INT/RDY

2

SDD

3

SDA/SDI/SPC

4

VDD_IO

5

SCL/SPC

6

12

CS

7

NC

8

CK

Must be placed in the center of the system.

1 2

D

C294

0.1U_0402_16V4Z

CLKREQD#_MC

PCIE_C_RXN2PCIE_RXN2 PCIE_C_RXP2

+3VS_WLAN

R1355

0_0805_5%@

D64

+1.5VS_WLAN

4.7U_0805_10V4Z

1

2

C533

JP44

112 334 556 778 9910 111112 131314 151516 171718 191920 212122 232324 252526 272728 292930 313132 333334 353536 373738 393940 414142 434344 454546 474748 494950 515152

GND153GND2

MOLEX 67910-0002 52P

D72

CH751H-40_SC76

0811 HP request

R1356

1 2

0_0603_5%

16

GND

15

RES

14

GND

13

VDD

12

RES

11

VDD

10

RES

9

GND

LIS3LV02DL-TR _LGA16

1

2

0.1U_0402_16V4Z

0821 Install R1364

56

conn@

2 4

DIP155DIP2

6 8 10 12 14 16 18

XMIT_OFF#

20 22 24 26 28 30 32 34 36 38 40

WW_LED#_R

42

WL_LED#

44

WP_LED#_R

46 48 50 52

54

10K_0402_5%@

21

RHU002N06_SOT323@

+3VS_ACL_IO

0.01U_0402_16V7K@

1 2

0_0402_5%

R1357

1 2

E

0824 Add +1.5VS_WLAN 0811 Isolate SLOT power from SYSTEM power.

1

2

+3VS

+1.5VS

+3VS_WLAN +1.5VS_WLAN

1 2

0_1206_5%

+1.5VS_WLAN

R71

1 2

0_1206_5%

R72

+3VS_WLAN

C954

+3VALW

0906 Remove debug resistors

0_0402_5%

R1364 0_0402_5%@R1364 0_0402_5%@

0_0402_5%

1 2 1 2

R1363

0612 change power plane

WW_LED#

1 2

WP_LED#

1 2

0627 Add 0 ohm on PIN 42,46

+3VALW

12

R517

12

R516

Q58

R1422 0_0402_5%R1422 0_0402_5%

R1361

1 2

0_0402_5%

R1362

2

G

1 2

C994

100K_0402_5%@

XMIT_OFF#

13

D

S

1

C995

2

0.1U_0402_16V4Z

+3VS_ACL

PLT_RST_B# <28,35,36> +3VALW +3VM

ICH_SMB_CLK <26> ICH_SMB_DATA <26>PCIE_TXN2<26>

WW_LED# <36>

WL_LED# <36>

WP_LED# <36>

+3VS_ACL

1

C996

C996 10U_0805_10V4Z

10U_0805_10V4Z

2

R1754

@R1754

@

0_0402_5%

R1913

@R1913

@

0_0402_5%

0619 Follow ST Demo circuit

0_0402_5%

+3VS_ACL_IO

0821 Delete SW1,C986,R521,D65,R200

A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2006/09/25 2006/09/25

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

D

Date: Sheet

Compal Electronics, Inc.

Mini-Card/Mini-PCI/Accelerometer

LA3262P_DIS__M64

E

of

31 57Tuesday, August 21, 2007

of

31 57Tuesday, August 21, 2007

of

31 57Tuesday, August 21, 2007

1A

A

B

C

D

E

F

G

H

VDDA_CODEC

12

R329

R329 10K_0402_5%

10K_0402_5%

C390

1 2

13

D

0.1U_0402_16V4Z

2

PCM_SPK<31>

1 1

SB_SPKR<26>

2 2

Q35

RHU002N06_SOT323

Q68

RHU002N06_SOT323

Place close to U14

R1400

0_1206_5%

C409 0.1U_0402_16V4ZC409 0.1U_0402_16V4Z

C427 0.1U_0402_16V4ZC427 0.1U_0402_16V4Z

C431 0.1U_0402_16V4ZC431 0.1U_0402_16V4Z

G

VDDA_CODEC

2

G

12

S

12

R350

R350 10K_0402_5%

10K_0402_5%

13

D

0.1U_0402_16V4Z

S

C396

1 2

GNDAGND

DLINE_IN_L<39>

DLINE_IN_R<39>

3 3

VDDA_CODEC

1 2

SENSE_A

4 4

SENSE_B

R980

0_0402_5%@

1 2

A

2

1

R341

1 2

150K_0402_1%

R359

1 2

150K_0402_1%

R370 6.04K_0402_5%R370 6.04K_0402_5% R375 2K_0402_5%R375 2K_0402_5% R369 6.04K_0402_5%R369 6.04K_0402_5% R374 2K_0402_5%R374 2K_0402_5%

2007,0125 change

R969

2.67K_0402_1%

1 2

R970 39.2K_0402_1%

1 2

R972 20K_0402_1%

1 2

R973 10K_0402_1%

C977

1U_0402_6.3V4Z@

1 2 1 2

2N7002_SOT23

B

10K_0402_5%

R330

INT_MIC<33>

12 12

SENSE_A_C

Q97

12

C430 0.1U_0402_16V4ZC430 0.1U_0402_16V4Z

2

C377

0.01U_0402_16V7K

1

V_CODEC +3VS

1 2

INT_MIC

DLINE_IN_R_L DLINE_IN_R_R

MIC1<33> MIC2<33>

VDDA_CODEC

HDA_RST#_CODEC<25>

HDA_SYNC_CODEC<25>

HDA_SDOUT_CODEC<25>

SENSE_A_A <33>

SENSE_A_B <33>

13

D

2

G

S

R988

1 2

100K_0402_5%

VDDA_CODEC

0_0603_5%

R159

1

C147

C395

0.1U_0402_16V4Z

2

0.1U_0402_16V4Z

C425 1U_0603_10V4ZC425 1U_0603_10V4Z

1 2

C426 1U_0603_10V4ZC426 1U_0603_10V4Z

1 2

C423 1U_0603_10V4ZC423 1U_0603_10V4Z

1 2

C422 1U_0603_10V4ZC422 1U_0603_10V4Z

1 2

MIC2 MIC2_C

R231 2.2K_0402_1%

R231 2.2K_0402_1% R169 0_0402_5%@R169 0_0402_5%@

EAPD<33,37>

VDDA_CODEC

R974

0_0402_5%@

1 2

LINE_IN_SENSE

1

C978

0.1U_0402_16V4Z

2

C

0.1U_0402_16V4Z

1

C148

2

T24 PADT24 PAD T21 PADT21 PAD

DLINE_IN_RC_L DLINE_IN_RC_R

T23 PADT23 PAD T25 PADT25 PAD T26 PADT26 PAD

MIC1_CMIC1

SENSE_A

SENSE_B

1 2

LINE_IN_SENSE <39>

0.1U_0402_16V4Z

1

2

10U_0805_10V4Z

0.1U_0402_16V4Z

1

C417

2

1 2

C204 1U_0603_10V4ZC204 1U_0603_10V4Z

1 2

C205 1U_0603_10V4ZC205 1U_0603_10V4Z

1 2 1 2

L53

L53 FBM-L10-160808-301-T_0603

FBM-L10-160808-301-T_0603

T22 PADT22 PAD

C402

MONO_IN

1 2

+5VAMP

1

+

2

1

U14

AVDD125AVDD2

14

AUX_L

15

AUX_R

16

MIC3

17

MIC4

23

LINE_IN_L

24

LINE_IN_R

18

CD_L

20

CD_R

19

CD_GND

21

MIC1

22

MIC2

13

SENSEA

34

SENSEB

11

RESET#

10

SYNC

5

SDATA_OUT

47

EAPD

48

SPDIFO

4

DVSS1

7

DVSS2

AD1981HDJSTZ-REEL_LQFP48

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

D

C548

C548 22U_B_10V

22U_B_10V

38

2

C552

C552 1U_0603_10V4Z

1U_0603_10V4Z

1

DVDD11DVDD2

LINE_OUT_L

LINE_OUT_R

MONO_OUT HP_LOUT_L HP_LOUT_R

BIT_CLK

SDATA_IN

GPIO_0 GPIO_1 GPIO_2 GPIO_3

VREF

MIC_BIAS_B MIC_BIAS_C MIC_BIAS_F MIC_BIAS_D

PCBEEP

AVSS1 AVSS2

N/C N/C N/C

NC NC

SLP_S3#<26,29,33,37,39,40,47,48,49,50,51,52>

2

C551

C551 100P_0402_50V8J

100P_0402_50V8J

1

1 2

R258

0_0805_5%

U18

1

IN

5

OUT

3

EN

4

ADJ

2

GND

MIC5205BM5_SOT23-5

0.01U_0402_16V7K

Place R258 between DGND & AGND & close to U14

4.7U_0603_6.3V6M

1 2

+5VS

300K_0402_5%

1 2

+3VS

10K_0402_5%

HDA_RST#_MDC<25,38>

R1399

0.1U_0402_16V4Z

9

35 36 37 39 41

6 8

43 44 2 3

27 28

29 30 32 12

31 33 40 45 46

26 42

2006/09/25 2006/09/25

+3VS_CODEC

1

C175

C156

E

C175

2

0.1U_0402_16V4Z

LINE_OUTL LINE_OUTR

L_HP R_HP

R1038 33_0402_5% @R1038 33_0402_5% @

HDA_SDIN0_CODEC

R168 4.7K_0402_5%@R168 4.7K_0402_5%@

1 2

R167 4.7K_0402_5%@R167 4.7K_0402_5%@

1 2

R136 10K_0402_5%

1 2

R32 4.7K_0402_5%@R32 4.7K_0402_5%@

1 2

AUD_REF

T27

T27 T13

T13 T12

T12 T11

T11

MONO_IN

T7 PADT7 PAD T8 PADT8 PAD T10 PADT10 PAD T6 PADT6 PAD T9 PADT9 PAD

Compal Secret Data

1 2

0_0805_5%

1

C393

C393 10U_0805_10V4Z

10U_0805_10V4Z

2

T20

12

R373

33_0402_5%

PAD

PAD PAD

PAD

Deciphered Date

R1399

LINE_OUTL <33> LINE_OUTR <33>

PAD

L_HP <33> R_HP <33>

C1064

HDA_BITCLK_CODEC <25>

12

F

V_CODEC

2

C553

1

C4

@C4

@

1 2

R61

@R61

@

R62

@R62

@

2

G

1 2

1K_0402_5%

R70

@R70

@

1 2

HDA_SDIN0 <25>

PORT_A_SNS <33>

PREP# <26,30,39>

1

C424

C424 1U_0603_10V4Z

1U_0603_10V4Z

2

12

R456

49.9K_0402_1%

12

R457

R457 143K_0402_1%

143K_0402_1%

13

D

RHU002N06_SOT323

Q140

@

Q140

@

S

1

C3

0.47U_0402_10V4Z~D

2

@

10P_0402_25V8K@

1

C416

0.1U_0402_16V4Z

2

1

+

2

Size Document Number Rev

Date: Sheet

C309

C309 22U_B_10V

22U_B_10V

2

10K_0402_5%

@

R57

RHU002N06_SOT323

R1915

10K_0402_5%

@

Title

G

C307

0.1U_0402_16V4Z

R35

0_0402_5%

12

@

12

PORT MONO_OUT PORT A PORT B PORT C PORT D PORT E PORT F

Compal Electronics, Inc.

AC97 CODEC AD1981B

0_0402_5%

S

D

S

D

S

1 3

Q138RHU002N06_SOT323

@

Q141

2 2

1 3

D

G

R1916

G

S

0_0402_5%

PLACE TO X HP OUT, DOCK HP LO M/B MIC DOCK LI M/B SPK X Internal MIC

LA3262P_DIS__M64

@

12

1 2

D

13

Q139

@

Q139

@

RHU002N06_SOT323

2 2

RHU002N06_SOT323

Q142

@

Q142

@

13

D

12

1 2

R1917

@

R1914

10K_0402_5%

32 57Tuesday, August 21, 2007

H

10K_0402_5%

HP_R_JACK <33>R_C_HP<33>

HP_L_JACK <33>L_C_HP<33>

of

1A

A

B

C

D

E

AMP. FOR INTERNAL SPEAKER

1

+

C662

2

5

INR

1

INL

4

MUTE

14

SHDN

C493

1

C536

2.2U_0603_6.3V4Z

2

CHB1608B121_0603

1 2

L52

L51

1 2

470P_0402_50V7K

J_MIC1 J_MIC2

+5VAMP

12

8

18

VDD

PVDD1

PGND1

PGND211PGND315PGND4

6

VDDA_CODEC

12

47K_0402_5%

12

2

47K_0402_5%

1

R255

1 2

100K_0402_5%

C563

J_MIC_REF

B

C659

C659 10U_0805_10V4Z

10U_0805_10V4Z

1

2

1U_0603_10V4Z

U39

BIAS

PVDD2

OUTR+

OUTR-

OUTL+

OUTL-

NC1 NC2 NC3 NC4

PGND5

MAX9710ETP_QFN20

20

21

R426

R428

VDDA_CODEC

R_CRL_HP

L_CRL_HP

1

2

ACES_87213-0600

1

C660

C539

0.1U_0402_16V4Z

2

C1044 1U_0603_10V4ZC1044 1U_0603_10V4Z

2

7 9

19 17

3 10 13 16

VDDA_CODEC

5 6

12

R251

R251 100K_0402_5%

100K_0402_5%

1

C526

@C526

@

1U_0603_10V4Z

2

1

C564

C564 470P_0402_50V7K

470P_0402_50V7K

2

R1405

R_SPK+ R_SPK-

R1406

L_SPK+ L_SPK-

8

P

+

O

-

G

U27B

TLV2462_SO8

4

DLINE_OUT_L<39> DLINE_OUT_R<39>

DLINE_OUT_L

1 2

15K_0402_5%

1 2

15K_0402_5%

MIC_REF

R978

100_0402_5%

1 2

7

VDDA_CODEC

5 4 3

6 2 1

SUYIN_010030FR006G101ZL_6P

Place close to JP24

JP28

conn@ JP28

conn@

1 2 3 4 5 6

1 2 3

J_DLINE_OUT_L

4

J_DLINE_OUT_R

5 6

J_R_HP J_L_HP

J_VDDA_CODEC

Keep 10 mil width

LINE_C_R_OUTR

10 dB

LINE_C_R_OUTL

10 dB

C471

0.01U_0402_16V7K

1 2

C982

1

4.7U_0805_10V4Z

2

conn@

MIC1

MIC1<32> MIC2<32> MIC_REF

R_HP<32> L_HP<32>

MIC_SENSE

conn@

1 2

MIC2

3 4 5 6

R_HP

7

L_HP

8

9 10 11 12

ACES_87213-1200

JP24

8 7

Place close to U14

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

+5VALW

R443

1 2

0_1206_5%

C1098

10U_0805_10V4Z

1 1

C503

LINE_C_OUTR

LINE_OUTR<32>

LINE_OUTL<32>

2 2

1 2

0.1U_0402_16V4Z

0.1U_0402_16V4Z C502

C502

1 2

0.1U_0402_16V4Z

MUTE_LED#

EAPD<32,37>

A_SD<37>

SLP_S3#<26,29,32,37,39,40,47,48,49,50,51,52>

Place close to U14 audio CODEC

PORT_A_SNS<32>

SENSE_A_A<32>

RHU002N06_SOT323

150U_D_6.3VM

+

1 2

C577

+

1 2

C581

150U_D_6.3VM

S DIO(BR) NUP4301MR6T1 TSOP-6@

L_SPK+ L_SPKR_SPK+ R_SPK-

C506

100P_0402_50V8J

DOCK_HPS#<39>

1 2

100P_0402_50V8J

1

C514

2

3 3

J_R_HP J_L_HP

4 4

Q49

J_DLINE_OUT_R J_DLINE_OUT_L

R_C_HP <32> L_C_HP <32>

U73

CH1

CH4

Vn

Vp

CH23CH3

1

C507

2

100P_0402_50V8J

13

D

S

0.1U_0603_50V4Z

HP_R_JACK<32>

HP_L_JACK<32>

6 5 4

1

2

A

10 dB

R1410

1 2

10K_0402_5%

R1411

1 2

10K_0402_5%

10 dB

R430 10K_0402_5%R430 10K_0402_5%

1 2

12

R1421 0_0402_5%@R1421 0_0402_5%@

Q28

RHU002N06_SOT323@

RHU002N06_SOT323

VDDA_CODEC

12

R995

100K_0402_5%

Q48

13

D

RHU002N06_SOT323

2

G

S

2

G

1

C527

2

+3VS

JP21

conn@JP21

conn@

1

2

3

4

1

C518

E&T_3801-04

100P_0402_50V8J

2

Q44

RHU002N06_SOT323

R261

1 2

60.4_0805_1%

R253

1 2

60.4_0805_1%

R445

1K_0402_1%

ACES_87213-0600

Place close to JP15

0_1206_5%

1

2

150U_D_6.3VM

LINE_C_R_OUTR

LINE_C_R_OUTLLINE_C_OUTL

R1407

12

0_0402_5%

13

D

2

G

S

13

D

2

G

Q32

S

VDDA_CODEC

12

R423

R423 100K_0402_5%

100K_0402_5%

13

D

2

G

S

R_CR_HP

L_CR_HP

Place close to JP24

12

R446

R446 1K_0402_1%

1K_0402_1%

JP27

conn@ JP27

conn@

1

2

3

4

5

6

@

4.7U_0805_10V4Z

CHB1608B121_0603

J_MIC_SENSE

AMP. FOR INTERNAL MICROPHONE

Place close to U14 audio CODEC

conn@

JP36

INT_MIC_2

1 2

ACES_85205-0200

VDDA_CODEC

R196

1 2

3K_0402_5%

AMP. FOR EXTERNAL MICROPHONE

D62

2 3

@

PACDN042_SOT23~D

C585

1 2

1200P_0402_50V7K@

R193

1 2

C226

1

4.7U_0805_10V4Z

2

1

3K_0402_5%

HLC0603CSCCR11JT_0603

C231

INT_MIC_3INT_MIC_1 INT_MIC_4

1 2

0.22U_0603_10V7K

1 2

68P_0402_50V8J

Place close to JP15

C276

JP9

1 2 3 4 5 6 7 8 9 10 11 12

C

EXT_MICA

4.7U_0805_10V4Z

EXT_MICB

SENSE_A_B<32>

RHU002N06_SOT323

J_VDDA_CODEC

2006/09/25 2006/09/25

C276

1 2

0.22U_0603_10V7K

J_VDDA_CODEC

R427

47K_0402_5%

2

C492

1

C275

1 2

0.22U_0603_10V7K

VDDA_CODEC

D

Q50

S

EXT_MICA_1

12

R429

47K_0402_5%

EXT_MICB_1

13

2

G

Compal Secret Data

L58

1 2

HLC0603CSCCR10JT_0603

R1424 0_0402_5%R1424 0_0402_5%

R1423 0_0402_5%@R1423 0_0402_5%@

L61

1 2

HLC0603CSCCR10JT_0603

R979

R979 47K_0402_5%

47K_0402_5%

1 2

MIC_SENSE

2

C984

0.1U_0402_16V4Z

1

R418

1 2

470_0402_5%

1 2

R425

470_0402_5%

C487

10U_0805_10V4Z

Deciphered Date

1

2

12

R424

3.9K_0402_1%

1 2

R421

3.9K_0402_1%

C486

C486 10U_0805_10V4Z

10U_0805_10V4Z

D

C572

1

68P_0402_50V8J

2

JJ_MIC_REF

J_MIC_REF

1

C575

C575 68P_0402_50V8J

68P_0402_50V8J

2

EXT_MICB

EXT_MICA

1 2

L57

C571

R211

10K_0402_5%

R210

10K_0402_5%

C230

1 2

680P_0402_50V7K

R190

MIC_REF

C446

100P_0402_50V8J

R388

1 2

1

10K_0402_5%

2

JJ_MIC_REF

C249

EXT_MICA_2

JJ_MIC_REF

C248

EXT_MICB_2

1 2

L46

CHB1608B121_0603

1 2

L47

CHB1608B121_0603

470P_0402_50V7K

100P_0402_50V8J

J_VDDA_CODEC

1

2

100P_0402_50V8J

3 2

1

2

100P_0402_50V8J

5 6

1

C470

0.1U_0402_16V4Z

2

J_MIC_SENSE

C508

Title

Size Document Number Rev

Date: Sheet

VDDA_CODEC

1

2

+

-

J_VDDA_CODEC

+

-

1

2

Compal Electronics, Inc.

8

3

+

2

-

4

100P_0402_50V8J

U46A

8

TLV2462_SO8

P

1

O

G

4

100P_0402_50V8J

U46B

8

TLV2462_SO8

P

7

O

G

4

1

C522

C522 470P_0402_50V7K

470P_0402_50V7K

2

AMP & Audio Jack

LA3262P_DIS__M64

1 2

100K_0402_5%

1

C441

2

0.1U_0402_16V4Z

U27A

TLV2462_SO8

P

INT_MIC

1

O

G

C488

1 2

R413

1 2

100K_0402_5%

J_MIC1

C489

1 2

R414

1 2

100K_0402_5%

J_MIC2

5 4 3

6 2 1

SUYIN_010030FR006G101ZL_6P

E

33 57Tuesday, August 21, 2007

INT_MIC <32>

JP15

conn@

of

8 7

1A

5

4

3

2

1

Left side USB CONNECTOR 0

Left side USB CONNECTOR 1

U57

1

GND

2

D D

4.7U_0805_10V4Z

C550

S4_STATE

1

2

IN

3

IN

4

EN#

G548A2P1U

OUT OUT OUT OC#

8 7 6 5

R163

1

+

C567

2

150U_D_6.3VM

1 2

10K_0402_5%

USB_VCCA+5VALW USB_VCCA

JP23

conn@JP23

W=100mils

1

C515

2

+5VALW

1 2 1 2

0_0805_5%

R73

R6040_0603_5% R6040_0603_5%

USB20_P4_R

R6050_0603_5% R6050_0603_5%

12

0904 change for EMI

USB20_P4 USB20_N4

D52

USB20_N4 USB20_P4

3

1

2

1000P_0402_50V7K

USB20_N4<26> USB20_P4<26>

PJDLC05_SOT23~D

1

C519

2

0.1U_0402_16V4Z

conn@

1

2

3

4

5

GND

6

GND

7

GND

8

GND

SUYIN_020173MR004S558ZL

12

R56

0_0805_5%

SUYIN_020173MR004S558ZL

JP25

conn@JP25

conn@

GND GND GND GND

1

USB20_N5_R

2

USB20_P5_R

3

4

5 6 7 8

0904 change for EMI

1 2 1 2

12

R4

R4 0_0805_5%

0_0805_5%

R6060_0603_5% R6060_0603_5%

USB20_N5USB20_N4_R USB20_P5

R6070_0603_5% R6070_0603_5%

PJDLC05_SOT23~D

USB20_N5 <26> USB20_P5 <26>

USB20_P5 USB20_N5

D51

2

3

1

Right side USB CONNECTOR 0

+5VALW

U65

1

S4_STATE

Q132

2 3 4

2

G

GND IN IN EN#

TPS2061IDGN_MSOP8~N

+5VALW

12

10K_0402_5%

13

D

S

C C

1

C558

4.7U_0805_10V4Z

S4_STATE<36>

B B

S4_STATE#<26>

RHU002N06_SOT323

2

8

OUT

7

OUT

6

OUT

5

OC#

R1

R164

1

+

C569

2

150U_D_6.3VM

1 2

10K_0402_5%

SMART Card connector

W=60mils

1

2

USB_VCCC

C517

0.1U_0402_16V4Z

+5VALW

JP26

conn@JP26

R6170_0603_5% R6170_0603_5%

USB20_N0_R

1

C521

2

1000P_0402_50V7K

USB20_N0<26> USB20_P0<26>

1 2 1 2

PJDLC05_SOT23~D

+SC_PWR

USB20_P0_R

R6140_0603_5% R6140_0603_5%

USB20_P0 USB20_N0

D61

conn@

1

2

3

4

5

GND

6

GND

7

GND

8

GND

SUYIN_020173MR004S558ZL

2

3

1

1394 connector

XTPB0-<31> XTPB0+<31> XTPA0-<31> XTPA0+<31>

conn@JP22

conn@

XTPB0+ XTPA0-

JP22

1 2 3 4 5 6 7 8

ACES_87212-0800

BT Connector

JP3

conn@JP3

conn@ 1 2 3 4 5 6 7 8 9

10

A A

11

1

11

12

2

12

13

3

13

14

4

14

15

5

15

16

6

16

17

7

17

18

8

18

19

9

19

20

10

20

ACES_85203-1002

SC_CLK SC_RST

SC_CD#

SC_DATA

SC_CLK <31> SC_RST <31> +SC_PWR SC_CD# <31>

SC_DATA <31>

1

C367

0.1U_0402_16V4Z

2

1

C306

C306 1U_0603_10V4Z

1U_0603_10V4Z

2

BT_OFF<26>

11/06 fix DB2 1394 can not detect issue

2007,0125 change

R16970_0402_5%

1 2

R16960_0402_5%

1 2

R16990_0402_5%

1 2

R16980_0402_5%

1 2

R562

0_0402_5%

USB20_P6_R USB20_N6_R

R458 1K_0402_5%@R458 1K_0402_5%@

1 2

R459 1K_0402_5%@R459 1K_0402_5%@

1 2

12

R518

R518 100K_0402_5%

100K_0402_5%

R454

1 2

47K_0402_5%

0_0402_5%

12

0_0402_5%

12

R586

2

3

D53

PACDN042_SOT23~D@

1

Q51 SI2301BDS_SOT23

S

D

13

G

2

0.01U_0402_16V7K

1 2

1

C546

2

C556

0.1U_0402_16V4Z

R_XTPB0-XTPB0-

R_XTPB0+

R_XTPA0-

R_XTPA0+XTPA0+

+3VAUX_BT

USB20_P6 USB20_N6

BT_LED <36> CH_DATA <31>

CH_CLK <31>

1

C545

0.1U_0402_16V4Z

2

+3VAUX_BT+3VALW

conn@

JP19

1

XTPB0-

2

XTPB0+

3

XTPA0-

4

XTPA0+

5

GND

6

GND

7

GND

8

GND

AMP_440168-2

USB20_P6 <26> USB20_N6 <26>

1

C549

4.7U_0805_10V4Z

2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/09/25 2006/09/25

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

USB & BT Connector

LA3262P_DIS__M64

34 57Tuesday, August 21, 2007

1

1A

of

A

B

C

D

E

1 1

DCD#1 RI#1 CTS#1 DSR#1

4.7K_1206_8P4R_5%

IRRX

R76

R76 1K_0402_5%

1K_0402_5%

U8

LPC_AD0<25,36,37> LPC_AD1<25,36,37> LPC_AD2<25,36,37>

RP6

SIO_GPIO12

18

SIO_GPIO10

27

SIO_GPIO44

36

SIO_GPIO43

2 2

3 3

10K_1206_8P4R_5%

+3VS

R120

1 2

R121

1 2

R119

1 2

10K_0402_5%

R68

1 2

10K_0402_5%

R77

1 2

10K_0402_5%

R79

1 2

10K_0402_5%

R80

1 2

10K_0402_5%

R100

1 2

10K_0402_5%

45

SIO_IRQ

10K_0402_5%

SIO_DPIO45

10K_0402_5%

CARD_ID#

PID0

PID1

SIO_GPIO11

SIO_GPIO40

NPCI_RST#<26,37>

PLT_RST_B#<28,31,36>

+3VS

R108 0_0402_5%R108 0_0402_5%

1 2

R109 0_0402_5%@ R109 0_0402_5%@

1 2

R99 10K_0402_5%R99 10K_0402_5%

1 2

+3VS

R67 10K_0402_5%R67 10K_0402_5%

LPC_AD3<25,36,37>

LPC_FRAME#<25,36,37>

LPC_DRQ#0<25>

PM_CLKRUN#<26,31,36,37>

CLK_PCI_SIO<15>

SIRQ<26,31,36,37>

CLK_14M_SIO<15>

SER_SHD<39>

EXPCRD_RST#<39>

LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3

LPC_FRAME# LPC_DRQ#0

SIO_RST# SIO_PD#

PM_CLKRUN# CLK_PCI_SIO SIRQ SIO_PME#

CLK_14M_SIO SIO_GPIO40

PID0 PID1 SIO_GPIO43 SIO_GPIO44 SIO_DPIO45 CARD_ID# SER_SHD SIO_GPIO10 SIO_GPIO11 SIO_GPIO12 SIO_IRQ

U8

10

LAD0

12

LAD1

13

LAD2

14

LAD3

15

LFRAME#

16

LDRQ#

17

PCI_RESET#

18

LPCPD#

19

CLKRUN#

20

PCI_CLK

21

SER_IRQ

6

IO_PME#

9

CLK14

CLOCK

23

GPIO40

24

GPIO41

25

GPIO42

27

GPIO43

28

GPIO44

29

GPIO45

30

GPIO46

31

GPIO47

32

GPIO10

33

GPIO11/SYSOPT

34

GPIO12/IO_SMI#

35

GPIO13/IRQIN1

36

GPIO14/IRQIN2

40

GPIO23

8

VSS

22

VSS

43

VSS

52

VSS

LPC47N217_STQFP64

Base I/O Address

0 = 02Eh 1 = 04Eh*

CLK_PCI_SIO

12

R96

10_0402_5%@

1

C94

C94 18P_0402_50V8J

18P_0402_50V8J

@

2

LPC I/F

GPIO

POWER

RP3

1 8 2 7 3 6 4 5

1 2

SERIAL I/F

DCD1#

FIR

IRMODE/IRRX3

SLCTIN#

PARALLEL I/F

ERROR#

STROBE#

CLK_14M_SIO

12

R81

R81 10_0402_5%@

10_0402_5%@

1

C70

C70 10P_0402_25V8K

10P_0402_25V8K

@

2

RXD1

TXD1 DSR1# RTS1# CTS1# DTR1#

RI1#

IRRX2 IRTX2

INIT#

SLCT

BUSY

ACK#

ALF#

VCC VCC VCC VCC

+3VS

PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7

VTR

PE

62 63 64 1 2 3 4 5

37 38 39

41 42 44 46 47 48 49 50 51 53 55 56 57 58 59 60 61

7 11 26 45 54

RXD1 TXD1 DSR#1 RTS#1 CTS#1 DTR#1 RI#1 DCD#1

IRRX

LPTINIT# LPTSLCTIN# LPD0 LPD1 LPD2 LPD3 LPD4 LPD5 LPD6 LPD7 LPTSLCT LPTPE LPTBUSY LPTACK# LPTERR# LPTAFD# LPTSTB#

1

C84

2

0.1U_0402_16V4Z

RXD1 <39>

R64 1K_0402_5%R64 1K_0402_5%

1 2

TXD1 <39> DSR#1 <39> RTS#1 <39> CTS#1 <39> DTR#1 <39> RI#1 <39> DCD#1 <39>

IRRX <31> IRTXOUT <31> IRMODE <31>

LPTINIT# <39> LPTSLCTIN# <39> LPD0 <39> LPD1 <39> LPD2 <39> LPD3 <39> LPD4 <39> LPD5 <39> LPD6 <39> LPD7 <39> LPTSLCT <39> LPTPE <39> LPTBUSY <39> LPTACK# <39> LPTERR# <39> LPTAFD# <39> LPTSTB# <39>

1

C76

C88

2

0.1U_0402_16V4Z

4.7U_0805_10V4Z

+5VS

21

D36

D36 CH751H-40_SC76

CH751H-40_SC76

+5VS_PRN

RP51

LPD3 LPD2 LPD1 LPD0

LPD7 LPD6 LPD5 LPD4

LPTACK# LPTBUSY LPTPE LPTSLCT

LPTSTB# LPTAFD# LPTERR#

LPTSLCTIN#EXPCRD_RST#EXPCRD_RST#

+3VS

1

C57

2

LPTINIT#

RP51

1 8 2 7 3 6 4 5

4.7K_1206_8P4R_5%

4.7K_1206_8P4R_5% RP52

RP52

1 8 2 7 3 6 4 5

4.7K_1206_8P4R_5%

4.7K_1206_8P4R_5% RP53

RP53

1 8 2 7 3 6 4 5

4.7K_1206_8P4R_5%

4.7K_1206_8P4R_5% RP54

RP54

1 8 2 7 3 6 4 5

4.7K_1206_8P4R_5%

4.7K_1206_8P4R_5% R480

R480

1 2

4.7K_0402_5%

4.7K_0402_5% R481

R481

1 2

4.7K_0402_5%

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2006/09/25 2006/09/25

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

D

Date: Sheet

Compal Electronics, Inc.

SUPER I/O LPC47N217

LA3262P_DIS__M64

35 57Tuesday, August 21, 2007

E

1A

of

5

4

3

2

1

BIOS ROM

2007,0125 change

D D

20mils

R1288

1 2

+3VM

12

SPI_WP#

12

C C

R1287

3.3K_0402_5%

R1724

@R1724

@

0_0402_5%

3.3K_0402_5%

SPI_CS0#<26>

SPI_HOLD#_0

SPI_CS1#<26>

R1945 0_0402_5%R1945 0_0402_5%

+3VM

0.1U_0402_16V4Z

12

47_0402_5%

SPI_CLK

1 2

47_0402_5%

SPI_SI SPI_SI_0

1 2

C993

0.1U_0402_16V4Z

47_0402_5%@

SPI_CLK_L SPI_CLK_1

1 2

47_0402_5%@

1 2

20mils

1

2

1

2

C989

+3VM

R1290

R1290 R1294

R1294

R1296

R1296 R1295

R1295

SPI_WP#

SPI_HOLD#_0

SPI_CS0# SPI_CLK_0

20mils

SPI_WP#

SPI_HOLD#_0

SPI_CS1#

SPI_SI_1

U66

8

VCC

3

W

7

HOLD

1

S

6

C

5

D

4

VSS

SPI_SO_L0

2

Q

WIESO_G6179-100000_8P

SPI0 (16M*1)

U67

8

VCC

3

W

7

HOLD

1

S

6

C

5

D

4

VSS

SPI_SO_L1SPI_SI_L

2

Q

SST25LF080A_SO8-200mil@

SPI1 (16M*1)

R1291

1 2

15_0402_5%

R1297

@R1297

@

1 2

15_0402_5%

0821 SPI1 no install

12

SPI_SO_L

SPI_SO

R1924

R1924 0_0402_5%

0_0402_5%

SPI_SO <26>

R1794 0_0402_5%R1794 0_0402_5%

SPI_SI_L

SPI_CLK_L

12

R1795 0_0402_5%R1795 0_0402_5%

12

0907 Add 0 ohm for SPI

SPI_SI

SPI_CLK

SPI_SI <26>

SPI_CLK <26>

Debug port

CLK_DEBUG_PORT<15,31>

LPC_FRAME#<25,35,37>

+3VS

PLT_RST#<7,24,28>

LPC_AD0<25,35,37> LPC_AD1<25,35,37> LPC_AD2<25,35,37> LPC_AD3<25,35,37>

B+ STB_LED#<37> CAPS_LED#<37> NUM_LED#<37>

VCC1_PWRGD<37,41>

SPI_CLK_L SPI_CS0# SPI_SI_L SPI_SO_L

R170 0_0402_5%R170 0_0402_5% CLRP3 SHORT PADSCLRP3 SHORT PADS R201 0_0402_5%R201 0_0402_5% R202 0_0402_5%R202 0_0402_5%

0629 Change Pin3 to Pin23, change Pin24 to GND

R118 0_0402_5%@R118 0_0402_5%@

1 2

R123 0_0402_5%@R123 0_0402_5%@

1 2

12 1 2 1 2

SPICLK

SPICS0# SPISI SPISO

SPI_HOLD#_0

SPI_CS1#

JP52

1

Ground

2

LPC_PCI_CLK

3

Ground

4

LPC_FRAME#

5

+V3S

6

LPC_RESET#

7

+V3S

8

LPC_AD0

9

LPC_AD1

10

LPC_AD2

11

LPC_AD3

12

VCC_3VA

13

PWR_LED#

14

CAPS_LED#

15

NUM_LED#

16

VCC1_PWRGD

17

SPI_CLK

18

SPI_CS#

19

SPI_SI

20

SPI_SO

21

SPI_HOLD#

22

Reserved

23

Reserved

24

Reserved

ACES_87216-2404_24P

conn@

0906 SPI1 install

+3VS

Q75

47K

DTA114YKA_SC59

TPM1.2

U69

LAD0 LAD1 LAD2 LAD3

LCLK LFRAME# LRESET# SERIRQ CLKRUN#

7

PP

+3V_FP

1

2

USB20_N1_R

+3VS+3VALW

19

10

5

VSB

VDD24VDD

VDD

TESTB1/BADD

TPM

TPM SLB 9635 TT 1.1

SLB 9635 TT 1.1

GND4GND11GND18GND

25

JP38

1 2 3 4

ACES_85205-0400

conn@

1

C1052

0.1U_0402_16V4Z

2

28

LPCPD#

9 8

TEST1

14

XTALO

13

XTALI

2

GPIO2

6

GPIO

1

NC

3

NC

12

NC

SLB9635TT_TSSOP28

1 2 3 4

Base I/O Address

0 = 02Eh

* 1 = 04Eh

LPC_PD#

R1379 0_0402_5%R1379 0_0402_5%

TPM_XTALO TPM_XTALI

PAD

SI2301BDS_SOT23

+3VALW

4

12

1 2

R101 0_0402_5%@R101 0_0402_5%@ T41

T41 T42

T42

Q145

S

G

2

LPC_PD# <26>

+3VS

12

R1941

10K_0402_5%

@

D

13

+3V_FP

S4_STATE <34>

+3VS

12

TPM_32K_CLK <37>

TPM_XTALI

R1381

TPM_XTALO

10M_0402_5%

R1377

4.7K_0402_5%

R1378

4.7K_0402_5%@

18P_0402_50V8J

C1057

1 2

12

32.768KHZ_12.5P_1TJS125BJ2A251

1 4

Y8

C1056

1 2

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

IN

NC

OUT

NC

18P_0402_50V8J

Issued Date

2 3

2006/09/25 2006/09/25

3

0.1U_0402_16V4Z

1

C1053

2

0.1U_0402_16V4Z

LPC_AD0<25,35,37> LPC_AD1<25,35,37> LPC_AD2<25,35,37>

+3VS

LPC_AD3<25,35,37>

CLK_PCI_TCG<15> LPC_FRAME#<25,35,37> PLT_RST_B#<28,31,35> SIRQ<26,31,35,37> PM_CLKRUN#<26,31,35,37>

1 2

R1380

B B

LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3

CLK_PCI_TCG LPC_FRAME# PLT_RST_B# SIRQ PM_CLKRUN#

4.7K_0402_5%@

1

2

C1054

12

R1409

0_0402_5%

C1055

0.1U_0402_16V4Z

2

26 23 20 17

21 22 16 27 15

Finger printer

C206

0.1U_0402_16V4Z

0_0402_5%

5

R1334

R1334 R1335

R1335

3

2

1

0_0402_5%

12

USB20_P1_R

12

A A

USB20_N1<26> USB20_P1<26>

D54

PACDN042_SOT23~D@

D54

DTA114YKA_SC59

10K

2

+3VS

1 3

47K

10K

+3VS

1 3

Compal Secret Data

Deciphered Date

2

Q88

Q88 DTA114YKA_SC59

DTA114YKA_SC59

47K

10K

2

Q89

@

Q89

@

DTA114YKA_SC59

1 3

WL_LED

WW_LED# <31>

WL_LED# <31>

WP_LED# <31>

2

Mini-PCIE Card LED

BLUE

Q79

13

D

2

G

S

R505

R504

Title

Size Document Number Rev

Date: Sheet

S

1 2

13

D

Q78

2

RHU002N06_SOT323

G

S

1 2

Compal Electronics, Inc.

TCG/BIOS ROM/PS2/LED/SW

LA3262P_DIS__M64

1

BT_LED<34>

RHU002N06_SOT323

100K_0402_5%

WL_BLUE_LED# <31,38>

of

36 57Tuesday, August 21, 2007

of

36 57Tuesday, August 21, 2007

of

36 57Tuesday, August 21, 2007

1A

5

1070@

1021@

KSI0 KSI3 KSI2 KSI1

KSI7 KSI6 KSI5 KSI4

TP_CLK

TP_DATA

KBD_CLK KBD_DATA PS2_CLK PS2_DATA

RUNSCI_EC#

12

R14770_0603_5%

12

R14780_0603_5%

18P_0402_50V8J

32.768KHZ_12.5P_1TJS125BJ2A251

+3VL

+3VS

+3VL

D D

C C

B B

1 8 2 7 3 6 4 5

10K_1206_8P4R_5%

1 8 2 7 3 6 4 5

10K_1206_8P4R_5%

+5VS

1 2

10K_0402_5%

1 2

10K_0402_5%

1 8 2 7 3 6 4 5

10K_1206_8P4R_5%

+3VS

1 2

10K_0402_5%

CLK_PCI_EC

12

R86

10_0402_5%@

2

C80

10P_0402_50V8J@

1

RP58

RP59

R578

R580

RP60

R1289

PWR1

1

C39

0.1U_0402_16V4Z

2

C350

2/22 change

0.1U_0402_16V4Z

1 2

R74

R74 2M_0402_5%@

2M_0402_5%@

4

1

Y2

IN

1

OUT

NC3NC

2

1

C37

0.1U_0402_16V4Z

2

KSO[0..13]<38>

Pin3 250 : KSO12/OUT8/KBRST

KSI[0..7]<38>

TP_DATA<38> KBD_CLK<39>

KBD_DATA<39>

PS2_CLK<39>

PS2_DATA<39>

PM_CLKRUN#<26,31,35,36>

CLK_PCI_EC<15>

RUNSCI_EC#<26>

LPC_AD3<25,35,36> LPC_AD2<25,35,36> LPC_AD1<25,35,36> LPC_AD0<25,35,36>

LPC_FRAME#<25,35,36>

NPCI_RST#<26,35>

ADP_PS1<50>

120K_0402_5%

R75

12

1

18P_0402_50V8J

C349

2

C52

TP_CLK<38>

SIRQ<26,31,35,36>

+RTCVCC

+3VL

1

0.1U_0402_16V4Z

2

KSO[0..13]

TP_CLK TP_DATA KBD_CLK KBD_DATA PS2_CLK PS2_DATA

PM_CLKRUN# SIRQ CLK_PCI_EC RUNSCI_EC#

LPC_AD3 LPC_AD2 LPC_AD1 LPC_AD0

LPC_FRAME#

CRY1 CRY2

R1925 0_0402_5%@R1925 0_0402_5%@

1 2

0_0402_5%

1 2

R1926

@R1926

@

1 2

0_0402_5%

0_0402_5% R1942

R1942

1U_0603_10V4Z

C661

4

C51

KSO0 KSO1 KSO2 KSO3 KSO4 KSO5 KSO6 KSO7 KSO8 KSO9 KSO10 KSO11 KSO12 KSO13

KSI0 KSI1 KSI2 KSI3 KSI4 KSI5 KSI6 KSI7

2

1

0.1U_0402_16V4Z

2

U47

21

KSO0

20

KSO1

19

KSO2

18

KSO3

17

KSO4

16

KSO5

13

KSO6

12

KSO7

10

KSO8

9

KSO9

8

KSO10

7

KSO11

6

KSO12/GPIO00/KBRST

5

KSO13/GPIO18

29

KSI0

28

KSI1

27

KSI2

26

KSI3

25

KSI4

24

KSI5

23

KSI6

22

KSI7

35

IMCLK

36

IMDAT

38

KCLK

40

KDAT

41

EMCLK

42

EMDAT

55

CLKRUN#

57

SER_IRQ

54

PCI_CLK

76

EC_SCI#

51

LAD[3]

50

LAD[2]

48

LAD[1]

46

LAD[0]

52

LFRAME#

53

LRESET#

45

LPCPD#/GPIO23

70

XTAL1

71

XTAL2

68

VCC0

1

C1317

0.1U_0402_16V4Z

2

1

C36

4.7U_0805_10V4Z

2

NC94NC95NC96NC97NC

Power Mgmt/SIRQ

LPC

LPC Bus

Bus

NC1NC2NC3NC30NC31NC32NC33NC34NC43NC

3

+3VL

1070@

1

C34

2

PWR1

127NC128

VCC139VCC158VCC184VCC1

Keyboard/Mouse Interface

AGND

VSS11VSS37VSS47VSS56VSS

72

44

1070@

14

106

119

49

VCC1

Access Bus Interface

SMSC_1070_TQFP-128P

VSS82VSS

NC62NC63NC64NC65NC66NC

104

117

0_0402_5%

PWR_GD

12

R1642

1021@R1642

1021@

R1646

12

+3VS

0_0402_5%1070@

1

2

15

CAP

VCC2

General Purpose I/O Interface

24MHZ_OUT/GPIO19/WINDMON

Miscellaneous

67

T33

T32

C750.1U_0402_16V4Z

PAD

GPIO30

100

126

GPIO2893GPIO2998GPIO3099GPIO31

GPIO32

OUT1/IRQ8#

OUT8/KBRST

OUT9/PWM2 OUT10/PWM0 OUT11/PWM1

GPIO04/KSO14 GPIO05/KSO15

GPIO07/PWM3

GPIO08/RXD

GPIO09/TXD

GPIO11/AB2A_DATA

GPIO12/AB2A_CLK

GPIO13/AB2B_DATA

GPIO14/AB2B_CLK GPIO15/FAN_TACH1 GPIO16/FAN_TACH2

GPIO17/A20M

GPIO20/PS2CLK GPIO21/PS2DAT

GPIO24/KSO16

AB1A_DATA

AB1B_DATA

PGM Strap/GPIO25

EA Strap#/GPIO26/KSO17

32KHZ_OUT/GPIO22

RESET_OUT#/GPIO06

VCC1_PWRGD

DMS_LED#/GPIO10 PWR_LED#/8051TX

FDD_LED#/8051RX

KBC1070_VTQFP128

PM_SLP_M#

1 2

R38 0_0402_5%

R141 0_0402_5%R141 0_0402_5%

1 2

PCI_SERR# <24,31>

124

OUT0

125 123

OUT7/SMI#

122 121 120 118

107

GPIO01

79

GPIO02

80

GPIO03

81 83

85 86 87

88 89 90 91 92 101 102

103 105 4 74

GPIO27

111 112

AB1A_CLK

109 110

AB1B_CLK

73 108

59

CLOCKI

75 60 78

PWRGD

77 61

69

TEST PIN

116 113

BAT_LED#

115 114

PM_SLP_M# <26,40,47,48,52>

KBC_PWR_ON GREEN_BATLED#

BATSELB_A# KBRST# A_SD FAN_PWM CHGCTRL

THM_MBAY#

ON/OFFBTN_KBC#

LOW_BAT# KSO14 KSO15

RSMRST_EC CRACK_BGA EC_GPIO9

AB2A_DATA AB2A_CLK AB2B_DATA AB2B_CLK

BATCON THM_MAIN# A20M

NUM_LED# SLP_S3#

EC_GPIO27

AB1A_DATA AB1A_CLK

AB1B_DATA AB1B_CLK

Cap_INT EA#

CLK_14M_KBC 32K_CLK PM_POK PWR_GD VCC1_PWRGD

Pin50 250 -- 24MHz_Out

TEST

Pin52 250 -- XOSEL

AMBER_BATLED#

STB_LED# CAPS_LED#

2

CRACK_BGA

D10 CH751H-40_SC76D10 CH751H-40_SC76

1 2

GPIO29 <26>

EAPD <32,33>

AMT ADP_PRES <26>

1

1070@

C128910U_0805_10V4Z

2

GREEN_BATLED# <25,31> BATSELB_A# <45> A_SD <33>

FAN_PWM <4> CHGCTRL <44,45>

R204.7K_0402_5% R204.7K_0402_5%

R156 0_0402_5%R156 0_0402_5% R155 0_0402_5%R155 0_0402_5% R140 0_0402_5%R140 0_0402_5% R154 0_0402_5%R154 0_0402_5%

2 1

R184.7K_0402_5% R184.7K_0402_5%

1 2 1 2 1 2 1 2

R581

10K_0402_5%

T37 PADT37 PAD

Cap_INT <38>

1 2

R977 300_0402_5%R977 300_0402_5%

CRACK_GPIO28 <11,27>

R17260_0402_5% R17260_0402_5%

+3VL

12

R575

KBC_PWR_ON <46>

THM_MBAY# <43> ON/OFFBTN_KBC# <38>

LOW_BAT# <26> KSO14 <38> KSO15 <38> RSMRST_EC <26>

1 2 1 2

BATCON <45> THM_MAIN# <43>

12

+3VL

ADP_PRES <29,44,45,46,50>

CLK_14M_KBC <15> PM_POK <49>

PWR_GD <21,26,31,40,41,49,50> VCC1_PWRGD <36,41> ADP_PS0 <50>

ADP_ID <50> AMBER_BATLED# <31> STB_LED# <36> CAPS_LED# <36>

R62 250@

R575 10K_0402_5%

10K_0402_5%

CH751H-40_SC76

Cap_DAT <38> Cap_CLK <38> ME_EC_DATA1 <26> ME_EC_CLK1 <26>

D6 CH751H-40_SC76D6 CH751H-40_SC76

NUM_LED# <36> SLP_S3# <26,29,32,33,39,40,47,48,49,50,51,52>

AB1A_DATA <43> AB1A_CLK <43>

AB1B_DATA <43> AB1B_CLK <43>

Pin91 250 -- nDMS_LED

D7

21

KB_RST# <25>

+3VL

21

GATEA20 <25>

Pin1 250 -- TEST Pin ( NC !! ) Pin57 250 -- MODE

R58 100K_0402_5%R58 100K_0402_5%

+3VL

1 2

R59 100K_0402_5%R59 100K_0402_5%

1 2

R60 100K_0402_5%R60 100K_0402_5%

1 2

Remove from daughter board

1

RP1

AB1A_CLK AB1A_DATA AB1B_CLK AB1B_DATA

RP1

1 8 2 7 3 6 4 5

4.7K_1206_8P4R_5%

BIOS debug port Place under KB area

+3VL

VCC1_PWRGD EC_GPIO9

CRACK_BGA

THM_MAIN# ADP_PS1 EC_GPIO27

CLK_14M_KBC

FWP# PM_POK

VCC1_PWRGD NUM_LED# STB_LED# CAPS_LED#

R538 100K_0402_5%@R538 100K_0402_5%@

R282

1 2

10_0402_5%

@

R25

1 2

10K_0402_5%

+3VL

JP43

1 2 3 4 5 6

ACES_85201-0602@

R600

1 2

210K_0402_1%

1 2

R33

1 2

100K_0402_5%

C92

1 2

10P_0402_25V8K

@

JP31

1 2 3 4 5 6

ACES_85201-0602@

For KBC debugging used.

+3VL

AGND FILTER

R29

C58

1 2

0.1U_0402_16V4Z

A A

32K_CLK

R91 0_0402_5%R91 0_0402_5%

1 2

R97 0_0402_5%@R97 0_0402_5%@

1 2

ADP_EN <50> TPM_32K_CLK <36>

5

FWP#

TEST

EA#

FWP#

R29

1 2

100K_0402_5%

R28

1K_0402_5%@

R78

1K_0402_5%@

1K_0402_5%@ R27

R27

1K_0402_5%

4

+3VL

12

STB_LED#

U87

1

A1

2

GND

3

A2

NC7WZ07P6X_NL_SC70-6

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

6

Y1

5

VCC

4

Y2

2006/09/25 2006/09/25

3

+3VL

LED_STB# <31,38,39>

Compal Secret Data

Deciphered Date

2

11/20 for solve PM_PWROK glitch on power up

+3VALW

U89

5

1

PWR_GD<21,26,31,40,41,49,50>

PGOOD_PU19<49>

P

IN1

4

O

2

IN2

G

3

SN74AHC1G08DCKR_SC70

Title

Size Document Number Rev

Date: Sheet

0_0402_5%

0_0402_5% R1810

R1810

PM_PWROK <26>

VGATE <7,26>

Compal Electronics, Inc.

LPC47N1021

LA3262P_DIS__M64

37 57Tuesday, August 21, 2007

1

1A

of

SWITCH BOARD.

R21 0_0402_5%@R21 0_0402_5%@

Cap_RST#

1 2

0901 Change Cap_RST#_SB to SB GPIO28

+3VL +3VS

JP18

Cap_DAT<37>

Cap_RST#

1 2 3 4 5 6 7 8 9 10

ACES_85203-1002

conn@

0622 change

Cap_RST#_SB <26>

12

R30

10K_0402_5%

Cap_CLK <37> Cap_INT <37>

WL_BLUE_LED# <31,36>

0829 Change to WL_BLUE_LED#

WL,Vol up,Vol down,Mute,Present button

MDC 1.5 Conn.

HDA_SDOUT_MDC<25>

HDA_SYNC_MDC<25>

HDA_SDIN1<25>

HDA_RST#_MDC<25,32>

1 2

R1753 0_0402_5%R1753 0_0402_5%

0620 RESERVE FOR MDC

HDA_SYNC_MDC

R1313

HDA_RST#_MDC_R

Cap_INT

1

C1

C1 10P_0402_50V8K

10P_0402_50V8K

2

@

On/off ,information button

11/06 follow UMA SI-2 design change

JP32

1

HDA_SDOUT_MDC

HDA_SDIN1_MDC

12

33_0402_5%

GND1

3

IAC_SDATA_OUT

5

GND2

7

IAC_SYNC

9

IAC_SDATA_IN

11

IAC_RESET#

conn@

131314141515161617171818191920

C749220P_0402_50V4Z C749220P_0402_50V4Z

12

C750220P_0402_50V4Z C750220P_0402_50V4Z

12

2007,0125 change

JP20

@JP20

@

9 10 11 12 13 14 15 16

Aces_85203-08421-11

IAC_BITCLK

1

9

2

10

3

11

4

12

5

13

6

14

7

15

8

16

2

RES0

4

RES1

6

3.3V

8

GND3

10

GND4

HDA_BITCLK_MDC

12

20

Connector for MDC Rev1.5

LED_STB#

ON/OFF#

LID_SW# LED_STB#

ON/OFF#

0.1U_0402_16V4Z

+3VS

TYCO_1-179396-2~D

+3VALW

LID_SW# <17,26> LED_STB# <31,37,39>

ON/OFF# LID_SW#

D81

@D81

@

PJDLC05_SOT23~D

+3VS

1

C5

2

HDA_BITCLK_MDC <25>

INT_KBD CONN.

KSO[0..15]<37> KSI[0..7]<37>

2

3

1

KSO[0..15] KSI[0..7]

30

29

28

27

26

25

KSO15 KSO10 KSO11 KSO14 KSO13 KSO12

KSO3 KSO6 KSO8 KSO7 KSO4 KSO2

KSI0 KSO1 KSO5

KSI3

KSI2 KSO0

KSI5

KSI4 KSO9

KSI6

KSI7

KSI1

CP1

KSO9

4 5

KSI6

3

KSI7

2

KSI1

100P_1206_8P4C_50V8

CP3

KSI2

4 5

3

KSI5

2

KSI4

100P_1206_8P4C_50V8

CP7

KSI3

4 5

KSO5

3

KSO1 KSO10

2

KSI0

100P_1206_8P4C_50V8

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

FOX_GB1SV301-160K-7F

6 7 81

conn@

KSO2 KSO4 KSO7 KSO8

KSO6 KSO3KSO0 KSO12 KSO13

KSO14 KSO11

KSO15

JP6

A30

60

A29

59

A28

58

A27

57

A26

56

A25

55

KSO15

A24

54

KSO10

A23

53

KSO11

A22

52

KSO14

A21

51

KSO13

A20

50

KSO12

A19

49

A18

48

A17

47

A16

46

A15

45

A14

44

A13

43

A12

42

A11

41

A10

40

A9

39

A8

38

A7

37

A6

36

A5

35

A4

34

A3

33

A2

32

A1

31

CP6

4 5 3 2

100P_1206_8P4C_50V8

CP5

4 5 3 2

100P_1206_8P4C_50V8

CP2

4 5 3 2

100P_1206_8P4C_50V8

KSO3 KSO6 KSO8 KSO7 KSO4 KSO2

KSI0 KSO1 KSO5

KSI3

KSI2 KSO0

KSI5

KSI4 KSO9

KSI6

KSI7

KSI1

6 7 81

Power button

12

R22

100K_0402_5%

ON/OFF#<39>

ON/OFF#

C23

1U_0603_10V4Z

U5F

14

SN74LVC14APWLE_TSSOP14

P

13

O12I

G

1

7

2

R26

1 2

100K_0402_5%

1U_0603_10V4Z

+3VL

12

R536

100K_0402_5%

ON/OFFBTN_KBC#

13

D

2

G

S

1

C11

2

Q70

RHU002N06_SOT323

ON/OFFBTN_KBC# <37>

1 2

D42

CH751H-40_SOD323

R8

1 2

100K_0402_5%

ON/OFFBTN#

+3VALW

ON/OFFBTN# <26>

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

TrackPoint CONN. T/P BOARD.

+5VS

2

3

1

PJDLC05_SOT23~D

1

C321

0.1U_0402_16V4Z

2

D58

3

TP_DATA<37>

TP_CLK<37>

TP_DATA TP_CLK

2

1

TP_DATA TP_CLK

SP_DATA SP_CLK

Title

Size Document Number Rev

Date: Sheet

Issued Date

JP14

1

2

SP_DATA

3 5 7

ACES_87153-0801L

conn@

2006/09/25 2006/09/25

SP_CLK

4 6

+5VS

8

PACDN042_SOT23~D@

Compal Secret Data

Deciphered Date

D67

+5VS

JP17

ACES_87212-0800

conn@

Compal Electronics, Inc.

MDC/KBD/ON_OFF/LID

+5VS

1 2 3 4 5 6 7 8

LA3262P_DIS__M64

1

C319

0.1U_0402_16V4Z

2

1A

of

38 57Tuesday, August 21, 2007

of

38 57Tuesday, August 21, 2007

of

38 57Tuesday, August 21, 2007

A

DOCK CONN. 184PIN

C746 10P_0402_50V8J C746 10P_0402_50V8J

RED

1 1

2 2

3 3

GREEN BLUE

DOCK_RED DOCK_GRN DOCK_BLU

1 2

C747 10P_0402_50V8J C747 10P_0402_50V8J

1 2

C748 10P_0402_50V8J C748 10P_0402_50V8J

1 2

C1630 22P_0402_50V8J C1630 22P_0402_50V8J

1 2

C1631 22P_0402_50V8J C1631 22P_0402_50V8J

1 2

C1632 22P_0402_50V8J C1632 22P_0402_50V8J

1 2

0314 change

RED<19>

GREEN<19>

BLUE<19>

HLC0603CSCCR11JT_0603

R1404

1 2 1 2 1 2

R1428

R1429

HLC0603CSCCR11JT_0603

HLC0603CSCCR11JT_0603 HLC0603CSCCR11JT_0603

HLC0603CSCCR11JT_0603

1000P_0402_50V7K

ON/OFF#<38>

MDO2+<30> MDO2-<30>

MDO0+<30> MDO0-<30>

D_VSYNC<16> D_HSYNC<16>

D_DDCDATA<16>

D_DDCCLK<16>

DVI_DETECT<19>

DOCK_RED DOCK_GRN DOCK_BLU

COMP<16,19> CRMA<16,19>

LUMA<16,19>

LINE_IN_SENSE<32> ACOCP_EN#<50>

DCD#1<35>

DTR#1<35> CTS#1<35> RTS#1<35> DSR#1<35>

LPTSTB#<35> LPTAFD#<35>

LPTERR#<35>

L10

KC FBM-L18-453215-900LMA90T_1812

1

C72

2

ON/OFF# MDO2+

MDO2MDO0+

MDO0LED_ACT_LAN#_DOCK

LED_LINK_LAN#_DOCK

D_DDCDATA D_DDCCLK DVI_DETECT

DCD#1 RI#1

RI#1<35>

DTR#1 CTS#1 RTS#1 DSR#1 TXD1

TXD1<35>

RXD1

RXD1<35>

LPTSTB# LPTAFD# LPTERR#

12

1

2

B

DOCKVINVIN

C73

1000P_0402_50V7K

JP30A

conn@JP30A

conn@

172

10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45

JAE_SP03-14588-PCL03

P1

G1

1 2 3 4 5 6 7 8 9

83

1

84

2

85

3

86

4

87

5

88

6

89

7

90

8

91

9

92

10

93

11

94

12

95

13

96

14

97

15

98

16

99

17

100

18

101

19

102

20

103

21

104

22

105

23

106

24

107

25

108

26

109

27

110

28

111

29

112

30

113

31

114

32

115

33

116

34

117

35

118

36

119

37

120

38

121

39

122

40

123

41

124

42

125

43

126

44

127

45

173

DOCKVIN

DETECT

83 84

MDO3+

85

MDO3-

86 87

MDO1+

88

MDO1-

89 90

PWR_LED

91 92

R515 1K_0402_5%R515 1K_0402_5%

93

DVI_CLK

94

DVI_DAT

95 96 97

DVI_TX2-

98 99

DVI_TX2+

100 101 102

DVI_TX1-

103 104

DVI_TX1+

105 106 107

DVI_CLK-

108 109

DVI_CLK+

110 111 112

DVI_TX0-

113 114

DVI_TX0+

115 116

DOCK_ADP_SIGNAL

117

DOCK_ID

118 119 120 121 122 123 124 125 126 127

1 2

MDO3+ <30> MDO3- <30>

MDO1+ <30> MDO1- <30>

SLP_S5#_5R

DVI_CLK <19> DVI_DAT <19>

DVI_TX2- <19> DVI_TX2+ <19>

DVI_TX1- <19> DVI_TX1+ <19>

DVI_CLK- <19> DVI_CLK+ <19>

DVI_TX0- <19> DVI_TX0+ <19>

DOCK_ID <26>

C

DOCK_ID

DOCK_ADP_SIGNAL

EXPCRD_RST#<35>

R1387

1 2

10K_0402_5%@

R1401

1 2

1K_0402_1%

LPTACK#<35>

LPTBUSY<35>

LPTPE<35>

LPTSLCT<35>

LPTSLCTIN#<35>

LPTINIT#<35>

USB20_N7<26> USB20_P7<26> USB20_N9<26> USB20_P9<26>

SER_SHD<35>

ADP_SIGNAL

D

+5VALW

12

R529

R529 100K_0402_5%

100K_0402_5%

SLP_S5#_5R

13

D

Q65

2

SLP_S5<40>

LPTACK# LPTBUSY LPTPE LPTSLCT LPD7

LPD7<35>

LPD6

LPD6<35>

LPD5

LPD5<35>

LPD4

LPD4<35>

LPD3

LPD3<35>

LPD2

LPD2<35>

LPD1

LPD1<35>

LPD0

LPD0<35>

LPTSLCTIN# LPTINIT#

SER_SHD EXPCRD_RST# DETECT

+3VS

G

RHU002N06_SOT323

S

JP30B

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

176

GND

169

GND

175

GND

179

GND

181

GND

177

GND

165

G2

166

RING

JAE_SP03-14588-PCL03

conn@JP30B

conn@

128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164

GND GND GND GND GND GND

TIP

P2

DOCK_MOD_RING DOCK_MOD_TIP

128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153

PCIE_RXP5_DOCK

154 155

PCIE_RXN5_DOCK PCIE_RXN5

156 157 158 159 160 161 162 163 164

178 180 182 174 171 170

167

168

PACDN042_SOT23~D@

+5VS

DOCK_MOD_TIPDOCK_MOD_RING

D59

KBD_DATA KBD_CLK CPPE# PS2_DATA PS2_CLK DOCK_HPS#

DLINE_IN_L DLINE_IN_R

DLINE_OUT_L DLINE_OUT_R

PCIE_TXP5 PCIE_TXN5

1 2

0_0402_5%

1 2

0_0402_5%

CLK_PCIE_DOCK CLK_PCIE_DOCK# PREP#

VA_ON#

12

R66

1K_0402_5%

2

3

1

JP29

conn@

2 1

E-T_3800-02_2P

KBD_DATA <37> KBD_CLK <37> CPPE# <15> PS2_DATA <37> PS2_CLK <37> DOCK_HPS# <33>

DLINE_IN_L <32> DLINE_IN_R <32>

DLINE_OUT_L <33> DLINE_OUT_R <33>

PCIE_TXP5 <26> PCIE_TXN5 <26>

PCIE_RXP5

R1346

R1346 R1347

R1347

CLK_PCIE_DOCK <15> CLK_PCIE_DOCK# <15> PREP# <26,30,32>

C678

+

1 2

22U_1206_10V4Z@

SWAP

1

C59

0.1U_0402_16V4Z

2

E

PCIE_RXP5 <26> PCIE_RXN5 <26>

Closed to JP30

+3VS

U52

5

VCC

BLUE<19> L_BLUE<16>

ISO_PREP#<26>

+3VM_LAN

4 4

R527

10K_0402_5%

12

LED_ACT_LAN#_DOCK_R

13

D

2

G

S

LED_LINK_LAN#_DOCK_R

13

D

2

G

S

A

Q62

Q62 RHU002N06_SOT323

RHU002N06_SOT323

Q63

Q63 RHU002N06_SOT323

RHU002N06_SOT323

1

L_BLUE

2

ISO_PREP#

4 3

FSA66P5X_SC70-5

LED_ACT_LAN# <29,30>

LED_LINK_LAN# <26,29,30>

A B

OE GND

R1937

1 2

0_0402_5%

R1938

1 2

0_0402_5%

GREEN<19>

L_GREEN<16> L_RED<16>

LED_ACT_LAN#_DOCK

C1627

@

100P_0402_50V8J

LED_LINK_LAN#_DOCK

100P_0402_50V8J

C1628

@ C1628

@

+3VS +3VS

U51

5

VCC

12

L_GREEN

ISO_PREP#

B

1

A

2

B

4

OE

3

GND

FSA66P5X_SC70-5

LED_STB#<31,37,38>

RHU002N06_SOT323

SLP_S3#<26,29,32,33,37,40,47,48,49,50,51,52>

RED<19>

+3VALW

12

13

D

2

G

Q59

S

U50

5

VCC

1

A

L_RED

2

ISO_PREP#

R526

R526 10K_0402_5%

10K_0402_5%

PWR_LED

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

B

4

OE

3

GND

FSA66P5X_SC70-5

C

Compal Secret Data

2006/09/25 2006/09/25

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

D

Date: Sheet

Compal Electronics, Inc.

Docking CONN.

LA3262P_DIS__M64

39 57Tuesday, August 21, 2007

E

1A

of

A

B

C

D

E

+1.25VM to +1.25VS Transfer

1

S

2

S

3

S

4

G

1

0.1U_0402_16V4Z

C1616

0.1U_0402_16V4Z

2

@

1

C127

2

10U_0603_6.3V6M

R17 0_0402_5%

1 2

12

1SS355_SOD323

1 2

470_0402_5%

1

C120

0.01U_0402_25V7Z

2

+1.25VS+1.25VM

1

C1271

2

U13

8

D

7

D

6

D

5

D

SI4800DY_SO8

D76

@D76

@

10U_0603_6.3V6M

1

C1272

2

0904 Add

+3VS+3VALW

1

S

2

S

3

S

4

G

1

2

0904 Add

1

+

C254

C254 330U_D2E_2.5VM_R15

330U_D2E_2.5VM_R15

2

0.1U_0402_16V4Z

1

C128

C132

2

10U_0603_6.3V6M

C1619

0.1U_0402_16V4Z

@

U77

8

D

7

D

6

1

1 1

2

C1270

5

10U_0603_6.3V6M

0_0402_5%

1 2

R1918

1SS355_SOD323

1 2

D75

@D75

@

D D

SI4800DY_SO8

+1.25VS_ONRUNON

+3VALW to +3VS Transfer

B+

12

R139

330K_0402_5%

RUNON +3VS_ON

12

J34

R469

SHORT PADS

2 2

SLP_S3

Q18

R469

13

D

2

G

S

RHU002N06_SOT323

+5VALW to +5VS Transfer

+5VALW

U9

8

D

7

D

6

1

2

3 3

C86

5

10U_0603_6.3V6M

1 2 1 2

D78

@D78

@

1SS355_SOD323

D D

SI4800DY_SO8

+5VS

0.1U_0402_16V4Z

1

S

2

S

3

1

S

4

G

R19200_0402_5% R19200_0402_5%

+5VS_ONRUNON

1

2

1

C71

2

0904 Add

C1618

0.1U_0402_16V4Z

@

C77

C77 10U_0603_6.3V6M

10U_0603_6.3V6M

+3VALW to +3VM Transfer

+3VALW

12

R1647

100K_0402_5%

PM_SLP_M#<26,37,47,48,52>

BSS138_SOT23

Q116

2007,0125 change

Discharge circuit-2 for V-M

Q112

+1.05VM

12

R632

R632 470_0402_5%

470_0402_5%

13

D

2

G

S

SLP_S4#<26,48>

+1.25VM

12

R631

47_0603_5%

13

D

Q111

D

2

G

S

SLP_S3

SLP_S3#

RHU002N06_SOT323

Q19

RHU002N06_SOT323

+3VL

12

R125

R125 100K_0402_5%

100K_0402_5%

13

D

2

G

S

LAN_WOL_EN# LAN_WOL_EN#

RHU002N06_SOT323

SLP_S3#<26,29,32,33,37,39,47,48,49,50,51,52> SLP_S5#<26,48>

13

D

2

G

S

LAN_WOL_EN<26>

RHU002N06_SOT323

LAN_WOL_EN#

+3VALW

R1940

100K_0402_5%

R630

@R630

@

100K_0402_5%

LAN_WOL_EN#

Q113

RHU002N06_SOT323

SLP_S4

2

G

Q23

12

2

G

12

+3VM

2

G

+3VL

12

R129

R129 100K_0402_5%

100K_0402_5%

13

D

S

R1643

100K_0402_5%

2

G

13

D

Q110

S

BSS138_SOT23

12

R633

R633 470_0402_5%

470_0402_5%

13

D

S

B+

12

13

D

S

C1273

10U_0603_6.3V6M

Q108

Q108 BSS138_SOT23

BSS138_SOT23

+1.8V to VDD_MEM18 Transfer

SLP_S5<39>

+3VALW +3VM

1

2

12

R470

R470 470_0402_5%

470_0402_5%

1

C121

0.01U_0402_25V7Z

2

U85

8

D

7

D

6

1

2

SLP_S5#

RHU002N06_SOT323

C1602

5

10U_0603_6.3V6M

1 2

10K_0402_5%

R1919

D77

1 2

1SS355_SOD323

100K_0402_5%

SLP_S5

2

G

Q22

D D

SI4800DY_SO8

+5VALW

U78

8

D

7

D

6

D

5

D

SI4800DY_SO8

PM_SLP_M

S S S G

+1.8VS_ONRUNON

12

R135

13

D

S

1

S

2

S

3

S

4

G

1 2 3 4

1

2

1

C1274

C1275

C1275 10U_0603_6.3V6M

2

0.1U_0402_16V4Z

VDD_MEM18+1.8V

0.1U_0402_16V4Z

1

C1603

2

C1617

0.001U_0402_50V7M

11/20 for ATI power sequence to install

SLP_S3

10U_0603_6.3V6M

2

1

C1604

2

10U_0603_6.3V6M

2

G

Q131

RHU002N06_SOT323

1

+

C1601

C1601 330U_D2E_2.5VM_R15

330U_D2E_2.5VM_R15

2

VDD_MEM18

12

R1895

R1895 470_0402_5%

470_0402_5%

13

D

S

Discharge circuit-1

C91

1 2

0.1U_0402_16V4Z

C184

+VCCP +1.5VS

+1.5VS

4 4

1 2

0.1U_0402_16V4Z

0.1U_0402_16V4Z C93

C93

1 2

0.1U_0402_16V4Z

+VCCP+VCC_CORE

SLP_S4

1 2

R1311 0_0402_5%R1311 0_0402_5%

SLP_S5

+1.8V

A

1 2

R1312 0_0402_5%@R1312 0_0402_5%@

+0.9V

12

R186

R186 470_0402_5%

470_0402_5%

13

D

Q27

2

G

S

RHU002N06_SOT323

+3VS

12

R134

R134 470_0402_5%

470_0402_5%

13

D

SLP_S3

B

D

2

G

S

RHU002N06_SOT323

PWR_GD <21,26,31,37,41,49,50>

Q17

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

+1.5VS

2

G

RHU002N06_SOT323

C

12

R151

R151 470_0402_5%

470_0402_5%

13

D

Q47

S

2006/09/25 2006/09/25

+2.5VS

12

SLP_S3

RHU002N06_SOT323

13

2

G

Compal Secret Data

R130

R130 470_0402_5%

470_0402_5%

D

Q21

S

Deciphered Date

SLP_S3SLP_S3

2

G

RHU002N06_SOT323

D

+5VS

12

470_0402_5%

13

D

S

R116

Q16

SLP_S4

1 2

R107 0_0402_5%R107 0_0402_5%

SLP_S5

1 2

R110 0_0402_5%@R110 0_0402_5%@

Title

Size Document Number Rev

Date: Sheet

+1.8V

12

R1310

R1310 470_0402_5%

470_0402_5%

13

D

2

Q90

G

S

RHU002N06_SOT323

Compal Electronics, Inc.

DC/DC Circuits

LA3262P_DIS__M64

40 57Tuesday, August 21, 2007

E

1A

of

PWR_OK circuit

+1.25VS

VCCP_POK<52>

+5VS

+3VS

DDR_PGOOD

CH751H-40_SC76

VDD_MEM18

+2.5VS

CH751H-40_SC76

D69

21

130K_0402_5%@

49.9K_0402_1%

10K_0402_5%

232K_0402_1%

150K_0402_1%

10K_0402_5%

1 2

100K_0402_5%@R5100K_0402_5%@

1 2

R128

21

12

D71

R285

R288

R289

R1747

R5

R14

1

2

20K_0402_5%

12

R115

C32

1000P_0402_50V7K

VREF_393

KBC PWR_OK circuit

+3VL

12

R24

R24 100K_0402_5%

100K_0402_5%

1

C26

0.1U_0402_16V4Z

2

+3VL +3VL

14

U5D

P

9

O8I

G

7

SN74LVC14APWLE_TSSOP14

14

U5C

P

5

O6I

G

7

SN74LVC14APWLE_TSSOP14

R1943

R1943 0_0402_5%

0_0402_5%

1 2

12

R1939

R1939 100K_0402_5%

100K_0402_5%

VCC1_PWRGD <36,37>

1

J38

1 2

SHORT PADS

+3VS

12

R47

R47 10K_0402_5%

10K_0402_5%

PWR_GD <21,26,31,37,40,49,50>

R1261M_0402_5% R1261M_0402_5%

12

+5VALW

8

U91A

3

P

+

O

2

-

G

LM393M_SO8

4

1219 Add Schmitt Trigger to eliminate glitch and pull down resistor

+3VALW

12

R1910

10K_0402_5%

C

+0.9V

M_PROK<52>

R284

12

3.3K_0402_5%

DDR_PGOOD

CH751H-40_SC76

+3VM

C1613

1000P_0402_50V7K

2

B

D70

R1911

10K_0402_5%

1 2 1 2

76.8K_0402_1%

76.8K_0402_1% R1912

R1912

1

2

C

Q134

E

MMBT3904_SOT23

3 1

21

12

20K_0402_5%

1 2

10K_0402_5%

1.24VREF

R39

56.2K_0402_1%

LAN_RST circuit

11/20 Enable ACBS (power management for NIC)

+3VL

1

C991

0.1U_0402_16V4Z

+3VM

0.1U_0402_16V4Z

120K_0402_5%

R1732

2

1

12

14

P

O2I

G

U5A

7

SN74LVC14APWLE_TSSOP14

1.8PGOOD<48>

R198

R178

1 2

R117

0_0402_5%

R199

1 2

5

VREF_393

1

2

Need be tune to 10msec time delay

D60

R1350

1 2

100K_0402_1%

+

6

-

C33

C33 1000P_0402_50V7K

1000P_0402_50V7K

CH751H-40_SOD323

12

1

2

C990

0.1U_0603_50V4Z

2

G

+5VALW

8

U91B

P

G

4

DDR_PGOOD

12

13

D

S

1M_0402_5%

7

O

LM393M_SO8

+3VL

14

P

3

G

7

Q133

Q133 RHU002N06_SOT323

RHU002N06_SOT323

+3VALW

12

R49

R49 10K_0402_5%

10K_0402_5%

1

C992

0.1U_0402_16V4Z

2

O4I

SN74LVC14APWLE_TSSOP14

U5B

M_PWROK <7,26>

LAN_RST# <26>

Energy Star for CPU

1M_0402_5%

R43

@R43

@

1 2

CF12CF12

1

2

1

1 3

12

R1934

@R1934

@

100K_0402_5%

CF13CF13

+3VALW

IN+ IN-

LMV331IDCKRG4_SC70-5~D

1

20K_0402_5%

R1931

@R1931

@

+VCC_CORE

1.24VREF

FM1FM1

FM2FM2

1

CF8CF8

CF7CF7

1

H15

H15 HOLEC

HOLEC

1

H10

H10 HOLEB

HOLEB

1

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

FM4FM4

FM3FM3

1

CF9CF9

1

H16

H17

HOLEC

1

H11

H12

HOLEB

1

2006/09/25 2006/09/25

12

R1933

@R1933

@

12

20K_0402_5%

C1622

@C1622

@

0.1U_0402_16V4Z

FM5FM5

1

CF11CF11

CF10CF10

1

H14

H13

HOLEB

1

Compal Secret Data

Deciphered Date

5

2

CF14CF14

CF6CF6

P

G

@U88

@

O

U88

+3VALW

4

1114 Add

12

R46

@R46

@

10K_0402_5%

1 2

@R52

@

20K_0402_5%

H1 HOLEAH1HOLEA

1

H18

H18 HOLED

HOLED

1

H27

H27 HOLED

HOLED

1

R52

H2 HOLEAH2HOLEA

H28

H28 HOLED

HOLED

@D80

@

CH751H-40_SC76

100K_0402_5%

H3 HOLEAH3HOLEA

1

H19

H19 HOLED

HOLED

1

E_STAR <17>

D80

1

2

0.1U_0402_16V4Z

1

21

+3VALW

5

1

U90

@ U90

@

SN74LVC1G14DCKR_SC70-5

P

NC

1 2

R53

@R53

@

C1623

@C1623

@

H4

H5

HOLEAH4HOLEA

HOLEAH5HOLEA

1

H21

H20

HOLED

1

H32

H32 HOLED

HOLED

1

Title

Size Document Number Rev

Date: Sheet

4

H8 HOLEAH8HOLEA

1

H23

H23 HOLED

HOLED

1

H34

H34 HOLED

HOLED

1

POK CKT

VCC_IDL <26>

H9 HOLEAH9HOLEA

1

H24

H24 HOLED

HOLED

1

H35

H35 HOLED

HOLED

1

H25

H25 HOLED

HOLED

1

H36

H36 HOLED

HOLED

1

41 57Tuesday, August 21, 2007

A2Y

G

3

H7

H6

HOLEAH7HOLEA

HOLEAH6HOLEA

1

H22

H22 HOLED

HOLED

1

H33

H33 HOLED

HOLED

1

Compal Electronics, Inc.

LA3262P_DIS__M64

H37

H37 HOLED

HOLED

1

1A

of

5

D D

4

3

2

1

+1.25VM

AC Adapter in

Page37

ACOK

C C

B B

VIN

BQ24703 Charger

Battery

VS

SWITCH

B+ B+

+5VALWP

ENBL2 ENBL1

MAINPWON

+3VALWP 4A

MAX8734A

+1.25VM

DC/DC (3V/5V)

VMB

VIN

Page40

+5VALWP 4A

VS

+3VLP 0.1A

MAX8743 DC/DC

Page38

B+

SLP_S3#

(1.05V/1.5V)

ENBL1/ENBL2

BATSELB_A

APL5912 LDO (1.05V)

B+

Page41

+1.05VS

Page46

+1.05VM

Page46

ISL6269 DC/DC (VDD_CORE)

Page45

+1.8VS

+1.5VSP 4.2A

+1.25VM 8A

+3VS

VDD_CORE

APL5912 LDO (PCIE_VDD)

Page45

G965 LDO (2.5V)

PCIE_VDD

Page41

+2.5VS 1A

+5VS

VCC SHDN#

ISL6260 &ISL6208 DC/DC (CPU_CORE)

+5VALWP

PWR_GD

Page43

CPU_CORE ( 44A)

Selector Circuit

Page39

BATSELB_A#

Battery A 6 Cell

VMB

Battery B 8 Cell

TPS51116

B+

DC/DC (+1.8VP/+0.9VSP)

VCC

+1.8VP 7A

SWITCH

A A

SWITCHSWITCH

Battery Connector

Page37 Page37

A

VMB_A VMB_B

Battery Connector B

SLP_S5#

S3/S5

Page42

+0.9VP 2A

BATT

Title

BATT_A

BATT_B

5

4

3

Title

POWER BLOCK DIAGRAM

Size Document Number Rev

Date: Sheet

2

of

42 57Tuesday, August 21, 2007

of

42 57Tuesday, August 21, 2007

of

42 57Tuesday, August 21, 2007

1

A

B

C

D

PCN1

9

SINGAL

GND6

8

1 1

PCN2

2 2

TYCO_C-1746706_6P

3 3

GND5

7

GND4

6

GND3

4

GND2

3

GND1

FOX_JPD113E-LB103-7F

1

BATT+

2

SMD

3

SMC

4

RES

5

TS

6

GND

220P_0402_25V8K

PCN3

BATT+

SMD SMC

B/I TS

GND

SUYIN_20163S-06G1-K

PWR1

PWR2

100_0402_5%

1 2

3 4 5

6

5

1

2

EC_SMD_A

EC_SMC_A

PR4

PC143

EC_SMD_B EC_SMC_B

AB/I_B TS_B

ADP_SIGNAL

12

PR5

100_0402_5%

12

ADPIN

12

PC144

220P_0402_25V8K

1K_0402_5%

PR11

PR11 1K_0402_5%

1K_0402_5%

1 2

12

PC1

100P_0402_50V8J

AB/I_A <44>

PR2

PR2 1M_0402_1%

1M_0402_1%

12

PR3

PR3 1K_0402_5%

1K_0402_5%

PC145

PC145 220P_0402_25V8K

220P_0402_25V8K

PR7

12

1 2

PR9

210K_0402_1%

SMB3025500YA_2P

1 2

PC2

PC2 1000P_0402_50V7K

1000P_0402_50V7K

12

+3VL

PL1

EC_SMD_A1 EC_SMC_A1

12

PC4

PC3

1000P_0402_50V7K

100P_0402_50V8J

VMB_A

12

PC5

PC5 1000P_0402_50V7K

1000P_0402_50V7K

VMB_B

FBM-L18-453215-900LMA90T_1812

12

PC8

PC8 1000P_0402_50V7K

1000P_0402_50V7K

PL2

FBM-L18-453215-900LMA90T_1812

1 2

AB1A_DATA <37> AB1A_CLK <37>

PL3

1 2

12

PC6

0.01U_0402_50V4Z

12

PC9

0.01U_0402_50V4Z

12

BATT_A

BATT_B

VIN

PR1

PR1 @15K_0402_5%

@15K_0402_5%

+3VL

12

PR10

210K_0402_1%

THM_MAIN# <37>

PR14

100_0402_5%

4 4

100_0402_5%

EC_SMD_B1

EC_SMC_B1

A

THM_MBAY# <37>

AB1B_DATA <37> AB1B_CLK <37>

Security Classification

2005/03/10 2006/03/10

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

B

2005/03/10 2006/03/10

Compal Secret Data

Deciphered Date

C

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

BATTERY CONN

LA3262P_DIS__M64

D

43 57Tuesday, August 21, 2007

of

12

PR15

PR14

A

B

C

D

1 1

2 2

3 3

4 4

VIN

PQ5

DTA144EUA_SC70

47K

2

1 2

PR18 47K_0402_5%PR18 47K_0402_5%

1 2

PC13

47P_0402_50V8J

220K_0402_5%

BATCAL#<50>

AC detector High 11.689V Low 9.879V

PR50

Airline detector High 17.521V Low 16.871V

13

PR36

PR40

12

PR45

PR45 130K_0402_1%

130K_0402_1%

12

10K_0603_1%

PC12

12

PR343

2

P2

12

100K_0603_1%

2.15K_0402_1%

1 2

12

12.4K_0603_1%

PC29

22P_0402_50V8J

12

G

PR39

12

0.1U_0603_16V7K

13

D

S

1 2

PQ3

PQ3 AO4407_SO8

AO4407_SO8

1 2 3 6

4

PR16

PR16 200K_0402_5%

200K_0402_5%

PQ93

PQ93 RHU002N06_SOT323

RHU002N06_SOT323

PR21

PR21 150K_0402_5%

150K_0402_5%

PD7

12

1SS355_SOD323

CHGCTRL<37,45>

ACDET

PR34

1 2

330K_0402_5%

VL

8

PU3A

3

P

+

O

2

-

G

LM393M_SO8

4

PR46

1 2

1M_0402_5%

8

PU3B

5

P

+

O

6

-

G

LM393M_SO8

4

PR54

1 2

33K_0402_1%

4

REF

CATHODE

5

ANODE

APL1431LBBC_SOT23-5

A

P2

8 7

5

ADP_EN# <50>

1 2

191K_0402_1%

1

7

VL

PU5

3 2

NC

1

NC

AO4407_SO8

8 7

5

4

PR19

1 2

ACDRV#

@RHU002N06_SOT323

0_0402_5%

SRSET<50>

PC18

+3VL

12

PR37

10K_0402_1%

2

+3VL

AC_CHG

1.24VREF

0_0402_5%

1 2

12

ADP_PRES

PR26

PQ4

1 2 36

PR398

PR398 @200K_0402_5%

@200K_0402_5%

1 2 12

ADP_PRES <29,37,45,46,50>

PR399

0_0402_5%

13

D

@150K_0402_5%

S

PR397

@0_0402_5%

AC_CHG

PR29

1 2

137K_0402_1%

PC23

1U_0603_10V6K

12

PC25

0.1U_0402_16V7K

O4I

1

NC

PC27

PC27 @0.1U_0402_16V7K

@0.1U_0402_16V7K

AC_CHG <45>

PQ10

ACDET

2

G

2

G

1 2

+3VL

12

PQ131

PR396

1U_0603_10V6K

+3VL

5

PU4

PU4 SN74LVC1G17DBVR_SOT23-5

SN74LVC1G17DBVR_SOT23-5

P

G

3

12

PR51

@47K_0402_1%

RHU002N06_SOT323

P4

0.015_2512_1%

1 2

12

PR22

12

100_0402_1%

PC43

4.7U_0805_25V6K

1K_0402_1%

ALARM

PR27

BQ24703VREF

12

PR30

100K_0402_1%

12

PC21

PR33

80.6K_0402_1%

ADP_PRES <29,37,45,46,50>

+3VL

12

PR43

4.7K_0402_5%

1 2

100K_0402_5%

13

D

2

G

S

PR20

1 2

PC16

1U_0603_10V6K

1 2

PR24

PR24 1K_0402_1%

1K_0402_1%

PR25

12

100K_0402_5%

4.7U_0805_10V4Z

150P_0402_50V8J

PR47

BQ24703VREF

12

PR49

PR49 100_0402_5%

100_0402_5%

13

D

PQ11

PQ11 RHU002N06_SOT323

RHU002N06_SOT323

S

PL4

FBM-L11-322513-151LMAT_1210

1 2

ACN<50>

PU2

8

ACN

9

ACP

26

ACDET

5

ENABLE

28

ACSEL

19

ALARM

2

SRSET

3

ACSET ACPRES27VHSP

13

IBAT

4

VREF

7

COMP

10

NC1

11

NC2

BQ24703_QFN28

12

PR35

PR35 150_0402_1%

150_0402_1%

12

PC24

12

PC26

4.7U_0805_10V6K

ALARM <45>

B

12

PC14

ACDRV#

PWM#

BATDRV#

BATSET BATDEP

PGND

29

PQ2

PQ2 AO4407_SO8

AO4407_SO8

1 2 3 6

P2B+

PR17

0_0402_5%

1 2

12

PC15

PC198

4.7U_0805_25V6K

4.7U_0805_25V6K RLZ16B_LL34

RLZ16B_LL34

ACDRV#

25 22

VCC

21 16

SRP

15

SRN

12

BATP

24 18

VS

20 6

1 17

GND

23

NC4

14

NC3

12

PC28

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4.7U_0805_25V6K

PD5

BATT

100P_0402_50V8J

2 1

12

PR42

PR42 196K_0402_1%

196K_0402_1%

12

PR382

25.5K_0402_1%

12

PR48

10K_0402_1%

12

PC17

1U_0805_25V4Z

DH_CHG

13

D

S

PQ110

RHU002N06_SOT323

8 7

5

4

CHG_B+

PR23

0_0402_5%

12

PC200

36

241

4.7U_0805_25V6K

BATT

12

PR44

5.62K_0603_0.1%

12

PR380

PR380 100K_0603_0.1%

100K_0603_0.1%

12

PR381

7.68K_0603_0.1%

PR360

2

G

2.8K_0603_0.1%

1 2

2005/03/10 2006/03/10

PQ7

FDS4435_SO8

578

LX_CHG

1 2

10UH_PCMB104T-100MS_6A_20%

PD8

PD8 SKS30-04AT_TSMA

SKS30-04AT_TSMA

2 1

SE_CHG+

SE_CHG-

12

PR383

200K_0402_1%

Compal Secret Data

Deciphered Date

C

BATT

PL5

13

D

PQ8 RHU002N06_SOT323

2

G

S

12

PR28

0.015_1206_1%

1 2

PR31

3K_0402_1%

PC22

1 2

0.1U_0402_16V7K

CELLSEL#

12

PR32

3K_0402_1%

12

BATT

PC19

4.7U_0805_25V6K

AB/I_A<43>

CV=12.6V(6 CELLS LI-ION)

1

16.8V(8 CELL LI-ION) CC=3A for 2.4AHr

PC20

2

CC=3.57A for 2.55AHr

10U_1206_25V6M

Icharger=3A CELLSEL# =0,Vcharger= 12.6V CELLSEL# =1,Vcharger= 16.8V

+3VL

2

G

12

PR384

100K_0402_5%

13

D

S

PQ112

RHU002N06_SOT323

+3VL

12

CELLSEL#

PR385

330K_0402_5%

PR386

1 2

330K_0402_5%

Title

Size Document Number Rev

Custom

Date: Sheet

13

D

2

G

S

I_A#<50>

PQ111

RHU002N06_SOT323

Compal Electronics, Inc.

Charger

LA3262P_DIS__M64

D

44 57Tuesday, August 21, 2007

CFET_B <45,50>

of

A

B

+3VL

C

D

1 1

+3VL

PC31

BATSELB_A

BATSELB_A#

2 2

3 3

CHGCTRL

1000P_0402_50V7K

4 4

PC31

1 2

1000P_0402_50V7K

PC33

1 2

1000P_0402_50V7K

PC180

1 2

PD17

CFET_A

2

CFET_B

3

RB715F_SOT323

PR59

1 2

RHU002N06_SOT323

PR60

1 2

PR342

1K_0402_5%

1

PQ14

22K_0402_5%

PQ15

22K_0402_5%

12

PR344

12

A

2

G

2

G

BATSELB_A#<37>

+3VL

PC35

12

PD14

470K_0402_5%

1SS355_SOD323

PR77

100K_0402_5%

1 2

13

D

RHU002N06_SOT323

S

13

D

S

12

PR70

1 2

470K_0402_5%

0.047U_0402_16V7K

13

D

2

G

S

PQ94

PQ94 RHU002N06_SOT323

RHU002N06_SOT323

+3VL

5

PU13

P

2

O4I

NC

G

SN74LVC1G17DBVR_SOT23-5

3

ALARM<44>

PR57

47K_0402_5%

PQ16

BATSELB_A#

AC_CHG<44>

1

+3VL

PQ16

5

P

A2Y

G

3

RHU002N06_SOT323

13

D

S

+3VL

5

A2Y

3

1

PU11

PU11 SN74LVC1G14DCKR_SC70-5

SN74LVC1G14DCKR_SC70-5

NC

4

BATCON <37>

5

PU7

1

P

INB

2

INA

G

74LVC1G02_04_SOT353

3

2

ADP_PRES <29,37,44,46,50>

G

1

PU9

P

G

BATSELB_A

NC

4

SN74LVC1G14DCKR_SC70-5

PR71

10K_0402_1%

PQ27

1 2

RHU002N06_SOT323

S

G

ADP_PRES

4

O

+3VL

1

5

PU8

P

NC

4

A2Y

G

SN74LVC1G14DCKR_SC70-5

3

D

13

2

12

PC34

220P_0402_50V7K

PR69

220K_0402_5%

BATSELB_A#

1

INB

2

INA

1 2

B

12

PC30

5

PU6

P

4

O

G

74LVC1G02_04_SOT353

3

LATCH

+3VL

PU10

5

1

P

IN1

O

2

IN2

G

3

SN74AHC1G08DCKR_SC70

+3VL

PU12

5

1

P

IN1

O

2

IN2

G

3

SN74AHC1G08DCKR_SC70

BATT_A

@0.1U_0402_10V6K

BATT_B

PQ13

+3VL

PQ13

S

RHU002N06_SOT323

G

PD9

2

1

PR55

3

RB715F_SOT323

D

13

2

PR55

1 2

100_0402_5%

12

PC32

RHU002N06_SOT323

12

PR58

1.5M_0402_5%

0.1U_0603_50V4Z

BATT

12

PR61

PR61 470K_0402_5%

470K_0402_5%

1

C

2

B

PQ18

E

PD12

PR63

1 2

10K_0402_5%

1SS355_SOD323

RHU002N06_SOT323

12

PR68

PR68 470K_0402_5%

470K_0402_5%

2

B

12

PD16

1 2

1SS355_SOD323

13

D

RHU002N06_SOT323

S

3

1

C

E

3

12

CFET_A

PR65

4

PR65

1 2

10K_0402_5%

PQ23

BATT_IN

2

G

CFET_B#

1 2

CFET_B<44,50>

BATT_IN

Issued Date

G

PR75

10K_0402_5%

CFET_B

PQ31

2

G

RHU002N06_SOT323

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

13

D

PQ20

2

G

S

13

D

S

BATT

PR74

10K_0402_5%

PQ28

2

G

13

D

RHU002N06_SOT323

S

2005/03/10 2006/03/10

PR62

PMBT2222_SOT23

470K_0402_5%

1 2

PR72

PMBT2222_SOT23

Deciphered Date

C

PR72

1 2

470K_0402_5%

PQ26

Compal Secret Data

3 6 2 1

1 2 3 6

PQ12

D

1 3

G

2

PD13

SX34-40_SMA

4

AO4407_SO8

PQ24

AO4407_SO8

4

PD15

SX34-40_SMA

PR56

S

1 2

0_0402_5%

2 1

RHU002N06_SOT323

21

5 7

8

PQ21

8 7

5

21

PD10

PD10 1SS355_SOD323

1SS355_SOD323

1 2

PD11

PD11 RLZ6.2C_LL34

RLZ6.2C_LL34

PQ17

BATT_IN

PQ19

5 7

8

AO4407_SO8

PQ25

AO4407_SO8

8 7

5

RHU002N06_SOT323

BATT_IN

13

D

2

G

S

13

D

2

G

4

PQ22

4

PQ29

2

G

PQ30

2

G

Custom

Date: Sheet

12

PR64

S

36 2 1

1 2 36

PR64

4.7K_0402_5%

12

PR66

PR66 470K_0402_5%

470K_0402_5%

12

PR67

PR67 470K_0402_5%

470K_0402_5%

BATT_A

BATT_B

12

PR73

4.7K_0402_5%

13

D

S

13

D

S

Compal Electronics, Inc.

Title

Size Document Number Rev

Compal Electronics, Inc.

Battery selector

LA3262P_DIS__M64

D

45 57Tuesday, August 21, 2007

of

A

B

C

D

E

+3.3V/+5V

B+

1 1

2 2

3 3

PL6

PL6 FBM-L11-322513-151LMAT_1210

FBM-L11-322513-151LMAT_1210

1 2

+5VALWP

12

PC197

22U_0805_6.3VAM

B++

12

PC38

2200P_0402_50V7K

4.7UH_SIQB745-4R7_4A_30%

PC36

0.1U_0603_50V4Z

1 2

1

PC39

2

10U_1206_25V6M

12

PL7

1

PR88

+

1 2

PC47

2

150U_B2_6.3VM

1 2

@10.2K_0402_1%

PR92

0_0402_5%

PR90

47K_0402_5%

D8D7D6D

S1S2S3G

D8D7D6D

S1S2S3G

B++

12

5

PQ34

PQ34 AO4468_SO8

AO4468_SO8

4

5

PQ126

PQ126 AO4468_SO8

AO4468_SO8

4

PC48

0.1U_0603_50V4Z

DH5

LX_5V

LX_5V <50>

DL5

12

PC52

0.1U_0603_50V4Z

RHU002N06_SOT323

BST5B BST3B

PR79

PR79 0_0402_5%

0_0402_5%

1 2

3

2

PD18

PD18 CHP202U_SC70

CHP202U_SC70

1

B++

VL

BST5A

2VREF_1999

1 2

0_0402_5%

0_0402_5% PR91

PR91

MAINPWON

1 2

PR93

1 2

@0_0402_5%

PC45

PR89

PR89 0_0402_5%

0_0402_5%

2VREF_1999

12

4.7U_0805_10V4Z

14

BST5

16

DH5

15

LX5

19

DL5

21

OUT5

9

FB5

1

N.C.

6

SHDN#

4

ON5

3

ON3

12

SKIP#

8

REF

PC50

12

0.1U_0603_50V4Z

PC46

13

20

18

V+

TON

LD05

PU14

MAX8734EEI_QSOP28

GND

LDO3

23

25

VL

12

PR97

PR97 499K_0402_1%

499K_0402_1%

PQ36

0.22U_0603_10V7K

+3VL

12

PR98

PR98 100K_0402_5%

100K_0402_5%

13

D

2

G

S

13

D

PQ37

S

RHU002N06_SOT323

2

G

+3VLP

12

PC51

4.7U_0805_10V4Z

VL

12

PC40

0.1U_0603_50V4Z

PR80

1 2

47_0402_5%

2VREF_1999

12

PC44

1U_0805_25V4Z

17

5

VCC

ILIM3

11

ILIM5

28

BST3

26

DH3

24

DL3

27

LX3

22

OUT3

7

FB3

2

PGOOD

PRO#

10

1 2

PR95

PR95 0_0402_5%

0_0402_5%

PGOOD

+3VLP

KBC_PWR_ON <37>

PR83

1 2

PR86

1 2

200K_0402_1%

499K_0402_1%

12

PR84

100K_0402_1%

PR87

1 2

499K_0402_1%

12

100K_0402_5%

100K_0402_5% PR242

PR242

PJP1

2 1

PAD-OPEN 2x2m

PR82

PR82 0_0402_5%

0_0402_5%

1 2

BST3A

+3VALWP

B++

+3VL

12

DH3

PC37

0.1U_0603_50V4Z

1 2

12

PC42

PC41

2200P_0402_50V7K

5

PQ35

AO4468_SO8

4.7U_0805_25V6K

PQ127

AO4468_SO8

LX3

D8D7D6D

S1S2S3G

4

5

D8D7D6D

S1S2S3G

4

DL3

12

PL8

4.7UH_SIQB745-4R7_4A_30%

+3VALWP

1

+

PC49

2

150U_B2_6.3VM

1 2

PR94

@3.57K_0402_1%

PR96

0_0402_5%

RHU002N06_SOT323

13

D

PQ77

2

G

S

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

ADP_PRES <29,37,44,45,50>

2005/03/01 2006/03/01

C

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

B

Date: Sheet

D

Date: Sheet

3.3V / 5V

3.3V / 5V LA3262P_DIS__M64

LA3262P_DIS__M64

1A

of

46 57Tuesday, August 21, 2007

E

A

1

DL_1.5V

PD30

1 2

1SS355_SOD323

PR123

12

PC53

2200P_0402_50V7K

CHP202U_SC70

PC59

0.1U_0603_50V4Z

DH_1.5V_2

2

PR103

2.2_0402_5%

1 2

12

PQ38

AO4468_SO8

1 1

AO4468_SO8

+1.5VSP

PL10

3.3UH_SIQB74-3R3RF_4.8A_30%

1

12

+

PC63

2 2

PC64

2

220U_B2_2.5VM

3.3UH_SIQB74-3R3RF_4.8A_30%

12

2.2U_0603_6.3V6K

2.2U_0603_6.3V6K PR106

PR106

5.1K_0402_1%

12

PR107

PR107 10K_0402_1%

10K_0402_1%

12

SLP_S3#<26,29,32,33,37,39,40,48,49,50,51,52>

3 3

5

D8D7D6D

S1S2S3G

4

5

D/K8D/K7D/K6D/K

S/A1S/A3G

S/A

4

2

PQ40

PQ40 AO4712_SO8

AO4712_SO8

1 2

0_0402_5%

B

MAX8743_B+

PR100

9

VDD

UVP

BST2

DH2 LX2 DL2 CS2

OUT2

FB2

ON2

PGOOD

TON

ILIM2 ILIM1

REF

10

20K_0402_1%

12

PC69

0.22U_0603_10V7K

+5VALW

12

21 19

18 17 20 16

15 14 12

7 5

13 3

PR113

12 12

PR114

100K_0402_1%

PR117

BST_1.25V_1

12

BST_1.25V_2

PR102

0_0402_5%

1 2

DH_1.25V_1

12

PC55

4.7U_0805_10V4Z

12

PR99

PC54

10U_1206_25V6M

1

PD19

3

2

BST_1.5V_1

1 2

PR101

0_0402_5%

BST_1.5V_2

12

DH_1.5V_1

MAX8743EEI_QSOP28

VCC_MAX8743

PC71

@0.001U_0402_50V7M

0_0402_5%

1U_0805_25V4Z

PC56

PC60

0.1U_0603_50V4Z

PU15

25 26 27

24 28

1 2

11

@0_0402_5%

PR99

12

BST1 DH1 LX1

DL1 CS1

OUT1 FB1

ON1

PR116

0_0402_5%

8

OVP

12

PR120

1 2

VCC_MAX8743

12

4

1U_0805_25V4Z

V+

GND

23

20_0603_5%

PC61

22

VCC

SKIP

6

2VREF

12

0.1U_0603_50V4Z

PR104

PR104 0_0402_5%

0_0402_5%

1 2

LX_1.25VLX_1.5V

0_0402_5%

PR118

100K_0402_1%

PC62

12

PR108

C

PL9

FBM-L11-322513-151LMAT_1210

PQ39

DL_1.25V

12

DH_1.25V_2

+3VALW

PQ39

1

D2

2

D2

3

G1

4

S1/A

SI4914_SO8

D1/S2/K D1/S2/K D1/S2/K

8

G2

7 6 5

PD31

1SS355_SOD323

12

PC70

@0.001U_0402_50V7M

12

PC57

2200P_0402_50V7K

PL11

3.3UH_SIQB74-3R3RF_4.8A_30%

1 2

12

PR121

PR121 0_0402_5%

0_0402_5%

D

12

PC58

4.7U_0805_25V6K

12

PR105

2.49K_0402_1%

12

PR111

10K_0402_1%

PM_SLP_M# <26,37,40,48,52>

B+

+1.25VMP

1

+

PC66

2

220U_B2_2.5VM

PJP11

PJP11 PAD-OPEN 2x2m

PAD-OPEN 2x2m

2 1 12

PC134

10U_0805_6.3V6M

PJP3

PJP6

+0.9VP

1 2

PAD-OPEN 3x3m

PJP16

PAD-OPEN 4x4m

1 2

PJP8

1 2

PAD-OPEN 3x3m

PJP15

2 1

PAD-OPEN 2x2m

+1.5VSP

+1.05V_VCCP

4 4

+1.05VMP +1.05VM

+1.5VS

(4A,160mils ,Via NO.=8)

(4A,160mils ,Via NO.= 8)

+VCCP

(2A,80mils ,Via NO.= 4)

+0.9V

+5VALWP

+3VALWP

+1.25VMP +1.25VM

(1A,40mils ,Via NO.= 2)

A

PJP3

1 2

PAD-OPEN 4x4m

PAD-OPEN 4x4m PJP5

PJP5

1 2

PAD-OPEN 4x4m

PAD-OPEN 4x4m PJP2

PJP2

1 2

PAD-OPEN 4x4m

B

+5VALW

(4.5A,180mils ,Via NO.= 9)

SLP_S3#<26,29,32,33,37,39,40,48,49,50,51,52>

+3VALW

(3A,120mils ,Via NO.= 6)

0.1U_0402_16V7K

(8A,320mils ,Via NO.= 16)

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2005/03/10 2006/03/10

Compal Secret Data

Deciphered Date

C

PR243

47K_0402_5%

1 2

PC170

12

PU26

VIN2VO

1

EN

5

GND

6

GND

G965-18P1U_SO8

3 4

ADJ

7

GND

8

GND

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

2.5VALW/1.5VS/1.25VMP

LA3262P_DIS__M64

D

12

PR244

13.7K_0603_1%

12

PR245

PR245 12K_0402_1%

12K_0402_1%

+2.5VS

12

PC135

PC135 10U_0805_6.3V6M

10U_0805_6.3V6M

of

47 57Tuesday, August 21, 2007

5

D D

4

3

2

1

DDR_B+

+1.8V

1

PC72

2200P_0402_50V7K

PL13

12

2

+5VALWP

12

PR124

0_1206_5%

12

PC75

10U_0805_10V4Z

C C

+0.9VP

V_DDR_MCH_REF<7,13,14>

+5VALW

B B

12

PC79

PC79 22U_0805_6.3VAM

22U_0805_6.3VAM

PR127

PR127 0_0402_5%

0_0402_5%

1 2

PC76

10U_0805_10V4Z

12

PC81

0.033U_0402_16V7K

23

24

1

2

3

4

5

6

8

9

VLDOIN

VTT

VTTGND

VTTSNS

GND

MODE

VTTREF

TPS51116RGE_QFN24

COMP

VDDQSNS

VDDQSET

7

NC

CS_GND

17

12

PU17

NC

VBST

DRVH

LL

DRVL

PGND

CS

V5FILT

PGOOD

S5

S3

V5IN

Thermal pad

15

25

BST_1.8V_1 BST_1.8V_2

22

21

20

19

18

16

14

13

11

10

DH_1.8V_1

PR125

0_0402_5%

1 2

PR126

0_0402_5%

1 2

12

PC82

4.7U_0805_10V4Z

LX_1.8V

DL_1.8V

PR131

PR132

PR133

PR134

PC74

0.1U_0603_50V4Z

1 2

DH_1.8V_2

12

PC83

0.001U_0402_50V7M

@0_0402_5%

12

0_0402_5%

12

@0_0402_5%

12

@0_0402_5%

12

PR129

20K_0603_1%

5

PQ45

D8D7D6D

AO4468_SO8

S1S2S3G

4

2.2UH_IHLP-2525CZ-01_8A_+-20%

1 2

5

D8D7D6D

PQ46

PQ46 AO4712_SO8

AO4712_SO8

S1S2S3G

4

PR130

3_0402_5%

12

SLP_S5# <26,40>

SLP_S4# <26,40>

SLP_S3# <26,29,32,33,37,39,40,47,49,50,51,52>

SLP_S4# <26,40>

PL12

FBM-L11-322513-151LMAT_1210

PC73

PC73 10U_1206_25V6M

10U_1206_25V6M

12

1

+

PC78

PC78 330U_D2E_2.5VM_R15

330U_D2E_2.5VM_R15

2

12

PC80

B+

+1.8V

12

14.3K_0603_1%

14.3K_0603_1% PR128

PR128

22P_0402_50V8J

PR387

0_0402_5%

12

PC84

@0.001U_0402_50V7M

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2005/03/10 2006/03/10

@0.001U_0402_50V7M

3

12

PC85

@0.001U_0402_50V7M

Compal Secret Data

Deciphered Date

1 2

PR317

0_0402_5%

PM_SLP_M# <26,37,40,47,52>

1 2

PR294

100K_0402_5%

+3VALW

1.8PGOOD <41>

2

12

10K_0603_0.1%

10K_0603_0.1% PR135

PR135

Compal Electronics, Inc.

Title

Size Document Number Rev

B

Date: Sheet

Compal Electronics, Inc.

1.8V/0.9VS

LA3262P_DIS__M64

48 57Tuesday, August 21, 2007

of

1

of

8

7

6

5

4

3

2

1

+CPU_B+

H H

PQ50

SI7840DP_SO8

+CPU_B+

PR149

PR149 10_0603_5%

10_0603_5%

4 3 5 6

1 2

9

8

VR_TT# RBIAS NTC SOFT

VID0 VID1 VID2 VID3 VID4 VID5 VID6

DPRSTP# DPRSLPVR PSI# PGD_IN CLK_EN# VR_ON VSEN RTN

VDIFF

FB

COMP

VW

0.01U_0402_25V7K

PR190

1 2

12

PC106

19

20

18

VIN

VSS

VDD

PU19

DFB15VO

DROOP

14

12

PC127

12

330P_0402_50V7K

+3VS

1 2

39

40

3V3

PGOOD

PWM1

ISEN1

PWM2

ISEN2

CS_GND

FCCM

PWM3

ISEN3

OCSET

VSUM

16

PR191

1K_0402_1%

PR155

1.91K_0603_1%

PGOOD_PU19<37>

ISL6260CRZ-T_QFN40

PWM1

27

ISEN1

23

PWM2

26

ISEN2

22

41

24

25

21

7

VSUM

17

12

PR186

PC123

4.53K_0402_1%

VO

12

PR177

0_0402_5%

1 2

0.22U_0603_16V7K

12

PC126

12

+5VS

11.5K_0402_1%

PC122

1 2

@1000P_0402_50V7K

12

0.1U_0402_16V7K

0.1U_0402_16V7K PH3

PH3

PR181

10KB_0603_5%_ERTJ1VR103J

12

PR185

12

1.96K_0402_1%

PR189

@1K_0402_1%

G G

+5VS

10_0603_5%

PR152

1 2

PC108

+VCCP

12

PR370

PR370 68_0402_5%

68_0402_5%

12

PH2

12

12 12 12 12

PR171

12

PR174

12

PD44

PD44 @1SS355_SOD323

@1SS355_SOD323

12

PR178

@0.1U_0402_16V7K

PC118

12

0_0402_5%

12

PR187

51K_0603_1%

PC125

12

1U_0603_10V6K

NTC

PC185

PC119

12

PR183

12

28 29 30 31 32 33 34

37 36

38 35

12

12 13

11

10

6.34K_0603_1%

F F

PC109

NTC

12

0.01U_0402_16V7K

H_PROCHOT#<4>

147K_0402_1%

E E

CPU_VID0<5> CPU_VID1<5> CPU_VID2<5> CPU_VID3<5> CPU_VID4<5> CPU_VID5<5> CPU_VID6<5>

H_DPRSTP#<5,7,25>

DPRSLPVR<7,26>

CLK_EN#<26>

H_PSI#<5>

PM_POK<37>

PWR_GD<21,26,31,37,40,41,50>

SLP_S3#

D D

,32,33,37,39,40,47,48,50,51,52>

PR160

4.22K_0603_1%

0.015U_0402_16V7K

147K_0402_1%

12

VCCSENSE<5>

+VCC_CORE

VSSSENSE<5>

C C

B B

PR179,PR180 are for test need when M/B is without CPU R1269,R1270 are same funtion with PR179,PR180 Layout Note: Use27.4 Ohm(PR318,PR319) routing for Vssense and Vccsense

PR319

@27.4_0402_1%

12

PR179

@10_0402_1%

PR182

180_0603_1%

1 2

220P_0402_25V8K

12

PC124

12

1800P_0402_50V7K

0_0402_5%

PR159

12

PC115

470KB_0402_5%_ERTJ0EV474J

12

PR162

12

0_0402_5%

PR164

12

0_0402_5%

PR166

12

0_0402_5%

PR169

12

0_0402_5%

PR172

12

0_0402_5%

1 2

PR328

1 2

@100_0402_5%

PR318

@27.4_0402_1%

1000P_0402_50V7K

PC120

1 2

PC121

0.022U_0402_16V7K

6.98K_0402_1%

PR158

PR161

0_0402_5%

PR163

0_0402_5%

PR165

0_0402_5%

PR168

0_0402_5%

499_0402_1%

0_0402_5%

12

1000P_0402_50V7K

PR184

1.2K_0402_1%

1000P_0402_50V7K

1000P_0402_50V7K PR188

PR188

12

PC104

1U_0603_10V6K

+5VS

12

PU18

5

VCC

6

FCCM

2

PWM

3

GND

ISL6208CRZ-T_QFN8

+5VS

PC114

1U_0603_10V6K

5 6 2 3

PU20

VCC FCCM PWM GND

ISL6208CRZ-T_QFN8

BOOT

UGATE

PHASE LGATE

BOOT UGATE PHASE LGATE

0_0402_5%

BST_CPU1_1

1 8 7 4

BST_CPU2_1

1

8

7

4

PR148

DH_CPU1 LX_CPU1

DL_CPU1

PR157

0_0402_5%

DH_CPU2 LX_CPU2

12

DL_CPU2

BST_CPU1_2

PC105

0.22U_0603_16V7K

1 2

12

BST_CPU2_2

0.22U_0603_16V7K

1 2

SI7840DP_SO8

PC116

PQ54

3 5

241

5

D8D7D6D

PQ52

S1S3G

S

IRF7832Z_SO8

4

2

3 5

241

D8D7D6D

PQ56

S1S3G

S

IRF7832Z_SO8

2

5

D8D7D6D

PQ53

S1S3G

S

IRF7832Z_SO8

4

2

5

D8D7D6D

PQ57

S1S3G

S

IRF7832Z_SO8

4

2

PC100

5

4

12

PC101

0.01U_0402_50V4Z

12

PR347

@4.7_1206_5%

1 2

PC190

12

PC110

0.01U_0402_50V4Z

PR349

12

2200P_0402_50V7K

@680P_0603_50V7K

PC111

2200P_0402_50V7K

12

@4.7_1206_5%

1 2

PC191

1

12

2

PC102

4.7U_1206_25V6K

PL16

.36UH_MPC1040LR36_ 24A_20%

1 2

PR151

10K_0402_1%

1 2

PR153

5.11K_0402_1%

1 2

VSUM

1

12

2

PC112

4.7U_1206_25V6K

.36UH_MPC1040LR36_ 24A_20%

PR170

10K_0402_1%

1 2

PR173

5.11K_0402_1%

1 2

VSUM

@680P_0603_50V7K

PC103

10U_1206_25V6M

0.22U_0603_16V7K

+CPU_B+

PC113

PC113 10U_1206_25V6M

10U_1206_25V6M

1 2

PL15

FBM-L18-453215-900LMA90T_1812

1 2

1

+

PC148

47U_25V_M

2

PR150

PR150 10_0402_1%

12

PC117

PR175

@0_0402_5%

10_0402_1%

1 2

VO

12

PC107

12

PR154

@0_0402_5%

PL17

0.22U_0603_16V7K

1 2

VO

PR167

PR167 10_0402_1%

10_0402_1%

B+

+VCC_CORE

A A

8

7

6

5

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4

2005/03/10 2006/03/10

Compal Secret Data

Deciphered Date

3

Compal Electronics, Inc.

Title

Size Document Number Rev

C

LA3262P_DIS__M64

Date: Sheet

2

CPU_CORE

of

49 57Tuesday, August 21, 2007

1

5

PU22A

8

D D

12

PC130

1U_0805_50V4Z

C C

ADP_SIGNAL

B B

A A

PR196

0_0402_5%

1 2

B+

12

PR240

0_0402_5%

1

LM358A_SO8

PR223

PR223 137K_0402_1%

137K_0402_1%

PR235

PR235 10K_0402_1%

10K_0402_1%

13

D

PQ65

S

@RHU002N06_SOT323

P

+

0

-

G

4

12

ADP_PRES<29,37,44,45,46>

PR229

PR229 1M_0402_5%

1M_0402_5%

1 2

29.4K_0402_1%

2

G

10K_0402_1%

5

3 2

PR212

PR212 0_0402_5%

0_0402_5%

47.5K_0402_1%

1 2

PR258

PR241

PR217

VIN

12

VIN

12

PR195

0_0402_5%

2

B

PR224

PR224 226K_0402_1%

226K_0402_1%

PR236

PR236 100K_0402_1%

100K_0402_1%

P4

1 2

PR199

10K_0402_1%

12

PC132

PQ61

C

MMBT3904_SOT323

ADP_PRES<29,37,44,45,46>

E

3 1

NDS0610_NL_SOT23-3

PR197

6.81K_0402_1%

0.1U_0402_16V7K

RHU002N06_SOT323

S

PQ62

G

5 6

PQ92

D

13

2

3 2

1M_0402_5%

8

P

+

-

G

4

2005.8.20

1 2

100K_0603_0.5%

2

VIN

+

-

1 2

PU25B

O

LM393M_SO8

PR200

4

REF

5

ANODE

APL1431LBBC_SOT23-5

13

D

G

S

8

PU25A

P

1

O

G

LM393M_SO8

4

PR238

7

4

PU22B

5 6

LM358A_SO8

1 2

0.027U_0603_16V7K

PU23

CATHODE

NC NC

PQ113

RHU002N06_SOT323

12

PR237

47K_0402_5%

PD23

1 2

1SS355_SOD323

4

+

0

-

PC129

3 2 1

13

D

2

G

S

+3VL

12

VIN

12

PR231

PR231 220K_0402_5%

220K_0402_5%

ADP_EN# <44>

7

12

PR206

7.87K_0402_1%

13

D

12

S

PR210

215_0603_1%

13

D

I_A# <44>

S

PD25

12

1SS355_SOD323

PR221

PR221 10K_0402_5%

10K_0402_5%

+3VL

12

PR230

47K_0402_5%

13

D

2

G

12

S

Security Classification

PR239

220K_0402_5%

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

12

PR259

PR259 1M_0402_1%

1M_0402_1%

PR202

2K_0402_5%

B

2

PR260

39.2K_0402_1%

2

G

PQ73

12

RHU002N06_SOT323

PR261

PR261 1M_0402_1%

1M_0402_1%

CFET_B <44,45>

PQ74

2

G

RHU002N06_SOT323

ADP_ID <37>

BATCAL# <44>SLP_S3#<26,29,32,33,37,39,40,47,48,49,51,52>

13

D

PQ95

2

G

RHU002N06_SOT323

G

RHU002N06_SOT323

S

ADP_EN <37>

PQ64

PQ64 RHU002N06_SOT323

RHU002N06_SOT323

Issued Date

12

E

3

PQ58

C

1

MMBT3906_SOT23

100K_0402_5%

3

+3VS

PR256

PR205

1 2

13

D

2

G

S

PR265

PR265 47K_0402_5%

47K_0402_5%

12

PR192

PR192 133K_0402_1%

133K_0402_1%

12

PR211

0_0402_5%

PQ60

PQ60 RHU002N06_SOT323

RHU002N06_SOT323

PR194

330K_0402_5%

12

8

PU21B

5

P

+

7

O

6

-

G

LM393M_SO8

4

PR201

1 2

0_0402_5%

12

PR207

3.9K_0402_5%

PD22

@CH751H-40_SOD323

1 2

PWR_GD <21,26,31,37,40,41,49>

12

1

PR214

2

PC147

3.9K_0402_5%

3.9K_0402_5% 3900P_0402_50V7K

3900P_0402_50V7K

1U_0603_10V6K

SRSET<44>

1 2

PR233

1 2

2005/03/10 2006/03/10

3

C

2

B

E

3 1

12

10K_0402_5%

PR215

1 2

470K_0402_5%

12

PC146

ACN <44>

PR225

PR225 @100K_0402_5%

@100K_0402_5%

PQ63

MMBT3904_SOT323

Compal Secret Data

Deciphered Date

12

80.6K_0402_1%

PC131

PR216

12

470K_0402_5%

+3VS

12

PR222

71.5K_0402_1%

12

PR228

PR228 21K_0603_1%

21K_0603_1%

12

PR234

3.48K_0402_1%

2

+5VS

3

+

2

-

0.01U_0402_16V7K

OCP# <4,26>

ACOCP_EN#<39>

12

2

PR193

1 2

100K_0402_5%

8

PU21A

P

1

O

G

LM393M_SO8

4

1 2

PR203

PR203 200K_0603_1%

200K_0603_1%

PC133

0.1U_0603_16V7K

1 2

1

NDS0610_NL_SOT23-3

PD20

CH751H-40_SOD323

+5VS

VIN

150K_0402_5%

1SS355_SOD323

PR255

1 2

1K_0402_5%

PR220

10K_0402_5%

PR232

21K_0603_1%

Title

Size Document Number Rev

Custom

Date: Sheet

1 2

12

PR257

10K_0402_5%

PQ70

DTA144EUA_SC70

47K

2 12

PR254

PD27

1 2

+5VS

PR219

1M_0402_5%

1 2

3

+

2

-

+5VS

PR226

1M_0402_5%

1 2

5

+

6

-

Compal Electronics, Inc.

LA3262P_DIS__M64

1 2

12

13

PD28

PD28 1SS355_SOD323

1SS355_SOD323

1 2 12

PR253

PR253 210K_0402_1%

210K_0402_1%

ADP_SIGNAL

PD26

1 2

1SS355_SOD323

8

PU24A

P

1

O

G

LM393M_SO8

4

8

PU24B

P

7

O

G

LM393M_SO8

4

ADP_OCP

NDS0610_NL_SOT23-3

PD21

CH751H-40_SOD323

PC128

1U_0805_25V4Z

PR208

PR208 10_0402_5%

10_0402_5%

LX_5V <46>

+3VS

PQ71

2

G

ADP_PRES <29,37,44,45,46>

+3VS

12

PR218

PR218 10K_0402_5%

10K_0402_5%

ADP_PS0 <37>

+3VS

12

PR227

PR227 10K_0402_5%

10K_0402_5%

ADP_PS1 <37>

50 57Tuesday, August 21, 2007

1

PQ72

D

1 3

G

2

12

220K_0402_5%

PR251

1 2

13

D

S

of

S

PD24

+5VS

12

1SS355_SOD323

RHU002N06_SOT323

PR252

220K_0402_5%

5

4

3

2

1

PR350

PR350 0_0402_5%

0_0402_5%

1 2

PC155

1U_0603_10V6K

PR391

1 2

10K_0402_5%

1U_0603_10V6K

B+_VGA

PC196

12

PC169

1000P_0402_50V7K

+5VALW

12

+5VALW

2

G

12

PC159

PR367

PR367 10_0402_5%

10_0402_5%

12

PR390

PR390 100K_0402_5%

100K_0402_5%

RHU002N06_SOT323

13

D

PQ120

S

RHU002N06_SOT323

12

PR351

1M_0402_5%

12

PR393

PR393 @100K_0402_5%

@100K_0402_5%

PU29

2

VCCA

6

VSSA

17

TPAD

7

PGND

4

PGD

NC

5

SC411MLTRT_MLPQ16_4x4

12

PR392

24.9K_0402_1%

13

D

PQ121

2

G

S

16

TON

15

14

EN/PSV

FB

3

12

+5VALW

PD43

PD43 1SS355_SOD323-2

1SS355_SOD323-2

1 2

VGA_BOOT

13

NC

BST

DH

LX

ILIM

VDDP

VOUT

DL

1

8

PR355

9.76K_0402_1%

PR346

PR346 0_0402_5%

0_0402_5%

12 11 10 9

PR354

1 2

10K_0402_1%

12

PC154

PC154 33P_0402_50V8J

33P_0402_50V8J

VGA_BOOT1

PR353

1 2

19.6K_0402_1%

1 2

PC168

PC168 1U_0603_10V6K

1U_0603_10V6K

1 2

PC151

0.1U_0402_16V7K

SLP_S3#<26,29,32,33,37,39,40,47,48,49,50,52>

VGA_UG

VGA_LX

PQ79

AO4712_SO8

VGA_LG

5

D8D7D6D

S1S2S3G

4

5

D/K8D/K7D/K6D/K

S/A1S/A3G

S/A

4

2

1 2

PR357

0_0402_5%

PC171

@0.1U_0402_16V7K

PQ78

PQ78 AO4468_SO8

AO4468_SO8

PD29

2 1

+3VS

12

PR356

PR356 10K_0402_1%

10K_0402_1%

12

APL5913-KAC-TRL_SO8

1UH_IHLP-2525CZ-01_11A_+-20%

1 2

PL19

@SX34_SMA

VGA_VCORE

+5VALW

12

6

PU31

7

POK

8

EN

VCNTL

GND

1

VIN

VIN VOUT VOUT

FB

5 9 3 4 2

49.9K_0402_1%

100K_0402_1%

1

+

PC157

2

330U_D2E_2.5VM_R9

PC160

PC160 1U_0603_10V6K

1U_0603_10V6K

12

PR358

12

PR359

VDD_CORE

+1.8V

12

PC161

PC161 10U_1206_6.3V6M

10U_1206_6.3V6M

PCIE_1.2V

12

PC162

PC162 22U_0805_6.3VAM

12

PC164

PC164 47P_0402_50V8J

47P_0402_50V8J

SET TO 1.2V FOR M62S,M71S (R342= 49.9K) SET TO 1.1V FOR M72S (R342 = 39.2K)

22U_0805_6.3VAM

PL18

FBM-L11-322513-151LMAT_1210

B+

D D

12

PC152

PC153

10U_1206_25V6M

4.7U_1206_25V6K

SLP_S3#<26,29,32,33,37,39,40,47,48,49,50,52>

@0.1U_0402_16V7K

+5VALW

12

PR345

470K_0402_5%

C C

POW_SW<19>

B B

For M64S POW_SW= "0": VDD_CORE=1.2V "1": VDD_CORE=1V

(For M62S POW_SW= "0": VDD_CORE=1.1V "1": VDD_CORE=0.95V PR355 change to 11K and PR392 change to 33.2K)

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/03/10 2006/03/10

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

VDD_CORE

LA3262P_DIS__M64

1

of

51 57Tuesday, August 21, 2007

5

4

3

2

1

+5VALW

12

D D

SLP_S3#<26,29,32,33,37,39,40,47,48,49,50,51>

+5VALW

PR137

@10K_0402_5%

12

PC97

1U_0603_10V6K

PR142

12

10_0402_5%

PD45

1000P_0402_50V7K

1 2

1SS355_SOD323

1 2

PR249

PR249 47K_0402_5%

47K_0402_5%

PC186

47P_0402_50V8J

VCCP_POK<41>

C C

SC411MLTRT_MLPQ16_4x4

PR368

1M_0402_5%

PC95

12

2 6

17

7 4

PU28

VCCA VSSA TPAD

PGND PGD

12

NC

5

16

TON

15

14

EN/PSV

FB

3

12

PD42

1 2

1SS355_SOD323-2

BOOT

1 2

13

NC

BST

DH

LX

ILIM

VDDP

VOUT

DL

1

8

PR144

1 2

11K_0402_1%

1 2

PR147

PR147 10K_0402_1%

10K_0402_1%

PR136

PR136 0_0402_5%

0_0402_5%

12 11 10 9

PC96

PC96 33P_0402_50V8J

33P_0402_50V8J

PR141

1 2

18.2K_0402_1%

12

PC91

PC91 1U_0603_10V6K

1U_0603_10V6K

1 2

PC90

0.1U_0402_16V7K

B+_VGA

12

PC89

PC199

4.7U_0805_25V6K

UGBOOT1

PQ47

1

D2

2

D2

3

G1

4

S1/A

SI4914_SO8

LX6269

LG

8

G2

7

D1/S2/K

6

D1/S2/K

5

D1/S2/K

3.3UH_SIQB74-3R3RF_4.8A_30%

1 2

PL14

+1.05V_VCCP

1

+

PC142

2

220U_B2_2.5VM

+5VALW

1 2

PR323

0_0402_5%

+3VALW

12

PR293

PR293 @10K_0402_1%

@10K_0402_1%

7

PR292

2

8

1 2

0_0402_5%

0_0402_5% APL5915KAI-TRL_SO8

APL5915KAI-TRL_SO8

PU27

POK

EN

12

PC139

PC139 1U_0603_10V6K

1U_0603_10V6K

6

5

VIN

9

VIN

VCNTL

3

VOUT

4

VOUT

2

FB

GND

1

150K_0402_1%

12

PR247

47K_0402_1%

12

PR248

Title

Size Document Number Rev

Custom

LA3262P_DIS__M64

Date: Sheet

+1.25VM

12

PC138

PC138 10U_0805_6.3V6M

10U_0805_6.3V6M

+1.05VMP

12

PC141

PC141 22U_0805_6.3VAM

12

PC140

PC140 27P_0402_50V8J

27P_0402_50V8J

Compal Electronics, Inc.

22U_0805_6.3VAM

+1.25VMP/+1.05V_VCCP

1

of

52 57Tuesday, August 21, 2007

B B

M_PROK<41>

PM_SLP_M#<26,37,40,47,48>

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/03/10 2006/03/10

Compal Secret Data

Deciphered Date

5

4

Version Change List ( P. I. R. List ) for Power Circuit

3

2

1

Request

Item

Page# Title

43 DCIN/

D D

1

2

3

4

5

6

8

C C

9

10

11

12

13

BATTERY CONN

44

Charger

50 ADP_OCP 50 2006/10/12 DB2

VDD_CORE

51

/PCIE_VDD

+1.25VMP/

52

+1.05V_VCCP

VDD_CORE

51

/PCIE_VDD

51 2006/11/08

/PCIE_VDD

51 VDD_CORE

/PCIE_VDD

48 2006/11/08

1.8V/0.9V Add PM_SLP_M# sequence Add PR387 SI

+1.25VMP/

52

+1.05V_VCCP

+1.25VMP/

52

+1.05V_VCCP

50 2007/2/28 SI2System identity Change PR223 from 147K to 137KADP_OCP

Date

2006/09/07

2006/10/12

2006/10/12 Fine tune PCIE_VDD

2006/11/08

2006/11/08Charger44 SI

2006/11/20 For HW's requirement, fine tune +2.5VS sequence

2007/2/28

Owner

HP R.L.

HW Tony J

PWR Francis H

HW Tony J

PWR Francis H HP

HW Tony J

Change charger control from HW to FW All the related components

Identify 65W adapter as "light" Change PR223 from 180K to 147KADP_OCP

Change VGA chipset from ATi M62S to M64S Change PR355 from 11K to 9.76K

For HW's requirement, fine tune +1.05V_VCCP sequence

Fine tune the GPU "Power Play" sequence

Fine tune the power sequence of PCIE_VDD Change PU31 pin5, 9 source from VDD_MEM18 to +1.8V Base on "Energy STAR" spec, reduce S5 and S3

power consumption (AC mode)

Fine tune the +2.5VS power level to 2.57V (typ) Change PR244 from 13K to 13.7K SI2

HP R.L.

Issue Description

Solution Description Cut in

Change PR392 from 33.2K to 24.9K

Change PR249 from 0 to 47K Add PC186 as 47pF Install PD45

Change PR358 from 47K to 49.9K Change PR359 from 150K to 100K

Add PC196 as 1uf

Uninstall PQ11

Change PR243 to 47K, Change PC170 to 0.1uF

DB1B

DB2

SIVDD_CORE

SI

44 PWR

14

B B

15

16

17

18

A A

VDD_CORE

51

/PCIE_VDD

2007/3/1

50 ADP_OCP 2007/4/12

44

Charger

46

3.3V/5V

47

1.5VS/1.25VM +1.25VMP/

48

1.8V/0.9V

51

VDD_CORE /PCIE_VDD

52

+1.25VMP/ +1.05V_VCCP

44 Charger

5

2007/7/30 For TI's suggestion, add 4.7u at VCC pin Add PC200 as 4.7u_0805

Francis H

PWR Francis H

HP R.L.

TI

Reserve circuit for testing Energy STARCharger 2007/3/1 Reserve PR397, PR398, PR399 and PQ131

MOSFET change for M64s (original design is for M72)

Fine tune system OCP setting for battery spec

Change some MLCCs size from 1206 to 08052007/7/30

4

3

Add PR396 as 0 ohm.

Change PQ78 from IRF7413Z to AO4468 Change PQ79 from IRF8113 to AO4712 Change PR353 from 6.81K to 19.6K

Change PR210 from 422 to 215 Change PC129 from .22u to .027u Change PR203 from 604K to 200K Change PC131 from .027u to .01u

1. Change PC14 from 10u_1206 to 4.7u_0805 Add PC198 as 4.7u_0805

2. Change PC89 from 10u_1206 to 4.7u_0805 Add PC199 as 4.7u_0805

3. Change PC15, PC19, PC42 and PC58 from 4.7u_1206 to 4.7u_0805

4. Change PC79, PC141, PC162 and PC197 from 22u_1206 to 22u_0805

5. Change PC134, PC135 and PC138 from 10u_1206 to 10u_0805

Title

PIR

Size Document Number Rev

Date: Sheet

2

Date: Sheet

PV

MV

MP

of

53 57Tuesday, August 21, 2007

of

53 57Tuesday, August 21, 2007

of

53 57Tuesday, August 21, 2007

1

5

4

3

2

1

M.B. Ver.Reason for change PAGE Modify ListFixed IssueItem

<2006.09.11>

D D

<2006.10.14>

C C

1

2

3

4

5

6

7

1

2

3

4

5

6

7

Dseign issue (Lost VRAM RST pin)

Dseign issue (LVDS channel error)

19 0.2

Swapped LVDS upper and lower channel

Dseign issue (HSYNC & VSYNC error) 19 Swapped VSYNC & HSYNC each other

34isolate ESD to CPU core via USB and 1394 conn's pin Add R4, R73 and R56

Follow ATI design suggestion for VDDR4, VDDR5 21 change and reserve two jopens for +1.8VS and +3VS power rails

Follow ATI design suggestion for DPLL_VDDC 21 delete R1892

40 Add +1.25VS, +3VS, +5VS and VDD_MEM18 delay circuits.

RGB signal EA failed and CRT display garbage 16, 19 Change CRT circuit from MAX9511 to RLC circuit.

RGB signal EA failed and CRT display garbage

Change CRT circuit from MAX9511 to RLC circuit.

39

Add Q/Switch circuit.

follow ATI power sequence 21 install R1898 aand C1605, uninstall R1897

VDD_MEM18 no power noise, remove 1206 size resister.23Increase VDD_MEM18 via holes

uninstall JP53, R1906, R1736 and Q13628Cancel Kill switch function on Chimay

re-define JP13 pins' assignment31change 1394 bus route on board

add R1794, R1795, R192436implement one 4MB SPI chip

0.220, 22 Add DRAM_RST# from VGA to VRAM

0.2

0.2follow ATI power sequence

0.3

8

<2006.11.20>

B B

A A

1

2

3

4

5

6

7

8

9

5

HP request, support Penryn CPU Add R23, R344

For Intel ES2 Crestline thermtrip pin. Add R27

For EMI request enable 27MHz_SSC 15 install R1687

For Intel ES2 NB 800/667M Hz issue 15 Add CLRP4, CLRP5 to select FSB speed. 0.4

For RTC Accuracy fail to change 25 Change C528, C516 to 15pf

Enable ACBS (power management for NIC) 29 0.4install Q102, uninstall R1612, Q104, Q105

Enable ACBS (power management for NIC) 30 0.4Change R1639 value to 1.87k

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

re-define KBC connector JP6 pins assignmentimplement 30pins KBC connector 38

Compal Secret Data

2006/09/25 2006/09/25

Compal Secret Data

Deciphered Date

2

Title

Size Document Number Rev

Custom

Date: Sheet

0.3

0.4

0.4 For detect CPU and system power saving 26 Add some components

0.426Solve auto-turn on install R1590 pull up to +3valw, uninstall R1727

HW PIR

HW PIR LA3262P_DIS__M64

LA3262P_DIS__M64

1

1A

of

54 57Tuesday, August 21, 2007

5

4

3

2

1

M.B. Ver.Reason for change PAGE Modify ListFixed IssueItem

<2006.11.20>

D D

<2007.01.25>

C C

10

11

12

13

1

2

3

4

5

6

7

8

9

10

Add Energy Star for CPU schematics

Enable ACBS (power management for NIC)

HP request

Follow ATI power sequence

For HP request 40 Add R1940 and pull up +3valw 0.5

For 3VL/VCC1_PWRGD glitch change 41 Add U5C and R1939 pull down

For KBC VCC2 connection to 3VS 37 install R1646, C75

For HP request

For HP request to install BGA CRACK components 27

For possible Leak during ACBS on PREP# signal 26 Change pull up to +3valw

For HP request to change Line-in BOM 32 R370, R369 change to 6.04k, R374, R375 change to 2.00k

For SIM connector supply chain 31 SIM connector footprint change

reserve R1931, R1934, R1933, C1622, U88, U90, R43,

41

R46, R52, R53, C1623, D80

Change R1732 pin2 from +3VM_Lan to +3VM

41

MDC power change to +3vs

38

40

25

Install D77, C1617, change R1919 to 10K

Add Q144 and R1935 instead of D75

12

change JP20 connector Footprint

38For solving Power wireset interfere Fan

7For Intel Crestline thermtrip shutdowm Reserve 0.1uf *1 for THERMTRIP#

0.4

0.5

11

12

B B

13

14

15

16

17

18

A A

19

5

For LMV331 supply chain, change to LMV393 41 change U76 & U86 to U91

For EMI changes for VGA CRT 16 Install C310,C313,C314,R542,R543,R544

For EMI changes for LED_LAN_DOCK 33 Add R1805,R1806

For HP request, change R1780.1 to UIM_PWR 31 change R1780.1 to UIM_PWR

For Intel NIC crystal design 29 Add R1936 30ohm value

For G-Sensor LED 26 HDD_HALTLED (R15) pull down

For Intel new design 26

Remove pull ups for STP_PCI# and STP_CPU# uninstall R1581, R1580

36

Add CLRP6 for SPI ROMFor HP request

17 Change C586 to 10uf_1206, add C1629 10uf_1206For VGA wavy isse 0.5

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/09/25 2006/09/25

Compal Secret Data

Deciphered Date

2

Title

Size Document Number Rev

Custom

Date: Sheet

0.5

HW PIR

HW PIR LA3262P_DIS__M64

LA3262P_DIS__M64

1

1A

of

55 57Tuesday, August 21, 2007

5

4

3

2

1

M.B. Ver.Reason for change PAGE Modify ListFixed IssueItem

<2007.02.14>

D D

1

2

3

4

5

6

7

8

Add FP power supply circuit for Vista

Enable ACBS (power management for NIC)

HP request

Follow ATI power sequence

For HP request 40 Add R1940 and pull up +3valw 0.5

For 3VL/VCC1_PWRGD glitch change 41 Add U5C and R1939 pull down

For KBC VCC2 connection to 3VS 37 install R1646, C75

For HP request

For HP request to install BGA CRACK components 27

C C

For possible Leak during ACBS on PREP# signal 26 Change pull up to +3valw

9

10

For HP request to change Line-in BOM 32 R370, R369 change to 6.04k, R374, R375 change to 2.00k

For SIM connector supply chain 31 SIM connector footprint change

reserve R1931, R1934, R1933, C1622, U88, U90, R43,

41

R46, R52, R53, C1623, D80

Change R1732 pin2 from +3VM_Lan to +3VM

41

MDC power change to +3vs

38

40

25

Install D77, C1617, change R1919 to 10K

Add Q144 and R1935 instead of D75

12

change JP20 connector Footprint

38For solving Power wireset interfere Fan

7For Intel Crestline thermtrip shutdowm Reserve 0.1uf *1 for THERMTRIP#

0.4

0.5

11

12

B B

13

14

15

16

17

18

A A

19

5

For LMV331 supply chain, change to LMV393 41 change U76 & U86 to U91

For EMI changes for VGA CRT 16 Install C310,C313,C314,R542,R543,R544

For EMI changes for LED_LAN_DOCK 33 Add R1805,R1806

For HP request, change R1780.1 to UIM_PWR 31 change R1780.1 to UIM_PWR

For Intel NIC crystal design 29 Add R1936 30ohm value

For G-Sensor LED 26 HDD_HALTLED (R15) pull down

For Intel new design 26

Remove pull ups for STP_PCI# and STP_CPU# uninstall R1581, R1580

36

Add CLRP6 for SPI ROMFor HP request

17 Change C586 to 10uf_1206, add C1629 10uf_1206For VGA wavy isse 0.5

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/09/25 2006/09/25

Compal Secret Data

Deciphered Date

2

Title

Size Document Number Rev

Custom

Date: Sheet

0.5

HW PIR

HW PIR LA3262P_DIS__M64

LA3262P_DIS__M64

1

1A

of

56 57Tuesday, August 21, 2007

<2007.08.02>

5

4

3

2

1

M.B. Ver.Reason for change PAGE Modify ListFixed IssueItem

Add R229 (non-install) and contact to THERM#_VGA

1

Solve VGA can not thermal shutdown and KB dissolve

4

1A

2

D D

3

prevent Cap crack to change Cap size

Solve VGA can not thermal shutdown and KB dissolve Add R1906 (non-install) and R1896 install

17

C1629 & C586 size change from 1206 to 0805

23

1A

Add Q30 & Q31

4

Prevent GPIO33 leakage

25

5

6

7

8

C C

9

10

11

12

B B

13

Change Q144 to CHP202U_SC70

1A

14

15

16

17

18

A A

19

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/09/25 2006/09/25

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

Date: Sheet

2

Date: Sheet

HW PIR

HW PIR LA3262P_DIS__M64

LA3262P_DIS__M64

1

1A

of

57 57Tuesday, August 21, 2007

COMPAL LA-3262P Schematics

Specifications and Main Features

Frequently Asked Questions

User Manual