COMPAL LA-3221P Schematics

A

1 1

B

C

D

E

2 2

Compal Confidential

Schematics Document

AMD/S1/ATI RS485M(C)/SB460

2005 / 12 / 30

3 3

Rev:0.1

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2005/12/1 2006/12/01

Compal Secret Data

Deciphered Date

Title

Cover Sheet

Size Document Number Rev

Custom

LA-3221P

D

Date: Sheet

E

143Friday, January 06, 2006

0.1

of

A

B

C

D

E

Compal confidential

Project Code: ANRHAL5000(HAL50)
File Name : LA-3221P

1 1

Thermal Sensor
ADM1032ARM

page 4 page 13

Clock Generator
ICS951462

CRT

page 14

AMD S1 CPU

page 4,5,6,7

HT 16x16 800MHZ

ATI-RS485M(C)

DDR-2 DDR2-SO-DIMM X2

page 8,9

Daul Channel DDR-2

LCD CONN

page 14

PCI EXPRESS

2 2

Realtek

RTL8111B

page 23

Mini Card

page 26

RJ45 CONN

page 23

PCI BUS

Mini PCI
Socket

page 26

3 3

CradBus Controller

R5C841 or R5C811

Slot 0

page 22

Meadia Card

page 22

page 21,22

1394
Conn.

page 21

LPC BUS

BGA465

page 10,11,12

A-Link Express

2 x PCIE

ATI-SB460

BGA549

page 15,16,17,18

USB 2.0

USB 2.0

HD-Interface

SATA

PATA

USB conn x 4

page 29

Felica Conn

page 28

Audio CKT
ALC262

page 24

MDC Conn.

page 24

AMP & Audio Jack

RJ11 CONN

page 27

SATA HDD Conn.

page 20

HDD Conn.
CDROM Conn.

page 20

page 25

Power On/Off CKT.

page 31

ENE KB910L

DC/DC Interface CKT.

page 33

Power Circuit DC/DC

page 33~41

4 4

RTC CKT.

page 15

Power OK CKT.

page 30

Touch Pad
CONN.

page 28

page 27

Int. KBD

page 28

BIOS

page 28

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2005/12/1 2006/12/01

Compal Secret Data

Deciphered Date

Title

Block Diagrams

Size Document Number Rev

Custom

LA-3221P

D

Date: Sheet

E

243Friday, January 06, 2006

0.1

of

A

Voltage Rails

Power Plane Description

VIN

1 1

2 2

B+
+CPU_CORE
+1.2V_HT
+0.9V 0.9V switched power rail for DDR terminator
+1.8VALW 1.8V always on power rail
+1.5VS
+1.8VS 1.8V switched power rail
+1.8V
+3VALW
+3V
+3VS
+5VALW
+5VS
+RTCVCC RTC power

Adapter power supply (19V)
AC or battery power rail for power circuit.
Core voltage for CPU

1.2V switched power rail

1.5V switched power rail

1.8V power rail for DDR

3.3V always on power rail

3.3V power rail

3.3V switched power rail
5V always on power rail
5V switched power rail

B

S1 S3 S4/ S5

ON ON ON

ON OFF
ON OFF
ON OFF
ON
ON OFF OFF
ON OFF OFF
ON
ON
ON
ON
ON

ON ONON

ONONON
OFF
OFF

ON

ONON

OFF

ON
ON ON

OFF

ON

OFF

OFF
ON

ON
OFFON

OFF

C

SIGNAL

STATE

Full ON

S1(Power On Suspend)

S3 (Suspend to RAM)

SLP_S1# SLP_S3#

HIGH HIGH HIGH HIGH

LOW

LOW

LOW

S4 (Suspend to Disk)

S5 (Soft OFF)

LOW LOW LOW LOW

Board ID Table for AD channel

Vcc 3.3V +/- 5%

Board ID

0
1
2
3
4
5
6
7 NC

100K +/- 5%Ra / Rc

Rb / Rd V min

0

8.2K +/- 5%
18K +/- 5%
33K +/- 5%
56K +/- 5%
100K +/- 5%
200K +/- 5%

AD_BID

0 V

0.216 V 0.250 V 0.289 V

0.436 V

0.712 V

1.036 V

1.453 V 1.650 V 1.759 V

1.935 V

2.500 V

D

SLP_S4# SLP_S5# +VALW +V +VS Clock

ON

ON

ON

OFF

OFF

V

AD_BID

ON ON

ON

OFF

OFF

OFF

max

LOW

OFF

OFF

OFF

HIGH

LOWLOWLOW

HIGHHIGHHIGH

HIGH

HIGH

V typ

AD_BID

ON

ON

ON

ON

ON

0 V 0 V

0.503 V

0.819 V

0.538 V

0.875 V

1.185 V 1.264 V

2.200 V

3.300 V

2.341 V

3.300 V

E

External PCI Devices

Device IDSEL# REQ#/GNT# Interrupts

CardBus
Mini-PCI

AD21
AD22

0
1

PIRQE/PIRQF/PIRQG
PIRQF/PIRQG

BOARD ID Table

Board ID

0
1
2

PCB Revision

0.1

BTO Item BOM Structure

BTO Option Table

3
4
5
6
7

EC SM Bus1 address

3 3

Device

Smart Battery
EEPROM(24C16/02)

(24C04)

Address Address

1010 000X b?
1011 000Xb?

EC SM Bus2 address

Device

ADM1032

1001 110X b?0001 011X b?

SB460 SM Bus address

Device

Clock Generator
(ICS 951462AGT)

DDRII DIMM0
DDRII DIMM2

4 4

Address

1101 001Xb?

1001 000Xb?
1001 010Xb?

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2005/12/1 2006/12/01

Compal Secret Data

Deciphered Date

Title

Notes

Size Document Number Rev

Custom

LA-3221P

D

Date: Sheet

E

343Friday, January 06, 2006

0.1

of

5

4

3

2

1

H_CADIP[0..15]10

H_CADIP[0..15]
H_CADIN[0..15]

H_CADOP[0..15]
H_CADON[0..15]

H_CADOP[0..15] 10
H_CADON[0..15] 10H_CADIN[0..15]10

PROCESSOR HYPERTRANSPORT INTERFACE

D D

C C

+1.2V_HT

AMD : 49.9 1%

B B

ATI : 51 1%

R226 49.9_0402_1%
R225 49.9_0402_1%

VLDT_Ax AND VLDT_Bx ARE CONNECTED TO THE LDT_RUN POWER
SUPPLY THROUGH THE PACKAGE OR ON THE DIE. IT IS ONLY CONNECTED
ON THE BOARD TO DECOUPLING NEAR THE CPU PACKAGE

H_CLKIP110
H_CLKIN110
H_CLKIP010
H_CLKIN010

1 2
1 2

H_CTLIP010
H_CTLIN010

+1.2V_HT B+_BIAS

D4

VLDT_A3

D3

VLDT_A2

D2

VLDT_A1

D1

VLDT_A0

H_CADIP15

N5

P5
M3
M4

L5
M5

K3

K4
H3
H4
G5
H5

F3

F4

E5

F5
N3
N2

L1
M1

L3

L2

J1

K1
G1
H1
G3
G2

E1

F1

E3

E2

J5

K5

J3

J2

P3

P4
N1

P1

+1.2V_HT

L0_CADIN_H15
L0_CADIN_L15
L0_CADIN_H14
L0_CADIN_L14
L0_CADIN_H13
L0_CADIN_L13
L0_CADIN_H12
L0_CADIN_L12
L0_CADIN_H11
L0_CADIN_L11
L0_CADIN_H10
L0_CADIN_L10
L0_CADIN_H9
L0_CADIN_L9
L0_CADIN_H8
L0_CADIN_L8
L0_CADIN_H7
L0_CADIN_L7
L0_CADIN_H6
L0_CADIN_L6
L0_CADIN_H5
L0_CADIN_L5
L0_CADIN_H4
L0_CADIN_L4
L0_CADIN_H3
L0_CADIN_L3
L0_CADIN_H2
L0_CADIN_L2
L0_CADIN_H1
L0_CADIN_L1
L0_CADIN_H0
L0_CADIN_L0

L0_CLKIN_H1
L0_CLKIN_L1
L0_CLKIN_H0
L0_CLKIN_L0

L0_CTLIN_H1
L0_CTLIN_L1

L0_CTLIN_H0
L0_CTLIN_L0

H_CADIN15
H_CADIP14
H_CADIN14
H_CADIP13
H_CADIN13
H_CADIP12
H_CADIN12
H_CADIP11
H_CADIN11
H_CADIP10
H_CADIN10
H_CADIP9
H_CADIN9
H_CADIP8
H_CADIN8
H_CADIP7
H_CADIN7
H_CADIP6
H_CADIN6
H_CADIP5
H_CADIN5
H_CADIP4
H_CADIN4
H_CADIP3
H_CADIN3
H_CADIP2
H_CADIN2
H_CADIP1
H_CADIN1
H_CADIP0
H_CADIN0

H_CLKIP1
H_CLKIN1
H_CLKIP0
H_CLKIN0

H_CTLIP0
H_CTLIN0

CPU1A

VLDT_B3
VLDT_B2
VLDT_B1
VLDT_B0

L0_CADOUT_H15
L0_CADOUT_L15
L0_CADOUT_H14
L0_CADOUT_L14
L0_CADOUT_H13
L0_CADOUT_L13
L0_CADOUT_H12
L0_CADOUT_L12
L0_CADOUT_H11
L0_CADOUT_L11
L0_CADOUT_H10
L0_CADOUT_L10

L0_CADOUT_H9
L0_CADOUT_L9
L0_CADOUT_H8
L0_CADOUT_L8
L0_CADOUT_H7
L0_CADOUT_L7
L0_CADOUT_H6
L0_CADOUT_L6
L0_CADOUT_H5
L0_CADOUT_L5
L0_CADOUT_H4
L0_CADOUT_L4
L0_CADOUT_H3
L0_CADOUT_L3
L0_CADOUT_H2
L0_CADOUT_L2
L0_CADOUT_H1
L0_CADOUT_L1
L0_CADOUT_H0

HTT Interface

L0_CADOUT_L0
L0_CLKOUT_H1

L0_CLKOUT_L1

L0_CLKOUT_H0

L0_CLKOUT_L0

L0_CTLOUT_H1
L0_CTLOUT_L1

L0_CTLOUT_H0
L0_CTLOUT_L0

Athlon 64 S1
Processor Socket

AE5
AE4
AE3
AE2

T4
T3
V5
U5
V4
V3
Y5
W5
AB5
AA5
AB4
AB3
AD5
AC5
AD4
AD3
T1
R1
U2
U3
V1
U1
W2
W3
AA2
AA3
AB1
AA1
AC2
AC3
AD1
AC1

Y4
Y3
Y1
W1

T5
R5

R2
R3

H_CADOP15
H_CADON15
H_CADOP14
H_CADON14
H_CADOP13
H_CADON13
H_CADOP12
H_CADON12
H_CADOP11
H_CADON11
H_CADOP10
H_CADON10
H_CADOP9
H_CADON9
H_CADOP8
H_CADON8
H_CADOP7
H_CADON7
H_CADOP6
H_CADON6
H_CADOP5
H_CADON5
H_CADOP4
H_CADON4
H_CADOP3
H_CADON3
H_CADOP2
H_CADON2
H_CADOP1
H_CADON1
H_CADOP0
H_CADON0

H_CLKOP1
H_CLKON1
H_CLKOP0
H_CLKON0

H_CTLOP0
H_CTLON0

1 2

C341 4.7U_0805_6.3V6K

H_CLKOP1 10
H_CLKON1 10
H_CLKOP0 10
H_CLKON0 10

H_CTLOP0 10
H_CTLON0 10

+5VS

12

1

C104

2

1U_0603_10V4Z

R28

100K_0402_5%

EN_DFAN127

1 2

FAN1VREF

3

+IN

2

FAN1_VFB

1

C94

2

1U_0603_10V4Z

R31

1 2

150K_0402_5%

-IN

C99

2200P_0402_50V7K

1 2

R29

100K_0402_5%

8

U4A

P

1

OUT

G

4

LM358DR2G_SO8~N

12

FAN1_ON

D7

RB751V_SOD323

2 1

R230
0_0805_5%

6

2

1

D

Q31

G

3

S

SI3456DV-T1_TSOP6

4 5

FAN1_POWER

1

1

2

C100

2

C96

22U_1206_10V4Z

1000P_0402_50V7K~N

FAN1 Control and Tachometer

+3VS

12

R231

10K_0402_5%

2

1

FAN_SPEED1 27

C607

0.01U_0402_16V7K

JFAN1

1
2
3

4

G

5

G

MOLEX_53398-0371~N

FAN1

1

1

C3734.7U_0805_6.3V6K

C3774.7U_0805_6.3V6K

2

2

A A

5

1

1

1

1

C3720.22U_0603_10V7K

C3760.22U_0603_10V7K

2

C374

C375

2

2

2

180P_0402_50V8J~N

180P_0402_50V8J~N

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/12/1 2006/12/01

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

Compal Electronics, Inc.

ATHLON64 HT I/F

LA-3221P

1

0.1

of

443Friday, January 06, 2006

A

B

C

D

E

VDD_VTT_SUS_CPU IS CONNECTED TO THE VDD_VTT_SUS POWER
SUPPLY THROUGH THE PACKAGE OR ON THE DIE. IT IS ONLY CONNECTED

ON THE BOARD TO DECOUPLING NEAR THE CPU PACKAGE

+1.8V

4 4

3 3

2 2

12

R215

39.2_0603_1%

12

R212

39.2_0603_1%

PLACE THEM CLOSE TO
CPU WITHIN 1"

DDR_CS3_DIMMA#8
DDR_CS2_DIMMA#8
DDR_CS1_DIMMA#8
DDR_CS0_DIMMA#8

DDR_CS3_DIMMB#9
DDR_CS2_DIMMB#9
DDR_CS1_DIMMB#9
DDR_CS0_DIMMB#9

DDR_CKE1_DIMMB9
DDR_CKE0_DIMMB9
DDR_CKE1_DIMMA8
DDR_CKE0_DIMMA8

DDR_A_MA[15..0]8

DDR_A_BS#28
DDR_A_BS#18
DDR_A_BS#08

DDR_A_RAS#8
DDR_A_CAS#8
DDR_A_WE#8

DDR_A_CLK2

DDR_A_CLK#2
DDR_A_CLK1

DDR_A_CLK#1

PLACE CLOSE TO PROCESSOR
WITHIN 1.5 INCH

TP1

M_ZN
M_ZP

1

C339

1.5P 50V F NPO 0402

2

1

C383

1.5P 50V F NPO 0402

2

+CPU_M_VREF

VTT_SENSE

DDR_CS3_DIMMA#
DDR_CS2_DIMMA#
DDR_CS1_DIMMA#
DDR_CS0_DIMMA#

DDR_CS3_DIMMB#
DDR_CS2_DIMMB#
DDR_CS1_DIMMB#
DDR_CS0_DIMMB#

DDR_CKE1_DIMMB
DDR_CKE0_DIMMB
DDR_CKE1_DIMMA
DDR_CKE0_DIMMA

DDR_A_MA15
DDR_A_MA14
DDR_A_MA13
DDR_A_MA12
DDR_A_MA11
DDR_A_MA10
DDR_A_MA9
DDR_A_MA8
DDR_A_MA7
DDR_A_MA6
DDR_A_MA5
DDR_A_MA4
DDR_A_MA3
DDR_A_MA2
DDR_A_MA1
DDR_A_MA0

DDR_A_BS#2
DDR_A_BS#1
DDR_A_BS#0

DDR_A_RAS#
DDR_A_CAS#
DDR_A_WE#

AE10
AF10

W17

Y10

V19
J22
V22
T19

Y26
J24

W24

U23
H26

J23
J20
J21

K19
K20
V24
K24
L20
R19
L19
L22

L21
M19
M20
M24
M22

N22

N21

R21

K22

R20

T22

T20

U20

U21

M_VREF
VTT_SENSE

M_ZN
M_ZP

MA0_CS_L3
MA0_CS_L2
MA0_CS_L1
MA0_CS_L0

MB0_CS_L3
MB0_CS_L2
MB0_CS_L1
MB0_CS_L0

MB_CKE1
MB_CKE0
MA_CKE1
MA_CKE0

MA_ADD15
MA_ADD14
MA_ADD13
MA_ADD12
MA_ADD11
MA_ADD10
MA_ADD9
MA_ADD8
MA_ADD7
MA_ADD6
MA_ADD5
MA_ADD4
MA_ADD3
MA_ADD2
MA_ADD1
MA_ADD0

MA_BANK2
MA_BANK1
MA_BANK0

MA_RAS_L
MA_CAS_L
MA_WE_L

Athlon 64 S1
Processor
Socket

CPU1B

VTT1
VTT2
VTT3
VTT4
VTT5
VTT6
VTT7
VTT8
VTT9

MA0_CLK_H2
MA0_CLK_L2
MA0_CLK_H1
MA0_CLK_L1

MB0_CLK_H2
MB0_CLK_L2
MB0_CLK_H1
MB0_CLK_L1

MB0_ODT1
MB0_ODT0
MA0_ODT1
MA0_ODT0

MB_ADD15
MB_ADD14
MB_ADD13
MB_ADD12
MB_ADD11
MB_ADD10

MB_ADD9

DDRII Cmd/Ctrl//Clk

MB_ADD8
MB_ADD7
MB_ADD6
MB_ADD5
MB_ADD4
MB_ADD3
MB_ADD2
MB_ADD1
MB_ADD0

MB_BANK2
MB_BANK1
MB_BANK0

MB_RAS_L
MB_CAS_L

MB_WE_L

DDR_B_CLK2

DDR_B_CLK#2
DDR_B_CLK1

DDR_B_CLK#1

PLACE CLOSE TO PROCESSOR
WITHIN 1.5 INCH

D10
C10
B10
AD10
W10
AC10
AB10
AA10
A10

Y16
AA16
E16
F16

AF18
AF17
A17
A18

W23
W26
V20
U19

J25
J26
W25
L23
L25
U25
L24
M26
L26
N23
N24
N25
N26
P24
P26
T24

K26
T26
U26

U24
V26
U22

+0.9V

DDR_A_CLK2
DDR_A_CLK#2
DDR_A_CLK1
DDR_A_CLK#1

DDR_B_CLK2
DDR_B_CLK#2
DDR_B_CLK1
DDR_B_CLK#1

DDR_B_ODT1
DDR_B_ODT0
DDR_A_ODT1
DDR_A_ODT0

DDR_B_MA15
DDR_B_MA14
DDR_B_MA13
DDR_B_MA12
DDR_B_MA11
DDR_B_MA10
DDR_B_MA9
DDR_B_MA8
DDR_B_MA7
DDR_B_MA6
DDR_B_MA5
DDR_B_MA4
DDR_B_MA3
DDR_B_MA2
DDR_B_MA1
DDR_B_MA0

DDR_B_BS#2
DDR_B_BS#1
DDR_B_BS#0

DDR_B_RAS#
DDR_B_CAS#
DDR_B_WE#

1

2

1

2

C340

1.5P 50V F NPO 0402

C382

1.5P 50V F NPO 0402

DDR_A_CLK2 8
DDR_A_CLK#2 8
DDR_A_CLK1 8
DDR_A_CLK#1 8

DDR_B_CLK2 9
DDR_B_CLK#2 9
DDR_B_CLK1 9
DDR_B_CLK#1 9

DDR_B_ODT1 9
DDR_B_ODT0 9
DDR_A_ODT1 8
DDR_A_ODT0 8

DDR_B_MA[15..0] 9

DDR_B_BS#2 9
DDR_B_BS#1 9
DDR_B_BS#0 9

DDR_B_RAS# 9
DDR_B_CAS# 9
DDR_B_WE# 9

Processor DDR2 Memory Interface

DDR_B_D[63..0]9

To reverse SODIMM socket

DDR_B_DM[7..0]9 DDR_A_DM[7..0] 8

DDR_B_DQS79
DDR_B_DQS#79
DDR_B_DQS69
DDR_B_DQS#69
DDR_B_DQS59
DDR_B_DQS#59
DDR_B_DQS49
DDR_B_DQS#49
DDR_B_DQS39
DDR_B_DQS#39
DDR_B_DQS29
DDR_B_DQS#29
DDR_B_DQS19
DDR_B_DQS#19
DDR_B_DQS09
DDR_B_DQS#09

DDR_B_D63
DDR_B_D62
DDR_B_D61
DDR_B_D60
DDR_B_D59
DDR_B_D58
DDR_B_D57
DDR_B_D56
DDR_B_D55
DDR_B_D54
DDR_B_D53
DDR_B_D52
DDR_B_D51
DDR_B_D50
DDR_B_D49
DDR_B_D48
DDR_B_D47
DDR_B_D46
DDR_B_D45
DDR_B_D44
DDR_B_D43
DDR_B_D42
DDR_B_D41
DDR_B_D40
DDR_B_D39
DDR_B_D38
DDR_B_D37
DDR_B_D36
DDR_B_D35
DDR_B_D34
DDR_B_D33
DDR_B_D32
DDR_B_D31
DDR_B_D30
DDR_B_D29
DDR_B_D28
DDR_B_D27
DDR_B_D26
DDR_B_D25
DDR_B_D24
DDR_B_D23
DDR_B_D22
DDR_B_D21
DDR_B_D20
DDR_B_D19
DDR_B_D18
DDR_B_D17
DDR_B_D16
DDR_B_D15
DDR_B_D14
DDR_B_D13
DDR_B_D12
DDR_B_D11
DDR_B_D10
DDR_B_D9
DDR_B_D8
DDR_B_D7
DDR_B_D6
DDR_B_D5
DDR_B_D4
DDR_B_D3
DDR_B_D2
DDR_B_D1
DDR_B_D0

DDR_B_DM7
DDR_B_DM6
DDR_B_DM5
DDR_B_DM4
DDR_B_DM3
DDR_B_DM2
DDR_B_DM1
DDR_B_DM0

DDR_B_DQS7
DDR_B_DQS#7
DDR_B_DQS6
DDR_B_DQS#6
DDR_B_DQS5
DDR_B_DQS#5
DDR_B_DQS4
DDR_B_DQS#4
DDR_B_DQS3
DDR_B_DQS#3
DDR_B_DQS2
DDR_B_DQS#2
DDR_B_DQS1
DDR_B_DQS#1
DDR_B_DQS0
DDR_B_DQS#0

AD11
AF11
AF14
AE14

AB11
AC12
AF13
AF15
AF16
AC18
AF19
AD14
AC14
AE18
AD18
AD20
AC20
AF23
AF24
AF20
AE20
AD22
AC22
AE25
AD26
AA25
AA26
AE24
AD24
AA23
AA24

AD12
AC16
AE22
AB26

AF12
AE12
AE16
AD16
AF21
AF22
AC25
AC26

Y11

G24
G23
D26
C26
G26
G25
E24
E23
C24
B24
C20
B20
C25
D24
A21
D20
D18
C18
D14
C14
A20
A19
A16
A15
A13
D12
E11
G11
B14
A14
A11
C11

E25
A22
B16
A12

F26
E26
A24
A23
D16
C16
C12
B12

MB_DATA63
MB_DATA62
MB_DATA61
MB_DATA60
MB_DATA59
MB_DATA58
MB_DATA57
MB_DATA56
MB_DATA55
MB_DATA54
MB_DATA53
MB_DATA52
MB_DATA51
MB_DATA50
MB_DATA49
MB_DATA48
MB_DATA47
MB_DATA46
MB_DATA45
MB_DATA44
MB_DATA43
MB_DATA42
MB_DATA41
MB_DATA40
MB_DATA39
MB_DATA38
MB_DATA37
MB_DATA36
MB_DATA35
MB_DATA34
MB_DATA33
MB_DATA32
MB_DATA31
MB_DATA30
MB_DATA29
MB_DATA28
MB_DATA27
MB_DATA26
MB_DATA25
MB_DATA24
MB_DATA23
MB_DATA22
MB_DATA21
MB_DATA20
MB_DATA19
MB_DATA18
MB_DATA17
MB_DATA16
MB_DATA15
MB_DATA14
MB_DATA13
MB_DATA12
MB_DATA11
MB_DATA10
MB_DATA9
MB_DATA8
MB_DATA7
MB_DATA6
MB_DATA5
MB_DATA4
MB_DATA3
MB_DATA2
MB_DATA1
MB_DATA0

MB_DM7
MB_DM6
MB_DM5
MB_DM4
MB_DM3
MB_DM2
MB_DM1
MB_DM0

MB_DQS_H7
MB_DQS_L7
MB_DQS_H6
MB_DQS_L6
MB_DQS_H5
MB_DQS_L5
MB_DQS_H4
MB_DQS_L4
MB_DQS_H3
MB_DQS_L3
MB_DQS_H2
MB_DQS_L2
MB_DQS_H1
MB_DQS_L1
MB_DQS_H0
MB_DQS_L0

CPU1C

DDRII Data

Athlon 64 S1
Processor Socket

MA_DATA63
MA_DATA62
MA_DATA61
MA_DATA60
MA_DATA59
MA_DATA58
MA_DATA57
MA_DATA56
MA_DATA55
MA_DATA54
MA_DATA53
MA_DATA52
MA_DATA51
MA_DATA50
MA_DATA49
MA_DATA48
MA_DATA47
MA_DATA46
MA_DATA45
MA_DATA44
MA_DATA43
MA_DATA42
MA_DATA41
MA_DATA40
MA_DATA39
MA_DATA38
MA_DATA37
MA_DATA36
MA_DATA35
MA_DATA34
MA_DATA33
MA_DATA32
MA_DATA31
MA_DATA30
MA_DATA29
MA_DATA28
MA_DATA27
MA_DATA26
MA_DATA25
MA_DATA24
MA_DATA23
MA_DATA22
MA_DATA21
MA_DATA20
MA_DATA19
MA_DATA18
MA_DATA17
MA_DATA16
MA_DATA15
MA_DATA14
MA_DATA13
MA_DATA12
MA_DATA11
MA_DATA10

MA_DATA9
MA_DATA8
MA_DATA7
MA_DATA6
MA_DATA5
MA_DATA4
MA_DATA3
MA_DATA2
MA_DATA1
MA_DATA0

MA_DM7
MA_DM6
MA_DM5
MA_DM4
MA_DM3
MA_DM2
MA_DM1
MA_DM0

MA_DQS_H7

MA_DQS_L7

MA_DQS_H6

MA_DQS_L6

MA_DQS_H5

MA_DQS_L5

MA_DQS_H4

MA_DQS_L4

MA_DQS_H3

MA_DQS_L3

MA_DQS_H2

MA_DQS_L2

MA_DQS_H1

MA_DQS_L1

MA_DQS_H0

MA_DQS_L0

AA12
AB12
AA14
AB14
W11
Y12
AD13
AB13
AD15
AB15
AB17
Y17
Y14
W14
W16
AD17
Y18
AD19
AD21
AB21
AB18
AA18
AA20
Y20
AA22
Y22
W21
W22
AA21
AB22
AB24
Y24
H22
H20
E22
E21
J19
H24
F22
F20
C23
B22
F18
E18
E20
D22
C19
G18
G17
C17
F14
E14
H17
E17
E15
H15
E13
C13
H12
H11
G14
H14
F12
G12

Y13
AB16
Y19
AC24
F24
E19
C15
E12

W12
W13
Y15
W15
AB19
AB20
AD23
AC23
G22
G21
C22
C21
G16
G15
G13
H13

DDR_A_D63
DDR_A_D62
DDR_A_D61
DDR_A_D60
DDR_A_D59
DDR_A_D58
DDR_A_D57
DDR_A_D56
DDR_A_D55
DDR_A_D54
DDR_A_D53
DDR_A_D52
DDR_A_D51
DDR_A_D50
DDR_A_D49
DDR_A_D48
DDR_A_D47
DDR_A_D46
DDR_A_D45
DDR_A_D44
DDR_A_D43
DDR_A_D42
DDR_A_D41
DDR_A_D40
DDR_A_D39
DDR_A_D38
DDR_A_D37
DDR_A_D36
DDR_A_D35
DDR_A_D34
DDR_A_D33
DDR_A_D32
DDR_A_D31
DDR_A_D30
DDR_A_D29
DDR_A_D28
DDR_A_D27
DDR_A_D26
DDR_A_D25
DDR_A_D24
DDR_A_D23
DDR_A_D22
DDR_A_D21
DDR_A_D20
DDR_A_D19
DDR_A_D18
DDR_A_D17
DDR_A_D16
DDR_A_D15
DDR_A_D14
DDR_A_D13
DDR_A_D12
DDR_A_D11
DDR_A_D10
DDR_A_D9
DDR_A_D8
DDR_A_D7
DDR_A_D6
DDR_A_D5
DDR_A_D4
DDR_A_D3
DDR_A_D2
DDR_A_D1
DDR_A_D0

DDR_A_DM7
DDR_A_DM6
DDR_A_DM5
DDR_A_DM4
DDR_A_DM3
DDR_A_DM2
DDR_A_DM1
DDR_A_DM0

DDR_A_DQS7
DDR_A_DQS#7
DDR_A_DQS6
DDR_A_DQS#6
DDR_A_DQS5
DDR_A_DQS#5
DDR_A_DQS4
DDR_A_DQS#4
DDR_A_DQS3
DDR_A_DQS#3
DDR_A_DQS2
DDR_A_DQS#2
DDR_A_DQS1
DDR_A_DQS#1
DDR_A_DQS0
DDR_A_DQS#0

DDR_A_D[63..0] 8

DDR_A_DQS7 8
DDR_A_DQS#7 8
DDR_A_DQS6 8
DDR_A_DQS#6 8
DDR_A_DQS5 8
DDR_A_DQS#5 8
DDR_A_DQS4 8
DDR_A_DQS#4 8
DDR_A_DQS3 8
DDR_A_DQS#3 8
DDR_A_DQS2 8
DDR_A_DQS#2 8
DDR_A_DQS1 8
DDR_A_DQS#1 8
DDR_A_DQS0 8
DDR_A_DQS#0 8

To normal SODIMM socket

A1

+1.8V

R27

1K_0402_1%

1 2

1 1

R26

1K_0402_1%

1 2

VDD_VREF_SUS_CPU

LAYOUT:PLACE CLOSE TO CPU

A

1

2

C35

0.1U_0402_16V4Z

+CPU_M_VREF

1

C36

2

1000P_0402_50V7K~N

B

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2005/12/1 2006/12/01

Compal Secret Data

Deciphered Date

D

Title

AMD CPU DDRII MEMORY I/F

Size Document Number Rev

Custom

LA-3221P

Date: Sheet

Athlon 64 S1g1

uPGA638
Top View

AF1

E

A26

543Friday, January 06, 2006

0.1

of

5

R238

@

0_0805_5%

R2390_0805_5%
1U_0603_10V4Z

C379

CPU_PWRGD16

LDT_STOP#11,16

LDT_RST#15
SB_PWRGD16,30

12
12

2

1

R232

470_0402_5%

D

@

S

300_0402_5%

300_0402_5%

300_0402_5%

LDT_RST#

R241 0_0402_5%

1
2

12

13

SYSON#

2

G

Q32
2N7002LT1G_SOT23

+1.8VS

12

R244

4.7K_0402_5%

+1.8VS

12

R57

+1.8VS

12

R242

12

5

U25

IN
GND
SHDN3BYP

G914E_SOT23-5

0.01U_0402_16V7K

+3VS

12

R243

@

1
2

TP49PAD
TP51PAD

TP12PAD
TP20PAD

TP18PAD
TP17PAD

TP46PAD
TP16PAD
TP45PAD
TP30PAD

5

OUT

4

C378

SYSON# 31,37

+1.8V

1 2

5

U27

P

IN1

O

IN2

G

NC7SZ08P5X_NL_SC70-5

3

+1.8V

5

U6

1

P

IN1

O

2

IN2

G

NC7SZ08P5X_NL_SC70-5

3

+1.8V

5

U26

1

P

IN1

O

2

IN2

G

NC7SZ08P5X_NL_SC70-5

3

+2.5VDDA

2

C393
1U_0603_10V4Z

1

1

2

C385 0.1U_0402_16V4Z

R236

4

1 2

CPU_ALL_PWROK

0_0402_5%

100U_6.3V_M

NC7SZ08P5X

C121 0.1U_0402_16V4Z

1 2

R50

4

1 2

CPU_LDTSTOP#

0_0402_5%

NC7SZ08P5X

C384 0.1U_0402_16V4Z

1 2

1 2

CPU_HT_RESET#

0_0402_5%

+1.8V

R206220_0402_5%

12

HDT_RST#

NC7SZ08P5X_NL_SC70-5

R235

4

NC7SZ08P5X

CPU_DBREQ#
CPU_DBRDY
CPU_TCK
CPU_TMS
CPU_TDI
CPU_TRST#
CPU_TDO

NOTE: HDT TERMINATION IS REQUIRED
FOR REV. Ax SILICON ONLY.

+3VALW

+3VS +2.5VDDA

D D

C C

ASIC8M_CPU_PWRGD

B B

CPUCLK0_H
CPUCLK0_L

CPU_VDD_FB_H
CPU_VDD_FB_L

CPU_TEST29_H_FBCLKOUT_P
CPU_TEST29_L_FBCLKOUT_N

CPU_ALL_PWROK
CPU_LDTSTOP#
CPU_HT_RESET#
CPU_THERMTRIP#_R

A A

C398

R208220_0402_5%

R207220_0402_5%

12

12

4

L24
LQG21F4R7N00_0805

1 2

1

+

2

R209220_0402_5%

R210220_0402_5%

12

12

+3VALW

U30

4

O

@

4

LAYOUT: ROUTE VDDA TRACE APPROX.
50 mils WIDE (USE 2x25 mil TRACES TO
EXIT BALL FIELD) AND 500 mils LONG.

3300P_0402_50V7K

1

1

C401

2

4.7U_0805_6.3V6K

1

C358

2

2

0.22U_0603_10V7K

place them to CPU within 1"

1 2

CPUCLK0_H13

CPUCLK0_L13

C390

1 2

C389 3900P_0402_50V7K

HDT Connector

JHDT1

2

1

4

3

6

5

8

7

10

9

12

11

14

13

16

15

18

17

20

19

22

21

2423
26

SAMTEC_ASP-68200-07

5

LDT_RST#

1

P

IN1

SB_PWRGD

2

IN2

G

3

CPU_+VDDA

C402

R219 300_0402_5%

1 2

R224 44.2_0402_1%

+1.2V_HT

R223 44.2_0402_1%

3900P_0402_50V7K

12

R234
169_0402_1%

TP15
TP19

TP23
TP21
TP13
TP44

TP33

TP42

THERMDC_CPU

THERMDA_CPU

TP3
TP5

TP7
TP10
TP9
TP11

TP39
TP40
TP6
TP8

HDT_RST#

3

ATHLON Control and Debug

CPU_HT_RESET#
CPU_ALL_PWROK
CPU_LDTSTOP#

CPU_SIC_R

1 2
1 2

CPU_VDD_FB_H38
CPU_VDD_FB_L38

TP2

CPU_CLKIN_SC_P
CPU_CLKIN_SC_N

TP26

CPU_DBRDY
CPU_TMS

CPU_TCK
CPU_TRST#
CPU_TDI

CPU_TEST25_H_BYPASSCLK_H
CPU_TEST25_L_BYPASSCLK_L
CPU_TEST19_PLLTEST0
CPU_TEST18_PLLTEST1

CPU_TEST17_BP3
CPU_TEST16_BP2
CPU_TEST15_BP1
CPU_TEST14_BP0
CPU_TEST12_SCANSHIFTENB

CPU_TEST07_ANALOG_T
CPU_TEST6_DIECRACKMON

CPU_TEST3_GATE0
CPU_TEST2_DRAIN0

CPU_RSVD_MA0_CLK3_P
CPU_RSVD_MA0_CLK3_N
CPU_RSVD_MA0_CLK0_P
CPU_RSVD_MA0_CLK0_N

CPU_RSVD_MB0_CLK3_P
CPU_RSVD_MB0_CLK3_N
CPU_RSVD_MB0_CLK0_P
CPU_RSVD_MB0_CLK0_N

CPU_HTREF1
CPU_HTREF0

VDDIOFB_H
VDDIOFB_L

F8

VDDA2

F9

VDDA1

B7

RESET_L

A7

PWROK

F10

LDTSTOP_L

AF4

SIC

AF5

SID

P6

HTREF1

R6

HTREF0

F6

VDD_FB_H

E6

VDD_FB_L

W9

VDDIO_FB_H

Y9

VDDIO_FB_L

A9

CLKIN_H

A8

CLKIN_L

G10

DBRDY

AA9

TMS

AC9

TCK

AD9

TRST_L

AF9

TDI
TEST25_HE9TEST29_H

E8

TEST25_L

G9

TEST19

H10

TEST18

AA7

TEST13

C2

TEST9

D7

TEST17

E7

TEST16

F7

TEST15

C7

TEST14

AC8

TEST12

C3

TEST7

AA6

TEST6

W7

THERMDC

W8

THERMDA

Y6

TEST3

AB6

TEST2

P20

RSVD0

P19

RSVD1

N20

RSVD2

N19

RSVD3

R26

RSVD4

R25

RSVD5

P22

RSVD6

R22

RSVD7

THERMDA_CPU

2200P_0402_50V7K

THERMDC_CPU

EC_SMB_CK227
EC_SMB_DA227

CPU1D

THERMTRIP_L

PROCHOT_L

VID5
VID4
VID3
VID2
VID1
VID0

CPU_PRESENT_L

PSI_L

DBREQ_L

TDO

TEST29_L

TEST24
TEST23

MISC

TEST22
TEST21
TEST20

TEST28_H

TEST28_L

TEST27
TEST26
TEST10

TEST8

RSVD8
RSVD9

RSVD10
RSVD11

RSVD12
RSVD13
RSVD14

RSVD15
RSVD16
RSVD17
RSVD18
RSVD19
RSVD20

1

C344

2

EC_SMB_CK2
EC_SMB_DA2

2

+1.8V

12

12

R213

R216

CPU_THERMTRIP#_R

AF6

CPU_PROCHOT#_1.8

AC7

VID5

A5

VID4

C6

VID3

A6

VID2

A4

VID1

C5

VID0

B5

CPU_PRESENT#

AC6

CPU_PSI#

A3

CPU_DBREQ#

E10

CPU_TDO

AE9

CPU_TEST29_H_FBCLKOUT_P

C9

CPU_TEST29_L_FBCLKOUT_N

C8

ROUTE AS 80 Ohm DIFFERENTIAL PAIR
PLACE IT CLOSE TO CPU WITHIN 1"

CPU_TEST24_SCANCLK1

AE7

CPU_TEST23_TSTUPD

AD7

CPU_TEST22_SCANSHIFTEN

AE8

CPU_TEST21_SCANEN

AB8

CPU_TEST20_SCANCLK2

AF7

CPU_TEST28_H_PLLCHRZ_P

J7

CPU_TEST28_L_PLLCHRZ_N

H8
AF8

CPU_TEST26_BURNIN#

AE6

CPU_TEST10_ANALOGOUT

K8

CPU_TEST08_DIG_T

C4

CPU_MA_RESET#

H16

CPU_MB_RESET#

B18

CPU_RSVD_VIDSTRB1

B3

CPU_RSVD_VIDSTRB0

C1

CPU_RSVD_VDDNB_FB_P

H6

CPU_RSVD_VDDNB_FB_N

G6

CPU_RSVD_CORE_TYPE

D5
R24

W18
R23

AMD NPT S1 SOCKET

AA8

Processor Socket

H18
H19

from EFL50

U24

2

D+

3

D-

8

SCLK

7

SDATA

ADM1032ARMZ MSOP 8P

+3VS

1

C342

0.1U_0402_16V4Z

2

VDD1

ALERT#

THERM#

GND

300_0402_5%

TP50

CPU_PSI# 38

1
6
4
5

SMBus Address: 1001110X (b)

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/12/1 2006/12/01

Compal Secret Data

Deciphered Date

2

+1.8V +3VALW

R240

Q30

300_0402_5%

1 2

300_0402_5%

3 1

MMBT3904_NL_SOT23

R46

80.6_0402_1%

1 2

TP27
TP31
TP29
TP32
TP28

TP35
TP36TP4

TP34
TP43

TP14
TP48

TP47
TP41

TP37
TP38
TP22

R376

R220

1 2
2

10K_0402_5%

1 2

VID5 38
VID4 38
VID3 38
VID2 38
VID1 38
VID0 38

CPU_PROCHOT#_1.8

4.7K_0402_5%

H_THERMTRIP# 16

CPU_TEST26_BURNIN#
CPU_PRESENT#
CPU_TEST25_H_BYPASSCLK_H

CPU_TEST21_SCANEN
CPU_TEST19_PLLTEST0
CPU_TEST25_L_BYPASSCLK_L
CPU_TEST18_PLLTEST1

1

+1.8V

+3VALW

R214

1 2

@

10K_0402_5%

CPU_PH_G

2

Q29

3 1

MMBT3904_NL_SOT23

@

Thermal Sensor

12

R222

10K_0402_5%@

THERM#

Title

Size Document Number Rev

Custom

Date: Sheet

ADM1032

Compal Electronics, Inc.

ATHLON64 CTRL & DEBUG

LA-3221P

1

R211

@

4.7K_0402_5%

1 2

CPU_PROCHOT#

R218 300_0402_5%

1 2

R217 1K_0402_5%

1 2

R47 510_0402_5%

1 2

R221 300_0402_5%

1 2

R49 300_0402_5%

1 2

R48 510_0402_5%

1 2

R51 300_0402_5%

1 2

643Friday, January 06, 2006

TP25

+1.8V

of

0.1

5

4

3

2

1

Ground

Athlon 64 S1
Processor Socket

1

C55

2

180P_0402_50V8J~N

180P_0402_50V8J~N

C380

1000P_0402_50V7K~N

CPU1F

VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77
VSS78
VSS79
VSS80
VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS97
VSS98

VSS99
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129

C81

C388

1000P_0402_50V7K~N

J6
J8
J10
J12
J14
J16
J18
K2
K7
K9
K11
K13
K15
K17
L6
L8
L10
L12
L14
L16
L18
M7
M9
M11
M17
N4
N8
N10
N16
N18
P2
P7
P9
P11
P17
R8
R10
R16
R18
T7
T9
T11
T13
T15
T17
U4
U6
U8
U10
U12
U14
U16
U18
V2
V7
V9
V11
V13
V15
V17
W6
Y21
Y23
N6

+1.8V

330U_D2E_2.5VM

330U_D2E_2.5VM

1

1

C79

C38

+

+

2

2

12C338

180P_0402_50V8J~N

2

1

180P_0402_50V8J~N

2

2

1

C335

1

C336

180P_0402_50V8J~N

180P_0402_50V8J~N

AA4

VSS1

AA11

VSS2

AA13

VSS3

AA15

VSS4

AA17

VSS5

AA19

+CPU_CORE +CPU_CORE

AC4

VDD1

AD2

VDD2

G4

VDD3

H2

D D

BOTTOMSIDE DECOUPLING

+CPU_CORE

330U_D2E_2.5VM

1

proadlizer 1200uF

C C

PLACE CLOSE TO SO-DIMM1 AS POSSIBLE

+1.8V

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

2

C72

B B

A A

+1.8V

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

2

C67

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

2

2

C66

C47

PLACE CLOSE TO SO-DIMM2 AS POSSIBLE

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

2

2

C88

C40

2

+

PC44
1200P_PFAF250E128MNTTE_2.5VM

3 4

+1.8V

1

1

C91

C48

2

2

22U_0805_6.3V6M

22U_0805_6.3V6M

0.1U_0402_16V4Z

1

2

C30

0.1U_0402_16V4Z

1

2

C62

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

2

2

C82

C37

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

2

2

C51

C350

1

2

1

2

C354

C349

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

2

C352

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

2

C347

C351

1

2

1

2

1

2

C57

C345

C330

1

C346

2

0.22U_0603_10V7K

0.1U_0402_16V4Z

1

2

C93

0.1U_0402_16V4Z

1

2

C76

330U_D2E_2.5VM

1

1

C331

+

+

2

2

0.22U_0603_10V7K

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

2

2

C60

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

2

2

C33

1

1

C84

C98

2

2

C52

C26

C43

4.7U_0805_6.3V6K

4.7U_0805_6.3V6K

1

1

C27

2

2

4.7U_0805_6.3V6K

4.7U_0805_6.3V6K

VDD4

J9

VDD5

J11

VDD6

J13

VDD7

K6

VDD8

K10

VDD9

K12

VDD10

K14

VDD11

L4

VDD12

L7

VDD13

L9

VDD14

L11

VDD15

L13

VDD16

M2

VDD17

M6

VDD18

M8

VDD19

M10

VDD20

N7

VDD21

N9

VDD22

N11

VDD23

P8

VDD24

P10

VDD25

R4

VDD26

R7

VDD27

R9

VDD28

R11

VDD29

T2

VDD30

T6

VDD31

T8

VDD32

T10

VDD33

T12

VDD34

T14

VDD35

U7

VDD36

U9

VDD37

U11

VDD38

U13

VDD39

V6

VDD40

V8

VDD41

V10

VDD42

C334

CPU1E

V12

VDD43

V14

VDD44

W4

VDD45

Y2

VDD46

J15

VDD47

K16

VDD48

L15

VDD49

M16

VDD50

P16

VDD51

T16

VDD52

U15

VDD53

V16

Athlon 64 S1
Processor Socket

VDD54

VDDIO1
VDDIO2
VDDIO3
VDDIO4
VDDIO5
VDDIO6
VDDIO7
VDDIO8
VDDIO9

VDDIO10

Power

VDDIO11
VDDIO12
VDDIO13
VDDIO14
VDDIO15
VDDIO16
VDDIO17
VDDIO18
VDDIO19
VDDIO20
VDDIO21
VDDIO22
VDDIO23
VDDIO24
VDDIO25
VDDIO26
VDDIO27

+1.8V+CPU_CORE

H25
J17
K18
K21
K23
K25
L17
M18
M21
M23
M25
N17
P18
P21
P23
P25
R17
T18
T21
T23
T25
U17
V18
V21
V23
V25
Y25

DECOUPLING BETWEEN PROCESSOR AND DIMMs
PLACE CLOSE TO PROCESSOR AS POSSIBLE

+1.8V

1

1

C343

2

+0.9V

1

1

C399

2

2

4.7U_0805_6.3V6K

1

C28

2

4.7U_0805_6.3V6K

1

C394

2

4.7U_0805_6.3V6K

1

C97

C359

2

2

4.7U_0805_6.3V6K

4.7U_0805_6.3V6K

1

1

C83

C29

2

2

4.7U_0805_6.3V6K

4.7U_0805_6.3V6K

1

1

C355

2

4.7U_0805_6.3V6K

1

C395

2

4.7U_0805_6.3V6K

1

1

C95

C348

2

0.22U_0603_10V7K

C400

0.22U_0603_10V7K

C353

2

0.22U_0603_10V7K

1

C333

2

0.22U_0603_10V7K

C86

2

0.22U_0603_10V7K

0.22U_0603_10V7K

1

1

C337

C332

2

2

0.22U_0603_10V7K

0.22U_0603_10V7K

VSS6

AB2

VSS7

AB7

VSS8

AB9

VSS9

AB23

VSS10

AB25

VSS11

AC11

VSS12

AC13

VSS13

AC15

VSS14

AC17

VSS15

AC19

VSS16

AC21

VSS17

AD6

VSS18

AD8

VSS19

AD25

VSS20

AE11

VSS21

AE13

VSS22

AE15

VSS23

AE17

VSS24

AE19

VSS25

AE21

VSS26

AE23

VSS27

B4

VSS28

B6

VSS29

B8

VSS30

B9

VSS31

B11

VSS32

B13

VSS33

B15

VSS34

B17

VSS35

B19

VSS36

B21

VSS37

B23

VSS38

B25

VSS39

D6

VSS40

D8

VSS41

D9

VSS42

D11

VSS43

D13

VSS44

D15

VSS45

D17

VSS46

D19

VSS47

D21

VSS48

D23

VSS49

D25

VSS50

E4

VSS51

F2

VSS52

F11

VSS53

F13

VSS54

F15

VSS55

F17

VSS56

F19

VSS57

F21

VSS58

F23

VSS59

F25

VSS60

H7

VSS61

H9

VSS62

H21

VSS63

H23

VSS64

J4

VSS65

1

C78

2

0.01U_0402_16V7K

0.01U_0402_16V7K

C381

C387

1000P_0402_50V7K~N

1000P_0402_50V7K~N

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/12/1 2006/12/01

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

Compal Electronics, Inc.

ATHLON64 PWR & GND

LA-3221P

1

0.1

of

743Friday, January 06, 2006

5

JDIM1

1

VREF

3

DDR_A_D0

D D

C C

DDR_CKE0_DIMMA5
DDR_CS2_DIMMA#5

DDR_A_BS#25

DDR_A_BS#05
DDR_A_WE#5

DDR_A_CAS#5
DDR_CS1_DIMMA#5

DDR_A_ODT15

B B

A A

SMB_CK_DAT19,13,16,26
SMB_CK_CLK19,13,16,26

DDR_A_D1
DDR_A_DQS#0

DDR_A_DQS0
DDR_A_D2

DDR_A_D3
DDR_A_D8

DDR_A_D9
DDR_A_DQS#1

DDR_A_DQS1
DDR_A_D10

DDR_A_D11

DDR_A_D16
DDR_A_D17

DDR_A_DQS#2
DDR_A_DQS2

DDR_A_D18 DDR_A_D22
DDR_A_D19

DDR_A_D24
DDR_A_D25

DDR_A_DM3

DDR_A_D26
DDR_A_D27

DDR_CKE0_DIMMA
DDR_CS2_DIMMA#

DDR_A_BS#2
DDR_A_MA12

DDR_A_MA9

DDR_A_MA5
DDR_A_MA3
DDR_A_MA1

DDR_A_MA10
DDR_A_BS#0
DDR_A_WE#

DDR_A_CAS#
DDR_CS1_DIMMA#

DDR_A_ODT1
DDR_A_D32

DDR_A_D33
DDR_A_DQS#4

DDR_A_DQS4
DDR_A_D34

DDR_A_D35
DDR_A_D40

DDR_A_D41
DDR_A_DM5
DDR_A_D42

DDR_A_D43 DDR_A_D47
DDR_A_D48

DDR_A_D49 DDR_A_D53

DDR_A_DQS#6
DDR_A_DQS6

DDR_A_D50
DDR_A_D51 DDR_A_D55

DDR_A_D56
DDR_A_D57

DDR_A_DM7
DDR_A_D58

DDR_A_D59
SMB_CK_DAT1

SMB_CK_CLK1

+3VS

5

VSS

5

DQ0

7

DQ1

9

VSS

11

DQS0#

13

DQS0

15

VSS

17

DQ2

19

DQ3

21

VSS

23

DQ8

25

DQ9

27

VSS

29

DQS1#

31

DQS1

33

VSS

35

DQ10

37

DQ11

39

VSS

41

VSS

43

DQ16

45

DQ17

47

VSS

49

DQS2#

51

DQS2

53

VSS

55

DQ18

57

DQ19

59

VSS

61

DQ24

63

DQ25

65

VSS

67

DM3

69

NC

71

VSS

73

DQ26

75

DQ27

77

VSS

79

CKE0

81

VDD

83

NC

85

BA2

87

VDD

89

A12

91

A9

93

A8

95

VDD

97

A5

99

A3

101

A1

103

VDD

105

A10/AP

107

BA0

109

WE#

111

VDD

113

CAS#

115

NC/S1#

117

VDD

119

NC/ODT1

121

VSS

123

DQ32

125

DQ33

127

VSS

129

DQS4#

131

DQS4

133

VSS

135

DQ34

137

DQ35

139

VSS

141

DQ40

143

DQ41

145

VSS

147

DM5

149

VSS

151

DQ42

153

DQ43

155

VSS

157

DQ48

159

DQ49

161

VSS

163

NC,TEST

165

VSS

167

DQS6#

169

DQS6

171

VSS

173

DQ50

175

DQ51

177

VSS

179

DQ56

181

DQ57

183

VSS

185

DM7

187

VSS

189

DQ58

191

DQ59

193

VSS

195

SDA

197

SCL

199

VDDSPD

P-TWO_A5692C-A0G16

VSS
DQ4
DQ5

VSS
DM0
VSS
DQ6
DQ7
VSS

DQ12
DQ13

VSS
DM1
VSS

CK0

CK0#

VSS

DQ14
DQ15

VSS

VSS

DQ20
DQ21

VSS
DM2

VSS

DQ22
DQ23

VSS

DQ28
DQ29

VSS

DQS3#

DQS3

VSS

DQ30
DQ31

VSS

NC/CKE1

VDD

NC/A15
NC/A14

VDD

A11

VDD

VDD

BA1

RAS#

S0#
VDD

ODT0

NC/A13

VDD
VSS

DQ36
DQ37

VSS
DM4
VSS

DQ38
DQ39

VSS

DQ44
DQ45

VSS

DQS5#

DQS5

VSS

DQ46
DQ47

VSS

DQ52
DQ53

VSS

CK1

CK1#

VSS
DM6
VSS

DQ54
DQ55

VSS

DQ60
DQ61

VSS

DQS7#

DQS7

VSS

DQ62
DQ63

VSS
SAO

SA1

4

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

42
44
46
48
50

NC

52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92

A7

94

A6

96
98

A4

100

A2

102

A0

104
106
108
110
112
114
116
118
120

NC

122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200

4

DDR_A_D4
DDR_A_D5

DDR_A_DM0
DDR_A_D6

DDR_A_D7
DDR_A_D12

DDR_A_D13
DDR_A_DM1
DDR_A_CLK1

DDR_A_CLK#1
DDR_A_D14

DDR_A_D15

DDR_A_D20
DDR_A_D21

DDR_A_DM2

DDR_A_D23
DDR_A_D28

DDR_A_D29
DDR_A_DQS#3

DDR_A_DQS3
DDR_A_D30

DDR_A_D31
DDR_CKE1_DIMMA
DDR_A_MA15

DDR_A_MA14
DDR_A_MA11

DDR_A_MA7
DDR_A_MA6DDR_A_MA8

DDR_A_MA4
DDR_A_MA2
DDR_A_MA0

DDR_A_BS#1
DDR_A_RAS#
DDR_CS0_DIMMA#

DDR_A_ODT0
DDR_A_MA13

DDR_CS3_DIMMA#
DDR_A_D36

DDR_A_D37
DDR_A_DM4
DDR_A_D38

DDR_A_D39
DDR_A_D44

DDR_A_D45
DDR_A_DQS#5

DDR_A_DQS5
DDR_A_D46

DDR_A_D52

DDR_A_CLK2
DDR_A_CLK#2

DDR_A_DM6
DDR_A_D54

DDR_A_D60
DDR_A_D61

DDR_A_DQS#7
DDR_A_DQS7

DDR_A_D62
DDR_A_D63

R13 0_0402_5%

12
12

R14 0_0402_5%

1

2

DDR_A_CLK1 5
DDR_A_CLK#1 5

DDR_CKE1_DIMMA 5

DDR_A_BS#1 5
DDR_A_RAS# 5
DDR_CS0_DIMMA# 5

DDR_A_ODT0 5

DDR_CS3_DIMMA# 5

DDR_A_CLK2 5
DDR_A_CLK#2 5

3

+1.8V+DIMM_VREF+1.8V+1.8V

R63

1

C147

C148

2

1000P_0402_50V7K~N

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

1K_0402_1%

1 2

0.1U_0402_16V4Z
R62

1K_0402_1%

1 2

2005/12/1 2006/12/01

+1.8V

0.1U_0402_16V4Z

1

2

C85

+0.9V

+0.9V

0.1U_0402_16V4Z

1

2

C59

Compal Secret Data

Deciphered Date

2

DDR_A_D[0..63]5

DDR_A_DM[0..7]5

DDR_A_DQS[0..7]5

DDR_A_MA[0..15]5

DDR_A_DQS#[0..7]5

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

2

C41

0.1U_0402_16V4Z

1

2

C34

0.1U_0402_16V4Z

1

1

2

2

C45

C73

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

2

2

C75

C63

2

DDR_A_D[0..63]
DDR_A_DM[0..7]
DDR_A_DQS[0..7]
DDR_A_MA[0..15]
DDR_A_DQS#[0..7]

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

2

C56

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

2

C89

DDR_CKE1_DIMMA
DDR_A_MA7
DDR_A_MA14
DDR_A_MA15

DDR_A_CAS#
DDR_A_MA10
DDR_A_BS#0
DDR_A_MA1

DDR_A_MA2
DDR_A_BS#1
DDR_A_MA0
DDR_A_RAS#

DDR_A_MA9
DDR_A_MA5
DDR_A_MA3
DDR_A_MA8

DDR_A_MA11
DDR_A_MA6
DDR_A_MA4

DDR_A_ODT1
DDR_CS1_DIMMA#

DDR_A_WE#

DDR_CS0_DIMMA#
DDR_A_MA13
DDR_A_ODT0
DDR_CS3_DIMMA#

DDR_A_BS#2
DDR_A_MA12
DDR_CKE0_DIMMA
DDR_CS2_DIMMA#

1

Layout Note:
Place one cap close to every 2 pullup
resistors terminated to +0.9V

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

1

2

C80

1

2

C49

47_0804_8P4R_5%

47_0804_8P4R_5%

47_0804_8P4R_5%

47_0804_8P4R_5%

47_0804_8P4R_5%

47_0804_8P4R_5%

Size Document Number Rev

Custom

Date: Sheet

2

2

C69

C54

Layout Note:
Place one cap close to every 2 pullup
resistors terminated to +0.9V

0.1U_0402_16V4Z

1

2

C31

RP14

47_0804_8P4R_5%

RP7

RP9

47_0804_8P4R_5%

RP13

RP10

RP5

RP4

RP16

Title

DDR2 SO-DIMM I

LA-3221P

0.1U_0402_16V4Z

1

2

18
27
36
45

18
27
36
45

18
27
36
45

18
27
36
45

18
27
36
45

18
27
36
45

18
27
36
45

18
27
36
45

+0.9V

330U_D2E_2.5VM

1

C70

+

C92

+0.9V

2

1

843Friday, January 06, 2006

0.1

of

5

4

3

2

1

DDR_B_D[0..63]
DDR_B_DM[0..7]
DDR_B_DQS[0..7]
DDR_B_MA[0..15]
DDR_B_DQS#[0..7]

0.1U_0402_16V4Z

1

2

C71

0.1U_0402_16V4Z

1

2

C74

DDR_CKE1_DIMMB
DDR_B_MA14
DDR_B_MA15
DDR_B_MA11

DDR_B_MA1
DDR_B_MA3
DDR_B_MA9
DDR_B_MA12

DDR_B_BS#0
DDR_B_MA10
DDR_B_WE#
DDR_B_MA5

DDR_B_MA2
DDR_B_BS#1
DDR_CS0_DIMMB#
DDR_B_RAS#

DDR_B_ODT0
DDR_B_MA13
DDR_CS3_DIMMB#

DDR_B_ODT1
DDR_CS1_DIMMB#
DDR_B_CAS#

DDR_B_MA7
DDR_B_MA0
DDR_B_MA6
DDR_B_MA4

DDR_B_BS#2
DDR_B_MA8
DDR_CKE0_DIMMB
DDR_CS2_DIMMB#

0.1U_0402_16V4Z

1

2

0.1U_0402_16V4Z

1

2

C32

C50

47_0804_8P4R_5%

47_0804_8P4R_5%

47_0804_8P4R_5%

47_0804_8P4R_5%

47_0804_8P4R_5%

47_0804_8P4R_5%

47_0804_8P4R_5%

47_0804_8P4R_5%

0.1U_0402_16V4Z

1

Layout Note:
Place one cap close to every 2 pullup

2

C44

resistors terminated to +0.9V

0.1U_0402_16V4Z

Layout Note:

1

Place one cap close to every 2 pullup
resistors terminated to +0.9V

2

C39

+0.9V

RP15

18
27
36
45

RP12

18
27
36
45

RP8

18
27
36
45

RP6

18
27
36
45

RP2

18
27
36
45

RP3

18
27
36
45

RP11

18
27
36
45

RP17

18
27
36
45

Title

DDR2 SO-DIMM II

Size Document Number Rev

Custom

LA-3221P

Date: Sheet

1

943Friday, January 06, 2006

0.1

of

0.1U_0402_16V4Z

1

2

C77

0.1U_0402_16V4Z

1

2

C46

Deciphered Date

DDR_B_D[0..63]5
DDR_B_DM[0..7]5

DDR_B_DQS[0..7]5
DDR_B_MA[0..15]5

DDR_B_DQS#[0..7]5

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

2

2

C61

C42

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

2

2

C64

C58

2

+DIMM_VREF+1.8V+1.8V

JDIM2

1

VREF

3

DDR_B_D0

D D

C C

DDR_CKE0_DIMMB5
DDR_CS2_DIMMB#5

DDR_B_BS#25

DDR_B_BS#05
DDR_B_WE#5

DDR_B_CAS#5
DDR_CS1_DIMMB#5

DDR_B_ODT15

B B

A A

SMB_CK_DAT18,13,16,26
SMB_CK_CLK18,13,16,26

DDR_B_D1
DDR_B_DQS#0

DDR_B_DQS0
DDR_B_D2

DDR_B_D3
DDR_B_D8

DDR_B_D9
DDR_B_DQS#1

DDR_B_DQS1
DDR_B_D10

DDR_B_D11

DDR_B_D16
DDR_B_D17

DDR_B_DQS#2
DDR_B_DQS2

DDR_B_D18 DDR_B_D22
DDR_B_D19

DDR_B_D24
DDR_B_D25

DDR_B_DM3

DDR_B_D26
DDR_B_D27

DDR_CKE0_DIMMB
DDR_CS2_DIMMB#

DDR_B_BS#2
DDR_B_MA12

DDR_B_MA9

DDR_B_MA5
DDR_B_MA3
DDR_B_MA1

DDR_B_MA10
DDR_B_BS#0
DDR_B_WE#

DDR_B_CAS#
DDR_CS1_DIMMB#

DDR_B_ODT1
DDR_B_D32

DDR_B_D33
DDR_B_DQS#4

DDR_B_DQS4
DDR_B_D34

DDR_B_D35
DDR_B_D40

DDR_B_D41
DDR_B_DM5
DDR_B_D42

DDR_B_D43 DDR_B_D47
DDR_B_D48

DDR_B_D49 DDR_B_D53

DDR_B_DQS#6
DDR_B_DQS6

DDR_B_D50
DDR_B_D51 DDR_B_D55

DDR_B_D56
DDR_B_D57

DDR_B_DM7
DDR_B_D58

DDR_B_D59
SMB_CK_DAT1

SMB_CK_CLK1

+3VS

5

VSS

5

DQ0

7

DQ1

9

VSS

11

DQS0#

13

DQS0

15

VSS

17

DQ2

19

DQ3

21

VSS

23

DQ8

25

DQ9

27

VSS

29

DQS1#

31

DQS1

33

VSS

35

DQ10

37

DQ11

39

VSS

41

VSS

43

DQ16

45

DQ17

47

VSS

49

DQS2#

51

DQS2

53

VSS

55

DQ18

57

DQ19

59

VSS

61

DQ24

63

DQ25

65

VSS

67

DM3

69

NC

71

VSS

73

DQ26

75

DQ27

77

VSS

79

CKE0

81

VDD

83

NC

85

BA2

87

VDD

89

A12

91

A9

93

A8

95

VDD

97

A5

99

A3

101

A1

103

VDD

105

A10/AP

107

BA0

109

WE#

111

VDD

113

CAS#

115

NC/S1#

117

VDD

119

NC/ODT1

121

VSS

123

DQ32

125

DQ33

127

VSS

129

DQS4#

131

DQS4

133

VSS

135

DQ34

137

DQ35

139

VSS

141

DQ40

143

DQ41

145

VSS

147

DM5

149

VSS

151

DQ42

153

DQ43

155

VSS

157

DQ48

159

DQ49

161

VSS

163

NC,TEST

165

VSS

167

DQS6#

169

DQS6

171

VSS

173

DQ50

175

DQ51

177

VSS

179

DQ56

181

DQ57

183

VSS

185

DM7

187

VSS

189

DQ58

191

DQ59

193

VSS

195

SDA

197

SCL

199

VDDSPD

P-TWO_A5652C-A0G16

CONN@

VSS
DQ4
DQ5
VSS
DM0
VSS
DQ6
DQ7

VSS
DQ12
DQ13

VSS

DM1

VSS

CK0

CK0#

VSS
DQ14
DQ15

VSS

VSS
DQ20
DQ21

VSS

DM2

VSS
DQ22
DQ23

VSS
DQ28
DQ29

VSS

DQS3#

DQS3

VSS
DQ30
DQ31

VSS

NC/CKE1

VDD

NC/A15
NC/A14

VDD

A11

VDD

VDD

BA1

RAS#

S0#

VDD
ODT0

NC/A13

VDD

VSS
DQ36
DQ37

VSS

DM4

VSS
DQ38
DQ39

VSS
DQ44
DQ45

VSS

DQS5#

DQS5

VSS
DQ46
DQ47

VSS
DQ52
DQ53

VSS

CK1

CK1#

VSS

DM6

VSS
DQ54
DQ55

VSS
DQ60
DQ61

VSS

DQS7#

DQS7

VSS
DQ62
DQ63

VSS

SAO

SA1

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

42
44
46
48
50

NC

52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92

A7

94

A6

96
98

A4

100

A2

102

A0

104
106
108
110
112
114
116
118
120

NC

122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200

4

DDR_B_D4
DDR_B_D5

DDR_B_DM0
DDR_B_D6

DDR_B_D7
DDR_B_D12

DDR_B_D13
DDR_B_DM1
DDR_B_CLK1

DDR_B_CLK#1
DDR_B_D14

DDR_B_D15

DDR_B_D20
DDR_B_D21

DDR_B_DM2

DDR_B_D23
DDR_B_D28

DDR_B_D29
DDR_B_DQS#3

DDR_B_DQS3
DDR_B_D30

DDR_B_D31
DDR_CKE1_DIMMB
DDR_B_MA15

DDR_B_MA14
DDR_B_MA11

DDR_B_MA7
DDR_B_MA6DDR_B_MA8

DDR_B_MA4
DDR_B_MA2
DDR_B_MA0

DDR_B_BS#1
DDR_B_RAS#
DDR_CS0_DIMMB#

DDR_B_ODT0
DDR_B_MA13

DDR_CS3_DIMMB#
DDR_B_D36

DDR_B_D37
DDR_B_DM4
DDR_B_D38

DDR_B_D39
DDR_B_D44

DDR_B_D45
DDR_B_DQS#5

DDR_B_DQS5
DDR_B_D46

DDR_B_D52

DDR_B_CLK2
DDR_B_CLK#2

DDR_B_DM6
DDR_B_D54

DDR_B_D60
DDR_B_D61

DDR_B_DQS#7
DDR_B_DQS7

DDR_B_D62
DDR_B_D63

R15 4.7K_0402_5%

1 2

R16 0_0402_5%

12

DDR_B_CLK1 5
DDR_B_CLK#1 5

DDR_CKE1_DIMMB 5

DDR_B_BS#1 5
DDR_B_RAS# 5
DDR_CS0_DIMMB# 5

DDR_B_ODT0 5

DDR_CS3_DIMMB# 5

DDR_B_CLK2 5
DDR_B_CLK#2 5

+3VS

1

C156

2

1000P_0402_50V7K~N

C53

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

+0.9V

0.1U_0402_16V4Z

330U_D2E_2.5VM

1

+

2

2005/12/1 2006/12/01

0.1U_0402_16V4Z

1

1

2

2

C87

C90

+1.8V

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

2

2

C68

C65

+0.9V

Compal Secret Data

5

D D

4

3

2

1

H_CADIP[0..15]4
H_CADIN[0..15]4

H_CADOP[0..15]4

H_CADON[0..15]4

NB1B

G5
G4

J8
J7
J4
J5
L8
L7
L4

W11
W12

AA11
AB11

W14
W15

AB12
AA12

AA14
AB14

L5
M8
M7
M4
M5

P8

P7

P4

P5
R4
R5
R7
R8
U4
U5

W4
W5

Y4

Y5

V9

W9
AB7
AB6

Y7

AA7
AB9

AA9

C C

PCIE_LAN_C_RX_P223
PCIE_LAN_C_RX_N223

PCIE_WLAN_C_RX_P126
PCIE_WLAN_C_RX_N126

B B

SB_RX0P15
SB_RX0N15

SB_RX1P15
SB_RX1N15

PCIE_LAN_C_RX_P2
PCIE_LAN_C_RX_N2

PCIE_WLAN_C_RX_P1
PCIE_WLAN_C_RX_N1

R36 10K_0402_1%

1 2

R32 8.25K_0402_1%

1 2

SB_RX0P
SB_RX0N

SB_RX1P
SB_RX1N

PART 2 OF 5

GFX_RX0P
GFX_RX0N
GFX_RX1P
GFX_RX1N
GFX_RX2P
GFX_RX2N
GFX_RX3P
GFX_RX3N
GFX_RX4P
GFX_RX4N
GFX_RX5P
GFX_RX5N
GFX_RX6P
GFX_RX6N
GFX_RX7P
GFX_RX7N
GFX_RX8P
GFX_RX8N
GFX_RX9P
GFX_RX9N
GFX_RX10P
GFX_RX10N
GFX_RX11P
GFX_RX11N
GFX_RX12P
GFX_RX12N
GFX_RX13P
GFX_RX13N
GFX_RX14P
GFX_RX14N
GFX_RX15P
GFX_RX15N

GPP_RX0P
GPP_RX0N

GPP_RX1P
GPP_RX1N

GPP_RX2P
GPP_RX2N

GPP_RX3P
GPP_RX3N

SB_RX0P
SB_RX0N

SB_RX1P
SB_RX1N

PCEH_ISET
PCEH_TXISET

216MSA4ALA12FG RS485M_BGA465

PCIE I/F GFX

PCIE I/F GPP

PCIE I/F SB

GFX_TX0P
GFX_TX0N
GFX_TX1P
GFX_TX1N
GFX_TX2P
GFX_TX2N
GFX_TX3P
GFX_TX3N
GFX_TX4P
GFX_TX4N
GFX_TX5P
GFX_TX5N
GFX_TX6P
GFX_TX6N
GFX_TX7P
GFX_TX7N
GFX_TX8P
GFX_TX8N
GFX_TX9P
GFX_TX9N

GFX_TX10P

GFX_TX10N

GFX_TX11P

GFX_TX11N

GFX_TX12P

GFX_TX12N

GFX_TX13P

GFX_TX13N

GFX_TX14P

GFX_TX14N

GFX_TX15P

GFX_TX15N

GPP_TX0P
GPP_TX0N

GPP_TX1P
GPP_TX1N

GPP_TX2P
GPP_TX2N

GPP_TX3P
GPP_TX3N

SB_TX0P

SB_TX0N

SB_TX1P

SB_TX1N

PCEH_PCAL

PCEH_NCAL

J1
H2
K2
K1
K3
L3
L1
L2
N2
N1
P2
P1
P3
R3
R1
R2
T2
U1
V2
V1
V3
W3
W1
W2
Y2
AA1
AA2
AB2
AB1
AC1
AE3
AE4

PCIE_LAN_TX_P2

AD8

PCIE_LAN_TX_N2

AE8
AD7

AE7
AD4

AE5
AD5

AD6

SB_TX0P_C

AE9
AD10

AC8
AD9

AD11
AE11

C367 0.1U_0402_16V4Z

SB_TX0N_C

C368 0.1U_0402_16V4Z

SB_TX1P_C

C365 0.1U_0402_16V4Z

SB_TX1N_C

C366 0.1U_0402_16V4Z

R228 150_0402_1%

1 2

R227 100_0402_1%

1 2

C363 0.1U_0402_16V4Z

1 2

C364 0.1U_0402_16V4Z

1 2

C361 0.1U_0402_16V4Z

1 2

C362 0.1U_0402_16V4Z

1 2

1 2
1 2

1 2
1 2

PCIE_LAN_C_TX_P2
PCIE_LAN_C_TX_N2

PCIE_WLAN_C_TX_P1PCIE_WLAN_TX_P1
PCIE_WLAN_C_TX_N1PCIE_WLAN_TX_N1

SB_TX0P
SB_TX0N

SB_TX1P
SB_TX1N

+1.2V_HT

PCIE_LAN_C_TX_P2 23

PCIE_LAN_C_TX_N2 23

PCIE_WLAN_C_TX_P1 26

PCIE_WLAN_C_TX_N1 26

SB_TX0P 15
SB_TX0N 15

SB_TX1P 15
SB_TX1N 15

H_CLKOP14
H_CLKON14

H_CLKOP04
H_CLKON04

H_CTLOP04
H_CTLON04

+1.2V_HT

H_CADOP15
H_CADON15
H_CADOP14
H_CADON14
H_CADOP13
H_CADON13
H_CADOP12
H_CADON12
H_CADOP11
H_CADON11
H_CADOP10
H_CADON10
H_CADOP9
H_CADON9
H_CADOP8
H_CADON8

H_CADOP7
H_CADON7
H_CADOP6
H_CADON6
H_CADOP5
H_CADON5
H_CADOP4
H_CADON4
H_CADOP3
H_CADON3
H_CADOP2
H_CADON2
H_CADOP1
H_CADON1
H_CADOP0
H_CADON0

R253 49.9_0402_1%

1 2

R249 49.9_0402_1%

1 2

H_CLKOP1

H_CLKON1

H_CLKOP0

H_CLKON0

H_CTLOP0
H_CTLON0

NB1A

R19

HT_RXCAD15P

R18

HT_RXCAD15N

R21

HT_RXCAD14P

R22

HT_RXCAD14N

U22

HT_RXCAD13P

U21

HT_RXCAD13N

U18

HT_RXCAD12P

U19

HT_RXCAD12N

W19

HT_RXCAD11P

W20

HT_RXCAD11N

AC21

HT_RXCAD10P

AB22

HT_RXCAD10N

AB20

HT_RXCAD9P

AA20

HT_RXCAD9N

AA19

HT_RXCAD8P

Y19

HT_RXCAD8N

T24

HT_RXCAD7P

R25

HT_RXCAD7N

U25

HT_RXCAD6P

U24

HT_RXCAD6N

V23

HT_RXCAD5P

U23

HT_RXCAD5N

V24

HT_RXCAD4P

V25

HT_RXCAD4N

AA25

HT_RXCAD3P

AA24

HT_RXCAD3N

AB23

HT_RXCAD2P

AA23

HT_RXCAD2N

AB24

HT_RXCAD1P

AB25

HT_RXCAD1N

AC24

HT_RXCAD0P

AC25

HT_RXCAD0N

W21

HT_RXCLK1P

W22

HT_RXCLK1N

Y24

HT_RXCLK0P

W25

HT_RXCLK0N

P24

HT_RXCTLP

P25

HT_RXCTLN

A24

HT_RXCALP

C24

HT_RXCALN

216MSA4ALA12FG RS485M_BGA465

H_CADIP[0..15]
H_CADIN[0..15]

H_CADOP[0..15]

H_CADON[0..15]

HT_TXCTLP
HT_TXCTLN

HT_TXCALP
HT_TXCALN

P21
P22
P18
P19
M22
M21
M18
M19
L18
L19
G22
G21
J20
J21
F21
F22

N24
N25
L25
M24
K25
K24
J23
K23
G25
H24
F25
F24
E23
F23
E24
E25

L21
L22

J24
J25

N23
P23

C25
D24

PART 1 OF 5

HT_TXCAD15P
HT_TXCAD15N
HT_TXCAD14P
HT_TXCAD14N
HT_TXCAD13P
HT_TXCAD13N
HT_TXCAD12P
HT_TXCAD12N
HT_TXCAD11P
HT_TXCAD11N
HT_TXCAD10P
HT_TXCAD10N

HT_TXCAD9P
HT_TXCAD9N
HT_TXCAD8P
HT_TXCAD8N

HT_TXCAD7P
HT_TXCAD7N
HT_TXCAD6P
HT_TXCAD6N
HT_TXCAD5P
HT_TXCAD5N
HT_TXCAD4P
HT_TXCAD4N
HT_TXCAD3P
HT_TXCAD3N
HT_TXCAD2P
HT_TXCAD2N
HT_TXCAD1P
HT_TXCAD1N
HT_TXCAD0P
HT_TXCAD0N

HT_TXCLK1P
HT_TXCLK1N

HYPER TRANSPORT CPU

I/F

HT_TXCLK0P
HT_TXCLK0N

H_CADIP15
H_CADIN15
H_CADIP14
H_CADIN14
H_CADIP13
H_CADIN13
H_CADIP12
H_CADIN12
H_CADIP11
H_CADIN11
H_CADIP10
H_CADIN10
H_CADIP9
H_CADIN9
H_CADIP8
H_CADIN8

H_CADIP7
H_CADIN7
H_CADIP6
H_CADIN6
H_CADIP5
H_CADIN5
H_CADIP4
H_CADIN4
H_CADIP3
H_CADIN3
H_CADIP2
H_CADIN2
H_CADIP1
H_CADIN1
H_CADIP0
H_CADIN0

H_CLKIP1
H_CLKIN1

H_CLKIP0
H_CLKIN0

H_CTLIP0

H_CTLIN0

R245 100_0402_1%

1 2

H_CLKIP1 4
H_CLKIN1 4

H_CLKIP0 4
H_CLKIN0 4

H_CTLIP0 4

H_CTLIN0 4

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/12/1 2006/12/01

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

RS480M-HT/VMEM
LA-3221P

1

0.1

of

10 43Friday, January 06, 2006

R59 150_0402_1%
R58 150_0402_1%
R54 150_0402_1%

+3VS

R262

1 2

1 2

4.7K_0402_5%

1 2
1 2
1 2

+1.8VS

+1.8VS

R260

4.7K_0402_5%

EDID_CLK_LCD
EDID_DAT_LCD

For Debug

U7

1

A0

2

A1

3

A2

4

VSS

AT24C04N-10SI-2.7_SO8

@

VGA_CRT_R
VGA_CRT_G
VGA_CRT_B

+1.8VS

L26

1 2

FBML10160808121LMT_0603

100U_D2_10VM

1 2

FBML10160808121LMT_0603

10U_0805_10V4Z

R60

1 2

150_0603_1%

10U_0805_10V4Z

8

VCC

7

WP

6

SCL

5

SDA

1

+

C406

2

L29

1U_0603_10V4Z

1

C429

2

1U_0603_10V4Z

1

C153

2

+3VS +3VS

1

C158

0.1U_0402_16V4Z

2

@

C419

10U_0805_10V4Z

R265

1 2

715_0402_1%

1

C420

2

1

C151

2

@

10U_0805_10V4Z

12

R72
10K_0402_5%

@

EDID_CLK_LCD

1

2

1

2

10U_0805_10V4Z

C152

+1.8VS

+3VS

FBML10160808121LMT_0603

+1.8VS

FBML10160808121LMT_0603

1

C418

2

1U_0603_10V4Z

VGA_CRT_VSYNC14
VGA_CRT_HSYNC14

VGA_DDC_CLK14
VGA_DDC_DATA14

@

C415

1

ALLOW_LDTSTOP15

2

NB_GFX_CLKP13

NB_GFX_CLKN13

R88 10K_0402_5%@
R90 10K_0402_5%@
R91 10K_0402_5%@
R89 10K_0402_5%@
R263 10K_0402_5%@
R264 10K_0402_5%@

BMREQ#15
EDID_CLK_LCD14
EDID_DAT_LCD14

+3VS

R86 4.7K_0402_5%

NB_STRAP_DATA16

FBML10160808121LMT_0603

12

R71
2K_0402_5%

NB_STRAP_DATA

12

R70
2K_0402_5%

@

26 ohm / 100MHz

L13

1 2

0.1U_0402_16V4Z

L31

1 2

0.1U_0402_16V4Z

VGA_CRT_R14
VGA_CRT_G14
VGA_CRT_B14

NB_PWRGD30

HTREFCLK13

NB_REFCLK13

SBLINKCLK13

SBLINKCLK#13

1 2

C414

NB_RST#15,20,23,26,27,40

12
12
12
12
12
12

L12

12

10U_0805_10V4Z

+AVDDI

1

2

10U_0805_10V4Z

12

12

EDID_CLK_LCD
EDID_DAT_LCD

12

C155

POWER PLAY
HI: 1.2V
LOW : 1.0V

+AVDD

1

1

C160

10U_0805_10V4Z

2

2

1

2

C422

+AVDDQ

VGA_CRT_R
VGA_CRT_G

VGA_CRT_B
VGA_CRT_VSYNC
VGA_CRT_HSYNC

VGA_DDC_CLK
VGA_DDC_DATA

+NB_PLLVDD

+NB_HTPVDD

NB_RST#

NB_PWRGD
NB_LDTSTOP#

ALLOW_LDTSTOP

R25010K_0402_5%

HTREFCLK

NB_REFCLK

NB_GFX_CLKP
NB_GFX_CLKN

SBLINKCLK

SBLINKCLK#

DFT_GPIO0
DFT_GPIO1
DFT_GPIO2
DFT_GPIO3
DFT_GPIO4
DFT_GPIO5

BMREQ#

R2614.7K_0402_5%

NB_STRAP_DATA

0.1U_0402_16V4Z

1

1

C146

2

2

GND_LVSSR

C161

R9610K_0402_5%

NB1C

B22

AVDD1

C22

AVDD2

G17

AVSSN1

H17

AVSSN2

A20

AVDDDI

B20

AVSSDI

A21

AVDDQ

A22

AVSSQ

C21

C_R

C20

Y_G

D19

COMP_B

E19

RED

F19

GREEN

G19

BLUE

C6

DACVSYNC

A5

DACHSYNC

B21

RSET

B6

DACSCL

A6

DACSDA

A10

PLLVDD

B10

PLLVSS

B24

HTPVDD

B25

HTPVSS

C10

SYSRESET#

C11

POWERGOOD

C5

LDTSTOP#

B5

ALLOW_LDTSTOP

C23

HTTSTCLK

B23

HTREFCLK

C2

TVCLKIN

B11

OSCIN

A11

OSCOUT

F2

GFX_CLKP

E1

GFX_CLKN

G1

SB_CLKP

G2

SB_CLKN

D6

DFT_GPIO0

D7

DFT_GPIO1

C8

DFT_GPIO2

C7

DFT_GPIO3

B8

DFT_GPIO4

A8

DFT_GPIO5

B2

BMREQb

A2

I2C_CLK

B4

I2C_DATA

AA15

THERMALDIODE_P

AB15

THERMALDIODE_N

C14

TMDS_HPD

B3

DDC_DATA

C3

TESTMODE

A3

STRP_DATA

216MSA4ALA12FG RS485M_BGA465

+LVDDR18A

R92
0_0805_5%

12

LVDSB0+

B14

LDT_STOP#6,16

TXOUT_L0P
TXOUT_L0N
TXOUT_L1P
TXOUT_L1N
TXOUT_L2P
TXOUT_L2N
TXOUT_L3P
TXOUT_L3N

TXOUT_U0P

TXOUT_U0N

TXOUT_U1P

TXOUT_U1N

TXOUT_U2P

TXOUT_U2N

TXOUT_U3P

TXOUT_U3N

TXCLK_LP
TXCLK_LN
TXCLK_UP
TXCLK_UN

LPVDD
LPVSS

LVDDR18D_1
LVDDR18D_2
LVDDR18A_1
LVDDR18A_2

LVSSR1
LVSSR3
LVSSR5
LVSSR6
LVSSR7
LVSSR8

LVSSR12
LVSSR13

LVDS_DIGON

LVDS_BLON
LVDS_BLEN

DVO_D0
DVO_D1
DVO_D2
DVO_D3
DVO_D4
DVO_D5
DVO_D6
DVO_D7
DVO_D8

DVO_D9
DVO_D10
DVO_D11

DVO_VSYNC

DVO_DE

DVO_HSYNC

DVO_IDCKP
DVO_IDCKN

PART 3 OF 5

CRT/TVOUT

PLL PWR

PM

CLOCKs

MIS.

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

LVDSB0-

B15

LVDSB1+

B13

LVDSB1-

A13

LVDSB2+

H14

LVDSB2-

G14
D17
E17

LVDSA0+

A15

LVDSA0-

B16

LVDSA1+

C17

LVDSA1-

C18

LVDSA2+

B17

LVDSA2-

A17
A18
B18

LVDSBC+

E15

LVDSBC-

D15

LVDSAC+

H15

LVDSAC-

G15
D14

E14

+LVDDR18D

A12
B12
C12

+LVDDR18A

C13
A16

A14
D12
C19
C15
C16

F14
F15

ENVDD

E12

ENABLT

G12
F12

AD14
AD15
AE15
AD16
AE16
AC17
AD18
AE19
AD19
AE20
AD20
AE21

AD13
AC13
AE13
AE17
AD17

+1.8VS

1 2

2

Q11

3 1

MMBT3904_NL_SOT23

2005/12/1 2006/12/01

+LPVDD

SUS_STAT#

R229

470K_0402_5%

R93

10K_0402_5%

R87

LVDSB0+ 14
LVDSB0- 14
LVDSB1+ 14
LVDSB1- 14
LVDSB2+ 14
LVDSB2- 14

LVDSA0+ 14
LVDSA0- 14
LVDSA1+ 14
LVDSA1- 14
LVDSA2+ 14
LVDSA2- 14

LVDSBC+ 14
LVDSBC- 14
LVDSAC+ 14
LVDSAC- 14

0.1U_0402_16V4Z
C413

GND_LVSSR

1 2

+3VS

12

1K_0402_5%

NB_LDTSTOP#

Compal Secret Data

0.1U_0402_16V4Z

C138

1

1

10U_0805_10V4Z

2

2

R56

Deciphered Date

1

2

1 2

FBML10160808121LMT_0603

C421

12

1K_0402_5%

+1.8VS

+1.8VS

+1.8VS

C118

330U_D2E_2.5VM

1

+

2

FBML10160808121LMT_0603

1

C139

10U_0805_10V4Z

2

L30

12

R55

1K_0402_5%

@

L8

1 2

ENVDD 14
ENABLT 14,27

RS485M STRAPS(Internal pull up)

DFT_GPIO1:LOAD ROM STRAPS #

*High, LOAD ROM STRAP DISABLE

Low, LOAD ROM STRAP ENABLE

DFT_GPIO2:HT LINK WIDTH

*High, 8 BIT

Low,RESERVED

DFT_GPIO3,4:HT LINK FREQ

GPIO3GPIO4
00
0
1

*

11

DFT_GPIO5:LOAD MEM STRAPS #

*High, LOAD MEM STRAP DISABLE

Low, LOAD MEM STRAP ENABLE

DESCRIPTION
RESERVED

1

RESERVED

0

RESERVED

200MHz

Title

Size Document Number Rev

Custom

Date: Sheet

RS480M VIDEO_IF/CLOCK GEN
LA-3221P

of

11 43Friday, January 06, 2006

0.1

5

+1.2V_HT

C360

12

+

330U_D2E_2.5VM

+

C35622U_A_4VM

12

+

C35722U_A_4VM

D D

L7

FBML10160808121LMT_0603

1 2

+1.8VS

R67
0_0805_5%

12

+3VS

C C

+1.8VS

B B

C105 1U 6.3V Z Y5V 0402
C102 1U_0402_6.3V4Z
C101 1U_0402_6.3V4Z
C108 1U_0402_6.3V4Z
C369 1U_0402_6.3V4Z

12
12

12

C14122U_1206_10V4Z

12

C1360.1U_0402_16V4Z

R30
0_0805_5%

12

1 2
1 2
1 2
1 2
1 2

NB_VDD18

NB_VDDR3

+1.8VS

+1.2V_HT

C37122U_A_4VM

12

C37022U_A_4VM

12

C1161U_0402_6.3V4Z

12

C1091U_0402_6.3V4Z

12

C1071U_0402_6.3V4Z

12

C1061U_0402_6.3V4Z

12

C1031U_0402_6.3V4Z

12

NB_VDDA18

NB_VDDA12

12

NB_VDDA18

C4164.7U_0805_6.3V6K

C1234.7U_0805_6.3V6K

C1320.1U_0402_16V4Z

12

+

+

4

NB1D

AE24
AD24
AD22
AB17
AE23

W17
AC18
AD21
AC19
AC20
AB19
AD23
AA17
AE25

AC12
AD12
AE12

AC11

Y17

J14
J15

AE2
AB3

U7

W7
AB4
AC3
AD2
AE1

E11
D11

E7
F7
F9

G9

D22

M1

PART 4 OF 5

VDD_HT1
VDD_HT2
VDD_HT5
VDD_HT6
VDD_HT9
VDD_HT10
VDD_HT11
VDD_HT12
VDD_HT13
VDD_HT14
VDD_HT15
VDD_HT16
VDD_HT17
VDD_HT18
VDD_HT19

VDD18_1
VDD18_2

VDDA18_1
VDDA18_2
VDDA18_3
VDDA18_4
VDDA18_5
VDDA18_6
VDDA18_7
VDDA18_8

VDDR3_2
VDDR3_1

VDDR_1
VDDR_2
VDDR_3

VDDA12/VDDPLL_1
VDDA12/VDDPLL_2
VSSA12/VSSPLL_1
VSSA12/VSSPLL_2

VDDHT_PKG
VDDA12_PKG1
VDDA12_PKG2

216MSA4ALA12FG RS485M_BGA465

+1.2V_HT

12

L11
FBML10160808121LMT_0603

NB_VDDA12

C1544.7U_0805_6.3V6K

1

2

VDDA_12_1
VDDA_12_2
VDDA_12_3
VDDA_12_4
VDDA_12_5
VDDA_12_6
VDDA_12_7
VDDA_12_8

VDDA_12_9
VDDA_12_10
VDDA_12_11
VDDA_12_12

POWER

C1340.1U_0402_16V4Z

C1440.1U_0402_16V4Z

1

1

2

2

VDDC_1
VDDC_2
VDDC_3
VDDC_4
VDDC_5
VDDC_6
VDDC_7
VDDC_8

VDDC_9
VDDC_10
VDDC_11
VDDC_12
VDDC_13
VDDC_14
VDDC_15
VDDC_16
VDDC_17
VDDC_18
VDDC_19
VDDC_20
VDDC_21
VDDC_22
VDDC_23
VDDC_24
VDDC_25
VDDC_26
VDDC_27
VDDC_28
VDDC_29
VDDC_30
VDDC_31
VDDC_32

3

+1.2V_HT

+

D1
G7
E2
C1
E3
D2
M9
F4
B1
D3
L9
E6

L11
L13
L15
M12
R15
M14
N11
N13
N15
J11
H11
P12
P14
R11
R13
A19
B19
U11
U14
P17
L17
J19
D20
G20
A9
B9
C9
D9
A7
A4
U12
U15

C408 22U_A_4VM
C404 22U_A_4VM

+NB_CORE

1

1

1

1

C1450.1U_0402_16V4Z

C1430.1U_0402_16V4Z

C1170.1U_0402_16V4Z

C1420.1U_0402_16V4Z

2

2

2

2

1 2
1 2

1

C1130.1U_0402_16V4Z

2

1

C1120.1U_0402_16V4Z

2

+

12
12
12
12
12

1

C1140.1U_0402_16V4Z

2

C1371U_0402_6.3V4Z
C1271U_0402_6.3V4Z
C1401U_0402_6.3V4Z
C1351U_0402_6.3V4Z
C1301U_0402_6.3V4Z

+RS480_COREP

1

JNB1

1

JUMP_43X118

2

2

1

1

C1260.1U_0402_16V4Z

C4170.1U_0402_16V4Z

2

2

A25

F11

D23

E9
G11
Y23
P11
R24

AE18

M15

J22

G23

J12
L12
L14
L20

L23
M11
M20
M23
M25
N12
N14

B7

L24
P13
P20
P15
R12
R14

330U_D2E_2.5VM

1

C128

1

1

C11522U_1206_10V4Z

C12922U_1206_10V4Z

+

2

2

2

W23

AD25

W24

AC23

AC14
AC22

AE22

AE14

AC15

AC16

R20
Y25
U20

H25
Y22
D25

G24
H12
R23

C4

T23
T25

R17
H23
M17
A23

F17

D4

M13

2

NB1E

VSS1

PAR 5 OF 5

VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59

216MSA4ALA12FG RS485M_BGA465

GROUND

VSSA1
VSSA2
VSSA3
VSSA4
VSSA5
VSSA6
VSSA7
VSSA8

VSSA9
VSSA10
VSSA11
VSSA12
VSSA13
VSSA14
VSSA15
VSSA16
VSSA17
VSSA18
VSSA19
VSSA20
VSSA21
VSSA22
VSSA23
VSSA24
VSSA25
VSSA26
VSSA27
VSSA28
VSSA29
VSSA30
VSSA31
VSSA32
VSSA33
VSSA34
VSSA35
VSSA36
VSSA93
VSSA94
VSSA95
VSSA37
VSSA38
VSSA39
VSSA40
VSSA41
VSSA42
VSSA43
VSSA44
VSSA45

M3
V12
V11
V14
F3
V15
A1
H1
G3
J2
H3
AE10
J6
AE6
F1
L6
M2
M6
J3
P6
T1
N3
P9
R6
U2
T3
U3
U6
AC4
Y1
Y15
W6
AC2
Y3
Y9
Y11
Y12
Y14
AA3
R9
AD1
AC5
AC6
AC7
AD3
AC9
AC10
G6

1

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/12/1 2006/12/01

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

RS480M Power/GND
LA-3221P

1

0.1

of

12 43Friday, January 06, 2006

A

B

C

D

E

F

G

H

12

C44610U_0805_10V4Z

1 2

C447 0.1U_0402_16V4Z

1 1

2 2

EXT CLK FREQUENCY SELECT TABLE(MHZ)

3 3

FS2

0 0 0
0 0 1

0 1 0
0 1 1
1 0 0
1 0 1

1 1 1

1 2

C20010U_0805_10V4Z

1 2

C201 0.1U_0402_16V4Z

1 2

R269 10K_0402_5%

CPUFS1

Hi-Z
X

180.00

220.00

100.00

133.33

200.00

L32

FBML10160808121LMT_0603

+3VS_CLK_VDD48

+3VS

12

L14

FBML10160808121LMT_0603

+3VS_CLK_VDDREF +3VS_CLK_VDD48

CLK_RESET+3VS_CLK

1 2

SRCCLK

HTTFS0 PCI

[2:1]

Hi-Z Hi-Z100.00 Reserved

100.00

100.00

100.00

36.56 73.12

100.00

66.66 33.33

100.00

66.66 33.33

100.00

66.66 33.33 Normal ATHLON64 operation

10U_0805_10V4Z

USB

48.00

X/6X/3

48.00

30.0060.00

48.00

48.00

48.00

48.00

48.00

+3VS

C423

SMB_CK_CLK18,9,16,26
SMB_CK_DAT18,9,16,26

COMMENT

Reserved
Reserved
Reserved
Reserved
Reserved

L27
CHB2012U121_0805

1

2

33P_0402_50V8J

33P_0402_50V8J

1 2

C170

1 2

1 2

C164

+3VS_CLK +3VS_CLK_VDDA

14.31818MHz_20P_1BX14318BE1A

12

Y2

SMB_CK_CLK1 SMB_CCK_CLK1
SMB_CK_DAT1

0.1U_0402_16V4Z

1

1

C438

C434

2

2

10U_0805_10V4Z

+3VS_CLK_VDDREF

XTALIN_CLK
XTALOUT_CLK

CLK_RESET

SMB_CCK_DAT1

@

R97

1 2

1M_0402_5%

R104 33_0402_5%

1 2
1 2

R105 33_0402_5%

1 2

R81 475_0603_1%

FS0
FS1
FS2

0.1U_0402_16V4Z

1

C439

2

0.1U_0402_16V4Z

CLKIREF

+3V_CLK (40 mils)

+3VS_CLK

1

C425

54
14
23
28
44

39
60
53

15
22
29
45

38
58

11
61

10

48

5
2

8
1

3
4

9

@

1

C428

2

2

0.1U_0402_16V4Z

U8

VDDCPU
VDDSRC
VDDSRC
VDDSRC
VDDSRC
VDD48
VDDATIG
VDDREF
VDDHTT

GNDCPU
GNDSRC
GNDSRC
GNDSRC
GNDSRC
GND48
GNDATIG
GNDREF
GNDHTT

X1
X2

RESET_IN#
NC

SMBCLK
SMBDAT

IREF

ICS951462AGLFT_TSSOP64

12

12

R74

R254

2.2K_0402_5%

2.2K_0402_5%

12

12

R75

R255

@

2.2K_0402_5%

2.2K_0402_5%

0.1U_0402_16V4Z

C424

+3VS_CLK +3VS_CLK

R73

R257

@

1

2

0.1U_0402_16V4Z

CPUCLK8T0
CPUCLK8C0

CPUCLK8T1

CPUCLK8C1

SRCCLKT6

SRCCLKC6
ATIGCLKT0
ATIGCLKC0
ATIGCLKT1
ATIGCLKC1
ATIGCLKT2
ATIGCLKC2
ATIGCLKT3
ATIGCLKC3

SRCCLKT5

SRCCLKC5

SRCCLKT4

SRCCLKC4

SRCCLKT3

SRCCLKC3

SRCCLKT2

SRCCLKC2

SRCCLKT0

SRCCLKC0

SRCCLKT1

SRCCLKC1

SRCCLKT7

SRCCLKC7

CLKREQA#

CLKREQB#

CLKREQC#

48MHz_1
48MHz_0

FS1/REF1
FS0/REF0
FS2/REF2

HTTCLK0

12

2.2K_0402_5%

12

2.2K_0402_5%

0.1U_0402_16V4Z

1

C440

2

50

VDDA

49

GNDA

56
55
52
51

16
17
41
40
37
36
35
34
30
31
18
19
20
21
24
25
26
27
47
46
43
42
12
13

57
32
33

7
6

63
64
62
59

CLKREQA#
CLKREQB#
CLKREQC#

1

C427

2

CPUCLK0H
CPUCLK0L

SBLINKCLK_R
SBLINKCLK#_R
CLK_GFX_CLKP
CLK_GFX_CLKN

CLK_LAN
CLK_LAN#

CLK_WCARD
CLK_WCARD#

SBSRCCLK_R
SBSRCCLK#_R

CLKREQA#
CLKREQB#
CLKREQC#

CLK_USB

FS1
FS0
FS2

CLK_HTREFCLK

CHECK

一下料號

12

R78

10K_0402_5%

12

R66

@

2.2K_0402_5%

R79 47_0402_1%

1 2

R80 47_0402_1%

1 2

R103 33_0402_5%

1 2

R256 33_0402_5%
R76 33_0402_5%

R77 33_0402_5%

1 2

12

R85

R115

10K_0402_5%

12

R84

R114

@

@

2.2K_0402_5%

1

2

C426

0.1U_0402_16V4Z

R108 33_0402_5%

1 2

R109 33_0402_5%

1 2

R82 33_0402_5%

1 2

R83 33_0402_5%

1 2

R110 33_0402_5%

1 2

R111 33_0402_5%

1 2

R112 33_0402_5%

1 2

R113 33_0402_5%

1 2

R106 33_0402_5%

1 2

R107 33_0402_5%

1 2

12

1 2

12

10K_0402_5%

12

2.2K_0402_5%

C412

10U_0805_10V4Z

L25

1 2

FBML10160808121LMT_0603

1

2

SBLINKCLK

SBLINKCLK#
NB_GFX_CLKP
NB_GFX_CLKN

CLK_PCIE_LAN
CLK_PCIE_LAN#

CLK_PCIE_WCARD
CLK_PCIE_WCARD#

SBSRCCLK
SBSRCCLK#

12

HTREFCLK 11

R64

51.1_0402_1%

USBCLK_EXT
NB_REFCLK
SB_OSC_INT

CLK_PCIE_WCARD
CLK_PCIE_WCARD#

CLK_PCIE_LAN
CLK_PCIE_LAN#

SBSRCCLK
SBSRCCLK#

SBLINKCLK
SBLINKCLK#

NB_GFX_CLKP
NB_GFX_CLKN

+3VS+3VS

12

R65
261_0402_1%

CLKREQB# 26

USBCLK_EXT 16

NB_REFCLK 11

SB_OSC_INT 16

C448 10P_0402_25V8K@
C411 10P_0402_25V8K@
C159 10P_0402_25V8K@

R277 49.9_0402_1%

1 2

R278 49.9_0402_1%

1 2

R275 49.9_0402_1%

1 2

R276 49.9_0402_1%

1 2

R271 49.9_0402_1%

1 2

R272 49.9_0402_1%

1 2

R273 49.9_0402_1%

1 2

R274 49.9_0402_1%

1 2

R258 49.9_0402_1%

1 2

R259 49.9_0402_1%

1 2

CPUCLK0_H 6

CPUCLK0_L 6

SBLINKCLK 11
SBLINKCLK# 11
NB_GFX_CLKP 11
NB_GFX_CLKN 11

CLK_PCIE_LAN 23
CLK_PCIE_LAN# 23

CLK_PCIE_WCARD 26
CLK_PCIE_WCARD# 26

SBSRCCLK 15
SBSRCCLK# 15

1 2
1 2
1 2

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

C

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

D

2005/12/1 2006/12/01

E

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

F

Date: Sheet

G

Clock Generator
LA-3221P

0.1

of

13 43Friday, January 06, 2006

H

A

1 1

VGA_CRT_R11

VGA_CRT_G11
VGA_CRT_B11

+3VS

12

R186

D13
RB751V_SOD323

21

D12
RB751V_SOD323@

21

VGA_CRT_HSYNC11

BKOFF#27

ENABLT11,27

2 2

BKOFF#

4.7K_0402_5%

DISPOFF#

1 2

R178 39_0402_5%

VGA_CRT_VSYNC11

VGA_CRT_VSYNC CRT_VSYNC D_CRT_VSYNC

LCD POWER CIRCUIT

+LCDVDD

12

13

D

3 3

ENVDD11

4 4

1N4148_SOT23@

2N7002LT1G_SOT23

+3VS

1

C22

2

12

D14

Q24

ENVDD

10K_0402_5%

0.1U_0402_16V4Z@

S

R205

1

2

R191
360_0402_5%

2

G

12

INVT_PWM

C327

1U_0603_10V4Z@

A

+5VALW

2

G

R200
1M_0402_5%

1 2

R204 100K_0402_5%

13

D

S

Q27
BSS138_NL_SOT23

12

C329

0.047U_0402_16V7K

G

2

1

2

4.7U_0805_10V4Z

B

VGA_CRT_R

VGA_CRT_G

VGA_CRT_B

1 2

C287 0.1U_0402_16V4Z

+3VS

W=60mils

S

SI2301BDS-T1-E3 1P SOT23
Q25

7.3

D

1 3

+LCDVDD

1

C319

0.1U_0402_16V4Z

2

B

12

12

R175

CRT_HSYNC D_CRT_HSYNCVGA_CRT_HSYNC

1

2

R176

150_0402_1%

150_0402_1%

+CRT_VCC

C286 0.1U_0402_16V4Z

B+

C318

5

P

A2Y

G

3

1 2

F3

2.5A_32V

1 2

R179 39_0402_5%

W=60mils

+LCDVDD

MSEN#27

1

12

R177

150_0402_1%

1

OE#

U18

74AHCT1G125GW_SOT353-5

21

0.1U_0603_50V4Z

4

R187
0_0805_5%

2

8P_0402_50V8K

INVPWR_B+

12

C290

+CRT_VCC

2

1

C

D1

DAN217_SC59@

+3VS

L19

L20

L21

12

4.7K

C

CRT_R_L

CRT_G_L

CRT_B_L

C281

8P_0402_50V8K

R3

R4

1 2

6.8K_0402_5%

EDID_CLK_LCD
EDID_DAT_LCD

LVDSAC+
LVDSAC-

LVDSA0+
LVDSA0-

LVDSA1+
LVDSA1-

LVDSA2+
LVDSA2-

11
13
15
17
19
21
23
25
27
29
31
33
35
37
39

JST_BM40B-SRDS-G-TFCLFSN~N

1

2

1
3
5
7
9

CONN@

2005/12/1 2006/12/01

1 2

FCM2012C-800_0805

1 2

FCM2012C-800_0805

1 2

FCM2012C-800_0805

1

C288

1

2

C289

8P_0402_50V8K

2

8P_0402_50V8K

R180 10K_0402_5%

1

5

P

4

OE#

A2Y

G

U19
74AHCT1G125GW_SOT353-5

3

原本為

VGA_DDC_DATA_C

VGA_DDC_CLK_C

0.1U_0603_50V4Z

2

+LCDVDD

+3VS

C321

C320

EDID_CLK_LCD11

1

EDID_DAT_LCD11

LVDSAC+11
LVDSAC-11

LVDSA0+11
LVDSA0-11

LVDSA1+11
LVDSA1-11

LVDSA2+11
LVDSA2-11

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

D2

1

2

3

1

C282

2

8P_0402_50V8K

1 2

R173 0_0603_5%

1 2

R174 0_0603_5%

1 2

1 2

6.8K_0402_5%

2.2K_0402_5%

2

1 3

D

BSS138_NL_SOT23

41

JLCD1

2

1

2

4

3

4

GND

6

5

6

8

7

8

10

9

10

12

11

12

14

13

14

16

15

16

18

17

18

20

19

20

22

21

22

24

23

24

26

25

26

28

27

28

30

29

30

32

31

32

34

33

34

36

35

36

38

37

38

40

39

40

GND

42

DAN217_SC59@

1

2

3

1

8P_0402_50V8K

2

C284

10P_0402_50V8J

R5

G

Q1BSS138_NL_SOT23

S

2

1 3

D

Q2

R6

1 2

4.7K_0402_5%

G

S

LVDSBC+
LVDSBC-

LVDSB0+
LVDSB0-

LVDSB1+
LVDSB1-

LVDSB2+
LVDSB2-

DISPOFF#
DAC_BRIG

INVT_PWM

AMBER_LED#
BATT_LED1#
GREEN_LED#

Compal Secret Data

Deciphered Date

1

2

3

C283

CRT_GND

1

2

+3VS+CRT_VCC +3VS+CRT_VCC +3VS

4.7K_0402_5%

D3

DAN217_SC59@

HSYNC_L

VSYNC_L

原本為

R7

1 2

2

C326

0.1U_0402_10V6K

1

D

+5VS

1.1A_6VDC_FUSE

1

C285
10P_0402_50V8J

2

10K

VGA_DDC_DATA 11

VGA_DDC_CLK 11

+5VALW

LVDSBC+ 11
LVDSBC- 11

LVDSB0+ 11
LVDSB0- 11

LVDSB1+ 11
LVDSB1- 11

LVDSB2+ 11
LVDSB2- 11

DAC_BRIG 27
INVT_PWM 27

D

E

+CRT_VCC

W=40mils

CRT_GND

CRT_GND

GREEN_LED#

Battery low LED Color:Amber

AMBER_LED#

Battery low LED Color:Amber

BATT_LED1#

Battery low LED Color:Amber

1 2

R192
330_0603_5%

1 2

1 2

R198
330_0603_5%

1 2

1 2

R201
330_0603_5%

1 2

6

11

1
7

12

2
8

13

3
9

14

4
10
15

5

R2
0_0805_5%

R1
0_0805_5%

R194

330_0603_5%

R197

330_0603_5%

R203

330_0603_5%

TV_OUT/CRT CONN
LA-3221P

JCRT1

17
16

SUYIN_7849S-15G2T-HC

CONN@

12

12

2

B

R193

1 2

1M_0603_1%

2

B

R199

1 2

1M_0603_1%

2

B

R202

1 2

1M_0603_1%

E

CRT_GND

C

Q23
MMBT3904_NL_SOT23

E

3 1

C

Q26
MMBT3904_NL_SOT23

E

3 1

C

Q28
MMBT3904_NL_SOT23

E

3 1

of

14 43Friday, January 06, 2006

0.1

21

DDC_MD2

C280100P_0402_25V8K

W=40mils

D4

2 1

RB411DT146 SOT23

0.1U_0402_16V4Z

C3

100P_0402_25V8K

1

2

C1
68P_0402_50V8K

PWR_GREEN_LED#27,30

PWR_AMBER_LED#27,30

BATT_FULL_LED#27,30

1

C2

2

VGA_DDC_DATA_C

VGA_DDC_CLK_C

1

C4
68P_0402_50V8K

2

Title

Size Document Number Rev

Custom

Date: Sheet

F1

5

4

3

2

1

PCICLK0
PCICLK1
PCICLK2
PCICLK3
PCICLK4
PCICLK5
PCICLK6

PCIRST#

AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31

CBE3#

FRAME#

IRDY#

STOP#
PERR#
SERR#
REQ0#
REQ1#
REQ2#

GNT0#
GNT1#
GNT2#

CLKRUN#

LOCK#

LAD0
LAD1
LAD2
LAD3

LFRAME#

LDRQ0#
LDRQ1#

BMREQ#

SERIRQ

RTCCLK

VBAT

3

BATT1

PCI_AD[0..31]

PCICLK0_R

U2

PCICLK1_R

T2

PCICLK2_R

U1

PCICLK3_R

V2

PCICLK4_R

W3

PCICLK5_R

U3

PCICLK6_R

V1

SB_SPDIF_OUT

T1

PCIRST#

AJ9

PCI_AD0

W7

PCI_AD1

Y1

PCI_AD2

W8

PCI_AD3

W5

PCI_AD4

AA5

PCI_AD5

Y3

PCI_AD6

AA6

PCI_AD7

AC5

PCI_AD8

AA7

PCI_AD9

AC3

PCI_AD10

AC7

PCI_AD11

AJ7

PCI_AD12

AD4

PCI_AD13

AB11

PCI_AD14

AE6

PCI_AD15

AC9

PCI_AD16

AA3

PCI_AD17

AJ4

PCI_AD18

AB1

PCI_AD19

AH4

PCI_AD20

AB2

PCI_AD21

AJ3

PCI_AD22

AB3

PCI_AD23

AH3

PCI_AD24

AC1

PCI_AD25

AH2

PCI_AD26

AC2

PCI_AD27

AH1

PCI_AD28

AD2

PCI_AD29

AG2

PCI_AD30

AD1

PCI_AD31

AG1

PCI_CBE#0

AB9

PCI_CBE#1

AF9

PCI_CBE#2

AJ5

PCI_CBE#3

AG3

PCI_FRAME#

AA2

PCI_DEVSEL#

AH6

PCI_IRDY#

AG5

PCI_TRDY#

AA1

PCI_PAR

AF7

PCI_STOP#

Y2

PCI_PERR#

AG8

PCI_SERR#

AC11

PCI_REQ#0

AJ8

PCI_REQ#1

AE2

PCI_REQ#2

AG9

PCI_REQ#3

AH8

PCI_REQ#4

AH5

PCI_GNT#0

AD11

PCI_GNT#1

AF2

PCI_GNT#2

AH7

PCI_GNT#3

AB12

PCI_GNT#4

AG4

PM_CLKRUN#

AG7

LOCK#

AF6

PCI_PIRQE#

AD3

PCI_PIRQF#

AF1

PCI_PIRQG#

AF4

PCI_PIRQH#

AF3

LPC_AD0

AG24

LPC_AD1

AG25

LPC_AD2

AH24

LPC_AD3

AH25

LPC_FRAME#

AF24

LDRQ0#

AJ24

LDRQ1#

AH26

BMREQ#

W22

SIRQ

AF23

RTC_CLK

D3

RTC_IRQ#

F5
E1

D1

2005/12/1 2006/12/01

8.2K_0402_5%

R308

SBSRCCLK#13

Y4

LDT_RST#6

OUT
IN

SBSRCCLK13

12

A_RST#

R284
R282

R292 4.12K_0402_1%

+PCIE_VDDR

3

NC

2

NC

ALLOW_LDTSTOP

A_RST#

SB_RX0P10

+3VS

D D

C C

B B

A A

RP27

1 8
2 7
3 6
4 5

8.2K_0804_8P4R_5%

RP21

1 8
2 7
3 6
4 5

8.2K_0804_8P4R_5%

RP25

1 8
2 7
3 6
4 5

8.2K_0804_8P4R_5%

RP24

1 8
2 7
3 6
4 5

8.2K_0804_8P4R_5%

RP28

1 8
2 7
3 6
4 5

8.2K_0804_8P4R_5%

RP22

1 8
2 7
3 6
4 5

8.2K_0804_8P4R_5%

R385

8.2K_0402_5%

R372
10K_0402_5%

+1.2V_HT

+3VS

PCI_PIRQF#
PCI_PIRQG#
PCI_IRDY#
PCI_PIRQH#

PCI_REQ#0
PCI_REQ#3
PCI_PERR#
PCI_REQ#2

PCI_GNT#0
PCI_REQ#1
PCI_GNT#1
PCI_GNT#4

PCI_SERR#
PCI_GNT#3

PCI_TRDY#
PCI_FRAME#
PCI_PIRQE#
PCI_STOP#

PCI_REQ#4
PCI_DEVSEL#
LOCK#
PCI_GNT#2

PCI_PAR

12

@

PM_CLKRUN#

12

R128
10K_0402_5%

1 2

Hi: Enable thermtrip

Low: Disable thermtrip

SB_RX0N10
SB_RX1P10
SB_RX1N10

SB_TX0P10
SB_TX0N10
SB_TX1P10
SB_TX1N10

+1.8VS

FBML10160808121LMT_0603

C449 1U_0603_10V4Z
C462 10U_0805_10V4Z
C454 0.1U_0402_16V4Z

ALLOW_LDTSTOP

12

R31210K_0402_5%

12

LDRQ0#

R30310K_0402_5%

12

LDRQ1#

R29610K_0402_5%

12

LPC_AD0

R298100K_0402_5%

12

LPC_AD1

R124100K_0402_5%

12

LPC_AD2

R304100K_0402_5%

12

LPC_AD3

R299100K_0402_5%

12

LPC_FRAME#

R2914.7K_0402_5%

L33

SIRQ

SB_RX0P
SB_RX0N
SB_RX1P
SB_RX1N

1 2

1 2
1 2
1 2

C209 22U_A_4VM
C465 0.1U_0402_16V4Z

C459 0.1U_0402_16V4Z
C457 0.1U_0402_16V4Z
C461 0.1U_0402_16V4Z
C460 0.1U_0402_16V4Z
C455 0.1U_0402_16V4Z
C463 0.1U_0402_16V4Z
C458 0.1U_0402_16V4Z

C554
18P_0402_50V8J

1 2

R413

20M_0603_5%

1 2

C555
18P_0402_50V8J

C451 0.01U_0402_16V7K
C450 0.01U_0402_16V7K
C453 0.01U_0402_16V7K
C452 0.01U_0402_16V7K

+PCIE_VDDR

+PCIE_PVDD

+1.8VS

R419
20M_0603_5%

L16

FBM-L11-321611-260-LMT_1206

+

12

1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2

12

12

32.768K 20PPM Q13MC30610003

ALLOW_LDTSTOP11

4
1

1 2

SBSRCCLK
SBSRCCLK#

SB_RX0P_C
SB_RX0N_C
SB_RX1P_C
SB_RX1N_C

SB_TX0P
SB_TX0N
SB_TX1P
SB_TX1N

150_0402_1%

150_0402_1%

LDT_RST#

12
12

12

SB_32KHI

SB_32KH0

SB1A

AG10

A_RST#

J24

PCIE_RCLKP

J25

PCIE_RCLKN

P29

PCIE_TX0P

P28

PCIE_TX0N

M29

PCIE_TX1P

M28

PCIE_TX1N

K29

PCIE_TX2P

K28

PCIE_TX2N

H29

PCIE_TX3P

H28

PCIE_TX3N

T25

PCIE_RX0P

T26

PCIE_RX0N

T22

PCIE_RX1P

T23

PCIE_RX1N

M25

PCIE_RX2P

M26

PCIE_RX2N

M22

PCIE_RX3P

M23

PCIE_RX3N

E29

PCIE_CALRP

E28

PCIE_CALRN

E27

PCIE_CALI

U29

PCIE_PVDD

U28

NC

F27

PCIE_VDDR_1

F28

PCIE_VDDR_2

F29

PCIE_VDDR_3

G26

PCIE_VDDR_4

G27

PCIE_VDDR_5

G28

PCIE_VDDR_6

G29

PCIE_VDDR_7

J27

PCIE_VDDR_8

J29

PCIE_VDDR_9

L25

PCIE_VDDR_10

L26

PCIE_VDDR_11

L29

PCIE_VDDR_12

N29

PCIE_VDDR_13

D2

X1

C1

X2

AC26

CPU_PG

W26

INTR/LINT0

W24

NMI/LINT1

W25

INIT#

AA24

SMI#

AA23

NC

AA22

IGNNE#

AA26

A20M#

Y27

FERR#

AA25

STPCLK#/ALLOW_LDTSTP

AH9

CPU_STP#/DPSLP_3V#

B24

NC

W23

DPRSLPVR

AC25

LDT_RST#/DPRSTP#/PROCHOT#

218S4RASA11GS SB460_BGA549

SB460

Part 1 of 4

SPDIF_OUT/GPIO41

PCI EXPRESS INTERFACE

PCI INTERFACE

REQ3#/PDMA_REQ0#

REQ4#/PLL_BP33/PDMA_REQ1#

GNT3#/PLL_BP66/PDMA_GNT0#
GNT4#/PLL_BP50/PDMA_GNT1#

XTAL

LPC

CPU

RTC_IRQ#/ACPWR_STRAP

RTC

Security Classification

PCI CLKS

AD0/ROMA18
AD1/ROMA17
AD2/ROMA16
AD3/ROMA15
AD4/ROMA14
AD5/ROMA13
AD6/ROMA12
AD7/ROMA11

AD8/ROMA9

AD9/ROMA8
AD10/ROMA7
AD11/ROMA6
AD12/ROMA5
AD13/ROMA4
AD14/ROMA3
AD15/ROMA2
AD16/ROMD0
AD17/ROMD1
AD18/ROMD2
AD19/ROMD3
AD20/ROMD4
AD21/ROMD5
AD22/ROMD6
AD23/ROMD7

CBE0#/ROMA10

CBE1#/ROMA1

CBE2#/ROMWE#

DEVSEL#/ROMA0

TRDY#/ROMOE#

PAR/ROMA19

INTE#/GPIO33
INTF#/GPIO34

INTG#/GPIO35

INTH#/GPIO36

RTC_GND

ML1220 MAXELL LITHIUM RTC BATTERY

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

PCI_AD[0..31] 19,21,26

R450 22_0402_5%

1 2

R452 22_0402_5%

1 2

R451 22_0402_5%

1 2

R448 22_0402_5%

1 2

+3VS +3VS

12

FBML10160808121LMT_0603

@

2

2

C5910.1U_0402_16V4Z

@

1

1

PCI_CBE#0 21,26
PCI_CBE#1 21,26
PCI_CBE#2 21,26
PCI_CBE#3 21,26
PCI_FRAME# 21,26
PCI_DEVSEL# 21,26
PCI_IRDY# 21,26
PCI_TRDY# 21,26
PCI_PAR 21,26
PCI_STOP# 21,26
PCI_PERR# 21,26
PCI_SERR# 21,26
PCI_REQ#0 21
PCI_REQ#1 26
PCI_REQ#2
PCI_REQ#3

PCI_GNT#0 21
PCI_GNT#1 26
PCI_GNT#2
PCI_GNT#3

PM_CLKRUN# 21,26,27

PCI_PIRQE# 21

PCI_PIRQF# 21,26
PCI_PIRQG# 21,26
PCI_PIRQH#

LPC_AD0 27
LPC_AD1 27
LPC_AD2 27
LPC_AD3 27
LPC_FRAME# 19,27
LDRQ0# 27

BMREQ# 11

SIRQ 21,27
RTC_CLK 19

RTC_IRQ# 19

+SB_VBAT

2

C551
1U_0603_10V4Z

1

Compal Secret Data

Deciphered Date

L45

PCICLK0_R

C6050.1U_0402_16V4Z

@

CLK_PCI_EC 27
CLK_PCI_MINI 26

CLK_PCI_CB 21
CLK_PCI_SIO_DB 27
PCICLK4_R 19
PCICLK5_R 19
PCICLK6_R 19
SB_SPDIF_OUT 19

@

1 2

R488 0_0402_5%

1 2

R503 10K_0402_5%

@

R492

10K_0402_5%

@

PCIRST#

12

R309

8.2K_0402_5%

-

+SB_VBAT

W=20mils

2

12

R493
10K_0402_5%

@

12

JBATT1

2

1 2

U45

@

8

DLY_CNTL

CLKOUT1

1
3

13

9
4

5

12

ASM3P623S00EF-16-TR_TSSOP16

CIS SYMBOL
PART NO. & PART DESCRIPTION

+3VALW

C470 0.1U_0402_16V4Z

5

1

P

OE#

I2O

G

3

A_RST#

R295 0_0402_5%@

CLKOUT2
CLKIN
VDD

CLKOUT3
VDD

CLKOUT4
SSON

CLKOUT5
SS%

CLKOUT6
GND

CLKOUT7
GND

CLKOUT8

尚未出現,暫代

1 2

U35

R310 33_0402_5%

4

74LVC1G125GW_SOT3535

+3VALW

R311 0_0402_5%@

C456 0.1U_0402_16V4Z

1 2

5

1

U33

P

OE#

I2O

G

74LVC1G125GW_SOT3535

3

1 2

+

-

MAXELL_1220G

R143
1K_0603_5%

CLR_CMOS 28

+

Size Document Number Rev

Custom

Date: Sheet

1 2

1 2

4

RTC_BAT_PWR

1

1

C239

0.1U_0402_16V4Z

2

Title

PCICLK0_R
PCICLK1_R
PCICLK2_R
PCICLK3_R

CLK_PCI_MINI
CLK_PCI_CB
CLK_PCI_EC

R491 22_0402_5%@

2

R495 22_0402_5%@

6

R494 22_0402_5%@

7

R502 22_0402_5%@

10
11

14
15

16

3

PCICLK0_R 19
PCICLK1_R 19
PCICLK2_R 19
PCICLK3_R 19

C571 10P_0402_25V8K@

1 2

C570 10P_0402_25V8K@

1 2

C569 10P_0402_25V8K@

1 2

1 2
1 2

1 2
1 2

已更換

R294
33_0402_5%

1 2

1

2

PCI_RST#

D10
BAS40-04_SOT23

2

C464
10P_0402_25V8K

1

@

CHGRTC

PCI_RST# 21,26

SB400-PCI_EXP/PCI/LPC/RTC
LA-3221P

1

CLK_PCI_EC 27
CLK_PCI_MINI 26

CLK_PCI_CB 21

CLK_PCI_SIO_DB 27

NB_RST# 11,20,23,26,27,40

of

15 43Friday, January 06, 2006

0.1

5

4

3

2

1

+3VALW

PWRBTN_OUT#27

SB_PWRGD6,30

PCIE_WAKE#23,26
H_THERMTRIP#6

EC_RSMRST#27

SB_OSC_INT13

EC_FLASH#28

SMB_CK_CLK18,9,13,26
SMB_CK_DAT18,9,13,26

HD_BITCLK24
HD_SDOUT24

HD_SYNC24

AC97_SDOUT19
HD_SDIN024
HD_SDIN124

SB460_GPIO1319
SB460_GPIO1419

EC_THERM#27

10K_0402_5%

PWM_CTRL#

Q34
2N7002LT1G_SOT23

@

12

@

EC_SWI#27

EC_SCI#27

SLP_S3#27
SLP_S5#27

R343 10K_0402_5%

1 2

R355 10K_0402_5%

1 2

EC_GA2027
KB_RST#27

SB_SPKR25

LDT_STOP#6,11

R297 10K_0402_5%

LPC_PME#
LPC_SMI#
S3_STATE
SYS_RESET#
PCIE_WAKE#
BLINK/GPM6_

R306 10K_0402_5%
R317 10K_0402_5%

R307 10K_0402_5%
R305 10K_0402_5%

CPU_PWRGD6

EC_SMI#27

OVCUR#6

1 2

OVCUR#4
OVCUR#329

EC_LID_OUT#27

OVCUR#129
OVCUR#029

1 2
1 2

1 2

1 2

@

4

R382 0_0402_5%

4

U10

@

PWM_CTRL#

1

OE#

EC_SCI#
SLP_S3#
SLP_S5#
EC_FLASH#
SYS_RESET#
S3_STATE

KB_RST#
EC_RSMRST#
LPC_PME#

PWRBTN_OUT#

EC_THERM#

OVCUR#3

PCIE_WAKE#

EC_SWI#

BLINK/GPM6_

SMB_CK_CLK1
SMB_CK_DAT1

LPC_SMI#

AZ_DOCK_EN#

SB460_GPIO13
SB460_GPIO31

AC97_RST#

SB_HD_RST#

AC97_BITCLK
HD_SDIN0
HD_SDIN1
AC97_SDIN2

+3VS

5

P
I2O

G

3

12

12

R288 0_0402_5%

@

HD_RST#24

+3VS

12

@

R281

13

D

2

G

S

R286 0_0402_5%

R388 10K_0402_5%

1 2

R359 4.7K_0402_5%

1 2

R367 4.7K_0402_5%

D D

+3VS

C C

+3VALW

B B

A A

1 2

R300 4.7K_0402_5%

1 2

R441 10K_0402_5%

1 2

R344 10K_0402_5%

1 2

R125 10K_0402_5%@

1 2

R410 10K_0402_5%@

1 2

R353 10K_0402_5%

1 2

R409 10K_0402_5%

1 2

R403 10K_0402_5%

1 2

R354 10K_0402_5%

1 2

R360 10K_0402_5%

1 2

R381 4.7K_0402_5%
R412 10K_0402_5%

R285 2.2K_0402_5%

1 2

R293 2.2K_0402_5%

1 2

R301 10K_0402_5%

1 2

1 2

R392

R414 10K_0402_5%

1 2

R316 10K_0402_5%

1 2

R456 8.2K_0402_5%@

1 2

R368 10K_0402_5%

1 2

R407 10K_0402_5%

1 2

R439 10K_0402_5%

1 2

R408 10K_0402_5%

1 2

R457 8.2K_0402_5%

1 2

STRAP_DATA40 NB_STRAP_DATA 11

74LVC1G125GW_SOT3535

12

1 2

10K_0402_5%

@

R122 0_0402_5%

PWM_CTRL

5

TP53

1 2
1 2

TP52

1 2
1 2

HD_SDIN0
HD_SDIN1
AC97_SDIN2

AZ_DOCK_EN#

MDC_HD_SYNC24

MDC_HD_RST#24

MDC_HD_SDOUT24
MDC_HD_BITCLK24

EC_SWI#
EC_SCI#
SLP_S3#
SLP_S5#
PWRBTN_OUT#
SB_PWRGD
SB_SUS_STAT-

SB_TEST1

SB_TEST0
EC_GA20
KB_RST#

H_THERMTRIP#

EC_RSMRST#
SB_OSC_INT

PWM_CTRL
EC_FLASH#
SB_SPKR

SMB_CK_CLK1
SMB_CK_DAT1

OVCUR#6

SB_HD_RST#

R37539_0402_5%

OVCUR#4
OVCUR#3

EC_LID_OUT#

OVCUR#1
OVCUR#0

SB_HD_BITCLK

R46639_0402_5%

SB_HD_SDOUT

R43739_0402_5%

SB_HD_SYNC

R46739_0402_5%

AC97_BITCLK

AC97_RST#

SB460_GPIO31

EC_THERM#

12

PWM_CTRL

EC_SMI#

SB1D

A3

PCI_PME#/GEVENT4#

B2

RI#/EXTEVNT0#

F7

SLP_S3#

A5

SLP_S5#

E3

PWR_BTN#

B5

PWR_GOOD

B3

SUS_STAT#

F9

NC

E9

TEST1

G9

TEST0

AF26

GA20IN

AG26

KBRST#

D7

LPC_PME#/GEVENT3#

C25

LPC_SMI#/EXTEVNT1#

D9

S3_STATE/GEVENT5#

F4

SYS_RESET#/GPM7#

E7

WAKE#/GEVENT8#

C2

BLINK/GPM6#

G7

SMBALERT#/THRMTRIP#/GEVENT2#

E2

RSMRST#

B23

14M_OSC

C28

NC

A26

ROM_CS#/GPIO1

B29

GHI#/GPIO6

A23

VGATE/GPIO7

B27

GPIO4

D23

GPIO5

B26

SPKR/GPIO2

C27

SCL0/GPOC0#

B28

SDA0/GPOC1#

C3

NC

F3

NC

D26

DDC1_SCL/GPIO9

C26

DDC1_SDA/GPIO8

A27

LDT_PG/SSMUXSEL/GPIO0

A4

NC

C6

NC

C5

NC

C4

USB_OC7#/GEVENT7#

B4

USB_OC6#/GEVENT6#

B6

USB_OC5#/AZ_RST#/GPM5#

A6

USB_OC4#/GPM4#

C8

USB_OC3#/GPM3#

C7

USB_OC2#/FANOUT1/LLB#/GPM2#

B8

USB_OC1#/GPM1#

A8

USB_OC0#/GPM0#

N2

AZ_BITCLK

M2

AZ_SDOUT

K2

NC

L3

AZ_SYNC

K3

NC

L1

AC_BITCLK/GPIO38

L2

AC_SDOUT/GPIO39

L4

ACZ_SDIN0/GPIO42

J2

ACZ_SDIN1/GPIO43

J4

ACZ_SDIN2/GPIO44

M3

AC_SYNC/GPIO40

L5

AC_RST#/GPIO45

E23

FANOUT0/GPIO3

AC21

GPIO31

AD7

GPIO13

AE7

DPSLP_OD#/GPIO37

AA4

GPIO14

T4

TALERT#/GPIO10

D4

SLP#/LDT_STP#

AB19

NC

218S4RASA11GS SB460_BGA549

1 2

R45439_0402_5%

1 2

R38339_0402_5%

1 2

R40639_0402_5%

1 2

R45339_0402_5%

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

OSC / RST

AC97 AZALIA

SB_HD_SYNC
SB_HD_RST#
SB_HD_SDOUT
SB_HD_BITCLK

3

SB460

ACPI / WAKE UP EVENTS

USB INTERFACE

GPIO

USB OC

USB PWR

2005/12/1 2006/12/01

Part 4 of 4

USBCLK
USB_RCOMP
USB_ATEST1

USB_ATEST0

USB_HSDP7+
USB_HSDM7-

USB_HSDP6+
USB_HSDM6-

USB_HSDP5+
USB_HSDM5-

USB_HSDP4+
USB_HSDM4-

USB_HSDP3+
USB_HSDM3-

USB_HSDP2+
USB_HSDM2-

USB_HSDP1+
USB_HSDM1-

USB_HSDP0+
USB_HSDM0-

AVDDTX_0
AVDDTX_1
AVDDTX_2
AVDDTX_3
AVDDTX_4
AVDDRX_0
AVDDRX_1
AVDDRX_2
AVDDRX_3
AVDDRX_4

AVDDC
AVSSC

AVSS_USB_1
AVSS_USB_2
AVSS_USB_3
AVSS_USB_4
AVSS_USB_5
AVSS_USB_6
AVSS_USB_7
AVSS_USB_8
AVSS_USB_9

AVSS_USB_10
AVSS_USB_11
AVSS_USB_12
AVSS_USB_13
AVSS_USB_14
AVSS_USB_15
AVSS_USB_16
AVSS_USB_17
AVSS_USB_18
AVSS_USB_19
AVSS_USB_20
AVSS_USB_21
AVSS_USB_22
AVSS_USB_23
AVSS_USB_24
AVSS_USB_25
AVSS_USB_26
AVSS_USB_27
AVSS_USB_28
AVSS_USB_29
AVSS_USB_30
AVSS_USB_31
AVSS_USB_32
AVSS_USB_33

USBCLK_EXT

A17
A14
A11

A10
H12

NC

G12

NC

E12

NC

D12

NC

E14
D14

G14
H14

D16
E16

D18
E18

G16
H16

G18
H18

D19
E19

G19
H19

B9
B11
B13
B16
B18
A9
B10
B12
B14
B17

A12
A13
A16

C9
C10
C11
C12
C13
C14
C16
C17
C18
C19
C20
D11
D21
E11
E21
F11
F12
F14
F16
F18
F19
F21
G11
G21
H11
H21
J11
J12
J14
J16
J18
J19

+AVDDTX

+AVDDC

Compal Secret Data

Deciphered Date

USBCLK_EXT 13

1 2

USB20P5+ 28
USB20P5- 28

USB20P4+ 26
USB20P4- 26

USB20P3+ 29
USB20P3- 29

USB20P2+ 29
USB20P2- 29

USB20P1+ 29
USB20P1- 29

USB20P0+ 29
USB20P0- 29

2

R32511.8K_0603_1%

+3VALW

+AVDDTX

+AVDDC

OVCUR#0
OVCUR#1
OVCUR#4

EC_SMI#
EC_LID_OUT#
OVCUR#6

L38 KC FBM-L11-201209-221LMAT_0805

1 2

C242 0.1U_0402_16V4Z

1 2

C514 0.1U_0402_16V4Z

1 2

C513 0.1U_0402_16V4Z

1 2

C516 10U_0805_10V4Z

1 2

C515 1U_0603_10V4Z

1 2

C246 0.1U_0402_16V4Z

1 2

C237 0.1U_0402_16V4Z

1 2

C250 0.1U_0402_16V4Z

1 2

L36 KC FBM-L11-201209-221LMAT_0805

1 2

C508 10U_0805_10V4Z

1 2

C501 1U_0603_10V4Z

1 2

C507 0.1U_0402_16V4Z

1 2

Title

Size Document Number Rev

Custom

Date: Sheet

1 2

10K_0402_5%

1 2

10K_0402_5%

1 2

10K_0402_5%

1 2

10K_0402_5%

1 2

10K_0402_5%

1 2

10K_0402_5%

R349
R348
R358
R389
R369
R374

+3VALW

+3VALW

SB400-USB/ACPI/AC97/GPIO
LA-3221P

1

16 43Friday, January 06, 2006

0.1

of

5

4

3

2

1

SATA_DTX_IRX_P0

SATA_DTX_IRX_N0

SATA_ITX_DRX_N0

12

C5250.01U_0402_16V7K @

C238

SATA_ITX_DRX_P0

SATA_ITX_DRX_N1

SATA_ITX_DRX_P1

SATA_ITX_DRX_N2
SATA_ITX_DRX_P2

SATA_ITX_DRX_N3

SATA_ITX_DRX_P3

1

C225

2

0.1U_0402_16V4Z

SATA_CAL
SATA_X1
SATA_X2

SATA_LED#
+PLLVDD_ATA

+XTLVDD_ATA

1

C247

2

0.1U_0402_16V4Z

D D

+1.8VS

C C

+1.8VS

B B

33P_0402_25V8K

33P_0402_25V8K

1 2

CHB1608U301_0603

1U_0402_6.3V4Z

L37

1 2

CHB1608U301_0603

1U_0402_6.3V4Z

Y325MHZ_20P_1BX25000CK1A

1 2

C492

12

L40

1

C240

2

1

C231

2

C510

12

12

R327
10M_0402_5%

+PLLVDD_ATA

2

1

+XTLVDD_ATA

2

C51810U_0805_10V4Z

1

SATA_X1

SATA_X2

C52910U_0805_10V4Z

R302 0_0805_5%

+1.8VS

+3VS

SATA_LED#30

12

C471

22U_A_4VM

+

R363
10K_0402_5%

1

2

8.2K_0804_8P4R_5%

4 5
3 6
2 7
1 8

1 8
2 7
3 6
4 5

8.2K_0804_8P4R_5%

R345 1K_0402_1%

1 2

12

1

C234

2

0.1U_0402_16V4Z

RP18
RP19

1

2

0.1U_0402_16V4Z

AH21

AJ21

AH20

AJ20

AH18

AJ18

AH17

AJ17

AH13
AH14

AH16

AJ16
AJ11

AH11
AH12

AJ13
AF12
AD16
AD18
AC12
AD14

AJ10
AC16
AE14

AE16
AE18
AE19
AF19
AF21
AG22
AG23
AH22
AH23

AJ12

AJ14

AJ19

AJ22

AJ23
AB14

AB16
AB18
AC14
AC18
AC19
AD12
AD19
AD21
AE12
AE21
AF11
AF14
AF16
AF18
AG11
AG12
AG13
AG14
AG16
AG17
AG18
AG19
AG20
AG21
AH10
AH19

SB1B

SATA_TX0+
SATA_TX0-

SATA_RX0­SATA_RX0+

SATA_TX1+
SATA_TX1-

SATA_RX1­SATA_RX1+

SATA_TX2+
SATA_TX2-

SATA_RX2­SATA_RX2+

SATA_TX3+
SATA_TX3-

SATA_RX3­SATA_RX3+

SATA_CAL
SATA_X1
SATA_X2
SATA_ACT#
PLLVDD_SATA_1

PLLVDD_SATA_2
XTLVDD_SATA
AVDD_SATA_1

AVDD_SATA_2
AVDD_SATA_3
AVDD_SATA_4
AVDD_SATA_5
AVDD_SATA_6
AVDD_SATA_7
AVDD_SATA_8
AVDD_SATA_9
AVDD_SATA_10
AVDD_SATA_11
AVDD_SATA_12
AVDD_SATA_13
AVDD_SATA_14
AVDD_SATA_15

AVSS_SATA_1
AVSS_SATA_2
AVSS_SATA_3
AVSS_SATA_4
AVSS_SATA_5
AVSS_SATA_6
AVSS_SATA_7
AVSS_SATA_8
AVSS_SATA_9
AVSS_SATA_10
AVSS_SATA_11
AVSS_SATA_12
AVSS_SATA_13
AVSS_SATA_14
AVSS_SATA_15
AVSS_SATA_16
AVSS_SATA_17
AVSS_SATA_18
AVSS_SATA_19
AVSS_SATA_20
AVSS_SATA_21
AVSS_SATA_22
AVSS_SATA_23
AVSS_SATA_24
AVSS_SATA_25
AVSS_SATA_26
AVSS_SATA_27

218S4RASA11GS SB460_BGA549

SB460

Part 2 of 4

SERIAL ATA

SPI ROMHW MONITOR

SERIAL ATA POWER

ATA 66/100

PIDE_IORDY

PIDE_IRQ

PIDE_A0
PIDE_A1
PIDE_A2

PIDE_DACK#

PIDE_DRQ

PIDE_IOR#

PIDE_IOW#

PIDE_CS1#
PIDE_CS3#

PIDE_D0
PIDE_D1
PIDE_D2
PIDE_D3
PIDE_D4
PIDE_D5
PIDE_D6
PIDE_D7
PIDE_D8

PIDE_D9
PIDE_D10
PIDE_D11
PIDE_D12
PIDE_D13
PIDE_D14
PIDE_D15

IDEIORDYA

AB29

IDEIRQA

AA28

IDESAA0

AA29

IDESAA1

AB27

IDESAA2

Y28

IDEDACK#A

AB28

IDEREQA

AC27

IDEIOR#A

AC29

IDEIOW#A

AC28

IDECS#A1

W28

IDECS#A3

W27

IDEDA0

AD28

IDEDA1

AD26

IDEDA2

AE29

IDEDA3

AF27

IDEDA4

AG29

IDEDA5

AH28

IDEDA6

AJ28

IDEDA7

AJ27

IDEDA8

AH27

IDEDA9

AG27

IDEDA10

AG28

IDEDA11

AF28

IDEDA12

AF29

IDEDA13

AE28

IDEDA14

AD25

IDEDA15

AD29

J3

NC

J6

NC

G3

NC

G2

NC

G6

NC

C23

NC

G5

NC

M4

NC

T3

NC

V4

NC

N3

NC

P2

NC

W4

NC

P5

NC

P7

NC

P8

NC

T8

NC

T7

NC

V5

NC

L7

NC

M8

NC

V6

NC

M6

NC

P4

NC

M7

NC

V7

NC

N1

NC

M1

NC

IDEIORDYA 20

IDEIRQA 20
IDESAA0 20
IDESAA1 20
IDESAA2 20
IDEDACK#A 19,20

IDEREQA 20
IDEIOR#A 20
IDEIOW#A 20
IDECS#A1 20
IDECS#A3 20
IDEDA[0..15] 20

SATA_DTX_IRX_N0

SATA_DTX_IRX_P0 SATA_DTX_C_IRX_P0

SATA_ITX_DRX_N0

SATA_ITX_DRX_P0 SATA_ITX_C_DRX_P0

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/12/1 2006/12/01

Compal Secret Data

SATA_DTX_C_IRX_N0

12

C479 0.01U_0402_16V7K

12

C476 0.01U_0402_16V7K

SATA_ITX_C_DRX_N0

12

C486 0.01U_0402_16V7K

12

C490 0.01U_0402_16V7K

Deciphered Date

2

SATA_DTX_C_IRX_N0 20

SATA_DTX_C_IRX_P0 20

SATA_ITX_C_DRX_N0 20

SATA_ITX_C_DRX_P0 20

Title

Size Document Number Rev

Custom

Date: Sheet

SB400-IDE/SATA
LA-3221P

1

of

17 43Friday, January 06, 2006

0.1

C473 150U_D2_6.3VM

C252 0.1U_0402_16V4Z

1 2

C248 0.1U_0402_16V4Z

1 2

C220 0.1U_0402_16V4Z

1 2

C217 0.1U_0402_16V4Z

1 2

C467 0.1U_0402_16V4Z

1 2

C214 0.1U_0402_16V4Z

1 2

C251 0.1U_0402_16V4Z

1 2

C258 0.1U_0402_16V4Z

1 2

C253 0.1U_0402_16V4Z

1 2

C228 0.1U_0402_16V4Z

1 2

C212 0.1U_0402_16V4Z

1 2

C226 0.1U_0402_16V4Z

1 2

C255 0.1U_0402_16V4Z

1 2

C215 0.1U_0402_16V4Z

1 2

C262 0.1U_0402_16V4Z

1 2

C213 0.1U_0402_16V4Z

1 2

C229 0.1U_0402_16V4Z

1 2

22U_A_4VM

+

C541

12

C259 0.1U_0402_16V4Z

1 2

C254 0.1U_0402_16V4Z

1 2
1 2
1 2
1 2

+5VS

+3VS

+1.8VALW

+1.2V_HT

1 2

2 1

C256 0.1U_0402_16V4Z
C260 0.1U_0402_16V4Z
C261 0.1U_0402_16V4Z

12

+

+3VALW_SB

R321
0_0805_5%

L15

FBML10160808121LMT_0603

1 2

R443
1K_0402_5%

D15
CH751H-40_SC76

JSB1

2

112

JUMP_43X118

+

12

+3VALW

2

C49110U_0805_10V4Z

1

C210

0.1U_0402_16V4Z

2

C550

1

L34

2

C5400.1U_0402_16V4Z

1

R425
0_0805_5%

2

C2270.1U_0402_16V4Z

1

2

1

FBM-L11-321611-260-LMT_1206

C477 22U_A_4VM
C241 0.1U_0402_16V4Z

1 2

C235 0.1U_0402_16V4Z

1 2

C236 0.1U_0402_16V4Z

1 2

C232 0.1U_0402_16V4Z

1 2

C243 0.1U_0402_16V4Z

1 2

C249 0.1U_0402_16V4Z

1 2

C245 0.1U_0402_16V4Z

1 2

C244 0.1U_0402_16V4Z

1 2

C233 0.1U_0402_16V4Z

1 2

C230 0.1U_0402_16V4Z

1 2

12

1

2

1U_0603_10V4Z

+3VS

+3.3VS_SB_VDDQ

+1.8VS

12

+1.8VS_SB_VDD

12

+1.8VALW_SB

2

2

2

C2220.1U_0402_16V4Z

C4940.1U_0402_16V4Z

C2640.1U_0402_16V4Z

1

1

1

C549

0.1U_0402_16V4Z

+3VALW_SB

2

2

C4930.1U_0402_16V4Z

C2570.1U_0402_16V4Z

1

1

+SB_CPUPWR
+V5_VREF
+SB_AVDDCK

SB1C

A25

VDDQ_1

A28

VDDQ_2

C29

VDDQ_3

D24

VDDQ_4

L9

VDDQ_5

L21

VDDQ_6

M5

VDDQ_7

P3

VDDQ_8

P9

VDDQ_9

T5

VDDQ_10

V9

VDDQ_11

W2

VDDQ_12

W6

VDDQ_13

W21

VDDQ_14

W29

VDDQ_15

AA12

VDDQ_16

AA16

VDDQ_17

AA19

VDDQ_18

AC4

VDDQ_19

AC23

VDDQ_20

AD27

VDDQ_21

AE1

VDDQ_22

AE9

VDDQ_23

AE23

VDDQ_24

AH29

VDDQ_25

AJ2

VDDQ_26

AJ6

VDDQ_27

AJ26

VDDQ_28

M13

VDD_1

M17

VDD_2

N12

VDD_3

N15

VDD_4

N18

VDD_5

R13

VDD_6

R17

VDD_7

U12

VDD_8

U15

VDD_9

U18

VDD_10

V13

VDD_11

V17

VDD_12

A2

S5_3.3V_1

A7

S5_3.3V_2

F1

S5_3.3V_3

J5

S5_3.3V_4

J7

S5_3.3V_5

K1

S5_3.3V_6

G4

S5_1.8V_1

H1

S5_1.8V_2

H2

S5_1.8V_3

H3

S5_1.8V_4

A18

USB_PHY_1.8V_1

A19

USB_PHY_1.8V_2

B19

USB_PHY_1.8V_3

B20

USB_PHY_1.8V_4

B21

USB_PHY_1.8V_5

AA27

CPU_PWR

AE11

V5_VREF

A24

AVDDCK

A22

NC

B22

AVSSCK

V29

PCIE_VSS_42

V28

PCIE_VSS_41

V27

PCIE_VSS_40

V26

PCIE_VSS_39

V25

PCIE_VSS_38

V24

PCIE_VSS_37

V23

PCIE_VSS_36

V22

PCIE_VSS_35

U27

PCIE_VSS_34

T29

PCIE_VSS_33

T28

PCIE_VSS_32

T27

PCIE_VSS_31

T24

PCIE_VSS_30

T21

PCIE_VSS_29

P27

PCIE_VSS_28

218S4RASA11GS SB460_BGA549

SB460

Part 3 of 4

POWER

VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8

VSS_9
VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47
VSS_48
VSS_49
VSS_50
VSS_51
VSS_52
VSS_53
VSS_54
VSS_55
VSS_56
VSS_57

PCIE_VSS_1
PCIE_VSS_2
PCIE_VSS_3
PCIE_VSS_4
PCIE_VSS_5
PCIE_VSS_6
PCIE_VSS_7
PCIE_VSS_8

PCIE_VSS_9
PCIE_VSS_10
PCIE_VSS_11
PCIE_VSS_12
PCIE_VSS_13
PCIE_VSS_14
PCIE_VSS_15
PCIE_VSS_16
PCIE_VSS_17
PCIE_VSS_18
PCIE_VSS_19
PCIE_VSS_20
PCIE_VSS_21
PCIE_VSS_22
PCIE_VSS_23
PCIE_VSS_24
PCIE_VSS_25
PCIE_VSS_26
PCIE_VSS_27

A1
A20
A21
A29
B1
B7
B25
C21
C22
C24
D6
E24
F2
F23
G1
J1
J8
L6
L8
M9
M12
M15
M18
N13
N17
P1
P6
P21
R12
R15
R18
T6
T9
U13
U17
V3
V8
V12
V15
V18
V21
W1
W9
Y29
AA11
AA14
AA18
AC6
AC24
AD9
AD23
AE3
AE27
AG6
AJ1
AJ25
AJ29

D27
D28
D29
F26
G23
G24
G25
H27
J23
J26
J28
K27
L22
L23
L24
L27
L28
M21
M24
M27
N27
N28
P22
P23
P24
P25
P26

L35

FBML10160808121LMT_0603

1 2

+1.8VS

12
12

+SB_AVDDCK

C4834.7U_0805_6.3V6K

C4800.1U_0402_16V4Z

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2005/12/1 2006/12/01

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

Date: Sheet

SB400-Power/GND
LA-3221P

of

18 43Friday, January 06, 2006

0.1

5

4

3

2

1

REQUIRED STRAPS

SB600 HAS 15K INTERNAL PD FOR AC_SDATA_OUT,
15K PU FOR RTC_CLK, EXTERNAL PU/PD IS
NOT REQUIRED; FOR SB460, EXTERNAL PU/PD ARE

D D

AC97_SDOUT16

RTC_CLK15
PCICLK4_R15
PCICLK6_R15
PCICLK0_R15

PCICLK1_R15

C C

PULL
HIGH

PULL
LOW

AC_SDOUT

USE
DEBUG
STRAPS

IGNORE
DEBUG
STRAPS

DEFAULT

REQUIRED

12

R455

2.2K_0402_5%

12

R438
10K_0402_5%

RTC_CLK

INTERNAL
RTC

DEFAULT

EXTERNAL
RTC

12

@

R411
10K_0402_5%

PCI_CLK4 PCI_CLK6

USE INT.
PLL48

USE EXT.
48MHZ

DEFAULT

+3VS+3VALW+3VS +3VS +3VS +3VS

12

R399
10K_0402_5%

@

12

R430
10K_0402_5%

12

R401
10K_0402_5%

PCICLK6_RPCICLK4_RAC97_SDOUT RTC_CLK PCICLK0_RPCICLK1_R

PCI_CLK1 PCI_CLK0

CPU IF=K8

DEFAULT

ROM TYPE:
H, H = PCI ROM
H, L = LPC I ROM
L, H = LPC II ROM

CPU IF=P4

L, L = FWH ROM

NOTE: FOR SB460, PCICLK[8:7] ARE
CONNECTED TO SUBSTRATE
BALLS PCICLK[1:0]

12

R402
10K_0402_5%

@

12

R433
10K_0402_5%

DEFAULT

NOTE: R751 PU RESISTOR FOR
RTC_IRQ# IS REQUIRED FOR SB600
TO KEEP THE INPUT FROM FLOATING.

12

R404
10K_0402_5%

12

R435
10K_0402_5%

@

SB460 ONLY

+3VS +3VS +3VS +3VS+3VALW

12

R449
10K_0402_5%

12

R432
10K_0402_5%

@

PCI_CLK5

PCIE_CM_SET
LOW

DEFAULT

PCIE_CM_SET
HIGH

12

12

LFRAME#

ENABLE
THERMTRIP#

DEFAULT

DISABLE
THERMTRIP#

R127
10K_0402_5%

R126
10K_0402_5%

@

12

R405
10K_0402_5%

@

12

R436
10K_0402_5%

SPDIF_OUT

SIO 24MHz

SIO 48MHz

DEFAULT

12

PCI_CLK2

XTAL MODE

NOT
SUPPORTED

48MHZ OSC
MODE

DEFAULT

12

R458
10K_0402_5%

RTC_IRQ#15

SB_SPDIF_OUT15

PCICLK2_R15
PCICLK3_R15
PCICLK5_R15
LPC_FRAME#15,27

12

R440
10K_0402_5%

@

ACPWRON

PULL
HIGH

PULL
LOW

MANUAL
PWR ON

DEFAULT

AUTO
PWR
ON

R434
10K_0402_5%

PCI_CLK3

USB PHY
POWERDOWN
DISABLE

DEFAULT

USB PHY
POWERDOWN
ENABLE

12

R400
10K_0402_5%

12

R431
10K_0402_5%

@

OVERLAP COMMON PADS WHERE
POSSIBLE FOR DUAL-OP RESISTORS.

DEBUG STRAPS

SB600 HAS 15K INTERNAL PU FOR PCI_AD[28:23]

+3VS+3VS+3VS+3VS+3VS

10K_0402_5%
R289

B B

IDEDACK#A17,20

1 2

12

R290
10K_0402_5%

@

12

R396
10K_0402_5%

12

R427
10K_0402_5%

@

12

R397
10K_0402_5%

12

R428
10K_0402_5%

@

12

R395

PCI_AD25PCI_AD27 PCI_AD26

10K_0402_5%

12

R426
10K_0402_5%

@

PCI_AD24

12

R398
10K_0402_5%

12

R429
10K_0402_5%

@

PCI_AD[0..31]

2.2K IF USED FOR SB600.
10K IF USED FOR SB460.

PCI_AD[0..31] 15,21,26

+3VS

C575

0.1U_0402_10V6K

R471 0_0402_5%

SB460_GPIO1416
SB460_GPIO1316

1 2

R465 0_0402_5%

1 2

@
@

1

R474
1K_0402_5%

@

2

@

1 2

FOR DEBUG

U41

8

VCC

7

WP

6

SCL

5

VSS

SDA

AT24C04N-10SI-2.7_SO8

@

1

A0

2

A1

3

A2

4

IDE_DACK#

USE

PULL

LONG

HIGH

RESET

DEFAULT

USE

PULL

SHORT

LOW

A A

RESET

PCI_AD27 PCI_AD26

USE PCI
PLL

DEFAULT

BYPASS
PCI PLL

USE ACPI
BCLK

DEFAULT

BYPASS
ACPI
BCLK

PCI_AD25

USE IDE
PLL

DEFAULT

BYPASS IDE
PLL

PCI_AD24

USE DEFAULT
PCIE STRAPS

DEFAULT

USE EEPROM
PCIE STRAPS

SB PCIE EEPROM STRAPS

SB460 ONLY

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/12/1 2006/12/01

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

Hardware Trap
LA-3221P

1

0.1

of

19 43Friday, January 06, 2006

5

4

3

2

1

JODD1

GND

2
4
6
8

10

ODD_ACT_LED#

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54

IDEDA8
IDEDA9
IDEDA10
IDEDA11
IDEDA12
IDEDA13
IDEDA14
IDEDA15
IDEREQA
IDEIOR#A

IDEDACK#A

PDIAG#

IDESAA2
IDECS#A3

1 2

R35
100K_0402_5%

@

R52 10K_0402_5%@

1 2

80mils

IDEDA[0..15] 17

IDEREQA 17
IDEIOR#A 17

IDEDACK#A 17,19

IDESAA2 17

IDECS#A3 17

+5VS

+5VS

+5VS

+5VS

10U_0805_10V4Z

1

C110

2

1U_0603_10V4Z

Close to ODD Conn

1

C111

2

0.1U_0402_16V4Z

1

C119

2

1

C120

2

1000P_0402_50V7K~N

ODD_ACT_LED#30

C157 47P_0402_50V8J

+5VS

12

NB_RST#
IDEDA7
IDEDA6
IDEDA5
IDEDA4
IDEDA3
IDEDA2
IDEDA1
IDEDA0

IDEIOW#A
IDEIORDYA
IDEIRQA
IDESAA1
IDESAA0
IDECS#A1

SD_CSEL

12

D D

+5VS

12

R33

100K_0402_5%

ODD_ACT_LED#

C C

NB_RST#11,15,23,26,27,40

IDEIOW#A17
IDEIORDYA17
IDEIRQA17

IDESAA117
IDESAA017

IDECS#A117

R34 470_0402_5%

If CDROM is Slave
then SD_CSEL= Floating

CDROM CONN

1

1

3

3

5

5

7

7

9

9
111112
131314
151516
171718
191920
212122
232324
252526
272728
292930
313132
333334
353536
373738
393940
414142
434344
454546
474748
494950
GND51GND

53

GND

SUYIN_800059MR050S119ZL

CONN@

else SD_CSEL= Low

+5VS

SATA HDD CONN

JSATA1

S1

SATA_DTX_C_IRX_P017

B B

SATA_DTX_C_IRX_N017
SATA_ITX_C_DRX_N017

SATA_ITX_C_DRX_P017

SATA_DTX_C_IRX_P0
SATA_DTX_C_IRX_N0

SATA_ITX_C_DRX_N0
SATA_ITX_C_DRX_P0

+3VS

+5VS

GND

S2

HTX+

S3

HTX-

S4

GND

S5

HRX-

S6

HRX+

S7

GND

16

VCC3.3
VCC3.3
VCC3.3
GND
GND
GND
VCC5
VCC5
VCC5
GND
RESERVED
GND
VCC12
VCC12
VCC12

GND
GND

NC

17

NC

18
19

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15

OCTEK_SAT-22RD1_REVERS

CONN@

C468

150U_D2_6.3VM

1

+

2

+3VS

10U_0805_10V4Z

1

C522

2

10U_0805_10V4Z

1

C474

2

0.1U_0402_16V4Z

1

C511

2

0.1U_0402_16V4Z

Close to SATA HDD

C484

1

2

0.1U_0402_16V4Z

1

C517

2

0.1U_0402_16V4Z

1

C488

2

C504

1000P_0402_50V7K~N

C478

1000P_0402_50V7K~N

1

2

1

2

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/12/1 2006/12/01

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

HDD/CDROM
LA-3221P

1

0.1

of

20 43Friday, January 06, 2006

5

PCI_AD[0..31]15,19,26

D D

R5C811 & R5C841
PULL DOWN :Disable media card function

R319 10K_0402_5%@

1 2

R320 10K_0402_5%

1 2

@

C C

+3V

12

R318
100K_0402_5%

CBS_GRST#

1

C499
1U_0603_10V4Z

2

R329

C498

CLK_PCI_CB

@

10_0402_5%

12

@

4.7P_0402_50V8C

CLK_PCI_CB_TERM

2

1

B B

A A

PCI_AD21

CLK_PCI_CB15

PCI_RST#15,26

PM_CLKRUN#15,26,27

+3V

+3V

5

UDIO3
UDIO4

PCI_CBE#315,26
PCI_CBE#215,26
PCI_CBE#115,26
PCI_CBE#015,26

PCI_PAR15,26

PCI_FRAME#15,26
PCI_TRDY#15,26
PCI_IRDY#15,26
PCI_STOP#15,26
PCI_DEVSEL#15,26

1 2

PCI_PERR#15,26
PCI_SERR#15,26

PCI_REQ#015
PCI_GNT#015

SHIELD GND

R315 0_0402_5%@

1 2

R322 10K_0402_5%

1 2

PCI_PIRQE#15
PCI_PIRQF#15,26
PCI_PIRQG#15,26 CBS_CVS1 22

R313 10K_0402_5%
R314 10K_0402_5%

WLANPME#26,27

PCM_SPK#25

1 2
1 2

R328 10K_0402_5%
R323 100K_0402_5%

1 2

12

PCI_AD31
PCI_AD30
PCI_AD29
PCI_AD28
PCI_AD27
PCI_AD26
PCI_AD25
PCI_AD24
PCI_AD23
PCI_AD22
PCI_AD21
PCI_AD20
PCI_AD19
PCI_AD18
PCI_AD17
PCI_AD16
PCI_AD15
PCI_AD14
PCI_AD13
PCI_AD12
PCI_AD11
PCI_AD10
PCI_AD9
PCI_AD8
PCI_AD7
PCI_AD6
PCI_AD5
PCI_AD4
PCI_AD3

W11

PCI_AD2
PCI_AD1
PCI_AD0

W12

PCI_PAR

PCI_FRAME#
PCI_TRDY#
PCI_IRDY#
PCI_STOP#
PCI_DEVSEL# CBS_CDEVSEL#
CBS_IDSEL

R326100_0402_5%

PCI_PERR#
PCI_SERR#

PCI_RST#
CBS_GRST#

SIRQ15,27

UDIO3
UDIO4

PCM_SPK#

IEEE1394_TPBIAS0

IEEE1394_TPAP0
IEEE1394_TPAN0
IEEE1394_TPBP0
IEEE1394_TPBN0

R365

R386

C547

56.2_0603_1%

12

56.2_0603_1%

12

Z3008

270P_0402_50V7K

2

1

4

U38A

M2

AD31

M1

AD30

N5

AD29

N4

AD28

N2

AD27

N1

AD26

P5

AD25

P4

AD24

R4

AD23

R2

AD22

R1

AD21

T2

AD20

T1

AD19

U2

AD18

U1

AD17

V1

AD16

T7

AD15

V7

AD14

W7

AD13

R8

AD12

T8

AD11

V8

AD10

W8

AD9

R9

AD8

V9

AD7

W9

AD6

T11

AD5

V11

AD4
AD3

T12

AD2

V12

AD1
AD0

P2

C/BE3#

W2

C/BE2#

W6

C/BE1#

T9

C/BE0#

V6

PAR

V3

FRAME#

W4

TRDY#

V4

IRDY#

V5

STOP#

T5

DEVSEL#

P1

IDSEL

W5

PERR#

T6

SERR#

M4

REQ#

M5

GNT#

K1

PCICLK

L4

PCIRST#

G2

GBRST#

L5

CLKRUN#

J2

INTA#

K4

INTB#

K2

INTC#

J4

UDIO0/SERIRQ#

H1

UDIO1

H2

UDIO2

H4

UDIO3

H5

UDIO4

G1

UDIO5

G4

RI_OUT#/PME#

F1

SPKROUT

F2

HWSPND#

F4

TEST

R5C841_CSP208~D

CAD31/CDATA10

CAD30/CDATA9
CAD29/CDATA1

R5C841

CSTSCHG/BVD1(STSCHG#/RI#)

CAD28/CDATA8
CAD27/CDATA0

CAD26/CADR0
CAD25/CADR1
CAD24/CADR2
CAD23/CADR3
CAD22/CADR4
CAD21/CADR5
CAD20/CADR6

CAD19/CADR25

CAD18/CADR7
CAD17/CADR24
CAD16/CADR17

CAD15/IOWR#

CAD14/CADR9

CAD13/IORD#

CAD12/CADR11

CAD9/CADR10
CAD8/CDATA15

CAD7/CDATA7
CAD6/CDATA13

CAD5/CDATA6
CAD4/CDATA12

CAD3/CDATA5
CAD2/CDATA11

CAD1/CDATA4

CAD0/CDATA3

CC/BE3#/REG#

CC/BE2#/CADR12

CC/BE1#/CADR8

CC/BE0#/CE1#

CPAR/CADR13

CFRAME#/CADR23

CTRDY#/CADR22

CIRDY#/CADR15

CSTOP#/CADR20

CDEVSEL#/CADR21

RESERVED/CADR19

CPERR#/CADR14

CSERR#/WAIT#

CREQ#/INPACK#

CCLKRUN#/WP(IOIS16#)

CCLK/CADR16

CINT#/RDY(IREQ#)

CRST#/RESET

CAUDIO/BVD2(SPKR#/LED)

RESERVED/CDATA14

RESERVED/CDATA2
RESERVED/CADR18

CAD11/OE#

CAD10/CE2#

CGNT#/WE#

CCD1#/CD1#
CCD2#/CD2#

CVS1/VS1#
CVS2/VS2#

CBS_CAD31

B19

CBS_CAD30

C18

CBS_CAD29

D19

CBS_CAD28

D18

CBS_CAD27

E19

CBS_CAD26

E16

CBS_CAD25

F18

CBS_CAD24

F15

CBS_CAD23

G18

CBS_CAD22

G15

CBS_CAD21

H18

CBS_CAD20

H15

CBS_CAD19

J18

CBS_CAD18

J16

CBS_CAD17

J15

CBS_CAD16

P16

CBS_CAD15

P19

CBS_CAD14

R19

CBS_CAD13

P18

CBS_CAD12

R18

CBS_CAD11

T19

CBS_CAD10

T18

CBS_CAD9

U19

CBS_CAD8

U18

CBS_CAD7

W17

CBS_CAD6

V17

CBS_CAD5

W16

CBS_CAD4

V16

CBS_CAD3

W15

CBS_CAD2

V15

CBS_CAD1

T15

CBS_CAD0

R14

CBS_CC/BE3#

F16

CBS_CC/BE2#

K18

CBS_CC/BE1#

P15

CBS_CC/BE0#

V19

CBS_CPAR

N15

CBS_CFRAME#

K16
L16

CBS_CIRDY#

K15

CBS_CSTOP#

M16
L18

CBS_CBLOCK#

N19

CBS_CPERR#

N18

CBS_CSERR#

G16

CBS_CREQ#

G19

CBS_CGNT#

M15

CBS_CSTSCHNG

E18

CBS_CCLKRUN#

A18

CBS_CCLK_INTERNAL

L19

CBS_CINT#

M18

CBS_CRST#

H19

CBS_CAUDIO

F19

CBS_CCD1C#

T14

CBS_CCD2C#

D15

CBS_CVS1

R16

CBS_CVS2

H16

CBS_RSVD/D14

W18

CBS_RSVD/D2

C19

CBS_RSVD/A18

N16

apply same length for set of TPA+,TPA-and TPB+,TPB-

0.01U_0402_16V7K

56.2_0603_1%
C535

12

R377

56.2_0603_1%

12

R394

5.1K_0603_1%

R391

1 2

Placement Near Card Bus Controller

4

0.33U_0603_10V7K

C531

1

1

2

2

8

4

4

3

3

2

GND15GND26GND37GND4

2

1

1

SUYIN_020204FR004S506ZL
J139A1

3

R461 22_0402_5%

1 2

C564 0.01U_0402_16V7K

CBS_CAUDIO 22

CBS_CAD[0..31] 22

[1]

C560

22P_0402_50V8J

C561

22P_0402_50V8J

CBS_CC/BE3# 22
CBS_CC/BE2# 22
CBS_CC/BE1# 22
CBS_CC/BE0# 22

CBS_CPAR 22

CBS_CFRAME# 22
CBS_CTRDY# 22
CBS_CIRDY# 22
CBS_CSTOP# 22
CBS_CDEVSEL# 22
CBS_CBLOCK# 22
CBS_CPERR# 22

CBS_CSERR# 22
CBS_CREQ# 22

CBS_CGNT# 22

CBS_CSTSCHNG 22

CBS_CCLKRUN# 22

12

CBS_CINT# 22

CBS_CRST# 22

CBS_CVS2 22

CBS_RSVD/D14 22
CBS_RSVD/D2 22
CBS_RSVD/A18 22

R5C841XI

12

X1

24.576MHz_16P_3XG-24576-43E1

1 2

R5C841XO

12

0.01U_0402_16V7K

[1]

C559

2

1

1 2

SDLED#_MSLED#_XDLED#

0_0402_5%

R468

1 2

270P_0402_50V7K

C563

2

1

[1]

C556 0.01U_0402_16V7K

10K_0603_1%

R420

VPPEN022
VPPEN122

VCC5EN#22
VCC3EN#22

CBS_CCLK 22

R445
0_0402_5%

1 2

270P_0402_50V7K

C553

2

1

1 2

1 2

+3V

1 2

R423
100K_0402_5%

CBS_CCD2# 22
CBS_CCD1# 22

+3V_PHY

R5C841XI
R5C841XO

IEEE1394_TPAP0
IEEE1394_TPAN0

IEEE1394_TPBP0
IEEE1394_TPBN0

[1]

R356

0_0402_5%

IEEE1394_TPBIAS0

[1]

R337

1 2

0_0402_5%

2

R364

12

D11

A16
B16
A14

B12
A12

B13
A13

B10
A10

B11
A11

D12
D10

D13

B14

V14

W14

V13

W13
R13

T13

R7

100K_0402_5%

[1]

[1] For R5C811, these parts are NOT installed.

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/12/1 2006/12/01

Compal Secret Data

Deciphered Date

2

U38B

CPS

R5C841

XI
XO
FIL0

TPAP0
TPAN0

TPBP0
TPBN0

TPAP1
TPAN1

TPBP1
TPBN1

TPBIAS0
TPBIAS1

VREF
REXT

USBDP
USBDM

VPPEN0
VPPEN1

VCC5EN#
VCC3EN#

REGEN#

R5C841_CSP208~D

CARD_LED 30

1

MDIO00
MDIO01
MDIO02
MDIO03
MDIO04
MDIO05
MDIO06
MDIO07
MDIO08
MDIO09
MDIO10
MDIO11
MDIO12
MDIO13
MDIO14
MDIO15
MDIO16
MDIO17
MDIO18
MDIO19

B1
A2
A3
B3
B4
A5

SDLED#_MSLED#_XDLED#

B5
D5

R341

A6
B6

22_0402_5%

D6
E6
A7
B7
D7
E7
A8
B8
D8
E8

12

R346
0_0402_5%

12

SDDET#_XDDET0# 22
MSDET#_XDDET1# 22
XDCE# 22

SDWP#_XDRB# 22

SD_EN 22

XDWP 22

SDCMD_MSBS_XDWE# 22

SDCLK_MSCLK_XDRE# 22
SDDATA0_MSDATA0_XDDATA0 22
SDDATA1_MSDATA1_XDDATA1 22
SDDATA2_MSDATA2_XDDATA2 22
SDDATA3_MSDATA3_XDDATA3 22
XDDATA4 22
XDDATA5 22
XDDATA6 22
XDDATA7 22
XDCLE 22
XDALE 22

Function Seclect

UDIO3 UDIO4 VPPEN0 SD MS

0

00

00 1

01 0

101

010

10 1

11 0

11 1

*

Title

Size Document Number Rev

Date: Sheet

CardBus Controller(R5C841)

Friday, January 06, 2006

LA-3221P

XX

XX

EnableX

Enable EnableX

Enable X X

Enable EnableX

Enable Enable X

Enable Enable Enable

of

1

21 43

Enable

0.1

5

+3V

*as close as possible to VCC_3V pin

0.01U_0402_16V7K

10U_0805_10V4Z

0.01U_0402_16V7K

C572

+3VS

D D

*as close as possible to VCC_PCI pin

10U_0805_10V4Z

C534

C496

1

2

C481

C C

B B

VPPEN021
VPPEN121

VCC3EN#21
VCC5EN#21

SDDATA3_MSDATA3_XDDATA321
SDCMD_MSBS_XDWE#21

SDCLK_MSCLK_XDRE#21
SDDATA3_MSDATA3_XDDATA321
MSDET#_XDDET1#21

SDDATA2_MSDATA2_XDDATA221

SDDATA0_MSDATA0_XDDATA021
SDDATA1_MSDATA1_XDDATA121
SDCMD_MSBS_XDWE#21

SDCLK_MSCLK_XDRE#21
SDDATA0_MSDATA0_XDDATA021

A A

0.01U_0402_16V7K

0.01U_0402_16V7K

C542

1

1

2

2

+3V

*as close as possible to VCC_RIN pin

0.1U_0402_16V4Z

10U_0805_10V4Z

C495

1

2

2

1

C597

1

2

SDDET#_XDDET0#21

+3VS

+3VS

SDWP#_XDRB#21

C565

1

1

2

2

0.01U_0402_16V7K

+3V

C537

1

2

C523

0.01U_0402_16V7K

C528

C497

1

2

0.1U_0402_16V4Z

+5V

0.1U_0402_16V4Z

C581

1

2

MSDET#_XDDET1#

SD_MS_XDDATA1

1 2

[1]

R139 100K_0402_5%

1 2

[1]

R142 100K_0402_5%

5

C558

1

2

1

2

0.01U_0402_16V7K

0.01U_0402_16V7K

C500

C489

1

1

1

2

2

2

*as close as possible to VCC_MD3V pin

10U_0805_10V4Z

C566

1

2

0.01U_0402_16V7K

0.01U_0402_16V7K

+3V_PHY

R351 0_0402_5%

1 2

R350 0_0402_5%

1 2

R459 0_0402_5%

1 2

R460 0_0402_5%

1 2

[1]

0.01U_0402_16V7K

0.01U_0402_16V7K

C612

C613

1

1

2

2

U42

11

VCC3IN

VCCOUT
VCCOUT

VCC5IN
VCC5IN

EN0
EN1

VCC3_EN
VCC5_EN

FLG
GND

VCCOUT

VPPOUT

MS10

13
15

3
4

2
1

5

16

R5531V002-E2-FA_SSOP16~D

SD_MS_XDDATA2

1 2

R159 22_0402_5%

1 2

R157 22_0402_5%

+SD_VCC

R155 22_0402_5%

1 2

R154 22_0402_5%

1 2
1 2

R153 22_0402_5%

1 2

R152 22_0402_5%

1 2

R151 22_0402_5%

1 2

R150 22_0402_5%

1 2

R149 22_0402_5%

+SD_VCC

1 2

R146 22_0402_5%

1 2

R145 22_0402_5%

1 2

R144 22_0402_5%

SDDET#_XDDET0#

SDWP#_XDRB#

F5

G5
J19
K19

W3
R11
R12

A4

R6
E13

L1

E14

E10
E11
A17
B17

A9
B9

D9

D14

A15
B15

J1
J5
K5

E9
R10
T10
V10

W10

L15

M19

9
14
12

8

7

NC

6

NC

10

NC

JSD1

SD9

D2

SD1

CD/D3

SD2

CMD

SD3

VSS
VSS

MS9

VCC

MS8

SCLK

MS7

D3

MS6

INS

MS5

D2

MS4

D0

MS3

D1

MS2

BS

MS1

VSS

SD4

VDD

SD5

CLK

SD6

VSS

SD7

D0

SD8

D1

4

CD_SW

3

COMMDN

1

WP_SW

ALPS_SCDE1C0102

U38C

VCC_3V1
VCC_3V2
VCC_3V3
VCC_3V4

VCC_PCI3V1
VCC_PCI3V2
VCC_PCI3V3

VCC_MD3V

VCC_RIN1
VCC_RIN2

VCC_ROUT1
VCC_ROUT2

AVCC_PHY1
AVCC_PHY2
AVCC_PHY3
AVCC_PHY4

AGND1
AGND2
AGND3
AGND4
AGND5
AGND6

GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8
GND9
GND10

R5C841_CSP208~D

+CBS_VPP

C593

1

2

R5C841

0.1U_0402_16V4Z
C584

1

2

JSD1 Pin1

0.01U_0402_16V7K

GND

R/-B

-WE

-WP

GND

VCC

GND

4

+SD_VCC

L2

NC1

C1

NC2

D1

NC3

E1

NC4

C2

NC5

D2

NC6

E2

NC7

E4

NC8

E12

NC9

+CBS_VCC+3V

0.01U_0402_16V7K

C598

1

2

XD1
XD0

CD

XD2
XD3

-RE

XD4

-CE

XD5

CLE

XD6

ALE

XD7
XD8
XD9
XD10

D0

XD11

D1

XD12

D2

XD13

D3

XD14

D4

XD15

D5

XD16

D6

XD17

D7

XD18

2

1

C585

2

10U_0805_10V4Z

R476 0_0402_5%

XDDET0#

1 2

R473 22_0402_5%

1 2

R470 22_0402_5%

1 2

R464 22_0402_5%

1 2

R462 22_0402_5%

1 2

R447 22_0402_5%

1 2

R444 22_0402_5%

1 2

R442 22_0402_5%

1 2

R421 22_0402_5%

1 2

R417 22_0402_5%

1 2

R393 22_0402_5%

1 2

R387 22_0402_5%

1 2

R380 22_0402_5%

1 2

R373 22_0402_5%

1 2

R366 22_0402_5%

1 2

R357 22_0402_5%

1 2

R352 22_0402_5%

12

XDDET0#

SDWP#_XDRB# 21
SDCLK_MSCLK_XDRE# 21
XDCE# 21
XDCLE 21
XDALE 21
SDCMD_MSBS_XDWE# 21
XDWP 21

+XD_VCC

R134 0_0805_5%

1 2

1

C218

1U_0805_25V4Z

2

SDDET#_XDDET0#

CBS_CCLK21

[1]

SDDATA0_MSDATA0_XDDATA0 21
SDDATA1_MSDATA1_XDDATA1 21
SDDATA2_MSDATA2_XDDATA2 21
SDDATA3_MSDATA3_XDDATA3 21
XDDATA4 21
XDDATA5 21
XDDATA6 21
XDDATA7 21

JSD1 Pin3

Short (L)

SD UnWP
SD WPOpen (H)

4

D

S

G

@

2

AOS3401_SOT23

3

+XD_VCC

13

1

C224

Q13

2.2U_0603_6.3V4Z

2

1.on top or bottom layer

2.no via hole

3.90 Ohm compliant with USB platform

[1]

D8
RB751V_SOD323

2 1

2 1

D9
RB751V_SOD323

CBS_CC/BE0#21

CBS_CC/BE1#21
CBS_CPAR21
CBS_CPERR#21
CBS_CGNT#21

CBS_CINT#21

+CBS_VCC

CBS_CCLK_E

CBS_CIRDY#21

12

R156

@

2

33_0402_5%

C266
22P_0402_50V8J

1

CBS_CC/BE2#21

CBS_RSVD/D221
CBS_CCLKRUN#21

@

BLM21A601SPT_0805@

SDDATA1_MSDATA1_XDDATA121

1 2

BLM21A601SPT_0805@

1 2

1 2

1 2

SDDATA2_MSDATA2_XDDATA221

R463

R469

L42

L43

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34

CBS_CAD13 CBS_CAD13_L

CBS_CAD15 CBS_CAD15_L

USB Signals for Epress Card

+3VS

12

R138
33K_0402_5%

XDDET0#MSDET#_XDDET1#

CBS_CAD0
CBS_CAD1
CBS_CAD3
CBS_CAD5
CBS_CAD7
CBS_CC/BE0#
CBS_CAD9 CBS_CAD10
CBS_CAD11
CBS_CAD12 CBS_CAD13_L
CBS_CAD14 CBS_CAD15_L
CBS_CC/BE1#
CBS_CPAR

CBS_CGNT#
CBS_CINT#

+CBS_VPP

CBS_CIRDY#

CBS_CC/BE2#
CBS_CAD18 CBS_CAD19
CBS_CAD20
CBS_CAD21
CBS_CAD22
CBS_CAD23
CBS_CAD24
CBS_CAD25
CBS_CAD26
CBS_CAD27 CBS_CAD28
CBS_CAD29 CBS_CAD30
CBS_RSVD/D2
CBS_CCLKRUN#

2

0_0402_5%

0_0402_5%

SDDET#_XDDET0#

SD_EN21

JPC1

1

35

2

36

3

37

4

38

5

39

6

40

7

41

8

42

9

43

10

44

11

45

12

46

13

47

14

48

15

49

16

50

17

51

18

52

19

53

20

54

21

55

22

56

23

57

24

58

25

59

26

60

27

61

28

62

29

63

30

64

31

65

32

66

33

67

34

68
69
70
71
72

SANTA_130622-2_LB

CONN@

SDDET#_XDDET0#

SDCMD_MSBS_XDWE#

35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72

[1]

2
4

SN74CBT1G384_SOT23-5

2
4

SD_EN

10K_0402_1%

R334

CBS_CCD1#
CBS_CAD2
CBS_CAD4
CBS_CAD6
CBS_RSVD/D14
CBS_CAD8

CBS_CVS1

CBS_CAD16
CBS_RSVD/A18
CBS_CBLOCK#CBS_CPERR#
CBS_CSTOP#
CBS_CDEVSEL#

CBS_CTRDY#
CBS_CFRAME#
CBS_CAD17

CBS_CVS2
CBS_CRST#
CBS_CSERR#
CBS_CREQ#
CBS_CC/BE3#
CBS_CAUDIO
CBS_CSTSCHNG

CBS_CAD31
CBS_CCD2#

[1] For R5C811, these parts are NOT installed.

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/12/1 2006/12/01

Compal Secret Data

Deciphered Date

2

+3V

U13

B
OE

U14

B
OE

SN74CBT1G384_SOT23-5

CBS_CRST#

5

VCC

1

A

3

GND

5

VCC

1

A

3

GND

+3VS

12

R347
33K_0402_5%

+3VS

U37

3

VIN

4

VIN/CE

2

12

GND

RT9701-CB_SOT23-5

CBS_CCD1# 21

CBS_RSVD/D14 21

CBS_CVS1 21

CBS_RSVD/A18 21
CBS_CBLOCK# 21
CBS_CSTOP# 21
CBS_CDEVSEL# 21

CBS_CTRDY# 21
CBS_CFRAME# 21

CBS_CVS2 21
CBS_CRST# 21
CBS_CSERR# 21
CBS_CREQ# 21
CBS_CC/BE3# 21
CBS_CAUDIO 21
CBS_CSTSCHNG 21

CBS_CCD2# 21

2

1

Title

Size Document Number Rev

Date: Sheet

L44

1 2

BLM21A601SPT_0805

+5VS

SD_MS_XDDATA1

+5VS

SD_MS_XDDATA2

[1]

1

VOUT

5

VOUT

+CBS_VCC
+CBS_VPP

C562

0.01U_0402_16V7K

@

Friday, January 06, 2006

1

1

1

C582

C576

C596

2

2

0.1U_0402_16V4Z

22U_1206_10V4Z

SDCLK_MSCLK_XDRE#

+SD_VCC

1

1

C482

0.01U_0402_16V7K

2

CBS_CAD31
CBS_CAD30
CBS_CAD29
CBS_CAD28
CBS_CAD27
CBS_CAD26
CBS_CAD25
CBS_CAD24
CBS_CAD23
CBS_CAD22
CBS_CAD21
CBS_CAD20
CBS_CAD19
CBS_CAD18
CBS_CAD17
CBS_CAD16
CBS_CAD15
CBS_CAD14
CBS_CAD13
CBS_CAD12
CBS_CAD11
CBS_CAD10
CBS_CAD9
CBS_CAD8
CBS_CAD7
CBS_CAD6
CBS_CAD5
CBS_CAD4
CBS_CAD3
CBS_CAD2
CBS_CAD1
CBS_CAD0

C485

2

1U_0603_10V4Z

Compal Electronics, Inc.

1394 & Media Card

LA-3221P

1

0.1U_0402_16V4Z

[1]

XDCE#

[1]

1

2

+3V_PHY

1

C579

C263

2

1000P_0402_50V7K~N

+XD_VCC

12

R331

2.2K_0402_5%

+3VS

12

R340
33K_0402_5%

12

R336

@

33_0402_5%

2

C512

@

22P_0402_50V8J

1

CBS_CAD[0..31] 21

of

22 43

1

2

1000P_0402_50V7K~N

0.1

5

PCIE_LAN_C_RX_P210

PCIE_LAN_C_RX_N210

D D

1 2

R181 15K_0402_5%

C C

C312 0.01U_0402_16V7K

1 2

C314 0.01U_0402_16V7K

1 2

B B

A A

PCIE_LAN_C_RX_P2
PCIE_LAN_C_RX_N2

power trace width=20mil

+3VS

12

R182
1K_0402_5%

1 2

2

25MHZ 20PF XSL025000FK1H-O

C20

1

27P_0402_50V8J

R185
0_0805_5%

@

C313 0.01U_0402_16V7K

1 2

C315 0.01U_0402_16V7K

1 2

RJ45_TX3­RJ45_TX3+
RJ45_RX1­RJ45_TX2­RJ45_TX2+
RJ45_RX1+
RJ45_TX0­RJ45_TX0+

5

Y1

1 2

C296 0.1U_0402_16V4Z

1 2

C295 0.1U_0402_16V4Z

1 2
PCIE_LAN_C_TX_P210
PCIE_LAN_C_TX_N210

CLK_PCIE_LAN13
CLK_PCIE_LAN#13

NB_RST#11,15,20,26,27,40

PCIE_WAKE#16,26

2

1

V_DACLAN_AVDD18

V_DAC

V_DAC

12
11

10

1 2

R184 2.49K_0402_1%

C21

27P_0402_50V8J

FBML10160808121LMT_0603

MDIN3
MDIP3

MDIN2
MDIP2

V_DAC
MDIN1
MDIP1

V_DAC
MDIN0
MDIP0

JLAN1

Amber LED+
Amber LED-

8

PR4-

7

PR4+

6

PR2-

5

PR3-

4

PR3+

3

PR2+

2

PR1-

1

PR1+
Green LED-

9

Green LED+

TYCO_1566735-1

RTL_LAN_TX_P2

RTL_LAN_TX_N2
PCIE_LAN_C_TX_P2
PCIE_LAN_C_TX_N2

CLK_PCIE_LAN
CLK_PCIE_LAN#
NB_RST#

LAN_CTRL18
LAN_CTRL15

RSET

ISOLATEB

LAN_XTAL1
LAN_XTAL2

LAN_GVDD

1 2

C311 0.1U_0402_10V6K

1 2

C310 1U_0402_6.3V4Z

LAN_EGND

12

L22

T1

1

TCT1

2

TD1+

3

TD1-

4

TCT2

5

TD2+
TD2-6MX2-

7

TCT3

8

TD3+

9

TD3-

10

TCT4

11

TD4+

12

TD4-

BOTH_GST5009-LF

16

SHLD4

15

SHLD3

14

SHLD2

13

SHLD1

MCT1
MX1+

MX1-

MCT2
MX2+

MCT3
MX3+

MX3-

MCT4
MX4+

MX4-

4

U1

29

HSOP

30

HSON

23

HSIP

24

HSIN

26

REFCLK_P

27

REFCLK_N

20

PERSTB

1

VCTRL18

63

VCTRL15

64

RSET

19

LANWAKEB

36

ISOLATEB

60

CKXTAL1

61

CKXTAL2

62

GVDD

25

EGND

31

EGND

17

NC

18

NC

35

NC

34

NC

39

NC

40

NC

42

NC

50

NC

51

NC

65

GND

RTL8111B-GR_QFN64

24

RJ45_TX3-

23

RJ45_TX3+

22
21

RJ45_TX2-

20

RJ45_TX2+

19
18

RJ45_RX1-

17

RJ45_RX1+

16
15

RJ45_TX0-

14

RJ45_TX0+

13

4

EEDO

EDDI/AUX

EESK
EECS

LED3
LED2
LED1
LED0

MDIP0
MDIN0
MDIP1
MDIN1

MDIP2
MDIN2
MDIP3
MDIN3

VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15

VDD33
VDD33
VDD33

VDD33
AVDD33
AVDD33

AVDD18
AVDD18
AVDD18
AVDD18

EVDD18
EVDD18

RP1

1 8
2 7
3 6
4 5

75_1206_8P4R_5%

LAN_EEDO

45

LAN_EEDI

47

LAN_EECLK

48

LAN_EECS

44

54
55
56
57

MDIP0

3

MDIN0

4

MDIP1

6

MDIN1

7

MDIP2

9

MDIN2

10

MDIP3

12

MDIN3

13

LAN_DVDD15

15
21
32
33
38
41
43
49
52
58

16
37
53
46

LAN_AVDD33

2
59

LAN_AVDD18

5
8
11
14

22
28

LAN_EGND

C297
1000P_1206_2KV7K

12

1 2

C608 0.1U_0402_10V6K

1 2

C609 0.1U_0402_10V6K

1 2

C610 0.1U_0402_10V6K

1 2

C611 0.1U_0402_10V6K

3

R188

LAN_EVDD18

3.6K_0402_5%

1 2

U20

4

DO

GND

3

DI

NC

2

SK

NC

1

CS

VCC

AT93C46-10SU-2.7 SO 8P

1.5v & 1.8v output power trace width=40mil

+LAN_IO

C308 0.1U_0402_16V4Z
C303 0.1U_0402_16V4Z

1

1

C60.1U_0402_10V6K

2

1

C50.1U_0402_10V6K

2

2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

+LAN_IO

5

R189

6

1 2

0_0402_5%

7

@

8

FBML10160808121LMT_0603

1 2
1 2

R183 0_0805_5%

1 2

C292

4.7U_0805_10V4Z

3

1

C323

0.1U_0402_16V4Z

+LAN_IO

2

+3VALW

L5

FBM-L11-321611-260-LMT_1206

1 2

1

C17

1U_0603_10V6K

L23

12

+LAN_IO

LAN_AVDD18

LAN_CTRL15

1

2005/12/1 2006/12/01

2

LAN_CTRL18

+3VALW

要改

Only For 8111B and 8100E application

3

Q3
2SB1188_SOT89

2

2SB1182

1

1

C1922U_1206_10V4Z

2

Compal Secret Data

Deciphered Date

2

+LAN_IO

1

C12

22U_1206_10V4Z

+3VALW

Only For 8111B and 8100E application

3

Q21
2SB1188_SOT89

2

1

1

C180.1U_0402_10V6K

C2930.1U_0402_10V6K

2

2

2

1

C302

0.1U_0402_10V6K

2

2

1

1

C2980.1U_0402_10V6K

C3094.7U_0805_10V4Z

2

2

LAN_DVDD15

1

1

C150.1U_0402_10V6K

C3040.1U_0402_10V6K

2

2

1

1

C306

0.1U_0402_10V6K

2

1

C3010.1U_0402_10V6K

2

1

1

C160.1U_0402_10V6K

C3050.1U_0402_10V6K

2

2

Title

Size Document Number Rev

Custom

Date: Sheet

LAN_AVDD18

1

C2940.1U_0402_10V6K

2

1

C80.1U_0402_10V6K

2

1

C291

0.1U_0402_10V6K

2

1

1

C3000.1U_0402_10V6K

C3160.1U_0402_10V6K

2

2

1

C130.1U_0402_10V6K

2

Realtek 8100CL/RJ45
LA-3221P

1

C299

0.1U_0402_10V6K

2

1

C31722U_1206_10V4Z

2

1

1

1

1

C70.1U_0402_10V6K

C140.1U_0402_10V6K

C3070.1U_0402_10V6K

2

2

1

C90.1U_0402_10V6K

2

2

of

23 43Friday, January 06, 2006

0.1

A

B

C

D

E

F

G

H

MDC CONN.

MDC_HD_SDOUT

W=20 mil

1

C519

2

10P_0402_50V8J

MDC_HD_BITCLK

+3V

1

C521

2

4.7U_0805_10V4Z

0.1U_0402_16V4Z

C520

@

1 2

MDC_ACZ_BITCLK_TERM

1

2

R342

@

10_0402_5%

MDC_ACZ_SDOUT_MDCTERM

1 2

1

2

R416

@

C546

@

10_0402_5%

10P_0402_50V8J

Adjustable Output

U28

4

VIN

2

SENSE or ADJ

DELAY
ERROR7CNOISE

C397

C133

1 1

4.7U_0805_10V4Z

+5VS

R61 10K_0402_5%

0.1U_0402_16V4Z

1 2

8

SD

SI9182DH-AD-T1-E3_MSOP8~N

VOUT

GND

5
6
1
3

C396 0.01U_0402_16V7K

1 2

12

R69

30.1K_0402_1%

R68
10K_0603_1%

+VDDA+5VS

1

2

C409 4.7U_0805_10V4Z

HD_SDIN116

C410 0.1U_0402_16V4Z

R415

1 2

33_0402_5%

MDC_HD_SDOUT

MDC_HD_SYNC

MDC_HD_RST#

MDC_HD_SDOUT16

MDC_HD_SYNC16
MDC_HD_RST#16

1 2

C545 10P_0402_50V8J@

1 2

C544 10P_0402_50V8J@

1 2

C543 10P_0402_50V8J@

MDC_HD_SDOUT
MDC_HD_SYNC

HD_SDIN1_MDC
MDC_HD_RST#

JMDC1

1

GND1

3

IAC_SDATA_OUT

5

GND2

7

IAC_SYNC

9

IAC_SDATA_IN

11

IAC_RESET#

131314141515161617171818191920

RES0
RES1

3.3V
GND3
GND4

IAC_BITCLK

2
4
6
8
10
12

20

ACES_88023-12001~N

Connector for MDC Rev1.5

check Azalia MDC Module

MDC_HD_BITCLK16

MDC_POWER

MDC_HD_BITCLK

0_0603_5%

1 2

R339

HD Audio Codec

20mil

DVDD11DVDD2

MONO_O

HP_OUT_L

HP_OUT_R

BIT_CLK

SDATA_IN

GPIO2

GPIO3

VREF

DCVOL

SENSE B

GPIO0
GPIO1

JDREF
AVSS1
AVSS2

0.1U_0402_16V4Z

9

35
36
37
39
41

6
8
2

3
29
30
28
27
32

31
33
34
43
44

40
26
42

1

1

C199

C167

2

2

0.1U_0402_16V4Z

C442 1000P_0402_50V7K~N@

C437 1000P_0402_50V7K~N@

LINEL
LINER

C204 1000P_0402_50V7K~N@

C203 1000P_0402_50V7K~N@

HP_LOUT
HP_ROUT

1 2

R99 0_0402_5%

AC97_SDIN0_CODEC

R98

R101 0_0402_5%

10mil

10mil

+MIC1_VREFO_L

+MIC1_VREFO_R

+AVDD_AC97

L28

+VDDA

2 2

3 3

HD_RST#16
HD_SYNC16
HD_SDOUT16

1 2

FBM-L11-160808-800LMT_0603

10U_1206_16V4Z

MIC125
MIC225

2

2

C163

1

@

10P_0402_25V8K

C193

C165

1

@

@

10P_0402_25V8K

10P_0402_25V8K

2

1

1

C433

2

C162 1U_0603_10V6K
C166 1U_0603_10V6K

EAPD25

R120

0_0402_5%@

1 2

0.1U_0402_16V4Z

C202

1 2
1 2

1

2

0.1U_0402_16V4Z

C_MIC1
C_MIC2

R121

40mil

1

C432

2

0_0402_5%@

U9

14
15
16
17
23
24
18
20
19
21
22
13
12

11
10

5

45
46

47

12

48

4
7

38

AVDD125AVDD2
LINE2_L
LINE2_R
MIC2_L
MIC2_R
LINE1_L
LINE1_R
CD_L
CD_R
CD_GND
MIC1_L
MIC1_R
SENSE A
BEEP

RESET#
SYNC
SDATA_OUT
NC

NC
SPDIFI/EAPD
SPDIFO
DVSS1

DVSS2

ALC262-GR_LQFP48~N

MIC1_VREFO_L

MIC1_VREFO_R

LINE_OUT_L

LINE_OUT_R

LINE1_VREFO

MIC2_VREFO

LINE2_VREFO

DGND AGND

10_0402_5% @

1 2

12

AC97_VREF

12

R118
20K_0402_1%

For EMI

0_0603_5%

1 2

R116

1

C205
10U_1206_16V4Z

2

R100

0_0402_5%

1 2

26

26

+3VS

10P_0402_25V8K

12

1 2

@

HD_SDIN0 16

EAPD 25

10K_0402_5%
R102

1 2

R268 0_0603_5%

1 2

R270 0_0603_5%

1 2

R117 0_0603_5%

1 2

R119 0_0603_5%

C194

HD_BITCLK 16

10mil

1

C192
10U_0805_10V4Z

2

AMP_LEFT 25
AMP_RIGHT 25

HP_LEFT 25
HP_RIGHT 25

Reserved for TEST

1 2

R233 0_0805_5%

1 2

R140 0_0805_5%

1 2

R133 0_0805_5%

1 2

R53 0_0805_5%

GND AGND

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

C

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

D

2005/12/1 2006/12/01

E

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

F

Date: Sheet

Compal Electronics, Inc.

Codec ALC262

LA-3221P

G

0.1

of

24 43Friday, January 06, 2006

H

A

W=40Mil

1

1

2

2

12

R237
10K_0402_5%

C124
10U_0805_10V4Z

7

RIN+

17

RIN-

9

LIN+

5

LIN-

19

SHUTDOWN

16

15

VDD

PVDD1

GND41GND311GND213GND1

P3017THF B0 TSSOP 20P

20

PLUG_IN

C386

0.1U_0402_16V4Z

4 4

AMP_RIGHT24

AMP_LEFT24

3 3

EC_MUTE27

C122

0.47U_0603_16V4Z

C391

0.47U_0603_16V4Z

C125

0.47U_0603_16V4Z

C392

0.47U_0603_16V4Z

+3VS

12

R37
100K_0402_5%

13

D

Q10

2

2N7002LT1G_SOT23

G

S

1 2

1 2

1 2

1 2

AMP_R

AMP_L

6

PVDD2

GAIN0
GAIN1

ROUT+

ROUT-

LOUT+

LOUT-

BYPASS

2

G

B

U5

2
3

18

14

4

8

12

NC

10

13

D

S

+5VS

+5VS

2

C131

0.47U_0603_16V4Z

1

Q33
2N7002LT1G_SOT23

R44 10K_0402_5%@

1 2

R42 10K_0402_5%

1 2

SPK_R1

SPK_R2

SPK_L1

SPK_L2

1 2

R41 0_0603_5%

1 2

R40 0_0603_5%

1 2

R38 0_0603_5%

1 2

R39 0_0603_5%

GAIN0 GAIN1 GAIN

C

R43 10K_0402_5%@

1 2

R45 10K_0402_5%

1 2

INTSPK_R1

INTSPK_R2

INTSPK_L1

INTSPK_L2

00

0

1

6dB

10dB

MIC224
MIC124

HP_OUTR
HP_OUTL

1 2

L10 CHB2012U170_0805

1 2

L9 CHB2012U170_0805

R131 47_0402_5%

1 2

R132 47_0402_5%

1 2

1K_0402_5%@

D

Speaker Connector

INTSPK_R1
INTSPK_R2
INTSPK_L1
INTSPK_L2

JSPK1

1

1

2

2

3

3

4

4

5

G1

6

G2

MOLEX_53398-0471~N

MICROPHONE IN JACK

R953K_0402_5%
R943K_0402_5%

12
12

220P_0402_50V7K

+MIC1_VREFO_R
+MIC1_VREFO_L

MIC-2
MIC-1

C149

1

2

HEADPHONE OUT JACK

0.1U_0402_16V4Z

1 2

L17 CHB2012U170_0805

1 2

L18 CHB2012U170_0805

R129
1K_0402_5%@

470P_0402_50V7K

HPR
HPL

HP_R
HP_L

R130

PLUG_IN

12

12

1

C150

2

220P_0402_50V7K

C206

2

C208

1

JMIC1

5
4
3

6
2
1

FOX_JA6333L-B1ST-7F~N

+3VS

12

12

2

C207
470P_0402_50V7K

1

E

R123
10K_0402_5%

JHP1

5
4
3

6
2
1

FOX_JA6333L-B1ST-7F~N

EAPD24

EAPD

*

Buzzer need to support ICH/PCM_SPK/Battery_low and WL_on/off

2 2

BUZR_OFF27

EC Beep

0.1U_0402_16V4Z

A

1 2

R501
0_0402_5%

BUZR_OFF27

1 2

R504
0_0402_5%

BUZR_OFF27

1 2

R505
0_0402_5%

BEEP#27

CardBus Beep

PCM_SPK#21

1 1

ICH Beep

SB_SPKR16

C603

BUZR

+3VS

12

14

P

I2O

G

7

I5O

I9O

1

U46A

3

OE#

SN74LVC125APWLE_TSSOP14

4

U46B

6

OE#

SN74LVC125APWLE_TSSOP14

10

U46C

8

OE#

SN74LVC125APWLE_TSSOP14

R506
10K_0402_5%@

1 2

R510
0_0402_5%@

12

B

+5VS

C

2

B

E

D16

CH751H-40_SC76

2 1

12

R509

56.2_0603_1%

12

C606
1U_0805_50V4Z

BUZZER

1

Q41
2SC2411KT146 NPN SOT23

3

0

1

1

15.6dB

21.6dB1

PLUG_IN
EAPD

HP_RIGHT24

BUR1

+

1
2

-

LET9040-03A_2P

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2005/12/1 2006/12/01

HP_LEFT24

Compal Secret Data

Deciphered Date

+3VS

5

U12

2

P

B

4

Y

1

A

G

NC7SZ08P5X_NL_SC70-5

3

R137

6.8K_0603_5%

HP_INR HPINR

1 2

C221 2.2U_0603_6.3V4Z

1 2

C216 2.2U_0603_6.3V4Z

1 2

HP_INL HPINL

1 2

R136

6.8K_0603_5%

D

HP_MUTE#

HP_MUTE#

1

2

C219
1U_0603_10V4Z

+3VS

Reserve the 0 ohm resistor.

12

for voltage filtering

R141

0_0603_5%

U11

14

SHDNR#

18

SHDNL#

15

INR

13

INL

1

C1P

3

C1N

Title

Size Document Number Rev

Date: Sheet

1 2

C223 1U_0603_10V4Z

10

19

11

OUTR

SVDD

PVDD

PVss

SVss

5

7

1

C211
1U_0603_10V4Z

2

PGND

2

9

OUTL

4

NC-4

6

NC-6

8

NC-8

12

NC-12

16

NC-16

20

NC-20

SGND

MAX4411ETP+T_TQFN20~N

17

Compal Electronics, Inc.

AMP/Audio Jack

LA-3221P

HP_OUTR
HP_OUTL

E

25 43Friday, January 06, 2006

0.1

of

A

PCI_AD[0..31] 15,19,21

WLAN_LINK27

WLAN_OFF#27

PCI_PIRQG#15,21

1 1

2 2

CLK_PCI_MINI15

PCI_REQ#115

PCI_CBE#315,21

PCI_CBE#215,21
PCI_IRDY#15,21

PM_CLKRUN#15,21,27

PCI_SERR#15,21
PCI_PERR#15,21

PCI_CBE#115,21

+5VS

WLAN_LINK

WLAN_OFF#

PCI_PIRQG#

R165 0_0402_5%

CLK_PCI_MINI
PCI_REQ#1
PCI_AD31

PCI_AD29
PCI_AD27

PCI_AD25
PCI_CBE#3

PCI_AD23
PCI_AD21

PCI_AD19
PCI_AD17

PCI_CBE#2
PCI_IRDY#

PM_CLKRUN#
PCI_SERR#

PCI_PERR#
PCI_CBE#1
PCI_AD14

PCI_AD12
PCI_AD10

PCI_AD8
PCI_AD7

PCI_AD5
PCI_AD3
PCI_AD1

+5VS

1 2

2

C274

0.1U_0402_16V4Z

1

+3VS

JMPCI1

112

KEY KEY

334
556
778
9910
111112
131314
151516
171718
191920
212122
232324
252526
272728
292930
313132
333334
353536
373738
393940
414142
434344
454546
474748
494950
515152
535354
555556
575758
595960
616162
636364
656566
676768
696970
717172
737374
757576
777778
797980
818182
838384
858586
878788
898990
919192
939394
959596
979798
9999100

101

101

103

103

105

105

107

107

109

109

111

111

113

113

115

115

117

117

119

119

121

121

123

123

125

125

TYCO_1734064-3

102
104
106
108
110
112
114
116
118
120
122
124
126

B

+3VS

2
4

6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126

WLAN_ACT

PCI_PIRQF#

PCI_RST#
PCI_GNT#1
WLANPME#
PCI_AD30
PCI_AD28

PCI_AD26
PCI_AD24
MINIDSEL

PCI_AD22
PCI_AD20
PCI_PAR
PCI_AD18
PCI_AD16

PCI_FRAME#
PCI_TRDY#
PCI_STOP#

PCI_DEVSEL#
PCI_AD15

PCI_AD13
PCI_AD11

PCI_AD9
PCI_CBE#0

PCI_AD6
PCI_AD4
PCI_AD2
PCI_AD0

+3V

2

C592

0.1U_0402_16V4Z

1

PCI_PIRQF# 15,21

PCI_RST# 15,21
PCI_GNT#1 15

WLANPME# 21,27

R490

10K_0402_5%

1 2

R496

100_0402_5%

PCI_PAR 15,21

PCI_FRAME# 15,21
PCI_TRDY# 15,21
PCI_STOP# 15,21

PCI_DEVSEL# 15,21

PCI_CBE#0 15,21

CLK_PCI_MINI

R500
10_0402_5%@

1 2

12

PCI_AD22

+3V

2

1

PCIE_WLAN_C_RX_N110
PCIE_WLAN_C_RX_P110

C

R489

+5VS

0_0402_5%

2

C588

0.1U_0402_16V4Z

1

C589

0.1U_0402_16V4Z

IDSEL:PCI_AD22

PCIE_WLAN_C_TX_N110

PCIE_WLAN_C_TX_P110

PCIE_WAKE#16,23

WLAN_ACT MINI_PIN3

CLKREQB#13

CLK_PCIE_WCARD#13

CLK_PCIE_WCARD13

PCIE_WLAN_C_RX_N1
PCIE_WLAN_C_RX_P1

1 2

R332 0_0402_5% @

CLK_PCIE_WCARD#
CLK_PCIE_WCARD

R147 0_0402_5%

1 2
1 2

R148 0_0402_5%

PCIE_WLAN_C_TX_N1
PCIE_WLAN_C_TX_P1

Wireless_BTN

Killer switch

+3VS

@

12

R172

SW2

1BS003-1211L_3P

11223

3

D

2

C536

0.1U_0402_16V4Z

1

2

C567

0.1U_0402_16V4Z

1

2

C506

0.1U_0402_16V4Z

1

2

C568

0.1U_0402_16V4Z

1

Mini-Express Card

JMINI1

PCIE_C_RXN2
PCIE_C_RXP2

1

1

3

3

5

5

7

7

9

9

11

11

13

13

15

15

17

17

19

19

21

21

23

23

25

25

27

27

29

29

31

31

33

33

35

35

37

37

39

39

41

41

43

43

45

45

47

47

49

49

51

51

53

GND1

FOX_AS0B226-S52N-7F~N

GND2

2

2

4

4

6

6

8

8

10

10

12

12

14

14

16

16

18

18

20

20

22

22

24

24

26

26

28

28

30

30

32

32

34

34

36

36

38

38

40

40

42

42

44

44

46

46

48

48

50

50

52

52

54

+3VALW

+1.5VS

+1.5VS

1

C557
10U_1206_16V4Z

2

+3VS

1

C487
10U_1206_16V4Z

2

+3VS

MINI_PIN46

WLAN_OFF# 27
NB_RST# 11,15,20,23,27,40

SMB_CK_CLK1 8,9,13,16

SMB_CK_DAT1 8,9,13,16

USB20P4- 16
USB20P4+ 16

WLAN_LINK

1 2

R424 0_0402_5%

2

C533

0.1U_0402_16V4Z

1

WLAN_ACT

E

1

2

+3VALW

C530
10U_1206_16V4Z

100K_0402_5%

WLAN_OFF#

R171

1.5M_0402_5%

1 2

+3VS

10K_0402_5%

WLAN_ACT

2005/12/1 2006/12/01

2

G

Compal Secret Data

WLAN_OFF# 27

12

R170

13

D

Q18
2N7002LT1G_SOT23

S

Deciphered Date

WLAN_LINK

WLAN_ACT#

D

+3VS

1

B

2

A

5

U17

P

4

Y

G

TC7SH08FU_SSOP5

3

WLAN_LINK#27

D1 Pin3 Open PAST & MASK layer

WLAN LED

D17
12-21-BHC-ZL1M2RY-2C BLUE

12

1 2

13

WLAN_LED

D

2

G

S

WLAN_LINK#

Title

Size Document Number Rev

Custom

Date: Sheet

D18

12-21-BHC-ZL1M2RY-2C_AMBER
Q19
2N7002LT1G_SOT23

13

D

2

G

S

Q20
2N7002LT1G_SOT23

MINI PCI
LA-3221P

100_0603_1%

12

1 2

300_0603_5%

E

R507

R508

26 43Friday, January 06, 2006

+5VS

0.1

of

+3VS

CLK_PCI_MINI_TERM

2

1

C600

4.7P_0402_50V8C

@

1 2

R166 10K_0402_5%@

1 2

R164 10K_0402_5%

WLAN_OFF#

WLAN_LINK

3 3

4 4

1

C587

1000P_0402_50V7K~N

2

2

C594

0.1U_0402_16V4Z

1

2

C275

0.1U_0402_16V4Z

1

2

C273

0.1U_0402_16V4Z

1

2

C272

0.1U_0402_16V4Z

1

2

C277

0.1U_0402_16V4Z

1

2

C590

0.1U_0402_16V4Z

1

1

C278

10U_1206_16V4Z

2

2

C276

0.1U_0402_16V4Z

1

+5VS

+3VS

1

C279
10U_1206_16V4Z

2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

5

L39

WLANPME#21,26

TP_DATA
TP_CLK
EC_MUTE

LID_SW#
FRD#
FSEL#

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20

Ra

Rb

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

1 2

MBK1608800YZF 0603

0.1U_0402_16V4Z

1 2

L41 MBK1608800YZF 0603

R379 0_0402_5%

RP26

1 8
2 7
3 6
4 5

10K_0804_8P4R_5%

RP23

1 8
2 7
3 6
4 5

10K_0804_8P4R_5%

+3VALW

12

R335

@

100K_0402_5%

12

R338

@

8.2K_0402_5%

E-Mail_BTN
Internet_BTN

10K_0402_5%

1 2
1 2

10K_0402_5%

+5VS

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
LPC_FRAME#
LDRQ0#
NB_RST#

CLK_PCI_SIO_DBR
SIRQ

1

2

1

1 2

+3VALW

+5VS

C526

ECAGND

R330

1 2

47K_0402_5%

0.1U_0402_16V4Z

C527
1000P_0402_50V7K~N

2

+3VALW

1 2

C503

08/17: modify

EC_SMB_DA1
EC_SMB_CK1
EC_SMB_DA2
EC_SMB_CK2

+3VALW

2

1

FOR Board ID

AD_BID0

1

C524

0.1U_0402_16V4Z

2

+3VALW

FOR LPC SIO DEBUG PORT

R362

+3VS

R446

LDRQ0# 15

5

+3VALW +EC_AVCC

D D

C C

B B

JLPC1

A A

ACES_85201-2005 CONN@

+3VALW

R371
10K_0402_5%

EC_PME#

EC_RST#

2

1

R378 4.7K_0402_5%
R370 4.7K_0402_5%
R390 4.7K_0402_5%
R384 4.7K_0402_5%

C539
1000P_0402_50V7K~N

@

10K_0402_5%@

1 2

R169

22_0402_5%@

PWRBTN_OUT#16

R168

1 2

0_0805_5%

LPC_AD[0..3]15

LPC_FRAME#15,19

KSO[0..15]28

12
12
12
12

PWR_GREEN_LED#14,30

BATT_FULL_LED#14,30

PWR_AMBER_LED#14,30

BKOFF#14
SLP_S3#16

SLP_S5#16

12

R480

1

2

0.1U_0402_16V4Z

EC_GA2016
KB_RST#16

SIRQ15,21

CLK_PCI_EC15

NB_RST#11,15,20,23,26,40

EC_SCI#16

PM_CLKRUN#15,21,26

KSI[0..7]28

+5VALW

SW_CONFIG128
SW_CONFIG228

EC_SMB_DA26
EC_SMB_CK26
EC_SMB_DA128,39
EC_SMB_CK128,39

NUMLED#30

CAPSLED#30

SCRLED#30

SYSON31

EC_RSMRST#16

EC_LID_OUT#16
EC_SMI#16

EC_SWI#16
SUSP#28,31

CLK_PCI_SIO_DB 15

0.1U_0402_16V4Z

C552

KSI[0..7]

KSO[0..15]

BATT_FULL_LED#

EC_SMI#
LID_SW#

EC_PME#

4

1

C532

2

EC_GA20
KB_RST#

EC_SMB_DA2
EC_SMB_CK2
EC_SMB_DA1
EC_SMB_CK1

E51_TXD

4

LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0

NB_RST#

EC_SCI#

SW_CONFIG1
SW_CONFIG2

CRY1
CRY2

0.1U_0402_16V4Z

1

C502

2

1000P_0402_50V7K~N

1

GA20/ GPIO00/GA20

2

KBRST#/GPIO01/KBRST#

3

SERIRQ

5

LPC_FRAME# / LFRAME#

6

LPC AD3/LAD3

9

LPC AD2/LAD2

10

LPC AD1/LAD1

12

LPC AD0/LAD0

14

CLK_PCI_EC/PCICLK

15

PCIRST#

42

EC RST#/ ECRST#

24

EC SCI#/SCI#/GPIO0E

44

PM_CLKRUN#/ CLKRUN#

KSI0

63

KSI0/GPIO30

KSI1

64

KSI1/GPIO31

KSI2

65

KSI2/GPI032

KSI3

66

KSI3/GPIO33

KSI4

67

KSI4/GPIO34

KSI5

68

KSI5/GPI035

KSI6

69

KSI6/GPIO36

KSI7

70

KSI7/GPIO37

KSO0

47

KSO0/GPIO20

KSO1

48

KSO1/GPIO21

KSO2

49

KSO2/GPIO22

KSO3

50

KSO3/GPIO23

KSO4

51

KSO4/GPIO24

KSO5

52

KSO5/GPIO25

KSO6

53

KSO6/GPIO26

KSO7

54

KSO7/GPIO27

KSO8

55

KSO8/GPIO28

KSO9

56

KSO9/GPIO29

KSO10

57

KSO10/GPIO2A

KSO11

58

KSO11/GPIO2B

KSO12

59

KSO12/GPIO2C

KSO13

60

KSO13/GPIO2D

KSO14

61

KSO14/GPIO2E

KSO15

62

KSO15/GPIO2F

89

EC URXD/KSO16/GPIO48

90

EC UTXD/KSO17/GPIO49

88

EC SMD2/ GPIO47/SDA2

87

EC SMC2/GPIO46/SCL2

86

EC SMD1/GPIO44/SDA1

85

EC SMC1/GPIO44/SCL1

34

PCM_SPK#/EMAIL_LED#/ GPIO16

35

SB_SPKR/PWR_SUSP_LED#/ GPIO17

38

PWRLED#/ GPIO19

40

NUMLED#/ GPIO1A

99

BATT CHGI LED#/ E51CS#

101

BATT LOW LED#/ E51MR0

100

CAPS LED#/ E51TMR1

102

ARROW LED#/ E51 INT0

104

SYSON/GPIO56/ E51 INT1

4

EC_RSMRST#/ GPIO02

7

BKOFF#/GPIO03

8

PM SLP S3#/GPIO04

16

EC LID OUT#/GPIO06

17

PM SLP S05#/ GPIO07

18

EC SMI#/GPIO08

19

EC SWI#/GPIO09

20

LID SW#/ GPIO0A

21

SUSP#/GPIO0B

22

PBTN_OUT#/GPIO0C

23

EC PME#/GPIO0D

140

XCLKO

138

XCLKI

3

1

2

U40

C577

C578

2

Host

INTERFACE

key Matrix

scan

1000P_0402_50V7K~N

1

+EC_AVCC

C505

11

139

75

127

141

26

105

VCC

VCC

VCC/ EC VCC

VCC / EC VCC

VCC / EC VCC37VCC / EC VCC

PWR

FAN/PWM

INVT_PWM/GPIO0F/PWM1

OUT BEEP/GPIO12/PWM3

FAN SPEED1/GPIO14/FANFB1
FAN SPEED2/GPIO15/FANFB2

PS2 interface

Data
BUS

Address

BUS

SM BUS

GND13GND28GND

GND

GND

GND

39

103

129

BATTEMP/AD0/GPIO38

BATT OVP/AD1/GPIO39

ADP_I/AD2/GPIO3A

AD BID0/AD3/GPIO3B

AD INtput or GPI

EC_AVCC / AVCC

DAC_BRIG/DA0/GPIO3D

EN DFAN1/DA1/GPIO3D

IREF2/DA2

EN DFAN2/DA3/ GPIO3F

DA output or GPO

BEEP#/GPIO10/PWM2

ACOFF/GPIO18/PWM4

PSCLK1
PSDAT1
PSCLK2
PSDAT2
PSCLK3
PSDAT3

ADB0/D0
ADB1/D1
ADB2/D2

ADB3/ D3

ADB4/D4
ADB5/D5
ADB6/D6
ADB7/D7

KBA0/A0
KBA1/A1
KBA2/A2
KBA3/A3
KBA4/A4
KBA5/A5
KBA6/A6
KBA7/A7
KBA8/A8

KBA9/A9
KBA10/A10
KBA11/A11
KBA12/A12
KBA13/A13
KBA14/A14
KBA15/A15
KBA16/A16
KBA17/A17
KBA18/A18
KBA19/A19

SELIO2#/ GPIO43

SELIO#/ GPIO50

FRD#/RD#

FWR#/WR#

FSEL#/SELMEM#

EC ON/ GPIO1B

AC IN/ GPIO1C

ECTHERM#/GPIO11

ONOFF/GPIO18

PCMRST#/GPIO1E

WL OFF#/GPIO1F

ALI/MH#/GPIO40

FSTCHG/GPIO41

VR ON/ GPIO42
GPIO57/GPIO57
GPIO58/GPIO58
GPIO59/GPIO59

AGND

77

ECAGND

71
72
73
74

76
78
79
80

25
27
30
31
32
33

91
92
93
94
95
96

125
126
128
130
131
132
133
134
111
112
113
114
115
116
117
118
119
120
121
122
123
124
110
109
108
107
106
98

84
97
135
136
144

41
43
29
36
45
46

81
82
83
137
142
143

KB910L_LQFP144

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

1 2

EC_ADC
AD_BID0

VLDT_EN

FAN_SPEED1

EC_MUTE

BUZR_OFF
TP_CLK

TP_DATA

E-Mail_BTN
Internet_BTN

EC_THERM#

ENABLT

+5VALW

E51_TXD

2005/12/1 2006/12/01

0.01U_0402_16V7K

BATT_TEMP 39

BATT_OVP 34
EC_ADC 38

DAC_BRIG 14
EN_DFAN1 4
IREF 34

VLDT_EN 30,36,40

INVT_PWM 14
BEEP# 25

SW_RSV2 28

ACOFF 33,34

FAN_SPEED1 4
SW_RSV1 28

EC_MUTE 25

BUZR_OFF 25
TP_CLK 28
TP_DATA 28

ADB0
ADB1
ADB2
ADB3
ADB4
ADB5
ADB6
ADB7
KBA0
KBA1
KBA2
KBA3
KBA4
KBA5
KBA6
KBA7
KBA8

KBA9
KBA10
KBA11
KBA12
KBA13
KBA14
KBA15
KBA16
KBA17
KBA18
KBA19

JECDB1

1
2
3
4

ACES_85205-0400

CONN@

Compal Secret Data

ECAGND

ADB[0..7]

KBA[0..19]

E-Mail_BTN 30

Internet_BTN 30
FRD# 28
FWR# 28
FSEL# 28

EC_ON 30,35
ACIN 33,35
EC_THERM# 16
ON_OFF 30
WLAN_LINK# 26
WLAN_OFF# 26

ENABLT 11,14

FSTCHG 34

VR_ON 38

MSEN# 14

WLAN_LINK 26

VGATE 38

1
2
3
4

Deciphered Date

2

ADB[0..7] 28

KBA[0..19] 28

LC2A KH3

KBSEL0# SW_CONFIG1

KBSEL1# SW_CONFIG2

FINGERPRINT#

10P_0402_50V8J

2

KBA0
KBA1
KBA2
KBA3
KBA4
KBA5

NB_RST#

SW_CONFIG1
SW_CONFIG2
SW_RSV1
SW_RSV2

LID_SW#

R484 10K_0402_5%@
R483 10K_0402_5% @
R486 10K_0402_5%@
R485 10K_0402_5%@
R482 10K_0402_5%@
R481 10K_0402_5%@

1 8
2 7
3 6
4 5

10K_0804_8P4R_5%

SW_RSV1

SW_RSV2

1 2

R477 20M_0603_5%@

1

C580

32.768K 20PPM Q13MC30610003

1

2

IN

2

1

+3VALW

1 2
1 2
1 2
1 2
1 2
1 2

R418

1 2

100K_0402_5%@

+3VALW

RP20

+3V

Q36

S

MRSS23E

G

2

D

1 3

REED Switch

CLK_PCI_EC

12

R422
10_0402_5%@

1

C548
15P_0402_50V8D@

2

CRY1

CRY2

12

0_0603_5%

R478

1

4

C583
10P_0402_50V8J

2

Y5

OUT

NC3NC

Title

Size Document Number Rev

Custom

Date: Sheet

KB910L/LIT SW
LA-3221P

1

of

27 43Friday, January 06, 2006

0.1

KSO8

C183 100P_0402_25V8K

KSI3
KSO9
KSI2
KSI1
KSO10
KSO11
KSI0
KSO12
KSO13
KSO14
KSO15

C182 100P_0402_25V8K

C195 100P_0402_25V8K

C177 100P_0402_25V8K

C181 100P_0402_25V8K

C180 100P_0402_25V8K

C196 100P_0402_25V8K

C198 100P_0402_25V8K

C179 100P_0402_25V8K

C197 100P_0402_25V8K

C178 100P_0402_25V8K

INT_KBD CONN.

(Right)

(Left)

FSEL#27
FRD#27
FWE# FWR# 27

KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15
KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7

JKB1

24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

ACES_85201-2405

CONN@

KBA0
KBA1
KBA2
KBA3
KBA4

KBA6
KBA7
KBA8
KBA9
KBA10
KBA11
KBA12
KBA13
KBA14
KBA15
KBA16
KBA17
KBA18
KBA19

FSEL#
FRD#
FWE#

KBA[0..19]27

21
20
19
18
17
16
15
14

8
7

36

6
5
4
3
2

1
40
13
37

22
24

9

SST39VF080-70-4C-EIE_TSOP40~N

KSI7
KSI6
KSI5
KSO0
KSO1
KSO2
KSI4
KSO3
KSO4
KSO5
KSO6
KSO7

0.01U_0402_16V7K

1M Byte BIOS ROM

U16

A0

VCC0

A1

VCC1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19

CE#
OE#
WE#

READY/BUSY#

GND0

GND1

RP#

NC0
NC1

C173 100P_0402_25V8K
C174 100P_0402_25V8KC176 100P_0402_25V8K
C175 100P_0402_25V8K
C191 100P_0402_25V8K
C190 100P_0402_25V8K
C189 100P_0402_25V8K
C172 100P_0402_25V8K
C188 100P_0402_25V8K
C187 100P_0402_25V8K
C186 100P_0402_25V8K
C185 100P_0402_25V8K
C184 100P_0402_25V8K

TP_DATA27
TP_CLK27

+5VS

1

C171

2

KBA[0..19]
ADB[0..7]

31
30

ADB0

25

D0
D1
D2
D3
D4
D5
D6
D7

NC

26
27
28
32
33
34
35

10
11
12
29
38

23
39

ADB1KBA5
ADB2
ADB3
ADB4
ADB5
ADB6
ADB7

BIOS_RST#

TO M/B

1

@

2

C168

100P_0402_25V8K

R161

1 2

10K_0402_5%

@

TP_DATA
TP_CLK

C169100P_0402_25V8K

+3VALW

+3VALW

1

2

1

2

KSI[0..7]
KSO[0..15]

@

C270

0.1U_0402_16V4Z

ACES_85201-0805

CONN@

10

GND

9

GND
8
7
6
5
4
3
2
1

JTP1

KSI[0..7] 27
KSO[0..15] 27

KBA14
KBA13
KBA12
KBA11
KBA10

KBA9
KBA8
KBA7
KBA6
KBA5
KBA4
KBA3
KBA2
KBA1
KBA0

BIOS_RST#

Debug Tool

JP1

1 2
3 4
5 6
7 8
9 10
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
29 30
31 32
33 34

SUYIN_127212FA034G200ZX@

Felica Conn

+5VS

F2 1.1A_6VDC_FUSE

TP24

21

1 2

0.1U_0402_16V4Z

USB20P5-16

USB20P5+16

CLR_CMOS15
SW_CONFIG127
SW_CONFIG227

SW_RSV127
SW_RSV227

+3VALW

FSEL#
FRD#
FWE#
ADB7
ADB6
ADB5
ADB4
ADB3
ADB2
ADB1
ADB0
KBA19
KBA18
KBA17
KBA16
KBA15 FWE#

+5VS_FP_FE

LEC

SW1

1
2
3
4
5
6
7
8 9

HPS608-E_16P

EC_SMB_CK127,39
EC_SMB_DA127,39ADB[0..7]27

C538

4

O

JFE1

1
2
3
4
5
6

JST_06FHJ-SM1-GB-TB(LF)(SN)~N

CONN@

ONOFF

ON

16
15
14
13
12
11
10

+5VALW

C509 0.1U_0402_16V4Z

1 2

U36

8
7
6
5

AT24C16AN-10SU-2-7 SO 8P

+3VALW

5

U39

P

I0
I1

G

TC7SH32FU(TE85L) SSOP 5P

3

+3VALW

12

2
1

VCC
WP
SCL
SDA

R361
100K_0402_5%

GND

A0
A1
A2

1
2
3
4

2

1 3

D

Q35
2N7002LT1G_SOT23

+5VALW

12

12

G

S

+5VS_FP_FE

1

C265
10U_0805_10V4Z

2

R333
100K_0402_5%

R324
100K_0402_5%

SUSP# 27,31

EC_FLASH# 16

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2005/12/1 2006/12/01

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

Date: Sheet

MDA/BT/KBD/TP Conn
LA-3221P

28 43Friday, January 06, 2006

of

0.1

A

B

C

D

E

+USB_AS

+5VS

1 1

2 2

SUSP31,37

SUSP31,37

1

C328

0.1U_0402_16V4Z

2

+5VS

1

C24

0.1U_0402_16V4Z

2

1 2

R196
0_0402_5%

1 2

R20
0_0402_5%

12

R195
100K_0402_5%

@

12

R19
100K_0402_5%

@

U23

1

GND

2

IN

3

IN

4

EN#

G528_MSOP8

U2

1

GND

2

IN

3

IN

4

EN#

G528_MSOP8

OUT
OUT
OUT
OC#

OUT
OUT
OUT
OC#

8
7
6
5

8
7
6
5

+USB_BS

W=40mils

OVCUR#0 16

W=40mils

OVCUR#1 16

12

R190
470_0805_5%

13

D

2

G

Q22

S

2N7002LT1G_SOT23

SUSP

12

R18
470_0805_5%

13

D

2

G

Q5

S

2N7002LT1G_SOT23

SUSP

R8

1 2

0_0402_5%

L6

USB20P0-16

USB20P0+16

USB20P0-

USB20P0+

WCM2012F2S-900T04_0805

3

2

3

2

R9

1 2

0_0402_5%

@

4

1

150U_D2_6.3VM

4

1

C322

4

CH4
CH11Vn2CH2

1

+

2

470P_0402_50V7K

6

5

D11

Vp

NUP4301MR6T1_TSOP6

CH3

3

+USB_AS

1

C10

2

CON-USBP0­CON-USBP0+

+USB_AS

470P_0402_50V7K

1

C11

2

JUSB1

1

VCC

2

D-

3

D+

4

GND

5

GND1

6

GND2

7

GND3

8

GND4

SUYIN_020173MR004G533ZR

3 3

+5VS

1

C25

0.1U_0402_16V4Z

2

SUSP31,37

4 4

1 2

R25
0_0402_5%

A

12

R24
100K_0402_5%

@

U3

1

GND

2

IN

3

IN

4

EN#

G528_MSOP8

OUT
OUT
OUT
OC#

+USB_CS

8
7
6
5

W=40mils

OVCUR#3 16

B

12

R21
470_0805_5%

13

D

2

G

Q8

S

2N7002LT1G_SOT23

SUSP

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2005/12/1 2006/12/01

JUSB2

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16

ACES_87212-1600

Compal Secret Data

Deciphered Date

+USB_CS+USB_BS

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

USB20P1+
USB20P1-

USB20P2+
USB20P2-

USB20P3­USB20P3+

D

USB20P1+ 16
USB20P1- 16

USB20P2+ 16
USB20P2- 16

USB20P3- 16
USB20P3+ 16

Compal Electronics, Inc.

Title

Size Document Number Rev

Friday, January 06, 2006

Date: Sheet

USB Port

LA-3221P

E

of

29 43

0.1

A

+3VALW

2

1

R252

R251

470K_0402_1%

1 2

12

0.1U_0402_16V7K~N

C407

1

2

VLDT_EN27,36,40 SB_PWRGD 6,16

1 1

VLDT_EN

10K_0402_5%

14

P

1

O2I

G

U29A

TC74LCX14FTF TSSOP 14P S-INV

7

C405

0.1U_0402_16V4Z

B

+3VALW +3VALW +3VALW

14

P

3

O4I

G

U29B

TC74LCX14FTF TSSOP 14P S-INV

7

R248
200K_0402_1%

1 2

C403

0.47U_0603_16V7K

R247
10_0402_5%

1 2

1

2

C

14

P

5

O6I

G

U29C

TC74LCX14FTF TSSOP 14P S-INV

7

NB_PWRGD 11

14

P

9

O8I

G

U29D

TC74LCX14FTF TSSOP 14P S-INV

7

note:T1 minimum 15ms,T2 minimum 33ms/maximum 500ms,
SUSP# goes to low after SB_PWRGD goes to low for power
down.

R246
10_0402_5%

1 2

D

E

T1

VLDT_EN

Power Button

+3VALW

R10
100K_0402_5%

1 2

D5

PWR_ON-OFF_BTN#

2 2

EC_ON27,35

3 3

+3VALW

EC_ON

R12

4.7K_0402_5%

1 2

1 2

R11
33K_0402_5%

DTC124EKAT146 NPN SOT23

SATA_LED#17

ODD_ACT_LED#20

DAN202U_SC70

2

1

2

Q4

CARD_LED21

3

13

SATA_LED#
ODD_ACT_LED#

51ON#

2

1

ON_OFF 27
51ON# 33

C23
1000P_0402_50V7K~N

+5VS

5

U22

1

P

B

Y

2

A

G

TC7SH08FU_SSOP5

3

+3VS

5

U21

2

P

B

Y

1

A

G

NC7SZ08P5X_NL_SC70-5

3

12

2

C325

0.1U_0402_16V4Z

1

IDE_ACT_LED#

4

2

C324

0.1U_0402_16V4Z

1

4

D6
RLZ20A_LL34

CARD_LED#

SCRLED#27
NUMLED#27
CAPSLED#27

E-Mail_BTN27
Internet_BTN27

PWR_GREEN_LED#14,27

PWR_AMBER_LED#14,27

BATT_FULL_LED#14,27

NB_PWRGD

SB_PWRGD

SUSP#

+1.8VS

SCRLED#
NUMLED#
CAPSLED#

E-Mail_BTN
Internet_BTN

T2

E-Mail_BTN

Internet_BTN

+5VS +5VALW

E-Mail_BTN
Internet_BTN
SCRLED#
NUMLED#
CAPSLED#
CARD_LED#
IDE_ACT_LED#
PWR_ON-OFF_BTN#
PWR_GREEN_LED#
PWR_AMBER_LED#
BATT_FULL_LED#

JFN1

1 2
3 4
5 6
7 8
9 10
11 12
13 14
15 16
17 18

19 20

SUYIN_80030A-020G2T

CONN@

C625 100P_0402_25V8K@
C621 100P_0402_25V8K@
C617 100P_0402_25V8K@
C615 100P_0402_25V8K@
C618 100P_0402_25V8K@
C624 100P_0402_25V8K@
C619 100P_0402_25V8K@
C623 100P_0402_25V8K@
C614 100P_0402_25V8K@
C622 100P_0402_25V8K@
C616 100P_0402_25V8K@

SCRLED#
NUMLED#
CAPSLED#
CARD_LED#
IDE_ACT_LED#

PWR_ON-OFF_BTN#

PWR_GREEN_LED#
PWR_AMBER_LED#
BATT_FULL_LED#

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2005/12/1 2006/12/01

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

D

Date: Sheet

PWR_OK/BTN
LA-3221P

E

0.1

of

30 43Friday, January 06, 2006

A

B

C

D

E

+5VALW TO +5V

+5V

0_0603_5%

1 2

R498

1

C602
1U_0805_25V4Z

2

R497

100K_0603_5%

1 2

13

D

2

G

Q40

S

2N7002LT1G_SOT23

B+_BIAS

SYSON#

+5VALW

U44

8

S

D

7

S

1 1

D

6

S

D

5

G

D

SI4800DY-T1-E3 1N SO8

1

C601
10U_1206_16V4Z

2

1

C604
10U_1206_16V4Z

2

1
2
3

5V_GATE SUSON

4

12

C599

0.1U_0603_25V7K~N

@

+5VALW

8
7
6
5

SI4800DY-T1-E3 1N SO8

1

C268

4.7U_0805_10V4Z

2

+3VALW TO +3V

+3V

1

2

0_0603_5%

1 2

R287

C466

0.22U_0603_10V7K

C431

4.7U_0805_10V4Z

R267

1 2

47K_0603_1%

1

C430

0.22U_0603_10V7K

2

C475
1U_0805_25V4Z

SUSON RUN_ON

+1.8V+1.8VALW

1

2

100K_0603_5%

1 2

C435
1U_0805_25V4Z

100K_0603_5%

1 2

R283

B+_BIAS

R266

B+_BIAS

+3VALW

8
7
6
5

SI4800DY-T1-E3 1N SO8

1

C586
10U_1206_16V4Z

2

+1.8VALW

8
7
6
5

SI4800DY-T1-E3 1N SO8

1

C436

4.7U_0805_10V4Z

2

1
2
3
4

3V_GATE

1

C469
10U_1206_16V4Z

2

1

2

+3VALW

U34

8

S

D

7

S

D

6

S

D

5

G

D

2 2

SI4800DY-T1-E3 1N SO8

1

C472
10U_1206_16V4Z

2

+1.8VALW TO +1.8V

U31

8
7
6
5

1

2

3 3

1

S

D

2

S

D

3

S

D

4

G

D

SI4800DY-T1-E3 1N SO8
C441

4.7U_0805_10V4Z

1

2

1.8V_GATE

+5VALW TO +5VS

+5VS

U15

1

S

D

2

S

D

3

S

D

4

G

D

5VS_GATE

+3VALW TO +3VS

1

U43

S

D

S

D

S

D

G

D

1
2
3
4

2

3VS_GATE

+1.8VALW TO +1.8VS

U32

1

S

D

2

S

D

3

S

D

4

G

D

1.8VS_GATE3

4.7U_0805_10V4Z

1

2

1

C269

4.7U_0805_10V4Z

2

0_0603_5%

1 2

R160

12

C267

0.1U_0603_25V7K~N

@

C574
10U_1206_16V4Z

0_0603_5%

1 2

R487

1

C595

0.22U_0603_10V7K

2

1

C444

2

R279

1 2

47K_0603_1%

C445

0.22U_0603_10V7K

+3VS

1

2

+1.8VS

1

2

1

C271
1U_0805_25V4Z

2

RUN_ON

C573
1U_0805_25V4Z

C443
1U_0805_25V4Z

RUN_ONSUSON

R158

100K_0603_5%

1 2

13

D

Q14

S

2N7002LT1G_SOT23

R479

100K_0603_5%

1 2

R280

100K_0603_5%

1 2

+5VALW

R163
10K_0402_5%

SYSON#

2

G

2

G

+5VALW

1 2

13

D

Q17
2N7002LT1G_SOT23

S

R472
10K_0402_5%

1 2

13

D

Q37
2N7002LT1G_SOT23

S

SUSP29,37

B+_BIAS

SUSP

2

G

B+_BIAS

B+_BIAS

SUSP#27,28

SYSON27

SUSP

SYSON#6,37

SYSON

+1.2V_HT

12

R23
470_0805_5%

13

D

SYSON# SYSON# SYSON#SUSP

2

G

Q9

S

2N7002LT1G_SOT23

4 4

A

12

R135
470_0805_5%

13

D

S

2

G

Q12

2N7002LT1G_SOT23

+1.8V

D

S

12

13

R22
470_0805_5%

2

G

Q7

2N7002LT1G_SOT23

+1.8VS

12

R162
470_0805_5%

13

D

SUSP

2

G

Q15

S

2N7002LT1G_SOT23

B

+3V+0.9V

12

R475
470_0805_5%

13

D

S

Q38

+5V

12

R167
470_0805_5%

13

2

G

2N7002LT1G_SOT23

D

2

G

Q16

S

2N7002LT1G_SOT23

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

12

R499
470_0805_5%

13

D

SYSON#

2

G

Q39

S

2N7002LT1G_SOT23

2005/12/1 2006/12/01

+5VS+3VS

12

R17
470_0805_5%

13

D

2

G

Q6

S

Compal Secret Data

Deciphered Date

SUSPSUSP

2N7002LT1G_SOT23

D

Title

Size Document Number Rev

Custom

Date: Sheet of

DC Interface
LA-3221P

E

31 43Friday, January 06, 2006

0.1

5

CF6

CF11
SMD40M80

1

CF9
SMD40M80

1

FD1
FIDUCAL

1

CF5
SMD40M80

@

CF7
SMD40M80

@

FD4
FIDUCAL

@

CF4
SMD40M80

1

CF12
SMD40M80

1

FD6
FIDUCAL

1

CF3
SMD40M80

@

CF13
SMD40M80

@

1

1

SMD40M80

@

@

1

1

CF14
SMD40M80

@

@

1

1

FD5
FIDUCAL

@

@

1

1

@

1

CF1
SMD40M80

@

1

D D

FD3
FIDUCAL

@

1

C C

B B

CF2
SMD40M80

@

FD2
FIDUCAL

@

@

1

@

1

@

1

CF10

CF8

SMD40M80

SMD40M80

@

4

H1

H4

HOLEA@

HOLEA@

1

1

H20

H2

HOLEA@

HOLEA@

1

1

H3
HOLEA@

H_C315D197P2

1

H13

H21

HOLEA@

HOLEA@

1

1

H8

H9

HOLEA@

HOLEA@

1

1

H7

H15

HOLEA@

HOLEA@

1

1

H16
HOLEA@

H_R335X394D118L30P2

1

H19

H17

HOLEA@

HOLEA@

1

1

H22
HOLEA@

H_R354X374D118R20D30P2

1

H24
HOLEA@

H_O177X122D177X122N

1

H_R453X394D118P2

H_S315D118P2

H5

H14

HOLEA@

1

H12
HOLEA@

1

H10

HOLEA@

HOLEA@

1

1

H11
HOLEA@

H_C276D165P2--- CPU

1

H_C236D118BR335X295P2

H18
HOLEA@

H_C236D157P2

1

H6
HOLEA@

1

3

H_S394D118P2

2

Chip_Name Label_Name

EXP_TXP0/SDVOB_RED

EXP_TXN0/SDVOB_RED#

EXP_TXP1/SDVOB_GREEN

EXP_TXN1/SDVOB_GREEN#

EXP_TXP2/SDVOB_BLUE

EXP_TXN2/SDVOB_BLUE#

EXP_TXP3/SDVOB_CLKP

EXP_TXN3/SDVOB_CLKN

EXP_RXP1/SDVO_INT

EXP_RXN1/SDVO_INT#

PCIE_MTX_C_GRX_P0

PCIE_MTX_C_GRX_N0

PCIE_MTX_C_GRX_P1

PCIE_MTX_C_GRX_N1

PCIE_MTX_C_GRX_P2

PCIE_MTX_C_GRX_N2

PCIE_MTX_C_GRX_P3

PCIE_MTX_C_GRX_N3

PCEI_GTX_C_MRX_P1

PCEI_GTX_C_MRX_N1

1

H23
HOLEA@

H_S315D118U16P2

1

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/12/1 2006/12/01

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

Screws
LA-3221P

1

32 43Friday, January 06, 2006

0.1

of

5

4

3

2

1

ADPIN

PL2

PF2

PD12

CHGRTCP

PR152

PR153

1 2

RTCVREF

12

PC74

PJP12
JUMP_43X118@

112

PJP13
JUMP_43X118@

112

PJP11
JUMP_43X118@

112

PJP8
JUMP_43X118@

112

PJP7
JUMP_43X118@

112

5

10A_65VDC_451010

12

12

G920AT24U_SOT89

3

4.7U_0805_6.3V6K~N

2

2

2

2

2

OUT

21

12

PJP6
JUMP_43X118@

2

112

PQ45

TP0610K-T1-E3_SOT23

12

PC113

0.22U_1206_25V7K

PU9

2

IN

GND

1

+5VALW

+3VALW

+1.8VALW

P-TWO_AW6044-B0D1Z

D D

C C

B B

A A

CHGRTC

4

3

2

1

PCN1

BATT+

51ON#30

PR113

1 2

560_0603_5%

+5VALWP

+3VALWP

+1.8VALWP

3.3V

PR112

1 2

560_0603_5%

RB751V_SOD323

100K_0402_5%

22K_0402_5%

FBMA-L18-453215-900LMA90T_1812

12

PC15

PC14

100P_0402_50V8J~N

1000P_0402_50V7K~N

PD11

PR143

33_1206_5%

13

2

12

PR109
200_0805_5%

12

PC72
1U_0805_25V4Z

+1.5VSP

+0.9VP

+1.2V_HTP

1 2

VIN

VIN

RLS4148_LLDS2

1 2
12

12

PC114

0.1U_0603_25V7K~N

PC30

100P_0402_50V8J~N

PD1

RLS4148_LLDS2

VS

PJP4
JUMP_43X118@

112

PJP1
JUMP_43X118@

112

PJP10
JUMP_43X118@

112

PJP9
JUMP_43X118@

112

12

12

2

2

2

2

4

VIN

Max. typ. Min.

H-->L 18.234 17.841 17.449
L-->H 17.597 17.210 16.813

PC37

2200P_0402_50V7K~N

@

12

PC31

1000P_0402_50V7K~N

ACOFF27,34

PR59

1K_1206_5%

1 2

PR55

1K_1206_5%

1 2

PR51

1K_1206_5%

1 2

PR43

1K_1206_5%

1 2

DTC115EUA_SC70

PQ7

2

12

PR24

470K_0402_5%

13

DTC115EUA_SC70

12

PR18

PQ3

TP0610K-T1-E3_SOT23

470K_0402_5%

PQ6

2

2

12

PR17
470K_0402_5%

13

13

ACIN

VIN

12

PR71

82.5K_0402_1%~N
PR72

22K_0402_1%

1 2

12

B+

12

PC40

1000P_0402_50V7K~N

12

PR75

19.6K_0402_1%~N

PC34
1000P_0402_50V7K~N

VL

12

PR68

100K_0402_1%

MAINPWON35,39

ACON34

PD2

2
3

RB715F_SOT323

1

12

PC38

0.1U_0603_25V7K~N

RTCVREF

1 2

N40N41
N35

7

O

Precharge detector
Min. typ. Max.

H-->L 14.589V 14.84V 15.243V

+1.5VS

L-->H 15.562V 15.97V 16.388V

1 2

PR70
1M_0402_1%~N

1 2

VS

8

3

+

2

-

4

PR65

10K_0402_5%

12

PR73

2.2M_0402_5%

VS

8

PU4B

P

+

-

G

LM393DR_SO8

4

PR76

34K_0402_1%

PR69

56K_0402_5%@

12

PC35

PU4A

P

1

O

G

LM393DR_SO8

12

5
6

12

12

0.01U_0402_25V7K~N

RLZ4.3B_LL34

RTCVREF

3.3V

PC41

1000P_0402_50V7K~N

12

PR77

66.5K_0402_1%

@

PD17

D

S

VIN

12

PR67
10K_0402_5%

12

12

PR79
191K_0402_1%

PRG++

RHU002N06_SOT323

PQ20

13

2

G

PR63
1K_0402_5%

1 2

PACIN

12

PR64
10K_0402_5%

PR74

499K_0402_1%

PR80
47K_0402_5%

13

B+

12

PR78
499K_0402_1%

12

12

PQ19
DTC115EUA_SC70

2

ACIN 27,35

PACIN 34

12

PC39

0.01U_0402_25V7K~N

PACIN 34

+5VALWP

BATT ONLY

+0.9V

Precharge detector
Min. typ. Max.

+1.2V_HT

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

H-->L 6.138V 6.214V 6.359V
L-->H 7.196V 7.349V 7.505V

2005/12/1 2006/12/01

3

Compal Secret Data

Deciphered Date

Title

DCIN / Precharge

Size Document Number Rev

LA-3221P 0.1

Custom

2

Date: Sheet

1

of

33 43Friday, January 06, 2006

Vin Detector

A

B

C

D

E

ACOFF 27,33

PC106

4.7U_1206_25V6K~N

E

Charger

BATT+

12

34 43Friday, January 06, 2006

BATT+

0.1

of

P2

PQ4

PQ12

AO4407L_SO8~N

8

2

13

PR149

22K_0402_5%

1 2

+3VALWP

2

7
5

PQ39

47K

47K

1 3

PQ40
DTC115EUA_SC70

12

PR5
47K_0402_5%

13

VIN

1 1

12

PQ43

2

G

ACOFF#

PACIN33

DTA144EUA_SC70

2

13

D

S

ACON33

RHU002N06_SOT323

PD13

1 2

RLS4148_LLDS2

PR150
47K_0402_5%

2 2

3 3

FSTCHG27

1
2
36

4

PR141

PQ41 RHU002N06_SOT323

2

G

2

PQ1
DTC115EUA_SC70

12

PC11

0.1U_0603_25V7K~N

12

150K_0402_5%

13

D

S

13

CP Point=2.89A
5V*(10K/(33.2k+10k))=1.157V

CS

AO4407L_SO8~N

1
2
3 6

12

PR33
200K_0402_1%

12

PC4

0.1U_0402_16V7K~N

IREF27

IREF=1.0288*Icharge
IREF=0.6V~3.21V

PQ2
DTC115EUA_SC70

4

ADP_I

12

12

PR20

33.2K_0402_1%

PR6

10K_0402_1%

12

PR147

1 2

143K_0402_1%~N

PR145

100K_0402_1%

8
7

5

PC7

0.1U_0402_16V7K~N

12

1500P_0402_50V7K~N

1000P_0402_50V7K~N

12

PC107

0.1U_0402_16V7K~N

P3

PR138

100K_0402_1%

PR140

PC98

1 2

1 2

10K_0402_5%

PR32

PC13

1 2

1 2

1K_0402_5%

PR41 10K_0402_5%

1.157V/(20*0.02)=2.89A

PR107

1 2

B+

100_0805_5%~N

+5VALW

PR108

470K_0402_5%

1 2

12

PR111

4 4

220K_0402_5%

PR110

1 2

PD7

1SS355_SOD323

220K_0402_5%

2

G

A

1 2

12

PC75

0.1U_0603_25V7K~N

PQ29

TP0610K-T1-E3_SOT23

13

2

13

D

PQ32
2N7002-7-F_SOT23-3

S

PC71

1 2

0.1U_0805_25V7M~N

B+_BIAS

12

PD6

RLZ18B_LL34-2

LI-4S :18V----BATT-OVP=1.498V
Ni-8S :16V----BATT-OVP=1.496V

B

Iadp=0~3.16A(60W)

PR19

0.015_2512_1%

4
3

1

12

FB8

FB7

10

11

12

PR50

46.4K_0603_1%

D

S

G

2

1 2

2

3

4

5

6

7

8

9

13

12

PC27

0.1U_0402_16V7K~N

B+

1
2

PU1

-INC2

OUTC2

+INE2

-INE2

FB2

VREF

FB1

-INE1

+INE1

OUTC1

OUTD

-INC1

MB3887PFV-ERE1_SSOP24

12

PQ14
2N7002-7-F_SOT23-3

FBMA-L18-453215-900LMA90T_1812

24

+INC2

23

GND

22

CS

21

VCC(o)

20

OUT

19

VH

0.1U_0603_25V7K

18

VCC

17

RT

16

-INE3

15

FB3

14

CTL

13

+INC1

1 2

200K_0603_1%

PR58

1 2

13

100K_0402_5%

PQ15
DTC115EUA_SC70

2

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

PL3

1 2

CS

PC8

1 2

1 2

PR38
68K_0402_5%~N

PR48

FB9

1 2

47K_0402_5%~N

CTL pin = 0 >
>Charger Shutdown.

PR54

VL

MH/LI# 39

BATT_OVP27

Issued Date

0.1U_0603_25V7K

1500P_0402_50V7K~N

1

C

Fosc=14100/Rt=14100/47=300KHz

12

0.1U_0603_25V7K~N

12

12

Deciphered Date

12

PC22

2200P_0402_50V7K~N

PD10

EC31QS04

13

D

S

578

12

12

12

PC12

PC23

4.7U_1206_25V6K~N

PC2

0.022U_0402_16V7K~N

1 2

PC5

1 2

0.1U_0603_25V7K

PC10

1 2

PC16

1 2

ACON 33

4.2V

PC17

4.7U_1206_25V6K~N

PR7

0_0603_5%~N

4.7U_1206_25V6K~N

12

HG7DH7

PC18

PR53

113K_0603_1%

BATT+

12

PR37
340K_0402_1%

0.01U_0402_25V7K~N

12

PR44

499K_0402_1%

PR182

634K_0402_1%

12

PR52

86.6K_0402_1%

Compal Secret Data

VS

12

PC32

8

PU3A

3

P

+

0

2

-

G

LM358ADR_SO8

4

2005/12/1 2006/12/01

CHG_B+

36

241

PQ5
AO4407L_SO8~N

LXCHRG

12

1 2

PQ50
2N7002-7-F_SOT23-3

2

G

PL8

10U_LF919AS-100M-P3_4.5A_20%

1 2

12

PD9

EC31QS04

8

PU3B

P

+

7

0

-

G

LM358ADR_SO8

4

PC26

0.01U_0402_25V7K~N

D

5
6

13

PR183

1 2

100K_0402_5%

2

PQ49

DTC115EUA_SC70

PQ9

1
2
3 6

PR142

4
3

0.02_2512_1%

AO4407L_SO8~N

PR47

10K_0402_1%

1
2

4

1 2

13

8
7

5

PR46

47K_0402_1%

1 2

ACOFF#

PQ13
DTC115EUA_SC70

ACOFF

2

12

PC96

4.7U_1206_25V6K~N

VIN

12

PC95

4.7U_1206_25V6K~N

Charge voltage
4S CC-CV MODE : 16.8V(Li-Ion)
8S CC-CV MODE : 14.4V(Ni-MH)

VL

MH/LI# 39

Title

Size Document Number Rev

B

Date: Sheet

Compal Electronics, Inc.

PWR-Charger

5

4

3

2

1

+3.3VALWP/+5VALWP

12

PC87

4.7U_1206_25V6K~N
2200P_0402_50V7K~N

12

PL15

MAINPWON33,39

B+++

12

VS

12

PD16

RLZ5.1B_LL34

1 2

47K_0402_5%

D8D7D6D

S1S2S3G

D8D7D6D

S1S2S3G

PR176

5

PQ34

SI4800BDY-T1-E3_SO8

4

5

PQ35
SI4810BDY-T1-E3_SO8

4

DL_5V

12

PR175

100K_0402_5%

0_0402_5%

PR127

0_0603_5%~N

1 2

12

PC132

PR174

12

0.047U_0603_16V7K~N

1U_1206_25V7K @

PC131

PR128

1 2

0_0805_5%@

DH_5V

PC82

0.1U_0603_25V7K~N

ACIN27,33

VL

12

PR179

806K_0603_1%

12

12

10K_0402_5%

PQ48

1 2

RHU002N06_SOT323

DAP202U_SOT323

PR126

0_0805_5%

VL

12

PC81

4.7U_0805_6.3V6K~N

PR125 0_0603_5%~N

LX_5V

PR181

2VREF_8734

@

13

D

2

G

S

+LDO5

12

BST_5V

12

FB5

PC78

LDO3P

@

PQ33

PD8

14
16
15

19
21

9
1

6
4
3

12

8

12

0.22U_0603_16V7K~N

PR130
100K_0402_5%

@

1 2

13

D

S

2

1

PC80

4.7U_1206_25V6K~N

PU10

BST5
DH5
LX5

DL5
OUT5
FB5
N.C.

SHDN#
ON5
ON3

SKIP#
REF

ACIN

2

G

3

PR122

12

18

B+++

12

0_1206_5%

20

V+

LD05

GND

23

@

D

S

PQ36

VL

1 2

PC79

12

0.1U_0603_25V7K~N

13

17

ILIM3

TON

VCC

ILIM5
BST3

OUT3

PGOOD

PRO#

LDO3

10

25

LDO3P

12

PC77

4.7U_0805_6.3V6K~N

13

2

G

12

PC84

PR129

DH3

DL3
LX3

FB3

0.1U_0402_16V7K~N

PC83

1 2

5

11
28

26
24
27
22

7
2

1 2

@

1U_0603_10V6K

ILIM3

ILIM5

FB3

PR180

0_0402_5%

1 2

PR117
0_0805_5%

47_0402_5%

MAX8734AEEI+_QSOP28

EC_ON 27,30

2VREF_8734

PR118

1 2

45.3K_0402_1%

PR119

1 2

499K_0402_1%

BST_3V
DH_3V

PR178

1 2

40.2K_0402_1%

PR177

1 2

499K_0402_1%

PR115

0_0603_5%~N

+LDO3

PR116

1 2

0_0805_5%@

0.1U_0603_25V7K~N

12

LX_3V

PC76

B+++

12

PC73

4.7U_1206_25V6K~N

0_0603_5%~N

12

12

PC70

4.7U_1206_25V6K~N

PR114

12

PC69

2200P_0402_50V7K~N

1 2

DL_3V

LX_3V

1 2

1 2

5

4

5

4

PR120

3.57K_0402_1%@

PR121

0_0402_5%

PQ30

D8D7D6D

SI4800BDY-T1-E3_SO8

S1S2S3G

D8D7D6D

PQ31

S1S2S3G

SI4810BDY-T1-E3_SO8

12

PL14

1

+

2

PC129

4.7UH_SIL104R-4R7PF_5.7A_30%

+3VALWP

150U_V_6.3VM_R18

PL5

D D

B+

FBMA-L18-453215-900LMA90T_1812

C C

B B

PF4

10A_65VDC_451010

2 1

12

4.7UH_SIL104R-4R7PF_5.7A_30%

+5VALWP

1

+

PC133

2

150U_V_6.3VM_R18

12

PC85

4.7U_1206_25V6K~N

PR124

1 2

PR123

1 2

PC86

10.2K_0402_1%@

0_0402_5%

RHU002N06_SOT323

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

RHU002N06_SOT323

2005/12/1 2006/12/01

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

2

Date: Sheet

+5V/+3V

LA-3221P

Friday, January 06, 2006

1

35 43

of

0.1

5

4

3

2

1

D D

12

PC64

4.7U_1206_25V6K~N

1

2

3

BST_1.2V-2

1 2

12

PR99

PC59

0_0603_5%~N

0.1U_0603_25V7K~N

LX_1.2V

PR101

1.15K_0402_1%

1 2

VSE_1.2V

12

PC62

12

PC67

@

4.7U_1206_25V6K~N

12

PC128

12

0.01U_0402_25V7K~N

BST_1.2V-1

DH_1.2VDH_1.5V

ISE_1.2V
DL_1.2V

12

PR171
110K_0402_1%

PC58

2.2U_0805_10V6K

PU8

12

SOFT1

6

BOOT1

5

UGATE1

4

PHASE1

7

ISEN1

2

LGATE1

3

PGND1

9

VOUT1

10

VSEN1

8

EN1

15

PG1

11

OCSET1

PR106

+5VALWP

1 2

10_0805_5%

12

PC66

0.1U_0603_25V7K~N

14

1

PR162

1 2

2.2_0603_5%

28

VIN

GND

SOFT2

VCC

BOOT2

UGATE2
PHASE2

ISEN2

LGATE2

PGND2

VOUT2
VSEN2

EN2

PG2/REF

OCSET2

DDR

ISL6227CAZ-T_SSOP28

13

12

PC61

0.1U_0603_25V7K~N

RB717F_SOT323-3

VOUT_1.2V

PR103

1 2

0_0402_5%

PD5

RB751V_SOD323 @

1 2

0.1U_0402_16V7K~N@

PD4

PQ28

SI4800BDY-T1-E3_SO8

+1.2V_HTP

1

C C

B B

+

2

PC125

220U_D2_4VM_R15

PR165

7.32K_0402_1%~N

12

12

12

PR168

10K_0402_1%

1.8UH_SIL104R-1R8PF_9.5A_30%

PC123

0.01U_0402_25V7K~N

1 2

AO4704L_SO8~N

12

PR164
0_0402_5%

12

PR169

0_0402_5% @

PL13

PQ26

5

D8D7D6D

S1S2S3G

4

578

3 6

241

VLDT_EN27,30,40

12

PC121

BST_1.8V-2

PC127

17

12

0.01U_0402_25V7K~N

BST_1.8V-1

23

1 2

PR100

0_0603_5%~N

DH_1.8V

24

LX_1.8V

25

ISE_1.8V

22

DL_1.8V

27

26

VOUT_1.8V

20

VSE_1.8V

19
21
16

18

12

PR170
121K_0402_1%

B++++

12

PC65

@

2.2U_0805_10V6K

0.1U_0603_25V7K~N

PR102

1.65K_0402_1%

1 2

4.7U_1206_25V6K~N

12

FBMA-L11-322513-151LMA50T_1210

12

PC60

PC63

4.7U_1206_25V6K~N

5

4

12

578

3 6

1 2

PR172 10K_0402_5%

1 2

PR167
10K_0402_5%

@

PC126

0.1U_0402_16V7K~N@

12

241

PL6

12

PC68

0.1U_0603_25V7K~N

D8D7D6D

PQ27

SI4800BDY-T1-E3_SO8

S1S2S3G

PL12

1.8UH_SIL104R-1R8PF_9.5A_30%

1 2

PQ25
AO4704L_SO8~N

0_0402_5%

+3VALWP

+5VALWP

0_0402_5% @

PR104

PR105

PF5

2 1

7A_24VDC_429007.WRML

12

12

PC122

0.01U_0402_25V7K~N

12

12

PR163

0.9V0.9V

12

PR166

B+

PC124

10.2K_0402_1%

10K_0402_1%

+1.8VALWP

1

+

2

220U_D2_4VM_R15

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/12/1 2006/12/01

Compal Secret Data

Deciphered Date

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

+1.2V_HTP & +1.8VALWP

Friday, January 06, 2006

1

36 43

0.1

of

5

4

3

2

1

+1.5VSP/+0.9VSP

+1.8VALW

D D

10U_1206_25V6M~N

PR88

0_0402_5%

SYSON#6,31

C C

1 2

0.1U_0402_16V7K~N @

PC49

PC54

PQ22

2N7002-7-F_SOT23-3

12

1

PJP2

1

JUMP_43X118@

2

2

1.8V_0.9V

12

13

D

2

G

S

PR94

1K_0402_1%

PR95

12

12

1K_0402_1%

12

PC50

0.1U_0402_16V7K~N

PU6

VIN1VCNTL

2

GND

3

VREF

4

VOUT

APL5331KAC-TRL_SO8~N

+0.9VP

12

PC48
22U_1206_6.3V6M~N

6
5

NC

7

NC

8

NC

9

TP

+3VALWP

12

PC47
1U_0603_6.3V6M~N

10U_1206_25V6M~N

PR132

0_0402_5%

SUSP29,31

1 2

0.1U_0402_16V7K~N @

PC91

PC88

+1.8VALW

1

PJP3

1

2

2

12

PQ37

13

D

2N7002-7-F_SOT23-3

2

G

S

12

JUMP_43X118@

PR133

1K_0402_1%

PR131

1.8V_1.5V

12

12

1K_0402_1%

12

PC89

0.1U_0402_16V7K~N

PU11

VIN1VCNTL

2

GND

3

VREF

4

VOUT

APL5331KAC-TRL_SO8~N

+1.5VSP

12

PC90
10U_1206_25V6M~N

6
5

NC

7

NC

8

NC

9

TP

+3VALWP

12

PC92
1U_0603_6.3V6M~N

B B

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/12/1 2006/12/01

Compal Secret Data

Deciphered Date

Title

+1.5VSP/+0.9VP

Size Document Number Rev

LA-3221P 0.1

Custom

2

Date: Sheet

1

of

37 43Friday, January 06, 2006

5

4

3

2

1

+CPU_CORE

12

@

10_0402_5%

12

38 43Friday, January 06, 2006

of

B+

PR3

0_0402_5%
PR1

0.1

+5VS

+3VS

12

D D

VID06
VID16
VID26
VID36
VID46
VID56

VGATE27

+3VS

C C

VR_ON27

PR28

0_0402_5%

1 2

1 2

EC_ADC27

1 2

PC1

0.1U_0402_16V7K~N

REF

1 2

PR13

31.6K_0402_1%

169K_0603_1%

B B

CPU_PSI#6

A A

AGND

PR14

PQ38

2

G

2

G

PR144

0_0402_5%

1 2

CPU_B+

200K_0402_1%

13

D

S

PR40 0_0402_5%
PR39 0_0402_5%

PR36 0_0402_5%
PR35 0_0402_5%

PR31 0_0402_5%
PR30 0_0402_5%
PR8 0_0402_5%@

1 2

PR42 100K_0402_1%

PR27

@

100K_0402_5%

PR12 10K_0402_1%

1 2

PR11

1 2

200K_0402_1%

12

13

D

RHU002N06_SOT323

S

12

PR23

200K_0402_1%

PQ10
RHU002N06_SOT323

1 2

PR22

PQ8

2

G

12

PR15

10K_0402_5%

@

12
12

12
12
12
12

TP AGND

PR139 71.5K_0402_1%

1 2

PC97 0.1U_0603_25V7K~N

+3VS

12

13

D

RHU002N06_SOT323

S

PR146 10_0402_5%

PC108

2.2U_0603_10V6K

1 2

VCC

J1 SHORT PADS

1 2

For EC ATE

VCC

12

PC99

150P_0402_50V8J

0_0402_5%

PR21

12

REF

12

PU2

19

VCC

31

D0

32

D1

33

D2

34

D3

35

D4

36

D5

1

PWRGD

17

PHASEGD

37

TWO-PH

38

SHDN#

6

TIME

8

CCV

3

POUT

10

REF

7

TON

2

OFS

4

VRHOT#

39

SKIP#

EP

41

4700P_0603_50V7K~N

10_0402_5%

PC102

PR25

@

PC110

1 2

2.2U_0603_6.3V6K~N

25

VDD

5

THRM

30

BST1

29

DH1

28

LX1

26

DL1

27

PGND1

16

CSP1

15

CSN1

18

GND

40

IC

FB

11

FB

9

CCI

20

BST2

21

DH2

22

LX2

24

DL2

23

PGND2

13

CSP2

14

CSN2

GNDS

12

MAX8774GTL+_TQFN40

12

12

12

CPU_VDD_FB_L6

0_0603_5%~N

1 2

DH1
LX1
DL1

PGND1

PR16

2.55K_0603_1%

1 2

1 2

PC3 470P_0402_50V8J~N

DH2
LX2
DL2
PGND2
CSP2

PR26
100_0402_1%

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

12

PC104

0.01U_0402_25V7K~N

12

PR45

PC19

0.22U_0603_16V7K~N

PC94

4700P_0402_25V7K

1 2

1 2

PR49

1 2

PR4 20K_0402_1%

1 2

PR148

0_0603_5%~N

1 2

PR2

0_0603_5%~N

12

PC25

@

4700P_0402_25V7K

100_0402_1%

12

1 2

0.22U_0603_16V7K~N

4700P_0402_25V7K

PR151
0_0603_5%~N

PC24

@

PC20

1 2

2005/12/1 2006/12/01

3

Compal Secret Data

Deciphered Date

CPU_B+

3 5

241

5

D8D7D6D

PQ16

S1S2S3G

4

PR34 0_0402_5%

1 2

3 5

241

5

PQ18

4

FDS6676AS_SO8

PR29

1 2

0_0402_5%

12

PC109

PQ42
SI7840DP-T1-E3_SO8

5

D8D7D6D

PQ11

S1S2S3G

4

FDS6676AS_SO8

PQ44
SI7840DP-T1-E3_SO8

5

D8D7D6D

S1S2S3G

PQ17

D8D7D6D

S1S2S3G

4

FDS6676AS_SO8

12

12

PC105

4.7U_1206_25V6K~N

4.7U_1206_25V6K~N

PR62

@

1 2

4.7_1206_5%~N

12

FDS6676AS_SO8

PC33

@

680P_0603_50V8J

CPU_B+

12

PC9

PR66

@

4.7_1206_5%~N

PC36

@

680P_0603_50V8J

2

FBMA-L18-453215-900LMA90T_1812

PC112

PL7

1 2

12

PC111

0.01U_0402_25V7K~N

2200P_0402_50V7K~N

0.36UH_PCMC104T-R36MN1R17_30A_20%

1 2

12

PD15

PR57

2 1

SKS30-04AT_TSMA

4.22K_0402_1%

PR61

2.1K_0402_1%

1 2

8A_125V_451008MRL

PL10

10KB_0603_ERTJ1VR103J

1 2

1 2

PC29

0.22U_0603_16V7K~N

12

PC100

PC101

4.7U_1206_25V6K~N

4.7U_1206_25V6K~N

12

PC103

0.01U_0402_25V7K~N

12

2200P_0402_50V7K~N

1 2

PR56

4.22K_0402_1%

PD14

1 2

12

1 2

2 1

Title

Size Document Number Rev

Custom
Date: Sheet

PR60

2.1K_0402_1%

1 2

SKS30-04AT_TSMA

0.22U_0603_16V7K~N

CSP2

PF6

2 1

1

+

PC93

2

220U_25V_M~N

PH3

CPU_VDD_FB_H6

PL9

0.36UH_PCMC104T-R36MN1R17_30A_20%

PH2
10KB_0603_ERTJ1VR103J

1 2

PC28

1 2

+CPU_CORE

HCW51 LA-3121P

1

5

4

3

2

1

D D

C C

B B

BATT+

PL1

FBMA-L18-453215-900LMA90T_1812

BATT+

1 2

12

PC21

0.01U_0402_25V7K~N

PJPB1 battery connector

SMART
Battery:

1.BAT+

2.BAT+

3.ID

4.B/I

5.TS

6.SMD

7.SMC

8.GND

9.GND

12

PC6
1000P_0402_50V7K~N

SUYIN_200275MR009G154ZL_RV

10

GND

11

GND

BATT++

PJP5

BATT+
BATT+

SMD

SMC
GND­GND-

BATT++

21

PF1
15A_65VDC_451015

1
2
3

ID

4

B/I

5

TS

6
7
8
9

MH/LI#

+3VALWP

1 2

1 2

PR10

100_0402_5%

1 2

PR9

100_0402_5%

PR136
47K_0402_5%~N

PR137

1K_0402_5%

12

MH/LI# 34

AMH/LI#

PR135

1K_0402_5%

EC_SMB_DA1 27,28

EC_SMB_CK1 27,28

12

Place clsoe to EC pin

BATT_TEMP

1 2

PR173

1K_0402_5%

1 2

1 2

PR134

6.49K_0402_1%

PC130

0.1U_0402_16V7K~N

@

CPU

12

PC43

0.22U_0603_16V7K~N

BATT_TEMP 27

CPU

+3VALWP

PH1 under CPU botten side :

CPU thermal protection at 90 +-3 degree C
Recovery at 50 +-3 degree C

VL VS

12

PR86
0_0402_5%

PR83

200K_0402_1%

1 2

VL

PC45

0.1U_0402_16V7K~N@

1 2

PR84

100K_0402_1%

100K_0402_1%

PR85

1 2

12

12

PH1
100K_0603_1%_TH11-4H104FT

12

12

PR87
20K_0402_1%

PR82

499K_0402_1%

12

PC42
1000P_0402_50V7K~N

8

3

+

2

-

4

Battery Connect/OTP

PC115

0.1U_0603_25V7K~N

1 2

VL

PR81
499K_0402_1%

PU5A

P

G

LM393DR_SO8

1 2

1

O

MAINPWON33,35

13

D

2

G

PQ21

S

RHU002N06_SOT323

5
6

8

P

+

-

G

4

PU5B

7

O

LM393DR_SO8

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/12/1 2006/12/01

Compal Secret Data

Deciphered Date

Title

BATTERY CONN

Size Document Number Rev

LA-3221P 0.1

Custom

2

Date: Sheet

1

of

39 43Friday, January 06, 2006

5

D D

PL4

FBMA-L18-453215-900LMA90T_1812

PF3

2 1

B+

7A_24VDC_429007.WRML

C C

B B

VLDT_EN27,30,36

1 2

NB_RST#11,15,20,23,26,27

12

PC56

10U_1206_25V6M~N

12

4

12

6269_VCC

12

2.2U_0603_6.3V6K~N

PC117

0.1U_0402_16V7K~N

2

PC57

10U_1206_25V6M~N

0.01U_0603_50V7K~N@

PC116

+5V

PQ47

TP0610K-T1-E3_SOT23

PR89

0_0603_5%~N

1 2

PC46

12

PR156

1 2

0_0402_5%

12

PC53

3

+5VS

17

PU7

GND

1

VIN

2

VCC

3

4

2

G

FCCM

EN

COMP5FB6FSET

12

PR91

49.9K_0402_1%

12

PC52
6800P_0402_25V7K~N

PR157

49.9K_0402_1%

1 2
13

D

PQ46
2N7002-7-F_SOT23-3

S

22P_0402_50V8J

PR90
10K_0402_5%

1 2

16

PGOOD

57.6K_0402_1%

15

PHASE

PR161

12

PHASE_VCCPP

14

UG

7

12

PR159
3K_0402_1%

PR93

1 2

2.2_0603_5%

BOOT_VCCPP

13

BOOT

12

PVCC

11

LG

10

PGND

9

ISEN

VO

8

12

PC119

0.01U_0402_25V7K~N

UG_VCCPP

1 2

PC51 0.1U_0603_25V7K~N

12

PR155

4.7_0603_5%

@

PR154

1 2

4.7_0603_5%

1 2

2.2U_0603_6.3V6K~N

LG_VCCPP

ISEN_VCCPP

1 2

8.66K_0402_1%

ISL6269CRZ-T_QFN16

PR92

1 2

2.26K_0402_1%

PR96

+5VS

6269_VCC

PC55

10K_0402_5%@

PR97

2

5

4

PR98
10K_0402_5%

@

1 2

5

4

1 2

PQ23

D8D7D6D

SI4800BDY-T1-E3_SO8

S1S2S3G

PL11
1UH_SIL1035-1R0PF_9A_20%

1 2

PQ24

D8D7D6D

SI4810BDY-T1-E3_SO8

S1S2S3G

1

+RS480_COREP

1

+

PC120

220U_D2_4VM_R15

2

1 3

PR158

4

PR160
100K_0402_5%

1 2

10K_0402_5%

12

12

PC118
1000P_0402_50V7K~N

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/12/1 2006/12/01

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

RS480_CoreP

LA-3221P

Friday, January 06, 2006

of

1

40 43

0.1

PD3

STRAP_DATA16

A A

5

12

RB751V_SOD323

5

4

3

2

1

Version Change List ( P. I. R. List )

Page 1

Request

Item Issue DescriptionDate

1

D D

2

3

4

5

6

C C

7

8

10

Owner

Solution Description Rev.Page# Title

11

12

13

B B

14

15

16

17

A A

Compal Electronics, Inc.

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

Next: PR238, PC202, PQ56, PD42, PJP21

5

4

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

EE-PIR

Size Document Number Rev

LA-3221P

Date: Sheet

Friday, January 06, 2006 4341

1

of

0.1

5

4

3

2

1

Version change list (P.I.R. List) Page 1 of 1 for HW

Reason for change Rev. PG# Modify List VER PhaseFixed IssueItem

1

D D

CPU bypass Cap change to Proadlizer 1200uF. 7

2

3

4

C C

5

6

7

8

Change Felica connector package. 28

Change R536 value.

24 R536 change to 10K ohm

Change net (WLAN_ACT) from pin 3 to pin46.

RS485MC only support 2 lane PCI-E A-LINK 4X---->2X

10,15

Part reference rename for layout All Part reference change

To support WOL on S3/S4/S5 23

Change R185 BOM structure 23

From 4pin change to 6 pin.

Add R516, R53826

Change PCI-E port 2,3 ---->0,1

Change the power rail from +3V to +3VALW.

9

B B

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/12/1 2006/12/01

Compal Secret Data

Deciphered Date

Title

PIR (HW)

Size Document Number Rev

Custom

LA-3221P

2

Date: Sheet

1

42 43Friday, January 06, 2006

0.1

of

ACIN

5

4

3

2

1

+5/3/1.8VALW

ON/OFF#

D D

32ms

8.5/2.44/3.792ms

t<=10 ms

EC_ON

t=100 ms

PWRBTN_OUT#

438ms

364us

t=109 ms

SYSON

+5/3/1.8V

<1ms

EC_RSMRST#

C C

SLP_S3/S5#

<10ms

200ns

92.88ms

SUSP#
+5/3/1.8VS

1.25VS(104us) 1.5VS(2.64ms) 3VS(7.044ms) 5VS(10.26ms) 2.5VS(4.966ms)

t>0

+RS480_COREP

*VR_ON/VLDT_EN

*+CPU_CORE/+1.2V_HT

B B

NB_PWRGD

SB_PWRGD

15ms

rising time <15ns

SB_SSMUXSEL(LDT_PG)

t<100 us

>48ms

KB_RST#

A_RST#

PCI_RST#

A A

>51ms

LDT_RST#

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2005/03/11 2006/03/11

3

Compal Secret Data

Deciphered Date

80ns

2ms

Compal Electronics, Inc.

Title

Size Document Number Rev

2

Date: Sheet

Power Sequence

Friday, January 06, 2006

LA-3221

1

of

43 43

0.1