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LA-3221P
Schematics
43 pgs1.17 Mb0

COMPAL LA-3221P Schematics

A
1 1
B
C
D
E
2 2
Compal Confidential
Schematics Document
AMD/S1/ATI RS485M(C)/SB460
2005 / 12 / 30
3 3
Rev:0.1
4 4
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2005/12/1 2006/12/01
Deciphered Date
Title
Cover Sheet
Size Document Number Rev
Custom
LA-3221P
D
Date: Sheet
E
143Friday, January 06, 2006
0.1
of
A
B
C
D
E
Compal confidential
Project Code: ANRHAL5000(HAL50) File Name : LA-3221P
1 1
Thermal Sensor ADM1032ARM
page 4 page 13
Clock Generator ICS951462
CRT
page 14
AMD S1 CPU
page 4,5,6,7
HT 16x16 800MHZ
ATI-RS485M(C)
DDR-2 DDR2-SO-DIMM X2
page 8,9
Daul Channel DDR-2
LCD CONN
page 14
PCI EXPRESS
2 2
Realtek
RTL8111B
page 23
Mini Card
page 26
RJ45 CONN
page 23
PCI BUS
Mini PCI Socket
page 26
3 3
CradBus Controller
R5C841 or R5C811
Slot 0
page 22
Meadia Card
page 22
page 21,22
1394 Conn.
page 21
LPC BUS
BGA465
page 10,11,12
A-Link Express
2 x PCIE
ATI-SB460
BGA549
page 15,16,17,18
USB 2.0
USB 2.0
HD-Interface
SATA
PATA
USB conn x 4
page 29
Felica Conn
page 28
Audio CKT ALC262
page 24
MDC Conn.
page 24
AMP & Audio Jack
RJ11 CONN
page 27
SATA HDD Conn.
page 20
HDD Conn. CDROM Conn.
page 20
page 25
Power On/Off CKT.
page 31
ENE KB910L
DC/DC Interface CKT.
page 33
Power Circuit DC/DC
page 33~41
4 4
RTC CKT.
page 15
Power OK CKT.
page 30
Touch Pad CONN.
page 28
page 27
Int. KBD
page 28
BIOS
page 28
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2005/12/1 2006/12/01
Deciphered Date
Title
Block Diagrams
Size Document Number Rev
Custom
LA-3221P
D
Date: Sheet
E
243Friday, January 06, 2006
0.1
of
A
Voltage Rails
Power Plane Description
VIN
1 1
2 2
B+ +CPU_CORE +1.2V_HT +0.9V 0.9V switched power rail for DDR terminator +1.8VALW 1.8V always on power rail +1.5VS +1.8VS 1.8V switched power rail +1.8V +3VALW +3V +3VS +5VALW +5VS +RTCVCC RTC power
Adapter power supply (19V) AC or battery power rail for power circuit. Core voltage for CPU
1.2V switched power rail
1.5V switched power rail
1.8V power rail for DDR
3.3V always on power rail
3.3V power rail
3.3V switched power rail 5V always on power rail 5V switched power rail
B
S1 S3 S4/ S5
ON ON ON
ON OFF ON OFF ON OFF ON ON OFF OFF ON OFF OFF ON ON ON ON ON
ON ONON
ONONON OFF OFF
ON
ONON
OFF
ON ON ON
OFF
ON
OFF
OFF ON
ON OFFON
OFF
C
SIGNAL
STATE
Full ON
S1(Power On Suspend)
S3 (Suspend to RAM)
SLP_S1# SLP_S3#
HIGH HIGH HIGH HIGH
LOW
LOW
LOW
S4 (Suspend to Disk)
S5 (Soft OFF)
LOW LOW LOW LOW
Board ID Table for AD channel
Vcc 3.3V +/- 5%
Board ID
0 1 2 3 4 5 6 7 NC
100K +/- 5%Ra / Rc
Rb / Rd V min
0
8.2K +/- 5% 18K +/- 5% 33K +/- 5% 56K +/- 5% 100K +/- 5% 200K +/- 5%
AD_BID
0 V
0.216 V 0.250 V 0.289 V
0.436 V
0.712 V
1.036 V
1.453 V 1.650 V 1.759 V
1.935 V
2.500 V
D
SLP_S4# SLP_S5# +VALW +V +VS Clock
ON
ON
ON
OFF
OFF
V
AD_BID
ON ON
ON
OFF
OFF
OFF
max
LOW
OFF
OFF
OFF
HIGH
LOWLOWLOW
HIGHHIGHHIGH
HIGH
HIGH
V typ
AD_BID
ON
ON
ON
ON
ON
0 V 0 V
0.503 V
0.819 V
0.538 V
0.875 V
1.185 V 1.264 V
2.200 V
3.300 V
2.341 V
3.300 V
E
External PCI Devices
Device IDSEL# REQ#/GNT# Interrupts
CardBus Mini-PCI
AD21 AD22
0 1
PIRQE/PIRQF/PIRQG PIRQF/PIRQG
BOARD ID Table
Board ID
0 1 2
PCB Revision
0.1
BTO Item BOM Structure
BTO Option Table
3 4 5 6 7
EC SM Bus1 address
3 3
Device
Smart Battery EEPROM(24C16/02)
(24C04)
Address Address
1010 000X b? 1011 000Xb?
EC SM Bus2 address
Device
ADM1032
1001 110X b?0001 011X b?
SB460 SM Bus address
Device
Clock Generator (ICS 951462AGT)
DDRII DIMM0 DDRII DIMM2
4 4
Address
1101 001Xb?
1001 000Xb? 1001 010Xb?
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2005/12/1 2006/12/01
Deciphered Date
Title
Notes
Size Document Number Rev
Custom
LA-3221P
D
Date: Sheet
E
343Friday, January 06, 2006
0.1
of
5
4
3
2
1
H_CADIP[0..15]10
H_CADIP[0..15] H_CADIN[0..15]
H_CADOP[0..15] H_CADON[0..15]
H_CADOP[0..15] 10 H_CADON[0..15] 10H_CADIN[0..15]10
PROCESSOR HYPERTRANSPORT INTERFACE
D D
C C
+1.2V_HT
AMD : 49.9 1%
B B
ATI : 51 1%
R226 49.9_0402_1% R225 49.9_0402_1%
VLDT_Ax AND VLDT_Bx ARE CONNECTED TO THE LDT_RUN POWER SUPPLY THROUGH THE PACKAGE OR ON THE DIE. IT IS ONLY CONNECTED ON THE BOARD TO DECOUPLING NEAR THE CPU PACKAGE
H_CLKIP110 H_CLKIN110 H_CLKIP010 H_CLKIN010
1 2 1 2
H_CTLIP010 H_CTLIN010
+1.2V_HT B+_BIAS
D4
VLDT_A3
D3
VLDT_A2
D2
VLDT_A1
D1
VLDT_A0
H_CADIP15
N5
P5 M3 M4
L5 M5
K3
K4 H3 H4 G5 H5
F3
F4
E5
F5 N3 N2
L1 M1
L3
L2
J1
K1 G1 H1 G3 G2
E1
F1
E3
E2
J5
K5
J3
J2
P3
P4 N1
P1
+1.2V_HT
L0_CADIN_H15 L0_CADIN_L15 L0_CADIN_H14 L0_CADIN_L14 L0_CADIN_H13 L0_CADIN_L13 L0_CADIN_H12 L0_CADIN_L12 L0_CADIN_H11 L0_CADIN_L11 L0_CADIN_H10 L0_CADIN_L10 L0_CADIN_H9 L0_CADIN_L9 L0_CADIN_H8 L0_CADIN_L8 L0_CADIN_H7 L0_CADIN_L7 L0_CADIN_H6 L0_CADIN_L6 L0_CADIN_H5 L0_CADIN_L5 L0_CADIN_H4 L0_CADIN_L4 L0_CADIN_H3 L0_CADIN_L3 L0_CADIN_H2 L0_CADIN_L2 L0_CADIN_H1 L0_CADIN_L1 L0_CADIN_H0 L0_CADIN_L0
L0_CLKIN_H1 L0_CLKIN_L1 L0_CLKIN_H0 L0_CLKIN_L0
L0_CTLIN_H1 L0_CTLIN_L1
L0_CTLIN_H0 L0_CTLIN_L0
H_CADIN15 H_CADIP14 H_CADIN14 H_CADIP13 H_CADIN13 H_CADIP12 H_CADIN12 H_CADIP11 H_CADIN11 H_CADIP10 H_CADIN10 H_CADIP9 H_CADIN9 H_CADIP8 H_CADIN8 H_CADIP7 H_CADIN7 H_CADIP6 H_CADIN6 H_CADIP5 H_CADIN5 H_CADIP4 H_CADIN4 H_CADIP3 H_CADIN3 H_CADIP2 H_CADIN2 H_CADIP1 H_CADIN1 H_CADIP0 H_CADIN0
H_CLKIP1 H_CLKIN1 H_CLKIP0 H_CLKIN0
H_CTLIP0 H_CTLIN0
CPU1A
VLDT_B3 VLDT_B2 VLDT_B1 VLDT_B0
L0_CADOUT_H15 L0_CADOUT_L15 L0_CADOUT_H14 L0_CADOUT_L14 L0_CADOUT_H13 L0_CADOUT_L13 L0_CADOUT_H12 L0_CADOUT_L12 L0_CADOUT_H11 L0_CADOUT_L11 L0_CADOUT_H10 L0_CADOUT_L10
L0_CADOUT_H9 L0_CADOUT_L9 L0_CADOUT_H8 L0_CADOUT_L8 L0_CADOUT_H7 L0_CADOUT_L7 L0_CADOUT_H6 L0_CADOUT_L6 L0_CADOUT_H5 L0_CADOUT_L5 L0_CADOUT_H4 L0_CADOUT_L4 L0_CADOUT_H3 L0_CADOUT_L3 L0_CADOUT_H2 L0_CADOUT_L2 L0_CADOUT_H1 L0_CADOUT_L1 L0_CADOUT_H0
HTT Interface
L0_CADOUT_L0 L0_CLKOUT_H1
L0_CLKOUT_L1
L0_CLKOUT_H0
L0_CLKOUT_L0
L0_CTLOUT_H1 L0_CTLOUT_L1
L0_CTLOUT_H0 L0_CTLOUT_L0
Athlon 64 S1 Processor Socket
AE5 AE4 AE3 AE2
T4 T3 V5 U5 V4 V3 Y5 W5 AB5 AA5 AB4 AB3 AD5 AC5 AD4 AD3 T1 R1 U2 U3 V1 U1 W2 W3 AA2 AA3 AB1 AA1 AC2 AC3 AD1 AC1
Y4 Y3 Y1 W1
T5 R5
R2 R3
H_CADOP15 H_CADON15 H_CADOP14 H_CADON14 H_CADOP13 H_CADON13 H_CADOP12 H_CADON12 H_CADOP11 H_CADON11 H_CADOP10 H_CADON10 H_CADOP9 H_CADON9 H_CADOP8 H_CADON8 H_CADOP7 H_CADON7 H_CADOP6 H_CADON6 H_CADOP5 H_CADON5 H_CADOP4 H_CADON4 H_CADOP3 H_CADON3 H_CADOP2 H_CADON2 H_CADOP1 H_CADON1 H_CADOP0 H_CADON0
H_CLKOP1 H_CLKON1 H_CLKOP0 H_CLKON0
H_CTLOP0 H_CTLON0
1 2
C341 4.7U_0805_6.3V6K
H_CLKOP1 10 H_CLKON1 10 H_CLKOP0 10 H_CLKON0 10
H_CTLOP0 10 H_CTLON0 10
+5VS
12
1
C104
2
1U_0603_10V4Z
R28
100K_0402_5%
EN_DFAN127
1 2
FAN1VREF
3
+IN
2
FAN1_VFB
1
C94
2
1U_0603_10V4Z
R31
1 2
150K_0402_5%
-IN
C99
2200P_0402_50V7K
1 2
R29
100K_0402_5%
8
U4A
P
1
OUT
G
4
LM358DR2G_SO8~N
12
FAN1_ON
D7
RB751V_SOD323
2 1
R230 0_0805_5%
6
2
1
D
Q31
G
3
S
SI3456DV-T1_TSOP6
4 5
FAN1_POWER
1
1
2
C100
2
C96
22U_1206_10V4Z
1000P_0402_50V7K~N
FAN1 Control and Tachometer
+3VS
12
R231
10K_0402_5%
2
1
FAN_SPEED1 27
C607
0.01U_0402_16V7K
JFAN1
1 2 3
4
G
5
G
MOLEX_53398-0371~N
FAN1
1
1
C3734.7U_0805_6.3V6K
C3774.7U_0805_6.3V6K
2
2
A A
5
1
1
1
1
C3720.22U_0603_10V7K
C3760.22U_0603_10V7K
2
C374
C375
2
2
2
180P_0402_50V8J~N
180P_0402_50V8J~N
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2005/12/1 2006/12/01
Deciphered Date
Title
Size Document Number Rev
Custom
2
Date: Sheet
Compal Electronics, Inc.
ATHLON64 HT I/F
LA-3221P
1
0.1
of
443Friday, January 06, 2006
A
B
C
D
E
VDD_VTT_SUS_CPU IS CONNECTED TO THE VDD_VTT_SUS POWER SUPPLY THROUGH THE PACKAGE OR ON THE DIE. IT IS ONLY CONNECTED
ON THE BOARD TO DECOUPLING NEAR THE CPU PACKAGE
+1.8V
4 4
3 3
2 2
12
R215
39.2_0603_1%
12
R212
39.2_0603_1%
PLACE THEM CLOSE TO CPU WITHIN 1"
DDR_CS3_DIMMA#8 DDR_CS2_DIMMA#8 DDR_CS1_DIMMA#8 DDR_CS0_DIMMA#8
DDR_CS3_DIMMB#9 DDR_CS2_DIMMB#9 DDR_CS1_DIMMB#9 DDR_CS0_DIMMB#9
DDR_CKE1_DIMMB9 DDR_CKE0_DIMMB9 DDR_CKE1_DIMMA8 DDR_CKE0_DIMMA8
DDR_A_MA[15..0]8
DDR_A_BS#28 DDR_A_BS#18 DDR_A_BS#08
DDR_A_RAS#8 DDR_A_CAS#8 DDR_A_WE#8
DDR_A_CLK2
DDR_A_CLK#2 DDR_A_CLK1
DDR_A_CLK#1
PLACE CLOSE TO PROCESSOR WITHIN 1.5 INCH
TP1
M_ZN M_ZP
1
C339
1.5P 50V F NPO 0402
2
1
C383
1.5P 50V F NPO 0402
2
+CPU_M_VREF
VTT_SENSE
DDR_CS3_DIMMA# DDR_CS2_DIMMA# DDR_CS1_DIMMA# DDR_CS0_DIMMA#
DDR_CS3_DIMMB# DDR_CS2_DIMMB# DDR_CS1_DIMMB# DDR_CS0_DIMMB#
DDR_CKE1_DIMMB DDR_CKE0_DIMMB DDR_CKE1_DIMMA DDR_CKE0_DIMMA
DDR_A_MA15 DDR_A_MA14 DDR_A_MA13 DDR_A_MA12 DDR_A_MA11 DDR_A_MA10 DDR_A_MA9 DDR_A_MA8 DDR_A_MA7 DDR_A_MA6 DDR_A_MA5 DDR_A_MA4 DDR_A_MA3 DDR_A_MA2 DDR_A_MA1 DDR_A_MA0
DDR_A_BS#2 DDR_A_BS#1 DDR_A_BS#0
DDR_A_RAS# DDR_A_CAS# DDR_A_WE#
AE10 AF10
W17
Y10
V19 J22 V22 T19
Y26 J24
W24
U23 H26
J23 J20 J21
K19 K20 V24 K24 L20 R19 L19 L22
L21 M19 M20 M24 M22
N22
N21
R21
K22
R20
T22
T20
U20
U21
M_VREF VTT_SENSE
M_ZN M_ZP
MA0_CS_L3 MA0_CS_L2 MA0_CS_L1 MA0_CS_L0
MB0_CS_L3 MB0_CS_L2 MB0_CS_L1 MB0_CS_L0
MB_CKE1 MB_CKE0 MA_CKE1 MA_CKE0
MA_ADD15 MA_ADD14 MA_ADD13 MA_ADD12 MA_ADD11 MA_ADD10 MA_ADD9 MA_ADD8 MA_ADD7 MA_ADD6 MA_ADD5 MA_ADD4 MA_ADD3 MA_ADD2 MA_ADD1 MA_ADD0
MA_BANK2 MA_BANK1 MA_BANK0
MA_RAS_L MA_CAS_L MA_WE_L
Athlon 64 S1 Processor Socket
CPU1B
VTT1 VTT2 VTT3 VTT4 VTT5 VTT6 VTT7 VTT8 VTT9
MA0_CLK_H2 MA0_CLK_L2 MA0_CLK_H1 MA0_CLK_L1
MB0_CLK_H2 MB0_CLK_L2 MB0_CLK_H1 MB0_CLK_L1
MB0_ODT1 MB0_ODT0 MA0_ODT1 MA0_ODT0
MB_ADD15 MB_ADD14 MB_ADD13 MB_ADD12 MB_ADD11 MB_ADD10
MB_ADD9
DDRII Cmd/Ctrl//Clk
MB_ADD8 MB_ADD7 MB_ADD6 MB_ADD5 MB_ADD4 MB_ADD3 MB_ADD2 MB_ADD1 MB_ADD0
MB_BANK2 MB_BANK1 MB_BANK0
MB_RAS_L MB_CAS_L
MB_WE_L
DDR_B_CLK2
DDR_B_CLK#2 DDR_B_CLK1
DDR_B_CLK#1
PLACE CLOSE TO PROCESSOR WITHIN 1.5 INCH
D10 C10 B10 AD10 W10 AC10 AB10 AA10 A10
Y16 AA16 E16 F16
AF18 AF17 A17 A18
W23 W26 V20 U19
J25 J26 W25 L23 L25 U25 L24 M26 L26 N23 N24 N25 N26 P24 P26 T24
K26 T26 U26
U24 V26 U22
+0.9V
DDR_A_CLK2 DDR_A_CLK#2 DDR_A_CLK1 DDR_A_CLK#1
DDR_B_CLK2 DDR_B_CLK#2 DDR_B_CLK1 DDR_B_CLK#1
DDR_B_ODT1 DDR_B_ODT0 DDR_A_ODT1 DDR_A_ODT0
DDR_B_MA15 DDR_B_MA14 DDR_B_MA13 DDR_B_MA12 DDR_B_MA11 DDR_B_MA10 DDR_B_MA9 DDR_B_MA8 DDR_B_MA7 DDR_B_MA6 DDR_B_MA5 DDR_B_MA4 DDR_B_MA3 DDR_B_MA2 DDR_B_MA1 DDR_B_MA0
DDR_B_BS#2 DDR_B_BS#1 DDR_B_BS#0
DDR_B_RAS# DDR_B_CAS# DDR_B_WE#
1
2
1
2
C340
1.5P 50V F NPO 0402
C382
1.5P 50V F NPO 0402
DDR_A_CLK2 8 DDR_A_CLK#2 8 DDR_A_CLK1 8 DDR_A_CLK#1 8
DDR_B_CLK2 9 DDR_B_CLK#2 9 DDR_B_CLK1 9 DDR_B_CLK#1 9
DDR_B_ODT1 9 DDR_B_ODT0 9 DDR_A_ODT1 8 DDR_A_ODT0 8
DDR_B_MA[15..0] 9
DDR_B_BS#2 9 DDR_B_BS#1 9 DDR_B_BS#0 9
DDR_B_RAS# 9 DDR_B_CAS# 9 DDR_B_WE# 9
Processor DDR2 Memory Interface
DDR_B_D[63..0]9
To reverse SODIMM socket
DDR_B_DM[7..0]9 DDR_A_DM[7..0] 8
DDR_B_DQS79 DDR_B_DQS#79 DDR_B_DQS69 DDR_B_DQS#69 DDR_B_DQS59 DDR_B_DQS#59 DDR_B_DQS49 DDR_B_DQS#49 DDR_B_DQS39 DDR_B_DQS#39 DDR_B_DQS29 DDR_B_DQS#29 DDR_B_DQS19 DDR_B_DQS#19 DDR_B_DQS09 DDR_B_DQS#09
DDR_B_D63 DDR_B_D62 DDR_B_D61 DDR_B_D60 DDR_B_D59 DDR_B_D58 DDR_B_D57 DDR_B_D56 DDR_B_D55 DDR_B_D54 DDR_B_D53 DDR_B_D52 DDR_B_D51 DDR_B_D50 DDR_B_D49 DDR_B_D48 DDR_B_D47 DDR_B_D46 DDR_B_D45 DDR_B_D44 DDR_B_D43 DDR_B_D42 DDR_B_D41 DDR_B_D40 DDR_B_D39 DDR_B_D38 DDR_B_D37 DDR_B_D36 DDR_B_D35 DDR_B_D34 DDR_B_D33 DDR_B_D32 DDR_B_D31 DDR_B_D30 DDR_B_D29 DDR_B_D28 DDR_B_D27 DDR_B_D26 DDR_B_D25 DDR_B_D24 DDR_B_D23 DDR_B_D22 DDR_B_D21 DDR_B_D20 DDR_B_D19 DDR_B_D18 DDR_B_D17 DDR_B_D16 DDR_B_D15 DDR_B_D14 DDR_B_D13 DDR_B_D12 DDR_B_D11 DDR_B_D10 DDR_B_D9 DDR_B_D8 DDR_B_D7 DDR_B_D6 DDR_B_D5 DDR_B_D4 DDR_B_D3 DDR_B_D2 DDR_B_D1 DDR_B_D0
DDR_B_DM7 DDR_B_DM6 DDR_B_DM5 DDR_B_DM4 DDR_B_DM3 DDR_B_DM2 DDR_B_DM1 DDR_B_DM0
DDR_B_DQS7 DDR_B_DQS#7 DDR_B_DQS6 DDR_B_DQS#6 DDR_B_DQS5 DDR_B_DQS#5 DDR_B_DQS4 DDR_B_DQS#4 DDR_B_DQS3 DDR_B_DQS#3 DDR_B_DQS2 DDR_B_DQS#2 DDR_B_DQS1 DDR_B_DQS#1 DDR_B_DQS0 DDR_B_DQS#0
AD11 AF11 AF14 AE14
AB11 AC12 AF13 AF15 AF16 AC18 AF19 AD14 AC14 AE18 AD18 AD20 AC20 AF23 AF24 AF20 AE20 AD22 AC22 AE25 AD26 AA25 AA26 AE24 AD24 AA23 AA24
AD12 AC16 AE22 AB26
AF12 AE12 AE16 AD16 AF21 AF22 AC25 AC26
Y11
G24 G23 D26 C26 G26 G25 E24 E23 C24 B24 C20 B20 C25 D24 A21 D20 D18 C18 D14 C14 A20 A19 A16 A15 A13 D12 E11 G11 B14 A14 A11 C11
E25 A22 B16 A12
F26 E26 A24 A23 D16 C16 C12 B12
MB_DATA63 MB_DATA62 MB_DATA61 MB_DATA60 MB_DATA59 MB_DATA58 MB_DATA57 MB_DATA56 MB_DATA55 MB_DATA54 MB_DATA53 MB_DATA52 MB_DATA51 MB_DATA50 MB_DATA49 MB_DATA48 MB_DATA47 MB_DATA46 MB_DATA45 MB_DATA44 MB_DATA43 MB_DATA42 MB_DATA41 MB_DATA40 MB_DATA39 MB_DATA38 MB_DATA37 MB_DATA36 MB_DATA35 MB_DATA34 MB_DATA33 MB_DATA32 MB_DATA31 MB_DATA30 MB_DATA29 MB_DATA28 MB_DATA27 MB_DATA26 MB_DATA25 MB_DATA24 MB_DATA23 MB_DATA22 MB_DATA21 MB_DATA20 MB_DATA19 MB_DATA18 MB_DATA17 MB_DATA16 MB_DATA15 MB_DATA14 MB_DATA13 MB_DATA12 MB_DATA11 MB_DATA10 MB_DATA9 MB_DATA8 MB_DATA7 MB_DATA6 MB_DATA5 MB_DATA4 MB_DATA3 MB_DATA2 MB_DATA1 MB_DATA0
MB_DM7 MB_DM6 MB_DM5 MB_DM4 MB_DM3 MB_DM2 MB_DM1 MB_DM0
MB_DQS_H7 MB_DQS_L7 MB_DQS_H6 MB_DQS_L6 MB_DQS_H5 MB_DQS_L5 MB_DQS_H4 MB_DQS_L4 MB_DQS_H3 MB_DQS_L3 MB_DQS_H2 MB_DQS_L2 MB_DQS_H1 MB_DQS_L1 MB_DQS_H0 MB_DQS_L0
CPU1C
DDRII Data
Athlon 64 S1 Processor Socket
MA_DATA63 MA_DATA62 MA_DATA61 MA_DATA60 MA_DATA59 MA_DATA58 MA_DATA57 MA_DATA56 MA_DATA55 MA_DATA54 MA_DATA53 MA_DATA52 MA_DATA51 MA_DATA50 MA_DATA49 MA_DATA48 MA_DATA47 MA_DATA46 MA_DATA45 MA_DATA44 MA_DATA43 MA_DATA42 MA_DATA41 MA_DATA40 MA_DATA39 MA_DATA38 MA_DATA37 MA_DATA36 MA_DATA35 MA_DATA34 MA_DATA33 MA_DATA32 MA_DATA31 MA_DATA30 MA_DATA29 MA_DATA28 MA_DATA27 MA_DATA26 MA_DATA25 MA_DATA24 MA_DATA23 MA_DATA22 MA_DATA21 MA_DATA20 MA_DATA19 MA_DATA18 MA_DATA17 MA_DATA16 MA_DATA15 MA_DATA14 MA_DATA13 MA_DATA12 MA_DATA11 MA_DATA10
MA_DATA9 MA_DATA8 MA_DATA7 MA_DATA6 MA_DATA5 MA_DATA4 MA_DATA3 MA_DATA2 MA_DATA1 MA_DATA0
MA_DM7 MA_DM6 MA_DM5 MA_DM4 MA_DM3 MA_DM2 MA_DM1 MA_DM0
MA_DQS_H7
MA_DQS_L7
MA_DQS_H6
MA_DQS_L6
MA_DQS_H5
MA_DQS_L5
MA_DQS_H4
MA_DQS_L4
MA_DQS_H3
MA_DQS_L3
MA_DQS_H2
MA_DQS_L2
MA_DQS_H1
MA_DQS_L1
MA_DQS_H0
MA_DQS_L0
AA12 AB12 AA14 AB14 W11 Y12 AD13 AB13 AD15 AB15 AB17 Y17 Y14 W14 W16 AD17 Y18 AD19 AD21 AB21 AB18 AA18 AA20 Y20 AA22 Y22 W21 W22 AA21 AB22 AB24 Y24 H22 H20 E22 E21 J19 H24 F22 F20 C23 B22 F18 E18 E20 D22 C19 G18 G17 C17 F14 E14 H17 E17 E15 H15 E13 C13 H12 H11 G14 H14 F12 G12
Y13 AB16 Y19 AC24 F24 E19 C15 E12
W12 W13 Y15 W15 AB19 AB20 AD23 AC23 G22 G21 C22 C21 G16 G15 G13 H13
DDR_A_D63 DDR_A_D62 DDR_A_D61 DDR_A_D60 DDR_A_D59 DDR_A_D58 DDR_A_D57 DDR_A_D56 DDR_A_D55 DDR_A_D54 DDR_A_D53 DDR_A_D52 DDR_A_D51 DDR_A_D50 DDR_A_D49 DDR_A_D48 DDR_A_D47 DDR_A_D46 DDR_A_D45 DDR_A_D44 DDR_A_D43 DDR_A_D42 DDR_A_D41 DDR_A_D40 DDR_A_D39 DDR_A_D38 DDR_A_D37 DDR_A_D36 DDR_A_D35 DDR_A_D34 DDR_A_D33 DDR_A_D32 DDR_A_D31 DDR_A_D30 DDR_A_D29 DDR_A_D28 DDR_A_D27 DDR_A_D26 DDR_A_D25 DDR_A_D24 DDR_A_D23 DDR_A_D22 DDR_A_D21 DDR_A_D20 DDR_A_D19 DDR_A_D18 DDR_A_D17 DDR_A_D16 DDR_A_D15 DDR_A_D14 DDR_A_D13 DDR_A_D12 DDR_A_D11 DDR_A_D10 DDR_A_D9 DDR_A_D8 DDR_A_D7 DDR_A_D6 DDR_A_D5 DDR_A_D4 DDR_A_D3 DDR_A_D2 DDR_A_D1 DDR_A_D0
DDR_A_DM7 DDR_A_DM6 DDR_A_DM5 DDR_A_DM4 DDR_A_DM3 DDR_A_DM2 DDR_A_DM1 DDR_A_DM0
DDR_A_DQS7 DDR_A_DQS#7 DDR_A_DQS6 DDR_A_DQS#6 DDR_A_DQS5 DDR_A_DQS#5 DDR_A_DQS4 DDR_A_DQS#4 DDR_A_DQS3 DDR_A_DQS#3 DDR_A_DQS2 DDR_A_DQS#2 DDR_A_DQS1 DDR_A_DQS#1 DDR_A_DQS0 DDR_A_DQS#0
DDR_A_D[63..0] 8
DDR_A_DQS7 8 DDR_A_DQS#7 8 DDR_A_DQS6 8 DDR_A_DQS#6 8 DDR_A_DQS5 8 DDR_A_DQS#5 8 DDR_A_DQS4 8 DDR_A_DQS#4 8 DDR_A_DQS3 8 DDR_A_DQS#3 8 DDR_A_DQS2 8 DDR_A_DQS#2 8 DDR_A_DQS1 8 DDR_A_DQS#1 8 DDR_A_DQS0 8 DDR_A_DQS#0 8
To normal SODIMM socket
A1
+1.8V
R27
1K_0402_1%
1 2
1 1
R26
1K_0402_1%
1 2
VDD_VREF_SUS_CPU
LAYOUT:PLACE CLOSE TO CPU
A
1
2
C35
0.1U_0402_16V4Z
+CPU_M_VREF
1
C36
2
1000P_0402_50V7K~N
B
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2005/12/1 2006/12/01
Compal Secret Data
Deciphered Date
D
Title
AMD CPU DDRII MEMORY I/F
Size Document Number Rev
Custom
LA-3221P
Date: Sheet
Athlon 64 S1g1
uPGA638 Top View
AF1
E
A26
543Friday, January 06, 2006
0.1
of
5
R238
@
0_0805_5%
R2390_0805_5% 1U_0603_10V4Z
C379
CPU_PWRGD16
LDT_STOP#11,16
LDT_RST#15 SB_PWRGD16,30
12 12
2
1
R232
470_0402_5%
D
@
S
300_0402_5%
300_0402_5%
300_0402_5%
LDT_RST#
R241 0_0402_5%
1 2
12
13
SYSON#
2
G
Q32 2N7002LT1G_SOT23
+1.8VS
12
R244
4.7K_0402_5%
+1.8VS
12
R57
+1.8VS
12
R242
12
5
U25
IN GND SHDN3BYP
G914E_SOT23-5
0.01U_0402_16V7K
+3VS
12
R243
@
1 2
TP49PAD TP51PAD
TP12PAD TP20PAD
TP18PAD TP17PAD
TP46PAD TP16PAD TP45PAD TP30PAD
5
OUT
4
C378
SYSON# 31,37
+1.8V
1 2
5
U27
P
IN1
O
IN2
G
NC7SZ08P5X_NL_SC70-5
3
+1.8V
5
U6
1
P
IN1
O
2
IN2
G
NC7SZ08P5X_NL_SC70-5
3
+1.8V
5
U26
1
P
IN1
O
2
IN2
G
NC7SZ08P5X_NL_SC70-5
3
+2.5VDDA
2
C393 1U_0603_10V4Z
1
1
2
C385 0.1U_0402_16V4Z
R236
4
1 2
CPU_ALL_PWROK
0_0402_5%
100U_6.3V_M
NC7SZ08P5X
C121 0.1U_0402_16V4Z
1 2
R50
4
1 2
CPU_LDTSTOP#
0_0402_5%
NC7SZ08P5X
C384 0.1U_0402_16V4Z
1 2
1 2
CPU_HT_RESET#
0_0402_5%
+1.8V
R206220_0402_5%
12
HDT_RST#
NC7SZ08P5X_NL_SC70-5
R235
4
NC7SZ08P5X
CPU_DBREQ# CPU_DBRDY CPU_TCK CPU_TMS CPU_TDI CPU_TRST# CPU_TDO
NOTE: HDT TERMINATION IS REQUIRED FOR REV. Ax SILICON ONLY.
+3VALW
+3VS +2.5VDDA
D D
C C
ASIC8M_CPU_PWRGD
B B
CPUCLK0_H CPUCLK0_L
CPU_VDD_FB_H CPU_VDD_FB_L
CPU_TEST29_H_FBCLKOUT_P CPU_TEST29_L_FBCLKOUT_N
CPU_ALL_PWROK CPU_LDTSTOP# CPU_HT_RESET# CPU_THERMTRIP#_R
A A
C398
R208220_0402_5%
R207220_0402_5%
12
12
4
L24 LQG21F4R7N00_0805
1 2
1
+
2
R209220_0402_5%
R210220_0402_5%
12
12
+3VALW
U30
4
O
@
4
LAYOUT: ROUTE VDDA TRACE APPROX. 50 mils WIDE (USE 2x25 mil TRACES TO EXIT BALL FIELD) AND 500 mils LONG.
3300P_0402_50V7K
1
1
C401
2
4.7U_0805_6.3V6K
1
C358
2
2
0.22U_0603_10V7K
place them to CPU within 1"
1 2
CPUCLK0_H13
CPUCLK0_L13
C390
1 2
C389 3900P_0402_50V7K
HDT Connector
JHDT1
2
1
4
3
6
5
8
7
10
9
12
11
14
13
16
15
18
17
20
19
22
21
2423 26
SAMTEC_ASP-68200-07
5
LDT_RST#
1
P
IN1
SB_PWRGD
2
IN2
G
3
CPU_+VDDA
C402
R219 300_0402_5%
1 2
R224 44.2_0402_1%
+1.2V_HT
R223 44.2_0402_1%
3900P_0402_50V7K
12
R234 169_0402_1%
TP15 TP19
TP23 TP21 TP13 TP44
TP33
TP42
THERMDC_CPU
THERMDA_CPU
TP3 TP5
TP7 TP10 TP9 TP11
TP39 TP40 TP6 TP8
HDT_RST#
3
ATHLON Control and Debug
CPU_HT_RESET# CPU_ALL_PWROK CPU_LDTSTOP#
CPU_SIC_R
1 2 1 2
CPU_VDD_FB_H38 CPU_VDD_FB_L38
TP2
CPU_CLKIN_SC_P CPU_CLKIN_SC_N
TP26
CPU_DBRDY CPU_TMS
CPU_TCK CPU_TRST# CPU_TDI
CPU_TEST25_H_BYPASSCLK_H CPU_TEST25_L_BYPASSCLK_L CPU_TEST19_PLLTEST0 CPU_TEST18_PLLTEST1
CPU_TEST17_BP3 CPU_TEST16_BP2 CPU_TEST15_BP1 CPU_TEST14_BP0 CPU_TEST12_SCANSHIFTENB
CPU_TEST07_ANALOG_T CPU_TEST6_DIECRACKMON
CPU_TEST3_GATE0 CPU_TEST2_DRAIN0
CPU_RSVD_MA0_CLK3_P CPU_RSVD_MA0_CLK3_N CPU_RSVD_MA0_CLK0_P CPU_RSVD_MA0_CLK0_N
CPU_RSVD_MB0_CLK3_P CPU_RSVD_MB0_CLK3_N CPU_RSVD_MB0_CLK0_P CPU_RSVD_MB0_CLK0_N
CPU_HTREF1 CPU_HTREF0
VDDIOFB_H VDDIOFB_L
F8
VDDA2
F9
VDDA1
B7
RESET_L
A7
PWROK
F10
LDTSTOP_L
AF4
SIC
AF5
SID
P6
HTREF1
R6
HTREF0
F6
VDD_FB_H
E6
VDD_FB_L
W9
VDDIO_FB_H
Y9
VDDIO_FB_L
A9
CLKIN_H
A8
CLKIN_L
G10
DBRDY
AA9
TMS
AC9
TCK
AD9
TRST_L
AF9
TDI TEST25_HE9TEST29_H
E8
TEST25_L
G9
TEST19
H10
TEST18
AA7
TEST13
C2
TEST9
D7
TEST17
E7
TEST16
F7
TEST15
C7
TEST14
AC8
TEST12
C3
TEST7
AA6
TEST6
W7
THERMDC
W8
THERMDA
Y6
TEST3
AB6
TEST2
P20
RSVD0
P19
RSVD1
N20
RSVD2
N19
RSVD3
R26
RSVD4
R25
RSVD5
P22
RSVD6
R22
RSVD7
THERMDA_CPU
2200P_0402_50V7K
THERMDC_CPU
EC_SMB_CK227 EC_SMB_DA227
CPU1D
THERMTRIP_L
PROCHOT_L
VID5 VID4 VID3 VID2 VID1 VID0
CPU_PRESENT_L
PSI_L
DBREQ_L
TDO
TEST29_L
TEST24 TEST23
MISC
TEST22 TEST21 TEST20
TEST28_H
TEST28_L
TEST27 TEST26 TEST10
TEST8
RSVD8 RSVD9
RSVD10 RSVD11
RSVD12 RSVD13 RSVD14
RSVD15 RSVD16 RSVD17 RSVD18 RSVD19 RSVD20
1
C344
2
EC_SMB_CK2 EC_SMB_DA2
2
+1.8V
12
12
R213
R216
CPU_THERMTRIP#_R
AF6
CPU_PROCHOT#_1.8
AC7
VID5
A5
VID4
C6
VID3
A6
VID2
A4
VID1
C5
VID0
B5
CPU_PRESENT#
AC6
CPU_PSI#
A3
CPU_DBREQ#
E10
CPU_TDO
AE9
CPU_TEST29_H_FBCLKOUT_P
C9
CPU_TEST29_L_FBCLKOUT_N
C8
ROUTE AS 80 Ohm DIFFERENTIAL PAIR PLACE IT CLOSE TO CPU WITHIN 1"
CPU_TEST24_SCANCLK1
AE7
CPU_TEST23_TSTUPD
AD7
CPU_TEST22_SCANSHIFTEN
AE8
CPU_TEST21_SCANEN
AB8
CPU_TEST20_SCANCLK2
AF7
CPU_TEST28_H_PLLCHRZ_P
J7
CPU_TEST28_L_PLLCHRZ_N
H8 AF8
CPU_TEST26_BURNIN#
AE6
CPU_TEST10_ANALOGOUT
K8
CPU_TEST08_DIG_T
C4
CPU_MA_RESET#
H16
CPU_MB_RESET#
B18
CPU_RSVD_VIDSTRB1
B3
CPU_RSVD_VIDSTRB0
C1
CPU_RSVD_VDDNB_FB_P
H6
CPU_RSVD_VDDNB_FB_N
G6
CPU_RSVD_CORE_TYPE
D5 R24
W18 R23
AMD NPT S1 SOCKET
AA8
Processor Socket
H18 H19
from EFL50
U24
2
D+
3
D-
8
SCLK
7
SDATA
ADM1032ARMZ MSOP 8P
+3VS
1
C342
0.1U_0402_16V4Z
2
VDD1
ALERT#
THERM#
GND
300_0402_5%
TP50
CPU_PSI# 38
1 6 4 5
SMBus Address: 1001110X (b)
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2005/12/1 2006/12/01
Deciphered Date
2
+1.8V +3VALW
R240
Q30
300_0402_5%
1 2
300_0402_5%
3 1
MMBT3904_NL_SOT23
R46
80.6_0402_1%
1 2
TP27 TP31 TP29 TP32 TP28
TP35 TP36TP4
TP34 TP43
TP14 TP48
TP47 TP41
TP37 TP38 TP22
R376
R220
1 2 2
10K_0402_5%
1 2
VID5 38 VID4 38 VID3 38 VID2 38 VID1 38 VID0 38
CPU_PROCHOT#_1.8
4.7K_0402_5%
H_THERMTRIP# 16
CPU_TEST26_BURNIN# CPU_PRESENT# CPU_TEST25_H_BYPASSCLK_H
CPU_TEST21_SCANEN CPU_TEST19_PLLTEST0 CPU_TEST25_L_BYPASSCLK_L CPU_TEST18_PLLTEST1
1
+1.8V
+3VALW
R214
1 2
@
10K_0402_5%
CPU_PH_G
2
Q29
3 1
MMBT3904_NL_SOT23
@
Thermal Sensor
12
R222
10K_0402_5%@
THERM#
Title
Size Document Number Rev
Custom
Date: Sheet
ADM1032
Compal Electronics, Inc.
ATHLON64 CTRL & DEBUG
LA-3221P
1
R211
@
4.7K_0402_5%
1 2
CPU_PROCHOT#
R218 300_0402_5%
1 2
R217 1K_0402_5%
1 2
R47 510_0402_5%
1 2
R221 300_0402_5%
1 2
R49 300_0402_5%
1 2
R48 510_0402_5%
1 2
R51 300_0402_5%
1 2
643Friday, January 06, 2006
TP25
+1.8V
of
0.1
5
4
3
2
1
Ground
Athlon 64 S1 Processor Socket
1
C55
2
180P_0402_50V8J~N
180P_0402_50V8J~N
C380
1000P_0402_50V7K~N
CPU1F
VSS66 VSS67 VSS68 VSS69 VSS70 VSS71 VSS72 VSS73 VSS74 VSS75 VSS76 VSS77 VSS78 VSS79 VSS80 VSS81 VSS82 VSS83 VSS84 VSS85 VSS86 VSS87 VSS88 VSS89 VSS90 VSS91 VSS92 VSS93 VSS94 VSS95 VSS96 VSS97 VSS98
VSS99 VSS100 VSS101 VSS102 VSS103 VSS104 VSS105 VSS106 VSS107 VSS108 VSS109 VSS110 VSS111 VSS112 VSS113 VSS114 VSS115 VSS116 VSS117 VSS118 VSS119 VSS120 VSS121 VSS122 VSS123 VSS124 VSS125 VSS126 VSS127 VSS128 VSS129
C81
C388
1000P_0402_50V7K~N
J6 J8 J10 J12 J14 J16 J18 K2 K7 K9 K11 K13 K15 K17 L6 L8 L10 L12 L14 L16 L18 M7 M9 M11 M17 N4 N8 N10 N16 N18 P2 P7 P9 P11 P17 R8 R10 R16 R18 T7 T9 T11 T13 T15 T17 U4 U6 U8 U10 U12 U14 U16 U18 V2 V7 V9 V11 V13 V15 V17 W6 Y21 Y23 N6
+1.8V
330U_D2E_2.5VM
330U_D2E_2.5VM
1
1
C79
C38
+
+
2
2
12C338
180P_0402_50V8J~N
2
1
180P_0402_50V8J~N
2
2
1
C335
1
C336
180P_0402_50V8J~N
180P_0402_50V8J~N
AA4
VSS1
AA11
VSS2
AA13
VSS3
AA15
VSS4
AA17
VSS5
AA19
+CPU_CORE +CPU_CORE
AC4
VDD1
AD2
VDD2
G4
VDD3
H2
D D
BOTTOMSIDE DECOUPLING
+CPU_CORE
330U_D2E_2.5VM
1
proadlizer 1200uF
C C
PLACE CLOSE TO SO-DIMM1 AS POSSIBLE
+1.8V
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
2
C72
B B
A A
+1.8V
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
2
C67
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
1
2
2
C66
C47
PLACE CLOSE TO SO-DIMM2 AS POSSIBLE
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
1
2
2
C88
C40
2
+
PC44 1200P_PFAF250E128MNTTE_2.5VM
3 4
+1.8V
1
1
C91
C48
2
2
22U_0805_6.3V6M
22U_0805_6.3V6M
0.1U_0402_16V4Z
1
2
C30
0.1U_0402_16V4Z
1
2
C62
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
1
2
2
C82
C37
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
1
2
2
C51
C350
1
2
1
2
C354
C349
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
2
C352
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
2
C347
C351
1
2
1
2
1
2
C57
C345
C330
1
C346
2
0.22U_0603_10V7K
0.1U_0402_16V4Z
1
2
C93
0.1U_0402_16V4Z
1
2
C76
330U_D2E_2.5VM
1
1
C331
+
+
2
2
0.22U_0603_10V7K
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
1
2
2
C60
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
1
2
2
C33
1
1
C84
C98
2
2
C52
C26
C43
4.7U_0805_6.3V6K
4.7U_0805_6.3V6K
1
1
C27
2
2
4.7U_0805_6.3V6K
4.7U_0805_6.3V6K
VDD4
J9
VDD5
J11
VDD6
J13
VDD7
K6
VDD8
K10
VDD9
K12
VDD10
K14
VDD11
L4
VDD12
L7
VDD13
L9
VDD14
L11
VDD15
L13
VDD16
M2
VDD17
M6
VDD18
M8
VDD19
M10
VDD20
N7
VDD21
N9
VDD22
N11
VDD23
P8
VDD24
P10
VDD25
R4
VDD26
R7
VDD27
R9
VDD28
R11
VDD29
T2
VDD30
T6
VDD31
T8
VDD32
T10
VDD33
T12
VDD34
T14
VDD35
U7
VDD36
U9
VDD37
U11
VDD38
U13
VDD39
V6
VDD40
V8
VDD41
V10
VDD42
C334
CPU1E
V12
VDD43
V14
VDD44
W4
VDD45
Y2
VDD46
J15
VDD47
K16
VDD48
L15
VDD49
M16
VDD50
P16
VDD51
T16
VDD52
U15
VDD53
V16
Athlon 64 S1 Processor Socket
VDD54
VDDIO1 VDDIO2 VDDIO3 VDDIO4 VDDIO5 VDDIO6 VDDIO7 VDDIO8 VDDIO9
VDDIO10
Power
VDDIO11 VDDIO12 VDDIO13 VDDIO14 VDDIO15 VDDIO16 VDDIO17 VDDIO18 VDDIO19 VDDIO20 VDDIO21 VDDIO22 VDDIO23 VDDIO24 VDDIO25 VDDIO26 VDDIO27
+1.8V+CPU_CORE
H25 J17 K18 K21 K23 K25 L17 M18 M21 M23 M25 N17 P18 P21 P23 P25 R17 T18 T21 T23 T25 U17 V18 V21 V23 V25 Y25
DECOUPLING BETWEEN PROCESSOR AND DIMMs PLACE CLOSE TO PROCESSOR AS POSSIBLE
+1.8V
1
1
C343
2
+0.9V
1
1
C399
2
2
4.7U_0805_6.3V6K
1
C28
2
4.7U_0805_6.3V6K
1
C394
2
4.7U_0805_6.3V6K
1
C97
C359
2
2
4.7U_0805_6.3V6K
4.7U_0805_6.3V6K
1
1
C83
C29
2
2
4.7U_0805_6.3V6K
4.7U_0805_6.3V6K
1
1
C355
2
4.7U_0805_6.3V6K
1
C395
2
4.7U_0805_6.3V6K
1
1
C95
C348
2
0.22U_0603_10V7K
C400
0.22U_0603_10V7K
C353
2
0.22U_0603_10V7K
1
C333
2
0.22U_0603_10V7K
C86
2
0.22U_0603_10V7K
0.22U_0603_10V7K
1
1
C337
C332
2
2
0.22U_0603_10V7K
0.22U_0603_10V7K
VSS6
AB2
VSS7
AB7
VSS8
AB9
VSS9
AB23
VSS10
AB25
VSS11
AC11
VSS12
AC13
VSS13
AC15
VSS14
AC17
VSS15
AC19
VSS16
AC21
VSS17
AD6
VSS18
AD8
VSS19
AD25
VSS20
AE11
VSS21
AE13
VSS22
AE15
VSS23
AE17
VSS24
AE19
VSS25
AE21
VSS26
AE23
VSS27
B4
VSS28
B6
VSS29
B8
VSS30
B9
VSS31
B11
VSS32
B13
VSS33
B15
VSS34
B17
VSS35
B19
VSS36
B21
VSS37
B23
VSS38
B25
VSS39
D6
VSS40
D8
VSS41
D9
VSS42
D11
VSS43
D13
VSS44
D15
VSS45
D17
VSS46
D19
VSS47
D21
VSS48
D23
VSS49
D25
VSS50
E4
VSS51
F2
VSS52
F11
VSS53
F13
VSS54
F15
VSS55
F17
VSS56
F19
VSS57
F21
VSS58
F23
VSS59
F25
VSS60
H7
VSS61
H9
VSS62
H21
VSS63
H23
VSS64
J4
VSS65
1
C78
2
0.01U_0402_16V7K
0.01U_0402_16V7K
C381
C387
1000P_0402_50V7K~N
1000P_0402_50V7K~N
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2005/12/1 2006/12/01
Deciphered Date
Title
Size Document Number Rev
Custom
2
Date: Sheet
Compal Electronics, Inc.
ATHLON64 PWR & GND
LA-3221P
1
0.1
of
743Friday, January 06, 2006
5
JDIM1
1
VREF
3
DDR_A_D0
D D
C C
DDR_CKE0_DIMMA5 DDR_CS2_DIMMA#5
DDR_A_BS#25
DDR_A_BS#05 DDR_A_WE#5
DDR_A_CAS#5 DDR_CS1_DIMMA#5
DDR_A_ODT15
B B
A A
SMB_CK_DAT19,13,16,26 SMB_CK_CLK19,13,16,26
DDR_A_D1 DDR_A_DQS#0
DDR_A_DQS0 DDR_A_D2
DDR_A_D3 DDR_A_D8
DDR_A_D9 DDR_A_DQS#1
DDR_A_DQS1 DDR_A_D10
DDR_A_D11
DDR_A_D16 DDR_A_D17
DDR_A_DQS#2 DDR_A_DQS2
DDR_A_D18 DDR_A_D22 DDR_A_D19
DDR_A_D24 DDR_A_D25
DDR_A_DM3
DDR_A_D26 DDR_A_D27
DDR_CKE0_DIMMA DDR_CS2_DIMMA#
DDR_A_BS#2 DDR_A_MA12
DDR_A_MA9
DDR_A_MA5 DDR_A_MA3 DDR_A_MA1
DDR_A_MA10 DDR_A_BS#0 DDR_A_WE#
DDR_A_CAS# DDR_CS1_DIMMA#
DDR_A_ODT1 DDR_A_D32
DDR_A_D33 DDR_A_DQS#4
DDR_A_DQS4 DDR_A_D34
DDR_A_D35 DDR_A_D40
DDR_A_D41 DDR_A_DM5 DDR_A_D42
DDR_A_D43 DDR_A_D47 DDR_A_D48
DDR_A_D49 DDR_A_D53
DDR_A_DQS#6 DDR_A_DQS6
DDR_A_D50 DDR_A_D51 DDR_A_D55
DDR_A_D56 DDR_A_D57
DDR_A_DM7 DDR_A_D58
DDR_A_D59 SMB_CK_DAT1
SMB_CK_CLK1
+3VS
5
VSS
5
DQ0
7
DQ1
9
VSS
11
DQS0#
13
DQS0
15
VSS
17
DQ2
19
DQ3
21
VSS
23
DQ8
25
DQ9
27
VSS
29
DQS1#
31
DQS1
33
VSS
35
DQ10
37
DQ11
39
VSS
41
VSS
43
DQ16
45
DQ17
47
VSS
49
DQS2#
51
DQS2
53
VSS
55
DQ18
57
DQ19
59
VSS
61
DQ24
63
DQ25
65
VSS
67
DM3
69
NC
71
VSS
73
DQ26
75
DQ27
77
VSS
79
CKE0
81
VDD
83
NC
85
BA2
87
VDD
89
A12
91
A9
93
A8
95
VDD
97
A5
99
A3
101
A1
103
VDD
105
A10/AP
107
BA0
109
WE#
111
VDD
113
CAS#
115
NC/S1#
117
VDD
119
NC/ODT1
121
VSS
123
DQ32
125
DQ33
127
VSS
129
DQS4#
131
DQS4
133
VSS
135
DQ34
137
DQ35
139
VSS
141
DQ40
143
DQ41
145
VSS
147
DM5
149
VSS
151
DQ42
153
DQ43
155
VSS
157
DQ48
159
DQ49
161
VSS
163
NC,TEST
165
VSS
167
DQS6#
169
DQS6
171
VSS
173
DQ50
175
DQ51
177
VSS
179
DQ56
181
DQ57
183
VSS
185
DM7
187
VSS
189
DQ58
191
DQ59
193
VSS
195
SDA
197
SCL
199
VDDSPD
P-TWO_A5692C-A0G16
VSS DQ4 DQ5
VSS DM0 VSS DQ6 DQ7 VSS
DQ12 DQ13
VSS DM1 VSS
CK0
CK0#
VSS
DQ14 DQ15
VSS
VSS
DQ20 DQ21
VSS DM2
VSS
DQ22 DQ23
VSS
DQ28 DQ29
VSS
DQS3#
DQS3
VSS
DQ30 DQ31
VSS
NC/CKE1
VDD
NC/A15 NC/A14
VDD
A11
VDD
VDD
BA1
RAS#
S0# VDD
ODT0
NC/A13
VDD VSS
DQ36 DQ37
VSS DM4 VSS
DQ38 DQ39
VSS
DQ44 DQ45
VSS
DQS5#
DQS5
VSS
DQ46 DQ47
VSS
DQ52 DQ53
VSS
CK1
CK1#
VSS DM6 VSS
DQ54 DQ55
VSS
DQ60 DQ61
VSS
DQS7#
DQS7
VSS
DQ62 DQ63
VSS SAO
SA1
4
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40
42 44 46 48 50
NC
52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92
A7
94
A6
96 98
A4
100
A2
102
A0
104 106 108 110 112 114 116 118 120
NC
122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200
4
DDR_A_D4 DDR_A_D5
DDR_A_DM0 DDR_A_D6
DDR_A_D7 DDR_A_D12
DDR_A_D13 DDR_A_DM1 DDR_A_CLK1
DDR_A_CLK#1 DDR_A_D14
DDR_A_D15
DDR_A_D20 DDR_A_D21
DDR_A_DM2
DDR_A_D23 DDR_A_D28
DDR_A_D29 DDR_A_DQS#3
DDR_A_DQS3 DDR_A_D30
DDR_A_D31 DDR_CKE1_DIMMA DDR_A_MA15
DDR_A_MA14 DDR_A_MA11
DDR_A_MA7 DDR_A_MA6DDR_A_MA8
DDR_A_MA4 DDR_A_MA2 DDR_A_MA0
DDR_A_BS#1 DDR_A_RAS# DDR_CS0_DIMMA#
DDR_A_ODT0 DDR_A_MA13
DDR_CS3_DIMMA# DDR_A_D36
DDR_A_D37 DDR_A_DM4 DDR_A_D38
DDR_A_D39 DDR_A_D44
DDR_A_D45 DDR_A_DQS#5
DDR_A_DQS5 DDR_A_D46
DDR_A_D52
DDR_A_CLK2 DDR_A_CLK#2
DDR_A_DM6 DDR_A_D54
DDR_A_D60 DDR_A_D61
DDR_A_DQS#7 DDR_A_DQS7
DDR_A_D62 DDR_A_D63
R13 0_0402_5%
12 12
R14 0_0402_5%
1
2
DDR_A_CLK1 5 DDR_A_CLK#1 5
DDR_CKE1_DIMMA 5
DDR_A_BS#1 5 DDR_A_RAS# 5 DDR_CS0_DIMMA# 5
DDR_A_ODT0 5
DDR_CS3_DIMMA# 5
DDR_A_CLK2 5 DDR_A_CLK#2 5
3
+1.8V+DIMM_VREF+1.8V+1.8V
R63
1
C147
C148
2
1000P_0402_50V7K~N
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
1K_0402_1%
1 2
0.1U_0402_16V4Z R62
1K_0402_1%
1 2
2005/12/1 2006/12/01
+1.8V
0.1U_0402_16V4Z
1
2
C85
+0.9V
+0.9V
0.1U_0402_16V4Z
1
2
C59
Deciphered Date
2
DDR_A_D[0..63]5
DDR_A_DM[0..7]5
DDR_A_DQS[0..7]5
DDR_A_MA[0..15]5
DDR_A_DQS#[0..7]5
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
2
C41
0.1U_0402_16V4Z
1
2
C34
0.1U_0402_16V4Z
1
1
2
2
C45
C73
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
1
2
2
C75
C63
2
DDR_A_D[0..63] DDR_A_DM[0..7] DDR_A_DQS[0..7] DDR_A_MA[0..15] DDR_A_DQS#[0..7]
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
2
C56
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
2
C89
DDR_CKE1_DIMMA DDR_A_MA7 DDR_A_MA14 DDR_A_MA15
DDR_A_CAS# DDR_A_MA10 DDR_A_BS#0 DDR_A_MA1
DDR_A_MA2 DDR_A_BS#1 DDR_A_MA0 DDR_A_RAS#
DDR_A_MA9 DDR_A_MA5 DDR_A_MA3 DDR_A_MA8
DDR_A_MA11 DDR_A_MA6 DDR_A_MA4
DDR_A_ODT1 DDR_CS1_DIMMA#
DDR_A_WE#
DDR_CS0_DIMMA# DDR_A_MA13 DDR_A_ODT0 DDR_CS3_DIMMA#
DDR_A_BS#2 DDR_A_MA12 DDR_CKE0_DIMMA DDR_CS2_DIMMA#
1
Layout Note: Place one cap close to every 2 pullup resistors terminated to +0.9V
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
1
1
2
C80
1
2
C49
47_0804_8P4R_5%
47_0804_8P4R_5%
47_0804_8P4R_5%
47_0804_8P4R_5%
47_0804_8P4R_5%
47_0804_8P4R_5%
Size Document Number Rev
Custom
Date: Sheet
2
2
C69
C54
Layout Note: Place one cap close to every 2 pullup resistors terminated to +0.9V
0.1U_0402_16V4Z
1
2
C31
RP14
47_0804_8P4R_5%
RP7
RP9
47_0804_8P4R_5%
RP13
RP10
RP5
RP4
RP16
Title
DDR2 SO-DIMM I
LA-3221P
0.1U_0402_16V4Z
1
2
18 27 36 45
18 27 36 45
18 27 36 45
18 27 36 45
18 27 36 45
18 27 36 45
18 27 36 45
18 27 36 45
+0.9V
330U_D2E_2.5VM
1
C70
+
C92
+0.9V
2
1
843Friday, January 06, 2006
0.1
of
5
4
3
2
1
DDR_B_D[0..63] DDR_B_DM[0..7] DDR_B_DQS[0..7] DDR_B_MA[0..15] DDR_B_DQS#[0..7]
0.1U_0402_16V4Z
1
2
C71
0.1U_0402_16V4Z
1
2
C74
DDR_CKE1_DIMMB DDR_B_MA14 DDR_B_MA15 DDR_B_MA11
DDR_B_MA1 DDR_B_MA3 DDR_B_MA9 DDR_B_MA12
DDR_B_BS#0 DDR_B_MA10 DDR_B_WE# DDR_B_MA5
DDR_B_MA2 DDR_B_BS#1 DDR_CS0_DIMMB# DDR_B_RAS#
DDR_B_ODT0 DDR_B_MA13 DDR_CS3_DIMMB#
DDR_B_ODT1 DDR_CS1_DIMMB# DDR_B_CAS#
DDR_B_MA7 DDR_B_MA0 DDR_B_MA6 DDR_B_MA4
DDR_B_BS#2 DDR_B_MA8 DDR_CKE0_DIMMB DDR_CS2_DIMMB#
0.1U_0402_16V4Z
1
2
0.1U_0402_16V4Z
1
2
C32
C50
47_0804_8P4R_5%
47_0804_8P4R_5%
47_0804_8P4R_5%
47_0804_8P4R_5%
47_0804_8P4R_5%
47_0804_8P4R_5%
47_0804_8P4R_5%
47_0804_8P4R_5%
0.1U_0402_16V4Z
1
Layout Note: Place one cap close to every 2 pullup
2
C44
resistors terminated to +0.9V
0.1U_0402_16V4Z
Layout Note:
1
Place one cap close to every 2 pullup resistors terminated to +0.9V
2
C39
+0.9V
RP15
18 27 36 45
RP12
18 27 36 45
RP8
18 27 36 45
RP6
18 27 36 45
RP2
18 27 36 45
RP3
18 27 36 45
RP11
18 27 36 45
RP17
18 27 36 45
Title
DDR2 SO-DIMM II
Size Document Number Rev
Custom
LA-3221P
Date: Sheet
1
943Friday, January 06, 2006
0.1
of
0.1U_0402_16V4Z
1
2
C77
0.1U_0402_16V4Z
1
2
C46
Deciphered Date
DDR_B_D[0..63]5 DDR_B_DM[0..7]5
DDR_B_DQS[0..7]5 DDR_B_MA[0..15]5
DDR_B_DQS#[0..7]5
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
1
2
2
C61
C42
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
1
2
2
C64
C58
2
+DIMM_VREF+1.8V+1.8V
JDIM2
1
VREF
3
DDR_B_D0
D D
C C
DDR_CKE0_DIMMB5 DDR_CS2_DIMMB#5
DDR_B_BS#25
DDR_B_BS#05 DDR_B_WE#5
DDR_B_CAS#5 DDR_CS1_DIMMB#5
DDR_B_ODT15
B B
A A
SMB_CK_DAT18,13,16,26 SMB_CK_CLK18,13,16,26
DDR_B_D1 DDR_B_DQS#0
DDR_B_DQS0 DDR_B_D2
DDR_B_D3 DDR_B_D8
DDR_B_D9 DDR_B_DQS#1
DDR_B_DQS1 DDR_B_D10
DDR_B_D11
DDR_B_D16 DDR_B_D17
DDR_B_DQS#2 DDR_B_DQS2
DDR_B_D18 DDR_B_D22 DDR_B_D19
DDR_B_D24 DDR_B_D25
DDR_B_DM3
DDR_B_D26 DDR_B_D27
DDR_CKE0_DIMMB DDR_CS2_DIMMB#
DDR_B_BS#2 DDR_B_MA12
DDR_B_MA9
DDR_B_MA5 DDR_B_MA3 DDR_B_MA1
DDR_B_MA10 DDR_B_BS#0 DDR_B_WE#
DDR_B_CAS# DDR_CS1_DIMMB#
DDR_B_ODT1 DDR_B_D32
DDR_B_D33 DDR_B_DQS#4
DDR_B_DQS4 DDR_B_D34
DDR_B_D35 DDR_B_D40
DDR_B_D41 DDR_B_DM5 DDR_B_D42
DDR_B_D43 DDR_B_D47 DDR_B_D48
DDR_B_D49 DDR_B_D53
DDR_B_DQS#6 DDR_B_DQS6
DDR_B_D50 DDR_B_D51 DDR_B_D55
DDR_B_D56 DDR_B_D57
DDR_B_DM7 DDR_B_D58
DDR_B_D59 SMB_CK_DAT1
SMB_CK_CLK1
+3VS
5
VSS
5
DQ0
7
DQ1
9
VSS
11
DQS0#
13
DQS0
15
VSS
17
DQ2
19
DQ3
21
VSS
23
DQ8
25
DQ9
27
VSS
29
DQS1#
31
DQS1
33
VSS
35
DQ10
37
DQ11
39
VSS
41
VSS
43
DQ16
45
DQ17
47
VSS
49
DQS2#
51
DQS2
53
VSS
55
DQ18
57
DQ19
59
VSS
61
DQ24
63
DQ25
65
VSS
67
DM3
69
NC
71
VSS
73
DQ26
75
DQ27
77
VSS
79
CKE0
81
VDD
83
NC
85
BA2
87
VDD
89
A12
91
A9
93
A8
95
VDD
97
A5
99
A3
101
A1
103
VDD
105
A10/AP
107
BA0
109
WE#
111
VDD
113
CAS#
115
NC/S1#
117
VDD
119
NC/ODT1
121
VSS
123
DQ32
125
DQ33
127
VSS
129
DQS4#
131
DQS4
133
VSS
135
DQ34
137
DQ35
139
VSS
141
DQ40
143
DQ41
145
VSS
147
DM5
149
VSS
151
DQ42
153
DQ43
155
VSS
157
DQ48
159
DQ49
161
VSS
163
NC,TEST
165
VSS
167
DQS6#
169
DQS6
171
VSS
173
DQ50
175
DQ51
177
VSS
179
DQ56
181
DQ57
183
VSS
185
DM7
187
VSS
189
DQ58
191
DQ59
193
VSS
195
SDA
197
SCL
199
VDDSPD
P-TWO_A5652C-A0G16
CONN@
VSS DQ4 DQ5 VSS DM0 VSS DQ6 DQ7
VSS DQ12 DQ13
VSS
DM1
VSS
CK0
CK0#
VSS DQ14 DQ15
VSS
VSS DQ20 DQ21
VSS
DM2
VSS DQ22 DQ23
VSS DQ28 DQ29
VSS
DQS3#
DQS3
VSS DQ30 DQ31
VSS
NC/CKE1
VDD
NC/A15 NC/A14
VDD
A11
VDD
VDD
BA1
RAS#
S0#
VDD ODT0
NC/A13
VDD
VSS DQ36 DQ37
VSS
DM4
VSS DQ38 DQ39
VSS DQ44 DQ45
VSS
DQS5#
DQS5
VSS DQ46 DQ47
VSS DQ52 DQ53
VSS
CK1
CK1#
VSS
DM6
VSS DQ54 DQ55
VSS DQ60 DQ61
VSS
DQS7#
DQS7
VSS DQ62 DQ63
VSS
SAO
SA1
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40
42 44 46 48 50
NC
52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92
A7
94
A6
96 98
A4
100
A2
102
A0
104 106 108 110 112 114 116 118 120
NC
122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200
4
DDR_B_D4 DDR_B_D5
DDR_B_DM0 DDR_B_D6
DDR_B_D7 DDR_B_D12
DDR_B_D13 DDR_B_DM1 DDR_B_CLK1
DDR_B_CLK#1 DDR_B_D14
DDR_B_D15
DDR_B_D20 DDR_B_D21
DDR_B_DM2
DDR_B_D23 DDR_B_D28
DDR_B_D29 DDR_B_DQS#3
DDR_B_DQS3 DDR_B_D30
DDR_B_D31 DDR_CKE1_DIMMB DDR_B_MA15
DDR_B_MA14 DDR_B_MA11
DDR_B_MA7 DDR_B_MA6DDR_B_MA8
DDR_B_MA4 DDR_B_MA2 DDR_B_MA0
DDR_B_BS#1 DDR_B_RAS# DDR_CS0_DIMMB#
DDR_B_ODT0 DDR_B_MA13
DDR_CS3_DIMMB# DDR_B_D36
DDR_B_D37 DDR_B_DM4 DDR_B_D38
DDR_B_D39 DDR_B_D44
DDR_B_D45 DDR_B_DQS#5
DDR_B_DQS5 DDR_B_D46
DDR_B_D52
DDR_B_CLK2 DDR_B_CLK#2
DDR_B_DM6 DDR_B_D54
DDR_B_D60 DDR_B_D61
DDR_B_DQS#7 DDR_B_DQS7
DDR_B_D62 DDR_B_D63
R15 4.7K_0402_5%
1 2
R16 0_0402_5%
12
DDR_B_CLK1 5 DDR_B_CLK#1 5
DDR_CKE1_DIMMB 5
DDR_B_BS#1 5 DDR_B_RAS# 5 DDR_CS0_DIMMB# 5
DDR_B_ODT0 5
DDR_CS3_DIMMB# 5
DDR_B_CLK2 5 DDR_B_CLK#2 5
+3VS
1
C156
2
1000P_0402_50V7K~N
C53
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
+0.9V
0.1U_0402_16V4Z
330U_D2E_2.5VM
1
+
2
2005/12/1 2006/12/01
0.1U_0402_16V4Z
1
1
2
2
C87
C90
+1.8V
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
1
2
2
C68
C65
+0.9V
5
D D
4
3
2
1
H_CADIP[0..15]4 H_CADIN[0..15]4
H_CADOP[0..15]4
H_CADON[0..15]4
NB1B
G5 G4
J8 J7 J4 J5 L8 L7 L4
W11 W12
AA11 AB11
W14 W15
AB12 AA12
AA14 AB14
L5 M8 M7 M4 M5
P8
P7
P4
P5 R4 R5 R7 R8 U4 U5
W4 W5
Y4
Y5
V9
W9 AB7 AB6
Y7
AA7 AB9
AA9
C C
PCIE_LAN_C_RX_P223 PCIE_LAN_C_RX_N223
PCIE_WLAN_C_RX_P126 PCIE_WLAN_C_RX_N126
B B
SB_RX0P15 SB_RX0N15
SB_RX1P15 SB_RX1N15
PCIE_LAN_C_RX_P2 PCIE_LAN_C_RX_N2
PCIE_WLAN_C_RX_P1 PCIE_WLAN_C_RX_N1
R36 10K_0402_1%
1 2
R32 8.25K_0402_1%
1 2
SB_RX0P SB_RX0N
SB_RX1P SB_RX1N
PART 2 OF 5
GFX_RX0P GFX_RX0N GFX_RX1P GFX_RX1N GFX_RX2P GFX_RX2N GFX_RX3P GFX_RX3N GFX_RX4P GFX_RX4N GFX_RX5P GFX_RX5N GFX_RX6P GFX_RX6N GFX_RX7P GFX_RX7N GFX_RX8P GFX_RX8N GFX_RX9P GFX_RX9N GFX_RX10P GFX_RX10N GFX_RX11P GFX_RX11N GFX_RX12P GFX_RX12N GFX_RX13P GFX_RX13N GFX_RX14P GFX_RX14N GFX_RX15P GFX_RX15N
GPP_RX0P GPP_RX0N
GPP_RX1P GPP_RX1N
GPP_RX2P GPP_RX2N
GPP_RX3P GPP_RX3N
SB_RX0P SB_RX0N
SB_RX1P SB_RX1N
PCEH_ISET PCEH_TXISET
216MSA4ALA12FG RS485M_BGA465
PCIE I/F GFX
PCIE I/F GPP
PCIE I/F SB
GFX_TX0P GFX_TX0N GFX_TX1P GFX_TX1N GFX_TX2P GFX_TX2N GFX_TX3P GFX_TX3N GFX_TX4P GFX_TX4N GFX_TX5P GFX_TX5N GFX_TX6P GFX_TX6N GFX_TX7P GFX_TX7N GFX_TX8P GFX_TX8N GFX_TX9P GFX_TX9N
GFX_TX10P
GFX_TX10N
GFX_TX11P
GFX_TX11N
GFX_TX12P
GFX_TX12N
GFX_TX13P
GFX_TX13N
GFX_TX14P
GFX_TX14N
GFX_TX15P
GFX_TX15N
GPP_TX0P GPP_TX0N
GPP_TX1P GPP_TX1N
GPP_TX2P GPP_TX2N
GPP_TX3P GPP_TX3N
SB_TX0P
SB_TX0N
SB_TX1P
SB_TX1N
PCEH_PCAL
PCEH_NCAL
J1 H2 K2 K1 K3 L3 L1 L2 N2 N1 P2 P1 P3 R3 R1 R2 T2 U1 V2 V1 V3 W3 W1 W2 Y2 AA1 AA2 AB2 AB1 AC1 AE3 AE4
PCIE_LAN_TX_P2
AD8
PCIE_LAN_TX_N2
AE8 AD7
AE7 AD4
AE5 AD5
AD6
SB_TX0P_C
AE9 AD10
AC8 AD9
AD11 AE11
C367 0.1U_0402_16V4Z
SB_TX0N_C
C368 0.1U_0402_16V4Z
SB_TX1P_C
C365 0.1U_0402_16V4Z
SB_TX1N_C
C366 0.1U_0402_16V4Z
R228 150_0402_1%
1 2
R227 100_0402_1%
1 2
C363 0.1U_0402_16V4Z
1 2
C364 0.1U_0402_16V4Z
1 2
C361 0.1U_0402_16V4Z
1 2
C362 0.1U_0402_16V4Z
1 2
1 2 1 2
1 2 1 2
PCIE_LAN_C_TX_P2 PCIE_LAN_C_TX_N2
PCIE_WLAN_C_TX_P1PCIE_WLAN_TX_P1 PCIE_WLAN_C_TX_N1PCIE_WLAN_TX_N1
SB_TX0P SB_TX0N
SB_TX1P SB_TX1N
+1.2V_HT
PCIE_LAN_C_TX_P2 23
PCIE_LAN_C_TX_N2 23
PCIE_WLAN_C_TX_P1 26
PCIE_WLAN_C_TX_N1 26
SB_TX0P 15 SB_TX0N 15
SB_TX1P 15 SB_TX1N 15
H_CLKOP14 H_CLKON14
H_CLKOP04 H_CLKON04
H_CTLOP04 H_CTLON04
+1.2V_HT
H_CADOP15 H_CADON15 H_CADOP14 H_CADON14 H_CADOP13 H_CADON13 H_CADOP12 H_CADON12 H_CADOP11 H_CADON11 H_CADOP10 H_CADON10 H_CADOP9 H_CADON9 H_CADOP8 H_CADON8
H_CADOP7 H_CADON7 H_CADOP6 H_CADON6 H_CADOP5 H_CADON5 H_CADOP4 H_CADON4 H_CADOP3 H_CADON3 H_CADOP2 H_CADON2 H_CADOP1 H_CADON1 H_CADOP0 H_CADON0
R253 49.9_0402_1%
1 2
R249 49.9_0402_1%
1 2
H_CLKOP1
H_CLKON1
H_CLKOP0
H_CLKON0
H_CTLOP0 H_CTLON0
NB1A
R19
HT_RXCAD15P
R18
HT_RXCAD15N
R21
HT_RXCAD14P
R22
HT_RXCAD14N
U22
HT_RXCAD13P
U21
HT_RXCAD13N
U18
HT_RXCAD12P
U19
HT_RXCAD12N
W19
HT_RXCAD11P
W20
HT_RXCAD11N
AC21
HT_RXCAD10P
AB22
HT_RXCAD10N
AB20
HT_RXCAD9P
AA20
HT_RXCAD9N
AA19
HT_RXCAD8P
Y19
HT_RXCAD8N
T24
HT_RXCAD7P
R25
HT_RXCAD7N
U25
HT_RXCAD6P
U24
HT_RXCAD6N
V23
HT_RXCAD5P
U23
HT_RXCAD5N
V24
HT_RXCAD4P
V25
HT_RXCAD4N
AA25
HT_RXCAD3P
AA24
HT_RXCAD3N
AB23
HT_RXCAD2P
AA23
HT_RXCAD2N
AB24
HT_RXCAD1P
AB25
HT_RXCAD1N
AC24
HT_RXCAD0P
AC25
HT_RXCAD0N
W21
HT_RXCLK1P
W22
HT_RXCLK1N
Y24
HT_RXCLK0P
W25
HT_RXCLK0N
P24
HT_RXCTLP
P25
HT_RXCTLN
A24
HT_RXCALP
C24
HT_RXCALN
216MSA4ALA12FG RS485M_BGA465
H_CADIP[0..15] H_CADIN[0..15]
H_CADOP[0..15]
H_CADON[0..15]
HT_TXCTLP HT_TXCTLN
HT_TXCALP HT_TXCALN
P21 P22 P18 P19 M22 M21 M18 M19 L18 L19 G22 G21 J20 J21 F21 F22
N24 N25 L25 M24 K25 K24 J23 K23 G25 H24 F25 F24 E23 F23 E24 E25
L21 L22
J24 J25
N23 P23
C25 D24
PART 1 OF 5
HT_TXCAD15P HT_TXCAD15N HT_TXCAD14P HT_TXCAD14N HT_TXCAD13P HT_TXCAD13N HT_TXCAD12P HT_TXCAD12N HT_TXCAD11P HT_TXCAD11N HT_TXCAD10P HT_TXCAD10N
HT_TXCAD9P HT_TXCAD9N HT_TXCAD8P HT_TXCAD8N
HT_TXCAD7P HT_TXCAD7N HT_TXCAD6P HT_TXCAD6N HT_TXCAD5P HT_TXCAD5N HT_TXCAD4P HT_TXCAD4N HT_TXCAD3P HT_TXCAD3N HT_TXCAD2P HT_TXCAD2N HT_TXCAD1P HT_TXCAD1N HT_TXCAD0P HT_TXCAD0N
HT_TXCLK1P HT_TXCLK1N
HYPER TRANSPORT CPU
I/F
HT_TXCLK0P HT_TXCLK0N
H_CADIP15 H_CADIN15 H_CADIP14 H_CADIN14 H_CADIP13 H_CADIN13 H_CADIP12 H_CADIN12 H_CADIP11 H_CADIN11 H_CADIP10 H_CADIN10 H_CADIP9 H_CADIN9 H_CADIP8 H_CADIN8
H_CADIP7 H_CADIN7 H_CADIP6 H_CADIN6 H_CADIP5 H_CADIN5 H_CADIP4 H_CADIN4 H_CADIP3 H_CADIN3 H_CADIP2 H_CADIN2 H_CADIP1 H_CADIN1 H_CADIP0 H_CADIN0
H_CLKIP1 H_CLKIN1
H_CLKIP0 H_CLKIN0
H_CTLIP0
H_CTLIN0
R245 100_0402_1%
1 2
H_CLKIP1 4 H_CLKIN1 4
H_CLKIP0 4 H_CLKIN0 4
H_CTLIP0 4
H_CTLIN0 4
A A
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2005/12/1 2006/12/01
Deciphered Date
Title
Size Document Number Rev
Custom
2
Date: Sheet
RS480M-HT/VMEM LA-3221P
1
0.1
of
10 43Friday, January 06, 2006
R59 150_0402_1% R58 150_0402_1% R54 150_0402_1%
+3VS
R262
1 2
1 2
4.7K_0402_5%
1 2 1 2 1 2
+1.8VS
+1.8VS
R260
4.7K_0402_5%
EDID_CLK_LCD EDID_DAT_LCD
For Debug
U7
1
A0
2
A1
3
A2
4
VSS
AT24C04N-10SI-2.7_SO8
@
VGA_CRT_R VGA_CRT_G VGA_CRT_B
+1.8VS
L26
1 2
FBML10160808121LMT_0603
100U_D2_10VM
1 2
FBML10160808121LMT_0603
10U_0805_10V4Z
R60
1 2
150_0603_1%
10U_0805_10V4Z
8
VCC
7
WP
6
SCL
5
SDA
1
+
C406
2
L29
1U_0603_10V4Z
1
C429
2
1U_0603_10V4Z
1
C153
2
+3VS +3VS
1
C158
0.1U_0402_16V4Z
2
@
C419
10U_0805_10V4Z
R265
1 2
715_0402_1%
1
C420
2
1
C151
2
@
10U_0805_10V4Z
12
R72 10K_0402_5%
@
EDID_CLK_LCD
1
2
1
2
10U_0805_10V4Z
C152
+1.8VS
+3VS
FBML10160808121LMT_0603
+1.8VS
FBML10160808121LMT_0603
1
C418
2
1U_0603_10V4Z
VGA_CRT_VSYNC14 VGA_CRT_HSYNC14
VGA_DDC_CLK14 VGA_DDC_DATA14
@
C415
1
ALLOW_LDTSTOP15
2
NB_GFX_CLKP13
NB_GFX_CLKN13
R88 10K_0402_5%@ R90 10K_0402_5%@ R91 10K_0402_5%@ R89 10K_0402_5%@ R263 10K_0402_5%@ R264 10K_0402_5%@
BMREQ#15 EDID_CLK_LCD14 EDID_DAT_LCD14
+3VS
R86 4.7K_0402_5%
NB_STRAP_DATA16
FBML10160808121LMT_0603
12
R71 2K_0402_5%
NB_STRAP_DATA
12
R70 2K_0402_5%
@
26 ohm / 100MHz
L13
1 2
0.1U_0402_16V4Z
L31
1 2
0.1U_0402_16V4Z
VGA_CRT_R14 VGA_CRT_G14 VGA_CRT_B14
NB_PWRGD30
HTREFCLK13
NB_REFCLK13
SBLINKCLK13
SBLINKCLK#13
1 2
C414
NB_RST#15,20,23,26,27,40
12 12 12 12 12 12
L12
12
10U_0805_10V4Z
+AVDDI
1
2
10U_0805_10V4Z
12
12
EDID_CLK_LCD EDID_DAT_LCD
12
C155
POWER PLAY HI: 1.2V LOW : 1.0V
+AVDD
1
1
C160
10U_0805_10V4Z
2
2
1
2
C422
+AVDDQ
VGA_CRT_R VGA_CRT_G
VGA_CRT_B VGA_CRT_VSYNC VGA_CRT_HSYNC
VGA_DDC_CLK VGA_DDC_DATA
+NB_PLLVDD
+NB_HTPVDD
NB_RST#
NB_PWRGD NB_LDTSTOP#
ALLOW_LDTSTOP
R25010K_0402_5%
HTREFCLK
NB_REFCLK
NB_GFX_CLKP NB_GFX_CLKN
SBLINKCLK
SBLINKCLK#
DFT_GPIO0 DFT_GPIO1 DFT_GPIO2 DFT_GPIO3 DFT_GPIO4 DFT_GPIO5
BMREQ#
R2614.7K_0402_5%
NB_STRAP_DATA
0.1U_0402_16V4Z
1
1
C146
2
2
GND_LVSSR
C161
R9610K_0402_5%
NB1C
B22
AVDD1
C22
AVDD2
G17
AVSSN1
H17
AVSSN2
A20
AVDDDI
B20
AVSSDI
A21
AVDDQ
A22
AVSSQ
C21
C_R
C20
Y_G
D19
COMP_B
E19
RED
F19
GREEN
G19
BLUE
C6
DACVSYNC
A5
DACHSYNC
B21
RSET
B6
DACSCL
A6
DACSDA
A10
PLLVDD
B10
PLLVSS
B24
HTPVDD
B25
HTPVSS
C10
SYSRESET#
C11
POWERGOOD
C5
LDTSTOP#
B5
ALLOW_LDTSTOP
C23
HTTSTCLK
B23
HTREFCLK
C2
TVCLKIN
B11
OSCIN
A11
OSCOUT
F2
GFX_CLKP
E1
GFX_CLKN
G1
SB_CLKP
G2
SB_CLKN
D6
DFT_GPIO0
D7
DFT_GPIO1
C8
DFT_GPIO2
C7
DFT_GPIO3
B8
DFT_GPIO4
A8
DFT_GPIO5
B2
BMREQb
A2
I2C_CLK
B4
I2C_DATA
AA15
THERMALDIODE_P
AB15
THERMALDIODE_N
C14
TMDS_HPD
B3
DDC_DATA
C3
TESTMODE
A3
STRP_DATA
216MSA4ALA12FG RS485M_BGA465
+LVDDR18A
R92 0_0805_5%
12
LVDSB0+
B14
LDT_STOP#6,16
TXOUT_L0P TXOUT_L0N TXOUT_L1P TXOUT_L1N TXOUT_L2P TXOUT_L2N TXOUT_L3P TXOUT_L3N
TXOUT_U0P
TXOUT_U0N
TXOUT_U1P
TXOUT_U1N
TXOUT_U2P
TXOUT_U2N
TXOUT_U3P
TXOUT_U3N
TXCLK_LP TXCLK_LN TXCLK_UP TXCLK_UN
LPVDD LPVSS
LVDDR18D_1 LVDDR18D_2 LVDDR18A_1 LVDDR18A_2
LVSSR1 LVSSR3 LVSSR5 LVSSR6 LVSSR7 LVSSR8
LVSSR12 LVSSR13
LVDS_DIGON
LVDS_BLON LVDS_BLEN
DVO_D0 DVO_D1 DVO_D2 DVO_D3 DVO_D4 DVO_D5 DVO_D6 DVO_D7 DVO_D8
DVO_D9 DVO_D10 DVO_D11
DVO_VSYNC
DVO_DE
DVO_HSYNC
DVO_IDCKP DVO_IDCKN
PART 3 OF 5
CRT/TVOUT
PLL PWR
PM
CLOCKs
MIS.
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LVDSB0-
B15
LVDSB1+
B13
LVDSB1-
A13
LVDSB2+
H14
LVDSB2-
G14 D17 E17
LVDSA0+
A15
LVDSA0-
B16
LVDSA1+
C17
LVDSA1-
C18
LVDSA2+
B17
LVDSA2-
A17 A18 B18
LVDSBC+
E15
LVDSBC-
D15
LVDSAC+
H15
LVDSAC-
G15 D14
E14
+LVDDR18D
A12 B12 C12
+LVDDR18A
C13 A16
A14 D12 C19 C15 C16
F14 F15
ENVDD
E12
ENABLT
G12 F12
AD14 AD15 AE15 AD16 AE16 AC17 AD18 AE19 AD19 AE20 AD20 AE21
AD13 AC13 AE13 AE17 AD17
+1.8VS
1 2
2
Q11
3 1
MMBT3904_NL_SOT23
2005/12/1 2006/12/01
+LPVDD
SUS_STAT#
R229
470K_0402_5%
R93
10K_0402_5%
R87
LVDSB0+ 14 LVDSB0- 14 LVDSB1+ 14 LVDSB1- 14 LVDSB2+ 14 LVDSB2- 14
LVDSA0+ 14 LVDSA0- 14 LVDSA1+ 14 LVDSA1- 14 LVDSA2+ 14 LVDSA2- 14
LVDSBC+ 14 LVDSBC- 14 LVDSAC+ 14 LVDSAC- 14
0.1U_0402_16V4Z C413
GND_LVSSR
1 2
+3VS
12
1K_0402_5%
NB_LDTSTOP#
0.1U_0402_16V4Z
C138
1
1
10U_0805_10V4Z
2
2
R56
Deciphered Date
1
2
1 2
FBML10160808121LMT_0603
C421
12
1K_0402_5%
+1.8VS
+1.8VS
+1.8VS
C118
330U_D2E_2.5VM
1
+
2
FBML10160808121LMT_0603
1
C139
10U_0805_10V4Z
2
L30
12
R55
1K_0402_5%
@
L8
1 2
ENVDD 14 ENABLT 14,27
RS485M STRAPS(Internal pull up)
DFT_GPIO1:LOAD ROM STRAPS #
*High, LOAD ROM STRAP DISABLE
Low, LOAD ROM STRAP ENABLE
DFT_GPIO2:HT LINK WIDTH
*High, 8 BIT
Low,RESERVED
DFT_GPIO3,4:HT LINK FREQ
GPIO3GPIO4 00 0 1
*
11
DFT_GPIO5:LOAD MEM STRAPS #
*High, LOAD MEM STRAP DISABLE
Low, LOAD MEM STRAP ENABLE
DESCRIPTION RESERVED
1
RESERVED
0
RESERVED
200MHz
Title
Size Document Number Rev
Custom
Date: Sheet
RS480M VIDEO_IF/CLOCK GEN LA-3221P
of
11 43Friday, January 06, 2006
0.1
5
+1.2V_HT
C360
12
+
330U_D2E_2.5VM
+
C35622U_A_4VM
12
+
C35722U_A_4VM
D D
L7
FBML10160808121LMT_0603
1 2
+1.8VS
R67 0_0805_5%
12
+3VS
C C
+1.8VS
B B
C105 1U 6.3V Z Y5V 0402 C102 1U_0402_6.3V4Z C101 1U_0402_6.3V4Z C108 1U_0402_6.3V4Z C369 1U_0402_6.3V4Z
12 12
12
C14122U_1206_10V4Z
12
C1360.1U_0402_16V4Z
R30 0_0805_5%
12
1 2 1 2 1 2 1 2 1 2
NB_VDD18
NB_VDDR3
+1.8VS
+1.2V_HT
C37122U_A_4VM
12
C37022U_A_4VM
12
C1161U_0402_6.3V4Z
12
C1091U_0402_6.3V4Z
12
C1071U_0402_6.3V4Z
12
C1061U_0402_6.3V4Z
12
C1031U_0402_6.3V4Z
12
NB_VDDA18
NB_VDDA12
12
NB_VDDA18
C4164.7U_0805_6.3V6K
C1234.7U_0805_6.3V6K
C1320.1U_0402_16V4Z
12
+
+
4
NB1D
AE24 AD24 AD22 AB17 AE23
W17 AC18 AD21 AC19 AC20 AB19 AD23 AA17 AE25
AC12 AD12 AE12
AC11
Y17
J14 J15
AE2 AB3
U7
W7 AB4 AC3 AD2 AE1
E11 D11
E7 F7 F9
G9
D22
M1
PART 4 OF 5
VDD_HT1 VDD_HT2 VDD_HT5 VDD_HT6 VDD_HT9 VDD_HT10 VDD_HT11 VDD_HT12 VDD_HT13 VDD_HT14 VDD_HT15 VDD_HT16 VDD_HT17 VDD_HT18 VDD_HT19
VDD18_1 VDD18_2
VDDA18_1 VDDA18_2 VDDA18_3 VDDA18_4 VDDA18_5 VDDA18_6 VDDA18_7 VDDA18_8
VDDR3_2 VDDR3_1
VDDR_1 VDDR_2 VDDR_3
VDDA12/VDDPLL_1 VDDA12/VDDPLL_2 VSSA12/VSSPLL_1 VSSA12/VSSPLL_2
VDDHT_PKG VDDA12_PKG1 VDDA12_PKG2
216MSA4ALA12FG RS485M_BGA465
+1.2V_HT
12
L11 FBML10160808121LMT_0603
NB_VDDA12
C1544.7U_0805_6.3V6K
1
2
VDDA_12_1 VDDA_12_2 VDDA_12_3 VDDA_12_4 VDDA_12_5 VDDA_12_6 VDDA_12_7 VDDA_12_8
VDDA_12_9 VDDA_12_10 VDDA_12_11 VDDA_12_12
POWER
C1340.1U_0402_16V4Z
C1440.1U_0402_16V4Z
1
1
2
2
VDDC_1 VDDC_2 VDDC_3 VDDC_4 VDDC_5 VDDC_6 VDDC_7 VDDC_8
VDDC_9 VDDC_10 VDDC_11 VDDC_12 VDDC_13 VDDC_14 VDDC_15 VDDC_16 VDDC_17 VDDC_18 VDDC_19 VDDC_20 VDDC_21 VDDC_22 VDDC_23 VDDC_24 VDDC_25 VDDC_26 VDDC_27 VDDC_28 VDDC_29 VDDC_30 VDDC_31 VDDC_32
3
+1.2V_HT
+
D1 G7 E2 C1 E3 D2 M9 F4 B1 D3 L9 E6
L11 L13 L15 M12 R15 M14 N11 N13 N15 J11 H11 P12 P14 R11 R13 A19 B19 U11 U14 P17 L17 J19 D20 G20 A9 B9 C9 D9 A7 A4 U12 U15
C408 22U_A_4VM C404 22U_A_4VM
+NB_CORE
1
1
1
1
C1450.1U_0402_16V4Z
C1430.1U_0402_16V4Z
C1170.1U_0402_16V4Z
C1420.1U_0402_16V4Z
2
2
2
2
1 2 1 2
1
C1130.1U_0402_16V4Z
2
1
C1120.1U_0402_16V4Z
2
+
12 12 12 12 12
1
C1140.1U_0402_16V4Z
2
C1371U_0402_6.3V4Z C1271U_0402_6.3V4Z C1401U_0402_6.3V4Z C1351U_0402_6.3V4Z C1301U_0402_6.3V4Z
+RS480_COREP
1
JNB1
1
JUMP_43X118
2
2
1
1
C1260.1U_0402_16V4Z
C4170.1U_0402_16V4Z
2
2
A25
F11
D23
E9 G11 Y23 P11 R24
AE18
M15
J22
G23
J12 L12 L14 L20
L23 M11 M20 M23 M25 N12 N14
B7
L24 P13 P20 P15 R12 R14
330U_D2E_2.5VM
1
C128
1
1
C11522U_1206_10V4Z
C12922U_1206_10V4Z
+
2
2
2
W23
AD25
W24
AC23
AC14 AC22
AE22
AE14
AC15
AC16
R20 Y25 U20
H25 Y22 D25
G24 H12 R23
C4
T23 T25
R17 H23 M17 A23
F17
D4
M13
2
NB1E
VSS1
PAR 5 OF 5
VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 VSS42 VSS43 VSS44 VSS45 VSS46 VSS47 VSS48 VSS49 VSS50 VSS51 VSS52 VSS53 VSS54 VSS55 VSS56 VSS57 VSS58 VSS59
216MSA4ALA12FG RS485M_BGA465
GROUND
VSSA1 VSSA2 VSSA3 VSSA4 VSSA5 VSSA6 VSSA7 VSSA8
VSSA9 VSSA10 VSSA11 VSSA12 VSSA13 VSSA14 VSSA15 VSSA16 VSSA17 VSSA18 VSSA19 VSSA20 VSSA21 VSSA22 VSSA23 VSSA24 VSSA25 VSSA26 VSSA27 VSSA28 VSSA29 VSSA30 VSSA31 VSSA32 VSSA33 VSSA34 VSSA35 VSSA36 VSSA93 VSSA94 VSSA95 VSSA37 VSSA38 VSSA39 VSSA40 VSSA41 VSSA42 VSSA43 VSSA44 VSSA45
M3 V12 V11 V14 F3 V15 A1 H1 G3 J2 H3 AE10 J6 AE6 F1 L6 M2 M6 J3 P6 T1 N3 P9 R6 U2 T3 U3 U6 AC4 Y1 Y15 W6 AC2 Y3 Y9 Y11 Y12 Y14 AA3 R9 AD1 AC5 AC6 AC7 AD3 AC9 AC10 G6
1
A A
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2005/12/1 2006/12/01
Deciphered Date
Title
Size Document Number Rev
Custom
2
Date: Sheet
RS480M Power/GND LA-3221P
1
0.1
of
12 43Friday, January 06, 2006
A
B
C
D
E
F
G
H
12
C44610U_0805_10V4Z
1 2
C447 0.1U_0402_16V4Z
1 1
2 2
EXT CLK FREQUENCY SELECT TABLE(MHZ)
3 3
FS2
0 0 0 0 0 1
0 1 0 0 1 1 1 0 0 1 0 1
1 1 1
1 2
C20010U_0805_10V4Z
1 2
C201 0.1U_0402_16V4Z
1 2
R269 10K_0402_5%
CPUFS1
Hi-Z X
180.00
220.00
100.00
133.33
200.00
L32
FBML10160808121LMT_0603
+3VS_CLK_VDD48
+3VS
12
L14
FBML10160808121LMT_0603
+3VS_CLK_VDDREF +3VS_CLK_VDD48
CLK_RESET+3VS_CLK
1 2
SRCCLK
HTTFS0 PCI
[2:1]
Hi-Z Hi-Z100.00 Reserved
100.00
100.00
100.00
36.56 73.12
100.00
66.66 33.33
100.00
66.66 33.33
100.00
66.66 33.33 Normal ATHLON64 operation
10U_0805_10V4Z
USB
48.00
X/6X/3
48.00
30.0060.00
48.00
48.00
48.00
48.00
48.00
+3VS
C423
SMB_CK_CLK18,9,16,26 SMB_CK_DAT18,9,16,26
COMMENT
Reserved Reserved Reserved Reserved Reserved
L27 CHB2012U121_0805
1
2
33P_0402_50V8J
33P_0402_50V8J
1 2
C170
1 2
1 2
C164
+3VS_CLK +3VS_CLK_VDDA
14.31818MHz_20P_1BX14318BE1A
12
Y2
SMB_CK_CLK1 SMB_CCK_CLK1 SMB_CK_DAT1
0.1U_0402_16V4Z
1
1
C438
C434
2
2
10U_0805_10V4Z
+3VS_CLK_VDDREF
XTALIN_CLK XTALOUT_CLK
CLK_RESET
SMB_CCK_DAT1
@
R97
1 2
1M_0402_5%
R104 33_0402_5%
1 2 1 2
R105 33_0402_5%
1 2
R81 475_0603_1%
FS0 FS1 FS2
0.1U_0402_16V4Z
1
C439
2
0.1U_0402_16V4Z
CLKIREF
+3V_CLK (40 mils)
+3VS_CLK
1
C425
54 14 23 28 44
39 60 53
15 22 29 45
38 58
11 61
10
48
5 2
8 1
3 4
9
@
1
C428
2
2
0.1U_0402_16V4Z
U8
VDDCPU VDDSRC VDDSRC VDDSRC VDDSRC VDD48 VDDATIG VDDREF VDDHTT
GNDCPU GNDSRC GNDSRC GNDSRC GNDSRC GND48 GNDATIG GNDREF GNDHTT
X1 X2
RESET_IN# NC
SMBCLK SMBDAT
IREF
ICS951462AGLFT_TSSOP64
12
12
R74
R254
2.2K_0402_5%
2.2K_0402_5%
12
12
R75
R255
@
2.2K_0402_5%
2.2K_0402_5%
0.1U_0402_16V4Z
C424
+3VS_CLK +3VS_CLK
R73
R257
@
1
2
0.1U_0402_16V4Z
CPUCLK8T0 CPUCLK8C0
CPUCLK8T1
CPUCLK8C1
SRCCLKT6
SRCCLKC6 ATIGCLKT0 ATIGCLKC0 ATIGCLKT1 ATIGCLKC1 ATIGCLKT2 ATIGCLKC2 ATIGCLKT3 ATIGCLKC3
SRCCLKT5
SRCCLKC5
SRCCLKT4
SRCCLKC4
SRCCLKT3
SRCCLKC3
SRCCLKT2
SRCCLKC2
SRCCLKT0
SRCCLKC0
SRCCLKT1
SRCCLKC1
SRCCLKT7
SRCCLKC7
CLKREQA#
CLKREQB#
CLKREQC#
48MHz_1 48MHz_0
FS1/REF1 FS0/REF0 FS2/REF2
HTTCLK0
12
2.2K_0402_5%
12
2.2K_0402_5%
0.1U_0402_16V4Z
1
C440
2
50
VDDA
49
GNDA
56 55 52 51
16 17 41 40 37 36 35 34 30 31 18 19 20 21 24 25 26 27 47 46 43 42 12 13
57 32 33
7 6
63 64 62 59
CLKREQA# CLKREQB# CLKREQC#
1
C427
2
CPUCLK0H CPUCLK0L
SBLINKCLK_R SBLINKCLK#_R CLK_GFX_CLKP CLK_GFX_CLKN
CLK_LAN CLK_LAN#
CLK_WCARD CLK_WCARD#
SBSRCCLK_R SBSRCCLK#_R
CLKREQA# CLKREQB# CLKREQC#
CLK_USB
FS1 FS0 FS2
CLK_HTREFCLK
CHECK
一下料號
12
R78
10K_0402_5%
12
R66
@
2.2K_0402_5%
R79 47_0402_1%
1 2
R80 47_0402_1%
1 2
R103 33_0402_5%
1 2
R256 33_0402_5% R76 33_0402_5%
R77 33_0402_5%
1 2
12
R85
R115
10K_0402_5%
12
R84
R114
@
@
2.2K_0402_5%
1
2
C426
0.1U_0402_16V4Z
R108 33_0402_5%
1 2
R109 33_0402_5%
1 2
R82 33_0402_5%
1 2
R83 33_0402_5%
1 2
R110 33_0402_5%
1 2
R111 33_0402_5%
1 2
R112 33_0402_5%
1 2
R113 33_0402_5%
1 2
R106 33_0402_5%
1 2
R107 33_0402_5%
1 2
12
1 2
12
10K_0402_5%
12
2.2K_0402_5%
C412
10U_0805_10V4Z
L25
1 2
FBML10160808121LMT_0603
1
2
SBLINKCLK
SBLINKCLK# NB_GFX_CLKP NB_GFX_CLKN
CLK_PCIE_LAN CLK_PCIE_LAN#
CLK_PCIE_WCARD CLK_PCIE_WCARD#
SBSRCCLK SBSRCCLK#
12
HTREFCLK 11
R64
51.1_0402_1%
USBCLK_EXT NB_REFCLK SB_OSC_INT
CLK_PCIE_WCARD CLK_PCIE_WCARD#
CLK_PCIE_LAN CLK_PCIE_LAN#
SBSRCCLK SBSRCCLK#
SBLINKCLK SBLINKCLK#
NB_GFX_CLKP NB_GFX_CLKN
+3VS+3VS
12
R65 261_0402_1%
CLKREQB# 26
USBCLK_EXT 16
NB_REFCLK 11
SB_OSC_INT 16
C448 10P_0402_25V8K@ C411 10P_0402_25V8K@ C159 10P_0402_25V8K@
R277 49.9_0402_1%
1 2
R278 49.9_0402_1%
1 2
R275 49.9_0402_1%
1 2
R276 49.9_0402_1%
1 2
R271 49.9_0402_1%
1 2
R272 49.9_0402_1%
1 2
R273 49.9_0402_1%
1 2
R274 49.9_0402_1%
1 2
R258 49.9_0402_1%
1 2
R259 49.9_0402_1%
1 2
CPUCLK0_H 6
CPUCLK0_L 6
SBLINKCLK 11 SBLINKCLK# 11 NB_GFX_CLKP 11 NB_GFX_CLKN 11
CLK_PCIE_LAN 23 CLK_PCIE_LAN# 23
CLK_PCIE_WCARD 26 CLK_PCIE_WCARD# 26
SBSRCCLK 15 SBSRCCLK# 15
1 2 1 2 1 2
4 4
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
A
B
C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
D
2005/12/1 2006/12/01
E
Deciphered Date
Title
Size Document Number Rev
Custom
F
Date: Sheet
G
Clock Generator LA-3221P
0.1
of
13 43Friday, January 06, 2006
H
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