A
1 1
B
C
D
E
Compal Confidential
2 2
HCL51 Schematics Document
Intel Yonah Processor with ATIRC410MD/E + DDRII + SB460M
3 3
2006-04-05
REV: 1.0
4 4
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2005/06/20 2006/06/20
Compal Secret Data
Deciphered Date
Title
Size Document Number Rev
B
D
Date: Sheet
Compal Electronics, Inc.
Cover Page
HCL51 LA-3211P
星期二, 四月
11, 2006
E
0.4
of
14 3
A
B
C
D
E
Compal Confidential
Model Name : HCL51
Fan Control
page 35
File Name : LA-3211P
1 1
LCD Conn.
page 18
CRT & TV-out
page 19
LVDS
H_A#(3..31)
Yonah
uPGA-478 Package
PSB
533/667MHz
page 4,5
H_D#(0..63)
ATI RC410MB/D/E
uFCBGA-1466
Mini card
page 25
2 2
IDSEL:AD18
(PIRQF/H#,
GNT#3,
REQ#3)
Mini PCI
socket
(WLAN)
(TV-Tuner)
page 25
3.3V 33 MHz
IDSEL:AD22
(PIRQG#,
GNT#1,
REQ#1)
LAN (100/1000)
RTL8100/8110
page 23
RJ45
page 24
PCI-Express
PCI BUS
IDSEL:AD20
(PIRQE#/B#,
GNT#2,
REQ#2)
CardBus
ENE CB714
Slot 0
page 22
page 21
6 in 1
socket
page 22
page 7,8,9
Alink
ATI SB460M
page 13~~17
Thermal Sensor
F75383M
page 4
Memory BUS(DDRII)
Single Channel
1.8V DDRII 400/533/667
3.3V 48MHz
3.3V 24.576MHz/48Mhz
3.3V ATA-100
S-ATA
IDE
PIDE-HDD
Conn.
page 20
S-ATA HDD
Conn.
page 15
LPC BUS
3 3
RTC CKT.
page 13
Power On/Off CKT.
page 32
DC/DC Interface CKT.
page 36
Power Circuit DC/DC
page 37~~43
4 4
Switch/B Conn.
USB port4, 6
page 31
CD-PLAY/B Conn.
page 31
MEDIA/B Conn.
page 31
Touch Pad
EC I/O Buffer
ENE KB910Q
page 32
page 30
page 29
Int.KBD
page 30
BIOS
page 30
Super I/O
SMsC LPC47N207
page 28
FIR
TFDU6102-TR3
page 28
Clock Generator
ICS951413
page 12
200pin DDRII-SO-DIMM X2
BANK 0, 1, 2, 3
page 10,11
USB conn x4
page 26
USB port 0, 2 on M/B
USB port 4, 6 on PWRBTN/B
HD Audio
SIDE-ODD
page 20
MDC 1.5
Conn
page 31
HDA Codec
ALC883
page 33
Audio AMP
page 34
Phone Jack x3
page 34
Bluetooth
Conn
page 31
USB port1
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2005/06/20 2006/06/20
Compal Secret Data
Deciphered Date
Title
Size Document Number Rev
B
D
Date: Sheet
Compal Electronics, Inc.
Block Diagrams
HCL51 LA-3211P
星期二, 四月
11, 2006
E
0.4
of
24 3
A
Voltage Rails
Power Plane Description
VIN
1 1
2 2
B+
+CPU_CORE
+0.9VS 0.9V switched power rail for DDR terminator
+1.05VS
+1.5VS
+1.8V
+1.8VS 1.8V switched power rail
+2.5VS
+3VALW
+3VS
+5VALW
+5VS
+VSB VSB alw ays on power rail ON ON*
+RTCVCC RTC p o w e r
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OF F.
Adapter power supply (19V)
AC or battery power rail for power circui t.
Core voltage for CPU
1.05V switched power rail
1.5V switched power rail
1.8V power rail for DDR
2.5V switched power rail
3.3V always on power rail
3.3V switched power rail
5V always on power rail
5V switched power rail
External PCI Devices
Device IDSEL# REQ#/GNT# Interrupts
CardBus(SD)
1394
LAN(10/100)
Mini-PCI(WLAN/TV-Tuner)
AD20
AD16 0
AD22
AD18
2
1
3
B
S1 S3 S5
N/A N/A N/A
ON OFF
ON OFF
ON OFF OFF
ON OFF OFF
ON
ON
ON
ON
ON
ON
ON
ON
PIRQE/PIRQH
PIRQA
PIRQG
PIRQF/PORQH
N/A N/A N/A
OFF
OFF
ON
OFF
OFF
OFF
OFF
OFF
ON ON*
OFF
OFF
ON
ON*
OFF
OFF ON
ON ON
C
STATE
Full ON
S1(Power On Suspend)
S3 (Suspend to RAM)
S4 (Suspend to Disk)
S5 (Soft OFF)
SIGNAL
SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock
HIGH HIGH HIGH HIGH
LOW
LOW
LOW
HIGH
LOW LOW LOW
LOW LOW LOW LOW
Board ID / SKU ID Table for AD channel
Vcc 3.3V +/- 5%
Board ID
0
1
2
3
4
5
6
7 NC
100K +/- 5%Ra/Rc/Re
Rb / Rd / Rf V min
0
8.2K +/- 5%
18K +/- 5%
33K +/- 5%
56K +/- 5%
100K +/- 5%
200K +/- 5%
AD_BID
0 V
0.216 V 0.250 V 0.289 V
0.436 V
0.712 V
1.036 V
1.453 V 1.650 V 1.759 V
1.935 V
2.500 V
BOARD ID Table
Board ID
0
1
2
3
4
5
PCB Revision
0.2
0.2
D
ON
ONONON ON
HIGH HIGH HIGH
HIGH
HIGH
ON
ON
ON
ON
V typ
AD_BID
ON
OFF
OFF
V
0 V 0 V
0.503 V
0.819 V
1.185 V 1.264 V
2.200 V
3.300 V
BTO Option Table
BTO Item BOM Structure
LAN(10/100)
LAN(GIGA)
FIR FIR@
MINI CARD1 MINI1@
SATA HDD SATA@
CardReader 4IN1@
ON
OFF
OFF
OFF
AD_BID
0.538 V
0.875 V
2.341 V
3.300 V
E
LOW
OFF
OFF
OFF
max
8100C@
8110S@
6
7
EC SM Bus1 address
3 3
Device
Smart Battery
EEPROM(24C16/02)
GMT G781-1
Address Address
1010 000X b
1001 101X b
EC SM Bus2 address
Device
Fintek F75383M
1001 100X b 0001 011X b
SKU ID Table
SKU ID
0
1
2
3
SKU
4
5
SB460M SM Bus address
Device
Clock Generator
(ICS951413)
DDR DIMM0
DDR DIMM2
4 4
A
Address
1101 001Xb
1001 000Xb
1001 010Xb
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
6
7
2005/06/20 2006/06/20
C
Compal Secret Data
Deciphered Date
D
Title
Size Document Number Rev
B
Date: Sheet
Compal Electronics, Inc.
Notes List
HCL51 LA-3211P
星期二, 四月
11, 2006
E
0.4
of
34 3
5
4
3
2
1
H_A#[3..31] (7)
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
D D
H_REQ#[0..4] (7)
H_ADSTB#0 (7)
C C
B B
B
H_THERMDA, H_THERMDC routing together.
Trace width / Spacing = 10 / 10 mil
A A
For B-0 stepping engineering samples (ES) of Celeron M
processor need to pop this 51 ohm resistor.
H_ADSTB#1 (7)
CLK_CPU_BCLK (12)
CLK_CPU_BCLK# (12)
H_ADS# (7)
H_BNR# (7)
H_BPRI# (7)
H_BR0# (7)
H_DEFER# (7)
H_DRDY# (7)
H_HIT# (7)
H_HITM# (7)
H_LOCK# (7)
H_RS#[0..2] (7)
H_RESET# (7,13)
H_TRDY# (7)
H_DBSY# (7)
H_DPSLP# (13,14)
H_DPRSTP# (42)
H_DPWR# (7)
H_PWRGOOD (13)
H_CPUSLP# (14)
R20
1K_0402_5% @
1 2
1 2
51_0402_1%
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
H_ADSTB#0
H_ADSTB#1
CLK_CPU_BCLK
CLK_CPU_BCLK#
H_ADS#
H_BNR#
H_BPRI#
H_BR0#
H_DEFER#
H_DRDY#
H_HIT#
H_HITM#
H_IERR#
H_LOCK#
H_RESET#
H_RS#0
H_RS#1
H_RS#2
H_TRDY#
ITP_DBRESET#
H_DBSY#
H_DPSLP# H_BR0#
H_DPRSTP#
H_DPWR#
T2 PAD
T3 PAD
PROCHOT#
C
H_PWRGOOD
H_CPUSLP#
ITP_TCK
ITP_TDI
ITP_TDO
TEST1
R22
TEST2
ITP_TMS
ITP_TRST#
THERMDA
THERMDC
H_THERMTRIP#
A
JCPU1A
J4
A3#
L4
A4#
M3
A5#
K5
A6#
M1
A7#
N2
A8#
J1
A9#
N3
A10#
P5
A11#
P2
A12#
L1
A13#
P4
A14#
P1
A15#
R1
A16#
Y2
A17#
U5
A18#
R3
A19#
W6
A20#
U4
A21#
Y5
A22#
U2
A23#
R4
A24#
T5
ADDR GROUP
A25#
T3
A26#
W3
A27#
W5
A28#
Y4
A29#
W2
A30#
Y1
A31#
K3
REQ0#
H2
REQ1#
K2
REQ2#
J3
REQ3#
L5
REQ4#
L2
ADSTB0#
V4
ADSTB1#
A22
BCLK0
A21
F21
D20
AD4
AD3
AD1
AC4
C20
D24
AC2
AC1
D21
AC5
AA6
AB3
C26
D25
AB5
AB6
A24
A25
H1
E2
G5
F1
H5
G6
E4
H4
B1
F3
F4
G3
G2
E1
B5
E5
D6
D7
C7
HOST CLK
BCLK1
ADS#
BNR#
BPRI#
BR0#
DEFER#
DRDY#
HIT#
CONTROL
HITM#
IERR#
LOCK#
RESET#
RS0#
RS1#
RS2#
TRDY#
BPM0#
BPM1#
BPM2#
BPM3#
DBR#
DBSY#
DPSLP#
DPRSTP#
DPWR#
PRDY#
PREQ#
PROCHOT#
PWRGOOD
SLP#
TCK
TDI
TDO
TEST1
TEST2
TMS
TRST#
THERMAL
THERMDA
DIODE
THERMDC
THERMTRIP#
FOX_PZ47903-2741-42_YONAH
YONAH
DATA GROUP
MISC
LEGACY CPU
D10#
D11#
D12#
D13#
D14#
D15#
D16#
D17#
D18#
D19#
D20#
D21#
D22#
D23#
D24#
D25#
D26#
D27#
D28#
D29#
D30#
D31#
D32#
D33#
D34#
D35#
D36#
D37#
D38#
D39#
D40#
D41#
D42#
D43#
D44#
D45#
D46#
D47#
D48#
D49#
D50#
D51#
D52#
D53#
D54#
D55#
D56#
D57#
D58#
D59#
D60#
D61#
D62#
D63#
DINV0#
DINV1#
DINV2#
DINV3#
DSTBN0#
DSTBN1#
DSTBN2#
DSTBN3#
DSTBP0#
DSTBP1#
DSTBP2#
DSTBP3#
A20M#
FERR#
IGNNE#
INIT#
LINT0
LINT1
STPCLK#
SMI#
D0#
D1#
D2#
D3#
D4#
D5#
D6#
D7#
D8#
D9#
F24
E26
H22
F23
G25
E25
E23
K24
G24
J24
J23
H26
F26
K22
H25
N22
K25
P26
R23
L25
L22
L23
M23
P25
P22
P23
T24
R24
L26
T25
N24
AA23
AB24
V24
V26
W25
U23
U25
U22
AB25
W22
Y23
AA26
Y26
Y22
AC26
AA24
AC22
AC23
AB22
AA21
AB21
AC25
AD20
AE22
AF23
AD24
AE21
AD21
AE25
AF25
AF22
AF26
J26
M26
V23
AC20
H23
M24
W24
AD23
G22
N25
Y25
AE24
A6
A5
C4
B3
C6
B4
D5
A3
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20 H_A#23
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3
H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3
H_A20M#
H_FERR#
H_IGNNE#
H_INIT#
H_INTR
0_0402_5%
R25
H_STPCLK#
H_SMI#
1 2
H_NMI
H_DINV#0 (7)
H_DINV#1 (7)
H_DINV#2 (7)
H_DINV#3 (7)
H_A20M# (13)
H_FERR# (13)
H_IGNNE# (13)
H_INIT# (13)
H_INTR (13)
H_NMI (13)
H_STPCLK# (13)
H_SMI# (13)
H_D#0 H_A#3
E22
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
H_D#[0..63] (7)
+CPU_CORE
+1.05VS
1 2
1 2
R1
47K_0402_5% @
C3
1 2
+1.05VS
H_THERMTRIP#
0.1U_0603_25V7K@
56_0402_5%
1 2
R4
R2
47K_0402_5%
1
C
2
B
E
3
MAINPWON (14,36,37,39)
Q1
2SC2411K_SC59
A
+1.05VS
R6
R9
H_DPRSTP#
0_0402_5%
B
H_DSTBN#[0..3] (7)
H_DSTBP#[0..3] (7)
Place Caps Close to CPU Socket
C4 180P_0402_50V8J
1 2
C5 180P_0402_50V8J
1 2
C6 180P_0402_50V8J
1 2
C7 180P_0402_50V8J
1 2
C8 180P_0402_50V8J
1 2
C9 180P_0402_50V8J
1 2
C10 180P_0402_50V8J
1 2
C11 180P_0402_50V8J
1 2
C12 180P_0402_50V8J
1 2
C13 180P_0402_50V8J
1 2
2005/11/01 2006/11/30
470_0402_5%
1 2
1 2
1
C
2
B
E
2SC2411K_SC59
3
Q3
Compal Secret Data
Deciphered Date
R10 470_0402_5%
1 2
H_INIT#
H_A20M#
H_CPUSLP#
H_INTR
H_NMI
H_SMI#
H_STPCLK#
H_IGNNE#
H_PWRGOOD
H_FERR#
H_DPSLP#
R18 390_0402_5%@
R19 390_0402_5%@
R23 200_0402_5%
R24 390_0402_5%@
R26 390_0402_5%@
R28 390_0402_5%@
R30 390_0402_5%@
R31 390_0402_5%@
R32 332_0402_1%
R33 56_0402_5%
R34 200_0402_5%
2
C2
2200P_0402_50V7K
DPRSLPVR (13,42)
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
+3VS
1
THERMDA
2
THERMDC
+1.05VS
R7
75_0402_1%
PROCHOT#
C1
0.1U_0402_16V4Z
1 2
U1
1
VDD
2
3
4 5
1 2
SCLK
D+
SDATA
ALERT#
DTHERM# GND
ADM1032ARMZ-2REEL_MSOP8
F75383M_MSOP8
1 2
R8
56_0402_5%
2
B
8
7
6
+3VALW
1 2
1
C
E
3
1K_0402_5%
R5
Q2
PMBT3904_SOT23
C
H_DPRSTP#
H_RESET#
ITP_TMS
ITP_TDI
ITP_TDO
H_IERR#
+1.05VS
ITP_DBRESET#
ITP_TRST#
ITP_TCK
Compal Electronics, Inc.
Title
Yonah(1/2)-GTLITP
Size Document Number Rev
Custom
HCL51 LA-3211P
, 11, 2006
星期二 四月
Date: Sheet
R12 54.9_0402_1%@
R13 40.2_0402_1%
R15 54.9_0402_1%@
R16 200_0402_5%
R17 56_0402_5%
R27 680_0402_5%
R29 27.4_0402_1%
1 2
1 2
1 2
1 2
R14 150_0402_5%
1 2
1 2
1 2
1 2
R21 150_0402_5%
1 2
1 2
1
EC_SMB_CK2 (28)
EC_SMB_DA2 (28)
H_PROCHOT# (14,42)
+1.05VS
R11 56_0402_5%@
+3VALW
of
44 3
0.4
5
4
3
2
1
Length match within 25 mils
Layout close CPU
20mils
1
2
VCCSENSE
VSSENSE
1
C15
0.01U_0402_16V7K
2
CPU_VID0 (42)
CPU_VID1 (42)
CPU_VID2 (42)
CPU_VID3 (42)
CPU_VID4 (42)
CPU_VID5 (42)
CPU_VID6 (42)
+GTL_REF0
CPU_BSEL0 (12)
CPU_BSEL1 (8,12)
CPU_BSEL2 (12)
H_PSI# (42)
+1.05VS
+CPU_CORE
H_PSI#
CPU_VID0
CPU_VID1
CPU_VID2
CPU_VID3
CPU_VID4
CPU_VID5
CPU_VID6
CPU_BSEL0
CPU_BSEL1
CPU_BSEL2
COMP0
COMP1
COMP2
COMP3
JCPU1B
AF7
VCCSENSE
AE7
VSSSENSE
B26
VCCA
K6
VCCP
J6
VCCP
M6
VCCP
N6
VCCP
YONAH
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
PSI#
VID0
VID1
VID2
VID3
VID4
VID5
VID6
GTLREF
BSEL0
BSEL1
BSEL2
COMP0
COMP1
COMP2
COMP3
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
FOX_PZ47903-2741-42_YONAH
W21
G21
AD6
AE5
AE3
AE2
AD26
AB20
AA20
AF20
AE20
AB18
AB17
AA18
AA17
AD18
AD17
AC18
AC17
AF18
AF17
AA1
AA4
AB2
AA3
K21
M21
N21
T21
R21
V21
AE6
AF5
AF4
AF2
B22
B23
C21
R26
U26
AF1
D22
C23
C24
T22
T6
R6
J21
V6
U1
V1
E7
D2
F6
D3
C1
M4
N5
T2
V3
B2
C3
AB26
VSS
AA25
VSS
AD25
VSS
AE26
VSS
AB23
VSS
AC24
VSS
AF24
VSS
AE23
VSS
AA22
VSS
AD22
VSS
AC21
VSS
AF21
VSS
AB19
VSS
AA19
VSS
AD19
VSS
AC19
VSS
AF19
VSS
AE19
VSS
AB16
VSS
AA16
VSS
AD16
VSS
AC16
VSS
AF16
VSS
AE16
VSS
AB13
VSS
AA14
VSS
AD13
VSS
AC14
VSS
AF13
VSS
AE14
VSS
AB11
VSS
AA11
VSS
AD11
VSS
AC11
VSS
AF11
VSS
AE11
VSS
AB8
VSS
AA8
VSS
AD8
VSS
AC8
VSS
AF8
VSS
AE8
VSS
AA5
VSS
AD5
VSS
AC6
VSS
AF6
VSS
AB4
VSS
AC3
VSS
AF3
VSS
POWER, GROUNG, RESERVED SIGNALS AND NC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS RSVD
AE4
AB1
AA2
AD2
AE1
B6
C5
F5
E6
H6
J5
M5
L6
P6
R5
V5
U6
Y6
A4
D4
E3
H3
G4
K4
L3
P3
N4
T4
U3
Y3
W4
D1
C2
F2
G1 B25
+CPU_CORE
D D
+1.05VS
R_A
1 2
1 2
R37
1K_0402_1%
R_B
2K_0402_1%
R38
+GTL_REF0
VCCSENSE (42)
VSSENSE (42)
R35 100_0402_1%
1 2
R36 100_0402_1%
1 2
+1.5VS
C14
10U_0805_10V4Z
Layout close CPU PIN AD26
0.5 inch (max)
C C
R39 27.4_0402_1%
1 2
R40 54.9_0402_1%
1 2
R41 27.4_0402_1%
1 2
R42 54.9_0402_1%
1 2
CPU_BSEL CPU_BSEL0 CPU_BSEL1
133
166
B B
00
0
1
CPU_BSEL2
1
1
TRACE CLOSELY CPU < 0.5'
COMP0, COMP2 layout : Width 18mils and Space 25mils
COMP1, COMP3 layout : Space 25mils
+CPU_CORE
JCPU1C
AE18
VCC
AE17
VCC
AB15
VCC
AA15
VCC
AD15
VCC
AC15
VCC
AF15
VCC
AE15
VCC
AB14
VCC
AA13
VCC
AD14
VCC
AC13
VCC
AF14
VCC
AE13
VCC
AB12
VCC
AA12
VCC
AD12
VCC
AC12
VCC
AF12
VCC
AE12
VCC
AB10
VCC
AB9
VCC
AA10
VCC
AA9
VCC
AD10
VCC
AD9
VCC
AC10
VCC
AC9
VCC
AF10
VCC
AF9
VCC
AE10
AD7
AC7
POWER, GROUND
VCC
AE9
VCC
AB7
VCC
AA7
VCC
VCC
VCC
B20
VCC
A20
VCC
F20
VCC
E20
VCC
B18
VCC
B17
VCC
A18
VCC
A17
VCC
D18
VCC
D17
VCC
C18
VCC
C17
VCC
F18
VCC
F17
VCC
E18
VCC
E17
VCC
B15
VCC
A15
VCC
D15
VCC
C15
VCC
F15
VCC
E15
VCC
B14
VCC
A13
VCC
D14
VCC
C13
VCC
F14
VCC
E13
VCC
B12
VCC
A12
VCC
D12
VCC
C12
VCC
F12
VCC
E12
VCC
B10
VCC
B9
VCC
A10
VCC
A9
VCC
D10
VCC
D9
VCC
C10
VCC
C9
VCC
F10
VCC
F9
VCC
E10
VCC
E9
VCC
B7
VCC
A7
VCC
F7
VCC
FOX_PZ47903-2741-42_YONAH
YONAH
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
K1
J2
M2
N1
T1
R2
V2
W1
A26
D26
C25
F25
B24
A23
D23
E24
B21
C22
F22
E21
B19
A19
D19
C19
F19
E19
B16
A16
D16
C16
F16
E16
B13
A14
D13
C14
F13
E14
B11
A11
D11
C11
F11
E11
B8
A8
D8
C8
F8
E8
G26
K26
J25
M25
N26
T26
R25
V25
W26
H24
G23
K23
L24
P24
N23
T23
U24
Y24
W23
H21
J22
M22
L21
P21
R22
V22
U21
Y21
A A
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2005/11/01 2006/11/30
Compal Secret Data
Deciphered Date
Compal Electronics, Inc.
Title
Yonah(2/2)-PWR/GND
Size Document Number Rev
Custom
HCL51 LA-3211P 0.4
, 11, 2006
星期二 四月
2
Date: Sheet
1
of
54 3
5
Place these inside
socket cavity on L6
(North side
1
C16
22U_0805_6.3V6M
2
1
C26
22U_0805_6.3V6M
2
1
C36
22U_0805_6.3V6M
2
1
C42
22U_0805_6.3V6M
2
Secondary)
+CPU_CORE
D D
+CPU_CORE
+CPU_CORE
+CPU_CORE
C C
1
C17
22U_0805_6.3V6M
2
1
C27
22U_0805_6.3V6M
2
1
C37
22U_0805_6.3V6M
2
1
C43
22U_0805_6.3V6M
2
4
1
C18
22U_0805_6.3V6M
2
1
C28
22U_0805_6.3V6M
2
1
C38
22U_0805_6.3V6M
2
1
C44
22U_0805_6.3V6M
2
1
C19
22U_0805_6.3V6M
2
1
C29
22U_0805_6.3V6M
2
1
C39
22U_0805_6.3V6M
2
1
C45
22U_0805_6.3V6M
2
1
2
1
2
1
2
1
2
3
C20
22U_0805_6.3V6M
C30
22U_0805_6.3V6M
C40
22U_0805_6.3V6M
C46
22U_0805_6.3V6M
1
C21
22U_0805_6.3V6M
2
1
C31
22U_0805_6.3V6M
2
1
C41
22U_0805_6.3V6M
2
1
C47
22U_0805_6.3V6M
2
1
C22
22U_0805_6.3V6M
2
1
C32
22U_0805_6.3V6M
2
1
2
1
2
22uF 0805 X5R -> 85 degree C
C23
22U_0805_6.3V6M
C33
22U_0805_6.3V6M
2
1
2
1
2
C24
22U_0805_6.3V6M
C34
22U_0805_6.3V6M
1
C25
22U_0805_6.3V6M
2
1
C35
22U_0805_6.3V6M
2
1
High Frequence Decoupling
Near VCORE regulator.
+CPU_CORE
2006/02/13
South Side Secondary
B B
+1.05VS
1
+
C54
2
A A
5
330U_D2E_2.5VM_R9
330U_D2E_2.5VM_R9
1
+
C48
2
9mOhm
7343
PS CAP
1
+
C49
2
330U_D2E_2.5VM_R9
1
C55
2
0.1U_0402_16V4Z
4
330U_D2E_2.5VM_R9
1
+
C50
2
1
2
1
+
C51
@
2
330U_D2E_2.5VM_R9
1
+
C52
@
2
330U_D2E_2.5VM_R9
H=1.9mm H=1.9mm
C56
0.1U_0402_16V4Z
1
C57
2
0.1U_0402_16V4Z
1
C58
2
0.1U_0402_16V4Z
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
330U_D2E_2.5VM_R9
1
C59
2
0.1U_0402_16V4Z
1
+
C53
North Side Secondary
2
1
C60
2
0.1U_0402_16V4Z
2005/11/01 2006/11/30
Compal Secret Data
Deciphered Date
ESR <= 1.5m ohm
Capacitor > 1980uF
Place these inside
socket cavity on L8
(North side
Secondary)
2
Compal Electronics, Inc.
Title
Yonah Bypass
Size Document Number Rev
Custom
HCL51 LA-3211P 0.4
, 11, 2006
星期二 四月
Date: Sheet
1
of
64 3
A
H_A#[3..31] (4)
H_REQ#[0..4] (4)
H_RS#[0..2] (4)
U2A
H_A#3
G28
M28
K29
K30
M30
K27
M29
K26
N28
N25
N24
D25
E11
G22
H26
G27
G30
G29
G26
H28
J28
H25
K28
H29
J29
K24
K25
F29
G25
F26
F28
E29
H27
J26
L28
L29
L26
L25
L27
F25
F24
E23
E25
G24
F23
E27
C11
D23
G23
E26
F22
D26
E24
D11
B11
H22
CPU_A3#
CPU_A4#
CPU_A5#
CPU_A6#
CPU_A7#
CPU_A8#
CPU_A9#
CPU_A10#
CPU_A11#
CPU_A12#
CPU_A13#
CPU_A14#
CPU_A15#
CPU_A16#
CPU_REQ0#
CPU_REQ1#
CPU_REQ2#
CPU_REQ3#
CPU_REQ4#
CPU_ADSTB0#
CPU_A17#
CPU_A18#
CPU_A19#
CPU_A20#
CPU_A21#
CPU_A22#
CPU_A23#
CPU_A24#
CPU_A25#
CPU_A26#
CPU_A27#
CPU_A28#
CPU_A29#
CPU_A30#
CPU_A31#
CPU_ADSTB1#
CPU_ADS#
CPU_BNR#
CPU_BPRI#
CPU_DEFER#
CPU_DRDY#
CPU_DBSY#
CPU_LOCK#
CPU_CPURSET#
CPU_RS2#
CPU_RS1#
CPU_RS0#
CPU_TRDY#
CPU_HIT#
CPU_HITM#
CPU_COMP_N
CPU_COMP_P
CPU_VREF
RESERVED0
RESERVED1
CPU_DPWR#
PART 1 OF
ADDR.
ADDR.
6
GROUP 0
GROUP 1
CPU I/F
CONTROL MISC.
RC410MD
216CPP4AKA21HK_BGA707
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
R47
1 2
R48
1 2
+CPU_VREF
C69
A
1
2
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_RS#2
H_RS#1
H_RS#0
HSCOMP
HRCOMP
1 1
H_ADSTB#0 (4)
2 2
3 3
4 4
+1.05VS
49.9_0402_1%
220P_0402_50V7K
H_ADSTB#1 (4)
H_ADS# (4)
H_BNR# (4)
H_BPRI# (4)
H_DEFER# (4)
H_DRDY# (4)
H_DBSY# (4)
H_LOCK# (4)
H_RESET# (4,13)
H_TRDY# (4)
H_HIT# (4)
H_HITM# (4)
24.9_0402_1%
Place C close
to Ball H22
H_BR0# (4)
H_DPWR# (4)
DATA GROUP
0
CPU_DBI0#
CPU_DSTBN0#
CPU_DSTBP0#
DATA GROUP
1
CPU_DBI1#
CPU_DSTBN1#
CPU_DSTBP1#
DATA GROUP
2
CPU_DBI2#
CPU_DSTBN2#
CPU_DSTBP2#
DATA
GROUP 3
CPU_DBI3#
CPU_DSTBN3#
CPU_DSTBP3#
B
CPU_D0#
CPU_D1#
CPU_D2#
CPU_D3#
CPU_D4#
CPU_D5#
CPU_D6#
CPU_D7#
CPU_D8#
CPU_D9#
CPU_D10#
CPU_D11#
CPU_D12#
CPU_D13#
CPU_D14#
CPU_D15#
CPU_D16#
CPU_D17#
CPU_D18#
CPU_D19#
CPU_D20#
CPU_D21#
CPU_D22#
CPU_D23#
CPU_D24#
CPU_D25#
CPU_D26#
CPU_D27#
CPU_D28#
CPU_D29#
CPU_D30#
CPU_D31#
CPU_D32#
CPU_D33#
CPU_D34#
CPU_D35#
CPU_D36#
CPU_D37#
CPU_D38#
CPU_D39#
CPU_D40#
CPU_D41#
CPU_D42#
CPU_D43#
CPU_D44#
CPU_D45#
CPU_D46#
CPU_D47#
CPU_D48#
CPU_D49#
CPU_D50#
CPU_D51#
CPU_D52#
CPU_D53#
CPU_D54#
CPU_D55#
CPU_D56#
CPU_D57#
CPU_D58#
CPU_D59#
CPU_D60#
CPU_D61#
CPU_D62#
CPU_D63#
CPU_VREF
Trace=12Mil
Space=15Mil
+CPU_VREF
C72
B
H_D#[0..63] (4)
H_DINV#[0..3] (4)
H_DSTBN#[0..3] (4)
H_DSTBP#[0..3] (4)
H_D#0
E28
H_D#1
D28
H_D#2
D29
H_D#3
C29
H_D#4
D30
H_D#5
C30
H_D#6
B29
H_D#7
C28
H_D#8
C26
H_D#9
B25
H_D#10
B27
H_D#11
C25
H_D#12
A27
H_D#13
C24
H_D#14
A24
H_D#15
B26
H_DINV#0
C27
H_DSTBN#0
A28
H_DSTBP#0
B28
H_D#16
C19
H_D#17
C23
H_D#18
C20
H_D#19
C22
H_D#20
B22
H_D#21
B23
H_D#22
C21
H_D#23
B24
H_D#24
E21
H_D#25
B21
H_D#26
B20
H_D#27
G19
H_D#28
F21
H_D#29
B19
H_D#30
E20
H_D#31
D21
H_DINV#1
A21
H_DSTBN#1
D22
H_DSTBP#1
E22
H_D#32
C18
H_D#33
F19
H_D#34
E19
H_D#35
A18
H_D#36
D19
H_D#37
B18
H_D#38
C17
H_D#39
B17
H_D#40
E17
H_D#41
B16
H_D#42
C15
H_D#43
A15
H_D#44
B15
H_D#45
F16
H_D#46
G18
H_D#47
F18
H_DINV#2
C16
H_DSTBN#2
D18
H_DSTBP#2
E18
H_D#48
E16
H_D#49
D16
H_D#50
C14
H_D#51
B14
H_D#52
E15
H_D#53
D15
H_D#54
C13
H_D#55
E14
H_D#56
F13
H_D#57
B13
H_D#58
A12
H_D#59
C12
H_D#60
E12
H_D#61
D13
H_D#62
D12
H_D#63
B12
H_DINV#3
E13
H_DSTBN#3
F15
H_DSTBP#3
G15
+1.05VS
1
2
1U_0402_6.3V4Z
1 2
R49
49.9_0402_1%
1 2
R50
100_0402_1%
+1.2VS
SB_A_RXN0
SB_A_RXP0
SB_A_RXN1
SB_A_RXP1
NB_A_RXN0
NB_A_RXP0
NB_A_RXN1
NB_A_RXP1
C
ATI recommendation R33, R34
Place R
Close to Ball
C64 0.1U_0402_16V7K
C66 0.1U_0402_16V7K
C67 0.1U_0402_16V7K
C68 0.1U_0402_16V7K
CLK_NB_ALINK# (12)
CLK_NB_ALINK (12)
SB_A_RXN[0..3]
SB_A_RXP[0..3]
NB_A_RXN[0..3]
NB_A_RXP[0..3]
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
R43 10K_0402_1%
PCE_RXISET
R44 8.25K_0402_1%
PCE_TXISET
R45 82.5_0402_1%
PCE_NCAL
R46 150_0402_1%
PCE_PCAL
SB_A_RXN[0..3] (13)
SB_A_RXP[0..3] (13)
NB_A_RXN[0..3] (13)
NB_A_RXP[0..3] (13)
10 mils
10 mils
10 mils
10 mils
NB_A_TXN0
NB_A_TXP0
NB_A_TXP1
AJ12
AK13
AG12
AH12
AJ11
AJ10
AK10
AG10
AG9
AF10
AA4
AA5
AB3
AB4
AC5
AC6
AD4
AD5
AK9
AE9
J4
J5
L4
K4
L5
L6
M4
M5
P4
N4
P5
P6
R4
R5
T3
T4
U5
U6
V4
V5
W3
W4
Y5
Y6
L2
K2
U2C
GFX_RX0N
GFX_RX0P
GFX_RX1N
GFX_RX1P
GFX_RX2N
GFX_RX2P
GFX_RX3N
GFX_RX3P
GFX_RX4N
GFX_RX4P
GFX_RX5N
GFX_RX5P
GFX_RX6N
GFX_RX6P
GFX_RX7N
GFX_RX7P
GFX_RX8N
GFX_RX8P
GFX_RX9N
GFX_RX9P
GFX_RX10N
GFX_RX10P
GFX_RX11N
GFX_RX11P
GFX_RX12N
GFX_RX12P
GFX_RX13N
GFX_RX13P
GFX_RX14N
GFX_RX14P
GFX_RX15N
GFX_RX15P
PCE_ISET
PCE_TXISET
PCE_NCAL
PCE_PCAL
SB_TX0N
SB_TX0P
SB_TX1N
SB_TX1P
SB_RX0N
SB_RX0P
SB_RX1N
SB_RX1P
SB_CLKN
SB_CLKP
A-LINK EXPRESS
I/F
216CPP4AKA21HK_BGA707
PCIE_WLAN_TX_P1
D
PART 3 OF
6
PCI EXPRESS
PCI EXPRESS I/F
RC410MD
GPP_TX0N/SB_TX2N
GPP_TX0P/SB_TX2P
GPP_TX1N/SB_TX3N
GPP_TX1P/SB_TX3P
GPP_RX0N/SB_RX2N
GPP_RX0P/SB_RX2P
GPP_RX1N/SB_RX3N
GPP_RX1P/SB_RX3P
C70 0.1U_0402_16V7K
1 2
C71 0.1U_0402_16V7K
1 2
To SB A-PCIE Link
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2005/11/01 2006/11/30
Compal Secret Data
Deciphered Date
D
I/F
GFX_TX0N
GFX_TX0P
GFX_TX1N
GFX_TX1P
GFX_TX2N
GFX_TX2P
GFX_TX3N
GFX_TX3P
GFX_TX4N
GFX_TX4P
GFX_TX5N
GFX_TX5P
GFX_TX6N
GFX_TX6P
GFX_TX7N
GFX_TX7P
GFX_TX8N
GFX_TX8P
GFX_TX9N
GFX_TX9P
GFX_TX10N
GFX_TX10P
GFX_TX11N
GFX_TX11P
GFX_TX12N
GFX_TX12P
GFX_TX13N
GFX_TX13P
GFX_TX14N
GFX_TX14P
GFX_TX15N
GFX_TX15P
GFX_CLKN
GFX_CLKP
GPP_TX2N
GPP_TX2P
GPP_TX3N
GPP_TX3P
GPP_RX2N
GPP_RX2P
GPP_RX3N
GPP_RX3P
E
N2
N1
R2
P2
T1
R1
U2
T2
V1
V2
W2
W1
AA2
Y2
AB1
AA1
AC2
AB2
AD1
AD2
AE2
AE1
AG2
AF2
AH1
AG1
AJ2
AH2
AJ4
AJ3
AJ5
AK4
M1
M2
NB_A_TXN2
AJ9
NB_A_TXP2
AJ8
NB_A_TXN3
AF6
NB_A_TXP3
AE6
PCIE_WLAN_TX_N1
AK6
PCIE_WLAN_TX_P1 NB_A_TXN1
AJ6
AF4
AE4
NB_A_RXN2
AG8
NB_A_RXP2
AF8
NB_A_RXN3
AG7
NB_A_RXP3
AG6
PCIE_WLAN_C_RX_N1
AJ7
PCIE_WLAN_C_RX_P1
AK7
AH4
AG4
PCIE_WLAN_C_TX_N1 PCIE_WLAN_TX_N1
PCIE_WLAN_C_TX_P1
Compal Electronics, Inc.
Title
RC410MD-FSB, PCIE,A-PCIE
Size Document Number Rev
Custom
HCL51 LA-3211P
, 11, 2006
星期二 四月
Date: Sheet
C61 0.1U_0402_16V7K
SB_A_RXN2
1 2
C62 0.1U_0402_16V7K
SB_A_RXP2
1 2
C63 0.1U_0402_16V7K
SB_A_RXN3
1 2
C65 0.1U_0402_16V7K
SB_A_RXP3
1 2
PCIE_WLAN_C_RX_N1 (25)
PCIE_WLAN_C_RX_P1 (25)
PCIE_WLAN_C_TX_N1 (25)
PCIE_WLAN_C_TX_P1 (25)
E
0.4
of
74 3
A
DDR_DQ[0..63]
DDR_DQS[0..7]
DDR_DQS#[0..7]
DDR_DM[0..7]
DDR_SMA[0..17]
1 1
+1.8V
1 2
1
R55
1K_0402_1%
1K_0402_1%
2 2
1 2
R57
2
0.1U_0402_10V6K
1
2
0.1U_0402_10V6K
MEM_VMODE: 1.8V: DDR2
+1.8V
R62
1 2
61.9_0603_1%
R67
1 2
3 3
@
61.9_0603_1%
Place these R and C
close to relative Ball.
1
C76
2
MEM_COMPN
MEM_COMPP
C77
@
0.47U_0603_16V4Z
C74
+DDR_VREF
C75
MEM_CAP1
MEM_CAP2
1
2
0.47U_0603_16V4Z
DDR_DQ[0..63] (10,11)
DDR_DQS[0..7] (10,11)
DDR_DQS#[0..7] (10,11)
DDR_DM[0..7] (10,11)
DDR_SMA[0..17] (10,11)
DDR_SRAS# (10,11)
DDR_SCAS# (10,11)
DDR_SWE# (10,11)
EMC_DDR_CLK0# (10)
EMC_DDR_CLK0 (10)
EMC_DDR_CLK1# (10)
EMC_DDR_CLK1 (10)
EMC_DDR_CLK3# (11)
EMC_DDR_CLK3 (11)
EMC_DDR_CLK4# (11)
EMC_DDR_CLK4 (11)
DDR_SCKE0 (10)
DDR_SCKE1 (10)
DDR_SCKE2 (10,11)
DDR_SCKE3 (10,11)
DDR_SCS#0 (10)
DDR_SCS#1 (10)
DDR_SCS#2 (10,11)
DDR_SCS#3 (10,11)
DDR_ODT0 (10)
DDR_ODT1 (10,11)
DDR_ODT2 (10)
DDR_ODT3 (10,11)
+1.8V
DDR_SMA0
DDR_SMA1
DDR_SMA2
DDR_SMA3
DDR_SMA4
DDR_SMA5
DDR_SMA6
DDR_SMA7
DDR_SMA8
DDR_SMA9
DDR_SMA10
DDR_SMA11
DDR_SMA12
DDR_SMA13
DDR_SMA14
DDR_SMA15
DDR_SMA16
DDR_SMA17
DDR_SCS#0
DDR_SCS#1
DDR_SCS#2
DDR_SCS#3
DDR_ODT0
DDR_ODT1
DDR_ODT2
DDR_ODT3
R60 1K_0402_5%
1 2
MEM_CAP1
MEM_CAP2
MEM_COMPP
MEM_COMPN
+DDR_VREF
DDR_DQS#0
DDR_DQS0
DDR_DQS#1
DDR_DQS1
DDR_DQS#2
DDR_DQS2
DDR_DQS#3
DDR_DQS3
DDR_DQS#4
DDR_DQS4
DDR_DQS#5
DDR_DQS5
DDR_DQS#6
DDR_DQS6
DDR_DQS#7
DDR_DQS7
10mil
10mil
10mil
10mil
20mil
AK27
AJ27
AH26
AJ26
AH25
AJ25
AH24
AH23
AJ24
AJ23
AH27
AH22
AJ22
AF28
AJ21
AG27
AJ28
AH21
AJ29
AG28
AH30
AC26
AC25
AF16
AE16
V29
V30
AC24
AC23
AG17
AF17
W29
W28
AH20
AJ20
AE24
AE21
AH29
AG29
AH28
AF29
AG30
AE28
AC30
Y30
AD28
AJ14
N30
AJ15
AE29
AB27
AH17
AJ18
AF15
AE14
AE22
AF22
AF26
AE25
W26
W27
AB30
AB29
R25
P25
R30
R29
U2B
MEM_A0
MEM_A1
MEM_A2
MEM_A3
MEM_A4
MEM_A5
MEM_A6
MEM_A7
MEM_A8
MEM_A9
MEM_A10
MEM_A11
MEM_A12
MEM_A13
MEM_A14
MEM_A15
MEM_A16
MEM_A17
MEM_RAS#
MEM_CAS#
MEM_WE#
MEM_CK0N
MEM_CK0P
MEM_CK1N
MEM_CK1P
MEM_CK2N
MEM_CK2P
MEM_CK3N
MEM_CK3P
MEM_CK4N
MEM_CK4P
MEM_CK5N
MEM_CK5P
MEM_CKE0
MEM_CKE1
MEM_CKE2
MEM_CKE3
MEM_CS#0
MEM_CS#1
MEM_CS#2
MEM_CS#3
MEM_ODT0
MEM_ODT1
MEM_ODT2/RSV2
MEM_ODT3/RSV3
MEM_VMODE
MEM_CAP1
MEM_CAP2
MEM_COMPP
MEM_COMPN
MEM_VREF
MEM_DQS0N
MEM_DQS0P
MEM_DQS1N
MEM_DQS1P
MEM_DQS2N
MEM_DQS2P
MEM_DQS3N
MEM_DQS3P
MEM_DQS4N
MEM_DQS4P
MEM_DQS5N
MEM_DQS5P
MEM_DQS6N
MEM_DQS6P
MEM_DQS7N
MEM_DQS7P
NB STRAPING PINS
FSB SPEED
BM_REQ#
4 4
EMC_NB_CRT_VSYNC
EMC_NB_CRT_HSYNC
BM_REQ# EMC_NB_CRT_HSYNC EMC_NB_CRT_VSYNC
166MHZ
133MHZ
0
0
@
R70 4.7K_0402_5%
1 2
R71 4.7K_0402_5%
1 2
+3VS
R73 4.7K_0402_5%
1 2
R76
4.7K_0402_5%
2SC2411K_SC59
A
1 2
1 2
1
C
Q5
E
3
1
0
4.7K_0402_5%
R74
2
B
4.7K_0402_5%
+3VS
1
1
R77
1 2
+1.05VS
+1.05VS
1 2
B
ADDRESS
DATA CLK MISC
216CPP4AKA21HK_BGA707
2005/12/21
4.7K_0402_5%
R75
CPU_BSEL1 (5,12)
B
MEM_DQ0
MEM_DQ1
MEM_DQ2
MEM_DQ3
MEM_DQ4
MEM_DQ5
MEM_DQ6
DATA
MEM_DQ7
MEM_DQ8
MEM_DQ9
MEM_DQ10
MEM_DQ11
MEM_DQ12
MEM_DQ13
MEM_DQ14
MEM_DQ15
MEM_DQ16
MEM_DQ17
MEM_DQ18
MEM_DQ19
MEM_DQ20
MEM_DQ21
MEM_DQ22
MEM_DQ23
MEM_DQ24
MEM_DQ25
MEM_DQ26
MEM_DQ27
MEM_DQ28
MEM_DQ29
MEM_DQ30
MEM_DQ31
MEM_DQ32
MEM_DQ33
MEM_DQ34
MEM_DQ35
MEM_DQ36
MEM_DQ37
MEM_DQ38
MEM_DQ39
MEM_DQ40
MEM_DQ41
MEM_DQ42
MEM_DQ43
MEM_DQ44
MEM_DQ45
MEM_DQ46
MEM_DQ47
MEM_DQ48
MEM_DQ49
MEM_DQ50
MEM_DQ51
MEM_DQ52
MEM_DQ53
MEM_DQ54
MEM_DQ55
MEM_DQ56
MEM_DQ57
MEM_DQ58
MEM_DQ59
MEM_DQ60
MEM_DQ61
MEM_DQ62
MEM_DQ63
MEM_DM0
MEM_DM1
MEM_DM2
MEM_DM3
MEM_DM4
MEM_DM5
MEM_DM6
MEM_DM7
STRP_DATA
NB_DDC_CLK
2SC2411K_SC59
PART 2
OF 6
MEMORY I/F
RC410MD
C
DDR_DQ0
AJ16
DDR_DQ1
AH16
DDR_DQ2
AJ19
DDR_DQ3
AH19
DDR_DQ4
AH15
DDR_DQ5
AK16
DDR_DQ6
AH18
DDR_DQ7
AK19
DDR_DQ8
AF13
DDR_DQ9
AF14
DDR_DQ10
AE19
DDR_DQ11
AF19
DDR_DQ12
AE13
DDR_DQ13
AG13
DDR_DQ14
AF18
AE17
AF20
AF21
AG23
AF24
AG19
AG20
AG22
AF23
AD25
AG25
AE27
AD27
AE23
AD24
AE26
AD26
AA25
Y26
W24
U25
AA26
Y25
V26
W25
AC28
AC29
AA29
Y29
AD30
AD29
AA30
Y28
U27
T27
N26
M27
U26
T26
P27
P26
U29
T29
P29
N29
U28
T28
P28
N27
AJ17
AG15
AE20
AF25
Y27
AB28
R26
R28
Q4
DDR_DQ15
DDR_DQ16
DDR_DQ17
DDR_DQ18
DDR_DQ19
DDR_DQ20
DDR_DQ21
DDR_DQ22
DDR_DQ23
DDR_DQ24
DDR_DQ25
DDR_DQ26
DDR_DQ27
DDR_DQ28
DDR_DQ29
DDR_DQ30
DDR_DQ31
DDR_DQ32
DDR_DQ33
DDR_DQ34
DDR_DQ35
DDR_DQ36
DDR_DQ37
DDR_DQ38
DDR_DQ39
DDR_DQ40
DDR_DQ41
DDR_DQ42
DDR_DQ43
DDR_DQ44
DDR_DQ45
DDR_DQ46
DDR_DQ47
DDR_DQ48
DDR_DQ49
DDR_DQ50
DDR_DQ51
DDR_DQ52
DDR_DQ53
DDR_DQ54
DDR_DQ55
DDR_DQ56
DDR_DQ57
DDR_DQ58
DDR_DQ59
DDR_DQ60
DDR_DQ61
DDR_DQ62
DDR_DQ63
DDR_DM0
DDR_DM1
DDR_DM2
DDR_DM3
DDR_DM4
DDR_DM5
DDR_DM6
DDR_DM7
1
C
E
3
4.7K_0402_5%
R68
1 2
4.7K_0402_5%
R69
1 2
@
1 2
2
B
R72
2K_0402_1%
EMC_NB_CRT_HSYNC (19)
EMC_NB_CRT_VSYNC (19)
EMC_CLK_NB_14M (12)
NB_EDID_DATA (18)
+3VS
+3VS
SB_PWRGD# (15)
EMC_CLK_NB_BCLK (12)
EMC_CLK_NB_BCLK# (12)
NB_EDID_CLK (18)
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
1 2
R262 75_0402_1%
1 2
R263 75_0402_1%
1 2
R264 75_0402_1%
R51
1 2
715_0402_1%
NB_DDC_CLK (19)
NB_DDC_DATA (19)
R58
4.7K_0402_5%
R63
1 2
4.7K_0402_5%
R64
1 2
4.7K_0402_5%
R65
1 2
R52
10_0402_5%
NB_EDID_CLK
NB_EDID_DATA
NB_DVI_DDCDATA
STRP_DATA
TESTMODE
1 2
1.8K_0402_5%
NB_EDID_CLK
NB_EDID_DATA
NB_DVI_DDCDATA
RSET
15mil
NB_DDC_CLK
NB_DDC_DATA
C73
1 2
15P_0402_50V8D@
NB_14M
1 2
1 2
R56 10K_0402_5%
EMC_NB_CRT_R (19)
EMC_NB_CRT_G (19)
EMC_NB_CRT_B (19)
Low: Normal Mode(Fixed)
High: Test Mode
2005/12/21
STRP_DATA: DEBUG STRAP
DEFAULT: 1
0: MEMORY CHANNEL STRAPING
1: EEPROM STRAPING
NB_DDC_CLK: CPU VCC SEL
DEFAULT: 1 1: DESKTOP CPU 0: MOBILE CPU
2005/11/01 2006/11/30
Compal Secret Data
U2D
F9
Y
D9
C
E9
COMP
F10
RED
E10
GREEN
D10
BLUE
C3
DACHSYNC
B3
DACVSYNC
B10
RSET
B2
DACSCL
C2
DACSDA
G1
OSCIN
F1
OSCOUT
G2
TVCLKIN
J1
CPU_CLKP
K1
CPU_CLKN
D2
I2C_CLK
C1
I2C_DATA
H3
DDC_DATA
D1
STRP_DATA
C4
TESTMODE
AH13
THERMALDIODE_P
AJ13
THERMALDIODE_N
R66
1 2
4.7K_0402_5%
@
Deciphered Date
D
CRT &
TV I/F
CLK.
GEN.
216CPP4AKA21HK_BGA707
LVDS_ENBKL
LVDS_ENVDD
D
TXOUT_U0N
TXOUT_U0P
TXOUT_U1N
TXOUT_U1P
TXOUT_U2N
TXOUT_U2P
TXOUT_U3N
TXOUT_U3P
PART 4 OF
6
TXOUT_L0N
TXOUT_L0P
TXOUT_L1N
TXOUT_L1P
LVDS
TXOUT_L2N
TXOUT_L2P
TXOUT_L3N
TXOUT_L3P
LVDS_BLON
LVDS_DIGON
RC410MD
NB_PWRGD
LVDS_BLEN
SYSRESET#
SUS_STAT#
POWERGOOD
SUS_STAT#
1
2
Title
Size Document Number Rev
Custom
Date: Sheet
E
EMC_NB_TZOUT0-
B4
EMC_NB_TZOUT0+
A4
EMC_NB_TZOUT1-
B5
EMC_NB_TZOUT1+
C6
EMC_NB_TZOUT2-
B6
EMC_NB_TZOUT2+
A6
B7
A7
EMC_NB_TZCLK-
F7
TXCLK_UN
TXCLK_UP
TXCLK_LN
TXCLK_LP
BMREQ#
TMDS_HPD
+1.8V
EMC_NB_TZCLK+
F8
EMC_NB_TXOUT0-
E5
EMC_NB_TXOUT0+
F5
EMC_NB_TXOUT1-
D5
EMC_NB_TXOUT1+
C5
EMC_NB_TXOUT2-
E6
EMC_NB_TXOUT2+
D6
E7
E8
EMC_NB_TXCLK-
G6
EMC_NB_TXCLK+
F6
LVDS_ENBKL
G3
LVDS_ENVDD
E2
F2
NB_RST#
A3
SUS_STAT#
AH14
NB_PWRGD
E3
BM_REQ#
H2
J2
1 2
R59
10K_0402_5%
R53 4.7K_0402_5%@
1 2
1 2
R54
2006/03/31
R61
220K_0402_1%
D1
1 2
2 1
CH751H-40_SC76
D2
NB_RST#
2 1
CH751H-40_SC76
+3VALW
14 7
U3A
P G
A
O
B
SN74LVC08APW_TSSOP14
+3VALW
14 7
U3B
4
P G
A
O
5
B
SN74LVC08APW_TSSOP14
3
6
ENBKL (28)
NB_ENVDD (18)
Compal Electronics, Inc.
RC410MD-DDR/DISP/MISC
HCL51 LA-3211P
, 11, 2006
星期二 四月
E
EMC_NB_TZOUT0- (18)
EMC_NB_TZOUT0+ (18)
EMC_NB_TZOUT1- (18)
EMC_NB_TZOUT1+ (18)
EMC_NB_TZOUT2- (18)
EMC_NB_TZOUT2+ (18)
EMC_NB_TZCLK- (18)
EMC_NB_TZCLK+ (18)
EMC_NB_TXOUT0- (18)
EMC_NB_TXOUT0+ (18)
EMC_NB_TXOUT1- (18)
EMC_NB_TXOUT1+ (18)
EMC_NB_TXOUT2- (18)
EMC_NB_TXOUT2+ (18)
EMC_NB_TXCLK- (18)
EMC_NB_TXCLK+ (18)
4.7K_0402_5%@
NB_RST# (13)
NB_PWRGD (15)
BM_REQ# (13)
NB_SUS_STAT# (14,29)
of
84 3
0.4
A
C162
C172
1
2
0.1U_0402_16V4Z
+1.2VS
+1.05VS
1
2
0.1U_0402_16V4Z
1
2
0.1U_0402_16V4Z
C188
1
2
0.1U_0402_16V4Z
C133
C135
C137
C155
C158
C159
1 2
C78 10U_0805_10V4Z
1 2
C79 10U_0805_10V4Z
1 2
C82 1U_0402_6.3V4Z
1 2
C85 1U_0402_6.3V4Z
1 2
C88 1U_0402_6.3V4Z
1 2
C90 1U_0402_6.3V4Z
1 2
C92 1U_0402_6.3V4Z
1 1
1 2
C94 1U_0402_6.3V4Z
1 2
C96 1U_0402_6.3V4Z
1 2
C98 1U_0402_6.3V4Z
1 2
C100 1U_0402_6.3V4Z
1 2
C102 1U_0402_6.3V4Z
1 2
C104 1U_0402_6.3V4Z
1 2
C106 1U_0402_6.3V4Z
1 2
C108 1U_0402_6.3V4Z
1 2
C110 1U_0402_6.3V4Z
1 2
C112 1U_0402_6.3V4Z
1 2
C118 10U_0805_10V4Z
1 2
C120 10U_0805_10V4Z
1 2
C122 1U_0402_6.3V4Z
2 2
1 2
C124 1U_0402_6.3V4Z
1 2
C127 1U_0402_6.3V4Z
1 2
C130 1U_0402_6.3V4Z
1 2
C132 1U_0402_6.3V4Z
1 2
C134 1U_0402_6.3V4Z
1 2
C136 1U_0402_6.3V4Z
1 2
C138 1U_0402_6.3V4Z
1 2
C144 1U_0402_6.3V4Z
1 2
C147 1U_0402_6.3V4Z
1 2
C150 1U_0402_6.3V4Z
1 2
C153 1U_0402_6.3V4Z
1 2
C156 1U_0402_6.3V4Z
3 3
+1.8VS
L3
1 2
CHB1608U301_0603
+1.8VS +AVDDDI
L6
1 2
CHB1608U301_0603
C187
C186
4 4
1
2
0.1U_0402_16V4Z
1 2
1 2
1 2
1 2
1 2
1 2
+
1 2
C160
+AVDDQ
1
C163
2
1U_0402_6.3V4Z
1
C173
2
1U_0402_6.3V4Z
1
C189
2
10U_0805_10V4Z
A
10U_0805_10V4Z
10U_0805_10V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
470U_D2_2.5VM
+AVDDDI
2
C164
1
1U_0402_6.3V4Z
2
C174
1
1U_0402_6.3V4Z
+LPVDD
1
1U_0402_6.3V4Z
2
+AVDD
+CPVDD
+MPVDD
C190
+1.2VS
5A
+1.05VS
5A
1
+
2
220U_D2_4VM
H=1.9mm
1 2
CHB2012U170_0805
U2E
M13
VDD_CORE
M15
VDD_CORE
M17
VDD_CORE
M19
VDD_CORE
N12
VDD_CORE
N14
VDD_CORE
N16
VDD_CORE
N18
VDD_CORE
P13
VDD_CORE
P15
VDD_CORE
P17
VDD_CORE
P19
VDD_CORE
R12
VDD_CORE
R14
VDD_CORE
R16
VDD_CORE
R18
VDD_CORE
T13
VDD_CORE
T15
VDD_CORE
T17
VDD_CORE
T19
VDD_CORE
U12
VDD_CORE
U14
VDD_CORE
U16
VDD_CORE
U18
VDD_CORE
V13
VDD_CORE
V15
VDD_CORE
V17
VDD_CORE
V19
VDD_CORE
W12
VDD_CORE
W14
VDD_CORE
W16
VDD_CORE
W18
VDD_CORE
A10
VDD_CPU
F11
VDD_CPU
F12
VDD_CPU
F17
VDD_CPU
G11
VDD_CPU
G12
VDD_CPU
G13
VDD_CPU
G14
VDD_CPU
G16
VDD_CPU
G17
VDD_CPU
G20
VDD_CPU
H11
VDD_CPU
H12
VDD_CPU
H13
VDD_CPU
H14
VDD_CPU
H16
VDD_CPU
H17
VDD_CPU
H19
VDD_CPU
H23
VDD_CPU
H24
VDD_CPU
L23
VDD_CPU
L24
VDD_CPU
N23
VDD_CPU
P23
VDD_CPU
P24
VDD_CPU
C9
AVDD
B8
AVDDQ
D8
AVDDDI
H21
CPVDD
AB26
MPVDD
C165
22U_1206_6.3V6M
L10
2006/01/23
ATI recommend 2.2uF
1
C169
0.1U_0402_16V4Z
2
+1.8VS
CORE
PWR
216CPP4AKA21HK_BGA707
1
C170
2
+1.8VS
1
+
2
B
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
MEM I/F PWR CPU I/F
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
PART 5
OF 6
POWER
RC410MD
PWR
+AVDD
L5
1 2
CHB2012U170_0805
1
C171
1U_0402_6.3V4Z
2
+CPVDD
C191
470U_D2_2.5VM
B
VDD_18
VDD_18
VDD_18
VDD_18
VDDA_12
VDDA_12
VDDA_12
VDDA_12
VDDA_12
VDDA_12
VDDA_12
VDDA_12
VDDA_12
VDDA_12
VDDA_12
VDDA_12
VDDA_12
VDDA_12
VDDA_12
VDDA_12
VDDA_12
VDDA_12
VDDA_18
VDDA_18
VDDA_18
VDDA_18
VDDA_18
VDDA_18
VDDA_18
VDDA_18
VDDA_18
VDDA_18
VDDA_18
VDDR3
VDDR3
LPVDD
LVDDR18D
LVDDR18A
LVDDR18A
PLLVDD
1
2
C182
AB23
AB24
AC13
AC16
AC19
AC21
AC22
AD13
AD16
AD19
AD21
AD22
AD23
AK21
AK24
AK28
T23
T24
V23
V24
Y23
Y24
0.1A
AB22
AB9
J22
J9
AB7
AC7
AC8
AD9
H4
H5
J6
K6
L7
L8
M7
M8
P7
P8
T7
T8
W7
W8
0.75A
AB8
AC10
AC9
AD10
AE11
AF11
AG11
U7
U8
Y7
Y8
0.1A
G4
G5
J8
C7
H7
H8
H10
+3VS
1
C183
2
10U_0805_10V4Z
1U_0402_6.3V4Z
+1.8V
2A
RC_VDD_18
2.25A
RC_VDDA_18
C140 0.1U_0402_16V4Z
C142 1U_0402_6.3V4Z
C145 1U_0402_6.3V4Z
C148 1U_0402_6.3V4Z
C151 1U_0402_6.3V4Z
C154 1U_0402_6.3V4Z
C157 10U_0805_10V4Z
+VDDQ
20mils
+LPVDD
20mils
ATI recommend separate pure power
+PLLVDD
1
C166
10U_0805_10V4Z
2
L9
1 2
CHB1608U301_0603
1
C184
0.1U_0402_16V4Z
2
C80 0.1U_0402_16V4Z
C83 0.1U_0402_16V4Z
C86 0.1U_0402_16V4Z
L1
1 2
CHB1608U301_0603
1 2
C116 1U_0402_6.3V4Z
1 2
C119 1U_0402_6.3V4Z
1 2
C121 1U_0402_6.3V4Z
1 2
C123 1U_0402_6.3V4Z
1 2
C125 10U_0805_10V4Z
1 2
C128 10U_0805_10V4Z
RC_VDDA_12
L2
1 2
CHB1608U301_0603
1 2
1 2
1 2
1 2
1 2
1 2
1 2
20mils
0.1U_0402_16V4Z
1
C167
2
+1.8VS
1
C185
2
1U_0402_6.3V4Z
Security Classification
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
1 2
1 2
1 2
1
C168
0.1U_0402_16V4Z
2
Issued Date
C
+1.8V
+1.8VS
+1.8VS
L4
1 2
CHB2012U170_0805
1
C175
2
10U_0805_10V4Z
C
D
1 2
C81 10U_0805_10V4Z
1 2
C84 10U_0805_10V4Z
1 2
C87 10U_0805_10V4Z
1 2
C89 10U_0805_10V4Z
1 2
C91 1U_0402_6.3V4Z
1 2
C93 1U_0402_6.3V4Z
1 2
C95 1U_0402_6.3V4Z
1 2
C97 1U_0402_6.3V4Z
1 2
C99 1U_0402_6.3V4Z
1 2
C101 1U_0402_6.3V4Z
1 2
C103 1U_0402_6.3V4Z
1 2
C105 1U_0402_6.3V4Z
1 2
C107 1U_0402_6.3V4Z
1 2
C109 1U_0402_6.3V4Z
1 2
C111 1U_0402_6.3V4Z
1 2
C113 1U_0402_6.3V4Z
1 2
C114 1U_0402_6.3V4Z
1 2
C115 1U_0402_6.3V4Z
1 2
C117 1U_0402_6.3V4Z
+1.2VS
1 2
L50 CHB2012U170_0805
1 2
L51 CHB2012U170_0805
C126 10U_0805_10V4Z
1 2
C129 10U_0805_10V4Z
1 2
C131 10U_0805_10V4Z
1 2
C139 1U_0402_6.3V4Z
1 2
C141 1U_0402_6.3V4Z
1 2
C143 1U_0402_6.3V4Z
1 2
C146 1U_0402_6.3V4Z
1 2
C149 1U_0402_6.3V4Z
1 2
C152 1U_0402_6.3V4Z
1 2
+
1 2
470U_D2_2.5VM
C161
2006/01/23
+3VS +VDDQ
Place L close to Ball AB26
Place C between Ball AB26,AA27
L7
1 2
1
2
1U_0402_6.3V4Z
CHB1608U301_0603
1
C176
C177
0.1U_0402_16V4Z
2
2005/11/01 2006/11/30
Compal Secret Data
+1.8VS +MPVDD
1U_0402_6.3V4Z
Deciphered Date
D
AA23
AA24
AA28
AC11
AC12
AC14
AC15
AC17
AC18
AC20
AC27
AD11
AD12
AD14
AD15
AD17
AD18
AD20
AE30
AF12
AF27
AG14
AG16
AG18
AG21
AG24
AG26
AH11
AJ30
AK12
AK15
AK18
AK2
AK22
AK25
AK29
B30
D14
D17
D20
D24
D27
G10
H15
H18
K23
M12
M14
M16
M18
M23
M24
M26
N13
N15
N17
N19
P12
P14
P16
P18
C178
A13
A16
A19
A22
A25
A29
AJ1
D3
D4
F27
F30
J23
J24
J27
J30
U2F
A2
A9
B1
F3
F4
J3
K8
+PLLVDD
1
2
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
E
R13
VSS
R15
VSS
R17
VSS
R19
VSS
R23
VSS
R24
VSS
R27
VSS
T12
VSS
T14
VSS
T16
VSS
T18
VSS
T30
VSS
PART 6 OF
6
GOUND RC410MD
216CPP4AKA21HK_BGA707
L8
1 2
CHB1608U301_0603
1
C179
1U_0402_6.3V4Z
2
1
C180
10U_0805_10V4Z
2
Compal Electronics, Inc.
Title
RC410MB PWR/GND
Size Document Number Rev
Custom
HCL51 LA-3211P
, 11, 2006
星期二 四月
Date: Sheet
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
AVSSN
AVSSQ
AVSSDI
LPVSS
LVSSR
LVSSR
LVSSR
PLLVSS
CPVSS
MPVSS
+1.8VS
1
C181
10U_0805_10V4Z
2
E
U13
U15
U17
U19
U23
U24
V12
V14
V16
V18
V27
V28
W13
W15
W17
W19
W23
W30
AA3
AA7
AA8
AB5
AB6
AC3
AD3
AD7
AD8
AE8
AF3
AF5
AF7
AF9
AG5
AH10
AH3
AH5
AH6
AH7
AH8
AH9
K5
L3
M3
N5
N6
N7
N8
P3
R3
R7
R8
T5
T6
U3
V3
V7
V8
W5
W6
Y3
C10
B9
C8
J7
G7
G8
G9
H9
H20
AA27
0.4
of
94 3
A
+1.8V
1 1
C197 0.1U_0402_16V4Z
C196 0.1U_0402_16V4Z
C195 0.1U_0402_16V4Z
1
1
+
C194
470U_D2_2.5VM
2 2
3 3
4 4
2
2
+0.9VS
C208 0.1U_0402_16V4Z
C207 0.1U_0402_16V4Z
1
1
2
2
Layout Note:
Every four parallel termination resistors with two caps,
one is connected to ground, the other one is connected
between +1.8V and +0.9VS. Need to place each parallel
resistor with one cap to GND and one cap between
+1.8V and +0.9VS
DDR_SCKE3 (8,11)
DDR_SCS#3 (8,11)
2005/12/26
A
1
1
2
2
Layout Note:
Place one cap close to every 2 pullup
resistors terminated to V_DDR_MCH_REF
C210 0.1U_0402_16V4Z
C209 0.1U_0402_16V4Z
1
2
DDR_SMA14
DDR_SMA11
DDR_SCKE3
DDR_SMA5
DDR_SMA2
DDR_SMA12
DDR_SMA17
DDR_SWE#
DDR_SMA3
DDR_SMA10
DDR_SMA16
C211 0.1U_0402_16V4Z
1
1
2
2
1 4
2 3
1 2
1 4
2 3
1 4
2 3
1 4
2 3
1 4
2 3
RP37 56_0404_4P2 R_5%
1 4
DDR_SMA13
2 3
DDR_SCKE0
DDR_SCKE1
DDR_SCS#0
DDR_SCS#1
B
Layout Note:
Place near JDIM1
C199 0.1U_0402_16V4Z
C198 0.1U_0402_16V4Z
1
1
2
2
C212 0.1U_0402_16V4Z
C213 0.1U_0402_16V4Z
1
1
2
2
RP29 56_0404_4P2R_5%
56_0402_5%
R496
RP31 56_0404_4P2R_5%
56_0404_4P2R_5%
RP33
56_0404_4P2R_5%
RP35
RP39
56_0404_4P2R_5%
56_0402_5%
R491
1 2
56_0402_5%
R492
1 2
56_0402_5%
R493
1 2
56_0402_5%
R494
1 2
B
C200 0.1U_0402_16V4Z
1
2
C214 0.1U_0402_16V4Z
1
2
+0.9VS
C225 0.01U_0402_16V7K @
C226 0.01U_0402_16V7K @
C227 0.01U_0402_16V7K @
C228 0.01U_0402_16V7K @
C229 0.01U_0402_16V7K @
C230 0.01U_0402_16V7K @
C231 0.01U_0402_16V7K @
C232 0.01U_0402_16V7K @
C235 0.01U_0402_16V7K @
C201 0.1U_0402_16V4Z
1
2
C215 0.1U_0402_16V4Z
1
2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
R80
1 2
56_0402_5%
C202 0.1U_0402_16V4Z
1
2
C216 0.1U_0402_16V4Z
1
2
+1.8V
1
2
C
C203 0.1U_0402_16V4Z
C204 0.1U_0402_16V4Z
1
1
2
2
C218 0.1U_0402_16V4Z
C217 0.1U_0402_16V4Z
1 2
1 4
2 3
1 4
2 3
1 4
2 3
1 4
2 3
1 4
2 3
1 4
2 3
1 4
2 3
C219 0.1U_0402_16V4Z
1
1
2
2
56_0402_5%
R495
DDR_SCKE2
DDR_SMA6
DDR_SMA7
56_0404_4P2R_5%
RP30
RP32 56_0404_4P2R_5%
DDR_SMA9
DDR_SMA8
DDR_SRAS#
DDR_SMA4
56_0404_4P2R_5%
RP34
RP36 56_0404_4P2R_5%
DDR_SMA0
DDR_SMA1
DDR_SCS#2
DDR_SMA15
56_0404_4P2R_5%
RP38
RP40 56_0404_4P2R_5%
DDR_SCAS# DDR_SCS#3
DDR_ODT2
DDR_ODT3
DDR_ODT1
56_0404_4P2R_5%
RP41
DDR_ODT0
C
C205 0.1U_0402_16V4Z
1
2
C220 0.1U_0402_16V4Z
1
2
R78
1K_0402_1%
+DDR_VREF1
R79
1K_0402_1%
C206 0.1U_0402_16V4Z
1
2
C222 0.1U_0402_16V4Z
C221 0.1U_0402_16V4Z
1
1
2
2
2006/01/23
DDR_SCKE2 (8,11)
DDR_SCS#2 (8,11)
DDR_ODT3 (8,11)
DDR_ODT1 (8,11)
1
2
C223 22U_1206_6.3V6M
D
+1.8V
1 2
1 2
1
2
C224 22U_1206_6.3V6M
2
C192
0.1U_0402_16V4Z
1
C193 0.1U_0402_16V4Z
1
2
DDR_SCKE0 (8)
DDR_SWE# (8,11)
DDR_SCAS# (8,11)
DDR_SCS#1 (8)
DDR_ODT2 (8)
SB_SMDATA (11,12,14,25)
SB_SMCLK (11,12,14,25)
DDR_DQS#6
DDR_DQS6
DDR_DQ50
DDR_DQ55
DDR_DQ60
DDR_DQ57
DDR_DM7
DDR_DQ58
DDR_DQ62
+3VS
E
DDR_DQ8
DDR_DQ10
DDR_DQS#1
DDR_DQS1
DDR_DQ14
DDR_DQ11
DDR_DQ0
DDR_DQ5
DDR_DQS#0
DDR_DQS0
DDR_DQ7
DDR_DQ2
DDR_DQ16
DDR_DQ20
DDR_DQS#2
DDR_DQS2
DDR_DQ23
DDR_DQ22
DDR_DQ25
DDR_DQ28
DDR_DM3
DDR_DQ31
DDR_DQ30
DDR_SCKE0
DDR_SMA17
DDR_SMA12
DDR_SMA9
DDR_SMA8
DDR_SMA5
DDR_SMA3
DDR_SMA1
DDR_SMA10
DDR_SMA15
DDR_SWE#
DDR_SCAS#
DDR_SCS#1
DDR_ODT2
DDR_DQ36
DDR_DQ32
DDR_DQS#4
DDR_DQS4
DDR_DQ39
DDR_DQ34
DDR_DQ41
DDR_DQ45
DDR_DM5
DDR_DQ42
DDR_DQ46
DDR_DQ53
DDR_DQ48
F
+1.8V +1.8V
+DDR_VREF1
Trace=20mil
JP1
1
VREF
3
VSS
5
DQ0
7
DQ1
9
VSS
11
DQS0#
13
DQS0
15
VSS
17
DQ2
19
C233 0.1U_0402_16V4Z
10U_0805_10V6K
1
2
DQ3
21
VSS
23
DQ8
25
DQ9
27
VSS
29
DQS1#
31
DQS1
33
VSS
35
DQ10
37
DQ11
39
VSS
41
VSS
43
DQ16
45
DQ17
47
VSS
49
DQS2#
51
DQS2
53
VSS
55
DQ18
57
DQ19
59
VSS
61
DQ24
63
DQ25
65
VSS
67
DM3
69
NC
71
VSS
73
DQ26
75
DQ27
77
VSS
79
CKE0
81
VDD
83
NC
85
BA2
87
VDD
89
A12
91
A9
93
A8
95
VDD
97
A5
99
A3
101
A1
103
VDD
105
A10/AP
107
BA0
109
WE#
111
VDD
113
CAS#
115
NC/S1#
117
VDD
119
NC/ODT1
121
VSS
123
DQ32
125
DQ33
127
VSS
129
DQS4#
131
DQS4
133
VSS
135
DQ34
137
DQ35
139
VSS
141
DQ40
143
DQ41
145
VSS
147
DM5
149
VSS
151
DQ42
153
DQ43
155
VSS
157
DQ48
159
DQ49
161
VSS
163
NC,TEST
165
VSS
167
DQS6#
169
DQS6
171
VSS
173
DQ50
175
DQ51
177
VSS
179
DQ56
181
DQ57
183
VSS
185
DM7
187
VSS
189
DQ58
191
DQ59
193
VSS
195
SDA
197
SCL
199
VDDSPD
P-TWO_A5692B-A0G16-P
C234
1
2
NC/CKE1
DIMMA
DQ12
DQ13
CK0#
DQ14
DQ15
DQ20
DQ21
DQ22
DQ23
DQ28
DQ29
DQS3#
DQS3
DQ30
DQ31
NC/A15
NC/A14
RAS#
ODT0
NC/A13
DQ36
DQ37
DQ38
DQ39
DQ44
DQ45
DQS5#
DQS5
DQ46
DQ47
DQ52
DQ53
CK1#
DQ54
DQ55
DQ60
DQ61
DQS7#
DQS7
DQ62
DQ63
VSS
DQ4
DQ5
VSS
DM0
VSS
DQ6
DQ7
VSS
VSS
DM1
VSS
CK0
VSS
VSS
VSS
VSS
DM2
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDD
BA1
VDD
VDD
VSS
VSS
DM4
VSS
VSS
VSS
VSS
VSS
VSS
CK1
VSS
DM6
VSS
VSS
VSS
VSS
VSS
SAO
SA1
G
DDR_DQ[0..63]
DDR_DQS[0..7]
DDR_DQS#[0..7]
DDR_DM[0..7]
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
NC
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
A11
92
A7
94
A6
96
98
A4
100
A2
102
A0
104
106
108
110
S0#
112
114
116
118
120
NC
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
DDR_DQ15
DDR_DQ12
DDR_DM1
DDR_DQ9
DDR_DQ13
DDR_DQ1
DDR_DQ4
DDR_DM0
EMC_DDR_CLK1
EMC_DDR_CLK1#
DDR_DQ3
DDR_DQ6
DDR_DQ17
DDR_DQ21
DDR_DM2
DDR_DQ19
DDR_DQ18
DDR_DQ29
DDR_DQ24
DDR_DQS#3
DDR_DQS3
DDR_DQ26
DDR_DQ27
DDR_SCKE1
DDR_SMA14
DDR_SMA11
DDR_SMA7
DDR_SMA6
DDR_SMA4
DDR_SMA2
DDR_SMA0
DDR_SMA16
DDR_SRAS#
DDR_SCS#0
DDR_ODT0
DDR_SMA13
DDR_DQ37
DDR_DQ33
DDR_DM4
DDR_DQ35
DDR_DQ38
DDR_DQ44
DDR_DQ40
DDR_DQS#5
DDR_DQS5
DDR_DQ47
DDR_DQ43
DDR_DQ49
DDR_DQ52
EMC_DDR_CLK0
EMC_DDR_CLK0#
DDR_DM6
DDR_DQ54
DDR_DQ51
DDR_DQ56
DDR_DQ61
DDR_DQS#7
DDR_DQS7
DDR_DQ63
DDR_DQ59
+3VS
DDR_SMA[0..17]
EMC_DDR_CLK1 (8)
EMC_DDR_CLK1# (8)
DDR_SCKE1 (8)
DDR_SRAS# (8,11)
DDR_SCS#0 (8)
DDR_ODT0 (8)
EMC_DDR_CLK0 (8)
EMC_DDR_CLK0# (8)
DDR_DQ[0..63] (8,11)
DDR_DQS[0..7] (8,11)
DDR_DQS#[0..7] (8,11)
DDR_DM[0..7] (8,11)
DDR_SMA[0..17] (8,11)
H
Reverse H9.2
2006/03/27
Security Classific a t i o n
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHE R THIS SHEE T NOR THE INF ORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
D
2005/11/01 2006/11/30
E
Compal Secret Data
Deciphered Date
Title
DDRII-SODIMM2
Size Document Number Rev
Custom
HCL51 LA-3211P
,
星期二 四
11, 2006
F
Date: Sheet
月
G
10 43
H
0.4
of
Compal Electronics, Inc.
A
B
C
D
E
+1.8V +1.8V
+DDR_VREF2
Trace=20mil
JP2
1
VREF
3
C253
VSS
5
DQ0
7
DQ1
9
VSS
11
DQS0#
13
DQS0
15
VSS
17
DQ2
19
DQ3
21
VSS
23
DQ8
25
DQ9
27
VSS
29
DQS1#
31
DQS1
33
VSS
35
DQ10
37
DQ11
39
VSS
41
VSS
43
DQ16
45
DQ17
47
VSS
49
DQS2#
51
DQS2
53
VSS
55
DQ18
57
DQ19
59
VSS
61
DQ24
63
DQ25
65
VSS
67
DM3
69
NC
71
VSS
73
DQ26
75
DQ27
77
VSS
79
CKE0
81
VDD
83
NC
85
BA2
87
VDD
89
A12
91
A9
93
A8
95
VDD
97
A5
99
A3
101
A1
103
VDD
105
A10/AP
107
BA0
109
WE#
111
VDD
113
CAS#
115
NC/S1#
117
VDD
119
NC/ODT1
121
VSS
123
DQ32
125
DQ33
127
VSS
129
DQS4#
131
DQS4
133
VSS
135
DQ34
137
DQ35
139
VSS
141
DQ40
143
DQ41
145
VSS
147
DM5
149
VSS
151
DQ42
153
DQ43
155
VSS
157
DQ48
159
DQ49
161
VSS
163
NC,TEST
165
VSS
167
DQS6#
169
DQS6
171
VSS
173
DQ50
175
DQ51
177
VSS
179
DQ56
181
DQ57
183
VSS
185
DM7
187
VSS
189
DQ58
191
DQ59
193
VSS
195
SDA
197
SCL
199
VDDSPD
PTI_A5652D-A0G16-P
DIMMB
Reverse H5.6
DDR_DQ8
DDR_DQ[0..63] (8,10)
1 1
2 2
3 3
4 4
DDR_DQS[0..7] (8,10)
DDR_DQS#[0..7] (8,10)
DDR_DM[0..7] (8,10)
DDR_SMA[0..17] (8,10)
DDR_DQ[0..63]
DDR_DQS[0..7]
DDR_DQS#[0..7]
DDR_DM[0..7]
DDR_SMA[0..17]
DDR_SCKE2 (8,10)
DDR_SWE# (8,10)
DDR_SCAS# (8,10)
DDR_SCS#3 (8,10)
DDR_ODT3 (8,10)
SB_SMDATA (10,12,14,25)
SB_SMCLK (10,12,14,25)
DDR_DQ10
DDR_DQS#1
DDR_DQS1
DDR_DQ14
DDR_DQ11
DDR_DQ0
DDR_DQ5
DDR_DQS#0
DDR_DQS0
DDR_DQ7 DDR_DQ3
DDR_DQ2 DDR_DQ6
DDR_DQ16
DDR_DQ20
DDR_DQS#2
DDR_DQS2 DDR_DM2
DDR_DQ23
DDR_DQ22
DDR_DQ25
DDR_DQ28
DDR_DM3
DDR_DQ31
DDR_DQ30
DDR_SCKE2
DDR_SMA17
DDR_SMA12
DDR_SMA9
DDR_SMA8
DDR_SMA5
DDR_SMA3
DDR_SMA1
DDR_SMA10
DDR_SMA15
DDR_SWE#
DDR_SCAS#
DDR_SCS#3
DDR_ODT3
DDR_DQ36
DDR_DQ32
DDR_DQS#4
DDR_DQS4
DDR_DQ39
DDR_DQ34
DDR_DQ41
DDR_DQ45
DDR_DM5
DDR_DQ42
DDR_DQ46
DDR_DQ53
DDR_DQ48
DDR_DQS#6
DDR_DQS6
DDR_DQ50
DDR_DQ55
DDR_DQ60
DDR_DQ57
DDR_DM7
DDR_DQ58
DDR_DQ62
+3VS
10U_0805_10V6K
0.1U_0402_16V4Z
C252
1
2
1
2
2006/03/27
A
B
VSS
DQ4
DQ5
VSS
DM0
VSS
DQ6
DQ7
VSS
DQ12
DQ13
VSS
DM1
VSS
CK0
CK0#
VSS
DQ14
DQ15
VSS
VSS
DQ20
DQ21
VSS
DM2
VSS
DQ22
DQ23
VSS
DQ28
DQ29
VSS
DQS3#
DQS3
VSS
DQ30
DQ31
VSS
NC/CKE1
VDD
NC/A15
NC/A14
VDD
VDD
VDD
BA1
RAS#
VDD
ODT0
NC/A13
VDD
VSS
DQ36
DQ37
VSS
DM4
VSS
DQ38
DQ39
VSS
DQ44
DQ45
VSS
DQS5#
DQS5
VSS
DQ46
DQ47
VSS
DQ52
DQ53
VSS
CK1
CK1#
VSS
DM6
VSS
DQ54
DQ55
VSS
DQ60
DQ61
VSS
DQS7#
DQS7
VSS
DQ62
DQ63
VSS
SAO
SA1
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
NC
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
A11
92
A7
94
A6
96
98
A4
100
A2
102
A0
104
106
108
110
S0#
112
114
116
118
120
NC
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
DDR_DQ15
DDR_DQ12
DDR_DM1
DDR_DQ9
DDR_DQ13
DDR_DQ1
DDR_DQ4
DDR_DM0
EMC_DDR_CLK4
EMC_DDR_CLK4#
DDR_DQ17
DDR_DQ21
DDR_DQ19
DDR_DQ18
DDR_DQ29
DDR_DQ24
DDR_DQS#3
DDR_DQS3
DDR_DQ26
DDR_DQ27
DDR_SCKE3
DDR_SMA14
DDR_SMA11
DDR_SMA7
DDR_SMA6
DDR_SMA4
DDR_SMA2
DDR_SMA0
DDR_SMA16
DDR_SRAS#
DDR_SCS#2
DDR_ODT1
DDR_SMA13
DDR_DQ37
DDR_DQ33
DDR_DM4
DDR_DQ35
DDR_DQ38
DDR_DQ44
DDR_DQ40
DDR_DQS#5
DDR_DQS5
DDR_DQ47
DDR_DQ43
DDR_DQ49
DDR_DQ52
EMC_DDR_CLK3
EMC_DDR_CLK3#
DDR_DM6
DDR_DQ54
DDR_DQ51
DDR_DQ56
DDR_DQ61
DDR_DQS#7
DDR_DQS7
DDR_DQ63
DDR_DQ59
EMC_DDR_CLK4 (8)
EMC_DDR_CLK4# (8)
DDR_SCKE3 (8,10)
DDR_SRAS# (8,10)
DDR_SCS#2 (8,10)
DDR_ODT1 (8,10)
EMC_DDR_CLK3 (8)
EMC_DDR_CLK3# (8)
+3VS
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
+1.8V
C236
470U_D2_2.5VM
C237 0.1U_0402_16V4Z
1
2
C238 0.1U_0402_16V4Z
1
2
Compal Secret Data
1
+
2
2005/11/01 2006/11/30
Layout Note:
Place near JDIM1
C240 0.1U_0402_16V4Z
C239 0.1U_0402_16V4Z
1
1
2
2
1K_0402_1%
+DDR_VREF2
1K_0402_1%
Deciphered Date
R81
R82
C241 0.1U_0402_16V4Z
1
2
+1.8V
1 2
1 2
D
C242 0.1U_0402_16V4Z
1
2
C243 0.1U_0402_16V4Z
1
2
1
C250
0.1U_0402_16V4Z
2
1
C251
0.1U_0402_16V4Z
2
C246 0.1U_0402_16V4Z
C244 0.1U_0402_16V4Z
C245 0.1U_0402_16V4Z
1
1
2
2
Title
Size Document Number Rev
Custom
Date: Sheet
C247 0.1U_0402_16V4Z
1
1
2
2
C248 0.1U_0402_16V4Z
1
2
C249 0.1U_0402_16V4Z
1
2
Compal Electronics, Inc.
DDR-II SODIMM1
HCL51 LA-3211P
, 11, 2006
星期二 四月
E
of
11 43
0.4
A
1 1
+3VS
KC FBM-L11-201209-221LMAT_0805
+3VS
+3VS
2 2
Clock Generator
L11
1 2
L12
1 2
CHB1608U301_0603
L14
1 2
CHB1608U301_0603
4.7U_0805_10V4Z
CLK_EN# (42)
+CLK_VDD1
1 2
10K_0402_5%
+CLK_VDD1
C263
R104 0_0402_5%
R109
1
C254
10U_0805_10V4Z
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
C260
10U_0805_10V4Z
2
0.1U_0402_16V4Z
1
2
@
1 2
1 3
D
2
G
S
2N7002_SOT23
0.1U_0402_16V4Z
1
C255
2
1
C261
2
1
C264
2
Q6
1
1
C256
2
2
0.1U_0402_16V4Z
1
C262
0.1U_0402_16V4Z
2
33P_0402_50V8J
33P_0402_50V8J
+CLK_VDD1
CPU_STP# (13)
0.1U_0402_16V4Z
1
C258
C257
2
R113 4.7K_0402_5%
2006/03/03
3 3
B
0.1U_0402_16V4Z
1
C259
2
+3VS
1 2
C267
1 2
C268
Y1
1 2
14.31818MHZ_20P_6X1430004201
1 2
2
C725
33P_0402_50V8J
1
1 2
L13 CHB1608U301_0603
2
2
C266
C265
1
1
10U_0805_10V4Z
EMC_XTALIN_CLK
EMC_XTALOUT_CLK
R111 4.7K_0402_5% @
1 2
SB_SMCLK (10,11,14,25)
SB_SMDATA (10,11,14,25)
C
1- PLACE ALL THE SERIES TERMINATION RESISTORS
AS CLOSE TO CLOCK GEN AS POSSIBLE
2- ROUTE ALL CPUCLK/#, NBCLK/#, ITPCLK/#
AND SCR/# ,AS DIFFERENT PAIR RULE
3- PUT DECOUPLING CAPS CLOSE TO CLOCK GEN
POWER PIN
U4
1 2
R103
1M_0402_5%
@
0.1U_0402_16V4Z
1 2
R122
475_0402_1%
45
VDDCPU
51
VDDPCI
32
VDDATI
35
VDDSRC
14
VDDSRC
21
VDDSRC
3
VDD48
56
VDDREF
39
VDDA
44
GNDCPU
49
GNDPCI
31
GNDATI
36
GNDSRC
26
GNDSRC
20
GNDSRC
15
GNDSRC
5
GND
55
GND
38
GNDA
1
XIN
2
XOUT
6
VTT_PWRGD#/PD
48
CPU_STOP#
7
SCLK
37
IREF
ICS951413CGLFT_TSSOP56
ICS951413
CPUCLKT0
CPUCLKC0
CPUCLKT1
CPUCLKC1
CPUCLKT2_ITP
CPUCLKC2_ITP
SRCCLKT0
SRCCLKC0
ATIGCLKT0
ATIGCLKC0
ATIGCLKT1
ATIGCLKC1
SRCCLKT3
SRCCLKC3
SRCCLKT4
SRCCLKC4
SRCCLKT5
SRCCLKC5
SRCCLKT6
SRCCLKC6
SRCCLKT7
SRCCLKC7
CLKREQA#
CLKREQB#
CK410#/PCICLK0
USB_48MHZ
FS_B/REF1
FS_A/REF0 SDATA
TEST_SEL/REF2
FS_C
47
46
43
42
41
40
34
33
30
29
27
28
24
25
22
23
18
19
16
17
12
13
10
11
50
4
9
53
54 8
52
CPUCLKT0
CPUCLKC0
CPUCLKT1
CPUCLKC1
SRCCLKT0
SRCCLKC0
SRCCLKT3
SRCCLKC3
SRCCLKT5
SRCCLKC5
48M_SB
FS_C
FS_B/REF1
FS_A/REF0
TEST_SEL/REF2
R87 33_0402_5%
1 2
R88 33_0402_5%
1 2
R89 33_0402_5%
1 2
R90 33_0402_5%
1 2
R91 33_0402_5%
1 2
R92 33_0402_5%
1 2
R93 33_0402_5%
1 2
R94 33_0402_5%
1 2
R95 33_0402_5%
1 2
R96 33_0402_5%
1 2
R105
1 2
10K_0402_5%
R108 4.7K_0402_5%
1 2
R110 4.7K_0402_5%
1 2
@
R112 33_0402_5%
1 2
R114 33_0402_5%
1 2
R116 33_0402_5%
1 2
R118 33_0402_5%
1 2
R120 33_0402_5%
1 2
D
R84
R83
1 2
1 2
49.9_0402_1%
CLK_PCIE_MINI1 (25)
R99 49.9_0402_1%
R102 49.9_0402_1%
@
CLK_PCIE_MINI1# (25)
1 2
1 2
R106 10K_0402_5%
+CLK_VDD1
R115 4.7K_0402_5%
1 2
R117 4.7K_0402_5%
1 2
R119 4.7K_0402_5%
1 2
R107 0_0402_5%
R85
49.9_0402_1%
E
R86
1 2
1 2
49.9_0402_1%
49.9_0402_1%
1 2
1 2
R100
R101
49.9_0402_1%
1 2
MINI_CLKREQ#
1 2
EMC_CLK_SB_14M (14)
EMC_CLK_NB_BCLK (8)
EMC_CLK_NB_BCLK# (8)
CLK_CPU_BCLK (4)
CLK_CPU_BCLK# (4)
1 2
1 2
R98
R97
49.9_0402_1%
49.9_0402_1%
49.9_0402_1%
+CLK_VDD1
+CLK_VDD1
MINI1_CLKREQ# (25)
CLK_48M_SB (14)
CLK_SD_48M (21) CLK_OK (14,15)
CPU_BSEL2 (5)
CPU_BSEL1 (5,8)
CPU_BSEL0 (5)
EMC_CLK_NB_14M (8)
CLK_14M_SIO (27)
CLK_SB_ALINK (13)
CLK_SB_ALINK# (13)
CLK_NB_ALINK (7)
CLK_NB_ALINK# (7)
FS_C FS_B FS_A CPU SRC PCI REF USB
10
0
4 4
A
B
1
133.33 100.00 33.33 14.318 48.000
1
0 0
166.66 100.00 33.33 14.318 48.000
1 1
100.00 33.33 14.318 48.000 100.00
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2005/11/01 2006/11/30
Compal Secret Data
Deciphered Date
D
Compal Electronics, Inc.
Title
ClockGen ICS 951413
Size Document Number Rev
Custom
HCL51 LA-3211P
, 11, 2006
星期二 四月
Date: Sheet
E
of
12 43
0.4
+3VS
5
1219 DEL
CLK_SB_ALINK (12)
CLK_SB_ALINK# (12)
C269 0.01U_0402_16V7K
8.2K_1206_8P4R_5%
D D
1 8
2 7
3 6
4 5
8.2K_1206_8P4R_5%
8.2K_1206_8P4R_5%
1 8
2 7
3 6
4 5
8.2K_1206_8P4R_5%
C C
1 8
2 7
3 6
4 5
8.2K_1206_8P4R_5%
8.2K_1206_8P4R_5%
C283 470U_D2_2.5VM
B B
C284 10U_0805_10V4Z
C285 10U_0805_10V4Z
C286 0.1U_0402_16V4Z
C287 0.1U_0402_16V4Z
C288 0.1U_0402_16V4Z
C289 0.1U_0402_16V4Z
C290 0.1U_0402_16V4Z
C291 0.1U_0402_16V4Z
C292 0.1U_0402_16V4Z
C293 0.1U_0402_16V4Z
C294 0.1U_0402_16V4Z
RP10
RP11
RP12
RP13
RP14
RP15
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
4 5
3 6
2 7
1 8
LOCK#
PCI_DEVSEL#
PCI_REQ#1
4 5
PCI_PIRQF#
3 6
PCI_GNT#1
2 7
PCI_GNT#4
1 8
PCI_FRAME#
PCI_STOP#
PCI_GNT#3
PCI_TRDY#
PCI_GNT#0
PCI_REQ#2
PCI_PERR#
PCI_REQ#3
1 8
PCI_REQ#0
2 7
PCI_GNT#2
3 6
PCI_REQ#4
4 5
1 2
+
PCI_PIRQE#
PCI_IRDY#
PCI_PIRQG#
PCI_SERR#
PCI_PIRQH#
NB_A_RXP0 (7)
NB_A_RXN0 (7)
NB_A_RXP1 (7)
NB_A_RXN1 (7)
NB_A_RXP2 (7)
NB_A_RXN2 (7)
NB_A_RXP3 (7)
NB_A_RXN3 (7)
SB_A_RXP0 (7)
SB_A_RXN0 (7)
SB_A_RXP1 (7)
SB_A_RXN1 (7)
SB_A_RXP2 (7)
SB_A_RXN2 (7)
SB_A_RXP3 (7)
SB_A_RXN3 (7)
CHB2012U170_0805
15P_0402_50V8K
+PCIE_VDDR
L16
C278
1 2
1U_0402_6.3V4Z
C279
1 2
10U_0805_10V4Z
C280
1 2
0.1U_0402_10V6K
C297
+1.8VS
+1.8VS
L17
CHB2012U170_0805
1 2
Pull-high on CPU side
CPU_STP# (12)
CPU_STP#
1 2
C270 0.01U_0402_16V7K
1 2
C271 0.01U_0402_16V7K
1 2
C272 0.01U_0402_16V7K
1 2
C273 0.01U_0402_16V7K
1 2
C275 0.01U_0402_16V7K
1 2
C276 0.01U_0402_16V7K
1 2
C277 0.01U_0402_16V7K
1 2
1 2
+PCIE_VDDR
80mA
+PCIE_VDDR
2006/03/03
R155
1 2
20M_0603_5%
EMC_SB_32KH0
1
2
4
Y2
OUT
NC
3
32.768KHZ_12.5P_1TJS125DJ2A073
H_PWRGOOD (4)
H_INTR (4)
H_NMI (4)
H_INIT# (4)
H_SMI# (4)
H_IGNNE# (4)
H_A20M# (4)
H_FERR# (4)
H_STPCLK# (4)
DPRSLPVR (4,42)
H_RESET# (4,7)
PCIE_PVDD
50mil trace width
EMC_SB_32KHI
1
IN
NC
2
EMC_SB_32KH0
2006/03/03
+3VALW
0.1U_0402_16V4Z
C726
14 7
P G
12 13
OI
1 2
U35F
SN74LVC14APWLE_TSSOP14
1
C274
2
5
2N7002_SOT23
H_DPSLP#
Q42
1 3
D
2
G
S
A A
H_DPSLP# (4,14)
R123
8.2K_0402_5%
1 2
A_RST#
SB_A_TXP0
SB_A_TXN0
SB_A_TXP1
SB_A_TXN1
SB_A_TXP2
SB_A_TXN2
SB_A_TXP3
SB_A_TXN3
SB_A_RXP0
SB_A_RXN0
SB_A_RXP1
SB_A_RXN1
SB_A_RXP2
SB_A_RXN2
SB_A_RXP3
SB_A_RXN3
150_0402_1%
R134
R135
150_0402_1%
R137
1 2
4.12K_0402_1%
1
15P_0402_50V8K
C298
2
EMC_SB_32KHI
H_PWRGD
H_A20M#
1 2
R148 0_0402_5%
1 2
R154 0_0402_5%
1 2
D36
2 1
330P_0402_50V7K
CH751H-40_SC76
4
1 2
1 2
R158
20M_0603_5%
1 2
@
215K_0603_1%
R503
4
U5A
AG10
A_RST#
J24
PCIE_RCLKP
J25
PCIE_RCLKN
P29
PCIE_TX0P
P28
PCIE_TX0N
M29
PCIE_TX1P
M28
PCIE_TX1N
K29
PCIE_TX2P
K28
PCIE_TX2N
H29
PCIE_TX3P
H28
PCIE_TX3N
T25
PCIE_RX0P
T26
PCIE_RX0N
T22
PCIE_RX1P
T23
PCIE_RX1N
M25
PCIE_RX2P
M26
PCIE_RX2N
M22
PCIE_RX3P
M23
PCIE_RX3N
E29
PCIE_CALRP
E28
PCIE_CALRN
E27
PCIE_CALI
U29
PCIE_PVDD
U28
NC
F27
PCIE_VDDR_1
F28
PCIE_VDDR_2
F29
PCIE_VDDR_3
G26
PCIE_VDDR_4
G27
PCIE_VDDR_5
G28
PCIE_VDDR_6
G29
PCIE_VDDR_7
J27
PCIE_VDDR_8
J29
PCIE_VDDR_9
L25
PCIE_VDDR_10
L26
PCIE_VDDR_11
L29
PCIE_VDDR_12
N29
PCIE_VDDR_13
D2
X1
C1
X2
AC26
CPU_PG
W26
INTR/LINT0
W24
NMI/LINT1
W25
INIT#
AA24
SMI#
AA23
NC
AA22
IGNNE#
AA26
A20M#
Y27
FERR#
AA25
STPCLK#/ALLOW_LDTSTP
AH9
CPU_STP#/DPSLP_3V#
B24
NC
W23
DPRSLPVR
AC25
LDT_RST#/DPRSTP#/PROCHOT#
218S4RASA11GS SB460_BGA549
CPU_STP#
SB460
Part 1 of 4
PCI EXPRESS INTERFACE
REQ4#/PLL_BP33/PDMA_REQ1#
GNT3#/PLL_BP66/PDMA_GNT0#
GNT4#/PLL_BP50/PDMA_GNT1#
XTAL
CPU
NB_RST# (8)
PCICLK0
PCICLK1
PCICLK2
PCICLK3
PCICLK4
PCICLK5
PCICLK6
PCI CLKS
SPDIF_OUT/GPIO41
PCIRST#
AD0/ROMA18
AD1/ROMA17
AD2/ROMA16
AD3/ROMA15
AD4/ROMA14
AD5/ROMA13
AD6/ROMA12
AD7/ROMA11
AD8/ROMA9
AD9/ROMA8
AD10/ROMA7
AD11/ROMA6
AD12/ROMA5
AD13/ROMA4
AD14/ROMA3
AD15/ROMA2
AD16/ROMD0
AD17/ROMD1
AD18/ROMD2
AD19/ROMD3
AD20/ROMD4
AD21/ROMD5
AD22/ROMD6
AD23/ROMD7
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
CBE0#/ROMA10
CBE1#/ROMA1
CBE2#/ROMWE#
CBE3#
FRAME#
DEVSEL#/ROMA0
PCI INTERFACE
REQ3#/PDMA_REQ0#
LPC
RTC_IRQ#/ACPWR_STRAP
RTC
TRDY#/ROMOE#
PAR/ROMA19
INTE#/GPIO33
INTF#/GPIO34
INTG#/GPIO35
INTH#/GPIO36
+3VS
4
Y
IRDY#
STOP#
PERR#
SERR#
REQ0#
REQ1#
REQ2#
GNT0#
GNT1#
GNT2#
CLKRUN#
LOCK#
LAD0
LAD1
LAD2
LAD3
LFRAME#
LDRQ0#
LDRQ1#
BMREQ#
SERIRQ
RTCCLK
VBAT
RTC_GND
TC7SH08FU_SSOP5
5 3
P G
B
A
3
PCI_AD[0..31] (17,21,23,25,31)
U2
PCI_CLK1_R
T2
PCI_CLK2_R CLK_PCI_LAN
U1
PCI_CLK3_R
V2
PCI_CLK4_R
W3
PCI_CLK5_R CLK_PCI_LPC
U3
PCI_CLK6_R
V1
SPDIF_OUT
T1
PCI_PLTRST#
AJ9
PCI_AD0
W7
PCI_AD1
Y1
PCI_AD2
W8
PCI_AD3
W5
PCI_AD4
AA5
PCI_AD5
Y3
PCI_AD6
AA6
PCI_AD7
AC5
PCI_AD8
AA7
PCI_AD9
AC3
PCI_AD10
AC7
PCI_AD11
AJ7
PCI_AD12
AD4
PCI_AD13
AB11
PCI_AD14
AE6
PCI_AD15
AC9
PCI_AD16
AA3
PCI_AD17
AJ4
PCI_AD18
AB1
PCI_AD19
AH4
PCI_AD20
AB2
PCI_AD21
AJ3
PCI_AD22
AB3
PCI_AD23
AH3
PCI_AD24
AC1
PCI_AD25
AH2
PCI_AD26
AC2
PCI_AD27
AH1
PCI_AD28
AD2
PCI_AD29
AG2
PCI_AD30
AD1
PCI_AD31
AG1
AB9
AF9
AJ5
AG3
PCI_FRAME#
AA2
PCI_DEVSEL#
AH6
PCI_IRDY#
AG5
PCI_TRDY#
AA1
PCI_PAR
AF7
PCI_STOP#
Y2
PCI_PERR#
AG8
PCI_SERR#
AC11
PCI_REQ#0
AJ8
PCI_REQ#1
AE2
PCI_REQ#2
AG9
PCI_REQ#3
AH8
PCI_REQ#4
AH5
PCI_GNT#0
AD11
PCI_GNT#1
AF2
PCI_GNT#2
AH7
PCI_GNT#3
AB12
PCI_GNT#4
AG4
PM_CLKRUN#
AG7
LOCK#
AF6
PCI_PIRQE#
AD3
PCI_PIRQF#
AF1
PCI_PIRQG#
AF4
PCI_PIRQH#
AF3
LPC_AD0
AG24
LPC_AD1
AG25
LPC_AD2
AH24
LPC_AD3
AH25
LPC_FRAME#
AF24
LPC_DRQ0#
AJ24
LPC_DRQ1#
AH26
W22
SERIRQ
AF23
RTC_CLK
D3
F5
E1
+SB_VBAT
D1
R124 22_0402_5%@
1 2
R125 22_0402_5%@
1 2
R127 22_0402_5%
1 2
R128 22_0402_5%@
1 2
R130 22_0402_5%@
1 2
R126 22_0402_5%@
1 2
R129 22_0402_5%@
1 2
R132
1 2
8.2K_0402_5%
SS_DECT (14)
C281
1U_0402_6.3V4Z
PCI_CBE#0 (21,23,25,31)
PCI_CBE#1 (21,23,25,31)
PCI_CBE#2 (21,23,25,31)
PCI_CBE#3 (21,23,25,31)
PCI_FRAME# (21,23,25,31)
PCI_DEVSEL# (21,23,25)
PCI_IRDY# (21,23,25)
PCI_TRDY# (21,23,25,31)
PCI_PAR (21,23,25)
PCI_STOP# (21,23,25)
PCI_PERR# (21,23,25)
PCI_SERR# (21,23,25)
PCI_REQ#1 (23)
PCI_REQ#2 (21)
PCI_REQ#3 (25)
PCI_GNT#1 (23)
PCI_GNT#2 (21)
PCI_GNT#3 (25)
PM_CLKRUN# (23,25,27)
LPC_AD0 (27,28)
LPC_AD1 (27,28)
LPC_AD2 (27,28)
LPC_AD3 (27,28)
LPC_FRAME# (17,27,28)
LPC_DRQ0# (27)
BM_REQ# (8)
SERIRQ (21,27,28)
RTC_CLK (17)
AUTO_ON# (17)
Consider
--connect
RTC_CLK
U37
1
2
to EC
A_RST#
PCI_AD[0..31]
1 2
1 2
10K_0402_5%
FBM-L11-160808-800LMT_0603
1
2
PCI_PIRQE# (21)
PCI_PIRQF# (25)
PCI_PIRQG# (23)
PCI_PIRQH# (21,25)
CLK_PCI_MINI PCI_CLK0_R
CLK_PCI_CB
CLK_PCI3
CLK_PCI_DB
CLK_PCI_SIO
SPDIF_OUT (17)
L15
PCI_CLK3_R
SS_VDD
R141
10K_0402_5%
R145
@
2
+3VS +3VS
1 2
R133
10K_0402_5%
8
1
3
13
9
4
5
1 2
12
PCI_PIRQE#
PCI_PIRQF#
PCI_PIRQG#
PCI_PIRQH#
Close to SB
PIN A2
Layout Note:
1. Under BATT1 battery Body, no Trace and Via
2. BATT1 + - PIN keep out 80mil from other
component ,trace and via
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2005/11/01 2006/11/30
Compal Secret Data
Deciphered Date
2
CLK_PCI_MINI (25)
CLK_PCI_CB (21)
CLK_PCI_LAN (23)
CLK_PCI_DB (31)
CLK_PCI_LPC (28)
CLK_PCI_SIO (27)
EMI 11/15 Modify
U6
DLY CNTRL
CLKIN
VDD
VDD
SSON
SS%
GND
GND
ASM3P623S00EF-16-TR_TSSOP16
+SB_VBAT
C295
1
2
2
CLKOUT1
6
CLKOUT2
7
CLKOUT3
10
CLKOUT4
11
CLKOUT5
14
CLKOUT6
15
CLKOUT7
16
CLKOUT8
Place JOPEN1 close
to DDR-SODIMM
470_0603_5%
R156
1 2
W=20mils
1U_0402_6.3V4Z
1
PCI_CLK0_R
PCI_CLK1_R
PCI_CLK2_R
PCI_CLK3_R
PCI_CLK4_R
PCI_CLK5_R
PCI_CLK6_R
PCI_CLK0_R (17)
PCI_CLK1_R (17)
PCI_CLK2_R (17)
PCI_CLK3_R (17)
PCI_CLK4_R (17)
PCI_CLK5_R (17)
PCI_CLK6_R (17)
2006/03/09
CKO1 CLK_PCI_MINI
R136 39_0402_5%
1 2
CKO2
R138 39_0402_5%
1 2
CKO3
R139 39_0402_5%
1 2
CKO4
R140 39_0402_5%@
1 2
CKO5
R142 39_0402_5%
1 2
CKO6
R143 39_0402_5%
1 2
CKO7
R144 39_0402_5%
1 2
+3VS
C282
5 3
PCI_PLTRST#
R146 0_0402_5%
PCI_PAR
LPC_DRQ0#
SERIRQ
LPC_DRQ1#
10K_1206_8P4R_5%
LPC_AD2
LPC_AD0
LPC_AD3
LPC_AD1
PM_CLKRUN#
RTC Battery
-
+VBAT_JOP
1 2
JOPEN1
1 2
JUMP_43X39@
No short
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet
U7
1
P G
B
2
A
1 2
R147
8.2K_0402_5%
1 2
RP16
4 5
3 6
2 7
1 8
RP17
1 2
R152 4.7K_0402_5%
BATT1
RTCBATT45@
+RTCVCC
470_0603_5%
R157
1 2
PCI_EXP/LPC/RTC
HCL51 LA-3211P 0.4
, 11, 2006
星期二 四月
0.1U_0402_16V4Z
1 2
4
Y
TC7SH08FU_SSOP5@
4 5
3 6
2 7
1 8
100K_1206_8P4R_5%
+
+RTCBATT
1 2
3
1
C296
0.1U_0402_16V4Z
2
CLK_PCI_CB
CLK_PCI3
CLK_PCI_LAN
CLK_PCI_LPC
CLK_PCI_DB
CLK_PCI_SIO
PCI_RST# (15,21,23,25,27,28,31)
+3VS
+RTCBATT
D3
1
BAS40-04_SOT23
2
+CHGRTC
1
13 43
of
+3VALW
D D
R169 4.7K_0402_5%
R170 10K_0402_5%
R171 4.7K_0402_5%
+3VS
R173 10K_0402_5%
R175 10K_0402_5%
R176 10K_0402_5%
R177 10K_0402_5%
+3VS
C C
AZ_BITCLK_HD (32)
AZ_SYNC_HD (32)
AZ_SDOUT_HD (32)
AZ_RST_HD# (32)
AZ_BITCLK_MDC (30)
AZ_SYNC_MDC (30)
AZ_SDOUT_MDC (30)
AZ_RST_MDC# (30)
B B
+3VALW
@
0_0603_5%
R191
1 2
1
C313
@
0.1U_0402_10V6K
A A
2
5
RP18
1 8
2 7
3 6
4 5
10K_1206_8P4R_5%
RP19
1 8
2 7
3 6
4 5
4.7K_1206_8P4R_5%
1 2
1 2
1 2
1 2
1 2
1 2
1 2
R178 2.2K_0402_5%
1 2
R179 2.2K_0402_5%
1 2
10K_1206_8P4R_5%
4 5
3 6
2 7
1 8
RP28
RP21
1 8
2 7
3 6
4 5
10K_1206_8P4R_5%
10K_1206_8P4R_5%
4 5
3 6
2 7
1 8
RP22
1 2
R192
10K_0402_5%
@
R161
1 2
10K_0402_5%
SB_FANOUT0
SB_GPIO31
SB_GPIO13
SB_GPIO14
SS_DECT (13)
SBGPIO40
AZ_BITCLK
SBGPIO44
AZ_SDIN0_MDC
GPIO_M
LDT_PG
AZ_RST
AGP_STP#
R181 33_0402_5%
R183 33_0402_5%
R182 33_0402_5%
R184 33_0402_5%
R185 33_0402_5%
R187 33_0402_5%
R186 33_0402_5%
R188 33_0402_5%
GPIO_M
AZ_RST
X1 48MHZ_4P_FN4800002
4
OUT
VDD
1
GND
OE
@
5
EC_PME#
EC_THERM#
MASTER_RST#
PBTN_OUT#
GPM6#
PCIE_PME#
PM_SLP_S5#
EC_FLASH#
EXTEVENT0#
EC_SWI#
PM_SLP_S3#
MAINPWON_R
AGP_BUSY#
SIO_SMI#
SB_GA20
SB_KBRST#
SB_SMCLK
SB_SMDATA
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
+3VALW
5 3
1
P G
B
2
A
@
3
2
2006/02/07
1
C712
0.1U_0402_10V6K@
2
U32
AZ_RST_MDC#
4
Y
TC7SH08FU_SSOP5
EMC_OSCLIN
MINI_WAKE# (25)
AZ_SDIN3_HD (32)
AZ_SDIN0_MDC (30)
AZ_BITCLK
AZ_SYNC
AZ_SDOUT
AZ_RST
NB_SUS_STAT# (8,29)
EMC_CLK_SB_14M (12)
ACIN (28,36)
2006/01/23
AC_SDOUT (17)
H_DPSLP# (4,13)
4
EC_SWI# (28)
PM_SLP_S3# (28)
PM_SLP_S5# (28)
PBTN_OUT# (28)
SB_PWRGD (15)
H_PROCHOT# (4,42)
1 2
R172 0_0402_5%
EC_RSMRST# (28)
R174
1 2
0_0402_5%
SB_INT_FLASH_SEL (29)
SIDERST# (15)
CLK_OK (12,15)
SB_SPKR (32)
SB_SMCLK (10,11,12,25)
SB_SMDATA (10,11,12,25)
D35
ACIN SB_GPIO9
@
CH751H-40_SC76
EC_SMI# (28)
EC_LID_OUT# (28)
USB_OC2# (26)
EC_FLASH# (29)
EC_SCI# (28)
R488 10K_0402_5%
1 2
AC_SDOUT
AZ_SDIN3_HD
AZ_SDIN0_MDC
R189 0_0402_5%
2006/03/06
R149
EC_THERM# (28)
H_CPUSLP# (4)
MAINPWON_R
4
EC_SWI#
EXTEVENT0#
PM_SLP_S3#
PM_SLP_S5#
PBTN_OUT#
1 2
R166 0_0402_5%
R167 10K_0402_5%
1 2
R168 10K_0402_5%
1 2
SB_GA20
SB_KBRST#
EC_PME#
SIO_SMI#
MASTER_RST#
PCIE_PME#
GPM6#
MAINPWON_R
EC_RSMRST#
SB_14M
1
C299
15P_0402_50V8D@
2
SB_INT_FLASH_SEL
AGP_STP#
AGP_BUSY#
SPKR
SB_SMCLK
SB_SMDATA
2 1
GPIO_M
LDT_PG
EC_SMI#
USB_OC6#
AZ_RST
USB_OC4#
EC_LID_OUT#
USB_OC2#
EC_FLASH#
EC_SCI#
AZ_BITCLK
AZ_SDOUT
AZ_SYNC
R486
AC_BITCLK
1 2
10K_0402_5%
1 2
0_0402_5%@
1 2
SBGPIO44
SBGPIO40
AC_RST
1 2
R487 10K_0402_5%
SB_FANOUT0
SB_GPIO31
SB_GPIO13
SB_GPIO14
EC_THERM#
SB_GA20
SB_KBRST#
CH751H-40_SC76
2 1
D6
2 1
1 2
2 1
3
2005/12/22
U5D
Part 4 of 4
USB_RCOMP
USB_ATEST1
USB_ATEST0
USB_HSDP7+
USB_HSDM7-
USB_HSDP6+
USB_HSDM6-
USB_HSDP5+
USB_HSDM5-
USB_HSDP4+
USB INTERFACE
USB_HSDM4USB_HSDP3+
USB_HSDM3USB_HSDP2+
USB_HSDM2USB_HSDP1+
USB_HSDM1USB_HSDP0+
USB_HSDM0-
AVDDTX_0
AVDDTX_1
AVDDTX_2
AVDDTX_3
AVDDTX_4
AVDDRX_0
AVDDRX_1
AVDDRX_2
AVDDRX_3
AVDDRX_4
AVSS_USB_1
AVSS_USB_2
AVSS_USB_3
AVSS_USB_4
AVSS_USB_5
AVSS_USB_6
AVSS_USB_7
AVSS_USB_8
AVSS_USB_9
AVSS_USB_10
AVSS_USB_11
AVSS_USB_12
USB PWR
AVSS_USB_13
AVSS_USB_14
AVSS_USB_15
AVSS_USB_16
AVSS_USB_17
AVSS_USB_18
AVSS_USB_19
AVSS_USB_20
AVSS_USB_21
AVSS_USB_23
AVSS_USB_24
AVSS_USB_25
AVSS_USB_26
AVSS_USB_27
AVSS_USB_28
AVSS_USB_29
AVSS_USB_30
AVSS_USB_31
AVSS_USB_32
AVSS_USB_33
2005/11/01 2006/11/30
OSC / RST
GATEA20
EC_KBRST#
SB460
ACPI / WAKE UP EVENTS
GPIO
USB OC
AC97 AZALIA
EC_GA20 (28)
EC_KBRST# (28)
MAINPWON (4,36,37,39)
A3
PCI_PME#/GEVENT4#
B2
RI#/EXTEVNT0#
F7
SLP_S3#
A5
SLP_S5#
E3
PWR_BTN#
B5
PWR_GOOD
B3
SUS_STAT#
F9
NC
E9
TEST1
G9
TEST0
AF26
GA20IN
AG26
KBRST#
D7
LPC_PME#/GEVENT3#
C25
LPC_SMI#/EXTEVNT1#
D9
S3_STATE/GEVENT5#
F4
SYS_RESET#/GPM7#
E7
WAKE#/GEVENT8#
C2
BLINK/GPM6#
G7
SMBALERT#/THRMTRIP#/GEVENT2#
E2
RSMRST#
B23
14M_OSC
C28
NC
A26
ROM_CS#/GPIO1
B29
GHI#/GPIO6
A23
VGATE/GPIO7
B27
GPIO4
D23
GPIO5
B26
SPKR/GPIO2
C27
SCL0/GPOC0#
B28
SDA0/GPOC1#
C3
NC
F3
NC
D26
DDC1_SCL/GPIO9
C26
DDC1_SDA/GPIO8
A27
LDT_PG/SSMUXSEL/GPIO0
A4
NC
C6
NC
C5
NC
C4
USB_OC7#/GEVENT7#
B4
USB_OC6#/GEVENT6#
B6
USB_OC5#/AZ_RST#/GPM5#
A6
USB_OC4#/GPM4#
C8
USB_OC3#/GPM3#
C7
USB_OC2#/FANOUT1/LLB#/GPM2#
B8
USB_OC1#/GPM1#
A8
USB_OC0#/GPM0#
N2
AZ_BITCLK
M2
AZ_SDOUT
K2
NC
L3
AZ_SYNC
K3
NC
L1
AC_BITCLK/GPIO38
L2
AC_SDOUT/GPIO39
L4
ACZ_SDIN0/GPIO42
J2
ACZ_SDIN1/GPIO43
J4
ACZ_SDIN2/GPIO44
M3
AC_SYNC/GPIO40
L5
AC_RST#/GPIO45
E23
FANOUT0/GPIO3
AC21
GPIO31
AD7
GPIO13
AE7
DPSLP_OD#/GPIO37
AA4 F19
GPIO14 AVSS_USB_22
T4
TALERT#/GPIO10
D4
SLP#/LDT_STP#
AB19
NC
218S4RASA11GS SB460_BGA549
D4
CH751H-40_SC76@
R190 0_0402_5%
CH751H-40_SC76@
D5
1 2
R194 0_0402_5%
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
A17
USBCLK
AVDDC
AVSSC
USB_RCOMP
A14
A11
A10
H12
NC
G12
NC
E12
NC
D12
NC
E14
D14
G14
H14
D16
E16
D18
E18
G16
H16
G18
H18
D19
E19
G19
H19
B9
B11
B13
B16
B18
A9
B10
B12
B14
B17
A12
A13
A16
C9
C10
C11
C12
C13
C14
C16
C17
C18
C19
C20
D11
D21
E11
E21
F11
F12
F14
F16
F18
F21
G11
G21
H11
H21
J11
J12
J14
J16
J18
J19
Compal Secret Data
Deciphered Date
2
@
R163
CLK_48M_SB
EMC_OSCLIN
1 2
10.7K_0402_1%
2006/03/27
1 2
R159 0_0402_5%
1 2
R160 0_0402_5%
Only for HCL51
default value is 11.8K
USBP6+
USBP6-
USBP4+
USBP4-
USBP2+
USBP2-
USBP1+
USBP1-
USBP0+
USBP0-
+AVDDTX
+AVDDRX
+AVDDC
USBP6+ (30)
USBP6- (30)
USBP4+ (30)
USBP4- (30)
USBP2+ (25)
USBP2- (25)
USBP1+ (30)
USBP1- (30)
USBP0+ (26)
USBP0- (26)
+AVDDTX
+AVDDRX
+AVDDC
Control by EC
Delay 50ms
after +3VALW
ready
2
1
CLK_48M_SB (12)
EC_SCI#
EC_LID_OUT#
L18 FBM-10-201209-260-T_0805
C300 10U_0805_10V4Z
C301 1U_0402_6.3V4Z
C302 0.1U_0402_16V4Z
C303 0.1U_0402_16V4Z
C304 0.1U_0402_16V4Z
L19 FBM-10-201209-260-T_0805
C305 10U_0805_10V4Z
C306 1U_0402_6.3V4Z
C307 0.1U_0402_16V4Z
C308 0.1U_0402_16V4Z
C309 0.1U_0402_16V4Z
C310 10U_0805_10V4Z
C311 1U_0402_6.3V4Z
C312 0.1U_0402_16V4Z
R164 10K_0402_5%
1 2
R165 10K_0402_5%
1 2
10K_1206_8P4R_5%
EC_SMI#
USB_OC6#
USB_OC2#
USB_OC4#
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
L20 FBM-10-201209-260-T_0805
1 2
1 2
1 2
1 2
EC_RSMRST# (28)
Compal Electronics, Inc.
Title
SB450 USB/ACPI/AC97/GPIO
Size Document Number Rev
Custom
Date: Sheet
HCL51 LA-3211P
, 11, 2006
星期二 四月
RP20
+3VALW
4 5
3 6
2 7
1 8
+3VALW
EC_RSMRST#
1 2
R193
47K_0402_5%
1
14 43
0.4
of