Compal LA-3151P, Aspire 3100, Aspire 5100, Aspire 5110, Extensa 5010 Schematic

A

1 1

B

C

D

E

2 2

Compal Confidential

HCW50 Schematics Document

AMD/Sempron/ATI RX485/SB460 W/s M52/54/56P

2006 / 02 / 28

3 3

4 4

Rev:0.3 (For PVT)

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2005/05/09 2006/03/08

C

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

D

Date: Sheet

Compal Electronics, inc.

SCHEMATIC, M /B LA-3151P

401412

星期四

09, 2006

三月

E

B

155,

of

5

4

3

2

1

Compal confidential

Project Code: HCW50
File Name : LA-3151P

D D

Thermal Sensor
ADM1032ARM

page 7 page 15

Clock Generator
ICS951462

AMD Turion/Sempron CPU

Socket S1 638P

H_A#(3..31)

page 5,6,7,8

DDRII DDRII-SO-DIMM X2

page 9,10

Dual Channel DDR-II

H_D#(0..63)

HT 16x16 800MHZ

DVI-D Conn.

page 30

LCD CONN

page 29

CRT & TV-OUT

page 28

ATI-RX485M

465 BGA

page 11,12,13,14

A-Link Express

PCI-Express

ATI M52PG/M54P/M56P

with 64/128/256MB VRAM

C C

page 16,17,18,19,20,21

ATI-SB460

PCI BUS

Mini PCI Socket
Mini card / CAM RTL8110SCL

B B

page 36

Realtek

RTL8100CL

page 31

RJ45 CONN

page 32

ENE Controller

CB714

page 37

Slot 0

page 38

6in1 CardReader
Slot

1394 Controller

page 38

VT6311S

page 40

1394
Conn.

page 40

LPC BUS

549 BGA

page 22,23,24,25,26

2 x PCIE

PATA

USB 2.0

USB 2.0

AC-LINK

SATA

One Channel

USB conn x 2 / New card

BT Conn

Audio CKT
ALC883

MDC Conn.

page 39

page 34

AMP & Audio Jack

page 44

page 34

SATA HDD Conn.

page 27

HDD Conn.
CDROM Conn.

page 27

page 45

Power On/Off C KT / LID switch / Power OK CKT

page 42

DC/DC Interface CKT.

page 46

CIR/LED

page 43

RTC CKT.

page 22

SMsC LPC47N207

page 41

ENE KB910

page 33

Power Circuit DC/DC

page 46~

A A

5

4

FIR module

page 41

Security Classification

Issued Date

THIS SHEET OF ENG INEE RIN G DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY O R DIS CLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

Touch Pad
CONN.

2005/03/08 2006/03/08

page 34

Compal Secret Data

Deciphered Date

Int. KBD

page 34

BIOS

page 35

2

Compal Electronics, inc.

Title

SCHEMATIC, M/B LA-3151P

Size Document Number R ev

Custom

401412

Date: Sheet

星期四 三

09, 2006

月

255,

1

of

B

5

Voltage Rails

Power Plane Description

D D

C C

VIN
B+
+CPU_CORE
+0.9V 0.9V switched power rail for DDRII terminator
+1.2V_HT
+1.5VS
+1.8V
+1.8VS 1.8V switched power rail
+2.5VS
+3VALW
+3VS
+5VALW
+5VS
+VSB VSB always on power rail O N ON*
+RT CVCC RTC power
+1.2VS 1.2V switched power rail for PCIE ON OFF OFF
+0.9VS 0.9V switched power rail for VRAM terminator O N OFF OFF
+1.8VALW 1.8V switched power rail O N ON ON*
+V DD_ CORE 1.0~1.2V switched power rail for VGA ON OFF OFF

Adapter power supply (19V)
AC or battery power rail for power circuit.
Core voltage for CPU

1.2V switched power rail

1.5V switched power rail

1.8V power rail for DDRII

2.5V switched power rail

3.3V always on power rail

3.3V switched power rail
5V always on power rail
5V switched power rail

4

S0 S3 S5

N/A N/A N/A

ON OFF
ON ON
ON OFF OFF
ON OFF OFF
ON
ON
ON
ON
ON
ON

ON
ON

N/AN/AN/A
OFF
OFF

OFF

ON

OFF

OFF
OFF

OFF

ON ON*

OFF

OFF

ON*

ON

OFFON

OFF

ON*ON

3

SIGNAL

STATE

Full ON

S1(Power On Suspend)

S3 (Suspend to RAM)

S4 (Suspend to Disk)

S5 (Soft OFF)

SLP_S1# SLP_S3#

HIGH HIGH HIGH

LOW

LOW

LOW LOW LOW LOW

SLP_S4# SLP_S5# +VA LW +V +VS Clock

HIGH

LOW

Board ID / SKU ID Table for AD channel

Vcc 3.3V +/- 5%

Board ID

0
1
2
3
4
5
6
7 NC

100K +/- 5%Ra/Rc/Re

Rb / Rd / Rf V min

0

8.2K +/- 5%
18K +/- 5%
33K +/- 5%
56K +/- 5%
100K +/- 5%
200K +/- 5%

AD_BID

0 V

0.216 V 0.250 V 0.289 V

0.436 V

0.712 V

1.036 V

1.453 V 1.650 V 1.759 V

1.935 V

2.500 V

2

LOWLOWLOW

ON

HIGH

HIGHHIGHHIGH

HIGH

HIGH

ON

ON

ON

ON

ON

V typ

AD_BID

ON

ON

OFF

OFF

V

AD_BID

0 V 0 V

0.503 V

0.819 V

1.185 V 1.264 V

2.200 V

3.300 V

ON ON

ON

OFF

OFF

OFF

max

0.538 V

0.875 V

2.341 V

3.300 V

1

LOW

OFF

OFF

OFF

Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.

External PCI Devices

Device IDSEL# REQ#/GNT# Interrupts

CardBus(SD)

1394
LAN(10/100)

Mini-PCI(WLAN/TV-Tuner)

AD20
AD16 0
AD17
AD18

2

3
1

PIRQE/PIRQH
PIRQE
PIRQF
PIRQG/PORQH

BOARD ID Table

Board ID

0
1
2
3
4
5

PCB Revision

0.1

6
7

B B

EC SM Bus1 address

Device

Smart Battery
EEPROM(24C16/02)
GMT G781-1

Address Address

1010 000X b
1001 101X b

EC SM Bus2 address

Device

Fintek F75383M

1001 100X b0001 011X b

SKU ID Table

SKU ID

0
1
2
3

SKU

PM
GM

4
5

SB460 SM Bus address

Device

Clock Generator

A A

(ICS9LPRS325AKLFT_MLF72)
DDR DIMM0
DDR DIMM2

5

Address

1101 001Xb

1001 000Xb
1001 010Xb

Security Classification

Issued Date

THIS SHEET OF ENG INEE RIN G DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

4

MAY BE USED BY O R DIS CLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

6
7

2005/03/08 2006/03/08

Compal Secret Data

Deciphered Date

2

BTO Option Table

BTO Item BOM Structure

VGA
UMA

UMA's DVI

LAN(10/100)

LAN(GIGA)
MINI CARD1
MINI CARD2

SATA-to-IDE

PATA

GRAPEVINE

G72MV Only
G73 Only

VRAM
VRAM 64M
VRAM 128M
VRAM 256M

MEDIA/B

CIR
FIR

GENEVA

LCM

Sub-woofer

Compal Electronics, inc.

Title

SCHEMATIC, M/B LA-3151P

Size Document Number R ev

Custom

401412

Date: Sheet

星期四 三

09, 2006

月

355,

1

B

of

5

+3.3VALW_NTB
+3.3VSUS_NTB

+VDC

BATTERY

BATTERY

D D

CPU

CHARGER

PWR

12V

12V

5VSB

+/-5%

+/-5%

+/-5%

SWITCH

MAIN PWR SW
REGULATOR

SW

+5VALW_NTB
+5VSUS_NTB

+VIN_MEM

+5VSUS

SW

5V

+/-5%

ATX POWER SUPPLY

C C

3.3V

+/-5%

+3.3VALW LDO
REGULATOR

SW

4

+5VALW_ATX

+5VDUAL_ATX
+5V_ATX

+3.3VALW_ATX
+3.3VDUAL_ATX
+3.3V_ATX

+3.3V_NTB

+5V_NTB

SWITCH

+3.3VALW

+3.3VSUS

+3.3V

POWER SWITCH

+5VALW

+5VSUS

+5V

3

+5V

+VIN
+5V

+VIN
+5V

+VIN
+5V

+VIN
+5V

+5V

+3.3V

+VIN
+5VSUS

1.5V SW
REGULATOR

SW REGULATOR

VLDT 1.2V SW
REGULATOR

NB CORE SW
REGULATOR

PCIE&SB SW
REGULATOR

1.8V SW
REGULATOR

1.8V VDD&VTT
SW REGULATOR

CPU_VDDA_RUN (S0, S1)

CPU_VDD_RUN (S0, S1)

VLDT_RUN (S0, S1)

VCC_NB (S0, S1)

VDDA_1V2(S0, S1)

+1.8V(S0, S1)

AVDD (S0, S1)

CPU_VDDIO_SUS (S0, S1, S3)
CPU_VTT_SUS (S0, S1,S3)

2

1

AMD CPU

VCCA 2.5V

VDDCORE

0.375-1.500V 30A

VLDT 1.2V 3A

NB RS485

HT VLDT 1.2V 1A
NB CORE 10A
PCI-E CORE

&PCI-E IO 3.5A
HTPLL (1.8V) 200mA

PLL & DAC-Q(1.8V)
200mA

TRANSFORMER
400mA

DAC 300mA

DDRII SODIMMX2

VDD MEM 4A

VTT_MEM 0.5A

SB SB600

VCC_SB (S0, S1)

X4 PCI-E 0.8A

ATA I/O 0.2A

ATA PLL 0.01A

PCI-E PVDD 80mA

SB CORE 0.6A

1.2V S5 PW 0.22A

3.3V I/O 0.45A

3.3V S5 PW 0.01A

USB CORE I/O 0.2A

-12V

+/-5%

CONTROL SIGNAL:

MOBILE: BATTERY
DESKTOP: ATX

+3.3VALW
+3.3V
+3.3VALW

1.2V LDO
REGULATOR

+1.2VALW

+5V

+3.3V

B B

+5V
+3.3VALW

MINI PCI SLOT

3.3V(S0, S1)1.5A
5V (S0, S1) 0.1A

3.3V(S3, S5) 0.2A

+VIN

GBIT ENTHENET

3.3V 0.5A

(S0, S1, S3, S4, S5)

PCI-E CARD

1.5V (S0, S1) 0.7A

+3.3V

+5V
+5VALW

USB X7 FR

VDD
5VDual

3.5A

2005/03/08 2006/03/08

3

VDD
5VDual

1.0A

Compal Secret Data

Deciphered Date

2XPS/2USB X2 RL

5VDual

1.0A

2

3.0A3.0A

5.5A

CNR CONNECTOR
5V

3.3V
12V

3.3Vaux

-12V
5VDual

1.0A

1.0A

0.5A

1.0A

0.1A

0.5A

Security Classification

Issued Date

THIS SHEET OF ENG INEE RIN G DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY O R DIS CLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

0.5A

0.1A

4

X16 PCIEX1 PCIE per

3.3V
12V

PCI Slot (per slot)

5.0A

5V

3.3V
12V

3.3Vaux

-12V

A A

5

7.6A

0.5A

0.375A

0.1A

3.3V
12V

3.3Vaux

3.3V (S3, S5) 0.3A

3.3V (S0, S1) 1.3A

SUPER I/O

+3.3VDUAL (S3) 0.01A

+3.3V (S0, S1) 0.01A

+5V (S0, S1) 0.1A

HD CODEC

3.3V CORE 0.3A

5V ANALOG 0.1A

Compal Electronics, inc.

Title

SCHEMATIC, M/B LA-3151P

Size Document Number R ev

Custom

401412

Date: Sheet

星期四 三

09, 2006

月

455,

1

of

B

5

4

3

2

1

H_CADIP[0..15]<11>

H_CADIP[0..15]
H_CADIN[0..15]

H_CADOP[0..15]
H_CADON[0..15]

H_CADOP[0..15] <11>
H_CADON[0..15] <11>H_CADIN[0..15]<11>

PROCESSOR HYPERTRANSPORT INTERFACE

D D

C C

H_CLKIP1<11>
H_CLKIN1<11>

1 2
1 2

H_CLKIP0<11>
H_CLKIN0<11>

H_CTLIP0<11>
H_CTLIN0<11>

+1.2V_HT

R2 51_0402_1%
R3 51_0402_1%

B B

VLDT_A x AND VLDT _B x ARE CONNEC T E D TO T HE LDT_RUN POWER
SUPPLY THRO UGH T HE PA CKA GE OR ON T HE DIE. IT IS ONLY CONNECTED
ON THE BOA RD T O DEC OUPLING NEA R THE CPU PACKA GE

H_CADIP15
H_CADIP14

H_CADIN14
H_CADIP13
H_CADIN13
H_CADIP12
H_CADIN12
H_CADIP11
H_CADIN11
H_CADIP10
H_CADIN10
H_CADIP9
H_CADIN9
H_CADIP8
H_CADIN8
H_CADIP7
H_CADIN7
H_CADIP6
H_CADIN6
H_CADIP5
H_CADIN5
H_CADIP4
H_CADIN4
H_CADIP3
H_CADIN3
H_CADIP2
H_CADIN2
H_CADIP1
H_CADIN1
H_CADIP0
H_CADIN0

H_CLKIP1
H_CLKIN1
H_CLKIP0
H_CLKIN0

H_CTLIP1
H_CTLIN1

H_CTLIP0
H_CTLIN0

+1.2V_HT

D4
D3
D2
D1

N5

P5
M3
M4

L5

M5

K3

K4

H3

H4
G5

H5

F3

F4

E5

F5

N3

N2

L1

M1

L3
L2
J1

K1
G1

H1
G3
G2

E1

F1

E3

E2

J5

K5

J3
J2

P3

P4

N1

P1

VLDT_A3
VLDT_A2
VLDT_A1
VLDT_A0

L0_CADIN_H15
L0_CADIN_L15
L0_CADIN_H14
L0_CADIN_L14
L0_CADIN_H13
L0_CADIN_L13
L0_CADIN_H12
L0_CADIN_L12
L0_CADIN_H11
L0_CADIN_L11
L0_CADIN_H10
L0_CADIN_L10
L0_CADIN_H9
L0_CADIN_L9
L0_CADIN_H8
L0_CADIN_L8
L0_CADIN_H7
L0_CADIN_L7
L0_CADIN_H6
L0_CADIN_L6
L0_CADIN_H5
L0_CADIN_L5
L0_CADIN_H4
L0_CADIN_L4
L0_CADIN_H3
L0_CADIN_L3
L0_CADIN_H2
L0_CADIN_L2
L0_CADIN_H1
L0_CADIN_L1
L0_CADIN_H0
L0_CADIN_L0

L0_CLKIN_H1
L0_CLKIN_L1
L0_CLKIN_H0
L0_CLKIN_L0

L0_CTLIN_H1
L0_CTLIN_L1

L0_CTLIN_H0
L0_CTLIN_L0

JP72A

L0_CADOUT_H15
L0_CADOUT_L15
L0_CADOUT_H14
L0_CADOUT_L14
L0_CADOUT_H13
L0_CADOUT_L13
L0_CADOUT_H12
L0_CADOUT_L12
L0_CADOUT_H11
L0_CADOUT_L11
L0_CADOUT_H10
L0_CADOUT_L10

L0_CADOUT_H9

L0_CADOUT_L9

L0_CADOUT_H8

L0_CADOUT_L8

L0_CADOUT_H7

L0_CADOUT_L7

L0_CADOUT_H6

L0_CADOUT_L6

L0_CADOUT_H5

L0_CADOUT_L5

L0_CADOUT_H4

L0_CADOUT_L4

L0_CADOUT_H3

L0_CADOUT_L3

L0_CADOUT_H2

L0_CADOUT_L2

L0_CADOUT_H1

L0_CADOUT_L1

L0_CADOUT_H0

HTT Interface

L0_CADOUT_L0
L0_CLKOUT_H1

L0_CLKOUT_L1

L0_CLKOUT_H0

L0_CLKOUT_L0

L0_CTLOUT_H1

L0_CTLOUT_L1

L0_CTLOUT_H0

L0_CTLOUT_L0

Athlon 64 S1
Processor Socket

VLDT_B3
VLDT_B2
VLDT_B1
VLDT_B0

AE5
AE4
AE3
AE2

T4
T3
V5
U5
V4
V3
Y5
W5
AB5
AA5
AB4
AB3
AD5
AC5
AD4
AD3
T1
R1
U2
U3
V1
U1
W2
W3
AA2
AA3
AB1
AA1
AC2
AC3
AD1
AC1

Y4
Y3
Y1
W1

T5
R5

R2
R3

1 2

H_CADOP15
H_CADON15H_CADIN15
H_CADOP14
H_CADON14
H_CADOP13
H_CADON13
H_CADOP12
H_CADON12
H_CADOP11
H_CADON11
H_CADOP10
H_CADON10
H_CADOP9
H_CADON9
H_CADOP8
H_CADON8
H_CADOP7
H_CADON7
H_CADOP6
H_CADON6
H_CADOP5
H_CADON5
H_CADOP4
H_CADON4
H_CADOP3
H_CADON3
H_CADOP2
H_CADON2
H_CADOP1
H_CADON1
H_CADOP0
H_CADON0

H_CLKOP1
H_CLKON1
H_CLKOP0
H_CLKON0

H_CTLOP0
H_CTLON0

C1

4.7U_0805_10V4Z

H_CLKOP1 <11>
H_CLKON1 <11>
H_CLKOP0 <11>
H_CLKON0 <11>

H_CTLOP0 <11>
H_CTLON0 <11>

FAN1 Conn

+5VS

+VCC_FAN1

EN_DFAN1<33>

EN_DFAN1

C2 10U_0805_10V4Z

U2

1

VEN

2

VIN

3

VO

4

VSET

G993P1UF_SOP8

FAN_SPEED1<33>

1 2

GND
GND
GND
GND

8
7
6
5

+3VS

12

R1
10K_0402_5%

1

C5
1000P_0402_50V7K

2

40mil

+VCC_FAN1

+5VS

12

D1
1SS355_SOD323

1N4148_SOT23

1 2

10U_0805_10V4Z

1000P_0402_50V7K

D2

C3

1 2

C4

1 2

ACES_85205-03001

JP73

1
2
3

+1.2V_HT

1

C6
10U_0805_10V4Z

2

A A

5

1

C8

2

0.22U_0603_10V7K

LAYOUT: Place bypass cap on topside of board

NEAR HT POWER PINS T HA T A RE NOT CONNECTED DIRECTLY
TO DOWNSTREAM HT DEVICE, BUT CONNECTED INTERNA LLY
TO OTHER HT POWER PINS
PLACE CLOSE TO VLDT0 POWER PINS

C9

0.22U_0603_10V7K

1

2

180P_0402_50V8J

C10

1

2

1

C11

180P_0402_50V8J

2

4

Security Classification

Issued Date

THIS SHEET OF ENG INEE RIN G DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY O R DIS CLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/10/11 2006/10/11

Compal Secret Data

Deciphered Date

Compal Electronics, inc.

Title

SCHEMATIC, M/B LA-3151P

Size Document Number R ev

Custom

401412

Date: Sheet

星期四 三

09, 2006

2

月

555,

1

B

of

A

B

C

D

E

DDR_A_DQS[0..7]
DDR_A_DQS#[0..7]DDR_B_DQS[0..7]

+0.9V

1

C13

1.5P_0402_50V8C

2

1

C15

1.5P_0402_50V8C

2

DDR_A_MA[0..15]

DDR_B_DQS#[0..7]

DDR_A_CLK2 <9>
DDR_A_CLK#2 <9>
DDR_A_CLK1 <9>
DDR_A_CLK#1 <9>

DDR_B_CLK2 <10>
DDR_B_CLK#2 <10>
DDR_B_CLK1 <10>
DDR_B_CLK#1 <10>

DDR_B_ ODT1 <10>
DDR_B_ ODT0 <10>
DDR_A_ODT1 <9>
DDR_A_ODT0 <9>

DDR_B_MA[0..15] <10>

DDR_B_BS#2 <10>
DDR_B_BS#1 <10>
DDR_B_BS#0 <10>

DDR_B_RAS# <10>
DDR_B_CAS# <10>
DDR_B_WE# <10>

DDR_B_D[0..63]<10>

To reverse SODIMM socket

DDR_B_DM[0..7]<10>

Processor DDR2 Memory Interface

AD11
AF11
AF14
AE14

AB11
AC12
AF13
AF15
AF16
AC18
AF19
AD14
AC14
AE18
AD18
AD20
AC20
AF23
AF24
AF20
AE20
AD22
AC22
AE25
AD26
AA25
AA26
AE24
AD24
AA23
AA24

AD12
AC16
AE22
AB26

AF12
AE12
AE16
AD16
AF21
AF22
AC25
AC26

Y11

G24
G23
D26
C26
G26
G25
E24
E23
C24
B24
C20
B20
C25
D24
A21
D20
D18
C18
D14
C14
A20
A19
A16
A15
A13
D12
E11
G11
B14
A14
A11
C11

E25
A22
B16
A12

F26
E26
A24
A23
D16
C16
C12
B12

JP72C

MB_DATA63
MB_DATA62
MB_DATA61
MB_DATA60
MB_DATA59
MB_DATA58
MB_DATA57
MB_DATA56
MB_DATA55
MB_DATA54
MB_DATA53
MB_DATA52
MB_DATA51
MB_DATA50
MB_DATA49
MB_DATA48
MB_DATA47
MB_DATA46
MB_DATA45
MB_DATA44
MB_DATA43
MB_DATA42
MB_DATA41
MB_DATA40
MB_DATA39
MB_DATA38
MB_DATA37
MB_DATA36
MB_DATA35
MB_DATA34
MB_DATA33
MB_DATA32
MB_DATA31
MB_DATA30
MB_DATA29
MB_DATA28
MB_DATA27
MB_DATA26
MB_DATA25
MB_DATA24
MB_DATA23
MB_DATA22
MB_DATA21
MB_DATA20
MB_DATA19
MB_DATA18
MB_DATA17
MB_DATA16
MB_DATA15
MB_DATA14
MB_DATA13
MB_DATA12
MB_DATA11
MB_DATA10
MB_DATA9
MB_DATA8
MB_DATA7
MB_DATA6
MB_DATA5
MB_DATA4
MB_DATA3
MB_DATA2
MB_DATA1
MB_DATA0

MB_DM7
MB_DM6
MB_DM5
MB_DM4
MB_DM3
MB_DM2
MB_DM1
MB_DM0

MB_DQS_H7
MB_DQS_L7
MB_DQS_H6
MB_DQS_L6
MB_DQS_H5
MB_DQS_L5
MB_DQS_H4
MB_DQS_L4
MB_DQS_H3
MB_DQS_L3
MB_DQS_H2
MB_DQS_L2
MB_DQS_H1
MB_DQS_L1
MB_DQS_H0
MB_DQS_L0

DDRII Data

DDR: DATA

Athlon 64 S1
Processor Socket

MA_DATA63
MA_DATA62
MA_DATA61
MA_DATA60
MA_DATA59
MA_DATA58
MA_DATA57
MA_DATA56
MA_DATA55
MA_DATA54
MA_DATA53
MA_DATA52
MA_DATA51
MA_DATA50
MA_DATA49
MA_DATA48
MA_DATA47
MA_DATA46
MA_DATA45
MA_DATA44
MA_DATA43
MA_DATA42
MA_DATA41
MA_DATA40
MA_DATA39
MA_DATA38
MA_DATA37
MA_DATA36
MA_DATA35
MA_DATA34
MA_DATA33
MA_DATA32
MA_DATA31
MA_DATA30
MA_DATA29
MA_DATA28
MA_DATA27
MA_DATA26
MA_DATA25
MA_DATA24
MA_DATA23
MA_DATA22
MA_DATA21
MA_DATA20
MA_DATA19
MA_DATA18
MA_DATA17
MA_DATA16
MA_DATA15
MA_DATA14
MA_DATA13
MA_DATA12
MA_DATA11
MA_DATA10

MA_DATA9
MA_DATA8
MA_DATA7
MA_DATA6
MA_DATA5
MA_DATA4
MA_DATA3
MA_DATA2
MA_DATA1
MA_DATA0

MA_DM7
MA_DM6
MA_DM5
MA_DM4
MA_DM3
MA_DM2
MA_DM1
MA_DM0

MA_DQS_H7

MA_DQS_L7

MA_DQS_H6

MA_DQS_L6

MA_DQS_H5

MA_DQS_L5

MA_DQS_H4

MA_DQS_L4

MA_DQS_H3

MA_DQS_L3

MA_DQS_H2

MA_DQS_L2

MA_DQS_H1

MA_DQS_L1

MA_DQS_H0

MA_DQS_L0

AA12
AB12
AA14
AB14
W11
Y12
AD13
AB13
AD15
AB15
AB17
Y17
Y14
W14
W16
AD17
Y18
AD19
AD21
AB21
AB18
AA18
AA20
Y20
AA22
Y22
W21
W22
AA21
AB22
AB24
Y24
H22
H20
E22
E21
J19
H24
F22
F20
C23
B22
F18
E18
E20
D22
C19
G18
G17
C17
F14
E14
H17
E17
E15
H15
E13
C13
H12
H11
G14
H14
F12
G12

Y13
AB16
Y19
AC24
F24
E19
C15
E12

W12
W13
Y15
W15
AB19
AB20
AD23
AC23
G22
G21
C22
C21
G16
G15
G13
H13

DDR_B_D63
DDR_B_D62
DDR_B_D61
DDR_B_D60
DDR_B_D59
DDR_B_D58
DDR_B_D57
DDR_B_D56
DDR_B_D55
DDR_B_D54
DDR_B_D53
DDR_B_D52
DDR_B_D51
DDR_B_D50
DDR_B_D49
DDR_B_D48
DDR_B_D47
DDR_B_D46
DDR_B_D45
DDR_B_D44
DDR_B_D43
DDR_B_D42
DDR_B_D41
DDR_B_D40
DDR_B_D39
DDR_B_D38
DDR_B_D37
DDR_B_D36
DDR_B_D35
DDR_B_D34
DDR_B_D33
DDR_B_D32
DDR_B_D31
DDR_B_D30
DDR_B_D29
DDR_B_D28
DDR_B_D27
DDR_B_D26
DDR_B_D25
DDR_B_D24
DDR_B_D23
DDR_B_D22
DDR_B_D21
DDR_B_D20
DDR_B_D19
DDR_B_D18
DDR_B_D17
DDR_B_D16
DDR_B_D15
DDR_B_D14
DDR_B_D13
DDR_B_D12
DDR_B_D11
DDR_B_D10
DDR_B_D9
DDR_B_D8
DDR_B_D7
DDR_B_D6
DDR_B_D5
DDR_B_D4
DDR_B_D3
DDR_B_D2
DDR_B_D1
DDR_B_D0

DDR_B_DM7
DDR_B_DM6
DDR_B_DM5
DDR_B_DM4
DDR_B_DM3
DDR_B_DM2
DDR_B_DM1
DDR_B_DM0

DDR_B_DQS7
DDR_B_DQS#7
DDR_B_DQS6
DDR_B_DQS#6
DDR_B_DQS5
DDR_B_DQS#5
DDR_B_DQS4
DDR_B_DQS#4
DDR_B_DQS3
DDR_B_DQS#3
DDR_B_DQS2
DDR_B_DQS#2
DDR_B_DQS1
DDR_B_DQS#1
DDR_B_DQS0
DDR_B_DQS#0

DDR_A_D63
DDR_A_D62
DDR_A_D61
DDR_A_D60
DDR_A_D59
DDR_A_D58
DDR_A_D57
DDR_A_D56
DDR_A_D55
DDR_A_D54
DDR_A_D53
DDR_A_D52
DDR_A_D51
DDR_A_D50
DDR_A_D49
DDR_A_D48
DDR_A_D47
DDR_A_D46
DDR_A_D45
DDR_A_D44
DDR_A_D43
DDR_A_D42
DDR_A_D41
DDR_A_D40
DDR_A_D39
DDR_A_D38
DDR_A_D37
DDR_A_D36
DDR_A_D35
DDR_A_D34
DDR_A_D33
DDR_A_D32
DDR_A_D31
DDR_A_D30
DDR_A_D29
DDR_A_D28
DDR_A_D27
DDR_A_D26
DDR_A_D25
DDR_A_D24
DDR_A_D23
DDR_A_D22
DDR_A_D21
DDR_A_D20
DDR_A_D19
DDR_A_D18
DDR_A_D17
DDR_A_D16
DDR_A_D15
DDR_A_D14
DDR_A_D13
DDR_A_D12
DDR_A_D11
DDR_A_D10
DDR_A_D9
DDR_A_D8
DDR_A_D7
DDR_A_D6
DDR_A_D5
DDR_A_D4
DDR_A_D3
DDR_A_D2
DDR_A_D1
DDR_A_D0

DDR_A_DM7
DDR_A_DM6
DDR_A_DM5
DDR_A_DM4
DDR_A_DM3
DDR_A_DM2
DDR_A_DM1
DDR_A_DM0

DDR_A_DQS7
DDR_A_DQS#7
DDR_A_DQS6
DDR_A_DQS#6
DDR_A_DQS5
DDR_A_DQS#5
DDR_A_DQS4
DDR_A_DQS#4
DDR_A_DQS3
DDR_A_DQS#3
DDR_A_DQS2
DDR_A_DQS#2
DDR_A_DQS1
DDR_A_DQS#1
DDR_A_DQS0
DDR_A_DQS#0

DDR_A_D[0..63] <9>

To normal SODIMM socket

DDR_A_DM[0..7] <9>

DDR_A_MA[0..15]<9>

VDD_VTT_SUS_CPU IS CONNECTED TO THE VDD_VTT_SUS POWER
SUPPLY THROUGH TH E P ACKAGE OR ON THE DIE. IT IS ONLY CONNECTED

ON THE BOARD TO DECOUPLING NEAR THE CPU PACKAGE

4 4

3 3

2 2

+1.8V

12

R4

39.2_0402_1%~D

R5

12

39.2_0402_1%~D

PLACE THEM CLOSE TO
CPU WITHIN 1"

DDR_CS3_DIMMA#<9>
DDR_CS2_DIMMA#<9>
DDR_CS1_DIMMA#<9>
DDR_CS0_DIMMA#<9>

DDR_CS3_DIMMB#<10>
DDR_CS2_DIMMB#<10>
DDR_CS1_DIMMB#<10>
DDR_CS0_DIMMB#<10>

DDR_CKE1_DIMMB<10>
DDR_CKE0_DIMMB<10>
DDR_CKE1_DIMMA<9>
DDR_CKE0_DIMMA<9>

DDR_A_CLK2

DDR_A_CLK#2
DDR_A_CLK1

DDR_A_CLK#1

PLACE CLOSE TO PRO CESSOR
WITHIN 1.5 INCH

+0.9VREF_CPU

M_ZN
M_ZP

DDR_CS3_DIMMA#
DDR_CS2_DIMMA#
DDR_CS1_DIMMA#
DDR_CS0_DIMMA#

DDR_CS3_DIMMB#
DDR_CS2_DIMMB#
DDR_CS1_DIMMB#
DDR_CS0_DIMMB#

DDR_CKE1_DIMMB
DDR_CKE0_DIMMB
DDR_CKE1_DIMMA
DDR_CKE0_DIMMA

DDR_A_MA15
DDR_A_MA14
DDR_A_MA13
DDR_A_MA12
DDR_A_MA11
DDR_A_MA10
DDR_A_MA9
DDR_A_MA8
DDR_A_MA7
DDR_A_MA6
DDR_A_MA5
DDR_A_MA4
DDR_A_MA3
DDR_A_MA2
DDR_A_MA1
DDR_A_MA0

1

C12

1.5P_0402_50V8C

2

1

C14

1.5P_0402_50V8C

2

DDR_A_BS#2
DDR_A_BS#1
DDR_A_BS#0

DDR_A_RAS#
DDR_A_CAS#
DDR_A_WE#

DDR_A_BS#2<9>
DDR_A_BS#1<9>
DDR_A_BS#0<9>

DDR_A_RAS#<9>
DDR_A_CAS#<9>
DDR_A_WE#<9>

AE10

AF10

W17

Y10

V19
J22
V22
T19

Y26
J24

W24

U23
H26

J23
J20
J21

K19
K20
V24
K24
L20
R19
L19
L22

L21
M19
M20
M24
M22

N22

N21

R21

K22

R20

T22

T20

U20

U21

JP72B

M_VREF
VTT_SENSE

M_ZN
M_ZP

MA0_CS_L3
MA0_CS_L2
MA0_CS_L1
MA0_CS_L0

MB0_CS_L3
MB0_CS_L2
MB0_CS_L1
MB0_CS_L0

MB_CKE1
MB_CKE0
MA_CKE1
MA_CKE0

MA_ADD15
MA_ADD14
MA_ADD13
MA_ADD12
MA_ADD11
MA_ADD10
MA_ADD9
MA_ADD8
MA_ADD7
MA_ADD6
MA_ADD5
MA_ADD4
MA_ADD3
MA_ADD2
MA_ADD1
MA_ADD0

MA_BANK2
MA_BANK1
MA_BANK0

MA_RAS_L
MA_CAS_L
MA_WE_L

Athlon 64 S1
Processor
Socket

DDR_B_DQS[0..7]<10>
DDR_B_DQS#[0..7]<10>

D10

VTT1

C10

VTT2

B10

VTT3

AD10

VTT4

W10

VTT5

AC10

VTT6

AB10

VTT7

AA10

VTT8

A10

VTT9

Y16

MA0_CLK_H2

AA16

MA0_CLK_L2

E16

MA0_CLK_H1

F16

MA0_CLK_L1

AF18

MB0_CLK_H2

AF17

MB0_CLK_L2

A17

MB0_CLK_H1

A18

MB0_CLK_L1

W23

MB0_ODT1

W26

MB0_ODT0

V20

MA0_ODT1

U19

MA0_ODT0

J25

MB_ADD15

J26

MB_ADD14

W25

MB_ADD13

L23

MB_ADD12

L25

MB_ADD11

U25

MB_ADD10

L24

MB_ADD9

DDRII Cmd/Ctrl//Clk

M26

MB_ADD8

L26

MB_ADD7

N23

MB_ADD6

N24

MB_ADD5

N25

MB_ADD4

N26

MB_ADD3

P24

MB_ADD2

P26

MB_ADD1

T24

MB_ADD0

K26

MB_BANK2

T26

MB_BANK1

U26

MB_BANK0

U24

MB_RAS_L

V26

MB_CAS_L

U22

MB_WE_L

DDR_B_CLK2

DDR_B_CLK#2
DDR_B_CLK1

DDR_B_CLK#1

PLACE CLOSE TO PRO CESSOR
WITHIN 1.5 INCH

DDR_A_CLK2
DDR_A_CLK#2
DDR_A_CLK1
DDR_A_CLK#1

DDR_B_CLK2
DDR_B_CLK#2
DDR_B_CLK1
DDR_B_CLK#1

DDR_B_ODT1
DDR_B_ODT0
DDR_A_ODT1
DDR_A_ODT0

DDR_B_MA15
DDR_B_MA14
DDR_B_MA13
DDR_B_MA12
DDR_B_MA11
DDR_B_MA10
DDR_B_MA9
DDR_B_MA8
DDR_B_MA7
DDR_B_MA6
DDR_B_MA5
DDR_B_MA4
DDR_B_MA3
DDR_B_MA2
DDR_B_MA1
DDR_B_MA0

DDR_B_BS#2
DDR_B_BS#1
DDR_B_BS#0

DDR_B_RAS#
DDR_B_CAS#
DDR_B_WE#

DDR_A_DQS[0..7]<9>
DDR_A_DQS#[0..7]<9>

ATI check ,Use +0.9V PWR , can delete or not

A1

+1.8V

12

R6

1K_0402_1%

1 1

R7

1K_0402_1%

12

1

C16

2

1000P_0402_50V7K

+0.9VREF_CPU

0.1U_0402_16V4Z

C18

VDD_VREF_SUS_CPU

LAYOUT:PLACE CLOSE TO CPU

A

1

1

2

2

1000P_0402_50V7K

+0.9VREF_CPU

1

C20

C19

1U_0402_6.3V4Z

2

Security Classification

Issued Date

THIS SHEET OF ENG INEE RING D RAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY CO MPAL ELECTRONICS, IN C. NEITHER THIS SHE ET NOR THE INFORMATI ON IT CONTAINS

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PART Y WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2005/10/11 2006/10/11

Compal Secret Data

Deciphered Date

D

Title

SCHEMATIC, M/B LA-3151P

Size Document Number Rev

Custom

401412

星期四 三月

Date: Sheet

Athlon 64 S1g1

uPGA638
Top View

AF1

Compal Electronics, inc.

006

E

A26

655, 09, 2

B

of

5

+2.5VS

L1

12

FBM-L11-321611-260-LMT_1206

D D

1

2

4.7U_0805_10V4Z

+VDDA_25V

C22

50mil width(600mA)

1

C23

2

0.22U_0603_10V7K

SB460 ONLY

+3VS

4.7K_0402_5%

@

+1.8V

12

R15

U49

2

B

1

A

R806 0_0402_5%@

+1.8V

U50

2

B

1

A

R807 0_0402_5%@

+1.8V

U51

2

B

1

A

R808 0_0402_5%@

C26

1 2

5

0.1U_0402_16V4Z

P

4

Y

G

NC7SZ08P5 X_NL_SC70-5

3

1 2

C28

1 2

5

0.1U_0402_16V4Z

P

4

Y

G

NC7SZ08P5 X_NL_SC70-5

3

1 2

C29

1 2

5

0.1U_0402_16V4Z

P

4

Y

G

NC7SZ08P5 X_NL_SC70-5

3

1 2

+1.8VS

12

R14

300_0402_5%

CPU_PWRGD<23>

+1.8VS

12

R18

300_0402_5%

C C

SB_PWRGD<23,42>

LDT_STOP#<13,23>

R804 0_0402_5%

1 2

LDT_RST#<22>

300_0402_5%

SB_PWROK_R

+1.8V

+1.8VS

12

R19

HDT Connector

12

12

12

CPU_DBREQ#
CPU_DBRDY
CPU_TCK
CPU_TMS
CPU_TDI
CPU_TRST#
CPU_TDO

CPU_THERMDA
CPU_THERMDC

12

R26 220_0402_5%@

R27 220_0402_5%@12R25 220_0402_5%@

R24 220_0402_5%@

+3VS

C30

0.1U_0402_16V4Z

1 2

U4

1

VDD

2

D+

3

D­THERM#4GND

ADM1032ARMZ-2REEL_MSOP8

F75383M_MSOP8

SMBus Address: 1001110X (b)

+1.8V

R28 220_0402_5%@

SCLK

SDATA

ALERT#

8
7
6
5

JP74

2

1

4

3

6

5

8

7

10

9

12

11

14

13

16

15

18

17

20

19

22

21

2423
26

SAMTEC_ASP-68200-07

@

EC_SMB_CK2 <33>
EC_SMB_DA2 <33>

B B

NOTE: HDT TERMINATION IS REQUIRED
FOR REV. Ax SILICON ONLY.

1

C31

A A

2200P_0402_50V7K

2

5

4

1

C24
3300P_0402_50V7K

2

4

CPU_ALL_PWROK

CPU_LDTSTOP#

CPU_HT_RESET#

3V_LDT_RST#

+1.2V_HT

place them to CPU within 1"

LDT_RST# 3V_LDT_RST#

3

LAYOUT: ROUTE VDDA TRACE APPROX.
50 mils WIDE (USE 2x25 mil TRACES TO
EXIT BALL FIE L D) AND 500 mils LONG.

R10 300_0402_5%

1 2

1 2
1 2

CPUCLK<15>

CPUCLK#<15>

R12 44.2_0603_1%
R13 44.2_0603_1%

CPU_SIC_R

CPU_HTREF1
CPU_HTREF0 VID0

C25

1 2

3900P_0402_50V7K

R16

169_0402_1%

C27

1 2

3900P_0402_50V7K

Modify 11/22

+1.8VS

+3VS

12

R844

10K_0402_5%@

Q47

E

3 1

MMBT3904_SOT23@

+1.8V

12

R22
300_0402_5%

H_THERMTRIP_S# H_THERMTRIP#

12

R845

C

+1.8V

12

2

Q1

3 1

MMBT3904_SOT23

4.7K_0402_5%@

R20
1K_0402_5%

B

2

CPU_TEST26_BURNIN#
CPU_PRESENT#

CPU_TEST25_H_BYPASSCLK_H

CPU_TEST25_L_BYPASSCLK_L
CPU_TEST19_PLLTEST0
CPU_TEST18_PLLTEST1
CPU_TEST21_SCANEN

Security Classification

THIS SHEET OF ENG INEE RING D RAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY CO MPAL ELECTRONICS, IN C. NEITHER THIS SHE ET NOR THE INFORMATI ON IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PART Y WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

CPU_VCC_SENSE<54>
CPU_VSS_SENSE<54>

CPU_CLKIN_SC_P
CPU_CLKIN_SC_N

12

CPU_TEST25_H_BYPASSCLK_H
CPU_TEST25_L_BYPASSCLK_L
CPU_TEST19_PLLTEST0
CPU_TEST18_PLLTEST1

CPU_THERMDC
CPU_THERMDA

+3VALW

12

R23
10K_0402_5%

H_THERMTRIP# <23>

R32 300_0402_5%

1 2

R33 1K_0402_5%

1 2

R34 510_0402_5%

1 2

R42 510_0402_5%

1 2

R43 300_0402_5%

1 2

R44 300_0402_5%

1 2

R35 300_0402_5%

1 2

Issued Date

2

ATHLON Control and Debug

JP72D

F8

VDDA2

THERMTRIP_L

VDDA1

PROCHOT_L

RESET_L
PWROK
LDTSTOP_L

SIC
SID

HTREF1
HTREF0

CPU_PRESENT_L
VDD_FB_H
VDD_FB_L

VDDIO_FB_H
VDDIO_FB_L

CLKIN_H
CLKIN_L

DBRDY
TMS

TCK
TRST_L
TDI

TEST25_HE9TEST29_H
TEST25_L
TEST19
TEST18
TEST13
TEST9
TEST17
TEST16
TEST15
TEST14
TEST12

TEST7
TEST6
THERMDC
THERMDA
TEST3
TEST2

RSVD0
RSVD1
RSVD2
RSVD3

RSVD4
RSVD5
RSVD6
RSVD7

AMD NPT S1 SOCKET
Processor Socket

2

PSI_L

DBREQ_L

TEST29_L

TEST24
TEST23

MISC

TEST22
TEST21
TEST20

TEST28_H
TEST28_L

TEST27
TEST26
TEST10

TEST8

RSVD8
RSVD9

RSVD10
RSVD11

RSVD12
RSVD13
RSVD14

RSVD15
RSVD16
RSVD17
RSVD18
RSVD19
RSVD20

CPU_PROCHOT#_1.8

VID5
VID4
VID3
VID2
VID1
VID0

TDO

VDDIOFB_H
VDDIOFB_L

T13PAD
T15PAD
T17PAD
T19PAD
T20PAD

T23PAD
T25PAD

T28PAD
T30PAD

MAINPW ON <4 7,48,50>

Compal Secret Data

F9
B7

A7

F10

AF4
AF5

P6

R6

F6
E6

W9

Y9
A9

A8
G10
AA9

AC9
AD9
AF9

E8

G9
H10
AA7

C2

D7

E7
F7

C7
AC8

C3
AA6

W7
W8

Y6

AB6
P20

P19
N20
N19

R26
R25
P22
R22

Deciphered Date

CPU_HT_RESET#
CPU_ALL_PWROK
CPU_LDTSTOP#

CPU_VCC_SENSE
CPU_VSS_SENSE

T1PAD
T2PAD

CPU_DBRDY
CPU_TMS

CPU_TCK
CPU_TRST#
CPU_TDI

+3VALW

12

R21

1K_0402_5%@

2

Q2

MMBT3904_SOT23@

3 1

+1.8V

2005/03/08 2006/03/08

H_THERMTRIP_S#

AF6

CPU_PROCHOT#_1.8

AC7

VID5

A5

VID4

C6

VID3

A6

VID2

A4

VID1

C5
B5

CPU_PRESENT#

AC6

PSI#

A3

CPU_DBREQ#

E10

CPU_TDO

AE9

CPU_TEST29_H_FBCLKOUT_P

C9

CPU_TEST29_L_FBCLKOUT_N

C8

AE7

T14 PAD

AD7

T16 PAD

AE8

T18 PAD

CPU_TEST21_SCANEN

AB8
AF7

T21 PAD

J7

T24 PAD

H8

T26 PAD

AF8

T27 PAD

CPU_TEST26_BURNIN#

AE6
K8

T29 PAD

C4

T31 PAD

H16
B18

B3
C1

H6
G6
D5

R24
W18
R23
AA8
H18
H19

10K_0402_5%

1

+1.8V

12

12

R8

300_0402_5%

+1.8V

12

R29

CPU_PH_G

B

2

Q3

E

3 1

C

MMBT3904_SOT23

Title

Size Document Number Rev

C

Date: Sheet

R9
300_0402_5%

VID5 <54>
VID4 <54>
VID3 <54>
VID2 <54>
VID1 <54>
VID0 <54>

PSI# <54>

Place within 0.5" from CPU
25mil/6mil/6mil/6mil/25mil

R17

1 2

80.6_0402_1%

ROUTE AS 80 Ohm DIFFERENTIAL PAIR
PLACE IT CLOSE TO CPU WITHIN 1"

+3VS

12

R30

4.7K_0402_5%

Compal Electronics, inc.

SCHEMATIC, M/B LA-3151P

401412

星期四 三月

006

1

EC_THERM# <23,33>

755, 09, 2

B

of

5

D D

4

3

2

1

BOTTOMSIDE DECOUPLING

+CPU_CORE

1

C60
180P_0402_50V8J

2

1

C38
22U_0805_6.3V6M

2

1

C46
22U_0805_6.3V6M

2

1

2

+0.9V

1

C63

4.7U_0805_10V4Z

2

1

C71
1000P_0402_50V7K

2

C54

0.22U_0603_10V7K

1

+

C795
220U_D2_4VM

2

1

C39
22U_0805_6.3V6M

2

1

C47

0.22U_0603_10V7K

2

1

C55

0.22U_0603_10V7K

2

1

C65

0.22U_0603_10V7K

2

1

C76
180P_0402_50V8J

2

1

C40
22U_0805_6.3V6M

2

1

C48

0.22U_0603_10V7K

2

1

JP72F

AA4

VSS1

AA11

JP72E

AC4

VDD1

AD2

VDD2

G4

VDD3

H2

VDD4

J9

VDD5

J11

VDD6

J13

VDD7

K6

VDD8

K10

VDD9

K12

VDD10

K14

VDD11

L4

VDD12

L7

VDD13

L9

VDD14

L11

VDD15

L13

VDD16

M2

C C

B B

M6
M8

M10

N7
N9

N11

P8

P10

R4
R7
R9

R11

T2
T6

T8
T10
T12
T14

U7

U9

U11
U13

V6

V8

V10

+CPU_CORE

1

45@

2

VDD17
VDD18
VDD19
VDD20
VDD21
VDD22
VDD23
VDD24
VDD25
VDD26
VDD27
VDD28
VDD29
VDD30
VDD31
VDD32
VDD33
VDD34
VDD35
VDD36
VDD37
VDD38
VDD39
VDD40
VDD41
VDD42

Athlon 64 S1
Processor Socket

+

C796
820U_E9_2.5V_M_R7

Power

45@

VDD43
VDD44
VDD45
VDD46
VDD47
VDD48
VDD49
VDD50
VDD51
VDD52
VDD53
VDD54

VDDIO1
VDDIO2
VDDIO3
VDDIO4
VDDIO5
VDDIO6
VDDIO7
VDDIO8

VDDIO9
VDDIO10
VDDIO11
VDDIO12
VDDIO13
VDDIO14
VDDIO15
VDDIO16
VDDIO17
VDDIO18
VDDIO19
VDDIO20
VDDIO21
VDDIO22
VDDIO23
VDDIO24
VDDIO25
VDDIO26
VDDIO27

1

+

C797
820U_E9_2.5V_M_R7

2

+CPU_CORE+CPU_CORE

V12
V14
W4
Y2
J15
K16
L15
M16
P16
T16
U15
V16

+1.8V

H25
J17
K18
K21
K23
K25
L17
M18
M21
M23
M25
N17
P18
P21
P23
P25
R17
T18
T21
T23
T25
U17
V18
V21
V23
V25
Y25

1

+

C798
330U_D2E_2.5VM_R9

2

1

+

C799
330U_D2E_2.5VM_R9

2

AA13
AA15
AA17
AA19

AB23
AB25
AC11
AC13
AC15
AC17
AC19
AC21

AD25
AE11
AE13
AE15
AE17
AE19
AE21
AE23

VSS2
VSS3
VSS4
VSS5
VSS6

AB2

VSS7

AB7

VSS8

AB9

VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17

AD6

VSS18

AD8

VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27

B4

VSS28

B6

VSS29

B8

VSS30

B9

VSS31

B11

VSS32

B13

VSS33

B15

VSS34

B17

VSS35

B19

VSS36

B21

VSS37

B23

VSS38

B25

VSS39

D6

VSS40

D8

VSS41

D9

VSS42

D11

VSS43

D13

VSS44

D15

VSS45

D17

VSS46

D19

VSS47

D21

VSS48

D23

VSS49

D25

VSS50

E4

VSS51

F2

VSS52

F11

VSS53

F13

VSS54

F15

VSS55

F17

VSS56

F19

VSS57

F21

VSS58

F23

VSS59

F25

VSS60

H7

VSS61

H9

VSS62

H21

VSS63

H23

VSS64

J4

VSS65

Athlon 64 S1
Processor Socket

J6

VSS66

J8

VSS67

J10

VSS68

J12

VSS69

J14

VSS70

J16

VSS71

J18

VSS72

K2

VSS73

K7

VSS74

K9

VSS75

K11

VSS76

K13

VSS77

K15

VSS78

K17

VSS79

L6

VSS80

L8

VSS81

L10

VSS82

L12

VSS83

L14

VSS84

L16

VSS85

L18

VSS86

M7

VSS87

M9

VSS88

M11

VSS89

M17

VSS90

N4

VSS91

N8

VSS92

N10

VSS93

N16

VSS94

N18

VSS95

P2

VSS96

P7

VSS97

P9

VSS98

P11

VSS99

P17

VSS100

R8

VSS101

R10

Ground

VSS102

R16

VSS103

R18

VSS104

T7

VSS105

T9

VSS106

T11

VSS107

T13

VSS108

T15

VSS109

T17

VSS110

U4

VSS111

U6

VSS112

U8

VSS113

U10

VSS114

U12

VSS115

U14

VSS116

U16

VSS117

U18

VSS118

V2

VSS119

V7

VSS120

V9

VSS121

V11

VSS122

V13

VSS123

V15

VSS124

V17

VSS125

W6

VSS126

Y21

VSS127

Y23

VSS128

N6

VSS129

C32
10U_0805_10V4Z

2

+CPU_CORE

1

C41

0.22U_0603_10V7K

2

1

C923

0.01U_0402_16V7K

2

1

C33
10U_0805_10V4Z

2

1

2

1

C924
180P_0402_50V8J

2

+1.8V

1

C49

4.7U_0805_10V4Z

2

1

C56

0.22U_0603_10V7K

2

CPU left-hand side CPU right-hand side

C42

0.22U_0603_10V7K

1

C34
10U_0805_10V4Z

2

1

C43

0.22U_0603_10V7K

2

1

C35
10U_0805_10V4Z

2

DECOUPLING BETWEEN PROCESSOR AND DIMMs
PLACE CLOSE TO PROCESSOR AS POSSIBLE

+0.9V

1

C61

4.7U_0805_10V4Z

2

1

C69
1000P_0402_50V7K

2

1

C50

4.7U_0805_10V4Z

2

1

2

C57

0.01U_0402_16V7K

1

C68

0.22U_0603_10V7K

2

1

C74
180P_0402_50V8J

2

1

C51

4.7U_0805_10V4Z

2

1

C44

0.22U_0603_10V7K

2

1

C58

0.01U_0402_16V7K

2

1

C36
10U_0805_10V4Z

2

1

C52

4.7U_0805_10V4Z

2

1

C59
180P_0402_50V8J

2

+1.8V

1

C45
22U_0805_6.3V6M

2

1

C37
22U_0805_6.3V6M

2

1

C53

0.22U_0603_10V7K

2

A1

A26

PROCESSOR POWER AND GROUND

Athlon 64 S1g1

uPGA638
Top View

A A

AF1

Security Classification

Issued Date

THIS SHEET OF ENG INEE RING D RAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY CO MPAL ELECTRONICS, IN C. NEITHER THIS SHE ET NOR THE INFORMATI ON IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PART Y WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/03/08 2006/03/08

Compal Secret Data

Deciphered Date

2

Compal Electronics, inc.

Title

SCHEMATIC, M/B LA-3151P

Size Document Number Rev

C

401412

星期四 三月

Date: Sheet

006

1

855, 09, 2

of

B

5

4

3

2

1

+1.8V+DIMM_VREF+1.8V+1.8V

JP1

1

VREF

3

DDR_A_D0

D D

C C

DDR_CKE0_DIMMA<6>
DDR_CS2_DIMMA#<6>

DDR_A_BS#2<6>

DDR_A_BS#0<6>
DDR_A_WE#<6>

DDR_A_CAS#<6>
DDR_CS1_DIMMA#<6>

DDR_A_ODT1<6>

B B

A A

SB_CK_SDAT<10,15,23>
SB_CK_SCLK<10,15,23>

DDR_A_D1
DDR_A_DQS#0

DDR_A_DQS0
DDR_A_D2

DDR_A_D3
DDR_A_D8

DDR_A_D9
DDR_A_DQS#1

DDR_A_DQS1
DDR_A_D10

DDR_A_D11

DDR_A_D16
DDR_A_D17

DDR_A_DQS#2
DDR_A_DQS2

DDR_A_D18 DDR_A_D22
DDR_A_D19

DDR_A_D24
DDR_A_D25

DDR_A_DM3

DDR_A_D26
DDR_A_D27

DDR_CKE0_DIMMA
DDR_CS2_DIMMA#

DDR_A_BS#2
DDR_A_MA12

DDR_A_MA9

DDR_A_MA5
DDR_A_MA3
DDR_A_MA1

DDR_A_MA10
DDR_A_BS#0
DDR_A_WE#

DDR_A_CAS#
DDR_CS1_DIMMA#

DDR_A_ODT1
DDR_A_D32

DDR_A_D33
DDR_A_DQS#4

DDR_A_DQS4
DDR_A_D34

DDR_A_D35
DDR_A_D40

DDR_A_D41
DDR_A_DM5
DDR_A_D42

DDR_A_D43 DDR_A_D47
DDR_A_D48

DDR_A_D49 DDR_A_D53

DDR_A_DQS#6
DDR_A_DQS6

DDR_A_D50
DDR_A_D51 DDR_A_D55

DDR_A_D56
DDR_A_D57

DDR_A_DM7
DDR_A_D58

DDR_A_D59
SB_CK_SDAT

SB_CK_SCLK

+3VS

1

C104

0.1U_0402_16V4Z

2

5

VSS

5

DQ0

7

DQ1

9

VSS

11

DQS0#

13

DQS0

15

VSS

17

DQ2

19

DQ3

21

VSS

23

DQ8

25

DQ9

27

VSS

29

DQS1#

31

DQS1

33

VSS

35

DQ10

37

DQ11

39

VSS

41

VSS

43

DQ16

45

DQ17

47

VSS

49

DQS2#

51

DQS2

53

VSS

55

DQ18

57

DQ19

59

VSS

61

DQ24

63

DQ25

65

VSS

67

DM3

69

NC

71

VSS

73

DQ26

75

DQ27

77

VSS

79

CKE0

81

VDD

83

NC

85

BA2

87

VDD

89

A12

91

A9

93

A8

95

VDD

97

A5

99

A3

101

A1

103

VDD

105

A10/AP

107

BA0

109

WE#

111

VDD

113

CAS#

115

NC/S1#

117

VDD

119

NC/ODT1

121

VSS

123

DQ32

125

DQ33

127

VSS

129

DQS4#

131

DQS4

133

VSS

135

DQ34

137

DQ35

139

VSS

141

DQ40

143

DQ41

145

VSS

147

DM5

149

VSS

151

DQ42

153

DQ43

155

VSS

157

DQ48

159

DQ49

161

VSS

163

NC,TEST

165

VSS

167

DQS6#

169

DQS6

171

VSS

173

DQ50

175

DQ51

177

VSS

179

DQ56

181

DQ57

183

VSS

185

DM7

187

VSS

189

DQ58

191

DQ59

193

VSS

195

SDA

197

SCL

199

VDDSPD

P-TWO_A5692C-A0G16

VSS
DQ4
DQ5
VSS
DM0
VSS
DQ6
DQ7

VSS
DQ12
DQ13

VSS

DM1

VSS

CK0
CK0#

VSS
DQ14
DQ15

VSS

VSS
DQ20
DQ21

VSS

DM2

VSS
DQ22
DQ23

VSS
DQ28
DQ29

VSS

DQS3#

DQS3

VSS
DQ30
DQ31

VSS

NC/CKE1

VDD

NC/A15
NC/A14

VDD

VDD

VDD

BA1
RAS#

VDD
ODT0

NC/A13

VDD

VSS
DQ36
DQ37

VSS

DM4

VSS
DQ38
DQ39

VSS
DQ44
DQ45

VSS

DQS5#

DQS5

VSS
DQ46
DQ47

VSS
DQ52
DQ53

VSS

CK1
CK1#

VSS

DM6

VSS
DQ54
DQ55

VSS
DQ60
DQ61

VSS

DQS7#

DQS7

VSS
DQ62
DQ63

VSS

SAO

SA1

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

42
44
46
48
50

NC

52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90

A11

92

A7

94

A6

96
98

A4

100

A2

102

A0

104
106
108
110

S0#

112
114
116
118
120

NC

122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200

4

DDR_A_D4
DDR_A_D5

DDR_A_DM0
DDR_A_D6

DDR_A_D7
DDR_A_D12

DDR_A_D13
DDR_A_DM1
DDR_A_CLK1

DDR_A_CLK#1
DDR_A_D14

DDR_A_D15

DDR_A_D20
DDR_A_D21

DDR_A_DM2

DDR_A_D23
DDR_A_D28

DDR_A_D29
DDR_A_DQS#3

DDR_A_DQS3
DDR_A_D30

DDR_A_D31
DDR_CKE1_DIMMA
DDR_A_MA15

DDR_A_MA14
DDR_A_MA11

DDR_A_MA7
DDR_A_MA6DDR_A_MA8

DDR_A_MA4
DDR_A_MA2
DDR_A_MA0

DDR_A_BS#1
DDR_A_RAS#
DDR_CS0_DIMMA#

DDR_A_ODT0
DDR_A_MA13

DDR_CS3_DIMMA#
DDR_A_D36

DDR_A_D37
DDR_A_DM4
DDR_A_D38

DDR_A_D39
DDR_A_D44

DDR_A_D45
DDR_A_DQS#5

DDR_A_DQS5
DDR_A_D46

DDR_A_D52

DDR_A_CLK2
DDR_A_CLK#2

DDR_A_DM6
DDR_A_D54

DDR_A_D60
DDR_A_D61

DDR_A_DQS#7
DDR_A_DQS7

DDR_A_D62
DDR_A_D63

R77 10K_0402_5%

1 2

R78 10K_0402_5%

1 2

DDR_A_CLK1 <6>
DDR_A_CLK#1 <6>

DDR_CKE1_DIMMA <6>

DDR_A_BS#1 <6>
DDR_A_RAS# <6>
DDR_CS0_DIMMA# <6>

DDR_A_ODT0 <6>

DDR_CS3_DIMMA# <6>

DDR_A_CLK2 <6>
DDR_A_CLK#2 <6>

0.1U_0402_16V4Z

C77

1

4.7U_0805_10V4Z

1

2

2

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C78

3

12

R45

1K_0402_1%

12

R46

1K_0402_1%

DDR_A_MA15
DDR_A_MA14
DDR_A_MA13
DDR_A_MA12
DDR_A_MA11
DDR_A_MA10
DDR_A_MA9
DDR_A_MA8
DDR_A_MA7
DDR_A_MA6
DDR_A_MA5
DDR_A_MA4
DDR_A_MA3
DDR_A_MA2
DDR_A_MA1
DDR_A_MA0

DDR_A_BS#2
DDR_A_BS#1
DDR_A_BS#0

DDR_A_CAS#
DDR_A_WE#
DDR_A_RAS#

DDR_CKE1_DIMMA
DDR_CKE0_DIMMA

DDR_CS3_DIMMA#
DDR_CS2_DIMMA#
DDR_CS1_DIMMA#
DDR_CS0_DIMMA#

DDR_A_ODT1
DDR_A_ODT0

+0.9V

2005/10/11 2006/10/11

DDR_A_D[0..63]<6>
DDR_A_DM[0..7]<6>

DDR_A_DQS[0..7]<6>
DDR_A_MA[0..15]<6>

DDR_A_DQS#[0..7]<6>

4.7U_0805_10V4Z

4.7U_0805_10V4Z

1

C79

2

Layout Note:
Place one cap close to every 2 pullup
resistors terminated to +0.9V

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

2

C89

R47 47_0402_5%

1 2

R48 47_0402_5%

1 2

R49 47_0402_5%

1 2

R50 47_0402_5%

1 2

R51 47_0402_5%

1 2

R52 47_0402_5%

1 2

R53 47_0402_5%

1 2

R54 47_0402_5%

1 2

R55 47_0402_5%

1 2

R56 47_0402_5%

1 2

R57 47_0402_5%

1 2

R58 47_0402_5%

1 2

R59 47_0402_5%

1 2

R60 47_0402_5%

1 2

R61 47_0402_5%

1 2

R62 47_0402_5%

1 2

R63 47_0402_5%

1 2

R64 47_0402_5%

1 2

R65 47_0402_5%

1 2

R66 47_0402_5%

1 2

R67 47_0402_5%

1 2

R68 47_0402_5%

1 2

R69 47_0402_5%

1 2

R70 47_0402_5%

1 2

R71 47_0402_5%

1 2

R72 47_0402_5%

1 2

R73 47_0402_5%

1 2

R74 47_0402_5%

1 2

R75 47_0402_5%

1 2

R76 47_0402_5%

1 2

4.7U_0805_10V4Z

1

1

C80

2

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

2

2

C90

C91

+0.9V

Compal Secret Data

Deciphered Date

DDR_A_D[0..63]
DDR_A_DM[0..7]
DDR_A_DQS[0..7]
DDR_A_MA[0..15]
DDR_A_DQS#[0..7]

+1.8V

4.7U_0805_10V4Z

4.7U_0805_10V4Z

1

C82

C81

2

0.1U_0402_16V4Z

1

1

2

2

C92

C93

Layout Note:
Place one cap close to every 2 pullup
resistors terminated to +0.9V

4.7U_0805_10V4Z

1

1

C83

C84

2

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

2

2

C94

C95

0.1U_0402_16V4Z

+0.9V

2

4.7U_0805_10V4Z

4.7U_0805_10V4Z

1

C85

2

0.1U_0402_16V4Z

1

1

2

2

C97

C96

11/3 Modify

0.1U_0402_16V4Z

1

2

C926

Layout Note:
Place one 0. 1 u F c ap c l ose to every 2 pullup
resistors terminated to +0.9V

4.7U_0805_10V4Z

1

C86

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

2

C98

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

2

2

C927

C928

Title

Size Docum ent Number Rev

Custom
Date: Sheet

4.7U_0805_10V4Z

1

C87

2

0.1U_0402_16V4Z

1

1

2

2

C100

C99

0.1U_0402_16V4Z

1

2

C929

1

2

C930

1

1

+

C802

C88

220U_D2_4VM

2

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

C931

1

+

2

2

C102

C103

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

2

2

C932

C933

1

2

C101

1

2

Compal Electronics, inc.

SCHEMATIC, M/B LA-3151P

401412

星期四 三月

1

11/01 modify

1

C925
150U_D2_6.3VM

2

+1.8V

955, 09, 2006

B

of

5

4

3

2

1

+DIMM_VREF+1.8V+1.8V

0.1U_0402_16V4Z

C105

4.7U_0805_10V4Z

JP2

1

VREF

3

DDR_B_D0

D D

C C

DDR_CKE0_DIMMB<6>
DDR_CS2_DIMMB#<6>

DDR_B_BS#2<6>

DDR_B_BS#0<6>
DDR_B_WE#<6>

DDR_B_CAS#<6>
DDR_CS1_DIMMB#<6>

DDR_B_ODT1<6>

B B

A A

SB_CK_SDAT<9,15,23>
SB_CK_SCLK<9,15,23>

DDR_B_D1
DDR_B_DQS#0

DDR_B_DQS0
DDR_B_D2

DDR_B_D3
DDR_B_D8

DDR_B_D9
DDR_B_DQS#1

DDR_B_DQS1
DDR_B_D10

DDR_B_D11

DDR_B_D16
DDR_B_D17

DDR_B_DQS#2
DDR_B_DQS2

DDR_B_D18 DDR_B_D22
DDR_B_D19

DDR_B_D24
DDR_B_D25

DDR_B_DM3

DDR_B_D26
DDR_B_D27

DDR_CKE0_DIMMB
DDR_CS2_DIMMB#

DDR_B_BS#2
DDR_B_MA12

DDR_B_MA9

DDR_B_MA5
DDR_B_MA3
DDR_B_MA1

DDR_B_MA10
DDR_B_BS#0
DDR_B_WE#

DDR_B_CAS#
DDR_CS1_DIMMB#

DDR_B_ODT1
DDR_B_D32

DDR_B_D33
DDR_B_DQS#4

DDR_B_DQS4
DDR_B_D34

DDR_B_D35
DDR_B_D40

DDR_B_D41
DDR_B_DM5
DDR_B_D42

DDR_B_D43 DDR_B_D47
DDR_B_D48

DDR_B_D49 DDR_B_D53

DDR_B_DQS#6
DDR_B_DQS6

DDR_B_D50
DDR_B_D51 DDR_B_D55

DDR_B_D56
DDR_B_D57

DDR_B_DM7
DDR_B_D58

DDR_B_D59
SB_CK_SDAT

SB_CK_SCLK

+3VS

1

C132

0.1U_0402_16V4Z

2

5

VSS

5

DQ0

7

DQ1

9

VSS

11

DQS0#

13

DQS0

15

VSS

17

DQ2

19

DQ3

21

VSS

23

DQ8

25

DQ9

27

VSS

29

DQS1#

31

DQS1

33

VSS

35

DQ10

37

DQ11

39

VSS

41

VSS

43

DQ16

45

DQ17

47

VSS

49

DQS2#

51

DQS2

53

VSS

55

DQ18

57

DQ19

59

VSS

61

DQ24

63

DQ25

65

VSS

67

DM3

69

NC

71

VSS

73

DQ26

75

DQ27

77

VSS

79

CKE0

81

VDD

83

NC

85

BA2

87

VDD

89

A12

91

A9

93

A8

95

VDD

97

A5

99

A3

101

A1

103

VDD

105

A10/AP

107

BA0

109

WE#

111

VDD

113

CAS#

115

NC/S1#

117

VDD

119

NC/ODT1

121

VSS

123

DQ32

125

DQ33

127

VSS

129

DQS4#

131

DQS4

133

VSS

135

DQ34

137

DQ35

139

VSS

141

DQ40

143

DQ41

145

VSS

147

DM5

149

VSS

151

DQ42

153

DQ43

155

VSS

157

DQ48

159

DQ49

161

VSS

163

NC,TEST

165

VSS

167

DQS6#

169

DQS6

171

VSS

173

DQ50

175

DQ51

177

VSS

179

DQ56

181

DQ57

183

VSS

185

DM7

187

VSS

189

DQ58

191

DQ59

193

VSS

195

SDA

197

SCL

199

VDDSPD

P-TWO_A5652C-A0G16

VSS
DQ4
DQ5
VSS
DM0
VSS
DQ6
DQ7

VSS
DQ12
DQ13

VSS

DM1

VSS

CK0
CK0#

VSS
DQ14
DQ15

VSS

VSS
DQ20
DQ21

VSS

DM2

VSS
DQ22
DQ23

VSS
DQ28
DQ29

VSS

DQS3#

DQS3

VSS
DQ30
DQ31

VSS

NC/CKE1

VDD

NC/A15
NC/A14

VDD

VDD

VDD

BA1
RAS#

VDD
ODT0

NC/A13

VDD

VSS
DQ36
DQ37

VSS

DM4

VSS
DQ38
DQ39

VSS
DQ44
DQ45

VSS

DQS5#

DQS5

VSS
DQ46
DQ47

VSS
DQ52
DQ53

VSS

CK1
CK1#

VSS

DM6

VSS
DQ54
DQ55

VSS
DQ60
DQ61

VSS

DQS7#

DQS7

VSS
DQ62
DQ63

VSS

SAO

SA1

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

42
44
46
48
50

NC

52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90

A11

92

A7

94

A6

96
98

A4

100

A2

102

A0

104
106
108
110

S0#

112
114
116
118
120

NC

122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200

4

DDR_B_D4
DDR_B_D5

DDR_B_DM0
DDR_B_D6

DDR_B_D7
DDR_B_D12

DDR_B_D13
DDR_B_DM1
DDR_B_CLK1

DDR_B_CLK#1
DDR_B_D14

DDR_B_D15

DDR_B_D20
DDR_B_D21

DDR_B_DM2

DDR_B_D23
DDR_B_D28

DDR_B_D29
DDR_B_DQS#3

DDR_B_DQS3
DDR_B_D30

DDR_B_D31
DDR_CKE1_DIMMB
DDR_B_MA15

DDR_B_MA14
DDR_B_MA11

DDR_B_MA7
DDR_B_MA6DDR_B_MA8

DDR_B_MA4
DDR_B_MA2
DDR_B_MA0

DDR_B_BS#1
DDR_B_RAS#
DDR_CS0_DIMMB#

DDR_B_ODT0
DDR_B_MA13

DDR_CS3_DIMMB#
DDR_B_D36

DDR_B_D37
DDR_B_DM4
DDR_B_D38

DDR_B_D39
DDR_B_D44

DDR_B_D45
DDR_B_DQS#5

DDR_B_DQS5
DDR_B_D46

DDR_B_D52

DDR_B_CLK2
DDR_B_CLK#2

DDR_B_DM6
DDR_B_D54

DDR_B_D60
DDR_B_D61

DDR_B_DQS#7
DDR_B_DQS7

DDR_B_D62
DDR_B_D63

R109 10K_0402_5%

1 2

R110 10K_0402_5%

1 2

1

2

DDR_B_CLK1 <6>
DDR_B_CLK#1 <6>

DDR_CKE1_DIMMB <6>

DDR_B_BS#1 <6>
DDR_B_RAS# <6>
DDR_CS0_DIMMB# <6>

DDR_B_ODT0 <6>

DDR_CS3_DIMMB# <6>

DDR_B_CLK2 <6>
DDR_B_CLK#2 <6>

+3VS

C106

1

2

4.7U_0805_10V4Z

1

C107

2

Layout Note:
Place one cap close to every 2 pullup
resistors terminated to +0.9V

+0.9V

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

2

C117

DDR_B_MA15
DDR_B_MA14
DDR_B_MA13
DDR_B_MA12
DDR_B_MA11
DDR_B_MA10
DDR_B_MA9
DDR_B_MA8
DDR_B_MA7
DDR_B_MA6
DDR_B_MA5
DDR_B_MA4
DDR_B_MA3
DDR_B_MA2
DDR_B_MA1
DDR_B_MA0

DDR_B_BS#2
DDR_B_BS#1
DDR_B_BS#0

DDR_B_CAS#
DDR_B_WE#
DDR_B_RAS#

DDR_CKE1_DIMMB
DDR_CKE0_DIMMB

DDR_CS3_DIMMB#
DDR_CS2_DIMMB#
DDR_CS1_DIMMB#
DDR_CS0_DIMMB#

DDR_B_ODT1
DDR_B_ODT0

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/10/11 2006/10/11

DDR_B_D[0..63]<6>
DDR_B_DM[0..7]<6>

DDR_B_DQS[0..7]<6>
DDR_B_MA[0..15]<6>

DDR_B_DQS#[0..7]<6>

4.7U_0805_10V4Z

4.7U_0805_10V4Z

1

1

C108

2

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

1

2

2

2

C118

C119

R79 47_0402_5%
R80 47_0402_5%
R81 47_0402_5%
R82 47_0402_5%
R83 47_0402_5%
R84 47_0402_5%
R85 47_0402_5%
R86 47_0402_5%
R87 47_0402_5%
R88 47_0402_5%
R89 47_0402_5%
R90 47_0402_5%
R91 47_0402_5%
R92 47_0402_5%
R93 47_0402_5%
R94 47_0402_5%

R95 47_0402_5%
R96 47_0402_5%
R97 47_0402_5%

R98 47_0402_5%
R99 47_0402_5%
R100 47_0402_5%

R101 47_0402_5%
R102 47_0402_5%

R103 47_0402_5%
R104 47_0402_5%
R105 47_0402_5%
R106 47_0402_5%

R107 47_0402_5%
R108 47_0402_5%

Compal Secret Data

Deciphered Date

4.7U_0805_10V4Z

1

C110

C109

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

2

C120

C121

Layout Note:
Place one cap close to every 2 pullup
resistors terminated to +0.9V

1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2

1 2
1 2
1 2

1 2
1 2
1 2

1 2
1 2

1 2
1 2
1 2
1 2

1 2
1 2

4.7U_0805_10V4Z

1

2

1

2

C122

2

DDR_B_D[0..63]
DDR_B_DM[0..7]
DDR_B_DQS[0..7]
DDR_B_MA[0..15]
DDR_B_DQS#[0..7]

4.7U_0805_10V4Z

C111

0.1U_0402_16V4Z

1

2

C123

1

2

0.1U_0402_16V4Z

+0.9V

+1.8V

4.7U_0805_10V4Z

4.7U_0805_10V4Z

1

1

C113

C112

0.1U_0402_16V4Z

1

2

C124

+0.9V

2

1

2

C125

2

0.1U_0402_16V4Z

1

2

C126

11/3 Modify

0.1U_0402_16V4Z

1

2

C934

C114

4.7U_0805_10V4Z

4.7U_0805_10V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

Layout Note:
Place one 0. 1 u F c ap c l ose to every 2 pullup
resistors te r m inated to +0.9V

Size Docum ent Number Rev

Custom
Date: Sheet

1

1

C116

C115

2

2

1

2

C127

1

2

C935

Title

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

2

C128

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

2

C936

0.1U_0402_16V4Z

1

1

2

C129

1

2

C937

1

2

2

C130

C131

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

2

2

C938

C939

Compal Electronics, inc.

SCHEMATIC, M/B LA-3151P

401412

星期四 三月

1

+1.8V

0.1U_0402_16V4Z

1

1

2

2

C940

C941

of

10 55, 09, 2006

B

5

D D

4

3

2

1

H_CADOP[0..15]
H_CADON[0..15] H_CADIN[0..15]

C C

H_CLKOP1<5>

H_CLKON1<5>

H_CLKOP0<5>

H_CLKON0<5>

B B

H_CTLOP0<5>
H_CTLON0<5>

R111 49.9_0402_1%
R113 49.9_0402_1%

+1.2V_HT

1 2
1 2

H_CADOP[0..15] <5> H_CADIP[0..15]<5>
H_CADON[0..15] <5>

H_CADOP15
H_CADON15
H_CADOP14
H_CADON14
H_CADOP13

H_CADOP12
H_CADON12
H_CADOP11
H_CADON11
H_CADOP10
H_CADON10
H_CADOP9
H_CADON9
H_CADOP8
H_CADON8

H_CADOP7
H_CADON7
H_CADOP6
H_CADON6
H_CADOP5
H_CADON5
H_CADOP4
H_CADON4
H_CADOP3
H_CADON3
H_CADOP2
H_CADON2
H_CADOP1
H_CADON1
H_CADOP0
H_CADON0

H_CLKOP1
H_CLKON1

H_CLKON0

H_CTLON0

HT_RXCALP
HT_RXCALN

U58A

R19

HT_RXCAD15P

R18

HT_RXCAD15N

R21

HT_RXCAD14P

R22

HT_RXCAD14N

U22

HT_RXCAD13P

U21

HT_RXCAD13N

U18

HT_RXCAD12P

U19

HT_RXCAD12N

W19

HT_RXCAD11P

W20

HT_RXCAD11N

AC21

HT_RXCAD10P

AB22

HT_RXCAD10N

AB20

HT_RXCAD9P

AA20

HT_RXCAD9N

AA19

HT_RXCAD8P

Y19

HT_RXCAD8N

T24

HT_RXCAD7P

R25

HT_RXCAD7N

U25

HT_RXCAD6P

U24

HT_RXCAD6N

V23

HT_RXCAD5P

U23

HT_RXCAD5N

V24

HT_RXCAD4P

V25

HT_RXCAD4N

AA25

HT_RXCAD3P

AA24

HT_RXCAD3N

AB23

HT_RXCAD2P

AA23

HT_RXCAD2N

AB24

HT_RXCAD1P

AB25

HT_RXCAD1N

AC24

HT_RXCAD0P

AC25

HT_RXCAD0N

W21

HT_RXCLK1P

W22

HT_RXCLK1N

Y24

HT_RXCLK0P

W25

HT_RXCLK0N

P24

HT_RXCTLP

P25

HT_RXCTLN

A24

HT_RXCALP

C24

HT_RXCALN

215NSA4ALA11FG RS485M_BGA465

PART 1 OF 5

HT_TXCAD15P
HT_TXCAD15N
HT_TXCAD14P
HT_TXCAD14N
HT_TXCAD13P
HT_TXCAD13N
HT_TXCAD12P
HT_TXCAD12N
HT_TXCAD11P
HT_TXCAD11N
HT_TXCAD10P
HT_TXCAD10N

HT_TXCAD9P
HT_TXCAD9N
HT_TXCAD8P
HT_TXCAD8N

HT_TXCAD7P
HT_TXCAD7N
HT_TXCAD6P
HT_TXCAD6N
HT_TXCAD5P
HT_TXCAD5N
HT_TXCAD4P
HT_TXCAD4N
HT_TXCAD3P
HT_TXCAD3N
HT_TXCAD2P
HT_TXCAD2N
HT_TXCAD1P
HT_TXCAD1N
HT_TXCAD0P
HT_TXCAD0N

HT_TXCLK1P

HT_TXCLK1N

HYPER TRANSPORT CPU

I/F

HT_TXCLK0P

HT_TXCLK0N

HT_TXCTLP
HT_TXCTLN

HT_TXCALP
HT_TXCALN

P21
P22
P18
P19
M22
M21
M18
M19
L18
L19
G22
G21
J20
J21
F21
F22

N24
N25
L25
M24
K25
K24
J23
K23
G25
H24
F25
F24
E23
F23
E24
E25

L21
L22

J24
J25

N23
P23

C25
D24

H_CADIN[0..15]<5>

H_CADIP15
H_CADIN15
H_CADIP14
H_CADIN14
H_CADIP13
H_CADIN13H_CADON13
H_CADIP12
H_CADIN12
H_CADIP11
H_CADIN11
H_CADIP10
H_CADIN10
H_CADIP9
H_CADIN9
H_CADIP8
H_CADIN8

H_CADIP7
H_CADIN7
H_CADIP6
H_CADIN6
H_CADIP5
H_CADIN5
H_CADIP4
H_CADIN4
H_CADIP3
H_CADIN3
H_CADIP2
H_CADIN2
H_CADIP1
H_CADIN1
H_CADIP0
H_CADIN0

H_CLKIP1
H_CLKIN1

H_CLKIP0H_CLKOP0
H_CLKIN0

H_CTLIP0H_CTLOP0
H_CTLIN0

HT_TXCALP
HT_TXCALN

1 2

R112

100_0402_1%

H_CADIP[0..15]

H_CLKIP1 <5>
H_CLKIN1 <5>

H_CLKIP0 <5>
H_CLKIN0 <5>

H_CTLIP0 <5>
H_CTLIN0 <5>

A A

Security Classification

Issued Date

THIS SHEET OF ENG INEE RIN G DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY O R DIS CLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/03/08 2006/03/08

Compal Secret Data

Deciphered Date

Compal Electronics, inc.

Title

SCHEMATIC, M/B LA-3151P

Size Document Number R ev

Custom

401412

Date: Sheet

星期四 三

09, 2006

2

月

11 55,

1

B

of

5

4

3

2

1

PCIE_GTX_C_MRX_P[0..15]<16>

D D

C C

PCIE_MRX_PTX_P0<39>
PCIE_MRX_PTX_N0<39>

PCIE_MRX_PTX_P1<36>
PCIE_MRX_PTX_N1<36>

B B

PCIE_GTX_C_MRX_N[0..15]<16>

10KOhm FOR RS485

R214:

1.47KOhm FOR RS690

8.25KOhm FOR RS485

R213:

DNI FOR RS690

R114 0_0402_5%

1 2

R115 0_0402_5%

1 2

R116 0_0402_5%

1 2

R117 0_0402_5%

1 2

PCIE_GTX_C_MRX_P[0..15]
PCIE_GTX_C_MRX_N[0..15]

PCIE_GTX_C_MRX_P0
PCIE_GTX_C_MRX_N0
PCIE_GTX_C_MRX_P1
PCIE_GTX_C_MRX_N1
PCIE_GTX_C_MRX_P2
PCIE_GTX_C_MRX_N2
PCIE_GTX_C_MRX_P3
PCIE_GTX_C_MRX_N3
PCIE_GTX_C_MRX_P4
PCIE_GTX_C_MRX_N4
PCIE_GTX_C_MRX_P5
PCIE_GTX_C_MRX_N5
PCIE_GTX_C_MRX_P6
PCIE_GTX_C_MRX_N6
PCIE_GTX_C_MRX_P7
PCIE_GTX_C_MRX_N7
PCIE_GTX_C_MRX_P8
PCIE_GTX_C_MRX_N8
PCIE_GTX_C_MRX_P9
PCIE_GTX_C_MRX_N9
PCIE_GTX_C_MRX_P10
PCIE_GTX_C_MRX_N10
PCIE_GTX_C_MRX_P11
PCIE_GTX_C_MRX_N11
PCIE_GTX_C_MRX_P12
PCIE_GTX_C_MRX_N12
PCIE_GTX_C_MRX_P13
PCIE_GTX_C_MRX_N13
PCIE_GTX_C_MRX_P14
PCIE_GTX_C_MRX_N14
PCIE_GTX_C_MRX_P15
PCIE_GTX_C_MRX_N15

A_MRX_STX_P0<22>
A_MRX_STX_N0<22>

A_MRX_STX_P1<22>
A_MRX_STX_N1<22>

R118 10K_0402_1%

1 2

R120 8.25K_0402_1%

1 2

U58B

G5

GFX_RX0P

G4

GFX_RX0N

J8

GFX_RX1P

J7

GFX_RX1N

J4

GFX_RX2P

J5

GFX_RX2N

L8

GFX_RX3P

L7

GFX_RX3N

L4

GFX_RX4P

L5

GFX_RX4N

M8

GFX_RX5P

M7

GFX_RX5N

M4

GFX_RX6P

M5

GFX_RX6N

P8

GFX_RX7P

P7

GFX_RX7N

P4

GFX_RX8P

P5

GFX_RX8N

R4

GFX_RX9P

R5

GFX_RX9N

R7

GFX_RX10P

R8

GFX_RX10N

U4

GFX_RX11P

U5

GFX_RX11N

W4

GFX_RX12P

W5

GFX_RX12N

Y4

GFX_RX13P

Y5

GFX_RX13N

V9

GFX_RX14P

W9

GFX_RX14N

AB7

GFX_RX15P

AB6

PCIE_MRX_PTX_P0_R
PCIE_MRX_PTX_N0_R

PCIE_MRX_PTX_P1_R
PCIE_MRX_PTX_N1_R

A_MRX_STX_P0
A_MRX_STX_N0 A_MTX_SRX_N0

A_MRX_STX_P1
A_MRX_STX_N1

GFX_RX15N

W11

GPP_RX0P

W12

GPP_RX0N

AA11

GPP_RX1P

AB11

GPP_RX1N

Y7

GPP_RX2P

AA7

GPP_RX2N

AB9

GPP_RX3P

AA9

GPP_RX3N

W14

SB_RX0P

W15

SB_RX0N

AB12

SB_RX1P

AA12

SB_RX1N

AA14

PCEH_ISET

AB14

PCEH_TXISET

215NSA4ALA11FG RS485M_BGA465

PART 2 OF 5

PCIE I/F GFX

PCIE I/F GPP

PCIE I/F SB

GFX_TX0P
GFX_TX0N
GFX_TX1P
GFX_TX1N
GFX_TX2P
GFX_TX2N
GFX_TX3P
GFX_TX3N
GFX_TX4P
GFX_TX4N
GFX_TX5P
GFX_TX5N
GFX_TX6P
GFX_TX6N
GFX_TX7P
GFX_TX7N
GFX_TX8P
GFX_TX8N
GFX_TX9P

GFX_TX9N
GFX_TX10P
GFX_TX10N
GFX_TX11P
GFX_TX11N
GFX_TX12P
GFX_TX12N
GFX_TX13P
GFX_TX13N
GFX_TX14P
GFX_TX14N
GFX_TX15P
GFX_TX15N

GPP_TX0P

GPP_TX0N

GPP_TX1P

GPP_TX1N

GPP_TX2P

GPP_TX2N

GPP_TX3P

GPP_TX3N

SB_TX0P

SB_TX0N

SB_TX1P

SB_TX1N

PCEH_PCAL
PCEH_NCAL

PCIE_MTX_GRX_P0

J1

PCIE_MTX_GRX_N0

H2

PCIE_MTX_GRX_P1

K2

PCIE_MTX_GRX_N1

K1

PCIE_MTX_GRX_P2

K3

PCIE_MTX_GRX_N2

L3

PCIE_MTX_GRX_P3

L1

PCIE_MTX_GRX_N3

L2

PCIE_MTX_GRX_P4

N2

PCIE_MTX_GRX_N4

N1

PCIE_MTX_GRX_P5

P2

PCIE_MTX_GRX_N5

P1

PCIE_MTX_GRX_P6

P3

PCIE_MTX_GRX_N6

R3

PCIE_MTX_GRX_P7

R1

PCIE_MTX_GRX_N7

R2

PCIE_MTX_GRX_P8

T2

PCIE_MTX_GRX_N8

U1

PCIE_MTX_GRX_P9

V2

PCIE_MTX_GRX_N9

V1

PCIE_MTX_GRX_P10

V3

PCIE_MTX_GRX_N10

W3

PCIE_MTX_GRX_P11

W1

PCIE_MTX_GRX_N11

W2

PCIE_MTX_GRX_P12

Y2

PCIE_MTX_GRX_N12

AA1

PCIE_MTX_GRX_P13

AA2

PCIE_MTX_GRX_N13

AB2

PCIE_MTX_GRX_P14

AB1

PCIE_MTX_GRX_N14

AC1

PCIE_MTX_GRX_P15

AE3

PCIE_MTX_GRX_N15

AE4

PCIE_MTX_PRX_P0

AD8

PCIE_MTX_PRX_N0

AE8

PCIE_MTX_PRX_P1

AD7

PCIE_MTX_PRX_N1

AE7
AD4

AE5
AD5

AD6
AE9

AD10
AC8

A_MTX_SRX_N1

AD9

R119 150_0402_1%

AD11

R121 100_0402_1%

AE11

R119:

R121:

1 2
1 2

150 Ohm FOR RS485
562 Ohm FOR RS690

100 Ohm FOR RS485
2KOhm FOR RS690

C134 0.1U_0402_16V7K

1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2

1 2

1 2

1 2

C136 0.1U_0402_16V7K
C138 0.1U_0402_16V7K
C140 0.1U_0402_16V7K
C142 0.1U_0402_16V7K
C144 0.1U_0402_16V7K
C146 0.1U_0402_16V7K
C148 0.1U_0402_16V7K
C150 0.1U_0402_16V7K
C152 0.1U_0402_16V7K
C154 0.1U_0402_16V7K
C156 0.1U_0402_16V7K
C158 0.1U_0402_16V7K
C160 0.1U_0402_16V7K
C162 0.1U_0402_16V7K
C164 0.1U_0402_16V7K
C165 0.1U_0402_16V7K

C167 0.1U_0402_16V7K

C169 0.1U_0402_16V7K

C171 0.1U_0402_16V7K

ATI side check , use +1.2V or not

PCIE_MTX_C_GRX_P[0..15]<16>
PCIE_MTX_C_GRX_N[0..15]<16>

C133 0.1U_0402_16V7K

1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2

1 2

1 2

1 2

1 2

+1.2V_HT

C135 0.1U_0402_16V7K
C137 0.1U_0402_16V7K
C139 0.1U_0402_16V7K
C141 0.1U_0402_16V7K
C143 0.1U_0402_16V7K
C145 0.1U_0402_16V7K
C147 0.1U_0402_16V7K
C149 0.1U_0402_16V7K
C151 0.1U_0402_16V7K
C153 0.1U_0402_16V7K
C155 0.1U_0402_16V7K
C157 0.1U_0402_16V7K
C159 0.1U_0402_16V7K
C161 0.1U_0402_16V7K
C163 0.1U_0402_16V7K

C166 0.1U_0402_16V7K

C168 0.1U_0402_16V7K

C170 0.1U_0402_16V7K

C172 0.1U_0402_16V7K

PCIE_MTX_C_GRX_P[0..15]

PCIE_MTX_C_GRX_N[0..15]

PCIE_MTX_C_GRX_P0

PCIE_MTX_C_GRX_N0
PCIE_MTX_C_GRX_P1
PCIE_MTX_C_GRX_N1
PCIE_MTX_C_GRX_P2
PCIE_MTX_C_GRX_N2
PCIE_MTX_C_GRX_P3
PCIE_MTX_C_GRX_N3
PCIE_MTX_C_GRX_P4
PCIE_MTX_C_GRX_N4
PCIE_MTX_C_GRX_P5
PCIE_MTX_C_GRX_N5
PCIE_MTX_C_GRX_P6
PCIE_MTX_C_GRX_N6
PCIE_MTX_C_GRX_P7
PCIE_MTX_C_GRX_N7

PCIE_MTX_C_GRX_P8
PCIE_MTX_C_GRX_N8

PCIE_MTX_C_GRX_P9
PCIE_MTX_C_GRX_N9
PCIE_MTX_C_GRX_P10
PCIE_MTX_C_GRX_N10
PCIE_MTX_C_GRX_P11
PCIE_MTX_C_GRX_N11
PCIE_MTX_C_GRX_P12
PCIE_MTX_C_GRX_N12
PCIE_MTX_C_GRX_P13

PCIE_MTX_C_GRX_N13

PCIE_MTX_C_GRX_P14

PCIE_MTX_C_GRX_N14

PCIE_MTX_C_GRX_P15

PCIE_MTX_C_GRX_N15

PCIE_MTX_C_PRX_P0
PCIE_MTX_C_PRX_N0

PCIE_MTX_C_PRX_P1
PCIE_MTX_C_PRX_N1

A_MTX_C_SRX_P0A_MTX_SRX_P0
A_MTX_C_SRX_N0

A_MTX_C_SRX_P1A_MTX_SRX_P1
A_MTX_C_SRX_N1

PCIE_MTX_C_PRX_P0 <39>
PCIE_MTX_C_PRX_N0 <39>

PCIE_MTX_C_PRX_P1 <36>
PCIE_MTX_C_PRX_N1 <36>

A_MTX_C_SRX_P0 <22>
A_MTX_C_SRX_N0 <22>

A_MTX_C_SRX_P1 <22>
A_MTX_C_SRX_N1 <22>

A A

Security Classification

Issued Date

THIS SHEET OF ENG INEE RIN G DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY O R DIS CLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/03/08 2006/03/08

Compal Secret Data

Deciphered Date

Compal Electronics, inc.

Title

SCHEMATIC, M/B LA-3151P

Size Document Number R ev

Custom

401412

Date: Sheet

星期四 三

09, 2006

2

月

12 55,

1

B

of

5

4

3

2

1

ATI check , CRT / TV/ LVDS can delete or not when I use RX485

D D

Modify 11/29

+1.8VS

+1.8VS

MBK1608800YZF_0805

+1.8VS

C C

1 2

MBK1608800YZF_0805

Modify : 11/07

L63

1 2

L67

PLLVDD

1

C173

2

HTPVDD

1

C175

2

10U_0805_10V4Z

10U_0805_10V4Z

1

C174

4.7U_0805_10V4Z

2

1

C176

4.7U_0805_10V4Z

2

Modify : 11/07

+1.8VS

R810

10K_0402_5%

B

E

LDT_STOP#<7,23>

3 1

MMBT3904_SOT23

+1.8VS

+3VS

12

12

R125
1K_0402_5%

2

Q4

C

LOAD_ROM#: LOAD ROM ST RA P ENABLE

High, LOAD R O M STRAP DISABLE

B B

Low, LOAD ROM STRAP ENABLE

1 2

NB_PWRGD<42>

ALLOW_LDTSTOP<22>

NBSRC_CLKP<15>
NBSRC_CLKN<15>

SBLINK_CLKP<15>
SBLINK_CLKN<15>

R847

0_0603_5%

NB_RST#<16,22,27,33,36,41>

HTREFCLK<15>

NB_OSC<15>

R129

1 2

1

C948

2

R846

0_0603_5%

1 2

3K_0402_5%@

1

2

1U_0402_6.3V4Z@

R126 0_0402_5%

1 2

R128 2.7K_0402_5%@
R130 2.7K_0402_5%@

R131 2.7K_0402_5%@
R132 2.7K_0402_5%@
R133 2.7K_0402_5%@

BMREQ#<22>

12

R134

4.7K_0402_5%

+3VS

C947

1U_0402_6.3V4Z@

PLLVDD

HTPVDD

LDT_STOP#_NB

R127 10K_0402_5%

1 2
1 2

1 2
1 2
1 2

1 2

R809 0_0603_5%

1 2

R123 715_0402_1%@

12

DFT_GPIO0
LOAD_ROM#
DFT_GPIO2
DFT_GPIO3
DFT_GPIO4

T11PAD

T7PAD

DFT_GPIO5

T8PAD
T9PAD

T10PAD

D33 1N4148_SOT23

12

U58C

B22

AVDD1

C22

AVDD2

G17

AVSSN1

H17

AVSSN2

A20

AVDDDI

B20

AVSSDI

A21

AVDDQ

A22

AVSSQ

C21

C_R

C20

Y_G

D19

COMP_B

E19

RED

F19

GREEN

G19

BLUE

C6

DACVSYNC

A5

DACHSYNC

B21

RSET

B6

DACSCL

A6

DACSDA

A10

PLLVDD

B10

PLLVSS

B24

HTPVDD

B25

HTPVSS

C10

SYSRESET#

C11

POWERGOOD

C5

LDTSTOP#

B5

ALLOW_LDTSTOP

C23

HTTSTCLK

B23

HTREFCLK

C2

TVCLKIN

B11

OSCIN

A11

OSCOUT

F2

GFX_CLKP

E1

GFX_CLKN

G1

SB_CLKP

G2

SB_CLKN

D6

DFT_GPIO0

D7

DFT_GPIO1

C8

DFT_GPIO2

C7

DFT_GPIO3

B8

DFT_GPIO4

A8

DFT_GPIO5

B2

BMREQb

A2

I2C_CLK

B4

I2C_DATA

AA15

THERMALDIODE_P

AB15

THERMALDIODE_N

C14

TMDS_HPD

B3

DDC_DATA

C3

TESTMODE

A3

STRP_DATA

215NSA4ALA11FG RS485M_BGA465

PART 3 OF 5

CRT/TVOUT

PLL PWR

PM

CLOCKs

MIS.

TXOUT_L0P

TXOUT_L0N

TXOUT_L1P

TXOUT_L1N

TXOUT_L2P

TXOUT_L2N

TXOUT_L3P

TXOUT_L3N
TXOUT_U0P

TXOUT_U0N
TXOUT_U1P
TXOUT_U1N
TXOUT_U2P
TXOUT_U2N
TXOUT_U3P
TXOUT_U3N

TXCLK_LP
TXCLK_LN

TXCLK_UP

TXCLK_UN

LPVDD
LPVSS

LVDDR18D_1
LVDDR18D_2
LVDDR18A_1
LVDDR18A_2

LVSSR1
LVSSR3
LVSSR5
LVSSR6
LVSSR7
LVSSR8

LVSSR12
LVSSR13

LVDS_DIGON

LVDS_BLON
LVDS_BLEN

DVO_D0
DVO_D1
DVO_D2
DVO_D3
DVO_D4
DVO_D5
DVO_D6
DVO_D7
DVO_D8

DVO_D9
DVO_D10
DVO_D11

DVO_VSYNC

DVO_DE

DVO_HSYNC

DVO_IDCKP
DVO_IDCKN

B14
B15
B13
A13
H14
G14
D17
E17

A15
B16
C17
C18
B17
A17
A18
B18

E15
D15
H15
G15

D14
E14

A12
B12
C12
C13

A16
A14
D12
C19
C15
C16

F14
F15

E12
G12
F12

AD14
AD15
AE15
AD16
AE16
AC17
AD18
AE19
AD19
AE20
AD20
AE21

AD13
AC13
AE13
AE17
AD17

T4 PAD
T5 PAD
T6 PAD

C950
1U_0402_6.3V4Z@

1

2

Modify 11/29

R848

1 2

0_0603_5%

1

C949

1U_0402_6.3V4Z@

2

R849

1 2

0_0603_5%

R850

1 2

0_0603_5%

1

C951

1U_0402_6.3V4Z@

2

+1.8VS

+1.8VS

A A

Security Classification

Issued Date

THIS SHEET OF ENG INEE RIN G DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY O R DIS CLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/03/08 2006/03/08

Compal Secret Data

Deciphered Date

Compal Electronics, inc.

Title

SCHEMATIC, M/B LA-3151P

Size Document Number R ev

Custom

401412

Date: Sheet

星期四 三

09, 2006

2

月

13 55,

1

B

of

5

4

3

2

1

NB RS485 POWER STATES

Power Signal

VDDHT
VDDR
VDD18

D D

VDDC
VDDA18
VDDA12

AVDDDI
PLLVDD
HTPVDD
VDDR3
LPVDD
LVDDR18D

S3

S0

S1

ON

ON

OFF

ON

ON

OFF

ON

ON

OFF

ON

ON

OFF

ON

ON

OFF

ON

ON

OFF

ON

ON

OFFAVDD

ON

ON

OFF

ON

ON

OFF

ON

ON

OFF

ON

ON

OFF

ON

ON

OFF

ON

ON

OFF

S4/S5

OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF

G3

OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF

LVDDR18A OFFON ON OFF OFF

U58E

A25

VSS1

F11

AE18

M15

M11
M20
M23
M25

W23

AD25

W24

AC23

AC14
AC22

AE22

AE14

M17

AC15

AC16

M13

D23
G11

Y23
P11
R24

G23

N12
N14

P13
P20
P15
R12
R14
R20

Y25
U20

H25
Y22
D25

G24
H12
R23

T23
T25

R17
H23

A23
F17

E9

J22
J12

L12
L14
L20
L23

B7

L24

C4

D4

CURRENT MEASUREMENT

1

C181

2

10U_0805_10V4Z

1

C194

2

1U_0402_6.3V4Z

1

C205

2

1U_0402_6.3V4Z

+VDDA_12

1

C182

2

1U_0402_6.3V4Z

1

C195

2

1

C206

2

1U_0402_6.3V4Z

L69

1 2

KC FBM-L11-201209-221LMAT_0805

+1.2V_HT

1

C196

2

1U_0402_6.3V4Z

1

C207

2

1U_0402_6.3V4Z

+1.2V_HT

C C

KC FBM-L11-201209-221LMAT_0805

+1.8VS

1 2

MBK1608800YZF_0805

RS690: VDDA18=1.2V
RS485: VDDA18=1.8V

+1.8VS

L64

1 2

KC FBM-L11-201209-221LMAT_0805

+3VS

B B

+1.8VS

Modify 11/07 for EMI

+VDD_HT

L70

1 2

L2

1

2

3A bead

10U_0805_10V4Z

L3

1 2

MBK1608800YZF_0805

L4

1 2

MBK1608800YZF_0805

+VDDA_12

10U_0805_10V4Z

1

C183

C184

2

10U_0805_10V4Z

1

C190

2.2U_0603_6.3V6K

2

1

1

C198

2

2

10U_0805_10V4Z

VDDR3

1

C208

4.7U_0805_10V4Z

2

1U_0402_6.3V4Z

1

C209

@

2

1U_0402_6.3V4Z@

4.7U_0805_10V4Z

1

2

1

C185

2

1U_0402_6.3V4Z

VDD18

1

C200

C199

2

1U_0402_6.3V4Z

VDDR

1

C210

2

1U_0402_6.3V4Z@

1

C213

C214
1U_0402_6.3V4Z

2

1

C186

2

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1

C191

2.2U_0603_6.3V6K

2

1

C201

2

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1

C211

2

1

C187

2

1U_0402_6.3V4Z

1

C202

2

1U_0402_6.3V4Z

1

C188

2

VDDA18

1

C203

2

1U_0402_6.3V4Z

+1.2V_HT

1

2

1

C189
1U_0402_6.3V4Z

2

1

C204

2

+1.2V_HT
+1.2V_HT
+1.2V_HT

C212
10U_0805_10V4Z

Close to U58.M1

U58D

AE24
AD24
AD22
AB17
AE23

W17
AC18
AD21
AC19
AC20
AB19
AD23
AA17
AE25

AC3

AD2

AC12
AD12
AE12

AC11

Y17

AE2
AB3

AB4

AE1
E11

D11

D22

J14
J15

U7

W7

E7
F7
F9
G9

M1

PART 4 OF 5

VDD_HT1
VDD_HT2
VDD_HT5
VDD_HT6
VDD_HT9
VDD_HT10
VDD_HT11
VDD_HT12
VDD_HT13
VDD_HT14
VDD_HT15
VDD_HT16
VDD_HT17
VDD_HT18
VDD_HT19

VDD18_1
VDD18_2

VDDA18_1
VDDA18_2
VDDA18_3
VDDA18_4
VDDA18_5
VDDA18_6
VDDA18_7
VDDA18_8

VDDR3_2
VDDR3_1

VDDR_1
VDDR_2
VDDR_3

VDDA12/VDDPLL_1
VDDA12/VDDPLL_2
VSSA12/VSSPLL_1
VSSA12/VSSPLL_2

VDDHT_PKG
VDDA12_PKG1
VDDA12_PKG2

215NSA4ALA11FG RS485M_BGA465

VDDA_12_10
VDDA_12_11
VDDA_12_12

POWER

VDDA_12_1
VDDA_12_2
VDDA_12_3
VDDA_12_4
VDDA_12_5
VDDA_12_6
VDDA_12_7
VDDA_12_8
VDDA_12_9

VDDC_1
VDDC_2
VDDC_3
VDDC_4
VDDC_5
VDDC_6
VDDC_7
VDDC_8

VDDC_9
VDDC_10
VDDC_11
VDDC_12
VDDC_13
VDDC_14
VDDC_15
VDDC_16
VDDC_17
VDDC_18
VDDC_19
VDDC_20
VDDC_21
VDDC_22
VDDC_23
VDDC_24
VDDC_25
VDDC_26
VDDC_27
VDDC_28
VDDC_29
VDDC_30
VDDC_31
VDDC_32

D1
G7
E2
C1
E3
D2
M9
F4
B1
D3
L9
E6

L11
L13
L15
M12
R15
M14
N11
N13
N15
J11
H11
P12
P14
R11
R13
A19
B19
U11
U14
P17
L17
J19
D20
G20
A9
B9
C9
D9
A7
A4
U12
U15

1U_0402_6.3V4Z

1

C178

2

1U_0402_6.3V4Z

10U_0805_10V4Z

1

+

C803
220U_D2_4VM

2

1

C179

2

1

C192

2

10U_0805_10V4Z

1

C180

2

1U_0402_6.3V4Z

10U_0805_10V4Z

1

C193

2

1

C197
1U_0402_6.3V4Z

2

+1.2V_HT

PAR 5 OF 5

VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59

215NSA4ALA11FG RS485M_BGA465

GROUND

VSSA1
VSSA2
VSSA3
VSSA4
VSSA5
VSSA6
VSSA7
VSSA8

VSSA9
VSSA10
VSSA11
VSSA12
VSSA13
VSSA14
VSSA15
VSSA16
VSSA17
VSSA18
VSSA19
VSSA20
VSSA21
VSSA22
VSSA23
VSSA24
VSSA25
VSSA26
VSSA27
VSSA28
VSSA29
VSSA30
VSSA31
VSSA32
VSSA33
VSSA34
VSSA35
VSSA36
VSSA93
VSSA94
VSSA95
VSSA37
VSSA38
VSSA39
VSSA40
VSSA41
VSSA42
VSSA43
VSSA44
VSSA45

M3
V12
V11
V14
F3
V15
A1
H1
G3
J2
H3
AE10
J6
AE6
F1
L6
M2
M6
J3
P6
T1
N3
P9
R6
U2
T3
U3
U6
AC4
Y1
Y15
W6
AC2
Y3
Y9
Y11
Y12
Y14
AA3
R9
AD1
AC5
AC6
AC7
AD3
AC9
AC10
G6

RS485: 0 Ohm RESISTOR
RS690: 220 Ohm 500mA FERRITE BEAD

A A

Security Classification

Issued Date

THIS SHEET OF ENG INEE RIN G DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY O R DIS CLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/03/08 2006/03/08

Compal Secret Data

Deciphered Date

Compal Electronics, inc.

Title

SCHEMATIC, M/B LA-3151P

Size Document Number R ev

Custom

401412

Date: Sheet

星期四 三

09, 2006

2

月

14 55,

1

B

of

5

4

3

2

1

+3VS

L5

1 2

MBK2012121YZF_0805

D D

1- PLACE ALL SERIAL TERMINATION
RESISTORS CLOSE TO U800

2- PUT DECOUPLING CAPS CLOSE TO U800
POWER PIN

C C

ICH_SMBDATA<36,39>

B B

ICH_SMBCLK<36,39>

ICH_SMBDATA
ICH_SMBCLK

CLK_VDD

10U_0805_10V4Z

1

C215

2

0.1U_0402_16V4Z

CLK_VDD

12

R153
10K_0402_5%

1

C230

0.1U_0402_16V4Z

2

@

R192 0_0402_5%

1 2

R193 0_0402_5%

1 2

1

C216

2

0.1U_0402_16V4Z

+3VS

L7

1 2

MBK2012121YZF_0805

2.2U_0603_6.3V6K

+3VS

L8

1 2

MBK2012121YZF_0805

2.2U_0603_6.3V6K

Parallel Resonance Crystal

C228

1 2

33P_0402_50V8J

33P_0402_50V8J

1 2

C229

1

1

C217

2

0.1U_0402_16V4Z

C226

C227

Y1

14.31818MHz_20P_1BX14318BE1A

SB_CK_SCLK<9,10,23>
SB_CK_SDAT<9,10,23>

Ioh = 5 * Iref
(2.32mA)

1

C218

2

2

0.1U_0402_16V4Z

1

2

1

2

12

R148

@

1M_0402_5%

1 2

R154 0_0402_5%

SB_CK_SCLK
SB_CK_SDAT

Voh = 0.71V @ 60 ohm

SB_CK_SDAT
SB_CK_SCLK

1

C219

2

0.1U_0402_16V4Z

CLK_VDD

C220

0.1U_0402_16V4Z

12

R173
475_0402_1%

1 2

1

1

C221

2

2

0.1U_0402_16V4Z

U8

54
14
23
28
44

5

39

2

60
53

15
22
29
45

8

38

1

58

3
4

11
61

9

10

48

ICS951462AGLFT_TSSOP64

C222

0.1U_0402_16V4Z

VDDCPU
VDDSRC
VDDSRC
VDDSRC
VDDSRC
VDD48
VDDATIG
VDDREF
VDDHTT

GNDCPU
GNDSRC
GNDSRC
GNDSRC
GNDSRC
GND48
GNDATIG
GNDREF
GNDHTT

X1
X2

RESET_IN#
NC

SMBCLK
SMBDAT

IREF

1

C223

2

50

VDDA

49

GNDA

SRCCLKT6
SRCCLKC6
ATIGCLKT0
ATIGCLKC0
ATIGCLKT1
ATIGCLKC1
ATIGCLKT2
ATIGCLKC2
ATIGCLKT3
ATIGCLKC3

SRCCLKT5
SRCCLKC5

SRCCLKT4
SRCCLKC4

SRCCLKT3
SRCCLKC3

SRCCLKT2
SRCCLKC2

SRCCLKT0
SRCCLKC0

SRCCLKT1
SRCCLKC1

SRCCLKT7
SRCCLKC7

CLKREQA#
CLKREQB#
CLKREQC#

48MHz_1
48MHz_0

FS1/REF1
FS0/REF0
FS2/REF2
HTTCLK0

56
55
52
51

16
17
41
40
37
36
35
34
30
31
18
19
20
21
24
25
26
27
47
46
43
42
12
13

57
32
33

7
6

63
64
62
59

CPUCLK8T0

CPUCLK8C0

CPUCLK8T1

CPUCLK8C1

CLK_VDDA

2

C224

0.1U_0402_16V4Z

1

CPUCLK_EXT_R
CPUCLK#_EXT_R

SBLINK_CLKP_R
SBLINK_CLKN_R
NBSRC_CLKP_R
NBSRC_CLKN_R
GFX_CLKP_R
GFX_CLKN_R

R158 0_0402_5%
R171 0_0402_5%

CLK_48M_SIO_R
CLK_48M_USB_R

R140 47_0402_1%
R141 47_0402_1%

SBSRC_CLKP_R
SBSRC_CLKN_R
GPP_CLK4P_R
GPP_CLK4N_R
GPP_CLK0P_R
GPP_CLK0N_R

1 2
1 2

1 2
1 2

R142 33_0402_1%
R143 33_0402_1%
R144 33_0402_1%
R145 33_0402_1%
R146 33_0402_1%
R147 33_0402_1%

R149 33_0402_1%
R150 33_0402_1%
R151 33_0402_1%
R152 33_0402_1%
R155 33_0402_1%
R156 33_0402_1%

R175 33_0402_1%

1 2

R176 33_0402_1%

1 2

SB_OSCIN_R
FS0

1 2
1 2
1 2
1 2
1 2
1 2

1 2
1 2
1 2
1 2
1 2
1 2

EXP_CLKREQ# <39>

MINI1_CLKREQ# <36>

L6

1 2

MBK2012121YZF_0805

1

C225
10U_0805_10V4Z

2

R139

261_0402_1%

1 2

R180 8.2K_0402_5%

1 2

R182 8.2K_0402_5%

1 2

R184 8.2K_0402_5%

1 2

R186 33_0402_1%

1 2

R187 33_0402_1%

1 2

+3VS

R160 49.9_0402_1%

R159 49.9_0402_1%

R162 49.9_0402_1%

R161 49.9_0402_1%

1 2

1 2

1 2

1 2

CLK_SD_48M <37>
CLK_USB_48M <23>

R164 49.9_0402_1%

R163 49.9_0402_1%

1 2

1 2

CLK_VDD

2.2K_0402_5%

CPUCLK <7>
CPUCLK# <7>

2.2K_0402_5%

12

R177

R178

SB_OSCIN <23>
CLK_14M_SIO <41>

R165 49.9_0402_1%

1 2

12

R166 49.9_0402_1%

R167 49.9_0402_1%

R168 49.9_0402_1%

1 2

1 2

1 2

12

R179

2.2K_0402_5%
R181 0_0402_5%@

R183 0_0402_5%@
R185 0_0402_5%@

R169 49.9_0402_1%

1 2

R170 49.9_0402_1%

1 2

12
12
12

SBLINK_CLKP <13>
SBLINK_CLKN <13>
NBSRC_CLKP <13>
NBSRC_CLKN <13>
CLK_PCIE_VGA <16>
CLK_PCIE_VGA# <16>

SBSRC_CLKP <22>
SBSRC_CLKN <22>
CLK_PCIE_CARD <39>
CLK_PCIE_CARD# <39>
CLK_PCIE_MINI1 <36>
CLK_PCIE_MINI1# <36>

NB_OSCIN_R
HTREFCLK_R

R188 33_0402_1%

1 2
1 2

R190 33_0402_1%

12

R191

51.1_0402_1%

NB_OSC <13>
HTREFCLK <13>

EXT CLK FREQUENCY SELECT TABLE(MHZ)

FS2

0 0 0

A A

0 0 1

0 1 0
0 1 1
1 0 0
1 0 1
1 1 1

CPUFS1

Hi-Z
X

180.00

220.00

100.00

133.33

200.00

5

SRCCLK

HTTFS0 PCI

[2:1]

Hi-Z Hi-Z100.00 Reserved

100.00

100.00

100.00

100.00

100.00

100.00

X/6X/3

30.0060.00

36.56 73.12

66.66 33.33

66.66 33.33

66.66 33.33 Norma l A T H L O N6 4 o p e r at i o n

USB

48.00

48.00

48.00

48.00

48.00

48.00

48.00

COMMENT

Reserved
Reserved
Reserved
Reserved
Reserved

Security Classification

Issued Date

THIS SHEET OF ENG INEE RIN G DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

4

MAY BE USED BY O R DIS CLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/03/08 2006/03/08

Compal Secret Data

Deciphered Date

Compal Electronics, inc.

Title

SCHEMATIC, M/B LA-3151P

Size Document Number R ev

Custom

401412

Date: Sheet

星期四 三

09, 2006

2

月

15 55,

1

B

of

5

PCIE Lane Reversal

PCIE_GTX_C_MRX_N15
PCIE_GTX_C_MRX_P15
PCIE_GTX_C_MRX_N14
PCIE_GTX_C_MRX_P14
PCIE_GTX_C_MRX_N13
PCIE_GTX_C_MRX_P13
PCIE_GTX_C_MRX_N12

D D

C C

R210

2.2K_0402_5%

THM@

D+
D-

C264

1 2

B B

2200P_0402_50V7KTHM@

+3VS

12

PCIE_GTX_C_MRX_P12
PCIE_GTX_C_MRX_N11
PCIE_GTX_C_MRX_P11
PCIE_GTX_C_MRX_N10
PCIE_GTX_C_MRX_P10
PCIE_GTX_C_MRX_N9
PCIE_GTX_C_MRX_P9
PCIE_GTX_C_MRX_N8
PCIE_GTX_C_MRX_P8
PCIE_GTX_C_MRX_N7
PCIE_GTX_C_MRX_P7
PCIE_GTX_C_MRX_N6
PCIE_GTX_C_MRX_P6
PCIE_GTX_C_MRX_N5
PCIE_GTX_C_MRX_P5
PCIE_GTX_C_MRX_N4
PCIE_GTX_C_MRX_P4
PCIE_GTX_C_MRX_N3
PCIE_GTX_C_MRX_P3
PCIE_GTX_C_MRX_N2
PCIE_GTX_C_MRX_P2
PCIE_GTX_C_MRX_N1
PCIE_GTX_C_MRX_P1
PCIE_GTX_C_MRX_N0
PCIE_GTX_C_MRX_P0

PCIE_GTX_C_MRX_P[0..15]<12>
PCIE_GTX_C_MRX_N[0..15]<12>

PCIE_MTX_C_GRX_P[0..15]<12>
PCIE_MTX_C_GRX_N[0..15]<12>

+3VS

Thermal sensor

12

U10

1

VDD

2

D+

3

D-

4

OVERT#

MAX6649MUA_8UMAXTHM@

SCLK

SDATA

ALERT#

GND

C232 0.1U_0402_16V7K

1 2

C234 0.1U_0402_16V7K

1 2

C236 0.1U_0402_16V7K

1 2

C238 0.1U_0402_16V7K

1 2

C240 0.1U_0402_16V7K

1 2

C242 0.1U_0402_16V7K

1 2

C244 0.1U_0402_16V7K

1 2

C246 0.1U_0402_16V7K

1 2

C248 0.1U_0402_16V7K

1 2

C251 0.1U_0402_16V7K

1 2

C253 0.1U_0402_16V7K

1 2

C255 0.1U_0402_16V7K

1 2

C257 0.1U_0402_16V7K

1 2

C259 0.1U_0402_16V7K

1 2

C261 0.1U_0402_16V7K

1 2

C263 0.1U_0402_16V7K

1 2

PCIE_GTX_C_MRX_P[0..15]
PCIE_GTX_C_MRX_N[0..15]

PCIE_MTX_C_GRX_P[0..15]

PCIE_MTX_C_GRX_N[0..15]

THERM_SCL

8

THERM_SDA

7

1 2

6

R212 0_0402_5%

5

THM@

+3VS

2.2K_0402_5%

THM@

1 2

C231 0.1U_0402_16V7K

1 2

C233 0.1U_0402_16V7K

1 2

C235 0.1U_0402_16V7K

1 2

C237 0.1U_0402_16V7K

1 2

C239 0.1U_0402_16V7K

1 2

C241 0.1U_0402_16V7K

1 2

C243 0.1U_0402_16V7K

1 2

C245 0.1U_0402_16V7K

1 2

C247 0.1U_0402_16V7K

1 2

C249 0.1U_0402_16V7K

1 2

C252 0.1U_0402_16V7K

1 2

C254 0.1U_0402_16V7K

1 2

C256 0.1U_0402_16V7K

1 2

C258 0.1U_0402_16V7K

1 2

C260 0.1U_0402_16V7K

1 2

C262 0.1U_0402_16V7K

1 2

R211

THER_ALERT#

NB_RST#<13,22,27,33,36,41>

Spread spectrum

R222

0_0603_5%

SSC@

1

C265

2

SSC@

A A

+3VS

0.1U_0402_16V4Z

12

R230

1K_0402_5%

U11

7

VDD

1

XIN

8

XOUT

2

VSS

ASM3P1819N-SR_SO8

SSC@

1 2

C266

0.1U_0402_16V4Z
X1

4

VDD

1

OE

27MHZ_15P

5

5

REF

MODOUT

PD#

OUT

GND

NC

3
2

1 2

4

R226 22_0402_5%

3
6

Minimize dis t a nc e f r o m X1 pin3 to U3 pin1

OSC_IN

Keep away from other signal at last 25mils

Memory Interface SS

OSC_SPREAD

SSC@

4

U9A

R215 2K_0402_1%

1 2

R217 562_0603_1%

1 2

R218 1.47K_0603_1%

1 2

R220 0_0402_5%

1 2

R221 10K_0402_5%

1 2

4.7K_0402_5%

1 2
1 2

4.7K_0402_5%

1 2

R227 121_0402_1%

71.5_0402_1%

CLK_PCIE_VGA
CLK_PCIE_VGA#

PCIE_GTX_MRX_N15
PCIE_GTX_MRX_P15
PCIE_GTX_MRX_N14
PCIE_GTX_MRX_P14
PCIE_GTX_MRX_N13
PCIE_GTX_MRX_P13
PCIE_GTX_MRX_N12
PCIE_GTX_MRX_P12
PCIE_GTX_MRX_N11
PCIE_GTX_MRX_P11
PCIE_GTX_MRX_N10
PCIE_GTX_MRX_P10
PCIE_GTX_MRX_N9
PCIE_GTX_MRX_P9
PCIE_GTX_MRX_N8
PCIE_GTX_MRX_P8
PCIE_GTX_MRX_N7
PCIE_GTX_MRX_P7
PCIE_GTX_MRX_N6
PCIE_GTX_MRX_P6
PCIE_GTX_MRX_N5
PCIE_GTX_MRX_P5
PCIE_GTX_MRX_N4
PCIE_GTX_MRX_P4
PCIE_GTX_MRX_N3
PCIE_GTX_MRX_P3
PCIE_GTX_MRX_N2
PCIE_GTX_MRX_P2
PCIE_GTX_MRX_N1
PCIE_GTX_MRX_P1
PCIE_GTX_MRX_N0
PCIE_GTX_MRX_P0

PCIE_MTX_C_GRX_N15

PCIE_MTX_C_GRX_P15

PCIE_MTX_C_GRX_N14

PCIE_MTX_C_GRX_P14

PCIE_MTX_C_GRX_N13

PCIE_MTX_C_GRX_P13
PCIE_MTX_C_GRX_N12
PCIE_MTX_C_GRX_P12
PCIE_MTX_C_GRX_N11
PCIE_MTX_C_GRX_P11
PCIE_MTX_C_GRX_N10
PCIE_MTX_C_GRX_P10
PCIE_MTX_C_GRX_N9
PCIE_MTX_C_GRX_P9

PCIE_MTX_C_GRX_N8
PCIE_MTX_C_GRX_P8

PCIE_MTX_C_GRX_N7
PCIE_MTX_C_GRX_P7
PCIE_MTX_C_GRX_N6
PCIE_MTX_C_GRX_P6
PCIE_MTX_C_GRX_N5
PCIE_MTX_C_GRX_P5
PCIE_MTX_C_GRX_N4
PCIE_MTX_C_GRX_P4
PCIE_MTX_C_GRX_N3
PCIE_MTX_C_GRX_P3
PCIE_MTX_C_GRX_N2
PCIE_MTX_C_GRX_P2
PCIE_MTX_C_GRX_N1
PCIE_MTX_C_GRX_P1
PCIE_MTX_C_GRX_N0

PCIE_MTX_C_GRX_P0

D+

D-

THERM_SDA
THERM_SCL

12

R229

CLK_PCIE_VGA<15>
CLK_PCIE_VGA#<15>

+1.2VS

+3VS

R224
R225

OSC_IN

AL28
AK28

AK27

AJ27

AJ25
AH25
AH28

AG28
AG27

AF27
AF25
AE25
AE28
AD28
AD27
AC27
AC25
AB25
AB28
AA28
AA27

Y27

Y25
W25
W28

V28

V27

U27

U25

R28

R27

P27

AJ31
AH31
AH30

AG30
AG32

AF32
AF31
AE31
AE30
AD30
AD32
AC32
AC31
AB31
AB30
AA30
AA32

Y32

Y31
W31
W30

V30

V32

U32

U31

R30

R32

P32

P31

N31

AE24
AD24
AB24

AG24

AA24
AF24

AG12

AH12

AE12
AF12

AL26

AM26

T25
T28

T31
T30

PCIE_REFCLKP
PCIE_REFCLKN

PCIE_TX0P
PCIE_TX0N
PCIE_TX1P
PCIE_TX1N
PCIE_TX2P
PCIE_TX2N
PCIE_TX3P
PCIE_TX3N
PCIE_TX4P
PCIE_TX4N
PCIE_TX5P
PCIE_TX5N
PCIE_TX6P
PCIE_TX6N
PCIE_TX7P
PCIE_TX7N
PCIE_TX8P
PCIE_TX8N
PCIE_TX9P
PCIE_TX9N
PCIE_TX10P
PCIE_TX10N
PCIE_TX11P
PCIE_TX11N
PCIE_TX12P
PCIE_TX12N
PCIE_TX13P
PCIE_TX13N
PCIE_TX14P
PCIE_TX14N
PCIE_TX15P
PCIE_TX15N

PCIE_RX0P
PCIE_RX0N
PCIE_RX1P
PCIE_RX1N
PCIE_RX2P
PCIE_RX2N
PCIE_RX3P
PCIE_RX3N
PCIE_RX4P
PCIE_RX4N
PCIE_RX5P
PCIE_RX5N
PCIE_RX6P
PCIE_RX6N
PCIE_RX7P
PCIE_RX7N
PCIE_RX8P
PCIE_RX8N
PCIE_RX9P
PCIE_RX9N
PCIE_RX10P
PCIE_RX10N
PCIE_RX11P
PCIE_RX11N
PCIE_RX12P
PCIE_RX12N
PCIE_RX13P
PCIE_RX13N
PCIE_RX14P
PCIE_RX14N
PCIE_RX15P
PCIE_RX15N

PCIE_CALRN
PCIE_CALRP
PCIE_CALI

PERST#
PCIE_TEST

PERST#_MASK

DPLUS
DMINUS

DDC3DATA
DDC3CLK

XTALIN
XTALOUT

M56P

M56@

XTAL

3

GPIO_0

GPIO

PCI EXPRESS

GPIO_1
GPIO_2
GPIO_3
GPIO_4
GPIO_5
GPIO_6

GPIO_7_BLON

GPIO_8

GPIO_9
GPIO_10
GPIO_11
GPIO_12
GPIO_13
GPIO_14
GPIO_15
GPIO_16
GPIO_17

VREFG

NC_DVOVMODE_0
NC_DVOVMODE_1

DVPCNTL_0
DVPCNTL_1
DVPCNTL_2

DVPCLK

DVPDATA_0
DVPDATA_1
DVPDATA_2
DVPDATA_3
DVPDATA_4
DVPDATA_5
DVPDATA_6
DVPDATA_7
DVPDATA_8

DVPDATA_9
DVPDATA_10
DVPDATA_11
DVPDATA_12
DVPDATA_13
DVPDATA_14
DVPDATA_15
DVPDATA_16
DVPDATA_17
DVPDATA_18
DVPDATA_19
DVPDATA_20
DVPDATA_21
DVPDATA_22

VIP HOST/ EXTERNAL TMDS

DVPDATA_23

CRT

HSYNC
VSYNC

DDC1DATA

DDC1CLK

GENERICA
GENERICB

TV

H2SYNC
V2SYNC

THERMAL

R2SET

ROMCS#
PLLTEST

TESTEN

RSET

COMP

NC

R
G
B

R2

G2

B2

Y
C

AD4
AD2
AD1
AD3
AC1
AC2
AC3
AB2
AC6
AC5
AC4
AB3
AB4
AB5
AD5
AB8
AA8
AB7
AB6

AC8

AK4
AL4

AF2
AF1
AF3
AG1
AG2
AG3
AH2
AH3
AJ2
AJ1
AK2
AK1
AK3
AL2
AL3
AM3
AE6
AF4
AF5
AG4
AJ3
AH4
AJ4
AG5
AH5
AF6
AE7
AG6

AK24
AM24
AL24

AJ23
AJ22

AH22
AH23

AK22

R216 1K_0402_5%

AF23

R219 499_0402_1%

AL22

AK15
AM15
AL15

AF15
AG15

AJ15
AJ13
AH15

R223 715_0402_1%

AK14

AC7
AG14

R228 1K_0402_5%

AG22

+3VS

R194 10K_0402_5%

1 2

R195 10K_0402_5%

1 2

R196 10K_0402_5%

1 2

R197 10K_0402_5%

1 2

R198 10K_0402_5%

1 2

R199 10K_0402_5%

1 2

TP1

R200 10K_0402_5%

1 2

R201 10K_0402_5%

1 2

R202 10K_0402_5%

1 2

POWER_SEL

OSC_SPREAD

THER_ALERT#

R203 499_0402_1%
R204 499_0402_1%

1 2

TP2
TP3

MEMID0
MEMID1
MEMID2

TP4

VGA_CRT_R
VGA_CRT_G
VGA_CRT_B

CRT_HSYNC
CRT_VSYNC

R213 4.7K_0402_5%

1 2

R214 4.7K_0402_5%

1 2

GENERICA NC,GENERICB Grounded -->Internal SS

VGA_TV_Y
VGA_TV_C

VGA_TV_COMP

@

@

@

@
X76@
X76@

POWER_SEL <53>

12

C250

R205 4.7K_0402_5%

1 2

R206 4.7K_0402_5%

1 2

R207 10K_0402_5% X76@

1 2

R208 10K_0402_5% X76@

1 2

R209 10K_0402_5% X76@

1 2

12
12

12

12

+3VS

1 2

0.1U_0402_16V4Z

+3VS

VGA_CRT_R <28>
VGA_CRT_G <28>
VGA_CRT_B <28>

CRT_HSYNC <28>
CRT_VSYNC <28>

VGA_TV_Y <28>
VGA_TV_C <28>
VGA_TV_COMP <28>

2

Low -> VDDC=1.2V
High -> VDDC=1.0V

I2C_DAT
I2C_CLK

Need Level Shift

+3VS

VGA_CRT_DAT
VGA_CRT_CLK

LVDS Bus

Straps: (Inter nal pull down)

I2C_DAT <29>
I2C_CLK <29>

+3VS

Need Level Shift

VGA_CRT_DAT <28>
VGA_CRT_CLK <28>

Transmitter power
saving enable

Transmitter
de-emphasis enable

Debug Access GPIO[4]

ROM ID Config GPIO[9,

GPIO[0]

GPIO[1] 0: TX de-emphasis disable

GPIO[6,5]PLL_IBIAS_RD Default : 0 1

13:11]

Vedio Memory Config. (VGA Internal PD)

MEMID[2:0]

0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1

Size Vender Chips

Size

64MB

16M16 Hynix 2
16M16 Samsung 2

64MB

16M16 Hynix 4

128MB

16M16 Samsung 4

128MB

32M16 Hynix 4

256MB
256MB

32M16 Samsung 4
Resreved
Resreved

1

0: 50% TX output swing
1: Full TX output swing

1: TX de-emphasis enable
0: OFF Pad must be available

1: ON

000X: No ROM,
AP_SIZE=00
001X: No ROM,
AP_SIZE=01
010X: No ROM,
AP_SIZE=10
011X: No ROM,
AP_SIZE=11

128M share
Memory
256M share
Memory
64M share
Memory
Reserved

FrequenceVGA

A-test

A-test

TBD

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2005/09/10

3

Compal Secret Data

Deciphered Date

2006/09/10

2

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, M/ B LA-3151P

401412

星期|, 09, 2006

三月

1

16 55

of

B

5

U9B

AE13

GPIO_18

AF13

GPIO_19

AF9

GPIO_20

AG7

GPIO_21

AE10

GPIO_22

AE9

GPIO_23

AF7

GPIO_24

100mA

0.1U_0402_16V4Z

100mA

C268

AF8

GPIO_25

AH6

GPIO_26

AF10

GPIO_27

AG10

GPIO_28

AH9

GPIO_29

AJ8

GPIO_30

AH8

GPIO_31

AG9

GPIO_32

AH7

GPIO_33

AG8

GPIO_34

AE23

GENERICC

Y23

BBN

K15

BBN

R10

BBN

AC17

BBN

AC14

BBP

M23

BBP

V10

BBP

K18

BBP

L10

VDD25

K22

VDD25

AA10

VDD25

1

2

M56P

M56@

EXPAND GPIO

FOREARD

COMPATIBILITY

D D

+VDD_CORE

C C

B B

+VDD25

0.1U_0402_16V4Z

C267

1

2

TXCLK_UP

TXCLK_UN
TXOUT_U0P
TXOUT_U0N
TXOUT_U1P
TXOUT_U1N
TXOUT_U2P
TXOUT_U2N
TXOUT_U3P
TXOUT_U3N

TXCLK_LN
TXCLK_LP

TXOUT_L0P

LVDS

TXOUT_L0N
TXOUT_L1P
TXOUT_L1N
TXOUT_L2P
TXOUT_L2N
TXOUT_L3P
TXOUT_L3N

VARY_BL

DIGON

GENERICD

INTERGRATED TMDS

DDC2DATA

DDC2CLK

TXCM

TXCP
TX0M

TX0P

TX1M

TX1P

TX2M

TX2P

TX3M

TX3P

TX4M

TX4P

TX5M

TX5P

HPD1

4

AJ21
AK21
AG18
AH18
AK20
AJ20
AG20
AH20
AH21
AG21

AL18
AM18
AL19
AK19
AM20
AL20
AM21
AL21
AJ18
AK18

AD12
AE11
AD23

AL9
AM9

AK10
AL10

AL11
AM11

AL12
AM12

AK9
AJ9

AK11
AJ11

AK12
AJ12

AH13
AG13

AF11

VGA_LVDSBC+
VGA_LVDSBC­VGA_LVDSB0+
VGA_LVDSB0­VGA_LVDSB1+
VGA_LVDSB1­VGA_LVDSB2+
VGA_LVDSB2-

VGA_LVDSAC­VGA_LVDSAC+
VGA_LVDSA0+
VGA_LVDSA0­VGA_LVDSA1+
VGA_LVDSA1­VGA_LVDSA2+
VGA_LVDSA2-

R231 10K_0402_5%

1 2

ENVDD

DVI_TXC-_L

R629 0_0402_5% DVI@

DVI_TXC+_L

R630 0_0402_5% DVI@

DVI_TX0-_L

R631 0_0402_5% DVI@

DVI_TX0+_L

R632 0_0402_5% DVI@

DVI_TX1-_L

R633 0_0402_5% DVI@

DVI_TX1+_L

R634 0_0402_5% DVI@

DVI_TX2-_L

R635 0_0402_5% DVI@

DVI_TX2+_L

R636 0_0402_5% DVI@

11/07/05"

R236 6.8K_0402_5%

1 2

R237 6.8K_0402_5%

1 2

DVI_TXC-

DVI_TXC+

DVI_TX0-

DVI_TX0+

DVI_TX1-

DVI_TX1+
DVI_TX2-

DVI_TX2+

VGA_LVDSBC+ <29>
VGA_LVDSBC- <29>
VGA_LVDSB0+ <29>
VGA_LVDSB0- <29>
VGA_LVDSB1+ <29>
VGA_LVDSB1- <29>
VGA_LVDSB2+ <29>
VGA_LVDSB2- <29>

VGA_LVDSAC- <29>
VGA_LVDSAC+ <29>
VGA_LVDSA0+ <29>
VGA_LVDSA0- <29>
VGA_LVDSA1+ <29>
VGA_LVDSA1- <29>
VGA_LVDSA2+ <29>
VGA_LVDSA2- <29>

ENBKL <33>

ENVDD <29>

10/20/05"

12
12

12
12

12
12

12
12

+3VS

VGA_DVI_DAT
VGA_DVI_CLK

VGA_DVI_DET

R232 180_0402_5%DVI@

1 2

R233 180_0402_5%DVI@

1 2

R234 180_0402_5%DVI@

1 2

R235 180_0402_5%DVI@

1 2

10/20/05"
Close to connector

3

To EC

DVI_TXC-

DVI_TXC+

DVI_TX0-

DVI_TX0+

DVI_TX1-

DVI_TX1+
DVI_TX2-

DVI_TX2+

Need Level
Shift

VGA_DVI_DAT <30>
VGA_DVI_CLK <30>

VGA_DVI_DET <30>

AH27
AC23

AL27

R23
P25
R25
T26
U26

Y26
AB26
AC26
AD25
AE26
AF26
AD26

AG25

AH26
AC28

Y28

U28

P28
AH29
AF28

V29
AC29

W27

AB27

V26

AJ26
AJ32

AK29

P26

P29

R29

T29

U29

W29

Y29
AA29
AB29
AD29
AE29
AF29

AG29

AJ29
AK26
AK30

AG26

N30

R31
AF30
AC30

V31

P30
AA31

U30
AD31
AK32

AJ28

Y30

AJ30

AK31

DVI_TXC- <30>
DVI_TXC+ <30>

DVI_TX0- <30>
DVI_TX0+ <30>

DVI_TX1- <30>
DVI_TX1+ <30>

DVI_TX2- <30>
DVI_TX2+ <30>

U9G

PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS

M56P

M56@

PCIE GND

TXVSSR
TXVSSR
TXVSSR
TXVSSR
TXVSSR

TPVSS

TMDS GNDCRT GNDTV GNDPLL GNDLV DS PL L&I/O GND

AVSSQ
AVSSN
AVSSN

VSS1DI

A2VSSQ
A2VSSN
A2VSSN

VSS2DI

MPVSS

LVSSR
LVSSR
LVSSR
LVSSR
LVSSR
LVSSR
LVSSR
LVSSR
LVSSR
LVSSR

PCIE_PVSS

PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS

PVSS

LPVSS

2

AJ7
AK7
AL7
AM7
AK8

AL8

AK23
AK25
AJ24

AL23

AK13
AM17
AL17

AJ17

AH14
A5

AE18
AK17

AJ19
AF18
AH17
AG17
AG19
AH19
AF22
AF17
AF21

W23
AB23
P24
R24
T24
U24
V24
W24
Y24
AC24
AH24
V25
AA25
R26
AA26
T27
AE27
AG31
W26
N24
AA23

Use 15mils trace
connect to GND

AD7
AE8
AL1

AM2

AD10

K10

E12
AC9

AF14

AD8

AA4

AG11
AG16

AD16

AA6

AD17
AH11

C10

AM13

AC10

AL13

A11

U10
AD6

AD14
AD13

D11
K12

A13
E13
K16

W18

1

U9F

B1

VSS

H1

VSS

L1

VSS

P1

VSS

U1

VSS

Y1

VSS
VSS
VSS
VSS

A2

VSS
VSS
VSS

E8

VSS

H5

VSS
VSS

M8

VSS

T10

VSS
VSS
VSS
VSS
VSS

C5

VSS

F10

VSS

J3

VSS

L6

VSS

M6

VSS

P6

VSS
VSS
VSS

V3

VSS
VSS

CORE

R3

VSS

C6

VSS

C9

VSS

F6

VSS

H7

VSS

GND

J6

VSS
VSS
VSS

P7

VSS

P5

VSS

M3

VSS

M9

VSS

L7

VSS

M7

VSS
VSS
VSS

A8

VSS

U7

VSS
VSS

E9

VSS

F3

VSS

J9

VSS

N7

VSS

N3

VSS

Y5

VSS
VSS
VSS

Y6

VSS

U6

VSS

E5

VSS
VSS
VSS

U8

VSS

U9

VSS
VSS

R6

VSS
VSS

V6

VSS
VSS
VSS
VSS

J12

VSS
VSS
VSS

F13

VSS
VSS

F15

VSS
VSS
VSS

M56P

M56@

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

C27
E32
H28
J30
K17
K27
M32
A22
C20
E19
H20
J24
M28
J28
J16
F30
L29
A31
B32
E30
AE15
AG23
AD9
AF16
AH10
AJ10
AD15
AH16
K23
U18
AE16
AE17
A19
H32
F19
G19
N8
Y7
T19
V19
G21
C21
F21
AE14
AK16
U5
F22
F18
K30
C24
F24
M24
A25
D30
E25
G25
G20
G22
F27
E28
H21
J21
H16
T15
V17
C15
C4
U14
P15
A16
E16
G13
G16
P17
R16
R14
W16
C18
F16

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2005/09/10

3

Compal Secret Data

Deciphered Date

2006/09/10

2

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, M/ B LA-3151P

401412

星期|, 09, 2006

三月

1

17 55

of

B