Compal LA-3071P, Latitude D420 Schematic
A
B
COMPAL CONFIDENTIAL
C
D
E
1 1
PCB NO :
LA-3071P
COMPAL P/N :
2 2
MODEL NAME :
HAU30
DA800004H1L
Crockett Schematics Document
uFCBGA Mobile Yonah-ULV
Intel Calistoga-GMS + ICH7M
2006-5-12
3 3
4 4
REV : 1.0 (DELL: A00)
DELL CONFIDENTIAL/PROPRIETARY
MB PCB
Part Number Description
DA800004H1L
PCB 00B LA-3071P REV1 M/B
A
BOM NO. 43140131L01
PCB P/N: DA800004H1L
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
B
C
D
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
Cover Sheet
LA-3071P
159Friday, May 12, 2006
E
1.0
of
5
4
3
2
1
D D
PS_ID_IN
PS_ID_IN<38>
2
PD3
SM24_SOT23
@
C C
PR4
3
1
1 2
100K_0402_1%~D
PR7
1 2
15K_0402_1%~D
PS_ID Detector
PR2
0_0402_5%~D@
1 2
PQ1
FDV301N_SOT23
D
S
1 3
G
2
C
PQ2
2
B
PMBT3904_SOT23~D
E
3 1
PR3
33_0402_5%~D
1 2
PD1
+5V_ALW
3
DA204U_SOT323~D
+5V_ALW
PR5
10K_0402_1%~D
+3.3V_ALW
2
PR1
2.2K_0402_5%~D
PD2
DA204U_SOT323~D
@
1 2
+5V_ALW
3
2
1
PS_I D <40>
PS_ID_DISABLE# <40>
+PWR_SRC
PC143
1U_0805_25V4Z~D
1
3
12
+3.3VX Source
PU10
IN
5
OUT
EN
4
NC
GND
MIC5235-3.3BM5_SOT23-5~D
2
+3.3V_RTC_LDO_1
1
PC142
2.2U_0603_6.3V6K~D
2
1
PS_ID
12
PR6
100_0402_5%~D@
1 2
+DC_IN Source
PL1
B B
PJDCIN
9
GND4
8
GND3
7
GND2
6
GND1
FOX_JPD113E-LB103-7F
SINGAL
DC+_1
DC+_2
DC-_1
DC-_2
5
1
+DCIN_JACK
2
3
4
-DCIN_JACK
BLM11B102S 0603~D
PWR_ID
FBM-L11-453215-900LMAT_1812~D
FBM-L11-453215-900LMAT_1812~D
PL2
1 2
PL3
1 2
12
PS_I D_IN <38>
PC1
12
PC6
0.47U_0805_25V7k
0.01U_0402_25V7K~D
@
+DOCK_DC_IN
PR8
1 2
240K_0402_5%~D
SI4825DY_SO8~D
1
2
3 6
12
PQ_G
PR10
PQ3
8
7
5
4
12
PC2
PC3
12
47K_0402_5%~D
0.01U_0402_25V7K~D
12
12
PC4
0.1U_0603_25V7K~D
0.1U_0603_25V7K~D
+DC_IN_SS
12
12
PC5
PR9
4.7K_0603_5%~D
10U_1206_25V6M~D
THE POINT
NOTE: "THE POINT LOCATED
AT PS MODULE
A A
DELL CONFIDENTIAL/PROPRIETARY
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISI ON OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INF ORMATION IT CONTA INS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WR ITT EN CO NSE NT OF COMPAL ELECTRONICS, INC.
3
2
Title
Size Document N u mb er Re v
Date: Sheet
Compal Electronics, Inc.
+DCIN
LA-3071P
1
110Friday, May 12, 2006
0.4
of
A
Compal confidential
Model : HAU30
B
C
D
E
Block Diagram
FAN
+FAN1_VOUT
1 1
pg 18
+2.5V_RUN
pg 18
DVI
2 2
PCI BUS
IDSEL:AD24
(PIRQA#,GNT0#,REQ0#)
DOCKING PORT
+DOCK_PWR_SRC
+3.3V_RUN
+2.5V_LOM
pg 38
USB[7]
Mini Card2
WLAN
3 3
+3.3V_RUN
pg 36
DOCKING
BUFFER
+5V_RUN
Mini Card 1
+3.3V_RUN
+3.3V_LAN+3.3V_LAN
+1.5V_RUN+1.5V_RUN
SIM Card
+SIM_PWR
CardBus & 1394 & SD
R5C843 CSP208
pg 37
+3.3V_RUN/ +1.5V_RUN 100MHz
+3.3V_RUN
+3.3V_SUS
GIGA Enthernet
WWAN
pg 36
HUB USB[2]USB[0]
pg 36
+3.3V_LAN
Thermal
GUARDIAN
EMC4000
+3.3V_SUS
CRT CONN
+5V_RUN
LVDS CONN
+LCDVDD
+GFX_PWR_SRC
DVI Bridge SI1362
+3.3V_RUN
+1.8V_RUN
+3.3V_RUN 33MHz
IDSEL:AD17
(PIRQB,C,D#,GNT2#,REQ2#)
pg 31,32
BCM5752
pg 29
LAN SWITCH
PI3L500E
+3.3V_LAN
pg 30
pg 18
pg 21
RGB
pg 19
LVDS
DVO
pg 20
HUB USB[1]
TV
SD card SLOT
+SD_VCC
1394 CONNCard Bus SLOT
PCI Express BUS
LPC BUS
USB[1]
HUB USB[4]
HUB_USB[3]
pg 32
pg 31pg 32
Yonah-2M ULV
+1.05V_VCCP
+VCC_CORE
Calistoga-GMS
+1.5V_RUN
+1.8V_SUS
+1.05V_VCCP
+3.3V_RUN
+2.5V_RUN
+1.5V_RUN
100MHz
+3.3V_RUN
+3.3V_SUS
+1.5V_RUN
+1.05V_VCCP
+3.3V_RUN
33MHz
SMSC SIO
ECE5018
+3.3V_ALW
Pentium-M
uFCBGA CPU
479pin
System Bus
FSB 400/533 MHz
INTEL
998pin BGA
pg 10,11,12,13,14
DMI
INTEL
ICH7-M
652pin BGA
HUB USB[1]
HUB USB[2]
pg 39
pg 7,8
H_D#(0..63)H_A#(3..31)
pg 22,23,24,25
SPI
Memory BUS
(DDR2)
48MHz
Azalia I/F
ATA100
+1.05V_VCCP
+1.8V_SUS 400/533MHz
USB[4] REAR
USB[6] REAR
USB[5] REAR
PATA HDD
+3.3V_HDD
pg 26 pg 27
Azalia Codec
STAC9200
+3.3V_RUN
+VDDA
CPU ITP Port
Clock Generator
SLG84450VTR
+3.3V_RUN
DDRII 512MB on Board
+0.9V_DDR_VTT
+1.8V_SUS
DDRII-DIMM X1
BANK 2, 3
+0.9V_DDR_VTT
+1.8V_SUS
pg 6pg 7
pg 16,17
USB Ports X1
+5V_SUS
pg 33
USB Ports X1
+5V_SUS
PWR USB X1
+5V_SUS
DH_PORT_PWRSRC
pg 33
pg 33
MDC
+3.3V_SUS
pg 34
Cable
RJ11
pg 30
pg 15
RJ45
pg 30
Power Sequence
DC IN
4 4
BATT IN
CHARGER
pg 45
pg 46
pg 51
3V/5V/15V
1.5V/1.05V
1.8V/0.9V
VCORE (IMVP-6)
A
pg 47pg 42,43
pg 48
pg 49
pg 50
Transformer
+2.5V_LOM
pg 30
Power On/Off
SW & LED
pg 44
DC/DC Interface
pg 45
B
Bluetooth
+3.3V_RUN
USB_BIO
Fingerprint
+3.3V_RUN
pg 34
Smart Card
+5V_RUN
pg 41
+3.3V_RUN
OZ77C6
pg 35
SLOT
pg 35
FIR
pg 37
Int.KBD &
Stick
Stick
C
pg 41
+RTC_CELL
+3.3V_ALW
SMSC KBC
MEC5004
Touch Pad
+5V_RUN
pg 40
+3.3V_ALW
pg 41
SPI
ST M25P80
pg 40
AMP & INT.
Speaker
+5V_SUS +3.3V_RUN
INT MIC
+5V_SUS
pg 28 pg 28
DELL CONFIDENTIAL/PROPRIETARY
Title
Size Document Number Rev
D
Date: Sheet
HeadPhone &
MIC Jack
Compal Electronics, Inc.
Block Diagram
LA-3071P
259Friday, May 12, 2006
E
1.0
of
5
4
3
2
1
2
PD5
DA204U_SOT323~D@
PR13
1 2
ESD Diodes
2
3
1
PR14
100_0402_5%~D
1 2
3
100_0402_5%~D
1 2
9
8
2
PD6
1
DA204U_SOT323~D@
PR15
2
3
+VCHGR
PD7
1
DA204U_SOT323~D@
PBAT_SMBCLK <40,51>
PBAT_SMBDAT <40,51>
PBAT_ALARM# <39>
PC7
0.1U_0603_25V7K~D
PL4
FBM-L11-453215-900LMAT_1812~D
1 2
12
+3.3V_ALW
12
PR11
10K_0402_1%~D
PBAT_PRES# <39>
7
6
5
4
3
2
1
SUYIN_200028MR009G502ZL
TOP view
D D
+PBATT
Z4304
Z4305
Z4306
Z4307
+PBATT
Battery Connector
PJBAT1
SUYIN200277MR009G508ZR~D
12
PC8
2200P_0402_50V7K~D
C C
BATT_PRES#
10
GND
11
GND
BATT1+
BATT2+
SMB_CLK
SMB_DAT
SYSPRES#
BATT_VOLT
BATT1BATT2-
9
8
7
6
5
4
3
2
1
+3.3V_ALW
PD4
DA204U_SOT323~D@
PR12
100_0402_5%~D
1 2
3
1
100_0402_5%~D
B B
A A
DELL CONFIDENTIAL/PROPRIETARY
Title
THIS SHEET OF EN GINEE RING D RAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
Battery Conn
LA-3071P
210Friday, May 12, 2006
1
0.4
of
5
Ceramic Capacitors :
4
3
TABLE
PCI
2
1
0.1U_0402_6.3VXX
D D
Tolerance
Temperatur e Characteristics
Rated Voltage
PCI DEVICE
CARD BUS
DOCKING
IDSEL
AD17
AD24 0
REQ#/GNT#
2
PIRQ
B,C,D
A
Package Size
Value
PM TABLE
+5V_RUN
Tantalum or Polymer Capacitors :
power
plane
+3.3V_ALW
10U_D2_10VX_R45
C C
Low ESR Mark : 45 m ohm
Tolerance
Rated Voltage
Package Size
Value
State
S0
S1
S3
S5 S4/AC
S5 S4/AC don't exist
ON
ON
ON
ON
+3.3V_SRC
+3.3V_SUS
+5V_SUS+5V_ALW
+1.8V_SUS
+15V_SUS
ON
ON
ON
OFF
OFF
+3.3V_RUN
+1.8V_RUN
+0.9V_DDR_VTT
+1.5V_RUN
+VCC_CORE
+1.05V_VCCP
+2.5V_RUN
ON
ON
OFF
OFF
OFFOFF
Capacitor Spec Guide:
Temperature Characteristics:
B B
A A
Symbol
CODE
Tolerance:
Symbol
CODE
Z5U
8
9
COG SJ
HI J
UK
UJ
A
+-0.1PF
+-0.05PF
M
K
+-20%
+-10%
+-30%
Z5V
X6SNPO
SL
N
1
A
B
2
Z5P
B
BJ
K
X5S
C
+-0.25PF
P
+100,-0%
4
5
G
X
6
X5R
SH
H
+-3%
Z
+80,-20%
30
Y5U X7R
C
CH
D
+-0.5PF +-1PF
Q
+20,-10%
+30,-10%
Y5P
Y5V
DEFG
CJ
CK
F
+-2%
V
+40,-20%
7
J
+-5%
NOTE1:
@XX : Depop component
USB
TABLE
USB PORT#
0
1
2
3
4,6
5
7
DESTINATION
Mini 2(WLAN)
USB Hub (5018)
N/A
N/A
REAR
PWR USB
Docking
USB H U B DESTINATION
1
2
3
4
USB HUB on
OZ77C6LN
DP_HUB
PC Card Bay
Mini 1(WWAN)
SMART CARD
Blue tooth
DESTINATION
Fingerprint
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
Index and Config.
LA-3071P
359Friday, May 12, 2006
1
1.0
of
5
PJP2
@
1 2
PAD-OPEN 4x4m
PL5
FBM-L11-453215-900LMAT_1812~D
+PWR_SRC
D D
3.3 Volt +/- 5%
Design Current: 6.5 A
Maximum current: 9.1A
OCP: 10.95A
+3.3V_SRCP
+3.3V_SRCP
1
12
+
PC26
PC25
2
C C
AUX_EN<40,42>
SUS_ON<40,42,43>
B B
+3.3V_SRCP
S
D
6
2451
+3.3V_ALW
3.3V OCP
Fsw=440 KHZ
Rds_on_MAX=15m; Itrip_MIN=8.5uA;L=2.7uH
Delta_I=Vout/L * 1/Fsw * (1-Vout/Vin)
=3.3/2.7u * 1/440K *(1-3.3/19)=2.3A
Ivalley_MIN= Itrip*Rtrip/Rds_on=8.5u*14.7K/15m=8.33A
Ivalley= Itrip*Rtrip/Rds_on=10u*14.7K/15m=9.8A
A A
Iocp_MIN=8.33+2.3/2=9.48A
Iocp=9.8+2.3/2=10.95A
0.1U_0603_25V7K~D
330U_D3L_6.3VM_R25~D
+VCC_TPS51120
PC118
0.1U_0603_25V7K~D
3
RUN_ENABLE <42>
G
PQ24
FDC655BN_NL_SSOT-6~D
PR135
12
5
0_0402_5%~D
1
2
+3.3V_RTC_LDO
1 2
PR21
0_0402_5%~D
1 2
@
PR24
1 2
1 2
0_0402_5%~D
@
GNDA_DCDC1
PR136
0_0402_5%~D@
12
3
G
I1
4
O
I0
P
PU7
5
SN74AHC1G32DCKR_SSOP5~D
PR160
0_0402_5%~D
@
1 2
+3.3V_RTC_LDO_1
THERM_STP#<18>
2.7U_SIL1055R-2R7PF_9A
PL7
1 2
PR27
10K_0402_5%~D
PQ5
SI4800DY-T1_SO8~D
PQ7
FDS6690AS_NL_SO8~D
12
SUS_ON<40,42,43>
PD18
2
BAT54CW_SOT323~D
1
PC10
2200P_0402_50V7K~D
Place these CAPs
close to FETs
578
3 6
241
578
3 6
241
PR157
1 2
3
100K_0402_1%~D
4
+DC1_PWR_SRC
12
12
PC11
0.1U_0603_25V7K~D
+3.3V_SRCP_L
PR30
10K_0402_5%~D
ALWON<40>
4
12
PC12
10U_1206_25V6M~D
0.1U_0603_25V7K~D
12
12
PR40
PC32
4.7K_0402_5%~D
PC20
0.01U_0603_25V7K~D
PC120
@
0.1U_0603_25V7K~D
12
12
10U_1206_25V6M~D
12
PC22
12
PR36
1K_0402_5%~D
+3.3V_RTC_LDO
DC/DC +3V/ +5V/ +15V
+VCC_TPS51120
PR17
5.1_0603_5%~D
12
PR20
0_0603_5%~D
1 2
TPS51120_DRVH2
TPS51120_LL2
TPS51120_DRVL2
TPS51120_VO2
TPS51120_VFB2
12
PC31
1000P_0402_50V7K~D
@
12
@
S
G
PR159
2.2M_0402_5%~D
2
G
0_0805_5%~D
2
12
13
D
S
12
PC19
1U_0603_10V6K~D
GNDA_DCDC1
22
20
9
13
14
15
16
17
8
6
12
29
PR162
19
0_0402_5%~D@
10
12
+3.3V_RTC_LDO
12
PC30
10U_0805_6.3V5K~D
PR161
12
D
13
PQ9
SI2301BDS-T1-E3 _SOT23~D
1
BAT54CW_SOT323~D
3
PQ11
RHU002N06_SOT323
PU1
2
VIN
V5FILT
EN5
VBST2
DRVH2
LL2
DRVL2
PGND2
VO2
VFB2
EN2
EN1
VREG3
EN3
@
PD21
PD10
RB717F_SOT323~D
2
@
TPS51120
32 QFN 5X5
SKIPSEL
32
TPS51120_SKIP#
12
PR38
0_0402_5%~D
1
3
TONSEL
PGOOD1
PGOOD2
PAD
33
PR34
0_0402_5%~D@
1 2
PR35
0_0402_5%~D @
1 2
PR37
0_0402_5%~D @
1 2
RUN_ON<19,40,42,43,48,49>
VREG5
VBST1
DRVH1
DRVL1
PGND1
VFB1
COMP1
COMP2
VREF2
GND
LL1
VO1
CS1
CS2
+3.3V_ALW
PC33
3
12
PC13
10U_1206_25V6M~D
PQ4
PQ6
PR25
SUSP WROK_5V <49>
PC14
SI4800DY-T1_SO8~D
SI4810BDY_SO8~D
10K_0402_1%~D
0.1U_0603_25V7K~D
1 2
12
578
3 6
578
3 6
PC15
2200P_0402_50V7K~D
241
+5V_SUSP_L
241
PC28
12
1000P_0402_50V7K~D
12
PC18
PC21
0.1U_0603_25V7K~D
1 2
1 2
100K_0402_1%~D
+VCC_TPS51120
0_0402_5%~D@
1 2
PQ10
RHU002N06_SOT323 @
PC134
10U_1206_25V6M~D
@
12
Place these CAPs
close to FETs
1U_0603_10V6K~D
PC27
GNDA_DCDC1
PR39
D
S
13
G
2
12
1000P_0402_50V7K~D
PQ8
SI2301BDS-T1-E3 _SOT23~D@
+5V_ALW
12
PC17
10U_1206_25V6M~D
PR18
21
0_0603_5%~D
28
1 2
TPS51120_DRVH1
27
TPS51120_LL1
26
TPS51120_DRVL1
25
24
TPS51120_VO1
1
TPS51120_VFB1
3
2
7
TPS51120_CS1
23
TPS51120_CS2
18
4
31
5
30
11
GNDA_DCDC1
+3.3V_SRCP
PR31
+VCC_TPS51120
12
PR41
200K_0402_1%~D
@
13
D
2
G
12
4.7U_1206_10V7K~D
3
S
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISI ON OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INF ORMATION IT CONTA INS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WR ITT EN CO NSE NT OF COMPAL ELECTRONICS, INC.
2
PR16
0_0805_5%~D
+15VS_L
1 2
12
PC9
PD9
EC11FS2_SOD106~D
12
PR26
2 1
2.2U_1206_25V7M~D
+15VS
PL6
3 2
12
PC29
1 2
1000P_0402_50V7K~D
GNDA_DCDC1
2
4.7U_SDT-1204P-4R7D-122GP_20%
PR19
@
PR22
@
GNDA_DCDC1
PR28
0_0402_5%~D
1 2
@
PR32
0_0402_5%~D
1 2
@
1 4
14.7K_0402_1%~D
15 Volt
Maximum Current: 10mA
PQ25
2N2222_SOT23~D
31
CBE
12
2
PR138
0_0805_5%~D
1 2
@
1
PR137
0_0402_5%~D
0_0402_5%~D
PR29
10K_0805_5%~D
+5V_SUSP
1 2
1 2
0_0402_5%~D
1 2
PR23
PD8
2
3
MMBZ5245B_SOT23~D
+5V_SUSP
12
PC24
PC23
0.1U_0603_25V7K~D
1 2
0_0402_5%~D
+VCC_TPS51120
5V OCP
Fsw=290 KHZ
Rds_on_MAX=20m; Itrip_MIN=8.5uA;L=4.7uH
Delta_I=Vout/L * 1/Fsw * (1-Vout/Vin)
=5/4.7u * 1/290K *(1-5/19)=2.7A
Ivalley_MIN= Itrip*Rtrip/Rds_on=8.5u*10K/20m=4.25A
Ivalley= Itrip*Rtrip/Rds_on=10u*10K/20m=5A
Iocp_MIN=4.25+2.7/2=5.6A
Iocp=5+2.7/2=6.35A
1
+15VP
12
PC16
2.2U_1206_25V7M~D
5 Volt +/- 5%
Design Current:3.63A
Maximum current: 5.191 A
OCP: 6.35A
1
+
2
330U_D3L_6.3VM_R25~D
PR133
0_0603_5%~D
12
GNDA_DCDC1
PJP3
@
+15VP
1 2
PAD-OPEN 4x4m
PJP4
@
+5V_SUSP
+3.3V_SRCP
1 2
PAD-OPEN 4x4m
PJP5
@
1 2
PAD-OPEN 4x4m
PJP12
@
1 2
PAD-OPEN 4x4m
DELL CONFIDENTIAL/PROPRIETARY
Title
Size Document N u mb er Re v
Date: Sheet
Compal Electronics, Inc.
+3.3V/+5V/+15V
LA-3071P
1
310Friday, M ay 1 2, 2006
of
+15V_SUS
+5V_SUS
+3.3V_SRC
0.4
5
4
3
2
1
ALWON
D D
ALWON
ADAPTER
+5V_ALW
+3.3V_ALW
+PWR_SRC
FDS4435 +GFX_PWR_SRC
RUN_ON
BATTERY
TPS51120
C C
SUS_ON
+5V_SUS
SUS_ON
+3.3V_SRC
AD3207 SC480
RUNPWROK
+VCC_CORE
SC483
RUNPWROK
+1.5V_RUN
RUNPWROK
+VCCP
SUSPWROK_5V
+1.8V_SUS
RUN_ON
+0.9V_DDR_VTT
B B
SI4800
RUN_ON
+5V_RUN
PL8
+15V_SUS
793475
VDDA
SI4800
RUN_ON
(Option)
AUDIO_AVDD_ON
+3.3V_RUN
SI3456
ENAB_3VLAN
+3.3V_LAN
SI3456
RUN_ON
+1.8V_RUN
L47
EMC4000
A A
+2.5V_RUN
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
DELL CONFIDENTIAL/PROPRIETARY
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
Power Rail
LA-3071P
459Friday, May 12, 2006
1
of
1.0
A
PJP6
@
1 2
PAD-OPEN 4x4m
PL8
FBM-L11-453215-900LMAT_1812~D
+PWR_SRC
1 1
1 2
12
PC35
10U_1206_25V6M~D
+DC2_PWR_SRC
12
12
PC37
PC36
0.1U_0603_25V7K~D
2200P_0402_50V7K~D
1.5V +/- 5%
Thermal Design Current: 2.5A
Maximum Current: 3.6A
MIN_OCP: 3.7A
+1.5V_RUN_P
1
12
+
PC49
PC50
2 2
3 3
330U_D2E_2.5VM_R9
1U_0603_10V6K~D@
+1.5V_RUN_P
+1.05V_VCCP_P
2
RUN_ON<19,40,42,43,47,49>
PL9
3.3uH_PCMC063T-3R3MN_6A_20%
PJP7
@
1 2
PAD-OPEN 4x4m
PJP8
@
1 2
PAD-OPEN 4x4m
12
1.5V_RUN_PWRGD<43>
Place these CAPs
close to FETs
PQ12
FDS6994S_SO8~D
4
3
2
1
+1.5V_RUN
+1.05V_VCCP
5
D1
G1
6
S1
D1
7
G2
D2
8
D2
S2
Use PR56 and PR58 for
Voltage Margining.
0_0603_5%~D
0_0603_5%~D
PR63
PR64
15K_0402_1%
GNDA_DC2A
12
GNDA_DC2A
12
PR47
453K_0402_1%~D5@
PC47
0.1U_0603_25V7K~D
PR58
12
12
12
8.45K_0402_1%
1 2
9.09K_0603_1%~D5@
1 2
PR56
30K_0402_1%
+3.3V_RUN
PR140
PR51
PR54
12
12
100K_0402_1%~D
B
1M_0402_5%~D
PR43
PR45
1 2
12
PC44
PC43
1000P_0402_50V7K~D
PR49
0_0603_5%~D
12
PC55
18P_0402_50V8J
PD20
MMBD4148W-7-F_SOD323~D
10_0402_5%
1 2
1 2
1U_0603_6.3V6M
GNDA_DC2A
12
1 2
BAT54A-7-F_SOT23~L
12
PC41
PU2
3
VDDP1
1
PGND1
1U_0603_10V6K~D
25
VCCA1
28
AGND1
23
TON1
7
BST1
6
DH1
5
LX1
4
ILIM1
2
DL1
24
VOUT1
26
FBK1
22
EN/PSV1
27
PGOOD1
SC1485ITSTR-TPS51483_TSSOP28
1 2
PC141
@
0.1U_0603_25V7K~D
12
PR60
1K_0402_1%~D
+5V_SUS
1
PD17
VDDP2
PGND2
VCCA2
AGND2
SC483/TPS51483
VOUT2
EN/PSV2
PGOOD2
PR62
1K_0402_1%~D
1 2
TON2
BST2
DH2
ILIM2
FBK2
C
12
PC34
32
PC42
17
15
11
14
9
21
20
19
LX2
18
16
DL2
10
12
8
13
12
1U_0603_10V6K~D
GNDA_DC2B
1U_0603_10V6K~D
PR46
PC45
10_0402_5%
1 2
1 2
1U_0603_6.3V6M
0_0603_5%~D
PR52
12.7K_0402_1%
1 2
+3.3V_RUN
PR61
100K_0402_1%~D
750K_0402_1%~D
Create new P/N
PR44
1 2
12
PC46
1000P_0402_50V7K~D
12
PR50
12
PC54
82P_0402_50V8J
12
PR48
5@
499K_0402_1%
1 2
PC48
0.1U_0603_25V7K~D
12
PR53
10K_0402_1%~D 5@
1 2
12
PR55
16.5K_0402_1%
12
Use PR55 and P57 for
Voltage Margining.
PR57
15K_0402_1%~D
GNDA_DC2B
12
PC38
2200P_0402_50V7K~D
12
12
PC40
PC39
0.1U_0603_25V7K~D
10U_1206_25V6M~D
1.05V +/- 5%
Thermal Design Current: 3.36A
Place these CAPs
close to FETs
PQ13
FDS6994S_SO8~D
5
6
7
8
PR139
0_0402_5%~D@
1 2
4
D1
G1
3
S1
D1
2
G2
D2
1
D2
S2
3.3uH_PCMC063T-3R3MN_6A_20%
Maximum Current:4.8A
MIN_OCP:5.2A
PL10
12
D
+1.05V_VCCP_P
1
12
+
PC53
PC51
2
1U_0603_10V6K~D@
330U_D2E_2.5VM_R9
1.05V_RUN_PWRGD <43>
BOM
Structure Description
---------------------------------------------- @ Do Not Populate
4@ Populate for Semtech - SC483 Only
5@ Populate for Ti - TPS51483 Only
4 4
Ref Des SC483 TPS52483
-------------------------------- PR56 30.0K 15.0K
PR58 15.0K 15.0K
PR55 16.5K 11.8K
PR57 15.0K 29.4K
A
GNDA_DC2B
DELL CONFIDENTIAL/PROPRIETARY
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
B
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
+1.5VRUNP /+VCCP_1P05VP
LA-3071P
D
410Friday, May 12, 2006
of
0.4
5
4
3
2
1
+3.3V_SUS
2.2K 2.2K 2.2K 2. 2K
ICH_SMBCLK
C22
D D
C C
ICH7-M
SIO
ICH_SMBDATA
B22
+3.3V_ALW
10K
CLK_SMB
6
DAT_SMB +3.3V_ALW
5
+5V_ALW
10K 10K
DOCK_SMB_CLK
10
DOCK_SMB_DAT
9
+3.3V_ALW
+3.3V_SUS
10K
SMBUS Address [TBD]
+5V_ALW
WWAN
2N7002
2N7002
3032
C8C7
5752M
LOM
SMBUS Address [C8]
SMBUS Address [TBD]
8
GUARDIAN
7
Power USB
DOG house
39
DOCKING
40
3032
WLAN
SMBUS Address [2F]
SMBUS Address [5A]
SMBUS Address [C4, 72, 70, 48]
CLK_SCLK
CLK_SDATA
+3.3V_RUN
16
CLK GEN.
17
SMBUS Address [D2]
DDR II 512M
ON Board
SMBUS Address [A0]
197
DIMM1
195
SMBUS Address [A2]
8.2K 8. 2K
112
Macallan IV
B B
A A
111
8
7
SBAT_SMBCLK
SBAT_SMBDAT
+3.3V_ALW
+3.3V_ALW
8.2K8.2K
PBAT_SMBCLK
PBAT_SMBDAT +3.3V_ALW
100
100
6
INV
5
3
BATTERY
4
CONN
9
CHARGER
10
Inverter
SMBUS Address [58]
SMBUS Address [16]
SMBUS Address [12]
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
SMBUS TOPOLOGY
LA-3071P
559Friday, May 12, 2006
1
1.0
of
5
D D
+PWR_SRC
.9 Volt +/- 5%
Design Current:1.05A
Maximum current:1.5A
+0.9V_DDR_VTTP
+DDR_PWR_SRC
C C
B B
PJP10
@
PAD-OPEN 4x4m
+1.8V_SUSP
1 2
+1.8V_SUSP
PR67
1M_0402_5%~D
PC68
1000P_0402_50V7K~D
GNDA_DDR
+1.8V_SUS
1 2
1 2
V_DDR_MCH_REF<10,15,16,17>
<GMCH, DDR>
PR73
0_0402_5%~D
@
FBM-L11-453215-900LMAT_1812~D
12
GNDA_DDR
PJP9
@
1 2
PAD-OPE N 4x4m
PL11
1 2
4
PC63
PR71
10_0402_1%~D
1 2
12
PC72
1U_0603_10V6K~D
GNDA_DDR
3
NOTE: Component Values Shown for SEMTECH SC480 ONLY.
For Texas Instruments TPS51116, Please USE Reference BOM.
+DDR_PWR_SRC
Place these CAPs
10U_0805_6.3V5K~D
1
2
+5V_SUS
+5V_SUS
+1.8V_SUSP
PC64
10U_0805_6.3V5K~D
GNDA_DDR
+1.8V_SUSP
close to FETs
PD13
RB751V-40_SOD323~D
2 1
1
1
2
PR72
PC65
@
10_0402_1%~D
2
10U_0805_6.3V5K~D
1 2
PC66
1U_0603_10V6K~D
12
PC71
1U_0603_10V6K~D
GNDA_DDR
PR75
0_0402_5%~D
1 2
12
24
1
PGND2
2
VTTS
SC480ITSTR_MLPQ24~D
3
VSSA
4
TON
5
REF
6
VCCA
PR74
100_0402_5%~D
1 2
PC73
GNDA_DDR
NOTE: For Test purposes only
PC59
12
PR65
0_0603_5%~D
22
21
23
VTT
BST
VTTIN
PU3
TPS51116
20 QFN 4 X 4
NC7VTTEN10FB
VDDQS
9
8
12
0.1U_0402_10V7K~D
12
0.1U_0603_25V7K~D
20
DH
11
@
LX
PGND1
PGND1
PC119
19
18P_0402_50V8J
DL
VDDP
VDDP
PGD
NC12EN/PSV
ILIM
PAD
12
FDS6994S_SO8~D
5
D1
6
D1
7
D2
8
D2
18
17
16
15
14
13
PAD
25
GNDA_DDR
+1.8V_SUSP
12
12
GNDA_DDR
PQ14
G1
S1
G2
S2
PR76
27.4K_0603_1%~D
@
PR77
17.4K_0603_1%~D
@
PC56
4
3
2
1
PR66
12.4K_0402_1%~D
PR68
10K_0402_1%~D
@
12
PC69
1U_0603_10V6K~D
GNDA_DDR
@
Create new P/N
2200P_0402_50V7K~D
12
12
12
12
12
PC57
PC58
PC132
0.1U_0603_25V7K~D
10U_1206_25V6M~D
PL12
3.3uH_PCMC063T-3R3MN_6A_20%
12
12
PC67
1U_0603_10V6K~D
PR69
@
0_0402_5%~D
1 2
2
12
10U_1206_25V6M~D @
1
2
PC133
220U_D2_4VM~D
12
PC70
PR70
1U_0603_10V6K~D
100K_0402_1%~D
1.8 Volt +/- 5%
Design Current:3.5A
Maximum current:4.9A
MIN_OCP:5A
+1.8V_SUSP
1
12
+
+
PC62
PC60
2
0.1U_0402_10V7K~D
220U_D2_4VM~D
+5V_SUS
12
SUSPW ROK_1P8V <43>
SUSPWROK_5V <47>
RUN_ON <19,40, 42,43,4 7,48>
<GMCH>
<5V_3V regulator>
<EC>
1
PJP11
+0.9V_DDR_VTTP
A A
@
1 2
PAD-OPEN 43X79
5
+0.9V_DDR_VTT
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
4
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
Title
+1.8VSUSP/ +0.9 V _ DDR_VT
Size Document N u mb er Re v
Date: Sheet
LA-3071P
510Friday, May 12, 2006
1
of
0.4
5
D
1
3
G S
2
2N7002
ICH_SMBDATA<24,29,36> CLK_SDATA <15,17>
D D
+3.3V_RUN
ICH_SMBCLK<24,29,36>
FSC FSB FSA CPU
CLKSEL2 CLKSEL0CLKSEL1
ICH_SMBDATA
ICH_SMBCLK
000
1
*
C C
00
1
0
11
0
1
1
0
1
1
11
0
00
1
0
1
CPU_BSEL CPU_BSEL2(FSC) CPU_BSEL1(FSB)
133
166
B B
A A
0
0
+3.3V_RUN
5
1 2
12
2N7002W-7-F_SOT323~D
MHz
266
133
200
166
333
100
400
R69
10K_0402_5%~D
FSA
R72
@
10K_0402_5%~D
+3.3V_RUN
Q1
D
1 3
1 3
D
SRC
MHz
100
100
100
100
100
100
100
Reserve
12
S
G
2
2
G
Q2
S
2N7002W-7-F_SOT323~D
PCI
MHz
33.3
33.3
33.3
33.3
33.3
33.3
33.3
0
1
12
R5
R4
2.2K_0402_5%~D
2.2K_0402_5%~D
CLK_SDATA
CLK_SCLK
1
2
C10
4.7U_0603_6.3V6M~D
Place crystal within
500 mils of CK410
CLK_SD_48M<31>
CLK_ICH_48M<24>
CLK_SMCARD_48M<35>
CPU_MCH_BSEL0<8,10>
CPU_MCH_BSEL1<8,10>
CPU_MCH_BSEL2<8,10>
CLK_PCI_5004<40>
CLK_PCI_SIO<39>
CLK_PCI_PCCARD<31>
CLK_PCI_DOCK<38>
CLK_PCI_LOM<29>
CLK_ICH_14M<24>
CLK_SIO_14M<39>
MCH_DREFCLK<10>
MCH_DREFCLK#<10>
CLK_PCI_ICH<22>
CLK_ENABLE#<50>
FCTSEL1 PIN43 PIN44 PIN47 PIN48
01DOT96T DOT96C 96/100M_T 96/100M_C
27M_out 27M SSout SRCT0 SRCC0
4
+3.3V_RUN
C6
0.1U_0402_16V4Z~D
CLK_SCLK <15,17>
+CK_VDD_48+CK_VDD_A +CK_VDD_REF
1
2
C11
0.047U_0402_16V7K~D
1
2
C12
4.7U_0603_6.3V6M~D
C15
27P_0402_50V8J~D
12
C16
27P_0402_50V8J~D
12
CLK_SD_48M
CLK_ICH_48M FSA
CLK_SMCARD_48M
CLK_PCI_5004
CLK_PCI_SIO
CLK_PCI_PCCARD PCI_PCCARD
CLK_PCI_LOM PCI_LOM
CLK_SIO_14M
MCH_DREFCLK# DOT96#
CLK_PCI_ICH PCI_ICH
CLK_ENABLE#
4
1 2
L1
BLM18PG600SN1_0603~D
1
60ohm,500mA,0.1ohm
2
1
2
12
L2
BLM18PG600SN1_0603~D
C13
0.047U_0402_16V7K~D
X1
14.31818MHz_20P_1BX14318CC1A~D
R30 0_0402_5%~D
R605 39_0402_5%~D
R32 39_0402_5%~D
R34 39_0402_5%~D
R561 8.2K_0402_5%~D@
R56 8.2K_0402_5%~D
R35 39_0402_5%~D
R36 39_0402_5%~D
R38 56_0402_5%~D
R39 56_0402_5%~D
R37 56_0402_5%~D
R40 15_0402_5%~D
R41 15_0402_5%~D
R42 33_0402_5%~D
R43 33_0402_5%~D
+3.3V_RUN
R48 56_0402_5%~D
+CK_VDD_MAIN2
1 2
60ohm,500mA,0.1ohm
1
2
1 2
12
12
1 2
12
12
12
12
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
+3.3V_RUN
@
10K_0402_5%~D
1 2
12
R71
10K_0402_5%~D
+CK_VDD_MAIN
C14
0.047U_0402_16V7K~D
1 2
R25 1_0603_5%~D
1 2
R27 2.2_0603_5%~D
1 2
R46 10K_0402_5%~D
1 2
R51 475_0402_1%~D
R67
FCTSEL1
3
+CK_VDD_MAIN
1
C1
10U_0805_10V4Z~D
2
1
C7
10U_0805_10V4Z~D
2
1
C2
0.1U_0402_16V4Z~D
2
1
C8
0.1U_0402_16V4Z~D
2
1
C3
0.1U_0402_16V4Z~D
2
1
C9
0.1U_0402_16V4Z~D
2
2
1
C4
0.1U_0402_16V4Z~D
2
Place near each pin
W>40 mil
1 2
R15 2.2_0603_5%~D
U1
1
VDDSRC
49
VDDSRC
54
VDDSRC
65
VDDSRC
30
VDDPCI
36
VDDPCI
12
+CK_VDD_REF
+CK_VDD_48
CLK_XTAL_IN
CLK_XTAL_OUT
FSC
FCTSEL1
PCI_DOCKCLK_PCI_DOCK
CLK14M_REFCLK_ICH_14M
DOT96MCH_DREFCLK
CLKIREF
CLK_SCLK
CLK_SDATA
VDDCPU
18
VDDREF
40
VDD48
20
X1
19
X2
41
USB_48MHz/FSLA
45
FSLB/TEST_MODE
23
REF0/FSLC/TEST_SEL
34
PCICLK4/FCTSEL1
33
PCICLK3
32
PCICLK2
27
PCICLK1
22
REF1
43
DOTT_96MHz/27MHz
44
DOTC_96MHz/27MHz(SS)
37
ITP_EN/PCICLK_F0
39
Vtt_PwrGd#/PD
9
IREF
16
SMBCLK
17
SMBDAT
4
GNDSRC
15
GNDCPU
21
GNDREF
31
GNDPCI
35
GNDPCI
42
GND48
68
GNDSRC
73
THRM_PAD
74
THRM_PAD
75
THRM_PAD
76
THRM_PAD
SLG84450VTR_QFN72~D
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
+CK_VDD_A
VDDA
GNDA
PCI_SRC_STOP#
CPU_STOP#
CPUT1
CPUC1
CPUT0
CPUC0
CPUT_ITP/SRCT10
CPUC_ITP/SRCC10
SRCT9
SRCC9
CLKREQ9#
SRCT8
SRCC8
CLKREQ8#
SRCT7
SRCC7
CLKREQ7#
SRCT6
SRCC6
CLKREQ6#
SRCT5
SRCC5
CLKREQ5#
SRCT4
SRCC4
CLKREQ4#
SRCT3
SRCC3
CLKREQ3#
SRCT2
SRCC2
CLKREQ2#
SRCT1
SRCC1
CLKREQ1#
LCD100/96/SRC0_T
LCD100/96/SRC0_C
Place near CK410+
7
8
H_STP_PCI#
25
H_STP_CPU#
24
11
10
CPU_BCLK
14
13
CPU_ITP
6
CPU_ITP#
5
3
2
72
MCH_3GPLL CLK_MCH_3GPLL
70
69
71
66
67
38
PCIE_ICH
63
PCIE_ICH#
64
62
60
61
29
58
59
57
55
56
28
PCIE_MINI2
52
PCIE_MINI2#
53
26
PCIE_MINI1
50
PCIE_MINI1#
51
46
DOT96_SSC
47
DOT96_SSC#
48
2
1
C5
0.1U_0402_16V4Z~D
2
1 2
R24 33_0402_5%~D
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
R26 33_0402_5%~D
R28 33_0402_5%~D
R29 33_0402_5%~D
R31 33_0402_5%~D
R33 33_0402_5%~D
R53 33_0402_5%~D
R54 33_0402_5%~D
R55 10K_0402_5%~D
R49 33_0402_5%~D
R50 33_0402_5%~D
R52 10K_0402_5%~D
R44 33_0402_5%~D
R45 33_0402_5%~D
R47 10K_0402_5%~D
R61 33_0402_5%~D
R62 33_0402_5%~D
R63 10K_0402_5%~D
R64 33_0402_5%~D
R65 33_0402_5%~D
R66 10K_0402_5%~D
R68 33_0402_5%~D
R70 33_0402_5%~D
1
2
CLK_MCH_BCLKMCH_BCLK
CLK_MCH_BCLK#MCH_BCLK#
CLK_CPU_BCLK
CLK_CPU_BCLK#CPU_BCLK#
CLK_CPU_ITP
CLK_CPU_ITP#
CLK_PCIE_LOMPCIE_LOM
CLK_PCIE_LOM#PCIE_LOM#
CLK_MCH_3GPLL#MCH_3GPLL#
CLK_PCIE_ICH
CLK_PCIE_ICH#
CLK_PCIE_MINI2
CLK_PCIE_MINI2#
CLK_PCIE_MINI1
CLK_PCIE_MINI1#
1
C643
0.1U_0402_16V4Z~D
H_STP_PCI# <24>
CLK_MCH_BCLK <10>
CLK_MCH_BCLK# <10>
CLK_CPU_BCLK <7>
CLK_CPU_BCLK# <7>
CLK_CPU_ITP <7>
CLK_CPU_ITP# <7>
+3.3V_RUN
+3.3V_RUN
CLK_PCIE_ICH <24>
CLK_PCIE_ICH# <24>
+3.3V_RUN
CLK_PCIE_MINI2 <36>
CLK_PCIE_MINI2# <36>
MINI2CLK_REQ# <36>
+3.3V_RUN
CLK_PCIE_MINI1 <36>
MINI1CLK_REQ# <36>
+3.3V_RUN
DREF_SSCLK <10>
DREF_SSCLK# <10>
CLK_CPU_ITP
CLK_CPU_ITP#
CLK_MCH_BCLK
CLK_MCH_BCLK#
CLK_CPU_BCLK
CLK_CPU_BCLK#
CLK_MCH_3GPLL
CLK_MCH_3GPLL#
CLK_PCIE_ICH
CLK_PCIE_ICH#
CLK_PCIE_LOM
CLK_PCIE_LOM#
CLK_PCIE_MINI2
CLK_PCIE_MINI2#
CLK_PCIE_MINI1
CLK_PCIE_MINI1#
MCH_DREFCLK
MCH_DREFCLK#
DREF_SSCLK
H_STP_CPU# <24>
CLK_PCIE_LOM <29>
CLK_PCIE_LOM# <29>
LOM_CLKREQ# <29>
CLK_MCH_3GPLL <12>
CLK_MCH_3GPLL# <12>
CLK_3GPLLREQ# <10>
CLK_PCIE_MINI1# <36>
DREF_SSCLK#
R1 49.9_0402_1%~D
R2 49.9_0402_1%~D
R3 49.9_0402_1%~D
R6 49.9_0402_1%~D
R7 49.9_0402_1%~D
R8 49.9_0402_1%~D
R9 49.9_0402_1%~D
R10 49.9_0402_1%~D
R11 49.9_0402_1%~D
R12 49.9_0402_1%~D
R13 49.9_0402_1%~D
R14 49.9_0402_1%~D
R16 49.9_0402_1%~D
R17 49.9_0402_1%~D
R18 49.9_0402_1%~D
R19 49.9_0402_1%~D
R20 49.9_0402_1%~D
R21 49.9_0402_1%~D
R22 49.9_0402_1%~D
R23 49.9_0402_1%~D
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
12
12
12
12
12
12
DELL CONFIDENTIAL/PROPRIETARY
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
Clock Generator
LA-3071P
659Friday, May 12, 2006
1
of
1.0
5
4
3
2
1
H_A#[3..31]<10>
H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
D D
H_REQ#[0..4]<10>
H_ADSTB#0<10>
C C
R82
56_0402_5%~D
@
1 2
C18
+1.05V_VCCP
B B
H_THERMDA<18>
2200P_0402_50V7K~D
H_THERMDC<18>
H_THERMDA, H_THERMDC routing together.
Trace width / Spacing = 10 / 10 mil
A A
H_ADSTB#1<10>
CLK_CPU_BCLK<6>
CLK_CPU_BCLK#<6>
H_ADS#<10>
H_BNR#<10>
H_BPRI#<10>
H_BR0#<10>
H_DEFER#<10>
H_DRDY#<10>
H_HIT#<10>
H_HITM#<10>
H_LOCK#<10>
H_RESET#<10>
H_RS#[0..2]<10>
H_TRDY#<10>
ITP_DBRESET#<24,40>
H_DBSY#<10>
H_DPSLP#<23>
H_DPRSTP#<23,50>
H_DPWR#<10>
CPU_PROCHOT#<39>
H_PWRGOOD<23>
H_CPUSLP#<10,23>
1
2
H_THERMTRIP#<18>
5
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
H_ADSTB#0
H_ADSTB#1
CLK_CPU_BCLK
CLK_CPU_BCLK#
H_ADS#
H_BNR#
H_BPRI#
H_BR0#
H_DEFER#
H_DRDY#
H_HIT#
H_HITM#
H_IERR#
H_LOCK#
H_RESET#
H_RS#0
H_RS#1
H_RS#2
H_TRDY#
ITP_BPM#0
ITP_BPM#1
ITP_BPM#2
ITP_BPM#3
ITP_DBRESET#
H_DBSY#
H_DPSLP#
H_DPRSTP#
H_DPWR#
ITP_BPM#4
ITP_BPM#5
CPU_PROCHOT#
H_CPUSLP#
ITP_TCK
ITP_TDI
ITP_TDO
TEST1
TEST2
ITP_TMS
ITP_TRST#
H_THERMDA
H_THERMDC
H_THERMTRIP#
TEST2
R84 51_0402_5%~D
R579 1K_0402_5%~D@
1 2
1 2
J4
L4
M3
K5
M1
N2
J1
N3
P5
P2
L1
P4
P1
R1
Y2
U5
R3
W6
U4
Y5
U2
R4
T5
T3
W3
W5
Y4
W2
Y1
K3
H2
K2
J3
L5
L2
V4
A22
A21
H1
E2
G5
F1
H5
F21
G6
E4
D20
H4
B1
F3
F4
G3
G2
AD4
AD3
AD1
AC4
C20
E1
B5
E5
D24
AC2
AC1
D21
D6
D7
AC5
AA6
AB3
C26
D25
AB5
AB6
A24
A25
C7
U2A
A3#
A4#
A5#
A6#
A7#
A8#
A9#
A10#
A11#
A12#
A13#
A14#
A15#
A16#
A17#
A18#
A19#
A20#
A21#
A22#
A23#
A24#
ADDR GROUP
A25#
A26#
A27#
A28#
A29#
A30#
A31#
REQ0#
REQ1#
REQ2#
REQ3#
REQ4#
ADSTB0#
ADSTB1#
BCLK0
BCLK1
ADS#
BNR#
BPRI#
BR0#
DEFER#
DRDY#
HIT#
HITM#
IERR#
LOCK#
RESET#
RS0#
RS1#
RS2#
TRDY#
BPM0#
BPM1#
BPM2#
BPM3#
DBR#
DBSY#
DPSLP#
DPRSTP#
DPWR#
PRDY#
PREQ#
PROCHOT#
PWRGOOD
SLP#
TCK
TDI
TDO
TEST1
TEST2
TMS
TRST#
THERMDA
THERMDC
THERMTRIP#
Yonah-ULV_1.06G SC_UFCBGA479~D1@
YONAH-ULV
DATA GROUP
HOST CLK
CONTROL
MISC
THERMAL
DIODE
LEGACY CPU
For Yonah B0
4
DINV0#
DINV1#
DINV2#
DINV3#
DSTBN0#
DSTBN1#
DSTBN2#
DSTBN3#
DSTBP0#
DSTBP1#
DSTBP2#
DSTBP3#
A20M#
FERR#
IGNNE#
LINT0
LINT1
STPCLK#
+1.05V_VCCP
D10#
D11#
D12#
D13#
D14#
D15#
D16#
D17#
D18#
D19#
D20#
D21#
D22#
D23#
D24#
D25#
D26#
D27#
D28#
D29#
D30#
D31#
D32#
D33#
D34#
D35#
D36#
D37#
D38#
D39#
D40#
D41#
D42#
D43#
D44#
D45#
D46#
D47#
D48#
D49#
D50#
D51#
D52#
D53#
D54#
D55#
D56#
D57#
D58#
D59#
D60#
D61#
D62#
D63#
INIT#
SMI#
D0#
D1#
D2#
D3#
D4#
D5#
D6#
D7#
D8#
D9#
1 2
R83 56_0402_5%~D
1 2
R468 75_0402_5%~D
F24
E26
H22
F23
G25
E25
E23
K24
G24
J24
J23
H26
F26
K22
H25
N22
K25
P26
R23
L25
L22
L23
M23
P25
P22
P23
T24
R24
L26
T25
N24
AA23
AB24
V24
V26
W25
U23
U25
U22
AB25
W22
Y23
AA26
Y26
Y22
AC26
AA24
AC22
AC23
AB22
AA21
AB21
AC25
AD20
AE22
AF23
AD24
AE21
AD21
AE25
AF25
AF22
AF26
J26
M26
V23
AC20
H23
M24
W24
AD23
G22
N25
Y25
AE24
A6
A5
C4
B3
C6
B4
D5
A3
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3
H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3
H_A20M#
H_FERR#
H_IGNNE#
H_INIT#
H_INTR
H_NMI
H_STPCLK#
H_SMI#
H_THERMTRIP#
CPU_PROCHOT#TEST1
H_D#0
E22
H_DINV#0 <10>
H_DINV#1 <10>
H_DINV#2 <10>
H_DINV#3 <10>
H_A20M# <23>
H_FERR# <23>
H_IGNNE# <23>
H_INIT# <23>
H_INTR <23>
H_NMI <23>
H_STPCLK# <23>
H_SMI# <23>
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
H_D#[0..63] <10>
ITP_TDO
1 2
R80 22.6_0402_1%~D
H_DSTBN#[0..3] <10>
H_DSTBP#[0..3] <10>
+1.05V_VCCP
1
2
+3.3V_SUS
R73 150_0402_1%~D
+1.05V_VCCP
R74 51_0402_5%~D
R75 54.9_0402_1%~D
R76 39_0402_5%~D
R78 150_0402_1%~D
R575 54.9_0402_1%~D@
R79 680_0402_5%~D
R81 27.4_0402_1%~D
1
C17
C633
2
0.1U_0402_16V4Z~D
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
0.1U_0402_16V4Z~D
ITP_DBRESET#
ITP_TDO
H_RESET#
ITP_TMS
ITP_TDI
ITP_BPM#5
ITP_TRST#
ITP_TCK
This shall place near CPU
+1.05V_VCCP
J2
28
VTT1
27
VTT0
26
ITP_DBRESET#
ITP_BPM#0
ITP_BPM#1
ITP_BPM#2
ITP_BPM#3
R77
22.6_0402_1%~D
H_RESET#
1 2
CLK_CPU_ITP<6>
CLK_CPU_ITP#<6>
ITP_BPM#4
ITP_BPM#5
ITP_TCK
CLK_CPU_ITP
CLK_CPU_ITP#
ITP_TCK
ITP_TRST#
ITP_TMS
ITP_TDI
VTAP
25
DBR#
24
DBA#
23
BPM0#
22
GND5
21
BPM1#
20
GND4
19
BPM2#
18
GND3
17
BPM3#
16
GND2
15
BPM4#
14
GND1
13
BPM5#
12
RESET#
11
FBO
10
GND0
9
BCLKP
8
BCLKN
7
TDO
6
NC2
5
TCK
4
NC1
3
TRST#
2
TMS
1
TDI
GND7
MOLEX_52435-2891_28P~D@
30
DELL CONFIDENTIAL/PROPRIETARY
Title
Size Document Number Rev
2
Date: Sheet
Compal Electronics, Inc.
Yonah-ULV in mFCPGA479
LA-3071P
759Friday, May 12, 2006
1
of
1.0
5
4
3
2
1
+DC_IN discharge path
D D
+DC_IN_SS
12
PC97
10U_1206_25V6M~D
PR121
1 2
365K_0402_1%~D
C C
B B
Battery Type:
4cell: Charging Voltage=17.325V;Charging Current =1.6A
6cell: Charging Voltage=12.975V;Charging Current =3.15A
9cell:Charging Voltage=12.975V;Charging Current =3.15A
A A
PR124
49.9K_0402_1%~D
PC104
0.01U_0402_25V7K~D
PBAT_SMBCLK<40,46>
PBAT_SMBDAT<40,46>
GND
12
12
5
GNDA_CHGR
PR131
0_0603_5%~D
MAX8731_IINP
RHU002N06_SOT323
ACAV_IN
GNDA_CHGR
12
PQ21
2
G
PR122
15.8K_0402_1%~D
ACAV_IN<18,40>
+5V_ALW
PC106
0.1U_0402_10V7K~D
GNDA_CHGR
PR146
0_0402_5%
1 2
ADAPT_TRIP_SEL<39>
12
13
D
S
ACAV_IN
12
12
PC126
0.01U_0402_25V8K
12
PR117
10K_0402_1%~D
13
D
2
G
S
PR123
10K_0402_1%~D
1 2
PR126
0_0402_5%~D
1 2
12
PC115
PR132
10K_0402_1%~D
MAX8731_REF
12
PR154
154K_0402_1%@
PQ20
RHU002N06_SOT323
10K_0402_1%~D
0.1U_0402_10V7K~D
8
7
5
PR119
MAX8731_LDO
PR130
4.7K_0402_5%~D
12
PC116
0.01U_0402_25V7K~D
PQ19
SI4835BDY_SO8~D
4
12
GNDA_CHGR
12
12
12
PC113
PC112
0.01U_0402_25V7K~D
12
PR145
301K_0402_1%~D
Need modify
12
PR147
56.2K_0402_1%
PC129
12
PR148
27.4K_0402_1%
4
1
2
36
PR120
100K_0402_1%~D
12
PC98
1U_0805_25V4Z~D
12
MAX8731_ACIN
MAX8731_ACOK
MAX8731_IINP
MAX8731_CCV
MAX8731_CCI
MAX8731_CCS
MAX8731_REF
12
12
PC114
1U_0603_10V6K~D
0.01U_0402_25V7K~D
12
0.01U_0402_25V8K
PC117
0.1U_0402_10V7K~D
GNDA_CHGR
Smart Charger
N657586
PC139
@
0.01U_0402_50V7K~D
GNDA_CHGR
GNDA_CHGR
PU6
22
DCIN
2
ACIN
13
ACOK
11
VDD
10
SCL
9
SDA
14
BATSEL
8
IINP
6
CCV
5
CCI
4
CCS
3
REF
7
DAC
12
GND
MAX8731_DAC
12
12
PC128
PC127
100P_0402_50V8J
PR116
0.01_2512_1%~D
4
3
12
MAX8731_CSSP
1
28
GND
CSSP
MAX8731_TQFN28~D
2
3
12
100P_0402_50V8J
+PWR_SRC
PL15
FBM-L11-453215-900LMAT_1812~D
MAX8731_BSTB
12
PC105
0.1U_0603_25V7K~D
PR155
1 2
PR127
PD15
33_0603_1%~D
2 1
RB751V-40_SOD323~D
+VCHGR
+5V_ALW +3.3V_ALW
PR143
100K_0402_1%~D
PC125
10P_0402_50V8J~D
<BOM Structure>
PC121
2200P_0402_50V7K~D
PC99
1U_0603_10V6K~D
1 2
PC107
1 2
1U_0603_10V6K~D
1 2
PR128
1_0603_5%~D
1 2
1 2
PC111
220P_0603_50V8J~D
MAX8731_CSIP
MAX8731_CSIN
12
12
1
2
12
PC140
@
0.01U_0402_50V7K~D
GNDA_CHGR
MAX8731_CSSN
27
MAX8731_VCC
26
VCC
CSSN
BST
LDO
DHI
DLO
PGND
CSIP
CSIN
FBSA
FBSB
4
G
IN-
O
IN+
P
8
+5V_ALW
THIS SHEET OF EN GINEE RING D RAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
25
MAX8731_LDO
21
MAX8731_DHI
24
MAX8731_LX
23
LX
MAX8731_DLO
20
19
18
17
15
16
PC135
@
0.01U_0603_25V7M~D
GNDA_CHGR
PR142
4.32M_0402_1%
1 2
PU9A
LM393DR_SO8~D
1
12
PC130
100P_0402_50V8J
PR125
0_0603_5%~D
1 2
1 2
100_0402_5%~D
12
12
PC131
0.01U_0402_25V8K
3
12
PC122
0.1U_0603_25V7M~D
GNDA_CHGR
12
PR144
100K_0402_1%~D
13
D
2
G
S
PQ26
RHU002N06_SOT323
12
PC138
+CHRG_IN
PQ22
IRF7821_SO8~D
1 2
3300P_0402_50V7K~D
PQ23
SI4810BDY_SO8~D
PR149
1 2
100K_0402_1%~D
＠
Place these CAPs
close to FETs
578
3 6
241
578
3 6
241
5
6
SI4835BDY_SO8~D
1
2
3 6
12
PC100
2200P_0402_50V7K~D
PL16
5.6U_HMU1356-5R6_8.8A_20%~D
2 1
+5V_ALW
8
P
IN+
7
O
IN-
G
PU9B
LM393DR_SO8~D
4
ADAPT_OC <39>
2
PQ18
8
4
12
0.1U_0603_25V7M~D
12
PC102
10U_1206_25V6M~D
+VCHGR_L
7
5
12
12
PC103
10U_1206_25V6M~D
PR129
0.01_2512_1%~D
4
3
+VCHGR
+DC_IN_SS
1
2
12
PC108
0.1U_0805_50V7M~D
PR118
470K_0402_5%~D
PC101
Maximum Battery Charge current = 3.15A
when system off, S3, S4.
Table1
PR142 PR145 PR148 PR154
4.32M 301K 56.2K 27.4K NA
976K 49.9K 13.3K 9.31K 38.3K
976K 13.3K
ADAPTER(W)
65
90
130
150
TRIP CURRENT
(A)
3.17
4.43
6.44
7.44
DELL CONFIDENTIAL/PROPRIETARY
DELL CONFIDENTIAL/PROPRIETARY
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
Charger
LA-3071P
+5V_ALW
PD19
PR158
PC109
33.2K
20K649K
21
1SS355_SOD323~D
1K_0603_1%~D
1 2
12
10U_1206_25V6M~D
+VCHGR
12
PC110
10U_1206_25V6M~D
Need double confirm
PR147
15K
10K
13K
1
710Friday, May 12, 2006
33.2K
66.1K
of
0.4
5
4
3
2
1
Length match within 25 mils
+VCC_CORE
W21
AD26
AB20
AA20
AF20
AE20
AB18
AB17
AA18
AA17
AD18
AD17
AC18
AC17
AF18
AF17
U2B
AF7
AE7
B26
K6
J6
M6
N6
T6
R6
K21
J21
M21
N21
T21
R21
V21
V6
G21
AE6
AD6
AF5
AE5
AF4
AE3
AF2
AE2
B22
B23
C21
R26
U26
U1
V1
E7
D2
F6
D3
C1
AF1
D22
C23
C24
AA1
AA4
AB2
AA3
M4
N5
T2
V3
B2
C3
T22
B25
VCCSENSE
VSSSENSE
VCCA
VCCP
VCCP
VCCP
VCCP
YONAH-ULV
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
PSI#
VID0
VID1
VID2
VID3
VID4
VID5
VID6
GTLREF
BSEL0
BSEL1
BSEL2
COMP0
COMP1
COMP2
COMP3
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
Yonah-ULV_1.06G SC_UFCBGA479~D1@
AB26
VSS
AA25
VSS
AD25
VSS
AE26
VSS
AB23
VSS
AC24
VSS
AF24
VSS
AE23
VSS
AA22
VSS
AD22
VSS
AC21
VSS
AF21
VSS
AB19
VSS
AA19
VSS
AD19
VSS
AC19
VSS
AF19
VSS
AE19
VSS
AB16
VSS
AA16
VSS
AD16
VSS
AC16
VSS
AF16
VSS
AE16
VSS
AB13
VSS
AA14
VSS
AD13
VSS
AC14
VSS
AF13
VSS
AE14
VSS
AB11
VSS
AA11
VSS
AD11
VSS
AC11
VSS
AF11
VSS
AE11
VSS
AB8
VSS
AA8
VSS
AD8
VSS
AC8
VSS
AF8
VSS
AE8
VSS
AA5
VSS
AD5
VSS
AC6
VSS
AF6
VSS
AB4
VSS
AC3
VSS
AF3
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AE4
AB1
AA2
AD2
AE1
B6
C5
F5
E6
H6
J5
M5
L6
P6
R5
V5
U6
Y6
A4
D4
E3
H3
G4
K4
L3
P3
N4
T4
U3
Y3
W4
D1
C2
F2
G1
POWER, GROUNG, RESERVED SIGNALS AND NC
VCCSENSE<50>
VSSSENSE<50>
+1.5V_RUN
D D
+VCC_CORE
1 2
R88 100_0402_1%~D
1 2
R89 100_0402_1%~D
Layout close CPU
VCCSENSE
VSSSENSE
1
C20
C19
2
0.01U_0402_16V7K~D
Close to U2.B26
10U_0805_6.3V6M~D
V_CPU_GTLREF
+1.05V_VCCP
R_A
12
R87
1K_0402_1%~D
R_B
12
R90
2K_0402_1%~D
VCCSENSE/VSSSENSE
Layout close CPU PIN AD26
0.5 inch (max)
C C
B B
trace width 18mil,
space 7mil, for
other signal 15mil
12
R91
R92
27.4_0402_1%~D
CPU_BSEL CPU_BSEL2 CPU_BSEL1
133
166
00
0
12
12
R93
27.4_0402_1%~D
54.9_0402_1%~D
1
Resistor placed within
0.5" of CPU pin.Trace
should be at least 25
12
mils away from any
other toggling signal.
R94
54.9_0402_1%~D
CPU_BSEL0
1
1
1
2
V_CPU_GTLREF
CPU_MCH_BSEL0<6,10>
CPU_MCH_BSEL1<6,10>
CPU_MCH_BSEL2<6,10>
+1.05V_VCCP
H_PSI#<50>
VID0<50>
VID1<50>
VID2<50>
VID3<50>
VID4<50>
VID5<50>
VID6<50>
+VCC_CORE
VCCSENSE
VSSSENSE
H_PSI#
VID0
VID1
VID2
VID3
VID4
VID5
VID6
COMP0
COMP1
COMP2
COMP3
AE18
AE17
AB15
AA15
AD15
AC15
AF15
AE15
AB14
AA13
AD14
AC13
AF14
AE13
AB12
AA12
AD12
AC12
AF12
AE12
AB10
AA10
AD10
AC10
AF10
AE10
U2C
AB9
AA9
AD9
AC9
AF9
AE9
AB7
AA7
AD7
AC7
B20
A20
F20
E20
B18
B17
A18
A17
D18
D17
C18
C17
F18
F17
E18
E17
B15
A15
D15
C15
F15
E15
B14
A13
D14
C13
F14
E13
B12
A12
D12
C12
F12
E12
B10
B9
A10
A9
D10
D9
C10
C9
F10
F9
E10
E9
B7
A7
F7
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
YONAH-ULV
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
POWER, GROUND
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
Yonah-ULV_1.06G SC_UFCBGA479~D1@
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
K1
J2
M2
N1
T1
R2
V2
W1
A26
D26
C25
F25
B24
A23
D23
E24
B21
C22
F22
E21
B19
A19
D19
C19
F19
E19
B16
A16
D16
C16
F16
E16
B13
A14
D13
C14
F13
E14
B11
A11
D11
C11
F11
E11
B8
A8
D8
C8
F8
E8
G26
K26
J25
M25
N26
T26
R25
V25
W26
H24
G23
K23
L24
P24
N23
T23
U24
Y24
W23
H21
J22
M22
L21
P21
R22
V22
U21
Y21
A A
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
Yonah-ULV in mFCBGA479
LA-3071P
859Friday, May 12, 2006
1
1.0
of
5
+VCC_CORE
Place these inside
socket cavity on L8
(North side
Secondary)
D D
Place these inside
socket cavity on L8
(Sorth side
Secondary)
1
2
+VCC_CORE
1
2
+VCC_CORE
1
2
C21
22U_0805_6.3V6M~D
C31
22U_0805_6.3V6M~D
C693
4@
10U_0805_4VAM~D
1
C22
4@
10U_0805_4VAM~D
2
1
C32
@
10U_0805_4VAM~D
2
1
C694
4@
10U_0805_4VAM~D
2
1
C23
22U_0805_6.3V6M~D
2
1
C33
4@
10U_0805_4VAM~D
2
1
C695
@
10U_0805_4VAM~D
2
4
1
C24
@
10U_0805_4VAM~D
2
1
C34
22U_0805_6.3V6M~D
2
1
C696
@
10U_0805_4VAM~D
2
1
C25
4@
10U_0805_4VAM~D
2
1
C35
4@
10U_0805_4VAM~D
2
1
C697
4@
10U_0805_4VAM~D
2
1
C26
22U_0805_6.3V6M~D
2
1
C36
22U_0805_6.3V6M~D
2
1
C698
4@
10U_0805_4VAM~D
2
1
C27
4@
10U_0805_4VAM~D
2
1
C37
4@
10U_0805_4VAM~D
2
1
C699
4@
10U_0805_4VAM~D
2
3
1
C28
22U_0805_6.3V6M~D
2
1
C38
4@
10U_0805_4VAM~D
2
1
C700
4@
10U_0805_4VAM~D
2
1
C29
22U_0805_6.3V6M~D
2
1
C39
4@
10U_0805_4VAM~D
2
1
C701
@
10U_0805_4VAM~D
2
1
4@
10U_0805_4VAM~D
2
1
4@
10U_0805_4VAM~D
2
1
@
10U_0805_4VAM~D
2
C30
C40
C702
2
1
+VCC_CORE
1
C703
4@
10U_0805_4VAM~D
2
C C
1
C704
4@
10U_0805_4VAM~D
2
Note:
C21,C23,C26,C28,C29,C31,C34,C36
use 22U on Single Core CPU and
use 10U on Dual Core CPU.
High Frequence Decoupling
Temp. characteristics: X5R
Operating range: -55~+85degree
BOM introduction
BOM
Near VCORE regulator.
Note:
C42,C43,C41,C44
will change to
220U 2.5V 6M on
Dual Core CPU for
CPU transition
noise
ESR <= 1.5m ohm
Part Number Description
South Side Secondary
+VCC_CORE
1
+
C42
4@
2
220U_D_2VM_R7M~D
1
1
+
C705
+
C43
@
4@
2
2
330U_D_2.5VM_R6M~D
220U_D_2VM_R7M~D
1
+
C44
C41
2
330U_D_2.5VM_R6M~D
330U_D_2.5VM_R6M~D
North Side Secondary
1
1
+
+
C706
@
2
2
330U_D_2.5VM_R6M~D
Capacitor = 1320uF
7mOhm
7mOhm
6mOhm
6/7mOhm
6/7mOhm
B B
+1.05V_VCCP
1
+
C45
@
2
330U_D2E_2.5VM_R9~D
PS CAP
1
C46
0.1U_0402_10V7K~D
2
PS CAP
PS CAP
1
C47
0.1U_0402_10V7K~D
2
PS CAP
1
2
6mOhm
PS CAP
PS CAP
C48
0.1U_0402_16V4Z~D
1
C49
0.1U_0402_16V4Z~D
2
1
C50
0.1U_0402_10V7K~D
2
1
C51
0.1U_0402_10V7K~D
2
Place these inside
socket cavity on L8
(North side
Secondary)
Part Number Description
Part Number Description
CPU speed
1.06G 5.5W
1@
1.2G 5.5W
2@
1.06G 7.5W
3@
4@
1.2G 9.5W
5@ W
6@
1.2G
8@ 1.06G 5.5W
Yonah-ULV_1.2G SC_UFCBGA479~D2@
S IC LE80538UE0092M SL8W6 1.2G C0 FCBGA
SA000017Z2L
Yonah-ULV_1.2G DC_UFCBGA479~D4@
S IC YONAH ULV QKEY 1.2G C0 FCBGA 479P
SA00001CF1L
Yonah-ULV_1.2G DC_UFCBGA479~D5@
S IC YONAH ULV QKEY 1.2G C0 FCBGA 479P
SA00001CF1L
CPU type
Signal core
Dual core
Signal core
CRB was 270uF
P/N
SA00000Z33L
SA000017Z2L
SA00000Z30L
SA00001CF1L
SA000017Z2L
SA00000Z33L
Yonah-ULV_1.2G SC_UFCBGA479~D6@
Part Number Description
Part Number Description
S IC LE80538UE0092M SL8W6 1.2G C0 FCBGA
SA000017Z2L
Yonah-ULV_1.06G SC_UFCBGA479~D8@
S IC LE80538UE0042M SL8W7 1.06G C0 FCBGA
SA00000Z33L
Use of decoupling
TAA
1. 220uF poly cap 2pcs
W/O
2. 22uF MLCC cap 8pcs
W/O
1. 220uF poly cap 4pcs
2. 10uF MLCC cap 26pcs
1. 220uF poly cap 2pcs
W
2. 22uF MLCC cap 8pcs
A A
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
CPU Bypass
LA-3071P
959Friday, May 12, 2006
1
1.0
of
5
4
3
2
1
AF33
AM30
AG33
AN30
AN21
AN22
AF26
AF25
AG14
AF12
AK14
AH12
AJ21
AF11
AE12
AF14
AJ14
AJ12
AN12
AN14
AA33
Y29
Y32
Y28
Y31
V28
V31
V29
V32
AG1
AF1
AK1
AE1
AJ1
U3B
DMI_RXN_0
DMI_RXN_1
DMI_RXP_0
DMI_RXP_1
DMI_TXN_0
DMI_TXN_1
DMI_TXP_0
DMI_TXP_1
SM_CK_0
SM_CK_1
SM_CK_2
SM_CK_3
SM_CK#_0
SM_CK#_1
SM_CK#_2
SM_CK#_3
SM_CKE_0
SM_CKE_1
SM_CKE_2
SM_CKE_3
SM_CS#_0
SM_CS#_1
SM_CS#_2
SM_CS#_3
SM_OCDCOMP_0
SM_OCDCOMP_1
SM_ODT_0
SM_ODT_1
SM_ODT_2
SM_ODT_3
SM_RCOMPN
SM_RCOMPP
SM_VREF_0
SM_VREF_1
Calistoga-GMS_FCBGA998~D
CFG_0
CFG_1
CFG_2
CFG_3
CFG_5
CFG_6
DMI
RESERVED1
RESERVED2
RESERVED7
RESERVED8
RESERVED9
CFG/RSVD
DDR2 MUXING
PM_ICHSYNC#
PM_BMBUSY#
PM_EXTTS#_0
PM
PM_EXTTS#_1
THRMTRIP#
PWROK
RSTIN#
D_REFCLKN
D_REFCLKP
CLK
D_REFSSCLKN
D_REFSSCLKP
CLKREQ#
C18
E18
G20
G18
J20
J18
K32
K31
C17
F18
A3
E31
G21
F26
H26
J15
AB29
W27
A27
A26
J33
H33
J22
CPU_MCH_BSEL0
CPU_MCH_BSEL1
CPU_MCH_BSEL2
CFG3
CFG5
CFG6
PM_EXTTS#0
PM_EXTTS#1
ICH_PWRGD
PLTRST_R#
1 2
MCH_ICH_SYNC# <22>
PM_BMBUSY# <24>
PM_EX TTS#0 <15>
PM_EX TTS#1 <24>
THERMTRIP_MCH# <18>
ICH_PWRGD <24,43>
MCH_DREFCLK# <6>
MCH_DREFCLK <6>
DREF_SSCLK# <6>
DREF_SSCLK <6>
CLK_3GPLLREQ# <6>
Strap Pin Table
CFG5
CFG19
(DMI Lane Reversal)
Calistoga-GM S n ot ha ve CFG4,CFG[7..18],CFG[20]
Need to double check
CFG19<13>
Low = DMI x 2
High = DMI x 4
Low = Normal
Operation (Default):
Lane number in Order
High = Reverse Lane
PM_EXTTS#0
PM_EXTTS#1
CPU_MCH_BSEL0
THERMTRIP_MCH#
CFG5
R108 10K_0402_5%~D
R109 10K_0402_5%~D@
1 2
R110 1K_0402_5%~D @
1 2
R113 1K_0402_5%~D @
1 2
R114 75_0402_5%~D
1 2
R115 2.2K_0402_5%~D
12
12
CPU_MCH_BSEL0 <6,8>DMI_MRX_ITX_N0<24>
CPU_MCH_BSEL1 <6,8>
CPU_MCH_BSEL2 <6,8>
T2PAD~D
T3PAD~D
PLTRST# <20,22,24,29,36>
R100100_0402_1%~D
*
+3.3V_RUN
+1.05V_VCCP
H_D#[0..63]<7>
D D
C C
+1.05V_VCCP
12
12
R104
R103
54.9_0402_1%~D
54.9_0402_1%~D
B B
12
R106
24.9_0402_1%~D
Layout Note:
H_XRCOMP & H_YRCOMP trace width
A A
and spacing is 10/20
H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
H_XRCOMP
H_XSCOMP
H_SWNG0
H_YRCOMP
H_YSCOMP
H_SWNG1
12
R107
24.9_0402_1%~D
M5
M4
M3
M1
W2
W1
W4
W7
W5
AB4
AB8
W8
AA9
AA8
AB1
AB7
AA2
AB5
A10
C15
C4
F6
H9
H6
F7
E3
C2
C3
K9
F5
J7
K7
H8
E5
K8
J8
J2
J3
N1
K5
J5
H3
J4
N3
N8
N6
K3
N9
V8
V9
R6
T8
R2
N5
N2
R5
U7
R8
T4
T7
R3
T5
V6
V3
V2
V5
A6
J1
K1
H1
U3A
H_D#_0
H_D#_1
H_D#_2
H_D#_3
H_D#_4
H_D#_5
H_D#_6
H_D#_7
H_D#_8
H_D#_9
H_D#_10
H_D#_11
H_D#_12
H_D#_13
H_D#_14
H_D#_15
H_D#_16
H_D#_17
H_D#_18
H_D#_19
H_D#_20
H_D#_21
H_D#_22
H_D#_23
H_D#_24
H_D#_25
H_D#_26
H_D#_27
H_D#_28
H_D#_29
H_D#_30
H_D#_31
H_D#_32
H_D#_33
H_D#_34
H_D#_35
H_D#_36
H_D#_37
H_D#_38
H_D#_39
H_D#_40
H_D#_41
H_D#_42
H_D#_43
H_D#_44
H_D#_45
H_D#_46
H_D#_47
H_D#_48
H_D#_49
H_D#_50
H_D#_51
H_D#_52
H_D#_53
H_D#_54
H_D#_55
H_D#_56
H_D#_57
H_D#_58
H_D#_59
H_D#_60
H_D#_61
H_D#_62
H_D#_63
H_XRCOMP
H_XSCOMP
H_XSWING
H_YRCOMP
H_YSCOMP
H_YSWING
V_DDR_MCH_REF<15,16,17,49>
H_A#_3
H_A#_4
H_A#_5
H_A#_6
H_A#_7
H_A#_8
H_A#_9
H_A#_10
H_A#_11
H_A#_12
H_A#_13
H_A#_14
H_A#_15
H_A#_16
H_A#_17
H_A#_18
H_A#_19
H_A#_20
H_A#_21
H_A#_22
H_A#_23
H_A#_24
H_A#_25
H_A#_26
H_A#_27
H_A#_28
H_A#_29
H_A#_30
H_A#_31
H_ADS#
H_ADSTB#_0
H_ADSTB#_1
H_VREF0
H_BNR#
H_BPRI#
H_BREQ0#
H_CPURST#
H_VREF1
HCLKN
HOST
HCLKP
H_DBSY#
H_DEFER#
H_DINV#_0
H_DINV#_1
H_DINV#_2
H_DINV#_3
H_DPWR#
H_DRDY#
H_DSTBN#_0
H_DSTBN#_1
H_DSTBN#_2
H_DSTBN#_3
H_DSTBP#_0
H_DSTBP#_1
H_DSTBP#_2
H_DSTBP#_3
H_HIT#
H_HITM#
H_LOCK#
H_REQ#_0
H_REQ#_1
H_REQ#_2
H_REQ#_3
H_REQ#_4
H_RS#_0
H_RS#_1
H_RS#_2
H_SLPCPU#
H_TRDY#
Calistoga-GMS_FCBGA998~D
V_DDR_MCH_REF
C55
@
0.1U_0402_10V6K~D
H_A#3
F8
H_A#4
D12
H_A#5
C13
H_A#6
A8
H_A#7
E13
H_A#8
E12
H_A#9
J12
H_A#10
B13
H_A#11
A13
H_A#12
G13
H_A#13
A12
H_A#14
D14
H_A#15
F14
H_A#16
J13
H_A#17
E17
H_A#18
H15
H_A#19
G15
H_A#20
G14
H_A#21
A15
H_A#22
B18
H_A#23
B15
H_A#24
E14
H_A#25
H13
H_A#26
C14
H_A#27
A17
H_A#28
E15
H_A#29
H17
H_A#30
D17
H_A#31
G17
H_ADS#
F10
H_ADSTB#0
C12
H_ADSTB#1
H16
H_VREF
E2
H_BNR#
B9
H_BPRI#
C7
H_BR0#
G8
H_RESET#
B10
H_VREF
E1
AA6
AA5
H_DBSY#
C10
H_DEFER#
C6
H5
J6
T9
U6
H_DPWR#
G7
H_DRDY#
E6
H_DSTBN#0
F3
H_DSTBN#1
M8
H_DSTBN#2
T1
H_DSTBN#3
AA3
H_DSTBP#0
F4
H_DSTBP#1
M7
H_DSTBP#2
T2
H_DSTBP#3
AB3
H_HIT#
C8
H_HITM#
B4
H_LOCK#
C5
H_REQ#0
G9
H_REQ#1
E9
H_REQ#2
G12
H_REQ#3
B8
H_REQ#4
F12
H_RS#0
A5
H_RS#1
B6
H_RS#2
G10
H_CPUSLP#
E8
H_TRDY#
E10
1
2
H_A#[3..31] <7>
+1.05V_VCCP
12
R95
221_0402_1%~D
12
R96
100_0402_1%~D
+1.05V_VCCP
12
H_ADS# <7>
H_ADSTB#0 <7>
H_ADSTB#1 <7>
H_BNR# <7>
H_BPRI# <7>
H_BR0# <7>
H_RESET# <7>
CLK_MCH_BCLK# <6>
CLK_MCH_BCLK <6>
H_DBSY# <7>
H_DEFER# <7>
H_DINV#0 <7>
H_DINV#1 <7>
H_DINV#2 <7>
H_DINV#3 <7>
H_DPWR# <7>
H_DRDY# <7>
H_DSTBN#[0..3] <7>
H_DSTBP#[0..3] <7>
H_HIT# <7>
H_HITM# <7>
H_LOCK# <7>
H_REQ#[0..4] <7>
H_RS#[0..2] <7>
H_CPUSLP# <7,23>
H_TRDY# <7>
12
+1.05V_VCCP
12
12
R105
R97
221_0402_1%~D
R98
100_0402_1%~D
R102
100_0402_1%~D
200_0402_1%~D
Stuff R111 & R112 for A1 Calistoga
1
2
1
2
1
C54
2
H_SWNG1
C52
0.1U_0402_10V6K~D
H_SWNG0
0.1U_0402_10V6K~D
H_VREF
0.1U_0402_10V6K~D
+1.8V_SUS
C53
R99 80.6_0402_1%~D
R101 80.6_0402_1%~D
DMI_MRX_ITX_N1<24>
DMI_MRX_ITX_P0<24>
DMI_MRX_ITX_P1<24>
DMI_MTX_IRX_N0<24>
DMI_MTX_IRX_N1<24>
DMI_MTX_IRX_P0<24>
DMI_MTX_IRX_P1<24>
T13 PAD~D
DDR_CKE2_DIMMA<15>
DDR_CKE3_DIMMA<15>
T14 PAD~D
DDR_CS2_DIMMA#<15>
DDR_CS3_DIMMA#<15>
T15 PAD~D
1 2
1 2
V_DDR_MCH_REF
Layout Note:
Route as short
as possible
12
R111
@
40.2_0402_1%~D
DMI_MRX_ITX_N0
DMI_MRX_ITX_N1
DMI_MRX_ITX_P0
DMI_MRX_ITX_P1
DMI_MTX_IRX_N0
DMI_MTX_IRX_N1
DMI_MTX_IRX_P0
DMI_MTX_IRX_P1
12
M_CLK_DDR0
M_CLK_DDR1
M_CLK_DDR2
M_CLK_DDR3
M_CLK_DDR#0
M_CLK_DDR#1
M_CLK_DDR#2
M_CLK_DDR#3
DDR_CKE0
DDR_CKE1
DDR_CKE2_DIMMA
DDR_CKE3_DIMMA
DDR_CS0#
DDR_CS1#
DDR_CS2_DIMMA#
DDR_CS3_DIMMA#
M_OCDOCMP0
M_OCDOCMP1
M_ODT0
M_ODT1
M_ODT2
M_ODT3
SMRCOMPN
SMRCOMPP
M_OCDOCMP0
M_OCDOCMP1
M_CLK_DDR0<16,17>
M_CLK_DDR1<16,17>
M_CLK_DDR2<15>
M_CLK_DDR3<15>
M_CLK_DDR#0<16,17>
M_CLK_DDR#1<16,17>
M_CLK_DDR#2<15>
M_CLK_DDR#3<15>
DDR_CKE0<16,17>
DDR_CS0#<16,17>
M_ODT0<16,17>
M_ODT2<15>
M_ODT3<15>
R112
@
40.2_0402_1%~D
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
Calistoga(1 of 5)
LA-3071P
1
10 59Friday, May 12, 2006
1.0
of
5
4
3
2
1
D D
DDR_A_BS0<16,17>
DDR_A_BS1<16,17>
DDR_A_DM[0..7]<15,16>
DDR_A_DQS[0..7]<15,16>
DDR_A_DQS#[0..7]<15,16>
C C
B B
DDR_A_MA[0..13]<16,17>
DDR_B_MA[0..13]<15>
DDR_A_CAS#<16,17>
DDR_A_RAS#<16,17>
DDR_A_WE#<16,17>
DDR_B_BS0<15>
DDR_B_BS1<15>
DDR_B_BS2<15>
T4 PAD~D
T5 PAD~D
DDR_A_BS0
DDR_A_BS1
DDR_A_DM0
DDR_A_DM1
DDR_A_DM2
DDR_A_DM3
DDR_A_DM4
DDR_A_DM5
DDR_A_DM6
DDR_A_DM7
DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7
DDR_A_DQS#0
DDR_A_DQS#1
DDR_A_DQS#2
DDR_A_DQS#3
DDR_A_DQS#4
DDR_A_DQS#5
DDR_A_DQS#6
DDR_A_DQS#7
DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_CAS#
DDR_A_RAS#
SA_RCVENIN#
SA_RCVENOUT#
DDR_A_WE#
DDR_B_BS0
DDR_B_BS1
DDR_B_BS2
DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7 DDR_A_D63
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13
AK12
AH11
AG17
AB30
AL31
AF30
AK26
AC28
AJ30
AK33
AL25
AM2
AC29
AK30
AJ33
AM25
AM3
AJ15
AM17
AM15
AH15
AK15
AN15
AJ18
AF19
AN17
AL17
AG16
AL18
AG18
AL14
AJ17
AK18
AN28
AM28
AH17
AH21
AJ20
AE27
AN20
AL21
AK21
AK22
AL22
AH22
AG22
AF21
AM21
AE21
AL20
AE22
AE26
AE20
AG7
AK5
AH3
AN9
AH8
AE3
AN8
AE2
AL9
AJ8
U3C
SA_BS_0
SA_BS_1
SA_BS_2
SA_DM_0
SA_DM_1
SA_DM_2
SA_DM_3
SA_DM_4
SA_DM_5
SA_DM_6
SA_DM_7
SA_DQS_0
SA_DQS_1
SA_DQS_2
SA_DQS_3
SA_DQS_4
SA_DQS_5
SA_DQS_6
SA_DQS_7
SA_DQS#_0
SA_DQS#_1
SA_DQS#_2
SA_DQS#_3
SA_DQS#_4
SA_DQS#_5
SA_DQS#_6
SA_DQS#_7
SA_MA_0
SA_MA_1
SA_MA_2
SA_MA_3
SA_MA_4
SA_MA_5
SA_MA_6
SA_MA_7
SA_MA_8
SA_MA_9
SA_MA_10
SA_MA_11
SA_MA_12
SA_MA_13
SA_CAS#
SA_RAS#
SA_RCVENIN#
SA_RCVENOUT#
SA_WE#
SB_BS_0
SB_BS_1
SB_BS_2
SB_MA_0
SB_MA_1
SB_MA_2
SB_MA_3
SB_MA_4
SB_MA_5
SB_MA_6
SB_MA_7
SB_MA_8
SB_MA_9
SB_MA_10
SB_MA_11
SB_MA_12
SB_MA_13
SA_DQ_0
SA_DQ_1
SA_DQ_2
SA_DQ_3
SA_DQ_4
SA_DQ_5
SA_DQ_6
SA_DQ_7
SA_DQ_8
SA_DQ_9
SA_DQ_10
SA_DQ_11
SA_DQ_12
SA_DQ_13
SA_DQ_14
SA_DQ_15
SA_DQ_16
SA_DQ_17
SA_DQ_18
SA_DQ_19
SA_DQ_20
SA_DQ_21
SA_DQ_22
SA_DQ_23
SA_DQ_24
SA_DQ_25
SA_DQ_26
SA_DQ_27
SA_DQ_28
SA_DQ_29
SA_DQ_30
SA_DQ_31
SA_DQ_32
SA_DQ_33
SA_DQ_34
SA_DQ_35
SA_DQ_36
SA_DQ_37
SA_DQ_38
SA_DQ_39
SA_DQ_40
SA_DQ_41
SA_DQ_42
SA_DQ_43
SA_DQ_44
SA_DQ_45
SA_DQ_46
SA_DQ_47
DDR2 SYSTEM MEMORY
SA_DQ_48
SA_DQ_49
SA_DQ_50
SA_DQ_51
SA_DQ_52
SA_DQ_53
SA_DQ_54
SA_DQ_55
SA_DQ_56
SA_DQ_57
SA_DQ_58
SA_DQ_59
SA_DQ_60
SA_DQ_61
SA_DQ_62
SA_DQ_63
SB_CAS#
SB_RAS#
SB_WE#
Calistoga-GMS_FCBGA998~D
AC31
AB28
AE33
AF32
AC33
AB32
AB31
AE31
AH31
AK31
AL28
AK27
AH30
AL32
AJ28
AJ27
AH32
AF31
AH27
AF28
AJ32
AG31
AG28
AG27
AN27
AM26
AJ26
AJ25
AL27
AN26
AH25
AG26
AM12
AL11
AH9
AK9
AM11
AK11
AM8
AK8
AG9
AF9
AF8
AK6
AF7
AG11
AJ6
AH6
AN6
AM6
AK3
AL2
AM5
AL5
AJ3
AJ2
AG2
AF3
AE7
AF6
AH5
AG3
AG5
AF5
AG19
AG21
AG20
DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_B_CAS#
DDR_B_RAS#
DDR_B_WE#
DDR_A_D[0..63] <15,16>
DDR_B_CAS# <15>
DDR_B_RAS# <15>
DDR_B_WE# <15>
A A
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
Calistogo(2 of 5)
LA-3071P
11 59Friday, May 12, 2006
1
1.0
of
5
D D
4
3
2
1
R116
24.9_0402_1%~D
1 2
C56 0.1U_0402_10V6K~D
C57 0.1U_0402_10V6K~D
C58 0.1U_0402_10V6K~D
C59 0.1U_0402_10V6K~D
C60 0.1U_0402_10V6K~D
C61 0.1U_0402_10V6K~D
C62 0.1U_0402_10V6K~D
C63 0.1U_0402_10V6K~D
12
AA26
H27
J27
Y26
H20
H22
A24
A23
E25
F25
C25
D25
F27
D27
H25
H30
G29
F28
E28
G28
H28
K30
K27
J29
J30
K29
D30
C30
A30
A29
G31
F32
D31
H31
G32
C31
F33
D33
F30
E33
D32
F29
U3F
SDVO_CTRLDATA
SDVO_CTRLCLK
G_CLKN
G_CLKP
CRT_DDC_CLK
CRT_DDC_DATA
CRT_BLUE
CRT_BLUE#
CRT_GREEN
CRT_GREEN#
CRT_RED
CRT_RED#
CRT_VSYNC
CRT_HSYNC
CRT_IREF
L_BKLTCTL
L_BKLTEN
L_CLKCTLA
L_CTLBDATA
L_DDC_CLK
L_DDC_DATA
L_VDDEN
L_IBG
L_VBG
L_VREFH
L_VREFL
LA_CLKN
LA_CLKP
LB_CLKN
LB_CLKP
LA_DATAN_0
LA_DATAN_1
LA_DATAN_2
LA_DATAP_0
LA_DATAP_1
LA_DATAP_2
LB_DATAN_0
LB_DATAN_1
LB_DATAN_2
LB_DATAP_0
LB_DATAP_1
LB_DATAP_2
EXP_A_COMPI
EXP_A_ICOMPO
SDVO_TVCLKIN#
SDVO_INT#
SDVO_FLDSTALL#
MISC
SDVO_TVCLKIN
SDVO_INT
SDVO_FLDSTALL
SDVO
SDVO_RED#
SDVO_GREEN#
SDVO_BLUE#
SDVO_CLKN
SDVO_RED
SDVO_GREEN
SDVO_BLUE
SDVO_CLKP
TV_DACA
TV_DACB
TV_DACC
TV_IREF
TV_IRTNA
TV
TV_IRTNB
LVDS VGA
TV_IRTNC
TV_DCONSEL0
TV_DCONSEL1
Calistoga-GMS_FCBGA998~D
R28
M28
N30
R30
T29
M30
P30
T30
DVO_RED#_C
P28
DVO_GREEN#_C
N32
DVO_BLUE#_C
P32
DVO_CLK#_C
T32
DVO_RED_C
N28
DVO_GREEN_C
M32
DVO_BLUE_C
P33
DVO_CLK_C
R32
A21
C20
E20
G23
B21
C21
D21
G26
J26
+PEGCOMP
TVIREF
VGA_BLU<21,38>
VGA_GRN<21,38>
VGA_RED<21,38>
BIA_PWM<19,40>
ENVDD<19>
12
LCD_A0-<19>
LCD_A1-<19>
LCD_A2-<19>
LCD_A0+<19>
LCD_A1+<19>
LCD_A2+<19>
LCD_ACLK-
LCD_ACLK+
LCD_A1-
LCD_A1+
LCD_A0-
LCD_A0+
LCD_A2-
LCD_A2+
SDVO_CTRLDATA
SDVO_CTRLCLK
C711
C712
C713
C714
G_CLK_DDC2
G_DAT_DDC2
CRT_IREF
BIA_PWM
PANEL_BKEN
LCTLA_CLK
LCTLB_DATA
LCD_DDCCLK
LCD_DDCDATA
L_IBG
LCD_ACLKLCD_ACLK+
LCD_A0LCD_A1LCD_A2-
LCD_A0+
LCD_A1+
LCD_A2+
2
1
1
2
1
2
1
2
SDVO_CTRLDATA<20>
SDVO_CTRLCLK<20>
CLK_MCH_3GPLL#<6>
CLK_MCH_3GPLL<6>
Close to U3.H25
C C
+3.3V_RUN
B B
A A
1 2
R580 2.2K_0402_5%~D
1 2
R581 2.2K_0402_5%~D
1 2
R123 10K_0402_5%~D
1 2
R124 10K_0402_5%~D
R126 150_0402_1%~D
R127 150_0402_1%~D
R128 150_0402_1%~D
12
12
12
LCD_DDCCLK
LCD_DDCDATA
LCTLA_CLK
LCTLB_DATA
VGA_RED
VGA_GRN
VGA_BLU
R117 255_0402_1%~D
VGA_VSYNC<21>
VGA_HSYNC<21>
12
PANEL_BKEN<19>
LCD_DDCCLK<19>
LCD_DDCDATA<19>
R118 1.5K_0402_1%~D
LCD_ACLK-<19>
LCD_ACLK+<19>
8.2P_0402_50V8J~D
3.3P_0402_50VJ~D
3.3P_0402_50VJ~D
3.3P_0402_50VJ~D
+1.5VRUN_PCIE
SDVOB_INT- <20>
SDVOB_INT+ <20>
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
12
R119
R122
4.99K_0402_1%~D
Close to U3.G23
SDVOB_RED- <20>
SDVOB_GREEN- <20>
SDVOB_BLUE- <20>
SDVOB_CLK- <20>
SDVOB_RED+ <20>
SDVOB_GREEN+ <20>
SDVOB_BLUE+ <20>
SDVOB_CLK+ <20>
TV_CVBS <38>
TV_Y <38>
TV_C <38>
12
12
R120
R121
150_0402_1%~D
150_0402_1%~D
150_0402_1%~D
G_CLK_DDC2
G_DAT_DDC2
+3.3V_RUN
12
R129
2.2K_0402_5%~D
12
R130
+3.3V_RUN
2.2K_0402_5%~D
13
Q3
G
2N7002W-7-F_SOT323~D
2
G
2
13
D
S
Q4
2N7002W-7-F_SOT323~D
CLK_DDC2
DAT_DDC2
CLK_DDC2 <21,38>
DAT_DDC2 <21,38>
D
S
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
Calistoga(3 of 5)
LA-3071P
12 59Friday, May 12, 2006
1
1.0
of
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