Compal LA-3061, Tianyi F40, Tianyi F40A Schematic

A

1 1

2 2

B

C

D

E

Compal confidential

HGT30/31 Schematics Document

Mobile Yonah uFCPGA with Intel

3 3

4 4

A

PDF created with pdfFactory Pro trial version www.pdffactory.com

Calistoga_GM/PM+ICH7-M core logic

2006-02-15

REV:0.3

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2005/03/10 2006/03/10

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

D

Date: Sheet of

Compal Electronics, Inc.

Cover Sheet

HGT30/31 LA-3061

星期四二月

23, 2006

1 47,

E

0.1

A

Compal confidential

File Name : LA-3061

ZZZ1

PCB

B

C

D

E

PCI-E x 16 VGA Sub BD

1 1

LVDS Panel
Interface

VRAM
128/256MB

Thermal Sensor
ADM1032

page 4

Fan Control

page 4

uFCBGA-479/uFCPGA-478 CPU

Nvidia
G72/G73M

PCI-E x 16

page 18

Intel Calistoga GMCH

LVDS Panel

2 2

Interface

page 16

CRT & TV OUT

page 17, 36

LAN I/F

PCI BUS

3.3V 33 MHz

10/100/1G LAN

RTL8110CL/SBL

3 3

RJ45 CONN

page 27

page 28

CardBus Controller

ENE CB1410

page 24

Slot 0

page 25

1394+CARD
READER R5C832

1394

page 26

3IN1 READER

page 26

page 38

RTC CKT.

page 20

Power On/Off CKT.

page 32

DC/DC Interface CKT.

4 4

page 35

Mobile Yonah

page 4, 5, 6

H_A#(3..31)
H_D#(0..63)

FSB

533/667MHz

PCBGA 1466

page 7, 8, 9, 10,11,12

DMI

Intel ICH7-M

mBGA-652

page 19, 20, 21, 22

LPC BUS

ENE KB910/L

Int.KBD

page 32

BIOS

page 34

Touch Pad

page 37

DDR2 -400/533/667

Dual Channel

PCIE x3

USB2.0

AC-LINK

DDR2-SO-DIMM X2

BANK 0, 1, 2, 3

page 13,14

Mini-PCIE Card

New Card
Connector x2

USB conn X3

page 31, 37

BT Conn

Audio AD1986A
AMOM

SATA HDD
Connector x2

PATA CDROM
Connector

page 28

page 37

page 28

page 29page 33

page 23

page 23

Clock Generator
ICS 954306

page 15

MODEM

page 29

AMOM

SubWoofer

page 31

AMP & Audio Jack

SPR CONN.

*RJ45 CONN
*MIC IN JACK
*LINE OUT JACK
*1394 CONN
*SPDIF CONN
*DC JACK
*TVOUT CONN
*USB CONN x1
*CIR x1

page 30

page 34

Power Circuit DC/DC

page 39~45

A

B

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

PDF created with pdfFactory Pro trial version www.pdffactory.com

2005/03/10 2006/03/10

C

Compal Secret Data

Deciphered Date

D

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

Block Diagram

HGT30/31 LA-3061

星期四二月

23, 2006

E

2 47,

0.1

A

Power Block Diagram Of The IMVP6

RTCVREF

(3.3V)

AO4916

PWM CONT.

DC IN

VIN
Detector

VIN

Regulator

G920AT24

B+

+5VALW

MOS

B+

SPOK#

SUSP

MOS

TP0610K

MOS

SI4800

MAX8734AEE

BATT+ Switch

BATT

MOS

AO4916

MOS

AO4407

MOS

U:SI4810B

Charger

L:SI4810B

MB39A126

+CPU_CORE

P.40

PWM

OZ813

U:SI7840 X1

VID[0..6]

L:AO4410X2

PWM CONT.

MOS

AO4916

MAX8770GTL+

PCI DEVICES

1 1

EXTERNAL

CARD BUS
CB1410

CARD READER & 1394

R5C832

LAN CONTROLLER

RTL8110SBL/CL

PCIE LANE

LANE

1

Express Card

2 Mini Card

I2C / SMB Address

KB910/L (SM1-Pulled-Up 5V)

DEVICE ADDRESS R/W
AT24C16AN A3/A2 H
SMART BATTERY 17/16 H

KB910/L (SM2-Pulled-Up 3.3V)

ADM1032AR 99/98 H

G7xM (I2CC-Pulled-Up 3.3V)

G781-1 9B/9A(RESERVED)

ICH7M SM Bus

ICS9LPR325AKLFT D3/D2 H
DDR II DIMM0 A1/A0 H
DDR II DIMM1 A3/A2 H

Mini-Express (2.5V)

IDSEL# REQ/GNT# PIRQ
AD20

AD22

AD17 3 PCI_PIRQF#

2 PCI_PIRQA#

0

DEVICE

(3.3V)
(3.3V)
(3.3V)
(2.5V)Express Card

NC
NC

PCI_PIRQG# PCI_PIRQH#

USB

PORT DEVICE

0

LEFT SIDE

1

BLUE TOOTH

2

RIGHT SIDE

3

NC

4

RIGHT SIDE

5

NC
NC

6

BOM Structure

MARK FUNCTION

NC FOR ALL@
PCIE-NEW CARD

EXP@

BLUE TOOTH

BT@

Internal 945GM

UMA@

External G7xM

VGA@
SUBWOOFER@
HGT30@

CB@
GIGA@
10/100@

SUBWOOFER
HGT30
PCMCIA/CARD BUS
8110SBL(SCL)Giga LAN
8110CL 10/100Mb LAN

OUT2

OUT1

ON2

ON1

+3VALW

+1.8V

+1.05VS

VCCP

Regulator

APL5912-KAC

SUSP#

Regulator

APL5331KAC

SYSON

SUSP#

U:SI4810B
L:SI4810B

ISL6269CRZ

Voltage Rails

State
S4 : STD
S5 : SOFT OFF

S0

S1

S3 : STR

S5 S4/AC

S5 S4/ Battery only
S5 S4/AC & Battery

don't exist

MB_ID

MB ID

0
1

MOS

PWM

P NAME
HGT-30
HGT-31

+VSB

+5VS

+VDDA+5VALW

SI9182DH

+3.3VS

SUSP

+2.5VS

MOS

SI4800

+1.8VS

+0.9VS

SUSP

MOS

SI4800

+1.5VS

OUT2

SUSP#

O MEANS ON

X MEANS OFF

+5VS
+3VS

power
plane

+B
LDO3
LDO5

O
O
O
O
O

X

+5VALW
+3VALW

+5V

O
O
O
O

X
X X X

BRD_ID

ID

MB REV#

R01 (EVT)

0
1

R02 (DVT)

2

R03
R04

3
4
5
6
7

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

2005/03/10 2006/03/10

+2.5VS
+1.8VS
+1.5VS+1.8V
+VGA_CORE
+1.2VS
+0.9VS
+CPU_CORE
+VCCP

OO
OO

O

X
X X
X

R119(Ra)=100K Ohm

X

R115(Rb)0Vab

8.2K

0.25V

0.50V

18K

0.82V

33K

1.19V

56K

1.65V

100K

2.20V

200K

NC

3.30V

Compal Secret Data

Deciphered Date

0V

+3VALW

+CPU_CORE

+3VS

+2.5VS

+1.8V

+1.8VS

+0.9VREF

+0.9VS

+1.5V

+1.5VS

KB910L
SB

mA

160mA

RTL8110SBL/CL

CPU

CPU+VCCP
NB

EXPRESS CARD
HDD
ODD
MDC
APA2066

36A

2.5A

9.8A
(14.7A)

1A+5VS

1.5A

1.8A

300mA

1A
TPA0211 mA
AD1986
USB PORT * 6

70mA

3A

NB 480mA
EXPRESS CARD
CLK_GEN
LCDVCC

1A

200mA

1A

VGA CARD (G7XM) 655mA
SB
R5C832
BIOS ROM
KB910L

680mA

mA

15mA

200mA

CB1410 mA

VGA CARD (G7XM) 130mA
NB

(143mA)

DDR2_DIMM 8A
NB (667Mhz)

GDDR2
VGA CARD (G7XM)

DDR2_DIMM

GDDR2

3.1A

6A

4.06A

10mA

1A

DDR2_DIMM 2A

SB 40mA

NB 8.9A(13.8A)
SB 3.8A
MiniCard 1A
EXPRESS CARD 0.65A
VGA CARD (G7XM)

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

Notes List

HGT30/31 LA-3061

星期四二月

23, 2006

2A

3 47,

0.1

PDF created with pdfFactory Pro trial version www.pdffactory.com

5

4

3

2

1

H_A#[3..31]<7>

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8

CLK_CPU_BCLK
CLK_CPU_BCLK#

ITP_DBRESET#

H_THERMDA
H_THERMDC
H_THERMTRIP#

OCP# <21>

H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

H_ADSTB#0
H_ADSTB#1

H_ADS#
H_BNR#
H_BPRI#
H_BR0#
H_DEFER#
H_DRDY#
H_HIT#
H_HITM#
H_IERR#
H_LOCK#
H_RESET#

H_RS#0
H_RS#1
H_RS#2
H_TRDY#

ITP_BPM#0
ITP_BPM#1
ITP_BPM#2
ITP_BPM#3

H_DBSY#
H_DPSLP#
H_DPRSTP#
H_DPWR#
ITP_BPM#4
ITP_BPM#5
H_PROCHOT#

H_PWRGOOD
H_CPUSLP#
ITP_TCK
ITP_TDI
ITP_TDO
TEST1
TEST2
ITP_TMS
ITP_TRST#

D D

H_REQ#[0..4]<7>

H_ADSTB#0<7>

C C

R84

56_0402_5%

1 2

+VCCP

B B

H_PROCHOT#<45>

1 2

+VCCP

68_0402_5%

H_THERMDA, H_THERMDC routing together.
Trace width / Spacing = 10 / 10 mil

A A

H_PROCHOT# OCP#

H_ADSTB#1<7>

CLK_CPU_BCLK<15>

CLK_CPU_BCLK#<15>

H_ADS#<7>
H_BNR#<7>
H_BPRI#<7>

H_BR0#<7>

H_DEFER#<7>

H_DRDY#<7>

H_HIT#<7>

H_HITM#<7>

H_LOCK#<7>

H_RESET#<7>

H_RS#[0..2]<7>

H_TRDY#<7>

ITP_DBRESET#<21>

H_DBSY#<7>

H_DPSLP#<20>

H_DPRSTP#<20,45>

H_DPWR#<7>

R83

H_PWRGOOD<20>

H_CPUSLP#<7,20>

R71 1K_0402_5%@

1 2

R74 51_0402_5%

1 2

H_THERMTRIP#<7,20>

+VCCP

12

R73

56_0402_5%@

CBE

123

Q4

PMBT3904_SOT23@

5

JP1A

J4

A3#

L4

A4#

M3

A5#

K5

A6#

M1

A7#

N2

A8#

J1

A9#

N3

A10#

P5

A11#

P2

A12#

L1

A13#

P4

A14#

P1

A15#

R1

A16#

Y2

A17#

U5

A18#

R3

A19#

W6

A20#

U4

A21#

Y5

A22#

U2

A23#

R4

A24#

T5

ADDR GROUP

A25#

T3

A26#

W3

A27#

W5

A28#

Y4

A29#

W2

A30#

Y1

A31#

K3

REQ0#

H2

REQ1#

K2

REQ2#

J3

REQ3#

L5

REQ4#

L2

ADSTB0#

V4

ADSTB1#

A22

BCLK0

A21

F21

D20

AD4
AD3
AD1
AC4

C20

D24
AC2
AC1

D21

AC5

AA6

AB3

C26

D25

AB5

AB6

A24

A25

HOST CLK

BCLK1

H1

ADS#

E2

BNR#

G5

BPRI#

F1

BR0#

H5

DEFER#
DRDY#

G6

HIT#

E4

CONTROL

HITM#
IERR#

H4

LOCK#

B1

RESET#

F3

RS0#

F4

RS1#

G3

RS2#

G2

TRDY#

BPM0#
BPM1#
BPM2#
BPM3#

DBR#

E1

DBSY#

B5

DPSLP#

E5

DPRSTP#
DPWR#
PRDY#
PREQ#
PROCHOT#

D6

PWRGOOD

D7

SLP#
TCK
TDI
TDO
TEST1
TEST2
TMS
TRST#

THERMDA
THERMDC

C7

THERMTRIP#

TYCO_1-1674770-2_Yonah~D

ME@

H_DPSLP#

H_DPRSTP#

YONAH

MISC

THERMAL
DIODE

R100

1 2

56_0402_5%@

R99

1 2

56_0402_5%@

DATA GROUP

LEGACY CPU

+VCCP

4

D10#
D11#
D12#
D13#
D14#
D15#
D16#
D17#
D18#
D19#
D20#
D21#
D22#
D23#
D24#
D25#
D26#
D27#
D28#
D29#
D30#
D31#
D32#
D33#
D34#
D35#
D36#
D37#
D38#
D39#
D40#
D41#
D42#
D43#
D44#
D45#
D46#
D47#
D48#
D49#
D50#
D51#
D52#
D53#
D54#
D55#
D56#
D57#
D58#
D59#
D60#
D61#
D62#
D63#

DINV0#
DINV1#
DINV2#
DINV3#

DSTBN0#
DSTBN1#
DSTBN2#
DSTBN3#
DSTBP0#
DSTBP1#
DSTBP2#
DSTBP3#

A20M#
FERR#

IGNNE#

LINT0
LINT1

STPCLK#

SMI#

INIT#

H_D#0

E22

D0#

H_D#1

F24

D1#

H_D#2

E26

D2#

H_D#3

H22

D3#

H_D#4

F23

D4#

H_D#5

G25

D5#

H_D#6

E25

D6#

H_D#7

E23

D7#

H_D#8

K24

D8#

H_D#9

G24

D9#

H_D#10

J24

H_D#11

J23

H_D#12

H26

H_D#13

F26

H_D#14

K22

H_D#15

H25

H_D#16

N22

H_D#17

K25

H_D#18

P26

H_D#19

R23

H_D#20

L25

H_D#21

L22

H_D#22

L23

H_D#23

M23

H_D#24

P25

H_D#25

P22

H_D#26

P23

H_D#27

T24

H_D#28

R24

H_D#29

L26

H_D#30

T25

H_D#31

N24

H_D#32

AA23

H_D#33

AB24

H_D#34

V24

H_D#35

V26

H_D#36

W25

H_D#37

U23

H_D#38

U25

H_D#39

U22

H_D#40

AB25

H_D#41

W22

H_D#42

Y23

H_D#43

AA26

H_D#44

Y26

H_D#45

Y22

H_D#46

AC26

H_D#47

AA24

H_D#48

AC22

H_D#49

AC23

H_D#50

AB22

H_D#51

AA21

H_D#52

AB21

H_D#53

AC25

H_D#54

AD20

H_D#55

AE22

H_D#56

AF23

H_D#57

AD24

H_D#58

AE21

H_D#59

AD21

H_D#60

AE25

H_D#61

AF25

H_D#62

AF22

H_D#63

AF26

H_DINV#0

J26

H_DINV#1

M26

H_DINV#2

V23

H_DINV#3

AC20

H_DSTBN#0

H23

H_DSTBN#1

M24

H_DSTBN#2

W24

H_DSTBN#3

AD23

H_DSTBP#0

G22

H_DSTBP#1

N25

H_DSTBP#2

Y25

H_DSTBP#3

AE24

H_A20M#

A6

H_FERR#

A5

H_IGNNE#

C4

H_INIT#

B3

H_INTR

C6

H_NMI

B4

H_STPCLK#

D5

H_SMI#

A3

H_D#[0..63]<7>

This shall place near CPU

ITP_TDI
ITP_TMS
ITP_TDO
ITP_BPM#5
ITP_TRST# ITP_BPM#4
ITP_TCK

R98 56_0402_5%

1 2

R97 56_0402_5%

1 2

R101 56_0402_5%

1 2

R103 56_0402_5%

1 2

R95 56_0402_5%

1 2

R96 56_0402_5%

1 2

Thermal Sensor G781F

EC_SMB_CK2<33>
EC_SMB_DA2<33>

H_DINV#0<7>
H_DINV#1<7>
H_DINV#2<7>
H_DINV#3<7>

H_DSTBN#[0..3]<7>

H_DSTBP#[0..3]<7>

H_A20M# <20>
H_FERR#<20>
H_IGNNE#<20>
H_INIT# <20>
H_INTR <20>
H_NMI <20>

H_STPCLK#<20>
H_SMI# <20>

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/10/06 2006/10/06

EN_FAN1<33>

Compal Secret Data

Deciphered Date

12

R219
150K_0402_5%

+VCCP

H_THERMDA

C311

H_THERMDC

1 2

2200P_0402_50V7K

EC_SMB_CK2 THERM#
EC_SMB_DA2

+VSB

C309

12

8

0.01U_0402_25V4Z

P

3

+IN

OUT

2

-IN

U15A

G

LM358A_SO8

4

1 2

R218
100K_0402_5%

5

+IN

OUT

6

-IN

U15B
LM358A_SO8

2

1

7

FAN1_ON

1N4148_SOD80

ITP_DBRESET#

U16

2

D+

3

D-

8

SCLK

7

SDATA

G781F_SOP8

Address:100_1100

+5VS

1

G

3

D11

R85 200_0402_1%@

1 2

1

VDD1

6

ALERT#

4

THERM#

5

GND

1 2

C303
10U_1206_10V4Z

6

2

D

Q19
SI3456BDV-T1-E3_TSOP6

S

4 5

FAN1

1

12

2

FAN_SPEED1<33>

Title

Yonah CPU in mFCPGA479

Size Document Number Rev

Custom

HGT30/31 LA-3061

Date: Sheet of

星期四二月

ITP_BPM#0
ITP_BPM#1
ITP_BPM#2
ITP_BPM#3

+3VS

12

C310 0.1U_0402_16V4Z

1

2

1000P_0402_50V7K

C307

C305 10U_0805_10V4Z

C308

1000P_0402_50V7K

Compal Electronics, Inc.

23, 2006

12

R22610K_0402_5%

+3VS

R222
10K_0402_5%

1 2

ACES_85205-0300

1

2

1

PAD
PAD

PAD
PAD
PAD
PAD

+3VS

T13
T17

T18
T20
T16
T19

JP2

1
2
3

4 47,

0.1

PDF created with pdfFactory Pro trial version www.pdffactory.com

5

4

3

2

1

+CPU_GTLREF

+VCCP

12

R69
1K_0402_1%

12

R62
2K_0402_1%

+CPU_CORE

R93
100_0402_1%

1 2

R94
100_0402_1%

1 2

Close to CPU pin
within 500mils.

VCCSENSE

VSSENSE

CPU_BSEL CPU_BSEL2 CPU_BSEL1

133

166

12

R70

27.4_0402_1%

0 0

0

12

R72

R102

54.9_0402_1%

D D

Close to CPU pin AD26
within 500mils.

C C

B B

Length match within 25 mils
The trace width 18 mils space
7 mils

+1.5VS

1

C122

2

10U_0805_10V4Z

CPU_BSEL0

1

1

12

12

R104

54.9_0402_1%

27.4_0402_1%

1

Resistor placed within

0.5" of CPU pin.Trace
should be at least 25
mils away from any
other toggling signal.

VCCSENSE<45>
VSSENSE<45>

1

C132

2

0.01U_0402_25V4Z

H_PSI#<45>

CPU_VID0<45>
CPU_VID1<45>
CPU_VID2<45>
CPU_VID3<45>
CPU_VID4<45>
CPU_VID5<45>
CPU_VID6<45>

+CPU_GTLREF

CPU_BSEL0<15>
CPU_BSEL1<15>
CPU_BSEL2<15>

+VCCP

+CPU_CORE

VCCSENSE
VSSENSE

H_PSI#
CPU_VID0

CPU_VID1
CPU_VID2
CPU_VID3
CPU_VID4
CPU_VID5
CPU_VID6

CPU_BSEL0
CPU_BSEL1
CPU_BSEL2

COMP0
COMP1
COMP2
COMP3

JP1B

AF7

VCCSENSE

AE7

VSSSENSE

B26

VCCA

K6

VCCP

J6

VCCP

M6

VCCP

N6

VCCP

T6

VCCP

R6

VCCP

K21

VCCP

J21

VCCP

M21

VCCP

N21

VCCP

T21

VCCP

R21

VCCP

V21

VCCP

W21

VCCP

V6

VCCP

G21

VCCP

AE6

PSI#

AD6

VID0

AF5

VID1

AE5

VID2

AF4

VID3

AE3

VID4

AF2

VID5

AE2

VID6

AD26

GTLREF

B22

BSEL0

B23

BSEL1

C21

BSEL2

R26

COMP0

U26

COMP1

U1

COMP2

V1

COMP3

E7

VCC

AB20

VCC

AA20

VCC

AF20

VCC

AE20

VCC

AB18

VCC

AB17

VCC

AA18

VCC

AA17

VCC

AD18

VCC

AD17

VCC

AC18

VCC

AC17

VCC

AF18

VCC

AF17

VCC

D2

RSVD

F6

RSVD

D3

RSVD

C1

RSVD

AF1

RSVD

D22

RSVD

C23

RSVD

C24

RSVD

AA1

RSVD

AA4

RSVD

AB2

RSVD

AA3

RSVD

M4

RSVD

N5

RSVD

T2

RSVD

V3

RSVD

B2

RSVD

C3

RSVD

T22

RSVD

B25

RSVD

TYCO_1-1674770-2_Yonah~D

ME@

YONAH

POWER, GROUNG, RESERVED SIGNALS AND NC

AB26

VSS

AA25

VSS

AD25

VSS

AE26

VSS

AB23

VSS

AC24

VSS

AF24

VSS

AE23

VSS

AA22

VSS

AD22

VSS

AC21

VSS

AF21

VSS

AB19

VSS

AA19

VSS

AD19

VSS

AC19

VSS

AF19

VSS

AE19

VSS

AB16

VSS

AA16

VSS

AD16

VSS

AC16

VSS

AF16

VSS

AE16

VSS

AB13

VSS

AA14

VSS

AD13

VSS

AC14

VSS

AF13

VSS

AE14

VSS

AB11

VSS

AA11

VSS

AD11

VSS

AC11

VSS

AF11

VSS

AE11

VSS

AB8

VSS

AA8

VSS

AD8

VSS

AC8

VSS

AF8

VSS

AE8

VSS

AA5

VSS

AD5

VSS

AC6

VSS

AF6

VSS

AB4

VSS

AC3

VSS

AF3

VSS

AE4

VSS

AB1

VSS

AA2

VSS

AD2

VSS

AE1

VSS

B6

VSS

C5

VSS

F5

VSS

E6

VSS

H6

VSS

J5

VSS

M5

VSS

L6

VSS

P6

VSS

R5

VSS

V5

VSS

U6

VSS

Y6

VSS

A4

VSS

D4

VSS

E3

VSS

H3

VSS

G4

VSS

K4

VSS

L3

VSS

P3

VSS

N4

VSS

T4

VSS

U3

VSS

Y3

VSS

W4

VSS

D1

VSS

C2

VSS

F2

VSS

G1

VSS

+CPU_CORE

JP1C

AE18

VCC

AE17

VCC

AB15

VCC

AA15

VCC

AD15

VCC

AC15

VCC

AF15

VCC

AE15

VCC

AB14

VCC

AA13

VCC

AD14

VCC

AC13

VCC

AF14

VCC

AE13

VCC

AB12

VCC

AA12

VCC

AD12

VCC

AC12

VCC

AF12

VCC

AE12

VCC

AB10

VCC

AB9

VCC

AA10

VCC

AA9

VCC

AD10

VCC

AD9

VCC

AC10

VCC

AC9

VCC

AF10

VCC

AF9

VCC

AE10

VCC

AE9

VCC

AB7

VCC

AA7

VCC

AD7

VCC

AC7

VCC

B20

VCC

A20

VCC

F20

VCC

E20

VCC

B18

VCC

B17

VCC

A18

VCC

A17

VCC

D18

VCC

D17

VCC

C18

VCC

C17

VCC

F18

VCC

F17

VCC

E18

VCC

E17

VCC

B15

VCC

A15

VCC

D15

VCC

C15

VCC

F15

VCC

E15

VCC

B14

VCC

A13

VCC

D14

VCC

C13

VCC

F14

VCC

E13

VCC

B12

VCC

A12

VCC

D12

VCC

C12

VCC

F12

VCC

E12

VCC

B10

VCC

B9

VCC

A10

VCC

A9

VCC

D10

VCC

D9

VCC

C10

VCC

C9

VCC

F10

VCC

F9

VCC

E10

VCC

E9

VCC

B7

VCC

A7

VCC

F7

VCC

TYCO_1-1674770-2_Yonah~D

ME@

YONAH

POWER, GROUND

K1

VSS

J2

VSS

M2

VSS

N1

VSS

T1

VSS

R2

VSS

V2

VSS

W1

VSS

A26

VSS

D26

VSS

C25

VSS

F25

VSS

B24

VSS

A23

VSS

D23

VSS

E24

VSS

B21

VSS

C22

VSS

F22

VSS

E21

VSS

B19

VSS

A19

VSS

D19

VSS

C19

VSS

F19

VSS

E19

VSS

B16

VSS

A16

VSS

D16

VSS

C16

VSS

F16

VSS

E16

VSS

B13

VSS

A14

VSS

D13

VSS

C14

VSS

F13

VSS

E14

VSS

B11

VSS

A11

VSS

D11

VSS

C11

VSS

F11

VSS

E11

VSS

B8

VSS

A8

VSS

D8

VSS

C8

VSS

F8

VSS

E8

VSS

G26

VSS

K26

VSS

J25

VSS

M25

VSS

N26

VSS

T26

VSS

R25

VSS

V25

VSS

W26

VSS

H24

VSS

G23

VSS

K23

VSS

L24

VSS

P24

VSS

N23

VSS

T23

VSS

U24

VSS

Y24

VSS

W23

VSS

H21

VSS

J22

VSS

M22

VSS

L21

VSS

P21

VSS

R22

VSS

V22

VSS

U21

VSS

Y21

VSS

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/10/06 2006/10/06

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet of

Compal Electronics, Inc.

Yonah CPU in mFCPGA479

HGT30/31 LA-3061

星期四二月

23, 2006

5 47,

1

0.1

PDF created with pdfFactory Pro trial version www.pdffactory.com

5

4

3

2

1

D D

Place these capacitors on L8
(North side,Secondary Layer)

Place these capacitors on L8
(North side,Secondary Layer)

Place these capacitors on L8
(Sorth side,Secondary Layer)

C C

Place these capacitors on L8
(Sorth side,Secondary Layer)

South Side Secondary

B B

+CPU_CORE

+CPU_CORE

+CPU_CORE

+CPU_CORE

+CPU_CORE

1

+

C324

2

330U_V_2.5VK_R9

1

C318
10U_0805_6.3V6M

2

1

C325
10U_0805_6.3V6M

2

1

C183
10U_0805_6.3V6M

2

1

C150
10U_0805_6.3V6M

2

C180

330U_V_2.5VK_R9

1

C326
10U_0805_6.3V6M

2

1

C186
10U_0805_6.3V6M

2

1

C170
10U_0805_6.3V6M

2

1

C165
10U_0805_6.3V6M

2

1

1

+

+

C175

2

2

330U_V_2.5VK_R9

1

C151
10U_0805_6.3V6M

2

1

C341
10U_0805_6.3V6M

2

1

C334
10U_0805_6.3V6M

2

1

C345
10U_0805_6.3V6M

2

1

+

C339

2

330U_V_2.5VK_R9

1

C171
22U_0805_6.3V6M

2

1

C178
10U_0805_6.3V6M

2

1

C319
10U_0805_6.3V6M

2

1

C173
10U_0805_6.3V6M

2

1

+

C343

C320

2

330U_V_2.5VK_R9

330U_V_2.5VK_R9

1

C346
10U_0805_6.3V6M

2

1

C316
10U_0805_6.3V6M

2

1

C172
22U_0805_6.3V6M

2

1

C179
10U_0805_6.3V6M

2

1

+

2

North Side Secondary

1

C184
10U_0805_6.3V6M

2

1

C185
10U_0805_6.3V6M

2

1

C333
10U_0805_6.3V6M

2

1

C177
10U_0805_6.3V6M

2

1

2

1

2

1

2

ESR <= 1.5m ohm
Capacitor > 1980uF

C166
10U_0805_6.3V6M

C181
22U_0805_6.3V6M

C317
10U_0805_6.3V6M

1

C342
10U_0805_6.3V6M

2

1

C176
10U_0805_6.3V6M

2

1

C182
22U_0805_6.3V6M

2

Mid Frequence Decoupling

+VCCP

1

C109

220U_D2_4VM

2

A A

C190

0.1U_0402_16V4Z

2

1

+

1

C136

0.1U_0402_16V4Z

2

1

C138

0.1U_0402_16V4Z

2

1

C137

0.1U_0402_16V4Z

2

1

C189

0.1U_0402_16V4Z

2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

1

C188

0.1U_0402_16V4Z

2

3

Place these inside
socket cavity on L8
(North side
Secondary)

2005/10/06 2006/10/06

Compal Secret Data

Deciphered Date

2

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

CPU Bypass capacitors

HGT30/31 LA-3061

星期四二月

23, 2006

1

6 47,

0.1

PDF created with pdfFactory Pro trial version www.pdffactory.com

5

4

U14

3

2

1

H_D#[0..63]<4>

D D

C C

+VCCP

12

12

R26

B B

R27

54.9_0402_1%

54.9_0402_1%

+H_VREF
H_XRCOMP
H_XSCOMP
H_YRCOMP
H_YSCOMP
+H_SWNG0
+H_SWNG1

12

12

R20

R23

24.9_0402_1%

24.9_0402_1%

Layout Note:
H_XRCOMP / H_YRCOMP / H_VREF / H_SWNG0 /
H_SWNG1 trace width and spacing is 10/20.

+VCCP

12

A A

R30

100_0402_1%

+H_VREF

12

1

R36

C26

2

200_0402_1%

0.1U_0402_16V4Z

5

H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63

U14A

F1

HD0#

J1

HD1#

H1

HD2#

J6

HD3#

H3

HD4#

K2

HD5#

G1

HD6#

G2

HD7#

K9

HD8#

K1

HD9#

K7

HD10#

J8

HD11#

H4

HD12#

J3

HD13#

K11

HD14#

G4

HD15#

T10

HD16#

W11

HD17#

T3

HD18#

U7

HD19#

U9

HD20#

U11

HD21#

T11

HD22#

W9

HD23#

T1

HD24#

T8

HD25#

T4

HD26#

W7

HD27#

U5

HD28#

T9

HD29#

W6

HD30#

T5

HD31#

AB7

HD32#

AA9

HD33#

W4

HD34#

W3

HD35#

Y3

HD36#

Y7

HD37#

W5

HD38#

Y10

HD39#

AB8

HD40#

W2

HD41#

AA4

HD42#

AA7

HD43#

AA2

HD44#

AA6

HD45#

AA10

HD46#

Y8

HD47#

AA1

HD48#

AB4

HD49#

AC9

HD50#

AB11

HD51#

AC11

HD52#

AB3

HD53#

AC2

HD54#

AD1

HD55#

AD9

HD56#

AC1

HD57#

AD7

HD58#

AC6

HD59#

AB5

HD60#

AD10

HD61#

AD4

HD62#

AC8

HD63#

J13

HVREF0

K13

HVREF1

E1

HXRCOMP

E2

HXSCOMP

Y1

HYRCOMP

U1

HYSCOMP

E4

HXSWING

W1

HYSWING

CALISTOGA_FCBGA1466~D

UMA_GM@

HOST

HA3#
HA4#
HA5#
HA6#
HA7#
HA8#

HA9#
HA10#
HA11#
HA12#
HA13#
HA14#
HA15#
HA16#
HA17#
HA18#
HA19#
HA20#
HA21#
HA22#
HA23#
HA24#
HA25#
HA26#
HA27#
HA28#
HA29#
HA30#
HA31#

HREQ#0
HREQ#1
HREQ#2
HREQ#3
HREQ#4

HADSTB#0
HADSTB#1

HCLKN
HCLKP

HDSTBN#0
HDSTBN#1
HDSTBN#2
HDSTBN#3
HDSTBP#0
HDSTBP#1
HDSTBP#2
HDSTBP#3

HDINV#0
HDINV#1
HDINV#2
HDINV#3

HCPURST#

HADS#

HTRDY#

HDPWR#

HDRDY#

HDEFER#

HHITM#

HHIT#

HLOCK#

HBREQ0#

HBNR#
HBPRI#

HDBSY#

HCPUSLP#

HRS0#
HRS1#
HRS2#

12

R22

12

R24

221_0603_1%

100_0402_1%

H9
C9
E11
G11
F11
G12
F9
H11
J12
G14
D9
J14
H13
J15
F14
D12
A11
C11
A12
A13
E13
G13
F12
B12
B14
C12
A14
C14
D14

D8
G8
B8
F8
A8

B9
C13

AG1
AG2

K4
T7
Y5
AC4
K3
T6
AA5
AC5

J7
W8
U3
AB10

B7
E8
E7
J9
H8
C3
D4
D3
B3
C7
C6
F6
A7
E3

B4
E6
D6

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

H_ADSTB#0
H_ADSTB#1

CLK_MCH_BCLK#
CLK_MCH_BCLK

H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3
H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3

H_DINV#0
H_DINV#1
H_DINV#2
H_DINV#3

H_RESET#
H_ADS#
H_TRDY#
H_DPWR#
H_DRDY#
H_DEFER#
H_HITM#
H_HIT#
H_LOCK#
H_BR0#
H_BNR#
H_BPRI#
H_DBSY#
H_CPUSLP#

H_RS#0
H_RS#1
H_RS#2

+H_SWNG0

1

C19

2

0.1U_0402_16V4Z

4

+VCCP+VCCP

12

R18

12

R19

H_A#[3..31]<4>

H_REQ#[0..4]<4>

H_ADSTB#0<4>
H_ADSTB#1<4>

CLK_MCH_BCLK#<15>
CLK_MCH_BCLK<15>
H_DSTBN#[0..3]<4>

H_DSTBP#[0..3]<4>

H_DINV#0<4>
H_DINV#1<4>
H_DINV#2<4>
H_DINV#3<4>

H_RESET#<4>
H_ADS# <4>
H_TRDY#<4>
H_DPWR#<4>
H_DRDY#<4>
H_DEFER#<4>
H_HITM# <4>
H_HIT# <4>
H_LOCK#<4>
H_BR0# <4>
H_BNR# <4>
H_BPRI# <4>
H_DBSY#<4>
H_CPUSLP#<4,20>

H_RS#[0..2]<4>

221_0603_1%

+H_SWNG1

1

2

100_0402_1%

0.1U_0402_16V4Z

PM

VGA@

3

DDR_CKE0_DIMMA<13>
DDR_CKE1_DIMMA<13>
DDR_CKE2_DIMMB<14>
DDR_CKE3_DIMMB<14>

DDR_CS0_DIMMA#<13>
DDR_CS1_DIMMA#<13>
DDR_CS2_DIMMB#<14>
DDR_CS3_DIMMB#<14>

1 2
1 2

DMI_TXN0<21>
DMI_TXN1<21>
DMI_TXN2<21>
DMI_TXN3<21>

DMI_TXP0<21>
DMI_TXP1<21>
DMI_TXP2<21>
DMI_TXP3<21>

DMI_RXN0<21>
DMI_RXN1<21>
DMI_RXN2<21>
DMI_RXN3<21>

DMI_RXP0<21>
DMI_RXP1<21>
DMI_RXP2<21>
DMI_RXP3<21>

M_CLK_DDR0<13>
M_CLK_DDR1<13>
M_CLK_DDR2<14>
M_CLK_DDR3<14>

M_CLK_DDR#0<13>
M_CLK_DDR#1<13>
M_CLK_DDR#2<14>
M_CLK_DDR#3<14>

M_ODT0<13>
M_ODT1<13>
M_ODT2<14>
M_ODT3<14>

+DDR_MCH_REF

PM_BMBUSY#<21>
PM_EXTTS#0<13,14>

12

H_THERMTRIP#<4,20>

ICH_POK<21,33>

R55 100_0402_1%

MCH_ICH_SYNC#<19>

Layout Note:
+DDR_MCH_REF
trace width and
spacing is 20/20.

+DDR_MCH_REF PM_EXTTS#1

C16

0.1U_0402_16V4Z

2005/10/06 2006/10/06

U14

GML

UMA_GML@

+1.8V

R29 80.6_0402_1%
R28 80.6_0402_1%

R88
0_0402_5%

DPRSLPVR<21,45>

PLT_RST#<19,23,28,37>

C11

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

1

2

DMI_TXN0
DMI_TXN1
DMI_TXN2
DMI_TXN3

DMI_TXP0

DMI_TXP1
DMI_TXP2
DMI_TXP3

DMI_RXN0
DMI_RXN1
DMI_RXN2
DMI_RXN3

DMI_RXP0
DMI_RXP1
DMI_RXP2
DMI_RXP3

M_CLK_DDR0
M_CLK_DDR1
M_CLK_DDR2
M_CLK_DDR3

M_CLK_DDR#0
M_CLK_DDR#1
M_CLK_DDR#2
M_CLK_DDR#3

DDR_CKE0_DIMMA
DDR_CKE1_DIMMA
DDR_CKE2_DIMMB
DDR_CKE3_DIMMB

DDR_CS0_DIMMA#
DDR_CS1_DIMMA#
DDR_CS2_DIMMB#
DDR_CS3_DIMMB#

M_OCDOCMP0
M_OCDOCMP1

M_ODT0
M_ODT1
M_ODT2
M_ODT3

SMRCOMPN
SMRCOMPP

PM_BMBUSY#
PM_EXTTS#0
PM_EXTTS#1
H_THERMTRIP#
ICH_POK
PLTRST_R#

12

+1.8V

12

R25

12

R21

Compal Secret Data

100_0402_1%

100_0402_1%

U14B

AE35
AF39
AG35
AH39

AC35
AE39
AF35
AG39

AE37
AF41
AG37
AH41

AC37
AE41
AF37
AG41

AY35

AR1

AW7

AW40
AW35

AT1
AY7

AY40

AU20

AT20

BA29

AY29

AW13
AW12

AY21

AW21

AL20

AF10
BA13

BA12

AY20

AU21

AV9

AT9

AK1

AK41

G28

F25
H26

G6
AH33
AH34

K28

CALISTOGA_FCBGA1466~D

UMA_GM@

Deciphered Date

DMIRXN0
DMIRXN1
DMIRXN2
DMIRXN3

DMIRXP0
DMIRXP1
DMIRXP2
DMIRXP3

DMITXN0
DMITXN1
DMITXN2
DMITXN3

DMITXP0
DMITXP1
DMITXP2
DMITXP3

SM_CK0
SM_CK1
SM_CK2
SM_CK3

SM_CK0#
SM_CK1#
SM_CK2#
SM_CK3#

SM_CKE0
SM_CKE1
SM_CKE2
SM_CKE3

SM_CS0#
SM_CS1#
SM_CS2#
SM_CS3#

SM_OCDCOMP0
SM_OCDCOMP1

SM_ODT0
SM_ODT1
SM_ODT2
SM_ODT3

SM_RCOMPN
SM_RCOMPP

SM_VREF0
SM_VREF1

PM_BMBUSY#
PM_EXTTS0#
PM_EXTTS1#
PM_THERMTRIP#
PWROK
RSTIN#

ICH_SYNC#

CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6

DMI

DDR MUXING

PM

2

CFG7
CFG8

CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG16

C FG

CFG17
CFG18
CFG19
CFG20

G_CLKP
G_CLKN

D_REF_CLKN
D_REF_CLKP

CLKNC

D_REF_SSCLKN
D_REF_SSCLKP

CLK_REQ#

NC0
NC1
NC2
NC3
NC4
NC5
NC6
NC7
NC8

NC9
NC10
NC11
NC12
NC13
NC14
NC15
NC16
NC17
NC18

RESERVED1
RESERVED2
RESERVED3
RESERVED4
RESERVED5
RESERVED6
RESERVED7
RESERVED8

RESERVED9
RESERVED10
RESERVED11
RESERVED12
RESERVED13

RESE RVED

Title

Size Document Number Rev

Custom

Date: Sheet of

Description at page15.

MCH_CLKSEL0

K16

MCH_CLKSEL1

K18

MCH_CLKSEL2

J18

CFG3

F18

CFG4

E15

CFG5

F15

CFG6

E18

CFG7

D19

CFG8

D16

CFG9

G16

CFG10

E16

CFG11

D15

CFG12

G15

CFG13

K15

CFG14

C15

CFG15

H16

CFG16

G18

CFG17

H15

CFG18

J25

CFG19

K27

CFG20

J26

CLK_MCH_3GPLL

AG33

CLK_MCH_3GPLL#

AF33

CLK_MCH_DREFCLK#

A27

CLK_MCH_DREFCLK

A26

MCH_SSCDREFCLK#

C40

MCH_SSCDREFCLK

D41

MCH_CLKREQ#

H32

A3
A39
A4
A40
AW1
AW41
AY1
BA1
BA2
BA3
BA39
BA40
BA41
C1
AY41
B2
B41
C41
D1

T32
R32
F3
F7
AG11
AF11
H7
J19
A41
A34
D28
D27
A35

M_OCDOCMP0

M_OCDOCMP1

PAD
PAD

PAD
PAD
PAD

PAD
PAD

PAD

PM_EXTTS#0

MCH_CLKSEL0<15>
MCH_CLKSEL1<15>

MCH_CLKSEL2<15>

T9
T3

CFG5 <11>

T10

CFG7 <11>

T7

CFG9 <11>

T5

CFG11 <11>

CFG12 <11>

CFG13 <11>

T2
T8

CFG16 <11>

T1

CFG18 <11>

CFG19 <11>

CFG20 <11>

MCH_CLKREQ#<15>

R46

10K_0402_5%

R49

10K_0402_5%@

R45

40.2_0402_1%@

R31

40.2_0402_1%@

Compal Electronics, Inc.

Calistoga (1/6)

HGT30/31 LA-3061

星期四二月

23, 2006

1

CLK_MCH_3GPLL<15>
CLK_MCH_3GPLL#<15>

CLK_MCH_DREFCLK#<15>
CLK_MCH_DREFCLK<15>

CLK_MCH_SSCDREFCLK#<15>
CLK_MCH_SSCDREFCLK<15>

+3VS

12

12

12

12

7 47,

0.1

PDF created with pdfFactory Pro trial version www.pdffactory.com

5

D D

4

3

2

1

DDR_A_BS#0<13>
DDR_A_BS#1<13>
DDR_A_BS#2<13>

DDR_A_DM[0..7]<13>

DDR_A_DQS[0..7]<13>

C C

DDR_A_DQS#[0..7]<13>

DDR_A_MA[0..13]<13>

B B

DDR_A_CAS#<13>
DDR_A_RAS#<13>

DDR_A_WE#<13>

T6 PAD
T12PAD

DDR_A_BS#0
DDR_A_BS#1
DDR_A_BS#2

DDR_A_DM0
DDR_A_DM1
DDR_A_DM2
DDR_A_DM3
DDR_A_DM4
DDR_A_DM5
DDR_A_DM6
DDR_A_DM7

DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7

DDR_A_DQS#0
DDR_A_DQS#1
DDR_A_DQS#2
DDR_A_DQS#3
DDR_A_DQS#4
DDR_A_DQS#5
DDR_A_DQS#6
DDR_A_DQS#7

DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5

DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11 DDR_B_MA11
DDR_A_MA12
DDR_A_MA13

DDR_A_CAS#
DDR_A_RAS#
DDR_A_WE#
SA_RCVENIN#
SA_RCVENOUT#

check layout check layout

U14D

AU12

SA_BS0

AV14

SA_BS1

BA20

SA_BS2

AJ33

SA_DM0

AM35

SA_DM1

AL26

SA_DM2

AN22

SA_DM3

AM14

SA_DM4

AL9

SA_DM5

AR3

SA_DM6

AH4

SA_DM7

AK33

SA_DQS0

AT33

SA_DQS1

AN28

SA_DQS2

AM22

SA_DQS3

AN12

SA_DQS4

AN8

SA_DQS5

AP3

SA_DQS6

AG5

SA_DQS7

AK32

SA_DQS0#

AU33

SA_DQS1#

AN27

SA_DQS2#

AM21

SA_DQS3#

AM12

SA_DQS4#

AL8

SA_DQS5#

AN3

SA_DQS6#

AH5

SA_DQS7#

AY16

SA_MA0

AU14

SA_MA1

AW16

SA_MA2

BA16

SA_MA3

BA17

SA_MA4

AU16

SA_MA5

AV17

SA_MA6

AU17

SA_MA7

AW17

SA_MA8

AT16

SA_MA9

AU13

SA_MA10

AT17

SA_MA11

AV20

SA_MA12

AV12

SA_MA13

AY13

SA_CAS#

AW14

SA_RAS#

AY14

SA_WE#

AK23

SA_RCVENIN#

AK24

SA_RCVENOUT#

CALISTOGA_FCBGA1466~D

UMA_GM@

SA_DQ0
SA_DQ1
SA_DQ2
SA_DQ3
SA_DQ4
SA_DQ5
SA_DQ6
SA_DQ7
SA_DQ8

SA_DQ9
SA_DQ10
SA_DQ11
SA_DQ12
SA_DQ13
SA_DQ14
SA_DQ15
SA_DQ16
SA_DQ17
SA_DQ18
SA_DQ19
SA_DQ20
SA_DQ21
SA_DQ22
SA_DQ23
SA_DQ24
SA_DQ25
SA_DQ26
SA_DQ27
SA_DQ28
SA_DQ29
SA_DQ30
SA_DQ31
SA_DQ32
SA_DQ33
SA_DQ34
SA_DQ35
SA_DQ36
SA_DQ37
SA_DQ38
SA_DQ39

DDR SYS MEMORY A

SA_DQ40
SA_DQ41
SA_DQ42
SA_DQ43
SA_DQ44
SA_DQ45
SA_DQ46
SA_DQ47
SA_DQ48
SA_DQ49
SA_DQ50
SA_DQ51
SA_DQ52
SA_DQ53
SA_DQ54
SA_DQ55
SA_DQ56
SA_DQ57
SA_DQ58
SA_DQ59
SA_DQ60
SA_DQ61
SA_DQ62
SA_DQ63

AJ35
AJ34
AM31
AM33
AJ36
AK35
AJ32
AH31
AN35
AP33
AR31
AP31
AN38
AM36
AM34
AN33
AK26
AL27
AM26
AN24
AK28
AL28
AM24
AP26
AP23
AL22
AP21
AN20
AL23
AP24
AP20
AT21
AR12
AR14
AP13
AP12
AT13
AT12
AL14
AL12
AK9
AN7
AK8
AK7
AP9
AN9
AT5
AL5
AY2
AW2
AP1
AN2
AV2
AT3
AN1
AL2
AG7
AF9
AG4
AF6
AG9
AH6
AF4
AF8

DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63

DDR_A_D[0..63]<13> DDR_B_D[0..63]<14>

DDR_B_BS#0<14>
DDR_B_BS#1<14>
DDR_B_BS#2<14>

DDR_B_DM[0..7]<14>

DDR_B_DQS[0..7]<14>

DDR_B_DQS#[0..7]<14>

DDR_B_MA[0..13]<14>

DDR_B_CAS#<14>

DDR_B_RAS#<14>

DDR_B_WE#<14>

T4 PAD
T11PAD

DDR_B_BS#0
DDR_B_BS#1
DDR_B_BS#2

DDR_B_DM0
DDR_B_DM1
DDR_B_DM2
DDR_B_DM3
DDR_B_DM4
DDR_B_DM5
DDR_B_DM6
DDR_B_DM7

DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4
DDR_B_DQS5
DDR_B_DQS6
DDR_B_DQS7

DDR_B_DQS#0
DDR_B_DQS#1
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS#4
DDR_B_DQS#5
DDR_B_DQS#6
DDR_B_DQS#7

DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6DDR_A_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10

DDR_B_MA12
DDR_B_MA13

DDR_B_CAS#
DDR_B_RAS#
DDR_B_WE#
SB_RCVENIN#
SB_RCVENOUT#

U14E

AT24

SB_BS0

AV23

SB_BS1

AY28

SB_BS2

AK36

SB_DM0

AR38

SB_DM1

AT36

SB_DM2

BA31

SB_DM3

AL17

SB_DM4

AH8

SB_DM5

BA5

SB_DM6

AN4

SB_DM7

AM39

SB_DQS0

AT39

SB_DQS1

AU35

SB_DQS2

AR29

SB_DQS3

AR16

SB_DQS4

AR10

SB_DQS5

AR7

SB_DQS6

AN5

SB_DQS7

AM40

SB_DQS0#

AU39

SB_DQS1#

AT35

SB_DQS2#

AP29

SB_DQS3#

AP16

SB_DQS4#

AT10

SB_DQS5#

AT7

SB_DQS6#

AP5

SB_DQS7#

AY23

SB_MA0

AW24

SB_MA1

AY24

SB_MA2

AR28

SB_MA3

AT27

SB_MA4

AT28

SB_MA5

AU27

SB_MA6

AV28

SB_MA7

AV27

SB_MA8

AW27

SB_MA9

AV24

SB_MA10

BA27

SB_MA11

AY27

SB_MA12

AR23

SB_MA13

AR24

SB_CAS#

AU23

SB_RAS#

AR27

SB_WE#

AK16

SB_RCVENIN#

AK18

SB_RCVENOUT#

CALISTOGA_FCBGA1466~D

UMA_GM@

SB_DQ0
SB_DQ1
SB_DQ2
SB_DQ3
SB_DQ4
SB_DQ5
SB_DQ6
SB_DQ7
SB_DQ8

SB_DQ9
SB_DQ10
SB_DQ11
SB_DQ12
SB_DQ13
SB_DQ14
SB_DQ15
SB_DQ16
SB_DQ17
SB_DQ18
SB_DQ19
SB_DQ20
SB_DQ21
SB_DQ22
SB_DQ23
SB_DQ24
SB_DQ25
SB_DQ26
SB_DQ27
SB_DQ28
SB_DQ29
SB_DQ30
SB_DQ31
SB_DQ32
SB_DQ33
SB_DQ34
SB_DQ35
SB_DQ36
SB_DQ37
SB_DQ38
SB_DQ39

DDR SYS MEMORY B

SB_DQ40
SB_DQ41
SB_DQ42
SB_DQ43
SB_DQ44
SB_DQ45
SB_DQ46
SB_DQ47
SB_DQ48
SB_DQ49
SB_DQ50
SB_DQ51
SB_DQ52
SB_DQ53
SB_DQ54
SB_DQ55
SB_DQ56
SB_DQ57
SB_DQ58
SB_DQ59
SB_DQ60
SB_DQ61
SB_DQ62
SB_DQ63

AJ37
AP39
AR41
AJ38
AK38
AN41
AP41
AT40
AV41
AU38
AV38
AP38
AR40
AW38
AY38
BA38
AV36
AR36
AP36
BA36
AU36
AP35
AP34
AY33
BA33
AT31
AU29
AU31
AW31
AV29
AW29
AM19
AL19
AP14
AN14
AN17
AM16
AP15
AL15
AJ11
AH10
AJ9
AN10
AK13
AH11
AK10
AJ8
BA10
AW10
BA4
AW4
AY10
AY9
AW5
AY5
AV4
AR5
AK4
AK3
AT4
AK5
AJ5
AJ3

DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63

DDR_B_D0

AK39

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/10/06 2006/10/06

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet of

Compal Electronics, Inc.

Calistoga (2/6)

HGT30/31 LA-3061

星期四二月

23, 2006

1

8 47,

0.1

PDF created with pdfFactory Pro trial version www.pdffactory.com

5

D D

LVDSA0+<38>
LVDSA1+<38>
LVDSA2+<38>

LVDSA0-<38>
LVDSA1-<38>

LVDSA2-<38>

LVDSB0+<38>
LVDSB1+<38>
LVDSB2+<38>

LVDSB0-<38>
LVDSB1-<38>
LVDSB2-<38>

LVDSAC+<38>
LVDSAC-<38>

LVDSBC+<38>

C C

TV_COMPS

12

R207 150_0603_1%UMA@
R208 150_0603_1% UMA@
R209 150_0603_1%UMA@

B B

+2.5VS +3VS

12
12

R210 150_0603_1% UMA@

R212 150_0603_1%UMA@

TV_LUMA
TV_CRMA

12
12
12

CRT_R
CRT_G

CRT_B

LVDSBC-<38>

GMCH_ENBKL<16>

GMCH_LVDDEN<16>

TV_COMPS<17>
TV_LUMA<17>
TV_CRMA<17>

3VDDCCL<17>

3VDDCDA<17>

CRT_VSYNC<17>
CRT_HSYNC<17>

CRT_B<17>
CRT_G<17>
CRT_R<17>

R53 1.5K_0402_1%

TV_COMPS
TV_LUMA
TV_CRMA

4

LVDSA0+
LVDSA1+
LVDSA2+

LVDSA0­LVDSA1­LVDSA2-

LVDSB0+
LVDSB1+
LVDSB2+

LVDSB0­LVDSB1­LVDSB2-

LVDSAC+
LVDSAC­LVDSBC+
LVDSBC-

GMCH_ENBKL

LDDC_CLK
LDDC_DATA

GMCH_LVDDEN

12

R42

4.99K_0402_1%

3VDDCCL
3VDDCDA

CRT_VSYNC
CRT_HSYNC
CRT_B

CRT_G
CRT_R

R47

255_0402_1%

H27
H28

B37
B34
A36

C37
B35
A37

F30
D29
F28

G30
D30
F29

A32
A33
E26
E27

D32
H30

H29
G26
G25
F32
B38
C35
C33
C32

A16
C18
A19

12

B16
B18
B19

K30

C26
C25

H23
G23
E23
D23
C22
B22
A21
B21

12

U14C

SDVOCTRL_DATA
SDVOCTRL_CLK

LA_DATA0
LA_DATA1
LA_DATA2

LA_DATA#0
LA_DATA#1
LA_DATA#2

LB_DATA0
LB_DATA1
LB_DATA2

LB_DATA#0
LB_DATA#1
LB_DATA#2

LA_CLK
LA_CLK#
LB_CLK
LB_CLK#

LBKLT_CTL

J30

LBKLT_EN
LCTLA_CLK
LCTLB_DATA
LDDC_CLK
LDDC_DATA
LVDD_EN
LIBG
LVBG
LVREFH
LVREFL

TVDAC_A
TVDAC_B
TVDAC_C

J20

TV_IREF
TV_IRTNA

TV_IRTNB
TV_IRTNC

J29

TV_DCONSEL1
TV_DCONSEL0

DDCCLK
DDCDATA

VSYNC
HSYNC
BLUE
BLUE#
GREEN
GREEN#
RED
RED#

J22

CRT_IREF

CALISTOGA_FCBGA1466~D

UMA_GM@

3

+1.5VS_PCIE

R54

EXP_COMPO

EXP_RXN0
EXP_RXN1
EXP_RXN2
EXP_RXN3
EXP_RXN4
EXP_RXN5
EXP_RXN6
EXP_RXN7

PCI-EXPRESS GRAPHICS

EXP_RXN8

EXP_RXN9
EXP_RXN10
EXP_RXN11
EXP_RXN12
EXP_RXN13
EXP_RXN14
EXP_RXN15

EXP_RXP0

EXP_RXP1

EXP_RXP2

EXP_RXP3

EXP_RXP4

EXP_RXP5

EXP_RXP6

EXP_RXP7

EXP_RXP8

EXP_RXP9
EXP_RXP10
EXP_RXP11
EXP_RXP12
EXP_RXP13
EXP_RXP14
EXP_RXP15

EXP_TXN0

EXP_TXN1

EXP_TXN2

EXP_TXN3

EXP_TXN4

EXP_TXN5

EXP_TXN6

EXP_TXN7

EXP_TXN8

EXP_TXN9
EXP_TXN10
EXP_TXN11
EXP_TXN12
EXP_TXN13
EXP_TXN14
EXP_TXN15

EXP_TXP0

EXP_TXP1

EXP_TXP2

EXP_TXP3

EXP_TXP4

EXP_TXP5

EXP_TXP6

EXP_TXP7

EXP_TXP8

EXP_TXP9
EXP_TXP10
EXP_TXP11
EXP_TXP12
EXP_TXP13
EXP_TXP14
EXP_TXP15

LV DS

TV CRT

F34
G38
H34
J38
L34
M38
N34
P38
R34
T38
V34
W38
Y34
AA38
AB34
AC38

D34
F38
G34
H38
J34
L38
M34
N38
P34
R38
T34
V38
W34
Y38
AA34
AB38

F36
G40
H36
J40
L36
M40
N36
P40
R36
T40
V36
W40
Y36
AA40
AB36
AC40

D36
F40
G36
H40
J36
L40
M36
N40
P36
R40
T36
V40
W36
Y40
AA36
AB40

PEG_RXN0
PEG_RXN1
PEG_RXN2
PEG_RXN3
PEG_RXN4
PEG_RXN5
PEG_RXN6
PEG_RXN7
PEG_RXN8
PEG_RXN9
PEG_RXN10
PEG_RXN11
PEG_RXN12
PEG_RXN13
PEG_RXN14
PEG_RXN15

PEG_RXP0
PEG_RXP1
PEG_RXP2
PEG_RXP3
PEG_RXP4
PEG_RXP5
PEG_RXP6
PEG_RXP7
PEG_RXP8
PEG_RXP9
PEG_RXP10
PEG_RXP11
PEG_RXP12
PEG_RXP13
PEG_RXP14
PEG_RXP15

PEG_TXN0
PEG_TXN1
PEG_TXN2
PEG_TXN3
PEG_TXN4
PEG_TXN5
PEG_TXN6
PEG_TXN7
PEG_TXN8
PEG_TXN9
PEG_TXN10
PEG_TXN11
PEG_TXN12
PEG_TXN13
PEG_TXN14
PEG_TXN15

PEG_TXP0
PEG_TXP1
PEG_TXP2
PEG_TXP3
PEG_TXP4
PEG_TXP5
PEG_TXP6
PEG_TXP7
PEG_TXP8
PEG_TXP9
PEG_TXP10
PEG_TXP11
PEG_TXP12
PEG_TXP13
PEG_TXP14
PEG_TXP15

PEGCOMP

D40

EXP_COMPI

D38

24.9_0402_1%

1 2

C153 0.1U_0402_16V4Z
C124 0.1U_0402_16V4Z
C142 0.1U_0402_16V4Z
C115 0.1U_0402_16V4Z
C155 0.1U_0402_16V4Z
C126 0.1U_0402_16V4Z
C148 0.1U_0402_16V4Z
C117 0.1U_0402_16V4Z
C157 0.1U_0402_16V4Z
C128 0.1U_0402_16V4Z
C140 0.1U_0402_16V4Z
C119 0.1U_0402_16V4Z
C159 0.1U_0402_16V4Z
C130 0.1U_0402_16V4Z
C144 0.1U_0402_16V4Z
C121 0.1U_0402_16V4Z

C152 0.1U_0402_16V4Z
C123 0.1U_0402_16V4Z
C141 0.1U_0402_16V4Z
C114 0.1U_0402_16V4Z
C154 0.1U_0402_16V4Z
C125 0.1U_0402_16V4Z
C147 0.1U_0402_16V4Z
C116 0.1U_0402_16V4Z
C156 0.1U_0402_16V4Z R211 150_0603_1%UMA@
C127 0.1U_0402_16V4Z
C139 0.1U_0402_16V4Z
C118 0.1U_0402_16V4Z
C158 0.1U_0402_16V4Z
C129 0.1U_0402_16V4Z
C143 0.1U_0402_16V4Z
C120 0.1U_0402_16V4Z

PEG_RXN[0..15]<18>

PEG_RXP[0..15]<18>

PEG_M_TXN0
PEG_M_TXN1
PEG_M_TXN2
PEG_M_TXN3
PEG_M_TXN4
PEG_M_TXN5
PEG_M_TXN6
PEG_M_TXN7
PEG_M_TXN8
PEG_M_TXN9
PEG_M_TXN10
PEG_M_TXN11
PEG_M_TXN12
PEG_M_TXN13
PEG_M_TXN14
PEG_M_TXN15

PEG_M_TXP0
PEG_M_TXP1
PEG_M_TXP2
PEG_M_TXP3
PEG_M_TXP4
PEG_M_TXP5
PEG_M_TXP6
PEG_M_TXP7
PEG_M_TXP8
PEG_M_TXP9
PEG_M_TXP10
PEG_M_TXP11
PEG_M_TXP12
PEG_M_TXP13
PEG_M_TXP14
PEG_M_TXP15

2

PEG_M_TXN[0..15]<18>

PEG_M_TXP[0..15]<18>

1

12

12

2.2K_0402_5%

R215

UMA@

LDDC_CLK

A A

LDDC_DATA EDID_DAT_LCD

R216

UMA@

2.2K _0402_5%

2.2K_0402_5%

BSS138_SOT23

+2.5VS

BSS138_SOT23

R710 0_0402_5%@

5

R709 0_0402_5%@

S

Q18

G

UMA@

2

G

2

S

Q17

UMA@

12

D

13

13

D

12

R214

UMA@

12

4

12

R217

2.2K_0402_5%

UMA@

EDID_CLK_LCD

EDID_CLK_LCD<38>

EDID_DAT_LCD<38>

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/10/06 2006/10/06

Compal Secret Data

Deciphered Date

2

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

Calistoga (3/6)

HGT30/31 LA-3061

星期四二月

23, 2006

1

9 47,

0.1

PDF created with pdfFactory Pro trial version www.pdffactory.com

5

+VCCP

4

3

2

1

21

VCC3G0
VCC3G1
VCC3G2
VCC3G3
VCC3G4
VCC3G5
VCC3G6

VCCHV0
VCCHV1
VCCHV2

H22

B30
C30
A30

AB41
AJ41
L41
N41
R41
V41
Y41

AC33
G41
H41

E21
F21
G21

B26
C39
AF1

A38
B39

AF2
H20

G20

E19
F19
C20
D20
E20
F20

AH1
AH2

A28
B28
C28

D21
H19

A23
B23
B25

AK31
AF31
AE31
AC31
AL30
AK30
AJ30
AH30
AG30
AF30
AE30
AD30
AC30
AG29
AF29
AE29
AD29
AC29
AG28
AF28
AE28
AH22
AJ21
AH21
AJ20
AH20
AH19
P19
P16
AH15
P15
AH14

+2.5VS

1 2

C306

0.1U_0402_16V4Z

+2.5VS

W=40 mils

+1.5VS_3GPLL
+2.5VS

+2.5VS_CRTDAC

+1.5VS_DPLLA
+1.5VS_DPLLB
+1.5VS_HPLL

+2.5VS

+1.5VS_MPLL
+3VS_TVBG

+3VS_TVDACA
+3VS_TVDACA
+3VS_TVDACA

+1.5VS

+1.5VS_TVDAC

1

2

C302

0.1 U _040 2_16V4Z

+1.5VS

1

C299

2

+1.5VS_PCIE

1

1

+

C108

C107

2

2

220U _ D2_4VM

1

C72

2

+3VS

1

2

C298

10U_ 1206_6.3V6M

0.1 U _040 2_16V4Z

R57

0_0805_5%

1

C105

2

10U_ 1206_6.3V6M

10U_ 1206_6.3V6M

L4 FBM-11-160808-601-T_0603

1 2

1

C71

2

220 0P_0402_50V7K

0.1 U _040 2_16V4Z

1

1

C711

2

2

C63

4.7U_0 8 05_10V4Z

12

+1.5VS

+2.5VS

CRTDAC: Route caps within
250mil of Alviso. Route FB
within 3" of Calistoga

1

C102

2

+2.5VS

1

C304

2

0.1U _ 0402_16V4Z

close pin G41

0.0 1 U_04 02_25V4Z

close pin A38

+3VS+3VS_TVBG

R205

12

0_0805_5%

1

2

220 0P_0402_50V7K

C49

0.1 U _040 2_16V4Z

+2.5VS

1

C99

2

0.1 U _040 2_16V4Z

+1.5VS_DPLLA +1.5VS_DPLLB

CHB1608U301_0603

330U_V _2. 5VK_R9

0.1 U _040 2_16V4Z
C300

1

C82

1

+

UMA@

2

2

1

1

C54

C55

2

2

2200P_0402_50V7K

PCI-E/MEM/PSB PLL decoupling

R56
0_0603_5%

1

C97

C98

2

0.1 U _040 2_16V4Z

10U_ 1206_6.3V6M

+1.5VS_MPLL

45mA Max. 45mA Max.

1

C13

2

0.1 U _040 2_16V4Z

1

2

R16
0_0603_5%

1

C8

2

10U_12 06_6.3V6M

L16

12

1

2

0.1 U _040 2_16V4Z

+1.5VS+1.5VS_3GPLL

0.1 U _040 2_16V4Z

C101

1

2

1

C297

2

220 0P_0402_50V7K

+1.5VS_TVDAC +1.5VS

1

C58

2

0.1 U _040 2_16V4Z

12

1

C104

2

0.1 U _040 2_16V4Z

@

C67

1

2

0.1 U _040 2_16V4Z

1

C37

2

2200P_0402_50V7K

+1.5VS_HPLL

12

1

C14

2

CHB1608U301_0603

330 U_V_ 2.5VK_R9

C100

1

+

UMA@

2

1

C45

2

2200P_0402_50V7K

R213
0_0603_5%

R17
0_0603_5%

1

C9

2

0.1 U _040 2_16V4Z

C46

10U_ 1206_6.3V6M

L5

0_0603_5%

0.1 U_0 402_ 16V4Z

12

C301

@

R206

0.1 U _040 2_16V4Z

12

+1.5VS+1.5VS

+3VS+3VS_TVDACA+3VS_TVDACA+3VS_TVDACA

12

1

2

12

+1.5VS+1.5VS

D13

R221

R220

+1.5VS

@

12

+2.5VS

21

D12

@

12

+3VS

1

C24

2

4.7 U _080 5_10V4Z

1

C94

2

1

0.2 2 U_0603_10V7K

2

+VCCP

1

+

C91

220U_D2_4VM

2

1

C50

2

2.2 U _080 5_16V4Z

MCH_A6

1

C296

2

0.47U_ 0 603_16V4Z

MCH_D2

C12

MCH_AB1

1

C10

0.2 2 U_0603_10V7K

2

0.4 7 U_06 03_16V4Z

+1.5VS

U14H

AC14

VTT0

AB14

VTT1

W14

VTT2

V14

VTT3

T14

VTT4

R14

VTT5

P14

VTT6

N14

VTT7

M14

VTT8

L14

VTT9

AD13

VTT10

AC13

VTT11

AB13

VTT12

AA13

VTT13

Y13

VTT14

W13

VTT15

V13

VTT16

U13

VTT17

T13

VTT18

R13

VTT19

N13

VTT20

M13

VTT21

L13

VTT22

AB12

VTT23

AA12

VTT24

Y12

VTT25

W12

VTT26

V12

VTT27

U12

VTT28

T12

VTT29

R12

VTT30

P12

VTT31

N12

VTT32

M12

VTT33

L12

VTT34

R11

VTT35

P11

VTT36

N11

VTT37

M11

VTT38

R10

VTT39

P10

VTT40

N10

VTT41

M10

VTT42

P9

VTT43

N9

VTT44

M9

VTT45

R8

VTT46

P8

VTT47

N8

VTT48

M8

VTT49

P7

VTT50

N7

VTT51

M7

VTT52

R6

VTT53

P6

VTT54

M6

VTT55

A6

VTT56

R5

VTT57

P5

VTT58

N5

VTT59

M5

VTT60

P4

VTT61

N4

VTT62

M4

VTT63

R3

VTT64

P3

VTT65

N3

VTT66

M3

VTT67

R2

VTT68

P2

VTT69

M2

VTT70

D2

VTT71

AB1

VTT72

R1

VTT73

P1

VTT74

N1

VTT75

M1

VTT76

AG14

VCCAUX32

AF14

VCCAUX33

AE14

VCCAUX34

Y14

VCCAUX35

AF13

VCCAUX36

AE13

VCCAUX37

AF12

VCCAUX38

AE12

VCCAUX39

AD12

VCCAUX40

CALISTOGA_FCBGA1466~D

UMA_GM@

P O W E R

VCC_SYNC

VCCTX_LVDS0
VCCTX_LVDS1
VCCTX_LVDS2

VCCA_3GPLL

VCCA_3GBG
VSSA_3GBG

VCCA_CRTDAC0
VCCA_CRTDAC1
VSSA_CRTDAC2

VCCA_DPLLA
VCCA_DPLLB

VCCA_HPLL

VCCA_LVDS

VSSA_LVDS

VCCA_MPLL

VCCA_TVBG

VSSA_TVBG

VCCA_TVDACA0
VCCA_TVDACA1
VCCA_TVDACB0
VCCA_TVDACB1
VCCA_TVDACC0
VCCA_TVDACC1

VCCD_HMPLL0
VCCD_HMPLL1

VCCD_LVDS0
VCCD_LVDS1
VCCD_LVDS2

VCCD_TVDAC

VCCDQ_TVDAC

VCCAUX0
VCCAUX1
VCCAUX2
VCCAUX3
VCCAUX4
VCCAUX5
VCCAUX6
VCCAUX7
VCCAUX8

VCCAUX9
VCCAUX10
VCCAUX11
VCCAUX12
VCCAUX13
VCCAUX14
VCCAUX15
VCCAUX16
VCCAUX17
VCCAUX18
VCCAUX19
VCCAUX20
VCCAUX21
VCCAUX22
VCCAUX23
VCCAUX24
VCCAUX25
VCCAUX26
VCCAUX27
VCCAUX28
VCCAUX29
VCCAUX30
VCCAUX31

D D

CH751H-40_SC76

10_0402_5%@

CH751H-40_SC76

10_0402_5% @

C C

B B

A A

Security Classification Compal Secret Data

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

PDF created with pdfFactory Pro trial version www.pdffactory.com

2005/10/06 2006/10/06

3

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

HGT30/31 LA-3061

Date: Sheet of

2

星期四二月

Calistoga (4/6)

23, 2006

10 47,

1

0.1

5

4

3

2

1

Strap Pin Table

CFG[3:17] have internal pull up

+VCCP

D D

1

C69

2

0.22U_060 3_10V7K

1

C48

2

10U_1206_6.3V6M

C C

B B

1

1

C25

C61

2

2

0.22U_060 3_10V7K

C95

10U_ 1206_6.3V 6M

220U_D2_4VM

C18

C79

220U_D2_4VM@

0.22U_060 3_10V7K

1

1

C31

2

2

1U_0 603_10V4Z

1

+

2

1

+

2

+VCCP

U14F

AD27

VCC_NCTF0

AC27

VCC_NCTF1

AB27

VCC_NCTF2

AA27

VCC_NCTF3

Y27

VCC_NCTF4

W27

VCC_NCTF5

V27

VCC_NCTF6

U27

VCC_NCTF7

T27

VCC_NCTF8

R27

VCC_NCTF9

AD26

VCC_NCTF10

AC26

VCC_NCTF11

AB26

VCC_NCTF12

AA26

VCC_NCTF13

Y26

VCC_NCTF14

W26

VCC_NCTF15

V26

VCC_NCTF16

U26

VCC_NCTF17

T26

VCC_NCTF18

R26

VCC_NCTF19

AD25

VCC_NCTF20

AC25

VCC_NCTF21

AB25

VCC_NCTF22

AA25

VCC_NCTF23

Y25

VCC_NCTF24

W25

VCC_NCTF25

V25

VCC_NCTF26

U25

VCC_NCTF27

T25

VCC_NCTF28

R25

VCC_NCTF29

AD24

VCC_NCTF30

AC24

VCC_NCTF31

AB24

VCC_NCTF32

AA24

VCC_NCTF33

Y24

VCC_NCTF34

W24

VCC_NCTF35

V24

VCC_NCTF36

U24

VCC_NCTF37

T24

VCC_NCTF38

R24

VCC_NCTF39

AD23

VCC_NCTF40

V23

VCC_NCTF41

U23

VCC_NCTF42

T23

VCC_NCTF43

R23

VCC_NCTF44

AD22

VCC_NCTF45

V22

VCC_NCTF46

U22

VCC_NCTF47

T22

VCC_NCTF48

R22

VCC_NCTF49

AD21

VCC_NCTF50

V21

VCC_NCTF51

U21

VCC_NCTF52

T21

VCC_NCTF53

R21

VCC_NCTF54

AD20

VCC_NCTF55

V20

VCC_NCTF56

U20

VCC_NCTF57

T20

VCC_NCTF58

R20

VCC_NCTF59

AD19

VCC_NCTF60

V19

VCC_NCTF61

U19

VCC_NCTF62

T19

VCC_NCTF63

AD18

VCC_NCTF64

AC18

VCC_NCTF65

AB18

VCC_NCTF66

AA18

VCC_NCTF67

Y18

VCC_NCTF68

W18

VCC_NCTF69

V18

VCC_NCTF70

U18

VCC_NCTF71

T18

VCC_NCTF72

M19

VCC100

L19

VCC101

N18

VCC102

M18

VCC103

L18

VCC104

P17

VCC105

N17

VCC106

M17

VCC107

N16

VCC108

M16

VCC109

L16

VCC110

CALISTOGA_FCBGA1466~D

UMA_GM@

VCCAUX_NCTF0
VCCAUX_NCTF1
VCCAUX_NCTF2
VCCAUX_NCTF3
VCCAUX_NCTF4
VCCAUX_NCTF5
VCCAUX_NCTF6
VCCAUX_NCTF7
VCCAUX_NCTF8

VCCAUX_NCTF9
VCCAUX_NCTF10
VCCAUX_NCTF11
VCCAUX_NCTF12
VCCAUX_NCTF13
VCCAUX_NCTF14
VCCAUX_NCTF15
VCCAUX_NCTF16
VCCAUX_NCTF17
VCCAUX_NCTF18
VCCAUX_NCTF19
VCCAUX_NCTF20
VCCAUX_NCTF21
VCCAUX_NCTF22
VCCAUX_NCTF23
VCCAUX_NCTF24
VCCAUX_NCTF25
VCCAUX_NCTF26
VCCAUX_NCTF27
VCCAUX_NCTF28
VCCAUX_NCTF29
VCCAUX_NCTF30
VCCAUX_NCTF31
VCCAUX_NCTF32
VCCAUX_NCTF33
VCCAUX_NCTF34
VCCAUX_NCTF35
VCCAUX_NCTF36

P O W E R

VCCAUX_NCTF37
VCCAUX_NCTF38
VCCAUX_NCTF39
VCCAUX_NCTF40
VCCAUX_NCTF41
VCCAUX_NCTF42
VCCAUX_NCTF43
VCCAUX_NCTF44
VCCAUX_NCTF45
VCCAUX_NCTF46
VCCAUX_NCTF47
VCCAUX_NCTF48
VCCAUX_NCTF49
VCCAUX_NCTF50
VCCAUX_NCTF51
VCCAUX_NCTF52
VCCAUX_NCTF53
VCCAUX_NCTF54
VCCAUX_NCTF55
VCCAUX_NCTF56
VCCAUX_NCTF57

VSS_NCTF0
VSS_NCTF1
VSS_NCTF2
VSS_NCTF3
VSS_NCTF4
VSS_NCTF5
VSS_NCTF6
VSS_NCTF7
VSS_NCTF8

VSS_NCTF9
VSS_NCTF10
VSS_NCTF11
VSS_NCTF12

VCC_SM100

VCC_SM101

VCC_SM102

VCC_SM103

VCC_SM104

VCC_SM105

VCC_SM106

VCC_SM107

AG27
AF27
AG26
AF26
AG25
AF25
AG24
AF24
AG23
AF23
AG22
AF22
AG21
AF21
AG20
AF20
AG19
AF19
R19
AG18
AF18
R18
AG17
AF17
AE17
AD17
AB17
AA17
W17
V17
T17
R17
AG16
AF16
AE16
AD16
AC16
AB16
AA16
Y16
W16
V16
U16
T16
R16
AG15
AF15
AE15
AD15
AC15
AB15
AA15
Y15
W15
V15
U15
T15
R15

AE27
AE26
AE25
AE24
AE23
AE22
AE21
AE20
AE19
AE18
AC17
Y17
U17

AR6
AP6
AN6
AL6
AK6
AJ6
AV1
AJ1

+1.5VS

+1.8V

1

1

C17

C15

2

2

0.47U_0603_16V4Z

0.47U_0603_16V4Z

Place near pin AV1 & AJ1

A A

+VCCP

U14G

AA33

VCC0

W33

VCC1

P33

VCC2

N33

VCC3

L33

VCC4

J33

VCC5

AA32

VCC6

Y32

VCC7

W32

VCC8

V32

VCC9

P32

VCC10

N32

VCC11

M32

VCC12

L32

VCC13

J32

VCC14

AA31

VCC15

W31

VCC16

V31

VCC17

T31

VCC18

R31

VCC19

P31

VCC20

N31

VCC21

M31

VCC22

AA30

VCC23

Y30

VCC24

W30

VCC25

V30

VCC26

U30

VCC27

T30

VCC28

R30

VCC29

P30

VCC30

N30

VCC31

M30

VCC32

L30

VCC33

AA29

VCC34

Y29

VCC35

W29

VCC36

V29

VCC37

U29

VCC38

R29

VCC39

P29

VCC40

M29

VCC41

L29

VCC42

AB28

VCC43

AA28

VCC44

Y28

VCC45

V28

VCC46

U28

VCC47

T28

VCC48

R28

VCC49

P28

VCC50

N28

VCC51

M28

VCC52

L28

VCC53

P27

VCC54

N27

VCC55

M27

VCC56

L27

VCC57

P26

VCC58

N26

VCC59

L26

VCC60

N25

VCC61

M25

VCC62

L25

VCC63

P24

VCC64

N24

VCC65

M24

VCC66

AB23

VCC67

AA23

VCC68

Y23

VCC69

P23

VCC70

N23

VCC71

M23

VCC72

L23

VCC73

AC22

VCC74

AB22

VCC75

Y22

VCC76

W22

VCC77

P22

VCC78

N22

VCC79

M22

VCC80

L22

VCC81

AC21

VCC82

AA21

VCC83

W21

VCC84

N21

VCC85

M21

VCC86

L21

VCC87

AC20

VCC88

AB20

VCC89

Y20

VCC90

W20

VCC91

P20

VCC92

N20

VCC93

M20

VCC94

L20

VCC95

AB19

VCC96

AA19

VCC97

Y19

VCC98

N19

VCC99

CALISTOGA_FCBGA1466~D

UMA_GM@

P O W E R

VCC_SM0
VCC_SM1
VCC_SM2
VCC_SM3
VCC_SM4
VCC_SM5
VCC_SM6
VCC_SM7
VCC_SM8

VCC_SM9
VCC_SM10
VCC_SM11
VCC_SM12
VCC_SM13
VCC_SM14
VCC_SM15
VCC_SM16
VCC_SM17
VCC_SM18
VCC_SM19
VCC_SM20
VCC_SM21
VCC_SM22
VCC_SM23
VCC_SM24
VCC_SM25
VCC_SM26
VCC_SM27
VCC_SM28
VCC_SM29
VCC_SM30
VCC_SM31
VCC_SM32
VCC_SM33
VCC_SM34
VCC_SM35
VCC_SM36
VCC_SM37
VCC_SM38
VCC_SM39
VCC_SM40
VCC_SM41
VCC_SM42
VCC_SM43
VCC_SM44
VCC_SM45
VCC_SM46
VCC_SM47
VCC_SM48
VCC_SM49
VCC_SM50
VCC_SM51
VCC_SM52
VCC_SM53
VCC_SM54
VCC_SM55
VCC_SM56
VCC_SM57
VCC_SM58
VCC_SM59
VCC_SM60
VCC_SM61
VCC_SM62
VCC_SM63
VCC_SM64
VCC_SM65
VCC_SM66
VCC_SM67
VCC_SM68
VCC_SM69
VCC_SM70
VCC_SM71
VCC_SM72
VCC_SM73
VCC_SM74
VCC_SM75
VCC_SM76
VCC_SM77
VCC_SM78
VCC_SM79
VCC_SM80
VCC_SM81
VCC_SM82
VCC_SM83
VCC_SM84
VCC_SM85
VCC_SM86
VCC_SM87
VCC_SM88
VCC_SM89
VCC_SM90
VCC_SM91
VCC_SM92
VCC_SM93
VCC_SM94
VCC_SM95
VCC_SM96
VCC_SM97
VCC_SM98
VCC_SM99

AU41
AT41
AM41
AU40
BA34
AY34
AW34
AV34
AU34
AT34
AR34
BA30
AY30
AW30
AV30
AU30
AT30
AR30
AP30
AN30
AM30
AM29
AL29
AK29
AJ29
AH29
AJ28
AH28
AJ27
AH27
BA26
AY26
AW26
AV26
AU26
AT26
AR26
AJ26
AH26
AJ25
AH25
AJ24
AH24
BA23
AJ23
BA22
AY22
AW22
AV22
AU22
AT22
AR22
AP22
AK22
AJ22
AK21
AK20
BA19
AY19
AW19
AV19
AU19
AT19
AR19
AP19
AK19
AJ19
AJ18
AJ17
AH17
AJ16
AH16
BA15
AY15
AW15
AV15
AU15
AT15
AR15
AJ15
AJ14
AJ13
AH13
AK12
AJ12
AH12
AG12
AK11
BA8
AY8
AW8
AV8
AT8
AR8
AP8
BA6
AY6
AW6
AV6
AT6

+1.8V

MCH_AT41
MCH_AM41

1

1

C106

C103

2

2

0.47U_0603_16V4Z

0.47U_0603_16V4Z

Place near pin AT41 & AM41

1

1

C21

C20

2

C27

2

0.1U_0402_16V4Z

1

2

0.47U_0603_16V4Z

Place near pin BA23

1

1

C78

C44

C93

2

2

10U_1206_6.3V6M

10U_1206_6.3V6M

1

2

0.47U_060 3_16V4Z

Place near pin BA15

CFG[2:0]

PSB 4X CLK Enable1 = Calistoga

CFG[13:12]

0.1U_0402_16V4Z

CFG10 CFG18

SDVO_CTRLDATA

1

1

C86

C47

2

0.1U_0402_16V4Z

2

0.1U_ 0402 _16V 4Z

(PCIE/SDVO select)

1

+

C59

2

220U_D2_4M_R45@

CFG[19:18] have internal pull down

011 = 667MT/s FSB
001 = 533MT/s FSB

CFG5

CFG7

CFG9

CFG6

CFG16

CFG19

0 = DMI x 2
1 = DMI x 4

0 = Reserved
1 = Mobile Yonah CPU

0 = Lane Reversal Enable
1 = Normal Operation

0 = Reserved

00 = Reserved
01 = XOR Mode Enabled
10 = All Z Mode Enabled
11 = Normal Operation

0 = Dynamic ODT Disabled
1 = Dynamic ODT Enabled(Default)

10 = 1.05V
01 = 1.5V

0 = Normal Operation
1 = DMI Lane Reversal Enable

0 = No SDVO Device Present

(Default)

1 = SDVO Device Present

CFG20

0 = Only PCIE or SDVO is
operational.
1 = PCIE/SDVO are operating
simu.

R32 2.2K_0402_5% @

CFG5<7>

R40 2.2K_0402_5%@

CFG7<7>

R37 2.2K_0402_5%@

CFG9<7>
CFG11<7>
CFG12<7>
CFG13<7>
CFG16<7>

CFG18<7>
CFG19<7>
CFG20<7>

R35 2.2K_0402_5%@
R34 2.2K_0402_5%@
R38 2.2K_0402_5%@
R33 2.2K_0402_5% @

R48 1K_0402_5%@
R50 1K_0402_5% @
R51 1K_0402_5% @

(Default)

*

*

(Default)

*

*

1 2
1 2
1 2
1 2
1 2
1 2
1 2

1 2
1 2
1 2

(Default)

*

(Default)

*

(Default)

(Default)

*

*

(Default)

*

*

+3VS

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

PDF created with pdfFactory Pro trial version www.pdffactory.com

2005/10/06 2006/10/06

3

Compal Secret Data

Deciphered Date

2

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

Calistoga (5/6)

HGT30/31 LA-3061

星期四二月

23, 2006

1

11 47,

0.1

5

4

3

2

1

U14I

AC41

VSS0

AA41

VSS1

W41

VSS2

T41

VSS3

P41

VSS4

M41

D D

C C

B B

A A

VSS5

J41

VSS6

F41

VSS7

AV40

VSS8

AP40

VSS9

AN40

VSS10

AK40

VSS11

AJ40

VSS12

AH40

VSS13

AG40

VSS14

AF40

VSS15

AE40

VSS16

B40

VSS17

AY39

VSS18

AW39

VSS19

AV39

VSS20

AR39

VSS21

AN39

VSS22

AJ39

VSS23

AC39

VSS24

AB39

VSS25

AA39

VSS26

Y39

VSS27

W39

VSS28

V39

VSS29

T39

VSS30

R39

VSS31

P39

VSS32

N39

VSS33

M39

VSS34

L39

VSS35

J39

VSS36

H39

VSS37

G39

VSS38

F39

VSS39

D39

VSS40

AT38

VSS41

AM38

VSS42

AH38

VSS43

AG38

VSS44

AF38

VSS45

AE38

VSS46

C38

VSS47

AK37

VSS48

AH37

VSS49

AB37

VSS50

AA37

VSS51

Y37

VSS52

W37

VSS53

V37

VSS54

T37

VSS55

R37

VSS56

P37

VSS57

N37

VSS58

M37

VSS59

L37

VSS60

J37

VSS61

H37

VSS62

G37

VSS63

F37

VSS64

D37

VSS65

AY36

VSS66

AW36

VSS67

AN36

VSS68

AH36

VSS69

AG36

VSS70

AF36

VSS71

AE36

VSS72

AC36

VSS73

C36

VSS74

B36

VSS75

BA35

VSS76

AV35

VSS77

AR35

VSS78

AH35

VSS79

AB35

VSS80

AA35

VSS81

Y35

VSS82

W35

VSS83

V35

VSS84

T35

VSS85

R35

VSS86

P35

VSS87

N35

VSS88

M35

VSS89

L35

VSS90

J35

VSS91

H35

VSS92

G35

VSS93

F35

VSS94

D35

VSS95

AN34

VSS96

AK34

VSS97

AG34

VSS98

AF34

VSS99

CALISTOGA_FCBGA1466~D

UMA_GM@

P O W E R

VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS140
VSS141
VSS142
VSS143
VSS144
VSS145
VSS146
VSS147
VSS148
VSS149
VSS150
VSS151
VSS152
VSS153
VSS154
VSS155
VSS156
VSS157
VSS158
VSS159
VSS160
VSS161
VSS162
VSS163
VSS164
VSS165
VSS166
VSS167
VSS168
VSS169
VSS170
VSS171
VSS172
VSS173
VSS174
VSS175
VSS176
VSS177
VSS178
VSS179
VSS180
VSS181
VSS182
VSS183
VSS184
VSS185
VSS186
VSS187
VSS188
VSS189
VSS190
VSS191
VSS192
VSS193
VSS194
VSS195
VSS196
VSS197
VSS198
VSS199

AE34
AC34
C34
AW33
AV33
AR33
AE33
AB33
Y33
V33
T33
R33
M33
H33
G33
F33
D33
B33
AH32
AG32
AF32
AE32
AC32
AB32
G32
B32
AY31
AV31
AN31
AJ31
AG31
AB31
Y31
AB30
E30
AT29
AN29
AB29
T29
N29
K29
G29
E29
C29
B29
A29
BA28
AW28
AU28
AP28
AM28
AD28
AC28
W28
J28
E28
AP27
AM27
AK27
J27
G27
F27
C27
B27
AN26
M26
K26
F26
D26
AK25
P25
K25
H25
E25
D25
A25
BA24
AU24
AL24
AW23
AT23
AN23
AM23
AH23
AC23
W23
K23
J23
F23
C23
AA22
K22
G22
F22
E22
D22
A22
BA21
AV21
AR21

U14J

AN21

VSS200

AL21

VSS201

AB21

VSS202

Y21

VSS203

P21

VSS204

K21

VSS205

J21

VSS206

H21

VSS207

C21

VSS208

AW20

VSS209

AR20

VSS210

AM20

VSS211

AA20

VSS212

K20

VSS213

B20

VSS214

A20

VSS215

AN19

VSS216

AC19

VSS217

W19

VSS218

K19

VSS219

G19

VSS220

C19

VSS221

AH18

VSS222

P18

VSS223

H18

VSS224

D18

VSS225

A18

VSS226

AY17

VSS227

AR17

VSS228

AP17

VSS229

AM17

VSS230

AK17

VSS231

AV16

VSS232

AN16

VSS233

AL16

VSS234

J16

VSS235

F16

VSS236

C16

VSS237

AN15

VSS238

AM15

VSS239

AK15

VSS240

N15

VSS241

M15

VSS242

L15

VSS243

B15

VSS244

A15

VSS245

BA14

VSS246

AT14

VSS247

AK14

VSS248

AD14

VSS249

AA14

VSS250

U14

VSS251

K14

VSS252

H14

VSS253

E14

VSS254

AV13

VSS255

AR13

VSS256

AN13

VSS257

AM13

VSS258

AL13

VSS259

AG13

VSS260

P13

VSS261

F13

VSS262

D13

VSS265

B13

VSS264

AY12

VSS263

AC12

VSS266

K12

VSS267

H12

VSS268

E12

VSS269

AD11

VSS270

AA11

VSS271

Y11

VSS272

J11

VSS273

D11

VSS274

B11

VSS275

AV10

VSS276

AP10

VSS277

AL10

VSS278

AJ10

VSS279

CALISTOGA_FCBGA1466~D

UMA_GM@

P O W E R

VSS280
VSS281
VSS282
VSS283
VSS284
VSS285
VSS286
VSS287
VSS288
VSS289
VSS290
VSS292
VSS291
VSS293
VSS294
VSS295
VSS296
VSS297
VSS298
VSS299
VSS300
VSS301
VSS302
VSS303
VSS304
VSS305
VSS306
VSS307
VSS308
VSS309
VSS310
VSS311
VSS312
VSS313
VSS314
VSS315
VSS316
VSS317
VSS318
VSS319
VSS320
VSS321
VSS322
VSS323
VSS324
VSS325
VSS326
VSS327
VSS328
VSS329
VSS330
VSS331
VSS332
VSS333
VSS334
VSS335
VSS336
VSS337
VSS338
VSS339
VSS340
VSS341
VSS342
VSS343
VSS344
VSS345
VSS346
VSS347
VSS348
VSS349
VSS350
VSS351
VSS352
VSS353
VSS354
VSS355
VSS356
VSS357
VSS358
VSS359
VSS360

AG10
AC10
W10
U10
BA9
AW9
AR9
AH9
AB9
Y9
R9
G9
E9
A9
AG8
AD8
AA8
U8
K8
C8
BA7
AV7
AP7
AL7
AJ7
AH7
AF7
AC7
R7
G7
D7
AG6
AD6
AB6
Y6
U6
N6
K6
H6
B6
AV5
AF5
AD5
AY4
AR4
AP4
AL4
AJ4
Y4
U4
R4
J4
F4
C4
AY3
AW3
AV3
AL3
AH3
AG3
AF3
AD3
AC3
AA3
G3
AT2
AR2
AP2
AK2
AJ2
AD2
AB2
Y2
U2
T2
N2
J2
H2
F2
C2
AL1

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

PDF created with pdfFactory Pro trial version www.pdffactory.com

2005/10/06 2006/10/06

3

Compal Secret Data

Deciphered Date

2

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

Calistoga (6/6)

HGT30/31 LA-3061

星期四二月

23, 2006

1

12 47,

0.1

5

DDR_A_DQS#[0..7]<8>

DDR_A_D[0..63]<8>

DDR_A_DM[0..7]<8>
DDR_A_DQS[0..7]<8>
DDR_A_MA[0..13]<8>

D D

Layout Note:
Place near JP41

+1.8V

2.2U_0805_16V4Z

2.2U_ 0805 _16V 4Z
C89

1

1

2

2

C C

B B

A A

Layout Note:
Place one cap close to every 2 pullup
resistors terminated to +0.9VS

+0.9VS

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

2

2

C74

C66

DDR_A_WE#
DDR_A_CAS#
DDR_CS1_DIMMA#
M_ODT1

DDR_A_BS#0
DDR_A_MA10

DDR_A_MA1
DDR_A_MA3
DDR_A_MA5
DDR_A_MA8

DDR_A_MA9
DDR_A_MA12
DDR_A_BS#2
DDR_CKE0_DIMMA

1 8
2 7
3 6
4 5

56_0804_8P4R_5%

56_0402_5%

R39

1 2

R43

1 2

4 5
3 6
2 7
1 8

56_0804_8P4R_5%

4 5
3 6
2 7
1 8

56_0804_8P4R_5%

5

2.2U_0805_16V4Z

C87

0.1U_0402_16V4Z

1

2

C60

RP1

56_0402_5%

RP7

RP10

C28

1

2

0.1U_0402_16V4Z

1

2

+0.9VS

2.2U_ 0805 _16V 4Z
C92

1

2

0.1U_ 0402 _16V 4Z

1

2

C42

C51

RP2

56_0804_8P4R_5%

RP6

56_0804_8P4R_5%

RP9

56_0804_8P4R_5%

2.2U_0805_16V4Z
C30

1

2

0.1U_0402_16V4Z

1

2

C34

DDR_A_RAS#

18

DDR_CS0_DIMMA#

27

M_ODT0

36

DDR_A_MA13

45

DDR_A_BS#1

45

DDR_A_MA0

36

DDR_A_MA2

27

DDR_A_MA4

18

DDR_A_MA6

45

DDR_A_MA7

36

DDR_A_MA11

27

DDR_CKE1_DIMMA

18

0.1U_0402_16V4Z

0.1U_0402_16V4Z

C85

1

1

2

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

2

2

C40

C53

0.1U_ 0402 _16V 4Z

C57

1

2

C64

4

+DDR_MCH_REF1<14>

0.1U_ 0402 _16V 4Z

C43

1

1

2

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

2

2

C39

C77

Layout Note:
Place these resistor
closely JP41,all
trace length Max=1.5"

4

DDR_CKE0_DIMMA<7>

DDR_CS1_DIMMA#<7>

Issued Date

3

+1.8V

JP3

1

VREF

3

DDR_A_D4
DDR_A_D1

DDR_A_DQS#0
DDR_A_DQS0

DDR_A_D2
DDR_A_D3

DDR_A_D8
DDR_A_D14

DDR_A_DQS#1
DDR_A_DQS1

DDR_A_D9 DDR_A_D11
DDR_A_D15 DDR_A_D10

DDR_A_D16
DDR_A_D17

DDR_A_DQS#2
DDR_A_DQS2

DDR_A_D18
DDR_A_D19

EC_P80_DATA<14,33>

EC_P80_CLK<14,33>

DDR_A_BS#2<8>

DDR_A_BS#0<8>

DDR_A_WE#<8>

DDR_A_CAS#<8>

M_ODT1<7>

CLK_SMBDATA<14,15>

CLK_SMBCLK<14,15>

3

DDR_A_DM3

DDR_A_D26
DDR_A_D27

DDR_CKE0_DIMMA

DDR_A_BS#2
DDR_A_MA12

DDR_A_MA9 DDR_A_MA7
DDR_A_MA8

DDR_A_MA5
DDR_A_MA3
DDR_A_MA1

DDR_A_MA10
DDR_A_BS#0
DDR_A_WE#

DDR_A_CAS#
DDR_CS1_DIMMA#

M_ODT1
DDR_A_D37

DDR_A_D36
DDR_A_DQS#4

DDR_A_DQS4
DDR_A_D35

DDR_A_D32
DDR_A_D40

DDR_A_D44
DDR_A_DM5
DDR_A_D41

DDR_A_D46
DDR_A_D49

DDR_A_D48

DDR_A_DQS#6
DDR_A_DQS6

DDR_A_D50
DDR_A_D61 DDR_A_D57

DDR_A_D60
DDR_A_DM7
DDR_A_D59

DDR_A_D58
CLK_SMBDATA

CLK_SMBCLK

+3VS

1

C7

0.1U_0402_16V4Z

2005/10/06 2006/10/06

2

Compal Secret Data

VSS

5

DQ0

7

DQ1

9

VSS

11

DQS0#

13

DQS0

15

VSS

17

DQ2

19

DQ3

21

VSS

23

DQ8

25

DQ9

27

VSS

29

DQS1#

31

DQS1

33

VSS

35

DQ10

37

DQ11

39

VSS

41

VSS

43

DQ16

45

DQ17

47

VSS

49

DQS2#

51

DQS2

53

VSS

55

DQ18

57

DQ19

59

VSS

61

DQ24

63

DQ25

65

VSS

67

DM3

69

NC

71

VSS

73

DQ26

75

DQ27

77

VSS

79

CKE0

81

VDD

83

NC

85

BA2

87

VDD

89

A12

91

A9

93

A8

95

VDD

97

A5

99

A3

101

A1

103

VDD

105

A10/AP

107

BA0

109

WE#

111

VDD

113

CAS#

115

NC/S1#

117

VDD

119

NC/ODT1

121

VSS

123

DQ32

125

DQ33

127

VSS

129

DQS4#

131

DQS4

133

VSS

135

DQ34

137

DQ35

139

VSS

141

DQ40

143

DQ41

145

VSS

147

DM5

149

VSS

151

DQ42

153

DQ43

155

VSS

157

DQ48

159

DQ49

161

VSS

163

NC,TEST

165

VSS

167

DQS6#

169

DQS6

171

VSS

173

DQ50

175

DQ51

177

VSS

179

DQ56

181

DQ57

183

VSS

185

DM7

187

VSS

189

DQ58

191

DQ59

193

VSS

195

SDA

197

SCL

199

VDDSPD

FOX_ASOA426-M2RN-7F

ME@

SO-DIMM A

Deciphered Date

Layout Note:
+DDR_MCH_REF
trace width and
spacing is 20/20.

+1.8V

12

R86

+DDR_MCH_REF1

1

C149

2

0.1U_0402_16V4Z

C83

0.1U_0402_16V4Z

0.1U_ 0402 _16V 4Z

1

1

2

2

C70

C33

100_0402_1%

12

R87

100_0402_1%

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

NC/CKE1

NC/A15
NC/A14

NC/A13

Top side

VSS
DQ4
DQ5
VSS
DM0
VSS
DQ6
DQ7

VSS
DQ12
DQ13

VSS

DM1

VSS

CK0

CK0#

VSS
DQ14
DQ15

VSS

VSS
DQ20
DQ21

VSS

DM2

VSS
DQ22
DQ23

VSS
DQ28
DQ29

VSS

DQS3#

DQS3

VSS
DQ30
DQ31

VSS

VDD

VDD

VDD

VDD
RAS#

VDD
ODT0

VDD

VSS
DQ36
DQ37

VSS

DM4

VSS
DQ38
DQ39

VSS
DQ44
DQ45

VSS

DQS5#

DQS5

VSS
DQ46
DQ47

VSS
DQ52
DQ53

VSS

CK1

CK1#

VSS

DM6

VSS
DQ54
DQ55

VSS
DQ60
DQ61

VSS

DQS7#

DQS7

VSS
DQ62
DQ63

VSS

2

+1.8V

+DDR_MCH_REF1

2

DDR_A_D6

4

DDR_A_D0

6
8

DDR_A_DM0

10
12

DDR_A_D5

14

DDR_A_D7

16
18

DDR_A_D13

20

DDR_A_D12

22
24

DDR_A_DM1

26
28

M_CLK_DDR0

30

M_CLK_DDR#0

32
34
36
38
40

42

DDR_A_D20

44

DDR_A_D21

46
48
50

NC

A11

A7
A6

A4
A2

A0
BA1
S0#

NC

SA0
SA1

2

52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200

DDR_A_DM2
DDR_A_D23

DDR_A_D22
DDR_A_D28DDR_A_D29

DDR_A_D25DDR_A_D24
DDR_A_DQS#3

DDR_A_DQS3
DDR_A_D31

DDR_A_D30
DDR_CKE1_DIMMA

DDR_A_MA11
DDR_A_MA6
DDR_A_MA4

DDR_A_MA2
DDR_A_MA0

DDR_A_BS#1
DDR_A_RAS#
DDR_CS0_DIMMA#

M_ODT0
DDR_A_MA13

DDR_A_D39
DDR_A_D38

DDR_A_DM4
DDR_A_D34

DDR_A_D33
DDR_A_D45

DDR_A_D43
DDR_A_DQS#5

DDR_A_DQS5
DDR_A_D47

DDR_A_D42
DDR_A_D52

DDR_A_D53
M_CLK_DDR1

M_CLK_DDR#1
DDR_A_DM6
DDR_A_D51DDR_A_D54

DDR_A_D55

DDR_A_D56
DDR_A_DQS#7

DDR_A_DQS7
DDR_A_D62

DDR_A_D63

12

R15

R13

10K _0402_5%

10K_0402_5%

12

2.2U_0805_16V4Z
C145

1

2

M_CLK_DDR0<7>
M_CLK_DDR#0<7>

PM_EXTTS#0<7,14>

DDR_CKE1_DIMMA<7>

DDR_A_BS#1<8>
DDR_A_RAS#<8>
DDR_CS0_DIMMA#<7>

M_ODT0 <7>

M_CLK_DDR1<7>
M_CLK_DDR#1<7>

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

DDRII-SODIMM SLOT1

HGT30/31 LA-3061

星期四二月

23, 2006

1

C134

1

2

+DDR_MCH_REF1<14>

1

13 47,

0.1

0.1U_0402_16V4Z

PDF created with pdfFactory Pro trial version www.pdffactory.com

5

DDR_B_DQS#[0..7]<8>

DDR_B_D[0..63]<8>

DDR_B_DM[0..7]<8>
DDR_B_DQS[0..7]<8>
DDR_B_MA[0..13]<8>

D D

C C

B B

A A

Layout Note:
Place near JP42

+1.8V

2.2U_0805_16V4Z

2.2U_ 0805 _16V 4Z

C29

1

1

2

2

Layout Note:
Place one cap close to every 2 pullup
resistors terminated to +0.9VS

+0.9VS

0.1U_ 0402 _16V 4Z

0.1U_0402_16V4Z

1

1

2

2

C73

C80

DDR_B_CAS#
DDR_B_WE#

M_ODT3

DDR_B_BS#0
DDR_B_MA10

DDR_B_MA1
DDR_B_MA3
DDR_B_MA5
DDR_B_MA9

DDR_CKE2_DIMMB
DDR_B_BS#2
DDR_B_MA12
DDR_B_MA8

56_0804_8P4R_5%

R44
R41

56_0804_8P4R_5%

56_0804_8P4R_5%

2.2U_0805_16V4Z

C23

0.1U_0402_16V4Z

1

2

C76

RP3

1 2

56_0402_5%

56_0402_5%

1 2

RP8

RP12

5

C90

1

2

0.1U_0402_16V4Z

2.2U_ 0805 _16V 4Z

0.1U_ 0402 _16V 4Z

1

2

C35

+0.9VS

18
27
36
45

45
36
27
18

18
27
36
45

2.2U_ 0805 _16V 4Z

C96

1

2

0.1U_ 0402 _16V 4Z

1

2

C41

RP4

4 5
3 6
2 7
1 8

56_0804_8P4R_5%

RP5

4 5
3 6
2 7
1 8

56_0804_8P4R_5%

RP11

4 5
3 6
2 7
1 8

56_0804_8P4R_5%

C22

1

2

1

2

C56

0.1U_ 0402 _16V 4Z
C68

1

2

0.1U_ 0402 _16V 4Z

0.1U_ 0402 _16V 4Z

1

1

2

2

C81

DDR_B_MA13
M_ODT2
DDR_CS2_DIMMB#DDR_CS3_DIMMB#
DDR_B_RAS#

DDR_B_BS#1
DDR_B_MA0
DDR_B_MA2
DDR_B_MA4

DDR_B_MA7
DDR_B_MA11
DDR_B_MA6
DDR_CKE3_DIMMB

0.1U_ 0402 _16V 4Z

0.1U_0402_16V4Z
C75

1

2

0.1U_ 0402 _16V 4Z

1

2

C52

C62

0.1U_ 0402 _16V 4Z

C88

1

2

0.1U_ 0402 _16V 4Z

0.1U_0402_16V4Z

1

2

C84

Layout Note:
Place these resistor
closely JP42,all
trace length Max=1.5"

4

C32

1

2

0.1U_ 0402 _16V 4Z

0.1U_ 0402 _16V 4Z

1

1

1

2

2

2

C65

C36

C38

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

EC_P80_DATA<13,33>

DDR_CKE2_DIMMB<7>

EC_P80_CLK<13,33>

DDR_CS3_DIMMB#<7>

Issued Date

3

+1.8V

JP4

1

VREF

3

DDR_B_D0
DDR_B_D1

DDR_B_DQS#0
DDR_B_DQS0

DDR_B_D2
DDR_B_D3

DDR_B_D8
DDR_B_D9

DDR_B_DQS#1
DDR_B_DQS1

DDR_B_D10
DDR_B_D11

DDR_B_D20
DDR_B_DQS#2

DDR_B_DQS2
DDR_B_D18

DDR_B_D19
DDR_B_D28

DDR_B_DM3

DDR_B_D30
DDR_B_D31

DDR_CKE2_DIMMB

DDR_B_BS#2<8>

DDR_B_BS#0<8>
DDR_B_WE#<8>

DDR_B_CAS#<8>

M_ODT3<7>

CLK_SMBDATA<13,15>

CLK_SMBCLK<13,15>

3

DDR_B_BS#2
DDR_B_MA12

DDR_B_MA9
DDR_B_MA8

DDR_B_MA5
DDR_B_MA3
DDR_B_MA1

DDR_B_MA10
DDR_B_BS#0
DDR_B_WE#

DDR_B_CAS#
DDR_CS3_DIMMB#

M_ODT3
DDR_B_D32

DDR_B_D33
DDR_B_DQS#4

DDR_B_DQS4
DDR_B_D34

DDR_B_D35
DDR_B_D40

DDR_B_D41
DDR_B_DM5
DDR_B_D42

DDR_B_D43
DDR_B_D48

DDR_B_D49

DDR_B_DQS#6
DDR_B_DQS6

DDR_B_D51
DDR_B_D50

DDR_B_D56
DDR_B_D61 DDR_B_D57

DDR_B_DM7
DDR_B_D59

DDR_B_D58
CLK_SMBDATA

CLK_SMBCLK

+3VS

1

C6

0.1U_0402_16V4Z

2005/10/06 2006/10/06

2

Compal Secret Data

VSS

5

DQ0

7

DQ1

9

VSS

11

DQS0#

13

DQS0

15

VSS

17

DQ2

19

DQ3

21

VSS

23

DQ8

25

DQ9

27

VSS

29

DQS1#

31

DQS1

33

VSS

35

DQ10

37

DQ11

39

VSS

41

VSS

43

DQ16

45

DQ17

47

VSS

49

DQS2#

51

DQS2

53

VSS

55

DQ18

57

DQ19

59

VSS

61

DQ24

63

DQ25

65

VSS

67

DM3

69

NC

71

VSS

73

DQ26

75

DQ27

77

VSS

79

CKE0

81

VDD

83

NC

85

BA2

87

VDD

89

A12

91

A9

93

A8

95

VDD

97

A5

99

A3

101

A1

103

VDD

105

A10/AP

107

BA0

109

WE#

111

VDD

113

CAS#

115

NC/S1#

117

VDD

119

NC/ODT1

121

VSS

123

DQ32

125

DQ33

127

VSS

129

DQS4#

131

DQS4

133

VSS

135

DQ34

137

DQ35

139

VSS

141

DQ40

143

DQ41

145

VSS

147

DM5

149

VSS

151

DQ42

153

DQ43

155

VSS

157

DQ48

159

DQ49

161

VSS

163

NC,TEST

165

VSS

167

DQS6#

169

DQS6

171

VSS

173

DQ50

175

DQ51

177

VSS

179

DQ56

181

DQ57

183

VSS

185

DM7

187

VSS

189

DQ58

191

DQ59

193

VSS

195

SDA

197

SCL

199

VDDSPD

P-TWO_A5692B-A0G16-P

ME@

SO-DIMM B

Deciphered Date

VSS
DQ4
DQ5
VSS
DM0
VSS
DQ6
DQ7

VSS
DQ12
DQ13

VSS

DM1

VSS

CK0#

VSS
DQ14
DQ15

VSS

VSS
DQ20
DQ21

VSS

DM2

VSS
DQ22
DQ23

VSS
DQ28
DQ29

VSS

DQS3#

DQS3

VSS
DQ30
DQ31

VSS

NC/CKE1

VDD

NC/A15
NC/A14

VDD

VDD

VDD
RAS#

VDD
ODT0

NC/A13

VDD

VSS
DQ36
DQ37

VSS

DM4

VSS
DQ38
DQ39

VSS
DQ44
DQ45

VSS

DQS5#

DQS5

VSS
DQ46
DQ47

VSS
DQ52
DQ53

VSS

CK1#

VSS

DM6

VSS
DQ54
DQ55

VSS
DQ60
DQ61

VSS

DQS7#

DQS7

VSS
DQ62
DQ63

VSS

SAO

2

+1.8V

+DDR_MCH_REF1

2

DDR_B_D5

4

DDR_B_D4

6
8

DDR_B_DM0

10
12

DDR_B_D6

14

DDR_B_D7

16
18

DDR_B_D12

20

DDR_B_D13

22
24

DDR_B_DM1

26
28

M_CLK_DDR3

30

CK0

NC

A11

A7
A6

A4
A2
A0

BA1

S0#

NC

CK1

SA1

2

32
34
36
38
40

42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200

M_CLK_DDR#3
DDR_B_D14

DDR_B_D15

DDR_B_D21DDR_B_D17
DDR_B_D16

DDR_B_DM2
DDR_B_D22

DDR_B_D23
DDR_B_D26

DDR_B_D24DDR_B_D25
DDR_B_DQS#3

DDR_B_DQS3
DDR_B_D29

DDR_B_D27
DDR_CKE3_DIMMB

DDR_B_MA11
DDR_B_MA7
DDR_B_MA6

DDR_B_MA4
DDR_B_MA2
DDR_B_MA0

DDR_B_BS#1
DDR_B_RAS#
DDR_CS2_DIMMB#

M_ODT2
DDR_B_MA13

DDR_B_D36
DDR_B_D37

DDR_B_DM4
DDR_B_D39

DDR_B_D38
DDR_B_D44

DDR_B_D45
DDR_B_DQS#5

DDR_B_DQS5
DDR_B_D46

DDR_B_D47
DDR_B_D52

DDR_B_D53
M_CLK_DDR2

M_CLK_DDR#2
DDR_B_DM6
DDR_B_D54

DDR_B_D55
DDR_B_D60

DDR_B_DQS#7
DDR_B_DQS7

DDR_B_D62
DDR_B_D63

10K_0402_5%

12

2.2U_ 0805 _16V 4Z

0.1U_ 0402 _16V 4Z

1

C146

2

M_CLK_DDR3<7>
M_CLK_DDR#3<7>

PM_EXTTS#0<7,13>

DDR_CKE3_DIMMB<7>

DDR_B_BS#1<8>
DDR_B_RAS#<8>
DDR_CS2_DIMMB#<7>

M_ODT2 <7>

M_CLK_DDR2<7>
M_CLK_DDR#2<7>

R12

1 2

10K_0402_5%

R14

Title

Size Document Number Rev

Date: Sheet of

+3VS

Compal Electronics, Inc.

DDRII-SODIMM SLOT2

HGT30/31 LA-3061

星期四二月

23, 2006

+DDR_MCH_REF1<13>

1

C135

2

1

14 47,

1

0.1

PDF created with pdfFactory Pro trial version www.pdffactory.com

5

PCI

SRC

CPU

CLKSEL1

0

1

FSLA

CLKSEL0

Stuff

No Stuff

Stuff

No Stuff

Stuff

No Stuff

MHz

133

166

CLK_Ra

CLK_Rd

CLK_Rd

CLK_Ra

CLK_Rd

CLK_Ra

MHz

1000

100

CLK_Rb

CLK_Re

CLK_Re

CLK_Rb

CLK_Rf

CLK_Rb

MHz

33.31

33.3

CLK_Rc

CLK_Rf

CLK_Rf

CLK_Rc

CLK_Rc

ICH_SMBDATA<21,28,37>

ICH_SMBCLK<21,28,37>

FSLC1FSLB

CLKSEL2

0

Table : ICS954306

D D

FSB Frequency Selet:

CPU Driven

(Default)

*

533MHz

667MHz

CLK_Re

+VCCP

R349

@

R353

8.2K_0402_5%

C C

B B

A A

FSA

FSB

CLKREF1

R374

10K_0402_5%@

PCI_MINI

R373
10K_0402_5%

1 2

R332

0_0402_5%

CLK_Ra

R701

8.2K_0402_5%

1 2

R121

0_0402_5%

CLK_Rb

8.2K_0402_5%

1 2

0_0402_5%

CLK_Rc

CPU_BSEL0<5>

HGT30 @ 10/7 HGT30 @ 10/7

CPU_BSEL1<5>

CPU_BSEL2<5>

+3VS

12

12

56_0402_5%

CLK_Rd

1 2

1 2

12

R326

1K_0402_5%

R396

R397

12

R323

1K_0402_5%@

+VCCP

R123

1K_0402_5%@

1 2

12

1 2

R122

1K_0402_5%

12

R120

@

0_0402_5%

CLK_Re

+VCCP

R383
1K_0402_5%@

1 2

12

1 2

R407

1K_0402_5%

12

@

0_0402_5%

CLK_Rf

R390

PCI_MINI = FCTSEL1

FCTSEL1
(PIN34)

PIN43

0

1

27Mout

5

MCH_CLKSEL0<7>

MCH_CLKSEL1<7>

MCH_CLKSEL2<7>

12

R363

10K_0402_5%

CLK_ENABLE#

12

R352
10K_0402_5%

@

CLK_14M_CODEC<29>

+3VS

12

R368

12

R367

CLK_14M_SIO<32>

10K_0402_5%

PCI_ICH

10K_0402_5%

@

CLK_MCH_DREFCLK<7>

CLK_MCH_DREFCLK#<7>

PIN47PIN44

96/100M_TDOT96CDOT96T

SRCT027MSSout

+3VS

CLK_48M_ICH<21>

CLK_14M_ICH<21>

CLK_PCI_1394<26>

CLK_PCI_LPC<33>

CLK_PCI_PCM<24>

CLK_PCI_LAN<27>
CLK_PCI_DB<32>

CLK_MCH_DREFCLK
CLK_MCH_DREFCLK#

CLK_PCI_ICH<19>

CLK_ENABLE#<45>

CLK_SMBCLK<13,14>

CLK_SMBDATA<13,14>

+3VS

12

12

PIN48

96/100M_C

SRCC0

4

2.2K_0402_5%
Q29
2N7002_SOT23

D

1 3

2

2

1 3

D

2N7002_SOT23

Q28

PCI6 PCI5ITP

R382

10K_0402_5%@

PCI_LAN

R389
10K_0402_5%

4

+3VS

R428

S

G

G

S

HGT30 @ 10/11

CLK_48M_ICH

CLK_14M_ICH

1 2

R362 33_0402_5% UMA@

1 2

R361 33_0402_5%UMA@

CLK_PCI_ICH

CLK_ENABLE#

CLK_SMBCLK

CLK_SMBDATA

R430 0_0402_5%

+3VS+3VS

12

R406

CLK_CODEC

12

R405
10K_0402_5%

PCI_PME=SEL_PCI6

PCI_LAN

0
1 PCICLK6

R419

2.2K_0402_5%

CLK_SMBDATA

CLK_SMBCLK

+CK_VDD_MAIN1

+CK_VDD_REF

1 2

C452 0.1U_0402_16V4Z

+CK_VDD_48

1 2

C422 0.1U_0402_16V4Z

CLK_XTAL_IN

CLK_XTAL_OUT

R364

12

33_0402_5%

12

R412 33_0402_5%

R38133_0402_5%

12

R38733_0402_5%

12

R38833_0402_5%

12

R40415_0402_5%

12

R39515_0402_5%

12

CLK_CODEC

R41515_0402_5%

12

R14515_0402_5%

12

MCH_DREFCLK
MCH_DREFCLK#

R372

12

33_0402_5%

1 2

10K_0402_5% @

PIN27

CLKREQ5

3

+CK_VDD_MAIN1

1 2

+3VS

FSA
FSB
CLKREF1

PCI_MINI
PCI_EC
PCI_PCM

PCI_LAN

PCI_ICH

CLKIREF

R429 0_0805_5%

1 2

+3VS

R331 0_0805_5%

U29

1

VDDSRC

49

VDDSRC

54

VDDSRC

65

VDDSRC

30

VDDPCI

36

VDDPCI

12

VDDCPU

18

VDDREF

40

VDD48

20

X1

19

X2

41

USB_48MHz/FSLA

45

FSLB/TEST_MODE/24Mhz

23

REF0/FSLC/TEST_SEL

34

PCICLK4/FCTSEL1

33

SEL_48M/PCICLK3

32

SEL_24M/PCICLK2

27

SEL_PCI6/PCICLK1

22

SEL_PCI5/REF1

43

DOTT_96MHz/27MHz_Nonspread

44

DOTC_96MHz/27MHz_spread

37

ITP_EN/PCICLK_F0

39

VTT_PWRGD#/PD

16

SMBCLK

17

SMBDAT

9

GND

4

GNDSRC

15

GNDCPU

21

GNDREF

31

GNDPCI

35

GNDPCI

42

GND48

68

GNDSRC

SLG8LP465VTR_QFN72

1

2

+CK_VDD_MAIN2

1

2

CPUCLKT2_ITP/SRCCLKT10LP

CPUCLKC2_ITP/SRCCLKC10LP

C227
10U_0805_10V4Z

C413
10U_0805_10V4Z

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

1

C218

0.1U_0402_16V4Z

2

1

C458

0.1U_0402_16V4Z

2

VDDA
GNDA

PCI_SRC_STOP#

CPU_STOP#

CPUCLKT1LP

CPUCLKC1LP

CPUCLKT0LP

CPUCLKC0LP

SRCCLKT9LP

SRCCLKC9LP

CLKREQ9#

SRCCLKT8LP

SRCCLKC8LP

CLKREQ8#

SRCCLKT7LP

SRCCLKC7LP

CLKREQ7#/48Mhz_1

SRCCLKT6LP

SRCCLKC6LP

CLKREQ6#

SRCCLKT5LP

SRCCLKC5LP

CLKREQ5#/PCICLK6

SRCCLKT4LP

SRCCLKC4LP

CLKREQ4#

SRCCLKT3LP

SRCCLKC3LP

CLKREQ3#/PCICLK5

SRCCLKT2LP

SRCCLKC2LP

CLKREQ2#

SRCCLKT1LP

SRCCLKC1LP

CLKREQ1#
LCD100/96/SRC0_TLP
LCD100/96/SRC0_CLP

2005/10/06 2006/10/06

1

C219

0.1U_0402_16V4Z

2

1

C457

0.1U_0402_16V4Z

2

1

C450

7

0.1U_0402_16V4Z

2

8

25
24

11
10

14
13

6
5

3
2
72
70
69
71
66
67
38
63
64
62
60
61
29
58
59
57
55
56
28
52
53
26
50
51
46
47
48

H_STP_PCI#
H_STP_CPU#

MCH_BCLK

1 2

R424 0_0402_5%

MCH_BCLK#

1 2

R423 0_0402_5%

1 2

R426 0_0402_5%

1 2

R425 0_0402_5%

PCIE_SATA

1 2

R414 0_0402_5%

PCIE_SATA#

1 2

R417 0_0402_5%

MCH_3GPLL

1 2

R399 0_0402_5%

MCH_3GPLL#

1 2

R410 0_0402_5%
R394 0_0402_5%

1 2

R386 0_0402_5%

PCIE_ICH#

1 2

R393 0_0402_5%

PCIE_NC1 CLK_PCIE_NC1

1 2

R371 0_0402_5% EXP@

1 2

R378 0_0402_5% EXP@

1 2

R356 0_0402_5%

PCIE_MCARD#

1 2

R355 0_0402_5%

PCIE_VGA CLK_PCIE_VGA

1 2

R358 0_0402_5%VGA@

1 2

R357 0_0402_5% VGA@

SSCDREFCLK

1 2

R360 0_0402_5%UMA@

SSCDREFCLK#

1 2

R359 0_0402_5% UMA@

Compal Secret Data

Deciphered Date

2

1

C432

0.1U_0402_16V4Z

2

1 2

R330

1_0805_1%

1 2

R427

2.2_0805_1%

L17

CHB1608U301_0603

1 2

1

C451
10U_0805_10V4Z

2

CLK_MCH_BCLK
CLK_MCH_BCLK#

CLK_CPU_BCLKCPU_BCLK
CLK_CPU_BCLK#CPU_BCLK#

CLK_PCIE_SATA
CLK_PCIE_SATA#

CLK_MCH_3GPLL
CLK_MCH_3GPLL#
MCH_CLKREQ#CLKREQ5#

12

CLK_PCIE_ICHPCIE_ICH
CLK_PCIE_ICH#

CLK_PCIE_NC1#PCIE_NC1#
CLKREQ_NC#
CLK_PCIE_MCARDPCIE_MCARD
CLK_PCIE_MCARD#
CLKREQ_MCARD#

CLK_PCIE_VGA#PCIE_VGA#

CLK_MCH_SSCDREFCLK
CLK_MCH_SSCDREFCLK#

2

1

2

+CK_VDD_REF

+CK_VDD_48

+3VS

H_STP_PCI#<21>
H_STP_CPU#<21>

SATAREQ#

C222

0.1U_0402_16V4Z

Place crystal within
500 mils of CK410

CLK_MCH_BCLK<7>
CLK_MCH_BCLK#<7>

CLK_CPU_BCLK<4>
CLK_CPU_BCLK#<4>

CLK_PCIE_SATA<20>
CLK_PCIE_SATA#<20>
SATAREQ#<21>

CLK_MCH_3GPLL<7>
CLK_MCH_3GPLL#<7>
MCH_CLKREQ#<7>
CLK_PCIE_ICH<21>
CLK_PCIE_ICH#<21>

CLK_PCIE_NC1<37>
CLK_PCIE_NC1#<37>
CLKREQ_NC#<37>
CLK_PCIE_MCARD<28>
CLK_PCIE_MCARD#<28>
CLKREQ_MCARD#<28>
CLK_PCIE_VGA<18>
CLK_PCIE_VGA#<18>

CLK_MCH_SSCDREFCLK<7>
CLK_MCH_SSCDREFCLK#<7>

Title

Size Document Number Rev

Date: Sheet of

1

1

C233

0.1U_0402_16V4Z

2

1

C449

0.1U_0402_16V4Z

2

C446 27P_0402_50V8J

12

CLK_XTAL_IN
CLK_XTAL_OUT

Place near U4

Place these components

Y2

14.31818MHZ_16PF_DSX840GA
C448 27P_0402_50V8J

near each pin within 40
mils.

CLK_CPU_BCLK

R434 49.9_0402_1%@

CLK_CPU_BCLK#

R433 49.9_0402_1%@

CLK_MCH_BCLK

R432 49.9_0402_1%@

CLK_MCH_BCLK#

R431 49.9_0402_1%@

CLK_MCH_SSCDREFCLK
CLK_MCH_SSCDREFCLK#
CLK_PCIE_MCARD
CLK_PCIE_MCARD#
CLK_MCH_3GPLL
CLK_MCH_3GPLL#
CLK_PCIE_VGA
CLK_PCIE_VGA#
CLK_PCIE_ICH
CLK_PCIE_ICH#
CLK_MCH_DREFCLK
CLK_MCH_DREFCLK#

SATAREQ#

CLKREQ_NC#

CLKREQ_MCARD#

CLK_PCIE_SATA
CLK_PCIE_SATA#
CLK_PCIE_NC1
CLK_PCIE_NC1#

R366 10K_0402_5%

R137 10K_0402_5%

R140 10K_0402_5%

R345 49.9_0402_1%@
R344 49.9_0402_1%@
R341 49.9_0402_1%@
R340 49.9_0402_1%@
R398 49.9_0402_1%@
R409 49.9_0402_1%@
R343 49.9_0402_1%@
R342 49.9_0402_1%@
R385 49.9_0402_1% @
R392 49.9_0402_1%@
R347 49.9_0402_1% @
R346 49.9_0402_1%@
R413 49.9_0402_1%@
R416 49.9_0402_1%@
R370 49.9_0402_1%@
R377 49.9_0402_1% @

Compal Electronics, Inc.

Clock generator

HGT30/31 LA3061

星期四二月

23, 2006

1

1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2

12
12

12
12

12
12

12

12

12

15 47,

+3VS

0.1

PDF created with pdfFactory Pro trial version www.pdffactory.com

A

1 1

B

C

D

E

F

G

H

+LCDVDD +5VALW

12

R196

100_0402_1%

UMA@

13

R203

0_0402_5%UMA@

0_0402_5% VGA@

D

Q15

S

UMA@

12

0_0402_5%UMA@

12

12

2N7002_SOT23

GMCH_LVDDEN<9>

2 2

INVPWR_B+B+

0.1U_0603_50V4Z

L14 0_0805_5%

1 2

L15 0_0805_5% @

1 2

INVT_PWM<33>

3 3

DAC_BRIG<33>

INVPWR_B+

C294

12

12

C295

68P_0402_50V8K

DISPOFF#

JP40

1
2
3
4
5
6
7

MOLEX_53780-0790

ENBKL<33>

GMCH_ENBKL<9>

G7X_ENBKL<18>

BKOFF#<33>

R52

R89

2

2

G

R204

1 2

R201
100K_0402_5%

UMA@

1 2

R711

1 2

10K_0402_5%

UMA@

13

Q16
DTC124EK_SC59

UMA@

D9
CH751H-40_SC76

21

D10

<BOM Structure>

CH751H-40_SC76

21

@

100K_0402_5%

0.047U_0402_16V4Z

+3VS

1

2

R202

4.7K_0402_5%

1 2

DISPOFF#

+LCDVDD

C291

UMA@

0.1U_0402_16V4Z

UMA@

1

C288

2

DISPOFF#

1

C289

4.7U_0805_10V4Z

2

UMA@

UMA@

Q14

D

1 3

2

+3VS

S

AO3413_SOT23

G

1

C290

4.7U_0805_10V4Z

2

UMA@

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

C

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

D

2005/10/06 2006/10/06

E

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

F

Date: Sheet of

Compal Electronics, Inc.

LVDS Connector

HGT30/31 LA3061

星期四二月

23, 2006

G

16 47,

H

0.1

PDF created with pdfFactory Pro trial version www.pdffactory.com

A

B

C

D

E

TV-OUT Conn.

CARD_LUMA<18>

CARD_CRMA<18>

1 1

CARD_COMP<18>

TV_LUMA<9>
TV_CRMA<9>

TV_COMPS<9>

R60 0_0402_5% VGA@

R59 0_0402_5%VGA@

R61 0_0402_5%VGA@

R224 0_0402_5%UMA@
R225 0_0402_5%UMA@
R223 0_0402_5%UMA@

12

12

12

12
12
12

R4

150_0603_1%

12

12

12

R5

R3

150_0 603_1%

150_0603_1%

LUMA <36>

CRMA <36>

COMP <36>

Pop when with internal graphics

CRT Conn.

VGA@

CARD_VGA_R<18>

CARD_VGA_G<18>

CARD_VGA_B<18>

2 2

CRT_R<9>

CRT_G<9>

CRT_B<9>

12

R64 0_0402_5%

VGA@

12

R66 0_0402_5%

VGA@

12

R68 0_0402_5%

UMA@

12

R63 0_0402_5%

UMA@

12

R65 0_0402_5%

UMA@

12

R67 0_0402_5%

12

12

12

R7

R6

R8

150_060 3_1%

150_0603_1%

150_0603_1%

Pop when with internal graphics

+3VS+3VS +2.5VS

12

12

12

R198

R197

0_0402_5%

0_0402_5%

VGA@

CARD_DDCDATA<18>

3 3

CARD_DDCCLK<18>

3VDDCDA<9>

3VDDCCL<9>

CARD_HSYNC<18>

CARD_VSYNC<18>

CRT_HSYNC<9>

CRT_VSYNC<9>

R80 0_0402_5%
R79 0_0402_5%VGA@

R76 0_0402_5%

R75 0_0402_5%

12
12

UMA@

1 2

UMA@

1 2

VGA@

12

R82 0_0402_5%

VGA@

12

R81 0_0402_5%

UMA@

1 2

R78 39_0402_5%

UMA@

1 2

R77 39_0402_5%

Pop when with internal graphics

4 4

VGA@

12

R9

2.2K_0402_5%

G

S

R2 0_0402_5%@

1

2

1

2

0.1U_0402_16V4Z

UMA@

+3VS

2

13

D

+CRT_VCC

0.1U_0402_16V4Z
C5

+CRT_VCC

C4

R199
0_0402_5%

UMA@

Q1

2N7002_SOT23

12

12

R200
0_0402_5%

VGA@

+3VS

12

R10

2.2K_0402_5%

G

2

S

R11 0_0402_5%@

1

5

U1

P

OE#

A2Y

G

74AHCT1G125GW_SOT353-5

3

1

5

U2

P

OE#

A2Y

G

74AHCT1G125GW_SOT353-5

3

L1 0_0603_5%

L2 0_0603_5%

L3 0_0603_5%

Q2

2N7002_SOT23

13

D

12

4

4

1 2

1 2

1 2

12

R1
1K_0402_5%

RED <36>

GREEN <36>

1

1

C3

C1

2

82P_0402_50V8J

@

@

1

C2

2

2

82P_0402_50V8J

82P_0402_50V8J

@

BLUE <36>

VGA_DDC_DAT<36>

VGA_DDC_CLK<36>

JVGA_HS<36>

JVGA_VS<36>

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

PDF created with pdfFactory Pro trial version www.pdffactory.com

2005/10/06 2006/10/06

C

Compal Secret Data

Deciphered Date

D

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

CRT & TVout

HGT30/31 LA3061

星期四二月

23, 2006

E

17 47,

0.1

5

4

3

2

1

D D

MAX. 4.06A @ 1.8V
MAX. 130mA @ 2.5V
MAX. 655mA @ 3.3V

PEG_M_TXP[0..15]
PEG_M_TXN[0..15]

JP7

1

PEG_M_TXP1
PEG_M_TXN1

PEG_M_TXP3
PEG_M_TXN3

PEG_M_TXP5
PEG_M_TXN5

PEG_M_TXP7
PEG_M_TXN7

C C

PEG_M_TXP9
PEG_M_TXN9

PEG_M_TXP11
PEG_M_TXN11

PEG_M_TXP13
PEG_M_TXN13

PEG_M_TXP15
PEG_M_TXN15

+3VS +5VS

+1.5VS

+2.5VS

B B

< New Add Pin.28 for +3VS, Pin.68 for +1.8VS @R03 >

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

11

11

12

12

13

13

14

14

15

15

16

16

17

17

18

18

19

19

20

20

21

21

22

22

23

23

24

24

25

25

26

26

27

27

28

28

29

29

30

30

31

31

32

32

33

33

34

34

35

35

36

36

37

37

38

38

39

39

40

40

ACES_88363-08001

ME@

41

41

42

42

43

43

44

44

45

45

46

46

47

47

48

48

49

49

50

50

51

51

52

52

53

53

54

54

55

55

56

56

57

57

58

58

59

59

60

60

61

61

62

62

63

63

64

64

65

65

66

66

67

67

68

68

69

69

70

70

71

71

72

72

73

73

74

74

75

75

76

76

77

77

78

78

79

79

80

80

PEG_RXP1

PEG_RXN1

PEG_RXP3

PEG_RXN3

PEG_RXP5
PEG_RXN5

PEG_RXP7
PEG_RXN7

PEG_RXP9
PEG_RXN9

PEG_RXP11
PEG_RXN11

PEG_RXP13
PEG_RXN13

PEG_RXP15
PEG_RXN15

+1.8VS

<@R03><@R03>

B+

CARD_DDCCLK<17>
CARD_DDCDATA<17>

CLK_PCIE_VGA<15>

CLK_PCIE_VGA#<15>

CARD_VSYNC<17>
CARD_HSYNC<17>

CARD_VGA_R<17>
CARD_VGA_G<17>

CARD_VGA_B<17>

PEG_M_TXP0
PEG_M_TXN0

PEG_M_TXP2
PEG_M_TXN2

PEG_M_TXP4
PEG_M_TXN4

PEG_M_TXP6
PEG_M_TXN6

PEG_M_TXP8
PEG_M_TXN8

PEG_M_TXP10
PEG_M_TXN10

PEG_M_TXP12
PEG_M_TXN12

PEG_M_TXP14
PEG_M_TXN14

JP8

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

11

11

12

12

13

13

14

14

15

15

16

16

17

17

18

18

19

19

20

20

21

21

22

22

23

23

24

24

25

25

26

26

27

27

28

28

29

29

30

30

31

31

32

32

33

33

34

34

35

35

36

36

37

37

38

38

39

39

40

40

ACES_88363-08001

ME@

41

41

42

42

43

43

44

44

45

45

46

46

47

47

48

48

49

49

50

50

51

51

52

52

53

53

54

54

55

55

56

56

57

57

58

58

59

59

60

60

61

61

62

62

63

63

64

64

65

65

66

66

67

67

68

68

69

69

70

70

71

71

72

72

73

73

74

74

75

75

76

76

77

77

78

78

79

79

80

80

PEG_RXP0

PEG_RXN0

PEG_RXP2

PEG_RXN2

PEG_RXP4

PEG_RXN4

PEG_RXP6

PEG_RXN6

PEG_RXP8

PEG_RXN8

PEG_RXP10
PEG_RXN10

PEG_RXP12
PEG_RXN12

PEG_RXP14
PEG_RXN14

SUSP#

G7X_THER_ALERT#

SUSP# <24,26,33,34,35,37,43,44>
G7X_THER_ALERT#<21>

G7X_ENBKL<16>

PLTRST_VGA#<19>

CARD_COMP<17>
CARD_LUMA<17>
CARD_CRMA<17>

PEG_RXP[0..15]
PEG_RXN[0..15]

2

1

VGA@

PEG_M_TXP[0..15]<9>
PEG_M_TXN[0..15]<9>

PEG_RXP[0:15]<9>
PEG_RXN[0:15]<9>

2

C244

C240

1

0.1U_0402_16V4Z

0.1U_0402_16V4Z

VGA@

+3VS

1

C111

C110

2

0.047U_ 0402_16V4Z

VGA@

VGA@

VGA@

0.047U_0402_16V 4Z

+2.5VS+5VS

2

2

C112

1

C113

1

0.1U_0402_16V4Z

0.1U_0402_16V4Z

VGA@

1

2

A A

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

Size Document Number Rev
Custom

Date: Sheet of

Compal Electronics, Inc.

星期四二月

VGA/B connector

23, 2006

1

HGT30/31 LA3061

18 47,

0.1

PDF created with pdfFactory Pro trial version www.pdffactory.com

5

4

3

2

1

D D

C C

B B

+3VS

R271 8.2K_0402_5%

1 2

R268 8.2K_0402_5%

1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2

1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2

R269 8.2K_0402_5%
R263 8.2K_0402_5%
R273 8.2K_0402_5%
R287 8.2K_0402_5%
R274 8.2K_0402_5%
R276 8.2K_0402_5%
R272 8.2K_0402_5%
R270 8.2K_0402_5%

+3VS

R298 8.2K_0402_5%
R300 8.2K_0402_5%
R294 8.2K_0402_5%
R291 8.2K_0402_5%
R283 8.2K_0402_5%
R290 8.2K_0402_5%
R279 8.2K_0402_5%
R284 8.2K_0402_5%
R286 8.2K_0402_5%
R264 8.2K_0402_5%
R261 8.2K_0402_5%
R282 8.2K_0402_5%

PCI_DEVSEL#
PCI_STOP#
PCI_TRDY#
PCI_FRAME#
PCI_PLOCK#
PCI_IRDY#
PCI_SERR#
PCI_PERR#
PCI_REQ4#
PCI_REQ3#

PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#
PCI_PIRQE#
PCI_PIRQF#
PCI_PIRQG#
PCI_PIRQH#
PCI_REQ0#
PCI_REQ1#
PCI_REQ2#
PCI_REQ5#

PCI_AD[0..31]<24,26,27,32>

PCI_PIRQA#<24>
PCI_PIRQB#

PCI_AD0
PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD6
PCI_AD7
PCI_AD8
PCI_AD9
PCI_AD10
PCI_AD11
PCI_AD12
PCI_AD13
PCI_AD14
PCI_AD15
PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20
PCI_AD21
PCI_AD22
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30
PCI_AD31

PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#

U3B

E18

AD0

C18

AD1

A16

AD2

F18

AD3

E16

AD4

A18

AD5

E17

AD6

A17

AD7

A15

AD8

C14

AD9

E14

AD10

D14

AD11

B12

AD12

C13

AD13

G15

AD14

G13

AD15

E12

AD16

C11

AD17

D11

AD18

A11

AD19

A10

AD20

F11

AD21

F10

AD22

E9

AD23

D9

AD24

B9

AD25

A8

AD26

A6

AD27

C7

AD28

B6

AD29

E6

AD30

D6

AD31

Interrupt I/F

A3

PIRQA#

B4

PIRQB#

C5

PIRQC#

B5

PIRQD#

AE5

RSVD[1]

AD5

RSVD[2]

AG4

RSVD[3]

AH4

RSVD[4]

AD9

RSVD[5]

ICH7_BGA652~D

PCI

REQ4# / GPIO22

GNT4# / GPIO48

GPIO1 / REQ5#

GPIO17 / GNT5#

GPIO2 / PIRQE#

GPIO3 / PIRQF#
GPIO4 / PIRQG#
GPIO5 / PIRQH#

MISC

MCH_SYNC#

REQ0#

GNT0#

REQ1#

GNT1#

REQ2#

GNT2#

REQ3#

GNT3#

C/BE0#
C/BE1#
C/BE2#
C/BE3#

IRDY#

PCIRST#

DEVSEL#

PERR#

PLOCK#

SERR#
STOP#

TRDY#

FRAME#

PLTRST#

PCICLK

PME#

RSVD[6]
RSVD[7]
RSVD[8]
RSVD[9]

PAR

D7
E7
C16
D16
C17
D17
E13
F13
A13
A14
C8
D8

B15
C12
D12
C15

A7
E10
B18
A12
C9
E11
B10
F15
F14
F16

C26
A9
B19

G8
F7
F8
G7

AE9
AG8
AH8
F21
AH20

PCI_REQ0#
PCI_GNT0#
PCI_REQ1#

PCI_REQ2#
PCI_GNT2#
PCI_REQ3#
PCI_GNT3#
PCI_REQ4#

PCI_REQ5#

PCI_CBE#0
PCI_CBE#1
PCI_CBE#2
PCI_CBE#3

PCI_IRDY#
PCI_PAR
PCI_PCIRST#
PCI_DEVSEL#
PCI_PERR#
PCI_PLOCK#
PCI_SERR#
PCI_STOP#
PCI_TRDY#

PCI_FRAME#

PCI_PLTRST#
CLK_PCI_ICH
PCI_PME#

PCI_PIRQE#
PCI_PIRQF#
PCI_PIRQG#
PCI_PIRQH#

PCI_REQ0#<26>
PCI_GNT0#<26>

PCI_REQ2#<24>
PCI_GNT2#<24>
PCI_REQ3#<27>
PCI_GNT3#<27>

PCI_CBE#0<24,26,27,32>
PCI_CBE#1<24,26,27,32>
PCI_CBE#2<24,26,27,32>
PCI_CBE#3<24,26,27,32>

PCI_IRDY#<24,26,27>
PCI_PAR <24,26,27>

PCI_DEVSEL#<24,26,27>
PCI_PERR#<24,26,27>

PCI_SERR#<24,26,27>
PCI_STOP#<24,26,27>
PCI_TRDY#<24,26,27,32>
PCI_FRAME#<24,26,27,32>

CLK_PCI_ICH<15>
PCI_PME#<33>

PCI_PIRQE#
PCI_PIRQF#<27>
PCI_PIRQG#<26>
PCI_PIRQH#<26>

MCH_ICH_SYNC#<7>

PCI_PCIRST#

PCI_PLTRST#

+3VS

5

1

B

2

A

3

12

R257 0_0402_5%@

R235 0_0402_5%@

+3VS

5

1

B

2

A

3

12

Place closely pin A9

CLK_PCI_ICH

R277

10_0402_5%@

C364

8.2P_0402_50V@

U21

P

PCI_RST#

4

Y

G

TC7SH08FUF_SSOP5

U18

P

PLT_RST#

4

Y

G

TC7SH08FUF_SSOP5

1 2

1

2

PCI_RST#<21,24,25,26,27,32,33>

R236

12

0_0402_5%

PLT_RST#<7,23,28,37>

PLTRST_VGA#<18>

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/10/06 2006/10/06

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

2

Date: Sheet of

Compal Electronics, Inc.

ICH7-M(1/4)

HGT30/31 LA3061

星期四二月

23, 2006

1

19 47,

0.1

PDF created with pdfFactory Pro trial version www.pdffactory.com

5

4

3

2

1

C195 15P_0402_50V8J

Y1

2

32.768KHZ_12.5P_1TJS125BJ2A251

D D

+RTCVCC

12

R288
1M_0402_5%

SM_INTRUDER#

+RTCVCC

12

R296
332K_0402_1%

C C

ICH_INTVRMEN

+RTCVCC

R293

1 2

20K_0402_5%

J1

C392

1U_0603_10V4Z

1 2

ICH_BITCLK_MDC<28>
ICH_SYNC_MDC<28>

ICH_RST_MDC#<28>

ICH_AC_SDIN0<29>
ICH_AC_SDIN1<28>

ICH_SDOUT_MDC<28>

C196 15P_0402_50V8J

3MM

NC

3

OUT

NC

21

C389

@

10P_0402_25V8K

SATA RX n/p need tie to GND when no used

+3VS

R2664.7K_0402_5%

12

R2658.2K_0402_5%

12

R25910K_0402_5%

B B

PSATA_ITX_DRX_N0<23>

PSATA_ITX_DRX_P0<23>

12

PSATA_ITX_DRX_N0

PSATA_ITX_DRX_P0

Close to U7

ICH_AC_SDOUT_R

ICH_SDOUT_AUDIO<29>

ICH_SYNC_AUDIO<29>

A A

ICH_RST_AUDIO#<29>

ICH_BITCLK_AUDIO<29>

5

1 2

R299 33_0402_5%

1 2

R280 33_0402_5%

1 2

R313 33_0402_5%

1 2

R312 33_0402_5%

1

C390

@

22P_0402_50V8J

2

ICH_AC_SYNC_R

ICH_AC_RST_R#

ICH_AC_BITCLK_R

4

ICH_RTCX1

1

IN

4

ICH_RTCX2

R310

1 2

12

10_0402_5%@

SATA_LED#<38>

PSATA_IRX_DTX_N0_C<23>
PSATA_IRX_DTX_P0_C<23>

HGT30 @ 10/11

CLK_PCIE_SATA#<15>
CLK_PCIE_SATA<15>

PD_IORDY
PD_IRQ
SATA_LED#

1 2

C387 3900P_0402_50V7K

1 2

C388 3900P_0402_50V7K

12

R109

10M_0402_5%

ICH_RTCRST#
ICH_INTVRMEN

SM_INTRUDER#

R311

33_0402_5%

1 2

1 2

R281 33_0402_5%

1 2

R314 33_0402_5%

1 2

R315 33_0402_5%

R702 1K_0402_5%
R703 1K_0402_5%

PD_IORDY<23>
PD_DACK#<23>

PSATA_ITX_DRX_N0_C

PSATA_ITX_DRX_P0_C

1 2
1 2

PD_IRQ<23>
PD_IOW#<23>

PD_IOR#<23>

ICH_AC_BITCLK_R
ICH_AC_SYNC_R

ICH_AC_RST_R#
ICH_AC_SDIN0

ICH_AC_SDIN1

ICH_AC_SDOUT_R

SATA_LED#

PSATA_IRX_DTX_N0_C
PSATA_IRX_DTX_P0_C
PSATA_ITX_DRX_N0_C
PSATA_ITX_DRX_P0_C

CLK_PCIE_SATA#
CLK_PCIE_SATA

R275

1 2

24.9_0402_1%

PD_IORDY
PD_IRQ
PD_DACK#
PD_IOW#
PD_IOR#

U3A

RTXC1
RTCX2

RTCRST#
INTVRMEN

INTRUDER#

EE_CS
EE_SHCLK
EE_DOUT
EE_DIN

LAN_CLK
LAN_RSTSYNC
LAN_RXD0

LAN_RXD1
LAN_RXD2

LAN_TXD0
LAN_TXD1
LAN_TXD2

ACZ_BCLK
ACZ_SYNC

ACZ_RST#
ACZ_SDIN0

ACZ_SDIN1
ACZ_SDIN2

ACZ_SDOUT

SATALED#

SATA0RXN
SATA0RXP
SATA0TXN
SATA0TXP

SATA2RXN
SATA2RXP
SATA2TXN
SATA2TXP

SATA_CLKN
SATA_CLKP

SATARBIASN
SATARBIASP

IORDY
IDEIRQ
DDACK#
DIOW#
DIOR#

ICH7_BGA652~D

3

RTC

LAD0
LAD1
LAD2
LAD3

LDRQ0#

LPCCPU

LDRQ1# / GPIO23

LFRAME#

LAN

A20GATE

A20M#

CPUSLP#

TP1 / DPRSTP#

TP2 / DPSLP#

FERR#

GPIO49 / CPUPWRGD

IGNNE#

INIT3_3V#

AC-97/AZALIA

RCIN#

STPCLK#

THERMTRIP#

DCS1#
DCS3#

SATA

DD10
DD11
DD12
DD13

IDE

DD14
DD15

DDREQ

2005/10/06 2006/10/06

AB1
AB2

AA3

W4

Y5

W1

Y1
Y2

W3

V3
U3
U5

V4
T5

U7
V6
V7

U1
R6

R5
T2

T3
T1

T4

AF18

AF3
AE3
AG2
AH2

AF7
AE7
AG6
AH6

AF1
AE1

AH10
AG10

AG16
AH16
AF16
AH15
AF15

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

INIT#
INTR

SMI#

DD0
DD1
DD2
DD3
DD4
DD5
DD6
DD7
DD8
DD9

AA6
AB5
AC4
Y6

AC3
AA5

AB3

AE22
AH28

AG27
AF24

AH25
AG26
AG24
AG22

AG21
AF22
AF25

AG23
AF23

AH24

NMI

AH22
AF26

AH17

DA0

AE17

DA1

AF17

DA2

AE16
AD16

AB15
AE14
AG13
AF13
AD14
AC13
AD12
AC12
AE12
AF12
AB13
AC14
AF14
AH13
AH14
AC15

AE15

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3

LPC_DRQ0#

LPC_FRAME#

GATEA20
H_A20M#

H_CPUSLP_R#
DPRSLP#

H_DPSLP#
H_FERR#
H_PWRGOOD
H_IGNNE#
H_INIT#

H_INTR

KB_RST#
H_SMI#

H_NMI
H_STPCLK#
THRMTRIP_ICH#

PD_A0
PD_A1
PD_A2

PD_CS#1
PD_CS#3

PD_D0
PD_D1
PD_D2
PD_D3
PD_D4
PD_D5
PD_D6
PD_D7
PD_D8
PD_D9
PD_D10
PD_D11
PD_D12
PD_D13
PD_D14
PD_D15

PD_DREQ

PD_D[0..15]

Compal Secret Data

Deciphered Date

LPC_AD[0..3]<32,33>

LPC_DRQ#0<32>

LPC_FRAME#<32,33>

R250 10K_0402_5%

12

GATEA20 <33>
H_A20M# <4>

R233 0_0402_5% @

12

R243 0_0402_5%

12

H_DPSLP#<4>

12

H_FERR#<4>
H_PWRGOOD<4>
H_IGNNE#<4>
H_INIT# <4>

H_INTR <4>

R251 10K_0402_5%

12

KB_RST# <33>
H_SMI# <4>

H_NMI <4>
H_STPCLK#<4>

R237

1 2

24.9_0402_1%

PD_A0 <23>
PD_A1 <23>
PD_A2 <23>

PD_CS#1 <23>
PD_CS#3 <23>

PD_DREQ<23>

PD_D[0..15]<23>

+RTCVCC

2

1

56_0402_5%
R234

R114

1 2

100_0603_1%

C203

0.1U_0402_16V4Z

2

+3VS

H_CPUSLP#<4,7>
H_DPRSTP#<4,45>

+VCCP

+3VS

D3

RB751V_SOD323

+VCCP

12

R245
56_0402_5%

H_THERMTRIP#<4,7>

BATT1.1

BATT1

+ -

W=20mils

Title

Size Document Number Rev

Custom

Date: Sheet of

1 2

+CHGRTC

ML1220T13RE

45@

21

Compal Electronics, Inc.

ICH7-M(2/4)

HGT30/31 LA3061

星期四二月

23, 2006

20 47,

1

0.1

PDF created with pdfFactory Pro trial version www.pdffactory.com

5

+3VS

10K_0402_5%

1 2

8.2K_0402_5%

1 2

10K_0402_5%

1 2

10K_0402_5%

1 2

150_0402_5%

1 2

10K_0402_5%

1 2

10K_0402_5%

1 2

10K_0402_5%

1 2

1K_0402_5%

1 2

8.2K_0402_5%
10K_0402_5%

1 2

10K_0402_5%

1 2

SIRQ

PCI_CLKRUN#

G7X_THER_ALERT#

LINKALERT#

ITP_DBRESET#

OCP#

SPI_MISO

SPI_CS#

ICH_PCIE_WAKE#

ICH_LOW_BAT#

12

WL_ON

SPI_MOSI

R239

10K_0402_5%

R253

R258

D D

C C

R254

+3VALW

R242

R248

R246

R304

R285

R255

R252
R240

R292

4

3

2

1

Place closely pin B2 Place closely pin AC1

100K_0402_5%@

CLK_14M_ICH

12

R308

10_0402_5%@

1

C391

4.7P_0402_50V8C@

2

SLP_S4#<33>

12

R91

SLP_S5# <33>

+3VALW+3VALW

12

12

R256

R247

PM_BMBUSY#<7>

H_STP_PCI#<15>

H_STP_CPU#<15>

EC_THERM#<33>

EC_SMI#<33>

R232

1 2

8.2K_0402_5%

SB_SPKR<29>

OCP#<4>

SIRQ<24,26,32,33>

VGATE<45>

2.2K_0402_5%

T41PAD

IDERST_CD#

G7X_THER_ALERT#
EC_SMI#

ICH_SMBCLK
ICH_SMBDATA
LINKALERT#
ICH_SMLINK0
ICH_SMLINK1

ICH_RI#
SB_SPKR

SUS_STAT#
ITP_DBRESET#

PM_BMBUSY#
OCP#
H_STP_PCI#

H_STP_CPU#

PCI_CLKRUN#

ICH_PCIE_WAKE#

SIRQ
EC_THERM#

VGATE

U3C

C22

SMBCLK

B22

SMBDATA

A26

LINKALERT#

B25

SMLINK0

A25

SMLINK1

A28

RI#

A19

SPKR

A27

SUS_STAT#

A22

SYS_RST#

AB18

GPIO0 / BM_BUSY#

B23

GPIO11 / SMBALERT#

AC20

GPIO18 / STPPCI#

AF21

GPIO20 / STPCPU#

A21

GPIO26

B21

GPIO27

E23

GPIO28

AG18

GPIO32 / CLKRUN#

AC19

GPIO33 / AZ_DOCK_EN#

U2

GPIO34 / AZ_DOCK_RST#

F20

WAKE#

AH21

SERIRQ

AF20

THRM#

AD22

VRMPWRGD

AC21

GPIO6

AC18

GPIO7

E21

GPIO8

ICH7_BGA652~D

GPIO21 / SATA0GP
GPIO19 / SATA1GP
GPIO36 / SATA2GP
GPIO37 / SATA3GP

SATA

GPIO

SYSSMB

Clocks

GPIO

GPIO16 / DPRSLPVR

TP0 / BATLOW#

POWER MGT

GPIO

GPIO35 / SATAREQ#

Need update symbol

CLK14
CLK48

SUSCLK

SLP_S3#
SLP_S4#
SLP_S5#

PWROK

PWRBTN#

LAN_RST#

RSMRST#

GPIO9
GPIO10
GPIO12
GPIO13
GPIO14
GPIO15
GPIO24
GPIO25

GPIO38
GPIO39

AF19
AH18
AH19
AE19

CLK_14M_ICH

AC1

CLK_48M_ICH

B2

ICH_SUSCLK

C20

SLP_S3#

B24

SLP_S4#

D23

SLP_S5#

F22

ICH_POK

AA4
AC22

R90 100_0402_5%

ICH_LOW_BAT#

C21

PBTN_OUT#

C23

PCI_RST#

C19

EC_RSMRST#

Y4

R297 10K_0402_5%

EC_SCI#

E20
A20
F19

EC_LID_OUT#

E19
R4

CPUSB#

E22

WL_ON

R3

EC_FLASH#

D20

SATAREQ#

AD21
AD20
AE20

1 2

100_0402_5%

1 2

1 2

SB_INT_FLASH_SEL<34>

R260

CLK_14M_ICH<15>
CLK_48M_ICH<15>

T44 PAD

SLP_S3# <33>

ICH_POK<7,33>

DPRSLPVR

PBTN_OUT#<33>
PCI_RST#<19,24,25,26,27,32,33>
EC_RSMRST#<33>

EC_SCI# <33>
ACIN <33,39>

EC_LID_OUT#<33>
CPUSB# <37>
EC_FLASH#<34>

SATAREQ#<15>
KILL_MDC#<28>

1 2

R241
10K_0402_5%

1 2

1 2

2.2K_0402_5%

ICH_SMBCLK<15,28,37>

ICH_SMBDATA<15,28,37>

+3VALW

ITP_DBRESET#<4>

IDERST_CD#<23>

PCI_CLKRUN#<24,26,27,33>

ICH_PCIE_WAKE#<28,37>

G7X_THER_ALERT#<18>

12

R305

1

C384

<>

2

SLP_S4#

SLP_S5#

R295
10K_0402_5%

DPRSLPVR<7,45>

CLK_48M_ICH

10_0402_5%@

4.7P_0402_50V8C@

1 2

R482 0_0402_5%@

DPRSLPVR

PCIE_RXN1<37>
PCIE_RXP1<37>
PCIE_TXN1<37>

PCIE_TXP1<37>

PCIE_RXN2<28>
PCIE_RXP2<28>
PCIE_TXN2<28>

PCIE_TXP2<28>

B B

USB_OC#0<31>
USB_OC#2<37>
USB_OC#4<37>

A A

PCIE_RXN1
PCIE_RXP1
PCIE_C_TXN1

C3230.1U_0402_16V7K

PCIE_C_TXP1

C3310.1U_0402_16V7K

PCIE_RXN2
PCIE_RXP2
PCIE_C_TXN2

C3280.1U_0402_16V7K

PCIE_C_TXP2

C3290.1U_0402_16V7K

SPI_CS#

SPI_MOSI
SPI_MISO

USB_OC#0
USB_OC#1
USB_OC#2
USB_OC#3
USB_OC#4
USB_OC#5
USB_OC#6
USB_OC#7

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

U3D

F26

PERn1

F25

PERp1

E28

PETn1

E27

PETp1

H26

PERn2

H25

PERp2

G28

PETn2

G27

PETp2

K26

PERn3

K25

PERp3

J28

PETn3

J27

PETp3

M26

PERn4

M25

PERp4

L28

PETn4

L27

PETp4

P26

PERn5

P25

PERp5

N28

PETn5

N27

PETp5

T25

PERn6

T24

PERp6

R28

PETn6

R27

PETp6

R2

SPI_CLK

P6

SPI_CS#

P1

SPI_ARB

P5

SPI_MOSI

P2

SPI_MISO

D3

OC0#

C4

OC1#

D5

OC2#

D4

OC3#

E5

OC4#

C3

OC5# / GPIO29

A2

OC6# / GPIO30

B3

OC7# / GPIO31

ICH7_BGA652~D

3

DMI0RXN
DMI0RXP
DMI0TXN
DMI0TXP

DMI1RXN
DMI1RXP
DMI1TXN
DMI1TXP

PCI-EX P RESS

DMI2RXN
DMI2RXP
DMI2TXN
DMI2TXP

DMI3RXN
DMI3RXP
DMI3TXN
DMI3TXP

DMI_CLKN
DMI_CLKP

DIRECT M E DI A I N TERFACE

DMI_ZCOMP

DMI_IRCOMP

USBP0N
USBP0P
USBP1N
USBP1P
USBP2N

SPI

USBP2P
USBP3N
USBP3P
USBP4N
USBP4P
USBP5N
USBP5P
USBP6N

USB

USBP6P
USBP7N
USBP7P

USBRBIAS#

USBRBIAS

2005/10/06 2006/10/06

Compal Secret Data

V26
V25
U28
U27

Y26
Y25
W28
W27

AB26
AB25
AA28
AA27

AD25
AD24
AC28
AC27

AE28
AE27

C25
D25

F1
F2
G4
G3
H1
H2
J4
J3
K1
K2
L4
L5
M1
M2
N4
N3

D2
D1

Deciphered Date

DMI_RXN0
DMI_RXP0
DMI_TXN0
DMI_TXP0

DMI_RXN1
DMI_RXP1
DMI_TXN1
DMI_TXP1

DMI_RXN2
DMI_RXP2
DMI_TXN2
DMI_TXP2

DMI_RXN3
DMI_RXP3
DMI_TXN3
DMI_TXP3

CLK_PCIE_ICH#
CLK_PCIE_ICH

DMI_IRCOMP
USB20_N0

USB20_P0
USB20_N1
USB20_P1
USB20_N2
USB20_P2

USB20_N4
USB20_P4

USB20_N7
USB20_P7

USBRBIAS

DMI_RXN0<7>
DMI_RXP0<7>
DMI_TXN0<7>
DMI_TXP0<7>

DMI_RXN1<7>
DMI_RXP1<7>
DMI_TXN1<7>
DMI_TXP1<7>

DMI_RXN2<7>
DMI_RXP2<7>
DMI_TXN2<7>
DMI_TXP2<7>

DMI_RXN3<7>
DMI_RXP3<7>
DMI_TXN3<7>
DMI_TXP3<7>

CLK_PCIE_ICH#<15>
CLK_PCIE_ICH<15>

R238 24.9_0402_1%

1 2

USB20_N0<31>
USB20_P0<31>
USB20_N1<28>
USB20_P1<28>
USB20_N2<37>
USB20_P2<37>

USB20_N4<37>

USB20_P4<37>

T701PAD
T702PAD

USB20_N7<37>

USB20_P7<37>

R307 22.6_0402_1%

1 2

Within 500 mils

2

Within 500 mils

+1.5VS

Title

Size Document Number Rev

Custom

Date: Sheet of

USB_OC#4
USB_OC#2
USB_OC#3
USB_OC#1

USB_OC#0
USB_OC#5
USB_OC#6
USB_OC#7

RP15

4 5
3 6
2 7
1 8

10K_1206_8P4R_5%

RP16

4 5
3 6
2 7
1 8

10K_1206_8P4R_5%

Compal Electronics, Inc.

ICH7-M(3/4)

HGT30/31 LA3061

星期四二月

23, 2006

1

+3VALW

+3VALW

0.1

21 47,

PDF created with pdfFactory Pro trial version www.pdffactory.com

5

4

3

2

1

ICH_V5REF_RUN

+1.5VS

C327

+1.5VS_DMIPLL

1

2

10U_0805_10V4Z

1

2

C366

+3VALW

1

1

+

C335

2

2

220U_D2_4VM

0.1U_0402_16V4Z

Place closely pin
D28,T28,AD28.

1

C338

0.01U_0402_25V4Z

2

Place closely pin AG5.

C355

0.1U_0402_16V4Z

Place closely pin AG9.

1

2

R712 0_0402_5%@

+3VS

R497 0_0402_5%

D D

100_0402_5%

10_0402_5%

C C

B B

A A

R278

R289

12

12

+3VS+5VS

21

1

2

+3VALW+5VALW

21

1

2

D15
CH751H-40_SC76

ICH_V5REF_RUN

C362

0.1U_0402_16V4Z

D16
CH751H-40_SC76

ICH_V5REF_SUS

C371

0.1U_0402_16V4Z

+1.5VS

1

C361

0.1U_0402_16V4Z

2

Place closely pin AG28 within 100mlis.

R229

1 2

0.5_0805_1%

0.1U_0402_16V4Z

+1.5VS_DMIPLLR

+1.5VS

+3VALW

C372

1 2

0_0805_5%

1

C375

2

1

2

R230

+3VS

0.1U_0402_16V4Z

+1.5VS

0.1U_0402_16V4Z

C330

0.1U_0402_16V4Z

1

C340

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

+1.5VS

C373

0.1U_0402_16V4Z

+1.5VS

C365

1U_0603_10V4Z

T47 PAD
T45 PAD

1 2
1 2

ICH_V5REF_SUS

1

C332

2

+3VS

1

C352

2

+1.5VS_DMIPLL

1

2

1

2

ICH_AA2
ICH_Y7

G10

AD17

F6

AA22
AA23
AB22
AB23
AC23
AC24
AC25
AC26
AD26
AD27
AD28

D26
D27
D28
E24
E25
E26
F23
F24
G22
G23
H22
H23

J22

J23
K22
K23
L22
L23
M22
M23
N22
N23
P22
P23
R22
R23
R24
R25
R26
T22
T23
T26
T27
T28
U22
U23
V22
V23

W22
W23

Y22
Y23

B27

AG28

AB7

AC6
AC7
AD6

AE6
AF5
AF6

AG5

AH5

AD2
AH11
AB10

AB9
AC10
AD10
AE10
AF10

AF9

AG9

AH9

E3

C1

AA2

Y7
V5

V1
W2
W7

1

C349

0.1U_0402_16V4Z

2

U3F

V5REF[1]
V5REF[2]
V5REF_Sus
Vcc1_5_B[1]

Vcc1_5_B[2]
Vcc1_5_B[3]
Vcc1_5_B[4]
Vcc1_5_B[5]
Vcc1_5_B[6]
Vcc1_5_B[7]
Vcc1_5_B[8]
Vcc1_5_B[9]
Vcc1_5_B[10]
Vcc1_5_B[11]
Vcc1_5_B[12]
Vcc1_5_B[13]
Vcc1_5_B[14]
Vcc1_5_B[15]
Vcc1_5_B[16]
Vcc1_5_B[17]
Vcc1_5_B[18]
Vcc1_5_B[19]
Vcc1_5_B[20]
Vcc1_5_B[21]
Vcc1_5_B[22]
Vcc1_5_B[23]
Vcc1_5_B[24]
Vcc1_5_B[25]
Vcc1_5_B[26]
Vcc1_5_B[27]
Vcc1_5_B[28]
Vcc1_5_B[29]
Vcc1_5_B[30]
Vcc1_5_B[31]
Vcc1_5_B[32]
Vcc1_5_B[33]
Vcc1_5_B[34]
Vcc1_5_B[35]
Vcc1_5_B[36]
Vcc1_5_B[37]
Vcc1_5_B[38]
Vcc1_5_B[39]
Vcc1_5_B[40]
Vcc1_5_B[41]
Vcc1_5_B[42]
Vcc1_5_B[43]
Vcc1_5_B[44]
Vcc1_5_B[45]
Vcc1_5_B[46]
Vcc1_5_B[47]
Vcc1_5_B[48]
Vcc1_5_B[49]
Vcc1_5_B[50]
Vcc1_5_B[51]
Vcc1_5_B[52]
Vcc1_5_B[53]

Vcc3_3[1]
VccDMIPLL
Vcc1_5_A[1]

Vcc1_5_A[2]
Vcc1_5_A[3]
Vcc1_5_A[4]
Vcc1_5_A[5]
Vcc1_5_A[6]
Vcc1_5_A[7]
Vcc1_5_A[8]
Vcc1_5_A[9]

VccSATAPLL
Vcc3_3[2]
Vcc1_5_A[10]

Vcc1_5_A[11]
Vcc1_5_A[12]
Vcc1_5_A[13]
Vcc1_5_A[14]
Vcc1_5_A[15]
Vcc1_5_A[16]
Vcc1_5_A[17]
Vcc1_5_A[18]

VccSus3_3[19]
VccUSBPLL
VccSus1_05/VccLAN1_05[1]

VccSus1_05/VccLAN1_05[2]
VccSus3_3/VccLAN3_3[1]

VccSus3_3/VccLAN3_3[2]
VccSus3_3/VccLAN3_3[3]
VccSus3_3/VccLAN3_3[4]

ICH7_BGA652~D

Vcc1_05[1]
Vcc1_05[2]
Vcc1_05[3]
Vcc1_05[4]
Vcc1_05[5]
Vcc1_05[6]
Vcc1_05[7]
Vcc1_05[8]

Vcc1_05[9]
Vcc1_05[10]
Vcc1_05[11]
Vcc1_05[12]
Vcc1_05[13]
Vcc1_05[14]
Vcc1_05[15]
Vcc1_05[16]
Vcc1_05[17]
Vcc1_05[18]
Vcc1_05[19]
Vcc1_05[20]

Vcc3_3 / VccHDA

VccSus3_3/VccSusHDA

V_CPU_IO[1]
V_CPU_IO[2]
V_CPU_IO[3]

Vcc3_3[3]
Vcc3_3[4]
Vcc3_3[5]
Vcc3_3[6]
Vcc3_3[7]
Vcc3_3[8]

Vcc3_3[9]
Vcc3_3[10]
Vcc3_3[11]

Vcc3_3[12]
Vcc3_3[13]
Vcc3_3[14]
Vcc3_3[15]
Vcc3_3[16]
Vcc3_3[17]
Vcc3_3[18]
Vcc3_3[19]
Vcc3_3[20]
Vcc3_3[21]

VccRTC
VccSus3_3[1]
VccSus3_3[2]

VccSus3_3[3]
VccSus3_3[4]
VccSus3_3[5]
VccSus3_3[6]

VccSus3_3[7]
VccSus3_3[8]
VccSus3_3[9]

VccSus3_3[10]
VccSus3_3[11]
VccSus3_3[12]
VccSus3_3[13]
VccSus3_3[14]
VccSus3_3[15]
VccSus3_3[16]
VccSus3_3[17]
VccSus3_3[18]

Vcc1_5_A[19]
Vcc1_5_A[20]

Vcc1_5_A[21]
Vcc1_5_A[22]
Vcc1_5_A[23]

Vcc1_5_A[24]

Vcc1_5_A[25]
VccSus1_05[1]
VccSus1_05[2]

VccSus1_05[3]

Vcc1_5_A[26]

Vcc1_5_A[27]

Vcc1_5_A[28]

Vcc1_5_A[29]

Vcc1_5_A[30]

L11
L12
L14
L16
L17
L18
M11
M18
P11
P18
T11
T18
U11
U18
V11
V12
V14
V16
V17
V18

U6
R7
AE23

AE26
AH26

AA7
AB12
AB20
AC16
AD13
AD18
AG12
AG15
AG19

A5
B13
B16
B7
C10
D15
F9
G11
G12
G16

W5
P7
A24

C24
D19
D22
G19

K3
K4
K5
K6
L1
L2
L3
L6
L7
M6
M7
N7

AB17
AC17

T7
F17
G17

AB8
AC8

K7
C28

G20
A1

H6
H7
J6
J7

+VCCP

0.1U_0402_16V4Z

1

C363

C357

2

1U_0603_10V4Z

1

C368

2

0.1U_0402_16V4Z

1

C386

0.1U_0402_16V4Z

2

1

C367

0.1U_0402_16V4Z

2

+1.5VS

1 2

C348 0.1U_0402_16V4Z

ICH_K7
ICH_C28

ICH_G20

+1.5VS

1

C360

0.1U_0402_16V4Z

2

1

2

+3VALW

+3VS

1

C359

0.1U_0402_16V4Z

2

1

1

C350

2

2

0.1U_0402_16V4Z

1

C376

0.1U_0402_16V4Z

2

1

C377

0.1U_0402_16V4Z

2

1

+

C351
220U_D2_4VM

2

C337

0.1U_0402_16V4Z

T46PAD
T15PAD

T43PAD

+VCCP

+3VS

+3VALW

+3VALW

C354

1 2

0.1U_0402_16V4Z

1 2

C353

0.1U_0402_16V4Z

1 2

C358

4.7U_0805_10V4Z

C369

0.1U_0402_16V4Z

+3VS

1

C356

0.1U_0402_16V4Z

2

+RTCVCC

1

1

C370

2

2

0.1U_0402_16V4Z

U3E

A4

VSS[0]

A23

VSS[1]

B1

VSS[2]

B8

VSS[3]

B11

VSS[4]

B14

VSS[5]

B17

VSS[6]

B20

VSS[7]

B26

VSS[8]

B28

VSS[9]

C2

VSS[10]

C6

VSS[11]

C27

VSS[12]

D10

VSS[13]

D13

VSS[14]

D18

VSS[15]

D21

VSS[16]

D24

VSS[17]

E1

VSS[18]

E2

VSS[19]

E4

VSS[21]

E8

VSS[22]

E15

VSS[23]

F3

VSS[24]

F4

VSS[25]

F5

VSS[26]

F12

VSS[27]

F27

VSS[28]

F28

VSS[29]

G1

VSS[30]

G2

VSS[31]

G5

VSS[32]

G6

VSS[33]

G9

VSS[34]

G14

VSS[35]

G18

VSS[36]

G21

VSS[37]

G24

VSS[38]

G25

VSS[39]

G26

VSS[40]

H3

VSS[41]

H4

VSS[42]

H5

VSS[43]

H24

VSS[44]

H27

VSS[45]

H28

VSS[46]

J1

VSS[47]

J2

VSS[48]

J5

VSS[49]

J24

VSS[50]

J25

VSS[51]

J26

VSS[52]

K24

VSS[53]

K27

VSS[54]

K28

VSS[55]

L13

VSS[56]

L15

VSS[57]

L24

VSS[58]

L25

VSS[59]

L26

VSS[60]

M3

VSS[61]

M4

VSS[62]

M5

VSS[63]

M12

VSS[64]

M13

VSS[65]

M14

VSS[66]

M15

VSS[67]

M16

VSS[68]

M17

VSS[69]

M24

VSS[70]

M27

VSS[71]

M28

VSS[72]

N1

VSS[73]

N2

VSS[74]

N5

VSS[75]

N6

VSS[76]

N11

VSS[77]

N12

VSS[78]

N13

VSS[79]

N14

VSS[80]

N15

VSS[81]

N16

VSS[82]

N17

VSS[83]

N18

VSS[84]

N24

VSS[85]

N25

VSS[86]

N26

VSS[87]

P3

VSS[88]

P4

VSS[89]

P12

VSS[90]

P13

VSS[91]

P14

VSS[92]

P15

VSS[93]

P16

VSS[94]

P17

VSS[95]

P24

VSS[96]

P27

VSS[97]

ICH7_BGA652~D

VSS[98]

VSS[99]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
VSS[159]
VSS[160]
VSS[161]
VSS[162]
VSS[163]
VSS[164]
VSS[165]
VSS[166]
VSS[167]
VSS[168]
VSS[169]
VSS[170]
VSS[171]
VSS[172]
VSS[173]
VSS[174]
VSS[175]
VSS[176]
VSS[177]
VSS[178]
VSS[179]
VSS[180]
VSS[181]
VSS[182]
VSS[183]
VSS[184]
VSS[185]
VSS[186]
VSS[187]
VSS[188]
VSS[189]
VSS[190]
VSS[191]
VSS[192]
VSS[193]
VSS[194]

P28
R1
R11
R12
R13
R14
R15
R16
R17
R18
T6
T12
T13
T14
T15
T16
T17
U4
U12
U13
U14
U15
U16
U17
U24
U25
U26
V2
V13
V15
V24
V27
V28
W6
W24
W25
W26
Y3
Y24
Y27
Y28
AA1
AA24
AA25
AA26
AB4
AB6
AB11
AB14
AB16
AB19
AB21
AB24
AB27
AB28
AC2
AC5
AC9
AC11
AD1
AD3
AD4
AD7
AD8
AD11
AD15
AD19
AD23
AE2
AE4
AE8
AE11
AE13
AE18
AE21
AE24
AE25
AF2
AF4
AF8
AF11
AF27
AF28
AG1
AG3
AG7
AG11
AG14
AG17
AG20
AG25
AH1
AH3
AH7
AH12
AH23
AH27

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

PDF created with pdfFactory Pro trial version www.pdffactory.com

2005/10/06 2006/10/06

3

Compal Secret Data

Deciphered Date

2

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

ICH7-M(4/4)

HGT30/31 LA3061

星期四二月

23, 2006

1

22 47,

0.1

5

4

3

2

1

D D

PSATA_ITX_DRX_P0<20>
PSATA_ITX_DRX_N0<20>

PSATA_IRX_DTX_N0_C<20>

PSATA_IRX_DTX_P0_C<20>

+3VS

+5VS

C C

IDERST_CD#<21>

B B

PLT_RST#<7,19,28,37>

ODD_LED#<38>

12

C230 3900P_0402_50V7K

12

C234 3900P_0402_50V7K

1 2

R151 0_0805_5%@

1 2

R170 0_0805_5%

R262 0_0402_5%@

1 2

R267 33_0402_5%

1 2

+3VS

12

R249

10K_0402_5%

ODD_LED#

PSATA_ITX_DRX_P0
PSATA_ITX_DRX_N0

PSATA_IRX_DTX_N0

PSATA_IRX_DTX_P0

INT_CD_L<29> INT_CD_R<29>

CD_AGND<29>

PD_IOW#<20>

PD_IORDY<20>

PD_IRQ<20>

PD_CS#1<20> PD_CS#3<20>

+5VS

1 2

JP9

1

GND

2

A+

3

A-

4

GND

5

B-

6

B+

7

GND

8

V33

9

V33

10

V33

11

GND

12

GND

13

GND

14

V5

15

V5

16

V5

17

GND

18

Reserved

19

GND

20

V12

21

V12

22

V12

ALLTO_C16630-122A4-L_RV

Main SATA +5V Default

PD_D[0..15]
PD_A[0..2]

PD_D7
PD_D6
PD_D5
PD_D4
PD_D3
PD_D2
PD_D1
PD_D0

PD_IOW#
PD_IORDY
PD_IRQ
PD_A1
PD_A0
PD_CS#1

PRI_CSEL

R231
470_0402_5%

JP10

2

112

4

334

6

556

8

778

10

9910

12

111112

14

131314

16

151516

18

171718

20

191920

22

212122

24

232324

26

252526

28

272728

30

292930

32

313132

34

333334

36

353536

38

373738

40

393940

42

414142

44

434344

46

454546

48

474748

50

494950

OCTEK_CDR-50DY1G

ME@

PD_D[0..15]<20>

PD_A[0..2]<20>

PD_D8
PD_D9
PD_D10
PD_D11
PD_D12
PD_D13
PD_D14
PD_D15
PD_DREQ
PD_IOR#

PD_DACK#
PDIAG#

PD_A2
PD_CS#3

12

C347 0.1U_0402_16V4Z

1

C266

C257

2

22U_1206_6.3V6M

PD_DREQ<20>
PD_IOR# <20>

PD_DACK#<20>

1 2

R244 100K_0402_5%

+5VS

+5VS +3VS

0.1U_0402_16V4Z

1

1

C256

2

2

1000P_0402_50V7K

Pleace near HD CONN

+5VS

1

C271

2

1U_0603_10V4Z

1

C258

2

0.1U_0402_16V4Z

1

C252

C246

2

22U_1206_6.3V6M

@

@

+5VS

0.1U_0402_16V4Z@

1

1

2

1000P_0402_50V7K

1

C344
1U_0603_10V4Z

2

C247

2

Pleace near HD CONN

1

2

1

C251

2

1U_0603_10V4Z@

C336
10U_0805_10V4Z

1

C245

2

0.1U_0402_16V4Z

@

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/10/06 2006/10/06

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet of

Compal Electronics, Inc.

HDD & CDROM

HGT30/31 LA3061

星期四二月

23, 2006

1

23 47,

0.1

PDF created with pdfFactory Pro trial version www.pdffactory.com

A

B

C

D

E

CARD_S1_A[0..25]

CARD_S1_D[0..15]
PCI_AD[0..31]

Power on RESET#

CLK_PCI_PCM

12

1

2

>1ms

Reset# Here

>1ms

SUSP#<18,26,33,34,35,37,43,44>

1 2

+3VS

R318 10K_0402_5%

CB@

21

D17
RB751V_SOD323@

Note: MF0 -- MF6 must
refer the data sheet for
design.

4 4

VCC

CLK

SUSPEND#

PCIRST#

3 3

Entry S3

SUSPEND#

PCIRST#

SUSPEND# will gate the PCIRST# or
GRST#, so need S3 wake up function,
SUSPEND# must be LOW ahead the PCIRST#
about 1ms.

2 2

R379

33_0402_5%@

C429

10P_0402_25V8K

1 1

@

CARD_S1_A[0..25]<25>
CARD_S1_D[0..15]<25>
PCI_AD[0..31]<19,26,27,32>

PCI_CBE#3<19,26,27,32>
PCI_CBE#2<19,26,27,32>
PCI_CBE#1<19,26,27,32>
PCI_CBE#0<19,26,27,32>

PCI_RST#<19,21,25,26,27,32,33>

PCI_FRAME#<19,26,27,32>

PCI_IRDY#<19,26,27>

PCI_TRDY#<19,26,27,32>

PCI_DEVSEL#<19,26,27>

PCI_STOP#<19,26,27>
PCI_PERR#<19,26,27>
PCI_SERR#<19,26,27>

PCI_PAR<19,26,27>

PCI_REQ2#<19>

PCI_GNT2#<19>

CLK_PCI_PCM<15>

CB_PME#<33>

PCI_AD20

1 2

R408 100_0402_5%

PCI_PIRQA#<19>

SIRQ<21,26,32,33>

PCI_CLKRUN#<21,26,27,33>

PCI_RST#<19,21,25,26,27,32,33>

CB@

PCI_CBE#3
PCI_CBE#2
PCI_CBE#1
PCI_CBE#0

CLK_PCI_PCM

PCI_PIRQA#

4.7U_0805_10V4Z

VPPD0<25>

VPPD1<25>
VCCD0#<25>
VCCD1#<25>

PCI_AD31
PCI_AD30
PCI_AD29
PCI_AD28
PCI_AD27
PCI_AD26
PCI_AD25
PCI_AD24
PCI_AD23
PCI_AD22
PCI_AD21
PCI_AD20
PCI_AD19
PCI_AD18
PCI_AD17
PCI_AD16
PCI_AD15
PCI_AD14
PCI_AD13
PCI_AD12
PCI_AD11
PCI_AD10
PCI_AD9
PCI_AD8
PCI_AD7
PCI_AD6
PCI_AD5
PCI_AD4
PCI_AD3
PCI_AD2
PCI_AD1
PCI_AD0

PCI_RST#

PCI_PCM_ID

C400

CB@

U28

3

AD31

4

AD30

5

AD29

7

AD28

8

AD27

9

AD26

10

AD25

11

AD24

15

AD23

16

AD22

17

AD21

19

AD20

23

AD19

24

AD18

25

AD17

26

AD16

38

AD15

39

AD14

40

AD13

41

AD12

43

AD11

45

AD10

46

AD9

47

AD8

49

AD7

51

AD6

52

AD5

53

AD4

54

AD3

55

AD2

56

AD1

57

AD0

12

C/BE3#

27

C/BE2#

37

C/BE1#

48

C/BE0#

20

RST#

28

FRAME#

29

IRDY#

31

TRDY#

32

DEVSEL#

33

STOP#

34

PERR#

35

SERR#

36

PAR

1

REQ#

2

GNT#

21

PCLK

59

RI_OUT#/PME#

70

SUSPEND#

13

IDSEL

60

MFUNC0

61

MFUNC1

64

MFUNC2

65

MFUNC3

67

MFUNC4

68

MFUNC5

69

MFUNC6

66

VCC/GRST#

1

1

C402

0.1U_0402_16V4Z

2

2

CB@

72

74

VPPD071VPPD1

VCCD0#73VCCD1#

PQFP 144

22.2 X 22.2 X 1.60

GND1

GND2

6

22

+3VS

44

GND3

42

58

18

126

VCCP1

VCCP0

GND4

GND5

GND6

78

94

114

+S1_VCC

1

C456

0.1U_0402_16V4Z

2

CB@

90

102

122

138

VCC2

VCC1

VCCSK1

VCCSK0

RSVD/D14

GND7

GND8

84

100

130

1

CB@

C436

0.1U_0402_16V4Z

2

+3VS

14

30

50

86

VCC6

VCC5

VCC4

VCC3

CAD15/IOWR#

CAD13/IORD#

CAD10/CE2#

CC/BE3#/REG#

CC/BE2#/A12
CC/BE0#/CE1#
CRST#/RESET

CFRAME#/A23

CTRDY#/A22

CDEVSEL#/A21

CSTOP#/A20
CPERR#/A14

CSERR#/WAIT#

CREQ#/INPACK#

CSTSCHG/BVD1

CCLKRUN#/WP

CBLOCK#/A19
CINT#/READY

CAUDIO/BVD2

CCD2#/CD2#

CCD1#/CD1#

RSVD/A18

RSVD/D2

CB1410_LQFP144

CB@

143

+3VS

0.1U_0402_16V4Z

63

VCCI

VCC7

CAD31/D10

CAD30/D9
CAD29/D1
CAD28/D8
CAD27/D0

CAD26/A0
CAD25/A1
CAD24/A2
CAD23/A3
CAD22/A4
CAD21/A5
CAD20/A6

CAD19/A25

CAD18/A7
CAD17/A24
CAD16/A17

CAD14/A9
CAD12/A11

CAD11/OE#

CAD9/A10

CAD8/D15

CAD7/D7

CAD6/D13

CAD5/D6

CAD4/D12

CAD3/D5

CAD2/D11

CAD1/D4
CAD0/D3

CC/BE1#/A8

CIRDY#/A15

CPAR/A13

CGNT#/WE#

CCLK/A16

SPKOUT

CVS2/VS2#
CVS1/VS1#

1 2

C403

CB@

144
142
141
140
139
129
128
127
124
121
120
118
116
115
113
98
96
97
93
95
92
91
89
87
85
82
83
80
81
77
79
76

125
112
99
88

119
111
110
109
107
105
104
133
101
123
106
108

135
136

103
132
62

134
137

75
117
131

C455

0.1U_0402_16V4Z

CARD_S1_D10
CARD_S1_D9
CARD_S1_D1
CARD_S1_D8
CARD_S1_D0
CARD_S1_A0
CARD_S1_A1
CARD_S1_A2
CARD_S1_A3
CARD_S1_A4
CARD_S1_A5
CARD_S1_A6
CARD_S1_A25
CARD_S1_A7
CARD_S1_A24
CARD_S1_A17
CARD_S1_IOWR#
CARD_S1_A9
CARD_S1_IORD#
CARD_S1_A11
CARD_S1_OE#
CARD_S1_CE2#
CARD_S1_A10
CARD_S1_D15
CARD_S1_D7
CARD_S1_D13
CARD_S1_D6
CARD_S1_D12
CARD_S1_D5
CARD_S1_D11
CARD_S1_D4
CARD_S1_D3

CARD_S1_REG#
CARD_S1_A12
CARD_S1_A8
CARD_S1_CE1#

CARD_S1_RST
CARD_S1_A23
CARD_S1_A15
CARD_S1_A22
CARD_S1_A21
CARD_S1_A20
CARD_S1_A14
CARD_S1_WAIT#
CARD_S1_A13
CARD_S1_INPACK#
CARD_S1_WE#
CARD_A16_CLK

CARD_S1_BVD1
CARD_S1_WP

CARD_S1_A19
CARD_S1_RDY#
PCM_SPK#

CARD_S1_BVD2
CARD_S1_CD2#

CARD_S1_CD1#
CARD_S1_VS2
CARD_S1_VS1

CARD_S1_D2
CARD_S1_A18
CARD_S1_D14

+3VS

1

2

CB@

1

CB@

2

C445

0.1U_0402_16V4Z

C431

0.1U_0402_16V4Z

1

CB@

2

C404

0.1U_0402_16V4Z

1

2

CB@

C438

0.1U_0402_16V4Z

1

CB@

2

1

CB@

2

C421

0.1U_0402_16V4Z

ENE CB1410 just have one vcc plane internal,
if want S3 wake-up function(PME#),then at S3
status must keep all Vcc +3V. That is different
with TI 1410 and O2-Micro 6912, just keep the
VCCI pin +3V, the other vcc can use +3VS.

CARD_S1_IOWR#<25>
CARD_S1_IORD#<25>
CARD_S1_OE#<25>

CARD_S1_CE2#<25>

CARD_S1_REG#<25>

CARD_S1_CE1#<25>
CARD_S1_RST<25>

CARD_S1_WAIT#<25>
CARD_S1_INPACK#<25>

CARD_S1_WE#<25>

1 2

R420 33_0402_5% CB@

CARD_S1_BVD1<25>
CARD_S1_WP<25>

CARD_S1_RDY#<25>
PCM_SPK#<29>

CARD_S1_BVD2<25>
CARD_S1_CD2#<25>

CARD_S1_CD1#<25>
CARD_S1_VS2<25>
CARD_S1_VS1<25>

CARD_S1_A16

C454

0.1U_0402_16V4Z

1

CB@

2

Security Classification

Issued Date

PROPRIETARY NOTE

A

B

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

PDF created with pdfFactory Pro trial version www.pdffactory.com

2005/10/06 2006/10/06

C

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

CB ENE1410(One Solt)

Size Document Number Rev

Custom

HGT30/31 LA3061

,

星期四G月

D

Date: Sheet of

23, 2006

E

24 47

0.1

A

B

C

D

E

PCMCIA Power Controller

CARD_S1_A[0..25]<24>

+S1_VCC

U5

1 1

+5VS

1

C193
10U_1206_10V4Z

2

CB@

+3VS

1

C194
10U_1206_10V4Z

2

CB@

2 2

0.1U_0402_16V4Z CB@

0.1U_0402_16V4Z

C198

C197

1

2

1

2

+5VS

+3VS

CB@

9

5
6

3
4

12V

5V
5V

3.3V

3.3V

CB@

GND

7

VCC
VCC
VCC

VPP

VCCD0
VCCD1

VPPD0
VPPD1

OC

SHDN

CP-2211_SSOP16

16

13
12
11

10

1
2
15
14

8

PCI_RST#

1

C210

0.1U_0402_16V4Z

2

CB@

+S1_VPP

1

C209

CB@

0.1U_0402_16V4Z

2

VCCD0# <24>
VCCD1# <24>
VPPD0 <24>
VPPD1 <24>

PCI_RST#<19,21,24,26,27,32,33>

CARD_S1_D[0..15]<24>

+S1_VPP

1

C241

CB@

2

0.01U_0402_25V4Z

CARD_S1_CE1#<24>

CARD_S1_OE#<24>

CARD_S1_WE#<24>

CARD_S1_RDY#<24>

CARD_S1_WP<24>

CARD_S1_A[0..25]
CARD_S1_D[0..15]

CARD_S1_D3
CARD_S1_D4
CARD_S1_D5
CARD_S1_D6
CARD_S1_D7
CARD_S1_CE1#
CARD_S1_A10
CARD_S1_OE#
CARD_S1_A11
CARD_S1_A9
CARD_S1_A8
CARD_S1_A13
CARD_S1_A14
CARD_S1_WE#

+S1_VCC +S1_VCC
+S1_VPP

1

C215

CB@

2

4.7U_0805_10V4Z

CARD_S1_RDY#

CARD_S1_A16
CARD_S1_A15
CARD_S1_A12
CARD_S1_A7
CARD_S1_A6
CARD_S1_A5
CARD_S1_A4
CARD_S1_A3
CARD_S1_A2
CARD_S1_A1
CARD_S1_A0
CARD_S1_D0
CARD_S1_D1
CARD_S1_D2

CARD_S1_WP

1

C243
1U_0805_25V4Z

2

CB@

JP11

1

GND
D3
D4
D5
D6
D7
CE1#
A10
OE#
A11
A9
A8
A13
A14
WE#
IREQ#
VCC
VPP1
A16
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
D0
D1
D2
IOIS16#
GND

GND
GND
GND
GND
GND
GND
GND
GND

ME@

GND

CD1#

CE2#
VS1#

IORD#

IOWR#

VCC

VPP2

VS2#

RESET

WAIT#

INPACK#

REG#

SPKR#

STSCHG#

CD2#

GND
GND

GND
GND
GND
GND
GND
GND
GND

HOLE1
HOLE2
HOLE3
HOLE4

D11
D12
D13
D14
D15

A17
A18
A19
A20
A21

A22
A23
A24
A25

D8
D9

D10

2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34

69
70
71
72
73
74
75
76

FOX_WZ21131-G2-P4_LT

35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68

77
78
79
80
81
82
83
84

87
88
89
90

CARD_S1_CD1#

CARD_S1_D11
CARD_S1_D12
CARD_S1_D13
CARD_S1_D14
CARD_S1_D15
CARD_S1_CE2#
CARD_S1_VS1

CARD_S1_IORD#

CARD_S1_IOWR#

CARD_S1_A17
CARD_S1_A18
CARD_S1_A19
CARD_S1_A20
CARD_S1_A21

CARD_S1_A22
CARD_S1_A23
CARD_S1_A24
CARD_S1_A25
CARD_S1_VS2
CARD_S1_RST

CARD_S1_WAIT#

CARD_S1_INPACK#

CARD_S1_REG#
CARD_S1_BVD2
CARD_S1_BVD1

CARD_S1_D8
CARD_S1_D9

CARD_S1_D10

CARD_S1_CD2#

C239

0.1U_0402_16V4Z

CB@

+S1_VPP

+S1_VCC

1

2

CARD_S1_CD1#<24>

CARD_S1_CE2#<24>
CARD_S1_VS1<24>

CARD_S1_IORD#<24>
CARD_S1_IOWR#<24>

CARD_S1_VS2<24>
CARD_S1_RST<24>
CARD_S1_WAIT#<24>
CARD_S1_INPACK#<24>
CARD_S1_REG#<24>
CARD_S1_BVD2<24>
CARD_S1_BVD1<24>

CARD_S1_CD2#<24>

1

1

2

10U_1206_10V4Z

CB@

C216

C238

0.01U_0402_25V4Z

2

CB@

3 3

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2005/10/06 2006/10/06

C

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

CardBus Socket

Size Document Number Rev

Custom

HGT30/31 LA3061

,

星期四G月

D

Date: Sheet of

23, 2006

E

0.1

25 47

PDF created with pdfFactory Pro trial version www.pdffactory.com

5

1

2

1 2

1 2

125
126
127

11
12
14
15
17
18
19
36
37
38
39
40
42
43
44
46
47
48
49
50
51
52
53

21
35
45

33
23
25
24
29
26

30
31

124
123

121
119

71

117

70

115
116

69
66

111
107
103
102

99

97

C453

270 P_0402_50V7K

R439

56. 2 _0603_1%

R437

56.2_0603_1%

U34

AD31
AD30
AD29

1

AD28

2

AD27

3

AD26

5

AD25

6

AD24

9

AD23
AD22
AD21
AD20
AD19
AD18
AD17
AD16
AD15
AD14
AD13
AD12
AD11
AD10
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0

7

C/BE3#
C/BE2#
C/BE1#
C/BE0#

PAR
FRAME#
TRDY#
IRDY#
STOP#
DEVSEL#

8

IDSEL
PERR#
SERR#

REQ#
GNT#

PCICLK
PCIRST#
GBRST#
CLKRUN#
PME#

INTA#
INTB#

HWSPND#
TEST

AGND
AGND
AGND
AGND
AGND

NC

R5C832_TQFP128~D

12

R421

Z3008

R440

1 2

R438

1 2

56. 2 _0603_1%

5.1 K _0603_1%

56. 2 _0603_1%

2

1

PCI_AD[0..31]<19,24,27,32>

D D

PCI_CBE#3<19,24,27,32>
PCI_CBE#2<19,24,27,32>
PCI_CBE#1<19,24,27,32>
PCI_CBE#0<19,24,27,32>

PCI_PAR<19,24,27>
PCI_FRAME#<19,24,27,32>

C C

B B

PCI_AD22 CBS_IDSEL

1 2

R455 100_0402_5%

PCI_CLKRUN#<21,24,27,33>

SUSP#<18,24,33,34,35,37,43,44>

PCI_TRDY#<19,24,27,32>
PCI_IRDY#<19,24,27>
PCI_STOP#<19,24,27>
PCI_DEVSEL#<19,24,27>

PCI_PERR#<19,24,27>
PCI_SERR#<19,24,27>

PCI_REQ0#<19>
PCI_GNT0#<19>

CLK_PCI_1394<15>

PCI_RST#<19,21,24,25,27,32,33>

R436 10K_0402_5%

1 2

R435 0_0402_5%

1 2

R5_PME#<33>
PCI_PIRQG#<19>
PCI_PIRQH#<19>

1 2

+3VS

R464 10K_0402_5%

1 2

R463 0_0402_5%

@

@

PCI_AD31
PCI_AD30
PCI_AD29
PCI_AD28
PCI_AD27
PCI_AD26
PCI_AD25
PCI_AD24
PCI_AD23
PCI_AD22
PCI_AD21
PCI_AD20
PCI_AD19
PCI_AD18
PCI_AD17
PCI_AD16
PCI_AD15
PCI_AD14
PCI_AD13
PCI_AD12
PCI_AD11
PCI_AD10
PCI_AD9
PCI_AD8
PCI_AD7
PCI_AD6
PCI_AD5
PCI_AD4
PCI_AD3
PCI_AD2
PCI_AD1
PCI_AD0

PCI_CBE#3
PCI_CBE#2
PCI_CBE#1
PCI_CBE#0

PCI_PAR
PCI_FRAME#
PCI_TRDY#
PCI_IRDY#
PCI_STOP#
PCI_DEVSEL#

PCI_PERR#
PCI_SERR#

PCI_REQ0#
PCI_GNT0#

CBS_GRST#

R5_PME#

Layout Note: Place close to R5C832

CLK_PCI_1394

12

R444

@

10_ 0402_5%

2

A A

C463

1

@

4.7P_04 02_50V8C

+3VS

12

R462

CBS_GRST#

1

C493
1U_0603_10V4Z

2

IEEE1394_TPBN0
IEEE1394_TPBP0

10 0K_0402_5%

5

IEEE1394_TPAN0
IEEE1394_TPAP0

IEEE1394_TPBIAS0

R5C832

2

C459

C462

0.01U_0402_25V4Z

1

4

VCC_PCI3V
VCC_PCI3V
VCC_PCI3V
VCC_PCI3V
VCC_PCI3V
VCC_PCI3V

VCC_RIN

VCC_ROUT
VCC_ROUT
VCC_ROUT
VCC_ROUT
VCC_ROUT

VCC_3V

VCC_MD3V

AVCC_PHY3V
AVCC_PHY3V
AVCC_PHY3V
AVCC_PHY3V

TPBIAS0

TPAP0
TPAN0

TPBP0
TPBN0

MDIO00
MDIO01
MDIO02
MDIO03
MDIO04
MDIO05
MDIO06
MDIO07
MDIO08
MDIO09
MDIO10
MDIO11
MDIO12
MDIO13
MDIO14
MDIO15
MDIO16
MDIO17
MDIO18
MDIO19

MSEN
XDEN

XI

XO

FIL0
REXT
VREF

UDIO0/SERIRQ#

UDIO1
UDIO2
UDIO3
UDIO4
UDIO5

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

Layout Note: Shield GND for
IEEE1394_TPA and TPB

0.3 3 U_06 03_16V4Z

4

10
20
27
32
41
128

61
16

34
64
114
120

67
86

+3V_PHY

98
106
110
112

IEEE1394_TPBIAS0

113

IEEE1394_TPAP0

109

IEEE1394_TPAN0

108

IEEE1394_TPBP0

105

IEEE1394_TPBN0

104

SDCD#_XDCD0#

80

MSCD#_XDCD1

79
78

SDWP#_XDRB#

77

SDPWR0_MSPWR_XDPWR

76
75
74

TP_MSEXTCK

73

SDCMD_MSBS

88

SDCLK_MSCLK

84

SDDATA0_MSDATA0

82

SDDATA1_MSDATA1

81

SDDATA2_MSDATA2

93

SDDATA3_MSDATA3

90
91
89
92
87
85
83

MSEN

58

XDEN

55

R5C832XI

94

R5C832XO

95
96

101
100

SIRQ

72

TP_UDIO1

60

TP_UDIO2

56

UDIO3

65

UDIO4

59

UDIO5

57
4

13
22
28
54
62
63
68
118
122

+3VS

0.01U_0402_25V4Z

+VCC_4IN1

1

C521

2

10U_ 1206_6.3V6M

JP13

1
2
3
4

SUYIN_020115FB004S512ZL

ME@

TPB­TPB+
TPA­TPA+

5

GND

6

GND

7

GND

8

GND

1

1

C468

C506

2

2

10U_0805_6.3V6M

0.01U_0402_25V4Z

SDCD#_XDCD0#<38>
MSCD#_XDCD1<38>

SDWP#_XDRB#<38>

SDCMD_MSBS<38>
SDCLK_MSCLK<38>

SDDATA0_MSDATA0<38>

SDDATA3_MSDATA3<38>

1 2

SIRQ <21,24,32,33>

T49PAD
T48PAD

0.01U_0402_25V4Z

Layout Note: Shield GND for
CBS_CCLK_INTERNAL and CBS_CCLK

1

C437

2

0.1 U _040 2_16V4Z

SDPWR0_MSPWR_XDPWR

3

1

C486

2

C471

0.01U_0402_25V4Z

+3VS

1

C505

2

10U_0805_6.3V6M

2

C461

1

+3VS

0.0 1 U_04 02_25V4Z

1

C491

2

1 2

BLM21A601SPT_0805

16P_0603_50V8J

16P_0603_50V8J

0.4 7 U_06 03_16V4Z

C516

L18

C481

1 2

C473

1 2

1

C515

2

0.4 7 U_06 03_16V4Z

1 2

1

1

C464

C460

2

2

0.01U_ 0 402_25V4Z

+3VS

Layout Note: Place close to R5C832
and Shield GND for SDCLK_MSCLK

R441

10K_ 0402_5%

1 2

2

1

2

0.0 1 U_04 02_25V4Z

1

C465

2

R5C832XI

X2

24.576MHz_16P_1BG24576CKIA

R5C832XO

1

1

C489

C507

2

2

0.1 U _040 2_16V4Z

1

1

C470

C469

2

2

0.1 U _040 2_16V4Z

22 U_ 08 05_ 6.3V6 M

Layout Note: Place close to R5C832
and Shield GND for SD_CLK

40mil

+3VS

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

U35

3

VIN

4

VIN/CE

2

GND

RT9701CB_SOT25

1

C494

2

0.1 U_0402_16V4Z

+VCC_4IN1

1

VOUT

5

VOUT

12

1

R483

C517

2

150K_0402_5%

1U_0 603_10V4Z

2

1

C522

2

0.0 1 U_04 02_25V4Z

+3V_PHY

1

C466

2

0.1 U _040 2_16V4Z
10 00 P_ 0402_50V7 K

SDDATA1_MSDATA1

SDDATA2_MSDATA2

+5VS

1 2

R456 10K_0402_5%

10U_ 0805_6.3V6M

1

C467

2

100 0P_0402_50V7K

SDCD#_XDCD0#

2N7002_SOT23

1

SD,MMC,MS,XD muti-function pin define

MDIO
PIN Name
MDIO00

MDIO01
MDIO02
MDIO03
MDIO04
MDIO05
MDIO06
MDIO07
MDIO08
MDIO09 SDCCLK
MDIO10
MDIO11
MDIO12
MDIO13
MDIO14
MDIO15
MDIO16
MDIO17
MDIO18
MDIO19

Function set pin define

Pull-up

SD Card
PIN Name
SDCD#

SDWP#
SDPWR0
SDPWR1
SDLED#

SDCCMD

SDCDAT0
SDCDAT1
SDCDAT2
SDCDAT3

MMC Card
PIN Name
MMCCD#

MMCPWR

MMCLED#

MMCCMD
MMCCLK
MMCDAT

MSEN XDENUDIO3 UDIO4

Pull-upPull-up Enable

Pull-up

R474 10K_0402_5%

MSEN
UDIO3
UDIO4
UDIO5

XDEN

1 2

R468 10K_0402_5%

1 2

R475 10K_0402_5%

1 2

R473 100K_0402_5%

1 2

R471 10K_0402_5%

1 2

MS Card
PIN Name

MSCD#

MSWR

MSLED#
MSEXTCK
MSBS
MSCCLK
MSCDAT0
MSCDAT1
MSCDAT2
MSCDAT3

Function

SD,XD,MS,MMC Card

+3VS

Solve MS Duo Adaptor short problem

R705 0_0402_5% @

1 2

Q33

D

S

2N7002_SOT23

1 3

G

2

R706 0_0402_5% @

1 2

D

1 3

G

2

13

D

2

G

S

Q34

@

Title

Size Document Number Rev

星期四二月

Date: Sheet of

SDDATA1

Q35
2N7002_SOT23

S

SDDATA2

Compal Electronics, Inc.

1394+3 in 1 Card

HGT30/31 LA3061

23, 2006

1

SDDATA1<38>

SDDATA2<38>

26 47,

XD Card
PIN Name
XDCD0#

XDCD1#
XDCE#
XDR/B#
XDPWR
XDWP#
XDLED#

XDWE#
XDRE#
XDCDAT0
XDCDAT1
XDCDAT2
XDCDAT3
XDCDAT4
XDCDAT5
XDCDAT6
XDCDAT7
XDCLE
XDALE

0.1

PDF created with pdfFactory Pro trial version www.pdffactory.com

5

+3V_LAN

C385
1U_0603_10V4Z

CTRL25

1

2SB1188_SC62

U24

104

AD0

103

AD1

102

AD2

98

AD3

97

AD4

96

AD5

95

AD6

93

AD7

90

AD8

89

AD9

87

AD10

86

AD11

85

AD12

83

AD13

82

AD14

79

AD15

59

AD16

58

AD17

57

AD18

55

AD19

53

AD20

50

AD21

49

AD22

47

AD23

43

AD24

42

AD25

40

AD26

39

AD27

37

AD28

36

AD29

34

AD30

33

AD31

92

C/BE#0

77

C/BE#1

60

C/BE#2

44

C/BE#3

46

IDSEL

76

PAR

61

FRAME#

63

IRDY#

67

TRDY#

68

DEVSEL#

69

STOP#

70

PERR#

75

SERR#

30

REQ#

29

GNT#

25

INTA#

31

PME#

27

RST#

28

CLK

65

CLKRUN#

4

GND/VSS

17

GND/VSS

128

GND/VSS

21

GND/VSSPST

38

GND/VSSPST

51

GND/VSSPST

66

GND/VSSPST

81

GND/VSSPST

91

GND/VSSPST

101

GND/VSSPST

119

GND/VSSPST

35

GND

52

GND

80

GND

100

GND

RTL8110SCL_LQFP128

GIGA@

12

Q27

2 3

C433

22U_A_4VM

NC/SMBDATA

PCI I/F

Power

U24

8100CL

100@

D D

C C

B B

A A

R403

5.6K_0603_1%

100@

PCI_AD[0..31]<19,24,26,32>

PCI_CBE#0<19,24,26,32>
PCI_CBE#1<19,24,26,32>
PCI_CBE#2<19,24,26,32>
PCI_CBE#3<19,24,26,32>

PCI_AD17 LAN_IDSEL

PCI_PAR<19,24,26>

PCI_FRAME#<19,24,26,32>

PCI_IRDY#<19,24,26>

PCI_TRDY#<19,24,26,32>

PCI_DEVSEL#<19,24,26>

PCI_STOP#<19,24,26>

PCI_PERR#<19,24,26>
PCI_SERR#<19,24,26>

PCI_REQ3#<19>

PCI_GNT3#<19>

PCI_PIRQF#<19>

LAN_PME#<33>

PCI_RST#

33>

CLK_PCI_LAN<15>

PCI_CLKRUN#<21,24,26,33>

CLK_PCI_LAN

12

R316

10_0402_5%

@

1

C397
10P_0402_25V8K

@

2

PCI_AD[0..31]

PCI_AD0
PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD6
PCI_AD7
PCI_AD8
PCI_AD9
PCI_AD10
PCI_AD11
PCI_AD12
PCI_AD13
PCI_AD14
PCI_AD15
PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20
PCI_AD21
PCI_AD22
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30
PCI_AD31

PCI_CBE#0
PCI_CBE#1
PCI_CBE#2
PCI_CBE#3

1 2

R302 100_0402_5%

CLK_PCI_LAN

5

1 2

R498 0_0402_5%

1 2

R499 0_0402_5%

@

+2.5V_LAN

1

+

2

EEDO

AUX/EEDI

EESK

EECS

LED0
LED1
LED2

NC/LED3

TXD+/MDI0+

TXD-/MDI0-

RXIN+/MDI1+

RXIN-/MDI1-

NC/MDI2+

NC/MDI2-

NC/MDI3+

NC/MDI3-

LWAKE

ISOLATE#

RTSET

NC/SMBCLK

NC/M66EN

NC/AVDDH

AVDDH

NC/HSDAC+

NC/HG

NC/LG2

VDD12A

NC/VSS
NC/VSS

NC/GND
NC/GND
NC/GND
NC/GND
NC/GND
NC/GND

LAN I/F

CTRL25
CTRL12

VDD33

VDD33
VDD33
VDD33
VDD33
VDD33
VDD33

AVDDL
AVDDL
AVDDL
AVDDL

VDD12
VDD12
VDD12
VDD12

NC/VDD12
NC/VDD12
NC/VDD12
NC/VDD12
NC/VDD12

+3VALW

1

C393

2

108
109
111
106

117
115
114
113

1
2
5
6

14
15
18
19

121

X1

122

X2

105
23
127
72
74

88
10

120
11

123
124
126

9
13

22
48
62
73
112
118

8
125
26

41
56
71
84
94
107

3
7
20
16

32
54
78
99

24
45
64
110
116

12

NC

+3VS

0.1U_0402_16V4Z

LAN_EEDO
LAN_EEDI
LAN_EECLK
LAN_EECS

TXD+/MDI0+
TXD-/MDI0­RXIN+/MDI1+
RXIN-/MDI1-

NC/MDI2+
NC/MDI2­NC/MDI3+
NC/MDI3-

LAN_X1
LAN_X2

ISOLATE#

RTSET

5.6K for 8100CL

2.49K for 8110S(B)

R354

DVDD_A

CTRL25
CTRL12

GIGA@

0.1U_0402_16V4Z

V_12P

1

C414

0.1U_0402_16V4Z

2

4

+3V_LAN

2SB1188_SC62GIGA@

CTRL12

1

Q21

R400 3.6K_0402_5%

1 2

U31

4

DO

3

DI

2

SK

1

CS

R319 1K_0402_5%

1 2

R317 15K_0402_5%

1 2

R403 2.49K_0603_1%

1 2

0_0402_5%

1 2

1

2

C378

0.1U_0402_16V4ZGIGA@

C394

0.1U_0402_16V4Z

C409

0.1U_0402_16V4Z

C405

0.1U_0402_16V4Z

2

C380

1

R350

1 2

R351

1 2

0.1U_0402_16V4ZGIGA@

R301

1

C441

2

0_0402_5%GIGA@

1

2

1

2

1

2

2

0.1U_0402_16V4ZGIGA@

1

0_0402_5% 100@
0_0402_5%GIGA@

+AVDDH

12

GIGA@

1

2

1

2

1

2

4

2 3

GIGA@

C374

22U_A_4VM

5

GND

6

NC

7

NC

8

VCC

AT93C46-10SU-2.7_SO8

GIGA@

1 2

1

C420

0.1U_0402_16V4ZGIGA@

2

+1.2V_LAN

C381

0.1U_0402_16V4Z

C425

0.1U_0402_16V4Z

C427

0.1U_0402_16V4Z

GIGA@

C383

+2.5V_LAN

+AVDDH

+1.2V_LAN

1

1

+

C379

2

2

+3V_LAN

1

2

25MHZ_20P_1BG25000CK1A

1

C442
22P_0402_50V8J

2

+3VS

R418 0_0805_5%GIGA@

1

C406

0.1U_0402_16V4Z

2

1

C428

0.1U_0402_16V4Z

2

1

C395

0.1U_0402_16V4Z

2

2

C439

1

0.1U_0402_16V4Z

3

0.1U_0402_16V4ZGIGA@

C410 0.1U_0402_16V4Z

+3VALW

Y3

LAN_X2LAN_X1

1 2

+3V_LAN

1

C440

0.1U_0402_16V4Z

2

+DVDD

1

C382

0.1U_0402_16V4Z

2

2

C444

1

Issued Date

1

2

AVDDL

+DVDD

3

C443
22P_0402_50V8J

+3V_LAN

1

C423

0.1U_0402_16V4Z

2

R422

R376
R303

R306

100@

+1.2V_LAN

2

C407

0.1U_0402_16V4ZGIGA@

1

2005/10/06 2006/10/06

GIGA@

0.1U_0402_16V4Z

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

12

12

12

12

1 2

100@

1 2

1 2
1 2

1 2

+2.5V_LAN

@

1 2

C398

0.01U_0402_25V4Z

GIGA@

C396

0.01U_0402_25V4Z

GIGA@

C418

0.01U_0402_25V4Z

GIGA@

C408

0.01U_0402_25V4Z

GIGA@

0.1U_0402_16V4Z

C401

0_0805_5%100@
0_0805_5%GIGA@

0_0805_5%GIGA@

0_0805_5%

Compal Secret Data

R734
0_0402_5%

TXD-/MDI0-

RXIN+/MDI1+

RXIN-/MDI1-

NC/MDI2+
NC/MDI2- MDO2-

NC/MDI3+
NC/MDI3-

TXD+/MDI0+
TXD-/MDI0-

RXIN+/MDI1+
RXIN-/MDI1-

+3V_LAN

+2.5V_LAN
+1.2V_LAN

+2.5V_LAN

Deciphered Date

U23

12
11
10

9
8
7

5
4

3
2
1

U22

TD-8TX-

7

TD+

6

CT

3

CT

2

RD-

1

RD+

NS0013_16P

100@

2

TD4-

MX4-

TD4+

MX4+

TCT4

MCT4

TD3-

MX3-

TD3+

MX3+

TCT3

MCT3

TD2-6MX2­TD2+

MX2+

TCT2

MCT2

TD1-

MX1-

TD1+

MX1+

TCT1

MCT1

0.5u_24HST1041A-2GIGA@

TX+

CT

CT

RX-

RX+

2

MDO0+TXD+/MDI0+

13

MDO0-

14
15

MDO1+

16

MDO1-

17

MCT1

18

MDO2+

19
20
21

MDO3+

22

MDO3-

23
24

use 24ST1041A-4

use 24ST1041A-4

MDO0+

9

MDO0-

10

MCT0

11

MCT1

14

MDO1+

15

MDO1-

16

1

MDO0+ <38>

MDO0- <38>

75_0402_5%

MDO1+ <38>

MDO1- <38>

75_0402_5%

MDO2+ <38>

MDO2- <38>

75_0402_5% GIGA@

MDO3+ <38>

MDO3- <38>

75_0402_5% GIGA@

TXD+/MDI0+

TXD-/MDI0-

RXIN+/MDI1+

RXIN-/MDI1-

49.9_0402_1%@

NC/MDI3+
NC/MDI3-

49.9_0402_1%@

49.9_0402_1%@

NC/MDI2+
NC/MDI2-

49.9_0402_1%@

49.9_0402_1%100@

49.9_0402_1% 100@

49.9_0402_1% 100@

49.9_0402_1%100@

RJ45_PRMCT0

R348

12

R325

12

R320

12

R322

12

R324

12
12

0.01U_0402_25V4Z

R321

R333

12
12

0.01U_0402_25V4Z

R329

R380

12
12

R375

0.01U_0402_25V4Z

R369

12
12

0.01U_0402_25V4Z

R365

C412

C415

C430

100@

C424

100@

RJ45_PR<38>

12

@

12

@

12

12

near LAN controller

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

LAN CONTROLLER

HGT30/31 LA3061

星期四二月

23, 2006

1

27 47,

0.1

PDF created with pdfFactory Pro trial version www.pdffactory.com

A

B

C

D

E

Mini-Express Card(Slot 1-WLAN)

ICH_PCIE_WAKE#<21,37>

BT_AVTIVE

1 1

2 2

ICH_SDOUT_MDC<20>
ICH_SYNC_MDC<20>

ICH_AC_SDIN1<20>

ICH_RST_MDC#<20>

KILL_MDC#<21>

3 3

WLAN_AVTIVE

CLKREQ_MCARD#<15>

CLK_PCIE_MCARD#<15>
CLK_PCIE_MCARD<15>

PCIE_RXN2<21>
PCIE_RXP2<21>

PCIE_TXN2<21>
PCIE_TXP2<21>

33_0402_5%

1 2

R107

R496 0_0402_5%

D23

2
3

DAP202U_SOT323@

R480 0_0402_5%@
R479 0_0402_5%

CLK_PCIE_MCARD#
CLK_PCIE_MCARD

AZ_SYNC
AZ_SDIN3

1

12

+5VS

@

+3VALW

12

13

12
12

12

R495
10K_0402_1%

@

R108
10K_0402_1%

BT_OFF

JP16

1

1

3

3

5

5

7

7

9

9

11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51

53

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

GND1

GND2

FOX_AS0B226-S56N-7F

MDC CONN.

JP17

1

1

3

3

5

5

7

7

9

9

11

11

131314141515161617171818191920

2

2

4

4

6

6

8

8

10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

54

R729 0_0402_5%
R730 0_0402_5%@

2

2

4

4

6

6

8

8

10

10

12

12

ACES_88012-1207

ME@

20

PLT_RST#

ICH_SMBCLK

ICH_SMBDATA

WIRELESS_LED#

1 2

WL_OFF#<33>
PLT_RST#<7,19,23,37>

12
12

ICH_SMBCLK<15,21,37>
ICH_SMBDATA<15,21,37>

C495

1U_0805_25V4Z

+3VALW

+3VALW
+3VS

WIRELESS_LED#<37>

11/20

ICH_BITCLK_MDC<20>

1

C498

2

+3VS
+1.5VS

1

C499

2

0.1U_0402_16V4Z

0.1U_ 0402 _16V 4Z

BT MODULE CONN

C701 0.1U_0402_16V4Z

12

R309
10K_0402_5%

@

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

+3VS

AO3413_SOT23

USB20_N1<21>
USB20_P1<21>

Issued Date

Q22

S

BTON_LED
BT_AVTIVE
WLAN_AVTIVE

C

+3VS_BT

G

2

USB20_N1
USB20_P1

D

13

C164

12

0.1U_0402_16V4Z

JP38

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

GND1

10

GND2

MOLEX_53780-0870

ME@

2005/10/06 2006/10/06

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

D

Date: Sheet of

Compal Electronics, Inc.

Mini Card / MDC CONN

HGT30/31 LA3061

星期四二月

23, 2006

E

28 47,

0.1

BTONLED<37>

2

DTC124EK_SC59

B

BT_OFF#<33>

4 4

A

BTONLED

Q23

Q9
DTC124EK_SC59

13

1

2

2

PDF created with pdfFactory Pro trial version www.pdffactory.com

A

+VDDA

12

R153
10K_0402_1%

C255

12

12

2

12

C

B

E

1U_0603_10V4Z

R159
10K_0402_1%

1 2

R158 20K_0402_5%

1

Q12
2SC2411K_SC59

3

D4

RB751V_SOD323

2 1

1 1

BEEP#<33>

0.1U_0402_16V4Z@

PCM_SPK#<24>

0.1U_0402_16V4Z@

SB_SPKR<21>

C477

C472

C263

1

2

1

2

1U_0603_10V4Z

1 2

12

1U_0603_10V4Z

C253

12

1 2

1U_0603_10V4Z

C254

1 2

12

10K_0402_5%@

R168

560_0402_5%

R160

560_0402_5%

R161

560_0402_5%

R171

B

C487 1U_0603_10V4Z

MONO_IN1 MONO_IN

12

R167

1 2

10K_0402_5%

10U_0805_10V4Z

C

+5VS +5VAMP

L22

1 2

KC FBM-L11-201209-221LMAT_0805

L21

1 2

KC FBM-L11-201209-221LMAT_0805

1

C490

2

60mil

C482

10U_1206_10V4Z

D

E

AC97 Codec

28.7K for Module Design (VDDA = 4.702)

U33

4

VIN

2

SENSE or ADJ

1

2

DELAY
ERROR7CNOISE

8

SD

SI9182DH-AD_MSOP8

VOUT

GND

5
6
1
3

1

C476

2

0.1U_0402_16V4Z

40mil

R449
150K_0603_1%

1 2
12

R450
51K_0603_1%

(output = 250 mA)

+VDDA

4.85V

1

C478
10U_0805_10V4Z

2

+VDDC

U11

14

AUX_L

15

AUX_R

16

SENSE_A

17

SENSE_B

23

LINE_IN_L

24

LINE_IN_R

18

CD_L

20

CD_R

19

CD_GND_REF

21

MIC1

22

MIC2

13

PHONE

12

PC_BEEP

11

RESET#

10

SYNC

5

SDATA_OUT

47

EAPD

48

SPDIF_OUT

4

DVSS1

7

DVSS2

AD1986A_CSP48

+AVDD_AC97

38

46

34

42

AVDD125AVDD2

AVDD4

AVDD5

AVDD3

MONO_OUT

HP_OUT_L

HP_OUT_R

SDATA_IN

VREFOUT_LI

VREFOUT_CL

VREFOUT_MIC

LFE_OUT

CENTER_OUT

LINE_OUT_L
LINE_OUT_R

Compal Secret Data

Deciphered Date

DVDD11DVDD2

SURR_L

SURR_R

BIT_CLK

XTL_IN

GPIO

VREF

AVSS1
AVSS2
AVSS3
AVSS4

1

C496

2

0.1U_0402_16V4Z

9

35
36
37
39
41

6
8
2

3
29

33

28
27
32

31

R718 0_0402_5%

43

R719 0_0402_5%

45
26

40
44
30

1

C503

2

0.1U_0402_16V4Z

R715 0_0402_5%
R716 0_0402_5%

250_SDIN ICH_AC_SDIN0

250_XTL_IN

R177 0_0402_5%@

1 2
1 2

D

2 2

L11

CHB1608U301_0603

+VDDA

INT_CD_L<23>

3 3

4 4

CD_AGND<23>

1 2

R152 0_0603_5%

1 2

R451 0_0603_5%

1 2

R187 0_0603_5%

R447

10K_0402_5%

12

INT_CD_R<23>

CD_GNACD_AGND

12

R448
10K_0402_5%

1 2

10U_0805_10V4Z

JACK_PLUG<37>

JACK_PLUG_MIC<37>

+AVDD_AC97

R157 20K_0402_5%
R156 20K_0402_5%
R155 20K_0402_5%
R154 20K_0402_5%

C275

1U_0603_10V4Z

12
12
12
12

ICH_SYNC_AUDIO<20>
ICH_SDOUT_AUDIO<20>

+AUD_VREF

1

2

ICH_RST_AUDIO#<20>

10mil

GND GNDA

A

B

0.1U_0402_16V4Z

1

C264

C277

2

R166 40.2K_0402_1%
R717 20K_0402_5%

R484 2.49K_0402_1%

CD_R_L

CD_R_R

MIC<30>

MIC

+3VS

1

C272

0.1U_0402_16V4Z

2

1

1

C282

2

2

0.1U_0402_16V4Z

@12/20

1 2

1 2

C261 1U_0402_6.3V4Z

1 2

C260 1U_0402_6.3V4Z

1 2

C479 1U_0603_10V4Z

1 2
1 2

C480 1U_0603_10V4Z

1 2

C703 1U_0603_10V4Z

1 2

C262 0.1U_0402_16V4Z@

+AVDD_AC97

2

R494

2.49K_0402_1%

12

@

R458 47K_0402_5%

1 2

R459 0_0402_5%

1 2

EAPD<30,31,33>

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

1 2

CHB1608U301_0603

1 2

C

C702

1U_0603_10V4Z

1

CD_RC_L
CD_RC_R
CD_GNDACD_GNA
C_MIC

MDC_RC_SPK

MONO_IN

L701

2005/10/06 2006/10/06

R176

CHB1608U301_0603

1 2

1

C497
10U_0805_10V4Z

2

@

1 2
1 2

@

1 2

R174 33_0402_5%@

R173 33_0402_5%

1 2

10K_0402_5%

1

2

250_LINE_OUTL

250_LINE_OUTR

R169

C2680.1U_0402_16V4Z

12

+AUD_VREF

+3VS

250_LINE_OUTL
250_LINE_OUTR

250_LINE_OUTL
250_LINE_OUTR

R175 0_0402_5%@

12

1

C274
22P_0402_50V8J

2

@

1U_0603_10V4Z

1 2

C704 1U_0603_10V4Z

1 2

C705 1U_0603_10V4Z

C509 1U_0603_10V4Z

1 2

C508 1U_0603_10V4Z

1 2

C706 1U_0603_10V4Z

1 2

C707 1U_0603_10V4Z

1 2

Title

AD1986 Codec

Size Document Number Rev

Custom

HGT30/31 LA3061

Date: Sheet of

星期四二月

1 2

C280 1000P_0402_50V7K@

1 2

C281 1000P_0402_50V7K@

HP_L <30>

C267 22P_0402_50V8J

1 2

@

ICH_BITCLK_AUDIO

CLK_14M_CODEC

1 2

+AVDD_AC97

R457
1M_0402_5%

@

1 2
1

C492

2

LINE_OUTL
LINE_OUTR

HP_R <30>

ICH_BITCLK_AUDIO<20>
ICH_AC_SDIN0<20>

CLK_14M_CODEC<15>

INT_MIC <30,37,38>

LINE_OUTL<30>
LINE_OUTR<30>

LFE_OUT<31>

Compal Electronics, Inc.

23, 2006

E

29 47,

0.1

PDF created with pdfFactory Pro trial version www.pdffactory.com

A

1 1

B

C

D

E

+5VAMP

R704
10K_0402_5%

@

MUTE

1

12

R183
10K_0402_5%

AMP_OFF#

Q13

DTC124EK_SC59 @

1 2
12

R708

1.5K_0402_1%

R454 0_0402_5%

12

R467 100K_0402_5%

R165 10K_0402_5%

1 2
1 2

R721
100K_0402_5%

AMP_OFF#<31>

R162 10K_0402_5%

12

(0.65V -> 10dB)

MUTE

LINE_OUTL
LINE_OUTR

A

D20

2
3

DAN202U_SC70

R485 0_0402_5%

+3VS

1 2

13

2

LINE_OUTL<29>

LINE_OUTR<29>

2 2

EAPD<29,31,33>

EC_MUTE<33>

3 3

4 4

C504

0.1U_0402_16V4Z

VOL_AMP

12

B

+5VAMP

1

2

VOLMAX

LIN
RIN

W=40mil

1

C502

4.7U_0805_10V4Z

2

1

C488

4.7U_0805_10V4Z

2

U36

10

VDD

15

SHUTDOWN#

VDD

7

VOLUME

8

VOLMAX

13

SE/BTL#

6

LIN-

3

RIN-

4

BYPASS

APA2068KAI-TRL_SOP16

1 2

C511 0.1U_0402_16V4Z

1

MUTE

2
9

LOUT-

16

ROUT­LOUT+
ROUT+

GND
GND

SPKL+

11

SPKR+

14

5
12

HP_L<29>

HP_R<29>

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MUTE

L23 0_0603_5%

1 2

L24 0_0603_5%

1 2

L20 0_0603_5%

1 2

L8 0_0603_5%

1 2

MIC<29>

C270

100U_D2_6.3VM

+

1 2

C269

+

1 2

100U_D2_6.3VM

2005/10/06 2006/10/06

C

AMP_OFF#<31>

SPKL+_C

SPKR+_C

R720

1 2

1K_0402_5%

R181

0_0402_5%

1 2

R179

0_0402_5%

1 2

R180

1K_0402_5%

Compal Secret Data

Deciphered Date

SPKL-OSPKL­SPKR-OSPKR­SPKL+O
SPKR+O

R445

2.2K_0402_5%

47P_0402_50V8J

INTSPK_CL+

12

12

12

1 2

1

C474

2

1 2

L10 FBM-11-160808-601-T_0603

INTSPK_CR+

1 2

L9 FBM-11-160808-601-T_0603

R178

1K_0402_5%

MUTE

D

SPKL+O
SPKL-O
SPKR+O
SPKR-O

C163

47P_0402_50V8J@

+AUD_VREF

L19

C279

47P_0402_50V8J

1

1

C162

47P_0402_50V8J @

2

2

47P_0402_50V8J@

1

1

C167

C168

47P_0402_50V8J@

2

2

12

R446

2.2K_0402_5%

FBM-11-160808-601-T_0603

1

C475

47P_0402_50V8J

2

EXT_MIC

INT_MIC

HEADPHONE

PL

PR

1

1

C278
47P_0402_50V8J

2

2

1 2

R727 1K_0402_5%

1 2

R728 1K_0402_5%

Title

AMP & Audio Jack

Size Document Number Rev

Custom

HGT30/31 LA3061

Date: Sheet of

星期四二月

1

C

Q701

2

B

2SC2411K_SC59

E

3

1

C

Q702

2

B

2SC2411K_SC59

E

3

Compal Electronics, Inc.

23, 2006

E

JP20

1
2
3
4

ACES_85204-0400

ME@

MIC IN

EXT_MIC<37>

INT_MIC <29,37,38>

PL <37>

PR <37>

30 47,

0.1

PDF created with pdfFactory Pro trial version www.pdffactory.com

SUBWOOFER (Reserved for C38)

WOOFER@

LFE_OUT<29>

+AVDD_AC97

12

R722
100K_0402_5%

+AUD_VREF_LF

C709

1U_0603_10V4Z

2

12

R723
100K_0402_5%

1

LFE_OUT

R478

100K_0402_5%

AMP_OFF#<30>

1 2

EAPD<29,30,33>

C514 1U_0603_10V4Z

+AUD_VREF_LF

1 2

1 2

C512

0.1U_0402_16V4Z
C519

1 2

1U_0603_10V4Z

Gain = 3.1dB

Fc(HPF)= 36.2Hz

Gain = 15.9dB

MIX_OUT WOOFER_IN

R732 0_0402_5%@

R733 0_0402_5%

3
2

1 2

@

R185
20K_0402_5%

12

12

+AVDD_AC97

C285 1U_0603_10V4Z

1 2

U37A

8

TLV2462CDR_SO8

P

+

1

O

-

G

4

43K_0402_5%

12

12

2

C710

1

1U_0603_10V4Z

+AUD_VREF_LF

R477

C708 100P_0402_50V8J

2

1

0.1U_0402_16V4Z

C284

R184

560_0402_5%

+5VAMP

2

C283

1

0.47U_0603_16V4Z

12

560_0402_5%

0.1U_0603_50V4Z

Fc(LPF)= 1.5KHz

U12

1

IN

2
3

VO-

SD#

GND

VDD

SE/BTL#

BYPASS4VO+

TPA0211DGN_MSOP8

C518 0.1U_0603_50V4Z

1 2

R182

12

2

C513

1

30mil

WOOFER-

8
7
6

WOOFER+

5

12

R724
100K_0402_5%

+AVDD_AC97

8

5

P

+

7

O

6

-

G

U37B
TLV2462CDR_SO8

4

20mil

SubWoofer Conn.

L13 FBMA-L11-160808-700LMT_0603

1 2

L12 FBMA-L11-160808-700LMT_0603

1 2

C523

MIX_OUT

12

0.22U_0603_10V7K

JP44

1

1

2

2

3

GND

4

GND

MOLEX_53780-0270

ME@

10mil

+5VS

C411 0.1U_0402_16V4Z

12

SYSON#<35,37>

SYSON#

U25

1
2
3
4

GND
IN
IN
EN#

OUT
OUT
OUT
FLG

G528_SO8

+USB_VCCA

8
7
6
5

USB_OC#0<21>

1

C417

1000P_0402_50V7K@

2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

PDF created with pdfFactory Pro trial version www.pdffactory.com

USB Port

150U_D_6.3VM

USB20_N0<21>
USB20_P0<21>

PSOT24C_SOT23@

For EMI

2005/10/06 2006/10/06

Compal Secret Data

Deciphered Date

2

3

D14

10P_0402_25V8K @

1

C174

C321

0.1U_0402_16V4Z

1

2

+USB_VCCA

1

1

+

2

1

C161

C160
1000P_0402_50V7K

2

2

1

C322
10P_0402_25V8K

@

2

Title

Size Document Number Rev

Custom

Date: Sheet of

JP21

1

VCC

2

D-

3

D+

4

GND

5

GND1

6

GND2

7

GND3

8

GND4

SUYIN_020173MR004G565ZR

ME@

Compal Electronics, Inc.

Bluetooth & USB CONN.

HGT30/31 LA3061

星期四二月

23, 2006

31 47,

0.1

5

D D

4

3

2

1

INT_KBD CONN.( TYPE "D" KB)

KSI[0..7]

KSO[0..16]

C C

KSO12
KSO13
KSO14
KSO11
KSO10
KSO15

B B

JP33

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

+5VS

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
LPC_FRAME#
LPC_DRQ#0
PCI_RST#

SIRQ

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20

ACES_85201-2005

A A

ME@

KSI[0..7] <33,38>

KSO[0..16]<33,38>

JP26

KSI1

24

24

KSI7

23

23

KSI6

22

22

KSO9

21

21

KSI4

20

20

KSI5

19

19

KSO0

18

18

KSI2

17

17

KSI3

16

16

KSO5

15

15

KSO1

14

14

KSI0

13

13

KSO2

12

12

KSO4

11

11

KSO7

10

10

KSO8

9

9

KSO6

8

8

KSO3

7

7

6

6

5

5

4

4

3

3

2

2

1

1

ACES_85202-2405

+3VS

CLK_14M_SIO<15>

LPC_FRAME#<20,33>
LPC_DRQ#0<20>

PCI_RST#<19,21,24,25,26,27,33>
CLK_PCI_DB<15>

SIRQ <21,24,26,33>

FOR LPC SIO DEBUG PORT

LPC_AD[0..3]

CP1

KSI1
KSI7

2

KSI6

3

KSO9

4 5

100P_1206_8P4C_50V8

CP2

KSI4
KSI5

2

KSO0

3

KSI2

4 5

100P_1206_8P4C_50V8

CP3

KSI3
KSO5

2

KSO1

3

KSI0

4 5

100P_1206_8P4C_50V8

CP4

KSO2
KSO4

2

KSO7

3

KSO8

4 5

100P_1206_8P4C_50V8

CP6

KSO6
KSO3

2

KSO12

3

KSO13

4 5

100P_1206_8P4C_50V8

CP5

KSO14
KSO11

2

KSO10

3

KSO15

4 5

100P_1206_8P4C_50V8

R391

10K_0402_5%

12

@

81
7
6

81
7
6

81
7
6

81
7
6

81
7
6

81
7
6

LPC_AD[0..3]<20,33>

JP43

20

20

19

19

18

18

17

17

16

16

15

15

14

14

13

13

12

12

11

11

10

10

9

9

8

8

7

7

6

6

5

5

4

4

3

3

2

2

1

1

ACES_85201-2005

ME@

ON/OFFBTN#<38>

PCI_CBE#0
PCI_AD6
PCI_AD4
PCI_AD2
PCI_AD0
PCI_AD1
PCI_AD3
PCI_AD5
PCI_AD7
PCI_AD8
PCI_CBE#1
PCI_CBE#2
PCI_CBE#3

PCI_AD9

Power BTN

ON/OFFBTN#

SW1

3

1
2

4

5

6

SMT1-05_4P

EC_ON<33>

PCI_CBE#0<19,24,26,27>
PCI_AD6 <19,24,26,27>
PCI_AD4 <19,24,26,27>
PCI_AD2 <19,24,26,27>
PCI_AD0 <19,24,26,27>
PCI_AD1 <19,24,26,27>
PCI_AD3 <19,24,26,27>
PCI_AD5 <19,24,26,27>
PCI_AD7 <19,24,26,27>
PCI_AD8 <19,24,26,27>
PCI_CBE#1<19,24,26,27>
PCI_CBE#2<19,24,26,27>
PCI_CBE#3<19,24,26,27>

CLK_PCI_DB<15>

+5VS

PCI_RST#<19,21,24,25,26,27,33>
PCI_FRAME#<19,24,26,27>
PCI_TRDY#<19,24,26,27>
PCI_AD9 <19,24,26,27>

EC_ON

+3VALW

12

100K_0402_5%

1

DAN202U_SC70

R113

4.7K_0402_5%

@

2

D2

R118

2
3

+5VALW

+3VS

+3VALW

12

Q10
DTC124EK_SC59

13

EC_TX<33>
EC_RX<33>

ON/OFF
51ON#

1

2

C205

1000P_0402_50V7K

DEBUG PORT

12

R725 0_0402_5%@

12

R726 0_0402_5%@

EC_TX

ON/OFF#<33>
51ON# <38,39>

12

D1
RLZ20A_LL34

+5VALW : FOR EC
+3VS : FOR P-80

JP22

1

1

2

2

3

3

4

4

ACES_85205-0400

ME@

P80_DATA
P80_CLK

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

PDF created with pdfFactory Pro trial version www.pdffactory.com

2005/10/06 2006/10/06

3

Compal Secret Data

Deciphered Date

2

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

KBD,ON/OFF,T/P,LED/B,DEBUG

HGT30/31 LA3061

星期四二月

23, 2006

32 47,

1

0.1

5

L6

+3VALW +EC_AVCC

D D

CLK_PCI_LPC<15>

C C

B B

CB_PME#<24>
R5_PME#<26>
LAN_PME#<27>
PCI_PME#<19>

1 2

FBM-11-160808-601-T_0603

0.1U_0402_16V4Z
L7

1 2

FBM-11-160808-601-T_0603

12

R143 10_0402_5%@

C232

22P_0402_50V8J@

1 2

R131 0_0402_5%@

1 2

R141 0_0402_5%@

1 2

R138 0_0402_5%

1 2

R127 0_0402_5%

+5VS

RP13

1 8
2 7
3 6
4 5

+3VALW

+5VALW

+3VS

10K_1206_8P4R_5%

@

RP14

1 8
2 7
3 6
4 5

100K_1206_8P4R_5%

1 2

R130 4.7K_0402_5%

1 2

1 2
1 2

R133 4.7K_0402_5%

R135 4.7K_0402_5%
R139 4.7K_0402_5%

C211

12

EC_GPIO4C
EC_GPIO4D

FRD#
FSEL#

EC_SMB_CK1
EC_SMB_DA1

EC_SMB_CK2
EC_SMB_DA2

100P_0402_50V8J@

2

1

ECAGND

+3VALW

EC_P80_CLK<13,14>
EC_P80_DATA<13,14>

C226

1

C212
1000P_0402_50V7K

2

+3VALW

R134
10K_0402_5%

1 2

1

2

1 2

R112 47K_0402_5%

0.1U_0402_16V4Z

EC_PME#

KSO[0..15]<32>

KSI[0..7]<32,38>

R713 0_0402_5%
R714 0_0402_5%

1

C223

100P_0402_50V8J @

2

2

C200

1

1 2
1 2

EC_GPIO09<38>

0.1U _ 0402_16V4Z

COMM EC_GPIO Configuration

PIN GPIO HDL00/HDL10 HGT30/HGT31

80

EC_GPIO3F

19

EC_GPIO09

35

EC_GPIO17

44

EC_GPIO1D
EC_GPIO4A NC

91
92 NC
93

A A

94

102

97
137
142
143

EC_GPIO4C
EC_GPIO4D
EC_GPIO55
EC_GPIO50
EC_GPIO57
EC_GPIO58
EC_GPIO59
EC_GPIO1230 AMP_MUTE TP_LOCK_LED#

5

NC
EASY_KEY1#
SUSP_LED#
NC

NCEC_GPIO4B
NC
NC
NC
MEDIA#
VOL_UP#
VOL_DOWN#
KILL_SW#

TP_ACT_LED#
LED6#
EC_P80_DATA
LED3#
LED4#

LED1#
LED2#
LED5#
BT_OFF#
NOVO_BTN#
SLP_S4#
WIRE_LAN_BTN#

4

+3VALW

C248

0.1U _ 0402_16V4Z

C447

0.1U _ 0402_16V4Z

C231

1

1

2

2

GATEA20<20>
KB_RST#<20>

SIRQ<21,24,26,32>

LPC_FRAME#<20,32>

LPC_AD3<20,32>
LPC_AD2<20,32>
LPC_AD1<20,32>
LPC_AD0<20,32>

PCI_RST#<19,21,24,25,26,27,32>

EC_SCI#<21>

PCI_CLKRUN#<21,24,26,27>

EC_GPIO1D<38>

KSO[0..15]
KSI[0..7]

KSO16<38>
KSO17<38>

EC_SMB_DA2<4>
EC_SMB_CK2<4>

EC_SMB_DA1<34,40>
EC_SMB_CK1<34,40>

EC_TX<32>
EC_RX<32>

PWR_LED#<37>

NUM_LED#<38>
CHARGE_LED0#<37>
CHARGE_LED1#<37>

CAPS_LED#<38>

EC_GPIO55<38>

SYSON<35,37,43>

EC_RSMRST#<21>
BKOFF#<16>

SLP_S3#<21>

EC_LID_OUT#<21>

SLP_S5#<21>

EC_SMI#<21>

R401 0_0402_5%

LID_SWITCH#<37>

SUSP#<18,24,26,34,35,37,43,44>

PBTN_OUT#<21>

1

2

R336

1 2

C220

0.1U _ 0402_16V4Z

1

2

LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0

EC_RST#
EC_SCI#

1 2

0_0402_5%@

KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7

KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15
KSO16
KSO17

EC_SMB_DA2
EC_SMB_CK2
EC_SMB_DA1
EC_SMB_CK1

EC_TX
EC_RX

CHARGE_LED0#
CHARGE_LED1#
CAPS_LED#

SYSON

BKOFF#

EC_LID_OUT#

EC_SMI#
LID_SWITCH#

SUSP#

PBTN_OUT#

EC_PME#

CRY1
CRY2

C237

1000P_0402_50V7K

C201

1000P_0402_50V7K

1

1

2

2

U6

1

GA20/ GPIO00/GA20

2

KBRST#/GPIO01/KBRST#

3

SERIRQ

5

LPC_FRAME# / LFRAME#

6

LPC AD3/LAD3

9

LPC AD2/LAD2

10

LPC AD1/LAD1

12

LPC AD0/LAD0

14

CLK_PCI_EC/PCICLK

15

PCIRST#

42

EC RST#/ ECRST#

24

EC SCI#/SCI#/GPIO0E

44

PM_CLKRUN#/ CLKRUN#

63

KSI0/GPIO30

64

KSI1/GPIO31

65

KSI2/GPI032

66

KSI3/GPIO33

67

KSI4/GPIO34

68

KSI5/GPI035

69

KSI6/GPIO36

70

KSI7/GPIO37

47

KSO0/GPIO20

48

KSO1/GPIO21

49

KSO2/GPIO22

50

KSO3/GPIO23

51

KSO4/GPIO24

52

KSO5/GPIO25

53

KSO6/GPIO26

54

KSO7/GPIO27

55

KSO8/GPIO28

56

KSO9/GPIO29

57

KSO10/GPIO2A

58

KSO11/GPIO2B

59

KSO12/GPIO2C

60

KSO13/GPIO2D

61

KSO14/GPIO2E

62

KSO15/GPIO2F

89

EC URXD/KSO16/GPIO48

90

EC UTXD/KSO17/GPIO49

88

EC SMD2/ GPIO47/SDA2

87

EC SMC2/GPIO46/SCL2

86

EC SMD1/GPIO44/SDA1

85

EC SMC1/GPIO44/SCL1

34

PCM_SPK#/EMAIL_LED#/ GPIO16

35

SB_SPKR/PWR_SUSP_LED#/ GPIO17

38

PWRLED#/ GPIO19

40

NUMLED#/ GPIO1A

99

BATT CHGI LED#/ E51CS#

101

BATT LOW LED#/ E51MR0

100

CAPS LED#/ E51TMR1

102

ARROW LED#/ E51 INT0

104

SYSON/GPIO56/ E51 INT1

4

EC_RSMRST#/ GPIO02

7

BKOFF#/GPIO03

8

PM SLP S3#/GPIO04

16

EC LID OUT#/GPIO06

17

PM SLP S05#/ GPIO07

18

EC SMI#/GPIO08

19

EC SWI#/GPIO09

20

LID SW#/ GPIO0A

21

SUSP#/GPIO0B

22

PBTN_OUT#/GPIO0C

23

EC PME#/GPIO0D

140

XCLKO

138

XCLKI

Host

INTERFACE

key Matrix

scan

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

+EC_AVCC

11

26

127

141

105

VCC

VCC

VCC/ EC VCC

VCC / EC VCC

VCC / EC VCC37VCC / EC VCC

PWR

FAN/PWM

FAN SPEED1/GPIO14/FANFB1
FAN SPEED2/GPIO15/FANFB2

PS2 interface

SM BUS

GND13GND28GND39GND

GND

GND

103

129

139

3

75

BATTEMP/AD0/GPIO38
BATT OVP/AD1/GPIO39

ADP_I/AD2/GPIO3A

AD BID0/AD3/GPIO3B

AD INtput or GPI

EC_AVCC / AVCC

DAC_BRIG/DA0/GPIO3D
EN DFAN1/DA1/GPIO3D

IREF2/DA2

EN DFAN2/DA3/ GPIO3F

DA output or GPO

INVT_PWM/GPIO0F/PWM1

BEEP#/GPIO10/PWM2

OUT BEEP/GPIO12/PWM3

ACOFF/GPIO18/PWM4

PSCLK1
PSDAT1
PSCLK2
PSDAT2
PSCLK3
PSDAT3

ADB0/D0
ADB1/D1
ADB2/D2

Data

ADB3/ D3

BUS

ADB4/D4
ADB5/D5
ADB6/D6
ADB7/D7

KBA0/A0
KBA1/A1
KBA2/A2
KBA3/A3
KBA4/A4
KBA5/A5

BUS

SELIO2#/ GPIO43

FSEL#/SELMEM#

ECTHERM#/GPIO11

PCMRST#/GPIO1E

WL OFF#/GPIO1F

ALI/MH#/GPIO40

FSTCHG/GPIO41

AGND

77

E CA GN D

KBA6/A6
KBA7/A7
KBA8/A8

KBA9/A9
KBA10/A10
KBA11/A11
KBA12/A12
KBA13/A13
KBA14/A14
KBA15/A15
KBA16/A16
KBA17/A17
KBA18/A18
KBA19/A19

SELIO#/ GPIO50

FRD#/RD#

FWR#/WR#

EC ON/ GPIO1B

AC IN/ GPIO1C

ONOFF/GPIO18

VR ON/ GPIO42
GPIO57/GPIO57
GPIO58/GPIO58
GPIO59/GPIO59

KB910L_LQFP144

Address

2005/10/06 2006/10/06

BATT_TEMP

71

BATT_OVP

72
73

BRD_ID

74

DAC_BRIG

76

EN_FAN1

78

IREF

79
80

INVT_PWM

25

BEEP#

27
30

ACOFF

31

FAN_SPEED1

32

MB_ID

33

91
92

EC_GPIO4C

93

EC_GPIO4D

94

TP_CLK

95

TP_DATA

96

ADB0

125

ADB1

126

ADB2

128

ADB3

130

ADB4

131

ADB5

132

ADB6

133

ADB7

134

KBA0

111

KBA1

112

KBA2

113

KBA3

114

KBA4

115

KBA5

116

KBA6

117

KBA7

118

KBA8

119

KBA9

120

KBA10

121

KBA11

122

KBA12

123

KBA13

124

KBA14

110

KBA15

109

KBA16

108

KBA17

107

KBA18

106

KBA19

98
84

BT_OFF#

97

FRD#

135

FWR#

136

FSEL#

144

EC_ON

41
43

EC_THERM#

29
36

ICH_POK

45
46

81

FSTCHG

82

VR_ON

83

EC_GPIO57

137

EC_GPIO58

142

EC_GPIO59

143

Compal Secret Data

Deciphered Date

BATT_OVP<41>

DAC_BRIG<16>
EN_FAN1<4>
IREF <41>
TP_ACT_LED#<37>

INVT_PWM<16>
BEEP# <29>
TP_LOCK_LED#<37>
ACOFF <39,41>
FAN_SPEED1<4>

EC_GPIO4A<38>

EAPD <29,30,31>
EC_GPIO4C<38>
EC_GPIO4D<38>

TP_CLK <37>

1 2

R486 0_0402_5%

12

TP_DATA<37>

KBA[0..19]<34>

ADB[0..7]<34>

ENBKL <16>
BT_OFF# <28>
FRD# <34>
FWR# <34>

FSEL# <34>

EC_ON <32>
ACIN <21,39>
EC_THERM#<21>
ON/OFF#<32>
ICH_POK<7,21>

WL_OFF#<28>

EC_MUTE<30>
FSTCHG <41>
VR_ON <45>
EC_GPIO57<38>

EC_GPIO59<38>

2

ECAGND

C202

0.01U_0402_25V4Z

C206 0.1U_0402_16V4Z

1 2

@

ID

0
1
2
3

BATT_TEMP<40>
ADP_ID

R01 (EVT)
R02 (DVT)
R03 (PVT)

R04
4
5
6
7

R119(Ra)=100K Ohm

ID

0

HGT30(VGA)

1

HGT31(UMA)

KBA[0..19]
ADB[0..7]

SLP_S4# <21>

2

1

Analog Board ID definition,
Please see page 3.

100K_0402_1%

<For HDL Only>

BRD ID

BRD ID

R115(Rb)Vab

0

8.2K

0.25V

18K

0.50V

33K

0.82V

56K

1.19V

100K

1.65V

200K

2.20V

NC

3.30V

0V

C208

BRD_ID

1

2

0.1U _ 0402_16V4Z

100K_0402_1%

MB_ID

0_0402_5%

MB_ID

MB

R125(Ra)R126(Rb)

NC

0 Ohm

NC100K Ohm

TP_CLK

1 2

4.7K_0402_5%

R142

TP_DATA

1 2

4.7K_0402_5%

R146

KBA1

@

1 2

R147 1K_0402_5%

KBA4

1 2

R148 1K_0402_5%@

KBA5

1 2

R149 1K_0402_5%@

CRY1 CRY2

R150

1 2

20M_0603_5%@

C250

15P_0402_50V8J

32.768KHZ_12.5P_1TJS125BJ2A251

Compal Electronics, Inc.

Title

ENE-KB910L

Size Document Number Rev

Custom

HGT30/31 LA3061

,

星期四二月

Date: Sheet of

23, 2006

4IN1

X1

OUT

NC3NC

2

1

+3VALW

R119

1 2

R115

18K_0402_5%

+3VALW

R125

UMA@

1 2

R126

VGA@

1 2

+5VS

+3VALW

C249

15P_0402_50V8J

33 47

Ra

Rb

HGT31

Ra

Rb

HGT30

0.1

PDF created with pdfFactory Pro trial version www.pdffactory.com

GND

+5VALW

12

R116
100K_0402_1%

1

A0

2

A1

3

A2

4

12

R117
100K_0402_1%

R337
100K_0402_5%@

1 2

FSEL# <33>

FWE#

C501

1 2

0.1U_0402_16V4Z

4

R707 0_0402_5%

+3VALW

5

P

O

G

3

1 2

@

U32
TC7SH32FU_SSOP5

2

I0

1

I1

+3VALW

12

R442
100K_0402_1%

2

G

1 3

D

Q30
2N7002_SOT23

+5VALW

C199

0.1U_0402_16V4Z

1 2

U4

8

VCC

7

WP

@

@

4

O

1 2

R338 0_0402_5%

6

SCL

5

SDA

AT24C16AN-10SU-2.7_SO8

+3VALW

U26

5

TC7SH32FU_SSOP5

INT_FLASH_EN#

2

P

I0

FSEL#

1

I1

G

3

EC_SMB_CK1<33,40>
EC_SMB_DA1<33,40>

SUSP# <18,24,26,33,35,37,43,44>

S

EC_FLASH#<21>

FWR# <33>

INT_FSEL#

R339

1 2

22_0402_5%

Reserve R339, if U26 is single gate.

KBA[0..19]<33>

ADB[0..7]<33>

KBA[0..19]
ADB[0..7]

1MB Flash ROM

KBA0
KBA1
KBA2
KBA3
KBA4
KBA5
KBA6
KBA7
KBA8
KBA9
KBA10
KBA11
KBA12
KBA13
KBA14
KBA15
KBA16
KBA17
KBA18
KBA19

INT_FSEL#

FRD#<33>

FRD#
FWE#

U30

21

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19

CE#
OE#
WE#

VCC0
VCC1

READY/BUSY#

GND0
GND1

D0
D1
D2
D3
D4
D5
D6
D7

RP#

NC

NC0
NC1

20
19
18
17
16
15
14

8
7

36

6
5
4
3
2

1
40
13
37

22
24

9

SST39VF080-70-4C-EIE_TSOP40

31
30

ADB0

25

ADB1

26

ADB2

27

ADB3

28

ADB4

32

ADB5

33

ADB6

34

ADB7

35

RESET#

10
11
12
29
38

23
39

1 2

R443
100K_0402_1%

+3VALW

1

C416

0.1U_0402_16V4Z

2

+3VALW

SB_INT_FLASH_SEL tie to ATI SB
GPIO1 and pull down

SB_INT_FLASH_SEL<21>

1MB ROM Socket

KBA16
KBA15
KBA14
KBA13
KBA12
KBA11
KBA9
KBA8
FWE#
RESET#
INT_FLASH_EN#
SB_INT_FLASH_SEL
KBA18
KBA7
KBA6
KBA5
KBA4
KBA3
KBA2
KBA1

JP34

1 2
3 4
5 6
7 8
9 10
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
29 30
31 32
33 34
35 36
37 38
39 40

SUYIN_80065AR-040G2TME@

KBA17

KBA19
KBA10
ADB7
ADB6
ADB5
ADB4

ADB3
ADB2
ADB1
ADB0
FRD#

FSEL#
KBA0

+3VALW

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

PDF created with pdfFactory Pro trial version www.pdffactory.com

2005/10/06 2006/10/06

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

BIOS & EC I/O Port

HGT30/31 LA3061

星期四二月

23, 2006

34 47,

0.1

A

1 1

2 2

B

C

D

SUSP

Q26

2N7002_SOT23

2

G

+VSB

12

R384
10K_0402_5%

13

D

S

E

C435

10U_0805_10V4Z

+5VALW to +5VS Transfer

+5VALW +5VS

U27

1

8

S

D

2

7

1

2

RUNON

1

C434

0.1U_0603_50V4Z

2

D

6

D

5

D

SI4800DY_SO8

S

3

S

4

G

F

1

C426
10U_0805_10V4Z

2

0.1U_0402_16V4Z

1

C419

2

G

H

I

+5VALW

12

R92
47K_0402_5%

SYSON#<31,37>

SYSON<33,37,43>

SUSP<44>

SUSP#<18,24,26,33,34,37,43,44>

SYSON#

2

G

SUSP

2

G

+5VALW

13

D

S

12

13

D

S

Q6
2N7002_SOT23

R334
10K_0402_5%

Q24
2N7002_SOT23

J

3 3

+3VALW to +3VS Transfer

+3VALW

U7

8

S

D

7

+VSB

2

G

10U_0805_10V4Z

12

R136
22K_0402_5%

13

D

S

4 4

SUSP

Q11

2N7002_SOT23

5 5

C236

1

2

1

C224

0.1U_0603_50V4Z

2

D

6

D

5

D

SI4800DY_SO8

S
S
G

+1.8V to +1.8VS Transfer

+1.8V

U17

8

S

D

7

6 6

7 7

2N7002_SOT23

SUSP

2

G

Q20

VGA@

+VSB

12

R227
33K_0402_5%

VGA@

13

D

S

10U_0805_10V4Z

C313

VGA@

1

2

1

C312

0.1U_0603_50V4Z

2

VGA@

D

6

D

5

D

SI4800DY_SO8

VGA@

S
S
G

+3VS

1

C229
10U_0805_10V4Z

2

1 2

+1.8VS

1

C131

VGA@

10U_0805_10V4Z

2

1 2

0.1U_0402_16V4Z

1

C225

2

RUNON

0_0402_5% @

VGA@

0.1U_0402_16V4Z

1

C133

2

RUNON

0_0402_5%@

12

R335
470_0402_5%

13

D

S

12

R228
470_0402_5%

13

D

S

SUSP

2

G

Q25
2N7002_SOT23

2

G

Q5
2N7002_SOT23

+1.8VS

12

13

D

S

+3VS

12

13

D

S

R58
470_0402_5%

SUSP

2

G

Q3
2N7002_SOT23

R731
470_0402_5%

SUSP

2

G

Q704
2N7002_SOT23

+0.9VS+5VS

12

R106
470_0402_5%

13

D

S

+2.5VS+1.8V

12

R105
470_0402_5%

13

D

S

SUSP

2

G

Q8
2N7002_SOT23

SUSPSYSON#

2

G

Q7
2N7002_SOT23

1
2
3
4

R132

1
2
3
4

R129

8 8

A

B

C

D

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

E

2005/10/06 2006/10/06

F

Compal Secret Data

Deciphered Date

G

Title

Size Document Number Rev

Custom

H

Date: Sheet of

Compal Electronics, Inc.

DC/DC Circuit

HGT30/31 LA3061

星期四二月

23, 2006

I

35 47,

0.1

J

PDF created with pdfFactory Pro trial version www.pdffactory.com

A

B

C

D

E

CLOSE TO JTVOUT1

L802

1

C802

2

82P_0402_50V8J

1

C803

2

82P_0402_50V8J

1

C805

2

82P_0402_50V8J

1

C808

2

22P_0402_50V8J

FLM1608081R8K_0603

FLM1608081R8K_0603

FLM1608081R8K_0603

1 2

C801

L803

1 2

C804

L801

1 2

C806

L804

CHB1608B121_0603

1 2

L805

CHB1608B121_0603

1 2

L806

CHB1608B121_0603

1 2

1

C809

2

22P_0402_50V8J

22P_0402_50V8J

L807 CHB1608B121_0603

1 2
1 2

L808 CHB1608B121_0603

82P_0402_50V8J

82P_0402_50V8J

82P_0402_50V8J

1

2

1

2

1

2

+CRT_VCC

R801

1K_0402_5%

C815

+3VS

+3VS

12

R802

1K_0402_5%

1

@

C816

2

33P_0402_50V8 J

33P_0402_50V8J

1

D805

DA204U_SC70

2

3

@

1

1

2

12

1

@

2

C810
10P_0402_25V8K

2

@

R803

1 2

2.2K_0402_5%

C811
10P_0402_25V8K

R804

1

D801

DA204U_SC70

2

3

@

@

1 2

2.2K_0402_5%

1

D802

DA204U_SC70

2

@

1

C812
10P_0402_25V8K

2

3

1

D806

DA204U_SC70

2

3

@

@

1

D803

DA204U_SC70

2

3

@

1

D804

DA204U_SC70

2

3

@

LUMA_OUT
CRMA_OUT

COMP_OUT

+5VS

+CRT_VCC

D807

21

RB751V_SOD323

VGA_DDC_DAT_OUT
VGA_DDC_CLK_OUT

1

C813

0.01U_0402_25V4Z

2

RED_OUT

GREEN_OUT

BLUE_OUT

JVGA_HS_OUT
JVGA_VS_OUT

MSEMS#

1
2
3
4
5

LUMA<17>

1 1

CRMA<17>

COMP<17>

2 2

3 3

RED<17>

GREEN<17>

BLUE<17>

VGA_DDC_DAT<17>
VGA_DDC_CLK<17>

JVGA_HS<17>
JVGA_VS<17>

1

C807

2

6

CF4

FM4

H4
HOLEA

1

H20
HOLEA

1

CF5

1

1

FM5

1

1

H5
HOLEA

1

H21
HOLEA

1

CF1

1

1

FM1

1

1

H1
HOLEA

1

4 4

H17
HOLEA

1

CF2

FM2

H2
HOLEA

1

H18
HOLEA

1

1

1

CF3

FM3

H3
HOLEA

1

H19
HOLEA

1

A

1

1

CF6

FM6

H6
HOLEA

1

H22
HOLEA

1

1

CF7

H7

HOLEA

1

H23

HOLEA

1

1

CF8

H8
HOLEA

1

H25
HOLEA

1

1

CF9

H9
HOLEA

1

H26
HOLEA

1

1

CF10

H10

HOLEA

1

H27

HOLEA

1

B

1

H28
HOLEA

CF11

H11
HOLEA

1

1

1

H29
HOLEA

1

CF12

H12
HOLEA

1

H30
HOLEA

1

1

CF13

H13
HOLEA

1

CL1
CLIP

CF14

1

H15

H14

HOLEA

HOLEA

1

1

1

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2005/03/10 2006/03/10

Compal Secret Data

7
8
9
10
11
12
13
14

Deciphered Date

VGA I/O PORT Connector

S-VIDEO

JP802

1

1

CRMA_OUT
LUMA_OUT
COMP_OUT

+CRT_VCC

RED_OUT
GREEN_OUT

BLUE_OUT
JVGA_VS_OUT
JVGA_HS_OUT
VGA_DDC_DAT_OUT

VGA_DDC_CLK_OUT

1

2

PIN ASSIGMENT

D-SUB SVIDEOPIN PIN

FUNCTION FUNCTION
+CRT_VCC

9

RED

6
2
7
3
8

14
10
13
11
12
15

4

D

GND

GREEN

GND

BLUE

GND

VSYNC

GND

HSYNC

SENSE
SM_DAT
SM_CLK

PIN4

G1

2

2

3

3

4

4

5

5

6

6

G2

MOLEX_53780-0670

ME@

DSUB

JP801

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

11

11

12

12

13

13

14

14

PIN4

ACES_87213-1400

C814

ME@

0.1U_0402_16V4Z

1
2
3
4
5
6

Title

CRT & TVout Connector

Size Document Number Rev

Custom

HGT30/31 LA3061

Date: Sheet of

星期四二月

7

8

1
4
2
3
5
6

NC

CRMA1

GND

LUMA

GND

CVBS

Compal Electronics, Inc.

23, 2006

E

36 47,

0.1

PDF created with pdfFactory Pro trial version www.pdffactory.com

5

4

3

2

1

NEW CARD FOR C38

LED Indicator ON M/B

+1.5VS_PEC

4.7U_0805_10V4Z

EXP@

+3VALW

CPUSB#<21>

PLT_RST#<7,19,23,28>

SYSON<33,35,43>
SUSP#<18,24,26,33,34,35,43,44>

0.1U_0402_16V4Z

EXP@

0.1U_0402_16V4Z

EXP@

0.1U_0402_16V4Z

D D

12

C820

12

C821

12

R807 100K_0402_5%EXP@

12

+1.5VS

+3VS

+3VALW

PLT_RST#
SYSON
SUSP#

U801

12

1.5Vin

14

1.5Vin

2

3.3Vin

4

3.3Vin
AUX_IN17AUX_OUT

6

SYSRST#

20

SHDN#

1

STBY#

10

CPPE#

9

CPUSB#

18

RCLKEN

R5538_QFN20

EXP@

1.5Vout

1.5Vout

3.3Vout

3.3Vout

PERST#

GND

OC#

11
13

3
5

15
19
8
16

NC

7

Express Card Power Switch

C819

+1.5VS_PEC

+3VS_PEC

+3V_PEC

PERST#

EXP@

0.1U_0402_16V4Z

EXP@

0.1U_0402_16V4Z

EXP@

0.1U_0402_16V4Z

close to JP14

C C

USB20_N7<21>

USB20_P7<21>

ICH_PCIE_WAKE#<21,28>

USB20_N7
USB20_P7

R808
R809

R811

EXP@

0_0402_5%

ICH_SMBCLK<15,21,28>

ICH_SMBDATA<15,21,28>

1 2

CLKREQ_NC#<15>

CLK_PCIE_NC1#<15>

CLK_PCIE_NC1<15>

PCIE_RXN1<21>

PCIE_RXP1<21>
PCIE_TXN1<21>

PCIE_TXP1<21>

0_0402_5%EXP@

1 2
1 2

0_0402_5%EXP@

+3V_PEC
+3VS_PEC

+1.5VS_PEC
+1.5VS_PEC

USB7­USB7+
CPUSB#

ICH_SMBCLK
ICH_SMBDATA

PCIE_PME#_R

PERST#

CLKRENC#
CPUSB#
CLK_PCIE_NC1#
CLK_PCIE_NC1

PCIE_RXN1
PCIE_RXP1

PCIE_TXN1
PCIE_TXP1

close to JP14

B B

C817

C822

C824

JP803

1

GND

2

USB_D-

3

USB_D+

4

CPUSB#

5

RSV

6

RSV

7

SMB_CLK

8

SMB_DATA

9

+1.5V

10

+1.5V

11

WAKE#

12

+3.3VAUX

13

PERST#

14

+3.3V

15

+3.3V

16

CLKREQ#

17

CPPE#

18

REFCLK-

19

REFCLK+

20

GND

21

PERn0

22

PERp0

23

GND

24

PETn0

25

PETp0

26

GND

27

GND

28

GND

FOX_1CH4110C

ME@

1

2

+3V_PEC

1

2

+3VS_PEC

1

2

1

C818

2

1

2

4.7U_0805_10V4Z

1

C825

2

EXP@

C823

EXP@

4.7U_0805_10V4Z

EXP@

( 1 )

( 2 )

( 3 )

TP_ACT_LED#<33>

Wireless / Bluetooth LED

R805 150_0402_5%

WIRELESS_LED#<28>

BTONLED<28>

BTONLED

1 2

R806 220_0402_5%

1 2

STATUS

AC

Chargin

Blinking Blue

Low BATT

BATT_CHG_LED#

CHARGE_LED0#<33>

CHARGE_LED1#<33>

CHARGE_LED0#

CHARGE_LED1#

R810 150_0402_5%

1 2

R812 220_0402_5%

1 2

BATT_LOW_LED#

PWR_LED#<33>

PWR_LED#

R813 150_0402_5%

1 2

Blue : Power On,
Blinking Blue : Suspend

47K

2

10K

DTA114YKA_SC59
Q802

1 3

47K

TP_LOCK_LED#<33>

2

10K

DTA114YKA_SC59
Q803

1 3

150_0402_5%

R844

1 2

R845 470_0402_5%

1 2

BLUE

Amber

Blue

Amber

123

BBB

AA

Blue

HT-297UD/NB_BLUE/AMB_0603

Amber

HT-297UD/NB_BLUE/AMB_0603

1 2

HT-191NB5-DT_BLUE_0603~D

TP_ACT

1 2

HT-191NB5-DT_BLUE_0603~D

1 2

HT-191NB5-DT_BLUE_0603~D

TP_LOCK

LED803

LED804

LED805

+5VS

LED801

21

34

+5VALW

LED802

21

34

+5VS

+USB_VCCB

T/P Board

JP804

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

ACES_87151-0807G

A A

ME@

TP_DATA
TP_CLK

+5VS

TP_DATA <33>
TP_CLK <33>

+3VALW

1 2

R195 0_0402_5%

0.1U_0402_16V4Z

LID Switch

1

C286

2

A3212EEHLT-T_SOT23W-3

2

VDD

OUTPUT

GND

1

+3VALW

D19

21

RB751V_SOD323

12

R481
100K_0402_5%

LID_SWITCH#<33>

R193
47K_0402_5%

1 2

3

C287

U13

C483 0.1U_0402_16V4Z

12

SYSON#<31,35>

Pulled up on ICH7M side

C835 ~ C838 For EMI Solution

15P_0402_50V8J

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

USB board

U9

1

GND

2

IN

3

IN

SYSON#

4

EN#

2005/03/10 2006/03/10

+USB_VCCB+5VS

8

OUT

7

OUT

6

OUT

5

FLG

G528_SO8

Compal Secret Data

Deciphered Date

1 2

R816 0_0402_5%

1

C500

1000P_0402_50V7K@

2

EXT_MIC

C835
680P_0402_50V7K

USB_OC#2<21>

USB_OC#4<21>

JACK_PLUG<29>

2

150U_D_6.3VM

PL<30>
PR<30>

680P_0402_50V7K

1

1

+

C826

2

0.1U_0402_16V4Z

USB20_N2<21>
USB20_P2<21>

USB20_N4<21>
USB20_P4<21>

C837

C836

680P_0402_50V7K

Title

Size Document Number Rev

Custom

Date: Sheet of

1

C827

C828
1000P_0402_50V7K

2

2

1 2

R814 0_0402_5%

1 2

R815 0_0402_5%

1 2

R817 0_0402_5%

1 2

R818 0_0402_5%

EXT_MIC<30>
INT_MIC<29,30,38>

JACK_PLUG_MIC<29>

C838
680P_0402_50V7K

EXT_MIC

1 2

R846 0_0402_5%

@

C169
680P_0402_50V7K

Normally Short For JACK_PLUG

Compal Electronics, Inc.

INDICATE LED

HGT30/31 LA3061

星期四二月

23, 2006

1

37 47,

JP27

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

11

11

12

12

13

13

14

14

15

15

16

16

17

17

18

18

19

19

20

20

ACES_87213-2000

ME@

0.1

PDF created with pdfFactory Pro trial version www.pdffactory.com

5

3 IN 1 Card Reader

D D

SDDATA2<26>
SDDATA3_MSDATA3<26>
SDCMD_MSBS<26>

+VCC_4IN1

SDCLK_MSCLK<26>

SDDATA0_MSDATA0<26>

SDDATA1<26>

SDCD#_XDCD0#<26>
SDWP#_XDRB#<26>

SDDATA2
SDDATA3_MSDATA3
SDCMD_MSBS

SDCLK_MSCLK
SDDATA0_MSDATA0

SDDATA1
SDCD#_XDCD0#

SDWP#_XDRB#

2
4
6

8
10
12
14
16
18
20
21
22
23
24
25

4

JP806

3 IN 1 MS/SD/MMC

Connector

DAT2_SD
DAT3_SD
CMD_SD
VSS_SD
VCC_SD
CLK_SD
VSS_SD
DAT0_SD
DAT1_SD
GND_SD
CD_SD
WP_SD
GND_SD
GND
GND

TAISO_143-2300302900_23P_LB

ME@

MS INTERFACE

SD INTERFACE

VSS_MS

VCC_MS
SCLK_MS
DAT3_MS

INS_MS

DAT2_MS

SDIO/DAT0_MS

DAT1_MS

BS_MS

VSS_MS

3

1
3
5
7
9
11
13
15
17
19

SDCLK_MSCLK
SDDATA3_MSDATA3
MSCD#_XDCD1
SDDATA2
SDDATA0_MSDATA0
SDDATA1
SDCMD_MSBS

+VCC_4IN1

SDCLK_MSCLK<26>
SDDATA3_MSDATA3<26>
MSCD#_XDCD1<26>
SDDATA2<26>
SDDATA0_MSDATA0<26>
SDDATA1<26>
SDCMD_MSBS<26>

2

31

GND

32

GND

FOX_GS23302-1010S-7F

ME@

1

UMA LCD/PANEL Conn.

JP805

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

11

11

12

12

13

13

14

14

15

15

16

16

17

17

18

18

19

19

20

20

21

21

22

22

23

23

24

24

25

25

26

26

27

27

28

28

29

29

30

30

(60 MIL)

EDID_CLK_LCD
EDID_DAT_LCD
LVDSBC+
LVDSBC-

LVDSB2+
LVDSB2-

LVDSB1+
LVDSB1-

LVDSB0+
LVDSB0-

LVDSAC+
LVDSAC-

LVDSA1+
LVDSA1-

LVDSA0+
LVDSA0-

LVDSA2+
LVDSA2-

+LCDVDD

+3VS

EDID_CLK_LCD<9>
EDID_DAT_LCD<9>

LVDSBC+<9>

LVDSBC-<9>

LVDSB2+ <9>

LVDSB2- <9>

LVDSB1+ <9>

LVDSB1- <9>

LVDSB0+ <9>

LVDSB0- <9>

LVDSAC+ <9>

LVDSAC- <9>
LVDSA1+ <9>

LVDSA1- <9>

LVDSA0+ <9>

LVDSA0- <9>

LVDSA2+ <9>

LVDSA2- <9>

C C

RJ11+RJ45 CONN

SWITCH BD

Dial Wheel

LED Indicator BD

654321
HML

LED6#
LED5#
LED4#
LED3#
LED2#

LED6#

DTA114YKA_SC59
Q801

1 3

LED4#

DTA114YKA_SC59
Q804

1 3

12

EC_GPIO57
51ON#

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

EC_GPIO57<33>
51ON# <32,39>

Issued Date

3

LED1#

WIRE_LAN_BTN#

2005/03/10 2006/03/10

Compal Secret Data

RJ45_PR

JP809

1
2

EDL71_MDC

JP807

1

TX1+

2

TX1-

3

RX1+

4

TX2+

5

TX2-

6

RX1-

7

RX2+

8

RX2-

RJ45

9

RJ11_1

10

RJ11_2

RJ11

ALLTO_C100B6-110A4-L

ME@

1 2

C840

1000P_1206_2KV7K

4.7U_0805_10V4Z

SGND1
SGND2

0.1U_0402_16V4Z

1

C834

2

Function

KEY Matrix

11
12

C833

1

2

EC_GPIO09<33>

EC_GPIO4A<33>

NOVO BTN

NOVO_BTN#

4

KSI0

DW-UP DW-DOWN

KSI1

DW-ENTER MUTE

2

2

100K_0402_5%

1

DAN202U_SC70

KO16 KO17

47K

10K

47K

10K

+3VALW

R835

D810

2
3

MDO0+<27>
MDO0-<27>
MDO1+<27>
MDO2+<27>
MDO2-<27>
MDO1-<27>
MDO3+<27>
MDO3-<27>

B B

RJ_TIP
RJ_RING

MDO0+
MDO0­MDO1+
MDO2+
MDO2­MDO1­MDO3+
MDO3-

R827

12

0_0603_5%

12

0_0603_5%

R828

RJ45_PR<27>

MDC CONN

A A

RJ_TIP

RJ_RING

5

NOVA_BTN#

KSO16<33>
KSO17<33>
KSI0<32,33>

ON/OFFBTN#<32>

EC_GPIO55<33>
EC_GPIO1D<33>

EC_GPIO4D<33>
EC_GPIO4C<33>

EC_GPIO59<33>

KSI1<32,33>

0.1U_0402_16V4Z

LED6#
LED4#

1

C830

2

NOVO_BTN#

HDD

SATA_LED#<20>

CD-ROM

ODD_LED#<23>

CAPS_LED#<33>

NUM_LED#<33>

C839, C841, C842 For EMI Solution

Deciphered Date

+5VS +VCC5_LED+5VALW

1 2
1 2

KSO16
KSO17
KSI0
KSI1

R821 220_0402_5%

1 2

R822 220_0402_5%

1 2

R823 220_0402_5%

1 2

R824 220_0402_5%

1 2

R825 220_0402_5%

1 2

R826 220_0402_5%

1 2

INT_MIC<29,30,37>

1

C832

C831

2

21

CH751H-40_SC76

21

CH751H-40_SC76

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

2

D808

D809

2

R819 0_0402_5%
R820 0_0402_5%

@

100K_0402_5%

100K_0402_5%

12

12

R829

@

R832 220_0402_5%

1 2

R833 220_0402_5%

1 2

R834 220_0402_5%

1 2

Title

Size Document Number Rev

Custom

Date: Sheet of

C829

1 2

1000P_0402_50V7K

+3VS

100K_0402_5%

12

R831

R830

@

470P_0402_50V8J

C841

1

2

Compal Electronics, Inc.

INDICATE LED

HGT30/31 LA3061

星期四二月

23, 2006

2

C842
1000P_0402_50V7K

1

1

2

C839
1000P_0402_50V7K

1

@

JP808

20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

ME@

ACES_87151-2007L~N

38 47,

0.1

PDF created with pdfFactory Pro trial version www.pdffactory.com

A

PJP1

1

1

1 1

2

2

3

3

4

4

JST_B4B-EH-A(LF)(SN)@

VIN

12

PR1 0

PR12

84.5 K_ 0402_1%

12

12

21

22K_0402_1%

1 2

PR1 4

20K_0402_1%

PU2
G920AT24U_SOT89

3

OUT

PC 1 1

4.7 U _ 080 5_6 .3V6 K

+1.5VS+1.5VSP

+5VALW

+3VALW

A

+VCCP

2 2

12

P C5

100 0 P_0 4 0 2_5 0 V 7K

3.3V

3 3

PR21
560_0603_5%

1 2

+CHGRTC

(6A,240mils ,Via NO.=12) (6A,240mils ,Via NO.= 12)

+5VALWP

(5A,200mils ,Via NO.= 10)

4 4

+3VALWP

(4.5A,180mils ,Via NO.= 9)

+1.05VSP

PR22
560_0603_5%

1 2

RTCVREF

PJ1
PAD-OPEN 3x3m

PJ3
PAD-OPEN 3x3m

1 2

PJ6
PAD-OPEN 3x3m

1 2

PJ7
PAD-OPEN 3x3m

1 2

(5A,200mils ,Via NO.= 10)

ADPIN

12

P C 1

560P_040 2_50V 7K

PR175
10K_0402_1%@

1 2

PR5
1M_0402_1%

1 2

VS

8

3

P

+

2

-

G

4

PR16

10K_0402_1%

12

PR23
200_0805_5%

12

PC 10

O

PU1A
LM393DG_SO8

1U _0 8 0 5_2 5 V 4Z

1 2

1 2

GND

12

P C6

0.1U_0402_16V7K

2

IN

1

+1.8VP

+0.9VSP

(0.3A,40mils ,Via NO.= 2)

+2.5VSP

+VSBP +VSB

1 2

1 2

(0.3A,40mils ,Via NO.= 2)

PL2
FBMA-L18-453215-900LMA90T_1812

1 2

12

P C2

100P_0402_50V8J

PC131

0.01U_0402_25V7K@

1 2

1

RTCVREF

3.3V

PD5

RB751V-40TE17_SOD323-2

BATT+

CHGRTCP

12

PR27
22K_0402_1%

51ON#<32,38>

PJ2

PAD-OPEN 3x3m

PJ4
PAD-OPEN 3x3m

PJ11
PAD-OPEN 3x3m

PJ8
PAD-OPEN 3x3m

1 2

+1.8V

+0.9VS

+2.5VS

12

12

P C3

100P_0402_50V8J

VS

12

P R9

10K_0402_1%

12

P D3

RLZ 4.3B_LL34

12

12

PR2 6

P C4

560 P _04 0 2 _50 V 7 K

12

PR1 5

12

100K_0402_5%

B

PR11
10K_0402_5%

1 2

PACIN

10K_0402_1%

PQ4
TP0610K-T1-E3_SOT23

PC1 2

0.22U_1 206_2 5V7K

B

C

ACIN

Precharge detector
Min. typ. Max.

H-->L 14.620V 14.853V 15.245V

VIN

12

P R1

10_1206_5%

12

P D1

RLZ24B_LL34

ACIN <21,33>

PACIN <41>

L-->H 15.534V 15.970V 16.421V

PR2
1K_1206_5%

1 2

ACOFF<33,41>

PR3
1K_1206_5%

1 2

PR4
1K_1206_5%

1 2

PR8
1K_1206_5%

1 2

DTC115EUA_SC70

VIN

PD2
RLS4148_LLDS2

12

Vin Detector

High 18.384 17.901 17.430
Low 17.370 16.907 16.630

VIN

P D4

1 2

RLS 4148_LLDS2

12

VS

PR20

33_1206_5%

13

12

PC 13

2

0.1 U_060 3_25 V7K

VL

12

PR19

PD6
RB715F_SOT323

MAINPWON<40,42>

ACON<41>

2
3

100K_0402_1%

1

LM393DG_SO8

12

PC8

0.1U_0603_25V7K

7

O

PU1B

PR28
34K_0402_1%

PR17

2.2M_0402_5%

VS

8

4

RTCVREF

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2005/08/01 2006/08/01

Compal Secret Data

Deciphered Date

C

D

BATT ONLY

Precharge detector

Min. typ. Max.
H-->L 6.169V 6.231V 6.361V
L-->H 7.168V 7.349V 7.537V

PQ1
TP0610K-T1-E3_SOT23

13

12

12

P R6

P R7

10 0 K_0 4 0 2_5 %

13

2

PQ2

DTC115EUA_SC70

12

5

P

+

6

-

G

12

P C9

1000P_0402_50V7K

12

12

PR30

@

66.5K_0402_1%

Title

Size Document Number Rev

B

Date: Sheet of

2

100K_0402_5%

12

PR1 3

100K_0402_5%

13

2

PQ3

12

PR24

191K_0402_1%

PRG ++

PQ5
RHU002N06_SOT323

13

D

2

G

S

13

PQ6
DTC115EUA_SC70

Compal Electronics, Inc.

DCIN/DECTOR

星期

, 20, 2006

一二月

D

12

PR1 8

12

PR25

PR29

47K_0402_5%

12

2

B+

499K_0402_1%

12

499K_0402_1%

39 48

PC7

0.0 1U_04 02 _2 5V 7K

PACIN<41>

+5VALWP

0.1

PDF created with pdfFactory Pro trial version www.pdffactory.com

A

PJP2

BATT+

ID
B/I
TS

1 1

2 2

3 3

SMD
SMC
GND

SUYIN_250005MR007G161ZL_7P_RV@

SPOK<42>

BATT_S1

1

ALI/NIMH#

2

AB/I

3

TS_A

4

EC_SMDA

5

EC_SMCA

6
7

12

12

PR3 1

PR3 5

100_0402_1%

100_0402_1%

B+

PR42

2

G

PC 22

22K_0402_1%

1 2

13

D

PQ8

S

RHU002N06_SOT323

VL

PR 43

1 2

PR44

100K _0402 _5%

0_0402_5%

1 2

12

PR177
1K_0402_1%

1 2

12

12

PR3 8

1K_0402_1%

PJ22

PAD-OPEN 3x3m

PR176

1K_0402_1%

12

P R 41

10 0 K_040 2_5 %

12

PR178
47K_0402_5%

1 2

PR36

6.49K_0402_1%

1 2

12

PC2 0

0.22U_1206_25V7K

PQ7

TP0610K-T1-E3_SOT23

2

+3VALWP

13

B

12

+3VALWP

12

C

BATT++

PL3
FBMA-L18-453215-900LMA90T_1812

1 2

12

PC14

1000P_0603_50V7K

PC 15

100 0 P_0 6 0 3_5 0 V 7K

ALI/MH#

BATT_TEMP<33>

EC_SMB_DA1<33,34>
EC_SMB_CK1<33,34>

12

PC16

0.01U_0603_50V7K

BATT+

PH1 under CPU botten side :

CPU thermal protection at 85 degree C
Recovery at 70 degree C

VL

12

12

12

PC1 8

1000P_0402_50V7K

PR3 3

10.7K_0402_1%

PR37

61.9K_0603_1%

1 2

TM_REF1

PH1

12

100 K_0603_1%_TH11-4H104FT

12

PC17

PC 19

1U _0 6 0 3_6 .3 V 6M

12

0.1U_0603_25V7K

3
2

PR39
150K_0402_1%

P R 40

15 0K_04 02_ 1%

8

+

-

4

VS

1 2

P

G

12

PR34
442K_0603_1%

O

PU3A

LM393DG_SO8

D

VL

PR3 2

1 2

150K_0402_1%

1

VL

MAINPWON<39,42>

VS

+VSBP

8

PC2 1

0.1U_0603_25V7K

5
6

PU3B

LM393DG_SO8

P

+

7

O

-

G

4

0. 1 U_0 4 02_ 1 6 V 7K

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

B

2005/08/01 2006/08/01

Compal Secret Data

Deciphered Date

C

Title

Size Document Number Rev

B

Date: Sheet of

Compal Electronics, Inc.
BATTERY CONN. / OTP

星期

, 20, 2006

一二月

D

40 48

0.1

PDF created with pdfFactory Pro trial version www.pdffactory.com

A

65W PR45=0.02_2512_1% PR54=30K_0402_1%
90W PR45=0.02_2512_1% PR54=20K_0402_1%

1
2
36

4

12

12

PR55

150K_0402_1%

13

D

PQ17

S

RHU002N06_SOT323

P2

PC27

0.1U_ 0603 _25V 7K

IREF <33>

PQ9

AO4407_SO8

8

PQ12

47K _0402_5%

2

13

PD12
RLS4148_LLDS2

PR66
22K_0402_1%

1 2

7
5

47K

47K

1 3

PQ15
DTC115EUA_SC70

2

G

VIN

1 1

12

PR47

DTA144EUA_SC70

2

13

D

2

G

2 2

PACIN<39>

ACOFF#

S

PQ16
RHU002N06_SOT323

1 2

12

PR46

200K_0402_1%

PR60
133K_0402_1%

PQ10
AO4407_SO8

1
2
3 6

4

MB39A126

1 2

12

12

PC31

PR53

10K_0402_1%

0.01U_0402_25V7K

1 2

12

PR63

PR51
10K_0402_1%

12

12

100K_0402_1%

IREF=0.932*Icharge

ACON<39>

3 3

4 4

IREF=0.466~2.61V
I fast charge=2.8A

FSTCHG<33>

PR54

8
7

5

NA

20K_0402 _ 1 %

PC33

0.22U_060 3_16V7K

12

2

PC28
4700P_0402_25V7K

MB39A126

PC39

0.01U_040 2_25V7K

+3VALWP

12

13

1

B

1 2

PR57
1K_0402_1%

1 2

PR67

47K _0402_5%

2

PQ19
DTC115EUA_SC70

VS

8

3

P

+

0

2

-

G

PU12A

4

LM358A_SO8

Iadp=0~3.125A
Iadp=0~4.166A

PR45

0.02_2512_1%

4

213

PR52
100K_0402_1%

12

PC34
2200P_0402_50V7K

1 2

PR61
10K_0402_1%

12

PR65

0_0402_5%

CS

13

PQ18
DTC115EUA_SC70

B+

PU4
MB39A126PFV-ER_SSOP24

1

-INC2

2

OUTC2

3

+INE2

4

-INE2

5

ACOK

6

VREF

7

ACIN

8

-INE1

9

+INE1

10

12

OUTC1

11

SEL

12

-INC1

+INC2

XACOK

-INE3

FB123

+INC1

GND

VCC

OUT

CTL

CS

VH

RT

24

23

22

21

20

PC32

0.1U_0603_25V7K

19

18

17

16

15

14

13

BATT_OVP<33>

C

PR58
47K_0402_1%

MB39A126

Fosc=14100/Rt=14100/47=300KHz

PL4
FBMA-L11-322513-201LMA40T_1210

1 2

P2

12

PR49

0_0603_5%

PC29

0.22U_0603_16V7K

1 2

1 2

PR62
33K_0402_1%

1 2

PC40
10P_0402_50V8J

CS

1 2

1 2

PC30

0.1U_0603_25V7K

1 2

PC35
1500P_0603_50V7K

1 2

VIN

LI-3S :13.05V----BATT-OVP=1.45V
BATT-OVP=0.111*BATT+

7

0

12

PC23

12

PR59

47K _0402_5%

12

PR64

47K _0402_5%

+

-

PU12B
LM358A_SO8

12

4.7U_ 1206 _25V 6K

578

PC41
47P_0402_50V8J

1 2

VS

12

PC42

0.01U_0402_25V7K

5
6

D

CHG_B+

12

PC24

36

PC25

4.7U_1206_25V6K

0.1U_ 0603 _25V 7K

241

PQ13
AO4407_SO8

PL5

LXCHRG

10U_LF919AS-100M-P3_4.5A_20%

1 2

12

12

PD11

PD10

EC31QS04

EC31QS04

BATT+

12

PR68

340K_0402_1%

12

PR69

499K_0402_1%

12

PR72

105K_0402_1%

E

Charger

PQ11
AO4407_SO8

1
2
3 6

12

PC26

2200P_ 0402_50V7K

PR56

0.02_2512_1%

12

PC43

213

0.01U_040 2_25V7K

8
7

5

4

PR48
47K_0402_1%

1 2

PR50

10K_0402_1%

1 2

ACOFF#

13

2

PQ14
DTC115EUA_SC70

4

ACOFF

VIN

ACOFF<33,39>

BATT+

12

12

PC36

12

PC37

PC38

4.7U_ 1206 _25V 6K

4.7U_1206_25V6K

4.7U_1206_25V6K

CC=2.8A

(100K/(100K+133K))*2.61V=1.12V

1.12/(20*0.02)=2.8A

90W HGT30 CP Point=4.166A
5V*(10K/(30k+10k))=1.666V

1.666V/(20*0.02)=4.166A

65W HGT31 CP Point=3.125A
5V*(10K/(30K+10K))=1.25V

1.25V/(20*0.02)=3.125A

Charge voltage
3S CC-CV MODE : 12.6V
SEL is L

BATT+

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

PDF created with pdfFactory Pro trial version www.pdffactory.com

2005/08/01 2006/08/01

C

Compal Secret Data

Deciphered Date

D

Title

Size Document Number Rev

B

Date: Sheet of

Compal Electronics, Inc.

PWR-Charger

星期一二月

20, 2006

41 48,

E

0.1

A

B+

PL6
FBMA-L11-322513-201LMA40T_1210

1 2

1 1

PJ23

PAD-OPEN 3x3m

MAX8743_B+

B+++

12

12

12

PC4 8

PC4 7

2200P_0402_50V7K

10U_1206_25VAK

D8D7D6D

S1S2S3G

5

PQ21

4

5

PC45

0.1U_0603_25V7K

1 2

SI4 800BDY-T1-E3_SO8

5HG

PR78
0_0603_5%

1 2

LX5

D8D7D6D

2 2

+5VALWP

1

+

P C 56

2

15 0 U_V_6 .3V M_R18

PL7

1 2

4.7U H_ PC MC0 63T-4R7MN_5.5A_20%

PR8 5

1 2

10.2K_04 02 _1 %

@

PR8 7

0_0402_5%

1 2

VS

+5V Ipeak = 6.5A ~ 10.4A

3 3

S1S2S3G

4

PZD1
RLZ5.1B_LL34

1 2

PQ29

SI4 810BDY-T1-E3_SO8

DL5

PR88
47K_0402_5%

1 2

12

PR9 1

1 2

100K_0402_5%

DH5

P C 57

0. 047U_ 0 60 3 _1 6 V7K

B

PR7 4

1 2

PR94
47K_0402_5%

1 2

C

PC46

200K_0402_1%

374K_0402_1%

1 2

0.1U_0603_25V7K

1 2

MAX8743_B+

PR7 9

0_0603_5%

BST3A

DH3

PJ24

12

PAD-OPEN 3x3m

12

12

PC5 0

PC5 1

2200P_0402_50V7K

10U_1206_25VAK

LX3

PR8 2

0_06 03 _5 %

1 2

DL3

3

2

PD13
CHP202U_SC70

1

MAX8743_B+

12

0_0603_5%

P R 76

4.7_1 206 _5 %

12

VL

PC5 2

12

PC54

4.7U _0805_6.3V6K

BST5A

1 2

PR86
0_0402_5%

2VREF_1999

PR89

0_0402_5%

1 2

12

14

BST5

16

DH5

15

LX5

19

DL5

21

OUT5

9

FB5

1

N.C.

MAX8734AEEI+_QSOP28

6

SHDN#

4

ON5

3

ON3

12

SKIP#

8

REF

PC5 9

0.22U_0603_16V7K

18

LD05

GND

23

1U_ 0805_25V4Z

20

PU6

VL

12

PC5 5

12

V+

LDO3

25

12

P R 75

PR 77

1 2

47 _0 4 02 _ 5%

4.7 _ 120 6 _ 5 %

@

12

0.1U_0603_25V7K

13

17

5

TON

VCC

ILIM3

11

ILIM5

28

BST3

26

DH3

24

DL3

27

LX3

22

OUT3

7

FB3

2

PGOOD

PRO#

10

PC60

PR92

0_0402_5%

4.7U _0805_6.3V6K

1 2

12

2VREF_1999

PC5 3

1U_0805_ 16 V7 K

SPOK<40>

BST3BBST5B

P C 49

0. 1U_ 04 0 2_ 1 6V7K

PR8 1

PR8 0

1 2

1 2

200K_0402_1%

PR83

PR8 4

1 2

1 2

374K_0402_1%

12

PC6 1

0.047U_0603_16V7K

+3.3V Ipeak = 6.5A ~ 8.26A

3HG

1 2

1 2

D

5

D8D7D6D

PQ20

S1S2S3G

4

SI4 800BDY-T1-E3_SO8

5

D8D7D6D

PQ30

S1S2S3G

4

SI4 810BDY-T1-E3_SO8

PL8

1 2

+3VALWP

4.7U H_ PC MC0 6 3T-4R7MN_5.5A_20%

PR9 0

3.57K_0402_1%@

PR9 3

0_0402_5%

1

+

PC5 8

2

150 U_V_6.3V M_R18

MAINPWON<39,40>

12

P C 62

1U _0 603 _6 . 3 V6M

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

B

2005/08/01 2006/08/01

Compal Secret Data

Deciphered Date

C

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

+5VALWP/+3VALWP

星期

, 20, 2006

一二月

D

42 48

0.1

PDF created with pdfFactory Pro trial version www.pdffactory.com

5

4

3

2

1

+1.8VP Ilimit = 7.87A~12.5A

+1.05VSP Ilimit=6.33A~10.03A

D D

OZ813_B+

PR98

PC80

12

12

12

22P_0402_50 V8J

OZ813_B+

12

PR107

12

12

22P_0402_50V8J

PL9
FBMA-L11-322513-201LMA40T_1210

1 2

28mohm

+1.8VP

1

+

PR95

PC66

51_0402_1%

2

220U_D2_4VM_R15

PC70

4700P_0402_25V7K

28mohm

51_04 02_1%

PC82

4700P_0 402_25V7K

+1.05VSP

1

+

PC78

2

220U_D2_4 VM_R15

B+

PJ25

PR262

0_0402_5%

1 2

18
17
16
15
14
13

12

BST_1.8V

12

+3VALWP

12

PR261

1K_ 0402_1%

PQ23

SI4810BDY-T1-E3_SO8

PC67

0.1U_0603_25V 7K

DL_1.8V

RB751V-40TE17_SOD323-2

PD16

1 2

+5VALWP

12

PC71
1U_0805_16V7K

PD17

BST_1.05V

1 2

RB751V-40TE17_SOD323-2

PC76

0.1U_0603_25V7K

DL_1.05V

5

4

5

4

D8D7D6D

S1S2S3G

D8D7D6D

S1S2S3G

D8D7D6D

S1S2S3G

PQ24

D8D7D6D

PQ31

S1S2S3G

5

PQ22

4

SI4800BDY-T1-E3_SO8

5

4

12

PC156

2.2U_0603_6.3V6K

12

PC79

10U_1206_25VAK

SI4800BDY-T1-E3_SO8

SI4810BDY-T1-E3_SO8

1.8VS2N

1.8VS2P

12

PR105

1 2

75K_0402_1%

1 2

150K_0402_1 %

+5VALWP

PR99

22_0402_1%

DREF

PR104

1 2

100K_0402_1 %

1.05SET

PR172

61.9K_0402_1%

1 2

12

PR100

1 2

1K_0402_1%

12

PC74

1U_0603_6.3V6M

PC132

0.1U_0402_16V7K

1 2

12

PC75

0.01U_0402_25V7K

1.8VSET

12

PC65

1000P_0402_50V7K

PU7

25

GNDA

1

ON/SKIP2

2

VIN

3

VREF

4

TSET

5

VDDA

6

ON/SKIP1

OZ813LN_QFN24

12

PC77

1000P_0402_50V7K

24

PR266

0_0402_5%

SYSON<33,35,37>

C C

12

12

PC184

0.01U_0402_25V7K

@

PR101

0_0402_5%

12

12

PC72

PR103

@

PC73

1 2

24K_0402_1%

0.1U_0603_25V 7K

0.022U_0402_16V7K

1.8VSET

PR106

B B

PR179

100K_0402_1%

1 2

SUSP#<18,24,26,33,34,35,37,44>

21

23

CS2P22CS2N

PGD2

VSET2

VSET17CS1N8CS1P9PGD110LX111HDR1

PR263

1 2

12

PR264

+3VALWP

DH_1.8V
LX_1.8V

19

20

LX2

HDR2

BST2

LDR2
VDDP
GDNP

LDR1

BST1

12

DH_1.05V

LX1.05V

0_0402_5%

1.05VS1P

1.05VS1N

1K_ 0402_1%

PAD-OPEN 3x3m

12

PC63

10U_1206_25VAK

PL10

3.3UH_PCMC063T-3R3MN_6A_20%

1 2

PR97

1.8VS2P

1.8VS2N

+5VALWP

PJ26

PAD-OPEN 3x3m

PL11

1 2

PR108

1.05VS1P

1.05VS1N

22K_0402_1%

1 2

PC68
6800P_0402_25V7K

1 2

12

PC69

12

PR109

29.4K_0402_1%

1 2

5600P_0402_50V7K

12

PC81

100K_0402_1%

1 2

3.3UH_PCMC063T-3R3MN_6A_20%

100K_0402_1%

1 2

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/08/01 2006/08/01

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

2

Date: Sheet of

Custom

1.05VP/1.8VP

,

星期一二月

20, 2006

0.1

43 48

1

PDF created with pdfFactory Pro trial version www.pdffactory.com

5

4

3

2

1

+1.5VSP Ilimit = 9.38A~12.5A

D D

C C

B B

SUSP#

43>

A A

PL12

1 2

B+

FBMA-L11-322513-201LMA40T_1210

SUSP#<18,24,26,33,34,35,37,43>

PR121

33K_0402_1%

1 2

PC100

0.01U_0402_25V7K

PJ27

12

PAD-OPEN 3x3m

PR114

1 2

47K_0402_5%

12

PC83

10U_1206_2 5 VAK

6269_VCC

12

PC87

2.2U_0603_6.3V6K

12

PC89

0.01U_0402_25V7K

PR113

1 2

0_0402_5%

PR265

10K_0402_1%

1 2

1

2

3

4

PU8

VIN

VCC

FCCM

EN

17

GND

COMP5FB6FSET

12

12

PC9 1

22P_0402_50V8J

+3VS

+5VS

12

PC93

1U_0603_6.3V6M

6

PU10

7

POK

8

EN

12

5

VIN

4

VOUT

VCNTL

3

VOUT

2

FB

9

VIN

GND

1

APL5912-KAC-TRL_SO8

1

PJ10

1

JUMP_43X79

2

2

12

PC96
22U_1206_6.3V6M

PR122

2.15K_0402_1%

12

12

PR125

1K_0402_1%

12

PC99

0.01U_0402_25V7K

PC97

PR116

49.9K_0402_1%

12

PC92
6800P_0402_25V7K

3K_0402_1%

+2.5VSP

1

12

+

PC98

150U_D_6.3VM@

2

22U_1206_6.3V6M

16

PGOOD

57.6K_0402_1%

PR119

15UG14

PHASE

PR117

12

PHASE_VCCPP

7

12

SUSP<35>

PR110

1 2

0_0603_5%

BOOT_VCCPP

13

BOOT

PVCC

LG

PGND

ISEN

VO

8

12

PC90

0.01U_0402_25V7K

12

12

2.2U_0603_6.3V6K

11

10

ISEN_VCCPP

9

1 2

8.66K_0402_1%

ISL6269CRZ-T_QFN16

4.53K_0402_1%

100K_0402_1%

1 2

UG_VCCPP

1 2

PC850.1U_0402_16V7K

PR111

4.7_0603_5%

@

PR112

1 2

4.7_0603_5%

1 2

LG_VCCPP

PR115

PR118

1 2

PC94

22U_1206_6.3V6M

PR123

+5VS

6269_VCC

PC86

+1.8VP

RHU002N06_SOT323

PQ28

2

G

12

PC103

0.1U_0402_16V7K

1

1

2

2

12

PJ9

JUMP_43X118

1K_0402_1%

13

D

S

12

PR120

12

PR124
1K_0402_1%

5

4

5

4

PC101

0.1U_0402_16V7K

PQ26

D8D7D6D

S1S2S3G

SI4800BDY-T1-E3_SO8

1 2

3.3UH_PCMC063T-3R3MN_6A_20%

PQ27

D8D7D6D

SI4810BDY-T1-E3_SO8

S1S2S3G

PU9

2
3
4

APL5331KAC-TRL_SO8

12

PC102
22U_1206_6.3V6M

+0.9VSP

12

PL13

VIN1VCNTL
GND
VREF
VOUT

+1.5VSP

1

+

PC88
220U_D2_4VM_R15

2

6
5

NC

7

NC

8

NC

9

TP

+3VALWP

12

PC95
1U_0603_6.3V6M

5

4

PDF created with pdfFactory Pro trial version www.pdffactory.com

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/08/01 2006/08/01

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Custom

星期一二月

+VCCPP/+2.5VSP/0.9VSP

,

20, 2006

1

0.1

44 48

5

D D

PR217

13K_0402_1%@

NTC

0_0402_5%

PR218

1 2

1 2

1 2
1 2
1 2

2K_0402_1%@

1 2

1 2

PR249

0_0402_5%

PR253 0_0402_5%@

12
12
12
12
12
12

PR241

10K_0402_5%

@
1 2

1 2

1 2

PC181

0.1U_0402_16V7K

1 2

PR250

56_0402_5%

PR25410K_0402_5%

PR2190_0402_5%
PR2210_0402_5%
PR2220_0402_5%
PR2230_0402_5%
PR2250_0402_5%
PR2270_0402_5%
PR2280_0402_5%

C C

PR233 499_0402_1%
PR234 0_0402_5%
PR236 0_0402_5%

0_0402_5%

VGATE<21>

CLK_ENABLE#<15>

RHU002N06_SOT323

B B

A A

1 2

1 2

13

D

PQ38

S

PR244

0_0402_5%
PR247

@

2

G

CPU_VID0<5>
CPU_VID1<5>
CPU_VID2<5>
CPU_VID3<5>
CPU_VID4<5>
CPU_VID5<5>
CPU_VID6<5>

DPRSLPVR<7,21>
H_DPRSTP#<4,20>

H_PSI#<5>

+3VS

PR240

2.1K_0402_1%

1 2

VR_ON<33>

H_PROCHOT#<4>

POUT

1 2

PR232 71.5K_0402_1%

1 2

PC170 0.22U_0603_16V7K

+3VS

12

PR252

4

+5VS

PR214

PR215
10_0402_5%

PC165
1U_0603_6.3V6M

1 2

PU11

19

Vcc

6

THRM

31

D0

32

D1

33

D2

34

D3

35

D4

36

D5

37

D6

7

TIME

9

CCV

11

REF

39

DPRSLPVR

40

DPRSTP

3

PSI

2

PWRGD

1

CLKEN

38

SHDN

5

VRHOT

4

POUT

MAX8770GTL+_TQFN40

VSSENSE<5>

5VS1

12

VCC

12
12

PC168470P_0402_50V8J

12

0_1206_5%

PC164

2.2U_0603_6.3V6K

VDD
TON

BST1

DH1

LX1
DL1

PGND1

GND
CSP1
CSN1

FB

CCI

DH2

BST2

LX2
DL2

PGND2

CSP2
CSN2

GNDS

41

1000P_0402_50V7K

VSSENSE

12

12

PR216

1 2

25
8
30
29
28
26
27
18
17
16
12
10
21
20
22
24
23
14
15
13

TP

PC174

100_0402_5%

@10_0402_5%

200K_0402_5%

0_0402_5%

PR220

BST1_CPU BSTM1_CPU

1 2

DH1__CPU
LX1__CPU
DL1__CPU

CSP1__CPU
CSN1_CPU
FB_CPU
CCI_CPU
DH2_CPU
BST2_CPU
LX2_CPU
DL2__CPU

CSP2_CPU
CSN2__CPU

1 2

PR251

1 2

12

PR255

3

CPU_B+

PC157

0.01 U_0402_25V7K

0.22U_0603_16V7K

PR239

0_0402_5%

1 2

BST M2_CPU

12

PC175

0.22 U_0603_16V7K

PC166

1 2

2.2_0603_5%
PR267

1 2

2.2_0603_5%
PR268

1 2

PQ33

PR238 3K_0603_1%@

PR242 3.65K_0402_1%

1 2

NTC

PR245

3K_0603_1%@

1 2

PR248

20K_0402_1%

PQ37

FDS6 676AS_SO8

5

4

FDS6 676AS_SO8

1 2

1 2

5

4

2

D8D7D6D

S1S3G

S

2

SI7840DP_SO8

DHS

D8D7D6D

S1S3G

S

DL1__CPU

PQ35

PQ34

FDS6 676AS_SO8

1 2

PR246
3K_0603_1%@

PQ36

DL2__CPU

PQ32
SI7840DP_SO8

3 5

241

5

D8D7D6D

S1S3G

S

4

2

PR2370_0402_5%

1 2

1 2

PC173

470P_0402_50V8J

29.6

3 5

241

5

D8D7D6D

S1S3G

S

4

2

FDS6 676AS_SO8

PR2600_0402_5%

1 2

2

PC159

10U_1206_25VA K

PR224

PR256

12

12

4.7 _1206_5%

12

1 2

12

4.7_ 1206_5%

12

12

12

PC161

PC160

10U_1206_25VA K

10U_1206_25VA K

P_0.36H_ETQP4LR36WFC_24A_20%

PR226

3.48K_0402_1%

2.1K _0402_1% 1 2
PR230

1 2

PC167

PC169 0.22U_0603_16V7K

680P_0603_50V7K

PC171 0.022U_0402_16V7K@

1 2

1 2

PR243 100_0402_5%

PC172
4700P_0402_25V7K

12

PC182

680P_0603_50V7K

FBM-L11-322513-201LMAT_1210

12

12

PC162

PC163

0.1U _ 0603_25V7K

1 2

PC176

PR257

2.1K_0402_1%

2200P_0402_50V7K

PL15

12

NTC

10K_0603_5%

PR231

1 2

CPU_VCC_SENSE

12

12

PC177

10U_1206_25VA K

10U_1206_25VA K

PL16

P_0.36H_ETQP4LR36WFC_24A_20%

PR258

3.48K_0402_1%

1 2

PC183 0.22U_0603_16V7K

PL14

PC178

10U_1206_25VA K

1 2

12

12

12

1

+

2

+CPU_CORE

12

VCCSENSE<5>

PR229 10_0402_5%

CPU_B+

12

PC179

0.1U _0603_25V7K

NTC

PR259

10K_0603_5%

1 2

B+

PC158

PC180

100U_25V_M

1 2

12

2200P_0402_50V7K

1

+CPU_CORE

PR235
0_0402_5%

Security Classification Compal Secret Data

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

PDF created with pdfFactory Pro trial version www.pdffactory.com

2005/06/20 2006/06/20

3

Deciphered Date

Compal Electronics, Inc.

星期一二

?20, 2006

+CPU_CORE

1

45 48,

0.1

Title

Size Document Number Rev

Custom

2

Date: Sheet of

5

4

3

2

1

Version change list (P.I.R. List) Page 1 of 1

for PWR

Reason for change Rev. PG# Modify List VER PhaseFixed IssueItem

1

D D

MODIFY 3V/5V current limit to 6.5A~8.1A/6.5A to 10.2A

42 MODIFY PR83/PR84 FROM 499K TO 374K DVT

2

3
4

5

6

C C

7

ADD or decrease CPU CORE ring with EMI solution :
snubber

Reserve PR267,PR268 seperate in CPU CORE high
side gate for EMI require

change PJP1 from 5 pin to 4 pin 39

modify sequecce 43 change PR179 to 100k, PC132 =0.1U DVT

modify Vgate

Reserve PR224//PR256: 4.7 1206 ,add

45 DVT

PC167/PC182:680P

Reserve PR267,PR268:0 0603

45

change PJP1 from 5 pin to 4 pin

add PQ38:RHU002N06,PR240:2K,delete PR247

45

DVT

DVT

8

9

10

11

B B

8

9

A A

Title

Size Document Number Rev

5

4

3

2

Date: Sheet of

Compal Electronics, Inc.

PIR (PWR)

星

, 20, 2006

期一二月

46 48

0.2

1

PDF created with pdfFactory Pro trial version www.pdffactory.com

A

B

C

D

E

Version change list (P.I.R. List) Page 1 of 1

Rev. PG# Modify List B.Ver#PhaseFixed IssueItem

1 1

Add EC_Port80 Signals to DDR2 DIMM1 & DIMM2

1

0.2

P.13

1.Connect U6.91 (EC_P80_CLK) through a 0 Ohm R to JP3.83 & JP4.83

P.14

2.Connect U6.92 (EC_P80_DATA) through a 0 Ohm R to JP3.69 & JP4.69

0.2

DVT

Impedance not match for both CRT & TV Out

2

LCD Panel will flash white frame when power on

3

ICH7's GPIO configuration modification

4

0.2 P.17

0.2 P.16

0.2

P.21

R3, R4, R5, R6, R7, R8 Change from NC to 150 Ohm

no stuff D10 (CH751H), stuff R204 (100K)

GPIO10 connect to ACIN
GPIO7 connect to G7X_THER_ALERT#

0.2

0.2

0.2

DVT

DVT

DVT

GPIO39 connect to KILL_MDC#

<New Add> MDC supports S4/S5 resuming

5

2 2

Audio Circuit modification for :

6

1. Line-Out connection change from Pin.35/Pin.36 to Pin.43/Pin.45

2. Audio-OUT Auto-Switch by HP Pluging In

0.2 P.28

0.2

3. MicPhone Noise Reduction

4. Cleared off BO Sound from both entry of Windows XP & Power Off

MDC power connection change to +3VALW from +3VS

Line-Out connection change from Pin.35/Pin.36 to Pin.43/Pin.45
Connect Pin.32 (LFE_OUT) through 2 1uF Cap to Pin.43/Pin.45
+Audio_VREF_LF connection change to 1/2 +AVDD_AC97
Int.MIC connection changes to Pin31/Pin32 through 1uF for each

P.29-31

New Add a JACK_PLUG_MIC signal from MIC JACK
EAPD signal connect to EC'sGPIO4B

0.2

DVT

DVT0.2

APA2068's 13PIN(SE/BTL#) connect to GND

EC GPIO configuration modification

New add Port80 information OUT from Pin34(CLK), pin35(DATA)
LED4 connection changes from GPIO17(35 PIN) to GPIO4A(91 PIN)
New Add DAC’s EAPD connect to EC’s GPIO4B (92PIN).
SKU_ID (GPIO3B) Changes to BRD_ID

7

0.2

New Add WL_OFF# (GPIO1F, 46PIN)

P.33

0.2

DVT
New Add BT_OFF# (GPIO50, 84PIN)
New Add TP_ACT_LED# (GPIO3F, 80PIN)

3 3

Lid Switch changes from USB BD to M/B

8

Blue LED too dark when active due to VF too High on blue LED

9

New Add LED Buffer for LED4, TP_LOCK_LED#, TP_ACT_LED#

0.2 P.37

0.2 P.37-38

0.2 P.37

10

New Add TP_LOCK_LED# (GPIO12, 30PN)

Circuit of Lid SW changes from USB BD to M/B (DEL Lid SW on USB BD)

Changes LED power from +3VS(+3VALW) to +5VS(+5VALWS)

TP_ACT_LED# connect to Q802.2, and Q802.1 to GND,
then connect to LED804 through a 220 Ohm R

TP_LOCK_LED# connect to Q803.2, and Q802.1 to GND,

0.2

0.2

0.2

DVT

DVT

DVT
then connect to LED805 through a 220 Ohm R

P.38

EC_GPIO4A connect to Q804.2, and Q804.1 to GND,
then connect to R283 (220 Ohm)

leakage of electricit when System is running S3 mode

11

4 4

0.2

NC For R458, R402, R411, R128, R831, R829

0.2

DVT

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

PDF created with pdfFactory Pro trial version www.pdffactory.com

Compal Electronics, Inc.

Title

PIR

Size Document Number Rev

HGT30/31 LA-3061

C

D

Date: Sheet of

二月

47 48 星期@, 20, 2006

E

0.0

A

B

C

D

E

Version change list (P.I.R. List) Page 1 of 1

Rev. PG# Modify List B.Ver#PhaseFixed IssueItem

1 1

GIGA LAN function failed for both Loopback or PXE on RTL8110SCL solution

12

0.3 P.27

1. Add a R734 (0 Ohm) resistor between +2.5V_LAN & VTCT for MAC

2. Removed all of the bypass Cap.(C398, C396, C418, C408)

for MAC's TCT pins

3. Removed all of pulled down resistors (49.9 Ohm) & Cap.(0.01u)

0.3

PVT

Subwoofer still make POP Sound

13

0.3 P.31

1. Add 0 Ohm resistors, R732 (0 Ohm) connection between AMP_OFF# &
U12.2 (SD#) for reserved

0.3

PVT

2. a 0 Ohm connection between EAPD & U12.2(SD#)

Mic Switch between Int. & Ext. be Failed

14

Wrong parts

15

0.3

0.3 P.35

1. R717.1 Disconnect from U11.17

P.29

2. R717.1 connect to U11.16

Change package of C434, C224 & C312 from 0402 to 0603

0.3

0.3

PVT

PVT

1. Connect +3.3VS to R731.1

2 2

Add a discharging path of +3.3VS

16

0.3 P.35

2. Connect R731.2 to Q704.1

3. Connect Q704.2 to NET : SUSP signal

PVT0.3

4. Connect Q704.3 to GND

3 3

4 4

Compal Electronics, Inc.

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

D

PIR

Size Document Number Rev

HGT30/31 LA-3061

Date: Sheet of

二月

48 48 星期@, 20, 2006

E

0.0

PDF created with pdfFactory Pro trial version www.pdffactory.com