COMPAL LA-3051P Schematics
A
1 1
B
C
D
E
LC2A Schematic
2 2
Pentium-M
945GM+ICH7
DATE: Sept. 10th Revision: 0.2
3 3
4 4
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITT EN CON SENT O F COMPAL ELECTRONICS, INC.
2005/09/10 2006/06/23
C
Compal Secret Data
Deciphered Date
Title
Size Document Number Rev
D
Date: Sheet
Compal Electronics, Inc.
SCHEMATIC, M/B LA-3051P
星期
四十月
401397
, 06, 2005
E
145
A
of
Page Function
5
4
3
2
1
1 Cover Page
2
3
4
D D
5
6
7
8
9
10
11
12
13
14
15
C C
16
17
18
19
20
21
22
23
24
25
B B
26
27
28
29
30
31
32
33
34
35
36
A A
37
38
39
40
41
42 PWR-CPU_CORE
5
Index
Block Diagram
Notes List
Power Block
Yonah(1/2)-GTL/ITP-XDP
Yonah(2/2)-PWR/GND
Yonah bypass
Calistoga(1/6)-GTL/DMI/DDR
Calistoga(2/6)-DDR2 A/B CH
Calistoga(3/6)-VGA/LVDS/TV
Calistoga(4/6)-PWR
Calistoga(5/6)-PWR/GND
Calistoga(6/6)-PWR/GND
DDRII-SODIMM2
DDRII SO-DIMM B
ClockGen
TV-OUT/LVDS/CRT
ICH7M(1/4)_HUB,PCI,HOST
ICH7M(2/4)LAN,ATA,LPC,RTC
ICH7M(3/4)USB,GPIO,PCIE
ICH7-M(4/4)_POWER&GND
SATA/CD_ROM/G-SENSORConn.
USB/BlueTooth/FP
BCM5751M-GLAN
RJ-45 Connector
MINI_CARD SLOT-WLAN
R5C842-PCI/CARD BUS/OHCI
CARD BUS/1394
HD Audio Codec_ALC260D
AMP./Audio Jack
ENE-KB910L/TPM
BIOS/EE-Prom/TP/KB/SW
DC TO DC
PWR DCIN / Precharge
PWR CPU OTP
PWR-Battery Select
PWR-Charger
PWR-3V/5V
PWR-1.8V/1.5V
PWR-VCCPP/2.5V/0.9V
Security Classification
Issued Date
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
4
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2005/09/10 2006/06/23
Compal Secret Data
Deciphered Date
Title
Size Document Number Rev
2
Date: Sheet
Compal Electronics, Inc.
SCHEMATIC, M/B LA-3051P
星期四 十月
401397
245, 06, 2005
1
A
of
A
B
C
D
E
BLOCK DIAGRAM
4 4
Pentium-M
CPU Yonah
6,7,8
LM75CIMMX-5
10
Thermal Sensor
ADM1032ARM
Clock Generator
617
ICS954325
G SENSORThermal Sensor
23
FSB
533/667MHz
TV-OUT
CRT Conn.
3 3
LVDS Conn.
18
18
18
Intel Calistoga
GMCH
PCBGA 1466
9,10,11,12,13,14
2.5GHz(1.2V)
Bandwidth 500MB
400/533/667MHz
(1.8V)
Memory Bus
SO-DIMM x 2(DDRII)
BANK 0,1,2,3
15,16
FANController
Power Buttom/SW/LED
6
33
DMI
BATTERY
CHARGER
IDSEL: AD20 IRQE/F/G/H REQ#/GNT#2 IDSEL: AD18 IRQF/G REQ#/GNT#3
PCI BUS
33MHz (3.3V)
Intel ICH7-M
PCIE BUS
2 2
Ricoh
R5C842
Broadcom
BCM5751M
25
Mini Card
FOR WLAN
2728
mBGA-652
19,20,21,22
LPC 33MHz
480MHz
SATA
IDE
AC-LINK
24.576MHz
USB 2.0 Port *4
SATA HDD
ODD Module
24
23
23
DC/DC Interface
3VALWP/5VALWP
VCCP/0.9VSP
1.2VSP/1.8VALWP
37
38
35
39
41
40
RJ-45
1394-Port
CB PWR SW
CardBus*2
29 29
29
R5534V
26
Mini PCI
FOR WLAN
1 1
A
43
B
Embedded
Controller
ENE KB910L
BIOS(1MB)
MDC
31
Int. KB &
Touch-PAD
32 32
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITT EN CON SENT O F COMPAL ELECTRONICS, INC.
2005/09/10 2006/06/23
C
Connector
30
RJ-11
Compal Secret Data
Deciphered Date
Audio Amp.
TPA6017
SPK 1W*2
D
Realtek
ALC262
31 31
31
30
HP*1
MIC*1
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
SCHEMATIC, M/B LA-3051P
星期
, 06, 2005
四十月
CPU_CORE
401397
E
42
A
of
345
A
B
C
D
E
Voltage Rails
Dip SW function
KBSEL0/1# 11:JP K/B 01:US K/B 10:UK K/B 00: Reserve
Power Plane Description
VIN
1 1
2 2
B+
+CPU_CORE
+VCCP
+1.8VS ON OFF OFF1.8VS switched power rail
+0.9VS
+3.3V 3.3V switched power rail
+3VALW
+3VS
+5VALW ON
+5VS
+RTCVCC
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.
Adapter power supply (19V)
AC or battery power rail for power circuit.
Core voltage for CPU
1.05V switched power rail for CPU AGTL Bus
0.9V power rail
3.3V always on powe r rail
3.3V switched power rail
5V always on power r ail ON+5V ON OFF
5V always on power r ail
5V switched power rail
RTC power
External PCI Devices
CardBus(R5C842)
Mini-PCI(WLAN) AD18 3 PIRQG/PIRQH
IDSEL#Device
AD20 2 PIRQE/PIRQF/PIRQG/PIRQH
REQ#/GNT# Interrupts
S1 S3 S5
ON
ON ONONON
ON OFF
ON OFF
ON ON OFF1.8V power rail+1.8V
OFFON
ON
ON
ON
ON ON *
OFF
ON
OFF
ON
ON
ON
ON
OFF
OFF
OFF
OFF
OFFON
ON*
OFF
ON
PASSWORD# 0:Override 1:Avaliable
FINGERPRINT# 0:Existence 1:Non-Existence
Function Table
Function
TV-OUT
Bluetooth
PWR LED
(Odekake)
S/W I/II Key
4 in 1 Card
Adapter
Finger Print
TPM
W-LAN
Japan
Commercial Consumer
NEC
Direct(Internet
LaVie
Retailing)
Yes
YesNo
No
No Yes
Yes (BTO)
Yes
JP JP JP
No No
No
Yes (BTO)
Chip Reversion
945GM
ICH7
CLK Gen
KB910L
ALC262
Phase
ES Phase
A2
B0
A
A1
A2
PP Phase MP1 Phae IRT
Chip
HK/CHINA
Oversea
Comment
Need BTO
Not need
Odekake
all same
Need BTO
Need BTO
BCM5751 C1
3 3
EC SM Bus1 address
AddressDevice AddressDevice
Main Battery
EEPROM(24C16/02) Second Battery
ADM1032
0001 011X b
1010 000X b
1001 110X b
EC SM Bus2 address
KXP84-0200
LM75CIMMX-5
0011 000X b
ICH7 SM Bus address
Device
Clock Generator
4 4
(ICS954325AKLFT)
DDR DIMM0
DDR DIMM1
A
Address
1101 001Xb
1010 000Xb
1010 001Xb
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITT EN CON SENT O F COMPAL ELECTRONICS, INC.
2005/09/10 2006/06/23
C
Compal Secret Data
Deciphered Date
Title
Size Document Number Rev
D
Date: Sheet
Compal Electronics, Inc.
SCHEMATIC, M/B LA-3051P
星期
四十月
401397
, 06, 2005
E
445
A
of
5
4
3
2
1
LC2a Power block
RTC Charger
D D
Battery OVP
Vin Detector
Page 35
Input
DC IN
C C
CHARGER
Switch
Turn Off
Page 37
Page 38
+CHGRTC
B+
Page 35
CPU OTP
Page 36
Turn Off
+3VALWP: OCP:6A OVP:107%~115%
+5VALWP: OCP:8A OVP:107%~115%
(MAX8734A)
Page 39
Always
CC:0.6A~3.3A
CV:12.6V
(MB3887)
Page 38
+3VALW
+2.5VSP
Thermal protection: 150 degree C
(G914E)
Page 41
SUSP#
Battery
B B
CPU CORE
+1.8VP: OCP:11.7A OVP:112%~117%
+1.5VSP: OCP:6A OVP:112%~117%
(MAX8743)
+1.8V
+0.9VSP
Protectio n :d e pend on +1.8 VP
(APL5331)
Page 40
Page 41
+1.8VP:SYSON
+1.5VSP:SUSP#
SUSP
VR_ON
OCP:54A
OVP:2V
(ISL6262)
Page 42
+VCCP:OCP:12A OVP:115%
A A
Security Cla ssification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONIC S, INC. AND CONTAI NS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
3
2005/09/10 2006/06/23
Protection:depend on +1.05VSP
(ISL6269)
Compal Secret Data
Deciphered Date
2
Page 41
SUSP#
Title
Size Docu m e n t N u m b e r Re v
Date: Sheet
Compal Electronics, Inc.
SCHEMATIC, M/B LA-3051P
星期四
401397
06, 2005
十月
545,
1
of
A
A
H_A#[3..31]9
H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
CLK_CPU_BCLK
CLK_CPU_BCLK#
H_RESET#
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
H_ADSTB#0
H_ADSTB#1
H_ADS#
H_BNR#
H_BPRI#
H_BR0#
H_DEFER#
H_DRDY#
H_HIT#
H_HITM#
H_IERR#
H_LOCK#
H_RESET#
H_RS#0
H_RS#1
H_RS#2
H_TRDY#
ITP_BPM#0
ITP_BPM#1
ITP_BPM#2
ITP_BPM#3
ITP_DBRESET#
H_DBSY#
H_DPSLP#
H_DPRSTP#
H_DPWR#
ITP_BPM#4
ITP_BPM#5
H_PROCHOT#
H_PWRGOOD
H_CPUSLP#
ITP_TCK
ITP_TDI
ITP_TDO
TEST1
TEST2
ITP_TMS
ITP_TRST#
H_THERMDA
H_THERMDC
H_THERMTRIP#
1 1
H_REQ#[0..4]9
H_ADSTB#09
2 2
R265
56_0402_5%
1 2
+VCCP
3 3
H_THERMDA, H_THERMDC routing together.
Trace width / Spacing = 10 / 10 mil
4 4
H_ADSTB#19
CLK_CPU_BCLK17
CLK_CPU_BCLK#17
H_ADS#9
H_BNR#9
H_BPRI#9
H_DEFER#9
H_DRDY#9
H_HITM#9
H_LOCK#9
H_RESET#9
H_RS#[0..2]9
H_TRDY#9
ITP_DBRESET#21
H_DBSY#9
H_DPSLP#20
H_DPRSTP#20,42
H_DPWR#9
H_PWRGOOD20
H_CPUSLP#9,20
R275 1K_0402_5%@
1 2
R276 51_0402_5%
1 2
H_THERMTRIP#9,20
+VCCP
R270
54.9_0402_1%
1 2
A
H_BR0#9
H_HIT#9
JP3A
J4
A3#
L4
A4#
M3
A5#
K5
A6#
M1
A7#
N2
A8#
J1
A9#
N3
A10#
P5
A11#
P2
A12#
L1
A13#
P4
A14#
P1
A15#
R1
A16#
Y2
A17#
U5
A18#
R3
A19#
W6
A20#
U4
A21#
Y5
A22#
U2
A23#
R4
A24#
T5
ADDR GROUP
A25#
T3
A26#
W3
A27#
W5
A28#
Y4
A29#
W2
A30#
Y1
A31#
K3
REQ0#
H2
REQ1#
K2
REQ2#
J3
REQ3#
L5
REQ4#
L2
ADSTB0#
V4
ADSTB1#
A22
BCLK0
AD4
AD3
AD1
AC4
C20
D24
AC2
AC1
D21
AC5
AA6
AB3
C26
D25
AB5
AB6
A21
H1
E2
G5
F1
H5
F21
G6
E4
D20
H4
B1
F3
F4
G3
G2
E1
B5
E5
D6
D7
A24
A25
C7
HOST CLK
BCLK1
ADS#
BNR#
BPRI#
BR0#
DEFER#
DRDY#
HIT#
CONTROL
HITM#
IERR#
LOCK#
RESET#
RS0#
RS1#
RS2#
TRDY#
BPM0#
BPM1#
BPM2#
BPM3#
DBR#
DBSY#
DPSLP#
DPRSTP#
DPWR#
PRDY#
PREQ#
PROCHOT#
PWRGOOD
SLP#
TCK
TDI
TDO
TEST1
TEST2
TMS
TRST#
THERMAL
THERMDA
DIODE
THERMDC
THERMTRIP#
FOX_PZ47823-2743-41_YONAH
H_DPSLP#
H_DPRSTP#
YONAH
MISC
1 2
1 2
B
DATA GROUP
LEGACY CPU
+VCCP
R271
56_0402_5%@
R266
56_0402_5%@
B
D10#
D11#
D12#
D13#
D14#
D15#
D16#
D17#
D18#
D19#
D20#
D21#
D22#
D23#
D24#
D25#
D26#
D27#
D28#
D29#
D30#
D31#
D32#
D33#
D34#
D35#
D36#
D37#
D38#
D39#
D40#
D41#
D42#
D43#
D44#
D45#
D46#
D47#
D48#
D49#
D50#
D51#
D52#
D53#
D54#
D55#
D56#
D57#
D58#
D59#
D60#
D61#
D62#
D63#
DINV0#
DINV1#
DINV2#
DINV3#
DSTBN0#
DSTBN1#
DSTBN2#
DSTBN3#
DSTBP0#
DSTBP1#
DSTBP2#
DSTBP3#
A20M#
FERR#
IGNNE#
INIT#
LINT0
LINT1
STPCLK#
SMI#
C
ITP_DBRESET#
H_D#[0..63] 9
H_D#0
E22
D0#
H_D#1
F24
D1#
H_D#2
E26
D2#
H_D#3
H22
D3#
H_D#4
F23
D4#
H_D#5
G25
D5#
H_D#6
E25
D6#
H_D#7
E23
D7#
H_D#8
K24
D8#
H_D#9
G24
D9#
H_D#10
J24
H_D#11
J23
H_D#12
H26
H_D#13
F26
H_D#14
K22
H_D#15
H25
H_D#16
N22
H_D#17
K25
H_D#18
P26
H_D#19
R23
H_D#20
L25
H_D#21
L22
H_D#22
L23
H_D#23
M23
H_D#24
P25
H_D#25
P22
H_D#26
P23
H_D#27
T24
H_D#28
R24
H_D#29
L26
H_D#30
T25
H_D#31
N24
H_D#32
AA23
H_D#33
AB24
H_D#34
V24
H_D#35
V26
H_D#36
W25
H_D#37
U23
H_D#38
U25
U22
AB25
W22
Y23
AA26
Y26
Y22
AC26
AA24
AC22
AC23
AB22
AA21
AB21
AC25
AD20
AE22
AF23
AD24
AE21
AD21
AE25
AF25
AF22
AF26
J26
M26
V23
AC20
H23
M24
W24
AD23
G22
N25
Y25
AE24
A6
A5
C4
B3
C6
B4
D5
A3
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
H_DINV#0
H_DINV#1
H_DINV#2
H_DINV#3
H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3
H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3
H_A20M#
H_FERR#
H_IGNNE#
H_INIT#
H_INTR
H_NMI
H_STPCLK#
H_SMI#
H_DINV#0 9
H_DINV#1 9
H_DINV#2 9
H_DINV#3 9
H_DSTBN#[0..3] 9
H_DSTBP # [0 ..3 ] 9
H_A20M# 20
H_FERR# 20
H_IGNNE# 20
H_INIT# 20
H_INTR 20
H_NMI 20
H_STPCLK# 20
H_SMI# 20
FAN CONN. 1
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITT EN CON SENT O F COMPAL ELECTRONICS, INC.
C
R273 200_0402_5%@
1 2
EN_FAN132
2005/09/10 2006/06/23
R344 100K_0402_5%
0.1U_0402_16V4Z
5
6
Compal Secret Data
1 2
C393
U14B
+IN
OUT
-IN
LM358DR2G_SO8~N
100K_0402_5%
1 2
C70
0.1U_0402_10V6K~N@
+VCCP
H_THERMTRIP#
Deciphered Date
ITP_BPM#0
ITP_BPM#1
ITP_BPM#2
ITP_BPM#3
ITP_BPM#4
2
1
7
+CPU_CORE
12
R45
1 2
R342
12
R47
56_0402_5%
PAD
PAD
PAD
PAD
PAD
PAD
+5VS
3
+IN
2
-IN
1 2
100K_0402_5%
R343
150K_0402_5%
C
2
B
E
1 2
OUT
D
T16
ITP_TDI
T11
ITP_TMS
T13
T12
ITP_TDO
T15
T14
ITP_BPM#5
ITP_TRST#
ITP_TCK
Thermal Sensor
C388
0.1U_0402_16V4Z
8
U14A
P
ENFAN1
1
G
4
LM358DR2G_SO8~N
1 2
C391 2200P_0402_50V7K~N
RB751V_SOD323
+3VS
FAN1_SPEED32
Q10
PMBT3904_SOT23
D
MAINPWON 35,36,39
1
3
This shall place near CPU
R259 56_0402_5%
1 2
R261 56_0402_1%
1 2
R262 56_0402_5%
1 2
R258 56_0402_5%
1 2
R260 56_0402_5%
1 2
R257 56_0402_5%
1 2
H_THERMDA
1
2200P_0402_50V7K~N
C78
EC_SMB_CK110,23,32,37
EC_SMB_DA110,23,32,37
+5VS +5VS_FAN
2
G
D13
1 2
R120 10K_0402_5%
2
H_THERMDC
F1
1.1A_6VDC_FUSE
12
R354
1K_0402_5%
3
13
D
Q21
S
2N7002_SOT23
1
@
2
2 1
22U_1206_10V4Z
Title
Size Document Number Rev
星期
Date: Sheet
+VCCP
21
SI3443DV_TSOP6
S
G
D
Q12
6
2451
1
C147
C144
2
1000P_0402_50V7K~N
1
C145
0.01U_0402_16V7K
2
+3V
12
R48
@
330_0603_5%
C
2
B
E
Q11
@
3 1
MMBT3904_SOT23
Compal Electronics, Inc.
SCHEMATIC, M/B LA-3051P
401397
, 06, 2005
四十月
E
+3VS
1
2
0.1U_0402_16V4Z
U6
2
3
8
7
VDD1
D+
ALERT#
D-
THERM#
SCLK
GND
SDATA
ADM1032ARMZ_MSOP8~N
Level shifter
H_PROCHOT_SIO#
1 2
R50 56_0402_5%@
1 2
R51 56_0402_5%
H_PROCHOT#
E
C76
12
R52
1
10K_0402_5%
6
@
4
5
JP5
1
2
3
MOLEX_53398-0371~N
+VCCP
+VCCP
H_PROCHOT#
of
645
A
A
B
C
D
E
+VCCP
12
V_CPU_GTLREF
1 1
R253
1K_0402_1%
12
R256
2K_0402_1%
Close to CPU pin AD26
within 0.5 inch
CPU_BSEL CPU_BSEL2 CPU_BSEL1
133
166
2 2
3 3
00
0
+CPU_CORE
Close to CPU pin
within 500mils.
CPU_BSEL0
1
R254
100_0402_1%
1 2
R255
100_0402_1%
1 2
1
1
12
R42
27.4_0402_1%
R39
54.9_0402_1%
VCCSENSE
VSSSENSE
12
R264
Length match within 25 mils
The trace width 18 mils space
7 mils
+1.5VS
1
C71
12
27.4_0402_1%
0.01U_0402_16V7K
Resistor placed within
12
0.5" of CPU pin.Trace
should be at least 25
mils away from any
R263
other toggling signal.
54.9_0402_1%
2
1
2
VCCSENSE42
VSSSENSE42
+VCCP
C69
10U_0805_10V4Z~N
H_PSI#42
CPU_VID042
CPU_VID142
CPU_VID242
CPU_VID342
CPU_VID442
CPU_VID542
CPU_VID642
V_CPU_GTLREF
CPU_BSEL017
CPU_BSEL117
CPU_BSEL217
+CPU_CORE
VCCSENSE
VSSSENSE
H_PSI#
CPU_VID0
CPU_VID1
CPU_VID2
CPU_VID3
CPU_VID4
CPU_VID5
CPU_VID6
CPU_BSEL0
CPU_BSEL1
CPU_BSEL2
COMP0
COMP1
COMP2
COMP3
JP3B
AF7
VCCSENSE
AE7
VSSSENSE
B26
VCCA
K6
VCCP
J6
VCCP
M6
VCCP
N6
VCCP
YONAH
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
PSI#
VID0
VID1
VID2
VID3
VID4
VID5
VID6
GTLREF
BSEL0
BSEL1
BSEL2
COMP0
COMP1
COMP2
COMP3
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
FOX_PZ47823-2743-41_YONAH
W21
AD6
AD26
AB20
AA20
AF20
AE20
AB18
AB17
AA18
AA17
AD18
AD17
AC18
AC17
AF18
AF17
T6
R6
K21
J21
M21
N21
T21
R21
V21
V6
G21
AE6
AF5
AE5
AF4
AE3
AF2
AE2
B22
B23
C21
R26
U26
U1
V1
E7
D2
F6
D3
C1
AF1
D22
C23
C24
AA1
AA4
AB2
AA3
M4
N5
T2
V3
B2
C3
T22
B25
AB26
VSS
AA25
VSS
AD25
VSS
AE26
VSS
AB23
VSS
AC24
VSS
AF24
VSS
AE23
VSS
AA22
VSS
AD22
VSS
AC21
VSS
AF21
VSS
AB19
VSS
AA19
VSS
AD19
VSS
AC19
VSS
AF19
VSS
AE19
VSS
AB16
VSS
AA16
VSS
AD16
VSS
AC16
VSS
AF16
VSS
AE16
VSS
AB13
VSS
AA14
VSS
AD13
VSS
AC14
VSS
AF13
VSS
AE14
VSS
AB11
VSS
AA11
VSS
AD11
VSS
AC11
VSS
AF11
VSS
AE11
VSS
AB8
VSS
AA8
VSS
AD8
VSS
AC8
VSS
AF8
VSS
AE8
VSS
AA5
VSS
AD5
VSS
AC6
VSS
AF6
VSS
AB4
VSS
AC3
VSS
POWER, GROUNG, RESERVED SIGNALS AND NC
AF3
VSS
AE4
VSS
AB1
VSS
AA2
VSS
AD2
VSS
AE1
VSS
B6
VSS
C5
VSS
F5
VSS
E6
VSS
H6
VSS
J5
VSS
M5
VSS
L6
VSS
P6
VSS
R5
VSS
V5
VSS
U6
VSS
Y6
VSS
A4
VSS
D4
VSS
E3
VSS
H3
VSS
G4
VSS
K4
VSS
L3
VSS
P3
VSS
N4
VSS
T4
VSS
U3
VSS
Y3
VSS
W4
VSS
D1
VSS
C2
VSS
F2
VSS
G1
VSS
+CPU_CORE
JP3C
AE18
VCC
AE17
VCC
AB15
VCC
AA15
VCC
AD15
VCC
AC15
VCC
AF15
VCC
AE15
VCC
AB14
VCC
AA13
VCC
AD14
VCC
AC13
VCC
AF14
VCC
AE13
VCC
AB12
VCC
AA12
VCC
AD12
VCC
AC12
VCC
AF12
VCC
AE12
VCC
AB10
VCC
AB9
VCC
AA10
VCC
AA9
VCC
AD10
VCC
AD9
VCC
AC10
VCC
AC9
VCC
AF10
VCC
AF9
VCC
AE10
POWER, GROUND
VCC
AE9
VCC
AB7
VCC
AA7
VCC
AD7
VCC
AC7
VCC
B20
VCC
A20
VCC
F20
VCC
E20
VCC
B18
VCC
B17
VCC
A18
VCC
A17
VCC
D18
VCC
D17
VCC
C18
VCC
C17
VCC
F18
VCC
F17
VCC
E18
VCC
E17
VCC
B15
VCC
A15
VCC
D15
VCC
C15
VCC
F15
VCC
E15
VCC
B14
VCC
A13
VCC
D14
VCC
C13
VCC
F14
VCC
E13
VCC
B12
VCC
A12
VCC
D12
VCC
C12
VCC
F12
VCC
E12
VCC
B10
VCC
B9
VCC
A10
VCC
A9
VCC
D10
VCC
D9
VCC
C10
VCC
C9
VCC
F10
VCC
F9
VCC
E10
VCC
E9
VCC
B7
VCC
A7
VCC
F7
VCC
FOX_PZ47823-2743-41_YONAH
YONAH
K1
VSS
J2
VSS
M2
VSS
N1
VSS
T1
VSS
R2
VSS
V2
VSS
W1
VSS
A26
VSS
D26
VSS
C25
VSS
F25
VSS
B24
VSS
A23
VSS
D23
VSS
E24
VSS
B21
VSS
C22
VSS
F22
VSS
E21
VSS
B19
VSS
A19
VSS
D19
VSS
C19
VSS
F19
VSS
E19
VSS
B16
VSS
A16
VSS
D16
VSS
C16
VSS
F16
VSS
E16
VSS
B13
VSS
A14
VSS
D13
VSS
C14
VSS
F13
VSS
E14
VSS
B11
VSS
A11
VSS
D11
VSS
C11
VSS
F11
VSS
E11
VSS
B8
VSS
A8
VSS
D8
VSS
C8
VSS
F8
VSS
E8
VSS
G26
VSS
K26
VSS
J25
VSS
M25
VSS
N26
VSS
T26
VSS
R25
VSS
V25
VSS
W26
VSS
H24
VSS
G23
VSS
K23
VSS
L24
VSS
P24
VSS
N23
VSS
T23
VSS
U24
VSS
Y24
VSS
W23
VSS
H21
VSS
J22
VSS
M22
VSS
L21
VSS
P21
VSS
R22
VSS
V22
VSS
U21
VSS
Y21
VSS
4 4
Security Cla ssification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONIC S, INC. AND CONTAI NS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
2005/09/10 2006/06/23
C
Compal Secret Data
Deciphered Date
Title
Size Doc u m e n t N umber Rev
D
Date: Sheet
Compal Electronics, Inc.
SCHEMATIC, M/B LA-3051P
星期四
401397
, 06, 2005
十月
E
745
A
of
A
B
C
D
E
1 1
Place these capacitors on L8
(North side,Secondary Layer)
Place these capacitors on L8
(North side,Secondary Layer)
Place these capacitors on L8
(Sorth side,Secondary Layer)
2 2
Place these capacitors on L8
(Sorth side,Secondary Layer)
3 3
South Side Secondary
+CPU_CORE
1
2
+CPU_CORE
1
2
+CPU_CORE
1
2
+CPU_CORE
1
2
+CPU_CORE
C54
22U_0805_6.3V6M
C66
22U_0805_6.3V6M
C285
22U_0805_6.3V6M
C300
22U_0805_6.3V6M
1
+
C36
2
330U_D2E_2.5VM_R9
C38
1
+
2
330U_D2E_2.5VM_R9
1
C55
22U_0805_6.3V6M
2
1
C65
22U_0805_6.3V6M
2
1
C286
22U_0805_6.3V6M
2
1
C299
22U_0805_6.3V6M
2
C37
330U_D2E_2.5VM_R9
C311
330U_D2E_2.5VM_R9
1
C57
22U_0805_6.3V6M
2
1
C63
22U_0805_6.3V6M
2
1
C288
22U_0805_6.3V6M
2
1
C297
22U_0805_6.3V6M
2
1
+
2
C312
330U_D2E_2.5VM_R9
1
C56
22U_0805_6.3V6M
2
1
C64
22U_0805_6.3V6M
2
1
C287
22U_0805_6.3V6M
2
1
C298
22U_0805_6.3V6M
2
1
+
2
1
+
C310
2
330U_D2E_2.5VM_R9
1
2
1
2
1
2
1
2
1
+
North Side Secondary
2
C58
22U_0805_6.3V6M
C281
22U_0805_6.3V6M
C304
22U_0805_6.3V6M
C308
22U_0805_6.3V6M
1
C59
22U_0805_6.3V6M
2
1
C282
22U_0805_6.3V6M
2
1
C303
22U_0805_6.3V6M
2
1
C307
22U_0805_6.3V6M
2
1
2
1
2
1
2
1
2
ESR <= 1.5m ohm
Capacitor > 1980uF
C68
22U_0805_6.3V6M
C283
22U_0805_6.3V6M
C302
22U_0805_6.3V6M
C278
22U_0805_6.3V6M
1
C67
22U_0805_6.3V6M
2
1
C284
22U_0805_6.3V6M
2
1
C301
22U_0805_6.3V6M
2
1
C277
22U_0805_6.3V6M
2
Mid Frequence Decoupling
7mOhm
330U_D2E_2.5VM_R9
@
C60
+VCCP
7mOhm
PS CAP
1
+
2
1
C289
0.1U_0402_16V4Z
2
1
C291
0.1U_0402_16V4Z
2
PS CAP
7mOhm
PS CAP
1
2
7mOhm
PS CAP
C294
0.1U_0402_16V4Z
7mOhm
PS CAP
1
C290
0.1U_0402_16V4Z
2
7mOhm
PS CAP
1
2
C292
0.1U_0402_16V4Z
1
C293
0.1U_0402_16V4Z
2
Place these inside
socket cavity on L8
(North side
Secondary)
330U ?
4 4
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITT EN CON SENT O F COMPAL ELECTRONICS, INC.
2005/09/10 2006/06/23
C
Compal Secret Data
Deciphered Date
Title
Size Document Number Rev
Custom
D
Date: Sheet
Compal Electronics, Inc.
SCHEMATIC, M/B LA-3051P
401397
星期
, 06, 2005
四十月
E
845
A
of
A
H_D#[0..63]6
1 1
2 2
+VCCP
12
12
R56
54.9_0402_1%
+VCCP
R68
R65
12
R59
24.9_0402_1%
12
100_0402_1%
12
200_0402_1%
R55
54.9_0402_1%
3 3
4 4
H_D#0
H_D#1
H_D#2
H_D#3
H_D#4 CFG3
H_D#5 CFG4
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
H_VREF
H_XRCOMP
H_XSCOMP
H_YRCOMP
H_YSCOMP
H_SWNG0
H_SWNG1
12
R57
24.9_0402_1%
Layout Note:
H_XRCOMP / H_YRCOMP / H_VREF / H_SWNG0 /
H_SWNG1 trace width and spacing is 10/20.
H_VREF
1
C88
2
0.1U_0402_16V4Z
A
K11
T10
W11
U11
T11
W9
W7
W6
AB7
AA9
W4
W3
W5
Y10
AB8
W2
AA4
AA7
AA2
AA6
AA10
AA1
AB4
AC9
AB11
AC11
AB3
AC2
AD1
AD9
AC1
AD7
AC6
AB5
AD10
AD4
AC8
J13
K13
W1
U7A
F1
HD0#
J1
HD1#
H1
HD2#
J6
HD3#
H3
HD4#
K2
HD5#
G1
HD6#
G2
HD7#
K9
HD8#
K1
HD9#
K7
HD10#
J8
HD11#
H4
HD12#
J3
HD13#
HD14#
G4
HD15#
HD16#
HD17#
T3
HD18#
U7
HD19#
U9
HD20#
HD21#
HD22#
HD23#
T1
HD24#
T8
HD25#
T4
HD26#
HD27#
U5
HD28#
T9
HD29#
HD30#
T5
HD31#
HD32#
HD33#
HD34#
HD35#
Y3
HD36#
Y7
HD37#
HD38#
HD39#
HD40#
HD41#
HD42#
HD43#
HD44#
HD45#
HD46#
Y8
HD47#
HD48#
HD49#
HD50#
HD51#
HD52#
HD53#
HD54#
HD55#
HD56#
HD57#
HD58#
HD59#
HD60#
HD61#
HD62#
HD63#
HVREF0
HVREF1
E1
HXRCOMP
E2
HXSCOMP
Y1
HYRCOMP
U1
HYSCOMP
E4
HXSWING
HYSWING
CALISTOGA_FCBGA1466~D
<BOM Structure>
HADSTB#0
HADSTB#1
HOST
HDSTBN#0
HDSTBN#1
HDSTBN#2
HDSTBN#3
HDSTBP#0
HDSTBP#1
HDSTBP#2
HDSTBP#3
HCPURST#
HDPWR#
HDEFER#
HBREQ0#
HCPUSLP#
HA3#
HA4#
HA5#
HA6#
HA7#
HA8#
HA9#
HA10#
HA11#
HA12#
HA13#
HA14#
HA15#
HA16#
HA17#
HA18#
HA19#
HA20#
HA21#
HA22#
HA23#
HA24#
HA25#
HA26#
HA27#
HA28#
HA29#
HA30#
HA31#
HREQ#0
HREQ#1
HREQ#2
HREQ#3
HREQ#4
HCLKN
HCLKP
HDINV#0
HDINV#1
HDINV#2
HDINV#3
HADS#
HTRDY#
HDRDY#
HHITM#
HHIT#
HLOCK#
HBNR#
HBPRI#
HDBSY#
HRS0#
HRS1#
HRS2#
12
R61
12
R60
B
+VCCP+VCCP
R54
R58
H_A#[3..31] 6
H_REQ#[0..4] 6
H_ADSTB#0 6
H_ADSTB#1 6
CLK_MCH_BCLK# 17
CLK_MCH_BCLK 17
H_DSTBN#[0..3] 6
H_DSTBP # [0 ..3 ] 6
H_DINV#0 6
H_DINV#1 6
H_DINV#2 6
H_DINV#3 6
H_RESET# 6
H_ADS# 6
H_TRDY# 6
H_DPWR# 6
H_DRDY# 6
H_DEFER# 6
H_HITM# 6
H_HIT# 6
H_LOCK# 6
H_BR0# 6
H_BNR# 6
H_BPRI# 6
H_DBSY# 6
H_CPUSLP# 6,20
H_RS#[0..2] 6
12
221_0603_1%
12
100_0402_1%
H_SWNG1
1
2
0.1U_0402_16V4Z
C82
Security Classification
H_A#3
H9
H_A#4
C9
H_A#5
E11
H_A#6
G11
H_A#7
F11
H_A#8
G12
H_A#9
F9
H_A#10
H11
H_A#11
J12
H_A#12
G14
H_A#13
D9
H_A#14
J14
H_A#15
H13
H_A#16
J15
H_A#17
F14
H_A#18
D12
H_A#19
A11
H_A#20
C11
H_A#21
A12
H_A#22
A13
H_A#23
E13
H_A#24
G13
H_A#25
F12
H_A#26
B12
H_A#27
B14
H_A#28
C12
H_A#29
A14
H_A#30
C14
H_A#31
D14
H_REQ#0
D8
H_REQ#1
G8
H_REQ#2
B8
H_REQ#3
F8
H_REQ#4 DDR_CKE1_DIMMA
A8
H_ADSTB#0
B9
H_ADSTB#1
C13
CLK_MCH_BCLK#
AG1
CLK_MCH_BCLK
AG2
H_DSTBN#0
K4
H_DSTBN#1
T7
H_DSTBN#2
Y5
H_DSTBN#3
AC4
H_DSTBP#0
K3
H_DSTBP#1
T6
H_DSTBP#2
AA5
H_DSTBP#3
AC5
H_DINV#0
J7
H_DINV#1
W8
H_DINV#2
U3
H_DINV#3
AB10
H_RESET#
B7
H_ADS#
E8
H_TRDY#
E7
H_DPWR#
J9
H_DRDY#
H8
H_DEFER#
C3
H_HITM#
D4
H_HIT#
D3
H_LOCK#
B3
H_BR0#
C7
H_BNR#
C6
H_BPRI#
F6
H_DBSY#
A7
H_CPUSLP#
E3
H_RS#0
B4
H_RS#1
E6
H_RS#2
D6
221_0603_1%
H_SWNG0
1
C83
2
100_0402_1%
0.1U_0402_16V4Z
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITT EN CON SENT O F COMPAL ELECTRONICS, INC.
C
DDR_CKE0_DIMMA15
DDR_CKE1_DIMMA15
DDR_CKE2_DIMMB16
DDR_CKE3_DIMMB16
DDR_CS0_DIMMA#15
DDR_CS1_DIMMA#15
DDR_CS2_DIMMB#16
DDR_CS3_DIMMB#16
+1.8V
R279 80.6_0402_1%
1 2
1 2
R280 80.6_0402_1%
PLT_RST#19,21,25,27,32
V_DDR_MCH_REF15,16
Stuff R286 & R281 for A1 Calistoga
C
DMI_TXN021
DMI_TXN121
DMI_TXN221
DMI_TXN321
DMI_TXP021
DMI_TXP121
DMI_TXP221
DMI_TXP321
DMI_RXN021
DMI_RXN121
DMI_RXN221
DMI_RXN321
DMI_RXP021
DMI_RXP121
DMI_RXP221
DMI_RXP321
M_CLK_DDR015
M_CLK_DDR115
M_CLK_DDR216
M_CLK_DDR316
M_CLK_DDR#015
M_CLK_DDR#115
M_CLK_DDR#216
M_CLK_DDR#316
M_ODT015
M_ODT115
M_ODT216
M_ODT316
V_DDR_MCH_REF
PM_BMBUSY#21
PM_EXTTS#015
PM_EXTTS#116
H_THERMTRIP#6,20
NB_PWRGD19
R305 100_0402_1%
MCH_ICH_SYNC#19
Layout Note:
V_DDR_MCH_REF
trace width and
spacing is 20/20.
V_DDR_MCH_REF
1
C315
2
0.1U_0402_16V4Z
2005/09/10 2006/06/23
DMI_TXN0
DMI_TXN1
DMI_TXN2
DMI_TXN3
DMI_TXP0
DMI_TXP1
DMI_TXP2
DMI_TXP3
DMI_RXN0
DMI_RXN1
DMI_RXN2
DMI_RXN3
DMI_RXP0
DMI_RXP1
DMI_RXP2
DMI_RXP3
M_CLK_DDR1
M_CLK_DDR2
M_CLK_DDR3
M_CLK_DDR#0
M_CLK_DDR#1
M_CLK_DDR#2
M_CLK_DDR#3
DDR_CKE0_DIMMA
DDR_CKE2_DIMMB
DDR_CKE3_DIMMB
DDR_CS0_DIMMA#
DDR_CS1_DIMMA#
DDR_CS2_DIMMB#
DDR_CS3_DIMMB#
M_OCDOCMP0
M_OCDOCMP1
M_ODT0
M_ODT1
M_ODT2
M_ODT3
SMRCOMPN
SMRCOMPP
PM_BMBUSY#
PM_EXTTS#0
PM_EXTTS#1
H_THERMTRIP#
NB_PWRGD
PLTRST_R#
12
+1.8V
12
R277
100_0402_1%
12
R278
100_0402_1%
Compal Secret Data
Deciphered Date
U7B
AE35
DMIRXN0
AF39
DMIRXN1
AG35
DMIRXN2
AH39
DMIRXN3
AC35
DMIRXP0
AE39
DMIRXP1
AF35
DMIRXP2
AG39
DMIRXP3
AE37
DMITXN0
AF41
DMITXN1
AG37
DMITXN2
AH41
DMITXN3
AC37
DMITXP0
AE41
DMITXP1
AF37
DMITXP2
AG41
DMITXP3
AY35
SM_CK0
AR1
SM_CK1
AW7
SM_CK2
AW40
SM_CK3
AW35
SM_CK0#
AT1
SM_CK1#
AY7
SM_CK2#
AY40
SM_CK3#
AU20
SM_CKE0
AT20
SM_CKE1
BA29
SM_CKE2
AY29
SM_CKE3
AW13
SM_CS0#
AW12
SM_CS1#
AY21
SM_CS2#
AW21
SM_CS3#
AL20
SM_OCDCOMP0
AF10
SM_OCDCOMP1
BA13
SM_ODT0
BA12
SM_ODT1
AY20
SM_ODT2
AU21
SM_ODT3
AV9
SM_RCOMPN
AT9
SM_RCOMPP
AK1
SM_VREF0
AK41
SM_VREF1
G28
PM_BMBUSY#
F25
PM_EXTTS0#
H26
PM_EXTTS1#
G6
PM_THERMTRIP#
AH33
PWROK
AH34
RSTIN#
K28
ICH_SYNC#
CALISTOGA_FCBGA1466~D
<BOM Structure>
D
DMI
DDR MUXING
PM
Layout Note:
Route as short
as possible
12
R281
R286
40.2_0402_1%
40.2_0402_1%
@
@
D
E
Description at page13.
MCH_CLKSEL0
K16
CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG16
CFG
CFG17
CFG18
CFG19
CFG20
G_CLKP
G_CLKN
D_REF_CLKN
D_REF_CLKP
CLKNC
D_REF_SSCLKN
D_REF_SSCLKP
CLK_REQ#
NC0
NC1
NC2
NC3
NC4
NC5
NC6
NC7
NC8
NC9
NC10
NC11
NC12
NC13
NC14
NC15
NC16
NC17
NC18
RESERVED1
RESERVED2
RESERVED3
RESERVED4
RESERVED5
RESERVED6
RESERVED7
RESERVED8
RESERVED9
RESERVED10
RESERVED11
RESERVED12
RESERVED13
RESERVED
M_OCDOCMP0
M_OCDOCMP1
12
0_0402_5%
1 2
Title
Size Document Number Rev
Custom
Date: Sheet
MCH_CLKSEL1
K18
MCH_CLKSEL2
J18
F18
E15
CFG5
F15
CFG6
E18
CFG7
D19
CFG8
D16
CFG9
G16
CFG10
E16
CFG11
D15
CFG12
G15
CFG13
K15
CFG14
C15
CFG15
H16
CFG16
G18
CFG17
H15
CFG18
J25
CFG19
K27
CFG20
J26
CLK_MCH_3GPLL
AG33
CLK_MCH_3GPLL#M_CLK_DDR0
AF33
CLK_MCH_DREFCLK#
A27
CLK_MCH_DREFCLK
A26
MCH_SSCDREFCLK#
C40
MCH_SSCDREFCLK
D41
CLKREQA#
H32
A3
A39
A4
A40
AW1
AW41
AY1
BA1
BA2
BA3
BA39
BA40
BA41
C1
AY41
B2
B41
C41
D1
T32
R32
F3
F7
AG11
AF11
H7
J19
A41
A34
D28
D27
A35
PM_EXTTS#0
PM_EXTTS#1
R526
DPRSLPVR 21,42
Compal Electronics, Inc.
SCHEMATIC, M/B LA-3051P
, 06, 2005
四十月
401397
星期
PAD
PAD
PAD
PAD
PAD
PAD
R95
10K_0402_5%
R94
10K_0402_5%
MCH_CLKSEL0 17
MCH_CLKSEL1 17
MCH_CLKSEL2 17
CFG3 13
T17
CFG5 13
T24
CFG7 13
T22
CFG9 13
T19
CFG11 13
CFG12 13
CFG13 13
T18
T21
CFG16 13
CFG17 13
CFG18 13
CFG19 13
CFG20 13
12
12
E
CLK_MCH_3GPLL 17
CLK_MCH_3GPLL# 17
CLK_MCH_DREFCLK# 17
CLK_MCH_DREFCLK 17
MCH_SSCDREFCLK# 17
MCH_SSCDREFCLK 17
CLKREQA# 17
+3VS
of
945
A
A
1 1
B
C
D
E
DDR_A_BS#015
DDR_A_BS#115
DDR_A_BS#215
DDR_A_DM[0..7]15
DDR_A_DQS[0..7]15
2 2
DDR_A_DQS#[0..7]15
DDR_A_MA[0..13]15
3 3
DDR_A_CAS#15
DDR_A_RAS#15
DDR_A_WE#15
T25 PAD
T26 PAD
DDR_A_BS#0
DDR_A_BS#1
DDR_A_BS#2
DDR_A_DM0
DDR_A_DM1
DDR_A_DM2
DDR_A_DM3
DDR_A_DM4
DDR_A_DM5
DDR_A_DM6
DDR_A_DM7
DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7
DDR_A_DQS#0
DDR_A_DQS#1
DDR_A_DQS#2
DDR_A_DQS#3
DDR_A_DQS#4
DDR_A_DQS#5
DDR_A_DQS#6
DDR_A_DQS#7
DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_CAS#
DDR_A_RAS#
DDR_A_WE#
SA_RCVENIN# SB_RCVENIN#
SA_RCVENOUT#
check layout check layout
U7D
AU12
SA_BS0
AV14
SA_BS1
BA20
SA_BS2
AJ33
SA_DM0
AM35
SA_DM1
AL26
SA_DM2
AN22
SA_DM3
AM14
SA_DM4
AL9
SA_DM5
AR3
SA_DM6
AH4
SA_DM7
AK33
SA_DQS0
AT33
SA_DQS1
AN28
SA_DQS2
AM22
SA_DQS3
AN12
SA_DQS4
AN8
SA_DQS5
AP3
SA_DQS6
AG5
SA_DQS7
AK32
SA_DQS0#
AU33
SA_DQS1#
AN27
SA_DQS2#
AM21
SA_DQS3#
AM12
SA_DQS4#
AL8
SA_DQS5#
AN3
SA_DQS6#
AH5
SA_DQS7#
AY16
SA_MA0
AU14
SA_MA1
AW16
SA_MA2
BA16
SA_MA3
BA17
SA_MA4
AU16
SA_MA5
AV17
SA_MA6
AU17
SA_MA7
AW17
SA_MA8
AT16
SA_MA9
AU13
SA_MA10
AT17
SA_MA11
AV20
SA_MA12
AV12
SA_MA13
AY13
SA_CAS#
AW14
SA_RAS#
AY14
SA_WE#
AK23
SA_RCVENIN#
AK24
SA_RCVENOUT#
CALISTOGA_FCBGA1466~D
<BOM Stru cture>
SA_DQ0
SA_DQ1
SA_DQ2
SA_DQ3
SA_DQ4
SA_DQ5
SA_DQ6
SA_DQ7
SA_DQ8
SA_DQ9
SA_DQ10
SA_DQ11
SA_DQ12
SA_DQ13
SA_DQ14
SA_DQ15
SA_DQ16
SA_DQ17
SA_DQ18
SA_DQ19
SA_DQ20
SA_DQ21
SA_DQ22
SA_DQ23
SA_DQ24
SA_DQ25
SA_DQ26
SA_DQ27
SA_DQ28
SA_DQ29
SA_DQ30
SA_DQ31
SA_DQ32
SA_DQ33
SA_DQ34
SA_DQ35
SA_DQ36
SA_DQ37
SA_DQ38
SA_DQ39
DDR SYS MEMORY A
SA_DQ40
SA_DQ41
SA_DQ42
SA_DQ43
SA_DQ44
SA_DQ45
SA_DQ46
SA_DQ47
SA_DQ48
SA_DQ49
SA_DQ50
SA_DQ51
SA_DQ52
SA_DQ53
SA_DQ54
SA_DQ55
SA_DQ56
SA_DQ57
SA_DQ58
SA_DQ59
SA_DQ60
SA_DQ61
SA_DQ62
SA_DQ63
AJ34
AM31
AM33
AJ36
AK35
AJ32
AH31
AN35
AP33
AR31
AP31
AN38
AM36
AM34
AN33
AK26
AL27
AM26
AN24
AK28
AL28
AM24
AP26
AP23
AL22
AP21
AN20
AL23
AP24
AP20
AT21
AR12
AR14
AP13
AP12
AT13
AT12
AL14
AL12
AK9
AN7
AK8
AK7
AP9
AN9
AT5
AL5
AY2
AW2
AP1
AN2
AV2
AT3
AN1
AL2
AG7
AF9
AG4
AF6
AG9
AH6
AF4
AF8
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63
DDR_A_D0
AJ35
DDR_A_D[0..63] 15 DDR_B_D[0..63] 16
DDR_B_BS#016
DDR_B_BS#116
DDR_B_BS#216
DDR_B_DM[0..7]16
DDR_B_DQS[0..7]16
DDR_B_DQS#[0..7]16
DDR_B_MA[0..13]16
DDR_B_CAS#16
DDR_B_RAS#16
DDR_B_WE#16
T20 PAD
T23 PAD
DDR_B_BS#0
DDR_B_BS#1
DDR_B_BS#2
DDR_B_DM0
DDR_B_DM1
DDR_B_DM2
DDR_B_DM3
DDR_B_DM4
DDR_B_DM5
DDR_B_DM6
DDR_B_DM7
DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4
DDR_B_DQS5
DDR_B_DQS6
DDR_B_DQS7
DDR_B_DQS#0
DDR_B_DQS#1
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS#4
DDR_B_DQS#5
DDR_B_DQS#6
DDR_B_DQS#7
DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13
DDR_B_CAS#
DDR_B_RAS#
DDR_B_WE#
SB_RCVENOUT#
U7E
AT24
SB_BS0
AV23
SB_BS1
AY28
SB_BS2
AK36
SB_DM0
AR38
SB_DM1
AT36
SB_DM2
BA31
SB_DM3
AL17
SB_DM4
AH8
SB_DM5
BA5
SB_DM6
AN4
SB_DM7
AM39
SB_DQS0
AT39
SB_DQS1
AU35
SB_DQS2
AR29
SB_DQS3
AR16
SB_DQS4
AR10
SB_DQS5
AR7
SB_DQS6
AN5
SB_DQS7
AM40
SB_DQS0#
AU39
SB_DQS1#
AT35
SB_DQS2#
AP29
SB_DQS3#
AP16
SB_DQS4#
AT10
SB_DQS5#
AT7
SB_DQS6#
AP5
SB_DQS7#
AY23
SB_MA0
AW24
SB_MA1
AY24
SB_MA2
AR28
SB_MA3
AT27
SB_MA4
AT28
SB_MA5
AU27
SB_MA6
AV28
SB_MA7
AV27
SB_MA8
AW27
SB_MA9
AV24
SB_MA10
BA27
SB_MA11
AY27
SB_MA12
AR23
SB_MA13
AR24
SB_CAS#
AU23
SB_RAS#
AR27
SB_WE#
AK16
SB_RCVENIN#
AK18
SB_RCVENOUT#
CALISTOGA_FCBGA1466~D
<BOM Stru cture>
SB_DQ0
SB_DQ1
SB_DQ2
SB_DQ3
SB_DQ4
SB_DQ5
SB_DQ6
SB_DQ7
SB_DQ8
SB_DQ9
SB_DQ10
SB_DQ11
SB_DQ12
SB_DQ13
SB_DQ14
SB_DQ15
SB_DQ16
SB_DQ17
SB_DQ18
SB_DQ19
SB_DQ20
SB_DQ21
SB_DQ22
SB_DQ23
SB_DQ24
SB_DQ25
SB_DQ26
SB_DQ27
SB_DQ28
SB_DQ29
SB_DQ30
SB_DQ31
SB_DQ32
SB_DQ33
SB_DQ34
SB_DQ35
SB_DQ36
SB_DQ37
SB_DQ38
SB_DQ39
DDR SYS MEMORY B
SB_DQ40
SB_DQ41
SB_DQ42
SB_DQ43
SB_DQ44
SB_DQ45
SB_DQ46
SB_DQ47
SB_DQ48
SB_DQ49
SB_DQ50
SB_DQ51
SB_DQ52
SB_DQ53
SB_DQ54
SB_DQ55
SB_DQ56
SB_DQ57
SB_DQ58
SB_DQ59
SB_DQ60
SB_DQ61
SB_DQ62
SB_DQ63
AJ37
AP39
AR41
AJ38
AK38
AN41
AP41
AT40
AV41
AU38
AV38
AP38
AR40
AW38
AY38
BA38
AV36
AR36
AP36
BA36
AU36
AP35
AP34
AY33
BA33
AT31
AU29
AU31
AW31
AV29
AW29
AM19
AL19
AP14
AN14
AN17
AM16
AP15
AL15
AJ11
AH10
AJ9
AN10
AK13
AH11
AK10
AJ8
BA10
AW10
BA4
AW4
AY10
AY9
AW5
AY5
AV4
AR5
AK4
AK3
AT4
AK5
AJ5
AJ3
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63
DDR_B_D0
AK39
DDR Thermal Sensor
4 4
EC_SMB_DA26,23,32,37
EC_SMB_CK26,23,32,37
A
SMB_EC_DA2
SMB_EC_CK2
U11
1
SDA
2
SCL
3
OS#
4
GND
LM75CIMMX-5_MSOP8@
VCC
+5VS
1
C305
0.1U_0402_16V4Z@
2
8
7
A0
6
A1
5
A2
1 2
R269 1K_0402_5%@
B
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2005/09/10 2006/06/23
Compal Secret Data
Deciphered Date
D
Title
Size Document Number Re v
Custom
Date: Sheet
Compal Electronics, Inc.
SCHEMATIC, M/B LA-3051P
星期四 十
06, 2005
月
401397
E
10 45,
of
A
5
4
3
2
1
D D
U7C
H27
SDVOCTRL_DATA
H28
SDVOCTRL_CLK
R63
1 2
1 2
150_0402_1%
150_0402_1%
R301 1.5K_0402_1%
TV_COMPS
TV_LUMA
TV_CRMA
LVDSA0+
LVDSA1+
LVDSA2+
LVDSA0LVDSA1LVDSA2-
LVDSB0+
LVDSB1+
LVDSB2+
LVDSB0LVDSB1LVDSB2-
LVDSAC+
LVDSACLVDSBC+
LVDSBC-
GMCH_ENBKL
LCTLA_CLK
LCTLB_DATA
EDID_CLK_LCD
EDID_DAT_LCD
GMCH_LVDDEN
R287
4.99K_0402_1%
3VDDCCL
3VDDCDA
CRT_VSYNC
CRT_HSYNC
CRT_B
CRT_G
CRT_R
R288
255_0402_1%
LVDSA0+18
LVDSA1+18
LVDSA2+18
LVDSA0-18
LVDSA1-18
LVDSA2-18
LVDSB0+18
LVDSB1+18
LVDSB2+18
LVDSB0-18
LVDSB1-18
LVDSB2-18
LVDSAC+18
LVDSAC-18
LVDSBC+18
LVDSBC-18
BIA_PWM18
R66
1 2
R70
GMCH_ENBKL18
EDID_CLK_LCD18
EDID_DAT_LCD18
GMCH_LVDDEN18
150_0402_1%
1 2
150_0402_1%
R62
1 2
150_0402_1%
3VDDCCL18
3VDDCDA18
CRT_VSYNC18
CRT_HSYNC18
R73
R75
1 2
150_0402_1%
C C
B B
+3VS
@
1 2
R295 10K_0402_5%
@
1 2
R291 10K_0402_5%
GMCH_ENBKL
R32 100K_0402_1%
GMCH_LVDDEN
R33 100K_0402_5%
LCTLA_CLK
LCTLB_DATA
1 2
1 2
TV_COMPS18
TV_LUMA18
TV_CRMA18
CRT_B18
CRT_G18
CRT_R18
BIA_PWM
12
B37
B34
A36
C37
B35
A37
F30
D29
F28
G30
D30
F29
A32
A33
E26
E27
D32
J30
H30
H29
G26
G25
F32
B38
C35
C33
C32
A16
C18
A19
J20
12
B16
B18
B19
J29
K30
C26
C25
H23
G23
E23
D23
C22
B22
A21
B21
J22
12
LA_DATA0
LA_DATA1
LA_DATA2
LA_DATA#0
LA_DATA#1
LA_DATA#2
LB_DATA0
LB_DATA1
LB_DATA2
LB_DATA#0
LB_DATA#1
LB_DATA#2
LA_CLK
LA_CLK#
LB_CLK
LB_CLK#
LBKLT_CTL
LBKLT_EN
LCTLA_CLK
LCTLB_DATA
LDDC_CLK
LDDC_DATA
LVDD_EN
LIBG
LVBG
LVREFH
LVREFL
TVDAC_A
TVDAC_B
TVDAC_C
TV_IREF
TV_IRTNA
TV_IRTNB
TV_IRTNC
TV_DCONSEL1
TV_DCONSEL0
DDCCLK
DDCDATA
VSYNC
HSYNC
BLUE
BLUE#
GREEN
GREEN#
RED
RED#
CRT_IREF
CALISTOGA_FCBGA1466~D
<BOM Stru cture>
LVDS
TV CRT
EXP_COMPI
EXP_COMPO
EXP_RXN0
EXP_RXN1
EXP_RXN2
EXP_RXN3
EXP_RXN4
EXP_RXN5
EXP_RXN6
EXP_RXN7
EXP_RXN8
EXP_RXN9
EXP_RXN10
EXP_RXN11
EXP_RXN12
EXP_RXN13
EXP_RXN14
EXP_RXN15
EXP_RXP0
EXP_RXP1
EXP_RXP2
EXP_RXP3
EXP_RXP4
EXP_RXP5
EXP_RXP6
EXP_RXP7
EXP_RXP8
EXP_RXP9
EXP_RXP10
EXP_RXP11
EXP_RXP12
EXP_RXP13
EXP_RXP14
EXP_RXP15
EXP_TXN0
EXP_TXN1
EXP_TXN2
EXP_TXN3
EXP_TXN4
EXP_TXN5
EXP_TXN6
EXP_TXN7
EXP_TXN8
PCI-EXPRESS GRAPHICS
EXP_TXN9
EXP_TXN10
EXP_TXN11
EXP_TXN12
EXP_TXN13
EXP_TXN14
EXP_TXN15
EXP_TXP0
EXP_TXP1
EXP_TXP2
EXP_TXP3
EXP_TXP4
EXP_TXP5
EXP_TXP6
EXP_TXP7
EXP_TXP8
EXP_TXP9
EXP_TXP10
EXP_TXP11
EXP_TXP12
EXP_TXP13
EXP_TXP14
EXP_TXP15
D40
D38
F34
G38
H34
J38
L34
M38
N34
P38
R34
T38
V34
W38
Y34
AA38
AB34
AC38
D34
F38
G34
H38
J34
L38
M34
N38
P34
R38
T34
V38
W34
Y38
AA34
AB38
F36
G40
H36
J40
L36
M40
N36
P40
R36
T40
V36
W40
Y36
AA40
AB36
AC40
D36
F40
G36
H40
J36
L40
M36
N40
P36
R40
T36
V40
W36
Y40
AA36
AB40
PEGCOMP
R302
24.9_0402_1%
1 2
+1.5VS_PCIE
A A
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2005/09/10 2006/06/23
Compal Secret Data
Deciphered Date
Title
Size Document Number Re v
Custom
2
Date: Sheet
Compal Electronics, Inc.
SCHEMATIC, M/B LA-3051P
星期四 十
06, 2005
月
401397
1
11 45,
A
of
A
+VCCP
21
D9
CH751H-40_SC76@
1 1
CH751H-40_SC76@
2 2
3 3
4 4
12
+2.5VS
R90
10_0402_5%@
+1.5VS
21
D10
12
+3VS
R93
10_0402_5%@
C77
4.7U_0805_10V4Z
C74
0.22U_0603_10V7K
C75
1
C80
2
2.2U_0805_16V4Z
1
2
1
C318
2
1
+
220U_D2_4VM
2
1
2
MCH_A6
1
C84
2
MCH_D2
0.22U_0603_10V7K
C320
+1.5VS
+VCCP
0.47U_0603_10V7K
MCH_AB1
1
2
0.47U_0603_10V7K
U7H
AC14
VTT0
AB14
VTT1
W14
VTT2
V14
VTT3
T14
VTT4
R14
VTT5
P14
VTT6
N14
VTT7
M14
VTT8
L14
VTT9
AD13
VTT10
AC13
VTT11
AB13
VTT12
AA13
VTT13
Y13
VTT14
W13
VTT15
V13
VTT16
U13
VTT17
T13
VTT18
R13
VTT19
N13
VTT20
M13
VTT21
L13
VTT22
AB12
VTT23
AA12
VTT24
Y12
VTT25
W12
VTT26
V12
VTT27
U12
VTT28
T12
VTT29
R12
VTT30
P12
VTT31
N12
VTT32
M12
VTT33
L12
VTT34
R11
VTT35
P11
VTT36
N11
VTT37
M11
VTT38
R10
VTT39
P10
VTT40
N10
VTT41
M10
VTT42
P9
VTT43
N9
VTT44
M9
VTT45
R8
VTT46
P8
VTT47
N8
VTT48
M8
VTT49
P7
VTT50
N7
VTT51
M7
VTT52
R6
VTT53
P6
VTT54
M6
VTT55
A6
VTT56
R5
VTT57
P5
VTT58
N5
VTT59
M5
VTT60
P4
VTT61
N4
VTT62
M4
VTT63
R3
VTT64
P3
VTT65
N3
VTT66
M3
VTT67
R2
VTT68
P2
VTT69
M2
VTT70
D2
VTT71
AB1
VTT72
R1
VTT73
P1
VTT74
N1
VTT75
M1
VTT76
AG14
VCCAUX32
AF14
VCCAUX33
AE14
VCCAUX34
Y14
VCCAUX35
AF13
VCCAUX36
AE13
VCCAUX37
AF12
VCCAUX38
AE12
VCCAUX39
AD12
VCCAUX40
CALISTOGA_FCBGA1466~D
<BOM Structure>
P O W E R
B
VCC_SYNC
VCCTX_LVDS0
VCCTX_LVDS1
VCCTX_LVDS2
VCC3G0
VCC3G1
VCC3G2
VCC3G3
VCC3G4
VCC3G5
VCC3G6
VCCA_3GPLL
VCCA_3GBG
VSSA_3GBG
VCCA_CRTDAC0
VCCA_CRTDAC1
VSSA_CRTDAC2
VCCA_DPLLA
VCCA_DPLLB
VCCA_HPLL
VCCA_LVDS
VSSA_LVDS
VCCA_MPLL
VCCA_TVBG
VSSA_TVBG
VCCA_TVDACA0
VCCA_TVDACA1
VCCA_TVDACB0
VCCA_TVDACB1
VCCA_TVDACC0
VCCA_TVDACC1
VCCD_HMPLL0
VCCD_HMPLL1
VCCD_LVDS0
VCCD_LVDS1
VCCD_LVDS2
VCCD_TVDAC
VCCDQ_TVDAC
VCCHV0
VCCHV1
VCCHV2
VCCAUX0
VCCAUX1
VCCAUX2
VCCAUX3
VCCAUX4
VCCAUX5
VCCAUX6
VCCAUX7
VCCAUX8
VCCAUX9
VCCAUX10
VCCAUX11
VCCAUX12
VCCAUX13
VCCAUX14
VCCAUX15
VCCAUX16
VCCAUX17
VCCAUX18
VCCAUX19
VCCAUX20
VCCAUX21
VCCAUX22
VCCAUX23
VCCAUX24
VCCAUX25
VCCAUX26
VCCAUX27
VCCAUX28
VCCAUX29
VCCAUX30
VCCAUX31
H22
B30
C30
A30
AB41
AJ41
L41
N41
R41
V41
Y41
AC33
G41
H41
E21
F21
G21
B26
C39
AF1
A38
B39
AF2
H20
G20
E19
F19
C20
D20
E20
F20
AH1
AH2
A28
B28
C28
D21
H19
A23
B23
B25
AK31
AF31
AE31
AC31
AL30
AK30
AJ30
AH30
AG30
AF30
AE30
AD30
AC30
AG29
AF29
AE29
AD29
AC29
AG28
AF28
AE28
AH22
AJ21
AH21
AJ20
AH20
AH19
P19
P16
AH15
P15
AH14
+2.5VS
1 2
C356
0.1U_0402_16V4Z
+2.5VS
W=40 mils
+1.5VS_3GPLL
+2.5VS
+2.5VS_CRTDAC
+1.5VS_DPLLA
+1.5VS_DPLLB
+1.5VS_HPLL
+2.5VS
+1.5VS_MPLL
+3VS_TVBG
VSSA_TVBG
+3VS_TVDACA
+3VS_TVDACB
+3VS_TVDACC
+1.5VS
+1.5VS_TVDAC
+1.5VS_QTVDAC
1
2
C358
0.1U_0402_16V4Z
+1.5VS
1
C351
2
C378
C352
0.1U_0402_16V4Z
10U_0805_6.3V6M
1
+
2
1
2
+1.5VS_PCIE
1
C129
2
220U_D2_4VM
1
C347
2
0.022U_0402_16V7K~N
1
2
C345
0.022U_0402_16V7K~N
+3VS
C
R91
0_0805_5%
1
C128
2
10U_0805_6.3V6M
L12 BLM11A601S_0603
1 2
1
2
1
C96
2
1
C118
2
10U_0805_4VAM
10U_0805_6.3V6M
CRTDAC: Route caps within
C114
250mil of Alviso. Route FB
0.1U_0402_16V4Z
within 3" of Calistoga
R76
12
0_0805_5%
0.1U_0402_16V4Z
+1.5VS
1
C309
2
0.01U_0402_16V7K
12
+2.5VS
+3VS+3VS_TVBG
+2.5VS
1
C366
2
+1.5VS
4.7U_0603_6.3V6M
close pin B30/C30/A30
+2.5VS
1
C374
2
0.1U_0402_16V4Z
close pin G41
+2.5VS
1
1
C372
C371
2
2
0.1U_0402_16V4Z
0.01U_0402_16V7K
close pin A38
D
+1.5VS_DPLLA +1.5VS_DPLLB
470U_D2_2.5VM
0.1U_0402_16V4Z
1
C367
2
0.1U_0402_16V4Z
C363
1
2
1
C339
2
1
C102
2
L13
CHB1608U301_0603
1
C121
+
2
R285
0_0805_5%
1
C344
2
0.1U_0402_16V4Z
0.022U_0402_16V7K~N
R78
0_0805_5%
1
C101
2
0.1U_0402_16V4Z
0.022U_0402_16V7K~N
12
PCI-E/MEM/PSB PLL decoupling
R92
0_0603_5%
12
C127
1
2
10U_1206_6.3V6M
R274
0_0603_5%
22U_0805_6.3V6M
12
1
1
C368
2
2
0.1U_0402_16V4Z
+1.5VS_MPLL
45mA Max. 45mA Max.
1
C313
C319
2
0.1U_0402_16V4Z
E
L14
CHB1608U301_0603
470U_D2_2.5VM
0.1U_0402_16V4Z
1
C373
1
+
2
2
12
+3VS+3VS_TVDACC
12
+1.5VS+1.5VS_3GPLL
1
C131
2
0.1U_0402_16V4Z
1
1
C340
2
2
0.022U_0402_16V7K~N
+1.5VS_TVDAC +1.5VS
1
C109
2
0.022U_0402_16V7K~N
+1.5VS_QTVDAC +1.5VS
1
C338
2
0.1U_0402_16V4Z
1
2
+1.5VS_HPLL
1
C317
2
R79
0_0603_5%
C105
0.022U_0402_16V7K~N
0.1U_0402_16V4Z
C132
C93
C79
0_0805_5%
0.1U_0402_16V4Z
1
2
0.1U_0402_16V4Z
R53
0_0603_5%
1
2
22U_0805_6.3V6M
12
R71
0_0603_5%
R80
C348
12
C107
0.1U_0402_16V4Z
+1.5VS+1.5VS
+3VS+3VS_TVDACA+3VS+3VS_TVDACB
12
12
1
2
12
+1.5VS+1.5VS
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITT EN CON SENT O F COMPAL ELECTRONICS, INC.
2005/09/10 2006/06/23
C
Compal Secret Data
Deciphered Date
Title
Size Document Number Rev
Custom
D
Date: Sheet
Compal Electronics, Inc.
SCHEMATIC, M/B LA-3051P
401397
星期
, 06, 2005
四十月
12 45
E
A
of
5
4
3
2
1
Strap Pin Table
+VCCP
D D
1
1
C364
2
0.22U_0603_10V7K
1
C328
2
10U_1206_6.3V6M
C C
B B
C350
C369
C306
C314
1
C353
2
2
0.22U_0603_10V7K
10U_1206_6.3V6M
220U_D2_4VM
220U_D2_4VM@
0.22U_0603_10V7K
1
1
C336
2
2
1U_0603_10V4Z
1
+
2
1
+
2
+VCCP
U7F
AD27
VCC_NCTF0
AC27
VCC_NCTF1
AB27
VCC_NCTF2
AA27
VCC_NCTF3
Y27
VCC_NCTF4
W27
VCC_NCTF5
V27
VCC_NCTF6
U27
VCC_NCTF7
T27
VCC_NCTF8
R27
VCC_NCTF9
AD26
VCC_NCTF10
AC26
VCC_NCTF11
AB26
VCC_NCTF12
AA26
VCC_NCTF13
Y26
VCC_NCTF14
W26
VCC_NCTF15
V26
VCC_NCTF16
U26
VCC_NCTF17
T26
VCC_NCTF18
R26
VCC_NCTF19
AD25
VCC_NCTF20
AC25
VCC_NCTF21
AB25
VCC_NCTF22
AA25
VCC_NCTF23
Y25
VCC_NCTF24
W25
VCC_NCTF25
V25
VCC_NCTF26
U25
VCC_NCTF27
T25
VCC_NCTF28
R25
VCC_NCTF29
AD24
VCC_NCTF30
AC24
VCC_NCTF31
AB24
VCC_NCTF32
AA24
VCC_NCTF33
Y24
VCC_NCTF34
W24
VCC_NCTF35
V24
VCC_NCTF36
U24
VCC_NCTF37
T24
VCC_NCTF38
R24
VCC_NCTF39
AD23
VCC_NCTF40
V23
VCC_NCTF41
U23
VCC_NCTF42
T23
VCC_NCTF43
R23
VCC_NCTF44
AD22
VCC_NCTF45
V22
VCC_NCTF46
U22
VCC_NCTF47
T22
VCC_NCTF48
R22
VCC_NCTF49
AD21
VCC_NCTF50
V21
VCC_NCTF51
U21
VCC_NCTF52
T21
VCC_NCTF53
R21
VCC_NCTF54
AD20
VCC_NCTF55
V20
VCC_NCTF56
U20
VCC_NCTF57
T20
VCC_NCTF58
R20
VCC_NCTF59
AD19
VCC_NCTF60
V19
VCC_NCTF61
U19
VCC_NCTF62
T19
VCC_NCTF63
AD18
VCC_NCTF64
AC18
VCC_NCTF65
AB18
VCC_NCTF66
AA18
VCC_NCTF67
Y18
VCC_NCTF68
W18
VCC_NCTF69
V18
VCC_NCTF70
U18
VCC_NCTF71
T18
VCC_NCTF72
M19
VCC100
L19
VCC101
N18
VCC102
M18
VCC103
L18
VCC104
P17
VCC105
N17
VCC106
M17
VCC107
N16
VCC108
M16
VCC109
L16
VCC110
CALISTOGA_FCBGA1466~D
<BOM Structure>
VCCAUX_NCTF0
VCCAUX_NCTF1
VCCAUX_NCTF2
VCCAUX_NCTF3
VCCAUX_NCTF4
VCCAUX_NCTF5
VCCAUX_NCTF6
VCCAUX_NCTF7
VCCAUX_NCTF8
VCCAUX_NCTF9
VCCAUX_NCTF10
VCCAUX_NCTF11
VCCAUX_NCTF12
VCCAUX_NCTF13
VCCAUX_NCTF14
VCCAUX_NCTF15
VCCAUX_NCTF16
VCCAUX_NCTF17
VCCAUX_NCTF18
VCCAUX_NCTF19
VCCAUX_NCTF20
VCCAUX_NCTF21
VCCAUX_NCTF22
VCCAUX_NCTF23
VCCAUX_NCTF24
VCCAUX_NCTF25
VCCAUX_NCTF26
VCCAUX_NCTF27
VCCAUX_NCTF28
VCCAUX_NCTF29
VCCAUX_NCTF30
VCCAUX_NCTF31
VCCAUX_NCTF32
VCCAUX_NCTF33
VCCAUX_NCTF34
VCCAUX_NCTF35
VCCAUX_NCTF36
P O W E R
VCCAUX_NCTF37
VCCAUX_NCTF38
VCCAUX_NCTF39
VCCAUX_NCTF40
VCCAUX_NCTF41
VCCAUX_NCTF42
VCCAUX_NCTF43
VCCAUX_NCTF44
VCCAUX_NCTF45
VCCAUX_NCTF46
VCCAUX_NCTF47
VCCAUX_NCTF48
VCCAUX_NCTF49
VCCAUX_NCTF50
VCCAUX_NCTF51
VCCAUX_NCTF52
VCCAUX_NCTF53
VCCAUX_NCTF54
VCCAUX_NCTF55
VCCAUX_NCTF56
VCCAUX_NCTF57
VSS_NCTF0
VSS_NCTF1
VSS_NCTF2
VSS_NCTF3
VSS_NCTF4
VSS_NCTF5
VSS_NCTF6
VSS_NCTF7
VSS_NCTF8
VSS_NCTF9
VSS_NCTF10
VSS_NCTF11
VSS_NCTF12
VCC_SM100
VCC_SM101
VCC_SM102
VCC_SM103
VCC_SM104
VCC_SM105
VCC_SM106
VCC_SM107
AG27
AF27
AG26
AF26
AG25
AF25
AG24
AF24
AG23
AF23
AG22
AF22
AG21
AF21
AG20
AF20
AG19
AF19
R19
AG18
AF18
R18
AG17
AF17
AE17
AD17
AB17
AA17
W17
V17
T17
R17
AG16
AF16
AE16
AD16
AC16
AB16
AA16
Y16
W16
V16
U16
T16
R16
AG15
AF15
AE15
AD15
AC15
AB15
AA15
Y15
W15
V15
U15
T15
R15
AE27
AE26
AE25
AE24
AE23
AE22
AE21
AE20
AE19
AE18
AC17
Y17
U17
AR6
AP6
AN6
AL6
AK6
AJ6
AV1
AJ1
+1.5VS
C316
+1.8V
0.47U_0603_10V7K
1
1
C81
2
2
0.47U_0603_10V7K
Place near pin AV1 & AJ1
A A
+VCCP
AA33
W33
N33
AA32
W32
N32
M32
AA31
W31
R31
N31
M31
AA30
W30
U30
R30
N30
M30
AA29
W29
U29
R29
M29
AB28
AA28
U28
R28
N28
M28
N27
M27
N26
N25
M25
N24
M24
AB23
AA23
N23
M23
AC22
AB22
W22
N22
M22
AC21
AA21
W21
N21
M21
AC20
AB20
W20
N20
M20
AB19
AA19
N19
P33
L33
J33
Y32
V32
P32
L32
J32
V31
T31
P31
Y30
V30
T30
P30
L30
Y29
V29
P29
L29
Y28
V28
T28
P28
L28
P27
L27
P26
L26
L25
P24
Y23
P23
L23
Y22
P22
L22
L21
Y20
P20
L20
Y19
U7G
VCC0
VCC1
VCC2
VCC3
VCC4
VCC5
VCC6
VCC7
VCC8
VCC9
VCC10
VCC11
VCC12
VCC13
VCC14
VCC15
VCC16
VCC17
VCC18
VCC19
VCC20
VCC21
VCC22
VCC23
VCC24
VCC25
VCC26
VCC27
VCC28
VCC29
VCC30
VCC31
VCC32
P O W E R
VCC33
VCC34
VCC35
VCC36
VCC37
VCC38
VCC39
VCC40
VCC41
VCC42
VCC43
VCC44
VCC45
VCC46
VCC47
VCC48
VCC49
VCC50
VCC51
VCC52
VCC53
VCC54
VCC55
VCC56
VCC57
VCC58
VCC59
VCC60
VCC61
VCC62
VCC63
VCC64
VCC65
VCC66
VCC67
VCC68
VCC69
VCC70
VCC71
VCC72
VCC73
VCC74
VCC75
VCC76
VCC77
VCC78
VCC79
VCC80
VCC81
VCC82
VCC83
VCC84
VCC85
VCC86
VCC87
VCC88
VCC89
VCC90
VCC91
VCC92
VCC93
VCC94
VCC95
VCC96
VCC97
VCC98
VCC99
CALISTOGA_FCBGA1466~D
<BOM Structure>
VCC_SM0
VCC_SM1
VCC_SM2
VCC_SM3
VCC_SM4
VCC_SM5
VCC_SM6
VCC_SM7
VCC_SM8
VCC_SM9
VCC_SM10
VCC_SM11
VCC_SM12
VCC_SM13
VCC_SM14
VCC_SM15
VCC_SM16
VCC_SM17
VCC_SM18
VCC_SM19
VCC_SM20
VCC_SM21
VCC_SM22
VCC_SM23
VCC_SM24
VCC_SM25
VCC_SM26
VCC_SM27
VCC_SM28
VCC_SM29
VCC_SM30
VCC_SM31
VCC_SM32
VCC_SM33
VCC_SM34
VCC_SM35
VCC_SM36
VCC_SM37
VCC_SM38
VCC_SM39
VCC_SM40
VCC_SM41
VCC_SM42
VCC_SM43
VCC_SM44
VCC_SM45
VCC_SM46
VCC_SM47
VCC_SM48
VCC_SM49
VCC_SM50
VCC_SM51
VCC_SM52
VCC_SM53
VCC_SM54
VCC_SM55
VCC_SM56
VCC_SM57
VCC_SM58
VCC_SM59
VCC_SM60
VCC_SM61
VCC_SM62
VCC_SM63
VCC_SM64
VCC_SM65
VCC_SM66
VCC_SM67
VCC_SM68
VCC_SM69
VCC_SM70
VCC_SM71
VCC_SM72
VCC_SM73
VCC_SM74
VCC_SM75
VCC_SM76
VCC_SM77
VCC_SM78
VCC_SM79
VCC_SM80
VCC_SM81
VCC_SM82
VCC_SM83
VCC_SM84
VCC_SM85
VCC_SM86
VCC_SM87
VCC_SM88
VCC_SM89
VCC_SM90
VCC_SM91
VCC_SM92
VCC_SM93
VCC_SM94
VCC_SM95
VCC_SM96
VCC_SM97
VCC_SM98
VCC_SM99
AU41
AT41
AM41
AU40
BA34
AY34
AW34
AV34
AU34
AT34
AR34
BA30
AY30
AW30
AV30
AU30
AT30
AR30
AP30
AN30
AM30
AM29
AL29
AK29
AJ29
AH29
AJ28
AH28
AJ27
AH27
BA26
AY26
AW26
AV26
AU26
AT26
AR26
AJ26
AH26
AJ25
AH25
AJ24
AH24
BA23
AJ23
BA22
AY22
AW22
AV22
AU22
AT22
AR22
AP22
AK22
AJ22
AK21
AK20
BA19
AY19
AW19
AV19
AU19
AT19
AR19
AP19
AK19
AJ19
AJ18
AJ17
AH17
AJ16
AH16
BA15
AY15
AW15
AV15
AU15
AT15
AR15
AJ15
AJ14
AJ13
AH13
AK12
AJ12
AH12
AG12
AK11
BA8
AY8
AW8
AV8
AT8
AR8
AP8
BA6
AY6
AW6
AV6
AT6
+1.8V
MCH_AT41
MCH_AM41
C125
1
1
C124
2
2
0.47U_0603_10V7K
0.47U_0603_10V7K
Place near pin AT41 & AM41
1
1
C329
C370
2
2
0.1U_0402_16V4Z
1
C123
2
0.47U_0603_10V7K
Place near pin BA23
1
1
C126
C122
C365
2
2
10U_1206_6.3V6M
10U_1206_6.3V6M
1
2
0.47U_0603_10V7K
Place near pin BA15
CFG[2:0]
CFG5
CFG7
CFG9
CFG6
PSB 4X CLK Enable 1 = Calistoga
CFG[13:12]
CFG16
1
2
0.1U_0402_16V4Z
CFG10 CFG18
CFG19
1
C355
C341
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
SDVO_CTRLDATA
CFG20
(PCIE/SDVO select)
1
+
C85
2
220U_D2_4M_R45@
CFG[3:17] have internal pull up
CFG[19:18] have internal pull down
011 = 667MT/s FSB
001 = 533MT/s FSB
0 = DMI x 2
1 = DMI x 4
0 = Reserved
1 = Mobile Yonah CPU
0 = Lane Reversal Enable
1 = Normal Operation
(Default)
*
(Default)
*
(Default)
0 = Reserved
*
00 = Reserved
01 = XOR Mode Enabled
10 = All Z Mode Enabled
11 = Normal Operation
0 = Dynamic ODT Disabled
1 = Dynamic ODT Enabled (Default)
10 = 1.05V
01 = 1.5V
0 = Normal Operation
1 = DMI Lane Reversal Enable
0 = No SDVO Device Present
*
(Default)
(Default)
1 = SDVO Device Present
0 = Only PCIE or SDVO is
operational.
1 = PCIE/SDVO are operating
simu.
CFG39
CFG179
CFG59
CFG79
CFG99
CFG119
CFG129
CFG139
CFG169
CFG189
CFG199
CFG209
*
R284 2.2K_0402_5%@
1 2
R282 2.2K_0402_5%@
1 2
R67 2.2K_0402_5%@
1 2
R77 2.2K_0402_5%@
1 2
R72 2.2K_0402_5%@
1 2
R69 2.2K_0402_5%@
1 2
R64 2.2K_0402_5%@
1 2
R283 2.2K_0402_5%@
1 2
R74 2.2K_0402_5%@
1 2
R289 1K_0402_5%@
1 2
R292 1K_0402_5%@
1 2
R290 1K_0402_5%@
1 2
*
*
(Default)
*
(Default)
*
(Default)
*
+3VS
Security Classification
Issued Date
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2005/09/10 2006/06/23
Compal Secret Data
Deciphered Date
Title
Size Document Number Rev
Custom
2
Date: Sheet
Compal Electronics, Inc.
SCHEMATIC, M/B LA-3051P
401397
星期四 十月
13 45, 06, 2005
1
A
of
5
4
3
2
1
U7I
AC41
VSS0
AA41
VSS1
W41
VSS2
T41
VSS3
P41
VSS4
M41
D D
C C
B B
A A
VSS5
J41
VSS6
F41
VSS7
AV40
VSS8
AP40
VSS9
AN40
VSS10
AK40
VSS11
AJ40
VSS12
AH40
VSS13
AG40
VSS14
AF40
VSS15
AE40
VSS16
B40
VSS17
AY39
VSS18
AW39
VSS19
AV39
VSS20
AR39
VSS21
AN39
VSS22
AJ39
VSS23
AC39
VSS24
AB39
VSS25
AA39
VSS26
Y39
VSS27
W39
VSS28
V39
VSS29
T39
VSS30
R39
VSS31
P39
VSS32
N39
VSS33
M39
VSS34
L39
VSS35
J39
VSS36
H39
VSS37
G39
VSS38
F39
VSS39
D39
VSS40
AT38
VSS41
AM38
VSS42
AH38
VSS43
AG38
VSS44
AF38
VSS45
AE38
VSS46
C38
VSS47
AK37
VSS48
AH37
VSS49
AB37
VSS50
AA37
VSS51
Y37
VSS52
W37
VSS53
V37
VSS54
T37
VSS55
R37
VSS56
P37
VSS57
N37
VSS58
M37
VSS59
L37
VSS60
J37
VSS61
H37
VSS62
G37
VSS63
F37
VSS64
D37
VSS65
AY36
VSS66
AW36
VSS67
AN36
VSS68
AH36
VSS69
AG36
VSS70
AF36
VSS71
AE36
VSS72
AC36
VSS73
C36
VSS74
B36
VSS75
BA35
VSS76
AV35
VSS77
AR35
VSS78
AH35
VSS79
AB35
VSS80
AA35
VSS81
Y35
VSS82
W35
VSS83
V35
VSS84
T35
VSS85
R35
VSS86
P35
VSS87
N35
VSS88
M35
VSS89
L35
VSS90
J35
VSS91
H35
VSS92
G35
VSS93
F35
VSS94
D35
VSS95
AN34
VSS96
AK34
VSS97
AG34
VSS98
AF34
VSS99
CALISTOGA_FCBGA1466~D
<BOM Structure>
P O W E R
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS140
VSS141
VSS142
VSS143
VSS144
VSS145
VSS146
VSS147
VSS148
VSS149
VSS150
VSS151
VSS152
VSS153
VSS154
VSS155
VSS156
VSS157
VSS158
VSS159
VSS160
VSS161
VSS162
VSS163
VSS164
VSS165
VSS166
VSS167
VSS168
VSS169
VSS170
VSS171
VSS172
VSS173
VSS174
VSS175
VSS176
VSS177
VSS178
VSS179
VSS180
VSS181
VSS182
VSS183
VSS184
VSS185
VSS186
VSS187
VSS188
VSS189
VSS190
VSS191
VSS192
VSS193
VSS194
VSS195
VSS196
VSS197
VSS198
VSS199
AE34
AC34
C34
AW33
AV33
AR33
AE33
AB33
Y33
V33
T33
R33
M33
H33
G33
F33
D33
B33
AH32
AG32
AF32
AE32
AC32
AB32
G32
B32
AY31
AV31
AN31
AJ31
AG31
AB31
Y31
AB30
E30
AT29
AN29
AB29
T29
N29
K29
G29
E29
C29
B29
A29
BA28
AW28
AU28
AP28
AM28
AD28
AC28
W28
J28
E28
AP27
AM27
AK27
J27
G27
F27
C27
B27
AN26
M26
K26
F26
D26
AK25
P25
K25
H25
E25
D25
A25
BA24
AU24
AL24
AW23
AT23
AN23
AM23
AH23
AC23
W23
K23
J23
F23
C23
AA22
K22
G22
F22
E22
D22
A22
BA21
AV21
AR21
U7J
AN21
VSS200
AL21
VSS201
AB21
VSS202
Y21
VSS203
P21
VSS204
K21
VSS205
J21
VSS206
H21
VSS207
C21
VSS208
AW20
VSS209
AR20
VSS210
AM20
VSS211
AA20
VSS212
K20
VSS213
B20
VSS214
A20
VSS215
AN19
VSS216
AC19
VSS217
W19
VSS218
K19
VSS219
G19
VSS220
C19
VSS221
AH18
VSS222
P18
VSS223
H18
VSS224
D18
VSS225
A18
VSS226
AY17
VSS227
AR17
VSS228
AP17
VSS229
AM17
VSS230
AK17
VSS231
AV16
VSS232
AN16
VSS233
AL16
VSS234
J16
VSS235
F16
VSS236
C16
VSS237
AN15
VSS238
AM15
VSS239
AK15
VSS240
N15
VSS241
M15
VSS242
L15
VSS243
B15
VSS244
A15
VSS245
BA14
VSS246
AT14
VSS247
AK14
VSS248
AD14
VSS249
AA14
VSS250
U14
VSS251
K14
VSS252
H14
VSS253
E14
VSS254
AV13
VSS255
AR13
VSS256
AN13
VSS257
AM13
VSS258
AL13
VSS259
AG13
VSS260
P13
VSS261
F13
VSS262
D13
VSS265
B13
VSS264
AY12
VSS263
AC12
VSS266
K12
VSS267
H12
VSS268
E12
VSS269
AD11
VSS270
AA11
VSS271
Y11
VSS272
J11
VSS273
D11
VSS274
B11
VSS275
AV10
VSS276
AP10
VSS277
AL10
VSS278
AJ10
VSS279
CALISTOGA_FCBGA1466~D
<BOM Structure>
P O W E R
VSS280
VSS281
VSS282
VSS283
VSS284
VSS285
VSS286
VSS287
VSS288
VSS289
VSS290
VSS292
VSS291
VSS293
VSS294
VSS295
VSS296
VSS297
VSS298
VSS299
VSS300
VSS301
VSS302
VSS303
VSS304
VSS305
VSS306
VSS307
VSS308
VSS309
VSS310
VSS311
VSS312
VSS313
VSS314
VSS315
VSS316
VSS317
VSS318
VSS319
VSS320
VSS321
VSS322
VSS323
VSS324
VSS325
VSS326
VSS327
VSS328
VSS329
VSS330
VSS331
VSS332
VSS333
VSS334
VSS335
VSS336
VSS337
VSS338
VSS339
VSS340
VSS341
VSS342
VSS343
VSS344
VSS345
VSS346
VSS347
VSS348
VSS349
VSS350
VSS351
VSS352
VSS353
VSS354
VSS355
VSS356
VSS357
VSS358
VSS359
VSS360
AG10
AC10
W10
U10
BA9
AW9
AR9
AH9
AB9
Y9
R9
G9
E9
A9
AG8
AD8
AA8
U8
K8
C8
BA7
AV7
AP7
AL7
AJ7
AH7
AF7
AC7
R7
G7
D7
AG6
AD6
AB6
Y6
U6
N6
K6
H6
B6
AV5
AF5
AD5
AY4
AR4
AP4
AL4
AJ4
Y4
U4
R4
J4
F4
C4
AY3
AW3
AV3
AL3
AH3
AG3
AF3
AD3
AC3
AA3
G3
AT2
AR2
AP2
AK2
AJ2
AD2
AB2
Y2
U2
T2
N2
J2
H2
F2
C2
AL1
Security Classification
Issued Date
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2005/09/10 2006/06/23
Compal Secret Data
Deciphered Date
Title
Size Document Number Rev
Custom
2
Date: Sheet
Compal Electronics, Inc.
SCHEMATIC, M/B LA-3051P
401397
星期四 十月
05
14 45, 06, 20
1
A
of
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