COMPAL LA-3051P Schematics

A

1 1

B

C

D

E

LC2A Schematic

2 2

Pentium-M

945GM+ICH7

DATE: Sept. 10th Revision: 0.2

3 3

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITT EN CON SENT O F COMPAL ELECTRONICS, INC.

2005/09/10 2006/06/23

C

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

D

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, M/B LA-3051P

星期

四十月

401397

, 06, 2005

E

145

A

of

Page Function

5

4

3

2

1

1 Cover Page

2

3

4

D D

5

6

7

8

9

10

11

12

13

14

15

C C

16

17

18

19

20

21

22

23

24

25

B B

26

27

28

29

30

31

32

33

34

35

36

A A

37

38

39

40

41

42 PWR-CPU_CORE

5

Index

Block Diagram

Notes List

Power Block

Yonah(1/2)-GTL/ITP-XDP

Yonah(2/2)-PWR/GND

Yonah bypass

Calistoga(1/6)-GTL/DMI/DDR

Calistoga(2/6)-DDR2 A/B CH

Calistoga(3/6)-VGA/LVDS/TV

Calistoga(4/6)-PWR

Calistoga(5/6)-PWR/GND

Calistoga(6/6)-PWR/GND

DDRII-SODIMM2

DDRII SO-DIMM B

ClockGen

TV-OUT/LVDS/CRT

ICH7M(1/4)_HUB,PCI,HOST

ICH7M(2/4)LAN,ATA,LPC,RTC

ICH7M(3/4)USB,GPIO,PCIE

ICH7-M(4/4)_POWER&GND

SATA/CD_ROM/G-SENSORConn.

USB/BlueTooth/FP

BCM5751M-GLAN

RJ-45 Connector

MINI_CARD SLOT-WLAN

R5C842-PCI/CARD BUS/OHCI

CARD BUS/1394

HD Audio Codec_ALC260D

AMP./Audio Jack

ENE-KB910L/TPM

BIOS/EE-Prom/TP/KB/SW

DC TO DC

PWR DCIN / Precharge

PWR CPU OTP

PWR-Battery Select

PWR-Charger

PWR-3V/5V

PWR-1.8V/1.5V

PWR-VCCPP/2.5V/0.9V

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

4

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/09/10 2006/06/23

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

2

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, M/B LA-3051P

星期四 十月

401397

245, 06, 2005

1

A

of

A

B

C

D

E

BLOCK DIAGRAM

4 4

Pentium-M
CPU Yonah

6,7,8

LM75CIMMX-5

10

Thermal Sensor
ADM1032ARM

Clock Generator

617

ICS954325

G SENSORThermal Sensor

23

FSB

533/667MHz

TV-OUT

CRT Conn.

3 3

LVDS Conn.

18

18

18

Intel Calistoga
GMCH

PCBGA 1466

9,10,11,12,13,14

2.5GHz(1.2V)

Bandwidth 500MB

400/533/667MHz
(1.8V)

Memory Bus

SO-DIMM x 2(DDRII)

BANK 0,1,2,3

15,16

FANController

Power Buttom/SW/LED

6

33

DMI

BATTERY

CHARGER

IDSEL: AD20 IRQE/F/G/H REQ#/GNT#2 IDSEL: AD18 IRQF/G REQ#/GNT#3

PCI BUS

33MHz (3.3V)

Intel ICH7-M

PCIE BUS

2 2

Ricoh

R5C842

Broadcom

BCM5751M

25

Mini Card
FOR WLAN

2728

mBGA-652

19,20,21,22

LPC 33MHz

480MHz

SATA

IDE

AC-LINK

24.576MHz

USB 2.0 Port *4

SATA HDD

ODD Module

24

23

23

DC/DC Interface

3VALWP/5VALWP

VCCP/0.9VSP

1.2VSP/1.8VALWP

37

38

35

39

41

40

RJ-45

1394-Port

CB PWR SW

CardBus*2

29 29

29

R5534V

26

Mini PCI
FOR WLAN

1 1

A

43

B

Embedded
Controller

ENE KB910L

BIOS(1MB)

MDC

31

Int. KB &
Touch-PAD

32 32

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITT EN CON SENT O F COMPAL ELECTRONICS, INC.

2005/09/10 2006/06/23

C

Connector

30

RJ-11

Compal Secret Data

Deciphered Date

Audio Amp.

TPA6017

SPK 1W*2

D

Realtek
ALC262

31 31

31

30

HP*1
MIC*1

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, M/B LA-3051P

星期

, 06, 2005

四十月

CPU_CORE

401397

E

42

A

of

345

A

B

C

D

E

Voltage Rails

Dip SW function

KBSEL0/1# 11:JP K/B 01:US K/B 10:UK K/B 00: Reserve

Power Plane Description

VIN

1 1

2 2

B+

+CPU_CORE

+VCCP

+1.8VS ON OFF OFF1.8VS switched power rail

+0.9VS

+3.3V 3.3V switched power rail

+3VALW

+3VS

+5VALW ON

+5VS

+RTCVCC

Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.

Adapter power supply (19V)

AC or battery power rail for power circuit.

Core voltage for CPU

1.05V switched power rail for CPU AGTL Bus

0.9V power rail

3.3V always on powe r rail

3.3V switched power rail

5V always on power r ail ON+5V ON OFF

5V always on power r ail

5V switched power rail

RTC power

External PCI Devices

CardBus(R5C842)

Mini-PCI(WLAN) AD18 3 PIRQG/PIRQH

IDSEL#Device

AD20 2 PIRQE/PIRQF/PIRQG/PIRQH

REQ#/GNT# Interrupts

S1 S3 S5

ON

ON ONONON

ON OFF

ON OFF

ON ON OFF1.8V power rail+1.8V

OFFON

ON

ON

ON

ON ON *

OFF

ON

OFF

ON

ON

ON

ON

OFF

OFF

OFF

OFF

OFFON

ON*

OFF

ON

PASSWORD# 0:Override 1:Avaliable
FINGERPRINT# 0:Existence 1:Non-Existence

Function Table

Function

TV-OUT
Bluetooth
PWR LED

(Odekake)
S/W I/II Key

4 in 1 Card
Adapter
Finger Print

TPM
W-LAN

Japan

Commercial Consumer

NEC
Direct(Internet

LaVie

Retailing)

Yes

YesNo

No

No Yes

Yes (BTO)

Yes

JP JP JP

No No
No

Yes (BTO)

Chip Reversion

945GM

ICH7
CLK Gen
KB910L
ALC262

Phase

ES Phase

A2
B0
A
A1
A2

PP Phase MP1 Phae IRT

Chip

HK/CHINA

Oversea

Comment

Need BTO
Not need

Odekake
all same

Need BTO
Need BTO

BCM5751 C1

3 3

EC SM Bus1 address

AddressDevice AddressDevice

Main Battery

EEPROM(24C16/02) Second Battery

ADM1032

0001 011X b

1010 000X b

1001 110X b

EC SM Bus2 address

KXP84-0200

LM75CIMMX-5

0011 000X b

ICH7 SM Bus address

Device

Clock Generator

4 4

(ICS954325AKLFT)

DDR DIMM0

DDR DIMM1

A

Address

1101 001Xb

1010 000Xb

1010 001Xb

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITT EN CON SENT O F COMPAL ELECTRONICS, INC.

2005/09/10 2006/06/23

C

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

D

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, M/B LA-3051P

星期

四十月

401397

, 06, 2005

E

445

A

of

5

4

3

2

1

LC2a Power block

RTC Charger

D D

Battery OVP

Vin Detector

Page 35

Input

DC IN

C C

CHARGER

Switch

Turn Off

Page 37

Page 38

+CHGRTC

B+

Page 35

CPU OTP

Page 36

Turn Off

+3VALWP: OCP:6A OVP:107%~115%
+5VALWP: OCP:8A OVP:107%~115%
(MAX8734A)

Page 39

Always

CC:0.6A~3.3A
CV:12.6V
(MB3887)

Page 38

+3VALW

+2.5VSP
Thermal protection: 150 degree C
(G914E)

Page 41

SUSP#

Battery

B B

CPU CORE

+1.8VP: OCP:11.7A OVP:112%~117%
+1.5VSP: OCP:6A OVP:112%~117%
(MAX8743)

+1.8V

+0.9VSP
Protectio n :d e pend on +1.8 VP
(APL5331)

Page 40

Page 41

+1.8VP:SYSON

+1.5VSP:SUSP#

SUSP

VR_ON

OCP:54A
OVP:2V
(ISL6262)

Page 42

+VCCP:OCP:12A OVP:115%

A A

Security Cla ssification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONIC S, INC. AND CONTAI NS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

3

2005/09/10 2006/06/23

Protection:depend on +1.05VSP
(ISL6269)

Compal Secret Data

Deciphered Date

2

Page 41

SUSP#

Title

Size Docu m e n t N u m b e r Re v

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, M/B LA-3051P

星期四

401397

06, 2005

十月

545,

1

of

A

A

H_A#[3..31]9

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9

CLK_CPU_BCLK
CLK_CPU_BCLK#

H_RESET#

H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

H_ADSTB#0
H_ADSTB#1

H_ADS#
H_BNR#
H_BPRI#
H_BR0#
H_DEFER#
H_DRDY#
H_HIT#
H_HITM#
H_IERR#
H_LOCK#
H_RESET#

H_RS#0
H_RS#1
H_RS#2
H_TRDY#

ITP_BPM#0
ITP_BPM#1
ITP_BPM#2
ITP_BPM#3

ITP_DBRESET#

H_DBSY#
H_DPSLP#
H_DPRSTP#
H_DPWR#
ITP_BPM#4
ITP_BPM#5
H_PROCHOT#

H_PWRGOOD
H_CPUSLP#
ITP_TCK
ITP_TDI
ITP_TDO
TEST1
TEST2
ITP_TMS
ITP_TRST#

H_THERMDA
H_THERMDC
H_THERMTRIP#

1 1

H_REQ#[0..4]9

H_ADSTB#09

2 2

R265

56_0402_5%

1 2

+VCCP

3 3

H_THERMDA, H_THERMDC routing together.
Trace width / Spacing = 10 / 10 mil

4 4

H_ADSTB#19

CLK_CPU_BCLK17

CLK_CPU_BCLK#17

H_ADS#9
H_BNR#9

H_BPRI#9

H_DEFER#9

H_DRDY#9

H_HITM#9

H_LOCK#9

H_RESET#9

H_RS#[0..2]9

H_TRDY#9

ITP_DBRESET#21

H_DBSY#9

H_DPSLP#20

H_DPRSTP#20,42

H_DPWR#9

H_PWRGOOD20

H_CPUSLP#9,20

R275 1K_0402_5%@

1 2

R276 51_0402_5%

1 2

H_THERMTRIP#9,20

+VCCP

R270

54.9_0402_1%

1 2

A

H_BR0#9

H_HIT#9

JP3A

J4

A3#

L4

A4#

M3

A5#

K5

A6#

M1

A7#

N2

A8#

J1

A9#

N3

A10#

P5

A11#

P2

A12#

L1

A13#

P4

A14#

P1

A15#

R1

A16#

Y2

A17#

U5

A18#

R3

A19#

W6

A20#

U4

A21#

Y5

A22#

U2

A23#

R4

A24#

T5

ADDR GROUP

A25#

T3

A26#

W3

A27#

W5

A28#

Y4

A29#

W2

A30#

Y1

A31#

K3

REQ0#

H2

REQ1#

K2

REQ2#

J3

REQ3#

L5

REQ4#

L2

ADSTB0#

V4

ADSTB1#

A22

BCLK0

AD4
AD3
AD1
AC4

C20

D24
AC2
AC1
D21

AC5
AA6
AB3
C26
D25
AB5
AB6

A21

H1

E2

G5

F1

H5

F21

G6

E4

D20

H4

B1

F3

F4
G3
G2

E1

B5

E5

D6
D7

A24
A25

C7

HOST CLK

BCLK1

ADS#
BNR#
BPRI#
BR0#
DEFER#
DRDY#
HIT#

CONTROL

HITM#
IERR#
LOCK#
RESET#

RS0#
RS1#
RS2#
TRDY#

BPM0#
BPM1#
BPM2#
BPM3#

DBR#
DBSY#
DPSLP#
DPRSTP#
DPWR#
PRDY#
PREQ#
PROCHOT#

PWRGOOD
SLP#
TCK
TDI
TDO
TEST1
TEST2
TMS
TRST#

THERMAL

THERMDA

DIODE

THERMDC
THERMTRIP#

FOX_PZ47823-2743-41_YONAH

H_DPSLP#

H_DPRSTP#

YONAH

MISC

1 2

1 2

B

DATA GROUP

LEGACY CPU

+VCCP

R271

56_0402_5%@

R266

56_0402_5%@

B

D10#
D11#
D12#
D13#
D14#
D15#
D16#
D17#
D18#
D19#
D20#
D21#
D22#
D23#
D24#
D25#
D26#
D27#
D28#
D29#
D30#
D31#
D32#
D33#
D34#
D35#
D36#
D37#
D38#
D39#
D40#
D41#
D42#
D43#
D44#
D45#
D46#
D47#
D48#
D49#
D50#
D51#
D52#
D53#
D54#
D55#
D56#
D57#
D58#
D59#
D60#
D61#
D62#
D63#

DINV0#
DINV1#
DINV2#
DINV3#

DSTBN0#
DSTBN1#
DSTBN2#
DSTBN3#
DSTBP0#
DSTBP1#
DSTBP2#
DSTBP3#

A20M#
FERR#

IGNNE#

INIT#
LINT0
LINT1

STPCLK#

SMI#

C

ITP_DBRESET#

H_D#[0..63] 9

H_D#0

E22

D0#

H_D#1

F24

D1#

H_D#2

E26

D2#

H_D#3

H22

D3#

H_D#4

F23

D4#

H_D#5

G25

D5#

H_D#6

E25

D6#

H_D#7

E23

D7#

H_D#8

K24

D8#

H_D#9

G24

D9#

H_D#10

J24

H_D#11

J23

H_D#12

H26

H_D#13

F26

H_D#14

K22

H_D#15

H25

H_D#16

N22

H_D#17

K25

H_D#18

P26

H_D#19

R23

H_D#20

L25

H_D#21

L22

H_D#22

L23

H_D#23

M23

H_D#24

P25

H_D#25

P22

H_D#26

P23

H_D#27

T24

H_D#28

R24

H_D#29

L26

H_D#30

T25

H_D#31

N24

H_D#32

AA23

H_D#33

AB24

H_D#34

V24

H_D#35

V26

H_D#36

W25

H_D#37

U23

H_D#38

U25
U22
AB25
W22
Y23
AA26
Y26
Y22
AC26
AA24
AC22
AC23
AB22
AA21
AB21
AC25
AD20
AE22
AF23
AD24
AE21
AD21
AE25
AF25
AF22
AF26

J26
M26
V23
AC20

H23
M24
W24
AD23
G22
N25
Y25
AE24

A6
A5
C4
B3
C6
B4

D5
A3

H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63

H_DINV#0
H_DINV#1
H_DINV#2
H_DINV#3

H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3
H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3

H_A20M#
H_FERR#
H_IGNNE#
H_INIT#
H_INTR
H_NMI

H_STPCLK#
H_SMI#

H_DINV#0 9
H_DINV#1 9
H_DINV#2 9
H_DINV#3 9

H_DSTBN#[0..3] 9

H_DSTBP # [0 ..3 ] 9

H_A20M# 20
H_FERR# 20
H_IGNNE# 20
H_INIT# 20
H_INTR 20
H_NMI 20

H_STPCLK# 20
H_SMI# 20

FAN CONN. 1

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITT EN CON SENT O F COMPAL ELECTRONICS, INC.

C

R273 200_0402_5%@

1 2

EN_FAN132

2005/09/10 2006/06/23

R344 100K_0402_5%

0.1U_0402_16V4Z

5
6

Compal Secret Data

1 2

C393

U14B

+IN

OUT

-IN

LM358DR2G_SO8~N

100K_0402_5%

1 2

C70

0.1U_0402_10V6K~N@

+VCCP

H_THERMTRIP#

Deciphered Date

ITP_BPM#0
ITP_BPM#1
ITP_BPM#2
ITP_BPM#3
ITP_BPM#4

2

1

7

+CPU_CORE

12

R45

1 2

R342

12

R47
56_0402_5%

PAD
PAD

PAD
PAD
PAD
PAD

+5VS

3

+IN

2

-IN

1 2

100K_0402_5%

R343
150K_0402_5%

C

2

B

E

1 2

OUT

D

T16

ITP_TDI

T11

ITP_TMS

T13
T12

ITP_TDO

T15
T14

ITP_BPM#5
ITP_TRST#
ITP_TCK

Thermal Sensor

C388

0.1U_0402_16V4Z

8

U14A

P

ENFAN1

1

G

4

LM358DR2G_SO8~N

1 2

C391 2200P_0402_50V7K~N

RB751V_SOD323

+3VS

FAN1_SPEED32

Q10
PMBT3904_SOT23

D

MAINPWON 35,36,39

1

3

This shall place near CPU

R259 56_0402_5%

1 2

R261 56_0402_1%

1 2

R262 56_0402_5%

1 2

R258 56_0402_5%

1 2

R260 56_0402_5%

1 2

R257 56_0402_5%

1 2

H_THERMDA

1

2200P_0402_50V7K~N

C78

EC_SMB_CK110,23,32,37
EC_SMB_DA110,23,32,37

+5VS +5VS_FAN

2

G

D13

1 2

R120 10K_0402_5%

2

H_THERMDC

F1

1.1A_6VDC_FUSE

12

R354
1K_0402_5%

3

13

D

Q21

S

2N7002_SOT23

1

@

2

2 1

22U_1206_10V4Z

Title

Size Document Number Rev

星期

Date: Sheet

+VCCP

21

SI3443DV_TSOP6

S

G

D

Q12

6

2451

1

C147

C144

2

1000P_0402_50V7K~N

1

C145

0.01U_0402_16V7K

2

+3V

12

R48

@

330_0603_5%

C

2

B

E

Q11

@

3 1

MMBT3904_SOT23

Compal Electronics, Inc.

SCHEMATIC, M/B LA-3051P

401397

, 06, 2005

四十月

E

+3VS

1

2

0.1U_0402_16V4Z

U6

2
3
8
7

VDD1

D+

ALERT#

D-

THERM#

SCLK

GND

SDATA

ADM1032ARMZ_MSOP8~N

Level shifter

H_PROCHOT_SIO#

1 2

R50 56_0402_5%@

1 2

R51 56_0402_5%

H_PROCHOT#

E

C76

12

R52

1

10K_0402_5%

6

@

4
5

JP5

1
2
3

MOLEX_53398-0371~N

+VCCP

+VCCP

H_PROCHOT#

of

645

A

A

B

C

D

E

+VCCP

12

V_CPU_GTLREF

1 1

R253
1K_0402_1%

12

R256
2K_0402_1%

Close to CPU pin AD26
within 0.5 inch

CPU_BSEL CPU_BSEL2 CPU_BSEL1

133

166

2 2

3 3

00

0

+CPU_CORE

Close to CPU pin
within 500mils.

CPU_BSEL0

1

R254
100_0402_1%

1 2

R255
100_0402_1%

1 2

1

1

12

R42

27.4_0402_1%

R39

54.9_0402_1%

VCCSENSE

VSSSENSE

12

R264

Length match within 25 mils
The trace width 18 mils space
7 mils

+1.5VS

1

C71

12

27.4_0402_1%

0.01U_0402_16V7K

Resistor placed within

12

0.5" of CPU pin.Trace
should be at least 25
mils away from any

R263

other toggling signal.

54.9_0402_1%

2

1

2

VCCSENSE42
VSSSENSE42

+VCCP

C69
10U_0805_10V4Z~N

H_PSI#42

CPU_VID042
CPU_VID142
CPU_VID242
CPU_VID342
CPU_VID442
CPU_VID542
CPU_VID642

V_CPU_GTLREF
CPU_BSEL017

CPU_BSEL117
CPU_BSEL217

+CPU_CORE

VCCSENSE
VSSSENSE

H_PSI#
CPU_VID0

CPU_VID1
CPU_VID2
CPU_VID3
CPU_VID4
CPU_VID5
CPU_VID6

CPU_BSEL0
CPU_BSEL1
CPU_BSEL2

COMP0
COMP1
COMP2
COMP3

JP3B

AF7

VCCSENSE

AE7

VSSSENSE

B26

VCCA

K6

VCCP

J6

VCCP

M6

VCCP

N6

VCCP

YONAH

VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP

PSI#
VID0

VID1
VID2
VID3
VID4
VID5
VID6

GTLREF
BSEL0

BSEL1
BSEL2

COMP0
COMP1
COMP2
COMP3

VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC

RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD

FOX_PZ47823-2743-41_YONAH

W21

AD6

AD26

AB20
AA20
AF20
AE20
AB18
AB17
AA18
AA17
AD18
AD17
AC18
AC17
AF18
AF17

T6
R6

K21

J21
M21
N21
T21
R21
V21

V6

G21

AE6

AF5
AE5
AF4
AE3
AF2
AE2

B22
B23
C21

R26
U26

U1
V1

E7

D2
F6
D3

C1
AF1
D22
C23
C24
AA1
AA4
AB2
AA3

M4

N5

T2

V3

B2

C3
T22
B25

AB26

VSS

AA25

VSS

AD25

VSS

AE26

VSS

AB23

VSS

AC24

VSS

AF24

VSS

AE23

VSS

AA22

VSS

AD22

VSS

AC21

VSS

AF21

VSS

AB19

VSS

AA19

VSS

AD19

VSS

AC19

VSS

AF19

VSS

AE19

VSS

AB16

VSS

AA16

VSS

AD16

VSS

AC16

VSS

AF16

VSS

AE16

VSS

AB13

VSS

AA14

VSS

AD13

VSS

AC14

VSS

AF13

VSS

AE14

VSS

AB11

VSS

AA11

VSS

AD11

VSS

AC11

VSS

AF11

VSS

AE11

VSS

AB8

VSS

AA8

VSS

AD8

VSS

AC8

VSS

AF8

VSS

AE8

VSS

AA5

VSS

AD5

VSS

AC6

VSS

AF6

VSS

AB4

VSS

AC3

VSS

POWER, GROUNG, RESERVED SIGNALS AND NC

AF3

VSS

AE4

VSS

AB1

VSS

AA2

VSS

AD2

VSS

AE1

VSS

B6

VSS

C5

VSS

F5

VSS

E6

VSS

H6

VSS

J5

VSS

M5

VSS

L6

VSS

P6

VSS

R5

VSS

V5

VSS

U6

VSS

Y6

VSS

A4

VSS

D4

VSS

E3

VSS

H3

VSS

G4

VSS

K4

VSS

L3

VSS

P3

VSS

N4

VSS

T4

VSS

U3

VSS

Y3

VSS

W4

VSS

D1

VSS

C2

VSS

F2

VSS

G1

VSS

+CPU_CORE

JP3C

AE18

VCC

AE17

VCC

AB15

VCC

AA15

VCC

AD15

VCC

AC15

VCC

AF15

VCC

AE15

VCC

AB14

VCC

AA13

VCC

AD14

VCC

AC13

VCC

AF14

VCC

AE13

VCC

AB12

VCC

AA12

VCC

AD12

VCC

AC12

VCC

AF12

VCC

AE12

VCC

AB10

VCC

AB9

VCC

AA10

VCC

AA9

VCC

AD10

VCC

AD9

VCC

AC10

VCC

AC9

VCC

AF10

VCC

AF9

VCC

AE10

POWER, GROUND

VCC

AE9

VCC

AB7

VCC

AA7

VCC

AD7

VCC

AC7

VCC

B20

VCC

A20

VCC

F20

VCC

E20

VCC

B18

VCC

B17

VCC

A18

VCC

A17

VCC

D18

VCC

D17

VCC

C18

VCC

C17

VCC

F18

VCC

F17

VCC

E18

VCC

E17

VCC

B15

VCC

A15

VCC

D15

VCC

C15

VCC

F15

VCC

E15

VCC

B14

VCC

A13

VCC

D14

VCC

C13

VCC

F14

VCC

E13

VCC

B12

VCC

A12

VCC

D12

VCC

C12

VCC

F12

VCC

E12

VCC

B10

VCC

B9

VCC

A10

VCC

A9

VCC

D10

VCC

D9

VCC

C10

VCC

C9

VCC

F10

VCC

F9

VCC

E10

VCC

E9

VCC

B7

VCC

A7

VCC

F7

VCC

FOX_PZ47823-2743-41_YONAH

YONAH

K1

VSS

J2

VSS

M2

VSS

N1

VSS

T1

VSS

R2

VSS

V2

VSS

W1

VSS

A26

VSS

D26

VSS

C25

VSS

F25

VSS

B24

VSS

A23

VSS

D23

VSS

E24

VSS

B21

VSS

C22

VSS

F22

VSS

E21

VSS

B19

VSS

A19

VSS

D19

VSS

C19

VSS

F19

VSS

E19

VSS

B16

VSS

A16

VSS

D16

VSS

C16

VSS

F16

VSS

E16

VSS

B13

VSS

A14

VSS

D13

VSS

C14

VSS

F13

VSS

E14

VSS

B11

VSS

A11

VSS

D11

VSS

C11

VSS

F11

VSS

E11

VSS

B8

VSS

A8

VSS

D8

VSS

C8

VSS

F8

VSS

E8

VSS

G26

VSS

K26

VSS

J25

VSS

M25

VSS

N26

VSS

T26

VSS

R25

VSS

V25

VSS

W26

VSS

H24

VSS

G23

VSS

K23

VSS

L24

VSS

P24

VSS

N23

VSS

T23

VSS

U24

VSS

Y24

VSS

W23

VSS

H21

VSS

J22

VSS

M22

VSS

L21

VSS

P21

VSS

R22

VSS

V22

VSS

U21

VSS

Y21

VSS

4 4

Security Cla ssification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONIC S, INC. AND CONTAI NS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

2005/09/10 2006/06/23

C

Compal Secret Data

Deciphered Date

Title

Size Doc u m e n t N umber Rev

D

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, M/B LA-3051P

星期四

401397

, 06, 2005

十月

E

745

A

of

A

B

C

D

E

1 1

Place these capacitors on L8
(North side,Secondary Layer)

Place these capacitors on L8
(North side,Secondary Layer)

Place these capacitors on L8
(Sorth side,Secondary Layer)

2 2

Place these capacitors on L8
(Sorth side,Secondary Layer)

3 3

South Side Secondary

+CPU_CORE

1

2

+CPU_CORE

1

2

+CPU_CORE

1

2

+CPU_CORE

1

2

+CPU_CORE

C54
22U_0805_6.3V6M

C66
22U_0805_6.3V6M

C285
22U_0805_6.3V6M

C300
22U_0805_6.3V6M

1

+

C36

2

330U_D2E_2.5VM_R9

C38

1

+

2

330U_D2E_2.5VM_R9

1

C55
22U_0805_6.3V6M

2

1

C65
22U_0805_6.3V6M

2

1

C286
22U_0805_6.3V6M

2

1

C299
22U_0805_6.3V6M

2

C37

330U_D2E_2.5VM_R9

C311

330U_D2E_2.5VM_R9

1

C57
22U_0805_6.3V6M

2

1

C63
22U_0805_6.3V6M

2

1

C288
22U_0805_6.3V6M

2

1

C297
22U_0805_6.3V6M

2

1

+

2

C312

330U_D2E_2.5VM_R9

1

C56

22U_0805_6.3V6M

2

1

C64

22U_0805_6.3V6M

2

1

C287
22U_0805_6.3V6M

2

1

C298
22U_0805_6.3V6M

2

1

+

2

1

+

C310

2

330U_D2E_2.5VM_R9

1

2

1

2

1

2

1

2

1

+

North Side Secondary

2

C58
22U_0805_6.3V6M

C281
22U_0805_6.3V6M

C304
22U_0805_6.3V6M

C308
22U_0805_6.3V6M

1

C59
22U_0805_6.3V6M

2

1

C282
22U_0805_6.3V6M

2

1

C303
22U_0805_6.3V6M

2

1

C307
22U_0805_6.3V6M

2

1

2

1

2

1

2

1

2

ESR <= 1.5m ohm
Capacitor > 1980uF

C68
22U_0805_6.3V6M

C283
22U_0805_6.3V6M

C302
22U_0805_6.3V6M

C278
22U_0805_6.3V6M

1

C67
22U_0805_6.3V6M

2

1

C284
22U_0805_6.3V6M

2

1

C301
22U_0805_6.3V6M

2

1

C277
22U_0805_6.3V6M

2

Mid Frequence Decoupling

7mOhm

330U_D2E_2.5VM_R9

@

C60

+VCCP

7mOhm
PS CAP

1

+

2

1

C289

0.1U_0402_16V4Z

2

1

C291

0.1U_0402_16V4Z

2

PS CAP

7mOhm
PS CAP

1

2

7mOhm
PS CAP

C294

0.1U_0402_16V4Z

7mOhm
PS CAP

1

C290

0.1U_0402_16V4Z

2

7mOhm
PS CAP

1

2

C292

0.1U_0402_16V4Z

1

C293

0.1U_0402_16V4Z

2

Place these inside
socket cavity on L8
(North side
Secondary)

330U ?

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITT EN CON SENT O F COMPAL ELECTRONICS, INC.

2005/09/10 2006/06/23

C

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

D

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, M/B LA-3051P

401397

星期

, 06, 2005

四十月

E

845

A

of

A

H_D#[0..63]6

1 1

2 2

+VCCP

12

12

R56

54.9_0402_1%

+VCCP

R68

R65

12

R59

24.9_0402_1%

12

100_0402_1%

12

200_0402_1%

R55

54.9_0402_1%

3 3

4 4

H_D#0
H_D#1
H_D#2
H_D#3
H_D#4 CFG3
H_D#5 CFG4
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63

H_VREF
H_XRCOMP
H_XSCOMP
H_YRCOMP
H_YSCOMP
H_SWNG0
H_SWNG1

12

R57

24.9_0402_1%

Layout Note:
H_XRCOMP / H_YRCOMP / H_VREF / H_SWNG0 /
H_SWNG1 trace width and spacing is 10/20.

H_VREF

1

C88

2

0.1U_0402_16V4Z

A

K11
T10

W11

U11
T11

W9

W7

W6

AB7
AA9

W4
W3

W5
Y10
AB8

W2
AA4
AA7
AA2
AA6

AA10

AA1
AB4

AC9

AB11

AC11

AB3

AC2
AD1
AD9
AC1
AD7
AC6

AB5

AD10

AD4
AC8

J13
K13

W1

U7A

F1

HD0#

J1

HD1#

H1

HD2#

J6

HD3#

H3

HD4#

K2

HD5#

G1

HD6#

G2

HD7#

K9

HD8#

K1

HD9#

K7

HD10#

J8

HD11#

H4

HD12#

J3

HD13#
HD14#

G4

HD15#
HD16#
HD17#

T3

HD18#

U7

HD19#

U9

HD20#
HD21#
HD22#
HD23#

T1

HD24#

T8

HD25#

T4

HD26#
HD27#

U5

HD28#

T9

HD29#
HD30#

T5

HD31#
HD32#
HD33#
HD34#
HD35#

Y3

HD36#

Y7

HD37#
HD38#
HD39#
HD40#
HD41#
HD42#
HD43#
HD44#
HD45#
HD46#

Y8

HD47#
HD48#
HD49#
HD50#
HD51#
HD52#
HD53#
HD54#
HD55#
HD56#
HD57#
HD58#
HD59#
HD60#
HD61#
HD62#
HD63#

HVREF0
HVREF1

E1

HXRCOMP

E2

HXSCOMP

Y1

HYRCOMP

U1

HYSCOMP

E4

HXSWING
HYSWING

CALISTOGA_FCBGA1466~D

<BOM Structure>

HADSTB#0
HADSTB#1

HOST

HDSTBN#0
HDSTBN#1
HDSTBN#2
HDSTBN#3
HDSTBP#0
HDSTBP#1
HDSTBP#2
HDSTBP#3

HCPURST#

HDPWR#

HDEFER#

HBREQ0#

HCPUSLP#

HA3#
HA4#
HA5#
HA6#
HA7#
HA8#

HA9#
HA10#
HA11#
HA12#
HA13#
HA14#
HA15#
HA16#
HA17#
HA18#
HA19#
HA20#
HA21#
HA22#
HA23#
HA24#
HA25#
HA26#
HA27#
HA28#
HA29#
HA30#
HA31#

HREQ#0
HREQ#1
HREQ#2
HREQ#3
HREQ#4

HCLKN
HCLKP

HDINV#0
HDINV#1
HDINV#2
HDINV#3

HADS#

HTRDY#
HDRDY#

HHITM#

HHIT#

HLOCK#

HBNR#

HBPRI#

HDBSY#

HRS0#
HRS1#
HRS2#

12

R61

12

R60

B

+VCCP+VCCP

R54

R58

H_A#[3..31] 6

H_REQ#[0..4] 6

H_ADSTB#0 6
H_ADSTB#1 6

CLK_MCH_BCLK# 17
CLK_MCH_BCLK 17
H_DSTBN#[0..3] 6

H_DSTBP # [0 ..3 ] 6

H_DINV#0 6
H_DINV#1 6
H_DINV#2 6
H_DINV#3 6

H_RESET# 6
H_ADS# 6
H_TRDY# 6
H_DPWR# 6
H_DRDY# 6
H_DEFER# 6
H_HITM# 6
H_HIT# 6
H_LOCK# 6
H_BR0# 6
H_BNR# 6
H_BPRI# 6
H_DBSY# 6
H_CPUSLP# 6,20

H_RS#[0..2] 6

12

221_0603_1%

12

100_0402_1%

H_SWNG1

1

2

0.1U_0402_16V4Z

C82

Security Classification

H_A#3

H9

H_A#4

C9

H_A#5

E11

H_A#6

G11

H_A#7

F11

H_A#8

G12

H_A#9

F9

H_A#10

H11

H_A#11

J12

H_A#12

G14

H_A#13

D9

H_A#14

J14

H_A#15

H13

H_A#16

J15

H_A#17

F14

H_A#18

D12

H_A#19

A11

H_A#20

C11

H_A#21

A12

H_A#22

A13

H_A#23

E13

H_A#24

G13

H_A#25

F12

H_A#26

B12

H_A#27

B14

H_A#28

C12

H_A#29

A14

H_A#30

C14

H_A#31

D14

H_REQ#0

D8

H_REQ#1

G8

H_REQ#2

B8

H_REQ#3

F8

H_REQ#4 DDR_CKE1_DIMMA

A8

H_ADSTB#0

B9

H_ADSTB#1

C13

CLK_MCH_BCLK#

AG1

CLK_MCH_BCLK

AG2

H_DSTBN#0

K4

H_DSTBN#1

T7

H_DSTBN#2

Y5

H_DSTBN#3

AC4

H_DSTBP#0

K3

H_DSTBP#1

T6

H_DSTBP#2

AA5

H_DSTBP#3

AC5

H_DINV#0

J7

H_DINV#1

W8

H_DINV#2

U3

H_DINV#3

AB10

H_RESET#

B7

H_ADS#

E8

H_TRDY#

E7

H_DPWR#

J9

H_DRDY#

H8

H_DEFER#

C3

H_HITM#

D4

H_HIT#

D3

H_LOCK#

B3

H_BR0#

C7

H_BNR#

C6

H_BPRI#

F6

H_DBSY#

A7

H_CPUSLP#

E3

H_RS#0

B4

H_RS#1

E6

H_RS#2

D6

221_0603_1%

H_SWNG0

1

C83

2

100_0402_1%

0.1U_0402_16V4Z

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITT EN CON SENT O F COMPAL ELECTRONICS, INC.

C

DDR_CKE0_DIMMA15
DDR_CKE1_DIMMA15
DDR_CKE2_DIMMB16
DDR_CKE3_DIMMB16

DDR_CS0_DIMMA#15
DDR_CS1_DIMMA#15
DDR_CS2_DIMMB#16
DDR_CS3_DIMMB#16

+1.8V

R279 80.6_0402_1%

1 2
1 2

R280 80.6_0402_1%

PLT_RST#19,21,25,27,32

V_DDR_MCH_REF15,16

Stuff R286 & R281 for A1 Calistoga

C

DMI_TXN021
DMI_TXN121
DMI_TXN221
DMI_TXN321

DMI_TXP021
DMI_TXP121
DMI_TXP221
DMI_TXP321

DMI_RXN021
DMI_RXN121
DMI_RXN221
DMI_RXN321

DMI_RXP021
DMI_RXP121
DMI_RXP221
DMI_RXP321

M_CLK_DDR015
M_CLK_DDR115
M_CLK_DDR216
M_CLK_DDR316

M_CLK_DDR#015
M_CLK_DDR#115
M_CLK_DDR#216
M_CLK_DDR#316

M_ODT015
M_ODT115
M_ODT216
M_ODT316

V_DDR_MCH_REF

PM_BMBUSY#21
PM_EXTTS#015
PM_EXTTS#116

H_THERMTRIP#6,20

NB_PWRGD19

R305 100_0402_1%

MCH_ICH_SYNC#19

Layout Note:
V_DDR_MCH_REF
trace width and
spacing is 20/20.

V_DDR_MCH_REF

1

C315

2

0.1U_0402_16V4Z

2005/09/10 2006/06/23

DMI_TXN0
DMI_TXN1
DMI_TXN2
DMI_TXN3

DMI_TXP0
DMI_TXP1
DMI_TXP2
DMI_TXP3

DMI_RXN0
DMI_RXN1
DMI_RXN2
DMI_RXN3

DMI_RXP0
DMI_RXP1
DMI_RXP2
DMI_RXP3

M_CLK_DDR1
M_CLK_DDR2
M_CLK_DDR3

M_CLK_DDR#0
M_CLK_DDR#1
M_CLK_DDR#2

M_CLK_DDR#3
DDR_CKE0_DIMMA
DDR_CKE2_DIMMB

DDR_CKE3_DIMMB
DDR_CS0_DIMMA#

DDR_CS1_DIMMA#
DDR_CS2_DIMMB#
DDR_CS3_DIMMB#

M_OCDOCMP0

M_OCDOCMP1

M_ODT0

M_ODT1

M_ODT2

M_ODT3

SMRCOMPN

SMRCOMPP

PM_BMBUSY#
PM_EXTTS#0
PM_EXTTS#1
H_THERMTRIP#
NB_PWRGD
PLTRST_R#

12

+1.8V

12

R277
100_0402_1%

12

R278
100_0402_1%

Compal Secret Data

Deciphered Date

U7B

AE35

DMIRXN0

AF39

DMIRXN1

AG35

DMIRXN2

AH39

DMIRXN3

AC35

DMIRXP0

AE39

DMIRXP1

AF35

DMIRXP2

AG39

DMIRXP3

AE37

DMITXN0

AF41

DMITXN1

AG37

DMITXN2

AH41

DMITXN3

AC37

DMITXP0

AE41

DMITXP1

AF37

DMITXP2

AG41

DMITXP3

AY35

SM_CK0

AR1

SM_CK1

AW7

SM_CK2

AW40

SM_CK3

AW35

SM_CK0#

AT1

SM_CK1#

AY7

SM_CK2#

AY40

SM_CK3#

AU20

SM_CKE0

AT20

SM_CKE1

BA29

SM_CKE2

AY29

SM_CKE3

AW13

SM_CS0#

AW12

SM_CS1#

AY21

SM_CS2#

AW21

SM_CS3#

AL20

SM_OCDCOMP0

AF10

SM_OCDCOMP1

BA13

SM_ODT0

BA12

SM_ODT1

AY20

SM_ODT2

AU21

SM_ODT3

AV9

SM_RCOMPN

AT9

SM_RCOMPP

AK1

SM_VREF0

AK41

SM_VREF1

G28

PM_BMBUSY#

F25

PM_EXTTS0#

H26

PM_EXTTS1#

G6

PM_THERMTRIP#

AH33

PWROK

AH34

RSTIN#

K28

ICH_SYNC#

CALISTOGA_FCBGA1466~D

<BOM Structure>

D

DMI

DDR MUXING

PM

Layout Note:
Route as short
as possible

12

R281

R286

40.2_0402_1%

40.2_0402_1%

@

@

D

E

Description at page13.

MCH_CLKSEL0

K16

CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8

CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG16

CFG

CFG17
CFG18
CFG19
CFG20

G_CLKP

G_CLKN

D_REF_CLKN

D_REF_CLKP

CLKNC

D_REF_SSCLKN
D_REF_SSCLKP

CLK_REQ#

NC0
NC1
NC2
NC3
NC4
NC5
NC6
NC7
NC8

NC9
NC10
NC11
NC12
NC13
NC14
NC15
NC16
NC17
NC18

RESERVED1
RESERVED2
RESERVED3
RESERVED4
RESERVED5
RESERVED6
RESERVED7
RESERVED8

RESERVED9
RESERVED10
RESERVED11
RESERVED12
RESERVED13

RESERVED

M_OCDOCMP0
M_OCDOCMP1

12

0_0402_5%

1 2

Title

Size Document Number Rev

Custom

Date: Sheet

MCH_CLKSEL1

K18

MCH_CLKSEL2

J18
F18
E15

CFG5

F15

CFG6

E18

CFG7

D19

CFG8

D16

CFG9

G16

CFG10

E16

CFG11

D15

CFG12

G15

CFG13

K15

CFG14

C15

CFG15

H16

CFG16

G18

CFG17

H15

CFG18

J25

CFG19

K27

CFG20

J26

CLK_MCH_3GPLL

AG33

CLK_MCH_3GPLL#M_CLK_DDR0

AF33

CLK_MCH_DREFCLK#

A27

CLK_MCH_DREFCLK

A26

MCH_SSCDREFCLK#

C40

MCH_SSCDREFCLK

D41

CLKREQA#

H32

A3
A39
A4
A40
AW1
AW41
AY1
BA1
BA2
BA3
BA39
BA40
BA41
C1
AY41
B2
B41
C41
D1

T32
R32
F3
F7
AG11
AF11
H7
J19
A41
A34
D28
D27
A35

PM_EXTTS#0

PM_EXTTS#1

R526

DPRSLPVR 21,42

Compal Electronics, Inc.

SCHEMATIC, M/B LA-3051P

, 06, 2005

四十月

401397

星期

PAD
PAD
PAD
PAD

PAD
PAD

R95

10K_0402_5%

R94

10K_0402_5%

MCH_CLKSEL0 17
MCH_CLKSEL1 17
MCH_CLKSEL2 17
CFG3 13

T17

CFG5 13

T24

CFG7 13

T22

CFG9 13

T19

CFG11 13
CFG12 13

CFG13 13

T18
T21

CFG16 13

CFG17 13

CFG18 13

CFG19 13

CFG20 13

12

12

E

CLK_MCH_3GPLL 17
CLK_MCH_3GPLL# 17

CLK_MCH_DREFCLK# 17
CLK_MCH_DREFCLK 17

MCH_SSCDREFCLK# 17
MCH_SSCDREFCLK 17

CLKREQA# 17

+3VS

of

945

A

A

1 1

B

C

D

E

DDR_A_BS#015
DDR_A_BS#115
DDR_A_BS#215

DDR_A_DM[0..7]15

DDR_A_DQS[0..7]15

2 2

DDR_A_DQS#[0..7]15

DDR_A_MA[0..13]15

3 3

DDR_A_CAS#15
DDR_A_RAS#15

DDR_A_WE#15

T25 PAD
T26 PAD

DDR_A_BS#0
DDR_A_BS#1
DDR_A_BS#2

DDR_A_DM0
DDR_A_DM1
DDR_A_DM2
DDR_A_DM3
DDR_A_DM4
DDR_A_DM5
DDR_A_DM6
DDR_A_DM7

DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7

DDR_A_DQS#0
DDR_A_DQS#1
DDR_A_DQS#2
DDR_A_DQS#3
DDR_A_DQS#4
DDR_A_DQS#5
DDR_A_DQS#6
DDR_A_DQS#7

DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13

DDR_A_CAS#
DDR_A_RAS#
DDR_A_WE#
SA_RCVENIN# SB_RCVENIN#
SA_RCVENOUT#

check layout check layout

U7D

AU12

SA_BS0

AV14

SA_BS1

BA20

SA_BS2

AJ33

SA_DM0

AM35

SA_DM1

AL26

SA_DM2

AN22

SA_DM3

AM14

SA_DM4

AL9

SA_DM5

AR3

SA_DM6

AH4

SA_DM7

AK33

SA_DQS0

AT33

SA_DQS1

AN28

SA_DQS2

AM22

SA_DQS3

AN12

SA_DQS4

AN8

SA_DQS5

AP3

SA_DQS6

AG5

SA_DQS7

AK32

SA_DQS0#

AU33

SA_DQS1#

AN27

SA_DQS2#

AM21

SA_DQS3#

AM12

SA_DQS4#

AL8

SA_DQS5#

AN3

SA_DQS6#

AH5

SA_DQS7#

AY16

SA_MA0

AU14

SA_MA1

AW16

SA_MA2

BA16

SA_MA3

BA17

SA_MA4

AU16

SA_MA5

AV17

SA_MA6

AU17

SA_MA7

AW17

SA_MA8

AT16

SA_MA9

AU13

SA_MA10

AT17

SA_MA11

AV20

SA_MA12

AV12

SA_MA13

AY13

SA_CAS#

AW14

SA_RAS#

AY14

SA_WE#

AK23

SA_RCVENIN#

AK24

SA_RCVENOUT#

CALISTOGA_FCBGA1466~D

<BOM Stru cture>

SA_DQ0
SA_DQ1
SA_DQ2
SA_DQ3
SA_DQ4
SA_DQ5
SA_DQ6
SA_DQ7
SA_DQ8

SA_DQ9
SA_DQ10
SA_DQ11
SA_DQ12
SA_DQ13
SA_DQ14
SA_DQ15
SA_DQ16
SA_DQ17
SA_DQ18
SA_DQ19
SA_DQ20
SA_DQ21
SA_DQ22
SA_DQ23
SA_DQ24
SA_DQ25
SA_DQ26
SA_DQ27
SA_DQ28
SA_DQ29
SA_DQ30
SA_DQ31
SA_DQ32
SA_DQ33
SA_DQ34
SA_DQ35
SA_DQ36
SA_DQ37
SA_DQ38
SA_DQ39

DDR SYS MEMORY A

SA_DQ40
SA_DQ41
SA_DQ42
SA_DQ43
SA_DQ44
SA_DQ45
SA_DQ46
SA_DQ47
SA_DQ48
SA_DQ49
SA_DQ50
SA_DQ51
SA_DQ52
SA_DQ53
SA_DQ54
SA_DQ55
SA_DQ56
SA_DQ57
SA_DQ58
SA_DQ59
SA_DQ60
SA_DQ61
SA_DQ62
SA_DQ63

AJ34
AM31
AM33
AJ36
AK35
AJ32
AH31
AN35
AP33
AR31
AP31
AN38
AM36
AM34
AN33
AK26
AL27
AM26
AN24
AK28
AL28
AM24
AP26
AP23
AL22
AP21
AN20
AL23
AP24
AP20
AT21
AR12
AR14
AP13
AP12
AT13
AT12
AL14
AL12
AK9
AN7
AK8
AK7
AP9
AN9
AT5
AL5
AY2
AW2
AP1
AN2
AV2
AT3
AN1
AL2
AG7
AF9
AG4
AF6
AG9
AH6
AF4
AF8

DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63

DDR_A_D0

AJ35

DDR_A_D[0..63] 15 DDR_B_D[0..63] 16

DDR_B_BS#016
DDR_B_BS#116
DDR_B_BS#216

DDR_B_DM[0..7]16

DDR_B_DQS[0..7]16

DDR_B_DQS#[0..7]16

DDR_B_MA[0..13]16

DDR_B_CAS#16
DDR_B_RAS#16

DDR_B_WE#16

T20 PAD
T23 PAD

DDR_B_BS#0
DDR_B_BS#1
DDR_B_BS#2

DDR_B_DM0
DDR_B_DM1
DDR_B_DM2
DDR_B_DM3
DDR_B_DM4
DDR_B_DM5
DDR_B_DM6
DDR_B_DM7

DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4
DDR_B_DQS5
DDR_B_DQS6
DDR_B_DQS7

DDR_B_DQS#0
DDR_B_DQS#1
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS#4
DDR_B_DQS#5
DDR_B_DQS#6
DDR_B_DQS#7

DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13

DDR_B_CAS#
DDR_B_RAS#
DDR_B_WE#

SB_RCVENOUT#

U7E

AT24

SB_BS0

AV23

SB_BS1

AY28

SB_BS2

AK36

SB_DM0

AR38

SB_DM1

AT36

SB_DM2

BA31

SB_DM3

AL17

SB_DM4

AH8

SB_DM5

BA5

SB_DM6

AN4

SB_DM7

AM39

SB_DQS0

AT39

SB_DQS1

AU35

SB_DQS2

AR29

SB_DQS3

AR16

SB_DQS4

AR10

SB_DQS5

AR7

SB_DQS6

AN5

SB_DQS7

AM40

SB_DQS0#

AU39

SB_DQS1#

AT35

SB_DQS2#

AP29

SB_DQS3#

AP16

SB_DQS4#

AT10

SB_DQS5#

AT7

SB_DQS6#

AP5

SB_DQS7#

AY23

SB_MA0

AW24

SB_MA1

AY24

SB_MA2

AR28

SB_MA3

AT27

SB_MA4

AT28

SB_MA5

AU27

SB_MA6

AV28

SB_MA7

AV27

SB_MA8

AW27

SB_MA9

AV24

SB_MA10

BA27

SB_MA11

AY27

SB_MA12

AR23

SB_MA13

AR24

SB_CAS#

AU23

SB_RAS#

AR27

SB_WE#

AK16

SB_RCVENIN#

AK18

SB_RCVENOUT#

CALISTOGA_FCBGA1466~D

<BOM Stru cture>

SB_DQ0
SB_DQ1
SB_DQ2
SB_DQ3
SB_DQ4
SB_DQ5
SB_DQ6
SB_DQ7
SB_DQ8

SB_DQ9
SB_DQ10
SB_DQ11
SB_DQ12
SB_DQ13
SB_DQ14
SB_DQ15
SB_DQ16
SB_DQ17
SB_DQ18
SB_DQ19
SB_DQ20
SB_DQ21
SB_DQ22
SB_DQ23
SB_DQ24
SB_DQ25
SB_DQ26
SB_DQ27
SB_DQ28
SB_DQ29
SB_DQ30
SB_DQ31
SB_DQ32
SB_DQ33
SB_DQ34
SB_DQ35
SB_DQ36
SB_DQ37
SB_DQ38
SB_DQ39

DDR SYS MEMORY B

SB_DQ40
SB_DQ41
SB_DQ42
SB_DQ43
SB_DQ44
SB_DQ45
SB_DQ46
SB_DQ47
SB_DQ48
SB_DQ49
SB_DQ50
SB_DQ51
SB_DQ52
SB_DQ53
SB_DQ54
SB_DQ55
SB_DQ56
SB_DQ57
SB_DQ58
SB_DQ59
SB_DQ60
SB_DQ61
SB_DQ62
SB_DQ63

AJ37
AP39
AR41
AJ38
AK38
AN41
AP41
AT40
AV41
AU38
AV38
AP38
AR40
AW38
AY38
BA38
AV36
AR36
AP36
BA36
AU36
AP35
AP34
AY33
BA33
AT31
AU29
AU31
AW31
AV29
AW29
AM19
AL19
AP14
AN14
AN17
AM16
AP15
AL15
AJ11
AH10
AJ9
AN10
AK13
AH11
AK10
AJ8
BA10
AW10
BA4
AW4
AY10
AY9
AW5
AY5
AV4
AR5
AK4
AK3
AT4
AK5
AJ5
AJ3

DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63

DDR_B_D0

AK39

DDR Thermal Sensor

4 4

EC_SMB_DA26,23,32,37
EC_SMB_CK26,23,32,37

A

SMB_EC_DA2
SMB_EC_CK2

U11

1

SDA

2

SCL

3

OS#

4

GND

LM75CIMMX-5_MSOP8@

VCC

+5VS

1

C305

0.1U_0402_16V4Z@

2

8
7

A0

6

A1

5

A2

1 2

R269 1K_0402_5%@

B

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2005/09/10 2006/06/23

Compal Secret Data

Deciphered Date

D

Title

Size Document Number Re v

Custom

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, M/B LA-3051P

星期四 十

06, 2005

月

401397

E

10 45,

of

A

5

4

3

2

1

D D

U7C

H27

SDVOCTRL_DATA

H28

SDVOCTRL_CLK

R63

1 2

1 2

150_0402_1%

150_0402_1%

R301 1.5K_0402_1%

TV_COMPS
TV_LUMA
TV_CRMA

LVDSA0+
LVDSA1+
LVDSA2+

LVDSA0­LVDSA1­LVDSA2-

LVDSB0+
LVDSB1+
LVDSB2+

LVDSB0­LVDSB1­LVDSB2-

LVDSAC+
LVDSAC­LVDSBC+
LVDSBC-

GMCH_ENBKL

LCTLA_CLK

LCTLB_DATA
EDID_CLK_LCD
EDID_DAT_LCD

GMCH_LVDDEN

R287

4.99K_0402_1%

3VDDCCL

3VDDCDA

CRT_VSYNC

CRT_HSYNC

CRT_B

CRT_G

CRT_R

R288

255_0402_1%

LVDSA0+18
LVDSA1+18

LVDSA2+18

LVDSA0-18
LVDSA1-18

LVDSA2-18

LVDSB0+18
LVDSB1+18
LVDSB2+18

LVDSB0-18
LVDSB1-18
LVDSB2-18

LVDSAC+18

LVDSAC-18
LVDSBC+18
LVDSBC-18

BIA_PWM18

R66

1 2

R70

GMCH_ENBKL18

EDID_CLK_LCD18
EDID_DAT_LCD18

GMCH_LVDDEN18

150_0402_1%

1 2

150_0402_1%

R62

1 2

150_0402_1%

3VDDCCL18

3VDDCDA18

CRT_VSYNC18
CRT_HSYNC18

R73

R75

1 2

150_0402_1%

C C

B B

+3VS

@

1 2

R295 10K_0402_5%

@

1 2

R291 10K_0402_5%

GMCH_ENBKL

R32 100K_0402_1%

GMCH_LVDDEN

R33 100K_0402_5%

LCTLA_CLK

LCTLB_DATA

1 2

1 2

TV_COMPS18
TV_LUMA18
TV_CRMA18

CRT_B18
CRT_G18
CRT_R18

BIA_PWM

12

B37
B34
A36

C37
B35
A37

F30
D29
F28

G30
D30
F29

A32
A33
E26
E27

D32

J30
H30
H29
G26
G25
F32
B38
C35
C33
C32

A16
C18
A19

J20

12

B16
B18
B19

J29
K30

C26
C25

H23
G23
E23
D23
C22
B22
A21
B21

J22

12

LA_DATA0
LA_DATA1
LA_DATA2

LA_DATA#0
LA_DATA#1
LA_DATA#2

LB_DATA0
LB_DATA1
LB_DATA2

LB_DATA#0
LB_DATA#1
LB_DATA#2

LA_CLK
LA_CLK#
LB_CLK
LB_CLK#

LBKLT_CTL
LBKLT_EN
LCTLA_CLK
LCTLB_DATA
LDDC_CLK
LDDC_DATA
LVDD_EN
LIBG
LVBG
LVREFH
LVREFL

TVDAC_A
TVDAC_B
TVDAC_C

TV_IREF
TV_IRTNA

TV_IRTNB
TV_IRTNC

TV_DCONSEL1
TV_DCONSEL0

DDCCLK
DDCDATA

VSYNC
HSYNC
BLUE
BLUE#
GREEN
GREEN#
RED
RED#

CRT_IREF

CALISTOGA_FCBGA1466~D

<BOM Stru cture>

LVDS

TV CRT

EXP_COMPI

EXP_COMPO

EXP_RXN0
EXP_RXN1
EXP_RXN2
EXP_RXN3
EXP_RXN4
EXP_RXN5
EXP_RXN6
EXP_RXN7
EXP_RXN8

EXP_RXN9
EXP_RXN10
EXP_RXN11
EXP_RXN12
EXP_RXN13
EXP_RXN14
EXP_RXN15

EXP_RXP0

EXP_RXP1

EXP_RXP2

EXP_RXP3

EXP_RXP4

EXP_RXP5

EXP_RXP6

EXP_RXP7

EXP_RXP8

EXP_RXP9
EXP_RXP10
EXP_RXP11
EXP_RXP12
EXP_RXP13
EXP_RXP14
EXP_RXP15

EXP_TXN0

EXP_TXN1

EXP_TXN2

EXP_TXN3

EXP_TXN4

EXP_TXN5

EXP_TXN6

EXP_TXN7

EXP_TXN8

PCI-EXPRESS GRAPHICS

EXP_TXN9

EXP_TXN10
EXP_TXN11
EXP_TXN12
EXP_TXN13
EXP_TXN14
EXP_TXN15

EXP_TXP0
EXP_TXP1
EXP_TXP2
EXP_TXP3
EXP_TXP4
EXP_TXP5
EXP_TXP6
EXP_TXP7
EXP_TXP8

EXP_TXP9
EXP_TXP10
EXP_TXP11
EXP_TXP12
EXP_TXP13
EXP_TXP14
EXP_TXP15

D40
D38

F34
G38
H34
J38
L34
M38
N34
P38
R34
T38
V34
W38
Y34
AA38
AB34
AC38

D34
F38
G34
H38
J34
L38
M34
N38
P34
R38
T34
V38
W34
Y38
AA34
AB38

F36
G40
H36
J40
L36
M40
N36
P40
R36
T40
V36
W40
Y36
AA40
AB36
AC40

D36
F40
G36
H40
J36
L40
M36
N40
P36
R40
T36
V40
W36
Y40
AA36
AB40

PEGCOMP

R302

24.9_0402_1%

1 2

+1.5VS_PCIE

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/09/10 2006/06/23

Compal Secret Data

Deciphered Date

Title

Size Document Number Re v

Custom

2

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, M/B LA-3051P

星期四 十

06, 2005

月

401397

1

11 45,

A

of

A

+VCCP

21

D9

CH751H-40_SC76@

1 1

CH751H-40_SC76@

2 2

3 3

4 4

12

+2.5VS

R90

10_0402_5%@

+1.5VS

21

D10

12

+3VS

R93

10_0402_5%@

C77

4.7U_0805_10V4Z

C74

0.22U_0603_10V7K

C75

1

C80

2

2.2U_0805_16V4Z

1

2

1

C318

2

1

+

220U_D2_4VM

2

1

2

MCH_A6

1

C84

2

MCH_D2

0.22U_0603_10V7K

C320

+1.5VS

+VCCP

0.47U_0603_10V7K

MCH_AB1

1

2

0.47U_0603_10V7K

U7H

AC14

VTT0

AB14

VTT1

W14

VTT2

V14

VTT3

T14

VTT4

R14

VTT5

P14

VTT6

N14

VTT7

M14

VTT8

L14

VTT9

AD13

VTT10

AC13

VTT11

AB13

VTT12

AA13

VTT13

Y13

VTT14

W13

VTT15

V13

VTT16

U13

VTT17

T13

VTT18

R13

VTT19

N13

VTT20

M13

VTT21

L13

VTT22

AB12

VTT23

AA12

VTT24

Y12

VTT25

W12

VTT26

V12

VTT27

U12

VTT28

T12

VTT29

R12

VTT30

P12

VTT31

N12

VTT32

M12

VTT33

L12

VTT34

R11

VTT35

P11

VTT36

N11

VTT37

M11

VTT38

R10

VTT39

P10

VTT40

N10

VTT41

M10

VTT42

P9

VTT43

N9

VTT44

M9

VTT45

R8

VTT46

P8

VTT47

N8

VTT48

M8

VTT49

P7

VTT50

N7

VTT51

M7

VTT52

R6

VTT53

P6

VTT54

M6

VTT55

A6

VTT56

R5

VTT57

P5

VTT58

N5

VTT59

M5

VTT60

P4

VTT61

N4

VTT62

M4

VTT63

R3

VTT64

P3

VTT65

N3

VTT66

M3

VTT67

R2

VTT68

P2

VTT69

M2

VTT70

D2

VTT71

AB1

VTT72

R1

VTT73

P1

VTT74

N1

VTT75

M1

VTT76

AG14

VCCAUX32

AF14

VCCAUX33

AE14

VCCAUX34

Y14

VCCAUX35

AF13

VCCAUX36

AE13

VCCAUX37

AF12

VCCAUX38

AE12

VCCAUX39

AD12

VCCAUX40

CALISTOGA_FCBGA1466~D

<BOM Structure>

P O W E R

B

VCC_SYNC

VCCTX_LVDS0
VCCTX_LVDS1
VCCTX_LVDS2

VCC3G0
VCC3G1
VCC3G2
VCC3G3
VCC3G4
VCC3G5
VCC3G6

VCCA_3GPLL

VCCA_3GBG
VSSA_3GBG

VCCA_CRTDAC0
VCCA_CRTDAC1
VSSA_CRTDAC2

VCCA_DPLLA
VCCA_DPLLB

VCCA_HPLL

VCCA_LVDS

VSSA_LVDS

VCCA_MPLL
VCCA_TVBG

VSSA_TVBG

VCCA_TVDACA0
VCCA_TVDACA1
VCCA_TVDACB0
VCCA_TVDACB1
VCCA_TVDACC0
VCCA_TVDACC1

VCCD_HMPLL0
VCCD_HMPLL1

VCCD_LVDS0
VCCD_LVDS1
VCCD_LVDS2

VCCD_TVDAC

VCCDQ_TVDAC

VCCHV0
VCCHV1
VCCHV2

VCCAUX0
VCCAUX1
VCCAUX2
VCCAUX3
VCCAUX4
VCCAUX5
VCCAUX6
VCCAUX7
VCCAUX8

VCCAUX9
VCCAUX10
VCCAUX11
VCCAUX12
VCCAUX13
VCCAUX14
VCCAUX15
VCCAUX16
VCCAUX17
VCCAUX18
VCCAUX19
VCCAUX20
VCCAUX21
VCCAUX22
VCCAUX23
VCCAUX24
VCCAUX25
VCCAUX26
VCCAUX27
VCCAUX28
VCCAUX29
VCCAUX30
VCCAUX31

H22

B30
C30
A30

AB41
AJ41
L41
N41
R41
V41
Y41

AC33
G41
H41

E21
F21
G21

B26
C39
AF1

A38
B39

AF2
H20

G20

E19
F19
C20
D20
E20
F20

AH1
AH2

A28
B28
C28

D21
H19

A23
B23
B25

AK31
AF31
AE31
AC31
AL30
AK30
AJ30
AH30
AG30
AF30
AE30
AD30
AC30
AG29
AF29
AE29
AD29
AC29
AG28
AF28
AE28
AH22
AJ21
AH21
AJ20
AH20
AH19
P19
P16
AH15
P15
AH14

+2.5VS

1 2

C356

0.1U_0402_16V4Z

+2.5VS

W=40 mils

+1.5VS_3GPLL
+2.5VS

+2.5VS_CRTDAC

+1.5VS_DPLLA
+1.5VS_DPLLB
+1.5VS_HPLL

+2.5VS

+1.5VS_MPLL
+3VS_TVBG

VSSA_TVBG

+3VS_TVDACA
+3VS_TVDACB
+3VS_TVDACC

+1.5VS

+1.5VS_TVDAC
+1.5VS_QTVDAC

1

2

C358

0.1U_0402_16V4Z

+1.5VS

1

C351

2

C378

C352

0.1U_0402_16V4Z

10U_0805_6.3V6M

1

+

2

1

2

+1.5VS_PCIE

1

C129

2

220U_D2_4VM

1

C347

2

0.022U_0402_16V7K~N

1

2

C345

0.022U_0402_16V7K~N

+3VS

C

R91

0_0805_5%

1

C128

2

10U_0805_6.3V6M

L12 BLM11A601S_0603

1 2

1

2

1

C96

2

1

C118

2

10U_0805_4VAM

10U_0805_6.3V6M

CRTDAC: Route caps within

C114

250mil of Alviso. Route FB

0.1U_0402_16V4Z

within 3" of Calistoga

R76

12

0_0805_5%

0.1U_0402_16V4Z

+1.5VS

1

C309

2

0.01U_0402_16V7K

12

+2.5VS

+3VS+3VS_TVBG

+2.5VS

1

C366

2

+1.5VS

4.7U_0603_6.3V6M

close pin B30/C30/A30

+2.5VS

1

C374

2

0.1U_0402_16V4Z

close pin G41

+2.5VS

1

1

C372

C371

2

2

0.1U_0402_16V4Z

0.01U_0402_16V7K

close pin A38

D

+1.5VS_DPLLA +1.5VS_DPLLB

470U_D2_2.5VM

0.1U_0402_16V4Z

1

C367

2

0.1U_0402_16V4Z

C363

1

2

1

C339

2

1

C102

2

L13

CHB1608U301_0603

1

C121

+

2

R285

0_0805_5%

1

C344

2

0.1U_0402_16V4Z

0.022U_0402_16V7K~N

R78

0_0805_5%

1

C101

2

0.1U_0402_16V4Z

0.022U_0402_16V7K~N

12

PCI-E/MEM/PSB PLL decoupling

R92
0_0603_5%

12

C127

1

2

10U_1206_6.3V6M

R274
0_0603_5%

22U_0805_6.3V6M

12

1

1

C368

2

2

0.1U_0402_16V4Z

+1.5VS_MPLL

45mA Max. 45mA Max.

1

C313

C319

2

0.1U_0402_16V4Z

E

L14

CHB1608U301_0603

470U_D2_2.5VM

0.1U_0402_16V4Z

1

C373

1

+

2

2

12

+3VS+3VS_TVDACC

12

+1.5VS+1.5VS_3GPLL

1

C131

2

0.1U_0402_16V4Z

1

1

C340

2

2

0.022U_0402_16V7K~N

+1.5VS_TVDAC +1.5VS

1

C109

2

0.022U_0402_16V7K~N

+1.5VS_QTVDAC +1.5VS

1

C338

2

0.1U_0402_16V4Z

1

2

+1.5VS_HPLL

1

C317

2

R79
0_0603_5%

C105

0.022U_0402_16V7K~N

0.1U_0402_16V4Z

C132

C93

C79

0_0805_5%

0.1U_0402_16V4Z

1

2

0.1U_0402_16V4Z

R53
0_0603_5%

1

2

22U_0805_6.3V6M

12

R71

0_0603_5%
R80

C348

12

C107

0.1U_0402_16V4Z

+1.5VS+1.5VS

+3VS+3VS_TVDACA+3VS+3VS_TVDACB

12

12

1

2

12

+1.5VS+1.5VS

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITT EN CON SENT O F COMPAL ELECTRONICS, INC.

2005/09/10 2006/06/23

C

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

D

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, M/B LA-3051P

401397

星期

, 06, 2005

四十月

12 45

E

A

of

5

4

3

2

1

Strap Pin Table

+VCCP

D D

1

1

C364

2

0.22U_0603_10V7K

1

C328

2

10U_1206_6.3V6M

C C

B B

C350

C369

C306

C314

1

C353

2

2

0.22U_0603_10V7K

10U_1206_6.3V6M

220U_D2_4VM

220U_D2_4VM@

0.22U_0603_10V7K

1

1

C336

2

2

1U_0603_10V4Z

1

+

2

1

+

2

+VCCP

U7F

AD27

VCC_NCTF0

AC27

VCC_NCTF1

AB27

VCC_NCTF2

AA27

VCC_NCTF3

Y27

VCC_NCTF4

W27

VCC_NCTF5

V27

VCC_NCTF6

U27

VCC_NCTF7

T27

VCC_NCTF8

R27

VCC_NCTF9

AD26

VCC_NCTF10

AC26

VCC_NCTF11

AB26

VCC_NCTF12

AA26

VCC_NCTF13

Y26

VCC_NCTF14

W26

VCC_NCTF15

V26

VCC_NCTF16

U26

VCC_NCTF17

T26

VCC_NCTF18

R26

VCC_NCTF19

AD25

VCC_NCTF20

AC25

VCC_NCTF21

AB25

VCC_NCTF22

AA25

VCC_NCTF23

Y25

VCC_NCTF24

W25

VCC_NCTF25

V25

VCC_NCTF26

U25

VCC_NCTF27

T25

VCC_NCTF28

R25

VCC_NCTF29

AD24

VCC_NCTF30

AC24

VCC_NCTF31

AB24

VCC_NCTF32

AA24

VCC_NCTF33

Y24

VCC_NCTF34

W24

VCC_NCTF35

V24

VCC_NCTF36

U24

VCC_NCTF37

T24

VCC_NCTF38

R24

VCC_NCTF39

AD23

VCC_NCTF40

V23

VCC_NCTF41

U23

VCC_NCTF42

T23

VCC_NCTF43

R23

VCC_NCTF44

AD22

VCC_NCTF45

V22

VCC_NCTF46

U22

VCC_NCTF47

T22

VCC_NCTF48

R22

VCC_NCTF49

AD21

VCC_NCTF50

V21

VCC_NCTF51

U21

VCC_NCTF52

T21

VCC_NCTF53

R21

VCC_NCTF54

AD20

VCC_NCTF55

V20

VCC_NCTF56

U20

VCC_NCTF57

T20

VCC_NCTF58

R20

VCC_NCTF59

AD19

VCC_NCTF60

V19

VCC_NCTF61

U19

VCC_NCTF62

T19

VCC_NCTF63

AD18

VCC_NCTF64

AC18

VCC_NCTF65

AB18

VCC_NCTF66

AA18

VCC_NCTF67

Y18

VCC_NCTF68

W18

VCC_NCTF69

V18

VCC_NCTF70

U18

VCC_NCTF71

T18

VCC_NCTF72

M19

VCC100

L19

VCC101

N18

VCC102

M18

VCC103

L18

VCC104

P17

VCC105

N17

VCC106

M17

VCC107

N16

VCC108

M16

VCC109

L16

VCC110

CALISTOGA_FCBGA1466~D

<BOM Structure>

VCCAUX_NCTF0
VCCAUX_NCTF1
VCCAUX_NCTF2
VCCAUX_NCTF3
VCCAUX_NCTF4
VCCAUX_NCTF5
VCCAUX_NCTF6
VCCAUX_NCTF7
VCCAUX_NCTF8

VCCAUX_NCTF9
VCCAUX_NCTF10
VCCAUX_NCTF11
VCCAUX_NCTF12
VCCAUX_NCTF13
VCCAUX_NCTF14
VCCAUX_NCTF15
VCCAUX_NCTF16
VCCAUX_NCTF17
VCCAUX_NCTF18
VCCAUX_NCTF19
VCCAUX_NCTF20
VCCAUX_NCTF21
VCCAUX_NCTF22
VCCAUX_NCTF23
VCCAUX_NCTF24
VCCAUX_NCTF25
VCCAUX_NCTF26
VCCAUX_NCTF27
VCCAUX_NCTF28
VCCAUX_NCTF29
VCCAUX_NCTF30
VCCAUX_NCTF31
VCCAUX_NCTF32
VCCAUX_NCTF33
VCCAUX_NCTF34
VCCAUX_NCTF35
VCCAUX_NCTF36

P O W E R

VCCAUX_NCTF37
VCCAUX_NCTF38
VCCAUX_NCTF39
VCCAUX_NCTF40
VCCAUX_NCTF41
VCCAUX_NCTF42
VCCAUX_NCTF43
VCCAUX_NCTF44
VCCAUX_NCTF45
VCCAUX_NCTF46
VCCAUX_NCTF47
VCCAUX_NCTF48
VCCAUX_NCTF49
VCCAUX_NCTF50
VCCAUX_NCTF51
VCCAUX_NCTF52
VCCAUX_NCTF53
VCCAUX_NCTF54
VCCAUX_NCTF55
VCCAUX_NCTF56
VCCAUX_NCTF57

VSS_NCTF0
VSS_NCTF1
VSS_NCTF2
VSS_NCTF3
VSS_NCTF4
VSS_NCTF5
VSS_NCTF6
VSS_NCTF7
VSS_NCTF8

VSS_NCTF9
VSS_NCTF10
VSS_NCTF11
VSS_NCTF12

VCC_SM100
VCC_SM101
VCC_SM102
VCC_SM103
VCC_SM104
VCC_SM105
VCC_SM106
VCC_SM107

AG27
AF27
AG26
AF26
AG25
AF25
AG24
AF24
AG23
AF23
AG22
AF22
AG21
AF21
AG20
AF20
AG19
AF19
R19
AG18
AF18
R18
AG17
AF17
AE17
AD17
AB17
AA17
W17
V17
T17
R17
AG16
AF16
AE16
AD16
AC16
AB16
AA16
Y16
W16
V16
U16
T16
R16
AG15
AF15
AE15
AD15
AC15
AB15
AA15
Y15
W15
V15
U15
T15
R15

AE27
AE26
AE25
AE24
AE23
AE22
AE21
AE20
AE19
AE18
AC17
Y17
U17

AR6
AP6
AN6
AL6
AK6
AJ6
AV1
AJ1

+1.5VS

C316

+1.8V

0.47U_0603_10V7K

1

1

C81

2

2

0.47U_0603_10V7K

Place near pin AV1 & AJ1

A A

+VCCP

AA33

W33

N33

AA32

W32

N32
M32

AA31

W31

R31
N31

M31

AA30

W30

U30
R30
N30

M30

AA29

W29

U29
R29

M29

AB28
AA28

U28
R28
N28

M28

N27
M27

N26
N25

M25

N24

M24
AB23
AA23

N23

M23
AC22

AB22

W22

N22

M22
AC21

AA21

W21

N21

M21
AC20

AB20

W20

N20

M20
AB19

AA19

N19

P33
L33

J33
Y32
V32

P32

L32
J32

V31
T31

P31

Y30
V30
T30
P30

L30
Y29
V29

P29
L29

Y28
V28

T28
P28

L28
P27

L27
P26

L26

L25
P24

Y23
P23

L23

Y22
P22

L22

L21

Y20
P20

L20

Y19

U7G

VCC0
VCC1
VCC2
VCC3
VCC4
VCC5
VCC6
VCC7
VCC8
VCC9
VCC10
VCC11
VCC12
VCC13
VCC14
VCC15
VCC16
VCC17
VCC18
VCC19
VCC20
VCC21
VCC22
VCC23
VCC24
VCC25
VCC26
VCC27
VCC28
VCC29
VCC30
VCC31
VCC32

P O W E R

VCC33
VCC34
VCC35
VCC36
VCC37
VCC38
VCC39
VCC40
VCC41
VCC42
VCC43
VCC44
VCC45
VCC46
VCC47
VCC48
VCC49
VCC50
VCC51
VCC52
VCC53
VCC54
VCC55
VCC56
VCC57
VCC58
VCC59
VCC60
VCC61
VCC62
VCC63
VCC64
VCC65
VCC66
VCC67
VCC68
VCC69
VCC70
VCC71
VCC72
VCC73
VCC74
VCC75
VCC76
VCC77
VCC78
VCC79
VCC80
VCC81
VCC82
VCC83
VCC84
VCC85
VCC86
VCC87
VCC88
VCC89
VCC90
VCC91
VCC92
VCC93
VCC94
VCC95
VCC96
VCC97
VCC98
VCC99

CALISTOGA_FCBGA1466~D

<BOM Structure>

VCC_SM0
VCC_SM1
VCC_SM2
VCC_SM3
VCC_SM4
VCC_SM5
VCC_SM6
VCC_SM7
VCC_SM8

VCC_SM9
VCC_SM10
VCC_SM11
VCC_SM12
VCC_SM13
VCC_SM14
VCC_SM15
VCC_SM16
VCC_SM17
VCC_SM18
VCC_SM19
VCC_SM20
VCC_SM21
VCC_SM22
VCC_SM23
VCC_SM24
VCC_SM25
VCC_SM26
VCC_SM27
VCC_SM28
VCC_SM29
VCC_SM30
VCC_SM31
VCC_SM32
VCC_SM33
VCC_SM34
VCC_SM35
VCC_SM36
VCC_SM37
VCC_SM38
VCC_SM39
VCC_SM40
VCC_SM41
VCC_SM42
VCC_SM43
VCC_SM44
VCC_SM45
VCC_SM46
VCC_SM47
VCC_SM48
VCC_SM49
VCC_SM50
VCC_SM51
VCC_SM52
VCC_SM53
VCC_SM54
VCC_SM55
VCC_SM56
VCC_SM57
VCC_SM58
VCC_SM59
VCC_SM60
VCC_SM61
VCC_SM62
VCC_SM63
VCC_SM64
VCC_SM65
VCC_SM66
VCC_SM67
VCC_SM68
VCC_SM69
VCC_SM70
VCC_SM71
VCC_SM72
VCC_SM73
VCC_SM74
VCC_SM75
VCC_SM76
VCC_SM77
VCC_SM78
VCC_SM79
VCC_SM80
VCC_SM81
VCC_SM82
VCC_SM83
VCC_SM84
VCC_SM85
VCC_SM86
VCC_SM87
VCC_SM88
VCC_SM89
VCC_SM90
VCC_SM91
VCC_SM92
VCC_SM93
VCC_SM94
VCC_SM95
VCC_SM96
VCC_SM97
VCC_SM98
VCC_SM99

AU41
AT41
AM41
AU40
BA34
AY34
AW34
AV34
AU34
AT34
AR34
BA30
AY30
AW30
AV30
AU30
AT30
AR30
AP30
AN30
AM30
AM29
AL29
AK29
AJ29
AH29
AJ28
AH28
AJ27
AH27
BA26
AY26
AW26
AV26
AU26
AT26
AR26
AJ26
AH26
AJ25
AH25
AJ24
AH24
BA23
AJ23
BA22
AY22
AW22
AV22
AU22
AT22
AR22
AP22
AK22
AJ22
AK21
AK20
BA19
AY19
AW19
AV19
AU19
AT19
AR19
AP19
AK19
AJ19
AJ18
AJ17
AH17
AJ16
AH16
BA15
AY15
AW15
AV15
AU15
AT15
AR15
AJ15
AJ14
AJ13
AH13
AK12
AJ12
AH12
AG12
AK11
BA8
AY8
AW8
AV8
AT8
AR8
AP8
BA6
AY6
AW6
AV6
AT6

+1.8V

MCH_AT41
MCH_AM41

C125

1

1

C124

2

2

0.47U_0603_10V7K

0.47U_0603_10V7K

Place near pin AT41 & AM41

1

1

C329

C370

2

2

0.1U_0402_16V4Z

1

C123

2

0.47U_0603_10V7K

Place near pin BA23

1

1

C126

C122

C365

2

2

10U_1206_6.3V6M

10U_1206_6.3V6M

1

2

0.47U_0603_10V7K

Place near pin BA15

CFG[2:0]

CFG5

CFG7

CFG9

CFG6

PSB 4X CLK Enable 1 = Calistoga

CFG[13:12]

CFG16

1

2

0.1U_0402_16V4Z

CFG10 CFG18

CFG19

1

C355

C341

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

SDVO_CTRLDATA

CFG20

(PCIE/SDVO select)

1

+

C85

2

220U_D2_4M_R45@

CFG[3:17] have internal pull up
CFG[19:18] have internal pull down

011 = 667MT/s FSB
001 = 533MT/s FSB

0 = DMI x 2
1 = DMI x 4

0 = Reserved
1 = Mobile Yonah CPU

0 = Lane Reversal Enable
1 = Normal Operation

(Default)

*

(Default)

*

(Default)

0 = Reserved

*

00 = Reserved
01 = XOR Mode Enabled
10 = All Z Mode Enabled
11 = Normal Operation

0 = Dynamic ODT Disabled
1 = Dynamic ODT Enabled (Default)

10 = 1.05V
01 = 1.5V

0 = Normal Operation
1 = DMI Lane Reversal Enable

0 = No SDVO Device Present

*

(Default)

(Default)

1 = SDVO Device Present

0 = Only PCIE or SDVO is
operational.
1 = PCIE/SDVO are operating
simu.

CFG39

CFG179

CFG59
CFG79

CFG99
CFG119
CFG129
CFG139
CFG169

CFG189
CFG199
CFG209

*

R284 2.2K_0402_5%@

1 2

R282 2.2K_0402_5%@

1 2

R67 2.2K_0402_5%@

1 2

R77 2.2K_0402_5%@

1 2

R72 2.2K_0402_5%@

1 2

R69 2.2K_0402_5%@

1 2

R64 2.2K_0402_5%@

1 2

R283 2.2K_0402_5%@

1 2

R74 2.2K_0402_5%@

1 2

R289 1K_0402_5%@

1 2

R292 1K_0402_5%@

1 2

R290 1K_0402_5%@

1 2

*

*

(Default)

*

(Default)

*

(Default)

*

+3VS

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/09/10 2006/06/23

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, M/B LA-3051P

401397

星期四 十月

13 45, 06, 2005

1

A

of

5

4

3

2

1

U7I

AC41

VSS0

AA41

VSS1

W41

VSS2

T41

VSS3

P41

VSS4

M41

D D

C C

B B

A A

VSS5

J41

VSS6

F41

VSS7

AV40

VSS8

AP40

VSS9

AN40

VSS10

AK40

VSS11

AJ40

VSS12

AH40

VSS13

AG40

VSS14

AF40

VSS15

AE40

VSS16

B40

VSS17

AY39

VSS18

AW39

VSS19

AV39

VSS20

AR39

VSS21

AN39

VSS22

AJ39

VSS23

AC39

VSS24

AB39

VSS25

AA39

VSS26

Y39

VSS27

W39

VSS28

V39

VSS29

T39

VSS30

R39

VSS31

P39

VSS32

N39

VSS33

M39

VSS34

L39

VSS35

J39

VSS36

H39

VSS37

G39

VSS38

F39

VSS39

D39

VSS40

AT38

VSS41

AM38

VSS42

AH38

VSS43

AG38

VSS44

AF38

VSS45

AE38

VSS46

C38

VSS47

AK37

VSS48

AH37

VSS49

AB37

VSS50

AA37

VSS51

Y37

VSS52

W37

VSS53

V37

VSS54

T37

VSS55

R37

VSS56

P37

VSS57

N37

VSS58

M37

VSS59

L37

VSS60

J37

VSS61

H37

VSS62

G37

VSS63

F37

VSS64

D37

VSS65

AY36

VSS66

AW36

VSS67

AN36

VSS68

AH36

VSS69

AG36

VSS70

AF36

VSS71

AE36

VSS72

AC36

VSS73

C36

VSS74

B36

VSS75

BA35

VSS76

AV35

VSS77

AR35

VSS78

AH35

VSS79

AB35

VSS80

AA35

VSS81

Y35

VSS82

W35

VSS83

V35

VSS84

T35

VSS85

R35

VSS86

P35

VSS87

N35

VSS88

M35

VSS89

L35

VSS90

J35

VSS91

H35

VSS92

G35

VSS93

F35

VSS94

D35

VSS95

AN34

VSS96

AK34

VSS97

AG34

VSS98

AF34

VSS99

CALISTOGA_FCBGA1466~D

<BOM Structure>

P O W E R

VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS140
VSS141
VSS142
VSS143
VSS144
VSS145
VSS146
VSS147
VSS148
VSS149
VSS150
VSS151
VSS152
VSS153
VSS154
VSS155
VSS156
VSS157
VSS158
VSS159
VSS160
VSS161
VSS162
VSS163
VSS164
VSS165
VSS166
VSS167
VSS168
VSS169
VSS170
VSS171
VSS172
VSS173
VSS174
VSS175
VSS176
VSS177
VSS178
VSS179
VSS180
VSS181
VSS182
VSS183
VSS184
VSS185
VSS186
VSS187
VSS188
VSS189
VSS190
VSS191
VSS192
VSS193
VSS194
VSS195
VSS196
VSS197
VSS198
VSS199

AE34
AC34
C34
AW33
AV33
AR33
AE33
AB33
Y33
V33
T33
R33
M33
H33
G33
F33
D33
B33
AH32
AG32
AF32
AE32
AC32
AB32
G32
B32
AY31
AV31
AN31
AJ31
AG31
AB31
Y31
AB30
E30
AT29
AN29
AB29
T29
N29
K29
G29
E29
C29
B29
A29
BA28
AW28
AU28
AP28
AM28
AD28
AC28
W28
J28
E28
AP27
AM27
AK27
J27
G27
F27
C27
B27
AN26
M26
K26
F26
D26
AK25
P25
K25
H25
E25
D25
A25
BA24
AU24
AL24
AW23
AT23
AN23
AM23
AH23
AC23
W23
K23
J23
F23
C23
AA22
K22
G22
F22
E22
D22
A22
BA21
AV21
AR21

U7J

AN21

VSS200

AL21

VSS201

AB21

VSS202

Y21

VSS203

P21

VSS204

K21

VSS205

J21

VSS206

H21

VSS207

C21

VSS208

AW20

VSS209

AR20

VSS210

AM20

VSS211

AA20

VSS212

K20

VSS213

B20

VSS214

A20

VSS215

AN19

VSS216

AC19

VSS217

W19

VSS218

K19

VSS219

G19

VSS220

C19

VSS221

AH18

VSS222

P18

VSS223

H18

VSS224

D18

VSS225

A18

VSS226

AY17

VSS227

AR17

VSS228

AP17

VSS229

AM17

VSS230

AK17

VSS231

AV16

VSS232

AN16

VSS233

AL16

VSS234

J16

VSS235

F16

VSS236

C16

VSS237

AN15

VSS238

AM15

VSS239

AK15

VSS240

N15

VSS241

M15

VSS242

L15

VSS243

B15

VSS244

A15

VSS245

BA14

VSS246

AT14

VSS247

AK14

VSS248

AD14

VSS249

AA14

VSS250

U14

VSS251

K14

VSS252

H14

VSS253

E14

VSS254

AV13

VSS255

AR13

VSS256

AN13

VSS257

AM13

VSS258

AL13

VSS259

AG13

VSS260

P13

VSS261

F13

VSS262

D13

VSS265

B13

VSS264

AY12

VSS263

AC12

VSS266

K12

VSS267

H12

VSS268

E12

VSS269

AD11

VSS270

AA11

VSS271

Y11

VSS272

J11

VSS273

D11

VSS274

B11

VSS275

AV10

VSS276

AP10

VSS277

AL10

VSS278

AJ10

VSS279

CALISTOGA_FCBGA1466~D

<BOM Structure>

P O W E R

VSS280
VSS281
VSS282
VSS283
VSS284
VSS285
VSS286
VSS287
VSS288
VSS289
VSS290
VSS292
VSS291
VSS293
VSS294
VSS295
VSS296
VSS297
VSS298
VSS299
VSS300
VSS301
VSS302
VSS303
VSS304
VSS305
VSS306
VSS307
VSS308
VSS309
VSS310
VSS311
VSS312
VSS313
VSS314
VSS315
VSS316
VSS317
VSS318
VSS319
VSS320
VSS321
VSS322
VSS323
VSS324
VSS325
VSS326
VSS327
VSS328
VSS329
VSS330
VSS331
VSS332
VSS333
VSS334
VSS335
VSS336
VSS337
VSS338
VSS339
VSS340
VSS341
VSS342
VSS343
VSS344
VSS345
VSS346
VSS347
VSS348
VSS349
VSS350
VSS351
VSS352
VSS353
VSS354
VSS355
VSS356
VSS357
VSS358
VSS359
VSS360

AG10
AC10
W10
U10
BA9
AW9
AR9
AH9
AB9
Y9
R9
G9
E9
A9
AG8
AD8
AA8
U8
K8
C8
BA7
AV7
AP7
AL7
AJ7
AH7
AF7
AC7
R7
G7
D7
AG6
AD6
AB6
Y6
U6
N6
K6
H6
B6
AV5
AF5
AD5
AY4
AR4
AP4
AL4
AJ4
Y4
U4
R4
J4
F4
C4
AY3
AW3
AV3
AL3
AH3
AG3
AF3
AD3
AC3
AA3
G3
AT2
AR2
AP2
AK2
AJ2
AD2
AB2
Y2
U2
T2
N2
J2
H2
F2
C2
AL1

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/09/10 2006/06/23

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, M/B LA-3051P

401397

星期四 十月

05

14 45, 06, 20

1

A

of

A

DDR_A_DQS#[0..7]10

DDR_A_D[0..63]10

DDR_A_DM[0..7]10
DDR_A_DQS[0..7]10
DDR_A_MA[0..13]10

1 1

Layout Note:
Place near JP41

+1.8V

2.2U_0603_6.3V6K

1

2

C91

1

2

0.1U_0402_16V4Z

1

2

+0.9VS

2.2U_0603_6.3V6K

C115

C113

1

2

0.1U_0402_16V4Z

1

2

C106

C110

RP14 56_0404_4P2R_5%

14
23

RP12 56_0404_4P2R_5%

14
23

RP11 56_0404_4P2R_5%

14
23

RP9 56_0404_4P2R_5%

14
23

RP7 56_0404_4P2R_5%

14
23

RP4 56_0404_4P2R_5%

14
23

RP13 56_0404_4P2R_5%

14
23

2.2U_0603_6.3V6K

2.2U_0603_6.3V6K
C86

1

2

2 2

Layout Note:
Place one cap close to every 2 pullup
resistors terminated to +0.9VS

+0.9VS

0.1U_0402_16V4Z

1

2

C99

3 3

DDR_A_MA5
DDR_A_MA8

DDR_A_MA1
DDR_A_MA3

DDR_A_RAS#
DDR_CS0_DIMMA#

DDR_A_BS#0
DDR_A_MA10

DDR_A_CAS#
DDR_A_WE#

4 4

DDR_CS1_DIMMA#
M_ODT1

0.1U_0402_16V4Z

1

2

C97

2.2U_0603_6.3V6K

C116

1

2

0.1U_0402_16V4Z

1

2

C94

RP10

1 4
2 3

RP8

56_0404_4P2R_5%

1 4
2 3

RP6

56_0404_4P2R_5%

1 4
2 3

RP5

56_0404_4P2R_5%

1 4
2 3

RP3

56_0404_4P2R_5%

1 4
2 3

RP2

56_0404_4P2R_5%

2 3
1 4

56_0404_4P2R_5%

A

C87

1

2

0.1U_0402_16V4Z

B

0.1U_0402_16V4Z

0.1U_0402_16V4Z

C111

1

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

2

2

C92

C90

DDR_A_BS#2
DDR_CKE0_DIMMA

DDR_A_MA7
DDR_A_MA6

DDR_A_MA9
DDR_A_MA12

DDR_A_MA4
DDR_A_MA2

DDR_A_MA0
DDR_A_BS#1

M_ODT0
DDR_A_MA13

DDR_CKE1_DIMMA
DDR_A_MA11

B

C

0.1U_0402_16V4Z

0.1U_0402_16V4Z

C103

C98

1

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

2

C95

1

1

2

2

0.1U_0402_16V4Z

1

1

2

2

C100

C104

Layout Note:
Place these resistor
closely JP41,all
trace length Max=1.5"

C89

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

2

2

C108

C112

D

DDR_A_D4
DDR_A_D1

DDR_A_DQS#0
DDR_A_DQS0

DDR_A_D2
DDR_A_D3

DDR_A_D8
DDR_A_D14

DDR_A_DQS#1
DDR_A_DQS1

DDR_A_D9
DDR_A_D15 DDR_A_D10

DDR_A_D16
DDR_A_D17

DDR_A_DQS#2
DDR_A_DQS2

DDR_A_D18
DDR_A_D19

DDR_A_D24
DDR_A_DM3

DDR_A_D26
DDR_A_D27

DDR_CKE0_DIMMA9

DDR_A_BS#210

DDR_A_BS#010

DDR_A_WE#10

DDR_A_CAS#10

DDR_CS1_DIMMA#9

M_ODT19

CLK_SMBDATA16,17

CLK_SMBCLK16,17

DDR_CKE0_DIMMA

DDR_A_BS#2
DDR_A_MA12

DDR_A_MA9 DDR_A_MA7
DDR_A_MA8

DDR_A_MA5
DDR_A_MA3
DDR_A_MA1

DDR_A_MA10
DDR_A_BS#0
DDR_A_WE#

DDR_A_CAS#
DDR_CS1_DIMMA#

M_ODT1
DDR_A_D37

DDR_A_D36
DDR_A_DQS#4

DDR_A_DQS4
DDR_A_D35

DDR_A_D32
DDR_A_D40

DDR_A_D44
DDR_A_DM5
DDR_A_D41

DDR_A_D46
DDR_A_D49

DDR_A_D48

DDR_A_DQS#6
DDR_A_DQS6

DDR_A_D50
DDR_A_D61

DDR_A_D60
DDR_A_DM7
DDR_A_D59

DDR_A_D58
CLK_SMBDATA

CLK_SMBCLK

+3VS

1

C72

0.1U_0402_16V4Z

2

E

+1.8V

1

C73

2.2U_0603_6.3V6K

2

JP4

1

VREF

3

VSS

5

DQ0

7

DQ1

9

VSS

11

DQS0#

13

DQS0

15

VSS

17

DQ2

19

DQ3

21

VSS

23

DQ8

25

DQ9

27

VSS

29

DQS1#

31

DQS1

33

VSS

35

DQ10

37

DQ11

39

VSS

41

VSS

43

DQ16

45

DQ17

47

VSS

49

DQS2#

51

DQS2

53

VSS

55

DQ18

57

DQ19

59

VSS

61

DQ24

63

DQ25

65

VSS

67

DM3

69

NC

71

VSS

73

DQ26

75

DQ27

77

VSS

79

CKE0

81

VDD

83

NC

85

BA2

87

VDD

89

A12

91

A9

93

A8

95

VDD

97

A5

99

A3

101

A1

103

VDD

105

A10/AP

107

BA0

109

WE#

111

VDD

113

CAS#

115

NC/S1#

117

VDD

119

NC/ODT1

121

VSS

123

DQ32

125

DQ33

127

VSS

129

DQS4#

131

DQS4

133

VSS

135

DQ34

137

DQ35

139

VSS

141

DQ40

143

DQ41

145

VSS

147

DM5

149

VSS

151

DQ42

153

DQ43

155

VSS

157

DQ48

159

DQ49

161

VSS

163

NC,TEST

165

VSS

167

DQS6#

169

DQS6

171

VSS

173

DQ50

175

DQ51

177

VSS

179

DQ56

181

DQ57

183

VSS

185

DM7

187

VSS

189

DQ58

191

DQ59

193

VSS

195

SDA

197

SCL

199

VDDSPD

FOX_AS0A426-N8RN-7F~N

SO-DIMM A

REVERSE

VSS
DQ4
DQ5
VSS
DM0
VSS
DQ6
DQ7

VSS
DQ12
DQ13

VSS

DM1

VSS

CK0

CK0#

VSS
DQ14
DQ15

VSS

VSS
DQ20
DQ21

VSS

DM2

VSS
DQ22
DQ23

VSS
DQ28
DQ29

VSS

DQS3#

DQS3

VSS
DQ30
DQ31

VSS

NC/CKE1

VDD

NC/A15
NC/A14

VDD

VDD

VDD

RAS#

VDD
ODT0

NC/A13

VDD

VSS
DQ36
DQ37

VSS

DM4

VSS
DQ38
DQ39

VSS
DQ44
DQ45

VSS

DQS5#

DQS5

VSS
DQ46
DQ47

VSS
DQ52
DQ53

VSS

CK1

CK1#

VSS

DM6

VSS
DQ54
DQ55

VSS
DQ60
DQ61

VSS

DQS7#

DQS7

VSS
DQ62
DQ63

VSS

F

+1.8V

V_DDR_MCH_REF

2

DDR_A_D6

4

DDR_A_D0

6
8

DDR_A_DM0

10
12

DDR_A_D5

14

DDR_A_D7

16
18

DDR_A_D13

20

DDR_A_D12

22
24

DDR_A_DM1

26
28

M_CLK_DDR0

30

M_CLK_DDR#0

32
34

DDR_A_D11

36
38
40

42

DDR_A_D20

44

DDR_A_D21

46
48
50

NC

A11

A7
A6

A4
A2

A0
BA1
S0#

NC

SA0
SA1

52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200

DDR_A_DM2
DDR_A_D23

DDR_A_D22
DDR_A_D28DDR_A_D29

DDR_A_D25
DDR_A_DQS#3

DDR_A_DQS3
DDR_A_D31

DDR_A_D30
DDR_CKE1_DIMMA

DDR_A_MA11
DDR_A_MA6
DDR_A_MA4

DDR_A_MA2
DDR_A_MA0

DDR_A_BS#1
DDR_A_RAS#
DDR_CS0_DIMMA#

M_ODT0
DDR_A_MA13

DDR_A_D39
DDR_A_D38

DDR_A_DM4
DDR_A_D34

DDR_A_D33
DDR_A_D45

DDR_A_D43
DDR_A_DQS#5

DDR_A_DQS5
DDR_A_D47

DDR_A_D42
DDR_A_D52

DDR_A_D53
M_CLK_DDR1

M_CLK_DDR#1
DDR_A_DM6
DDR_A_D51DDR_A_D54

DDR_A_D55
DDR_A_D57

DDR_A_D56
DDR_A_DQS#7

DDR_A_DQS7
DDR_A_D62

DDR_A_D63

12

R46

10K_0402_5%

Close to VREF pins of SO-DIMM

2.2U_0805_16V4Z

M_CLK_DDR0 9
M_CLK_DDR#0 9

R83 0_0402_5%

DDR_CKE1_DIMMA 9

DDR_A_BS#1 10
DDR_A_RAS# 10
DDR_CS0_DIMMA# 9

M_ODT0 9

M_CLK_DDR1 9
M_CLK_DDR#1 9

12

R49

10K_0402_5%

G

C133

V_DDR_MCH_REF 9,16

V_DDR_MCH_REF

1

C375

2

@

0.1U_0402_16V4Z

0.1U_0402_16V4Z

C130

1

1

2

2

+1.8V

H

12

R306

100_0402_1%@

12

R304

100_0402_1%@

Close to connect

12

PM_EXTTS#0 9

Top side

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

C

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

D

2005/09/10 2006/06/23

E

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

F

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, M/B LA-3051P

401397

星期四 十月

G

A

of

15 45, 06, 2005

H

A

DDR_B_DQS#[0..7]10

DDR_B_D[0..63]10

DDR_B_DM[0..7]10
DDR_B_DQS[0..7]10
DDR_B_MA[0..13]10

1 1

Layout Note:

Place near JP42

+1.8V

2.2U_0603_6.3V6K

2.2U_0603_6.3V6K

2.2U_0603_6.3V6K

2.2U_0603_6.3V6K

C359

C322

1

1

2

2

2 2

Layout Note:
Place one cap close to every 2 pullup
resistors terminated to +0.9VS

+0.9VS

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

2

2

C334

C343

3 3

4 4

DDR_B_MA1
DDR_B_MA3

DDR_B_BS#0
DDR_B_MA10

DDR_B_MA0
DDR_B_BS#1

DDR_B_RAS#
DDR_CS2_DIMMB#

DDR_B_CAS#
DDR_B_WE#

DDR_CS3_DIMMB#
M_ODT3

RP29

1 4
2 3

RP26

1 4
2 3

RP28

1 4
2 3

RP27

1 4
2 3

RP24

1 4
2 3

RP23

2 3
1 4

C357

1

2

0.1U_0402_16V4Z

1

1

2

2

C332

56_0404_4P2R_5%

56_0404_4P2R_5%

56_0404_4P2R_5%

56_0404_4P2R_5%

56_0404_4P2R_5%

56_0404_4P2R_5%

A

C331

+0.9VS

2.2U_0603_6.3V6K
C323

1

2

0.1U_0402_16V4Z

1

2

C327

0.1U_0402_16V4Z

C362

1

1

2

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

2

2

C330

C349

RP32 56_0404_4P2R_5%

DDR_B_MA9

14

DDR_B_MA12

23

RP35 56_0404_4P2R_5%

DDR_CKE3_DIMMB

14

DDR_B_MA11

23

RP31 56_0404_4P2R_5%

DDR_B_MA5

14

DDR_B_MA8

23

RP34 56_0404_4P2R_5%

DDR_B_MA7

14

DDR_B_MA6

23

RP30 56_0404_4P2R_5%

DDR_B_MA4

14

DDR_B_MA2

23

RP25 56_0404_4P2R_5%

M_ODT2

14

DDR_B_MA13

23

RP36

DDR_B_BS#2

14

DDR_CKE2_DIMMB

23

56_0404_4P2R_5%

C321

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

2

C326

C325

C346

1

1

2

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

2

2

C333

C324

Layout Note:
Place these resistor
closely JP42,all
trace length Max=1.5"

B

0.1U_0402_16V4Z
C337

1

2

DDR_CKE2_DIMMB9

DDR_B_BS#210

DDR_B_BS#010

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

1

2

2

C335

2

C342

C354

DDR_B_CAS#10

DDR_CS3_DIMMB#9

CLK_SMBDATA15,17

CLK_SMBCLK15,17

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

B

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

DDR_B_WE#10

M_ODT39

C

+1.8V

JP16

1

VREF

3

DDR_B_D0
DDR_B_D1

DDR_B_DQS#0
DDR_B_DQS0

DDR_B_D2
DDR_B_D3

DDR_B_D8
DDR_B_D9

DDR_B_DQS#1
DDR_B_DQS1

DDR_B_D10
DDR_B_D11

DDR_B_D17
DDR_B_D20

DDR_B_DQS#2
DDR_B_DQS2

DDR_B_D18
DDR_B_D19

DDR_B_D28
DDR_B_D25

DDR_B_DM3

DDR_B_D30
DDR_B_D31

DDR_CKE2_DIMMB

DDR_B_BS#2
DDR_B_MA12

DDR_B_MA9
DDR_B_MA8

DDR_B_MA5
DDR_B_MA3
DDR_B_MA1

DDR_B_MA10
DDR_B_BS#0
DDR_B_WE#

DDR_B_CAS#
DDR_CS3_DIMMB#

M_ODT3
DDR_B_D32

DDR_B_D33
DDR_B_DQS#4

DDR_B_DQS4
DDR_B_D34

DDR_B_D35
DDR_B_D40

DDR_B_D41
DDR_B_DM5
DDR_B_D42

DDR_B_D43
DDR_B_D48

DDR_B_D49

DDR_B_DQS#6
DDR_B_DQS6

DDR_B_D51
DDR_B_D50

DDR_B_D56
DDR_B_D61 DDR_B_D57

DDR_B_DM7
DDR_B_D59

DDR_B_D58
CLK_SMBDATA

CLK_SMBCLK

+3VS

1

2

1

C296

2.2U_0603_6.3V6K

2

C295

0.1U_0402_16V4Z

2005/09/10 2006/06/23

C

VSS

5

DQ0

7

DQ1

9

VSS

11

DQS0#

13

DQS0

15

VSS

17

DQ2

19

DQ3

21

VSS

23

DQ8

25

DQ9

27

VSS

29

DQS1#

31

DQS1

33

VSS

35

DQ10

37

DQ11

39

VSS

41

VSS

43

DQ16

45

DQ17

47

VSS

49

DQS2#

51

DQS2

53

VSS

55

DQ18

57

DQ19

59

VSS

61

DQ24

63

DQ25

65

VSS

67

DM3

69

NC

71

VSS

73

DQ26

75

DQ27

77

VSS

79

CKE0

81

VDD

83

NC

85

BA2

87

VDD

89

A12

91

A9

93

A8

95

VDD

97

A5

99

A3

101

A1

103

VDD

105

A10/AP

107

BA0

109

WE#

111

VDD

113

CAS#

115

NC/S1#

117

VDD

119

NC/ODT1

121

VSS

123

DQ32

125

DQ33

127

VSS

129

DQS4#

131

DQS4

133

VSS

135

DQ34

137

DQ35

139

VSS

141

DQ40

143

DQ41

145

VSS

147

DM5

149

VSS

151

DQ42

153

DQ43

155

VSS

157

DQ48

159

DQ49

161

VSS

163

NC,TEST

165

VSS

167

DQS6#

169

DQS6

171

VSS

173

DQ50

175

DQ51

177

VSS

179

DQ56

181

DQ57

183

VSS

185

DM7

187

VSS

189

DQ58

191

DQ59

193

VSS

195

SDA

197

SCL

199

VDDSPD

FOX_AS0A426-N2SN-7F~N

SO-DIMM B
STANDARD

Bottom side

Compal Secret Data

Deciphered Date

VSS
DQ4
DQ5
VSS
DM0
VSS
DQ6
DQ7

VSS
DQ12
DQ13

VSS

DM1

VSS

CK0#

VSS
DQ14
DQ15

VSS

VSS
DQ20
DQ21

VSS

DM2

VSS
DQ22
DQ23

VSS
DQ28
DQ29

VSS

DQS3#

DQS3

VSS
DQ30
DQ31

VSS

NC/CKE1

VDD

NC/A15
NC/A14

VDD

VDD

VDD
RAS#

VDD
ODT0

NC/A13

VDD

VSS
DQ36
DQ37

VSS

DM4

VSS
DQ38
DQ39

VSS
DQ44
DQ45

VSS

DQS5#

DQS5

VSS
DQ46
DQ47

VSS
DQ52
DQ53

VSS

CK1#

VSS

DM6

VSS
DQ54
DQ55

VSS
DQ60
DQ61

VSS

DQS7#

DQS7

VSS
DQ62
DQ63

VSS

CK0

NC

A11

BA1
S0#

NC

CK1

SA0
SA1

D

+1.8V

V_DDR_MCH_REF

2

DDR_B_D5

4

DDR_B_D4

6
8

DDR_B_DM0

10
12

DDR_B_D6

14

DDR_B_D7

16
18

DDR_B_D12

20

DDR_B_D13

22
24

DDR_B_DM1

26
28

M_CLK_DDR3

30

M_CLK_DDR#3

32
34

DDR_B_D14

36

DDR_B_D15

38
40

42

DDR_B_D21

44

DDR_B_D16

46
48
50

DDR_B_DM2

52
54

DDR_B_D22

56

DDR_B_D23

58
60

DDR_B_D26

62

DDR_B_D24

64
66

DDR_B_DQS#3

68

DDR_B_DQS3

70
72

DDR_B_D29

74

DDR_B_D27

76
78

DDR_CKE3_DIMMB

80
82
84
86
88

DDR_B_MA11

90

DDR_B_MA7

92

A7
A6

A4
A2
A0

94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200

D

DDR_B_MA6
DDR_B_MA4

DDR_B_MA2
DDR_B_MA0

DDR_B_BS#1
DDR_B_RAS#
DDR_CS2_DIMMB#

M_ODT2
DDR_B_MA13

DDR_B_D36
DDR_B_D37

DDR_B_DM4
DDR_B_D39

DDR_B_D38
DDR_B_D44

DDR_B_D45
DDR_B_DQS#5

DDR_B_DQS5
DDR_B_D46

DDR_B_D47
DDR_B_D52

DDR_B_D53
M_CLK_DDR2

M_CLK_DDR#2
DDR_B_DM6
DDR_B_D54

DDR_B_D55
DDR_B_D60

DDR_B_DQS#7
DDR_B_DQS7

DDR_B_D62
DDR_B_D63

Close to VREF pins of SO-DIMM

2.2U_0805_16V4Z

1

2

M_CLK_DDR3 9
M_CLK_DDR#3 9

R299 0_0402_5%

DDR_CKE3_DIMMB 9

DDR_B_BS#1 10
DDR_B_RAS# 10
DDR_CS2_DIMMB# 9

M_ODT2 9

M_CLK_DDR2 9
M_CLK_DDR#2 9

R267

1 2

10K_0402_5%

12

10K_0402_5%

R268

Title

Size Document Number Rev

Date: Sheet

0.1U_0402_16V4Z

1

C383

C380

2

12

PM_EXTTS#0 9

+3VS

Compal Electronics, Inc.

SCHEMATIC, M/B LA-3051P

401397

星期四 十月

E

V_DDR_MCH_REF 9,15

16 45, 06, 2005

E

A

of

A

B

C

D

E

1

2

14M_ICH

2.2K_0402_5%
Q14
2N7002_SOT23

D

1 3

2

2

1 3

D

2N7002_SOT23

Q13

CK_VDD_A

C143

0.047U_0402_16V4Z

CLK_PCI_ICH19

+3VS

R118

S

G

G

S

1

C138

2

10U_0805_10V4Z~N

CLK_48M_ICH21

CLK_PCI_LPC32

CLK_PCI_CB28

CLK_14M_ICH21

CLK_SMBDATA15,16

10K_0402_5%

10K_0402_5%

1

2

C385

0.047U_0402_16V4Z

CLK_PCI_EC32

CLK_MCH_DREFCLK
CLK_MCH_DREFCLK#

+3VS

CLK_PCI_ICH

CLK_SMBCLK15,16

+3VS

12

R107

+3VS

12

R106

14M_ICH

R117

2.2K_0402_5%

CLK_SMBDATA

CLK_SMBCLK

0.1U_0402_16V4Z

CLK_14M_ICH

R339 33_0402_5%

+3VS

+3VS

+CK_VDD_MAIN2

CK_VDD_REF

1

C137

2

CLK_48M_ICH

R349 33_0402_5%

R326 12_0402_5%

1 2

R352 0_0402_5%

1 2

R351 0_0402_5%

12

R104 0_0402_5%

CLK_SMBCLK

CLK_SMBDATA

12

1 2

CLK_EN#

R35010K_0402_5%

PCI_PME=SEL_PCI6

PCI_PCM

PIN27

0

CLKREQ5

1 PCICLK6

PCI_PCM

PCI_PME=SEL_PCI5

PCI_PCM

PIN22

0

CLKREQ3

1 PCICLK5

+CK_VDD_MAIN1

1 2

R96 0_0805_5%

1 2

R126 0_0805_5%

+CK_VDD_MAIN1

CK_VDD_REF

CK_VDD_48

CLK_XTAL_IN

CLK_XTAL_OUT

12

PCI_ICH

R33633_0402_5%

12

R33533_0402_5%

12

R32933_0402_5%

12

12

MCH_DREFCLK
MCH_DREFCLK#

+CK_VDD_MAIN2

FSA
FSB

FSC

PCI_EC
PCI_SIO
PCI_PCM

14M_ICH

CLKIREF

1

C134
10U_0805_10V4Z~N

2

1

C149
10U_0805_10V4Z~N

2

U13

1

VDDSRC

49

VDDSRC

54

VDDSRC

65

VDDSRC

30

VDDPCI

36

VDDPCI

12

VDDCPU

18

VDDREF

40

VDD48

20

X1

19

X2

41

USB_48MHz/FSA

45

FSB/TEST_MODE/24Mhz

23

REF0/FSC/TEST_SEL

34

PCICLK4/FCTSEL1

33

**SEL_48M/PCICLK3

32

**SEL_24M/PCICLK2

27

**SEL_PCI6/PCICLK1

22

**SEL_PCI5/REF1

43

DOTT_96MHzLPR/27MHz_NonSpread

44

DOTC_96MHzLPR/27MHz_Spread

37

ITP_EN/PCICLK_F0

39

Vtt_PwrGd#/PD

9

GND

16

SMBCLK

17

SMBDAT

4

GNDSRC

15

GNDCPU

21

GNDREF

31

GNDPCI

35

GNDPCI

42

GND48

68

GNDSRC

73

THRM_PAD

74

THRM_PAD

75

THRM_PAD

76

THRM_PAD

ICS954305AKLFT MLF 72P

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

1

C139

0.1U_0402_16V4Z

2

1

C140

0.1U_0402_16V4Z

2

R97

2.2_0603_5%

1 2

CPUCLKT2_ITP/SRCCLKT10LPR

CPUCLKC2_ITP/SRCCLKC10LPR

2005/09/10 2006/06/23

1

C142

0.1U_0402_16V4Z

2

1

C392

0.1U_0402_16V4Z

2

CK_VDD_A

VDDA

GNDA

PCI_SRC_STOP#

CPU_STOP#

CPUCLKT1LPR
CPUCLKC1LPR

CPUCLKT0LPR
CPUCLKC0LPR

SRCCLKT9LPR
SRCCLKC9LPR

CLKREQ9#
SRCCLKT8LPR
SRCCLKC8LPR

CLKREQ8#
SRCCLKT7LPR
SRCCLKC7LPR

CLKREQ7#/48Mhz_1

SRCCLKT6LPR
SRCCLKC6LPR

CLKREQ6#
SRCCLKT5LPR
SRCCLKC5LPR

CLKREQ5#/PCICLK6

SRCCLKT4LPR
SRCCLKC4LPR

CLKREQ4#
SRCCLKT3LPR
SRCCLKC3LPR

CLKREQ3#/PCICLK5

SRCCLKT2LPR
SRCCLKC2LPR

CLKREQ2#
SRCCLKT1LPR
SRCCLKC1LPR

CLKREQ1#

LCD100/96/SRC0_TLPR
LCD100/96/SRC0_CLPR

Compal Secret Data

1

C141

0.1U_0402_16V4Z

2

1 2

R102

1_0805_1%

1 2

R128

2.2_0805_1%

7
8

H_STP_PCI#

25

H_STP_CPU#

24

MCH_BCLK

11

MCH_BCLK#

10

CPU_BCLK

14

CPU_BCLK#

13

6
5

MCH_3GPLL

3

MCH_3GPLL#

2
72
70
69
71

PCIE_LAN

66

PCIE_LAN#

67
38

PCIE_SATA

63

PCIE_SATA#

64

SATACLKREQ#

62

PCIE_SATA

60

PCIE_SATA#

61
29
58

PCIE_ICH#

59
57
55
56

MINI_PCI CLK_PCI_MINI

28
52
53
26

PCIE_MCARD

50
51
46
47
48

R346 0_0402_5%

PCIE_MCARD#

R345 0_0402_5%

SSCDREFCLK

R348 0_0402_5%

SSCDREFCLK#

R347 0_0402_5%

Deciphered Date

1

C136

0.1U_0402_16V4Z

2

CK_VDD_REF

CK_VDD_48

Place crystal within
500 mils of CK410

H_STP_PCI# 21

H_STP_CPU# 21

1 2

R317 0_0402_5%

1 2

R316 0_0402_5%

1 2

R319 0_0402_5%

1 2

R318 0_0402_5%

1 2

R315 0_0402_5%

1 2

R314 0_0402_5%

R321 10K_0402_5%
R323 10K_0402_5%@

1 2

R328 0_0402_5%

1 2

R325 0_0402_5%

R353 10K_0402_5%
R362 10K_0402_5%@

1 2

R334 0_0402_5%

1 2

R331 0_0402_5%

1 2

R332 33_0402_5%

1 2

R341 0_0402_5%

1 2

R338 0_0402_5%

R112 10K_0402_5%
R108 10K_0402_5%@

1 2

R110 33_0402_5%

1 2
1 2

R125 10K_0402_5%

1 2
1 2

D

CLK_MCH_BCLK
CLK_MCH_BCLK#

CLK_CPU_BCLK
CLK_CPU_BCLK#

CLK_MCH_3GPLL
CLK_MCH_3GPLL#

12
12

CLK_PCIE_LAN
CLK_PCIE_LAN#

12
12

CLK_PCIE_SATA
CLK_PCIE_SATA#
CLK_PCI_TPM
CLK_PCIE_ICHPCIE_ICH
CLK_PCIE_I CH#

12
12

CLK_PCIE_MCARD
CLK_PCIE_MCARD#

12

MCH_SSCDREFCLK
MCH_SSCDREFCLK#

1

2

CLKREQA#

CLKREQD#

C135

0.1U_0402_16V4Z

Place near U54

Place these components

CLK_MCH_BCLK 9
CLK_MCH_BCLK# 9

CLK_CPU_BCLK 6
CLK_CPU_BCLK# 6

CLK_MCH_3GPLL 9
CLK_MCH_3GPLL# 9
CLKREQA# 9

+3VS

CLK_PCIE_LAN 25
CLK_PCIE_LAN# 25
CLK_PCIE_LAN_EN 21

+3VS

CLK_PCIE_SATA 20
CLK_PCIE_SATA# 20
CLK_PCI_TPM 32
CLK_PCIE_ICH 21
CLK_PCIE_ICH# 21
CLK_PCIE_ICH_EN 21

+3VS

CLK_PCI_MINI 43

CLK_PCIE_MCARD 27
CLK_PCIE_MCARD# 27

+3VS

MCH_SSCDREFCLK 9
MCH_SSCDREFCLK# 9

Title

Size Document Number Rev

Date: Sheet

near each pin within 40
mils.

CLK_CPU_BCLK

R310 49.9_0402_1%@

CLK_CPU_BCLK#

R309 49.9_0402_1%@

CLK_MCH_BCLK

R308 49.9_0402_1%@

CLK_MCH_BCLK#

R307 49.9_0402_1%@

SATACLKREQ#

R109 10K_0402_5%
R111 10K_0402_5%@

CLKREQD# 27

MCH_SSCDREFCLK
MCH_SSCDREFCLK#
CLK_PCIE_MCARD
CLK_PCIE_MCARD#
CLK_MCH_3GPLL
CLK_MCH_3GPLL#
CLK_PCIE_LAN
CLK_PCIE_LAN#
CLK_PCIE_ICH
CLK_PCIE_ICH#
CLK_MCH_DREFCLK
CLK_MCH_DREFCLK#
CLK_PCIE_SATA
CLK_PCIE_SATA#

12
12

1 2

R358 49.9_0402_1%@

1 2

R357 49.9_0402_1%@

1 2

R356 49.9_0402_1%@

1 2

R355 49.9_0402_1%@

1 2

R312 49.9_0402_1%@

1 2

R311 49.9_0402_1%@

1 2

R327 49.9_0402_1%@

1 2

R324 49.9_0402_1%@

1 2

R340 49.9_0402_1%@

1 2

R337 49.9_0402_1%@

1 2

R360 49.9_0402_1%@

1 2

R359 49.9_0402_1%@

1 2

R333 49.9_0402_1%@

1 2

R330 49.9_0402_1%@

Compal Electronics, Inc.

SCHEMATIC, M/B LA-3051P

401397

期四 十月

E

+3VS

12
12

12
12

SATACLKREQ# 21

of

17 45¬P , 06, 2005

A

FSLC1FSLB

CLKSEL2

0

Table : ICS954325

1 1

R361

8.2K_0402_5%

FSA

FSB

CLK_EN#42

+3VS

12

12

1 2

0_0402_5%@

CLK_Ra

1 2

0_0402_5%

CLK_Rb

FSC

R113

10K_0402_5%@

PCI_ICH

R114
10K_0402_5%

R119

R129

8.2K_0402_5%

R127

0_0402_5%

1 2
1 2

R99

0_0402_5%@

CLK_Rc

CPU_BSEL07

2 2

CPU_BSEL17

ICS_CLK GEN BUG,
need FSC pull down

CPU_BSEL27

3 3

LCD clock select

4 4

FSLA

CLKSEL1

CLKSEL0

0

1

+VCCP

R123

56_0402_5%

CLK_Rd

1 2

1 2

12

R122

1K_0402_5%

12

R124
1K_0402_5%@

+VCCP

R131
1K_0402_5%@

1 2

1 2

12

R130

1K_0402_5%

12

R132

@

0_0402_5%

CLK_Re

+VCCP

R100

R105

1K_0402_5%@

1 2

1 2

R98

1K_0402_5%

12

R101

0_0402_5%

CLK_Rf

+3VS

12

R116

10K_0402_5%

CLK_EN#

PCI_ICH = FCTSEL1

FCTSEL1
(PIN34)

0

1

MHz

MHz

MHz

133

166

MCH_CLKSEL0 9

14.31818MHZ_20P_6X1430004201

MCH_CLKSEL1 9

33.31

1000

100

33.3

1 2

1 2

CLK_PCI_MINI

Reserved for PCI CLK when
use ICS954305

MCH_CLKSEL2 9

CLK_LPC_14M32

C39033P_0402_50V8J

Y2

C38933P_0402_50V8J

R525 12_0402_5%@

R115 12_0402_5%@

ICH_SMBDATA21,26,27

ICH_SMBCLK21,26, 27

12

CLK_XTAL_IN

CLK_XTAL_OUT

R530 12_0402_5%

CK_VDD_48

C148

PCI_SIOCLK_PCI_TPM

12

PCI_PCM

12

+3VS

1

2

10U_0805_10V4Z~N

CLK_MCH_DREFCLK9
CLK_MCH_DREFCLK#9

12

PIN43 PIN44 PIN47 PIN48

DOT96T DOT96C 96/100M_T 96/100M_C

27Mout 27MSSout SRCT0 SRCC0

PCI

SRC

CPU

Note: pin34 have invert this logic

High:Pin18/19 = 100MHz
Low:Pin18/19 = 96MHz

*

A

B

A

TV-OUT Connector

TV_CRMA11

TV_LUMA11

1 1

TV_COMPS11

C/R_VGA

12

R44

150_0402_1%

Y/G_VGA SVIDEO_Y

12

R38

150_0402_1%

COMP/B_VGA

12

R43

150_0402_1%

1

C62

82P_0402_50V8J

2

1

C50

82P_0402_50V8J

2

1

C53

82P_0402_50V8J

2

1 2

L11
CHB1608B121_0603

1 2

L9
CHB1608B121_0603

1 2

L10
CHB1608B121_0603

B

1

C61
82P_0402_50V8J

2

1

C49
82P_0402_50V8J

2

1

C52
82P_0402_50V8J

2

SVIDEO_C

SVIDEO_COMP/B

D7

2

DAN217_SC59@

C

D

E

Inverter Pin Define

INV_PWR

W to B Pin Define

B+

1392

JTV1

7
6
5
4
3
2
1

SUYIN_030107FR007T115ZR~N

1

3

1

D6

2

3

DAN217_SC59@

1

D8

2

3

+3VS

DAN217_SC59@

DISPOFF#
EDID_DAT EDID_CLK

UTX0­UTX0+

GND

UTX1­UTX1+

GND

UTX2­UTX2+

GND

UTX3­UTX3+

GND

UCLK-

UCLK+
LCDVDD
LCDVDD

354

9
11
13
15
17
19
21
23
25
27
29
31
33
35

B+

GND

DAC_BRIGINVT_PWM

6
87

GND

10

LTX1-

12

LTX1+

14

GND

16

LTX2-

18

LTX2+

20

GND

22

LTX0-

24

LTX0+

26

GND

28

LCLK-

30

LCLK+

32

GND

34
36

LTX3­LTX3+

3837
40

+3VS

1

INV_PWR

2

INV_PWM

3

DISOFF#

4

DAC_BRIG

5

GND

6

GND

7

2

R399

1

0_0402_5%

D18

1

2

3

10P_0402_50V8J

C4

27P_0402_50V8J

+3VS

5

U33

P

B

Y

A

G

NC7SZ08P5X_NL_SC70-5

3

0_0402_5%

1 2

R41

R40 0_0402_5%

D19

DAN217_SC59

1

2

1

C3

2

CRTHSYNC#

CRTVSYNC#

1

C5
27P_0402_50V8J

2

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITT EN CON SENT O F COMPAL ELECTRONICS, INC.

C48

DISPOFF#

1 2

4

220P_0402_50V7K

+3VS

1 2

+3VS

3

Issued Date

12

12

R37

R36

10K_0402_5%

10K_0402_5%

EDID_CLK

EDID_DAT

+5VS +CRT_VCC

+CRT_VCCF

D20

2 1

RB751V_SOD323

1.1A_6VDC_FUSE

0.1U_0402_16V4Z

CRTR

CRTG

CRTB

1

C225

2

100P_0402_50V8J

C6

100P_0402_50V8J

F4

2005/09/10 2006/06/23

C

BIA_PWM11

21

1

2

R297

BIA_PWM INVT_PWM

1

C7

JP4.18&19 will connect to GND by Layout.

2

1

C226

100P_0402_50V8J

2

12

10_0402_5%@

JP1

6

11

1
7

12

2
8

13

3
9

14

16

4

17
10
15

5

FOX_DZ11A91-NL201-7F~N

R1

1 2

2K_0402_5%

Compal Secret Data

Deciphered Date

D

B+

+LCDVDD

R216

1 2

2K_0402_5%

Q16 BSS138_SOT23

1 3

For EMI

R27 0_0603_5%

1 2

LVDSA0-11
LVDSA0+11

LVDSA1-11
LVDSA1+11

LVDSA2-11

LVDSA2+11

LVDSAC-11

LVDSAC+11

1 2

R28 0_0603_5%

For EMI

4.7U_0805_10V4Z

2

G

D

S

Q17 BSS138_SOT23

1 3

D

PANEL +LCDVDD CTRL CKT

C51

+LCDVDD

L1

L2

L3

R10

B

BKOFF#32

GMCH_ENBKL11

C46

D17

DAN217_SC59

1

C1

2

10P_0402_50V8J

L4

1 2

CHB1608U301_0603

L5

1 2

CHB1608U301_0603

VSYNC#

1

2

3

10P_0402_50V8J

1 2

EDID_CLK_LCD11

EDID_DAT_LCD11

DAN217_SC59

1

C2

2

1

2

Q6

2

2N7002_SOT23

G

2

G

+5VALW

12

R35
100K_0402_5%

13

D

Q5
BSS138_SOT23

S

10K_0402_5%

1 2

R30

Q7

2

2

1

C47

C45

0.01U_0402_16V7K

0.1U_0402_16V4Z

+3VS

S

G

D

1 3

1

2

4.7U_0805_10V4Z

80mil

AO3401L_SOT23

80mil

4.7U_0805_10V4Z

+LCDVDD

12

R34

2 2

GMCH_LVDDEN11

300_0402_5%

13

D

S

GMCH_LVDDEN

CRT CONNECTOR

3 3

CRT_R11

12

R4150_0402_1%

CRT_G11

CRT_B11

4 4

CRT_HSYNC11

SN74AHCT1G125DCKR_SC70-5

CRT_VSYNC11

12

R5150_0402_1%

12

R6150_0402_1%

C228

1 2

0.1U_0402_16V4Z

1 2

R9 39_0402_5%

1 2

R11 39_0402_5%

A

22P_0402_50V8J

1

C10

2

1

U1

1 2

4

OE#

0_0402_5%

C227

0.1U_0402_16V4Z

22P_0402_50V8J

R2

1 2

+CRT_VCC

5

P

A2Y

G

3

SN74AHCT1G125DCKR_SC70-5

1

2

C9

+CRT_VCC

5

1

P

A2Y

G

3

1 2

FCM2012C-800_0805

1 2

FCM2012C-800_0805

1 2

FCM2012C-800_0805

1

C8
22P_0402_50V8J

2

HSYNC#

1K_0402_5%

1 2

U2

1 2

4

OE#

R3 0_0402_5%

LVDS from NB

JP2

1

DISPOFF#
INVT_PWM
EDID_DAT EDID_CLK

C40

@

R217

1 2

2.2K_0402_5%

2

G

S

Title

Size Document Number Rev

Custom

Date: Sheet

1

3

3

5

5

7

7

9

9

11

11

13

13

15

15

17

17

19

19

21

21

23

23

25

25

27

27

29

29

31

31

33

33

35

35

37

37

39

39

2

1

JST_BM40B-SRDS-G-TFCLFSN~N

+3VS+CRT_VCC +3VS+CRT_VCC +3VS

R218

1 2

2.2K_0402_5%

Compal Electronics, Inc.

SCHEMATIC, M/B LA-3051P

401397

星期

, 06, 2005

四十月

41

2

2

4

4

GND

6

6

8

8

10

10

12

12

14

14

16

16

18

18

20

20

22

22

24

24

26

26

28

28

30

30

32

32

34

34

36

36

38

38

40

40

GND

42

D1

DAN217_SC59

1

2

0.1U_0603_50V4Z

12
12

68P_0402_50V8K

1

2

C43

0.1U_0402_16V4Z

DAN217_SC59

3

3VDDCDA 11

3VDDCCL 11

E

C44

C39

+3VS

D2

1

2

LVDSB1+ 11

LVDSB0- 11
LVDSB0+ 11

CRTHSYNC#
CRTVSYNC#

DAC_BRIG 32INVT_PWM32

LVDSB1- 11

LVDSB2- 11
LVDSB2+ 11

LVDSBC- 11
LVDSBC+ 11

+3VS

3

of

18 45

A

+3VS

5

4

3

2

1

R477 8.2K_0402_5%

1 2

R184 8.2K_0402_5%

1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2

1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2

R180 8.2K_0402_5%
R181 8.2K_0402_5%

D D

C C

R197 8.2K_0402_5%
R464 8.2K_0402_5%
R476 8.2K_0402_5%
R475 8.2K_0402_5%
R478 8.2K_0402_5%
R198 8.2K_0402_5%

+3VS

R461 8.2K_0402_5%
R462 8.2K_0402_5%
R485 8.2K_0402_5%
R486 8.2K_0402_5%
R179 8.2K_0402_5%
R195 8.2K_0402_5%
R465 8.2K_0402_5%
R178 8.2K_0402_5%
R463 8.2K_0402_5%
R479 8.2K_0402_5%
R480 8.2K_0402_5%
R487 8.2K_0402_5%

PCI_DEVSEL#
PCI_STOP#
PCI_TRDY#
PCI_FRAME#
PCI_PLOCK#
PCI_IRDY#
PCI_SERR#
PCI_PERR#
PCI_REQ4#
PCI_REQ3#

PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#
PCI_PIRQE#
PCI_PIRQF#
PCI_PIRQG#
PCI_PIRQH#
PCI_REQ0#
PCI_REQ1#
PCI_REQ2#
PCI_REQ5#

PCI_AD[0..31]28,32,43

PCI_PIRQA#28
PCI_PIRQB#28

PCI_PIRQD#

PCI_AD0
PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD6
PCI_AD7
PCI_AD8
PCI_AD9
PCI_AD10
PCI_AD11
PCI_AD12
PCI_AD13
PCI_AD14
PCI_AD15
PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20
PCI_AD21
PCI_AD22
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30
PCI_AD31

PCI_PIRQA#

PCI_PIRQB# PCI_PIRQF#
PCI_PIRQC#
PCI_PIRQD#

U19B

E18

AD0

C18

AD1

A16

AD2

F18

AD3

E16

AD4

A18

AD5

E17

AD6

A17

AD7

A15

AD8

C14

AD9

E14

AD10

D14

AD11

B12

AD12

C13

AD13

G15

AD14

G13

AD15

E12

AD16

C11

AD17

D11

AD18

A11

AD19

A10

AD20

F11

AD21

F10

AD22

E9

AD23

D9

AD24

B9

AD25

A8

AD26

A6

AD27

C7

AD28

B6

AD29

E6

AD30

D6

AD31

Interrupt I/F

A3

PIRQA#

B4

PIRQB#

C5

PIRQC#

B5

PIRQD#

AE5

RSVD[1]

AD5

RSVD[2]

AG4

RSVD[3]

AH4

RSVD[4]

AD9

RSVD[5]

ICH7_BGA652~D

PCI

REQ4# / GPIO22
GNT4# / GPIO48

GPIO1 / REQ5#

GPIO17 / GNT5#

GPIO2 / PIRQE#
GPIO3 / PIRQF#
GPIO4 / PIRQG#
GPIO5 / PIRQH#

MISC

MCH_SYNC#

REQ0#
GNT0#
REQ1#
GNT1#
REQ2#
GNT2#
REQ3#
GNT3#

C/BE0#
C/BE1#
C/BE2#
C/BE3#

IRDY#

PCIRST#

DEVSEL#

PERR#

PLOCK#

SERR#
STOP#
TRDY#

FRAME#

PLTRST#

PCICLK

PME#

RSVD[6]
RSVD[7]
RSVD[8]
RSVD[9]

PAR

D7
E7
C16
D16
C17
D17
E13
F13
A13
A14
C8
D8

B15
C12
D12
C15

A7
E10
B18
A12
C9
E11
B10
F15
F14
F16

C26
A9
B19

G8
F7
F8
G7

AE9
AG8
AH8
F21
AH20

PCI_REQ0#
PCI_REQ1#
PCI_REQ2#

PCI_GNT2#
PCI_REQ3#
PCI_GNT3#
PCI_REQ4#

PCI_REQ5#

PCI_CBE#0
PCI_CBE#1
PCI_CBE#2
PCI_CBE#3

PCI_IRDY#
PCI_PAR
PCI_PCIRST#
PCI_DEVSEL#
PCI_PERR#
PCI_PLOCK#
PCI_SERR#
PCI_STOP#
PCI_TRDY#
PCI_FRAME#

PCI_PLTRST#
CLK_PCI_ICH

PCI_PIRQE#
PCI_PIRQG#

PCI_PIRQH#

PCI_REQ2# 28
PCI_GNT2# 28
PCI_REQ3# 43
PCI_GNT3# 43

PCI_CBE#0 28,32,43
PCI_CBE#1 28,32,43
PCI_CBE#2 28,32,43
PCI_CBE#3 28,32,43

PCI_IRDY# 28,43
PCI_PAR 28,43

PCI_DEVSEL# 28,43
PCI_PERR# 28,43

PCI_SERR# 28,43
PCI_STOP# 28,43
PCI_TRDY# 28,32,43
PCI_FRAME# 28,32,43

CLK_PCI_ICH 17
EC_PME# 32

PCI_PIRQE# 28
PCI_PIRQF#
PCI_PIRQG# 28,43PCI_PIRQC#
PCI_PIRQH# 43

MCH_ICH_SYNC# 9

PCI_PCIRST#

PCI_PLTRST#

+3VS

5

U28

1

P

B

Y

2

A

G

TC7SH08FU_SSOP5@
R466
0_0402_5%

R471
0_0402_5%

3

12

+3VS

5

U29

1

P

B

Y

2

A

G

TC7SH08FU_SSOP5@

3

12

Place closely pin A9

CLK_PCI_ICH

R189

10_0402_5%@

1 2
1

C210

8.2P_0402_50V@

2

4

4

PCI_RST#

PLT_RST#

PCI_RST# 28,32,43

PLT_RST# 9,21,25,27,32

B B

+3VS

12

R388
100K_0402_5%@

14

U16A

P

VGATE21,32,42

A A

5

1

O2I

G

SN74LVC14APWR_TSSOP14~N@
R391

1M_0402_5%@

7

SN74LVC14APWR_TSSOP14~N@

12

14

U16B

P

3

O4I

G

7

R386

1 2

330K_0402_5%@

0.47U_0603_10V7K@

R381 0_0402_5%

12

4

C403

1

2

14

P

11

G

7

SN74LVC14APWR_TSSOP14~N@

NB_PWRGD 9

ICH_POK 21,23,32

U16E

O10I

+3VS

C407 0.1U_0402_16V4Z

14

U16F

P

13

O12I

G

SN74LVC14APWR_TSSOP14~N@

7

R389 0_0402_5%@

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

12

ICH_POK 21,23,32

2005/09/10 2006/06/23

Compal Secret Data

Deciphered Date

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, M/B LA-3051P

星期四 十月

401397

19 45, 06, 2005

1

of

A

5

+RTCVCC

12

R170
1M_0402_5%

D D

SM_INTRUDER#

32.768KHZ_12.5P_1TJS125BJ2A251

RTC Battery

-+

2

-

Place J1 close
to DDR-SODIMM

+RTCVCC

12

R172
332K_0402_1%

ICH_INTVRMEN

C C

+3VS

+3VS

B B

JRTC1
MAXELL_1220G

PUT JOPEN1 NEAR TO RAM DOOR

18P_0402_50V8J

18P_0402_50V8J

+RTCVCC

R16310K_0402_5%

12

R3834.7K_0402_5%

12

R3828.2K_0402_5%

12

C415

12

Y3

2
3

C412

12

+

BAT

SATA_LED#

IDE_DIORDY
IDE_IRQ

NC
NC

1

IN

OUT

+RTCBATT+RTCBATT

1
4

+RTCBATT

1

3

ACZ_BITCLK30

ACZ_SYNC30

ACZ_RST#30

ACZ_SDIN030
ACZ_SDIN130

ACZ_SDOUT30

SATA_LED#23

+RTCVCC

2

PSATA_IRX_DTX_N0_C23
PSATA_IRX_DTX_P0_C23

CLK_PCIE_SATA#17
CLK_PCIE_SATA17

4

ICH_RTCX1

R398

10M_0402_5%

ICH_RTCX2

R169
20K_0402_5%

1U_0603_10V6K
D34
BAS40-04_SOT23

+CHGRTC

IDE_DIORDY23

IDE_IRQ23

IDE_DDACK#23

IDE_DIOW#23
IDE_DIOR#23

12

1 2

C170

ACZ_SDIN0
ACZ_SDIN1

R414
39_0402_5%

SATA_LED#

ICH_RTCRST#

ICH_INTVRMEN
SM_INTRUDER#

1

1 2

2

R40939_0402_5%

1 2
1 2

R42439_0402_5%

1 2

R42039_0402_5%

1 2

PSATA_IRX_DTX_N0_C
PSATA_IRX_DTX_P0_C
PSATA_ITX_DRX_N0_C
PSATA_ITX_DRX_P0_C

CLK_PCIE_SATA#

CLK_PCIE_SATA

R380

1 2

24.9_0402_1%

IDE_DIORDY
IDE_IRQ
IDE_DDACK#
IDE_DIOW#

IDE_DIOR#

JOPEN1

@

ICH_ACZ_BITCLK
ICH_ACZSYNC#

ICH_ACZRST#

ICH_ACZSDOUT#

U19A

AB1
AB2

AA3

W4

Y5

W1

Y1
Y2

W3

V3
U3
U5

V4
T5

U7
V6
V7

U1
R6

R5
T2

T3
T1

T4

AF18

AF3
AE3
AG2
AH2

AF7
AE7
AG6
AH6

AF1
AE1

AH10
AG10

AG16
AH16
AF16
AH15
AF15

ICH7_BGA652~D

RTXC1
RTCX2

RTCRST#
INTVRMEN

INTRUDER#

EE_CS
EE_SHCLK
EE_DOUT
EE_DIN

LAN_CLK
LAN_RSTSYNC
LAN_RXD0

LAN_RXD1
LAN_RXD2

LAN_TXD0
LAN_TXD1
LAN_TXD2

ACZ_BCLK
ACZ_SYNC

ACZ_RST#
ACZ_SDIN0

ACZ_SDIN1
ACZ_SDIN2

ACZ_SDOUT

SATALED#

SATA0RXN
SATA0RXP
SATA0TXN
SATA0TXP

SATA2RXN
SATA2RXP
SATA2TXN
SATA2TXP

SATA_CLKN
SATA_CLKP

SATARBIASN
SATARBIASP

IORDY
IDEIRQ
DDACK#
DIOW#
DIOR#

3

RTC

GPIO49 / CPUPWRGD

IDE

LDRQ0#

LPCCPU

LDRQ1# / GPIO23

LFRAME#

LAN

A20GATE

A20M#

CPUSLP#

TP1 / DPRSTP#

TP2 / DPSLP#

FERR#

IGNNE#

INIT3_3V#

AC-97/AZALIA

RCIN#

STPCLK#

THERMTRIP#

DCS1#
DCS3#

SATA

DD10
DD11
DD12
DD13
DD14
DD15

DDREQ

LAD0
LAD1
LAD2
LAD3

INIT#

INTR

SMI#

DA0
DA1
DA2

DD0
DD1
DD2
DD3
DD4
DD5
DD6
DD7
DD8
DD9

NMI

AA6
AB5
AC4
Y6

AC3
AA5

AB3

AE22
AH28

AG27
AF24

AH25
AG26
AG24
AG22

AG21
AF22
AF25

AG23
AF23

AH24
AH22
AF26

AH17
AE17
AF17

AE16
AD16

AB15
AE14
AG13
AF13
AD14
AC13
AD12
AC12
AE12
AF12
AB13
AC14
AF14
AH13
AH14
AC15

AE15

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3

LPC_DRQ0#

LPC_FRAME#

GATEA20
H_A20M#

H_CPUSLP_R#
DPRSLP#

H_DPSLP#
H_FERR#
H_PWRGOOD
H_IGNNE#
H_INIT#

H_INTR

KB_RST#
H_SMI#

H_NMI
H_STPCLK#
THRMTRIP_ICH#

IDE_DA0
IDE_DA1
IDE_DA2

IDE_DCS1#
IDE_DCS3#

IDE_DD0
IDE_DD1
IDE_DD2
IDE_DD3
IDE_DD4
IDE_DD5
IDE_DD6
IDE_DD7
IDE_DD8
IDE_DD9
IDE_DD10
IDE_DD11
IDE_DD12
IDE_DD13
IDE_DD14
IDE_DD15

IDE_DDREQ

LPC_AD[0..3] 32

LPC_DRQ#0 32

LPC_FRAME# 32

12

GATEA20 32
H_A20M# 6

R160 0_0402_5%@

12
12

H_DPSLP# 6

12

H_FERR# 6
H_PWRGOOD 6
H_IGNNE# 6
H_INIT# 6

H_INTR 6

12

KB_RST# 32
H_SMI# 6

H_NMI 6
H_STPCLK# 6

IDE_DA0 23
IDE_DA1 23
IDE_DA2 23

IDE_DCS1# 23
IDE_DCS3# 23

IDE_DD[0..15]

IDE_DDREQ 23

R155 10K_0402_5%

R157 0_0402_5%

R156 10K_0402_5%

2

56_0402_5%
R158

IDE_DD[0..15] 23

+3VS

H_CPUSLP# 6,9
H_DPRSTP# 6,42

+VCCP

+VCCP

+3VS

12

R159

56_0402_5%

H_DPRSTP# daisy:

ICH7-M --> Yonah --> IMVP6

R165

1 2

24.9_0402_1%

@

H_THERMTRIP# 6,9

1

PSATA_ITX_DRX_N023

PSATA_ITX_DRX_P023

PSATA_ITX_DRX_N0

PSATA_ITX_DRX_P0

C408 3900P_0402_50V7K

C405 3900P_0402_50V7K

close ICH7

ICH_ACZSYNC#

R42339_0402_5%

ICH_ACZRST#

R41939_0402_5%

ICH_ACZSDOUT#

R41339_0402_5%

ICH_ACZ_BITCLK

R41039_0402_5%

2

1

1 2
1 2
1 2
1 2

C426

10P_0402_25V8K@

A A

MDC_ACZ_SYNC30

MDC_ACZ_RST#30

MDC_ACZ_SDOUT30

MDC_ACZ_BITCLK30

5

1 2

1 2

PSATA_ITX_DRX_N0_C

PSATA_ITX_DRX_P0_C

4

BATT1

ML1220 MAXELL LITHIUM RTC BATTERY

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2005/09/10 2006/06/23

3

Compal Secret Data

Deciphered Date

2

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, M/B LA-3051P

星期四

401397

06, 2005

十月

20 45,

1

of

A

5

+3VS

+3VALW

10K_0402_5%

1 2

8.2K_0402_5%

1 2

8.2K_0402_5%

10K_0402_5%

1 2

10K_0402_5%

1 2

10K_0402_5%@

1 2

10K_0402_5%

1 2

10K_0402_5%

1 2

10K_0402_5%

1 2

10K_0402_5%

1 2

SERIRQ

PCI_CLKRUN#
EC_THERM#

12

SMBALERT#

SYS_RST#

OCP#

SPI_MISO

SPI_CS#

WL_ON

SPI_MOSI

R457

10K_0402_5%

+3VALW

R469

1 2

1 2

R188

R190

R458
10K_0402_5%

1 2

10K_0402_5%

8.2K_0402_5%

1K_0402_5%

1 2

LINKALERT#

ICH_LOW_BAT#

12

ICH_PCIE_W AKE#

R133

R166
R164

D D

+3V

R192

R467

R193

R415

R173

R174

R176

C C

4

3

2

1

Place closely pin B2 P lace closely pin AC1

+3VALW

12

12

R468

R191

R470

1 2

8.2K_0402_5%

SB_SPKR31

R272 0_0402_5%

H_STP_PCI#17

ODD_EN#23
EC_SWI#32

SERIRQ28,32

VGATE19,32,42

EC_SMI#32

2.2K_0402_5%

T29PAD

1 2

ICH_SMBCLK
ICH_SMBDATA
LINKALERT#
ICH_SMLINK0
ICH_SMLINK1

ICH_RI#
SB_SPKR

SUS_STAT#

SYS_RST#
PM_BMBUSY#
SMBALERT#
H_STP_PCI#

H_STP_CPU#

PCI_CLKRUN#

ICH_PCIE_W AKE#

SERIRQ
EC_THERM#

VGATE

EC_SMI#

2.2K_0402_5%

ICH_SMBCLK17,26,27

ICH_SMBDATA17,26,27

+3V

ITP_DBRESET#6

PM_BMBUSY#9

H_STP_CPU#17

CLK_PCIE_LAN_EN17

PCI_CLKRUN#28,32,43

IDE_RESET#23

ICH_PCIE_WAKE#27

EC_THERM#

CLK_PCIE_ICH_EN17

U19C

C22

SMBCLK

B22

SMBDATA

A26

LINKALERT#

B25

SMLINK0

A25

SMLINK1

A28

RI#

A19

SPKR

A27

SUS_STAT#

A22

SYS_RST#

AB18

GPIO0 / BM_BUSY#

B23

GPIO11 / SMBALERT#

AC20

GPIO18 / STPPCI#

AF21

GPIO20 / STPCPU#

A21

GPIO26

B21

GPIO27

E23

GPIO28

AG18

GPIO32 / CLKRUN#

AC19

GPIO33 / AZ_DOCK_EN#

U2

GPIO34 / AZ_DOCK_RST#

F20

WAKE#

AH21

SERIRQ

AF20

THRM#

AD22

VRMPWRGD

AC21

GPIO6

AC18

GPIO7

E21

GPIO8

ICH7_BGA652~D

GPIO21 / SATA0GP

SMB

GPIO19 / SATA1GP
GPIO36 / SATA2GP
GPIO37 / SATA3GP

SATA

GPIO

SYS

Clocks

GPIO

GPIO16 / DPRSLPVR

TP0 / BATLOW#

POWER MGT

GPIO

GPIO35 / SATAREQ#

Need update symbol

CLK14
CLK48

SUSCLK
SLP_S3#

SLP_S4#
SLP_S5#

PWROK

PWRBTN#

LAN_RST#

RSMRST#

GPIO9
GPIO10
GPIO12
GPIO13
GPIO14
GPIO15
GPIO24
GPIO25

GPIO38
GPIO39

1 2

WL_ON
EC_FLASH#

12
12
12
12

CLK_14M_ICH 17
CLK_48M_ICH 17

T7 PA D

+3VS
+3VS
+3VS
+3VS

SLP_S3# 32
SLP_S4#

ICH_POK 19,23,32

1 2

DPRSLPVR 9,42

PBTN_OUT# 32

PLT_RST# 9,19,25,27,32

EC_RSMRST# 32

EC_SCI# 32

ACIN 32,35,39
BAY_ID1 23

EC_LID_OUT# 32

BAY_ID2 23

BAY_ID3 23
WL_ON
EC_FLASH# 33
SATACLKREQ# 17

R529 8.2K_0402_5%

AF19

R528 8.2K_0402_5%

AH18

R527 8.2K_0402_5%

AH19

R384 8.2K_0402_5%

AE19

CLK_14M_ICH

AC1

CLK_48M_ICH

B2

ICH_SUSCLK

C20

SLP_S3#

B24

SLP_S4#

D23

SLP_S5#_S SLP_S5#_S

F22

ICH_POK

AA4

DPRSLPVR

AC22

ICH_LOW_BAT#

C21

PBTN_OUT#

C23

PLT_RST#

C19

EC_RSMRST#

Y4

R171 10K_0402_5%

EC_SCI#

E20
A20
F19

EC_LID_OUT#

E19
R4
E22
R3
D20
AD21
AD20
AE20

12

R456

1

C494

2

R385
10K_0402_5%

10_0402_5%@

4.7P_0402_50V8C@

SLP_S4#

DPRSLPVR

+3VALW

R186
10K_0402_5%

@

1 2

PBTN_OUT#

CLK_14M_ICHCLK_48M_ICH

12

R168

10_0402_5%@

1

C162

4.7P_0402_50V8C@

2

+3VALW

5

U36

2

P

B

1

A

G

NC7SZ08P5X_NL_SC70-5

3

R154

100K_0402_5%@

4

Y

SLP_S5# 32

12

PCIE_RXN125
PCIE_RXP125
PCIE_TXN125

PCIE_TXP125

PCIE_RXN227
PCIE_RXP227
PCIE_TXN227

PCIE_TXP227

B B

A A

5

4

USB_OC#0
USB_OC#124
USB_OC#224
USB_OC#324
USB_OC#424
USB_OC#5
USB_OC#6
USB_OC#7

PCIE_RXN1
PCIE_RXP1
PCIE_C_TXN1

C4680.1U_0402_16V4Z

12

PCIE_C_TXP1

C4650.1U_0402_16V4Z

12

PCIE_RXN2
PCIE_RXP2
PCIE_C_TXN2

C4610.1U_0402_16V4Z

12

PCIE_C_TXP2

C4580.1U_0402_16V4Z

12

SPI_CS#

T3PAD

SPI_MOSI

T4PAD

SPI_MISO

T27PAD

USB_OC#0
USB_OC#1
USB_OC#2
USB_OC#3
USB_OC#4
USB_OC#5
USB_OC#6
USB_OC#7

U19D

F26

PERn1

F25

PERp1

E28

PETn1

E27

PETp1

H26

PERn2

H25

PERp2

G28

PETn2

G27

PETp2

K26

PERn3

K25

PERp3

J28

PETn3

J27

PETp3

M26

PERn4

M25

PERp4

L28

PETn4

L27

PETp4

P26

PERn5

P25

PERp5

N28

PETn5

N27

PETp5

T25

PERn6

T24

PERp6

R28

PETn6

R27

PETp6

R2

SPI_CLK

P6

SPI_CS#

P1

SPI_ARB

P5

SPI_MOSI

P2

SPI_MISO

D3

OC0#

C4

OC1#

D5

OC2#

D4

OC3#

E5

OC4#

C3

OC5# / GPIO29

A2

OC6# / GPIO30

B3

OC7# / GPIO31

ICH7_BGA652~D

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

DMI0RXN

DMI0RXP
DMI0TXN
DMI0TXP

DMI1RXN

DMI1RXP
DMI1TXN
DMI1TXP

PCI-EXPRESS

DMI2RXN

DMI2RXP
DMI2TXN
DMI2TXP

DMI3RXN

DMI3RXP
DMI3TXN
DMI3TXP

DMI_CLKN

DMI_CLKP

DIRECT MEDIA INTERFACE

DMI_ZCOMP

DMI_IRCOMP

USBP0N
USBP0P
USBP1N
USBP1P
USBP2N

SPI

USBP2P
USBP3N
USBP3P
USBP4N
USBP4P
USBP5N
USBP5P

USB

USBP6N
USBP6P
USBP7N
USBP7P

USBRBIAS#

USBRBIAS

2005/09/10 2006/06/23

DMI_RXN0

V26

DMI_RXP0

V25

DMI_TXN0

U28

DMI_TXP0

U27

DMI_RXN1

Y26

DMI_RXP1

Y25

DMI_TXN1

W28

DMI_TXP1

W27

DMI_RXN2

AB26

DMI_RXP2

AB25

DMI_TXN2

AA28

DMI_TXP2

AA27

DMI_RXN3

AD25

DMI_RXP3

AD24

DMI_TXN3

AC28

DMI_TXP3

AC27

CLK_PCIE_ICH#

AE28

CLK_PCIE_ICH

AE27
C25

DMI_IRCOMP

D25

USB20_N0

F1

USB20_P0

F2

USB20_N1

G4

USB20_P1

G3

USB20_N2

H1

USB20_P2

H2

USB20_N3

J4

USB20_P3

J3

USB20_N4

K1

USB20_P4

K2

USB20_N5

L4

USB20_P5

L5

USB20_N6

M1

USB20_P6

M2

USB20_N7

N4

USB20_P7

N3

USBRBIAS

D2
D1

Compal Secret Data

Deciphered Date

DMI_RXN0 9
DMI_RXP0 9
DMI_TXN0 9
DMI_TXP0 9

DMI_RXN1 9
DMI_RXP1 9
DMI_TXN1 9
DMI_TXP1 9

DMI_RXN2 9
DMI_RXP2 9
DMI_TXN2 9
DMI_TXP2 9

DMI_RXN3 9
DMI_RXP3 9
DMI_TXN3 9
DMI_TXP3 9

CLK_PCIE_ICH# 17
CLK_PCIE_ICH 17

R185 24.9_0402_1%

1 2

USB20_N0 24
USB20_P0 24
USB20_N1 24
USB20_P1 24
USB20_N2 24
USB20_P2 24
USB20_N3 24
USB20_P3 24
USB20_N4 24
USB20_P4 24
USB20_N5 27
USB20_P5 27
USB20_N6 24
USB20_P6 24
USB20_N7
USB20_P7

R435 22.6_0402_1%

1 2

Within 500 mils

2

Within 500 mils

+1.5VS

USB_OC#6
USB_OC#7
USB_OC#5
USB_OC#1

USB_OC#2
USB_OC#0
USB_OC#3
USB_OC#4

Title

Size Document Number Rev

Custom

Date: Sheet

R450

4 5
3 6
2 7
1 8

10K_1206_8P4R_5%

RP44

4 5
3 6
2 7
1 8

10K_1206_8P4R_5%

+3VALW

+3VALW

Compal Electronics, Inc.

SCHEMATIC, M/B LA-3051P

401397

星期四 十月

21 45, 06, 2005

1

of

A

R376

100_0402_5%

R177

10_0402_5%

12

12

+3VS+5VS

21

1

2

+3VALW+5VALW

21

1

2

D30
CH751H-40_SC76

ICH_V5REF_RUN

C165

0.1U_0402_16V4Z

D15
CH751H-40_SC76

ICH_V5REF_SUS

C194

0.1U_0402_16V4Z

+1.5VS

+1.5VS

Place closely pin AG28 within 100mlis.

+1.5VS_DMIPLLR

R153

1 2

0.5_0805_1%

0.1U_0402_16V4Z

+1.5VS

+3VALW

1 2

10U_0805_10V4Z~N

1

C161

2

C195

R152

0_0805_5%

+3VS

0.1U_0402_16V4Z

1

+1.5VS

2

0.1U_0402_16V4Z

C160

1

2

C197

1

+

C190

C427

2

220U_D2_4VM

0.1U_0402_16V4Z

+1.5VS_DMIPLL

1

C158

2

1

C159

2

0.1U_0402_16V4Z

1

2

0.01U_0402_16V7K

ICH_V5REF_RUN

ICH_V5REF_SUS

0.1U_0402_16V4Z

1

1

C182

2

0.1U_0402_16V4Z

+3VS

C203

+1.5VS_DMIPLL

C168

1

2

1

2

1

2

C172

2

Place closely pin
D28,T28,AD28.

0.1U_0402_16V4Z

+1.5VS

0.1U_0402_16V4Z

Place closely pin AG5.

+1.5VS

1U_0603_10V4Z

C169

1

2

Place closely pin AG9.

+3VALW

ICH_AA2

ICH_Y7

T1 PA D
T2 PA D

G10

AD17

F6

AA22
AA23
AB22
AB23
AC23
AC24
AC25
AC26
AD26
AD27
AD28

D26
D27
D28

E24
E25
E26
F23

F24
G22
G23
H22
H23

J22

J23
K22
K23
L22
L23

M22
M23
N22
N23

P22
P23

R22
R23
R24
R25
R26

T22
T23
T26
T27
T28

U22
U23

V22
V23

W22
W23

Y22
Y23

B27

AG28

AB7
AC6
AC7
AD6
AE6
AF5
AF6
AG5
AH5

AD2
AH11
AB10

AB9
AC10
AD10
AE10
AF10

AF9

AG9

AH9

E3
C1

AA2

Y7
V5

V1
W2
W7

1

C174

0.1U_0402_16V4Z

2

U19F

V5REF[1]
V5REF[2]
V5REF_Sus
Vcc1_5_B[1]

Vcc1_5_B[2]
Vcc1_5_B[3]
Vcc1_5_B[4]
Vcc1_5_B[5]
Vcc1_5_B[6]
Vcc1_5_B[7]
Vcc1_5_B[8]
Vcc1_5_B[9]
Vcc1_5_B[10]
Vcc1_5_B[11]
Vcc1_5_B[12]
Vcc1_5_B[13]
Vcc1_5_B[14]
Vcc1_5_B[15]
Vcc1_5_B[16]
Vcc1_5_B[17]
Vcc1_5_B[18]
Vcc1_5_B[19]
Vcc1_5_B[20]
Vcc1_5_B[21]
Vcc1_5_B[22]
Vcc1_5_B[23]
Vcc1_5_B[24]
Vcc1_5_B[25]
Vcc1_5_B[26]
Vcc1_5_B[27]
Vcc1_5_B[28]
Vcc1_5_B[29]
Vcc1_5_B[30]
Vcc1_5_B[31]
Vcc1_5_B[32]
Vcc1_5_B[33]
Vcc1_5_B[34]
Vcc1_5_B[35]
Vcc1_5_B[36]
Vcc1_5_B[37]
Vcc1_5_B[38]
Vcc1_5_B[39]
Vcc1_5_B[40]
Vcc1_5_B[41]
Vcc1_5_B[42]
Vcc1_5_B[43]
Vcc1_5_B[44]
Vcc1_5_B[45]
Vcc1_5_B[46]
Vcc1_5_B[47]
Vcc1_5_B[48]
Vcc1_5_B[49]
Vcc1_5_B[50]
Vcc1_5_B[51]
Vcc1_5_B[52]
Vcc1_5_B[53]

Vcc3_3[1]
VccDMIPLL
Vcc1_5_A[1]

Vcc1_5_A[2]
Vcc1_5_A[3]
Vcc1_5_A[4]
Vcc1_5_A[5]
Vcc1_5_A[6]
Vcc1_5_A[7]
Vcc1_5_A[8]
Vcc1_5_A[9]

VccSATAPLL
Vcc3_3[2]
Vcc1_5_A[10]

Vcc1_5_A[11]
Vcc1_5_A[12]
Vcc1_5_A[13]
Vcc1_5_A[14]
Vcc1_5_A[15]
Vcc1_5_A[16]
Vcc1_5_A[17]
Vcc1_5_A[18]

VccSus3_3[19]
VccUSBPLL
VccSus1_05/VccLAN1_05[1]

VccSus1_05/VccLAN1_05[2]
VccSus3_3/VccLAN3_3[1]

VccSus3_3/VccLAN3_3[2]
VccSus3_3/VccLAN3_3[3]
VccSus3_3/VccLAN3_3[4]

ICH7_BGA652~D

Vcc1_05[1]
Vcc1_05[2]
Vcc1_05[3]
Vcc1_05[4]
Vcc1_05[5]
Vcc1_05[6]
Vcc1_05[7]
Vcc1_05[8]

Vcc1_05[9]
Vcc1_05[10]
Vcc1_05[11]
Vcc1_05[12]
Vcc1_05[13]
Vcc1_05[14]
Vcc1_05[15]
Vcc1_05[16]
Vcc1_05[17]
Vcc1_05[18]
Vcc1_05[19]
Vcc1_05[20]

Vcc3_3 / VccHDA

VccSus3_3/VccSusHDA

V_CPU_IO[1]
V_CPU_IO[2]
V_CPU_IO[3]

Vcc3_3[3]
Vcc3_3[4]
Vcc3_3[5]
Vcc3_3[6]
Vcc3_3[7]
Vcc3_3[8]

Vcc3_3[9]
Vcc3_3[10]
Vcc3_3[11]

Vcc3_3[12]
Vcc3_3[13]
Vcc3_3[14]
Vcc3_3[15]
Vcc3_3[16]
Vcc3_3[17]
Vcc3_3[18]
Vcc3_3[19]
Vcc3_3[20]
Vcc3_3[21]

VccRTC
VccSus3_3[1]
VccSus3_3[2]

VccSus3_3[3]
VccSus3_3[4]
VccSus3_3[5]
VccSus3_3[6]

VccSus3_3[7]
VccSus3_3[8]
VccSus3_3[9]

VccSus3_3[10]
VccSus3_3[11]
VccSus3_3[12]
VccSus3_3[13]
VccSus3_3[14]
VccSus3_3[15]
VccSus3_3[16]
VccSus3_3[17]
VccSus3_3[18]

Vcc1_5_A[19]
Vcc1_5_A[20]

Vcc1_5_A[21]
Vcc1_5_A[22]
Vcc1_5_A[23]

Vcc1_5_A[24]

Vcc1_5_A[25]
VccSus1_05[1]
VccSus1_05[2]

VccSus1_05[3]

Vcc1_5_A[26]

Vcc1_5_A[27]

Vcc1_5_A[28]

Vcc1_5_A[29]

Vcc1_5_A[30]

L11
L12
L14
L16
L17
L18
M11
M18
P11
P18
T11
T18
U11
U18
V11
V12
V14
V16
V17
V18

U6
R7
AE23

AE26
AH26

AA7
AB12
AB20
AC16
AD13
AD18
AG12
AG15
AG19

A5
B13
B16
B7
C10
D15
F9
G11
G12
G16

W5
P7
A24

C24
D19
D22
G19

K3
K4
K5
K6
L1
L2
L3
L6
L7
M6
M7
N7

AB17
AC17

T7
F17
G17

AB8
AC8

K7
C28

G20
A1

H6
H7
J6
J7

+VCCP

0.1U_0402_16V4Z

1

C183

C186

2

1U_0603_10V4Z

1

C196

2

0.1U_0402_16V4Z

1

C187

0.1U_0402_16V4Z

2

1

C189

0.1U_0402_16V4Z

2

+1.5VS

1 2

C193 0.1U_0402_16V4Z

ICH_K7
ICH_C28

ICH_G20

+1.5VS

1

C192

0.1U_0402_16V4Z

2

1

2

+3VALW

+3VS

1

C166

0.1U_0402_16V4Z

2

1

1

C164

2

2

0.1U_0402_16V4Z

1

C191

0.1U_0402_16V4Z

2

1

C173

0.1U_0402_16V4Z

2

1

+

C401
220U_D2_4VM

2

C201

0.1U_0402_16V4Z

T5PAD
T28PAD

T6PAD

+VCCP

+3VS

+3VALW

+3VALW

C177

1 2

0.1U_0402_16V4Z

1 2

C179

0.1U_0402_16V4Z

1 2

C188

4.7U_0805_10V4Z

C175

0.1U_0402_16V4Z

U19E

A4

VSS[0]

A23

VSS[1]

B1

VSS[2]

B8

VSS[3]

B11

VSS[4]

B14

VSS[5]

B17

VSS[6]

B20

VSS[7]

B26

VSS[8]

B28

VSS[9]

C2

VSS[10]

C6

VSS[11]

C27

VSS[12]

D10

VSS[13]

D13

VSS[14]

D18

VSS[15]

D21

VSS[16]

D24

VSS[17]

E1

VSS[18]

E2

VSS[19]

E4

VSS[21]

E8

VSS[22]

+3VS

1

C178

0.1U_0402_16V4Z

2

+RTCVCC

1

1

C176

2

2

0.1U_0402_16V4Z

E15

F3
F4

F5
F12
F27
F28

G1

G2

G5

G6

G9

G14
G18
G21
G24
G25
G26

H3

H4

H5
H24
H27
H28

J1
J2

J5
J24
J25
J26

K24
K27
K28
L13
L15
L24
L25
L26

M3
M4
M5

M12
M13
M14
M15
M16
M17
M24
M27
M28

N1
N2
N5

N6
N11
N12
N13
N14
N15
N16
N17
N18
N24
N25
N26

P3

P4
P12
P13
P14
P15
P16
P17
P24
P27

ICH7_BGA652~D

VSS[23]
VSS[24]
VSS[25]
VSS[26]
VSS[27]
VSS[28]
VSS[29]
VSS[30]
VSS[31]
VSS[32]
VSS[33]
VSS[34]
VSS[35]
VSS[36]
VSS[37]
VSS[38]
VSS[39]
VSS[40]
VSS[41]
VSS[42]
VSS[43]
VSS[44]
VSS[45]
VSS[46]
VSS[47]
VSS[48]
VSS[49]
VSS[50]
VSS[51]
VSS[52]
VSS[53]
VSS[54]
VSS[55]
VSS[56]
VSS[57]
VSS[58]
VSS[59]
VSS[60]
VSS[61]
VSS[62]
VSS[63]
VSS[64]
VSS[65]
VSS[66]
VSS[67]
VSS[68]
VSS[69]
VSS[70]
VSS[71]
VSS[72]
VSS[73]
VSS[74]
VSS[75]
VSS[76]
VSS[77]
VSS[78]
VSS[79]
VSS[80]
VSS[81]
VSS[82]
VSS[83]
VSS[84]
VSS[85]
VSS[86]
VSS[87]
VSS[88]
VSS[89]
VSS[90]
VSS[91]
VSS[92]
VSS[93]
VSS[94]
VSS[95]
VSS[96]
VSS[97]

VSS[98]

VSS[99]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
VSS[159]
VSS[160]
VSS[161]
VSS[162]
VSS[163]
VSS[164]
VSS[165]
VSS[166]
VSS[167]
VSS[168]
VSS[169]
VSS[170]
VSS[171]
VSS[172]
VSS[173]
VSS[174]
VSS[175]
VSS[176]
VSS[177]
VSS[178]
VSS[179]
VSS[180]
VSS[181]
VSS[182]
VSS[183]
VSS[184]
VSS[185]
VSS[186]
VSS[187]
VSS[188]
VSS[189]
VSS[190]
VSS[191]
VSS[192]
VSS[193]
VSS[194]

P28
R1
R11
R12
R13
R14
R15
R16
R17
R18
T6
T12
T13
T14
T15
T16
T17
U4
U12
U13
U14
U15
U16
U17
U24
U25
U26
V2
V13
V15
V24
V27
V28
W6
W24
W25
W26
Y3
Y24
Y27
Y28
AA1
AA24
AA25
AA26
AB4
AB6
AB11
AB14
AB16
AB19
AB21
AB24
AB27
AB28
AC2
AC5
AC9
AC11
AD1
AD3
AD4
AD7
AD8
AD11
AD15
AD19
AD23
AE2
AE4
AE8
AE11
AE13
AE18
AE21
AE24
AE25
AF2
AF4
AF8
AF11
AF27
AF28
AG1
AG3
AG7
AG11
AG14
AG17
AG20
AG25
AH1
AH3
AH7
AH12
AH23
AH27

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2005/09/10 2006/06/23

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom
Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, M/B LA-3051P

401397

星期四 十月

05

22 45, 06, 20

of

A

+5VS +5VS

0.1U_0402_16V4Z

C152

1

1

C153

2

2

22U_1210_10V4Z

1000P_0402_50V7K~N

Pleace near HD CONN

PSATA_IRX_DTX_N0_C20

PSATA_IRX_DTX_P0_C20

1

C154

2

1U_0603_10V4Z

C200

3900P_0402_50V7K

C198

3900P_0402_50V7K

1

C150

2

close SATA connector

+3VS

5

SATA_LED#20

SATA_LED#
ODD_LED#

U4

2

P

B

1

A

G

NC7SZ08P5X_NL_SC70-5

3

Y

1

C155

2

0.1U_0402_16V4Z

PSATA_ITX_DRX_P020
PSATA_ITX_DRX_N020

12

12

+5VHDD

4

IDE_LED# 33

+3VS

1

C441

2

22U_1210_10V4Z

PSATA_ITX_DRX_P0
PSATA_ITX_DRX_N0

PSATA_IRX_DTX_N0

PSATA_IRX_DTX_P0

0.1U_0402_16V4Z

1

C443

1

2

1000P_0402_50V7K~N

C442

2

Pleace near HD CONN

JP9

1

GND

2

A+

3

A-

4

GND

5

B-

6

B+

7

GND

8

V33

9

V33

10

V33

11

GND

12

GND

13

GND

14

V5

15

V5

16

V5

17

GND

18

Reserved

19

GND

20

V12

21

V12

22

V12

SUYIN_127059FR022S305ZL

Main HDD

Need update symbol

Main SATA +5V Default

1

C435

2

1U_0603_10V4Z

HDD CONNECTOR

1

C423

2

0.1U_0402_16V4Z

G-SENSOR

1

C387

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

MOTION
F_FALL

1

1

C384

C386

2

2

0.1U_0402_16V4Z

1
2
3
4
5
6

1

C382

0.1U_0402_16V4Z

2

U12

GND
VDD
MOTION

SCL/SCLK

SDA/SDO

FF
Output X

ADDR0/SDI
Output Z
Output Y7RESET

KXP84-0200_DFN14

MOTION

2 1

D12

CH751H-40_SC76

F_FALL

2 1

D11

CH751H-40_SC76

IO VDD

14

NC

13
12
11
10
9

CS#

8

ODD_EN#21

ICH_POK19,21,32

+3VS+3VS

EC_SMB_CK2 6,10,32,37

R320 10K_0402_5%

1 2

EC_SMB_DA2 6,10,32,37

1 2

1 2

C381 10U_0805_10V4Z~N

R313

8.2K_0402_5%

12

R103
100K_0402_5%

1 2

R531
0_0402_5%

+3VS

GSENSOR 32

+3V

2

B

1

A

5

U35

P

4

Y

G

NC7SZ08P5X_NL_SC70-5

3

@

+5VS

B+_BIAS

12

R401
470K_0402_5%

13

D

Q28

12

R364
470K_0402_5%

13

D

Q22
2N7002_SOT23

S

2

2N7002_SOT23

G

S

Placea caps. near HDD

+5VHDD

CONN.

1000P_0402_50V7K~N

C180

10U_0805_10V4Z~N

+5VS

1

C163

2

D

6
2

1

HDD_EN#32

B+_BIAS

2

G

D

6

S

45
2
1

G

3

1

C438

0.1U_0603_50V4Z

2

10U_0805_10V4Z~N

1

C171

2

Q15

S

+5VS_ODD

45

SI3456BDV-T1-E3_TSOP6

G

3

1

C394

0.1U_0603_50V4Z

2

Q29

+5VS_HDD

SI3456BDV-T1-E3_TSOP6

2A_8VDC_SMD1812P200TF

0.1U_0402_16V4Z

1

C185

2

1U_0603_10V4Z

F2

3A_15VDC_SMD2920P300TF/15

F6

0.1U_0402_16V4Z

+5VHDD

21

C181

+5VODD

21

C146

12

1

R121
100K_0402_5%

2

+5VODD

1 2

R89 10K_0402_5%@

R298 5.6K_0603_1%@

1000P_0402_50V7K~N

C360

4.7U_0805_10V4Z

Place component's closely MODULE CONNECTOR.

+3VS

R84

@

4.7K_0402_5%

1 2

12

JODD1

STORAGE

USB

TVPOWER12

TYCO_1827257-1~N

CONN@

IDE_DD[0..1 5]

VBPOWER
VBPOWER
VBPOWER
VBPOWER
VBPOWER
VBPOWER

BAYDET1

BAYID1
BAYID2
BAYID3

AUXR
AUXL

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

AGND
AGND
AGND
AGND

TVPOWER5

VBPOWER
VBPOWER

GND
GND
GND
GND
GND
GND
GND
GND

A1
A2
B1
B2
A28
B28

B22
B21
A21
A20

A25
B25

A22

NC

A11
B11
A23
B23
A27
B27
A29
B29
A30
B30

A24
B24
A26
B26

D1
C3

C1
C2

C6
C8
C10
D6
D7
D8
D9
D10

+5VODD

R294

10K_0402_5%

BAY_TYPE
BAY_ID1
BAY_ID2
BAY_ID3

1

2

1

C120
1000P_0402_50V7K~N

1

2

2

C117
1000P_0402_50V7K~N

+3VS

R296
10K_0402_5%

12

12

12

12

R82

10K_0402_5%

R81 10K_0402_5%

C119
1000P_0402_50V7K~N

Security Classification

Issued Date

THIS SHEET OF ENGI NEERING DRAWING IS T HE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZ ED BY COMPAL EL ECTRONICS, IN C. NEITHER TH IS SHEET NOR TH E INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WI THOUT PRIOR W RITTEN CONSEN T OF COMPAL EL ECTRONICS, IN C.

BAY_TYPE 32
BAY_ID1 21
BAY_ID2 21
BAY_ID3 21

IDE_DIORDY20

2005/09/10 2006/06/23

Compal Secret Data

R85 0_0402_5%

Deciphered Date

1 2

IDE_DD[0..15]20

IDE_DD10 PD_D10
IDE_DD3 PD_D3
IDE_DD12 PD_D12

IDE_DD9 PD_D9
IDE_DD1 PD_D1
IDE_DD6 PD_D6
IDE_DD7 PD_D7

IDE_DIOW#20
IDE_DIOR#20

IDE_DA020
IDE_DA120

IDE_DCS1#20

IDE_DDACK#20

IDE_DDREQ20

IDE_DCS3#20

IDE_DA220

IDE_IRQ20

IDE_DA0 PD_PDA0
IDE_DA1 PD_PDA1

IDE_DCS1#
IDE_DD2 PD_D2

IDE_DD13 PD_D13
IDE_DD15 PD_D15

IDE_DDACK# PD_PDDACK#
IDE_DDREQ PD_PDDREQ
IDE_DCS3# PD_PDCS3#
IDE_DA2 PD_PDA2

IDE_DD8 PD_D8

INT_IRQ15

1 8
2 7
3 6
4 5

RP40 0_1206_8P4R_5%

1 8
2 7
3 6
4 5

RP39 0_1206_8P4R_5%

1 8
2 7
3 6
4 5

RP33 0_1206_8P4R_5%

1 8
2 7
3 6
4 5

RP38 0_1206_8P4R_5%

1 8
2 7
3 6
4 5

RP41 0_1206_8P4R_5%

1 8
2 7
3 6
4 5

RP37 0_1206_8P4R_5%

1 2

R303 0_0402_5%

1 2

R86 0_0402_5%

PD_D5IDE _DD5

PD_PDIOW#IDE_DIOW#
PD_PDIOR#ID E_DIOR#

PD_PDCS1#
PD_D0IDE _DD0

PD_D4IDE _DD4

PD_D11IDE_DD11

PD_D14IDE_DD14

PD_IRQ15

1 2

R87 8.2K_0402_5%

@

CSE- H: Master, L/NC:Slave

+5VS

IDE_RESET#21

RB751V_SOD323

1 2

R88

R293

10K_0402_5%

D23

8.2K_0402_5%

+3VS

12

21

PD_D0
PD_D1
PD_D2
PD_D3
PD_D4
PD_D5
PD_D6
PD_D7
PD_D8
PD_D9
PD_D10
PD_D11
PD_D12
PD_D13
PD_D14
PD_D15

12

R300 470_0805_5%

PD_PDCS1#
PD_PDCS3#

PD_PDA0
PD_PDA1
PD_PDA2

ODD_LED#
PD_IRQ15

PD_PDIORDY
PD_PDIOR#
PD_PDIOW#

PD_PDDACK#
PD_PDDREQ

B10

HD00

A10

HD01

B9

HD02

A9

HD03

B8

HD04

A8

HD05

B7

HD06

A7

HD07

B6

HD08

A6

HD09

B5

HD10

A5

HD11

B4

HD12

A4

HD13

B3

HD14

A3

HD15

B15

CSEL

B14

CSEL#

A13

CS0

B12

CS1

A14

SA0

A15

SA1

B13

SA2

A12

DASP

A16

IRQ

B16

PDIAG

A17

IOCHRDY

A18

IOR

A19

IOW

B17

IOCS16

B18

DMACK

B19

DMARQ

B20

RESET#

D2

USBDET1

C7

USBP0+

C9

USBP0-

C4

NC

C5

NC

D3

NC

D4

NC

D5

NC

1U_0603_10V4Z

1

C377

PD_PDIORDY

PD_D7

PD_PDDREQ

BAY TYPE- 0:Storage Device
1:2nd BATT or No pack

MODE BAY_ID3/2/1

Not Used

CD-ROM
CD-RW
Combo
DVD-ROM
DVD-RAM
2nd HDD

Reserved

C376

2

0.1U_0402_16V4Z

Compal Electronics, Inc.

Title

SCHEMATIC, M/B LA-3051P

Size Document Number Rev

薔十月

Date: Sheet

4.7U_0805_10V4Z

C361

000
001
010
011
100
101
110
111 IDE

401397

C379

IDE
IDE
IDE
IDE
IDE
IDE

A

of

23 45星|, 06, 2005

80 mils

1

C245

0.1U_0402_16V4Z

2

80 mils

1

C35

0.1U_0402_16V4Z

2

80 mils

1

C411

0.1U_0402_16V4Z

2

+USB_BS=60 mils

+USB_AS+5VS

U10

1

GND

2

IN

3

SUSP34,41

SUSP

SUSP

SUSP

IN

4

EN#

TPS2061DGNG4_MSOP8~N

U5

1

GND

2

IN

3

IN

4

EN#

TPS2061DGNG4_MSOP8~N

U18

1

GND

2

IN

3

IN

4

EN#

TPS2061DGNG4_MSOP8~N

OUT
OUT
OUT

OUT
OUT
OUT

OUT
OUT
OUT

OC#

OC#

OC#

8
7
6
5

+USB_BS+5VS

8
7
6
5

+USB_CS+5VS

8
7
6
5

R14 0_0402_5%
R15 0_0402_5%

R26 0_0402_5%

R406 0_0402_5%

1

+

C234
150U_D2_6.3VM

2

1 2
1 2

1 2

1 2

0.1U_0402_16V4Z

C15

1

+

C42
150U_D2_6.3VM

2

1

+

C417

150U_D2_6.3VM

2

USB_OC#2 21
USB_OC#1 21

SUSP

USB_OC#4 21

SUSP

USB_OC#3 21

SUSP

12

R16
30K_0402_5%

13

D

Q2

2

2N7002_SOT23

G

S

0.1U_0402_16V4Z

C41

2

G

0.1U_0402_16V4Z

C413

2

G

USB20_N221
USB20_P221

12

R29
30K_0402_5%

13

D

Q4
2N7002_SOT23

S

12

R405
30K_0402_5%

13

D

Q30
2N7002_SOT23

S

+USB_AS

4

5

CH4
CH11Vn2CH2

+USB_AS

4

5

CH4
CH11Vn2CH2

USB_P2+USB_P2-

6

D3

Vp

NUP4301MR6T1_TSOP6

CH3

3

USB_P1-USB_P1+

6

D21

Vp

NUP4301MR6T1_TSOP6

CH3

3

L6 WCM2012F2S-900T04_0805@

4

4

1

1

R13 0_0402_5%
R12 0_0402_5%

+USB_CS +USB_BS

4

CH4
CH11Vn2CH2

3

2

12
12

USB_P3-USB_P3+ USB_P4-USB_P4+

6

5

D14

Vp

NUP4301MR6T1_TSOP6

CH3

3

3

2

@

2.2P_0402_50V8C

USB_P2­USB_P2+

C13

C12

@

2.2P_0402_50V8C

USB20_N321
USB20_P321

USB20_N421
USB20_P421

4

5

Vp

CH4
CH11Vn2CH2

JUSBP1

1

VCC

2

D0-

3

D0+

4

VSS
G210G1

12

SUYIN_020122MR008G570ZL~N

CONN@

1

4

L25 WCM2012F2S-900T04_0805@

1

4

6

D22
NUP4301MR6T1_TSOP6

CH3

3

USB20_N021

USB20_P021

BT_ACTIVE
WL_OFF#27,32,33,43

BT_CHCLK27,43

WL_ACTIVE27,43

1 2

+3VS

L16

BLM11A601S_0603

5

VCC

USB_P1-

6

D1-

USB_P1+

7

D1+

8

VSS

9

G311G4

C232

@

2.2P_0402_50V8C

L28 WCM2012F2S-900T04_0805@

1

4

R393 0_0402_5%
R395 0_0402_5%

1

4

R252 0_0402_5%
R251 0_0402_5%

BT_EXIST#32

USB20_N621
USB20_P621

2

2

3

3

12
12

2

2

3

3

12
12

+5VS

+3VS_BT BT_PWR

1

F3 1.1A_6VDC_FUSE

C224

0.1U_0402_16V4Z

2

2

2

3

3

L19 WCM2012F2S-900T04_0805@
R226 0_0402_5%
R225 0_0402_5%

C233

@

2.2P_0402_50V8C

1

C409

@

2

2.2P_0402_50V8C

1

C276

@

2

2.2P_0402_50V8C

FINGERPRINT

F5 1.1A_6VDC_FUSE

+5VS_FP

21

BLUETOOTH

200mA

21

1

4

12
12

+USB_CS

USB_P3-

USB_P3+

1

C410

@
2

2.2P_0402_50V8C

+USB_BS

USB_P4­USB_P4+

1

C275

@
2

2.2P_0402_50V8C

JP7

1

1

2

2

3

3

4

4

JST_BM04B-SRSS~N

JP13

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

ACES_87151-2007L~N

1

4

JUSBP3

1
2
3
4

SUYIN_020133MR004S551ZL~N

JUSBP2

1
2
3
4

SUYIN_020133MR004S529ZL~N

USB20_N1 21
USB20_P1 21

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2005/09/10 2006/06/23

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, M/B LA-3051P

星期四 十月

401397

24 45, 06, 2005

of

A

5

4

3

2

1

MMJT9435

C

Layout Notice : Place as close
chip as possible.

Q3

+3VALW

D D

EN_WOL34

D

6
2

1

G

3

L24
FBM-L11-321611-260-LMT_1206

S

+3V_LAN

45

SI3456BDV-T1-E3_TSOP6

1 2

2

C266

C243

C264

1

4.7U_0805_10V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

+3VLAN

2

2

1

@

2

C251

C263

1

1

@

0.1U_0402_16V4Z

0.1U_0402_16V4Z

+3VLAN

R_CLK_PCI_LAN
R_LPC_AD0
R_LPC_AD1
R_LPC_AD2
R_LPC_AD3
R_LPC_FRAME#
R_PLT_RST#
R_SIRQ

1 2

R239

@

4.7K_0402_5%

1 2

@

5751_SI
SCLK
5751_SO

CS#

GPIO1

GPIO2

XTALI
XTALO

R231

1 2

4.7K_0402_5%

2

1

5

R_CLK_PCI_LAN
R_LPC_AD0
R_LPC_AD1
R_LPC_AD2

R_LPC_AD3
R_LPC_FRAME#
R_PLT_RST#
R_SIRQ

R232
0_0402_5%

GPIO1
GPIO2

@

R230

XTALO

XTALI

C272

27P_0402_50V8J

U3A

K10

LCLK

M11

LAD0

L11

LAD1

K9

LAD2

L5

LAD3

H11

LFRAME

M9

LRESET

L8

SERIRQ

L9

EXPORT

J11

BSAFE_GPIO0

N13

BSAFE_GPIO1

G12

GPIO0_TST_CLKOUT

H13

GPIO1

G13

GPIO2

D10

SMB_CLK

D9

SMB_DATA

K11

EECLK

L10

EEDATA

E12

SI

E11

SCLK

F11

SO

C12

CS

H2

PWR_IND

J2

ATTN_IND

A2

ATTN_BTTN

A11

LINKLED

B11

SPD100LED

A12

SPD1000LED

B10

TRAFFICLED

A9

WL_ACTIVITY

B9

WL_LINK5G

C10

WL_LINK2.4G

P12

XTALI

N12

XTALO

F4

REFCLK_SEL

BCM5751MKFBG_FPBGA196

1 2

4.7K_0402_5%

Pin L9, if TPM supported, Pull down
via 4.7K resister. L09 floating to
disable TPM function.

Pin L06:Low Power Mode
Driven High-IDDQ Mode(less than 20mA)
Driven Low-Normal Mode

BCM5751M

BroadSAFE

Media

Power

Msic

Regulator

Hot Plug

Support

PCI-ETEST

LED

Control

Control

VAUXPRSNT

TRD3+

TRD3-

TRD2+

TRD2-

TRD1+

TRD1-

TRD0+

TRD0-

LOW_PWR
VMAIN_ON

VAUX_ON

PERST

REGSUP12
REGCTL12
REGSEN12

REGOUT25

REGSUP25

PCIE_TXDN
PCIE_TXDP
PCIE_RXDN
PCIE_RXDP

WAKE

REFCLK-

REFCLK+

TST

TCK
TDO

TMS

TRST

E13
E14
D13
D14
C13
C14
B13
B14

L6
N14

M13
C2

K14
J13
J14

M14
L14

P6
N6
N10
P10
A6

P8
N8

J12
D8

D7
H12

TDI

D6
C11
D12

Clock

A10

RDAC

Bias

Layout Notice : No high
speed signal should be
routed near RDAC or on
adjacent layer to RDAC

4

R247 30K_0402_5%@

1 2

R246 30K_0402_5%@

1 2

R248 30K_0402_5%@

1 2

R245 30K_0402_5%@

1 2

R242 30K_0402_5%@

1 2

R249 30K_0402_5%@

1 2

R244 30K_0402_5%@

1 2

R243 30K_0402_5%@

1 2

C C

+3VLAN

SMBus to support ASF

+3VS

B B

A A

25MHZ_16P_XSL025000FK1H

2

C273

1

27P_0402_50V8J

R240

@

4.7K_0402_5%

1 2

LAN_SMBCLK26
LAN_SMBDATA26

1 2

R241

4.7K_0402_5%@

R227 4.7K_0402_5%

1 2

1 2

R235

4.7K_0402_5%

1 2

R236

4.7K_0402_5%

+3VS

R238
200_0603_1%

12

Y1

1 2

2

B

1C4

+3VLAN
REGCTL_PNP
+1.2VLAN

LAN_TX3+
LAN_TX3­LAN_TX2+
LAN_TX2­LAN_RX1+
LAN_RX1­LAN_TX0+
LAN_TX0-

REGCTL

1 2

R234 0_0402_5%

LAN_AUXPWR

R229

4.7K_0402_5%

@

R228

1 2

1.24K_0402_1%

1 2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

12

PCIE_MRX_C_LTX_N0
PCIE_MRX_C_LTX_P0

R224

E

3

LAN_TX3+ 26
LAN_TX3- 26
LAN_TX2+ 26
LAN_TX2- 26
LAN_RX1+ 26
LAN_RX1- 26
LAN_TX0+ 26
LAN_TX0- 26

LAN_LOW_PWR 32

PLT_RST# 9,19,21,27,32

+2.5VLAN

+3VLAN

C270

1 2
1 2

C269

1 2

R233

4.7K_0402_5%

4.7K_0402_5%

+3VLAN

+3VLAN

0.1U_0402_16V4Z

C230

R223

1_1210_5%

1 2

Z4011

Q1

1

MMJT9435T1G_SOT223

2 3

4

+1.2VLAN

0.1U_0402_16V4Z

+3VLAN

REGCTL_PNP

+1.2VLAN

PCIE_RXN1 21

PCIE_RXP1 21
PCIE_TXN1 21
PCIE_TXP1 21

PCIE_PME# 32
CLK_PCIE_LAN# 17
CLK_PCIE_LAN 17

0.1U_0402_16V4Z

5751_SI 5751_SO

C229

2

1

+3VLAN

U9

8

SO

7

GND

6

VCC

5

WP#

AT45DB011B-SU_SO8~N

4.7U_0805_10V4Z

C231

2

2

1

1

C16

2

2

1

1

Layout Notice : Place as close
chip as possible.

C238

C261

1

SI

2

SCK

3

RESET#

4

CS#

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C17
10U_0805_10V4Z~N

2

1

2

1

3

Layout Notice : 3.3V filter. Place as close
chip as possible.

+3VLAN

2

2

C240

C239

1

1

4.7U_0805_10V4Z

0.1U_0402_16V4Z

+1.2VLAN

+2.5VLAN

@

2

1

+3VLAN

R8

4.7K_0402_5%

22U_1206_10V4Z

22U_1206_10V4Z

@

C241

2

1

12

12

R7

4.7K_0402_5%

0.1U_0402_16V4Z

0.1U_0402_16V4Z

C11

+3VLAN

C30

SCLK
CS#

22U_1206_10V4Z

2

1

4.7U_0805_10V4Z

2

1

+3VLAN

C26

2005/09/10 2006/06/23

2

2

C237

C260

1

1

0.1U_0402_16V4Z

0.1U_0402_16V4Z

C274

1

1

C280

2

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

Notice : 4.7u 6.3V capactor Thickness 1.25mm

Layout Notice : Filter place as close
chip as possible.

Layout Notice : Filter place as close
chip as possible.

+2.5VLAN

L22 FBM-L11-160808-601LMT_0603

L17 FBM-L11-160808-601LMT_0603

L20 FBM-L11-160808-601LMT_0603

+1.2VLAN

L21 FBM-L11-160808-601LMT_0603

4.7U_0805_6.3V6K

L7 FBM-L11-160808-601LMT_0603

4.7U_0805_6.3V6K

L8 FBM-L11-160808-601LMT_0603

4.7U_0805_6.3V6K

L23 FBM-L11-160808-601LMT_0603

4.7U_0805_6.3V6K

12

C256

0.1U_0402_16V4Z

12

C235

0.1U_0402_16V4Z

12

C246

0.1U_0402_16V4Z

12

2

C252

1

12

2

C21

1

12

2

C24

1

12

1

C267

@

2

No CIS Symbol

Compal Secret Data

Deciphered Date

1

C279

2

0.1U_0402_16V4Z

+2.5VLAN

XTALVDD

2

1

+LAN_AVDD

2

1

+LAN_AVDD1

2

1

AVDDL

2

C249

0.1U_0402_16V4Z

1

GPHY_PLLVDD

2

C253

0.1U_0402_16V4Z

1

PCIE_PLLVDD

2

C271

0.1U_0402_16V4Z

1

PCIE_SDS_VDD

2

C265

0.1U_0402_16V4Z

1

2

Layout Notice : 1.2V filter. Place as close
chip as possible.

+1.2VLAN+3VS

2

2

C247

C255

1

1

0.1U_0402_16V4Z

4.7U_0805_6.3V6K

+1.2VLAN

0.1U_0402_16V4Z

0.1U_0402_16V4Z
C244

C268

2

2

1

1

+3VLAN

+3VS

+2.5VLAN

XTALVDD

1 2

+3VLAN

R250 0_0402_5%@

PCIE_SDS_VDD

AVDDL

+LAN_AVDD
+LAN_AVDD1

PCIE_PLLVDD

GPHY_PLLVDD

+3VS

T8 P AD

+2.5VLAN

12

FBM-L11-160808-601LMT_0603

L18

LAN_VBIAS

1

C236

0.1U_0402_16V4Z

2

2

C262

2

C259

1

1

0.1U_0402_16V4Z

0.1U_0402_16V4Z

VSS_10
VSS_11
VSS_12
VSS_13

GND

VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27

1

2

2

PAD

C248

T9

C258

1

1

0.1U_0402_16V4Z

0.1U_0402_16V4Z

U3B

B8

VDDC_0

E5

VDDC_1

E6

VDDC_2

E7

VDDC_3

E8

VDDC_4

E9

VDDC_5

E10

VDDC_6

F5

VDDC_7

F10

VDDC_8

G4

VDDC_9

J5

VDDC_10

J10

VDDC_11

K5

VDDC_12

K6

VDDC_13

K7

VDDC_14

K8

VDDC_15

K4

VDDC_16

J4

VDDC_17

D11

VDDIO_0

G11

VDDIO_1

K12

VDDIO_2

Digial power

A7

VDDIO-PCI_0

B3

VDDIO-PCI_1

C5

VDDIO-PCI_2

E1

VDDIO-PCI_3

E4

VDDIO-PCI_4

G1

VDDIO-PCI_5

K3

VDDIO-PCI_6

L4

VDDIO-PCI_7

P2

VDDIO-PCI_8

A8

VDDP_0

D5

VDDP_1

P13

VDDP_2

H14

XTALVDD

M12

WOL_VAUX

P14

WOL_INRSH_ON

M6

PCIE_SDS_VDD

F12

AVDDL_0

F13

AVDDL_1

A13

AVDD_0

F14

AVDD_1

M8

PCIE_PLLVDD

G14

GPHY_PLLVDD

P1

VESD1

G2

VESD2

A1

VESD3

L3

DC_31

M1

DC_32

M2

DC_33

M3

DC_34

M4

DC_35

M5

DC_36

M7

DC_37

N2

DC_38

N3

DC_39

N4

DC_40

N5

DC_41

N7

DC_42

P3

DC_43

P4

DC_44

P5

DC_45

P7

DC_46

A14

BIASVDD

BCM5751MKFBG_FPBGA196

Title

SCHEMATIC, M/B LA-3051P

Size Document Number Rev

Date: Sheet

星期四 十月

2

2

C250

C242

1

1

0.1U_0402_16V4Z

0.1U_0402_16V4Z

BCM5751M

Analog
power

PLL

Clamp

Don't care

BIAS

Compal Electronics, Inc.

401397

C254

VSS_0
VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9

NC_0
NC_1
NC_2
NC_3
NC_4
NC_5
NC_6

DC_0
DC_1
DC_2
DC_3
DC_4
DC_5
DC_6
DC_7
DC_8

DC_9
DC_10
DC_11
DC_12
DC_13
DC_14
DC_15
DC_16
DC_17
DC_18
DC_19
DC_20
DC_21
DC_22
DC_23
DC_24
DC_25
DC_26
DC_27
DC_28
DC_29
DC_30

2

1

0.1U_0402_16V4Z

@

4.7K_0402_5%

25 45, 06, 2005

C257

B4
B7
B12
E2
F6
F7
F8
F9
G5
G6
G7
G8
G9
G10
H5
H6
H7
H8
H9
H10
J6
J7
J8
J9
K2
N1
N9
P9

K13
L7
L12
L13
M10
N11
P11

A3
A4
A5
B1
B2
B5
B6
C1
C3
C4
C6
C7
C8
C9
D1
D2
D3
D4
E3
F1
F2
F3
G3
H1
H3
H4
J1
J3
K1
L1
L2

2

1

0.1U_0402_16V4Z

R237

of

12

+3VLAN

A

5

D D

V_DAC

+2.5VLAN

C32 0.1U_0402_16V4Z

1 2

LAN_TX3+25

LAN_TX3-25

C23 0.1U_0402_16V4Z

1 2

LAN_TX2+25

1 2

R25
0_0805_5%

V_DAC

LAN_TX3+

LAN_TX3-

V_DAC

LAN_TX2+

4

T10

1

TCT1

1:1

2

TD1+

3

TD1-

4

TCT2

1:1

5

TD21+

MCT1
MX1+

MX1­MCT2
MX2+

24
23

22
21
20

RJ45_TX3+

RJ45_TX3-

RJ45_TX2+

RP1

1 8
2 7
3 6
4 5

75_1206_8P4R_5%

3

C20
1000P_1206_2KV7K

12

2

1

LAN_TX2-

C C

B B

LAN_TX2-25

C27 0.1U_0402_16V4Z

1 2

LAN_RX1+25

LAN_RX1-25

C29 0.1U_0402_16V4Z

1 2

LAN_TX0+25

LAN_TX0-25

R18 49.9_0402_1%

LAN_TX0+

1 2

R17 49.9_0402_1%

LAN_TX0-

1 2

R20 49.9_0402_1%

LAN_RX1+

1 2

R19 49.9_0402_1%

LAN_RX1-

1 2

R22 49.9_0402_1%

LAN_TX2+

1 2

R21 49.9_0402_1%

LAN_TX2-

1 2

R24 49.9_0402_1%

LAN_TX3+

1 2

R23 49.9_0402_1%

LAN_TX3-

1 2

All 49.9 ohm + 0.1 uF
termination components close
to BCM5751M

C22 0.1U_0402_16V4Z

1 2

C25 0.1U_0402_16V4Z

1 2

C28 0.1U_0402_16V4Z

1 2

C31 0.1U_0402_16V4Z

1 2

V_DAC

LAN_RX1+

LAN_RX1-

V_DAC

LAN_TX0+

LAN_TX0-

6

TD2-

7

TCT3

8

TD3+

9

TD3-

10

TCT4

11

TD4+

12

TD4-

24HST1041A-3-LF_24P

1:1

1:1

ICH_SMBDATA17,21,27

ICH_SMBCLK17,21,27

RJ45_TX2-

19

MX2-

18

MCT3

RJ45_RX1+

17

MX3+

RJ45_RX1-

16

MX3-

15

MCT4

RJ45_TX0+

14

MX4+

RJ45_TX0-

13

MX4-

Layout Note
24HST1041A-3 pls close to conn.

+3VLAN

1 2

R221 0_0402_5%

Q19

D

S

2N7002_SOT23@

+3VS

2N7002_SOT23@

Q18

G

2

G

2

S

1 2

R219

13

13

D

0_0402_5%

RJ45_TX0­RJ45_TX0+
RJ45_RX1+
RJ45_TX2+
RJ45_TX2­RJ45_RX1­RJ45_TX3+
RJ45_TX3-

12

12

R222

R220

10K_0402_5%

10K_0402_5%

@

@

LAN_SDATA

LAN_SCLK

LAN_SMBDATA 25

LAN_SMBCLK 25

1 2

C19 0.1U_0402_16V4Z

1 2

C33 0.1U_0402_16V4Z

1 2

C18 0.1U_0402_16V4Z

1 2

C34 0.1U_0402_16V4Z

JLAN1

2

PR1-

1

PR1+

3

PR2+

4

PR3+

5

PR3-

6

PR2-

7

PR4+

8

PR4-

ALLTO_C100A9-108A4-L~N

SHLD1
SHLD2

9
10

A A

Security Cl assification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INF ORMATION IT CONTAI NS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WR ITT EN CO NSE NT OF COMPAL ELECTRONICS, INC.

3

2005/09/10 2006/06/23

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

SCHEMATIC, M/B LA-3051P

Size Docum e nt N u m be r Re v

Date: Sheet

星期四 十月

401397

, 2005

of

1

26 45, 06

A

ICH_PCIE_WAKE#21

WL_ACTIVE24,43

BT_CHCLK24,43

CLKREQD#17

CLK_PCIE_MCARD#17
CLK_PCIE_MCARD17

PCIE_RXN221
PCIE_RXP221

PCIE_TXN221
PCIE_TXP221

R215
R214

CLK_PCIE_MCARD#
CLK_PCIE_MCARD

+3VS

37 ~ 51 are Reserved Pin
Check

C223

12

0.1U_0402_16V4Z

0_0402_5%
0_0402_5%

JMINI1

1

1

3
5
7

9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51

53

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

GND1

GND2

FOX_AS0B226-S52N-7F~N

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

54

PLT_RST#

ICH_SMBCLK

ICH_SMBDATA

USB_P5­USB_P5+

+3VALW

WL_OFF# 24,32,33,43
PLT_RST# 9,19,21,25,32

ICH_SMBCLK 17,21,26
ICH_SMBDATA 17,21,26

WLAN_ACT_GOLAN 33

1

C516

2

0.1U_0402_16V4Z

30,32,36,38 are Reserved Pin Check

+3VS
+1.5VS

1

C518

2

0.1U_0402_16V4Z

0.047U_0402_16V4Z

2

C199

1

0.047U_0402_16V4Z

2

1

C538

0.047U_0402_16V4Z

1

C541

2

1

C517

2

0.047U_0402_16V4Z

USB_P5-

R183 0_0402_5%

USB_P5+

R182 0_0402_5%

0.047U_0402_16V4Z

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITT EN CON SENT O F COMPAL ELECTRONICS, INC.

+3VS

1

C167

2

2005/09/10 2006/06/23

Compal Secret Data

12

12

Deciphered Date

USB20_N5 21

USB20_P5 21

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, M/B LA-3051P

星期

四十月

401397

, 06, 2005

27 45

of

A

5

+3VS

U23B

W7

+3V

C47810 U_0805_10V4Z~N

1 2
1 2

C4710.01U_0402_16V7K

+2.5V_CORE

D D

+2.5V_CORE

1

C419

2

0.01U_0402_16V7K

PCI_AD20

PCI_CBE#319,32,43
PCI_CBE#219,32,43
PCI_CBE#119,32,43
PCI_CBE#019,32,43

PCI_RST#19,32,43
CLK_PCI_CB17

CB_PME#32

PCI_CLKRUN#21,32,43

PCI_AD[0..31]

1

C503

2

0.47U_0603_10V7K

PCI_FRAME#19,32,43

PCI_IRDY#19,43
PCI_TRDY#19,32,43

PCI_DEVSEL#19,43

PCI_STOP#19,43
PCI_PERR#19,43
PCI_SERR#19,43

PCI_REQ2#19

PCI_GNT2#19
PCI_PIRQG#19,43
PCI_PIRQE#19
PCI_PIRQB#19
PCI_PIRQA#19

PCI_AD[0..31]19,32,43

1

C502

C431

2

0.01U_0402_16V7K

C C

+3V

12

R490
100K_0402_5%

CBS_GRST#

1

C513
1U_0603_10V4Z

2

B B

R411
100K_0402_5%

1

2

0.47U_0603_10V7K

1 2

R442 100_0402_5%

PCI_PAR19,43

PCI_TRDY#

PCI_PERR#
PCI_SERR#

PCI_RST#
CLK_PCI_CB

R496 0_0402_5%
R489 10K_0402_5%@

PCI_AD31
PCI_AD30
PCI_AD29
PCI_AD28
PCI_AD27
PCI_AD26
PCI_AD25
PCI_AD24
PCI_AD23
PCI_AD22
PCI_AD21
PCI_AD20
PCI_AD19
PCI_AD18
PCI_AD17
PCI_AD16
PCI_AD15
PCI_AD14
PCI_AD13
PCI_AD12
PCI_AD11
PCI_AD10
PCI_AD9
PCI_AD8
PCI_AD7
PCI_AD6
PCI_AD5
PCI_AD4
PCI_AD3
PCI_AD2
PCI_AD1
PCI_AD0

CBS_IDSEL

PCI_PAR
PCI_FRAME#

PCI_IRDY#
PCI_DEVSEL#

PCI_STOP#

1 2

1 2

12

CBS_GRST#

+3VS

10U_0805_10V4Z~N

22U_1206_6.3V6M

1

2

1

C462

2

C463

0.01U_0402_16V7K

1

2

0.1U_0402_16V4Z

1

C477

2

C466

5

0.01U_0402_16V7K

1

C434

2

0.1U_0402_16V4Z

+3V_PHY

1

1

C433

2

2

1000P_0402_50V7K~N

1000P_0402_50V7K~N

1

1

C469

C457

2

2

10U_0805_10V4Z~N

L29

+3V

CHB1608B121_0603

1 2

A A

C418

VCC_PCI1

P10

VCC_PCI2

P11

VCC_PCI3

M6

VCC_RIN1

F19

VCC_RIN2

H1

VCC_ROUT1

G14

VCC_ROUT2

E19

REG_EN#

V3

AD31

W3

AD30

U4

AD29

V4

AD28

W4

AD27

U5

AD26

V5

AD25

W5

AD24

V6

AD23

W6

AD22

P7

AD21

R7

AD20

U7

AD19

V7

AD18

P8

AD17

R8

AD16

R11

AD15

U11

AD14

V11

AD13

W11

AD12

P12

AD11

R12

AD10

U12

AD9

V12

AD8

P13

AD7

R13

AD6

U13

AD5

V13

AD4

W13

AD3

U14

AD2

V14

AD1

W14

AD0

U6

IDSEL

R6

C/BE3#

U8

C/BE2#

W10

C/BE1#

W12

C/BE0#

V10

PAR

V8

FRAME#

W8

IRDY#

P9

TRDY#

R9

DEVSEL#

U9

STOP#

R10

PERR#

U10

SERR#

W2

REQ#

V2

GNT#

U3

INTD#

T1

INTC#

T2

INTB#

T3

INTA#

P3

GBRST#

U1

PCIRST#

V1

PCICLK

P5

RI_OUT#/PME#

U2

CLKRUN#

R5C842-CSP265P_CSP265

INTA# : Card Socket A
INTB# : Card Socket B
INTC# : IEEE1394

CLK_PCI_CB

12

CLK_PCI_CBS_TERM

1

2

R482
10_0402_5%

C511
22P_0402_25V8K

4

F7

VCC_3V4

J19

VCC_3V3

K19

VCC_3V2

F8

VCC_3V1

A8

VCC_MD

TPBIAS0/NC

TPBN0/NC
TPBP0/NC
TPAN0/NC
TPAP0/NC

TPBIAS1/NC

TPBN1/NC
TPBP1/NC
TPAN1/NC
TPAP1/NC

CPS/NC
VREF/NC
REXT/NC

FIL0/NC

SPKROUT

HWSPND#

UDIO1
UDIO2
UDIO3
UDIO4
UDIO5

XI/NC

XO/NC

TEST
AGND1/GND
AGND2/GND
AGND3/GND
AGND4/GND
AGND5/GND
AGND6/GND

GND1

GND2

GND3

GND4

GND5

GND6

GND7

GND8

GND9

E11
E13
A18
B18

C13
A14
B14
A13
B13

C11
A12
B12
A11
B11

C12
C14
B15
A15

P6
N1
R1
R2
R3
R5
P1
P2

A17
B17
N2

A10
B10
C10
A16
B16
C15

F1
V9
W9
M19
K9
K10
K11
J10
L10

AVCC_PHY1/NC
AVCC_PHY2/NC
AVCC_PHY3/NC
AVCC_PHY4/NC

PCI / MISC / 1394_OHCI PORTION

UDIO0/SRIRQ#

Please apply shield GND for TPAx0 and TPBx0 Separately;

========================================== GND

------------------------------------------ TPBN0

------------------------------------------ TPBP0
========================================== GND

------------------------------------------ TPAN0

------------------------------------------ TPAP0
========================================== GND

Layout Note: Shield GND for
CBS_BCCLK
CBS_ACCLK

Layout Note:
Y5,C482, C484
Should close to U22

Layout Note: Shield GND for
VREF (PIN C1 2 of U12)
REXT (PIN C14 of U12)
FIL0 (PIN A15 of U12)

Layout Note: C480, R304 and C481
need be closed to PAD.

Layout Note:CLK_PCI_CB SHOULD BE
GND SHIELDING.

Layout Note: CBS_ACCLK and
CBS_BCCLK should be shielded GND.

4

+3V

0.01U_0402_16V7K

C501

1

1

2

2

56.2_0402_1%

+3V

+3V

C429

12

16P_0603_50V8J

C428

12

16P_0603_50V8J

0.01U_0402_16V7K

12

12

R436

1

2

0.01U_0402_16V7K

PCM_SPK# 31

CBS_SPND# 32

SERIRQ 21,32

R429 56.2_0603_1%

C464

0.01U_0402_16V7K

10U_0805_10V4Z~N

C432

C424

+3V_PHY

IEEE1394_TPBIAS0
IEEE1394_TPBN0
IEEE1394_TPBP0
IEEE1394_TPAN0
IEEE1394_TPAP0

C455 0.01U_0402_16V7K
R421 10K_0603_1%
C453

0.01U_0402_16V7K
R448 100K_0402_5%

PCM_SPK#

R491 10K_0402_5%

SPKROUT: Pull-up disable Serial EEPROM.

1 2

R453 10K_0402_5%

1 2

R483 10K_0402_5%

R5C841XI
R5C841XO

C430

1

1

2

2

+3V_PHY

12

12

1 2

12

12

Y4

24.576MHZ_16P_XSL024576FG1H

1 2

3

CBS_BCAD[0..31]

Z3008

CBS_BCCLK29

12

R434 56.2_0603_1%

12

R439

56.2_0402_1%

0.33U_0603_10V7K

1

C470

2

C460

CBS_BCINT#29

CBS_BCAUDIO29

12

1

2

270P_0402_50V7K~N

IEEE1394_TPBIAS0
IEEE1394_TPBN0 29
IEEE1394_TPBP0 29
IEEE1394_TPAN0 29
IEEE1394_TPAP0 29

CBS_BCCBE3#29
CBS_BCCBE2#29
CBS_BCCBE1#29
CBS_BCCBE0#29

CBS_BCPAR29
CBS_BCFRAME#29

CBS_BCTRDY#29
CBS_BCIRDY#29
CBS_BCSTOP#29
CBS_BCDEVSEL#29
CBS_BCBLOCK#29
CBS_BCPERR#29
CBS_BCSERR#29
CBS_BCREQ#29
CBS_BCGNT#29
CBS_BCSTSCHNG29
CBS_BCCLKRUN#29

CBS_BCRST#29

CBS_BCRSV3/D229
CBS_BCRSV2/A1829
CBS_BCRSVD/D1429

CBS_BCVS129
CBS_BCVS229

BVPPEN129

BVPPEN029
BVCC5EN#29
BVCC3EN#29

R430

5.1K_0402_1%

R484 22_0402_5%

Security Cla ssification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONIC S, INC. AND CONTAI NS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

3

CBS_BCAD[0..31] 29

CBS_BCAD31
CBS_BCAD30
CBS_BCAD29
CBS_BCAD28
CBS_BCAD27
CBS_BCAD26
CBS_BCAD25
CBS_BCAD24
CBS_BCAD23
CBS_BCAD22
CBS_BCAD21
CBS_BCAD20
CBS_BCAD19
CBS_BCAD18
CBS_BCAD17
CBS_BCAD16
CBS_BCAD15
CBS_BCAD14
CBS_BCAD13
CBS_BCAD12
CBS_BCAD11
CBS_BCAD10
CBS_BCAD9
CBS_BCAD8
CBS_BCAD7
CBS_BCAD6
CBS_BCAD5
CBS_BCAD4
CBS_BCAD3
CBS_BCAD2
CBS_BCAD1
CBS_BCAD0

CBS_BCCBE3#
CBS_BCCBE2#
CBS_BCCBE1#
CBS_BCCBE0#

CBS_BCPAR
CBS_BCFRAME#

CBS_BCTRDY#
CBS_BCIRDY#
CBS_BCSTOP#
CBS_BCDEVSEL#
CBS_BCBLOCK#
CBS_BCPERR#
CBS_BCSERR#
CBS_BCREQ#
CBS_BCGNT#
CBS_BCSTSCHNG
CBS_BCCLKRUN#
CBS_BCCLK_INTERNAL

12

CBS_BCINT#
CBS_BCRST#
CBS_BCAUDIO

CBS_BCRSV3/D2
CBS_BCRSV2/A18
CBS_BCRSV/D14

CBS_BCCD1#_INTERNAL
CBS_BCCD2#_INTERNAL
CBS_BCVS1
CBS_BCVS2

CBS_ACCD1#_INTERNAL
CBS_ACCD2#_INTERNAL

270P_0402_50V7K~N

2005/09/10 2006/06/23

Compal Secret Data

U23A

N6
M2
M3
M5

L1
L3
L6
K2
K5
J1
J3

J6
H3
H2
H5
D2
C1

B1
C2

A2

A3

B3
C3

B4

B5
C5

A5

E5
C6

E6

F6

E7

K1
H6
D3

A4
D1
G3

G6
G5

F3
G1

E1

E2

K6

K3

F5

L2
N5
G2

F2

J2

L5
M1

E3
C4

C7
N3

B2

J5

B6

A6

P14
R14
R15
P15

A7

B7

B8
C8

E8

B9

A9
C9

E9

F9

R5C842-CSP265P_CSP265

R402

1 2

2

C425

1

Deciphered Date

2

BCAD31/D10
BCAD30/D9
BCAD29/D1
BCAD28/D8
BCAD27/D0
BCAD26/A0
BCAD25/A1
BCAD24/A2
BCAD23/A3
BCAD22/A4
BCAD21/A5
BCAD20/A6
BCAD19/A25
BCAD18/A7
BCAD17/A24
BCAD16/A17
BCAD15/IOWR#
BCAD14/A9
BCAD13/IORD#
BCAD12/A11
BCAD11/OE#
BCAD10/CE2#
BCAD9/A10
BCAD8/D15
BCAD7/D7
BCAD6/D13
BCAD5/D6
BCAD4/D12
BCAD3/D5
BCAD2/D11
BCAD1/D4
BCAD0/D3

BCCBE3#/REG#
BCCBE2#/A12
BCCBE1#/A8
BCCBE0/CE1#

BCPAR/A13
BCFRAME#/A23

BCTRDY#/A22
BCIRDY#/A15
BCSTOP/A20
BCDEVSEL#/A21
BCBLOCK#/A19
BCPERR#/A14
BCSERR#/WAIT#
BCREQ#/INPACK#
BCGNT#/WE#
BCSTSCHG/BVD1_STSCHG#
BCCLKRUN#/WP
BCCLK/A16

BCINT#/RDY_IREQ
BCRST#/RESET
BCAUDIO/BVD2_SPKR#
BCRSV3/D2

BCRSV2/A18
BCRSV1/D14

BCCD1/CD1#
BCCD2#/CD2#
BCVS1/VS1#
BCVS2/VS2#

BUSBDP
BUSBDM

BVPPEN1
BVPPEN0
BVCC5EN#
BVCC3EN#

MDIO00
MDIO01
MDIO02
MDIO03
MDIO04
MDIO05
MDIO06

MDIO07
MDIO08
MDIO09

CBS_ACD2#
CBS_ACD1#

0_0402_5%

R417
0_0402_5%

1 2

2

C449
270P_0402_50V7K~N

1

2

CARDBUS / MEDIA CARD PORTION

ACSTSCHG/BVD1_STSCHG#

ACAD31/D10

ACAD30/D9
ACAD29/D1
ACAD28/D8
ACAD27/D0
ACAD26/A0
ACAD25/A1
ACAD24/A2
ACAD23/A3
ACAD22/A4
ACAD21/A5
ACAD20/A6

ACAD19/A25

ACAD18/A7
ACAD17/A24
ACAD16/A17

ACAD15/IOWD#

ACAD14/A9

ACAD13/IORD#

ACAD12/A11

ACAD11/OE#

ACAD10/CE2#

ACAD9/A10

ACAD8/D15

ACAD7/D7

ACAD6/D13

ACAD5/D6

ACAD4/D12

ACAD3/D5

ACAD2/D11

ACAD1/D4
ACAD0/D3

ACCBE3#/REG#

ACCBE2#/A12

ACCBE1#/A8

ACCBE0#/CE1#

ACPAR/A13

ACFRAME#/A23

ACTRDY#/A22

ACIRDY#/A15

ACSTOP#/A20

ACDEVSEL#/A21

ACBLOCK#/A19

ACPERR#/A14

ACSERR#/WAIT#

ACREQ#/INPACK#

ACGNT#/WE#

ACCLKRUN#/WP

ACCLK/A16

ACINT#/RDY_IREQ

ACRST#/RESET

ACAUDIO/BVD2_SPKR#

ACRSV3/D2
ACRSV2/A18
ACRSV1/D14

ACCD1/CD1#
ACCD2/CD2#

ACVS1/VS1#
ACVS2/VS2#

AUSBDP

AUSBDM

AVPPEN1

AVPPEN0
AVCC3EN#
AVCC5EN#

MDIO10
MDIO11
MDIO12
MDIO13

MDIO14/NC
MDIO15/NC
MDIO16/NC
MDIO17/NC
MDIO18/NC
MDIO19/NC

CBS_ACD2# 29
CBS_ACD1# 29

CBS_BCCD1#_INTERNAL
CBS_BCCD2#_INTERNAL

270P_0402_50V7K~N

1

CBS_ACAD[0..31]

CBS_ACAD31

C18

CBS_ACAD30

D19

CBS_ACAD29

D18

CBS_ACAD28

D17

CBS_ACAD27

E18

CBS_ACAD26

F18

CBS_ACAD25

F15

CBS_ACAD24

G18

CBS_ACAD23

G15

CBS_ACAD22

H18

CBS_ACAD21

H15

CBS_ACAD20

J18

CBS_ACAD19

J17

CBS_ACAD18

J15

CBS_ACAD17

J14

CBS_ACAD16

N15

CBS_ACAD15

N19

CBS_ACAD14

P19

CBS_ACAD13

N18

CBS_ACAD12

P18

CBS_ACAD11

P17

CBS_ACAD10

R19

CBS_ACAD9

R18

CBS_ACAD8

R17

CBS_ACAD7

T17

CBS_ACAD6

U19

CBS_ACAD5

U18

CBS_ACAD4

V19

CBS_ACAD3

W18

CBS_ACAD2

V18

CBS_ACAD1

W17

CBS_ACAD0

U17

CBS_ACCBE3#

G19

CBS_ACCBE2#

K18

CBS_ACCBE1#

N14

CBS_ACCBE0#

T19

CBS_ACPAR

M14

CBS_ACFRAME#

K17

CBS_ACTRDY#

K14

CBS_ACIRDY#

K15

CBS_ACSTOP#

L15

CBS_ACDEVSEL#

L18

CBS_ACBLOCK#

M18

CBS_ACPERR#

M17

CBS_ACSERR#

H19

CBS_ACREQ#

G17

CBS_ACGNT#

L14

CBS_ACSTSCHNG

E17

CBS_ACCLKRUN#

C19

CBS_ACCLK_INTERNAL

L19

CBS_ACINT#

L17

CBS_ACRST#

H17

CBS_ACAUDIO

F17

CBS_ACRSV3/D2

C17

CBS_ACRSV2/A18

M15

CBS_ACRSV/D14

T18

CBS_ACCD1#_INTERNAL

V17

CBS_ACCD2#_INTERNAL

B19

CBS_ACVS1

N17

CBS_ACVS2

H14
V16

W16
U16

W15
V15
U15

E10
F10
F11
E12

F12
F13
E14
F14
E15
C16

R494

1 2

2

C508

1

Title

Size Docu m e n t N u m b e r Re v

星期四

Date: Sheet

1 2

CBS_BCD2#
CBS_BCD1#

0_0402_5%

R454
0_0402_5%

1 2

2

C484
270P_0402_50V7K~N

1

Compal Electronics, Inc.

SCHEMATIC, M/B LA-3051P

401397

06, 2005

十月

R407 22_0402_5%

R427
10K_0402_5%

CBS_ACAD[0..31] 29

CBS_ACCBE3# 29
CBS_ACCBE2# 29
CBS_ACCBE1# 29
CBS_ACCBE0# 29

CBS_ACPAR 29
CBS_ACFRAME# 29

CBS_ACTRDY# 29
CBS_ACIRDY# 29
CBS_ACSTOP# 29
CBS_ACDEVSEL# 29
CBS_ACBLOCK# 29

CBS_ACPERR# 29
CBS_ACSERR# 29
CBS_ACREQ# 29
CBS_ACGNT# 29
CBS_ACSTSCHNG 29

CBS_ACCLKRUN# 29

12

CBS_ACINT# 29
CBS_ACRST# 29
CBS_ACAUDIO 29

CBS_ACRSV3/D2 29

CBS_ACRSV2/A18 29

CBS_ACRSVD/D14 29

CBS_ACVS1 29

CBS_ACVS2 29

AVPPEN1 29
AVPPEN0 29
AVCC3EN# 29
AVCC5EN# 29

CBS_BCD2# 29
CBS_BCD1# 29

1

CBS_ACCLK 29

of

28 45,

A

5

4

3

2

1

D D

CBS_AVCC

+3V

0.1U_0402_16V4Z

1U_0603_10V6K

1

C496

1

2

C505

1

2

2

0.1U_0402_16V4Z

C486

1U_0603_10V6K

1

2

0.1U_0402_16V4Z

C523

+5V

+5V

1U_0603_10V6K

1

C482

1

2

1

2

IEEE1394_TPBN028
IEEE1394_TPBP028
IEEE1394_TPAN028
IEEE1394_TPAP028

C533

2

1U_0603_10V6K

1

2

AVCC3EN#28
AVCC5EN#28

AVPPEN028
AVPPEN128

BVCC3EN#28
BVCC5EN#28

BVPPEN128
BVPPEN028

AVCC3EN#
AVCC5EN#

AVPPEN0
AVPPEN1

BVCC3EN#
BVCC5EN#

BVPPEN1
BVPPEN0

R473 0_0402_5%

R460 0_0402_5%

R493 0_0402_5%

R488 0_0402_5%

C490

+3V

0.1U_0402_16V4Z

C510

C C

B B

U26

10

AVCC3IN

6

AVCC5IN

2
1

4

12

3

12

11
15

19
20

18

12

17

12

Slot A
Power

AVCC3_EN

Supply

AVCC5_EN
AEN0

AEN1

BVCC3IN
BVCC5IN

Slot B

BVCC3_EN

Power

BVCC5_EN

Supply

BEN0
BEN1

R5534V-E2-FB_SSOP20~N

AVCCOUT
AVCCOUT

AVPPOUT

BVCCOUT
BVCCOUT

BVPPOUT

GND

TST

7
8

9

+5V

5

13
14

12

16

CBS_ACCLK

CBS_BCCLK

33_0402_5%

22P_0402_25V8K

CBS_AVPP

C488

1

2

CBS_BVPP

C530

1

2

R472

@

C504

@

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1 2

1 2

1

2

1

2

For EMI

TPBN0
TPBP0
TPAN0
TPAP0

JP10

1

1

2

2

3

3

4

4

5

GND1

6

GND2

FOX_UV31413-WR50D-7F~N

C487

0.01U_0402_16V7K

C483

1

2

CBS_BVCC

C524

0.01U_0402_16V7K

C525

1

2

R443

@

33_0402_5%

C480

@

22P_0402_25V8K

0.01U_0402_16V7K

1

2

1

2

1

2

0.01U_0402_16V7K

1

2

14

1: TPB#

A A

2: TPB

CBS_ACAD[0..31]

C476
10U_0805_10V4Z~N

CBS_ACCBE1#28
CBS_ACRSV2/A1828

C536

CBS_ACPAR28

10U_0805_10V4Z~N

CBS_ACBLOCK#28
CBS_ACPERR#28
CBS_ACSTOP#28

CBS_ACGNT#28
CBS_ACDEVSEL#28

CBS_AVCC

CBS_AVPP

CBS_ACVS228

CBS_ACCBE3#28

CBS_ACSTSCHNG28

CBS_ACCLKRUN#28

CBS_ACAD[0..31] 28

CBS_ACD1#28

CBS_ACCBE0#28

CBS_ACVS128

CBS_ACINT#28

CBS_ACCLK28
CBS_ACTRDY#28
CBS_ACIRDY#28

CBS_ACFRAME#28

CBS_ACCBE2#28

CBS_ACRST#28
CBS_ACSERR#28
CBS_ACREQ#28

CBS_ACAUDIO28

CBS_ACD2#28

CBS_ACAD0
CBS_ACAD2
CBS_ACAD1
CBS_ACAD4
CBS_ACAD3

CBS_ACAD6
CBS_ACAD5

CBS_ACRSV/D14
CBS_ACAD7
CBS_ACAD8

CBS_ACCBE0#

CBS_ACAD10

CBS_ACAD9
CBS_ACVS1

CBS_ACAD11
CBS_ACAD13
CBS_ACAD12
CBS_ACAD15
CBS_ACAD14

CBS_ACAD16
CBS_ACCBE1#
CBS_ACRSV2/A18
CBS_ACPAR
CBS_ACBLOCK#
CBS_ACPERR#
CBS_ACSTOP#

CBS_ACGNT#
CBS_ACDEVSEL#

CBS_ACCLK
CBS_ACTRDY#
CBS_ACIRDY#

CBS_ACFRAME#
CBS_ACCBE2#

CBS_ACAD17

CBS_ACAD18

CBS_ACAD19

CBS_ACAD20

CBS_ACVS2
CBS_ACAD21
CBS_ACAD22

CBS_ACSERR#

CBS_ACAD23
CBS_ACREQ#
CBS_ACAD24

CBS_ACCBE3#
CBS_ACAD25

CBS_ACAD26

CBS_ACSTSCHNG

CBS_ACAD27
CBS_ACAD28

CBS_ACAD29
CBS_ACAD30

CBS_ACRSV3/D2

CBS_ACAD31

CBS_ACCLKRUN#

JCBS1

75

GND

74

GND

73

BCCD1#/CD1#

72

BCAD0/D3

71

BCAD2/D11

70

BCAD1/D4

69

BCAD4/D12

68

BCAD3/D5

67

GND

66

BCAD6/D13

65

BCAD5/D6

64

BRFU/D14

63

BCAD7/D7

62

BCAD8/D15

61

BCCBE0#CE1#

60

BCAD10/CE2#

59

GND

58

BCAD9/A10

57

BCVS1/VS1#

56

BCAD11/OE#

55

BCAD13/IORD#

54

BCAD12/A11

53

BCAD15/OWR#

52

BCAD14/A9

51

GND

50

BCAD16/A17

49

BCCBE1#/A8

48

BRFU/A18

47

BCPAR/A13

46

BCBLOCK#/A19

45

BCPERR#/A14

44

BCSTOP#/A20

43

GND

42

BCGNT#/WE#

41

BCDEVSEL#/A21

40

BCINT#/READY

39

VCC

38

NC

37

VPP

36

BCCLK/A16

35

BCTRDY#/A22

34

BCIRDY#/A15

33

GND

32

BCFRAME#/A23

31

BCCBE2#/A12

30

BCAD17/A24

29

BCAD18/A7

28

BCAD19/A25

27

BCAD20/A6

26

BCVS2/VS2#

25

GND

24

BCAD21/A5

23

BCRST#/RESET

22

BCAD22/A4

21

BCSERR#/WAIT#

20

BCAD23/A3

19

BCREQ#/INPACK#

18

BCAD24/A2

17

GND

16

BCCBE3#/REG#

15

BCAD25/A1

14

BCAUDIO/SPKR#

13

BCAD26/A0

12

BCSTSCHG/STSCHG#

11

BCAD27/D0

10

BCAD28/D8

9

GND

8

BCAD29/D1

7

BCAD30/D9

6

BRFU/D2

5

BCAD31/D10

4

BCCLKRUN/WP

3

BCCD2#CD2#

2

GND

1

GND

152

GND

154

GND

FOX_QTS1150A-1121W-F_LT~N

GND
GND

ACCD1#/CD1#

ACAD0/D3

ACAD2/D11

ACAD1/D4

ACAD4/D12

ACAD3/D5

GND

ACAD6/D13

ACAD5/D6
ARFU/D14
ACAD7/D7

ACAD8/D15

ACCBE0#/CE1#

ACAD10/CE2#

GND

ACAD9/A10

ACVS1/VS1#

ACAD11/OE#

ACAD13/IORD#

ACAD12/A11

ACAD15/IOWR#

ACAD14/A9

GND

ACAD16/A17

ACCBE1#/A8

ARFU/A18

ACPAR/A13

ACBLOCK#/A19

ACPERR#/A14

ACSTOP#A20

GND

ACGNT#/WE#

ACDEVSEL#/A21

ACINT#/READY

VCC

ACCLK/A16

ACTRDY#/A22

ACIRDY#/A15

GND

ACFRAME#/A23

ACCBE2#/A12

ACAD17/A24

ACAD18/A7

ACAD19/A25

ACAD20/A6

ACVS2/VS2#

GND

ACAD21/A5

ACRST#/RESET

ACAD22/A4

ACSERR#/WAIT#

ACAD23/A3

ACREQ#/INPACK#

ACAD24/A2

GND

ACCBE3#/REG#

ACAD25/A1

ACAUDIO/SPKR#

ACAD26/A0

ACSTSCHG/STSCHG#

ACAD27/D0
ACAD28/D8

GND
ACAD29/D1
ACAD30/D9

ARFU/D2

ACAD31/D10

ACCLKRUN/WP

ACCD2#/CD2#

GND

GND

GND

GND

150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113

NC

112

VPP

111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76

151
153

CBS_BCAD[0..31]

CBS_BCAD0
CBS_BCAD2
CBS_BCAD1
CBS_BCAD4
CBS_BCAD3

CBS_BCAD6
CBS_BCAD5
CBS_BCRSV/D14
CBS_BCAD7
CBS_BCAD8
CBS_BCCBE0#
CBS_BCAD10

CBS_BCAD9
CBS_BCVS1
CBS_BCAD11
CBS_BCAD13
CBS_BCAD12
CBS_BCAD15
CBS_BCAD14

CBS_BCAD16
CBS_BCCBE1#
CBS_BCRSV2/A18
CBS_BCPAR
CBS_BCBLOCK#
CBS_BCPERR#
CBS_BCSTOP#

CBS_BCGNT#
CBS_BCDEVSEL#

CBS_BCCLK
CBS_BCTRDY#
CBS_BCIRDY#

CBS_BCFRAME#
CBS_BCCBE2#
CBS_BCAD17
CBS_BCAD18
CBS_BCAD19
CBS_BCAD20
CBS_BCVS2

CBS_BCAD21
CBS_BCAD22

CBS_BCSERR#
CBS_BCAD23
CBS_BCREQ#
CBS_BCAD24

CBS_BCCBE3#
CBS_BCAD25

CBS_BCAD26
CBS_BCSTSCHNG
CBS_BCAD27
CBS_BCAD28

CBS_BCAD29
CBS_BCAD30
CBS_BCRSV3/D2
CBS_BCAD31
CBS_BCCLKRUN#

CBS_ACRST#

CBS_BCRST#

CBS_BCD1# 28

CBS_BCRSVD/D14 28CBS_ACRSVD/D1428

CBS_BCCBE0# 28

CBS_BCVS1 28

CBS_BCCBE1# 28
CBS_BCRSV2/A18 28
CBS_BCPAR 28
CBS_BCBLOCK# 28
CBS_BCPERR# 28
CBS_BCSTOP# 28

CBS_BCDEVSEL# 28

CBS_BVCC

CBS_BVPP

CBS_BCCLK 28
CBS_BCTRDY# 28
CBS_BCIRDY# 28

CBS_BCFRAME# 28
CBS_BCCBE2# 28

CBS_BCVS2 28

CBS_BCRST# 28

CBS_BCSERR# 28

CBS_BCREQ# 28

CBS_BCCBE3# 28

CBS_BCAUDIO 28

CBS_BCSTSCHNG 28

CBS_BCRSV3/D2 28CBS_ACRSV3/D228
CBS_BCCLKRUN# 28

CBS_BCD2# 28

1

C499

0.01U_0402_16V7K

2

2

C509

0.01U_0402_16V7K

1

CBS_BCAD[0..31] 28

CBS_BCGNT# 28

CBS_BCINT# 28

3: TPA#
4: TPA

Security Cla ssification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONIC S, INC. AND CONTAI NS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

3

2005/09/10 2006/06/23

Compal Secret Data

Deciphered Date

Title

Size Docu m e n t N u m b e r Re v

2

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, M/B LA-3051P

星期四

401397

06, 2005

十月

1

29 45,

A

of

A

B

C

D

E

F

G

H

MDC CONN.

MDC_ACZ_SDOUT

+3VS

1

2

MDC_ACZ_BITCLK

1

C202

C216

2

4.7U_0805_10V4Z

@

10P_0402_50V8J

0.1U_0402_16V4Z

MDC_ACZ_BITCLK_TERM

C422

1 2

1

2

R403

@

10_0402_5%

R412

@

1 2

MDC_ACZ_SDOUT_MDCTERM

C439

1

@

2

10_0402_5%

10P_0402_50V8J

Adjustable Output

U30

4

VIN

2

SENSE or ADJ

DELAY
ERROR7CNOISE

C212

1 1

C211

0.1U_0402_16V4Z

4.7U_0805_10V4Z

+5VS

1 2

R201 10K_0402_5%

8

SD

SI9182DH-AD-T1-E3_MSOP8~N

VOUT

GND

5
6
1
3

C498 0.01U_0402_16V7K

R203

30.1K_0402_1%

1 2

12

R204
10K_0603_1%

+VDDA+5VS

1

2

C214 4.7U_0805_10V4Z

C213 0.1U_0402_16V4Z

JP8

1

R404

ACZ_SDIN120

1 2

33_0402_5%

MDC_ACZ_SDOUT

MDC_ACZ_SYNC

MDC_ACZ_RST#

MDC_ACZ_SDOUT20
MDC_ACZ_SYNC20
MDC_ACZ_RST#20

1 2

C440 10P_0402_50V8J@

1 2

C450 10P_0402_50V8J@

1 2

C444 10P_0402_50V8J@

MDC_ACZ_SDOUT
MDC_ACZ_SYNC

AC97_SDIN1_MDC
MDC_ACZ_RST#

GND1

3

IAC_SDATA_OUT

5

GND2

7

IAC_SYNC

9

IAC_SDATA_IN

11

IAC_RESET#

IAC_BITCLK

131314141515161617171818191920

check Azalia MDC Module

2

RES0

4

RES1

6

3.3V

8

GND3

10

GND4

12

20

ACES_88023-12001~N

Connector for MDC Rev1.5

MDC_ACZ_BITCLK20

W=20 mil

MDC_ACZ_BITCLK

HD Audio Codec

20mil

DVDD11DVDD2

MONO_O

BIT_CLK

SDATA_IN

GPIO2

GPIO3

VREF

DCVOL

SENSE B

GPIO0
GPIO1

LFILT
AVSS1
AVSS2

0.1U_0402_16V4Z

9

35
36
37
39
41

6
8
2

3
29
30
28
27
32

31
33
34
43
44

40
26
42

1

1

2

LINEL
LINER

HP_LOUT
HP_ROUT

R440 0_0402_5%

AC97_SDIN0_CODEC

10mil

10mil

C472

C473

2

0.1U_0402_16V4Z

C520 1000P_0402_50V7K~N@
C521 1000P_0402_50V7K~N@

C492 1000P_0402_50V7K~N@
C497 1000P_0402_50V7K~N@

1 2

R441

R533 0_0402_5%

MIC1_VREFO_L

MIC1_VREFO_R

1 2

2 2

L31

+VDDA

3 3

ACZ_RST#20
ACZ_SYNC20
ACZ_SDOUT20

4 4

1 2

FBM-L11-160808-800LMT_0603

10U_1206_16V4Z

MIC131
MIC231

2

2

C446

1

@

10P_0402_25V8K

C436

C451

1

@

@

10P_0402_25V8K

10P_0402_25V8K

2

1

1

C529

2

C493 1U_0603_10V6K
C500 1U_0603_10V6K

EAPD31

R449

0_0402_5%@

1 2

0.1U_0402_16V4Z

1

C519

2

1 2
1 2

R199 0_0603_5%

40mil

1

C506

2

0.1U_0402_16V4Z

C_MIC1
C_MIC2

@

1 2

For EMI

DGND AGND

+AVDD_AC97

38

U25

AVDD125AVDD2

14

LINE2_L

15

LINE2_R

16

MIC2_L

17

MIC2_R

23

LINE1_L

24

LINE1_R

18

CD_L

20

CD_R

19

CD_GND

21

MIC1_L

22

MIC1_R

13

SENSE A

12

PC_BEEP

11

RESET#

10

SYNC

5

SDATA_OUT

45

NC

46

NC

47

SPDIFI/EAPD

48

SPDIFO

4

DVSS1

7

DVSS2

ALC262-GR_LQFP48-N

LINE_OUT_L
LINE_OUT_R

HP_OUT_L
HP_OUT_R

LINE1_VREFO

MIC2_VREFO

MIC1_VREFO_L

MIC1_VREFO_R

LINE2_VREFO

1

C474
10U_1206_16V4Z

2

10_0402_5% @

12

AC97_VREF

12

R455
20K_0402_1%

For EMI

0_0603_5%

1 2

R438

10P_0402_25V8K

R408

0_0402_5%

R379

10K_0402_5%

1 2

12

+3VS

R500 0_0603_5%
R499 0_0603_5%

R481 0_0603_5%

1 2

C421

@

ACZ_BITCLK 20

ACZ_SDIN0 20
EAPD
31

10mil

1

2

1 2
1 2

1 2
1 2

R459 0_0603_5%

C526
10U_0805_10V4Z~N

AMP_LEFT 31
AMP_RIGHT 31

HP_LEFT 31
HP_RIGHT 31

Reserved for TEST

1 2

R518 0_0805_5%

1 2

R447 0_0805_5%

1 2

R451 0_0805_5%

1 2

R452 0_0805_5%

GND AGND

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

C

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

D

2005/09/10 2006/06/23

Compal Secret Data

Deciphered Date

E

Title

Size Document Number Rev

F

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, M/B LA-3051P

星期四

G

401397

06, 2005

十月

30 45,

H

A

of

A

W=40Mil

1

1

2

2

12

R514
10K_0402_5%

C548
10U_0805_10V4Z~N

7

RIN+

17

RIN-

9

LIN+

5

LIN-

19

SHUTDOWN

20

NBA_PLUG#

C546

0.1U_0402_16V4Z

4 4

AMP_RIGHT30

AMP_LEFT30

3 3

EC_MUTE32

EC_MUTE

C547

0.47U_0603_16V4Z

C545

0.47U_0603_16V4Z

C551

0.47U_0603_16V4Z

C544

0.47U_0603_16V4Z

+3VS

12

R513
100K_0402_5%

13

D

Q40

2

2N7002_SOT23

G

S

1 2

1 2

1 2

1 2

AMP_R

AMP_L

B

PVDD2

GAIN0
GAIN1

ROUT+

ROUT-

LOUT+

LOUT-

BYPASS

2

G

NC

U32

2
3

18

14

4

8

12
10

13

D

Q41
2N7002_SOT23

S

16

15

6

VDD

PVDD1

GND41GND311GND213GND1

TPA6017A2PWPRG4_TSSOP20~N

+5VS

+5VS

R502 10K_0402_5%
R501 10K_0402_5%@

1

0.47U_0603_16V4Z
C553

2

1 2
1 2

SPK_R1

SPK_R2

SPK_L1

SPK_L2

C

R510 10K_0402_5%

1 2

R511 10K_0402_5%@

1 2

1 2

R206 0_0603_5%

1 2

R210 0_0603_5%

1 2

R207 0_0603_5%

1 2

R211 0_0603_5%

INTSPK_R1

INTSPK_R2

INTSPK_L1

INTSPK_L2

GAIN0 GAIN1 GAIN

00

0

1

6dB

10dB

MIC230
MIC130

HP_OUTR
HP_OUTL

D

1 2

L32 CHB2012U170_0805

1 2

L30 CHB2012U170_0805

R509 47_0402_5%

1 2

R506 47_0402_5%

1 2

1K_0402_5%@

Speaker Connector

INTSPK_R1
INTSPK_R2
INTSPK_L1
INTSPK_L2

MICROPHONE IN JACK

R4983K_0402_5%

12
12

R4923K_0402_5%

220P_0402_50V7K

MIC-2
MIC-1

C507

MIC1_VREFO_R
MIC1_VREFO_L

1

2

220P_0402_50V7K

HEADPHONE OUT JACK

0.1U_0402_16V4Z

1 2

L34 CHB2012U170_0805

1 2

L33 CHB2012U170_0805

R515
1K_0402_5%@

470P_0402_50V7K

HPR
HPL

C532

HP_R
HP_L

R503

12

NBA_PLUG#

12

JSPK1

1

1

2

2

3

3

4

4

5

G1

6

G2

MOLEX_53398-0471~N

1

C522

2

C552

2

1

E

JP11

5
4
3

6
2
1

FOX_JA6333L-B1ST-7F~N

+3VS

12

12

2

C542
470P_0402_50V7K

1

R517
10K_0402_5%

JP14

5
4
3

6
2
1

FOX_JA6333L-B1ST-7F~N

EAPD30

EAPD

0

1

1

Buzzer need to support ICH/PCM_SPK/Battery_low and WL_on/off

2 2

+5VS

BUZR_OFF32

EC Beep

0.1U_0402_16V4Z

A

1 2

R378
0_0402_5%

BUZR_OFF32

1 2

R377
0_0402_5%

BUZR_OFF32

1 2

R365
0_0402_5%

BEEP#32

CardBus Beep

PCM_SPK#28

1 1

ICH Beep

SB_SPKR21

C396

BUZR

+3VS

12

14

P
I2O

G

7

I5O

I9O

1

U15A

3

OE#

SN74LVC125APWLE_TSSOP14

4

U15B

6

OE#

SN74LVC125APWLE_TSSOP14

10

U15C

8

OE#

SN74LVC125APWLE_TSSOP14

R375
10K_0402_5%@

1 2

B

R371
0_0402_5%@

12

12

R374

56.2_0603_1%

12

C399
1U_0805_50V4Z

BUZZER

1

C

Q24

2

B

2SC2411K_SC59

E

3

D29

CH751H-40_SC76@

2 1

BUR1

+

1
2

-

LET9040-03A_2P

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITT EN CON SENT O F COMPAL ELECTRONICS, INC.

C

15.6dB

21.6dB1

2005/09/10 2006/06/23

Compal Secret Data

NBA_PLUG#

EAPD

HP_RIGHT30

HP_LEFT30

Deciphered Date

1 2

R202 0_0402_5%

1 2

R200 0_0402_5%

+3VS

5

U8

2

P

B

4

Y

1

A

G

NC7SZ08P5X_NL_SC70-5

3

HP_MUTE#

R507

6.8K_0603_5%

HP_INR HPINR

1 2

C537 2.2U_0603_6.3V4Z

1 2

C543 2.2U_0603_6.3V4Z

D

1 2

HP_INL HPINL

1 2

R512

6.8K_0603_5%

+3VS

HP_MUTE#

14
18

15
13

1

C512
1U_0603_10V4Z

2

1
3

Title

SCHEMATIC, M/B LA-3051P

Size Document Number Rev

星期

Date: Sheet

Reserve the 0 ohm resistor.

12

for voltage filtering

R497

0_0603_5%

1 2

C527 1U_0603_10V4Z

10

19

U31

SHDNR#
SHDNL#

INR
INL

C1P
C1N

PVDD

PVss

SVss

5

7

1

C515
1U_0603_10V4Z

2

SVDD

2

PGND

11

OUTR

9

OUTL

4

NC-4

6

NC-6

8

NC-8

12

NC-12

16

NC-16

20

NC-20

SGND

MAX4411ETP+T_TQFN20~N

17

Compal Electronics, Inc.

401397

, 06, 2005

四十月

E

HP_OUTR
HP_OUTL

31 45

A

of

5

PCI_CLKRUN# EC_CLKRUN#

PCI_CLKRUN#2 1,28,43

D D

C398 0.1 U _0402_16V4Z

12

+3V_EC

CB_PME#28

C C

WLAN_PME#43

PCIE_PME#25

+3V_EC

1 8
2 7
3 6
4 5

+3V_EC

1 8
2 7
3 6
4 5

+5VALW

1 8
2 7
3 6
4 5

B B

+5VS

+3VS

10K_0402_5%

1

C447

2

A A

10P_0402_50V8J

32.768KHZ_12.5P_1TJS125DJ2A073

12

R372 47K_0402_5%

RP43

MAIL#
NET#
LID_SW#

10K_1206_8P4R_5%

RP21

FRD#

FSEL#

100K_1206_8P4R_5%

RP42

EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2

4.7K_1206_8P4R_5%

12

R3974.7K_0402_5%

12

R4004.7K_0402_5%

BT_EXIST#

R167

R422

1 2

20M_0603_5%@

4

1

Y5

IN

OUT

NC3NC

2

1 2

0_0402_5%

ECRST# PCIRST_EC#

+3V_EC

1 2

21

D33CH751H-40_SC76

21

D32CH751H-40_SC76

21

D31CH751H-40_SC76

TP_CLK

TP_DAT

CRY2CRY1

1

C448

2

10P_0402_50V8J

5

R370

R392
10K_0402_5%

EC_PME#

R369

@

1K_0402_5%

1 2

+3VALW

R418

0_0805_5%

KSI[0..7]33

KSO[0..15]33

EC_PME# 19

12

0.1U_0402_16V4Z

PAD

1

C416

2

0.1U_0402_16V4Z

LPC_FRAME#20

CLK_PCI_EC17

EC_SMB_DA26,10,23,37
EC_SMB_CK26,10,23,37
EC_SMB_DA133,37
EC_SMB_CK133,37

SCROL_LED#33

EC_RSMRST#21

EC_LID_OUT#21

1

2

PWR_STA2#33
PWR_STA1#33
NUM_LED#33
BAT1_LED#33
BAT2_LED#33
CAPS_LED#33

SLP_S5#21

PBTN_OUT#21

C184

GATEA2020
KB_RST#20
SERIRQ21,28

LPC_AD320
LPC_AD220
LPC_AD120
LPC_AD020

PLT_RST#9,19,21,25,27
EC_SCI#21

KBSEL0#33
KBSEL1#33

SYSON34,40

BKOFF#18

SLP_S3#21

EC_SMI#21
EC_SWI#21
LID_SW#33

SUSP#33,34,40,41

E51_TXD

4

0.1U_0402_16V4Z

1

C397

2

0.1U_0402_16V4Z

SERIRQ
LPC_FRAME#
LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0
CLK_PCI_EC

ECRST#
EC_CLKRUN#

E51_TXD

4

EC_PME#

CRY1
CRY2

2

1

C420

1

2

1000P_0402_50V7K~N

U17

1

GA20/ GPIO00/GA20

2

KBRST#/GPIO01/KBRST#

3

SERIRQ

5

LPC_FRAME# / LFRAME#

6

LPC AD3/LAD3

9

LPC AD2/LAD2

10

LPC AD1/LAD1

12

LPC AD0/LAD0

14

CLK_PCI_EC/PCICLK

15

PCIRST#

42

EC RST#/ ECRST#

24

EC SCI#/SCI#/GPIO0E

44

PM_CLKRUN#/ CLKRUN#

KSI0

63

KSI0/GPIO30

KSI1

64

KSI1/GPIO31

KSI2

65

KSI2/GPI032

KSI3

66

KSI3/GPIO33

KSI4

67

KSI4/GPIO34

KSI5

68

KSI5/GPI035

KSI6

69

KSI6/GPIO36

KSI7

70

KSI7/GPIO37

KSO0

47

KSO0/GPIO20

KSO1

48

KSO1/GPIO21

KSO2

49

KSO2/GPIO22

KSO3

50

KSO3/GPIO23

KSO4

51

KSO4/GPIO24

KSO5

52

KSO5/GPIO25

KSO6

53

KSO6/GPIO26

KSO7

54

KSO7/GPIO27

KSO8

55

KSO8/GPIO28

KSO9

56

KSO9/GPIO29

KSO10

57

KSO10/GPIO2A

KSO11

58

KSO11/GPIO2B

KSO12

59

KSO12/GPIO2C

KSO13

60

KSO13/GPIO2D

KSO14

61

KSO14/GPIO2E

KSO15

62

KSO15/GPIO2F

89

EC URXD/KSO16/GPIO48

90

EC UTXD/KSO17/GPIO49

88

EC SMD2/ GPIO47/SDA2

87

EC SMC2/GPIO46/SCL2

86

EC SMD1/GPIO44/SDA1

85

EC SMC1/GPIO44/SCL1

34

PCM_SPK#/EMAIL_LED#/ GPIO16

35

SB_SPKR/PWR_SUSP_LED#/ GPIO17

38

PWRLED#/ GPIO19

40

NUMLED#/ GPIO1A

99

BATT CHGI LED#/ E51CS#

101

BATT LOW LED#/ E51MR0

100

CAPS LED#/ E51TMR1

102

ARROW LED#/ E51 INT0

104

SYSON/GPIO56/ E51 INT1

4

EC_RSMRST#/ GPIO02

7

BKOFF#/GPIO03

8

PM SLP S3#/GPIO04

16

EC LID OUT#/GPIO06

17

PM SLP S05#/ GPIO07

18

EC SMI#/GPIO08

19

EC SWI#/GPIO09

20

LID SW#/ GPIO0A

21

SUSP#/GPIO0B

22

PBTN_OUT#/GPIO0C

23

EC PME#/GPIO0D

140

XCLKO

138

XCLKI

C406

2

1

+3V_EC

L26

1 2

FBM-L11-160808-800LMT_0603

C445
1000P_0402_50V7K~N

127

141

11

26

105

VCC

VCC/ EC VCC

VCC / EC VCC

Host

INTERFACE

key Matrix

scan

VCC / EC VCC37VCC / EC VCC

PWR

FAN/PWM

FAN SPEED1/GPIO14/FANFB1
FAN SPEED2/GPIO15/FANFB2

PS2 interface

SM BUS

GND13GND28GND39GND

GND

GND

103

129

139

FBM-L11-160808-800LMT_0603

Security Class i f ication

THIS SHEET OF ENGINEERING DRAWING IS THE PR OPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. A ND CONTAINS CONFIDENTI AL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NO T BE TRANSFERED FROM THE C USTODY OF T HE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SH EET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WIT HOUT PRIOR WRITTEN CONSENT OF COMPA L ELECTRONI CS, INC.

3

+3VCCA_EC

1

C402

2

0.1U_0402_16V4Z

ECAGND

+3VCCA_EC

75

BATTEMP/AD0/GPIO38

BATT OVP/AD1/GPIO39

VCC

ADP_I/AD2/GPIO3A

AD BID0/AD3/GPIO3B

AD INtput or GPI

EC_AVCC / AVCC

DAC_BRIG/DA0/GPIO3D

EN DFAN1/DA1/GPIO3D

IREF2/DA2

EN DFAN2/DA3/ GPIO3F

DA output or GPO

INVT_PWM/GPIO0F/PWM1

BEEP#/GPIO10/PWM2

OUT BEEP/GPIO12/PWM3

ACOFF/GPIO18/PWM4

ADB0/D0
ADB1/D1
ADB2/D2

Data

ADB3/ D3

BUS

ADB4/D4
ADB5/D5
ADB6/D6
ADB7/D7
KBA0/A0
KBA1/A1
KBA2/A2
KBA3/A3
KBA4/A4
KBA5/A5

BUS

SELIO2#/ GPIO43

SELIO#/ GPIO50

FSEL#/SELMEM#

EC ON/ GPIO1B

AC IN/ GPIO1C

ECTHERM#/GPIO11

ONOFF/GPIO18

PCMRST#/GPIO1E

WL OFF#/GPIO1F

ALI/MH#/GPIO40

FSTCHG/GPIO41

VR ON/ GPIO42
GPIO57/GPIO57
GPIO58/GPIO58
GPIO59/GPIO59

AGND

77

ECAGND

KBA6/A6
KBA7/A7
KBA8/A8

KBA9/A9
KBA10/A10
KBA11/A11
KBA12/A12
KBA13/A13
KBA14/A14
KBA15/A15
KBA16/A16
KBA17/A17
KBA18/A18
KBA19/A19

FRD#/RD#

FWR#/WR#

Address

Issued Date

3

BATT_TEMP_A

71
72
73

BATT_TEMP_B

74

76
78
79
80

25
27
30

1 2

R387 0_0402_5%

31
32
33

BT_EXIST#

91

PSCLK1

92

PSDAT1

93

PSCLK2

94

PSDAT2

95

PSCLK3

96

PSDAT3

ADB0

125

ADB1

126

ADB2

128

ADB3

130

ADB4

131

ADB5

132

ADB6

133

ADB7

134

KBA0

111

KBA1

112

KBA2

113

KBA3

114

KBA4

115

KBA5

116

KBA6

117

KBA7

118

KBA8

119

KBA9

120

KBA10

121

KBA11

122

KBA12

123

KBA13

124

KBA14

110

KBA15

109

KBA16

108

KBA17

107

KBA18

106

KBA19

98
84

SELIO

97
135
136
144

41
43
29
36
45

BAY_TYPE

46
81

82
83
137

1 2

R175 0_0402_5%

142
143

KB910LQF A1_LQFP144~N

L27

12

2005/09/10 2006/06/23

C404 0. 01U_0402_16V7K

C400 0. 01U_0402_16V7K

DAC_BRIG 18
EN_FAN1 6
IREF
EN_WOL# 34

INVT_PWM 18
BEEP# 31
VGATE 19,21,42
ACOFF
FAN1_SPEED 6
FINGERPRINT# 33

BT_EXIST# 24
TRICKE 37
MAIL# 33
NET# 33
TP_CLK 33

TP_DAT 33

ADB[0..7]
KBA[0..19]

CBS_SPND# 28
FRD# 33

FWR# 33
FSEL# 33

EC_ON 33,39
A/B#USE 37

ON/OFF# 33

HDD_EN# 23

BAY_TYPE 23
BT_DIS#

FSTCHG 37
VR_ON 42

ICH_POK 19,21,23
GSENSOR 23
LAN_LOW_PW R 25

Compal Secret Data

Deciphered Date

ECAGND

12

BATT_OVP
ADP_I

ECAGND

12

+3V_EC

R373

10K_0402_5%@

1 2

2 1

CH751H-40_SC76@

1 2

R367 0_0402_5%

2

ADB[0..7] 33
KBA[0..19] 33

D25

2

BATT_TEMPA 37

BATT_TEMPB 37

KBA2
SELIO

+3VS

+3V

12mA

PCI_AD[0..31]19,28,43

PCI_CBE#019,28,43

PCI_CBE#119,28,43
PCI_CBE#219,28,43
PCI_CBE#319,28,43

ADB0

3

D0

ADB1

D14Q1

ADB2

+3VALW

1 2

C4540.1U_0402_16V4Z

5

U22

2

B

4

Vcc

Y

1

A

G

NC7SZ32P5X_NL_SC70-5

3

1 2

+3VALW

R444 20K_0402_5%

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3

ACIN 21,35,39

PCI_AD[0..31]

PCI_AD619, 28,43
PCI_AD419, 28,43
PCI_AD219, 28,43
PCI_AD019, 28,43
PCI_AD119, 28,43
PCI_AD319, 28,43
PCI_AD519, 28,43
PCI_AD719, 28,43
PCI_AD819, 28,43

CLK_PCI_LPC17

PCI_RST#1 9,28,43
PCI_FRAME#19,28,43

PCI_TRDY#19,28,43

PCI_AD919, 28,43

PCI_AD6
PCI_AD4
PCI_AD2
PCI_AD0
PCI_AD1
PCI_AD3
PCI_AD5
PCI_AD7
PCI_AD8

+5VS

PCI_AD9

Title

Size Document Number Rev

Date: Sheet of

D27Q2

ADB3

D38Q3

ADB4

D413Q4

ADB5

D514Q5

ADB6

D617Q6

ADB7

D718Q7

11

CP

1

MR

C485

1 2

1U_0603_10V6K

JP15

2

1

4

3

6

5

8

7

10

9

12

11

14

13

16

15

18

17

20

19

NAIS_AXK5S20045J~N

0.5A per each pin

R134 33_0402_5%
R135 33_0402_5%
R136 33_0402_5%
R137 33_0402_5%
R138 33_0402_5%
R139 33_0402_5%
R140 33_0402_5%
R141 33_0402_5%
R142 33_0402_5%
R143 33_0402_5%
R144 33_0402_5%
R145 33_0402_5%
R146 33_0402_5%

R147 33_0402_5%
R148 33_0402_5%

R149 33_0402_5%
R150 33_0402_5%
R151 33_0402_5%

Compal Electronics, Inc.

SCHEMATIC, M/B LA-3051P

401397

星期四

Q 06, 2005

月

1

+5VALW

1 2

C467 0.1 U _0402_16V4Z

U24

20

2

Q0

5

VCC

6
9
12
15
16
19

GND

SN74HCT273PWR_TSSOP20~N

10

LPC_FRAME#
SERIRQ

PCI_CLKRUN#

20

12

19

12

18

12

17

12

16

12

15

12

14

12

13

12

12

12

11

12

10

12

9

12

8

12

7
6

12

5
4

12

3

12

2

12

1

12

1

BUZR_OFF 31
EC_MUTE 31

AUX_S5EN
WL_OFF# 24,27,33,43

PLT_RST# 9,19, 21,25,27

CLK_PCI_TPM 17

ACES_85201-2005

20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

JP6

32 45, 

A

EC_SMB_CK132,37

+3VS

EC_ON32,39

EC_SMB_DA132,37

CAPS_LED#32

MAIL#32

+3VS

+5VALW

+5VS

PWR_BTN#

PASSWORD#

FINGERPRINT#32

KBSEL0#32
KBSEL1#32

RP22

1 8
2 7
3 6
4 5

1 2

R213 10K_0402_5%

PWR_BTN#

KBSEL1#
KBSEL0#
FINGERPRINT#

10K_1206_8P4R_5%

PASSWORD#

+3VALW

1 2

EC_ON

1 2

13

D

S

C437

0.1U_0402_16V4Z

1 2

U20

8

VCC

7

WP

6

SCL

5

SDA

JSW1

112
334
556
778
9910
111112

ACES_87153-1241L~N

KBSEL0#
KBSEL1#

+3V_EC

R368

100K_0402_5%

D27

1

CHN202U_SC70

2

Q25

2N7002_SOT23@

GND

1
2
3
4
5
6
7
8 9

3
2

AT24C16AN-10SU-2.7_SO8~N

PASSWORD#

FINGERPRINT#

R366

4.7K_0402_5%@

R363

33K_0603_1%@

DTC124EK_SC59@

Q23

2

G

1

A0

2

A1

3

A2

4

2
4
6
8
10
12

SW1

HPS608-E_16P

1 2

13

+5VALW

12

R416
100K_0402_5%

12

R432
100K_0402_5%

ONOFF

ON

16
15
14
13
12
11
10

1000P_0402_50V7K~N@

2 1

D26 C H 751H-40_SC76@

2 1

D28 C H 751H-40_SC76@

0.1U_0402_16V4Z

IDE_LED# 23
NUM_LED# 32
SCROL_LED# 32
NET# 32

C395

C459

FWE#

KSO[0..15]32

KSI[0..7]32

TP_CLK32
TP_DAT32

ON/OFF# 32

D24

12

MMGZ5248B_LL34@

2 1

+3VALW

12

5

U21

B

4

Vcc

Y

A

G

NC7SZ32P5X_NL_SC70-5

3

1 2

R431 0_0402_5%@

WLAN_ACT_GOLAN27

WLAN_ACT_CALE43

MAIL# 32

NET# 32

1MB Flash ROM

KBA[0..19]32
ADB[0..7]32

+3V_EC

+3VALW

2
1

R162 0_0603_5%

1 2
1 2

R161 0_0603_5%

+3VS

+3VS

KBA[0..19]
ADB[0..7]

1 2

R426 10K_0402_5%

12

R428
100K_0402_5%

1 3

D

KSO15
KSO14
KSO13
KSO12
KSO11
KSO10
KSO9
KSO8
KSO7
KSO6
KSO5
KSO4
KSO3
KSO2
KSO1
KSO0

KSI7
KSI6
KSI5
KSI4
KSI3
KSI2
KSI1
KSI0

1

C157

2

10P_0402_50V8J

1 2

R519 100K_0402_5%

1 2

R522 100K_0402_5%

2

G

MOUSECLK
MOUSEDAT

C156

+3V_EC

+3V_EC

1 2

R495 10K_0402_5%

FWE#

Q31
2N7002_SOT23

S

FWR# 32

SUSP# 32,34,40,41

EC_FLASH# 21

FSEL#32
FRD#32

KBA0

21

KBA1

20

KBA2

19

KBA3

18

KBA4

17
16

KBA6

15

KBA7

14

KBA8
KBA9
KBA10
KBA11
KBA12
KBA13
KBA14
KBA15
KBA16
KBA17
KBA18
KBA19

FSEL#
FRD#
FWE#

8
7

36

6
5
4
3
2

1
40
13
37

22
24

9

SST39VF080-70-4C-EIE_TSOP40~N

U27

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19

CE#
OE#
WE#

VCC0
VCC1

READY/BUSY#

NC0
NC1

GND0
GND1

RP#

31
30

ADB0

25

D0
D1
D2
D3
D4
D5
D6
D7

NC

26
27
28
32
33
34
35

10
11
12
29
38

23
39

ADB1KBA5
ADB2
ADB3
ADB4
ADB5
ADB6
ADB7

BIOS_RST#

KEYBOARD CONN.

KSI7
KSI6
KSI5
KSI4
KSI3
KSI2
KSI1
KSI0
KSO15
KSO14
KSO13
KSO12
KSO11
KSO10
KSO9
KSO8
KSO7
KSO6
KSO5
KSO4
KSO3
KSO2
KSO1
KSO0

6781

CP6

100P_1206_8P4C_50V8

+3VS

5

U34

2

P

B

Y

1

A

G

NC7SZ08P5X_NL_SC70-5

3

1

2

10P_0402_50V8J

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITT EN CON SENT O F COMPAL ELECTRONICS, INC.

6781

CP5

234 5

100P_1206_8P4C_50V8

4

2005/09/10 2006/06/23

6781

CP4

234 5

100P_1206_8P4C_50V8

2

G

+3VS

234 5

12

R532
10K_0402_5%

WLAN_ACT

13

D

Q45

S

BSS138_SOT23

6781

CP3

100P_1206_8P4C_50V8

CP2

234 5

100P_1206_8P4C_50V8

+5VS

FBM-L11-321611-260-LMT_1206

PWR_STA2#32
BAT2_LED#32

LID_SW#32

Compal Secret Data

Deciphered Date

6781

6781

CP1

234 5

100P_1206_8P4C_50V8

234 5

Touch-Pad CONN.

C151

1 2

MOUSEVDD

L15

WLAN_ACT

+5V +5VALW

12

1

C514

0.1U_0402_16V4Z

2

RP20 0_1206_8P4R_5%

4 5
3 6
2 7
1 8

RP19 0_1206_8P4R_5%

4 5
3 6
2 7
1 8

RP18 0_1206_8P4R_5%

4 5
3 6
2 7
1 8

RP17 0_1206_8P4R_5%

4 5
3 6
2 7
1 8

RP16 0_1206_8P4R_5%

4 5
3 6
2 7
1 8

RP15

4 5
3 6
2 7
1 8

KBA14
KBA13
KBA12
KBA11
KBA10

KBA9
KBA8
KBA7
KBA6
KBA5
KBA4
KBA3
KBA2
KBA1
KBA0

BIOS_RST#

0_1206_8P4R_5%

DEVICE SEL

GOLAN
Calexico

0.1U_0402_16V4Z

JPALM1

2

112
334
556
778
9910

11

12

11

13

14

13
151516

17

17

18

19

19

20

ACES_87153-2041L~N

MOUSECLK

4

MOUSEDAT

6
8
10
12
14
16
18
20

Title

SCHEMATIC, M/B LA-3051P

Size Document Number Rev

星期

四十月

Date: Sheet

Debug Tool

JP18

1 2
3 4
5 6
7 8
9 10
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
29 30
31 32
33 34

SUYIN_127212FA034G200ZX@

KBD24
KBD23
KBD22
KBD21
KBD20
KBD19
KBD18
KBD17
KBD16
KBD15
KBD14
KBD13
KBD12
KBD11
KBD10
KBD9
KBD8
KBD7
KBD6
KBD5
KBD4
KBD3
KBD2
KBD1

JKB1

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

11

11

12

12

13

13

14

14

15

15

16

16

17

17

18

18

19

19

20

20

21

21

22

22

23

23

24

24

ACES_85203-2402L~N

FSEL#
FRD#
FWE#
ADB7
ADB6
ADB5
ADB4
ADB3
ADB2
ADB1
ADB0
KBA19
KBA18
KBA17
KBA16
KBA15

25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48

+3V_EC

25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48

ABCD

PWR_STA1# 32
BAT1_LED# 32

R520
R521 0_0402_5% @

R523 100K_0402_5%

R524 0_0402_5%

OO
XX

1 2

D

1 2

C

B

1 2

A

0_0402_5% @

XX
OO

WL_OFF# 24,27,32,43
WLAN_LINK 43

12

WL_OFF# 24,27,32,43

Compal Electronics, Inc.

401397

, 06, 2005

33 45

KBD24
KBD23
KBD22
KBD21
KBD20
KBD19
KBD18
KBD17
KBD16
KBD15
KBD14
KBD13
KBD12
KBD11
KBD10

KBD9
KBD8
KBD7
KBD6
KBD5
KBD4
KBD3
KBD2
KBD1

of

*

A

A

B+_BIAS

R390
470K_0402_5%

1 1

EN_WOL25

1 2
13

D

S

Q26

2

2N7002_SOT23

G

EN_WOL# 32

B

C

D

E

+3VALW TO +3VS

+3VALW +3VS

Q43

S

D

S

D

S

D

G

D

AO4422L_SO8~N

1
2
3
4

8
7
6
5

1

2 2

C550

2

4.7U_0805_10V4Z

1

C534

1U_0603_10V4Z

2

1 2

R505 10K_0402_5%

1

C535

2

0.1U_0603_50V4Z

4.7U_0805_10V4Z

1

C531

2

RUN_ON SUSON

SUSP

R504

2

G

470_0805_5%

1 2
13

D

Q39
2N7002_SOT23

S

+5VALW TO +5VS

+5VALW

Q33

8

D

7

D

6

D

5

D

SI4362DY_SO8

1

C452

2

3 3

4.7U_0805_10V4Z

SUSP24,41

SUSP#32,33,40,41 SYSON32,40

4 4

C475

1

S

2

S

3

S

4

G

1

2

0.1U_0603_50V4Z

R433

10K_0402_5%

+5VS

1

2

1U_0603_10V4Z

RUN_ON

C456

SUSP

1 2

4.7U_0805_10V4Z

C481

R437

1 2

20K_0402_5%

13

D

2

2N7002_SOT23

G

Q34

S

+5VALW

1 2
13

D

2

G

S

1

2

R425
100K_0402_5%

Q32
2N7002_SOT23

R445

B+_BIAS

SUSP SYSON#SYSON#

470_0805_5%

1 2
13

D

Q35

2

2N7002_SOT23

G

S

+3VALW TO +3V

+3VALW +3V

8
7
6
5

1

C549

2

4.7U_0805_10V4Z

+5VALW TO +5V

+5VALW

Q37

8
7
6
5

AO4422L_SO8~N

1

C495

2

4.7U_0805_10V4Z

SYSON#

R396

10K_0402_5%

1 2

Q42

S

D

S

D

S

D

G

D

AO4422L_SO8~N

S

D

S

D

S

D

G

D

+5VALW

1 2
13

D

2

G

S

C528

1
2
3
4

1

C539

2

0.1U_0603_50V4Z

C491

1
2
3
4

1U_0603_10V4Z

SUSON

1

C479

2

0.1U_0603_50V4Z

R394
100K_0402_5%

Q27
2N7002_SOT23

4.7U_0805_10V4Z

1

C540

1U_0603_10V4Z

2

1 2

R508 47K_0402_5%

+5V

4.7U_0805_10V4Z

1

C489

2

1 2

22K_0402_5%

13

D

2

2N7002_SOT23

G

Q36

S

+0.9VS

470_0805_5%

D

S

1

2

R446

R322

1 2
13

Q20

2

2N7002_SOT23

G

ZZZ

1

2

SUSP

SYSON#

B+_BIAS

R474

2

G

2

R516

G

1 2
13

D

S

470_0805_5%

1 2
13

D

Q38
2N7002_SOT23

S

470_0805_5%

Q44
2N7002_SOT23

H24
HOLEA

1

H4
HOLEA@

1

H8
HOLEA

1

H5
HOLEA@

1

H12
H_c236D118@

1

H25
HOLEA

LA-3051P REV 0.1 M/B

H16
HOLEA@

1

H3
HOLEA@

1

H14

H13

HOLEA@

HOLEA@

1

1

H18

H15

HOLEA

HOLEA@

1

1

H27
H_c157D118

1

H26
HOLEA@

1

1

H2
HOLEA@

1

H1
HOLEA@

1

H21
HOLEA

1

H19
HOLEA@

H9
HOLEA@

H20
HOLEA@

H17
H_O138X107D118X87@

1

1

1

1

H22
HOLEA

1

H23
HOLEA

1

FD17

1

FIDUCIAL MARK

FD8

1

FIDUCIAL MARK

FD16

1

FIDUCIAL MARK

FD13

1

FIDUCIAL MARK

FD7

1

FIDUCIAL MARK

1

FIDUCIAL MARK

1

FIDUCIAL MARK

1

FIDUCIAL MARK

1

FIDUCIAL MARK

1

FIDUCIAL MARK

H6
HOLEA@

1

FD9

FD18

FD2

FD12

FD6

H7
HOLEA@

1

1

FIDUCIAL MARK

1

FIDUCIAL MARK

1

FIDUCIAL MARK

1

FIDUCIAL MARK

H10
HOLEA@

1

FD1

FD4

FD3

FD15

H11
HOLEA@

1

FD10

1

FIDUCIAL MARK

FD14

1

FIDUCIAL MARK

FD11

1

FIDUCIAL MARK

FD5

1

FIDUCIAL MARK

For CPU

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITT EN CON SENT O F COMPAL ELECTRONICS, INC.

2005/09/10 2006/06/23

C

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

D

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, M/B LA-3051P

星期

四十月

401397

, 06, 2005

34 45

E

A

of

5

4

3

2

1

Detector

Vin Detector Threshold:

Low > High:
High > Low:

0.1U_0603_25V7K

12

PJP6
JUMP_43X118@

PJP5
JUMP_43X118@

PJP7
JUMP_43X118@

PR127

112

112

PJP4
JUMP_43X118@

112

PJP3
JUMP_43X118@

112

112

1 2

13

VIN

12

PC16

1000P_0402_50V7K~N

VS

470K_0402_5%

470K_0402_5%

PR128

1 2

2

PQ31
DTC115EUA_SC70

2

2

2

2

2

PQ13

TP0610K-T1-E3_SOT23

2

470K_0402_5%

PR129

1 2
13

PQ32
DTC115EUA_SC70

+VCCP

+1.8V

Security Classification

+0.9VS

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

13

Issued Date

N3

3

VIN

12

PR138

60.4K_0402_1%

PR53
22K_0402_1%

1 2

12

PR45

1 2

1K_1206_5%

PR49

1 2

1K_1206_5%

PR51

1 2

1K_1206_5%

12

PC35

100P_0402_50V8J~N

MAINPWON6,36,39
ACON37,38

GA37
GB37

PR139

20K_0402_1%

B+

12

PC36
1000P_0402_50V7K~N

VL

Case 1: ACIN pre-chg threshold.
Low > High:

High > Low:

13.393V

11.980V

Case 2: BATT pre-chg threshold.
Low > High:

High > Low:

2005/06/23 2006/06/23

7.547V

6.134V

Compal Secret Data

21

PC14

IN

PD18

PD17

12

2

+1.5VS

+2.5VS+2.5VSP

+3VALW

+5VALW

ADPIN

CHGRTCP

12

12

FBMA-L18-453215-900LMA90T_1812

ADPIN

12

PC13

1000P_0402_50V7K~N

VIN

PR126

CHGRTCP

1 2

12

47_1206_5%

PR195
200_0603_5%

12

PC146
1U_0805_50V4Z

ACOFF##38

+0.9VSP

4

PL4

1 2

100P_0402_50V8J~N

PD3

1N4148_SOD80

1 2

+VCCPP

+1.8VP

PC15

PC31

12

2

D D

C C

PR198

+CHGRTC

B B

A A

1 2

560_0603_5%

PJP1

1

2

3

4

SINGA_2WA-8291T041

PR197

1 2

560_0603_5%

+1.5VSP

+3VALWP

+5VALWP

5

RTCVREF

12

1

2

3

4

3.3V

3

PC147

10U_0805_6.3V6M

PJP13
JUMP_43X118@

PJP8
JUMP_43X118@

PJP12
JUMP_43X118@

PJP11
JUMP_43X118@

PJP10
JUMP_43X118@

PF2

10A_65VDC_451010

100P_0402_50V8J~N

VMBA

RB751V_SOD323

VMBB

RB751V_SOD323

PU17 G920AT24U_SOT89

OUT

GND

1

2

112

2

112

2

112

2

112

2

112

PC101

2200P_0402_50V7K~N

1 2

1 2

PD4
RB715F_SOT323

2
3

2
3

PD5
RB715F_SOT323

Deciphered Date

PR57
1M_0402_1%

1 2

3
2

PR142
10K_0402_5%

PR58
47K_0402_5%

1

1

8

+

-

4

12

PR141
56K_0402_5%

1 2

PC37

P

1

O

G

PU5A
LM393M_SO8

2

13.757V

13.160V

12

0.01U_0402_25V7K~N

RTCVREF

3.3V

LM393M_SO8

12

PC102

0.1U_0603_25V7K

PU5B

7

PR143
1M_0402_1%

O

VINVL

12

12

PR54
1K_0402_5%

1 2

12

PR52

PR140
10K_0402_5%

PACIN

12

PR55

PD19

MMPZ5229BPT_SC76

12

8

P

+

-

G

4

10K_0402_5%

5
6

PQ33

2N7002-7-F_SOT23-3

Title

SCHEMATIC, M/B LA-3051P

Size Document Number Rev

Custom

星|, 06, 2005

薔十月

Date: Sheet

1K_0402_5%@

12

PR144

162K_0402_1%

13

D

2

G

S

Compal Electronics, Inc.

401397

PACIN 37,38

B+

12

12

PR59

PR56

1 2

47K_0402_5%

13

1

ACIN 21,32,39

PR60
287K_0402_1%

287K_0402_1%

PACIN

2

PQ15
DTC115EUA_SC70

35 45

+3VALW

12

PC38

100P_0402_50V8J~N

A

of

5

D D

4

3

2

1

PH1 under CPU botten side :

CPU thermal protection at 86 +-3 degree C
Recovery at 51 +-3 degree C

C C

PC24

0.22U_0603_16V7K

B B

VL VL

12

PR115
0_0402_5%

PR116

200K_0402_1%

1 2

VL

PC81

0.1U_0402_16V7K~N@

1 2

PR110

100K_0402_1%

100K_0402_1%

PR113

CPU

12

12

PH2

100K_0603_1%_TH11-4H104FT

12

12

PR119
20K_0402_1%

PR114

499K_0402_1%

1 2

12

8

PU2A

3

P

+

2

-

G

LM393M_SO8

4

12

PC83
1000P_0402_50V7K~N

1 2

1

O

PC17

0.1U_0603_25V7K

VL

PR112
499K_0402_1%

1 2

MAINPWON6,35,39

13

D

2

G

PQ29

S

RHU002N06_SOT323

8

PU2B

5

P

+

7

O

6

-

G

LM393M_SO8

4

A A

Security Classification

Issued Date

PROPRIETARY NOTE

5

4

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/06/23 2006/06/23

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

SCHEMATIC, M/B LA-3051P

Size Document Number Rev

Custom

2

Date: Sheet

星|, 06, 2005

薔十月

401397

1

36 45

A

of

5

4

3

2

1

12

2

G

Ciss<3000pF.
Qg<>40nC.

PQ8

1
2
3

12

PR106

@

1N4148_SOD80

1 2

AO4407L_SO8~N

S
S
S

G

4

39K_0402_5%

PD9

8

D

7

D

6

D

5

D

12

PC86

0.01U_0402_25V7K~N

+3VALWP

PL7

FBMA-L18-453215-900LMA90T_1812

PR111

1K_0603_5%

1 2

PR105

6.49K_0402_1%

PR102

1K_0402_5%

BATT_TEMPB32

EC_SMB_DA26,10,23,32

EC_SMB_CK26,10,23,32

{Vbatt_max *[499K/(499K+649K)]+V_dischg}
* {1- exp^[-Δt/(R*C)]}

PR145
649K_0402_1%

1 2

PR153

47K_0402_5%

1 2

PD20

1N4148_SOD80

12

47P_0402_50V8J

12

PC104
47P_0402_50V8J

12

PR148
499K_0402_1%

1 2

PR62
649K_0402_1%

1 2

PR61
499K_0402_1%

1 2

2005/06/23 2006/06/23

> {Vbatt_max *[499K/(499K+649K)] +V_dischg}

-RTCVREF +V_hysteresis

Sense Delay Time by hysteresis and R/C
is about 24.8uS.

PC103

2nd B Battery Detector

High:8.117V
Low :7.36V

Main A Battery Detector

High:8.117V
Low :7.36V

PACIN 3 5, 38

TRICKE 32

Compal Secret Data

When in Trickle charge, battery
is selected by EC "A/B#USE" pin

Deciphered Date

12

1 2

1 2

100_0402_5%

EC_SMD2

EC_SMC2

2

PC27

12

1000P_0402_50V7K~N

PF4

2 1

12A_65V_451012MRL

BB/I

TSB

PR100

1 2

1 2

PR98
100_0402_5%

1
2
3
4
5
6
7

Battery Selector

PBJ2

1
2
3
4
5
6
7

SUYIN_250233MR007GX26ZU

1.BAT+

2.ID

3.B/I

4.TS

5.SMD

6.SMC

7.GND

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, M/B LA-3051P

401397

星|, 06, 2005

薔十月

1

37 45

A

of

Ciss<3000pF.

PC11

12

1000P_0402_50V7K~N

PBJ1

D D

SUYIN_250233MR007GX26ZU

1.BAT+

2.ID

3.B/I

4.TS

5.SMD

6.SMC

7.GND

1

1

2

2

3

3

4

4

5

5

6

6

7

7

100_0402_5%

PF1

2 1

12A_65V_451012MRL

AB/I
TSA

PR27

1 2

1 2

PL3

1 2

FBMA-L18-453215-900LMA90T_1812

PR28
1K_0603_5%

1 2

PR26
100_0402_5%

1 2

EC_SMB_DA1 32 ,33

EC_SMB_CK1 32 ,33

13

GA35

RB751V_SOD323

VL

1 2

PC107

100P_0402_50V8J~N

12

PC106

0.1U_0402_16V7K~N

C C

Turn-On Delay
<> (10K + 3K + 100K) * (100pF+50pF)
<> 4uS.
Turn-Off < 2uS.

PR156

ACON

5,38

B B

PQ36
DTC115EUA_SC70

FSTCHG32,38

1 2

27K_0402_1%

2

A/B#USE

High: Main Battery (A)
Low : Second Battery (B)

S0 S1 nC0 nC1 nC2 nC3 nOE nY
X X X X X X H Z

A A

L L L X X X L L
L L H X X X L H
H L X L X X L L
H L X H X X L H
L H X X L X L L
L H X X H X L H
H H X X X L L L
H H X X X H L H

5

VMBA VMBBBATT+

PR24

6.49K_0402_1%

PR25
1K_0402_5%

12

PC10

0.01U_0402_25V7K~N

12

BATT_TEMPA 32

GA

1 2

10K_0402_5%

PU7

74HC253

16

13

PR155

1 2

100K_0402_1%

PR154

1 2

100K_0402_1%

12

PR158

1Y72Y

VCC

1C061C151C241C332C0102C1112C2122C313S014S121EN12EN

PQ37
DTC115EUA_SC70

2

PD21

PR157

100K_0402_5%

1 2

2

A/B#USE32

8

D

7

D

6

D

5

D

+3VALWP

12

9

AO4407L_SO8~N

2

PC82

2200P_0402_50V7K~N

13

PQ1

1

S

2

S

3

S

G

4

1 2

PR97

22K_0402_5%

PQ25

PMBT2222_SOT23

PR103

2.2K_0402_5%

13

PQ28
DTC115EUA_SC70

8

GND

15

PQ35
DTC115EUA_SC70

1
2
3

12

PR96

@

1

C

2

B

E

3

PD14
1N4148_SOD80

1 2

12

VL VMBB

1 2

VL VMBA

1 2

4

PQ2

AO4413L_SO8~N

S
S
S

G

4

39K_0402_5%

GB35

RB751V_SOD323

PR149

100K_0402_5%

PR147

27K_0402_5%

PR65

100K_0402_5%

PR63

27K_0402_5%

8

D

7

D

6

D

5

D

GB

PD22

PU6A
LM393M_SO8

1

12

PR150

5.6M_0603_5%

7

12

PR64

5.6M_0603_5%

LM393M_SO8

Qg<>40nC.

AO4413L_SO8~N

8

D

7

D

6

D

5

D

12

12

1 2

PR159
10K_0402_5%

VL

12

PC39

8

3

P

+

O

2

-

G

4

12

PU6B

8

5

P

+

O

6

-

G

4

12

TRICKLE EC Override time:
<> 3* (R-C) cha rging time
<> 3* (1K * 1000pF)
<> 3uS.

PQ3

S
S
S

G

4

13

2

PC78

2200P_0402_50V7K~N

100K_0402_5%

0.01U_0402_25V7K~N

RTCVREF

10K_0402_5%

1 2

12

PQ34

RHU002N06_SOT323

P4P5

1
2
3

1 2

PR107

22K_0402_5%

1

C

2

B

E

3

PQ26

PMBT2222_SOT23

PR95

2.2K_0402_5%

PQ24
DTC115EUA_SC70

PR146

12

PR152

PR151
100K_0402_5%

12

PC105
100P_0402_50V8J~N

13

D

S

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

A

B

C

D

P2

PQ10

AO4407L_SO8~N

PACIN35,37

ACON35,37

8
7
6
5

12

PR99

4.7K_0603_5%

1 2

RB751V_SOD323

PACIN

ACON

D
D
D
D

PD1

PR104

1 2

3.3K_0402_5%

VIN

1 1

2 2

ACOFF#

1

S

2

S

3

S

G

4

1 2

PR108

22K_0402_5%

C

2

B

E

PQ27

PMBT2222_SOT23

1 2

PR34

2.2K_0402_5%

1 2

RB751V_SOD323

1 2

47K_0402_5%

12

1

3

1N4148_SOD80

PD12

PR101

PR109
39K_0402_5%@

1
2
3

PD2

1 2

PQ11

AO4413L_SO8~N

S
S
S

G

4

1 2

2

PC18
470P_0402_50V8J~N

8

D

7

D

6

D

5

D

12

PC33

0.1U_0402_16V7K~N

IREF32

PQ7

13

DTC115EUA_SC70

12

PR47

10K_0402_1%

1 2

143K_0402_1%

100K_0402_1%

12

12

PR50

PR46

IREF=1.0288*Icharge

Iadp=0~4A

P3 B+

ADP_I32

PR48

26.1K_0402_1%

PC97

0.1U_0402_16V7K~N

12

PR35

0.015_2512_1%

4
3

100K_0402_1%

PC100

1 2

1500P_0402_50V7K

PC99

1 2

1000P_0402_50V7K~N

PR131 10K_0402_5%

12

PC32

0.1U_0402_16V7K~N

PR130

1
2

12

PR134

1 2

10K_0402_5%

PR133

1 2

1K_0402_5%

12

1 2

FBM-L11-322513-151LMAT_1210

12

PC22

0.01U_0402_25V7K~N

PU11

1

-INC2

2

OUTC2

3

+INE2

4

-INE2

FB8

5

FB7

FB2

6

VREF

7

FB1

8

-INE1

9

+INE1

10

OUTC1

11

OUTD

12

-INC1

MB3887_SSOP24

PL6

4.7U_1206_25V6K~N

+INC2

GND

CS

VCC(o)

OUT

VH

VCC

RT

-INE3

FB3

CTL

+INC1

12

PC85

24

23

22

21

20

PC30

1 2

19

0.1U_0603_25V7K

18

1 2

17

PR125
68K_0402_5%

16

FB9

1 2

15

47K_0402_5%

14

13

12

PC84

4.7U_1206_25V6K~N

PC96

CS7

PR124

CTL pin = 0 >
>Charger Shutdown.

0.022U_0402_16V7K~N

1 2

PC95

1 2

0.1U_0603_25V7K

PC29

1 2

0.1U_0603_25V7K

PC94

1 2

1500P_0402_50V7K

FSTCHG 32,37

12

PC89

4.7U_1206_25V6K~N

12

PR123

0_0603_5%

12

HG7DH7

PD15

EC31QS04

12

PC92

PC93

0.1U_0603_25V7K
2200P_0402_50V7K~N

3

2

S

S

4

G

D6D5D7D

10UH_SIL1035-100PF_3.7A_20%

12

1

PQ30

S

AO4407L_SO8~N

8

LX7

12

PD16
EC31QS04

PR41

470K_0402_5%

1 2

PR44

1M_0402_1%

1 2

ACOFF##35

PL11

1 2

B++

BATT+

C

2

PQ5

DTC115EUA_SC70

PR32

220K_0402_5%

1 2

PQ4

2

B

E

PMBT3904_SOT23

3 1

PR29

0.02_2512_1%

1
2

4.7U_1206_25V6K~N

AO4407L_SO8~N

1

S

2

S

3

S

12

ACOFF#

PR30
47K_0402_5%

4
3

PC12

PQ14

G

4

13

PR31

1 2

13

DTC115EUA_SC70

12

PC80

4.7U_1206_25V6K~N

8

D

7

D

6

D

5

D

12

PR33

4.7K_0402_5%

VIN

PD10

100K_0402_5%

2 1

PD11

1 2

2

PQ6

12

12

ACOFF 32

PD13

RLZ16B_LL34

1 2

1SS355_SOD323

1SS355_SOD323

PC79

4.7U_1206_25V6K~N

BATT+

IREF=0.6V~3.21V

Ciss <>50pF.
Turn-On <> 130nS.
(PR3 (10K) + PR45 (3K) to 100pF)

3 3

PR43

12

150K_0603_0.1%

4.2V

PR42

12

300K_0603_0.1%

CC=0.6~3.3A
CV=12.6V(6 CELLS LI-ION)

Vadp=15V

I limit: 4.61A

D.A.C.A. (C.P.) on 75W adaptor: Take PR47= 10K

4.65A*0.015*20 = 5*PR47/(PR47+PR48)<> PR48<>26.1K

Fast charge current <> 3.3A,

3.3A*0.02*20/[(3.21V- 3.3A*0.02*20)/PR46] <> PR50

4 4

PR46 <> 143K

PU4B

LM358NOPB_SO8

7

Trickle charge current <> 0.6A,

0.6A*0.02*20/[(0.6V- 0.6A*0.02*20)/PR46] <> PR50
PR46 <> 143K

A

B

OVP voltage : LI

3S2P : 13.5V--> BATT_OVP= 1.5V

(BAT_OVP=0.1112 *BATT+)

VIN

12

3
2

-

Deciphered Date

0.01U_0402_25V7K~N

105K_0402_1%

8

PU4A

BATT_OVP32

5

+

0

6

-

12

PR132

2.2K_0402_5%

LM358NOPB_SO8

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SE CRET INFOR MATI ON. THIS SHEET MAY NOT BE TRANSF ERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2005/06/23 2006/06/23

P

+

1

0

G

4

Compal Secret Data

PC34

C

PR135

BATT+

12

12

12

PR136
340K_0402_1%

PR137
499K_0402_1%

12

PC98

0.01U_0402_25V7K~N

PC54

PR73

1 2

B+

100_0805_5%

+5VALW

PR69

470K_0402_5%

1 2

12

PR75

1 2

12

0.1U_0603_25V7K

PD8

220K_0402_5%

Title

Size Document Number Rev

Date: Sheet

1SS355_SOD323

2

G

PR74

1 2

220K_0402_5%

Compal Electronics, Inc.

SCHEMATIC, M/B LA-3051P

B

星期五

, 07, 2005

十月

401397

PQ16

TP0610K-T1-E3_SOT23

13

2

13

D

PQ17
2N7002-7-F_SOT23-3

S

D

PC47

1 2

38 45

12

0.1U_0805_25V7M

of

B+_BIAS

PD6

RLZ18B_LL34

A

5

4

3

2

1

+3.3VALWP/+5VALWP

4.7U_1206_25V6K~N

PL14

12

B+++

PC129

2200P_0402_50V7K~N

12

MAINPWON6,35,36

12

VS

12

D8D7D6D

S1S2S3G

D8D7D6D

S1S2S3G

PD26

RLZ5.1B_LL34

PR192

1 2

47K_0402_5%

PR196

5

PQ44

SI4800BDY-T1-E3_SO8

4

1 2

5

PQ46
SI4810BDY-T1-E3_SO8

4

DL_5V

12

100K_0402_5%

PR185

0_0402_5%

PR176

0_0603_5%

12

PC145

1U_1206_25V7K @

12

0.047U_0603_16V7K

1 2

DH_5V

PC141

0.1U_0603_25V7K

ACIN21,32,35

VL

12

PR190

12

PC142

PR177

0_0805_5%@

12

1 2

10K_0402_5%

806K_0603_1%

PQ47

RHU002N06_SOT323

DAP202U_SOT323

PR181

0_0805_5%

VL

12

PC134

4.7U_0805_6.3V6K

PR184 0_0603_5%

PR78

2VREF_8734

@

13

D

2

G

S

LX_5V

+LDO5

12

BST_5V

12

FB5

LDO3

PQ48

PD25

14
16
15

19
21

9
1

6
4
3

12

8

12

PC143

0.22U_0603_16V7K

PR183
100K_0402_5%

@

1 2

@

13

D

S

G

PU16

2

2

1

PC135

4.7U_1206_25V6K~N

BST5
DH5
LX5

DL5
OUT5
FB5
N.C.

SHDN#
ON5
ON3

SKIP#
REF

ACIN

3

PR180

12

18

B+++

12

0_1206_5%

20

V+

LD05

GND

23

@

PQ49

0.1U_0603_25V7K

PC137

12

13

TON

LDO3

25

12

PC136

13

D

S

VL

PR186

1 2

47_0402_5%

PC138

1 2

17

5

ILIM3

VCC

11

ILIM5

28

BST3

26

DH3

24

DL3

27

LX3

22

OUT3

7

FB3

2

PGOOD

PRO#

10

MAX8734AEEI+_QSOP28

LDO3P

1 2

0_0805_5%

4.7U_0805_6.3V6K

2

G

12

PC144

0.1U_0402_16V7K~N

2VREF_8734

1U_0603_16V6K

ILIM3

ILIM5

FB3

PR76

0_0402_5%

1 2

PR179

EC_ON 32,33

1 2

1 2

PR77

PR79

BST_3V
DH_3V

POK

PR188

1 2

330K_0402_1%

PR193

1 2

499K_0402_1%

PR182

0_0603_5%

+LDO3

PR178

1 2

0_0805_5%@

200K_0402_1%

499K_0402_1%

0.1U_0603_25V7K

12

LX_3V

PC140

B+++

LX_3V

5

4

5

4

PQ43

D8D7D6D

S1S2S3G

SI4800BDY-T1-E3_SO8

D8D7D6D

PQ45

S1S2S3G

SI4810BDY-T1-E3_SO8

4.7U_SIL104R-4R7PF_5.7A_20%

12

PL15

12

12

12

PC124

4.7U_1206_25V6K~N

PR175

0_0603_5%

PC151

2200P_0402_50V7K~N

1 2

DL_3V

PC125

4.7U_1206_25V6K~N

12

+3VALWP

1

+

2

PC133

150U_V_6.3VM_R18

1 2

1 2

PR187

3.57K_0402_1%@

PR191

0_0402_5%

PL13

FBM-L11-322513-151LMAT_1210

D D

B+

C C

B B

PF6

2 1

12

10A_65VDC_451010

4.7U_SIL104R-4R7PF_5.7A_20%

+5VALWP

1

+

PC131

2

150U_V_6.3VM_R18

12

PC126

PC127

4.7U_1206_25V6K~N

PR189

10.2K_0402_1%@

1 2

PR194

0_0402_5%

1 2

RHU002N06_SOT323

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

RHU002N06_SOT323

2005/06/23 2006/06/23

3

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, M/B LA-3051P

401397

星期五

, 07, 2005

十月

1

39 45

A

of

A

1 1

B

C

D

B++++

PC42

12

PR169

PL8

12

PC43

4.7U_1206_25V6K~N

PD7
SKS10-04AT-G_TSMA@

1 2

PR168
10K_0402_1%

1 2

FBM-L11-322513-151LMAT_1210

12

12

PC113

2200P_0402_50V7K~N

@

2 2

+1.5VSP

+1.5VS

PC117

4.7U_1206_25V6K~N

2.5uH_SIL104R-2R5PF_7.5A_30%

1 2

4.7U_1206_25V6K~N

PL16

1 2

0_0402_5%

PR160
10_0402_5%

@

1 2

PR167

5.1K_0402_1%

1 2

12

PR161
10K_0402_1%

PR172

1

PC132

220U_D2_4VM_R15

+

2

3 3

PD24

12

PC139

SKS10-04AT-G_TSMA@

2 1

10U_0805_6.3V6M

@

12

PC120

12

PC115

SUSP#32,33,34,41

0.1U_0603_25V7K

5

D8D7D6D

S1S2S3G

4

5

PQ41

D8D7D6D

SI4810BDY-T1-E3_SO8

S1S2S3G

4

PQ42
SI4800BDY-T1-E3_SO8

PC128

0.1U_0603_25V7K

12

DL3

PR170

1 2

0_0402_5%

12

PR174

0_0603_5%

DH3

LX3

FB3

PC52

0.1U_0603_25V7K

@

1

PD23
RB717F_SOT323

2

3

0.1U_0603_25V7K

1 2

BST3

PC50

25
26
27

24
28

1
2

11

1U_0603_16V6K

12

PU15

BST1
DH1
LX1

DL1
CS1

OUT1
FB1

ON1

OVP

8

0.22U_0603_16V7K

MAX8743_VCC

PC123

12

4

V+

GND

6

23

PC51

22

SKIP

PR71

1 2

20_0603_5%

9

VDD

UVP

VCC

BST2

DH2

LX2
DL2
CS2

OUT2

FB2

ON2

PGOOD

TON

ILIM2
ILIM1

REF

MAX8743EEI+T_QSOP28~N

10

PR164

49.9K_0402_1%

12

+5VALW

21

BST4

19
18
17
20
16

15
14
12

7
5

13
3

PR165

12

7.5K_0402_1%

12

PR163

100K_0402_1%

12

PC46

4.7U_0805_6.3V6K

PR173
0_0603_5%

1 2

12

12

12

PR166
100K_0402_1%

PC122

0.1U_0603_25V7K

12

DH4

DL4

12

PR162
0_0402_5%

PC114

0.1U_0603_25V7K

@

PQ40

RSS090N03_SO8

5

4

LX4

578

3 6

241

FB4

SYSON 32 ,34

12

PC44

0.1U_0603_25V7K

D8D7D6D

S1S2S3G

1.8UH_SIL1035-1R8PF_8.7A_30%

PQ39
AO4704L_SO8~N

12

PC45

@

12

4.7U_1206_25V6K~N

2200P_0402_50V7K~N

PL12

8.06K_0402_1%

PF5

12

2 1

7A_24VDC_429007.WRML

PC130
10U_0805_6.3V6M@

12

2 1

PC121

220U_D2_4VM_R15

B+

12

PC48

0.01U_0402_25V7K~N

+1.8VP

PC53

220U_D2_4VM_R15@

1

+

+

2

1

2

4 4

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2005/06/23 2006/06/23

Compal Secret Data

Deciphered Date

C

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, M/B LA-3051P

401397

星期

, 07, 2005

五十月

D

40 45

of

A

5

4

3

2

1

PF3

2 1

PR199

0_0402_5%

B+

7A_24VDC_429007.WRML

12

12

PR200

12

0_0402_5%

PR201

100K_0402_5%

PC148

4.7U_0805_6.3V6K

12

PC150

0.01U_0402_25V7K~N

1 2

D D

C C

B B

+3VALW

SUSP#

A A

PL5

FBMA-L18-453215-900LMA90T_1812

1 2

12

SUSP#32,33,34,40

PU18

1

IN

4

BYP

3

SHDN

G914E_SOT23-5

OUT

GND

5

2

PC21

10U_1206_25V6M~N

12

PC90

0.1U_0402_16V7K~N

12

0.01U_0603_50V7K@

6269_VCC

12

PC87

2.2U_0603_6.3V6K

+2.5VSP

12

PC149

4.7U_0805_6.3V6K

+5VS

PC20

0_0603_5%

10U_1206_25V6M~N

1 2

PR36

PC23

1 2

PC26

12

PR120

0_0402_5%

12

PGD_IN

22P_0402_50V8J

PU3

1

VIN

2

VCC

3

FCCM

4

EN

12

12

17

GND

COMP5FB6FSET

PR40

49.9K_0402_1%

PC28
6800P_0402_25V7K

PR202
10K_0402_5%

1 2

16

PGOOD

57.6K_0402_1%

15

PHASE

PR121

12

PHASE_VCCPP

14

UG

7

12

PR122
3K_0402_1%

SUSP24,34

PR37

1 2

0_0603_5%

BOOT_VCCPP

13

BOOT

12

PVCC

11

LG

10

PGND

9

ISEN

VO

8

12

PC91

0.01U_0402_25V7K~N

UG_VCCPP

1 2

PC19 0.1U_0603_25V7K

12

PR118

4.7_0603_5%

@

PR117

1 2

4.7_0603_5%

1 2

2.2U_0603_6.3V6K

LG_VCCPP

ISEN_VCCPP

1 2

11.5K_0402_1%

ISL6269CRZ-T_QFN16

PR39

1 2

2.26K_0402_1%

10U_1206_25V6M~N

PR68

0_0402_5%

1 2

PC41

0.1U_0402_16V7K~N @

+5VS

6269_VCC

PC25

PR38

PC110

2N7002-7-F_SOT23-3

12

+1.8V

PQ38

5

PQ9

D8D7D6D

S1S2S3G

SI4800BDY-T1-E3_SO8

4

PR203
10K_0402_5%

@

1 2

5

4

PR204

10K_0402_5%@

1 2

1

PJP2

1

JUMP_43X118@

2

2

12

13

D

2

G

S

PR67

1K_0402_1%

PR66

12

12

1K_0402_1%

12

PC40

0.1U_0402_16V7K~N

PL10
1UH_SIL1035-1R0PF_9A_20%

1 2

PQ12

D8D7D6D

SI4810BDY-T1-E3_SO8

S1S2S3G

PU8

VIN1VCNTL

2

GND

3

VREF

4

VOUT

APL5331KAC-TRL_SO8~N

+0.9VSP

12

PC108
10U_1206_25V6M~N

+VCCPP

1

+

6
5

NC

7

NC

8

NC

9

TP

PC88

220U_D2_4VM_R15

2

12

+3VALWP

PC109
1U_0603_6.3V6M

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/06/23 2006/06/23

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, M/B LA-3051P

401397

星? 07, 2005

薑十月

1

41 45

A

of

5

D D

DPRSLPVR21

H_DPRSTP#6,20

CLK_EN#17

+3VS

+3VS

PR5

499_0402_1%

VGATE1 9 ,21,32

H_PSI#7

C C

PR1 4.22K_0402_1%@

B B

A A

PGD_IN

VR_TT#

1 2

VCCSENSE7

+CPU_CORE

PR4 147K_0402_1%

1 2

470K_0603_1%_TH11-4H104FT@

1 2

PC20.015U_0402_16V7K@

PR84 11.5K_0402_1%

PC61

1000P_0402_50V7K~N

PR81 82.5K_0402_1%

1 2

PC3 390P_0402_50V7K

3.4K_0402_1%

1 2

PR8 1.82K_0402_1%

1 2

PR93 20_0402_5%

VSSSENSE7

5

1 2

PR70 0_0402_5%

1 2

PH3

PC590.015U_0603_25V7K

1 2

1 2
1 2

PR3 3.57K_0402_1%

1 2

1 2

PC55 5600P_0402_25V7K

PC4 0.022U_0402_16V7K

1 2

PR80

PC1 470P_0402_50V7K

1 2

1 2

PR7 0_0402_5%

20_0402_5%

VCC_PRM

1 2

12

1 2

PR94

PR2

12

12

PR15 1K_0402_1%

PR12 0_0402_5%

1 2

PR10 0_0402_5%

1 2

PR9 0_0402_5%

1 2

PR6 0_0402_5%

1 2

12

12

PC56

1U_0603_16V6K

1
2
3
4
5
6
7
8

9
10
11
12

PGOOD
PSI#
PGD_IN
RBIAS
VR_TT#
NTC
SOFT
OCSET
VW
COMP
FB
FB2

1.91K_0402_1%

12

PR83
0_0402_5%@

PC58 0.018U_0603_50V7K

1 2

PC57

0.018U_0603_50V7K

@

1 2

PR82 0_0402_5%

PC5 180P_0402_50V8J

1 2

1 2

0.22U_0603_16V7K

PC62

48

1 2

PR11 5.62K_0402_1%

4

7

7

7

32

CPU_VID47CPU_VID3

CPU_VID5

CPU_VID6

VR_ON

CPU_VID27CPU_VID17CPU_VID0

12

PR14

0_0402_5%

45

46

47

44

43

3V3

CLK_EN#

VR_ON

DPRSTP#

DPRSLPVR

UGATE1

PHASE1

PGND1

LGATE1

LGATE2

ISL6262CRZ-T_QFN48

PGND2

PHASE2

UGATE2

VDIFF13VSEN14RTN15DROOP16DFB17VO18VSUM19VIN20GND21VDD22ISEN223ISEN1

1 2

12

PC64
1U_0603_6.3V6M

PR86

1 2

12

PC65

10_0603_5%

0.01U_0603_50V7K

12

PC60

0.018U_0603_50V7K

12

4

VSUM

PC6 0.033U_0603_25V7K

1 2

PC63 0.33U_0603_10V7K

12

12

PR18

12

PR16

2.61K_0402_1%
PH1
10KB_0603_ERTJ1VR103J

11K_0402_1%

1 2

3

+5VS

7

12

12

PC68

PC67

1U_0603_6.3V6M

PC8

0.22U_0603_10V7K

1 2

IRF8113PBF_SO8

VID037VID138VID239VID340VID441VID542VID6

BOOT1

PVCC

36
35
34
33
32
31
30

BOOT_CPU1

UGATE_CPU1
PHASE_CPU1

PC66

0.01U_0402_25V7K~N

PR20

1 2

0_0603_5%

LGATE_CPU1

LGATE_CPU2

29

BOOT_CPU2

0_0603_5%

+CPU_B+

PHASE_CPU2

PR19

1 2

+5VS

UGATE_CPU2

PC7

1 2

0.22U_0603_10V7K

IRF8113PBF_SO8

28
27
26

BOOT2

25

NC

PU1

24

ISEN1
ISEN2

PR13 1_0603_5%

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2005/06/23 2006/06/23

3

PR85
1_0603_5%

1 2

12

12

PC69

0.01U_0402_25V7K~N

578

PQ20

3 6

241

578

PQ22

Compal Secret Data

1U_0603_6.3V6M

3 5
578

3 6

241

Deciphered Date

PQ18
SI7840DP_SO8

241

PQ21

3 6

241

IRF8113PBF_SO8

PQ19
SI7840DP_SO8

3 5

241

578

PQ23
IRF8113PBF_SO8

3 6

241

PC74

10U_1206_25V6M~N

12

PR91

12

PC76

12

@

12

@

2

12

4.7_1206_5%

@

@

PR92

4.7_1206_5%

PC77
680P_0603_50V8J

2

PC71

680P_0603_50V8J

+CPU_B+

12

10U_1206_25V6M~N

PC73

10U_1206_25V6M~N

12

PC72

10U_1206_25V6M~N

P_0.36H_ETQP4LR36WFC_24A_20%

12

PR87

12

12

PR90

10K_0402_1%

3.65K_1206_1%

VSUM

ISEN1

0.22U_0402_10V4Z

12

PC75

10U_1206_25V6M~N

P_0.36H_ETQP4LR36WFC_24A_20%

12

PR22

PR17

10K_0402_1%

3.65K_1206_1%

VSUM

0.22U_0402_10V4Z

Title

Size Document Number Rev

Custom

Date: Sheet

1

PL9

FBMA-L18-453215-900LMA90T_1812

1 2

1

+

2

PR88 0_0402_5%@

1 2

1 2

12

PR21 0_0402_5%@

1 2

1 2

ISEN2

PL1

PC70

PC9

PC152

@

12

220U_25V_M

PC153

PL2

12

10U_1206_25V6M~N

12

PR89

1_0402_5%

VCC_PRM

+CPU_B+

12

12

PR23
1_0402_5%

VCC_PRM

PF7

8A_1255VDC_451008

2 1

Compal Electronics, Inc.

SCHEMATIC, M/B LA-3051P

401397

星期五

, 07, 2005

十月

1

+CPU_CORE

42 45

of

B+

A

5

4

3

2

1

TIP

PCI_AD31
PCI_AD29

PCI_AD27
PCI_AD25

R212

PCI_AD23
PCI_AD21

PCI_AD19
PCI_AD17

PCI_AD14
PCI_AD12

PCI_AD10
PCI_AD8

PCI_AD7
PCI_AD5
PCI_AD3
PCI_AD1

LAN RESERVED

WLAN_LINK
WLAN_SKILL#

W=40mils

0_0402_5%@

W=30mils

D16 CH751H-40_SC76

D D

C C

WL_OFF#24,27,32,33

+3VS

CLK_PCI_MINI

CLK_PCI_MINI17

PCI_CBE#219,28,32
PCI_IRDY#19,28

PCI_SERR#19,28
PCI_PERR#19,28

PCI_CBE#119,28,32

WLAN_LINK33

21

PCI_PIRQG#19,28

CLK_PCI_MINI

PCI_REQ3#19

WL_ACTIVE24,27
PCI_CBE#319,28,32

PCI_CLKRUN#21,28,32

12

R205
10_0402_5%

+5VS

1

C221
22P_0402_25V8K

2

B B

+5VS +3V

JP12

1

1

3

3

5

5

7

7

9

9

11

11

13

13

15

15

17

17

19

19

21

21

23

23

25

25

27

27

29

29

31

31

33

33

35

35

37

37

39

39

41

41

43

43

45

45

47

47

49

49

51

51

53

53

55

55

57

57

59

59

61

61

63

63

65

65

67

67

69

69

71

71

73

73

75

75

77

77

79

79

81

81

83

83

85

85

87

87

89

89

91

91

93

93

95

95

97

97

99

99

101

101

103

103

105

105

107

107

109

109

111

111

113

113

115

115

117

117

119

119

121

121

123

123

125

GND

TYCO_1734065-3~N

100
102
104
106
108
110
112
114
116
118
120
122
124

GND

2

2

4

4

6

6

8

8

10

10

12

12

14

14

16

16

18

18

20

20

22

22

24

24

26

26

28

28

30

30

32

32

34

34

36

36

38

38

40

40

42

42

44

44

46

46

48

48

50

50

52

52

54

54

56

56

58

58

60

60

62

62

64

64

66

66

68

68

70

70

72

72

74

74

76

76

78

78

80

80

82

82

84

84

86

86

88

88

90

90

92

92

94

94

96

96

98

98

100
102
104
106
108
110
112
114
116
118
120
122
124

126

RING

LAN RESERVED

WLAN_ACT_CALE

W=30mils

0_0402_5% @

PCI_AD30
PCI_AD28

PCI_AD26
PCI_AD24

MINI_IDSEL

PCI_AD22
PCI_AD20

PCI_AD18
PCI_AD16

PCI_AD15
PCI_AD13
PCI_AD11

PCI_AD9

PCI_AD6
PCI_AD4
PCI_AD2
PCI_AD0

W=20milsW=30mils

2

1

+3V

R194

1 2

R196 100_0402_1%

C208

0.1U_0402_16V4Z

WLAN_ACT_CALE 33

+5VS

PCI_PIRQH# 19

PCI_RST# 19,28,32
PCI_GNT3# 19
WLAN_PME# 32

BT_CHCLK 24,27

PCI_AD18

PCI_PAR 19,28

PCI_FRAME# 19,28,32
PCI_TRD Y# 19,28,32
PCI_STOP# 19 ,28

PCI_DEVSEL# 19,28

PCI_CBE#0 19,28,32

W=40mils

+3VS

IDSEL : PCI_AD18

+3VS

R187 10K_0402_5%@

PCI_AD[0..31]

1 2

R209 10K_0402_5%@

1 2

R208 10K_0402_5%

1 2

WLAN_SKILL#

WLAN_LINK
WLAN_ACT_CALE

PCI_AD[0..31] 19,28,32

0.047U_0402_16V4Z

C206

2

C207

1

2

1

0.047U_0402_16V4Z

A A

0.047U_0402_16V4Z

2

C209

1

0.047U_0402_16V4Z

2

C205

1

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

0.047U_0402_16V4Z

2

C219

1

0.047U_0402_16V4Z

Issued Date

4

1

C217

2

0.047U_0402_16V4Z

1

C222

2

0.047U_0402_16V4Z

+3VS

1

C215

2

0.1U_0402_16V4Z

2

C220

1

0.1U_0402_16V4Z

Compal Secret Data

2005/09/10 2006/06/23

Deciphered Date

3

0.1U_0402_16V4Z

2

C204

1

+5VS

1

C218

2

Title

Size Document Number R ev

Date : Sheet

2

Compal Electronics, Inc.

SCHEMATIC, M/B LA-3051P

星期五 十月

401397

07, 2005

43 45,

1

A

of

5

4

3

2

1

Version Change List ( P. I. R. List )

Page 1/1

Request

Item Issue DescriptionDate

1

D D

2

3

4 21 ICH7M(3/4)USB,GPIO,PCIE Add R527~R529 PULL-HIGH

5 ENE-KB910L/TPM32 Add R530 connect to U13 pin22

6 25 BCM5751-GLAN Connect to PLT_RST of ICH7

7 25 BCM5751-GLAN Aug. 8 NEC Change the pull high resistance Change R7 & R8 from 1K to 4.7K

8 17 ClockGen Aug. 11

9 33 BIOS/EE-Prom/TP/KB/SW Sep. 8 CO MPAL Fix the GOLAN LED incorrect light Del U33, Add Q45,R532, change R523.1 to WL_OFF# 0.2

10 30 HD Audio Codec_ALC262 Sep. 10 Using ALC262 GPIO2 (pin2) control amplifier status Del R199, GPIO2 Add R533,R379 and connect to EAPD 0.2NEC

11 24 USB/BlueTooth/FP Sep. 10 Change D3,D14,D21,D22 to NUP4301MR6T1Change USB diode to low capacitor diode COMPAL 0.2

C C

16 33 BIOS/EE-Prom/TP/KB/SW Sep. 14 NEC Modify the define LED to GOLAN Take off R520,R521, mount R523,R524

TV-OUT/LVDS/CRT18

BIOS/EE-Prom/TP/KB/SW33

9 Calistoga(1/6)-GTL/DMI/DDR INTEL

1812 Add U33(And gate)Change DISPOFF# control from EC to VBIOSSep. 10TV-OUT/LVDS/CRT 0.2COMPAL

613 Yonah(1/2)-GTL/ITP-XDP Sep. 10 For EC SM bus blance Change Thermal Sensor for SM bus2 to SM bus1EC 0.2

Aug. 1st NE C 0.1

Aug. 2nd

Aug. 8

Aug. 8

Aug. 8

Aug. 8

Owner

For EMI Add D1, D2 for CRTHSYNC# & CRTVHSYNC#

NEC For GALAN & CALEXICO LAN LED control Add U33, U34, R519~524 for the LAN LED control circuit 0 .1

To enable faster C4 exit

INTEL

INTEL

INTEL

COMPAL ICS_CLK GEN BUG, need FSC pull down R105 change to 0 ohm and remove R99

Define GPIO STATE

No connect clk of debug tool

No connect reset signal of LAN chip

For S4 needed Add U36 with S5 0.214 Se p. 10 E C21 ICH7M(3/4)USB,GPIO,PCIE

security issue Change :USB port0: Fingerprint & USB port6: Bluetooth 0.215 Se p. 14 N EC24 USB/BlueTooth/FP

Add R526 to connect PM_EXTTS1# of the GMCH and DPRSLPVR of the ICH

Solution Description Rev.Page# Title

0.1

0.1

0.1

0.1

0.1

0.1

B B

A A

Title

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

Size Document Number Re v

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, M/B LA-3051P

401397

, 07, 2005

星期五 十月

1

A

of

4544

5

4

3

2

1

Version Change List ( P. I. R. List )

Page 1/1

Request

Item Issue DescriptionDate

1 PWR-CPU_CORE42 For protection Add Fuse at CPU B+

D D

2 35 PWR-DCIN/Precharge A ug. 29 C ompal For VIN dector design issue at LC2 Change PC121 to 2200P and PR141 to 56K. 0.2

2 38 PWR-CHARGER Sep. 16 Compal Change adapter from 60W to 75W and modify the CP to 4.61A Change PR48 to 26.1K

C C

Aug. 2 NEC 0.1

Owner

Solution Description Rev.Page# Title

B B

A A

Title

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

Size Document Number Re v

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, M/B LA-3051P

401397

, 07, 2005

星期五 十月

1

A

of

4545