COMPAL LA-3041 Schematics

5

4

COMPAL CONFIDENTIAL

3

2

1

MODEL NAME :

D D

COMPAL P/N :

HDL75/76

PCB NO :
Revision :

0.1

HDL75/76 Schematics Document

C C

uFCBGA/uFCPGA Mobile Dothan
Intel Alviso + ICH6M

2005-07-14

REV : 1B

B B

A A

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

Cover Sheet

HDL75 LA3041

160Thursday, July 28, 2005

1

0.1

5

Compal confidential

4

3

2

1

Model : HDL75

FAN

+5VS

D D

TV OUT

CRT CONN

LVDS CONN

page 25

page 25

page 24

CRT Signal

Internal LVDS

Frame Buffer

C C

64/128

page 22,23

IDSEL:AD18
(PIRQG#,PIRQH#,GNT#1,REQ#1)

IDSEL:AD19
(PIRQH#,PIRQG#,GNT#4,REQ#4)

Minipci CONN X2

WIRELESS
TV Turner

page 37,38

IDSEL:AD16
(PIRQE#,GNT#0,REQ#0)

VT6301S

1394 Controller

+3VS

page 34

1394

B B

CONN

page 34

page 8

CardBus Controller

+S1_VCC
+3VS

Card
Reader

+VCC_5IN1 +S1_VCC

page 33

Thermal(CPU)

+3VS

+1.5VS
+1.8VS
+VGA_CORE
+3VS
+2.5VS
+1.2VS

G781

ATI M24P

page 18,19,20,21

Thermal(VGA)

+3VS

IDSEL:AD20
(PIRQA,B#,GNT#2,REQ#2),SIRQ

ENE CB712

G781-1

page 32

page 26

PCMCIA
Slot

+S1_VPP

page 33

page 8

PCI BUS

IDSEL:AD17
(PIRQF#,GNT#3,REQ#3)

RTL8110SBL
/8100CL

+3VALW

RJ45

page 36

PCI-E 16X

+3VALW 33MHz

page 35

X BUS

+VCCP (1.05V)
+CPU_CORE

H_A#(3..31) H_D#(0..63)

+1.5VS
+2.5V
+VCCP
+3VS
+2.5VS

+3VS
+3V
+1.5VS
+1.5V
+2.5VS

Port DEBUG

+5VS
+3VS

+1.5VS/+VCCP

page 53

+1.8VS/
+VGA_CORE

page 54

DC IN

RTC BATT

page 50

page 48

SST39VF040

page 42

Power On/Off

CPU_CORE

page 55

A A

CHARGER

page 49

5

2.5V/+1.2VS/
+1.25VS

page 52

3V/5V/12V

page 51

SW & LED

page 43

DC/DC Interface

page 47

4

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Pentium-M

Dothan

uFCPGA CPU

478pin

System Bus

+VCCP 400/533 MHz

INTEL

Alviso

1257BGA

DMI

+1.5VS
100MHz

INTEL
ICH6-M
609 BGA

page 43

KB910

+5VS
+3VALW

Touch Pad &
LID SW

+5VS

3

page 5,6,7

page 9,10,11,12,13

page 27,28,29,30

LPC BUS

+3VALW
33MHz

page 41

Int.KBD

page 43

page 43

Memory BUS
(DDRII)

48MHz

24.576MHz

ATA100

2

1.8V 533 MHz

USB[0,2,4,6]

AC-LINK

Parallel ATA

+5VS

page 31

IDE

CD-ROM

+5VCD

page 31

AMP & INT.
Speaker

+5VAMP +5VAMP

Title

Size Document Number Rev

Date: Sheet of

Clock Generator

ICS954226

+3VS

DDRII-DIMM X2

BANK 0, 1, 2, 3

+0.9VS
+1.8V

page 14,15

USB Ports X4

+5VALW

AC97 Codec

ALC250

+5VAMP
+3VS

page 44

HeadPhone &
MIC CONN

page 45

Compal Electronics, Inc.

Cover Sheet

HDL75 LA3041

1

page 45

260Thursday, July 28, 2005

+5VS
+3VS
+3V

page 17

page 40

MDC

page 39

Cable

RJ11

page 36

0.1

5

D D

4

3

2

1

AC
Adapter
in

C C

BATT+

51_ON#

VMB

P48

ADPPWR

VIN

SWITCH

MB3887
Charger

TPO610T
SWITCH

VS

P49

P50

P50

CHGRTC

G920
RTC BATT
Charger

B B

P50

CHG/DIS

BATT+

VS

LM393
BATT OVP

P49

BATT_OVP

MAINPWON

B+ B+

VS

RUN

MAX1902
DC/DC
(3V/5V/12V)

SHDN#

Battery A
8 Cell

LM358
Thermal
Protector

P50

P52

2.5VREF

VS_ON1/VS_ON2

VL

+5VALWP

+3VALWP

+12VALWP

B+

MAX8743
DC/DC
(1.5V/VCCP)

ON1/ON2

FAN5234
DC/DC
(2.5V)

P53

Vcc

+1.5VP 5A

P54

+2.5V 7.106A

SUSP

2.5VP

3VALW

+VCCP 6.420A

+1.25V 1A

ALP5331
DC/DC
(1.25V)

P53

EN

+5VS

VCC SHDN#

MAX1532
DC/DC
(CPU_CORE)

P55

SUSP

B+

Battery
Connector
A

SWITCH

P48

BATT

P48

VR_ON

CPU_CORE
(+1.308V 25A)

A A

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

Power Rail

HDL75 LA3041

360Thursday, July 28, 2005

1

0.1

5

4

3

2

1

Board ID Table for AD channel

Vcc 3.3V +/- 5%

Voltage Rails

Power Plane Description

D D

C C

VIN

B+

+CPU_CORE

+PCIE_1.2VS +PCIE_1.2VS power rail for VGA PCIExpress

+1.5VS

+1.8VS

+3VALW

+3V

+5VALW

+5VS

+12VALW

+RTCVCC

Adapter power supply (19V)

AC or battery power rail for power circuit.

Core voltage for CPU

0.9VS for DDR2 Termination+0.9VS

1.8V switched power rail

2.5VS switched power rail+2.5VS

3.3V always on power rail

3.3V power rail

3.3V switched power rail

5V always on power rail

5V switched power rail

12V always on power rail

RTC power

S0-S1 S3 S5

N/A N/A N/A

ON OFF

ONVGA Core Power+VGA_CORE

OFF

ON

OFF

ON

ON

ON

ON

OFF

ON+3VS

ON

ON

OFF

ON

ON

ON

ON

ON

N/AN/AN/A

OFF

OFFOFFON

OFFOFFON

OFFOFF

OFFOFFONMCH & ICH Core Power

OFF

OFF

ON*ON

OFF

OFF

ON*ON

OFF

ON*

Board ID

0
1
2
3
4
5
6
7 NC

Board ID

*

100K +/- 5%Ra

8.2K +/- 5%
18K +/- 5%
33K +/- 5%
56K +/- 5%
100K +/- 5%
200K +/- 5%

0
1
2
3
4
5
6
7

Rb V min

0

AD_BID

0 V

0.216 V 0.250 V 0.289 V

0.436 V

0.712 V

1.036 V

1.453 V 1.650 V 1.759 V

1.935 V

2.500 V

PCB Revision

0.1

0.2

0.3

0.4

0.5

0.6

1.0

1.B

Vtyp

AD_BID

V

AD_BID

0 V 0 V

0.503 V

0.819 V

0.538 V

0.875 V

1.185 V 1.264 V

2.200 V

3.300 V

2.341 V

3.300 V

max

SKU ID Table

Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.

External PCI Devices

Device IDSEL# REQ#/GNT# Interrupts

VGA

B B

1394 PIRQE

LAN
CardBus
Mini-PCI
Mini-PCI II for TV Turnner

AD16
AD17
AD20
AD18
AD19

EC SM Bus1 address

Device

Smart Battery

EEPROM(24C16/02)

G781-1

Address

0001 011X b

1010 000X b

1001 101X b

0

3PIRQF

2
1
4

EC SM Bus2 address

ICH6 SM Bus address

Device

Clock Generator

A A

( ICS954206)

DDRII DIMM0

DDRII DIMM1

Address

1101 001Xb

1010 000Xb

1010 001Xb

Device

G781

PIRQA

PIRQA,B
PIRQG/PIRQH
PIRQH/PIRQG

Address

1001 100X b

NOTE1:
SWDJ@ : SWDJ

NOSWDJ@ : W/O SWDJ
@XX : Depop component
1@XX : Pop for Integrated Graphic
2@XX : Pop for External Graphic

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

Vcc 3.3V +/- 5%

100K +/- 5%Ra

Board ID

0
1
2
3
4
5
6

Rb V min

0

8.2K +/- 5%
18K +/- 5%
33K +/- 5%
56K +/- 5%
100K +/- 5%
200K +/- 5%

7 NC

SKU ID

0

*

1
2
3
4
5
6
7

EDL71 10/100 LAN WO/TV TUNER
EDL71 GIGA LAN W/TV TURNER
EDL71 10/100LAN W/TV TUNER
EDL71 GIGA WO/TV TUNER
EDL71 10/100 LAN WO/TV TUNER
EDL71 10/100LAN W/TV TUNER
EDL71 GIGA WO/TV TUNER
EDL71 GIGA LAN W/TV TURNER

AD_BID

0 V

Vtyp

AD_BID

0 V 0 V

V

AD_BID

0.216 V 0.250 V 0.289 V

0.436 V

0.712 V

1.036 V

0.503 V

0.819 V

0.538 V

0.875 V

1.185 V 1.264 V

1.453 V 1.650 V 1.759 V

1.935 V

2.500 V

2.200 V

3.300 V

2.341 V

3.300 V

EDL71 SKU

TV@ : TV Tunner
100@ : 10/100M LAN

GIGA@ : 10/100M/1000M LAN

Title

Size Document Number Rev

2

Date: Sheet of

Compal Electronics, Inc.

Notes List

HDL75 LA3041

max

1

0.1

460Thursday, July 28, 2005

5

H_A#[3..31]<9>

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12

D D

H_REQ#[0..4]<9>

H_ADSTB#0<9>

H_RS#[0..2]<9>

H_THERMTRIP#

H_CPUPWRGD

5

H_ADSTB#1<9>

R801 0_0402_5%@
R802 0_0402_5%@

CLK_CPU_BCLK<16>
CLK_CPU_BCLK#<16>

H_ADS#<9>
H_BNR#<9>

H_BPRI#<9>

H_BR0#<9>

H_DEFER#<9>

H_DRDY#<9>
H_HIT#<9>
H_HITM#<9>

H_LOCK#<9>
H_RESET#<9>

H_TRDY#<9>

H_DBSY#<9>
H_DPSLP#<27>
H_DPRSLP#<27>

H_DPWR#<9>

H_CPUSLP#<9,27>

H_THERMDA<8>
H_THERMDC<8>
H_THERMTRIP#<8,9,27>

C C

B B

A A

CLK_CPU_ITP<16>
CLK_CPU_ITP#<16>

R72

56_0402_5%

+VCCP

H_CPUPWRGD<27>

+VCCP

+VCCP

1 2

H_THERMDA, H_THERMDC routing together.
Trace width / Spacing = 10 / 10 mil

R88 75_0402_5%

1 2

R74

200_0402_5%

1 2

H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

H_ADSTB#0
H_ADSTB#1

CPU_ITTP

12

CPU_ITTP#

12

CLK_CPU_BCLK
CLK_CPU_BCLK#

H_ADS#
H_BNR#

H_BPRI#

H_BR0#
H_DEFER#
H_DRDY#
H_HIT#
H_HITM#
H_IERR#
H_LOCK#
H_RESET#

H_RS#0
H_RS#1
H_RS#2
H_TRDY#

ITP_DBRESET#

H_DBSY#
H_DPSLP#
H_DPRSLP#

H_PROCHOT#

H_CPUSLP#
ITP_TCK
ITP_TDI
ITP_TDO
TEST1
TEST2
ITP_TMS
ITP_TRST#

H_THERMDC

75ohm pull-up of H_THERMTRIP#
should be within 2" from the
series resistor

Add pullups for PWRGOOD and THERMTRIP per INTEL

JP1A

P4
U4
V3
R3
V2

W1

T4

W2

Y4
Y1
U1

AA3

Y3
AA2
AF4
AC4
AC7
AC3
AD3
AE4
AD2
AB4
AC6
AD5
AE2
AD6
AF3
AE1
AF1

R2

P3

T2

P1

T1

U3
AE5

A16
A15

B15
B14

N2

L1

J3
N4
L4
H2
K3
K4
A4

J2

B11

H1
K1
L2

M3

C8
B8
A9
C9

A7

M2

B7

G1
C19
A10
B10
B17

E4

A6
A13
C12
A12

C5

F23
C11
B13

B18
A18
C17

TYCO_1612365-1_Dothan

<BOM Structu re>

A3#
A4#
A5#
A6#
A7#
A8#
A9#
A10#
A11#
A12#
A13#
A14#
A15#
A16#
A17#
A18#
A19#
A20#
A21#
A22#
A23#
A24#

ADDR GROUP

A25#
A26#
A27#
A28#
A29#
A30#
A31#

REQ0#
REQ1#
REQ2#
REQ3#
REQ4#

ADSTB0#
ADSTB1#

ITP_CLK0
ITP_CLK1

BCLK0
BCLK1

ADS#
BNR#
BPRI#
BR0#
DEFER#
DRDY#
HIT#
HITM#
IERR#
LOCK#
RESET#

RS0#
RS1#
RS2#
TRDY#

BPM0#
BPM1#
BPM2#
BPM3#

DBR#
DBSY#
DPSLP#
DPRSTP#
DPWR#
PRDY#
PREQ#
PROCHOT#

PWRGOOD
SLP#
TCK
TDI
TDO
TEST1
TEST2
TMS
TRST#

THERMDA
THERMDC
THERMTRIP#

4

Dothan

DATA GROUP

HOST CLK

CONTROL GROUP

MISC

THERMAL
DIODE

4

LEGACY CPU

3

H_D#[0..63] <9>

A19

D0#

A25

D1#

A22

D2#

B21

D3#

A24

D4#

B26

D5#

A21

D6#

B20

D7#

C20

D8#

B24

D9#

D24

D10#

E24

D11#

C26

D12#

B23

D13#

E23

D14#

C25

D15#

H23

D16#

G25

D17#

L23

D18#

M26

D19#

H24

D20#

F25

D21#

G24

D22#

J23

D23#

M23

D24#

J25

D25#

L26

D26#

N24

D27#

M25

D28#

H26

D29#

N25

D30#

K25

D31#

Y26

D32#

AA24

D33#

T25

D34#

U23

D35#

V23

D36#

R24

D37#

R26

D38#

R23

D39#

AA23

D40#

U26

D41#

V24

D42#

U25

D43#

V26

D44#

Y23

D45#

AA26

D46#

Y25

D47#

AB25

D48#

AC23

D49#

AB24

D50#

AC20

D51#

AC22

D52#

AC25

D53#

AD23

D54#

AE22

D55#

AF23

D56#

AD24

D57#

AF20

D58#

AE21

D59#

AD21

D60#

AF25

D61#

AF22

D62#

AF26

D63#

D25

DINV0#

J26

DINV1#

T24

DINV2#

AD20

DINV3#

C23

DSTBN0#

K24

DSTBN1#

W25

DSTBN2#

AE24

DSTBN3#

C22

DSTBP0#

L24

DSTBP1#

W24

DSTBP2#

AE25

DSTBP3#

C2

A20M#

D3

FERR#

A3

IGNNE#

B5

INIT#

D1

LINT0

D4

LINT1

C6

STPCLK#

B4

SMI#

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63

H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3
H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3

H_A20M#
H_FERR#
H_IGNNE#
H_INIT#
H_INTR

H_NMI

H_STPCLK#H_THERMDA

H_SMI#

H_DINV#0 <9>
H_DINV#1 <9>
H_DINV#2 <9>
H_DINV#3 <9>

3

H_A20M# <27>
H_FERR# <27>
H_IGNNE# <27>
H_INIT# <27>
H_INTR <27>
H_NMI <27>

H_STPCLK# <27>
H_SMI# <27>

H_DSTBN#[0..3] <9>

H_DSTBP#[0..3] <9>

2

R147
56_0402_5%

2

1

+3V

R63

150_0603_1%

1 2

+VCCP

R64

54.9_0603_1%@

1 2

R65

54.9_0603_1%@

1 2

+VCCP

R66

39.2_0603_1%

1 2

R68

150_0603_1%

1 2

R70

680_0402_5%

1 2

R71

27.4_0603_1%

1 2

+3VS

+VCCP

12

R730
56_0402_5%

12

H_PROCHOT#

TEST2

TEST1

R149

1 2

1K_0402_5%@

R148

1 2

1K_0402_5%@

Title

Size Document Number Rev

Date: Sheet of

12

R731
1K_0402_5%

1

C

Q67

2

B

2SC2411K_SC59

E

3

Compal Electronics, Inc.

Dothan Processor in mFCPGA479

HDL75 LA3041

ITP_DBRESET#

This shall place near CPU

1

ITP_TDO

H_RESET#

ITP_TMS

ITP_TDI

ITP_TRST#

ITP_TCK

PROCHOT# <40>

0.1

560Thursday, July 28, 2005

5

D D

C C

B B

+VCCP

R_A

12

V_CPU_GTLREF

R79
1K_0603_1%

R_B

12

R84
2K_0603_1%

Resistor placed within

0.5" of CPU pin.Trace
should be at least 25
miles away from any
other toggling signal.

27.4_0603_1%

R80

4

+VCCA_PROC

R78

0_0603_5%

1 2

+1.5VS

12

54.9_0603_1%

R81

1

1

C19

C18

14.5 mil
4 mil

14.5 mil
4 mil

12

27.4_0603_1%

R82

12

12

54.9_0603_1%

R83

2

0.01U_0402_16V7K

2

10U_0805_10V4Z

PSI#<54>
CPU_VID0<54>

CPU_VID1<54>
CPU_VID2<54>
CPU_VID3<54>
CPU_VID4<54>
CPU_VID5<54>

CPU_BSEL0<16>
CPU_BSEL1<16>

3

R75

54.9_0603_1%@

1 2
1 2

R76

54.9_0603_1%@

+VCCP

+CPU_CORE

V_CPU_GTLREF

VCCSENSE
VSSSENSE

H_PSI#
VID0

VID1
VID2
VID3
VID4
VID5

CPU_BSEL0
CPU_BSEL1

COMP0
COMP1
COMP2
COMP3

JP1B

AE7

VCCSENSE

AF6

VSSSENSE

F26

VCCA0

B1

VCCA1

N1

VCCA2

AC26

VCCA3

P23

VCCQ0

W4

VCCQ1

D10

VCCP

D12

VCCP

D14

VCCP

D16

VCCP

E11

VCCP

E13

VCCP

E15

VCCP

F10

VCCP

F12

VCCP

F14

VCCP

F16

VCCP

K6

VCCP

L5

VCCP

L21

VCCP

M6

VCCP

M22

VCCP

N5

VCCP

N21

VCCP

P6

VCCP

P22

VCCP

R5

VCCP

R21

VCCP

T6

VCCP

T22

VCCP

U21

VCCP

D6

VCC

D8

VCC

D18

VCC

D20

VCC

D22

VCC

E5

VCC

E7

VCC

E9

VCC

E17

VCC

E19

VCC

E21

VCC

F6

VCC

F8

VCC

F18

VCC

E1

PSI#

E2

VID0

F2

VID1

F3

VID2

G3

VID3

G4

VID4

H4

VID5

AD26

GTLREF

C16

BSEL0

C14

BSEL1

P25

COMP0

P26

COMP1

AB2

COMP2

AB1

COMP3

B2

RSVD

C3

RSVD

E26

RSVD

AF7

RSVD

AC1

RSVD

TYCO_1612365-1_Dothan

2

A2

VSS

A5

VSS

A8

VSS

A11

VSS

A14

VSS

A17

VSS

A20

VSS

A23

VSS

A26

VSS

B3

VSS

B6

VSS

B9

VSS

B12

Dothan

VSS

B16

VSS

B19

VSS

B22

VSS

B25

VSS

C1

VSS

C4

VSS

C7

VSS

C10

VSS

C13

VSS

C15

VSS

C18

VSS

C21

VSS

C24

VSS

D2

VSS

D5

VSS

D7

VSS

D9

VSS

D11

VSS

D13

VSS

D15

VSS

D17

VSS

D19

VSS

D21

VSS

D23

VSS

D26

VSS

E3

VSS

E6

VSS

E8

VSS

E10

VSS

E12

VSS

E14

VSS

E16

VSS

E18

VSS

E20

VSS

E22

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

E25
F1
F4
F5
F7
F9
F11
F13
F15
F17
F19
F21
F24
G2
G6
G22
G23
G26
H3
H5
H21
H25
J1
J4
J6
J22
J24
K2
K5
K21
K23
K26
L3
L6
L22
L25
M1

POWER, GROUNG, RESERVED SIGNALS AND NC

+CPU_CORE

JP1C

F20

VCC

F22

VCC

G5

VCC

G21

VCC

H6

VCC

H22

VCC

J5

VCC

J21

VCC

K22

VCC

U5

VCC

V6

VCC

V22

VCC

W5

VCC

W21

VCC

Y6

VCC

Y22

VCC

AA5

VCC

AA7

VCC

AA9

VCC

AA11

VCC

AA13

VCC

AA15

VCC

AA17

VCC

AA19

VCC

AA21

VCC

AB6

VCC

AB8

VCC

AB10

VCC

AB12

VCC

AB14

VCC

AB16

VCC

AB18

VCC

AB20

VCC

AB22

VCC

AC9

VCC

AC11

VCC

AC13

VCC

AC15

VCC

AC17

VCC

AC19

VCC

AD8

VCC

AD10

VCC

AD12

VCC

AD14

VCC

AD16

VCC

AD18

VCC

AE9

VCC

AE11

VCC

AE13

VCC

AE15

VCC

AE17

VCC

AE19

VCC

AF8

VCC

AF10

VCC

AF12

VCC

AF14

VCC

AF16

VCC

AF18

VCC

M4

VSS

M5

VSS

M21

VSS

M24

VSS

N3

VSS

N6

VSS

N22

VSS

N23

VSS

N26

VSS

P2

VSS

P5

VSS

P21

VSS

P24

VSS

R1

VSS

R4

VSS

R6

VSS

R22

VSS

R25

VSS

T3

VSS

T5

VSS

T21

VSS

T23

VSS

TYCO_1612365-1_Dothan

Dothan

POWER, GROUND

1

T26

VSS

U2

VSS

U6

VSS

U22

VSS

U24

VSS

V1

VSS

V4

VSS

V5

VSS

V21

VSS

V25

VSS

W3

VSS

W6

VSS

W22

VSS

W23

VSS

W26

VSS

Y2

VSS

Y5

VSS

Y21

VSS

Y24

VSS

AA1

VSS

AA4

VSS

AA6

VSS

AA8

VSS

AA10

VSS

AA12

VSS

AA14

VSS

AA16

VSS

AA18

VSS

AA20

VSS

AA22

VSS

AA25

VSS

AB3

VSS

AB5

VSS

AB7

VSS

AB9

VSS

AB11

VSS

AB13

VSS

AB15

VSS

AB17

VSS

AB19

VSS

AB21

VSS

AB23

VSS

AB26

VSS

AC2

VSS

AC5

VSS

AC8

VSS

AC10

VSS

AC12

VSS

AC14

VSS

AC16

VSS

AC18

VSS

AC21

VSS

AC24

VSS

AD1

VSS

AD4

VSS

AD7

VSS

AD9

VSS

AD11

VSS

AD13

VSS

AD15

VSS

AD17

VSS

AD19

VSS

AD22

VSS

AD25

VSS

AE3

VSS

AE6

VSS

AE8

VSS

AE10

VSS

AE12

VSS

AE14

VSS

AE16

VSS

AE18

VSS

AE20

VSS

AE23

VSS

AE26

VSS

AF2

VSS

AF5

VSS

AF9

VSS

AF11

VSS

AF13

VSS

AF15

VSS

AF17

VSS

AF19

VSS

AF21

VSS

AF24

VSS

A A

Layout close CPU

5

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

Title

Size Document Number Rev

2

Date: Sheet

Compal Electronics, Inc.

Dothan Processor in mFCPGA479

HDL75 LA3041

660Thursday, July 28, 2005

1

of

0.1

5

4

3

2

1

+CPU_CORE

1

C20
10U_1206_6.3V6M

2

D D

C C

+CPU_CORE

1

2

+CPU_CORE

1

2

+CPU_CORE

1

2

C30
10U_1206_6.3V6M

C40
10U_1206_6.3V6M

C50
10U_1206_6.3V6M

1

C21
10U_1206_6.3V6M

2

1

C31
10U_1206_6.3V6M

2

1

C41
10U_1206_6.3V6M

2

1

C51
10U_1206_6.3V6M

2

1

C22
10U_1206_6.3V6M

2

1

C32
10U_1206_6.3V6M

2

1

C42
10U_1206_6.3V6M

2

1

C52
10U_1206_6.3V6M

2

1

C23
10U_1206_6.3V6M

2

1

C33
10U_1206_6.3V6M

2

1

C43
10U_1206_6.3V6M

2

1

C53
10U_1206_6.3V6M

2

1

C24
10U_1206_6.3V6M

2

1

C34
10U_1206_6.3V6M

2

1

C44
10U_1206_6.3V6M

2

1

C54
10U_1206_6.3V6M

2

+CPU_CORE

1

2

+CPU_CORE

1

2

+CPU_CORE

1

2

C25
10U_1206_6.3V6M

C35
10U_1206_6.3V6M

C45
10U_1206_6.3V6M

1

2

1

2

1

2

10uF 1206 X5R -> 85 degree

C26
10U_1206_6.3V6M

C36
10U_1206_6.3V6M

C46
10U_1206_6.3V6M

High Frequence Decoupling

1

C27
10U_1206_6.3V6M

2

1

C37
10U_1206_6.3V6M

2

1

C47
10U_1206_6.3V6M

2

1

C28
10U_1206_6.3V6M

2

1

C38
10U_1206_6.3V6M

2

1

C48
10U_1206_6.3V6M

2

1

C29
10U_1206_6.3V6M

2

1

C39
10U_1206_6.3V6M

2

1

C49
10U_1206_6.3V6M

2

Near VCORE regulator.

+CPU_CORE

1

+

C57

2

330U_D2E_2.5VM_R9

9mOhm
7343
PS CAP

1

2

+

C58

330U_D2E_2.5VM_R9

9mOhm
7343
PS CAP

C60

0.1U_0402_16V4Z

1

+

2

1

2

ESR <= 3m ohm
Capacitor > 880uF

1

C61

0.1U_0402_16V4Z

C62

0.1U_0402_16V4Z

2

1

C63

0.1U_0402_16V4Z

2

4

1

C64

0.1U_0402_16V4Z

2

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

1

C65

0.1U_0402_16V4Z

2

3

1

C66

0.1U_0402_16V4Z

2

1

C67

0.1U_0402_16V4Z

2

1

C68

0.1U_0402_16V4Z

2

2

1

C69

0.1U_0402_16V4Z

2

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

CPU Bypass

HDL75 LA3041

760Thursday, July 28, 2005

1

0.1

+

+

C59
150U_C_4VM

C56

330U_D2E_2.5VM_R9

9mOhm
7343
PS CAP

1

2

5

1

@

C55

2

B B

A A

330U_D2E_2.5VM_R9

9mOhm
7343
PS CAP

+VCCP

1

2

5

4

3

2

1

Fan Control circuit

+12VALW

1

D D

C140

1U_0603_10V4Z

EN_FAN1

1

2

EN_FAN1<40>

C C

0.1U_0402_16V4Z

12

R150

150K_0402_5%

C73

2

8

U3A

P

3

+IN

2

-IN

4

C143

2200P_0402_50V7K

1 2

R162

100K_0402_5%

1 2

OUT

G

LM358A_SO8

FAN1

1

D23

RB751V_SOD323

+5VS

6

2

1

D

Q31

S

SI3456DV-T1_TSOP6

4 5

1

C72
22U_1206_10V4Z

2

2

C17

1

0.001U_0402_50V7M

FANVOUT1

JP2

ACES_85205-0300

G

3

2 1

+3VS

12

R163
10K_0402_5%

1

C145

0.01U_0402_16V7K

2

1
2
3

FANSPEED1 <40>

Thermal Sensor G781

+3VS

2

C147

1

12

R146
10K_0402_5%@

Title

Size Document Number Rev

Date: Sheet

0.1U_0402_16V4Z

Compal Electronics, Inc.

FAN & Thermal Sensor

HDL75 LA3041

1

860Thursday, July 28, 2005

of

0.1

EC_SMC_2<40>
EC_SMD_2<40>

+3VALW

H_THERMDA
H_THERMDC

1

C148

2

8.2K_0402_5%

R513

R145 300_0402_5%

+VCCP

B B

+1.8V

12

R1018

10K_0402_1%

A A

10K_0402_1%

5

R1019

12

1 2

H_THERMTRIP#

+12VALW

5

+IN

6

-IN

@

U3B

OUT

LM358A_SO8

7

C146 1U_0603_10V4Z

2

Q8

CBE

2SC2411K_SC59

1

3

@

1 2

@

4

MAINPWON <47,49,50>H_THERMTRIP#<5,9,27>

+V_DDR_MCH_REF

2200P_0402_25V7K

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

H_THERMDA <5>
H_THERMDC <5>

H_THERMDA
H_THERMDC

12

12

U4

2

D+

3

D-

8

SCLK

7

SDATA

G781_SOP8

R512

8.2K_0402_5%

VDD1

ALERT#

THERM#

GND

W=15mil

1
6
4
5

2

5

H_A#[3..31]<5> H_D#[0..63] <5>

D D

H_REQ#[0..4]<5>

C C

H_DSTBN#[0..3]<5>

H_DSTBP#[0..3]<5>

Layout Guide
will show these
signals routed
differentially.

B B

H_RS#[0..2]<5>

T5 PAD

H_ADSTB#0<5>
H_ADSTB#1<5>

CLK_MCH_BCLK#<16>
CLK_MCH_BCLK<16>

H_DINV#0<5>
H_DINV#1<5>
H_DINV#2<5>
H_DINV#3<5>

H_RESET#<5>

H_ADS#<5>
H_TRDY#<5>
H_DPWR#<5>

H_DRDY#<5>
H_DEFER#<5>

T6 PAD

H_HITM#<5>
H_HIT#<5>
H_LOCK#<5>

H_BR0#<5>
H_BNR#<5>

H_BPRI#<5>

H_DBSY#<5>

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31

TP_H_PCREQ#

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
H_ADSTB#0
H_ADSTB#1

H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3
H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3

H_RESET#
H_ADS#

H_TRDY#
H_DRDY#

H_DEFER#
TP_H_EDRDY#
H_HITM#
H_HIT#
H_LOCK#
H_BR0#
H_BNR#
H_BPRI#
H_DBSY#

H_R_CPUSLP#

H_RS#0
H_RS#1
H_RS#2

G10

G11
G13

G12

AB1
AB2

A10

B10
E10

E11
F10

C10
C11
D11
C12
B13
A12
F12

E12
C13
B11
D13
A13
F13

A11

E13

H10

G9

C9
E9
B7

F9
D8

D9

A7
D7
B8
C7
A8
B9

G4

K1
R3
V3

G5

K2
R2

W4

H8
K3
T7
U5

F8
B5

G6

F7
E6
F6
D6
D4
B3
E7
A5
D5
C6

G8

A4
C5
B4

HA3#

Alviso

HA4#
HA5#
HA6#
HA7#
HA8#
HA9#
HA10#
HA11#
HA12#
HA13#
HA14#
HA15#
HA16#
HA17#
HA18#
HA19#
HA20#
HA21#
HA22#
HA23#
HA24#
HA25#
HA26#
HA27#
HA28#
HA29#
HA30#
HA31#

HPCREQ#
HREQ#0
HREQ#1
HREQ#2
HREQ#3
HREQ#4
HADSTB#0
HADSTB#1

HCLKN
HCLKP

HDSTBN#0
HDSTBN#1
HDSTBN#2
HDSTBN#3
HDSTBP#0
HDSTBP#1
HDSTBP#2
HDSTBP#3
HDINV#0
HDINV#1
HDINV#2
HDINV#3

HCPURST#
HADS#

HTRDY#
HDPWR#
HDRDY#
HDEFER#
HEDRDY#
HHITM#
HHIT#
HLOCK#
HBREQ0#
HBNR#
HBPRI#
HDBSY#
HCPUSLP#
HRS0#
HRS1#
HRS2#

HOST

HXRCOMP
HXSCOMP
HYRCOMP
HYSCOMP

ALVISO_BGA1257

U2A

HD0#
HD1#
HD2#
HD3#
HD4#
HD5#
HD6#
HD7#
HD8#

HD9#
HD10#
HD11#
HD12#
HD13#
HD14#
HD15#
HD16#
HD17#
HD18#
HD19#
HD20#
HD21#
HD22#
HD23#
HD24#
HD25#
HD26#
HD27#
HD28#
HD29#
HD30#
HD31#
HD32#
HD33#
HD34#
HD35#
HD36#
HD37#
HD38#
HD39#
HD40#
HD41#
HD42#
HD43#
HD44#
HD45#
HD46#
HD47#
HD48#
HD49#
HD50#
HD51#
HD52#
HD53#
HD54#
HD55#
HD56#
HD57#
HD58#
HD59#
HD60#
HD61#
HD62#
HD63#

HVREF

HXSWING
HYSWING

4

E4
E1
F4
H7
E2
F1
E3
D3
K7
F2
J7
J8
H6
F3
K8
H5
H1
H2
K5
K6
J4
G3
H3
J1
L5
K4
J5
P7
L7
J3
P5
L3
U7
V6
R6
R5
P3
T8
R7
R8
U8
R4
T4
T5
R1
T3
V8
U6
W6
U3
V5
W8
W7
U2
U1
Y5
Y2
V4
Y7
W1
W3
Y3
Y6
W2

J11
C1
C2
T1
L1
D1
P1

H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63

H_VREF
H_XRCOMP
H_XSCOMP
H_YRCOMP
H_YSCOMP
H_SWNG0
H_SWNG1

R97

24.9_0603_1%

12

H_SWNG1

H_SWNG0

R98

24.9_0603_1%

C70

C71

0.1U_0402_16V4Z

+VCCP

12

R91

54.9_0603_1%

12

R85

1

R86

2

0.1U_0402_16V4Z

R87

1

R89

2

12

R92

54.9_0603_1%

+VCCP

12

221_0603_1%

12

100_0603_1%

+VCCP

12

221_0603_1%

12

100_0603_1%

1

C74

2

0.1U_0402_16V4Z

3

+VCCP

R94

100_0603_1%

R96

200_0603_1%

2

U2B

DMI_TXN0
DMI_TXN1
DMI_TXN2
DMI_TXN3

DMI_TXP1
DMI_TXP2
DMI_TXP3

DMI_RXN0
DMI_RXN1
DMI_RXN2
DMI_RXN3

DMI_RXP0
DMI_RXP1
DMI_RXP2
DMI_RXP3

M_CLK_DDR0
M_CLK_DDR1

M_CLK_DDR3
M_CLK_DDR4

M_CLK_DDR#0
M_CLK_DDR#1

M_CLK_DDR#3
M_CLK_DDR#4

DDR_CKE0_DIMMA
DDR_CKE1_DIMMA
DDR_CKE2_DIMMB
DDR_CKE3_DIMMB

DDR_CS0_DIMMA#
DDR_CS1_DIMMA#
DDR_CS2_DIMMB#
DDR_CS3_DIMMB#

M_OCDOCMP0
M_OCDOCMP1

M_ODT0
M_ODT1
M_ODT2
M_ODT3

SMRCOMPN
SMRCOMPP

1

C900

C901

2

0.1U_0402_16V4Z

DMI_TXN0<28>
DMI_TXN1<28>
DMI_TXN2<28>
DMI_TXN3<28>

DMI_TXP0<28>
DMI_TXP1<28>
DMI_TXP2<28>
DMI_TXP3<28>

DMI_RXN0< 28>
DMI_RXN1< 28>
DMI_RXN2< 28>
DMI_RXN3< 28>

DMI_RXP0<28>
DMI_RXP1<28>
DMI_RXP2<28>
DMI_RXP3<28>

M_CLK_DDR0<14>
M_CLK_DDR1<14>

M_CLK_DDR3<15>
M_CLK_DDR4<15>

M_CLK_DDR#0<14>
M_CLK_DDR#1<14>

M_CLK_DDR#3<15>
M_CLK_DDR#4<15>

DDR_CKE0_DIMMA<14>
DDR_CKE1_DIMMA<14>
DDR_CKE2_DIMMB<15>
DDR_CKE3_DIMMB<15>

DDR_CS0_DIMMA#<14>
DDR_CS1_DIMMA#<14>
DDR_CS2_DIMMB#<15>
DDR_CS3_DIMMB#<15>

M_ODT0<14>

+1.8V

12

R761

80.6_0603_1%

Layout Note:
Route as short
as possible

1 2

12

12

M_ODT1<14>
M_ODT2<15>
M_ODT3<15>

R760

80.6_0603_1%

+V_DDR_MCH_REF

1

2

0.1U_0402_16V4Z

AA31
AB35
AC31
AD35

Y31
AA35
AB31
AC35

AA33
AB37
AC33
AD37

Y33
AA37
AB33
AC37

AM33

AL1
AE11

AJ34

AF6
AC10

AN33

AK1
AE10

AJ33

AF5
AD10

AP21
AM21
AH21
AK21

AN16
AM14
AH15
AG16

AF22
AF16

AP14

AL15
AM11
AN10

AK10
AK11

AF37

AD1
AE27
AE28

AF9

AF10

ALVISO_BGA1257

DMIRXN0
DMIRXN1
DMIRXN2
DMIRXN3

DMIRXP0
DMIRXP1
DMIRXP2
DMIRXP3

DMITXN0
DMITXN1
DMITXN2
DMITXN3

DMITXP0
DMITXP1
DMITXP2
DMITXP3

SM_CK0
SM_CK1
SM_CK2
SM_CK3
SM_CK4
SM_CK5

SM_CK0#
SM_CK1#
SM_CK2#
SM_CK3#
SM_CK4#
SM_CK5#

SM_CKE0
SM_CKE1
SM_CKE2
SM_CKE3

SM_CS0#
SM_CS1#
SM_CS2#
SM_CS3#

SM_OCDCOMP0
SM_OCDCOMP1
SM_ODT0
SM_ODT1
SM_ODT2
SM_ODT3

SMRCOMPN
SMRCOMPP
SMVREF0
SMVREF1
SMXSLEWIN
SMXSLEWOUT
SMYSLEWIN
SMYSLEWOUT

CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8

CFG9
CFG10
CFG11
CFG12

DMIDDR MUXING

CFG13
CFG14
CFG15
CFG16
CFG17
CFG18
CFG19
CFG20

RSVD21
RSVD22

CFG/RSVD

RSVD23
RSVD24
RSVD25
RSVD26
RSVD27

BM_BUSY#

EXT_TS0#
EXT_TS1#

THRMTRIP#

PWROK

RSTIN#

PM

DREF_CLKN

DREF_CLKP

DREF_SSCLKP

CLK

DREF_SSCLKN

NC1
NC2
NC3
NC4
NC5
NC6
NC7
NC8
NC9

NC10

NC

NC11

G16
H13
G14
F16
F15
G15
E16
D17
J16
D15
E15
D14
E14
H12
C14
H15
J15
H14
G22
G23
D23
G25
G24
J17
A31
A30
D26
D25

J23
J21
H22
F5
AD30
AE29

A24
A23
D37
C37

AP37
AN37
AP36
AP2
AP1
AN1
B1
A2
B37
A36
A37

MCH_CLKSEL1
MCH_CLKSEL0

PM_EXTTS#0
PM_EXTTS#1

VGATE

PLTRST_R#

1

Note :
CFG3:17 has
internal pullup,
CFG18:19 has
internal pulldown

CFG0

CFG5DMI_TXP0
CFG6
CFG7

CFG9

CFG12
CFG13

CFG16
CFG18

CFG19

1 2

R90 100_0402_5%

CFG0 <11>
MCH_CLKSEL1 <16>

MCH_CLKSEL0 <16>

T3PAD
T4PAD

CFG5 <11>

CFG6 <11>

CFG7 <11>

CFG9 <11>

CFG12 <11>

CFG13 <11>

CFG16 <11>

CFG18 <11>

CFG19 <11>

PM_BMBUSY# <28>

H_THERMTRIP# <5,8,27>

DREFCLK# <16>

DREFCLK <16>

DREF_SSCLK <16>
DREF_SSCLK# <16>

1 2

R1054 0_0402_5%

1 2

R1055 0_0402_5%

2@
2@

VGATE <16,28,54>

PLTRST# <26,28,34,38,40,45>

+1.5VS

M_OCDOCMP0
M_OCDOCMP1

R99

H_CPUSLP#<5,27>

A A

H_CPUSLP# H_R_CPUSLP#

Note:
"Do not install R99 for Dothan-A,
Install R99 for Dothan-B"

5

0_0402_5%

1 2

Layout Note:
H_XRCOMP & H_YRCOMP trace width
and spacing is 10/20

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

12

12

@

@

R100

R101

40.2_0402_1%

40.2_0402_1%

3

PM_EXTTS#0

PM_EXTTS#1

Title

Size Document Number Rev

2

Date: Sheet of

Compal Electronics, Inc.

Alviso(1 of 5)

R102

10K_0402_5%

R103

10K_0402_5%

HDL75 LA3041

+2.5VS

12

12

0.1

960Thursday, July 28, 2005

1

5

4

3

2

1

DDR_A_BS#0<14>
DDR_A_BS#1<14>

D D

C C

This Symbol as same
as Intel CRB

B B

schematic, So Layout
Guide will show these
signals routed
differentially.

DDR_A_BS#2<14>
DDR_A_DM[0..7]<14>

DDR_A_DQS[0..7]<14>

DDR_A_DQS#[0..7]<14>

DDR_A_MA[0..13]<14>

DDR_A_CAS#<14> DDR_B_RAS#<15>
DDR_A_RAS#<14>

DDR_A_WE#<14>

DDR_A_BS#0
DDR_A_BS#1
DDR_A_BS#2

DDR_A_DM0
DDR_A_DM1
DDR_A_DM2
DDR_A_DM3
DDR_A_DM4
DDR_A_DM5
DDR_A_DM6
DDR_A_DM7

DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7

DDR_A_DQS#0
DDR_A_DQS#1
DDR_A_DQS#2
DDR_A_DQS#3
DDR_A_DQS#4
DDR_A_DQS#5
DDR_A_DQS#6
DDR_A_DQS#7

DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13

DDR_A_CAS#
DDR_A_RAS#

DDR_A_WE#

AK15

SA_BS0#

AK16

SA_BS1#

AL21

SA_BS2#

AJ37

SA_DM0

AP35

SA_DM1

AL29

SA_DM2

AP24

SA_DM3

AP9

SA_DM4

AP4

SA_DM5

AJ2

SA_DM6

AD3

SA_DM7

AK36

SA_DQS0

AP33

SA_DQS1

AN29

SA_DQS2

AP23

SA_DQS3

AM8

SA_DQS4

AM4

SA_DQS5

AJ1

SA_DQS6

AE5

SA_DQS7

AK35

SA_DQS0#

AP34

SA_DQS1#

AN30

SA_DQS2#

AN23

SA_DQS3#

AN8

SA_DQS4#

AM5

SA_DQS5#

AH1

SA_DQS6#

AE4

SA_DQS7#

AL17

SA_MA0

AP17

SA_MA1

AP18

SA_MA2

AM17

SA_MA3

AN18

SA_MA4

AM18

SA_MA5

AL19

SA_MA6

AP20

SA_MA7

AM19

SA_MA8

AL20

SA_MA9

AM16

SA_MA10

AN20

SA_MA11

AM20

SA_MA12

AM15

SA_MA13

AN15

SA_CAS#

AP16

SA_RAS#

AF29

SA_RCVENIN#

AF28

SA_RCVENOUT#

AP15

SA_WE#

ALVISO_BGA1257

U2C

SADQ0
SADQ1
SADQ2
SADQ3
SADQ4
SADQ5
SADQ6
SADQ7
SADQ8

SADQ9
SADQ10
SADQ11
SADQ12
SADQ13
SADQ14
SADQ15
SADQ16
SADQ17
SADQ18
SADQ19
SADQ20
SADQ21
SADQ22
SADQ23
SADQ24
SADQ25
SADQ26
SADQ27
SADQ28
SADQ29
SADQ30
SADQ31
SADQ32
SADQ33
SADQ34
SADQ35
SADQ36
SADQ37
SADQ38
SADQ39
SADQ40
SADQ41
SADQ42
SADQ43

DDR MEMORY SYSTEM A

SADQ44
SADQ45
SADQ46
SADQ47
SADQ48
SADQ49
SADQ50
SADQ51
SADQ52
SADQ53
SADQ54
SADQ55
SADQ56
SADQ57
SADQ58
SADQ59
SADQ60
SADQ61
SADQ62
SADQ63

AG35
AH35
AL35
AL37
AH36
AJ35
AK37
AL34
AM36
AN35
AP32
AM31
AM34
AM35
AL32
AM32
AN31
AP31
AN28
AP28
AL30
AM30
AM28
AL28
AP27
AM27
AM23
AM22
AL23
AM24
AN22
AP22
AM9
AL9
AL6
AP7
AP11
AP10
AL7
AM7
AN5
AN6
AN3
AP3
AP6
AM6
AL4
AM3
AK2
AK3
AG2
AG1
AL3
AM2
AH3
AG3
AF3
AE3
AD6
AC4
AF2
AF1
AD4
AD5

DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63

DDR_A_D[0..63] <14>

This Symbol as same
as Intel CRB
schematic, So Layout
Guide will show these
signals routed
differentially.

DDR_B_BS#0<15>
DDR_B_BS#1<15>
DDR_B_BS#2<15>
DDR_B_DM[0..7]<15>

DDR_B_DQS[0..7]<15>

DDR_B_DQS#[0..7]<15>

DDR_B_MA[0..13]<15>

DDR_B_CAS#<15>

DDR_B_WE#<15>

DDR_B_BS#0
DDR_B_BS#1
DDR_B_BS#2

DDR_B_DM0
DDR_B_DM1
DDR_B_DM2
DDR_B_DM3
DDR_B_DM4
DDR_B_DM5
DDR_B_DM6
DDR_B_DM7

DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4
DDR_B_DQS5
DDR_B_DQS6
DDR_B_DQS7

DDR_B_DQS#0
DDR_B_DQS#1
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS#4
DDR_B_DQS#5
DDR_B_DQS#6
DDR_B_DQS#7

DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13

DDR_B_CAS#
DDR_B_RAS#

DDR_B_WE#

AJ15
AG17
AG21

AF32
AK34
AK27
AK24

AJ10

AK5
AE7
AB7

AF34
AK32

AJ28
AK23

AM10

AH6
AF8
AB4

AF35
AK33
AK28

AJ23

AL10

AH7
AF7
AB5

AH17
AK17
AH18

AJ18
AK18

AJ19
AK19
AH19

AJ20
AH20

AJ16
AG18
AG20
AG15

AH14
AK14
AF15
AF14
AH16

SB_BS0#
SB_BS1#
SB_BS2#

SB_DM0
SB_DM1
SB_DM2
SB_DM3
SB_DM4
SB_DM5
SB_DM6
SB_DM7

SB_DQS0
SB_DQS1
SB_DQS2
SB_DQS3
SB_DQS4
SB_DQS5
SB_DQS6
SB_DQS7

SB_DQS0#
SB_DQS1#
SB_DQS2#
SB_DQS3#
SB_DQS4#
SB_DQS5#
SB_DQS6#
SB_DQS7#

SB_MA0
SB_MA1
SB_MA2
SB_MA3
SB_MA4
SB_MA5
SB_MA6
SB_MA7
SB_MA8
SB_MA9
SB_MA10
SB_MA11
SB_MA12
SB_MA13

SB_CAS#
SB_RAS#
SB_RCVENIN#
SB_RCVENOUT#
SB_WE#

ALVISO_BGA1257

U2D

SBDQ0
SBDQ1
SBDQ2
SBDQ3
SBDQ4
SBDQ5
SBDQ6
SBDQ7
SBDQ8

SBDQ9
SBDQ10
SBDQ11
SBDQ12
SBDQ13
SBDQ14
SBDQ15
SBDQ16
SBDQ17
SBDQ18
SBDQ19
SBDQ20
SBDQ21
SBDQ22
SBDQ23
SBDQ24
SBDQ25
SBDQ26
SBDQ27
SBDQ28
SBDQ29
SBDQ30
SBDQ31
SBDQ32
SBDQ33
SBDQ34
SBDQ35
SBDQ36
SBDQ37
SBDQ38
SBDQ39
SBDQ40
SBDQ41
SBDQ42

DDR SYSTEM MEMORY B

SBDQ43
SBDQ44
SBDQ45
SBDQ46
SBDQ47
SBDQ48
SBDQ49
SBDQ50
SBDQ51
SBDQ52
SBDQ53
SBDQ54
SBDQ55
SBDQ56
SBDQ57
SBDQ58
SBDQ59
SBDQ60
SBDQ61
SBDQ62
SBDQ63

AE31
AE32
AG32
AG36
AE34
AE33
AF31
AF30
AH33
AH32
AK31
AG30
AG34
AG33
AH31
AJ31
AK30
AJ30
AH29
AH28
AK29
AH30
AH27
AG28
AF24
AG23
AJ22
AK22
AH24
AH23
AG22
AJ21
AG10
AG9
AG8
AH8
AH11
AH10
AJ9
AK9
AJ7
AK6
AJ4
AH5
AK8
AJ8
AJ5
AK4
AG5
AG4
AD8
AD9
AH4
AG6
AE8
AD7
AC5
AB8
AB6
AA8
AC8
AC7
AA4
AA5

DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63

DDR_B_D[0..63] <15>

A A

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

Alviso(2 of 5)

HDL75 LA3041

1

0.1

10 60Thursday, July 28, 2005

5

AB29
AC29

12

U2G

H24

SDVOCTRL_DATA

H25

SDVOCTRL_CLK
GCLKN
GCLKP

A15

TVDAC_A

C16

TVDAC_B

A17

TVDAC_C

J18

TV_REFSET

B15

TV_IRTNA

B16

TV_IRTNB

B17

TV_IRTNC

E24

DDCCLK

E23

DDCDATA

E21

BLUE

D21

BLUE#

C20

GREEN

B20

GREEN#

A19

RED

B19

RED#

H21

VSYNC

G21

HSYNC

J20

REFSET

E25

LBKLT_CTL

F25

LBKLT_EN

C23

LCTLA_CLK

C22

LCTLB_DATA

F23

LDDC_CLK

F22

LDDC_DATA

F26

LVDD_EN

C33

LIBG

C31

LVBG

F28

LVREFH

F27

LVREFL

B30

LACLKN

B29

LACLKP

C25

LBCLKN

C24

LBCLKP

B34

LADATAN0

B33

LADATAN1

B32

LADATAN2

A34

LADATAP0

A33

LADATAP1

B31

LADATAP2

C29

LBDATAN0

D28

LBDATAN1

C27

LBDATAN2

C28

LBDATAP0

D27

LBDATAP1

C26

LBDATAP2

MISCTVVGALVDS

EXP_RXN2/SDVO_FLDSTALL#

EXP_RXP2/SDVO_FLDSTALL

PCI - EXPRESS GRAPHICS

SDVO_CTRLDATA

12

12

1@

R110

150_0603_1%

R1113 0_0402_5%1@

12

R93

SDVO_CTRLCLK

12

1@

1@

R111

R112

150_0603_1%

150_0603_1%

R117

255_0603_1%

1 2

LCTLA_CLK
LCTLB_DATA
LDDC_CLK
LDDC_DATA
LVDD_EN
L_IBG

1.5K_0603_5%

TVIREF

12

12

BIA_PWM

R120

4.99K_0603_1%

CLK_MCH_3GPLL#<16>
CLK_MCH_3GPLL<16>

COMP/B<24>
Y/G<24>
C/R<24>

D D

1@

R109

INT_CLK_DDC2<24>
INT_DAT_DDC2<24>

INTCRT_B<24>
INTCRT_G<24>
INTCRT_R<24>
INT_VSYNC<24>

INT_HSYNC<24>

BIA_PWM<23>

BACKLITE_ON7,23,40>

C C

100K_0402_5%

GM_ENVDD<23>

LCD_ACLK-<23>
LCD_ACLK+<23>
LCD_BCLK-<23>
LCD_BCLK+<23>

LCD_A0-<23>
LCD_A1-<23>
LCD_A2-<23>

LCD_A0+<23>
LCD_A1+<23>
LCD_A2+<23>

LCD_B0-<23>
LCD_B1-<23>

B B

LCD_B2-<23>

LCD_B0+<23>
LCD_B1+<23>
LCD_B2+<23>

4

EXP_COMPI

EXP_ICOMPO

EXP_RXN0/SDVO_TVCLKIN#

EXP_RXN1/SDVO_INT#

EXP_RXN3
EXP_RXN4
EXP_RXN5
EXP_RXN6
EXP_RXN7
EXP_RXN8

EXP_RXN9
EXP_RXN10
EXP_RXN11
EXP_RXN12
EXP_RXN13
EXP_RXN14
EXP_RXN15

EXP_RXP0/SDVO_TVCLKIN

EXP_RXP1/SDVO_INT

EXP_RXP3

EXP_RXP4

EXP_RXP5

EXP_RXP6

EXP_RXP7

EXP_RXP8

EXP_RXP9
EXP_RXP10
EXP_RXP11
EXP_RXP12
EXP_RXP13
EXP_RXP14
EXP_RXP15

EXP_TXN0/SDVOB_RED#

EXP_TXN1/SDVOB_GREEN#

EXP_TXN2/SDVOB_BLUE#

EXP_TXN3/SDVOB_CLKN
EXP_TXN4/SDVOC_RED#

EXP_TXN5/SDVOC_GREEN#

EXP_TXN6/SDVOC_BLUE#

EXP_TXN7/SDVOC_CLKN

EXP_TXP1/SDVOB_GREEN

EXP_TXP2/SDVOB_BLUE
EXP_TXP3/SDVOB_CLKP

EXP_TXP5/SDVOC_GREEN

EXP_TXP6/SDVOC_BLUE
EXP_TXP7/SDVOC_CLKP

EXP_TXN8

EXP_TXN9

EXP_TXN10
EXP_TXN11
EXP_TXN12
EXP_TXN13
EXP_TXN14
EXP_TXN15

EXP_TXP0/SDVOB_RED

EXP_TXP4/SDVOC_RED

EXP_TXP8

EXP_TXP9

EXP_TXP10
EXP_TXP11
EXP_TXP12
EXP_TXP13
EXP_TXP14
EXP_TXP15

D36
D34

E30
F34
G30
H34
J30
K34
L30
M34
N30
P34
R30
T34
U30
V34
W30
Y34

D30
E34
F30
G34
H30
J34
K30
L34
M30
N34
P30
R34
T30
U34
V30
W34

E32
F36
G32
H36
J32
K36
L32
M36
N32
P36
R32
T36
U32
V36
W32
Y36

D32
E36
F32
G36
H32
J36
K32
L36
M32
N36
P32
R36
T32
U36
V32
W36

PEGCOMP

EXP_RXN0
EXP_RXN1
EXP_RXN2
EXP_RXN3
EXP_RXN4
EXP_RXN5
EXP_RXN6
EXP_RXN7
EXP_RXN8
EXP_RXN9
EXP_RXN10
EXP_RXN11
EXP_RXN12
EXP_RXN13
EXP_RXN14
EXP_RXN15

EXP_RXP0
EXP_RXP1
EXP_RXP2
EXP_RXP3
EXP_RXP4
EXP_RXP5
EXP_RXP6
EXP_RXP7
EXP_RXP8
EXP_RXP9
EXP_RXP10
EXP_RXP11
EXP_RXP12
EXP_RXP13
EXP_RXP14
EXP_RXP15

EXP_TXN0
EXP_TXN1
EXP_TXN2
EXP_TXN3
EXP_TXN4
EXP_TXN5
EXP_TXN6
EXP_TXN7
EXP_TXN8
EXP_TXN9
EXP_TXN10
EXP_TXN11
EXP_TXN12
EXP_TXN13
EXP_TXN14
EXP_TXN15

EXP_TXP0
EXP_TXP1
EXP_TXP2
EXP_TXP3
EXP_TXP4
EXP_TXP5
EXP_TXP6
EXP_TXP7
EXP_TXP8
EXP_TXP9
EXP_TXP10
EXP_TXP11
EXP_TXP12
EXP_TXP13
EXP_TXP14
EXP_TXP15

R104

24.9_0603_1%

1 2

EXP_RXN[0..15]

This Symbol as same
as Intel CRB
schematic, So Layout
Guide will show these
signals routed
differentially.

EXP_RXP[0..15]

EXP_TXN[0..15]

EXP_TXP[0..15]

+1.5VS_PCIE

EXP_RXN[0..15] <20>

EXP_RXP[0..15] <20>

EXP_TXN[0..15] <20>

EXP_TXP[0..15] <20>

3

Strap Table

CFG5

CFG6

CFG7

CFG9

CFG[13:12]

CFG16
(FSB Dynamic
ODT)

CFG18
(VCC Select)

CFG19
(VTT Select)

SDVO_CTRLDATA

Low = DMI x 2
High = DMI x 4
Low = DDR-II
High = DDR-I
Low = DT/Transportable CPU
High = Mobile CPU
Low = Reverse Lane
High = Normal Operation
00 = Reserved

01 = XOR Mode Enabled
10 = All Z Mode Enabled
11 = Normal Operation

(Default)

Low = Disabled
High = Enabled

Low = 1.05V (Default)
High = 1.5V
Low = 1.05V (Default)
High = 1.2V
Low = No SDVO Device Present

(Default)

High = SDVO Device Present

2

CFG0<9>

*

*

*

*

CFG5<9>
CFG7<9>
CFG6<9>
CFG9<9>
CFG12<9>
CFG13<9>
CFG16<9>

*

*

CFG18<9>
CFG19<9>

*

R105 10K_0402_5%

R106 2.2K_0402_5%@
R108 2.2K_0402_5%@
R107 2.2K_0402_5%
R113 2.2K_0402_5%@
R114 2.2K_0402_5%@
R115 2.2K_0402_5% @
R116 2.2K_0402_5%@

CFG[3:17] have internal pullup

R118 1K_0402_5%
R119 1K_0402_5%@

1

1 2
1 2
1 2
1 2
1 2
1 2
1 2

1 2
1 2

+VCCP

12

+2.5VS

@

CFG[18:19] have internal pulldown

*

+2.5VS

*

SDVO_CTRLCLK

SDVO_CTRLDATA

R1180 3K_0402_5%@

1 2

R121 3K_0402_5%@

1 2

Have internal pulldown

+2.5VS

1@

1 2

R127 2.2K_0402_5%

1@

1 2

R128 2.2K_0402_5%

A A

1@

1 2

R133 100K_0402_5%

5

LCTLA_CLK

LCTLB_DATA

12

R122150_0603_1% 1@

12

R123150_0603_1% 1@

12

R124150_0603_1% 1@

BIA_PWM

INTCRT_R
INTCRT_G
INTCRT_B

ALVISO_BGA1257

1@

R129

LDDC_CLK

LDDC_DATA

+2.5VS

12

2.2K_0402_5%

4

12

1@

+2.5VS

R130

2.2K_0402_5%
Q4

BSS138_SOT23

BSS138_SOT23

+3VS

12

R132

2.2K_0402_5%

1@

1@

D

S

13

G

2

G

2

13

D

S

1@

Q6

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

12

R131

2.2K_0402_5%

1@

LCD_DDCCLK

LCD_DDCDATA

LCD_DDCCLK <23>

LCD_DDCDATA <23>

3

Title

Size Document Number Rev

2

Date: Sheet of

Compal Electronics, Inc.

Alviso(3 of 5)

HDL75 LA3041

11 60Thursday, July 28, 2005

1

0.1

5

U2F

K13

+VCCP

1

1

+

C159

2

150U_C_4VM

150U_C_4VM

+VCCP

1

C94

2

2.2U_0805_16V4Z

4.7U_0805_10V4Z

1

0.47U_0603_16V4Z

2

1

C112

2

0.47U_0603_16V4Z

CHB1608U301_0603

1 2

R139

10_0402_5%1@

+

2

1

2

C113

1 2

C158

D D

C93

C C

C103

1

2

B B

+1.5VS

A A

+VCCP

VTT0

J13

VTT1

K12

VTT2

W11

VTT3

V11

VTT4

U11

VTT5

T11

VTT6

R11

VTT7

P11
N11
M11

L11

K11

W10

V10
U10
T10
R10
P10
N10
M10
K10

J10
W9

M9

M8
M7
M6

M5
M4
M3
M2

M1
G1

1

C114

2

0.22U_0402_10V4Z

L14

1@

POWER

VTT8
VTT9
VTT10
VTT11
VTT12
VTT13
VTT14
VTT15
VTT16
VTT17
VTT18
VTT19
VTT20
VTT21
VTT22

Y9

VTT23
VTT24

U9

VTT25

R9

VTT26

P9

VTT27

N9

VTT28
VTT29

L9

VTT30

J9

VTT31

N8

VTT32
VTT33

N7

VTT34
VTT35

N6

VTT36
VTT37

A6

VTT38

N5

VTT39
VTT40

N4

VTT41
VTT42

N3

VTT43
VTT44

N2

VTT45
VTT46

B2

VTT47

V1

VTT48

N1

VTT49
VTT50
VTT51

0.22U_0402_10V4Z

ALVISO_BGA1257

+1.5VS_DPLLA

1

1

+

C126

C128

2

2

470U_D_2.5VM

0.1U_0402_16V4Z

Note : C126, C129 No stuff for Ext. VGA.
Stuff for Int. VGA.

+2.5VS

D1

12

LL4148_SOD80

1@

VCCSM0
VCCSM1
VCCSM2
VCCSM3
VCCSM4
VCCSM5
VCCSM6
VCCSM7
VCCSM8

VCCSM9
VCCSM10
VCCSM11
VCCSM12
VCCSM13
VCCSM14
VCCSM15
VCCSM16
VCCSM17
VCCSM18
VCCSM19
VCCSM20
VCCSM21
VCCSM22
VCCSM23
VCCSM24
VCCSM25
VCCSM26
VCCSM27
VCCSM28
VCCSM29
VCCSM30
VCCSM31
VCCSM32
VCCSM33
VCCSM34
VCCSM35
VCCSM36
VCCSM37
VCCSM38
VCCSM39
VCCSM40
VCCSM41
VCCSM42
VCCSM43
VCCSM44
VCCSM45
VCCSM46
VCCSM47
VCCSM48
VCCSM49
VCCSM50
VCCSM51
VCCSM52
VCCSM53
VCCSM54
VCCSM55
VCCSM56
VCCSM57
VCCSM58
VCCSM59
VCCSM60
VCCSM61
VCCSM62
VCCSM63
VCCSM64

Note : All VCCSM pin
shorted internally.

CHB1608U301_0603

+1.5VS

1 2

1 2

R140

10_0402_5%1@

+1.5VS

AM37
AH37
AP29
AD28
AD27
AC27
AP26
AN26
AM26
AL26
AK26
AJ26
AH26
AG26
AF26
AE26
AP25
AN25
AM25
AL25
AK25
AJ25
AH25
AG25
AF25
AE25
AE24
AE23
AE22
AE21
AE20
AE19
AE18
AE17
AE16
AE15
AE14
AP13
AN13
AM13
AL13
AK13
AJ13
AH13
AG13
AF13
AE13
AP12
AN12
AM12
AL12
AK12
AJ12
AH12
AG12
AF12
AE12
AD11
AC11
AB11
AB10
AB9
AP8
AM1
AE1

L16

V1.8_DDR_CAP1
V1.8_DDR_CAP2
V1.8_DDR_CAP5

V1.8_DDR_CAP6
V1.8_DDR_CAP4
V1.8_DDR_CAP3

C129

1@

470U_D_2.5VM

1

C111

C110

2

10U_0805_10V4Z

+1.5VS_DPLLB

1

+

C134

2

0.1U_0402_16V4Z

D2

12

LL4148_SOD80

1@

1

2

10U_0805_10V4Z

1

2

CRT DAC Voltge Follower Circuit - 700mV TV DAC Voltge Follower Circuit - 700mV

5

C75

0.1U_0402_16V4Z

1

C109

2

1

C121

2

+1.5VS

+3VS

4

1

1

C76

2

2

0.1U_0402_16V4Z

1

C86

C87

2

0.1U_0402_16V4Z

1

C95

C96

2

10U_0805_10V4Z

+1.8V

1

+

330U_D_4VM

2

1

C122

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

CHB1608U301_0603

1 2

4

C77

0.1U_0402_16V4Z

1

C88

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

C97

2

10U_0805_10V4Z

10U_0805_10V4Z

+1.5VS

+1.5VS_DPLLA
+1.5VS_DPLLB

+1.5VS_HPLL
+1.5VS_MPLL

1

C123

2

0.1U_0402_16V4Z

L17

3

W=30 mils

U2E

+VCCP

1

2

1

2

C130

470U_D_2.5VM

0.1U_0402_16V4Z

1

C152

2

+1.5VS_HPLL

1

+

C135

2

T29
R29
N29
M29
K29

J29
V28
U28
T28
R28
P28
N28
M28

L28
K28

J28
H28
G28
V27
U27
T27
R27
P27
N27
M27

L27
K27

J27
H27
K26
H26
K25

J25
K24
K23
K22
K21

W20

U20
T20
K20
V19
U19
K19

W18

V18
T18
K18
K17

AC1
AC2
B23
C35
AA1
AA2

0.1U_0402_16V4Z

1

C141

2

+1.5VS

1

2

0.1U_0402_16V4Z

VCC0
VCC1
VCC2
VCC3
VCC4
VCC5
VCC6
VCC7

POWER

VCC8
VCC9
VCC10
VCC11
VCC12
VCC13
VCC14
VCC15
VCC16
VCC17
VCC18
VCC19
VCC20
VCC21
VCC22
VCC23
VCC24
VCC25
VCC26
VCC27
VCC28
VCC29
VCC30
VCC31
VCC32
VCC33
VCC34
VCC35
VCC36
VCC37
VCC38
VCC39
VCC40
VCC41
VCC42
VCC43
VCC44
VCC45
VCC46
VCC47
VCC48

VCCD_HMPLL1
VCCD_HMPLL2
VCCA_DPLLA
VCCA_DPLLB
VCCA_HPLL
VCCA_MPLL

ALVISO_BGA1257

0.1U_0402_16V4Z

1

1

C149

C150

2

2

CHB1608U301_0603

1 2

VCCA_TVDACA0
VCCA_TVDACA1
VCCA_TVDACB0
VCCA_TVDACB1
VCCA_TVDACC0
VCCA_TVDACC1

VCCA_CRTDAC0
VCCA_CRTDAC1

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

C151

2

L15

+2.5VS_CRT

VCC_SYNC

VCCA_TVBG
VSSA_TVBG

VCCD_TVDAC

VCCDQ_TVDAC

VCCD_LVDS0
VCCD_LVDS1
VCCD_LVDS2

VCCA_LVDS

VCCTX_LVDS0
VCCTX_LVDS1
VCCTX_LVDS2

VCCA_SM0
VCCA_SM1
VCCA_SM2
VCCA_SM3

VCCA_3GPLL0
VCCA_3GPLL1
VCCA_3GPLL2

VCCA_3GBG
VSSA_3GBG

VCC_SYNC

VSSA_CRTDAC

+1.8V

C153

C127

470U_D_2.5VM

VCCHV0
VCCHV1
VCCHV2

VCC3G0
VCC3G1
VCC3G2
VCC3G3
VCC3G4
VCC3G5
VCC3G6

0.1U_0402_16V4Z

1

2

+1.5VS_MPLL

1

+

C131

2

F17

+3VS_TVDACA

E17
D18

+3VS_TVDACB

C18
F18

+3VS_TVDACC

E18

+3VS_ATVBG

H18

VSSA_TVBG

G18
D19

+1.5VS_TVDAC

H17

+1.5VS_QTVDAC

B26

+1.5VS_DLVDS

B25
A25

A35
B22

B21
A21

B28
A28
A27

AF20
AP19
AF19
AF18

AE37
W37
U37
R37
N37
L37
J37

Y29
Y28
Y27

F37
G37

H20
F19

E19
G19

1

2

0.1U_0402_16V4Z

R137

2@

0_0402_5%

1 2

R138

2@

0_0402_5%

1 2

+2.5VS_ALVDS

+2.5VS

+2.5VS_TXLVDS

C99

0.1U_0402_16V4Z

VCC_SYNC

+2.5VS_CRT

0.022U_0402_16V7K

CRTDAC: Route caps within
250mil of Alviso. Route FB
within 3" of Alviso.

+2.5VS_TXLVDS

1

C132

C133

2

4.7U_0805_10V4Z

+VCCP

+VCCP

1

2

1

2

0.1U_0402_16V4Z

Note : R137, R138 st uff for E xt. V GA.
R137, R138 no stuff for Int. VGA.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

1

C82

2

0.022U_0402_16V7K

+1.5VS_DDRDLL

1

+

C98

2

100U_C_4VM

1 2

1@

1

C117

C118

2

R136

0_0402_5%

1

2

Route VSSA_TVBG GND
from GMCH to decoupling
cap ground lead and then
connect to the GND plane.

R5160_0603_5%1@

1 2

0_0603_5%

0.1U_0402_16V4Z

2

L5

1 2

0_0603_5%

1

C83

2

0.1U_0402_16V4Z

+1.5VS_PCIE +1.5VS

1

+

C101

C104

2

220U_D_4VM

10U_0805_10V4Z

L12

C119

22U_1206_6.3V6M

+2.5VS

12

+1.5VS+1.5VS_QTVDAC

1

1

C84

C85

2

0.1U_0402_16V4Z

0.022U_0402_16V7K

1

1

C105

2

2

10U_0805_10V4Z

1

1

C120

2

2

0.1U_0402_16V4Z

Route VSSACRTDAC gnd from GMCH to
decoupling cap ground lead and then
connect to the gnd plane.

C136

0.022U_0402_16V7K

2

C78

2

0.022U_0402_16V7K

+3VS_TVDACB +3VS

C89

0.022U_0402_16V7K

+1.5VS_3GPLL

1

C106

2

0.1U_0402_16V4Z

+2.5VS

+1.5VS_TVDAC +1.5VS

1

1

C137

2

2

0.1U_0402_16V4Z

1 2

0_0603_5%

1

1

C79

2

2

0.1U_0402_16V4Z

1 2

1

2

C107

1 2

0_0603_5%

0_0603_5%

1

C90

2

0.1U_0402_16V4Z

R135

0.5_0805_1%

1 2

1

2

10U_0805_10V4Z

Route VSSA3GBG gnd from GMCH to
decoupling cap ground lead and
then connect to the gnd plane.

L18

Title

Size Document Number Rev

Date: Sheet

+3VS+3VS_TVDACA

L3

L6

CHB1608U301_0603

CHB1608U301_0805

1 2

CHB1608U301_0603

3GRLL_R

CHB1608U301_0603

1 2

1

C115

0.1U_0402_16V4Z

2

VSSA_TVBG

L8

1 2

L9

L10

1 2

L11

+2.5VS_ALVDS

1

C80

2

0.022U_0402_16V7K

1

C91

2

0.022U_0402_16V7K

+1.5VS

1

C108

2

0.1U_0402_16V4Z

+2.5VS+2.5VS_3GBG

1

C124

C125

2

0.1U_0402_16V4Z

0.01U_0402_16V7K

+1.5VS_DLVDS +1.5VS

1

C138

C139

2

10U_0805_10V4Z

Compal Electronics, Inc.

Alviso(4 of 5)

HDL75 LA3041

1

1

C81

2

0.1U_0402_16V4Z

1

C92

2

22U_1206_6.3V6M

C102

0.1U_0402_16V4Z

1

C116

0.1U_0402_16V4Z

2

1 2

0_0603_5%

1

2

1 2

0_0603_5%

1

2

0.01U_0402_16V7K

1

L4

1 2

0_0603_5%

L7

1 2

0_0603_5%

C100

1

2

L13

L19

12 60Thursday, July 28, 2005

+3VS+3VS_TVDACC

+3VS+3VS_ATVBG

+1.5VS

1

2

0.1U_0402_16V4Z

+2.5VS

of

0.1

5

AB12
AC12
AD12
AB13
AC13
AD13
AC14
AD14
AC15
AD15
AC16
AD16
AC17
AD17
AC18
AD18
AC19
AD19
AC20
AD20
AC21
AD21
AC22
AD22
AC23
AD23
AC24
AD24
AC25
AD25
AC26
AD26

L17
M17
N17
P17
T17
U17
V17
W17
L18
M18
N18
P18
R18
Y18
L19
M19
N19
P19
R19
Y19
L20
M20
N20
P20
R20
Y20
L21
M21
N21
P21
T21
U21
V21
W21
L22
M22
N22
P22
R22
T22
U22
V22
W22
L23
M23
N23
P23
R23
T23
U23
V23
W23
L24
M24
N24
P24
R24
T24
U24
V24
W24
L25
M25
N25
P25
R25
T25
U25

+1.8V

+VCCP

+VCCP

D D

C C

B B

A A

U2H

L12
M12
N12
P12
R12
T12
U12
V12

W12

L13
M13
N13
P13
R13
T13
U13
V13

W13

Y12

AA12

Y13

AA13

L14
M14
N14
P14
R14
T14
U14
V14

W14

Y14

AA14
AB14

L15
M15
N15
P15
R15
T15
U15
V15

W15

Y15

AA15
AB15

L16
M16
N16
P16
R16
T16
U16
V16

W16

Y16

AA16
AB16

R17
Y17

AA17
AB17
AA18
AB18
AA19
AB19
AA20
AB20

R21
Y21

AA21
AB21

Y22

AA22
AB22

Y23

AA23
AB23

Y24

AA24
AB24

Y25

AA25
AB25

Y26

AA26
AB26

V25

W25

L26
M26
N26
P26
R26
T26
U26
V26

W26

ALVISO_BGA1257

VTT_NCTF17
VTT_NCTF16
VTT_NCTF15
VTT_NCTF14
VTT_NCTF13
VTT_NCTF12
VTT_NCTF11
VTT_NCTF10
VTT_NCTF9
VTT_NCTF8
VTT_NCTF7
VTT_NCTF6
VTT_NCTF5
VTT_NCTF4
VTT_NCTF3
VTT_NCTF2
VTT_NCTF1
VTT_NCTF0

VSS_NCTF68
VSS_NCTF67
VSS_NCTF66
VSS_NCTF65
VSS_NCTF64
VSS_NCTF63
VSS_NCTF62
VSS_NCTF61
VSS_NCTF60
VSS_NCTF59
VSS_NCTF58
VSS_NCTF57
VSS_NCTF56
VSS_NCTF55
VSS_NCTF54
VSS_NCTF53
VSS_NCTF52
VSS_NCTF51
VSS_NCTF50
VSS_NCTF49
VSS_NCTF48
VSS_NCTF47
VSS_NCTF46
VSS_NCTF45
VSS_NCTF44
VSS_NCTF43
VSS_NCTF42
VSS_NCTF41
VSS_NCTF40
VSS_NCTF39
VSS_NCTF38
VSS_NCTF37
VSS_NCTF36
VSS_NCTF35
VSS_NCTF34
VSS_NCTF33
VSS_NCTF32
VSS_NCTF31
VSS_NCTF30
VSS_NCTF29
VSS_NCTF28
VSS_NCTF27
VSS_NCTF26
VSS_NCTF25
VSS_NCTF24
VSS_NCTF23
VSS_NCTF22
VSS_NCTF21
VSS_NCTF20
VSS_NCTF19
VSS_NCTF18
VSS_NCTF17
VSS_NCTF16
VSS_NCTF15
VSS_NCTF14
VSS_NCTF13
VSS_NCTF12
VSS_NCTF11
VSS_NCTF10
VSS_NCTF9
VSS_NCTF8
VSS_NCTF7
VSS_NCTF6
VSS_NCTF5
VSS_NCTF4
VSS_NCTF3
VSS_NCTF2
VSS_NCTF1
VSS_NCTF0

VCC_NCTF10
VCC_NCTF9
VCC_NCTF8
VCC_NCTF7
VCC_NCTF6
VCC_NCTF5
VCC_NCTF4
VCC_NCTF3
VCC_NCTF2
VCC_NCTF1
VCC_NCTF0

5

VCCSM_NCTF31
VCCSM_NCTF30
VCCSM_NCTF29
VCCSM_NCTF28
VCCSM_NCTF27
VCCSM_NCTF26
VCCSM_NCTF25
VCCSM_NCTF24
VCCSM_NCTF23
VCCSM_NCTF22
VCCSM_NCTF21
VCCSM_NCTF20
VCCSM_NCTF19
VCCSM_NCTF18
VCCSM_NCTF17
VCCSM_NCTF16
VCCSM_NCTF15
VCCSM_NCTF14
VCCSM_NCTF13
VCCSM_NCTF12
VCCSM_NCTF11
VCCSM_NCTF10

VCCSM_NCTF9
VCCSM_NCTF8
VCCSM_NCTF7
VCCSM_NCTF6
VCCSM_NCTF5
VCCSM_NCTF4
VCCSM_NCTF3
VCCSM_NCTF2
VCCSM_NCTF1
VCCSM_NCTF0

VCC_NCTF78
VCC_NCTF77
VCC_NCTF76
VCC_NCTF75
VCC_NCTF74
VCC_NCTF73
VCC_NCTF72
VCC_NCTF71
VCC_NCTF70

NCTF

VCC_NCTF69
VCC_NCTF68
VCC_NCTF67
VCC_NCTF66
VCC_NCTF65
VCC_NCTF64
VCC_NCTF63
VCC_NCTF62
VCC_NCTF61
VCC_NCTF60
VCC_NCTF59
VCC_NCTF58
VCC_NCTF57
VCC_NCTF56
VCC_NCTF55
VCC_NCTF54
VCC_NCTF53
VCC_NCTF52
VCC_NCTF51
VCC_NCTF50
VCC_NCTF49
VCC_NCTF48
VCC_NCTF47
VCC_NCTF46
VCC_NCTF45
VCC_NCTF44
VCC_NCTF43
VCC_NCTF42
VCC_NCTF41
VCC_NCTF40
VCC_NCTF39
VCC_NCTF38
VCC_NCTF37
VCC_NCTF36
VCC_NCTF35
VCC_NCTF34
VCC_NCTF33
VCC_NCTF32
VCC_NCTF31
VCC_NCTF30
VCC_NCTF29
VCC_NCTF28
VCC_NCTF27
VCC_NCTF26
VCC_NCTF25
VCC_NCTF24
VCC_NCTF23
VCC_NCTF22
VCC_NCTF21
VCC_NCTF20
VCC_NCTF19
VCC_NCTF18
VCC_NCTF17
VCC_NCTF16
VCC_NCTF15
VCC_NCTF14
VCC_NCTF13
VCC_NCTF12
VCC_NCTF11

4

U2I

Y1

VSS271

D2

VSS270

G2

VSS269

J2

VSS268

L2

VSS260

P2

VSS259

T2

VSS258

V2

VSS257

AD2

VSS256

AE2

VSS255

AH2

VSS254

AL2

VSS253

AN2

VSS252

A3

VSS251

C3

VSS250

AA3

VSS249

AB3

VSS248

AC3

VSS247

AJ3

VSS246

C4

VSS245

H4

VSS244

L4

VSS243

P4

VSS242

U4

VSS241

Y4

VSS240

AF4

VSS239

AN4

VSS238

E5

VSS237

W5

VSS236

AL5

VSS235

AP5

VSS234

B6

VSS233

J6

VSS232

L6

VSS231

P6

VSS230

T6

VSS229

AA6

VSS228

AC6

VSS227

AE6

VSS226

AJ6

VSS225

G7

VSS224

V7

VSS223

AA7

VSS222

AG7

VSS221

AK7

VSS220

AN7

VSS219

C8

VSS218

E8

VSS217

L8

VSS216

P8

VSS215

Y8

VSS214

AL8

VSS213

A9

VSS212

H9

VSS211

K9

VSS210

T9

VSS209

V9

VSS208

AA9

VSS207

AC9

VSS206

AE9

VSS205

AH9

VSS204

AN9

VSS203

D10

VSS202

L10

VSS201

Y10

VSS200

AA10

VSS199

F11

VSS198

H11

VSS197

Y11

VSS196

ALVISO_BGA1257

4

VSS

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

VSSALVDS

VSS195
VSS194
VSS193
VSS192
VSS191
VSS190
VSS189
VSS188
VSS187
VSS186
VSS185
VSS184
VSS183
VSS182
VSS181
VSS180
VSS179
VSS178
VSS177
VSS176
VSS175
VSS174
VSS173
VSS172
VSS171
VSS170
VSS169
VSS168
VSS167
VSS166
VSS165
VSS164
VSS163
VSS162
VSS161
VSS160
VSS159
VSS158
VSS157
VSS156
VSS155
VSS154
VSS153
VSS152
VSS151
VSS150
VSS149
VSS148
VSS147
VSS146
VSS145
VSS144
VSS143
VSS142
VSS141
VSS140
VSS139
VSS138
VSS137
VSS136
VSS135
VSS134
VSS133
VSS132
VSS131
VSS130

3

B36
AA11

AF11
AG11
AJ11
AL11
AN11
B12
D12
J12
A14
B14
F14
J14
K14
AG14
AJ14
AL14
AN14
C15
K15
A16
D16
H16
K16
AL16
C17
G17
AF17
AJ17
AN17
A18
B18
U18
AL18
C19
H19
J19
T19
W19
AG19
AN19
A20
D20
E20
F20
G20
V20
AK20
C21
F21
AF21
AN21
A22
D22
E22
J22
AH22
AL22
H23
AF23
B24
D24
F24
J24
AG24
AJ24

2

U2J

AL24

AN24

A26
E26
G26

J26
B27
E27
G27

W27
AA27
AB27

AF27

AG27

AJ27
AL27

AN27

E28

W28
AA28
AB28
AC28

A29
D29
E29

F29
G29
H29

L29
P29
U29
V29

W29
AA29
AD29
AG29

AJ29

AM29

C30

Y30
AA30
AB30
AC30
AE30
AP30

D31

E31

F31
G31
H31

J31
K31

L31
M31
N31
P31
R31

T31
U31
V31

W31
AD31
AG31

AL31

A32
C32

Y32
AA32
AB32

ALVISO_BGA1257

2

VSS267
VSS266
VSS265
VSS264
VSS263
VSS262
VSS261
VSS129
VSS128
VSS127
VSS126
VSS125
VSS124
VSS123
VSS122
VSS121
VSS120
VSS119
VSS118
VSS117
VSS116
VSS115
VSS114
VSS113
VSS112
VSS111
VSS110
VSS109
VSS108
VSS107
VSS106
VSS105
VSS104
VSS103
VSS102
VSS101
VSS100
VSS99
VSS98
VSS97
VSS96
VSS95
VSS94
VSS93
VSS92
VSS91
VSS90
VSS89
VSS88
VSS87
VSS86
VSS85
VSS84
VSS83
VSS82
VSS81
VSS80
VSS79
VSS78
VSS77
VSS76
VSS75
VSS74
VSS73
VSS72
VSS71
VSS70
VSS69
VSS68

1

AC32

VSS67

AD32

VSS66

AJ32

VSS65

AN32

VSS64

D33

VSS63

E33

VSS62

F33

VSS61

G33

VSS60

H33

VSS59

J33

VSS58

K33

VSS

Title

Size Document Number Rev

Date: Sheet of

VSS57

L33

VSS56

M33

VSS55

N33

VSS54

P33

VSS53

R33

VSS52

T33

VSS51

U33

VSS50

V33

VSS49

W33

VSS48

AD33

VSS47

AF33

VSS46

AL33

VSS45

C34

VSS44

AA34

VSS43

AB34

VSS42

AC34

VSS41

AD34

VSS40

AH34

VSS39

AN34

VSS38

B35

VSS37

D35

VSS36

E35

VSS35

F35

VSS34

G35

VSS33

H35

VSS32

J35

VSS31

K35

VSS30

L35

VSS29

M35

VSS28

N35

VSS27

P35

VSS26

R35

VSS25

T35

VSS24

U35

VSS23

V35

VSS22

W35

VSS21

Y35

VSS20

AE35

VSS19

C36

VSS18

AA36

VSS17

AB36

VSS16

AC36

VSS15

AD36

VSS14

AE36

VSS13

AF36

VSS12

AJ36

VSS11

AL36

VSS10

AN36

VSS9

E37

VSS8

H37

VSS7

K37

VSS6

M37

VSS5

P37

VSS4

T37

VSS3

V37

VSS2

Y37

VSS1

AG37

VSS0

Compal Electronics, Inc.

Alviso(5 of 5)

HDL75 LA3041

13 60Thursday, July 28, 2005

1

0.1

5

DDR_A_D0
DDR_A_D1

DDR_A_DQS#0
DDR_A_DQS0

DDR_A_D2

D D

C C

DDR_CKE0_DIMMA<9>

DDR_A_BS#2<10>

DDR_A_BS#0<10>
DDR_A_WE#<10>

DDR_A_CAS#<10>

DDR_CS1_DIMMA#<9>

M_ODT1<9>

B B

A A

CLK_SDATA<15,16>
CLK_SCLK<15,16>

DDR_A_D3
DDR_A_D8

DDR_A_D9
DDR_A_DQS#1

DDR_A_DQS1
DDR_A_D10

DDR_A_D11

DDR_A_D16
DDR_A_D17

DDR_A_DQS#2
DDR_A_DQS2

DDR_A_D18
DDR_A_D19

DDR_A_D24
DDR_A_D25

DDR_A_DM3

DDR_A_D26
DDR_A_D27

DDR_CKE0_DIMMA

DDR_A_BS#2

DDR_A_MA12
DDR_A_MA9
DDR_A_MA8

DDR_A_MA5
DDR_A_MA3
DDR_A_MA1

DDR_A_MA10
DDR_A_BS#0
DDR_A_WE#

DDR_A_CAS#
DDR_CS1_DIMMA#

M_ODT1
DDR_A_D32

DDR_A_D33
DDR_A_DQS#4

DDR_A_DQS4
DDR_A_D34

DDR_A_D35
DDR_A_D40

DDR_A_D41
DDR_A_DM5
DDR_A_D42

DDR_A_D43
DDR_A_D48

DDR_A_D49

DDR_A_DQS#6
DDR_A_DQS6

DDR_A_D50
DDR_A_D51

DDR_A_D56
DDR_A_D57

DDR_A_DM7
DDR_A_D58

DDR_A_D59
CLK_SDATA

CLK_SCLK

+3VS

C871

0.1U_0402_16V4Z

+1.8V

JDIM1

1

VREF

3

VSS

5

DQ0

7

DQ1

9

VSS

11

DQS0#

13

DQS0

15

VSS

17

DQ2

19

DQ3

21

VSS

23

DQ8

25

DQ9

27

VSS

29

DQS1#

31

DQS1

33

VSS

35

DQ10

37

DQ11

39

VSS

41

VSS

43

DQ16

45

DQ17

47

VSS

49

DQS2#

51

DQS2

53

VSS

55

DQ18

57

DQ19

59

VSS

61

DQ24

63

DQ25

65

VSS

67

DM3

69

NC

71

VSS

73

DQ26

75

DQ27

77

VSS

79

CKE0

81

VDD

83

NC

85

BA2

87

VDD

89

A12

91

A9

93

A8

95

VDD

97

A5

99

A3

101

A1

103

VDD

105

A10/AP

107

BA0

109

WE#

111

VDD

113

CAS#

115

NC/S1#

117

VDD

119

NC/ODT1

121

VSS

123

DQ32

125

DQ33

127

VSS

129

DQS4#

131

DQS4

133

VSS

135

DQ34

137

DQ35

139

VSS

141

DQ40

143

DQ41

145

VSS

147

DM5

149

VSS

151

DQ42

153

DQ43

155

VSS

157

DQ48

159

DQ49

161

VSS

163

NC,TEST

165

VSS

167

DQS6#

169

DQS6

171

VSS

173

DQ50

175

DQ51

177

VSS

179

DQ56

181

DQ57

183

VSS

185

DM7

187

VSS

189

DQ58

191

DQ59

193

VSS

195

SDA

197

SCL

199

1

2

VDDSPD

QTC_C111A-040RP31

DIMMA

VSS
DQ4
DQ5
VSS
DM0
VSS
DQ6
DQ7

VSS
DQ12
DQ13

VSS

DM1

VSS

CK0
CK0#

VSS
DQ14
DQ15

VSS

VSS
DQ20
DQ21

VSS

DM2

VSS
DQ22
DQ23

VSS
DQ28
DQ29

VSS

DQS3#

DQS3

VSS
DQ30
DQ31

VSS

NC/CKE1

VDD

NC/A15
NC/A14

VDD

A11

VDD

VDD

BA1

RAS#

S0#

VDD

ODT0

NC/A13

VDD

VSS
DQ36
DQ37

VSS

DM4

VSS
DQ38
DQ39

VSS
DQ44
DQ45

VSS

DQS5#

DQS5

VSS
DQ46
DQ47

VSS
DQ52
DQ53

VSS

CK1
CK1#

VSS

DM6

VSS
DQ54
DQ55

VSS
DQ60
DQ61

VSS

DQS7#

DQS7

VSS
DQ62
DQ63

VSS

SAO

SA1

NC

A7
A6

A4
A2
A0

NC

REVERSE

5

4

+1.8V

V_DDR_MCH_REF

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200

DDR_A_D4
DDR_A_D5

DDR_A_DM0

DDR_A_D6
DDR_A_D7

DDR_A_D12
DDR_A_D13

DDR_A_DM1
M_CLK_DDR0

M_CLK_DDR#0
DDR_A_D14

DDR_A_D15

DDR_A_D20
DDR_A_D21

DDR_A_DM2
DDR_A_D22

DDR_A_D23
DDR_A_D28

DDR_A_D29
DDR_A_DQS#3

DDR_A_DQS3
DDR_A_D30

DDR_A_D31
DDR_CKE1_DIMMA

DDR_A_MA11
DDR_A_MA7
DDR_A_MA6

DDR_A_MA4
DDR_A_MA2
DDR_A_MA0

DDR_A_BS#1
DDR_A_RAS#
DDR_CS0_DIMMA#

M_ODT0
DDR_A_MA13

DDR_A_D36
DDR_A_D37

DDR_A_DM4
DDR_A_D38

DDR_A_D39
DDR_A_D44

DDR_A_D45
DDR_A_DQS#5

DDR_A_DQS5
DDR_A_D46

DDR_A_D47
DDR_A_D52

DDR_A_D53
M_CLK_DDR1

M_CLK_DDR#1
DDR_A_DM6
DDR_A_D54

DDR_A_D55
DDR_A_D60

DDR_A_D61
DDR_A_DQS#7

DDR_A_DQS7
DDR_A_D62

DDR_A_D63

R756 10K_0402_5%

1 2

R757 10K_0402_5%

1 2

4

2.2U_0805_16V4Z

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

0.1U_0402_16V4Z

1

2

M_CLK_DDR0 <9>

M_CLK_DDR#0 <9>

DDR_CKE1_DIMMA <9>

DDR_A_BS#1 <10>

DDR_A_RAS# <10>

DDR_CS0_DIMMA# <9>

M_ODT0 <9>

M_CLK_DDR1 <9>

M_CLK_DDR#1 <9>

1

C847

2

C848

3

V_DDR_MCH_REF <15>

DDR_A_MA10
DDR_A_BS#0

DDR_CS1_DIMMA#

M_ODT1

DDR_A_RAS#
DDR_CS0_DIMMA#
M_ODT0
DDR_A_MA13

DDR_A_WE#

R803

DDR_A_CAS#

R804

3

DDR_A_DQS#[0..7]<10>

DDR_A_D[0..63]<10>

DDR_A_DM[0..7]<10>

DDR_A_DQS[0..7]<10>

DDR_A_MA[0..13]<10>

+0.9VS

RP35

18
27
36
45

56_0804_8P4R_5%

RP37

18
27
36
45

56_0804_8P4R_5%

56_0402_5%

1 2
1 2

56_0402_5%

RP36

1 8
2 7
3 6
4 5

56_0804_8P4R_5%

RP38

1 8
2 7
3 6
4 5

56_0804_8P4R_5%

RP40

1 8
2 7
3 6
4 5

56_0804_8P4R_5%

RP41

1 8
2 7
3 6
4 5

56_0804_8P4R_5%

DDR_CKE0_DIMMA
DDR_A_BS#2
DDR_A_MA12
DDR_A_MA9

DDR_CKE1_DIMMA
DDR_A_MA11
DDR_A_MA7
DDR_A_MA6

DDR_A_MA4
DDR_A_MA2
DDR_A_MA0

DDR_A_BS#1

DDR_A_MA8
DDR_A_MA5
DDR_A_MA3
DDR_A_MA1

+0.9VS

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

2

C858

2

Layout Note:
Place near JDIM1

+1.8V

2.2U_0805_16V4Z

2.2U_0805_16V4Z
C849

1

2

0.1U_0402_16V4Z

Layout Note:
Place these resistor
closely DIMM0,all
trace length<750 mil

Layout Note:
Place these resistor
closely DIMM0,all
trace length
Max=1.3"

Layout Note:
Place one cap close to every 2 pullup
resistors terminated to +0.9VS

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

2

C859

2

1

1

2

2

C860

2

C861

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

2

C863

C862

Title

Size Document Number Rev

Date: Sheet

2.2U_0805_16V4Z

C850

1

2

0.1U_0402_16V4Z
C855

C854

1

1

2

2

0.1U_0402_16V4Z

1

1

2

2

C865

C864

Compal Electronics, Inc.

DDRII-SODIMM SLOT1

1

2.2U_0805_16V4Z

2.2U_0805_16V4Z
C852

C851

1

1

2

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z
C857

C856

1

1

2

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

2

2

C866

C867

HDL75 LA3041

1

C853

1

2

1

2

C868

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

2

C869

14 60Thursday, July 28, 2005

of

1

2

C870

0.1

5

DDR_B_D0
DDR_B_D1

DDR_B_DQS#0
DDR_B_DQS0

DDR_B_D2

D D

C C

DDR_CKE2_DIMMB<9>

DDR_B_BS#2<10>

DDR_B_BS#0<10>
DDR_B_WE#<10>

DDR_B_CAS#<10>

DDR_CS3_DIMMB#<9>

M_ODT3<9>

B B

A A

CLK_SDATA<14,16>

CLK_SCLK<14,16>

DDR_B_D3
DDR_B_D8

DDR_B_D9
DDR_B_DQS#1

DDR_B_DQS1
DDR_B_D10

DDR_B_D11

DDR_B_D16
DDR_B_D17

DDR_B_DQS#2
DDR_B_DQS2

DDR_B_D18
DDR_B_D19

DDR_B_D24
DDR_B_D25

DDR_B_DM3

DDR_B_D26
DDR_B_D27

DDR_B_MA12
DDR_B_MA9
DDR_B_MA8

DDR_B_MA5
DDR_B_MA3
DDR_B_MA1

DDR_B_MA10

DDR_B_D32
DDR_B_D33

DDR_B_DQS#4
DDR_B_DQS4

DDR_B_D34
DDR_B_D35

DDR_B_D40
DDR_B_D41

DDR_B_DM5
DDR_B_D42

DDR_B_D43
DDR_B_D48

DDR_B_D49

DDR_B_DQS#6
DDR_B_DQS6

DDR_B_D50
DDR_B_D51

DDR_B_D56
DDR_B_D57

DDR_B_DM7
DDR_B_D58

DDR_B_D59
CLK_SDATA

CLK_SCLK

+3VS

C898

0.1U_0402_16V4Z

DDR_CKE2_DIMMB

DDR_B_BS#2

DDR_B_BS#0
DDR_B_WE#

DDR_B_CAS#
DDR_CS3_DIMMB#

M_ODT3

+1.8V +1.8V

JDIM2

1

VREF

3

VSS

5

DQ0

7

DQ1

9

VSS

11

DQS0#

13

DQS0

15

VSS

17

DQ2

19

DQ3

21

VSS

23

DQ8

25

DQ9

27

VSS

29

DQS1#

31

DQS1

33

VSS

35

DQ10

37

DQ11

39

VSS

41

VSS

43

DQ16

45

DQ17

47

VSS

49

DQS2#

51

DQS2

53

VSS

55

DQ18

57

DQ19

59

VSS

61

DQ24

63

DQ25

65

VSS

67

DM3

69

NC

71

VSS

73

DQ26

75

DQ27

77

VSS

79

CKE0

81

VDD

83

NC

85

BA2

87

VDD

89

A12

91

A9

93

A8

95

VDD

97

A5

99

A3

101

A1

103

VDD

105

A10/AP

107

BA0

109

WE#

111

VDD

113

CAS#

115

NC/S1#

117

VDD

119

NC/ODT1

121

VSS

123

DQ32

125

DQ33

127

VSS

129

DQS4#

131

DQS4

133

VSS

135

DQ34

137

DQ35

139

VSS

141

DQ40

143

DQ41

145

VSS

147

DM5

149

VSS

151

DQ42

153

DQ43

155

VSS

157

DQ48

159

DQ49

161

VSS

163

NC,TEST

165

VSS

167

DQS6#

169

DQS6

171

VSS

173

DQ50

175

DQ51

177

VSS

179

DQ56

181

DQ57

183

VSS

185

DM7

187

VSS

189

DQ58

191

DQ59

193

VSS

195

SDA

197

SCL

199

1

2

VDDSPD

QTC_C111A-040SP31

NC/CKE1

DIMMB

VSS
DQ4
DQ5
VSS
DM0
VSS
DQ6
DQ7

VSS
DQ12
DQ13

VSS

DM1

VSS

CK0

CK0#

VSS
DQ14
DQ15

VSS

VSS
DQ20
DQ21

VSS

DM2

VSS
DQ22
DQ23

VSS
DQ28
DQ29

VSS

DQS3#

DQS3

VSS
DQ30
DQ31

VSS

VDD

NC/A15
NC/A14

VDD

VDD

VDD

BA1

RAS#

VDD
ODT0

NC/A13

VDD

VSS
DQ36
DQ37

VSS

DM4

VSS
DQ38
DQ39

VSS
DQ44
DQ45

VSS

DQS5#

DQS5

VSS
DQ46
DQ47

VSS
DQ52
DQ53

VSS

CK1

CK1#

VSS

DM6

VSS
DQ54
DQ55

VSS
DQ60
DQ61

VSS

DQS7#

DQS7

VSS
DQ62
DQ63

VSS

SAO

SA1

A11

S0#

NC

A7
A6

A4
A2
A0

NC

STANDARD

5

4

V_DDR_MCH_REF

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200

DDR_B_D4
DDR_B_D5

DDR_B_DM0
DDR_B_D6

DDR_B_D7
DDR_B_D12

DDR_B_D13
DDR_B_DM1
M_CLK_DDR3

M_CLK_DDR#3
DDR_B_D14

DDR_B_D15

DDR_B_D20
DDR_B_D21

DDR_B_DM2
DDR_B_D22

DDR_B_D23
DDR_B_D28

DDR_B_D29
DDR_B_DQS#3

DDR_B_DQS3
DDR_B_D30

DDR_B_D31
DDR_CKE3_DIMMB

DDR_B_MA11
DDR_B_MA7
DDR_B_MA6

DDR_B_MA4
DDR_B_MA2
DDR_B_MA0

DDR_B_BS#1
DDR_B_RAS#
DDR_CS2_DIMMB#

M_ODT2
DDR_B_MA13

DDR_B_D36
DDR_B_D37

DDR_B_DM4
DDR_B_D38

DDR_B_D39
DDR_B_D44

DDR_B_D45
DDR_B_DQS#5

DDR_B_DQS5
DDR_B_D46

DDR_B_D47
DDR_B_D52

DDR_B_D53
M_CLK_DDR4

M_CLK_DDR#4
DDR_B_DM6
DDR_B_D54

DDR_B_D55
DDR_B_D60

DDR_B_D61
DDR_B_DQS#7

DDR_B_DQS7
DDR_B_D62

DDR_B_D63

4

12

R75910K_0402_5%

2.2U_0805_16V4Z

0.1U_0402_16V4Z

1

C873

1

2

M_CLK_DDR3 <9>

M_CLK_DDR#3 <9>

DDR_CKE3_DIMMB <9>

DDR_B_BS#1 <10>
DDR_B_RAS# <10>
DDR_CS2_DIMMB# <9>

M_ODT2 <9>

M_CLK_DDR4 <9>
M_CLK_DDR#4 <9>

+3VS

12

R758

10K_0402_5%

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C874

2

3

V_DDR_MCH_REF <14>

+0.9VS

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

2

2

C885

C886

3

DDR_B_DQS#[0..7]<10>

DDR_B_D[0..63]<10>

DDR_B_DM[0..7]<10>
DDR_B_DQS[0..7]<10>
DDR_B_MA[0..13]<10>

Layout Note:
Place one cap close to every 2 pullup
resistors terminated to +0.9VS

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

2

C887

DDR_B_MA8
DDR_B_MA5
DDR_B_MA3
DDR_B_MA10

DDR_B_MA2
DDR_B_MA0
DDR_B_BS#1

DDR_B_WE#
DDR_B_CAS#

1

2

C888

R805
R806

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

2

2

C889

RP42

18
27
36
45

56_0804_8P4R_5%

RP44

18
27
36
45

56_0804_8P4R_5%
56_0402_5%

1 2
1 2

56_0402_5%

C890

+0.9VS

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

2

C891

RP43

1 8
2 7
3 6
4 5

56_0804_8P4R_5%

RP45

1 8
2 7
3 6
4 5

56_0804_8P4R_5%

RP47

1 8
2 7
3 6
4 5

56_0804_8P4R_5%

RP48

1 8
2 7
3 6
4 5

56_0804_8P4R_5%

0.1U_0402_16V4Z

1

C893

2

C892

DDR_CKE2_DIMMB
DDR_B_BS#2
DDR_B_MA12
DDR_B_MA9

DDR_CKE3_DIMMBDDR_B_MA4
DDR_B_MA11
DDR_B_MA7
DDR_B_MA6

DDR_B_RAS#
DDR_CS2_DIMMB#
M_ODT2
DDR_B_MA13

DDR_B_MA1
DDR_B_BS#0
DDR_CS3_DIMMB#
M_ODT3

1

2

2

0.1U_0402_16V4Z

2

1

2

C894

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

2

C895

1

Layout Note:
Place near JDIM2

+1.8V

2.2U_0805_16V4Z

2.2U_0805_16V4Z

2.2U_0805_16V4Z

C875

C876

1

1

2

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z
C881

C880

1

1

2

2

+1.8V

0.1U_0402_16V4Z

1

1

2

2

C897

C896

Layout Note:
Place these resistor
closely DIMM0,all
trace length<750 mil

Layout Note:
Place these resistor
closely DIMM0,all
trace length
Max=1.3"

Title

Size Document Number Rev

Date: Sheet

1

C161

@

2

+5VALW

+VCCP +1.5VS

Compal Electronics, Inc.

DDRII-SODIMM SLOT2

HDL75 LA3041

1

2

0.1U_0402_16V4Z
C882

1

2

1

C162

2

@

0.1U_0402_16V4Z

+1.5VS_PCIE

+1.8V

1

C163

@

2

C877

0.1U_0402_16V4Z

0.1U_0402_16V4Z

@

0.1U_0402_16V4Z

+1.5VS_PCIE

1

2.2U_0805_16V4Z
C878

1

2

0.1U_0402_16V4Z

C883

1

2

C166

@

1

C164

2

0.1U_0402_16V4Z

15 60Friday, July 29 , 2005

2.2U_0805_16V4Z

C884

1

2

1

2

0.1U_0402_16V4Z

1

C165

@

2

of

1

2

+CPU_CORE

C879

0.1U_0402_16V4Z

0.1

5

+3VS

1 2

D

1 3

Q1
2N7002_SOT23

G

2

2

G

1 3

D

1 2

R2

S

Q2
2N7002_SOT23

S

R11670_0402_5% @

R11660_0402_5% @

ICH_SMBDATA<28,38>

D D

+3VS

ICH_SMBCLK<28,38>

ICH_SMBCLK

D

1

3

G

S

2

12

2.2K_0402_5%

12

R3

2.2K_0402_5%

CLK_SDATAICH_SMBDATA

CLK_SCLK

1

1

2

2

C10

C11

4.7U_0805_10V4Z

2N7002

FSC FSB FSA CPU

CLKSEL0 CLKSEL2CLKSEL1

000

C C

*

0

0

1

1

1

00

1

0

1

11

00

1

0

1

0

111

B B

CPU_BSEL0<6>

A A

CPU_BSEL1<6>

1 2

R48
0_0402_5%

1 2

R61 0_0402_5%

5

MHz

266

133

200

166

333

100

400

RESERVED

Table :

+VCCP

R44
1K_0402_5%

@

1 2

R51

@

0_0402_5%

1 2

+VCCP

R56
1K_0402_5%

@

1 2

R62

@

0_0402_5%

1 2

SRC
MHz

100

100

100

100

100

100

100

PCI
MHz

33.3

33.3

33.3

33.3

Stuff R73 for Cypress clock gen

33.3

33.3

33.3

R67

0_0402_5%

R46

1K_0402_5%

R1181

1 2

0_0402_5%

1 2

R59
1K_0402_5%

CLK_EXT_SD48<31>
CLK_ICH_48M<28>

CLK_SIO_14M<42>

CLK_PCI_PCM<31>
CLK_PCI_MINI1<37>
CLK_PCI_1394<33>
CLK_PCI_MINI<36>
CLK_PCI_LOM<34>
CLK_PCI_ICH<26>

CLK_PCI_EC<40,42>

CLKSEL0

12

12

CLKSEL1

4

C6

0.1U_0402_16V4Z

CLK_SDATA <14,15>

CLK_SCLK <14,15>

CK_VDD_48CK_VDD_A CK_VDD_REF

0.047U_0402_16V4Z

1 2

33P_0402_50V8J

33P_0402_50V8J

1 2

MCH_CLKSEL0 <9>

MCH_CLKSEL1 <9>

1

1

2

2

C12

C15

C16

C13

4.7U_0805_10V4Z

Place crystal within
500 mils of CK410

1 2

CLK_ICH_48M CLKSEL2

CLKSEL0
CLK_SIO_14M
CLKSEL1

CLK_PCI_PCM PCI_PCM

CLK_PCI_1394

CLK_PCI_LOM
CLK_PCI_ICH PCI_ICH

+3VS

CLK_PCI_EC

4

1 2

L1

CHB2012U121_0805

1

2

0.047U_0402_16V4Z

X1

14.31818MHZ_20P_6X1430004201

1 2

L2

CHB2012U121_0805

1

2

C14

0.047U_0402_16V4Z

CLK_XTAL_IN

CLK_XTAL_OUT

R1026 22_0402_5%

1 2

R1025 22_0402_5%

1 2

12

1 2

R73 475_0603_1%@
R31 10_0402_5%
R1065 10_0402_5%
R32 33_0402_5%
R33 33_0402_5%
R34 33_0402_5%
R36 33_0402_5%

1 2

R38 10K_0402_5%

12

R69 33_0402_5%

+3VS

R53
10K_0402_5%

1 2

CLKSEL2

R55
10K_0402_5%

@

1 2

+CK_VDD_MAIN2

1 2

1 2

R6022_0402_5% @

12
12
12

PCI_MINICLK_PCI_MINI

12
12
12

1 2

R41 475_0603_1%

3

+CK_VDD_MAIN+3VS

R22
1_0603_5%

R24

2.2_0603_5%

PCI_1394

PCI_LOM

PCICLKF0
CLK_SCLK

CLK_SDATA

CLKIREF

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

CK_VDD_REF

CK_VDD_48

3

+CK_VDD_MAIN

2

C1
10U_0805_10V4Z

1

2

C7
10U_0805_10V4Z

1

U1

21

VDDPCIEX_0

28

VDDPCIEX_1

34

VDDPCIEX_2

1

VDDPCI_0

7

VDDPCI_1

42

VDDCPU

48

VDDREF

11

VDD48

50

X1

49

X2

12

FS_A/USB_48MHz

53

REF1/FSLC/TEST_SEL

16

FSLB/TEST_MODE

5

PCICLK5

4

PCICLK4

3

PCICLK3

56

PCICLK2/REQ_SEL

9

SELPCIEX_LCDCLK#/PCICLK_F1

8

ITP_EN/PCICLK_F0

46

SCLK

47

SDATA

39

IREF

13

GND_0

29

GND_1

2

GND_2

45

GND_3

51

GND_4

6

GND_5

ICS954226AGT_TSSOP56

1

C2

0.1U_0402_16V4Z

2

1

C8

0.1U_0402_16V4Z

2

1 2

R14

2.2_0603_5%

1

C3

0.1U_0402_16V4Z

2

1

C9

0.1U_0402_16V4Z

2

CK_VDD_A CLK_PCIE_VGA#

VDDA
GNDA

PCI/SRC_STOP#

CPU_STOP#

CPUCLKT1
CPUCLKC1

CPUCLKT0
CPUCLKC0

CPUCLKT2_ITP/PCIEXT6

CPUCLKC2_ITP/PCIEXC6

PEREQ1#/PCIEXT5
PEREQ2#/PCIEXC5

PCIEXT4
PCIEXC4

SATACLKT
SATACLKC

PCIEXT3
PCIEXC3

PCIEXT2
PCIEXC2

PCIEXT1
PCIEXC1

LCDCLK_SS/PCIEX0T
LCDCLK_SS/PCIEX0C

DOTT_96MHz
DOTC_96MHz

VTT_PWRGD#/PD

REF0

1

C4

0.1U_0402_16V4Z

2

37
38

PM_STP_PCI#

55

PM_STP_CPU#

54

MCH_BCLK

41

MCH_BCLK#

40

CPU_BCLK

44

CPU_BCLK#

43

36

CPU_ITP# CLK_CPU_ITP#

35

PEREQ1#

33

PEREQ2#

32

MCH_3GPLL

31

MCH_3GPLL# CLK_MCH_3GPLL#

30

26

PCIE_VGA#

27

PCIE_ICH CLK_PCIE_ICH

24

PCIE_ICH#

25

22
23

PCIE_CARD CLK_PCIE_CARD

19

PCIE_CARD#

20

PCIE_GM

17

PCIE_GM# DREF_SSCLK#

18

DOT96 DREFCLK

14
15

CLK_ENABLE#

10
52

CLKREF

2

1

C5

0.1U_0402_16V4Z

2

Place near each pin
W>40 mil

Place near CK410

PM_STP_PCI# <28>
PM_STP_CPU# <28,54>

1 2

R1041 10K_0402_5%

13

2

G

CLK_ICH_14M

CLK_MCH_BCLK
CLK_MCH_BCLK#

CLK_CPU_BCLK
CLK_CPU_BCLK#

CLK_CPU_ITPCPU_ITP

CLK_MCH_3GPLL

CLK_PCIE_VGAPCIE_VGA
CLK_PCIE_VGA#

CLK_PCIE_ICH#

CLK_PCIE_CARD#

DREF_SSCLK

DREFCLK#DOT96#

Title

Size Document Number Rev

Date: Sheet

1 2

R23 33_0402_5%

1 2

R25 33_0402_5%

1 2

R26 33_0402_5%

1 2

R27 33_0402_5%

1 2

R29 33_0402_5%@

1 2

R30 33_0402_5%@

R1152 10K_0402_5%@

1 2

R1153 0_0402_5%@

1 2

1 2

R35 33_0402_5%

1 2

R37 33_0402_5%

2@

1 2

R1107 33_0402_5%

1 2

R1108 33_0402_5%2@

1 2

R39 33_0402_5%

1 2

R40 33_0402_5%

1 2

R45 33_0402_5% @

1 2

R47 33_0402_5%@

1@

1 2

R49 33_0402_5%

1@

1 2

R50 33_0402_5%

1 2

R52 33_0402_5%1@

1 2

R54 33_0402_5%1@

D

Q78 2N7002_SOT23

S

1 2

R57 22_0402_5%

1 2

R58 22_0402_5%

2

CLK_CPU_ITP
CLK_CPU_ITP#
CLK_MCH_BCLK
CLK_MCH_BCLK#
CLK_CPU_BCLK
CLK_CPU_BCLK#
CLK_MCH_3GPLL
CLK_MCH_3GPLL#
CLK_PCIE_ICH
CLK_PCIE_ICH#
CLK_PCIE_VGA

DREF_SSCLK
DREF_SSCLK#
DREFCLK
DREFCLK#
CLK_PCIE_CARD
CLK_PCIE_CARD#

CLK_MCH_BCLK <9>
CLK_MCH_BCLK# <9>

CLK_CPU_BCLK <5>
CLK_CPU_BCLK# <5>

CLK_CPU_ITP <5>
CLK_CPU_ITP# <5>

+3VS

PCIECARD_CLKEN <38,40>

CLK_MCH_3GPLL <11>
CLK_MCH_3GPLL# <11>

CLK_PCIE_VGA <17>
CLK_PCIE_VGA# <17>

CLK_PCIE_ICH <28>
CLK_PCIE_ICH# <28>

CLK_PCIE_CARD <38>
CLK_PCIE_CARD# <38>

DREF_SSCLK <9>
DREF_SSCLK# <9>

DREFCLK <9>
DREFCLK# <9>

+3VS

VGATE <9,28,54>

CLK_ICH_14M <28>

CLK_CODEC_14M <43>

Compal Electronics, Inc.

Clock Generator

HDL75 LA3041

1

1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2

16 60Thursday, July 28, 2005

12
12
12
12
12
12

of

R1 49.9_0402_1%@
R4 49.9_0402_1%@
R5 49.9_0402_1%
R6 49.9_0402_1%
R7 49.9_0402_1%
R8 49.9_0402_1%
R9 49.9_0402_1%
R10 49.9_0402_1%
R16 49.9_0402_1%
R17 49.9_0402_1%
R1105 49.9_0402_1%2@
R1106 49.9_0402_1% 2@
R18 49.9_0402_1%1@
R19 49.9_0402_1%1@
R20 49.9_0402_1%1@
R21 49.9_0402_1%1@
R13 49.9_0402_1%@
R15 49.9_0402_1%@

1

0.1

5

PEG_TXN[0..15]<20>
PEG_TXP[0..15]<20>
PEG_RXN[0..15]<20>
PEG_RXP[0..15]<20>

D D

FLASH ROM
(if no problem can be remove)

T25PAD
T26PAD
T27PAD
T28PAD

C C

SIN

SCLK
SOUT

PEG_TXN[0..15]

PEG_TXP[0..15]
PEG_RXN[0..15]
PEG_RXP[0..15]

SCS# <18>

U60 UNMOUNT : VBIOS MUST COMBINE WITH SYSTEM BIOS

CLK_PCIE_VGA<16>
CLK_PCIE_VGA#<16>

B B

A A

R182

1K_0402_5% 2@

+3VS

+3VS

12

5

R171

1 2

R172 10K_0402_5%

1 2

2@

C202 0.1U_0402_16V4Z

PLTRST_ICH#<26>

1 2

2@

X2

4

VDD

1

OE

27MHZ_15P

2@

10K_0402_5%@

OSC_OUT<25>

OUT

GND

PLTRST_VGA#<28>

3
2

+1.2VS

@

1 2

R1116 0_0402_5%

TV_Y<24>
TV_C<24>
TV_CVBS<24>

SMBCLK<25>
SMBDATA<25>

OSC_OUT

1 2

R184

121_0603_1%

75_0603_1%

+3VS

+3VS

2@

12

R186

2@

4

PEG_RXP0
PEG_RXN0
PEG_RXP1
PEG_RXN1
PEG_RXP2
PEG_RXN2
PEG_RXP3
PEG_RXN3
PEG_RXP4
PEG_RXN4
PEG_RXP5
PEG_RXN5
PEG_RXP6
PEG_RXN6
PEG_RXP7
PEG_RXN7
PEG_RXP8
PEG_RXN8
PEG_RXP9
PEG_RXN9
PEG_RXP10
PEG_RXN10
PEG_RXP11
PEG_RXN11
PEG_RXP12
PEG_RXN12
PEG_RXP13
PEG_RXN13
PEG_RXP14
PEG_RXN14
PEG_RXP15
PEG_RXN15

PEG_TXP0
PEG_TXN0
PEG_TXP1
PEG_TXN1
PEG_TXP2
PEG_TXN2
PEG_TXP3
PEG_TXN3
PEG_TXP4
PEG_TXN4
PEG_TXP5
PEG_TXN5
PEG_TXP6
PEG_TXN6
PEG_TXP7
PEG_TXN7
PEG_TXP8
PEG_TXN8
PEG_TXP9
PEG_TXN9
PEG_TXP10
PEG_TXN10
PEG_TXP11
PEG_TXN11
PEG_TXP12
PEG_TXN12
PEG_TXP13
PEG_TXN13
PEG_TXP14
PEG_TXN14
PEG_TXP15
PEG_TXN15

CLK_PCIE_VGA
CLK_PCIE_VGA#

R168 150_0402_1%

2@

1 2

R169 100_0402_1%

2@

1 2

R170 10K_0402_1%

2@

1 2

R1115 0_0402_5%

2@

1 2

2@

1 2

R173 1K_0402_5%

2@

R174 715_0402_1%

TV_Y
TV_C
TV_CVBS

R178 0_0402_5%

R179 0_0402_5%

1 2

R181 1K_0402_5%

R185 10K_0402_5%

12

2@

1 2

R392 4.7K_0402_5%
R762 0_0402_5%@

1 2

@

1 2

R391 0_0402_5%

2@

1 2

R393 4.7K_0402_5%

@

12

2@

12

2@

2@

12

4

3

U5A

AH30

PCIE_RX0P

AG30

PCIE_RX0N

AG29

PCIE_RX1P

AF29

PCIE_RX1N

AE29

PCIE_RX2P

AE30

PCIE_RX2N

AD30

PCIE_RX3P

AD29

PCIE_RX3N

AC29

PCIE_RX4P

AB29

PCIE_RX4N

AB30

PCIE_RX5P

AA30

PCIE_RX5N

AA29

PCIE_RX6P

Y29

PCIE_RX6N

W29

PCIE_RX7P

W30

PCIE_RX7N

V30

PCIE_RX8P

V29

PCIE_RX8N

U29

PCIE_RX9P

T29

PCIE_RX9N

T30

PCIE_RX10P

R30

PCIE_RX10N

R29

PCIE_RX11P

P29

PCIE_RX11N

N29

PCIE_RX12P

N30

PCIE_RX12N

M30

PCIE_RX13P

M29

PCIE_RX13N

L29

PCIE_RX14P

K29

PCIE_RX14N

K30

PCIE_RX15P

J30

PCIE_RX15N

AF26

PCIE_TX0P

AE26

PCIE_TX0N

AC25

PCIE_TX1P

AB25

PCIE_TX1N

AC27

PCIE_TX2P

AB27

PCIE_TX2N

AC26

PCIE_TX3P

AB26

PCIE_TX3N

Y25

PCIE_TX4P

W25

PCIE_TX4N

Y27

PCIE_TX5P

W27

PCIE_TX5N

Y26

PCIE_TX6P

W26

PCIE_TX6N

U25

PCIE_TX7P

T25

PCIE_TX7N

U27

PCIE_TX8P

T27

PCIE_TX8N

U26

PCIE_TX9P

T26

PCIE_TX9N

P25

PCIE_TX10P

N25

PCIE_TX10N

P27

PCIE_TX11P

N27

PCIE_TX11N

P26

PCIE_TX12P

N26

PCIE_TX12N

L25

PCIE_TX13P

K25

PCIE_TX13N

L27

PCIE_TX14P

K27

PCIE_TX14N

L26

PCIE_TX15P

K26

PCIE_TX15N

AF27

PCIE_REFCLKP

AE27

PCIE_REFCLKN

AC23

PCIE_CALRP

AB24

PCIE_CALRN

AB23

PCIE_CALI

AE25

PCIE_TESTIN

AD25

PWRGD

AD24

PWRGD_MASK

AH21

R2SET

AK21

Y_G

AJ22

C_R_PR

AK22

COMP_B_PB

AJ24

H2SYNC

AK24

V2SYNC

AG22

DDC3CLK

AG23

DDC3DATA

AJ23

SSIN

AH24

XTALIN
XTALOUT

SSOUT

AH28

XTALIN

AJ29

XTALOUT

AH27

TESTEN

E8

TEST_YCLK

B6

TEST_MCLK

AF25

PLLTEST

AH25

STEREOSYNC

M24P_BGA708

2@

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Part 1 of 5

GPIO_PWRCNTL

PCI EXPRESS

DAC2CLK

SS

GPIO_MEMSSIN

DVPDATA_0
DVPDATA_1
DVPDATA_2
DVPDATA_3
DVPDATA_4
DVPDATA_5
DVPDATA_6
DVPDATA_7
DVPDATA_8

DVPDATA_9
DVPDATA_10
DVPDATA_11
DVPDATA_12
DVPDATA_13
DVPDATA_14
DPVDATA_15

DVO / EXT TMDS / GPIOTMDSDAC1

DVPDATA_16
DVPDATA_17
DVPDATA_18
DVPDATA_19
DVPDATA_20
DVPDATA_21
DVPDATA_22
DVPDATA_23

DVPCNTL_0

DVPCNTL_1

DVPCNTL_2

DVPCNTL_3

TXOUT_L0N

TXOUT_L0P

TXOUT_L1N

TXOUT_L1P

TXOUT_L2N

TXOUT_L2P

TXOUT_L3N

TXOUT_L3P

TXOUT_U0N

TXOUT_U0P

TXOUT_U1N

TXOUT_U1P

TXOUT_U2N

LVDS

TXOUT_U2P

TXOUT_U3N

TXOUT_U3P

DDC2DATA

DDC1DATA

GPIO_AUXWIN

THERM

3

GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8

GPIO9
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14

DVOMODE

VREFG

TXCLK_LN

TXCLK_LP

TXCLK_UN
TXCLK_UP

DIGON

BLON
TX0M

TX0P

TX1M

TX1P

TX2M

TX2P
TXCM
TXCP

DDC2CLK

HPD1

HSYNC

VSYNC

RSET

DDC1CLK

DPLUS

DMINUS

AJ5
AH5
AJ4
AK4
AH4
AF4
AJ3

R151 0_0402_5%

1 2

AK3
AH3
AJ2
AH2
AH1
AG3
AG1
AG2
AF3
AF2

AE10
AH6

AJ6
AK6
AH7
AK7
AJ7
AH8
AJ8
AH9
AJ9
AK9
AH10
AE6
AG6
AF6
AE7
AF7
AE8
AG8
AF8
AE9
AF9
AG10
AF10

AJ10
AK10
AJ11
AH11

AG4
AH15

AH16
AJ16
AJ17
AJ18
AK18
AJ20
AJ21
AK19
AJ19
AG16
AG17
AF16
AF17
AE18
AE19
AF19
AF20
AG19
AG20

AE12

1 2

AG12

R1114 0_0402_5% 2@

AK13
AJ13
AJ14
AJ15
AK15
AK16
AJ12
AK12

AE13
AE14
AF12

AK27

R

AJ27

G

AJ26

B

AJ25
AK25

AH26
AG25
AF24
AG24

D+

AF11

D-

AE11

2@

R152 10K_0402_5%2@

MEMSEL0
MEMSEL1

1 2

R156 0_0402_5%@

10K_1206_8P4R_5%

4 5
3 6
2 7
1 8

RP28

2@

ENVDD

BACKLITE_ON

1 2

R177 100K_0402_5%2@

2@

1 2

R180 499_0402_1%

D+ <25>
D- <25>

1 2

SOUT
SIN
SCLK

12

2@

1 2

R763 0_0402_5%

R183
10K_0402_5%

0_0402_5%

@

2

GPIO0 <25>
GPIO1 <25>
GPIO2 <25>
GPIO3 <25>
GPIO4 <25>
GPIO5 <25>
GPIO6 <25>
ROM_ID4 <25>

ROM_ID1 <25>
ROM_ID2 <25>
ROM_ID3 <25>

POWER_SEL <53>
OSC_SPREAD <25>

R154 0_0402_5%@

1 2

R155 0_0402_5%2@

1 2

ROM_ID4 <25>

12

12

R157

R158

0_0402_5%

@

LVDSA0- <23>
LVDSA0+ <23>
LVDSA1- <23>
LVDSA1+ <23>
LVDSA2- <23>
LVDSA2+ <23>

LVDSAC- <23>
LVDSAC+ <23>
LVDSB0- <23>
LVDSB0+ <23>
LVDSB1- <23>
LVDSB1+ <23>
LVDSB2- <23>
LVDSB2+ <23>

LVDSBC- <23>
LVDSBC+ <23>

ENVDD <23>
BACKLITE_ON <11,23,40>

2

+3VS

R164 10K_0402_5% 2@

12

R167

2@

1K_0402_5%

VGA_RED <24>
VGA_GRN <24>
VGA_BLU <24>
HSYNC <24>
VSYNC <24>

DAT_DDC2 <24>
CLK_DDC2 <24>
AUXWIN <25>

1

MEM Type Selection

64M Samsung

64M Hynix
NEW 128M

HYNIX
128M Hynix

12

R1020

2.2K_0402_5%

2@

1 2

2@

1 2

R166 1K_0402_5%

+3VS

12

R1021

2.2K_0402_5%

2@

MEMSEL0

LOW

LOW

HI

HI HI

EDID_DAT <23>
EDID_CLK <23>

MEMSEL1

LOW

HI

LOW

+3VS

Note:
Keep toggling signals always from
RSET/RSET2 resistor and trace.
Layout wider in resistor to GND.

CRT I/F

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

ATI M24-P

HDL75 LA3041

17 60Thursday, July 28, 2005

1

of

0.1

5

4

3

2

1

MDA[63:0] <21>

MAA[13:0] <21>

DQSA[7:0] <21>

DQMA#[7:0] <21>

D D

MDA0
MDA1
MDA2
MDA3
MDA4
MDA5
MDA6
MDA7
MDA8
MDA9
MDA10
MDA11
MDA12
MDA13
MDA14
MDA15
MDA16
MDA17
MDA18
MDA19
MDA20
MDA21
MDA22
MDA23
MDA24

C C

B B

A A

MDA25
MDA26
MDA27
MDA28
MDA29
MDA30
MDA31
MDA32
MDA33
MDA34
MDA35
MDA36
MDA37
MDA38
MDA39
MDA40
MDA41
MDA42
MDA43
MDA44
MDA45
MDA46
MDA47
MDA48
MDA49
MDA50
MDA51
MDA52
MDA53
MDA54
MDA55
MDA56
MDA57
MDA58
MDA59
MDA60
MDA61
MDA62
MDA63

U5B

H28
H29

H25
H26
G26
G30
D29
D28
E28
E29
G29
G28
F28
G25
F26
E26
F25
E24
F23
E23
D22
B29
C29
C25
C27
B28
B25
C26
B26
F17
E17
D16
F16
E15
F14
E14
F13
C17
B18
B17
B15
C13
B14
C14
C16
A13
A12
C12
B12
C10

B10
E13
E12
E10
F12
F11

J28
J29
J26

C9
B9

E9
F9
F8

DQA0
DQA1
DQA2
DQA3
DQA4
DQA5
DQA6
DQA7
DQA8
DQA9
DQA10
DQA11
DQA12
DQA13
DQA14
DQA15
DQA16
DQA17
DQA18
DQA19
DQA20
DQA21
DQA22
DQA23
DQA24
DQA25
DQA26
DQA27
DQA28
DQA29
DQA30
DQA31
DQA32
DQA33
DQA34
DQA35
DQA36
DQA37
DQA38
DQA39
DQA40
DQA41
DQA42
DQA43
DQA44
DQA45
DQA46
DQA47
DQA48
DQA49
DQA50
DQA51
DQA52
DQA53
DQA54
DQA55
DQA56
DQA57
DQA58
DQA59
DQA60
DQA61
DQA62
DQA63

M24P_BGA708

2@

M_CSA1#

Part 2 of 5

MEMORY INTERFACE A

2@

1 2

R197 0_0402_5%

MAA0
MAA1
MAA2
MAA3
MAA4
MAA5
MAA6
MAA7
MAA8

MAA9
MAA10
MAA11
MAA12
MAA13
MAA14

DQMA#0
DQMA#1
DQMA#2
DQMA#3
DQMA#4
DQMA#5
DQMA#6
DQMA#7

QSA0

QSA1

QSA2

QSA3

QSA4

QSA5

QSA6

QSA7
RASA#
CASA#

WEA#
CSA0#
CSA1#

CKEA

CLKA0

CLKA0#

CLKA1

CLKA1#

MVREFD
MVREFS

DIMA_0
DIMA_1

Pop for 128MB Pop for 128MB

E22
B22
B23
B24
C23
C22
F22
F21
C21
A24
C24
A25
E21
B20
C19

J25
F29
E25
A27
F15
C15
C11
E11

J27
F30
F24
B27
E16
B16
B11
F10

A19
E18
E19
E20
F20
B19

B21
C20

C18
A18

B7
B8

D30
B13

CSA1# <21>

MAA0
MAA1
MAA2
MAA3
MAA4
MAA5
MAA6
MAA7
MAA8
MAA9
MAA10
MAA11
MAA12
MAA13

DQMA#0
DQMA#1
DQMA#2
DQMA#3
DQMA#4
DQMA#5
DQMA#6
DQMA#7

DQSA0
DQSA1
DQSA2
DQSA3
DQSA4
DQSA5
DQSA6
DQSA7

RASA#
CASA#
WEA#
CSA0#
M_CSA1#
CKEA

CLKA0
CLKA0#

CLKA1
CLKA1#

RASA# <21>
CASA# <21>
WEA# <21>
CSA0# <21>

CLKA0 <21>
CLKA0# <21>

CLKA1 <21>
CLKA1# <21>

0.1U_0402_16V4Z

0.1U_0402_16V4Z

12

2@

R188
10K_0402_5%

10mil

C203

2@

10mil

C204

2@

+VDD_MEM_IO

1

2

+VDD_MEM_IO

1

2

CKEA <21>

12

2@

R189
100_0402_1%

12

2@

R191
100_0402_1%

12

2@

R196
100_0402_1%

12

2@

R199
100_0402_1%

MDB0
MDB1
MDB2
MDB3
MDB4
MDB5
MDB6
MDB7
MDB8
MDB9
MDB10
MDB11
MDB12
MDB13
MDB14
MDB15
MDB16
MDB17
MDB18
MDB19
MDB20
MDB21
MDB22
MDB23
MDB24
MDB25
MDB26
MDB27
MDB28
MDB29
MDB30
MDB31
MDB32
MDB33
MDB34
MDB35
MDB36
MDB37
MDB38
MDB39
MDB40
MDB41
MDB42
MDB43
MDB44
MDB45
MDB46
MDB47
MDB48
MDB49
MDB50
MDB51
MDB52
MDB53
MDB54
MDB55
MDB56
MDB57
MDB58
MDB59
MDB60
MDB61
MDB62
MDB63

AA2
AA6
AA5
AB6
AB5
AD6
AD5
AE5
AE4
AB2
AB3
AC2
AC3
AD3
AE1
AE2
AE3

D7
F7

E7
G6
G5

F5

E5

C4

B5

C5

A4

B4

C2

D3

D1

D2
G4

H6

H5

J6

K5

K4

L6

L5
G2

F3

H2

E2

F2

J3

F1

H3

U6

U5

U3

V6

W5
W4

Y6

Y5

U2

V2

V1

V3

W3

Y2

Y3

M_CSB1#

U5C

DQB0
DQB1
DQB2
DQB3
DQB4
DQB5
DQB6
DQB7
DQB8
DQB9
DQB10
DQB11
DQB12
DQB13
DQB14
DQB15
DQB16
DQB17
DQB18
DQB19
DQB20
DQB21
DQB22
DQB23
DQB24
DQB25
DQB26
DQB27
DQB28
DQB29
DQB30
DQB31
DQB32
DQB33
DQB34
DQB35
DQB36
DQB37
DQB38
DQB39
DQB40
DQB41
DQB42
DQB43
DQB44
DQB45
DQB46
DQB47
DQB48
DQB49
DQB50
DQB51
DQB52
DQB53
DQB54
DQB55
DQB56
DQB57
DQB58
DQB59
DQB60
DQB61
DQB62
DQB63

M24P_BGA708

2@

Part 3 of 5

2@

1 2

R198 0_0402_5%

MEMORY INTERFACE B

MDB[63:0] <22>

MAB[13:0] <22>

DQSB[7:0] <22>

DQMB#[7:0] <22>

MAB0
MAB1
MAB2
MAB3
MAB4
MAB5
MAB6
MAB7
MAB8

MAB9
MAB10
MAB11
MAB12
MAB13
MAB14

DQMB#0
DQMB#1
DQMB#2
DQMB#3
DQMB#4
DQMB#5
DQMB#6
DQMB#7

QSB0

QSB1

QSB2

QSB3

QSB4

QSB5

QSB6

QSB7
RASB#
CASB#

WEB#
CSB0#
CSB1#

CKEB

CLKB0

CLKB0#

CLKB1

CLKB1#

DIMB_0
DIMB_1

ROMCS#

MEMVMODE_0
MEMVMODE_1

MEMTEST

N5
M1
M3
L3
L2
M2
M5
P6
N3
K2
K3
J2
P5
P3
P2

E6
B2
J5
G3
W6
W2
AC6
AD2

F6
B3
K6
G1
V5
W1
AC5
AD1

R2
T5
T6
R5
R6
R3
N1

N2
T2

T3

E3
AA3

AF5
C6

C7
C8

R193

47_0402_5%

CSB1# <22>

2@

MAB0
MAB1
MAB2
MAB3
MAB4
MAB5
MAB6
MAB7
MAB8
MAB9
MAB10
MAB11
MAB12
MAB13

DQMB#0
DQMB#1
DQMB#2
DQMB#3
DQMB#4
DQMB#5
DQMB#6
DQMB#7

DQSB0
DQSB1
DQSB2
DQSB3
DQSB4
DQSB5
DQSB6
DQSB7

RASB#
CASB#
WEB#
CSB0#

M_CSB1#

CKEB
CLKB0

CLKB0#
CLKB1

CLKB1#

12

12

2@

R194

4.7K_0402_5%

NOTE :Elpida Memory Data Groups
Swapping Possibilities-­Shaded group belonging to QS1 and QS5
can't be swapped with other groups
(MD15:8) & (MD47:40)

RASB# <22>
CASB# <22>
WEB# <22>
CSB0# <22>

CKEB <22>

+VDD_CORE1.8

CLKB0 <22>
CLKB0# <22>

CLKB1 <22>
CLKB1# <22>

SCS# <17>

R190 4.7K_0402_5%2@

1 2

R192 4.7K_0402_5%@

1 2

12

@

R195

4.7K_0402_5%

12

2@

R187
10K_0402_5%

MEM IO Voltage Selection

MEMVMODE0
MEMVMODE1

2.5V *
VDDR1

HI

LOW

1.8V
VDDR1

LOW
HI

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

ATI M24P MEM_Interface

HDL75 LA3041

18 60Thursday, July 28, 2005

1

0.1

5

+VDD_MEM_IO

D D

2@

C213

0.1U_0402_16V4Z

0.1U_0402_16V4Z

C C

0.1U_0402_16V4Z

B B

+1.8VS to +1.8V_REG

+1.8VS

A A

D28

80 mil

2@

1

2

1000P_0402_50V7K

1

2@

C221

2

1

2@

C228

2

+3VS

2@

MMSZ4678T1_SOD123

2 1

80 mil

C205

2

2@

C214

+1.8VS

1

1

C206

2@

2

22U_1206_10V4Z

1

2

0.1U_0402_16V4Z

1

2@

C222

2

0.1U_0402_16V4Z

1

2@

C229

2

0.1U_0402_16V4Z

+VDD_PNLIO_2.5

+VDD_PNL_IO1.8

+VDD_PNL_PLL

+VDD_MEM_CLK

+VDD_DAC2.5

+A2VDDQ_1.8

+AVDD_1.8

+VDDDI_1.8

+VDD_PLL

+VDD_MEM_PLL

22U_1206_10V4Z

1

2@

C215

2

1000P_0402_50V7K

1000P_0402_50V7K

2@

C223

1000P_0402_50V7K

2@

C230

2@

C216

4

U5D

T7

VDDR1_0

R4

VDDR1_1

R1

VDDR1_2

N8

VDDR1_3

N7

VDDR1_4

M4

VDDR1_5

L8

VDDR1_6

K23

VDDR1_7

K24

VDDR1_8

N4

VDDR1_9

J8

VDDR1_10

J7

VDDR1_11

J4

VDDR1_12

J1

VDDR1_13

H10

VDDR1_14

H13

VDDR1_15

H15

VDDR1_16

AD4

AE16
AE17

AF15

AE15

AH19
AH13

AF13
AF14

AF21

AE20

AF23

AH23

AE23
AE22

AK28

H17

AA1
AA4
AA7
AA8

A15
A21
A28

B30
D26
D23
D20
D17
D14
D11

E27

G10
G13
G15
G19
G22
G27
H22
H19

L23

F18

T8
V4
V7
V8

A3
A9

B1

D8
D5

F4
G7

N6

A7

VDDR1_17
VDDR1_18
VDDR1_19
VDDR1_20
VDDR1_21
VDDR1_22
VDDR1_23
VDDR1_24
VDDR1_25
VDDR1_26
VDDR1_27
VDDR1_28
VDDR1_29
VDDR1_30
VDDR1_31
VDDR1_32
VDDR1_33
VDDR1_34
VDDR1_35
VDDR1_36
VDDR1_37
VDDR1_38
VDDR1_39
VDDR1_40
VDDR1_41
VDDR1_42
VDDR1_43
VDDR1_44
VDDR1_45
VDDR1_46
VDDR1_47
VDDR1_48
VDDR1_49
VDDR1_50
VDDR1_51
VDDR1_52
VDDR1_53

LVDDR_25_0
LVDDR_25_1
LVDDR_18_0
LVDDR_18_1

LPVDD
TPVDD

TXVDDR_0
TXVDDR_1

VDDRH0
VDDRH1

A2VDD_0
A2VDD_1

A2VDDQ
AVDD

VDD1DI
VDD2DI

PVDD
MPVDD

M24P_BGA708

2@

1

2

1

2

1

2

Part 4 of 5

POWER

PCIE_VDDR_12_0
PCIE_VDDR_12_1
PCIE_VDDR_12_2
PCIE_VDDR_12_3
PCIE_VDDR_12_4

PCIE_PVDD_12_0
PCIE_PVDD_12_1
PCIE_PVDD_12_2

PCIE_PVDD_18_0
PCIE_PVDD_18_1
PCIE_PVDD_18_2
PCIE_PVDD_18_3

VDDC_0
VDDC_1
VDDC_2
VDDC_3
VDDC_4
VDDC_5
VDDC_6
VDDC_7
VDDC_8

VDDC_9
VDDC_10
VDDC_11
VDDC_12
VDDC_13
VDDC_14
VDDC_15
VDDC_16
VDDC_17
VDDC_18
VDDC_19
VDDC_20
VDDC_21
VDDC_22
VDDC_23
VDDC_24
VDDC_25
VDDC_26
VDDC_27
VDDC_28
VDDC_29
VDDC_30
VDDC_31
VDDC_32
VDDC_33
VDDC_34
VDDC_35
VDDC_36
VDDC_37
VDDC_38
VDDC_39
VDDC_40

VDDC1_0
VDDC1_1
VDDC1_2
VDDC1_3

VDD15_0
VDD15_1
VDD15_2
VDD15_3
VDD15_4
VDD15_5
VDD15_6
VDD15_7

VDDR3_0
VDDR3_1
VDDR3_2
VDDR3_3
VDDR3_4
VDDR3_5
VDDR3_6

VDDR4_0
VDDR4_1
VDDR4_2
VDDR4_3
VDDR4_4

AC13
AD13
AD15
AC15
AC17
P17
P18
P19
U12
U13
U14
U17
U18
U19
V19
V18
V17
V14
V13
V12
N18
N17
N14
W17
W18
W12
W13
W14
N13
N19
M19
M18
M12
N12
M13
M14
P12
P13
P14
M17
W19

W16
M15
R19
T12

P8
Y8
AC11
AC20
H20
H11
M23
Y23

AD7
AD19
AD21
AC22
AC8
AC21
AC19

AG7
AD9
AC9
AC10
AD10

AG26
AK29
AJ30
AG28
AG27

N24
N23
P23

U23
T23
V23
W23

3

1

C207

2@

0.1U_0402_16V4Z

2

L20

1 2

2@

CHB1608U301_0603

0.1U_0402_16V4Z

0.1U_0402_16V4Z

2.2U_0603_6.3V6K

1

C234

2@

12

2

R204
0_0603_5%

2@

2@

C238

22U_A_4VM

1

C242

2@

2

1

2@

2

1

2@

C217

2

0.1U_0402_16V4Z

1

C224

2@

2

1

C226

2@

2

0.1U_0402_16V4Z

1

C235

2@

1000P_0402_50V7K

2

0.1U_0402_16V4Z

1

+

C239

2@

2

0.1U_0402_16V4Z

1

C243

2@

2

22U_1206_10V4Z

C208

0.1U_0402_16V4Z

1

2@

2

0.1U_0402_16V4Z

VDDL_CORE

1

C225

2@

0.1U_0402_16V4Z

2

1

C227

2@

0.1U_0402_16V4Z

2

2@

1

C231

2@

2

22U_1206_10V4Z

1

C236

2@

2

1

2

1

2@

2

1000P_0402_50V7K

1

C244
1000P_0402_50V7K2@

2

1

C209

2@

0.1U_0402_16V4Z

2

C218

L_+1.5V

1

C232

2

+3VS

30 mil

1

2

C240

PCIEL_1.2V

2

2@

+3VS

D6

0.1U_0402_16V4Z

+

C237
22U_A_4VM

2@

1

2@

C241

0.1U_0402_16V4Z

2

+3VS

DIODE SUPPLIES POWER
TO VDDC RAIL
WHILE VDDC REGULATOR
STABALIZES DURING POWER ON

D5

2@

MMSZ4678T1_SOD123

2 1

1

C210

2@

0.1U_0402_16V4Z

2

1

C219

2

0.1U_0402_16V4Z

2@

MMSZ4678T1_SOD123

20 mil

2 1

2@

1

C233

0.1U_0402_16V4Z

2

L25

1 2

2@

FBM-L11-321611-260-LMT_1206

L23

1 2

2@

CHB1608U301_0603

1

2@

2

0.1U_0402_16V4Z

1 2

0_0805_5%

1

C211

2@

0.1U_0402_16V4Z

2

C220

L21

2@

+PCIE_PVDD1.8

40 mil

+VGA_CORE

+1.5VS

+1.2VS

1

1

+

C212
470U_D4_2.5VM_R10

2@

2

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

ATI M24P I/O PWR(1/2)

HDL75 LA3041

19 60Thursday, July 28, 2005

1

0.1

of

5

EXP_TXN[0..15]<11>

U5E

A2

VSS_0

A10

VSS_1

A16

VSS_2

A22

VSS_3

D D

C C

B B

A A

A29

VSS_4

C1

VSS_5

C3

VSS_6

C28

VSS_7

C30

VSS_8

D27

VSS_9

D24

VSS_10

D21

VSS_11

D18

VSS_12

D15

VSS_13

D12

VSS_14

D10

VSS_15

D6

VSS_16

D4

VSS_17

F27

VSS_18

G9

VSS_19

G12

VSS_20

G16

VSS_21

G18

VSS_22

G21

VSS_23

G24

VSS_24

H27

VSS_25

H23

VSS_26

H21

VSS_27

H18

VSS_28

H16

VSS_29

H14

VSS_30

H12

VSS_31

H9

VSS_32

H8

VSS_33

H4

VSS_34

J23

VSS_35

J24

VSS_36

AD12

VSS_37

AG5

VSS_38

AG9

VSS_39

AG11

VSS_40

R7

VSS_41

P4

VSS_42

M7

VSS_43

M8

VSS_44

L4

VSS_45

K1

VSS_46

K7

VSS_47

K8

VSS_48

R8

VSS_49

T1

VSS_50

U4

VSS_51

U8

VSS_52

W7

VSS_53

W8

VSS_54

Y4

VSS_55

AB8

VSS_56

AB7

VSS_57

AB1

VSS_58

AC4

VSS_59

AC12

VSS_60

AC14

VSS_61

AD16

VSS_62

AC16

VSS_63

AC18

VSS_64

AD18

VSS_65

AK2

VSS_66

AJ1

VSS_67

M16

VSS_68

N16

VSS_69

N15

VSS_70

P15

VSS_71

P16

VSS_72

R18

VSS_73

R17

VSS_74

R16

VSS_75

R15

VSS_76

R14

VSS_77

R13

VSS_78

R12

VSS_79

T13

VSS_80

T14

VSS_81

T15

VSS_82

W15

VSS_83

V16

VSS_84

V15

VSS_85

U15

VSS_86

U16

VSS_87

T19

VSS_88

T18

VSS_89

T17

VSS_90

T16

VSS_91

M24P_BGA708

2@

Note: C261,C336, C268
C281, C320, C274, C295
C328, C301 need to replace by Oxi Cap in B test.

Part 5 of 5

5

GND

PCIE_VSS_0
PCIE_VSS_1
PCIE_VSS_2
PCIE_VSS_3
PCIE_VSS_4
PCIE_VSS_5
PCIE_VSS_6
PCIE_VSS_7
PCIE_VSS_8

PCIE_VSS_9
PCIE_VSS_10
PCIE_VSS_11
PCIE_VSS_12
PCIE_VSS_13
PCIE_VSS_14
PCIE_VSS_15
PCIE_VSS_16
PCIE_VSS_17
PCIE_VSS_18
PCIE_VSS_19
PCIE_VSS_20
PCIE_VSS_21
PCIE_VSS_22
PCIE_VSS_23
PCIE_VSS_24
PCIE_VSS_25
PCIE_VSS_26
PCIE_VSS_27
PCIE_VSS_28
PCIE_VSS_29
PCIE_VSS_30
PCIE_VSS_31
PCIE_VSS_32
PCIE_VSS_33
PCIE_VSS_34
PCIE_VSS_35
PCIE_VSS_36
PCIE_VSS_37
PCIE_VSS_38
PCIE_VSS_39

NC_0
NC_1
NC_2
NC_3
NC_4
NC_5
NC_6

AVSSQ

LVSSR_0
LVSSR_1
LVSSR_2
LVSSR_3

LPVSS

TPVSS

TXVSSR_0
TXVSSR_1
TXVSSR_2

VSSRH0
VSSRH1

A2VSSN_0
A2VSSN_1

A2VSSQ

AVSSN

VSS1DI
VSS2DI

PVSS

MPVSS

K28
L28
M27
M26
M24
M25
M28
P28
N28
R25
R23
R24
R26
R27
R28
T28
T24
U28
V24
V26
V27
V25
V28
Y28
W24
W28
AA26
AA27
AA23
AA24
AA25
AA28
AB28
AC28
AD28
AD26
AD27
AE28
AF28
AH29

D9
D13
D19
D25
E4
T4
AB4

AD22

AF18
AH17
AG15
AG18

AH18
AH12

AH14
AG13
AG14

F19
M6

AH20
AG21

AF22
AH22

AE24
AE21

AJ28

A6

EXP_TXP[0..15]<11>

EXP_RXN[0..15]<11>

EXP_RXP[0..15]<11>

4

EXP_TXN[0..15]

EXP_TXN0
EXP_TXN1

EXP_TXN2
EXP_TXN3

EXP_TXN5
EXP_TXN6

EXP_TXN7
EXP_TXN8

EXP_TXN9
EXP_TXN10

EXP_TXN11
EXP_TXN12

EXP_TXN13
EXP_TXN14

EXP_TXN15

EXP_TXP[0..15]

EXP_TXP0
EXP_TXP1

EXP_TXP2
EXP_TXP3

EXP_TXP4
EXP_TXP5

EXP_TXP6
EXP_TXP7

EXP_TXP8
EXP_TXP9

EXP_TXP10
EXP_TXP11

EXP_TXP12
EXP_TXP13

EXP_TXP14
EXP_TXP15

EXP_RXN[0..15]

EXP_RXN0
EXP_RXN1

EXP_RXN2
EXP_RXN3

EXP_RXN4
EXP_RXN5

EXP_RXN6
EXP_RXN7

EXP_RXN8
EXP_RXN9

EXP_RXN10
EXP_RXN11

EXP_RXN12
EXP_RXN13

EXP_RXN14
EXP_RXN15

EXP_RXP[0..15]

EXP_RXP0
EXP_RXP1

EXP_RXP2
EXP_RXP3

EXP_RXP4
EXP_RXP5

EXP_RXP6
EXP_RXP7

EXP_RXP8
EXP_RXP9

EXP_RXP10
EXP_RXP11

EXP_RXP12
EXP_RXP13

EXP_RXP14
EXP_RXP15

4

3

Close ALVISO

2@

C245 0.1U_0402_16V4Z

1 2

C246 0.1U_0402_16V4Z

1 2

2@

C250 0.1U_0402_16V4Z

1 2

2@

C252 0.1U_0402_16V4Z

1 2

2@

C257 0.1U_0402_16V4Z

1 2

2@

C259 0.1U_0402_16V4Z

1 2

2@

C264 0.1U_0402_16V4Z

1 2

2@

C266 0.1U_0402_16V4Z

1 2

2@

C271 0.1U_0402_16V4Z

1 2

2@

C273 0.1U_0402_16V4Z

1 2

2@

C278 0.1U_0402_16V4Z

1 2

2@

C280 0.1U_0402_16V4Z

1 2

2@

C285 0.1U_0402_16V4Z

1 2

2@

C287 0.1U_0402_16V4Z

1 2

2@

C292 0.1U_0402_16V4Z

1 2

2@

C294 0.1U_0402_16V4Z

1 2

2@

C299 0.1U_0402_16V4Z

1 2

Close M24P

2@

C304 0.1U_0402_16V4Z

1 2

2@

C306 0.1U_0402_16V4Z

1 2

2@

C308 0.1U_0402_16V4Z

1 2

2@

C310 0.1U_0402_16V4Z

1 2

2@

C314 0.1U_0402_16V4Z

1 2

2@

C316 0.1U_0402_16V4Z

1 2

2@

C318 0.1U_0402_16V4Z

1 2

2@

C323 0.1U_0402_16V4Z

1 2

2@

C325 0.1U_0402_16V4Z

1 2

2@

C327 0.1U_0402_16V4Z

1 2

2@

C332 0.1U_0402_16V4Z

1 2

2@

C334 0.1U_0402_16V4Z

1 2

2@

C338 0.1U_0402_16V4Z

1 2

2@

C340 0.1U_0402_16V4Z

1 2

2@

C342 0.1U_0402_16V4Z

1 2

2@

C344 0.1U_0402_16V4Z

1 2

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2@

C251 0.1U_0402_16V4Z

1 2

2@

C253 0.1U_0402_16V4Z

1 2

2@

C258 0.1U_0402_16V4Z

1 2

2@

C260 0.1U_0402_16V4Z

1 2

2@

C265 0.1U_0402_16V4Z

1 2

2@

C267 0.1U_0402_16V4Z

1 2

2@

C272 0.1U_0402_16V4Z

1 2

2@

C277 0.1U_0402_16V4Z

1 2

2@

C279 0.1U_0402_16V4Z

1 2

2@

C284 0.1U_0402_16V4Z

1 2

2@

C286 0.1U_0402_16V4Z

1 2

2@

C291 0.1U_0402_16V4Z

1 2

2@

C293 0.1U_0402_16V4Z

1 2

2@

C298 0.1U_0402_16V4Z

1 2

2@

C300 0.1U_0402_16V4Z

1 2

2@

C305 0.1U_0402_16V4Z

1 2

2@

C307 0.1U_0402_16V4Z

1 2

2@

C309 0.1U_0402_16V4Z

1 2

2@

C311 0.1U_0402_16V4Z

1 2

2@

C315 0.1U_0402_16V4Z

1 2

2@

C317 0.1U_0402_16V4Z

1 2

2@

C319 0.1U_0402_16V4Z

1 2

2@

C324 0.1U_0402_16V4Z

1 2

2@

C326 0.1U_0402_16V4Z

1 2

2@

C331 0.1U_0402_16V4Z

1 2

2@

C333 0.1U_0402_16V4Z

1 2

2@

C335 0.1U_0402_16V4Z

1 2

2@

C339 0.1U_0402_16V4Z

1 2

2@

C341 0.1U_0402_16V4Z

1 2

2@

C343 0.1U_0402_16V4Z

1 2

2@

C345 0.1U_0402_16V4Z

1 2

2@

3

PEG_RXN0
PEG_RXN1

PEG_RXN2
PEG_RXN3

PEG_RXN4EXP_TXN4
PEG_RXN5

PEG_RXN6
PEG_RXN7

PEG_RXN8
PEG_RXN9

PEG_RXN10
PEG_RXN11

PEG_RXN12
PEG_RXN13

PEG_RXN14
PEG_RXN15

PEG_RXP0
PEG_RXP1

PEG_RXP2
PEG_RXP3

PEG_RXP4
PEG_RXP5

PEG_RXP6
PEG_RXP7

PEG_RXP8
PEG_RXP9

PEG_RXP10
PEG_RXP11

PEG_RXP12
PEG_RXP13

PEG_RXP14
PEG_RXP15

PEG_TXN0
PEG_TXN1

PEG_TXN2
PEG_TXN3

PEG_TXN4
PEG_TXN5

PEG_TXN6
PEG_TXN7

PEG_TXN8
PEG_TXN9

PEG_TXN10
PEG_TXN11

PEG_TXN12
PEG_TXN13

PEG_TXN14
PEG_TXN15

PEG_TXP0
PEG_TXP1

PEG_TXP2
PEG_TXP3

PEG_TXP4
PEG_TXP5

PEG_TXP6
PEG_TXP7

PEG_TXP8
PEG_TXP9

PEG_TXP10
PEG_TXP11

PEG_TXP12
PEG_TXP13

PEG_TXP14
PEG_TXP15

PEG_RXN[0..15]

PEG_RXN[0..15] <17>

PEG_RXP[0..15]

PEG_RXP[0..15] <17>

PEG_TXN[0..15]

PEG_TXN[0..15] <17>

PEG_TXP[0..15]

PEG_TXP[0..15] <17>

+1.8VS

+2.5VS

+1.8VS

*

VDDR1
VDDRH

1.8V

2.5V

2

L24

1 2

0_0805_5%

R1132

1 2

0_0603_5%

L61

1 2

CHB1608U301_0603

R1133

1 2

0_0603_5%

L63

1 2

CHB1608U301_0603

R1134

1 2

0_0603_5%

L70

1 2

CHB1608U301_0603

R1135

1 2

0_0603_5%

R1136

1 2

0_0603_5%

L33 FBM-L11-201209-121LMT_0805@
L34

L37 0_0603_5%2@
L38 CHB1608U301_0603@

FBa

FBb

OUT OUT

IN

IN

OUT

J6

2 1

JUMP_43X79

2

1

2@

2@

C247

22U_1206_10V4Z

2@

2@

C254

22U_A_4VM

2@

2@

C261

22U_1206_10V4Z

2@

2@

C268

22U_1206_10V4Z

2@

2@

C274

22U_1206_10V4Z

2@

2@

C281

22U_1206_10V4Z

2@

2@

2@

C295

22U_1206_10V4Z

2@

2@

C301

22U_1206_10V4Z

FBa

1 2
1 2

FBb

FBc

1 2
1 2

FBd

FBc

FBd

IN

IN

OUT

Title

Size Document Number Rev

Date: Sheet of

0.1U_0402_16V4Z

1

2

1

+

2

0.1U_0402_16V4Z

1

2

0.1U_0402_16V4Z

1

2

0.1U_0402_16V4Z

1

2

0.1U_0402_16V4Z

1

2

0.1U_0402_16V4Z

1

+

C288
22U_A_4VM

2@

2

0.1U_0402_16V4Z

1

2

0.1U_0402_16V4Z

1

2

0_0805_5%2@

+

C312

22U_A_4VM

2@

C328

22U_1206_10V4Z

2@

C336

22U_1206_10V4Z

2@

C320

22U_1206_10V4Z

1

2

0.1U_0402_16V4Z

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2@

2

1

2

1

2

1

2

1

2@

C248

2@

C255

2@

C262

2@

C269

2@

C275

2@

C282

2@

C289

2@

C296

2@

C302

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

2@

C249
1000P_0402_50V7K

2

1

2@

C256
1000P_0402_50V7K

2

1

2@

C263
1000P_0402_50V7K

2

1

2@

C270
1000P_0402_50V7K

2

1

2@

C276
1000P_0402_50V7K

2

1

2@

C283
1000P_0402_50V7K

2

1

2@

C290
1000P_0402_50V7K

2

1

2@

C297
1000P_0402_50V7K

2

1

2@

C303
1000P_0402_50V7K

2

(1000 MA 1.8V/2.5V EXT MEM VDDQ, VDDR1)

1

2@

C313

2

0.1U_0402_16V4Z

1

2@

C329

2

1

2@

C337

2

1

2@

C321

2

(500 MA 1.8V PCIE PVDD)

(150 MA 1.8V VDDC1.8)

(30MA 1.8V PVDD)

(35 MA 1.8V
LVDDR18,LVDDR18_25,TXVDDR)

(10MA 1.8V LPVDD,TPVDD)

(35 MA 1.8V A2VDDQ)

(5 MA 1.8V MPVDD)

(35 MA 1.8V AVDD)

(10 MA 1.8V VDDDI)

(INCLUDED IN VDD_MEM_IO)

1

2@

C330

0.1U_0402_16V4Z

2

(1000MA 2.5V EXT MEM VDD)

1

2@

C322

0.1U_0402_16V4Z

2

Compal Electronics, Inc.

ATI M24P I/O PWR(2/2)

HDL75 LA3041

1

+PCIE_PVDD1.8

+VDD_CORE1.8

+VDD_PLL

+VDD_PNL_IO1.8

+VDD_PNL_PLL

+A2VDDQ_1.8

+VDD_MEM_PLL

+AVDD_1.8

+VDDDI_1.8

+VDD_MEM_IO

+VDD_MEM_CLK

+VDD_DAC2.5

(80MA 2.5V A2VDD)

+VDD_PNLIO_2.5

(200MA 2.5V LVDDR_25)

+MEM_VDD+2.5VS

20 60Thursday, July 28, 2005

0.1

5

4

3

2

1

2@

R209

56_0402_5%

2@

C348

2@

R211
56_0402_5%

C354

2@

1

DQMA#[7..0]
MAA[13..0]
DQSA[7..0]

MDA[63..0]

1

2

1

2

21 60Thursday, July 28, 2005

12

2@

R210

56_0402_5%

12

2@

R212
56_0402_5%

0.1

DQMA#[7:0]<18>

B11

D10

D11

F10

G10

H10

J10

U6

2@

VSSQB4VSSQ

VSSQD4VSSQD5VSSQD6VSSQD9VSSQ

VSSQ

VSSQE6VSSQE9VSSQF5VSSQ

MAA0
MAA1
MAA2

D D

+VDD_MEM_IO

12

R205

2@

1K_0402_5%

10mil 10mil

12

R207

1K_0402_5%

C C

B B

2@

C346

1

2@

0.1U_0402_16V4Z

2

RASA#<18>
CASA#<18>
WEA#<18>
CSA0#<18>

CKEA<18>
CLKA0<18>

CLKA0#<18>

CSA1#<18>

MAA3
MAA4
MAA5
MAA6
MAA7
MAA8
MAA9
MAA10
MAA11
MAA12
MAA13

DQMA#3
DQMA#0
DQMA#1
DQMA#2

DQSA3
DQSA0
DQSA1
DQSA2

RASA#
CASA#
WEA#
CSA0#

CKEA
CLKA0

CLKA0#

CSA1#

N10
N11

H12
B12

H13
B13
N13

M13
M10

N12

M11
M12

C11
H11

E10

N5

A0

N6

A1

M6

A2

N7

A3

N8

A4

M9

A5

N9

A6
A7
A8/AP

M8

A9

L6

A10

M7

A11

N4

BA0

M5

BA1

B3

DM0
DM1

H3

DM2
DM3

B2

DQS0
DQS1

H2

DQS2
DQS3

VREF
MCL

L9

RFU1
RFU2

M2

RAS#

L2

CAS#

L3

WE#

N2

CS#
CKE
CK

CK#

C4

NC
NC

H4

NC
NC

L12

NC

L13

NC

M3

NC

M4

NC

N3

NC

E7

VSS

E8

VSS
VSS

K6

VSS

K7

VSS

K8

VSS

K9

VSS

L5

VSS

L10

VSS

E5

VSS

VSSQG5VSSQ

VSS THF6VSS THF7VSS THF8VSS THF9VSS THG6VSS THG7VSS THG8VSS THG9VSS THH6VSS THH7VSS THH8VSS THH9VSS THJ6VSS THJ7VSS THJ8VSS TH

+VDD_MEM_IO

1U_0603_10V4Z

1

C355

2@

2

0.1U_0402_16V4Z

+MEM_VDD

A A

1

C365

2@

2

0.1U_0402_16V4Z

1

2@

C356

2

1U_0603_10V4Z

1

2@

C366

2

1

C357

2@

2

1000P_0402_50V7K

1

2@

C367

2

1000P_0402_50V7K

Samsung 8M32-33/600 FBGA 2.5V

0.01U_0402_16V7K

1

C358

2@

2

0.1U_0402_16V4Z

1

2@

C368

2

1

+

2

1

+

2

C359
22U_A_4VM

2@

C369
22U_A_4VM

2@

Place close to U6

5

K10

VSSQH5VSSQ

VSSQJ5VSSQ

VSSQK5VSSQ

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8

DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

K4D553238E-JC33_FBGA144

J9

B7
C6
B6
B5
C2
D3
D2
E2
K13
K12
J13
J12
G13
G12
F13
F12
F3
F2
G3
G2
J3
J2
K2
K3
E13
D13
D12
C13
B10
B9
C9
B8

C3
C5
C7
C8
C10
C12
E3
E12
F4
F11
G4
G11
J4
J11
K4
K11

D7
D8
E4
E11
L4
L7
L8
L11

0.1U_0402_16V4Z

0.1U_0402_16V4Z

MDA29
MDA31
MDA26
MDA30
MDA27
MDA28
MDA24
MDA25
MDA3
MDA4
MDA5
MDA6
MDA7
MDA0
MDA2
MDA1
MDA10
MDA9
MDA11
MDA12
MDA15
MDA14
MDA13
MDA8
MDA16
MDA23
MDA21
MDA22
MDA20
MDA19
MDA18
MDA17

+VDD_MEM_IO

+MEM_VDD

Place close to U7

4

MAA0
MAA1
MAA2
MAA3
MAA4
MAA5
MAA6
MAA7

CSA1#

1

+

2

1

+

2

MAA8
MAA9
MAA10
MAA11
MAA12
MAA13

DQMA#4
DQMA#6
DQMA#5
DQMA#7

DQSA4
DQSA6
DQSA5
DQSA7

RASA#
CASA#
WEA#
CSA0#

CKEA
CLKA1

CLKA1#

C353
22U_A_4VM

2@

C364
22U_A_4VM

2@

+VDD_MEM_IO

12

2@

R206
1K_0402_5%

12

2@

R208

1K_0402_5%

+VDD_MEM_IO

+MEM_VDD

1U_0603_10V4Z

C349

2@

C360

2@

1

2@

C350

2

1U_0603_10V4Z

1

C361

2@

2

1000P_0402_50V7K

0.1U_0402_16V4Z

1

2

1

2

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C351

2@

1

2

0.01U_0402_16V7K

1

2

0.01U_0402_16V7K

1

C362

2@

2

C347

2@

0.1U_0402_16V4Z

RASA#<18>
CASA#<18>
WEA#<18>
CSA0#<18>

CKEA<18>
CLKA1<18>

CLKA1#<18>

CSA1#<18>

1

C352

2@

2

1

C363

2@

2

3

B11

D10

D11

F10

VSSQ

VSSQE6VSSQE9VSSQF5VSSQ

G10

VSSQG5VSSQ

N10
N11

H12
B12

H13
B13
N13

M13
M10

N12
M11

M12

C11
H11

E10

U7

2@

VSSQB4VSSQ

VSSQD4VSSQD5VSSQD6VSSQD9VSSQ

N5

A0

N6

A1

M6

A2

N7

A3

N8

A4

M9

A5

N9

A6
A7
A8/AP

M8

A9

L6

A10

M7

A11

N4

BA0

M5

BA1

B3

DM0
DM1

H3

DM2
DM3

B2

DQS0
DQS1

H2

DQS2
DQS3

VREF
MCL

L9

RFU1
RFU2

M2

RAS#

L2

CAS#

L3

WE#

N2

CS#
CKE
CK

CK#

C4

NC
NC

H4

NC
NC

L12

NC

L13

NC

M3

NC

M4

NC

N3

NC

E7

VSS

E8

VSS
VSS

K6

VSS

K7

VSS

K8

VSS

K9

VSS

L5

VSS

L10

VSS

E5

VSS

VSS THF6VSS THF7VSS THF8VSS THF9VSS THG6VSS THG7VSS THG8VSS THG9VSS THH6VSS THH7VSS THH8VSS THH9VSS THJ6VSS THJ7VSS THJ8VSS TH

Samsung 8M32-33/600 FBGA 2.5V

2

H10

J10

K10

VSSQH5VSSQ

VSSQJ5VSSQ

VSSQK5VSSQ

B7

DQ0

C6

DQ1

B6

DQ2

B5

DQ3

C2

DQ4

D3

DQ5

D2

DQ6

E2

DQ7

K13

DQ8

K12

DQ9

J13

DQ10

J12

DQ11

G13

DQ12

G12

DQ13

F13

DQ14

F12

DQ15

F3

DQ16

F2

DQ17

G3

DQ18

G2

DQ19

J3

DQ20

J2

DQ21

K2

DQ22

K3

DQ23

E13

DQ24

D13

DQ25

D12

DQ26

C13

DQ27

B10

DQ28

B9

DQ29

C9

DQ30

B8

DQ31

C3

VDDQ

C5

VDDQ

C7

VDDQ

C8

VDDQ

C10

VDDQ

C12

VDDQ

E3

VDDQ

E12

VDDQ

F4

VDDQ

F11

VDDQ

G4

VDDQ

G11

VDDQ

J4

VDDQ

J11

VDDQ

K4

VDDQ

K11

VDDQ

D7

VDD

D8

VDD

E4

VDD

E11

VDD

L4

VDD

L7

VDD

L8

VDD

L11

VDD

K4D553238E-JC33_FBGA144

J9

MAA[13:0]<18>

DQSA[7:0]<18>

+MEM_VDD

MDA[63:0]<18>

CLKA0
CLKA0#

12

470P_0402_50V7K

MDA35
MDA39
MDA37
MDA38
MDA36
MDA33
MDA34
MDA32
MDA52
MDA53
MDA55
MDA54
MDA51
MDA50
MDA48
MDA49
MDA44
MDA45
MDA46
MDA43
MDA47
MDA40
MDA42
MDA41
MDA62
MDA61
MDA63
MDA58
MDA60
MDA59
MDA57
MDA56

+VDD_MEM_IO

Place as close to U6, U7 as possible

CLKA1
CLKA1#

12

470P_0402_50V7K

Place as close to U6, U7 as possible

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

Channel A External 128/64M DDR

HDL75 LA3041

5

B11

D10

D11

VSSQ

VSSQE6VSSQE9VSSQF5VSSQ

F10

U8

2@

VSSQB4VSSQ

N10
N11

H12
B12

H13
B13
N13

M13
M10

N12
M11

M12

C11
H11

L12
L13

E10

L10

VSSQD4VSSQD5VSSQD6VSSQD9VSSQ

N5

A0

N6

A1

M6

A2

N7

A3

N8

A4

M9

A5

N9

A6
A7
A8/AP

M8

A9

L6

A10

M7

A11

N4

BA0

M5

BA1

B3

DM0
DM1

H3

DM2
DM3

B2

DQS0
DQS1

H2

DQS2
DQS3

VREF
MCL

L9

RFU1
RFU2

M2

RAS#

L2

CAS#

L3

WE#

N2

CS#
CKE
CK

CK#

C4

NC
NC

H4

NC
NC
NC
NC

M3

NC

M4

NC

N3

NC

E7

VSS

E8

VSS
VSS

K6

VSS

K7

VSS

K8

VSS

K9

VSS

L5

VSS
VSS

E5

VSS

MAB0
MAB1
MAB2

D D

+VDD_MEM_IO

12

2@

1K_0402_5%
R214

10mil

12

2@

R215

1K_0402_5%

C C

B B

C370

1

0.1U_0402_16V4Z

2@

2

RASB#<18>
CASB#<18>
WEB#<18>
CSB0#<18>

CKEB<18>
CLKB0<18>

CLKB0#<18>

CSB1#<18>

MAB3
MAB4
MAB5
MAB6
MAB7
MAB8
MAB9
MAB10
MAB11
MAB12
MAB13

DQMB#0
DQMB#2
DQMB#1
DQMB#3

DQSB0
DQSB2
DQSB1
DQSB3

RASB#
CASB#
WEB#
CSB0#

CKEB
CLKB0

CLKB0#

CSB1#

VSS THF6VSS THF7VSS THF8VSS THF9VSS THG6VSS THG7VSS THG8VSS THG9VSS THH6VSS THH7VSS THH8VSS THH9VSS THJ6VSS THJ7VSS THJ8VSS TH

Samsung 8M32-33/600 FBGA 2.5V

+VDD_MEM_IO

1U_0603_10V4Z

1

C379

2@

2

0.1U_0402_16V4Z

+MEM_VDD

A A

1

C389

2@

2

0.1U_0402_16V4Z

1

C380

2@

2

1U_0603_10V4Z

1

C390

2@

2

C381

2@

1000P_0402_50V7K

0.1U_0402_16V4Z

1

2

1

C391

2@

2

0.1U_0402_16V4Z

1

C382

2@

2

0.01U_0402_16V7K

1

C392

2@

2

1

+

2

1

+

2

C383
22U_A_4VM

2@

C393
22U_A_4VM

2@

Place close to U8

5

G10

VSSQG5VSSQ

4

H10

J10

K10

VSSQH5VSSQ

VSSQJ5VSSQ

VSSQK5VSSQ

B7

DQ0

C6

DQ1

B6

DQ2

B5

DQ3

C2

DQ4

D3

DQ5

D2

DQ6

E2

DQ7

K13

DQ8

K12

DQ9

J13

DQ10

J12

DQ11

G13

DQ12

G12

DQ13

F13

DQ14

F12

DQ15

F3

DQ16

F2

DQ17

G3

DQ18

G2

DQ19

J3

DQ20

J2

DQ21

K2

DQ22

K3

DQ23

E13

DQ24

D13

DQ25

D12

DQ26

C13

DQ27

B10

DQ28

B9

DQ29

C9

DQ30

B8

DQ31

C3

VDDQ

C5

VDDQ

C7

VDDQ

C8

VDDQ

C10

VDDQ

C12

VDDQ

E3

VDDQ

E12

VDDQ

F4

VDDQ

F11

VDDQ

G4

VDDQ

G11

VDDQ

J4

VDDQ

J11

VDDQ

K4

VDDQ

K11

VDDQ

D7

VDD

D8

VDD

E4

VDD

E11

VDD

L4

VDD

L7

VDD

L8

VDD

L11

VDD

K4D553238E-JC33_FBGA144

J9

+VDD_MEM_IO

0.1U_0402_16V4Z

+MEM_VDD

0.1U_0402_16V4Z

Place close to U9

4

3

B11

D10

U9

2@

VSSQB4VSSQ

MDB3
MDB5 MDB39
MDB4
MDB6
MDB7
MDB2
MDB1
MDB0
MDB17
MDB19
MDB22
MDB23
MDB21
MDB20
MDB18
MDB16
MDB14
MDB15
MDB13
MDB12
MDB11
MDB9
MDB10
MDB8
MDB29
MDB31
MDB24
MDB26
MDB25
MDB30
MDB28
MDB27

+VDD_MEM_IO

1K_0402_5%

+VDD_MEM_IO

+MEM_VDD

12

2@

R213
1K_0402_5%

10mil

12

2@

C371 0.1U_0402_16V4Z

2@

R216

1

2

RASB#<18>
CASB#<18>
WEB#<18>
CSB0#<18>

CKEB<18>
CLKB1<18>

CLKB1#<18>

CSB1#<18>

MAB0
MAB1
MAB2
MAB3
MAB4
MAB5
MAB6
MAB7
MAB8
MAB9
MAB10
MAB11
MAB12
MAB13

DQMB#4
DQMB#6
DQMB#5
DQMB#7

DQSB4
DQSB6
DQSB5
DQSB7

RASB#
CASB#
WEB#
CSB0#

CKEB
CLKB1

CLKB1#

CSB1#

M13
M10

M11
M12

N10
N11

H12
B12

H13
B13
N13

N12

C11
H11

E10

N5

A0

N6

A1

M6

A2

N7

A3

N8

A4

M9

A5

N9

A6
A7
A8/AP

M8

A9

L6

A10

M7

A11

N4

BA0

M5

BA1

B3

DM0
DM1

H3

DM2
DM3

B2

DQS0
DQS1

H2

DQS2
DQS3

VREF
MCL

L9

RFU1
RFU2

M2

RAS#

L2

CAS#

L3

WE#

N2

CS#
CKE
CK

CK#

C4

NC
NC

H4

NC
NC

L12

NC

L13

NC

M3

NC

M4

NC

N3

NC

E7

VSS

E8

VSS
VSS

K6

VSS

K7

VSS

K8

VSS

K9

VSS

L5

VSS

L10

VSS

E5

VSS

D11

VSSQD4VSSQD5VSSQD6VSSQD9VSSQ

VSSQ

VSSQE6VSSQE9VSSQF5VSSQ

VSS THF6VSS THF7VSS THF8VSS THF9VSS THG6VSS THG7VSS THG8VSS THG9VSS THH6VSS THH7VSS THH8VSS THH9VSS THJ6VSS THJ7VSS THJ8VSS TH

1U_0603_10V4Z

1

C373

2@

2

1

C384

2@

2

1

C374

2@

2

0.1U_0402_16V4Z

1U_0603_10V4Z

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

1

C385

2@

2

0.1U_0402_16V4Z

1

C375

2@

2

1

C386

2@

2

0.1U_0402_16V4Z

1

C376

2@

2

0.01U_0402_16V7K

1

C387

2@

2

3

1

+

2

1

+

2

C377
22U_A_4VM

2@

C388
22U_A_4VM

2@

Samsung 8M32-33/600 FBGA 2.5V

F10

G10

VSSQG5VSSQ

2

H10

J10

K10

VSSQH5VSSQ

VSSQJ5VSSQ

VSSQK5VSSQ

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8

DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

K4D553238E-JC33_FBGA144

J9

2

B7
C6
B6
B5
C2
D3
D2
E2
K13
K12
J13
J12
G13
G12
F13
F12
F3
F2
G3
G2
J3
J2
K2
K3
E13
D13
D12
C13
B10
B9
C9
B8

C3
C5
C7
C8
C10
C12
E3
E12
F4
F11
G4
G11
J4
J11
K4
K11

D7
D8
E4
E11
L4
L7
L8
L11

MDB38
MDB35

MDB37
MDB36
MDB33
MDB34
MDB32
MDB50
MDB48
MDB54
MDB52
MDB55
MDB53
MDB49
MDB51
MDB46
MDB47
MDB44
MDB45
MDB41
MDB42
MDB43
MDB40
MDB63
MDB61
MDB62
MDB60
MDB59
MDB57
MDB58
MDB56

1

1

2

DQMB#[7:0]
MAB[13:0]
DQSB[7:0]

MDB[63:0]

12

2@

R218
56_0402_5%

+VDD_MEM_IO

+MEM_VDD

CLKB0
CLKB0#

470P_0402_50V7K

DQMB#[7:0]<18>
MAB[13:0]<18>
DQSB[7:0]<18>
MDB[63:0]<18>

12

2@

R217
56_0402_5%

2@

C372

Place as close to U8, U9 as possible

CLKB1
CLKB1#

2@

R219

56_0402_5%

470P_0402_50V7K

12

2@

C378

12

2@

R220
56_0402_5%

1

2

Place as close to U8, U9 as possible

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

Channel B External 128/64M DDR

HDL75 LA3041

22 60Thursday, July 28, 2005

1

0.1

5

4

3

2

1

LCD CONN NOTE : place need to ASIC

C940 4.7U_0805_10V4Z2@

1 2

ACES_87212-2200

D D

2@

Pop when with EXTERNAL graphics

C C

B B

ACES_87212-2200

1@

Pop when with INTERNAL graphics

Width: 60mils

LCDVCC

22

22

21

21

20

20

19

19

18

18

17

17

16

16

15

15

14

14

13

13

12

12

11

11

10

10

9

9

8

8

7

7

6

6

5

5

4

4

3

3

2

2

1

1

JP3

Width: 60mils

LCDVCC

22

22

21

21

20

20

19

19

18

18

17

17

16

16

15

15

14

14

13

13

12

12

11

11

10

10

9

9

8

8

7

7

6

6

5

5

4

4

3

3

2

2

1

1

JP35

EDID_CLK
EDID_DAT

LVDSBC- <17>
LVDSBC+ <17>
LVDSB2- <17>
LVDSB2+ <17>
LVDSB1- <17>
LVDSB1+ <17>
LVDSB0- <17>
LVDSB0+ <17>

LVDSAC- <17>
LVDSAC+ <17>
LVDSA2- <17>
LVDSA2+ <17>
LVDSA1- <17>
LVDSA1+ <17>
LVDSA0- <17>
LVDSA0+ <17>

LCD_DDCCLK <11>
LCD_DDCDATA <11>

LCD_BCLK- <11>
LCD_BCLK+ <11>
LCD_B2- <11>
LCD_B2+ <11>
LCD_B1- <11>
LCD_B1+ <11>
LCD_B0- <11>
LCD_B0+ <11>

LCD_ACLK- <11>
LCD_ACLK+ <11>
LCD_A2- <11>
LCD_A2+ <11>
LCD_A1- <11>
LCD_A1+ <11>
LCD_A0- <11>
LCD_A0+ <11>

L71 0_0603_5%
L72 0_0603_5%

EDID_CLK <17>
EDID_DAT <17>

LCDVCC

C943 4.7U_0805_10V4Z1@

1@

L73 0_0603_5%
L74 0_0603_5%

1@

LCDVCC

2@

1 2
1 2

2@

1 2

1 2
1 2

C395 0.1U_0402_16V4Z2@

1 2

+LCDVDD
+3VS

(DDC Power)

EDID_CLK

EDID_DAT

C944 0.1U_0402_16V4Z1@

1 2

+LCDVDD
+3VS

(DDC Power)

C941 47P_0402_50V8J2@

1 2

C942 47P_0402_50V8J2@

1 2

C917

2

G

+3VS

13

D

Q73
AO3400_SOT23

S

1

C918

0.1U_0402_16V4Z

2

1

C916

4.7U_0805_10V4Z

2

+LCDVDD

1

2

C919

4.7U_0805_10V4Z

+12VALW

12

+5VALW+LCDVDD

12

R795
220_0402_5%

13

D

Q75

2

G

2N7002_SOT23

S

2

ENVDD<17>

GM_ENVDD<11>

R249 0_0402_5%2@

R252 0_0402_5%1@

12

12

R796
10K_0402_5%

1 2

13

1 2

R798
47K_0402_5%

Q77
DTC124EK_SC59

2

R794
100K_0402_5%

13

Q76
DTC124EK_SC59

200K_0402_5%

R797

12

1000P_0402_50V7K

1

2

+3VS

JP4

1
2
3
4
5
6
7

ACES_85205-0700

A A

INV_PWR_SRC

1

2

C1131

1000P_0402_50V7K

C1132

1

1

2

C399

0.1U_0603_50V4Z

2

1000P_0402_50V7K

12

R390 0_0402_5%@

12

R264 0_0402_5%

1

C400
10U_1210_35V4Z

2

BIA_PWM <11>
INVT_PWM <40>

DAC_BRIG <40>

L41

1 2

0_0805_5%

12

R263

4.7K_0402_5%

DISPOFF#

1

C398

B+

2

2 1

D7
CH751H-40_SC76

2 1

D34
CH751H-40_SC76

1@

1000P_0402_50V7K

12

R1117 0_0402_5%

12

R1118 0_0402_5%

1@

BKOFF# <40>

BACKLITE_ON <11,17,40>

INVERTER CONN

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

LVDS Connector

HDL75 LA3041

23 60Thursday, July 28, 2005

1

0.1

5

TV_Y<17>

TV_C<17>

TV_CVBS<17>

D D

Y/G<11>
C/R<11>
COMP/B<11>

Pop when with internal graphics

C C

VGA_RED<17>

VGA_GRN<17>

VGA_BLU<17>

INTCRT_R<11>

INTCRT_G<11>

INTCRT_B<11>

2@

R276 0_0402_5%

2@

R277 0_0402_5%

2@

R278 0_0402_5%

1@

R282 0_0402_5%

1@

R283 0_0402_5%

1@

R284 0_0402_5%

R267 0_0402_5%2@

R268 0_0402_5%2@

R270 0_0402_5%2@

R274 0_0402_5%1@
R273 0_0402_5%1@
R271 0_0402_5% 1@

12

12

12

12

12

12

12

12

12

R269

2@

12
12
12

R95

150_0402_1%

1@

R279 75_0402_1% 2@

1 2

R280 75_0402_1%2@

1 2

R281 75_0402_1%

2@

1 2

12

R275

75_0402_1%

75_0402_1%

2@

12

R141

150_0402_1%

1@

R1128

0_0402_5%

Pop when with internal graphics

2@

DAT_DDC2<17>

B B

A A

CLK_DDC2<17>

HSYNC<17>

VSYNC<17>

INT_DAT_DDC2<11>

INT_CLK_DDC2<11>

INT_HSYNC<11>

INT_VSYNC<11>

12

R289 0_0402_5%

12

R290 0_0402_5%2@

2@

12

R291 0_0402_5%

2@

12

R292 0_0402_5%

1@

1 2

R294 0_0402_5%

1@

1 2

R295 0_0402_5%

1@

1 2

R296 39_0402_5%

1@

1 2

R298 39_0402_5%

Pop when with internal graphics

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETAR Y PRO PERT Y OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

12

12

R272

75_0402_1%

2@

12

12

R142

150_0402_1%

1@

12

0_0402_5%

2@

12

R1028

2.2K_0402_5%

G

S

1

2

1

2

0.1U_0402_16V4Z

4

INTCRT_R_F

INTCRT_G_F

INTCRT_B_F

12

R1123

1@

+3VS

2

Q10

2N7002_SOT23

13

D

+5VS

0.1U_0402_16V4Z
C417

+5VS

C420

4

C402

C403

C405

+3VS+3VS +2.5VS

12

12

R1124
0_0402_5%

1@

12

R1029

2.2K_0402_5%

5

P

A2Y

G

3

5

P

A2Y

G

3

82P_0402_50V8J

82P_0402_50V8J

82P_0402_50V8J

R1129
0_0402_5%

2@

S

L42

FLM1608081R8K_0603

1 2

CLOSE TO JTVOUT1

1

2

1

2

1

2

C407

+3VS

G

2

1

U10

OE#

74AHCT1G125GW_SOT353-5

1

U11

OE#

74AHCT1G125GW_SOT353-5

1 2

1 2

C408

22P_0402_50V8J

Q9

2N7002_SOT23

13

D

4

4

L43

L44

1

2

22P_0402_50V8J

FLM1608081R8K_0603

FLM1608081R8K_0603

1

2

1 2

1 2

1 2

1

C409

2

22P_0402_50V8J

L48

CHB1608B121_0603

1 2
1 2

L49

CHB1608B121_0603

12

R293
1K_0402_5%

3

1

C401

2

82P_0402_50V8J

1

C404

2

82P_0402_50V8J

1

C406

2

82P_0402_50V8J

L45

CHB1608B121_0603

L46
CHB1608B121_0603

L47
CHB1608B121_0603

+CRT_VCC

R285

1K_0402_5%

@

C415

33P_0402_50V8J

3

2

+3VS

+3VS

R286

1K_0402_5%

@

C416

33P_0402_50V8J

12

1

2

12

1

2

1

D11

DA204U_SC70

2

@

1

C410
10P_0402_50V8J

2

@

R287

2.2K_0402_5%

1@
1@
1@

3

1 2

12
12
12

R1190150_0603_1%
R1191150_0603_1%
R1192150_0603_1%

D12

DA204U_SC70

2

@

1

C411
10P_0402_50V8J

2

@

R288

2.2K_0402_5%

INTCRT_R_F
INTCRT_G_F
INTCRT_B_F

1

3

1 2

1

D8

DA204U_SC70

2

3

@

D13

DA204U_SC70

2

@

1

C412
10P_0402_50V8J

2

@

MSEN#<40>

1

3

1

D9

DA204U_SC70

2

3

@

1

D10

DA204U_SC70

2

3

@

C414

0.1U_0402_16V4Z

SVIDEO_Y
SVIDEO_C

SVIDEO_CVBS

+5VS

+CRT_VCC

D14

21

RB751V_SOD323

C413

0.01U_0402_16V7K

RED

VGA_DDC_DAT

GREEN

JVGA_HS

BLUE
CRT_VCC

JVGA_VS

VGA_DDC_CLK

1

2

1

2

1

TV-OUT Conn.

JP5

1
2
3
4
5
6
7

SUYIN_33007SR-07T1-C

CRT Conn.

JP6

6

11

1
7

12

2
8

13

3
9

14

4
10
15

5

FOX_DZ11A91-L7

DA204U

K1 A2

16
17

A1 K2

Title

Size Document Number Rev

2

Date: Sheet of

Compal Electronics, Inc.

TV_OUT and CRT

HDL75 LA3041

24 60Thursday, July 28, 2005

1

0.1

5

R301 10K_0402_5%2@

GPIO0<17>

D D

C C

GPIO1<17>

GPIO2<17>

GPIO3<17>

GPIO4<17>

GPIO5<17>

GPIO6<17>

ROM_ID1<17>

ROM_ID2<17>

ROM_ID3<17>

ROM_ID4<17>

1 2

R302 10K_0402_5%@

1 2

R303 10K_0402_5%@

1 2

R304 10K_0402_5%@

1 2

R305 10K_0402_5%@

1 2

R306 10K_0402_5%@

1 2

R307 10K_0402_5%@

1 2

R308 10K_0402_5%@

1 2

R309 10K_0402_5% @

1 2

R310 10K_0402_5%@

1 2

R311 10K_0402_5% @

1 2

4

+3VS

3

2

1

STRAPS PIN DESCRIPTION DEFAULT

CAL_BG_BACKUP

PLL_CAL_FORCE_EN

GPIO0

GPIO1

PCIE_MODE(1:0) GPIO(3:2)

CAL_OFF GPIO4

BYPASS_PLL

ICOMP

DEBUG_ACCESS

ROMIDCFG(3:0) 1011

GPIO5

GPIO6

GPIO8
ROMID

(4:1)

PCI-EXPRESS CURRENT CALIBRATION BANDCAP BACKUP
USING REFERENCE VOLTAGE FROM BANDGAP

PCI-EXPRESS FORCE PLL CALIBRATION DISABLED

PCI-EXPRESS 1:0A MODE

ENABLE TURN OFFPCI-EXPRESS IMPEDENCE/STRRENGTH
CALIBRATION

BYPASS PCI-EXPRESS PLL
NORMAL PCI-EXPRESS TRANSMITTER CURRENT

COMPENSATION

DEBUG SIGNALS NOT BROUGHT OUT

SERIAL M25P10 ROM

0

0

00

0

0

0

0

THERMAL SENSOR

DDR SPREAD SPECTRUM

Theraml Chip for M24P only

+3VS +3VS

12

2

12

R765
10K_0402_5%

@

Q68

MMBT3904_SOT23

@

3 1

AUXWIN <17>

+3VS

D+<17>

2@

1

B B

2200P_0402_50V7K

C419

D-<17>

2

2@

1 2

C418 0.1U_0402_16V4Z

U13

1

VCC

2
3

SMBCLK

DXP

SMBDATA

ALERT

DXN
THERM4GND

G781-1_SOP8

2@

8
7
6
5

SMBCLK
SMBDATA

R764

10K_0402_5%

@

SMBCLK <17>
SMBDATA <17>

ALERT#

Reserve for EC to monitor VGA temperature

SMBCLK
SMBDATA

A A

5

R394 0_0402_5%

1 2
1 2

R395 0_0402_5%

4

EC_SMC_1 <40,41,47>
EC_SMD_1 <40,41,47>

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

+3VS

2@

C422 0.1U_0402_16V4Z

1 2

U14

7

REF

VDD

1

MODOUT

XIN

8

XOUT

2

PD#

VSS

ASM3P1819N-SR_SO8

2@

2

5
4
3

NC

6

2@

1 2

R312 22_0402_5%

1 2

R313 10K_0402_5%@

1 2

R314 10K_0402_5%@

OSC_SPREAD <17>OSC_OUT<17>

Note: Pin3 Reserved for P1819 Spread Rate selection.

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

SS & Thermal Sensor

HDL75 LA3041

25 60Thursday, July 28, 2005

1

0.1

5

4

3

2

1

PCI_AD[0..31]<31,33,34,36,37>

+3VS

RP49

PCI_STOP#
PCI_SERR#
PCI_PERR#
PCI_REQ3#

PCI_PLOCK#
PCI_DEVSEL#
PCI_REQ1#
PCI_IRDY#

PCI_PIRQD#
PCI_PIRQB#
PCI_FRAME#
PCI_TRDY#

ICH_GPIO2_PIRQE#
PCI_REQ5#
PCI_REQ6#
ICH_GPIO2_PIRQF#

PCI_PIRQA#
PCI_REQ2#
PCI_REQ0#
PCI_PIRQC#

PCI_REQ4#
ICH_GPIO2_PIRQG#
ICH_GPIO2_PIRQH#

PCI_FRAME#<31,33,34,36,37>

PCI_PIRQA#<31>
PCI_PIRQB#<31>

+3VS

1 8
2 7
3 6
4 5

8.2K_0804_8P4R_5%
RP50

1 8
2 7
3 6
4 5

8.2K_0804_8P4R_5%

RP51

1 8
2 7
3 6
4 5

8.2K_0804_8P4R_5%

RP54

1 8
2 7
3 6
4 5

8.2K_0804_8P4R_5%

RP53

1 8
2 7
3 6
4 5

8.2K_0804_8P4R_5%
RP52

1 8
2 7
3 6
4 5

8.2K_0804_8P4R_5%

D D

C C

B B

PCI_AD0
PCI_AD1 PCI_GNT0#
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD6
PCI_AD7
PCI_AD8
PCI_AD9
PCI_AD10
PCI_AD11
PCI_AD12
PCI_AD13
PCI_AD14
PCI_AD15
PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20
PCI_AD21
PCI_AD22
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30
PCI_AD31

PCI_FRAME#

PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#

U16B

E2

AD[0]

E5

AD[1]

C2

AD[2]

F5

AD[3]

F3

AD[4]

E9

AD[5]

F2

AD[6]

D6

AD[7]

E6

AD[8]

D3

AD[9]

A2

AD[10]

D2

AD[11]

D5

AD[12]

H3

AD[13]

B4

AD[14]

J5

AD[15]

K2

AD[16]

K5

AD[17]

D4

AD[18]

L6

AD[19]

G3

AD[20]

H4

AD[21]

H2

AD[22]

H5

AD[23]

B3

AD[24]

M6

AD[25]

B2

AD[26]

K6

AD[27]

K3

AD[28]

A5

AD[29]

L1

AD[30]

K4

AD[31]

J3

FRAME#

Interrupt I/F

N2

PIRQ[A]#

L2

PIRQ[B]#

M1

PIRQ[C]#

L3

PIRQ[D]#

AC5

SATA[1]RXN/RSVD[1]

AD5

SATA[1]RXP/RSVD[2]

AF4

SATA[1]TXN/RSVD[3]

AG4

SATA[1]TXP/RSVD[4]

AC9

SATA[3]RXN/RSVD[5]

AD9

SATA[3]RXP/RSVD[6]

AF8

SATA[3]TXN/RSVD[7]

AG8

SATA[3]TXP/RSVD[8]

U3

TP[3]/RSVD[9]

ICH6_BGA609

PCI

REQ[4]#/GPI[40]

GNT[4]#/GPO[48]

REQ[5]#/GPI[1]

GNT[5]#/GPO[17]

REQ[6]#/GPI[0]

GNT[6]#/GPO[16]

DEVSEL#

PIRQ[E]#/GPI[2]
PIRQ[F]#/GPI[3]

PIRQ[G]#GPI[4]

PIRQ[H]#/GPI[5]

RESERVED

REQ[0]#
GNT[0]#
REQ[1]#
GNT[1]#
REQ[2]#
GNT[2]#
REQ[3]#
GNT[3]#

C/BE[0]#
C/BE[1]#
C/BE[2]#
C/BE[3]#

IRDY#

PAR

PCIRST#

PERR#

PLOCK#

SERR#
STOP#
TRDY#

PLTRST#

PCICLK

PME#

L5
C1
B5
B6
M5
F1
B8
C8
F7
E7
E8
F6
B7
D8

J6
H6
G4
G2

A3
E1
R2
C3
E3
C5
G5
J1
J2

R5
G6
P6

D9
C7
C6
M3

PCI_REQ0#
PCI_REQ1#

PCI_GNT1#
PCI_REQ2#

PCI_REQ3#
PCI_GNT3#
PCI_REQ4#
PCI_GNT4#
PCI_REQ5#
PCI_GNT5#
PCI_REQ6#

PCI_C_BE0#
PCI_C_BE1#

PCI_C_BE2#

PCI_C_BE3#
PCI_IRDY#

PCI_PAR
PCI_PCIRST#
PCI_DEVSEL#
PCI_PERR#
PCI_PLOCK#
PCI_SERR#
PCI_STOP#
PCI_TRDY#

PCI_PLTRST#

CLK_PCI_ICH

ICH_GPIO2_PIRQE#
ICH_GPIO2_PIRQF#
ICH_GPIO2_PIRQG#
ICH_GPIO2_PIRQH#

PCI_REQ0# <33>
PCI_GNT0# <33>

PCI_REQ1# <36>
PCI_GNT1# <36>

PCI_REQ2# <31>
PCI_GNT2# <31>

PCI_REQ3# <34>
PCI_GNT3# <34>

PCI_REQ4# <37>
PCI_GNT4# <37>

PCI_C_BE0# <31,33,34,36,37>
PCI_C_BE1# <31,33,34,36,37>
PCI_C_BE2# <31,33,34,36,37>
PCI_C_BE3# <31,33,34,36,37>

PCI_IRDY# <31,33,34,36,37>

PCI_PAR <31,33,34,36,37>

PCI_DEVSEL# <31,33,34,36,37>

PCI_PERR # <31,33,34,36,37>

PCI_SERR# <31,34,36,37>
PCI_STOP# <31,33,34,36,37>
PCI_T R D Y # <31,33,34,36,37>

CLK_PCI_ICH <16>

ICH_GPIO2_PIRQE# <33>
ICH_GPIO2_PIRQF# <34>
ICH_GPIO2_PIRQG# <36,37>
ICH_GPIO2_PIRQH# <36,37>

Internal Pull-up.
Sample high destination is LPC.

PCI_PCIRST#

PCI_PLTRST#

PCI_GNT5#

PCI_PLTRST#

12

R341
0_0402_5%@

+3V

1

A

2

B

+3V

4

A

5

B

+3V

10

A

9

B

+3V

13

A

12

B

C945

12

0.1U_0402_16V4Z

14

U17A

P

3

O

G

74VHC08MTC_TSSOP14

7

14

U17B

P

6

O

G

74VHC08MTC_TSSOP14

7

14

U17C

P

8

O

G

74VHC08MTC_TSSOP14

7

14

U17D

P

11

O

G

74VHC08MTC_TSSOP14

7

PCI_RST#

PLTRST#

PLTRST_ICH#

Place closely pin G6

8.2P_0402_50V @

PCI_RST# <31,33,36,37,42>

PLTRST# <9,28,34,38,40,45>

PLTRST_ICH# <17>ICH_PME# <31,33,34,36,37,40,41>

CLK_PCI_ICH

R339

10_0402_5%@

C423

1 2
1

2

A A

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

ICH6(1/4)

HDL75 LA3041

26 60Thursday, July 28, 2005

1

0.1

5

C424

12P_0402_50V8J

12

Y1

+RTCVCC

4

OUT

1

IN

32.768KHZ_12.5PF_6H03200468

R344
180K_0402_5%

J7

C426

0.1U_0402_16V4Z

1 2

Package

9.6X4.06 mm

C425

12P_0402_50V8J

12

D D

+RTCVCC

12

R354
1M_0402_5%

SM_INTRUDER#

NC
NC

1 2

21

3MM

ICH_RTCX1

3
2

ICH_RTCX2

+RTCVCC

R343

10M_0402_5%

12

1 2

R1178
330K_0402_5%

@

INTVRMEN

ENABLE INTEGRATED VCCSUS1.5 VRMHIGH

DISABLE INTEGRATED VCCSUS1.5 VRM

LOW

1 2
1 2

R353

1 2

33_0402_5%

R1182

R34833_0402_5%
R34933_0402_5%

12

ICH_AC_BITCLK<38,43>

C C

+3VS

R1060

4.7K_0402_5%

1 2

IDE_DIORDY

ICH_SYNC_MDC<38>
ICH_RST_MDC#<38>

ICH_AC_SDIN0<43>
ICH_AC_SDIN1<38>

ICH_SDOUT_MDC<38>

ICH_AC_BITCLK

Place closely pin C10

ICH_AC_BITCLK

12

R355
10_0402_5%

B B

@

2

C427
10P_0402_50V8J

1

@

IDE_DIORDY<30>

IDE_IRQ<30,45>
IDE_DDACK#<30>
IDE_DIOW#<30>
IDE_DIOR#<45>

1 2

ICH_RTCRST#
SM_INTRUDER#

R1179

0_0402_5%

0_0402_5%

ICH_AC_SYNC_R
ICH_AC_RST_R#
ICH_AC_SDIN0

ICH_AC_SDIN1

ICH_AC_SDOUT_R

R356

24.9_0603_1%

IDE_DIORDY
IDE_IRQ
IDE_DDACK#
IDE_DIOW#
IDE_DIOR#

4

U16A

Y1

Y2
AA2
AA3

AA5

D12
B12
D11

F13

1 2

F12
B11
E12

E11
C13

C12
C11
E13

C10

B9

A10

F11

F10
B10

C9

AC19

AE3
AD3
AG2
AF2

AD7
AC7
AF6
AG6

AC2
AC1

AG11

AF11

AF16
AB16
AB15
AC14
AE16

ICH6_BGA609

RTCX1
RTCX2

RTCRST#
INTRUDER#

INTVRMEN

EE_CS
EE_SHCLK
EE_DOUT
EE_DIN

LAN_CLK
LAN_RSTSYNC
LANRXD[0]

LANRXD[1]
LANRXD[2]

LANTXD[0]
LANTXD[1]
LANTXD[2]

ACZ_BIT_CLK
ACZ_SYNC

ACZ_RST#
ACZ_SDIN[0]

ACZ_SDIN[1]
ACZ_SDIN[2]

ACZ_SDO

SATALED#

SATA[0]RXN
SATA[0]RXP
SATA[0]TXN
SATA[0]TXP

SATA[2]RXN
SATA[2]RXP
SATA[2]TXN
SATA[2]TXP

SATA_CLKN
SATA_CLKP

SATARBIAS#
SATARBIAS

IORDY
IDEIRQ
DDACK#
DIOW#
DIOR#

RTC

LAD[0]/FWH[0]
LAD[1]/FWH[1]
LAD[2]/FWH[2]
LAD[3]/FWH[3]

LPC

LDRQ[1]#/GPI[41]

LFRAME#/FWH[4]

LAN

CPU

DPRSLP#/TP[4]

DPSLP#/TP[2]

CPUPWRGD/GPO[49]

THRMTRIP#

SATAAC-97/AZALIA

LDRQ[0]#

A20GATE

A20M#

CPUSLP#

FERR#

IGNNE#

INIT3_3V#

INIT#
INTR

RCIN#

SMI#

STPCLK#

DA[0]
DA[1]
DA[2]

DCS1#
DCS3#

DD[0]
DD[1]
DD[2]
DD[3]

PIDE

DD[4]
DD[5]
DD[6]
DD[7]
DD[8]

DD[9]
DD[10]
DD[11]
DD[12]
DD[13]
DD[14]
DD[15]

DDREQ

NMI

P2
N3
N5
N4

N6
P4

P3

AF22
AF23

AE27
AE24

AD27
AF24
AG25
AG26

AE22
AF27
AG24

AD23
AF25

AG27
AE26
AE23

AC16
AB17
AC17

AD16
AE17

AD14
AF15
AF14
AD12
AE14
AC11
AD11
AB11
AE13
AF13
AB12
AB13
AC13
AE15
AG15
AD13

AB14

3

LPC_LAD0
LPC_LAD1
LPC_LAD2
LPC_LAD3

LPC_LDRQ1#
LPC_LFRAME#

H_CPUSLP_R#

DPRSLP#

FERR#

THRMTRIP_ICH#

IDE_DA0
IDE_DA1
IDE_DA2

IDE_DCS1#
IDE_DCS3#

IDE_DD0
IDE_DD1
IDE_DD2
IDE_DD3
IDE_DD4
IDE_DD5
IDE_DD6
IDE_DD7
IDE_DD8
IDE_DD9
IDE_DD10
IDE_DD11
IDE_DD12
IDE_DD13
IDE_DD14
IDE_DD15

IDE_DDREQ

LPC_LAD[0..3] <40,42>

LPC_LDRQ1# <42>

LPC_LFRAME# <40,42>

R345 0_0402_5% @
R346 0_0402_5%

R1059 56_0402_5%

R351 56_0402_5%

12
12

1 2

1 2

IDE_DA[0..2] <30>

IDE_DCS1# <30,45>
IDE_DCS3# <30,45>

IDE_DD[0..15] <30>

IDE_DDREQ <30>

2

Note :
R345 Populte zero ohm for Dothan-A,
no stuff for Dothan-B.
R346 no stuff for Dothan-A, Populte zero ohm for
Dothan-B.
Stuff R352 for Dothan B, no stuff R352 for Dothan A

EC_A20GATE
H_A20M#

H_CPUSLP#
H_DPRSLP#

H_DPSLP#

H_CPUPWRGD
H_IGNNE#
H_INIT#

H_INTR

EC_RCIN#
H_NMI

H_SMI#
H_STPCLK#

EC_A20GATE <40>

H_A20M# <5>
H_CPUSLP# <5,9>
H_DPRSLP# <5>

H_DPSLP# <5>
H_FERR# <5>
H_CPUPWRGD <5>
H_IGNNE# <5>
H_INIT# <5>

H_INTR <5>

EC_RCIN# <40>

H_NMI <5>
H_SMI# <5>

H_STPCLK# <5>
H_THERMTRIP# <5,8,9>

H_FERR#

H_DPRSLP#

1

56_0402_5%

56_0402_5%

R350

R352

+VCCP

12

12

+3VS

R357

8.2K_0402_5%

ICH_SDOUT_AUDIO<43>

A A

ICH_SYNC_AUDIO<43>

ICH_RST_AUDIO#<43>

5

IDE_IRQ

12

R358
33_0402_5%

1 2

R359
33_0402_5%

1 2

R360
33_0402_5%

1 2

ICH_AC_SDOUT_R

ICH_AC_SYNC_R

ICH_AC_RST_R#

BATT1

ML1220T13RE

4

+RTCVCC

12

RTCPWR

20mil

1

2

3

D25
BAS40-04_SOT23

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

20mil

CHGRTC

3

Title

Size Document Number Rev

2

Date: Sheet of

Compal Electronics, Inc.

ICH6(2/4)

HDL75 LA3041

27 60Thursday, July 28, 2005

1

0.1

5

R362

2.2K_0402_5%

45
36
27
18

45
36
27
18

+3VALW

12

R363

10K_0402_5%

LINKALERT#

EC_SMI#

GPI11

SIRQ

GPI7

PM_CLKRUN#

ICH_THRM#

MCH_SYNC#

SYS_RESET#

PM_BATLOW#

ICH_PCIE_WAKE#

12

12

R364

10K_0402_5%

ICH_SMLINK0
ICH_SMLINK1
ICH_SMBDATA
ICH_SMBCLK

+3VALW

12

D D

ICH_SMBDATA<16,38>

ICH_SMBCLK<16,38>

+3VALW

+3VS

+3VS

C C

+3VALW

R361

2.2K_0402_5%

RP55

10K_0804_8P4R_5%

RP56

10K_0804_8P4R_5%

R376
10K_0402_5%

1 2

R379

8.2K_0402_5%

1 2

R380
680_0402_5%

1 2

(PCI Express Wake Event)

B B

+3VS

R382

1 2

1K_0402_5%

@

PM_DPRSLPVR<54>

12

R386

100K_0402_5%

A A

System can't boot issue
May need pulldown for DPRSLPVR in case

the ICH6m does not set this value in time
for boot.

5

EXPRESSCARD_RST#<38>

4

ICH_PCIE_WAKE#<38,40>

4

R365

33_0402_5%

SPKR<44>

PM_BMBUSY#<9>

EC_SMI#<40>
ACIN<40,47,50>
EC_LID_OUT#<40>

EC_SCI#<40>

PM_STP_PCI#<16>

PM_STP_CPU#<16,54>

PLTRST_VGA#<17>
IDERST_HD#<45>
IDERST_CD#<45>

EC_FLASH#<41>
PM_CLKRUN#<34,36,37,40,42>

SIRQ<31,40,42>
EC_THRM#<40>
VGATE<9,16,54>
CLK_ICH_14M<16>
CLK_ICH_48M<16>

EC_SLP_S3#< 40>
EC_SLP_S4#< 40>
EC_SLP_S5#< 40>

ICH_PWRGD<38,40>

PM_BATLOW#<40>
EC_PWRBTN#<40>
PLTRST#<9,26,34,38,40,45>
EC_RSMRST#<40>

12

T24PAD

T12PAD

3

+3VALW

12

R1061

10K_0402_5%

ICH_RI#

ICH_SMBCLK
ICH_SMBDATA
LINKALERT#
ICH_SMLINK0
ICH_SMLINK1
MCH_SYNC#
SPKR

ICH_SUS_RESET

SYS_RESET#
PM_BMBUSY#
GPI7

EC_SMI#

R1183 0_0402_5%

ACIN

EC_LID_OUT#

EC_SCI#
PM_STP_PCI#

PM_STP_CPU#

PLTRST_VGA#
IDERST_HD#
IDERST_CD#
EC_FLASH#

PM_CLKRUN#

EXPRESSCARD_RST#

ICH_PCIE_WAKE#

SIRQ

D29

VGATE
CLK_ICH_14M USB_OC3#
CLK_ICH_48M

ICH_SUSCLK

EC_SLP_S3#

EC_SLP_S4#

EC_SLP_S5#
ICH_PWRGD
PM_DPRSLPVR
PM_BATLOW#
EC_PWRBTN#
PLTRST#
EC_RSMRST#

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

@

R1188 0_0402_5%

ICH_THRM#

21

RB751V_SOD323

R1194 0_0402_5%

12

12

10K_0402_5%

R384

12

12

GPI11

T2

AF17
AE18
AF18
AG18

Y4

W5

Y5

W4

U6

AG21

F8

W3

U2
AD19
AE19

R1

W6

M2

R6
AC21
AB21
AD22

AD20
AD21

V3

P5

R3

T3
AF19
AF20
AC18

U5
AB20
AC20
AF21

E10
A27

V6

T4

T5

T6

AA1

AE20

V2

U1

V5

Y3

12

10K_0402_5%

R385

U16C

RI#
SATA[0]GP/GPI[26]

SATA[1]GP/GPI[29]
SATA[2]GP/GPI[30]
SATA[3]GP/GPI[31]

SMBCLK
SMBDATA
LINKALERT#
SMLINK[0]
SMLINK[1]
MCH_SYNC#
SPKR

SUS_STAT#/LPCPD#
SYS_RESET#
BM_BUSY#/GPI[6]
GPI[7]

GPI[8]
SMBALERT#/GPI[11]
GPI[12]

GPI[13]
STP_PCI#/GPO[18]
GPO[19]
STP_CPU#/GPO[20]

GPO[21]
GPO[23]

GPIO[24]
GPIO[25]

GPIO[27]
GPIO[28]
CLKRUN#/GPIO[32]
GPIO[33]
GPIO[34]

WAKE#
SERIRQ
THRM#
VRMPWRGD
CLK14
CLK48
SUSCLK
SLP_S3#

SLP_S4#
SLP_S5#

PWROK
DPRSLPVR/TP[1]
BATLOW#/TP[0]
PWRBTN#
LAN_RST#
RSMRST#

ICH6_BGA609

3

PERn[1]
PERp[1]

PETn[1]
PETp[1]

PERn[2]
PERp[2]

PETn[2]
PETp[2]

PERn[3]
PERp[3]

PETn[3]
PETp[3]

GPIO

PERn[4]
PERp[4]

PETn[4]

PCI-EXPRESSDIRECT MEDIA INTERFACE

PETp[4]

DMI[0]RXN

DMI[0]RXP
DMI[0]TXN
DMI[0]TXP

DMI[1]RXN

DMI[1]RXP
DMI[1]TXN
DMI[1]TXP

DMI[2]RXN

DMI[2]RXP
DMI[2]TXN
DMI[2]TXP

DMI[3]RXN

DMI[3]RXP
DMI[3]TXN
DMI[3]TXP

DMI_CLKN

DMI_CLKP

DMI_ZCOMP

DMI_IRCOMP

OC[4]#/GPI[9]
OC[5]#/GPI[10]
OC[6]#/GPI[14]
OC[7]#/GPI[15]

OC[0]#
OC[1]#
OC[2]#
OC[3]#

USBP[0]N
USBP[0]P
USBP[1]N

CLOCK

USBP[1]P
USBP[2]N
USBP[2]P
USBP[3]N
USBP[3]P

USB

USBP[4]N
USBP[4]P
USBP[5]N
USBP[5]P
USBP[6]N
USBP[6]P
USBP[7]N

POWER MGT

USBP[7]P

USBRBIAS#

USBRBIAS

H25
H24
G27
G26

K25
K24
J27
J26

M25
M24
L27
L26

P24
P23
N27
N26

T25
T24
R27
R26

V25
V24
U27
U26

Y25
Y24
W27
W26

AB24
AB23
AA27
AA26

AD25
AC25

F24
F23
C23

D23
C25
C24

C27
B27
B26
C26

C21
D21
A20
B20
D19
C19
A18
B18
E17
D17
B16
A16
C15
D15
A14
B14

A22
B22

PCIE_RXN0
PCIE_RXP0

PCIE_C_TXP0

DMI_RXN0
DMI_RXP0
DMI_TXN0
DMI_TXP0

DMI_RXN1
DMI_RXP1
DMI_TXN1
DMI_TXP1

DMI_RXN2
DMI_RXP2
DMI_TXN2
DMI_TXP2

DMI_RXN3
DMI_RXP3
DMI_TXN3
DMI_TXP3

CLK_PCIE_ICH#
CLK_PCIE_ICH

DMI_IRCOMP
USB_OC4#

USB_OC5#
USB_OC6#
USB_OC7#

USB_OC0#
USB_OC1#
USB_OC2#

USBP0­USBP0+
USBP1­USBP1+

USBP3­USBP3+
USBP4­USBP4+

USBP6­USBP6+

USBRBIAS

2

C1087 0.1U_0402_16V4Z

1 2

R377 24.9_0603_1%

22.6_0603_1%

2

1 2

@

@

1 2

USB_OC4# <39>
USB_OC6# <39>

USB_OC0# <39>
USB_OC1# <38>

USB_OC3# <39>

1 2

R383

C1088

0.1U_0402_16V4Z

DMI_RXN0 <9>
DMI_RXP0 <9>
DMI_TXN0 <9>
DMI_TXP0 <9>

DMI_RXN1 <9>
DMI_RXP1 <9>
DMI_TXN1 <9>
DMI_TXP1 <9>

DMI_RXN2 <9>
DMI_RXP2 <9>
DMI_TXN2 <9>
DMI_TXP2 <9>

DMI_RXN3 <9>
DMI_RXP3 <9>
DMI_TXN3 <9>
DMI_TXP3 <9>

CLK_PCIE_ICH# <16>
CLK_PCIE_ICH <16>

+1.5VS

USBP0- <39>
USBP0+ <39>
USBP1- <38>
USBP1+ <38>

USBP3- <39>
USBP3+ <39>
USBP4- <39>
USBP4+ <39>

USBP6- <39>
USBP6+ <39>

1

PCIE_RXN0 <38>

PCIE_TXN0PCIE_C_TXN0
PCIE_TXP0

PCIE_RXP0 <38>
PCIE_TXN0 <38>
PCIE_TXP0 <38>

Place closely pin A27Place closely pin E10

CLK_ICH_14M CLK_ICH_48M

12

R366
10_0402_5%

@

1

C430

@

2

4.7P_0402_50V8C

USB_OC2#
USB_OC1#
USB_OC5#
USB_OC7#

USB_OC3#

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

ICH6(3/4)

HDL75 LA3041

12

1

2

RP29

4 5
3 6
2 7
1 8

10K_1206_8P4R_5%

R1207

12

10K_0402_5%

1

R367
10_0402_5%

@

C431

4.7P_0402_50V8C

@

+3VALW

+3VALW

28 60Thursday, July 28, 2005

0.1

5

+1.5VS

ICH_V5REF_RUN

R1023

10_0402_5%

U69 APL5301-15DC_3P

Vin2Vout

2

C439

0.1U_0402_16V4Z

@

1

ICH_V5REF_SUS

2

C449

0.1U_0402_16V4Z

@

1

+5VALW +3VALW

1 2

1 2

1

2

3

GND

1

2

1

D26

1SS355_SOD323

ICH_V5REF_SUS

C946

0.1U_0402_16V4Z

Near PIN F21

R12 0_0402_5%

1 2

2

C438

D D

C C

1U_0603_10V4Z

1

2

C448
1U_0603_10V4Z

1

+3VALW

1

C1126

0.1U_0402_16V4Z

2

L51
0_0805_5%

C440

0.1U_0402_16V4Z

@

1 2

10_0402_5%

+1.5VALW

1

2

+1.5VS_L

C433

220U_D_4VM

R1024

1 2

Near PIN AG5

C1127

0.1U_0402_16V4Z

1

2

Near PIN AG9

B B

+3VS

C464

0.1U_0402_16V4Z

Near PIN
E26, E27

R389

+1.5VS

A A

1 2

1_0603_1%

L52

CHB1608U301_0603

1 2

2

C477

1

0.1U_0402_16V4Z

C478

1

2

0.01U_0402_16V7K

ICH6_VCCPLL

4

Near PIN F27(C968),
P27(C949), AB27(C950)

2

+

+3VS+5VCD

+1.5VS

+1.5VS

2

1

1SS355_SOD323

@

1 2

1

C948

0.1U_0402_16V4Z

2

Near PIN A8

+1.5VS

2

C434

C435

1

1

0.1U_0402_16V4Z

D27

ICH_V5REF_RUN

2

C465

1

0.1U_0402_16V4Z

C460

C462

Near PIN AE1

+3VALW

2

C471

1

0.1U_0402_16V4Z

Near PIN A17

2

C436

1

0.1U_0402_16V4Z

2

1

0.1U_0402_16V4Z

2

1

0.1U_0402_16V4Z

ICH6_VCCPLL

+3VS

+3VS

+3VALW

2

C472

1

AA22
AA23
AA24
AA25
AB25
AB26
AB27

0.1U_0402_16V4Z

AC27

AG10

0.1U_0402_16V4Z

U16E

VCC1_5[1]
VCC1_5[2]
VCC1_5[3]
VCC1_5[4]
VCC1_5[5]
VCC1_5[6]
VCC1_5[7]

F25

VCC1_5[8]

F26

VCC1_5[9]

F27

VCC1_5[10]

G22

VCC1_5[11]

G23

VCC1_5[12]

G24

VCC1_5[13]

G25

VCC1_5[14]

H21

VCC1_5[15]

H22

VCC1_5[16]

J21

VCC1_5[17]

J22

VCC1_5[18]

K21

VCC1_5[19]

K22

VCC1_5[20]

L21

VCC1_5[21]

L22

VCC1_5[22]

M21

VCC1_5[23]

M22

VCC1_5[24]

N21

VCC1_5[25]

N22

VCC1_5[26]

N23

VCC1_5[27]

N24

VCC1_5[28]

N25

VCC1_5[29]

P21

VCC1_5[30]

P25

VCC1_5[31]

P26

VCC1_5[32]

P27

VCC1_5[33]

R21

VCC1_5[34]

R22

VCC1_5[35]

T21

VCC1_5[36]

T22

VCC1_5[37]

U21

VCC1_5[38]

U22

VCC1_5[39]

V21

VCC1_5[40]

V22

VCC1_5[41]

W21

VCC1_5[42]

W22

VCC1_5[43]

Y21

VCC1_5[44]

Y22

VCC1_5[45]

AA6

VCC1_5[46]

AB4

VCC1_5[47]

AB5

VCC1_5[48]

AB6

VCC1_5[49]

AC4

VCC1_5[50]

AD4

VCC1_5[51]

AE4

VCC1_5[52]

AE5

VCC1_5[53]

AF5

VCC1_5[54]

AG5

VCC1_5[55]

AA7

VCC1_5[56]

AA8

VCC1_5[57]

AA9

VCC1_5[58]

AB8

VCC1_5[59]

AC8

VCC1_5[60]

AD8

VCC1_5[61]

AE8

VCC1_5[62]

AE9

VCC1_5[63]

AF9

VCC1_5[64]

AG9

VCC1_5[65]
VCCDMIPLL

E26

VCC3_3[1]

AE1

VCCSATAPLL
VCC3_3[22]

A13

VCCLAN3_3/VCCSUS3_3[1]

F14

VCCLAN3_3/VCCSUS3_3[2]

G13

VCCLAN3_3/VCCSUS3_3[3]

G14

VCCLAN3_3/VCCSUS3_3[4]

A11

VCCSUS3_3[1]

U4

VCCSUS3_3[2]

V1

VCCSUS3_3[3]

V7

VCCSUS3_3[4]

W2

VCCSUS3_3[5]

Y7

VCCSUS3_3[6]

A17

VCCSUS3_3[7]

B17

VCCSUS3_3[8]

C17

VCCSUS3_3[9]

F18

VCCSUS3_3[10]

G17

VCCSUS3_3[11]

G18

VCCSUS3_3[12]

ICH6_BGA609

3

COREIDE

PCIE

PCIUSB

VCCSUS1_5[3]
VCCSUS1_5[2]

VCCSUS1_5[1]

SATA

USB CORE

PCI/IDE RBP

V5REF_SUS

VCCUSBPLL

VCCSUS3_3[20]

VCCLAN1_5/VCCSUS1_5[2]
VCCLAN1_5/VCCSUS1_5[1]

V_CPU_IO[3]
V_CPU_IO[2]
V_CPU_IO[1]

VCCSUS3_3[19]
VCCSUS3_3[18]
VCCSUS3_3[17]
VCCSUS3_3[16]
VCCSUS3_3[15]
VCCSUS3_3[14]
VCCSUS3_3[13]

VCC1_5[98]
VCC1_5[97]
VCC1_5[96]
VCC1_5[95]
VCC1_5[94]
VCC1_5[93]
VCC1_5[92]
VCC1_5[91]
VCC1_5[90]
VCC1_5[89]
VCC1_5[88]
VCC1_5[87]
VCC1_5[86]
VCC1_5[85]
VCC1_5[84]
VCC1_5[83]
VCC1_5[82]
VCC1_5[81]
VCC1_5[80]
VCC1_5[79]

VCC3_3[21]
VCC3_3[20]
VCC3_3[19]
VCC3_3[18]
VCC3_3[17]
VCC3_3[16]
VCC3_3[15]
VCC3_3[14]
VCC3_3[13]
VCC3_3[12]

VCC3_3[11]
VCC3_3[10]

VCC3_3[9]
VCC3_3[8]
VCC3_3[7]
VCC3_3[6]
VCC3_3[5]
VCC3_3[4]
VCC3_3[3]
VCC3_3[2]

VCC1_5[78]
VCC1_5[77]
VCC1_5[76]
VCC1_5[75]
VCC1_5[74]
VCC1_5[73]
VCC1_5[72]
VCC1_5[71]
VCC1_5[70]
VCC1_5[69]
VCC1_5[68]

VCC1_5[67]

VCC2_5[4]
VCC2_5[2]

V5REF[2]
V5REF[1]

VCCRTC

F9
U17
U16
U14
U12
U11
T17
T11
P17
P11
M17
M11
L17
L16
L14
L12
L11
AA21
AA20
AA19

AA10
AG19
AG16
AG13
AD17
AC15
AA17
AA15
AA14
AA12

P1
M7
L7
L4
J7
H7
H1
E4
B1
A6

U7
R7

G19
G20

F20
E24
E23
E22
E21
E20
D27
D26
D25
D24

G8
AB18

P7
AA18

A8
F21
A25

A24
AB3
G11

G10
AG23

AD26
AB22

G16
G15
F16
F15
E16
D16
C16

+1.5VS

2

C446

1

0.1U_0402_16V4Z

2

C452

1

0.1U_0402_16V4Z

+1.5VALW

1

2

C461

0.1U_0402_16V4Z

+1.5VS

ICH_V5REF_RUN

ICH_V5REF_SUS

+1.5VS
+3VALW

+RTCVCC

+1.5VS

+VCCP

1

2

C468

0.1U_0402_16V4Z

2

C447

1

0.1U_0402_16V4Z

2

C453

C454

1

0.1U_0402_16V4Z

2

1

C458

Near PIN U7

Near PIN AB18

Near PIN AG23

+3VS

+3VS

Near PIN
AG13, AG16

+3VS

2

1

0.1U_0402_16V4Z

Near PIN
A2-A6, D1-H1

+1.5VALW

1

2

C459

0.1U_0402_16V4Z

0.1U_0402_16V4Z

+2.5VS

1

2

C463

0.01U_0402_16V7K

C469

0.1U_0402_16V4Z

1 2

C473

1 2

0.1U_0402_16V4Z

Near PIN AG10

2

+1.5VS

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z@

0.01U_0402_16V7K

Near PIN A25

0.01U_0402_16V7K

Near PIN AA19

+3VALW

C432

1 2

C437

1 2

C441

1 2

C442

1 2

C443

1 2

C444

1 2

C445

1 2

C450

1 2

C451

1 2

C455

1 2

C947

1 2

C456

1 2

C457

1 2

C466

0.1U_0402_16V4Z

1 2

C467

0.1U_0402_16V4Z

1 2

C470

0.1U_0402_16V4Z

1 2

C474

0.1U_0402_16V4Z

1 2

Near PIN A24

1

U16D

E27

VSS[172]

Y6

VSS[171]

Y27

VSS[170]

Y26

VSS[169]

Y23

VSS[168]

W7

VSS[167]

W25

VSS[166]

W24

VSS[165]

W23

VSS[164]

W1

VSS[163]

V4

VSS[162]

V27

VSS[161]

V26

VSS[160]

V23

VSS[159]

U25

VSS[158]

U24

VSS[157]

U23

VSS[156]

U15

VSS[155]

U13

VSS[154]

T7

VSS[153]

T27

VSS[152]

T26

VSS[151]

T23

VSS[150]

T16

VSS[149]

T15

VSS[148]

T14

VSS[147]

T13

VSS[146]

T12

VSS[145]

T1

VSS[144]

R4

VSS[143]

R25

VSS[142]

R24

VSS[141]

R23

VSS[140]

R17

VSS[139]

R16

VSS[138]

R15

VSS[137]

R14

VSS[136]

R13

VSS[135]

R12

VSS[134]

R11

VSS[133]

P22

VSS[132]

P16

VSS[131]

P15

VSS[130]

P14

VSS[129]

P13

VSS[128]

P12

VSS[127]

N7

VSS[126]

N17

VSS[125]

N16

VSS[124]

N15

VSS[123]

N14

VSS[122]

N13

VSS[121]

N12

VSS[120]

N11

VSS[119]

N1

VSS[118]

M4

VSS[117]

M27

VSS[116]

M26

VSS[115]

M23

VSS[114]

M16

VSS[113]

M15

VSS[112]

M14

VSS[111]

M13

VSS[110]

M12

VSS[109]

L25

VSS[108]

L24

VSS[107]

L23

VSS[106]

L15

VSS[105]

L13

VSS[104]

K7

VSS[103]

K27

VSS[102]

K26

VSS[101]

K23

VSS[100]

K1

VSS[99]

J4

VSS[98]

J25

VSS[97]

J24

VSS[96]

J23

VSS[95]

H27

VSS[94]

H26

VSS[93]

H23

G21
G12

G9
G7

G1

VSS[92]
VSS[91]
VSS[90]
VSS[89]
VSS[88]
VSS[87]

+RTCVCC

C475

0.1U_0402_16V4Z

GROUND

ICH6_BGA609

1

2

VSS[86]
VSS[85]
VSS[84]
VSS[83]
VSS[82]
VSS[81]
VSS[80]
VSS[79]
VSS[78]
VSS[77]
VSS[76]
VSS[75]
VSS[74]
VSS[73]
VSS[72]
VSS[71]
VSS[70]
VSS[69]
VSS[68]
VSS[67]
VSS[66]
VSS[65]
VSS[64]
VSS[63]
VSS[62]
VSS[61]
VSS[60]
VSS[59]
VSS[58]
VSS[57]
VSS[56]
VSS[55]
VSS[54]
VSS[53]
VSS[52]
VSS[51]
VSS[50]
VSS[49]
VSS[48]
VSS[47]
VSS[46]
VSS[45]
VSS[44]
VSS[43]
VSS[42]
VSS[41]
VSS[40]
VSS[39]
VSS[38]
VSS[37]
VSS[36]
VSS[35]
VSS[34]
VSS[33]
VSS[32]
VSS[31]
VSS[30]
VSS[29]
VSS[28]
VSS[27]
VSS[26]
VSS[25]
VSS[24]
VSS[23]
VSS[22]
VSS[21]
VSS[20]
VSS[19]
VSS[18]
VSS[17]
VSS[16]
VSS[15]
VSS[14]
VSS[13]
VSS[12]
VSS[11]
VSS[10]

VSS[9]
VSS[8]
VSS[7]
VSS[6]
VSS[5]
VSS[4]
VSS[3]
VSS[2]
VSS[1]

F4
F22
F19
F17
E25
E19
E18
E15
E14
D7
D22
D20
D18
D14
D13
D10
D1
C4
C22
C20
C18
C14
B25
B24
B23
B21
B19
B15
B13
AG7
AG3
AG22
AG20
AG17
AG14
AG12
AG1
AF7
AF3
AF26
AF12
AF10
AF1
AE7
AE6
AE25
AE21
AE2
AE12
AE11
AE10
AD6
AD24
AD2
AD18
AD15
AD10
AD1
AC6
AC3
AC26
AC24
AC23
AC22
AC12
AC10
AB9
AB7
AB2
AB19
AB10
AB1
AA4
AA16
AA13
AA11
A9
A7
A4
A26
A23
A21
A19
A15
A12
A1

Near PIN
AB27

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

ICH6(4/4)

HDL75 LA3041

29 60Thursday, July 28, 2005

1

0.1

5

4

3

2

1

HDD Connector

IDE_DD[0..15]<27>

IDE_DA[0..2]<27>

SUYIN_200138FR044G242ZL

D D

+5VS

Placea caps. near HDD

C C

CONN.

+5VS

1

C834

2

1000P_0402_50V7K

0.1U_0402_16V4Z

1

C835

2

IDE_LED#<42>

1 2

R728
100K_0402_5%

1

C836

2

1U_0603_10V4Z

HD_IDERST#<42,45>

IDE_DDREQ<27>

IDE_DIOW#<27>

IDE_DIORDY<27>
IDE_DDACK#<27>

HDD_IRQ<45>

IDE_DCS1#<27,45>

HD_IDERST#
IDE_DD7
IDE_DD6 IDE_DD9
IDE_DD5
IDE_DD4
IDE_DD3
IDE_DD2
IDE_DD1
IDE_DD0

IDE_DDREQ
IDE_DIOW#
HDD_IOR#
IDE_DIORDY
IDE_DDACK#
HDD_IRQ
IDE_DA1
IDE_DA0

IDE_DCS1#

IDE_LED#

+5VS +5VS

10U_0805_10V4Z

1

C837

2

1

C838
10U_0805_10V4Z

2

IDE_DD[0..15]
IDE_DA[0..2]

4344
4142
3940
3738
3536
3334
3132
2930
2728
2526
2324
2122
1920
1718
1516
1314
1112

910
78
56
34
12

JP7

IDE_DD8
IDE_DD10

IDE_DD11
IDE_DD12
IDE_DD13
IDE_DD14
IDE_DD15

PCSEL

PDIAG#
IDE_DA2
IDE_DCS3#

R727
470_0402_5%

1 2

Pull Down set Primary

IDE_DCS3# <27,45>

IDE_DIOW# HDD_IOR#

C154
12P_0402_50V8K

LGA@

HDD_B_IOR#<45>

HDD_B_IOR# HDD_IOR#

R43

0_0402_5%

SWDJ@

R77

0_0402_5%

NOSWDJ@

HDD_IOR#ODD_IOR#

C155
12P_0402_50V8K

LGA@

Close to JP7

CD-ROM Connector

ODD_IOR#

C156

JP8

CD_AGND<43>
SIDE_RST#<45>

B B

IDE_IRQ<27,45>

SW_IDE_SDCS1#<45>

SW_IDE_SDCS1#

Pull hign set Slave

+5VS

Place caps. near CDROM
CONN.

A A

+5VCD

1

2

1000P_0402_50V7K

C839

0.1U_0402_16V4Z

1

C840

2

5

56_0402_5%

1 2

R1199

+5VCD

SEC_CSEL

12

R729 4.7K_0402_5%

1

2

1U_0603_10V4Z

C841

@

10U_0805_10V4Z

1

C842

2

1

C1133

@

22P_0402_50V8J

2

1

C843
10U_0805_10V4Z

2

SIDE_RST#
IDE_DD7
IDE_DD6
IDE_DD5
IDE_DD4
IDE_DD3
IDE_DD2
IDE_DD1
IDE_DD0

IDE_DIOW#
IDE_DIORDY
IDE_IRQ
IDE_DA1
IDE_DA0

IDE_LED#

1 2
3 4
5 6
7 8
9 10
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
29 30
31 32
33 34
35 36
37 38
39 40
41 42
43 44
45 46
47 48
49 50

OCTEK_CDR-50JE2

Change PCB
Footprint.

4

IDE_DD8
IDE_DD9
IDE_DD10
IDE_DD11
IDE_DD12
IDE_DD13
IDE_DD14
IDE_DD15
IDE_DDREQ
ODD_IOR#

IDE_DDACK#
PDIAG#

IDE_DA2
SW_IDE_SDCS3#

W=80mils

INT_CD_R <43>INT_CD_L<43>

ODD_IOR# <45>

R1197 10K_0402_5%

12

+5VCD

SW_IDE_SDCS3# <45>

+5VCD

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

12P_0402_50V8K

@

IDE_DIOW#

C157
12P_0402_50V8K

@

Close to JP8

2

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

IDE CONNECTOR

HDL75 LA3041

30 60Thursday, July 28, 2005

1

0.1

A

B

C

D

E

G1

F3

VCC2

VCC3

VCC1

CAD31/D10

CAD30/D9
CAD29/D1
CAD28/D8
CAD27/D0
CAD26/A0
CAD25/A1
CAD24/A2
CAD23/A3
CAD22/A4
CAD21/A5
CAD20/A6

CAD19/A25

CAD18/A7
CAD17/A24
CAD16/A17

CAD15/IOWR#

CAD14/A9

CAD13/IORD#

CAD12/A11

CAD11/OE#

CAD10/CE2#

CAD9/A10

CAD8/D15

CAD7/D7

CAD6/D13

CAD5/D6

CAD4/D12

CAD3/D5

CAD2/D11

CAD1/D4
CAD0/D3

CCBE3#/REG#

CCBE2#/A12

CCBE1#/A8

CCBE0#/CE1#

CRST#/RESET
CFRAME#/A23

CIRDY#/A15

CTRDY#/A22
CSTOP#/A20

CPERR#/A14

CPAR/A13

CGNT#/WE#

CCLK/A16

CBLOCK#/A19

SPKROUT

CCD2#/CD2#
CCD1#/CD1#

CVS2/VS2#

CVS1/VS1

CRSV3/D2
CRSV2/A18
CRSV1/D14

MSINS#

SMBSY#

SMCD#
SMWP#

SMCE#

+S1_VCC
+3VS

B2
C3
B3
A3
C4
A6
D7
C7
A8
D8
A9
C9
A10
B10
D10
E12
F10
E13
F13
F11
G10
G11
G12
H12
H10
J11
J12
K13
J10
K10
K12
L13

B7
A11
E11
H13

B9
B11
A12
A13
B13
C12
C13
A5
D13
B8
C11
B12

C5
D5

D11
D6
M9

B5
A4

L12
D9
C6
A2
E10
J13

H7
J8
H8
E9
G9
H9
G8
F9

H6
J7
J6
J5

S1_A[0..25]
S1_D[0..15]

S1_D10
S1_D9
S1_D1
S1_D8
S1_D0
S1_A0
S1_A1
S1_A2
S1_A3
S1_A4
S1_A5
S1_A6
S1_A25
S1_A7
S1_A24
S1_A17
S1_IOWR#
S1_A9
S1_IORD#
S1_A11
S1_OE#
S1_CE2#
S1_A10
S1_D15
S1_D7
S1_D13
S1_D6
S1_D12
S1_D5
S1_D11
S1_D4
S1_D3

S1_REG#
S1_A12
S1_A8
S1_CE1#

S1_RST
S1_A23
S1_A15
S1_A22
S1_A21
S1_A20
S1_A14
S1_WAIT#
S1_A13
S1_INPACK#
S1_WE#
A16_CLK

S1_BVD1
S1_WP

S1_A19
S1_RDY#
PCM_SPK#

S1_BVD2
S1_CD2#

S1_CD1#
S1_VS2
S1_VS1
S1_D2
S1_A18
S1_D14

XD_MS_PWREN#
MSBS_XDD1

MSD0_XDD2
MSD1_XDD6
MSD2_XDD5
MSD3_XDD3

S1_A[0..25] <32>
S1_D[0..15] <32>

S1_IOWR# <32>

S1_IORD# <32>
S1_OE# <32>

S1_CE2# <32>

S1_CE1# <32>
S1_RST <32>

S1_WAIT# <32>

S1_INPACK# <32>

S1_WE# <32>

1 2

R571 33_0402_5%

S1_BVD1 <32>
S1_WP <32>

S1_RDY# <32>

PCM_SPK# <44>

S1_BVD2 <32>
S1_CD2# <32>

S1_CD1# <32>
S1_VS2 <32>
S1_VS1 <32>

MSINS# <32>
XD_MS_PWREN# <32>
MSBS_XDD1 <32>

1 2

R572 33_0402_5%

MSD0_XDD2 <32>
MSD1_XDD6 <32>
MSD2_XDD5 <32>
MSD3_XDD3 <32>

XDBSY# <32>
XDCD# <32>
XDWP# <32>
XDCE# <32>

VPPD0<32>

VPPD1<32>
VCCD0#<32>
VCCD1#<32>

U33

4 4

3 3

2 2

SD Pullhigh for BIOS default

CLK_PCI_PCM

12

R570

10_0402_5%@

1

C657

18P_0402_50V8K@

2

+VCC_5IN1

IDSEL:
PCI_AD20

43K_0402_5%

SM_CD#<32>

CLK_PCI_PCM<16>

R1169

+3VS

1 2

POP FOR 712

R1170

R833 0_0805_5%@

1 2

R791 43K_0402_5%

1 2

R788 43K_0402_5%

1 2

R576 43K_0402_5%

1 1

1 2

R577 43K_0402_5%

1 2

R578 43K_0402_5%

+3VS

1 2

12

0_0402_5%

SD_PULLHIGH

SDCM_XDALE
SDDA0_XDD7
SDDA1_XDD0
SDDA2_XDCL
SDDA3_XDD4

PCI_AD[0..31]<26,33,34,36,37>

PCI_C_BE3#<26,33,34,36,37> S1_REG# <32>
PCI_C_BE2#<26,33,34,36,37>
PCI_C_BE1#<26,33,34,36,37>
PCI_C_BE0#<26,33,34,36,37>

PCI_RST#<26,33,36,37,42>

PCI_FRAME#<26,33,34,36,37>

PCI_IRDY#<26,33,34,36,37>

PCI_TRDY#<26,33,34,36,37>

PCI_DEVSEL#<26,33,34,36,37>

PCI_STOP#<26,33,34,36,37>
PCI_PERR#<26,33,34,36,37>
PCI_SERR#<26,34,36,37>

PCI_PAR<26,33,34,36,37>

PCI_REQ2#<26>
PCI_GNT2#<26>

PCM_PME#<26,33,34,36,37,40,41>

+3VS

PCI_PIRQA#<26>
PCI_PIRQB#<26>

SIRQ<28,40,42>

SDOC#<32>

PCI_RST#

+VCC_5IN1

SDCD#<32>
SDWP#<32>

CLK_EXT_SD48<16>
SDCK_XDWE#<32>

SDCM_XDALE<32>

SDDA0_XDD7<32>
SDDA1_XDD0<32>
SDDA2_XDCL<32>
SDDA3_XDD4<32>

SDPWREN#<32>

PCI_AD[0..31]

PCI_AD31
PCI_AD30
PCI_AD29
PCI_AD28
PCI_AD27
PCI_AD26
PCI_AD25
PCI_AD24
PCI_AD23
PCI_AD22
PCI_AD21
PCI_AD20
PCI_AD19
PCI_AD18
PCI_AD17
PCI_AD16
PCI_AD15
PCI_AD14
PCI_AD13
PCI_AD12
PCI_AD11
PCI_AD10
PCI_AD9
PCI_AD8
PCI_AD7
PCI_AD6
PCI_AD5
PCI_AD4
PCI_AD3
PCI_AD2
PCI_AD1
PCI_AD0

CLK_PCI_PCM

+3V_PCM_SUSP

1 2

R573 10K_0402_5%
R575 100_0402_1%

1 2

SDCM_XDALE
SDDA0_XDD7
SDDA1_XDD0
SDDA2_XDCL
SDDA3_XDD4

PCM_IDPCI_AD20

1 2

PCI_PIRQA#
SD_PULLHIGH
PCI_PIRQB#

SDOC#

SDCD#
SDWP#

SDPWREN#

R1185 0_0402_5%
R574 0_0402_5%

12

R1186

43K_0402_5%

@

1 2

C2

AD31

C1

AD30

D4

AD29

D2

AD28

D1

AD27

E4

AD26

E3

AD25

E2

AD24

F2

AD23

F1

AD22

G2

AD21

G3

AD20

H3

AD19

H4

AD18

J1

AD17

J2

AD16

N2

AD15

M3

AD14

N3

AD13

K4

AD12

M4

AD11

K5

AD10

L5

AD9

M5

AD8

K6

AD7

M6

AD6

N6

AD5

M7

AD4

N7

AD3

L7

AD2

K7

AD1

N8

AD0

E1

CBE3#

J3

CBE2#

N1

CBE1#

N5

CBE0#

G4

PCIRST#

J4

FRAME#

K1

IRDY#

K3

TRDY#

L1

DEVSEL#

L2

STOP#

L3

PERR#

M1

SERR#

M2

PAR

A1

PCIREQ#

B1

PCIGNT#

H1

PCICLK

L8

RIOUT#_PME#

L11

SUSPEND#

F4

IDSEL

K8

MFUNC0

N9

MFUNC1

K9

MFUNC2

N10

MFUNC3

L10

MFUNC4

N11

MFUNC5

M11

MFUNC6

J9

MFUNC7

M10

GRST#

E7

VCC_SD

E8

SDCD#

F8

SDWP/SMWPD#

G7

SDPWREN33#

H5

SDCLKI

F6

SDCLK/SMWE#

E5

SDCMD/SMALE

E6

SDDAT0/SMDATA7

F7

SDDAT1/SMDATA0

F5

SDDAT2/SMCLE

G6

SDDAT3/SMDATA4

G5

GND_SD

N12

M12

N13

M13

VPPD0

VPPD1

VCCD0#

VCCD1#

PCI Interface

SD/MMC/MS/SM

G13

A7

VCCA1

VCCA2

GND1D3GND2H2GND3L4GND4M8GND5

K2

N4

L6

C8

L9

H11

D12

B4

VCC4

VCC5

VCC9

VCC6

VCC7

VCC8

VCC10

CARDBUS

CDEVSEL#/A21

CSERR#/WAIT#

CREQ#/INPACK#

CSTSCHG/BVD1_STSCHG#

CCLKRUN#/WP_IOIS16#

CINT#/READY_IREQ#

CAUDIO/BVD2_SPKR#

MSPWREN#/SMPWREN#

MSBS/SMDATA1

MSCLK/SMRE#
MSDATA0/SMDATA2
MSDATA1/SMDATA6
MSDATA2/SMDATA5
MSDATA3/SMDATA3

GND6

GND7

GND8

CB712_LFBGA169

B6

F12

K11

C10

+3VS

1

C645

0.1U_0402_16V4Z

2

+3VS

1

C649

0.1U_0402_16V4Z

2

+S1_VCC

1

C653

0.1U_0402_16V4Z

2

S1_A16

MSCLK_XDRE# <32>

1

C646

0.1U_0402_16V4Z

2

1

C650

0.1U_0402_16V4Z

2

1

C654

0.1U_0402_16V4Z

2

10P_0402_25V8K

1

2

1

2

S1_CD1# S1_CD2#

C658

Close chip termenal

MSD0_XDD2
MSD1_XDD6
MSD2_XDD5
MSD3_XDD3
MSBS_XDD1

C647

0.1U_0402_16V4Z

C652

0.1U_0402_16V4Z

1

C655

0.1U_0402_16V4Z

2

1

10P_0402_25V8K

2

Closed to Pin A4Closed to Pin L12

1 2

R584 43K_0402_5%@

1 2

R586 43K_0402_5%@

1 2

R587 43K_0402_5%

@

1 2

R588 43K_0402_5%

@

1 2

R589 43K_0402_5%

@

1

C656

0.1U_0402_16V4Z

2

1

C659

2

1 2

R580 43K_0402_5%@

1 2

R581 43K_0402_5%@

1 2

R1171 43K_0402_5%@

Close chip termenal

SDCD#
SDWP#
MSINS#

A

Title

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

B

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

D

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

PCMCIA Controller ENE CB714

HDL75 LA3041

31 60Thursday, July 28, 2005

E

of

0.1

5

PCMCIA Power Controller

U34

9

+5VS

5
6

+3VS

3
4

R590
10K_0402_5%

1 2

SDCD#
SDWP#

SDDA1_XDD0

SDDA0_XDD7

SDCK_XDWE#

SDCM_XDALE
SDDA3_XDD4
SDDA2_XDCL

1

C949

2

C951

0.1U_0402_16V4Z

12V

5V
5V

3.3V

3.3V

D D

1 2

C6660.1U_0402_16V4Z

1 2

C6674.7U_0805_10V4Z

1 2

C6700.1U_0402_16V4Z

1 2

C6714.7U_0805_10V4Z

C C

+VCC_5IN1

0.1U_0402_16V4Z

MSD1_XDD6<31>

+VCC_5IN1

MSD2_XDD5<31>
MSD3_XDD3<31>

B B

MSD0_XDD2<31>

MSINS#<31>

MSBS_XDD1<31>

XDWP#<31>

A A

+VCC_5IN1

MSD1_XDD6

MSD2_XDD5
MSD3_XDD3

MSD0_XDD2
MSCLK_XDRE#
MSINS#
MSBS_XDD1

SDDA1_XDD0
MSBS_XDD1
MSD0_XDD2
MSD3_XDD3
SDDA3_XDD4
MSD2_XDD5
MSD1_XDD6
SDDA0_XDD7

XDBSY#
MSCLK_XDRE#
XDCE#
SDCK_XDWE#
XDWP#
SDDA2_XDCL
SDCM_XDALE
XDCD#

1

2

5

GND

7

JP18

20

MS_1P(GND)

37

MS_10P(GND)

24

MS_3P(VCC)

35

MS_9P(VCC)

28

MS_5P(RSVD1)

32

MS_7P(RSVD2)

26

MS_4P(SDIO)

33

MS_8P(SCLK)

30

MS_6P(INS)

22

MS_2P(BS)

60

XD_10P(D0)

61

XD_11P(D1)

62

XD_12P(D2)

63

XD_13P(D3)

64

XD_14P(D4)

65

XD_15P(D5)

66

XD_16P(D6)

67

XD_17P(D7)

52

XD_2P(R/B#)

53

XD_3P(RE#)

54

XD_4P(CE#)

57

XD_7P(WE#)

58

XD_8P(WP#)

55

XD_5P(CLE)

56

XD_6P(ALE)

51

XD_1P(CD)

68

XD_18P(VCC)

50

XD_1P(GND)

59

XD_9P(GND)

TAISOL_152-1001001-00@

16

12
14
17
20
22
23
24
25
26

VCC
VCC
VCC

VPP

VCCD0
VCCD1

VPPD0
VPPD1

OC

SHDN

CP-2211_SSOP16

J23

3 IN 1 MS/SD/MMC

1

CD_SD

2

WP_SD

3

DAT1_SD

4

DAT0_SD

5

WP GND_SD

6

VSS_SD

9

CLK_SD
VDD_SD
VSS_SD
CMD_SD
CD/DAT3_SD
DAT2_SD
CD GND_SD
CD GND_SD
CD GND_SD
CD GND_SD

PROCO_MSD019-C0-1690

13
12
11

10

1
2
15
14

8

Connector

Connector

MS INTERFACE XD INTERFACE

+S1_VCC

40mil

+S1_VPP

20mil

SD INTERFACE

5 IN 1

1 2

C660 0.1U_0402_16V4Z

1 2

C661 0.1U_0402_16V4Z

1 2

C663 10U_0805_10V4Z

1 2

C664 0.01U_0402_16V7K

1 2

C665 1U_0603_10V4Z

VCCD0# <31>
VCCD1# <31>
VPPD0 <31>
VPPD1 <31>

MS INTERFACE

Vss_MS

VCC_MS

SCLK_MS

Reverved_MS

INS_MS

Reverved_MS

SDIO_MS

Vcc_MS

BS_MS

Vss_MS

SM_5P(WP-IN#)

SM_19P(BSY#)

SM_12P(VCC)
SM_22P(VCC)

SM INTERFACESD INTERFACE

SM_10P(GND)
SM_18P(GND)

SM_WP1(GND)

SM_WP2(SW-WP2)

SM_CD1(GND)

SM_CD2(SW-CD2)

SD_SW_WP1(SW-WP1)
SD_SW_WP2(SW-GND)

SD_SW_CD1(SW-CD1)

SD_SW_CD2(SW-GND)

4

21
19
18
16
15
13
11
10
8
7

SM_6P(D0)
SM_7P(D1)
SM_8P(D2)

SM_9P(D3)
SM_13P(D4)
SM_14P(D5)
SM_15P(D6)
SM_16P(D7)

SM_2P(CLE)
SM_3P(ALE)

SM_21P(CE#)
SM_20P(RE#)

SM_4P(WE#)

SM_11P(CD#)
SM_17P(LVD)

SM_1P(GND)

SD_IO(GND)

SD_7P(D0)

SD_8P(D1)

SD_9P(D2)

SD_1P(D3)

SD_5P(CLK)

SD_2P(CMD)

SD_4P(VCC)

SD_6P(GND)
SD_3P(GND)

4

MSCLK_XDRE#

MSD3_XDD3
MSD2_XDD5

MSD0_XDD2
MSD1_XDD6
MSBS_XDD1

18
16
14
12
9
11
13
15

45
43
44
42
41
39
40
8
17

7
46
47
10
38

49
48
6
5

69
21
19
36
34

25
31

27
23
29

1
2
3
4

MSINS#

SDDA1_XDD0
MSBS_XDD1
MSD0_XDD2
MSD3_XDD3
SDDA3_XDD4
MSD2_XDD5
MSD1_XDD6
SDDA0_XDD7

SDDA2_XDCL
SDCM_XDALE
XDCE#
MSCLK_XDRE#
SDCK_XDWE#
XDWP#
XDBSY#
XDCD#

1

2

SDWP#
SM_CD#

SDDA0_XDD7
SDDA1_XDD0
SDDA2_XDCL
SDDA3_XDD4

SDCK_XDWE#
SDCM_XDALE

SDWP#
SDCD#

1

2

3

CardBus Socket

1

C668

2

1

C672

0.01U_0402_16V7Z

2

U52

4

VIN

CE1GND

RT9702ACB_SOT23-5

SDPWREN#<31>

S1_A[0..25]
S1_D[0..15]

C669

0.1U_0402_16V4Z

C673

3

FLG

5

VOUT

2

R766

43K_0402_5%

+S1_VCC

1

2

+S1_VPP

1

2

MSCLK_XDRE#

12

1

2

+VCC_5IN1

+3VS

1 2

R787
0_0402_5%

@

C915
10P_0402_50V8K

@

+3VS

10K_0402_5%

1 2

40mil

+3VS

12

R515
10K_0402_5%

13

D

2

G

S

R767

Q94
2N7002_SOT23

S1_A[0..25]<31>
S1_D[0..15]<31>

Close to
CardBus Conn.

10U_0805_10V4Z

4.7U_0805_10V4Z

+VCC_5IN1

MS CLK

MSCLK_XDRE#<31>

SDDA0_XDD7 <31>

+VCC_5IN1

C950

0.1U_0402_16V4Z

SM_CD# <31>

SDDA0_XDD7 <31>

SDDA1_XDD0 <31>
SDDA2_XDCL <31>

SDDA3_XDD4 <31>

SDCM_XDALE <31>

+VCC_5IN1

SDWP# <31>

SDCD# <31>

C952

0.1U_0402_16V4Z

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

+3VS

SDPWREN

XD_MS_PWREN#<31>

2

SD CLK

SDPWREN

2

S1_CE1#<31>
S1_OE#<31>

S1_WE#<31>
S1_RDY#<31>

+S1_VCC

SDCK_XDWE#<31>

SDOC# <31>

S1_D3
S1_D4
S1_D5
S1_D6
S1_D7
S1_CE1#
S1_A10
S1_OE#
S1_A11
S1_A9
S1_A8
S1_A13
S1_A14
S1_WE#
S1_RDY#

+S1_VPP

S1_WP<31>

S1_A16
S1_A15
S1_A12
S1_A7
S1_A6
S1_A5
S1_A4
S1_A3
S1_A2
S1_A1
S1_A0
S1_D0
S1_D1
S1_D2
S1_WP S1_CD2#

R585

0_0402_5%

+3VS

R603 8.2K_0402_5%@

+VCC_5IN1

xD PU and PD. Close to Socket

1 2

R598 10K_0402_5%

1 2

R599 10K_0402_5%

1 2

R600 2.2K_0402_5%@
R604 10K_0402_5%@

Reserve for Debug.

S1_WP
S1_OE#
S1_RST
S1_CE1#
S1_CE2#

Title

Size Document Number Rev

Date: Sheet

SDCK_XDWE#

12

1

2

12

MSCLK_XDRE#
SDCK_XDWE#

12

10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34

C914
10P_0402_50V8K

XDCD#

XDBSY#

+S1_VCC

12

R59143K_0402_5%

12

R59247K_0402_5%

12

R59347K_0402_5%

12

R59447K_0402_5%

12

R59547K_0402_5%

JP24

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34

SANTA_130602-2

35

35

36

36

37

37

38

38

39

39

40

40

41

41

42

42

43

43

44

44

45

45

46

46

47

47

48

48

49

49

50

50

51

51

52

52

53

53

54

54

55

55

56

56

57

57

58

58

59

59

60

60

61

61

62

62

63

63

64

64

65

65

66

66

67

67

68

68

XDCD# <31>

XDCE# <31>

XDBSY# <31>

1

S1_CD1#

S1_D11
S1_D12
S1_D13
S1_D14
S1_D15

S1_CE2#

S1_VS1

S1_IORD#

S1_IOWR#

S1_A17
S1_A18
S1_A19
S1_A20
S1_A21

S1_A22
S1_A23
S1_A24
S1_A25
S1_VS2
S1_RST

S1_WAIT#

S1_INPACK#

S1_REG#

S1_BVD2
S1_BVD1

S1_D8
S1_D9

S1_D10

712@

712@

712@

Compal Electronics, Inc.

PCMCIA Socket

HDL75 LA3041

1

32 60Thursday, July 28, 2005

S1_CD1# <31>

S1_CE2# <31>
S1_VS1 <31>
S1_IORD# <31>
S1_IOWR# <31>

+S1_VCC
+S1_VPP

S1_VS2 <31>
S1_RST <31>
S1_WAIT# <31>
S1_INPACK# <31>
S1_REG# <31>
S1_BVD2 <31>
S1_BVD1 <31>

S1_CD2# <31>

0.1

of

A

B

C

D

E

+3VS

0.1U_0402_16V4Z

1

1

C920

2

2

4 4

3 3

2 2

0.1U_0402_16V4Z

CLK_PCI_1394

12

1

2

1

C921

2

0.1U_0402_16V4Z

R1008
22_0402_5%

@

C929
15P_0402_50V8D

@

PCI_AD16

0.1U_0402_16V4Z

1

C922

2

R991 100_0402_5%

1 2

ICH_GPIO2_PIRQE#<26>

1

C923

2

0.1U_0402_16V4Z

PCI_AD[0..31]<26,31,34,36,37>

PCI_C_BE0#<26,31,34,36,37>
PCI_C_BE1#<26,31,34,36,37>
PCI_C_BE2#<26,31,34,36,37>
PCI_C_BE3#<26,31,34,36,37>

PCI_FRAME#<26,31,34,36,37>

PCI_IRDY#<26,31,34,36,37>

PCI_TRDY#<26,31,34,36,37>

PCI_DEVSEL#<26,31,34,36,37>

PCI_STOP#<26,31,34,36,37>

PCI_PERR#<26,31,34,36,37>

PCI_PAR<26,31,34,36,37>
PCI_REQ0#<26>
PCI_GNT0#<26>

PCI_RST#<26,31,36,37,42>

CLK_PCI_1394<16>

0.1U_0402_16V4Z

C924

1

C925

2

0.1U_0402_16V4Z

PCI_AD[0..31]

PCI_C_BE0#
PCI_C_BE1#
PCI_C_BE2#
PCI_C_BE3#

PCI_FRAME#
PCI_IRDY#
PCI_TRDY#
PCI_DEVSEL#
PCI_STOP#
PCI_PERR#
PCI_PAR
PCI_REQ0#
PCI_GNT0#

0.1U_0402_16V4Z

1

C926

2

PCI_AD0
PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD6
PCI_AD7
PCI_AD8
PCI_AD9
PCI_AD10
PCI_AD11
PCI_AD12
PCI_AD13
PCI_AD14
PCI_AD15
PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20
PCI_AD21
PCI_AD22
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30
PCI_AD31

1394_IDSEL

1

1

C927

C928

2

0.1U_0402_16V4Z

2

+3VS

+3VS

100

108

118

126

112

46

110

122

111

VCC99VCC

VCC

VCC5VCC17VCC32VCC

21

VCC

U37

25

AD0

24

AD1

20

AD2

19

AD3

18

AD4

16

AD5

15

AD6

14

AD7

11

AD8

10

AD9

9

AD10

8

AD11

7

AD12

4

AD13

3

AD14

2

AD15

117

AD16

116

AD17

115

AD18

114

AD19

113

AD20

109

AD21

107

AD22

106

AD23

103

AD24

102

AD25

101

AD26

98

AD27

97

AD28

96

AD29

95

AD30

94

AD31

12

CBE0#

1

CBE1#

119

CBE2#

104

CBE3#

105

IDSEL

120

FRAME#

121

IRDY#

123

TRDY#

124

DEVSEL#

125

STOP#

127

PERR#

128

PAR

93

REQ#

92

GNT#

88

INTA#

89

PCIRST#

90

PCICLK

PCI Bus

NC45NC48NC49NC50NC37NC51NC52NC53NC54NC40NC39NC35NC74NC75NC76NC77NC78NC64NC81NC82NC83NC84NC85I2CEN43CARDEN

NC41NC

42

PVD36PVD

Power

IEEE 1394

VT6301S

30

VCC

+3VS

NC

31

44

R1017

4.7K_0402_5%

@

1 2

GND47GND

GND91GND

GND

GND

OSC

XI

57

38

GND

GND6GND13GND23GND33GND

GND22GND

EEPROM
I/F

EECK/SCL

PM & Test

PHYRESET#

XO

58

1394 Differential Pairs

59

PVA

62

PVA

72

PVA

73

PVA

86

PVA

87

PVA

61

GND

65

GND

66

GND

79

GND

80

GND

56

GND

26

EECS

27

EEDO

EEDI/SDA

PME#

XCPS
XREXT
TPB0M

TPB0P

TPA0M

TPA0P

TPBIAS0

VT6301S-CD_LQFP128

24.576MHz_16P_3XG-24576-43E1

28
29

34
60
63
67

68
69
70
71

55

Y4

1394SDA
1394SCL

C937

1 2

XCPS

1U_0402_6.3V4Z

1 2

1

1

C932

2

2

+3VS

C930

0.1U_0402_16V4Z

+3VS_1394

1

2

0.1U_0402_16V4Z

1

C931

2

0.1U_0402_16V4Z

4.7K_0402_5%
R1022

1 2

reserve 4.7K f or None EEprom

1394_PME# <26,31,34,36,37,40,41>

C935

1 2

47P_0402_25V8K

Note:
These Components need to Close to chip pins.

C938
10P_0402_50V8J

C939
10P_0402_50V8J

12

12

1 2

R1013

6.34K_0603_1%

1 2

R1016
1M_0402_5%

1 2

U59

1

A0

2

A1

3

A2

4

GND

AT24C02N-10SI-2.7_SO8@

L39

KC FBM-L11-201209-221LMAT_0805

C933

0.1U_0402_16V4Z

54.9_0402_1%
R1011

1 2

54.9_0402_1%
R1012

1 2

1 2

R1015

54.9_0402_1%
R1014

0.33U_0603_16V4Z

1 2

C936

1 2

54.9_0402_1%

8

VCC

7

WP

1394SCL

6

SCL

1394SDA

5

SDA

270P_0402_50V7K

1 2

4.99K_0402_1%
R1006

1 2

+3VS

C934

XCPS

1 2

R1007

C958

@

12

TPB0-

TPB0+

TPA0-

TPA0+

0.1U_0402_16V4Z @

510_0402_5%

12

R1010
1K_0402_5%

JP26

1
2
3
4

AMP_440168-2

1 1

Title

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

D

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

VIA1394A VT6301S

HDL75 LA3041

33 60Thursday, July 28, 2005

E

0.1

of

5

4

3

2

1

LAN RTL8110SB(L)

PCI_AD[0..31]<26,31,33,36,37>

PCI_AD[0..31]

PCI_AD0
PCI_AD1
PCI_AD2

R538
100_0402_1%

CLK_PCI_LOM
PM_CLKRUN#

8
7
6
5

PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD6
PCI_AD7
PCI_AD8
PCI_AD9

PCI_AD11
PCI_AD12
PCI_AD13
PCI_AD14
PCI_AD15
PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20
PCI_AD21
PCI_AD22
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30
PCI_AD31

PCI_C_BE0#
PCI_C_BE1#
PCI_C_BE2#
PCI_C_BE3#

LAN_IDSEL

+3V_LAN

1

2

D D

CLK_PCI_LOM

C C

IDSEL: AD17

B B

LAN_X1 LAN_X2

R1172 1M_0402_5%

1

C620
27P_0402_50V8J

2

A A

LAN_EECS
LAN_EECLK
LAN_EEDI
LAN_EEDO

12

1

2

PCI_AD17

1 2

@

Y2

12

25MHZ_20P

R529

10_0402_5%@

C606

18P_0402_50V8K@

PCI_C_BE0#<26,31,33,36,37>
PCI_C_BE1#<26,31,33,36,37>
PCI_C_BE2#<26,31,33,36,37>
PCI_C_BE3#<26,31,33,36,37>

PCI_PAR<26,31,33,36,37>

PCI_FRAME#<26,31,33,36,37>

PCI_IRDY#<26,31,33,36,37>

PCI_TRDY#<26,31,33,36,37>

PCI_DEVSEL#<26,31,33,36,37>

PCI_STOP#<26,31,33,36,37>

PCI_PERR#<26,31,33,36,37>
PCI_SERR#<26,31,36,37>

PCI_REQ3#<26>
PCI_GNT3#<26>

ICH_GPIO2_PIRQF#<26>

LAN_PME#<26,31,33,36,37,40,41>

CLK_PCI_LOM<16>
PM_CLKRUN#<28,36,37,40,42>

12

R1173

1

2

U32

1

CS

2

SK

3

DI

4

DO

AT93C46-10SI-2.7_SO8

5

1 2

PLTRST#<9,26,28,38,40,45>

0_0402_5%

C621
27P_0402_50V8J

VCC

NC
NC

GND

U31

104
103
102

98
97
96
95
93
90
89
87
86
85
83
82
79
59
58
57
55
53
50
49
47
43
42
40
39
37
36
34
33

92
77
60
44

46
76

61
63
67
68
69

70
75

30
29

25
31
27
28

65

4

17

128

21
38
51
66
81

91
101
119

35

52

80
100

RTL8110SBL_LQFP128

C631

0.1U_0402_16V4Z

AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31

PCI I/F

C/BE#0
C/BE#1
C/BE#2
C/BE#3

IDSEL
PAR

FRAME#
IRDY#
TRDY#
DEVSEL#
STOP#

PERR#
SERR#

REQ#
GNT#

INTA#
PME#
RST#
CLK

CLKRUN#

GND/VSS
GND/VSS
GND/VSS

GND/VSSPST
GND/VSSPST
GND/VSSPST
GND/VSSPST
GND/VSSPST
GND/VSSPST
GND/VSSPST
GND/VSSPST

GND
GND
GND
GND

108

EEDO

109

AUX/EEDI

111

EESK

106

EECS

117

LED0

115

LED1

114

LED2

113

NC/LED3

TXD-/MDI0-

NC/MDI2+

NC/MDI2-

NC/MDI3+

NC/MDI3-

X1
X2

LWAKE

ISOLATE#

RTSET

NC/M66EN

NC/AVDDH

AVDDH

NC/HG

NC/LG2

NC/VSS
NC/VSS

NC/GND
NC/GND
NC/GND
NC/GND
NC/GND
NC/GND

CTRL25
CTRL12

VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33

AVDDL
AVDDL
AVDDL
AVDDL

VDD12
VDD12
VDD12
VDD12
VDD12

NC/VDD12
NC/VDD12
NC/VDD12
NC/VDD12
NC/VDD12

NC

0.1U_0402_16V4Z

4

1
2
5
6

14
15
18
19

121
122

105
23
127
72
74

88
10

120
11

123
124

9
13

22
48
62
73
112
118

8
125
26

41
56
71
84
94
107

3
7
20
16

126
32
54
78
99

24
45
64
110
116

12

TXD+/MDI0+

RXIN+/MDI1+

RXIN-/MDI1-

NC/SMBCLK

NC/SMBDATA

NC/HSDAC+

LAN I/F

Power

LAN_EEDO
LAN_EEDI
LAN_EECLK
LAN_EECS

LAN_MDI0+PCI_AD10
LAN_MDI0­LAN_MDI1+
LAN_MDI1-

LAN_MDI2+
LAN_MDI2­LAN_MDI3+
LAN_MDI3-

LAN_X1
LAN_X2

10mil

10mil

R533 0_0402_5%

1 2

R534 0_0402_5%

1 2
1 2

R535 0_0402_5%

unpop when use 8100C(L)

CTRL25
CTRL18

R542 0_0402_5%

1 2

R557

1 2

+LAN_DVDD

20mil

1

C630

2

R527

3.6K_0402_5%

1 2

R530 1K_0402_5%@

1 2

R531 15K_0402_5%@

1 2

GIGA@

R532 2.49K_0603_1%

1 2

R1063 5.6K_0603_1%

1 2

100@

GIGA@

+3VALW

LAN_MIDI0+ <35>
LAN_MIDI0- <35>
LAN_MIDI1+ <35>
LAN_MIDI1- <35>

LAN_MIDI2+ <35>
LAN_MIDI2- <35>
LAN_MIDI3+ <35>
LAN_MIDI3- <35>

SUSP#

SUSP# <38,40,43,45,46>

+3VS

5.6K for 8100CL,

2.49K for 8110SBL

+3V_LAN

EN_WOL# = Low,
System can wake on LAN
( keep Low when Power On)

VGS(th) = -0.45V
IDmax = 2.3A

+3V_LAN

1

C607

2

0.1U_0402_16V4Z

+3V_LAN

60mil 40mil

CTRL25

1

Icmax = 2A Icmax = 2A

22U_A_4VM

+3V_LAN

C613

2 3

1

+

2

2SB1188_SC62
Q27

60mil

1

C614

0.1U_0402_16V4Z

2

+2.5V_LAN

pop when use 8110SB(L)

GIGA@

1 2

R540 0_0805_5%

1 2

R541 0_0805_5%

100@

reserved for 8100C(L)

C622

0.1U_0402_16V4Z

+2.5V_LAN
+3V_LAN

+LAN_DVDD

1

C623

2

0.1U_0402_16V4Z

+LAN_DVDD

40mil

1

C617

C618

0.1U_0402_16V4Z

2

0.1U_0402_16V4Z

+LAN_DVDD

1

1

C619

0.1U_0402_16V4Z

2

2

+LAN_AVDDL

0_0805_5%

GIGA@

unpop when use 8100C(L)

R545 0_0805_5%

1 2

GIGA@

reserved for 8100C(L)

R550 0_0805_5% 100@

1 2
1 2

R556 0_0805_5%

1

C629

0.1U_0402_16V4Z

2

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SE CRET INFO RMATI ON. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

+LAN_DVDD
+3V_LAN

when use 8110SB(L)

GIGA@

3

+3VALW

12

R528

0_1206_5%

+3V_LAN

40mil

0.1U_0402_16V4Z

1

2

C608

+3V_LAN

1

C609

2

0.1U_0402_16V4Z

unpop when use 8100C(L)

2.5V for RTL8100C(L)

1.8V for RTL8110S

1.2V for RTL8110SB(L)

1

1

C624

0.1U_0402_16V4Z

2

2

C625

2

0.1U_0402_16V4Z

1

2

0.1U_0402_16V4Z

1

2

1 2

R536 0_0805_5%

C610

GIGA@

CTRL18

1

GIGA@

22U_A_4VM

1

2

0.1U_0402_16V4Z

reserved for RTL8110S

Q28

C615

C611

+

1

2

2SB1188_SC62

GIGA@

40mil

2 3

1

2

C612

0.1U_0402_16V4Z

+1.2V_LAN

1

C616

0.1U_0402_16V4Z

2

GIGA@

pop when use 8110SB(L)

40mil

1

1

C626

C627

0.1U_0402_16V4Z

2

0.1U_0402_16V4Z

Title

Size Document Number Rev

Date: Sheet

1

C628

0.1U_0402_16V4Z

2

2

Compal Electronics, Inc.

LAN RTL8110SB(L)

1 2

R544 0_0805_5%

1 2

R547 0_0805_5%

reserved for 8100C(L)

HDL75 LA3041

GIGA@

100@

34 60Thursday, July 28, 2005

1

+1.2V_LAN
+2.5V_LAN

0.1

of

5

4

3

2

1

D D

LAN_MIDI0+<34>
LAN_MIDI0-<34>

LAN_MIDI1+<34>
LAN_MIDI1-<34>

C C

B B

LAN_MIDI2+<34>
LAN_MIDI2-<34>

LAN_MIDI3+<34>
LAN_MIDI3-<34>

Close to Chip side

R552

49.9_0402_1%

49.9_0402_1%

GIGA@

R558

1

C632

0.01U_0402_16V7K

2

12

12

R553

49.9_0402_1%

12

12

R559

49.9_0402_1%

GIGA@

1

C640

0.01U_0402_16V7K

2

49.9_0402_1%

49.9_0402_1%

R554

R560

GIGA@

1

C633

0.01U_0402_16V7K

2

12

12

R555

49.9_0402_1%

LAN_MDI0+
LAN_MDI0-

LAN_MDI1+
LAN_MDI1-

LAN_MDI2+
LAN_MDI2-

LAN_MDI3-

12

12

R561

49.9_0402_1%

GIGA@

1

C641

0.01U_0402_16V7K

2

unpop MIDI2+- MIDI3+- termination
resistor when use RTL8100C
Close to Chip side

+2.5V_LAN

12

R551
0_0805_5%

0.01U_0402_16V7K

1

C636

2

0.01U_0402_16V7K

GIGA@

0.01U_0402_16V7K

GIGA@

1

1

C638

C637

2

2

When 8110SBL C636-639 pop 0.01u,
When use RTL8100C C977 pop 0.1U

24ST8515A-2 for RTL8100C(10/100)
24HST1041A-2 for RTL8110SB(GbE)

GIGA@

R597 0_0402_5%

1 2

GIGA@

1

C639

2

0.01U_0402_16V7K

GIGA@

T16

1

TCT1

2

TD1+

3

TD1-

4

TCT2

5

TD2+
TD2-6MX2-

7

TCT3

8

TD3+

9

TD3-

10

TCT4

11

TD4+

12

TD4-

0.5u_24HST1041A-2

1

C977

2

0.1U_0402_16V7K

100@

MCT1

MX1+

MX1-

MCT2

MX2+

MCT3

MX3+

MX3-

MCT4

MX4+

MX4-

24
23
22

21
20
19

18
17
16

15
14
13

75_0402_1%

R568

12

12

RJ45_MDI0+
RJ45_MDI0-

RJ45_MDI1+
RJ45_MDI1-

RJ45_MDI2+
RJ45_MDI2-

RJ45_MDI3+LAN_MDI3+
RJ45_MDI3-

R569
75_0402_1%

J21

RJ45_MDI0+
RJ45_MDI0­RJ45_MDI1+
RJ45_MDI2+
RJ45_MDI2­RJ45_MDI1­RJ45_MDI3+
RJ45_MDI3-

MOD_RING
MOD_TIP

RJ45_GND LANGND

C642
1000P_1206_2KV7K

10

1 2

1

P1_1

2

P1_2

3

P1_3

4

P1_4

5

P1_5

6

P1_6

7

P1_7

SHLD_2

P1_88SHLD_1

RJ45

9

P2_1
P2_2

RJ11

TYCO_4-1470619-1

1

2

0.1U_0402_16V4Z

C643

12
11

1

C644

4.7U_0805_10V4Z

2

This area do not connect to power plan

12

12

R562

75_0402_1%

A A

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SE CRET INFO RMATI ON. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

R563
75_0402_1%

RJ45_GND

3

include Vcc and GND in any layer

2

MOD_RING

MOD_TIP

L22 CHB1608U301_0603

1 2
1 2

L26 CHB1608U301_0603

Title

Size Document Number Rev

Date: Sheet of

JP23

1
2

EDL71_MDC

Compal Electronics, Inc.

LAN Magnetic & RJ45/RJ11

HDL75 LA3041

35 60Thursday, July 28, 2005

1

0.1

5

4

3

2

1

D19

WL_ON<40>

D D

ICH_GPIO2_PIRQH#<26,37>

CLK_PCI_MINI<16>

PCI_REQ1#<26>

PCI_C_BE3#<26,31,33,34,37>

PCI_C_BE2#<26,31,33,34,37>

PCI_IRDY#<26,31,33,34,37>

+5VS

PCI_AD0
PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD6
PCI_AD7
PCI_AD8
PCI_AD9
PCI_AD10
PCI_AD11
PCI_AD12
PCI_AD13
PCI_AD14
PCI_AD15
PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20
PCI_AD21
PCI_AD22
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30
PCI_AD31

PM_CLKRUN#<28,34,37,40,42>

PCI_SERR#<26,31,34,37>
PCI_PERR#<26,31,33,34,37>

PCI_C_BE1#<26,31,33,34,37>

W=30mils

C C

Place closely pin 25

CLK_PCI_MINI

R629
10_0402_5%

@

1 2
2

C702

4.7P_0402_50V8C

1

@

B B

PCI_AD[0..31]<26,31,33,34,37>

A A

5

21

CH751H-40_SC76

+3VS

2

C704

0.047U_0402_16V4Z

1

ICH_GPIO2_PIRQH#

CLK_PCI_MINI
PCI_REQ1#
PCI_AD31

PCI_AD29
PCI_AD27

PCI_AD25
PCI_C_BE3#

PCI_AD23
PCI_AD21

PCI_AD19
PCI_AD17

PCI_C_BE2#
PCI_IRDY#

PM_CLKRUN#
PCI_SERR#

PCI_PERR#
PCI_C_BE1#
PCI_AD14

PCI_AD12
PCI_AD10

PCI_AD8
PCI_AD7

PCI_AD5
PCI_AD3
PCI_AD1

+3VS

W=40mils

2

C705

0.047U_0402_16V4Z

1

4

JP27

1

1

mPCI

3

3

5

5

7

7

9

9

11

11

13

13

15

15

17

17

19

19

21

21

23

23

25

25

27

27

29

29

31

31

33

33

35

35

37

37

39

39

41

41

43

43

45

45

47

47

49

49

51

51

53

53

55

55

57

57

59

59

61

61

63

63

65

65

67

67

69

69

71

71

73

73

75

75

77

77

79

79

81

81

83

83

85

85

87

87

89

89

91

91

93

93

95

95

97

97

99

99

101

101

103

103

105

105

107

107

109

109

111

111

113

113

115

115

117

117

119

119

121

121

123

123

125

GND

SUPER_AKE-1201-060

2

C706

0.047U_0402_16V4Z

1

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

GND

2

2

4

4

6

6

8

8

10

10

12

12

14

14

16

16

18

18

20

20

22

22

24

24

26

26

28

28

30

30

32

32

34

34

36

36

38

38

40

40

42

42

44

44

46

46

48

48

50

50

52

52

54

54

56

56

58

58

60

60

62

62

64

64

66

66

68

68

70

70

72

72

74

74

76

76

78

78

80

80

82

82

84

84

86

86

88

88

90

90

92

92

94

94

96

96

98

98

100

100

102

102

104

104

106

106

108

108

110

110

112

112

114

114

116

116

118

118

120

120

122

122

124

124

126

+3VS

W=40mils

LED_WLAN24
LED_WLAN5

2

1

2

C707

0.047U_0402_16V4Z

1

3

R623 100K_0402_5%
R624 100K_0402_5%

ICH_GPIO2_PIRQG#

PCI_RST#
PCI_GNT1#
MINI_PME#
PCI_AD30
PCI_AD28

PCI_AD26
PCI_AD24
MINIDSEL_1

PCI_AD22
PCI_AD20
PCI_PAR
PCI_AD18
PCI_AD16

PCI_FRAME#
PCI_TRDY#
PCI_STOP#

PCI_DEVSEL#
PCI_AD15

PCI_AD13
PCI_AD11

PCI_AD9
PCI_C_BE0#

PCI_AD6
PCI_AD4
PCI_AD2
PCI_AD0

+3V

W=40mils

C703

0.1U_0402_16V4Z

2

C708

0.047U_0402_16V4Z

1

1 2
1 2

W=30mils

ICH_GPIO2_PIRQG# <26,37>

W=40mils

PCI_RST# <26,31,33,37,42>
PCI_GNT1# <26>
MINI_PME# <26,31,33,34,37,40,41>

1 2

R628

100_0402_5%

PCI_PAR <26,31,33,34,37>

PCI_FRAME# <26,31,33,34,37>
PCI_T R D Y # <26,31,33,34,37>
PCI_STOP# <26,31,33,34,37>

PCI_DEVSEL# <26,31,33,34,37>

PCI_C_BE0# <26,31,33,34,37>

R630

10K_0402_5%

1 2

Power source

2

C709

0.047U_0402_16V4Z

1

PCI_AD18

+3V

2

C700

0.1U_0402_16V4Z

1

2

C710

0.047U_0402_16V4Z

1

2

+5VS

+3V

2

C701

0.1U_0402_16V4Z

1

2

C711

0.047U_0402_16V4Z

1

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

MINIPCI

2

C712

0.047U_0402_16V4Z

1

HDL75 LA3041

1

36 60Thursday, July 28, 2005

0.1

5

4

3

2

1

LAN RESERVED

D D

ICH_GPIO2_PIRQG#<26,36>

CLK_PCI_MINI1<16>

PCI_REQ4#<26>

PCI_C_BE3#<26,31,33,34,36>

PCI_C_BE2#<26,31,33,34,36>

PCI_IRDY#<26,31,33,34,36>

PM_CLKRUN#<28,34,36,40,42>

+5VS

PCI_SERR#<26,31,34,36>
PCI_PERR#<26,31,33,34,36>

PCI_C_BE1#<26,31,33,34,36>

W=30mils

C C

B B

PCI_AD[0..31]<26,31,33,34,36>

A A

5

PCI_AD0
PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD6
PCI_AD7
PCI_AD8
PCI_AD9
PCI_AD10
PCI_AD11
PCI_AD12
PCI_AD13
PCI_AD14
PCI_AD15
PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20
PCI_AD21
PCI_AD22
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30
PCI_AD31

ICH_GPIO2_PIRQG#

CLK_PCI_MINI1 PCI_RST#
PCI_REQ4#
PCI_AD31

PCI_AD29
PCI_AD27

PCI_AD25
PCI_C_BE3#

PCI_AD23
PCI_AD21

PCI_AD19
PCI_AD17

PCI_C_BE2#
PCI_IRDY#

PM_CLKRUN#
PCI_SERR#

PCI_PERR#
PCI_C_BE1#
PCI_AD14

PCI_AD12
PCI_AD10

PCI_AD8
PCI_AD7

PCI_AD5
CVBS_IN
PCI_AD3

PCI_AD1

AUDIO_INL

Power source

+3VS

2

C963

TV@

0.047U_0402_16V4Z

1

+3VS

W=40mils

2

C964

TV@

0.047U_0402_16V4Z

1

4

LAN RESERVED

JP37

2

112

KEY KEY

4

334

6

556

8

778

10

9910

12

111112

14

131314

16

151516

18

171718

20

191920

22

212122

24

232324

26

252526

28

272728

30

292930

32

313132

34

333334

36

353536

38

373738

40

393940

42

414142

44

434344

46

454546

48

474748

50

494950

52

515152

54

535354

56

555556

58

575758

60

595960

62

616162

64

636364

66

656566

68

676768

70

696970

72

717172

74

737374

76

757576

78

777778

80

797980

82

818182

84

838384

86

858586

88

878788

90

898990

92

919192

94

939394

96

959596

98

979798

100

9999100

101
103
105
107
109
111
113
115
117
119
121
123

102

101

102

104

103

104

106

105

106

108

107

108

110

109

110

112

111

112

114

113

114

116

115

116

118

117

118

120

119

120

122

121

122

124

123

124

AMP_1318644-1

TV@

2

C965

TV@

0.047U_0402_16V4Z

1

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

+3VS

W=40mils

S_CINS_YIN

AUDIO_INR

2

1

2

C966

TV@

0.047U_0402_16V4Z

1

ICH_GPIO2_PIRQH#

PCI_GNT4#
MINI_PME#
PCI_AD30
PCI_AD28

PCI_AD26
PCI_AD24
MINIDSEL

PCI_AD22
PCI_AD20
PCI_PAR
PCI_AD18
PCI_AD16

PCI_FRAME#
PCI_TRDY#
PCI_STOP#

PCI_DEVSEL#
PCI_AD15

PCI_AD13
PCI_AD11

PCI_AD9
PCI_C_BE0#

PCI_AD6
PCI_AD4
PCI_AD2
PCI_AD0
TV_AUDIO_R
TV_AUDIO_L

+3V

W=40mils

C962

0.1U_0402_16V4Z

TV@

3

W=30mils

ICH_GPIO2_PIRQH# <26,36>

W=40mils

PCI_RST# <26,31,33,36,42>
PCI_GNT4# <26>
MINI_PME# <26,31,33,34,36,40,41>

1 2

R1042

100_0402_5%

PCI_PAR <26,31,33,34,36>

PCI_FRAME# <26,31,33,34,36>
PCI_T R D Y # <26,31,33,34,36>
PCI_STOP# <26,31,33,34,36>

PCI_DEVSEL# <26,31,33,34,36>

PCI_C_BE0# <26,31,33,34,36>

TV_AUDIO_R <43>
TV_AUDIO_L <43>

R1044

10K_0402_5%

TV@

1 2

2

C967

TV@

0.047U_0402_16V4Z

1

PCI_AD19

TV@

TO Codec

+3V

2

1

AUDIO_INR
S_YIN

AUDIO_INL
S_CIN
CVBS_IN

C968

TV@

0.047U_0402_16V4Z

2

1

W=12mils space 12mil

+3V

C959

0.1U_0402_16V4Z

TV@

L87 0_0402_5%TV@
L88 0_0402_5%TV@

L89 0_0402_5%TV@
L90 0_0402_5%TV@
L91 0_0402_5%TV@

2

C969

TV@

0.047U_0402_16V4Z

1

2

+5VS

2

C960

0.1U_0402_16V4Z

TV@

1

RF

JP38

1
2
3

ANIMA_FR-003-000-A

TV@

AV IN

JP39

1 2
1 2

1 2
1 2
1 2

2

C970

TV@

0.047U_0402_16V4Z

1

Title

Size Document Number Rev

Date: Sheet of

1
2
3
4
5
6
7

SUYIN_33007SR-07T1-C

TV@

2

C971

TV@

0.047U_0402_16V4Z

1

Compal Electronics, Inc.

MINIPCI

HDL75 LA3041

37 60Thursday, July 28, 2005

1

0.1

5

4

3

2

1

MDC Conn.

JP17

1

MONO_OUT/PC_BEEP

3

GND

5

AUXA_RIGHT

D D

ICH_SDOUT_MDC<27>

ICH_RST_MDC#<27>

R521

R520

1 2

@

1 2

100K_0402_5%

CP_PE#
CP_USB#

+3VS_MDC

CHB1608B121_0603

+3VALW

12

R1103

@

+5VALW

RCIRRX<40>

12

R1104
100K_0402_5%

@

0_0603_5%

+3V
+3VS

C C

B B

A A

7

AUXA_LEFT

9

CD_GND

11

CD_RIGHT

13

CD_LEFT

15

GND

17

3.3Vaux

19

GND

21

3.3Vmain

23

AC97_SDATA_OUT

25

AC97_RESET#

27

GND

29

AC97_MSTRCLK

ACES_88021-3000

+3VS_MDC +5VS_MDC +3V

1

C603

@

1U_0603_10V4Z

2

Near to Express Card slot.

+1.5VS +3VS +3VALW

1

C1069

@

0.1U_0402_16V4Z

2

J25

1

RCIRRX

2
3

ACES_85205-0300

TV@

AUDIO_PWDN

MONO_PHONE

Bluetooth Enable

PRIMARY DN

AC97_SYNC
AC97_SDATA_IN1
AC97_SDATA_IN0

AC97_BITCLK

1

@

2

1

C1065

@

0.1U_0402_16V4Z

2

GND

+5V

USB Data+

USB Data-

5Vd

GND

GND

C604
1U_0603_10V4Z

1

@

2

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30

C1064

0.1U_0402_16V4Z

+5VS_MDC

1 2

1 2

R522 22_0402_5%
R523 22_0402_5%

R524 22_0402_5%

1

C605
1U_0603_10V4Z

2

1 2

+3VALW

12

A

13

B

+3VALW

9

A

10

B

12
12

@

14

P

O

G

7

14

P

O

G

7

MD_SPK <43>

R525

10_0402_5%

1 2
1

C602

22P_0402_25V8K@

2

11

8

R518

R519

10K_0402_5%

12

R526

@

10K_0402_5%

CHB1608B121_0603 @

U65D

SN74LVC08APW_TSSOP14

@

U65C

SN74LVC08APW_TSSOP14

@

+5VS

+3VS

ICH_SYNC_MDC <27>

ICH_AC_SDIN1 <27>

ICH_AC_BITCLK <27,43>

+3VALW

USBP1-<28>
USBP1+<28>

+3VS

+3VALW

+1.5VS

@

R1137 100K_0402_5%
R1138 100K_0402_5%@

EXPRESSCARD_RST#<28>

PLTRST#<9,26,28,34,40,45>

1 2

SUSP#<34,40,43,45,46>
SYSON<40,46,51>

12

PLTRST#

C1091

0.1U_0402_16V4Z @

PLTRST#
EXPRESSCARD_RST#

Express Card Conn.

USBP1-

R1099 0_0402_5%

1 2

R1100 0_0402_5%

1 2

PCIE_TXN0<28>
PCIE_TXP0<28>

PCIE_RXN0<28>
PCIE_RXP0<28>

U68

@

3.3Vin1

3.3Vin2

3.3Vaux_in

1.5Vin1

1.5Vin2

CPUSB#
CPPE#
STBY#
SHDN
SYSRST#

GND

NC11NC210NC312NC413NC5

11

U65A

NC_PERST#

3

SN74LVC08APW_TSSOP14

@

CP_USB#
CP_PE#

1 2

USBP1+

ICH_SMBCLK<16,28>
ICH_SMBDATA<16,28>

+1.5VS_CARD

ICH_PCIE_WAKE#<28,40>

+3VALW_CARD
+3VS_CARD

CLK_PCIE_CARD#<16>
CLK_PCIE_CARD<16>

5
6

21

18
19

14
15

4
3
2

+3VALW

14

1

P

A

O

2

B

G

7

ICH_PWRGD<28,40>

@

CP_USB#

@

ICH_PCIE_WAKE#
PERST#

CP_PE#

PCIE_TXN0
PCIE_TXP0

PCIE_RXN0
PCIE_RXP0

7

3.3Vout1

8

3.3Vout2

20

Aux_out

16

1.5Vout1

17

1.5Vout2

23

OC#

22

RCLKEN

9

PERST#

TPS2231PWPR_PWP24

24

4
5

USBP1-_EXP
USBP1+_EXP

+3VS_CARD

+3VALW_CARD

+1.5VS_CARD

PERST#

+3VALW

14

U65B

P

A

6

O

B

G

SN74LVC08APW_TSSOP14

7

@

JP40

@

1

GND

2

USB_D-

3

USB_D+

4

CPUSB#

5

RSV

6

RSV

7

RSV

8

SMB_CLK

9

SMB_DATA

10

+1.5V

11

WAKE#

12

+3.3VAUX

13

PERST#

14

+3.3V

15

+3.3V

16

CLKREQ#

17

CPPE#

18

REFCLK-

19

REFCLK+

20

GND

21

PERn0

22

PERp0

23

GND

24

PETn0

25

PETp0

26

GND

FOX_331-1CX41201-X1_1

40mil

40mil

40mil

USB_OC1# <28>

PCIECARD_CLKEN <16,40>

1 2

R1109 0_0402_5%@

PERST#

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

MDC Express Card Conn.

HDL75 LA3041

38 60Thursday, July 28, 2005

1

of

0.1

5

4

3

2

1

USB PORT#

C589

@

USBP3_VCC

USBP3_GND

USBP0_VCC

USBP0-<28>

USBP0+<28>

USBP0_GND

USBP0­USBP0+

JP11

@

1

VBUS

USBP3-<28>

USBP3+<28>

USBP3-

USBP3+

S_GND

2

D-

3

D+

4

GND

S_GND

TYCO_3-1470859-1

5

6

+USBP0_PWR

C904

1

2

150U_4A_10VM

+

1

C591

2

470P_0402_50V7K

+USBP3_PWR

1

+

C903

2

D D

150U_4A_10VM

@

1

2

470P_0402_50V7K

JP12

1
2
3
4

SUYIN_020167MR004S511ZU

0
1
2
3
4

+USBP46_PWR

1

+

C593

2

150U_4A_10VM

+USBP46_PWR

C C

+5VALW

USBP4_VCC

1

C594

2

USBP4_GND

470P_0402_50V7K

USBP6_VCC

USBP6_GND

USBP4-<28>
USBP4+<28>

USBP6-<28>

USBP6+<28>

USBP4-

USBP4+

USBP6­USBP6+

USBP4+

USBP6-

USB Over Current

+USBP46_PWR

+3VALW

JP13

1

A_VCC

2

A_D-

3

A_D+

4

A_GND

5

B_VCC

6

B_D-

7

B_D+

8

B_GND

9

G1

10

G2

11

G3

12

G4

SUYIN_020122MR008S548ZL

U70

1

AS

2

GND

3

VDD

AD7414ART-0_SOT23-6~D

@

SDA

ALERT

SCL

D38

1

GND

IO2

USBP0-

USBP3+

USBP4-

6
5

USBP6+

4

+5VALW

2

IO1

SR05_SOT143

@

D39

1

GND

2

IO1

SR05_SOT143

@

+5VALW

1

@

2

VIN

IO2

VIN

C495

0.1U_0402_16V4Z

USBP0+

3

4

3

4

USBP3-

U30

1

GND

2

IN

3

IN

4

EN#

G528_SO8@

SYSON#

+5VALW

+5VALW

OUT
OUT
OUT

FLG

8
7
6
5

5
6
7

+USBP3_PWR

+3VALW

DESTINATION

JUSB1(JP12)
Express Card

JUSB2(JP11)

Reserve
JUSB3(JP13UP)
Reserve
JUSB3(JP13LOW)
Reserve

R1204
10K_0402_5%

@

1 2

1 2

R1201
10K_0402_5%@

@

1 2

R1162 0_0402_5%

1

C1134

@

0.1U_0402_16V4Z

2

USB_OC3# <28>

U66

1

GND

2

IN

B B

1

C954

0.1U_0402_16V4Z

2

3

IN

4

EN#

G528_SO8

SYSON#

8

OUT

7

OUT

6

OUT

5

FLG

SYSON# <46>

Note:
USB_AS=USB_BS=Trace width=40mils

A A

5

R1205
10K_0402_5%

1 2

1 2

R1202
10K_0402_5%

1 2

R1111 0_0402_5%

1 2

R1163 0_0402_5%

4

1

C1135

0.1U_0402_16V4Z

2

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

USB_OC4# <28>

USB_OC6# <28>

+USBP0_PWR

+5VALW

U61

1

GND

2

IN

3

IN

1

C957

0.1U_0402_16V4Z

2

3

4

EN#

G528_SO8

SYSON#

2

OUT
OUT
OUT

FLG

8
7
6
5

Title

Size Document Number Rev

Date: Sheet of

+3VALW

R1206
10K_0402_5%

1 2

1 2

R1203
10K_0402_5%

1 2

R1164 0_0402_5%

1

C1136

0.1U_0402_16V4Z

2

Compal Electronics, Inc.

USB 2.0 Port

HDL75 LA3041

USB_OC0# <28>

39 60Thursday, July 28, 2005

1

0.1

A

L66

+3VALW +EC_AVCC

1 1

2 2

3 3

4 4

1 2

CHB1608U800_0603

0.1U_0402_16V4Z

L67 CHB1608U800_0603

CLK_PCI_EC

12

R636
10_0402_5%

@

1

C725
15P_0402_50V8D

2

@

KBD_DATA
KBD_CLK

PS2_DATA
PS2_CLK

TP_DATA

TP_CLK

FSEL#
SELIO#
FRD#
EC_TINIT#

EC_SMD_1
EC_SMC_1

LID_SW#
KILL_SW#

EMAIL#
INTERNET#
MODE#

C713

1 2

RP31

1 8
2 7
3 6
4 5

10K_0804_8P4R_5%

1 2

10K_0402_5%

1 2

10K_0402_5%

RP33

1 8
2 7
3 6
4 5

10K_0804_8P4R_5%

RP34

1 8
2 7
3 6
4 5

10K_0804_8P4R_5%

1 2

100K_0402_5%

1 2

100K_0402_5%

1 2

10K_0402_5%

2

1

R1150

R1151

R297
R299
R11

A

ECAGND

+3VALW

+5VS

+3VALW

+3VALW

+3VALW

1

C714
1000P_0402_50V7K

2

R633

1 2

47K_0402_5%

C723

0.1U_0402_16V4Z

ECAGND

2

1

10P_0402_50V8J

ICH_PCIE_WAKE#<28,38>

+3VALW

1

C715

2

0.1U_0402_16V4Z

EC_SCI#<28>

KSO[0..15]<42>

1

C727

2

0.1U_0402_16V4Z

LPC_LAD[0..3]<27,42>

KSI[0..7]<42>

1

C716

2

LPC_LFRAME#<27,42>

CLK_PCI_EC<16,42>

EC_A20GATE<27>
EC_RCIN#<27>

KBD_CLK

KBD_DATA

PS2_CLK

PS2_DATA

TP_DATA<42>

EC_RSMRST#<28>

CD_PLAY<43,45>

EC_IDERST<43,45>

EC_MUTEO<44>

EC_SLP_S4#<28>
IOMP_LED#<42>
PM_CLKRUN#<28,34,36,37,42>
BACKLITE_ON<11,17,23>

SCROLLED#<42>

CAPSLED#<42>

NUMLED#<42>
EC_SMI#<28>
MSEN#<24>
WL_ON<36>

ICH_PCIE_W AKE#

PROCHOT#<5>

1 2

R650 20M_0603_5%@

1

2

B

0.1U_0402_16V4Z

1

C717

2

1000P_0402_50V7K

SIRQ<28,31,42>

EC_RST#

EC_SCI#

R634

1 2

0_0402_5%@

EC_A20GATE
EC_RCIN#
KSI[0..7]

KSO[0..15]

KSO17<42>

TP_CLK<42>

CRY1
CRY2

BKOFF#<23>

FSTCHG<48>

IN

CRY1
CRY2

EC_SCI#

EC_SLP_S4#

BACKLITE_ON

R1193 0_0402_5%

R651

1

4

C728
10P_0402_50V8J

2

Y3

32.768KHZ_12.5PF_6H03200468

OUT

NC3NC

B

1

2

LPC_LAD0
LPC_LAD1
LPC_LAD2
LPC_LAD3

KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7

KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14

KSO15
KSO16
KSO17

KBD_CLK
KBD_DATA
PS2_CLK
PS2_DATA
TP_CLK
TP_DATA

EC_SMI#

@

CRY1

CRY2

0_0603_5%

12

12

C718

7

9
15
14
13
10
18
19
31

5

6
71

72
73
74
77
78
79
80

49
50
51
52
53
56
57
58
59
60
61
64
65
66
67
68

153
154

110
111
114
115
116
117

158
160

3

4

8
20
21
22
23
24
25
27
28
41

48
54
55
62
63
69
70
75

1000P_0402_50V7K

1

C719

2

U39

SERIRQ
LFRAME#
LAD0/FWH0
LAD1/FWH1
LAD2/FWH2
LAD3/FWH3
LCLK
ECRST#
ECSCI#

GPIO02/GA20
GPIO03/KBRST#

KSI0/GPIK0
KSI1/GPIK1
KSI2/GPIK2
KSI3/GPIK3
KSI4/GPIK4
KSI5/GPIK5
KSI6/GPIK6
KSI7/GPIK7

KSO0/GPOK0
KSO1/GPOK1
KSO2/GPOK2
KSO3/GPOK3
KSO4/GPOK4
KSO5/GPOK5
KSO6/GPOK6
KSO7/GPOK7
KSO8/GPOK8
KSO9/GPOK9
KSO10/GPOK10
KSO11/GPOK11
KSO12/GPOK12
KSO13/GPOK13
KSO14/GPOK14
KSO15/GPOK15
KSO16/GPOK16
KSO17/GPOK17

PSCLK1
PSDAT1
PSCLK2
PSDAT2
PSCLK3
PSDAT3

XCLKI
XCLKO

GPIO00/E51IT0
GPIO01/E51IT1
GPIO04
GPIO07
GPIO08
GPIO09
NUMLOCK#/GPIO0A
GPIO0B
CLKRUN#/GPIO0C
GPIO0D
GPIO0E
SCROLLLOCK#/GPIO0F

GPIO10
CAPLOCK#/GPIO11
FNLOCK#/GPIO12
GPIO13

GPIO1

GPIO14
GPIO15
GPIO16
GPIO17

A0

124

KBA0

C

+EC_AVCC

ECAGND

C720

1U_0603_10V4Z

159

123

136

157

166

VCC016VCC134VCC245VCC3

VCC4

VCC5

VCC6

GND117GND235GND346GND4

PWR/GND

Host interface

Key matrix scan

PS2 interface

GPIO0

BIOS I/F

A1/XIOP_TP

A4/DMRP_TP

A5/EMWB_TP

125A2126A3127

128

131A6132A7133

KBA3

KBA1

KBA6

KBA2

KBA7

KBA5

KBA4

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

143A9142

KBA8

A8

KBA9

A13

A12

A11

A10

A14

A15

129

130

134

135

121

120

113

KBA14

KBA10

KBA13

KBA12

KBA11

KBA15

KBA16

C

122

A16

A17

A18

112

104

KBA19

KBA17

KBA18

95

167

137

VCCA

GND6

GND7

DA output or GPO

FAN/PWM

SM BUS

GPIO2

GPWU or GPI

D0

A19

138D1139D2140D3141D4144D5145D6146D7147

103

ADB0

ADB2

ADB1

96

161

AGND

AD Input or GPI

PWM
or GPOW

GPIO05/FAN3PWM/TEST_TP

ADB4

ADB3

AD0/GPIAD0
AD1/GPIAD1

VCCBAT

BATGND

AD2/GPIAD2
AD3/GPIAD3
AD4/GPIAD4
AD5/GPIAD5
AD6/GPIAD6
AD7/GPIAD7

DA0/GPODA0
DA1/GPODA1
DA2/GPODA2
DA3/GPODA3
DA4/GPODA4
DA5/GPODA5
DA6/GPODA6
DA7/GPODA7

PWM0/GPOW0
PWM1/GPOW1
PWM3/GPOW3
PWM4/GPOW4
PWM5/GPOW5
PWM6/GPOW6

PWM2/GPOW2/FAN1PWM
PWM7/GPOW7/FAN2PWM

FANFB1/TOUT1/GPIO2E

GPWU7/TIN2/FANFB2

GPIO06/FANFB3/DPLL_TP

GPIO20/E51CS#/ISPEN_TP

GPIO21/E51RXD/ISPCLK
GPIO22/E51TXD/ISPDAT

A20/GPIO23

LRST#/GPIO2C
TOUT2/GPIO2F

GPWU6/TIN1

GPIO18/XIO8CS#

GPIO19/XIO9CS#
GPIO1A/XIOACS#
GPIO1B/XIOBCS#

GPIO1C/XIOCCS#
GPIO1D/XIODCS#

GPIO1E/XIOECS#
GPIO1F/XIOFCS#

RD#

WR#

IOCS#

150

151

152

ADB7

ADB6

ADB5

173

1 2

1 2

12

81
82
83
84
87
88
89
90

99
100
101
102
1
42
47
174

32
33
37
38
39
40

36
43
11
171
176
12

163

SCL1

164

SDA1

169

SCL2

170

SDA2

105
106
107
108
109

GPIO24

118

GPIO25

119

GPIO26

148

GPIO27

149

GPIO28

155

GPIO29

156

GPIO2A

162

GPIO2B

165
168

GPIO2D

175
2

GPWU0

26

GPWU1

29

GPWU2

30

GPWU3

44

GPWU4

76

GPWU5

172
85

86
91
92
93
94
97
98

MEMCS#

KB910_LQFP176

SELIO#

ADB[0..7]
KBA[0..19]

@

INTERNET#

INVT_PWM

EC_TINIT#

BATT_LOW_LED#
MP3_LED#
CDON_LED#
BATT_FULL_LED#

AD_BID0

AD_SKU_ID

EMAIL#

VOL_AMP

TEST_TP

DPLL_TP

EC_SMC_1
EC_SMD_1
EC_SMC_2
EC_SMD_2

EC_TCK

EC_TDO

EC_TDI

EC_TMS

LID_SW#

EC_USCLK
PLTRST#

EC_THERM#

RCIRRX
EC_SLP_S3#
EC_SLP_S5#

PME_EC#

PWR_LED#

1 2

FSEL# <41>

SELIO#

FWR# <41>

FRD# <41>

ADB[0..7] <41>

KBA[0..19] <41>

D

R7920_0402_5%

+RTCVCC

For KB910 Rev:B4

R7930_0402_5%

+3VALW

C721

1 2

0.01U_0402_16V7K

BATT_TEMP <47>

BATT_OVP <48>

DAC_BRIG <23>
IREF <48>

EN_FAN1 <8>

INVT_PWM <23>
BEEP# <44>
ACOFF <48>
PM_BATLOW# <28>
EC_ON <42>
EC_LID_OUT# <28>

FANSPEED1 <8>

EC_SMC_1 <25,41,47>
EC_SMD_1 <25,41,47>
EC_SMC_2 <8>
EC_SMD_2 <8>

LID_SW # <42>
PCMRST# <45>
SYSON <38,46,51>

VR_ON <54>
MODE# <42>

PLTRST# <9,26,28,34,38,45>
EC_PWRBTN# <28>
EC_THRM# <28>

ON/OFF# <42>
ACIN <28,47,50>

RCIRRX <38>

EC_SLP_S3# <28>
EC_SLP_S5# <28>

PME_EC# <26,31,33,34,36,37,41>

R11740_0402_5% @

D

ECAGND

EMAIL# <42>

INTERNET# <42>

ICH_PWRGD <28,38>
VOL_AMP <44>

SUSP# <34,38,43,45,46>

KILL_SW# <42>

PWR_LED# <42>
BATT_LOW_LED# <42>

MP3_LED# <42>

CDON_LED# <42>
BATT_FULL_LED# <42>
EAPD <43,44>
WL_LED# <42>
PCIECARD_CLKEN <16,38>

+3VALW

12

R646

Ra

100K_0402_5%

AD_BID0

12

Rb Rb

1

R647
200K_0402_5%

@

C726

0.1U_0402_16V4Z

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

KBD EC CTRL-ENE KB910

D40

1

2

SR05_SOT143

KBA0
KBA1
KBA2
KBA3
KBA4
KBA5

TEST_TP
DPLL_TP

PLTRST#

EC_TINIT#

EC_TCK
EC_TDO
EC_TDI
EC_TMS

KSO16
KSO17
EC_USCLK

+3VALW

Ra

HDL75 LA3041

E

GND

IO1

12

12

3

IO2

4

VIN

R635 10K_0402_5%

1 2
1 2
1 2
1 2
1 2
1 2

1 2

+5VALW

AD_SKU_ID

1

2

E

@
@
@
@
@

R596

100K_0402_5%

JP28

1
2
3
4
5
6
7
8
9
10

ACES_85201-1005@

C972

0.1U_0402_16V4Z

40 60Thursday, July 28, 2005

R637 10K_0402_5%
R638 10K_0402_5%
R639 10K_0402_5%
R640 10K_0402_5%
R641 10K_0402_5%

1 2

R517 10K_0402_5%

1 2

R583 10K_0402_5%

R1052
100K_0402_5%

R1053

8.2K_0402_5%

INVT_PWM

+5VALW

+3VALW

0.1

of

ADB[0..7]<40>

KBA[0..19]<40>

ADB[0..7]
KBA[0..19]

U40

KBA18

1

A18

KBA16

2

A16

KBA15

3

A15

KBA12

4

A12

KBA7

5

A7

KBA6

6

A6

KBA5

7

A5

KBA4

8

A4

KBA3

9

A3

KBA2

10

A2

KBA1

11

A1

KBA0

12

A0

ADB0

13

DQ0

ADB1

14

DQ1

ADB2

15

DQ2

16

VSS

SST39VF040-70-4C-NH_PLCC32

1MB Flash ROM

KBA0
KBA1
KBA2
KBA3
KBA4
KBA5
KBA6
KBA7
KBA8
KBA9
KBA10
KBA11
KBA12
KBA13
KBA14
KBA15
KBA16
KBA17
KBA18
KBA19

FSEL#
FRD#
FWE#

U67

21

A0

20

A1

19

A2

18

A3

17

A4

16

A5

15

A6

14

A7

8

A8

7

A9

36

A10

6

A11

5

A12

4

A13

3

A14

2

A15

1

A16

40

A17

13

A18

37

A19

22

CE#

24

OE#

9

WE#

SST39VF080-70_TSOP40@

VDD
WE#

A17
A14
A13

A8
A9

A11

OE#

A10
CE#
DQ7
DQ6
DQ5
DQ4
DQ3

VCC0
VCC1

RP#

READY/BUSY#

NC0
NC1

GND0

GND1

+3VALW

32

FWE#

31

KBA17

30

KBA14

29

KBA13

28

KBA8

27

KBA9

26

KBA11

25

FRD#

24

KBA10

23

FSEL#

22

ADB7

21

ADB6

20

ADB5

19

ADB4

18

ADB3

17

31
30

ADB0

25

D0
D1
D2
D3
D4
D5
D6
D7

NC

ADB1

26

ADB2

27

ADB3

28

ADB4

32

ADB5

33

ADB6

34

ADB7

35

10

1 2

R1130

11

100K_0402_5%

12
29
38

23
39

2

1

FRD# <40>
FSEL# <40>

@

C730

0.1U_0402_16V4Z

+3VALW

1

C1098

@

0.1U_0402_16V4Z

2

+3VALW

C733

0.1U_0402_16V4Z

FWE#

+3VALW

12

R652
10K_0402_5%

+3VALW +5VS

+3VALW

R653

100K_0402_5%

2

O

U41

5

TC7SH32FU_SSOP5

2

P

I0

1

I1

G

3

1

4

12

12

R654
100K_0402_5%

2

G

1 3

D

S

Q29 2N7002_SOT23

EC_FLASH# <28>

FWR# <40>

1394_PME#<26,31,33,34,36,37,40>

PCM_PME#<26,31,33,34,36,37,40>
MINI_PME#<26,31,33,34,36,37,40>

LAN_PME#<26,31,33,34,36,37,40>
ICH_PME#<26,31,33,34,36,37,40>

C731

0.1U_0402_16V4Z

EC_SMC_1<25,40,47>
EC_SMD_1<25,40,47>

1

2

12

R660
100K_0402_5%

U43

8
7
6
5

A0

VCC

A1

WP
SCL

A2

SDA

GND

AT24C16AN-10SI-2.7_SO8

PME_EC# <26,31,33,34,36,37,40>

+3VALW+3VALW

12

1
2
3
4

12

R657
100K_0402_5%

R659
100K_0402_5%

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

BIOS & EC I/O Port

HDL75 LA3041

41 60Thursday, July 28, 2005

of

0.1

5

4

3

2

1

INT_KBD CONN.

KSI[0..7]
KSO[0..15]

JP29

KSI1

1

KSI7

2

D D

C C

KSI6
KSO9
KSI4
KSI5
KSO0
KSI2
KSI3
KSO5
KSO1
KSI0
KSO2
KSO4

KSO8
KSO6
KSO3
KSO12
KSO13
KSO14
KSO11
KSO10
KSO15

3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

ACES_85203-2402

25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48

KSI[0..7] <40>
KSO[0..15] <40>

25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48

KSI1
KSI7
KSI6
KSO9
KSI4
KSI5
KSO0
KSI2
KSI3
KSO5
KSO1
KSI0
KSO2
KSO4
KSO7KSO7
KSO8
KSO6
KSO3
KSO12
KSO13
KSO14
KSO11
KSO10
KSO15

KSI0

C1102 100P_0402_50V8K

KSO1

C1103 100P_0402_50V8K

KSO5

C1104 100P_0402_50V8K

KSI3

C1105 100P_0402_50V8K

KSO8

C1106 100P_0402_50V8K

KSO7

C1107 100P_0402_50V8K

KSO4

C1108 100P_0402_50V8K

KSO2

C1109 100P_0402_50V8K

KSO9

C1110 100P_0402_50V8K

KSI6

C1111 100P_0402_50V8K

KSI7

C1112 100P_0402_50V8K

KSI1

C1113 100P_0402_50V8K

KSI2

C1114 100P_0402_50V8K

KSO0

C1115 100P_0402_50V8K

KSI5

C1116 100P_0402_50V8K

KSI4

C1117 100P_0402_50V8K

KSO15

C1118 100P_0402_50V8K

KSO10

C1119 100P_0402_50V8K

KSO11

C1120 100P_0402_50V8K

KSO14

C1121 100P_0402_50V8K

KSO13

C1122 100P_0402_50V8K

KSO12

C1123 100P_0402_50V8K

KSO3

C1124 100P_0402_50V8K

KSO6

C1125 100P_0402_50V8K

INTERNET_BTN#

EMAIL_BTN#

D30

1

DAN202U_SC70

D31

1

DAN202U_SC70

INTERNET#

3

51ON#

2

EMAIL#

3

51ON#

2

LID_SW#<40>

LID Switch

LID_SW#

INTERNET# <40>

EMAIL# <40>

Power BTN

D21

1

DAN202U_SC70
Q30

DTC124EK_SC59

R661 100K_0402_5%

1 2

3

51ON#

2

13

2

1000P_0402_50V7K

SW DJ

ON/OFF#

1

2

C732

ON/OFF# <40>

51ON# <49>

(51ON#)

12

D22
RLZ20A_LL34

WHEN R=0,Vbe=1.35V
WHEN R=33K,Vbe=0.8V

+3VALW

ESE11MV9_4P

2

4

SW1

IDE_LED#<30>

IDE_LED#

MMBT3904_SOT23

1 2
2

3 1

Q96

1

3

EC_ON<40>

HD_IDERST# <30,45>

R1189
10K_0402_5%

EC_ON

ON/OFFBTN#

+3VALW

12

R662
100K_0402_5%

1 2

R663 0_0402_5%

PWR_LED#<40>
BATT_LOW_LED#<40>
BATT_FULL_LED#<40>

CDON_LED#<40>

TO PWR /LED BOARD

JP31

SCROLLED#<40>

CAPSLED#<40>

NUMLED#<40>

B B

+5VS

SCROLLED#
CAPSLED#
NUMLED#

1 2
3 4
5 6
7 8
9 10

ACES_85203-1002

PWR_LED#

ON/OFFBTN#
INTERNET_BTN#
EMAIL_BTN#

+5VALW

PWR_LED# <40>

INTERNET_BTN#

EMAIL_BTN#

FRDBTN#

STOPBTN#

REVBTN#

PLAYBTN#

VOL_UP
VOLDN

MP3_LED#<40>
WL_LED#<40>

+5VALW +5VALW
KILL_SW#<40>

MODE#<40>
KSO17<40>

KSI0<40>
KSI1<40>
KSI2<40>
KSI3<40>
KSI4<40>
KSI5<40>

IOMP_LED#<40>

PWR_LED#
BATT_LOW_LED#
BATT_FULL_LED#
SWDJ_IDE_LED#
CDON_LED#
MP3_LED#
WL_LED#

KILL_SW#
51ON#
MODE#
KSO17
KSI0
KSI1
KSI2
KSI3
KSI4
KSI5

JP30

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

11

11

12

12

13

13

14

14

15

15

16

16

17

17

18

18

19

19

20

20

ACES_85203-2002

21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40

21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40

PWR_LED#

BATT_LOW_LED#

BATT_FULL_LED#

SWDJ_IDE_LED#

CDON_LED#

MP3_LED#

WL_LED#

KILL_SW#

51ON#

MODE#

KSO17

KSI0
KSI1
KSI2
KSI3
KSI4
KSI5

IOMP_LED#

FOR LPC SIO DEBUG PORT

JP32

A A

ACES_85201-2005

@

5

+5VS

1

1

2

2

3

3

4

4

5

5

CLK_SIO_14M

6

6

LPC_LAD0

7

7

LPC_LAD1

8

8

LPC_LAD2

9

9

LPC_LAD3

10

10

LPC_FRAME#

11

11

LPC_DRQ1# TP_CLK TP_DATA

12

12

PCIRST#

13

13

PM_CLKRUN#

14

14

15

15

16

16

17

17

18

18

19

19

20

20

+3VS

CLK_SIO_14M <16>

LPC_LFRAME# <27,40>

LPC_LDRQ1# <27>

PCI_RST# <26,31,33,36,37>
PM_CLKRUN# <28,34,36,37,40>
CLK_PCI_EC <16,40>

SIRQ <28,31,40>

LPC_LAD[0..3] <27,40>

4

C9730.1U_0402_16V4Z

ACES_87153-0801-01

7

JP34

8

5

6

3

4

1

2

TP_CLK<40>

12

+5VS

TP_DATA <40>

T/P

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

KBD,ON/OFF,T/P,LED & FIR

HDL75 LA3041

42 60Thursday, July 28, 2005

1

of

0.1

5

+5VALW

C974

0.1U_0402_16V4Z

12

R421

AC97_L AMP_LEFT

+5VAMP

D D

+5VAMP

AC97 Codec

1

C C

B B

2

MD_SPK<38>

ICH_RST_AUDIO#<27>
ICH_SYNC_AUDIO<27>
ICH_SDOUT_AUDIO<27>

C515

0.1U_0402_16V4Z

1M_0402_5%

R428

1M_0402_5%

EC_IDERST<40,45>

NBA_PLUG<44>

MIC<44>

@

0.01U_0402_16V7K
C535

10K_0402_5%@

12

12

R424
1M_0402_5%

AC97_R AMP_RIGHT

12

12

R430
1M_0402_5%

EC_IDERST

+5VAMP

1

C516
10U_0805_10V4Z

2

TV_AUDIO_L<37>
TV_AUDIO_R<37>

1U_0603_10V4Z

@

1 2

C520

D16 RB751V_SOD323

1 2

12

R439

1 2

0_0402_5%

MONO_IN<44>

ICH_RST_AUDIO#
ICH_SYNC_AUDIO
ICH_SDOUT_AUDIO

R453
0_0402_5%

1 2

R440

14

P

G7C

14

P

G7C

L54

1 2

0_0603_5%

TV_AUDIO_L
TV_AUDIO_R

21

CD_GNA

1 2

C534 1U_0603_10V4Z

1 2

C536 1U_0603_10V4Z

1 2

C537 1U_0603_10V4Z

22_0402_5%
22_0402_5%
22_0402_5%

EAPD<40,44>

A1B

A4B

POWER ON PATH

U19A

2

SN74HCT4066PW_TSSOP14

13

U19C

SN74HCT4066PW_TSSOP14

5

0.1U_0402_16V4Z

CD_L
CD_R

C_MD_SPK

@

R1175 0_0402_5%

1 2

3

@

R1176 0_0402_5%

1 2

1

C552

U21

2

14
15
16
17
23
24
18
20
19

C_MIC

21
22
13
12

R443

11

12

R445

10

12

R446

5

12

45
46

47
48

4
7

ALC250-VD_LQFP48

+AVDD_AC97

38

AVDD125AVDD2
AUX_L
AUX_R
JD2

MONO_OUT/VREFOUT3
JD1
LINE_IN_L
LINE_IN_R
CD_L
CD_R
CD_GND
MIC1
MIC2
PHONE
PC_BEEP

RESET#
SYNC
SDATA_OUT
SDA

XTLSEL
SPDIFI/EAPD
SPDIFO
DVSS1

DVSS2

EC_IDERST_1

DGND AGND

+5VALW

R456

A A

EC_IDERST_1

1 2
13

D

S

10K_0402_5%

Q18
2N7002_SOT23

1 2

2

G

0_0603_5%@

1 2

R1051 0_0603_5%

5

R1050

EC_IDERST

SUSP#

SUSP# <34,38,40,45,46>

+5VAMP

+5VAMP

DVDD11DVDD2

LINE_OUT_L

LINE_OUT_R

HP_OUT_L

HP_OUT_R

BIT_CLK

SDATA_IN

XTL_IN

XTL_OUT

AFILT1
AFILT2

VREFOUT

VREF

DCVOL

VREFOUT2

VAUX

DISABLE#

SCK

AVSS1
AVSS2

4

1U_0603_10V4Z

INT_CD_L

1M_0402_5%

1U_0603_10V4Z

INT_CD_R

1

2

0.1U_0402_16V4Z

9

LINEL

35

LINER

36
37
39
41

6
8

R436 22_0402_5%

2

3
29
30
28
27
32

31

NC

33
34
43
44

40

NC

AGND

26
42

Adjustable Output

4

C509

1 2

12

R422

12

C511

1 2

12

12

R429

1M_0402_5%

1

C551

C513

2

0.1U_0402_16V4Z

@

C517 1000P_0402_50V7K

@

C518 1000P_0402_50V7K

1 2

C519 1U_0603_10V4Z

1 2

C521 1U_0603_10V4Z

1 2

C522 47P_0402_50V8J

1 2

R434 22_0402_5%

1 2

1M_0402_5%@

C538 1000P_0402_50V7K
C541 1000P_0402_50V7K

@

R448 0_0402_5%

1 2

+5VALW

R425
1M_0402_5%

+5VALW+5VALW

R431
1M_0402_5%

Place very close to U44.2

+3VS

1

C514
10U_0805_10V4Z

2

12
12

ICH_AC_BITCLK

1 2

R435

10K_0402_5%@

R438

@

24.576MHz_16P_3XG-24576-43E1

1 2
12
12

+AUD_VREF

+AVDD_AC97

R451

1 2

0_0603_5%

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

14

U19B

P

10

A11B
G7C

SN74HCT4066PW_TSSOP14

12

14

U19D

P

9

A8B
G7C

SN74HCT4066PW_TSSOP14

6

3

DIRECT PLAY PATH

AMP_LEFT

AMP_RIGHT

+5VALWP TO +5VLDO

AMP_LEFT <44>

AMP_RIGHT <44>

CD_PLAY<40,45>

2

10K_0402_5%

CD_PLAY

R426

2

G

2N7002_SOT23

+5VLDO DECOUPLING

AC97_L
AC97_R

AC97_XTLIN

X4

1 2

1

C540

22P_0402_50V8J

2

1

C545

@

@

2

0.01U_0402_16V7K

ICH_AC_BITCLK <27,38>

ICH_AC_SDIN0 <27>

1

C539

2

22P_0402_50V8J @

1

1

C546

C547

2

2

1U_0603_10V4Z

0.1U_0402_16V4Z

3

+AVDD_AC97

ICH_AC_SDIN0

@

1

C544

@

2

1U_0603_10V4Z

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

+5VLDO

1

C523

2

1 2

R437 0_0402_5%

22U_1206_10V4Z

1

C524

2

4.7U_0805_10V4Z

CLK_CODEC_14M <16>

(4.5V)

1

2

4.7U_0805_10V4Z

Audio Signal Bias Circuit

R1165
1M_0402_5%

1 2

C548

INT_CD_L<30>
INT_CD_R<30>

1U_0603_10V4Z

R447 20K_0402_1%
R449 20K_0402_1%
R450 6.8K_0402_5%
R452 6.8K_0402_5%

1

2

CD_AGND To CD_GNA Bypass

CD_AGND<30>

R799
0_0603_5%

C525

1U_0603_10V4Z

12
12
12
12

1 2

1

C526

2

20K_0402_1%

R454

2

1

C527

1U_0603_10V4Z

2

12

R423 10K_0402_5%

1 2

+5VALW

+12VALW

12

12

13

2

G

13

D

Q17
2N7002_SOT23

S

1

C528

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

CD_L

1 2

C542 1U_0603_10V4Z

CD_R

1 2

C543 1U_0603_10V4Z

CD_GNA

12

R455

6.8K_0402_5%

1

+5VALW

S

Q15

G

2

SI2301BDS_SOT23

D

1 3

5

D8D7D6D

U20

S1S2S3G

4

+5VLDO

(4.5V)

12

R432

3.9K_0603_1%

2

K

3

R

12

R433

4.99K_0603_1%

R427
1K_0402_5%

D

Q16

S

1

C510

2

SI4800BDY_SO8

1U_0603_10V4Z

LM431SC_SOT23

1

D15

A

+5VALW DECOUPLING

+5VALW

1

1

C529

2

C530

1

1

C531

2

2

22U_1206_10V4Z

DGND To AGND Bypass

1U_0603_10V4Z

22U_1206_10V4Z

R441 0_0603_5%

1 2

R442 0_0603_5%

1 2

R444

1 2

C532

2

0_0603_5%

1

C533

2

1U_0603_10V4Z

DGND AGND

Analog Reference V

+AUD_VREF

1

1

C549

2

0.1U_0402_16V4Z

C550

2

1U_0603_10V4Z

+5VLDO TO +5VAMP

L56

0_0805_5%

+5VLDO +5VAMP

Title

Size Document Number Rev

Date: Sheet

1 2

L57

0_0805_5%

1 2

Compal Electronics, Inc.

AC_Link-Codec

HDL75 LA3041

43 60Thursday, July 28, 2005

1

0.1

of

A

Audio Amplifier

1

2

VOLAMP

C567

+5VAMP

C555

NBA_PLUG

1

2

W=40Mil

4 4

VOL_AMP<40>

AMP_LEFT<43>

AMP_RIGHT<43>

3 3

AMP_LEFT

0.47U_0603_16V4Z

AMP_RIGHT

0.47U_0603_16V4Z

AMP_LEFT

0.47U_0603_16V4Z

AMP_RIGHT

0.47U_0603_16V4Z

INTSPK_L1+
INTSPK_R1+

C558

1 2

C560

1 2

C562

1 2

C566

1 2

12

R465

@

1.5K_0603_5%

fo=1/(2*3.14*R*C)=225Hz
R=1.5K / C=0.47U

C975

R464 0_0402_5%

1 2

C559

1 2

1U_0603_10V4Z

C561

1 2

1U_0603_10V4Z

12

@

R466

1.5K_0603_5%

0.1U_0402_16V4Z

HP_L
HP_R

0.1U_0402_16V4Z

1

2

0.1U_0402_16V4Z

1

C568

2

0.047U_0402_16V4Z

B

1

C556

4.7U_0805_10V4Z

2

U23

7

PVDD

SHUTDOWN#

18

PVDD

19

VDD

2

HP/LINE#

3

VOLUME

4

LOUT+

21

ROUT+

5

LLINEIN

23

RLINEIN

6

LHPIN

20

RHPIN

17

CLK

TPA0232PWP_TSSOP24

SE/BTL#

PC-BEEP

BYPASS

LOUT-

ROUT-

GND
GND
GND
GND

22
15
14
11
9
16
10

LIN

8

RIN

1
12
13
24

+5VAMP

R459

100K_0402_5%

SHUTDOWN#

R462

100K_0402_5%

NBA_PLUG

C557 0.1U_0402_16V4Z

1 2

2

C563

1

0.47U_0603_16V4Z

+5VAMP

1 2

2

1

D

S

INTSPK_L2­INTSPK_R2-

C564

0.47U_0603_16V4Z

13

12

CH751H-40_SC76

Q19

2

G

2N7002_SOT23

12

R463

@

10K_0402_5%

2

C565

1

0.47U_0603_16V4Z

C

21

D35

CH751H-40_SC76

21

D36

Left Speaker Connector

Right Speaker Connector

EC_MUTEO <40>

EAPD <40,43>

NBA_PLUG<43>

CHANGE CONN

D

INTSPK_L1+
INTSPK_R1+

INTSPK_R2­INTSPK_R1-3 INTSPK_R1-3_C

INTSPK_L1-3
MIC-1

MIC-2

NBA_PLUG

L75 0_0603_5%

1 2

L77 0_0603_5%

1 2

L76 0_0603_5%

1 2

L78 0_0603_5%

1 2

L79 0_0603_5%

1 2

L80 0_0603_5%

1 2

L81 0_0603_5%

1 2

L82 0_0603_5%

1 2

L83 0_0603_5%

1 2

L92
0_0603_5%

1 2

INTSPK_L1+_C
INTSPK_L2-_CINTSPK_L2­INTSPK_R1+_C
INTSPK_R2-_C

INTSPK_L1-3_C
MIC-1_C

MIC-2_C
NBA_PLUG_C

ACES_85203-1202

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

11

11

12

12

JP36

E

INTSPK_L1+_C

13

13
14
15
16
17
18
19
20
21
22
23
24

14
15
16
17
18
19
20
21
22
23
24

INTSPK_L2-_C
INTSPK_R1+_C
INTSPK_R2-_C

INTSPK_R1-3_C
INTSPK_L1-3_C

MIC-1_C
MIC-2_C

NBA_PLUG_C

HEADPHONE OUT JACK

EC Beep

BEEP#<40>

2

C572

1

0.1U_0402_16V4Z

2 2

CardBus Beep

PCM_SPK#<31>

PCI Beep

+3VALW

+5VS

A2Y

12

5

1

U24

P

4

OE#

G

74AHCT1G125GW_SOT353-5

3

+3V POWER

+3VALW

R468
100K_0402_5%

R470

8.2K_0402_5%

1 2

+3VALW

1

1

C575

0.22U_0603_16V4Z

2

C578

1 2

1U_0603_10V4Z

1 2

C570 0.1U_0402_16V4Z

14

U25A

SN74LVC14APWLE_TSSOP14

P

O2I

G

+3V POWER

7

R475 560_0402_5%

1U_0603_10V4Z

1 2

1 2

C574

1 2

R471
560_0402_5%

System Beep To AC97' Codec

+AVDD_AC97

12

R472
10K_0402_5%

1

2

12

R473
10K_0402_5%

Q21
MMBT3904_SOT23

3 1

C576
10U_0805_10V4Z

2

1 2

C577 1U_0603_10V4Z

R476

2.4K_0402_5%

1 2

MONO_IN

MICROPHONE IN JACK

MONO_IN <43>

INTSPK_R1+
INTSPK_L1+

+AUD_VREF

C569

+

INTSPK_R1-2

1 2

150U_4A_6.3VM

+

INTSPK_L1-2

1 2

C571 150U_4A_6.3VM

MIC<43>

MIC-2
MIC-1

R467
47_0402_5%

1 2
1 2

R469
47_0402_5%

INTSPK_R1-3
INTSPK_L1-3

14

U25B

P

SPKR<28>

1 1

3

A

O4I

G

+3V POWER

SN74LVC14APWLE_TSSOP14

7

C580

1 2

1U_0603_10V4Z

1 2

R482
560_0402_5%

R483
10K_0402_5%

12

D17

CH751H-40_SC76

2 1

B

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITT EN CON SENT O F COMPAL ELECTRONICS, INC.

C

D

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

Audio_AMP&JACKs

HDL75 LA3041

E

44 60Thursday, July 28, 2005

of

0.1

A

B

C

D

E

+5VS

+3VS

12

R769
10K_0402_5%

CF4

1

1

1

H2
HOLEE

1

H13
HOLEE

1

H22
HOLEE

1

CF2

CF14

FD3

1

1

H3
HOLEE

1

H23
HOLEE

1

CF3

CF15

1

CF1

1

CF13

4 4

1

1

1

H1
HOLEE

CF25

FD1

1

H12
HOLEE

1

H21

3 3

HOLEE

1

1

1

FD2

H4
HOLEE

1

H24
HOLEE

1

CF16

1

1

1

FD4

H5
HOLEE

1

H11
HOLEE

1

H25
HOLEE

1

CF5

CF17

1

1

1

H6
HOLEE

1

H16
HOLEE

1

H26
HOLEE

1

CF6

CF18

FD5

1

1

1

H7
HOLEE

1

H17
HOLEE

1

H27
HOLEE

1

CF7

CF19

FD6

1

1

H8
HOLEE

1

H18
HOLEE

1

H28
HOLEE

1

CF8

CF20

1

1

H9
HOLEE

H19
HOLEE

H29
HOLEE

CF9

CF21

1

1

1

+3VALW +3VALW

14

R1140
20K_0402_5%

2 2

1 2

1

2

C1100

U25C

P

5

O6I

G

SN74LVC14APWLE_TSSOP14

7

1

H10
HOLEE

H20
HOLEE

H30
HOLEE

CF11

CF22

CF12

1

1

CF24

CF23

1

1

IDERST_HD#<28>

PLTRST#<9,26,28,34,38,40>

PLTRST#

1
2

+3VS +5VCD

12

R771
10K_0402_5%

1

+5VS

14

U54D

13

P

A

11

O

12

B

G

7

1

IDE_IRQ<27,30>

SWDJ@

2

G

+3VALW

12

R1198
10K_0402_5%

13

D

S

Q97
2N7002_SOT23

SWDJ@

1

HD_IDERST#

IDE_DIOR#<27> HDD_B_IOR# <30>

IDERST_CD#<28>

74VHC08MTC_TSSOP14

SWDJ@

HD_IDERST#

NOSWDJ@

1 2

R1208 0_0402_5%

Q98
2N7002_SOT23

D

S

HDD_IRQIDE_IRQ

1 3

G

2

SWDJ@

10

U55C

8

OE#

I9O

PLTRST#

8.2K_0402_5%

SN74LVC125APWLE_TSSOP14

14

U25D

P

9

O8I

G

SN74LVC14APWLE_TSSOP14

7

1 2

R1141 0_0402_5%

VS_ON1 <52>SUSP#<34,38,40,43,46>

12

R1142
100K_0402_5%

10

R1200

@

R42

33_0402_5%

SWDJ@

9

+3VS

+5VS

14

P

A
B

G

7

12

0.1U_0402_16V7K

2

G

+3VALW

+3VALW +3VALW

13

R28

SWDJ@

33_0402_5%

14

U25F

P

G

SN74LVC14APWLE_TSSOP14

7

R1210

8.2K_0402_5%

NOSWDJ@

O12I

R1139 0_0402_5%

1 2

12

R1196
100K_0402_5%

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITT EN CON SENT O F COMPAL ELECTRONICS, INC.

C

PLTRST#

R1195
100K_0402_5%

VS_ON1

VS_ON1<52> VS_ON2 <52>

1 2

C1129

1

2

0.022U_0402_16V7K

1 1

IDE_DIOR#<27> ODD_IOR# <30>

A

14

U25E

P

11

O10I

G

SN74LVC14APWLE_TSSOP14

7

C144

SWDJ@

0.1U_0402_16V4Z

+3VALW +3VS

1

5

U71

P

4

OE#

I2O

G

74LVC1G125GW_SOT3535

3

SWDJ@

NOSWDJ@

1 2

R1209 0_0402_5%

B

1

C905

0.1U_0402_16V4Z

2

14

U54A

P

A

3

O

B

G

74VHC08MTC_TSSOP14

7

PCMRST#<40>

U54C

SD_IDERST#

8

O

74VHC08MTC_TSSOP14

+5VS

HDD_IRQ <30>

+5VALW

SWDJ@

+5VALW

12

R783
10K_0402_5%

SWDJ@

13

D

Q72
2N7002_SOT23

S

SWDJ@

EC_IDERST<40,43>

EC_IDERST

+3VALW

C906 0.1U_0402_16V4Z

PCMRST#

14

1

P

OE#

I2O
G

7

SN74LVC125APWLE_TSSOP14

SWDJ@

R773

10K_0402_5%

80 mil 80 mil

1

C907
10U_0805_10V4Z

2

1 2

R774

1 2

R1158 0_0402_5%

1 2

R1159 0_0805_5%

NOSWDJ@

Q69

S

SWDJ@

240K_0402_5%

C910

1 2

1U_0603_10V4Z

SWDJ@

SUSP#<34,38,40,43,46>

1 2

NOSWDJ@

SWDJ@

D

13

SI2301BDS_SOT23

G

2

R775 10K_0402_5%

SWDJ@

DTC124EK_SC59

SUSP#SUSP#

SWDJ@

VCC= +3VALW

IDE_DCS1#<27,30>

G_PCI_RST#

SN74LVC125APWLE_TSSOP14

VCC= +3VALW

IDE_DCS3#<27,30>

D

+5VS

14

U54B

4

P

1 2
SWDJ@

U55A

SWDJ@

3

A

5

B

HD_IDERST#

6

O

G

74VHC08MTC_TSSOP14

7

12

R772

SWDJ@

10K_0402_5%

SIDE_RST#

HD_IDERST# <30,42>

SIDE_RST# <30>

+5VCD

1
SWDJ@

C908
10U_0805_10V4Z

2

1

SWDJ@

C909

0.1U_0402_16V4Z

2

12

Q70

2

CD_PLAY<40,43>

R1160 0_0402_5%

4

OE#

I5O

13

1 2

NOSWDJ@

U55B

6

DTC124EK_SC59

CD_PLAY

+5VCD

12

Q71

SWDJ@

R782
10K_0402_5%

SWDJ@

SW_IDE_SDCS1#

13

2

SW_IDE_SDCS1# <30>

SWDJ@

+5VCD

12

R785
10K_0402_5%

13

U55D

SWDJ@

11

OE#

I12O

SN74LVC125APWLE_TSSOP14

NOSWDJ@

1 2

R1161 0_0402_5%

Title

Size Document Number Rev

Date: Sheet

SWDJ@

SW_IDE_SDCS3#

SW_IDE_SDCS3# <30>

Compal Electronics, Inc.

SW DJ,RESET CKT,SW,LED BOAR

HDL75 LA3041

45 60Thursday, July 28, 2005

E

0.1

of

5

4

3

2

1

+5VALW to +5VS Transfer

+5VALW

C142

1

C740

2

2@

Q47

8

D

7

D

6

D

5

D

SI4800BDY_SO8

C748
10U_0805_10V4Z

8
7
6
5

1

C741

2

4.7U_0805_10V4Z

RUNON

1

S

2

S

3

S

4

G

+1.8V to +1.8VS Transfer

8
7
6
5

1

1

+

2

C1075

2

1 2

R126 0_0402_5%

10U_0805_10V4Z

Q45

D
D
D
D

SI4800BDY_SO8

+5VS

1

S

2

S

3

S

4

1

G

C738

C739

2

0.1U_0402_16V4Z

+3VALW to +3VS Transfer

0.1U_0402_16V4Z

C746
22U_A_4VM

+1.8VS+1.8V

1
2
3
4

1

2

0.1U_0402_16V4Z

C160
680P_0402_50V7K

1

C747

2

C1072

1

+

2

RUNON

Q82

S

D

S

D

S

D

G

D

SI4800BDY_SO8

1

2

1

2

22U_1206_10V4Z

12

R684
470_0402_5%

13

D

Q37

2N7002_SOT23

S

1

+

C1073
22U_A_4VM

2

12

R679
470_0402_5%

13

D

Q34

SUSP

2

G

2N7002_SOT23

S

SYSON#<39>

SYSON<38,40,51>

SUSP

2

G

SYSON

SUSP<51,53>

SUSP#<34,38,40,43,45>

SYSON#

SUSP

2

G

2

G

+5VALW

12

13

+5VALW

12

13

R681
10K_0402_5%

D

Q35
2N7002_SOT23

S

R683
10K_0402_5%

D

Q38

2N7002_SOT23

S

2N7002_SOT23

SUSP

2

SUSP

2

+12VALW

G

CE2

+12VALW

G

1 2

13

D

S

1

2

100U_C_4VM

12

13

D

S

R678
10K_0402_5%

1M_0402_5%

Q33

+

R685
10K_0402_5%

Q5
2N7002_SOT23

0.47U_0603_16V4Z

12

1

R680

2

1@

0.01U_0402_16V7Z

+3VALW +3VS

1

2

C1128

22U_A_4VM

Q79

+5V+5VALW

2N7002_SOT23

D

1 3

G

2

C744

1

C1058
10U_0805_10V4Z

2

0.1U_0402_16V4Z

Q46

8

D

7

D

6

D

5

D

SI4800BDY_SO8

1

2

0.1U_0402_16V4Z

D D

4.7U_0805_10V4Z

C C

B B

+5VALW to +5V Transfer

S

1

C1059

2

+3V+3VALW

+3VALW to +3V Transfer

1

S

2

C745

1

1

2

C742

4.7U_0805_10V4Z

2

3
4

S
S
G

0.1U_0402_16V4Z

1

C1057

2

13

D

Q95

2N7002_SOT23

S

0.1U_0402_16V4Z

1

C743

2

13

D

Q36

2N7002_SOT23

S

R1177 10K_0402_5%

1 2

SYSON#

2

G

R682

1 2

SYSON#

2

G

+12VALW

10K_0402_5%

+12VALW

Discharge circuit

SUSP

+0.9VS

12

R745
470_0402_5%

13

D

Q40

2

G

2N7002_SOT23

S

SUSP

+1.8VS

12

R741
470_0402_5%

13

D

Q41

2

G

2N7002_SOT23

S

SUSP

+1.5VS

12

R738
470_0402_5%

13

D

Q39

2

G

2N7002_SOT23

S

+3V +5V

A A

12

13

D

Q43

2N7002_SOT23

S

R602
470_0402_5%

SYSON#

2

G

5

12

13

D

Q80

2N7002_SOT23

S

R1064
470_0402_5%

SYSON#

2

G

2N7002_SOT23

+2.5VS

12

R125
470_0402_5%

13

D

Q3

SUSP

2

G

S

4

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

DC/DC Circuits

HDL75 LA3041

1

0.1

of

46 60Thursday, July 28, 2005

A

B

C

D

Vin Detector
Min. typ. Max.

H-->L 16.976V 17.257V 17.728V

1 1

12

PC4

560P_0402_50V7K

VIN

12

PR5
10_1206_5%

12

PZD1
RLZ24B_LL34

BATT_TEMP <40>

+3VALWP

EC_SMD_1 <25,40 ,41>

EC_SMC_1 <25,40,41>

PJPD1

P1

1

1

3

G

4

G

SINGA_2DC-G213-B04

2 2

2

2

DCIN-

P1

12

PC1

560P_0402_50V7K

BATT++BATT+

PL2

BATT+

12

PJPB1 battery connector

3 3

SMART
Battery:

1.BAT+

2.ID

3.B/I

4.TS

5.SMD

6.SMC

7.GND

HCB4532K-800T90_1812

1 2

PC7

0.01U_0402_25V7Z

PC8

1000P_0402_50V7K

SUYIN_200275MR007G161ZL

12

PJP1

1
2
3
4
5
6
7

BATT++

FBM-L18-453215-900LMA90T_1812

1 2

12

PR174

@

100K_0402_5%

1 2

PR176

@

1K_0402_5%

1 2

PR18

1K_0402_5%

3

OC8070-A301~D@

12

PR175
1K_0402_5%

@

12

PC2

12P_0402_50V8J

PL1

PL20

PJP12 3MM

1 2

100_0402_5%

1 2

100_0402_5%

14
2

PC3

21

+3VALWP

6C/8C# <48>

1 2

PR15

1K_0402_5%

PR21

25.5K_0402_1%

1 2

PR22

PR25

12

12P_0402_50V8J

BATT_TEMP

L-->H 17.430V 17.901V 18.384V

VIN

12

PR2

84.5K_0402_1%
PR6

22K_0402_5%

1 2

12

PC5

1000P_0402_50V7K

12

PR7

PC6

20K_0402_1%

12

VS

PU1A

LM393M_SO8

8

3

P

+

1

O

2

-

G

4

PR16

100K_0402_1%

MAINPWON<8,49,50>

ACON<48>

PD2

2
3

RB715F_SOT323

1

ACIN

Precharge detector

Min. typ. Max.
H-->L 14.589V 14.84V 15.243V
L-->H 15.562V 15.97V 16.388V

0.1U_0603_25V7K

VL

12

12

PC11

0.1U_0603_25V7K

VL

10K_0402_5%

12

PC9

0.01U_0402_25V7Z

PR1

1 2

1M_0402_1%

5

+

6

-

PR9

7

O

VS

8

P

O

G

PU4B
LM393M_SO8

4

12

RTCVREF

PR14

2.2M_0402_5%

VS

LM393M_SO8

8

P

+

-

G

4

PR23

34K_0402_1%

7

12

PU1B

5
6

12

12

PC12

1000P_0402_50V7K

12

VIN

12

PR3

10K_0402_5%

12

PZD2

RLZ4.3B_LL34

VIN

12

PRG++

13

D

S

PR26

66.5K_0402_1%

PR4

10K_0402_5%

1 2

12

PR8
10K_0402_5%

PD1

1N4148_SOD80

VIN+

12

PR19
191K_0402_1%

RHU002N06_SOT323

PQ1

2

G

13

ACIN

PACIN

1.5K_1206_5%

1.5K_1206_5%

1.5K_1206_5%

B+

12

PR17
499K_0402_1%

12

PR20
499K_0402_1%

PR24
47K_0402_5%

12

PQ2
DTC115EUA_SC70

2

ACIN <28,40,50>

PACIN <48>

PR10

1 2

PR11

1.5K_1206_5%

1 2

PR12

1 2

PR13

1 2

12

PC10
1000P_0402_50V7K

PACIN <4 8>

+5VALWP

B+

BATT ONLY

Precharge detector

4 4

Min. typ. Max.
H-->L 6.138V 6.214V 6.359V
L-->H 7.196V 7.349V 7.505V

THIS SHEET OF EN GINE ERI NG DR AWING IS THE PROPRIETARY PROPERTY
OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE
SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE
CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS
AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR
THE INFORMATION I T CONTA INS MAY BE USED BY OR DISCLOSED TO ANY
THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,

A

B

INC.

C

Compal Electronics, Inc.

Title

DCIN & DETECTOR & Precharge

Size Document Number Rev

B

EDL75/76 LA-3041

Date: Sheet of

D

47 60Thursday, July 28, 2005

0.2

A

B

C

D

E

Charger

Iadp=0~2.9A(65W)

PQ3

AO4407_SO8

PQ6

47K

47K

2

13

PQ8

DTC115EUA_SC70

PD6

8
7

5

1 3

PR33

150K_0402_5%

2

G

VIN

1 1

12

DTA144EUA_SC70

PR28

47K_0402_5%

2

13

D

2

G

S

PQ10

RHU002N06_SOT323

2 2

1 2

PR45

22K_0402_5%

1 2

ACON

1SS355_SOD323

ACOFF#

PACIN<47>

ACON<47>

P2 P3

1
2
36

4

12

12

PC18

0.1U_0603_25V7K

12

24.9K_0402_1%

RHU002N06_SOT323

PQ11

13

D

IREF<40>

S

PQ4

AO4407_SO8

1
2
3 6

4

PR30

200K_0402_1%

75K_0402_1%

PR35

1 2

1 2

PR40

180K_0402_1%

PR34

PR43

120K_0402_1%

8
7

5

PC26

0.1U_0603_25V7K

PR27

0.02_2512_1%

1 2

PC21

0.01U_0402_25V7Z

12

12

12

12

PC31

0.01U_0402_25V7Z

1 2

100K_0402_1%

1 2

4700P_0402_50V7K

1 2

PC24

2200P_0402_50V7K

10K_0402_5%

PR32

1 2

PC22

1K_0402_5%

1 2

1 2

PR41

PR36

10K_0402_5%

PR37

PU2

1

-INC2

2

OUTC2

3

+INE2

4

-INE2

5

FB2

6

VREF

7

FB1

8

-INE1

9

+INE1

10

OUTC1

11

OUTD

12

-INC1

MB3887_SSOP24

B+

+INC2

GND

CS

VCC(o)

OUT

VH

VCC

RT

-INE3

FB3

CTL

+INC1

1 2

PL3

HCB4532K-800T90_1812

24

23

22

21

20

19

1 2

PC23

0.1U_0603_25V7K

18

17

1 2

PR38

66.5K_0402_1%

16

PR42

47K_0402_5%

15

1 2

14

13

1500P_0402_50V7K

PC27

10U_1206_25V6K

PC13

10U_1206_25V6K

PC19

2200P_0402_50V7K

1 2

1 2

PC20

0.1U_0603_25V7K

PC25

0.1U_0603_25V7K

1 2

1 2

PC14

12

12

PR44
10K_0402_5%

1 2

CHG_B+

36

241

578

FSTCHG <40>

PC16

0.1U_0603_25V7K

12

12

PC17
2200P_0402_50V7K

PQ7
AO4407_SO8

LXCHRG

PL4

16UH_D104C-919AS-160M_3.7A_20%

1 2

12

PD5

EC31QS04

AO4407_SO8

PQ5

1
2
3 6

PR31

10K_0402_5%

ACOFF#

PR39

0.02_2512_1%

1 2

4

47K_0402_5%

1 2

1 2
13

10K

10K

PQ9

DTC114EKA_SC59

PR29

2

8
7

5

12

12

1 2

PC28

4.7U_1206_25V6K

VIN

PZD3

@

RLZ22B_LL34

PD3

@

1SS355_SOD323

1 2

PD4

1SS355_SOD323

12

PC29

4.7U_1206_25V6K

ACOFF<40>

BATT+

BATT+

12

PR46

49.9K_0603_0.1%

D

3 3

IREF=1*Icharge

RHU002N06_SOT323 @

PQ36

S

13

1 2

G

2

PR177

150K_0603_0.1%@

IREF=0~3.3V

PR178

1 2

1 2

PR179

100K_0402_5%@

100K_0402_5%@

VS

2P4S:4300mAH/cell

0.7C=3.0A

Charge voltage

13

PC152

0.1U_0402_16V8K@

1 2

2

PQ37

DTC115EKA_SC59@

6C/8C# <47>

For 4S battery only.PR46=49.9K
4S CC-CV MODE : 16.83V
For 3S/4S battery.PR46=75K,

4 4

PR177=150K,PQ36=2N7002,PR178=100K
PC152=0.1U,PQ37=DTC115EKA

OVP voltage :
LI-4S :18V----BATT-OVP=2V
BATT-OVP=0.111*BATT+

12

PR47

150K_0603_0.1%

BATT_OVP<40>

PU3A

LM358A_SO8

1

BATT+

VS

12

8

3

P

+

0

2

-

G

4

12

PR48
845K_0603_1%

12

PC32

PR49
300K_0603_0.1%

0.01U_0402_25V7Z

12

PR50
143K_0402_1%

12

PC33

0.01U_0402_25V7Z

PR174=100,PR176=1K.
4S CC-CV MODE : 16.8V
4S CC-CV MODE : 12.6V

A

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND

PROPRIETARY NOTE

B

TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

D

Compal Electronics, Inc.

Title

Charger

Size Document Number Rev

B

EDL75/76 LA-3041

Date: Sheet

E

of

48 60Thursday, July 28, 2005

0.2

A

1 1

B

C

D

VIN

PD9
1N4148_SOD80

1 2

PC42

12

13

1 2

PR67

560_0402_5%

PR63

68_1206_5%

PD10

BATT+

2 2

PR64

200_0805_5%

12

51ON#<42>

3 3

CHGRTCP

12

RB751V_SOD323

PR65

100K_0402_5%

1 2

PR66

22K_0402_5%

2

12

PC41
1U_0805_25V4Z

1 2

PU5

G920AT24U_SOT89

IN

OUT

GND

1

TP0610K_SOT23

12

PC40

0.22U_1206_25V7K

RTCVREF

3

PQ13

2

12

4.7U_0805_6.3V6K

12

VS

12

1 2

PR68
560_0402_5%

PR210
68_1206_5%

PC39

0.1U_0603_25V7K

CHGRTC

PH2 under CPU botten side :

CPU thermal protection at 80 degree C
Recovery at 44(45) degree C

PR54

47K_0402_1%

PR59

150K_0402_1%

12

PR62
150K_0402_1%

1 2

PC34

12

VS

12

0.1U_0603_25V7K

8

PU4A

3

P

+

O

2

-

G

LM393M_SO8

4

VL

PR57

1.82K_0603_1%

12

PH2

PC36

1000P_0402_50V7K

10KB_0603_1%_TH11-3H103FT

VL

12

12

PR55

20.5K_0402_1%

1 2

TM_REF1

12

PC35

1U_0805_16V7K

VL

PR52
150K_0402_1%

1 2

1

MAINPWON <8,47,50>

4 4

THIS SHEET OF EN GINE ERI NG DR AWING IS THE PROPRIETARY PROPERTY
OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE
SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE
CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS
AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR
THE INFORMATION I T CONTA INS MAY BE USED BY OR DISCLOSED TO ANY
THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,

A

B

INC.

C

Compal Electronics, Inc.

Title

RTC Battery & OTP

Size Document Number Rev

B

EDL75/76 LA-3041

Date: Sheet of

D

49 60Thursday, July 28, 2005

0.2

A

B

C

D

E

+3.3V/+5V/+12V

B+

+3VALWP Choke DCR = 26.5m[.

Current limit Threshold Min.=80 mV Mx.=120mV.
OCP Min.= 80mV/1.27K*(1.27K+1.27K)/26.6=6.038A
OCP Max.=120mV/1.27K*(1.27K+1.27K)/26.5=9.056A

1 1

2 2

10UH_D104C-919AS-100M_4.5A_20%

+3VALWP

PC59

1

3 3

+

2

150U_D2_6.3VM

PL5

FBM-L18-453215-900LMA90T_1812

1 2

12

PC47

2 1

2 1

PD15

SKS10-04AT_TSMA

@

PD16

2200P_0402_50V7K@

PL7

SKUL30-02AT_SMA

B++

12

PR83

3.57K_0402_1%

PC45

0.1U_0603_25V7K

1 2

VS

2

3

PD13

21

VL

1

12

ACIN

12OUT

VDD

BST5

DH5

PGND

CSH5

CSL5

SEQ
REF

SYNC

RST#

RHU002N06_SOT323@

LX5
DL5

FB5

DAP202U_SOT323

PC49

4.7U_0805_10V4Z

PQ16

4
5
18
16
17
19
20
14
13
12
15
9
6
11

PR84

0_0402_5%

PQ14

1

D2

2

D2

3

G1

12

PC55
47P_0402_50V8J

1 2

4

S1/A

AO4912_SO8

1 2

PR74

1.27K_0402_1%
PR75

1.27K_0402_1%

ACIN<28,40,47>

PC48

4.7U_1206_25V6K

12

PR76

1M_0402_1%

12

PC58

1 2

100P_0402_50V8J

PR86

1 2

10K_0402_1%

G2
D1/S2/K
D1/S2/K
D1/S2/K

12

0.47U_0603_16V7K

619_0402_1%

1 2

10K_0402_5%

300K_0402_5%

8
7
6
5

LX3

PC56

12

PR79

1 2

PR80

PR82

@

VS

12

PR87
0_0402_5%

12

12

PC65
1U_0805_25V4Z@

DL3

12

DH3

12

PC60

1000P_0402_50V7K

PD14

1SS355_SOD323

PR71
0_0603_5%

12

PC52

0.1U_0603_25V7K

PU6

25

BST3

27

DH3

26

LX3

24

DL3

1

CSH3

2

CSL3

3

FB3

10

SKIP#

23

SHDN#

7

TIME/ON5

28

RUN/ON3

MAX1902EAI_SSOP28

12

PC64

0.47U_0603_16V7K

1 2
12

PR190

10_1206_5%

22

VL

V+

GND

8

MAINPWON <8,47,4 9>

2

G

BST51BST31

+12VALWP

12

13

D

S

1 2

PR72

2.7K_1206_5%@

12

PC61

4.7U_0805_10V4Z

PC46

0.1U_0603_25V7K

1 2

PQ15

8

G2

D2

7

D2

D1/S2/K

6

G1

D1/S2/K

5

D1/S2/K

S1/A

AO4912_SO8

12

PC54

4.7U_1206_25V6K

BST5

2.5VREF

PR73
0_0603_5%

1 2

DH5

LX5

DL5

PC57

0.47U_0603_16V7K

12

12

PR81
698_0402_1%

12

PR85

10.2K_0402_1%

12

PR88
10K_0402_1%

PC44
470P_0805_100V7K

@

1 2

SNB

PR70
22_1206_5%@

12

FLYBACK

B++

1
2
3
4

PR78

1.54K_0402_1%

12

PC63

100P_0402_50V8J

12

PC50

12

12

PC51

2200P_0402_50V7K @

SKS10-04AT_TSMA

4.7U_1206_25V6K

PD17

+5VALWP Choke DCR = 40mΩ.
Current limit Threshold Min.=80 mV Mx.=120mV.

OCP Min.= 80mV/0.698K*(1.54K+0.698K)/40=6.412A

4 4

OCP Max.=120mV/0.698K*(0.698K+1.54K)/40=9.593A
RS2(PR64)=RS1(PR58)*RS3(PR61)/(RS1+RS3)
L/RL(DCR)=RS1*RS3(PR61)/(RS1+RS3)*Cs(PC56)

Title

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

D

3.3V / 5V / 12V

Size Document Number Rev

B

EDL75/76 LA-3041

Date: Sheet

PC43
10U_1210_25V6K

1 2

12

PD12
EC11FS2_SOD106

PL6

9U_SDT-1204P-9R0-120_4.5A_20%

1 4

3 2

12

PC53
47P_0402_50V8J

12

PR77
2M_0402_1%

1

+

2

2 1

150U_D2_6.3VM

Compal Electronics, Inc.

E

PC62

+5VALWP

50 60Thursday, July 28, 2005

0.2

of

5

4

3

2

1

13

D

S

+1.2VSP

1

+

PC69
150U_D2_6.3VM@

2

PR94

200K_0402_1%2@

1 2

PR191

0_0402_5%2@

2

1 2

G

12

PC195

@

0.1U_0402_16V7K

Compal Electronics, Inc.

Title

Size Document Number Rev

B

Date: Sheet

12

0.9VSP/1.8VP/1.2VSP

EDL75/76 LA-3041

PC70

22U_1206_10V6M2@

SUSP <46, 53>

+1.2VSP

2.5VREF

1

0.2

of

51 60Thursday, July 28, 2005

+1.8VP

PU7

PC84

11

15

14

10

13

12

9

6

5

12

10_0603_5%

1 2

VIN1VCNTL

2

GND

3

VREF

4

VOUT

APL5331KAC-TR_SO8

+0.9VSP

12

PC74

4.7U_0805_6.3V6K

+5VALW

PR99

1U_0805_25V4Z

PR102

0_0603_5%

PR106

2.74K_0603_1%

4

D D

SUSP<46,53>

C C

PL8

FBM-L11-322513-151LMAT_1210

B+

1 2

B B

SYSON<38,40,46>

A A

1 2

PR93

0_0402_5%

1 2

0_0402_5%

5

PR105

12

12

PC77

@

PC67
10U_1206_6.3V7K

13

D

2

G

S

12

PC78

0.1U_0603_25V7K
2200P_0402_50V7K

@

93.1K_0603_1%

1 2

PR90

1K_0402_1%

PQ18

RHU002N06_SOT323

12

12

PC79

4.7U_1206_25V6K

PR101

12

PR103

16

0_0402_5%

12

PC90

0.01U_0402_16V7K

12

PR89

1K_0402_1%

12

PC73

150U_D2_6.3VM

@

PC80

4.7U_1206_25V6K

PU8

4

ILIM

FPWM

3

EN

7

SS

2

PGOOD

12

PC68

0.1U_0603_25V7K

1

+

2

12

PR98

10_1206_5%

12

PC83

0.1U_0603_25V7K

1

VIN

VCC

BOOT

HDRV

LDRV

SW

ISNS

PGND

VSEN

VOUT

AGND

FAN5234QSCX_QSOP16

8

NC
NC
NC
TP

1 2

PC81

@

PD18

RB751V_SOD323

12

12

6
5
7
8
9

1U_0805_25V4Z

12

1 2

PC85

0.1U_0603_25V7K

+3VALW

12

PC66
1U_0603_16V6K

PQ21

1

D2

2

D2

3

G1

4

S1/A

AO4912_SO8

D1/S2/K
D1/S2/K
D1/S2/K

+1.5VSP

PC71

4.7U_1206_25V6K2@

8

G2

7
6
5

1.8UH_D104C-919AS-1R8N_9.5A_20%
PL11

1 2

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

6
2

1

12

12

PC88

PQ17

D

SI3456DV-T1_TSOP62@

S

45

G

3

VS

PU3B

+

7

0

-

LM358A_SO8

1 2

1 2

PC76

68P_0402_50V8K2@

PR96

PR91

5.1K_0402_5%2@

5
6

5.1K_0402_5%2@

1 2

PR92

1 2
12

PC72

12

PC75

4700P_0402_25V7K

2@

RHU002N06_SOT323

0_0402_5%2@

220P_0603_50V8J2@

PR95

187K_0402_1%2@

1 2

PQ19

2@

+1.8VP

1

12

PR104

1K_0603_1%

0.1U_0603_25V7K

12

PR108

1K_0402_1%

1

+

+

PC89

@

1 2

2

4.7U_0805_6.3V6K

PC87

PC86

2

220U_D2_4VM

330U_V_2.5VM

@

2

A

1 1

12

12

S1/A

PC93

1

D2

2

D2

3

G1

4

VS_ON1<45>

PC92

2200P_0402_50V7K

@

PQ23

8

G2

7

D1/S2/K

6

D1/S2/K

5

D1/S2/K

AO4912_SO8

+1.5VSP

2 2

1

12

+

PD20

EP10QY03

@

3 3

PC103

2

2 1

@

150U_D2_6.3VMV

4.7UH_D104C-919AS-4R7N_5.2A_20%

PC105

PR168

5.1K_0402_1%

4.7U_0805_6.3V6K

1 2

12

PR107
10K_0402_1%

PL9

1 2

Assume that PR107=10K ohm, then 1.5V=1*(1+PR168/PR107), so PR168=5K ohm.

4.7U_1206_25V6K

PD19

DAP202U_SOT323

0.1U_0603_25V7K
PC101

B

B++++

+5VALW

12

PC94

21
19

18
17
20
16

15
14
12

7
5

13
3

PR119

12

12

4.7U_0805_6.3V6K

PR113

0_0603_5%

1 2

BST2.5A

DH2.5

12

PR120

100K_0402_1%

3

12

1

2

PR111

0_0603_5%

1 2

PR116

0_0402_5%

1 2

0.1U_0603_25V7K
PC99

12

25

BST1

26

DH1

27

LX1

24

DL1

28

CS1

1

OUT1

2

FB1

MAX8743EEI_QSOP28

11

ON1

PR198

@

0_0402_5%

0.22U_0603_16V7K

1 2

4

OVP

8

23

1U_0805_50V4Z

PC100

MAX1845_VCC

12

22

V+

VCC

PU9

SKIP

GND

6

PC109

1 2

PR112

20_0603_5%

9

VDD

UVP

BST2

DH2

LX2
DL2

CS2

OUT2

FB2

ON2

PGOOD

TON

ILIM2
ILIM1

REF

PR118

10

49.9K_0402_1%

12

62K_0603_1%

BST2.5B

12

PR121

100K_0402_1%

C

PC102

0.1U_0603_25V7K

12

DL2.5

12

PR115
0_0402_5%

PQ24

8
7
6
5

AO4912_SO8

LX2.5

G2
D1/S2/K
D1/S2/K
D1/S2/K

VS_ON2 <45>

1

D2

2

D2

3

G1

4

S1/A

1.8UH_D104C-919AS-1R8N_9.5A_20%

FBM-L18-453215-900LMA90T_1812

PL10

1 2

12

12

PC96

2200P_0402_50V7K

@

PL12

1 2

PR114

499_0402_1%

PR117

10K_0402_1%

D

B+

12

PC98

PC97

4.7U_1206_25V6K

4.7U_1206_25V6K

+VCCPP

1

12

PC108

@

4.7U_0805_6.3V6K

1 2

1 2

1

+

+

PC106

PC107

2

150U_D2_6.3VMV

2 1

2

PD21

@

SKUL30-02AT_SMA

150U_D2_6.3VMV

@

MAX1845_VCC

PR196
33K_0402_1%

1 2

PR197
11K_0402_1%

1 2

4 4

2N7002_SOT23

A

B

PQ41

13

D

2

G

S

VS_ON2 <45>

THIS SHEET OF EN GINEE RING D RAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

Compal Electronics, Inc.

Title

+VCCPP & +1.5VSP

Size Document Number Rev

B

EDL75/76 LA-3041

Date: Sheet

D

of

52 60Thursday, July 28, 2005

0.2

A

B

C

D

+3VALW+3VALW

PU13

1 2

12

VIN1PVIN

2

GND

3

SD
VREF4VFB

12

PC151

0.01U_0603_16V7K

21

+5VALW

21

21

21

21

PC146

0.1U_0603_25V7K

1 1

2 2

SUSP<46,51>

1 2

@

560P_0603_50V7K

2.5VREF

PR171
0_0402_5%

PC150

100K_0402_5%

255K_0402_1%@

12

1 2

PR172

PR173
100K_0402_1%

12

PR182

PJP11
3MM

+5VALWP

3 3

PJP3
3MM

+3VALWP +3VALW

PJP5
3MM

+1.8VP +1.8V +2.5VSP

PJP7
3MM

+VCCPP +VCCP

PJP9
3MM

+1.2VSP +1.2VS

4 4

LX

PGND

CM3718_PSOP8

D

S

8
7
6
5

13

G

+VGA_CORE_P +VGA_CORE

5U_TPRH6D38-5R0M-N_2.9A_20%

12

PC148

4.7U_0805_6.3V6K

2

PQ35

RHU002N06_SOT323

+12VALWP

+1.5VSP

+0.9VSP

PL18

12

PJP2

PJP4

PJP6

PJP8

PJP10

2MM

3MM

3MM

3MM

3MM

PR169

PR170

1 2

100K_0402_5%

PC149

SUSP <46 ,51>

21

+12VALW

21

+1.5VS

21

+2.5VS

21

21

1K_0402_5%

1 2

1 2

220P_0603_50V8J

+0.9VS

+2.5VSP

1

+

2

PC147
220U_D2_4VM

+5VALW

12

PC153

12

PC160

PR185

2@

34K_0402_1%

POWER_SEL<17>

4.7U_0805_6.3V6K2@

+VGA_CORE_P

+VGA_CORE

12

PR184

10K_0402_1%2@

0.1U_0402_16V7K2@

PQ40

0.1U_0402_16V4Z2@

D

S

PR199

0_0402_5%2@

1 2

PC165

12

13

G

PR186

43.2K_0402_1%2@

2

12

PR187

1 2

0_0402_5%2@

12

PC161

@

0.01U_0402_25V7Z

+3VS

12

13

D

2

G

S

12

RHU002N06_SOT3232@

12

100K_0402_5%2@

PC159

PR200

PQ45

2N7002_SOT232@

1

+

PC158

2

4.7U_0805_6.3V6K2@
220U_D2_4VM_R152@

POWER_SEL#

POWER_SEL#

PC155

470P_0402_50V7K2@

12

12

PR181

16.2K_0402_1%

12

PC154

1U_0402_6.3V6K2@

PU14

7

OCSET

PR183
0_0402_5%2@

SUSP<46,51>

12

PC157

@

PQ39

13

D

2

G

S

12

0.1U_0402_16V7K

6

FB

3

RHU002N06_SOT3232@

GND

APW7057KC-TR_SOP82@

12

PR180

2.2_0402_5%2@

PD26

1SS355_SOD3232@

5

VCC

1

BOOT

2

UGATE

8

PHASE

4

LGATE

1 2

12

0.1U_0402_16V7K2@

PC156

POWER_SEL

H

8

G2

7

D1/S2/K

6

D1/S2/K

5

D1/S2/K

2@

1.8UH_D104C-919AS-1R8N_9.5A_20%2@

1 2

VGA_CORE

PQ38

D2
D2
G1

S1/A

AO4918_SO8

PL19

1.0V

1
2
3
4

VGA_CORE for ATI-M24

L

1.2V

Compal Electronics, Inc.

Title

THIS SHEET OF EN GINEE RING D RAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

+2.5VSP/VGA_CORE_P

Size Document Number Rev

B

EDL75/76 LA-3041

Date: Sheet

D

of

53 60Thursday, July 28, 2005

0.4

5

4

3

2

1

+5VS

+3VS

12

1 2

12

PC139

RHU002N06_SOT323

PR164

10K_0402_1%

1 2
13

D

RHU002N06_SOT323

S

PR132 10_0402_5%

PC129

1U_0603_16V6K

1 2

27P_0402_50V8J

VCC

VCC

10
24
23
22
21
20
19
25

12

18
11

PU12

VCC
D0
D1
D2
D3
D4
D5
VROK

4

S0

5

S1

6

SHDN#

1

TIME
CCV

2

TON

8

REF

9

ILIM

7

OFS

3

SUS
SKIP
GND

MAX1532AETL_TQFN40

PC128

2.2U_0603_6.3V6K

VDD

V+

BSTM

DHM

LXM

DLM

PGND

CMP

CMN

OAIN+

OAIN-

FB

CCI

BSTS

DHS

LXS

DLS
CSP
CSN

GNDS

2

1

30
36
26

PR203 2.2_0603_5%

28
27
29
31
37
38
17
16
15
14

PC135 470P_0603_50V8J

35

PR204 2.2_0603_5%

33
34
32
40
39
13

D D

PR133

10K_0402_1%

1 2

PR134 0_0402_5%

CPU_VID0<6>
CPU_VID1<6>
CPU_VID2<6>
CPU_VID3<6>
CPU_VID4<6>
CPU_VID5<6>

VGATE<9,16,28>

PR149

C C

VR_ON

0>

0_0402_5%

1 2

PR150

100K_0402_5% @

1 2

1 2

13

D

PR158

S

PR160

0_0402_5%

1 2

PR153

200K_0402_1%

1 2

10.7K_0402_1%

+5VS

PR165

100K_0402_1%

PR155

78.7K_0603_1%

1 2

FB

PR156 100K_0402_1%

PM_STP_CPU#

>

RHU002N06_SOT323

B B

PM_DPRSLPVR<28>

1 2

PQ29

2

G

PSI#<6>

A A

12

PR135 0_0402_5%

12

PR137 0_0402_5%

12

PR139 0_0402_5%

12

PR141 0_0402_5%

12

PR142 0_0402_5%

12

PR144 0_0402_5%

1 2

PR151 30.1K_0402_1%

PC134
270P_0402_50V7K

PC136 0.22U_0603_16V7K

12

PC138

2

100P_0402_50V8J

G

20K_0402_1%

1 2

1

C

2

B

E

PQ34

3

HMBT2222A_SOT23

1 2

1 2

13

D

S

1 2

PR162

PQ33

2

G

PQ30

PD22

EP10QY03

2 1

12

PC130

PR136 2.2_0603_5%

1 2

1 2

FB

1 2

1 2

12

12

12

PC124

PC122

4.7U_1206_25V6K

PC123

4.7U_1206_25V6K

0.01U_0402_25V7Z

5

12

PC131

0.01U_0402_25V7Z

0.22U_0603_16V7K

PQ27

AO4408_SO8

D8D7D6D

S1S3G

S

4

2

0.56UH_MPC1040LR56 23_21A_20%

1 2

5

PQ28

AO4410_SO8

4

PR152 909_0402_1%

1 2

12

D8D7D6D

S1S3G

S

2

PR201

4.7_1206_5%

@

1 2

PD23

EC31QS04

@

PC200

1 2

@

680P_0603_50V8J

PR143

@

1 2

100K_0402_1%

12

PR145 909_0402_1%

0.47U_0603_16V7K

+5VS

21

PD24

EP10QY03

PR159

1 2

2.2_0603_5%

12

PC144

0.22U_0603_16V7K

AO4408_SO8

AO4410_SO8

PQ31

PQ32

5

D8D7D6D

PC140

S1S3G

S

4

2

5

D8D7D6D

S1S3G

S

4

2

PR167 909_0402_1%

1 2

12

12

2200P_0402_50V7K

12

PD25

EC31QS04

@

PC141

1 2

1 2

4.7U_1206_25V6K

PR202

4.7_1206_5%

@

PC201

@

CPU_B+

12

PC142

4.7U_1206_25V6K

680P_0603_50V8J

12

PC143

PR166 909_0402_1%

12

PL16

FBM-L18-453215-900LMA90T_1812

PC125

2200P_0402_50V7K

PL15

1 2

1 2

0.001_2512_5%

12

PC132

1 2

PR146 499_0402_1%

1 2

1 2

PC137

0.022U_0402_16V7K

0.01U_0402_25V7Z

0.56UH_MPC1040LR56 23_21A_20%

PR154

3K_0603_1%

1 2

0_0402_5%

PR161

12

100K_0402_1%@

PL17

1 2

12

1 2

PC145

0.47U_0603_16V7K

PR140

PR157

1

+

PC126

100U_25V_M

2

12

PR147 499_0402_1%

1

+

PC127

100U_25V_M

2

+CPU_CORE

CPU VCC SENSE

1 2

PR148

3K_0603_1%

1 2

PC133

1000P_0402_50V7K

@

CPU_B+ B+

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SE CRET INFO RMATI ON. THIS SHEET MAY NO T BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

Compal Electronics, Inc.

Title

+CPU_CORE

Size Document Number Rev

B

EDL75/76 LA-3041

Date: Sheet

1

of

54 60Thursday, July 28, 2005

0.2

A

B

C

D

E

Version change list (P.I.R. List) Page 3 of 1

Reason for change Rev. PG# Modify List B.Ver# PhaseFixed IssueItem

1 1

Change DDRII to DDRI.

1

Ripple voltage of +1.2VSP is large The output voltage is unstable, so increase capacitance

2

Change DDRII to DDRI.

to improve it.

0.2

1.Change PR104 from 1K_0603_1% to 1.8K_0603_1%

2.Change PR106 from 2K_0402_5% to 2.74K_0603_1%

3.Change PR101 from 107K_0402_1% to 93.1K_0603_1%.

1.Change PC70 from 4.7U_1206_25V6K to 22U_1206_10V6M

54

0.2

DVT0.20.2 54

DVT

Ripple voltage of +VCCPP is large

3

+1.5VP is poor supply by using CM3718.

4

Ripple voltage is over spec.

Use MAX1845 to convert +1.5VP

0.2

0.2

55

Change PC106 from 150U_D2_6.3VM(45m) to 150U_D2_6.3VMV(15m)

1.Delete PU11 CM3718.

56

2.Delete PQ26 RHU002N06.

0.2

DVT

3.Delete PL14 5U_TPRH6D38-5R0M

4.Delete PC113 150U_D_6.3V

5.Delete PC115 4.7U_1206_25V6K.

6.Delete PC111,PC117PC121,PR123,PR125,PR127,

2 2

PR129,PR130,PR131.

1.Delete the PQ22 RHU002N06.

2.Delete PR109 100K_0402_1%

+1.5VP is poor supply by using CM3718. Use MAX1845 to convert +1.5VP

5

0.2 55

3.Delete the PC91 0.01U_0402_25V7Z

4.Change PR168 from 2K_0402_1% to 5.1K_0402_1%.

0.2
DVT

5.Change PC103 from 150U_D2_6.3VM(45m) to 150U_D2_6.3VMV(15m)

6.Change PL9 from 1.8UH_D104C-919AS-1R8N to

4.7UH_D104C-919AS-4R7N

Change +2.5VSP to +1.8VP

6

For UMA platform can no populate +1.2VSP.

7

For UMA platform can no populate +1.8VSP. For UMA platform can no populate +1.8VSP.

8

3 3

For charge current accuracy requirement

9

For charge voltage accuracy requirement For charge voltage accuracy requirement 50 Change PR46 from 49.9K_0402_1% to 49.9K_0603_0.1% 0.2 DVT

10

Use lower rating capacitors to improve

11

cost down.

Change +2.5VSP to +1.8VP

For UMA platform can no populate +1.2VSP.

0.2

0.2 55

For charge current accuracy requirement 0.2 50 Change PR43 from 120K_0402_5% to 120K_0402_1%. 0.2 DVT

0.2

Use lower rating capacitors to improve
cost down.

0.2 50 1.Change PC42 from 4.7U_1206_25V6K to 4.7U_0805_6.3V6K.

1.Change PR173 from 10K_0402_1% to 100K_0402_1%.

560.2

2..Add PR182 255K_0402_1%.

No populate PC71,PQ17,PR91,PR92,PC72,PR96,PC76,PC70,PR94,

54

PR95,PC75,PQ19,PR97,PQ20,PR100 and PC82.

No populate PU13,PC146,PR171,PR172,PR173,PR182,PC151,PQ35,
PL18,PC148,PR170,PR169,PC149 and PC147.

2.Change PC74 from 4.7U_1206_25V6K to 4.7U_0805_6.3V6K.

0.2

0.2 DVT

0.2 DVT

DVT0.2

DVT

3.Change PC94 from 4.7U_1206_25V6K to 4.7U_0805_6.3V6K.

4.Change PC148 from 4.7U_1206_25V6K to 4.7U_1206_6.3V6K

without populate.

For pull high to VGATE. For pull high to VGATE. 0.2 50 0.2 DVTPopulate PR133 with 10K_0402_1%.

12

To avoid inrush current. To avoid inrush current. 0.2 50 Add PR190 between PD14 pin2 and VS with 10_1206_5%. 0.2 DVT

13

To solve the no load PWM waveform issue. To solve the no load PWM waveform issue. 0.2 53 Change PC86 from 220U_D2_4VM to 220U_D2_4V_15m. 0.2 DVT

14

4 4

To solve the shutdown negtive voltage To solve the shutdown negtive voltage issue. 0.2 54 Add PQ41(2N7002_SOT23) and PR196(33K_0402_1%) and

15

issue.

PR197(11K_0402_1%)

0.2 DVT

Compal Electronics, Inc.

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SE CRET INFO RMATI ON. THIS SHEET MAY NO T BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

D

PIR

Size Document Number Rev

EDL71 LA-2351

Date: Sheet

E

of

55 60Thursday, July 28, 2005

0.0

A

B

C

D

E

Version change list (P.I.R. List)

Page 3 of 2

Reason for change Rev. PG# Modify List B.Ver# PhaseFixed IssueItem

1 1

2 2

To cost down. To cost down. 0.2 54 Change Max1845 to Max8743 and remove PD20 and PD21 0.2 DVT

16

To solve Max1902 can locked

17

as adapter plug in and

To solve Max1902 can locked as adapter plug in and uproot out the
electric socket continuous.

0.2 52 Add Precharge circuit. 0.2 DVT

uproot out the electric

socket continuous.

Power select action correct Power select action correct 0.2 55 Add PQ45 and PR199 and PR200 and PC165. 0.2

18

Increase choke rating of

19

5VALWP.

BOM Error of PD2 PD2 shows wrong location PD5 on SAP system, I update it. 49 Change its location from PD5 to PD2.

20

BOM Error of PQ41 and PQ45. SAP system has quantity but shows no location of PQ41 and PQ45. 52,55 Update the location of PQ41 and delete PQ45.

21

EMI issue. EMI's request.

22

Production EOL. SB906100109(TP0610T) will go EOL. 50

23

Time sequence error. Time sequence is error such that B+ can't biuld. 51,52 Change PR52 from SD034470200 to SD028150300.

24

Increase choke rating of 5VALWP.

0.3

0.3

0.3

0.3

0.3

0.3

52 Change PL6 from SH136100020 to SH13690AM00.

56 Change PR136 and PR159 from SD028000000 to SB028220B00.

Change SB906100109 to SB906100200.

Un-populate PC65.
Change PR87 from SD028470200 to SD028000000.

OTP setting adjust. 1 Change PR55 from SD034169200 to SD034205200.

25

Because we change PR52 such that OTP needs to reset.

2 Change PR57 from SD014215108 to SD014182102.0.3 50

0.3

0.3

0.3

0.3

0.3

0.3

0.3

DVT

PVT

PVT

PVT

PVT

PVT

PVT

PVT

Add other circuit of

26

precharge.

3 3

Because we need to populate this circuit such that precharge can
enable.

0.3 48

1 Add PD1 SC11N4148T8(S DIO 1N4148(SM)).
2 Add PR10 SD0111501T6(S RES 1/4W 1.5K +-5% 1206).
3 Add PR11 SD0111501T6(S RES 1/4W 1.5K +-5% 1206).
4 Add PR12 SD0111501T6(S RES 1/4W 1.5K +-5% 1206).

0.3

PVT

5 Add PR13 SD0111501T6(S RES 1/4W 1.5K +-5% 1206).

Un-populate VGA_CORE_P. Because EDL71 is Aviso GM plate form, we don't populate PQ45, PR199,

27

0.3 0.3 PVT54 Delete PQ45, PR199, PR200, PC165.

PR200, PC165.

28

29

30

31

32

4 4

33

Adjust CP point. Because we need to change CP point to improve CP mode. 0.4 49 Change PR35 from SD034226200 to SD034249200. 0.3 EVT

Add PC146 for EDL70. We need to add PC146 such that Vin can more clear and stable. 0.4 54 Add PC146 for1.8VSP of EDL70. 0.3 EVT

To cost down. To cost down. 0.4 54 Change PC147 from SG020151300 to SGA20221120. 0.3 EVT

Precharge circuit tolerance

adjust.

Because the tolerance shuld be 1% but the metirial on BOM is 5%
so we update it.

0.4 54 Change PR52 from SD028150300 to SD034150300. 0.4 EVT

UUT has Zi Zi noice issue. Because we have UUT zi zi noice issue, we add two capacitor to solve it. 0.4 54 Add PC126 and PC127 with SF10004M008. 54 EVT

Noise on S3 mode. Because we found noise on ceramic capacitor, we increase capacitance to

0.4 54 Change PC43 from SE142475K00 to SE142106M00. 54 EVT

decrease this noise.

Compal Electronics, Inc.

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SE CRET INFO RMATI ON. THIS SHEET MAY NO T BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

D

PIR

Size Document Number Rev

EDL71 LA-2351

Date: Sheet

E

of

56 60Thursday, July 28, 2005

0.0

A

B

C

D

E

Version change list (P.I.R. List) Page 3 of 3

Reason for change Rev. PG# Modify List B.Ver# PhaseFixed IssueItem

Make PU8 can into skip mode as S3 mode.

1 1

Make 1.2VSP start up waveform more smooth.

Make 1.8VSP start up waveform more smooth.

To improve noise issue when system
into S3 mode.

To meet EMI request. To meet EMI request. 0.5 55 Add PR203 and PR204 with SD0130000T4. 0.4 PVT

For EDL72, Transfer ISPD BOM Error. BOM error, update to correct value. 0.6 53

For EDL72, Transfer ISPD BOM Error. BOM error, update to correct value. 0.6 53

For EDL72, Transfer ISPD BOM Error.

2 2

For EDL72, Transfer ISPD BOM Error.

For EDL70_72, change AL to AP material.

For EDL70_72, change AL to AP material.

For EDL72, change AL to AP material.

For EDL70_72, change OCP point.

For EDL72, to meet EMI LGA request.

For EDL72, to meet EMI LGA request.

3 3

For EDL72, to meet EMI LGA request.

For EDL70, delete second source of PL7
and PL4.
For EDL71, delete second source of PL7
and PL4.
For EDL72, BOM transfer error. Because BOM of EDL72 of PQ27 and PQ31 show SI4892.It is wrong type for

For EDL72, BOM transfer error.

For EDL70_71_72, change RTC charing
resistor.
For EDL70_72, change VGA_COREP's voltage. Because system runs 3D mark and QuakeIII will hang up, we increase the

4 4

For EDL70_72, change VGA_COREP's voltage. Because system runs 3D mark and QuakeIII will hang up, we increase the

Because the power consumption is too high as S3 mode, we found PU8

doesn't into skip mode, we now improve it.
Because we found the start up waveform which has some delay such that
the waveform does'nt smooth. We improve it.
Because we found the start up waveform which has some delay such that
the waveform does'nt smooth. We improve it.

0.4 52 change PU8 from SGA20221150 to SGA20331D20. 0.4 EVT

0.5 52 Change PC75 from SE074222K00 to SE075472K00. 0.4 PVT

0.5 54 Change PC151 from SE026223K00 to SE026103K00. 0.4 PVT

Because we found that noise occurs when system into S3 mode,

so we need to improve and derease it. 0.5 51

BOM error, update to correct value.

BOM error, update to correct value.

Change AL material to AP material.

Change AL material to AP material.

Change AL material to AP material.

Because EDL70_72 runs 3D Mark2003 will get black screen, we must

increase OCP point from 6.8A~11.408A to 10.714A~17.975A.

To meet EMI request and we can cost down. 54

To meet EMI request and we can cost down.

To meet EMI request and we can cost down.

Because second source vendor can't sent approve sheet on time,

so delete it.

Because second source vendor can't sent approve sheet on time,

so delete it.

original design.
Because BOM of EDL72 of PQ27 and PQ31 show SI4892.It is wrong type for
original design.
Because RTC charge current needs to meet battery spec.

VGA_COREP's voltage level from 1.2V to 1.221V.

VGA_COREP's voltage level from 1.2V to 1.221V.

0.6

0.6

0.6

0.6

0.6

0.6

0.6

0.6

0.6

0.6

0.6

0.6

0.6

0.6

0.6

0.6

Change PC43 from SE142106M00 to SE065106K00.

Change PR115 from SD028200000(S RES 1/16W 200 +-5% 0402) to
SD028000000(S RES 1/16W 0 +- 5% 0402).
Change PR115 from SD028200000(S RES 1/16W 200 +-5% 0402) to
SD028000000(S RES 1/16W 0 +- 5% 0402).
Change PC126 from SF06804M000(S ELE CAP 68U 25V M B(6.3*6.0)

55

CV-GX) to SE10004M008(S ELE CAP 100U 25V M B(6.3*7.7) CV-GX).
Change PC127 from SF06804M000(S ELE CAP 68U 25V M B(6.3*6.0)

55

CV-GX) to SE10004M008(S ELE CAP 100U 25V M B(6.3*7.7) CV-GX).
Change PC124 from SE075103K00(S CER CAP 0.01U 25V K X7R) to

55

SE075103Z00(S CER CAP 0.01U 25V K X7R 0402).
Change PC143 from SE075103K00(S CER CAP 0.01U 25V K X7R) to

55

SE075103Z00(S CER CAP 0.01U 25V K X7R 0402).
Change PC66 from SE135105K00(S CER CAP 1U 16V +-10% X5R 0603)

52

to SE135105KT0(S CER CAP 1U 16V K X5R 0603 TAIYO)
Change PR181 from SD034806100(S RES 1/16W 8.06K +-1% 0402) to

54

SD034127200(S RES 1/16W 12.7K +-1% 0402).

Delete PR201 and PR202 SD011470BT9(S RES 1/4W 4.7 +-5% 1206).

Delete PC200 and PC201 SE024681J00(S CER CAP 680P 50V J NPO

54

0603).
Change PR203 and PR204 from SD0130000T4(S RES 1/16W 0 +-5%

54

0603) to SD013220B00(S RES 1/16W 2.2 +-5% 0603).

49 Delete PL4 SH035150000 and PL7 SH035100000.

49 Delete PL4 SH035150000 and PL7 SH035100000.

Change PQ27 from SB54892(S TR SI4892DY 1N SO-8 W/D) to

54

SB544080000(S TR AO4408 1N SO8 W/D).
Change PQ27 from SB54892(S TR SI4892DY 1N SO-8 W/D) to

54

SB544080000(S TR AO4408 1N SO8 W/D).
Change PR67 and PR68 from SD028300000(S RES 1/16W 300 +-5%

50

0402) to SD028560000(S RES 1/16W 560 +-5% 0402)
Change PR185 from SD034402200(S RES 1/16W 40.2k +-1% 0402) to

54

SD034340200(S RES 1/16W 34K +-1% 0402).
Change PR185 from SD034402200(S RES 1/16W 40.2k +-1% 0402) to

54

SD034340200(S RES 1/16W 34K +-1% 0402).

0.4 PVT

0.5

0.5

0.5

0.5

0.5

0.5

0.5

0.5

0.5

0.5

0.5

0.5

0.5

0.5

0.5

0.5

0.5

0.5

Pre-MP

Pre-MP

Pre-MP

Pre-MP

Pre-MP

Pre-MP

Pre-MP

Pre-MP

Pre-MP

Pre-MP

Pre-MP

Pre-MP

Pre-MP

Pre-MP

Pre-MP

Pre-MP

Pre-MP

Pre-MP

Compal Electronics, Inc.

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SE CRET INFO RMATI ON. THIS SHEET MAY NO T BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

D

PIR

Size Document Number Rev

EDL71 LA-2351

Date: Sheet

E

of

57 60Thursday, July 28, 2005

0.0

A

B

C

D

E

Version change list (P.I.R. List)

Page 3 of 3

Reason for change Rev. PG# Modify List B.Ver# PhaseFixed IssueItem

For EDL70_72, solve black

1 1

screen issue.

For EDL70_72, solve 3D Mark

hang up issue.

For EDL70_72, solve 3D Mark

hang up issue.

2 2

Because EDL70_72 still has black screen pheonomeon. We increase it to 15.692A. 0.7 54

Because EDL70_72 runs 3D Mark will hang at . We need to solve it.

Because EDL70_72 runs 3D Mark will hang at . We need to solve it.

美人頭

美人頭

0.7 54

0.7 54

Change PR181 from SD034127200(S RES 1/16W 12.7K 0402 +-1%) to

SD034162200(S RES 1/16W 16.2K +-1% 0402).
Change PC154 from SE076104K00(S CER CAP 0.1U 16V K X7R 0402) to
SE000000K00(S CER CAP 1U 6.3V K X5R 0402)
Change PQ38 from SB549120000( S TR AO4912 2N SO8 W/D) to
SB000003G00(S TR AO4918 2N SO8).

0.5

0.5

0.5

MP

MP

MP

3 3

4 4

Compal Electronics, Inc.

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SE CRET INFO RMATI ON. THIS SHEET MAY NO T BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

D

PIR

Size Document Number Rev

EDL71 LA-2351

Date: Sheet

E

of

58 60Thursday, July 28, 2005

0.0

A

B

C

D

Version change list (P.I.R. List) Page 3 of 3

E

Reason for change Rev. PG# Modify ListFixed IssueItem

1 1

1 S4 auto resume Can't auto resume from S4 0.4 3 0 Change VCCSUS3_3 from +3V to +3VALW

2 C615 short C615 short to logic low cause can't boot 0.4 35 Change C613 and C615 to SGN01220100

3 bo niose when

shut down
C904 too close

4

to JP12

+1.5V rising edge +1.5V ‘s rising edge is not smooth 0.4 3 0 Add R12

5

SW DJ can't play

6

with Hitach HDD

7 Mode m noise Mode m dial tone have noise 0. 4 39

2 2

speaker generate "bo" niose when system

0.4 45 Change R460 to R461

shut down

C904 too close to JP12 if C904 fail can't repair 0 .4 40 JP12 change to DC233104020

Hitachi HDD send IDE_DIOR# in SW DJ S0 mode 0.4 31,46 Add Q97, R1197, R1198

Change R518, R521 from SD0130000T4 to
SM010012000

8 KB91 0 damage issue KB910 INVT_PWM pin damage issue 0.5 41 Add D32,D33

B.Ver#

0.5

0.5

0.5

0.5

0.5

0.5

0.5

0.6

Phase

PVT

PVT

PVT

PVT

PVT

PVT

PVT

PVT

Change +3V to +3VALW for SMBUS and

S4 auto resume9 Can't auto resume from S4 0.5 29,30

LINKALERT#, EC_SMI#, SYS_RESET#
PM_BATLOW#, GPI11, ICH_PCIE_WAKE#

0.6

PVT

1.5V LDO

10 Bo noise Bo noise gernerate in SWDJ mode and power up 0.5 45 Del R460 and R461, add D35 and D36

11 Backlight issue backlight timing error 0.5 24 Add D34 and R1118

12 Sighting Alert Alviso SMVREF Sighting Alert (# 68363) 0.5 9 No stuff R100 and R101

0.6

0.6

0.6

PVT

PVT

PVT

13 CRT ISSUE CRT NOISE issue Change C119 from SE053106Z00 to

3 3

14 SWDJ issue SWDJ can't play 46 Add Q98

15 USB OC Add USB OC delay circuit 40 Add R1201,R1202,R1203,R1204,R1205,

16 SVIDEO ISSUE SVIDEO out noise issue 12 Change C92 from SE107475M00 to SE077226M10

17 TV TUNNER No sound in IOMP mode 38 ADD TV_AUDIO_R and TV_AUDIO_L

18 Power sequence Power sequence Add C172 for EDL70 power sequence47

19 LCD Power sequence

4 4

for EDL70/72

Power off white screen issue

20 ESD Add ESD diode for USB data and EC INVT_PWM pin

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SE CRET INFO RMATI ON. THIS SHEET MAY NO T BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

0.5

0.5

0.5

0.5

0.5

0.5

1.0 24 Add 1@ on R1118 and D34

1.0 40, 41

C

12

SE077226M10

R1206,C1134,C1135,C1136

Add U70, D38, D39 and D40

D

0.6

0.6

0.6

0.6

0.6

0.6

1.1

PVT

PVT

PVT

PVT

PVT

PVT

PVT

1.1 PVT

Compal Electronics, Inc.

Title

PIR

Size Document Number Rev

EDL71 LA-2351

Date: Sheet

E

of

59 60Thursday, July 28, 2005

0.0

5

4

3

2

Version change list (P.I.R. List) Page 2 of 2

1

Reason for change Rev. PG# Modify ListFixed IssueItem

21 VGA_CORE over spec VGA_CORE drop over 1.14V 1A 30

D D

22 IDE IOR ISSUE Data mismatch or Data lose issue 1B 46 1C MP

Change C212 to 470uF Cap
Add C144, U71, R28, R1210, R42, R43, R77,

No stuff R1200

B.Ver#MPPhase

1B

23 LGA over spec FIX LGA over spec 1B 31 Add C154, C155, C156, C157 1 C MP

C C

B B

A A

Title

<Title>

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SE CRET INFO RMATI ON. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

Custom

2

Size Document Number Rev

<Doc> <RevCode>

Date: Sheet of

60 60Thursday, July 28, 2005

1