COMPAL LA-3031P Schematics

A

1 1

2 2

B

C

D

E

Compal confidential

Schematics Document

Mobile Yonah uFCPGA with Intel
Calistoga_GM+ICH7-M core logic

3 3

4 4

A

B

2006-02-27

REV:0.5

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2006/02/27 2007/02/27

Compal Secret Data

Deciphered Date

Feb 27, 2007

Title

Size Docume nt Number Re v

D

Date : Sheet o f

Compal Electronics, Inc.

Cover Sheet

LA-3031P

1 49Tuesd ay, Febru ary 28, 2006

E

0.5

A

Compal confidential

File Name : LA-3031

B

C

Heavenly 2.0

D

E

1 1

2 2

DOCK/DVI

page 34

DVI controller
CH 7307C- DE

page 17

CRT/TV-OUT

pag e 16

LCD CONN

page 17 page 29

Fan Control

SD VO

PCI-E BUS

page 4

Mobile Yonah & Merom

uF CPGA-478 CPU

page 4,5,6

H_ A# (3.. 31)

FSB

533/667MHz

Intel Calistoga GMCH

945GM

PCBG A 1466

page 7,8,9,10,11,12

DM I

H_ D#( 0..6 3)

Thermal Sensor
ADM1032AR

page 4

DDR2 -400/533/667

Dual Channel

USB2.0

Clock Generator

IC S9L P306

DDR- SO-DIMM X2

BAN K 0, 1, 2, 3

FingerPrinter
AES2501

page 13,14

page 29

USB conn x3

BT Conn

page 29

page 15

MDC1. 5

page 31

PCI BUS

Intel ICH7-M

Gigabit LAN

BC M 5 75 3M

page 24

3 3

RTC CKT.

page 19

RJ45 /11 CONN

page 25

Mini C ard
socket

page 26

CardBus Controller

TI PCI6 612

page 22,23

Slot 0

page 23

SD/SDIO Slot

page 22

mBGA-652

page 18,19,20,21

SPI ROM

25LF080A

AC-LINK/Azalia

SATA Master

SPI

page 31

LPC BUS

Power OK C KT.

page 36

SMSC Super I/O

Power On/Off CKT.

page 33

4 4

DC/DC Interface CKT.

page 35

COM1 on
Docking side

LPC47N217

page 30

page 30

Touch Pad CONN. Int.KBD

page 33

SMSC KBC 1021

page 32

page 33

page 31

Audio CKT

AD1981HD

page 27

SATA HDD
Co nnector

page 19

SST49LF008A

AMP & Audio Jack

page 28

Docking CONN.

*RJ-45(LED*2)
*RJ-11(Pass Through)
*CRT
*COMPOSITE Video Out
*TVOUT
*DVI
*LINE IN
*LINE OUT
*PCI-E x2

Flash ROMSecurity Module

page 31

*Serial Port
*Parallel Port
*PS/2 x2
*USB x2
*DC JACK

page 34

Power Circuit DC/DC

36,37,38,39,40,41,42,43

A

LPT on
Docking side

page 30

FIR

B

page 30

Digitizer

page 17

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2006/02/27 2007/02/27

Compal Secret Data

Deciphered Date

D

Title

Size Docume nt Number Re v

Date : Sheet o f

Compal Electronics, Inc.

Block Diagram

LA-3031P

2 49Tuesd ay, Febru ary 28, 2006

E

0.5

A

Voltage Rails Symbol note:

Power Plane

VIN

B+

+CPU_CORE

+VCCP

+0.9VS

+1.5VS

+1.8V

+2.5VS

+3VALW

+3V

+5VALW

+5V

+5VS

RTCVCC

Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.

Description

Adapter power supply (19V)

AC or battery power rail for power circuit

Core voltage for CPU

1.05V power rail for Processor I/O and MCH core power

0.9V switched power rail for DDRII Vtt

1.5V switched power rail for PCI-E interface

1.8V power rail for DDRII

3.3V always on power rail

3V power rail

3.3V switched power rail+3VS

5V always on power rail

5V power rail

5V switched power rail

RTC power

S0-S1

N/A

ON OFF

ON

ON

ON

ON

ON

ON

ON OFF

ON

ON

ON

ON

S3

N/A

N/A

OFF

OFF

OFF

ON

ON2.5V always on power rail+2.5VALW ON*ON

OFF

ON

ON

OFF

ON

ON

OFF

ON

S5

N/A

N/AN/A

OFF

OFF

OFF

OFF

OFF

OFF2.5V switched power rail for MCH video PLL

ON*

OFF

ON*

OFF

OFF

ONON

:means digital ground.

:means analog ground.

:means reserved.@

@ : means just reserve , no build
SPI@ : means just build when SPI I/F BIOS function enable.
FWH@ : means just build when FWH I/F BIOS function enable.
NOXDP@ : means just build when XDP function disable.
XDP@ : means just build when XDP function enable. When this time, docking PCI express will not work.
TPM@ : means just build when TPM1.2 function enable.
250@ : means just build when SMsC LPC47N250 chip selected.
1021@ : means just build when SMsC KBC1021 chip selected.
45@ : means need be mounted when 45 level assy or rework stage.
ACCEL@ : means just build when Accelerometer chip LIS3LV02DQ selected.
DVI_7307@ : means just build when DVI chip CH7307 selected.
DVI_1362@ : means just build when DVI chip SIL1362 selected.

1 1

Internal PCI Devices

DE VICE

L AN

Az ali a D27

USB1 .1/2 .0

PCI to PC I (D MI to PCI)

AC9 7 MO DEM

AC9 7 Au di o

PA TA /S ATA

LPC I/F

SM BU S

PCI Devi ce ID

D8

D28PCI- E

D29

D30

D30

D30

D31

D31

D31

IDS EL #

AD2 4

AD1 1

AD1 2

AD1 3

AD1 4

AD1 4

AD1 4

AD1 5

AD1 5

AD1 5

(D is ab le d by BI OS )

(D is ab le d by BI OS )

(P AT A is D is abled b y B IOS)

External PCI Devices

DE VICE

CA RD BU S

PCI Devi ce ID

D6

I2C / SMBUS ADDRESSING

DE VICE

DDR S O-DIMM 0

DDR S O-DIMM 1

CL OC K G EN ER ATOR (E XT.)

HEX

A0

A4

D2

IDS EL #

AD2 2

AD DRESS

1 0 1 0 0 0 0 0

1 0 1 0 0 1 0 0

1 1 0 1 0 0 1 0

REQ /G NT #

2

PIR Q

C D E G

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

2006/02/27 2007/02/27

Compal Secret Data

Deciphered Date

Title

Size Docume nt Number Re v

Date : Sheet o f

Compal Electronics, Inc.

Notes List

LA-3031P

3 49Tuesd ay, Febru ary 28, 2006

0.5

5

4

3

2

1

H_A#[3 ..31]7

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8

D D

H_REQ# [0..4]7

H_ADSTB#07

C C

R560

56_0402_5%

1 2

+VCCP

B B

H_PROCHOT #43

1 2

+VCCP

68_0402_5%

H_ADSTB#17

CLK_CPU _BCLK15

CLK_CPU_ BCLK#15

H_BPRI#7

H_DEF ER#7

H_D RDY#7

H_HITM#7

H_LOCK#7

H_RESET#7

H_RS# [0..2]7

H_TR DY#7

XDP_DBRESET#20

H_DB SY#7

H_DPSLP#19

H_DPRSTP#19,43

H_DPW R#7

R561

H_PWR GOOD19

H_CPUSLP #7

R562 1K_0402_5%@

1 2

R563 51_0402_5%

1 2

H_ADS#7
H_BNR #7

H_BR0#7

H_HIT#7

7/14

H_THERMDA, H _THERMDC routing together.
Trace width / Spacing = 10 / 10 mil

A A

H_PROCHOT # OCP#

H_THERMTRIP#7,19

+VCCP

12

R564

B

2

E

3 1

Q73

MMBT3904_SOT23

@

56_0402_5%@

C

5

H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

H_ADSTB#0
H_ADSTB#1

CLK_CP U_BCLK
CLK_CPU _BCLK#

H_ADS#
H_BN R#
H_BPRI #
H_BR0#
H_DEF ER#
H_D RDY#
H_HIT#
H_HITM#
H_I ERR#
H_LOCK#
H_RESET#

H_RS#0
H_RS#1
H_RS#2
H_T RDY#

XDP_BPM#0
XDP_BPM#1
XDP_BPM#2
XDP_BPM#3

XDP_DBRESET#

H_DB SY#
H_DPSLP#
H_DPRSTP#
H_DPW R#
XDP_BPM#4
XDP_BPM#5
H_PROCHOT #

H_PW RGOOD
H_CPUSL P#
XDP_TCK
XDP_TDI
XDP_TDO
TEST1
TEST2

XDP_TMS

XDP_TRST#

H_THERMDA
H_THERM DC
H_THERMTRIP#

OCP# 20,44

JP12A

J4

A3#

L4

A4#

M3

A5#

K5

A6#

M1

A7#

N2

A8#

J1

A9#

N3

A10#

P5

A11#

P2

A12#

L1

A13#

P4

A14#

P1

A15#

R1

A16#

Y2

A17#

U5

A18#

R3

A19#

W6

A20#

U4

A21#

Y5

A22#

U2

A23#

R4

A24#

T5

ADDR G ROUP

A25#

T3

A26#

W3

A27#

W5

A28#

Y4

A29#

W2

A30#

Y1

A31#

K3

REQ0#

H2

REQ1#

K2

REQ2#

J3

REQ3#

L5

REQ4#

L2

ADSTB0#

V4

ADSTB1#

A22

BCLK0

A21

H1

E2

G5

F1

H5

F21

G6

E4

D20

H4

B1

F3

F4
G3
G2

AD4
AD3
AD1
AC4

C20

E1

B5

E5

D24
AC2
AC1
D21

D6
D7

AC5
AA6
AB3
C26
D25
AB5
AB6

A24
A25

C7

HOST CLK

BCLK1

ADS#
BNR#
BPRI#
BR0#
DEFER#
DRDY#
HIT#

CONTROL

HITM#
IERR#
LOCK#
RESET#

RS0#
RS1#
RS2#
TRDY#

BPM0#
BPM1#
BPM2#
BPM3#

DBR#
DBSY#
DPSLP#
DPRSTP#
DPWR#
PRDY#
PREQ#
PROCHOT#

PWRGOOD
SLP#
TCK
TDI
TDO
TEST1
TEST2
TMS
TRST#

THERMAL

THERMDA

DIODE

THERMDC
THERMTRIP#

FOX_PZ4790 3-2741-42_YONAH

YONAH

DATA GROUP

MISC

LEGACY CPU

7/19

4

D10#
D11#
D12#
D13#
D14#
D15#
D16#
D17#
D18#
D19#
D20#
D21#
D22#
D23#
D24#
D25#
D26#
D27#
D28#
D29#
D30#
D31#
D32#
D33#
D34#
D35#
D36#
D37#
D38#
D39#
D40#
D41#
D42#
D43#
D44#
D45#
D46#
D47#
D48#
D49#
D50#
D51#
D52#
D53#
D54#
D55#
D56#
D57#
D58#
D59#
D60#
D61#
D62#
D63#

DINV0#
DINV1#
DINV2#
DINV3#

DSTBN0#
DSTBN1#
DSTBN2#
DSTBN3#
DSTBP0#
DSTBP1#
DSTBP2#
DSTBP3#

A20M#
FERR#

IGNNE#

INIT#
LINT0
LINT1

STPCLK#

SMI#

H_D#0

E22

D0#

H_D#1

F24

D1#

H_D#2

E26

D2#

H_D#3

H22

D3#

H_D#4

F23

D4#

H_D#5

G25

D5#

H_D#6

E25

D6#

H_D#7

E23

D7#

H_D#8

K24

D8#

H_D#9

G24

D9#

H_D#10

J24

H_D#11

J23

H_D#12

H26

H_D#13

F26

H_D#14

K22

H_D#15

H25

H_D#16

N22

H_D#17

K25

H_D#18

P26

H_D#19

R23

H_D#20

L25

H_D#21

L22

H_D#22

L23

H_D#23

M23

H_D#24

P25

H_D#25

P22

H_D#26

P23

H_D#27

T24

H_D#28

R24

H_D#29

L26

H_D#30

T25

H_D#31

N24

H_D#32

AA23

H_D#33

AB24

H_D#34

V24

H_D#35

V26

H_D#36

W25

H_D#37

U23

H_D#38

U25

H_D#39

U22

H_D#40

AB25

H_D#41

W22

H_D#42

Y23

H_D#43

AA26

H_D#44

Y26

H_D#45

Y22

H_D#46

AC26

H_D#47

AA24

H_D#48

AC22

H_D#49

AC23

H_D#50

AB22

H_D#51

AA21

H_D#52

AB21

H_D#53

AC25

H_D#54

AD20

H_D#55

AE22

H_D#56

AF23

H_D#57

AD24

H_D#58

AE21

H_D#59

AD21

H_D#60

AE25

H_D#61

AF25

H_D#62

AF22

H_D#63

AF26

H_DI NV#0

J26

H_DI NV#1

M26

H_DI NV#2

V23

H_DI NV#3

AC20

H_DSTBN#0

H23

H_DSTBN#1

M24

H_DSTBN#2

W24

H_DSTBN#3

AD23

H_DSTBP#0

G22

H_DSTBP#1

N25

H_DSTBP#2

Y25

H_DSTBP#3

AE24

H_A20M#

A6

H_F ERR#

A5

H_IG NNE#

C4

H_INIT #

B3

H_INT R

C6

H_NMI

B4

H_STPCLK#

D5

H_SMI#

A3

H_D#[ 0..63] 7

R556

1K_0402_5%

+VCCP +VCCP

H_DIN V#0 7
H_DIN V#1 7
H_DIN V#2 7
H_DIN V#3 7

H_DST BN#[0..3] 7

H_DST BP#[0..3] 7

H_A20M# 19
H_FE RR# 19
H_IGN NE# 19
H_INIT# 19
H_INT R 19
H_NMI 19

H_STPCLK# 19
H_SMI# 19

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/02/27 2007/02/27

ITP-XDP Connector

JP19

1

XDP_BPM#5
XDP_BPM#4

XDP_BPM#3
XDP_BPM#2

XDP_BPM#1
XDP_BPM#0

H_PW RGOOD_RH_PWRGOOD CLK_CPU_XDP

12

12

C590 0.1U_0402_16 V4Z

ICH_SMBDATA
ICH_SMBC LK

XDP_TCK

GND0

3

OBSFN_A0

5

OBSFN_A1

7

GND2

9

OBSDATA_A0

11

OBSDATA_A1

13

GND4

15

OBSDATA_A2

17

OBSDATA_A3

19

GND6

21

OBSFN_B0

23

OBSFN_B1

25

GND8

27

OBSDATA_B0

29

OBSDATA_B1

31

GND10

33

OBSDATA_B2

35

OBSDATA_B3

37

GND12

39

PWRGOOD/HOOK0

41

HOOK1

43

VCC_OBS_AB

45

HOOK2

47

HOOK3

49

GND14

51

SDA

53

SCL

55

TCK1

57

TCK0

59

GND16

OBSDATA_C0
OBSDATA_C1

OBSDATA_C2
OBSDATA_C3

OBSDATA_D0
OBSDATA_D1

OBSDATA_D2
OBSDATA_D3

ITPCLK/HOOK4

ITPCLK#/HOOK5

VCC_OBS_CD

RESET#/HOOK6

DBR#/HOOK7

SAMTE_BSH-030-01-L-D-A

GND1
OBSFN_C0
OBSFN_C1

GND3

GND5

GND7
OBSFN_D0
OBSFN_D1

GND9

GND11

GND13

GND15

TRST#

TMS

GND17

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

CLK_CPU_XDP#

42
44
46
48
50

XDP_TDO

52

TD0

TDI

XDP_TRST#

54

XDP_TDI

56

XDP_TMS

58

XDP_PRE

60

Thermal Sensor ADM1032

+3VS

2

C273

0.1U_0402_ 16V4Z

C264

1 2

2200P_0402_50V7K

1 2

+3VS

PWM Fan Control circuit

FAN_PWM32

THERM#

Compal Secret Data

Deciphered Date

1

U16

1

VDD

H_THERMDA

H_THERM DC THERM_SCI#

R228
10K_0402_5%

+3VS

5

1

INB

2

INA

3

2

3

THERM#

Address:1001 _101

CH751H-40 _SC76

U24

P

4

O

G

TC7SH00FUF _SSOP5

2

SCLK

D+

SDATA

ALERT#

D-

THERM#4GND

ADM1032ARMZ-2REEL MSOP8

ICH_SMBCL K13,14,15,2 0,24,26

ICH_SMBDATA13,14,15,2 0,24,26

+5VS

2 1

6

2

1

G

3

S

4 5

AO6402_TSOP6

ICH_SMBC LK

8

ICH_SMBDATA

7

6

5

ICH_SMBC LK
ICH_SMBDATA

1

D11

2

1000P_0402_50V7K

Q33

D

Title

Size Docume nt Number Re v

Date : Sheet of

XDP_DBRESET#_R

XDP_TDI

XDP_TMS

XDP_BPM#5

XDP_TRST#

XDP_TCK

This shall place near JP19

XDP_TDO

1K_0402_1%

R557

1 2

R558

200_0402_1%

1 2

R549

1 2

This shall place near CPU

R550 56_0402_5%

1 2

R551 56_0402_1%

1 2

R553 56_0402_5%

1 2

R554 56_0402_5%

1 2

R555 56_0402_5%

1 2

R552 56_0402_5%

1 2

H_RESET#H_RESET#_R
XDP_DBRESET#XDP_DBRESET#_R

12

R559
0_0402_5%

9/2

12

R227
10K_0402_5%

THERM_SCI# 20

1

C932

2

7/28

1

C933

2

1000P_0402_50V7K

C122

4.7U_0805_ 10V4Z

12

ZD1

RLZ5.1B_LL 34@

1

C125

2

0.1U_0402_16 V4Z

FAN

Compal Electronics, Inc.

Yonah CPU in mFCPGA479

LA-3031P

1K_0402_5%@

CLK_CPU_XDP 15
CLK_CPU_XDP# 15

ACES_85205-0200

1

JP8

1
2

4 49Tuesd ay, Febru ary 28, 2006

+3VS

+VCCP

+VCCP

0.5

5

4

3

2

1

+VCCP

D D

V_CPU_GTLR EF

Close to CPU pin AD26
within 500mils.

C C

B B

12

R567
1K_0402_1%

12

R570
2K_0402_1%

+VCC_C ORE

R568
100_0402_1%

1 2

R569
100_0402_1%

1 2

VCCSENS E

VSSSENSE

Close to CPU pin
within 500mils.

CPU_BSEL CPU_BSEL2 CPU_BSEL1

133

166

12

R571

27.4_0402_1%

0 0

0

12

R573

R572

54.9_0402_1%

Length match within 25 mils
The trace width 18 mils space
7 mils

+1.5VS

1

C592

C591

2

.01U_0402_16V7K

10U_0805_10V4Z

CPU_BSEL0

1

1

12

12

R574

54.9_0402_1%

27.4_0402_1%

1

Resistor placed within

0.5" of CPU pin.Trace
should be at least 25
mils away from any
other toggling signal.

1

2

CPU_V ID043
CPU_V ID143
CPU_V ID243
CPU_V ID343
CPU_V ID443
CPU_V ID543
CPU_V ID643

V_CPU_GTLR EF

CPU_BSEL015
CPU_BSEL115
CPU_BSEL215

VCCSENS E43
VSSSENSE43

H_PSI#43

+VCCP

+VCC_C ORE

VCCSENS E
VSSSENSE

H_PSI#

CPU_ VID0
CPU_ VID1
CPU_ VID2
CPU_ VID3
CPU_ VID4
CPU_ VID5
CPU_ VID6

CPU_BSEL0
CPU_BSEL1
CPU_BSEL2

COMP0
COMP1
COMP2
COMP3

JP12B

AF7

VCCSENSE

AE7

VSSSENSE

B26

VCCA

K6

VCCP

J6

VCCP

M6

VCCP

N6

VCCP

YONAH

VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP

PSI#

VID0
VID1
VID2
VID3
VID4
VID5
VID6

GTLREF

BSEL0
BSEL1
BSEL2

COMP0
COMP1
COMP2
COMP3

VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC

RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD

FOX_PZ4790 3-2741-42_YONAH

W21

AD26

AB20
AA20
AF20
AE20
AB18
AB17
AA18
AA17
AD18
AD17
AC18
AC17
AF18
AF17

T6

R6

K21

J21
M21
N21
T21
R21
V21

V6

G21

AE6

AD6
AF5
AE5
AF4
AE3
AF2
AE2

B22
B23
C21

R26
U26

U1

V1

E7

D2

F6
D3
C1

AF1
D22
C23
C24
AA1
AA4
AB2
AA3

M4
N5

T2

V3

B2
C3

T22
B25

+VCC_C ORE

AB26

VSS

AA25

VSS

AD25

VSS

AE26

VSS

AB23

VSS

AC24

VSS

AF24

VSS

AE23

VSS

AA22

VSS

AD22

VSS

AC21

VSS

AF21

VSS

AB19

VSS

AA19

VSS

AD19

VSS

AC19

VSS

AF19

VSS

AE19

VSS

AB16

VSS

AA16

VSS

AD16

VSS

AC16

VSS

AF16

VSS

AE16

VSS

AB13

VSS

AA14

VSS

AD13

VSS

AC14

VSS

AF13

VSS

AE14

VSS

AB11

VSS

AA11

VSS

AD11

VSS

AC11

VSS

AF11

VSS

AE11

VSS

AB8

VSS

AA8

VSS

AD8

VSS

AC8

VSS

AF8

VSS

AE8

VSS

AA5

VSS

AD5

VSS

AC6

VSS

AF6

VSS

AB4

VSS

AC3

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

AF3
AE4
AB1
AA2
AD2
AE1
B6
C5
F5
E6
H6
J5
M5
L6
P6
R5
V5
U6
Y6
A4
D4
E3
H3
G4
K4
L3
P3
N4
T4
U3
Y3
W4
D1
C2
F2
G1

POWER, GROU NG, RE SERVED S IGNALS AND NC

JP12C

AE18

VCC

AE17

VCC

AB15

VCC

AA15

VCC

AD15

VCC

AC15

VCC

AF15

VCC

AE15

VCC

AB14

VCC

AA13

VCC

AD14

VCC

AC13

VCC

AF14

VCC

AE13

VCC

AB12

VCC

AA12

VCC

AD12
AC12
AF12
AE12
AB10

AB9

AA10

AA9

AD10

AD9

AC10

AC9

AF10

AF9

AE10

AE9
AB7
AA7
AD7
AC7
B20
A20
F20
E20
B18
B17
A18
A17
D18
D17
C18
C17
F18
F17
E18
E17
B15
A15
D15
C15
F15
E15
B14
A13
D14
C13
F14
E13
B12
A12
D12
C12
F12
E12
B10

A10

D10

C10

F10

E10

B9

A9

D9

C9

F9

E9
B7
A7
F7

YONAH

VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC

POWER, GROUND

VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC

FOX_PZ4790 3-2741-42_YONAH

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

K1
J2
M2
N1
T1
R2
V2
W1
A26
D26
C25
F25
B24
A23
D23
E24
B21
C22
F22
E21
B19
A19
D19
C19
F19
E19
B16
A16
D16
C16
F16
E16
B13
A14
D13
C14
F13
E14
B11
A11
D11
C11
F11
E11
B8
A8
D8
C8
F8
E8
G26
K26
J25
M25
N26
T26
R25
V25
W26
H24
G23
K23
L24
P24
N23
T23
U24
Y24
W23
H21
J22
M22
L21
P21
R22
V22
U21
Y21

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/02/27 2007/02/27

Compal Secret Data

Deciphered Date

Title

Size Docume nt Number Re v

2

Date : Sheet

Compal Electronics, Inc.

Yonah CPU in mFCPGA479

LA-3031P

1

o f

5 49Tuesd ay, Febru ary 28, 2006

0.5

5

4

3

2

1

D D

Place these capacitors on L8
(North side ,Secondary Layer)

Place these capacitors on L8
(North side ,Secondary Layer)

Place these capacitors on L8
(Sorth side ,Secondary Layer)

C C

Place these capacitors on L8
(Sorth side ,Secondary Layer)

South Side S econdary

B B

330U_D2E_2. 5VM_R9@

+VCC_C ORE

1

C593

10U_0805_6.3V6M

2

+VCC_C ORE

1

C601

10U_0805_6.3V6M

2

+VCC_C ORE

1

C609

10U_0805_6.3V6M

2

+VCC_C ORE

1

C617

10U_0805_6.3V6M

2

+VCC_C ORE

1

+

C626

C625

2

330U_D2E_2. 5VM_R9

1/4 1/4

330U_D2E_2. 5VM_R9

1

+

C627

2

1

C594

10U_0805_6.3V6M

2

1

C602

10U_0805_6.3V6M

2

1

C610

10U_0805_6.3V6M

2

1

C618

10U_0805_6.3V6M

2

1

+

C628

2

330U_D2E_2. 5VM_R9

@

1

+

2

1

2

1

2

1

2

1

2

330U_D2E_2. 5VM_R9

C629

C595

10U_0805_6.3V6M

C603

10U_0805_6.3V6M

C611

10U_0805_6.3V6M

C619

10U_0805_6.3V6M

1

+

C630

2

1

C596

10U_0805_6.3V6M

2

1

C604

10U_0805_6.3V6M

2

1

C612

10U_0805_6.3V6M

2

1

C620

10U_0805_6.3V6M

2

North Side S econdary

1

+

2

330U_D2E_2. 5VM_R9

1

C597

10U_0805_6.3V6M

2

1

C605

10U_0805_6.3V6M

2

1

C613

10U_0805_6.3V6M

2

1

C621

10U_0805_6.3V6M

2

1

C598

10U_0805_6.3V6M

2

1

C606

10U_0805_6.3V6M

2

1

C614

10U_0805_6.3V6M

2

1

C622

10U_0805_6.3V6M

2

1

C599

10U_0805_6.3V6M

2

1

C607

10U_0805_6.3V6M

2

1

C615

10U_0805_6.3V6M

2

1

C623

10U_0805_6.3V6M

2

ESR = 1.5m ohm
Capacitor = 1980uF

1

C600

10U_0805_6.3V6M

2

1

C608

10U_0805_6.3V6M

2

1

C616

10U_0805_6.3V6M

2

1

C624

10U_0805_6.3V6M

2

Mid Frequence Decoupling

+VCCP

220U_D2_2VK_R9

1

+

C634

2

A A

1

C635

0.1U_0402_16 V4Z

2

1

C636

0.1U_0402_ 16V4Z

2

1

C637

0.1U_0402_16 V4Z

2

1

C638

0.1U_0402_16 V4Z

2

1

C639

0.1U_0402_16 V4Z

2

1

C640

0.1U_0402_16 V4Z

2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

Place these inside
socket cavi ty on L8
(North side
Secondary)

2006/02/27 2007/02/27

Compal Secret Data

Deciphered Date

2

Title

Size Docume nt Number Re v

Date : Sheet of

Compal Electronics, Inc.

CPU Bypass capacitors

LA-3031P

6 49Tuesd ay, Febru ary 28, 2006

1

0.5

5

4

3

2

1

H_D# [0..63]4

D D

C C

+VCCP

12

12

R577

R578

54.9_0402_1%

L

H_XS COMP /H_Y SCOM P tr ace
width a nd spacin g is 5/20.

B B

A A

54.9_0402_1%

12

R583

24.9_0402_1%

+VCCP

12

R597

100_0402_1%

12

R601

200_0402_1%

H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63

H_VR EF
H_XRCOMP
H_XSCOMP
H_YR COMP
H_YSCO MP
H_SWN G0
H_SWN G1

12

R584

24.9_0402_1%

Layout Note:
H_XRCOMP / H _YRCOMP / H_VREF / H_SWNG0 /
H_SWNG1 trac e width and spacing is 18/20.

H_VR EF

1

C644

2

0.1U_0402_16 V4Z

5

U15A

F1

HD0#

J1

HD1#

H1

HD2#

J6

HD3#

H3

HD4#

K2

HD5#

G1

HD6#

G2

HD7#

K9

HD8#

K1

HD9#

K7

HD10#

J8

HD11#

H4

HD12#

J3

HD13#

K11

HD14#

G4

HD15#

T10

HD16#

W11

HD17#

T3

HD18#

U7

HD19#

U9

HD20#

U11

HD21#

T11

HD22#

W9

HD23#

T1

HD24#

T8

HD25#

T4

HD26#

W7

HD27#

U5

HD28#

T9

HD29#

W6

HD30#

T5

HD31#

AB7

HD32#

AA9

HD33#

W4

HD34#

W3

HD35#

Y3

HD36#

Y7

HD37#

W5

HD38#

Y10

HD39#

AB8

HD40#

W2

HD41#

AA4

HD42#

AA7

HD43#

AA2

HD44#

AA6

HD45#

AA10

HD46#

Y8

HD47#

AA1

HD48#

AB4

HD49#

AC9

HD50#

AB11

HD51#

AC11

HD52#

AB3

HD53#

AC2

HD54#

AD1

HD55#

AD9

HD56#

AC1

HD57#

AD7

HD58#

AC6

HD59#

AB5

HD60#

AD10

HD61#

AD4

HD62#

AC8

HD63#

J13

HVREF0

K13

HVREF1

E1

HXRCOMP

E2

HXSCOMP

Y1

HYRCOMP

U1

HYSCOMP

E4

HXSWING

W1

HYSWING

QG82945GM QK56 A3 FCBGA 1466

HOST

HA3#
HA4#
HA5#
HA6#
HA7#
HA8#

HA9#
HA10#
HA11#
HA12#
HA13#
HA14#
HA15#
HA16#
HA17#
HA18#
HA19#
HA20#
HA21#
HA22#
HA23#
HA24#
HA25#
HA26#
HA27#
HA28#
HA29#
HA30#
HA31#

HREQ#0
HREQ#1
HREQ#2
HREQ#3
HREQ#4

HADSTB#0
HADSTB#1

HCLKN
HCLKP

HDSTBN#0
HDSTBN#1
HDSTBN#2
HDSTBN#3
HDSTBP#0
HDSTBP#1
HDSTBP#2
HDSTBP#3

HDINV#0
HDINV#1
HDINV#2
HDINV#3

HCPURST#

HADS#

HTRDY#

HDPWR#

HDRDY#

HDEFER#

HHITM#

HHIT#

HLOCK#

HBREQ0#

HBNR#
HBPRI#

HDBSY#

HCPUSLP#

HRS0#
HRS1#
HRS2#

12

R595

12

R599

221_0603_1%

100_0402_1%

H9
C9
E11
G11
F11
G12
F9
H11
J12
G14
D9
J14
H13
J15
F14
D12
A11
C11
A12
A13
E13
G13
F12
B12
B14
C12
A14
C14
D14

D8
G8
B8
F8
A8

B9
C13

AG1
AG2

K4
T7
Y5
AC4
K3
T6
AA5
AC5

J7
W8
U3
AB10

B7
E8
E7
J9
H8
C3
D4
D3
B3
C7
C6
F6
A7
E3

B4
E6
D6

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

H_ADSTB#0
H_ADSTB#1

CLK_MCH_BCL K#
CLK_MCH_B CLK

H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3
H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3

H_DI NV#0
H_DI NV#1
H_DI NV#2
H_DI NV#3

H_RESET#
H_ADS#
H_T RDY#
H_DPW R#
H_D RDY#
H_DEF ER#
H_HITM#
H_HIT#
H_LOCK#
H_BR0#
H_BN R#
H_BPRI #
H_DB SY#
H_CPUSL P#

H_RS#0
H_RS#1
H_RS#2

H_SWN G0

1

C642

2

0.1U_0402_16 V4Z

4

+VCCP+VCCP

12

R596

12

R600

H_A#[3 ..31] 4

H_REQ# [0..4] 4

H_ADSTB#0 4
H_ADSTB#1 4

CLK_MCH_BCL K# 15
CLK_MCH_BCL K 15
H_DST BN#[0..3] 4

H_DSTBP #[0..3] 4

H_DIN V#0 4
H_DIN V#1 4
H_DIN V#2 4
H_DIN V#3 4

H_RESET# 4
H_ADS# 4
H_TR DY# 4
H_DPW R# 4
H_D RDY# 4
H_DEF ER# 4
H_HITM# 4
H_HIT# 4
H_LOCK# 4
H_BR0# 4
H_BNR # 4
H_BPRI # 4
H_DB SY# 4
H_CPUSLP # 4

H_RS# [0..2] 4

221_0603_1%

H_SWN G1

1

2

100_0402_1%

0.1U_0402_16 V4Z

U15B

AE35

DMIRXN0

AF39

DMIRXN1

AG35

DMIRXN2

AH39

DMIRXN3

AC35

DMIRXP0

AE39

DMIRXP1

AF35

DMIRXP2

AG39

DMIRXP3

AE37

DMITXN0

AF41

DMITXN1

AG37

DMITXN2

AH41

DMITXN3

AC37

DMITXP0

AE41

DMITXP1

AF37

DMITXP2

AG41

DMITXP3

AY35

SM_CK0

AR1

SM_CK1

AW7

SM_CK2

AW40

SM_CK3

AW35

SM_CK0#

AT1

SM_CK1#

AY7

SM_CK2#

AY40

SM_CK3#

AU20

SM_CKE0

AT20

SM_CKE1

BA29

SM_CKE2

AY29

SM_CKE3

AW13

SM_CS0#

AW12

SM_CS1#

AY21

SM_CS2#

AW21

SM_CS3#

AL20

SM_OCDCOMP0

AF10

SM_OCDCOMP1

BA13

SM_ODT0

BA12

SM_ODT1

AY20

SM_ODT2

AU21

SM_ODT3

AV9

SM_RCOMPN

AT9

SM_RCOMPP

AK1

SM_VREF0

AK41

SM_VREF1

G28

PM_BMBUSY#

F25

PM_EXTTS0#

H26

PM_EXTTS1#

G6

PM_THERMTRIP#

AH33

PWROK

AH34

RSTIN#

K28

ICH_SYNC#

QG82945GM QK56 A3 FCBGA 1466

Layout Note :
Route as sh ort
as possible

12

12

R591

R590

40.2_0402_1%@

40.2_0402_1%@

DMI

DDR MUXING

M_OCDOCMP0
M_OCDOCMP1

CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8

CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG16

CFG

CFG17
CFG18
CFG19
CFG20

G_CLKP

G_CLKN

D_REF_CLKN
D_REF_CLKP

CLKNC

D_REF_SSCLKN
D_REF_SSCLKP

CLK_REQ#

NC0
NC1
NC2
NC3
NC4
NC5
NC6
NC7
NC8

NC9
NC10
NC11
NC12
NC13
NC14
NC15
NC16
NC17
NC18

RESERVED1
RESERVED2

RESERVED

RESERVED3
RESERVED4
RESERVED5
RESERVED6
RESERVED7
RESERVED8

RESERVED9
RESERVED10
RESERVED11
RESERVED12
RESERVED13

PM_EXTTS#0

PM_EXTTS#1

PM

V_DDR_ MCH_REF13,14

DDR_THERM #13,14

DPRSLPV R20, 43

9/29

+1.8V

12

12

R587

100_0402_1%

12

R592

100_0402_1%

DMI_TXN0
DMI_TXN1
DMI_TXN2
DMI_TXN3

DMI_TXP0
DMI_TXP1
DMI_TXP2
DMI_TXP3

DMI_RXN0
DMI_RXN1
DMI_RXN2
DMI_RXN3

DMI_RXP0
DMI_RXP1
DMI_RXP2
DMI_RXP3

M_CLK_DD R0
M_CLK_DD R1
M_CLK_DD R2
M_CLK_DD R3

M_CLK_DDR #0
M_CLK_DDR #1
M_CLK_DDR #2
M_CLK_DDR #3

DDR_CKE0 _DIMMA
DDR_CKE1 _DIMMA
DDR_CKE2 _DIMMB
DDR_CKE3 _DIMMB

DDR_CS0_D IMMA#
DDR_CS1_D IMMA#
DDR_CS2_D IMMB#
DDR_CS3_D IMMB#

M_OCDOCMP0
M_OCDOCMP1

M_ODT0
M_ODT1
M_ODT2
M_ODT3

SMRCOMPN
SMRCOMPP

PM_BMBUSY#
PM_EXTTS#0
PM_EXTTS#1
H_THERMTRIP#
PWROK
PLTRST_R#

PWROK

DMI_TXN020
DMI_TXN120
DMI_TXN220
DMI_TXN320

DMI_TXP020
DMI_TXP120
DMI_TXP220
DMI_TXP320

DMI_RXN020
DMI_RXN120
DMI_RXN220
DMI_RXN320

DMI_RXP020
DMI_RXP120
DMI_RXP220
DMI_RXP320

M_CLK_DDR 013
M_CLK_DDR 113
M_CLK_DDR 214
M_CLK_DDR 314

M_CLK_DDR# 013
M_CLK_DDR# 113
M_CLK_DDR# 214
M_CLK_DDR# 314

DDR_CKE0_ DIMMA13
DDR_CKE1_ DIMMA13
DDR_CKE2_ DIMMB14
DDR_CKE3_ DIMMB14

DDR_CS0_DI MMA#13
DDR_CS1_DI MMA#13
DDR_CS2_DI MMB#14
DDR_CS3_DI MMB#14

+1.8V

R575 80.6_0402_1%

R576 80.6_0402_1%

10/6

R579

0_0402_5%

PLT_RST#17,18,20, 22,24,26,30,31,3 2

VGATE15,20, 43

PM_POK20,32

R581 0_0402_5%@

M_ODT013
M_ODT113
M_ODT214
M_ODT314

1 2
1 2

V_DDR_ MCH_REF

PM_BMBUSY#20

1 2

R1027 0_0402_5%

1 2

H_THERMTRIP#4,19

R580 100_0402_1%

MCH_ ICH_SYNC #18

1 2
1 2

R582 0_0402_5%

Layout Note :
V_DDR_MCH_R EF
trace width and
spacing is 20/20.

8/29

V_DDR_ MCH_REF

1

C641

2

0.1U_0402_16 V4Z

Stuff R590 & R591 for A1 Calistoga

C643

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/02/27 2007/02/27

Compal Secret Data

Deciphered Date

2

Title

Size Docume nt Number Re v

Date : Sheet of

Description at page11.

MCH_CLKSEL0

K16

MCH_CLKSEL1

K18

MCH_CLKSEL2

J18

CFG3

F18

CFG4

E15

CFG5

F15

CFG6

E18

CFG7

D19

CFG8

D16

CFG9

G16

CFG10

E16

CFG11

D15

CFG12

G15

CFG13

K15

CFG14

C15

CFG15

H16

CFG16

G18

CFG17

H15

CFG18

J25

CFG19

K27

CFG20

J26

CLK_MCH_3GPLL

AG33

CLK_MCH_3GPLL#

AF33

CLK_MC H_DREFCLK#

A27

CLK_MC H_DREFCLK

A26

MCH_SS CDREFCLK#

C40

MCH_SS CDREFCLK

D41

CLKREQ C#

H32

A3
A39
A4
A40
AW1
AW41
AY1
BA1
BA2
BA3
BA39
BA40
BA41
C1
AY41
B2
B41
C41
D1

T32
R32
F3
F7
AG11
AF11
H7
J19
A41
A34
D28
D27
A35

R585 10K_0402_5%

R586

10K_0402_5%@

12

12

PAD
PAD

PAD

PAD

PAD

PAD
PAD

PAD

+3VS

MCH_CLKSEL0 15
MCH_CLKSEL1 15

MCH_CLKSEL2 15

T1
T2

CFG5 11

T3

CFG7 11

T4

CFG9 11

T5

CFG11 11

CFG12 11

CFG13 11

T6
T7

CFG16 11

T8

CFG18 11

CFG19 11

CFG20 11

CLK_MCH_3GPLL 15

CLK_MCH_3GPLL# 15

CLK_MC H_DREFCLK# 15
CLK_MC H_DREFCLK 15

MCH_SS CDREFCLK# 15
MCH_SS CDREFCLK 15

CLKREQC # 15

7/25

Compal Electronics, Inc.

Calistoga (1/6)

LA-3031P

7 49Tuesd ay, Febru ary 28, 2006

1

0.5

5

D D

4

3

2

1

DDR_A_BS# 013
DDR_A_BS# 113
DDR_A_BS# 213

DDR_A_ DM[0..7]13

DDR_A _DQS[0..7 ]13

C C

DDR_A_ DQS#[0..7 ]13

DDR_A_ MA[0..13]13

B B

DDR_A_ CAS#13
DDR_A_ RAS#13

DDR_A_W E#13

T9 P AD
T11 P AD

DDR_A_BS #0
DDR_A_BS #1
DDR_A_BS #2

DDR_A_DM 0
DDR_A_DM 1
DDR_A_DM 2
DDR_A_DM 3
DDR_A_DM 4
DDR_A_DM 5
DDR_A_DM 6
DDR_A_DM 7

DDR_A_ DQS0
DDR_A_ DQS1
DDR_A_ DQS2
DDR_A_ DQS3
DDR_A_ DQS4
DDR_A_ DQS5
DDR_A_ DQS6
DDR_A_ DQS7

DDR_A_ DQS#0
DDR_A_ DQS#1
DDR_A_ DQS#2
DDR_A_ DQS#3
DDR_A_ DQS#4
DDR_A_ DQS#5
DDR_A_ DQS#6
DDR_A_ DQS#7

DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5

DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11 DDR_B_MA11
DDR_A_MA12
DDR_A_MA13

DDR_A_ CAS#
DDR_A_ RAS#
DDR_A_W E#
SA_RCVE NIN#
SA_RCVENOUT #

U15D

AU12

SA_BS0

AV14

SA_BS1

BA20

SA_BS2

AJ33

SA_DM0

AM35

SA_DM1

AL26

SA_DM2

AN22

SA_DM3

AM14

SA_DM4

AL9

SA_DM5

AR3

SA_DM6

AH4

SA_DM7

AK33

SA_DQS0

AT33

SA_DQS1

AN28

SA_DQS2

AM22

SA_DQS3

AN12

SA_DQS4

AN8

SA_DQS5

AP3

SA_DQS6

AG5

SA_DQS7

AK32

SA_DQS0#

AU33

SA_DQS1#

AN27

SA_DQS2#

AM21

SA_DQS3#

AM12

SA_DQS4#

AL8

SA_DQS5#

AN3

SA_DQS6#

AH5

SA_DQS7#

AY16

SA_MA0

AU14

SA_MA1

AW16

SA_MA2

BA16

SA_MA3

BA17

SA_MA4

AU16

SA_MA5

AV17

SA_MA6

AU17

SA_MA7

AW17

SA_MA8

AT16

SA_MA9

AU13

SA_MA10

AT17

SA_MA11

AV20

SA_MA12

AV12

SA_MA13

AY13

SA_CAS#

AW14

SA_RAS#

AY14

SA_WE#

AK23

SA_RCVENIN#

AK24

SA_RCVENOUT#

QG82945GM QK56 A3 FCBGA 1466

SA_DQ0
SA_DQ1
SA_DQ2
SA_DQ3
SA_DQ4
SA_DQ5
SA_DQ6
SA_DQ7
SA_DQ8

SA_DQ9
SA_DQ10
SA_DQ11
SA_DQ12
SA_DQ13
SA_DQ14
SA_DQ15
SA_DQ16
SA_DQ17
SA_DQ18
SA_DQ19
SA_DQ20
SA_DQ21
SA_DQ22
SA_DQ23
SA_DQ24
SA_DQ25
SA_DQ26
SA_DQ27
SA_DQ28
SA_DQ29
SA_DQ30
SA_DQ31
SA_DQ32
SA_DQ33
SA_DQ34
SA_DQ35
SA_DQ36
SA_DQ37
SA_DQ38
SA_DQ39

DDR SYS MEMORY A

SA_DQ40
SA_DQ41
SA_DQ42
SA_DQ43
SA_DQ44
SA_DQ45
SA_DQ46
SA_DQ47
SA_DQ48
SA_DQ49
SA_DQ50
SA_DQ51
SA_DQ52
SA_DQ53
SA_DQ54
SA_DQ55
SA_DQ56
SA_DQ57
SA_DQ58
SA_DQ59
SA_DQ60
SA_DQ61
SA_DQ62
SA_DQ63

AJ35
AJ34
AM31
AM33
AJ36
AK35
AJ32
AH31
AN35
AP33
AR31
AP31
AN38
AM36
AM34
AN33
AK26
AL27
AM26
AN24
AK28
AL28
AM24
AP26
AP23
AL22
AP21
AN20
AL23
AP24
AP20
AT21
AR12
AR14
AP13
AP12
AT13
AT12
AL14
AL12
AK9
AN7
AK8
AK7
AP9
AN9
AT5
AL5
AY2
AW2
AP1
AN2
AV2
AT3
AN1
AL2
AG7
AF9
AG4
AF6
AG9
AH6
AF4
AF8

DDR_A _D0
DDR_A _D1
DDR_A _D2
DDR_A _D3
DDR_A _D4
DDR_A _D5
DDR_A _D6
DDR_A _D7
DDR_A _D8
DDR_A _D9
DDR_A_ D10
DDR_A_ D11
DDR_A_ D12
DDR_A_ D13
DDR_A_ D14
DDR_A_ D15
DDR_A_ D16
DDR_A_ D17
DDR_A_ D18
DDR_A_ D19
DDR_A_ D20
DDR_A_ D21
DDR_A_ D22
DDR_A_ D23
DDR_A_ D24
DDR_A_ D25
DDR_A_ D26
DDR_A_ D27
DDR_A_ D28
DDR_A_ D29
DDR_A_ D30
DDR_A_ D31
DDR_A_ D32
DDR_A_ D33
DDR_A_ D34
DDR_A_ D35
DDR_A_ D36
DDR_A_ D37
DDR_A_ D38
DDR_A_ D39
DDR_A_ D40
DDR_A_ D41
DDR_A_ D42
DDR_A_ D43
DDR_A_ D44
DDR_A_ D45
DDR_A_ D46
DDR_A_ D47
DDR_A_ D48
DDR_A_ D49
DDR_A_ D50
DDR_A_ D51
DDR_A_ D52
DDR_A_ D53
DDR_A_ D54
DDR_A_ D55
DDR_A_ D56
DDR_A_ D57
DDR_A_ D58
DDR_A_ D59
DDR_A_ D60
DDR_A_ D61
DDR_A_ D62
DDR_A_ D63

DDR_ A_D[0..63 ] 13 DDR_ B_D[0..63 ] 14

DDR_B_BS# 014
DDR_B_BS# 114
DDR_B_BS# 214

DDR_B_ DM[0..7]14

DDR_B _DQS[0..7 ]14

DDR_B _DQS#[0.. 7]14

DDR_B_ MA[0..13]14

DDR_B_ CAS#14
DDR_B_ RAS#14

DDR_B_W E#14

T10 PAD
T12 PAD

DDR_B_BS# 0
DDR_B_BS #1
DDR_B_BS #2

DDR_B_DM 0
DDR_B_DM 1
DDR_B_DM 2
DDR_B_DM 3
DDR_B_DM 4
DDR_B_DM 5
DDR_B_DM 6
DDR_B_DM 7

DDR_B_ DQS0
DDR_B_ DQS1
DDR_B_ DQS2
DDR_B_ DQS3
DDR_B_ DQS4
DDR_B_ DQS5
DDR_B_ DQS6
DDR_B_ DQS7

DDR_B_ DQS#0
DDR_B_ DQS#1
DDR_B_ DQS#2
DDR_B_ DQS#3
DDR_B_ DQS#4
DDR_B_ DQS#5
DDR_B_ DQS#6
DDR_B_ DQS#7

DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6DDR_A_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10

DDR_B_MA12
DDR_B_MA13

DDR_B_ CAS#
DDR_B_ RAS#
DDR_B_W E#
SB_RCVE NIN#
SB_RCVENOUT #

U15E

AT24

SB_BS0

AV23

SB_BS1

AY28

SB_BS2

AK36

SB_DM0

AR38

SB_DM1

AT36

SB_DM2

BA31

SB_DM3

AL17

SB_DM4

AH8

SB_DM5

BA5

SB_DM6

AN4

SB_DM7

AM39

SB_DQS0

AT39

SB_DQS1

AU35

SB_DQS2

AR29

SB_DQS3

AR16

SB_DQS4

AR10

SB_DQS5

AR7

SB_DQS6

AN5

SB_DQS7

AM40

SB_DQS0#

AU39

SB_DQS1#

AT35

SB_DQS2#

AP29

SB_DQS3#

AP16

SB_DQS4#

AT10

SB_DQS5#

AT7

SB_DQS6#

AP5

SB_DQS7#

AY23

SB_MA0

AW24

SB_MA1

AY24

SB_MA2

AR28

SB_MA3

AT27

SB_MA4

AT28

SB_MA5

AU27

SB_MA6

AV28

SB_MA7

AV27

SB_MA8

AW27

SB_MA9

AV24

SB_MA10

BA27

SB_MA11

AY27

SB_MA12

AR23

SB_MA13

AR24

SB_CAS#

AU23

SB_RAS#

AR27

SB_WE#

AK16

SB_RCVENIN#

AK18

SB_RCVENOUT#

QG82945GM QK56 A3 FCBGA 1466

SB_DQ0
SB_DQ1
SB_DQ2
SB_DQ3
SB_DQ4
SB_DQ5
SB_DQ6
SB_DQ7
SB_DQ8

SB_DQ9
SB_DQ10
SB_DQ11
SB_DQ12
SB_DQ13
SB_DQ14
SB_DQ15
SB_DQ16
SB_DQ17
SB_DQ18
SB_DQ19
SB_DQ20
SB_DQ21
SB_DQ22
SB_DQ23
SB_DQ24
SB_DQ25
SB_DQ26
SB_DQ27
SB_DQ28
SB_DQ29
SB_DQ30
SB_DQ31
SB_DQ32
SB_DQ33
SB_DQ34
SB_DQ35
SB_DQ36
SB_DQ37
SB_DQ38
SB_DQ39

DDR SYS MEMORY B

SB_DQ40
SB_DQ41
SB_DQ42
SB_DQ43
SB_DQ44
SB_DQ45
SB_DQ46
SB_DQ47
SB_DQ48
SB_DQ49
SB_DQ50
SB_DQ51
SB_DQ52
SB_DQ53
SB_DQ54
SB_DQ55
SB_DQ56
SB_DQ57
SB_DQ58
SB_DQ59
SB_DQ60
SB_DQ61
SB_DQ62
SB_DQ63

AJ37
AP39
AR41
AJ38
AK38
AN41
AP41
AT40
AV41
AU38
AV38
AP38
AR40
AW38
AY38
BA38
AV36
AR36
AP36
BA36
AU36
AP35
AP34
AY33
BA33
AT31
AU29
AU31
AW31
AV29
AW29
AM19
AL19
AP14
AN14
AN17
AM16
AP15
AL15
AJ11
AH10
AJ9
AN10
AK13
AH11
AK10
AJ8
BA10
AW10
BA4
AW4
AY10
AY9
AW5
AY5
AV4
AR5
AK4
AK3
AT4
AK5
AJ5
AJ3

DDR_B _D1
DDR_B _D2
DDR_B _D3
DDR_B _D4
DDR_B _D5
DDR_B _D6
DDR_B _D7
DDR_B _D8
DDR_B _D9
DDR_B_ D10
DDR_B_ D11
DDR_B_ D12
DDR_B_ D13
DDR_B_ D14
DDR_B_ D15
DDR_B_ D16
DDR_B_ D17
DDR_B_ D18
DDR_B_ D19
DDR_B_ D20
DDR_B_ D21
DDR_B_ D22
DDR_B_ D23
DDR_B_ D24
DDR_B_ D25
DDR_B_ D26
DDR_B_ D27
DDR_B_ D28
DDR_B_ D29
DDR_B_ D30
DDR_B_ D31
DDR_B_ D32
DDR_B_ D33
DDR_B_ D34
DDR_B_ D35
DDR_B_ D36
DDR_B_ D37
DDR_B_ D38
DDR_B_ D39
DDR_B_ D40
DDR_B_ D41
DDR_B_ D42
DDR_B_ D43
DDR_B_ D44
DDR_B_ D45
DDR_B_ D46
DDR_B_ D47
DDR_B_ D48
DDR_B_ D49
DDR_B_ D50
DDR_B_ D51
DDR_B_ D52
DDR_B_ D53
DDR_B_ D54
DDR_B_ D55
DDR_B_ D56
DDR_B_ D57
DDR_B_ D58
DDR_B_ D59
DDR_B_ D60
DDR_B_ D61
DDR_B_ D62
DDR_B_ D63

DDR_B _D0

AK39

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/02/27 2007/02/27

Compal Secret Data

Deciphered Date

2

Title

Size Docume nt Number Re v

Date : Sheet of

Compal Electronics, Inc.

Calistoga (2/6)

LA-3031P

8 49Tuesd ay, Febru ary 28, 2006

1

0.5

5

4

3

2

1

D D

U15C

LIBG

12

12

255_0402_1%

L64

L66

L68

H27

SDVOCTRL_DATA

H28

SDVOCTRL_CLK

B37

LA_DATA0

B34

LA_DATA1

A36

LA_DATA2

C37

LA_DATA#0

B35

LA_DATA#1

A37

LA_DATA#2

F30

LB_DATA0

D29

LB_DATA1

F28

LB_DATA2

G30

LB_DATA#0

D30

LB_DATA#1

F29

LB_DATA#2

A32

LA_CLK

A33

LA_CLK#

E26

LB_CLK

E27

LB_CLK#

D32

LBKLT_CTL

J30

LBKLT_EN

H30

LCTLA_CLK

H29

LCTLB_DATA

G26

LDDC_CLK

G25

LDDC_DATA

F32

LVDD_EN

B38

LIBG

C35

LVBG

C33

LVREFH

C32

LVREFL

A16

TVDAC_A

C18

TVDAC_B

A19

TVDAC_C

J20

TV_IREF

B16

TV_IRTNA

B18

TV_IRTNB

B19

TV_IRTNC

J29

TV_DCONSEL1

K30

TV_DCONSEL0

C26

DDCCLK

C25

DDCDATA

H23

VSYNC

G23

HSYNC

E23

BLUE

D23

BLUE#

C22

GREEN

B22

GREEN#

A21

RED

B21

RED#

J22

CRT_IREF

QG82945GM QK56 A3 FCBGA 1466

TV CRT

D_RE D 16,34

D_GREE N 16,34

D_BLUE 16,34

LVDS

PCI-EXPRESS GRAPHICS

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

SDVO_SDAT17

SDVO_SCLK17

TXA0+17
TXA1+17
TXA2+17

TXA0-17
TXA1-17
TXA2-17

TXB0+17
TXB1+17
TXB2+17

+3VS

12

12

R603

C C

LCD_CL K17

LCD_DAT17

TV-Out Termination

COMPS

LUMA

CRMA

B B

10K_0402_5%

LCD_CL K
LCD_DAT

Place close t o U15

R608

12

R609

75_0402_1%

12

75_0402_1%

CRT Termination/EMI Filter

C_RE D

C_BLU

R611

12

75_0402_1%

5

A A

12

75_0402_1%

R612

HLC0603CSCC 39NJT_0603

HLC0603CSCC 39NJT_0603

HLC0603CSCC 39NJT_0603

12

R613

75_0402_1%

12

R610

75_0402_1%

L63

1 2

L65

1 2

L67

1 2

R604

10K_0402_5%

1

2

18P_0402_50V8J

C655

TXB0-17
TXB1-17
TXB2-17

TXACLK+17
TXACLK-17

TXBCLK+17

TXBCLK-17

ENAVD D17

DDCC LK16

DDCDAT A16

VSYNC16
HSYNC16

Place close t o U15

C_RED_ L

C_GRN _LC_G RN

C_BLU_L

1

C656

2

18P_0402_50V8J

TXB0+
TXB1+
TXB2+

TXB0­TXB1­TXB2-

TXBCLK+

TXBCLK-

BKLT_CTL
ENABLT

ENAV DD

R605 1.5K_0402_1%

COMPS
LUMA
CRMA

12

R606

4.99K_0603_1%

C_BLU

C_G RN

C_RE D

R607

1 2

HLC0603CSCC R11JT_0603

1 2

HLC0603CSCC R11JT_0603

1 2

HLC0603CSCC R11JT_0603

1

C657

18P_0402_50V8J

2

4

PEG COM P t race wid th
and s paci ng i s 18/ 25 mi ls.

D40

EXP_COMPI

EXP_RXN0
EXP_RXN1
EXP_RXN2
EXP_RXN3
EXP_RXN4
EXP_RXN5
EXP_RXN6
EXP_RXN7
EXP_RXN8

EXP_RXN9
EXP_RXN10
EXP_RXN11
EXP_RXN12
EXP_RXN13
EXP_RXN14
EXP_RXN15

EXP_RXP0

EXP_RXP1

EXP_RXP2

EXP_RXP3

EXP_RXP4

EXP_RXP5

EXP_RXP6

EXP_RXP7

EXP_RXP8

EXP_RXP9
EXP_RXP10
EXP_RXP11
EXP_RXP12
EXP_RXP13
EXP_RXP14
EXP_RXP15

EXP_TXN0

EXP_TXN1

EXP_TXN2

EXP_TXN3

EXP_TXN4

EXP_TXN5

EXP_TXN6

EXP_TXN7

EXP_TXN8

EXP_TXN9
EXP_TXN10
EXP_TXN11
EXP_TXN12
EXP_TXN13
EXP_TXN14
EXP_TXN15

EXP_TXP0

EXP_TXP1

EXP_TXP2

EXP_TXP3

EXP_TXP4

EXP_TXP5

EXP_TXP6

EXP_TXP7

EXP_TXP8

EXP_TXP9

EXP_TXP10
EXP_TXP11
EXP_TXP12
EXP_TXP13
EXP_TXP14
EXP_TXP15

D38

F34
G38
H34
J38
L34
M38
N34
P38
R34
T38
V34
W38
Y34
AA38
AB34
AC38

D34
F38
G34
H38
J34
L38
M34
N38
P34
R38
T34
V38
W34
Y38
AA34
AB38

F36
G40
H36
J40
L36
M40
N36
P40
R36
T40
V36
W40
Y36
AA40
AB36
AC40

D36
F40
G36
H40
J36
L40
M36
N40
P36
R40
T36
V40
W36
Y40
AA36
AB40

3

EXP_COMPO

+1.5VS_PCIE

PEGCOMP

1 2

R602 24.9_0402_1%

SDVOB_INT- 17

7/14

SDVOB_INT+ 17

PEG_TXN0
PEG_TXN1
PEG_TXN2
PEG_TXN3

PEG_TXP0
PEG_TXP1
PEG_TXP2
PEG_TXP3

C647 0.1U_0402_16 V4Z

1 2

C648 0.1U_0402_16 V4Z

1 2

C649 0.1U_0402_16 V4Z
C650 0.1U_0402_16 V4Z

C651 0.1U_0402_16 V4Z
C652 0.1U_0402_16 V4Z
C653 0.1U_0402_16 V4Z
C654 0.1U_0402_16 V4Z

2006/02/27 2007/02/27

1 2

1 2

1 2

1 2

1 2

1 2

C14

82P_0402_50V8J

Compal Secret Data

Deciphered Date

LUMA

CRMA

COMPS

1

2

82P_0402_50V8J

1

C30

2

SDVOB_R- 17
SDVOB_G- 17
SDVOB_B- 1 7
SDVOB_CLK- 17

SDVOB_R+ 17
SDVOB_G+ 17
SDVOB_B+ 17
SDVOB_CLK+ 17

LID_SW #20,33

L3

1 2

FCM1608C-121T_0603

L5

1 2

FCM1608C-121T_0603

L4

1 2

FCM1608C-121T_0603

1

C6

82P_0402_50V8J

2

Please close to U15

2

+5VS+3VS

12

G

2

BKLT_CTL

R509

2.2K_0402_5%

LID_SW #

ENABLT

100K_0402_5%

82P_0402_50V8J

S

12

BSS138_SOT23

+3VS

5

U35

1

P

IN1

2

IN2

G

R501

3

1 2

SN74AHC 1G08DCKR_SC70-5

1

C318

C317

2

82P_0402_50V8J

Title

Size Docume nt Number Re v

Date : Sheet of

R510

Q56

2.2K_0402_5%

13

D

Q53
DTA114YKA_S C59

+5VS

47K

10K

2

13

4

O

R360

1

2

2

G

100K_0402_5%

1 2

LUMA_CL

CRMA_CL

COMPS_CL

1

C316

82P_0402_50V8J

2

D

S

Compal Electronics, Inc.

Calistoga (3/6)

LA-3031P

1

BKLT_CTL_C 17

13

Q36

BSS138_SOT23

LUMA_CL 16,34

CRMA_CL 16,34

COMPS_CL 1 6,34

9 49Tuesd ay, Febru ary 28, 2006

+5VS_INV

0.5

5

D D

C669

Place o n edge

C C

1

C679

2

C678 4. 7U_0805_10V4Z

+VCCP

1

+

2

220U_D2_2VK_ R9

1

2

2.2U_0805_16V 4Z

Place i n cavity.

MCH_A6

1

C686

2

B B

1

C693

2

0.22U_0603_10V7K

Place o n edge

A A

0.47U_0603_10V7K

MCH_D2

1

C695

MCH_AB1

2

1

0.22U_0603_10V7K

C696

2

0.47U_0603_10V7K

+1.5VS

U15H

AC14

VTT0

AB14

VTT1

W14

VTT2

V14

VTT3

T14

VTT4

R14

VTT5

P14

VTT6

N14

VTT7

M14

VTT8

L14

VTT9

AD13

VTT10

AC13

VTT11

AB13

VTT12

AA13

VTT13

Y13

VTT14

W13

VTT15

V13

VTT16

U13

VTT17

T13

VTT18

R13

VTT19

N13

VTT20

M13

VTT21

L13

VTT22

AB12

VTT23

AA12

VTT24

Y12

VTT25

W12

VTT26

V12

VTT27

U12

VTT28

T12

VTT29

R12

VTT30

P12

VTT31

N12

VTT32

P O W E R

VTT33
VTT34
VTT35
VTT36
VTT37
VTT38
VTT39
VTT40
VTT41
VTT42
VTT43
VTT44
VTT45
VTT46
VTT47
VTT48
VTT49
VTT50
VTT51
VTT52
VTT53
VTT54
VTT55
VTT56
VTT57
VTT58
VTT59
VTT60
VTT61
VTT62
VTT63
VTT64
VTT65
VTT66
VTT67
VTT68
VTT69
VTT70
VTT71
VTT72
VTT73
VTT74
VTT75
VTT76

VCCAUX32
VCCAUX33
VCCAUX34
VCCAUX35
VCCAUX36
VCCAUX37
VCCAUX38
VCCAUX39
VCCAUX40

QG82945GM QK5 6 A3 FCBGA 1466

AG14
AF14
AE14

AF13
AE13
AF12
AE12
AD12

M12

L12
R11
P11
N11
M11
R10
P10
N10
M10

P9
N9
M9
R8
P8
N8
M8
P7
N7
M7
R6
P6
M6
A6
R5
P5
N5
M5
P4
N4
M4
R3
P3
N3
M3
R2
P2
M2
D2

AB1

R1
P1
N1
M1

Y14

4

VCCA_CRTDAC0
VCCA_CRTDAC1
VSSA_CRTDAC2

VCCA_TVDACA0
VCCA_TVDACA1
VCCA_TVDACB0
VCCA_TVDACB1
VCCA_TVDACC0
VCCA_TVDACC1

VCCDQ_TVDAC

VCC_SYNC

VCCTX_LVDS0
VCCTX_LVDS1
VCCTX_LVDS2

VCC3G0
VCC3G1
VCC3G2
VCC3G3
VCC3G4
VCC3G5
VCC3G6

VCCA_3GPLL

VCCA_3GBG
VSSA_3GBG

VCCA_DPLLA
VCCA_DPLLB

VCCA_HPLL

VCCA_LVDS
VSSA_LVDS

VCCA_MPLL

VCCA_TVBG

VSSA_TVBG

VCCD_HMPLL0
VCCD_HMPLL1

VCCD_LVDS0
VCCD_LVDS1
VCCD_LVDS2

VCCD_TVDAC

VCCHV0
VCCHV1
VCCHV2

VCCAUX0
VCCAUX1
VCCAUX2
VCCAUX3
VCCAUX4
VCCAUX5
VCCAUX6
VCCAUX7
VCCAUX8

VCCAUX9
VCCAUX10
VCCAUX11
VCCAUX12
VCCAUX13
VCCAUX14
VCCAUX15
VCCAUX16
VCCAUX17
VCCAUX18
VCCAUX19
VCCAUX20
VCCAUX21
VCCAUX22
VCCAUX23
VCCAUX24
VCCAUX25
VCCAUX26
VCCAUX27
VCCAUX28
VCCAUX29
VCCAUX30
VCCAUX31

H22

B30
C30
A30

AB41
AJ41
L41
N41
R41
V41
Y41

AC33
G41
H41

E21
F21
G21

B26
C39
AF1

A38
B39

AF2

H20
G20

E19
F19
C20
D20
E20
F20

AH1
AH2

A28
B28
C28

D21
H19

A23
B23
B25

AK31
AF31
AE31
AC31
AL30
AK30
AJ30
AH30
AG30
AF30
AE30
AD30
AC30
AG29
AF29
AE29
AD29
AC29
AG28
AF28
AE28
AH22
AJ21
AH21
AJ20
AH20
AH19
P19
P16
AH15
P15
AH14

+2.5VS

1 2

C659

0.1U_0402_16 V4Z

+2.5VS

W=40 mils

+1.5VS_3GPLL
+2.5VS

MCH_ CRTDAC

+1.5VS_DPLLA
+1.5VS_DPLLB
+1.5VS_HPLL

+1.5VS_MPLL

+3VS_TVBG

+3VS_TVDACA

+3VS_TVDACB

+3VS_TVDACC

+1.5VS

+1.5VS_TVDAC

+1.5VS

1

C694

2

3

+2.5VS

1

C658

2

0.1U_0402_16V 4Z

close pin G41

+1.5VS_PCIE

1

C664

220U_D2_2V K_R9

1

C912

2

0.1U_0402_16V 4Z

1

2

C687

0.1U_0402_16V 4Z

0.1U_0402_16V 4Z

+

2

10U_0805_6.3V6M

1

2

+2.5VS

1

2

+3VS

1

C688

10U_0805_6.3V6M

2

1

2

C676

2200P_0402_50V7K

C899

2200P_0402_50V7K

0_0805_5%

C666

C667

1

10U_0805_6.3V6M

2

1

1

C677

C927

2

2

0.1U_0402_16V 4Z

R940

0_0805_5%

1

C900

2

0.1U_0402_16V 4Z

Close to U15.H20

R614

12

+1.5VS

1 2

7/19

47U_1210_6.3V 4Z

@

12

R960

+3VS+3VS_TVBG

0_0603_5%

+2.5VS

C680

1

2

0.1U_0402_16V 4Z

10U_0805_6.3V6M

1

2

1

C681

2

+1.5VS_MPLL

1

C670

2

2200P_0402_50V7K

7/19

R618

1 2

0.5_0805_1%

45mA Max. 45mA Max.

1

C689

2

0.1U_0402_16V 4Z

+VCCP

D57

2 1

CH751H-4 0_SC76

+1.5VS +3VS

D58

2 1

CH751H-4 0_SC76

R961

10_0402_5%

R962

10_0402_5%

12

2

+1.5VS_DPLLA +1.5VS_DPLLB

1

C662

2

0.1U_0402_16 V4Z

R615

0_0805_5%

1

C926

C671

2

0.1U_0402_16V 4Z

47U_1210_6.3 V4Z

@

Close to U15.E20

CHB1608U301_0 603

1

+

C910

2

330U_D2E_2.5VM

12

L69

12

1

2

0.1U_0402_16 V4Z

R616

12

0_0805_5%

1

1

1

2

2

2

47U_1210_6.3V 4Z@

0.1U_0402_16V 4Z

C673

C672

2200P_0402_50V7K

C1033

9/27

Close to U15.C20 Close to U15.E19

PCI-E/MEM/PSB PLL decoupling

R621

0_0805_5%

1

C690

10U_0805_6.3V6M

2

+2.5VS

12

R619

0_0805_5%

12

+1.5VS+1.5VS_3GPLL

12

+1.5VS_TVDAC +1.5VS

2200P_0402_50V7K

1

C683

2

+1.5VS_HPLL

1

C691

2

0.1U_0402_16 V4Z

0.1U_0402_16V 4Z

0_0805_5%

1

C684

2

R622

0_0805_5%

1

C692

10U_0805_6.3V6M

2

R620

CHB1608U301_0 603

1

+

C663

2

C911

1

2

12

12

+1.5VS+1.5VS

1

L70

12

+1.5VS+1.5VS

330U_D2E_2.5VM

+3VS+3VS_TVDACA+3VS+3VS_TVDACB+3VS+3VS_TVDACC

R617

12

0_0805_5%

1

2

C1034

9/27

47U_1210_6.3V 4Z@

1

2

2200P_0402_50V7K

0.1U_0402_16V 4Z

C675

C674

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/02/27 2007/02/27

Compal Secret Data

Deciphered Date

Title

Size Document Number Re v

2

Date: Sheet of

Compal Electronics, Inc.

Calistoga (4/6)

LA-3031P

10 49Tuesday , February 28, 2006

1

0.5

5

4

3

2

1

Strap Pin Table

CFG[3:17] h ave internal pull up

+VCCP

D D

1

1

C699

2

0.22U_0603_10V7K

10U_0805_6.3V6M

1

C707

C706

2

10U_0805_6.3V6M

C C

B B

C700

C709

2

0.22U_0603_10V7K

1

2

1

+

2

220U_D2_2VK _R9

1

C701

2

0.22U_0603_10V7K

1

C708

2

1U_0603_10V4Z

+VCCP

U15F

AD27

VCC_NCTF0

AC27

VCC_NCTF1

AB27

VCC_NCTF2

AA27

VCC_NCTF3

Y27

VCC_NCTF4

W27

VCC_NCTF5

V27

VCC_NCTF6

U27

VCC_NCTF7

T27

VCC_NCTF8

R27

VCC_NCTF9

AD26

VCC_NCTF10

AC26

VCC_NCTF11

AB26

VCC_NCTF12

AA26

VCC_NCTF13

Y26

VCC_NCTF14

W26

VCC_NCTF15

V26

VCC_NCTF16

U26

VCC_NCTF17

T26

VCC_NCTF18

R26

VCC_NCTF19

AD25

VCC_NCTF20

AC25

VCC_NCTF21

AB25

VCC_NCTF22

AA25

VCC_NCTF23

Y25

VCC_NCTF24

W25

VCC_NCTF25

V25

VCC_NCTF26

U25

VCC_NCTF27

T25

VCC_NCTF28

R25

VCC_NCTF29

AD24

VCC_NCTF30

AC24

VCC_NCTF31

AB24

VCC_NCTF32

AA24

VCC_NCTF33

Y24

VCC_NCTF34

W24

VCC_NCTF35

V24

VCC_NCTF36

U24

VCC_NCTF37

T24

VCC_NCTF38

R24

VCC_NCTF39

AD23

VCC_NCTF40

V23

VCC_NCTF41

U23

VCC_NCTF42

T23

VCC_NCTF43

R23

VCC_NCTF44

AD22

VCC_NCTF45

V22

VCC_NCTF46

U22

VCC_NCTF47

T22

VCC_NCTF48

R22

VCC_NCTF49

AD21

VCC_NCTF50

V21

VCC_NCTF51

U21

VCC_NCTF52

T21

VCC_NCTF53

R21

VCC_NCTF54

AD20

VCC_NCTF55

V20

VCC_NCTF56

U20

VCC_NCTF57

T20

VCC_NCTF58

R20

VCC_NCTF59

AD19

VCC_NCTF60

V19

VCC_NCTF61

U19

VCC_NCTF62

T19

VCC_NCTF63

AD18

VCC_NCTF64

AC18

VCC_NCTF65

AB18

VCC_NCTF66

AA18

VCC_NCTF67

Y18

VCC_NCTF68

W18

VCC_NCTF69

V18

VCC_NCTF70

U18

VCC_NCTF71

T18

VCC_NCTF72

M19

VCC100

L19

VCC101

N18

VCC102

M18

VCC103

L18

VCC104

P17

VCC105

N17

VCC106

M17

VCC107

N16

VCC108

M16

VCC109

L16

VCC110

QG82945GM QK56 A3 FCBGA 1466

VCCAUX_NCTF0
VCCAUX_NCTF1
VCCAUX_NCTF2
VCCAUX_NCTF3
VCCAUX_NCTF4
VCCAUX_NCTF5
VCCAUX_NCTF6
VCCAUX_NCTF7
VCCAUX_NCTF8

VCCAUX_NCTF9
VCCAUX_NCTF10
VCCAUX_NCTF11
VCCAUX_NCTF12
VCCAUX_NCTF13
VCCAUX_NCTF14
VCCAUX_NCTF15
VCCAUX_NCTF16
VCCAUX_NCTF17
VCCAUX_NCTF18
VCCAUX_NCTF19
VCCAUX_NCTF20
VCCAUX_NCTF21
VCCAUX_NCTF22
VCCAUX_NCTF23
VCCAUX_NCTF24
VCCAUX_NCTF25
VCCAUX_NCTF26
VCCAUX_NCTF27
VCCAUX_NCTF28
VCCAUX_NCTF29
VCCAUX_NCTF30
VCCAUX_NCTF31
VCCAUX_NCTF32
VCCAUX_NCTF33
VCCAUX_NCTF34
VCCAUX_NCTF35
VCCAUX_NCTF36

P O W E R

VCCAUX_NCTF37
VCCAUX_NCTF38
VCCAUX_NCTF39
VCCAUX_NCTF40
VCCAUX_NCTF41
VCCAUX_NCTF42
VCCAUX_NCTF43
VCCAUX_NCTF44
VCCAUX_NCTF45
VCCAUX_NCTF46
VCCAUX_NCTF47
VCCAUX_NCTF48
VCCAUX_NCTF49
VCCAUX_NCTF50
VCCAUX_NCTF51
VCCAUX_NCTF52
VCCAUX_NCTF53
VCCAUX_NCTF54
VCCAUX_NCTF55
VCCAUX_NCTF56
VCCAUX_NCTF57

VSS_NCTF0
VSS_NCTF1
VSS_NCTF2
VSS_NCTF3
VSS_NCTF4
VSS_NCTF5
VSS_NCTF6
VSS_NCTF7
VSS_NCTF8

VSS_NCTF9
VSS_NCTF10
VSS_NCTF11
VSS_NCTF12

VCC_SM100

VCC_SM101

VCC_SM102

VCC_SM103

VCC_SM104

VCC_SM105

VCC_SM106

VCC_SM107

AG27
AF27
AG26
AF26
AG25
AF25
AG24
AF24
AG23
AF23
AG22
AF22
AG21
AF21
AG20
AF20
AG19
AF19
R19
AG18
AF18
R18
AG17
AF17
AE17
AD17
AB17
AA17
W17
V17
T17
R17
AG16
AF16
AE16
AD16
AC16
AB16
AA16
Y16
W16
V16
U16
T16
R16
AG15
AF15
AE15
AD15
AC15
AB15
AA15
Y15
W15
V15
U15
T15
R15

AE27
AE26
AE25
AE24
AE23
AE22
AE21
AE20
AE19
AE18
AC17
Y17
U17

AR6
AP6
AN6
AL6
AK6
AJ6
AV1
AJ1

+1.5VS

VCCSM_LF2
VCCSM_LF1

+1.8V

1

1

C717

C718

2

2

0.47U_0603_10V7K

0.47U_0603_10V7K

Place near pin AV1 & AJ1

A A

+VCCP

U15G

AA33

VCC0

W33

VCC1

P33

VCC2

N33

VCC3

L33

VCC4

J33

VCC5

AA32

VCC6

Y32

VCC7

W32

VCC8

V32

VCC9

P32

VCC10

N32

VCC11

M32

VCC12

L32

VCC13

J32

VCC14

AA31

VCC15

W31

VCC16

V31

VCC17

T31

VCC18

R31

VCC19

P31

VCC20

N31

VCC21

M31

VCC22

AA30

VCC23

Y30

VCC24

W30

VCC25

V30

VCC26

U30

VCC27

T30

VCC28

R30

VCC29

P30

VCC30

N30

VCC31

M30

VCC32

AA29

W29

AB28
AA28

AB23
AA23

AC22
AB22

W22

AC21
AA21

W21

AC20
AB20

W20

AB19
AA19

L30

Y29

V29
U29
R29

P29
M29

L29

Y28

V28
U28

T28
R28

P28
N28
M28

L28

P27
N27
M27

L27

P26
N26

L26
N25
M25

L25

P24
N24
M24

Y23

P23
N23
M23

L23

Y22

P22
N22
M22

L22

N21
M21

L21

Y20

P20
N20
M20

L20

Y19
N19

P O W E R

VCC33
VCC34
VCC35
VCC36
VCC37
VCC38
VCC39
VCC40
VCC41
VCC42
VCC43
VCC44
VCC45
VCC46
VCC47
VCC48
VCC49
VCC50
VCC51
VCC52
VCC53
VCC54
VCC55
VCC56
VCC57
VCC58
VCC59
VCC60
VCC61
VCC62
VCC63
VCC64
VCC65
VCC66
VCC67
VCC68
VCC69
VCC70
VCC71
VCC72
VCC73
VCC74
VCC75
VCC76
VCC77
VCC78
VCC79
VCC80
VCC81
VCC82
VCC83
VCC84
VCC85
VCC86
VCC87
VCC88
VCC89
VCC90
VCC91
VCC92
VCC93
VCC94
VCC95
VCC96
VCC97
VCC98
VCC99

QG82945GM QK56 A3 FCBGA 1466

VCC_SM0
VCC_SM1
VCC_SM2
VCC_SM3
VCC_SM4
VCC_SM5
VCC_SM6
VCC_SM7
VCC_SM8

VCC_SM9
VCC_SM10
VCC_SM11
VCC_SM12
VCC_SM13
VCC_SM14
VCC_SM15
VCC_SM16
VCC_SM17
VCC_SM18
VCC_SM19
VCC_SM20
VCC_SM21
VCC_SM22
VCC_SM23
VCC_SM24
VCC_SM25
VCC_SM26
VCC_SM27
VCC_SM28
VCC_SM29
VCC_SM30
VCC_SM31
VCC_SM32
VCC_SM33
VCC_SM34
VCC_SM35
VCC_SM36
VCC_SM37
VCC_SM38
VCC_SM39
VCC_SM40
VCC_SM41
VCC_SM42
VCC_SM43
VCC_SM44
VCC_SM45
VCC_SM46
VCC_SM47
VCC_SM48
VCC_SM49
VCC_SM50
VCC_SM51
VCC_SM52
VCC_SM53
VCC_SM54
VCC_SM55
VCC_SM56
VCC_SM57
VCC_SM58
VCC_SM59
VCC_SM60
VCC_SM61
VCC_SM62
VCC_SM63
VCC_SM64
VCC_SM65
VCC_SM66
VCC_SM67
VCC_SM68
VCC_SM69
VCC_SM70
VCC_SM71
VCC_SM72
VCC_SM73
VCC_SM74
VCC_SM75
VCC_SM76
VCC_SM77
VCC_SM78
VCC_SM79
VCC_SM80
VCC_SM81
VCC_SM82
VCC_SM83
VCC_SM84
VCC_SM85
VCC_SM86
VCC_SM87
VCC_SM88
VCC_SM89
VCC_SM90
VCC_SM91
VCC_SM92
VCC_SM93
VCC_SM94
VCC_SM95
VCC_SM96
VCC_SM97
VCC_SM98
VCC_SM99

AU41
AT41
AM41
AU40
BA34
AY34
AW34
AV34
AU34
AT34
AR34
BA30
AY30
AW30
AV30
AU30
AT30
AR30
AP30
AN30
AM30
AM29
AL29
AK29
AJ29
AH29
AJ28
AH28
AJ27
AH27
BA26
AY26
AW26
AV26
AU26
AT26
AR26
AJ26
AH26
AJ25
AH25
AJ24
AH24
BA23
AJ23
BA22
AY22
AW22
AV22
AU22
AT22
AR22
AP22
AK22
AJ22
AK21
AK20
BA19
AY19
AW19
AV19
AU19
AT19
AR19
AP19
AK19
AJ19
AJ18
AJ17
AH17
AJ16
AH16
BA15
AY15
AW15
AV15
AU15
AT15
AR15
AJ15
AJ14
AJ13
AH13
AK12
AJ12
AH12
AG12
AK11
BA8
AY8
AW8
AV8
AT8
AR8
AP8
BA6
AY6
AW6
AV6
AT6

+1.8V

VCCSM_LF4
VCCSM_LF5

C697

0.47U_0603_10V7K

Place near p in AT41 & AM41

C702

C711

0.47U_0603_10V7K

Place near pin BA23

C713

10U_0805_6.3V6M

C716

0.47U_0603_10V7K

Place near pin BA15

CFG[2:0]

1

1

C698

2

2

0.47U_0603_10V7K

CFG5

CFG7

CFG9

CFG11

CFG[13:12]

+1.8V

CFG16

1

2

0.1U_0402_16 V4Z

1

1

C703

2

0.1U_0402_16 V4Z

1

C704

C705

2

2

0.1U_0402_16 V4Z

0.1U_0402_16 V4Z

CFG18

CFG19

SDVO_CTRLDATA

Page 17

CFG20

(PCIE/SDVO select)

1

2

1

1

C714

2

2

10U_0805_6.3V6M

1

2

CFG[19:18] have interna l pull down

011 = 667MT/s FSB
001 = 533MT/s FSB

0 = DMI x 2
1 = DMI x 4

0 = Reserved
1 = Mobile Yonah CPU

0 = Lane Rev ersal Enable
1 = Normal Operation

0 = Calistoga

(According to Intel Napa Schematic Checklist & CRB
Rev1.301 do cument 2.2Kohm pull-down r esistor request)

1 = Reserved

00 = Reserved
01 = XOR Mode Enabled
10 = All Z Mode Enabled
11 = Normal Operation

0 = Dynamic ODT Disabled
1 = Dynamic ODT Enabled (Default)

0 = 1.05V
1 = 1.5V

0 = Normal Operation
1 = DMI Lane Reversal Enable

0 = No SDVO Device Present

(Default)

(Default)

*

*

(Default)

*

(Default)

*

(Default)

*

*

1 = SDVO Device Present

0 = Only PCIE or SDVO is
operational.
1 = PCIE/SDV O are operating
simu.

CFG57

CFG77

CFG97

CFG117

CFG127

CFG137

CFG167

CFG187
CFG197
CFG207

R623 2.2K_0402_5%@

R624 2.2K_0402_5%@

R625 2.2K_0402_5%@

R626 2.2K_0402_5%@

R627 2.2K_0402_5%@

R628 2.2K_0402_5%@

R629 2.2K_0402_5%@

R630 1K_0402_5%@
R631 1K_0402_5%@
R632 1K_0402_5%@

*

1 2

1 2

1 2

8/1

1 2

1 2

1 2

1 2

1 2
1 2
1 2

(Default)

*

(Default)

*

(Default)

*

+3VS

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/02/27 2007/02/27

Compal Secret Data

Deciphered Date

Title

Size Docume nt Number Re v

2

Date : Sheet of

Compal Electronics, Inc.

Calistoga (5/6)

LA-3031P

11 49Tuesd ay, Febru ary 28, 2006

1

0.5

5

4

3

2

1

U15I

AC41

VSS0

AA41

VSS1

W41

VSS2

T41

VSS3

P41

D D

C C

B B

A A

VSS4

M41

VSS5

J41

VSS6

F41

VSS7

AV40

VSS8

AP40

VSS9

AN40

VSS10

AK40

VSS11

AJ40

VSS12

AH40

VSS13

AG40

VSS14

AF40

VSS15

AE40

VSS16

B40

VSS17

AY39

VSS18

AW39

VSS19

AV39

VSS20

AR39

VSS21

AN39

VSS22

AJ39

VSS23

AC39

VSS24

AB39

VSS25

AA39

VSS26

Y39

VSS27

W39

VSS28

V39

VSS29

T39

VSS30

R39

VSS31

P39

VSS32

N39

VSS33

M39

VSS34

P O W E R

VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65
VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77
VSS78
VSS79
VSS80
VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS97
VSS98
VSS99

QG82945GM QK56 A3 FCBGA 1466

AT38

AM38

AH38
AG38
AF38
AE38

AK37
AH37
AB37
AA37

W37

M37

AY36

AW36

AN36
AH36
AG36
AF36
AE36
AC36

BA35
AV35
AR35
AH35
AB35
AA35

W35

M35

AN34
AK34
AG34
AF34

L39
J39
H39
G39
F39
D39

C38

Y37

V37
T37
R37
P37
N37

L37
J37
H37
G37
F37
D37

C36
B36

Y35

V35
T35
R35
P35
N35

L35
J35
H35
G35
F35
D35

VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS140
VSS141
VSS142
VSS143
VSS144
VSS145
VSS146
VSS147
VSS148
VSS149
VSS150
VSS151
VSS152
VSS153
VSS154
VSS155
VSS156
VSS157
VSS158
VSS159
VSS160
VSS161
VSS162
VSS163
VSS164
VSS165
VSS166
VSS167
VSS168
VSS169
VSS170
VSS171
VSS172
VSS173
VSS174
VSS175
VSS176
VSS177
VSS178
VSS179
VSS180
VSS181
VSS182
VSS183
VSS184
VSS185
VSS186
VSS187
VSS188
VSS189
VSS190
VSS191
VSS192
VSS193
VSS194
VSS195
VSS196
VSS197
VSS198
VSS199

AE34
AC34
C34
AW33
AV33
AR33
AE33
AB33
Y33
V33
T33
R33
M33
H33
G33
F33
D33
B33
AH32
AG32
AF32
AE32
AC32
AB32
G32
B32
AY31
AV31
AN31
AJ31
AG31
AB31
Y31
AB30
E30
AT29
AN29
AB29
T29
N29
K29
G29
E29
C29
B29
A29
BA28
AW28
AU28
AP28
AM28
AD28
AC28
W28
J28
E28
AP27
AM27
AK27
J27
G27
F27
C27
B27
AN26
M26
K26
F26
D26
AK25
P25
K25
H25
E25
D25
A25
BA24
AU24
AL24
AW23
AT23
AN23
AM23
AH23
AC23
W23
K23
J23
F23
C23
AA22
K22
G22
F22
E22
D22
A22
BA21
AV21
AR21

U15J

AN21

VSS200

AL21

VSS201

AB21

VSS202

Y21

VSS203

P21

VSS204

K21

VSS205

J21

VSS206

H21

VSS207

C21

VSS208

AW20

VSS209

AR20

VSS210

AM20

VSS211

AA20

VSS212

K20

VSS213

B20

VSS214

A20

VSS215

AN19

VSS216

AC19

VSS217

W19

VSS218

K19

VSS219

G19

VSS220

C19

VSS221

AH18

VSS222

P18

VSS223

H18

VSS224

D18

VSS225

A18

VSS226

AY17

VSS227

AR17

VSS228

AP17

VSS229

AM17

AK17
AV16
AN16

AL16

AN15

AM15

AK15

BA14
AT14
AK14
AD14
AA14

AV13
AR13
AN13

AM13

AL13

AG13

AY12
AC12

AD11
AA11

AV10
AP10

AL10
AJ10

J16
F16
C16

N15

M15

L15
B15
A15

U14
K14
H14
E14

P13
F13
D13
B13

K12
H12
E12

Y11

J11
D11
B11

P O W E R

VSS230
VSS231
VSS232
VSS233
VSS234
VSS235
VSS236
VSS237
VSS238
VSS239
VSS240
VSS241
VSS242
VSS243
VSS244
VSS245
VSS246
VSS247
VSS248
VSS249
VSS250
VSS251
VSS252
VSS253
VSS254
VSS255
VSS256
VSS257
VSS258
VSS259
VSS260
VSS261
VSS262
VSS265
VSS264
VSS263
VSS266
VSS267
VSS268
VSS269
VSS270
VSS271
VSS272
VSS273
VSS274
VSS275
VSS276
VSS277
VSS278
VSS279

QG82945GM QK56 A3 FCBGA 1466

VSS280
VSS281
VSS282
VSS283
VSS284
VSS285
VSS286
VSS287
VSS288
VSS289
VSS290
VSS292
VSS291
VSS293
VSS294
VSS295
VSS296
VSS297
VSS298
VSS299
VSS300
VSS301
VSS302
VSS303
VSS304
VSS305
VSS306
VSS307
VSS308
VSS309
VSS310
VSS311
VSS312
VSS313
VSS314
VSS315
VSS316
VSS317
VSS318
VSS319
VSS320
VSS321
VSS322
VSS323
VSS324
VSS325
VSS326
VSS327
VSS328
VSS329
VSS330
VSS331
VSS332
VSS333
VSS334
VSS335
VSS336
VSS337
VSS338
VSS339
VSS340
VSS341
VSS342
VSS343
VSS344
VSS345
VSS346
VSS347
VSS348
VSS349
VSS350
VSS351
VSS352
VSS353
VSS354
VSS355
VSS356
VSS357
VSS358
VSS359
VSS360

AG10
AC10
W10
U10
BA9
AW9
AR9
AH9
AB9
Y9
R9
G9
E9
A9
AG8
AD8
AA8
U8
K8
C8
BA7
AV7
AP7
AL7
AJ7
AH7
AF7
AC7
R7
G7
D7
AG6
AD6
AB6
Y6
U6
N6
K6
H6
B6
AV5
AF5
AD5
AY4
AR4
AP4
AL4
AJ4
Y4
U4
R4
J4
F4
C4
AY3
AW3
AV3
AL3
AH3
AG3
AF3
AD3
AC3
AA3
G3
AT2
AR2
AP2
AK2
AJ2
AD2
AB2
Y2
U2
T2
N2
J2
H2
F2
C2
AL1

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/02/27 2007/02/27

Compal Secret Data

Deciphered Date

Title

Size Docume nt Number Re v

2

Date : Sheet of

Compal Electronics, Inc.

Calistoga (6/6)

LA-3031P

12 49Tuesd ay, Febru ary 28, 2006

1

0.5

5

4

3

2

1

DDR_A_ DQS#[0..7 ]8

DDR_ A_D[0..63 ]8

DDR_A_ DM[0..7]8

DDR_A _DQS[0..7 ]8

DDR_A_ MA[0..13]8

D D

+1.8V

2.2U_0805_16 V4Z

C458

1

2

0.1U_0402_16 V4Z

1

2

C C

Layout Note:
Place one cap clo se to every 2 pullup
resistors terminated to +0.9V_DDR_VTT

+0.9VS

0.1U_0402_16 V4Z

0.1U_0402_16 V4Z

0.1U_0402_16 V4Z

1

1

2

2

C239

B B

A A

C229

DDR_A_MA5
DDR_A_MA8

DDR_A_MA1
DDR_A_MA3

DDR_A_ RAS#
DDR_CS0_D IMMA#

DDR_A_BS #0
DDR_A_MA10

DDR_A_ CAS#
DDR_A_W E#

DDR_CS1_D IMMA#
M_ODT1

1

2

C250

RP27

RP29

RP32

RP31

RP33

5

0.1U_0402_16 V4Z

0.1U_0402_16 V4Z

1

2

C257

1 4
2 3

56_0404_4P2R_5%

1 4
2 3

56_0404_4P2R_5%

1 4
2 3

56_0404_4P2R_5%

1 4
2 3

56_0404_4P2R_5%

1 4
2 3

56_0404_4P2R_5%

RP35

2 3
1 4

56_0404_4P2R_5%

1

2

C272

+0.9VS

0.1U_0402_16 V4Z

1

2

0.1U_0402_16 V4Z

C279

RP22 56_0404_ 4P2R_5%

RP26 56_0404_ 4P2R_5%

RP25 56_0404_ 4P2R_5%

RP28 56_0404_ 4P2R_5%

RP30 56_0404_ 4P2R_5%

RP34 56_0404_ 4P2R_5%

RP24 56_0404_ 4P2R_5%

0.1U_0402_16 V4Z

1

1

2

2

C274

C281

DDR_A_BS #2

14

DDR_CKE0 _DIMMA

23

DDR_A_MA7

14

DDR_A_MA6

23

DDR_A_MA9

14

DDR_A_MA12

23

DDR_A_MA4

14

DDR_A_MA2

23

DDR_A_MA0

14

DDR_A_BS #1

23

M_ODT0

14

DDR_A_MA13

23

DDR_CKE1 _DIMMA

14

DDR_A_MA11

23

0.1U_0402_16 V4Z

2.2U_0805_16 V4Z

1

2

C255

1

2

C268

Layou t No te:
Pla ce ne ar JP3 4

2.2U_0805_16 V4Z

C498

1

2

0.1U_0402_16 V4Z

C242

1

2

0.1U_0402_16 V4Z

0.1U_0402_16 V4Z

1

2

C252

2.2U_0805_16 V4Z

C473

C491

1

2

0.1U_0402_16 V4Z

0.1U_0402_16 V4Z

C280

1

2

0.1U_0402_16 V4Z

1

1

2

2

C234

C241

Layout Note:
Pla ce thes e res istor
closely JP34,all
trace length <750 mil

Lay out No te:
Pl ace th es e re sist or
clo sely JP 34,all
tra ce l ength Max=1 .3"

4

DDR_A _D0
DDR_A _D1

DDR_A_ DQS#0
DDR_A_ DQS0

DDR_A _D2
DDR_A _D3

DDR_A _D8

2.2U_0805_16 V4Z

C465

1

2

C235

1

2

DDR_CKE0_D IMMA7

DDR_A_BS# 28

DDR_A_BS# 08
DDR_A_W E#8

DDR_A_ CAS#8

DDR_CS1_DI MMA#7

0.1U_0402_16 V4Z

1

2

C227

M_ODT17

ICH_SMBDATA4, 14,15,20,24,26

ICH_SMBCL K4,14,15,2 0,24,26

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

DDR_A _D9

DDR_A_ DQS#1
DDR_A_ DQS1

DDR_A_ D10
DDR_A_ D11

DDR_A_ D16
DDR_A_ D17

DDR_A_ DQS#2
DDR_A_ DQS2

DDR_A_ D18
DDR_A_ D19

DDR_A_ D24
DDR_A_ D25

DDR_A_DM 3

DDR_A_ D26
DDR_A_ D27

DDR_CKE0 _DIMMA

DDR_A_BS #2

DDR_A_MA12
DDR_A_MA9 DDR_A_MA7
DDR_A_MA8

DDR_A_MA5
DDR_A_MA3
DDR_A_MA1

DDR_A_MA10
DDR_A_BS #0
DDR_A_W E#

DDR_A_ CAS#
DDR_CS1_D IMMA#

M_ODT1

DDR_A_ D32
DDR_A_ D33

DDR_A_ DQS#4
DDR_A_ DQS4

DDR_A_ D34
DDR_A_ D35

DDR_A_ D40
DDR_A_ D41

DDR_A_DM 5

DDR_A_ D42
DDR_A_ D43

DDR_A_ D48
DDR_A_ D49

DDR_A_ DQS#6
DDR_A_ DQS6

DDR_A_ D50
DDR_A_ D51

DDR_A_ D56
DDR_A_ D57

DDR_A_DM 7

DDR_A_ D58
DDR_A_ D59

ICH_SMBDATA
ICH_SMBC LK

0.1U_0402_16 V4Z

2006/02/27 2007/02/27

+1.8V

+3VS

1

C308

2

Compal Secret Data

JP34

1

VREF

3

VSS

5

DQ0

7

DQ1

9

VSS

11

DQS0#

13

DQS0

15

VSS

17

DQ2

19

DQ3

21

VSS

23

DQ8

25

DQ9

27

VSS

29

DQS1#

31

DQS1

33

VSS

35

DQ10

37

DQ11

39

VSS

41

VSS

43

DQ16

45

DQ17

47

VSS

49

DQS2#

51

DQS2

53

VSS

55

DQ18

57

DQ19

59

VSS

61

DQ24

63

DQ25

65

VSS

67

DM3

69

NC

71

VSS

73

DQ26

75

DQ27

77

VSS

79

CKE0

81

VDD

83

NC

85

BA2

87

VDD

89

A12

91

A9

93

A8

95

VDD

97

A5

99

A3

101

A1

103

VDD

105

A10/AP

107

BA0

109

WE#

111

VDD

113

CAS#

115

NC/S1#

117

VDD

119

NC/ODT1

121

VSS

123

DQ32

125

DQ33

127

VSS

129

DQS4#

131

DQS4

133

VSS

135

DQ34

137

DQ35

139

VSS

141

DQ40

143

DQ41

145

VSS

147

DM5

149

VSS

151

DQ42

153

DQ43

155

VSS

157

DQ48

159

DQ49

161

VSS

163

NC,TEST

165

VSS

167

DQS6#

169

DQS6

171

VSS

173

DQ50

175

DQ51

177

VSS

179

DQ56

181

DQ57

183

VSS

185

DM7

187

VSS

189

DQ58

191

DQ59

193

VSS

195

SDA

197

SCL

199

VDDSPD

FOX_ASOA426-M4R-TR

SO-DIMM A

REVERSE

Deciphered Date

DQ4
DQ5

DM0

DQ6
DQ7

DQ12
DQ13

DM1

CK0#

DQ14
DQ15

DQ20
DQ21

DM2

DQ22
DQ23

DQ28
DQ29

DQS3#

DQS3

DQ30
DQ31

NC/CKE1

VDD
NC/A15
NC/A14

VDD

VDD

VDD

RAS#

VDD

ODT0

NC/A13

VDD

DQ36
DQ37

DM4

DQ38
DQ39

DQ44
DQ45

DQS5#

DQS5

DQ46
DQ47

DQ52
DQ53

CK1#

DM6

DQ54
DQ55

DQ60
DQ61

DQS7#

DQS7

DQ62
DQ63

SAO

2

VSS

VSS

VSS

VSS

VSS

VSS
CK0

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

A11

BA1

S0#

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS
CK1

VSS

VSS

VSS

VSS

VSS

VSS

SA1

+1.8V

V_DDR_ MCH_REF

2

DDR_A _D4

4

DDR_A _D5

6
8

DDR_A_DM 0

10
12

DDR_A _D6

14

DDR_A _D7

16
18

DDR_A_ D12

20

DDR_A_ D13

22
24

DDR_A_DM 1

26
28

M_CLK_DD R0

30

M_CLK_DDR #0

32
34

DDR_A_ D14

36

DDR_A_ D15

38
40

42

DDR_A_ D20

44

DDR_A_ D21

46
48
50

NC

A7
A6

A4
A2
A0

NC

52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200

DDR_A_DM 2

DDR_A_ D22
DDR_A_ D23

DDR_A_ D28
DDR_A_ D29

DDR_A_ DQS#3
DDR_A_ DQS3

DDR_A_ D30
DDR_A_ D31

DDR_CKE1 _DIMMA

DDR_A_MA11

DDR_A_MA6

DDR_A_MA4
DDR_A_MA2
DDR_A_MA0

DDR_A_BS #1
DDR_A_ RAS#
DDR_CS0_D IMMA#

M_ODT0
DDR_A_MA13

DDR_A_ D36
DDR_A_ D37

DDR_A_DM 4

DDR_A_ D38
DDR_A_ D39

DDR_A_ D44
DDR_A_ D45

DDR_A_ DQS#5
DDR_A_ DQS5

DDR_A_ D46
DDR_A_ D47

DDR_A_ D52
DDR_A_ D53

M_CLK_DD R1
M_CLK_DDR #1

DDR_A_DM 6

DDR_A_ D54
DDR_A_ D55

DDR_A_ D60
DDR_A_ D61

DDR_A_ DQS#7
DDR_A_ DQS7

DDR_A_ D62
DDR_A_ D63

12

R455

R453

10K_0402_5%

12

10K_0402_5%

Title

Size Docume nt Number Re v

Date : Sheet o f

0.1U_0402_16 V4Z

2.2U_0805_16 V4Z

1

1

C363

2

2

M_CLK_DDR 0 7
M_CLK_DDR# 0 7

DDR_THERM # 7,14

DDR_CKE1_ DIMMA 7

DDR_A_BS# 1 8
DDR_A_ RAS# 8
DDR_CS0_DI MMA# 7

M_ODT0 7

M_CLK_DDR 1 7
M_CLK_DDR# 1 7

Compal Electronics, Inc.

DDRII-SODIMM SLOT1

LA-3031P

C362

V_DDR_ MCH_REF 7,14

1

13 49Tuesday, F ebruary 2 8, 2006

0.5

5

DDR_B_ DQS#[0..7 ]8

DDR_ B_D[0..63 ]8

DDR_B_ DM[0..7]8

DDR_B _DQS[0..7 ]8

DDR_B_ MA[0..13]8

0.1U_0402_16 V4Z

1

2

C220

C183

DDR_B_MA9
DDR_B_MA12

DDR_CKE3 _DIMMB
DDR_B_MA11

DDR_B_MA5
DDR_B_MA8

DDR_B_MA7
DDR_B_MA6

DDR_B_MA4
DDR_B_MA2

M_ODT2
DDR_B_MA13

DDR_B_BS #2
DDR_CKE2 _DIMMB

0.1U_0402_16 V4Z

+1.8V

2.2U_0805_16 V4Z

C236

1

2

0.1U_0402_16 V4Z

0.1U_0402_16 V4Z

0.1U_0402_16 V4Z

1

1

2

2

C199

C210

D D

C C

Layout Note:
Place one cap clo se to every 2 pullup
resistors terminated to +0.9V_DDR_VTT

+0.9VS

0.1U_0402_16 V4Z

0.1U_0402_16 V4Z

0.1U_0402_16 V4Z

0.1U_0402_16 V4Z

1

1

1

2

2

C179

RP14

1 4
2 3

56_0404_4P2R_5%

RP17

1 4
2 3

RP16

56_0404_4P2R_5%

1 4
2 3

56_0404_4P2R_5%

RP18

1 4
2 3

RP19

56_0404_4P2R_5%

1 4
2 3

56_0404_4P2R_5%

RP23

2 3
1 4

56_0404_4P2R_5%

2

C186

+0.9VS

5

C176

B B

A A

DDR_B_MA1
DDR_B_MA3

DDR_B_BS #0
DDR_B_MA10

DDR_B_MA0
DDR_B_BS #1

DDR_B_ RAS#
DDR_CS2_D IMMB#

DDR_B_ CAS#
DDR_B_W E#

DDR_CS3_D IMMB#
M_ODT3

0.1U_0402_16 V4Z

1

1

2

2

C197

C213

RP10 56_0404_ 4P2R_5%

RP11 56_0404_ 4P2R_5%

RP12 56_0404_ 4P2R_5%

RP13 56_0404_ 4P2R_5%

RP15 56_0404_ 4P2R_5%

RP21 56_0404_ 4P2R_5%

RP9

56_0404_4P2R_5%

0.1U_0402_16 V4Z

1

2

14
23

14
23

14
23

14
23

14
23

14
23

14
23

4

Layou t No te:
Pla ce ne ar JP1 0

2.2U_0805_16 V4Z

2.2U_0805_16 V4Z

C265

1

1

2

2

0.1U_0402_16 V4Z

C219

C166

1

1

2

2

0.1U_0402_16 V4Z

0.1U_0402_16 V4Z

1

1

2

C173

Layout Note:
Pla ce thes e res istor
closely JP10,all
trace length <750 mil

Lay out No te:
Pl ace th es e re sist or
clo sely JP 10,all
tra ce l ength Max=1 .3"

1

2

2

C218

C163

4

3

+1.8V

JP10

1

VREF

3

DDR_B _D0
DDR_B _D1

DDR_B_ DQS#0
DDR_B_ DQS0

DDR_B _D2
DDR_B _D3

DDR_B _D8

2.2U_0805_16 V4Z

2.2U_0805_16 V4Z

C159

C247

0.1U_0402_16 V4Z

C188

1

2

0.1U_0402_16 V4Z

1

2

C177

C164

1

1

2

2

0.1U_0402_16 V4Z

C161

1

2

DDR_CKE2_ DIMMB7

DDR_B_BS# 28

DDR_B_BS# 08
DDR_B_W E#8

DDR_B_ CAS#8

DDR_CS3_DI MMB#7

M_ODT37

ICH_SMBDATA4, 13,15,20,24,26

ICH_SMBCL K4,13,15,2 0,24,26

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

DDR_B _D9

DDR_B_ DQS#1
DDR_B_ DQS1

DDR_B_ D10
DDR_B_ D11

DDR_B_ D16
DDR_B_ D17

DDR_B_ DQS#2
DDR_B_ DQS2

DDR_B_ D18 DDR_B_D 22
DDR_B_ D19

DDR_B_ D24
DDR_B_ D25

DDR_B_DM 3

DDR_B_ D26
DDR_B_ D27

DDR_CKE2 _DIMMB

DDR_B_BS #2

DDR_B_MA12
DDR_B_MA9
DDR_B_MA8

DDR_B_MA5
DDR_B_MA3
DDR_B_MA1

DDR_B_MA10
DDR_B_BS #0
DDR_B_W E#

DDR_B_ CAS#
DDR_CS3_D IMMB#

M_ODT3

DDR_B_ D32
DDR_B_ D33

DDR_B_ DQS#4
DDR_B_ DQS4

DDR_B_ D34
DDR_B_ D35

DDR_B_ D40
DDR_B_ D41

DDR_B_DM 5

DDR_B_ D42
DDR_B_ D43

DDR_B_ D48
DDR_B_ D49

DDR_B_ DQS#6
DDR_B_ DQS6

DDR_B_ D50
DDR_B_ D51

DDR_B_ D56
DDR_B_ D57

DDR_B_DM 7

DDR_B_ D58
DDR_B_ D59

ICH_SMBDATA
ICH_SMBC LK

+3VS

1

C301

0.1U_0402_ 16V4Z

2006/02/27 2007/02/27

2

Compal Secret Data

VSS

5

DQ0

7

DQ1

9

VSS

11

DQS0#

13

DQS0

15

VSS

17

DQ2

19

DQ3

21

VSS

23

DQ8

25

DQ9

27

VSS

29

DQS1#

31

DQS1

33

VSS

35

DQ10

37

DQ11

39

VSS

41

VSS

43

DQ16

45

DQ17

47

VSS

49

DQS2#

51

DQS2

53

VSS

55

DQ18

57

DQ19

59

VSS

61

DQ24

63

DQ25

65

VSS

67

DM3

69

NC

71

VSS

73

DQ26

75

DQ27

77

VSS

79

CKE0

81

VDD

83

NC

85

BA2

87

VDD

89

A12

91

A9

93

A8

95

VDD

97

A5

99

A3

101

A1

103

VDD

105

A10/AP

107

BA0

109

WE#

111

VDD

113

CAS#

115

NC/S1#

117

VDD

119

NC/ODT1

121

VSS

123

DQ32

125

DQ33

127

VSS

129

DQS4#

131

DQS4

133

VSS

135

DQ34

137

DQ35

139

VSS

141

DQ40

143

DQ41

145

VSS

147

DM5

149

VSS

151

DQ42

153

DQ43

155

VSS

157

DQ48

159

DQ49

161

VSS

163

NC,TEST

165

VSS

167

DQS6#

169

DQS6

171

VSS

173

DQ50

175

DQ51

177

VSS

179

DQ56

181

DQ57

183

VSS

185

DM7

187

VSS

189

DQ58

191

DQ59

193

VSS

195

SDA

197

SCL

199

VDDSPD

FOX_ASOA426-M2R-TR

SO-DIMM B

REVERSE

Deciphered Date

DQ4
DQ5

DM0

DQ6
DQ7

DQ12
DQ13

DM1

CK0#

DQ14
DQ15

DQ20
DQ21

DM2

DQ22
DQ23

DQ28
DQ29

DQS3#

DQS3

DQ30
DQ31

NC/CKE1

VDD
NC/A15
NC/A14

VDD

VDD

VDD

RAS#

VDD

ODT0

NC/A13

VDD

DQ36
DQ37

DM4

DQ38
DQ39

DQ44
DQ45

DQS5#

DQS5

DQ46
DQ47

DQ52
DQ53

CK1#

DM6

DQ54
DQ55

DQ60
DQ61

DQS7#

DQS7

DQ62
DQ63

SAO

VSS

VSS

VSS

VSS

VSS

VSS
CK0

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

BA1

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS
CK1

VSS

VSS

VSS

VSS

VSS

VSS

SA1

2

+1.8V

V_DDR_ MCH_REF

2

DDR_B _D4

4

DDR_B _D5

6
8

DDR_B_DM 0

10
12

DDR_B _D6

14

DDR_B _D7

16
18

DDR_B_ D12

20

DDR_B_ D13

22
24

DDR_B_DM 1

26
28

M_CLK_DD R3

30

M_CLK_DDR #3

32
34

DDR_B_ D14

36

DDR_B_ D15

38
40

42

DDR_B_ D20

44

DDR_B_ D21

46
48
50

NC

A11

A7
A6

A4
A2
A0

S0#

NC

2

52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200

DDR_B_DM 2

DDR_B_ D23

DDR_B_ D28
DDR_B_ D29

DDR_B_ DQS#3
DDR_B_ DQS3

DDR_B_ D30
DDR_B_ D31

DDR_CKE3 _DIMMB

DDR_B_MA11
DDR_B_MA7
DDR_B_MA6

DDR_B_MA4
DDR_B_MA2
DDR_B_MA0

DDR_B_BS #1
DDR_B_ RAS#
DDR_CS2_D IMMB#

M_ODT2
DDR_B_MA13

DDR_B_ D36
DDR_B_ D37

DDR_B_DM 4

DDR_B_ D38
DDR_B_ D39

DDR_B_ D44
DDR_B_ D45

DDR_B_ DQS#5
DDR_B_ DQS5

DDR_B_ D46
DDR_B_ D47

DDR_B_ D52
DDR_B_ D53

M_CLK_DD R2
M_CLK_DDR #2

DDR_B_DM 6

DDR_B_ D54
DDR_B_ D55

DDR_B_ D60
DDR_B_ D61

DDR_B_ DQS#7
DDR_B_ DQS7

DDR_B_ D62
DDR_B_ D63

12

2.2U_0805_16 V4Z

0.1U_0402_16 V4Z

1

1

C89

2

2

M_CLK_DDR 3 7
M_CLK_DDR# 3 7

DDR_THERM # 7,13

DDR_CKE3_ DIMMB 7

DDR_B_BS# 1 8
DDR_B_ RAS# 8
DDR_CS2_DI MMB# 7

M_ODT2 7

M_CLK_DDR 2 7
M_CLK_DDR# 2 7

R257

1 2

R254
10K_0402_5%

Title

Size Docume nt Number Re v

Date : Sheet o f

+3VS

10K_0402_5%

Compal Electronics, Inc.

DDRII-SODIMM SLOT2

LA-3031P

1

V_DDR_ MCH_REF 7,13

C90

1

14 49Tuesday, F ebruary 2 8, 2006

0.5

5

PCI

SRC

CPU

CLKSEL1

0

1

Stuff

No Stuff

Stuff

No Stuff

Stuff

No Stuff

R650

8.2K_0402_5%

FSA

1 2

CLK_Ra

1 2

CLK_Rb

R697

8.2K_0402_5%

1 2

CLK_Rc

+3VS

1 2

R718

300_0402_5%

J6

FSLA

CLKSEL0

FSB

10/18

12

12

+VCCP

1 2

12

R655
0_0402_5%

12

+VCCP

1 2

R674
0_0402_5%

12

+VCCP

1 2

12

R701
0_0402_5%

12

1 3

D

5

MHz

133

166

CLK_Ra

CLK_Rd

CLK_Rd

CLK_Ra

CLK_Rd

CLK_Ra

CLK_Re

R646

@

56_0402_5%

CLK_Rd

1 2

R651

1K_0402_5%

R658

1K_0402_5%

R665

1K_0402_5%

1 2

R672

1K_0402_5%

R680

@

0_0402_5%

CLK_Re

R693

1K_0402_5%

1 2

R698

1K_0402_5%

R707

@

0_0402_5%

CLK_Rf

Q107

2

G

2N7002_SOT23@

S

MHz

MHz

1000

33.31

100

33.3

CLK_Rb

CLK_Rc

CLK_Rf

CLK_Re

CLK_Rf

CLK_Re

CLK_Rb

CLK_Rc

CLK_Rf

CLK_Rc

CLK_Rb

MCH_CLKSEL0 7 CL K_48M_CB23

MCH_CLKSEL1 7

MCH_CLKSEL2 7

VGATE 7,20,43

High:Pin18/19 = 100MHz

*

Low:Pin18/19 = 96MHz Low:Pin44/45 = CPUCLK2_ITP

+3VS

+3VS

+3VS

+VCCP

+CK_VDD_XDP

12

R640

0_0402_5%@

1

C734

0.1U_0402_16 V4Z@

2

CLK_14M_I CH20

CLK_DEBUG_PORT26

CLK_MC H_DREFCLK7

CLK_MC H_DREFCLK#7

NOXDP@ : means just build when XDP function disable.

XDP@ : means just build when XDP function enable.
When this time, docking PCI express will not work.

LCD(Low)/SRC(High)
clock select

+3VS +3VS

12

R716
10K_0402_5%

PCI _ICH

12

R719

10K_0402_5%@

FSLC1FSLB

CLKSEL2

0

Table : ICS954306

D D

FSB Frequency Selet:

CPU Driven

(Default)

*

533MHz

667MHz

C C

CPU_BSEL05

CPU_BSEL15

B B

CLKREF 1

CPU_BSEL25

R1032

2K_0402_1%@

CLK_ENABLE#

A A

NO SHO RT PADS

4

1 2

R633 0_0805_5%

1 2

R634 0_0805_5%

R637

1 2

0_0805_5%

NOXDP@

R638

1 2

0_0805_5%XDP@

0.1U_0402_16 V4Z

CLKI REF

0.1U_0402_16 V4Z

CLK_48M_I CH20

9/16

H_STP_CPU#20

H_STP_PCI#20

CLK_ENABLE#43

CLK_ PCI_ICH18

CLK_14M_KBC32

CLK_14M_SIO30

CLK_PC I_EC32

CLK_PCI_TC G31

CLK_PCI_PC M22

ICH_SMBDATA4, 13,14,20,24,26

ICH_SMBCL K4,13,14, 20,24,26

CLK_MC H_DREFCLK

CLK_MC H_DREFCLK#

CLK_PC I_FWH31

CLK_PC I_SIO30

Pin44/45 function select

High:Pin44/45 = CLKREQ

*

4

+CK_VDD_MAI N1

1

C719

10U_0805_10V4Z

2

+CK_VDD_MAI N2

1

C723

10U_0805_10V4Z

2

+CK_VDD_XDP

1

C726

10U_0805_10V4Z

2

+CK_VDD_XDP

1

C732

2

1

C733

2

CLK_48M_I CH
CLK_48M_CB

CLK_14M_I CH

H_STP_CPU#
H_STP_PCI#

CLK_ENABLE#

CLK_ PCI_ICH P CI_ICH

CLK_14M_KBC
CLK_14M_SIO

ICH_SMBDATA

ICH_SMBC LK

R700 12_0402_5%F WH@
R704 12_0402_5%

R649 12 _0402_5%

R652 12 _0402_5%

R657 33 _0402_5%

1 2

R668 12_0402_5%

R671 12_0402_5%

1 2

R945 33_0402_5%

1 2

R942 33_0402_5%

12

R717

PCI_M INI

12

R720

CK_VDD_ 48

CK_V DD_REF

R664

33_0402_5%

12

R67610K_0402_5%

12
12

12

12

12
12

10K_0402_5%NOXDP@

10K_0402_5%XDP@

1

2

1

2

5/20

1

2

+CK_VDD_M AIN1

12
12

12

R6604.7K_0402_1%

12

12
12

R67333_0402_5%DEBUG@

R67733_0402_5%

R68133_0402_5%

R68433_0402_5%

MCH_DR EFCLK

MCH_DR EFCLK#

3

1

C720

0.1U_0402_16 V4Z

C724

0.1U_0402_16 V4Z

C727

0.1U_0402_16 V4Z

FSA

FSB

CLKREF 1

CLKI REF

CLKREF 0

PCI_M INI

PCI_CL K3
PCI_ EC

PCI_CL K5

PCI_PCM

PCI_CL K3

C721

0.1U_0402_16 V4Z

2

1

C725

0.1U_0402_16 V4Z

2

1

C728

0.1U_0402_16 V4Z

2

U25

16

VDD

10

VDD48

5

VDDPCI

24

VDDSRC

33

VDDSATA

41

VDDSRC

50

VDDCPU

55

VDDREF

11

FSLA/USB_48MHz

15

FSLB/TEST_MODE

59

FSLC/TEST_SEL/REF1

46

IREF

61

CPU_STOP#

8

PCI/SRC_STOP#

9

Vtt_PwrGd#/PD

7

**SEL_LCDCLK#/PCICLK_F1

60

REF0/PCICLK1

62

*REQ_SEL/PCICLK2

1

*SEL_PCI1/PCICLK3

2

**SEL_SATA1/PCICLK4

3

**SEL_SATA2/PCICLK5

6

PCICLK6

54

SDATA

53

SCLK

13

DOTT_96MHz

14

DOTC_96MHz

4

GND

12

GND

17

GND

58

GND

47

GNDCPU

25

GNDSRC

40

GNDSRC

32

GNDSATA

ICS9LP30BGLF_TSSOP64

* Internal Pull-Up Resistor
** Internal Pull-Down Resistor

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

1

C722

0.1U_0402_16 V4Z

2

R635

1 2

1_0805_1%

1 2

R636

2.2_0805_1%

1

C729

0.1U_0402_16 V4Z

2

LCDCLK_SST/SRCCLKT0

LCDCLK_SSC/SRCCLKC0

SATA1/SRCCLKT4

SATA1/SRCCLKC4

SATA2/SRCCLKT5

SATA2/SRCCLKC5

*CPUCLKT2_ITP/CLKREQC#

*CPUCLKC2_ITP/CLKREQD#

2006/02/27 2007/02/27

3

CK_V DD_REF

CK_VDD_ 48

SATACLKT

SATACLKC

CPUCLKT0

CPUCLKC0

CPUCLKT1

CPUCLKC1

*CLKREQA#

SRCCLKT2

SRCCLKC2

*CLKREQB#

SRCCLKT1

SRCCLKC1

SRCCLKT3

SRCCLKC3

SRCCLKT6

SRCCLKC6

SRCCLKT8

SRCCLKC8

SRCCLKT7

SRCCLKC7

Pla ce c ryst al wit hin
500 mils of CK4 10

C730 33P_0402_50V8J

12

CLK_XTAL_IN

57

X1

CLK_XTAL_OUT

56

X2

28

29

CPU_BC LK

52

CPU_BCL K#

51

MCH_BCLK

49

MCH_BCLK#

48

64

SSCD REFCLK

18

SSCDREF CLK#

19

PCIE_LOM

22

PCIE_LOM#

23

PCIE_SATA

30

PCIE_SATA# CLK_PCIE_SATA#

31

63

20

21

PCIE_D OCK C LK_PCIE_DOC K

26

27

PCIE _ICH

35

PCIE _ICH#

34

CPU_XDP

45

MCH_3GPLL

37

MCH_3GPLL#

36

43

42

CPU_XDP#

44

PCIE_M CARD

39

PCIE_M CARD#

38

Y3

14.31818MHZ_20P_6X1430004201

C731 33P_0402_50V8J

Routing th e t race at leas t 10mil

R639

1 2

R641 0_0402_5%

1 2

Routing th e t race at leas t 10mil

1 2

R642 24_0402_5%

1 2

R644 24_0402_5%

1 2

R647 24_0402_5%

1 2

R653 24_0402_5%

9/16

1 2

R943 24_0402_5%

1 2

R944 24_0402_5%

9/16

1 2

R678 24_0402_5%

1 2

R682 24_0402_5%

1 2

R666 24_0402_5%

1 2

R669 24_0402_5%

9/16

R675 10K_0402_5%

9/16

1 2

R685 24_0402_5%

1 2

R687 24_0402_5%

1 2

R689 24_0402_5%

1 2

R691 24_0402_5%

R694 10K_0402_5%NOXDP@

R696 0_0402_5%NOXDP@

1 2

R699 24_0402_5%XDP@

1 2

R702 24_0402_5%

1 2

R705 24_0402_5%

9/16

R711 0_0402_5%NOXDP@

1 2

R712 24_0402_5%XDP@

1 2

R713 24_0402_5%

1 2

R714 24_0402_5%

9/16

+3VS

R695 10K_0402_5%@

Compal Secret Data

Deciphered Date

2

12

12

0_0402_5%

CLK_CP U_BCLK

CLK_CPU _BCLK#

CLK_MCH_B CLK

CLK_MCH_BCL K#

CLKREQA#

MCH_SS CDREFCLK

MCH_SS CDREFCLK#

12

12

R710 10K_0402_5%NOXDP@

12

10/04

CLK_PCIE_LOM

CLK_PCIE_LOM#

CLK_PCIE_SATA

CPPE#CLKREQ B#

CLK_PC IE_DOCK#PCIE_D OCK#

CLK_ PCIE_ICH

CLK_PC IE_ICH#

12

CLKREQ C#

CLK_CPU_XDP

CLK_MCH_3GPLL

CLK_MCH_3GPLL#

12

CLKREQ D#

CLK_CPU_XDP#

CLK_PC IE_MCARD

CLK_PC IE_MCARD#

5/23

12

2

CLKREQA# 24

10/04

PCI_ EC

1

CLKREQA#

CLKREQB#

CLKREQ C#

CLKREQ D#

1/12

Place near U25

1 2

C1050

@

1000P_0402_50V7K

1 2

C1051

1000P_0402_50V7K@

1 2

C1052

1000P_0402_50V7K@

1 2

C1049

1000P_0402_50V7K

Place near U25

Place these components
near each pin within 40
mils.

CLK_CPU _BCLK 4

CLK_CPU_ BCLK# 4

CLK_MCH_BCL K 7

CLK_MCH_BCL K# 7

MCH_SS CDREFCLK 7

MCH_SS CDREFCLK# 7

CLK_PCIE_LOM 24

CLK_PCIE_LOM# 24

CLK_PCIE_SATA 19

CLK_PCIE_SATA# 19

CPPE# 18,34

CLK_PC IE_DOCK 34

CLK_PC IE_DOCK# 34

CLK_P CIE_ICH 20

CLK_PC IE_ICH# 20

+3VS

CLKREQC # 7

CLK_CPU_XDP 4

CLK_MCH_3GPLL 7

CLK_MCH_3GPLL# 7

+3VS

CLKREQD # 26

CLK_CPU_XDP# 4

CLK_PC IE_MCARD 26

CLK_PC IE_MCARD# 26

Title

Size Docume nt Number Re v

Date : Sheet of

CLK_CP U_BCLK

CLK_CPU _BCLK#

CLK_MCH_B CLK

CLK_MCH_BCL K#

MCH_SS CDREFCLK

MCH_SS CDREFCLK#

CLK_PCIE_LOM

CLK_PCIE_LOM#

CLK_PCIE_SATA

CLK_PCIE_SATA#

CLK_MCH_3GPLL

CLK_MCH_3GPLL#

CLK_PC IE_MCARD

CLK_PC IE_MCARD#

CLK_ PCIE_ICH

CLK_PC IE_ICH#

CLK_CPU_XDP

CLK_CPU_XDP#

CLK_PC IE_DOCK

CLK_PC IE_DOCK#

CLK_MC H_DREFCLK

CLK_MC H_DREFCLK#

R643 49.9_0402_1%@

R645 49.9_0402_1%@

R648 49.9_0402_1%@

R654 49.9_0402_1%@

1 2

R659 49.9_0402_1%@

1 2

R661 49.9_0402_1%@

1 2

R662 49.9_0402_1%@

1 2

R663 49.9_0402_1%@

1 2

R667 49.9_0402_1%@

1 2

R670 49.9_0402_1%@

1 2

R679 49.9_0402_1%@

1 2

R683 49.9_0402_1% @

1 2

R686 49.9_0402_1%@

1 2

R688 49.9_0402_1%@

1 2

R690 49.9_0402_1%@

1 2

R692 49.9_0402_1%@

R703 49.9_0402_1%@

R706 49.9_0402_1%@

R708 49.9_0402_1%@

R709 49.9_0402_1%@

R981 49.9_0402_1%@

R982 49.9_0402_1%@

9/16

If LP Chip st uff, al l 49.9_0402
cou ld be remov ed .

Compal Electronics, Inc.

Clock generator

LA-3031P

1

12

12

12

12

12

12

12

12

12

12

0.5

15 49Tuesd ay, Febru ary 28, 2006

A

CRT Connector

B

C

D

E

1.1A_6 VDC_FUSE

1/12

L79

1 2

L80

1 2

L81

1 2

C310

12P_0402_50V8J

@

+5VS

CRTVDD+3VS

F1

D18

21

2 1

CH491D _SC59

0.1U_0402_16 V4Z

RED_ R

GREEN_ R

BLUE_R

D_DD CCLK

C315

D_DDCD ATA

1

2

1 1

HSYNC9
VSYNC9

DDCC LK9

DDCDAT A9

2 2

HSY NC
VSYN C

DDC CLK
DDCDAT A

C319

0.22U_0603_10V7K

1

2

CRTVD D

U19

13

SYNC_IN1

15

SYNC_IN2

10

DDC_IN1

11

DDC_IN2

8

BYP

HSY NC

R5 10K_0402_5%

1 2

VSYN C

R6 10K_0402_5%

1 2

C3

1 2

0.22U_0603_10V7K

+3VS

C321

1 2

0.22U_0603_10V7K

+2.5VS

1

2

7

VCC_DDC

VCC_SYNC

VCC_VIDEO

VIDEO_1
VIDEO_2
VIDEO_3

SYNC_OUT1
SYNC_OUT2

DDC_OUT1
DDC_OUT2

GND

6

D_BLUE

3

D_GREE N

4

D_RE D

5

R988 0_0402_5%

1 2

R989 0_0402_5%

14

1 2

16

9
12

CM2009-00QR_QSOP16

D_DD CCLK
D_DDCD ATA

D_H SYNC
D_ VSYNC

D_DD CCLK 34
D_DDCD ATA 34

D_H SYNC 3 4
D_V SYNC 34

D_RE D9,34

D_GRE EN9, 34

D_BLUE9,3 4

D_RE D

D_GREE N

D_BLUE

1

C313

12P_0402_50V8J

2

@

D_H SYNC
D_ VSYNC

DDC CLK
DDCDAT A

D_DD CCLK
D_DDCD ATA

BK2125LL560-T 0805

BK2125LL560-T 0805

BK2125LL560-T 0805

1 2
1 2

1 2
1 2

1

2

1

C314

12P_0402_50V8J

2

@

R2 2.2K_0402_5%
R4 2.2K_0402_5%

R1 2.2K_0402_5%
R3 2.2K_0402_5%

CRTVD D+RCRT_VCC

W=40mils

JP2

6

11

18
1
7

12

2
8

13

3
9

14

4

10
15

19
5

SUYIN_ 070453FR015S2 08ZR

1/12

TV-Out Connector

3 3

Please close to JP1

D3
DAN217_SC5 9@

D5
DAN217_SC5 9@

1

2

3

2

D1
DAN217_SC5 9@

1

3

1

2

+3VS

3

10/5

1

2

1 2

1 2

1 2

C1039

18P_0402_50V8J@

R991

0_0603_5%

R992

0_0603_5%

R993

0_0603_5%

LUMA_C

CRMA_C

COMPS_C

JP1

1
2
3
4
5
6
7

SUYIN_330 07SR-07T1-C

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2006/02/27 2007/02/27

Compal Secret Data

Deciphered Date

Title

Size Docume nt Number Re v

D

Date : Sheet o f

Compal Electronics, Inc.

CRT & TVout Connector

LA-3031P

16 49Tuesday, F ebruary 2 8, 2006

E

0.5

18P_0402_50V8J@

LUMA_CL

CRMA_CL

COMPS_CL

A

C1037

1

1

C1038

2

2

18P_0402_50V8J@

LUMA_CL9,3 4

4 4

CRMA_CL9,34

COMPS_CL9,34

5

4

3

2

1

LCD POWER CIRCUIT LCD/PANEL BD. CONN.

B+_LCD

C586

12

LCDV DD

DIGI_TX32
DIGI_RX32

ALS_EN18

+5VS_INV

KSI_D_832,33
KSI_D_932,33

KSI_D_1032, 33
KSI_D_1131, 32,33

KSO1432

USB20_N220
USB20_P220

0.1U_0603_50 V4Z

68P_0402_50V8J

1 2

B+

0_0805_5%

+3VS

D62

1

2

@

PRTR5V0U2X_SOT143-4

C587

L62

DIGI_TX
DIGI_RX
DIG_RESET#_ R
ALS_EN

KSI_D_8
KSI_D_9
KSI_D_10
KSI_D_11
KSO14
DIGI_ SLEEP_RDIGI_SL EEP

USB20_N2
USB20_P2

GND

IO2

IO1

VIN

12

3

4

JP28

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50

ACES_88107-5000G

USB20_P2

+3VS

8/12

1

TXBCLK+

3

TXBCLK-

5
7

TXB2+

9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49

TXB2-

TXB1+
TXB1-

TXB0­TXB0+

TXACLK+
TXACLK-

TXA2+
TXA2-

TXA1+
TXA1-

TXA0­TXA0+

TXBCLK+ 9
TXBCLK- 9

TXB2+ 9
TXB2- 9

TXB1+ 9
TXB1- 9

TXB0- 9
TXB0+ 9

TXACLK+ 9
TXACLK- 9

TXA2+ 9
TXA2- 9

TXA1+ 9
TXA1- 9

TXA0- 9
TXA0+ 9

LCDV DD

D D

100_0402_1%

ENAVD D9

R19

ENAV DD

12

Q5

13

D

2N7002_SOT23

S

2

R1038

2

G

13

1 2

47K_0402_5%

Q6
DTC124EK_SC59

LCDV DD

C29

0.1U_0402_16 V4Z

Q8

D

S

AO3413_SOT23

1 3

R1039 1M_0402_5%

G

2

1 2

C1045

1 2

1

C31

4.7U_0805_10 V4Z

2

0.047U_0402_16V7K

1

2

+3VALW

1

2

C20

4.7U_0805_10 V4Z

@

DIG_RESET#20

11/23

11/24

DIGI_SLEE P20

DIG_RESET#

9/14

R1041

1 2

0_0402_5%

R1040

1 2

0_0402_5%

BKLT_CTL_C9

LCD_CL K9

LCD_DAT9

11/23

Finger printer

C C

11/14

7/27

USB20_N2

DVI CONTROLLER

7/19

DVI_DV DD_2.5V

DVI_AV DD_3V

DVI_DV DD_2.5V

DVDD12DVDD

DGND7DGND30AGND31AGND39AGND45TGND18TGND24AGND_PLL

THEMPAD

49

28

B B

+2.5VS

12

A A

5

C645 a nd C6 46 nee d to be c lose to U1 1

7/14

R497
10K_0402_5%

AS

W=2 0 mi ls

SDVOB_INT+9
SDVOB_INT-9

1.2K_0402_1%

C646 0.1U_04 02_16V4Z
C645 0.1U_04 02_16V4Z

12

R103

10K_0402_5%

R_SDVOB_INT+
R_SDVOB_INT -

SDVOB_R+9
SDVOB_R-9

SDVOB_G+9
SDVOB_G-9

SDVOB_B+9
SDVOB_B-9

SDVOB_CLK+9
SDVOB_CLK-9

PLT_RST#7,18,20, 22,24,26,30,31,3 2

R107

AS
PLT_RST#

12

R498
10K_0402_5%

1 2

U11

32

SDVOB_INT+

33

SDVOB_INT-

37

SDVOB_R+

38

SDVOB_R-

40

SDVOB_G+

41

SDVOB_G-

43

SDVOB_B+

44

SDVOB_B-

46

SDVOB_CLK+

47

SDVOB_CLK-

3

AS

2

RESET#

25

VSWING

27

ATPG

26

SCEN

4

DVI_DV DD_2.5V

0.1U_0402_16 V4Z

48

21

1

TVDD15TVDD

AVDD36AVDD42AVDD

TLC#

6

SC_PROM
SD_PROM

34

TLC

TDC0#

TDC0

TDC1#

TDC1

TDC2#

TDC2

HPDET

SC_DDC
SD_DDC

SPD
SPC

NC

NC

CH7307C_LQ FP48

35

AVDD_PLL

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

DVI_CL K-

13

DVI_CLK+

14

DVI_TX0-

16

DVI_TX0+

17

DVI_TX1-

19

DVI_TX1+

20

DVI_TX2-

22

DVI_TX2+

23

DVI_DETECT

29

DVI_ DDC_CLK

11

DVI_DD C_DAT

10

9
8

SDVO_SDAT

5

SDVO_SCLK

4

Issued Date

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

DVI_CLK - 34
DVI_CLK+ 34
DVI_TX0- 34
DVI_TX0+ 34
DVI_TX1- 34
DVI_TX1+ 34
DVI_TX2- 34
DVI_TX2+ 34

DVI_DETECT 34

DVI_ DDC_CLK 34
DVI_DD C_DAT 34

SDVO_SDAT 9
SDVO_SCLK 9

2006/02/27 2007/02/27

C928

0.1U_0402_ 16V4Z

Compal Secret Data

C929

0.1U_0402_ 16V4Z

DVI_DD C_DAT

Deciphered Date

7/19

C115

C930

0.1U_0402_16 V4Z

0.1U_0402_16 V4Z

C931

+5VS +5VS

12

C104

DVI_AV DD_3V

C358

0.1U_0402_16 V4Z

0.1U_0402_16 V4Z

SDVO_SDAT
SDVO_SCLK

R301
10K_0402_5%

2

0.1U_0402_16 V4Z

C359

R131 5.6K_0402_5%

1 2

R132 5.6K_0402_5%

1 2

7/14 7/ 14

1

C584

2

150P_0402_50V8J

@

PJP23

2 1

PAD-SH ORT 2x2m

1

C123

10U_0805_10V4Z

2

PJP24

2 1

PAD-SH ORT 2x2m

1

C360

10U_0805_10V4Z

2

DVI_ DDC_CLK

Title

Size Docume nt Number Re v

Date : Sheet o f

+2.5VS

+3VS

+2.5VS

12

R300
10K_0402_5%

Compal Electronics, Inc.

DVI (CH7307)/LCD CONN.

LA-3031P

1

17 49Tuesday, F ebruary 2 8, 2006

0.5

5

4

3

2

1

D D

C C

B B

+3VS

R722 8.2K_0402_5%

1 2

R723 8.2K_0402_5%

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

R724 8.2K_0402_5%

R725 8.2K_0402_5%

R726 8.2K_0402_5%

R727 8.2K_0402_5%

R728 8.2K_0402_5%

R729 8.2K_0402_5%

R730 8.2K_0402_5%

R731 8.2K_0402_5%

R743 8.2K_0402_5%

R744 8.2K_0402_5%

R745 8.2K_0402_5%

+3VS

R733 8.2K_0402_5%

R734 8.2K_0402_5%

R735 8.2K_0402_5%

R736 8.2K_0402_5%

R737 8.2K_0402_5%

R738 8.2K_0402_5%

R740 8.2K_0402_5%

R741 8.2K_0402_5%@

R746 8.2K_0402_5%

R963 8.2K_0402_5%

PCI_DEVSE L#

PCI_STOP#

PCI_ TRDY#

PCI_FRAM E#

PCI_PLOC K#

PCI _IRDY#

PCI_SE RR#

PCI_PE RR#

PCI_REQ 4#

PCI_REQ 3#

PCI_REQ 0#

PCI_REQ 1#

PCI_REQ 2#

PCI_PI RQA#

PCI_PI RQB#

PCI_P IRQC#

PCI_P IRQD#

PCI_PI RQE#

PCI_P IRQF#

PCI_PI RQG#

PCI_P IRQH#

CPPE#

ICH_GP IO48

PCI_A D[0..31]22

PCI_P IRQC#22
PCI_P IRQD#22

PCI_AD 0
PCI_AD 1
PCI_AD 2
PCI_AD 3
PCI_AD 4
PCI_AD 5
PCI_AD 6
PCI_AD 7
PCI_AD 8
PCI_AD 9
PCI_AD 10
PCI_AD 11
PCI_AD 12
PCI_AD 13
PCI_AD 14
PCI_AD 15
PCI_AD 16
PCI_AD 17
PCI_AD 18
PCI_AD 19
PCI_AD 20
PCI_AD 21
PCI_AD 22
PCI_AD 23
PCI_AD 24
PCI_AD 25
PCI_AD 26
PCI_AD 27
PCI_AD 28
PCI_AD 29
PCI_AD 30
PCI_AD 31

PCI_PI RQA#

PCI_PI RQB#
PCI_P IRQC#
PCI_P IRQD#

U28B

E18

AD0

C18

AD1

A16

E16
A18
E17
A17
A15
C14
E14
D14
B12
C13
G15
G13
E12
C11
D11
A11
A10

AE5
AD5
AG4
AH4
AD9

F18

F11
F10

E9

D9

B9
A8
A6

C7

B6
E6

D6

A3
B4

C5

B5

PCI

AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31

Interrupt I/F

PIRQA#
PIRQB#
PIRQC#
PIRQD#

MISC

RSVD[1]
RSVD[2]
RSVD[3]
RSVD[4]
RSVD[5]

82801GHM QK65 B0_BGA652

REQ0#
GNT0#
REQ1#
GNT1#
REQ2#
GNT2#
REQ3#

GNT3#
REQ4# / GPIO22
GNT4# / GPIO48

GPIO1 / REQ5#

GPIO17 / GNT5#

C/BE0#

C/BE1#

C/BE2#

C/BE3#

IRDY#

PAR

PCIRST#

DEVSEL#

PERR#

PLOCK#

SERR#

STOP#

TRDY#

FRAME#

PLTRST#

PCICLK

PME#

GPIO2 / PIRQE#
GPIO3 / PIRQF#
GPIO4 / PIRQG#
GPIO5 / PIRQH#

RSVD[6]
RSVD[7]
RSVD[8]
RSVD[9]

MCH_SYNC#

D7
E7
C16
D16
C17
D17
E13
F13
A13
A14
C8
D8

B15
C12
D12
C15

A7
E10
B18
A12
C9
E11
B10
F15
F14
F16

C26
A9
B19

G8
F7
F8
G7

AE9
AG8
AH8
F21
AH20

PCI_REQ 0#

PCI_REQ 1#

PCI_REQ 2#
PCI_GNT2#
PCI_REQ 3#

PCI_REQ 4#
ICH_GP IO48
CPPE#
ALS_EN#

PCI_CBE #0
PCI_CBE #1
PCI_CBE #2
PCI_CBE #3

PCI _IRDY#
PCI_PA R
PCI_PC IRST#
PCI_DEVSE L#
PCI_PE RR#
PCI_PLOC K#
PCI_SE RR#
PCI_STOP#
PCI_ TRDY#

PCI_FRAM E#

PCI_PLTRST#
CLK_ PCI_ICH
PCI_PME#

PCI_PI RQE#
PCI_P IRQF#
PCI_PI RQG#
PCI_P IRQH#

PCI_REQ2# 22
PCI_GNT2# 22

CPPE# 15,34

PCI_CBE# 0 22
PCI_CBE# 1 22
PCI_CBE# 2 22
PCI_CBE# 3 22

PCI _IRDY# 22
PCI_PA R 22

PCI_DEVSEL # 22
PCI_PE RR# 22

PCI_SE RR# 22,32
PCI_STOP# 22
PCI_T RDY# 22
PCI_FRAME# 22

CLK_ PCI_ICH 15
PCI_PME# 22

PCI_PI RQE# 22

PCI_PI RQG# 22

R742

12

0_0402_5%

9/8

11/23

MCH_ ICH_SYNC # 7

PCI_PC IRST#

PCI_PLTRST#

ACCEL_INT 26, 32

ALS_EN#

Pla ce clos ely pin A9

CLK_ PCI_ICH

R748

10_0402_5% @

1 2

1

C735

8.2P_0402_50V@

2

+5VS

2

G

+3VS

1

B

2

A

R732

12

0_0402_5%

+3VS

1

B

2

A

R739

12

0_0402_5%

R721

330_0402_5%

1 2

ALS_EN

13

D

Q74
2N7002_SOT23

S

11/23

10/7

5

U39

P

4

Y

G

3

TC7SH08FUF _SSOP5

@

10/7

5

U40

P

4

Y

G

3

TC7SH08FUF _SSOP5@

ALS_EN 17

PCI_RST#

PLT_RST#

PCI_RST# 22,23

PLT_RST# 7,17, 20,22,24,26,30,3 1,32

ALS_EN#

Boot BIOS destination

LPC@SPI@

BIOS_SEL1 Short Open

A A

The pad mu st be pla ced on PCB easily

L

conta ct s pace for BIOS tea m se ttin g.

5

12

R749

1K_0402_5%SPI@

21

BIOS_SEL1
PAD-NO SHORT 2x2m

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/02/27 2007/02/27

Compal Secret Data

Deciphered Date

Title

Size Docume nt Number Re v

2

Date : Sheet of

Compal Electronics, Inc.

ICH7-M(1/4)

LA-3031P

18 49Tuesd ay, Febru ary 28, 2006

1

0.5

5

4

3

2

1

R75439_0402_5%

R75539_0402_5%

R75639_0402_5%

R75739_0402_5%

R75939_0402_5%

R76039_0402_5%

R99939_0402_5%
R100039_0402_5%

R76539_0402_5%

R76639_0402_5%

1 2

24.9_0402_1%

R3904.7K_0402_5%

12

R1918.2K_0402_5%

12

ICH_RTCX1

12

R432

10M_0402_5%

ICH_RTCX2

ICH_RT CRST#

ICH_IN TVRMEN
SM_INT RUDER#

AC97_BITCLK
AC97 _SYNC

AC97_RST#

AC97_ SDIN_0
AC97_ SDIN_1

AC97_SDOUT

HDD_L ED#

SATA_RXN0_C
SATA_RXP0_C
SATA_TXN0_C
SATA_TXP0_C

CLK_PCIE_SATA#
CLK_PCIE_SATA

R770

PD_ IORDY
PD_I RQ

U28A

AB1

RTXC1

AB2

RTCX2

AA3

RTCRST#

W4

INTVRMEN

Y5

INTRUDER#

W1

EE_CS

Y1

EE_SHCLK

Y2

EE_DOUT

W3

EE_DIN

V3

LAN_CLK

U3

LAN_RSTSYNC

U5

LAN_RXD0

V4

LAN_RXD1

T5

LAN_RXD2

U7

LAN_TXD0

V6

LAN_TXD1

V7

LAN_TXD2

U1

ACZ_BCLK

R6

ACZ_SYNC

R5

ACZ_RST#

T2

ACZ_SDIN0

T3

ACZ_SDIN1

T1

ACZ_SDIN2

T4

ACZ_SDOUT

AF18

SATALED#

AF3

SATA0RXN

AE3

SATA0RXP

AG2

SATA0TXN

AH2

SATA0TXP

AF7

SATA2RXN

AE7

SATA2RXP

AG6

SATA2TXN

AH6

SATA2TXP

AF1

SATA_CLKN

AE1

SATA_CLKP

AH10

SATARBIASN

AG10

SATARBIASP

AG16

IORDY

AH16

IDEIRQ

AF16

DDACK#

AH15

DIOW#

AF15

DIOR#

82801GHM QK65 B0_BGA652

RTC

GPIO49 / CPUPWRGD

LPCCPU

LDRQ1# / GPIO23

LFRAME#

LAN

A20GATE

CPUSLP#

TP1 / DPRSTP#

TP2 / DPSLP#

INIT3_3V#

AC-97/AZALIA

STPCLK#

THERMTRIP#

SATA

IDE

LAD0
LAD1
LAD2
LAD3

LDRQ0#

A20M#

FERR#

IGNNE#

INIT#

INTR

RCIN#

SMI#

DCS1#
DCS3#

DD10
DD11
DD12
DD13
DD14
DD15

DDREQ

NMI

DA0
DA1
DA2

DD0
DD1
DD2
DD3
DD4
DD5
DD6
DD7
DD8
DD9

AA6
AB5
AC4
Y6

AC3
AA5

AB3

AE22
AH28

AG27

AF24
AH25

AG26

AG24

AG22
AG21
AF22
AF25

AG23

AF23
AH24

AH22

AF26

AH17
AE17
AF17

AE16
AD16

AB15
AE14
AG13
AF13
AD14
AC13
AD12
AC12
AE12
AF12
AB13
AC14
AF14
AH13
AH14
AC15

AE15

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3

LPC_DRQ# 0

LPC_FRAME#

R750 10K_0402_5%

GATEA20
H_A20M#

H_CPUS LP_R#

DPRSLP#

R751 0_0402_5%

DPSLP#

R752 0_0402_5%

R753 56_0402_5%

H_F ERR#

H_PW RGOOD

H_IG NNE#
FWH_ INIT#
H_INIT #

H_INT R

KB_RST#

H_SMI#
H_NMI

R763

H_STPCLK#

12

0_0402_5%

THRMTRIP_ ICH#

LPC_AD [0..3] 2 6,30,31,32

LPC_DRQ# 0 30

T53

PAD

LPC_FRAME# 26,30,3 1,32

12

GATEA20 32
H_A20M# 4

T14

PAD

12
12
12

H_FE RR# 4

H_PW RGOOD 4

H_IGN NE# 4
FWH_ INIT# 31
H_INIT # 4
H_INT R 4

R758

12

10K_0402_5%

KB_RST# 32

H_SMI# 4
H_NMI 4

H_STPCLK# 4

R764 24.9_0402_1%

11/23

7/15

+3VS

H_DPRSTP# 4,43
H_DPSLP# 4
+VCCP

+VCCP

+3VS

12

R761

1 2

56_0402_5%

Pla ce c lose to ICH7

+RTCVCC

R122

1 2

100_0603_1%

2

C100

0.1U_0402_16 V4Z

1

H_THERMTRIP# 4,7

D10

1

DAN202U _SC70

+3VL

3

BATT1.2

2

R121

1 2

511_0603_1%

BATT1.1

W=20mils

JP32

E&T_7651

-+

21

12

C516 15 P_0402_50V8J

Y4

11/24

D D

C C

B B

+3VS

12

+3VALW

R762
10K_0402_5%

HDD_L ED#

12

R767

332K_0402_1%@

+RTCVCC

R230
20K_0402_5%

PAD-NO SHORT 2x2m

CMOS_CLR1

+RTCVCC

12

R768

332K_0402_1%

ICH_IN TVRMEN

12

R769

0_0402_5%@

1 2

1 2

AC97_BITCL K_MDC33

AC97_BIT CLK_CODEC27

AC97 _SYNC_COD EC27

AC97_RST# _CODEC27

AC97_SDO UT_CODEC27

AC97_SDOUT _MDC33

21

C287
1U_0603_10V4Z

AC97_S YNC_MDC33

AC97_RST#_MDC33

AC97_S DIN027
AC97_S DIN133

+3VS

2

3

32.768KHZ_ 12.5P_1TJS125BJ2A251

12

C528 15 P_0402_50V8J

1 2

+RTCVCC

R221 1M_0402_5%

C231

10P_0402_25V8K@

NC

NC

12

9/16

CLK_PCIE_SATA#15
CLK_PCIE_SATA15

IN

OUT

R202

1 2

10_0402_5%@

1 2

1 2

1 2

1 2

HDD_L ED#33

1

4

12

12

12
12

12

12

SATA CONN

C737 3900P_0402_50V7K

1 2

SATA_TXP0_C SATA_TXP0

C738 3900P_0402_50V7K

1 2

SATA_TXN0SATA_TXN0_C

Near ICH7(U26) side.

A A

SATA_RXN0_C

SATA_RXP0_C

C739 3900P_0402_50V7K

1 2

C740 3900P_0402_50V7K

1 2

Near Device(JP23) side.

SATA_RXN0

SATA_RXP0

OCTEK_SAT- 22DE1G_NR SUYIN_12705 9FR022S305ZL

JP23

GND

GND

GND

GND
GND
GND

GND

Reserved

GND

1

SATA_TXP0

2

A+

A-

B-

B+

V33
V33
V33

V5
V5
V5

V12
V12
V12

SATA_TXN0

3
4

SATA_RXN0

5

SATA_RXP0

6
7

8
9

7/29

10
11
12
13
14
15
16
17
18
19
20
21
22

+5VS

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

+5VS

C904

10U_0805_10V4Z

0.1U_0402_16 V4Z

1

2

1

1

C554

2

C913

2

0.1U_0402_16 V4Z

1

C556

2

0.1U_0402_16 V4Z

Pleace near HD CONN (JP23)

2006/02/27 2007/02/27

Compal Secret Data

Deciphered Date

ZZZ 1

PCB-MB

Title

Size Docume nt Number Re v

2

Date : Sheet of

Compal Electronics, Inc.

LA-3031P

BATT1

45@

CR2025 RTC BATTERY

ICH7-M(2/4)

1

19 49Tuesd ay, Febru ary 28, 2006

0.5

5

4

3

2

1

Pla ce clos ely pin B2 Place clo sely pin AC1

12

R772

@

1

C742

2

12

+3VALW

LOW_BAT# 32

R78610K_0402_5%

R789

100K_0402_5%@

LOM_LOW_PWR 24

CABLE_DETECT 24,25

1 2

RP55

4 5
3 6
2 7
1 8

R808

1 2

10K_0402_5%

R810

1 2

10K_0402_5%

R812

1 2

10K_0402_5%

CLK_14M_I CH

10_0402_5%

4.7P_0402_50V8C@

12

+3VL

12

USB_OC#5 29

R546
10K_0402_5%

7/21

+3VALW

+3VALW

R775

LOM_PCIE_WAKE#24

21

10K_0402_5%

PCIE_WAKE #26

+3VS

12

ISO_PREP#PREP#

9/29

PM_POK7,32

R187
10K_0402_5%

D D

+3VS

R787

R791

C C

B B

A A

+3VALW

R799

R800

R803

R804

R795

R1033

11/10

THERM_SCI#

1 2

10K_0402_5%@

1 2

1 2

1 2

1 2

1 2

1 2

1 2

11/24

11/23

10/11

PREP#25,34

SIRQ

10K_0402_5%

PM_CLKRU N# THERM_SCI#

8.2K_0402_5%

PANEL_FLI P#

10K_0402_5%

LINKALERT#

10K_0402_5%

XDP_DBRESET# PWRO K_ICH7

10K_0402_5%

OCP#

10K_0402_5%

LID_SW #

10K_0402_5%

+3VALW

R522

100K_0402_5%

D35

1 2

CH751H-40 _SC76

R776
10K_0402_5%

1 2

1 2

11/18

+3VALW

BSS138_SOT23

V_3P3_LAN

R796

1 2

0_0402_5%

VGATE7,15,4 3

1 2
1 2

PCIE_TXN124

PCIE_TXP124

PCIE_TXN226

PCIE_TXP226

PCIE_RXN434
PCIE_RXP434
PCIE_TXN434

PCIE_TXP434

8/18

+3VALW

R809

1 2

10K_0402_5%SPI@

R811

1 2

10K_0402_5%SPI@

R814

1 2

10K_0402_5%SPI@

R809 ,R811 and R81 4 shoul d

L

be plac ed clo se to U28 .

R788

1K_0402_5%

1 2

D

S

Q77

G

2

R8010_0402_5%

R8020_0402_5%@

PCIE_RXN124
PCIE_RXP124

PCIE_RXN226
PCIE_RXP226

SPI_CS#

SPI_SI

SPI_SO

ICH_SMBC LK4,13,14, 15,24,26

ICH_SMBDATA4, 13,14,15,24,26

13

11/17

2.2K_0402_5%

+3VALW

XDP_DBRESET#4

PM_BMBUSY#7

H_STP_CPU#15

DIG_RESET#17

11/15

9/14

PM_CLKRUN #22,30,31,32

THERM_SCI#4

+3VALW

RUNS CI_EC#32

R797 10K_0402_5%

11/15

7/22

R806/R807 sho uld be pl aced

L

L

less than 100 m ils fr om U28 .

SPI_CLK31
SPI_CS#31

SPI_SO31

SPI_CLK
SPI_CS#

SPI_SI

SPI_SI31

SPI_SO

SB_SPKR27
LPC_PD#31, 32

H_STP_PCI#15

DIGI_SLEE P17

FWH_W P#31

FWH_TBL#31

LP_EN#24

7/21

USB_OC#5_ R29

11/14

1 2

+3VALW

12

R773

R780

8.2K_0402_5%

OCP#4 ,44

T52PAD

SIRQ22, 30,31,32

1 2

C7430.1U_0402_16 V4Z

12

C7440.1U_0402_16 V4Z

12

C7450.1U_0402_16 V4Z

12

C7460.1U_0402_16 V4Z

12

C7470.1U_0402_16 V4Z

12

C7480.1U_0402_16 V4Z

12

R806

1 2

R807

1 2

12

R774

2.2K_0402_5%

ICH_SMBC LK
ICH_SMBDATA
LINKALERT#
ICH_SM LINK0
ICH_SM LINK1

ICH _RI#

SB_SPKR
LPC_PD#
XDP_DBRESET#

PM_BMBUSY#

OCP#

H_STP_PCI#
H_STP_CPU#

DIG_RESET#

DIGI_SL EEP

PM_CLKRU N#

FWH_W P#
FWH_TBL#

ICH_PC IE_WAKE#
SIRQ

PWRO K_ICH7

RUNS CI_EC#
ISO_PREP#

LP_EN#

PCIE_RXN1
PCIE_RXP1
PCIE_C_TXN1
PCIE_C_TXP1

PCIE_RXN2
PCIE_RXP2
PCIE_C_TXN2
PCIE_C_TXP2

PCIE_RXN4
PCIE_RXP4
PCIE_C_TXN4
PCIE_C_TXP4

47_0402_5%SPI@

47_0402_5%SPI@

USB_OC#0
USB_OC#1
USB_OC#2
USB_OC#3
USB_OC#4
USB_OC#5 _R
USB_OC#6
USB_OC#7

R773,R774 cha nge from 2.2Kohm to 10 Kohm

L

when Q75, Q76, R781,R 782 stu ffed.

U28C

C22

SMBCLK

B22

SMBDATA

A26

LINKALERT#

B25

SMLINK0

A25

SMLINK1

A28

RI#

A19

SPKR

A27

SUS_STAT#

A22

SYS_RST#

AB18

GPIO0 / BM_BUSY#

B23

GPIO11 / SMBALERT#

AC20

GPIO18 / STPPCI#

AF21

GPIO20 / STPCPU#

A21

GPIO26

B21

GPIO27

E23

GPIO28

AG18

GPIO32 / CLKRUN#

AC19

GPIO33 / AZ_DOCK_EN#

U2

GPIO34 / AZ_DOCK_RST#

F20

WAKE#

AH21

SERIRQ

AF20

THRM#

AD22

VRMPWRGD

AC21

GPIO6

AC18

GPIO7

E21

GPIO8

82801GHM QK65 B0_BGA652

U28D

F26

PERn1

F25

PERp1

E28

PETn1

E27

PETp1

H26

PERn2

H25

PERp2

G28

PETn2

G27

PETp2

K26

PERn3

K25

PERp3

J28

PETn3

J27

PETp3

M26

PERn4

M25

PERp4

L28

PETn4

L27

PETp4

P26

PERn5

P25

PERp5

N28

PETn5

N27

PETp5

T25

PERn6

T24

PERp6

R28

PETn6

R27

PETp6

R2

SPI_CLK

P6

SPI_CS#

P1

SPI_ARB

P5

SPI_MOSI

P2

SPI_MISO

D3

OC0#

C4

OC1#

D5

OC2#

D4

OC3#

E5

OC4#

C3

OC5# / GPIO29

A2

OC6# / GPIO30

B3

OC7# / GPIO31

82801GHM QK65 B0_BGA652

PCI-EXPRESS

SPI

USB

SMB

SYS

GPIO

GPIO

DIRECT MEDIA INT ERFACE

DMI_ZCOMP

DMI_IRCOMP

SATA

DMI0RXN
DMI0RXP
DMI0TXN

DMI0TXP

DMI1RXN
DMI1RXP
DMI1TXN

DMI1TXP

DMI2RXN
DMI2RXP
DMI2TXN

DMI2TXP

DMI3RXN
DMI3RXP
DMI3TXN

DMI3TXP

DMI_CLKN
DMI_CLKP

USBP0N

USBP0P

USBP1N

USBP1P

USBP2N

USBP2P

USBP3N

USBP3P

USBP4N

USBP4P

USBP5N

USBP5P

USBP6N

USBP6P

USBP7N

USBP7P

USBRBIAS#

USBRBIAS

GPIO21 / SATA0GP
GPIO19 / SATA1GP
GPIO36 / SATA2GP
GPIO37 / SATA3GP

GPIO

Clocks

GPIO16 / DPRSLPVR

TP0 / BATLOW#

POWER MGT

GPIO35 / SATAREQ#

V26
V25
U28
U27

Y26
Y25
W28
W27

AB26
AB25
AA28
AA27

AD25
AD24
AC28
AC27

AE28
AE27

C25
D25

F1
F2
G4
G3
H1
H2
J4
J3
K1
K2
L4
L5
M1
M2
N4
N3

D2
D1

CLK14
CLK48

SUSCLK

SLP_S3#
SLP_S4#
SLP_S5#

PWROK

PWRBTN#

LAN_RST#

RSMRST#

GPIO9
GPIO10
GPIO12
GPIO13
GPIO14
GPIO15
GPIO24
GPIO25

GPIO38
GPIO39

AF19
AH18
AH19
AE19

AC1
B2

C20

B24
D23
F22

AA4

AC22

C21

C23

C19

Y4

E20
A20
F19
E19

LANLINK_STATUS#_SB

R4
E22
R3
D20
AD21
AD20
AE20

DMI_RXN0
DMI_RXP0
DMI_TXN0
DMI_TXP0

DMI_RXN1
DMI_RXP1
DMI_TXN1
DMI_TXP1

DMI_RXN2
DMI_RXP2
DMI_TXN2
DMI_TXP2

DMI_RXN3
DMI_RXP3
DMI_TXN3
DMI_TXP3

CLK_PC IE_ICH#
CLK_ PCIE_ICH

DMI_IRCO MP

USB20_N0
USB20_P0

USB20_N2
USB20_P2
USB20_N3
USB20_P3
USB20_N4
USB20_P4
USB20_N5
USB20_P5
USB20_N6
USB20_P6
USB20_N7
USB20_P7

USBRBI AS

1 2

CLK_14M_I CH
CLK_48M_I CH

ICH_ SUSCLK

SLP_S3#
SLP_S4#
SLP_S5#

PM_POK

DPRSLP VR

ICH_LOW_BAT #

ON/OFF BTN#

PLT_RST#

PM_RSMRST#

R790

1 2

CB_IN #
PANEL_FLI P#
LID_SW #

BT_OFF
NPCI_RST #

1 2

R946 0_0402_5%@

R805 24.9_0402_1%

1 2

R813 22.6_0402_1%

1 2

Within 5 00 m ils

HDD_HA LTED 33

R779
100_0402_5%

CLK_14M_ICH 15
CLK_48M_ICH 15

T15 P AD

SLP_S3# 24,26,27, 28,32,34,35,39,4 1,42
SLP_S4# 41
SLP_S5# 35,41

1 2

DPRSLPV R 7,43

ON/OFF BTN# 33

PLT_RST# 7,17, 18,22,24,26,30,3 1,32

PM_RSMRST# 32

10K_0402_5%

T51 P AD

PANEL_FLI P# 33

LID_SW # 9,33
LANLINK_STATUS#_SB 24

T16 P AD

XMIT_OFF_R# 26
BT_OFF 29
NPCI_RST # 30

T45 P AD

DOCK _ID 34

DMI_RXN0 7
DMI_RXP0 7
DMI_TXN0 7
DMI_TXP0 7

DMI_RXN1 7
DMI_RXP1 7
DMI_TXN1 7
DMI_TXP1 7

DMI_RXN2 7
DMI_RXP2 7
DMI_TXN2 7
DMI_TXP2 7

DMI_RXN3 7
DMI_RXP3 7
DMI_TXN3 7
DMI_TXP3 7

CLK_PC IE_ICH# 15
CLK_P CIE_ICH 15

Within 5 00 m ils

USB20_N0 29
USB20_P0 29

USB20_N2 17
USB20_P2 17
USB20_N3 29
USB20_P3 29
USB20_N4 29
USB20_P4 29
USB20_N5 29
USB20_P5 29
USB20_N6 34
USB20_P6 34
USB20_N7 34
USB20_P7 34

+1.5VS

11/14

7/13

9/12

L

11/14

CLK_48M_I CH

12

R771

10_0402_5%

@

1

C741

4.7P_0402_50V8C@

2

R784

R783
10K_0402_5%

11/14

9/14

R78 9 need be rem ove d w hen ICH7M ES2 sam ples used ,
but nee d b e s tuffed wh en I CH7M ES1 sam ples used .

8.2K_0402_5%

D44

2 1

CH751H-40 _SC76

12

R794 0_ 0402_5%@

J7

2 1

PAD-SH ORT 2x2m

DPRSLP VR

11/14

USB_OC#5 _R

1

2

11/14

R545

1 2

C96

1K_0402_5%

1000P_0402_50V7K

USB_OC#3
USB_OC#0
USB_OC#1
USB_OC#7

7/21

USB_OC#4

USB_OC#2

USB_OC#6

10K_1206_8P4R_5%

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/02/27 2007/02/27

Compal Secret Data

Deciphered Date

Title

Size Docume nt Number Re v

2

Date : Sheet of

Compal Electronics, Inc.

ICH7-M(3/4)

LA-3031P

20 49Tuesd ay, Febru ary 28, 2006

1

0.5

5

4

3

2

1

ICH_ V5REF_R UN

C753

11/23

C775

10U_0805_10V4Z

+3VS

+1.5VS

C784

0.1U_0402_16 V4Z

+1.5VS

1

+

C754

2

0.1U_0402_16 V4Z

+1.5VS_DMIPLL

1

1

C776

2

2

.01U_0402_16V7K

1

C779

2

0.1U_0402_16 V4Z

1

2

1

2

Pla ce clos ely pi n
D28,T28 ,AD28.

Pla ce clos ely pin AG5 .

Pla ce clos ely pin AG9 .

D D

R816

100_0402_5%

10_0402_5%

C C

B B

A A

R817

12

12

+3VS+5VS

21

1

2

+3VALW+5VALW

21

1

2

D45

CH751H-40 _SC76

ICH_ V5REF_R UN

C757

0.1U_0402_ 16V4Z

D46

CH751H-40 _SC76

ICH_V5 REF_SUS

C764

0.1U_0402_ 16V4Z

+1.5VS

220U_D2_2VK _R9

1

C758

0.1U_0402_ 16V4Z

2

Pla ce clo sely pin AG28 wit hin 1 00ml is.

R818

1 2

0.5_0805_1%

0.1U_0402_ 16V4Z

+1.5VS_DMIPLLR

+1.5VS

+3VALW

C782

1 2

0_0805_5%

1

C778

2

1

2

R819

0.1U_0402_16 V4Z

0.1U_0402_16 V4Z

1

C755

2

0.1U_0402_ 16V4Z

0.1U_0402_16 V4Z

+1.5VS

C777

0.1U_0402_ 16V4Z

+1.5VS

C781

1U_0603_10V4Z

T20 PAD
T21 PAD

+3VALW

ICH_V5 REF_SUS

1

C756

2

+3VS

1

C768

2

+1.5VS_DMIPLL

1

2

1

2

ICH_AA 2
ICH _Y7

U28F

G10

V5REF[1]

AD17

V5REF[2]

F6

V5REF_Sus

AA22

Vcc1_5_B[1]

AA23

Vcc1_5_B[2]

AB22

Vcc1_5_B[3]

AB23

Vcc1_5_B[4]

AC23

Vcc1_5_B[5]

AC24

Vcc1_5_B[6]

AC25

Vcc1_5_B[7]

AC26

Vcc1_5_B[8]

AD26

Vcc1_5_B[9]

AD27

Vcc1_5_B[10]

AD28

Vcc1_5_B[11]

D26

Vcc1_5_B[12]

D27

Vcc1_5_B[13]

D28

Vcc1_5_B[14]

E24

Vcc1_5_B[15]

E25

Vcc1_5_B[16]

E26

Vcc1_5_B[17]

F23

Vcc1_5_B[18]

F24

Vcc1_5_B[19]

G22

Vcc1_5_B[20]

G23

Vcc1_5_B[21]

H22

Vcc1_5_B[22]

H23

Vcc1_5_B[23]

J22

Vcc1_5_B[24]

J23

Vcc1_5_B[25]

K22

Vcc1_5_B[26]

K23

Vcc1_5_B[27]

L22

Vcc1_5_B[28]

L23

Vcc1_5_B[29]

M22

Vcc1_5_B[30]

M23

Vcc1_5_B[31]

N22

Vcc1_5_B[32]

N23

Vcc1_5_B[33]

P22

Vcc1_5_B[34]

P23

Vcc1_5_B[35]

R22

Vcc1_5_B[36]

R23

Vcc1_5_B[37]

R24

Vcc1_5_B[38]

R25

Vcc1_5_B[39]

R26

Vcc1_5_B[40]

T22

Vcc1_5_B[41]

T23

Vcc1_5_B[42]

T26

Vcc1_5_B[43]

T27

Vcc1_5_B[44]

T28

Vcc1_5_B[45]

U22

Vcc1_5_B[46]

U23

Vcc1_5_B[47]

V22

Vcc1_5_B[48]

V23

Vcc1_5_B[49]

W22

Vcc1_5_B[50]

W23

Vcc1_5_B[51]

Y22

Vcc1_5_B[52]

Y23

Vcc1_5_B[53]

B27

Vcc3_3[1]

AG28

VccDMIPLL

AB7

Vcc1_5_A[1]

AC6

Vcc1_5_A[2]

AC7

Vcc1_5_A[3]

AD6

Vcc1_5_A[4]

AE6

Vcc1_5_A[5]

AF5

Vcc1_5_A[6]

AF6

Vcc1_5_A[7]

AG5

Vcc1_5_A[8]

AH5

Vcc1_5_A[9]

AD2

VccSATAPLL

AH11

Vcc3_3[2]

AB10

Vcc1_5_A[10]

AB9

Vcc1_5_A[11]

AC10

Vcc1_5_A[12]

AD10

Vcc1_5_A[13]

AE10

Vcc1_5_A[14]

AF10

Vcc1_5_A[15]

AF9

Vcc1_5_A[16]

AG9

Vcc1_5_A[17]

AH9

Vcc1_5_A[18]

E3

VccSus3_3[19]

C1

VccUSBPLL

AA2

VccSus1_05/VccLAN1_05[1]

Y7

VccSus1_05/VccLAN1_05[2]

V5

VccSus3_3/VccLAN3_3[1]

V1

VccSus3_3/VccLAN3_3[2]

W2

VccSus3_3/VccLAN3_3[3]

W7

VccSus3_3/VccLAN3_3[4]

82801GHM QK65 B0_BGA652

1

C785

0.1U_0402_16 V4Z

2

Vcc1_05[1]
Vcc1_05[2]
Vcc1_05[3]
Vcc1_05[4]
Vcc1_05[5]
Vcc1_05[6]
Vcc1_05[7]
Vcc1_05[8]

Vcc1_05[9]
Vcc1_05[10]
Vcc1_05[11]
Vcc1_05[12]
Vcc1_05[13]
Vcc1_05[14]
Vcc1_05[15]
Vcc1_05[16]
Vcc1_05[17]
Vcc1_05[18]
Vcc1_05[19]
Vcc1_05[20]

Vcc3_3 / VccHDA

VccSus3_3/VccSusHDA

V_CPU_IO[1]
V_CPU_IO[2]
V_CPU_IO[3]

Vcc3_3[3]
Vcc3_3[4]
Vcc3_3[5]
Vcc3_3[6]
Vcc3_3[7]
Vcc3_3[8]

Vcc3_3[9]
Vcc3_3[10]
Vcc3_3[11]

Vcc3_3[12]
Vcc3_3[13]
Vcc3_3[14]
Vcc3_3[15]
Vcc3_3[16]
Vcc3_3[17]
Vcc3_3[18]
Vcc3_3[19]
Vcc3_3[20]
Vcc3_3[21]

VccRTC

VccSus3_3[1]

VccSus3_3[2]
VccSus3_3[3]
VccSus3_3[4]
VccSus3_3[5]
VccSus3_3[6]

VccSus3_3[7]
VccSus3_3[8]

VccSus3_3[9]
VccSus3_3[10]
VccSus3_3[11]
VccSus3_3[12]
VccSus3_3[13]
VccSus3_3[14]
VccSus3_3[15]
VccSus3_3[16]
VccSus3_3[17]
VccSus3_3[18]

Vcc1_5_A[19]

Vcc1_5_A[20]

Vcc1_5_A[21]

Vcc1_5_A[22]

Vcc1_5_A[23]

Vcc1_5_A[24]

Vcc1_5_A[25]

VccSus1_05[1]

VccSus1_05[2]
VccSus1_05[3]

Vcc1_5_A[26]

Vcc1_5_A[27]

Vcc1_5_A[28]

Vcc1_5_A[29]

Vcc1_5_A[30]

L11
L12
L14
L16
L17
L18
M11
M18
P11
P18
T11
T18
U11
U18
V11
V12
V14
V16
V17
V18

U6

R7

AE23
AE26
AH26

AA7
AB12
AB20
AC16
AD13
AD18
AG12
AG15
AG19

A5
B13
B16
B7
C10
D15
F9
G11
G12
G16

W5

P7

A24
C24
D19
D22
G19

K3
K4
K5
K6
L1
L2
L3
L6
L7
M6
M7
N7

AB17
AC17

T7
F17
G17

AB8
AC8

K7

C28
G20

A1
H6
H7
J6
J7

+VCCP

0.1U_0402_16 V4Z

1

C751

C752

2

1U_0603_10V4Z

1

C765

2

0.1U_0402_16 V4Z

1

C769

0.1U_0402_16 V4Z

2

1

C773

0.1U_0402_16 V4Z

2

+1.5VS

1 2

C780 0.1U_0402_16 V4Z

ICH_ K7

ICH_ C28
ICH_G 20

+1.5VS

1

C783

0.1U_0402_16 V4Z

2

1

1

+

C749

2

2

220U_D2_2VK_R9

+3VS

+3VS

1

C762

0.1U_0402_16 V4Z

2

1

1

C766

2

2

0.1U_0402_16 V4Z

1

C770

0.1U_0402_ 16V4Z

2

1

C774

0.1U_0402_ 16V4Z

2

+3VS

+VCCP

C760

1 2

0.1U_0402_16 V4Z

1 2

C761

0.1U_0402_16 V4Z

1 2

C763

4.7U_0805_10 V4Z

+3VS

C767

0.1U_0402_16 V4Z

+3VALW

C771

+3VALW

T17PAD

T18PAD
T19PAD

1

C759

0.1U_0402_16 V4Z

2

+RTCVCC

1

1

C772

2

2

0.1U_0402_16 V4Z

0.1U_0402_16 V4Z

U28E

A4

VSS[0]

A23

VSS[1]

B1

VSS[2]

B8

VSS[3]

B11

VSS[4]

B14

VSS[5]

B17

VSS[6]

B20

VSS[7]

B26

VSS[8]

B28

VSS[9]

C2

VSS[10]

C6

VSS[11]

C27

VSS[12]

D10

VSS[13]

D13

VSS[14]

D18

VSS[15]

D21

VSS[16]

D24

VSS[17]

E1

VSS[18]

E2

VSS[19]

E4

VSS[21]

E8

VSS[22]

E15

VSS[23]

F3

VSS[24]

F4

VSS[25]

F5

VSS[26]

F12

VSS[27]

F27

VSS[28]

F28

VSS[29]

G1

VSS[30]

G2

VSS[31]

G5

VSS[32]

G6

VSS[33]

G9

VSS[34]

G14

VSS[35]

G18

VSS[36]

G21

VSS[37]

G24

VSS[38]

G25

VSS[39]

G26

VSS[40]

H3

VSS[41]

H4

VSS[42]

H5

VSS[43]

H24

VSS[44]

H27

VSS[45]

H28

VSS[46]

J1

VSS[47]

J2

VSS[48]

J5

VSS[49]

J24

VSS[50]

J25

VSS[51]

J26

VSS[52]

K24

VSS[53]

K27

VSS[54]

K28

VSS[55]

L13

VSS[56]

L15

VSS[57]

L24

VSS[58]

L25

VSS[59]

L26

VSS[60]

M3

VSS[61]

M4

VSS[62]

M5

VSS[63]

M12

VSS[64]

M13

VSS[65]

M14

VSS[66]

M15

VSS[67]

M16

VSS[68]

M17

VSS[69]

M24

VSS[70]

M27

VSS[71]

M28

VSS[72]

N1

VSS[73]

N2

VSS[74]

N5

VSS[75]

N6

VSS[76]

N11

VSS[77]

N12

VSS[78]

N13

VSS[79]

N14

VSS[80]

N15

VSS[81]

N16

VSS[82]

N17

VSS[83]

N18

VSS[84]

N24

VSS[85]

N25

VSS[86]

N26

VSS[87]

P3

VSS[88]

P4

VSS[89]

P12

VSS[90]

P13

VSS[91]

P14

VSS[92]

P15

VSS[93]

P16

VSS[94]

P17

VSS[95]

P24

VSS[96]

P27

VSS[97]

82801GHM QK65 B0_BGA652

VSS[98]

VSS[99]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
VSS[159]
VSS[160]
VSS[161]
VSS[162]
VSS[163]
VSS[164]
VSS[165]
VSS[166]
VSS[167]
VSS[168]
VSS[169]
VSS[170]
VSS[171]
VSS[172]
VSS[173]
VSS[174]
VSS[175]
VSS[176]
VSS[177]
VSS[178]
VSS[179]
VSS[180]
VSS[181]
VSS[182]
VSS[183]
VSS[184]
VSS[185]
VSS[186]
VSS[187]
VSS[188]
VSS[189]
VSS[190]
VSS[191]
VSS[192]
VSS[193]
VSS[194]

P28
R1
R11
R12
R13
R14
R15
R16
R17
R18
T6
T12
T13
T14
T15
T16
T17
U4
U12
U13
U14
U15
U16
U17
U24
U25
U26
V2
V13
V15
V24
V27
V28
W6
W24
W25
W26
Y3
Y24
Y27
Y28
AA1
AA24
AA25
AA26
AB4
AB6
AB11
AB14
AB16
AB19
AB21
AB24
AB27
AB28
AC2
AC5
AC9
AC11
AD1
AD3
AD4
AD7
AD8
AD11
AD15
AD19
AD23
AE2
AE4
AE8
AE11
AE13
AE18
AE21
AE24
AE25
AF2
AF4
AF8
AF11
AF27
AF28
AG1
AG3
AG7
AG11
AG14
AG17
AG20
AG25
AH1
AH3
AH7
AH12
AH23
AH27

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/02/27 2007/02/27

Compal Secret Data

Deciphered Date

Title

Size Docume nt Number Re v

2

Date : Sheet of

Compal Electronics, Inc.

ICH7-M(4/4)

LA-3031P

21 49Tuesd ay, Febru ary 28, 2006

1

0.5

A

B

C

D

E

0.1U_0402_ 16V4Z

C788

C792

1U_0603_10V4Z

VCCPP1VCCPW8RSVD

PCI6612ZHK_ PBGA216

+3VS_CBVCCP

1

1

C786

2

2

CHB1608U301_0603

U19

P15

RSVD

FRAME#

DEVSEL#

RI_OUT#/PME#

SUSPEND#

SPKROUT

MFUNC0
MFUNC1
MFUNC2
MFUNC3
MFUNC4
MFUNC5
MFUNC6

VR_EN#

+3VS

R821

0_0805_5%

C787

0.1U_0402_16 V4Z

AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0

PAR

SCL
SDA

12

M1
M2
M3
M6
M5
N1
N2
N3
P3
R1
R2
P5
R3
T1
T2
W4
W7
R8
U8
V8
W9
V9
U9
R9
V10
U10
R10
W11
V11
U11
P11
R11

P2
U5
V7
W10

U7
R6
W5
V5
V6
U6
N5
R7
W6
L3
L2

L1
K3
K5
L5

J5

H3

G1
H5
H2
H1
J1
J2
J3

G2
G3

K2

L72

+VDDPLL+VD D_PLL

PCI_AD 31
PCI_AD 30
PCI_AD 29
PCI_AD 28
PCI_AD 27
PCI_AD 26
PCI_AD 25
PCI_AD 24
PCI_AD 23
PCI_AD 22
PCI_AD 21
PCI_AD 20
PCI_AD 19
PCI_AD 18
PCI_AD 17
PCI_AD 16
PCI_AD 15
PCI_AD 14
PCI_AD 13
PCI_AD 12
PCI_AD 11
PCI_AD 10
PCI_AD 9
PCI_AD 8
PCI_AD 7
PCI_AD 6
PCI_AD 5
PCI_AD 4
PCI_AD 3
PCI_AD 2
PCI_AD 1
PCI_AD 0

PCI_CBE #3
PCI_CBE #2
PCI_CBE #1
PCI_CBE #0

CLK_PCI_P CM
PRST#
GRST#
CB_PME#

FM_LED#

10K_0402_5%

1 2

C793 0.1U_0402_16 V4Z

AD31
AD30
AD29
AD28
AD27
AD26
AD25
AD24
AD23
AD22
AD21
AD20
AD19
AD18
AD17
AD16
AD15
AD14
AD13
AD12
AD11
AD10

C/BE3#
C/BE2#
C/BE1#
C/BE0#

TRDY#

IRDY#

STOP#

IDSEL
PERR#
SERR#

REQ#

GNT#

PCLK
PRST#
GRST#

+3VS

R824 100_0402_5%

R826

R827

43K_0402_5%

PCI_AD 22

12

1 2
1 2

0_0402_5%@

+3VS

R8300_0402_5%

12

R8310_0402_5%

12

R8320_0402_5%

12

R8330_0402_5%

12

R8340_0402_5%

12

R822

12

R835220_0402_5%

12

R836220_0402_5%

12

R837220_0402_5%

12

+SD_3VCC

PCI_PA R 18
PCI_FRAME# 18
PCI_T RDY# 18

PCI _IRDY# 18

PCI_STOP# 18
PCI_DEVSEL # 18

PCI_PE RR# 18
PCI_SE RR# 18,32
PCI_REQ2# 18
PCI_GNT2# 18

CLK_PCI_PC M 15

R825

PCI_RST# 18,23

0_0402_5%

PLT_RST# 7,17, 18,20,24,26,30,3 1,32

PCM_SPK 27

PCI_P IRQC# 18
PCI_P IRQD# 18
PCI_PI RQG# 18

SIRQ 20,30,31, 32

PCI_PI RQE# 18

+3VS

PM_CLKRUN # 20,30,31,32

C38

0.1U_0402_16 V4Z

MC_PWRO N#

22P_0402_50V8J@

C43

1 2

R33 10_0402_5%@

1

C33

4.7U_0805_10 V4Z

2

SD_CMD

SD_WP

PRST#

PCM_SPK

+3VS

R21
10K_0402_5%

1 2

+3VS

C55

12

100P_0402_50V8J

SD_CARD _DET#

SD1
SD0

SD_CLK

SD_CMD
SD3

SD2

TI wor karound

8/1

R957 100K_0402_5%

R958 100K_0402_5%

R828 0_0402_5%

10K_0402_5%@

CB_PME#

1 2

R949

1 2

43K_0402_5%

R279

2N7002_SOT23@

12

12

GRST#

+3VS

12

Q78

S

G

2

+SD_3VCC

13

D

U3

1

GND

2

IN

3

IN

4

EN#

TPS2041BDR_SO8

SA020410030

JP27

MMC_DET#10Wr_Pt_Vss

8

SD4

7

SD3

6

Vss2

5

SDCLK

4

Vdd

3

Vss1

2

SD2

1

SD1

9

SD5

MOLEX_67913-0011

PCI_PME# 18

8
7
6
5

11

12
13
14

+SD_3VCC

R1012100_0402_5%@

RP56

4 5
3 6
2 7
1 8

100_1206_8P4R_5%@

SD_WP

+SD_3VCC

12

10/03

OUT
OUT
OUT
OC#

Vss3
Vss4

Wr_Pt

SD_CMD

SD3
SD2
SD1
SD0

Need c lose to U23B.A7

+3VS_CBPLL

10/6

1 2

1 2

+3VS

0_0805_5%

12

MC_PWRO N#

SD_CARD _DET#

SD_CLK _R
SD_CM D_R
SD3_R
SD2_R
SD1_R
SD0_R

SD_WP

R820

C790

1

1

1

C789

2

2

2

.01U_0402_16V7K

10U_0805_10V4Z

1U_0603_10V4Z

U23B

T18

GND

T19

GND

R13

RSVD

V14

RSVD

W14

RSVD

V13

RSVD

W13

RSVD

W17

RSVD

V16

RSVD

W16

RSVD

V15

RSVD

W15

RSVD

P17

PHY_TEST_MA

R18

RSVD

R19

RSVD

C8

MC_PWR_CTRL_0

F8

MC_PWR_CTRL_1/SM_R/B#

E9

SD_CD#

A8

MS_CD#

B8

SM_CD#

A7

MS_CLK/SD_CLK/SM_EL_WP#

E8

MS_BS/SD_CMD/SM_WE#

B6

MS_DATA3/SD_DAT3/SM_D3

A6

MS_DATA2/SD_DAT2/SM_D2

C7

MS_DATA1/SD_DAT1/SM_D1

B7

MS_SDIO(DATA0)/SD_DAT0/SM_D0

A4

SD_CLK/SM_RE#/SC_GPIO1

C5

SD_CMD/SM_ALE/SC_GPIO2

C6

SD_DAT0/SM_D4/SC_GPIO6

A5

SD_DAT1/SM_D5/SC_GPIO5

B5

SD_DAT2/SM_D6/SC_GPIO4

E6

SD_DAT3/SM_D7/SC_GPIO3

E7

SD_WP/SM_CE#

B4

SM_CLE/SC_GPIO0

F3

SC_CD#

E2

SC_CLK

F5

SC_RST

G6

SC_VCC_5V

E1

SC_DATA

F2

SC_OC#

G5

SC_PWR_CTRL

E3

SC_FCB

D1

SC_RFU

P12

TEST0

C791

P13

P14

U15

VCC

VCC

VCC

PCI6612

1U_0603_10V4Z

AGND

GND

R14

U13

U14

1

2

VR_PORTK1VR_PORT

GND

GND

R17

1

2

K19

+VDDPLL

PCI_A D[0..31]18

PCI_CB E#[0..3]18

1 1

2 2

PCI_ AD[0..31]

PCI_C BE#[0..3]

+3VS

SD_CLK

R823 22_0402_5%

SD_CMD

R1001 0_0402_5%

SD3

R1002 0_0402_5%

SD2

R1003 0_0402_5%

SD1

R1004 0_0402_5%

SD0

R1005 0_0402_5%

R941 4.7K_0402_5%

1 2
1 2
1 2
1 2
1 2
1 2

9/23

3 3

+5VS

+S1_VCC

4 4

R829 0_0402_5%@

R1028 0_04 02_5%

CLK_PCI_P CM

12

R282

10_0402_5%@

1

C348

15P_0402_50V8J@

2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2006/02/27 2007/02/27

Compal Secret Data

Deciphered Date

Title

Size Docume nt Number Re v

D

Date : Sheet of

Compal Electronics, Inc.

TI PCI6612 PCI/CardReader

LA-3031P

22 49Tuesd ay, Febru ary 28, 2006

E

0.5

A

1

1

C794

2

2

0.1U_0402_16 V4Z

0.1U_0402_16 V4Z

1 1

2 2

S1_A16_R

+3VS

1 2

R841 4.7K_0402_5%

CLK_48M_CB

12

R842

3 3

10_0402_5%@

2

C807

10P_0402_50V8J@

1

4 4

9/23

1 2

R983 33_0402_5%

CLK_48M_CB15

CPS

1

C795

2

0.1U_0402_16 V4Z

S1_D10
S1_D9
S1_D1
S1_D8
S1_D0
S1_A0
S1_A1
S1_A2
S1_A3
S1_A4
S1_A5
S1_A6
S1_A25
S1_A7
S1_A24
S1_A17
S1_IOWR #
S1_A9
S1_IOR D#
S1_A11
S1_OE#
S1_CE2#
S1_A10
S1_D15
S1_D7
S1_D13
S1_D6
S1_D12
S1_D5
S1_D11
S1_D4
S1_D3

S1_REG#
S1_A12
S1_A8
S1_CE1#

S1_A13
S1_A23
S1_A15
S1_A20
S1_A21
S1_A19
S1_A14
S1_WAIT#
S1_INPAC K#
S1_WE#
S1_BVD1
S1_WP

S1_R DY#
CPS

CLK_48M_CB

S1_A22
S1_BVD2
S1_RST

S1_CD1#
S1_CD2#
S1_VS1
S1_VS2

C796

S1_A16

1

1

C797

2

2

0.1U_0402_16 V4Z

0.1U_0402_16 V4Z

C10
A10
F11
E11
C11
B13
C13
A14
B14
B15
E14
A16
D19
E17
F15
H19

J17
J15

J18
K15
K17
K18

L15

L18

L19
M17
M18
N19
M15
N17
N18
P19

E13
E18
H18

L17

H14
E19
F17
G18
F19
H15
G19
C12
C14
G17
A12
A11
F18
E12
R12

F1
G15
B12
C15

N15
B11
A13
B16

E10

1

1

C798

2

0.1U_0402_16 V4Z

U23A

CAD31/D10
CAD30/D9
CAD29/D1
CAD28/D8
CAD27/D0
CAD26/A0
CAD25/A1
CAD24/A2
CAD23/A3
CAD22/A4
CAD21/A5
CAD20/A6
CAD19/A25
CAD18/A7
CAD17/A24
CAD16/A17
CAD15/IOWR#
CAD14/A9
CAD13/IORD#
CAD12/A11
CAD11/OE#
CAD10/CE2#
CAD9/A10
CAD8/D15
CAD7/D7
CAD6/D13
CAD5/D6
CAD4/D12
CAD3/D5
CAD2/D11
CAD1/D4
CAD0/D3

CC/BE3#/REG#
CC/BE2#/A12
CC/BE1#/A8
CC/BE0#/CE1#

CPAR/A13
CFRAME#/A23
CIRDY#/A15
CSTOP#/A20
CDEVSEL#/A21
CBLOCK#/A19
CPERR#/A14
CSERR#/WAIT#
CREQ#/INPACK#
CGNT#/WE#
CSTSCHG/BVD1(STSCHG#/RI#)
CCLKRUN#/WP(IOIS16#)
CCLK/A16
CINT#/READY(IREQ#)
GND
CLK_48
CTRDY#/A22
CAUDIO/BVD2(SPKR#)
CRST#/RESET

CCD1#/CD1#
CCD2#/CD2#
CVS1/VS1#
CVS2/VS2#

A_USB_EN#

SA00000X900

1

C800

C799

2

2

0.1U_0402_16 V4Z

B

+S1_VCC+3VS

1

C801

10U_0805_10V4Z

F12

F14

J14

L14

P10

VCCF6VCCF9VCC

VCC

VCCJ6VCC

VCCL6VCC

VCCP6VCCP8VCC

1

2

0.1U_0402_16 V4Z

A15

J19

VCCB

VCCB

C803

C802

2

0.1U_0402_16 V4Z

U12

NC

V12

NC

W12

NC

PCI6612

S1_D2

B10

RSVD/D2
RSVD/A18
RSVD/D14

RSVD/VD0/VCCD1#

XD_CD#/SM_PHYS_WP#

DATA/VD2/VPPD1

CLOCK/VD1/VCCD0#

LATCH/VD3/VPPD0

GNDF7GND

GND

GND

GNDH6GNDK6GND

GND

GNDN6GNDP7GND

F10

F13

G14

P9

K14

M14

PCI6612ZHK_ PBGA216

H17
M19

C4

A3

B9
A9
C9

S1_A18
S1_D14

CB_DAT
CB_CLK
CB_LATCH

R839

R840

C

43K_0402_5%

1 2

1 2

43K_0402_5%@

+3VS

PCI_RST#1 8,22

+S1_VPP

+S1_VCC

Near to PCMCIA slot.

+S1_VCC

1

C353

10U_0805_10V4Z

2

+S1_VPP

1

C344

10U_0805_10V4Z

2

CB_DAT
CB_CLK
CB_LATCH
PCI_RST#

6/22

1

C346

0.1U_0402_ 16V4Z

2

1

C345

0.1U_0402_ 16V4Z

2

D

U42

3

DATA

4

CLOCK

5

LATCH

12

RESET#

15

OC#

21

SHDN#

8

AVPP

19

NC0

9

AVCC

10

AVCC

17

NC1

18

NC2

TPS2220ADBR_SSOP24

+S1_VCC
+S1_VPP

12V
12V

NC3

3.3V

NC4

5V
5V

GND

NC5
NC6
NC7
NC8

S1_D3
S1_D4
S1_D5
S1_D6

S1_D7
S1_CE1#
S1_A10
S1_OE#
S1_A11
S1_A9
S1_A8
S1_A13
S1_A14
S1_WE#
S1_R DY#

S1_A16_R
S1_A15
S1_A12
S1_A7
S1_A6
S1_A5
S1_A4
S1_A3
S1_A2
S1_A1
S1_A0

S1_D0

S1_D1

S1_D2
S1_WP

20
7

14
13

24
2
1

11

23
22
16
6

+3VS

1

+5VS

C804

2

1

C805

2

0.1U_0402_16 V4Z

JP7

1

GND

2

S1_D3

3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
69
71
73
75
77
79
81
83

85
87

S1_CD1#
S1_D4
S1_D5
S1_D6
S1_D7
S1_CE1#
S1_A10

S1_CE2#
S1_OE#

S1_VS1#

S1_A11

S1_IORD#

S1_A9

S1_IOWR#
S1_A8
S1_A13
S1_A14
S1_WE#
S1_IREQ#
S1_VCC
S1_VPP1

S1_VPP2
S1_A16
S1_A15
S1_A12
S1_A7
S1_A6

S1_VS2#

S1_A5

S1_RESET

S1_A4

S1_WAIT#

S1_A3

S1_INPACK#

S1_A2

S1_REG#
S1_A1

S1_SPKR#

S1_A0

S1_STSCHG#
S1_D0
S1_D1
S1_D2
S1_IOIS16#

S1_CD2#
GND
GND
GND
GND
GND
GND
GND
GND
GND

GND
GND

FOX_WZ21131-G2-P4_LT

J5

CARDBUS HOUSING

S1_CD1#

S1_CD2#

0.1U_0402_16 V4Z

35

GND

36
37

S1_D11

38

S1_D12

39

S1_D13

40

S1_D14

41

S1_D15

42
43
44
45
46

S1_A17

47

S1_A18

48

S1_A19

49

S1_A20

50

S1_A21

51

S1_VCC

52
53

S1_A22

54

S1_A23

55

S1_A24

56

S1_A25

57
58
59
60
61
62
63
64

S1_D8

65

S1_D9

66

S1_D10

67
68

GND

70

GND

72

GND

74

GND

76

GND

78

GND

80

GND

82

GND

84

GND

86

GND

88

GND

C357

1 2

100P_0402_50V8J

C21

1 2

100P_0402_50V8J

E

S1_CD1#
S1_D11
S1_D12
S1_D13
S1_D14
S1_D15
S1_CE2#
S1_VS1
S1_IOR D#
S1_IOWR #
S1_A17
S1_A18
S1_A19
S1_A20
S1_A21

S1_A22
S1_A23
S1_A24
S1_A25
S1_VS2
S1_RST
S1_WAIT#
S1_INPAC K#
S1_REG#
S1_BVD2
S1_BVD1
S1_D8
S1_D9
S1_D10
S1_CD2#

+S1_VCC
+S1_VPP

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2006/02/27 2007/02/27

Compal Secret Data

Deciphered Date

Title

Size Docume nt Number Re v

D

Date : Sheet of

Compal Electronics, Inc.

TI PCI6612 CB/NewCard/SmartCard

LA-3031P

23 49Tuesd ay, Febru ary 28, 2006

E

0.5

5

R10130_0402_5%@

7/11

R10304.7K_0402_5%
R10314.7K_0402_5%

V_3P3_LAN+3VALW

10K_0402_5%

S

V_3P3_LAN

2

1

R860

1 2
1 2

1 2

5753_GPIO1

ICH_SMBC LK_LAN
ICH_SMBDATA _LAN

5753_EECLK
5753_EEDAT

LAN_SI
LAN_SO

LAN_SCLK

LAN_CS#

V_3P3_LAN

12

R1043

LANLINK_STATUS#

LANLINK_STATUS#

LAN_ACT#

R1046

1 2

10K_0402_5%

XTALO

XTALI

C825

27P_0402_50V8J

12

R861

1K_0402_5%

1K_0402_5%

7/11

U53

4

CS#

3

RESET#

2

SCK

1

SI

AT45DB011B-SI_SO8

@

12

4.7K_0402_5%
R852

V_3P3_LAN

12

R862

R10140_0402_5%@

12

1K_0402_5%

WP#

VCC

GND

SO

ICH_SMBC LK4,13,14, 15,20,26

ICH_SMBDATA4, 13,14,15,20,26

D D

V_3P3_LAN

10/11

11/24

R1044

C C

10K_0402_5%

LANLINK_STATUS#_SB20

LANLINK_STATUS#25,34

R849
10K_0402_5%

1 2
1 2

10/04

V_3P3_LAN

10K_0402_5%

12

R1042

12

2

G

1 3

D

Q108 2N7002_SOT23

R1045

1 2

0_0402_5%@

LAN_ACT#25,34

11/24

12

R857 200_0402_1%

Y5

1 2

B B

A A

4.7K_0402_5%@

25MHZ_16P_XSL025000FK1H

2

C824

27P_0402_50V8J

1

C827

12

0.1U_0402_16 V4Z

U44

1

A0

2

A1

3

NC

4

GND

AT24C64AN-1 0SU-2.7_SO8

R964

12

10/6

VCC

WP

SCL

SDA

12

R92

@

4.7K_0402_5%

LAN_CS#

8
7
6
5

LAN_SCLK

V_3P3_LANV_3P3_LAN

5

5753_GPIO1
5753_EECLK
5753_EEDAT

ICH_SMBC LK_LAN
ICH_SMBDATA _LAN

U6A

J10

GPIO0_TST_CLKOUT

J12

GPIO1

D9

SMB_CLK

D8

SMB_DATA

H10

EECLK

J11

EEDATA

F11

SI

E10

SO

D10

SCLK

D11

CS#

5/20

H2

PWR_IND#

J2

ATTN_IND#

B3

ATTN_BTTN#

B10

LINKLED#

C10

SPD100LED#

B11

SPD1000LED#

C9

TRAFFICLED#

N10

XTALO

M10

XTALI

BCM5753KFBG C1_FPBGA196~D

5
6
7

LAN_SILAN_SO

8

4

BCM5753

Misc

Hot Plug

Support

LED

Clock

Lay out No tice : No h igh
sp eed sign al sh ou ld b e
rou ted near RD AC o r on
adj acent layer to RDAC

4

Media

Power

Contro l

Control

Regulator

PCI-ETEST

Bias

NIC_ PD_N

TRD3+

TRD3-

TRD2+

TRD2-

TRD1+

TRD1-

TRD0+

TRD0-

LOW_PWR

REGSUP12
REGCTL12
REGSEN12

REGOUT25

REGSUP25

PCIE_TXDN

PCIE_TXDP

PCIE_RXDN

PCIE_RXDP

WAKE#

REFCLK-

REFCLK+

REFCLK_SEL

PCIE_TST

PERST#

TCK

TDO
TMS

TRST#

RDAC

TDI

11/22

LAN_TX3+

C12

LAN_TX3-

C13

LAN_TX2+

D12

LAN_TX2-

D13

LAN_TX1+

E12

LAN_TX1-

E13

LAN_TX0+

F12

LAN_TX0-

F13

LOM_LOW_PWR

J5

REGSUP12

L13

VAUX_1.2_CTL

K12
K13

N13

M13

PCIE_C_RX N1

N4

PCIE_C_RXP1

M4

M8

N8

LAN_WAKE#

B5

CLK_PCIE_LOM#

M6

CLK_PCIE_LOM

N6
C4

R854 4.7K_0402_5%

D7

PLT_RST#_LAN

C2

C6
G4
C5
F4
E5

B9

1 2

0.1U_0402_16 V4Z

LAN_TX3+ 25
LAN_TX3- 25
LAN_TX2+ 25
LAN_TX2- 25
LAN_TX1+ 25
LAN_TX1- 25
LAN_TX0+ 25
LAN_TX0- 25

10/7

1 2

R1029 4.7K_0402 _5%

C817

R856

4.7K_0402_5%@

8/15

12

9/27

C818

1 2

1 2

V_3P3_LAN

12

R1035
10K_0402_5%

0.1U_0402_16 V4Z

0.1U_0402_16 V4Z

1 2

R858

1.21K_0402_1%

10/04

0_0402_5%

@

D63 1N 4148_SOD80

1 2

1 2

R1024121K_0402_1%

2

1

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

PLT_RST#7,17,18, 20,22,26,30,31,3 2

V_1P2_LAN

V_2P5_LAN

V_3P3_LAN

PCIE_TXN1 20

PCIE_TXP1 20

5/20

11/15

V_3P3_LAN +3VS

R1021

2

C1036

Issued Date

3

R1006

0_0402_5%

@

PLT_RST#_LAN

NIC_ PD25

PCIE_RXN1 20

PCIE_RXP1 20

CLK_PCIE_LOM# 15
CLK_PCIE_LOM 15

12

R855

4.7K_0402_5%

R1022

0_0402_5%

1 2

1 2

5

P

O4I

R1025 0_04 02_5%

1

NC

G

SN74LVC1G17DBVR_SOT 23-5

3

U54

3

SI2301BDS_SOT23

S

Q100

12

NIC _PD

11/22

9/27

D

1 3

ADP_PRES32,3 9,40

10/04

G

11/17

2

0.1U_0402_16 V4Z@

SLP_S3#20,26,27, 28,32,34,35,39,4 1,42

10K_0402_5%

R1017

0_0402_5%

@

1

C1044

2

220K_0402_5%

0_0402_5%@

Q81

10/11

R853

LAN_WAKE#

12

NIC _PD

11/15

R1007

R850

2

G

V_3P3_LAN

12

V_3P3_LAN

2

G

LOM_LOW_PWR20

12

2 1

12

13

D

S

13

D

2N7002_SOT23

S

13

D

2

G

S

11/22

1 3

D

Q103

1 2

NIC_ PD_N

13

D

Q104

G

S

12

R1020

10K_0402_5%

@

NIC_ PD#

13

D

Q105

@

S

11/22

@

RB751V_SOD323
D64

9/27

Q80

LP_EN#

2

G

2N7002_SOT23

Q83
2N7002_SOT23

NIC _PD

2

G

S

BSS84_SOT23

@

R10150_0402_5%

1 2

100K_0402_5%@

BSS84_SOT23@

2

@

1 2

1 2

0_0402_5%@

2N7002_SOT23

11/22

12

2006/02/27 2007/02/27

CLKREQA# 15

CKT No tice : CABLE IN , CABLE_DET ECT=0

CABLE OUT, C ABLE_DETECT=1

CABLE_DETECT20, 25

Compal Secret Data

Deciphered Date

2

+3VALW

12

R845

4.7K_0402_5%

R848

4.7U_0805_ 10V4Z

R1016

0_0402_5%

R1018

R1019

LOM_LOW_PWR

SN74LVC1G17DBVR_SOT23-5@

2

J8

PAD-NO SHORT 2x2m

S

Q79

SI2301BDS_SOT23

12

47K_0402_5%

L

REGSUP12

2

2

C813

1

1

11/18

V_3P3_LAN

+3VS

10/7

U43

1

10/7

CABLE_DETECT

C829

0.1U_0402_16 V4Z

1

21

D

13

G

2

Mus t hav in g m axi miz ed
copper unde r pi n 2 & 4 of Q82

BCP69_SOT223
Q82

3

C814

0.1U_0402_16 V4Z

VAUX_1.2_CTL

LOM_PCIE_WAKE# 20

Lay out No tice : Plac e as close
ch ip a s po ssi ble.

2

2

C809

C808

1

1

0.1U_0402_16 V4Z

4.7U_0805_10 V4Z

V_1P2_LAN V_3P3_LAN

4
2

2

C815

1

1

0.1U_0402_16 V4Z

4.7U_0805_10 V4Z

L

V_2P5_LAN

C822

0.1U_0402_16 V4Z

2

2

C811

1

V_3P3_LAN

C819

1

0.1U_0402_16 V4Z

2

1

C812

0.1U_0402_16 V4Z

2

C820

0.1U_0402_16 V4Z

1

C810

0.1U_0402_16 V4Z

1

C816

10U_0805_10V4Z

2

Pla ce clos e U 6 pin M13

10U_0805_10V4Z@

2

1

1

1

+

C821

C823

100U_B2_6.3VM_R45

2

2

Pla ce close U6 pin N13

L

11/22

V_3P3_LAN

C826

1 2

0.1U_0402_16 V4Z@

5

P

O4I
NC

G

3

+3VALW

12

R865
10K_0402_5%

1

2

Size Docume nt Number Re v

Date : Sheet of

2

Title

R859

1 2

100K_0402_5%@

1

C828

0.1U_0402_16 V4Z

@

2

R867

1 2

0_0402_5%@

D

S

Compal Electronics, Inc.

LA-3031P

11/22

V_3P3_LAN

12

R1036 10K_0402_5%@

12

R866 10K_0402_5%

R1037 0_0402_5%

1 2

13

Q86

LP_EN#

2

G

2N7002_SOT23

BCM5753M

1

+3VS

2

1

NIC_ PD_N

24 49Tuesd ay, Febru ary 28, 2006

V_3P3_LAN

LP_EN# 20

0.5

5

RJ-45 CONN.

LANLINK_STATUS#24,34

V_3P3_LAN_LED

D D

V_3P3_LAN_LED

V_2P5_LAN

C C

B B

A A

R266 300_0402_5%

MDO3-34

MDO3+34

MDO1-34

MDO2-34

MDO2+34

MDO1+34

MDO0-34

MDO0+34

LAN_ACT#24,34

R265 300_0402_5%

PJP20

2 1

PAD-SH ORT 2x2m

C330 .01U_0402_16V7K

12

C327 .01U_0402_16V7K

12

C328 .01U_0402_16V7K

12

C329 .01U_0402_16V7K

12

0.1U_0402_16 V4Z
C56

0.1U_0402_16 V4Z
C54

0.1U_0402_16 V4Z
C50

0.1U_0402_16 V4Z
C49

LANLINK_STATUS#

12

MDO3-

MDO3+

MDO1-

MDO2-

MDO2+

MDO1+

MDO0-

MDO0+

LAN_ACT#

12

1 2

1 2

1 2

1 2

LAN_TX0­LAN_TX0+
TRM_CT

LAN_TX1­LAN_TX1+
TRM_CT

LAN_TX2­LAN_TX2+
TRM_CT

LAN_TX3­LAN_TX3+
TRM_CT

R50 49.9_0402_1%
R63 49.9_0402_1%
R45 49.9_0402_1%
R48 49.9_0402_1%
R42 49.9_0402_1%
R44 49.9_0402_1%
R40 49.9_0402_1%
R41 49.9_0402_1%

100K_0402_5%

PREP#2 0,34

JP3

14

Green LED-

13

Green LED+

8

PR4-

7

6

5

4

3

2

1

12

11

1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2

V_3P3_LAN V_3P 3_LAN_LED

12

R877

DETECT PIN1

PR4+

PR2-

PR3-

PR3+

PR2+

PR1-

DETCET PIN2

PR1+

Yellow LED-

Yellow LED+

FOX_JM36113-P1121-7F

U2

12

TD4-

MX4-

11

TD4+

MX4+

10

TCT4

MCT4

9

TD3-

MX3-

8

TD3+

MX3+

7

TCT3

MCT3

TD2-6MX2-

5

TD2+

MX2+

4

TCT2

MCT2

3

TD1-

MX1-

2

TD1+

MX1+

1

TCT1

MCT1

S X'FORM_ S Q-H40B-3F

Lay out No tice : P lace
te rmin ati on a s clo se a s
BC M57 53M as pos sibl e

D

S

13

Q87

G

FDN338P_SOT23

2

13

D

Q88

2

2N7002_SOT23

G

S

SHLD1

SHLD1

13
14
15

16
17
18

19
20
21

22
23
24

4

16

CABLE_DETECT

9

10

15

11/14

MDO0­MDO0+

75_0402_1%

1 2

C1040 .01 U_0805_100V

MDO1­MDO1+

75_0402_1%

1 2

C1041 .01 U_0805_100V

MDO2­MDO2+

75_0402_1%

1 2

C1042 .01 U_0805_100V

MDO3­MDO3+

75_0402_1%

1 2

C1043 .01 U_0805_100V

11/17

LAN_TX0­LAN_TX0+
LAN_TX1­LAN_TX1+
LAN_TX2­LAN_TX2+
LAN_TX3­LAN_TX3+

R269

12

R270

12

R271

12

R272

12

LAN_TX0- 24
LAN_TX0+ 24
LAN_TX1- 24
LAN_TX1+ 24
LAN_TX2- 24
LAN_TX2+ 24
LAN_TX3- 24
LAN_TX3+ 24

7/8

CABLE_DETECT 20,24

9/28

C320

2200P_1808_3KV7K

1 2

11/17

3

10/04

VMAINPRSNT V MAINPRSNT_R

Layout N otice : Fil ter place as c lose
chip as po ssible.

V_2P5_LAN

V_1P2_LAN

R868

0_0603_5%

R869

0_0603_5%

R872

0_0603_5%

L73

BLM11A601S_0603

4.7U_0805_ 10V4Z

L74

BLM11A601S_0603

4.7U_0805_10 V4Z

L75

BLM11A601S_0603

4.7U_0805_10 V4Z
L76

BLM11A601S_0603

4.7U_0805_ 10V4Z

1 3

D

Q106

1 2

12

0.1U_0402_16 V4Z

12

0.1U_0402_16 V4Z

12

0.1U_0402_16 V4Z

12

2

C845

1

12

2

C847

1

12

2

C849

1

12

1

C851

2

C842

C843

C844

2

G

S

BSS84_SOT23

@

R10260_0402_5%

2

1

2

1

2

1

2

C846

0.1U_0402_16 V4Z

1

2

C848

0.1U_0402_16 V4Z

1

2

C850

0.1U_0402_16 V4Z

1

2

C852

0.1U_0402_16 V4Z

1

NIC_ PD 24

XTALVDD

AVDD1

AVDD2

AVDDL

GPHY_P LLVDD

PCIE_P LLVDD

PCIE_S DS_VDD

+3VS

1 2

V_2P5_LAN V_1P2_LAN

R871
10K_0402_5%

10/11

V_3P3_LAN

1 2

R870 1K_0402_5%

PCIE_S DS_VDD

R873

4.7K_0402_5%@

T22

PAD

T59 , T60 pla ce toge ther

L

V_3P3_LAN

R874 4.7K_0402_5%@

1 2

R875 4.7K_0402_5%@

1 2

R876 4.7K_0402_5%@

1 2

0.1U_0402_16 V4Z

C830

2

1

V_3P3_LAN

V_2P5_LAN XTALVDD

V_3P3_LAN

1 2

T23
PAD

PCIE_P LLVDD

GPHY_P LLVDD

2

0.1U_0402_16 V4Z

C831

2

1

V_1P2_LAN

LAN_AUXPWR
VMAINPRSNT

AVDDL

AVDD1
AVDD2

Lay out No tice : 1.2V filt er. Pl ace as clo se
ch ip a s po ssi ble.

2

2

C832

4.7U_0805_10 V4Z

E6
E7
E8
E9

K5

A2
A6

A10

B4
D3

E11

G2

H11

K3
M2

P12

B6
H4

M12

J13

C7

H12

L5

A1
A4
A5
A7
A9
B2
B7
B8
C8
D1
D2
D4
D5
E1
E2
E4
F2
F3
G1
G3
H1
H3

K1
K2

K11

L1
L2
L3
L4
L8
L9

L11

M1
M5
M9
N2
N3
N9
P1
P2

G11
G12

B12

G13

L7

H13

C834

C833

1

1

0.1U_0402_16 V4Z

0.1U_0402_16 V4Z

U6B

BCM5753

VDDC_0
VDDC_1
VDDC_2
VDDC_3

J6

VDDC_4

J7

VDDC_5

J9

VDDC_6
VDDC_7

VDDIO_0
VDDIO_1
VDDIO_2
VDDIO_3
VDDIO_4
VDDIO_5
VDDIO_6
VDDIO_7
VDDIO_8
VDDIO_9
VDDIO_10

VDDP_0
VDDP_1
VDDP_2
XTALVDD
VAUXPRSNT
VMAINPRSNT
PCIE_SDSVDD

NC_0
NC_1
NC_2
NC_3
NC_4
NC_5
NC_6
NC_7
NC_8
NC_9
NC_10
NC_11
NC_12
NC_13
NC_14
NC_15
NC_16
NC_17
NC_18
NC_19
NC_20
NC_21

J3

NC_22

J4

NC_23
NC_24
NC_25
NC_26
NC_27
NC_28
NC_29
NC_30
NC_31
NC_32
NC_33
NC_34
NC_35
NC_36
NC_37
NC_38
NC_39
NC_40
NC_41

AVDDL_0

Analog

AVDDL_1
AVDD_0

power

AVDD_1

PCIE_PLLVDD
GPHY_PLLVDD

BCM5753KFBG C1_FPBGA196~D

1

2

2

1

PLL

2

2

2

C835

C836

C837

1

VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31

BIASVDD

0.1U_0402_16 V4Z

VSS_0
VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9

DC_0
DC_1
DC_2
DC_3
DC_4
DC_5
DC_6
DC_7
DC_8

DC_9
DC_10
DC_11
DC_12
DC_13
DC_14
DC_15
DC_16
DC_17
DC_18
DC_19
DC_20
DC_21
DC_22
DC_23
DC_24
DC_25
DC_26
DC_27
DC_28
DC_29
DC_30
DC_31
DC_32
DC_33
DC_34
DC_35
DC_36
DC_37
DC_38
DC_39

C838

1

1

0.1U_0402_16 V4Z

A3
A8
A12
A14
B1
C1
C3
C11
F1
F5
F6
F7
F8
F9
F10
G5
G6
G7
G8
G9
G10
H6
H7
H8
H9
J1
M3
M7
N1
N7
P11
P14

A11
A13
B14
C14
D6
D14
E3
E14
F14
G14
H5
H14
J8
J14
K4
K6
K7
K8
K9
K10
K14
L6
L10
L12
L14
M11
M14
N5
N11
N12
N14
P3
P4
P5
P6
P7
P8
P9
P10
P13

B13

1

0.1U_0402_16 V4Z

0.1U_0402_16 V4Z

Digial power

GND

Disconnected

Don't care

BIAS

2

C840

C839

1

0.1U_0402_16 V4Z

0.1U_0402_16 V4Z

L77

1 2

BLM11A601S_0603

1

C853

0.1U_0402_16 V4Z

2

2

C841

1

V_2P5_LAN

2

1

0.1U_0402_16 V4Z

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/02/27 2007/02/27

Compal Secret Data

Deciphered Date

Title

Size Docume nt Number Re v

2

Date : Sheet

Compal Electronics, Inc.

Magnetic & RJ45/RJ11

LA-3031P

1

25 49Tuesd ay, Febru ary 28, 2006

0.5

o f

A

B

C

D

E

+3VS_MINI +1.5VS

1

C854

.01U_0402_16V7K

1 1

0.1U_0402_16 V4Z

2

C855

1

2

4.7U_0805_10 V4Z

C856

1

2

.01U_0402_16V7K

C857

1

0.1U_0402_16 V4Z

2

C858

1

4.7U_0805_10 V4Z

2

C859

1

2

Mini-Express Card---WLAN

7/13

PCIE_WAKE #20

CH_DATA2 9
CH_CL K29
CLKREQD #15

CLK_PC IE_MCARD#15

CLK_PC IE_MCARD15

CLK_DEBUG_PORT15

PCIE_RXN220

7/13

PCIE_RXP220

PCIE_TXP220

2 2

STB_LED#3 1,32,34
NUM_LED#3 2,33
CAPS_LED#31,3 2

PCIE_RXP2

+3VL

PCIE_WAKE #
CH_DATA
CH_C LK

1 2

CLK_PC IE_MCARD#
CLK_PC IE_MCARD

PLT_RST#

PCIE_TXN2
PCIE_TXP2

R878 0_0402_5%

1 2

R884 0_0402_5%DEBUG@

R885 0_0402_5%

1 2
1 2

R886 0_0402_5%

8/29

R887 0_0402_5%DEB UG@

1 2

R889 0_0402_5%DEB UG@

1 2

R890 0_0402_5%DEB UG@

1 2

R888 0_0402_5%DEB UG@

1 2

8/29

CLKREQD#_ MC

PCIE_C_RX N2PCIE_RXN2
PCIE_C_RXP2

JP37

1

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51

GND1

GND2

2
4
6

8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

3
5
7

9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51

53

FOX_AS0B226-S40N-7F~D

2
4
6

R879 0_0402_5%DEB UG@

1 2

8

R880 0_0402_5%DEB UG@

1 2

10

R881 0_0402_5%DEB UG@

12

1 2

R882 0_0402_5%DEB UG@

1 2

14

R883 0_0402_5%DEB UG@

1 2

16
18

XMIT_OFF#

20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

54

WL_LED#

7/12

10K_0402_5%@

XMIT_OFF_R#2 0

PLT_RST# 7,17, 18,20,22,24,30,3 1,32

ICH_SMBC LK 4,13,14,1 5,20,24
ICH_SMBDATA 4,13,1 4,15,20,24PCIE_TXN220

R892

+3VALW

C860

0.1U_0402_16 V4Z

+1.5VS +3VS_MINI

+3VALW

12

R891

12

100K_0402_5%@

13

D

Q92

2

G

S

@

1

2

LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0

2N7002_SOT23

LPC_FRAME# 19,30,3 1,32

2 1

PAD-No SHORT 2x2m

2 1

PAD-SH ORT 2x2m

XMIT_OFF#

LPC_AD [0..3] 1 9,30,31,32

J9

J10

+3VALW

V_3P3_LAN

11/29 1/10

9/27

+3VS

+3VALW +3VS_MINI

SLP_S3#20,24,27,2 8,32,34,35,39,41 ,42

+3VS

47K

10K

2

Q90
DTA114YKA_S C59

1 3

100K_0402_5% @

SLP_S3#

2N7002_SOT23@

R1009

1 2

2

G

Q102

WL_LED#

WL_LED

1 2

0_0805_5%

S

Mini-PCIE Card LED

R1008

G

2

13

SI2301BDS_SOT23@

D

S

D

13

Q101

9/27

WL_LED 33

9/14

1 2

R990 0_0402_5%

8/1

R950

+3VS_ACL

1

2

+3VS

1 2

2 1

CH751H-40 _SC76ACCEL@

R954

18

20

12

14
15
21
22
23
24
25
26
27
28

12

12

0_0402_5%ACCEL@

Must be pl aced in the cente r of the system.

3 3

4 4

ACCELEROMETER

+3VS_ACL_IO

+3VS_ACL

1

C901

0.01U_0402_16V7K@

C902

2

0.1U_0402_16 V4ZACCEL@

R952 0_0402_5%ACCEL@

R953 0_0402_5%ACCEL@

10U_0805_6.3V6M ACCEL@

1

C903

2

Close to U52 pin 3

A

4

1
7
8

0_0805_5%@

D53

U52

Reserved2

Reserved3

Reserved1

NC1
NC2
NC3
NC4
NC5
NC6
NC7
NC8
NC9
NC10
NC11
NC12
NC13

+3VS_ACL

3

Vdd

PADDLE

29

19

GND

2

1 2

11

Vdd

Vdd_IO

SDA/SDI/SDO

GND

5

17

R951

RDY/INT

SCL/SPC

GND

+3VS_ACL_IO

0_0603_5%ACCEL@

SDO

CS

CK

LIS3LV02DQ_ QFN28ACCEL@

B

6

9

10

12

13

16

ICH_SMBDATA

ICH_SMBC LK

R955

1 2

10K_0402_5%ACCEL@

R956

1 2

0_0402_5%ACC EL@

ACCEL_INT 18, 32

+3VS_ACL

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2006/02/27 2007/02/27

Compal Secret Data

Deciphered Date

D

Title

Size Docume nt Number Re v

Date : Sheet of

Compal Electronics, Inc.

Mini-Card/ACCELEROMETER

LA-3031P

26 49Tuesd ay, Febru ary 28, 2006

E

0.5

A

VDDA _CODEC

1 1

PCM_SPK22

SB_SPKR20

2 2

3 3

12

R329
10K_0402_5%

13

D

Q35

2

2N7002_SOT23

G

S

VDDA _CODEC

12

R350
10K_0402_5%

13

D

Q37

2

G

2N7002_SOT23

S

DLINE _IN_L34 R_HP 28

DLIN E_IN_R34

VDDA_ CODEC

7/15

SENSE_A

4 4

SENSE_B

A

R980

0_0402_5%@

1 2

B

C390

1 2

0.1U_0402_16 V4Z

C396

1 2

0.1U_0402_16 V4Z

R969

2.67K_0402_1%

1 2

2

C917

1U_0402_6. 3V4Z@

1

1 2

150K_0402_1%

1 2

150K_0402_1%

R370 4.7K_0402_5%
R375 4.7K_0402_5%

1 2

R369 4.7K_0402_5%
R374 4.7K_0402_5%

1 2

39.2K_0402_1%

1 2

R970

20K_0402_1%

1 2

R972

10K_0402_1%

1 2

R973

B

R341

R359

INT_MIC28

12

12

SENSE_A_C

2N7002_SOT23

7/15

MIC128

MIC228

VDDA _CODEC

SENSE_A_A 2 8

SENSE_A_B 2 8

D

Q95

S

7/15

DLINE_ IN_R_L

DLIN E_IN_R_R

AC97_RST# _CODEC19

AC97 _SYNC_COD EC19

AC97_SDO UT_CODEC19

13

2

G

C

12

R330

10K_0402_5%

0.1U_0402_16 V4Z

VDDA_ CODEC

R985

1 2

100K_0402_5%

C

0.1U_0402_16 V4Z

2

C377

.01U_0402_16V7K

1

VDDA_ CODEC

1

C862

C861

2

0.1U_0402_16 V4Z

C922

1 2

1U_0603_10V4Z
C923

1 2

1U_0603_10V4Z
C869

1 2

1U_0603_10V4Z
C870

1 2

1U_0603_10V4Z

C924

1 2

1U_0603_10V4Z
C925

1 2

1U_0603_10V4Z

1 2

R966 2.2K_0402_5%

R994 0_0402_5%@

EAPD28,32

7/15

R974

@

0_0402_5%

1 2

LINE_I N_SENSE

1

C918

0.1U_0402_16 V4Z

2

C391

MONO_I N_HD

1 2

0.1U_0402_ 16V4Z

1

C863

2

1

1

C864

2

2

10U_0805_10V4Z

T24PAD

T25PAD

DLIN E_IN_RC_L

DLIN E_IN_RC _R

T28PAD

T29PAD

T30PAD

MIC1_C

MIC2_C

SENSE_A
SENSE_B

12

0.1U_0402_16 V4Z

C865

8/9

1 2

L78 CHB1 608B121_0603

7/28

LINE_I N_SENSE 34

T37PAD

D

+5VAMP

1

+

C548

22U_B_10V

2

E

2

C552
1U_0603_10V4Z

1

SLP_S3#20,24,26,2 8,32,34,35,39,41 ,42

2

C551

100P_0402_50V8J

1

R258

1 2

0_1206_5%

7/11

F

U18

1

IN

OUT

3

EN

ADJ

2

GND

MIC5205YM5_SOT23-5

.01U_0402_16V7K

7/19

+3VS

0.1U_0402_16 V4Z

2

1

38

U14

AVDD125AVDD2

14

AUX_L

15

AUX_R

16

MIC3

17

MIC4

23

LINE_IN_L

24

LINE_IN_R

18

CD_L

20

CD_R

19

CD_GND

21

MIC1

22

MIC2

13

SENSEA

34

SENSEB

11

RESET#

10

SYNC

5

SDATA_OUT

47

EAPD

48

SPDIFO

4

DVSS1

7

DVSS2

AD1981HDJST Z-REEL_LQFP48

LINE_OUT_L

LINE_OUT_R

MONO_OUT

HP_LOUT_L

HP_LOUT_R

MIC_BIAS_B
MIC_BIAS_C
MIC_BIAS_F
MIC_BIAS_D

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

D

C866

9

DVDD11DVDD2

35

36

37

39

41

6

BIT_CLK

8

SDATA_IN

43

GPIO_0

44

GPIO_1

2

GPIO_2

3

GPIO_3

27

VREF

28
29
30
32
12

PCBEEP

31

N/C

33

N/C

40

N/C

45

NC

46

NC

26

AVSS1

42

AVSS2

2006/02/27 2007/02/27

+3VS_CODEC

1

1

C867

2

2

0.1U_0402_16 V4Z

T27 P AD

R967 33_0402_5%@

AC97_S DIN0_CODEC

1 2

AUD_ REF

MONO_I N_HD

PIN33

PIN42

9/29

9/21

R965 4.7K_0402_5%@
R971 4.7K_0402_5%@
R898 10K_0402_5%
R968 4.7K_0402_5%@

Compal Secret Data

E

1 2

0_0805_5%

1

C868

10U_0805_10V4Z

2

8/9

L_HP 28

1 2

AC97_BIT CLK_CODEC 19

R897

39_0402_5%

12
12

12

MIC_BIAS_B 28

T31 P AD
T32 P AD
T34 P AD

T33 P AD
T40 P AD
T38 P AD

T35PAD

T36 P AD

Deciphered Date

R895

C871 10P_0402_25V8K@

12

AC97_S DIN0 19

PORT_A_SNS 28

PR_INSERT #

2

C875

1

1U_0402_6.3V4Z

F

5

4

LINE_OUTL 28

LINE_OUT R 28

1 2

1

C876

0.1U_0402_16 V4Z

2

C553

G

VDDA_ CODEC

12

R456

2

1

49.9K_0402_1%

12

R457

143K_0402_1%

1

+

C309

22U_B_10V

2

1

C307

0.1U_0402_16 V4Z

2

Place close t o U14

12

C874 0.1U_0805_25V7M

12

C877 0.1U_0805_25V7M

12

C878 0.1U_0805_25V7M

R901 0_1206_5%

12

9/21

GNDAGND

PORT

MONO_O UT

PORT A

PORT B

PORT C

PORT D

PORT E

PORT F

Title

Size Docume nt Number Re v

Date : Sheet of

Compal Electronics, Inc.

AC97 CODEC AD1981HD

LA-3031P

G

PLACE TO

X

HP OUT , DOCK HP LO

M/B MI C

DOCK L I

M/B SP K

X

Intern al MIC

H

27 49Tuesd ay, Febru ary 28, 2006

H

0.5

A

AMP. FOR INTERNAL SPEAKER

+5VAMP

+5VALW

1 1

LINE_OUT R27

LINE_OUTL27

SLP_S3#

MUTE_LED#33

12/9

EAPD27,32

2 2

LINE OUT/HEADPHONES AUDIO JACK

8/13

C503

LINE_C_ OUTR

1 2

0.1U_0603_50 V4Z

C502

LINE_C_OUT L

1 2

0.1U_0603_50 V4Z

C504

1 2

0.22U_0603_10V7K

1 2

R430

R995

0_0402_5%

R1034

1K_0402_5%@

1 2

Q28

2N7002_SOT23

A_SD32

12

2

G

VDDA_ CODEC

7/19

PORT_A_SNS27

SENSE_A_A27

DOCK_HPS #34

3 3

R_HP27

L_HP27

C262 1 50U_D_6.3VM

C263 1 50U_D_6.3VM

DLINE_O UT_R34
DLINE_OUT_ L34

4 4

+

1 2

+

1 2

A

Q44

13

D

2

G

S

2N7002_SOT23

C526

0.1U_0603_16 V4Z

7/19

R_C_ HP

R425

1 2

34.8K_0603_1%

R424

1 2

34.8K_0603_1%

R429

1 2

16.2K_0603_1%

10K_0402_5%

13

D

S

2

G

12

R986

100K_0402_5%

13

D

Q98

S

1

2

7/19

R252

1 2

16_0805_1%

R253

1 2

16_0805_1%

R445

1K_0402_1%

0_1206_5%

13

D

Q97
2N7002_SOT23

S

2N7002_SOT23

2

G

12

LINE_OUT

VDDA_ CODEC

D

S

2N7002_SOT23

R_CR _HP

L_CR_H P

12

R446

1K_0402_1%

R443

1 2

1 2

0_1206_5%

3

4

1

2

1

C521

0.47U_0603_10V7K

2

12

R251

100K_0402_5%

Q48

13

2

G

CHB1608B121_0603

1 2

L52

L51

1 2

CHB1608B121_0603

.01U_0402_16V7K

R442

U31

1

2

470P_0402_50V7K

6

IN+

IN-

SHUTDOWN

BYPASS

7

R255

1 2

C536

100K_0402_5%

2.2U_0603_6.3 V6K

7/15

R_CRL _HP

L_CRL_ HPL_C_HP

C540

C470

1 2

B

1

+

C300

150U_D_6.3VM

2

VDD

GND

SPK+

5

VO+

VO-

TPA6211A1DGNRG4_PMSOP8

VDDA _CODEC

1

2

B

8

12

R256

100K_0402_5%

1

2

CHB1608B121_0603

SPK-

CHB1608B121_0603

C920

1

4.7U_0805_ 6.3V6K

2

C547

470P_0402_50V7K

+5VAMPP

1

C539

0.1U_0402_ 16V4Z

2

L47

1 2

L48

1 2

R977

47K_0402_5%

JP21

5

4

3
6
2
1

SUYIN_ 010178FR006G100H L

C506

100P_0402_50V8J

C

AMP. FOR INTERNAL MICROPHONE

AMP. FOR EXTERNAL MICROPHONE

JP36

INT_MIC_2

1
2

ACES_85205-0200

VDDA_ CODEC

CODE C_REF

1 2

SENSE_A_B27

1 2

1 2

R987 0_0402_5%@

C

R196

1 2

3K_0402_5%

1

2

EXT_MICB

2N7002_SOT23

R979
0_0402_5%

2006/02/27 2007/02/27

SPK++

SPK--

1

1

2

2

C514

100P_0402_50V8J

R975

47K_0402_5%

1 2

1 2

VDDA_ CODECVDDA _CODEC

5

+

6

-

JP15

1
2

ACES_85205-0200

100_0402_5%

4

U27B

P

7

OUT

G

TLV2464_TSSOP14

11

R976

7/20

VDDA _CODEC

MIC_BIAS_B27

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C585

1 2

@

1200P_0402_50V7K

R193

INT_MIC_1 INT _MIC_3

1 2

3K_0402_5%

1

C224

4.7U_0603_6.3V6M

2

8/9

C921

4.7U_0805_ 6.3V6K

C271

EXT_MICA

1 2

0.22U_0603_10V7K

C270

EXT_MICB_1

1 2

0.22U_0603_10V7K

13

D

Q96

10U_0805_10V4Z

S

R418

1 2

470_0402_5%

1 2

R417

470_0402_5%

C487

G

C202

1 2

0.22U_0603_10V7K

EXT_MICA_1

HLC0603CSCC R10JT_0603

L61

1 2

HLC0603CSCC R10JT_0603

VDDA_ CODEC

R978
47K_0402_5%

1 2

2

2

C919

0.1U_0402_16 V4Z

1

1 2

R422 3.9K_0402_1%

1 2

R421

3.9K_0402_1%

2

2

C486
10U_0805_10V4Z

1

1

8/9

L58

1 2

Compal Secret Data

Deciphered Date

HLC0603CSCC R10JT_0603

D

CODE C_REF VDD A_CODEC

1

C446

2

L57

1 2

C571

68P_0402_50V8J

1

2

1 2

1

2

1 2

C572

1

68P_0402_50V8J

2

1 2

C575
68P_0402_50V8J

100P_0402_50V8J

INT_MIC_4

R385
10K_0402_5%

1

C244

2

100P_0402_50V8J

EXT_MICA_2

R211
10K_0402_5%

CODE C_REF VDD A_CODEC

1

C243

2

100P_0402_50V8J

EXT_MICB_2

R210
10K_0402_5%

3

2

VDDA_ CODECCODEC_ REF

10

9

12

13

EXT. MICIN AUDIO JACK

MIC_SENSE

EXT_MICB

EXT_MICA

1 2

CHB1608B121_0603

1 2

CHB1608B121_0603

D

L46

L45

1

C507

470P_0402_50V7K

2

Title

Size Docume nt Number Re v

Date : Sheet of

E

C211

1 2

150P_0402_50V8J

R190

1 2

100K_0402_5%

1

C441

2

0.1U_0402_16 V4Z

4

U27A

P

+

OUT

-

G

TLV2464_TSSOP14

11

4

U27C

P

+

OUT

-

G

TLV2464_TSSOP14

11

4

U27D

P

+

OUT

-

G

TLV2464_TSSOP14

11

1

C518

470P_0402_50V7K

2

INT_MIC

1

C488

1 2

100P_0402_50V8J

R413

1 2

100K_0402_5%

8

C489

1 2

100P_0402_50V8J

R414

1 2

100K_0402_5%

14

JP13

5

4

3
6
2
1

SUYIN_ 010178FR006G100H L

MIC1

MIC2

Compal Electronics, Inc.

AMP & Audio Jack

LA-3031P

E

INT_MIC 27

MIC1 27

MIC2 27

0.5

28 49Tuesd ay, Febru ary 28, 2006

5

4

3

2

1

U32

1

GND

2

D D

C C

SLP_S5

C535

4.7U_0805_10 V4Z

1

2

3
4

OUT

IN

OUT
OUT

IN

OC#

EN#

TPS2061IDGNR_MSOP8

USB20_N3 USB20_N4

USB_VCC A USB_V CCC

8
7
6
5

D54

1

GND

2

IO1

PRTR5V0U2X_SOT143-4

IO2

VIN

3

4

W=40mils

USB20_P3

USB_VCC A

1

+

C527

2

150U_D_6.3VM

USB20_N320
USB20_P320

1

1

2

C519

C515

2

0.1U_0402_ 16V4Z
1000P_0402_50V7K

JP16

USB20_N3
USB20_P3 USB20_P4

1
2
3
4

SUYIN_02013 3MR004S516ZL

SLP_S534,35

7/13 7/13

SLP_S5

4.7U_0805_10 V4Z

+5VALW+5VALW

C4

1

2

U1

1

GND

2
3
4

OUT

IN

OUT
OUT

IN

OC#

EN#

TPS2061IDGNR_MSOP8

8
7
6
5

USB CONNECTOR 1

USB CONNECTOR 2

W=40mils

D55

1

GND

2

IO1

PRTR5V0U2X_SOT143-4

USB20_P4

3

IO2

4

VIN

USB_ VCCC

1

+

C1

2

USB20_N420
USB20_P420

1

1

2

150U_D_6.3VM

C312

0.1U_0402_ 16V4Z

USB20_N4

C311

2

1000P_0402_50V7K

JP5

1
2
3
4

SUYIN_02013 3MR004S516ZL

USB CONNECTOR 3

R512

+5VALW

11/14

1

2

U12

13

ENABLE

11

FAULT

12

3
4

2
6
9

ISET

PWRGD

ISENSE

TIMER

GATE

VREG

DGND

DISCH

AGND

VSENSE

AGND

TPS2331IPWRG4_TSSOP14

IN

C589

1

2

1000P_0402_50V7K

USB_OC#5 _R
USB_OC#5

1

2

C582

2200P_0402_50V

9/8
11/29
12/9
1/12

C583

0.1U_0402_16 V4Z

USB_OC#5_ R20

USB_OC#520

B B

8

10

7

1

14

5

1

2

C579

2.2U_0805_16 V4Z

USB_ISENS E1

USB_ISENS E2

1 2

0.01_2512_1%

1

2

C580

12

0.1U_0402_16 V4Z

R513

1K_0805_1%

1/12

Q57

8

D

7

D

6

D

5

D

SI4800D Y_SO8

USB20_N5

11/14

A A

USB_VCC B

1

S

2

S

3

S

4

G

1

C581

2

0.1U_0402_16 V4Z

C102

220U_D_6.3VM

D56

1

2

3

GND

IO2

4

IO1

VIN

PRTR5V0U2X_SOT143-4

1/12

USB20_P5

W=40mils

1

+

0.1U_0402_16 V4Z

2

C437

11/14

USB_VCC B

USB20_N520
USB20_P520

1

2

1

C430

1000P_0402_50V7K

2

USB20_N5
USB20_P5

JP11

1
2
3
4

FOX_UB11123-C1203-TR

1

C306
1U_0603_10V4Z

2

BT_OFF20

BT Connector

JP22

1
2
3
4
5
6
7
8

ACES_87212-0800

8/30

Q51

S

12

R518

100K_0402_5%

R454

1 2

47K_0402_5%

9/27

G

2

USB20_P0 20
USB20_N0 20
BT_LED 33
CH_DATA 26
CH_CL K 26

AO3413_SOT23

D

13

1

C546

2

.01U_0402_16V7K

1

C1032

0.1U_0402_16 V4Z

@

2

+3VAUX_BT

7/13

1

C545

2

0.1U_0402_ 16V4Z

+3VAUX_BT+3VALW

1

C549

4.7U_0805_10 V4Z

2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/02/27 2007/02/27

Compal Secret Data

Deciphered Date

Title

Size Docume nt Number Re v

2

Date : Sheet of

Compal Electronics, Inc.

USB & BT Connector

LA-3031P

29 49Tuesd ay, Febru ary 28, 2006

1

0.5

A

1 1

RP6

2 2

10K_1206_8P4R_ 5%

RP7

10K_1206_8P4R_ 5%

1 2

R68 10K_0402_5%

3 3

+3VS

1 2

R79 10K_0402_5%

SIO _IRQ

18

SIO_GPI O12

27

SIO_GPI O10

36

SIO_GPI O46

45

SIO_GPI O45

18

SIO_GPI O44

27

SIO_GPI O43

36

SIO_GPI O41

45

1 2

R500 0_0402_5%

SW_EXPC RD_RST#

SIO_GPI O42

EXPCRD_RST# 34

B

LPC_A D019,26 ,31,32

LPC_AD 119,26, 31,32

LPC_A D219,26 ,31,32

LPC_AD 319,26, 31,32

LPC_FR AME#19,26 ,31,32

LPC_DR Q#019

1 2
1 2
1 2

@

PM_CLK RUN#20, 22,31,32

CLK_P CI_SIO15

CLK_14M_SIO15

SIR Q20,22 ,31,32

+3VS

+3VS

R67 10K_0402_5%

NPCI_R ST#
PLT_RST#

R902 0_0402_5%
R903 0_0402_5%
R99 10K_0402_5%

1 2

NPCI_R ST#20

PLT_RST#7,17, 18,20,22,24 ,26,31,32

7/28

SER_ SHD34

SW_EXPC RD_RST#

LPC_A D0
LPC_A D1
LPC_A D2
LPC_A D3

LPC_F RAME#
LPC_DR Q#0

SIO_P D#

PM_CLK RUN#
CLK_P CI_SIO
SIR Q
SIO_PME#

CLK_14M_SIO

SIO_GPI O40
SIO_GPI O41
SIO_GPI O42
SIO_GPI O43
SIO_GPI O44
SIO_GPI O45
SIO_GPI O46
SER_ SHD
SIO_GPI O10
SIO_GPI O11
SIO_GPI O12
SIO _IRQ

C

DCD #1
RI#1
CTS#1
DSR# 1

IRRX

U8

10

LAD0

12

LAD1

13

LAD2

14

LAD3

15

LFRAME#

16

LDRQ#

17

PCI_RESET#

18

LPCPD#

19

CLKRUN#

20

PCI_CLK

21

SER_IRQ

6

IO_PME#

9

CLK14

23

GPIO40

24

GPIO41

25

GPIO42

27

GPIO43

28

GPIO44

29

GPIO45

30

GPIO46

31

GPIO47

32

GPIO10

33

GPIO11/SYSOPT

34

GPIO12/IO_SMI#

35

GPIO13/IRQIN1

36

GPIO14/IRQIN2

40

GPIO23

8

VSS

22

VSS

43

VSS

52

VSS

LPC47N217 -JV_STQFP64

Base I/O Add ress

0 = 02Eh
1 = 04Eh*

4.7K_1206 _8P4R_5%

R76
1K_0402_5%

LPC I/F

CLO CK

GPIO

POWER

RP3

1 8
2 7
3 6
4 5

1 2

RXD1
TXD1

DSR1#

RTS1#
CTS1#
DTR1#

DCD1#

SERIAL I/F

IRRX2

FIR

IRTX2

IRMODE/IRRX3

INIT#

SLCTIN#

SLCT

BUSY

ACK#

PARALLEL I/F

ERROR#

STROBE#

RI1#

PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7

ALF#

VTR
VCC
VCC
VCC
VCC

PE

+3VS

62
63
64
1
2
3
4
5

37
38
39

41
42
44
46
47
48
49
50
51
53
55
56
57
58
59
60
61

7
11
26
45
54

RXD1
TXD1
DSR# 1
RTS#1
CTS#1
DTR#1
RI#1
DCD #1

IRRX
IRTXOUT
IRMO DE

LPTINIT#
LPTSLCTIN#
LPD0
LPD1
LPD2
LPD3
LPD4
LPD5
LPD6
LPD7
LPTSLCT
LPTPE
LPTBU SY
LPTACK#
LPTERR#
LPTAFD#
LPTSTB#

1

C84

2

0.1U_0402 _16V4Z

0.1U_0402 _16V4Z

D

RXD1 34

R64 1K_0402_5%

1 2

TXD1 34
DSR# 1 34
RTS#1 34
CTS#1 34
DTR#1 34
RI#1 34
DCD #1 34

IRRX 33
IRTXOUT 33
IRMOD E 33

LPTINIT# 34
LPTSLCTIN# 34
LPD0 34
LPD1 34
LPD2 34
LPD3 34
LPD4 34
LPD5 34
LPD6 34
LPD7 34
LPTSLCT 34
LPTPE 34
LPTBU SY 34
LPTACK# 34
LPTERR# 34
LPTAFD# 34
LPTSTB# 34

1

1

C88

C76

2

2

0.1U_0402 _16V4Z

1

2

+3VS

C57

4.7U_0805 _10V4Z

RB751V_SOD 323

+5VS_PRN

LPD3
LPD2
LPD1
LPD0

LPD7
LPD6
LPD5
LPD4

LPTACK#
LPTBU SY
LPTPE
LPTSLCT

LPTSTB#
LPTAFD#
LPTERR#

LPTSLCTIN#

LPTINIT#

RP51

1 8
2 7
3 6
4 5

4.7K_1206 _8P4R_5%

RP52

1 8
2 7
3 6
4 5

4.7K_1206 _8P4R_5%

RP53

1 8
2 7
3 6
4 5

4.7K_1206 _8P4R_5%

RP54

1 8
2 7
3 6
4 5

4.7K_1206 _8P4R_5%

1 2

R480 4.7K_0402_5%

1 2

R481 4.7K_0402_5%

D36

E

+5VS

21

SIO_GPI O11

SIO_GPI O40

CLK_14M_SIOCLK _PCI_SIO

12

R96
10_0402_5%@

1

C94
18P_0402_50V8J

@

2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2006/02/27 2007/02/27

C

12

R81
10_0402_5%@

1

C70
10P_0402_25V8K

@

2

Compal Secret Data

Deciphered Date

Title

Size Docum ent Numb er Re v

D

Dat e: Sheet o f

Compal Electronics, Inc.

SUPER I/O LPC47N217

LA-3031P

30 49Tues day, Feb ruary 28, 2006

E

0.5

1 2

R80 10K_0402_5%

1 2

R100 10K_0402_5%

4 4

A

5

4

3

2

1

Wireless/BT ON & OFF Button

BIOS ROM

FWH_TBL#20

D D

FWH_W P#20

1 2

R273 100_0402_5%FW H@

RP42

4 5
3 6
2 7
1 8

100_1206_8P4R_5%

FW H@

FWH_TBL#
FWH_W P#

FWH_ GPI0
FWH_ GPI1
FWH_ GPI2
FWH_ GPI3
FWH_ GPI4

SPI

SPI@

0.1U_0402_16 V4Z

C C

1 2

C883

SPI_CS#20

SPI_CLK20

SPI_SI20

U20

24

A0/ID0

23

A1/ID1

22

A2/ID2

21

A3/ID3

20

A4/TBL#

19

A5/WP#

18

A6/FGP10

17

A7/FGP11

16

A8/FGP12

15

A9/FGP13

7

A10/FGP14

1

NC1

3

NC2

4

NC3

5

NC4

6

NC5

8

NC6

11

NC7

13

NC8

14

NC9

31

NC10

36

NC11

SST49LF008A-33-4C-EI_TSOP40

@

+3VALW

SPI_WP#

SPI_HOL D#

SPI_CS#

SPI_CLK

SPI_SI

8

3

7

1

6

5

U45

VCC

W

HOLD

S

C

D

VDD2
VDD1

VSS3
VSS2
VSS1

DQ0/FWH0
DQ1/FWH1
DQ2/FWH2
DQ3/FWH3

WE#/FWH4

DQ4/RES
DQ5/RES
DQ6/RES
DQ7/RES

R/C#/CLK

RST#

OE#/INIT#

VSS

SST25LF080B_SO8-200milSPI@

IC

Q

+3VS +3VS

39
10

40
30
29

25
26
27
28
38

32
33
34
35

9
12
37

2

1

C333

FW H@

2

0.1U_0402_16 V4Z

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
LPC_FRAME#

CLK_PC I_FWH
PLT_RST#
FWH_ INIT#

FWH _IC

R278

1

C42

0.1U_0402_16 V4ZFW H@

2

CLK_PC I_FWH

12

R905

1

C884

2

CLK_PC I_FWH 1 5
PLT_RST# 7,17, 18,20,22,24,26,3 0,32

FWH_ INIT# 19

1 2

10K_0402_5%FW H@

10_0402_5% @

10P_0402_50V8K @

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
LPC_FRAME#
FWH_W P#
FWH_TBL#
PLT_RST#
FWH_ INIT#
CLK_PC I_FWH

FWH_ GPI0
FWH_ GPI1
FWH_ GPI2
FWH_ GPI3
FWH_ GPI4

&U21

45@

SST49LF008A-33-4C-NH

2/23

4

+3VALW

R906

2

47_0402_5%SPI@

R908 shou ld b e placed less
than 100 mils from U45 & U46.

L

R908

1 2

SPI_SO

SPI_SO 20

1 2

R907

1 2

3.3K_0402_5%SPI@

3.3K_0402_5%SPI@

U21

13

FWH0

14

FWH1

15

FWH2

17

FWH3

23

FWH4

7

WP#

8

TBL#

2

RST#

24

INIT#

31

CLK

6

FGPI0

5

FGPI1

4

FGPI2

3

FGPI3

30

FGPI4

1

NC

22

NC

26

NC

27

NC

FWH@1M8 _PLCC32

SPI_WP#

SPI_HOL D#

GND
GND

VDD
VDD

RES
RES
RES
RES

25
32

16
28

21
20
19
18

12

ID0

11

ID1

10

ID2

9

ID3

FWH _IC

29

IC

KSI_D_1117,3 2,33 KSO15 32,33

KSI_D_1232,33

ON/O FF#33,34

KSI_D_11 KSO15

KSI_D_12 KSO15

ON/OFF & SLEEP Button

ON/O FF#

STB_LED#26,32,34

TPM1.2

U47

LAD0
LAD1
LAD2
LAD3

LCLK
LFRAME#
LRESET#
SERIRQ
CLKRUN#

7

PP

TPM_XTALI

TPM@

10M_0402_5%

TPM_XTALO

+3VS+3VALW

19

10

VDD24VDD

VDD

TPM
SLB 9635 TT 1.2

GND4GND11GND18GND

12

R914

1

2

5

VSB

LPCPD#

TESTB1/BADD

TEST1

XTALO

XTALI

GPIO2

GPIO

SLB9635TT_TSSOP28TPM@

25

C889

1 2

1

IN

4

OUT

Y6

C891

1 2

C888

NC
NC
NC

32.768KHZ_ 12.5P_1TJS125BJ2A251TPM@

0.1U_0402_16 V4ZTPM@

LPC_PD R#

28
9

R910

8

TPM_XTALO

14

TPM_XTALI

13

GPIO2

2

GPIO

6

1
3
12

18P_0402_50V8JTPM@

2

NC

3

NC

18P_0402_50V8JTPM@

4

0.1U_0402_16 V4ZTPM@

1

1

C885

B B

LPC_AD [0..3]19,26,30 ,32

+3VS

@

4.7K_0402_5%

12

R912

12

R913

0_0402_5%TPM@

A A

2

0.1U_0402_16 V4ZTPM@

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3

5

+3VALW

1

2

CLK_PCI_TC G
LPC_FRAME#
PLT_RST#
SIRQ
PM_CLKRU N#

C890

CLK_PCI_TC G15

LPC_FRAME#19,2 6,30,32

SIRQ20, 22,30,32

PM_CLKRUN #20,22,30,32

1

C886

C887

TPM@

0.1U_0402_16 V4Z

2

2

26
23
20
17

21
22
16
27
15

0.1U_0402_16 V4ZTPM@

LPC_PD R#

Base I/O Add ress

0 = 02Eh

* 1 = 04Eh

12

0_0402_5%TPM@

T48

PAD

T49

PAD

TPM_XTALI

12

LPC_PD# 20,32

R9590_0 402_5%

+3VS

12

R909

4.7K_0402_5%TPM@

12

R911

4.7K_0402_5%@

R1010

12

0_0402_5%@

CLK_TPM 32

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/02/27 2007/02/27

Compal Secret Data

Deciphered Date

CAPS_LED#26, 32

17-21SYGC/S 530-E1/TR8_GRN

2

SW2

2 1

4 3

NTC303-DB1G-C180T_4P

S TACT SW NTC303-DB1G-C18 0T SPST MISAKI

QuickLook Button

SW1

2 1

4 3

NTC303-DB1G-C180T_4P

S TACT SW NTC303-DB1G-C18 0T SPST MISAKI

123

4

8

7

SS607-212N-FEEG1T

STB_LED#

GREEN
POWER LED

CAPS_LED#

GREEN
CAP LED

6

5

SW3

+3VL

47K

2

2

D12

Title

Size Docume nt Number Re v

Date : Sheet of

Q25

10K

DTA114YKA_S C59

1 3

STB_LED

12

R259

150_0402_5%

21

D41

17-21SYGC/S 530-E1/TR8_GRN

+3VL

47K

10K

Q72
DTA114YKA_S C59

1 3

12

R184

150_0402_5%

21

CAPS LED

STB_LED 33

12

R541

150_0402_5%

21

D30

17-21SYGC/S 530-E1/TR8_GRN

Compal Electronics, Inc.

TCG/BIOS ROM/PS2/LED/SW

LA-3031P

1

31 49Tuesd ay, Febru ary 28, 2006

0.5

250@
R78

5

1021@

R930

4

+3VL

+3VS

3

2

1

R62

1

C37

0.1U_0402_16 V4Z

+3VL

D D

C C

B B

A A

RP44

KSI0

1 8

KSI1

2 7

KSI2

3 6

KSI3

4 5

47K_1206_8P4R_5%

RP43

KSI4

1 8

KSI5

2 7

KSI6

3 6

KSI7

4 5

47K_1206_8P4R_5%

+5VS

R84

TP_CLK

1 2

10K_0402_5%

R85

TP_DATA

1 2

10K_0402_5%

RP5

KBD_CLK

1 8

KBD_DATA

2 7

PS2_CLK

3 6

PS2_DATA

4 5

10K_1206_8P4R_5%

Note: R94 mus t b e r emo ved w hen

+3VS

R1354 stu ff a nd R87 remov e.

L

LPCPD#

1 2

R94 10K_0402_5%

RUNS CI_EC#

1 2

10K_0402_5%

R923

CLK_PC I_EC

12

R86

10_0402_5%@

2

C80

10P_0402_50V8J@

1

D27

KSI_D_0

1

DAP202U_SOT323
D26

1

DAP202U_SOT323
D25

1

DAP202U_SOT323

RP4

1 8
2 7
3 6
4 5

0_1206_8P4R_5%@

2

KSI_D_8

3

KSI_D_1

2

KSI_D_9

3

KSI_D_2 KSI_D_5

2

KSI_D_10

3

KSI_D_0
KSI_D_1
KSI_D_2
KSI_D_3

KSI0

KSI1

KSI2

KSI1
KSI2
KSI3

Pin34 250 - - LPCPD#

10P_0402_50V8J

5

LPC_PD#20,31

ACCEL_INT18,26

1 2

R74
2M_0402_5%@

1

IN

1

C350

2

2

32.768KHZ_ 12.5P_1TJS125DJ2A073

KSI_D_0 33

KSI_D_8 17,33

KSI_D_1 33

KSI_D_9 17,33

KSI_D_2 33

KSI_D_10 17,33

0.1U_0402_16 V4Z

2

KSO[0. .13]33

Pin3 250 : KSO12/OUT8/KBRST

R87 0_0402_ 5%@

1 2

R924 0_0402_5%@

1 2

R75

120K_0402_5%

4

Y7

1

OUT

C349

10P_0402_50V8J

NC3NC

2

KSI3

1

KSI4

1

KSI5

1

KSI4KSI0

1 8

KSI5

2 7

KSI6

3 6
4 5

0_1206_8P4R_5%@

KSI[ 0..7]33

PM_CLKRUN #20,22,30,31

CLK_PC I_EC15

RUNS CI_EC#20

LPC_FRAME#19,2 6,30,31

D24

DAP202U_SOT323

D23

DAP202U_SOT323
D20

DAP202U_SOT323

RP2

C52

TP_CLK33
TP_DATA33
KBD_CLK34

KBD_DATA34

PS2_CLK34

PS2_DATA34

SIRQ2 0,22,30,31

LPC_AD319,26, 30,31
LPC_AD219,26, 30,31
LPC_AD119,26, 30,31
LPC_AD019,26, 30,31

PLT_RST#7,17,18, 20,22,24,26,30,3 1

12

1U_0603_10V4Z

2

3

2

3

2

3

1

2

KSO[0. .13]

+RTCVCC

C69

KSI_D_3

KSI_D_11

KSI_D_4

KSI_D_12

KSI_D_13

KSI_D_4
KSI_D_5
KSI_D_6

0.1U_0402_16 V4Z

LPCPD#
ACCEL_IN T_KBC

2

1

C51

KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13

KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7

TP_CLK
TP_DATA
KBD_CLK
KBD_DATA
PS2_CLK
PS2_DATA

PM_CLKRU N#
SIRQ
CLK_PC I_EC
RUNS CI_EC#

LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0

LPC_FRAME#
PLT_RST#

CR Y1
CR Y2

1

C67

0.1U_0402_16 V4Z

2

KSI_D_3 33

KSI_D_11 17,31,33

KSI_D_4 33

KSI_D_12 31,33

KSI_D_5 33

KSI_D_13 33

4

1

0.1U_0402_16 V4Z

2

U7

17

KSO0

16

KSO1

15

KSO2

14

KSO3

13

KSO4

12

KSO5

10

KSO6

9

KSO7

7

KSO8

6

KSO9

5

KSO10

4

KSO11

3

KSO12/GPIO00/KBRST

2

KSO13/GPIO18

25

KSI0

24

KSI1

23

KSI2

22

KSI3

21

KSI4

20

KSI5

19

KSI6

18

KSI7

26

IMCLK

27

IMDAT

29

KCLK

31

KDAT

32

EMCLK

33

EMDAT

44

CLKRUN#

46

SER_IRQ

43

PCI_CLK

59

EC_SCI#

40

LAD[3]

39

LAD[2]

37

LAD[1]

35

LAD[0]

41

LFRAME#

42

LRESET#

34

LPCPD#/GPIO23

53

XTAL1

54

XTAL2

51

VCC0

1

C36

2

Power Mgmt/ SIRQ

AGND FILTER

D19

KSI6

1

DAP202U_SOT323

1

C34

4.7U_0805_10 V4Z

2

VCC111VCC167VCC181VCC194VCC230VCC238VCC2

Keyboard/Mo use Interface LPC

Bus

AGND

GND92GND79GND65GND45GND36GND28GND

55

C58

1 2

0.1U_0402_16 V4Z

KSI_D_6

2

KSI_D_14

3

8

KSI_D_6 33

KSI_D_14 33

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

1

C75

0.1U_0402_16 V4Z

2

47

General Pur pose I/O In terface

Access Bus Interface

EA Strap#/GPIO26/KSO17

24MHZ_OUT/GPIO19/WINDMON

Miscellaneous

3

1

C79

0.1U_0402_16 V4Z

2

OUT0

OUT1/IRQ8#

OUT7/SMI#

OUT8/KBRST

OUT9/PWM2
OUT10/PWM0
OUT11/PWM1

GPIO01
GPIO02

GPIO03
GPIO04/KSO14
GPIO05/KSO15

GPIO07/PWM3

GPIO08/RXD

GPIO09/TXD

GPIO11/AB2A_DATA

GPIO12/AB2A_CLK

GPIO13/AB2B_DATA

GPIO14/AB2B_CLK
GPIO15/FAN_TACH1
GPIO16/FAN_TACH2

GPIO17/A20M

GPIO20/PS2CLK

GPIO21/PS2DAT

GPIO24/KSO16

GPIO27

AB1A_DATA

AB1A_CLK

AB1B_DATA

AB1B_CLK

PGM Strap/GPIO25

CLOCK

32KHZ_OUT/GPIO22

RESET_OUT#/GPIO06

PWRGD

VCC1_PWRGD

TEST PIN

DMS_LED#/GPIO10

BAT_LED#

PWR_LED#/8051TX

FDD_LED#/8051RX

KBC1021_TQFP100

2006/02/27 2007/02/27

Compal Secret Data

1

2

KBC_PW R_ON

99

GREEN_BATLED#

100

BATSELB_A#

98

KBRST#

97

INV_PWM

96

FAN_PWM

95

CHGCT RL

93

FWP#

82

ON/OFF BTN_KBC#

62

LOW_BAT#

63

KSO14

64

KSO15

66

PM_RSMRST#

68

DIGI_TX

69

DIGI_RX

70

BATCON

71

EC_GPIO12

72

EC_GPIO13

73

THM_MBAY#

74

PCI_SE RR#

75

THM_MAIN#

76

A20M

77

NUM_LED#

78

SLP_S3#

80

GPIO24

1

MODE

57

AB1A_DATA

86

AB1A_CLK

87

AB1B_DATA

84

AB1B_CLK

85

PGM

56

EA#

83

CLK_14M_KBC

48

S_CLK

58

PM_POK

49

PWR_ GD

61

VCC1_P WRGD

60

EC_GPIO19

50

Pin50 250 - - 24MHz_Out

TEST

52

Pin52 250 - - XOSEL

EC_GPIO10

91

AMBER_BATLED#

88

STB_LED#

90

CAPS_LED#

89

EC_GPIO19

EC_GPIO12

EC_GPIO10

S_CLK

MODE

R62

PGM

FWP#

J3

PGM

1 2

NO SHO RT PADS

FWP#

TEST

EA#

Deciphered Date

C78

0.1U_0402_16 V4Z

Pin 57 250 -- MODE

1 2

R925

R926

R927

R929

R1011

1 2

R52

R29

R65

R28

R930

R27

PAD

0_0402_5%

1 2

R78 300_0402_5%250@

Pin91 250 - - nDMS_LED

1 2

1 2

1 2

1 2

0_0402_5%

0_0402_5%@

10K_0402_5%250@

1 2

1K_0402_5%@

1 2

1K_0402_5%@

1 2

1K_0402_5%

1K_0402_5%@

1K_0402_5%@

1K_0402_5%

1

C81

4.7U_0805_10 V4Z

2

+3VL

12

R915

KBC_PW R_ON 40
GREEN_BATLED# 33

BATSELB_A# 39

T43

PAD

FAN_PWM 4
CHGCTR L 39

Pin82 250 - - nFWP

ON/OFF BTN_KBC# 33
LOW_BAT# 20
KSO14 17
KSO15 31,33

PM_RSMRST# 20
DIGI_TX 17
DIGI_RX 17

BATCON 39

ADP_PRES 24,39,4 0
THM_MBAY# 38
PCI_SE RR# 18,22
THM_MAIN# 38

CH751H-40 _SC76

T47

7/19

7/15

R921

CLK_14M_KBC 1 5

PWR_G D 35,3 6,43,44
VCC1_P WRGD 36

10K_0402_5%

D48

CH751H-40 _SC76

7/20

D50

NUM_LED# 26,33
SLP_S3# 20,24,26, 27,28,34,35,39,4 1,42

EAPD 27,28

AB1A_DATA 38
AB1A_CLK 3 8

AB1B_DATA 38
AB1B_CLK 3 8
A_SD 28

Pin56 250 - - PGM
Pin83 250 - - nEA ( pul l up !! )

9/8

AMBER_BATLED# 33
STB_LED# 26,3 1,34
CAPS_LED# 26,31

ADP_I D 44

0_0402_5%

ADP_PS1 44

0_0402_5%

ADP_PS0 44

0_0402_5%

ADP_EN 44

12

12

12

12

9/27

+3VL

2

CLK_TPM 31

1. For normal operation:

Un-install R29,R65

2. For KBC internal ROM flash:

Install R29,R65

BIOS debug port
Place under KB area

21

KB_RST# 19

R919

12

+3VL

10K_0402_5%

21

GATEA20 19

PM_POK 7,20

Pin58 250 - - 32KHz_OUT
Pin49 250 - - Reset Out

+3VL

VCC1_P WRGD

DIGI_TX
DIGI_RX

THM_MAIN#

EC_GPIO12

EC_GPIO13

DIGI_RX

AB1A_CLK
AB1A_DATA
AB1B_CLK
AB1B_DATA

NUM_LED#

CLK_14M_KBC

FWP# PM_POK

R25 10K_0402_5%

VCC1_P WRGD
NUM_LED#
STB_LED#
CAPS_LED#

JP40

1
2
3
4
5
6

ACES_85201-0602@

R916

1 2

210K_0402_1%

R917

1 2

100K_0402_5%

R918

1 2

100K_0402_5%

9/12

1 2

R998 10K_0402_5%

RP1

1 8
2 7
3 6
4 5

4.7K_1206_8P4R_5%

R32

1 2

100K_0402_5%

R922

10_0402_5%

@

1 2

+3VL

@

C892

1 2

10P_0402_50V8K

@

JP31

1
2
3
4
5
6

ACES_85201-0602

1 2

For KBC debugging used.

Title

Size Docume nt Number Re v

Date : Sheet of

Compal Electronics, Inc.

LPC47N1021

LA-3031P

32 49Tuesd ay, Febru ary 28, 2006

1

+3VL

+3VS

+3VL

0.5

FUN BD. FIR & LED BD.

INT_KBD CONN.

11/23

AC97_SDOUT _MDC19

AC97_S YNC_MDC19

KSO1531, 32

LID_SW #9,20

MUTE_LED#28

NUM_LED#26,32

D65

KSO15

1 6

2

KSI_D_13

AC97_S DIN119

+3VS

KSI_D_8
KSI_D_9
KSI_D_10
KSI_D_13

KSO15
LID_SW #
MUTE_LED#
NUM_LED#

NUP5120X6T1_SOT563-6

R904

1 2

33_0402_5%

C880

1000P_0402_50V7K

JP9

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

11

11

12

12

ACES_87212-1200

KSI_D_10

KSI_D_9

5

KSI_D_8

43

AC97_SDOUT _MDC

AC97_S YNC_MDC
AC97_S DIN1_MDC
AC97_RST#_MDC

+3VS

1

1

C881

2

2

0.1U_0402_16 V4Z

IRTXOUT30

IRMODE30

HDD_L ED#19

HDD_HA LTED20

AMBER_BATLED#32

BT_LED29

WL_LED26

STB_LED31

PANEL_FLI P#20

GREEN_BATLED#32

LID_SW #

C1046

0.1U_0402_16 V4Z

+3VS +5VS

IRRX

IRRX30

IRMODE IRMODE
HDD_L ED#

+3VL

HDD_HA LTED HDD_HALTED
AMBER_BATLED#
BT_LED
WL_LED WL_LED
STB_LED
PANEL_FLI P#
GREEN_BATLED# GREEN_BATLED#

1

1

C1047

0.1U_0402_16 V4Z

2

2

JP18

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

11

11

12

12

13

13

14

14

15

15

16

16

17

17

18

18

19

19

20

20

ACES_85203-2002

MDC 1.5 Conn.

JP25

1

GND1

3

IAC_SDATA_OUT

5

GND2

7

IAC_SYNC

9

IAC_SDATA_IN

11

IAC_RESET#

131314141515161617171818191920

1

C882

4.7U_0805_ 10V4Z@

2

2

RES0

4

RES1

6

3.3V

8

GND3

10

GND4

AC97_BITCL K_MDC

12

IAC_BITCLK

TYCO_1-179396-2~D

20

Connector for MDC Rev1.5

+3VS

21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40

+3VALW+3VALW

21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40

IRRX
IRTXOUTIRTXOUT

HDD_L ED#

AMBER_BATLED#
BT_LED

STB_LED
PANEL_FLI P#

220P_1808_3KV

AC97_BITCL K_MDC 19AC97_RST#_MDC19

+3VS+5VS

+3VL

C304

0.1U_0402_16 V4Z

8/1

2

C1053

1

+5VS

1

1

C303

0.1U_0402_16 V4Z

2

2

+3VS

1

C305

0.1U_0402_16 V4Z

2

RJ-11 CONN.

MOD_TIP
MOD_RI NG

2

220P_1808_3KV

C1054

1

MOD_TIP
MOD_RI NG

JP4

1

TIP

2

RING

3

GND

4

GND

ALLTOP_C10134-10204

JP24

1
2

ACES_88231-0200

+3VL

1

C302

0.1U_0402_16 V4Z

2

KSI_D_1432
KSI_D_81 7,32
KSI_D_1231,32
KSI_D_1017,32
KSI_D_032
KSI_D_432
KSI_D_232
KSI_D_132
KSI_D_332

KSI_D_532
KSI_D_632
KSI732
KSI_D_1332
KSI_D_1117,3 1,32
KSI_D_91 7,32

KSI_D_11

4 5

KSI_D_9

3

KSO9

2

100P_1206_8P4C_50V8@

KSO7

4 5

KSO6

3

KSO10

2

KSO1

100P_1206_8P4C_50V8@

KSO11

4 5

KSO0

3

KSO2

2

KSO5

100P_1206_8P4C_50V8

@

CP1

CP3

CP7

KSO[0. .11]32

KSO11
KSO0
KSO2
KSO5
KSI_D_14
KSI_D_8
KSI_D_12
KSI_D_10
KSI_D_0
KSI_D_4
KSI_D_2
KSI_D_1
KSI_D_3
KSO3
KSO8
KSO4
KSO7
KSO6
KSO10
KSO1
KSI_D_5
KSI_D_6
KSI7
KSI_D_13
KSI_D_11
KSI_D_9
KSO9

6
7
81

6
7
81

6
7
81

KSO[0. .11]

JP6

60

30

60

59

29

59

58

28

58

57

27

57

56

26

56

55

25

55

54

24

54

53

23

53

52

22

52

51

21

51

50

20

50

49

19

49

48

18

48

47

17

47

46

16

46

45

15

45

44

14

44

43

13

43

42

12

42

41

11

41

40

10

40

39

39

38

38

37

37

36

36

35

35

34

34

33

33

32

32

31

31

ACES_85203-3002

KSI_D_14
KSI_D_8
KSI_D_12
KSI_D_10

100P_1206_8P4C_50V8@

KSI_D_0
KSI_D_4
KSI_D_2
KSI_D_1

100P_1206_8P4C_50V8@

KSI_D_5
KSI_D_6
KSI7
KSI_D_13

100P_1206_8P4C_50V8

@

KSI_D_3
KSO3
KSO8
KSO4

100P_1206_8P4C_50V8@

30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9

9

8

8

7

7

6

6

5

5

4

4

3

3

2

2

1

1

CP6

4 5
3
2

CP5

4 5
3
2

CP2

4 5
3
2

CP4

4 5
3
2

KSO11
KSO0
KSO2
KSO5
KSI_D_14
KSI_D_8
KSI_D_12
KSI_D_10
KSI_D_0
KSI_D_4
KSI_D_2
KSI_D_1
KSI_D_3
KSO3
KSO8
KSO4
KSO7
KSO6
KSO10
KSO1
KSI_D_5
KSI_D_6
KSI7
KSI_D_13
KSI_D_11
KSI_D_9
KSO9

6
7
81

6
7
81

6
7
81

6
7
81

Power button

+3VL

+3VL

12

R22

ON/O FF#31,34

100K_0402_5%

ON/O FF#

C23

1U_0603_10V4Z

14

13

1

7

2

U5F
SN74LVC14APWLE_TSSOP14

R26

P

1 2

O12I

G

100K_0402_5%

2

G

1

C11

2

1U_0603_10V4Z

+3VL

12

R536

100K_0402_5%

ON/OFF BTN_KBC#

13

D

Q70
2N7002_SOT23

S

ON/OFF BTN_KBC# 32

D42

RB751V_SOD323

1 2

100K_0402_5%

ON/OFF BTN#

21

TrackPoint CONN. TP BD.

2/23

JP14

1

2

R8

+3VALW

ON/OFF BTN# 20

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2006/02/27 2007/02/27

SP_DATA

Compal Secret Data

3
5
7

ACES_87153-0801L

Deciphered Date

SP_CLK

4
6

+5VS

8

UESD3.3DT5G SOT- 723@

TP_DATA32

TP_CLK32

1

D66

2

3

1/12

SP_DATA

SP_CLK

Title

Size Docume nt Number Re v

Date : Sheet o f

+5VS

JP17

TP_DATA

TP_CLK

1
2
3
4
5
6
7
8

ACES_87212-0800

Compal Electronics, Inc.

MDC/KBD/ON_OFF/LID

LA-3031P

33 49Tuesday, F ebruary 2 8, 2006

0.5

A

B

C

D

E

1 1

ON/O FF#31,33

MDO2+25
MDO2-25

MDO0+25
MDO0-25

2 2

3 3

V_3P3_LAN

4 4

LINE_I N_SENSE27

9/8

R527

10K_0402_5%

D_V SYNC16

D_HSYNC1 6

D_DDCD ATA16

D_DD CCLK16

DVI_DETECT17

D_RE D9,16

D_GREE N9,16

D_BLUE9,16

COMPS_CL9,16
CRMA_CL9,16
LUMA_CL9,1 6

ACOCP_E N#44

DCD# 130

RI#130
DTR#130
CTS#130
RTS#130
DSR#130

TXD130
RXD130

LPTSTB#30
LPTAFD#30

LPTERR#30

2

12

G

2

G

ON/O FF#

MDO2+
MDO2-

MDO0+
MDO0-

LAN_ACT#_D OCK
LANLINK_STA TUS#_DOCK

D_ VSYNC
D_H SYNC
D_DDCD ATA
D_DD CCLK
DVI_DETECT

D_RE D
D_GREE N
D_BLUE

DCD# 1
RI#1
DTR#1
CTS#1
RTS#1
DSR#1
TXD1
RXD1

LPTSTB#
LPTAFD#
LPTERR#

LAN_ACT#_D OCK

13

D

Q62
2N7002_SOT23

S

LAN_ACT#

LANLINK_STA TUS#_DOCK

13

D

Q63
2N7002_SOT23

S

LANLINK_STATUS#

KC FBM-L18-453215-900LMA90T_1812

VIN

C72

1000P_0402_50V7K

L10

12

1

2

JP30A

P1G1

83

1

84

2

85

3

86

4

87

5

88

6

89

7

90

8

91

9

92

10

93

11

94

12

95

13

96

14

97

15

98

16

99

17

100

18

101

19

102

20

103

21

104

22

105

23

106

24

107

25

108

26

109

27

110

28

111

29

112

30

113

31

114

32

115

33

116

34

117

35

118

36

119

37

120

38

121

39

122

40

123

41

124

42

125

43

126

44

127

45

JAE_SP03-14588-PCL03

LAN_ACT# 2 4,25

LANLINK_STATUS# 24,25

DOCK VIN

1

C73

1000P_0402_50V7K

2

DOCK_A DP_SIGNAL

DOCK VIN

DETECT

MDO3+
MDO3-

MDO1+
MDO1-

PWR_L ED

1 2

R515 1K_0402_5%

DVI_ DDC_CLK
DVI_DD C_DAT

DVI_TX2-

DVI_TX2+

DVI_TX1-

DVI_TX1+

DVI_CL K-

DVI_CLK+

DVI_TX0-

DVI_TX0+

DOCK _ID

MDO3+ 25
MDO3- 25

MDO1+ 25
MDO1- 25

SLP_S5#_5R

DVI_ DDC_CLK 17
DVI_DD C_DAT 17

DVI_TX2- 17

DVI_TX2+ 17

DVI_TX1- 17

DVI_TX1+ 17

DVI_CLK - 17

DVI_CLK+ 17

DVI_TX0- 17

DVI_TX0+ 17

DOCK _ID 20

DOCK _ID

DOCK_A DP_SIGNAL

DOCK CONN. 184PIN

7/13

EXPCRD_RST#30

+3VS

ADP_SIGN AL 38,44

+3VALW +5VALW

12

R526

10K_0402_5%

PWR_L ED

13

D

Q59

2

2N7002_SOT23

G

S

1 2

1K_0402_1%

STB_LED#26,31,32

SLP_S3#20,24,26,2 7,28,32,35,39,41 ,42

R947

1 2

10K_0402_5%@

R948

LPTACK#30
LPTBUSY30

LPTPE30

LPTSLCT30

LPD730
LPD630
LPD530
LPD430
LPD330
LPD230
LPD130
LPD030

LPTSLCTIN#30

LPTINIT#30

USB20_N620

USB20_P620

USB20_N720

USB20_P720

SER_S HD30

LPTACK#
LPTBUSY
LPTPE
LPTSLCT
LPD7
LPD6
LPD5
LPD4
LPD3
LPD2
LPD1
LPD0
LPTSLCTIN#
LPTINIT#

USB20_N6

USB20_P6

USB20_N7

USB20_P7

SER_S HD
EXPCRD_RST#
DETECT

JP30B

46

46

47

47

48

48

49

49

50

50

51

51

52

52

53

53

54

54

55

55

56

56

57

57

58

58

59

59

60

60

61

61

62

62

63

63

64

64

65

65

66

66

67

67

68

68

69

69

70

70

71

71

72

72

73

73

74

74

75

75

76

76

77

77

78

78

79

79

80

80

81

81

82

82

165

GND

GND

166

GND

GND

167

GND

GND

168

GND

GND

169

GND

GND

170

GND

GND

G2

G2

RING

RING

JAE_SP03-14588-PCL03

128

128

129

129

130

130

131

131

132

132

133

133

134

134

135

135

136

136

137

137

138

138

139

139

140

140

141

141

142

142

143

143

144

144

145

145

146

146

147

147

148

148

149

149

150

150

151

151

152

152

153

153

154

154

155

155

156

156

157

157

158

158

159

159

160

160

161

161

162

162

163

163

164

164

171
172
173
174
175
176

P2

P2

TIP

TIP

KBD_DATA
KBD_CLK
CPPE#
PS2_DATA
PS2_CLK
DOCK_HP S#

DLIN E_IN_L
DLIN E_IN_R

DLINE_OUT_ L
DLINE_O UT_R

PCIE_TXP4

PCIE_TXN4

PCIE_RXP4

PCIE_RXN4

CLK_PC IE_DOCK

CLK_PC IE_DOCK#

PREP#
VA_ON#

12

R66

1K_0402_5%

+5VS

DOCK_MOD_TIPDOCK_M OD_RING

KBD_DATA 32
KBD_CLK 32
CPPE# 15,18
PS2_DATA 32
PS2_CLK 32
DOCK_HP S# 28

DLINE _IN_L 27
DLIN E_IN_R 2 7

DLINE_OUT_ L 28
DLINE_O UT_R 28

PCIE_TXP4 20

PCIE_TXN4 20

PCIE_RXP4 20

PCIE_RXN4 20

CLK_PC IE_DOCK 15

CLK_PC IE_DOCK# 15

PREP# 20,25

1

C59

0.1U_0402_16 V4Z

2

+5VS

1

+

C1035

22U_B_10V

2

7/21

9/27

1

2

R1047

1 2

22K_0402_1%@

C1048
1U_0603_10V4Z@

close to JP30 B.P2

DOCK_MOD_TIP
DOCK_M OD_RING

PREP#

JP29

1
2

ACES_88231-0200

11/24

SLP_S529,35

2

G

12

R529

220K_0402_5%

SLP_S5#_5R

13

D

Q65
2N7002_SOT23

S

11/24

13

D

2

Q109

G

S

2N7002_SOT23@

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2006/02/27 2007/02/27

Compal Secret Data

Deciphered Date

Title

Size Docume nt Number Re v

D

Date : Sheet o f

Compal Electronics, Inc.

SPR Connector

LA-3031P

34 49Tuesday, F ebruary 2 8, 2006

E

0.5

A

B

C

D

E

+5VALW to +5VS Transfer+3VALW to +3VS Transfer

G

RUN ON

SLP_S529,3 4SLP_S341

+5VS+5VALW

1

S

2

S

3

S

4

1

2

0.1U_0402_ 16V4Z

SLP_S5

SLP_S5#

1

C71

2

G

2

+5VALW

C77

10U_0805_10V4Z

12

R135

100K_0402_5%

13

D

Q22
2N7002_SOT23

S

1

S

2

S

3

S

4

G

12

1

2

SLP_S3

SLP_S3#

+3VS+3VALW

1

C132

2

0.1U_0402_16 V4Z

R469

470_0402_5%

C120

.01U_0402_16V7K

+5VALW

2

G

12

R125

100K_0402_5%

13

D

Q19
2N7002_SOT23

S

1

C128

10U_0805_10V4Z

2

1

C86

2

10U_0805_10V4Z

U9

8

D

7

D

6

D

5

D

SI4800D Y_SO8

R139

330K_0402_5%

J1

SLP_S3

2

G

B+

12

2 1
13

D

S

U13

8

D

7

D

6

1

D

C127

5

D

SI4800D Y_SO8

2

10U_0805_10V4Z

RUN ON

12

R138

100K_0402_5%@

Q18
2N7002_SOT23

SLP_S3#20,24,26, 27,28,32,34,39,4 1,42 SLP_S5#2 0,41

1 1

PAD-SHO RT 2x2m

2 2

+2.5VALW to +2.5VS Transfer

+2.5VS+2.5VALW

Q15

SI2306DS-T1 1N_SOT23

D

S

1 3

1

C93
1U_0603_10V4Z

2

RUN ON

1

G

2

C103
1U_0603_10V4Z

2

3 3

Discharge circuit

2

G

Issued Date

+3VS

12

R134

470_0402_5%

13

D

S

C

Q17
2N7002_SOT23

+0.9VS +1.5VS

12

R188

470_0402_5%

13

SLP_S3

4 4

D

Q27

2

2N7002_SOT23

G

S

SLP_S3 SLP_S3 SLP_S3 SLP_S3 SLP_S3

12

R151

470_0402_5%

@

13

D

Q24

2

2N7002_SOT23@

G

S

+1.8V

12

R95

470_0402_5%

13

D

Q14

2

2N7002_SOT23

G

S

+2.5VS

12

R130

470_0402_5%

13

D

Q21

2

2N7002_SOT23

G

S

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

PWR_G D 32,3 6,43,44

+5VS

12

R116

470_0402_5%

13

D

Q16

2

2N7002_SOT23

G

S

2006/02/27 2007/02/27

Compal Secret Data

Deciphered Date

D

Title

Size Docume nt Number Re v

Date : Sheet o f

Compal Electronics, Inc.

DC/DC Circuits

LA-3031P

35 49Tuesday, F ebruary 2 8, 2006

E

0.5

+VCCP

+3VS+3VS

+3VL+3VL

R996

1K_0402_5%

1 2

2

B

R82

330_0402_5%

C

Q99
MMBT3904_SOT23

E

3 1

R931

1K_0402_5%

1 2

560K_0402_5%

+1.5VS

330_0402_5%

1 2

R281

330_0402_5%

2

B

12

R37

R932

2

B

E

1 2

C

Q10

MMBT3904_SOT23

E

3 1

+5VS

330_0402_5%

1 2

C

Q94
MMBT3904_SOT23

3 1

1

12

R43

180K_0402_5%

1

C47

0.1U_0402_16 V4Z

2

+2.5VS+2.5VS

R23

1 2

C

Q93

2

B

E

3 1

14

U5A

P

O2I

G

SN74LVC14APWLE_TSSOP14

7

+3VL

14

5

7

11

MMBT3904_SOT23

R38

1 2

47K_0402_5%

1

2

U5C

P

O6I

G

SN74LVC14APWLE_TSSOP14

+3VL

SN74LVC14APWLE_TSSOP14

14

U5E

P

G

7

C25

0.1U_0402_16 V4Z

O10I

1

2

14

U5B

P

3

O4I

G

SN74LVC14APWLE_TSSOP14

7

C48

0.1U_0402_ 16V4Z

13

D

2

G

S

13

D

2

G

S

+3VS

12

13

D

2

G

S

Q9
2N7002_SOT23

Q2
2N7002_SOT23

R1048
10K_0402_5%

Q110
2N7002_SOT23

2/20

VCCP_O N 41

D8

21

RB751V_SOD323

J2

PAD-SH ORT 2x2m

+3VS

21

12

R47
10K_0402_5%

PWR_G D 32,3 5,43,44

+3VL

12

R24

560K_0402_5%

1

C26

0.1U_0402_16 V4Z

2

EMI Clip PAD

EP1

1

PAD_177X80@

+3VL

12

R7

+3VL

14

U5D

P

9

O8I

G

SN74LVC14APWLE_TSSOP14

7

FM6

FM3

FM1

CF1

FM2

1

CF2

1

1

1

1

CF3

CF5

1

1

1

10K_0402_5%

1

1

VCC1_P WRGD 32

CF6

1

CF4

1

CF8

CF12

CF7

1

CF11

1

13

D

Q3

2

2N7002_SOT23

G

S

FM5

FM4

1

1

CF9

1

CF10

1

9/29

EP2

1

PAD_177X80@

H35
HOLEA

1

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2006/02/27 2007/02/27

Compal Secret Data

Deciphered Date

H29
HOLEA

1

H14
HOLEA

1

H33
HOLEA

1

H2
HOLEA

1

H16
HOLEA

1

H12
HOLEA

1

H10

H3
HOLEA

1

H24
HOLEA

1

H11
HOLEA

1

H9

HOLEA

HOLEA

1

1

H18

H6

HOLEA

HOLEA

1

1

H34

H1

HOLEA

HOLEA

1

1

Title

Size Docume nt Number Re v

Date : Sheet o f

H5
HOLEA

1

H21
HOLEA

1

H13
HOLEA

1

H17
HOLEA

1

H22
HOLEA

1

H26
HOLEA

1

H4
HOLEA

1

H19
HOLEA

1

H27
HOLEA

1

Compal Electronics, Inc.

POK CKT

LA-3031P

H25
HOLEA

1

H15
HOLEA

1

H30
HOLEA

1

36 49Tuesday, F ebruary 2 8, 2006

H28
HOLEA

H23
HOLEA

H31
HOLEA

1

1

1

H32
HOLEA

1

0.5

5

4

3

2

1

AC

VIN

Adapter

D D

in

MAINP WON

+3VALW

APL5508
LDO
(2.5V)

ADP_EN#

REVBLK

SWITCH

+2.5VALW 400mA

ON 5

B+ B+

MAX8734A
DC/DC

CHGCTRL

MAX1908

BATT

BATSELB_A#

C C

ADP_PRES

Charger

(3V/5V)

SHDN#

+3VALWP 3A

+5VALWP 4.5A

MAX8743
DC/DC
(1.8V/1.05V)

B+

+5VAL W

Vcc

+1.5VS

APL5331
LDO
(0.9V)

+1.8VSP 6A
DDR II

SLP_S3

EN

+0.9VS 1.5A

+5 VS

VR _O N

VC C SH DN #

MAX8770
DC/DC
(CPU_CORE)

CPU_CORE
(YONAH PEAK 36A)

SLP_S5#/PWR_GD

ON1/ON2

+1.05VSP 6A

+5 VS

(MEROM PEAK 44A)

Vcc

B B

VIN

CHGCTRL/
BATSELB_A#

VS

BATT

BATT_B

VS 1

A A

REVBLK

MAX1538
Battery
Selector

LM393
ONE SHOT

5

B+

Battery A
8 Cell

Battery
Connector

VS1/V S

VMB_A VMB_B

BATT_VID

CHG/DIS

A

SWITCH

BATT_A

TRAVE L

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

BATT_B

Compal Secret Data

2006/02/27 2007/02/27

4

Battery B
8 Cell

Battery
Connector
B

Deciphered Date

B+

SLP_S3#

3

MAX8578
DC/DC
(1.5V)

EN

+1.5VALW 3A

Title

Size Document Number R e v

Compal Electronics, Inc.

POWER BLOCK DIAGRAM

LA-3031P

Dat e: Sheet o f

2

37 49Tuesday, F ebruary 28, 2006

1

0.5

A

B

C

D

ADP_SI GNAL 34 ,44

PCN 1

1

Low_PWR

9

GND_4

8

GND_3

1 1

7

GND_2

6

GND_1

MH1

MH2

DC+_1

DC+_2

DC-_1

DC-_2

2

3

4

5

PC1

100P_0402_50V8J

FBMA-L18-453215-900LMA90T_1812

12

12

PL1

1 2

PC2
1000P_0402_50V7K

12

PC3

100P_0402_50V8 J

12

PC4

1000P_0402_50V7K

12

PR270
15K_0402_5%

VIN

FOX_JPD113 E-LB103-7F

PCN 2

1

BATT+

SMD

7

8

2 2

SMC

GND

GND

GND

SUYIN_ 200275MR006G1 13ZL

B/I
TS

2
3
4
5

6

100_0402_5%

EC_SMD_A

EC_SMC_A
AB/I_ A

PR4

12

PR5

100_0402_5%

PR1

TS_A

PR3
1K_0402_5%

1 2

12

1K_0402_5%

1 2

PR2 210K_0402_1%

+3VL

12

VMB_A

12

EC_SMD_A1

EC_SMC_A1

PL2

FBMA-L18-453215-900LMA90T_1812

1 2

12

PC5
1000P_0402_50V7K

PC6

0.01U_040 2_25V7K

THM_MAIN# 32

AB1A_DATA 32

AB1A_CLK 32

BATT_A 39

VMB_A

VMB_B

PD3

12

RLS4148_S OD80

PD6

12

RLS4148_S OD80

VS1

PD45

RLS4148_S OD80

12

VS

3 3

PCN 3

1

BATT+

8

GND

7

GND

SUYIN_ 20163S-06G1-K

SMD
SMC

GND

TS

B/I

EC_SMD_B

2

EC_SMC_B

3

AB/I_ B

4

TS_B

5

6

PR15

100_0402_5%

2

+3VL

3

1

PD43
@SM24_SOT23

PR10

12

1K_0402_5%

1 2

PR12
1K_0402_5%

1 2

12

12

PR16

@SM05_SOT23

100_0402_5%

3

2

PR11 210K_0402_1%

PD42

1

EC_SMD_B1

EC_SMC_B1

4 4

A

VMB_B

PL3

FBMA-L18-453215-900LMA90T_1812

1 2

12

PC9
1000P_0402_50V7K

THM_MBAY# 32

AB1B_DATA 32

AB1B_CLK 32

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

B

12

PC10

0.01U_040 2_25V7K

BATT_B 39

2006/02/27 2007/02/27

Compal Secret Data

Deciphered Date

C

Title

Size Docum ent Numb er Re v

Dat e: Sheet o f

Compal Electronics, Inc.

BATTERY CONN

LA-3031P

D

38 49Tues day, Feb ruary 28, 2006

0.5

A

+3VL

12

PR165

12

PR268

47K_0402_5%

13

D

PQ52

2

G

S

D

S

1908LDO

1 2

332K_0402_1%

ADP_PRES

+3VL

12

PR327
100K_0402_5%

PQ81

RHU002N06_SOT 323

13

D

G

S

47K_0402_1%

PR167

47K_0402_1%

RHU002N06_SOT 323

+3VL

PR32

1 2

0_0402_5%

PR33

2

12

7

1U_0805_50V4Z

12

PC27

PC171

0.022U_0402_16V7K

VS1

O

A

12

Travel

PQ53

2

G

PR24

PR28

12

13

91K_0402_1%

1 2

12

100K_0402_1%

CHGCTR L32

PR166

47K_0402_5%

1 1

BATSELB_A#

RHU002N06_SOT 323

12

PC20

1U_0603_10V6K

ACN 44

12

PC21

2 2

0.1U_0402_16V7K

3 3

4 4

PQ73

NDS0610_SOT23

RHU002N06_SOT 323

SLP_S3#

PC19

1 2

1908_REF

0_0402_5%
PR29

VCTL

PR36

1 2

1U_0603_6.3V6M

PC35

+3VL

12

13

D

S

8

PU6B

P

+

-

G

LM393DR_SO8

4

D

1 3

2

1 2

PQ75

13

D

2

G

S

VCTL

PR329

1 2

@13.1K_0402_1%

12

PR328

1 2

@13.1K_0402_1%

PR330

1 2

@0_0402_5%

1M_0402_1%

VCTL

1908_INP

1 2

12

12

PR43

1 2

10K_0402_1%

0.01U_0402_16V7K

CHGCTRL(V)=1. 22( V/A )*I charger(A)
CHGCTRL=0.73~ 3.3V

PR326
470K_0402_1%

PQ80

RHU002N06_SOT 323

2

G

12

PD44

RLS4148_SOD80

5

6

S

G

PR316

1 2

100K_0402_5%

PR317

PQ74

47K_0402_5%

RHU002N06_SOT 323

13

D

S

PU3

1

DCIN

17

CELLS

4

REF

3

CLS

12

REFIN

15

VCTL

13

ICTL

11

ACOK#

8

SHDN#

10

ACIN

9

ICHG

28

IINP

7

CCV

6

PR40

7.32K_0402_1%

12

PC32

PC30

0.1U_0402_16V7K

0.01U_0402_16V7K

PC170

0.022U_0402_16V7K

12

12

PR325
470K_0402_1%

P4

12

PC167

0.22U_0603_16V7K

ADP_PRES

2

G

0.1U_0603_25V7K

27

CSSP

29

TP

26

CSSN

25

DHI

23

LX

21

DLO

24

BST

22

DLOV

2

LDO

19

CSIP

18

CSIN

16

CCI

CCS

5

12

PC31

0.01U_0402_16V7K

+3VL

12

PR324
47K_0402_1%

BATT

PGND

GND

MAX1908ETI+T_QFN28

20

14

VS1

12

8

PU6A

3

P

+

1

O

2

-

G

LM393DR_SO8

4

B

P4

PR20

0.012_2512_1%

1 2

PC14

1 2

PR34

2.2_0402_5%

1 2

1 2

PR35

33_1206_5%

1908LDO

PC28

1 2

PR44

BATT

1 2

0_0402_5%

PC102

0.01U_0402_5 0V4Z

VL

12

B

B+

PC15

1 2

0.1U_0603_25V7K

DLCH G

1 2

1U_0603_10V6K

12

12

PC169

100P_0402_50V8J

PL15

FBM-L11-322513-151LMAT_1210

1 2

PQ4

1

D2

2

D2

3

G1

4

S1/A

AO4916_SO8

LXCHG

BSTCHG

PD15

12

1SS355_SOD323

PC29

1U_0603_10V6K

12

D1/S2/K
D1/S2/K
D1/S2/K

DHC HG

12

12

PC18

4.7U_1206_25V6K

G2

PC22

0.1U_0603_50 V4Z

CC=0.5~3.36A
CV=12.6V(6 CELLS LI-ION)

16.8V(8 CELL LI-ION)

BATT_B

PR323
604K_0402_1%

PR322
1M_0402_1%

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

CHG_B+

PC17

10U_1206_25V6M

8
7
6
5

Issued Date

PL5

1 2

MSS1038-153NLC

C

PQ2
SI4835B DY_SO8

1
2
3 6

ADP_EN#44

PR27

1 2

13

D

S

RHU002N06_SOT 323

8
7

5

4

0.015_2512_1%

12

3K_0402_5%

PQ65

RHU002N06_SOT 323

+3VL

CHR G

12

2

G

13

D

PQ79

S

2006/02/27 2007/02/27

DCIN

PD47

1 2

RLS4148_SOD80

PR455

1 2

@0_0402_5%

2

+3VL

G

SLP_S3#20,24,26, 27,28,32,34,35,4 1,42

BATT

PR312

1 2

12

1 2

PC25

PC23

10U_1206_25V6M

4.7U_1206_25V6K

PQ31

FDS4925_SO8

PR300

DISB

12

12

PR302

2K_0402_5%

13

D

2

G

S

PR321

100K_0402_5%

PQ78

RHU002N06_SOT 323

ADP_PRES

2

G

Compal Secret Data

Deciphered Date

C

8
7

5

PR157

150K_0402_5%

PD46

@

1 2

@RLS4148_SOD80

13

D

S

PQ82

@RHU002N06_SOT323

47P_0402_50V8J

36

241

PQ5

40.2K_0402_1%

PR459

BATT_B38 BATT_A 38

578

604K_0402_1%

3

1

2

4

S1

S2

G2

G1

D2

D1

D2

D1

8

5

7

6

8

5

7

6

PQ32

D2

D1

D2

D1

G2

S1

S2

G1

2

3

1

4

PQ62

RHU002N06_SOT 323

PQ3

SI4835BD Y_SO8

4

12

200K_0402_5%

12

PC172

0.1U_0603_16V7K
PQ76
DTA144EUA_SC70

1 3

47K

47K

2

PC168

1 2

SI4835BD Y_SO8

1 2

PR269
0_0402_5%

FDS4925_SO8

PR299

3K_0402_5%

12

PR301

2K_0402_5%

13

D

2

G

S

VIN

1
2
36

PR156

12

12

PR308

10_1206_5%

PR320

47K_0402_5%

1 2

MAX1538ETI+T_QFN28

ADPPW R

DCIN

12

13

D

PQ48

NDS0610_SOT23

D

S

13

1 2

PR253

887K_0603_1%

G

2

ADPPW R

DCIN

42.2K_0603_0.1%

1 2

1U_0805_50V4Z

12

PC13

PU2

11

ADPIN

12

ADPPWR

13

REVBLK

16

EXTLD

14

ADPBLK

18

DISBAT

17

CHGIN

19

CHGA

20

CHGB

23

DISB

24

DISA

22

BATB

25

BATA

29

GND

PC33

1 2

1000P_0603_50V7K

OUT0

BATSELB_A#

CHR G

2

PQ67

DTC115EUA_ SC70

Travel

ADP_PRES

Title

Size Docume nt Number Re v

Date : Sheet o f

ACDET

PR17

GND

27

1 2

PC34

2

1

10

AIRDET

MINVA

1

PR38

200K_0402_1%

1 2

PR41

1 2

1000P_0603_50V7K

+3VL

5

PU19
74LVC1G86_SOT353

P

A

Y

B

G

3

O4I

1

NC

2

1

1.62K_0603_0.1%

180K_0402_1%

+3VL

+3VL

I0

I1

PR18

12

9

ACDET

CHRG

BATSEL

RELRN

OUT2
OUT1
OUT0

BATSUP

NC2
NC1

VDD

MINVB

2

100K_0402_1%

1 2

4

PU18

SN74LVC1G17DBVR_SOT 23-5

5

P

2

12

G

3

5

PU20

P

4

O

G

TC7SH32FU_ SSOP5

3

Compal Electronics, Inc.

Charger

LA-3031P

D

PR19

5.49K_0603_0.1%

1 2

5

3
4

8
7
6

26

21
15

28

PR256

12

PR257

180K_0402_1%

+3VL

2

G

0.022U_0603_25V7K

12

PD41

PR304

RLS4148_SOD80

CHR G

12

PR279

1M_0402_1%

PR22

1 2

0_0402_5%

OUT1

VS

12

PC26

0.1U_0603_50 V4Z

+3VL

1

PC36

2

1U_0603_10V4Z

12

PR306

200K_0402_5%

13

D

PQ69

RHU002N06_SOT 323

S

PC166

12

10K_0402_5%

470K_0402_1%

12

PC16

0.1U_0402_16V7K

OUT0

12

PR30

RHU002N06_SOT 323

PR311

39 49Tuesd ay, Febru ary 28, 2006

PR310

10K_0402_5%

BATSELB_A#32

OUT2

PR309

0_0402_5%

ADP_PRES24,3 2,40

PR26

1 2

100K_0402_5%

100K_0402_5%

PR313

@100K_0402_5%

ADP_PRES

2

G

1 3

D

S

PQ68

BATCON 32

12

CHGCT RL

1SS355_SOD323

PD39

1 2

12

12

12

0.5

A

B

C

D

E

+3.3V/+5V

B+

1 1

2 2

3 3

12

PL6

FBM-L11-322513-151LMAT_1210

B++

12

PC218

PC48

33P_0603_50V8J

12

12

PC50

2200P_0402_50V7K

10U_1206_25V6M

MSS1038-103NLC

PL18

12

1
2
3
4

D2
D2

D1/S2/K

G1

D1/S2/K
D1/S2/K

S1/A

AO4916_SO8

PQ9

G2

+5VALWP

B++

PC63

1

PR71

+

1 2

2

150U_D2_6.3VM

@10.2K_0402_1%

PR76

0_0402_5%

1 2

PR74

47K_0402_5%

8
7
6
5

12

12

PC66

PC44

0.1U_0603_ 50V4Z

1 2

5HG

1 2

DL5

VL

0.1U_0603_25V7K

PR57

0_0402_5%

LX5

2VREF_1999

PR77

499K_0603_1%

DH5

ADP_PRES24,3 2,39

MAINPW ON

12

12

PC67

0.1U_0603_16V7K

RHU002N06_SOT 323

PR56
0_0402_5%

1 2

PR332

0_0402_5%

1 2

PQ70

BST5A

@0_0402_5%

1 2

1 2

10K_0402_5%

PR331

PR67

2VREF_1999

PR314

13

100K_0402_5%

D

2

G

S

D

S

3

PD17

1

CHP202U _SC70

VL

PC51

4.7U_0805_10 V4Z
PU7

14

BST5

16

DH5

15

LX5

19

DL5

21

OUT5

9

FB5

1

N.C.

6

SHDN#

4

ON5

3

ON3

12

SKIP#

8

REF

12

PC164

0.22U_0603_10V7K

+3VL

12

13

ADP_PRES

2

G

PQ77

RHU002N06_SOT 323

2

1

2

B++

PC52

20

18

V+

LD05

GND

23

PC165

4.7U_0805_10 V4Z

13

D

S

VL

PR287

1 2

47_0402_5%

12

0.1U_0603_50 V4Z

12

13

17

VCC

ILIM3

TON

ILIM5

BST3

DH3
DL3
LX3

OUT3

FB3

PGOOD

PRO#

LDO3

MAX8734AEEI+_QSOP28

10

25

+3VLP

1

PR293
0_0402_5%

2

1 2

2

G

PQ71

RHU002N06_SOT 323

12

2VREF_1999

PC163

1U_0805_16V7K

5

11

28
26
24
27
22

7
2

PC161

0.1U_0603_16V7K

BST3BBST5B

PR289

1 2

1 2

220K_0402_1%

PR291

PR292

1 2

1 2

499K_0402_1%

KBC_PWR_ON 32

PC43

0.1U_0603_50 V4Z

1 2

B++

PR54
0_0402_5%

1 2

BST3A

PR290

220K_0402_1%

499K_0402_1%

DH3

12

PC45

0_0402_5%

2200P_0402_50V7K

PR53

12

PC46

4.7U_1206_25V6K

1 2

PQ8

1

D2

2

D2

3

G1

4

S1/A

AO4916_SO8

3HG

LX3

DL3

D1/S2/K
D1/S2/K
D1/S2/K

8

G2

7
6
5

12

PL7

MSS1038-103NLC

+3VALWP

PC59

1

PR68

1 2

@3.57K_0402_1%

PR75

1 2

0_0402_5%

+

2

150U_D2_6.3VM

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2006/02/27 2007/02/27

Compal Secret Data

Deciphered Date

Title

Size Docume nt Number Re v

D

Date : Sheet o f

Compal Electronics, Inc.

3.3V / 5V

LA-3031P

40 49Tuesday, F ebruary 2 8, 2006

E

0.5

A

1 1

12

12

PC69

PC68

2200P_0402_50V7K

PQ12

AO4422_SO8

8.2K_0603_0.1%

PL9

MSS1038-522NLC

1 2

PQ14

AO4702_SO8

2 2

3 3

+1.8VP

1

+

2

12

PC80

220U_D2_4VM

PC81

4.7U_0805_ 6.3V6K

12

PR456

12

PR457

10K_0603_0.1%

10U_1206_25V6M

5

D8D7D6D

S1S2S3G

4

5

D8D7D6D

S1S2S3G

4

+1.5VS

PU9

10U_0805_10V4Z

RHU002N06_SOT 323

SLP_S335

4 4

1 2

PR427

0_0402_5%

PC175

@0.1U_0402_16V7K

PQ85

13

D

2

G

S

12

12

12

PC87

+1.8V

12

PC88

PR425

1K_0402_1%

10U_0805_10V4Z

12

PR426

1K_0402_1%

12

PC176

0.1U_0402_16V7K

VIN1VCNTL

2

GND

3

VREF

4

VOUT

G2992F1U_SO8

12

PC93
22U_1206_6.3V6M

+0.9VSP

B

0.1U_0603_50 V4Z

PC78

1 2

SLP_S5#20, 35

SLP_S4#20

6

5

NC

7

NC

8

NC

9

TP

1

PD22

3

2

CHP202U _SC70

1 2

BST1.8

PR79

0_0402_5%

12

PR84

0_0402_5%

12

1U_0805_50V4Z

DH1. 8

LX1.8
DL1.8

1 2

PR87

0_0402_5%

1 2

PR441

@0_0402_5%

MAX1845_VCC

+5VALW

PC178
1U_0603_10V6K

PR78

0_0402_5%

PC75

12

0.1U_0603_50 V4Z
PC76

12

PU8

25

BST1

26

DH1

27

LX1

24

DL1

28

CS1

1

OUT1

2

FB1

11

ON1

@0_0402_5%

B++++

1 2

1U_0805_16V7K

4

V+

GND

OVP

8

23

PR160

PR161

0_0402_5%

PC77

MAX1845_VCC

12

22

VCC

MAX8743EEI+T_QSOP28~N

SKIP

6

12

12

PR80

20_0603_5%

1 2

9

VDD

UVP

BST2

DH2

LX2
DL2
CS2

OUT2

FB2

ON2

PGOOD

TON

ILIM2
ILIM1

REF

PR201

10

0_0402_5%

PR90

0_0402_5%

12

PC86

0.22U_0603_10V7K

21

19
18
17
20
16

15
14
12

7
5

13
3

+5VALW

12

12

12

PC71

4.7U_0805_10V6K

BSTVCCP

PR81

0_0402_5%

1 2

BST2VCCP

DHV CCP

1 2

12

0_0402_5%

PR91

100K_0402_1%

C

12

PC79

0.1U_0603_50 V4Z

12

PR82

PR86
0_0402_5%@

PR202
100K_0402_1%

5

4

LXVCCP

DLVC CP

12

5

4

SLP_S3# 20,2 4,26,27 ,28,32,34,35, 39,42

VCCP_ON 36

2/20

D8D7D6D

PQ83

AO4422_SO8

S1S2S3G

D8D7D6D

AO4702_SO8

S1S2S3G

FBM-L11-322513-151LMAT_1210

12

PC219

@220P_0402_50V7K

PQ84

12

12

PC72

33P_0402_50V8J

PL10

2.2UH_IHLP- 2525CZ-01_8A_+-2 0%_2525CZ

1 2

PL8

1 2

12

PC216

2200P_0402_50V7K

12

12

D

PC73

10U_1206_25V6M

PR85

5.1K_0402_1%

PR88

100K_0402_1%

B+

+1.05V_VCCP

1

12

+

PC82

PC83

2

4.7U_0805_ 6.3V6K
330U_D2E_2.5VM

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2006/02/27 2007/02/27

Compal Secret Data

Deciphered Date

C

Title

Size Docume nt Number Re v

Date : Sheet o f

Compal Electronics, Inc.

DDRII/+1.05VSP/+1.8VSP

LA-3031P

D

41 49Tuesd ay, Febru ary 28, 2006

0.5

A

SLP_S3# 20,24,26,27,28,32,34,35,39,41

1 1

PR428
@0_0402_5%

1 2

4.99K_0402_1%

9

DH

EN

LX

DL

BST

12

PR429

1 2

0_0402_5%

12

PC173

@0.1U_0603_16V7K

8

7

5

6

12

1.5V_BST

PR432
0_0402_5%

1 2

1.5VLX

PC180

0.1U_0402_16V7K

1.5V_ DH

8
7
6
5

G2
D1/S2/K
D1/S2/K
D1/S2/K

AO4916_SO8

S1/A

PQ86

D2
D2
G1

1
2
3
4

1.5VDL

12

12

PC174

PR430

0.01U_0402_25V7K

10

PU15

1

FB

OCSET

2

+5VS

12

PR431

1 2

0_0402_5%

PC177

3300P_0402_50V7K

2 2

SS

3

1U_0603_10V6K

VCC

PC179

12

MAX8578

GND

4

PD48

1SS355_SOD323

B

B+

12

PL17
FBM-L11-322513-151LMAT_1210

12

12

PC139

4.7U_1206_25V6K

3.3UH_MPL73 -3R3_6A_20%

1 2

PL16

12

PR433
15K_0402_1%

PC181

1 2

0.033U_0603_25V7K

PR333

1 2

787_0603_1%

12

PR334

499_0402_1%

PC138

33P_0402_50V8J

12

PC217

2200P_0402_50V7K

12

PR434

30_0402_5%

12

PC182

0.1U_0402_16V7K

C

12

PC220

@220P_0402_50V7K

D

+1.5VSP

1

+

PC148

2

220U_B2_2.5VM

+3VALWP

12

PC183

APL5508_SOT89

PU21

2

IN

GND

1

1U_0603_10V6K

(400mA,40mil s ,Via NO.= 1)

+2.5VALWP

3

OUT

12

PC184

4.7U_0805_ 6.3V6K

3 3

PJP2

+1.5VSP

+1.8VP

+1.05V_VCCP

+2.5VALWP

4 4

+3VLP

+0.9VSP

1 2

PAD-OP EN 3x3m

PJP4

PAD-OP EN 4x4m

1 2

PJP11

PAD-OP EN 4x4m

1 2

PJP6

PAD-OP EN 4x4m

1 2

PJP7

1 2

PAD-OP EN 3x3m

PJP9

2 1

PAD-OP EN 2x2m

PJP10

1 2

PAD-OP EN 3x3m

+1.5VS

(3A,120mils ,Via NO.=6)

(6A,240mils ,Via NO.= 12)

+1.8V

(6A,240mils ,Via NO.= 12)

+VCCP

(400mA,40mil s ,Via NO.= 1)

+2.5VALW

(100mA,20mil s ,Via NO.= 1)

+3VL

(2A,80mils ,Via NO.= 4)

+0.9VS

A

+5VALWP

(4.5A,180mil s ,Via NO.= 9)

+3VALWP

(3A,120mils ,Via NO.= 6)

PJP3

1 2

PAD-OP EN 4x4m

PJP5

1 2

PAD-OP EN 4x4m

+5VALW

+3VALW

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2006/02/27 2007/02/27

Compal Secret Data

Deciphered Date

C

Title

Size Docume nt Number Re v

Date : Sheet o f

Compal Electronics, Inc.

2.5VALWP/1.5VSP

LA-3031P

D

42 49Tuesd ay, Febru ary 28, 2006

0.5

5

D D

PR336

13K_0402_5%

NTC

@470KB_0402_5%_ERTJ0EV474J

PH3

12

CPU_V ID05

CPU_V ID15

CPU_V ID25

CPU_V ID35

CPU_V ID45

CPU_V ID55

CPU_V ID65

C C

VGATE7,15,20

CLK_ENABLE#15

PWR_G D32,3 5,36,44

B B

A A

PR351

0_0402_5%

1 2

0_0402_5%
PR352

1 2

1 2

PR353

0_0402_5%

DPRSLPV R7 ,20

H_DPRSTP#4,19

H_PROCHOT #4

H_PSI#5

+3VS

PR349

1.91K_0402_1%

1 2

1 2

PR338 0_0402_5%

PR339 0_0402_5%

PR340 0_0402_5%

PR341 0_0402_5%

PR342 0_0402_5%

PR343 0_0402_5%

PR344 0_0402_5%

PR346 499_0402_1%

PR347 0_0402_5%

PR348 0_0402_5%

PR354

@10K_0402_5%

POUT

12

12

12

12

12

12

1 2

1 2

1 2

1 2

PR350

2K_0402_1%

1 2

PR356 @0_0402_5%

1 2

1 2

PR357 10K_0402_5%

PC187

0.1U_0402_16V7K

1 2

1 2

PR345 71. 5K_0402_1%

1 2

PC188 0.22U_0603_16V7K

7/8

4

+5VS

12

PR335
10_0402_5%

PC201

PC185
1U_0603_16V6K

1 2

VCC

19

6

31

32

33

34

35

36

37

7

12

9

12

PC186470P_0402_50V8J

11

39

40

3

2

1

38

5

4

2.2U_0603_6.3V6K

PU22

Vcc

THRM

D0

D1

D2

D3

D4

D5

D6

TIME

CCV

REF

DPRSLPVR

DPRSTP

PSI

PWRGD

CLKEN

SHDN

VRHOT

POUT

MAX8770GTL+_TQFN40

VSSSENSE5

VDD

TON

BST1

DH1

DL1

PGND1

GND

CSP1

CSN1

DH2

BST2

DL2

PGND2

CSP2

CSN2

GNDS

LX1

FB

CCI

LX2

TP

41

100_0402_5%

1 2

25

8

30

29

28

26

27

18

17

16

12

10

21

20

22

24

23

14

15

13

PC189

PR363

VSSSENSE

BST1_CPU

DH1__C PU

LX1__CPU

DL1__C PU

CSP1__CP U

CSN1_C PU

FB_C PU

CCI _CPU

DH2_ CPU

BST2_CPU

LX2_CPU

DL2__C PU

CSP2_CP U

CSN2__ CPU

1 2

12

12

PR377

200K_0402_5%

1 2

PR376 0_0402_5%

1000P_0402_50V7K

1 2

PC200

0.01U_0402_25V7K

3

BSTM1_CPU

12

PC199

PR364

1 2

BSTM2_CPU

12

PC190

2

CPU_B+

12

12

PC203

PC202

PQ87

D8D7D6D

IRF7413 Z_SO8

S1S3G

S

2

D8D7D6D

PQ89

S1S3G

S

FDS6688S_SO8

2

PR371 0_0402_5%

1 2

1 2

PC195

D8D7D6D

PC192

S1S3G

S

2

D8D7D6D

S1S3G

S

2

PR358 0_0402_5%

1 2

10U_1206_25VAK

12

10U_1206_25VAK

5

0.22U_0603_16V7K

0_0402_5%

0.22U_0603_16V7K

PR450 0_0402_5%

1 2

PQ88

PR370 @3K_0603_1%

PR369 3.65K_0402_1%

1 2

NTC

PR366

@3K_0603_1%

1 2

PR365

20K_0402_1%

PR451 0_0402_5%

PQ91

FDS6688S_SO8

5

FDS6688S_SO8

4

1 2

1 2

1 2

5

4

2

S

2

IRF7413 Z_SO8

D8D7D6D

S1S3G

S

D8D7D6D

S1S3G

DL1__C PU

1 2

PR367
@3K_0603_1%

PQ90

PQ92

DL2__C PU

4

5

4

470P_0402_50V8J

5

4

5

FDS6688S_SO8

4

PC204

10U_1206_25VAK

.36UH_MPC1040 LR36_ 24A_20%

PR375

3.48K_0402_1%

1 2

2.1K_0603_1%

1 2

PC198 0.22U_0603_16V7K

PC197 @0.0 22U_0402_16V7K

1 2

1 2

PR368 100_0402_5%

PC196
4700P_0402_25V7K

1 2

12

PC193

PC194

10U_1206_25VAK

12

PL21

FBM-L11-322513-151LMAT_1210

12

12

2200P_0402_50V7K

1 2

PR374

12

2200P_0402_50V7K

PR361

2.1K_0603_1%

PL19

NTC

PH1

1 2

10KB_0603_5%_ERTJ1VR 103J

1 2

CPU_B+

PL20

.36UH_MPC1040 LR36_ 24A_20%

1 2

PR359

3.48K_0402_1%

1 2

1 2

PC191 0.22U_0603_16V7K

1

+

2

1 2

10KB_0603_5%_ERTJ1VR 103J

B+

PC205

68U_25V_M_R0.44

+VCC_ CORE

VCCSEN SE

NTC

PH2

1

+VCC_C ORE

VCCSENS E 5

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2006/02/27 2007/02/27

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Docum ent Number R ev

2

Date : Sheet o f

+CPU_CORE

LA-3031P

43 49Tues day, Februa ry 28, 2006

1

0.5

5

4

3

2

1

3

2

12

PC209

0.027U_06 03_16V7K

PC215

1U_0603_1 0V +-10% X7R

12

PR415470K_0402_5%

PR447

71.5K_0402_1%

PR420
21K_0402_1%

PR448

3.48K_0402_1%

+5VS

8

PU29A

P

+

-

G

LM393DR_SO8

4

OCP# 4,20

12

PC211

0.1U_0603 _16V7K

PR398

1 2

100K_0402_5%

1

O

1 2

PR399
604K_0603_1%

1 2

1 2

PR449

21K_0402_1%

D D

PR443
10K_0402_5%

PR397

13

2

G

PR458

47K_0402_5%

12

PR396
133K_0402_1%

12

80.6K_0402_1%

PR395

1 2

0_0402_5%

D

PQ96
RHU002N 06_SOT323

S

12

12

+3VS

12

12

12

PR391

330K_0402_5%

+5VS

B

2

12

VIN

12

PR410
220K_0402_5%

12

PR435
1K_0402_5%

E

3

PQ101

C

MMBT3906_SOT23

1

PR411
10K_0402_5%

2

G

12

PR412

220K_0402_5%

12

PR390

3.9K_0402_5%

PD53

12

CH355PT_SO D323-2

12

12

PR446

3.9K_0402_5%
PC214 3900P_0402_50V7K

+3VALW

ADP_ ID 32

12

PR413
47K_0402_5%

ADP_E N 32 ADP_PS1 32

13

D

PQ99
RHU002N0 6_SOT323

S

PR414

100K_0402_5%

1 2

12

PR436
10K_0402_5%

@

PC212 0.22U_0 603_16V7K

1 2

1

12

12

PR409

1 2

PR437
10K_0402_5%

47K_0402_5%

PD52

RLS4148_S OD80

ADP_EN # 39

1908_IN P

PR438

1908_RE F

ADP_SI GNAL

1 2

100K_0402_1%

PR440

1 2

10K_0402_1%

12

12

12

PR404

0_0402_5%

PR444
182K_0402_1%

PR402
1M_0402_5%

1 2

PR445
10K_0402_1%

13

D

2

G

PQ97

S

@RHU002N0 6_SOT323

PC213

VIN

12

12

PR405

22.6K_0402_1%

12

PR406
0_0402_5%

12

PR407
10K_0402_1%

C C

B B

A A

PU28

LMV321M7_SC70-5

12

PR439

11.5K_0402_1%

1000P_0402_50V7K

NDS0610_SOT23

2

3

G

-

4

O

1

+

P

5

+5VS

PQ98

D

S

13

VIN

G

2

5

6

3

2

1M_0402_5%

1 2

8

P

+

-

G

4

8

PU25A

P

+

O

-

G

LM393DR_SO8

4

PR408

PU25B

7

O

LM393DR_SO8

12

8

PU29B

5

P

+

7

O

6

-

G

LM393DR_SO8

4

PR392

1 2

0_0402_5%

PD49

@CH751 H-40_SOD323

1 2

PWR _GD 32 ,35,36,43

2

B

E

1 2

C

3 1

12

PR394

1 2

470K_0402_5%

PR225
0_0402_5%

PQ100

MMBT3904_SOT23

ACN 39

ACOCP_ EN#34

PR416
10K_0402_5%

+5VS+3VS

12

PR417

1M_0402_5%

1 2

PR423

1M_0402_5%

1 2

PR442
10K_0402_5%

VIN

150K_0402_5%

1SS355_SOD323

PR453

1K_0402_5%

+5VS

8

PU26A

3

P

+

2

-

G

LM393DR_SO8

4

+5VS

8

PU26B

5

P

+

6

-

G

LM393DR_SO8

4

DTA144EUA_ SC70

PR454

PD55

12

1

O

7

O

47K

PQ102

47K

2
12

1 2

+3VS

12

+3VS

12

PR424
10K_0402_5%

13

1 2

1 2

ADP_SI GNAL

PR418
10K_0402_5%

ADP_PS0 32

PD54
1SS355_SOD323

PR452
210K_0402_1%

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2006/02/27 2007/02/27

3

Compal Secret Data

Deciphered Date

Title

Size Docum ent Numb er Re v

2

Dat e: Sheet o f

Compal Electronics, Inc.

ADP_OCP

LA-3031P

44 49Tues day, Feb ruary 28, 2006

1

0.5

1

2

3

4

5

EE PIR list

DB Build:

07/19/2005

Page 4 -Rem ove R5 65 an d R566 and discon nect from +VCCP.

Page 1 0 - A dd a 4 7uF c ap on U15H.E 21,F2 1 for re solution o f possible wavy vide o issues..

Page 1 0 - A dd a 4 7uF c ap on R615-2 for resolution of possib le wavy vid eo issues.

1 1

Page 1 6 - A dd R98 8 and R989 to lea ve th e option in the fu ture to ch ange the v alues for
impeda nce ma tching.
Page 2 0 - M ake U2 8C.E23 a test point .

Page 2 7 - C hange DOCK_ HPS# to P ORT_A_SNS at R965
Page 2 7 - d elete R979 and j umper
Page 2 7 - d elete R894 and j umper
Page 2 7 - d elete R900 and j umper
Page 2 7 - C hange CODEC _REF t o MIC_BIAS _B on pin 28 of U14
Page 2 7 - C onnect LINE _IN_SE NSE to pin 27 of JP30A doc king conne ctor
Page 2 7 - C hange R526 fro m 1uF to 0 .1uF
Page 2 7 - R eserve C 917.
Page 2 7 - R eserve R90 1
Page 2 8 - a dd zer o ohm mic b ias op tions to V DDA_CODEC and MIC_BI AS_B
Page 2 8 - a dd inv ertin g fet and PORT_A_ SNS sense signal
Page 2 8 - C hange R252, R253 from 0402 to 0805 p ackage size .

Page 3 2 - R emove R928

Page 3 2 - R emove R538 and di sconnec t net EC_GP IO12 from +3VL.
R emove J10 a nd J12 . EC_ GPIO1 2 should b e directly connected to ADP_PS1

2 2

Page 3 2 - R emove J15 a nd dis connect ne t BATCON f rom OUT0.

Page 3 2 - R emove J11 a nd con nect d iode CH751H -40_SC76 (pin 2) t o EC_GPIO1 3 and pin1 to ADP_PRE S.

Page 3 4 - C onnect JP30A .27 to LIN E_IN_SENSE

07/20/2005

Page 2 8 - C onnect R418 and R 417 si de 1 togeth er to app ly the bias voltage ( VDDA_Codec or the
option al MI C_BIAS _B) t o both the tip and r ing.

Page 3 2 - Re move D62

07/21/2005

Page 2 0 - R emove conne ctions for U SB_OC #3 and USB_O C#4 from t he USB port s and USB_ OC#2 net f rom RP55.

Page 2 0 - R eserve R789 f or Calisto ga A1.

Page 2 0 - C onnect Net PM_EXT TS#0 ( U15B.F2 5) to JP34. 50 and JP1 0.50 for T S.

Page 2 6 - R emove Mini-Card Clip JP38 .

Page 2 6 - R eserve 0-oh m opti on res istor from XMIT _OFF to XM IT_OFF# to bypass Q92

07/22/2005

3 3

Page 1 7 - M odify fingerpri nt signal.

Page 2 0 - C hange PCIE port 5 to PC IE port 4 for the PCIE chan nel for th e dock

07/25/2005

Page 7 - Re serve R586. becau se IMV P6 VR had insta lled a ser ies Resisto r (500-Ohm )

07/27/2005

Page 1 7 - a dd 2 p ins G ND by removi ng B+ _LCD * 1 and LC DVDD *1 an d modify a ll signals except LVD S

Page 2 9 - I nstall D54, D55 and D56 for H P request.

07/28/2005

Page 4 - Ad d C932 and C 933 for EM I request.

Page 2 7 - A dd L78 for EMI request.

07/29/2005

4 4

Page 4 - Mo dify t he th ermal sensor fr om ADM1032 to ADT7461 .

Page11 - Re serve R626 per th e lates t Intel CRB schematic s v1.502

Page19 - Re move + 3VS f rom SATA f or HP requ est.

08/01/2005

Page22 - Mo dify R 957 a nd R95 8 from 2.2K to 100 K for TI r equest.

Page26 - Re serve R950 .

1

2

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

08/03/2005

Page16 - Ad d R991 , R992 and R993 f or EMI.

08/09/2005

Page 2 7 - a dd ope n pul l down resis tor (R 994) optio n on SENSE B for ADI request.

Page 2 7 - d elete C915 and C916 f or ADI req uest.

Page 2 8 - a dd res istor (R995 ) jump er op tion be tween pins 1 and 2 o f Q97 for A DI request .

Page 2 8 - c hange C224 from 1 uF to 4.7uF for ADI r equest.

Page 2 8 - c hange C487, C486 from 4. 7uF to 10uF for ADI r equest.

08/12/2005

Page 1 7 - c hange D62.4 from _USB _VCCA to + 3VS.

08/13/2005

Page 2 8 - c hange the o ption b ypass R995 to bypass Q28

Page 2 8 - C hange C502 and C503 from 0.1u F to 0.22uF

08/15/2005

Page 2 4 - r eserve R856b y Boardcom request.

08/17/2005

Page 2 8 - C hange C502 and C503 from 0.22 uF to 0.1uF

SI-1 Build:

08/19/2005

Page 7 - In stall R587 and R592 for V_DDR_ MCH_REF.

Page 2 6 - M ove +3 VL fr om JP3 7.39 t o JP3 7.45 and move CAPS _LED# from jp37.41 t o JP37.51.

09/08/2005

Page 4 - Ch ange t he Th ermal Sensor U16 back to AD M1032.

Page 1 8 - I nstall R742 to co nnect ACCEL_INT to PCI_PI RQH# (U28B. G7).

Page 2 0 - R 793 on U28C .E20 s hould be NC (with @ sy mbol NOT A CCEL@) to disconnect U28C.E20 f rom ACCEL_ INT.

Page 2 5 - d isconn ect R2 70 & R271 from C320.
Add an other 1000p F 2 t o 3KV capaci tor to ground for R270 & R27 1 connecti on

Page 2 9 - C hange the t iming capaci tor C58 2 on U12 p in 3 from 0.1UF to 0 .001UF

Page 3 2 - R 78 sho uld h ave an "250@ " sym bol and should not be install ed for the 1021.

Page 3 4 - R oute A COCP_ EN# fr om the circ uit to the d ocking con nector JP30 A.29 and r emove net SM_ADPTR.

09/12/2005

Page 2 0 - R emove R792 and R7 93 and disc onnect nets ADP_ID a nd ACCEL_I NT from U2 8C.E20. Ma ke U28C.E2 0 a TP.

Page 3 2 - A dd R99 8 for KBC TX issue.

09/14/2005

Page 1 7, 20 - Con nect JP28.4 0 to U 28.E23 for digitizer sleep pin.

Page 2 6 - i nstall R990 and u n-inst all R 891, R892 and Q92 fo r BIOS code implement .

09/16/2005

Page 1 5 - M odify R660 from 4 75 ohm to 4.7K ohm to meet I CS spec

Page 1 5 - I nstall R639 , R641 to m eet ICS sp ec

Page 1 5 - M odify R642, R644, R647, R653 , R943 , R94 4, R666, R669, R678 , R682, R6 85, R687, R 689, R691, R702,
R705, R713, R714 from 33 oh m to 24 ohm to meet I CS spec

Page 1 5 - N I R643 , R64 5, R64 8, R65 4, R6 59, R6 61, R 662, R663, R667, R670 , R679, R6 83, R686, R688, R690,
R692, R703, R706, R708 , R709 , R981, R9 82 to meet ICS spec

Page 1 9 - C hange R754, R755, R756, R757 , R759, R760, R765 , R766 fro m 33Ohm to 39Ohm.
Add 39 Ohm s eries resis tors to AC97_SDIN 0, AC97_SDI N1.

Issued Date

2006/02/27 2007/02/27

3

Compal Secret Data

Deciphered Date

4

Title

Size Docume nt Number Re v

Date : Sheet of

Compal Electronics, Inc.

H/W2 EE Dept. PIR SHEET

LA-3031P

5

45 49Tuesd ay, Febru ary 28, 2006

0.5

1

2

3

4

5

EE PIR list (II)

9/21/2005

Page 2 7 - I nstall 10K ohm re sistor in t he R898 l ocation an d install R901 with 0 ohm.

Page 2 8 - R esisto r R99 5 shou ld be placed f rom gate of Q28 to dr ain pin 1

9/23/2005

Page 2 2 - A dd dam ping resistor on SD_DAT/ SD_CMD.

1 1

Page 2 3 - M odify R983 from 4 .7K to 33 ohm for C ARDBUS issu e.

9/27/2005

Page 1 0 - A dd pla cehol der fo r 47uF capa citor at R61 6.2 to GND and R617.2 to GND fo r bulk cap acitance
on +3V S_TVD ACB and +3VS_TVDA CA.

Page 2 4 - D isconn ect P LT_RST from U6A.C 2. Add circuit shown for PLT_RST#_ LAN and con nect signa l
PLT_RS T#_LA N to U6A. C2.

Page 2 6 - A dd cir cuit for +3 VS_MIN I. Ad d pads for JP37.24 t o +3VS and +3VALW.

Page 2 9 - A t R454 .2 no de, ad d plac eholder NI for @0.1u F cap to G ND.

Page 3 1 - A dd CLK _TPM signal at R9 29.1 with N I @0Ohm option. Connect th is to U47.1 3 with ano ther
NI @0O hm op tion on this pin.

Page 3 4 - A t JP30 B.P2, add p lacehol der for 22u F NI @ cap acitor.

9/28/2005

Page 2 5 - M odify C320 and C9 34 from 1 000p 3KV t o 2200p 2KV .

9/29/2005

2 2

Page 2 2 - A dd the term inatio n resi stor fo r SD card o vershot an d undersho t.

Page 2 7 - i nstall R965 to fi x the issue of "i nternal speaker n o sound" t hat found o n all DB-B M/B.

Page 3 6 - R emove the PGD_I N circuit

Page 3 6 - R emove the VGA TE_INTEL c ircuit

10/04/2005

Page 1 5 - M ove PC IE_LO M/PCIE _LOM# from SCRCLKT1/ C1 to SRCCL KT2/C2 (U2 5.22, U25. 23).

Page 2 4 - A dd Cir cuits to p revent leak age fr om BCM575 3M and is u rgent to i mplement i n SI-1.

Page 2 4 - R emove R656 and di sconne ct fro m +3VS and connect C LKREQA# to circuit

Page 2 4 - A dd 0-O hm NI resis tors o n ICH_ SMBCLK and ICH_SMBDA TA on U6A.D 9/D8.
This i s to leave I2C d isconn ected and reser ved for AS F implement ation.

10/06/2005

Page 7 - ad d 0-Oh m jum per Inst alled for DDR_THERM#.

Page 2 2 - A t U23B .G6, add O- Ohm ju mper to +S1_V CC. Chang e R829 to 0-Ohm and NI R829.

Page 2 4 - C hange U44 f rom AT 24C512 N (51 2kB) to AT 24C64A whi ch is a 64k bit EEPROM .

3 3

10/07/2005

Page 1 8 - C hange U39.5 and U40.5 to +3VALW.

Page 2 4 - A dd 4.7 kOhm pulldo wn to GND on LO M_LOW_PWR U6A.J5 andN I U43.

Page 2 4 - C hange R865.1 r ail to +3V ALW

10/11/2005

Page 2 0 - m odify R522 from 1 0K to 100k an d the rail from V_3P 3_LAN to + 3VALW

Page 2 4 - I nstall 4.7k Ohm Pu llup R esist ors to +V_ 3P3_LAN at R1013.2 an d R1014.2.

Page 2 5 - C hange R871 to 10 K-Ohm.

11/10/2005

Page 1 5 - R eserve the workar ound circ uit for MA XIM IC issu e.

Page 2 0 - S wap PA NEL_F LIP# f rom GP IO39 to GPIO12 an d add a pu ll-up resi stor.

11/14/2005

Page 1 7,20, 29 - C hange USB20 _P1, N 1 to No Con nects. Connect U SB20_P2,N2 to Fingerp rint. Chan ge JP11.2

4 4

Page 2 5 - A dd 4x 12nF 100V c apacit or pl acehold ers at R26 9.2, R270. 2, R271.2, and R272.2 .

Page 2 8 - A dd the R103 4(1Koh m) and the R995(0 Ohm) betwe en EAPD and EAPD#. Ch ange net n ame

11/15/2005

Page 2 0 - M ove LP _EN# from G PIO27 (U28C .B21) to GPIO8 (U28C.E21) . Make U2 8C.B21 a T est Point.

Page 2 4 - A F30 ha ve bl ack sc reen i ssue whe n AC plug-i n(LP_EN# i nactive).

and JP 11.4 from U SB20_ N2/P2 to USB 20_N5 /P5 respe ctively. S wap USB_OC #5 and USB _OC#2.

from E APD# to MUTE_L ED#.

This i ssue is cau sed b y PLT_RS T# dropped to 1.12V.
Change R100 7 from 0 oh m to 2 20K ohm f or solving this issue .

1

2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Add R1 025 ( 10k oh m) in PLT _RST#_LAN.

11/17/2005

Page 2 4 - A dd C10 44 (0 .1uF cap .) to GND at Q57.2.

Page 2 5 - C hange C1040 , C104 1, C10 42, C 1043 i n series with R269- 2, R270-2, R271-2, a nd R272-2.

INSTAL L C10 40, C1 041, C1042, and C1043. Remove C 934.

Connec t C32 0 to R 269-1 , R270- 1, R271-1, and R272-2 .

11/18/2005

Page 2 5 - C hange C1040 ,C1041 ,C1042 ,C1043 valu e from 12n F to 10nF.

Page 2 4 - C hange Q103. 1 net na me to LOM_ PCIE_WAKE#.

Page 2 0 - C hange Q77.3 net n ame to LOM_P CIE_WAKE# and discon nect from R 796.1.

Instal l R79 6 and give R796.1 ne t name PCI E_WAKE#.

Page 2 4 - C hange C1044 to no stuff.

11/22/2005

Page 2 4 - N I C826 ,R859 ,C828, R1017, R1016, R101 8, R1020 a nd Q105.

Revers e Q10 3.1 to LAN_ WAKE# and Q103.3 to LOM_PC IE_WAKE#.

NI R10 21 an d Inst all R 1022. +3VS should be powering this Schm idt Trigge r.

Remove R102 3, we don't need this o ption. Connect N IC_PD_N to D63.1 dir ectly.

At Q86 .1, a dd 0-O hm(R1 037) I nstall ed option and call output NIC_ PD_N.

Add Op tion 10K oh m(R10 36) Pu llup a t Q86.1 but NI and pull-up t o V_3P3_LA N.

Add a NI Ze ner Di ode R B751V_ SOD23(D 64) in para llel with R1007.

11/23/2005

Page 2 1 - C hange C753 to 2 20uF 6.3V.

Page 1 7 - C hange the L CD Pow er Circuit from AF a nd Caymus.

Delete R12, R474 a nd C2 8. Add R1038 ,R1039 and C1045. No install C 20.

On JP2 8.40, add 0 -Ohm j umper on D IGI_SLEEP.

Page 1 8 - C hange U39.5 and U 40.5 t o +3VS. In stall R742 and NI R7 41.

Page 1 9 - R emove R984 and di sconne ct from +3 VS. Make U28A.AA5 a TP.

Page 2 0 - C hange R522.2 to V_3P3_LAN .

Page 3 3 - A dd fun ction board ESD s olution. A dd C1046,C 1047 and D 65.

11/24/2005

Page 1 7 - A dd 0-O hm Ju mper o n JP28.18 a lso (DIG_R ESET).

Page 2 0 - C hange R522.2 to +3VALW.

Page 3 4 - C hange R529 to 220 K and at no de SLP _S5#_5R a dd 2N7002 FET (NI) p in 1, pin 3 to GND,

and Pi n 2 o utput shoul d have 1uF 1 0V Ca p to G ND NI, and 22KOhm ser ies NI. C onnect out put

of 22K to PRE P#.

Page 2 0 - A dd LAN LINK_ STATUS # isol ation circu it.Cange U26C.R4 (GP IO14) to L ANLINK_STA TUS#_SB.

Add 0- Ohm o ption NI to bypas s this circ uit if nec essary.

Page 1 9 - C hange C516 and C5 28 fro m 10pf t o 15pf to s olve the R TC issue.

Page 2 4 - O n DC m ode w ithout LAN c able plugge d, system dose not p rovide pow er for LAN chip.

So LAN LINK_ STATUS # wil l be dri ven low by LAN chip.

We wil l add isola tion CKT to sol ve this is sue.

Add R1 042,R 1043,R 1044,R1046 ,Q108.

11/29/2005

Page 2 9 - C hange C582 from 0.001 uF to 0.04 7uF.

Page 2 6 - J 9 shor t and J10 o pen to solv e that 3.3V Aux power is not presen t on Mini Card slot.

12/09/2005

Page 2 8 - A dd Q28 and delete R1034 because au dio driver not ready .

Page 2 9 - C hange C582 from 0.047u F to 1500p F.

01/04/2006

Page 6 - Re serve C625 and C6 29 to sol ve PCA Aco ustic Noise .

Page 2 6 - A dd C10 49 to so lve EMI is sue.

Page 2 6 - S hort J 10 an d un-s hort J9 to fix WLAN l eakage.

2006/02/27 2007/02/27

3

Compal Secret Data

Deciphered Date

4

Title

Size Docume nt Number Re v

Date : Sheet of

Compal Electronics, Inc.

H/W2 EE Dept. PIR SHEET 2

LA-3031P

46 49Tuesd ay, Febru ary 28, 2006

5

0.5

1

2

3

4

5

EE PIR list (II)

1/10/2006

Page 2 6 - C hange J10.1 from +3VS t o V_3 P3_LAN to en sure that WoWLAN is s upported b ut no leak age on DC.

1/12/2006

Page 1 5 - R eserve C105 0, C1051 and C1052 for EMI.

Page 1 6 - A dd L79 , L80 and L81 to fix EMI issue.

1 1

Page 2 4 - C hange RDAC R858 fr om 1.24kOh m to 1.21kO hm.

Page 2 9 - C hange R513 to 1kO hm, C5 82 to 2200p F and C102 to 220uF.

Page 3 3 - R eserve D66 on TP_DA TA / TP CL K for EMI.

Page 3 3 - A dd C10 53 an d C105 4 on MO D_TIP / MOD _RING near RJ-11.

2/20/2006

Page 3 6 - A dd the circ uit fo r powe r seque nce timing between + 1.5VS and VCCP.

2 2

3 3

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

1

2

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/02/27 2007/02/27

Compal Secret Data

Deciphered Date

Title

Size Docume nt Number Re v

4

Date : Sheet of

Compal Electronics, Inc.

H/W2 EE Dept. PIR SHEET 3

LA-3031P

47 49Tuesd ay, Febru ary 28, 2006

5

0.5

5

Version Change List ( P. I. R. List ) for Power Circuit

Version Change List ( P. I. R. List ) for Power Circuit

Version Change List ( P. I. R. List ) for Power CircuitVersion Change List ( P. I. R. List ) for Power Circuit

Requ

Request

IIIItem

tem Issue Descr

Pa ge#

temtem

D D

1111 44

ge# Tit

PaPa

ge#ge#

44 HP

4444

Tit le

le

TitTit

lele

ADP _OCP

_OCP 7/29

ADPADP

_OCP_OCP

Da te

DaDa

7/29 PC212 chang

7/297/29

te

tete

RequRequ
Owner

Owner

OwnerOwner

HPADP

HPHP

4

est

estest

PC212 change from 2200pF to 0.22uF

PC212 changPC212 chang

Issue Description

Issue DescrIssue Descr

e from 2200pF to 0.22uF

e from 2200pF to 0.22uFe from 2200pF to 0.22uF

iptionDa

iptioniption

3

Solut

Solution Description

ion Description RRRRev.

SolutSolut

ion Descriptionion Description

PC212 chang

PC212 change from 2200pF to 0.22uF

PC212 changPC212 chang

2

e from 2200pF to 0.22uF

e from 2200pF to 0.22uFe from 2200pF to 0.22uF

1

ev.Pa

ev.ev.

2222 44

3333 44

4444 44

C C

6666 39

7777 39

8888 44

9999 44

10

10 44

1010

B B

11

11 44

1111

44 ADP

4444

44 ADP

4444

44 ADP

4444

41 1.0

4141

39 Charger/OCP

3939

39 Charger/OCP

3939

44 ADP

4444

44 ADP

4444

44 ADP

4444

44 ADP

4444

ADP _OCP

_OCP 7/29

ADPADP

_OCP_OCP

ADP _OCP

_OCP 7/29

ADPADP

_OCP_OCP

ADP _OCP

_OCP 7/29

ADPADP

_OCP_OCP

1.05V/1.8VP

5V/1.8VP Intel modify DDR2 spec can not less

1.01.0

5V/1.8VP5V/1.8VP

Charger/OCP 11

Charger/OCPCharger/OCP

Charger/OCP 11

Charger/OCPCharger/OCP

ADP _OCP

_OCP 11

ADPADP

_OCP_OCP

ADP _OCP

_OCP 11

ADPADP

_OCP_OCP

ADP _OCP

_OCP 11

ADPADP

_OCP_OCP

ADP _OCP

_OCP 11

ADPADP

_OCP_OCP

7/29 HP

7/297/29

7/29 HP

7/297/29

7/29 HP

7/297/29

10/3

10/3 In

10/310/3

11 /14

/14 H P

1111

/14/14

11 /14

/14 H P

1111

/14/14

11 /14

/14 H P

1111

/14/14

11 /14

/14 H P

1111

/14/14

11 /14

/14 H P

1111

/14/14

11 /14

/14 H P

1111

/14/14

HP PR416 cha

HPHP

HP PR449 cha

HPHP

HP PC211 change fr

HPHP

Intel

tel41

InIn

teltel

HP Rem

HPHP

HP PR36 chang

HPHP

HP PR390 cha

HPHP

HP PC209 c

HPHP

HP PR399 cha

HPHP

HP PC21

HPHP

PR416 cha nge from 10K to 3.3K

PR416 chaPR416 cha

PR449 cha nge from 3.3K to 10K

PR449 chaPR449 cha

PC211 change from 2.2uF to 10U_0805_6.3V6M

PC211 change frPC211 change fr

Intel modify DDR2 spec can not less than 1.75V.

Intel modify DDR2 spec can not less Intel modify DDR2 spec can not less

Remove PQ82 and PD46

ove PQ82 and PD46 Rem

RemRem

ove PQ82 and PD46ove PQ82 and PD46

PR36 change from 560k to 1M.

PR36 changPR36 chang

PR390 cha nge from 27K to 3.9K_5%

PR390 chaPR390 cha

PC209 change from 0.22uF to 0.027uF

PC209 cPC209 c

PR399 cha nge from 649K to 604K

PR399 chaPR399 cha

PC211 change from 10uF to 0.1uF X7R

PC21PC21

nge from 10K to 3.3K PR416 cha

nge from 10K to 3.3Knge from 10K to 3.3K

nge from 3.3K to 10K PR449 cha

nge from 3.3K to 10Knge from 3.3K to 10K

om 2.2uF to 10U_0805_6.3V6M PC211 change fr

om 2.2uF to 10U_0805_6.3V6Mom 2.2uF to 10U_0805_6.3V6M

than 1.75V. Modify 1.8VP

than 1.75V.than 1.75V.

e from 560k to 1M. PR36 chang

e from 560k to 1M.e from 560k to 1M.

nge from 27K to 3.9K_5%

nge from 27K to 3.9K_5%nge from 27K to 3.9K_5%

hange from 0.22uF to 0.027uF

hange from 0.22uF to 0.027uFhange from 0.22uF to 0.027uF

nge from 649K to 604K

nge from 649K to 604Knge from 649K to 604K

1 change from 10uF to 0.1uF X7R

1 change from 10uF to 0.1uF X7R1 change from 10uF to 0.1uF X7R

PR416 cha nge from 10K to 3.3K

PR416 chaPR416 cha

PR449 cha nge from 3.3K to 10K

PR449 chaPR449 cha

PC211 change from 2.2uF to 10U_0805_6.3V6M

PC211 change frPC211 change fr

Modify 1.8VP soultion from fix mode to adjustable mode.

Modify 1.8VPModify 1.8VP

Remove PQ82 and PD46

ove PQ82 and PD46

RemRem

ove PQ82 and PD46ove PQ82 and PD46

PR36 change from 560k to 1M.

PR36 changPR36 chang

PR390 cha

PR390 cha nge from 27K to 3.9K_5%

PR390 chaPR390 cha

PC209 c

PC209 change from 0.22uF to 0.027uF

PC209 cPC209 c

PR399 cha

PR399 cha nge from 649K to 604K

PR399 chaPR399 cha

PC21

PC211 change from 10uF to 0.1uF X7R

PC21PC21

nge from 10K to 3.3K

nge from 10K to 3.3Knge from 10K to 3.3K

nge from 3.3K to 10K

nge from 3.3K to 10Knge from 3.3K to 10K

om 2.2uF to 10U_0805_6.3V6M

om 2.2uF to 10U_0805_6.3V6Mom 2.2uF to 10U_0805_6.3V6M

soultion from fix mode to adjustable mode.5555

soultion from fix mode to adjustable mode. soultion from fix mode to adjustable mode.

e from 560k to 1M.

e from 560k to 1M.e from 560k to 1M.

nge from 27K to 3.9K_5%

nge from 27K to 3.9K_5%nge from 27K to 3.9K_5%

hange from 0.22uF to 0.027uF

hange from 0.22uF to 0.027uFhange from 0.22uF to 0.027uF

nge from 649K to 604K

nge from 649K to 604Knge from 649K to 604K

1 change from 10uF to 0.1uF X7R

1 change from 10uF to 0.1uF X7R1 change from 10uF to 0.1uF X7R

12

12 44

1212

13

13 44

1313

14

14 44

1414

15

15 44

1515

A A

16

16 44

1616

44 ADP

4444

44 ADP

4444

44 ADP

4444

44 ADP

4444

44 ADP

4444

ADP _OCP

ADPADP

ADP _OCP

ADPADP

ADP _OCP

ADPADP

ADP _OCP

ADPADP

ADP _OCP

ADPADP

5

_OCP 11

_OCP_OCP

_OCP 11

_OCP_OCP

_OCP 11

_OCP_OCP

_OCP 11

_OCP_OCP

_OCP 11

_OCP_OCP

11 /14

1111

11 /14

1111

11 /14

1111

11 /14

1111

11 /14

1111

/14 H P

/14/14

/14 H P

/14/14

/14 H P

/14/14

/14 H P

/14/14

/14 H P

/14/14

HP PR411 cha

HPHP

HP PR420 cha

HPHP

HP R448 ch

HPHP

HP PR416 cha

HPHP

HP PR449 cha

HPHP

PR411 cha nge from 47K to 10K_5%

PR411 chaPR411 cha

PR420 cha nge from 10K to 21K_1%

PR420 chaPR420 cha

R448 change from 11.5K to 3.48K_1%

R448 chR448 ch

PR416 cha nge from 3.3K to 10K_5%

PR416 chaPR416 cha

PR449 cha nge from 10K to 21K_1%

PR449 chaPR449 cha

4

nge from 47K to 10K_5%

nge from 47K to 10K_5%nge from 47K to 10K_5%

nge from 10K to 21K_1%

nge from 10K to 21K_1%nge from 10K to 21K_1%

ange from 11.5K to 3.48K_1%

ange from 11.5K to 3.48K_1%ange from 11.5K to 3.48K_1%

nge from 3.3K to 10K_5%

nge from 3.3K to 10K_5%nge from 3.3K to 10K_5%

nge from 10K to 21K_1%

nge from 10K to 21K_1%nge from 10K to 21K_1%

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

PR411 cha

PR411 cha nge from 47K to 10K_5%

PR411 chaPR411 cha

PR420 cha

PR420 cha nge from 10K to 21K_1%

PR420 chaPR420 cha

R448 ch

R448 change from 11.5K to 3.48K_1%

R448 chR448 ch

PR416 cha

PR416 cha nge from 3.3K to 10K_5%

PR416 chaPR416 cha

PR449 cha

PR449 cha nge from 10K to 21K_1%

PR449 chaPR449 cha

2006/01/10 2007/01/10

Compal Secret Data

nge from 47K to 10K_5%

nge from 47K to 10K_5%nge from 47K to 10K_5%

nge from 10K to 21K_1%

nge from 10K to 21K_1%nge from 10K to 21K_1%

ange from 11.5K to 3.48K_1%

ange from 11.5K to 3.48K_1%ange from 11.5K to 3.48K_1%

nge from 3.3K to 10K_5%

nge from 3.3K to 10K_5%nge from 3.3K to 10K_5%

nge from 10K to 21K_1%

nge from 10K to 21K_1%nge from 10K to 21K_1%

Deciphered Date

2

Title

Size Docume nt Number Re v

Date : Sheet o f

Compal Electronics, Inc.

Changed-List History-1

LA-3031

1

48 49Tuesday, F ebruary 2 8, 2006

0.4

5

Version Change List ( P. I. R. List ) for Power Circuit

Version Change List ( P. I. R. List ) for Power Circuit

Version Change List ( P. I. R. List ) for Power CircuitVersion Change List ( P. I. R. List ) for Power Circuit

Requ

Request

Da

Pa ge#

tem

temtem

D D

17

17 HP

1717

18

18 44

1818

19

19

1919

20

20

2020

21

21 02

2121

ge#IIIItem

PaPa

ge#ge#

44 11

4444

44 HP

4444

41

41 01

4141

40

40 3.3V/5V

4040

41

4141

Tit

Tit le

le

TitTit

lele

ADP _OCP

_OCP Add new 47K_5% resistor

ADPADP

_OCP_OCP

ADP _OCP

_OCP 11

ADPADP

_OCP_OCP

0.9VSP

VSP

0.90.9

VSPVSP

3.3V/5V HP

3.3V/5V3.3V/5V

1.05V41

1.05V1.05V

Da te

DaDa

11 /14

1111

11 /14

1111

01 /10

0101

02 /27

0202

02 /27

0202

RequRequ

tePa

tete

Owner

Owner

OwnerOwner

/14ADP

/14/14

/14 Add new

/14/14

/10 CCCCompal

/10/10

/27

/27/27

/271.05V

/27/27

HP44

HPHP

HPADP

HPHP

ompal Change PU9 from APL5

ompalompal

HP02

HPHP

HP

HP

HPHP

4

est

estest

Add new 47K_5% resistor in series with PR415-2

Add new 47K_5% resistorAdd new 47K_5% resistor

Add new 1uF X7R capacitor from PR415-2 to GND

Add newAdd new

Change PU9 from APL5331 to G2992F1U

Change PU9 from APL5Change PU9 from APL5

WW

WW AN noise issue

WWWW

WW AN noise issue

WWWW

1uF X7R capacitor from PR415-2 to GND

1uF X7R capacitor from PR415-2 to GND 1uF X7R capacitor from PR415-2 to GND

AN noise issue

AN noise issueAN noise issue

AN noise issue

AN noise issueAN noise issue

Issue Description

Issue DescrIssue Descr

in series with PR415-2

in series with PR415-2 in series with PR415-2

331 to G2992F1U0.9

331 to G2992F1U331 to G2992F1U

iption

iptioniption

3

2

Solution Description

ion DescriptionIssue Descr

SolutSolut

ion Descriptionion Description

Add new 47K_5% resistor

Add new 47K_5% resistor in series with PR415-2

Add new 47K_5% resistorAdd new 47K_5% resistor

Add new

Add new 1uF X7R capacitor from PR415-2 to GND

Add newAdd new

Add new 33pF

Add new 33pF X7R capacitor from PL6,2 to PC59 2.

Add new 33pF Add new 33pF

Add new 2200pF X7R capacito

Add new 2200pF X7R capacitor to parallel PC72

Add new 2200pF X7R capacitoAdd new 2200pF X7R capacito

1uF X7R capacitor from PR415-2 to GND

1uF X7R capacitor from PR415-2 to GND 1uF X7R capacitor from PR415-2 to GND

X7R capacitor from PL6,2 to PC59 2.

X7R capacitor from PL6,2 to PC59 2.X7R capacitor from PL6,2 to PC59 2.

in series with PR415-2

in series with PR415-2 in series with PR415-2

r to parallel PC72WW

r to parallel PC72r to parallel PC72

1

RRRRev.

ev.Solut

ev.ev.

C C

22

22

2222

23

23 1111.5V

2323

24

24

2424

25

2525

26 1111.5V

2626

B B

41

4141

41

41

4141

41

4141

41

4125

4141

41

4126

4141

1.05V

1.05V Change PC

1.05V1.05V

.5V 02

.5V.5V

1111.5V

.5V 02

.5V.5V

1.05V

1.05V HP

1.05V1.05V

.5V 02

.5V.5V

02

02 /27

/27 WW

0202

/27/27

02 /27

/27

0202

/27/27

02 /27

/2741

0202

/27/27

02

02 /28

/28

0202

/28/28

02 /28

/28

0202

/28/28

HP41

HPHP

HP

HP

HPHP

HP

HP

HPHP

HP

HPHP

HP

HP

HPHP

WW AN noise issue

AN noise issueHP

WWWW

AN noise issueAN noise issue

WW

WW AN noise issue

AN noise issue

WWWW

AN noise issueAN noise issue

WW

WW AN noise issue

AN noise issue

WWWW

AN noise issueAN noise issue

EMI

EMI issue

issue

EMI EMI

issueissue

EMI

EMI issue

issue Reserve PC220 220pF X7R capacitor to pa

EMI EMI

issueissue

Change PC73 from 2200pF to 33pF X7R capacitor.

Change PCChange PC

Add new 2200pF X7R capacitor

Add new 2200pF X7R capacitor to parallel PC138

Add new 2200pF X7R capacitorAdd new 2200pF X7R capacitor

Change PC1

Change PC138 from 2200pF to 33pF X7R capacitor.

Change PC1Change PC1

Reserve PC219 220pF X7R capacitor to p

Reserve PC219 220pF X7R capacitor to parallel PC72

Reserve PC219 220pF X7R capacitor to pReserve PC219 220pF X7R capacitor to p

Reserve PC220 220pF X7R capacitor to pa rallel PC138

Reserve PC220 220pF X7R capacitor to paReserve PC220 220pF X7R capacitor to pa

73 from 2200pF to 33pF X7R capacitor.

73 from 2200pF to 33pF X7R capacitor.73 from 2200pF to 33pF X7R capacitor.

to parallel PC138

to parallel PC138 to parallel PC138

38 from 2200pF to 33pF X7R capacitor.

38 from 2200pF to 33pF X7R capacitor.38 from 2200pF to 33pF X7R capacitor.

arallel PC72

arallel PC72arallel PC72

rallel PC138

rallel PC138rallel PC138

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/01/10 2007/01/10

Compal Secret Data

Deciphered Date

Title

Size Docume nt Number Re v

2

Date : Sheet o f

Compal Electronics, Inc.

Changed-List History-2

LA-3031

1

49 49Tuesday, F ebruary 2 8, 2006

0.4