COMPAL LA-3001P Schematics

A

B

COMPAL CONFIDENTIAL

C

D

E

1 1

PCB NO :

LA-3001P

COMPAL P/N :

MODEL NAME :

HAL31(Discrete) & HAL30(UMA)

45140031L11 (For Discrete)
45140031L01 (For UMA)

Bali (DIS&UMA) Schematics Document

2 2

uFCPGA Mobile Yonah
Intel Calistoga + ICH7M

2006-04-14

REV : 0.5 (DELL: X03)

3 3

@ : Nopop Component

1@ : UMA Used Only

2@ : Bali with descrete Used Only

4 4

MB PCB

Part Number Description

DA800004W0L

PCB LA-3001P
REV0.4 MB

BOM NO:
PCB P/N: DA800004W0L

A

45140031L11 (For Discrete)
45140031L01 (For UMA)

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

B

C

D

DELL CONFIDENTIAL/PROPRIETARY

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

Cover Sheet
LA-3001P

173Monday, April 17, 2006

E

0.4

of

A

Compal confidential

Model : Bali

B

C

D

E

Block Diagram

FAN

+FAN1_VOUT

1 1

VGA CONN

+5VRUN

+INV_PWR_SRC

+5VRUN

On LCD Panel

2 2

Camera

+5V_RUN

USB[4]

USB[6]

Left

3 3

USB[7]

page 20

LVDS CONN

+LCDVDD

page 19

TV CONN

page 20

Mini Card 2

WLAN

+3V_RUN
+1.5V_RUN

USB[0]
USB[1]Right

SPDIF

page 29

USB Ports X2 USB Ports X2

+5V_SUS

page 25

+5V_SUS

page 25

+3V_RUN

Thermal

GUARDIAN II
EMC4000

+3V_SUS

page 16page 16

8X32M GDDR3 x2

G72M

+1.22V_GFX_PCIE
+VCC_GFX_CORE

page 44,45,46,47,48,49,50

For Integrity UMA Graphic

PCI Express BUS

+3V_RUN/ +1.5V_RUN 100MHz

Mini Card 1

WWAN

+3V_RUN
+1.5V_RUN

page 29

USB[2]

Bluetooth

page 25

PCI-E 16X

USB[5]

48MHz

48MHz

Pentium-M

Yonah-2M (Merom Support)

+VCCP (1.05V)
+VCC_CORE

uFCPGA CPU

478pin

System Bus

FSB 533/667 MHz

INTEL

Calistoga

+1.5V_RUN
+1.8V_SUS
+VCCP (1.05V)
+3V_RUN
+2.5V_RUN

1466pin BGA

page 10,11,12,13,14,15

DMI

+1.5V_RUN
100MHz

INTEL

+3V_RUN
+3V_SUS
+1.5V_RUN
+VCCP

LPC BUS

+3V_RUN
33MHz

ICH7-M

652pin BGA

page 21,22,23,24

SPI

page 7,8,9

H_D#(0..63)H_A#(3..31)

CPU ITP Port

+VCCP

Memory BUS
(DDR2)

PCI BUS

+3V_RUN 33MHz

Azalia I/F
S-ATA 0/2
ATA100

+1.8V_SUS 400/533 / 667MHz

PCI Express BUS

+3V_RUN/ +1.5V_RUN 100MHz

ATA100

Clock Generator

CK410M+

+3V_RUN

R5C832

+3V_SUS

5 in 1 Card

Reader

page 28 page 29 page 27

page6page 7

DDRII-DIMM X2

BANK 0, 1, 2, 3, 4 ,5 ,6 ,7 ,8

+0.9V_DDR_VTT
+1.8V_SUS

IDSEL:AD17
(PIRQC,D#,GNT#1,REQ#1)

page 17,18

BCM4401KQL

page 28 page 26

+3V_LAN

1394

CONN

ExpressCard CONN

+3V_RUN
+3V_SUS
+1.5V_RUN

IO/B

USB[3]

Azalia Codec

STAC9220

+3V_RUN
+VDDA

IO/B

IDSEL:AD16
(PIRQC#,GNT#4,REQ#4)

RJ45

AMP & INT.
Speaker

+5V_SUS

IO/B

HeadPhone &
MIC Jack

+3V_RUN

IO/B

SMSC SIO
ECE5011

+3.3V_ALW

page 31

BC BUS

Touch Pad

1.8V/0.9V

4 4

page 41

VCORE (IMVP-6)

page 42

+VDD_CORE

page 50

1.5V/1.05V

page 40

DC IN

BATT IN

page 37

Power Sequence

page 33

page 38

Power On/Off

CHARGER

page 43

3V/5V/15V

page 39

A

DC/DC Interface

SW & LED

page 35page 37

B

SMSC KBC
MEC5004

+RTC_CELL
+3.3V_ALW

page 34

SPI

page 30

Int.KBD

page 34

ST M25P80

+3V_SUS

page 30

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

C

+5V_MOD

IO/B IO/B

RJ11

page 27

CD-ROM

S-HDD

+5V_HDD

D

MDC

+3V_SUS

IO/B

On I/O daughter Card

DELL CONFIDENTIAL/PROPRIETARY

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

Block Diagram
LA-3001P

273Monday, April 17, 2006

E

of

0.4

5

4

3

2

1

PM TABLE

D D

power
plane

State

S0

S1

S3

C C

S5 S4/AC

S5 S4/AC don't exist

+5V_ALW
+3.3V_ALW

ON

ON

ON

ON

+15V_SUS
+5V_SUS
+3.3V_SRC
+3.3V_SUS
+1.8V_SUS

ON ON

ON

ON

OFF

OFFOFF

+5V_RUN
+3.3V_RUN
+2.5V_RUN
+1.8V_RUN
+1.5V_RUN
+1.22V_GFX_PCIE
+0.9V_DDR_VTT
+VCC_GFX_CORE
+VCC_CORE
+1.05V_VCCP

ON

OFF

OFF

OFF

ICH7-M

SIO ECE5011

USB PORT#

0
1
2
3
4

JUSB1 (Ext Back Right Side)
JUSB1 (Ext Back Right Side)
Blue Tooth
EXPRESS CARD

CCD Camera
5WWAN
6
7
0
1
2
3
4

JUSB2 (Ext Back Left Side)

JUSB2 (Ext Back Left Side)

None

None

None

None

None

DESTINATION

PCI TABLE

PCI DEVICE IDSEL

REQ#/GNT#

PIRQ

B B

LAN

R5C832

AD17 REQ#2/GNT#2

REQ#3/GNT#3AD16 IRQB

IRQC
IRQD

Lane 1
Lane 2
Lane 3
Lane 4

A A

PCI EXPRESS

DESTINATION
MINI CARD-1 WWAN
MINI CARD-2 WLAN
None
EXPRESS CARD

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

Index and Config.

LA-3001P

373Monday, April 17, 2006

1

0.4

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5

4

3

2

1

ALWON

+5V_ALW

D D

ADAPTER

ALWON

+3.3V_ALW

ENAB_3VLAN

BATTERY

C C

+PWR_SRC

AUX_EN

+3.3V_SRC

SUS_ON

RUN_ON

Charger

SUS_ON

ADP3207

(PU7)

+5V_SUS

RUNPWROK

+VCC_CORE

+3.3V_LAN

+3.3V_SUS

+3.3V_RUN

ISL6227

(PU4)

RUN_ON

+1.5V_RUN

GUARDIAN II

+1.05V_VCCP

+2.5V_RUN

RUN_ON

GFX_RUN_ON

MAX8632

(PU5)

SUSPWROK_5V

+1.8V_SUS

MAX8632/
ISL88550

(PU13)

RUN_ON

+0.9V_DDR_VTT

+VCC_GFX_CORE

+1.22V_GFX_PCIE

B B

SI3456

(IO/B)

HDDC_EN#

SI3456

(IO/B)

MODC_EN#

SI4810

(Q28)

RUN_ON

793475

(IO/B)

AUDIO_AVDD_ON

PL8 & PD8

SI4800

(Q35)

RUN_ON

+1.8V_RUN

+5V_HDD +5V_MOD +5V_RUN +VDDA

A A

L57

(Option)

+15V_SUS

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

Power Rail

LA-3001P

473Monday, April 17, 2006

1

0.4

of

5

4

3

2

1

+3.3V_SUS

+3.3V_RUN

2.2K 2.2K 2.2K 2.2K

ICH_SMBCLK

D D

ICH7-M

C22

ICH_SMBDATA

B22

+3.3V_SUS

87

32 30

2N7002

2N7002

3032

CLK_SCLK

CLK_SDATA

16

CLK GEN.

17

SMBUS Address [D2]

+3.3V_ALW

Express Card

10K 10K

CLK_SMB

10

DAT_SMB +3.3V_ALW

9

C C

SMBUS Address [TBD]

MINI WLAN Card

SMBUS Address [TBD]

MINI WWAN Card

SMBUS Address [TBD]

8

GUARDIAN II

7

SMBUS Address [2F]

197

DIMMA

195

SMBUS Address [A0]

197

DIMMB

195

SMBUS Address [A2]

+3.3V_ALW

8.2K 8.2K

SIO

112

111

SBAT_SMBCLK
SBAT_SMBDAT

+3.3V_ALW

6

LVDS connector

5

Inverter

SMBUS Address [58]

+3.3V_ALW

8.2K8.2K

B B

Macallan IV

8

7

PBAT_SMBCLK
PBAT_SMBDAT +3.3V_ALW

100

3

BATTERY

4

CONN

SMBUS Address [16]

100

9

CHARGER

10

A A

SMBUS Address [12]

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

SMBUS TOPOLOGY

LA-3001P

573Monday, April 17, 2006

1

0.4

of

5

D
1

G S

2

D D

FSC FSB FSA CPU

CLKSEL2 CLKSEL0CLKSEL1

2N7002

3

ICH_SMBDATA<23,29,36> CLK_SDATA <17,18>

+3.3V_RUN

ICH_SMBCLK<23,29,36>

000

00

*

0

0

C C

1

1

1

11

1

0

1

11

00

1

0

1

0

1

+3.3V_RUN

ICH_SMBDATA

ICH_SMBCLK

MHz

266

133

200

166

333

100

400

Reserve

D

1 3

1 3

D

SRC
MHz

100

100

100

100

100

100

100

2.2K_0402_5%~D

S

Q51
2N7002_SOT23~D

G

2

2

G

S

Q50
2N7002_SOT23~D

PCI
MHz

33.3

33.3

33.3

33.3

33.3

33.3

33.3

R589

2.2K_0402_5%~D

12

12

R575

CLK_SDATA

CLK_SCLK

+CK_VDD_A

C573

4.7U_0603_6.3V6M~D

1

2

Place crystal within
500 mils of CK410M

CLK_ICH_48M<23>

CPU_MCH_BSEL0<8,10>

Table : ICS954305AK

CLK_PCI_LOM<26>

CPU_BSEL

B B

91_0402_5%~D

A A

CPU_BSEL2(FSC) CPU_BSEL1(FSB)

133

166

R457

2@

+3.3V_RUN

R453
10K_0402_5%~D

1 2
12

R444

FSA

10K_0402_5%~D@

00

0

XTALIN_CLK_GEN

12

Rd

Pop R451 for 27MHz
output for G72

+3.3V_RUN

5

Rc

R451

10K_0402_5%~D

1 2

PCI_LOM

12

R452

10K_0402_5%~D1@

CLK_PCI_PCCARD<28>

CLK_PCI_5004<30>

1

2@

CLK_ICH_14M<23>

MCH_DREFCLK<10>
MCH_DREFCLK#<10>
CLK_PCI_ICH<21>

XTALIN_CLK_GEN<44>

XTALSSIN_CLK_GEN<44>

Pop Ra,Rb,Rc, Rd for 27MHz output for G72
spectrum input
Routing trace length DOT96/DOT96# <50mil

FCTSEL1
(PIN34)

UMA

Discrete

4

Change to ECJCV50J106M 6.3V10UF 0805 X5R M H:0.85mm, wait CIS symbol.

+3.3V_RUN

BLM21PG600SN1D_0805~D

1

C530

0.1U_0402_16V4Z~D

CLK_SCLK <17,18>

Placec these caps closed to CK410M

+CK_VDD_48

C569

0.047U_0402_16V4Z~D

C552

4.7U_0603_6.3V6M~D

1

2

C166

1 2

27P_0402_50V8J~D

C174

27P_0402_50V8J~D

1 2

CLK_ICH_48M
CPU_MCH_BSEL0

CLK_PCI_LOM PCI_LOM

CLK_PCI_PCCARD PCI_PCCARD

CLK_ICH_14M

MCH_DREFCLK
MCH_DREFCLK#
CLK_PCI_ICH

+3.3V_RUN

XTALIN_CLK_GEN

PIN43

0

DOT96T DOT96C 96/100M_T 96/100M_C

1

27M_out

4

2

BLM21PG600SN1D_0805~D

+CK_VDD_REF

C549

0.047U_0402_16V4Z~D

1

1

2

2

12

X2

14.31818MHz_20P_1BX14318CC1A~D

1 2

390_0402_5%~D

R142 33_0402_5%~D
R141 8.2K_0402_5%~D

1 2

CPU_MCH_BSEL1<8,10>
CPU_MCH_BSEL2<8,10>

R122 33_0402_5%~D

R123 33_0402_5%~D
R125 33_0402_5%~D

R128 33_0402_5%~D

R144 33_0402_5%~D1@

1 2

R152 33_0402_5%~D1@

1 2

R121 33_0402_5%~D

1 2

R120 10K_0402_5%~D

1 2

CLK_ENABLE#<42>

R456

2@

Ra

Rb

R459

2@

1 2

33_0402_5%~D

12

150_0402_5%~D

PIN44

27M SSout

L48

1 2

+CK_VDD_MAIN2

L44

1 2

C543

0.047U_0402_16V4Z~D

1

2

CLK_XTAL_IN

CLK_XTAL_OUT

R119

12

R127 8.2K_0402_5%~D

12

12
12

12

1 2

R464 475_0603_1%~D

DOT96

DOT96#

PIN47 PIN48

SRCT0

3

+CK_VDD_MAIN

1

C579
10U_0805_10V4Z~D

2

1

C542
10U_0805_10V4Z~D

2

R455
1_0603_5%~D

+CK_VDD_REF

1 2

+CK_VDD_48

1 2

R132

2.2_0603_5%~D

FSA
CPU_MCH_BSEL1
FSC

12

PCI_SIOCLK_PCI_5004

CLKREF

DOT96
DOT96# PCIE_MINI1
PCI_ICH

CLK_ENABLE#
CLKIREF

CLK_SCLK

CLK_SDATA

SRCC0

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

place Decoupling as closed physically possible to each VDD oins

1

C554

0.1U_0402_16V4Z~D

2

1

C541

0.1U_0402_16V4Z~D

2

U15

1

VDDSRC

49

VDDSRC

54

VDDSRC

65

VDDSRC

30

VDDPCI

36

VDDPCI

12

VDDCPU

18

VDDREF

40

VDD48

20

XIN

19

XOUT

41

USB_48MHz/FSLA

45

FSLB/TEST_MODE

23

REF0/FSLC/TEST_SEL

34

PCICLK4/FCTSEL1

33

PCICLK3

32

PCICLK2

27

PCICLK1

22

REF1

43

DOTT_96MHz/27MHz

44

DOTC_96MHz/27MHz

37

ITP_EN/PCICLK_F0

39

Vtt_PwrGd#/PD

9

IREF

16

SMBCLK

17

SMBDAT

4

GNDSRC

15

GNDCPU

21

GNDREF

31

GNDPCI

35

GNDPCI

42

GND48

68

GNDSRC

73

THRM_PAD

74

THRM_PAD

75

THRM_PAD

76

THRM_PAD

ICS954305DKLFT_MLF72~D

R470

2.2_0603_5%~D

1 2

1

C200

0.1U_0402_16V4Z~D

2

1

C540

0.1U_0402_16V4Z~D

2

+CK_VDD_A

VDDA
GNDA

PCI_STOP#

CPU_STOP#

CPUT1
CPUC1

CPUT0
CPUC0

CPUT_ITP/SRCT10

CPUC_ITP/SRCC10

SRCT9
SRCC9

CLKREQ9#

SRCT8
SRCC8

CLKREQ8#

SRCT7
SRCC7

CLKREQ7#

SRCT6
SRCC6

CLKREQ6#

SRCT5
SRCC5

CLKREQ5#

SRCT4
SRCC4

CLKREQ4#

SRCT3
SRCC3

CLKREQ3#

SRCT2
SRCC2

CLKREQ2#

SRCT1
SRCC1

CLKREQ1#

LCD100/96/SRC0_T

LCD100/96/SRC0_C

2

1

C575

0.1U_0402_16V4Z~D

2

1

C570

0.1U_0402_16V4Z~D

2

Place near each pin
W>40 mil

Place near CK410+

7
8

H_STP_PCI#

25

H_STP_CPU#

24

MCH_BCLK

11
10

CPU_BCLK

14

CPU_BCLK#

13

6

CPU_ITP#

5

PCIE_VGA CLK_PCIE_VGA

3
2
72

MCH_3GPLL

70

MCH_3GPLL#

69

CLK_3GPLLREQ#

71
66
67
38
63

PCIE_MINI1#

64

MINI1CLK_REQ#

62

PCIE_ICH

60

PCIE_ICH#

61
29
58

PCIE_SATA#

59

SATA_CLKREQ#

57

PCIE_EXPCARD

55

PCIE_EXPCARD#

56

CARD_CLK_REQ#

28

PCIE_MINI2

52

PCIE_MINI2#

53

MINI2CLK_REQ#

26
50
51
46

DOT96_SSC

47

DOT96_SSC#

48

1 2

R158 33_0402_5%~D

1 2

R162 33_0402_5%~D

1 2

R146 33_0402_5%~D

1 2

R154 33_0402_5%~D

1 2

R168 33_0402_5%~D

1 2

R173 33_0402_5%~D

1 2

R184 33_0402_5%~D2@

1 2

R186 33_0402_5%~D2@

1 2

R207 33_0402_5%~D

1 2

R217 33_0402_5%~D

R204 10K_0402_5%~D

1 2

1 2

R215 33_0402_5%~D

1 2

R216 33_0402_5%~D

R473 10K_0402_5%~D

1 2
1 2

R213 33_0402_5%~D

1 2

R214 33_0402_5%~D

1 2

R211 33_0402_5%~D

1 2

R212 33_0402_5%~D

R472 10K_0402_5%~D

1 2
1 2

R209 33_0402_5%~D

1 2

R210 33_0402_5%~D

R124 10K_0402_5%~D

1 2
1 2

R165 33_0402_5%~D

1 2

R172 33_0402_5%~D

R126 10K_0402_5%~D

1 2

1 2

R157 33_0402_5%~D1@

1 2

R161 33_0402_5%~D1@

2

CLK_MCH_BCLK
CLK_MCH_BCLK#MCH_BCLK#

CLK_CPU_BCLK
CLK_CPU_BCLK#

CLK_CPU_ITPCPU_ITP
CLK_CPU_ITP#

CLK_PCIE_VGA#PCIE_VGA#

CLK_MCH_3GPLL
CLK_MCH_3GPLL#

CLK_PCIE_MINI1
CLK_PCIE_MINI1#

CLK_PCIE_ICH
CLK_PCIE_ICH#

CLK_PCIE_SATAPCIE_SATA
CLK_PCIE_SATA#

CLK_PCIE_EXPCARD
CLK_PCIE_EXPCARD#

CLK_PCIE_MINI2
CLK_PCIE_MINI2#

DREF_SSCLK
DREF_SSCLK#

1

1

C574

0.1U_0402_16V4Z~D

2

CLK_CPU_ITP
CLK_CPU_ITP#
CLK_MCH_BCLK
CLK_MCH_BCLK#
CLK_CPU_BCLK
CLK_CPU_BCLK#
CLK_MCH_3GPLL
CLK_MCH_3GPLL#
CLK_PCIE_SATA
CLK_PCIE_SATA#
CLK_PCIE_ICH
CLK_PCIE_ICH#
CLK_PCIE_MINI2
CLK_PCIE_MINI2#
CLK_PCIE_VGA
CLK_PCIE_VGA#
CLK_PCIE_MINI1
CLK_PCIE_MINI1#

H_STP_PCI# <23>
H_STP_CPU# <23>

CLK_MCH_BCLK <10>
CLK_MCH_BCLK# <10>

CLK_CPU_BCLK <7>
CLK_CPU_BCLK# <7>

CLK_CPU_ITP <7>
CLK_CPU_ITP# <7>

CLK_PCIE_VGA <44>
CLK_PCIE_VGA# <44>

CLK_MCH_3GPLL <10>

CLK_MCH_3GPLL# <10>

CLK_3GPLLREQ# <10>

+3.3V_RUN

CLK_PCIE_MINI1 <29>

CLK_PCIE_MINI1# <29>

MINI1CLK_REQ# <29>

+3.3V_RUN

CLK_PCIE_ICH <23>
CLK_PCIE_ICH# <23>

CLK_PCIE_SATA <22>
CLK_PCIE_SATA# <22>

SATA_CLKREQ# <23>

+3.3V_RUN

CLK_PCIE_EXPCARD <36>
CLK_PCIE_EXPCARD# <36>

CARD_CLK_REQ# <36>

+3.3V_RUN

CLK_PCIE_MINI2 <29>
CLK_PCIE_MINI2# <29>

MINI2CLK_REQ# <29>

+3.3V_RUN

DREF_SSCLK <10>
DREF_SSCLK# <10>

CLK_PCIE_EXPCARD
CLK_PCIE_EXPCARD#
MCH_DREFCLK
MCH_DREFCLK#
DREF_SSCLK
DREF_SSCLK#

R169 49.9_0402_1%~D
R174 49.9_0402_1%~D
R159 49.9_0402_1%~D
R163 49.9_0402_1%~D
R147 49.9_0402_1%~D
R155 49.9_0402_1%~D

1 2

R208 49.9_0402_1%~D

1 2

R218 49.9_0402_1%~D

1 2

R221 49.9_0402_1%~D

1 2

R222 49.9_0402_1%~D

1 2

R223 49.9_0402_1%~D

1 2

R224 49.9_0402_1%~D

1 2

R164 49.9_0402_1%~D

1 2

R171 49.9_0402_1%~D

1 2

R185 49.9_0402_1%~D2@

1 2

R187 49.9_0402_1%~D2@

1 2

R225 49.9_0402_1%~D

1 2

R226 49.9_0402_1%~D

1 2

R219 49.9_0402_1%~D

1 2

R220 49.9_0402_1%~D

1 2

R143 49.9_0402_1%~D1@

1 2

R151 49.9_0402_1%~D1@

1 2

R156 49.9_0402_1%~D1@

1 2

R160 49.9_0402_1%~D1@

Swap signals for
smooth routing

DELL CONFIDENTIAL/PROPRIETARY

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

Clock Generator

LA-3001P

673Monday, April 17, 2006

1

of

12
12
12
12
12
12

0.4

5

4

3

2

1

H_A#[3..31]<10>

D D

H_REQ#0<10>
H_REQ#1<10>
H_REQ#2<10>
H_REQ#3<10>
H_REQ#4<10>

H_ADSTB#0<10>

R427

51_0402_5%~D

1 2

1

2

H_ADSTB#1<10>

CLK_CPU_BCLK<6>
CLK_CPU_BCLK#<6>

H_ADS#<10>

H_BNR#<10>

H_BPRI#<10>

H_BR0#<10>

H_DEFER#<10>

H_DRDY#<10>

H_HIT#<10>
H_HITM#<10>

H_LOCK#<10>
H_RESET#<10>

H_RS#0<10>
H_RS#1<10>
H_RS#2<10>

H_TRDY#<10>

ITP_DBRESET#<23,30>

H_DBSY#<10>

H_DPSLP#<22>
H_DPRSTP#<22,42>

H_DPWR#<10>

CPU_PROCHOT#<31>

H_PWRGOOD<22>

H_CPUSLP#<10,22>

H_THERMTRIP#<16>

C C

R419

+1.05V_VCCP

B B

R431

1 2

1K_0402_5%~D@

Stuff R427 for Yonah B0 and
forward.

A A

+1.05V_VCCP

H_THERMDA, H_THERMDC routing together with guard trace,
Trace width / Spacing = 10 / 10 mil

R35
75_0402_5%~D

1 2

CPU_PROCHOT#

1 2

56_0402_5%~D

TEST1

H_THERMDA<16>

2200P_0402_50V7K~D@

H_THERMDC<16>

C164

5

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

H_ADSTB#0
H_ADSTB#1

CLK_CPU_BCLK
CLK_CPU_BCLK#

H_ADS#
H_BNR#
H_BPRI#
H_BR0#
H_DEFER#
H_DRDY#
H_HIT#
H_HITM#
H_IERR#
H_LOCK#
H_RESET#

H_RS#0
H_RS#1
H_RS#2
H_TRDY#

ITP_BPM#0
ITP_BPM#1
ITP_BPM#2
ITP_BPM#3

ITP_DBRESET#

H_DBSY#
H_DPSLP#
H_DPRSTP#
H_DPWR#
ITP_BPM#4
ITP_BPM#5
CPU_PROCHOT#

H_PWRGOOD
H_CPUSLP#
ITP_TCK
ITP_TDI H_A20M#
ITP_TDO
TEST1
TEST2
ITP_TMS
ITP_TRST#

H_THERMDA
H_THERMDC

H_THERMTRIP#

JCPU1A

J4

A3#

L4

A4#

M3

A5#

K5

A6#

M1

A7#

N2

A8#

J1

A9#

N3

A10#

P5

A11#

P2

A12#

L1

A13#

P4

A14#

P1

A15#

R1

A16#

Y2

A17#

U5

A18#

R3

A19#

W6

A20#

U4

A21#

Y5

A22#

U2

A23#

R4

A24#

T5

ADDR GROUP

A25#

T3

A26#

W3

A27#

W5

A28#

Y4

A29#

W2

A30#

Y1

A31#

K3

REQ0#

H2

REQ1#

K2

REQ2#

J3

REQ3#

L5

REQ4#

L2

ADSTB0#

V4

ADSTB1#

A22

BCLK0

A21

H1

E2

G5

F1

H5

F21

G6

E4

D20

H4

B1

F3

F4
G3
G2

AD4
AD3
AD1
AC4

C20

E1

B5

E5

D24
AC2
AC1
D21

D6
D7

AC5
AA6
AB3
C26
D25
AB5
AB6

A24
A25

C7

HOST CLK

BCLK1

ADS#
BNR#
BPRI#
BR0#
DEFER#
DRDY#
HIT#

CONTROL

HITM#
IERR#
LOCK#
RESET#

RS0#
RS1#
RS2#
TRDY#

BPM0#
BPM1#
BPM2#
BPM3#

DBR#
DBSY#
DPSLP#
DPRSTP#
DPWR#
PRDY#
PREQ#
PROCHOT#

PWRGOOD
SLP#
TCK
TDI
TDO
TEST1
TEST2
TMS
TRST#

THERMAL

THERMDA

DIODE

THERMDC
THERMTRIP#

TYCO_1-1674770-2_Yonah~D

+1.05V_VCCP

4

YONAH

MISC

R264

56_0402_5%~D

1 2

DATA GROUP

LEGACY CPU

H_THERMTRIP#

D10#
D11#
D12#
D13#
D14#
D15#
D16#
D17#
D18#
D19#
D20#
D21#
D22#
D23#
D24#
D25#
D26#
D27#
D28#
D29#
D30#
D31#
D32#
D33#
D34#
D35#
D36#
D37#
D38#
D39#
D40#
D41#
D42#
D43#
D44#
D45#
D46#
D47#
D48#
D49#
D50#
D51#
D52#
D53#
D54#
D55#
D56#
D57#
D58#
D59#
D60#
D61#
D62#
D63#

DINV0#
DINV1#
DINV2#
DINV3#

DSTBN0#
DSTBN1#
DSTBN2#
DSTBN3#
DSTBP0#
DSTBP1#
DSTBP2#
DSTBP3#

A20M#

FERR#

IGNNE#

INIT#
LINT0
LINT1

STPCLK#

SMI#

H_NMI <22>

H_D#[0..63] <10>

Notes: Can be nopop on X00 board.

R253

22.6_0402_1%~D

H_RESET#

1 2

@

ITP_TDO

1 2

R258

22.6_0402_1%~D@

No-stuff R253 & R258 for bits issue list: WI52082

CLK_CPU_ITP<6>
CLK_CPU_ITP#<6>

2

D0#
D1#
D2#
D3#
D4#
D5#
D6#
D7#
D8#
D9#

H_D#1

F24

H_D#2

E26

H_D#3

H22

H_D#4

F23

H_D#5

G25

H_D#6

E25

H_D#7

E23

H_D#8

K24

H_D#9

G24

H_D#10

J24

H_D#11

J23

H_D#12

H26

H_D#13

F26

H_D#14

K22

H_D#15

H25

H_D#16

N22

H_D#17

K25

H_D#18

P26

H_D#19

R23

H_D#20

L25

H_D#21

L22

H_D#22

L23

H_D#23

M23

H_D#24

P25

H_D#25

P22

H_D#26

P23

H_D#27

T24

H_D#28

R24

H_D#29

L26

H_D#30

T25

H_D#31

N24

H_D#32

AA23

H_D#33

AB24

H_D#34

V24

H_D#35

V26

H_D#36

W25

H_D#37

U23

H_D#38

U25

H_D#39

U22

H_D#40

AB25

H_D#41

W22

H_D#42

Y23

H_D#43

AA26

H_D#44

Y26

H_D#45

Y22

H_D#46

AC26

H_D#47

AA24

H_D#48

AC22

H_D#49

AC23

H_D#50

AB22

H_D#51

AA21

H_D#52

AB21

H_D#53

AC25

H_D#54

AD20

H_D#55

AE22

H_D#56

AF23

H_D#57

AD24

H_D#58

AE21

H_D#59

AD21

H_D#60

AE25

H_D#61

AF25

H_D#62

AF22

H_D#63

AF26

H_DINV#0

J26

H_DINV#1

M26

H_DINV#2

V23

H_DINV#3

AC20

H_DSTBN#0

H23

H_DSTBN#1

M24

H_DSTBN#2

W24

H_DSTBN#3

AD23

H_DSTBP#0

G22

H_DSTBP#1

N25

H_DSTBP#2

Y25

H_DSTBP#3

AE24

A6

H_FERR#

A5

H_IGNNE#

C4

H_INIT#

B3

H_INTR

C6

H_NMI

B4

H_STPCLK#

D5

H_SMI#

A3

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

H_DINV#0 <10>
H_DINV#1 <10>
H_DINV#2 <10>
H_DINV#3 <10>

H_DSTBN#0 <10>
H_DSTBN#1 <10>
H_DSTBN#2 <10>
H_DSTBN#3 <10>
H_DSTBP#0 <10>
H_DSTBP#1 <10>
H_DSTBP#2 <10>
H_DSTBP#3 <10>

H_A20M# <22>

H_FERR# <22>

H_IGNNE# <22>

H_INIT# <22>

H_INTR <22>

H_STPCLK# <22>

H_SMI# <22>

H_D#0

E22

+1.05V_VCCP

ITP_DBRESET#
ITP_BPM#0
ITP_BPM#1
ITP_BPM#2
ITP_BPM#3
ITP_BPM#4
ITP_BPM#5
ITP_TCK
CLK_CPU_ITP

CLK_CPU_ITP#

ITP_TCK

ITP_TRST#

ITP_TMS
ITP_TDI

+1.05V_VCCP

+3.3V_SUS

+1.05V_VCCP

29

JITP1

28

VTT1

27

GND6

VTT0

26

VTAP

25

DBR#

24

DBA#

23

BPM0#

22

GND5

21

BPM1#

20

GND4

19

BPM2#

18

GND3

17

BPM3#

16

GND2

15

BPM4#

14

GND1

13

BPM5#

12

RESET#

11

FBO

10

GND0

9

BCLKP

8

BCLKN

7

TDO

6

NC2

5

TCK

4

NC1

3

TRST#

2

TMS

1

TDI

GND7

MOLEX_52435-2891_28P~D@

30

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

1

1

C264

C263

2

2

Place near JITP

R246
150_0402_1%~D

1 2

51_0402_5%~D

1 2

51_0402_5%~D

R281 39_0402_5%~D

1 2

R245

54.9_0402_1%~D

1 2

R282

150_0402_5%~D

1 2

680_0402_5%~D

1 2

R261 27.4_0402_1%~D

1 2

ITP_DBRESET#

R257

ITP_TDO

R252

H_RESET#

ITP_TMS

@

ITP_BPM#5

ITP_TDI

This shall place near CPU

R262

ITP_TRST#

ITP_TCK

DELL CONFIDENTIAL/PROPRIETARY

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

Yonah Processor(1/2)

LA-3001P

1

773Monday, April 17, 2006

0.4

of

5

4

3

2

1

Length match within 25 mils

W21

AD26

AB20
AA20
AF20
AE20
AB18
AB17
AA18
AA17
AD18
AD17
AC18
AC17
AF18
AF17

AF7
AE7

B26

K21

J21
M21
N21
T21
R21
V21

G21

AE6
AD6

AF5
AE5
AF4
AE3
AF2
AE2

B22
B23
C21

R26
U26

AF1
D22
C23
C24
AA1
AA4
AB2
AA3

T22
B25

K6

J6
M6
N6

T6
R6

V6

U1

V1

E7

D2

F6
D3
C1

M4
N5

T2

V3

B2
C3

JCPU1B

VCCSENSE
VSSSENSE

VCCA
VCCP

VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP

PSI#
VID0

VID1
VID2
VID3
VID4
VID5
VID6

GTLREF
BSEL0

BSEL1
BSEL2

COMP0
COMP1
COMP2
COMP3

VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC

RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

YONAH

TYCO_1-1674770-2_Yonah~D

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

POWER, GROUNG, RESERVED SIGNALS AND NC

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

AB26
AA25
AD25
AE26
AB23
AC24
AF24
AE23
AA22
AD22
AC21
AF21
AB19
AA19
AD19
AC19
AF19
AE19
AB16
AA16
AD16
AC16
AF16
AE16
AB13
AA14
AD13
AC14
AF13
AE14
AB11
AA11
AD11
AC11
AF11
AE11
AB8
AA8
AD8
AC8
AF8
AE8
AA5
AD5
AC6
AF6
AB4
AC3
AF3
AE4
AB1
AA2
AD2
AE1
B6
C5
F5
E6
H6
J5
M5
L6
P6
R5
V5
U6
Y6
A4
D4
E3
H3
G4
K4
L3
P3
N4
T4
U3
Y3
W4
D1
C2
F2
G1

D D

+VCC_CORE

R293

1 2

100_0402_1%~D

R283

1 2

100_0402_1%~D

VCCSENSE

VSSSENSE

Layout close CPU within 1"

+1.5V_RUN

VCCSENSE<42>
VSSSENSE<42>

0.01U_0402_16V7K~D
C167

10U_0805_4VAM~D

+1.05V_VCCP

C173

1

1

2

2

VCCSENSE
VSSSENSE

Trace width/space=18mils/7mils

space with other is 50mil

H_PSI#<42>

VID0<42>
VID1<42>
VID2<42>
VID3<42>

V_CPU_GTLREF

CPU_MCH_BSEL0<6,10>
CPU_MCH_BSEL1<6,10>
CPU_MCH_BSEL2<6,10>

+VCC_CORE

VID4<42>
VID5<42>
VID6<42>

C C

CPU_BSEL CPU_BSEL2 CPU_BSEL1

133

166

00

01

54.9_0402_1%~D

27.4_0402_1%~D

12

R434

27.4_0402_1%~D

12

R435

12

R327

CPU_BSEL0

1

1

54.9_0402_1%~D

Resistor pl aced within

12

0.5" of CPU pin.Trace

R328

should be at least 25
mils away from any
other toggling signal.

H_PSI#
VID0

VID1
VID2
VID3
VID4
VID5
VID6

CPU_MCH_BSEL0
CPU_MCH_BSEL1
CPU_MCH_BSEL2

COMP0
COMP1
COMP2
COMP3

Layout Note:

COMP0,2 connect with Z0=27.4 ohm, make trace length shorter than 0.5".

B B

A A

COMP1,3 connect with Z0=55.5 ohm, make trace length shorter than 0.5".

V_CPU_GTLREF

+1.05V_VCCP

12

R428
1K_0402_1%~D

12

R429
2K_0402_1%~D

+VCC_CORE

AE18
AE17
AB15
AA15
AD15
AC15
AF15
AE15
AB14
AA13
AD14
AC13
AF14
AE13
AB12
AA12
AD12
AC12
AF12
AE12
AB10

AA10
AD10
AC10
AF10
AE10

JCPU1C

VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC

AB9

VCC
VCC

AA9

VCC
VCC

AD9

VCC
VCC

AC9

VCC
VCC

AF9

VCC
VCC

AE9

VCC

AB7

VCC

AA7

VCC

AD7

VCC

AC7

VCC

B20

VCC

A20

VCC

F20

VCC

E20

VCC

B18

VCC

B17

VCC

A18

VCC

A17

VCC

D18

VCC

D17

VCC

C18

VCC

C17

VCC

F18

VCC

F17

VCC

E18

VCC

E17

VCC

B15

VCC

A15

VCC

D15

VCC

C15

VCC

F15

VCC

E15

VCC

B14

VCC

A13

VCC

D14

VCC

C13

VCC

F14

VCC

E13

VCC

B12

VCC

A12

VCC

D12

VCC

C12

VCC

F12

VCC

E12

VCC

B10

VCC

B9

VCC

A10

VCC

A9

VCC

D10

VCC

D9

VCC

C10

VCC

C9

VCC

F10

VCC

F9

VCC

E10

VCC

E9

VCC

B7

VCC

A7

VCC

F7

VCC

YONAH

POWER, GROUND

TYCO_1-1674770-2_Yonah~D

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

K1
J2
M2
N1
T1
R2
V2
W1
A26
D26
C25
F25
B24
A23
D23
E24
B21
C22
F22
E21
B19
A19
D19
C19
F19
E19
B16
A16
D16
C16
F16
E16
B13
A14
D13
C14
F13
E14
B11
A11
D11
C11
F11
E11
B8
A8
D8
C8
F8
E8
G26
K26
J25
M25
N26
T26
R25
V25
W26
H24
G23
K23
L24
P24
N23
T23
U24
Y24
W23
H21
J22
M22
L21
P21
R22
V22
U21
Y21

Layout close CPU PIN AD26

0.5 inch (max)

5

4

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

2

DELL CONFIDENTIAL/PROPRIETARY

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

Yonah Processor(2/2)

LA-3001P

873Monday, April 17, 2006

1

of

0.4

5

4

3

2

1

Intel CRB schematic suggest to use X5R or better

+VCC_CORE

D D

C C

Place these inside
socket cavity on L8
(North side
Secondary)

Place these inside
socket cavity on L8
(North side
Secondary)

Place these inside
socket cavity on L8
(North side
Secondary)

Place these inside
socket cavity on L8
(North side
Secondary)

1

2

+VCC_CORE

1

2

+VCC_CORE

1

2

+VCC_CORE

1

2

C110
10U_0805_4VAM~D

C81
10U_0805_4VAM~D

C475
10U_0805_4VAM~D

C320
10U_0805_4VAM~D

1

C101
10U_0805_4VAM~D

2

1

C444
10U_0805_4VAM~D

2

1

C394
10U_0805_4VAM~D

2

1

C93
10U_0805_4VAM~D

2

1

C103
10U_0805_4VAM~D

2

1

C476
10U_0805_4VAM~D

2

1

C422
10U_0805_4VAM~D

2

1

C446
10U_0805_4VAM~D

2

1

C92
10U_0805_4VAM~D

2

1

C395
10U_0805_4VAM~D

2

1

C443
10U_0805_4VAM~D

2

1

C329
10U_0805_4VAM~D

2

1

C82
10U_0805_4VAM~D

2

1

C423
10U_0805_4VAM~D

2

1

C333
10U_0805_4VAM~D

2

1

C481
10U_0805_4VAM~D

2

1

C126
10U_0805_4VAM~D

2

1

C375
10U_0805_4VAM~D

2

1

C353
10U_0805_4VAM~D

2

1

C316
10U_0805_4VAM~D

2

1

C117
10U_0805_4VAM~D

2

1

C354
10U_0805_4VAM~D

2

1

C119
10U_0805_4VAM~D

2

1

C334
10U_0805_4VAM~D

2

1

C111
10U_0805_4VAM~D

2

1

C321
10U_0805_4VAM~D

2

1

C127
10U_0805_4VAM~D

2

1

C374
10U_0805_4VAM~D

2

10uF 0805 X6S -> 105 degree C

High Frequence Decoupling

Near VCORE regulator

+VCC_CORE

South Side Secondary

B B

+1.05V_VCCP

1

+

330U_D2E_2.5VM_R9~D@

A A

C432

2

1

C484

0.1U_0402_10V7K~D

2

1

+

C125

C324

2

330U_D_2VM_R6~D

330U_D_2VM_R6~D

6mOhm

6mOhm

PS CAP

PS CAP

1

C485

0.1U_0402_10V7K~D

2

1

1

+

+

C88

2

2

330U_D_2VM_R6~D

6mOhm
PS CAP

1

C130

2

330U_D_2VM_R6~D

6mOhm
PS CAP

1

C486

0.1U_0402_10V7K~D

2

+

C108

330U_D_2VM_R6~D

6mOhm
PS CAP

@

@

1

1

+

C98

2

2

330U_D_2VM_R6~D

6mOhm
PS CAP

1

C312

0.1U_0402_10V7K~D

2

North Side Secondary

+

1

C309

0.1U_0402_10V7K~D

2

ESR <= 1.5m ohm
Capacitor > 1980uF

1

C310

0.1U_0402_10V7K~D

2

Place these inside
socket cavity on L8
(North side
Secondary)

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

CPU Bypass

LA-3001P

973Monday, April 17, 2006

1

0.4

of

5

H_D#[0..63]<7>

D D

C C

+1.05V_VCCP

54.9_0402_1%~D

12

12

R383

R79

54.9_0402_1%~D

B B

Layout Note:
H_XRCOMP & H_YRCOMP / H_SWNG0 &
H_SWNG1 trace width and spacing is 10/20

A A

12

R81

24.9_0402_1%~D

H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63

H_VREF
H_XRCOMP
H_XSCOMP
H_YRCOMP
H_YSCOMP
H_SWNG0
H_SWNG1

12

R395

24.9_0402_1%~D

200_0402_1%~D

5

U9A

F1

HD0#

J1

HD1#

H1

HD2#

J6

HD3#

H3

HD4#

K2

HD5#

G1

HD6#

G2

HD7#

K9

HD8#

K1

HD9#

K7

HD10#

J8

HD11#

H4

HD12#

J3

HD13#

K11

HD14#

G4

HD15#

T10

HD16#

W11

HD17#

T3

HD18#

U7

HD19#

U9

HD20#

U11

HD21#

T11

HD22#

W9

HD23#

T1

HD24#

T8

HD25#

T4

HD26#

W7

HD27#

U5

HD28#

T9

HD29#

W6

HD30#

T5

HD31#

AB7

HD32#

AA9

HD33#

W4

HD34#

W3

HD35#

Y3

HD36#

Y7

HD37#

W5

HD38#

Y10

HD39#

AB8

HD40#

W2

HD41#

AA4

HD42#

AA7

HD43#

AA2

HD44#

AA6

HD45#

AA10

HD46#

Y8

HD47#

AA1

HD48#

AB4

HD49#

AC9

HD50#

AB11

HD51#

AC11

HD52#

AB3

HD53#

AC2

HD54#

AD1

HD55#

AD9

HD56#

AC1

HD57#

AD7

HD58#

AC6

HD59#

AB5

HD60#

AD10

HD61#

AD4

HD62#

AC8

HD63#

J13

HVREF0

K13

HVREF1

E1

HXRCOMP

E2

HXSCOMP

Y1

HYRCOMP

U1

HYSCOMP

E4

HXSWING

W1

HYSWING

CALISTOGA A0 _ FCBGA1466~D

12

R365
100_0402_1%~D

H_VREF H_SWNG0 H_SWNG1

R354

0.1U_0402_16V4Z~D

12

1

2

C326

HOST

100_0402_1%~D

R330

12

R318
221_0402_1%~D

12

HA3#
HA4#
HA5#
HA6#
HA7#
HA8#

HA9#
HA10#
HA11#
HA12#
HA13#
HA14#
HA15#
HA16#
HA17#
HA18#
HA19#
HA20#
HA21#
HA22#
HA23#
HA24#
HA25#
HA26#
HA27#
HA28#
HA29#
HA30#
HA31#

HREQ#0
HREQ#1
HREQ#2
HREQ#3
HREQ#4

HADSTB#0
HADSTB#1

HCLKN
HCLKP

HDSTBN#0
HDSTBN#1
HDSTBN#2
HDSTBN#3
HDSTBP#0
HDSTBP#1
HDSTBP#2
HDSTBP#3

HDINV#0
HDINV#1
HDINV#2
HDINV#3

HCPURST#

HADS#

HTRDY#
HDPWR#
HDRDY#

HDEFER#

HHITM#

HHIT#

HLOCK#

HBREQ0#

HBNR#

HBPRI#

HDBSY#

HCPUSLP#

HRS0#
HRS1#
HRS2#

0.1U_0402_16V4Z~D

1

2

C300

4

UMA use 945GM A2 ( P/N: SA00000592L )
Discrete use 945PM A2 ( P/N: SA00000KD1L)

H_REQ#0 <7>
H_REQ#1 <7>
H_REQ#2 <7>
H_REQ#3 <7>
H_REQ#4 <7>

H_ADSTB#0 <7>
H_ADSTB#1 <7>

CLK_MCH_BCLK# <6>
CLK_MCH_BCLK <6>

H_DSTBN#0 <7>
H_DSTBN#1 <7>
H_DSTBN#2 <7>
H_DSTBN#3 <7>
H_DSTBP#0 <7>
H_DSTBP#1 <7>
H_DSTBP#2 <7>
H_DSTBP#3 <7>

H_DINV#0 <7>
H_DINV#1 <7>
H_DINV#2 <7>
H_DINV#3 <7>

H_RESET# <7>
H_ADS# <7>
H_TRDY# <7>
H_DPWR# <7>
H_DRDY# <7>
H_DEFER# <7>

H_HITM# <7>
H_HIT# <7>

H_LOCK# <7>
H_BR0# <7>
H_BNR# <7>
H_BPRI# <7>
H_DBSY# <7>
H_CPUSLP# <7,22>

H_RS#0 <7>
H_RS#1 <7>
H_RS#2 <7>

C398

H_A#[3..31] <7>

H_A#3

H9

H_A#4

C9

H_A#5

E11

H_A#6

G11

H_A#7

F11

H_A#8

G12

H_A#9

F9

H_A#10

H11

H_A#11

J12

H_A#12

G14

H_A#13

D9

H_A#14

J14

H_A#15

H13

H_A#16

J15

H_A#17

F14

H_A#18

D12

H_A#19

A11

H_A#20

C11

H_A#21

A12

H_A#22

A13

H_A#23

E13

H_A#24

G13

H_A#25

F12

H_A#26

B12

H_A#27

B14

H_A#28

C12

H_A#29

A14

H_A#30

C14

H_A#31

D14

H_REQ#0

D8

H_REQ#1

G8

H_REQ#2

B8

H_REQ#3

F8

H_REQ#4

A8

H_ADSTB#0

B9

H_ADSTB#1

C13

CLK_MCH_BCLK#

AG1

CLK_MCH_BCLK

AG2

H_DSTBN#0

K4

H_DSTBN#1

T7

H_DSTBN#2

Y5

H_DSTBN#3

AC4

H_DSTBP#0

K3

H_DSTBP#1

T6

H_DSTBP#2

AA5

H_DSTBP#3

AC5

H_DINV#0

J7

H_DINV#1

W8

H_DINV#2

U3

H_DINV#3

AB10

H_RESET#

B7

H_ADS#

E8

H_TRDY#

E7

H_DPWR#

J9

H_DRDY#

H8

H_DEFER#

C3

H_HITM#

D4

H_HIT#

D3

H_LOCK#

B3

H_BR0#

C7

H_BNR#

C6

H_BPRI#

F6

H_DBSY#

A7

H_CPUSLP#

E3

H_RS#0

B4

H_RS#1

E6

H_RS#2

D6

+1.05V_VCCP+1.05V_VCCP+1.05V_VCCP

12

R397
221_0402_1%~D

R396

0.1U_0402_16V4Z~D

12

1

2

100_0402_1%~D

4

3

M_ODT0<17>
M_ODT1<17>
M_ODT2<18>
M_ODT3<18>

V_DDR_MCH_REF

R296

0_0402_5%~D

0.1U_0402_16V4Z~D
C509

1

2

DMI_MRX_ITX_N0
DMI_MRX_ITX_N1
DMI_MRX_ITX_N2
DMI_MRX_ITX_N3

DMI_MRX_ITX_P0
DMI_MRX_ITX_P1
DMI_MRX_ITX_P2
DMI_MRX_ITX_P3

DMI_MTX_IRX_N0
DMI_MTX_IRX_N1
DMI_MTX_IRX_N2
DMI_MTX_IRX_N3

DMI_MTX_IRX_P0
DMI_MTX_IRX_P1
DMI_MTX_IRX_P2
DMI_MTX_IRX_P3

M_CLK_DDR0
M_CLK_DDR1
M_CLK_DDR2
M_CLK_DDR3

M_CLK_DDR#0
M_CLK_DDR#1
M_CLK_DDR#2
M_CLK_DDR#3

DDR_CKE0_DIMMA
DDR_CKE1_DIMMA
DDR_CKE2_DIMMB
DDR_CKE3_DIMMB

DDR_CS0_DIMMA#
DDR_CS1_DIMMA#
DDR_CS2_DIMMB#
DDR_CS3_DIMMB#

M_OCDOCMP0
M_OCDOCMP1

M_ODT0
M_ODT1
M_ODT2
M_ODT3

SMRCOMPN
SMRCOMPP

PM_BMBUSY#
PM_EXTTS#0
PM_EXTTS#1_R
THERMTRIP_MCH#
ICH_PWRGD
PLTRST_MCH_R#

MCH_ICH_SYNC#

PM_EXTTS#1_R

0.1U_0402_16V4Z~D

DMI_MRX_ITX_N0<23>
DMI_MRX_ITX_N1<23>
DMI_MRX_ITX_N2<23>
DMI_MRX_ITX_N3<23>

DMI_MRX_ITX_P0<23>
DMI_MRX_ITX_P1<23>
DMI_MRX_ITX_P2<23>
DMI_MRX_ITX_P3<23>

DMI_MTX_IRX_N0<23>
DMI_MTX_IRX_N1<23>
DMI_MTX_IRX_N2<23>
DMI_MTX_IRX_N3<23>

DMI_MTX_IRX_P0<23>
DMI_MTX_IRX_P1<23>
DMI_MTX_IRX_P2<23>
DMI_MTX_IRX_P3<23>

M_CLK_DDR0<17>
M_CLK_DDR1<17>
M_CLK_DDR2<18>
M_CLK_DDR3<18>

M_CLK_DDR#0<17>
M_CLK_DDR#1<17>
M_CLK_DDR#2<18>
M_CLK_DDR#3<18>

DDR_CKE0_DIMMA<17>
DDR_CKE1_DIMMA<17>
DDR_CKE2_DIMMB<18>
DDR_CKE3_DIMMB<18>

DDR_CS0_DIMMA#<17>
DDR_CS1_DIMMA#<17>
DDR_CS2_DIMMB#<18>
DDR_CS3_DIMMB#<18>

+1.8V_SUS

R436 80.6_0402_1%~D

1 2
1 2

R432 80.6_0402_1%~D

PM_BMBUSY#<23>

PM_EXTTS#0<17>

THERMTRIP_MCH#<16>

ICH_PWRGD<23,33>

PLTRST_MCH#<21>

DPRSLPVR<23,42>

V_DDR_MCH_REF<17,18,41>

R425 100_0402_1%~D

DPRSLPVR

12

MCH_ICH_SYNC#<21>

AE35
AF39
AG35
AH39

AC35
AE39
AF35
AG39

AE37
AF41
AG37
AH41

AC37
AE41
AF37
AG41

AY35

AR1

AW7

AW40
AW35

AT1
AY7

AY40
AU20

AT20
BA29
AY29

AW13
AW12

AY21

AW21

AL20

AF10
BA13

BA12
AY20
AU21

AV9
AT9

AK1

AK41

G28

F25

H26

G6
AH33
AH34

K28

C704

1

2

2

U9B

DMIRXN0
DMIRXN1
DMIRXN2
DMIRXN3

DMIRXP0
DMIRXP1

DMI

DMIRXP2
DMIRXP3

DMITXN0
DMITXN1
DMITXN2
DMITXN3

DMITXP0
DMITXP1
DMITXP2
DMITXP3

SM_CK0
SM_CK1
SM_CK2
SM_CK3

SM_CK0#
SM_CK1#
SM_CK2#
SM_CK3#

SM_CKE0
SM_CKE1
SM_CKE2
SM_CKE3

SM_CS0#
SM_CS1#
SM_CS2#
SM_CS3#

SM_OCDCOMP0
SM_OCDCOMP1

SM_ODT0
SM_ODT1
SM_ODT2
SM_ODT3

SM_RCOMPN
SM_RCOMPP

SM_VREF0
SM_VREF1

PM_BMBUSY#
PM_EXTTS0#
PM_EXTTS1#
PM_THERMTRIP#
PWROK
RSTIN#

ICH_SYNC#

CALISTOGA A0 _ FCBGA1466~D

Place closed to U9 pinAK1,pinAK41

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

2

1

Description at page12
Note :

CFG3:17 has
internal pullup,
CFG18:19 has
internal pulldown

CPU_MCH_BSEL0

K16

CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8

CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG16
CFG17

CFG

CFG18
CFG19
CFG20

G_CLKP
G_CLKN

D_REF_CLKN

D_REF_CLKP

CLKNC

D_REF_SSCLKN
D_REF_SSCLKP

DDR MUXING

PM

CLK_REQ#

RESERVED1
RESERVED2
RESERVED3
RESERVED4
RESERVED5
RESERVED6
RESERVED7
RESERVED8

RESERVED9
RESERVED10
RESERVED11
RESERVED12
RESERVED13

RESERVED

NC10
NC11
NC12
NC13
NC14
NC15
NC16
NC17
NC18

NC0
NC1
NC2
NC3
NC4
NC5
NC6
NC7
NC8
NC9

CPU_MCH_BSEL1

K18

CPU_MCH_BSEL2

J18

CFG3

F18

CFG4

E15

CFG5

F15

CFG6

E18

CFG7

D19

CFG8

D16

CFG9

G16

CFG10

E16

CFG11

D15

CFG12

G15

CFG13

K15

CFG14

C15

CFG15

H16

CFG16

G18

CFG17

H15

CFG18

J25

CFG19

K27

CFG20

J26

CLK_MCH_3GPLL

AG33

CLK_MCH_3GPLL#

AF33

MCH_DREFCLK#

A27

MCH_DREFCLK

A26

DREF_SSCLK#

C40

DREF_SSCLK

D41

CLK_3GPLLREQ#

H32

A3
A39
A4
A40

MCH_DREFCLK

AW1
AW41

DREF_SSCLK

AY1
BA1

MCH_DREFCLK#

BA2
BA3

DREF_SSCLK#

BA39
BA40
BA41
C1
AY41
B2

For Discrete Only

B41
C41
D1

T32
R32
F3
F7
AG11
AF11
H7
J19
A41
A34
D28
D27
A35

PM_EXTTS#0V_DDR_MCH_REF

PM_EXTTS#1_R

THERMTRIP_MCH#

CPU_MCH_BSEL0 <6,8>
CPU_MCH_BSEL1 <6,8>
CPU_MCH_BSEL2 <6,8>

CFG5 <12>
CFG6 <12>
CFG7 <12>

CFG9 <12>
CFG10 <12>
CFG11 <12>
CFG12 <12>
CFG13 <12>

CFG16 <12>
CFG18 <12>

CFG19 <12>
CFG20 <12>

CLK_MCH_3GPLL <6>

CLK_MCH_3GPLL# <6>

MCH_DREFCLK# <6>
MCH_DREFCLK <6>

DREF_SSCLK# <6>
DREF_SSCLK <6>

CLK_3GPLLREQ# <6>

1 2

R49 0_0402_5%~D2@

1 2

R337 0_0402_5%~D2@

1 2

R50 0_0402_5%~D2@

1 2

R326 0_0402_5%~D2@

+3.3V_RUN

R300

12

10K_0402_5%~D

R297

@

12

10K_0402_5%~D

R313

1 2

75_0402_5%~D

+1.5V_RUN

+1.05V_VCCP

DELL CONFIDENTIAL/PROPRIETARY

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

Calistoga(1 of 6)

LA-3001P

10 73Monday, April 17, 2006

1

0.4

of

5

D D

4

3

2

1

DDR_A_BS0<17>
DDR_A_BS1<17>
DDR_A_BS2<17>

DDR_A_DM[0..7]<17>

DDR_A_DQS[0..7]<17>

C C

DDR_A_DQS#[0..7]<17>

DDR_A_MA[0..13]<17>

B B

DDR_A_CAS#<17>
DDR_A_RAS#<17>

T4 PAD~D T5 PAD~D

DDR_A_WE#<17>

DDR_A_BS0
DDR_A_BS1
DDR_A_BS2

DDR_A_DM0
DDR_A_DM1
DDR_A_DM2
DDR_A_DM3
DDR_A_DM4
DDR_A_DM5
DDR_A_DM6
DDR_A_DM7

DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7

DDR_A_DQS#0
DDR_A_DQS#1
DDR_A_DQS#2
DDR_A_DQS#3
DDR_A_DQS#4
DDR_A_DQS#5
DDR_A_DQS#6
DDR_A_DQS#7

DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13

DDR_A_CAS#
DDR_A_RAS#
DDR_A_WE#
SA_RCVENIN#
SA_RCVENOUT#

Add a test point Add a test point

U9D

AU12

SA_BS0

AV14

SA_BS1

BA20

SA_BS2

AJ33

SA_DM0

AM35

SA_DM1

AL26

SA_DM2

AN22

SA_DM3

AM14

SA_DM4

AL9

SA_DM5

AR3

SA_DM6

AH4

SA_DM7

AK33

SA_DQS0

AT33

SA_DQS1

AN28

SA_DQS2

AM22

SA_DQS3

AN12

SA_DQS4

AN8

SA_DQS5

AP3

SA_DQS6

AG5

SA_DQS7

AK32

SA_DQS0#

AU33

SA_DQS1#

AN27

SA_DQS2#

AM21

SA_DQS3#

AM12

SA_DQS4#

AL8

SA_DQS5#

AN3

SA_DQS6#

AH5

SA_DQS7#

AY16

SA_MA0

AU14

SA_MA1

AW16

SA_MA2

BA16

SA_MA3

BA17

SA_MA4

AU16

SA_MA5

AV17

SA_MA6

AU17

SA_MA7

AW17

SA_MA8

AT16

SA_MA9

AU13

SA_MA10

AT17

SA_MA11

AV20

SA_MA12

AV12

SA_MA13

AY13

SA_CAS#

AW14

SA_RAS#

AY14

SA_WE#

AK23

SA_RCVENIN#

AK24

SA_RCVENOUT#

CALISTOGA A0 _ FCBGA1466~D

SA_DQ0
SA_DQ1
SA_DQ2
SA_DQ3
SA_DQ4
SA_DQ5
SA_DQ6
SA_DQ7
SA_DQ8

SA_DQ9
SA_DQ10
SA_DQ11
SA_DQ12
SA_DQ13
SA_DQ14
SA_DQ15
SA_DQ16
SA_DQ17
SA_DQ18
SA_DQ19
SA_DQ20
SA_DQ21
SA_DQ22
SA_DQ23
SA_DQ24
SA_DQ25
SA_DQ26
SA_DQ27
SA_DQ28
SA_DQ29
SA_DQ30
SA_DQ31
SA_DQ32
SA_DQ33
SA_DQ34
SA_DQ35
SA_DQ36
SA_DQ37
SA_DQ38
SA_DQ39

DDR SYS MEMORY A

SA_DQ40
SA_DQ41
SA_DQ42
SA_DQ43
SA_DQ44
SA_DQ45
SA_DQ46
SA_DQ47
SA_DQ48
SA_DQ49
SA_DQ50
SA_DQ51
SA_DQ52
SA_DQ53
SA_DQ54
SA_DQ55
SA_DQ56
SA_DQ57
SA_DQ58
SA_DQ59
SA_DQ60
SA_DQ61
SA_DQ62
SA_DQ63

AJ35
AJ34
AM31
AM33
AJ36
AK35
AJ32
AH31
AN35
AP33
AR31
AP31
AN38
AM36
AM34
AN33
AK26
AL27
AM26
AN24
AK28
AL28
AM24
AP26
AP23
AL22
AP21
AN20
AL23
AP24
AP20
AT21
AR12
AR14
AP13
AP12
AT13
AT12
AL14
AL12
AK9
AN7
AK8
AK7
AP9
AN9
AT5
AL5
AY2
AW2
AP1
AN2
AV2
AT3
AN1
AL2
AG7
AF9
AG4
AF6
AG9
AH6
AF4
AF8

DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63

DDR_B_BS0<18>
DDR_B_BS1<18>
DDR_B_BS2<18>

DDR_B_DM[0..7]<18>

DDR_B_DQS[0..7]<18>

DDR_B_DQS#[0..7]<18>

DDR_B_MA[0..13]<18>

DDR_B_CAS#<18>
DDR_B_RAS#<18>

T3 PAD~DT2 PAD~D

DDR_B_WE#<18>

DDR_B_BS0
DDR_B_BS1
DDR_B_BS2

DDR_B_DM0
DDR_B_DM1
DDR_B_DM2
DDR_B_DM3
DDR_B_DM4
DDR_B_DM5
DDR_B_DM6
DDR_B_DM7

DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4
DDR_B_DQS5
DDR_B_DQS6
DDR_B_DQS7

DDR_B_DQS#0
DDR_B_DQS#1
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS#4
DDR_B_DQS#5
DDR_B_DQS#6
DDR_B_DQS#7

DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13

DDR_B_CAS#
DDR_B_RAS#
DDR_B_WE#
SB_RCVENIN#
SB_RCVENOUT#

U9E

AT24

SB_BS0

AV23

SB_BS1

AY28

SB_BS2

AK36

SB_DM0

AR38

SB_DM1

AT36

SB_DM2

BA31

SB_DM3

AL17

SB_DM4

AH8

SB_DM5

BA5

SB_DM6

AN4

SB_DM7

AM39

SB_DQS0

AT39

SB_DQS1

AU35

SB_DQS2

AR29

SB_DQS3

AR16

SB_DQS4

AR10

SB_DQS5

AR7

SB_DQS6

AN5

SB_DQS7

AM40

SB_DQS0#

AU39

SB_DQS1#

AT35

SB_DQS2#

AP29

SB_DQS3#

AP16

SB_DQS4#

AT10

SB_DQS5#

AT7

SB_DQS6#

AP5

SB_DQS7#

AY23

SB_MA0

AW24

SB_MA1

AY24

SB_MA2

AR28

SB_MA3

AT27

SB_MA4

AT28

SB_MA5

AU27

SB_MA6

AV28

SB_MA7

AV27

SB_MA8

AW27

SB_MA9

AV24

SB_MA10

BA27

SB_MA11

AY27

SB_MA12

AR23

SB_MA13

AR24

SB_CAS#

AU23

SB_RAS#

AR27

SB_WE#

AK16

SB_RCVENIN#

AK18

SB_RCVENOUT#

CALISTOGA A0 _ FCBGA1466~D

AK39

SB_DQ0

AJ37

SB_DQ1

AP39

SB_DQ2

AR41

SB_DQ3

AJ38

SB_DQ4

AK38

SB_DQ5

AN41

SB_DQ6

AP41

SB_DQ7

AT40

SB_DQ8

AV41

SB_DQ9

AU38

SB_DQ10

AV38

SB_DQ11

AP38

SB_DQ12

AR40

SB_DQ13

AW38

SB_DQ14

AY38

SB_DQ15

BA38

SB_DQ16

AV36

SB_DQ17

AR36

SB_DQ18

AP36

SB_DQ19

BA36

SB_DQ20

AU36

SB_DQ21

AP35

SB_DQ22

AP34

SB_DQ23

AY33

SB_DQ24

BA33

SB_DQ25

AT31

SB_DQ26

AU29

SB_DQ27

AU31

SB_DQ28

AW31

SB_DQ29

AV29

SB_DQ30

AW29

SB_DQ31

AM19

SB_DQ32

AL19

SB_DQ33

AP14

SB_DQ34

AN14

SB_DQ35

AN17

SB_DQ36

AM16

SB_DQ37

AP15

SB_DQ38

AL15

SB_DQ39
SB_DQ40
SB_DQ41
SB_DQ42
SB_DQ43
SB_DQ44
SB_DQ45
SB_DQ46
SB_DQ47
SB_DQ48
SB_DQ49
SB_DQ50
SB_DQ51
SB_DQ52
SB_DQ53
SB_DQ54
SB_DQ55
SB_DQ56
SB_DQ57
SB_DQ58
SB_DQ59
SB_DQ60
SB_DQ61
SB_DQ62
SB_DQ63

AJ11
AH10
AJ9
AN10
AK13
AH11
AK10
AJ8
BA10
AW10
BA4
AW4
AY10
AY9
AW5
AY5
AV4
AR5
AK4
AK3
AT4
AK5
AJ5
AJ3

DDR SYS MEMORY B

DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63

DDR_B_D[0..63] <18>DDR_A_D[0..63] <17>

A A

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

Calistogo(2 of 6)

LA-3001P

11 73Monday, April 17, 2006

1

0.4

of

5

4

3

2

1

Strap Pin Table

R274 2.2K_0402_5%~D@

1 2

R309 2.2K_0402_5%~D

R329 2.2K_0402_5%~D@

R311 2.2K_0402_5%~D@

R276 2.2K_0402_5%~D

R310 2.2K_0402_5%~D@

R277 2.2K_0402_5%~D@

R312 2.2K_0402_5%~D@

R275 2.2K_0402_5%~D@

@

1 2

1 2

@

1 2

1 2

1 2

1 2

CFG[3:17] have internal pullup

R57 1K_0402_5%~D@

1 2

R55 1K_0402_5%~D@

1 2

R56 1K_0402_5%~D@

1 2

CFG[18:19] have internal pulldown

Resistors Stuff Table

D

CLK_DDC2

13

Q18

BSS138_SOT23~D1@

DAT_DDC2G_DAT_DDC2

13

D

BSS138_SOT23~D1@

CLK_DDC2 <20>

DAT_DDC2 <20>

Calistoga(3 of 6)

12 73Monday, April 17, 2006

1

+3.3V_RUN

0.4

of

UMA

R298

2.2K_0402_5%~D1@

LA-3001P

CFG5<10>

CFG6<10>

CFG7<10>

CFG9<10>

CFG10<10>

CFG11<10>

CFG12<10>

CFG13<10>

CFG16<10>

CFG18<10>

CFG19<10>

CFG20<10>

R290,R305,R307,R308,R360
,R366,R301,R302,R303,R294
,R295,R292,R306,R304,R38
,R39,298,R299,

R271,R272,R273,R270,R53,
R358,R345,R266,R267,R268,
R371,R269

S

G

2

G

2

Q19

S

Compal Electronics, Inc.

CFG5

SDVO_CTRLDATA have internal pull down

D D

LCD_A0+_NB<19>
LCD_A1+_NB<19>
LCD_A2+_NB<19>

LCD_A0-_NB<19>
LCD_A1-_NB<19>
LCD_A2-_NB<19>

LCD_ACLK+_NB<19>
LCD_ACLK-_NB<19>

BIA_PWM<19>

PANEL_BKEN<19>

ENVDD<19>

C C

LVREF for Alviso N.C
for Calistoga to GND

TV_CVBS_NB<20>

TV_Y_NB<20>
TV_C_NB<20>

R305

12

150_0402_1%~D1@

R290 1.5K_0402_1%~D1@

R307

R308

12

12

4.99K_0402_1%~D1@

150_0402_1%~D1@

150_0402_1%~D1@

12

Close to U9.J20

VGA_VSYNC<20>
VGA_HSYNC<20>

VGA_BLU<20>
VGA_GRN<20>
VGA_RED<20>

B B

Close to U9.J22

12

VGA_RED
VGA_GRN
VGA_BLU

LCTLA_CLK
LCTLB_DATA

LVREF

1 2

R303 150_0402_1%~D1@

1 2

R302 150_0402_1%~D1@

1 2

R301 150_0402_1%~D1@

+3.3V_RUN

1 2

R294 10K_0402_5%~D1@

1 2

R295 10K_0402_5%~D1@

A A

R292 0_0402_5%~D1@

NOTE:
1@ is for UMA Implemetation.
2@ is for Discrete Implementation.

R366

255_0402_1%~D1@

Trace CRT_IREF should be at
least 25 mils away from any
other toggling signal.

+1.5V_RUN

+1.5V_RUN

5

12

R360

12

R271 0_0402_5%~D2@

R306 0_0402_5%~D1@

R272 0_0402_5%~D2@
R273 0_0402_5%~D2@
R270 0_0402_5%~D2@
R53 0_0402_5%~D2@
R358 0_0402_5%~D2@
R345 0_0402_5%~D2@

LCD_A0+_NB
LCD_A1+_NB
LCD_A2+_NB

LCD_A0-_NB
LCD_A1-_NB
LCD_A2-_NB

LCD_ACLK+_NB
LCD_ACLK-_NB

BIA_PWM
PANEL_BKEN
LCTLA_CLK
LCTLB_DATA
LDDC_CLK
LDDC_DATA
ENVDD
L_IBG

LVREF

TV_CVBS_NB
TV_Y_NB
TV_C_NB

TVIREF
TV_IRTN

G_CLK_DDC2
G_DAT_DDC2

VGA_VSYNC
VGA_HSYNC
VGA_BLU
CRT_RGB#
VGA_GRN

VGA_RED

CRT_IREF

12
12

12
12
12
12
12
12

TV_IRTN

TV_CVBS_NB
TV_Y_NB
TV_C_NB
TVIREF
VGA_VSYNC
VGA_HSYNC

U9C

H27

SDVOCTRL_DATA

H28

SDVOCTRL_CLK

B37

LA_DATA0

B34

LA_DATA1

A36

LA_DATA2

C37

LA_DATA#0

B35

LA_DATA#1

A37

LA_DATA#2

F30

LB_DATA0

D29

LB_DATA1

F28

LB_DATA2

G30

LB_DATA#0

D30

LB_DATA#1

F29

LB_DATA#2

A32

LA_CLK

A33

LA_CLK#

E26

LB_CLK

E27

LB_CLK#

D32

LBKLT_CTL

J30

LBKLT_EN

H30

LCTLA_CLK

H29

LCTLB_DATA

G26

LDDC_CLK

G25

LDDC_DATA

F32

LVDD_EN

B38

LIBG

C35

LVBG

C33

LVREFH

C32

LVREFL

A16

TVDAC_A

C18

TVDAC_B

A19

TVDAC_C

J20

TV_IREF

B16

TV_IRTNA

B18

TV_IRTNB

B19

TV_IRTNC

J29

TV_DCONSEL1

K30

TV_DCONSEL0

C26

DDCCLK

C25

DDCDATA

H23

VSYNC

G23

HSYNC

E23

BLUE

D23

BLUE#

C22

GREEN

B22

GREEN#

A21

RED

B21

RED#

J22

CRT_IREF

CALISTOGA A0 _ FCBGA1466~D

+1.05V_VCCP

R266 0_0402_5%~D2@
R267 0_0402_5%~D2@
R268 0_0402_5%~D2@
R371 0_0402_5%~D2@
R269 0_0402_5%~D2@

R304 0_0402_5%~D1@

PEGCOMP

D40

EXP_COMPI

EXP_RXN0
EXP_RXN1
EXP_RXN2
EXP_RXN3
EXP_RXN4
EXP_RXN5
EXP_RXN6
EXP_RXN7
EXP_RXN8

EXP_RXN9
EXP_RXN10
EXP_RXN11
EXP_RXN12
EXP_RXN13
EXP_RXN14
EXP_RXN15

EXP_RXP0
EXP_RXP1
EXP_RXP2
EXP_RXP3
EXP_RXP4
EXP_RXP5
EXP_RXP6
EXP_RXP7
EXP_RXP8

EXP_RXP9
EXP_RXP10
EXP_RXP11
EXP_RXP12
EXP_RXP13
EXP_RXP14
EXP_RXP15

EXP_TXN0

EXP_TXN1

EXP_TXN2

EXP_TXN3

EXP_TXN4

EXP_TXN5

EXP_TXN6

EXP_TXN7

EXP_TXN8

EXP_TXN9
EXP_TXN10
EXP_TXN11
EXP_TXN12
EXP_TXN13
EXP_TXN14
EXP_TXN15

EXP_TXP0

EXP_TXP1

EXP_TXP2

EXP_TXP3

EXP_TXP4

EXP_TXP5

EXP_TXP6

EXP_TXP7

EXP_TXP8

EXP_TXP9
EXP_TXP10
EXP_TXP11
EXP_TXP12
EXP_TXP13
EXP_TXP14
EXP_TXP15

2.2K_0402_5%~D1@

R39

D38

PEG_MRX_GTX_N0

F34

PEG_MRX_GTX_N1

G38

PEG_MRX_GTX_N2

H34

PEG_MRX_GTX_N3

J38

PEG_MRX_GTX_N4

L34

PEG_MRX_GTX_N5

M38

PEG_MRX_GTX_N6

N34

PEG_MRX_GTX_N7

P38

PEG_MRX_GTX_N8

R34

PEG_MRX_GTX_N9

T38

PEG_MRX_GTX_N10

V34

PEG_MRX_GTX_N11

W38

PEG_MRX_GTX_N12

Y34

PEG_MRX_GTX_N13

AA38

PEG_MRX_GTX_N14

AB34

PEG_MRX_GTX_N15

AC38

PEG_MRX_GTX_P0

D34

PEG_MRX_GTX_P1

F38

PEG_MRX_GTX_P2

G34

PEG_MRX_GTX_P3

H38

PEG_MRX_GTX_P4

J34

PEG_MRX_GTX_P5

L38

PEG_MRX_GTX_P6

M34

PEG_MRX_GTX_P7

N38

PEG_MRX_GTX_P8

P34

PEG_MRX_GTX_P9

R38

PEG_MRX_GTX_P10

T34

PEG_MRX_GTX_P11

V38

PEG_MRX_GTX_P12

W34

PEG_MRX_GTX_P13

Y38

PEG_MRX_GTX_P14

AA34

PEG_MRX_GTX_P15

AB38

PEG_MTX_GRX_C_N0

F36

PEG_MTX_GRX_C_N1

G40

PEG_MTX_GRX_C_N2

H36

PEG_MTX_GRX_C_N3

J40

PEG_MTX_GRX_C_N4

L36

PEG_MTX_GRX_C_N5

M40

PEG_MTX_GRX_C_N6

N36

PEG_MTX_GRX_C_N7

P40

PEG_MTX_GRX_C_N8

R36

PEG_MTX_GRX_C_N9

T40

PEG_MTX_GRX_C_N10

V36

PEG_MTX_GRX_C_N11

W40

PEG_MTX_GRX_C_N12

Y36

PEG_MTX_GRX_C_N13

AA40

PEG_MTX_GRX_C_N14

AB36

PEG_MTX_GRX_C_N15

AC40

PEG_MTX_GRX_C_P0

D36

PEG_MTX_GRX_C_P1

F40

PEG_MTX_GRX_C_P2

G36

PEG_MTX_GRX_C_P3

H40

PEG_MTX_GRX_C_P4

J36

PEG_MTX_GRX_C_P5

L40

PEG_MTX_GRX_C_P6

M36

PEG_MTX_GRX_C_P7

N40

PEG_MTX_GRX_C_P8

P36

PEG_MTX_GRX_C_P9

R40

PEG_MTX_GRX_C_P10

T36

PEG_MTX_GRX_C_P11

V40

PEG_MTX_GRX_C_P12

W36

PEG_MTX_GRX_C_P13

Y40

PEG_MTX_GRX_C_P14

AA36

PEG_MTX_GRX_C_P15

AB40

PEG_MRX_GTX_P[0:15] <44>
PEG_MRX_GTX_N[0:15] <44>

PEG_MTX_GRX_P[0:15] <44>
PEG_MTX_GRX_N[0:15] <44>

2.2K_0402_5%~D1@

12

LDDC_CLK <19>

LDDC_DATA <19>

EXP_COMPO

LVDS

TV CRT

PCI-EXPRESS GRAPHICS

PEG_MRX_GTX_P[0:15]
PEG_MRX_GTX_N[0:15]

PEG_MTX_GRX_P[0:15]
PEG_MTX_GRX_N[0:15]

+3.3V_RUN

12

R38

4

12
12
12
12

12
12

VGA_BLU
VGA_GRN
VGA_RED
CRT_IREF

CRT_RGB#

R353

24.9_0402_1%~D

1 2

+1.5V_RUN_PCIE

Stuff AC Caps For Discrete

PEG_MTX_GRX_C_N0
PEG_MTX_GRX_C_P1

PEG_MTX_GRX_C_N1
PEG_MTX_GRX_C_P2

PEG_MTX_GRX_C_N2
PEG_MTX_GRX_C_P3

PEG_MTX_GRX_C_N3
PEG_MTX_GRX_C_P4

PEG_MTX_GRX_C_N4
PEG_MTX_GRX_C_P5

PEG_MTX_GRX_C_N5
PEG_MTX_GRX_C_P6

PEG_MTX_GRX_C_N6
PEG_MTX_GRX_C_P7

PEG_MTX_GRX_C_N7
PEG_MTX_GRX_C_P8

PEG_MTX_GRX_C_N8
PEG_MTX_GRX_C_P9

PEG_MTX_GRX_C_N9
PEG_MTX_GRX_C_P10

PEG_MTX_GRX_C_N10
PEG_MTX_GRX_C_P11

PEG_MTX_GRX_C_N11
PEG_MTX_GRX_C_P12

PEG_MTX_GRX_C_N12
PEG_MTX_GRX_C_P13

PEG_MTX_GRX_C_N13
PEG_MTX_GRX_C_P14

PEG_MTX_GRX_C_N14
PEG_MTX_GRX_C_P15

PEG_MTX_GRX_C_N15

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

CFG6

CFG7

CFG9

CFG10

CFG11

CFG[13:12]

CFG16

(FSB Dynamic ODT)

CFG18

(VCC Select)

CFG19

(DMI Lane Reversal)

SDVO_CTRLDATA

CFG20

(PCIE/SDVO s e l ect)

C58 0.1U_0402_16V4Z~D 2@

1 2

C61 0.1U_0402_16V4Z~D 2@

C63 0.1U_0402_16V4Z~D 2@

1 2

C68 0.1U_0402_16V4Z~D 2@

1 2

C74 0.1U_0402_16V4Z~D 2@

1 2

C80 0.1U_0402_16V4Z~D 2@

1 2

C87 0.1U_0402_16V4Z~D 2@

1 2

C91 0.1U_0402_16V4Z~D 2@

1 2

C96 0.1U_0402_16V4Z~D 2@

1 2

C106 0.1U_0402_16V4Z~D 2@

1 2

C109 0.1U_0402_16V4Z~D 2@

1 2

C112 0.1U_0402_16V4Z~D 2@

1 2

C120 0.1U_0402_16V4Z~D 2@

1 2

C123 0.1U_0402_16V4Z~D 2@

1 2

C134 0.1U_0402_16V4Z~D 2@

1 2

C136 0.1U_0402_16V4Z~D 2@

1 2

C142 0.1U_0402_16V4Z~D 2@

1 2

1 2

C65 0.1U_0402_16V4Z~D 2@

1 2

C71 0.1U_0402_16V4Z~D 2@

1 2

C79 0.1U_0402_16V4Z~D 2@

1 2

C84 0.1U_0402_16V4Z~D 2@

1 2

C90 0.1U_0402_16V4Z~D 2@

1 2

C94 0.1U_0402_16V4Z~D 2@

1 2

C105 0.1U_0402_16V4Z~D 2@

1 2

C107 0.1U_0402_16V4Z~D 2@

1 2

C113 0.1U_0402_16V4Z~D 2@

1 2

C116 0.1U_0402_16V4Z~D 2@

1 2

C124 0.1U_0402_16V4Z~D 2@

1 2

C129 0.1U_0402_16V4Z~D 2@

1 2

C137 0.1U_0402_16V4Z~D 2@

1 2

C140 0.1U_0402_16V4Z~D 2@

1 2

C147 0.1U_0402_16V4Z~D 2@

1 2

Low = DMI x 2
High = DMI x 4

*

Low = Moby Dick
High = Calistoga

*

Low = DT/Transportable CPU
High = Mobile CPU

*

Low = Reverse Lane
High = Normal Operation

*

Low = Reserved
High = Mobility

Low = Calistoga
High = Reserved

00 = Reserved
01 = XOR Mode Enabled
10 = All Z Mode Enabled

11 = Normal Operation

*

*

(Default)

Low = Disabled
High = Enabled

Low = 1.05V (Default)
High = 1.5V

Low = Normal
Operation (De f ault):
Lane number in Order

*

*

*

High = Reverse Lane
Low = No SDVO Devi c e Present

(Default)

High = SDVO Dev i c e Present
Low = Only PCIE or SDVO is

operational.
High = PCIE/SDVO are

operating simu.

PEG_MTX_GRX_P0PEG_MTX_GRX_C_P0
PEG_MTX_GRX_N0

PEG_MTX_GRX_P1
PEG_MTX_GRX_N1

PEG_MTX_GRX_P2
PEG_MTX_GRX_N2

PEG_MTX_GRX_P3
PEG_MTX_GRX_N3

PEG_MTX_GRX_P4
PEG_MTX_GRX_N4

PEG_MTX_GRX_P5
PEG_MTX_GRX_N5

PEG_MTX_GRX_P6
PEG_MTX_GRX_N6

PEG_MTX_GRX_P7
PEG_MTX_GRX_N7

PEG_MTX_GRX_P8
PEG_MTX_GRX_N8

PEG_MTX_GRX_P9
PEG_MTX_GRX_N9

PEG_MTX_GRX_P10
PEG_MTX_GRX_N10

PEG_MTX_GRX_P11
PEG_MTX_GRX_N11

PEG_MTX_GRX_P12
PEG_MTX_GRX_N12

PEG_MTX_GRX_P13
PEG_MTX_GRX_N13

PEG_MTX_GRX_P14
PEG_MTX_GRX_N14

PEG_MTX_GRX_P15
PEG_MTX_GRX_N15

(Default)

2

*

*

*

2.2K_0402_5%~D1@

G_CLK_DDC2

Discrete

+3.3V_RUN

12

12

R299

+3.3V_RUN

DELL CONFIDENTIAL/PROPRIETARY

Title

Size Document Number Rev

Date: Sheet

5

AC14
AB14

W14

V14
T14
R14
P14
N14

M14

L14
AD13
AC13
AB13
AA13

Y13

W13

V13

U13

T13

R13
N13
M13

L13
AB12
AA12

Y12

W12

V12

U12

T12

R12

P12

N12
M12

L12

R11

P11

N11
M11
R10

P10

N10
M10

P9
N9
M9
R8

P8
N8
M8

P7
N7
M7
R6

P6
M6

A6
R5

P5
N5
M5

P4
N4
M4
R3

P3
N3
M3
R2

P2
M2
D2

AB1

R1

P1
N1
M1

AG14

AF14

AE14

Y14

AF13

AE13

AF12
AE12
AD12

CALISTOGA A0 _ FCBGA1466~D

+2.5V_CRT_DAC

5

U9H

VTT0
VTT1
VTT2
VTT3
VTT4
VTT5
VTT6
VTT7
VTT8
VTT9
VTT10
VTT11
VTT12
VTT13
VTT14
VTT15
VTT16
VTT17
VTT18
VTT19
VTT20
VTT21
VTT22
VTT23
VTT24
VTT25
VTT26
VTT27
VTT28
VTT29
VTT30
VTT31
VTT32
VTT33
VTT34
VTT35
VTT36
VTT37
VTT38
VTT39
VTT40
VTT41
VTT42
VTT43
VTT44
VTT45
VTT46
VTT47
VTT48
VTT49
VTT50
VTT51
VTT52
VTT53
VTT54
VTT55
VTT56
VTT57
VTT58
VTT59
VTT60
VTT61
VTT62
VTT63
VTT64
VTT65
VTT66
VTT67
VTT68
VTT69
VTT70
VTT71
VTT72
VTT73
VTT74
VTT75
VTT76

VCCAUX32
VCCAUX33
VCCAUX34
VCCAUX35
VCCAUX36
VCCAUX37
VCCAUX38
VCCAUX39
VCCAUX40

R378

1 2

10_0603_5%~D1@

P O W E R

+1.5V_RUN+1.05V_VCCP

+2.5V_RUN

H22

VCC_SYNC

VCC3G0
VCC3G1
VCC3G2
VCC3G3
VCC3G4
VCC3G5
VCC3G6

VCCA_3GBG
VSSA_3GBG

VCCA_HPLL

VCCA_LVDS
VSSA_LVDS

VCCA_MPLL
VCCA_TVBG

VSSA_TVBG

VCCHV0
VCCHV1
VCCHV2

VCCAUX0
VCCAUX1
VCCAUX2
VCCAUX3
VCCAUX4
VCCAUX5
VCCAUX6
VCCAUX7
VCCAUX8

VCCAUX9
VCCAUX10
VCCAUX11
VCCAUX12
VCCAUX13
VCCAUX14
VCCAUX15
VCCAUX16
VCCAUX17
VCCAUX18
VCCAUX19
VCCAUX20
VCCAUX21
VCCAUX22
VCCAUX23
VCCAUX24
VCCAUX25
VCCAUX26
VCCAUX27
VCCAUX28
VCCAUX29
VCCAUX30
VCCAUX31

MMBD4148_SOT23~D1@

B30
C30
A30

AB41
AJ41
L41
N41
R41
V41
Y41

AC33
G41
H41

E21
F21
G21

B26
C39
AF1

A38
B39

AF2
H20

G20

E19
F19
C20
D20
E20
F20

AH1
AH2

A28
B28
C28

D21
H19

A23
B23
B25

AK31
AF31
AE31
AC31
AL30
AK30
AJ30
AH30
AG30
AF30
AE30
AD30
AC30
AG29
AF29
AE29
AD29
AC29
AG28
AF28
AE28
AH22
AJ21
AH21
AJ20
AH20
AH19
P19
P16
AH15
P15
AH14

+3.3V_TV_DAC

1

VCCTX_LVDS0
VCCTX_LVDS1
VCCTX_LVDS2

VCCA_3GPLL

VCCA_CRTDAC0
VCCA_CRTDAC1
VSSA_CRTDAC2

VCCA_DPLLA
VCCA_DPLLB

VCCA_TVDACA0
VCCA_TVDACA1
VCCA_TVDACB0
VCCA_TVDACB1
VCCA_TVDACC0
VCCA_TVDACC1

VCCD_HMPLL0
VCCD_HMPLL1

VCCD_LVDS0
VCCD_LVDS1
VCCD_LVDS2

VCCD_TVDAC

VCCDQ_TVDAC

D17

2

3

TV DAC Voltge Follower Circuit - 700mV

+1.05V_VCCP

D D

CRB 270uF

220U_D2_4VM_R45~D

1

C367

+

2

4.7U_0603_6.3V6M~D

2.2U_0603_6.3V6K~D

C438

C332

1

1

2

2

0.22U_0402_10V4Z~D

2

3

0.47U_0402_10V4Z~D

C289

1

2

MCH_A6

1

2

MCH_D2
MCH_AB1

1

2

D12

MMBD4148_SOT23~D1@

C278

0.47U_0402_10V4Z~D
C434

+1.5V_RUN

1

C C

Place the C348
close to M3

B B

0.22U_0402_10V4Z~D

C348

1

2

Place the caps
close to pins

A A

CRT DAC Voltge Follower Cir cuit - 700mV

VCCTX_LVDS

W=30 mils

+1.5V_RUN_3GPLL
+2.5V_RUN

+1.5V_RUN_DPLLA
+1.5V_RUN_DPLLB
+1.5V_RUN_HPLL

VCCA_LVDS

+1.5V_RUN_MPLL

VCCA_TVBG
VSSA_TVBG

VCCA_TVDACA
VCCA_TVDACB
VCCA_TVDACC

+1.5V_RUN

VCCD_TVDAC

+1.5V_RUN_QTVDAC

+1.5V_RUN

1 2

10_0603_5%~D1@

4

VCC_SYNC

Should be placed on top

1 2

Cj

R344 0_0402_5%~D

1

2

R546

12

Place Bottom

VCCD_LVDS

0.1U_0402_16V4Z~D

C42

C483

0.1U_0402_16V4Z~D

+3.3V_RUN

4

1

2

R361

1@

+1.5V_RUN_PCIE

220U_D2_4VM_R45~D

1

+

2

C47

3

22n_0805_25V1@

+3.3V_RUN

1

2

0_0402_5%~D

R374

2@

0_0402_5%~D

10U_0805_4VAM~D

10U_0805_4VAM~D

C115

C83

1

1

2

2

+2.5V_CRT_DAC+2.5V_CRTDAC

0.022U_0402_16V7K~D

0.1U_0402_16V4Z~D

1@

C51

1

1

2

2

Ca Cb

Route VSSACRTDAC gnd from GMCH to
decoupling cap ground lead and then
connect to the gnd plane.

Connect the GND plane of pin G20
with decoupling cap of C296 pin2
GND via.

C33

10U_0805_4VAM~D1@

1

2

10U_0805_4VAM~D

Cc Cd

C30

Note : Ca~Cd No stuff for Ext. VGA.
Stuff for Int. VGA.

VCCTX_LVDS

4.7U_0603_6.3V6M~D1@

+2.5V_RUN

12

1

C304

12

C131

1@

C59

C274

0.1U_0402_16V4Z~D1@

2

L13

+1.5VRUN_PCIE

12

BLM21PG600SN1D_0805~D

Route +2.5V_RUN from GMCH pinG41 to
decoupling cap (C314)<200mil to the edge.

1 2

L10 BLM18PG181SN1_0603~D1@

CRTDAC: Route caps within
250mil of Alviso. Route FB
within 3" o f Calistoga

+1.5V_RUN

C43

0.01U_0402_16V7K~D1@

1

2

+1.5V_RUN_QTVDAC

C290

0.1U_0402_16V4Z~D1@

1

1

2

2

close pin B30/C30/A30

+1.5V_RUN_3GPLL +1.5V_RUN

0.1U_0402_16V4Z~D
C447

1

2

Should be placed in cavity

10U_0805_4VAM~D

C448

1

2

R409

1 2

0.5_0805_1%~D

+3GPLL_R

3

For Power measurement.
No need for RTS board

R99

0.1U_0402_16V4Z~D

22n_0805_25V

C273

1

1@

2

1 2

0_0805_5%~D

C271

1@

VCCD_TV_DAC

12

Cl

3

VCCA_LVDS

C41

0.1U_0402_16V4Z~D1@

+1.5V_RUN

+2.5V_RUN

close pin D21

0_0402_5%~D

0.022U_0402_16V7K~D
C270

1

1@

2

R54 0_0402_5%~D2@

C40

0.01U_0402_16V7K~D1@

1

1

2

2

1@

close pin A38

For Power measurement.
No need for RTS board

L39

+3V_GPLL

1 2

BLM21PG600SN1D_0805~D

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

12

0_0805_5%~D

3

+2.5V_RUN

1

2

+3VRUN_ATVBG

+3VRUN_TVDACA

+3VRUN_TVDACB

+3VRUN_TVDACC

R323

12

R421

2

+2.5V_RUN

R52 0_0402_5%~D1@

C314

0.1U_0402_16V4Z~D

+1.5V_RUN

+1.5V_RUN

+1.5V_RUN

+1.5V_RUN

VCCD_TVDAC

12

R51 0_0402_5%~D2@

+1.05V_VCCP

R60 0_0402_5%~D2@

+2.5V_RUN

R47 0_0402_5%~D1@

R48 0_0402_5%~D2@

R29 0_0402_5%~D1@

R24 0_0402_5%~D2@

R25 0_0402_5%~D1@

R30 0_0402_5%~D2@
R41 0_0402_5%~D1@

R46 0_0402_5%~D2@
R20 0_0402_5%~D1@

R23 0_0402_5%~D2@

45mA Max. 45mA Max.

0.1U_0402_16V4Z~D

40mA Max.

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

C514

1

2

VCCTX_LVDS

12
12

+2.5V_CRTDAC

12

VCCA_LVDS

12
12

VCCA_TVBG

12
12

VCCA_TVDACA

12
12

VCCA_TVDACB

12
12

VCCA_TVDACC

12
12

+1.5V_RUN_QTVDAC

0.022U_0402_16V7K~D
C307

1

2

+1.5V_RUN_HPLL

1

C460

2

+1.5V_RUN_DPLLA

1

C279

2

+3VRUN_TVDACA

1 2

0.022U_0402_16V7K~D

1@

3

22n_0805_25V1@

C14

Ce

1

2

+3VRUN_TVDACB

1 2

0.022U_0402_16V7K~D

1@

3

22n_0805_25V1@

C25

Cf

1

2

+3VRUN_TVDACC

1 2

0.022U_0402_16V7K~D

1@

3

22n_0805_25V1@

C39

Cg Ch

1

2

Ck

+1.5VRUN_QTVDAC

1 2

22n_0805_25V

C31

3

+1.5V_RUN

L38

12

BLM11A121S_0603~D

1

C450
22U_0805_6.3VAM~D

2

L6

12

10U_CK2125 100M-T_20%_0805~D

La Lb

1

+

C15

470U_D2_2.5VM_R15~D1@

2

Note : C15,C311 stuff for UMA
No Stuff for Ext. VGA.

2

BLM18PG181SN1_0603~D

1

2

La, Lb use 0_0805_5% resistor
for Int. VGA as Travis.

1

+3V_TVDAC

C19

0.1U_0402_16V4Z~D1@

1

2

C18

0.1U_0402_16V4Z~D1@

1

2

0.1U_0402_16V4Z~D

C21

1

2

L7

1 2

0.1U_0402_16V4Z~D

100mA

C32

C9

C8

+3VRUN_ATVBG

0.022U_0402_16V7K~D

1@

1@

C296

1

C7

2

+1.5V_RUN

+1.5V_RUN_MPLL

0.1U_0402_16V4Z~D

+1.5V_RUN_DPLLB

40mA Max.

0.1U_0402_16V4Z~D

L5

BLM18PG181SN1_0603~D1@

1 2

200mA

1 2

3

22n_0805_25V1@

1

C474

2

1

C285

2

C36

+3V_TVDAC

+3.3V_RUN

10U_0805_4VAM~D1@

C10

1

2

R28

0_0603_5%~D 1@

1 2

+3VRUN_ATV

0.1U_0402_16V4Z~D1@
C23

1

Ce, Cf, Cg, Ch, Cj, Ck,
Cl replace by 0 ohm

2

0805 resistor

+1.5V_RUN

R37 0_0402_5%~D1@

12
12

R36 0_0402_5%~D2@

+1.5V_RUN

L40

BLM11A121S_0603~D

1

2

10U_CK2125 100M-T_20%_0805~D

1

+

2

12

C488
22U_0805_6.3VAM~D

+1.5V_RUN+1.5V_RUN

L26

12

C311

470U_D2_2.5VM_R15~D1@

VCCD_LVDS

DELL CONFIDENTIAL/PROPRIETARY

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

Calistoga(4 of 6)

LA-3001P

13 73Monday, April 17, 2006

1

0.4

of

5

4

3

2

1

+1.05V_VCCP

AG27
AF27
AG26
AF26
AG25
AF25
AG24
AF24
AG23
AF23
AG22
AF22
AG21
AF21
AG20
AF20
AG19
AF19
R19
AG18
AF18
R18
AG17
AF17
AE17
AD17
AB17
AA17
W17
V17
T17
R17
AG16
AF16
AE16
AD16
AC16
AB16
AA16
Y16
W16
V16
U16
T16
R16
AG15
AF15
AE15
AD15
AC15
AB15
AA15
Y15
W15
V15
U15
T15
R15

AE27
AE26
AE25
AE24
AE23
AE22
AE21
AE20
AE19
AE18
AC17
Y17
U17

AR6
AP6
AN6
AL6
AK6
AJ6
AV1
AJ1

+1.5V_RUN+1.05V_VCCP

+1.8V_SUS+1.05V_VCCP

VCCSM_LF2
VCCSM_LF1

0.47U_0402_10V4Z~D
C497

Place near U9.AV1 & AJ1

0.47U_0402_10V4Z~D
C528

1

1

2

2

U9F

AD27

VCC_NCTF0

AC27

VCC_NCTF1

AB27

VCC_NCTF2

AA27

D D

0.22U_0402_10V4Z~D

0.22U_0402_10V4Z~D

C440

1

2

10U_0805_4VAM~D

10U_0805_4VAM~D

C345

1

2

C C

B B

0.22U_0402_10V4Z~D

C338

C413

1

1

2

2

1U_0603_10V4Z~D

C405

C337

1

1

2

2

220U_D2_4VM_R45~D

1

C548

+

2

220U_D2_4VM_R45~D

1

C568

+

2

CRB 270uF

A A

VCC_NCTF3

Y27

VCC_NCTF4

W27

VCC_NCTF5

V27

VCC_NCTF6

U27

VCC_NCTF7

T27

VCC_NCTF8

R27

VCC_NCTF9

AD26

VCC_NCTF10

AC26

VCC_NCTF11

AB26

VCC_NCTF12

AA26

VCC_NCTF13

Y26

VCC_NCTF14

W26

VCC_NCTF15

V26

VCC_NCTF16

U26

VCC_NCTF17

T26

VCC_NCTF18

R26

VCC_NCTF19

AD25

VCC_NCTF20

AC25

VCC_NCTF21

AB25

VCC_NCTF22

AA25

VCC_NCTF23

Y25

VCC_NCTF24

W25

VCC_NCTF25

V25

VCC_NCTF26

U25

VCC_NCTF27

T25

VCC_NCTF28

R25

VCC_NCTF29

AD24

VCC_NCTF30

AC24

VCC_NCTF31

AB24

VCC_NCTF32

AA24

VCC_NCTF33

Y24

VCC_NCTF34

W24

VCC_NCTF35

V24

VCC_NCTF36

U24

VCC_NCTF37

T24

VCC_NCTF38

R24

VCC_NCTF39

AD23

VCC_NCTF40

V23

VCC_NCTF41

U23

VCC_NCTF42

T23

VCC_NCTF43

R23

VCC_NCTF44

AD22

VCC_NCTF45

V22

VCC_NCTF46

U22

VCC_NCTF47

T22

VCC_NCTF48

R22

VCC_NCTF49

AD21

VCC_NCTF50

V21

VCC_NCTF51

U21

VCC_NCTF52

T21

VCC_NCTF53

R21

VCC_NCTF54

AD20

VCC_NCTF55

V20

VCC_NCTF56

U20

VCC_NCTF57

T20

VCC_NCTF58

R20

VCC_NCTF59

AD19

VCC_NCTF60

V19

VCC_NCTF61

U19

VCC_NCTF62

T19

VCC_NCTF63

AD18

VCC_NCTF64

AC18

VCC_NCTF65

AB18

VCC_NCTF66

AA18

VCC_NCTF67

Y18

VCC_NCTF68

W18

VCC_NCTF69

V18

VCC_NCTF70

U18

VCC_NCTF71

T18

VCC_NCTF72

M19

VCC100

L19

VCC101

N18

VCC102

M18

VCC103

L18

VCC104

P17

VCC105

N17

VCC106

M17

VCC107

N16

VCC108

M16

VCC109

L16

VCC110

CALISTOGA A0 _ FCBGA1466~D

VCCAUX_NCTF0
VCCAUX_NCTF1
VCCAUX_NCTF2
VCCAUX_NCTF3
VCCAUX_NCTF4
VCCAUX_NCTF5
VCCAUX_NCTF6
VCCAUX_NCTF7
VCCAUX_NCTF8

VCCAUX_NCTF9
VCCAUX_NCTF10
VCCAUX_NCTF11
VCCAUX_NCTF12
VCCAUX_NCTF13
VCCAUX_NCTF14
VCCAUX_NCTF15
VCCAUX_NCTF16
VCCAUX_NCTF17
VCCAUX_NCTF18
VCCAUX_NCTF19
VCCAUX_NCTF20
VCCAUX_NCTF21
VCCAUX_NCTF22
VCCAUX_NCTF23
VCCAUX_NCTF24
VCCAUX_NCTF25
VCCAUX_NCTF26
VCCAUX_NCTF27
VCCAUX_NCTF28
VCCAUX_NCTF29
VCCAUX_NCTF30
VCCAUX_NCTF31
VCCAUX_NCTF32
VCCAUX_NCTF33
VCCAUX_NCTF34
VCCAUX_NCTF35
VCCAUX_NCTF36
VCCAUX_NCTF37

P O W E R

VCCAUX_NCTF38
VCCAUX_NCTF39
VCCAUX_NCTF40
VCCAUX_NCTF41
VCCAUX_NCTF42
VCCAUX_NCTF43
VCCAUX_NCTF44
VCCAUX_NCTF45
VCCAUX_NCTF46
VCCAUX_NCTF47
VCCAUX_NCTF48
VCCAUX_NCTF49
VCCAUX_NCTF50
VCCAUX_NCTF51
VCCAUX_NCTF52
VCCAUX_NCTF53
VCCAUX_NCTF54
VCCAUX_NCTF55
VCCAUX_NCTF56
VCCAUX_NCTF57

VSS_NCTF0
VSS_NCTF1
VSS_NCTF2
VSS_NCTF3
VSS_NCTF4
VSS_NCTF5
VSS_NCTF6
VSS_NCTF7
VSS_NCTF8

VSS_NCTF9
VSS_NCTF10
VSS_NCTF11
VSS_NCTF12

VCC_SM100

VCC_SM101

VCC_SM102

VCC_SM103

VCC_SM104

VCC_SM105

VCC_SM106

VCC_SM107

U9G

AA33

VCC0

W33

VCC1

P33

VCC2

N33

VCC3

L33

VCC4

J33

VCC5

AA32

VCC6

Y32

VCC7

W32

VCC8

V32

VCC9

P32

VCC10

N32

VCC11

M32

VCC12

L32

VCC13

J32

VCC14

AA31

VCC15

W31

VCC16

V31

VCC17

T31

VCC18

R31

VCC19

P31

VCC20

N31

VCC21

M31

VCC22

AA30

VCC23

Y30

VCC24

W30

VCC25

V30

VCC26

U30

VCC27

T30

VCC28

R30

VCC29

P30

VCC30

N30

VCC31

M30

VCC32

AA29

W29

M29

AB28
AA28

M28

M27

M25

M24
AB23
AA23

M23
AC22

AB22

W22

M22
AC21

AA21

W21

M21
AC20

AB20

W20

M20
AB19

AA19

L30
Y29
V29

U29
R29
P29

L29

Y28
V28
U28
T28
R28
P28
N28

L28
P27
N27

L27
P26
N26

L26
N25

L25
P24
N24

Y23
P23
N23

L23

Y22
P22

N22

L22

N21

L21

Y20
P20

N20

L20

Y19
N19

P O W E R

VCC33
VCC34
VCC35
VCC36
VCC37
VCC38
VCC39
VCC40
VCC41
VCC42
VCC43
VCC44
VCC45
VCC46
VCC47
VCC48
VCC49
VCC50
VCC51
VCC52
VCC53
VCC54
VCC55
VCC56
VCC57
VCC58
VCC59
VCC60
VCC61
VCC62
VCC63
VCC64
VCC65
VCC66
VCC67
VCC68
VCC69
VCC70
VCC71
VCC72
VCC73
VCC74
VCC75
VCC76
VCC77
VCC78
VCC79
VCC80
VCC81
VCC82
VCC83
VCC84
VCC85
VCC86
VCC87
VCC88
VCC89
VCC90
VCC91
VCC92
VCC93
VCC94
VCC95
VCC96
VCC97
VCC98
VCC99

CALISTOGA A0 _ FCBGA1466~D

VCC_SM0
VCC_SM1
VCC_SM2
VCC_SM3
VCC_SM4
VCC_SM5
VCC_SM6
VCC_SM7
VCC_SM8

VCC_SM9
VCC_SM10
VCC_SM11
VCC_SM12
VCC_SM13
VCC_SM14
VCC_SM15
VCC_SM16
VCC_SM17
VCC_SM18
VCC_SM19
VCC_SM20
VCC_SM21
VCC_SM22
VCC_SM23
VCC_SM24
VCC_SM25
VCC_SM26
VCC_SM27
VCC_SM28
VCC_SM29
VCC_SM30
VCC_SM31
VCC_SM32
VCC_SM33
VCC_SM34
VCC_SM35
VCC_SM36
VCC_SM37
VCC_SM38
VCC_SM39
VCC_SM40
VCC_SM41
VCC_SM42
VCC_SM43
VCC_SM44
VCC_SM45
VCC_SM46
VCC_SM47
VCC_SM48
VCC_SM49
VCC_SM50
VCC_SM51
VCC_SM52
VCC_SM53
VCC_SM54
VCC_SM55
VCC_SM56
VCC_SM57
VCC_SM58
VCC_SM59
VCC_SM60
VCC_SM61
VCC_SM62
VCC_SM63
VCC_SM64
VCC_SM65
VCC_SM66
VCC_SM67
VCC_SM68
VCC_SM69
VCC_SM70
VCC_SM71
VCC_SM72
VCC_SM73
VCC_SM74
VCC_SM75
VCC_SM76
VCC_SM77
VCC_SM78
VCC_SM79
VCC_SM80
VCC_SM81
VCC_SM82
VCC_SM83
VCC_SM84
VCC_SM85
VCC_SM86
VCC_SM87
VCC_SM88
VCC_SM89
VCC_SM90
VCC_SM91
VCC_SM92
VCC_SM93
VCC_SM94
VCC_SM95
VCC_SM96
VCC_SM97
VCC_SM98
VCC_SM99

AU41
AT41
AM41
AU40
BA34
AY34
AW34
AV34
AU34
AT34
AR34
BA30
AY30
AW30
AV30
AU30
AT30
AR30
AP30
AN30
AM30
AM29
AL29
AK29
AJ29
AH29
AJ28
AH28
AJ27
AH27
BA26
AY26
AW26
AV26
AU26
AT26
AR26
AJ26
AH26
AJ25
AH25
AJ24
AH24
BA23
AJ23
BA22
AY22
AW22
AV22
AU22
AT22
AR22
AP22
AK22
AJ22
AK21
AK20
BA19
AY19
AW19
AV19
AU19
AT19
AR19
AP19
AK19
AJ19
AJ18
AJ17
AH17
AJ16
AH16
BA15
AY15
AW15
AV15
AU15
AT15
AR15
AJ15
AJ14
AJ13
AH13
AK12
AJ12
AH12
AG12
AK11
BA8
AY8
AW8
AV8
AT8
AR8
AP8
BA6
AY6
AW6
AV6
AT6

+1.8V_SUS

VCCSM_LF4
VCCSM_LF5

0.47U_0402_10V4Z~D

C515

Place near U9.AT41 & AM41

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

C496

1

2

0.47U_0402_10V4Z~D

1

2

Place near U9.BA23

0.47U_0402_10V4Z~D

1

2

Place near U9.BA15

10U_0805_4VAM~D

10U_0805_4VAM~D

C185

1

2

C533

C531

0.47U_0402_10V4Z~D

C526

1

1

2

2

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

C500

C490

1

2

C186

1

2

C184

1

1

2

2

0.47U_0402_10V4Z~D
C525

1

2

0.47U_0402_10V4Z~D
C489

1

2

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

Calistoga(5 of 6)

LA-3001P

14 73Monday, April 17, 2006

1

0.4

of

5

U9I

AC41

VSS0

AA41

VSS1

W41

VSS2

T41

VSS3

P41

VSS4

M41

VSS5

J41

VSS6

F41

VSS7

AV40

VSS8

AP40

D D

C C

B B

A A

VSS9

AN40

VSS10

AK40

VSS11

AJ40

VSS12

AH40

VSS13

AG40

VSS14

AF40

VSS15

AE40

VSS16

B40

VSS17

AY39

VSS18

AW39

VSS19

AV39

VSS20

AR39

VSS21

AN39

VSS22

AJ39

VSS23

AC39

VSS24

AB39

VSS25

AA39

VSS26

Y39

VSS27

W39

VSS28

V39

VSS29

T39

VSS30

R39

VSS31

P39

VSS32

N39

VSS33

M39

VSS34

P O W E R

VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65
VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77
VSS78
VSS79
VSS80
VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS97
VSS98
VSS99

CALISTOGA A0 _ FCBGA1466~D

AT38
AM38
AH38
AG38

AF38

AE38

AK37
AH37

AB37

AA37

W37

AY36
AW36
AN36
AH36
AG36

AF36

AE36
AC36

BA35

AV35
AR35
AH35

AB35

AA35

W35

AN34

AK34
AG34

AF34

L39

J39
H39
G39
F39
D39

C38

Y37
V37

T37
R37
P37
N37
M37

L37

J37
H37
G37
F37
D37

C36
B36

Y35
V35

T35
R35
P35
N35
M35

L35

J35
H35
G35
F35
D35

VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS140
VSS141
VSS142
VSS143
VSS144
VSS145
VSS146
VSS147
VSS148
VSS149
VSS150
VSS151
VSS152
VSS153
VSS154
VSS155
VSS156
VSS157
VSS158
VSS159
VSS160
VSS161
VSS162
VSS163
VSS164
VSS165
VSS166
VSS167
VSS168
VSS169
VSS170
VSS171
VSS172
VSS173
VSS174
VSS175
VSS176
VSS177
VSS178
VSS179
VSS180
VSS181
VSS182
VSS183
VSS184
VSS185
VSS186
VSS187
VSS188
VSS189
VSS190
VSS191
VSS192
VSS193
VSS194
VSS195
VSS196
VSS197
VSS198
VSS199

4

AE34
AC34
C34
AW33
AV33
AR33
AE33
AB33
Y33
V33
T33
R33
M33
H33
G33
F33
D33
B33
AH32
AG32
AF32
AE32
AC32
AB32
G32
B32
AY31
AV31
AN31
AJ31
AG31
AB31
Y31
AB30
E30
AT29
AN29
AB29
T29
N29
K29
G29
E29
C29
B29
A29
BA28
AW28
AU28
AP28
AM28
AD28
AC28
W28
J28
E28
AP27
AM27
AK27
J27
G27
F27
C27
B27
AN26
M26
K26
F26
D26
AK25
P25
K25
H25
E25
D25
A25
BA24
AU24
AL24
AW23
AT23
AN23
AM23
AH23
AC23
W23
K23
J23
F23
C23
AA22
K22
G22
F22
E22
D22
A22
BA21
AV21
AR21

3

U9J

AN21

VSS200

AL21

VSS201

AB21

VSS202

Y21

VSS203

P21

VSS204

K21

VSS205

J21

VSS206

H21

VSS207

C21

VSS208

AW20

VSS209

AR20

VSS210

AM20

VSS211

AA20

VSS212

K20

VSS213

B20

VSS214

A20

VSS215

AN19

VSS216

AC19

VSS217

W19

VSS218

K19

VSS219

G19

VSS220

C19

VSS221

AH18

VSS222

P18

VSS223

H18

VSS224

D18

VSS225

A18

VSS226

AY17

VSS227

AR17

VSS228

AP17

VSS229

AM17

AK17
AV16

AN16

AL16

AN15
AM15

AK15

M15

BA14
AT14
AK14

AD14

AA14

AV13
AR13
AN13
AM13

AL13
AG13

AY12
AC12

AD11

AA11

AV10

AP10

AL10

AJ10

J16
F16
C16

N15
L15

B15
A15

U14
K14
H14
E14

P13
F13
D13
B13

K12
H12
E12

Y11

J11
D11
B11

P O W E R

VSS230
VSS231
VSS232
VSS233
VSS234
VSS235
VSS236
VSS237
VSS238
VSS239
VSS240
VSS241
VSS242
VSS243
VSS244
VSS245
VSS246
VSS247
VSS248
VSS249
VSS250
VSS251
VSS252
VSS253
VSS254
VSS255
VSS256
VSS257
VSS258
VSS259
VSS260
VSS261
VSS262
VSS265
VSS264
VSS263
VSS266
VSS267
VSS268
VSS269
VSS270
VSS271
VSS272
VSS273
VSS274
VSS275
VSS276
VSS277
VSS278
VSS279

CALISTOGA A0 _ FCBGA1466~D

VSS280
VSS281
VSS282
VSS283
VSS284
VSS285
VSS286
VSS287
VSS288
VSS289
VSS290
VSS292
VSS291
VSS293
VSS294
VSS295
VSS296
VSS297
VSS298
VSS299
VSS300
VSS301
VSS302
VSS303
VSS304
VSS305
VSS306
VSS307
VSS308
VSS309
VSS310
VSS311
VSS312
VSS313
VSS314
VSS315
VSS316
VSS317
VSS318
VSS319
VSS320
VSS321
VSS322
VSS323
VSS324
VSS325
VSS326
VSS327
VSS328
VSS329
VSS330
VSS331
VSS332
VSS333
VSS334
VSS335
VSS336
VSS337
VSS338
VSS339
VSS340
VSS341
VSS342
VSS343
VSS344
VSS345
VSS346
VSS347
VSS348
VSS349
VSS350
VSS351
VSS352
VSS353
VSS354
VSS355
VSS356
VSS357
VSS358
VSS359
VSS360

2

AG10
AC10
W10
U10
BA9
AW9
AR9
AH9
AB9
Y9
R9
G9
E9
A9
AG8
AD8
AA8
U8
K8
C8
BA7
AV7
AP7
AL7
AJ7
AH7
AF7
AC7
R7
G7
D7
AG6
AD6
AB6
Y6
U6
N6
K6
H6
B6
AV5
AF5
AD5
AY4
AR4
AP4
AL4
AJ4
Y4
U4
R4
J4
F4
C4
AY3
AW3
AV3
AL3
AH3
AG3
AF3
AD3
AC3
AA3
G3
AT2
AR2
AP2
AK2
AJ2
AD2
AB2
Y2
U2
T2
N2
J2
H2
F2
C2
AL1

1

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

Calistoga(6 of 6)

LA-3001

15 73Monday, April 17, 2006

1

0.4

of

5

4

3

2

1

C

B

E

1

2

3

2222 SYMBOL(SOT23-NEW)

+1.05V_VCCP

FAN1 Control and Tachometer

D D

+3.3V_RUN

12

R113
10K_0402_5%~D

1

DAT_SMB<30>
CLK_SMB<30>

+3.3V_SUS

SUSPWROK<23,33>

ICH_PWRGD#<33>
POWER_SW#<30,35>

1 2

1K_0402_5%~D

1 2

SNIFFER_GREEN#<35>
SNIFFER_YELLOW#<35>

R256

C233

@

2

1

2

VGA_THERMDN<45>

VGA_THERMDP<45>

1

2

C269

R242

R247

12

12

JFAN1

1

1

2

2

3

3

MOLEX_53398-0371~D

1

2

THERMTRIP_VGA#<44>

12

2200P_0402_50V7K~D

12

C250

1

2

VGA_THERMDN_R

VGA_THERMDP_R

R321 8.2K_0402_5%~D

C235

RB751V_SOD323~D@

C C

H_THERMDA/H_THERMDC
routing together. Trace
width / Spacing = 10 / 10 mil

B B

VGA_THERMDN_R/VGA_THERMDN,
VGA_THERM DP_R/VGA _T HERMDP routing
together. Trace width / Spacing = 10 / 10 mil

A A

D10

H_THERMDA<7>

H_THERMDC<7>

Place C255 as close to the
Guardian pins as possible

1

C253

@

2200P_0402_50V7K~D

2

Place near the bottom SODIMM For UMA design

1

22U_1206_10V4Z~D

2

2 1

+3.3V_SUS

0.1U_0402_16V4Z~D

Vset=(Tp-70/21)

+3.3V_SUS

C247

0.1U_0402_16V4Z~D

Q13

1@

E

31

PMBT3904_SOT23~D

B

2

C

+FAN1_VOUT

1000P_0402_50V7K~D@

1

C234

2

Place C252 as close to the
Guardian pins as possible

2200P_0402_50V7K~D

C252

R320

49.9_0603_1%~D

1 2

1

C268

2

+RTC_CELL

0.1U_0402_16V4Z~D

1

2

332K_0402_1%~D

118K_0402_1%~D

To cut the stub trace
for discrete M/B

R608 0_0402_5%~D1@

R609 0_0402_5%~D1@

For Discrete: Stuff R259,R249 and no stuff Q13,C253
For UMA: Stuff Q13 and no stuff R259,R249

5

FAN1_TACH <30>

1000P_0402_50V7K~D

DAT_SMB
CLK_SMB

1 2

R284 7.5K_0402_5%~D

+3VSUS_THRM

1 2

R315 1K_0402_5%~D

1 2

R316 1K_0402_5%~D

THERMATRIP1#
THERMATRIP2#
THERMTRIP_VGA#

C255
2200P_0402_50V7K~D

4

+FAN1_VOUT

SMBUS ADDRESS : 2F

R259

2@

2@

0_0402_5%~D

R249

0_0402_5%~D

U16

7

SMDATA

8

SMBCLK

23

LDO_SHDN#_ADDR

35

DP2

34

DN2

12

+3V_SUS

21

VSUS_PWRGD

18

+RTC_PWR3V

13

+3V_PWROK#

38

POWER_SW#

14

THERMTRIP1#

15

THERMTRIP2#

16

THERMTRIP3#

39

VSET

29

HW_LOCK#

9

VSS

1

DP3

2

DN3

6

FAN_OUT

33

FAN_DAC

10

GPIO1

11

GPIO2

19

GPIO3

20

GPIO4

32

GPIO5

41

Thermal

EMC4000_C_QFN40~D

VGA_THERMDN_R

12

VGA_THERMDP_R

12

+1.05V_VCCP

THERMTRIP_MCH#<10>

THERMTRIP_SIO

2.2K_0402_5%~D

1 2

H_THERMTRIP#<7>

2.2K_0402_5%~D

1 2

ATF_INT#

LDO_POK

THERM_STP#

INTRUDER#

LDO_SET

LDO_OUT
LDO_OUT

LDO_IN
LDO_IN

VDD_5V

+5V_RUN

10U_0805_10V4Z~D

R255

PMBT3904_SOT23~D

R278

PMBT3904_SOT23~D

VCP
VCP

DN1
DP1

C257

1

2

+3.3V_SUS

12

R260

8.2K_0402_5%~D

THERMATRIP1#

C

1

3 1

12

8.2K_0402_5%~D
R317

THERMATRIP2#

C

3 1

1K_0603_5%~D

12

R279

C262

0.1U_0402_16V4Z~D

2

1

C267

0.1U_0402_16V4Z~D

2

ATF_INT# <30>

+3.3V_ALW

R285 10K_0402_5%~D@

1

C11
10U_0805_10V4Z~D

2

1

C259
1U_0603_10V4Z~D

2

May need to place thermal resistor underneath WWAN Mini Card stuff
this thermistor circuit for additional sensor in Discrete Down Designs

+5V_SUS

10KB_0603_1%_TSM1A103F34D3R~D

R21

2.21K_0603_1%~D

1

C16
2200P_0402_50V7K~D

2

2.5V_RUN_PWRGD <33>

1

C251

12

R250
10K_0402_5%~D

2200P_0402_50V7K~D

2

THERMTRIP_SIO <31>

ACAV_IN <30,43>

THERM_STP# <39>

12

1

C17

2

1

C260

2

+RTC_CELL

+2.5V_RUN

@

0.1U_0402_16V4Z~D

1 2

0.27_1210_5%~D

@

0.1U_0402_16V4Z~D

2

B

E

Q14

+3.3V_SUS

2

B

E

Q20

ATF_INT#

17

VCP1

3

VCP2

40

31

REM_DIODE1_ N , R E M _ D I O D E 1_P routing together.
Trace width / Spacing = 10 / 10 mil

REM_DIODE1_N

36

REM_DIODE1_P

37

30
4

22

LDO_SET

24
25

27

26
28

+3V_LDOIN

5

1

C261

0.1U_0402_16V4Z~D

2

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

Place thermal resistor near the SODIMM For discrete design

+5V_SUS

VCP1

R440

1 2

2N7002_SOT23~D

Q24

Place under CPU

E

31

B

Q3

2

PMBT3904_SOT23~D

C

Place C251 as close to the
Guardian pins as possible

R251

+3.3V_RUN

2

13

D

S

LDO_SET

+5V_SUS

2

G

2N7002_SOT23~D

2@

Q7

+2.5V_RUN

12

R18

2@

10K_0402_5%~D

5V_CAL_SIO# <31>

R280

@

31.6K_0402_1%~D

R133

10KB_0603_1%_TSM1A103F34D3R~D

R19

2@

2.21K_0603_1%~D

1

C12

2@

2200P_0402_50V7K~D

2

+5V_SUS

R22
10K_0402_5%~D

13

D

2

G

S

1

C100

2

Voltage marg i n i n g c i r c uit for LDO output.For
Vmargin, stu f f R 2 80 = 3 1 . 6K and R279=1K for production

2@

1 2

Dell COE schematic suggest populate
for discrete down design

5V_CAL_SIO2# <31>

2200P_0402_50V7K~D@

DELL CONFIDENTIAL/PROPRIETARY

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.
Thermal sensor and Fan

LA-3001P

1

16 73Monday, April 17, 2006

0.3

of

5

DDR_A_DQS#[0..7]<11>

DDR_A_D[0..63]<11>
DDR_A_DM[0..7]<11>
DDR_A_DQS[0..7]<11>

DDR_A_MA[0..13]<11>

D D

C C

+0.9V_DDR_VTT

C205

0.1U_0402_16V4Z~D

1

2

B B

DDR_A_BS0
DDR_A_MA10
DDR_A_MA1
DDR_A_MA3

DDR_A_MA5
DDR_A_MA8

DDR_A_MA12

M_ODT1
DDR_CS1_DIMMA#
DDR_A_CAS#

A A

DDR_A_WE#

5

C206

0.1U_0402_16V4Z~D

1

2

+1.8V_SUS

Layout Note:
Place one cap close to every 2 pullup
resistors terminated to +0.9V_DDR_VTT

0.1U_0402_16V4Z~D

C207

0.1U_0402_16V4Z~D

1

2

RP6

1 8
2 7
3 6
4 5

56_1206_8P4R_5%~D

RP7

1 8
2 7
3 6
4 5

56_1206_8P4R_5%~D

RP5

1 8
2 7
3 6
4 5

56_1206_8P4R_5%~D

2.2U_0603_6.3V6K~D

1

2

0.1U_0402_16V4Z~D

1

2

0.1U_0402_16V4Z~D

C208

1

2

+0.9V_DDR_VTT

1

2

Layout Note:
Place near JDIMA1

2.2U_0603_6.3V6K~D

2.2U_0603_6.3V6K~D

C224

C223

1

1

2

2

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

C221

C222

1

1

2

2

C209

C210

0.1U_0402_16V4Z~D

C211

0.1U_0402_16V4Z~D

1

1

2

2

RP10

DDR_A_MA6

1 8

DDR_A_MA7

2 7

DDR_A_MA11

3 6

DDR_CKE1_DIMMA

4 5

56_1206_8P4R_5%~D

RP8

DDR_A_MA13

1 8

M_ODT0

2 7

DDR_CS0_DIMMA#DDR_A_MA9

3 6

DDR_A_RAS#

4 5

56_1206_8P4R_5%~D

RP9

DDR_A_BS1

1 8

DDR_A_MA0

2 7

DDR_A_MA2

3 6

DDR_A_MA4

4 5

56_1206_8P4R_5%~D

DDR_A_BS2

1 2

R227 56_0402_5%~D

R228 56_0402_5%~D

1 2

DDR_CKE0_DIMMA

C217

C213

0.1U_0402_16V4Z~D

4

2.2U_0603_6.3V6K~D

2.2U_0603_6.3V6K~D

C214

C215

1

1

2

2

0.1U_0402_16V4Z~D

C216

1

2

C228

0.1U_0402_16V4Z~D

1

2

0.1U_0402_16V4Z~D

C226

0.1U_0402_16V4Z~D

C227

1

1

2

2

4

C229

1

2

Layout Note:
Place these resistor
closely JDIMA1,all
trace length<750 mil

Layout Note:
Place these resistor
closely JDIMA1,all
trace length
Max=1.3"

C231

0.1U_0402_16V4Z~D

C230

0.1U_0402_16V4Z~D

1

1

2

2

DDR_CKE0_DIMMA<10>

DDR_CS1_DIMMA#<10>

3

DDR_A_BS2<11>

DDR_A_BS0<11>
DDR_A_WE#<11>

DDR_A_CAS#<11>

CLK_SDATA<6,18>
CLK_SCLK<6,18>

+3.3V_RUN

+1.8V_SUS

JDIMA1

1

VREF

3

DDR_A_D0
DDR_A_D1

DDR_A_DQS#0
DDR_A_DQS0

DDR_A_D2
DDR_A_D3

DDR_A_D8
DDR_A_D9

DDR_A_DQS#1
DDR_A_DQS1

DDR_A_D10
DDR_A_D11

DDR_A_D16
DDR_A_D17

DDR_A_DQS#2
DDR_A_DQS2

DDR_A_D18
DDR_A_D19

DDR_A_D24
DDR_A_D25

DDR_A_DM3

DDR_A_D26
DDR_A_D27

DDR_CKE0_DIMMA

DDR_A_BS2
DDR_A_MA12

DDR_A_MA9
DDR_A_MA8

DDR_A_MA5
DDR_A_MA3
DDR_A_MA1

DDR_A_MA10
DDR_A_WE#
DDR_A_CAS#

DDR_CS1_DIMMA#

M_ODT1<10>

M_ODT1
DDR_A_D32

DDR_A_D33
DDR_A_DQS#4

DDR_A_DQS4
DDR_A_D34

DDR_A_D35
DDR_A_D40

DDR_A_D41
DDR_A_DM5
DDR_A_D42

DDR_A_D43
DDR_A_D48

DDR_A_D49

DDR_A_DQS#6
DDR_A_DQS6

DDR_A_D50
DDR_A_D51

DDR_A_D56
DDR_A_D57

DDR_A_DM7
DDR_A_D58

DDR_A_D59
CLK_SDATA

CLK_SCLK

0.1U_0402_16V4Z~D
C218

1

2

2.2U_0603_6.3V6K~D
C212

1

2

5
7

9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39

41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99

101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199

VSS
DQ0
DQ1
VSS
DQS0#
DQS0
VSS
DQ2
DQ3
VSS
DQ8
DQ9
VSS
DQS1#
DQS1
VSS
DQ10
DQ11
VSS

VSS
DQ16
DQ17
VSS
DQS2#
DQS2
VSS
DQ18
DQ19
VSS
DQ24
DQ25
VSS
DM3
NC
VSS
DQ26
DQ27
VSS
CKE0
VDD
NC
BA2
VDD
A12
A9
A8
VDD
A5
A3
A1
VDD
A10/AP
BA0
WE#
VDD
CAS#
NC/S1#
VDD
NC/ODT1
VSS
DQ32
DQ33
VSS
DQS4#
DQS4
VSS
DQ34
DQ35
VSS
DQ40
DQ41
VSS
DM5
VSS
DQ42
DQ43
VSS
DQ48
DQ49
VSS
NC,TEST
VSS
DQS6#
DQS6
VSS
DQ50
DQ51
VSS
DQ56
DQ57
VSS
DM7
VSS
DQ58
DQ59
VSS
SDA
SCL
VDDSPD

FOX_AS0A426-MARL-7F~D

DIMMA

REVERSE

VSS
DQ4
DQ5
VSS
DM0
VSS
DQ6
DQ7

VSS
DQ12
DQ13

VSS

DM1

VSS

CK0#

VSS
DQ14
DQ15

VSS

VSS
DQ20
DQ21

VSS

DM2

VSS
DQ22
DQ23

VSS
DQ28
DQ29

VSS

DQS3#

DQS3

VSS
DQ30
DQ31

VSS

NC/CKE1

VDD

NC/A15
NC/A14

VDD

VDD

VDD

RAS#

VDD
ODT0

NC/A13

VDD

VSS
DQ36
DQ37

VSS

DM4

VSS
DQ38
DQ39

VSS
DQ44
DQ45

VSS

DQS5#

DQS5

VSS
DQ46
DQ47

VSS
DQ52
DQ53

VSS

CK1#

VSS

DM6

VSS
DQ54
DQ55

VSS
DQ60
DQ61

VSS

DQS7#

DQS7

VSS
DQ62
DQ63

VSS

SAO

2

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30

CK0

32
34
36
38
40

42
44
46
48
50

NC

52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90

A11

92

A7

94

A6

96
98

A4

100

A2

102

A0

104
106

BA1

108
110

S0#

112
114
116
118
120

NC

122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164

CK1

166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200

SA1

Place DIMM-A on Top

(MH=6.5mm)

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

2

+1.8V_SUS

DDR_A_DM0
DDR_A_D6

DDR_A_D7
DDR_A_D12

DDR_A_D13
DDR_A_DM1
M_CLK_DDR0

M_CLK_DDR#0
DDR_A_D14

DDR_A_D15

DDR_A_D20
DDR_A_D21

DDR_A_DM2
DDR_A_D22

DDR_A_D23
DDR_A_D28

DDR_A_D29
DDR_A_DQS#3

DDR_A_DQS3
DDR_A_D30

DDR_A_D31
DDR_CKE1_DIMMA

DDR_A_MA11
DDR_A_MA7
DDR_A_MA6

DDR_A_MA4
DDR_A_MA2
DDR_A_MA0

DDR_A_BS1
DDR_A_RAS#DDR_A_BS0
DDR_CS0_DIMMA#

M_ODT0
DDR_A_MA13

DDR_A_D36
DDR_A_D37

DDR_A_DM4
DDR_A_D38

DDR_A_D39
DDR_A_D44

DDR_A_D45
DDR_A_DQS#5

DDR_A_DQS5
DDR_A_D46

DDR_A_D47
DDR_A_D52

DDR_A_D53
M_CLK_DDR1

M_CLK_DDR#1
DDR_A_DM6
DDR_A_D54

DDR_A_D55
DDR_A_D60

DDR_A_D61
DDR_A_DQS#7

DDR_A_DQS7
DDR_A_D62

DDR_A_D63

10K_0402_5%~D

V_DDR_MCH_REF

DDR_A_D4
DDR_A_D5

10K_0402_5%~D

R230

1 2

1

V_DDR_MCH_REF <10,18,41>

PM_EXTTS#0_R <18>

PM_EX TTS#0 <10>

M_CLK_DDR0 <10>

M_CLK_DDR#0 <10>

DDR_CKE1_DIMMA <10>

DDR_A_BS1 <11>
DDR_A_RAS# <11>
DDR_CS0_DIMMA# <10>

M_ODT0 <10>

M_CLK_DDR1 <10>
M_CLK_DDR#1 <10>

R229

1 2

2.2U_0603_6.3V6K~D
C219

1

2

1 2

0_0402_5%~D

0.1U_0402_16V4Z~D

R231

C220

1

2

DELL CONFIDENTIAL/PROPRIETARY

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

DDRII-SODIMM SLOT-A

LA-3001P

17 73Monday, April 17, 2006

1

0.4

of

5

DDR_B_DQS#[0..7]<11>

DDR_B_D[0..63]<11>
DDR_B_DM[0..7]<11>
DDR_B_DQS[0..7]<11>

DDR_B_MA[0..13]<11>

D D

+1.8V_SUS

C C

+0.9V_DDR_VTT

C585

0.1U_0402_16V4Z~D

C587

0.1U_0402_16V4Z~D

C586

0.1U_0402_16V4Z~D

1

2

1

2

RP22

1 8
2 7
3 6
4 5

56_1206_8P4R_5%~D

RP21

1 8
2 7
3 6
4 5

56_1206_8P4R_5%~D

RP20

1 8
2 7
3 6
4 5

56_1206_8P4R_5%~D

1

2

B B

M_ODT3
DDR_CS3_DIMMB#
DDR_B_CAS#
DDR_B_WE#

DDR_B_BS0
DDR_B_MA10
DDR_B_MA1
DDR_B_MA3

DDR_B_MA5
DDR_B_MA8
DDR_B_MA9

A A

DDR_B_MA12

5

Layout Note:
Place near JDIMB1

2.2U_0603_6.3V6K~D

C629

1

2

0.1U_0402_16V4Z~D

C630

1

2

Layout Note:
Place one cap close to every 2 pullup
resistors terminated to +0.9V_DDR_VTT

C584

0.1U_0402_16V4Z~D

C583

0.1U_0402_16V4Z~D

1

1

2

2

+0.9V_DDR_VTT

2.2U_0603_6.3V6K~D

2.2U_0603_6.3V6K~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

1 8
2 7
3 6
4 5

56_1206_8P4R_5%~D

1 8
2 7
3 6
4 5

56_1206_8P4R_5%~D

1 8
2 7
3 6
4 5

56_1206_8P4R_5%~D

1 2

R542 56_0402_5%~D

1 2

R541 56_0402_5%~D

1

2

1

2

C582

1

2

RP19

RP18

RP17

C624

1

2

0.1U_0402_16V4Z~D

C625

1

2

C643

0.1U_0402_16V4Z~D

1

2

DDR_B_MA13
M_ODT2
DDR_CS2_DIMMB#
DDR_B_RAS#

DDR_B_BS1
DDR_B_MA0
DDR_B_MA2
DDR_B_MA4

DDR_B_MA6
DDR_B_MA7
DDR_B_MA11
DDR_CKE3_DIMMB

DDR_B_BS2

DDR_CKE2_DIMMB

C602

C601

0.1U_0402_16V4Z~D

4

2.2U_0603_6.3V6K~D

2.2U_0603_6.3V6K~D

0.1U_0402_16V4Z~D

C642

1

2

C603

C600

1

1

2

2

C604

1

2

C638

0.1U_0402_16V4Z~D

C639

0.1U_0402_16V4Z~D

C641

0.1U_0402_16V4Z~D

C640

0.1U_0402_16V4Z~D

1

2

4

1

2

Layout Note:
Place these resistor
closely JDIMB1,all
trace length<750 mil

Layout Note:
Place these resistor
closely JDIMB1,all
trace length
Max=1.3"

1

2

C637

0.1U_0402_16V4Z~D

1

1

2

2

DDR_CKE2_DIMMB<10>

DDR_CS3_DIMMB#<10>

3

DDR_B_BS2<11>

DDR_B_BS0<11>
DDR_B_WE#<11>

DDR_B_CAS#<11>

CLK_SDATA<6,17>
CLK_SCLK<6,17>

+3.3V_RUN

+1.8V_SUS +1.8V_SUS

JDIMB1

1

VREF

3

VSS

5

DDR_B_D0
DDR_B_DQS#0

DDR_B_D1
DDR_B_D4

DDR_B_D8
DDR_B_D9

DDR_B_DQS#1
DDR_B_DQS1

DDR_B_D10
DDR_B_D11

DDR_B_D16
DDR_B_D17

DDR_B_DQS#2
DDR_B_DQS2

DDR_B_D18
DDR_B_D19

DDR_B_D24
DDR_B_D25

DDR_B_DM3

DDR_B_D26
DDR_B_D27

DDR_CKE2_DIMMB

DDR_B_BS2
DDR_B_MA12

DDR_B_MA9
DDR_B_MA8

DDR_B_MA5
DDR_B_MA3
DDR_B_MA1

DDR_B_MA10
DDR_B_BS0
DDR_B_WE#

DDR_B_CAS#
DDR_CS3_DIMMB#

M_ODT3<10>

M_ODT3
DDR_B_D32

DDR_B_D33
DDR_B_DQS#4

DDR_B_DQS4
DDR_B_D34

DDR_B_D35
DDR_B_D40

DDR_B_D41
DDR_B_DM5
DDR_B_D42

DDR_B_D43
DDR_B_D48

DDR_B_D49

DDR_B_DQS#6
DDR_B_DQS6

DDR_B_D50
DDR_B_D51

DDR_B_D56
DDR_B_D57

DDR_B_DM7
DDR_B_D58

DDR_B_D59
CLK_SDATA

CLK_SCLK

0.1U_0402_16V4Z~D
C621

1

2

2.2U_0603_6.3V6K~D
C626

1

2

7

9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39

41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99

101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199

DQ0
DQ1
VSS
DQS0#
DQS0
VSS
DQ2
DQ3
VSS
DQ8
DQ9
VSS
DQS1#
DQS1
VSS
DQ10
DQ11
VSS

VSS
DQ16
DQ17
VSS
DQS2#
DQS2
VSS
DQ18
DQ19
VSS
DQ24
DQ25
VSS
DM3
NC
VSS
DQ26
DQ27
VSS
CKE0
VDD
NC
BA2
VDD
A12
A9
A8
VDD
A5
A3
A1
VDD
A10/AP
BA0
WE#
VDD
CAS#
NC/S1#
VDD
NC/ODT1
VSS
DQ32
DQ33
VSS
DQS4#
DQS4
VSS
DQ34
DQ35
VSS
DQ40
DQ41
VSS
DM5
VSS
DQ42
DQ43
VSS
DQ48
DQ49
VSS
NC,TEST
VSS
DQS6#
DQS6
VSS
DQ50
DQ51
VSS
DQ56
DQ57
VSS
DM7
VSS
DQ58
DQ59
VSS
SDA
SCL
VDDSPD

FOX_AS0A426-M2SN-7F~D

DIMMB

STANDARD

VSS
DQ4
DQ5
VSS
DM0
VSS
DQ6
DQ7

VSS
DQ12
DQ13

VSS

DM1

VSS

CK0#

VSS
DQ14
DQ15

VSS

VSS
DQ20
DQ21

VSS

DM2

VSS
DQ22
DQ23

VSS
DQ28
DQ29

VSS

DQS3#

DQS3

VSS
DQ30
DQ31

VSS

NC/CKE1

VDD

NC/A15
NC/A14

VDD

VDD

VDD

RAS#

VDD
ODT0

NC/A13

VDD

VSS
DQ36
DQ37

VSS

DM4

VSS
DQ38
DQ39

VSS
DQ44
DQ45

VSS

DQS5#

DQS5

VSS
DQ46
DQ47

VSS
DQ52
DQ53

VSS

CK1#

VSS

DM6

VSS
DQ54
DQ55

VSS
DQ60
DQ61

VSS

DQS7#

DQS7

VSS
DQ62
DQ63

VSS

SAO

2

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30

CK0

32
34
36
38
40

42
44
46
48
50

NC

52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90

A11

92

A7

94

A6

96
98

A4

100

A2

102

A0

104
106

BA1

108
110

S0#

112
114
116
118
120

NC

122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164

CK1

166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200

SA1

Place DIMM-B on Bottom

(5.2mm)

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

2

V_DDR_MCH_REF

DDR_B_D3

DDR_B_D2DDR_B_D5
DDR_B_DM0
DDR_B_D7DDR_B_DQS0

DDR_B_D6
DDR_B_D12

DDR_B_D13
DDR_B_DM1
M_CLK_DDR3

M_CLK_DDR#3
DDR_B_D14

DDR_B_D15

DDR_B_D20
DDR_B_D21

DDR_B_DM2
DDR_B_D22

DDR_B_D23
DDR_B_D28

DDR_B_D29
DDR_B_DQS#3

DDR_B_DQS3
DDR_B_D30

DDR_B_D31
DDR_CKE3_DIMMB

DDR_B_MA11
DDR_B_MA7
DDR_B_MA6

DDR_B_MA4
DDR_B_MA2
DDR_B_MA0

DDR_B_BS1
DDR_B_RAS#
DDR_CS2_DIMMB#

M_ODT2
DDR_B_MA13

DDR_B_D36
DDR_B_D37

DDR_B_DM4
DDR_B_D38

DDR_B_D39
DDR_B_D44

DDR_B_D45
DDR_B_DQS#5

DDR_B_DQS5
DDR_B_D46

DDR_B_D47
DDR_B_D52

DDR_B_D53
M_CLK_DDR2

M_CLK_DDR#2
DDR_B_DM6
DDR_B_D54

DDR_B_D55
DDR_B_D60

DDR_B_D61
DDR_B_DQS#7

DDR_B_DQS7
DDR_B_D62

DDR_B_D63

1 2

R506
10K_0402_5%~D

1 2

1

2.2U_0603_6.3V6K~D

M_CLK_DDR3 <10>

M_CLK_DDR#3 <10>

PM_EXTTS#0_R <17>

DDR_CKE3_DIMMB <10>

DDR_B_BS1 <11>

DDR_B_RAS# <11>
DDR_CS2_DIMMB# <10>

M_ODT2 <10>

M_CLK_DDR2 <10>

M_CLK_DDR#2 <10>

+3.3V_RUN

R510

10K_0402_5%~D

C628

1

2

V_DDR_MCH_REF <10,17,41>

0.1U_0402_16V4Z~D
C622

1

2

DELL CONFIDENTIAL/PROPRIETARY

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

DDRII-SODIMM SLOT-B

LA-3001P

18 73Monday, April 17, 2006

1

of

0.4