Compal LA-2952P Caymus, Compaq nc6400 Schematic

A

1 1

2 2

B

C

D

E

Compal confidential

Schematics Document

Mobile Yonah uFCPGA with Intel
Calistoga_P/GM+ ICH7-M core logic

3 3

2005-10-26

REV:0.3

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2005/05/26 2006/07/26

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

D

Date: Sheet

Compal Electronics, Inc.

Cover Sheet

LA-2952P

E

0.3

of

146Wednesday, October 26, 2005

A

Compal confidential

File Name : LA-2952P

B

C

D

E

Caymus

1 1

CRT / TV-OUT

LCD CONN

2 2

daughter board

Mini-Card

10/100/1000 LAN

LED

3 3

page 29

RTC CKT.

page 19

BCM5753M

page 22/23

RJ45/11 CONN

page 23

WLAN

page 24

Slot 0/Smart Card

Fan Control

page 4

page 16

page 17

DVI
CH7307C

page 16

CardBus Controller

TI PCI6612

H_A#(3..31)

Intel Calistoga MCH

PCI-E BUS

PCI BUS

SD/MMC Slot

Mobile Yonah/Merom

uFCPGA-478 CPU

FSB

533/667MHz

945GM

PCBGA 1466

page 7,8,9,10,11,12

DMI

Intel ICH7-M

mBGA-652

page 18,19,20,21

SPI ROM
25LF080A

H_D#(0..63)

AC-LINK/Azalia

SPI

page 29

Thermal Sensor
ADM1032AR

page 4page 4,5,6

DDR2 -400/533/667

Dual Channel

USB2.0

SATA

PATA Slave

Clock Generator

ICS9LP306BGLFT

page 15

DDR2-SO-DIMM X2

BANK 0, 1, 2, 3

page 13,14

USB conn x2
(Docking)

page 32

FingerPrinter AES2501
USBx1

USB conn x3

BT Conn

page 29

page 27

page 27

Mini-Card WWAN

page 24

Audio CKT

AD1981HD

page 25

SATA HDD Connector

page 19

Multi-bay II Connector

page 19

LPC BUS

Power OK CKT.

page 34

Accelerometer

LIS3LV02DQ

page 24

daughter board

MDC

page 31

AMP & Audio Jack

MAX9710

Docking CONN.

*RJ-45(LED*2)
*RJ-11(Pass Through)
*CRT
*COMPOSITE Video Out
*TVOUT
*DVI
*LINE IN
*LINE OUT

page 26

*PCI-E x2
*Serial Port
*Parallel Port
*PS/2 x2
*USB x2

Power On/Off CKT.

page 31

TPM 1.2

page 29

SMSC KBC 1021

page 30

SMSC Super I/O

LPC47N217

page 34

*DC JACK

4 4

DC/DC Interface CKT.

page 33

Touch Pad CONN.

Int.KBD

page 37page 31

COM1 LPT
( Docking ) ( Docking )

page 32 page 32

page 34

Power Circuit DC/DC

Page 35,36,37,38,39,40,41,42,43

A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2005/05/26 2006/07/26

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

D

Date: Sheet

Compal Electronics, Inc.

Block Diagram

LA-2952P

E

0.3

of

246Wednesday, October 26, 2005

5

4

3

2

1

Voltage Rails

Power Plane

VIN

D D

C C

B+
+CPU_CORE
+VCCP
+0.9VS

+1.5VS
+1.8V

+2.5VS
+3VALW

+5VALW
+5VS
+RTC_VCC

Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.

Description

Adapter power supply (18.5V)
AC or battery power rail for power circuit
Core voltage for CPU

1.05V power rail for Processor I/O and MCH/ICH core power

0.9V switched power rail for DDRII Vtt

1.5V switched power rail for PCI-E interface

1.8V power rail for DDRII

3.3V always on power rail

3.3V switched power rail+3VS
5V always on power rail
5V switched power rail
RTC power ONON

S0-S1

S3

N/A

N/A

N/A
ON OFF
ON

OFF

OFF

ON

ON

OFF
ON

ON
ON+1.8VS OFF OFF1.8V switched power rail

ON OFF

ON

ON
ON OFF OFF

ON

ON
ON

OFF

ON

S5

N/A
N/AN/A
OFF
OFF
OFF

OFF
OFF

OFF2.5V switched power rail for MCH video PLL
ON*

ON*
OFF

Symbol Note :

: means Digital Ground

: means Analog Ground

@ : means just reserve , no build
M52@ : means build discrete sku with ATI VGA M52 .
UMA@ : means build UMA sku with Intel 945GM .

SPI@ : means just build when SPI I/F BIOS function reserve.
FWH@ : means just build when FWH I/F BIOS function reserve.
NOXDP@ : means just build when XDP function disable.
XDP@ : means just build when XDP function enable. When this time, docking PCI express will not work.

1021@ : means just build when SMsC KBC1021 chip selected.
LP@ : means just build when Low power clock gen. install
NOLP@ : means just build when Low power clock gen. NO install

45@ : means need be mounted when 45 level assy or rework stage.

Internal PCI Devices

DEVICE

LAN
Azalia D27

USB1.1/2.0
PCI to PCI (DMI to PCI)
AC97 MODEM
AC97 Audio
PATA/SATA
LPC I/F
SMBUS
CPU I/F

B B

Bus

1
0
0
0
0
0
0
0
0
0
0
0
0

PCI Device ID

D8

D28PCI-E
D29
D30
D30
D30
D31
D31
D31

D31 AD15DMA
D31 AD15PMU

IDSEL #

AD24
AD11
AD12
AD13
AD14
AD14
AD14
AD15
AD15
AD15
AD15D31

External PCI Devices

DEVICE

CARD BUS

PCI Device ID

D6

IDSEL #

AD22

REQ/GNT #

2

PIRQ

C D E G

I2C / SMBUS ADDRESSING

DEVICE

A A

DDR SO-DIMM 0
DDR SO-DIMM 1
CLOCK GENERATOR (EXT.)

5

HEX

A0
A4
D2

ADDRESS

1 0 1 0 0 0 0 0
1 0 1 0 0 1 0 0
1 1 0 1 0 0 1 0

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/05/26 2006/07/26

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

2

Date: Sheet

Compal Electronics, Inc.

Notes List

LA-2952P

346Wednesday, October 26, 2005

1

0.3

of

5

4

3

2

1

H_A#[3..31]<7>

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8

D D

H_REQ#[0..4]<7>

H_ADSTB#0<7>

R410

1 2

+VCCP

E

3 1

MMBT3904_SOT23@

H_ADSTB#1<7>

CLK_CPU_BCLK<15>

CLK_CPU_BCLK#<15>

H_ADS#<7>
H_BNR#<7>

H_BPRI#<7>

H_BR0#<7>

H_DEFER#<7>

H_DRDY#<7>

H_HIT#<7>

H_HITM#<7>

H_LOCK#<7>

H_RESET#<7>

H_RS#[0..2]<7>

H_TRDY#<7>

XDP_DBRESET#<20>

H_DBSY#<7>

H_DPSLP#<19>

H_DPRSTP#<19,42>

H_DPWR#<7>

H_PWRGOOD<19>

H_CPUSLP#<7>

12

H_THERMTRIP#<7,19>

12

R1255

56_0402_5%@

B

2

C

Q85

5

C C

R172

56_0402_5%

1 2

+VCCP

B B

H_PROCHOT#<42>

1 2

+VCCP

56_0402_5%

R1264 1K_0402_5%@
R1265 51_0402_5%

H_THERMDA, H_THERMDC routing together.
Trace width / Spacing = 10 / 10 mil

A A

H_PROCHOT# OCP#

H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

H_ADSTB#0
H_ADSTB#1

CLK_CPU_BCLK
CLK_CPU_BCLK#

H_ADS#
H_BNR#
H_BPRI#
H_BR0#
H_DEFER#
H_DRDY#
H_HIT#
H_HITM#
H_IERR#
H_LOCK#
H_RESET#

H_RS#0
H_RS#1
H_RS#2
H_TRDY#

XDP_BPM#0
XDP_BPM#1
XDP_BPM#2
XDP_BPM#3

XDP_DBRESET#

H_DBSY#
H_DPSLP#
H_DPRSTP#
H_DPWR#
XDP_BPM#4
XDP_BPM#5
H_PROCHOT#

H_PWRGOOD
H_CPUSLP#
XDP_TCK
XDP_TDI
XDP_TDO
TEST1
TEST2
XDP_TMS
XDP_TRST#

H_THERMDA
H_THERMDC
H_THERMTRIP#

OCP# <20,43>

JP12A

J4

A3#

L4

A4#

M3

A5#

K5

A6#

M1

A7#

N2

A8#

J1

A9#

N3

A10#

P5

A11#

P2

A12#

L1

A13#

P4

A14#

P1

A15#

R1

A16#

Y2

A17#

U5

A18#

R3

A19#

W6

A20#

U4

A21#

Y5

A22#

U2

A23#

R4

A24#

T5

ADDR GROUP

A25#

T3

A26#

W3

A27#

W5

A28#

Y4

A29#

W2

A30#

Y1

A31#

K3

REQ0#

H2

REQ1#

K2

REQ2#

J3

REQ3#

L5

REQ4#

L2

ADSTB0#

V4

ADSTB1#

A22

BCLK0

A21

H1

E2

G5

F1

H5

F21

G6

E4

D20

H4

B1

F3

F4
G3
G2

AD4
AD3
AD1
AC4

C20

E1

B5

E5

D24
AC2
AC1
D21

D6
D7

AC5
AA6
AB3
C26
D25
AB5
AB6

A24
A25

C7

HOST CLK

BCLK1

ADS#
BNR#
BPRI#
BR0#
DEFER#
DRDY#
HIT#

CONTROL

HITM#
IERR#
LOCK#
RESET#

RS0#
RS1#
RS2#
TRDY#

BPM0#
BPM1#
BPM2#
BPM3#

DBR#
DBSY#
DPSLP#
DPRSTP#
DPWR#
PRDY#
PREQ#
PROCHOT#

PWRGOOD
SLP#
TCK
TDI
TDO
TEST1
TEST2
TMS
TRST#

THERMAL

THERMDA

DIODE

THERMDC
THERMTRIP#

FOX_PZ47903-2741-42_YONAH

H_DPSLP#

1 2

H_DPRSTP#

1 2

YONAH

MISC

R1266

56_0402_5%@

R1267

56_0402_5%@

DATA GROUP

LEGACY CPU

4

D10#
D11#
D12#
D13#
D14#
D15#
D16#
D17#
D18#
D19#
D20#
D21#
D22#
D23#
D24#
D25#
D26#
D27#
D28#
D29#
D30#
D31#
D32#
D33#
D34#
D35#
D36#
D37#
D38#
D39#
D40#
D41#
D42#
D43#
D44#
D45#
D46#
D47#
D48#
D49#
D50#
D51#
D52#
D53#
D54#
D55#
D56#
D57#
D58#
D59#
D60#
D61#
D62#
D63#

DINV0#
DINV1#
DINV2#
DINV3#

DSTBN0#
DSTBN1#
DSTBN2#
DSTBN3#
DSTBP0#
DSTBP1#
DSTBP2#
DSTBP3#

A20M#
FERR#

IGNNE#

INIT#
LINT0
LINT1

STPCLK#

SMI#

H_D#0

E22

D0#

H_D#1

F24

D1#

H_D#2

E26

D2#

H_D#3

H22

D3#

H_D#4

F23

D4#

H_D#5

G25

D5#

H_D#6

E25

D6#

H_D#7

E23

D7#

H_D#8

K24

D8#

H_D#9

G24

D9#

H_D#10

J24

H_D#11

J23

H_D#12

H26

H_D#13

F26

H_D#14

K22

H_D#15

H25

H_D#16

N22

H_D#17

K25

H_D#18

P26

H_D#19

R23

H_D#20

L25

H_D#21

L22

H_D#22

L23

H_D#23

M23

H_D#24

P25

H_D#25

P22

H_D#26

P23

H_D#27

T24

H_D#28

R24

H_D#29

L26

H_D#30

T25

H_D#31

N24

H_D#32

AA23

H_D#33

AB24

H_D#34

V24

H_D#35

V26

H_D#36

W25

H_D#37

U23

H_D#38

U25

H_D#39

U22

H_D#40

AB25

H_D#41

W22

H_D#42

Y23

H_D#43

AA26

H_D#44

Y26

H_D#45

Y22

H_D#46

AC26

H_D#47

AA24

H_D#48

AC22

H_D#49

AC23

H_D#50

AB22

H_D#51

AA21

H_D#52

AB21

H_D#53

AC25

H_D#54

AD20

H_D#55

AE22

H_D#56

AF23

H_D#57

AD24

H_D#58

AE21

H_D#59

AD21

H_D#60

AE25

H_D#61

AF25

H_D#62

AF22

H_D#63

AF26

H_DINV#0

J26

H_DINV#1

M26

H_DINV#2

V23

H_DINV#3

AC20

H_DSTBN#0

H23

H_DSTBN#1

M24

H_DSTBN#2

W24

H_DSTBN#3

AD23

H_DSTBP#0

G22

H_DSTBP#1

N25

H_DSTBP#2

Y25

H_DSTBP#3

AE24

H_A20M#

A6

H_FERR#

A5

H_IGNNE#

C4

H_INIT#

B3

H_INTR

C6

H_NMI

B4

H_STPCLK#

D5

H_SMI#

A3

H_D#[0..63] <7>

ITP-XDP Connector

JP19

1

XDP_BPM#5
XDP_BPM#4

XDP_BPM#3
XDP_BPM#2

XDP_BPM#1
XDP_BPM#0

R1295

H_PWRGOOD_RH_PWRGOOD CLK_CPU_XDP

12

1K_0402_5%

+VCCP +VCCP

12

C948 0.1U_0402_16V4Z

ICH_SMBDATA
ICH_SMBCLK

XDP_TCK

GND0

3

OBSFN_A0

5

OBSFN_A1

7

GND2

9

OBSDATA_A0

11

OBSDATA_A1

13

GND4

15

OBSDATA_A2

17

OBSDATA_A3

19

GND6

21

OBSFN_B0

23

OBSFN_B1

25

GND8

27

OBSDATA_B0

29

OBSDATA_B1

31

GND10

33

OBSDATA_B2

35

OBSDATA_B3

37

GND12

39

PWRGOOD/HOOK0

41

HOOK1

43

VCC_OBS_AB

45

HOOK2

47

HOOK3

49

GND14

51

SDA

53

SCL

55

TCK1

57

TCK0

59

GND16

SAMTE_BSH-030-01-L-D-A

GND1
OBSFN_C0
OBSFN_C1

GND3

OBSDATA_C0
OBSDATA_C1

GND5

OBSDATA_C2
OBSDATA_C3

GND7
OBSFN_D0
OBSFN_D1

GND9

OBSDATA_D0
OBSDATA_D1

GND11
OBSDATA_D2
OBSDATA_D3

GND13

ITPCLK/HOOK4

ITPCLK#/HOOK5

VCC_OBS_CD

RESET#/HOOK6

DBR#/HOOK7

GND15

TRST#

TMS

GND17

TD0

TDI

Thermal Sensor ADM1032AR-2

+3VS

2

C273

H_DINV#0 <7>
H_DINV#1 <7>
H_DINV#2 <7>
H_DINV#3 <7>

H_DSTBN#[0..3] <7>

H_DSTBP#[0..3] <7>

1 2

2200P_0402_50V7K

+3VS

0.1U_0402_16V4Z

C264

R228

1 2

10K_0402_5%

1

H_THERMDA
H_THERMDC

THERM#

1
2
3

PWM Fan Control circuit

H_A20M# <19>
H_FERR# <19>
H_IGNNE# <19>
H_INIT# <19>
H_INTR <19>
H_NMI <19>

H_STPCLK# <19>
H_SMI# <19>

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/05/26 2006/07/26

FAN_PWM<30>

Compal Secret Data

Deciphered Date

THERM#

+3VS

1

INB

2

INA

5

U24

P

O

G

TC7SH00FU_SSOP5

3

2

CH751H-40_SC76

4

D11

G

3

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

CLK_CPU_XDP#

42
44
46
48
50

XDP_TDO

52

XDP_TRST#

54

XDP_TDI

56

XDP_TMS

58

XDP_PRE

60

U16

VDD

SCLK

D+

SDATA

ALERT#

D­THERM#4GND

ADM1032AR-2_MSOP8

Address:1001_101

ICH_SMBCLK<13,14,15,20,22,24>

ICH_SMBDATA<13,14,15,20,22,24>

+5VS

2 1

6

2

1

D

Q33
AO6402_TSOP6

S

4 5

Title

Size Document Number Rev

Date: Sheet

XDP_DBRESET#_R

XDP_TDI
XDP_TMS

XDP_TDO
XDP_BPM#5
XDP_TRST#
XDP_TCK

1K_0402_1%

1 2

200_0402_1%

R1296 0_0402_5%

1 2

ICH_SMBCLK

8

ICH_SMBDATA

7

THERM_SCI#

6
5

ICH_SMBCLK
ICH_SMBDATA

1

C122

4.7U_0805_10V4Z

2

R1294

1 2

This shall place near CPU

R246 56_0402_5%

1 2

R236 56_0402_1%

1 2

R238 56_0402_5%

1 2

R241 56_0402_5%

1 2

R237 56_0402_5%

1 2

R239 56_0402_5%

1 2

H_RESET#H_RESET#_R

R242

XDP_DBRESET#XDP_DBRESET#_R

R243

12

12

R227
10K_0402_5%

1

C125

0.1U_0402_16V4Z

2

FAN

12

ZD1

@

RLZ5.1B_LL34

Compal Electronics, Inc.

Yonah CPU in mFCPGA479

LA-2952P

1

+3VS

1K_0402_5%@

+VCCP

CLK_CPU_XDP <15>
CLK_CPU_XDP# <15>

THERM_SCI# <20>

ACES_85205-0200

446Wednesday, October 26, 2005

JP8

1
2

0.3

of

5

4

3

2

1

V_CPU_GTLREF

+VCCP

12

R1268
1K_0402_1%

12

R1271
2K_0402_1%

+VCC_CORE

R1269
100_0402_1%

1 2

R1270
100_0402_1%

1 2

VCCSENSE

VSSSENSE

Close to CPU pin
within 500mils.

CPU_BSEL CPU_BSEL2 CPU_BSEL1

133

166

00

0

12

12

R245

54.9_0402_1%

R355

R244

27.4_0402_1%

D D

Close to CPU pin AD26
within 500mils.

C C

B B

Length match within 25 mils
The trace width 18 mils space
7 mils

+1.5VS

1

C520

2

0.01U_0402_16V7K

CPU_BSEL0

1

1

12

R1220

27.4_0402_1%

12

54.9_0402_1%

1

Resistor placed within

0.5" of CPU pin.Trace
should be at least 25
mils away from any
other toggling signal.

C531

10U_0805_10V4Z

1

2

CPU_VID0<42>
CPU_VID1<42>
CPU_VID2<42>
CPU_VID3<42>
CPU_VID4<42>
CPU_VID5<42>
CPU_VID6<42>

V_CPU_GTLREF

CPU_BSEL0<15>
CPU_BSEL1<15>
CPU_BSEL2<15>

VCCSENSE<42>
VSSSENSE<42>

H_PSI#<42>

+VCCP

+VCC_CORE

VCCSENSE
VSSSENSE

H_PSI#
CPU_VID0

CPU_VID1
CPU_VID2
CPU_VID3
CPU_VID4
CPU_VID5
CPU_VID6

CPU_BSEL0
CPU_BSEL1
CPU_BSEL2

COMP0
COMP1
COMP2
COMP3

JP12B

AF7

VCCSENSE

AE7

VSSSENSE

B26

VCCA

K6

VCCP

J6

VCCP

M6

VCCP

N6

VCCP

YONAH

VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP

PSI#
VID0

VID1
VID2
VID3
VID4
VID5
VID6

GTLREF
BSEL0

BSEL1
BSEL2

COMP0
COMP1
COMP2
COMP3

VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC

RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD

FOX_PZ47903-2741-42_YONAH

W21

AD26

AB20
AA20
AF20
AE20
AB18
AB17
AA18
AA17
AD18
AD17
AC18
AC17
AF18
AF17

T6

R6

K21

J21
M21
N21
T21
R21
V21

V6

G21

AE6
AD6

AF5
AE5
AF4
AE3
AF2
AE2

B22
B23
C21

R26
U26

U1

V1

E7

D2

F6
D3
C1

AF1
D22
C23
C24
AA1
AA4
AB2
AA3

M4
N5

T2

V3

B2
C3

T22
B25

AB26

VSS

AA25

VSS

AD25

VSS

AE26

VSS

AB23

VSS

AC24

VSS

AF24

VSS

AE23

VSS

AA22

VSS

AD22

VSS

AC21

VSS

AF21

VSS

AB19

VSS

AA19

VSS

AD19

VSS

AC19

VSS

AF19

VSS

AE19

VSS

AB16

VSS

AA16

VSS

AD16

VSS

AC16

VSS

AF16

VSS

AE16

VSS

AB13

VSS

AA14

VSS

AD13

VSS

AC14

VSS

AF13

VSS

AE14

VSS

AB11

VSS

AA11

VSS

AD11

VSS

AC11

VSS

AF11

VSS

AE11

VSS

AB8

VSS

AA8

VSS

AD8

VSS

AC8

VSS

AF8

VSS

AE8

VSS

AA5

VSS

AD5

VSS

AC6

VSS

AF6

VSS

AB4

VSS

AC3

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

AF3
AE4
AB1
AA2
AD2
AE1
B6
C5
F5
E6
H6
J5
M5
L6
P6
R5
V5
U6
Y6
A4
D4
E3
H3
G4
K4
L3
P3
N4
T4
U3
Y3
W4
D1
C2
F2
G1

POWER, GROUNG, RESERVED SIGNALS AND NC

+VCC_CORE

JP12C

AE18

VCC

AE17

VCC

AB15

VCC

AA15

VCC

AD15

VCC

AC15

VCC

AF15

VCC

AE15

VCC

AB14

VCC

AA13

VCC

AD14

VCC

AC13

VCC

AF14

VCC

AE13

VCC

AB12

VCC

AA12

VCC

AD12

VCC

AC12

VCC

AF12

VCC

AE12

VCC

AB10

VCC

AB9

VCC

AA10

VCC

AA9

VCC

AD10

VCC

AD9

VCC

AC10

VCC

AC9

VCC

AF10

VCC

AF9

VCC

AE10

POWER, GROUND

VCC

AE9

VCC

AB7

VCC

AA7

VCC

AD7

VCC

AC7

VCC

B20

VCC

A20

VCC

F20

VCC

E20

VCC

B18

VCC

B17

VCC

A18

VCC

A17

VCC

D18

VCC

D17

VCC

C18

VCC

C17

VCC

F18

VCC

F17

VCC

E18

VCC

E17

VCC

B15

VCC

A15

VCC

D15

VCC

C15

VCC

F15

VCC

E15

VCC

B14

VCC

A13

VCC

D14

VCC

C13

VCC

F14

VCC

E13

VCC

B12

VCC

A12

VCC

D12

VCC

C12

VCC

F12

VCC

E12

VCC

B10

VCC

B9

VCC

A10

VCC

A9

VCC

D10

VCC

D9

VCC

C10

VCC

C9

VCC

F10

VCC

F9

VCC

E10

VCC

E9

VCC

B7

VCC

A7

VCC

F7

VCC

FOX_PZ47903-2741-42_YONAH

YONAH

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

K1
J2
M2
N1
T1
R2
V2
W1
A26
D26
C25
F25
B24
A23
D23
E24
B21
C22
F22
E21
B19
A19
D19
C19
F19
E19
B16
A16
D16
C16
F16
E16
B13
A14
D13
C14
F13
E14
B11
A11
D11
C11
F11
E11
B8
A8
D8
C8
F8
E8
G26
K26
J25
M25
N26
T26
R25
V25
W26
H24
G23
K23
L24
P24
N23
T23
U24
Y24
W23
H21
J22
M22
L21
P21
R22
V22
U21
Y21

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/05/26 2006/07/26

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

2

Date: Sheet

Compal Electronics, Inc.

Yonah CPU in mFCPGA479

LA-2952P

1

of

546Wednesday, October 26, 2005

0.3

5

4

3

2

1

D D

Place these capacitors on L8
(North side,Secondary Layer)

Place these capacitors on L8
(North side,Secondary Layer)

Place these capacitors on L8
(Sorth side,Secondary Layer)

C C

Place these capacitors on L8
(Sorth side,Secondary Layer)

+VCC_CORE

1

2

+VCC_CORE

1

2

+VCC_CORE

1

2

+VCC_CORE

1

2

C899
10U_0805_6.3V6M

C907
10U_0805_6.3V6M

C915
10U_0805_6.3V6M

C923
10U_0805_6.3V6M

1

C900
10U_0805_6.3V6M

2

1

C908
10U_0805_6.3V6M

2

1

C916
10U_0805_6.3V6M

2

1

C924
10U_0805_6.3V6M

2

1

C901
10U_0805_6.3V6M

2

1

C909
10U_0805_6.3V6M

2

1

C917
10U_0805_6.3V6M

2

1

C925
10U_0805_6.3V6M

2

1

C902
10U_0805_6.3V6M

2

1

C910
10U_0805_6.3V6M

2

1

C918
10U_0805_6.3V6M

2

1

C926
10U_0805_6.3V6M

2

1

C903
10U_0805_6.3V6M

2

1

C911
10U_0805_6.3V6M

2

1

C919
10U_0805_6.3V6M

2

1

C927
10U_0805_6.3V6M

2

1

C904
10U_0805_6.3V6M

2

1

C912
10U_0805_6.3V6M

2

1

C920
10U_0805_6.3V6M

2

1

C928
10U_0805_6.3V6M

2

1

C905
10U_0805_6.3V6M

2

1

C913
10U_0805_6.3V6M

2

1

C921
10U_0805_6.3V6M

2

1

C929
10U_0805_6.3V6M

2

1

C906
10U_0805_6.3V6M

2

1

C914
10U_0805_6.3V6M

2

1

C922
10U_0805_6.3V6M

2

1

C930
10U_0805_6.3V6M

2

Mid Frequence Decoupling

+VCC_CORE

330U_D2E_2.5VM_R9

1

+

C931

330U_D2E_2.5VM_R9

B B

@

C932

2

330U_D2E_2.5VM_R9@

1

1

+

+

C935

C933

2

2

330U_D2E_2.5VM_R9

1

+

2

330U_D2E_2.5VM_R9

1

+

C937

C936

2

330U_D2E_2.5VM_R9

820U_E9_2_5V_M_R745@

1

1

+

C934

2

1

+

+

C938

2

820U_E9_2_5V_M_R7

2

@

ESR <= 1.5m ohm
Capacitor > 1980uF

+VCCP

1

+

C983

330U_D2E_2.5VM_R9

A A

2

5

1

C940

0.1U_0402_10V6K

2

1

C941

0.1U_0402_10V6K

2

1

2

4

C942

0.1U_0402_10V6K

1

C943

0.1U_0402_10V6K

2

1

C944

0.1U_0402_10V6K

2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

1

C945

0.1U_0402_10V6K

2

3

2005/05/26 2006/07/26

Compal Secret Data

Deciphered Date

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

CPU Bypass capacitors

LA-2952P

646Wednesday, October 26, 2005

1

of

0.3

5

4

3

2

1

H_D#[0..63]<4>

D D

C C

L

H_XSCOMP/H_YSCOMP trace
width and spacing is 5/20.

B B

A A

12

R1196

54.9_0402_1%

+VCCP

12

R1197

54.9_0402_1%

R1199

24.9_0402_1%

+VCCP

12

R1208

12

R1212

12

100_0402_1%

200_0402_1%

H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63

H_VREF
H_XRCOMP
H_XSCOMP
H_YRCOMP
H_YSCOMP
H_SWNG0
H_SWNG1

12

R1200

24.9_0402_1%

Layout Note:
H_XRCOMP / H_YRCOMP / H_VREF / H_SWNG0 /
H_SWNG1 trace width and spacing is 18/20.

H_VREF

1

C898

2

0.1U_0402_16V4Z

5

K11
T10

W11

U11
T11

AB7
AA9

Y10
AB8

AA4
AA7
AA2
AA6

AA10

AA1
AB4

AC9
AB11
AC11

AB3

AC2

AD1

AD9

AC1

AD7

AC6

AB5
AD10

AD4

AC8

J13

K13

U15A

F1

HD0#

J1

HD1#

H1

HD2#

J6

HD3#

H3

HD4#

K2

HD5#

G1

HD6#

G2

HD7#

K9

HD8#

K1

HD9#

K7

HD10#

J8

HD11#

H4

HD12#

J3

HD13#
HD14#

G4

HD15#
HD16#
HD17#

T3

HD18#

U7

HD19#

U9

HD20#
HD21#
HD22#

W9

HD23#

T1

HD24#

T8

HD25#

T4

HD26#

W7

HD27#

U5

HD28#

T9

HD29#

W6

HD30#

T5

HD31#
HD32#
HD33#

W4

HD34#

W3

HD35#

Y3

HD36#

Y7

HD37#

W5

HD38#
HD39#
HD40#

W2

HD41#
HD42#
HD43#
HD44#
HD45#
HD46#

Y8

HD47#
HD48#
HD49#
HD50#
HD51#
HD52#
HD53#
HD54#
HD55#
HD56#
HD57#
HD58#
HD59#
HD60#
HD61#
HD62#
HD63#

HVREF0
HVREF1

E1

HXRCOMP

E2

HXSCOMP

Y1

HYRCOMP

U1

HYSCOMP

E4

HXSWING

W1

HYSWING

CALISTOGA_FCBGA1466~D

H9

HA3#

C9

HA4#

E11

HA5#

G11

HA6#

F11

HA7#

G12

HA8#

F9

HA9#

H11

HA10#

J12

HA11#

G14

HA12#

D9

HA13#

J14

HA14#

H13

HA15#

J15

HA16#

F14

HA17#

D12

HA18#

A11

HA19#

C11

HA20#

A12

HA21#

A13

HA22#

E13

HA23#

G13

HA24#

F12

HA25#

B12

HA26#

B14

HA27#

C12

HA28#

A14

HA29#

C14

HA30#

D14

HA31#

D8

HREQ#0

G8

HREQ#1

B8

HREQ#2

F8

HREQ#3

A8

HREQ#4

B9

HADSTB#0

C13

HADSTB#1

HCLKN
HCLKP

HDSTBN#0
HDSTBN#1
HDSTBN#2
HDSTBN#3
HDSTBP#0
HDSTBP#1
HDSTBP#2
HDSTBP#3

HDINV#0
HDINV#1
HDINV#2
HDINV#3

HCPURST#

HADS#

HTRDY#

HDPWR#

HDRDY#

HDEFER#

HHITM#

HHIT#

HLOCK#

HBREQ0#

HBNR#

HBPRI#

HDBSY#

HCPUSLP#

HRS0#
HRS1#
HRS2#

12

R1206

12

R1210

AG1
AG2

K4
T7
Y5
AC4
K3
T6
AA5
AC5

J7
W8
U3
AB10

B7
E8
E7
J9
H8
C3
D4
D3
B3
C7
C6
F6
A7
E3

B4
E6
D6

221_0603_1%

100_0402_1%

HOST

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

H_ADSTB#0
H_ADSTB#1

CLK_MCH_BCLK#
CLK_MCH_BCLK

H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3
H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3

H_DINV#0
H_DINV#1
H_DINV#2
H_DINV#3

H_RESET#
H_ADS#
H_TRDY#
H_DPWR#
H_DRDY#
H_DEFER#
H_HITM#
H_HIT#
H_LOCK#
H_BR0#
H_BNR#
H_BPRI#
H_DBSY#
H_CPUSLP#

H_RS#0
H_RS#1
H_RS#2

H_SWNG0

1

C896

2

0.1U_0402_16V4Z

4

+VCCP+VCCP

12

R1207

12

R1211

H_A#[3..31] <4>

H_REQ#[0..4] <4>

H_ADSTB#0 <4>
H_ADSTB#1 <4>

CLK_MCH_BCLK# <15>
CLK_MCH_BCLK <15>
H_DSTBN#[0..3] <4>

H_DSTBP#[0..3] <4>

H_DINV#0 <4>
H_DINV#1 <4>
H_DINV#2 <4>
H_DINV#3 <4>

H_RESET# <4>
H_ADS# <4>
H_TRDY# <4>
H_DPWR# <4>
H_DRDY# <4>
H_DEFER# <4>
H_HITM# <4>
H_HIT# <4>
H_LOCK# <4>
H_BR0# <4>
H_BNR# <4>
H_BPRI# <4>
H_DBSY# <4>
H_CPUSLP# <4>

H_RS#[0..2] <4>

221_0603_1%

H_SWNG1

1

C897

2

100_0402_1%

0.1U_0402_16V4Z

U15B

AE35

DMIRXN0

AF39

DMIRXN1

AG35

DMIRXN2

AH39

DMIRXN3

AC35

DMIRXP0

AE39

DMIRXP1

AF35

DMIRXP2

AG39

DMIRXP3

AE37

DMITXN0

AF41

DMITXN1

AG37

DMITXN2

AH41

DMITXN3

AC37

DMITXP0

AE41

DMITXP1

AF37

DMITXP2

AG41

DMITXP3

AY35

SM_CK0

AR1

SM_CK1

AW7

SM_CK2

AW40

SM_CK3

AW35

SM_CK0#

AT1

SM_CK1#

AY7

SM_CK2#

AY40

SM_CK3#

AU20

SM_CKE0

AT20

SM_CKE1

BA29

SM_CKE2

AY29

SM_CKE3

AW13

SM_CS0#

AW12

SM_CS1#

AY21

SM_CS2#

AW21

SM_CS3#

AL20

SM_OCDCOMP0

AF10

SM_OCDCOMP1

BA13

SM_ODT0

BA12

SM_ODT1

AY20

SM_ODT2

AU21

SM_ODT3

AV9

SM_RCOMPN

AT9

SM_RCOMPP

AK1

SM_VREF0

AK41

SM_VREF1

G28

PM_BMBUSY#

F25

PM_EXTTS0#

H26

PM_EXTTS1#

G6

PM_THERMTRIP#

AH33

PWROK

AH34

RSTIN#

K28

ICH_SYNC#

CALISTOGA_FCBGA1466~D

Layout Note:
Route as short
as possible

12

R1202

R1203

40.2_0402_1%

40.2_0402_1%

@

@

12

DMI

DDR MUXING

M_OCDOCMP0
M_OCDOCMP1

+1.8V

12

12

R1201

100_0402_1%@

12

R1204

100_0402_1%@

DMI_TXN0
DMI_TXN1
DMI_TXN2
DMI_TXN3

DMI_TXP0
DMI_TXP1
DMI_TXP2
DMI_TXP3

DMI_RXN0
DMI_RXN1
DMI_RXN2
DMI_RXN3

DMI_RXP0
DMI_RXP1
DMI_RXP2
DMI_RXP3

M_CLK_DDR0
M_CLK_DDR1
M_CLK_DDR2
M_CLK_DDR3

M_CLK_DDR#0
M_CLK_DDR#1
M_CLK_DDR#2
M_CLK_DDR#3

DDR_CKE0_DIMMA
DDR_CKE1_DIMMA
DDR_CKE2_DIMMB
DDR_CKE3_DIMMB

DDR_CS0_DIMMA#
DDR_CS1_DIMMA#
DDR_CS2_DIMMB#
DDR_CS3_DIMMB#

M_OCDOCMP0
M_OCDOCMP1

M_ODT0
M_ODT1
M_ODT2
M_ODT3

SMRCOMPN
SMRCOMPP

PM_BMBUSY#
DDR_THERM#
PM_EXTTS#1
H_THERMTRIP#
PWROK
PLTRST_R#

PWROK

DMI_TXN0<20>
DMI_TXN1<20>
DMI_TXN2<20>
DMI_TXN3<20>

DMI_TXP0<20>
DMI_TXP1<20>
DMI_TXP2<20>
DMI_TXP3<20>

DMI_RXN0<20>
DMI_RXN1<20>
DMI_RXN2<20>
DMI_RXN3<20>

DMI_RXP0<20>
DMI_RXP1<20>
DMI_RXP2<20>
DMI_RXP3<20>

M_CLK_DDR0<13>
M_CLK_DDR1<13>
M_CLK_DDR2<14>
M_CLK_DDR3<14>

M_CLK_DDR#0<13>
M_CLK_DDR#1<13>
M_CLK_DDR#2<14>
M_CLK_DDR#3<14>

DDR_CKE0_DIMMA<13>
DDR_CKE1_DIMMA<13>
DDR_CKE2_DIMMB<14>
DDR_CKE3_DIMMB<14>

DDR_CS0_DIMMA#<13>
DDR_CS1_DIMMA#<13>
DDR_CS2_DIMMB#<14>
DDR_CS3_DIMMB#<14>

+1.8V

R1194 80.6_0402_1%
R1195 80.6_0402_1%

PM_BMBUSY#<20>

DDR_THERM#<13,14>

DPRSLPVR<20,42>

VGATE_INTEL<20,34,42>

PM_POK<20,30>

V_DDR_MCH_REF<13,14,41>

R1309 0_0402_5%

PLT_RST#<16,18,19,20,22,24,30>

R1304 0_0402_5%@
R1305 0_0402_5%

M_ODT0<13>
M_ODT1<13>
M_ODT2<14>
M_ODT3<14>

1 2
1 2

V_DDR_MCH_REF

1 2

H_THERMTRIP#<4,19>

R1198 100_0402_1%

MCH_ICH_SYNC#<18>

1 2
1 2

Layout Note:
V_DDR_MCH_REF
trace width and
spacing is 20/20.

V_DDR_MCH_REF

1

C895

2

0.1U_0402_16V4Z

Stuff R1202 & R1203 for A1 Calistoga

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/05/26 2006/07/26

Compal Secret Data

Deciphered Date

2

CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8

CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG16

CFG

CFG17
CFG18
CFG19
CFG20

G_CLKP
G_CLKN

D_REF_CLKN
D_REF_CLKP

CLKNC

D_REF_SSCLKN
D_REF_SSCLKP

CLK_REQ#

NC0
NC1
NC2
NC3
NC4
NC5
NC6
NC7
NC8

NC9
NC10
NC11
NC12
NC13
NC14
NC15
NC16
NC17
NC18

RESERVED1
RESERVED2

PM

RESERVED3
RESERVED4
RESERVED5
RESERVED6
RESERVED7
RESERVED8

RESERVED9
RESERVED10
RESERVED11
RESERVED12
RESERVED13

RESERVED

DDR_THERM#

PM_EXTTS#1

Title

Size Document Number Rev

Date: Sheet

Description at page11.

MCH_CLKSEL0

K16

MCH_CLKSEL1

K18

MCH_CLKSEL2

J18

CFG3

F18

CFG4

E15

CFG5

F15

CFG6

E18

CFG7

D19

CFG8

D16

CFG9

G16

CFG10

E16

CFG11

D15

CFG12

G15

CFG13

K15

CFG14

C15

CFG15

H16

CFG16

G18

CFG17

H15

CFG18

J25

CFG19

K27

CFG20

J26

CLK_MCH_3GPLL

AG33

CLK_MCH_3GPLL#

AF33

CLK_MCH_REF#

A27

CLK_MCH_REF

A26

CLK_MCH_SS#

C40

CLK_MCH_SS

D41

GMCH_H32

H32

A3
A39
A4
A40
AW1
AW41
AY1
BA1
BA2
BA3
BA39
BA40
BA41
C1
AY41
B2
B41
C41
D1

T32
R32
F3
F7
AG11
AF11
H7
J19
A41
A34
D28
D27
A35

R1205

10K_0402_5%

R1209

10K_0402_5%@

1 2

R1344
0_0402_5%

PAD
PAD

PAD
PAD
PAD

PAD
PAD

PAD

12

12

CLKREQC#GMCH_H32

MCH_CLKSEL0 <15>
MCH_CLKSEL1 <15>

MCH_CLKSEL2 <15>

T72
T73

CFG5 <11>

T74

CFG7 <11>

T75

CFG9 <11>

T76

CFG11 <11>

CFG12 <11>

CFG13 <11>

T77
T78

CFG16 <11>

T79

CFG18 <11>

CFG19 <11>

CFG20 <11>

CLK_MCH_3GPLL <15>

CLK_MCH_3GPLL# <15>

CLK_MCH_REF# <15>

CLK_MCH_REF <15>

CLK_MCH_SS# <15>

CLK_MCH_SS <15>

+3VS

CLKREQC# <15>

Compal Electronics, Inc.

Calistoga (1/6)

LA-2952P

746Wednesday, October 26, 2005

1

0.3

of

5

D D

4

3

2

1

DDR_A_BS#0<13>
DDR_A_BS#1<13>
DDR_A_BS#2<13>

DDR_A_DM[0..7]<13>

DDR_A_DQS[0..7]<13>

C C

DDR_A_DQS#[0..7]<13>

DDR_A_MA[0..13]<13>

B B

DDR_A_CAS#<13>
DDR_A_RAS#<13>

DDR_A_WE#<13>

T68 PAD
T70 PAD

DDR_A_BS#0
DDR_A_BS#1
DDR_A_BS#2

DDR_A_DM0
DDR_A_DM1
DDR_A_DM2
DDR_A_DM3
DDR_A_DM4
DDR_A_DM5
DDR_A_DM6
DDR_A_DM7

DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7

DDR_A_DQS#0
DDR_A_DQS#1
DDR_A_DQS#2
DDR_A_DQS#3
DDR_A_DQS#4
DDR_A_DQS#5
DDR_A_DQS#6
DDR_A_DQS#7

DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5

DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11 DDR_B_MA11
DDR_A_MA12
DDR_A_MA13

DDR_A_CAS#
DDR_A_RAS#
DDR_A_WE#
SA_RCVENIN#
SA_RCVENOUT#

U15D

AU12

SA_BS0

AV14

SA_BS1

BA20

SA_BS2

AJ33

SA_DM0

AM35

SA_DM1

AL26

SA_DM2

AN22

SA_DM3

AM14

SA_DM4

AL9

SA_DM5

AR3

SA_DM6

AH4

SA_DM7

AK33

SA_DQS0

AT33

SA_DQS1

AN28

SA_DQS2

AM22

SA_DQS3

AN12

SA_DQS4

AN8

SA_DQS5

AP3

SA_DQS6

AG5

SA_DQS7

AK32

SA_DQS0#

AU33

SA_DQS1#

AN27

SA_DQS2#

AM21

SA_DQS3#

AM12

SA_DQS4#

AL8

SA_DQS5#

AN3

SA_DQS6#

AH5

SA_DQS7#

AY16

SA_MA0

AU14

SA_MA1

AW16

SA_MA2

BA16

SA_MA3

BA17

SA_MA4

AU16

SA_MA5

AV17

SA_MA6

AU17

SA_MA7

AW17

SA_MA8

AT16

SA_MA9

AU13

SA_MA10

AT17

SA_MA11

AV20

SA_MA12

AV12

SA_MA13

AY13

SA_CAS#

AW14

SA_RAS#

AY14

SA_WE#

AK23

SA_RCVENIN#

AK24

SA_RCVENOUT#

CALISTOGA_FCBGA1466~D

SA_DQ0
SA_DQ1
SA_DQ2
SA_DQ3
SA_DQ4
SA_DQ5
SA_DQ6
SA_DQ7
SA_DQ8

SA_DQ9
SA_DQ10
SA_DQ11
SA_DQ12
SA_DQ13
SA_DQ14
SA_DQ15
SA_DQ16
SA_DQ17
SA_DQ18
SA_DQ19
SA_DQ20
SA_DQ21
SA_DQ22
SA_DQ23
SA_DQ24
SA_DQ25
SA_DQ26
SA_DQ27
SA_DQ28
SA_DQ29
SA_DQ30
SA_DQ31
SA_DQ32
SA_DQ33
SA_DQ34
SA_DQ35
SA_DQ36
SA_DQ37
SA_DQ38
SA_DQ39

DDR SYS MEMORY A

SA_DQ40
SA_DQ41
SA_DQ42
SA_DQ43
SA_DQ44
SA_DQ45
SA_DQ46
SA_DQ47
SA_DQ48
SA_DQ49
SA_DQ50
SA_DQ51
SA_DQ52
SA_DQ53
SA_DQ54
SA_DQ55
SA_DQ56
SA_DQ57
SA_DQ58
SA_DQ59
SA_DQ60
SA_DQ61
SA_DQ62
SA_DQ63

AJ35
AJ34
AM31
AM33
AJ36
AK35
AJ32
AH31
AN35
AP33
AR31
AP31
AN38
AM36
AM34
AN33
AK26
AL27
AM26
AN24
AK28
AL28
AM24
AP26
AP23
AL22
AP21
AN20
AL23
AP24
AP20
AT21
AR12
AR14
AP13
AP12
AT13
AT12
AL14
AL12
AK9
AN7
AK8
AK7
AP9
AN9
AT5
AL5
AY2
AW2
AP1
AN2
AV2
AT3
AN1
AL2
AG7
AF9
AG4
AF6
AG9
AH6
AF4
AF8

DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63

DDR_A_D[0..63] <13> DDR_B_D[0..63] <14>

DDR_B_BS#0<14>
DDR_B_BS#1<14>
DDR_B_BS#2<14>

DDR_B_DM[0..7]<14>

DDR_B_DQS[0..7]<14>

DDR_B_DQS#[0..7]<14>

DDR_B_MA[0..13]<14>

DDR_B_CAS#<14>

DDR_B_RAS#<14>

DDR_B_WE#<14>

T69 PAD
T71 PAD

DDR_B_BS#0
DDR_B_BS#1
DDR_B_BS#2

DDR_B_DM0
DDR_B_DM1
DDR_B_DM2
DDR_B_DM3
DDR_B_DM4
DDR_B_DM5
DDR_B_DM6
DDR_B_DM7

DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4
DDR_B_DQS5
DDR_B_DQS6
DDR_B_DQS7

DDR_B_DQS#0
DDR_B_DQS#1
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS#4
DDR_B_DQS#5
DDR_B_DQS#6
DDR_B_DQS#7

DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6DDR_A_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10

DDR_B_MA12
DDR_B_MA13

DDR_B_CAS#
DDR_B_RAS#
DDR_B_WE#
SB_RCVENIN#
SB_RCVENOUT#

U15E

AT24

SB_BS0

AV23

SB_BS1

AY28

SB_BS2

AK36

SB_DM0

AR38

SB_DM1

AT36

SB_DM2

BA31

SB_DM3

AL17

SB_DM4

AH8

SB_DM5

BA5

SB_DM6

AN4

SB_DM7

AM39

SB_DQS0

AT39

SB_DQS1

AU35

SB_DQS2

AR29

SB_DQS3

AR16

SB_DQS4

AR10

SB_DQS5

AR7

SB_DQS6

AN5

SB_DQS7

AM40

SB_DQS0#

AU39

SB_DQS1#

AT35

SB_DQS2#

AP29

SB_DQS3#

AP16

SB_DQS4#

AT10

SB_DQS5#

AT7

SB_DQS6#

AP5

SB_DQS7#

AY23

SB_MA0

AW24

SB_MA1

AY24

SB_MA2

AR28

SB_MA3

AT27

SB_MA4

AT28

SB_MA5

AU27

SB_MA6

AV28

SB_MA7

AV27

SB_MA8

AW27

SB_MA9

AV24

SB_MA10

BA27

SB_MA11

AY27

SB_MA12

AR23

SB_MA13

AR24

SB_CAS#

AU23

SB_RAS#

AR27

SB_WE#

AK16

SB_RCVENIN#

AK18

SB_RCVENOUT#

CALISTOGA_FCBGA1466~D

SB_DQ0
SB_DQ1
SB_DQ2
SB_DQ3
SB_DQ4
SB_DQ5
SB_DQ6
SB_DQ7
SB_DQ8

SB_DQ9
SB_DQ10
SB_DQ11
SB_DQ12
SB_DQ13
SB_DQ14
SB_DQ15
SB_DQ16
SB_DQ17
SB_DQ18
SB_DQ19
SB_DQ20
SB_DQ21
SB_DQ22
SB_DQ23
SB_DQ24
SB_DQ25
SB_DQ26
SB_DQ27
SB_DQ28
SB_DQ29
SB_DQ30
SB_DQ31
SB_DQ32
SB_DQ33
SB_DQ34
SB_DQ35
SB_DQ36
SB_DQ37
SB_DQ38
SB_DQ39

DDR SYS MEMORY B

SB_DQ40
SB_DQ41
SB_DQ42
SB_DQ43
SB_DQ44
SB_DQ45
SB_DQ46
SB_DQ47
SB_DQ48
SB_DQ49
SB_DQ50
SB_DQ51
SB_DQ52
SB_DQ53
SB_DQ54
SB_DQ55
SB_DQ56
SB_DQ57
SB_DQ58
SB_DQ59
SB_DQ60
SB_DQ61
SB_DQ62
SB_DQ63

AJ37
AP39
AR41
AJ38
AK38
AN41
AP41
AT40
AV41
AU38
AV38
AP38
AR40
AW38
AY38
BA38
AV36
AR36
AP36
BA36
AU36
AP35
AP34
AY33
BA33
AT31
AU29
AU31
AW31
AV29
AW29
AM19
AL19
AP14
AN14
AN17
AM16
AP15
AL15
AJ11
AH10
AJ9
AN10
AK13
AH11
AK10
AJ8
BA10
AW10
BA4
AW4
AY10
AY9
AW5
AY5
AV4
AR5
AK4
AK3
AT4
AK5
AJ5
AJ3

DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63

DDR_B_D0

AK39

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/05/26 2006/07/26

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

2

Date: Sheet

Compal Electronics, Inc.

Calistoga (2/6)

LA-2952P

846Wednesday, October 26, 2005

1

0.3

of

5

D D

SDVO_SDAT<16>

SDVO_SCLK<16>

TXOUT_L0+<17>
TXOUT_L1+<17>
TXOUT_L2+<17>

TXOUT_L0-<17>
TXOUT_L1-<17>
TXOUT_L2-<17>

TXOUT_U0+<17>
TXOUT_U1+<17>
TXOUT_U2+<17>

TXOUT_U0-<17>
TXOUT_U1-<17>
TXOUT_U2-<17>

TXCLK_L+<17>
TXCLK_L-<17>
TXCLK_U+<17>
TXCLK_U-<17>

C C

+3VS

12

12

R9

10K_0402_5%

LCD_CLK
LCD_DAT

B B

R10

10K_0402_5%

BKLT_CTL<17>
ENABLT<17>

LCD_CLK<17>

LCD_DAT<17>
ENAVDD<17>

R351 1.5K_0402_1%

C_DDCCLK<16>

C_DDCDATA<16>

C_VSYNC<16>
C_HSYNC<16>

CRT Termination/EMI Filter

C_RED

A A

C_BLU

12

R171

75_0402_1%

75_0402_1%

5

12

R173

L28

1 2

HLC0603CSCC39NJT_0603

L35

1 2

HLC0603CSCC39NJT_0603

L27

1 2

HLC0603CSCC39NJT_0603

12

R174

18P_0402_50V8J

75_0402_1%

C_RED_L

C_GRN_LC_GRN

C_BLU_L

1

1

C193

C237

2

2

18P_0402_50V8J

1

C232
18P_0402_50V8J

2

4

BKLT_CTL
ENABLT

LCD_CLK
LCD_DAT

ENAVDD

LIBG

12

C_COMP
C_LUMA
C_CRMA

12

R393

4.99K_0603_1%

C_VSYNC
C_HSYNC

C_BLU
C_GRN
C_RED

CRT_IREF

12

R390

255_0402_1%

L31

1 2

HLC0603CSCCR11JT_0603

L34

1 2

HLC0603CSCCR11JT_0603

L26

1 2

HLC0603CSCCR11JT_0603

4

U15C

H27

SDVOCTRL_DATA

H28

SDVOCTRL_CLK

B37

LA_DATA0

B34

LA_DATA1

A36

LA_DATA2

C37

LA_DATA#0

B35

LA_DATA#1

A37

LA_DATA#2

F30

LB_DATA0

D29

LB_DATA1

F28

LB_DATA2

G30

LB_DATA#0

D30

LB_DATA#1

F29

LB_DATA#2

A32

LA_CLK

A33

LA_CLK#

E26

LB_CLK

E27

LB_CLK#

D32

LBKLT_CTL

J30

LBKLT_EN

H30

LCTLA_CLK

H29

LCTLB_DATA

G26

LDDC_CLK

G25

LDDC_DATA

F32

LVDD_EN

B38

LIBG

C35

LVBG

C33

LVREFH

C32

LVREFL

A16

TVDAC_A

C18

TVDAC_B

A19

TVDAC_C

J20

TV_IREF

B16

TV_IRTNA

B18

TV_IRTNB

B19

TV_IRTNC

J29

TV_DCONSEL1

K30

TV_DCONSEL0

C26

DDCCLK

C25

DDCDATA

H23

VSYNC

G23

HSYNC

E23

BLUE

D23

BLUE#

C22

GREEN

B22

GREEN#

A21

RED

B21

RED#

J22

CRT_IREF

CALISTOGA_FCBGA1466~D

<BOM Structure>

INTEL_RED <32>

INTEL_GREEN <32>

INTEL_BLUE <32>

LVDS

TV CRT

3

PEGCOMP trace width
and spacing is 18/25 mils.

EXP_COMPI

EXP_COMPO

EXP_RXN0
EXP_RXN1
EXP_RXN2
EXP_RXN3
EXP_RXN4
EXP_RXN5
EXP_RXN6
EXP_RXN7
EXP_RXN8

EXP_RXN9
EXP_RXN10
EXP_RXN11
EXP_RXN12
EXP_RXN13
EXP_RXN14
EXP_RXN15

EXP_RXP0

EXP_RXP1

EXP_RXP2

EXP_RXP3

EXP_RXP4

EXP_RXP5

EXP_RXP6

EXP_RXP7

EXP_RXP8

EXP_RXP9
EXP_RXP10
EXP_RXP11
EXP_RXP12
EXP_RXP13
EXP_RXP14
EXP_RXP15

EXP_TXN0

EXP_TXN1

EXP_TXN2

EXP_TXN3

EXP_TXN4

EXP_TXN5

EXP_TXN6

EXP_TXN7

EXP_TXN8

PCI-EXPRESS GRAPHICS

EXP_TXN9
EXP_TXN10
EXP_TXN11
EXP_TXN12
EXP_TXN13
EXP_TXN14
EXP_TXN15

EXP_TXP0

EXP_TXP1

EXP_TXP2

EXP_TXP3

EXP_TXP4

EXP_TXP5

EXP_TXP6

EXP_TXP7

EXP_TXP8

EXP_TXP9

EXP_TXP10
EXP_TXP11
EXP_TXP12
EXP_TXP13
EXP_TXP14
EXP_TXP15

D40
D38

F34
G38
H34
J38
L34
M38
N34
P38
R34
T38
V34
W38
Y34
AA38
AB34
AC38

D34
F38
G34
H38
J34
L38
M34
N38
P34
R38
T34
V38
W34
Y38
AA34
AB38

F36
G40
H36
J40
L36
M40
N36
P40
R36
T40
V36
W40
Y36
AA40
AB36
AC40

D36
F40
G36
H40
J36
L40
M36
N40
P36
R40
T36
V40
W36
Y40
AA36
AB40

PEGCOMP

PEG_RXN1

PEG_RXP1

PEG_TXN0
PEG_TXN1
PEG_TXN2
PEG_TXN3

PEG_TXP0
PEG_TXP1
PEG_TXP2
PEG_TXP3

C1045 0.1U_0402_16V4Z
C1046 0.1U_0402_16V4Z
C1047 0.1U_0402_16V4Z
C1048 0.1U_0402_16V4Z

C1049 0.1U_0402_16V4Z
C1050 0.1U_0402_16V4Z
C1051 0.1U_0402_16V4Z
C1065 0.1U_0402_16V4Z

R1176

24.9_0402_1%

1 2

PEG_RXN1 <16>

PEG_RXP1 <16>

1 2
1 2
1 2
1 2

1 2
1 2
1 2
1 2

+1.5VS_PCIE

2

SDVOB_R- <16>
SDVOB_G- <16>
SDVOB_B- <16>
SDVOB_CLK- <16>

SDVOB_R+ <16>
SDVOB_G+ <16>
SDVOB_B+ <16>
SDVOB_CLK+ <16>

TV-Out Termination/EMI Filter

C_COMP

C_LUMA

C_CRMA

12

R175

75_0402_1%

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/05/26 2006/07/26

12

12

R177

R176

75_0402_1%

75_0402_1%

Compal Secret Data

82P_0402_50V8J

1

C7

C238

2

82P_0402_50V8J

Deciphered Date

1

C251

2

82P_0402_50V8J

L38

1 2

CHB1608U301_0603
L37

1 2

CHB1608U301_0603
L17

1 2

CHB1608U301_0603

1

82P_0402_50V8J

2

2

C333

1

1

C354

2

2

82P_0402_50V8J

1

COMP <16,32>

LUMA <16,32>

CRMA <16,32>

1

C355
82P_0402_50V8J

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

Calistoga (3/6)

LA-2952P

946Wednesday, October 26, 2005

1

of

0.3

5

4

3

2

1

+1.5VS_DPLLA +1.5VS_DPLLB

12

+

1

@

330U_D2E_2.5VM

2

10_0402_5%@

R260

L40
CHB1608U301_0603@

C666

1

C155

2

2200P_0402_50V7K

R118
0_0603_5%

+1.5VS+1.5VS

R520

1 2

0_1206_5%

12

0_0805_5%

1

C157

2

0.1U_0402_16V4Z

12

+1.5VS

D21
CH751H-40_SOD323

@

1 2
12

R97

+1.5VS+1.5VS

12

1

C172

2

0.1U_0402_16V4Z

@

+3VS+3VS_TVDACA+3VS+3VS_TVDACB+3VS+3VS_TVDACC

Place close to Pin G41

+2.5VS

+2.5VS

1

2

1

2

+1.5VS_DPLLA +1.5VS_DPLLB

C158

0.1U_0402_16V4Z

C831

0.1U_0402_16V4Z

C154

2200P_0402_50V7K

1

2

R179

C149

0.1U_0402_16V4Z

1

2

12

0_0805_5%

L41

CHB1608U301_0603

1

C616

330U_D2E_2.5VM

+

2

12

1

C145

2

2200P_0402_50V7K

PCI-E/MEM/PSB PLL decoupling

R1339

1

2

0.1U_0402_16V4Z

12

0_0805_5%

3GPLL

R1173

0_0805_5%

C860
10U_0805_6.3V6M

+3VS+3VS_TVBG

1 2

0.5_0805_1%

1

1

C839

C838

2

2

0.1U_0402_16V4Z
10U_0805_6.3V6M

+1.5VS_MPLL

45mA Max. 45mA Max.

1

C859

2

R61

1

1

C151

2

2

C152

0.1U_0402_16V4Z

2200P_0402_50V7K

R1168

0_0805_5%

12

12

C841

@

+1.5VS+1.5VS_3GPLL

1

2

0.1U_0402_16V4Z

10_0402_5%@

C253

0.1U_0402_16V4Z

1

2

R115

12

1

2

+1.5VS_HPLL

0_0805_5%

C146

0.1U_0402_16V4Z

+1.5VS_TVDAC +1.5VS

1

1

C153

C614

2

2

0.1U_0402_16V4Z
2200P_0402_50V7K

R1174

0_0805_5%

1

1

C862

C861

10U_0805_6.3V6M

2

2

0.1U_0402_16V4Z

+VCCP

D12
CH751H-40_SOD323

@

1 2
12

+2.5VS +3VS

R127

+2.5VS

C162

D D

C C

1

C836

C837

2

4.7U_0805_10V4Z

B B

A A

1

C849

2

0.22U_0603_10V7K

1

2

1

+

2

1

2

2.2U_0805_16V4Z

MCH_A6

1

C844

2

MCH_D2

C853

0.22U_0603_10V7K

C856

+1.5VS

+VCCP

C830

220U_D2_2VM_R9

0.47U_0603_10V7K

MCH_AB1

1

2

0.47U_0603_10V7K

U15H

AC14

VTT0

AB14

VTT1

W14

VTT2

V14

VTT3

T14

VTT4

R14

VTT5

P14

VTT6

N14

VTT7

M14

VTT8

L14

VTT9

AD13

VTT10

AC13

VTT11

AB13

VTT12

AA13

VTT13

Y13

VTT14

W13

VTT15

V13

VTT16

U13

VTT17

T13

VTT18

R13

VTT19

N13

VTT20

M13

VTT21

L13

VTT22

AB12

VTT23

AA12

VTT24

Y12

VTT25

W12

VTT26

V12

VTT27

U12

VTT28

T12

VTT29

R12

VTT30

P12

VTT31

N12

VTT32

M12

VTT33

L12

VTT34

R11

VTT35

P11

VTT36

N11

VTT37

M11

VTT38

R10

VTT39

P10

VTT40

N10

VTT41

M10

VTT42

P9

VTT43

N9

VTT44

M9

VTT45

R8

VTT46

P8

VTT47

N8

VTT48

M8

VTT49

P7

VTT50

N7

VTT51

M7

VTT52

R6

VTT53

P6

VTT54

M6

VTT55

A6

VTT56

R5

VTT57

P5

VTT58

N5

VTT59

M5

VTT60

P4

VTT61

N4

VTT62

M4

VTT63

R3

VTT64

P3

VTT65

N3

VTT66

M3

VTT67

R2

VTT68

P2

VTT69

M2

VTT70

D2

VTT71

AB1

VTT72

R1

VTT73

P1

VTT74

N1

VTT75

M1

VTT76

AG14

VCCAUX32

AF14

VCCAUX33

AE14

VCCAUX34

Y14

VCCAUX35

AF13

VCCAUX36

AE13

VCCAUX37

AF12

VCCAUX38

AE12

VCCAUX39

AD12

VCCAUX40

CALISTOGA_FCBGA1466~D

P O W E R

VCC_SYNC

VCCTX_LVDS0
VCCTX_LVDS1
VCCTX_LVDS2

VCC3G0
VCC3G1
VCC3G2
VCC3G3
VCC3G4
VCC3G5
VCC3G6

VCCA_3GPLL

VCCA_3GBG
VSSA_3GBG

VCCA_CRTDAC0
VCCA_CRTDAC1
VSSA_CRTDAC2

VCCA_DPLLA
VCCA_DPLLB

VCCA_HPLL

VCCA_LVDS
VSSA_LVDS

VCCA_MPLL

VCCA_TVBG

VSSA_TVBG

VCCA_TVDACA0
VCCA_TVDACA1
VCCA_TVDACB0
VCCA_TVDACB1
VCCA_TVDACC0
VCCA_TVDACC1

VCCD_HMPLL0
VCCD_HMPLL1

VCCD_LVDS0
VCCD_LVDS1
VCCD_LVDS2

VCCD_TVDAC

VCCDQ_TVDAC

VCCHV0
VCCHV1
VCCHV2

VCCAUX0
VCCAUX1
VCCAUX2
VCCAUX3
VCCAUX4
VCCAUX5
VCCAUX6
VCCAUX7
VCCAUX8

VCCAUX9
VCCAUX10
VCCAUX11
VCCAUX12
VCCAUX13
VCCAUX14
VCCAUX15
VCCAUX16
VCCAUX17
VCCAUX18
VCCAUX19
VCCAUX20
VCCAUX21
VCCAUX22
VCCAUX23
VCCAUX24
VCCAUX25
VCCAUX26
VCCAUX27
VCCAUX28
VCCAUX29
VCCAUX30
VCCAUX31

H22

B30
C30
A30

AB41
AJ41
L41
N41
R41
V41
Y41

AC33
G41
H41

E21
F21
G21

B26
C39
AF1

A38
B39

AF2
H20

G20

E19
F19
C20
D20
E20
F20

AH1
AH2

A28
B28
C28

D21
H19

A23
B23
B25

AK31
AF31
AE31
AC31
AL30
AK30
AJ30
AH30
AG30
AF30
AE30
AD30
AC30
AG29
AF29
AE29
AD29
AC29
AG28
AF28
AE28
AH22
AJ21
AH21
AJ20
AH20
AH19
P19
P16
AH15
P15
AH14

0.1U_0402_16V4Z

1 2

W=40 mils

+1.5VS_3GPLL
+2.5VS

MCH_CRTDAC

+1.5VS_DPLLA
+1.5VS_DPLLB
+1.5VS_HPLL

+2.5VS

+1.5VS_MPLL

+3VS_TVBG

+3VS_TVDACA
+3VS_TVDACB
+3VS_TVDACC

+1.5VS

+1.5VS

+1.5VS_TVDAC

+1.5VS

1

C850

2

1

2

C845

0.1U_0402_16V4Z

0.1U_0402_16V4Z

+2.5VS

10U_0805_6.3V6M

1

+

2

C981
220U_D2_2VM_R9

1

C144

2

+3VS

1

C846
10U_0805_6.3V6M

2

+1.5VS_PCIE

C825

C824

1

1

10U_0805_6.3V6M

2

2

L39

1

C143

2

2200P_0402_50V7K

0.1U_0402_16V4Z

R1163

0_0805_5%

1 2

12

+1.5VS

BLM11A601S_0603

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/05/26 2006/07/26

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

2

Date: Sheet

Compal Electronics, Inc.

Calistoga (4/6)

LA-2952P

10 46Wednesday, October 26, 2005

1

0.3

of

5

4

3

2

1

Strap Pin Table

CFG[3:17] have internal pull up

+VCCP

D D

1

1

1

C798

C797

C796

2

0.22U_0603_10V7K

10U_0805_6.3V6M

1

C803

C804

2

10U_0805_6.3V6M

C C

C811

B B

C806

0.22U_0603_10V7K

220U_D2_2VM_R9

2

2

0.22U_0603_10V7K

1

1

C805

2

2

1U_0603_10V4Z

1

1

C980

+

+

2

2

330U_D2E_2.5VM_R9

@

1

+

2

330U_D2E_2.5VM_R9

@

+VCCP

U15F

AD27

VCC_NCTF0

AC27

VCC_NCTF1

AB27

VCC_NCTF2

AA27

VCC_NCTF3

Y27

VCC_NCTF4

W27

VCC_NCTF5

V27

VCC_NCTF6

U27

VCC_NCTF7

T27

VCC_NCTF8

R27

VCC_NCTF9

AD26

VCC_NCTF10

AC26

VCC_NCTF11

AB26

VCC_NCTF12

AA26

VCC_NCTF13

Y26

VCC_NCTF14

W26

VCC_NCTF15

V26

VCC_NCTF16

U26

VCC_NCTF17

T26

VCC_NCTF18

R26

VCC_NCTF19

AD25

VCC_NCTF20

AC25

VCC_NCTF21

AB25

VCC_NCTF22

AA25

VCC_NCTF23

Y25

VCC_NCTF24

W25

VCC_NCTF25

V25

VCC_NCTF26

U25

VCC_NCTF27

T25

VCC_NCTF28

R25

VCC_NCTF29

AD24

VCC_NCTF30

AC24

VCC_NCTF31

AB24

VCC_NCTF32

AA24

VCC_NCTF33

Y24

VCC_NCTF34

W24

VCC_NCTF35

V24

VCC_NCTF36

U24

VCC_NCTF37

T24

VCC_NCTF38

R24

VCC_NCTF39

AD23

VCC_NCTF40

V23

VCC_NCTF41

U23

VCC_NCTF42

T23

VCC_NCTF43

R23

VCC_NCTF44

AD22

VCC_NCTF45

V22

VCC_NCTF46

U22

VCC_NCTF47

T22

VCC_NCTF48

R22

VCC_NCTF49

AD21

VCC_NCTF50

V21

VCC_NCTF51

U21

VCC_NCTF52

T21

VCC_NCTF53

R21

VCC_NCTF54

AD20

VCC_NCTF55

V20

VCC_NCTF56

U20

VCC_NCTF57

T20

VCC_NCTF58

R20

VCC_NCTF59

AD19

VCC_NCTF60

V19

VCC_NCTF61

U19

VCC_NCTF62

T19

VCC_NCTF63

AD18

VCC_NCTF64

AC18

VCC_NCTF65

AB18

VCC_NCTF66

AA18

VCC_NCTF67

Y18

VCC_NCTF68

W18

VCC_NCTF69

V18

VCC_NCTF70

U18

VCC_NCTF71

T18

VCC_NCTF72

M19

VCC100

L19

VCC101

N18

VCC102

M18

VCC103

L18

VCC104

P17

VCC105

N17

VCC106

M17

VCC107

N16

VCC108

M16

VCC109

L16

VCC110

CALISTOGA_FCBGA1466~D

VCCAUX_NCTF0
VCCAUX_NCTF1
VCCAUX_NCTF2
VCCAUX_NCTF3
VCCAUX_NCTF4
VCCAUX_NCTF5
VCCAUX_NCTF6
VCCAUX_NCTF7
VCCAUX_NCTF8

VCCAUX_NCTF9
VCCAUX_NCTF10
VCCAUX_NCTF11
VCCAUX_NCTF12
VCCAUX_NCTF13
VCCAUX_NCTF14
VCCAUX_NCTF15
VCCAUX_NCTF16
VCCAUX_NCTF17
VCCAUX_NCTF18
VCCAUX_NCTF19
VCCAUX_NCTF20
VCCAUX_NCTF21
VCCAUX_NCTF22
VCCAUX_NCTF23
VCCAUX_NCTF24
VCCAUX_NCTF25
VCCAUX_NCTF26
VCCAUX_NCTF27
VCCAUX_NCTF28
VCCAUX_NCTF29
VCCAUX_NCTF30
VCCAUX_NCTF31
VCCAUX_NCTF32
VCCAUX_NCTF33
VCCAUX_NCTF34
VCCAUX_NCTF35
VCCAUX_NCTF36

P O W E R

VCCAUX_NCTF37
VCCAUX_NCTF38
VCCAUX_NCTF39
VCCAUX_NCTF40
VCCAUX_NCTF41
VCCAUX_NCTF42
VCCAUX_NCTF43
VCCAUX_NCTF44
VCCAUX_NCTF45
VCCAUX_NCTF46
VCCAUX_NCTF47
VCCAUX_NCTF48
VCCAUX_NCTF49
VCCAUX_NCTF50
VCCAUX_NCTF51
VCCAUX_NCTF52
VCCAUX_NCTF53
VCCAUX_NCTF54
VCCAUX_NCTF55
VCCAUX_NCTF56
VCCAUX_NCTF57

VSS_NCTF0
VSS_NCTF1
VSS_NCTF2
VSS_NCTF3
VSS_NCTF4
VSS_NCTF5
VSS_NCTF6
VSS_NCTF7
VSS_NCTF8

VSS_NCTF9
VSS_NCTF10
VSS_NCTF11
VSS_NCTF12

VCC_SM100

VCC_SM101

VCC_SM102

VCC_SM103

VCC_SM104

VCC_SM105

VCC_SM106

VCC_SM107

AG27
AF27
AG26
AF26
AG25
AF25
AG24
AF24
AG23
AF23
AG22
AF22
AG21
AF21
AG20
AF20
AG19
AF19
R19
AG18
AF18
R18
AG17
AF17
AE17
AD17
AB17
AA17
W17
V17
T17
R17
AG16
AF16
AE16
AD16
AC16
AB16
AA16
Y16
W16
V16
U16
T16
R16
AG15
AF15
AE15
AD15
AC15
AB15
AA15
Y15
W15
V15
U15
T15
R15

AE27
AE26
AE25
AE24
AE23
AE22
AE21
AE20
AE19
AE18
AC17
Y17
U17

AR6
AP6
AN6
AL6
AK6
AJ6
AV1
AJ1

+1.5VS

VCCSM_LF2
VCCSM_LF1

C813

+1.8V

0.47U_0603_10V7K

1

1

C814

2

2

0.47U_0603_10V7K

Place near pin AV1 & AJ1

A A

+VCCP

U15G

AA33

VCC0

W33

VCC1

P33

VCC2

N33

VCC3

L33

VCC4

J33

VCC5

AA32

VCC6

Y32

VCC7

W32

VCC8

V32

VCC9

P32

VCC10

N32

VCC11

M32

VCC12

L32

VCC13

J32

VCC14

AA31

VCC15

W31

VCC16

V31

VCC17

T31

VCC18

R31

VCC19

P31

VCC20

N31

VCC21

M31

VCC22

AA30

VCC23

Y30

VCC24

W30

VCC25

V30

VCC26

U30

VCC27

T30

VCC28

R30

VCC29

P30

VCC30

N30

VCC31

M30

VCC32

L30

VCC33

AA29

VCC34

Y29

VCC35

W29

VCC36

V29

VCC37

U29

VCC38

R29

VCC39

P29

VCC40

M29

VCC41

L29

VCC42

AB28

VCC43

AA28

VCC44

Y28

VCC45

V28

VCC46

U28

VCC47

T28

VCC48

R28

VCC49

P28

VCC50

N28

VCC51

M28

VCC52

L28

VCC53

P27

VCC54

N27

VCC55

M27

VCC56

L27

VCC57

P26

VCC58

N26

VCC59

L26

VCC60

N25

VCC61

M25

VCC62

L25

VCC63

P24

VCC64

N24

VCC65

M24

VCC66

AB23

VCC67

AA23

VCC68

Y23

VCC69

P23

VCC70

N23

VCC71

M23

VCC72

L23

VCC73

AC22

VCC74

AB22

VCC75

Y22

VCC76

W22

VCC77

P22

VCC78

N22

VCC79

M22

VCC80

L22

VCC81

AC21

VCC82

AA21

VCC83

W21

VCC84

N21

VCC85

M21

VCC86

L21

VCC87

AC20

VCC88

AB20

VCC89

Y20

VCC90

W20

VCC91

P20

VCC92

N20

VCC93

M20

VCC94

L20

VCC95

AB19

VCC96

AA19

VCC97

Y19

VCC98

N19

VCC99

CALISTOGA_FCBGA1466~D

P O W E R

VCC_SM0
VCC_SM1
VCC_SM2
VCC_SM3
VCC_SM4
VCC_SM5
VCC_SM6
VCC_SM7
VCC_SM8

VCC_SM9
VCC_SM10
VCC_SM11
VCC_SM12
VCC_SM13
VCC_SM14
VCC_SM15
VCC_SM16
VCC_SM17
VCC_SM18
VCC_SM19
VCC_SM20
VCC_SM21
VCC_SM22
VCC_SM23
VCC_SM24
VCC_SM25
VCC_SM26
VCC_SM27
VCC_SM28
VCC_SM29
VCC_SM30
VCC_SM31
VCC_SM32
VCC_SM33
VCC_SM34
VCC_SM35
VCC_SM36
VCC_SM37
VCC_SM38
VCC_SM39
VCC_SM40
VCC_SM41
VCC_SM42
VCC_SM43
VCC_SM44
VCC_SM45
VCC_SM46
VCC_SM47
VCC_SM48
VCC_SM49
VCC_SM50
VCC_SM51
VCC_SM52
VCC_SM53
VCC_SM54
VCC_SM55
VCC_SM56
VCC_SM57
VCC_SM58
VCC_SM59
VCC_SM60
VCC_SM61
VCC_SM62
VCC_SM63
VCC_SM64
VCC_SM65
VCC_SM66
VCC_SM67
VCC_SM68
VCC_SM69
VCC_SM70
VCC_SM71
VCC_SM72
VCC_SM73
VCC_SM74
VCC_SM75
VCC_SM76
VCC_SM77
VCC_SM78
VCC_SM79
VCC_SM80
VCC_SM81
VCC_SM82
VCC_SM83
VCC_SM84
VCC_SM85
VCC_SM86
VCC_SM87
VCC_SM88
VCC_SM89
VCC_SM90
VCC_SM91
VCC_SM92
VCC_SM93
VCC_SM94
VCC_SM95
VCC_SM96
VCC_SM97
VCC_SM98
VCC_SM99

AU41
AT41
AM41
AU40
BA34
AY34
AW34
AV34
AU34
AT34
AR34
BA30
AY30
AW30
AV30
AU30
AT30
AR30
AP30
AN30
AM30
AM29
AL29
AK29
AJ29
AH29
AJ28
AH28
AJ27
AH27
BA26
AY26
AW26
AV26
AU26
AT26
AR26
AJ26
AH26
AJ25
AH25
AJ24
AH24
BA23
AJ23
BA22
AY22
AW22
AV22
AU22
AT22
AR22
AP22
AK22
AJ22
AK21
AK20
BA19
AY19
AW19
AV19
AU19
AT19
AR19
AP19
AK19
AJ19
AJ18
AJ17
AH17
AJ16
AH16
BA15
AY15
AW15
AV15
AU15
AT15
AR15
AJ15
AJ14
AJ13
AH13
AK12
AJ12
AH12
AG12
AK11
BA8
AY8
AW8
AV8
AT8
AR8
AP8
BA6
AY6
AW6
AV6
AT6

+1.8V

VCCSM_LF4
VCCSM_LF5

C794

Place near pin AT41 & AM41

C807

Place near pin BA23

C809

10U_0805_6.3V6M

C812

Place near pin BA15

1

C795

2

0.47U_0603_10V7K

1

C799

2

0.1U_0402_16V4Z

1

2

0.47U_0603_10V7K

1

C810

2

10U_0805_6.3V6M

1

2

0.47U_0603_10V7K

CFG[2:0]

1

2

0.47U_0603_10V7K

CFG5

CFG7

CFG9

CFG11

CFG[13:12]

+1.8V

CFG16

1

C800

2

0.1U_0402_16V4Z

C801

1

1

C802

2

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

CFG18

CFG19

SDVO_CTRLDATA

CFG20

(PCIE/SDVO select)

1

1

+

C808

220U_D2_4VM@

2

2

CFG[19:18] have internal pull down

011 = 667MT/s FSB
001 = 533MT/s FSB

0 = DMI x 2
1 = DMI x 4

0 = Reserved
1 = Mobile Yonah CPU

0 = Lane Reversal Enable
1 = Normal Operation

0 = Calistoga

(According to Intel Napa Schematic Checklist & CRB
Rev1.301 document 2.2Kohm pull-down resistor request)

1 = Reserved

00 = Reserved
01 = XOR Mode Enabled
10 = All Z Mode Enabled
11 = Normal Operation

0 = Dynamic ODT Disabled
1 = Dynamic ODT Enabled (Default)

0 = 1.05V
1 = 1.5V

0 = Normal Operation
1 = DMI Lane Reversal Enable

0 = No SDVO Device Present

(Default)

(Default)

*

*

(Default)

*

(Default)

*

(Default)

*

*

1 = SDVO Device Present

0 = Only PCIE or SDVO is
operational.
1 = PCIE/SDVO are operating
simu.

R1151 2.2K_0402_5%@

CFG5<7>

R1152 2.2K_0402_5%@

CFG7<7>

R1153 2.2K_0402_5%@

CFG9<7>
CFG11<7>
CFG12<7>
CFG13<7>
CFG16<7>

CFG18<7>
CFG19<7>
CFG20<7>

R1154 2.2K_0402_5%@
R1155 2.2K_0402_5%@
R1156 2.2K_0402_5%@
R1157 2.2K_0402_5%@

R1158 1K_0402_5%@
R1159 1K_0402_5%@
R1160 1K_0402_5%@

*

1 2
1 2
1 2
1 2
1 2
1 2
1 2

1 2
1 2
1 2

(Default)

*

(Default)

*

(Default)

*

+3VS

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/05/26 2006/07/26

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

2

Date: Sheet

Compal Electronics, Inc.

Calistoga (5/6)

LA-2952P

11 46Wednesday, October 26, 2005

1

0.3

of

5

4

3

2

1

U15I

AC41

VSS0

AA41

VSS1

W41

VSS2

T41

VSS3

P41

VSS4

M41

D D

C C

B B

A A

VSS5

J41

VSS6

F41

VSS7

AV40

VSS8

AP40

VSS9

AN40

VSS10

AK40

VSS11

AJ40

VSS12

AH40

VSS13

AG40

VSS14

AF40

VSS15

AE40

VSS16

B40

VSS17

AY39

VSS18

AW39

VSS19

AV39

VSS20

AR39

VSS21

AN39

VSS22

AJ39

VSS23

AC39

VSS24

AB39

VSS25

AA39

VSS26

Y39

VSS27

W39

VSS28

V39

VSS29

T39

VSS30

R39

VSS31

P39

VSS32

N39

VSS33

M39

VSS34

L39

VSS35

J39

VSS36

H39

VSS37

G39

VSS38

F39

VSS39

D39

VSS40

AT38

VSS41

AM38

VSS42

AH38

VSS43

AG38

VSS44

AF38

VSS45

AE38

VSS46

C38

VSS47

AK37

VSS48

AH37

VSS49

AB37

VSS50

AA37

VSS51

Y37

VSS52

W37

VSS53

V37

VSS54

T37

VSS55

R37

VSS56

P37

VSS57

N37

VSS58

M37

VSS59

L37

VSS60

J37

VSS61

H37

VSS62

G37

VSS63

F37

VSS64

D37

VSS65

AY36

VSS66

AW36

VSS67

AN36

VSS68

AH36

VSS69

AG36

VSS70

AF36

VSS71

AE36

VSS72

AC36

VSS73

C36

VSS74

B36

VSS75

BA35

VSS76

AV35

VSS77

AR35

VSS78

AH35

VSS79

AB35

VSS80

AA35

VSS81

Y35

VSS82

W35

VSS83

V35

VSS84

T35

VSS85

R35

VSS86

P35

VSS87

N35

VSS88

M35

VSS89

L35

VSS90

J35

VSS91

H35

VSS92

G35

VSS93

F35

VSS94

D35

VSS95

AN34

VSS96

AK34

VSS97

AG34

VSS98

AF34

VSS99

CALISTOGA_FCBGA1466~D

P O W E R

VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS140
VSS141
VSS142
VSS143
VSS144
VSS145
VSS146
VSS147
VSS148
VSS149
VSS150
VSS151
VSS152
VSS153
VSS154
VSS155
VSS156
VSS157
VSS158
VSS159
VSS160
VSS161
VSS162
VSS163
VSS164
VSS165
VSS166
VSS167
VSS168
VSS169
VSS170
VSS171
VSS172
VSS173
VSS174
VSS175
VSS176
VSS177
VSS178
VSS179
VSS180
VSS181
VSS182
VSS183
VSS184
VSS185
VSS186
VSS187
VSS188
VSS189
VSS190
VSS191
VSS192
VSS193
VSS194
VSS195
VSS196
VSS197
VSS198
VSS199

AE34
AC34
C34
AW33
AV33
AR33
AE33
AB33
Y33
V33
T33
R33
M33
H33
G33
F33
D33
B33
AH32
AG32
AF32
AE32
AC32
AB32
G32
B32
AY31
AV31
AN31
AJ31
AG31
AB31
Y31
AB30
E30
AT29
AN29
AB29
T29
N29
K29
G29
E29
C29
B29
A29
BA28
AW28
AU28
AP28
AM28
AD28
AC28
W28
J28
E28
AP27
AM27
AK27
J27
G27
F27
C27
B27
AN26
M26
K26
F26
D26
AK25
P25
K25
H25
E25
D25
A25
BA24
AU24
AL24
AW23
AT23
AN23
AM23
AH23
AC23
W23
K23
J23
F23
C23
AA22
K22
G22
F22
E22
D22
A22
BA21
AV21
AR21

U15J

AN21

VSS200

AL21

VSS201

AB21

VSS202

Y21

VSS203

P21

VSS204

K21

VSS205

J21

VSS206

H21

VSS207

C21

VSS208

AW20

VSS209

AR20

VSS210

AM20

VSS211

AA20

VSS212

K20

VSS213

B20

VSS214

A20

VSS215

AN19

VSS216

AC19

VSS217

W19

VSS218

K19

VSS219

G19

VSS220

C19

VSS221

AH18

VSS222

P18

VSS223

H18

VSS224

D18

VSS225

A18

VSS226

AY17

VSS227

AR17

VSS228

AP17

VSS229

AM17

VSS230

AK17

VSS231

AV16

VSS232

AN16

VSS233

AL16

VSS234

J16

VSS235

F16

VSS236

C16

VSS237

AN15

VSS238

AM15

VSS239

AK15

VSS240

N15

VSS241

M15

VSS242

L15

VSS243

B15

VSS244

A15

VSS245

BA14

VSS246

AT14

VSS247

AK14

VSS248

AD14

VSS249

AA14

VSS250

U14

VSS251

K14

VSS252

H14

VSS253

E14

VSS254

AV13

VSS255

AR13

VSS256

AN13

VSS257

AM13

VSS258

AL13

VSS259

AG13

VSS260

P13

VSS261

F13

VSS262

D13

VSS265

B13

VSS264

AY12

VSS263

AC12

VSS266

K12

VSS267

H12

VSS268

E12

VSS269

AD11

VSS270

AA11

VSS271

Y11

VSS272

J11

VSS273

D11

VSS274

B11

VSS275

AV10

VSS276

AP10

VSS277

AL10

VSS278

AJ10

VSS279

CALISTOGA_FCBGA1466~D

P O W E R

VSS280
VSS281
VSS282
VSS283
VSS284
VSS285
VSS286
VSS287
VSS288
VSS289
VSS290
VSS292
VSS291
VSS293
VSS294
VSS295
VSS296
VSS297
VSS298
VSS299
VSS300
VSS301
VSS302
VSS303
VSS304
VSS305
VSS306
VSS307
VSS308
VSS309
VSS310
VSS311
VSS312
VSS313
VSS314
VSS315
VSS316
VSS317
VSS318
VSS319
VSS320
VSS321
VSS322
VSS323
VSS324
VSS325
VSS326
VSS327
VSS328
VSS329
VSS330
VSS331
VSS332
VSS333
VSS334
VSS335
VSS336
VSS337
VSS338
VSS339
VSS340
VSS341
VSS342
VSS343
VSS344
VSS345
VSS346
VSS347
VSS348
VSS349
VSS350
VSS351
VSS352
VSS353
VSS354
VSS355
VSS356
VSS357
VSS358
VSS359
VSS360

AG10
AC10
W10
U10
BA9
AW9
AR9
AH9
AB9
Y9
R9
G9
E9
A9
AG8
AD8
AA8
U8
K8
C8
BA7
AV7
AP7
AL7
AJ7
AH7
AF7
AC7
R7
G7
D7
AG6
AD6
AB6
Y6
U6
N6
K6
H6
B6
AV5
AF5
AD5
AY4
AR4
AP4
AL4
AJ4
Y4
U4
R4
J4
F4
C4
AY3
AW3
AV3
AL3
AH3
AG3
AF3
AD3
AC3
AA3
G3
AT2
AR2
AP2
AK2
AJ2
AD2
AB2
Y2
U2
T2
N2
J2
H2
F2
C2
AL1

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/05/26 2006/07/26

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

2

Date: Sheet

Compal Electronics, Inc.

Calistoga (6/6)

LA-2952P

12 46Wednesday, October 26, 2005

1

0.3

of

5

DDR_A_DQS#[0..7]<8>

DDR_A_D[0..63]<8>

DDR_A_DM[0..7]<8>
DDR_A_DQS[0..7]<8>
DDR_A_MA[0..13]<8>

D D

Layout Note:
Place near JP34

+1.8V

2.2U_0805_16V4Z

2.2U_0805_16V4Z

C C

B B

A A

Layout Note:
Place one cap close to every 2 pullup
resistors terminated to +0.9V

+0.9V

0.1U_0402_16V4Z

DDR_A_MA5
DDR_A_MA8

DDR_A_MA1
DDR_A_MA3

DDR_A_RAS#
DDR_CS0_DIMMA#

DDR_A_BS#0
DDR_A_MA10

DDR_A_CAS#
DDR_A_WE#

DDR_CS1_DIMMA#
M_ODT1

1

2

1

2

C229

C458

C498

1

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

2

C239

RP27

1 4
2 3

RP29

1 4
2 3

RP32

1 4
2 3

RP31

1 4
2 3

RP33

1 4
2 3

RP35

2 3
1 4

5

2.2U_0805_16V4Z
C473

1

2

0.1U_0402_16V4Z

1

1

2

2

C250

56_0404_4P2R_5%

56_0404_4P2R_5%

56_0404_4P2R_5%

56_0404_4P2R_5%

56_0404_4P2R_5%

56_0404_4P2R_5%

C257

2.2U_0805_16V4Z

+0.9V

C491

1

2

0.1U_0402_16V4Z

1

2

C272

0.1U_0402_16V4Z

2.2U_0805_16V4Z
C465

1

1

2

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

2

2

C279

C281

RP22 56_0404_4P2R_5%

DDR_A_BS#2

14

DDR_CKE0_DIMMA

23

RP26 56_0404_4P2R_5%

DDR_A_MA7

14

DDR_A_MA6

23

RP25 56_0404_4P2R_5%

DDR_A_MA9

14

DDR_A_MA12

23

RP28 56_0404_4P2R_5%

DDR_A_MA4

14

DDR_A_MA2

23

RP30 56_0404_4P2R_5%

DDR_A_MA0

14

DDR_A_BS#1

23

RP34 56_0404_4P2R_5%

M_ODT0

14

DDR_A_MA13

23

RP24 56_0404_4P2R_5%

DDR_CKE1_DIMMA

14

DDR_A_MA11

23

C255

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

2

0.1U_0402_16V4Z

1

2

C274

C242

1

2

C268

0.1U_0402_16V4Z
C280

1

2

0.1U_0402_16V4Z

1

2

C252

4

0.1U_0402_16V4Z
C235

1

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

2

2

C234

C241

Layout Note:
Place these resistor
closely JP34,all
trace length Max=1.5"

4

3

+1.8V

JP34

1

VREF

3

DDR_A_D0
DDR_A_D4

DDR_A_DQS#0
DDR_A_DQS0

DDR_A_D2
DDR_A_D3

DDR_A_D8
DDR_A_D14

DDR_A_DQS#1
DDR_A_DQS1

DDR_A_D10
DDR_A_D11

DDR_A_D21
DDR_A_D17

DDR_A_DQS#2
DDR_A_DQS2

DDR_A_D22
DDR_A_D19 DDR_A_D23

DDR_A_D25
DDR_A_D24

DDR_A_DM3

DDR_A_D27
DDR_A_D30

DDR_CKE0_DIMMA<7>

DDR_A_BS#2<8>

DDR_A_BS#0<8>

DDR_A_WE#<8>

DDR_A_CAS#<8>

0.1U_0402_16V4Z

1

2

C227

DDR_CS1_DIMMA#<7>

M_ODT1<7>

ICH_SMBDATA<4,14,15,20,22,24>

ICH_SMBCLK<4,14,15,20,22,24>

DDR_CKE0_DIMMA

DDR_A_BS#2
DDR_A_MA12

DDR_A_MA9 DDR_A_MA7
DDR_A_MA8

DDR_A_MA5
DDR_A_MA3
DDR_A_MA1

DDR_A_MA10
DDR_A_BS#0
DDR_A_WE#

DDR_A_CAS#
DDR_CS1_DIMMA#

M_ODT1
DDR_A_D34

DDR_A_D38
DDR_A_DQS#4

DDR_A_DQS4
DDR_A_D39

DDR_A_D35
DDR_A_D45

DDR_A_D41
DDR_A_DM5
DDR_A_D42

DDR_A_D43
DDR_A_D52

DDR_A_D53

DDR_A_DQS#6
DDR_A_DQS6

DDR_A_D55
DDR_A_D56

DDR_A_D61
DDR_A_DM7
DDR_A_D58

DDR_A_D59
ICH_SMBDATA

ICH_SMBCLK

+3VS

1

C308

0.1U_0402_16V4Z

2

VSS

5

DQ0

7

DQ1

9

VSS

11

DQS0#

13

DQS0

15

VSS

17

DQ2

19

DQ3

21

VSS

23

DQ8

25

DQ9

27

VSS

29

DQS1#

31

DQS1

33

VSS

35

DQ10

37

DQ11

39

VSS

41

VSS

43

DQ16

45

DQ17

47

VSS

49

DQS2#

51

DQS2

53

VSS

55

DQ18

57

DQ19

59

VSS

61

DQ24

63

DQ25

65

VSS

67

DM3

69

NC

71

VSS

73

DQ26

75

DQ27

77

VSS

79

CKE0

81

VDD

83

NC

85

BA2

87

VDD

89

A12

91

A9

93

A8

95

VDD

97

A5

99

A3

101

A1

103

VDD

105

A10/AP

107

BA0

109

WE#

111

VDD

113

CAS#

115

NC/S1#

117

VDD

119

NC/ODT1

121

VSS

123

DQ32

125

DQ33

127

VSS

129

DQS4#

131

DQS4

133

VSS

135

DQ34

137

DQ35

139

VSS

141

DQ40

143

DQ41

145

VSS

147

DM5

149

VSS

151

DQ42

153

DQ43

155

VSS

157

DQ48

159

DQ49

161

VSS

163

NC,TEST

165

VSS

167

DQS6#

169

DQS6

171

VSS

173

DQ50

175

DQ51

177

VSS

179

DQ56

181

DQ57

183

VSS

185

DM7

187

VSS

189

DQ58

191

DQ59

193

VSS

195

SDA

197

SCL

199

VDDSPD

203

GND

FOX_ASOA426-M4R-TR

SO-DIMM A

REVERSE

DQ4
DQ5

DM0
DQ6

DQ7

DQ12
DQ13

DM1

CK0#

DQ14
DQ15

DQ20
DQ21

DM2

DQ22
DQ23

DQ28
DQ29

DQS3#

DQS3
DQ30

DQ31

NC/CKE1

VDD
NC/A15
NC/A14

VDD

VDD

VDD

RAS#

VDD

ODT0

NC/A13

VDD

DQ36
DQ37

DM4

DQ38
DQ39

DQ44
DQ45

DQS5#

DQS5
DQ46

DQ47
DQ52

DQ53

CK1#

DM6

DQ54
DQ55

DQ60
DQ61

DQS7#

DQS7
DQ62

DQ63

SAO

GND

VSS

VSS
VSS

VSS

VSS
VSS

CK0
VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

A11

BA1
S0#

VSS

VSS
VSS

VSS

VSS

VSS

VSS

VSS
CK1

VSS
VSS

VSS

VSS

VSS

VSS
SA1

2

+1.8V

V_DDR_MCH_REF

2

DDR_A_D7

4

DDR_A_D1

6
8

DDR_A_DM0

10
12

DDR_A_D5

14

DDR_A_D6

16
18

DDR_A_D12

20

DDR_A_D13

22
24

DDR_A_DM1

26
28

M_CLK_DDR0

30

M_CLK_DDR#0

32
34

DDR_A_D9

36

DDR_A_D15

38
40

42

DDR_A_D20

44

DDR_A_D16

46
48
50

NC

A7
A6

A4
A2
A0

NC

52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
204

DDR_A_DM2
DDR_A_D18

DDR_A_D29
DDR_A_D28

DDR_A_DQS#3
DDR_A_DQS3

DDR_A_D26
DDR_A_D31

DDR_CKE1_DIMMA

DDR_A_MA11
DDR_A_MA6
DDR_A_MA4

DDR_A_MA2
DDR_A_MA0

DDR_A_BS#1
DDR_A_RAS#
DDR_CS0_DIMMA#

M_ODT0
DDR_A_MA13

DDR_A_D36
DDR_A_D33

DDR_A_DM4
DDR_A_D37

DDR_A_D32
DDR_A_D40

DDR_A_D44
DDR_A_DQS#5

DDR_A_DQS5
DDR_A_D47

DDR_A_D46
DDR_A_D48

DDR_A_D49
M_CLK_DDR1

M_CLK_DDR#1
DDR_A_DM6
DDR_A_D50DDR_A_D51

DDR_A_D54
DDR_A_D60

DDR_A_D57
DDR_A_DQS#7

DDR_A_DQS7
DDR_A_D62

DDR_A_D63

12

R453

R455

10K_0402_5%

10K_0402_5%

12

2.2U_0805_16V4Z
C363

1

2

M_CLK_DDR0 <7>
M_CLK_DDR#0 <7>

DDR_THERM# <7,14>

DDR_CKE1_DIMMA <7>

DDR_A_BS#1 <8>
DDR_A_RAS# <8>
DDR_CS0_DIMMA# <7>

M_ODT0 <7>

M_CLK_DDR1 <7>
M_CLK_DDR#1 <7>

1

0.1U_0402_16V4Z

1

2

V_DDR_MCH_REF <7,14,41>

C362

Top side

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/05/26 2006/07/26

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

2

Date: Sheet

Compal Electronics, Inc.

DDRII-SODIMM SLOT1

LA-2952P

13 46Wednesday, October 26, 2005

1

0.3

of

5

DDR_B_DQS#[0..7]<8>

DDR_B_D[0..63]<8>

DDR_B_DM[0..7]<8>
DDR_B_DQS[0..7]<8>
DDR_B_MA[0..13]<8>

D D

C C

B B

A A

Layout Note:
Place near JP34

+1.8V

2.2U_0805_16V4Z

2.2U_0805_16V4Z
C236

1

2

Layout Note:
Place one cap close to every 2 pullup
resistors terminated to +0.9V

+0.9V

0.1U_0402_16V4Z

1

2

C176

DDR_B_MA1
DDR_B_MA3

DDR_B_BS#0
DDR_B_MA10

DDR_B_MA0
DDR_B_BS#1

DDR_B_RAS#
DDR_CS2_DIMMB#

DDR_B_CAS#
DDR_B_WE#

DDR_CS3_DIMMB# M_ODT2
M_ODT3

0.1U_0402_16V4Z

1

2

1

2

C179

RP14

RP17

RP16

RP18

RP19

RP23

C265

0.1U_0402_16V4Z

1 4
2 3

1 4
2 3

1 4
2 3

1 4
2 3

1 4
2 3

2 3
1 4

5

2.2U_0805_16V4Z
C247

1

2

0.1U_0402_16V4Z

1

2

C186

56_0404_4P2R_5%

56_0404_4P2R_5%

56_0404_4P2R_5%

56_0404_4P2R_5%

56_0404_4P2R_5%

56_0404_4P2R_5%

1

2

C197

2.2U_0805_16V4Z

+0.9V

C159

1

2

0.1U_0402_16V4Z

1

2

C213

2.2U_0805_16V4Z
C164

1

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

2

C220

RP10 56_0404_4P2R_5%

14
23

RP11 56_0404_4P2R_5%

14
23

RP12 56_0404_4P2R_5%

14
23

RP13 56_0404_4P2R_5%

14
23

RP15 56_0404_4P2R_5%

14
23

RP21 56_0404_4P2R_5%

14
23

RP9

14
23

56_0404_4P2R_5%

0.1U_0402_16V4Z

0.1U_0402_16V4Z

C166

1

2

0.1U_0402_16V4Z

1

1

2

2

C183

C210

DDR_B_MA9
DDR_B_MA12

DDR_CKE3_DIMMB
DDR_B_MA11

DDR_B_MA5
DDR_B_MA8

DDR_B_MA7
DDR_B_MA6

DDR_B_MA4
DDR_B_MA2

DDR_B_MA13

DDR_B_BS#2
DDR_CKE2_DIMMB

0.1U_0402_16V4Z

C219

1

2

0.1U_0402_16V4Z

1

2

C199

0.1U_0402_16V4Z

C188

1

1

2

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

2

2

C173

Layout Note:
Place these resistor
closely JP10,all
trace length Max=1.5"

4

C218

4

C161

3

+1.8V

JP10

1

VREF

3

DDR_B_D0
DDR_B_D5

DDR_B_DQS#0
DDR_B_DQS0

DDR_B_D7
DDR_B_D3

DDR_B_D8
DDR_B_D9

DDR_B_DQS#1
DDR_B_DQS1

DDR_B_D10
DDR_B_D11

DDR_B_D20
DDR_B_DQS#2

DDR_B_DQS2
DDR_B_D22

DDR_B_D23
DDR_B_D24

DDR_B_D25
DDR_B_DM3

DDR_B_D30
DDR_B_D31

DDR_CKE2_DIMMB<7>

DDR_B_BS#2<8>

DDR_B_BS#0<8>

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

2

2

C177

C163

DDR_B_WE#<8>

DDR_B_CAS#<8>

DDR_CS3_DIMMB#<7>

M_ODT3<7>

ICH_SMBDATA<4,13,15,20,22,24>

ICH_SMBCLK<4,13,15,20,22,24>

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

DDR_CKE2_DIMMB

DDR_B_BS#2
DDR_B_MA12

DDR_B_MA9
DDR_B_MA8

DDR_B_MA5
DDR_B_MA3
DDR_B_MA1

DDR_B_MA10
DDR_B_BS#0
DDR_B_WE#

DDR_B_CAS#
DDR_CS3_DIMMB#

M_ODT3
DDR_B_D37

DDR_B_D36
DDR_B_DQS#4

DDR_B_DQS4
DDR_B_D35

DDR_B_D34
DDR_B_D40

DDR_B_D41
DDR_B_DM5
DDR_B_D42

DDR_B_D47
DDR_B_D48

DDR_B_D53

DDR_B_DQS#6
DDR_B_DQS6

DDR_B_D51
DDR_B_D50

DDR_B_D60
DDR_B_D61

DDR_B_DM7
DDR_B_D58

DDR_B_D59
ICH_SMBDATA

ICH_SMBCLK

+3VS

1

C301

0.1U_0402_16V4Z

2005/05/26 2006/07/26

2

Compal Secret Data

VSS

5

DQ0

7

DQ1

9

VSS

11

DQS0#

13

DQS0

15

VSS

17

DQ2

19

DQ3

21

VSS

23

DQ8

25

DQ9

27

VSS

29

DQS1#

31

DQS1

33

VSS

35

DQ10

37

DQ11

39

VSS

41

VSS

43

DQ16

45

DQ17

47

VSS

49

DQS2#

51

DQS2

53

VSS

55

DQ18

57

DQ19

59

VSS

61

DQ24

63

DQ25

65

VSS

67

DM3

69

NC

71

VSS

73

DQ26

75

DQ27

77

VSS

79

CKE0

81

VDD

83

NC

85

BA2

87

VDD

89

A12

91

A9

93

A8

95

VDD

97

A5

99

A3

101

A1

103

VDD

105

A10/AP

107

BA0

109

WE#

111

VDD

113

CAS#

115

NC/S1#

117

VDD

119

NC/ODT1

121

VSS

123

DQ32

125

DQ33

127

VSS

129

DQS4#

131

DQS4

133

VSS

135

DQ34

137

DQ35

139

VSS

141

DQ40

143

DQ41

145

VSS

147

DM5

149

VSS

151

DQ42

153

DQ43

155

VSS

157

DQ48

159

DQ49

161

VSS

163

NC,TEST

165

VSS

167

DQS6#

169

DQS6

171

VSS

173

DQ50

175

DQ51

177

VSS

179

DQ56

181

DQ57

183

VSS

185

DM7

187

VSS

189

DQ58

191

DQ59

193

VSS

195

SDA

197

SCL

199

VDDSPD

203

GND

FOX_ASOA426-M2RN-7F

SO-DIMM B
STANDARD

Bottom side

Deciphered Date

DQ12
DQ13

CK0#

DQ14
DQ15

DQ20
DQ21

DQ22
DQ23

DQ28
DQ29

DQS3#

DQS3
DQ30

DQ31

NC/CKE1

NC/A15
NC/A14

RAS#

ODT0

NC/A13

DQ36
DQ37

DQ38
DQ39

DQ44
DQ45

DQS5#

DQS5
DQ46

DQ47
DQ52

DQ53

CK1#

DQ54
DQ55

DQ60
DQ61

DQS7#

DQS7
DQ62

DQ63

GND

VSS
DQ4
DQ5
VSS
DM0
VSS
DQ6
DQ7
VSS

VSS
DM1
VSS
CK0

VSS

VSS

VSS

VSS
DM2

VSS

VSS

VSS

VSS

VSS
VDD

VDD

VDD

VDD

VDD

VDD
VSS

VSS
DM4
VSS

VSS

VSS

VSS

VSS

VSS
CK1

VSS
DM6
VSS

VSS

VSS

VSS

VSS

2

+1.8V

V_DDR_MCH_REF

2

DDR_B_D4

4

DDR_B_D1

6
8

DDR_B_DM0

10
12

DDR_B_D6

14

DDR_B_D2

16
18

DDR_B_D12

20

DDR_B_D13

22
24

DDR_B_DM1

26
28

M_CLK_DDR3

30

M_CLK_DDR#3

32
34

DDR_B_D14

36

DDR_B_D15

38
40

42

DDR_B_D16DDR_B_D21

44

DDR_B_D18

46
48
50

NC

A11

A7
A6

A4
A2

A0
BA1
S0#

NC

SA0
SA1

2

DDR_B_DM2

52
54

DDR_B_D17

56

DDR_B_D19

58
60

DDR_B_D26

62

DDR_B_D28

64
66

DDR_B_DQS#3

68

DDR_B_DQS3

70
72

DDR_B_D29

74

DDR_B_D27

76
78

DDR_CKE3_DIMMB

80
82
84
86
88

DDR_B_MA11

90

DDR_B_MA7

92

DDR_B_MA6

94
96

DDR_B_MA4

98

DDR_B_MA2

100

DDR_B_MA0

102
104

DDR_B_BS#1

106

DDR_B_RAS#

108

DDR_CS2_DIMMB#

110
112

M_ODT2

114

DDR_B_MA13

116
118
120
122

DDR_B_D33

124

DDR_B_D32

126
128

DDR_B_DM4

130
132

DDR_B_D38

134

DDR_B_D39

136
138

DDR_B_D44

140

DDR_B_D45

142
144

DDR_B_DQS#5

146

DDR_B_DQS5

148
150

DDR_B_D43

152

DDR_B_D46

154
156

DDR_B_D49

158

DDR_B_D52

160
162

M_CLK_DDR2

164

M_CLK_DDR#2

166
168

DDR_B_DM6

170
172

DDR_B_D54

174

DDR_B_D55

176
178

DDR_B_D56

180

DDR_B_D57

182
184

DDR_B_DQS#7

186

DDR_B_DQS7

188
190

DDR_B_D62

192

DDR_B_D63

194
196
198
200
204

R257

1 2

10K_0402_5%

12

10K_0402_5%

R254

Title

Size Document Number Rev

Date: Sheet

0.1U_0402_16V4Z

2.2U_0805_16V4Z

1

1

C89

2

2

M_CLK_DDR3 <7>
M_CLK_DDR#3 <7>

DDR_THERM# <7,13>

DDR_CKE3_DIMMB <7>

DDR_B_BS#1 <8>
DDR_B_RAS# <8>
DDR_CS2_DIMMB# <7>

M_ODT2 <7>

M_CLK_DDR2 <7>
M_CLK_DDR#2 <7>

+3VS

Compal Electronics, Inc.

DDRII-SODIMM SLOT2

LA-2952P

1

V_DDR_MCH_REF <7,13,41>

C90

1

0.3

of

14 46Wednesday, October 26, 2005

5

PCI

SRC

CPU

CLKSEL1

0

1

8.2K_0402_5%

FSA

0_0402_5%

CLK_Ra

0_0402_5%

CLK_Rb

8.2K_0402_5%

0_0402_5%

CLK_Rc

FSLA

CLKSEL0

Stuff

No Stuff

Stuff

No Stuff

Stuff

No Stuff

R1078

1 2

R1083

FSB

1 2

R1107

R1130

1 2

R1135

12

12

+VCCP

+VCCP

+VCCP

MHz

133

166

CLK_Ra

CLK_Rd

CLK_Rd

CLK_Ra

CLK_Rd

CLK_Ra
CLK_Re

R1074

@

56_0402_5%

CLK_Rd

1 2

1 2

R1079

1K_0402_5%

12

R1086
1K_0402_5%

R1098
1K_0402_5%

1 2

1 2

R1105

1K_0402_5%

12

R1113

@

0_0402_5%

CLK_Re

R1128
1K_0402_5%

1 2

1 2

R1131

1K_0402_5%

12

R1139

@

0_0402_5%

CLK_Rf

MHz

MHz

33.31

1000

100

33.3

CLK_Rc

CLK_Rb

CLK_Re

CLK_Rf

CLK_Rf

CLK_Re

CLK_Rc

CLK_Rb

CLK_Rf

CLK_Rc

CLK_Rb

MCH_CLKSEL0 <7> CLK_48M_CB<24>

MCH_CLKSEL1 <7>

+3VS

R1394 10K_0402_5%@

MCH_CLKSEL2 <7>

NOXDP@ : means just build when XDP function disable.
XDP@ : means just build when XDP function enable.

+3VS

+3VS

+3VS

+VCCP

+CK_VDD_DP

1

C1061

0.1U_0402_16V4Z@

2

CLK_14M_ICH<20>

CLK_DEBUG_PORT<24>

12

CLK_MCH_REF<7>
CLK_MCH_REF#<7>

CLK_PCI_SIO<28>

FSLC1FSLB

CLKSEL2

0

Table : ICS954306

D D

FSB Frequency Selet:

CPU Driven

(Default)

*

533MHz

667MHz

C C

CPU_BSEL0<5>

CPU_BSEL1<5>

B B

CLKREF1

CPU_BSEL2<5>

When this time, docking PCI express will not work.

+3VS

12

R1146

10K_0402_5%@

A A

CLK_ENABLE#

R1351

300_0402_5%

J29

NO SHORT PADS

12

12

5

LCD(Low)/SRC(High)
clock select

+3VS +3VS

12

R1108
10K_0402_5%

PCI_ICH

12

R1246

10K_0402_5%@

High:Pin18/19 = 100MHz

*

Low:Pin18/19 = 96MHz Low:Pin44/45 = CPUCLK2_ITP

4

1 2

R1066 0_0805_5%

1 2

R1067 0_0805_5%

R1389

1 2

0_0805_5%NOXDP@

R1390

1 2

0_0805_5%XDP@

0.1U_0402_16V4Z

CLKIREF

R1393

12

0_0402_5%@

0.1U_0402_16V4Z

CLK_48M_ICH<20>

H_STP_CPU#<20>

H_STP_PCI#<20>

CLK_ENABLE#<34,42>

CLK_PCI_ICH<18>

CLK_14M_KBC<30>

CLK_14M_SIO<28>

CLK_DEBUG_PORT PCI_MINI

CLK_PCI_EC<30>

CLK_PCI_TCG<29>

CLK_PCI_PCM<24>

PCI_EC

ICH_SMBDATA<4,13,14,20,22,24>

ICH_SMBCLK<4,13,14,20,22,24>

CLK_MCH_REF
CLK_MCH_REF#

Pin44/45 function select

High:Pin44/45 = CLKREQ

*

4

+CK_VDD_MAIN1

1

CLK_14M_ICH

C730
10U_0805_10V4Z

2

+CK_VDD_MAIN2

1

C737
10U_0805_10V4Z

2

+CK_VDD_DP

1

C1062
10U_0805_10V4Z

2

+CK_VDD_DP

1

C742

2
1

C743

2

CLK_48M_ICH
CLK_48M_CB

H_STP_CPU#
H_STP_PCI#

CLK_ENABLE#
CLK_PCI_ICH PCI_ICH

CLK_14M_KBC
CLK_14M_SIO

33_0402_5%DEBUG@

ICH_SMBDATA
ICH_SMBCLK

R1077 12_0402_5%

R1080 12_0402_5%

R1087 33_0402_5%

R1092

R111433_0402_5%

12

12

R1245

10K_0402_5%@

PCI_MINI

12

R1247
10K_0402_5%

+CK_VDD_MAIN1

CK_VDD_48

CK_VDD_REF

12
12

12

910_0402_1%

R1097

12

33_0402_5%

R1101 12_0402_5%

12
12

R1104 12_0402_5%

R1117

12

R110910K_0402_5%

12

R111033_0402_5%

12

R114033_0402_5%

12

R114133_0402_5%

12

R114833_0402_5%

12

R114933_0402_5%

12

PCI_CLK3

3

1

C731

0.01U_0402_16V7K

2

1

C738

0.1U_0402_16V4Z

2

1

C734

0.1U_0402_16V4Z

2

FSA
FSB
CLKREF1

CLKIREF

CLKREF0

PCI_CLK3
PCI_EC

PCI_CLK5
PCI_PCM

MCH_REF
MCH_REF#

1

C732

0.01U_0402_16V7K

2

1

C739

0.1U_0402_16V4Z

2

1

C735

0.1U_0402_16V4Z

2

U25

16

VDD

10

VDD48

5

VDDPCI

24

VDDSRC

33

VDDSATA

41

VDDSRC

50

VDDCPU

55

VDDREF

11

FSLA/USB_48MHz

15

FSLB/TEST_MODE

59

FSLC/TEST_SEL/REF1

46

IREF

61

CPU_STOP#

8

PCI/SRC_STOP#

9

Vtt_PwrGd#/PD

7

**SEL_LCDCLK#/PCICLK_F1

60

REF0/PCICLK1

62

*REQ_SEL/PCICLK2

1

*SEL_PCI1/PCICLK3

2

**SEL_SATA1/PCICLK4

3

**SEL_SATA2/PCICLK5

6

PCICLK6

54

SDATA

53

SCLK

13

DOTT_96MHz

14

DOTC_96MHz

4

GND

12

GND

17

GND

58

GND

47

GNDCPU

25

GNDSRC

40

GNDSRC

32

GNDSATA

ICS9LP306_TSSOP64

* Internal Pull-Up Resistor
** Internal Pull-Down Resistor

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

1

C733

0.01U_0402_16V7K

2

R1068

1 2

1_0805_1%

1 2

R1069

2.2_0805_1%

1

C736

0.1U_0402_16V4Z

2

LCDCLK_SST/SRCCLKT0

LCDCLK_SSC/SRCCLKC0

SATA1/SRCCLKT4
SATA1/SRCCLKC4

SATA2/SRCCLKT5
SATA2/SRCCLKC5

*CPUCLKT2_ITP/CLKREQC#

*CPUCLKC2_ITP/CLKREQD#

2005/05/26 2006/07/26

3

CK_VDD_REF

CK_VDD_48

SATACLKT
SATACLKC

CPUCLKT0
CPUCLKC0

CPUCLKT1
CPUCLKC1

*CLKREQA#

SRCCLKT2
SRCCLKC2

*CLKREQB#

SRCCLKT1
SRCCLKC1

SRCCLKT3
SRCCLKC3

SRCCLKT6
SRCCLKC6

SRCCLKT8
SRCCLKC8

SRCCLKT7
SRCCLKC7

Place crystal within
500 mils of CK410

C361

12

Y3

CLK_XTAL_IN

57

X1

CLK_XTAL_OUT

56

X2

28
29

CPU_BCLK

52

CPU_BCLK#

51

MCH_BCLK

49

MCH_BCLK#

48

CLKREQA#

64
18

MCH_SS#

19

PCIE_LOM

22

PCIE_LOM#

23

PCIE_SATA

30

PCIE_SATA# CLK_PCIE_SATA#

31

63
20

T92 PAD

21

T93 PAD

PCIE_DOCK CLK_PCIE_DOCK

26
27

PCIE_ICH

35

PCIE_ICH#

34

CPU_XDP

45

MCH_3GPLL

37

MCH_3GPLL#

36

43
42

CPU_XDP#

44

PCIE_MCARD

39

PCIE_MCARD#

38

14.31818MHZ_16P

C364 27P_0402_50V8J

R1352 0_0402_5%LP@

1 2

R1333 0_0402_5%LP@

1 2

1 2

R1070 33_0402_5%

1 2

R1072 33_0402_5%

1 2

R1075 33_0402_5%

1 2

R1081 33_0402_5%

CLKREQA# <22>

1 2

R1129 33_0402_5%

1 2

R1132 33_0402_5%

1 2

R1093 33_0402_5%

1 2

R1095 33_0402_5%

1 2

R1257 33_0402_5%

1 2

R1259 33_0402_5%

12

R1106 10K_0402_5%

1 2

R1144 33_0402_5%

1 2

R1145 33_0402_5%

1 2

R1123 33_0402_5%

1 2

R1126 33_0402_5%

R1120 10K_0402_5%NOXDP@

R1142 0_0402_5%NOXDP@

R1254 0_0402_5%NOXDP@

12

1 2

R1133 33_0402_5%XDP@

1 2

R1111 33_0402_5%

1 2

R1115 33_0402_5%

12

1 2

R1143 33_0402_5%XDP@

1 2

R1249 33_0402_5%

1 2

R1251 33_0402_5%

Compal Secret Data

Deciphered Date

2

12

27P_0402_50V8J

R1147 10K_0402_5%NOXDP@

Routing the trace at least 10mil

12

CLK_CPU_BCLK
CLK_CPU_BCLK#

CLK_MCH_BCLK
CLK_MCH_BCLK#

CLK_MCH_SSMCH_SS
CLK_MCH_SS#

CLK_PCIE_LOM
CLK_PCIE_LOM#

CLK_PCIE_SATA

CPPE#CLKREQB#

CLK_PCIE_DOCK#PCIE_DOCK#

CLK_PCIE_ICH
CLK_PCIE_ICH#

12

CLKREQC#
CLK_CPU_XDP
CLK_MCH_3GPLL
CLK_MCH_3GPLL#

12

CLKREQD#
CLK_CPU_XDP#
CLK_PCIE_MCARD
CLK_PCIE_MCARD#

2

1

C353
C356
C357
C372
C373
C374
C375
C376
C378
C379

C380

CLK_CPU_BCLK <4>
CLK_CPU_BCLK# <4>

CLK_MCH_BCLK <7>
CLK_MCH_BCLK# <7>

CLK_MCH_SS <7>
CLK_MCH_SS# <7>

CLK_PCIE_LOM <22>
CLK_PCIE_LOM# <22>

CLK_PCIE_SATA <19>
CLK_PCIE_SATA# <19>

CPPE# <18,32>

CLK_PCIE_DOCK <32>
CLK_PCIE_DOCK# <32>

CLK_PCIE_ICH <20>
CLK_PCIE_ICH# <20>

CLKREQC# <7>
CLK_CPU_XDP <4>
CLK_MCH_3GPLL <7>
CLK_MCH_3GPLL# <7>

CLKREQD# <24>
CLK_CPU_XDP# <4>
CLK_PCIE_MCARD <24>
CLK_PCIE_MCARD# <24>

CLK_48M_ICH

12

5P_0402_50V8C@

CLK_48M_CB

12

5P_0402_50V8C@

CLK_14M_ICH

12

5P_0402_50V8C@

CLK_PCI_ICH

12

5P_0402_50V8C@

CLK_14M_KBC

12

5P_0402_50V8C@

CLK_14M_SIO

12

5P_0402_50V8C@

CLK_PCI_EC

12

5P_0402_50V8C@

CLK_PCI_TCG

12

5P_0402_50V8C@

CLK_PCI_PCM

12

5P_0402_50V8C@

CLK_PCI_SIO

12

5P_0402_50V8C@

CLK_DEBUG_PORT

12

5P_0402_50V8C@

+3VS

+3VS

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

Place close to U25

Clock generator

LA-2952P

1

0.3

of

15 46Wednesday, October 26, 2005

A

B

C

D

E

+5VS

D18

2 1

21

CH491D_SC59

0.1U_0402_16V4Z

RED_R

GREEN_R

BLUE_R

C174

C178

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

28

DVDD12DVDD

AVDD_PLL

DGND7DGND30AGND31AGND39AGND45TGND18TGND24AGND_PLL

PAD

49

1

C315

2

2.2K_0402_5%

D_DDCDATA

D_DDCCLK

C150

0.1U_0402_16V4Z

21

TVDD15TVDD

AVDD36AVDD42AVDD

6

48

SC_PROM
SD_PROM

34

CRT Connector

BLUE<32>

R545

1 2

0_0603_5%

R546

1 2

0_0603_5%

5P_0402_50V8C@

PEG_RXP1<9>
PEG_RXN1<9>

GREEN<32>

C351

RED<32>

1

2

1.2K_0402_1%

R542

1 2

0_0603_5%

R543

1 2

0_0603_5%

C313

5P_0402_50V8C

@

1

1

2

2

1

C352

5P_0402_50V8C@

2

+2.5VS

12

R497

AS

W=20 mils

C1043
C1042

SDVOB_R+<9>
SDVOB_R-<9>

SDVOB_G+<9>
SDVOB_G-<9>

SDVOB_B+<9>
SDVOB_B-<9>

SDVOB_CLK+<9>
SDVOB_CLK-<9>

PLT_RST#<7,18,19,20,22,24,30>

12

R103

R114

10K_0402_5%

R544

1 2

0_0603_5%

C314

1

5P_0402_50V8C

@

C310

2

5P_0402_50V8C

@

DVI Transnitter

10K_0402_5%

0.1U_0402_16V4Z<BOM Structure>

SDVOB_INT+
SDVOB_INT-

0.1U_0402_16V4Z

AS
PLT_RST#

DVI_VSWING

12

R498

1 2

1 1

+5VS

1

5

1 2

1 2

R54 51K_0402_5%

P

A2Y

G

3

C_HSYNC<9>

C_VSYNC<9>

2 2

Place close to docking connector

R53 51K_0402_5%

+5VS

C359

1 2

0.1U_0402_16V4Z

U33
SN74AHCT1G125GW_SOT353-5

HSYNC_G_A D_HSYNC

4

OE#

1

5

P

OE#

A2Y

G

U54
SN74AHCT1G125GW_SOT353-5

3

C370

1 2

0.1U_0402_16V4Z

VSYNC_G_A D_VSYNC

4

TV-Out Connector

3 3

Place close to JP1

D5
DAN217_SC59@

2

D1
DAN217_SC59@

1

3

SUYIN_33007SR-07T1-C

D3
DAN217_SC59@

1

2

3

R547

LUMA<9,32>
CRMA<9,32>
COMP<9,32>

4 4

R548
R549

1 2
1 2
1 2

0_0603_5%
0_0603_5%
0_0603_5%

TV_LUMA
TV_CRMA
TV_COMP

+3VS

1

2

3

JP1

1
2
3
4
5
6
7

1.1A_6VDC_FUSE

D_HSYNC <32>

D_VSYNC <32>

D_DDCDATA<32>

D_DDCCLK<32>

32
33

37
38

40
41

43
44

46
47

3
2

25
27

26

10K_0402_5%

F1

DVI_AVDD_3V
DVI_DVDD_2.5V

U11

SDVOB_INT+
SDVOB_INT-

SDVOB_R+
SDVOB_R-

SDVOB_G+
SDVOB_G-

SDVOB_B+
SDVOB_B-

SDVOB_CLK+
SDVOB_CLK-

AS
RESET#
VSWING

ATPG
SCEN

+CRTVDD+RCRT_VCC

W=40mils

JP2

6

11

1
7

12

2
8

13

3
9

14

4
10
15

5

SUYIN_070912FR015S207CR

+CRTVDD +CRTVDD

12

R162

DVI_DVDD_2.5V

C141

C142

0.1U_0402_16V4Z

DVI_DVDD_2.5V

13

TLC#

14

TLC

16

TDC0#

17

TDC0

19

TDC1#

20

TDC1

22

TDC2#

23

TDC2

29

HPDET

11

SC_DDC

10

SD_DDC

9
8

5

SPD

4

SPC

NC

NC

CH7307C_LQFP48

35

16
17

12

R183

2.2K_0402_5%

Q46
BSS138_SOT23

0.1U_0402_16V4Z

DVI_DETECT

SDVO_SDAT
SDVO_SCLK

2

G

1 3

D

1 3

Q52

D

BSS138_SOT23

1

C140
10U_0805_10V4Z

2

BLUE_R
GREEN_R
RED_R

+3VS

R2

R4

1 2

2.2K_0402_5%

S

2

G

S

DVI_CLK <32>
DVI_DAT <32>

SDVO_SDAT <9>
SDVO_SCLK <9>

1

D4

DAN217_SC59

@

2

3

2

1 2

2.2K_0402_5%

+2.5VS +3VS

C371

0.1U_0402_16V4Z

DVI_CLK- <32>
DVI_CLK+ <32>
DVI_TX0- <32>
DVI_TX0+ <32>
DVI_TX1- <32>
DVI_TX1+ <32>
DVI_TX2- <32>
DVI_TX2+ <32>

DVI_DETECT <32>

SDVO_SDAT
SDVO_SCLK

DVI_AVDD_3V

C358

0.1U_0402_16V4Z

R143 5.6K_0402_5%
R142 5.6K_0402_5%

1

D19

3

1 2
1 2

@

1

D20

DAN217_SC59

2

3

1

C368

2

0.1U_0402_16V4Z

DAN217_SC59@

C369
10U_0805_10V4Z

+CRTVDD

C_DDCDATA <9>

C_DDCCLK <9>

+2.5VS

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2005/05/26 2006/07/26

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

D

Date: Sheet

Compal Electronics, Inc.

CRT & TVout Connector

LA-2952P

16 46Wednesday, October 26, 2005

E

0.3

of

5

4

3

2

1

JP35

B+_LCD

1 2

C586 0.1U_0603_50V4Z

1 2

C587 68P_0402_50V8J

40

40

39

39

38

38

37

37

36

36

35

35

34

34

33

33

32

32

31

31

30

30

29

29

28

28

27

27

26

26

25

25

24

24

23

23

22

22

21

21

20

20

19

19

18

18

17

17

16

16

15

15

14

14

13

13

12

12

11

11

10

10

9

9

8

8

7

7

6

6

5

5

4

4

3

3

2

2

1

1

L76 KC FBM-L11-201209-221LMA30T_0805 @
L62 KC FBM-L11-201209-221LMA30T_0805

+3VS

LCDVDD

12
12

+5VS_INV

ALS_EN <18>

LCD_CLK <9>
LCD_DAT <9>

TXCLK_U+ <9>
TXCLK_U- <9>

TXOUT_U2+ <9>
TXOUT_U2- <9>

TXOUT_U1+ <9>
TXOUT_U1- <9>

TXOUT_U0+ <9>
TXOUT_U0- <9>

TXOUT_L0- <9>
TXOUT_L0+ <9>

TXOUT_L1- <9>
TXOUT_L1+ <9>

TXOUT_L2- <9>
TXOUT_L2+ <9>

TXCLK_L- <9>
TXCLK_L+ <9>

R509

2.2K_0402_5%

B+

BKLT_CTL <9>

12

LCD POWER CIRCUIT

LCDVDD

R19

100_0402_1%

D

Q5

RHU002N06_SOT323

ENAVDD<9>

S

LID_SW#<20,31>

ENABLT<9>

Q8

AO3413_SOT23

D

S

1

C29

2

Q53
DTA114YKA_SC59

47K

2

G

1 3

G

2

C31

4.7U_0805_10V4Z

13

10K

2

13

D

Q36
BSS138_SOT23

S

R12

1 2

1M_0402_5%

C28

1 2

0.047U_0402_16V7K

+5VS_INV

12

13

2

G

2

LID_SW#

13

R474

1 2

47K_0402_5%

Q6
DTC124EK_SC59

+3VS

U43A
SN74LVC08APW_TSSOP14

14

1

P

A

2

B

G

7

100K_0402_5%

R501

1 2

100K_0402_5%

0.1U_0402_16V4Z

+5VS

3

O

1

2

R360

1 2

+3VALWLCDVDD

1

C20

4.7U_0805_10V4Z@

2

LVDS CONN

D D

C C

ACES_88316-4000

B B

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/05/26 2006/07/26

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

2

Date: Sheet

Compal Electronics, Inc.

LCD CONN.

LA-2952P

17 46Wednesday, October 26, 2005

1

0.3

of

5

4

3

2

1

D D

C C

B B

+3VS

R1041 8.2K_0402_5%

1 2

R1042 8.2K_0402_5%

1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2

1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2

R1043 8.2K_0402_5%
R1044 8.2K_0402_5%
R1045 8.2K_0402_5%
R1046 8.2K_0402_5%
R1047 8.2K_0402_5%
R1048 8.2K_0402_5%
R1049 8.2K_0402_5%
R1050 8.2K_0402_5%

+3VS

R1052 8.2K_0402_5%
R1053 8.2K_0402_5%
R1054 8.2K_0402_5%
R1055 8.2K_0402_5%
R1056 8.2K_0402_5%
R1058 8.2K_0402_5%
R1059 8.2K_0402_5%
R1060 8.2K_0402_5%
R1061 8.2K_0402_5%
R1062 8.2K_0402_5%
R1063 8.2K_0402_5%
R1064 8.2K_0402_5%
R1262 8.2K_0402_5%@

PCI_DEVSEL#
PCI_STOP#
PCI_TRDY#
PCI_FRAME#
PCI_PLOCK#
PCI_IRDY#
PCI_SERR#
PCI_PERR#
PCI_REQ4#
PCI_REQ3#

PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#
PCI_PIRQE#
PCI_PIRQF#
PCI_PIRQG#
PCI_PIRQH#
PCI_REQ0#
PCI_REQ1#
PCI_REQ2#
CPPE#
IDE_RESET#

PCI_AD[0..31]<24>

PCI_PIRQC#<24>
PCI_PIRQD#<24>

PCI_AD0
PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD6
PCI_AD7
PCI_AD8
PCI_AD9
PCI_AD10
PCI_AD11
PCI_AD12
PCI_AD13
PCI_AD14
PCI_AD15
PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20
PCI_AD21
PCI_AD22
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30
PCI_AD31

PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#

U26B

E18

AD0

C18

AD1

A16

AD2

F18

AD3

E16

AD4

A18

AD5

E17

AD6

A17

AD7

A15

AD8

C14

AD9

E14

AD10

D14

AD11

B12

AD12

C13

AD13

G15

AD14

G13

AD15

E12

AD16

C11

AD17

D11

AD18

A11

AD19

A10

AD20

F11

AD21

F10

AD22

E9

AD23

D9

AD24

B9

AD25

A8

AD26

A6

AD27

C7

AD28

B6

AD29

E6

AD30

D6

AD31

Interrupt I/F

A3

PIRQA#

B4

PIRQB#

C5

PIRQC#

B5

PIRQD#

AE5

RSVD[1]

AD5

RSVD[2]

AG4

RSVD[3]

AH4

RSVD[4]

AD9

RSVD[5]

ICH7_BGA652~D

PCI

REQ4# / GPIO22
GNT4# / GPIO48

GPIO1 / REQ5#

GPIO17 / GNT5#

GPIO2 / PIRQE#
GPIO3 / PIRQF#
GPIO4 / PIRQG#
GPIO5 / PIRQH#

MISC

MCH_SYNC#

REQ0#

GNT0#

REQ1#

GNT1#

REQ2#

GNT2#

REQ3#

GNT3#

C/BE0#
C/BE1#
C/BE2#
C/BE3#

IRDY#

PAR

PCIRST#

DEVSEL#

PERR#

PLOCK#

SERR#

STOP#
TRDY#

FRAME#

PLTRST#

PCICLK

PME#

RSVD[6]
RSVD[7]
RSVD[8]
RSVD[9]

D7
E7
C16
D16
C17
D17
E13
F13
A13
A14
C8
D8

B15
C12
D12
C15

A7
E10
B18
A12
C9
E11
B10
F15
F14
F16

C26
A9
B19

G8
F7
F8
G7

AE9
AG8
AH8
F21
AH20

PCI_REQ0#
PCI_GNT0#
PCI_REQ1#

PCI_REQ2#
PCI_GNT2#
PCI_REQ3#

PCI_REQ4#
IDE_RESET#
CPPE#
ALS_EN#

PCI_CBE#0
PCI_CBE#1
PCI_CBE#2
PCI_CBE#3

PCI_IRDY#
PCI_PAR
PCI_PCIRST#
PCI_DEVSEL#
PCI_PERR#
PCI_PLOCK#
PCI_SERR#
PCI_STOP#
PCI_TRDY#

PCI_FRAME#

PCI_PLTRST#
CLK_PCI_ICH
PCI_PME#

PCI_PIRQE#
PCI_PIRQF#
PCI_PIRQG#
PCI_PIRQH#

PCI_REQ0#
PCI_GNT0#

PCI_REQ2# <24>
PCI_GNT2# <24>

IDE_RESET# <19>

CPPE# <15,32>

PCI_CBE#0 <24>
PCI_CBE#1 <24>
PCI_CBE#2 <24>
PCI_CBE#3 <24>

PCI_IRDY# <24>
PCI_PAR <24>

PCI_DEVSEL# <24>
PCI_PERR# <24>

PCI_SERR# <24,30>
PCI_STOP# <24>
PCI_TRDY# <24>
PCI_FRAME# <24>

CLK_PCI_ICH <15>
PCI_PME#

PCI_PIRQE# <24>
PCI_PIRQG# <24>

12

0_0402_5%

R1388

MCH_ICH_SYNC# <7>

PCI_PCIRST#

PCI_PLTRST#

ACCEL_INT <24>

Place closely pin A9

ALS_EN#

R1051
0_0402_5%

R1057
0_0402_5%

CLK_PCI_ICH

10_0402_5% @

8.2P_0402_50V@

2

G

1
2

12

1
2

12

R1065

C729

+5VS

R433
330_0402_5%

1 2

ALS_EN

13

D

S

RHU002N06_SOT323

+3VS

5

U56

P

B

Y

A

G

TC7SH08FU_SSOP5@

3

+3VS

5

U59

P

B

Y

A

G

TC7SH08FU_SSOP5@

3

1 2
1

2

ALS_EN <17>

Q45

PCI_RST#

4

PLT_RST#

4

PCI_RST# <19,24>

PLT_RST# <7,16,19,20,22,24,30>

Boot BIOS destination

LPC@SPI@

ALS_EN#

12

R1290
1K_0402_5%

BIOS_SEL1 Short Open

A A

The pad must be placed on PCB easily

L

contact space for BIOS team setting.

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/05/26 2006/07/26

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

2

Date: Sheet

Compal Electronics, Inc.

ICH7-M(1/4)

LA-2952P

18 46Wednesday, October 26, 2005

1

0.3

of

5

C516

1 2

18P_0402_50V8J

Y4

1

GND4IN

2

C721

10P_0402_25V8K@

GND3OUT

1 2

R1026

1 2

1M_0402_5%

12

AC97_SDIN0<25>
AC97_SDIN1<31>

IDE_LED# <24>

CLK_PCIE_SATA#<15>
CLK_PCIE_SATA<15>

C528

18P_0402_50V8J

R1028

1 2

10_0402_5%@

1 2
1 2
1 2

1 2

JP45

32.768KHZ_1TJT125DN1A103L

D D

C C

R90

10K_0402_5%

+3VALW

B B

+RTCVCC

+5VS +3VS

12

MB2_LED#

+RTCVCC

12

R1263
332K_0402_1%@

R230

1 2

20K_0402_5%

CMOS_CLR1

1 2

NO SHORT PADS

C287

1U_0603_10V4Z

1 2

AC97_BITCLK_MDC<31>

AC97_BITCLK_CODEC<25>

AC97_SYNC_CODEC<25>

AC97_RST#_CODEC<25>

AC97_SDOUT_CODEC<25>

AC97_SDOUT_MDC<31>

12

R88
10K_0402_5%

D16 CH751H-40_SC76

D15 CH751H-40_SC76

12

R1240
332K_0402_1%

12

R1241

0_0402_5%@

21

21

ICH_INTVRMEN

+RTCVCC

AC97_SYNC_MDC<31>

AC97_RST#_MDC<31>

IDE_LED#SATA_LED#

+3VS

SATA CONN

C955 3900P_0402_50V7K

1 2

SATA_TXP0_C SATA_TXP0

C956 3900P_0402_50V7K

1 2

SATA_TXN0SATA_TXN0_C

Near ICH7(U26) side.

A A

SATA_RXN0_C

SATA_RXP0_C

C957 3900P_0402_50V7K

1 2

C958 3900P_0402_50V7K

1 2

SATA_RXN0

SATA_RXP0

26

Near Device(JP45) side.

5

R131433_0402_5%
R37133_0402_5%

R40233_0402_5%

R37633_0402_5%

12

R131533_0402_5%

R102933_0402_5%

12

R36733_0402_5%

12

R40533_0402_5%

12

12
12

1 2

24.9_0402_1%

R10334.7K_0402_5%
R10348.2K_0402_5%

GND

GND

GND

GND
GND
GND

GND
GND

4

ICH_RTCX1

12

R432
10M_0402_5%

ICH_RTCX2
ICH_RTCRST#
ICH_INTVRMEN

SM_INTRUDER#

AC97_BITCLK
AC97_SYNC

AC97_RST#
AC97_SDIN0

AC97_SDIN1

AC97_SDOUT

SATA_LED#

SATA_RXN0_C
SATA_RXP0_C
SATA_TXN0_C
SATA_TXP0_C

CLK_PCIE_SATA#
CLK_PCIE_SATA

R1256

PD_IORDY
PD_IRQ
PD_DACK#
PD_IOW#
PD_IOR#

S1
S2

RX+

S3

RX-

S4
S5

TX-

S6

TX+

S7

P1

3.3V

P2

3.3V

P3

3.3V

P4
P5
P6
P7

5V

P8

5V

P9

5V

P10
P11

Rsv

P12
P13

12V

P14

12V

P15

12V

boss23boss24GND25GND

OCTEK_SAT-22DD1G

4

AB1
AB2

AA3

W4

Y5

W1

Y1
Y2

W3

V3
U3
U5

V4
T5

U7
V6
V7

U1
R6

R5
T2

T3
T1

T4

AF18

AF3

AE3
AG2
AH2

AF7

AE7
AG6
AH6

AF1

AE1

AH10
AG10

AG16
AH16
AF16
AH15
AF15

SATA_TXP0
SATA_TXN0

SATA_RXN0
SATA_RXP0

C629

10U_0805_10V4Z

U26A

RTXC1
RTCX2

RTCRST#
INTVRMEN

INTRUDER#

EE_CS
EE_SHCLK
EE_DOUT
EE_DIN

LAN_CLK
LAN_RSTSYNC
LAN_RXD0

LAN_RXD1
LAN_RXD2

LAN_TXD0
LAN_TXD1
LAN_TXD2

ACZ_BCLK
ACZ_SYNC

ACZ_RST#
ACZ_SDIN0

ACZ_SDIN1
ACZ_SDIN2

ACZ_SDOUT

SATALED#

SATA0RXN
SATA0RXP
SATA0TXN
SATA0TXP

SATA2RXN
SATA2RXP
SATA2TXN
SATA2TXP

SATA_CLKN
SATA_CLKP

SATARBIASN
SATARBIASP

IORDY
IDEIRQ
DDACK#
DIOW#
DIOR#

ICH7_BGA652~D

1

2

0.1U_0402_16V4Z

RTC

GPIO49 / CPUPWRGD

1

C630

2

LAD0
LAD1
LAD2
LAD3

LDRQ0#

LPCCPU

LDRQ1# / GPIO23

LFRAME#

LAN

A20GATE

A20M#

CPUSLP#

TP1 / DPRSTP#

TP2 / DPSLP#

FERR#

IGNNE#

INIT3_3V#

INIT#
INTR

AC-97/AZALIA

RCIN#

SMI#

STPCLK#

THERMTRIP#

DCS1#
DCS3#

SATA

DD10
DD11
DD12
DD13

IDE

DD14
DD15

DDREQ

+RTCVCC

1

C665
1U_0603_10V4Z

2

1

C631

0.1U_0402_16V4Z

2

3

+3VS

IDE_RESET#<18>

PLT_RST_B#

R1036 0_0402_5%

LPC_AD0

AA6

LPC_AD1

AB5

LPC_AD2

AC4

LPC_AD3

Y6

LPC_DRQ#0

AC3
AA5

LPC_FRAME#

AB3

GATEA20

AE22

H_A20M#

AH28

H_CPUSLP_R#

AG27

DPRSLP#

AF24

DPSLP#

AH25

H_FERR#

AG26

H_PWRGOOD

AG24

H_IGNNE#

AG22

FWH_INIT#

AG21

H_INIT#

AF22

H_INTR

AF25

KB_RST#

AG23

H_SMI#

AF23

H_NMI

AH24

NMI

AH22

R1408 0_0402_5%

THRMTRIP_ICH#

AF26

PD_A0

AH17

DA0
DA1
DA2

DD0
DD1
DD2
DD3
DD4
DD5
DD6
DD7
DD8
DD9

AE17
AF17

AE16
AD16

AB15
AE14
AG13
AF13
AD14
AC13
AD12
AC12
AE12
AF12
AB13
AC14
AF14
AH13
AH14
AC15

AE15

R133

1 2

100_0402_5%

+5VS

PD_A1
PD_A2

PD_CS#1
PD_CS#3

PD_D0
PD_D1
PD_D2
PD_D3
PD_D4
PD_D5
PD_D6
PD_D7
PD_D8
PD_D9
PD_D10
PD_D11
PD_D12
PD_D13
PD_D14
PD_D15

PD_DREQ

D14

1

DAN202U_SC70

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

LPC_AD[0..3] <24,28,29,30>

PCI_RST#<18,24>

R1025 0_0402_5%
R1035 0_0402_5%
R1027 56_0402_5%

R1244 10K_0402_5%

H_STPCLK#

12

R1037 0_0402_5%@

LPC_DRQ#0 <28>

T88

PAD

LPC_FRAME# <24,28,29,30>

R1243 10K_0402_5%

12

GATEA20 <30>
H_A20M# <4>

T86

PAD

12
12
12

H_FERR# <4>
H_PWRGOOD <4>
H_IGNNE# <4>

FWH_INIT#
H_INIT# <4>
H_INTR <4>

12

KB_RST# <30>
H_SMI# <4>

H_NMI <4>

H_STPCLK# <4>

1 2

R1031 24.9_0402_1%

Place close to ICH7

+3VL

3

RTC_R

1 2

2

R976 1K_0402_5%

W=20mils

2005/05/26 2006/07/26

PLT_RST#<7,16,18,20,22,24,30>

12

12

+3VS

H_DPRSTP# <4,42>
H_DPSLP# <4>

+VCCP

+VCCP

+3VS

12

R1030
56_0402_5%

JP42
ACES_85205-0200

1

2

-+

RTC

SN74LVC08APW_TSSOP14

Compal Secret Data

14

12

P

A

13

B

G

7

H_THERMTRIP# <4,7>

MBAY_DET#<20>

MB_PWR<20>

+3VS

14

4

P

A

5

B

G

U43B

7

Deciphered Date

2

C641

1 2

0.1U_0402_16V4Z
R301

11

O

U43D

SN74LVC08APW_TSSOP14

+3VS

R72

4.7K_0402_5%

C628

0.1U_0402_16V4Z

+5VS

R83

470K_0402_5%

2

G

Q38

RHU002N06_SOT323

1

C646

0.1U_0402_16V4Z

2

PLT_RST_B#

6

O

2

ODD_RST#

12

33_0402_5%

12

MBAY_DET#

1

2

12

13

D

S

55
56
57
58

JAE_WM2M054JKB

10U_0805_10V4Z
R93

1 2

220K_0402_5%

2

G

Q39

RHU002N06_SOT323

PLT_RST_B# <24,28,29>

1

Multi Bay II connector

JP5

1

1

2

2

3

3

4

4

ODD_RST#

5

5

PD_D8

6

6

PD_D7

7

7

PD_D9

8

8

PD_D6

9

9

PD_D10

10

10

PD_D5

11

11

PD_D11

12

12

PD_D4

13

13

PD_D12

14

14

PD_D3

15

15

PD_D13

16

16

PD_D2

17

17

PD_D14

18

18

PD_D1

19

19

PD_D15

20

20

PD_D0

21

21

PD_DREQ

22

22

23

23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51

GND

52

GND

53

GND

54

GND

+5VS

1

C640

2

1

C633

0.1U_0402_16V4Z

2

+5VS_MB

12

R98
100_0402_5%

13

D

S

PCB-MB

Title

Size Document Number Rev

Date: Sheet

PD_IOR#

24

PD_IOW#

25
26

PD_IORDY

27

PD_DACK#

28

PD_IRQ

29
30

PD_A1

31
32

PD_A0

33

PD_A2

34

PD_CS#1

35

PD_CS#3

36

MB2_LED#

37
38
39
40
41
42
43
44

MBAY_DET#

45
46
47
48
49

R1032

50

0_0402_5%

51
52
53
54

Q92
AO4407_SO8

1
2
3 6

4

12

8
7

5

10U_0805_10V4Z

+5VS_MB

+5VS_MB

+5VS_MB

1

2

C624

1

C626

0.1U_0402_16V4Z

2

0.1U_0402_16V4Z

Place close to JP37

ZZZ

ZZZ

Audio-wire

Compal Electronics, Inc.

ICH7-M(2/4)

LA-2952P

19 46Wednesday, October 26, 2005

1

1

C625

2

1

C627

0.1U_0402_16V4Z

2

of

0.3

5

4

3

2

1

Place closely pin B2 Place closely pin AC1

+3VALW

R1001

R1000

10K_0402_5%

1 2

1 2

D

13

Q24

G

RHU002N06_SOT323@

2

+5VS

PM_POK<7,30>

ICH_SMBCLK
ICH_SMBDATA

ICH_SMB_DATAICH_SMBDATA

LP_EN#<22>

R532

1K_0402_5%

1 2

+3VALW

ICH_PCIE_WAKE#<22,24>

R1374 0_0402_5%

1 2

R1373 0_0402_5%@

1 2

PCIE_RXN1<22>
PCIE_RXP1<22>
PCIE_TXN1<22>

PCIE_TXP1<22>

PCIE_RXN2<24>
PCIE_RXP2<24>
PCIE_TXN2<24>

PCIE_TXP2<24>

PCIE_RXN4<32>
PCIE_RXP4<32>
PCIE_TXN4<32>

PCIE_TXP4<32>

+3VALW

R1284

SPI_CS#

1 2

R1285

1 2

R1286

SPI_SO

1 2

L

R1284,R1285 and R1286 should
be placed close to U26.

4

10K_0402_5%

SPI_SI

10K_0402_5%

10K_0402_5%

D D

R206

2.2K_0402_5%@

ICH_SMBDATA<4,13,14,15,22,24>

ICH_SMBCLK<4,13,14,15,22,24>

+3VS

10K_0402_5%@

R993

1 2

10K_0402_5%

R994

1 2

C C

+3VALW

B B

A A

R999

R1004

R1005

R1006

R1009

8.2K_0402_5%

1 2

10K_0402_5%

1 2

10K_0402_5%

1 2

10K_0402_5%

1 2

10K_0402_5%

1 2

10K_0402_5%

PREP#<23,25,32>

ICH_SMBCLK ICH_SMB_CLK

THERM_SCI#

SIRQ

PM_CLKRUN#

LINKALERT#

XDP_DBRESET# PWROK_ICH7

OCP#

LID_SW#

V_3P3_LAN +3VS

12

R1007

D57

CH751H-40_SC76

5

+3VS

12

21

12

R204

2.2K_0402_5%@

S

G

12

R1008
10K_0402_5%

10K_0402_5%

Q23

RHU002N06_SOT323@

D

13

S

2

VGATE_INTEL<7,34,42>

ISO_PREP#PREP#

2.2K_0402_5%

R1319

0_0402_5%

1 2

0_0402_5%

1 2

R1320

+3VALW

R1384 0_0402_5%

BT_OFF

R1385 0_0402_5%@

+3VALW

R1292/R1293 should be placed

L

less than 100 mils from U26.

SPI_CLK<29>
SPI_CS#<29>

SPI_SI<29>

SPI_SO<29>

+3VALW

12

12

R233

R213

2.2K_0402_5%

ICH_SMB_CLK
ICH_SMB_DATA
LINKALERT#
ICH_SMLINK0
ICH_SMLINK1

R1003

1 2

C7080.1U_0402_16V4Z

12

C7090.1U_0402_16V4Z

12

C7100.1U_0402_16V4Z

12

C7110.1U_0402_16V4Z

12

C9520.1U_0402_16V4Z

12

C9530.1U_0402_16V4Z

12

R1292

1 2

R1293

1 2

ICH_RI#
SB_SPKR

LPC_PD#
XDP_DBRESET#

PM_BMBUSY#
OCP#
H_STP_PCI#

H_STP_CPU#

PM_CLKRUN#
FWH_WP#

FWH_TBL#
ICH_PCIE_WAKE#

SIRQ
THERM_SCI#

PWROK_ICH7

RUNSCI_EC#
ISO_PREP#

PCIE_RXN1
PCIE_RXP1
PCIE_C_TXN1
PCIE_C_TXP1

PCIE_RXN2
PCIE_RXP2
PCIE_C_TXN2
PCIE_C_TXP2

PCIE_RXN4
PCIE_RXP4
PCIE_C_TXN4
PCIE_C_TXP4

47_0402_5%

47_0402_5%

USB_OC#0
USB_OC#1
USB_OC#2
USB_OC#3
USB_OC#4
USB_OC#5
USB_OC#6
USB_OC#7

1 2

8.2K_0402_5%

SB_SPKR<25>

LPC_PD#<29,30>

XDP_DBRESET#<4>

PM_BMBUSY#<7>

OCP#<4,43>

H_STP_PCI#<15>

H_STP_CPU#<15>
WXMIT_OFF#<24>

1 2
1 2

PM_CLKRUN#<24,28,29,30>

FWH_WP#

FWH_TBL#

SIRQ<24,28,29,30>

THERM_SCI#<4>

RUNSCI_EC#<30>

ISO_PREP#<32>

R1322 10K_0402_5%

SPI_CLK
SPI_CS#

SPI_SI
SPI_SO

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

R213,R233 change from 2.2Kohm to

L

10Kohm when Q23,Q24,R206,R204 stuffed.

U26C

C22

SMBCLK

GPIO27

T90PAD

Issued Date

B22

SMBDATA

A26

LINKALERT#

B25

SMLINK0

A25

SMLINK1

A28

RI#

A19

SPKR

A27

SUS_STAT#

A22

SYS_RST#

AB18

GPIO0 / BM_BUSY#

B23

GPIO11 / SMBALERT#

AC20

GPIO18 / STPPCI#

AF21

GPIO20 / STPCPU#

A21

GPIO26

B21

GPIO27

E23

GPIO28

AG18

GPIO32 / CLKRUN#

AC19

GPIO33 / AZ_DOCK_EN#

U2

GPIO34 / AZ_DOCK_RST#

F20

WAKE#

AH21

SERIRQ

AF20

THRM#

AD22

VRMPWRGD

AC21

GPIO6

AC18

GPIO7

E21

GPIO8

ICH7_BGA652~D

U26D

F26

PERn1

F25

PERp1

E28

PETn1

E27

PETp1

H26

PERn2

H25

PERp2

G28

PETn2

G27

PETp2

K26

PERn3

K25

PERp3

J28

PETn3

J27

PETp3

M26

PERn4

M25

PERp4

L28

PETn4

L27

PETp4

P26

PERn5

P25

PERp5

N28

PETn5

N27

PETp5

T25

PERn6

T24

PERp6

R28

PETn6

R27

PETp6

R2

SPI_CLK

P6

SPI_CS#

P1

SPI_ARB

P5

SPI_MOSI

P2

SPI_MISO

D3

OC0#

C4

OC1#

D5

OC2#

D4

OC3#

E5

OC4#

C3

OC5# / GPIO29

A2

OC6# / GPIO30

B3

OC7# / GPIO31

ICH7_BGA652~D

3

SMB

SYS

GPIO

GPIO

PCI-EXPRESS

DIRECT MEDIA INTERFACE

DMI_ZCOMP

DMI_IRCOMP

SPI

USB

USBRBIAS#

2005/05/26 2006/07/26

GPIO21 / SATA0GP
GPIO19 / SATA1GP
GPIO36 / SATA2GP
GPIO37 / SATA3GP

SATA

GPIO

Clocks

GPIO16 / DPRSLPVR

TP0 / BATLOW#

POWER MGT

GPIO35 / SATAREQ#

V26

DMI0RXN

V25

DMI0RXP

U28

DMI0TXN

U27

DMI0TXP

Y26

DMI1RXN

Y25

DMI1RXP

W28

DMI1TXN

W27

DMI1TXP

AB26

DMI2RXN

AB25

DMI2RXP

AA28

DMI2TXN

AA27

DMI2TXP

AD25

DMI3RXN

AD24

DMI3RXP

AC28

DMI3TXN

AC27

DMI3TXP

AE28

DMI_CLKN

AE27

DMI_CLKP

C25
D25

F1

USBP0N

F2

USBP0P

G4

USBP1N

G3

USBP1P

H1

USBP2N

H2

USBP2P

J4

USBP3N

J3

USBP3P

K1

USBP4N

K2

USBP4P

L4

USBP5N

L5

USBP5P

M1

USBP6N

M2

USBP6P

N4

USBP7N

N3

USBP7P

D2
D1

USBRBIAS

Compal Secret Data

CLK14
CLK48

SUSCLK

SLP_S3#
SLP_S4#
SLP_S5#

PWROK

PWRBTN#

LAN_RST#

RSMRST#

GPIO9
GPIO10
GPIO12
GPIO13
GPIO14
GPIO15
GPIO24
GPIO25

GPIO38
GPIO39

DMI_RXN0
DMI_RXP0
DMI_TXN0
DMI_TXP0

DMI_RXN1
DMI_RXP1
DMI_TXN1
DMI_TXP1

DMI_RXN2
DMI_RXP2
DMI_TXN2
DMI_TXP2

DMI_RXN3
DMI_RXP3
DMI_TXN3
DMI_TXP3

CLK_PCIE_ICH#
CLK_PCIE_ICH

DMI_IRCOMP
USB20_N0

USB20_P0
USB20_N1
USB20_P1
USB20_N2
USB20_P2
USB20_N3
USB20_P3
USB20_N4
USB20_P4
USB20_N5
USB20_P5
USB20_N6
USB20_P6
USB20_N7
USB20_P7

USBRBIAS

Deciphered Date

AF19
AH18
AH19
AE19

CLK_14M_ICH

AC1

CLK_48M_ICH

B2

C20
B24

D23
F22

AA4
AC22
C21
C23
C19
Y4

R1014 10K_0402_5%

E20
A20
F19
E19
R4
E22
R3
D20
AD21
AD20
AE20

1 2

R1002 100_0402_5%

ICH_SUSCLK

SLP_S3#
SLP_S4#
SLP_S5#

PM_POK
DPRSLPVR
ICH_LOW_BAT#
ON/OFFBTN#
PLT_RST#
PM_RSMRST#

1 2

CB_IN#
LID_SW#

LANLINK_STATUS#
XMIT_OFF

GPIO25
NPCI_RST#

1 2

R1386 0_0402_5%@

T91

PAD

DMI_RXN0 <7>
DMI_RXP0 <7>
DMI_TXN0 <7>
DMI_TXP0 <7>

DMI_RXN1 <7>
DMI_RXP1 <7>
DMI_TXN1 <7>
DMI_TXP1 <7>

DMI_RXN2 <7>
DMI_RXP2 <7>
DMI_TXN2 <7>
DMI_TXP2 <7>

DMI_RXN3 <7>
DMI_RXP3 <7>
DMI_TXN3 <7>
DMI_TXP3 <7>

CLK_PCIE_ICH# <15>
CLK_PCIE_ICH <15>

R1016 24.9_0402_1%

1 2

USB20_N0 <27>
USB20_P0 <27>
USB20_N1 <24>
USB20_P1 <24>
USB20_N2 <29>
USB20_P2 <29>
USB20_N3 <27>
USB20_P3 <27>
USB20_N4 <27>
USB20_P4 <27>
USB20_N5 <27>
USB20_P5 <27>
USB20_N6 <32>
USB20_P6 <32>
USB20_N7 <32>
USB20_P7 <32>

R1019 22.6_0402_1%

1 2

Within 500 mils

2

MB_PWR <19>
HDD_HALTLED# <24>

CLK_14M_ICH <15>
CLK_48M_ICH <15>

T67 PAD

SLP_S3# <22,24,25,26,30,32,33,40,41>
SLP_S4# <41>
SLP_S5# <33,41>

PM_POK <7,30>

1 2

DPRSLPVR <7,42>

ON/OFFBTN# <31>
PLT_RST# <7,16,18,19,22,24,30>
PM_RSMRST# <30>

T89 PAD

MBAY_DET# <19>
LID_SW# <17,31>
LANLINK_STATUS# <22,23,32>

T80 PAD

XMIT_OFF <24>
NPCI_RST# <28>

R1015 need be removed when ICH7M ES2 samples used,
but need be stuffed when ICH7M ES1 samples used.

Within 500 mils

+1.5VS

CLK_48M_ICH

12

R997

10_0402_5%@

1

C706

4.7P_0402_50V8C@

2

R1011
R1010
10K_0402_5%

DOCK_ID <32>

GPIO25

Title

Size Document Number Rev

Date: Sheet

8.2K_0402_5%

D58

2 1

CH751H-40_SC76

DPRSLPVR

12

R1017 0_0402_5%@

J28

2 1

PAD-SHORT 2x2m

R1395 0_0402_5%

1 2
1 2

R1427 0_0402_5%@

USB_OC#3
USB_OC#0
USB_OC#1
USB_OC#2

USB_OC#4

USB_OC#5

USB_OC#6

USB_OC#7

RP64

4 5
3 6
2 7
1 8

10K_1206_8P4R_5%

R1018
10K_0402_5%

1 2

R1261
10K_0402_5%

1 2

R1020
10K_0402_5%

1 2

R1237
10K_0402_5%

1 2

Compal Electronics, Inc.

ICH7-M(3/4)

LA-2952P

CLK_14M_ICH

12

R998

10_0402_5%@

1

C707

4.7P_0402_50V8C@

2

12

+3VALW

LOW_BAT# <30>

R1013

10K_0402_5%

R1015

100K_0402_5%@

LOM_LOW_PWR <22>

CABLE_DETECT <22,23>

LP_EN#

1

12
12

+3VALW

20 46Wednesday, October 26, 2005

+3VL

BT_OFF <27>

0.3

of

5

4

3

2

1

ICH_V5REF_RUN

D D

100_0402_5%

10_0402_5%

C C

B B

A A

R989

R990

12

12

+3VS+5VS

+3VALW+5VALW

21

D55
CH751H-40_SC76

ICH_V5REF_RUN

1

C676

0.1U_0402_16V4Z

2

21

D56
CH751H-40_SC76

ICH_V5REF_SUS

1

C684

0.1U_0402_16V4Z

2

+1.5VS

1

C677

0.1U_0402_16V4Z

2

Place closely pin AG28 within 100mlis.

C702

1 2

0_0805_5%

1

C698

2

1

2

R992

0.1U_0402_16V4Z

R991

1 2

0.5_0805_1%

0.1U_0402_16V4Z

+1.5VS

+3VALW

1

+

C570

2

150U_D_6.3VM

C693

10U_0805_10V4Z

+3VS

+1.5VS

C703

0.1U_0402_16V4Z

+1.5VS

+1.5VS_DMIPLL+1.5VS_DMIPLLR

1

2

1

2

1

C672

2

0.1U_0402_16V4Z

Place closely pin
D28,T28,AD28.

1

C694

2

0.01U_0402_16V7K

Place closely pin AG5.

C699

0.1U_0402_16V4Z

Place closely pin AG9.

1

2

0.1U_0402_16V4Z

1

C673

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

+1.5VS

C697

0.1U_0402_16V4Z

+1.5VS

C700

1U_0603_10V4Z

T84 PAD
T85 PAD

+3VALW

ICH_V5REF_SUS

1

C674

2

+3VS

1

C688

2

+1.5VS_DMIPLL

1

2

1

2

ICH_AA2
ICH_Y7

G10

AD17

F6

AA22
AA23
AB22
AB23
AC23
AC24
AC25
AC26
AD26
AD27
AD28

D26
D27
D28
E24
E25
E26
F23
F24
G22
G23
H22
H23
J22
J23
K22
K23
L22

L23
M22
M23

N22

N23

P22

P23

R22

R23

R24

R25

R26

T22

T23

T26

T27

T28

U22

U23

V22

V23
W22
W23

Y22

Y23

B27

AG28

AB7
AC6
AC7
AD6

AE6

AF5

AF6
AG5
AH5

AD2

AH11
AB10

AB9

AC10
AD10
AE10
AF10

AF9
AG9
AH9

E3

C1

AA2

Y7
V5

V1
W2
W7

1

C705

0.1U_0402_16V4Z

2

U26F

V5REF[1]
V5REF[2]
V5REF_Sus
Vcc1_5_B[1]

Vcc1_5_B[2]
Vcc1_5_B[3]
Vcc1_5_B[4]
Vcc1_5_B[5]
Vcc1_5_B[6]
Vcc1_5_B[7]
Vcc1_5_B[8]
Vcc1_5_B[9]
Vcc1_5_B[10]
Vcc1_5_B[11]
Vcc1_5_B[12]
Vcc1_5_B[13]
Vcc1_5_B[14]
Vcc1_5_B[15]
Vcc1_5_B[16]
Vcc1_5_B[17]
Vcc1_5_B[18]
Vcc1_5_B[19]
Vcc1_5_B[20]
Vcc1_5_B[21]
Vcc1_5_B[22]
Vcc1_5_B[23]
Vcc1_5_B[24]
Vcc1_5_B[25]
Vcc1_5_B[26]
Vcc1_5_B[27]
Vcc1_5_B[28]
Vcc1_5_B[29]
Vcc1_5_B[30]
Vcc1_5_B[31]
Vcc1_5_B[32]
Vcc1_5_B[33]
Vcc1_5_B[34]
Vcc1_5_B[35]
Vcc1_5_B[36]
Vcc1_5_B[37]
Vcc1_5_B[38]
Vcc1_5_B[39]
Vcc1_5_B[40]
Vcc1_5_B[41]
Vcc1_5_B[42]
Vcc1_5_B[43]
Vcc1_5_B[44]
Vcc1_5_B[45]
Vcc1_5_B[46]
Vcc1_5_B[47]
Vcc1_5_B[48]
Vcc1_5_B[49]
Vcc1_5_B[50]
Vcc1_5_B[51]
Vcc1_5_B[52]
Vcc1_5_B[53]

Vcc3_3[1]
VccDMIPLL
Vcc1_5_A[1]

Vcc1_5_A[2]
Vcc1_5_A[3]
Vcc1_5_A[4]
Vcc1_5_A[5]
Vcc1_5_A[6]
Vcc1_5_A[7]
Vcc1_5_A[8]
Vcc1_5_A[9]

VccSATAPLL
Vcc3_3[2]
Vcc1_5_A[10]

Vcc1_5_A[11]
Vcc1_5_A[12]
Vcc1_5_A[13]
Vcc1_5_A[14]
Vcc1_5_A[15]
Vcc1_5_A[16]
Vcc1_5_A[17]
Vcc1_5_A[18]

VccSus3_3[19]
VccUSBPLL
VccSus1_05/VccLAN1_05[1]

VccSus1_05/VccLAN1_05[2]
VccSus3_3/VccLAN3_3[1]

VccSus3_3/VccLAN3_3[2]
VccSus3_3/VccLAN3_3[3]
VccSus3_3/VccLAN3_3[4]

ICH7_BGA652~D

Vcc1_05[1]
Vcc1_05[2]
Vcc1_05[3]
Vcc1_05[4]
Vcc1_05[5]
Vcc1_05[6]
Vcc1_05[7]
Vcc1_05[8]

Vcc1_05[9]
Vcc1_05[10]
Vcc1_05[11]
Vcc1_05[12]
Vcc1_05[13]
Vcc1_05[14]
Vcc1_05[15]
Vcc1_05[16]
Vcc1_05[17]
Vcc1_05[18]
Vcc1_05[19]
Vcc1_05[20]

Vcc3_3 / VccHDA

VccSus3_3/VccSusHDA

V_CPU_IO[1]
V_CPU_IO[2]
V_CPU_IO[3]

Vcc3_3[3]
Vcc3_3[4]
Vcc3_3[5]
Vcc3_3[6]
Vcc3_3[7]
Vcc3_3[8]

Vcc3_3[9]
Vcc3_3[10]
Vcc3_3[11]

Vcc3_3[12]
Vcc3_3[13]
Vcc3_3[14]
Vcc3_3[15]
Vcc3_3[16]
Vcc3_3[17]
Vcc3_3[18]
Vcc3_3[19]
Vcc3_3[20]
Vcc3_3[21]

VccRTC
VccSus3_3[1]
VccSus3_3[2]

VccSus3_3[3]
VccSus3_3[4]
VccSus3_3[5]
VccSus3_3[6]

VccSus3_3[7]
VccSus3_3[8]
VccSus3_3[9]

VccSus3_3[10]
VccSus3_3[11]
VccSus3_3[12]
VccSus3_3[13]
VccSus3_3[14]
VccSus3_3[15]
VccSus3_3[16]
VccSus3_3[17]
VccSus3_3[18]

Vcc1_5_A[19]
Vcc1_5_A[20]

Vcc1_5_A[21]
Vcc1_5_A[22]
Vcc1_5_A[23]

Vcc1_5_A[24]
Vcc1_5_A[25]

VccSus1_05[1]
VccSus1_05[2]

VccSus1_05[3]

Vcc1_5_A[26]
Vcc1_5_A[27]
Vcc1_5_A[28]
Vcc1_5_A[29]
Vcc1_5_A[30]

L11
L12
L14
L16
L17
L18
M11
M18
P11
P18
T11
T18
U11
U18
V11
V12
V14
V16
V17
V18

U6
R7
AE23

AE26
AH26

AA7
AB12
AB20
AC16
AD13
AD18
AG12
AG15
AG19

A5
B13
B16
B7
C10
D15
F9
G11
G12
G16

W5
P7
A24

C24
D19
D22
G19

K3
K4
K5
K6
L1
L2
L3
L6
L7
M6
M7
N7

AB17
AC17

T7
F17
G17

AB8
AC8

K7
C28

G20
A1

H6
H7
J6
J7

+VCCP

0.1U_0402_16V4Z

1

C975

C974

2

1U_0603_10V4Z

1

C685

2

0.1U_0402_16V4Z

1

C689

0.1U_0402_16V4Z

2

1

C695

0.1U_0402_16V4Z

2

+1.5VS

1 2

C701 0.1U_0402_16V4Z

ICH_K7
ICH_C28

ICH_G20

+1.5VS

1

C704

0.1U_0402_16V4Z

2

1

2

+3VS

+3VS

1

C681

0.1U_0402_16V4Z

2

1

1

C686

2

2

0.1U_0402_16V4Z

1

C690

0.1U_0402_16V4Z

2

1

C696

0.1U_0402_16V4Z

2

1

1

+

+

2

2

C670
220U_D2_2VM_R9

+VCCP

+3VS

C687

0.1U_0402_16V4Z

+3VALW

+3VALW

T81PAD
T82PAD

T83PAD

C979

330U_D2E_2.5VM_R9@

C679

1 2

0.1U_0402_16V4Z

1 2

C680

0.1U_0402_16V4Z

1 2

C682

4.7U_0805_10V4Z

C691

+3VS

1

C678

0.1U_0402_16V4Z

2

+RTCVCC

1

1

C692

2

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

U26E

A4

A23

B1

B8
B11
B14
B17
B20
B26
B28

C2

C6
C27
D10
D13
D18
D21
D24

E1
E2
E4
E8

E15

F3
F4

F5
F12
F27
F28

G1
G2
G5
G6

G9
G14
G18
G21
G24
G25
G26

H3

H4

H5
H24
H27
H28

J1
J2

J5
J24
J25
J26
K24
K27
K28
L13
L15
L24
L25
L26

M3
M4

M5
M12
M13
M14
M15
M16
M17
M24
M27
M28

N1

N2

N5

N6
N11
N12
N13
N14
N15
N16
N17
N18
N24
N25
N26

P3

P4
P12
P13
P14
P15
P16
P17
P24
P27

ICH7_BGA652~D

VSS[0]
VSS[1]
VSS[2]
VSS[3]
VSS[4]
VSS[5]
VSS[6]
VSS[7]
VSS[8]
VSS[9]
VSS[10]
VSS[11]
VSS[12]
VSS[13]
VSS[14]
VSS[15]
VSS[16]
VSS[17]
VSS[18]
VSS[19]
VSS[21]
VSS[22]
VSS[23]
VSS[24]
VSS[25]
VSS[26]
VSS[27]
VSS[28]
VSS[29]
VSS[30]
VSS[31]
VSS[32]
VSS[33]
VSS[34]
VSS[35]
VSS[36]
VSS[37]
VSS[38]
VSS[39]
VSS[40]
VSS[41]
VSS[42]
VSS[43]
VSS[44]
VSS[45]
VSS[46]
VSS[47]
VSS[48]
VSS[49]
VSS[50]
VSS[51]
VSS[52]
VSS[53]
VSS[54]
VSS[55]
VSS[56]
VSS[57]
VSS[58]
VSS[59]
VSS[60]
VSS[61]
VSS[62]
VSS[63]
VSS[64]
VSS[65]
VSS[66]
VSS[67]
VSS[68]
VSS[69]
VSS[70]
VSS[71]
VSS[72]
VSS[73]
VSS[74]
VSS[75]
VSS[76]
VSS[77]
VSS[78]
VSS[79]
VSS[80]
VSS[81]
VSS[82]
VSS[83]
VSS[84]
VSS[85]
VSS[86]
VSS[87]
VSS[88]
VSS[89]
VSS[90]
VSS[91]
VSS[92]
VSS[93]
VSS[94]
VSS[95]
VSS[96]
VSS[97]

VSS[98]

VSS[99]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
VSS[159]
VSS[160]
VSS[161]
VSS[162]
VSS[163]
VSS[164]
VSS[165]
VSS[166]
VSS[167]
VSS[168]
VSS[169]
VSS[170]
VSS[171]
VSS[172]
VSS[173]
VSS[174]
VSS[175]
VSS[176]
VSS[177]
VSS[178]
VSS[179]
VSS[180]
VSS[181]
VSS[182]
VSS[183]
VSS[184]
VSS[185]
VSS[186]
VSS[187]
VSS[188]
VSS[189]
VSS[190]
VSS[191]
VSS[192]
VSS[193]
VSS[194]

P28
R1
R11
R12
R13
R14
R15
R16
R17
R18
T6
T12
T13
T14
T15
T16
T17
U4
U12
U13
U14
U15
U16
U17
U24
U25
U26
V2
V13
V15
V24
V27
V28
W6
W24
W25
W26
Y3
Y24
Y27
Y28
AA1
AA24
AA25
AA26
AB4
AB6
AB11
AB14
AB16
AB19
AB21
AB24
AB27
AB28
AC2
AC5
AC9
AC11
AD1
AD3
AD4
AD7
AD8
AD11
AD15
AD19
AD23
AE2
AE4
AE8
AE11
AE13
AE18
AE21
AE24
AE25
AF2
AF4
AF8
AF11
AF27
AF28
AG1
AG3
AG7
AG11
AG14
AG17
AG20
AG25
AH1
AH3
AH7
AH12
AH23
AH27

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/05/26 2006/07/26

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

2

Date: Sheet

Compal Electronics, Inc.

ICH7-M(4/4)

LA-2952P

21 46Wednesday, October 26, 2005

1

0.3

of

5

4

3

2

1

J7

PLT_RST#<7,16,18,19,20,24,30>

V_3P3_LAN

R275 1K_0402_5%

1 2

R289 1K_0402_5%

1 2

D D

R277 10K_0402_5%

C C

B B

A A

25MHZ_20P_1BG25000CK1A

2

1

V_3P3_LAN

V_3P3_LAN

LANLINK_STATUS#<20,23,32>

LAN_ACT#<23,32>

R14 200_0402_1%

Y1

1 2

C16
27P_0402_50V8J

0.1U_0402_16V4Z

U4

1

A0

2

A1

3

NC

4

GND

AT24C64AN-10SU-2.7_SO8

1 2

R69 3.3K_0402_5%@

1 2

R92 3.3K_0402_5%@

12

5751_GPIO1
ICH_LAN_SMBCLK

ICH_LAN_SMBDATA
5751_EECLK

5751_EEDAT
LAN_SI

LAN_SO
LAN_SCLK

LAN_CS#

1 2

R73 4.7K_0402_5%

LANLINK_STATUS#

LAN_ACT#

12

XTALO

XTALI

2

C19
27P_0402_50V8J

1

C9

12

8

VCC

5751_GPIO1

7

WP

5751_EECLK

6

SCL

5751_EEDAT

5

SDA

V_3P3_LAN

LAN_CS#
LAN_SCLK
LAN_SI

R16

1K_0402_5%

U71

8
3
7
1
6
5

VCC
W
HOLD
S
C
D

Need 512K

5

12

SST25LF080A_SO8-200mil@

ICH_LAN_SMBCLK
ICH_LAN_SMBDATA

U7A

J10

GPIO0_TST_CLKOUT

J12

GPIO1

D9

SMB_CLK

D8

SMB_DATA

H10

EECLK

J11

EEDATA

F11

SI

E10

SO

D10

SCLK

D11

CS#

H2

PWR_IND#

J2

ATTN_IND#

B3

ATTN_BTTN#

B10

LINKLED#

C10

SPD100LED#

B11

SPD1000LED#

C9

TRAFFICLED#

N10

XTALO

M10

XTALI

BCM5753MKFBG P3_FPBGA196~D

V_3P3_LAN

12

12

R34

R35

1K_0402_5%

1K_0402_5%

4

VSS

2

Q

R1297

1 2

47_0402_5%@

R1396 0_0402_5%@

1 2

R1398 0_0402_5%@

1 2

BCM5753

Media

Misc

Power

Control

Control

Regulator

Hot Plug

Support

PCI-ETEST

LED

Clock

Bias

Layout Notice : No high
speed signal should be
routed near RDAC or on
adjacent layer to RDAC

+3VS

12

R1392

2.2K_0402_5%@

ICH_SMBDATA

LAN_SO

4

LOW_PWR

REGSUP12
REGCTL12
REGSEN12

REGOUT25
REGSUP25

PCIE_TXDN
PCIE_TXDP
PCIE_RXDN
PCIE_RXDP

REFCLK-

REFCLK+

REFCLK_SEL

PCIE_TST

12

R1403

Q96 RHU002N06_SOT323@

S

G

TRD3+

TRD3-

TRD2+

TRD2-

TRD1+

TRD1-

TRD0+

TRD0-

WAKE#

PERST#

TCK

TDI
TDO
TMS

TRST#

RDAC

NIC_PD_N

2.2K_0402_5%@

D

13

S

2

ICH_SMBCLK
ICH_SMBDATA

C12
C13
D12
D13
E12
E13
F12
F13

J5

L13
K12
K13

N13
M13

N4
M4
M8
N8
B5

M6
N6
C4

D7
C2

C6
G4
C5
F4
E5

B9

0_0402_5%

Q93

RHU002N06_SOT323@

D

13

G

2

+5VS

ICH_SMBCLK <4,13,14,15,20,24>
ICH_SMBDATA <4,13,14,15,20,24>

LAN_TX3+
LAN_TX3­LAN_TX2+
LAN_TX2­LAN_TX1+
LAN_TX1­LAN_TX0+
LAN_TX0-

LOM_LOW_PWR

REGSUP12
VAUX_1.2_CTL

PCIE_C_RXN1
PCIE_C_RXP1

LOM_PCIE_WAKE#
CLK_PCIE_LOM#
CLK_PCIE_LOM

R36 4.7K_0402_5%

PLT_RST_LAN#

1 2

R1023

ICH_LAN_SMBDATA
ICH_LAN_SMBCLKICH_SMBCLK

4.7K_0402_5%

0.1U_0402_16V4Z

0.1U_0402_16V4Z

12

R70

1.24K_0402_1%

D63 1N4148_SOD80

1 2
1 2

12

0.1U_0402_16V4Z

1 2

R1420

0_0402_5%@

LAN_TX3+ <23>
LAN_TX3- <23>
LAN_TX2+ <23>
LAN_TX2- <23>
LAN_TX1+ <23>
LAN_TX1- <23>
LAN_TX0+ <23>
LAN_TX0- <23>

R1076

V_1P2_LAN
V_2P5_LAN
V_3P3_LAN

C17

1 2

C18

1 2

PCIE_TXN1 <20>
PCIE_TXP1 <20>

V_3P3_LAN

1 2

R71 4.7K_0402_5%

0_0402_5%

R1024121K_0402_1%

2

C1058

1

PLT_RST_LAN#

PCIE_RXN1 <20>
PCIE_RXP1 <20>

CLK_PCIE_LOM# <15>
CLK_PCIE_LOM <15>

V_3P3_LAN +3VS

R1021

1 2
5

P

2

O4I

NC

G

3

R1022

0_0402_5%@

1 2

R1094 0_0402_5%

1

SN74LVC1G17DBVR_SOT23-5
U55

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

S

G

2

D

1 3

Q40
AO7407_SOT323

ADP_PRES<30,37,38,39,43>

RHU002N06_SOT323

SLP_S3#<20,24,25,26,30,32,33,40,41>

12

R1089

NIC_PD

12

220K_0402_5%

Q30

RHU002N06_SOT323

LOM_PCIE_WAKE#

V_3P3_LAN

2

G

Compal Secret Data

1 2

0_0402_5%

2005/05/26 2006/07/26

R1419

1 2

R1397

0_0402_5%@

2

G

Q29

NIC_PD_N

13

D

S

12

R1085
10K_0402_5%

NIC_PD#

13

D

S

CLKREQA# <15>

Deciphered Date

+3VALW

12

R267

4.7K_0402_5%
R268

12

13

D

2

G

S

13

D

S

13

D

2

G

S

1 3

D

Q103

AO7407_SOT323

1 2

R1082

1 2

100K_0402_5%

Q104

AO7407_SOT323@

2

G

0_0402_5%
R1088

1 2
1 2

R1090
0_0402_5%@

Q105
RHU002N06_SOT323

LOM_LOW_PWR<20>

SI2301BDS_SOT23

47K_0402_5%

NIC_PD <23>

LP_EN#

Q94
RHU002N06_SOT323

NIC_PD

2

G

S

R10910_0402_5%@

CABLE_DETECT<20,23>

CKT Notice : CABLE IN, CABLE_DETECT=0

21

PAD-NO SHORT 2x2m

S

D

13

Q31

G

2

12

C347

4.7U_0805_10V4Z

V_3P3_LAN
+3VS

LOM_LOW_PWR

SN74LVC1G17DBVR_SOT23-5@

C324

Must having maximized
copper under pin 2 & 4 of Q13

L

REGSUP12

2

2

C55

0.1U_0402_16V4Z

1

1

ICH_PCIE_WAKE# <20,24>

CABLE_DETECT

0.1U_0402_16V4Z

CABLE OUT, CABLE_DETECT=1

2

Layout Notice : Place as close
chip as possible.

V_3P3_LAN

2

2

2

C41

1

1

4.7U_0805_10V4Z

0.1U_0402_16V4Z

BCP69_SOT223
Q13

3

VAUX_1.2_CTL

V_3P3_LAN

0.1U_0402_16V4Z

5

U36

P

O4I

1

NC

G

3

+3VALW

12

R506
10K_0402_5%

1

C578

2

Title

Size Document Number Rev

Date: Sheet

2

2

C44

C32

C39

1

0.1U_0402_16V4Z

4
2

C68

1

0.1U_0402_16V4Z

1

1

0.1U_0402_16V4Z

0.1U_0402_16V4Z

V_1P2_LAN V_3P3_LAN

1

2

1

C228
10U_0805_10V4Z

2

4.7U_0805_10V4Z

L

V_2P5_LAN

2

C74

C580

1 2

2

1

2

1 2

0.1U_0402_16V4Z

R503

1 2

100K_0402_5%

C576

0.1U_0402_16V4Z

R507

0_0402_5%@

1

13

D

S

RHU002N06_SOT323

Compal Electronics, Inc.

BCM5751M

LA-2952P

V_3P3_LAN

2

C348

1

Place close U6 pin M13

1

2

C243

10U_0805_10V4Z @

Place close U6 pin N13

L

+3VS

R540

12

10K_0402_5%

LP_EN#

2

G

Q54

1

2

C83

0.1U_0402_16V4Z

1

1

+

C976
100U_B2_6.3VM

2

of

22 46Wednesday, October 26, 2005

LP_EN# <20>

0.3

5

LAN_TX0-

V_2P5_LAN

LAN_TX0+

12

C330

0.01U_0402_16V7K

D D

C327

0.01U_0402_16V7K

C328

0.01U_0402_16V7K

C329

0.01U_0402_16V7K

C C

V_3P3_LAN_LED

B B

V_3P3_LAN_LED

LANLINK_STATUS#<20,22,32>

A A

LAN_TX1-

LAN_TX1+
TRM_CT

12

LAN_TX2-

LAN_TX2+
TRM_CT

12

LAN_TX3-

LAN_TX3+
TRM_CT

12

LAN_ACT#<22,32>

MDO3-<32>
MDO3+<32>
MDO1-<32>
MDO2-<32>
MDO2+<32>
MDO1+<32>
MDO0-<32>
MDO0+<32>

T66

12

TD4-

11

TD4+

10

TCT4

9

TD3-

8

TD3+

7

TCT3

6

TD2-

5

TD21+

4

TCT2

3

TD1-

2

TD1+

1

TCT1

LG-2410S-5

R50 49.9_0402_1%

C560.1U_0402_16V4Z

1 2
1 2
1 2
1 2

Layout Notice : Place
termination as close as
BCM5751M as possible

R266 300_0402_5%

R265 300_0402_5%

5

1 2

R63 49.9_0402_1%

1 2

C540.1U_0402_16V4Z

R45 49.9_0402_1%

1 2

R48 49.9_0402_1%

1 2

C500.1U_0402_16V4Z

R42 49.9_0402_1%

1 2

R44 49.9_0402_1%

1 2

C490.1U_0402_16V4Z

R40 49.9_0402_1%

1 2

R41 49.9_0402_1%

1 2

12

LAN_ACT#
MDO3­MDO3+
MDO1­MDO2­MDO2+
MDO1+
MDO0­MDO0+

12

LANLINK_STATUS#

V_3P3_LAN V_3P3_LAN_LED

12

R525

100K_0402_5%

PREP#<20,25,32>

Q61

RHU002N06_SOT323

1:1

1:1

1:1

1:1

13
14

11
12

S

G

2

13

D

2

G

S

JP4

Yellow LED+
Yellow LED-

8

PR4-

7
6
5
4
3
2
1

DETECT PIN1

PR4+
PR2­PR3­PR3+
PR2+
PR1-

DETCET PIN2

PR1+
Green LED+
Green LED-

FOX_JM36113-P1122-7F

D

13

Q60
AO3413L_SOT23

MX4-

MX4+
MCT4

MX3-

MX3+
MCT3

MX2-

MX2+
MCT2

MX1-

MX1+
MCT1

SHLD1

SHLD1

13

14
15
16

17
18
19

20
21
22

23
24

LAN_TX0­LAN_TX0+
LAN_TX1­LAN_TX1+
LAN_TX2­LAN_TX2+
LAN_TX3­LAN_TX3+

MDO0-

MDO0+
MCT0TRM_CT
MDO1-

MDO1+
MCT1
MDO2-

MDO2+

MDO3-

MDO3+

16
9

10
15

4

R269

75_0402_1%

R270

75_0402_1%

R271

75_0402_1%

R272

75_0402_1%

LAN_TX0- <22>
LAN_TX0+ <22>
LAN_TX1- <22>
LAN_TX1+ <22>
LAN_TX2- <22>
LAN_TX2+ <22>
LAN_TX3- <22>
LAN_TX3+ <22>

1

C579

0.1U_0402_16V4Z

2

4

12

12

12

12

1000P_1808_3KV7K

CABLE_DETECT <20,22>

RJ-45 CONN.

C344

1 2

1000P_1808_3KV7K

C320

1 2

VMAINPRSNT VMAINPRSNT_R

Layout Notice : Filter place as close
chip as possible.

V_2P5_LAN

V_1P2_LAN

R985

0_0603_5%

R986

0_0603_5%

R987

0_0603_5%

L33

BLM11A601S_0603

4.7U_0805_10V4Z

L32

BLM11A601S_0603

4.7U_0805_10V4Z

L30

BLM11A601S_0603

4.7U_0805_10V4Z
L29

BLM11A601S_0603

4.7U_0805_10V4Z

3

+3VS

NIC_PD <22>

2

G

1 3

D

1 2

C35

C60

C46

S

R10400_0402_5%

XTALVDD

2

1

AVDD1

2

1

AVDD2

2

1

AVDDL

2

C339

0.1U_0402_16V4Z

1

GPHY_PLLVDD

2

C332

0.1U_0402_16V4Z

1

PCIE_PLLVDD

2

C326

0.1U_0402_16V4Z

1

PCIE_SDS_VDD

2

C325

0.1U_0402_16V4Z

1

Q106 AO7407_SOT323@

12

0.1U_0402_16V4Z

12

0.1U_0402_16V4Z

12

0.1U_0402_16V4Z

12

2

C342

1

12

2

C331

1

12

2

C323

1

12

1

C322

2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

R871

10K_0402_5%

1 2

L

2005/05/26 2006/07/26

V_2P5_LAN V_1P2_LAN

0.1U_0402_16V4Z

C65

2

1

V_3P3_LAN

R2761K_0402_5%

1 2

PCIE_SDS_VDD

V_3P3_LAN

R284

4.7K_0402_5%@

PAD

1 2

T59

T59 , T60 place together

V_3P3_LAN

R285 4.7K_0402_5%@

1 2

T60
PAD

R287 4.7K_0402_5%@

1 2

R286 4.7K_0402_5%@

1 2

PCIE_PLLVDD

GPHY_PLLVDD

Compal Secret Data

Deciphered Date

C15

2

1

V_3P3_LAN

V_2P5_LAN XTALVDD

LAN_AUXPWR
VMAINPRSNT

AVDDL
AVDD1

AVDD2

2

0.1U_0402_16V4Z

V_1P2_LAN

2

C66

4.7U_0805_10V4Z

A10

E11
H11

P12

M12

J13

H12

K11

L11

G11
G12
B12
G13

H13

2

1

U7B

E6
E7
E8
E9

J6
J7
J9

K5
A2

A6
B4

D3

G2

K3

M2

B6
H4

C7
L5
A1

A4
A5
A7
A9
B2
B7
B8
C8
D1
D2
D4
D5
E1
E2
E4
F2

F3
G1
G3

H1

H3

J3

J4
K1
K2

L1
L2
L3
L4
L8
L9

M1
M5
M9

N2
N3
N9
P1
P2

L7

2

C61

1

0.1U_0402_16V4Z

VDDC_0
VDDC_1
VDDC_2
VDDC_3
VDDC_4
VDDC_5
VDDC_6
VDDC_7

VDDIO_0
VDDIO_1
VDDIO_2
VDDIO_3
VDDIO_4
VDDIO_5
VDDIO_6
VDDIO_7
VDDIO_8
VDDIO_9
VDDIO_10

VDDP_0
VDDP_1
VDDP_2
XTALVDD
VAUXPRSNT
VMAINPRSNT
PCIE_SDSVDD

NC_0
NC_1
NC_2
NC_3
NC_4
NC_5
NC_6
NC_7
NC_8
NC_9
NC_10
NC_11
NC_12
NC_13
NC_14
NC_15
NC_16
NC_17
NC_18
NC_19
NC_20
NC_21
NC_22
NC_23
NC_24
NC_25
NC_26
NC_27
NC_28
NC_29
NC_30
NC_31
NC_32
NC_33
NC_34
NC_35
NC_36
NC_37
NC_38
NC_39
NC_40
NC_41

AVDDL_0
AVDDL_1
AVDD_0
AVDD_1

PCIE_PLLVDD
GPHY_PLLVDD

Layout Notice : 1.2V filter. Place as close
chip as possible.

2

C341

1

0.1U_0402_16V4Z

BCM5753

Analog
power

PLL

BCM5753MKFBG P3_FPBGA196~D

2

2

C334

1

0.1U_0402_16V4Z

Digial power

Disconnected

BIAS

Title

Size Document Number Rev

Date: Sheet

2

1

C335

VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31

BIASVDD

0.1U_0402_16V4Z

VSS_0
VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9

DC_0
DC_1
DC_2
DC_3
DC_4
DC_5
DC_6
DC_7
DC_8

DC_9
DC_10
DC_11
DC_12
DC_13
DC_14
DC_15
DC_16
DC_17
DC_18
DC_19
DC_20
DC_21
DC_22
DC_23
DC_24
DC_25
DC_26
DC_27
DC_28
DC_29
DC_30
DC_31
DC_32
DC_33
DC_34
DC_35
DC_36
DC_37
DC_38
DC_39

C336

1

A3
A8
A12
A14
B1
C1
C3
C11
F1
F5
F6
F7
F8
F9
F10
G5
G6
G7
G8
G9
G10
H6
H7
H8
H9
J1
M3
M7
N1
N7
P11
P14

A11
A13
B14
C14
D6
D14
E3
E14
F14
G14
H5
H14
J8
J14
K4
K6
K7
K8
K9
K10
K14
L6
L10
L12
L14
M11
M14
N5
N11
N12
N14
P3
P4
P5
P6
P7
P8
P9
P10
P13

B13

C340

0.1U_0402_16V4Z

GND

Don't care

Compal Electronics, Inc.

Magnetic & RJ45/RJ11

LA-2952P

2

1

0.1U_0402_16V4Z

2

C343

1

0.1U_0402_16V4Z

BIASVDD_LAN

1

C63

0.1U_0402_16V4Z

2

1

C337

0.1U_0402_16V4Z

1

2

1

1 2

2

C338

1

0.1U_0402_16V4Z

V_2P5_LAN

L8

BLM11A601S_0603

23 46Wednesday, October 26, 2005

0.3

of

A

B

C

D

E

+3VS +1.5VS

+3VALW

B/B connector with PCI / LED / FIR / SC interface

1

C538

4.7U_0805_10V4Z

2

ICH_PCIE_WAKE#

CH_DATA
CH_CLK

CLK_PCIE_MCARD#
CLK_PCIE_MCARD

PCIE_RXP2

PCIE_TXN2
PCIE_TXP2

S

G

2

G

R1357 0_0402_5%

R1359 0_0402_5%

1

C995

2

0.1U_0402_16V4Z

R1336 0_0402_5%

PLT_RST_B#

R1412 0_0402_5%DEBUG@

R1348 0_0402_5%

1 2
1 2

R1349 0_0402_5%

R1418 0_0402_5%DEBUG@

1 2

R1358 0_0402_5%DEBUG@

1 2

R1353 0_0402_5%DEBUG@

1 2

R1360 0_0402_5%DEBUG@

1 2

D

13

2
13

D

S

12

12

0_0402_5%

+3VS_ACL

1

2

Deciphered Date

SC_CD#
SC_FCB
SC_CLK
SC_RST

SC_DATA
SC_RFU

PCI_AD[0..31]

PCI_PIRQE#
PCI_PIRQC#
PCI_RST#
PCI_GNT2#

PCI_AD30
PCI_AD28
PCI_AD26
PCI_AD24

PCI_AD22
PCI_AD20

PCI_PAR

PCI_AD18

PCI_AD16
PCI_FRAME#
PCI_TRDY#
PCI_STOP#
PCI_DEVSEL#

PCI_AD15

PCI_AD13

PCI_AD11

PCI_AD9
PCI_CBE#0

PCI_AD6

PCI_AD4

PCI_AD2

PCI_AD0

1
3
5
7

9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89

91
93
95

JP13

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89

GND
GND
GND

88020-90101

GND
GND
GND

2

2

4

4

6

6

8

8

10

10

12

12

14

14

16

16

18

18

20

20

22

22

24

24

26

26

28

28

30

30

32

32

34

34

36

36

38

38

40

40

42

42

44

44

46

46

48

48

50

50

52

52

54

54

56

56

58

58

60

60

62

62

64

64

66

66

68

68

70

70

72

72

74

74

76

76

78

78

80

80

82

82

84

84

86

86

88

88

90

90

92
94
96

+3VL

+3VS

+5VS

CLK_PCI_PCM
PCI_PIRQG#

PCI_PIRQD#
PCI_REQ2#

PCI_AD31
PCI_AD29
PCI_AD27
PCI_AD25

PCI_AD23
PCI_AD21

PCI_AD19
PCI_AD17
PCI_CBE#2
PCI_IRDY#

PCI_SERR#
PCI_PERR#
PCI_CBE#1

PCI_AD14
PCI_AD12
PCI_AD10
PCI_AD8
PCI_AD7
PCI_AD5
PCI_AD3
PCI_AD1

CLK_PCI_PCM<15>
PCI_PIRQG#<18>

R106
10_0402_5%@

PCI_PIRQD#<18>

PCI_REQ2#<18>

PCI_CBE#3<18>

PCI_CBE#2<18>

PCI_IRDY#<18>

PM_CLKRUN#<20,28,29,30>

PCI_SERR#<18,30>
PCI_PERR#<18>

PCI_CBE#1<18>

HDD_HALTLED#<20>

WL_BLUE_LED#<29,31>
GREEN_BATLED#<30>
AMBER_BATLED#<30>

STB_LED#<30,31,32>

IDE_LED#<19>

1 1

2 2

CLK_48M_CB

12

1

C165
18P_0402_50V8J

@

2

Mini-Express Card--WWAN

1

C295

2

PLT_RST_B# <19,28,29>

+3VALW
+3VS

R1425

1 2

0_0402_5%@

R1426

P

8

1 2

O

0_0402_5%

G

U43C

SN74LVC08APW_TSSOP14

0.1U_0402_16V4Z

WW_LED#

12

+3VS+1.5VS

M_WXMIT_OFF#

R521
100K_0402_5%

0.01U_0402_16V7K

UIM_PWR
UIM_DATA
UIM_CLK
UIM_RST
UIM_VPP

1 2

R1365 0_0402_5%@

1 2

R1366 0_0402_5%

USB20_N1 <20>
USB20_P1 <20>

WW_LED# <29>

+3VS

14

9

A

10

B

7

+3VALW

1

C959

3 3

4 4

2

0.1U_0402_16V4Z

+3VS

R1071

0_0603_5%

1 2
1 2

R1073

0_0603_5%

+3VS

MOLEX 67910-0002 52P

SW1
ESE11MV9_4P

2

4

JP46

112
334
556
778
9910
111112
131314
151516
171718
191920
212122
232324
252526
272728
292930
313132
333334
353536
373738
393940
414142
434344
454546
474748
494950
515152

GND153GND2

1

3

A

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

54

WXMIT_OFF#<20>

0.1U_0402_16V4Z

1

C986

2

1

C540

4.7U_0805_10V4Z

2

U72

1

CH1

2

Vn
CH23CH3

S DIO(BR) NUP4301MR6T1 TSOP-6

JP50

4

UIM_VPP

UIM_DATA

M_WXMIT_OFF#

B

GND

5

VPP

6

I/O

SUYIN_254021MA006G100ZL

PCI_AD[0..31] <18>

PCI_PIRQE# <18>
PCI_PIRQC# <18>
PCI_RST# <18,19>
PCI_GNT2# <18>
SIRQ <20,28,29,30>
CLK_48M_CB <15>

PLT_RST# <7,16,18,19,20,22,30>

PCM_SPK <25>

PCI_PAR <18>

PCI_FRAME# <18>
PCI_TRDY# <18>
PCI_STOP# <18>
PCI_DEVSEL# <18>

PCI_CBE#0 <18>

IRRX <28>
IRTXOUT <28>
IRMODE <28>

SC_CD# <27>
SC_FCB <27>
SC_CLK <27>
SC_RST <27>
+SC_PWR
SC_DATA <27>
SC_RFU <27>

+1.5VS +3VS

1

2

Vp

VCC
RST
CLK

C291

0.01U_0402_16V7K

6
5
4

1
2
3

1

0.01U_0402_16V7K

2

UIM_PWR
UIM_RST
UIM_CLK

4.7U_0805_10V4Z

C544

CH4

0.1U_0402_16V4Z

Mini-Express Card---WLAN

ICH_PCIE_WAKE#<20,22>

CH_DATA<27>
CH_CLK<27>
CLKREQD#<15>

CLK_PCIE_MCARD#<15>

CLK_PCIE_MCARD<15>

PLT_RST_B#<19,28,29>

CLK_DEBUG_PORT<15>

PCIE_RXN2<20>
PCIE_RXP2<20>

PCIE_TXP2<20>

+3VL
STB_LED#<30,31,32>
NUM_LED#<30,31>
CAPS_LED#<30,31>

+3VALW +3V_MINI

SLP_S3#<20,22,25,26,30,32,33,40,41>

1

C547

2

C554

D13

1

DAN217_SC59

1

2

+3VS_UIM

1

2

+3VS_UIM

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

ACCELEROMETER

3
2

C960

0.1U_0402_16V4Z

@

C

0.01U_0402_16V7K@

2005/05/26 2006/07/26

SI2301BDS_SOT23@

R519

1 2

100K_0402_5%@

Q42

RHU002N06_SOT323@

+3VS_ACL_IO

+3VS_ACL

C994

Compal Secret Data

Q41

1

C542

0.01U_0402_16V7K

2

CLKREQD#_MC

1 2

1 2

PCIE_C_RXN2PCIE_RXN2
PCIE_C_RXP2

+3VS

R996

1 2

0_0805_5%

+3VS +3VS_ACL

R1355

1 2

0_0805_5%

2 1

D64

CH751H-40_SC76@

U64

18

Reserved2

20

Reserved3

4

Reserved1

12

R1361

1

2

14
15
21
22
23
24
25
26
27

28

C996
10U_0805_10V4Z

1

NC1

7

NC2

8

NC3
NC4
NC5
NC6
NC7
NC8
NC9
NC10
NC11
NC12
NC13

C293

MOLEX 67910-0002 52P

19

3

Vdd

Vdd

GND

GND

PADDLE

2

5

29

1

2

JP44

112
334
556
778
9910
111112
131314
151516
171718
191920
212122
232324
252526
272728
292930
313132
333334
353536
373738
393940
414142
434344
454546
474748
494950
515152

GND153GND2

R1356

1 2

11

Vdd_IO

SDA/SDI/SDO

17

Must be placed in the center of the system.

D

1

C294

0.1U_0402_16V4Z

+3VS_ACL_IO

0_0603_5%

RDY/INT

SDO

SCL/SPC

CS

CK

GND

Title

Size Document Number Rev

Date: Sheet

4.7U_0805_10V4Z

2

2
4
6

R1413

8

1 2

R1414

10

1 2

R1415

12

1 2

R1416

14

1 2

R1417

16

1 2

18

XMIT_OFF#

20
22

R1363

24

R1364

26
28
30
32
34
36
38
40

WW_LED#

42

WL_LED#

44

WP_LED#

46
48
50
52

54

XMIT_OFF<20>

6

9

10

12

13

1 2

10K_0402_5%

R1391

16

1 2

0_0402_5%

LIS3LV02DQ_QFN28

Compal Electronics, Inc.

Mini-Card/Mini-PCI/Accelerometer

1

C533

2

0_0402_5%DEBUG@
0_0402_5%DEBUG@
0_0402_5%DEBUG@
0_0402_5%DEBUG@
0_0402_5%DEBUG@

LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0

0_0402_5%@

1 2
1 2

0_0402_5%

ICH_SMBCLK <4,13,14,15,20,22>
ICH_SMBDATA <4,13,14,15,20,22>PCIE_TXN2<20>

WW_LED# <29>
WL_LED# <29>
WP_LED# <29>

R516

10K_0402_5%@

Q58

RHU002N06_SOT323@

1 2

R1422 0_0402_5%

ACCEL_INT <18>

ICH_SMBDATA <4,13,14,15,20,22>
ICH_SMBCLK <4,13,14,15,20,22>

R1362

+3VS_ACL

LA-2952P

E

1

C954

0.1U_0402_16V4Z

LPC_FRAME# <19,28,29,30>

+3VALW
+3VS

12

2

G

2

+1.5VS +3V_MINI

LPC_AD[0..3] <19,28,29,30>
PLT_RST_B# <19,28,29>

+3VALW

12

R517
100K_0402_5%@

XMIT_OFF#

13

D

S

of

24 46Wednesday, October 26, 2005

0.3

A

B

C

D

E

F

G

H

VDDA_CODEC

12

R329
10K_0402_5%

C390

1 2

13

D

0.1U_0402_16V4Z

2

1 1

2 2

PCM_SPK<24>

Q35

RHU002N06_SOT323

SB_SPKR<20>

Q37

RHU002N06_SOT323

Place close to U14

R1400

0_1206_5%

C409 0.1U_0402_16V4Z

C427 0.1U_0402_16V4Z

C431 0.1U_0402_16V4Z

G

VDDA_CODEC

2

G

12

12

12

12

S

12

R350
10K_0402_5%

13

D

0.1U_0402_16V4Z

S

C396

1 2

GNDAGND

DLINE_IN_L<32>

DLINE_IN_R<32>

3 3

VDDA_CODEC

1 2

SENSE_A

4 4

SENSE_B

R980

0_0402_5%@

1 2

A

2

1

R341

1 2

150K_0402_1%

R359

1 2

150K_0402_1%

R370 4.7K_0402_5%
R375 4.7K_0402_5%
R369 4.7K_0402_5%
R374 4.7K_0402_5%

R969

2.67K_0402_1%

1 2

R970 39.2K_0402_1%

1 2

R972 20K_0402_1%

1 2

R973 10K_0402_1%

C977

1U_0402_6.3V4Z@

1 2
1 2

2N7002_SOT23

B

10K_0402_5%

R330

INT_MIC<26>

12
12

SENSE_A_C

Q97

12

2

C377

0.01U_0402_16V7K

1

SENSE_A_A <26>

SENSE_A_B <26>

13

D

S

1 2

C430 0.1U_0402_16V4Z

INT_MIC

DLINE_IN_R_L
DLINE_IN_R_R

MIC1<26>
MIC2<26>

VDDA_CODEC

AC97_RST#_CODEC<19>

AC97_SYNC_CODEC<19>

AC97_SDOUT_CODEC<19>

2

G

R988

1 2

100K_0402_5%

MONO_IN

VDDA_CODEC

1

C147

C395

0.1U_0402_16V4Z

2

0.1U_0402_16V4Z

C425 1U_0603_10V4Z

1 2

C426 1U_0603_10V4Z

1 2

C423 1U_0603_10V4Z

1 2

C422 1U_0603_10V4Z

1 2

MIC2 MIC2_C

R231 2.2K_0402_1%
R169 0_0402_5%@

EAPD<26,30>

VDDA_CODEC

R974

0_0402_5%@

1 2

LINE_IN_SENSE

1

C978

0.1U_0402_16V4Z

2

C

0.1U_0402_16V4Z

1

1

2

1 2

C204 1U_0603_10V4Z

1 2

C205 1U_0603_10V4Z

1 2
1 2

L53
FBM-L10-160808-301-T_0603

T15 PAD

C417

C148

2

T16 PAD
T17 PAD

T18 PAD
T19 PAD
T20 PAD

1 2

LINE_IN_SENSE <32>

1

2

10U_0805_10V4Z

DLINE_IN_RC_L
DLINE_IN_RC_R

MIC1_CMIC1

SENSE_A

SENSE_B

0.1U_0402_16V4Z

C402

+5VAMP

2

1

U14

14

AUX_L

15

AUX_R

16

MIC3

17

MIC4

23

LINE_IN_L

24

LINE_IN_R

18

CD_L

20

CD_R

19

CD_GND

21

MIC1

22

MIC2

13

SENSEA

34

SENSEB

11

RESET#

10

SYNC

5

SDATA_OUT

47

EAPD

48

SPDIFO

4

DVSS1

7

DVSS2

AD1981HDJSTZ-REEL_LQFP48

1

+

2

C548
22U_B_10V

38

AVDD125AVDD2

2

C552
1U_0603_10V4Z

1

DVDD11DVDD2

LINE_OUT_L

LINE_OUT_R

MONO_OUT
HP_LOUT_L
HP_LOUT_R

BIT_CLK

SDATA_IN

GPIO_0
GPIO_1
GPIO_2
GPIO_3

VREF

MIC_BIAS_B
MIC_BIAS_C
MIC_BIAS_F
MIC_BIAS_D

PCBEEP

AVSS1
AVSS2

N/C
N/C
N/C

NC
NC

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

D

SLP_S3#<20,22,24,26,30,32,33,40,41>

2

C551
100P_0402_50V8J

1

1 2

R258

0_1206_5%

U18

1

IN

5

OUT

3

EN

4

ADJ

2

GND

MIC5205BM5_SOT23-5

0.01U_0402_16V7K

Place R258 between DGND & AGND & close to U14

+3VS

0.1U_0402_16V4Z

9

35
36
37
39
41

6
8

43
44
2
3

27
28

29
30
32
12

31
33
40
45
46

26
42

2005/05/26 2006/07/26

+3VS_CODEC

1

1

C156

C175

2

2

0.1U_0402_16V4Z

LINE_OUTL
LINE_OUTR

L_HP
R_HP

R1038 33_0402_5% @

AC97_SDIN0_CODEC

R168 4.7K_0402_5%@

1 2

R167 4.7K_0402_5%@

1 2

R136 10K_0402_5%

1 2

R32 4.7K_0402_5%@

1 2

AUD_REF

T21
T13
T12
T11

MONO_IN

T6 PAD
T7 PAD
T5 PAD
T3 PAD
T4 PAD

Compal Secret Data

E

1 2

0_0805_5%

1

C393
10U_0805_10V4Z

2

T14

12

AC97_BITCLK_CODEC <19>

R373

33_0402_5%

PAD
PAD
PAD
PAD

Deciphered Date

R1399

LINE_OUTL <26>
LINE_OUTR <26>

PAD

L_HP <26>
R_HP <26>

12

C1064

F

VDDA_CODEC

2

C553

1

10P_0402_25V8K@

1 2

AC97_SDIN0 <19>

PORT_A_SNS <26>

PREP# <20,23,32>

1

C424
1U_0603_10V4Z

2

12

R456

49.9K_0402_1%

12

R457
143K_0402_1%

1

C416

0.1U_0402_16V4Z

2

1

1

+

2

Size Document Number Rev

Date: Sheet

C309
22U_B_10V

Title

C307

0.1U_0402_16V4Z

2

PORT
MONO_OUT
PORT A
PORT B
PORT C
PORT D
PORT E
PORT F

PLACE TO
X
HP OUT, DOCK HP LO
M/B MIC
DOCK LI
M/B SPK
X
Internal MIC

Compal Electronics, Inc.

AC97 CODEC AD1981B

LA-2952P

G

of

25 46Wednesday, October 26, 2005

H

0.3

A

B

C

D

E

AMP. FOR INTERNAL SPEAKER

+5VAMP+5VALW

12

8

VDD

PGND1

6

VDDA_CODEC

2

1

R255

1 2

100K_0402_5%

J_MIC_REF

B

C659
10U_0805_10V4Z

18

PVDD1

PVDD2

PGND211PGND315PGND4

20

12

R426

47K_0402_5%

12

R428

47K_0402_5%

VDDA_CODEC

L_CRL_HP

C563

ACES_87213-0600

1

2

1U_0603_10V4Z

U39

BIAS

OUTR+

OUTR-

OUTL+
OUTL-

NC1
NC2
NC3
NC4

MAX9710ETP_QFN20

12

1

2

1

2

C539

C660

0.1U_0402_16V4Z

2

2

C1044 1U_0603_10V4Z

2

R1405

R_SPK+

7

R_SPK-

9

R1406

L_SPK+

19

L_SPK-

17

3
10
13
16

VDDA_CODEC

8

5

P

+

O

6

-

G

U27B

TLV2462_SO8

4

DLINE_OUT_L<32>
DLINE_OUT_R<32>

R251
100K_0402_5%

DLINE_OUT_L

C526
1U_0603_10V6K@

1

C564
470P_0402_50V7K

2

1 2

15K_0402_5%

1 2

15K_0402_5%

1

1

Place close to JP24

JP28

1

1

2

2

3

3

J_DLINE_OUT_L

4

4

J_DLINE_OUT_R

5

5

6

6

Keep 10 mil width

1 2

LINE_C_R_OUTR

10 dB

LINE_C_R_OUTL

10 dB

1 2

MIC_REF

R978

100_0402_5%

1 2

7

MIC1<25>
MIC2<25>
MIC_REF

R_HP<25>
L_HP<25>

VDDA_CODEC

5
4
3

6
2
1

SUYIN_010030FR006G101ZL_6P

J_R_HP
J_L_HP

J_VDDA_CODEC

C471

0.01U_0402_16V7K

C982

1

4.7U_0805_6.3V6K

2

MIC1

1
2

MIC2

3
4

MIC_SENSE

5
6

R_HP

7

L_HP

8

9
10
11
12

ACES_87213-1200

JP24

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

R443

1 2

C1098

10U_0805_10V4Z

1 1

C503

LINE_OUTR<25>

LINE_OUTL<25>

2 2

1 2

0.1U_0402_16V4Z
C502

1 2

0.1U_0402_16V4Z

MUTE_LED#<31>

EAPD<25,30>

A_SD<30>

SLP_S3#<20,22,24,25,30,32,33,40,41>

Place close to U14 audio CODEC

PORT_A_SNS<25>

SENSE_A_A<25>

RHU002N06_SOT323

S DIO(BR) NUP4301MR6T1 TSOP-6@

L_SPK+
L_SPK­R_SPK+
R_SPK-

C506

100P_0402_50V8J

DOCK_HPS#<32>

J_R_HP

J_L_HP

1
2

100P_0402_50V8J

1

C514

2

3 3

4 4

13

D

Q49

S

0.1U_0603_16V4Z

+

1 2

C577 150U_D_6.3VM

J_DLINE_OUT_R
J_DLINE_OUT_L

+

1 2

C581 150U_D_6.3VM

Place close to JP24

U73

6

CH1

CH4

5

Vn

Vp

4

CH23CH3

1

1

C507

2

2

100P_0402_50V8J

A

10 dB

LINE_C_OUTR LINE_C_R_OUTR

LINE_C_OUTL LINE_C_R_OUTL

G

1

2

R1410

1 2

10K_0402_5%

R1411

1 2

10K_0402_5%

10 dB

R430 10K_0402_5%

1 2

12

R1421 0_0402_5%@

Q28

RHU002N06_SOT323@

RHU002N06_SOT323

VDDA_CODEC

12

R995

100K_0402_5%

Q48

13

D

RHU002N06_SOT323

2

G

S

2

1

C527

2

R_C_HP

1 2

L_C_HP

1 2

16_0805_1%

1K_0402_1%

+3VS

JP21

1

1

2

2

3

3

ACES_87213-0600

4

4

C518

E&T_3801-04

100P_0402_50V8J

Q44

RHU002N06_SOT323

R261

16_0805_1%

R253

R445

Place close to JP15

0_1206_5%

1

@

2

150U_D_6.3VM

R1407

12

0_0402_5%

13

D

2

G

S

13

D

2

G

Q32

S

4.7U_0805_10V4Z

VDDA_CODEC

12

R423
100K_0402_5%

13

D

2

G

S

R_CR_HP R_CRL_HP

L_CR_HP

CHB1608B121_0603

12

12

R446
1K_0402_1%

JP27

1

1

2

2

3

3

4

4

5

5

J_MIC_SENSE

6

6

1

+

C662

2

5

INR

1

INL

4

MUTE

14

SHDN

C490

1

C536

2.2U_0603_6.3V6K

2

CHB1608B121_0603

1 2

L52

L51

1 2

470P_0402_50V7K

J_MIC1
J_MIC2

AMP. FOR INTERNAL MICROPHONE

Place close to U14 audio CODEC

JP36

INT_MIC_2

1
2

ACES_85205-0200

VDDA_CODEC

R196

1 2

3K_0402_5%

AMP. FOR EXTERNAL MICROPHONE

D62

2

1

3

@

PACDN042_SOT23~D

C585

1 2

1200P_0402_50V7K@

INT_MIC_1 INT_MIC_3 INT_MIC_4

R193

1 2

3K_0402_5%

C226

1

4.7U_0805_6.3V6K

2

HLC0603CSCCR11JT_0603

C231

1 2

0.22U_0603_10V7K

1 2

68P_0402_50V8J

Place close to JP15

EXT_MICA

JP9

1
2
3
4
5
6
7
8
9
10
11
12

4.7U_0805_10V4Z

EXT_MICB

SENSE_A_B<25>

RHU002N06_SOT323

Place close to U14

2005/05/26 2006/07/26

C

C276

1 2

0.22U_0603_10V7K

J_VDDA_CODEC

R427

47K_0402_5%

2

C492

1

C275

1 2

0.22U_0603_10V7K

VDDA_CODEC

D

Q50

S

J_VDDA_CODEC

EXT_MICA_1

12

12

R429

47K_0402_5%

EXT_MICB_1

13

2

G

Compal Secret Data

L58

1 2

HLC0603CSCCR10JT_0603

R1424 0_0402_5%

R1423 0_0402_5%@

L61

1 2

HLC0603CSCCR10JT_0603

R979
47K_0402_5%

1 2

MIC_SENSE

2

C984

0.1U_0402_16V4Z

1

R418

1 2

470_0402_5%

1 2

R425

470_0402_5%

C487

10U_0805_10V4Z

Deciphered Date

1

1

2

2

12

12

1

2

R424

3.9K_0402_1%

1 2

1 2

R421

3.9K_0402_1%
C486
10U_0805_10V4Z

D

1 2

C572

1

68P_0402_50V8J

2

JJ_MIC_REF

J_MIC_REF

1 2

C575
68P_0402_50V8J

EXT_MICB

EXT_MICA

L57

C571

R211

10K_0402_5%

R210

10K_0402_5%

C230

1 2

680P_0402_50V7K

R190

MIC_REF

C446

R388

1 2

1

10K_0402_5%

2

JJ_MIC_REF

C249

EXT_MICA_2

JJ_MIC_REF

C248

EXT_MICB_2

1 2

L46

CHB1608B121_0603

1 2

L47

CHB1608B121_0603

470P_0402_50V7K

100P_0402_50V8J

J_VDDA_CODEC

1

2

100P_0402_50V8J

3
2

1

2

100P_0402_50V8J

5
6

1

C470

0.1U_0402_16V4Z

2

J_MIC_SENSE

C508

Title

Size Document Number Rev

Date: Sheet

VDDA_CODEC

1

2

+

-

J_VDDA_CODEC

+

-

1

2

3
2

U46A

8

TLV2462_SO8

P

1

O

G

4

U46B

8

TLV2462_SO8

P

7

O

G

4

1

C522
470P_0402_50V7K

2

8

+

-

4

100P_0402_50V8J

100P_0402_50V8J

Compal Electronics, Inc.

AMP & Audio Jack

LA-2952P

1 2

100K_0402_5%

1

C441

2

0.1U_0402_16V4Z

U27A

TLV2462_SO8

P

INT_MIC

1

O

G

C488

1 2

R413

1 2

100K_0402_5%

J_MIC1

C489

1 2

R414

1 2

100K_0402_5%

J_MIC2

5
4
3

6
2
1

SUYIN_010030FR006G101ZL_6P

E

26 46Wednesday, October 26, 2005

INT_MIC <25>

JP15

0.3

of

5

4

3

2

1

Left side USB CONNECTOR 0

Left side USB CONNECTOR 1

USB_VCCA

U57

1

GND

2

D D

4.7U_0805_10V4Z

C550

1

2

SLP_S5

IN

3

IN
EN#4OC#

G548A2P1U

OUT
OUT
OUT

8
7
6
5

R163

1

+

C567

2

150U_D_6.3VM

1 2

10K_0402_5%

W=80mils

USB_VCCA+5VALW

1 2
1 2

3

R6040_0603_5%

USB20_P4_R

R6050_0603_5%

2

1

USB20_P4
USB20_N4

PACDN042_SOT23~D@

USB20_N4
USB20_P4

D52

1

C515

2

0.1U_0402_16V4Z

+5VALW

USB20_N4<20>

1

USB20_P4<20>

C519

2

1000P_0402_50V7K

JP23

1

1

2

2

3

3

4

4

5

GND

6

GND

7

GND

8

GND

SUYIN_020173MR004S558ZL

SUYIN_020173MR004S558ZL

GND
GND
GND
GND

JP25

1

1

USB20_N5_R

2

2

USB20_P5_R

3

3

4

4

5
6
7
8

1 2
1 2

USB20_P5
USB20_N5

PACDN042_SOT23~D@

R6060_0603_5%

USB20_N5USB20_N4_R
USB20_P5

R6070_0603_5%

D51

USB20_N5 <20>
USB20_P5 <20>

2

3

1

Right side USB CONNECTOR 0

+5VALW USB_VCCC

U65

1

C C

1

C558

4.7U_0805_10V4Z

2

GND

2

IN

3

IN

4

EN#

TPS2061DGNRG4_MSOP8~N

SLP_S5

SLP_S5 <32,33>

OUT
OUT
OUT

OC#

8
7
6
5

R164

1

+

C569

2

150U_D_6.3VM

1 2

10K_0402_5%

W=40mils

1

2

+5VALW

C517

R6170_0603_5%

USB20_N3_R

USB20_P3
USB20_N3

PACDN042_SOT23~D@

1 2
1 2

D61

USB20_P3_R

R6140_0603_5%

3

C521

USB20_N3<20>
USB20_P3<20>

1000P_0402_50V7K

1

2

0.1U_0402_16V4Z

2

1

JP26

1

1

2

2

3

3

4

4

5

GND

6

GND

7

GND

8

GND

SUYIN_020173MR004S558ZL

BT Connector

JP22

1
2

USB20_P0_R

3

USB20_N0_R

B B

SMART Card connector

JP3

1

1

11

2

2

12

3

3

13

4

4

14

5

5

15

6

6

16

7

7

17

8

8

18

9

9

19

10

10

20

ACES_85203-1002

A A

5

SC_FCB

11

SC_CLK

12

SC_RST

13
14

SC_CD#

15
16
17
18

SC_DATA

19

SC_RFU

20

SC_FCB <24>
SC_CLK <24>

SC_RST <24>
+SC_PWR
SC_CD# <24>

SC_DATA <24>
SC_RFU <24>

4

+SC_PWR

1

2

C367

0.1U_0402_16V4Z

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/05/26 2006/07/26

Compal Secret Data

Deciphered Date

4
5
6
7
8

ACES_87212-0800

1

2

2

R458 1K_0402_5%
R459 1K_0402_5%

C306
1U_0603_10V4Z

BT_OFF<20>

R562

0_0402_5%

12

0_0402_5%

12

R586

1 2
1 2

12

R518
100K_0402_5%

1 2

47K_0402_5%

Title

Size Document Number Rev

Date: Sheet

3

Q51 SI2301BDS_SOT23

S

G

2

R454

Compal Electronics, Inc.

USB & BT Connector

USB20_P0
USB20_N0

2

D53

PACDN042_SOT23~D@

1

D

13

1

C546

2

0.01U_0402_16V7K
C556

1 2

0.1U_0402_16V4Z

LA-2952P

+3VAUX_BT

BT_LED <29,31>
CH_DATA <24>

CH_CLK <24>

+3VAUX_BT+3VALW

1

C545

0.1U_0402_16V4Z

2

1

USB20_P0 <20>
USB20_N0 <20>

1

C549

4.7U_0805_10V4Z

2

of

27 46Wednesday, October 26, 2005

0.3

A

B

C

D

E

1 1

DCD#1
RI#1
CTS#1
DSR#1

4.7K_1206_8P4R_5%

IRRX

R76
1K_0402_5%

LPC_AD0<19,24,29,30>
LPC_AD1<19,24,29,30>
LPC_AD2<19,24,29,30>

RP6

SIO_GPIO12

18

SIO_GPIO10

27

SIO_GPIO44

36

SIO_GPIO43

2 2

+3VS

+3VS

3 3

45

10K_1206_8P4R_5%

R120

1 2

R121

1 2

R119

1 2

10K_0402_5%

R68

1 2

10K_0402_5%

R77

1 2

10K_0402_5%

R79

1 2

10K_0402_5%

R80

1 2

10K_0402_5%

R100

1 2

10K_0402_5%

SIO_IRQ

10K_0402_5%

SIO_DPIO45

10K_0402_5%

CARD_ID#

PID0

PID1

SIO_GPIO11

SIO_GPIO40

NPCI_RST#<20>

PLT_RST_B#<19,24,29>

+3VS

R108 0_0402_5%

1 2

R109 0_0402_5%@

1 2

R99 10K_0402_5%

1 2

1 2

+3VS

R67 10K_0402_5%

LPC_AD3<19,24,29,30>

LPC_FRAME#<19,24,29,30>

LPC_DRQ#0<19>

PM_CLKRUN#<20,24,29,30>

CLK_PCI_SIO<15>

SIRQ<20,24,29,30>

CLK_14M_SIO<15>

SER_SHD<32>

EXPCRD_RST#<32>

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3

LPC_FRAME#
LPC_DRQ#0

SIO_RST#
SIO_PD#

PM_CLKRUN#
CLK_PCI_SIO
SIRQ
SIO_PME#

CLK_14M_SIO
SIO_GPIO40

PID0
PID1
SIO_GPIO43
SIO_GPIO44
SIO_DPIO45
CARD_ID#
SER_SHD
SIO_GPIO10
SIO_GPIO11
SIO_GPIO12
SIO_IRQ

EXPCRD_RST#

U8

10

LAD0

12

LAD1

13

LAD2

14

LAD3

15

LFRAME#

16

LDRQ#

17

PCI_RESET#

18

LPCPD#

19

CLKRUN#

20

PCI_CLK

21

SER_IRQ

6

IO_PME#

9

CLK14

CLOCK

23

GPIO40

24

GPIO41

25

GPIO42

27

GPIO43

28

GPIO44

29

GPIO45

30

GPIO46

31

GPIO47

32

GPIO10

33

GPIO11/SYSOPT

34

GPIO12/IO_SMI#

35

GPIO13/IRQIN1

36

GPIO14/IRQIN2

40

GPIO23

8

VSS

22

VSS

43

VSS

52

VSS

LPC47N217_STQFP64

Base I/O Address

0 = 02Eh
1 = 04Eh*

12

R96
10_0402_5%@

1

C94
18P_0402_50V8J

@

2

LPC I/F

GPIO

POWER

RP3

1 8
2 7
3 6
4 5

1 2

SERIAL I/F

FIR

IRMODE/IRRX3

SLCTIN#

PARALLEL I/F

ERROR#

STROBE#

CLK_14M_SIOCLK_PCI_SIO

12

R81
10_0402_5%@

1

C70
10P_0402_25V8K

@

2

RXD1

TXD1

DSR1#

RTS1#
CTS1#

DTR1#

RI1#

DCD1#

IRRX2
IRTX2

INIT#

PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7

SLCT

BUSY

ACK#
ALF#

VTR
VCC
VCC
VCC
VCC

+3VS

PE

62
63
64
1
2
3
4
5

37
38
39

41
42
44
46
47
48
49
50
51
53
55
56
57
58
59
60
61

7
11
26
45
54

RXD1
TXD1
DSR#1
RTS#1
CTS#1
DTR#1
RI#1
DCD#1

IRRX

LPTINIT#
LPTSLCTIN#
LPD0
LPD1
LPD2
LPD3
LPD4
LPD5
LPD6
LPD7
LPTSLCT
LPTPE
LPTBUSY
LPTACK#
LPTERR#
LPTAFD#
LPTSTB#

1

C84

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

RXD1 <32>

R64 1K_0402_5%

1 2

TXD1 <32>
DSR#1 <32>
RTS#1 <32>
CTS#1 <32>
DTR#1 <32>
RI#1 <32>
DCD#1 <32>

IRRX <24>
IRTXOUT <24>
IRMODE <24>

LPTINIT# <32>
LPTSLCTIN# <32>
LPD0 <32>
LPD1 <32>
LPD2 <32>
LPD3 <32>
LPD4 <32>
LPD5 <32>
LPD6 <32>
LPD7 <32>
LPTSLCT <32>
LPTPE <32>
LPTBUSY <32>
LPTACK# <32>
LPTERR# <32>
LPTAFD# <32>
LPTSTB# <32>

1

1

C76

C88

2

2

0.1U_0402_16V4Z

4.7U_0805_10V4Z

+5VS

21

D36
CH751H-40_SC76

+5VS_PRN

LPD3
LPD2
LPD1
LPD0

LPD7
LPD6
LPD5
LPD4

LPTACK#
LPTBUSY
LPTPE
LPTSLCT

LPTSTB#
LPTAFD#
LPTERR#

LPTSLCTIN#EXPCRD_RST#

+3VS

1

C57

2

LPTINIT#

RP51

1 8
2 7
3 6
4 5

4.7K_1206_8P4R_5%
RP52

1 8
2 7
3 6
4 5

4.7K_1206_8P4R_5%
RP53

1 8
2 7
3 6
4 5

4.7K_1206_8P4R_5%
RP54

1 8
2 7
3 6
4 5

4.7K_1206_8P4R_5%
R480

1 2

4.7K_0402_5%
R481

1 2

4.7K_0402_5%

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2005/05/26 2006/07/26

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

D

Date: Sheet

Compal Electronics, Inc.

SUPER I/O LPC47N217

LA-2952P

28 46Wednesday, October 26, 2005

E

0.3

of

5

4

3

2

1

BIOS ROM

+3VALW

1

+3VALW

D D

R1287

SPI_WP#

1 2

3.3K_0402_5%

R1288

SPI_HOLD#

1 2

3.3K_0402_5%

C C

C989

0.1U_0402_16V4Z

SPI_CS#<20>
SPI_CLK<20>

SPI_SI<20>

SPI_CS#<20>
SPI_CLK<20>

SPI_SI<20>

2

+3VALW

SPI_WP#
SPI_HOLD#
SPI_CS#
SPI_CLK
SPI_SI

SPI_WP#
SPI_HOLD#
SPI_CS#
SPI_CLK
SPI_SI

U66

8

VCC

3

W

7

HOLD

1

S

6

C

5

D

U61

8

VCC

3

W

7

HOLD

1

S

6

C

5

D

MX25L8005MI-15G_SO8-150mil@

4

VSS

SPI_SO_L SPI_SO

2

Q

SST25LF080A_SO8-200mil

4

VSS

SPI_SO_L

2

Q

R1291

1 2

47_0402_5%

R1291 place cloe to U66

SPI_SO <20>

+3VS

Q75

47K

DTA114YKA_SC59

10K

1 3

+3VS

2

47K

10K

1 3

2

Q88
DTA114YKA_SC59

+3VS

47K

10K

Q89
DTA114YKA_SC59

1 3

2

WL_LED

WW_LED# <24>

WL_LED# <24>

WP_LED# <24>

Mini-PCIE Card LED

RHU002N06_SOT323

BT_LED<27,31>

R505

100K_0402_5%

1 2

R504

100K_0402_5%

1 2

Q79

2

G

BLUE

13

D

S

2

G

WL_BLUE_LED#<24,31>

13

D

Q78
RHU002N06_SOT323

S

TPM1.2

Footprint need to update

Base I/O Address

0 = 02Eh

* 1 = 04Eh

LPC_PD# <20,30>

12

T87PAD
T62PAD

+3VS

12

12

TPM_32K_CLK <30>

TPM_XTALI

R1381

TPM_XTALO

10M_0402_5%

R1377

4.7K_0402_5%

R1378

4.7K_0402_5%@

C1057

12

C1056

1
4

Y8

1 2

IN
OUT

1 2

18P_0402_50V8J

32.768KHZ_12.5P_1TJS125BJ2A251

2

NC

3

NC

18P_0402_50V8J

26
23
20
17

21
22
16
27
15

7

U69

LAD0
LAD1
LAD2
LAD3

LCLK
LFRAME#
LRESET#
SERIRQ
CLKRUN#
PP

+3VS+3VALW

5

19

10

VSB

VDD24VDD

VDD

TESTB1/BADD

TPM
SLB 9635 TT 1.1

GND4GND11GND18GND

25

1

C1052

0.1U_0402_16V4Z

2

LPCPD#

TEST1
XTALO

XTALI

GPIO2

GPIO

NC
NC
NC

LPC_PD#

28
9

R1379 0_0402_5%

8

TPM_XTALO

14

TPM_XTALI

13

2
6

1
3
12

SLB9635TT_TSSOP28

TPM_GPIO2
TPM_GPIO

R101 0_0402_5%@

1 2

0.1U_0402_16V4Z

1

1

C1053

2

0.1U_0402_16V4Z

LPC_AD0<19,24,28,30>
LPC_AD1<19,24,28,30>
LPC_AD2<19,24,28,30>

+3VS

LPC_AD3<19,24,28,30>

CLK_PCI_TCG<15>
LPC_FRAME#<19,24,28,30>
PLT_RST_B#<19,24,28>
SIRQ<20,24,28,30>
PM_CLKRUN#<20,24,28,30>

1 2

R1380

B B

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3

CLK_PCI_TCG
LPC_FRAME#
PLT_RST_B#
SIRQ
PM_CLKRUN#

4.7K_0402_5%@

1

C1054

C1055

0.1U_0402_16V4Z

2

2

12

R1409

0_0402_5%

C206

+3VS

USB20_N2_R

12

USB20_P2_R

12

1

2

JP38

1

1

2

2

3

3

4

4

ACES_85205-0400

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/05/26 2006/07/26

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

2

Date: Sheet

Compal Electronics, Inc.

TCG/BIOS ROM/PS2/LED/SW

LA-2952P

1

of

29 46Wednesday, October 26, 2005

0.3

Finger printer

0.1U_0402_16V4Z

5

R1334
R1335

3

2

1

0_0402_5%

0_0402_5%

A A

USB20_N2<20>
USB20_P2<20>

PACDN042_SOT23~D@

D54

5

4

+3VL

+3VS

3

2

1

1

C37

ADP_EN<43>

C350

0.1U_0402_16V4Z

1 2

R74
2M_0402_5%@

1

Y2

IN

1

2

2

+3VL

D D

C C

B B

RP44

KSI0

1 8

KSI3

2 7

KSI2

3 6

KSI1

4 5

47K_1206_8P4R_5%

RP43

KSI7

1 8

KSI6

2 7

KSI5

3 6

KSI4

4 5

47K_1206_8P4R_5%

+5VS

R84

TP_CLK

1 2

10K_0402_5%

R85

TP_DATA

1 2

10K_0402_5%

RP5

KBD_CLK

1 8

KBD_DATA

2 7

PS2_CLK

3 6

PS2_DATA

4 5

10K_1206_8P4R_5%

Note: R94 must be removed when
R1354 stuff and R87 remove.

+3VS

R94

LPCPD#

1 2

10K_0402_5%

R1289

RUNSCI_EC#

1 2

10K_0402_5%

CLK_PCI_EC

12

R86

10_0402_5%@

2

C80

10P_0402_25V8K@

1

Pin34 250 -- LPCPD#

LPC_PD#<20,29>

10P_0402_50V8J

32.768KHZ_12.5P_1TJS125BJ2A251

0.1U_0402_16V4Z

2

KSO[0..13]<31>

Pin3 250 : KSO12/OUT8/KBRST

KSI[0..7]<31>

PM_CLKRUN#<20,24,28,29>

RUNSCI_EC#<20>

LPC_FRAME#<19,24,28,29>

R87 0_0402_5%@

1 2

R1354 0_0402_5%@

1 2

R75

120K_0402_5%

4

1

OUT

C349
10P_0402_50V8J

NC3NC

2

CLK_PCI_EC<15>

C52

TP_CLK<31>
TP_DATA<31>
KBD_CLK<32>

KBD_DATA<32>

PS2_CLK<32>

PS2_DATA<32>

SIRQ<20,24,28,29>

LPC_AD3<19,24,28,29>
LPC_AD2<19,24,28,29>
LPC_AD1<19,24,28,29>
LPC_AD0<19,24,28,29>

PLT_RST#<7,16,18,19,20,22,24>

12

1U_0603_10V4Z

1

0.1U_0402_16V4Z

2

KSO[0..13]

ACCEL_INT_KBC

+RTCVCC

2

C69

1

C51

KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11

KSO13

KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7

TP_CLK
TP_DATA
KBD_CLK
KBD_DATA
PS2_CLK
PS2_DATA

PM_CLKRUN#
SIRQ
CLK_PCI_EC
RUNSCI_EC#

LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0

LPC_FRAME#
PLT_RST#

LPCPD#
CRY1

CRY2

1

C67

0.1U_0402_16V4Z

2

1

0.1U_0402_16V4Z

2

U47

17

KSO0

16

KSO1

15

KSO2

14

KSO3

13

KSO4

12

KSO5

10

KSO6

9

KSO7

7

KSO8

6

KSO9

5

KSO10

4

KSO11

3

KSO12/GPIO00/KBRST

2

KSO13/GPIO18

25

KSI0

24

KSI1

23

KSI2

22

KSI3

21

KSI4

20

KSI5

19

KSI6

18

KSI7

26

IMCLK

27

IMDAT

29

KCLK

31

KDAT

32

EMCLK

33

EMDAT

44

CLKRUN#

46

SER_IRQ

43

PCI_CLK

59

EC_SCI#

40

LAD[3]

39

LAD[2]

37

LAD[1]

35

LAD[0]

41

LFRAME#

42

LRESET#

34

LPCPD#/GPIO23

53

XTAL1

54

XTAL2

51

VCC0

C36

1

4.7U_0805_10V4Z

2

Power Mgmt/SIRQ

32K_CLK

1

C34

2

VCC111VCC167VCC181VCC194VCC230VCC238VCC2

Keyboard/Mouse Interface

LPC

Bus

AGND

55

R91 0_0402_5%
R102 0_0402_5%@

SMSC_LPC47N250_TQFP-100P

GND92GND79GND65GND45GND36GND28GND

1 2
1 2

1

C75

0.1U_0402_16V4Z

2

47

Access Bus Interface

24MHZ_OUT/GPIO19/WINDMON

Miscellaneous

8

General Purpose I/O Interface

EA Strap#/GPIO26/KSO17

RESET_OUT#/GPIO06

ADP_EN <43>
TPM_32K_CLK <29>

1

2

OUT0

OUT1/IRQ8#

OUT7/SMI#

OUT8/KBRST

OUT9/PWM2
OUT10/PWM0
OUT11/PWM1

GPIO01
GPIO02

GPIO03
GPIO04/KSO14
GPIO05/KSO15

GPIO07/PWM3

GPIO08/RXD

GPIO09/TXD

GPIO11/AB2A_DATA

GPIO12/AB2A_CLK

GPIO13/AB2B_DATA

GPIO14/AB2B_CLK
GPIO15/FAN_TACH1
GPIO16/FAN_TACH2

GPIO17/A20M

GPIO20/PS2CLK
GPIO21/PS2DAT

GPIO24/KSO16

GPIO27

AB1A_DATA

AB1A_CLK

AB1B_DATA

AB1B_CLK

PGM Strap/GPIO25

CLOCK

32KHZ_OUT/GPIO22

PWRGD

VCC1_PWRGD

TEST PIN

DMS_LED#/GPIO10

BAT_LED#

PWR_LED#/8051TX

FDD_LED#/8051RX

KBC1021_TQFP100

C79

0.1U_0402_16V4Z

AGND FILTER

C58

1 2

A A

250@

1021@
R129

R127

R131

R128

R78

R977
R62

5

0.1U_0402_16V4Z

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/05/26 2006/07/26

Compal Secret Data

1

C78

0.1U_0402_16V4Z

2

KBC_PWR_ON

99

GREEN_BATLED#

100

BATSELB_A#

98

KBRST#

97

INV_PWM

96

FAN_PWM

95

CHGCTRL

93

FWP#

82

ON/OFFBTN_KBC#

62

LOW_BAT#

63

KSO14KSO12

64

KSO15

66

PM_RSMRST#

68

EC_GPIO8

69

EC_GPIO9

70

BATCON

71

ADP_PS1

72

EC_GPIO13

73

THM_MBAY#

74

PCI_SERR#

75

THM_MAIN#

76

A20M

77

NUM_LED#

78

SLP_S3#

80
1

MODE

57

AB1A_DATA

86

AB1A_CLK

87

AB1B_DATA

84

AB1B_CLK

85

PGM

56

EA#

83

CLK_14M_KBC

48

32K_CLK

58

PM_POK

49

PWR_GD

61

VCC1_PWRGD

60
50

Pin50 250 -- 24MHz_Out

TEST

52

Pin52 250 -- XOSEL

91

AMBER_BATLED#

88

STB_LED#

90

CAPS_LED#

89

PGM

NO SHORT PADS

FWP#

TEST

EA#

Deciphered Date

1

C81

4.7U_0805_10V4Z

2

KBC_PWR_ON <39>
GREEN_BATLED# <24>

BATSELB_A# <38>
INV_PWM

FAN_PWM <4>
CHGCTRL <37,38>

Pin82 250 -- nFWP

ON/OFFBTN_KBC# <31>
LOW_BAT# <20>
KSO14 <31>
KSO15 <31>

PM_RSMRST# <20>

BATCON <38>
ADP_PS1 <43>

THM_MBAY# <36>
PCI_SERR# <18,24>
THM_MAIN# <36>

CH751H-40_SC76

1 2

CLK_14M_KBC <15>
PM_POK <7,20>

PWR_GD <33,34,42,43>
VCC1_PWRGD <34>
ADP_ID <43>

1 2

R977 300_0402_5%

ADP_PS0 <43>
AMBER_BATLED# <24>
STB_LED# <24,31,32>
CAPS_LED# <24,31>

R62

1 2

10K_0402_5%@

R52

1 2

1K_0402_5%@

R29

1 2

1K_0402_5%@

R65

1 2

1K_0402_5%

R28

1K_0402_5%@

R78

1K_0402_5%@
R27

1K_0402_5%

2

0_0402_5%

R62 250@

+3VL

12

12

12

1 2

R140

R141 0_0402_5%

Pin83 250 -- nEA ( pull up !! )

MODE

PGM

FWP#

J3

1 2

+3VL

12

R30
10K_0402_5%

D7

21

CH751H-40_SC76

D10

2 1

CH751H-40_SC76

R31

10K_0402_5%

D6

NUM_LED# <24,31>
SLP_S3# <20,22,24,25,26,32,33,40,41>

EAPD <25,26>

AB1A_DATA <36>
AB1A_CLK <36>

AB1B_DATA <36>
AB1B_CLK <36>

A_SD <26>

Pin91 250 -- nDMS_LED

1. For normal operation:

Un-install R29,R65

2. For KBC internal ROM flash:

Install R29,R65

KB_RST# <19>

ADP_PRES <22,37,38,39,43>

12

+3VL

21

GATEA20 <19>

Pin1 250 -- TEST Pin ( NC !! )
Pin57 250 -- MODE

Pin56 250 -- PGM
Pin58 250 -- 32KHz_OUT
Pin49 250 -- Reset Out

R58 100K_0402_5%

+3VL

1 2

R59 100K_0402_5%

1 2

R60 100K_0402_5%

1 2

Remove from daughter board

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

LA-2952P

BIOS debug port
Place under KB area

+3VL

VCC1_PWRGD
EC_GPIO9

EC_GPIO8

THM_MAIN#

EC_GPIO13

ADP_PS1

AB1A_CLK
AB1A_DATA
AB1B_CLK
AB1B_DATA

CLK_14M_KBC

FWP# PM_POK

VCC1_PWRGD
NUM_LED#
STB_LED#
CAPS_LED#

4.7K_1206_8P4R_5%

R282

1 2

10_0402_5% @

R25

1 2

10K_0402_5%

+3VL

JP43

1
2
3
4
5
6

ACES_85201-0602@

R600

1 2

210K_0402_1%

R33

1 2

100K_0402_5%@

R538

1 2

100K_0402_5%@

RP1

1 8
2 7
3 6
4 5

C92

1 2

@

10P_0402_25V8K

JP31

1
2
3
4
5
6

ACES_85201-0602@

For KBC debugging used.

LPC47N1021

of

30 46Wednesday, October 26, 2005

1

+3VL

+3VL

0.3

SWITCH
BOARD.

JP18

14

14

13

13

12

12

11

11

10

10

9

9

8

8

7

7

6

6

5

5

4

4

3

3

2

2

1

1

conn@

ACES_85203-1402

28
27
26
25
24
23
22
21
20
19
18
17
16
15

28
27
26

NUM_LED#

25

CAPS_LED#

24

MUTE_LED#

23

WL_BLUE_LED#

22

KSO12

21

KSI0

20

KSI4

19

KSI5

18

KSI6

17

KSI7

16
15

WL,Vol up,Vol down,Mute,Present button

MDC 1.5 Conn.

JP32

1

AC97_SDOUT_MDC<19>
AC97_SYNC_MDC<19>

AC97_SDIN1<19>

AC97_RST#_MDC<19>

AC97_SDOUT_MDC
AC97_SYNC_MDC

R1313

AC97_SDIN1_MDC

12

33_0402_5%

AC97_RST#_MDC

GND1

3

IAC_SDATA_OUT

5

GND2

7

IAC_SYNC

9

IAC_SDATA_IN

11

IAC_RESET#

+3VS +5VS

131314141515161617171818191920

BT_LED <27,29>
NUM_LED# <24,30>
CAPS_LED# <24,30>
MUTE_LED# <26>
WL_BLUE_LED# <24,29>

2

RES0

4

RES1

6

3.3V

8

GND3

10

GND4

AC97_BITCLK_MDC

12

IAC_BITCLK

20

Connector for MDC Rev1.5

ACES_85205-07001

+3VS

TYCO_1-179396-2~D

+3VL

JP20

1

1

2

2

STB_LED#

3

3

ON/OFF#

GND
GND

4

4

KSO12

5

5

KSI1

6

6

7

7

8
9

LID_SW# <17,20>
STB_LED# <24,30,32>

On/off ,information button

+3VS

1

C5

0.1U_0402_16V4Z

2

AC97_BITCLK_MDC <19>

INT_KBD CONN.

KSI0

KSI3
KSI2

KSI5
KSI4

KSI6
KSI7
KSI1

KSO[0..15]
KSI[0..7]

JP6

48

48

47

47

46

46

45

45

44

44

43

43

42

42

41

41

40

40

39

39

38

38

37

37

36

36

35

35

34

34

33

33

32

32

31

31

30

30

29

29

28

28

27

27

26

26

25

25

conn@

ACES_85203-2402

6
7
81

6
7
81

6
7
81

24

24

23

23

22

22

21

21

20

20

19

19

18

18

17

17

16

16

15

15

14

14

13

13

12

12

11

11

10

10

9

9

8

8

7

7

6

6

5

5

4

4

3

3

2

2

1

1

KSO2

4 5

KSO4

3

KSO7

2

KSO8

KSO6

4 5

KSO3

3

KSO12

2

KSO13

KSO14

4 5

KSO11

3

KSO10

2

KSO15

KSO[0..15]<30>
KSI[0..7]<30>

KSO9

4 5

KSI6

3

KSI7

2

KSI1

100P_1206_8P4C_50V8

KSI2

4 5

KSO0

3

KSI5

2

KSI4

100P_1206_8P4C_50V8

KSI3

4 5

KSO5

3

KSO1

2

KSI0

100P_1206_8P4C_50V8

KSO15
KSO10
KSO11
KSO14
KSO13
KSO12

KSO3
KSO6
KSO8
KSO7
KSO4
KSO2

KSO1
KSO5

KSO0

KSO9

CP1

CP3

CP7

CP6

6
7

81

100P_1206_8P4C_50V8
CP5

6

7

81

100P_1206_8P4C_50V8
CP2

6

7

81

100P_1206_8P4C_50V8

Power button

+3VL

+3VL

12

R22

100K_0402_5%

ON/OFF#<32>

ON/OFF#

C23

1U_0603_10V4Z

U5F

14

SN74LVC14APWLE_TSSOP14

P

13

O12I

G

1

7

2

R26

1 2

100K_0402_5%

1U_0603_10V4Z

C11

1

2

+3VL

12

R536
100K_0402_5%

ON/OFFBTN_KBC#

13

D

2

G

S

Q70

RHU002N06_SOT323

ON/OFFBTN_KBC# <30>

1 2

D42

CH751H-40_SOD323

R8

1 2

100K_0402_5%

ON/OFFBTN#

+3VALW

TrackPoint CONN. T/P BOARD.

JP14

1

2

ON/OFFBTN# <20>

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

SP_DATA

2005/05/26 2006/07/26

3
5
7

ACES_87153-0801L

Compal Secret Data

SP_CLK

4
6
8

Deciphered Date

+5VS

+5VS

+5VS +5VS

1

C321

0.1U_0402_16V4Z

2

TP_DATA<30>

TP_CLK<30>

TP_DATA
TP_CLK

SP_DATA
SP_CLK

Title

Size Document Number Rev

Date: Sheet

JP17

1
2
3
4
5
6
7
8

ACES_87212-0800

Compal Electronics, Inc.

MDC/KBD/ON_OFF/LID

LA-2952P

1

C319

0.1U_0402_16V4Z

2

0.3

of

31 46Wednesday, October 26, 2005

A

DOCK CONN. 184PIN

L10

KC FBM-L18-453215-900LMA90T_1812

1 1

ON/OFF#<31>

MDO2+<23>
MDO2-<23>

MDO0+<23>
MDO0-<23>

D_VSYNC<16>

D_HSYNC<16>

D_DDCDATA<16>

D_DDCCLK<16>

INTEL_RED DOCK_RED
INTEL_GREEN

2 2

INTEL_BLUE

COMP<9,16>
CRMA<9,16>

LUMA<9,16>

3 3

4 4

DVI_DETECT<16>

R1404 0_0402_5%

1 2

R1428 0_0402_5%

1 2

R1429 0_0402_5%

1 2

R1430 0_0402_5%

1 2

R1431 0_0402_5%

1 2

R1432 0_0402_5%

1 2

LINE_IN_SENSE<25>

ACOCP_EN#<43>

DCD#1<28>

RI#1<28>
DTR#1<28>
CTS#1<28>
RTS#1<28>
DSR#1<28>

TXD1<28>

RXD1<28>

LPTSTB#<28>
LPTAFD#<28>

LPTERR#<28>

INTEL_BLUE<9>

BLUE<16>

ISO_PREP#<20>

INTEL_BLUE

ISO_PREP#

1000P_0402_50V7K

ON/OFF#
MDO2+

MDO2­MDO0+

MDO0­LAN_ACT#_DOCK

LANLINK_STATUS#_DOCK

D_DDCDATA
D_DDCCLK
DVI_DETECT

DOCK_GRN
DOCK_BLU

DOCK_COMP
DOCK_CRMA
DOCK_LUMA

DCD#1
RI#1
DTR#1
CTS#1
RTS#1
DSR#1
TXD1
RXD1

LPTSTB#
LPTAFD#
LPTERR#

C360

0.1U_0402_16V4Z
U52

5

VCC

1

BLUE

A

2

B

4

OE

3

GND

FSA66P5X_SC70-5

C72

12

1

2

JP30A

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17

100

18

101

19

102

20

103

21

104

22

105

23

106

24

107

25

108

26

109

27

110

28

111

29

112

30

113

31

114

32

115

33

116

34

117

35

118

36

119

37

120

38

121

39

122

40

123

41

124

42

125

43

126

44

127

45

JAE_SP03-14588-PCL03

INTEL_GREEN<9> INTEL_RED<9>

GREEN<16> RED<16>

12

1

2

P1G1

83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99

B

DOCKVINVIN

C73

1000P_0402_50V7K

DETECT
MDO3+

MDO3­MDO1+

MDO1­PWR_LED

R515 1K_0402_5%

DVI_CLK
DVI_DAT

DOCK_DVI_TX2­DOCK_DVI_TX2+

DOCK_DVI_TX1­DOCK_DVI_TX1+

DOCK_DVI_CLK­DOCK_DVI_CLK+

DOCK_DVI_TX0­DOCK_DVI_TX0+

DOCK_ADP_SIGNAL

DOCK_ID

INTEL_GREEN
GREEN

ISO_PREP#

1 2

+3VS

DOCKVIN

MDO3+ <23>
MDO3- <23>

MDO1+ <23>
MDO1- <23>

SLP_S5#_5R

DVI_CLK <16>
DVI_DAT <16>

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

DOCK_ID <20>

C366

1 2

0.1U_0402_16V4Z
U51

5

VCC

1

A

2

B

4

OE

3

GND

FSA66P5X_SC70-5

R6090_0603_5%
R6080_0603_5%

R6110_0603_5%
R6100_0603_5%

R6130_0603_5%
R6120_0603_5%

R6160_0603_5%
R6150_0603_5%

DVI_TX2- <16>
DVI_TX2+ <16>

DVI_TX1- <16>
DVI_TX1+ <16>

DVI_CLK- <16>
DVI_CLK+ <16>

DVI_TX0- <16>
DVI_TX0+ <16>

DOCK_ID

DOCK_ADP_SIGNAL

R1387

1 2

10K_0402_5%@

R1401

1 2

1K_0402_1%

C

ADP_SIGNAL

+3VS+3VS

INTEL_RED
RED

ISO_PREP#

+3VS

C365

5
1

2
4
3

FSA66P5X_SC70-5

12

0.1U_0402_16V4Z
U50

VCC
A

B
OE
GND

D

+5VALW

12

R529
100K_0402_5%

SLP_S5#_5R

13

D

Q65

2

SLP_S5<27,33>

LPTACK#<28>

LPTBUSY<28>

LPTPE<28>

LPTSLCT<28>

LPTSLCTIN#<28>

LPTINIT#<28>

USB20_N6<20>
USB20_P6<20>
USB20_N7<20>
USB20_P7<20>

SER_SHD<28>

EXPCRD_RST#<28>

LPTACK#
LPTBUSY
LPTPE
LPTSLCT
LPD7

LPD7<28>

LPD6

LPD6<28>

LPD5

LPD5<28>

LPD4

LPD4<28>

LPD3

LPD3<28>

LPD2

LPD2<28>

LPD1

LPD1<28>

LPD0

LPD0<28>

LPTSLCTIN#
LPTINIT#

SER_SHD
EXPCRD_RST#
DETECT

G

RHU002N06_SOT323

S

JP30B

46

46

47

47

48

48

49

49

50

50

51

51

52

52

53

53

54

54

55

55

56

56

57

57

58

58

59

59

60

60

61

61

62

62

63

63

64

64

65

65

66

66

67

67

68

68

69

69

70

70

71

71

72

72

73

73

74

74

75

75

76

76

77

77

78

78

79

79

80

80

81

81

82

82

165

GND

166

GND

167

GND

168

GND

169

GND

170

GND

G2

G2

RING

RING

JAE_SP03-14588-PCL03

GND
GND
GND
GND
GND
GND

128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164

P2

TIP

DOCK_MOD_RING
DOCK_MOD_TIP

128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164

171
172
173
174
175
176

P2

TIP

V_3P3_LAN

KBD_DATA
KBD_CLK
CPPE#
PS2_DATA
PS2_CLK
DOCK_HPS#

DLINE_IN_L
DLINE_IN_R

DLINE_OUT_L
DLINE_OUT_R

PCIE_TXP4
PCIE_TXN4

PCIE_C_RXP4
PCIE_C_RXN4 PCIE_RXN4

CLK_PCIE_DOCK
CLK_PCIE_DOCK#
PREP#

VA_ON#

+5VS

DOCK_MOD_TIPDOCK_MOD_RING

R527

10K_0402_5%

R1346

1 2

0_0402_5%

R1347

1 2

0_0402_5%

C555

1 2

12

JP29

2
1

ACES_85205-0200

PCIE_RXP4

12

R66
1K_0402_5%

+

22U_1206_10V4Z@

LAN_ACT#_DOCK

13

D

2

G

S

LAN_ACT#

LANLINK_STATUS#_DOCK

13

D

2

G

S

LANLINK_STATUS#

STB_LED#<24,30,31>

SWAP

KBD_DATA <30>
KBD_CLK <30>
CPPE# <15,18>
PS2_DATA <30>
PS2_CLK <30>
DOCK_HPS# <26>

DLINE_IN_L <25>
DLINE_IN_R <25>

DLINE_OUT_L <26>
DLINE_OUT_R <26>

PCIE_TXP4 <20>
PCIE_TXN4 <20>

CLK_PCIE_DOCK <15>
CLK_PCIE_DOCK# <15>
PREP# <20,23,25>

1

C59

0.1U_0402_16V4Z

2

Q62
RHU002N06_SOT323

Q63
RHU002N06_SOT323

RHU002N06_SOT323

SLP_S3#<20,22,24,25,26,30,33,40,41>

E

PCIE_RXP4 <20>
PCIE_RXN4 <20>

+3VALW

2

G

Q59

LAN_ACT# <22,23>

LANLINK_STATUS# <20,22,23>

12

R526
10K_0402_5%

PWR_LED

13

D

S

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2005/05/26 2006/07/26

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

D

Date: Sheet

Compal Electronics, Inc.

Docking CONN.

LA-2952P

32 46Wednesday, October 26, 2005

E

0.3

of

A

B

C

D

E

+1.8V to +1.8VS Transfer

VRAM

+1.8V VDD_MEM18

U10

1 1

1

C171

2

10U_0805_10V4Z

8
7
6
5

S

D

S

D

S

D

G

D

SI4800DY_SO8

RUNON

1
2
3
4

1

2

0.1U_0402_16V4Z

C160

1

C170
10U_0805_10V4Z

2

C91

1 2

0.1U_0402_16V4Z

C184

+VCCP +1.5VS

+1.5VS

1 2

0.1U_0402_16V4Z
C93

1 2

0.1U_0402_16V4Z

+VCCP+VCC_CORE

+1.8V

SLP_S5<27,32>

SLP_S5#<20,41>

SLP_S5

SLP_S5#

2

G

Q22

RHU002N06_SOT323

+5VALW

12

R135
100K_0402_5%

13

D

S

+5VALW to +5VS Transfer

2 2

1

2

3 3

8
7
6

C86

5

10U_0805_10V4Z

U9

D
D
D
D

SI4800DY_SO8

Discharge circuit

1 2

R1311 0_0402_5%@

SLP_S3

1 2

R1312

0_0402_5%

+5VS+5VALW

1

S

2

S

3

S

4

1

G

RUNON

C71

2

0.1U_0402_16V4Z

+0.9V +1.5VS+1.8V

12

R188
470_0402_5%

13

D

2

G

S

Q27
RHU002N06_SOT323

1

C77
10U_0805_10V4Z

2

2

G

Q90

RHU002N06_SOT323

12

R1310
470_0402_5%

13

D

S

RHU002N06_SOT323

RHU002N06_SOT323

+3VALW to +3VS Transfer

S
S
S
G

+2.5VS

2

G

+3VS+3VALW

1
2
3
4

1

2

0.1U_0402_16V4Z

12

R130
470_0402_5%

13

D

S

10U_0805_10V4Z

1

C132

C128

2

RHU002N06_SOT323

+3VS

12

R134
470_0402_5%

13

D

2

G

Q17

S

Q16

RHU002N06_SOT323

B+

12

R139

330K_0402_5%

J34

SHORT PADS

SLP_S3

2

G

Q18

SLP_S3 SLP_S3 SLP_S3 SLP_S3

2

G

Q14

12

13

D

S

VDD_MEM18

12

R95
470_0402_5%

13

D

S

1

2

8
7
6

C127

5

10U_0805_10V4Z

RUNON

RHU002N06_SOT323

U13

D
D
D
D

SI4800DY_SO8

12

R469
470_0402_5%

1

C120

0.01U_0402_25V7Z

2

Q21

PWR_GD <30,34,42,43>

+5VS

12

R116

470_0402_5%

13

D

2

G

S

SLP_S3SLP_S5SLP_S5

2

G

Q47

RHU002N06_SOT323

12

R151
470_0402_5%

13

D

S

SLP_S3#<20,22,24,25,26,30,32,40,41>

SLP_S3

SLP_S3#

2

G

Q19

RHU002N06_SOT323

+3VL

12

R125
100K_0402_5%

13

D

S

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2005/05/26 2006/07/26

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

D

Date: Sheet of

Compal Electronics, Inc.

DC/DC Circuits

LA-2952P

33 46Wednesday, October 26, 2005

E

0.3

R89

1K_0402_5%

VDD_MEM18

330_0402_5%

1 2

R82

2

B

330_0402_5%

1 2

1

C

Q11
PMST3904_SOT323

E

3

R37

560K_0402_5%

R281

2

B

12

+3VS+3VS

1 2
1

C

Q10

E

3

+5VS

1

PMST3904_SOT323

12

R43
180K_0402_5%

1

C47

0.1U_0402_16V4Z

2

14

U5A

P

O2I

G

SN74LVC14APWLE_TSSOP14

7

1 2

47K_0402_5%

+3VL

1

2

14

U5C

P

5

O6I

G

SN74LVC14APWLE_TSSOP14

7

R38

C25

0.1U_0402_16V4Z

+3VL+3VL

14

U5B

P

3

O4I

G

SN74LVC14APWLE_TSSOP14

1

7

C48

0.1U_0402_16V4Z

2

13

D

2

G

S

Q9
RHU002N06_SOT323

D8

CH751H-40_SOD323

1 2

J32

1 2

SHORT PADS

+3VS

12

R47
10K_0402_5%

PWR_GD

+3VL

12

1

2

PWR_GD <30,33,42,43>

R24
100K_0402_5%

C26

0.1U_0402_16V4Z

+3VL

14

U5D

P

9

O8I

G

SN74LVC14APWLE_TSSOP14

7

2

G

+3VL

12

R7
10K_0402_5%

13

D

Q3
RHU002N06_SOT323

S

VCC1_PWRGD <30>

+1.5VS

330_0402_5%

1 2

C991

0.1U_0402_16V4Z

PGD_IN

1 2

0_0402_5%@

R1306

R113

1 2

1

C

2

B

E

3

+3VS

1

2

2

R1303

+3VS +3VS

2

R122

1K_0402_5%

VCCP_POK<40>

PWR_GD

CLK_ENABLE#<15,42>

VGATE<42>

R123

1 2

0_0402_5%

R1402

1 2

0_0402_5%@

CLK_ENABLE#

1 2

0_0402_5%@

Reserve for DB-1 only

L

+2.5VS+2.5VS

R283

330_0402_5%

Q15
PMST3904_SOT323

5

U62

P

NC

G

SN74LVC1G17DBVR_SOT23-5

3

0.1U_0402_16V4Z

5

U45

P

NC

G

SN74LVC1G17DBVR_SOT23-5

3

O4I

C33

1 2

O4I

2

B

1

1

1 2
1

C

Q26

E

PMST3904_SOT323

3

Need be tune to
3msec time delay

CH751H-40_SOD323

150K_0402_1%

1 2

1 2

150K_0402_1%

11

D60

1 2

R1350

1 2

D9
CH751H-40_SOD323

R117

C87

0.47U_0603_10V7K

+3VL

14

U5E

P

O10I

G

SN74LVC14APWLE_TSSOP14

7

2

1

2

C990

0.47U_0603_10V7K

U48

2

1

2

2

G

+3VS

1

C992

0.1U_0402_16V4Z

2

5

U63

P

O4I

1

NC

G

SN74LVC1G17DBVR_SOT23-5

3

1

C993

0.1U_0402_16V4Z

5

2

P

O4I

NC

G

SN74LVC1G17DBVR_SOT23-5

3

1 2

1

Reserve for DB-1 only

L

13

D

S

R1307

0_0402_5%@

Q2
RHU002N06_SOT323

FM1

1

CF7

1

H1
HOLEA

1

H10
HOLEB

1

H15
HOLEC

PGD_IN <42>

VGATE_INTEL <7,20,42>

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2005/05/26 2006/07/26

Compal Secret Data

Deciphered Date

1

H18
HOLED

1

H27
HOLED

1

1

FM2

1

H2
HOLEA

1

H11
HOLEB

1

H16
HOLEC

1

H28
HOLED

1

CF8

1

1

H19
HOLED

FM3

H3
HOLEA

1

H12
HOLEB

1

H17
HOLEC

1

1

CF9

1

H20
HOLED

FM4

1

H4
HOLEA

1

H13
HOLEB

1

1

CF11

CF10

H5
HOLEA

H14
HOLEB

H32
HOLED

1

CF12

CF13

1

1

H6

H7

HOLEA

HOLEA

1

1

1

H21

H22

HOLED

HOLED

1

1

H33
HOLED

1

Title

Size Document Number Rev

Date: Sheet

CF14

1

1

H8

H9

HOLEA

HOLEA

1

H23
HOLED

1

H34
HOLED

1

H24

H25

HOLED

HOLED

1

1

H35

H36

HOLED

HOLED

1

1

1

1

Compal Electronics, Inc.

POK CKT

LA-2952P

H37
HOLED

1

0.3

of

34 46Wednesday, October 26, 2005

5

D D

4

3

2

1

AC
Adapter
in

ACOK

VIN

SWITCH

VS

+5VALWP

LM358
Thermal
Protector

MAINPWON

VL

+3VS

LDO
(2.5V)

+2.5VS 1A

G965

ENBL2 ENBL1

C C

B+ B+

MAX8734A

+3VALWP 4A

+5VS

PWR_GD

DC/DC

VCC SHDN#

ISL6260 &ISL6208
DC/DC

VMB

(3V/5V)

+5VALWP 4A

VIN

VS

(CPU_CORE)

+3VLP 0.1A

BQ24703
Charger

B+

B B

SLP_S3#

Battery

BATSELB_A

MAX8743
DC/DC
(1.05V/1.5V)

ENBL1/ENBL2

+1.5VSP 4.2A

+1.05V_VCCP 6.4A

CPU_CORE
( 44A)

+5VALWP

Selector
Circuit

BATSELB_A#

Battery A
6 Cell

VMB

Battery B
8 Cell

TPS51116

B+

DC/DC
(+1.8VP/+0.9VSP)

VCC

+1.8VP 7A

SWITCH

A A

SWITCHSWITCH

Battery
Connector
A

VMB_A VMB_B

Battery
Connector
B

SLP_S5#

S3/S5

+0.9VP 2A

BATT

BATT_A

BATT_B

5

4

3

Title

POWER BLOCK DIAGRAM

Size Document Number Rev

Date: Sheet

2

of

35 46Wednesday, October 26, 2005

1

A

B

C

D

PCN1

9

SINGAL

GND6

8

1 1

GND5

7

PWR1

GND4

6

GND3

4

PWR2

GND2

3

GND1

FOX_JPD113E-LB103-7F

PCN2

1

BATT+

2

SMD

3

2 2

SMC

RES

TS

GND

TYCO_C-1746706_6P

4
5

6

100_0402_5%

220P_0402_25V8K

3 3

PCN3

1

BATT+

2

SMD

3

SMC

4

B/I

5

TS

6

GND

SUYIN_20163S-06G1-K

5

1

2

EC_SMD_A

EC_SMC_A

PR4

PC143

EC_SMD_B
EC_SMC_B

AB/I_B
TS_B

ADP_SIGNAL

ADPIN

12

PR5

100_0402_5%

12

12

12

PC144

220P_0402_25V8K

1 2

12

12

1K_0402_5%

PR11
1K_0402_5%

12

PC1

100P_0402_50V8J

AB/I_A <38>

PR2
1M_0402_1%

1 2

PR10

210K_0402_1%

12

PR3
1K_0402_5%

PC145
220P_0402_25V8K

PR7

12

1 2

PR9

210K_0402_1%

PL1

FBM-L18-453215-900LMA90T_1812

1 2

PC2
1000P_0402_50V7K

12

+3VL

THM_MAIN# <30>

EC_SMD_A1
EC_SMC_A1

+3VL

VIN

12

PC3

VMB_A

12

PC4

1000P_0402_50V7K

100P_0402_50V8J

PL2

FBM-L18-453215-900LMA90T_1812

1 2

PC5
1000P_0402_50V7K

12

AB1A_DATA <30>
AB1A_CLK <30>

VMB_B

PL3

FBM-L18-453215-900LMA90T_1812

1 2

12

PC8
1000P_0402_50V7K

12

PC6

0.01U_0402_50V4Z

BATT_B

12

PC9

0.01U_0402_50V4Z

12

PR1
15K_0402_5%

BATT_A

12

PR14

100_0402_5%

4 4

12

PR15

100_0402_5%

EC_SMD_B1

EC_SMC_B1

A

THM_MBAY# <30>

AB1B_DATA <30>
AB1B_CLK <30>

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

B

2005/03/10 2006/03/10

Compal Secret Data

Deciphered Date

C

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

BATTERY CONN

LA-2821

D

36 46Wednesday, October 26, 2005

of

A

B

C

D

1 1

2 2

3 3

AC detector
High 11.689V
Low 9.879V

4 4

Airline detector
High 17.521V
Low 16.871V

1 2

PR18 47K_0402_5%

47K

PC13

47P_0402_50V8J

VIN

PQ5

DTA144EUA_SC70

47K

2

1 2

12

12

PR50

13

P2

12

PR36

12

PR40

PR45
130K_0402_1%

PC29

10K_0603_1%

12

12

PC12

0.1U_0603_16V7K

1 2

100K_0603_1%

PR39

2.15K_0402_1%

1 2

12.4K_0603_1%

12

0.022U_0402_16V7K

PQ3
AO4407_SO8

1
2
3 6

4

PR16
200K_0402_5%

PR21
150K_0402_5%

PD7

ADP_EN# <43>

12

1SS355_SOD323

CHGCTRL<30,38>

ACDET

PR34

1 2

330K_0402_5%

VL

8

PU3A

3

P

+

O

2

-

G

LM393M_SO8

4

PR46

1 2

1M_0402_5%

8

PU3B

5

P

+

7

O

6

-

G

LM393M_SO8

4

PR54

1 2

33K_0402_1%

4

REF

CATHODE

5

ANODE

LMV431ACM5X_SOT23-5

A

1

VL

PU5

8
7

5

1 2

NC
NC

P2

8
7

5

ACDRV#

ADP_PRES

PR26
191K_0402_1%

AC_CHG

1.24VREF

3
2
1

12

PR37

PC18

+3VL

10K_0402_1%

2

+3VL

AO4407_SO8

4

PR19

1 2

12

1U_0603_6.3V6M

+3VL

5

3

12

PR51

RHU002N06_SOT323

PQ4

1
2
36

0_0402_5%

AC_CHG

+3VL

BQ24703VREF

12

PR29

1 2

143K_0402_1%

12

12

PC23

1U_0603_6.3V6M

12

PC25

0.1U_0402_10V6K

PU4
SN74LVC1G17DBVR_SOT23-5

P

O4I

1

NC

G

12

PC27
@0.1U_0402_16V7K

AC_CHG <38>

13

D

PQ10

@47K_0402_1%

2

G

S

P4

PR20

0.015_2512_1%

1 2

12

PR22
100_0402_1%

1 2

PC16

1U_0603_6.3V6M

1 2

PR24
1K_0402_1%

PR25

12

1K_0402_1%

ALARM

PR27

12

100K_0402_5%

PR30

100K_0402_1%

12

PC21

PR33

4.7U_0805_6.3V6K

80.6K_0402_1%

PC24

150P_0402_50V8J

ADP_PRES <22,30,38,39,43>

+3VL

12

PR43

4.7K_0402_5%
PR47

1 2

100K_0402_5%

BQ24703VREF

12

PR49
100_0402_5%

13

D

PQ11

2

G

RHU002N06_SOT323

S

PL4

FBM-L11-322513-151LMAT_1210

1 2

ACN <43>

PU2

8

ACN

ACDRV#
ACP
ACDET

ENABLE
ACSEL
ALARM

BATDRV#
SRSET
ACSET
ACPRES27VHSP
IBAT
VREF

BATSET

BATDEP
COMP
NC1
NC2

BQ24703_QFN28

12

PR35
150_0402_1%

12

PC26

4.7U_0805_10V6K

PWM#

12

B

9

26

5
28
19

2

3
13

4

7
10
11

ALARM <38>

PL5

PQ8
RHU002N06_SOT323

2

G

BATT

12

CELLSEL# <38>

PQ2
AO4407_SO8

1
2
3 6

P2B+

PR17

0_0402_5%

1 2

12

10U_1206_25V6M

RLZ16B_LL34

ACDRV#

12

PC28

PC15

BATT

100P_0402_50V8J

4.7U_1206_25V6K
PD5

2 1

12

PR42
174K_0603_1%

12

PR48

22.6K_0402_1%

12

PR52

7.87K_0402_1%

12

PC17

1U_0805_25V4Z

DH_CHG

PQ9

13

D

RHU002N06_SOT323

2

G

S

VCC

SRN

BATP

GND

SRP

NC4
NC3

1

PC14

2

25
22
21
16
15
12
24

18

VS

20
6

1
17
23
14

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

8
7

5

4

CHG_B+

PR23

0_0402_5%

12

36

241

PQ7

SI4835BDY_SO8

578

LX_CHG

1 2

8.2UH_MPL73-8R2_4A_20%

PD8
SKS30-04AT_TSMA

2 1

SE_CHG+

SE_CHG-

BATT

12

PR38

13.7K_0603_0.1%

12

PR41
301K_0603_0.1%

12

PR44
24K_0603_0.5%

13

D

12

PR53

8.87K_0603_1%

2005/03/10 2006/03/10

S

Compal Secret Data

Deciphered Date

C

PR28

0.015_2512_1%

1 2

PR31

3K_0402_1%

PC22

1 2

0.1U_0402_16V7K

BATT

1

12

12

PR32

3K_0402_1%

PC20

PC19

2

10U_1206_25V6M

4.7U_1206_25V6K

CV=12.6V(6 CELLS LI-ION)

16.8V(8 CELL LI-ION)
CC=3A

Icharger=3A
CELLSEL# =0,Vcharger= 12.6V
CELLSEL# =1,Vcharger= 16.8V

Title

Size Document Number Rev

Custom

LA-2821

Date: Sheet

Compal Electronics, Inc.

Charger

D

37 46Wednesday, October 26, 2005

of

A

B

C

D

+3VL

1 1

+3VL

BATSELB_A

BATSELB_A#

2 2

PC31

1 2

1000P_0402_50V7K

PC33

1 2

1000P_0402_50V7K

PQ14

PR59

1 2

22K_0402_5%

PR60

1 2

PQ15

22K_0402_5%

RHU002N06_SOT323

2

G

2

G

1 2

13

D

RHU002N06_SOT323

S

13

D

S

ALARM<37>

PR57

47K_0402_5%

RHU002N06_SOT323

PQ16

13

D

S

5

1

P

INB

2

INA

G

3

2

G

PU7

4

O

74LVC1G02_04_SOT353

+3VL

1

5

PU8

P

NC

4

A2Y

G

SN74LVC1G14DCKR_SC70-5

3

ADP_PRES <22,30,37,39,43>

1

INB

2

INA

+3VL

5

1

PU9

BATSELB_A#<30>

BATSELB_A#

P

NC

4

A2Y

G

SN74LVC1G14DCKR_SC70-5

3

BATSELB_A

12

PC34

220P_0402_50V7K

PR69

220K_0402_5%

BATSELB_A#

1 2

+3VL

1 2

PR70

470K_0402_5%

+3VL

5

SN74LVC1G17DBVR_SOT23-5

PU11

P

2

O4I

NC

G

3

AC_CHG<37>

1

PR71

10K_0402_1%

1 2

PQ27

RHU002N06_SOT323

S

G

ADP_PRES

2

D

13

3 3

CHGCTRL30,37>

PD14

12

1SS355_SOD323

12

PC35

0.22U_0402_10V4Z

+3VL

CELLSEL#<37>

+3VL +3VL

PR77

100K_0402_5%

2

5

PU13

P

O4I

1

NC

G

SN74LVC1G17DBVR_SOT23-5

3

AB/I_A<36>

1 2

BATCON <30>

PR262

330K_0402_5%

PQ75

2

G

12

PR263
330K_0402_5%

13

D

S

RHU002N06_SOT323

PD17

CFET_A

2
3

RB715F_SOT323

1

12

4 4

CFET_B

I_A#

CFET_B

CELLSEL#

PQ32

2

G

RHU002N06_SOT323

2005.8.26

A

B

12

PC30

5

PU6

P

G

74LVC1G02_04_SOT353

3

@0.1U_0402_10V6K

4

O

+3VL

PU10

5

1

P

IN1

4

O

2

IN2

G

3

SN74AHC1G08DCKR_SC70

+3VL

PU12

5

1

P

IN1

4

O

2

IN2

G

3

SN74AHC1G08DCKR_SC70

12

PR76
100K_0402_5%

13

D

12

S

RHU002N06_SOT323

13

D

PQ76

2

G

S

BATT_A

BATT_B

RHU002N06_SOT323

PQ13

S

+3VL

G

PD9

2

1

PR55

1 2

100_0402_5%

D

13

3

RB715F_SOT323

2

12

PC32

RHU002N06_SOT323

12

PR58

1.5M_0402_5%

0.1U_0603_50V4Z

BATT

12

PR61
470K_0402_5%

1

C

2

B

PQ18

E

PD12

PR63

1 2

10K_0402_5%

1SS355_SOD323

RHU002N06_SOT323

12

PR68
470K_0402_5%

2

B

12

PD16

1 2

1SS355_SOD323

13

D

RHU002N06_SOT323

S

3

1

C

E

3

PR264
330K_0402_5%

PR65

1 2

10K_0402_5%

PQ23

BATT_IN

RHU002N06_SOT323

PR75

1 2

10K_0402_5%

CFET_B<43>

CFET_B

PQ31

BATT_IN

CFET_A

2

G

2

G

PQ20

2

G

13

D

S

13

D

S

12

13

D

S

BATT

PR74

10K_0402_5%

PQ28

2

G

RHU002N06_SOT323

I_A <43>

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2005/03/10 2006/03/10

PR62

PMBT2222_SOT23

470K_0402_5%

1 2

PR72

PMBT2222_SOT23

1 2

470K_0402_5%

PQ26

Compal Secret Data

Deciphered Date

C

3 6
2
1

1
2
3 6

PQ12

D

S

1 3

1 2

G

2

PD13
SKS30-04AT_TSMA

21

4

PQ21

AO4407_SO8

PQ24

AO4407_SO8

4

PD15

21

SKS30-04AT_TSMA

PR56

0_0402_5%

PD11
RLZ6.2C_LL34

2 1

RHU002N06_SOT323

BATT_IN

RHU002N06_SOT323

5

5

7

7

8

8

AO4407_SO8

8

8

7

7

5

5

RHU002N06_SOT323

RHU002N06_SOT323

BATT_IN

PD10
1SS355_SOD323

1 2

PQ17

13

D

2

G

S

PQ19

13

D

2

G

4

PQ22

AO4407_SO8

PQ25

4

PQ29

2

G

PQ30

BATT_IN

2

G

Custom

Date: Sheet

12

S

36
2
1

1
2
36

PR64

4.7K_0402_5%

12

PR66
470K_0402_5%

12

PR67
470K_0402_5%

BATT_A

BATT_B

12

PR73

4.7K_0402_5%

13

D

S

13

D

S

Title

Size Document Number Rev

Compal Electronics, Inc.

Battery selector

LA-2821

D

of

38 46Wednesday, October 26, 2005

A

B

C

D

E

+3.3V/+5V

B+

1 1

PL6
FBM-L18-453215-900LMA90T_1812

1 2

2 2

B++

1

12

PC38

2200P_0402_50V7K

PC39

2

10U_1206_25V6M

PL7

10UH_D104C-919AS-100M_20%

PQ34

1

G2

D2

2

D2

D1/S2/K

3

G1

D1/S2/K

4

D1/S2/K

S1/A

AO4916_SO8

12

+5VALWP

1

PR88

+

1 2

1 2

10.2K_0402_1%

@

PR92

0_0402_5%

PC47

2

150U_B2_6.3VM

3 3

B++

PR90

47K_0402_5%

12

12

PC48

0.1U_0603_25V7K

0.1U_0603_50V4Z

5HG

8
7
6
5

LX_5V<43>

DL5

PC36

1 2

PR78

0_0402_5%

1 2

LX5

DH5

12

PC52

0.1U_0603_16V7K

RHU002N06_SOT323

1 2

1 2

0_0402_5%@
PR91

MAINPWON

VL

12

PR97
499K_0402_1%

PR79
0_0402_5%

BST5A

2VREF_1999

1 2

PQ36

1 2

PR89
0_0402_5%

2VREF_1999

PR93
0_0402_5%

13

D

S

3

2

PD18
CHP202U_SC70

1

B++

PR81

4.7_1206_5%

12

VL

PC43

4.7U_1206_25V6K

12

PC45

4.7U_0805_10V4Z

18

14

BST5

LD05

16

DH5

15

LX5

19

DL5

21

OUT5

MAX1999EEI_QSOP28

9

FB5

1

N.C.

6

SHDN#

4

ON5

3

ON3

12

SKIP#

8

REF

12

23

PC50

0.22U_0603_10V7K

+3VL

12

PR98
100K_0402_5%

2

G

13

D

PQ37

S

RHU002N06_SOT323

2

G

GND

PC51

12

20

PU14

12

0.1U_0603_50V4Z

PC46

13

V+

TON

LDO3

25

+3VLP

12

4.7U_0805_10V4Z

VL

PR80

1 2

47_0402_5%

12

17

VCC

ILIM3

ILIM5
BST3

DH3
DL3
LX3

OUT3

FB3

PGOOD

PRO#

10

1 2

KBC_PWR_ON <30>

12

2VREF_1999

PC44

1U_0805_16V7K

5

11
28

26
24
27
22

7
2

PR95
0_0402_5%

BST3BBST5B

PC40

0.1U_0603_16V7K

PR83

1 2

200K_0402_1%

PR86

1 2

499K_0402_1%

+3VLP

PR84

1 2

PR87

1 2

12

100K_0402_5%

PR242

200K_0402_1%

499K_0402_1%

PR82
0_0402_5%

1 2

BST3A

+3VALWP

PJP1

2 1

PAD-OPEN 2x2m

PC37

0.1U_0603_50V4Z

1 2

DH3

B++

12

PC41

0_0402_5%

2200P_0402_50V7K

PR85

12

PC42

4.7U_1206_25V6K

1 2

PQ35

1

D2

2

D2

3

G1

4

S1/A

AO4916_SO8

3HG

LX3

DL3

D1/S2/K
D1/S2/K
D1/S2/K

8

G2

7
6
5

12

PL8

4.7UH_PLFC0745-4R7_3A_30%

+3VALWP

1

+

PC49

2

150U_B2_6.3VM

1 2

1 2

PR94

3.57K_0402_1%@

PR96

0_0402_5%

+3VL

RHU002N06_SOT323

13

D

PQ77

2

G

S

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

ADP_PRES <22,30,37,38,43>

2005/03/01 2006/03/01

C

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

B

D

Date: Sheet

3.3V / 5V
LA-2541

0.3

of

39 46Wednesday, October 26, 2005

E

A

1

12

PC53

2

DH_1.05V_2

DL_1.05V

SLP_S3#

+5VALW

1 2

0_0402_5%

2200P_0402_50V7K

PR123

CHP202U_SC70

PC59

0.1U_0603_50V4Z

@0_0402_5%

1 2

PR119

100K_0402_5%

PR122
47K_0402_5%

1 2

12

PC71

+5VALWP

+3VALWP

+2.5VSP

1 1

PQ38

AO4422_SO8

PL10

12

PR106

5.1K_0402_1%

12

PR107
100K_0402_1%

3.3UH_MPL73-3R3_6A_20%

12

PQ40

AO4702_SO8

+1.05V_VCCP

1

12

+

PC63

2 2

3 3

PC64

2

220U_B2_2.5VM

4.7U_0805_6.3V6K

5

D8D7D6D

S1S2S3G

4

5

D8D7D6D

S1S2S3G

4

SLP_S3#<20,22,24,25,26,30,32,33,41>

1.5VSP/ +1.05V_VCCP/+2.5VALWP

PJP2

+0.9VP

1 2

PAD-OPEN 3x3m
PJP4

PAD-OPEN 4x4m

1 2

PJP6

PAD-OPEN 4x4m

1 2

PJP8

1 2

PAD-OPEN 3x3m

+1.5VSP

+1.8VP

+1.05V_VCCP

4 4

+1.5VS

(4A,160mils ,Via NO.=8)

(7A,280mils ,Via NO.= 14)

+1.8V

(6A,240mils ,Via NO.= 12)

+VCCP

+0.9V

A

(2A,80mils ,Via NO.= 4)

PC54

10U_1206_25V6M

1 2

PR103

2.2_0402_5%

PR110

12

2

G

@0.001U_0402_50V7M

13

B

1

PD19

3

2

1 2

BST_1.05V_2

PR101

0_0402_5%

12

DH_1.05V_1
LX_1.05V

VCC_MAX8743

13

D

2

G

S

PQ43

D

RHU002N06_SOT323

PQ44

S

RHU002N06_SOT323

PJP3

1 2

PAD-OPEN 4x4m
PJP5

1 2

PAD-OPEN 4x4m

PJP9

2 1

PAD-OPEN 2x2m

B

1U_0805_50V4Z

PC56

BST_1.05V_1

PC60

25
26
27

24
28

1
2

11

MAX8743EEI_QSOP28

C

MAX8743_B+

PR100

9

VDD

UVP

BST2

DH2
DL2

CS2

OUT2

FB2

ON2

PGOOD

TON

ILIM2
ILIM1

REF

10

0_0402_5%

0_0402_5%

12

PC69

12

LX2

PR113

PR114

100K_0402_1%

0.22U_0603_10V7K

+5VALW

12

PC55

4.7U_1206_16V4Z

BST_1.5V_2

1 2

12

PR118

PC62

0.1U_0603_50V4Z

12

PR104
0_0402_5%

LX_1.5V

PR108

0_0402_5%

100K_0402_1%

12

PR102

0_0402_5%

1 2

BST_1.5V_1

PR117

DH_1.5V_1

12

21
19

18
17
20
16

15
14
12

7
5

13
3

12
12

Fine tune power sequence

10U_1206_6.3V6M

DL_1.5V

PQ42

PC134

1
2
3
4

VCCP_POK <34>

RHU002N06_SOT323

+3VALW

2 1
12

SLP_S3#<20,22,24,25,26,30,32,33,41>

2005/03/10 2006/03/10

Compal Secret Data

Deciphered Date

C

AO4916_SO8

D2
D2

D1/S2/K

G1

D1/S2/K
D1/S2/K

S1/A

DH_1.5V_2

PJP11
PAD-OPEN 2x2m

PR99

0_0402_5%

0.1U_0603_50V4Z

PU15

@0_0402_5%

+5VALW

+3VALW

1 2

12

20_0603_5%

VCC_MAX8743

12

12

PC61

4

22

1U_0805_16V7K

BST1

V+

8

OVP

12

PR120

VCC

SKIP

GND

6

23

2VREF

12

DH1
LX1

DL1
CS1

OUT1
FB1

ON1

PR116

0_0402_5%

(4.5A,180mils ,Via NO.= 9)

(3A,120mils ,Via NO.= 6)

(1A,40mils ,Via NO.= 2)

+2.5VS

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

8

G2

7
6
5

PQ39

13

D

S

PQ41

RHU002N06_SOT323

PR243

10K_0402_5%

1 2

PL11

3.3UH_PLFC0745-3R3_4.8A_30%

1 2

PR109

@0_0402_5%

2

G

12

100K_0402_5%

47K_0402_5%

13

D

2

G

S

PU26

VIN2VO

1

EN

5

GND

6

GND

G965-18P1U_SO8

SLP_S3#

PR112

PR115

12

D

PL9

FBM-L11-322513-151LMAT_1210

12

12

PC57

2200P_0402_50V7K

12

PC58

4.7U_1206_25V6K

B+

+1.5VSP

1

+

PC66

2

220U_B2_2.5VM

12

12

PC70

@0.001U_0402_50V7M

PR121
0_0402_5%

12

PR105

5.1K_0402_1%

12

PR111

10K_0402_1%

+5VALW

12

SLP_S3# <20,22,24,25,26,30,32,33,41>

+2.5VSP

3
4

ADJ

7

GND

8

GND

Title

2.5VALW/1.5VS/1.05VCCP

Size Document Number Rev

Custom

LA-2821

Date: Sheet

12

PR244
13K_0603_1%

12

PR245
12K_0402_1%

12

PC135
10U_1206_6.3V6M

Compal Electronics, Inc.

D

40 46Wednesday, October 26, 2005

of

5

D D

+1.5VS

12

PR124

0_1206_5%

12

PC75

10U_0805_10V4Z

C C

+0.9VP

V_DDR_MCH_REF<7,13,14>

12

12

PC79
22U_1206_6.3V6M

PR127

0_0402_5%

1 2

PC76

10U_0805_10V4Z

12

+5VALW

B B

PC81

0.033U_0402_16V7K

4

23

24

1

2

3

4

5

6

8

9

VLDOIN

VTT

VTTGND

VTTSNS

GND

MODE

VTTREF

TPS51116RGE_QFN24

COMP

VDDQSNS

VDDQSET

7

NC

CS_GND

17

25

Thermal pad

12

NC

VBST

DRVH

DRVL

PGND

V5FILT

PGOOD

V5IN

15

PU17

LL

CS

S5

S3

3

PR125

0_0402_5%

BST_1.8V_1 BST_1.8V_2

1 2

PR126

0_0402_5%

DH_1.8V_1

22

21

20

19

18

16

14

13

11

10

1 2

12

PC82

LX_1.8V

DL_1.8V

PR131

0_0402_5%

4.7U_0805_10V6K
PR132
0_0402_5%@

PR133

0_0402_5%

PR134

@0_0402_5%

PC74

0.1U_0603_50V4Z

1 2

DH_1.8V_2

12

PC83

0.001U_0402_50V7M

12

12

12

12

2

5

PQ45

D8D7D6D

AO4422_SO8

S1S2S3G

4

2.2UH_IHLP-2525CZ-01_8A_+-20%_2525CZ

1 2

5

D8D7D6D

PQ46
AO4702_SO8

S1S2S3G

4

12

PR129

20K_0603_1%

PR130

3_0402_5%

12

SLP_S5# <20,33>

SLP_S4# <20>

SLP_S3# <20,22,24,25,26,30,32,33,40>

SLP_S5# <20,33>

DDR_B+

PC72

2200P_0402_50V7K

PL13

FBM-L11-322513-151LMAT_1210

1

12

PC73
10U_1206_25V6M

2

PC78

+5VALWP

220U_B2_2.5VM

1

PL12

12

B+

+1.8VP

1

+

2

12

PC80

22P_0402_50V8J

14K_0402_1%
PR128

12

12

PC84

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2005/03/10 2006/03/10

3

12

PC85

@0.001U_0402_50V7M

Compal Secret Data

Deciphered Date

@0.001U_0402_50V7M

Title

Size Document Number Rev

B

2

Date: Sheet

Compal Electronics, Inc.

1.8V/0.9VS

LA-2821

12

10K_0402_1%
PR135

41 46Wednesday, October 26, 2005

1

of

8

7

6

5

4

3

2

1

+CPU_B+

H H

PQ50

SI7840DP_SO8

+CPU_B+

PR149
10_0603_5%

4
3
5
6

28
29
30
31
32
33
34

37
36

1

2
38
35
12
13

11

10

9

8

12

0.01U_0402_25V7K
PC106

19

20

VSS

VDD
VR_TT#
RBIAS
NTC
SOFT

VID0
VID1
VID2
VID3
VID4
VID5
VID6

DPRSTP#
DPRSLPVR
PSI#
PGD_IN
CLK_EN#
VR_ON
VSEN
RTN

VDIFF

FB

COMP

VW

DROOP

14

PR190

12

PC127

330P_0402_50V7K

1 2

18

VIN

PU19

DFB15VO

12

+3VS

1 2

39

40

3V3

PGOOD

PWM1

ISEN1

PWM2

ISEN2

CS_GND

FCCM

PWM3

ISEN3

OCSET

VSUM

16

PR191

1K_0402_1%

PR155

1.91K_0603_1%

1 2

PR156
0_0402_5%

ISL6260CRZ-T_QFN40

PWM1

27

ISEN1

23

PWM2

26

ISEN2

22

41

24

25

21

7

VSUM

17

12

PR186

PC123

4.53K_0402_1%

VO

12

VGATE_INTEL<7,20,34>

VGATE <34>

PR177

12

0_0402_5%

PC122

1 2

1 2

0.22U_0603_16V7K

12

0.1U_0402_16V7K

PC126

PH3

+5VS

PR181

12

11.5K_0402_1%

12

PR185

3K_0402_1%

1000P_0402_50V7K

12

12

PR189

10KB_0603_5%_ERTJ1VR103J

@1K_0402_1%

G G

+5VS

10_0603_5%

PR152

1 2

12

PH2

12

12
12
12
12

PR171

PR174

PR178

12

51K_0603_1%

PC125

12

12

12

12

12

PC118

PC108

1U_0603_10V6K

12

PC119

PR183

0_0402_5%

PR187

12

NTC

12

12

12

6.19K_0603_1%

F F

PC109

NTC

12

0.01U_0402_16V7K

H_PROCHOT#<4>

E E

CPU_VID0<5>
CPU_VID1<5>
CPU_VID2<5>
CPU_VID3<5>
CPU_VID4<5>
CPU_VID5<5>
CPU_VID6<5>

H_DPRSTP#<4,19>

DPRSLPVR<7,20>

D D

H_PSI#<5>

PGD_IN<34>

CLK_ENABLE#<15,34>

PWR_GD<30,33,34,43>

PR160

4.22K_0603_1%

0.015U_0402_16V7K

147K_0402_1%

12

VCCSENSE<5>

+VCC_CORE

PR180

10_0402_1%

VSSSENSE<5>

C C

B B

10_0402_1%

12

PR179

12

PR182

180_0603_1%

12

PC124

1 2

220P_0402_25V8K

1800P_0402_50V7K

0_0402_5%

PR159

12

PC115

470KB_0402_5%_ERTJ0EV474J

12

PR162

12

0_0402_5%

PR164

12

0_0402_5%

PR166

12

0_0402_5%

PR169

12

0_0402_5%

PR172

12

0_0402_5%

PR176

12

0_0402_5%

1000P_0402_50V7K

PC120

1 2

1 2

PC121

0.022U_0402_16V7K

6.98K_0402_1%

PR158

PR161

0_0402_5%

PR163

0_0402_5%

PR165

0_0402_5%

PR168

0_0402_5%

499_0402_1%

0_0402_5%

0_0402_5%

1000P_0402_50V7K

PR184

1.2K_0402_1%

1000P_0402_50V7K
PR188

12

PC104

1U_0603_10V6K

+5VS

12

PU18

5

VCC

6

FCCM

2

PWM

3

GND

ISL6208CRZ-T_QFN8

+5VS

PC114

1U_0603_10V6K

5
6
2
3

PU20

VCC
FCCM
PWM
GND

ISL6208CRZ-T_QFN8

BOOT

UGATE

PHASE
LGATE

BOOT
UGATE
PHASE
LGATE

0_0402_5%

BST_CPU1_1

1
8
7
4

BST_CPU2_1

1

8

7

4

PR148

DH_CPU1
LX_CPU1

DL_CPU1

PR157

0_0402_5%

DH_CPU2
LX_CPU2

12

DL_CPU2

BST_CPU1_2

PC105

0.22U_0603_16V7K

1 2

12

BST_CPU2_2

0.22U_0603_16V7K

1 2

SI7840DP_SO8

PC116

PQ52

FDS6676AS_SO8

PQ54

PQ56

3 5

241

5

D8D7D6D

S1S3G

S

4

2

3 5

241

5

D8D7D6D

S1S3G

S

4

2

FDS6676AS_SO8

PQ53

FDS6676AS_SO8

D8D7D6D

S1S3G

S

2

D8D7D6D

S1S3G

2

12

12

PC100

PC101

0.01U_0402_50V4Z

2200P_0402_50V7K

5

4

12

PC110

PC111

0.01U_0402_50V4Z

2200P_0402_50V7K

5

PQ57

S

4

FDS6676AS_SO8

1

12

2

PC102

4.7U_1206_25V6K

PL16

.36UH_MPC1040LR36_ 24A_20%

1 2

PR151

10K_0402_1%

1 2

PR153

5.11K_0402_1%

1 2

VSUM

12

1

12

2

PC112

4.7U_1206_25V6K

.36UH_MPC1040LR36_ 24A_20%

PR170

10K_0402_1%

1 2

PR173

5.11K_0402_1%

1 2

VSUM

PL15

FBM-L18-453215-900LMA90T_1812

1 2

PC103
10U_1206_25V6M

PC107

0.22U_0603_16V7K

12

PR154

12

@0_0402_5%

+CPU_B+

PC113
10U_1206_25V6M

PL17

1 2

PC117

0.22U_0603_16V7K

12

PR175

@0_0402_5%

12

1 2

VO

PR150
10_0402_1%

1 2

VO

PR167
10_0402_1%

B+

+VCC_CORE

+VCC_CORE

A A

8

7

6

5

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4

2005/03/10 2006/03/10

Compal Secret Data

Deciphered Date

3

Compal Electronics, Inc.

Title

Size Document Number Rev

C

LA-2821

Date: Sheet

2

CPU_CORE

42 46Wednesday, October 26, 2005

of

1

5

PU22A

8

D D

PR196

1 2

LM358A_SO8

0_0402_5%

1

3

P

+

0

2

-

G

4

PR195

12

P4

1 2

0_0402_5%

10K_0402_1%

1 2

PR199

PR197

6.81K_0402_1%

1 2

100K_0603_0.5%

12

PC130

1U_0805_50V4Z

C C

B+

ADP_SIGNAL

PR258

PR241

10K_0402_1%

VIN

12

12

VIN

12

12

PR224

22.6K_0402_1%

PR236
10K_0402_1%

12

PR223

12

12

PR240

0_0402_5%

180K_0402_1%

PR229
1M_0402_5%

1 2

PR235
10K_0402_1%

29.4K_0402_1%

13

D

2

G

PQ65

S

@RHU002N06_SOT323

5

B B

A A

12

PC132

0.1U_0402_16V7K

12

PR212
0_0402_5%

PQ62

NDS0610_SOT23

S

G

5
6

D

13

2

3
2

1M_0402_5%

8

+

-

4

2005.8.20

VIN

+

-

1 2

PU25B

P

O

G

LM393M_SO8

4

PU22B

5

+

6

PR200

-

LM358A_SO8

1 2

PC129

0.22U_0603_16V7K

PU23

CATHODE

2

B

NC
NC

C

E

3 1

4

REF

5

ANODE

LMV431ACM5X_SOT23-5

ADP_PRES <22,30,37,38,39>

PR217

47.5K_0402_1%

1 2

8

PU25A

P

1

O

G

LM393M_SO8

4

PR238

7

12

PR237

47K_0402_5%

PD23

1 2

1SS355_SOD323

ADP_EN# <37>

4

7

0

3
2
1

PQ61
MMBT3904_SOT23

I_A <38>

CFET_B <38>

12

PR221
10K_0402_5%

VIN

12

PR231
220K_0402_5%

3

12

PR259
1M_0402_1%

12

PR202

2K_0402_5%

E

3

B

12

12

PR260

PR206

PR210

7.87K_0402_1%

12

422_0603_1%

PD25

39.2K_0402_1%

S

2

D

1 3

NDS0610_SOT23

2

G

G

PQ73

12

13

D

S

2005.8.24

12

1SS355_SOD323

+3VALW

ADP_ID <30>

12

PR230
47K_0402_5%

ADP_EN <30>

13

D

PQ64

2

G

12

RHU002N06_SOT323

S

Security Classification

PR239

Issued Date

220K_0402_5%

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

PQ58

2

C

1

MMBT3906_SOT23

PR261
1M_0402_1%

PQ74
RHU002N06_SOT323

100K_0402_5%

12

12

3.9K_0402_5%

PR233

1 2

PR194

330K_0402_5%

8

PU21B

5

P

+

O

6

-

G

LM393M_SO8

4

PR201

1 2

0_0402_5%

PR207

3.9K_0402_5%

PD22

@CH751H-40_SOD323

1 2

PWR_GD <30,33,34,42>

1

PR214

2

PC147

3900P_0402_50V7K

1U_0603_16V6K

2

B

2005/03/10 2006/03/10

3

+3VS

12

12

7

PR215

1 2

470K_0402_5%

12

12

PC146

PR225
100K_0402_5%

1 2

C

PQ63

MMBT3904_SOT23

E

3 1

Compal Secret Data

Deciphered Date

PR256

10K_0402_5%

13

D

2

G

S

PR265
47K_0402_5%

ACN <37>

12

PR192
133K_0402_1%

12

PR205

80.6K_0402_1%

PR211

1 2

0_0402_5%

PQ60
RHU002N06_SOT323

PR216

470K_0402_5%

+3VS

12

12

12

PC131

PR222

71.5K_0402_1%

2

+5VS

3
2

12

0.027U_0603_16V7K

OCP# <4,20>

ACOCP_EN#<32>

12

PR228
21K_0603_1%

PR234

3.48K_0402_1%

2

PR193

1 2

100K_0402_5%

8

PU21A

P

+

O

-

G

LM393M_SO8

4

1 2

12

PC133

0.1U_0603_16V7K

1

PD20

CH751H-40_SOD323

1

PR203
604K_0603_1%

VIN

+5VS

12

PR257

10K_0402_5%

DTA144EUA_SC70

1 2

PQ70

12

12

1 2

PD21

CH751H-40_SOD323

PC128

1U_0805_16V7K

PR208
10_0402_5%

LX_5V <39>

13

PD28

47K

47K

2
12

PR254

150K_0402_5%

PD27

1SS355_SOD323

PR255

1 2

1 2

1K_0402_5%

+5VS

PR219

1M_0402_5%

PR220

10K_0402_5%

1 2

PR232

21K_0603_1%

1 2

1 2

3

+

2

-

+5VS

PR226

1M_0402_5%

1 2

5

+

6

-

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

LA-2821

1 2
12

ADP_SIGNAL

PD26

1 2

1SS355_SOD323

8

PU24A

P

1

O

G

LM393M_SO8

4

8

PU24B

P

7

O

G

LM393M_SO8

4

ADP_OCP

1SS355_SOD323

PR253
210K_0402_1%

+3VS

12

+3VS

12

PR227
10K_0402_5%

1

PQ72

D

1 3

G

2

12

220K_0402_5%

PR251

1 2

13

D

S

of

S

+5VS

PD24

1SS355_SOD323

RHU002N06_SOT323

12

PR252

220K_0402_5%

NDS0610_SOT23

+3VS

PQ71

2

G

ADP_PRES <22,30,37,38,39>

PR218
10K_0402_5%

ADP_PS0 <30>

ADP_PS1 <30>

43 46Wednesday, October 26, 2005

1

EE PIR list

06/01/2005 schematics review start :

06/02/2005

Page38 : Add R58,R59,R60 ,those are removed from daughter board
Page39 : JP18 pin3 change from ground to BT_LED
Page37 : Remove JP16 & change debug port interface to JP44

1 1

Page27 : ICH7M pin R7 change to +3VS
Page32 : JP44 PLT_RST# change to PLT_RST_B# to reduce the loading
Page33 : Update audio amp to MAX9710

06/03/2005

Page10 : Add R260 to reduce one 330U cap C666
Page25 : 1. R27 change to +3VS

2..Add R1035 for H_DPSLP#
Page26 : 1.Add T80 for GPIO25

2. GPIO21 change net name to VGARST#

3. Add T88 for GPIO23

4. Add T89 for GPIO26

5. GPIO30 change net name to USB_OC#6

6. GPIO31 change net name to USB_OC#7

7. Add R1036/7 for RESET option

8. Remove the connection of USB_OC#3/4/5

Page24 : Add ALS_EN on JP35 pin24 for light sensor
Page32 : 1.JP13 change to 90 pins connector

2.Add U72 for ESD protection

2 2

06/04/2005

Page10 : A. U71 change to U43D (the fourth gate in U43)
B. Add +3VS_TVBG R/C filters & voltage follower D12,D21,R127,R520
Page34 : audio change-- add R1419 ,R431,R434,R435 for BIASA/B/C

Page35 : Add JP3 for Smart card FFC connector
Page18 : 1.R1365 CHANGE TO 2K_0402_1%

2. R1366 change to 562_0402_1%

3. R1367 change to 1.47K_0402_1%
Page31 : JP4 update to RJ45 connector
Page15 :Add the connection for UMA VGA clock , & SRC0/2 SWAP

1.Add R1148/R1149 , R1129/R1132 , R1118/R1121

2.Add R1242/R1248,R1253/R1272
Page09 : Change 0 ohm resistors before filters ,

and delete the other group of filtes at page 19
Page16 : add R671~R678 ,R530,R531 for DVI

Page19 : Swap I2C bus for LVDS/Thermal sensor

06/07/2005

3 3

Page47 : PQ34 pin5/6/7 change netname to LX_5V
Page38 : Pin96: INVPWM rename to OUT9 & add T90
Page36 : Delete R500 & rename to EXPCRD_RST#
Page35 : Add JP3 for Smart card FFC connector

06/08/2005

Page7 : Delete PD resistor R1340~R1343.
Page17 : Update JP35 LVDS connector
Page26 : A. GPIO28 ==Delete R1321 & A_SD , change to VGA_RST#

B. GPIO21 ==Change to MB_PWR
C. GPIO19 ==Change to PD

06/09/2005

Page17 : Delete Q56 ,R510 ,Caymus support 3V PWM
Page25 : Update Q92 to AOS4407
Page26 : Delete R252
Page37 : Add PD RP42,R273

4 4

Delete Cardbus 6612 circuit & move to daughter board LS-2953

2

3

06/11/2005

Page28: 1.Delete R15 ,due to Internal PD

2.Delete R69 ,due to Internal PD

3. Add U70,U71,R69,R92 R1297 for serial falsh support.

Page19 : Add T8/T9 for GPIO10/14
Page23 : Change L1,L2,L63,L6,L7,L9,L11-16,L65,L66 to FB
Page30 : Disconnect the I2C bus / WL_LED#/WP_LED# on JP46
Page10 : 1. Add R504/R505 for VCC_SYNC

2. Add R490/R491 for VCCTX_LVDS

3. Add R494 for VCCA_CRTDAC

4. Add R492/R493 for VCCA_LVDS

5. Add R495 for +3VS_TVBG

6. Add R500 for +3VS_TVDACA

7. Add R502 for +1,5VS_TVDAC

7. Add R499 for +3VS_TVDACB

8. Add R496 for +3VS_TVDACC
Page09 : 1.Add R460,R461, R550,R552,R553 for CRT discrete/uma option

2. Add R462,R463,R464 for TV discrete/uma option

06/13/2005

Page23 : Add R6 R15,R106,R128,R129 GPIO PD

06/14/2005

Page21 : Change L1,L2,L63 to FB
Page16 : 1. Add C174,C150,C142,C371,C358 for DVI

2. R103 change to 1%
Page35 : U69 pin7 change to PD

06/15/2005

Page04 : R1265 change to 51_0402_5% & install
Page07 : Install R1344
Page28 : Delete U70 ,reserve U71 for 200 mil
Page35 : Delete U61 , resevre U66 for 200 mil
Page29 : Update U7 symbol pinB7/B8/C8

06/16/2005

Page36 : Delete R32 ,double PU
Page41 : Delete R180,Q49 ,the same function for +1.8VS
Page10 : Delete C982 for Lead-free
Page20 : Add C570 for Lead free
Page32 : 1,Delete Q28 .

2. D49,D50 change to U73

3. Add C577,C581 for Lead free
Page33 : Add R163,R164,R165 for USB power switch PU
Page26 : Separate PCIE_WAKE# to NIC/Mini-card PCIE_WAKE# to avoid battery mode can't enter S3 issue
Page23 : Delete L65,C270,C269,C271 for M52-T
Page18~23 : ATI VGA controller change to M52T

06/22/2005

Page09 : Add R554 , R555 for CRT disable
Page10 : 1. Add R508,R510 for VCCD_LVDS1/1/2

2. R504,R505 chnage for +2.5VS_GMCH,&delete R490,R491,R492,R493
Page30 : Delete JP48,49 & change screw holes

06/23/2005

Page16 : Change SDVOB_INT+/- net name to PEG_RXP1/N1
Page10 : 1.R505 / R510 for M52 , R504 / R508 for UMA

2. R499,R500,R496 connect to +1.5VS for diable CRT
Page36: Delete R49 & CB_CLK

Page25: JP42 change to wire to board connector
Page19: 1.Add CRT,TV filters for M52T

2. Add DVI BOM option 0 ohm
Page16 : Move 0 ohm to TV-out connector for TV

Page38 : Move 0 ohm to docking connector for CRT

4

5

06/24/2005

Page19 : Add LVDS L-shape BOM option resistors
Page10 : Enable TV/ CRT when using 945PM
Page9 : Enable TV/ CRT when using 945PM

06/25/2005

Page33 : Delete U58, R165,C568,C1,C312,C311 FOR LAYOUT SPACE

06/27/2005

Change All 2N7002_SOT23 to RHU002N06_SOT323 to save layout space

06/28/2005

Page40 : Change Q10,Q11,Q15,Q26 from SOT23 to SOT323
to save layout space
Page37 : 1 . Update JP20 to 6 pin connector

2. Update JP20 & JP18 pin assignments to follow Taos

06/30/2005

Page28 : Y1 update to smaller package 6x3.5
Page25 : Y4 update to smaller package 14M-J
Page15 : Y3 update to smaller package 6x3.5

07/01/2005

Page23 : Add HW strpping pin on DVPDATA20,21,22,23 for VRAM ID0,1,2,3
Page33 : U57 change to 2A current limit power switch G548

07/04/2005

Page17 : Add R131 for inverter PWM when ATI PWM issue
Page19 : 1. Add R49 , R189 for 1.2V voltage divider

2. Add Q12 for M52_therm# & change to GPIO14
Page32 : The limitation for 5 pin audio jack can't switch
headphone/docking line-out ,so add R1420,R1421,C526,R252
Delete R256,R255,C536.

Page39 : Delete C984~C988
Page33 : Delete C527
Page10 : Delete C823 reserved pad
Page25 : Add JP5 slim type ODD connector

07/12/2005

Page25 : Add C629,C630,C631 for SATA connector
Page33 : Swap JP3 samrt card pin assignment for FFC

07/14/2005

Page25 : Add R133 100 ohm to avoid RTC short
Page15 : 1. clock gen. pin 5 change to connect to +ck_vdd_dp

2. C731,C732,C733 change from 0.1u to 0.01u

3. C361,C364 change from 33p to 27p

07/19/2005

Page39 : Add C91,C93,C181 for low speed signal

07/20/2005

Page30 : Add R1422 pad for XMIT_OFF

06/10/2005

Page17 : Add R458,R459 for ch_data,ch_clk
Page33 : Add C367 0.1U for +SC_PWR

1

2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/05/26 2006/07/26

Compal Secret Data

Deciphered Date

4

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

H/W2 EE Dept. PIR SHEET

LA-2952P

5

of

44 46Wednesday, October 26, 2005

0.3

1

For DB2 Modification

08/11/2005

Page31/32 : Update Audio portion for jack sensing
Page35 : Delete LED circuit & connect to LS-2953 directly
Page11 : Change R1154 to NI
Page30 : Add C554 for UIM power

1 1

Page25 : Delete JP37 MB2 conector
Page19 : Change C611 to NI ,R662 to 0 ohm for clcok spectrum
Page15 : Add R1136 PD for clk_pcie_m52 ,R1084 change to NI
Page24 : R1388 change to Install
Page26 : R1364 change to NI
Page36 : R1354 change to NI

08/15/2005

Page30 : R1418 , R1360 change to NI

08/19/2005

Page35 : Delete FWH , SPI change to +3VALW
Page36 :Delete R538
Page10 : Delete L39
Page25 : Add D15, D16 , R90 , R88 for HDD LED

08/20/2005

2 2

Page30 : Change +3VL / Caps_LED# to Pin45/51
Page38 : Delete R551 ,R548,R549,R541
Page25 : Add D15,D16,R88,R90 for HDD_LED
Page30 : Add SW1 C986, R521 , D65,D66 for SIM power off

08/24/2005

Page15 : Add C353~C372 for clk cap

08/25/2005

Page31/32 : Add JP16 for audio cable

2

10/04/2005

Page32 : Reserve C555

10/06/2005

Page24: NI D64 ,install R1355

3

4

5

Page07: NI R1202,R1203
Page22: NI R1397,U36

；

Install Q94；Add R1076
Page29:Reserve U61
Page24:Add R1364

；

Reserve R1363
Page30:Install R91
Page24:Add R1366

10/07/2005

Page24: Add R1071,R1073

；

Reserve R1365

Page07: NI R1209
Page22: Install R275,R289
Page20: Install R1384,R1395

Del Q71,R1345
Page20: Add R1040,R871

Page22 : Add R1091,R1082,R1088,R1085,Q105,R1023,
R1024,D63,C1042,U55,R1021,R1076
Reserve Q103,Q104,R1090,
Del R601.
Page15 : Del R1084,R1136

10/08/2005

Page28 :Install Q103；NI R1091

10/13/2005

Page33 :Delete J33

；

NI R1396,R1398

；

Reserve R1385,R1427

；

Reserve Q106；Del R1404

；

Page18 :Delete BIOS_SEL jump

10/26/2005

Page26 :NI C526
Page32 :Add R1404,R1428,R1429,R1430,R1431,R1432,

R609,R608,R611,R610,R613,R612,R616,R615
Page31 :Install CP1~CP6

Page30 : Internal MIC signal change to JP13

08/26/2005

Page32 : Add R427,R429,C492 for J_MIC_REF

08/29/2005

Page32 : Add 1423,R1424 for MIC_REF , & MIC_SENSE connection
Page23 : R154 change to NI
Page29 : Add C333 for NIC

08/30/2005

3 3

Page15 : Add C373 for clk_debug_port

Page23 : Add R173 for Therm_SCI#
Page36 : R538 change to NI
Page21 : Add C140, C172 , C141 , L17 for VDDPLL

08/31/2005

Page32 : Delete R1419, R1420
Page19 : R189 change to 56_0402_1%

10/04/2005

Page26 : R251.2/C526.1 connect to DLINE_OUT_L
Page32 : PR255.1 connect to pin 29 of the docking connector.

(ACOCP_EN#)
Page29 : Add discharge circuit for BT_LED and WL_LED(R504,R505)
(this issue occurs when there is no WLAN card)

Page20 : Delete R1323 (EAPD to ICH7)
Page22 : Add Q40,R1419, reserve R1420

4 4

Page24 : Add R996,reserve R519,Q41,Q42
Page29 : Install R1409, Make R1380 NI
Page30 : Reserve R91,R102
Page27 : Change R454 to 47K , add C556
Page25 : Install R136
Page15 :Delete R1071,R1073,R1076,R1082,R1094,R1096,R1258,R1260

R1112,R1116,R1250,R1252,R1124,R1127,R1134,R1137,R1238
R1239,R1242,R1248,R1253,R1272(NOLP@)

1

；

reserve R101

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

2

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/05/26 2006/07/26

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

4

Date: Sheet

Compal Electronics, Inc.

H/W2 EE Dept. PIR SHEET

LA-2952P

5

of

45 46Wednesday, October 26, 2005

0.3

5

4

Version Change List ( P. I. R. List ) for Power Circuit

3

2

1

Item Issue DescriptionDate

D D

1

8/26/2005
(DB)

Owner

HP To implement 4 cell main battery

Add PR2,PR259,PR261(1M ohm),
Add PQ73,PQ74,PQ75,PQ76(RHU002N06_SOT323)
Add PR260(39.2k)

2

48

50

3

8/30/2005
(DB)

10/18/2005
(SI)

HP To fix VDD_CORE in 1V(Only for Discrete).

HP Changes for OCP circuit

Remove PQ49,PQ66

Add PC147 3900pF capacitor across PR214
Change PR207 from 0 Ohm to 3.9K_5%
Change PC131 from 0.22uF to 0.027uF
Change PR203 from 649K to 604K_1%
Change PR221 from 47K to 10K_5%
Add a newPR265 47K_5% resistor in series with PR216-2
Add a new PC146 1uF X7R capacitor from PR216-2 to GND
Change PC133 from 10uF to 0.1uF X7R

C C

Change PR228 from 10K to 21K_1%
Change PR234 from 11.5K to 3.48K_1%
Change PR232 from 3.3K to 21K_1%

4

43

10/18/2005
(SI)

HP sets Max charge current to 3.75A Change PR29 from 100K to 143K_1%

Solution Description Rev.Page# Title

DB42,44,50

DB

SI

SI

Request

B B

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/03/01 2006/03/01

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

PWR PIR Sheet (1)

LA-2541

1

0.3

of

46 46Wednesday, October 26, 2005