Compal LA-2931P HGW51, Aspire 5030 Schematic

A

1 1

2 2

B

C

D

E

Compal Confidential

HGW51 Schematics Document

AMD/Sempron/ATI RS482M/SB450

3 3

4 4

A

2005 / 08 / 18 For C test

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev:0.3

2005/05/09 2006/03/08

C

Compal Secret Data

Deciphered Date

D

Title

Cover Sheet

Size Document Number Rev

Custom

LA-2931

Date: Sheet

148Thursday, August 18, 2005

E

of

0.3

A

Compal confidential

B

C

D

E

Project Code: HGW51
File Name : LA-2931

1 1

Thermal Se nsor
ADM1032ARM

page 4 page 15

CRT & TV-OUT

page 16

Clock Generator
ICS951412

AMD Turion/Sempron CPU

page 4,5,6,7

H_A#(3..31)

ATI-RS482M

705 BGA

page 11,12,13,14

H_D#(0..63)

HT 16x16 800MHZ

DDR-1

One Channel DDR-1

DDRI-SO-DIMM X2

BANK 0, 1, 2, 3

page 8,9,10

A-Link Express

LCD CONN

2 x PCIE

page 17

2 2

ATI-SB450

PCI BUS

Mini PCI
Socket

page 31

3 3

Realtek

RTL8100CL

page 26

RJ45 CONN

page 26

ENE Controller

CB714

page 24

Slot 0

page 25

6in1 CardReader
Slot

page 25

1394 Controller

VT6311S

page 27

1394
Conn.

page 27

LPC BUS

564 BGA

page 18,19,20,21

USB 2.0

USB 2.0

AC-LINK

SATA

PATA

USB conn x 3

BT Conn

page 35

page 30

Audio CKT
AD1888

page 28

MDC Conn.

page 30

SATA HDD Conn.

page 23

HDD Conn.
CDROM Conn.

page 23

AMP & Audio Jack

page 29

RJ11 CONN

page 26

Power On/Off CKT.

page 36

DC/DC Interface CKT.

page 37

RTC CKT.

page 18

SMsC LPC47N207

page 32

ENE KB910L

page 33

Power Circuit DC/DC

4 4

Button

page 36

page 39~48

LED

A

Power OK CKT.

page 36

B

FIR module

page 32

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Touch Pad
CONN.

2005/05/09 2006/03/08

C

page 30

Compal Secret Data

Deciphered Date

Int. KBD

page 30

BIOS

page 34

Title

Block Diagrams

Size Document Number Rev

Custom

LA-2931

D

Date: Sheet

248Thursday, August 18, 2005

E

0.3

of

A

Voltage Rails

Power Plane Description

1 1

2 2

VIN
B+
+CPU_CORE
+1.05VS
+DDRVTT 0.9V switched power rail for DDR terminator
+1.5VALW 1.5V always on power rail
+1.5VS
+1.8VS 1.8V switched power rail
+DDRVCC
+2.5VS
+3VALW
+3V
+3VS
+5VALW
+5VS
+5VMO D 5 V sw i tc he d po we r rail for Module Bay
+12VALW 12V always on power rail
+RTC V C C RTC power

Adapter power supply (19V)
AC or batte ry power rail for power circuit.
Core voltage for CPU

1.05V switched power rail

1.5V switched power rail

1.8V power rail for DDR

2.5V switched power rail

3.3V always on power rail

3.3V power rail

3.3V switched power rail
5V always on power rail
5V switched power rail

B

S1 S3 S4/ S5

N/A N/A N/A

ON OFF
ON OFF
ON OFF OF F
ON
ON OFF OF F
ON OFF OF F
ON
ON
ON
ON
ON
ON

ON ONON

N/AN/AN/A
OFF
OFF

ON*ON

OFF

ON

OFF

OFF
ON ON*

OFF

ON
OFF

OFF

ON

ON*

OFF

OFFON
OFF OFFON
ONON ON*

C

STATE

Full ON

SIGNAL

SLP_S1# SLP_S3#

HIGH HIGH HIGH HIGH

S1(Power On Suspend)

S3 (Suspend to RAM)

S4 (Suspend to Disk)

S5 (Soft OFF)

Board ID Table for AD channel

Vcc 3.3V +/- 5%

Board ID

0
1
2
3
4
5
6
7 NC

100K +/- 5%Ra / Rc

Rb / Rd V min

0

8.2K +/- 5%
18K +/- 5%
33K +/- 5%
56K +/- 5%
100K +/- 5%
200K +/- 5%

D

SLP_S4# SLP_S5# +VA LW +V +VS Clock

ON

LOW

LOW

LOW

HIGH

LOW LOW LOW LOW

AD_BID

0 V

HIGHHIGHHIGH

HIGH

HIGH

LOWLOWLOW

ON

ON

ON

ON

Vtyp

AD_BID

0 V 0 V

0.216 V 0.250 V 0.289 V

0.436 V

0.712 V

1.036 V

0.503 V

0.819 V

1.185 V 1.264 V

1.453 V 1.650 V 1.759 V

1.935 V

2.500 V

2.200 V

3.300 V

ON

ON

ON

OFF

OFF

V

AD_BID

0.538 V

0.875 V

2.341 V

3.300 V

E

ON ON

ON

OFF

OFF

OFF

LOW

OFF

OFF

OFF

max

Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.

External PCI Devices

Device IDSEL # REQ # / GNT # Interrupts

CardBus

1394
SD

Mini-PCI

LAN

3 3

AD20
AD16 0
AD20
AD18
AD22 3

EC SM Bus1 address

Device

Smart Battery
EEPROM(24C16/02)

(24C04)

Address Address

1010 000X b
1011 000Xb

2

2
1

PIRQE/PIRQH
PIRQE
PIRQE/PIRQH
PIRQF
PIRQG

EC SM Bus2 address

Device

ADM1032

1001 110X b0001 011X b

BOARD ID Table

Board ID

0
1
2
3
4
5
6
7

PCB Revision

0.1

0.2

BTO Item BOM Structure

BTO Option Table

SB450 SM Bus address

Device

4 4

Clock Generator
(ICS 951412AGT)

DDRII DIMM0
DDRII DIMM2

A

Address

1101 001Xb

1001 000Xb
1001 010Xb

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2005/03/08 2006/03/08

C

Compal Secret Data

Deciphered Date

Title

Notes

Size Document Number Rev

Custom

EFL50 LA-2761

D

Date: Sheet

348Thursday, August 18, 2005

E

0.3

of

A

B

C

D

E

H_CADIP15
H_CADIN15
H_CADIP14
H_CADIN14
H_CADIP13
H_CADIN13
H_CADIP12
H_CADIN12
H_CADIP11
H_CADIN11
H_CADIP10
H_CADIN10
H_CADIP9
H_CADIN9
H_CADIP8
H_CADIN8
H_CADIP7
H_CADIN7
H_CADIP6
H_CADIN6
H_CADIP5
H_CADIN5
H_CADIP4
H_CADIN4
H_CADIP3
H_CADIN3
H_CADIP2
H_CADIN2
H_CADIP1
H_CADIN1
H_CADIP0
H_CADIN0

H_CLKIP1
H_CLKIN1
H_CLKIP0
H_CLKIN0

H_CTLIP1
H_CTLIN1
H_CTLIP0
H_CTLIN0

R646

44.2_0603_1%

H_CADIP[0..15]
H_CADIN[0..15]

T25
R25
U27
U26
V25

U25
W27
W26

AA27
AA26
AB25
AA25
AC27
AC26
AD25
AC25

T27

T28

V29

U29

V27

V28

Y29
W29

AB29
AA29
AB27
AB28
AD29
AC29
AD27
AD28

Y25
W25

Y27

Y28

R27

R26

T29

R29

AF27

AE26

LVREF0

12

U50A

Claw Hammer-DTR

L0_CADIN_H15
L0_CADIN_L15
L0_CADIN_H14
L0_CADIN_L14
L0_CADIN_H13
L0_CADIN_L13
L0_CADIN_H12
L0_CADIN_L12
L0_CADIN_H11
L0_CADIN_L11
L0_CADIN_H10
L0_CADIN_L10
L0_CADIN_H9
L0_CADIN_L9
L0_CADIN_H8
L0_CADIN_L8
L0_CADIN_H7
L0_CADIN_L7
L0_CADIN_H6
L0_CADIN_L6
L0_CADIN_H5
L0_CADIN_L5
L0_CADIN_H4
L0_CADIN_L4
L0_CADIN_H3
L0_CADIN_L3
L0_CADIN_H2
L0_CADIN_L2
L0_CADIN_H1
L0_CADIN_L1
L0_CADIN_H0
L0_CADIN_L0

L0_CLKIN_H1
L0_CLKIN_L1
L0_CLKIN_H0
L0_CLKIN_L0

L0_CTLIN_H1
L0_CTLIN_L1
L0_CTLIN_H0
L0_CTLIN_L0

L0_REF1
L0_REF0

FOX_PZ75403-2941-42

CONN@

L0_CADOUT_H15

L0_CADOUT_L15

L0_CADOUT_H14

L0_CADOUT_L14

L0_CADOUT_H13

L0_CADOUT_L13

L0_CADOUT_H12

L0_CADOUT_L12

L0_CADOUT_H11

L0_CADOUT_L11

L0_CADOUT_H10

L0_CADOUT_L10

L0_CADOUT_H9

L0_CADOUT_L9

L0_CADOUT_H8

L0_CADOUT_L8

L0_CADOUT_H7

L0_CADOUT_L7

L0_CADOUT_H6

L0_CADOUT_L6

L0_CADOUT_H5

L0_CADOUT_L5

L0_CADOUT_H4

L0_CADOUT_L4

L0_CADOUT_H3

L0_CADOUT_L3

L0_CADOUT_H2

L0_CADOUT_L2

L0_CADOUT_H1

L0_CADOUT_L1

L0_CADOUT_H0

L0_CADOUT_L0

HTT Interface

L0_CLKOUT_H1

L0_CLKOUT_L1

L0_CLKOUT_H0

L0_CLKOUT_L0

L0_CTLOUT_H1

L0_CTLOUT_L1

L0_CTLOUT_H0

L0_CTLOUT_L0

LDTSTOP_L

H_CADIP[0..15]<11>

4 4

3 3

+1.2V_HT

R642 49.9_0402_1%

1 2

R643 49.9_0402_1%

1 2

+1.2V_HT

2 2

H_CLKIP1<11>
H_CLKIN1<11>
H_CLKIP0<11>
H_CLKIN0<11>

H_CTLIP0<11>
H_CTLIN0<11>

R645 44.2_0603_1%

12

LVREF1

H_CADOP[0..15]
H_CADON[0..15]

H_CADOP15

N26

H_CADON15

N27

H_CADOP14

L25

H_CADON14

M25

H_CADOP13

L26

H_CADON13

L27

H_CADOP12

J25

H_CADON12

K25

H_CADOP11

G25

H_CADON11

H25

H_CADOP10

G26

H_CADON10

G27

H_CADOP9

E25

H_CADON9

F25

H_CADOP8

E26

H_CADON8

E27

H_CADOP7

N29

H_CADON7

P29

H_CADOP6

M28

H_CADON6

M27

H_CADOP5

L29

H_CADON5

M29

H_CADOP4

K28

H_CADON4

K27

H_CADOP3

H28

H_CADON3

H27

H_CADOP2

G29

H_CADON2

H29

H_CADOP1

F28

H_CADON1

F27

H_CADOP0

E29

H_CADON0

F29

H_CLKOP1

J26

H_CLKON1

J27

H_CLKOP0

J29

H_CLKON0

K29
N25

P25

H_CTLOP0

P28

H_CTLON0

P27

LDTSTOP#

AJ27

H_CADOP[0..15] <11>
H_CADON[0..15] <11>H_CADIN[0..15]<11>

H_CTLOP0 <11>
H_CTLON0 <11>

1 2

R644 680_0402_5%

LDTSTOP# <13,18>

H_CLKOP1 <11>
H_CLKON1 <11>
H_CLKOP0 <11>
H_CLKON0 <11>

+2.5VS

EN_DFAN1<33>

0.1U_0402_16V4Z

C698

1U_0603_10V4Z

C696

EN_DFAN1

1

2

R641

1

2

3

+IN

2

-IN

100K_0402_5%

1 2

12

150K_0402_5%

FAN Conn

+VSB

8

U3A

P

FAN1

1

OUT

G

LM358A_SO8

4

C697

2200P_0402_50V7K

1 2

R640

D25

RB751V_SOD323

+VSB

+5VS

6

2

1

D

Q47

G

3

S

SI3456DV-T1_TSOP6

4 5

FANVOUT1

2

1

C700

C1

2 1

22U_1206_10V4Z

1

2

0.001U_0402_50V7M

+3VS

12

1

＠

2

JP43

ACES_85205-0300

CONN@

R639
10K_0402_5%

C699

0.01U_0402_16V7K

1
2
3

5

+IN

OUT

6

-IN

FAN_SPEED1 <33>

U3B

7

LM358A_SO8

+3VS

1

2

THERMDA_CPU
THERMDC_CPU

THERMDA_CPU

THERMDC_CPU
EC_SMB_CK2
EC_SMB_DA2

from EFL50

U53

2

D+

3

D-

8

SCLK

7

SDATA

ADM1032ARM_RM8

1

C702

0.1U_0402_16V4Z

2

VDD1

ALERT#

THERM#

GND

1
6

THERM#

4
5

THERMDA_CPU<6>
THERMDC_CPU<6>

C703

2200P_0402_50V7K

EC_SMB_CK2<33>

1 1

EC_SMB_DA2<33>

Thermal Sensor
ADM1032

12

R647

10K_0402_5%@

SMBus Address: 1001110X (b)

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2005/05/09 2006/03/11

C

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

D

Date: Sheet of

Claw Harmmer CPU (Host Bus)

LA-2931

448Thursday, August 18, 2005

E

0.3

A

B

C

D

E

+2.5V

DDR_SDQ[0..63]<8>

1 1

2 2

3 3

DDR_SDM[0..7]<8>

DDR_SDQS[0..7]<8>

+1.25VREF_CPU

50 mil width

R64834.8_0603_1%

12

R64934.8_0603_1%

12

DDR_SDQ63
DDR_SDQ62
DDR_SDQ61
DDR_SDQ60
DDR_SDQ59
DDR_SDQ58
DDR_SDQ57
DDR_SDQ56
DDR_SDQ55
DDR_SDQ54
DDR_SDQ53
DDR_SDQ52
DDR_SDQ51
DDR_SDQ50
DDR_SDQ49
DDR_SDQ48
DDR_SDQ47
DDR_SDQ46
DDR_SDQ45
DDR_SDQ44
DDR_SDQ43
DDR_SDQ42
DDR_SDQ41
DDR_SDQ40
DDR_SDQ39
DDR_SDQ38
DDR_SDQ37
DDR_SDQ36
DDR_SDQ35
DDR_SDQ34
DDR_SDQ33
DDR_SDQ32
DDR_SDQ31
DDR_SDQ30
DDR_SDQ29
DDR_SDQ28
DDR_SDQ27
DDR_SDQ26
DDR_SDQ25
DDR_SDQ24
DDR_SDQ23
DDR_SDQ22
DDR_SDQ21
DDR_SDQ20
DDR_SDQ19
DDR_SDQ18
DDR_SDQ17
DDR_SDQ16
DDR_SDQ15
DDR_SDQ14
DDR_SDQ13
DDR_SDQ12
DDR_SDQ11
DDR_SDQ10
DDR_SDQ9
DDR_SDQ8
DDR_SDQ7
DDR_SDQ6
DDR_SDQ5
DDR_SDQ4
DDR_SDQ3
DDR_SDQ2
DDR_SDQ1
DDR_SDQ0

DDR_SDM7
DDR_SDM6
DDR_SDM5
DDR_SDM4
DDR_SDM3
DDR_SDM2
DDR_SDM1
DDR_SDM0

DDR_SDQS7
DDR_SDQS6
DDR_SDQS5
DDR_SDQS4
DDR_SDQS3
DDR_SDQS2
DDR_SDQS1
DDR_SDQS0

MEMZN
MEMZP

AG12

D14
C14

A16
B15
A12
B11
A17
A15
C13
A11
A10

C11

AC1
AC3

AC2
AD1
AE1
AE3
AG3

AJ4

AE2

AF1

AH3

AJ3
AJ5
AJ6

AJ7
AH9
AG5
AH5

AJ9

AJ10

AH11

AJ11

AH15

AJ15

AG11

AJ12
AJ14
AJ16

A13

AA1
AG1
AH7

AH13

A14

AB1

AJ2

AJ8

AJ13

B9
C7
A6

A9
A5
B5
C5
A4
E2
E1
A3
B3
E3

F1
G2
G1

L3

L1
G3

J2

L2
M1
W1
W3

W2

Y1

R1

A7

C2

H1

T1

A8

D1

J1

U50B

MEMVREF1
MEMZN

MEMZP
MEMDATA63

MEMDATA62
MEMDATA61
MEMDATA60
MEMDATA59
MEMDATA58
MEMDATA57
MEMDATA56
MEMDATA55
MEMDATA54
MEMDATA53
MEMDATA52
MEMDATA51
MEMDATA50
MEMDATA49
MEMDATA48
MEMDATA47
MEMDATA46
MEMDATA45
MEMDATA44
MEMDATA43
MEMDATA42
MEMDATA41
MEMDATA40
MEMDATA39
MEMDATA38
MEMDATA37
MEMDATA36
MEMDATA35
MEMDATA34
MEMDATA33
MEMDATA32
MEMDATA31
MEMDATA30
MEMDATA29
MEMDATA28
MEMDATA27
MEMDATA26
MEMDATA25
MEMDATA24
MEMDATA23
MEMDATA22
MEMDATA21
MEMDATA20
MEMDATA19
MEMDATA18
MEMDATA17
MEMDATA16
MEMDATA15
MEMDATA14
MEMDATA13
MEMDATA12
MEMDATA11
MEMDATA10
MEMDATA9
MEMDATA8
MEMDATA7
MEMDATA6
MEMDATA5
MEMDATA4
MEMDATA3
MEMDATA2
MEMDATA1
MEMDATA0

MEMDQS17
MEMDQS16
MEMDQS15
MEMDQS14
MEMDQS13
MEMDQS12
MEMDQS11
MEMDQS10
MEMDQS9
MEMDQS8
MEMDQS7
MEMDQS6
MEMDQS5
MEMDQS4
MEMDQS3
MEMDQS2
MEMDQS1
MEMDQS0

Claw Hammer-DTR

DDR Memory

A CHANGEL ADDRESSB CHANGEL ADDRESS

MEMCKEA
MEMCKEB

MEMCLK_H7

MEMCLK_L7

MEMCLK_H6

MEMCLK_L6

MEMCLK_H5

MEMCLK_L5

MEMCLK_H4

MEMCLK_L4

MEMCLK_H3

MEMCLK_L3

MEMCLK_H2

MEMCLK_L2

MEMCLK_H1

MEMCLK_L1

MEMCLK_H0

MEMCLK_L0

MEMCS_L7
MEMCS_L6
MEMCS_L5
MEMCS_L4
MEMCS_L3
MEMCS_L2
MEMCS_L1
MEMCS_L0

MEMRASA_L
MEMCASA_L

MEMWEA_L

MEMBANKA1
MEMBANKA0

MEMADDA13
MEMADDA12
MEMADDA11
MEMADDA10

MEMADDA9
MEMADDA8
MEMADDA7
MEMADDA6
MEMADDA5
MEMADDA4
MEMADDA3
MEMADDA2
MEMADDA1
MEMADDA0

MEMRASB_L
MEMCASB_L

MEMWEB_L

MEMBANKB1
MEMBANKB0

MEMADDB_B13
MEMADDB_B12
MEMADDB_B11
MEMADDB_B10

MEMADDB_B9
MEMADDB_B8
MEMADDB_B7
MEMADDB_B6
MEMADDB_B5
MEMADDB_B4
MEMADDB_B3
MEMADDB_B2
MEMADDB_B1
MEMADDB_B0

MEMCHECK7
MEMCHECK6
MEMCHECK5
MEMCHECK4
MEMCHECK3
MEMCHECK2
MEMCHECK1
MEMCHECK0

AE8
AE7

D10
C10
E12
E11
AF8
AG8
AF10
AE10
V3
V4
K5
K4
R5
P5
P3
P4

D8
C8
E8
E7
D6
E6
C4
E5

H5
D4
G5

K3
H3

E10
AE6
AF3
M5
AE5
AB5
AD3
Y5
AB4
Y3
V5
T5
T3
N5

H4
F5
F4

L5
J5

E9
AF6
AF4
M4
AD5
AC5
AD4
AA5
AB3
Y4
W5
U5
T4
M3

N3
N1
U3
V1
N2
P1
U1
U2

DDR_CKE0
DDR_CKE1

DDR_CLK7
DDR_CLK7#
DDR_CLK6
DDR_CLK6#
DDR_CLK5
DDR_CLK5#
DDR_CLK4
DDR_CLK4#

DDR_SCS#3
DDR_SCS#2
DDR_SCS#1
DDR_SCS#0

DDR_SMAA13
DDR_SMAA12
DDR_SMAA11
DDR_SMAA10
DDR_SMAA9
DDR_SMAA8
DDR_SMAA7
DDR_SMAA6
DDR_SMAA5
DDR_SMAA4
DDR_SMAA3
DDR_SMAA2
DDR_SMAA1
DDR_SMAA0

DDR_SMAB13
DDR_SMAB12
DDR_SMAB11
DDR_SMAB10
DDR_SMAB9
DDR_SMAB8
DDR_SMAB7
DDR_SMAB6
DDR_SMAB5
DDR_SMAB4
DDR_SMAB3
DDR_SMAB2
DDR_SMAB1
DDR_SMAB0

DDR_CKE0 <8>
DDR_CKE1 <9>

DDR_CLK7 <8>
DDR_CLK7# <8>
DDR_CLK6 <9>
DDR_CLK6# <9>
DDR_CLK5 <8>
DDR_CLK5# <8>
DDR_CLK4 <9>
DDR_CLK4# <9>

DDR_SCS#3 <9>
DDR_SCS#2 <9>
DDR_SCS#1 <8>
DDR_SCS#0 <8>

DDR_SRASA# <8>
DDR_SCASA# <8>
DDR_SWEA# <8>

DDR_SBSA1 <8>
DDR_SBSA0 <8>

DDR_SMAA[0..13] <8>

DDR_SRASB# <9>
DDR_SCASB# <9>
DDR_SWEB# <9>

DDR_SBSB1 <9>
DDR_SBSB0 <9>
DDR_SMAB[0..13] <9>

DDR_CLK5/5# & DDR_CLK7/7#
route to nearest DIMM
DDR_CLK4/4# & DDR_CLK6/6#
route to farthest DIMM

R650 120_0402_5%

DDR_CLK6
DDR_CLK5
DDR_CLK4

1 2

R651 120_0402_5%

1 2

R652 120_0402_5%

1 2

R653 120_0402_5%

1 2

within 1.00"

+2.5V

12

R654
1K_0402_1%

12

1

C704

R655
1K_0402_1%

2

0.1U_0402_16V4Z

DDR_CLK7#DDR_CLK7
DDR_CLK6#
DDR_CLK5#
DDR_CLK4#

+1.25VREF_CPU

1

C705
1000P_0402_50V7K

2

4 4

A

FOX_PZ75403-2941-42

CONN@

B

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2005/03/01 2006/03/11

C

Compal Secret Data

Deciphered Date

D

Title

Size Document Number Rev

Custom

Date: Sheet

Claw Harmmer (Memory Bus)

LA-2931

E

548Thursday, August 18, 2005

of

0.3

A

H_RST_CPU#

R656

H_RST#<18>

1 1

CPUCLK0_H<15>

CPUCLK0_L<15>

Place 169 Ohm within 0.5" from CPU
Route as DIF 5/5/5/20

+2.5VDDA

2 2

+2.5VS

R660 680_0402_5%

1 2

1 2

0_0402_5%

C709
3900P_0402_50V7K

169_0402_1%

C719 3900P_0402_50V7K

L47
LQG21F4R7N00_0805

1 2

1

+

C730
100U_D2_10VM

2

4.7U_0805_6.3V6K

H_PWRGD

1

C720

470P_0402_50V7K@

1

C706

0.001U_0402_50V7M@

2

12

12

Route as DIFF pair 10/5/10

1

C731

2

H_PWRGD<18>

12

R657

CPU_COREFB<46>
CPU_COREFB#<46>

3300P_0402_50V7K

1

C732

2

0.22U_0603_10V7K

R658 80.6_0402_1%

Place within 0.5" from CPU
Route as 80 Ohm DIFF impedence 8/5/20

+VDDA_CPU

1

C733

2

T4PAD
T6PAD
T8PAD

H_THERMTRIP_S#

H_RST_CPU#

R100

1 2

0_0402_5%

12

CPU_COREFB
CPU_COREFB#

VDDIOFB_H
VDDIOFB_L
VDDIO_SENSE

50 mils width

VID4<46>
VID3<46>
VID2<46>
VID1<46>
VID0<46>

H_PWRGD_R

CLKIN
CLKIN#
FBCLKOUT
FBCLKOUT#

VID4
VID3
VID2
VID1
VID0

2

THERMDA_CPU<4>
THERMDC_CPU<4>

+1.2V_HT

JOPEN@

1 2

H_RST#

R663

100_0402_5%

@

J3

use plane

as heavy as possible

1

3 3

+2.5VS

1 2

R157 680_0402_5%

0.22U_0603_10V7K

H_RST#

D

S

C737

2

13

SUSP

2

G

Q55

2N7002_SOT23@

1

0.22U_0603_10V7K

2

T17PAD
T18PAD

SUSP <37>

8/9 modify close to U50

4 4

1

C738

C739

4.7U_0805_6.3V6K

2

+1.25V +1.25V

TP_K8_A28
TP_K8_AJ28

B

U50C

A20

THERMTRIP_L

AF20

RESET_L

AE18

PWROK

AJ21

CLKIN_H

AH21

CLKIN_L

AH19

FBCLKOUT_H

AJ19

FBCLKOUT_L

A23

COREFB_H

A24

COREFB_L

B23

CORE_SENSE

AE12

VDDIOFB_H

AF12

VDDIOFB_L

AE11

VDDIO_SENSE

AH25

VDDA1

AJ25

VDDA2

AG13

VID4

AF14

VID3

AG14

VID2

AF15

VID1

AE15

VID0

AH17

DBRDY

AE19

DBREQ_L

A26

THERMDA

A27

THERMDC

A22

TDO

E20

TMS

E17

TCK

B21

TRST_L

A21

TDI

D29

VLDT0_A

D27

VLDT0_A

D25

VLDT0_A

C28

VLDT0_A

C26

VLDT0_A

B29

VLDT0_A

B27

VLDT0_A

D17

VTT_A

A18

VTT_A

B17

VTT_A

C17

VTT_A

C16

VTT_A

A28

KEY1

AJ28

KEY0

FOX_PZ75403-2941-42

CONN@

Claw Hammer-DTR

Miscellaneous

Clock

Debug

JTAG

H_THERMTRIP_S# H_THERMTRIP#

VLDT0_B
VLDT0_B
VLDT0_B
VLDT0_B
VLDT0_B
VLDT0_B
VLDT0_B

VTT_B
VTT_B
VTT_B
VTT_B
VTT_B

VTT_SENSE

+2.5VS

AG10

NC

E14

NC

D12

NC

E13

NC

C12

NC

D22

NC

C22

NC

B13

NC

B7

NC

C3

NC

K1

NC

R2

NC

AA3

NC

F3

NC

C23

NC

AG7

NC

AE22

NC

C24

NC

A25

NC

C9

NC

AE23

NC

AF23

NC

AF22

NC

AF21

NC

C1

NC

J3

NC

R3

NC

AA2

NC

D3

NC

AG2

NC

B18

NC

AH1

NC

AE21

NC

C20

NC

AG4

NC

C6

NC

AG6

NC

AE9

NC

AG9

NC

AF18

NC

AJ23

NC

AH23

NC

AE24

NC

AF24

NC

C15

NC

AG18

NC

AH18

NC

AG17

NC

AJ18

NC

C18

NC

A19

NC

D20

NC

C21

NC

D18

NC

C19

NC

B19

NC

AH29
AH27
AG28
AG26
AF29
AE28
AF25

AG15
AF16
AG16
AH16
AJ17
AE13

12

R678
680_0402_5%

TP_M_RESET#

TP_K8_D22
TP_K8_C22

CLAW_ANALOG3
CLAW_ANALOG2
CLAW_ANALOG1
CLAW_ANALOG0

BPSCLK
BPSCLK#
TP_K8_AE24
TP_K8_AF24
TP_K8_C15
TP_CPU_BP3
TP_CPU_BP2
BP1
BP0
SINCHN
BRN#
SCANCLK1
SCANCLK2
SCANEN
SCANSHENB
SCANSHENA

+1.2V_HT

VTT_SENSE

+2.5VS

12

R669
1K_0402_5%

2

Q48

3 1

MMBT3904_SOT23

C

T20 PAD

T2 PAD
T3 PAD

T5 PAD
T7 PAD
T9 PAD
T10 PAD

+2.5V

R661 820_0402_5%

1 2

R662 820_0402_5%

1 2

T11 PAD
T12 PAD
T13 PAD
T14 PAD
T15 PAD

R664 680_0402_5%

1 2

R665 680_0402_5%

1 2

R666 680_0402_5%

1 2

R667 680_0402_5%

1 2

R668 680_0402_5%

1 2

T16 PAD

+3VALW

12

R679
10K_0402_5%

+2.5V

+3VALW

12

R670

1K_0402_5%@

2

Q49

MMBT3904_SOT23@

3 1

H_THERMTRIP# <19>

+2.5VS

220U_D2_4VM

D

+1.25V

1

+

C707

2

+1.25V

4.7U_0805_6.3V6K

1

C710

2

4.7U_0805_6.3V6K

+1.25V

0.22U_0603_10V7K

1

C721

2

0.22U_0603_10V7K

+3VS +2.5VDDA

1U_0603_10V4Z@

+1.2V_HT

MAINPWON <39,40,42>

Near Power Supply

1

+

C708

220U_D2_4VM

2

4.7U_0805_6.3V6K

1

C712

2

0.22U_0603_10V7K

1

C723

2

1 2

RP25

4 5
3 6
2 7
1 8

680_0804_8P4R_5%

1

C741

2

0.22U_0603_10V7K

1

2

1

2

R101
0_0402_5%@

C713

C724

1

2

1

C711

2

4.7U_0805_6.3V6K

1

C722

2

0.22U_0603_10V7K

2

C734

1

SCANCLK2
SCANCLK1
SCANEN
SCANSHENB

0.22U_0603_10V7K

250 mil

1

+

C740

2

100U_D2_10VM

1

C714

2

4.7U_0805_6.3V6K

1

C725

2

0.22U_0603_10V7K

U54

1

IN

2

GND
SHDN3BYP

0.22U_0603_10V7K

1

C742

C743

2

4.7U_0805_6.3V6K

1

C715

2

4.7U_0805_6.3V6K

0.22U_0603_10V7K

1

C726

2

0.22U_0603_10V7K

+2.5VS

1 2

5

OUT

4

G914E_SOT23-5@

0.01U_0402_16V7K@

0.22U_0603_10V7K

1

C744

2

0.22U_0603_10V7K

E

4.7U_0805_6.3V6K

1

C716

2

0.22U_0603_10V7K

1

C727

2

R659

0_0805_5%

1

C736

2

1

C745

2

0.22U_0603_10V7K

1

C717

2

4.7U_0805_6.3V6K

1

C728

2

0.22U_0603_10V7K

2

C735
1U_0603_10V4Z

1

1

C746

2

1

C718

2

1

C729

2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2005/03/01 2006/03/11

C

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

D

Date: Sheet

Claw Harmmer (MISC)
LA-2931

648Thursday, August 18, 2005

E

0.3

of

A

U50E

B2

VSS

AH20

VSS

AB21

VSS

W22

+CPU_CORE +2.5V

U50D

L7

VDD

AC15

VDD

H18

VDD

B20

VDD

E21

VDD

H22

1 1

2 2

3 3

4 4

VDD

J23

VDD

H24

VDD

F26

VDD

N7

VDD

L9

VDD

V10

VDD

G13

VDD

K14

VDD

Y14

VDD

AB14

VDD

G15

VDD

J15

VDD

AA15

VDD

H16

VDD

K16

VDD

Y16

VDD

AB16

VDD

G17

VDD

J17

VDD

AA17

VDD

AC17

VDD

AE17

VDD

F18

VDD

K18

VDD

Y18

VDD

AB18

VDD

AD18

VDD

AG19

VDD

E19

VDD

G19

VDD

AC19

VDD

AA19

VDD

J19

VDD

F20

VDD

H20

VDD

K20

VDD

M20

VDD

P20

VDD

T20

VDD

V20

VDD

Y20

VDD

AB20

VDD

AD20

VDD

G21

VDD

J21

VDD

L21

VDD

N21

VDD

R21

VDD

U21

VDD

W21

VDD

AA21

VDD

AC21

VDD

F22

VDD

K22

VDD

M22

VDD

P22

VDD

T22

VDD

V22

VDD

Y22

VDD

AB22

VDD

AD22

VDD

E23

VDD

G23

VDD

L23

VDD

N23

VDD

R23

VDD

U23

VDD

W23

VDD

AA23

VDD

AC23

VDD

B24

VDD

D24

VDD

F24

VDD

K24

VDD

M24

VDD

P24

VDD

T24

VDD

V24

VDD

Y24

VDD

AB24

VDD

AD24

VDD

AH24

VDD

AE25

VDD

K26

VDD

P26

VDD

V26

VDD

FOX_PZ75403-2941-42

CONN@

POWER

A

VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

E4
G4
J4
L4
N4
U4
W4
AA4
AC4
AE4
D5
AF5
F6
H6
K6
M6
P6
T6
V6
Y6
AB6
AD6
D7
G7
J7
AA7
AC7
AF7
F8
H8
AB8
AD8
D9
G9
AC9
AF9
F10
AD10
D11
AF11
F12
AD12
D13
AF13
F14
AD14
F16
AD16
D15
R4

N28
U28
AA28
AE27
R7
U7
W7
K8
M8
P8
T8
V8
Y8
J9
N9
R9
U9
W9
AA9
H10
K10
M10
P10
T10
Y10
AB10
G11
J11
AA11
AC11
H12
K12
Y12
AB12
J13
AA13
AC13
H14
AB26
E28
J28

+CPU_CORE

VSS

M23

VSS

L24

VSS

AG25

VSS

AG27

VSS

D2

VSS

AF2

VSS

W6

VSS

Y7

VSS

AA8

VSS

AB9

VSS

AA10

VSS

J12

VSS

B14

VSS

Y15

VSS

AE16

VSS

J18

VSS

G20

VSS

R20

VSS

U20

VSS

W20

VSS

AA20

VSS

AC20

VSS

AE20

VSS

AG20

VSS

AJ20

VSS

D21

VSS

F21

VSS

H21

VSS

K21

VSS

M21

VSS

P21

VSS

T21

VSS

V21

VSS

Y21

VSS

AD21

VSS

AG21

VSS

B22

VSS

E22

VSS

G22

VSS

J22

VSS

L22

VSS

N22

VSS

R22

VSS

U22

VSS

AG29

VSS

AA22

VSS

AC22

VSS

AG22

VSS

AH22

VSS

AJ22

VSS

D23

VSS

F23

VSS

H23

VSS

K23

VSS

P23

VSS

T23

VSS

V23

VSS

Y23

VSS

AB23

VSS

AD23

VSS

AG23

VSS

E24

VSS

G24

VSS

J24

VSS

N24

VSS

R24

VSS

U24

VSS

W24

VSS

AA24

VSS

AC24

VSS

AG24

VSS

AJ24

VSS

B25

VSS

C25

VSS

B26

VSS

D26

VSS

H26

VSS

M26

VSS

T26

VSS

Y26

VSS

AD26

VSS

AF26

VSS

AH26

VSS

C27

VSS

B28

VSS

D28

VSS

G28

VSS

F15

VSS

H15

VSS

AB17

VSS

AD17

VSS

B16

VSS

G18

VSS

AA18

VSS

AC18

VSS

D19

VSS

F19

VSS

H19

VSS

K19

VSS

Y19

VSS

AB19

VSS

AD19

VSS

AF19

VSS

J20

VSS

L20

VSS

N20

VSS

FOX_PZ75403-2941-42

CONN@

B

POWER

B

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

C

L28
R28
W28
AC28
AF28
AH28
C29
F2
H2
K2
M2
P2
T2
V2
Y2
AB2
AD2
AH2
B4
AH4
B6
G6
J6
L6
N6
R6
U6
AA6
AC6
AH6
F7
H7
K7
M7
P7
T7
V7
AB7
AD7
B8
G8
J8
L8
N8
R8
U8
W8
AC8
AH8
F9
H9
K9
M9
P9
T9
V9
Y9
AD9
B10
G10
J10
L10
N10
R10
U10
W10
AC10
AH10
F11
H11
K11
Y11
AB11
AD11
B12
G12
AA12
AC12
AH12
F13
H13
K13
Y13
AB13
AD13
AF17
G14
J14
AA14
AC14
AE14
D16
E15
K15
AB15
AD15
AH14
E16
G16
J16
AA16
AC16
AE29
AJ26
E18

Security Classification

F17
H17
K17
Y17

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

+CPU_CORE

820U_E9_2_5V_M_R7

+

C747

10U_0805_10V4Z

C751

4.7U_0805_6.3V6K

C759

1

+

C748

2

1

C752

2

10U_0805_10V4Z

1

C760

2

4.7U_0805_6.3V6K

330U_D_2VM_R15

1

2

820U_E9_2_5V_M_R7

+CPU_CORE

1

2

10U_0805_10V4Z

4 in Socket Cavity,
2 on backside under Socket

+CPU_CORE

1

2

4.7U_0805_6.3V6K

1

+

2

10U_0805_10V4Z

1

C753

2

4.7U_0805_6.3V6K

1

C761

2

330U_D_2VM_R15

1

+

C749

2

1

C754

2

10U_0805_10V4Z

1

C762

2

4.7U_0805_6.3V6K

CPU Decouping Capacitor

4.7U_0805_6.3V6K

1

1

C773

C772

2

2

4.7U_0805_6.3V6K

2005/03/01 2006/03/11

C

Compal Secret Data

Deciphered Date

C750

10U_0805_10V4Z

1

C755

2

4.7U_0805_6.3V6K

1

C763

2

D

1

C756

2

1

C764

2

4.7U_0805_6.3V6K

D

+CPU_CORE

+CPU_CORE

1

C765

2

0.22U_0603_10V7K

Near Socket

+2.5V+2.5V

1

C774

2

0.22U_0603_10V7K

0.22U_0603_10V7K

1

2

E

1

C757
1000P_0402_50V7K

2

0.22U_0603_10V7K

1

1

C766

2

2

In Socket CavityClose to Socket

Loop Bandwidth
KHz

20
50

* 300 3300

1

C776

C775

2

0.22U_0603_10V7K

Title

Size Document Number Rev

Custom

Date: Sheet

1

C758

0.1U_0402_16V4Z

2

1

C767

C768

2

0.22U_0603_10V7K

Bulk Cappacitance
uF

0.22U_0603_10V7K

1

C769

2

0.22U_0603_10V7K

0.22U_0603_10V7K

1

C770

2

23000
9000

0.22U_0603_10V7K

1

C777

2

0.22U_0603_10V7K

Claw Harmmer (Power & Ground)

1

2

LA-2931

0.22U_0603_10V7K

1

C778

2

C779

E

1

C771

2

Total
ESR

2.5m ohm
(AMD)

0.9m ohm

1.5m ohm

748Thursday, August 18, 2005

of

0.3

A

+1.25VREF_MEM

+2.5V

DDR_DQ0
DDR_DQ5

DDR_DQS0

A

DDR_DQ3
DDR_DQ7

DDR_DQ9
DDR_DQ12

DDR_DQS1
DDR_DQ14

DDR_DQ15

DDR_DQ20
DDR_DQ17

DDR_DQS2
DDR_DQ18

DDR_DQ19
DDR_DQ28

DDR_DQ24
DDR_DQS3

DDR_DQ26
DDR_DQ27

KBD_DATA

KBD_CLK

DDR_CKE0
DDR_SMAA12

DDR_SMAA9
DDR_SMAA7

DDR_SMAA5
DDR_SMAA3
DDR_SMAA1

DDR_SMAA10
DDR_SBSA0
DDR_SWEA#
DDR_SCS#0
DDR_SMAA13

DDR_DQ32
DDR_DQ36

DDR_DQS4
DDR_DQ34

DDR_DQ38
DDR_DQ40

DDR_DQ44
DDR_DQS5

DDR_DQ47
DDR_DQ46

DDR_DQ48
DDR_DQ49

DDR_DQS6
DDR_DQ50

DDR_DQ55
DDR_DQ56

DDR_DQ61
DDR_DQS7

DDR_DQ58
DDR_DQ59

+3VS

1 1

DDR_CLK5<5>
DDR_CLK5#<5>

2 2

KBD_DATA<9,33>
KBD_CLK<9,33>

DDR_CKE0<5>

DDR_SBSA0<5>
DDR_SWEA#<5>
DDR_SCS#0<5>

3 3

4 4

SMB_CK_DAT1<9,15,19>

SMB_CK_CLK1<9,15,19>

JP45

1

VREF

3

VSS

5

DQ0

7

DQ1

9

VDD

11

DQS0

13

DQ2

15

VSS

17

DQ3

19

DQ8

21

VDD

23

DQ9

25

DQS1

27

VSS

29

DQ10

31

DQ11

33

VDD

35

CK0

37

CK0#

39

VSS

41

DQ16

43

DQ17

45

VDD

47

DQS2

49

DQ18

51

VSS

53

DQ19

55

DQ24

57

VDD

59

DQ25

61

DQS3

63

VSS

65

DQ26

67

DQ27

69

VDD

71

CB0

73

CB1

75

VSS

77

DQS8

79

CB2

81

VDD

83

CB3

85

DU

87

VSS

89

CK2

91

CK2#

93

VDD

95

CKE1

97

DU/A13

99

A12

101

A9

103

VSS

105

A7

107

A5

109

A3

111

A1

113

VDD

115

A10/AP

117

BA0

119

WE#

121

S0#

123

DU

125

VSS

127

DQ32

129

DQ33

131

VDD

133

DQS4

135

DQ34

137

VSS

139

DQ35

141

DQ40

143

VDD

145

DQ41

147

DQS5

149

VSS

151

DQ42

153

DQ43

155

VDD

157

VDD

159

VSS

161

VSS

163

DQ48

165

DQ49

167

VDD

169

DQS6

171

DQ50

173

VSS

175

DQ51

177

DQ56

179

VDD

181

DQ57

183

DQS7

185

VSS

187

DQ58

189

DQ59

191

VDD

193

SDA

195

SCL

197

VDD_SPD

199

VDD_ID

QTC_C106A-040SP11

CONN@

B

VREF

VSS
DQ4
DQ5
VDD
DM0
DQ6
VSS
DQ7

DQ12

VDD

DQ13

DM1

VSS
DQ14
DQ15

VDD

VDD

VSS

VSS

DQ20
DQ21

VDD

DM2
DQ22

VSS
DQ23
DQ28

VDD
DQ29

DM3

VSS
DQ30
DQ31

VDD

CB4

CB5

VSS

DM8

CB6

VDD

CB7

DU/RESET#

VSS

VSS

VDD

VDD

CKE0

DU/BA2

A11

A8

VSS

A6
A4
A2

A0
VDD
BA1

RAS#
CAS#

S1#

DU

VSS

DQ36
DQ37

VDD
DM4

DQ38

VSS

DQ39
DQ44

VDD

DQ45

DM5
VSS

DQ46
DQ47

VDD

CK1#

CK1
VSS

DQ52
DQ53

VDD
DM6

DQ54

VSS

DQ55
DQ60

VDD

DQ61

DM7
VSS

DQ62
DQ63

VDD
SA0
SA1
SA2

DU

B

C

+2.5V

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200

40mil

DDR_DQ4
DDR_DQ1

DDR_DM0
DDR_DQ2

DDR_DQ6
DDR_DQ8

DDR_DQ13
DDR_DM1

DDR_DQ10
DDR_DQ11

DDR_DQ16
DDR_DQ21

DDR_DM2
DDR_DQ22

DDR_DQ23
DDR_DQ25

DDR_DQ29
DDR_DM3

DDR_DQ30
DDR_DQ31

DDR_CKE0
DDR_SMAA11

DDR_SMAA8
DDR_SMAA6

DDR_SMAA4
DDR_SMAA2
DDR_SMAA0

DDR_SBSA1
DDR_SRASA#
DDR_SCASA#
DDR_SCS#1

DDR_DQ37
DDR_DQ33

DDR_DM4
DDR_DQ35

DDR_DQ39
DDR_DQ41

DDR_DQ45
DDR_DM5

DDR_DQ42
DDR_DQ43

DDR_DQ53
DDR_DQ52

DDR_DM6
DDR_DQ54

DDR_DQ51
DDR_DQ60

DDR_DQ57
DDR_DM7

DDR_DQ62
DDR_DQ63

STANDARD

SO-DIMM0

C

1

C780

0.1U_0402_16V4Z

2

DDR_SBSA1 <5>
DDR_SRASA# <5>
DDR_SCASA# <5>
DDR_SCS#1 <5>

DDR_CLK7# <5>
DDR_CLK7 <5>

D

DDR_SDQS[0..7]<5>
DDR_SDQ[0..63]<5>

+1.25VREF_MEM

DDR_SDQ0 DDR_DQ0
DDR_SDQ4
DDR_SDQ5
DDR_SDQ1

DDR_SDM0
DDR_SDQS0
DDR_SDQ2
DDR_SDQ3

DDR_SDQ7
DDR_SDQ9
DDR_SDQ6
DDR_SDQ8

DDR_SDQ12
DDR_SDQS1

DDR_SDM1 DDR_DM1

DDR_SDQ14

DDR_SDQ11

DDR_SDQ16 DDR_DQ16
DDR_SDQ21 DDR_DQ21

DDR_SDQ17

DDR_SDM2 DDR_DM2
DDR_SDQ18

DDR_SDQ28
DDR_SDQ25

DDR_SDQ24
DDR_SDQ29
DDR_SDQS3
DDR_SDM3

DDR_SDQ26
DDR_SDQ27
DDR_SDQ30
DDR_SDQ31

DDR_SDM[0..7]<5>
DDR_SMAA[0..13]<5>

RP27

1 8
2 7
3 6
4 5

10_0804_8P4R_5%
RP30

1 8
2 7
3 6
4 5

10_0804_8P4R_5%
RP33

1 8
2 7
3 6
4 5

10_0804_8P4R_5%
RP36

1 8
2 7
3 6
4 5

10_0804_8P4R_5%
RP39

1 8
2 7
3 6
4 5

10_0804_8P4R_5%
RP40

1 8
2 7
3 6
4 5

10_0804_8P4R_5%
RP42

1 8
2 7
3 6
4 5

10_0804_8P4R_5%
RP44

1 8
2 7
3 6
4 5

10_0804_8P4R_5%

RP46

1 8
2 7
3 6
4 5

10_0804_8P4R_5%
RP48

1 8
2 7
3 6
4 5

10_0804_8P4R_5%

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

D

2005/03/01 2006/03/11

E

DDR_SDQS[0..7]

DDR_SDQ[0..63]
DDR_SDM[0..7]

DDR_SMAA[0..13]

DDR_DQ4
DDR_DQ5
DDR_DQ1

DDR_DM0
DDR_DQS0
DDR_DQ2
DDR_DQ3

DDR_DQ7
DDR_DQ9
DDR_DQ6
DDR_DQ8

DDR_DQ12
DDR_DQS1
DDR_DQ13DDR_SDQ13

DDR_DQ14
DDR_DQ15DDR_SDQ15
DDR_DQ10DDR_SDQ10
DDR_DQ11

DDR_DQ20DDR_SDQ20
DDR_DQ17

DDR_DQS2DDR_SDQS2
DDR_DQ18

DDR_DQ22DDR_SDQ22

DDR_DQ19DDR_SDQ19
DDR_DQ23DDR_SDQ23
DDR_DQ28
DDR_DQ25

DDR_DQ24
DDR_DQ29
DDR_DQS3
DDR_DM3

DDR_DQ26
DDR_DQ27
DDR_DQ30
DDR_DQ31

Compal Secret Data

Deciphered Date

E

F

RP26

DDR_SDQ32 DDR_DQ32
DDR_SDQ33
DDR_SDQ36 DDR_DQ36
DDR_SDQ37

DDR_SDQS4
DDR_SDQ34
DDR_SDM4 DDR_DM4
DDR_SDQ39

DDR_SDQ38
DDR_SDQ35

DDR_SDQ45

DDR_SDQ44
DDR_SDQS5

DDR_SDM5

DDR_SDQ42
DDR_SDQ43
DDR_SDQ47
DDR_SDQ46

DDR_SDQ48
DDR_SDQ53
DDR_SDQ49
DDR_SDQ52

DDR_SDQ54
DDR_SDQ50

DDR_SDQ51
DDR_SDQ55

DDR_SDQ57
DDR_SDQ61
DDR_SDM7
DDR_SDQS7 DDR_DQS7

DDR_SDQ62
DDR_SDQ58
DDR_SDQ63 DDR_DQ63
DDR_SDQ59

F

1 8
2 7
3 6
4 5

10_0804_8P4R_5%
RP29

1 8
2 7
3 6
4 5

10_0804_8P4R_5%
RP32

1 8
2 7
3 6
4 5

10_0804_8P4R_5%
RP35

1 8
2 7
3 6
4 5

10_0804_8P4R_5%

RP38

1 8
2 7
3 6
4 5

10_0804_8P4R_5%

RP41

1 8
2 7
3 6
4 5

10_0804_8P4R_5%

RP43

1 8
2 7
3 6
4 5

10_0804_8P4R_5%

RP45

1 8
2 7
3 6
4 5

10_0804_8P4R_5%

RP47

1 8
2 7
3 6
4 5

10_0804_8P4R_5%

RP49

1 8
2 7
3 6
4 5

10_0804_8P4R_5%

DDR_DQ[0..63]
DDR_DQS[0..7]
DDR_DM[0..7]

DDR_DQ33
DDR_DQ37

DDR_DQS4
DDR_DQ34

DDR_DQ39

DDR_DQ38
DDR_DQ35
DDR_DQ40DDR_SDQ40
DDR_DQ45

DDR_DQ44
DDR_DQ41DDR_SDQ41
DDR_DQS5
DDR_DM5

DDR_DQ42
DDR_DQ43
DDR_DQ47
DDR_DQ46

DDR_DQ48
DDR_DQ53
DDR_DQ49
DDR_DQ52

DDR_DM6DDR_SDM6
DDR_DQS6DDR_SDQS6
DDR_DQ54
DDR_DQ50

DDR_DQ51
DDR_DQ55
DDR_DQ60DDR_SDQ60
DDR_DQ56DDR_SDQ56

DDR_DQ57
DDR_DQ61
DDR_DM7

DDR_DQ62
DDR_DQ58

DDR_DQ59

G

DDR_DQ[0..63] <9>
DDR_DQS[0..7] <9>
DDR_DM[0..7] <9>

DDR_SMAA13
DDR_SWEA#

DDR_SCASA#

DDR_SCS#0
DDR_SCS#1

DDR_CKE0

Note:
DDR_SMAA13 Recommend for AMD

DDR_SMAA12
DDR_SMAA9
DDR_SMAA7
DDR_SMAA5

DDR_SMAA3
DDR_SMAA1
DDR_SMAA10
DDR_SBSA0

DDR_SMAA11
DDR_SMAA8
DDR_SMAA6
DDR_SMAA4

DDR_SMAA2
DDR_SMAA0
DDR_SBSA1
DDR_SRASA#

1 2
1 2
1 2

H

RP28

47_0804_8P4R_5%

RP31

47_0804_8P4R_5%

RP34

47_0804_8P4R_5%

RP37

47_0804_8P4R_5%
R6 47_0402_5%
R1 47_0402_5%
R5 47_0402_5%

R8 47_0402_5%

1 2

R10 47_0402_5%

1 2

R9 47_0402_5%

1 2

+1.25V

18
27
36
45

18
27
36
45

18
27
36
45

18
27
36
45

Layout note

Place these resistors
close to DIMM0,
all trace length<500 mil

+2.5V

12

R686
1K_0402_1%

12

R687

1K_0402_1%

Title

Size Document Number Rev

Custom

Date: Sheet

G

DDR-SODIMM SLOT0
LA-2931

+1.25VREF_MEM

1

C781

0.1U_0402_16V4Z

2

1

C782

1000P_0402_50V7K

2

848Thursday, August 18, 2005

of

H

0.3

A

+2.5V

JP46

1

VREF

3

DDR_DQ0
DDR_DQ5

DDR_DQS0
DDR_DQ3

DDR_DQ7

1 1

DDR_CLK4<5>
DDR_CLK4#<5>

2 2

3 3

4 4

KBD_DATA<8,33>
KBD_CLK<8,33>

DDR_CKE1<5>

DDR_SBSB0<5>
DDR_SWEB#<5>

DDR_SCS#2<5>

SMB_CK_DAT1<8,15,19>

SMB_CK_CLK1<8,15,19>

DDR_DQ9
DDR_DQ12

DDR_DQS1
DDR_DQ14

DDR_DQ15

DDR_DQ20
DDR_DQ17

DDR_DQS2
DDR_DQ18

DDR_DQ19
DDR_DQ28

DDR_DQ24
DDR_DQS3

DDR_DQ26
DDR_DQ27

KBD_DATA

KBD_CLK

DDR_CKE1 DDR_CKE1
DDR_SMAB12

DDR_SMAB9
DDR_SMAB7

DDR_SMAB5
DDR_SMAB3
DDR_SMAB1

DDR_SMAB10
DDR_SBSB0
DDR_SWEB#
DDR_SCS#2 DDR_SCS#3
DDR_SMAB13

DDR_DQ32
DDR_DQ36

DDR_DQS4
DDR_DQ34

DDR_DQ38
DDR_DQ40

DDR_DQ44
DDR_DQS5

DDR_DQ47
DDR_DQ46

DDR_DQ48
DDR_DQ49

DDR_DQS6
DDR_DQ50

DDR_DQ55
DDR_DQ56

DDR_DQ61
DDR_DQS7

DDR_DQ58
DDR_DQ59

+3VS

A

VSS

5

DQ0

7

DQ1

9

VDD

11

DQS0

13

DQ2

15

VSS

17

DQ3

19

DQ8

21

VDD

23

DQ9

25

DQS1

27

VSS

29

DQ10

31

DQ11

33

VDD

35

CK0

37

CK0#

39

VSS

41

DQ16

43

DQ17

45

VDD

47

DQS2

49

DQ18

51

VSS

53

DQ19

55

DQ24

57

VDD

59

DQ25

61

DQS3

63

VSS

65

DQ26

67

DQ27

69

VDD

71

CB0

73

CB1

75

VSS

77

DQS8

79

CB2

81

VDD

83

CB3

85

DU

87

VSS

89

CK2

91

CK2#

93

VDD

95

CKE1

97

DU/A13

99

A12

101

A9

103

VSS

105

A7

107

A5

109

A3

111

A1

113

VDD

115

A10/AP

117

BA0

119

WE#

121

S0#

123

DU

125

VSS

127

DQ32

129

DQ33

131

VDD

133

DQS4

135

DQ34

137

VSS

139

DQ35

141

DQ40

143

VDD

145

DQ41

147

DQS5

149

VSS

151

DQ42

153

DQ43

155

VDD

157

VDD

159

VSS

161

VSS

163

DQ48

165

DQ49

167

VDD

169

DQS6

171

DQ50

173

VSS

175

DQ51

177

DQ56

179

VDD

181

DQ57

183

DQS7

185

VSS

187

DQ58

189

DQ59

191

VDD

193

SDA

195

SCL

197

VDD_SPD

199

VDD_ID

QTC_C106A-040SP11

CONN@

DU/RESET#

DIMM1

VREF

VSS
DQ4
DQ5
VDD
DM0
DQ6
VSS
DQ7

DQ12

VDD

DQ13

DM1

VSS
DQ14
DQ15

VDD

VDD

VSS

VSS

DQ20
DQ21

VDD

DM2
DQ22

VSS
DQ23
DQ28

VDD
DQ29

DM3

VSS
DQ30
DQ31

VDD

CB4

CB5

VSS

DM8

CB6

VDD

CB7

VSS

VSS

VDD

VDD

CKE0

DU/BA2

VSS

VDD

BA1

RAS#
CAS#

VSS
DQ36
DQ37

VDD

DM4
DQ38

VSS
DQ39
DQ44

VDD
DQ45

DM5

VSS
DQ46
DQ47

VDD
CK1#

CK1

VSS
DQ52
DQ53

VDD

DM6
DQ54

VSS
DQ55
DQ60

VDD
DQ61

DM7

VSS
DQ62
DQ63

VDD

SA0

SA1

SA2

A11

S1#

B

+2.5V

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102

A8

104
106

A6

108

A4

110

A2

112

A0

114
116
118
120
122
124

DU

126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200

DU

20 mil width

DDR_DQ4
DDR_DQ1

DDR_DM0
DDR_DQ2

DDR_DQ6
DDR_DQ8

DDR_DQ13
DDR_DM1

DDR_DQ10
DDR_DQ11

DDR_DQ16
DDR_DQ21

DDR_DM2
DDR_DQ22

DDR_DQ23
DDR_DQ25

DDR_DQ29
DDR_DM3

DDR_DQ30
DDR_DQ31

DDR_SMAB11
DDR_SMAB8

DDR_SMAB6
DDR_SMAB4
DDR_SMAB2
DDR_SMAB0

DDR_SBSB1
DDR_SRASB#
DDR_SCASB#

DDR_DQ37
DDR_DQ33

DDR_DM4
DDR_DQ35

DDR_DQ39
DDR_DQ41

DDR_DQ45
DDR_DM5

DDR_DQ42
DDR_DQ43

DDR_DQ53
DDR_DQ52

DDR_DM6
DDR_DQ54

DDR_DQ51
DDR_DQ60

DDR_DQ57
DDR_DM7

DDR_DQ62
DDR_DQ63

+3VS

+1.25VREF_MEM

1

C783

0.1U_0402_16V4Z

2

DDR_SBSB1 <5>
DDR_SRASB# <5>
DDR_SCASB# <5>
DDR_SCS#3 <5>

DDR_CLK6# <5>
DDR_CLK6 <5>

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2005/03/01 2006/03/11

C

Compal Secret Data

Note:
DDR_SMAB13 Recommend
for AMD.

DDR_DQ63

1 8

DDR_DQ62

2 7

DDR_DM7

3 6

DDR_DQ57

4 5

68_0804_8P4R_5%

DDR_DQ60

1 8

DDR_DQ51

2 7

DDR_DQ54

3 6

DDR_DM6

4 5

68_0804_8P4R_5%

DDR_DQ52

1 8

DDR_DQ53

2 7

DDR_DQ43

3 6

DDR_DQ42

4 5

68_0804_8P4R_5%

DDR_DM5

1 8

DDR_DQ45

2 7

DDR_DQ41

3 6

DDR_DQ39

4 5

68_0804_8P4R_5%

DDR_DQ35

1 8

DDR_DM4

2 7

DDR_DQ33

3 6

DDR_DQ37

4 5

68_0804_8P4R_5%

DDR_DQ31

1 8

DDR_DQ30

2 7

DDR_DM3

3 6

DDR_DQ29

4 5

68_0804_8P4R_5%

DDR_DQ25

1 8

DDR_DQ23

2 7

DDR_DQ22

3 6

DDR_DM2

4 5

68_0804_8P4R_5%

RP68

DDR_DQ21

1 8

DDR_DQ16

2 7

DDR_DQ11

3 6

DDR_DQ10

4 5

68_0804_8P4R_5%

RP70

DDR_DM1

1 8

DDR_DQ13

2 7

DDR_DQ8

3 6

DDR_DQ6

4 5

68_0804_8P4R_5%

RP72

DDR_DQ2

1 8

DDR_DM0

2 7

DDR_DQ1

3 6

DDR_DQ4

4 5

68_0804_8P4R_5%

DDR_DQS[0..7]<8>
DDR_DQ[0..63]<8>

DDR_DM[0..7]<8>
DDR_SMAB[0..13]<5>

Deciphered Date

RP52

RP55

RP58

RP61

RP63

RP65

RP66

DDR_DQS[0..7]

DDR_DQ[0..63]
DDR_DM[0..7]

DDR_SMAB[0..13]

D

+1.25V

D

E

+1.25V

DDR_DQ59
DDR_DQ58
DDR_DQS7
DDR_DQ61

DDR_DQ56
DDR_DQ55
DDR_DQ50
DDR_DQS6

68_0804_8P4R_5%

DDR_DQ49
DDR_DQ48
DDR_DQ46
DDR_DQ47

DDR_DQS5
DDR_DQ44
DDR_DQ40
DDR_DQ38

DDR_DQ34
DDR_DQS4
DDR_DQ36
DDR_DQ32

68_0804_8P4R_5%

DDR_DQ27
DDR_DQ26
DDR_DQS3
DDR_DQ24

DDR_DQ28
DDR_DQ19
DDR_DQ18
DDR_DQS2

DDR_DQ17
DDR_DQ20
DDR_DQ15
DDR_DQ14

DDR_DQS1
DDR_DQ12
DDR_DQ9
DDR_DQ7

DDR_DQ3
DDR_DQS0
DDR_DQ5
DDR_DQ0

RP51

1 8
2 7
3 6
4 5

68_0804_8P4R_5%

RP54

1 8
2 7
3 6
4 5

RP57

1 8
2 7
3 6
4 5

68_0804_8P4R_5%
RP60

1 8
2 7
3 6
4 5

68_0804_8P4R_5%

RP62

1 8
2 7
3 6
4 5

RP64

1 8
2 7
3 6
4 5

68_0804_8P4R_5%
RP67

1 8
2 7
3 6
4 5

68_0804_8P4R_5%
RP69

1 8
2 7
3 6
4 5

68_0804_8P4R_5%
RP71

1 8
2 7
3 6
4 5

68_0804_8P4R_5%
RP73

1 8
2 7
3 6
4 5

68_0804_8P4R_5%

DDR_SBSB0
DDR_SMAB10
DDR_SMAB1
DDR_SMAB3

DDR_SMAB5
DDR_SMAB7
DDR_SMAB9
DDR_SMAB12

DDR_SMAB8
DDR_SMAB11

DDR_CKE1

DDR_SMAB0
DDR_SMAB2
DDR_SMAB4
DDR_SMAB6

DDR_SMAB13
DDR_SWEB#

DDR_SCASB#

DDR_SBSB1
DDR_SRASB#
DDR_SCS#2
DDR_SCS#3

RP50

1 8
2 7
3 6
4 5

47_0804_8P4R_5%

RP53

1 8
2 7
3 6
4 5

47_0804_8P4R_5%

RP56

1 8
2 7
3 6
4 5

47_0804_8P4R_5%

RP59

1 8
2 7
3 6
4 5

47_0804_8P4R_5%

RP3

47_0804_8P4R_5%

RP4

47_0804_8P4R_5%

Layout note
Place these resistor

closely DIMM1,
all trace
length<=800mil

Title

Size Document Number Rev

Custom

Date: Sheet

DDR-SODIMM SLOT1

LA-2931

E

+1.25V

18
27
36
45

18
27
36
45

0.3

948Thursday, August 18, 2005

of

A

B

C

D

E

07/07/'05

+2.5V

1

C784

2

1 1

1

+

+

C785

2

330U_D_4VM

330U_D_4VM

4.7U_0805_6.3V6K

1

C786

2

4.7U_0805_6.3V6K

1

C787

2

Near DIMMs

Layout note :

Place one cap close to every 2 pull up resistors termination to
+1.25V

+1.25V

+2.5V

C1657

100P_0402_25V8K@

100P_0402_25V8K@

C1658

Please Close to DDR_CLK4/5 via hole

1

C788

2

0.1U_0402_16V4Z

+1.25V

2 2

1

C800

2

0.1U_0402_16V4Z

+1.25V

1

C812

2

0.1U_0402_16V4Z

+1.25V

1

C824

3 3

2

0.1U_0402_16V4Z

+1.25V

1

C836

2

0.1U_0402_16V4Z

+1.25V

1

C789

2

0.1U_0402_16V4Z

1

C801

2

0.1U_0402_16V4Z

1

C813

2

0.1U_0402_16V4Z

1

C825

2

0.1U_0402_16V4Z

1

C837

2

0.1U_0402_16V4Z

1

C790

2

0.1U_0402_16V4Z

1

C802

2

0.1U_0402_16V4Z

1

C814

2

0.1U_0402_16V4Z

1

C826

2

0.1U_0402_16V4Z

1

C838

2

0.1U_0402_16V4Z

1

C791

2

0.1U_0402_16V4Z

1

C803

2

0.1U_0402_16V4Z

1

C815

2

0.1U_0402_16V4Z

1

C827

2

0.1U_0402_16V4Z

1

C839

2

0.1U_0402_16V4Z

1

C792

2

0.1U_0402_16V4Z

1

C804

2

0.1U_0402_16V4Z

1

C816

2

0.1U_0402_16V4Z

1

C828

2

0.1U_0402_16V4Z

1

C840

2

0.1U_0402_16V4Z

1

C793

2

0.1U_0402_16V4Z

1

C805

2

0.1U_0402_16V4Z

1

C817

2

0.1U_0402_16V4Z

1

C829

2

0.1U_0402_16V4Z

1

C841

2

0.1U_0402_16V4Z

1

C794

2

0.1U_0402_16V4Z

1

C806

2

0.1U_0402_16V4Z

1

C818

2

0.1U_0402_16V4Z

1

C830

2

0.1U_0402_16V4Z

1

C842

2

0.1U_0402_16V4Z

1

C795

2

0.1U_0402_16V4Z

1

C807

2

0.1U_0402_16V4Z

1

C819

2

0.1U_0402_16V4Z

1

C831

2

0.1U_0402_16V4Z

1

C843

2

0.1U_0402_16V4Z

1

C796

2

0.1U_0402_16V4Z

1

C808

2

0.1U_0402_16V4Z

1

C820

2

0.1U_0402_16V4Z

1

C832

2

0.1U_0402_16V4Z

1

C844

2

0.1U_0402_16V4Z

1

C797

2

0.1U_0402_16V4Z

1

C809

2

0.1U_0402_16V4Z

1

C821

2

0.1U_0402_16V4Z

1

C833

2

0.1U_0402_16V4Z

1

C845

2

0.1U_0402_16V4Z

1

C798

2

0.1U_0402_16V4Z

1

C810

2

0.1U_0402_16V4Z

1

C834

2

0.1U_0402_16V4Z

1

C846

2

0.1U_0402_16V4Z

1

C799

2

0.1U_0402_16V4Z

1

C811

2

0.1U_0402_16V4Z

1

C835

2

0.1U_0402_16V4Z

+2.5V

1

C847

2

0.1U_0402_16V4Z

+2.5V

10U_0805_10V4Z

+1.25V

1

2

C822

1

C823

10U_0805_10V4Z

2

1

C848

2

0.1U_0402_16V4Z

4 4

1

2

0.1U_0402_16V4Z

A

C849

1

C850

2

0.1U_0402_16V4Z

1

C851

2

0.1U_0402_16V4Z

1

C852

2

0.1U_0402_16V4Z

B

1

C853

2

0.1U_0402_16V4Z

1

C854

2

0.1U_0402_16V4Z

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

1

C855

2

0.1U_0402_16V4Z

1

C856

2

0.1U_0402_16V4Z

2005/03/01 2006/03/11

C

1

C857

2

0.1U_0402_16V4Z

+2.5V

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

D

Date: Sheet of

DDR SODIMM Decoupling

LA-2931

E

0.3

10 48Thursday, August 18, 2005

5

4

3

2

1

H_CADIP[0..15]<4>
H_CADIN[0..15]<4>

H_CADOP[0..15]<4>

D D

H_CADOP15
H_CADON15
H_CADOP14
H_CADON14
H_CADOP13
H_CADON13
H_CADOP12
H_CADON12
H_CADOP11
H_CADON11
H_CADOP10
H_CADON10
H_CADOP9
H_CADON9
H_CADOP8
H_CADON8

H_CADOP7
H_CADON7
H_CADOP6
H_CADON6
H_CADOP5
H_CADON5
H_CADOP4

1 2
1 2

H_CADON4
H_CADOP3
H_CADON3
H_CADOP2
H_CADON2
H_CADOP1
H_CADON1
H_CADOP0
H_CADON0

H_CLKOP1
H_CLKON1

H_CLKOP0
H_CLKON0

H_CTLOP0
H_CTLON0

C C

H_CLKOP1<4>
H_CLKON1<4>

H_CLKOP0<4>
H_CLKON0<4>

H_CTLOP0<4>

H_CTLON0<4>

+1.2V_HT

B B

R1157 49.9_0402_1%
R1159 49.9_0402_1%

H_CADON[0..15]<4>

U55A

T26

HT_RXCAD15P

R26

HT_RXCAD15N

U25

HT_RXCAD14P

U24

HT_RXCAD14N

V26

HT_RXCAD13P

U26

HT_RXCAD13N

W25

HT_RXCAD12P

W24

HT_RXCAD12N

AA25

HT_RXCAD11P

AA24

HT_RXCAD11N

AB26

HT_RXCAD10P

AA26

HT_RXCAD10N

AC25

HT_RXCAD9P

AC24

HT_RXCAD9N

AD26

HT_RXCAD8P

AC26

HT_RXCAD8N

R29

HT_RXCAD7P

R28

HT_RXCAD7N

T30

HT_RXCAD6P

R30

HT_RXCAD6N

T28

HT_RXCAD5P

T29

HT_RXCAD5N

V29

HT_RXCAD4P

U29

HT_RXCAD4N

Y30

HT_RXCAD3P

W30

HT_RXCAD3N

Y28

HT_RXCAD2P

Y29

HT_RXCAD2N

AB29

HT_RXCAD1P

AA29

HT_RXCAD1N

AC29

HT_RXCAD0P

AC28

HT_RXCAD0N

Y26

HT_RXCLK1P

W26

HT_RXCLK1N

W29

HT_RXCLK0P

W28

HT_RXCLK0N

P29

HT_RXCTLP

N29

HT_RXCTLN

D27

HT_RXCALN

E27

HT_RXCALP

216RS480M_BGA706

H_CADIP[0..15]
H_CADIN[0..15]

H_CADOP[0..15]

H_CADON[0..15]

HYPER TRANSPORT CPU

I/F

HT_TXCAD15P
HT_TXCAD15N
HT_TXCAD14P
HT_TXCAD14N
HT_TXCAD13P
HT_TXCAD13N
HT_TXCAD12P
HT_TXCAD12N
HT_TXCAD11P
HT_TXCAD11N
HT_TXCAD10P
HT_TXCAD10N

HT_TXCAD9P
HT_TXCAD9N
HT_TXCAD8P
HT_TXCAD8N

HT_TXCAD7P
HT_TXCAD7N
HT_TXCAD6P
HT_TXCAD6N
HT_TXCAD5P
HT_TXCAD5N
HT_TXCAD4P
HT_TXCAD4N
HT_TXCAD3P
HT_TXCAD3N
HT_TXCAD2P
HT_TXCAD2N
HT_TXCAD1P
HT_TXCAD1N
HT_TXCAD0P
HT_TXCAD0N

HT_TXCLK1P
HT_TXCLK1N

HT_TXCLK0P
HT_TXCLK0N

HT_TXCTLP

HT_TXCTLN

HT_TXCALP

HT_TXCALN

H_CADIP15

R24

H_CADIN15

R25

H_CADIP14

N26

H_CADIN14

P26

H_CADIP13

N24

H_CADIN13

N25

H_CADIP12

L26

H_CADIN12

M26

H_CADIP11

J26

H_CADIN11

K26

H_CADIP10

J24

H_CADIN10

J25

H_CADIP9

G26

H_CADIN9

H26

H_CADIP8

G24

H_CADIN8

G25

H_CADIP7

L30

H_CADIN7

M30

H_CADIP6

L28

H_CADIN6

L29

H_CADIP5

J29

H_CADIN5

K29

H_CADIP4

H30

H_CADIN4

H29

H_CADIP3

E29

H_CADIN3

E28

H_CADIP2

D30

H_CADIN2

E30

H_CADIP1

D28

H_CADIN1

D29

H_CADIP0

B29

H_CADIN0

C29

H_CLKIP1

L24

H_CLKIN1

L25

H_CLKIP0

F29

H_CLKIN0

G29

H_CTLIP0

M29

H_CTLIN0

M28

R1158 100_0402_1%

B28

1 2

A28

H_CLKIP1 <4>

H_CLKIN1 <4>

H_CLKIP0 <4>

H_CLKIN0 <4>

H_CTLIP0 <4>
H_CTLIN0 <4>

0.1U_0402_16V4Z

0.1U_0402_16V4Z

C1637

C1638

+2.5VS

U55B

AF17

MEM_A0

AK17

MEM_A1

AH16

MEM_A2

AF16

MEM_A3

AJ22

MEM_A4

AJ21

MEM_A5

AH20

MEM_A6

AH21

MEM_A7

AK19

MEM_A8

AH19

MEM_A9

AJ17

MEM_A10

AG16

MEM_A11

AG17

MEM_A12

AH17

MEM_A13

AJ18

MEM_A14

AG26

MEM_DM0

AJ29

MEM_DM1

AE21

MEM_DM2

AH24

MEM_DM3

AH12

MEM_DM4

AG13

MEM_DM5

AH8

MEM_DM6

AE8

MEM_DM7

AF25

MEM_DQS0P

AH30

MEM_DQS1P

AG20

MEM_DQS2P

AJ25

MEM_DQS3P

AH13

MEM_DQS4P

AF14

MEM_DQS5P

AJ7

MEM_DQS6P

AG8

MEM_DQS7P

AG25

MEM_DQS0N

AH29

MEM_DQS1N

AF21

MEM_DQS2N

AK25

MEM_DQS3N

AJ12

MEM_DQS4N

AF13

MEM_DQS5N

AK7

MEM_DQS6N

AF9

MEM_DQS7N

AE17

MEM_RAS#

AH18

MEM_CAS#

AE18

MEM_WE#

AJ19

MEM_CS#

AF18

MEM_CKE

AK16

MEM_CKP

AJ16

MEM_CKN

C1635 0.47U_0603_16V7K

1 2

C1636 0.47U_0603_16V7K

12

1

2

1

2

R1334
1K_0402_1%

12

R1336
1K_0402_1%

MEM_VREF

+1.8VS

1 2

R56 0_0402_5%

1 2

1 2

R1333
0_0805_5%

+MPVDD

C1634

1 2

1U_0603_10V4Z

AE28

MEM_CAP1

AJ4

MEM_CAP2

AJ20

MEM_VMODE

AK20

MEM_VREF

AJ15

MPVDD

AJ14

MPVSS

216RS480M_BGA706

MEM_A I/F

MEM_COMPP
MEM_COMPN

MEM_DQ0
MEM_DQ1
MEM_DQ2
MEM_DQ3
MEM_DQ4
MEM_DQ5
MEM_DQ6
MEM_DQ7
MEM_DQ8

MEM_DQ9
MEM_DQ10
MEM_DQ11
MEM_DQ12
MEM_DQ13
MEM_DQ14
MEM_DQ15
MEM_DQ16
MEM_DQ17
MEM_DQ18
MEM_DQ19
MEM_DQ20
MEM_DQ21
MEM_DQ22
MEM_DQ23
MEM_DQ24
MEM_DQ25
MEM_DQ26
MEM_DQ27
MEM_DQ28
MEM_DQ29
MEM_DQ30
MEM_DQ31
MEM_DQ32
MEM_DQ33
MEM_DQ34
MEM_DQ35
MEM_DQ36
MEM_DQ37
MEM_DQ38
MEM_DQ39
MEM_DQ40
MEM_DQ41
MEM_DQ42
MEM_DQ43
MEM_DQ44
MEM_DQ45
MEM_DQ46
MEM_DQ47
MEM_DQ48
MEM_DQ49
MEM_DQ50
MEM_DQ51
MEM_DQ52
MEM_DQ53
MEM_DQ54
MEM_DQ55
MEM_DQ56
MEM_DQ57
MEM_DQ58
MEM_DQ59
MEM_DQ60
MEM_DQ61
MEM_DQ62
MEM_DQ63

AF28
AF27
AG28
AF26
AE25
AE24
AF24
AG23
AE29
AF29
AG30
AG29
AH28
AJ28
AH27
AJ27
AE23
AG22
AF23
AF22
AE20
AG19
AF20
AF19
AH26
AJ26
AK26
AH25
AJ24
AH23
AJ23
AH22
AK14
AH14
AK13
AJ13
AJ11
AH11
AJ10
AH10
AE15
AF15
AG14
AE14
AE12
AF12
AG11
AE11
AJ9
AH9
AJ8
AK8
AH7
AJ6
AH6
AJ5
AG10
AF11
AF10
AE9
AG7
AF8
AF7
AE7

AH5
AD30

R1337 61.9_0402_1%@

1 2

R1335 61.9_0402_1%@

1 2

+2.5VS

MEM_VREF , MPVDD (20mils)

A A

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/03/01 2005/04/06

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

RS480M-HT/VMEM
LA-2931

1

0.3

of

11 48Thursday, August 18, 2005

5

D D

C C

SB_RX0P<18>
SB_RX0N<18>

SB_RX1P<18>
SB_RX1N<18>

B B

R1166 10K_0402_1%

1 2

R1167 8.25K_0402_1%

1 2

4

U55C

D8

GFX_RX0P

D7

GFX_RX0N

D5

GFX_RX1P

D4

GFX_RX1N

E4

GFX_RX2P

F4

GFX_RX2N

G5

GFX_RX3P

G4

GFX_RX3N

H4

GFX_RX4P

J4

GFX_RX4N

H5

GFX_RX5P

H6

GFX_RX5N

G1

GFX_RX6P

G2

GFX_RX6N

K5

GFX_RX7P

K4

GFX_RX7N

L4

GFX_RX8P

M4

GFX_RX8N

N5

GFX_RX9P

N4

GFX_RX9N

P4

GFX_RX10P

R4

GFX_RX10N

P5

GFX_RX11P

P6

GFX_RX11N

P2

GFX_RX12P

R2

GFX_RX12N

T5

SB_RX0P
SB_RX0N

SB_RX1P
SB_RX1N

GFX_RX13P

T4

GFX_RX13N

U4

GFX_RX14P

V4

GFX_RX14N

W1

GFX_RX15P

W2

GFX_RX15N

AE1

GPP_RX0P

AE2

GPP_RX0N

AB2

GPP_RX1P

AC2

GPP_RX1N

AB5

GPP_RX2P

AB4

GPP_RX2N

Y4

GPP_RX3P

AA4

GPP_RX3N

AG1

SB_RX0P

AH1

SB_RX0N

AC5

SB_RX1P

AC6

SB_RX1N

AH3

PCE_ISET

AJ3

PCE_TXISET

216RS480M_BGA706

PCIE I/F TO VIDEO

PCIE I/F TO SLOT

PCIE I/F TO SB

GFX_TX0P
GFX_TX0N
GFX_TX1P
GFX_TX1N
GFX_TX2P
GFX_TX2N
GFX_TX3P
GFX_TX3N
GFX_TX4P
GFX_TX4N
GFX_TX5P
GFX_TX5N
GFX_TX6P
GFX_TX6N
GFX_TX7P
GFX_TX7N
GFX_TX8P
GFX_TX8N
GFX_TX9P

GFX_TX9N
GFX_TX10P
GFX_TX10N
GFX_TX11P
GFX_TX11N
GFX_TX12P
GFX_TX12N
GFX_TX13P
GFX_TX13N
GFX_TX14P
GFX_TX14N
GFX_TX15P
GFX_TX15N

GPP_TX0P

GPP_TX0N

GPP_TX1P

GPP_TX1N

GPP_TX2P

GPP_TX2N

GPP_TX3P

GPP_TX3N

SB_TX0P
SB_TX0N

SB_TX1P
SB_TX1N

PCE_PCAL

PCE_NCAL

3

A7
B7
B6
B5
A5
A4
B3
B2
C1
D1
D2
E2
F2
F1
H2
J2
J1
K1
K2
L2
M2
M1
N1
N2
R1
T1
T2
U2
V2
V1
Y2
AA2

AD2
AD1

AA1
AB1

Y5
Y6

W5
W4

SB_TX0P_C

AF2

SB_TX0N_C

AG2

SB_TX1P_C

AC4
AD4

R1168 150_0402_1%

AH2

R1169 82.5_0402_1%

AJ2

C1413 0.1U_0402_16V4Z
C1414 0.1U_0402_16V4Z

C1415 0.1U_0402_16V4Z
C1416 0.1U_0402_16V4Z

1 2
1 2

1 2
1 2

1 2
1 2

SB_TX0P
SB_TX0N

SB_TX1P
SB_TX1NSB_TX1N_C

+1.2V_HT

2

SB_TX0P <18>

SB_TX0N <18>

SB_TX1P <18>

SB_TX1N <18>

1

A A

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/03/01 2005/04/06

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

RS480M PCIE/DVI Controller
LA-2931

1

of

12 48Thursday, August 18, 2005

0.3

AVDD , AVDDI , AVDDQ , +NB_PLLVDD , +NB_HTPVDD
+NB_VDDR3 , LPVDD , LVDDR18D , LVDDR18A (20mils)

+1.8VS

L78

1 2

FBML10160808121LMT_0603

100U_D2_10VM

1

+

2

C1663

C1419

10U_0805_10V4Z

8/16: modify

R1170

1 2

1U_0603_10V4Z

1

1

2

2

1U_0603_10V4Z

1

1

2

2

1 2

715_0402_1%

C1424

C1430

+1.8VS

R1172

4.7K_0402_5%

1 2

R1173
470K_0402_5%

@

1 2

+1.8VS

1 2

FBML10160808121LMT_0603

+1.8VS

10U_0805_10V4Z

R1171

1 2

150_0603_1%

10U_0805_10V4Z

+3VS

L80

C1423

C1429

L83
FBML10160808121LMT_0603

NB STRAPS(Internal pull up)

DEF_GPIO0:SIDE PORT EN#

High, SIDE PORT MEMORY DISABLE
Low, SIDE PORT MEMORY ENABLE

DEF_GPIO1:LOAD ROM ST RAPS #

High, LOAD ROM STRAP DISABLE
Low, LOAD RO M STRAP ENABLE

1U_0603_10V4Z

1

1

C1420

2

2

VGA_CRT_ VSYNC<16>
VGA_CRT_HSYNC<16>

VGA_DDC_CLK<16>
VGA_DDC_DATA<16>

+3VS

1 2

FBML10160808121LMT_0603

0.1U_0402_16V4Z

+1.8VS

0.1U_0402_16V4Z

TV_CRMA<16>
TV_LUMA<16>

TV_COMPS<16>

VGA_CRT_R< 16>

VGA_CRT_G<16>
VGA_CRT_B<16>

NB_RST#<18,23,32>

NB_PWRGD<36>

LDTSTOP#<4,18>

ALLOW_LDTSTOP<18>

C1431
1U_0603_10V4Z

NB_REFCLK<15>

R1177 10K_0402_5%

R1178 3K_0402_5%@

BMREQ#<18>
EDID_CLK_LCD<17>
EDID_DAT_LCD<17>

+3VS

L77

1

C1418

2

1 2

1 2

T21PAD

EDID_CLK_LCD

EDID_DAT_LCD

+AVDD

1

1

C35

C1417

2

2

+AVDDI

+AVDDQ

TV_CRMA
TV_LUMA
TV_COMPS

VGA_CRT_R
VGA_CRT_G
VGA_CRT_B

VGA_CRT_ VSYNC
VGA_CRT_HSYNC

VGA_DDC_CLK
VGA_DDC_DATA

+NB_PLLVDD

+NB_HTPVDD

NB_RST#

NB_PWRGD

LDTSTOP#

ALLOW_LDTSTOP

SUS_STAT#

+NB_VDDR3

NB_REFCLK

12

BMREQ#

1U_0603_10V4Z

B27
C27
D26
D25
C24
B24

E24
D24

B25
A25
A24

C25
A26
B26

A11
B11
C26
E11
F11

A14
B14

M23
L23

D14
B15
B12
C12
AH4

H13
H12

A13
B13

B9

F12
E13
D13

F10
C10
C11
AF4
AE4

U55D

AVDD1
AVDD2
AVSSN1
AVSSN2
AVDDDI
AVSSDI

AVDDQ
AVSSQ

C
Y
COMP

RED
GREEN
BLUE

DAC_VSYNC
DAC_HSYNC
RSET
DAC_SCL
DAC_SDA

PLLVDD
PLLVSS

HTPVDD
HTPVSS

SYSRESET#
POWERGOOD
LDTSTOP#
ALLOW_LDTSTOP
SUS_STAT#

VDDR3_1
VDDR3_2

OSCIN
OSCOUT

TVCLKIN

DFT_GPIO0/RSV
DFT_GPIO1/RSV
DFT_GPIO2/RSV

BMREQb
I2C_CLK
I2C_DATA
THERMALDIODE_P
THERMALDIODE_N

216RS480M_BGA706

CRT/TVOUT

PLL PWR

PM

CLOCKs

MIS.

TXOUT_U0P

TXOUT_U0N

TXOUT_U1P

TXOUT_U1N

TXOUT_U2P

TXOUT_U2N

TXOUT_U3P

TXOUT_U3N

TXOUT_L0P
TXOUT_L0N
TXOUT_L1P
TXOUT_L1N
TXOUT_L2P
TXOUT_L2N
TXOUT_L3P
TXOUT_L3N

TXCLK_UP
TXCLK_UN

TXCLK_LP

TXCLK_LN

LVDS

LPVDD
LPVSS

LVDDR18D
LVDDR18A_1
LVDDR18A_2

LVSSR1
LVSSR2
LVSSR3
LVSSR4
LVSSR5
LVSSR6
LVSSR7
LVSSR8

LVDS_DIGON

LVDS_BLON
LVDS_BLEN

GFX_CLKP

GFX_CLKN

HTTSTCLK

HTREFCLK

SB_CLKP
SB_CLKN

DFT_GPIO3/RSV
DFT_GPIO4/RSV
DFT_GPIO5/RSV

TMDS_HPD

STRP_DATA

DDC_DATA

TESTMODE

LVDSB0+

D18

LVDSB0-

C18

LVDSB1+

B19

LVDSB1-

A19

LVDSB2+

D19

LVDSB2-

C19
D20
C20

LVDSA0+

B16

LVDSA0-

A16

LVDSA1+

D16

LVDSA1-

C16

LVDSA2+

B17

LVDSA2-

A17
E17
D17

LVDSBC+

B20

LVDSBC-

A20

LVDSAC+

B18

LVDSAC-

C17
E18

F17
E19
G20

+LVDDR18A

H20
G19

E20
F20
H18
G18
F19
H19
F18

ENVDD

E14

ENABLT

F14
F13

B8
A8

R1176 10K_0402_5%

P23

HTREFCLK

N23

SBLINKCLK

E8

SBLINKCLK#

E7

C13
C14
C15

A10
E10

R1338 4.7K_0402_5%

B10

R1179 4.7K_0402_5%

E12

LVDSB0+ <17>
LVDSB0- <17>
LVDSB1+ <17>
LVDSB1- <17>
LVDSB2+ <17>
LVDSB2- <17>

LVDSA0+ <17>
LVDSA0- <17>
LVDSA1+ <17>
LVDSA1- <17>
LVDSA2+ <17>
LVDSA2- <17>

LVDSBC+ <17>
LVDSBC- <17>
LVDSAC+ <17>
LVDSAC- <17>

0.1U_0402_16V4Z

1

C1427

2

1 2

HTREFCLK <15>
SBLINKCLK <15>

SBLINKCLK# <15>

T22 PAD

1 2
1 2

+LPVDD
+LVDDR18D

L82

1 2

FBML10160808121LMT_0603

1

C1428
1U_0603_10V4Z

2

+3VS

1K_0402_5%

R1174

+1.8VS

12

R1175

@

0.1U_0402_16V4Z

C1421

0.1U_0402_16V4Z

C1425

12

1K_0402_5%

1

1

C1422
1U_0603_10V4Z

2

2

1

1

C1426
1U_0603_10V4Z

2

2

ENVDD <17>
ENABLT <17,33>

L79

1 2

FBML10160808121LMT_0603

L81

1 2

FBML10160808121LMT_0603

+1.8VS

+1.8VS

R1180

4.7K_0402_5%

1 2

R1181

4.7K_0402_5%

1 2

EDID_CLK_LCD

EDID_DAT_LCD

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2005/03/01 2005/04/06

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

Date: Sheet

RS480M VIDEO_IF/CLOCK GEN
LA-2931

of

13 48Thursday, August 18, 2005

0.3

5

U55F

G10

VSS1

G12

VSS2

AD29

VSS3

AD27

VSS4

AC27

VSS5

G15

VSS6

G14

VSS7

Y24

VSS8

G13

VSS9

E9

VSS10

D15

VSS11

D9

VSS12

AD9

VSS13

G11

5

VSS14

F16

VSS15

G30

VSS16

AB28

VSS17

AB25

VSS18

D12

VSS19

AD24

VSS20

AA28

VSS21

G17

VSS22

Y23

VSS23

AC9

VSS24

R19

VSS25

Y27

VSS26

C28

VSS27

G16

VSS28

F25

VSS29

B30

VSS30

T24

VSS31

F26

VSS32

W27

VSS33

D11

VSS34

H11

VSS35

AD25

VSS36

H17

VSS37

H10

VSS38

H16

VSS39

H14

VSS40

E16

VSS41

D10

VSS42

E15

VSS43

F15

VSS44

U15

VSS45

V14

VSS46

R15

VSS47

T14

VSS48

N15

VSS49

V12

VSS50

N13

VSS51

P14

VSS52

U17

VSS53

T16

VSS54

R17

VSS55

P12

VSS56

T12

VSS57

R13

VSS58

W13

VSS59

W17

VSS60

P18

VSS61

V18

VSS62

M18

VSS63

U13

VSS64

N17

VSS65

W15

VSS66

V16

VSS67

T18

VSS68

M14

VSS69

M12

VSS70

M16

VSS71

P16

VSS72

U19

VSS73

AC16

VSS74

AG18

VSS75

AC23

VSS76

AD8

VSS77

AD11

VSS78

AD13

VSS79

AD16

VSS80

AD19

VSS81

AD23

VSS82

AG5

VSS83

AG6

VSS84

AG21

VSS85

AD17

VSS86

AG15

VSS87

AG12

VSS88

AF30

VSS89

AG24

VSS90

AG9

VSS91

AC19

VSS92

AG27

VSS93

AC11

VSS94

AD7

VSS95

AJ30

VSS96

AC21

VSS97

AK5

VSS98

AK10

VSS99

AC13

VSS100

AD21

VSS101

AK22

VSS102

AK29

VSS103

W19

VSS104

AE26

VSS105

AE27

VSS106

T27

VSS107

R27

VSS108

AD28

VSS109

F24

VSS110

F27

VSS111

G28

VSS112

216RS480M_BGA706

GROUND

D D

VSS30

C C

B B

VSS89

A A

VSSA1
VSSA2
VSSA3
VSSA4
VSSA5
VSSA6
VSSA7
VSSA8

VSSA9
VSSA10
VSSA11
VSSA12
VSSA13
VSSA14
VSSA15
VSSA16
VSSA17
VSSA18
VSSA19
VSSA20
VSSA21
VSSA22
VSSA23
VSSA24
VSSA25
VSSA26
VSSA27
VSSA28
VSSA29
VSSA30
VSSA31
VSSA32
VSSA33
VSSA34
VSSA35
VSSA36
VSSA37
VSSA38
VSSA39
VSSA40
VSSA41
VSSA42
VSSA43
VSSA44
VSSA45
VSSA46
VSSA47
VSSA48
VSSA49
VSSA50
VSSA51
VSSA52
VSSA53
VSSA54
VSSA55
VSSA56
VSSA57
VSSA58
VSSA59
VSSA60
VSSA61
VSSA62
VSSA63
VSSA64
VSSA65
VSSA66
VSSA67
VSSA68

VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120

VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132

R5
AE5
V5
N3
F7
F5
R3
AA6
T3
M6
C5
F8
M8
Y8
V3
C3
W3
K8
D3
C6
AA3
A2
AB3
P8
J6
C8
AD3
V8
F3
AE3
AF3
M5
AB7
G3
B4
P7
AA5
C9
C7
J5
R6
J3
AD5
D6
C4
K3
AB8
T7
Y7
AD6
K7
H7
M3
V6
H8
C2
AG3
L6
AJ1
M7
V7
F6
E6
U5
U6
E5
L5
T8

F28
H28
M24
J28
N19
K28
T23
L27

M27
H24
N28
P25
P28
E26
K25
U28
V25
V28
R23

VSSA22

VSSA59

4

+1.8VS

VDDA12_13

1

C1504

4.7U_0805_6.3V6K

2

VSSA22

VDDA18_13

1

C1505

4.7U_0805_6.3V6K

2

VSSA59

VDDHT30

1

C1506

4.7U_0805_6.3V6K

2

VSS30

VDDHT31

1

C1507

4.7U_0805_6.3V6K

2

VSS89

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

4

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

C1435 1U_0402_6.3V4Z

1 2

C1436 1U_0402_6.3V4Z

1 2

C1438 1U_0402_6.3V4Z

1 2

C1440 1U_0402_6.3V4Z

1 2

C1442 1U_0402_6.3V4Z

1 2

C1444 1U_0402_6.3V4Z

1 2

C1445 1U_0402_6.3V4Z

1 2

C1446 1U_0402_6.3V4Z

1 2

C1447 1U_0402_6.3V4Z

1 2

C1448 1U_0402_6.3V4Z

1 2

C1449 1U_0402_6.3V4Z

1 2

C1450 1U_0402_6.3V4Z

1 2

C1451 1U_0402_6.3V4Z

1 2

0811 : modify

L84

FBML10160808121LMT_0603

1 2

2005/03/01 2005/04/06

3

+

+

12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12

12
12

12
12
12

C14961U_0402_6.3V4Z
C14981U_0402_6.3V4Z
C15001U_0402_6.3V4Z
C15021U_0402_6.3V4Z

C143322U_A_4VM

12

C1457330U_D_2VM_R15

12

C14580.1U_0402_16V4Z
C14590.1U_0402_16V4Z
C14600.1U_0402_16V4Z
C14610.1U_0402_16V4Z
C14620.1U_0402_16V4Z
C14630.1U_0402_16V4Z
C14650.1U_0402_16V4Z
C14660.1U_0402_16V4Z
C14670.1U_0402_16V4Z
C14690.1U_0402_16V4Z
C14710.1U_0402_16V4Z
C14720.1U_0402_16V4Z
C14740.1U_0402_16V4Z
C14760.1U_0402_16V4Z
C14780.1U_0402_16V4Z
C14800.1U_0402_16V4Z
C14820.1U_0402_16V4Z
C14840.1U_0402_16V4Z

+VDD18

C14931U_0603_10V4Z

+1.2V_HT

+1.8VS

N27
U27

V27
G27
V24
H27
K24

AB24

P27

J27

AA27

K27
P24

AB27
AB23

V23
G23
E23

W23

K23

J23
H23
U23

AA23

D23
F23
C23
B23
A23

VDDHT30

A29

VDDHT31

AC30
AK23

AK28
AK11

AK4

AE30
AC14
AD12
AC18
AC20
AD10
AD14
AD15
AD20
AC10
AD18
AC12
AD22
AC22
AH15

H15

AC17
AC15

B21
C21
A22
B22
C22
F21
F22
E21
G21

Compal Secret Data

Deciphered Date

2

U55E

VDD_HT1
VDD_HT2
VDD_HT3
VDD_HT4
VDD_HT5
VDD_HT6
VDD_HT7
VDD_HT8
VDD_HT9
VDD_HT10
VDD_HT11
VDD_HT12
VDD_HT13
VDD_HT14
VDD_HT15
VDD_HT16
VDD_HT17
VDD_HT18
VDD_HT19
VDD_HT20
VDD_HT21
VDD_HT22
VDD_HT23
VDD_HT24
VDD_HT25
VDD_HT26
VDD_HT27
VDD_HT28
VDD_HT29
VDD_HT30
VDD_HT31

VDD_MEM1
VDD_MEM2
VDD_MEM3
VDD_MEM4
VDD_MEM5
VDD_MEM6
VDD_MEM7
VDD_MEM8
VDD_MEM9
VDD_MEM10
VDD_MEM11
VDD_MEM12
VDD_MEM13
VDD_MEM14
VDD_MEM15
VDD_MEM16
VDD_MEM17
VDD_MEM18
VDD_MEMCK

VDD18_1
VDD18_2
VDD18_3

VDD_CORE47
VDD_CORE46
VDD_CORE45
VDD_CORE44
VDD_CORE43
VDD_CORE42
VDD_CORE41
VDD_CORE40
VDD_CORE39

216RS480M_BGA706

2

POWER

VDDA12_14

VDDA12_1
VDDA12_2
VDDA12_3
VDDA12_4
VDDA12_5
VDDA12_6
VDDA12_7
VDDA12_8

VDDA12_9
VDDA12_10
VDDA12_11
VDDA12_12
VDDA12_13

VDDA18_1

VDDA18_2

VDDA18_3

VDDA18_4

VDDA18_5

VDDA18_6

VDDA18_7

VDDA18_8

VDDA18_9
VDDA18_10
VDDA18_11
VDDA18_12
VDDA18_13

VDD_CORE1
VDD_CORE2
VDD_CORE3
VDD_CORE4
VDD_CORE5
VDD_CORE6
VDD_CORE7
VDD_CORE8

VDD_CORE9
VDD_CORE10
VDD_CORE11
VDD_CORE12
VDD_CORE13
VDD_CORE14
VDD_CORE15
VDD_CORE16
VDD_CORE17
VDD_CORE18
VDD_CORE19
VDD_CORE20
VDD_CORE21
VDD_CORE22
VDD_CORE23
VDD_CORE24
VDD_CORE25
VDD_CORE26
VDD_CORE27
VDD_CORE28
VDD_CORE29
VDD_CORE30
VDD_CORE31
VDD_CORE32
VDD_CORE33
VDD_CORE34
VDD_CORE35
VDD_CORE36
VDD_CORE37
VDD_CORE38

1

+1.2V_HT

H9
AA7
G9
U8
N7
N8
U7
F9
AA8
G8
G7
J8
J7

VDDA12_13

B1
AG4
R8
AC8
AC7
AF6
AE6
L8
W8
W7
L7
R7
AF5

VDDA18_13

AK2
N16
M13
M15
W16
N18
P19
N12
P15
N14
M17
T19
G22
R12
P13
R14
V19
R18
U16
U12
T13
U14
T17
U18
E22
R16
V13
T15
P17
W18
D22
W12
V15
W14
V17
M19
H22
H21
D21

+1.2V_HT

Title

Size Document Number Rev

Custom

Date: Sheet

+

C1432 22U_A_4VM

1 2

C1434 1U_0603_10V4Z

1 2
1 2

1 2
1 2
1 2

R1182
0_0805_5%

1 2
1 2
1 2
1 2
1 2

+

1 2

1 2
1 2

1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2

12

C1437 1U_0402_6.3V4Z
C1439 1U_0402_6.3V4Z
C1441 1U_0402_6.3V4Z
C1443 1U_0402_6.3V4Z

+VDDA18

C1452 1U_0603_10V4Z
C1453 1U_0402_6.3V4Z
C1454 1U_0402_6.3V4Z
C1455 1U_0402_6.3V4Z
C1456 1U_0402_6.3V4Z

C1464 100U_D2_10VM

C1468 22U_1206_10V4Z
C1470 22U_1206_10V4Z

C1473 0.1U_0402_16V4Z
C1475 0.1U_0402_16V4Z
C1477 0.1U_0402_16V4Z
C1479 0.1U_0402_16V4Z
C1481 0.1U_0402_16V4Z
C1483 0.1U_0402_16V4Z
C1485 0.1U_0402_16V4Z
C1486 0.1U_0402_16V4Z
C1487 0.1U_0402_16V4Z
C1488 0.1U_0402_16V4Z
C1489 0.1U_0402_16V4Z
C1490 0.1U_0402_16V4Z
C1491 0.1U_0402_16V4Z
C1492 0.1U_0402_16V4Z
C1494 0.1U_0402_16V4Z
C1495 0.1U_0402_16V4Z
C1497 0.1U_0402_16V4Z
C1499 0.1U_0402_16V4Z
C1501 0.1U_0402_16V4Z
C1503 0.1U_0402_16V4Z

RS480M Power/GND
LA-2931

1

14 48Thursday, August 18, 2005

+1.8VS

0.3

of

A

B

C

D

E

F

G

H

+3VS +3V_CLK

1 2

1 1

22P_0402_50V8J

2 2

22P_0402_50V8J

L85
CHB2012U121_0805

C165010U_0805_10V4Z

C1543

1 2

1 2

C1544

C1651 0.1U_0402_16V4Z

14.31818MHz_20P_1BX14318BE1A

12

Y6

CHB2012U121_0805

1 2

1 2

NB_REFCLK<13>

+3VS

12

L87

SMB_CK_CLK1<8,9,19>
SMB_CK_DAT1<8,9,19>

0.1U_0402_16V4Z

1

1

C1536

C1535

2

10U_0805_10V4Z

R1203 33_0402_5%

1 2

R1204 475_0402_1%

1 2

R1209 10K_0402_5%

@

1 2

@

1 2

R11 10K_0402_5%

C1537

2

0.1U_0402_16V4Z

XTALIN_CLK
XTALOUT_CLK

SMB_CK_CLK1
SMB_CK_DAT1 SBSRCCLK_R

NC_CLKSEL1#
NC_CLKSEL0#

0.1U_0402_16V4Z

1

1

C1538

2

2

U56

43

VDDCPU

14

VDDSRC

21

VDDSRC

35

VDDSRC

32

VDDATI

51

VDD_PCI

48

VDDHTT

56

VDDREF

3

VDD48

1

X1

2

X2

6

NC

7

SCLK

8

SDATA

52

REF2

37

IREF

11

CLKREQB#

10

CLKREQA#

5

GND

55

GND

36

GNDSRC

26

GNDSRC

20

GNDSRC

15

GNDSRC

31

GNDATI

49

GNDPCI

46

GNDHTT

42

GNDCPU

ICS951412AGLFT_TSSOP56

0.1U_0402_16V4Z

1

C1540

C1539

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

C1541

2

0.1U_0402_16V4Z

VDDA

GNDA

CPUCLK8T0

CPUCLK8C0

CPUCLK8T1

CPUCLK8C1

SRCCLKT7

SRCCLKC7

SRCCLKT6

SRCCLKC6

SRCCLKT5

SRCCLKC5

SRCCLKT4

SRCCLKC4

SRCCLKT3
SRCCLKC3
ATIGCLKT1
ATIGCLKC1
ATIGCLKT0
ATIGCLKC0

SRCCLKT0
SRCCLKC0

PCICLK0

FS0/REF0
FS1/REF1

FS2

USB_48MHz

HTTCLK0

1

2

39
38

45
44
41
40

12
13
16
17
18
19
22
23
24
25
27
28
30
29
34
33

50

54
53
9

4
47

1

C1648

@

2

0.1U_0402_16V4Z

CPUCLK0H
CPUCLK0L

SBSRCCLK#_R

SBLINKCLK_R
SBLINKCLK#_R

FS0
FS2

+3V_CLK (40 mils)

+3V_VDD (20mils)

1

C1649

@

2

R1189 15_0402_1%

1 2

R1190 15_0402_1%

1 2

R1199 33_0402_5%

1 2

R1201 33_0402_5%

1 2

R1205 33_0402_5%

1 2

R1207 33_0402_5%

1 2

R1211 33_0402_5%

1 2

R1212 33_0402_5%@

1 2

R1213 33_0402_5%

1 2

+3V_VDD

1 2
1 2
1 2

C1533

1

2

0.1U_0402_16V4Z

C1534

10U_0805_10V4Z

R121033_0402_5%
R74210_0402_5%

CLK_14M_CODEC

R74310_0402_5%

L86

CHB2012U121_0805

1

2

SBSRCCLK

SBSRCCLK#

SBLINKCLK
SBLINKCLK#

CLK_14M_SIOFS1

12

R1214

51.1_0402_1%

+3VS+3V_VDD

12

CPUCLK0_H <6>
CPUCLK0_L <6>

SBSRCCLK <18>
SBSRCCLK# <18>

SBLINKCLK <13>
SBLINKCLK# <13>

SB_OSC_INT <19>
CLK_14M_SIO <32>

CLK_14M_CODEC <28>

CLK_SD_48M <24>
USBCLK_EXT <19>
HTREFCLK <13>

A link Express

A link Express

SBSRCCLK
SBSRCCLK#
SBLINKCLK
SBLINKCLK#

R1200 49.9_0402_1%

1 2

R1202 49.9_0402_1%

1 2

R1206 49.9_0402_1%

1 2

R1208 49.9_0402_1%

1 2

3 3

+3V_CLK

EXT CLK FREQU ENCY SELECT TABLE(MHZ)

12

R1215

FS0
FS1
FS2

4 4

10K_0402_5%

12

R1218

8.2K_0402_5%@

12

R1216

10K_0402_5%

12

R1219

8.2K_0402_5% @

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

C

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

D

12

R1217

10K_0402_5%

12

R1220

8.2K_0402_5% @

2005/03/01 2005/04/06

E

Compal Secret Data

Deciphered Date

FS1 CPU

FS2

0 0 0
0 0 1

0 1 0
0 1 1
1 0 0
1 0 1
1 1 1

*

F

Hi-Z
X

180.00

220.00

100.00

133.33

200.00

SRCCLK

[2:1]

100.00

100.00

100.00

100.00

100.00

100.00

100.00

USB

PCIFS0 HTT

Hi-Z

Hi-Z

X/3 X/6

60.00 30.00

36.56

73.12

33.33

66.66

33.33

66.66

66.66

33.33

Title

Size Document Number Rev

Custom

Date: Sheet

G

COMMENT

48.00

Reserved

48.00

Reserved

48.00

Reserved

48.00

Reserved

48.00

Reserved

48.00

Reserved
Normal HAMMER operation

48.00

Clock Generator
LA-2931

15 48Thursday, August 18, 2005

H

0.3

of

A

CRT/TV-OUT Connector

1 1

2 2

VGA_CRT_HSYNC<13>

VGA_CRT_VSYNC<13>

B

VGA_CRT_R<13>

VGA_CRT_G<13>

VGA_CRT_B<13>

1 2

R372 39_0402_5%

VGA_CRT_VSYNC CRT _VSYNC D_CRT_VSYNC

VGA_CRT_R

VGA_CRT_G

VGA_CRT_B

12

R32

75_0402_5%

1 2

C399 0.1U_0402_16V4Z

CRT_HSYNC D_CRT_HSYNCVGA_CRT_HSYNC

1 2

R378 39_0402_5%

12

12

R25

R30

75_0402_5%

75_0402_5%

+CRT_VCC

C400 0.1U_0402_16V4Z

1

5

P

4

OE#

A2Y

G

U27

SN74AHCT1G125GW_SOT353-5

3

1 2

C

1

C5

2

8P_0402_50V8K

8P_0402_50V8K

+CRT_VCC

+3VS

1 2

L5

FCM2012C-800_0805

1 2

L4

FCM2012C-800_0805

1 2

L2

FCM2012C-800_0805

1

C14

1

2

C10

8P_0402_50V8K

2

12

R370 10K_0402_5%

1

5

P

4

OE#

A2Y

G

U28
SN74AHCT1G125GW_SOT353-5

3

CRT_R_L

CRT_G_L

CRT_B_L

C16

8P_0402_50V8K

D21

DAN217_SC59@

1

2

3

1

C11

2

8P_0402_50V8K
L3

1 2

CHB1608U301_0603

L1

1 2

CHB1608U301_0603

D20

1

2

DAN217_SC59@

2

D

1

3

1

8P_0402_50V8K

2

C9

10P_0402_50V8J

E

+5VS

1

D19

DAN217_SC59@

2

3

C8

HSYNC_L

VSYNC_L

1

2

D18

2 1

RB411D_SOT23

1

C6
10P_0402_50V8J

2

W=40mils

0.1U_0402_16V4Z

DDC_MD2

C4

100P_0402_25V8K

1

2

C13
68P_0402_50V8K

W=40mils

1

C398

2

VGA_DDC_DATA_C

VGA_DDC_CLK_C

+CRT_VCC

JP3

6

11

1
7

12

2
8

13

3
9

14

4
10
15

5

SUYIN_070112FR015S222ZU_15P

CONN@

1

C3
68P_0402_50V8K

2

1

D23

@

DAN217_SC59

2

3

3 3

TV_LUMA<13>

TV_CRMA<13>

TV_COMPS<13>

4 4

TV_LUMA

TV_CRMA

TV_COMPS

R66

75_0402_5%

12

12

R74
75_0402_5%

12

R62

75_0402_5%

1

1

C40

2

270P_0402_50V7K

2

270P_0402_50V7K

C48

L8

1 2

CHB1608U301_0603

L14

1 2

CHB1608U301_0603

L13

1 2

CHB1608U301_0603

1

C28

2

270P_0402_50V7K

1

D24

@

DAN217_SC59

2

3

C44

1

2

330P_0402_50V7K

C53

1

2

330P_0402_50V7K

330P_0402_50V7K

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

1

C30

2

1

D22

@

DAN217_SC59

2

CRMA_L
COMPS_L

+3VS+ CRT_VCC +3VS+CRT_VCC +3VS

3

+3VS

JP17

3
6
7
5
2

LUMA_L

4
1
8
9

SUYIN_030107FR007SX08FU

CONN@

2005/03/01 2005/04/06

C

Compal Secret Data

Deciphered Date

VGA_DDC_DATA_C

VGA_DDC_CLK_C

D

R1368

1 2

4.7K_0402_5%

R1369

1 2

4.7K_0402_5%

Custom

R1370

1 2

2.2K_0402_5%

2

G

1 3

D

Q33BSS138_SOT23

BSS138_SOT23

Title

Size Document Number Rev

Date: Sheet

S

2

1 3

D

Q34

1 2

10K_0402_5%

G

S

R1372

R1371

1 2

10K_0402_5%

TV_OUT/CRT CONN
LA-2931

E

VGA_DDC_DATA <13>

VGA_DDC_CLK <13>

16 48Thursday, August 18, 2005

of

0.3

5

4

3

2

1

LCD POWER CIRCUIT

D D

07/07/'05

+LCDVDD

12

13

C C

B B

2N7002_SOT23

ENVDD<13>

+3VS

1

C25

2

D5

1N4148_SOT23@

Q7

ENVDD

10K_0402_5%

0.1U_0402_16V4Z@

12

D

S

R625

1

C33

2

R61
360_0402_5%

2

G

2

12

INVT_PWM

1U_0603_10V4Z@

G

+5VALW

R63
100K_0402_5%

1 2

13

D

S

Q43
BSS138_SOT23

R65
100K_0402_5%

1 2

@

BKOFF#<33>

ENABLT<13,33>

+3VS

W=60mils

S

G

Q6

2

1

C29

2

0.047U_0402_16V7K

4.7U_0805_10V4Z

D3
RB751V_SOD323

21

D37
RB751V_SOD323

21

BKOFF# DISPOFF#

D

1 3

1

C21

2

SI2301BDS_SOT23

W=60mils

7.3

+LCDVDD

+3VS

12

+LCDVDD

R57

4.7K_0402_5%

1

C27

0.1U_0402_16V4Z

2

B+

+3VS

EDID_CLK_LCD<13>

EDID_DAT_LCD<13>

LVDSB0-<13>
LVDSB0+<13>

LVDSB1+<13>
LVDSB1-<13>

LVDSB2+<13>
LVDSB2-<13>

LVDSBC-<13>
LVDSBC+<13>

8/17:modify

R1403
0_0805_5%

12

EDID_CLK_LCD
EDID_DAT_LCD

LVDSB0-

LVDSB1+
LVDSB1-

LVDSB2+
LVDSB2-

LVDSBC­LVDSBC+

LCD/PANEL BD. Conn.

JP16

1

21

2

22

3

23

4

24

5

25

6

26

7

27

8

28

9

29

10

30

11

31

12

32

13

33

14

34

15

35

16

36

17

37

18

38

19

39

20

40

ACES_88107-4000G

CONN@

DAC_BRIG
INVT_PWM
DISPOFF#

LVDSA0­LVDSA0+LVDSB0+

LVDSA1­LVDSA1+

LVDSA2+
LVDSA2-

LVDSAC­LVDSAC+

DAC_BRIG <33>
INVT_PWM <33>

+LCDVDD

LVDSA0- <13>
LVDSA0+ <13>

LVDSA1- <13>
LVDSA1+ <13>

LVDSA2+ <13>
LVDSA2- <13>

LVDSAC- <13>
LVDSAC+ <13>

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2005/03/01 2005/04/06

3

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet of

LCD Conn
LA-2931

0.3

17 48Thursday, August 18, 2005

1

5

+3VS

RP86

1 8
2 7
3 6
4 5

D D

C C

B B

A A

8.2K_0804_8P4R_5%
RP87

1 8
2 7
3 6
4 5

8.2K_0804_8P4R_5%
RP88

1 8
2 7
3 6
4 5

8.2K_0804_8P4R_5%
RP89

1 8
2 7
3 6
4 5

8.2K_0804_8P4R_5%
RP90

1 8
2 7
3 6
4 5

8.2K_0804_8P4R_5%

1 2

R1238

8.2K_0402_5%

1 2

R1239

8.2K_0402_5%
RP91

1 8
2 7
3 6
4 5

8.2K_0804_8P4R_5%
RP92

1 8
2 7
3 6
4 5

8.2K_0804_8P4R_5%

R1242

8.2K_0402_5%

R1245
10K_0402_5%

PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#

PCI_PIRQF#
PCI_PIRQE#
PCI_PIRQG#
PCI_PIRQH#

PCI_REQ#0
PCI_REQ#1
PCI_REQ#2
PCI_REQ#3

PCI_GNT#0
PCI_GNT#1
PCI_GNT#2
PCI_GNT#3

PCI_REQ#4
PCI_GNT#4
PCI_REQ#5
PCI_GNT#5

PCI_REQ#6

PCI_GNT#6

PCI_FRAME#

PCI_IRDY#
PCI_TRDY#
PCI_STOP#

PCI_SERR#
PCI_PAR
PCI_DEVSEL#
LOCK#

PCI_PERR#

12

PCI_CLKRUN#

12

R1250
20M_0603_5%

5

SB_RX0P<12>
SB_RX0N<12>
SB_RX1P<12>
SB_RX1N<12>

SB_TX0P<12>
SB_TX0N<12>
SB_TX1P<12>
SB_TX1N<12>

+1.8VS

L88

FBM-L11-321611-260-LMT_1206

C1551 1U_0603_10V4Z

1 2

C1552 10U_0805_10V4Z

1 2

C1553 0.1U_0402_16V4Z

1 2

C1563
18P_0402_50V8J

1 2

1 2

12

C1564
18P_0402_50V8J

SB_RX0P

C1545 0.1U_0402_16V4Z

1 2

C1546 0.1U_0402_16V4Z

1 2

C1547 0.1U_0402_16V4Z

1 2

C1548 0.1U_0402_16V4Z

1 2

R1228 49.9_0402_1%

1 2

R1230 49.9_0402_1%

1 2

R1231 49.9_0402_1%

1 2

R1233 49.9_0402_1%

1 2

+PCIE_VDDR

+PCIE_PVDD

+1.8VS

FBM-L11-321611-260-LMT_1206

+

C1554 22U_A_4VM
C1555 0.1U_0402_16V4Z

C1556 0.1U_0402_16V4Z
C1557 0.1U_0402_16V4Z
C1558 0.1U_0402_16V4Z
C1559 0.1U_0402_16V4Z
C1560 0.1U_0402_16V4Z
C1561 0.1U_0402_16V4Z
C1562 0.1U_0402_16V4Z

1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2

12

12

SB_RX0N
SB_RX1P
SB_RX1N

PCIE_PVDD (20mils)
PCIE_VDDR (40mils)

PCI_PIRQE#<24,27>
PCI_PIRQF#<31>
PCI_PIRQG#<26>
PCI_PIRQH#<24>

1 2

4
1

20M_0603_5%

R1247

32.768KHZ_12.5PF_6H03200468

LDTSTOP#<4,13>

ALLOW_LDTSTOP<13>

H_PWRGD<6>

4

8.2K_0402_5%

R1221

1 2

A_RST#

SBSRCCLK<15>

SBSRCCLK#<15>

R1234
R1235

R1236 4.12K_0402_1%

L89

12

Y7

OUT
IN

BMREQ#<13>

H_RST#<6>

3

NC

2

NC

SBSRCCLK
SBSRCCLK#

SB_RX0P_C
SB_RX0N_C
SB_RX1P_C
SB_RX1N_C

SB_TX0P
SB_TX0N
SB_TX1P
SB_TX1N
SB_TX2P
SB_TX2N
SB_TX3P
SB_TX3N

150_0402_1%

150_0402_1%

+PCIE_VDDR

PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#
PCI_PIRQE#
PCI_PIRQF#
PCI_PIRQG#
PCI_PIRQH#

SB_32KHI

SB_32KH0

LDTSTOP#

ALLOW_LDTSTOP

H_PWRGD
BMREQ#

H_RST#

AH8

L27

M27
M30

N30

K30
L30

H30

J30
F30

G30
M29

N29
M28
N28

J29
K29
J28
K28

12

G27

12

H27

12

G28
R30

F26
R29
G26

P26

K26

L26

P28
N26

P27
H28

F29
H29
H26

F27
G29

L29

J26

L28

J27
N27
M26

K27

P29

P30

AJ8
AK7

AG5

AH5

AJ5
AH6

AJ6
AK6

AG7

AH7

B2

B1

C29

A28
C28

B29
D29

E4
B30
F28
E28
E29

D25

E27

D27
D28

U58A

A_RST#
PCIE_RCLKP

PCIE_RCLKN
PCIE_TX0P

PCIE_TX0N
PCIE_TX1P
PCIE_TX1N
PCIE_TX2P
PCIE_TX2N
PCIE_TX3P
PCIE_TX3N

PCIE_RX0P
PCIE_RX0N
PCIE_RX1P
PCIE_RX1N
PCIE_RX2P
PCIE_RX2N
PCIE_RX3P
PCIE_RX3N

PCIE_CALRP
PCIE_CALRN

PCIE_CALI
PCIE_PVDD
PCIE_VDDR_1

PCIE_VDDR_2
PCIE_VDDR_3
PCIE_VDDR_4
PCIE_VDDR_5
PCIE_VDDR_6
PCIE_VDDR_7
PCIE_VDDR_8
PCIE_VDDR_9

PCIE_VSS_1
PCIE_VSS_2
PCIE_VSS_3
PCIE_VSS_4
PCIE_VSS_5
PCIE_VSS_6
PCIE_VSS_7
PCIE_VSS_8
PCIE_VSS_9
PCIE_VSS_10
PCIE_VSS_11
PCIE_VSS_12
PCIE_VSS_13
PCIE_VSS_14
PCIE_VSS_15

CPU_STP#/DPSLP_3V#
DPSLP_OD#/GPIO37
INTA#
INTB#
INTC#
INTD#
INTE#/GPIO33
INTF#/GPIO34
INTG#/GPIO35
INTH#/GPIO36

X1

X2

CPU_PG
INTR/LINT0
NMI/LINT1
INIT#
SMI#
SLP#/LDT_STP#
IGNNE#
A20M#
FERR#
STPCLK#/ALLOW_LDTSTP
LDT_PG/SSMUXSEL/GPIO0
DPRSLPVR
BMREQ#
LDT_RST#

PCI EXPRESS INTERFACE

SB450 SB

CPU XTAL

SB450

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

Part 1 of 4

PCI CLKS

CBE0#/ROMA10

CBE2#/ROMWE#

DEVSEL#/ROMA0

TRDY#/ROMOE#

PCI INTERFACE

REQ3#/PDMA_REQ0#

REQ4#/PLL_BP33/PDMA_REQ1#

GNT3#/PLL_BP66/PDMA_GNT0#
GNT4#/PLL_BP50/PDMA_GNT1#

LPC

RTC_IRQ#/ACPWR_STRAP

RTC

2005/03/01 2005/04/06

3

PCICLK0
PCICLK1
PCICLK2
PCICLK3
PCICLK4
PCICLK5
PCICLK6
PCICLK7
PCICLK8
PCICLK9

PCICLK_FB

PCIRST#
AD0/ROMA18
AD1/ROMA17
AD2/ROMA16
AD3/ROMA15
AD4/ROMA14
AD5/ROMA13
AD6/ROMA12
AD7/ROMA11

AD8/ROMA9

AD9/ROMA8
AD10/ROMA7
AD11/ROMA6
AD12/ROMA5
AD13/ROMA4
AD14/ROMA3
AD15/ROMA2
AD16/ROMD0
AD17/ROMD1
AD18/ROMD2
AD19/ROMD3
AD20/ROMD4
AD21/ROMD5
AD22/ROMD6
AD23/ROMD7

AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31

CBE1#/ROMA1

CBE3#

FRAME#

IRDY#

PAR/ROMA19

STOP#
PERR#
SERR#

REQ0#

REQ1#

REQ2#

REQ5#/GPIO13
REQ6#/GPIO31

GNT0#

GNT1#

GNT2#

GNT5#/GPIO14
GNT6#/GPIO32

CLKRUN#

LOCK#

LAD0
LAD1
LAD2
LAD3

LFRAME#

LDRQ0#
LDRQ1#

SERIRQ

RTCCLK

VBAT

RTC_GND

PCI_AD[0..31]

PCICLK0_R

L4

PCICLK1_R

L3

PCICLK2_R

L2

PCICLK3_R

L1

PCICLK4_R

M4

PCICLK5_R

M3

PCICLK6_R

M2

CLK_PCI7

M1

CLK_PCI8

N4

PCICLK9_R

N3

PCICLKFB

N2

PCIRST#

AJ7

PCI_AD0

W3

PCI_AD1

Y2

PCI_AD2

W4

PCI_AD3

Y3

PCI_AD4

V1

PCI_AD5

Y4

PCI_AD6

V2

PCI_AD7

W2

PCI_AD8

AA4

PCI_AD9

V4

PCI_AD10

AA3

PCI_AD11

U1

PCI_AD12

AA2

PCI_AD13

U2

PCI_AD14

AA1

PCI_AD15

U3

PCI_AD16

T4

PCI_AD17

AC1

PCI_AD18

R2

PCI_AD19

AD4

PCI_AD20

R3

PCI_AD21

AD3

PCI_AD22

R4

PCI_AD23

AD2

PCI_AD24

P2

PCI_AD25

AE3

PCI_AD26

P3

PCI_AD27

AE2

PCI_AD28

P4

PCI_AD29

AF2

PCI_AD30

N1

PCI_AD31

AF1

PCI_CBE#0

V3

PCI_CBE#1

AB4

PCI_CBE#2

AC2

PCI_CBE#3

AE4

PCI_FRAME#

T3

PCI_DEVSEL#

AC4

PCI_IRDY#

AC3

PCI_TRDY#

T2

PCI_PAR

U4

PCI_STOP#

T1

PCI_PERR#

AB2

PCI_SERR#

AB3

PCI_REQ#0

AF4

PCI_REQ#1

AF3

PCI_REQ#2

AG2

PCI_REQ#3

AG3

PCI_REQ#4

AH1

PCI_REQ#5

AH2

PCI_REQ#6

AH3

PCI_GNT#0

AJ2

PCI_GNT#1

AK2

PCI_GNT#2

AJ3

PCI_GNT#3

AK3

PCI_GNT#4

AG4

PCI_GNT#5

AH4

PCI_GNT#6

AJ4

PCI_CLKRUN#

AG1

LOCK#

AB1

LPC_AD0

AG25

LPC_AD1

AH25

LPC_AD2

AJ25

LPC_AD3

AH24

LPC_FRAME#

AG24

LDRQ0#

AH26

LDRQ1#

AG26

SIRQ

AK27

RTC_CLK

C2

AUTO_ON#

F3
A2

A1

Compal Secret Data

Deciphered Date

2

R1222 22_0402_5%
R1224 22_0402_5%
R1225 22_0402_5%
R1226 22_0402_5%
R1331 22_0402_5%
R1332 22_0402_5%
R1374 22_0402_5%

R1227 22_0402_5%

2

C1566
1U_0603_10V4Z

1

PCI_AD[0..31] <22,24,26,27,31>

1 2
1 2
1 2
1 2
1 2
1 2
1 2

1 2

12

R1229

8.2K_0402_5%

PCI_CBE#0 <24,26,27,31>
PCI_CBE#1 <24,26,27,31>
PCI_CBE#2 <24,26,27,31>
PCI_CBE#3 <24,26,27,31>
PCI_FRAME# <24,26,27,31>
PCI_DEVSEL# <24,26,27,31>
PCI_IRDY# <24,26,27,31>
PCI_TRDY# <24,26,27,31>
PCI_PAR <24,26,27,31>
PCI_STOP# <24,26,27,31>
PCI_PERR# <24,26,27,31>
PCI_SERR# <24,26,31>
PCI_REQ#0 <27>
PCI_REQ#1 <31>
PCI_REQ#2 <24>
PCI_REQ#3 <26>

PCI_GNT#0 <27>
PCI_GNT#1 <31>
PCI_GNT#2 <24>
PCI_GNT#3 <26>

PCI_CLKRUN# <26,32>

LPC_AD0 <32,33>
LPC_AD1 <32,33>
LPC_AD2 <32,33>
LPC_AD3 <32,33>
LPC_FRAME# <32,33>
LDRQ0# <32,33>

SIRQ <24,32,33>

RTC_CLK <22>

AUTO_ON# <22>

+SB_VBAT

2

C1549 0.1U_0402_16V4Z@

+3VALW

C1550 0.1U_0402_16V4Z

1 2

1

5

U76

P

OE#

I2O

G

74LVC1G125GW_SOT3535

3

R450 0_0402_5%@

+SB_VBAT

W=20mils

1

CLK_PCI_PCM <24>
CLK_PCI_LAN <26>
CLK_PCI_MINI <22,31>
CLK_PCI_EC <22,33>
CLK_PCI_SIO <22,32>

CLK_PCI_1394 <22,27>
CLK_PCI_SIO_DB <22,33>
CLK_PCI7 <22>
CLK_PCI8 <22>

1 2

R1232 33_0402_5%

4

1 2

1 2

A_RST#

+3VALW

5

I2O

3

1 2

R451 0_0402_5%@

SIRQ

LDRQ0#
LDRQ1#

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3

LPC_FRAME#

PCI_RST#

C1644 0.1U_0402_16V4Z

1 2

1

U77

R1237

P

G

74LVC1G125GW_SOT3535

33_0402_5%

1 2

4

OE#

R1240 10K_0402_5%

1 2

R1241 10K_0402_5%

1 2

R1243 10K_0402_5%

1 2

R1244 100K_0402_5%

1 2

R1246 100K_0402_5%

1 2

R1248 100K_0402_5%

1 2

R1249 100K_0402_5%

1 2

R17 4.7K_0402_5%

Hi: Enable thermtrip
Low: Disable thermtrip

PCI_RST# <24,26,27,31,33>

12

RTC Battery

BATT1

-+

RTCBATT

+RTCVCC

1

No short

1

2

2

R1366

1 2

470_0805_5%

JOPEN1

JUMP_43X39 @

R1373

1 2

470_0805_5%

Title

Size Document Number Rev

Custom

Date: Sheet

+RTCBATT

+RTCBATT

12

1

2

3

1

C1652

0.1U_0402_16V4Z

2

SB400-PCI_EXP/PCI/LPC/RTC
LA-2931

1

NB_RST# <13,23,32>

+3VS

D9
BAS40-04_SOT23

+CHGRTC

18 48Thursday, August 18, 2005

of

0.3

5

+3VALW

R1252 10K_0402_5%

1 2

R1253 4.7K_0402_5%

1 2

R1254 4.7K_0402_5%

D D

+3VS

C C

+3VALW

B B

C1574 20P_0402_50V8J@

14.31818MHz_20P_1BX14318BE1A @
C1578 20P_0402_50V8J @

1 2

R1256 4.7K_0402_5%

1 2

R1258 10K_0402_5%

1 2

R1261 10K_0402_5%

1 2

R1263 10K_0402_5%@

1 2

R1265 10K_0402_5%@

1 2

R1343 10K_0402_5%

1 2

R1344 10K_0402_5%

1 2

R1345 10K_0402_5%

1 2

R1367 10K_0402_5%

1 2

R1377 10K_0402_5%

1 2

R18 4.7K_0402_5%

R1266 2.2K_0402_5%

1 2

R1267 2.2K_0402_5%

1 2

R1268 10K_0402_5%

1 2

R1363 8.2K_0402_5%@

1 2

R1361 10K_0402_5%@

1 2

R1277 10K_0402_5%

1 2

R1280 10K_0402_5%

1 2

R1282 10K_0402_5%

1 2

R1283 10K_0402_5%

1 2

R1284 8.2K_0402_5%

1 2

1 2

Y8

1 2

12

EC_SCI#
SLP_S3#
SLP_S5#
EC_FLASH#
SYS_RESET#
S3_STATE
KB_RST#

EC_RSMRST#
LPC_PME#

PWRBTN_OUT#
EC_THERM#
OVCUR#3

WAKE#
EC_SWI#

SMB_CK_CLK1
SMB_CK_DAT1
LPC_SMI#

AZ_RST# AZ_SDIN3
AZ_SDIN3
AC97_RST#

AC97_BITCLK
AC97_SDIN0
AC97_SDIN1
AC97_SDIN2

R1353 0_0402_5%

SB_OSC_INT

1 2

R1288
1M_0402_5%

14M_X2

@

12

@

1 2

4

U58B

1 2
1 2

1 2
1 2
1 2

1 2
1 2
1 2
1 2

AZ_RST#

1 2

AC97_SDIN1
AC97_SDIN2

1 2

EC_THERM#
EC_SWI#
EC_SCI#
SLP_S3#
SLP_S5#
PWRBTN_OUT#
SB_PWRGD

EC_GA20
KB_RST#
H_THERMTRIP#

EC_RSMRST#
SB_OSC_INT

14M_X2

EC_FLASH#

SB_SPKR
SMB_CK_CLK1
SMB_CK_DAT1

AC97_BITCLK
AC97_SDIN0

AC97_RST#
SB_SPDIFO

EC_THERM#<33>

EC_SWI#<33>

EC_SCI#<33>

SLP_S3#<33>
SLP_S5#<33>

PWRBTN_OUT#<33>

SB_PWRGD<36>

EC_GA20<33>
KB_RST#<33>

H_THERMTRIP#<6>

SB_OSC_INT<15>

EC_FLASH#<34>

SB_SPKR<28>
SMB_CK_CLK1<8,9,15>
SMB_CK_DAT1<8,9,15>

AC97_BITCLK<28,30>

AC97_SDOUT<22,28,30>

AC97_SDIN0<28>
AC97_SDIN1<30>

AC97_SYNC<28,30>
AC97_RST#<28,30>

SB_SPDIFO<22>

R1262 10K_0402_5%
R1264 10K_0402_5%

LPC_PME#
LPC_SMI#
S3_STATE
SYS_RESET#
WAKE#

R1271 10K_0402_5%
R1272 10K_0402_5%
R1273 10K_0402_5%

R1274 10K_0402_5%
R1275 10K_0402_5%
R1276 10K_0402_5%
R1278 10K_0402_5%

R1286 33_0402_5%

R1287 33_0402_5%

C6

TALERT#/TEMP_ALERT#/GPIO10

C4

PCI_PME#/GEVENT4#

D3

RI#/EXTEVNT0#

B4

SLP_S3#

E3

SLP_S5#

B3

PWR_BTN#

C3

PWR_GOOD

D4

SUS_STAT#

F2

TEST1

E2

TEST0

AJ26

GA20IN

AJ27

KBRST#

D6

SMBALERT#/THRMTRIP#/GEVENT2#

C5

LPC_PME#/GEVENT3#

A25

LPC_SMI#/EXTEVNT1#

D8

VOLT_ALERT#/S3_STATE/GEVENT5#

D7

SYS_RESET#/GPM7#

D2

WAKE#/GEVENT8#

D1

RSMRST#

A23

14M_X1/OSC

B23

14M_X2

AK24

SIO_CLK

B25

ROM_CS#/GPIO1

C25

GHI#/GPIO6

C23

VGATE/GPIO7

D24

GPIO4

D23

GPIO5

A27

FANOUT0/GPIO3

C24

SPKR/GPIO2

A26

SCL0/GPOC0#

B26

SDA0/GPOC1#

B27

DDC1_SCL/GPIO9

C26

DDC1_SDA/GPIO8

C27

DDC2_SCL/GPIO11

D26

DDC2_SDA/GPIO12

J2

AZ_BITCLK

J3

AZ_SDOUT

D5

BLINK/AZ_SDIN3/GPM6#

K2

AZ_SYNC

A6

USB_OC5#/AZ_RST#/GPM5#

K3

48M_AZ/GPIO46

G1

AC_BITCLK/GPIO38

G2

AC_SDOUT/GPIO39

H4

ACZ_SDIN0/GPIO42

G3

ACZ_SDIN1/GPIO43

G4

ACZ_SDIN2/GPIO44

H1

AC_SYNC/GPIO40

H3

AC_RST#/GPIO45

H2

SPDIF_OUT/GPIO41

SB450

3

SB450 SB

ACPI / WAKE UP EVENTS

CLK / RST

Part 4 of 4

USB_OC0#/GPM0#

USB_OC2#/FANOUT1/LLB#/GPM2#

USB_OC6#/FAN_ALERT#/GEVENT6#

USB_OC7#/CASE_ALERT#/GEVENT7#

USB_OC1#/GPM1#
USB_OC3#/GPM3#

USB_OC4#/GPM4#

USB INTERFACE

GPIOAC97

AZALIA

USB PWR

48M_X1/USBCLK

48M_X2

USB_RCOMP

USB_VREFOUT

USB_ATEST1
USB_ATEST0

USB_HSDP7+
USB_HSDP7+

USB_HSDP6+
USB_HSDM6-

USB_HSDP5+
USB_HSDM5-

USB_HSDP4+
USB_HSDM4-

USB_HSDP3+
USB_HSDM3-

USB_HSDP2+
USB_HSDM2-

USB_HSDP1+
USB_HSDM1-

USB_HSDP0+
USB_HSDM0-

AVDDTX_0
AVDDTX_1
AVDDTX_2
AVDDTX_3
AVDDRX_0
AVDDRX_1
AVDDRX_2
AVDDRX_3

AVDDC

AVSSC

AVSS_USB_1
AVSS_USB_2
AVSS_USB_3
AVSS_USB_4
AVSS_USB_5
AVSS_USB_6
AVSS_USB_7
AVSS_USB_8

AVSS_USB_9
AVSS_USB_10
AVSS_USB_11
AVSS_USB_12
AVSS_USB_13
AVSS_USB_14
AVSS_USB_15
AVSS_USB_16
AVSS_USB_17
AVSS_USB_18
AVSS_USB_19
AVSS_USB_20
AVSS_USB_21
AVSS_USB_22
AVSS_USB_23
AVSS_USB_24

A15
B15
C15
D16
C16
D15
B8
C8
C7
B7
B6
B5
A5

A11
B11

A10
B10

A14
B14

A13
B13

A18
B18

A17
B17

A21
B21

A20
B20

C21
C18
D13
D10
D20
D17
C14
C11

A16
B16
A9

A12
A19
A22
B9
B12
B19
B22
C9
C10
C12
C13
C17
C19
C20
C22
D9
D11
D12
D14
D18
D19
D21
D22

2

USB_VREFOUT

OVCUR#0
OVCUR#1

EC_LID_OUT#

OVCUR#3
OVCUR#4

EC_SMI#

USB20P5+

USB20P5-

+AVDDTX

+AVDDRX

+AVDDC

USBCLK_EXT <15>

1 2

T23 PAD

USB20P5+ <30>EC_RSMRST#<33>
USB20P5- <30>

USB20P4+ <35>
USB20P4- <35>

USB20P1+ <35>
USB20P1- <35>

USB20P0+ <35>
USB20P0- <35>

R125711.8K_0603_1%

OVCUR#0 <35>
OVCUR#1 <35>

EC_LID_OUT# <33>

OVCUR#4 <35>
EC_SMI# <33>

OVCUR#0

1 2

10K_0402_5%

OVCUR#1

1 2

10K_0402_5%

OVCUR#4
EC_SMI#

1 2

10K_0402_5%

1 2

10K_0402_5%

+AVDDTX

C1567 10U_0805_10V4Z
C1568 1U_0603_10V4Z
C1569 0.1U_0402_16V4Z

C1570 0.1U_0402_16V4Z
C1571 0.1U_0402_16V4Z

+AVDDRX

C1572 10U_0805_10V4Z
C1573 1U_0603_10V4Z
C1575 0.1U_0402_16V4Z

C1576 0.1U_0402_16V4Z
C1577 0.1U_0402_16V4Z

+AVDDC

C1579 10U_0805_10V4Z
C1580 1U_0603_10V4Z
C1581 0.1U_0402_16V4Z

1

+3VALW

R19
R20
R21
R22

L90 FBM-L11-321611-260-LMT_1206

12
1 2
1 2
1 2

1 2
1 2

L91 FBM-L11-321611-260-LMT_1206

12
1 2
1 2
1 2

1 2
1 2

L92 FBM-L11-321611-260-LMT_1206

12
1 2
1 2
1 2

+3VALW

+3VALW

+3VALW

AVDDC (20mils)
AVDDTX , AVDDR X (40mils)

HYNIX 128MB

A A

SAMSUMG 128MB

*

No VRAM
Reserved

5

0
1

1

1
00
10

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

4

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/03/01 2005/04/06

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

SB400-USB/ACPI/AC97/GPIO
LA-2931

1

of

19 48Thursday, August 18, 2005

0.3

GPIO11GPIO12

5

4

3

2

1

R681 0_0402_5%

1 2

D D

+1.8VS

+1.8VS

C C

B B

CHB1608U301_0603

L94

1 2

SATA@

CHB1608U301_0603

1U_0402_6.3V4Z SATA@

L95

1 2

SATA@

1U_0402_6.3V4Z SATA@

1

2

1

2

C1643

C1641

+PLLVDD_ATA

R1339
0_0402_5%

NOSATA@

1 2

+XTLVDD_ATA

R1341
0_0402_5%

NOSATA@

1 2

SATA@

33P_0402_25V8K

33P_0402_25V8K SATA@

C1639

12

SATA@

1 2

C1640

12

+1.8VS

CHB1608U301_0603

NOSATA@

Y925MHZ_20P_1BX25000CK1A

1 2

HDD_ACT_LED#<23>

L96

SATA@

12

R680
10M_0402_5%

SATA@

C667

22U_A_4VM

SATA@

SATA_X1

SATA_X2

R1387 close to HDD CONN (JP28)

0.1U_0402_16V4Z

1

C669

2
SATA@

R831

220_0402_5%

SATA@

1 2

R1387 0_0402_5%SATA@

1

C670

2
SATA@

0.1U_0402_16V4Z

+3VS

+

1

2

07/07/'05

R1340 1K_0402_1%SATA@

1 2

0.01U_0402_16V7K@

1

C671

2
SATA@

0.1U_0402_16V4Z

0.1U_0402_16V4Z

12

C1642

1

2
SATA@

SATA_DTX_IRX_P0

SATA_DTX_IRX_N0

SATA_ITX_DRX_N0

SATA_ITX_DRX_P0

C672

SATA_X1
SATA_X2

+PLLVDD_ATA
+XTLVDD_ATA

R1342
0_0402_5%

NOSATA@

1 2

SATA_CAL

SATA_ACT#

AK22

AJ22

AK21

AJ21

AK19

AJ19

AK18

AJ18

AK14

AJ14

AK13

AJ13

AK11

AJ11

AK10

AJ10
AJ15
AJ16

AK16

AH15
AH16
AG10

AG14
AH12
AG12
AG18
AG21
AH18
AG20

AF10
AF11
AF12
AF13
AF14
AF15
AF16
AF17
AF18
AF19
AF20
AF21
AF22

AG11
AG15
AG17
AG19
AG22
AG23

AH17
AH23
AH13
AH20

AJ12
AK17
AK23
AH10

AJ23

AK8

AG9

AH9

AF9

AK9

U58C

SATA_TX0+
SATA_TX0-

SATA_RX0­SATA_RX0+

SATA_TX1+
SATA_TX1-

SATA_RX1­SATA_RX1+

SATA_TX2+
SATA_TX2-

SATA_RX2­SATA_RX2+

SATA_TX3+
SATA_TX3-

SATA_RX3­SATA_RX3+

SATA_CAL
SATA_X1
SATA_X2
SATA_ACT#
PLLVDD_SATA
XTLVDD_SATA
AVDD_SATA_1

AVDD_SATA_2
AVDD_SATA_3
AVDD_SATA_4
AVDD_SATA_5
AVDD_SATA_6
AVDD_SATA_7
AVDD_SATA_8

AVSS_SATA_1
AVSS_SATA_2
AVSS_SATA_3
AVSS_SATA_4
AVSS_SATA_5
AVSS_SATA_6
AVSS_SATA_7
AVSS_SATA_8
AVSS_SATA_9
AVSS_SATA_10
AVSS_SATA_11
AVSS_SATA_12
AVSS_SATA_13
AVSS_SATA_14
AVSS_SATA_15
AVSS_SATA_16
AVSS_SATA_17
AVSS_SATA_18
AVSS_SATA_19
AVSS_SATA_20
AVSS_SATA_21
AVSS_SATA_22
AVSS_SATA_23
AVSS_SATA_24
AVSS_SATA_25
AVSS_SATA_26
AVSS_SATA_27
AVSS_SATA_28
AVSS_SATA_29
AVSS_SATA_30
AVSS_SATA_31
AVSS_SATA_32

SB450 SB

Part 2 of 4

SERIAL ATA

SERIAL ATA POWER

PIDE_IORDY

PIDE_DACK#

PRIMARY ATA 66/100

SIDE_IORDY

SIDE_DACK#

SIDE_D0/GPIO15
SIDE_D1/GPIO16
SIDE_D2/GPIO17
SIDE_D3/GPIO18
SIDE_D4/GPIO19
SIDE_D5/GPIO20
SIDE_D6/GPIO21
SIDE_D7/GPIO22
SIDE_D8/GPIO23

SIDE_D9/GPIO24
SIDE_D10/GPIO25
SIDE_D11/GPIO26
SIDE_D12/GPIO27
SIDE_D13/GPIO28
SIDE_D14/GPIO29
SIDE_D15/GPIO30

SECONDARY ATA 66/100

AVSS_SATA_33
AVSS_SATA_34
AVSS_SATA_35
AVSS_SATA_36
AVSS_SATA_37
AVSS_SATA_38
AVSS_SATA_39
AVSS_SATA_40
AVSS_SATA_41
AVSS_SATA_42
AVSS_SATA_43
AVSS_SATA_44
AVSS_SATA_45

PIDE_IRQ

PIDE_A0
PIDE_A1
PIDE_A2

PIDE_DRQ

PIDE_IOR#
PIDE_IOW#
PIDE_CS1#
PIDE_CS3#

PIDE_D0
PIDE_D1
PIDE_D2
PIDE_D3
PIDE_D4
PIDE_D5
PIDE_D6
PIDE_D7
PIDE_D8

PIDE_D9
PIDE_D10
PIDE_D11
PIDE_D12
PIDE_D13
PIDE_D14
PIDE_D15

SIDE_IRQ

SIDE_A0

SIDE_A1

SIDE_A2

SIDE_DRQ

SIDE_IOR#
SIDE_IOW#
SIDE_CS1#
SIDE_CS3#

AD30
AE28
AD27
AC27
AD28
AD29
AE27
AE30
AE29
AC28
AC29

AF29
AF27
AG29
AH30
AH28
AK29
AK28
AH27
AG27
AJ28
AJ29
AH29
AG28
AG30
AF30
AF28

V29
T27
T28
U29
T29
V30
U28
W29
W30
R27
R28

V28
W28
Y30
AA30
Y28
AA28
AB28
AB27
AB29
AA27
Y27
AA29
W27
Y29
V27
U27

AG13
AH22
AK12
AH11
AJ17
AH14
AH19
AJ20
AH21
AJ9
AG16
AK15
AK20

IDEIORDYA
IDEIRQA
IDESAA0
IDESAA1
IDESAA2
IDEDACK#A
IDEREQA
IDEIOR#A
IDEIOW#A
IDECS#A1
IDECS#A3

IDEDA0
IDEDA1
IDEDA2
IDEDA3
IDEDA4
IDEDA5
IDEDA6
IDEDA7
IDEDA8
IDEDA9
IDEDA10
IDEDA11
IDEDA12
IDEDA13
IDEDA14
IDEDA15

IDEIORDYB
IDEIRQB

IDESAB0
IDESAB1

IDESAB2
IDEDACK#B
IDEREQB
IDEIOR#B
IDEIOW#B

IDECS#B1

IDECS#B3
IDEDB0

IDEDB1
IDEDB2
IDEDB3
IDEDB4
IDEDB5
IDEDB6
IDEDB7
IDEDB8
IDEDB9

IDEDB10
IDEDB11
IDEDB12
IDEDB13
IDEDB14
IDEDB15

IDEIORDYA <23>

IDEI RQA <23>
IDESAA0 <23>
IDESAA1 <23>
IDESAA2 <23>
IDEDACK#A <22,23>

IDEREQA <23>
IDEIOR#A <23>
IDEIOW#A <23>
IDECS#A1 <23>
IDECS#A3 <23>
IDEDA[0..15] <23>

IDEIORDYB <23>
IDEI RQB <23>
IDESAB0 <23>
IDESAB1 <23>
IDESAB2 <23>
IDEDACK#B <23>
IDEREQB <23>
IDEIOR#B <23>
IDEIOW#B <23>
IDECS#B1 <23>
IDECS#B3 <23>
IDEDB[0..15] <23>

SB450

SATA_DTX_IRX_N0

SATA_DTX_IRX_P0 SATA_DTX_C_IRX_P0

SATA_ITX_DRX_N0

SATA_ITX_DRX_P0 SATA_ITX_C_DRX_P0

A A

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/03/01 2005/04/06

Compal Secret Data

Deciphered Date

SATA@

SATA_DTX_C_IRX_N0

12

C1054 0.01U_0402_16V7K

SATA@

12

C1055 0.01U_0402_16V7K

SATA@

SATA_ITX_C_DRX_N0

12

C1056 0.01U_0402_16V7K

SATA@

12

C1057 0.01U_0402_16V7K

2

SATA_DTX_C_IRX_N0 <23>

SATA_DTX_C_IRX_P0 <23>

SATA_ITX_C_DRX_N0 <23>

SATA_ITX_C_DRX_P0 <23>

Title

Size Document Number Rev

Custom

Date: Sheet

SB400-IDE/SATA
LA-2931

1

of

20 48Thursday, August 18, 2005

0.3

+5VS

+3VS

R1289
1K_0402_5%

1 2

D36
CH751H-40_SC76

2 1

C1629

1U_0603_10V4Z

C1582 22U_A_4VM

C1583 0.1U_0402_16V4Z

1 2

C1584 0.1U_0402_16V4Z

1 2

C1585 0.1U_0402_16V4Z

1 2

C1586 0.1U_0402_16V4Z

1 2

C1587 0.1U_0402_16V4Z

1 2

C1588 0.1U_0402_16V4Z

1 2

C1589 0.1U_0402_16V4Z

1 2

C1590 0.1U_0402_16V4Z

1 2

C1591 0.1U_0402_16V4Z

1 2

C1592 0.1U_0402_16V4Z

1 2

C1593 0.1U_0402_16V4Z

1 2

C1594 0.1U_0402_16V4Z

1 2

C1595 0.1U_0402_16V4Z

1 2

C1596 0.1U_0402_16V4Z

1 2

C1597 0.1U_0402_16V4Z

1 2

C1598 0.1U_0402_16V4Z

1 2

C1599 0.1U_0402_16V4Z

1 2

C1600 22U_A_4VM
C1601 22U_A_4VM

C1602 0.1U_0402_16V4Z

1 2

C1603 0.1U_0402_16V4Z

1 2

C1604 0.1U_0402_16V4Z

1 2

C1605 0.1U_0402_16V4Z

1 2

C1606 0.1U_0402_16V4Z

1 2

C1607 0.1U_0402_16V4Z

1 2

C1608 0.1U_0402_16V4Z

1 2

C1609 0.1U_0402_16V4Z

1 2

C1610 0.1U_0402_16V4Z

1 2

C1611 0.1U_0402_16V4Z

1 2

C1612 0.1U_0402_16V4Z

1 2

C1613 0.1U_0402_16V4Z

1 2

C1614 22U_A_4VM

C1615 0.1U_0402_16V4Z

1 2

C1616 0.1U_0402_16V4Z

1 2

C1617 0.1U_0402_16V4Z

1 2

C1618 0.1U_0402_16V4Z

1 2

C1619 0.1U_0402_16V4Z

1 2

C1620 10U_0805_10V4Z

1 2
1 2

1 2
1 2

1 2
1 2
1 2
1 2

2

C1630

0.1U_0402_16V4Z

1

+V5_VREF

C1631 10U_0805_10V4Z
C1632 1U_0603_10V4Z
C1633 0.1U_0402_16V4Z

C1621 0.1U_0402_16V4Z
C1622 0.1U_0402_16V4Z
C1623 0.1U_0402_16V4Z

C1625 0.1U_0402_16V4Z
C1626 0.1U_0402_16V4Z
C1627 0.1U_0402_16V4Z
C1628 0.1U_0402_16V4Z

2

1

+3VS

+

12

+1.8VS

+

12

+

12

+3VALW

+

12

+1.8VALW

C1624 0.1U_0402_16V4Z

+1.2V_HT

FBM-L11-321611-260-LMT_1206

1 2
1 2
1 2

L93

V5_VREF (20mils)
AVDD_CK(40mils)

+1.8VS

U58D

A30
D30
E24
E25

J5
K1
K5

N5

P5
R1
U5

U26
U30

V5

V26

Y1

Y26

AA5

AA26

AB5

AC30

AD5

AD26

AE1
AE5

AE26

AF6

AF7
AF24
AF25

AK1

AK4
AK26
AK30

M12

M13

M18

M19

N12

N13

N18

N19

V12

V13

V18

V19

W12
W13
W18
W19

A3
A7
E6
E7
E1
F5

E9
E10
E20
E21

E13
E14
E16

12

+AVDD_CK

12

E17
C30
AG6
A24

B24

A29
B28

E11
E12
E15
E18

A4

A8

C1

E5

E8

VDDQ_1
VDDQ_2
VDDQ_3
VDDQ_4
VDDQ_5
VDDQ_6
VDDQ_7
VDDQ_8
VDDQ_9
VDDQ_10
VDDQ_11
VDDQ_12
VDDQ_13
VDDQ_14
VDDQ_15
VDDQ_16
VDDQ_17
VDDQ_18
VDDQ_19
VDDQ_20
VDDQ_21
VDDQ_22
VDDQ_23
VDDQ_24
VDDQ_25
VDDQ_26
VDDQ_27
VDDQ_28
VDDQ_29
VDDQ_30
VDDQ_31
VDDQ_32
VDDQ_33
VDDQ_34

VDD_1
VDD_2
VDD_3
VDD_4
VDD_5
VDD_6
VDD_7
VDD_8
VDD_9
VDD_10
VDD_11
VDD_12
VDD_13
VDD_14
VDD_15
VDD_16

S5_3.3V_1
S5_3.3V_2
S5_3.3V_3
S5_3.3V_4
S5_3.3V_5
S5_3.3V_6

S5_1.8V_1
S5_1.8V_2
S5_1.8V_3
S5_1.8V_4

USB_PHY_1.8V_1
USB_PHY_1.8V_2
USB_PHY_1.8V_3
USB_PHY_1.8V_4

CPU_PWR
V5_VREF
AVDDCK

AVSSCK
VSS_1

VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
VSS_10
VSS_11

SB450

SB450 SB

Part 3 of 4

POWER

VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47
VSS_48
VSS_49
VSS_50
VSS_51
VSS_52
VSS_53
VSS_54
VSS_55
VSS_56
VSS_57
VSS_58
VSS_59
VSS_60
VSS_61
VSS_62
VSS_63
VSS_64
VSS_65
VSS_66
VSS_67
VSS_68
VSS_69
VSS_70
VSS_71
VSS_72
VSS_73
VSS_74
VSS_75
VSS_76
VSS_77
VSS_78
VSS_79
VSS_80
VSS_81
VSS_82
VSS_83
VSS_84
VSS_85
VSS_86
VSS_87
VSS_88
VSS_89
VSS_90
VSS_91
VSS_92
VSS_93
VSS_94
VSS_95
VSS_96
VSS_97
VSS_98

E19
E22
E23
E26
E30
F1
F4
G5
H5
J1
J4
K4
L5
M5
P1
R5
R26
T5
T26
T30
W1
W5
W26
Y5
AB26
AB30
AC5
AC26
AD1
AF5
AF8
AF23
AF26
AG8
AJ1
AJ24
AJ30
AK5
AK25
M14
M15
M16
M17
N14
N15
N16
N17
P12
P13
P14
P15
P16
P17
P18
P19
R12
R13
R14
R15
R16
R17
R18
R19
T12
T13
T14
T15
T16
T17
T18
T19
U12
U13
U14
U15
U16
U17
U18
U19
V14
V15
V16
V17
W14
W15
W16
W17

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2005/03/01 2005/04/06

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

Date: Sheet

SB400-Power/GND
LA-2931

of

21 48Thursday, August 18, 2005

0.3

5

4

3

2

1

+3VALW +3VS +3VALW +3VS +3VS +3VS +3VS +3VS +3VS +3VS

+3VS

REQUIRED STRAPS

12

R1290
10K_0402_5%

AUTO_ON#<18>

AC97_SDOUT<19,28,30>

D D

RTC_CLK<18>
SB_SPDIFO<19>

CLK_PCI_EC<18,33>

CLK_PCI_SIO<18,32>

CLK_PCI_1394<18,27>

CLK_PCI_SIO_DB<18,33>

CLK_PCI7<18>
CLK_PCI8<18>

CLK_PCI_MINI<18,31>

AUTO_ON#
AC97_SDOUT
RTC_CLK
SB_SPDIFO
CLK_PCI_EC
CLK_PCI_SIO
CLK_PCI_1394
CLK_PCI6
CLK_PCI7
CLK_PCI8
CLK_PCI_MINI

12

R1301
10K_0402_5%@

12

R1291
10K_0402_5%

@

12

R1302
10K_0402_5%

ACPWRON

AUTO_ON#

PULL

C C

HIGH

PULL
LOW

MANUAL

PWR ON

DEFAULT

AUTO
PWR
ON

DEBUG STRAPS

IDEDACK#A<20,23>

PCI_AD31<18,24,26,27,31>
PCI_AD30<18,24,26,27,31>
PCI_AD29<18,24,26,27,31>
PCI_AD28<18,24,26,27,31>
PCI_AD27<18,24,26,27,31>

B B

PCI_AD26<18,24,26,27,31>
PCI_AD25<18,24,26,27,31>
PCI_AD24<18,24,26,27,31>
PCI_AD23<18,24,26,27,31>

IDEDACK#A
PCI_AD31
PCI_AD30
PCI_AD29
PCI_AD28
PCI_AD27
PCI_AD26
PCI_AD25
PCI_AD24
PCI_AD23

AC97_SDOUT SB _SPDIFO

USE
DEBUG
STRAPS

IGNORE
DEBUG
STRAPS

DEFAULT

+3VS +3VS +3VS +3VS +3VS +3VS +3VS +3VS +3VS +3VS

12

R1311
10K_0402_5%

12

R1321
1K_0402_5%

@

12

R1312
10K_0402_5%

12

R1322
10K_0402_5%

@

12

R1292
10K_0402_5%

RTC_CLK

INTERNAL
RTC

DEFAULT

EXTERNAL
RTC (NOT
SUPPORTED
W/ IT8712 )

12

R1313
10K_0402_5%

12

R1323
10K_0402_5%

@

12

R1293
10K_0402_5%

@

12

R1303
10K_0402_5%

SIO 24MHz

SIO 48MHz

DEFAULT

12

R1314
10K_0402_5%

12

R1324
10K_0402_5%

@

12

R1294
10K_0402_5%

12

R1304
10K_0402_5%

@

12

R1295
10K_0402_5%

12

R1305
10K_0402_5%

@

12

R1296
10K_0402_5%

12

R1306
10K_0402_5%

@

12

R1297
10K_0402_5%

12

R1307
10K_0402_5%

@

PCI_CLK2 PCI_CLK3 PCI_CLK4 PCI_CLK5

CLK_PCI_MINI

48MHz OSC
MODE

48MHz XTAL
MODE

12

R1315
10K_0402_5%

12

R1325
10K_0402_5%

@

CLK_PCI_EC

USB PHY
PWRDOWN
DISABLE

DEFAULT DEFAULT

USB PHY
PWRDOWN
ENABLE

12

R1316
10K_0402_5%

@

12

R1326
10K_0402_5%

12

R1317
10K_0402_5%

@

12

R1327
10K_0402_5%

CLK_PCI_SIO

INTERNAL
48MHz

DEFAULT

EXTERNAL
48MHz

12

12

CLK_PCI_1394

PCIE_CM_SET
LOW

DEFAULT

PCIE_CM_SET
High

R1318
10K_0402_5%

@

R1328
10K_0402_5%

12

R1298
10K_0402_5%

@

12

R1308
10K_0402_5%

12

R1319
10K_0402_5%

@

12

R1329
10K_0402_5%

12

R1299
10K_0402_5%

12

R1309
10K_0402_5%

@

CLK_PCI6

CPU I/F = K8

CPU I/F = P4

12

R1320
10K_0402_5%

12

R1330
10K_0402_5%

@

12

R1300
10K_0402_5%

@

12

R1310
10K_0402_5%

@

CLK_PCI7

PCI_CLK8

ROM TYPE
H,H = PCI ROM

H,L = PMC LPC ROM

L,H = NORMAL LPC ROM

L,L = FWH ROM

DEFAULT

PD_DACK#

PULL
HIGH

PULL

A A

5

LOW

USE
LONG
RESET

DEFAULT

USE
SHORT
RESET

PCI_AD31

4

PCI_AD30

PCI_AD29

PCI_AD28

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

PCI_AD27 PCI_AD26

BYPASS
PCI PLL

USE PCI
PLL

DEFAULT

3

BYPASS
ACPI
BCLK

USE
ACPI
BCLK

DEFAULT

2005/03/01 2005/04/06

Compal Secret Data

PCI_AD25 PCI_AD24

BYPASS IDE
PLL

USE IDE
PLL

DEFAULT

Deciphered Date

USE EEPROM
PCIE STRAPS

USE DEFAULT
PCIE STRAPS

DEFAULT

2

PCI_AD23

RESERVEDRESERVED RESERVED RESERVED RESERVED

Title

Size Document Number Rev

Custom

Date: Sheet

Hardware Trap
LA-2931

1

22 48Thursday, August 18, 2005

0.3

of

5

4

3

2

1

HDD CONN

IDEDA[0..15]<20>

C590

IDESAA[0..2]<20>

NB_RST#
IDEDA7
IDEDA6
IDEDA5
IDEDA4
IDEDA3
IDEDA2
IDEDA1
IDEDA0

IDEREQA
IDEIOW#A
IDEIOR#A
IDEIORDYA
IDEDACK#A
IDEIRQA
IDESAA1
IDESAA0
IDECS#A1

1

2

For 2 Spindle

D D

NB_RST#<13,18,32>

7/14

1

2

IDEREQA<20>
IDEIOW#A<20>
IDEIOR#A<20>
IDEIORDYA<20>
IDEDACK#A<20,22>
IDEIRQA<20>

IDECS#A1<20>

0.1U_0402_16V4Z

1

C593

2

+5VS

1000P_0402_50V7K

+5VS

12

R224

100K_0402_5%

HDD_ACT_LED#

C C

B B

HDD_ACT_LED#<20>

+5VS

10U_0805_10V4Z

1

C598

2

C594

0.1U_0402_16V4Z

IDEDA[0..15]
IDESAA[0..2]

JP28

1 2
3 4
5 6
7 8
9 10
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
29 30
31 32
33 34
35 36
37 38
39 40
41 42
43 44

CONN@

SUYIN_200138FR044G272ZU_RV

R1389

100K_0402_5%

+5VS

12

ODD_ACT_LED#

IDEDA8
IDEDA9
IDEDA10
IDEDA11
IDEDA12
IDEDA13
IDEDA14
IDEDA15

IDE_CSEL

IDESAA2
IDECS#A3

7/14

80mils80mils

IDEIOW#B<20>
IDEIORDYB<20>
IDEIRQB<20>

SATA HDD CONN

JP29

S1

SATA_DTX_C_IRX_P0<20>
SATA_DTX_C_IRX_N0<20>

SATA_ITX_C_DRX_N0<20>
SATA_ITX_C_DRX_P0<20>

SATA_DTX_C_IRX_P0
SATA_DTX_C_IRX_N0

SATA_ITX_C_DRX_N0
SATA_ITX_C_DRX_P0

GND

S2

HTX+

S3

HTX-

S4

GND

S5

HRX-

S6

HRX+

S7

GND

IDEDB[0..15]<20>

IDESAB[0..2]<20>

R219 470_0402_5%

1 2

IDECS#A3 <20>

+5VS

INT_CD_L INT_CD_R

12

CD_AGND
NB_RST#
IDEDB7
IDEDB6
IDEDB5
IDEDB4
IDEDB3
IDEDB2
IDEDB1
IDEDB0

IDEIOW#B
IDEIORDYB
IDEIRQB
IDESAB1
IDESAB0
IDECS#B1

SD_CSEL

CD_AGND<28>

IDECS#B1<20>

+5VS

R567 470_0402_5%

If CDROM is Slave
then SD_CSEL= Floating
else SD_CSEL= Low

IDEDB[0..15]

IDESAB[0..2]

CDROM CONN

JP39

1
3
5
7

9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51 52

OCTEK_CDR-50JD1

CONN@

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50

HDD_ACT_LED#

ODD_ACT_LED#

IDEDB8
IDEDB9
IDEDB10
IDEDB11
IDEDB12
IDEDB13
IDEDB14
IDEDB15
IDEREQB
IDEIOR#B

IDEDACK#B

IDESAB2
IDECS#B3

1 2

R566
100K_0402_5%

@

D38

21

RB751V_SOD323

D39

21

RB751V_SOD323

7/14

IDEREQB <20>
IDEIOR#B <20>

IDEDACK#B <20>

IDECS#B3 <20>

80mils

+5VS

R1388

100K_0402_5%

INT_CD_R <28>INT_CD_L<28>

+5VS

+5VS

12

IDE_LED# <33>

+5VS

1

C270

2

0.1U_0402_16V4Z

1

C268

2

1

C267

2

1000P_0402_50V7K

10U_0805_10V4Z

1

C279

2

1U_0603_10V4Z

P1

+3VS

+5VS

1

C548

A A

150U_D2_6.3VM@

+

2

+5VS

Close to SATA HDD

5

VCC3.3

P2

VCC3.3

P3

VCC3.3

P4

GND

P5

GND

P6

GND

P7

VCC5

P8

VCC5

P9

VCC5

P10

GND

P11

RESERVED

P12

GND

P13

VCC12
VCC12
VCC12

GND
GND

P14
P15

OCTEK_SAT-22RD1_REVERS

@

For 2 Spindle

23
24

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2005/03/01 2005/04/06

3

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

HDD/CDROM
LA-2931

1

0.3

23 48Thursday, August 18, 2005

of

5

4

3

2

1

2

+3VS

+3VS

+S1_VCC

S1_A16

1 2

R590 33_0402_5%51@

1

C347

0.1U_0402_16V4Z

2

1

C349

0.1U_0402_16V4Z

2

1

C617

0.1U_0402_16V4Z

2

1

C346

0.1U_0402_16V4Z

2

1

C357

0.1U_0402_16V4Z

2

1

C618

0.1U_0402_16V4Z

2

10P_0402_50V8K

S1_CD1#

1

2

1

2

C348

C620

0.1U_0402_16V4Z

C605

0.1U_0402_16V4Z

1

C616

0.1U_0402_16V4Z

2

1

10P_0402_50V8K

2

S1_CD2#

2

C623

0.1U_0402_16V4Z

1

1

C599

0.1U_0402_16V4Z

2

1

C615

0.1U_0402_16V4Z

2

1

C619

2

Closed to Pin A4Closed to Pin L12

Chip has internal pull low

MSD0_XDD2
MSD1_XDD6
MSD2_XDD5
MSD3_XDD3
MSBS_XDD1

1 2

R582 43K_0402_5%@

1 2

R579 43K_0402_5%@

1 2

R585 43K_0402_5%@

1 2

R588 43K_0402_5% @

1 2

R575 43K_0402_5%@

Close chip termenal

MSCLK_XDRE# <25>

Title

Size Document Number Rev

Custom

Date: Sheet

PCMCIA ENE CB714
LA-2931

1

of

24 48Thursday, August 18, 2005

0.3

VPPD0<25>

VPPD1<25>
VCCD0#<25>
VCCD1#<25>

U39

PCI_AD[0..31]

PCI_AD31

C2

PCI_AD30
PCI_AD29
PCI_AD28
PCI_AD27
PCI_AD26
PCI_AD25
PCI_AD24
PCI_AD23
PCI_AD22
PCI_AD21
PCI_AD20
PCI_AD19
PCI_AD18
PCI_AD17
PCI_AD16
PCI_AD15
PCI_AD14
PCI_AD13
PCI_AD12
PCI_AD11
PCI_AD10
PCI_AD9
PCI_AD8
PCI_AD7
PCI_AD6
PCI_AD5
PCI_AD4
PCI_AD3
PCI_AD2
PCI_AD1
PCI_AD0

PCI_RST#
PCI_FRAME#
PCI_IRDY#
PCI_TRDY#
PCI_DEVSEL#
PCI_STOP#
PCI_PERR#
PCI_SERR#
PCI_PAR
PCI_REQ#2
PCI_GNT#2

CLK_PCI_PCM

1 2

R563 10K_0402_5%
R584 100_0402_1%

+VCC_5IN1

PCM_ID

1 2

PCI_PIRQE#

SD_PULLHIGH

PCI_PIRQH#

SIRQ

PCI_RST#

SDCD#
SDWP

CLK_SD_48M

SDCM_XDALE
SDDA0_XDD7
SDDA1_XDD0
SDDA2_XDCL XDWP#
SDDA3_XDD4

AD31

C1

AD30

D4

AD29

D2

AD28

D1

AD27

E4

AD26

E3

AD25

E2

AD24

F2

AD23

F1

AD22

G2

AD21

G3

AD20

H3

AD19

H4

AD18

J1

AD17

J2

AD16

N2

AD15

M3

AD14

N3

AD13

K4

AD12

M4

AD11

K5

AD10

L5

AD9

M5

AD8

K6

AD7

M6

AD6

N6

AD5

M7

AD4

N7

AD3

L7

AD2

K7

AD1

N8

AD0

E1

CBE3#

J3

CBE2#

N1

CBE1#

N5

CBE0#

G4

PCIRST#

J4

FRAME#

K1

IRDY#

K3

TRDY#

L1

DEVSEL#

L2

STOP#

L3

PERR#

M1

SERR#

M2

PAR

A1

PCIREQ#

B1

PCIGNT#

H1

PCICLK

L8

RIOUT#_PME#

L11

SUSPEND#

F4

IDSEL

K8

MFUNC0

N9

MFUNC1

K9

MFUNC2

N10

MFUNC3

L10

MFUNC4

N11

MFUNC5

M11

MFUNC6

J9

MFUNC7

M10

GRST#

E7

VCC_SD

E8

SDCD#

F8

SDWP/SMWPD#

G7

SDPWREN33#

H5

SDCLKI

F6

SDCLK/SMWE#

E5

SDCMD/SMALE

E6

SDDAT0/SMDATA7

F7

SDDAT1/SMDATA0

F5

SDDAT2/SMCLE

G6

SDDAT3/SMDATA4

G5

GND_SD

+3VS

PCI_AD[0..31]<18,22,26,27,31>

PCI_AD20

SDOC#
MSOC#

SDPWREN#<25>

CLK_SD_48M<15>

SDCM_XDALE<25>

SDDA0_XDD7<25>
SDDA1_XDD0<25>
SDDA2_XDCL<25>
SDDA3_XDD4<25>

PCI_CBE#3<18,26,27,31>
PCI_CBE#2<18,26,27,31>
PCI_CBE#1<18,26,27,31>
PCI_CBE#0<18,26,27,31>

PCI_RST#<18,26,27,31,33>

PCI_FRAME#<18,26,27,31>

PCI_IRDY#<18,26,27,31>
PCI_TRDY#<18,26,27,31>

PCI_DEVSEL#<18,26,27,31>

PCI_STOP#<18,26,27,31>
PCI_PERR#<18,26,27,31>

PCI_SERR#<18,26,31>

PCI_PAR<18,26,27,31>
PCI_REQ#2<18>
PCI_GNT#2<18>

CLK_PCI_PCM<18>

PCI_PIRQE#<18,27>
PCI_PIRQH#<18>

SIRQ<18,32,33>

SDCD#<25>
SDWP<25>

4

D D

CLK_PCI_PCM

12

R581
10_0402_5%@

1

C591
15P_0402_50V8J

@

2

C C

+3VS

R834

PCI_PERR#

1 2

4.7K_0402_5%

+3VS

IDSEL:
PCI_AD20

R565

R297

43K_0402_5%51@

B B

A A

CARD_LED#<33>

12

@

1

@

2

+3VS

Chip has internal pull high

1 2

R592 43K_0402_5%@

1 2

R568 43K_0402_5%@

1 2

R587 43K_0402_5%@

CLK_SD_48M

R296

10_0402_5%

C344

15P_0402_50V8J

SDCD#
SDWP
MSINS#

43K_0402_5%51@

1 2

1 2

SDCK<25>

XDWE#<25>

Close chip termenal

5

SD_PULLHIGH<25>

SDOC#<25>
MSOC#<25>

R570 22_0402_5%51@

1 2

R569 22_0402_5%51@

1 2

SDCD# & SDWP# & MSINS# have
internal 30Kohm pull up resistor

N12

N13

M13

VCCD0#

VCCD1#

M12

VPPD1

VPPD0

PCI Interface

G13

A7

VCCA2

B4

VCCA1

K2

N4

L6

C8

L9

H11

D12

VCC3

VCC4

VCC5

VCC9

VCC6

VCC7

VCC8

VCC10

CAD15/IOWR#

CCBE3#/REG#

CARDBUS

CRST#/RESET
CFRAME#/A23

CDEVSEL#/A21

CSERR#/WAIT#

CREQ#/INPACK#

CSTSCHG/BVD1_STSCHG#

CCLKRUN#/WP_IOIS16#

CBLOCK#/A19

CINT#/READY_IREQ#

CAUDIO/BVD2_SPKR#

SD/MMC/MS/SM

MSPWREN#/SMPWREN#

MSBS/SMDATA1

MSCLK/SMRE#
MSDATA0/SMDATA2
MSDATA1/SMDATA6
MSDATA2/SMDATA5
MSDATA3/SMDATA3

GND1D3GND2H2GND3L4GND4M8GND5

GND6

GND7

GND8

CB714_LFBGA169

B6

F12

K11

C10

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

+S1_VCC
+3VS

G1

F3

VCC2

VCC1

CAD31/D10

CAD30/D9
CAD29/D1
CAD28/D8
CAD27/D0
CAD26/A0
CAD25/A1
CAD24/A2
CAD23/A3
CAD22/A4
CAD21/A5
CAD20/A6

CAD19/A25

CAD18/A7
CAD17/A24
CAD16/A17

CAD14/A9

CAD13/IORD#

CAD12/A11

CAD11/OE#

CAD10/CE2#

CAD9/A10

CAD8/D15

CAD7/D7

CAD6/D13

CAD5/D6

CAD4/D12

CAD3/D5

CAD2/D11

CAD1/D4
CAD0/D3

CCBE2#/A12

CCBE1#/A8

CCBE0#/CE1#

CIRDY#/A15

CTRDY#/A22
CSTOP#/A20

CPERR#/A14

CPAR/A13

CGNT#/WE#

CCLK/A16

SPKROUT

CCD2#/CD2#
CCD1#/CD1#

CVS2/VS2#

CVS1/VS1

CRSV3/D2
CRSV2/A18
CRSV1/D14

MSINS#

SMBSY#

SMCD#
SMWP#

SMCE#

2005/03/01 2005/04/06

S1_A[0..25]
S1_D[0..15]

S1_D10

B2

S1_D9

C3

S1_D1

B3

S1_D8

A3

S1_D0

C4

S1_A0

A6

S1_A1

D7

S1_A2

C7

S1_A3

A8

S1_A4

D8

S1_A5

A9

S1_A6

C9

S1_A25

A10

S1_A7

B10

S1_A24

D10

S1_A17

E12

S1_IOWR#

F10

S1_A9

E13

S1_IORD#

F13

S1_A11

F11

S1_OE#

G10

S1_CE2#

G11

S1_A10

G12

S1_D15

H12

S1_D7

H10

S1_D13

J11

S1_D6

J12

S1_D12

K13

S1_D5

J10

S1_D11

K10

S1_D4

K12

S1_D3

L13

S1_REG#

B7

S1_A12

A11

S1_A8

E11

S1_CE1#

H13

S1_RST

B9

S1_A23

B11

S1_A15

A12

S1_A22

A13

S1_A21

B13

S1_A20

C12

S1_A14

C13

S1_WAIT#

A5

S1_A13

D13

S1_INPACK#

B8

S1_WE#

C11

A16_CLK

B12

S1_BVD1

C5

S1_WP

D5

S1_A19

D11

S1_RDY#

D6

PCM_SPK#

M9

S1_BVD2

B5

S1_CD2#

A4

S1_CD1#

L12

S1_VS2

D9

S1_VS1

C6

S1_D2

A2

S1_A18

E10

S1_D14

J13

MSINS#

H7
J8

MSBS_XDD1

H8
E9

MSD0_XDD2

G9

MSD1_XDD6

H9

MSD2_XDD5

G8

MSD3_XDD3

F9

H6
J7
J6
J5

Compal Secret Data

S1_A[0..25] <25>
S1_D[0..15] <25>

S1_IOWR# <25>
S1_IORD# <25>
S1_OE# <25>

S1_CE2# <25>

S1_REG# <25>

S1_CE1# <25>
S1_RST <25>

S1_WAIT# <25>
S1_INPACK# <25>

S1_WE# <25>

1 2

R593 33_0402_5%

S1_BVD1 <25>
S1_WP <25>

S1_RDY# <25>
PCM_SPK# <28>

S1_BVD2 <25>
S1_CD2# <25>

S1_CD1# <25>
S1_VS2 <25>
S1_VS1 <25>

XDBSY#
XDCD#

XDCE#

R574

2.2K_0402_5%51@

1 2

Deciphered Date

MSINS# <25>

XD_MS_PWREN# <25>
MSBS_XDD1 <25>

MSD0_XDD2 <25>
MSD1_XDD6 <25>
MSD2_XDD5 <25>
MSD3_XDD3 <25>

XDBSY# <25>

XDCD# <25>
XDWP# <25>
XDCE# <25>

5

PCMCIA Power Controller

+5VS

+3VS

U36

9

12V

5

5V

6

5V

3

3.3V

4

3.3V
GND

7

1 2

XDBSY# <24>
XDCE# <24>

XDWE# <24>

Don't support 12V card

D D

C5730.1U_0402_16V4Z
C5704.7U_0805_10V4Z

C5740.1U_0402_16V4Z
C5714.7U_0805_10V4Z

R562

10K_0402_5%

C C

+VCC_SM/XD

XDBSY#

12

R551 43K_0402_5%51@

1 2

R547 43K_0402_5%51@
R564 43K_0402_5%51@
R545 2.2K_0402_5%51@

MSCLK_XDRE#

12

XDWE#

12

+SD_PULLHIGH by BIOS setting

SD_PULLHIGH<24>

1 2

R294 43K_0402_5%@

1 2

B B

R557 43K_0402_5%@

1 2

R553 43K_0402_5%@

1 2

R541 43K_0402_5%@

1 2

R560 43K_0402_5%@

1 2

R559 43K_0402_5%@

SD_PULLHIGH

10.4

SD_PULLHIGH
SDCM_XDALE
SDDA0_XDD7
SDDA1_XDD0
SDDA2_XDCL
SDDA3_XDD4

Close to 5 in 1 socket

+3VS

R536

A A

SDPWREN#<24>

XD_MS_PWREN#<24>

4.7K_0402_5%51@

1 2

1 2

R632 0_0402_5%51@

5

13

VCC

12

VCC

11

VCC

10

VPP

1

VCCD0

2

VCCD1

15

VPPD0

14

VPPD1

8

OC

SHDN

16

CP2211D3_SSOP16

Reserve for SD pull high issue.

SD CLK

MS CLK

+3VS

40mil

20mil

@

SDCK<24>

10P_0402_50V8K@

MSCLK_XDRE#<24>

10P_0402_50V8K@

1
2
3
4

4

+S1_VCC

+S1_VPP

12

C585 0.1U_0402_16V4Z
C584 0.1U_0402_16V4Z
C586 10U_0805_10V4Z
C583 0.01U_0402_16V7K
C587 1U_0603_10V4Z

VCCD0# <24>
VCCD1# <24>
VPPD0 <24>
VPPD1 <24>

R550
0_0805_5%

C579

R549

0_0402_5%@

C572

1 2

1 2
1 2
1 2

1

2

SDCK

MSCLK_XDRE#

12

1

2

5 IN 1 PWR Control

U49

GND
IN
IN
EN#

TPS2041ADR_SO851@

8

OUT

7

OUT

6

OUT

5

OC#

R531

100K_0402_5%51@

4

+VCC_5IN1

3

Chip has internal pull high

XDCD#<24>

Close to
CardBus Conn.

1

C337

C343

0.1U_0402_16V4Z

2

1

2

10U_0805_10V4Z

4.7U_0805_10V4Z

SD/ MMC/ MS

+VCC_5IN1

SDDA1_XDD0
MSBS_XDD1
MSD0_XDD2
MSD3_XDD3
SDDA3_XDD4
MSD2_XDD5
MSD1_XDD6
SDDA0_XDD7

XDWE#

XDWP#<24>

1U_0603_10V4Z@

R538

1 2

0_0402_5%51@

12

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

XDWP#
SDCM_XDALE
XD_CD#
XDBSY#
MSCLK_XDRE#
XDCE#
SDDA2_XDCL

+VCC_SM/XD

1

2

0.1U_0402_16V4Z51@

R537

10K_0402_5%51@

R633

1 2

0_0402_5%51@

1

C657

2

SDOC# <24>

3

C656

+3VS

1 2

+VCC_5IN1 +VCC_SM/XD

+S1_VCC

1

C339

2

+S1_VPP

1

C341

0.01U_0402_16V7K

MSOC#

R571

1 2

0_0603_5%51@

2005/03/01 2005/04/06

2

1U_0603_10V4Z@

JP36

34

XD-VCC

SD / MMC / MS(PRO) / XD

26

XD-D0

27

XD-D1

28

XD-D2

29

XD-D3

30

XD-D4

31

XD-D5

32

XD-D6

33

XD-D7

24

XD-WE

25

XD-WP

23

XD-ALE

18

XD-CD

19

XD-R/B

20

XD-RE

21

XD-CE

22

XD-CLE

37

GND

38

GND

TAITW_R007-520-L351@

+VCC_5IN1

0.1U_0402_16V4Z51@

1

2

0.1U_0402_16V4Z51@

MSOC# <24>

1

2

C551

1U_0603_10V4Z@

Compal Secret Data

Deciphered Date

1

C589

2

4 IN 1 CONN

1

C556

C555

2

SDDA3_XDD4
SDDA1_XDD0
SDDA0_XDD7
SDCM_XDALE
SDDA2_XDCL
MSBS_XDD1
MSD1_XDD6
MSD0_XDD2
MSD2_XDD5
MSINS#
MSD3_XDD3
SDWP
SDCD#

0.1U_0402_16V4Z51@

SD-VCC
MS-VCC

SD-CLK
SD-DAT0
SD-DAT1
SD-DAT2
SD-DAT3

SD-CMD

SD-CD-SW

SD-WP-SW

MS-SCLK
MS-DATA0
MS-DATA1
MS-DATA2
MS-DATA3

MS-INS

MS-BS

4IN1-GND
4IN1-GND

1

C554

2

0.1U_0402_16V4Z51@

C580

0.1U_0402_16V4Z51@

2

R552

43K_0402_5%@

XDCD#

0.1U_0402_16V4Z51@

14
3

15
16
17
11
12
13
2
35

4
8
9
7
5
6
10

1
36

1

C553

2

R629

4.7K_0402_5%@

XD_MS_PWREN#

2

+3VS

12

51@

C588

SDCK
SDDA0_XDD7
SDDA1_XDD0
SDDA2_XDCL
SDDA3_XDD4
SDCM_XDALE
SDCD#
SDWP

MSCLK_XDRE#
MSD0_XDD2
MSD1_XDD6
MSD2_XDD5
MSD3_XDD3
MSINS#
MSBS_XDD1

+3VS

1 2

13

D

MSINS#

2

G

Q45

S

2N7002_SOT23

XD_CD#

SDDA3_XDD4 <24>

SDDA1_XDD0 <24>

SDDA0_XDD7 <24>

SDCM_XDALE <24>
SDDA2_XDCL <24>

MSBS_XDD1 <24>
MSD1_XDD6 <24>
MSD0_XDD2 <24>
MSD2_XDD5 <24>

MSINS# <24>

MSD3_XDD3 <24>

SDWP <24>

SDCD# <24>

+VCC_5IN1

+3VS

R627

10K_0402_5%@

100K

2

100K

1

R628

1 2

0_0402_5%@

R630
100K_0402_5%@

1

S1_A[0..25]
S1_D[0..15]

S1_CD1# <24>

S1_CE1# <24>

S1_CE2# <24>
S1_OE# <24>
S1_VS1 <24>

S1_IORD# <24>
S1_IOWR# <24>

S1_WE# <24>
S1_RDY# <24>

+S1_VCC
+S1_VCC
+S1_VPP
+S1_VPP

S1_VS2 <24>
S1_RST <24>
S1_WAIT# <24>
S1_INPACK# <24>
S1_REG# <24>
S1_BVD2 <24>
S1_BVD1 <24>

S1_WP <24>
S1_CD2# <24>

+3VS

R626

10K_0402_5% @

1 2

1

C666

0.1U_0402_16V4Z@

2

25 48Thursday, August 18, 2005

of

S1_A[0..25]<24>
S1_D[0..15]<24>

CardBus Socket

JP7

69

GND

70

GND

SANTA_130609-1_LT

CONN@

5 IN 1 PWR Control

+3VS

U48

4

Q44
DTC115EKA_SOT23@

VIN

CE1GND

RT9702ACB_SOT23-5 @

13
1 2

Title

Size Document Number Rev

Custom

Date: Sheet

GND
GND

DATA3

CD1#

DATA4

DATA11

DATA5

DATA12

DATA6

DATA13

DATA7

DATA14

CE1#

DATA15

ADD10

CE2#

OE#

VS1#

ADD11

IORD#

ADD9

IOWR#

ADD8
ADD17
ADD13
ADD18
ADD14
ADD19

WE#

ADD20

READY

ADD21

VCC
VCC
VPP

VPP
ADD16
ADD22
ADD15
ADD23
ADD12
ADD24

ADD7

ADD25

ADD6

VS2#

ADD5

RESET

ADD4

WAIT#

ADD3

INPACK#

ADD2
REG#
ADD1
BVD2
ADD0

BVD1
DATA0
DATA8
DATA1
DATA9
DATA2

DATA10

CD2#

GND
GND

VOUT

WP

FLG

1
35

S1_D3

2

S1_CD1#

36

S1_D4

3

S1_D11

37

S1_D5

4

S1_D12

38

S1_D6

5

S1_D13

39

S1_D7

6

S1_D14

40

S1_CE1#

7

S1_D15

41

S1_A10

8

S1_CE2#

42

S1_OE#

9

S1_VS1

43

S1_A11

10

S1_IORD#

44

S1_A9

11

S1_IOWR#

45

S1_A8

12

S1_A17

46

S1_A13

13

S1_A18

47

S1_A14

14

S1_A19

48

S1_WE#

15

S1_A20

49

S1_RDY#

16

S1_A21

50
17
51
18
52

S1_A16

19

S1_A22

53

S1_A15

20

S1_A23

54

S1_A12

21

S1_A24

55

S1_A7

22

S1_A25

56

S1_A6

23

S1_VS2

57

S1_A5

24

S1_RST

58

S1_A4

25

S1_WAIT#

59

S1_A3

26

S1_INPACK#

60

S1_A2

27

S1_REG#

61

S1_A1

28

S1_BVD2

62

S1_A0

29

S1_BVD1

63

S1_D0

30

S1_D8

64

S1_D1

31

S1_D9

65

S1_D2

32

S1_D10

66

S1_WP

33

S1_CD2#

67
34
68

+VCC_SM/XD

3
5

12

2

PCMCIA Socket
LA-2931

0.3

5

4

3

2

1

PCI_AD0
PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD6
PCI_AD7
PCI_AD8
PCI_AD9
PCI_AD10
PCI_AD11
PCI_AD12
PCI_AD13
PCI_AD14
PCI_AD15
PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20
PCI_AD21
PCI_AD22
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30
PCI_AD31

5

PCI_AD[0..31]

104
103
102

98
97
96
95
93
90
89
87
86
85
83
82
79
59
58
57
55
53
50
49
47
43
42
40
39
37
36
34
33

92
77
60
44

46
76

61
63
67
68
69

70
75

30
29

25
31
27
28

65

4

17

128

21
38
51
66
81

91
101
119

35

52

80
100

U63

AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31

PCI I/F

C/BE#0
C/BE#1
C/BE#2
C/BE#3

IDSEL
PAR

FRAME#
IRDY#
TRDY#
DEVSEL#
STOP#

PERR#
SERR#

REQ#
GNT#

INTA#
PME#
RST#
CLK

CLKRUN#

GND/VSS
GND/VSS
GND/VSS

GND/VSSPST
GND/VSSPST
GND/VSSPST
GND/VSSPST
GND/VSSPST
GND/VSSPST
GND/VSSPST
GND/VSSPST

GND
GND
GND
GND

RTL8100CL_LQFP128

AVDD25/HSDAC-

108

EEDO

109

AUX/EEDI

111

EESK

106

EECS

117

LED0

115

LED1

114

LED2

113

NC/LED3

NC/MDI2+

NC/MDI2-

NC/MDI3+

NC/MDI3-

LWAKE

ISOLATE#

RTSET

NC/M66EN

NC/HV

NC/HG
NC/LG2
NC/LV2

NC/VSS
NC/VSS

NC/GND
NC/GND
NC/GND
NC/GND
NC/GND
NC/GND

CTRL25

VDD33

VDD33

VDD33

VDD33

VDD33

VDD33

VDD33

NC/AVDDL

NC/VDD18
NC/VDD18
NC/VDD18
NC/VDD18
NC/VDD18

1
2
5
6

14
15
18
19

121

X1

122

X2

105
23
127
72
74

88
10

120
11

123
124
126

9
13

22
48
62
73
112
118

8
125
26

41
56
71
84
94
107

3
7
20
16

32
54
78
99

24
45
64
110
116

12

TXD+/MDI0+

TXD-/MDI0-

RXIN+/MDI1+

RXIN-/MDI1-

NC/SMBCLK

NC/SMBDATA

NC/AVDDH

NC/HSDAC+

LAN I/F

RTT3/CRTL18

AVDD33/AVDDL
AVDD33/AVDDL
AVDD33/AVDDL

VDD25/VDD18
VDD25/VDD18
VDD25/VDD18
VDD25/VDD18

Power

R837

LAN_EEDO
LAN_EEDI
LAN_EECLK
LAN_EECS

L_LAN_ACTIVITY#
LINK_100#

1 2

R840 0_0402_5%

LINK_1000#

1 2

TXD+/MDI0+
TXD-/MDI0­RXIN+/MDI1+
RXIN-/MDI1-

R845 1K_0402_5%
R847 15K_0402_5%
R848 5.6K_0603_1%

R852 0_0402_5%

R841 0_0402_5%

LAN_X1
LAN_X2

1 2
1 2
1 2

R8 5.6K for 8100CL

2.49K for 8110S(B)

@

12

3.6K_0402_5%

1 2

U64

4

DO

GND

3

DI

2

SK

1

CS

AT93C46-10SI-2.7_SO8

@
@

C1094

CTRL25

08/15: modify

Y4

LAN_X2LAN_X1

25MHZ_20P

1

C1103
27P_0402_50V8J

2

CTRL25

1

C1107

0.1U_0402_16V4Z

2

1

C1112

2

0.1U_0402_16V4Z

1

C1116

0.1U_0402_16V4Z

2

0.1U_0402_16V4Z

2

C1121

@

1

+V_12P

1

C1126

0.1U_0402_16V4Z

2

4

0.1U_0402_16V4Z

R863

1

0.1U_0402_16V4Z

2

0.1U_0402_16V4Z

1

C1113

2

0.1U_0402_16V4Z

1

0.1U_0402_16V4Z
C1117

2

2

C1122

@

1

1 2

0_0402_5%

5
6

NC

7

NC

8

VCC

1U_0603_10V4Z

+3VS

1

2

C1108

1

C1114

2

1

C1118

0.1U_0402_16V4Z

2

0.1U_0402_16V4Z

2

C1123

@

1

+2.5V_LAN

+3VALW

1

2

+3VALW
+3VALW

12

2

4.7U_0805_10V4Z

C1104
27P_0402_50V8J

1

2

1

2

1

2

2

1

0.1U_0402_16V4Z

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C1092

0.1U_0402_16V4Z

+3VALW

P/N: SB1103600T3

31

Q52
2SA1036K_SOT23

+2.5V_LAN

C1097

C1109

0.1U_0402_16V4Z

+AVDDL

0.1U_0402_16V4Z

C1115

+DVDD

0.1U_0402_16V4Z

C1119

2

1

C1125

0.1U_0402_16V4Z@

C1124

@

Issued Date

1

2

1

C1110

0.1U_0402_16V4Z

2

R857 0_0805_5%

1 2

R862 0_0805_5%

1 2

T1

TXD+/MDI0+
TXD-/MDI0-

C1096 0.1U_0402_16V4Z

1 2

RXIN+/MDI1+
RXIN-/MDI1-

TD-8TX-

7

TD+

6

CT

3

CT

2

RD-

1

RD+

NS0013_16P

TX+

RX+

CT

CT

RX-

Location

R848

+3VALW

1

C1111

0.1U_0402_16V4Z

2

+3VALW

+2.5V_LAN

2005/03/01 2005/04/06

3

Compal Secret Data

Deciphered Date

MDO0+

9

MDO0-

10

MCT0

11

MCT1

14

MDO1+

15

MDO1-

16

U4 10/100 only,

8110SBL(10/100/1000 LAN)8100CL(10/100 LAN)

2.49K5.6K

MOLEX_53398-0290

CONN@

R835

75_0402_5%

R836

75_0402_5%

+3VALW

+3VALW

JP23

1
2

2

RJ45_GND

12

12

MOD_RING

1 2

1 2

R849

49.9_0402_1%

TXD+/MDI0+

TXD-/MDI0-

RXIN+/MDI1+

RXIN-/MDI1-

near U1

R90

300_0603_5%

LINK_100#

R133

300_0603_5%

L22 0_0603_5%

1 2

L23 0_0603_5%

1 2

Title

Size Document Number Rev

Custom

Date: Sheet

R851

49.9_0402_1%

R854

49.9_0402_1%

R855

49.9_0402_1%

LAN_LED_ACTIVE
L_LAN_ACTIVITY#

MDO1­MDO1+
MDO0­MDO0+

LAN_LED_LINK

RJ11_RING

RJ11_TIPMOD_TIP

C64

1 2

1000P_1206_2KV7K

Realtek 8100CL/RJ45
LA-2931

C1099

12
12

12
12

12

0.01U_0402_16V7K

C1102

12

0.01U_0402_16V7K

JP19

1

Yellow LED+

2

Yellow LED-

5

RX1-

8

RX1+

9

TX1-

10

TX1+

3

RX2-

4

RX2+

6

TX2-

7

TX2+

12

Green LED-

11

Green LED+

RJ45 / LED

13

RJ11_1

14

RJ11_2

TYCO_1770365-1 CONN@

1

C62

0.1U_0402_16V4Z

2

1

RJ11

LANGNDRJ45_GND

1

C67

4.7U_0805_10V4Z

2

26 48Thursday, August 18, 2005

SGND1
SGND2

of

15
16

0.3

PCI_AD[0..31]<18,22,24,27,31>

D D

C C

PCI_CBE#0<18,24,27,31>
PCI_CBE#1<18,24,27,31>
PCI_CBE#2<18,24,27,31>
PCI_CBE#3<18,24,27,31>

PCI_AD22 LAN_IDSEL

B B

12

@

1

@

A A

2

PCI_PAR<18,24,27,31>

PCI_FRAME#<18,24,27,31>

PCI_IRDY#<18,24,27,31>

PCI_TRDY#<18,24,27,31>

PCI_DEVSEL#<18,24,27,31>

PCI_STOP#<18,24,27,31>

PCI_PERR#<18,24,27,31>
PCI_SERR#<18,24,31>

PCI_REQ#3<18>

PCI_GNT#3<18>

PCI_PIRQG#<18>

LAN_PME#<33>

PCI_RST#<18,24,27,31,33>

CLK_PCI_LAN<18>
PCI_CLKRUN#<18,32>

CLK_PCI_LAN

R861

10_0402_5%

C1120
10P_0402_50V8K

1 2

R853 100_0402_5%

5

Analog Pin

VT6308S

Pin

74
75
76
77
78

D D

C C

B B

VT6311S

XTPB1M

NC
XTPB1P NC
XTPA1M

NC

NC

XTPA1P

NC

XTPBIAS1

IDSEL:PCI_AD16

PCI_AD16 1394_IDSEL

1 2

100_0402_5%

R533

U37

PCI_AD[0..31]<18,22,24,26,31>

PCI_CBE#3<18,24,26,31>
PCI_CBE#2<18,24,26,31>
PCI_CBE#1<18,24,26,31>
PCI_CBE#0<18,24,26,31>
PCI_STOP#<18,24,26,31>
PCI_PERR#<18,24,26,31>

PCI_PAR<18,24,26,31>

PCI_PIRQE#<18,24>

PCI_RST#<18,24,26,31,33>

CLK_PCI_1394<18,22>

PCI_GNT#0<18>
PCI_REQ#0<18>

1394_PME#<33>
PCI_IRDY#<18,24,26,31>
PCI_TRDY#<18,24,26,31>

PCI_DEVSEL#<18,24,26,31>

PCI_FRAME#<18,24,26,31>

PCI_AD[0..31]

PCI_AD31
PCI_AD30
PCI_AD29
PCI_AD28
PCI_AD27
PCI_AD26
PCI_AD25
PCI_AD24
PCI_AD23
PCI_AD22
PCI_AD21
PCI_AD20
PCI_AD19
PCI_AD18
PCI_AD17
PCI_AD16
PCI_AD15
PCI_AD14
PCI_AD13
PCI_AD12
PCI_AD11
PCI_AD10

PCI_AD9
PCI_AD8
PCI_AD7
PCI_AD6
PCI_AD5
PCI_AD4
PCI_AD3
PCI_AD2
PCI_AD1

PCI_AD0
PCI_CBE#3
PCI_CBE#2
PCI_CBE#1
PCI_CBE#0
PCI_STOP#
PCI_PERR#
PCI_PAR
PCI_PIRQE#
PCI_RST#
CLK_PCI_1394
PCI_GNT#0
PCI_REQ#0
1394_IDSEL
1394_PME#
PCI_IRDY#
PCI_TRDY#
PCI_DEVSEL#

PCI_FRAME#

94

AD31

95

AD30

96

AD29

97

AD28

98

AD27

101

AD26

102

AD25

103

AD24

106

AD23

107

AD22

109

AD21

113

AD20

114

AD19

115

AD18

116

AD17

117

AD16

2

AD15

3

AD14

4

AD13

7

AD12

8

AD11

9

AD10

10

AD9

11

AD8

14

AD7

15

AD6

16

AD5

18

AD4

19

AD3

20

AD2

24

AD1

25

AD0

104

CBE3#

119

CBE2#

1

CBE1#

12

CBE0#

125

STOP#

127

PERR#

128

PAR

88

INTA#

89

PCIRST#

90

PCICLK

92

GNT#

93

REQ#

105

IDSEL

34

PME#

121

IRDY#

123

TRDY#

124

DEVSEL#

120

FRAME#

PCI I/F

4

+2.5VS_1394

+3VS

111

VDD446VDD330VDD221VDD1

VCC699VCC536VCC417VCC35VCC2

VT6311S

GNDATX166GNDARX165GNDATX280GNDARX279GND19

GND18

GND17

GND16

GND1591GND1061GND956GND847GND738GND633GND531GND423GND322GND26GND113GND0

118

112

108

100

122

110

VCC1

EEPROM

59

PVA587PVA486PVA373PVA272PVA162PVA0

SDA/EEDI

SCL/EECK

PHYRST#

others

REG_OUT

OSCILLATOR

PHY PORT0

XTPBIAS0

PHY PORT1

XTPBIAS1

1

C15

2

0.1U_0402_16V4Z

26

EECS

27

EEDO

28
29

55
81

BJT_CTL

43

I2CEN

32

PWRDET

84

REG_FB

85
60

XCPS

63

XREXT

57

XI

58

XO

67

XTPB0M

68

XTPB0P

69

XTPA0M

70

XTPA0P

71
74

XTPB1M

75

XTPB1P

76

XTPA1M

77

XTPA1P

78
83

NC17

82

NC16

64

NC15

54

NC14

53

NC13

52

NC12

51

NC11

50

NC10

49

NC9

48

NC8

45

NC7

44

NC6

42

NC5

41

NC4

40

NC3

39

NC2

37

NC1

35

NC0

VT6311S_LQFP128

126

+1394_PLLVDD

1

2

0.1U_0402_16V4Z

R37 1K_0402_5%
R36

0.01U_0402_16V7K

1

C12

C7

2

0.1U_0402_16V4Z

@

R548 4.7K_0402_5%

1 2

EEDI
EECK

I2CEEN

REG_FB
REG_OUT

12
12

6.19K_0603_1%

1394_X1

1394_X0

XTPB0M
XTPB0P
XTPA0M
XTPA0P
XTPBIAS0

1

2

1 2
1 2

1394 CHIP

VT6301S

VT6311S

3

L34
BLM21A601SPT_0805

1 2

1

C568

C569

4.7U_0805_10V4Z

2

+3VS

+3VS

R35 4.7K_0402_5%6311@
R33 4.7K_0402_5%

0.1U_0402_16V4Z

24.576MHz_16P_3XG-24576-43E1

VCC/PWRDET
Enable(R33)

C2

6301@

+3VS

31

E

Q1

2

B

2SB1197K_SOT23

C

6311@

C575 10P_0402_50V8J

C576

0 ohm

4.7K ohm

+3VS

1

1

1U_0402_6.3V4Z

C34

2

2

+2.5VS_1394

1 2

X2

1 2

10P_0402_50V8J

1 2

VCC/PWRDET
Enable(C2)

ON

REMOVE ON

I2CEEN

U2

1

A0

2

A1

3

A2

4

GND

AT24C02N-10SI-2.7_SO8

EECK and EEDI is pull high internal
External pull high circuit is unnecessary

+3VS

6301@

1 2

0_0603_5%

R38

XTPA0M
XTPA0P

XTPB0M
XTPB0P

Table 1

VT6311S VDD
Power

Internal Regulator REMOVE
External BJT

BJT CTL
Enable(R35,Q1)

REMOVE

2

R554

12

4.7K_0402_5%

8

VCC

7

WP

EECK

6

SCL

EEDI

5

SDA

R555

2

3

WCM2012F2S-900T04_0805@

2

3

WCM2012F2S-900T04_0805@

BJT CTL
Enable(R35)

ON

VCC/VDD POWER

R38 must mount.
R39 doesn't mount.

R38 don't mount.
R39 must mount.

+3VS

510_0402_5%

1 2

XTPBIAS0
XTPA0P
XTPA0M
XTPB0P
XTPB0M

1 2

R1399 0_0402_5%

2

3

1 2

R1400 0_0402_5%

1 2

R1401 0_0402_5%

2

3

1 2

R1402 0_0402_5%

See Table 2S e e Table 1

L100

1

1

4

4

L101

1

1

4

4

VDD POWER

(Q1)

REMOVE
ON

XREXT (R36)

6.34K 1%

6.20K 1%

12

R217

54.9_0402_1%

12

R220

54.9_0402_1%

1

C271
270P_0402_50V7K

2

XTPA0M_1
XTPA0P_1

XTPB0M_1
XTPB0P_1

Table 2

Pin

81

84

85

32
36
46
21
111
30

12

R218

54.9_0402_1%

12

R225

54.9_0402_1%

12

R221

4.99K_0402_1%

XTPA0P_1
XTPA0M_1
XTPB0P_1
XTPB0M_1

Power Pin

VT6301S

NC
NC
NC
VCC(+3.3V)
PVD(+3.3V)

PVD(+3.3V)
VCC(+3.3V)
VCC(+3.3V)
VCC(+3.3V)

1

JP30

4
3
2
1

VT6311S

BJT_CTL
REG_FB
REG_OUT
PWRDET
VCC(+3.3V)

VDD(+2.5V)
VDD(+2.5V)
VDD(+2.5V)
VDD(+2.5V)

1

C266

2

0.33U_0603_16V4Z

XTPA0P
XTPA0M
XTPB0P
XTPB0M

4
3

GND15GND26GND37GND4

2
1

SUYIN_020204FR004S506ZLCONN@

8

PHY Differential Pin

NC

74

+3VS+2.5VS_1394

1

C31

C26

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

C32

2

1

2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2005/05/09 2006/03/11

3

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

0.1U_0402_16V4Z

1

C22

C23

2

0.1U_0402_16V4Z

1

C18

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

2

C20

C19

2

0.1U_0402_16V4Z

1

2

A A

0.1U_0402_16V4Z

C17

5

1

C24

2

0.1U_0402_16V4Z

4

0.1U_0402_16V4Z

1

2

NC

75

NC

76

NC

77

78

NC

VIA 1394 VT6311S

LA-2931

NC
NC
NC
NC
NC

0.3

27 48Thursday, August 18, 2005

1

of

5

4

3

2

1

+VDDA

12

R865
10K_0402_1%

C1129

12

12

D D

C C

B B

BEEP#<33>

C1127

0.1U_0402_10V6K@

PCM_SPK#<24>

C100

0.1U_0402_10V6K@

SB_SPKR<19>

1U_0603_10V4Z

C1128

1

1U_0603_10V4Z

2

1

1U_0603_10V4Z

2

1U_0603_10V4Z

+AUD_VREF

C1137

CD_AGND<23>

1

2

12

C1135

12

C1136

12

10mil

R866

1 2

560_0402_5%

R871

1 2

560_0402_5%

R873

1 2

560_0402_5%

10K_0402_5% @

1

C1138

0.1U_0402_16V4Z

2

R875

R891

1U_0603_10V4Z

R868
10K_0402_1%

1 2

R103 20K_0402_5%

1

C

Q54

2

B

E

2SC2411K_SOT23

3

12

D34

RB751V_SOD323

2 1

1 2

R872 0_0603_5%

1 2

R874 0_0603_5%

1 2

R876 0_0603_5%

GND GNDA

INT_CD_L<23>

INT_CD_R<23>

CD_GNACD_AGND

12

2.4K_0402_5%

12

R893

2.4K_0402_5%

C1134 1U_0603_10V4Z

MONO_IN1 MONO_IN

R879 4.7K_0402_5%
R881 4.7K_0402_5%
R882 4.7K_0402_5%
R884 4.7K_0402_5%

12

R870

1 2

10K_0402_5%

+VDDA

12
12
12
12

AUD_MIC1<29>

NBA_PLUG_MP<29>
NBA_PLUG<29>

SPDIFO<29>

10U_0805_10V4Z

L74

1 2

FBM-L10-160808-301-T_0603

C1141

10U_0805_10V4Z

CD_R_L

C1151 1U_0402_6.3V4Z

CD_R_R

AUD_MIC1 C_AUD_MIC1

AC97_RST#<19,30>
AC97_SYNC<19,30>
AC97_SDOUT<19,22,30>

EAPD<33>

1 2

C1152 1U_0402_6.3V4Z

1 2

C1153 1U_0603_10V4Z

1 2
1 2

C612 1U_0603_10V4Z

+3VS

+5VS +5VAMP

L72

1 2

KC FBM-L11-201209-221LMAT_0805

L73

1 2

KC FBM-L11-201209-221LMAT_0805

1

C1131

2

0.1U_0402_16V4Z

1

1

C1142

2

R878 0_0402_5%

NBA_PLUG

LINE_IN_L<29>
LINE_IN_R<29>

R889 47K_0402_5%@

1 2

R890 0_0402_5%

1 2

1

2

2

0.1U_0402_16V4Z

1 2

C1143

MONO_IN

07/16

1 2

R1394 0_0603_5%

SPDIFO

12

R1156
1K_0402_5%

CD_RC_L
CD_RC_R
CD_GNDACD_GNA

10U_1206_16V4Z

U75

14
15
17
16
23
24
18
20
19
21
22

13
11
10

5

12
42

47
48

4
7

60mil

1

C1132

2

+AVDD_AC97

38

43

AVDD125AVDD2
AUX_IN_L
AUX_IN_R
JS0
JS1
LINE_IN_L
LINE_IN_R
CD_IN_L
CD_IN_R
CD_GND_REF
MIC1
MIC2

PHONE
RESET#
SYNC
SDATA_OUT

NC
NC

EAPD
SPDIF_OUT
DVSS1

DVSS2

AD1888AJCP-REEL_LFCSP48

4
2

8

AVDD434AVDD3

LINE_OUT_L

LINE_OUT_R

MONO_OUT

SURR/HP_OUT_L

SUR/HP_OUT_R

VREFOUT_MIC

CENTER_OUT

U66

SI9182DH-AD_MSOP8

BIT_CLK

SDATA_IN

XLT_OUT

LFE_OUT

VIN

SENSE or ADJ

DELAY
ERROR7CNOISE
SD

+VDDC

1

C1139

0.1U_0402_16V4Z

9

2

DVDD11DVDD2

35
36
37
39
41

6
8
2

XTL_IN

3

29

AFLT1

30

AFLT2

28
27

VREF

31
32

45

ID0#

46

ID1#

26

AVSS1

40

AVSS2

44

AVSS3

33

AVSS4

28.7K for Module Design (VDDA = 4.702)

40mil

5

VOUT

6
1
3

GND

R877 0_0805_5%

1 2

1

C1140
10U_0805_10V4Z

2

1000P_0402_50V7K

C1150

C1337 270P_0402_50V7K

1 2

C1338 270P_0402_50V7K

1 2

R1154 1K_0402_5%
R1155 1K_0402_5%

1

C1133

2

0.1U_0402_16V4Z

+3VS

C1144

27P_0402_50V8J

1 2

250_BIT_CLK AC97_BITCLK

250_SDIN AC97_SDIN0

1

2

+AUD_VREF

12
12

(output = 250 mA)

R867
150K_0603_1%

1 2
12

R869
51K_0603_1%

1

1

C1145

2

2

C1147 4.7U_0805_10V4Z
C1149 4.7U_0805_10V4Z

1000P_0402_50V7K

R880 22_0402_5%

1 2

R883 22_0402_5%

1 2

1 2

R885 0_0402_5%

C1156
22P_0402_50V8J

@

1

C1158

2

0.1U_0402_16V4Z

AC97 Codec

1

C1130
10U_0805_10V4Z

2

LINE_OUTL250_LINE_OUTL

1 2

LINE_OUTR250_LINE_OUTR

1 2

CLK_14M_CODEC250_XTL_IN

+VDDA

4.85V

LINE_OUTL <29>
LINE_OUTR <29>

AC97_BITCLK <19,30>
AC97_SDIN0 <19>

CLK_14M_CODEC <15>

+AVDD_AC97

R888
1M_0402_5%

@

1 2
1

C1159

2

1U_0603_10V4Z

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2005/03/01 2005/04/06

3

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

AC97 Codec AD1888
LA-2931

28 48Thursday, August 18, 2005

1

0.3

of

A

B

C

D

E

07/07/'05

1 1

C648 100P_0402_25V8K

R348 33K_0402_5%

1 2

C649 100P_0402_25V8K

R347 33K_0402_5%

1 2

SPKR+RIN

0.1U_0402_16V4Z

SPKL+LIN

07/25/'05

1 2
1 2

+5VAMP

R316

1 2

RIGHT_2
LEFT_2

R314100K_0402_5%

12

12

R1375
100K_0402_5%

R346 10K_0402_5%

1 2

R345 10K_0402_5%

1 2

AMP_MUTE<33>

100K_0402_5%

NBA_PLUG_MP

NBA_PLUG

Q37

13

2N7002_SOT23

D

2

G

S

R313

+5VAMP

LINE_OUTR
LINE_OUTL

+5VAMP

C644 2.2U_0603_6.3V6K
C645 2.2U_0603_6.3V6K

NBA_PLUG<28>

10K_0402_5%

NBA_PLUG#

LINE_OUTR<28>

LINE_OUTL<28>

2 2

3 3

C363

NBA_PLUG

12

+5VAMP

1

2

RIN
LIN

AMP_MUTE

1

C621

4.7U_0805_10V4Z

2

W=40mil

1

C603

4.7U_0805_10V4Z

2

16

9
2

7

12
14

1

U41

RVDD

SHUTDOWN

LVDD

ROUT+
RIN
LIN

MUTE
SE/BTL#
RBYPASS
LBYPASS8GND

APA2066KAI-TRL_SOP16

SPKL+

SPKR+

LOUT+
ROUT­LOUT-

GND
GND

C608
C622

R638

1 2

1

1K_0402_5%

C695

0.1U_0402_16V4Z

2

10

SPKR+

3

SPKL+

6

SPKR-

15

SPKL-

11
4

5
13

+

INTSPK_L1-2 INTSPK_L1-3

1 2

150U_4A_6.3VM

+

INTSPK_R1-2 INTSPK_R1-3

1 2

150U_4A_6.3VM

EC_MUTE

L43 FBM-11-160808-700T_0603

1 2

L44 FBM-11-160808-700T_0603

1 2

L45 FBM-11-160808-700T_0603

1 2

L46 FBM-11-160808-700T_0603

1 2

47_0402_5%

1 2

R591

1 2

R604

47_0402_5%

R589

1K_0402_5%@

EC_MUTE <33>

12

12

FBM-11-160808-700T_0603

1 2
1 2

FBM-11-160808-700T_0603

R607
1K_0402_5%

@

Docking MIC

L35

L38

330P_0402_50V7K

SPKR+O
SPKL+O
SPKR-O
SPKL-O

INTSPK_L1-4
INTSPK_R1-4

C379

Speaker Conn.

SPKR+O
SPKR-O
SPKL+O
SPKL-O

HeadPhone JACK

C382
330P_0402_50V7K

NBA_PLUG#

SPDIFO<28>

+5VSPDIF

JP9

4

4

3

3

2

2

1

1

ACES_85205-0400

CONN@

JP40

1
2
6
3

5
4

7
8

10

9

FOX_2F11381-SJ5-TR

CONN@

NBA_PLUG_MP<28>

Close to U75

C1661

1 2

1U_0402_6.3V4Z
C1662

1 2

1U_0402_6.3V4Z

3

INT_MIC1

2

1

D40

LINE_IN_R<28>

PSOT24C-LF-T7_SOT23 @

LINE_IN_L<28>

7/14

JP10

INT_MIC1

4 4

1
2

MOLEX_53398-0290

CONN@

NBA_PLUG#

+5VSPDIF

+5VS

S

G

Q38

2

D

1 3

20mil

SI2301BDS_SOT23

7.3

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

R1390 6.8K_0402_5%@
R1391 6.8K_0402_5%@
R1392 6.8K_0402_5%

R1393 6.8K_0402_5%

2005/03/01 2005/04/06

C

12
12
12

12

AUD_MIC1<28>

Compal Secret Data

Deciphered Date

LINE_IN_R-1

LINE_IN_L-1

INT_MIC1
AUD_MIC1

1 2

L41
FBM-11-160808-700T_0603

220P_0402_50V7K

D

+AUD_VREF

12

R350

2.2K_0402_5%

1

C385

2

Title

Size Document Number Rev

Custom

Date: Sheet

NBA_PLUG_MP

12

R351

2.2K_0402_5%@

1

C386
220P_0402_50V7K

2

5

LINE_IN_R-1
LINE_IN_L-1

4
3

6
2
1

AMP & Audio Jack
LA-2931

E

MIC JACK

JP41

PHONEJACK

CONN@

29 48Thursday, August 18, 2005

of

0.3

MDC CONN.

JP47

1

GND1

AC97_SDOUT<19,22,28>
AC97_SYNC<19,28>

AC97_SDIN1<19>
AC97_RST#<19,28>

1 2

R896 22_0402_5%

AC97_SYNC
AC97_SDIN1_R

3

IAC_SDATA_OUT

5

GND2

7

IAC_SYNC

9

IAC_SDATA_IN

11

IAC_RESET#

IAC_BITCLK

RES0
RES1

3.3V
GND3
GND4

2
4
6
8
10
12

+3VALW

AC97_BITCLK_R

+3VALW

1

C1164

1U_0805_25V4Z

2

1 2

R897 22_0402_5%

AC97_BITCLK <19,28>

KSO8

C215 100P_0402_25V8K

KSI3
KSO9
KSI2
KSI1
KSO10
KSO11
KSI0
KSO12
KSO13
KSO14
KSO15

C220 100P_0402_25V8K

C222 100P_0402_25V8K

C224 100P_0402_25V8K

C227 100P_0402_25V8K

C233 100P_0402_25V8K

C235 100P_0402_25V8K

C237 100P_0402_25V8K

C239 100P_0402_25V8K

C241 100P_0402_25V8K

C242 100P_0402_25V8K

INT_KBD CONN.

(Right)

(Left)

KSO15
KSO14
KSO13
KSO12
KSI0
KSO11
KSO10
KSI1
KSI2
KSO9
KSI3
KSO8
KSO7
KSO6
KSO5
KSO4
KSO3
KSI4
KSO2
KSO1
KSO0
KSI5
KSI6
KSI7

JP4

24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

ACES_85201-2405

CONN@

KSI7

C238 100P_0402_25V8K

KSI6

C236 100P_0402_25V8KC217 100P_0402_25V8K

KSI5

C234 100P_0402_25V8K

KSO0

C232 100P_0402_25V8K

KSO1

C226 100P_0402_25V8K

KSO2

C223 100P_0402_25V8K

KSI4

C221 100P_0402_25V8K

KSO3

C218 100P_0402_25V8K

KSO4

C216 100P_0402_25V8K

KSO5

C214 100P_0402_25V8K

KSO6

C213 100P_0402_25V8K

KSO7

C212 100P_0402_25V8K

TP_CLK<33>
TP_DATA<33>

100P_0402_25V8K@

TP_CLK
TP_DATA

C1659

CONN@

(EMW80)

<>

+5VS

100P_0402_25V8K@

131314141515161617171818191920

KSI[0..7]
KSO[0..15]

TO M/B

C1660

Close to JP5

FOX_QT8A0121-4011~D

20

Connector for MDC Rev1.5

07/11/'05

KSI[0..7] <33,36>
KSO[0..15] <33>

ACES_85201-0605

6
5
4
3
2
1

JP5

CONN@

BlueTooth Interface

+3VALW

S

Q31

G

C396

1

2

2

D

1 3

1

C397

0.1U_0402_16V4Z

2

SI2301BDS_SOT23

+BT_VCC

Bluetooth Connector

ACES_87213-0800

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

JP1

CONN@

BT_ON#<33>

USB20P5+<19>

USB20P5-<19>

WLAN_BT_DATA<31>
WLAN_BT_CLK<31>

USB20P5+
USB20P5-

+BT_VCC

10U_0805_10V4Z

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2005/03/01 2005/04/06

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom
Date: Sheet

MDA/BT/KBD/TP Conn
LA-2931

30 48Thursday, August 18, 2005

of

0.3

A

1 1

B

PCI_AD[0..31]

C

PCI_AD[0..31] <18,22,24,26,27>

D

E

MINI_PCI SOCKET

TIP

LAN RESERVED

D10

RB751V_SOD323

WL_ON
PCI_PIRQF#

CLK_PCI_MINI

PCI_REQ#1 PCI_GNT#1
PCI_AD31

PCI_AD29
PCI_AD27

PCI_AD25
WLAN_BT_DATA
PCI_CBE#3
PCI_AD23

PCI_AD21
PCI_AD19

PCI_AD17
PCI_CBE#2
PCI_IRDY#

PCI_SERR#
PCI_PERR#

PCI_CBE#1
PCI_AD14

PCI_AD12
PCI_AD10

PCI_AD8
PCI_AD7

PCI_AD5
PCI_AD3
PCI_AD1

L30

W=30mils W=20mils

0_0603_5%

+5VS_MINIPCI1

0603

PCI_PIRQF#<18>

W= 40mils

CLK_PCI_MINI<18,22>

PCI_REQ#1<18>

WLAN_BT_DATA<30>

PCI_CBE#3<18,24,26,27>

WL_ON<33>

+3VS_MINIPCI1

+3VS

2 2

CLK_PCI_MINI

12

R544

33_0402_5%@

L29

1 2

0_0603_5%

1

C566

10P_0402_50V8J@

2

3 3

PM_CLKRUN#<33>

+5VS

PCI_CBE#2<18,24,26,27>

PCI_IRDY#<18,24,26,27>

PCI_SERR#<18,24,26>

PCI_CBE#1<18,24,26,27>

+5VS_MINIPCI1

1 2

21

?

W=30mils

JP35

1

1

3

3

5

5

7

7

9

9
111112
131314
151516
171718
191920
212122
232324
252526
272728
292930
313132
333334
353536
373738
393940
414142
434344
454546
474748
494950
515152
535354
555556
575758
595960
616162
636364
656566
676768
696970
717172
737374
757576
777778
797980
818182
838384
858586
878788
898990
919192
939394
959596
979798
9999100

101

101

103

103

105

105

107

107

109

109

111

111

113

113

115

115

117

117

119

119

121

121

123

123

QTC_C102A-040B31-4

CONN@

RING

2

2

4

4

6

6

8

8

10

102
104
106
108
110
112
114
116
118
120
122
124

LAN RESERVED

10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124

W=30mils

PCI_PIRQF#

W=40mils

PCI_RST#

WLANPME#
WLAN_BT_CLK
PCI_AD30

PCI_AD28
PCI_AD26
PCI_AD24
MINI_IDSEL1

PCI_AD22
PCI_AD20

PCI_AD18
PCI_AD16

PCI_FRAME#
PCI_TRDY#PM_CLKRUN#
PCI_STOP#

PCI_DEVSEL#
PCI_AD15

PCI_AD13
PCI_AD11

PCI_AD9
PCI_CBE#0

PCI_AD6
PCI_AD4
PCI_AD2
PCI_AD0

2

C378

0.1U_0402_16V4Z

1

PCI_RST# <18,24,26,27,33>

1 2

R281

PCI_PAR <18,24,26,27>

PCI_FRAME# <18,24,26,27>
PCI_TRDY# <18,24,26,27>
PCI_STOP# <18,24,26,27>

PCI_CBE#0 <18,24,26,27>

+3VALW

+5VS_MINIPCI1

+3VALW

PCI_GNT#1 <18>
WLANPME# <33>

WLAN_BT_CLK <30>

PCI_AD18

100_0402_5%

PCI_DEVSEL# <18,24,26,27>PCI_PERR#<18,24,26,27>

W= 40mils

IDSEL : PCI_AD18

1

C381

1000P_0402_50V7K

2

2

C355

0.1U_0402_16V4Z

1

+3VS_MINIPCI1

1 2

0_0603_5%

L26

+3VS

2

C327

0.1U_0402_16V4Z

1

2

C352

0.1U_0402_16V4Z

1

2

1

2

C345

0.1U_0402_16V4Z

1

C364

0.1U_0402_16V4Z

2

1

1

2

C334

0.1U_0402_16V4Z

+5VS_MINIPCI1

C315

10U_1206_16V4Z

2

C330

0.1U_0402_16V4Z

1

+3VS_MINIPCI1

1

C331
10U_1206_16V4Z

2

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2005/03/01 2005/04/06

C

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

D

Date: Sheet

MINI PCI
LA-2931

0.3

31 48Thursday, August 18, 2005

E

of

5

SUPER I/O SMsC FDC47N207

D D

LPC_AD0<18,33>
LPC_AD1<18,33>
LPC_AD2<18,33>
LPC_AD3<18,33>

LDRQ0#<18,33>

LPC_FRAME#<18,33>

PCI_CLKRUN#<18,26>

SIRQ<18,24,33>

CLK_PCI_SIO<18,22>

NB_RST#<13,18,23>

LPCPD#
SIO_PME#

R911
10_0402_5%@

C1173
10P_0402_25V8K

@

CLK_14M_SIO<15>

SIO_PME#<33>

+3VS

C C

1 2

R904 10K_0402_5%

1 2

R905 10K_0402_5%

CLK_PCI_SIO CLK_14M_SIO

12

R910
10_0402_5%@

1

C1172
18P_0402_50V8K

@

2

12

1

2

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3

LDRQ0#
LPC_FRAME#
PCI_CLKRUN#
SIRQ
CLK_PCI_SIO
NB_RST#
CLK_14M_SIO
LPCPD#
SIO_PME#

4

U69

64

LAD0

2

LAD1

4

LAD2

7

LAD3

10

LPC_CLK_33

12

LDRQ1#

24

LDRQ0#

14

LFRAME#

16

CLKRUN#

19

SERIRQ

21

PCI_CLK

22

PCIRST#

23

SIO_14M

25

LPCPD#

47

IO_PME#

63

DLAD0

1

DLAD1

3

DLAD2

6

DLAD3

9

DLPC_CLK_33

11

DLDRQ1#

13

DLFRAME#

15

DCLKRUN#

18

DSER_IRQ

26

DSIO_14M

LPC47N207-JN_STQFP64

3.3V53.3V173.3V313.3V423.3V

LPC I/F

DLPC I/F

48

60

VTR

GPIO12/IO_SMI#

GPIO13/IRQIN1
GPIO14/IRQIN2

RTS1#/SYSOPT0
DTR1#/SYSOPT1

SERIAL I/F

IRMODE/IRRX3

IR GPIO

GND08GND120GND229GND337GND445GND5

1

C1169

0.1U_0402_16V4Z

2

1

C1168

4.7U_0805_10V4Z

2

27

GPIO10

28

GPIO11

30
32
33
34

GPIO15

35

GPIO16

36

GPIO17

38

GPIO30

39

GPIO31

40

GPIO32

41

GPIO33

43

GPIO34

44

GPIO35

46

GPIO36

61

GPIO37

52

RXD1

53

TXD1

54

DRSR1#

55
56

CTS1#

57
58

RI1#

59

DCD1#

49

IRTX2

50

IRRX2

51

62

1

C1171

0.1U_0402_16V4Z

2

1

C1170

0.1U_0402_16V4Z

2

R903 10K_0402_5%

1 2

DCD0#
RI0#
CTS0#
DSR0#

RXD0
TXD0
DSR0#
RTS0#
CTS0#
DTR0#
RI0#
DCD0#

IRTXOUT
IRRX
IRMODE

IRRX

1 2

R909
1K_0402_5%

3

+3VS

@

+3VS

RP82

1 8
2 7
3 6
4 5

4.7K_8P4R_1206_5%

1 2

R906 1K_0402_5%

1 2

R907 10K_0402_5%

1 2

R908 10K_0402_5%

RTS0

TXD0#

DTR0

R912

33_0402_5%@

1 2

R913

33_0402_5%@

1 2

R914

33_0402_5%@

1 2

Base I/O Address

0 = 02Eh

*

1 = 04Eh

DCD0
DSR0
RXD0#
RTS0F
TXD0F#
CTS0
DTR0F
RI0

2

CP1

4 5
3
2

4 5
3
2

6
7
81

@

270P_1206_8P4C_50V8K
CP2

6
7
81

@

270P_1206_8P4C_50V8K

1

JSIO1

1

1

6

6

2

2

7

7

3

3

8

8

4

4

9

9

5

5

12

12

13

13

10

10

11

11

FOX_DS00191-MT631-7F~D@

FIR Module

Vishay populate two 4.7 Ohm resistor
Agilent populate one 4.7 Ohm resistor

+3VS

1

C610

2

2
4
6
8

SD/MODE: SHUTDOWN MODE, HIGH ACTIVE
MODE: HIGH/LOW SPEED SELECT

R605

4.7_1206_5%

1 2
1 2

R606

4.7_1206_5%

IR1

IRED_C

SD/MODE

RXD
VCC
GND

TFDU6102-TR3_8P

IRED_A

TXD

MODE

2

+IR_ANODE

(60mil)

1
3
5
7

150U_D2_6.3VM@

IRTXOUT

C624

1 2

+

1 2

R586

0_0402_5%@

Title

Size Document Number Rev

Custom

Date: Sheet

Super IO/FIR
LA-2931

1

32 48Thursday, August 18, 2005

of

0.3

U70

C1+

C1­C2+

C2­TIN1
TIN2
TIN3
ROUT1
ROUT2
ROUT3
ROUT4
ROUT5
ROUTB2

FORCEON
FORCEOFF#

MAX3243CAI_SSOP28@

+5VS

1

C1174

0.1U_0402_16V4Z@

2

26

27

V+

VCC

3

V-

9

TOUT1

10

TOUT2

11

TOUT3

4

RIN1

5

RIN2

6

RIN3

7

RIN4

8

RIN5

21

INVLD#

25

GND

4

3243V+

3243V-

0.47U_0603_16V7K@

TXD0#
RTS0
DTR0
DCD0
RI0
RXD0#
CTS0
DSR0

C1175

1 2

0.47U_0603_16V7K@

C1178

1 2

+3VS

1

2

R594
47_1206_5%

1 2
1

C600

0.1U_0402_16V4Z

2

Vishay = 47 Ohm
Agilent = 0 Ohm

C604

10U_1206_16V4Z

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2005/03/01 2005/04/06

3

10U_1206_16V4Z

IRRX IRMODE
+IR_3VS IRMODE1

Compal Secret Data

Deciphered Date

B B

C1176

0.1U_0402_16V4Z @

C1177

0.47U_0603_16V7K@

1 2

RI0#

A A

1 2

R915 0_0402_5%@

5

1 2

+5VS

SUSP#<33,34,37>

3243C1+

3243C1­3243C2+

3243C2­TXD0
RTS0#
DTR0#
DCD0#

RXD0
CTS0#
DSR0#

28

24

1

2
14
13
12
19
18
17
16
15
20

23
22

5

L75

LAN_PME#<26>
1394_PME#<27>
WLANPME#<31>

SIO_PME#<32>

KBD_DATA
KBD_CLK
TP_DATA
TP_CLK

12

R931
100K_0402_5%

12

R933

8.2K_0402_5%

LID_SW#
EN_WL#

1
2
3
4
5
6

LPC_AD0

7

LPC_AD1

8

LPC_AD2

9

LPC_AD3

10

LPC_FRAME#

11

LDRQ0#

12

PCI_RST#

13
14

CLK_PCI_SIO_DBR

15

SIRQ

16
17
18
19
20

1 2

CHB1608U800_0603

0.1U_0402_16V4Z

1 2

L76 CHB1608U800_0603

R302 0_0402_5%

1 2

R304 0_0402_5%

1 2

R303 0_0402_5%

1 2

R299 0_0402_5%@

1 2

+3VALW

RP83

1 8
2 7
3 6
4 5

10K_0804_8P4R_5%

1 2

10K_0402_5%@

1 2

10K_0402_5% @

RP84

1 8
2 7
3 6
4 5

10K_0804_8P4R_5%

R924

R925

+3VALW

AD_BID0

1

C1191

0.1U_0402_16V4Z

2

1 2

10K_0402_5%

1 2

10K_0402_5%

FOR LPC SIO DEBUG PORT

+5VS

LDRQ0# <18,32>

5

2

C1179

1

ECAGND

0.1U_0402_16V4Z

+5VS

EC_SMB_DA1
EC_SMB_CK1
EC_SMB_DA2
EC_SMB_CK2

+3VALW

R2
R3

+3VS

1

C1180
1000P_0402_50V7K

2

R923

1 2

47K_0402_5%

+3VALW

R305
10K_0402_5%

1 2

2

C1187

1

1 2

R386

22_0402_5%@

EC_PME#

EC_RST#

R1395 4.7K_0402_5%
R1396 4.7K_0402_5%
R1397 4.7K_0402_5%
R1398 4.7K_0402_5%

08/17: modify

+3VALW +EC_AVCC

D D

AMP_MUTE

C C

EC_MUTE

FSEL#
EN_BT#
FRD#

+3VALW

Ra

Rb

B B

JP49

1
2
3
4
5
6
7
8
9

10

A A

11
12
13
14
15
16
17
18
19
20

ACES_85201-2005@

+3VALW

1

C1181

2

0.1U_0402_16V4Z

LPC_AD[0..3]<18,32>

LPC_FRAME#<18,32>

KSI[0..7]<30,36>

KSO[0..15]<30>

12
12
12
12

E_MAIL_LED#<36>

PWR_LED#<36>

BATT_FULL_LED#<36>

BATT_CHGI_LED#<36>

CAPSLED#<36>

MEDIA_LED#<36>

EC_RSMRST#<19>
BKOFF#<17>
SLP_S3#<19>

EC_LID_OUT#<19>
SLP_S5#<19>

EC_SMI#<19>

EC_SWI#<19>

SUSP#<32,34,37>

R1376

10K_0402_5%@

12

CLK_PCI_SIO_DB <18,22>

4

0.1U_0402_16V4Z

1

C1182

2

1000P_0402_50V7K

EC_GA20<19>
KB_RST#<19>

SIRQ<18,24,32>

CLK_PCI_EC<18,22>

PCI_RST#<18,24,26,27,31> EN_DFAN1 <4>

EC_SCI#<19>

PM_CLKRUN#<31>

KSO[0..15]

+5VALW

KSO16<36>

CARD_LED#<24>

EC_SMB_DA2<4>
EC_SMB_CK2<4>
EC_SMB_DA1<34,42>
EC_SMB_CK1<34,42>

NUMLED#<36>

SYSON<37,44>

0.1U_0402_16V4Z

1

C1183

2

EC_GA20
KB_RST#

LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0

PCI_RST#

EC_SCI#

KSI[0..7]

KSO16

EC_SMB_DA2
EC_SMB_CK2
EC_SMB_DA1
EC_SMB_CK1

TXD

E_MAIL_LED#

PWR_LED#

BATT_FULL_LED#

BATT_CHGI_LED#

EC_SMI#
LID_SW#

EC_PME#

CRY1
CRY2

KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7

KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15

1

2

1000P_0402_50V7K

1

C1184

C1185

2

U72

1

GA20/ GPIO00/GA20

2

KBRST#/GPIO01/KBRST#

3

SERIRQ

5

LPC_FRAME# / LFRAME#

6

LPC AD3/LAD3

9

LPC AD2/LAD2

10

LPC AD1/LAD1

12

LPC AD0/LAD0

14

CLK_PCI_EC/PCICLK

15

PCIRST#

42

EC RST#/ ECRST#

24

EC SCI#/SCI#/GPIO0E

44

PM_CLKRUN#/ CLKRUN#

63

KSI0/GPIO30

64

KSI1/GPIO31

65

KSI2/GPI032

66

KSI3/GPIO33

67

KSI4/GPIO34

68

KSI5/GPI035

69

KSI6/GPIO36

70

KSI7/GPIO37

47

KSO0/GPIO20

48

KSO1/GPIO21

49

KSO2/GPIO22

50

KSO3/GPIO23

51

KSO4/GPIO24

52

KSO5/GPIO25

53

KSO6/GPIO26

54

KSO7/GPIO27

55

KSO8/GPIO28

56

KSO9/GPIO29

57

KSO10/GPIO2A

58

KSO11/GPIO2B

59

KSO12/GPIO2C

60

KSO13/GPIO2D

61

KSO14/GPIO2E

62

KSO15/GPIO2F

89

EC URXD/KSO16/GPIO48

90

EC UTXD/KSO17/GPIO49

88

EC SMD2/ GPIO47/SDA2

87

EC SMC2/GPIO46/SCL2

86

EC SMD1/GPIO44/SDA1

85

EC SMC1/GPIO44/SCL1

34

PCM_SPK#/EMAIL_LED#/ GPIO16

35

SB_SPKR/PWR_SUSP_LED#/ GPIO17

38

PWRLED#/ GPIO19

40

NUMLED#/ GPIO1A

99

BATT CHGI LED#/ E51CS#

101

BATT LOW LED#/ E51MR0

100

CAPS LED#/ E51TMR1

102

ARROW LED#/ E51 INT0

104

SYSON/GPIO56/ E51 INT1

4

EC_RSMRST#/ GPIO02

7

BKOFF#/GPIO03

8

PM SLP S3#/GPIO04

16

EC LID OUT#/GPIO06

17

PM SLP S05#/ GPIO07

18

EC SMI#/GPIO08

19

EC SWI#/GPIO09

20

LID SW#/ GPIO0A

21

SUSP#/GPIO0B

22

PBTN_OUT#/GPIO0C

23

EC PME#/GPIO0D

140

XCLKO

138

XCLKI

Host

INTERFACE

key Matrix

scan

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

+EC_AVCC

AD_BID0

VLDT_EN

BT_ON#

FAN_SPEED1

KBD_CLK

KBD_DATA

EC_MUTE

AMP_MUTE
TP_CLK

TP_DATA

EN_WL#
EN_BT#

EC_THERM#

ENABLT

EAPD

1 2

26

105

11

VCC/ EC VCC

GND

139

SM BUS

129

75

127

141

BATTEMP/AD0/GPIO38

BATT OVP/AD1/GPIO39

VCC

VCC

ADP_I/AD2/GPIO3A

AD BID0/AD3/GPIO3B

VCC / EC VCC

GND

VCC / EC VCC37VCC / EC VCC

PWR

FAN/PWM

GND

103

GND13GND28GND

AD INtput or GPI

EC_AVCC / AVCC

DAC_BRIG/DA0/GPIO3D

EN DFAN1/DA1/GPIO3D

EN DFAN2/DA3/ GPIO3F

DA output or GPO

INVT_PWM/GPIO0F/PWM1

BEEP#/GPIO10/PWM2

OUT BEEP/GPIO12/PWM3

ACOFF/GPIO18/PWM4
FAN SPEED1/GPIO14/FANFB1
FAN SPEED2/GPIO15/FANFB2

PS2 interface

Data
BUS

Address

BUS

SELIO2#/ GPIO43

SELIO#/ GPIO50

FWR#/WR#

FSEL#/SELMEM#

EC ON/ GPIO1B

AC IN/ GPIO1C

ECTHERM#/GPIO11

ONOFF/GPIO18

PCMRST#/GPIO1E

WL OFF#/GPIO1F

ALI/MH#/GPIO40

FSTCHG/GPIO41

VR ON/ GPIO42
GPIO57/GPIO57
GPIO58/GPIO58
GPIO59/GPIO59

AGND

39

77

ECAGND

2005/03/01 2005/04/06

3

71
72
73
74

76
78
79

IREF2/DA2

80

25
27
30
31
32
33

91

PSCLK1

92

PSDAT1

93

PSCLK2

94

PSDAT2

95

PSCLK3

96

PSDAT3

125

ADB0/D0

126

ADB1/D1

128

ADB2/D2

130

ADB3/ D3

131

ADB4/D4

132

ADB5/D5

133

ADB6/D6

134

ADB7/D7

111

KBA0/A0

112

KBA1/A1

113

KBA2/A2

114

KBA3/A3

115

KBA4/A4

116

KBA5/A5

117

KBA6/A6

118

KBA7/A7

119

KBA8/A8

120

KBA9/A9

121

KBA10/A10

122

KBA11/A11

123

KBA12/A12

124

KBA13/A13

110

KBA14/A14

109

KBA15/A15

108

KBA16/A16

107

KBA17/A17

106

KBA18/A18

98

KBA19/A19

84
97
135

FRD#/RD#

136
144

41
43
29
36
45
46

81
82
83
137
142
143

KB910L_LQFP144

Compal Secret Data

Deciphered Date

C1186

0.01U_0402_16V7K

ADB0
ADB1
ADB2
ADB3
ADB4
ADB5
ADB6
ADB7
KBA0
KBA1
KBA2
KBA3
KBA4
KBA5
KBA6
KBA7
KBA8

KBA9
KBA10
KBA11
KBA12
KBA13
KBA14
KBA15
KBA16
KBA17
KBA18
KBA19

2

ECAGND

BATT_TEMP <42>

BATT_OVP <41>

IDE_LED# <23>

DAC_BRIG <17>
IREF <41>

VLDT_EN <36,43>

INVT_PWM <17>
BEEP# <28>

BT_ON# <30>

ACOFF <39,41>

FAN_SPEED1 <4>

PWR_SUSP_LED# <36>

KBD_CLK <8,9>

KBD_DATA <8,9>

EC_MUTE <29>

AMP_MUTE <29>
TP_CLK <30>
TP_DATA <30>

ADB[0..7]

KBA[0..19]

EN_WL# <36>
EN_BT# <36>
FRD# <34>
FWR# <34>
FSEL# <34>

EC_ON <36>
ACIN <41>
EC_THERM# <19>
ON/OFF <36>
WL_ON_LED# <36>
WL_ON <31>PWRBTN_OUT#<19>

ENABLT <13,17>

FSTCHG <41>

VR_ON <46>

BT_ON_LED# <36>

EAPD <28>

VGATE <46>

2

ADB[0..7] <34>

KBA[0..19] <34>

1

+3VALW

KBA0
KBA1
KBA2
KBA3
KBA4
KBA5

R916 10K_0402_5%

1 2

R917 10K_0402_5%

1 2

R918 10K_0402_5%

1 2

R919 10K_0402_5%

1 2

R920 10K_0402_5%

1 2

R921 10K_0402_5%

1 2

PCI_RST#

1 2

@
@
@
@
@

R922

100K_0402_5%

EC DEBUG port

JP31

1

1

E_MAIL_LED#

2

2

TXD

3

3

4

4

ACES_85205-0400 @

SW1

1

2

MPU-101-81_4P

3

4

(ELW80)

1 2

R929 20M_0603_5%@

1

C1189

10P_0402_50V8J

Title

Size Document Number Rev

Custom

Date: Sheet

2

32.768KHZ_12.5P_1TJS125DJ2A073

1

4

IN

OUT

NC3NC

2

KB910L/LIT SW
LA-2931

LID_SW#

CLK_PCI_EC

12

R926
10_0402_5%@

1

C1188
15P_0402_50V8D@

2

Y5

1

+5VALW

2

3

1

R930

1

C1190
10P_0402_50V8J

2

D1

PSOT24C_SOT23@

CRY1

CRY2

0_0603_5%

33 48Thursday, August 18, 2005

12

of

0.3

KBA[0..19]<33>

ADB[0..7]<33>

KBA[0..19]
ADB[0..7]

KBA18
KBA16
KBA15
KBA12
KBA7
KBA6
KBA5
KBA4
KBA3
KBA2
KBA1
KBA0
ADB0
ADB1
ADB2

U42

1

NC

2

A16

3

A15

4

A12

5

A7

6

A6

7

A5

8

A4

9

A3

10

A2

11

A1

12

A0

13

DQ0

14

DQ1

15

DQ2

16

VSS

29F040/SST39VF040_PLCC

VCC
WE*

A17
A14
A13

A11
OE*

A10

CE*
DQ7
DQ6
DQ5
DQ4
DQ3

+3VALW

2

C614

0.1U_0402_16V4Z

32

FWE#

31

KBA17

30

KBA14

29

KBA13

28

KBA8

27

A8

KBA9

26

A9

KBA11

25

FRD#

24

KBA10

23

FSEL#

22

ADB7

21

ADB6

20

ADB5

19

ADB4

18

ADB3

17

1

FRD# <33>
FSEL# <33>

0.1U_0402_16V4Z

1 2

FWE#

C372

+3VALW

4

O

5

U23

2

P

I0

1

I1

G

TC7SH32FU_SSOP5

3

+3VALW

12

R335
100K_0402_5%

2

G

1 3

D

Q21
2N7002_SOT23

FWR# <33>

S

SUSP# <32,33,37>

EC_FLASH# <19>

EC_SMB_CK1<33,42>
EC_SMB_DA1<33,42>

+5VALW

C361 0.1U_0402_16V4Z

1 2

U21

8

VCC

7

WP

6

SCL

5

SDA

AT24C16AN-10SI-2.7_SO8

GND

+5VALW

12

R315
100K_0402_5%

1

A0

2

A1

3

A2

4

12

R309
100K_0402_5%

Bios Rom Chip Daughter Card

KBA16
KBA15
KBA14
KBA13
KBA12
KBA11
KBA9
KBA8
FWR#

KBA18
KBA7
KBA6
KBA5
KBA4
KBA3
KBA2
KBA1

JP2

112
334
556
778
9910
111112
131314
151516
171718
191920
212122
232324
252526
272728
292930
313132
333334
353536
373738
393940

HRS_DF23C-40DS-0.5V@

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

KBA17

KBA19
KBA10
ADB7
ADB6
ADB5
ADB4

ADB3
ADB2
ADB1
ADB0
FRD#

FSEL#
KBA0

+3VALW

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2005/03/01 2005/04/06

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom
Date: Sheet

BIOS
LA-2931

of

34 48Thursday, August 18, 2005

0.3

5

D D

4.7U_0805_10V4Z

C390

+5VALW

1

2

SYSON_R#

U26

1
2
3
4

G528_SO8

GND
IN
IN
EN#

OUT
OUT
OUT

FLG

8
7
6
5

07/06/'05

4

+USB_AS

1 2

R23 10K_0402_5%

1

C1656

0.1U_0402_16V4Z

2

OVCUR#0 <19>

3

2

470P_0402_50V7K

1

+

C338
150U_D2_6.3VM

C387

2

1

+USB_AS

1

2

07/06/'05

L97

2

USB20P0+<19>
USB20P0-<19>

2

3

3

WCM2012F2S-900T04_0805

1

1

4

4

USB20P0R-

USB20P0R-USB20P0R+

USB20P0R+

JP13

1

VCC

2

D-

3

D+

4

GND

5

GND1

6

GND2

7

GND3

8

GND4

SUYIN_020173MR004G533ZR

CONN@

(Rear)

USB20P0- USB20P0+

C C

4.7U_0805_10V4Z

SYSON#<37,45>

B B

C211

R1379

1 2

+5VALW

1

2

SYSON_R#

0_0402_5%

U16

1

GND

2

IN

3

IN

4

EN#

G528_SO8

12

R1380
0_0402_5%@

OUT
OUT
OUT

FLG

8
7
6
5

8/18:modify

R1404 0_0805_5%
R1405 0_0805_5%

12
12

1 2

R179

10K_0402_5%

1 2

R174

10K_0402_5%

C206

0.1U_0402_16V4Z

1

2

+USB_BS

1

C209

0.1U_0402_16V4Z

2

OVCUR#4 <19>

OVCUR#1 <19>

USB20P1- USB20P1+

USB20P4+ USB20P4-

07/06/'05

U1

1

AS

2

GND

3

VDD

IP4220CZ6_SOT23-6@

USB20P1+<19>
USB20P1-<19>

SDA

ALERT

SCL

6
5
4

+USB_AS

2

2

3

3

WCM2012F2S-900T04_0805

C204
150U_D2_6.3VM

L98

1

1

USB20P1R+
USB20P1R- USB20P1R+

4

4

+

07/06/'05

+USB_BS

470P_0402_50V7K

1

1

C202

2

2

USB20P1R-

12

R1406
0_0805_5%

JP24

1
2
3
4

SUYIN_020173MR004S312ZL

CONN@

(Left)

8/18:modify

U32

1

AS

2

GND

3

VDD

IP4220CZ6_SOT23-6@

SDA

ALERT

SCL

6
5
4

+USB_BS

C240
150U_D2_6.3VM

470P_0402_50V7K

1

+

C225

2

+USB_BS

1

2

L99

2

USB20P4+<19>
USB20P4-<19>

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2005/03/01 2005/04/06

3

Compal Secret Data

Deciphered Date

2

3

3

WCM2012F2S-900T04_0805

2

1

1

4

4

Title

Size Document Number Rev

Custom

Date: Sheet

07/06/'05

USB20P4R+

USB20P4R- USB20P4R+

USB20P4R-

12

R1407
0_0805_5%

USB 2.0 Conn
LA-2931

JP25

1
2
3
4

SUYIN_020173MR004S312ZL

CONN@

(Left)

8/18:modify

35 48Thursday, August 18, 2005

1

of

0.3

A

+3VALW

B

C

D

E

2

C1645

0.1U_0402_16V4Z

R1348

1 1

VLDT_EN<33,43> SB_PWRGD <19>

VLDT_EN

R1351

10K_0402_5%

470K_0402_5%

1 2

12

0.1U_0402_16V4Z

1

C1646

2

14

1

7

1

P

O2I

G

U78A

SN74LVC14APWLE_TSSOP14

08/15: modify

KSO16
KSI1

2

3

D41

PSOT24C-LF-T7_SOT23 @

1

+3VALW +3VALW +3VALW

14

P

3

O

I

G

U78B

SN74LVC14APWLE_TSSOP14

7

R1349
200K_0402_5%

4

1 2

0.47U_0603_16V7K

C1647

R1352
10_0402_5%

1 2

1

2

14

P

5

6

O

I

G

U78C

SN74LVC14APWLE_TSSOP14

7

NB_PWRGD <13>

08/15: modify

14

P

9

O

I

G

U78D

SN74LVC14APWLE_TSSOP14

7

R1350
10_0402_5%

8

1 2

note:T1 minimu m 15ms,T2 minimum 33ms/maximum 500ms,
SUSP# goes to low after SB_PWRGD goes to low for power
down.

VLDT_EN

NB_PWRGD

SB_PWRGD

T1

T2

SUSP#

3

2

1

EN_BT#
BT_ON_LED#

D42

PSOT24C-LF-T7_SOT23@

Compal Secret Data

PWR_SUSP_LED#<33>

E_MAIL_LED#<33>

CAPSLED#<33>

NUMLED#<33>

PWR_LED#<33>

BATT_FULL_LED#<33>

BATT_CHGI_LED#<33>

MEDIA_LED#<33>

WL_ON_LED#<33>

BT_ON_LED#<33>

Deciphered Date

+1.8VS

BlueTooth_BTN Wireless_BTN

SW7

1 2

PTS-042_2P

LED Indicator

LED7 HT-170UD_0805

LED1 HT-170UD_0805

LED2 HT-170UYG-DT GRN_0805

LED3 HT-170UYG-DT GRN_0805

LED5 HT-170UYG-DT GRN_0805

LED6 HT-170UYG-DT GRN_0805

LED8 HT-170UD_0805

LED4 HT-170UYG-DT GRN_0805

LED10

1

12-21UYOC/S530-A2/TR8_YEL

LED9

1

12-21UYOC/S530-A2/TR8_YEL

D

EN_BT# <33> EN_WL# <33>

PWR_SUSP_LED#D

21

E_MAIL_LED#D

21

CAPSLED#D

21

NUMLED#D

21

PWR_LED#D

21

BATT_FULL_LED#D

21

BATT_CHGI_LED#D

21

MEDIA_LED#D

21

3
2

WL_ON_LED#D

3

BT_ON_LED#D

2

Title

Size Document Number Rev

Custom

Date: Sheet

SW8

1 2

PTS-042_2P

R612 360_0402_5%

R12 360_0402_5%

R45 360_0402_5%

R58 360_0402_5%

R613 360_0402_5%

R610 360_0402_5%

R611 360_0402_5%

R85 360_0402_5%

R353 360_0402_5%

R354 360_0402_5%

12

12

12

12

12

12

12

12

12

12

PWR_OK/BTN
LA-2931

E

+5VALW

+5VS

+5VS

+5VS

+5VALW

+5VALW

+5VALW

+5VS

+5VALW

+5VALW

0.3

36 48Thursday, August 18, 2005

of

E-Mail_BTN Internet_BTN

2 2

KSO16<33> KSO16<33>

SW2
EVQPLHA15_4P

3
4

5

1
2

6

KSI3 <30,33>

SW4
EVQPLHA15_4P

3
4

5

1
2

6

KSI2 <30,33>

e/eManager_BTN Launch Manager_BTN

3
4

ON/OFF <33>
51ON# <39>

2

C389
1000P_0402_50V7K

1

SW6
EVQPLHA15_4P

5

6

1
2

12

D17
RLZ20A_LL34

2

3

1

2

3

1

2

3

1

BATT_FULL_LED#

BATT_CHGI_LED#

D43

PSOT24C-LF-T7_SOT23@

PWR_SUSP_LED#
PWR_LED#

D44

PSOT24C-LF-T7_SOT23@

WL_ON_LED#

EN_WL#

D45

PSOT24C-LF-T7_SOT23@

08/15: modify

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2005/03/01 2005/04/06

C

SW5
EVQPLHA15_4P

SW3
EVQPLHA15_4P

5

6

A

3
4

1
2

EC_ON<33>

KSO16<33> KSO16<33>

3 3

3
4

4 4

1
2

5

6

2N7002_SOT23

TOP Side

12

J5 JOPEN

12

J2 JOPEN

Bottom Side

ON/OFFBTN#

+3VALW

1 2

EC_ON

13

D

Q29

S

KSI0 <30,33> KSI1 <30,33>

+3VALW

Power Button

R358
100K_0402_5%

1 2

D16

2

R368

4.7K_0402_5%

1 2

R367
33K_0402_5%

DTC124EK_SC59

2

G

1

DAN202U_SC70

2

Q2

3

51ON#

13

B

A

B

C

D

E

SUSP#<32,33,34>

SYSON<33,44>

+1.8VS

D

S

D

S

SUSP<6>

DTC115EKA_SOT23
Q25

SYSON#<35,45>

DTC115EKA_SOT23
Q22

1 2
13

+5VS

1 2
13

R169
470_0402_5%

SUSP

2

G

Q14

2N7002_SOT23

R609

470_0402_5%

SUSP

2

G

Q41

2N7002_SOT23

SUSP

SYSON

100K

2

SYSON#

100K

2

+5VALW

100K

+5VALW

100K

R343
10K_0402_5%

1 2
13

R344
10K_0402_5%

1 2
13

D

S

+3VS

1 2
13

R156
470_0402_5%

SUSP

2

G

Q13

2N7002_SOT23

+5VALW TO +5VS

+5VALW

8
7
6
5

1 1

SI4800DY_SO8

1

C653

4.7U_0805_10V4Z

2

+2.5V TO +2.5VS

+2.5V

U73

8

D

7

D

6

D

5

D

SI4800DY_SO8

1

+3VALW TO +3VS

+3VS

2 2

+3VALW

U11

8

S

D

7

S

D

6

S

D

5

G

D

SI4800DY_SO8

1

C196
10U_1206_16V4Z

2

3 3

+1.25V +2.5VS+2.5V +1.2V_HT

1 2
13

D

S

1

C194
10U_1206_16V4Z

2

1
2
3

5VS_GATE0

4

2

C180

0.1U_0402_16V4Z @

1

R16

470_0402_5%

SYSON# SUSPSYSON# SUSP

2

G

Q9

2N7002_SOT23

1

2

12

R155

1M_0402_1%@

C190
1U_0805_25V4Z

R15
470_0402_5%

1 2
13

D

Q8

S

R161

100K_0402_5%

1 2

13

D

G

Q12

S

2N7002_SOT23

2

G

2N7002_SOT23

+1.8VALW TO +1.8VS

+VSB

SUSP

2

R14
10_0603_1%

1 2
13

D

2

G

Q5

S

2N7002_SOT23

2

+1.8VALW

1

2

C1403

4.7U_0805_10V4Z

U12

8

D

7

D

6

D

5

D

SI4800DY_SO8

C193

4.7U_0805_10V4Z

D

S

U45

D
D
D
D

1 2
13

+5VS

1

S

2

S

3

S

4

G

+2.5VS

1

S

2

S

3

S

4

G

1

S

2

S

3

S

4

G

R13
470_0402_5%

2

G

Q4

2N7002_SOT23

5VS_GATE3

4.7U_0805_10V4Z

2

1

0.1U_0402_16V4Z

1

C647

4.7U_0805_10V4Z

2

5VS_GATE1

2

C1653

0.1U_0402_16V4Z@

1

1

C1401

4.7U_0805_10V4Z

2

1

C1654

0.47U_0603_16V7K

2

1

C192

2

R1378

0_0402_5%

1 2

C1655

5VS_GATE2

07/07/'05

1

2

D

S

1

C1402
1U_0805_25V4Z

2

D

S

1

C191
1U_0805_25V4Z

2

D

S

C646
1U_0805_25V4Z

R70

100K_0402_5%

1 2

13

2

G

Q18
2N7002_SOT23

R71

100K_0402_5%

1 2

13

2

G

Q19
2N7002_SOT23

+1.8VS

R72

100K_0402_5%

1 2

13

2

G

Q20
2N7002_SOT23

+VSB

SUSP

+VSB

SUSP

+VSB

SUSP

4 4

Security Classification

PROPRIETARY NOTE

A

B

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2005/03/01 2005/04/06

C

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

B

D

Date: Sheet

DC Interface
LA-2931

E

0.3

37 48Thursday, August 18, 2005

of

5

CF15

CF14
SMD40M80

1

CF4
SMD40M80

1

FD1
FIDUCAL

1

CF16
SMD40M80

1

CF13
SMD40M80

1

FD4
FIDUCAL

1

SMD40M80

1

CF7
SMD40M80

1

FD2
FIDUCAL

1

CF2
SMD40M80

1

CF9
SMD40M80

1

FD5
FIDUCAL

1

CF3
SMD40M80

1

CF10
SMD40M80

1

CF8

CF1

SMD40M80

SMD40M80

1

1

CF6

CF5

SMD40M80

SMD40M80

1

D D

FD3
FIDUCAL

1

FD6
FIDUCAL

1

1

4

H1

H_S354D118

1

H21

H_S354D118

1

H6

H_C394BC217D177

1

H23

H_S354D118

1

H7

H_S354D118

1

H13

H_C394BC217D177

1

H25

H_C394BC217D177

H20

H_S354D118

1

H14

H_S354D118

1

H10

H_C394BC217D177

1

H26

H_O95X52D75X32

H19

H_S354D118

1

H2

H_C276D173

1

H11

H_C394BC217D177

1

H27

H_C197D118

3

H18

H_S354D118

1

H5

H_C276D173

1

H3

H_S433D118

1

H28

H_C394BC217D177

H16

H_C197D118

1

H15

H_C315D315N

1

H9

H_R551X350D165

1

H29
H_C394BC217D177

H17

H_C315D165

1

H4

H_O335X236D256X157

1

H8

H_S354D165

1

H12

H_R354X348D118

1

H22

H_S429D157

1

2

Chip_Name Labe l _Name

EXP_TXP0/SDVOB_RED

EXP_TXN0/SDVOB_RED#

EXP_TXP1/SDVOB_GREEN

EXP_TXN1/SDVOB_GREEN#

EXP_TXP2/SDVOB_BLUE

EXP_TXN2/SDVOB_BLUE#

EXP_TXP3/SDVOB_CLKP

EXP_TXN3/SDVOB_CLKN

EXP_RXP1/SDVO_INT

EXP_RXN1/SDVO_INT#

1

PCIE_MTX_C_GRX_P0

PCIE_MTX_C_GRX_N0

PCIE_MTX_C_GRX_P1

PCIE_MTX_C_GRX_N1

PCIE_MTX_C_GRX_P2

PCIE_MTX_C_GRX_N2

PCIE_MTX_C_GRX_P3

PCIE_MTX_C_GRX_N3

PCEI_GTX_C_MRX_P1

PCEI_GTX_C_MRX_N1

1

C C

B B

1

1

1

1

A A

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/03/01 2005/04/06

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

Screws
LA-2931

0.3

of

38 48Thursday, August 18, 2005

1

A

B

C

D

PJP1

1

3

G

4

G

5

G

@

SINGATRON 2DC-S026-I07

1 1

2 2

3 3

PJP2

G
G

SINGA_2DC-G756I200

PR16

1 2

+CHGRTC

560_0603_5%

PAD-OPEN 3x3m

(4A,160mils ,Via NO.=8) (6A,240mils ,Via NO.= 12)

+5VALWP

PJ3

1 2

PAD-OPEN 3x3m

(5A,200mils ,Via NO.= 10)

4 4

+3VALWP

1 2

(4.5A,180mils ,Via NO.= 9)

+1.2VSP

1 2

(3A,120mils ,Via NO.= 6)

1

2

2

1

2

3

BATT+

51ON#<36>

3.3V

PR17

1 2

560_0603_5%

PJ1

21

PJ5

PAD-OPEN 3x3m

PJ7

PAD-OPEN 3x3m

PD4

RB751V_SOD323

12

CHGRTCP

PR10

100K_0402_5%

PR11

22K_0402_5%

1 2

RTCVREF

12

PC8

4.7U_0805_6.3V6K

+1.8VALW+1.8VALWP

+5VALW

+3VALW

+1.2V_HT

A

ADPIN VIN

12

PC1

560P_0402_50V7K

12

12

PC5

0.22U_1206_25V7K

PU1

G920AT24U_SOT89

3

OUT

GND

1

+2.5VP

+1.25VP

(0.3A,40mils ,Via NO.= 2)

PL1

FBM-L18-453215-900LMA90T_1812

1 2

12

PC2

100P_0402_50V8J

PR9

33_1206_5%

PQ4

TP0610K-T1-E3_SOT23

13

2

12

PR15
200_0805_5%

2

IN

PJ2

1 2

PAD-OPEN 3x3m

PJ4

1 2

PAD-OPEN 3x3m

12

PC7
1U_0805_25V4Z

12

PC3

VIN

+2.5V

+1.25V

12

PC4

100P_0402_50V8J

PD3
1N4148_SOD80

1 2
12

12

PC6

0.1U_0603_25V7K

560P_0402_50V7K

VS

RLZ24B_LL34

ACIN

Precharge detector

Min. typ. Max.
H-->L 14.589V 14.84V 15.243V
L-->H 15.562V 15.97V 16.388V

BATT ONLY

Precharge detector

Min. typ. Max.
H-->L 6.138V 6.214V 6.359V
L-->H 7.196V 7.349V 7.505V

(0.3A,40mils ,Via NO.= 2)

+VSBP +VSB

PJ8

1 2

PAD-OPEN 3x3m

B

PR1

1K_1206_5%

12

PD2

12

PR2
10_1206_5%

VIN

PD1

12

1N4148_SOD80

VL

12

PR14

100K_0402_1%

MAINPWON<6,40,42>

ACON<41>

PD5

2
3

RB715F_SOT323

1

12

RTCVREF

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SE CRET INFOR MATI ON. THIS SHEET MAY NOT BE TRANSF ERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2005/05/10 2006/05/10

1 2

PR3

1K_1206_5%

1 2

PR4

1K_1206_5%

1 2

PR7

1K_1206_5%

1 2

DTC115EUA_SC70

ACOFF<33,41>

NA

PC10

0.1U_0603_25V7K

PU2A

1

LM393M_SO8

O

Compal Secret Data

Deciphered Date

C

PQ2

2

PR12

2.2M_0402_5%

VS

8

P

+

-

G

4

PR20

34K_0402_1%

12

3
2

12

12

PR5

100K_0402_5%

13

DTC115EUA_SC70

12

PC11

1000P_0402_50V7K

12

12

PR6

100K_0402_5%

PQ3

2

12

NA

PRG++

13

D

S

PR22

66.5K_0402_1%

@

PR18
191K_0402_1%

RHU002N06_SOT323

PQ5

2

G

B+

C1664

2200P_0402_50V7K@

TP0610K-T1-E3_SOT23

2

12

PR8
100K_0402_5%

13

2200P_0402_50V7K@

1

1

C1665

2

2

2200P_0402_50V7K@

PQ1

13

C1666

2200P_0402_50V7K@

1

C1667

2

2200P_0402_50V7K@

1

1

C1668

C1669

2

2

2200P_0402_50V7K@

08/15: modify

1

2

B+

12

PR13
499K_0402_1%

12

12

PR19

499K_0402_1%

PR21
47K_0402_5%

13

2

Title

Size Document Number Rev

B

Date: Sheet

PC9

0.01U_0402_25V7Z

12

PQ6
DTC115EUA_SC70

PACIN <41>

+5VALWP

Compal Electronics, Inc.

DCIN/DECTOR

D

39 48Thursday, August 18, 2005

of

0.3

A

B+

PL2

1 2

1 1

FBM-L11-322513-151LMAT_1210

2 2

3 3

B+++

12

PC14

2200P_0402_50V7K

+5VALWP

PD29

2 1

@SKUL30-02AT_SMA

PC15

PC23

12

1

2

150U_D_6.3VM

PQ7

8

G2
D1/S2/K
D1/S2/K
D1/S2/K

AO4916_SO8

S1/A

D2
D2
G1

7
6

4.7U_1206_25V6K

5

5HG

PL3
SIL104R-100

1 2

PR34

+

@

1 2

10.2K_0402_1%

PR36

0_0402_5%

1 2

VS

PZD1

1 2

RLZ5.1B_LL34

1
2
3
4

47K_0402_5%

1 2

PC12

0.1U_0603_25V7K

1 2

<Function Field>

PR27

0_0603_5%

1 2

PR37

PR40

1 2

100K_0402_5%

DL5

DH5

LX5

12

+3.3V Ipeak = 6.66A ~ 10A

PC24

0.047U_0603_16V7K

B

PR23
0_0603_5%

1 2

PR43

1 2

47K_0402_5%

BST5A

1 2

1 2

0_0402_5%

12

PC28

0.047U_0603_16V7K

PC21

PR35
0_0402_5%

2VREF_1999

PR38

12

3

1

PR25

4.7_1206_5%

VL

PC19

12

4.7U_0805_10V4Z

14

BST5

16

DH5

15

LX5

19

DL5

21

OUT5

9

FB5

1

N.C.

MAX8734AEEI+_QSOP28

6

SHDN#

4

ON5

3

ON3

12

SKIP#

8

REF

PC26

0.22U_0603_16V7K

2

PD6
CHP202U_SC70

B+++

12

12

1U_1206_25V7K

18

20

V+

LD05

PU3

GND

23

PC27

12

PR26

4.7_1206_5%

@

PC22

12

0.1U_0603_25V7K

13

TON

LDO3

25

12

4.7U_0805_10V4Z

VL

1 2

17

ILIM3

VCC

ILIM5

BST3

OUT3

PGOOD

PRO#

10

1 2

PR24

47_0402_5%

12

DH3

DL3
LX3

FB3

PR41
0_0402_5%

12

2VREF_1999

PC20

1U_0805_16V7K

5

11
28

26
24
27
22

7
2

SPOK<42>

C

BST3BBST5B

PC16

0.1U_0603_25V7K

PR29

1 2

200K_0402_1%

PR32

1 2

499K_0402_1%

PR30

1 2

200K_0402_1%

PR33

1 2

499K_0402_1%

PC13

0.1U_0603_25V7K

1 2

PR28
0_0603_5%

1 2

BST3A

DH3

B+++

12

PC17

0_0603_5%

12

PC18

2200P_0402_50V7K

4.7U_1206_25V6K

PR31

1 2

D

PQ8

AO4916_SO8

D1/S2/K
D1/S2/K
D1/S2/K

8

G2

7
6
5

PL4
SIL104R-100

DL3

1

D2

2

D2

3

G1

4

S1/A

3HG

LX3

1 2

PR42

0_0402_5%

PR39

1 2

3.57K_0402_1%@

1 2

PC25

150U_D_6.3VM

1

+

PD30

2

2 1

@SKUL30-02AT_SMA

+5V Ipeak = 6.66A ~ 10A

+3VALWP

MAINPWON <6,39,42>

12

PC29
1U_0603_16V6M

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SE CRET INFOR MATI ON. THIS SHEET MAY NOT BE TRANSF ERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

B

2005/05/10 2006/05/10

Compal Secret Data

Deciphered Date

C

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

+5VALWP/+3VALWP

D

40 48Thursday, August 18, 2005

of

0.3

A

B

C

D

E

ACOFF <33,39>

12

PC45

4.7U_1206_25V6K

E

Charger

BATT+

BATT+

of

41 48Thursday, August 18, 2005

0.3

P2

12

PR45
200K_0402_1%

PC38

0.01U_0402_25V7Z

FSTCHG<33>

PZD2

RLZ4.3B_LL34

133K_0402_1%

1 2

VIN

PQ10
AO4407_SO8

1
2
3 6

4

PR52

10K_0402_1%

PR59

PR69
10K_0402_5%

12

10K_0402_1%

1 2

12

PR53

PC40

12

PC46

PR62

100K_0402_1%

PACIN

PR74

10K_0402_5%

MB39A126

12

12

12

8
7

5

12

12

12

4700P_0402_25V7K

MB39A126

PC35

1 2

1K_0402_1%

1 2

PR56

PR50

30.9K_0603_1%

0.22U_0603_16V7K

0.01U_0402_25V7Z

+3VALWP

12

PR65
47K_0402_5%

2

13

2

PQ19
DTC115EUA_SC70

Vin Detector

L->H 18.49 17.92 17.35
H->L 17.17 16.64 16.11

PD31

1 2

@RB751V_SOD323
PR72

10K_0402_5%

1 2

12

PC153

@1000P_0402_50V7K

B

PC41
2200P_0402_50V7K

1 2

ACIN <33>

PQ9

AO4407_SO8

8

RHU002N06_SOT323

PR64

7
5

PQ12

47K

2

47K

13

PQ15
DTC115EUA_SC70

VIN

1 1

12

PR46
47K_0402_5%

DTA144EUA_SC70

2

13

D

PQ16

2

ACOFF#

PACIN<39>

G

S

PD9

1 2

1N4148_SOD80

22K_0402_5%

1 2

2 2

1
2
36

4

1 3

PR54

PQ17

2

G

12

PC34

12

150K_0402_1%

13

D

RHU002N06_SOT323

S

0.1U_0603_25V7K

IREF <33>

IREF=0.932*Icharge

ACON<39>

3 3

IREF=0.466~3.1V

VIN

12

PR68

0_0402_5%

12

PR70

4 4

118K_0402_0.1%

PR75

10K_0402_0.1%

MB39A126_ACIN

12

12

PC127
1000P_0402_50V7K

A

PC51

0.01U_0402_25V7Z@

1 2

1 2

10K_0402_1%@
PR73

Iadp=0~3.42A(65W)

PR44

0.02_2512_1%

1 2

PR51

100K_0402_1%

12

MB39A126_ACIN

PR60

10K_0603_1%

12

PR167
0_0402_5%

CS

13

PQ18
DTC115EUA_SC70

B+

PU4

1

-INC2

2

OUTC2

3

+INE2

4

-INE2

5

ACOK

6

VREF

7

ACIN

8

-INE1

9

+INE1

10

12

OUTC1

11

SEL

12

-INC1

MB39A126PFV-ER_SSOP24

PL5

FBM-L18-453215-900LMA90T_1812

1 2

24

+INC2

23

GND

22

CS

21

VCC

20

OUT

0.1U_0603_25V7K

19

VH

18

XACOK

-INE3

FB123

+INC1

PU5B

LM358A_SO8

47K_0402_1%

17

RT

16

MB39A126

15

14

CTL

13

+

7

0

-

BATT_OVP<33>

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

Fosc=14100/Rt=14100/47=300KHz

12

PC30

4.7U_1206_25V6K

PR58
47K_0402_5%

PR63
47K_0402_5%

12

PC31

4.7U_1206_25V6K

578

PD7

EC31QS04

PC48
47P_0402_25V8K

1 2

PC39

1 2

PACIN

PR57

1 2

PR61

33K_0402_1%

1 2

PC47
10P_0402_50V8J

P2

PR48

0_0603_5%

CS

1 2

12

PC36

0.22U_0603_16V7K

1 2

PC37

0.1U_0603_25V7K

1 2

PC42
1500P_0603_50V7K

1 2

VIN

12

12

LI-3S :13.35V----BATT-OVP=1.482V
BATT-OVP=0.111*BATT+

5
6

PU5A

LM358A_SO8

1

2005/05/10 2006/05/10

VS

12

PC49

8

3

P

+

0

2

-

G

4

Compal Secret Data

Deciphered Date

0.01U_0402_25V7Z

CHG_B+

12

PC32

0.1U_0603_25V7K

PQ13
AO4407_SO8

12

PD8

EC31QS04

BATT+

12

PR66
845K_0603_1%

12

PR67

300K_0603_0.1%

12

PR71

143K_0402_1%

PC33

2200P_0402_50V7K

PL6

1 2

D

36

241

LXCHRG

10U_SIQB125-100A_4.5A_20%

12

12

12

PC50

0.01U_0402_25V7Z

PQ11
AO4407_SO8

1
2
3 6

PR49

10K_0402_1%

PR55

0.02_2512_1%

1 2

4

1 2

13

8
7

5

PR47

47K_0402_1%

1 2

ACOFF#

PQ14
DTC115EUA_SC70

ACOFF

2

12

PC43

4.7U_1206_25V6K

VIN

12

PC44

4.7U_1206_25V6K

CC=3.3A

(100K/(100K+133K))*3.1V=1.33V

1.33/(20*0.02)=3.33A

CP Point=3.06A

5V*(10K/(30. 9 k+10k))=1.222V

1.222V/(20*0.02)=3.06A

Charge voltage
3S CC-CV MODE : 12.6V
SEL is L

Title

Size Document Number Rev

B

Date: Sheet

Compal Electronics, Inc.

PWR-Charger

A

B

C

D

BATT++

PJP3

5

BATT+

TS

SMC

7

SMD

1 1

G

6

GND

G

P_SUYIN_200275MR005G179ZL

TSA

4

EC_SMC1

3

EC_SMD1

2
1

12

PC52
1000P_0603_50V7K

12

12

PR76

100_0603_1%

12

PR80

100_0603_1%

12

PR83
1K_0603_1%

1

PD11

1

PD12

PR81

1 2

@BAS40-04_SOT23

1

6.49K_0603_1%

3

+3VALWP

PL7

1 2

FBM-L18-453215-900LMA90T_1812

PC53
1000P_0603_50V7K

12

PC54

0.01U_0603_50V7K

2

2

2

3

2 2

@BAS40-04_SOT23

@BAS40-04_SOT23

3

+3VALWP

B+

12

PR86

100K_0402_5%

PR87

VL

22K_0402_5%

1 2

12

PD10

PC58

0.22U_1206_25V7K

2

PQ20

TP0610K-T1-E3_SOT23

13

12

PC59

0.1U_0603_25V7K

BATT_TEMP <33>

EC_SMB_CK1 <33,34>
EC_SMB_DA1 <33,34>

+VSBP

BATT+

PC56

1000P_0402_50V7K

PH1 under CPU botten side :

CPU thermal protection at 85 degree C
Recovery at 70 degree C

PR78

10.7K_0402_1%

12

VL

12

1 2

12

12

PC55

0.1U_0603_25V7K

PR82

61.9K_0603_1%

TM_REF1

PH1
100K_0603_1%_TH11-4H104FT

12

PC57

1U_0603_10V

12

5

+

6

-

PR84

150K_0402_1%

PR85
150K_0402_1%

VS

PR79

1 2

442K_0603_1%

8

PU2B

P

O

G

LM393M_SO8

4

12

7

VL

VL

PR77
150K_0402_1%

1 2

MAINPWON <6,39,40>

3 3

SPOK<40>

PR88
100K_0402_5%

PR89

1 2

0_0402_5%

1 2

PC60

@

0.1U_0402_16V7K

13

D

PQ21

2

G

RHU002N06_SOT323

S

12

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SE CRET INFOR MATI ON. THIS SHEET MAY NOT BE TRANSF ERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

B

2005/05/10 2006/05/10

Compal Secret Data

Deciphered Date

C

Title

Size Document Number Rev

B

Date: Sheet

Compal Electronics, Inc.

BATTERY CONN. / OTP

D

42 48Thursday, August 18, 2005

of

0.3

5

D D

4

3

2

1

FBM-L11-322513-201LMAT_1210

B+

PL8

1 2

+1.2VSP Current limit = 8.29A ~9.6A

C C

PR91

5.62K_0402_1%

1 2

0.01U_0402_25V7Z

1 2

12

PC65

3300P_0402_50V7K

B B

+5VS

12

PC66

4.7U_0805_6.3V6K

PC63

PU6

10

OCSET

2

SS

1

FB

3

VCC

4

GND

MAX8578EUB

12

PC61

0.1U_0603_25V7K

9

IN

DH_1.2V

8

DH

LX_1.2V

7

LX

5

DL

6

BST

BST_1.2V

PD13

12

1SS355_SOD323

12

PC62

4.7U_1206_25V6K

1 2

PR92

0_0402_5%
PR162

0_0402_5%

DL_1.2V

1 2

4.7_0402_5%
PR93

1 2

PC67

0.1U_0603_25V7K

680P_0603_50V8J

PC64

12
12

1U_0805_25V4Z@

PC69

PR90

1 2

0_0402_5%

12

PR94

12

PR98

866_0402_1%

8

G2

7

D1/S2/K

6

D1/S2/K

5

D1/S2/K

FDS6900_SO8

12

8.2K_0402_1%

4.7_1206_5%

12

0.033U_0603_25V7K

VLDT_EN<33,36>

PQ22

1

D2

2

D2

3

G1

4

S1/A

PL9 2.0UH_SPC-07040-2R0_6A_30%

12

PR95

PR97
1K_0402_1%

1 2

1 2

PC70

12

1 2

PR96

30_0402_5%

PC71

0.1U_0603_25V7K

1

+

PC68
220U_D2_2VMR15

2

+1.2VSP

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2005/05/10 2006/05/10

3

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

B

2

Date: Sheet

Compal Electronics, Inc.

+1.2VSP

43 48Thursday, August 18, 2005

1

0.3

of

5

4

3

2

1

+2.5VP O.C.P. =9A ~ 12.2A

+1.8VALWP Current limit = 9.55A ~12.76A

B++++

D D

12

12

PC73

PC72

4.7U_1206_25V6K

12

PC75

4.7U_0805_6.3V6K

PQ23

SI4800BDY-T1-E3_SO8

5

D8D7D6D

S1S2S3G

C C

+1.8VALWP

PC82

330U_V_2V_R15

1

+

2

12

4.7U_0805_6.3V6K

PC83

10.5K_0402_1%

PR103

1.8U_SIL104R-1R8_9.5A_30%

12

12

PC84

0.01U_0402_25V7Z

PL11

1 2

SI4810BDY-T1-E3_SO8

12

PR104
0_0402_5%

PQ25

D8D7D6D

S1S2S3G

4

0.1U_0402_16V7K

5

4

PC80

1.96K_0402_1%

0.1U_0603_25V7K

BST_1.8V-2

1 2

12

PR105

1 2

PD14

DAP202U_SOT323

1

0.1U_0603_25V7K

2

3

PC78

0.01U_0402_25V7Z

BST_1.8V-1

PR101
0_0603_5%

DH_1.8V

ISE_1.8V

DL_1.8V

PC76

12

12

6

5
4

7
2

3

9

10

8

15
11

12

PR116

90.9K_0402_1%

PC89

VSE_1.8V

12

12

B B

PR112

10K_0402_1%

12

PR114

0_0402_5%@

+5VALWP

1 2

0_0402_5%

0.1U_0402_16V7K@

PR109

PR99

51_1206_5%

12

SOFT1

BOOT1

UGATE1
PHASE1

ISEN1
LGATE1

PGND1

VOUT1
VSEN1
EN1
PG1

OCSET1

12

+5VALWP

14

VIN

PU7

ISL6227CA-T_SSOP28

GND

1

PR100

2.2_0603_5%

1 2

28

SOFT2

VCC

BOOT2

UGATE2
PHASE2

ISEN2

LGATE2

PGND2

VOUT2
VSEN2

PG2/REF

OCSET2

DDR

13

EN2

PC77

12

2.2U_0805_10V6K

BST_2.5V-2

PC79

12

17

0.01U_0402_25V7Z

BST_2.5V-1

1 2

23

0_0603_5%

DH_2.5V

24

LX_2.5VLX_1.8V

25

ISE_2.5V

22

DL_2.5V

27

26

VOUT_2.5VVOUT_1.8V

20

VSE_2.5V

19
21
16

18

12

PR102

PR106

1.96K_0402_1%

1 2

PR115

90.9K_0402_1%

PC81

0.1U_0402_16V7K

12

1 2

PR110 0_0402_5%

12

PC88

0.1U_0402_16V7K@

5

PQ24
SI4800BDY-T1-E3_SO8

D8D7D6D

S1S2S3G

4

1.8U_SIL104R-1R8_9.5A_30%

5

1 2

PQ26

D8D7D6D

SI4810BDY-T1-E3_SO8

S1S2S3G

4

PL12

PR107

0_0402_5%

12

PC74

4.7U_1206_25V6K

PL10
FBM-L11-322513-151LMAT_1210

1 2

12

12

PC87

0.01U_0402_25V7Z

12

PR113
0_0402_5%@

B+

12

PR108

18.2K_0402_1%

12

PR111
10K_0402_1%

+2.5VP

1

12

+

220U_D2_4VM

PC85

PC86

4.7U_0805_6.3V6K

2

SYSON <33,37>

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2005/05/10 2006/05/10

3

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

B

2

Date: Sheet

Compal Electronics, Inc.

+1.8VALWP/+2.5VP

44 48Thursday, August 18, 2005

1

0.3

of

5

4

3

2

1

D D

10U_1206_6.3V7K

PR122

0_0402_5%

SYSON#<35,37>

C C

B B

1 2

0.1U_0402_16V7K@

PC100

PC90

12

+1.8VALWP

12

1K_0402_1%

13

D

2

G

S

PQ28

RHU002N06_SOT323

+2.5VP

PR119

PR123

1K_0402_1%

PU8

VIN1VCNTL

2

GND

3

VREF

4

12

12

12

PC98

0.1U_0402_16V7K

VOUT

APL5331KAC-TR_SO8

12

PC95

22U_1206_6.3V6M

12

6
5

NC

7

NC

8

NC

9

TP

+1.25VP

PC96

@

22U_1206_6.3V6M

12

PC91
1U_0603_10V

+3VALWP

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2005/05/10 2006/05/10

3

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

B

2

Date: Sheet

Compal Electronics, Inc.

+1.25VSP/+1.5VSP

45 48Thursday, August 18, 2005

1

0.3

of

5

4

3

2

1

+CPU_CORE

12

PR135
10_0402_5%

@

CPU VCC SENSE

1 2

PC112

1 2

46 48Thursday, August 18, 2005

of

B+

1000P_0402_50V7K

@

12

PR152

CPU_COREFB

0.3

0_0402_5%

+5VS

+3VS

12

D D

VID0<6>
VID1<6>
VID2<6>
VID3<6>
VID4<6>

VGATE< 33>

PR141

VR_ON <33>

0_0402_5%

1 2

1 2

C C

VCC

PR143

100K_0402_5% @

PR126 0_0402_5%
PR128 0_0402_5%

PR130 0_0402_5%
PR132 0_0402_5%
PR134 0_0402_5%

PR136 0_0402_5%

1 2

PR137 @0_0402_5%

1 2

1 2

PR149

1 2

121K_0402_1%

B B

A A

5

PR146 200K_0402_1%

PR148

80.6K_0402_1%

PR150

1 2

80.6K_0402_1%

PC115 0.22U_0603_16V7K

12

PC116

100P_0402_50V8J

PR125 @10K_0402_5%

12
12

12
12
12
12

PR144

PC113

1 2

270P_0402_50V7K

1 2

PR151 0_0402_5%

REF

12

@

For EC ATE

PR124 10_0402_5%

PC107
1U_0603_10V6K

1 2

VCC

J1 SHORT PADS

1 2

12

60.4K_0402_1%

REF
ILIM

12

4

PC106

DHM
LXM

PGND

OAIN+
OAIN-

BSTM

12

PC109

0.22U_0603_16V7K

1 2

DLM

FDS6294_SO8

PR131
0_0603_5%

BSTM

PQ29

12

PQ31

PC110

4700P_0402_25V7K

@

PD17

2

3

CHP202U_SC70

PR153

1 2

2.2_0402_5%

12

PC122

0.22U_0603_16V7K

100K_0402_5%@
PR158

1 2

OAIN+

<6>

PC125

OAIN+

12

@1000P_0402_50V7K

PC126

@

OAIN-

12

@1000P_0402_50V7K

2005/05/10 2006/05/10

3

PQ33

FDS6294_SO8
PR155

0_0603_5%

1 2

PC124

1 2

4700P_0402_25V7K@

Compal Secret Data

Deciphered Date

1 2

2.2U_0603_6.3V6K

10

VCC

24

D0

23

D1

22

D2

21

D3
D4
OVP
VROK
S0
S1
SHDN#
TIME
CCV
TON
REF
ILIM
OFS
SUS
SKIP
GND

PU10

MAX1544

Near CPU GND

20
19
25

4
5
6
1

12

2
8
9
7

3
18
11

VDD

BSTM

DHM

LXM

DLM

PGND

CMP
CMN

OAIN+

OAIN-

BSTS

DHS

LXS

DLS
CSP
CSN

GNDS

V+

FB

CCI

30
36
26
28
27
29
31
37
38
17
16
15
14
35
33
34
32
40
39
13

12

@

1000P_0402_50V7K

PR156
10_0402_5%

12

PC108

0.01U_0402_25V7Z

PR129

1 2

2.2_0402_5%

FB

1 2

PC114 470P_0402_50V8J

DHS
LXS
DLSREF

GNDS

12

PC121

1 2

PR154

100_0402_5%

CPU_COREFB#

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

CPU_B+

5

D8D7D6D

S1S3G

S

4

2

5

D8D7D6D

S1S3G

S

4

2

FDS6676AS_SO8

PR145 820_0402_5%

1 2

+5VS

1

5

D8D7D6D

S1S3G

S

4

2

5

D8D7D6D

PQ35

S1S3G

S

4

2

FDS6676AS_SO8

PR159

1 2

820_0402_5%

PQ32

PQ36

PL13

FBM-L18-453215-900LMA90T_1812

1 2

12

12

PC102

PC101

4.7U_1206_25V6K

PR127

PR190

PC151

CPU_B+

PC117

100K_0402_5%@

1 2
12

12

PR191

PC152

OAIN+

@4.7_1206_5%

2 1

SKS30-04AT_TSMA

PD16

@680P_0603_50V8J

12

PC118

4.7U_1206_25V6K

2200P_0402_50V7K

@4.7_1206_5%

1 2

12

@680P_0603_50V8J

1 2

5

4

FDS6676AS_SO8

D8D7D6D

S1S3G

S

2

FDS6676AS_SO8

5

D8D7D6D

S1S3G

S

4

2

2

12

12

PC103

4.7U_1206_25V6K

0.01U_0402_25V7Z

PL14

PCMC104T-R56MN25A

1 2

12

PR138

820_0402_5%

PC111

PC104

2200P_0402_50V7K

12

1 2

1 2

0.47U_0603_16V7K

PR147

1 2

1.82K_0402_1%

12

12

PC120

PC119

4.7U_1206_25V6K

0.01U_0402_25V7Z

PL15

PCMC104T-R56MN25A

1 2

PR157
820_0402_5%

PD18

1 2

2 1

Title

Size Document Number Rev

Custom

Date: Sheet

SKS30-04AT_TSMA

1 2

PC123

0.47U_0603_16V7K

+CPU_CORE

1

+

PC105

2

PR133 0.001_2512_1%

12

PR140 499_0402_1%

PR139 499_0402_1%

1

100U_25V_M

PR142 1.82K_0402_1%

<6>

5

4

3

2

1

Version change list (P.I.R. List) Page 1 of 1

for PWR

Reason for change Rev. PG# Modify List VER PhaseFixed IssueItem

1

D D

add ACIN detect RC filter

42 add PD31,PC153 DVT

2

3
4

5

reverve or decrease CPU CORE ring with EMI solution :
snubber

Modify 1.2VP voltage level 44 change PR95 from 6.81k to 8.2k

delete 1.2VP power good 44 delete PR164,PR163, PR165,PR166,PQ38,PQ39, PC128

delete Charger 3S/4S selector

Reserve PR190//PR191: 4.7 1206 ,add

47 DVT

PC151/PC152:680P

DVT

DVT

42

delete PR160,PQ37

DVT

6

C C

7

8

9

10

11

B B

8

9

A A

Title

Size Document Number Rev

5

4

3

2

Date: Sheet

Compal Electronics, Inc.

PIR (PWR)

LA-2931

of

47 48Thursday, August 18, 2005

1

0.3

5

4

3

2

1

Version change list (P.I.R. List) Page 1 o f 1 for HW

Reason for change Rev. PG # Modify List VER P haseFixed IssueItem

1

D D

1.Del +3V PWR

1.Del Q3,C611,C609,C639,R341,Q24,R340

2

0.2

0.2

30,31

37

1.Del JP6

2.PWR_SUSP_LED#/WL_ON_LED#/BT_ON_LED# conn to EC

3

1.Del NET MSPWREN#

2.Del R561/R634

4

3.Change XDOC# to MSOC#

C C

1.change LAN LED PWR from +2.5V_LAN to +3VALW

5

2.DEL R856

3.Change Q52

1.DEL MIC1

2.Change Q38

6

1.Change U26 to G528

7

2.ADD C1656/R1379/R1380/L97/L98/L99/R1381~R1386

0.2

0.2 24/25

0.2 26

0.2 29

0.2 35

36

8

B B

9

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2005/03/08 2006/03/08

3

Compal Secret Data

Deciphered Date

Title

PIR (HW)

Size Document Number Rev

Custom

EFL50 LA-2761

2

Date: Sheet

48 48Thursday, August 18, 2005

1

0.3

of