Page 1
5
4
3
2
1
REV : A01
ZRS
D D
@ : Nopop Component
1@ : ZUMA Used Only
2@ : Riker Used Only
3@ : ZRS with discrete Used Only
4@ : ZUMA & Zanzibar Used Only
C C
with BCM4401E w/o Docking and Smart card
5@ : Rikers & Suva Used Only
with BCM5752/Docking/Smart Card
6@ : Suva Used Only
7@ : Rikers/Zanzibar/ZUMA Used Only
Config. TABLE
Project Config.
B B
ZUMA 1@ + 4@ +7@
Zanzibar 3@ + 4@ + 7@
Suva 3@ + 5@ + 6@
Rikers 2@ + 3@ + 5@ + 7@
Yonah Schematics with Capture CIS and Function Field
A A
uFCPGA Yonah
12/13/2005
REV : 2.0
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
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NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
DELL CONFIDENTIAL/PROPRIETARY
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
Cover Sheet
LA-2881P
162Tuesday, December 13, 2005
1
of
2.0
Page 2
5
4
3
2
1
Compal confidential
Clock Generator
Block Diagram
CK410M+
Yonah
D D
C C
B B
5 in 1 CONN.
Media/Touch Pad
CONN.
A A
Multi-media
Thermal
GUARDIAN II
EMC4000
+3.3V_SUS
VGA
Board
Docking
Port
page 36
IDSEL:AD17
(PIRQA/B#,GNT#2,REQ#2)
Docking
Buffer
Memory Card &
1394 Controller
RICOH R5C832
1394 CONN.
page33
page39
Board
5
SMBus
page 16
CRT CONN.
& TV-OUT
VGA CONN.
page 35
3.3V 33MHz
Express
Card
page 33
page33
ST M25P80
+3.3V_ALW
page 37
LED Controller
PAC9532
Rikers Used Only
page 41
LOM
4401E
page 31
page 34
USB3
page 20
page 19
PCI-E 16X
MINI
Card
page 34
USB1
GPIO
SPI
SMBus
Touch Pad
USB
4
PCI BUS
PCIe BUS
LOM
BCM5752
page 31
RJ45 with
Giga
Magnetic
page 32
MEC5004
LPC to X-BUS
PS2
page 39
Bluetooth
page 28
uFCPGA CPU
HA#(3..31)
System Bus
533 / 667 MHz
Calistoga
GMCH-M
1466 FC-BGA
Intel 945PM/945GM
DMI
1.5V
100MHz
ICH7-M
652 BGA
Intel 82801GBM
page 22,23,24,25
LPC BUS
3.3V 33MHz
ECE5018
Super I/O
page 38
Int.KBD
page 39
USB4
Smart Card
Fan Control
page 7,8,9
HD#(0..63)
Memory
BUS(DDRII)
1.8V 533 / 667 MHz
page 10,11,12,13,14,15
DDRII-SODIMM X2
BANK 0, 1, 2, 3
Azalia
3.3V or 5V SATA
SATA
ATA100
HDD
USB5
CDROM
page 26
page 26
Phone Jack
48MHz / 480Mb
USB0
page 37
USB2
OZ77C6
page 34
USB2.0
IO PORT
page 30
USBPORT 0
USBPORT 1
USBPORT 2
USBPORT 3
USBPORT 4
USBPORT 5
USBPORT 6
USBPORT 7
Ext. USB
Ext. USB
Ext. USB
Ext. USB
Ext. USB
SIO ECE5018
Ext. USB
Dock
Slot
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
AMP &
page 6
page 16
page 17,18
MDC
page 29
Azalia CODEC
STAC9200
page 27
Subwoofer
page 28
DELL CONFIDENTIAL/PROPRIETARY
Title
Size Document Number Rev
Date: Sheet
1.5V/1.05V(+VCCP)
page 29
Compal Electronics, Inc.
Block Diagram
LA-2881P
DC IN
page 43
BATT IN/+2.5V
page 44
3.3V/5V/15V
page 45
page 46
1.8V / 0.9V
page 47
IMVP6 VCORE
3 Phase
page 48
CHARGER
page 49
262Tuesday, December 13, 2005
1
of
2.0
Page 3
5
4
3
2
1
D D
C C
PM TABLE
State
S0
S1
S3
S5 S4/AC
S5 S4/AC don't exist
power
plane
+5V_ALW
+3.3V_ALW
+3.3V_SRC
ON
ON
ON
ON
+5V_RUN
+15V_SUS
+5V_SUS
+3.3V_SUS
+1.8V_SUS
ON ON
ON
ON
OFF
OFFOFF
+3.3V_RUN
+2.5V_RUN
+1.8V_RUN
+0.9V_DDR_VTT
+VCC_CORE
+1.05V_VCCP
ON
OFF
OFF
OFF
ICH7-M
SIO
ECE5018
USB PORT#0Description
SUPER I/O ECE5018
1
2
3
4
5
6
JUSB_R (Ext Back Right Bottom)
JUSB_S (Ext Side Bottom)
JUSB_R (Ext Back Right Top)
JUSB_L (Ext Back Left Top)
JUSB_S (Ext Side Top)
JUSB_L (Ext Back Left Bottom)
7 DOCKING
0
1
2
3
4
ICH7-M
MINI CARD WLAN
SMART CARD
EXPRESS CARD
BLUE TOOTH
B B
A A
PCI TABLE
PCI DEVICE IDSEL
LAN
Dock
AD24 REQ#0/GNT#0 IRQA
REQ#/GNT#
REQ#3/GNT#3AD16 IRQB
PIRQ
R5C832 AD17 REQ#2/GNT#2 IRQC,D
PCI EXPRESS
Lane 1
Lane 2
Lane 3
Lane 4
DESTINATION
No
MINI CARD WLAN
GIGA LAN
EXPRESS CARD
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
Index and Config.
LA-2881P
362Tuesday, December 13, 2005
1
2.0
of
Page 4
5
4
3
2
1
ALWON
D D
ADAPTER
ALWON
+PWR_SRC
BATTERY
+3.3V_ALW
C C
+5V_ALW
+3.3V_ALW
+3.3V_SRC
ENAB_3VLAN
SUS_ON
RUN_ON
+3.3V_LAN
+3.3V_SUS
+3.3V_RUN
Guardian II
5752 Only
REGCTL_PNP12
MMJT9435T1G
( Q102 )
REGCTL_PNP25
BCP69
( Q103 )
+2.5V_RUN
+1.2V_1.8V_LAN
+2.5V_LAN
Charger
MAX8632
(PU6)
SUSPWROK_5V
+1.8V_SUS
RUN_ON
+0.9V_DDR_VTT
+5V_SUS
SUS_ON
ISL6220
(PU8)
RUN_ON
+VCC_CORE
ISL6227
(PU5)
RUNPWROK
+1.5V_RUN
RUN_ON
+1.05V_VCCP
B B
SI3456
(Q22)
HDDC_EN#
+5V_HDD +5V_MOD +5V_RUN +VDDA
A A
SI3456
(Q24)
MODC_EN#
PJP19
( Option )
5
PJP20
( Option )
SI4810
(Q61)
RUN_ON
AUDIO_AVDD_ON
L31
(Option)
793475
(U12)
PL8 & PD8
+15V_SUS
4
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
DELL CONFIDENTIAL/PROPRIETARY
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
Power Rail
LA-2881P
462Tuesday, December 13, 2005
1
of
2.0
Page 5
5
ICH_SMBCLK
C22
D D
ICH7-M
ICH_SMBDATA
B22
CLK_SMB
10
DAT_SMB
9
4
+3.3V_SUS
2.2K 2.2K 2.2K 2.2K
+3.3V_SUS
+3.3V_ALW
87
Express Card
2.2K 2.2K
SMBUS Address [TBD]
+3.3V_ALW
+5V_ALW
3
5752M
LOM
SMBUS Address [C8]
2
+3.3V_RUN
2N7002
2N7002
C8C7
3032
CLK_SCLK
CLK_SDATA
MINI WLAN Card
SMBUS Address [TBD]
8
GUARDIAN
7
SMBUS Address [5E]
16
17
197
195
197
195
1
CLK GEN.
SMBUS Address [D2]
DIMMA
SMBUS Address [A0]
DIMMB
C C
DOCK_SMB_CLK
6
DOCK_SMB_DAT
SIO
Macallan IV
B B
5
112
111
8
7
SBAT_SMBCLK
SBAT_SMBDAT
PBAT_SMBCLK
PBAT_SMBDAT +3V_ALW
10K 10K
+3.3V_ALW
2.2K 2.2K
+3.3V_ALW
2.2K 2.2K
+5V_ALW
+3.3V_ALW
39
DOCK
40
6
LVDS connector
5
10
Discrete
8
Graphic
100
100
SMBUS Address [C4, 72, 70, 48]
Inverter
SMBUS Address [58]
SMBUS Address [98]
3
BATTERY
4
CONN
9
CHARGER
10
SMBUS Address [16]
SMBUS Address [12]
SMBUS Address [A4]
A A
23
22
LED PWM
SMBUS Address [C0]
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
SMBUS TOPOLOGY
LA-2881P
562Tuesday, December 13, 2005
1
2.0
of
Page 6
5
D
1
G S
2
D D
FSC FSB FSA CPU
CLKSEL2 CLKSEL0CLKSEL1
2N7002
3
ICH_SMBDATA<23,30,34> CLK_SDATA <17,18>
+3.3V_RUN
ICH_SMBCLK<23,30,34>
000
00
*
0
0
C C
1
1
1
11
1
0
1
11
00
1
0
1
0
1
+3.3V_RUN
ICH_SMBDATA
ICH_SMBCLK
MHz
266
133
200
166
333
100
400
Reserve
Table : ICS954305AK
CPU_BSEL CPU_BSEL2(FSC) CPU_BSEL1(FSB)
133
166
B B
0
0
D
1 3
1 3
D
SRC
MHz
100
100
100
100
100
100
100
G
2
2
G
0
1
2.2K_0402_5%~D
12
R232
S
Q51
2N7002_SOT23~D
S
Q52
2N7002_SOT23~D
PCI
MHz
33.3
33.3
33.3
33.3
33.3
33.3
33.3
2.2K_0402_5%~D
12
R233
CLK_SDATA
CLK_SCLK
+CK_VDD_A
C508
4.7U_0805_10V4Z~D
1
2
Place crystal within
500 mils of CK410M
CLK_ICH_48M<23>
CLK_SMCARD_48M<34>
CPU_MCH_BSEL0<8,10,12>
CLK_PCI_5004<38>
CLK_PCI_5018<37>
CLK_PCI_LAN_LPC<30>
CLK_PCI_PCCARD<33>
CLK_PCI_DOCK<36>
CLK_ICH_14M<23>
CLK_SIO_14M<37>
MCH_DREFCLK<10>
MCH_DREFCLK#<10>
CLK_PCI_ICH<21>
CLK_PCI_LAN<31>
Layout Notes:
Trace length between R255.2, R222.2 and R579.2 =< 50 mils
Trace length between R176.2, R175.2 =< 50 mils
Trace length between R191.2, R190.2 =< 50 mils
+3.3V_RUN
R578
A A
10K_0402_5%~D
1 2
FSA
12
R575
10K_0402_5%~D@
5
+3.3V_RUN
R204
1 2
PCI_SIO
12
R203
FCTSEL1
10K_0402_5%~D3@
(PIN34)
0
10K_0402_5%~D1@
1
4
0.1U_0402_16V4Z~D
CLK_SCLK <17,18>
C511
0.047U_0402_10V7K~D
1
2
27P_0402_50V8J~D
27P_0402_50V8J~D
+3.3V_RUN
PIN43
+3.3V_RUN
1
C509
2
+CK_VDD_48
C532
4.7U_0805_10V4Z~D
C232
1 2
C236
1 2
CLK_ICH_48M
CLK_SMCARD_48M
CPU_MCH_BSEL0
CLK_PCI_5004
CLK_PCI_5018
CLK_PCI_LAN_LPC
CLK_PCI_PCCARD
CLK_ICH_14M
CLK_SIO_14M
MCH_DREFCLK
CLK_PCI_ICH PCI_ICH
CLK_PCI_LAN
C525
0.047U_0402_10V7K~D
1
1
2
2
12
R213 15_0402_5%~D
R222 15_0402_5%~D
R579 8.2K_0402_5%~D
CPU_MCH_BSEL1<8,10>
CPU_MCH_BSEL2<8,10>
R176 15_0402_5%~D
R175 15_0402_5%~D
R202 33_0402_5%~D
R201 33_0402_5%~D
R200 33_0402_5%~D
R191 15_0402_5%~D
R190 15_0402_5%~D
R228 33_0402_5%~D1@
R236 33_0402_5%~D1@
R205 15_0402_5%~D
R206 15_0402_5%~D4@
R180 10K_0402_5%~D
CLK_ENABLE#<48>
PIN44
L48
1 2
BLM21PG600SN1D_0805~D
+CK_VDD_MAIN2
L51
1 2
BLM21PG600SN1D_0805~D
+CK_VDD_REF
Y1
14.31818MHz_20P_1BX14318CC1A~D
R199 220_0402_5%~D
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
0.047U_0402_10V7K~D
1
2
12
12
12
12
R563 475_0603_1%~D
PIN47 PIN48
DOT96T DOT96C 96/100M_T 96/100M_C
27M_out
4
27M SSout
SRCT0
SRCC0
C528
R582
1_0603_5%~D
1 2
1 2
R585
2.2_0603_5%~D
CLK_XTAL_IN
CLK_XTAL_OUT
R588 8.2K_0402_5%~D
1 2
3
+CK_VDD_MAIN
1
C504
0.1U_0402_16V4Z~D
2
1
C530
0.1U_0402_16V4Z~D
2
2.2_0603_5%~D
1 2
U16
1
VDDSRC
VDDSRC
VDDSRC
VDDSRC
VDDPCI
VDDPCI
VDDCPU
VDDREF
VDD48
XIN
XOUT
USB_48MHz/FSLA
FSLB/TEST_MODE
REF0/FSLC/TEST_SEL
PCICLK4/FCTSEL1
PCICLK3
PCICLK2
PCICLK1
REF1
DOTT_96MHz/27MHz
DOTC_96MHz/27MHz
ITP_EN/PCICLK_F0
Vtt_PwrGd#/PD
9
IREF
SMBCLK
SMBDAT
4
GNDSRC
GNDCPU
GNDREF
GNDPCI
GNDPCI
GND48
GNDSRC
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
ICS954305EKLFT_MLF72~D
R556
1
C506
0.1U_0402_16V4Z~D
2
1
C531
0.1U_0402_16V4Z~D
2
+CK_VDD_A
VDDA
GNDA
PCI_STOP#
CPU_STOP#
CPUT1
CPUC1
CPUT0
CPUC0
CPUT_ITP/SRCT10
CPUC_ITP/SRCC10
SRCT9
SRCC9
CLKREQ9#
SRCT8
SRCC8
CLKREQ8#
SRCT7
SRCC7
CLKREQ7#
SRCT6
SRCC6
CLKREQ6#
SRCT5
SRCC5
CLKREQ5#
SRCT4
SRCC4
CLKREQ4#
SRCT3
SRCC3
CLKREQ3#
SRCT2
SRCC2
CLKREQ2#
SRCT1
SRCC1
CLKREQ1#
LCD100/96/SRC0_T
LCD100/96/SRC0_C
1
C512
0.1U_0402_16V4Z~D
2
7
8
H_STP_PCI#
25
H_STP_CPU#
24
11
10
CPU_BCLK
14
13
CPU_ITP
6
CPU_ITP#
5
3
2
72
70
PCIE_SATA#
69
SATA_CLKREQ#
71
66
67
38
PCIE_ICH
63
PCIE_ICH#
64
62
MCH_3GPLL
60
MCH_3GPLL#
61
CLK_3GPLLREQ#
29
PCIE_LOM
58
PCIE_LOM#
59
57
PCIE_VGA CLK_PCIE_VGA
55
56
28
PCIE_EXPCARD CLK_PCIE_EXPCARD
52
PCIE_EXPCARD# CLK_PCIE_EXPCARD#
53
CARD_CLK_REQ#
26
PCIE_MINI
50
PCIE_MINI#
51
MINICLK_REQ#
46
DOT96_SSC
47
DOT96_SSC#
48
+CK_VDD_REF
+CK_VDD_48
FSA
CPU_MCH_BSEL1
FSC
12
PCI_SIO
PCI_LOM
PCI_PCCARD
PCI_DOCKCLK_PCI_DOCK
CLKREF
DOT96
DOT96#MCH_DREFCLK#
CLK_ENABLE#
CLKIREF
CLK_SCLK
CLK_SDATA
1
C499
10U_0805_10V4Z~D
2
C534
10U_0805_10V4Z~D
49
54
65
30
36
12
18
40
20
19
41
45
23
34
33
32
27
22
43
44
37
39
16
17
15
21
31
35
42
68
73
74
75
76
Solder Thermal Pad to GND. Add Min. 4 vias.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
1
C520
0.1U_0402_16V4Z~D
2
1
2
Place near each pin
W>40 mil
Place near CK410+
CLK_MCH_BCLKMCH_BCLK
CLK_MCH_BCLK#MCH_BCLK#
CLK_CPU_BCLK
CLK_CPU_BCLK#CPU_BCLK#
CLK_CPU_ITP
CLK_CPU_ITP#
CLK_PCIE_SATAPCIE_SATA
CLK_PCIE_SATA#
CLK_PCIE_ICH
CLK_PCIE_ICH#
CLK_MCH_3GPLL
CLK_MCH_3GPLL#
CLK_PCIE_LOM
CLK_PCIE_LOM#
CLK_PCIE_VGA#PCIE_VGA#
CLK_PCIE_MINI
CLK_PCIE_MINI#
DREF_SSCLK
DREF_SSCLK#
1 2
R239 33_0402_5%~D
1 2
R248 33_0402_5%~D
1 2
R224 33_0402_5%~D
1 2
R231 33_0402_5%~D
1 2
R255 33_0402_5%~D
1 2
R260 33_0402_5%~D
1 2
R276 33_0402_5%~D
1 2
R277 33_0402_5%~D
1 2
R547 10K_0402_5%~D
1 2
R279 33_0402_5%~D
1 2
R278 33_0402_5%~D
1 2
R281 33_0402_5%~D
1 2
R280 33_0402_5%~D
R590 10K_0402_5%~D
1 2
1 2
R283 33_0402_5%~D5@
1 2
R282 33_0402_5%~D5@
1 2
R285 33_0402_5%~D3@
1 2
R284 33_0402_5%~D3@
1 2
R270 33_0402_5%~D
1 2
R272 33_0402_5%~D
R589 10K_0402_5%~D
1 2
1 2
R257 33_0402_5%~D
1 2
R264 33_0402_5%~D
R566 10K_0402_5%~D
1 2
1 2
R241 33_0402_5%~D1@
1 2
R252 33_0402_5%~D1@
2
1
C699
0.1U_0402_16V4Z~D
H_STP_PCI# <23>
H_STP_CPU# <23>
CLK_MCH_BCLK <10>
CLK_MCH_BCLK# <10>
CLK_CPU_BCLK <7>
CLK_CPU_BCLK# <7>
CLK_CPU_ITP <7>
CLK_CPU_ITP# <7>
CLK_PCIE_SATA <22>
CLK_PCIE_SATA# <22>
SATA_CLKREQ# <23>
+3.3V_RUN
CLK_PCIE_ICH <23>
CLK_PCIE_ICH# <23>
CLK_MCH_3GPLL <10>
CLK_MCH_3GPLL# <10>
CLK_3GPLLREQ# <10>
+3.3V_RUN
CLK_PCIE_LOM <30>
CLK_PCIE_LOM# <30>
CLK_PCIE_VGA <19>
CLK_PCIE_VGA# <19>
CLK_PCIE_EXPCARD <34>
CLK_PCIE_EXPCARD# <34>
CARD_CLK_REQ# <34>
+3.3V_RUN
CLK_PCIE_MINI# <34>
MINICLK_REQ# <34>
+3.3V_RUN
DREF_SSCLK <10>
DREF_SSCLK# <10>
CLK_PCIE_MINI <34>
CLK_CPU_ITP
CLK_CPU_ITP#
CLK_MCH_BCLK
CLK_MCH_BCLK#
CLK_CPU_BCLK
CLK_CPU_BCLK#
CLK_MCH_3GPLL
CLK_MCH_3GPLL#
CLK_PCIE_SATA
CLK_PCIE_SATA#
CLK_PCIE_ICH
CLK_PCIE_ICH#
CLK_PCIE_LOM
CLK_PCIE_LOM#
CLK_PCIE_VGA
CLK_PCIE_VGA#
CLK_PCIE_MINI
CLK_PCIE_MINI#
CLK_PCIE_EXPCARD
CLK_PCIE_EXPCARD#
MCH_DREFCLK
MCH_DREFCLK#
DREF_SSCLK
DREF_SSCLK#
R254 49.9_0402_1%~D
R259 49.9_0402_1%~D
R238 49.9_0402_1%~D
R247 49.9_0402_1%~D
R223 49.9_0402_1%~D
R230 49.9_0402_1%~D
R292 49.9_0402_1%~D
R291 49.9_0402_1%~D
R287 49.9_0402_1%~D
R288 49.9_0402_1%~D
R290 49.9_0402_1%~D
R289 49.9_0402_1%~D
R294 49.9_0402_1%~D5@
R293 49.9_0402_1%~D5@
R296 49.9_0402_1%~D3@
R295 49.9_0402_1%~D3@
R258 49.9_0402_1%~D
R265 49.9_0402_1%~D
R271 49.9_0402_1%~D
R273 49.9_0402_1%~D
R229 49.9_0402_1%~D1@
R237 49.9_0402_1%~D1@
R242 49.9_0402_1%~D1@
R253 49.9_0402_1%~D1@
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
12
12
12
12
12
12
DELL CONFIDENTIAL/PROPRIETARY
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
Clock Generator
LA-2881P
662Tuesday, December 13, 2005
1
of
2.0
Page 7
5
4
3
2
1
H_A#[3..31]<10>
D D
H_REQ#0<10>
H_REQ#1<10>
H_REQ#2<10>
H_REQ#3<10>
H_REQ#4<10>
H_ADSTB#0<10>
CPU_PROCHOT#
R714
1 2
1K_0402_5%~D@
1 2
1
2
H_ADSTB#1<10>
CLK_CPU_BCLK<6>
CLK_CPU_BCLK#<6>
H_ADS#<10>
H_BNR#<10>
H_BPRI#<10>
H_BR0#<10>
H_DEFER#<10>
H_DRDY#<10>
H_HIT#<10>
H_HITM#<10>
H_LOCK#<10>
H_RESET#<10>
H_RS#0<10>
H_RS#1<10>
H_RS#2<10>
H_TRDY#<10>
ITP_DBRESET#<23,38>
H_DBSY#<10>
H_DPSLP#<22>
H_DPRSTP#<22,48>
H_DPWR#<10>
H_PWRGOOD<22>
H_CPUSLP#<10,22>
H_THERMTRIP#<16>
C C
R715
2200P_0402_50V7K~D@
H_THERMDA<16>
H_THERMDC<16>
5
1 2
56_0402_5%~D
+1.05V_VCCP
75_0402_5%~D
12
R576
R718 51_0402_5%~D
C20
+1.05V_VCCP
B B
CPU_PROCHOT#<37>
Populate R718 for
Yonah B0 and forward.
A A
H_THERMDA, H_THERMDC routing together,
Trace width / Spacing = 10 / 10 mil
H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
H_ADSTB#0
H_ADSTB#1
CLK_CPU_BCLK
CLK_CPU_BCLK#
H_ADS#
H_BNR#
H_BPRI#
H_BR0#
H_DEFER#
H_DRDY#
H_HIT#
H_HITM#
H_IERR#
H_LOCK#
H_RESET#
H_RS#0
H_RS#1
H_RS#2
H_TRDY#
ITP_BPM#0
ITP_BPM#1
ITP_BPM#2
ITP_BPM#3
ITP_DBRESET#
H_DBSY#
H_DPSLP#
H_DPRSTP#
H_DPWR#
ITP_BPM#4
ITP_BPM#5
H_PWRGOOD
H_CPUSLP#
ITP_TCK
ITP_TDI H_A20M#
ITP_TDO
TEST1
TEST2
ITP_TMS
ITP_TRST#
H_THERMDA
H_THERMDC
H_THERMTRIP#
JCPUA
J4
A3#
L4
A4#
M3
A5#
K5
A6#
M1
A7#
N2
A8#
J1
A9#
N3
A10#
P5
A11#
P2
A12#
L1
A13#
P4
A14#
P1
A15#
R1
A16#
Y2
A17#
U5
A18#
R3
A19#
W6
A20#
U4
A21#
Y5
A22#
U2
A23#
R4
A24#
T5
ADDR GROUP
A25#
T3
A26#
W3
A27#
W5
A28#
Y4
A29#
W2
A30#
Y1
A31#
K3
REQ0#
H2
REQ1#
K2
REQ2#
J3
REQ3#
L5
REQ4#
L2
ADSTB0#
V4
ADSTB1#
A22
BCLK0
A21
H1
E2
G5
F1
H5
F21
G6
E4
D20
H4
B1
F3
F4
G3
G2
AD4
AD3
AD1
AC4
C20
E1
B5
E5
D24
AC2
AC1
D21
D6
D7
AC5
AA6
AB3
C26
D25
AB5
AB6
A24
A25
C7
HOST CLK
BCLK1
ADS#
BNR#
BPRI#
BR0#
DEFER#
DRDY#
HIT#
CONTROL
HITM#
IERR#
LOCK#
RESET#
RS0#
RS1#
RS2#
TRDY#
BPM0#
BPM1#
BPM2#
BPM3#
DBR#
DBSY#
DPSLP#
DPRSTP#
DPWR#
PRDY#
PREQ#
PROCHOT#
PWRGOOD
SLP#
TCK
TDI
TDO
TEST1
TEST2
TMS
TRST#
THERMAL
THERMDA
DIODE
THERMDC
THERMTRIP#
TYCO_1-1674770-2_Yonah~D
+1.05V_VCCP
4
YONAH
MISC
R721
56_0402_5%~D
1 2
DATA GROUP
LEGACY CPU
H_THERMTRIP#
D10#
D11#
D12#
D13#
D14#
D15#
D16#
D17#
D18#
D19#
D20#
D21#
D22#
D23#
D24#
D25#
D26#
D27#
D28#
D29#
D30#
D31#
D32#
D33#
D34#
D35#
D36#
D37#
D38#
D39#
D40#
D41#
D42#
D43#
D44#
D45#
D46#
D47#
D48#
D49#
D50#
D51#
D52#
D53#
D54#
D55#
D56#
D57#
D58#
D59#
D60#
D61#
D62#
D63#
DINV0#
DINV1#
DINV2#
DINV3#
DSTBN0#
DSTBN1#
DSTBN2#
DSTBN3#
DSTBP0#
DSTBP1#
DSTBP2#
DSTBP3#
A20M#
FERR#
IGNNE#
INIT#
LINT0
LINT1
STPCLK#
SMI#
H_NMI <22>
H_D#[0..63] <10>
Notes: Can be nopop on X00 board.
R725
22.6_0402_1%~D
H_RESET#
1 2
ITP_TDO
1 2
22.6_0402_1%~D
R726
CLK_CPU_ITP<6>
CLK_CPU_ITP#<6>
2
D0#
D1#
D2#
D3#
D4#
D5#
D6#
D7#
D8#
D9#
H_D#1
F24
H_D#2
E26
H_D#3
H22
H_D#4
F23
H_D#5
G25
H_D#6
E25
H_D#7
E23
H_D#8
K24
H_D#9
G24
H_D#10
J24
H_D#11
J23
H_D#12
H26
H_D#13
F26
H_D#14
K22
H_D#15
H25
H_D#16
N22
H_D#17
K25
H_D#18
P26
H_D#19
R23
H_D#20
L25
H_D#21
L22
H_D#22
L23
H_D#23
M23
H_D#24
P25
H_D#25
P22
H_D#26
P23
H_D#27
T24
H_D#28
R24
H_D#29
L26
H_D#30
T25
H_D#31
N24
H_D#32
AA23
H_D#33
AB24
H_D#34
V24
H_D#35
V26
H_D#36
W25
H_D#37
U23
H_D#38
U25
H_D#39
U22
H_D#40
AB25
H_D#41
W22
H_D#42
Y23
H_D#43
AA26
H_D#44
Y26
H_D#45
Y22
H_D#46
AC26
H_D#47
AA24
H_D#48
AC22
H_D#49
AC23
H_D#50
AB22
H_D#51
AA21
H_D#52
AB21
H_D#53
AC25
H_D#54
AD20
H_D#55
AE22
H_D#56
AF23
H_D#57
AD24
H_D#58
AE21
H_D#59
AD21
H_D#60
AE25
H_D#61
AF25
H_D#62
AF22
H_D#63
AF26
H_DINV#0
J26
H_DINV#1
M26
H_DINV#2
V23
H_DINV#3
AC20
H_DSTBN#0
H23
H_DSTBN#1
M24
H_DSTBN#2
W24
H_DSTBN#3
AD23
H_DSTBP#0
G22
H_DSTBP#1
N25
H_DSTBP#2
Y25
H_DSTBP#3
AE24
A6
H_FERR#
A5
H_IGNNE#
C4
H_INIT#
B3
H_INTR
C6
H_NMI
B4
H_STPCLK#
D5
H_SMI#
A3
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
H_DINV#0 <10>
H_DINV#1 <10>
H_DINV#2 <10>
H_DINV#3 <10>
H_DSTBN#0 <10>
H_DSTBN#1 <10>
H_DSTBN#2 <10>
H_DSTBN#3 <10>
H_DSTBP#0 <10>
H_DSTBP#1 <10>
H_DSTBP#2 <10>
H_DSTBP#3 <10>
H_A20M# <22>
H_FERR# <22>
H_IGNNE# <22>
H_INIT# <22>
H_INTR <22>
H_STPCLK# <22>
H_SMI# <22>
H_D#0
E22
+1.05V_VCCP
ITP_DBRESET#
ITP_BPM#0
ITP_BPM#1
ITP_BPM#2
ITP_BPM#3
ITP_BPM#4
ITP_BPM#5
ITP_TCK
CLK_CPU_ITP
CLK_CPU_ITP#
ITP_TCK
ITP_TRST#
ITP_TMS
ITP_TDI
+1.05V_VCCP
+3.3V_SUS
+1.05V_VCCP
29
JITP
28
VTT1
27
GND6
VTT0
26
VTAP
25
DBR#
24
DBA#
23
BPM0#
22
GND5
21
BPM1#
20
GND4
19
BPM2#
18
GND3
17
BPM3#
16
GND2
15
BPM4#
14
GND1
13
BPM5#
12
RESET#
11
FBO
10
GND0
9
BCLKP
8
BCLKN
7
TDO
6
NC2
5
TCK
4
NC1
3
TRST#
2
TMS
1
TDI
GND7
MOLEX_52435-2891_28P~D@
30
@
@
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
1
1
C695
C697
2
2
Place near JITP
R729
150_0402_5%~D
1 2
51_0402_5%~D
51_0402_5%~D
39_0402_5%~D
@
54.9_0402_1%~D
150_0402_5%~D
680_0402_5%~D
27_0402_5%~D
ITP_DBRESET#
R730
ITP_TDO
R723
H_RESET#
R733
ITP_TMS
R735
ITP_BPM#5
R734
ITP_TDI
This shall place near CPU
R732
ITP_TRST#
R731
ITP_TCK
DELL CONFIDENTIAL/PROPRIETARY
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
Yonah Processor(1/2)
LA-2881P
1
762Tuesday, December 13, 2005
2.0
of
Page 8
5
4
3
2
1
Place R719 and R722 near CPU
D D
C C
+VCC_CORE
Route VCCSENSE and VSSSENSE trace at
27.4 ohms, 50 mils spacing a nd 1 inch (max)
R719
1 2
100_0402_1%~D
R722
1 2
100_0402_1%~D
VCCSENSE
VSSSENSE
CPU_BSEL CPU_BSEL2 CPU_BSEL1
133
166
00
01
27.4_0402_1%~D
54.9_0402_1%~D
12
12
R15
R16
+1.5V_RUN
0.01U_0402_16V7K~D
C19
1
2
Close to
pin B26
CPU_BSEL0
1
1
27.4_0402_1%~D
54.9_0402_1%~D
12
R727
Resistor pl aced within
12
0.5" of CPU pin.Trace
R728
should be at least 25
mils away from any
other toggling signal.
CPU_MCH_BSEL0<6,10,12>
CPU_MCH_BSEL1<6,10>
CPU_MCH_BSEL2<6,10>
Layout Note:
COMP0,2 connect with Z0=27.4 ohm, make trace length shorter than 0.5".
B B
A A
COMP1,3 connect with Z0=55.5 ohm, make trace length shorter than 0.5".
+1.05V_VCCP
V_CPU_GTLREF
Length match within 25 mils
VCCSENSE<48>
VSSSENSE<48>
10U_0805_10V4Z~D
+1.05V_VCCP
C21
1
2
H_PSI#<48>
VID0<48>
VID1<48>
VID2<48>
VID3<48>
VID4<48>
VID5<48>
VID6<48>
V_CPU_GTLREF
+VCC_CORE
12
R716
1K_0402_1%~D
12
R717
2K_0402_1%~D
VCCSENSE
VSSSENSE
H_PSI#
VID0
VID1
VID2
VID3
VID4
VID5
VID6
CPU_MCH_BSEL0
CPU_MCH_BSEL1
CPU_MCH_BSEL2
COMP0
COMP1
COMP2
COMP3
W21
AD26
AB20
AA20
AF20
AE20
AB18
AB17
AA18
AA17
AD18
AD17
AC18
AC17
AF18
AF17
AF7
AE7
B26
K21
J21
M21
N21
T21
R21
V21
G21
AE6
AD6
AF5
AE5
AF4
AE3
AF2
AE2
B22
B23
C21
R26
U26
AF1
D22
C23
C24
AA1
AA4
AB2
AA3
T22
B25
K6
J6
M6
N6
T6
R6
V6
U1
V1
E7
D2
F6
D3
C1
M4
N5
T2
V3
B2
C3
JCPUB
VCCSENSE
VSSSENSE
VCCA
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
PSI#
VID0
VID1
VID2
VID3
VID4
VID5
VID6
GTLREF
BSEL0
BSEL1
BSEL2
COMP0
COMP1
COMP2
COMP3
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
YONAH
TYCO_1-1674770-2_Yonah~D
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
POWER, GROUNG, RESERVED SIGNALS AND NC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AB26
AA25
AD25
AE26
AB23
AC24
AF24
AE23
AA22
AD22
AC21
AF21
AB19
AA19
AD19
AC19
AF19
AE19
AB16
AA16
AD16
AC16
AF16
AE16
AB13
AA14
AD13
AC14
AF13
AE14
AB11
AA11
AD11
AC11
AF11
AE11
AB8
AA8
AD8
AC8
AF8
AE8
AA5
AD5
AC6
AF6
AB4
AC3
AF3
AE4
AB1
AA2
AD2
AE1
B6
C5
F5
E6
H6
J5
M5
L6
P6
R5
V5
U6
Y6
A4
D4
E3
H3
G4
K4
L3
P3
N4
T4
U3
Y3
W4
D1
C2
F2
G1
+VCC_CORE
AE18
AE17
AB15
AA15
AD15
AC15
AF15
AE15
AB14
AA13
AD14
AC13
AF14
AE13
AB12
AA12
AD12
AC12
AF12
AE12
AB10
AA10
AD10
AC10
AF10
AE10
JCPUC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
AB9
VCC
VCC
AA9
VCC
VCC
AD9
VCC
VCC
AC9
VCC
VCC
AF9
VCC
VCC
AE9
VCC
AB7
VCC
AA7
VCC
AD7
VCC
AC7
VCC
B20
VCC
A20
VCC
F20
VCC
E20
VCC
B18
VCC
B17
VCC
A18
VCC
A17
VCC
D18
VCC
D17
VCC
C18
VCC
C17
VCC
F18
VCC
F17
VCC
E18
VCC
E17
VCC
B15
VCC
A15
VCC
D15
VCC
C15
VCC
F15
VCC
E15
VCC
B14
VCC
A13
VCC
D14
VCC
C13
VCC
F14
VCC
E13
VCC
B12
VCC
A12
VCC
D12
VCC
C12
VCC
F12
VCC
E12
VCC
B10
VCC
B9
VCC
A10
VCC
A9
VCC
D10
VCC
D9
VCC
C10
VCC
C9
VCC
F10
VCC
F9
VCC
E10
VCC
E9
VCC
B7
VCC
A7
VCC
F7
VCC
YONAH
POWER, GROUND
TYCO_1-1674770-2_Yonah~D
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
K1
J2
M2
N1
T1
R2
V2
W1
A26
D26
C25
F25
B24
A23
D23
E24
B21
C22
F22
E21
B19
A19
D19
C19
F19
E19
B16
A16
D16
C16
F16
E16
B13
A14
D13
C14
F13
E14
B11
A11
D11
C11
F11
E11
B8
A8
D8
C8
F8
E8
G26
K26
J25
M25
N26
T26
R25
V25
W26
H24
G23
K23
L24
P24
N23
T23
U24
Y24
W23
H21
J22
M22
L21
P21
R22
V22
U21
Y21
Layout close CPU PIN AD26
0.5 inch (max)
5
4
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
DELL CONFIDENTIAL/PROPRIETARY
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
Yonah Processor(2/2)
LA-2881P
862Tuesday, December 13, 2005
1
of
2.0
Page 9
5
+VCC_CORE
D D
C C
Place these inside
socket cavity on L8
(North side
Secondary)
Place these inside
socket cavity on L8
(North side
Secondary)
Place these inside
socket cavity on L8
(North side
Secondary)
Place these inside
socket cavity on L8
(North side
Secondary)
1
2
+VCC_CORE
1
2
+VCC_CORE
1
2
+VCC_CORE
1
2
C5
10U_0805_4VAM~D
C7
10U_0805_4VAM~D
C688
10U_0805_4VAM~D
C669
10U_0805_4VAM~D
4
1
C8
10U_0805_4VAM~D
2
1
C4
10U_0805_4VAM~D
2
1
C682
10U_0805_4VAM~D
2
1
C663
10U_0805_4VAM~D
2
1
C11
10U_0805_4VAM~D
2
1
C687
10U_0805_4VAM~D
2
1
C678
10U_0805_4VAM~D
2
1
C664
10U_0805_4VAM~D
2
1
C13
10U_0805_4VAM~D
2
1
C681
10U_0805_4VAM~D
2
1
C675
10U_0805_4VAM~D
2
1
C689
10U_0805_4VAM~D
2
3
1
C16
10U_0805_4VAM~D
2
1
C677
10U_0805_4VAM~D
2
1
C673
10U_0805_4VAM~D
2
1
C686
10U_0805_4VAM~D
2
1
C18
10U_0805_4VAM~D
2
1
C674
10U_0805_4VAM~D
2
1
C671
10U_0805_4VAM~D
2
1
C658
10U_0805_4VAM~D
2
1
C17
10U_0805_4VAM~D
2
1
C672
10U_0805_4VAM~D
2
10uF 0805 X6S
1
C15
10U_0805_4VAM~D
2
1
C670
10U_0805_4VAM~D
2
2
1
C12
10U_0805_4VAM~D
2
1
C668
10U_0805_4VAM~D
2
1
C10
10U_0805_4VAM~D
2
1
C662
10U_0805_4VAM~D
2
1
High Frequence Decoupling
Near VCORE regulator
+VCC_CORE
330U_D_2VM_R6~D
1
South Side Secondary
B B
+1.05V_VCCP
1
+
330U_D2E_2.5VM~D@
A A
C657
2
CRB was 270uF
1
C659
0.1U_0402_10V7K~D
2
+
2
6mOhm
PS CAP
C685
6mOhm
PS CAP
1
C660
0.1U_0402_10V7K~D
2
@
330U_D_2VM_R6~D
330U_D_2VM_R6~D
1
C667
+
2
6mOhm
PS CAP
1
C666
+
2
1
C661
2
330U_D_2VM_R6~D
1
C665
+
2
6mOhm
6mOhm
PS CAP
PS CAP
0.1U_0402_10V7K~D
@
330U_D_2VM_R6~D
1
C676
+
2
1
C690
0.1U_0402_10V7K~D
2
330U_D_2VM_R6~D
1
C683
North Side Secondary
+
2
6mOhm
PS CAP
1
C691
0.1U_0402_10V7K~D
2
ESR <= 1.5m ohm
1
C692
0.1U_0402_10V7K~D
2
Place these inside
socket cavity on L8
(North side
Secondary)
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
CPU Bypass
LA-2881P
962Tuesday, December 13, 2005
1
2.0
of
Page 10
5
4
3
2
1
ZUMA use 945GM ( P/N: SA0000059GL )
ZRS use 945PM ( P/N: SA00000KDBL)
54.9_0402_1%~D
H_D#[0..63]<7>
+1.05V_VCCP
12
R60
24.9_0402_1%~D
12
R56
54.9_0402_1%~D
12
R61
H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
H_VREF
H_XRCOMP
H_XSCOMP
H_YRCOMP
H_YSCOMP
H_SWNG0
H_SWNG1
12
R59
24.9_0402_1%~D
200_0402_1%~D
5
U6A
F1
HD0#
J1
HD1#
H1
HD2#
J6
HD3#
H3
HD4#
K2
HD5#
G1
HD6#
G2
HD7#
K9
HD8#
K1
HD9#
K7
HD10#
J8
HD11#
H4
HD12#
J3
HD13#
K11
HD14#
G4
HD15#
T10
HD16#
W11
HD17#
T3
HD18#
U7
HD19#
U9
HD20#
U11
HD21#
T11
HD22#
W9
HD23#
T1
HD24#
T8
HD25#
T4
HD26#
W7
HD27#
U5
HD28#
T9
HD29#
W6
HD30#
T5
HD31#
AB7
HD32#
AA9
HD33#
W4
HD34#
W3
HD35#
Y3
HD36#
Y7
HD37#
W5
HD38#
Y10
HD39#
AB8
HD40#
W2
HD41#
AA4
HD42#
AA7
HD43#
AA2
HD44#
AA6
HD45#
AA10
HD46#
Y8
HD47#
AA1
HD48#
AB4
HD49#
AC9
HD50#
AB11
HD51#
AC11
HD52#
AB3
HD53#
AC2
HD54#
AD1
HD55#
AD9
HD56#
AC1
HD57#
AD7
HD58#
AC6
HD59#
AB5
HD60#
AD10
HD61#
AD4
HD62#
AC8
HD63#
J13
HVREF0
K13
HVREF1
E1
HXRCOMP
E2
HXSCOMP
Y1
HYRCOMP
U1
HYSCOMP
E4
HXSWING
W1
HYSWING
CALISTOGA A3 _ FCBGA1466~D
12
R684
100_0402_1%~D
H_VREF H_SWNG0 H_SWNG1
R689
0.1U_0402_16V4Z~D
12
1
C623
2
HOST
12
R700
221_0402_1%~D
100_0402_1%~D
12
R695
HA3#
HA4#
HA5#
HA6#
HA7#
HA8#
HA9#
HA10#
HA11#
HA12#
HA13#
HA14#
HA15#
HA16#
HA17#
HA18#
HA19#
HA20#
HA21#
HA22#
HA23#
HA24#
HA25#
HA26#
HA27#
HA28#
HA29#
HA30#
HA31#
HREQ#0
HREQ#1
HREQ#2
HREQ#3
HREQ#4
HADSTB#0
HADSTB#1
HCLKN
HCLKP
HDSTBN#0
HDSTBN#1
HDSTBN#2
HDSTBN#3
HDSTBP#0
HDSTBP#1
HDSTBP#2
HDSTBP#3
HDINV#0
HDINV#1
HDINV#2
HDINV#3
HCPURST#
HADS#
HTRDY#
HDPWR#
HDRDY#
HDEFER#
HHITM#
HHIT#
HLOCK#
HBREQ0#
HBNR#
HBPRI#
HDBSY#
HCPUSLP#
HRS0#
HRS1#
HRS2#
0.1U_0402_16V4Z~D
1
2
H9
C9
E11
G11
F11
G12
F9
H11
J12
G14
D9
J14
H13
J15
F14
D12
A11
C11
A12
A13
E13
G13
F12
B12
B14
C12
A14
C14
D14
D8
G8
B8
F8
A8
B9
C13
AG1
AG2
K4
T7
Y5
AC4
K3
T6
AA5
AC5
J7
W8
U3
AB10
B7
E8
E7
J9
H8
C3
D4
D3
B3
C7
C6
F6
A7
E3
B4
E6
D6
+1.05V_VCCP+1.05V_VCCP+1.05V_VCCP
100_0402_1%~D
C634
4
H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
H_ADSTB#0
H_ADSTB#1
CLK_MCH_BCLK#
CLK_MCH_BCLK
H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3
H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3
H_DINV#0
H_DINV#1
H_DINV#2
H_DINV#3
H_RESET#
H_ADS#
H_TRDY#
H_DPWR#
H_DRDY#
H_DEFER#
H_HITM#
H_HIT#
H_LOCK#
H_BR0#
H_BNR#
H_BPRI#
H_DBSY#
H_CPUSLP#
H_RS#0
H_RS#1
H_RS#2
12
R55
221_0402_1%~D
12
R58
1
2
0.1U_0402_16V4Z~D
D D
C C
B B
Layout Note:
H_XRCOMP & H_YRCOMP / H_SWNG0 &
H_SWNG1 trace width and spacing is 10/20
A A
H_REQ#0 <7>
H_REQ#1 <7>
H_REQ#2 <7>
H_REQ#3 <7>
H_REQ#4 <7>
H_ADSTB#0 <7>
H_ADSTB#1 <7>
CLK_MCH_BCLK# <6>
CLK_MCH_BCLK <6>
H_DSTBN#0 <7>
H_DSTBN#1 <7>
H_DSTBN#2 <7>
H_DSTBN#3 <7>
H_DSTBP#0 <7>
H_DSTBP#1 <7>
H_DSTBP#2 <7>
H_DSTBP#3 <7>
H_DINV#0 <7>
H_DINV#1 <7>
H_DINV#2 <7>
H_DINV#3 <7>
H_RESET# <7>
H_ADS# <7>
H_TRDY# <7>
H_DPWR# <7>
H_DRDY# <7>
H_DEFER# <7>
H_HITM# <7>
H_HIT# <7>
H_LOCK# <7>
H_BR0# <7>
H_BNR# <7>
H_BPRI# <7>
H_DBSY# <7>
H_CPUSLP# <7,22>
H_RS#0 <7>
H_RS#1 <7>
H_RS#2 <7>
C58
H_A#[3..31] <7>
U6B
AE35
DMIRXN0
AF39
DMIRXN1
AG35
DMIRXN2
AH39
DMIRXN3
AC35
DMIRXP0
AE39
DMIRXP1
AF35
DMIRXP2
AG39
DMIRXP3
AE37
DMITXN0
AF41
DMITXN1
AG37
DMITXN2
AH41
DMITXN3
AC37
DMITXP0
AE41
DMITXP1
AF37
DMITXP2
AG41
DMITXP3
AY35
SM_CK0
AR1
SM_CK1
AW7
SM_CK2
AW40
SM_CK3
AW35
SM_CK0#
AT1
SM_CK1#
AY7
SM_CK2#
AY40
SM_CK3#
AU20
SM_CKE0
AT20
SM_CKE1
BA29
SM_CKE2
AY29
SM_CKE3
AW13
SM_CS0#
AW12
SM_CS1#
AY21
SM_CS2#
AW21
SM_CS3#
AL20
SM_OCDCOMP0
AF10
SM_OCDCOMP1
BA13
SM_ODT0
BA12
SM_ODT1
AY20
SM_ODT2
AU21
SM_ODT3
AV9
SM_RCOMPN
AT9
SM_RCOMPP
AK1
SM_VREF0
AK41
SM_VREF1
G28
PM_BMBUSY#
F25
PM_EXTTS0#
H26
PM_EXTTS1#
G6
PM_THERMTRIP#
AH33
PWROK
AH34
RSTIN#
K28
ICH_SYNC#
CALISTOGA A3 _ FCBGA1466~D
1
C702
0.1U_0402_16V4Z~D
2
T24
T25
M_ODT0<18>
M_ODT1<18>
M_ODT2<17>
M_ODT3<17>
+0.9V_DDR_REF
R683
0_0402_5%~D
DMI_MRX_ITX_N0
DMI_MRX_ITX_N1
DMI_MRX_ITX_N2
DMI_MRX_ITX_N3
DMI_MRX_ITX_P0
DMI_MRX_ITX_P1
DMI_MRX_ITX_P2
DMI_MRX_ITX_P3
DMI_MTX_IRX_N0
DMI_MTX_IRX_N1
DMI_MTX_IRX_N2
DMI_MTX_IRX_N3
DMI_MTX_IRX_P0
DMI_MTX_IRX_P1
DMI_MTX_IRX_P2
DMI_MTX_IRX_P3
M_CLK_DDR0
M_CLK_DDR1
M_CLK_DDR2
M_CLK_DDR3
M_CLK_DDR#0
M_CLK_DDR#1
M_CLK_DDR#2
M_CLK_DDR#3
DDR_CKE0_DIMMA
DDR_CKE1_DIMMA
DDR_CKE2_DIMMB
DDR_CKE3_DIMMB
DDR_CS0_DIMMA#
DDR_CS1_DIMMA#
DDR_CS2_DIMMB#
DDR_CS3_DIMMB#
M_OCDOCMP0
M_OCDOCMP1
M_ODT0
M_ODT1
M_ODT2
M_ODT3
SMRCOMPN
SMRCOMPP
PM_BMBUSY#
PM_EXTTS#0
PM_EXTTS#1_R
THERMTRIP_MCH#
ICH_PWRGD
PLTRST1_R#
MCH_ICH_SYNC#
+0.9V_DDR_REF
1
C146
0.1U_0402_16V4Z~D
2
DMI_MRX_ITX_N0<23>
DMI_MRX_ITX_N1<23>
DMI_MRX_ITX_N2<23>
DMI_MRX_ITX_N3<23>
DMI_MRX_ITX_P0<23>
DMI_MRX_ITX_P1<23>
DMI_MRX_ITX_P2<23>
DMI_MRX_ITX_P3<23>
DMI_MTX_IRX_N0<23>
DMI_MTX_IRX_N1<23>
DMI_MTX_IRX_N2<23>
DMI_MTX_IRX_N3<23>
DMI_MTX_IRX_P0<23>
DMI_MTX_IRX_P1<23>
DMI_MTX_IRX_P2<23>
DMI_MTX_IRX_P3<23>
M_CLK_DDR0<18>
M_CLK_DDR1<18>
M_CLK_DDR2<17>
M_CLK_DDR3<17>
M_CLK_DDR#0<18>
M_CLK_DDR#1<18>
M_CLK_DDR#2<17>
M_CLK_DDR#3<17>
DDR_CKE0_DIMMA<18>
DDR_CKE1_DIMMA<18>
DDR_CKE2_DIMMB<17>
DDR_CKE3_DIMMB<17>
DDR_CS0_DIMMA#<18>
DDR_CS1_DIMMA#<18>
DDR_CS2_DIMMB#<17>
DDR_CS3_DIMMB#<17>
+1.8V_SUS
R681 80.6_0402_1%~D
1 2
1 2
R687 80.6_0402_1%~D
PM_BMBUSY#<23>
PM_EXTTS#0<18>
THERMTRIP_MCH#<16>
ICH_PWRGD<23,40>
PLTRST1#<21,23,30>
DPRSLPVR<23,48>
+0.9V_DDR_REF<17,18,47>
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
12
R625 100_0402_1%~D
MCH_ICH_SYNC#<21>
DPRSLPVR PM_EXTTS#1_R
Place Close To
AK1 and AK41
DMI
2
CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG16
CFG17
CFG
CFG18
CFG19
CFG20
G_CLKP
G_CLKN
D_REF_CLKN
D_REF_CLKP
CLKNC
D_REF_SSCLKN
D_REF_SSCLKP
DDR MUXING
PM
CLK_REQ#
RESERVED1
RESERVED2
RESERVED3
RESERVED4
RESERVED5
RESERVED6
RESERVED7
RESERVED8
RESERVED9
RESERVED10
RESERVED11
RESERVED12
RESERVED13
RESERVED
NC10
NC11
NC12
NC13
NC14
NC15
NC16
NC17
NC18
Description at page12
Note :
CFG3:17 has
internal pullup,
CFG18:19 has
internal pulldown
CPU_MCH_BSEL0
NC0
NC1
NC2
NC3
NC4
NC5
NC6
NC7
NC8
NC9
K16
CPU_MCH_BSEL1
K18
CPU_MCH_BSEL2
J18
CFG3
F18
CFG4
E15
CFG5
F15
CFG6
E18
CFG7
D19
CFG8
D16
CFG9
G16
CFG10
E16
CFG11
D15
CFG12
G15
CFG13
K15
CFG14
C15
CFG15
H16
CFG16
G18
CFG17
H15
CFG18
J25
CFG19
K27
CFG20
J26
CLK_MCH_3GPLL
AG33
CLK_MCH_3GPLL#
AF33
MCH_DREFCLK#
A27
MCH_DREFCLK
A26
DREF_SSCLK#
C40
DREF_SSCLK
D41
CLK_3GPLLREQ#
H32
A3
A39
A4
A40
AW1
AW41
AY1
BA1
Pop R92/R96/R114/R115 for discrete only
BA2
BA3
BA39
BA40
BA41
MCH_DREFCLK
C1
AY41
DREF_SSCLK
B2
B41
MCH_DREFCLK#
C41
D1
DREF_SSCLK#
T32
R32
F3
F7
AG11
AF11
H7
J19
A41
A34
D28
D27
A35
PM_EXTTS#0
PM_EXTTS#1_R
THERMTRIP_MCH#
CPU_MCH_BSEL0 <6,8,12>
CPU_MCH_BSEL1 <6,8>
CPU_MCH_BSEL2 <6,8>
T17
T22
CFG5 <12>
CFG6 <12>
CFG7 <12>
T20
CFG9 <12>
CFG10 <12>
CFG11 <12>
CFG12 <12>
CFG13 <12>
T21
T16
CFG16 <12>
T19
CFG18 <12>
CFG19 <12>
CFG20 <12>
CLK_MCH_3GPLL <6>
CLK_MCH_3GPLL# <6>
MCH_DREFCLK# <6>
MCH_DREFCLK <6>
DREF_SSCLK# <6>
DREF_SSCLK <6>
CLK_3GPLLREQ# <6>
These connection for UMA only
+1.5V_RUN
1 2
R92 0_0402_5%~D3@
1 2
R115 0_0402_5%~D3@
1 2
R96 0_0402_5%~D3@
1 2
R114 0_0402_5%~D3@
+3.3V_RUN
R643
12
10K_0402_5%~D
R623
12
10K_0402_5%~D@
R690
1 2
75_0402_5%~D
+1.05V_VCCP
DELL CONFIDENTIAL/PROPRIETARY
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
Calistoga(1 of 6)
LA-2881P
10 62Tuesday, December 13, 2005
1
of
2.0
Page 11
5
D D
4
3
2
1
DDR_A_BS0<18>
DDR_A_BS1<18>
DDR_A_BS2<18>
DDR_A_DM[0..7]<18>
DDR_A_DQS[0..7]<18>
C C
DDR_A_DQS#[0..7]<18>
DDR_A_MA[0..13]<18>
B B
DDR_A_CAS#<18>
DDR_A_RAS#<18>
DDR_A_WE#<18>
DDR_A_BS0
DDR_A_BS1
DDR_A_BS2
DDR_A_DM0
DDR_A_DM1
DDR_A_DM2
DDR_A_DM3
DDR_A_DM4
DDR_A_DM5
DDR_A_DM6
DDR_A_DM7
DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7
DDR_A_DQS#0
DDR_A_DQS#1
DDR_A_DQS#2
DDR_A_DQS#3
DDR_A_DQS#4
DDR_A_DQS#5
DDR_A_DQS#6
DDR_A_DQS#7
DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_CAS#
DDR_A_RAS#
DDR_A_WE#
SA_RCVENIN#
T13
SA_RCVENOUT#
T14
U6D
AU12
SA_BS0
AV14
SA_BS1
BA20
SA_BS2
AJ33
SA_DM0
AM35
SA_DM1
AL26
SA_DM2
AN22
SA_DM3
AM14
SA_DM4
AL9
SA_DM5
AR3
SA_DM6
AH4
SA_DM7
AK33
SA_DQS0
AT33
SA_DQS1
AN28
SA_DQS2
AM22
SA_DQS3
AN12
SA_DQS4
AN8
SA_DQS5
AP3
SA_DQS6
AG5
SA_DQS7
AK32
SA_DQS0#
AU33
SA_DQS1#
AN27
SA_DQS2#
AM21
SA_DQS3#
AM12
SA_DQS4#
AL8
SA_DQS5#
AN3
SA_DQS6#
AH5
SA_DQS7#
AY16
SA_MA0
AU14
SA_MA1
AW16
SA_MA2
BA16
SA_MA3
BA17
SA_MA4
AU16
SA_MA5
AV17
SA_MA6
AU17
SA_MA7
AW17
SA_MA8
AT16
SA_MA9
AU13
SA_MA10
AT17
SA_MA11
AV20
SA_MA12
AV12
SA_MA13
AY13
SA_CAS#
AW14
SA_RAS#
AY14
SA_WE#
AK23
SA_RCVENIN#
AK24
SA_RCVENOUT#
CALISTOGA A3 _ FCBGA1466~D
SA_DQ0
SA_DQ1
SA_DQ2
SA_DQ3
SA_DQ4
SA_DQ5
SA_DQ6
SA_DQ7
SA_DQ8
SA_DQ9
SA_DQ10
SA_DQ11
SA_DQ12
SA_DQ13
SA_DQ14
SA_DQ15
SA_DQ16
SA_DQ17
SA_DQ18
SA_DQ19
SA_DQ20
SA_DQ21
SA_DQ22
SA_DQ23
SA_DQ24
SA_DQ25
SA_DQ26
SA_DQ27
SA_DQ28
SA_DQ29
SA_DQ30
SA_DQ31
SA_DQ32
SA_DQ33
SA_DQ34
SA_DQ35
SA_DQ36
SA_DQ37
SA_DQ38
SA_DQ39
DDR SYS MEMORY A
SA_DQ40
SA_DQ41
SA_DQ42
SA_DQ43
SA_DQ44
SA_DQ45
SA_DQ46
SA_DQ47
SA_DQ48
SA_DQ49
SA_DQ50
SA_DQ51
SA_DQ52
SA_DQ53
SA_DQ54
SA_DQ55
SA_DQ56
SA_DQ57
SA_DQ58
SA_DQ59
SA_DQ60
SA_DQ61
SA_DQ62
SA_DQ63
AJ35
AJ34
AM31
AM33
AJ36
AK35
AJ32
AH31
AN35
AP33
AR31
AP31
AN38
AM36
AM34
AN33
AK26
AL27
AM26
AN24
AK28
AL28
AM24
AP26
AP23
AL22
AP21
AN20
AL23
AP24
AP20
AT21
AR12
AR14
AP13
AP12
AT13
AT12
AL14
AL12
AK9
AN7
AK8
AK7
AP9
AN9
AT5
AL5
AY2
AW2
AP1
AN2
AV2
AT3
AN1
AL2
AG7
AF9
AG4
AF6
AG9
AH6
AF4
AF8
DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63
DDR_B_BS0<17>
DDR_B_BS1<17>
DDR_B_BS2<17>
DDR_B_DM[0..7]<17>
DDR_B_DQS[0..7]<17>
DDR_B_DQS#[0..7]<17>
DDR_B_MA[0..13]<17>
DDR_B_CAS#<17>
DDR_B_RAS#<17>
DDR_B_WE#<17>
DDR_B_BS0
DDR_B_BS1
DDR_B_BS2
DDR_B_DM0
DDR_B_DM1
DDR_B_DM2
DDR_B_DM3
DDR_B_DM4
DDR_B_DM5
DDR_B_DM6
DDR_B_DM7
DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4
DDR_B_DQS5
DDR_B_DQS6
DDR_B_DQS7
DDR_B_DQS#0
DDR_B_DQS#1
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS#4
DDR_B_DQS#5
DDR_B_DQS#6
DDR_B_DQS#7
DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13
DDR_B_CAS#
DDR_B_RAS#
DDR_B_WE#
SB_RCVENIN#
SB_RCVENOUT#
T18
T15
Add a VIAAdd a VIA
U6E
AT24
SB_BS0
AV23
SB_BS1
AY28
SB_BS2
AK36
SB_DM0
AR38
SB_DM1
AT36
SB_DM2
BA31
SB_DM3
AL17
SB_DM4
AH8
SB_DM5
BA5
SB_DM6
AN4
SB_DM7
AM39
SB_DQS0
AT39
SB_DQS1
AU35
SB_DQS2
AR29
SB_DQS3
AR16
SB_DQS4
AR10
SB_DQS5
AR7
SB_DQS6
AN5
SB_DQS7
AM40
SB_DQS0#
AU39
SB_DQS1#
AT35
SB_DQS2#
AP29
SB_DQS3#
AP16
SB_DQS4#
AT10
SB_DQS5#
AT7
SB_DQS6#
AP5
SB_DQS7#
AY23
SB_MA0
AW24
SB_MA1
AY24
SB_MA2
AR28
SB_MA3
AT27
SB_MA4
AT28
SB_MA5
AU27
SB_MA6
AV28
SB_MA7
AV27
SB_MA8
AW27
SB_MA9
AV24
SB_MA10
BA27
SB_MA11
AY27
SB_MA12
AR23
SB_MA13
AR24
SB_CAS#
AU23
SB_RAS#
AR27
SB_WE#
AK16
SB_RCVENIN#
AK18
SB_RCVENOUT#
CALISTOGA A3 _ FCBGA1466~D
AK39
SB_DQ0
AJ37
SB_DQ1
AP39
SB_DQ2
AR41
SB_DQ3
AJ38
SB_DQ4
AK38
SB_DQ5
AN41
SB_DQ6
AP41
SB_DQ7
AT40
SB_DQ8
AV41
SB_DQ9
AU38
SB_DQ10
AV38
SB_DQ11
AP38
SB_DQ12
AR40
SB_DQ13
AW38
SB_DQ14
AY38
SB_DQ15
BA38
SB_DQ16
AV36
SB_DQ17
AR36
SB_DQ18
AP36
SB_DQ19
BA36
SB_DQ20
AU36
SB_DQ21
AP35
SB_DQ22
AP34
SB_DQ23
AY33
SB_DQ24
BA33
SB_DQ25
AT31
SB_DQ26
AU29
SB_DQ27
AU31
SB_DQ28
AW31
SB_DQ29
AV29
SB_DQ30
AW29
SB_DQ31
AM19
SB_DQ32
AL19
SB_DQ33
AP14
SB_DQ34
AN14
SB_DQ35
AN17
SB_DQ36
AM16
SB_DQ37
AP15
SB_DQ38
AL15
SB_DQ39
SB_DQ40
SB_DQ41
SB_DQ42
SB_DQ43
SB_DQ44
SB_DQ45
SB_DQ46
SB_DQ47
SB_DQ48
SB_DQ49
SB_DQ50
SB_DQ51
SB_DQ52
SB_DQ53
SB_DQ54
SB_DQ55
SB_DQ56
SB_DQ57
SB_DQ58
SB_DQ59
SB_DQ60
SB_DQ61
SB_DQ62
SB_DQ63
AJ11
AH10
AJ9
AN10
AK13
AH11
AK10
AJ8
BA10
AW10
BA4
AW4
AY10
AY9
AW5
AY5
AV4
AR5
AK4
AK3
AT4
AK5
AJ5
AJ3
DDR SYS MEMORY B
DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63
DDR_B_D[0..63] <17>DDR_A_D[0..63] <18>
A A
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
Calistogo(2 of 6)
LA-2881P
11 62Tuesday, December 13, 2005
1
2.0
of
Page 12
5
No connection for discrete
SDVO_CTRLDATA<19>
D D
+3.3V_RUN
C705
0.1U_0402_16V4Z~D1@
BIA_PWM<19,20,38>
C C
12
4
O
TV_CVBS_NB<20>
TV_Y_NB<20>
TV_C_NB<20>
150_0402_1%~D1@
SDVO_CTRLCLK<19>
LCD_A0+<20>
LCD_A1+<20>
LCD_A2+<20>
LCD_A0-<20>
LCD_A1-<20>
LCD_A2-<20>
LCD_B0+<20>
LCD_B1+<20>
LCD_B2+<20>
LCD_B0-<20>
LCD_B1-<20>
LCD_B2-<20>
LCD_ACLK+<20>
LCD_ACLK-<20>
LCD_BCLK+<20>
LCD_BCLK-<20>
5
R112 0_0402_5%~D1@
1
P
IN1
2
IN2
G
3
R86
12
150_0402_1%~D1@
PANEL_BKEN<20>
U49
1@
74AHC1G08GW_SOT353-5~D
R629 1.5K_0402_1%~D1@
R635 0_0402_5%~D1@
R85
R80
12
12
4.99K_0402_1%~D1@
150_0402_1%~D1@
Close to U6.J20
No connection for discrete
VSYNC_NB<20>
HSYNC_NB<20>
BLU_NB<20>
GRN_NB<20>
RED_NB<20>
B B
Close to U6.J22
R647
255_0402_1%~D1@
Trace CRT_IREF should be at
least 20 miles away from any
other toggling signal.
Connect to +1.5V_RUN for discrete
+1.5V_RUN
R77 0_0402_5%~D3@
R82 0_0402_5%~D3@
R83 0_0402_5%~D3@
R649 0_0402_5%~D3@
R669 0_0402_5%~D3@
A A
Connect to GND for discrete
R644 0_0402_5%~D3@
R650 0_0402_5%~D3@
12
12
12
12
12
12
12
5
TV_CVBS_NB
TV_Y_NB
TV_C_NB
TVIREF
TV_IRTN
VSYNC_NB
HSYNC_NB
SDVO_CTRLDATA
SDVO_CTRLCLK
LCD_A0+
LCD_A1+
LCD_A2+
LCD_A0LCD_A1LCD_A2-
LCD_B0+
LCD_B1+
LCD_B2+
LCD_B0LCD_B1LCD_B2LCD_ACLK+
LCD_ACLKLCD_BCLK+
LCD_BCLK-
BIA_PWM_MCH
12
PANEL_BKEN
LCTLA_CLK
LCTLB_DATA
LDDC_CLK
LDDC_DATA
ENVDD<20>
12
ENVDD
L_IBG
12
LVREF
12
TV_CVBS_NB
TV_Y_NB
TV_C_NB
TVIREF
TV_IRTN
R648
12
0_0402_5%~D1@
R674
G_CLK_DDC2
G_DAT_DDC2
VSYNC_NB
HSYNC_NB
BLU_NB
CRT_RGB#
GRN_NB
RED_NB
CRT_IREF
12
Connect to +1.05V for discrete
+1.05V_VCCP
R645 0_0402_5%~D3@
R651 0_0402_5%~D3@
R656 0_0402_5%~D3@
R654 0_0402_5%~D3@
R661 0_0402_5%~D3@
R662 0_0402_5%~D1@
U6C
H27
SDVOCTRL_DATA
H28
SDVOCTRL_CLK
B37
LA_DATA0
B34
LA_DATA1
A36
LA_DATA2
C37
LA_DATA#0
B35
LA_DATA#1
A37
LA_DATA#2
F30
LB_DATA0
D29
LB_DATA1
F28
LB_DATA2
G30
LB_DATA#0
D30
LB_DATA#1
F29
LB_DATA#2
A32
LA_CLK
A33
LA_CLK#
E26
LB_CLK
E27
LB_CLK#
D32
LBKLT_CTL
J30
LBKLT_EN
H30
LCTLA_CLK
H29
LCTLB_DATA
G26
LDDC_CLK
G25
LDDC_DATA
F32
LVDD_EN
B38
LIBG
C35
LVBG
C33
LVREFH
C32
LVREFL
A16
TVDAC_A
C18
TVDAC_B
A19
TVDAC_C
J20
TV_IREF
B16
TV_IRTNA
B18
TV_IRTNB
B19
TV_IRTNC
J29
TV_DCONSEL1
K30
TV_DCONSEL0
C26
DDCCLK
C25
DDCDATA
H23
VSYNC
G23
HSYNC
E23
BLUE
D23
BLUE#
C22
GREEN
B22
GREEN#
A21
RED
B21
RED#
J22
CRT_IREF
CALISTOGA A3 _ FCBGA1466~D
BLU_NB
12
GRN_NB
12
RED_NB
12
CRT_IREF
12
CRT_RGB#
12
12
4
R113
24.9_0402_1%~D
PEGCOMP
D40
EXP_COMPI
EXP_RXN0
EXP_RXN1
EXP_RXN2
EXP_RXN3
EXP_RXN4
EXP_RXN5
EXP_RXN6
EXP_RXN7
EXP_RXN8
EXP_RXN9
EXP_RXN10
EXP_RXN11
EXP_RXN12
EXP_RXN13
EXP_RXN14
EXP_RXN15
EXP_RXP0
EXP_RXP1
EXP_RXP2
EXP_RXP3
EXP_RXP4
EXP_RXP5
EXP_RXP6
EXP_RXP7
EXP_RXP8
EXP_RXP9
EXP_RXP10
EXP_RXP11
EXP_RXP12
EXP_RXP13
EXP_RXP14
EXP_RXP15
EXP_TXN0
EXP_TXN1
EXP_TXN2
EXP_TXN3
EXP_TXN4
EXP_TXN5
EXP_TXN6
EXP_TXN7
EXP_TXN8
EXP_TXN9
EXP_TXN10
EXP_TXN11
EXP_TXN12
EXP_TXN13
EXP_TXN14
EXP_TXN15
EXP_TXP0
EXP_TXP1
EXP_TXP2
EXP_TXP3
EXP_TXP4
EXP_TXP5
EXP_TXP6
EXP_TXP7
EXP_TXP8
EXP_TXP9
EXP_TXP10
EXP_TXP11
EXP_TXP12
EXP_TXP13
EXP_TXP14
EXP_TXP15
D38
F34
G38
H34
J38
L34
M38
N34
P38
R34
T38
V34
W38
Y34
AA38
AB34
AC38
D34
F38
G34
H38
J34
L38
M34
N38
P34
R38
T34
V38
W34
Y38
AA34
AB38
F36
G40
H36
J40
L36
M40
N36
P40
R36
T40
V36
W40
Y36
AA40
AB36
AC40
D36
F40
G36
H40
J36
L40
M36
N40
P36
R40
T36
V40
W36
Y40
AA36
AB40
RED_NB
GRN_NB
BLU_NB
LCTLA_CLK
LCTLB_DATA
EXP_COMPO
LVDS
TV CRT
PCI-EXPRESS GRAPHICS
1@ is for UMA Implemetation.
3@ is for Discrete Implementation.
1 2
R657 150_0402_1%~D1@
1 2
R652 150_0402_1%~D1@
1 2
R646 150_0402_1%~D1@
+3.3V_RUN
1 2
R637 10K_0402_5%~D1@
1 2
R639 10K_0402_5%~D1@
1 2
PEG_MRX_GTX_N0
PEG_MRX_GTX_N1
PEG_MRX_GTX_N2
PEG_MRX_GTX_N3
PEG_MRX_GTX_N4
PEG_MRX_GTX_N5
PEG_MRX_GTX_N6
PEG_MRX_GTX_N7
PEG_MRX_GTX_N8
PEG_MRX_GTX_N9
PEG_MRX_GTX_N10
PEG_MRX_GTX_N11
PEG_MRX_GTX_N12
PEG_MRX_GTX_N13
PEG_MRX_GTX_N14
PEG_MRX_GTX_N15
PEG_MRX_GTX_P0
PEG_MRX_GTX_P1
PEG_MRX_GTX_P2
PEG_MRX_GTX_P3
PEG_MRX_GTX_P4
PEG_MRX_GTX_P5
PEG_MRX_GTX_P6
PEG_MRX_GTX_P7
PEG_MRX_GTX_P8
PEG_MRX_GTX_P9
PEG_MRX_GTX_P10
PEG_MRX_GTX_P11
PEG_MRX_GTX_P12
PEG_MRX_GTX_P13
PEG_MRX_GTX_P14
PEG_MRX_GTX_P15
PEG_MTX_GRX_C_N0
PEG_MTX_GRX_C_N1
PEG_MTX_GRX_C_N2
PEG_MTX_GRX_C_N3
PEG_MTX_GRX_C_N4
PEG_MTX_GRX_C_N5
PEG_MTX_GRX_C_N6
PEG_MTX_GRX_C_N7
PEG_MTX_GRX_C_N8
PEG_MTX_GRX_C_N9
PEG_MTX_GRX_C_N10
PEG_MTX_GRX_C_N11
PEG_MTX_GRX_C_N12
PEG_MTX_GRX_C_N13
PEG_MTX_GRX_C_N14
PEG_MTX_GRX_C_N15
PEG_MTX_GRX_C_P0
PEG_MTX_GRX_C_P1
PEG_MTX_GRX_C_P2
PEG_MTX_GRX_C_P3
PEG_MTX_GRX_C_P4
PEG_MTX_GRX_C_P5
PEG_MTX_GRX_C_P6
PEG_MTX_GRX_C_P7
PEG_MTX_GRX_C_P8
PEG_MTX_GRX_C_P9
PEG_MTX_GRX_C_P10
PEG_MTX_GRX_C_P11
PEG_MTX_GRX_C_P12
PEG_MTX_GRX_C_P13
PEG_MTX_GRX_C_P14
PEG_MTX_GRX_C_P15
3
+1.5V_RUN_PCIE
PEG_MRX_GTX_N[0..15]
PEG_MRX_GTX_P[0..15]
PEG_MTX_GRX_C_N[0..15]
PEG_MTX_GRX_C_P[0..15]
+3.3V_RUN
R622
NOTE: For A Platform That Support Both
Integrated and Down Video Solution, A
Translation Circuit Could Be Needed At
LDDC_CLK and LDDC_DATA signals.
PEG_MRX_GTX_N[0..15] <19>
PEG_MRX_GTX_P[0..15] <19>
PEG_MTX_GRX_C_N[0..15] <19>
PEG_MTX_GRX_C_P[0..15] <19>
2.2K_0402_5%~D1@
12
12
2.2K_0402_5%~D1@
R641
LDDC_DATA <20>
LDDC_CLK <20>
Strap Pin Table
CFG5
CFG6
CFG7
CFG9
CFG10
CFG11
CFG[13:12]
CFG16
(FSB Dynamic ODT)
CFG18
(VCC Select)
CFG19
(DMI Lane Reversal)
SDVO_CTRLDATA
CFG20
(PCIE/SDVO s e l ect)
2
Note :
CFG3:17 has
internal pullup,
CFG18:19 has
internal pulldown
Low = DMI x 2
High = DMI x 4
Low = Moby Dick
High = Calistoga
Low = DT/Transportable CPU
High = Mobile CPU
Low = Reverse Lane
High = Normal Operation
Low = Reserved
High = Mobility
Low = Calistoga
High = Reserved
00 = Reserved
01 = XOR Mode Enabled
10 = All Z Mode Enabled
11 = Normal Operation
Low = Disabled
High = Enabled
Low = 1.05V (Default)
High = 1.5V
Low = Normal
Operation (De f ault):
Lane number in Order
High = Reverse Lane
Low = No SDVO Devi c e Present
(Default)
High = SDVO Dev i c e Present
Low = Only PCIE or SDVO is
operational.
High = PCIE/SDVO are
operating simu.
2.2K_0402_5%~D1@
G_CLK_DDC2 CLK_DDC2_NB
*
*
(Default)
+3.3V_RUN
R653
*
*
*
*
*
12
*
(Default)
*
*
*
12
R655
+3.3V_RUN
1
+1.05V_VCCP
R673 1K_0402_5%~D@
CPU_MCH_BSEL0<6,8,10>
CFG5<10>
CFG6<10>
CFG7<10>
CFG9<10>
CFG10<10>
CFG11<10>
CFG12<10>
CFG13<10>
CFG16<10>
1 2
R677 2.2K_0402_5%~D@
1 2
R686 2.2K_0402_5%~D@
1 2
R688 2.2K_0402_5%~D@
1 2
R664 2.2K_0402_5%~D@
1 2
R79 2.2K_0402_5%~D@
1 2
R678 2.2K_0402_5%~D@
1 2
R672 2.2K_0402_5%~D@
1 2
R668 2.2K_0402_5%~D@
1 2
R667 2.2K_0402_5%~D@
1 2
*
CFG[3:17] have internal pullup
+3.3V_RUN
R628 1K_0402_5%~D@
CFG18<10>
CFG19<10>
CFG20<10>
CFG[18:19] have internal pulldown
NO CONNECT FOR DISCRETENOTE:
2.2K_0402_5%~D1@
Q97
D
S
13
BSS138_SOT23~D1@
G
2
G
2
Q96
DAT_DDC2_NBG_DAT_DDC2
13
D
S
BSS138_SOT23~D1@
1 2
R627 1K_0402_5%~D@
1 2
R626 1K_0402_5%~D@
1 2
CLK_DDC2_NB <20>
DAT_DDC2_NB <20>
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
4
3
2
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
Calistoga(3 of 6)
LA-2881P
12 62Tuesday, December 13, 2005
1
2.0
of
Page 13
5
+1.05V_VCCP
D D
CRB 270uF
220U_D2_4VM~D
1
C649
+
2
0.22U_0402_10V4Z~D
4.7U_0603_6.3V6M~D
2.2U_0603_6.3V6K~D
C581
C626
1
2
U6_A6
1
2
C633
C607
1
2
1
2
C C
0.47U_0402_10V4Z~D
close pin A6
0.22U_0402_10V4Z~D
C641
U6_D2
U6_AB1
0.47U_0402_10V4Z~D
C59
1
1
2
2
+1.5V_RUN
B B
close pin D2/AB1
+1.05V_VCCP +1.5V_RUN
A A
2
3
NOTE: Populate D4, R54, D2 and R52 for UMA Implemetation.
D4
1
MMBD4148-7-F_SOT23-3~D1@
CRT DAC Voltge Follower Circuit - 700mV
AC14
AB14
W14
AD13
AC13
AB13
AA13
W13
AB12
AA12
W12
AG14
AF14
AE14
AF13
AE13
AF12
AE12
AD12
R54
1 2
10_0603_5%~D1@
5
V14
T14
R14
P14
N14
M14
L14
Y13
V13
U13
T13
R13
N13
M13
L13
Y12
V12
U12
T12
R12
P12
N12
M12
L12
R11
P11
N11
M11
R10
P10
N10
M10
P9
N9
M9
R8
P8
N8
M8
P7
N7
M7
R6
P6
M6
A6
R5
P5
N5
M5
P4
N4
M4
R3
P3
N3
M3
R2
P2
M2
D2
AB1
R1
P1
N1
M1
Y14
U6H
VTT0
VTT1
VTT2
VTT3
VTT4
VTT5
VTT6
VTT7
VTT8
VTT9
VTT10
VTT11
VTT12
VTT13
VTT14
VTT15
VTT16
VTT17
VTT18
VTT19
VTT20
VTT21
VTT22
VTT23
VTT24
VTT25
VTT26
VTT27
VTT28
VTT29
VTT30
VTT31
VTT32
P O W E R
VTT33
VTT34
VTT35
VTT36
VTT37
VTT38
VTT39
VTT40
VTT41
VTT42
VTT43
VTT44
VTT45
VTT46
VTT47
VTT48
VTT49
VTT50
VTT51
VTT52
VTT53
VTT54
VTT55
VTT56
VTT57
VTT58
VTT59
VTT60
VTT61
VTT62
VTT63
VTT64
VTT65
VTT66
VTT67
VTT68
VTT69
VTT70
VTT71
VTT72
VTT73
VTT74
VTT75
VTT76
VCCAUX32
VCCAUX33
VCCAUX34
VCCAUX35
VCCAUX36
VCCAUX37
VCCAUX38
VCCAUX39
VCCAUX40
CALISTOGA A3 _ FCBGA1466~D
+2.5V_RUN
H22
VCC_SYNC
VCC3G0
VCC3G1
VCC3G2
VCC3G3
VCC3G4
VCC3G5
VCC3G6
VCCA_HPLL
VCCA_LVDS
VSSA_LVDS
VCCA_MPLL
VSSA_TVBG
VCCHV0
VCCHV1
VCCHV2
VCCAUX0
VCCAUX1
VCCAUX2
VCCAUX3
VCCAUX4
VCCAUX5
VCCAUX6
VCCAUX7
VCCAUX8
VCCAUX9
VCCAUX10
VCCAUX11
VCCAUX12
VCCAUX13
VCCAUX14
VCCAUX15
VCCAUX16
VCCAUX17
VCCAUX18
VCCAUX19
VCCAUX20
VCCAUX21
VCCAUX22
VCCAUX23
VCCAUX24
VCCAUX25
VCCAUX26
VCCAUX27
VCCAUX28
VCCAUX29
VCCAUX30
VCCAUX31
1
B30
C30
A30
AB41
AJ41
L41
N41
R41
V41
Y41
AC33
G41
H41
E21
F21
G21
B26
C39
AF1
A38
B39
AF2
H20
G20
E19
F19
C20
D20
E20
F20
AH1
AH2
A28
B28
C28
D21
H19
A23
B23
B25
AK31
AF31
AE31
AC31
AL30
AK30
AJ30
AH30
AG30
AF30
AE30
AD30
AC30
AG29
AF29
AE29
AD29
AC29
AG28
AF28
AE28
AH22
AJ21
AH21
AJ20
AH20
AH19
P19
P16
AH15
P15
AH14
R52
1 2
10_0603_5%~D1@
2
3
VCCTX_LVDS0
VCCTX_LVDS1
VCCTX_LVDS2
VCCA_CRTDAC0
VCCA_CRTDAC1
VSSA_CRTDAC2
VCCA_TVDACA0
VCCA_TVDACA1
VCCA_TVDACB0
VCCA_TVDACB1
VCCA_TVDACC0
VCCA_TVDACC1
VCCD_HMPLL0
VCCD_HMPLL1
VCCDQ_TVDAC
D2
MMBD4148-7-F_SOT23-3~D1@
VCCA_3GPLL
VCCA_3GBG
VSSA_3GBG
VCCA_DPLLA
VCCA_DPLLB
VCCA_TVBG
VCCD_LVDS0
VCCD_LVDS1
VCCD_LVDS2
VCCD_TVDAC
TV DAC Voltge Follower Circuit - 700mV
VSSA_TVBG
+3.3V_RUN
4
R89
1@
0_0402_5%~D
12
12
R90
3@
0_0402_5%~D
VCCTX_LVDS
W=30 mils
+1.5V_RUN_3GPLL
+2.5V_RUN
+2.5V_CRTDAC
+1.5V_RUN_DPLLA
+1.5V_RUN_DPLLB
+1.5V_RUN_HPLL
VCCA_LVDS
+1.5V_RUN_MPLL
+3VRUN_ATVBG
+3VRUN_TVDACA
+3VRUN_TVDACB
+3VRUN_TVDACC
+1.5V_RUN
VCCD_LVDS
+1.5V_RUN_TVDAC
+1.5V_RUN_QTVDAC
0.1U_0402_16V4Z~D
1
C105
2
+1.5V_RUN
1
C624
2
0.1U_0402_16V4Z~D
4
3
+2.5V_RUN
1
C99
0.1U_0402_16V4Z~D1@
2
Should be placed on same side. No Vias.
+1.5V_RUN_PCIE
220U_D2_4VM~D
10U_0805_4VAM~D
C147
C149
1
+
2
+3.3V_RUN
10U_0805_6.3V6M~D
1
C597
2
+2.5V_RUN
+1.5V_RUN_3GPLL
0.1U_0402_16V4Z~D
C580
1
2
1
1
2
2
+2.5V_CRTDAC
1 2
0.022U_0402_16V7K~D
3
C703
22n_0805_25V1@
Route VSSACRTDAC gnd from GMCH to
decoupling cap ground lead and then
connect to the gnd plane.
Route VSSA_TVBG GND from GMCH to
decoupling cap ground lead and then
connect to the GND plane.
C117
10U_0805_4VAM~D1@
1
2
R638
0_0603_5%~D1@
R636
0_0603_5%~D3@
1 2
10U_0805_4VAM~D
C565
0.5_0805_1%~D
1
2
NOTE:
1@ is for UMA Implemetation.
3@ is for Discrete Implementation.
L8
12
10U_0805_4VAM~D
BLM21PG600SN1D_0805~D
C148
FB
1@
0.1U_0402_16V4Z~D
C600
1
1
2
2
C587
0.01U_0402_16V7K~D1@
1
R640
0_0603_5%~D
3@
2
+1.5V_RUN
Route +2.5V_RUN from GMCH pinG41 to
decoupling cap(C567)<200mil to the edge
R658
0_0402_5%~D3@
1 2
1 2
L7
1@
BLM18PG181SN1_0603~D1@
C604
CRTDAC: Route caps within
250mil of GMCH. Route FB
within 3" o f Calistoga
+1.5V_RUN
R642
0_0603_5%~D1@
+2.5V_RUN
R634
0_0402_5%~D1@
12
12
R633
0_0402_5%~D3@
VCCTX_LVDS
C579
0.1U_0402_16V4Z~D1@
C129
4.7U_0603_6.3V6M~D1@
1
1
2
2
close pin B30/C30/A30
R624
+3GPLL_R
BLM21PG600SN1D_0805~D
12
L52
10uF should be placed in cavity
+2.5V_RUN
1
2
+1.05V_VCCP
+2.5V_RUN
VCCA_LVDS
0.1U_0402_16V4Z~D1@
C571
C572
1
2
close pin A38
+1.5V_RUN
0.1U_0402_16V4Z~D
C568
1
2
C567
0.1U_0402_16V4Z~D
+1.5V_RUN
0.01U_0402_16V7K~D1@
1
2
+3VRUN_TVDACC
12
R676
0_0402_5%~D3@
0.1U_0402_16V4Z~D1@
C615
1
2
+1.5V_RUN_HPLL
C638
0.1U_0402_16V4Z~D
+1.5V_RUN_DPLLA
40mA Max.
C590
0.1U_0402_16V4Z~D
Refer to the latest Intel layout check list for Calistoga de-couping capacitors layout placement
4.7uF, 10uF and 22uF should be placed < 500 mils within its pins
0.1uF should be placed < 200 mils within its pins
22nF should be placed within its pins
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
+3VRUN_TVDACA
12
+3VRUN_TVDACB
12
1 2
0_0402_5%~D3@
1 2
22n_0805_25V1@
1 2
22n_0805_25V1@
R660
3
3
R666
+1.5V_RUN
+1.5V_RUN
1 2
C627
3
22n_0805_25V1@
1 2
3
22n_0805_25V1@
1
1
2
2
1
1
+
2
2
Note : C588, C564 No stuff for Ext. VGA.
Stuff for Int. VGA.
R680
0_0402_5%~D3@
R670
0_0402_5%~D3@
0.1U_0402_16V4Z~D
1@
1
C629
+1.5V_RUN
2
+1.5V_RUN_TVDAC+1.5V_RUN +1.5V_RUN_QTVDAC
0.022U_0402_16V7K~D
1@
C707
C603
1
2
+1.5V_RUN
L59
BLM18AG121SN1D_0603~D
C645
22U_0805_6.3VAM~D
10U_CK2125 100M-T_20%_0805~D
C588
12
L54, L53 use 0_0805_5% resistor
for Int. VGA as Travis.
L54
12
470U_D2_2.5VM~D1@
2
1
+3V_TVDAC
+3.3V_RUN
C605
10U_0805_6.3V6M~D1@
1
2
NOTE:
Follow Intel Layout Guideline
toplace 4.7uF, 10uF, 22uF,
0.1uF and 22nF within 250 mils
from Calistoga.
R76
0_0603_5%~D 1@
1 2
+3VRUN_ATV
C630, C617, C611, C627,
0.1U_0402_16V4Z~D1@
C703, C704, C707 replace
C612
1
by 0 ohm 0805 resistor
2
L55
BLM18PG181SN1_0603~D
1 2
C610
1
C708
22U_0805_6.3VAM~D
2
3@
+1.5V_RUN
L60
BLM18AG121SN1D_0603~D
1
C646
22U_0805_6.3VAM~D
2
10U_CK2125 100M-T_20%_0805~D
1
+
C564
2
12
+1.5V_RUN+1.5V_RUN
L53
12
470U_D2_2.5VM~D1@
C630
C617
0_0402_5%~D3@
1
2
1
2
12
C609
0.022U_0402_16V7K~D1@
+3V_TVDAC
C616
0.1U_0402_16V4Z~D1@
C621
0.1U_0402_16V4Z~D1@
VSSA_TVBG
1
2
BLM18PG181SN1_0603~D1@
1 2
+3VRUN_ATVBG
1 2
4.7U_0603_6.3V6M~D
@
C613
1
2
R659
0_0402_5%~D3@
1 2
C704
3
22n_0805_25V1@
+1.5V_RUN_MPLL
45mA Max.45mA Max.
C639
0.1U_0402_16V4Z~D
+1.5V_RUN_DPLLB
40mA Max.
C570
0.1U_0402_16V4Z~D
L56
C611
3
22n_0805_25V1@
12
0.1U_0402_16V4Z~D
1
2
1
2
1
2
0.1uF should be placed < 200 mils within its pins
DELL CONFIDENTIAL/PROPRIETARY
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
Calistoga(4 of 6)
LA-2881P
1
+1.5V_RUN
13 62Tuesday, December 13, 2005
2.0
of
Page 14
5
4
3
2
1
+1.05V_VCCP
D D
0.22U_0402_10V4Z~D
0.22U_0402_10V4Z~D
C606
1
2
10U_0805_4VAM~D
10U_0805_4VAM~D
C594
C C
1
2
220U_D2_4VM~D
0.22U_0402_10V4Z~D
C593
C589
1
1
2
2
1U_0603_10V4Z~D
C628
C601
1
1
2
2
1
C54
+
2
CRB 270uF
220U_D2_4VM~D
1
C648
B B
A A
+
2
U6F
AD27
VCC_NCTF0
AC27
VCC_NCTF1
AB27
VCC_NCTF2
AA27
VCC_NCTF3
Y27
VCC_NCTF4
W27
VCC_NCTF5
V27
VCC_NCTF6
U27
VCC_NCTF7
T27
VCC_NCTF8
R27
VCC_NCTF9
AD26
VCC_NCTF10
AC26
VCC_NCTF11
AB26
VCC_NCTF12
AA26
VCC_NCTF13
Y26
VCC_NCTF14
W26
VCC_NCTF15
V26
VCC_NCTF16
U26
VCC_NCTF17
T26
VCC_NCTF18
R26
VCC_NCTF19
AD25
VCC_NCTF20
AC25
VCC_NCTF21
AB25
VCC_NCTF22
AA25
VCC_NCTF23
Y25
VCC_NCTF24
W25
VCC_NCTF25
V25
VCC_NCTF26
U25
VCC_NCTF27
T25
VCC_NCTF28
R25
VCC_NCTF29
AD24
VCC_NCTF30
AC24
VCC_NCTF31
AB24
VCC_NCTF32
AA24
VCC_NCTF33
Y24
VCC_NCTF34
W24
VCC_NCTF35
V24
VCC_NCTF36
U24
VCC_NCTF37
T24
VCC_NCTF38
R24
VCC_NCTF39
AD23
VCC_NCTF40
V23
VCC_NCTF41
U23
VCC_NCTF42
T23
VCC_NCTF43
R23
VCC_NCTF44
AD22
VCC_NCTF45
V22
VCC_NCTF46
U22
VCC_NCTF47
T22
VCC_NCTF48
R22
VCC_NCTF49
AD21
VCC_NCTF50
V21
VCC_NCTF51
U21
VCC_NCTF52
T21
VCC_NCTF53
R21
VCC_NCTF54
AD20
VCC_NCTF55
V20
VCC_NCTF56
U20
VCC_NCTF57
T20
VCC_NCTF58
R20
VCC_NCTF59
AD19
VCC_NCTF60
V19
VCC_NCTF61
U19
VCC_NCTF62
T19
VCC_NCTF63
AD18
VCC_NCTF64
AC18
VCC_NCTF65
AB18
VCC_NCTF66
AA18
VCC_NCTF67
Y18
VCC_NCTF68
W18
VCC_NCTF69
V18
VCC_NCTF70
U18
VCC_NCTF71
T18
VCC_NCTF72
M19
VCC100
L19
VCC101
N18
VCC102
M18
VCC103
L18
VCC104
P17
VCC105
N17
VCC106
M17
VCC107
N16
VCC108
M16
VCC109
L16
VCC110
CALISTOGA A3 _ FCBGA1466~D
VCCAUX_NCTF0
VCCAUX_NCTF1
VCCAUX_NCTF2
VCCAUX_NCTF3
VCCAUX_NCTF4
VCCAUX_NCTF5
VCCAUX_NCTF6
VCCAUX_NCTF7
VCCAUX_NCTF8
VCCAUX_NCTF9
VCCAUX_NCTF10
VCCAUX_NCTF11
VCCAUX_NCTF12
VCCAUX_NCTF13
VCCAUX_NCTF14
VCCAUX_NCTF15
VCCAUX_NCTF16
VCCAUX_NCTF17
VCCAUX_NCTF18
VCCAUX_NCTF19
VCCAUX_NCTF20
VCCAUX_NCTF21
VCCAUX_NCTF22
VCCAUX_NCTF23
VCCAUX_NCTF24
VCCAUX_NCTF25
VCCAUX_NCTF26
VCCAUX_NCTF27
VCCAUX_NCTF28
VCCAUX_NCTF29
VCCAUX_NCTF30
VCCAUX_NCTF31
VCCAUX_NCTF32
VCCAUX_NCTF33
VCCAUX_NCTF34
VCCAUX_NCTF35
VCCAUX_NCTF36
VCCAUX_NCTF37
P O W E R
VCCAUX_NCTF38
VCCAUX_NCTF39
VCCAUX_NCTF40
VCCAUX_NCTF41
VCCAUX_NCTF42
VCCAUX_NCTF43
VCCAUX_NCTF44
VCCAUX_NCTF45
VCCAUX_NCTF46
VCCAUX_NCTF47
VCCAUX_NCTF48
VCCAUX_NCTF49
VCCAUX_NCTF50
VCCAUX_NCTF51
VCCAUX_NCTF52
VCCAUX_NCTF53
VCCAUX_NCTF54
VCCAUX_NCTF55
VCCAUX_NCTF56
VCCAUX_NCTF57
VSS_NCTF0
VSS_NCTF1
VSS_NCTF2
VSS_NCTF3
VSS_NCTF4
VSS_NCTF5
VSS_NCTF6
VSS_NCTF7
VSS_NCTF8
VSS_NCTF9
VSS_NCTF10
VSS_NCTF11
VSS_NCTF12
VCC_SM100
VCC_SM101
VCC_SM102
VCC_SM103
VCC_SM104
VCC_SM105
VCC_SM106
VCC_SM107
AG27
AF27
AG26
AF26
AG25
AF25
AG24
AF24
AG23
AF23
AG22
AF22
AG21
AF21
AG20
AF20
AG19
AF19
R19
AG18
AF18
R18
AG17
AF17
AE17
AD17
AB17
AA17
W17
V17
T17
R17
AG16
AF16
AE16
AD16
AC16
AB16
AA16
Y16
W16
V16
U16
T16
R16
AG15
AF15
AE15
AD15
AC15
AB15
AA15
Y15
W15
V15
U15
T15
R15
AE27
AE26
AE25
AE24
AE23
AE22
AE21
AE20
AE19
AE18
AC17
Y17
U17
AR6
AP6
AN6
AL6
AK6
AJ6
AV1
AJ1
+1.5V_RUN+1.05V_VCCP
VCCSM_LF2
VCCSM_LF1
+1.8V_SUS+1.05V_VCCP
0.47U_0402_10V4Z~D
C640
0.47U_0402_10V4Z~D
C637
1
1
2
2
Place near U6.AV1 & AJ1
U6G
AA33
VCC0
W33
VCC1
P33
VCC2
N33
VCC3
L33
VCC4
J33
VCC5
AA32
VCC6
Y32
VCC7
W32
VCC8
V32
VCC9
P32
VCC10
N32
VCC11
M32
VCC12
L32
VCC13
J32
VCC14
AA31
VCC15
W31
VCC16
V31
VCC17
T31
VCC18
R31
VCC19
P31
VCC20
N31
VCC21
M31
VCC22
AA30
VCC23
Y30
VCC24
W30
VCC25
V30
VCC26
U30
VCC27
T30
VCC28
R30
VCC29
P30
VCC30
N30
VCC31
M30
VCC32
AA29
W29
M29
AB28
AA28
M28
M27
M25
M24
AB23
AA23
M23
AC22
AB22
W22
M22
AC21
AA21
W21
M21
AC20
AB20
W20
M20
AB19
AA19
L30
Y29
V29
U29
R29
P29
L29
Y28
V28
U28
T28
R28
P28
N28
L28
P27
N27
L27
P26
N26
L26
N25
L25
P24
N24
Y23
P23
N23
L23
Y22
P22
N22
L22
N21
L21
Y20
P20
N20
L20
Y19
N19
P O W E R
VCC33
VCC34
VCC35
VCC36
VCC37
VCC38
VCC39
VCC40
VCC41
VCC42
VCC43
VCC44
VCC45
VCC46
VCC47
VCC48
VCC49
VCC50
VCC51
VCC52
VCC53
VCC54
VCC55
VCC56
VCC57
VCC58
VCC59
VCC60
VCC61
VCC62
VCC63
VCC64
VCC65
VCC66
VCC67
VCC68
VCC69
VCC70
VCC71
VCC72
VCC73
VCC74
VCC75
VCC76
VCC77
VCC78
VCC79
VCC80
VCC81
VCC82
VCC83
VCC84
VCC85
VCC86
VCC87
VCC88
VCC89
VCC90
VCC91
VCC92
VCC93
VCC94
VCC95
VCC96
VCC97
VCC98
VCC99
CALISTOGA A3 _ FCBGA1466~D
VCC_SM0
VCC_SM1
VCC_SM2
VCC_SM3
VCC_SM4
VCC_SM5
VCC_SM6
VCC_SM7
VCC_SM8
VCC_SM9
VCC_SM10
VCC_SM11
VCC_SM12
VCC_SM13
VCC_SM14
VCC_SM15
VCC_SM16
VCC_SM17
VCC_SM18
VCC_SM19
VCC_SM20
VCC_SM21
VCC_SM22
VCC_SM23
VCC_SM24
VCC_SM25
VCC_SM26
VCC_SM27
VCC_SM28
VCC_SM29
VCC_SM30
VCC_SM31
VCC_SM32
VCC_SM33
VCC_SM34
VCC_SM35
VCC_SM36
VCC_SM37
VCC_SM38
VCC_SM39
VCC_SM40
VCC_SM41
VCC_SM42
VCC_SM43
VCC_SM44
VCC_SM45
VCC_SM46
VCC_SM47
VCC_SM48
VCC_SM49
VCC_SM50
VCC_SM51
VCC_SM52
VCC_SM53
VCC_SM54
VCC_SM55
VCC_SM56
VCC_SM57
VCC_SM58
VCC_SM59
VCC_SM60
VCC_SM61
VCC_SM62
VCC_SM63
VCC_SM64
VCC_SM65
VCC_SM66
VCC_SM67
VCC_SM68
VCC_SM69
VCC_SM70
VCC_SM71
VCC_SM72
VCC_SM73
VCC_SM74
VCC_SM75
VCC_SM76
VCC_SM77
VCC_SM78
VCC_SM79
VCC_SM80
VCC_SM81
VCC_SM82
VCC_SM83
VCC_SM84
VCC_SM85
VCC_SM86
VCC_SM87
VCC_SM88
VCC_SM89
VCC_SM90
VCC_SM91
VCC_SM92
VCC_SM93
VCC_SM94
VCC_SM95
VCC_SM96
VCC_SM97
VCC_SM98
VCC_SM99
AU41
AT41
AM41
AU40
BA34
AY34
AW34
AV34
AU34
AT34
AR34
BA30
AY30
AW30
AV30
AU30
AT30
AR30
AP30
AN30
AM30
AM29
AL29
AK29
AJ29
AH29
AJ28
AH28
AJ27
AH27
BA26
AY26
AW26
AV26
AU26
AT26
AR26
AJ26
AH26
AJ25
AH25
AJ24
AH24
BA23
AJ23
BA22
AY22
AW22
AV22
AU22
AT22
AR22
AP22
AK22
AJ22
AK21
AK20
BA19
AY19
AW19
AV19
AU19
AT19
AR19
AP19
AK19
AJ19
AJ18
AJ17
AH17
AJ16
AH16
BA15
AY15
AW15
AV15
AU15
AT15
AR15
AJ15
AJ14
AJ13
AH13
AK12
AJ12
AH12
AG12
AK11
BA8
AY8
AW8
AV8
AT8
AR8
AP8
BA6
AY6
AW6
AV6
AT6
+1.8V_SUS
VCCSM_LF4
VCCSM_LF5
0.47U_0402_10V4Z~D
0.47U_0402_10V4Z~D
C569
1
1
2
2
Place near U6.AT41 & AM41
0.1U_0402_16V4Z~D
C614
1
2
0.47U_0402_10V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
C622
1
2
0.47U_0402_10V4Z~D
C608
1
2
Place near U6.BA23
0.47U_0402_10V4Z~D
0.47U_0402_10V4Z~D
C598
1
2
Place near U6.BA15
10U_0805_4VAM~D
C87
1
2
330U_D2E_2.5VM~D@
10U_0805_4VAM~D
C102
1
2
C566
0.1U_0402_16V4Z~D
C599
C631
1
1
2
2
C576
1
2
C584
1
2
1
C130
+
2
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
Calistoga(5 of 6)
LA-2881P
14 62Tuesday, December 13, 2005
1
2.0
of
Page 15
5
U6I
AC41
VSS0
AA41
VSS1
W41
VSS2
T41
VSS3
P41
VSS4
M41
D D
C C
B B
A A
VSS5
J41
VSS6
F41
VSS7
AV40
VSS8
AP40
VSS9
AN40
VSS10
AK40
VSS11
AJ40
VSS12
AH40
VSS13
AG40
VSS14
AF40
VSS15
AE40
VSS16
B40
VSS17
AY39
VSS18
AW39
VSS19
AV39
VSS20
AR39
VSS21
AN39
VSS22
AJ39
VSS23
AC39
VSS24
AB39
VSS25
AA39
VSS26
Y39
VSS27
W39
VSS28
V39
VSS29
T39
VSS30
R39
VSS31
P39
VSS32
N39
VSS33
M39
VSS34
L39
VSS35
J39
VSS36
H39
VSS37
G39
VSS38
F39
VSS39
D39
VSS40
AT38
VSS41
AM38
VSS42
AH38
VSS43
AG38
VSS44
AF38
VSS45
AE38
VSS46
C38
VSS47
AK37
VSS48
AH37
VSS49
AB37
VSS50
AA37
VSS51
Y37
VSS52
W37
VSS53
V37
VSS54
T37
VSS55
R37
VSS56
P37
VSS57
N37
VSS58
M37
VSS59
L37
VSS60
J37
VSS61
H37
VSS62
G37
VSS63
F37
VSS64
D37
VSS65
AY36
VSS66
AW36
VSS67
AN36
VSS68
AH36
VSS69
AG36
VSS70
AF36
VSS71
AE36
VSS72
AC36
VSS73
C36
VSS74
B36
VSS75
BA35
VSS76
AV35
VSS77
AR35
VSS78
AH35
VSS79
AB35
VSS80
AA35
VSS81
Y35
VSS82
W35
VSS83
V35
VSS84
T35
VSS85
R35
VSS86
P35
VSS87
N35
VSS88
M35
VSS89
L35
VSS90
J35
VSS91
H35
VSS92
G35
VSS93
F35
VSS94
D35
VSS95
AN34
VSS96
AK34
VSS97
AG34
VSS98
AF34
VSS99
CALISTOGA A3 _ FCBGA1466~D
4
P O W E R
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS140
VSS141
VSS142
VSS143
VSS144
VSS145
VSS146
VSS147
VSS148
VSS149
VSS150
VSS151
VSS152
VSS153
VSS154
VSS155
VSS156
VSS157
VSS158
VSS159
VSS160
VSS161
VSS162
VSS163
VSS164
VSS165
VSS166
VSS167
VSS168
VSS169
VSS170
VSS171
VSS172
VSS173
VSS174
VSS175
VSS176
VSS177
VSS178
VSS179
VSS180
VSS181
VSS182
VSS183
VSS184
VSS185
VSS186
VSS187
VSS188
VSS189
VSS190
VSS191
VSS192
VSS193
VSS194
VSS195
VSS196
VSS197
VSS198
VSS199
AE34
AC34
C34
AW33
AV33
AR33
AE33
AB33
Y33
V33
T33
R33
M33
H33
G33
F33
D33
B33
AH32
AG32
AF32
AE32
AC32
AB32
G32
B32
AY31
AV31
AN31
AJ31
AG31
AB31
Y31
AB30
E30
AT29
AN29
AB29
T29
N29
K29
G29
E29
C29
B29
A29
BA28
AW28
AU28
AP28
AM28
AD28
AC28
W28
J28
E28
AP27
AM27
AK27
J27
G27
F27
C27
B27
AN26
M26
K26
F26
D26
AK25
P25
K25
H25
E25
D25
A25
BA24
AU24
AL24
AW23
AT23
AN23
AM23
AH23
AC23
W23
K23
J23
F23
C23
AA22
K22
G22
F22
E22
D22
A22
BA21
AV21
AR21
3
U6J
AN21
VSS200
AL21
VSS201
AB21
VSS202
Y21
VSS203
P21
VSS204
K21
VSS205
J21
VSS206
H21
VSS207
C21
VSS208
AW20
VSS209
AR20
VSS210
AM20
VSS211
AA20
VSS212
K20
VSS213
B20
VSS214
A20
VSS215
AN19
VSS216
AC19
VSS217
W19
VSS218
K19
VSS219
G19
VSS220
C19
VSS221
AH18
VSS222
P18
VSS223
H18
VSS224
D18
VSS225
A18
VSS226
AY17
VSS227
AR17
VSS228
AP17
VSS229
AM17
VSS230
AK17
VSS231
AV16
VSS232
AN16
VSS233
AL16
VSS234
J16
VSS235
F16
VSS236
C16
VSS237
AN15
VSS238
AM15
VSS239
AK15
VSS240
N15
VSS241
M15
VSS242
L15
VSS243
B15
VSS244
A15
VSS245
BA14
VSS246
AT14
VSS247
AK14
VSS248
AD14
VSS249
AA14
VSS250
U14
VSS251
K14
VSS252
H14
VSS253
E14
VSS254
AV13
VSS255
AR13
VSS256
AN13
VSS257
AM13
VSS258
AL13
VSS259
AG13
VSS260
P13
VSS261
F13
VSS262
D13
VSS265
B13
VSS264
AY12
VSS263
AC12
VSS266
K12
VSS267
H12
VSS268
E12
VSS269
AD11
VSS270
AA11
VSS271
Y11
VSS272
J11
VSS273
D11
VSS274
B11
VSS275
AV10
VSS276
AP10
VSS277
AL10
VSS278
AJ10
VSS279
CALISTOGA A3 _ FCBGA1466~D
2
P O W E R
VSS280
VSS281
VSS282
VSS283
VSS284
VSS285
VSS286
VSS287
VSS288
VSS289
VSS290
VSS292
VSS291
VSS293
VSS294
VSS295
VSS296
VSS297
VSS298
VSS299
VSS300
VSS301
VSS302
VSS303
VSS304
VSS305
VSS306
VSS307
VSS308
VSS309
VSS310
VSS311
VSS312
VSS313
VSS314
VSS315
VSS316
VSS317
VSS318
VSS319
VSS320
VSS321
VSS322
VSS323
VSS324
VSS325
VSS326
VSS327
VSS328
VSS329
VSS330
VSS331
VSS332
VSS333
VSS334
VSS335
VSS336
VSS337
VSS338
VSS339
VSS340
VSS341
VSS342
VSS343
VSS344
VSS345
VSS346
VSS347
VSS348
VSS349
VSS350
VSS351
VSS352
VSS353
VSS354
VSS355
VSS356
VSS357
VSS358
VSS359
VSS360
AG10
AC10
W10
U10
BA9
AW9
AR9
AH9
AB9
Y9
R9
G9
E9
A9
AG8
AD8
AA8
U8
K8
C8
BA7
AV7
AP7
AL7
AJ7
AH7
AF7
AC7
R7
G7
D7
AG6
AD6
AB6
Y6
U6
N6
K6
H6
B6
AV5
AF5
AD5
AY4
AR4
AP4
AL4
AJ4
Y4
U4
R4
J4
F4
C4
AY3
AW3
AV3
AL3
AH3
AG3
AF3
AD3
AC3
AA3
G3
AT2
AR2
AP2
AK2
AJ2
AD2
AB2
Y2
U2
T2
N2
J2
H2
F2
C2
AL1
1
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
Calistoga(6 of 6)
LA-2881P
15 62Tuesday, December 13, 2005
1
2.0
of
Page 16
5
+15V_SUS
FAN2_PWM FAN2VREF
D D
+15V_SUS
8
U35B
5
P
IN+
7
O
6
IN-
G
LM358DR2G_SOIC8~D3@
4
C C
B B
REM_DIODE3_ N , R E M _ D I O D E 3_P routing together.
Trace width / Spacing = 10 / 10 mil
1
2200P_0402_50V7K~D@
A A
C635
2
Place near the bottom SODIMM
R490
1 2
120K_0402_5%~D3@
0.22U_0603_10V7K~D3@
+3.3V_SUS
+3.3V_SUS
0.1U_0402_16V4Z~D
C412
120K_0402_5%~D3@
Place C39 as close to the
Guardian pins as possible
H_THERMDA<7>
2200P_0402_50V7K~D
H_THERMDC<7>
49.9_0603_1%~D
1 2
0.1U_0402_16V4Z~D
1
C43
2
Q98
E
31
PMBT3904_SOT23~D
B
2
C
2200P_0402_50V7K~D
FAN2_VFB
1
2
R489
1 2
C39
R24
1
C32
2
+RTC_CELL
0.1U_0402_16V4Z~D
147K_0402_1%~D
41.2K_0603_1%~D
C28
1
2
R21
R23
1
2
8
U35A
3
P
IN+
1
O
2
IN-
G
LM358DR2G_SOIC8~D3@
4
1 2
C410 2200P_0402_50V7K~D3@
12
R488 78.7K_0402_1%~D3@
RB751V_SOD323~D3@
RB751V_SOD323~D@
DAT_SMB<38>
CLK_SMB<38>
+3.3V_SUS
SUSPWROK<23,40>
1
C48
12
12
ICH_PWRGD#<40>
POWER_SW#<38,39>
2
1 2
R709 8.2K_0402_5%~D
1K_0402_5%~D
2200P_0402_50V7K~D
C31
Place C28 as close to the
Guardian pins as possible.
1
1 2
2
REM_DIODE3_N
REM_DIODE3_P
R49
Notes:
"Solder thermal pad to plane. Add 9 ground vias to pad."
5
0.1U_0603_50V4Z~D3@
1
2
FAN2_ON
D15
D21
4
+5V_RUN
C408
2
1
G
3
4 5
1
C400
2
2 1
C694
2 1
DAT_SMB
CLK_SMB
1 2
R50 7.5K_0402_5%~D
+3VSUS_THRM
1 2
R51 1K_0402_5%~D
1 2
R712 1K_0402_5%~D
THERMATRIP1#
THERMATRIP2#
THERMATRIP_VGA#
4
6
D
S
22U_1206_10V4Z~D3@
1
2
Q86
SI3456BDV-T1_TSOP6~D3@
22U_1206_10V4Z~D
FAN1_VOUT
FAN2_PWM
C402
1000P_0402_50V7K~D@
1
2
1000P_0402_50V7K~D@
1
C696
2
U2
7
8
23
35
34
12
21
18
13
38
14
15
16
39
29
9
1
2
6
33
10
11
19
20
32
41
EMC4000_C_QFN40~D
SMBUS ADDRESS : 2F
FAN2_5V
FAN1_VOUT
SMDATA
SMBCLK
LDO_SHDN#_ADDR
DP2
DN2
+3V_SUS
VSUS_PWRGD
+RTC_PWR3V
+3V_PWROK#
POWER_SW#
THERMTRIP1#
THERMTRIP2#
THERMTRIP3#
VSET
HW_LOCK#
VSS
DP3
DN3
FAN_OUT
FAN_DAC
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
Thermal
+5V_RUN
JFAN2
1
1
2
2
3
3
MOLEX_53398-0371~D3@
FAN2
JFAN1
1
1
2
2
3
3
MOLEX_53398-0371~D
FAN1
ATF_INT#
VCP
VCP
LDO_POK
DN1
DP1
THERMTRIP_SIO
THERM_STP#
INTRUDER#
LDO_SET
LDO_OUT
LDO_OUT
LDO_IN
LDO_IN
VDD_5V
0.1U_0402_16V4Z~D
C26
C27
1
2
3
C
B
E
1
2
2
3
2222 SYMBOL(SOT23-NEW)
+3.3V_RUN
12
FAN2 Control and Tachometer
R450
10K_0402_5%~D3@
1
C352
@
2
+3.3V_RUN
12
R736
10K_0402_5%~D
1
C698
@
2
17
3
40
31
36
37
30
4
22
24
25
27
26
28
5
10U_0805_10V4Z~D
1
2
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
FAN2_TACH <38>
1000P_0402_50V7K~D
FAN1 Control and Tachometer
FAN1_TACH <38>
1000P_0402_50V7K~D
ATF_INT#
VCP1
VCP2
REM_DIODE1_N
REM_DIODE1_P
LDO_SET
3
ATF_INT# <38>
2.5V_RUN_PWRGD <40>
Place C37 as close to the
Guardian pins as possible
+3.3V_ALW
12
R48
10K_0402_5%~D
THERMTRIP_SIO <37>
ACAV_IN <19,38,49>
THERM_STP# <45>
12
R702 10K_0402_5%~D@
1
C50
10U_0805_10V4Z~D
2
+3V_LDOIN
1
C651
1U_0603_10V4Z~D
2
+1.05V_VCCP
1
C37
2200P_0402_50V7K~D
2
+RTC_CELL
+2.5V_RUN
1
C51
0.1U_0402_16V4Z~D
@
2
R705
1 2
0_1210_5%~D
1
C650
0.1U_0402_16V4Z~D
@
2
R25
2.2K_0402_5%~D
1 2
PMBT3904_SOT23~D
+5V_SUS
12
1
2
+5V_SUS
12
1
2
B
2
Place under CPU
+3.3V_RUN
2
B
E
Q13
R738
2.21K_0603_1%~D
@
C700
2200P_0402_50V7K~D
@
R741
2.21K_0603_1%~D
@
C701
2200P_0402_50V7K~D
@
E
31
Q7
PMBT3904_SOT23~D
C
2
1
Note: +3.3V_RUN leakage issue from ATI M22
+3.3V_RUN
R44
1 2
2.2K_0402_5%~D
OTBMP#<19>
12
R31
8.2K_0402_5%~D
THERMATRIP1# THERMATRIP2#
C
1
C34
0.1U_0402_16V4Z~D
3 1
2
12
R739
10KB_0603_1%_TSM1A103F34D3R~D
@
13
D
Q102
2N7002_SOT23~D
@
Q103
2N7002_SOT23~D
@
2
G
S
12
R742
10KB_0603_1%_TSM1A103F34D3R~D
@
13
D
2
G
S
1
C14
2200P_0402_50V7K~D@
2
LDO_SET
THERMATRIP_VGA#
C
Q17
2
B
PMBT3904_SOT23~D
E
3 1
R45
0_0402_5%~D@
1 2
+3.3V_SUS+3.3V_SUS
+1.05V_VCCP
R27
2.2K_0402_5%~D
1 2
PMBT3904_SOT23~D
THERMTRIP_MCH#<10>H_THERMTRIP#<7>
This unused thermistor circuit is
located near DIMM A slot
This unused thermistor circuit is
located near the ICH7
+2.5V_RUN
31.6K_0603_1%
12
R737
Ra
@
1K_0603_5%~D
12
R703
2
B
Q14
+5V_SUS
12
+5V_SUS
12
E
R740
10K_0402_5%~D
@
R743
10K_0402_5%~D
@
12
R35
8.2K_0402_5%~D
C
3 1
Rb
Voltage marg i n i n g c i r cuit for LDO output.
For Vmargin, s t u f f R a =31.5K and Rb=30K.
Rb=1K for production
DELL CONFIDENTIAL/PROPRIETARY
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
Thermal sensor and Fan
LA-2881P
1
1
C38
0.1U_0402_16V4Z~D
2
5V_CAL_SIO# <37>
5V_CAL_SIO2# <37>
16 62Tuesday, December 13, 2005
of
2.0
Page 17
5
DDR_B_DQS#[0..7]<11>
DDR_B_D[0..63]<11>
DDR_B_DM[0..7]<11>
DDR_B_DQS[0..7]<11>
DDR_B_MA[0..13]<11>
D D
+1.8V_SUS
C C
+0.9V_DDR_VTT
C592
0.1U_0402_16V4Z~D
C596
0.1U_0402_16V4Z~D
1
2
B B
M_ODT3
DDR_CS3_DIMMB#
DDR_B_CAS#
DDR_B_WE#
DDR_B_BS0
DDR_B_MA10
DDR_B_MA1
DDR_B_MA3
DDR_B_MA5
DDR_B_MA8
DDR_B_MA9
A A
DDR_B_MA12
5
C586
0.1U_0402_16V4Z~D
1
1
2
2
56_1206_8P4R_5%~D
56_1206_8P4R_5%~D
56_1206_8P4R_5%~D
0.1U_0402_16V4Z~D
RP1
1 8
2 7
3 6
4 5
RP3
1 8
2 7
3 6
4 5
RP5
1 8
2 7
3 6
4 5
Layout Note:
Place near JDIMB
2.2U_0603_6.3V6K~D
C132
1
2
0.1U_0402_16V4Z~D
C140
1
2
Layout Note:
Place one cap close to every 2 pullup
resistors terminated to +0.9V_DDR_VTT
C583
C578
0.1U_0402_16V4Z~D
1
1
2
2
+0.9V_DDR_VTT
2.2U_0603_6.3V6K~D
2.2U_0603_6.3V6K~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
1 8
2 7
3 6
4 5
56_1206_8P4R_5%~D
1 8
2 7
3 6
4 5
56_1206_8P4R_5%~D
1 8
2 7
3 6
4 5
56_1206_8P4R_5%~D
1 2
R106 56_0402_5%~D
1 2
R108 56_0402_5%~D
1
2
1
2
C575
1
2
RP14
RP12
RP10
C120
1
2
0.1U_0402_16V4Z~D
C138
1
2
C110
0.1U_0402_16V4Z~D
1
2
DDR_B_MA13
M_ODT2
DDR_CS2_DIMMB#
DDR_B_RAS#
DDR_B_BS1
DDR_B_MA0
DDR_B_MA2
DDR_B_MA4
DDR_B_MA6
DDR_B_MA7
DDR_B_MA11
DDR_CKE3_DIMMB
DDR_B_BS2
DDR_CKE2_DIMMB
C108
C125
0.1U_0402_16V4Z~D
4
2.2U_0603_6.3V6K~D
2.2U_0603_6.3V6K~D
C143
C113
1
1
2
2
0.1U_0402_16V4Z~D
C121
1
2
C114
C118
0.1U_0402_16V4Z~D
1
1
2
2
0.1U_0402_16V4Z~D
C123
0.1U_0402_16V4Z~D
1
2
4
C136
1
2
Layout Note:
Place these resistor
closely JDIMB,all
trace length<750 mil
Layout Note:
Place these resistor
closely JDIMB,all
trace length
Max=1.3"
C131
0.1U_0402_16V4Z~D
C128
0.1U_0402_16V4Z~D
1
1
2
2
DDR_CKE2_DIMMB<10>
DDR_CS3_DIMMB#<10>
3
DDR_B_BS2<11>
DDR_B_BS0<11>
DDR_B_WE#<11>
DDR_B_CAS#<11>
CLK_SDATA<6,18>
CLK_SCLK<6,18>
+3.3V_RUN
+1.8V_SUS +1.8V_SUS
JDIMB
1
VREF
3
DDR_B_D1
DDR_B_D5
DDR_B_DQS#0
DDR_B_D2
DDR_B_D3
DDR_B_D8
DDR_B_D9
DDR_B_DQS#1
DDR_B_DQS1
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D21
DDR_B_DQS#2
DDR_B_DQS2
DDR_B_D23
DDR_B_D19
DDR_B_D24
DDR_B_D25
DDR_B_DM3
DDR_B_D30
DDR_B_D31
DDR_CKE2_DIMMB
DDR_B_BS2
DDR_B_MA12
DDR_B_MA9
DDR_B_MA8
DDR_B_MA5
DDR_B_MA3
DDR_B_MA1
DDR_B_MA10
DDR_B_BS0
DDR_B_WE#
DDR_B_CAS#
DDR_CS3_DIMMB#
M_ODT3<10>
M_ODT3
DDR_B_D36
DDR_B_D37
DDR_B_DQS#4
DDR_B_DQS4
DDR_B_D35
DDR_B_D34
DDR_B_D41
DDR_B_D40
DDR_B_DM5
DDR_B_D43
DDR_B_D46
DDR_B_D49
DDR_B_D53
DDR_B_DQS#6
DDR_B_DQS6
DDR_B_D54
DDR_B_D50
DDR_B_D60
DDR_B_D57
DDR_B_DM7
DDR_B_D58
DDR_B_D59
CLK_SDATA
CLK_SCLK
0.1U_0402_16V4Z~D
C61
1
2
2.2U_0603_6.3V6K~D
C55
1
2
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
VSS
DQ0
DQ1
VSS
DQS0#
DQS0
VSS
DQ2
DQ3
VSS
DQ8
DQ9
VSS
DQS1#
DQS1
VSS
DQ10
DQ11
VSS
VSS
DQ16
DQ17
VSS
DQS2#
DQS2
VSS
DQ18
DQ19
VSS
DQ24
DQ25
VSS
DM3
NC
VSS
DQ26
DQ27
VSS
CKE0
VDD
NC
BA2
VDD
A12
A9
A8
VDD
A5
A3
A1
VDD
A10/AP
BA0
WE#
VDD
CAS#
NC/S1#
VDD
NC/ODT1
VSS
DQ32
DQ33
VSS
DQS4#
DQS4
VSS
DQ34
DQ35
VSS
DQ40
DQ41
VSS
DM5
VSS
DQ42
DQ43
VSS
DQ48
DQ49
VSS
NC,TEST
VSS
DQS6#
DQS6
VSS
DQ50
DQ51
VSS
DQ56
DQ57
VSS
DM7
VSS
DQ58
DQ59
VSS
SDA
SCL
VDDSPD
FOX_AS0A426-M2S-TR~D
DIMMB
VSS
DQ4
DQ5
VSS
DM0
VSS
DQ6
DQ7
VSS
DQ12
DQ13
VSS
DM1
VSS
CK0#
VSS
DQ14
DQ15
VSS
VSS
DQ20
DQ21
VSS
DM2
VSS
DQ22
DQ23
VSS
DQ28
DQ29
VSS
DQS3#
DQS3
VSS
DQ30
DQ31
VSS
NC/CKE1
VDD
NC/A15
NC/A14
VDD
VDD
VDD
RAS#
VDD
ODT0
NC/A13
VDD
VSS
DQ36
DQ37
VSS
DM4
VSS
DQ38
DQ39
VSS
DQ44
DQ45
VSS
DQS5#
DQS5
VSS
DQ46
DQ47
VSS
DQ52
DQ53
VSS
CK1#
VSS
DM6
VSS
DQ54
DQ55
VSS
DQ60
DQ61
VSS
DQS7#
DQS7
VSS
DQ62
DQ63
VSS
SAO
2
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
CK0
32
34
36
38
40
42
44
46
48
50
NC
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
A11
92
A7
94
A6
96
98
A4
100
A2
102
A0
104
106
BA1
108
110
S0#
112
114
116
118
120
NC
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
CK1
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
SA1
STANDARD
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
+0.9V_DDR_REF
DDR_B_D4
DDR_B_D0
DDR_B_DM0
DDR_B_D6DDR_B_DQS0
DDR_B_D7
DDR_B_D12
DDR_B_D13
DDR_B_DM1
M_CLK_DDR3
M_CLK_DDR#3
DDR_B_D10
DDR_B_D11
DDR_B_D17
DDR_B_D20
PM_EXTTS#0_R
DDR_B_DM2
DDR_B_D18
DDR_B_D22
DDR_B_D26
DDR_B_D28
DDR_B_DQS#3
DDR_B_DQS3
DDR_B_D27
DDR_B_D29
DDR_CKE3_DIMMB
DDR_B_MA11
DDR_B_MA7
DDR_B_MA6
DDR_B_MA4
DDR_B_MA2
DDR_B_MA0
DDR_B_BS1
DDR_B_RAS#
DDR_CS2_DIMMB#
M_ODT2
DDR_B_MA13
DDR_B_D33
DDR_B_D32
DDR_B_DM4
DDR_B_D39
DDR_B_D38
DDR_B_D44
DDR_B_D45
DDR_B_DQS#5
DDR_B_DQS5
DDR_B_D42
DDR_B_D47
DDR_B_D48
DDR_B_D52
M_CLK_DDR2
M_CLK_DDR#2
DDR_B_DM6
DDR_B_D55
DDR_B_D51
DDR_B_D61
DDR_B_D56
DDR_B_DQS#7
DDR_B_DQS7
DDR_B_D62
DDR_B_D63
1 2
100K_0402_5%~D
12
R66
1
0.1U_0402_16V4Z~D
C169
1
2
+0.9V_DDR_REF <10,18,47>
2.2U_0603_6.3V6K~D
M_CLK_DDR3 <10>
M_CLK_DDR#3 <10>
PM_EXTTS#0_R <18>
DDR_CKE3_DIMMB <10>
DDR_B_BS1 <11>
DDR_B_RAS# <11>
DDR_CS2_DIMMB# <10>
M_ODT2 <10>
M_CLK_DDR2 <10>
M_CLK_DDR#2 <10>
+3.3V_RUN
R63
10K_0402_5%~D
C172
1
2
DELL CONFIDENTIAL/PROPRIETARY
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
DDRII-SODIMM SLOT-B
LA-2881P
17 62Tuesday, December 13, 2005
1
of
2.0
Page 18
5
DDR_A_DQS#[0..7]<11>
DDR_A_D[0..63]<11>
DDR_A_DM[0..7]<11>
DDR_A_DQS[0..7]<11>
DDR_A_MA[0..13]<11>
D D
C C
+0.9V_DDR_VTT
C111
0.1U_0402_16V4Z~D
1
2
B B
DDR_A_BS0
DDR_A_MA10
DDR_A_MA1
DDR_A_MA3
DDR_A_MA5
DDR_A_MA8
DDR_A_MA12
M_ODT1
DDR_CS1_DIMMA#
DDR_A_CAS#
A A
DDR_A_WE#
5
C116
0.1U_0402_16V4Z~D
1
2
+1.8V_SUS
Layout Note:
Place one cap close to every 2 pullup
resistors terminated to +0.9V_DDR_VTT
C122
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
1
2
RP11
1 8
2 7
3 6
4 5
56_1206_8P4R_5%~D
RP9
1 8
2 7
3 6
4 5
56_1206_8P4R_5%~D
RP13
1 8
2 7
3 6
4 5
56_1206_8P4R_5%~D
2.2U_0603_6.3V6K~D
1
2
0.1U_0402_16V4Z~D
1
2
0.1U_0402_16V4Z~D
C126
1
1
2
2
+0.9V_DDR_VTT
Layout Note:
Place near JDIMA
2.2U_0603_6.3V6K~D
2.2U_0603_6.3V6K~D
C133
C602
1
2
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
C142
C127
1
2
C135
0.1U_0402_16V4Z~D
C139
0.1U_0402_16V4Z~D
1
1
2
2
RP6
DDR_A_MA6
1 8
DDR_A_MA7
2 7
DDR_A_MA11
3 6
DDR_CKE1_DIMMA
4 5
56_1206_8P4R_5%~D
RP2
DDR_A_MA13
1 8
M_ODT0
2 7
DDR_CS0_DIMMA#DDR_A_MA9
3 6
DDR_A_RAS#
4 5
56_1206_8P4R_5%~D
RP4
DDR_A_BS1
1 8
DDR_A_MA0
2 7
DDR_A_MA2
3 6
DDR_A_MA4
4 5
56_1206_8P4R_5%~D
DDR_A_BS2
1 2
R632 56_0402_5%~D
R630 56_0402_5%~D
1 2
DDR_CKE0_DIMMA
C145
1
2
C106
1
2
C574
0.1U_0402_16V4Z~D
4
2.2U_0603_6.3V6K~D
2.2U_0603_6.3V6K~D
C109
C119
1
1
2
2
0.1U_0402_16V4Z~D
C141
1
2
0.1U_0402_16V4Z~D
C582
0.1U_0402_16V4Z~D
C577
1
1
2
2
4
0.1U_0402_16V4Z~D
C585
C573
0.1U_0402_16V4Z~D
1
1
2
2
Layout Note:
Place these resistor
closely JDIMA,all
trace length<750 mil
Layout Note:
Place these resistor
closely JDIMA,all
trace length
Max=1.3"
C591
C595
0.1U_0402_16V4Z~D
1
1
2
2
DDR_CKE0_DIMMA<10>
DDR_CS1_DIMMA#<10>
3
DDR_A_BS2<11>
DDR_A_BS0<11>
DDR_A_WE#<11>
DDR_A_CAS#<11>
CLK_SDATA<6,17>
CLK_SCLK<6,17>
+3.3V_RUN
+1.8V_SUS +1.8V_SUS
JDIMA
1
VREF
3
DDR_A_D0
DDR_A_D1
DDR_A_DQS#0
DDR_A_DQS0
DDR_A_D2
DDR_A_D3
DDR_A_D8
DDR_A_D14
DDR_A_DQS#1
DDR_A_DQS1
DDR_A_D11
DDR_A_D10
DDR_A_D16
DDR_A_D17
DDR_A_DQS#2
DDR_A_DQS2
DDR_A_D18
DDR_A_D22
DDR_A_D24
DDR_A_D28
DDR_A_DM3
DDR_A_D26
DDR_A_D27
DDR_CKE0_DIMMA
DDR_A_BS2
DDR_A_MA12
DDR_A_MA9 DDR_A_MA7
DDR_A_MA8
DDR_A_MA5
DDR_A_MA3
DDR_A_MA1
DDR_A_MA10
DDR_A_BS0
DDR_A_WE#
DDR_A_CAS#
DDR_CS1_DIMMA#
M_ODT1<10>
M_ODT1
DDR_A_D36
DDR_A_D37
DDR_A_DQS#4
DDR_A_DQS4
DDR_A_D34
DDR_A_D33
DDR_A_D44
DDR_A_D42
DDR_A_DM5
DDR_A_D41
DDR_A_D43
DDR_A_D49
DDR_A_D48
DDR_A_DQS#6
DDR_A_DQS6
DDR_A_D50
DDR_A_D51
DDR_A_D57
DDR_A_D56
DDR_A_DM7
DDR_A_D58
DDR_A_D59
CLK_SDATA
CLK_SCLK
0.1U_0402_16V4Z~D
C57
1
2
2.2U_0603_6.3V6K~D
C53
1
2
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
FOX_AS0A426-M2R-TR~D
VSS
DQ0
DQ1
VSS
DQS0#
DQS0
VSS
DQ2
DQ3
VSS
DQ8
DQ9
VSS
DQS1#
DQS1
VSS
DQ10
DQ11
VSS
VSS
DQ16
DQ17
VSS
DQS2#
DQS2
VSS
DQ18
DQ19
VSS
DQ24
DQ25
VSS
DM3
NC
VSS
DQ26
DQ27
VSS
CKE0
VDD
NC
BA2
VDD
A12
A9
A8
VDD
A5
A3
A1
VDD
A10/AP
BA0
WE#
VDD
CAS#
NC/S1#
VDD
NC/ODT1
VSS
DQ32
DQ33
VSS
DQS4#
DQS4
VSS
DQ34
DQ35
VSS
DQ40
DQ41
VSS
DM5
VSS
DQ42
DQ43
VSS
DQ48
DQ49
VSS
NC,TEST
VSS
DQS6#
DQS6
VSS
DQ50
DQ51
VSS
DQ56
DQ57
VSS
DM7
VSS
DQ58
DQ59
VSS
SDA
SCL
VDDSPD
DIMMA
VSS
DQ4
DQ5
VSS
DM0
VSS
DQ6
DQ7
VSS
DQ12
DQ13
VSS
DM1
VSS
CK0#
VSS
DQ14
DQ15
VSS
VSS
DQ20
DQ21
VSS
DM2
VSS
DQ22
DQ23
VSS
DQ28
DQ29
VSS
DQS3#
DQS3
VSS
DQ30
DQ31
VSS
NC/CKE1
VDD
NC/A15
NC/A14
VDD
VDD
VDD
RAS#
VDD
ODT0
NC/A13
VDD
VSS
DQ36
DQ37
VSS
DM4
VSS
DQ38
DQ39
VSS
DQ44
DQ45
VSS
DQS5#
DQS5
VSS
DQ46
DQ47
VSS
DQ52
DQ53
VSS
CK1#
VSS
DM6
VSS
DQ54
DQ55
VSS
DQ60
DQ61
VSS
DQS7#
DQS7
VSS
DQ62
DQ63
VSS
SAO
2
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
CK0
32
34
36
38
40
42
44
46
48
50
NC
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
A11
92
A7
94
A6
96
98
A4
100
A2
102
A0
104
106
BA1
108
110
S0#
112
114
116
118
120
NC
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
CK1
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
SA1
REVERSE
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
DDR_A_D4
DDR_A_D7
DDR_A_DM0
DDR_A_D6
DDR_A_D5
DDR_A_D13
DDR_A_D12
DDR_A_DM1
M_CLK_DDR0
M_CLK_DDR#0
DDR_A_D9
DDR_A_D15
DDR_A_D21
DDR_A_D20
PM_EXTTS#0_R
DDR_A_DM2
DDR_A_D19
DDR_A_D23
DDR_A_D25
DDR_A_D29
DDR_A_DQS#3
DDR_A_DQS3
DDR_A_D31
DDR_A_D30
DDR_CKE1_DIMMA
DDR_A_MA11
DDR_A_MA6
DDR_A_MA4
DDR_A_MA2
DDR_A_MA0
DDR_A_BS1
DDR_A_RAS#
DDR_CS0_DIMMA#
M_ODT0
DDR_A_MA13
DDR_A_D35
DDR_A_D32
DDR_A_DM4
DDR_A_D39
DDR_A_D38
DDR_A_D40
DDR_A_D45
DDR_A_DQS#5
DDR_A_DQS5
DDR_A_D46
DDR_A_D47
DDR_A_D52
DDR_A_D53
M_CLK_DDR1
M_CLK_DDR#1
DDR_A_DM6
DDR_A_D55
DDR_A_D54
DDR_A_D60
DDR_A_D61
DDR_A_DQS#7
DDR_A_DQS7
DDR_A_D62
DDR_A_D63
100K_0402_5%~D
12
R65
1
+0.9V_DDR_REF
100K_0402_5%~D
12
R62
2.2U_0603_6.3V6K~D
C173
1
2
M_CLK_DDR0 <10>
M_CLK_DDR#0 <10>
R118
1 2
0_0402_5%~D
DDR_CKE1_DIMMA <10>
DDR_A_BS1 <11>
DDR_A_RAS# <11>
DDR_CS0_DIMMA# <10>
M_ODT0 <10>
M_CLK_DDR1 <10>
M_CLK_DDR#1 <10>
0.1U_0402_16V4Z~D
C170
1
2
PM_EXTTS#0 <10>
PM_EXTTS#0_R <17>
+0.9V_DDR_REF <10,17,47>
DELL CONFIDENTIAL/PROPRIETARY
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
DDRII-SODIMM SLOT-A
LA-2881P
1
18 62Tuesday, December 13, 2005
2.0
of
Page 19
5
+3.3V_RUN
DVI_CLK+
0.047U_0402_16V4Z~D
1
2
1 2
C192 0.1U_0402_16V4Z~D
1 2
C176 0.1U_0402_16V4Z~D
1 2
C194 0.1U_0402_16V4Z~D
1 2
C178 0.1U_0402_16V4Z~D
1 2
C196 0.1U_0402_16V4Z~D3@
1 2
C180 0.1U_0402_16V4Z~D3@
1 2
C198 0.1U_0402_16V4Z~D3@
1 2
C182 0.1U_0402_16V4Z~D3@
1 2
C200 0.1U_0402_16V4Z~D3@
1 2
C184 0.1U_0402_16V4Z~D3@
1 2
C202 0.1U_0402_16V4Z~D3@
1 2
C186 0.1U_0402_16V4Z~D3@
1 2
C204 0.1U_0402_16V4Z~D3@
1 2
C188 0.1U_0402_16V4Z~D3@
1 2
C206 0.1U_0402_16V4Z~D3@
1 2
C190 0.1U_0402_16V4Z~D3@
C208
0.047U_0402_16V4Z~D
C209
1
DVI2_TX0+<36>
DVI2_TX0-<36>
2
DVI2_TX1+<36>
DVI2_TX1-<36>
DVI2_TX2+<36>
DVI2_TX2-<36>
DVI2_CLK+<36>
DVI2_CLK-<36>
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
+3.3V_SUS
1
C561
3@
0.1U_0603_50V4Z~D
2
+15V_SUS
RUNPWROK<37,38,40,48>
+2.5V_RUN
PEG_MTX_GRX_C_N[0..15]
PEG_MTX_GRX_C_P0
PEG_MTX_GRX_C_P1
PEG_MTX_GRX_C_P2
PEG_MTX_GRX_C_P3
PEG_MTX_GRX_C_P4
PEG_MTX_GRX_C_P5
PEG_MTX_GRX_C_P6
PEG_MTX_GRX_C_P7
PEG_MTX_GRX_C_P8
PEG_MTX_GRX_C_P9
PEG_MTX_GRX_C_P10
PEG_MTX_GRX_C_P11
PEG_MTX_GRX_C_P12
PEG_MTX_GRX_C_P13
PEG_MTX_GRX_C_P14
PEG_MTX_GRX_C_P15
0.047U_0402_16V4Z~D
C207
1
D D
PEG_MTX_GRX_C_P0
PEG_MTX_GRX_C_N0
PEG_MTX_GRX_C_P1
PEG_MTX_GRX_C_N1
PEG_MTX_GRX_C_P2
PEG_MTX_GRX_C_N2
PEG_MTX_GRX_C_P3
PEG_MTX_GRX_C_N3
PEG_MTX_GRX_C_P4
C C
B B
PEG_MTX_GRX_C_P[0..15]<12>
A A
PEG_MTX_GRX_C_N4
PEG_MTX_GRX_C_P5
PEG_MTX_GRX_C_N5
PEG_MTX_GRX_C_P6
PEG_MTX_GRX_C_N6
PEG_MTX_GRX_C_P7
PEG_MTX_GRX_C_N7
PEG_MTX_GRX_C_P8
PEG_MTX_GRX_C_N8
PEG_MTX_GRX_C_P9
PEG_MTX_GRX_C_N9
PEG_MTX_GRX_C_P10
PEG_MTX_GRX_C_N10
PEG_MTX_GRX_C_P11
PEG_MTX_GRX_C_N11
PEG_MTX_GRX_C_P12
PEG_MTX_GRX_C_N12
PEG_MTX_GRX_C_P13
PEG_MTX_GRX_C_N13
PEG_MTX_GRX_C_P14
PEG_MTX_GRX_C_N14
PEG_MTX_GRX_C_P15
PEG_MTX_GRX_C_N15
2
C191 0.1U_0402_16V4Z~D
C175 0.1U_0402_16V4Z~D
C193 0.1U_0402_16V4Z~D
C177 0.1U_0402_16V4Z~D
C195 0.1U_0402_16V4Z~D3@
C179 0.1U_0402_16V4Z~D3@
C197 0.1U_0402_16V4Z~D3@
C181 0.1U_0402_16V4Z~D3@
C199 0.1U_0402_16V4Z~D3@
C183 0.1U_0402_16V4Z~D3@
C201 0.1U_0402_16V4Z~D3@
C185 0.1U_0402_16V4Z~D3@
C203 0.1U_0402_16V4Z~D3@
C187 0.1U_0402_16V4Z~D3@
C205 0.1U_0402_16V4Z~D3@
C189 0.1U_0402_16V4Z~D3@
+GFX_PWR_SRC
PEG_MTX_GRX_C_N[0..15]<12>
PEG_MTX_GRX_C_P[0..15]
5
DVI_CLKDVI2_TX0+
DVI2_TX0DVI2_TX1+
DVI2_TX1DVI2_TX2+
DVI2_TX2DVI2_CLK+
DVI2_CLKDVI_TX0+
DVI_TX0DVI_TX1+
DVI_TX1DVI_TX2+
DVI_TX2PEG_MTX_GRX_P0
PEG_MTX_GRX_N0
PEG_MTX_GRX_P1
PEG_MTX_GRX_N1
PEG_MTX_GRX_P2
PEG_MTX_GRX_N2
PEG_MTX_GRX_P3
PEG_MTX_GRX_N3
PEG_MTX_GRX_P4
PEG_MTX_GRX_N4
PEG_MTX_GRX_P5
PEG_MTX_GRX_N5
PEG_MTX_GRX_P6
PEG_MTX_GRX_N6
PEG_MTX_GRX_P7
PEG_MTX_GRX_N7
PEG_MTX_GRX_P8
PEG_MTX_GRX_N8
PEG_MTX_GRX_P9
PEG_MTX_GRX_N9
PEG_MTX_GRX_P10
PEG_MTX_GRX_N10
PEG_MTX_GRX_P11
PEG_MTX_GRX_N11
PEG_MTX_GRX_P12
PEG_MTX_GRX_N12
PEG_MTX_GRX_P13
PEG_MTX_GRX_N13
PEG_MTX_GRX_P14
PEG_MTX_GRX_N14
PEG_MTX_GRX_P15
PEG_MTX_GRX_N15
1
3@
0.1U_0603_50V4Z~D
2
RUNPWROK
PEG_MTX_GRX_C_N0
PEG_MTX_GRX_C_N1
PEG_MTX_GRX_C_N2
PEG_MTX_GRX_C_N3
PEG_MTX_GRX_C_N4
PEG_MTX_GRX_C_N5
PEG_MTX_GRX_C_N6
PEG_MTX_GRX_C_N7
PEG_MTX_GRX_C_N8
PEG_MTX_GRX_C_N9
PEG_MTX_GRX_C_N10
PEG_MTX_GRX_C_N11
PEG_MTX_GRX_C_N12
PEG_MTX_GRX_C_N13
PEG_MTX_GRX_C_N14
PEG_MTX_GRX_C_N15
C560
4
4
JVGA
1
1
3
3
5
5
7
7
9
9
11
11
13
13
15
15
17
17
19
19
21
21
23
23
25
25
27
27
29
29
31
31
33
33
35
35
37
37
39
39
41
41
43
43
45
45
47
47
49
49
51
51
53
53
55
55
57
57
59
59
61
61
63
63
65
65
67
67
69
69
71
71
73
73
75
75
77
77
79
79
81
81
83
83
85
85
87
87
89
89
91
91
93
93
95
95
97
97
99
99
101
101
103
103
105
105
107
107
109
109
111
111
113
113
115
115
117
117
119
119
121
121
123
123
125
125
127
127
129
129
131
131
133
133
135
135
137
137
139
139
141
141
143
143
145
145
147
147
149
149
151
151
153
153
155
155
157
157
159
159
161
161
163
163
165
165
167
167
169
169
171
171
173
173
175
175
177
177
179
179
181
181
183
183
185
185
187
187
189
189
191
191
193
193
195
195
197
197
199
199
201
201
203
203
205
205
JAE_WB3M200VD1~D
2
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204
206
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204
206
YPRPB_DET#
SBAT_SMBCLK_R
SBAT_SMBDAT_R
TV_Y_VGA
TV_CVBS_VGA
TV_C_VGA
VSYNC_VGA
HSYNC_VGA
BLU_VGA
GRN_VGA
RED_VGA
CLK_DDC2_VGA
DAT_DDC2_VGA
DVI_DETECT_L
DVI_SCLK_L
DVI_SDAT_L
PLTRST_DELAY#
CLK_PCIE_VGA
CLK_PCIE_VGA#
PEG_MRX_GTX_P0
PEG_MRX_GTX_N0
PEG_MRX_GTX_P1
PEG_MRX_GTX_N1
PEG_MRX_GTX_P2
PEG_MRX_GTX_N2
PEG_MRX_GTX_P3
PEG_MRX_GTX_N3
PEG_MRX_GTX_P4
PEG_MRX_GTX_N4
PEG_MRX_GTX_P5
PEG_MRX_GTX_N5
PEG_MRX_GTX_P6
PEG_MRX_GTX_N6
PEG_MRX_GTX_P7
PEG_MRX_GTX_N7
PEG_MRX_GTX_P8
PEG_MRX_GTX_N8
PEG_MRX_GTX_P9
PEG_MRX_GTX_N9
PEG_MRX_GTX_P10
PEG_MRX_GTX_N10
PEG_MRX_GTX_P11
PEG_MRX_GTX_N11
PEG_MRX_GTX_P12
PEG_MRX_GTX_N12
PEG_MRX_GTX_P13
PEG_MRX_GTX_N13
PEG_MRX_GTX_P14
PEG_MRX_GTX_N14
PEG_MRX_GTX_P15
PEG_MRX_GTX_N15
OTBMP#
FPBACK_EN
0.1U_0603_50V4Z~D
2
1
GFX_PWR_LIMIT
3
SBAT_SMBCLK_R
SBAT_SMBDAT_R
YPRPB_DET# <20,37>
+5V_ALW
TV_Y_VGA <20>
TV_CVBS_VGA <20>
TV_C_VGA <20>
VSYNC_VGA <20>
HSYNC_VGA <20>
BLU_VGA <20>
GRN_VGA <20>
RED_VGA <20>
CLK_DDC2_VGA <20>
DAT_DDC2_VGA <20>
DVI_SCLK_L <36>
DVI_SDAT_L <36>
PLTRST_DELAY# <23>
CLK_PCIE_VGA <6>
CLK_PCIE_VGA# <6>
PEG_MTX_GRX_C_P[0..15]、PEG_MTX_GRX_C_N[0..15]
PEG_MRX_GTX_P[0..15] PEG_MRX_GTX_N[0、、..15]
are PCI-E for external GFx in ZRS.
PEG_MTX_GRX_C_P[0..3] PEG_MTX_GR、 X_C_N[0..3]、
PEG_MRX_GTX_P1 PEG、 _MRX_GTX_N1
are SDVO for DVI transmitter in ZUMA.
+3.3V_RUN
R158 0_0402_5%~D3@
1 2
OTBMP# <16>
+5V_RUN
FPBACK_EN <20,37>
0.1U_0603_50V4Z~D
0.1U_0603_50V4Z~D
0.1U_0603_50V4Z~D
3@
C552
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
2
1
3@
C551
4
+3.3V_RUN
U13
O
3
3@
C550
2
1
C224
0.1U_0402_16V4Z~D3@
5
1
P
IN1
2
IN2
G
74AHC1G08GW_SOT353-5~D3@
3
+3.3V_RUN
PEG_MRX_GTX_P0
PEG_MRX_GTX_P1
PEG_MRX_GTX_P2
PEG_MRX_GTX_P3
PEG_MRX_GTX_P4
PEG_MRX_GTX_P5
PEG_MRX_GTX_P6
PEG_MRX_GTX_P7
PEG_MRX_GTX_P8
PEG_MRX_GTX_P9
PEG_MRX_GTX_P10
PEG_MRX_GTX_P11
PEG_MRX_GTX_P12
PEG_MRX_GTX_P13
PEG_MRX_GTX_P14
PEG_MRX_GTX_P15
BIA_PWMBIA_PWM_VGA
10U_1206_25V6M~D
@
3@
C549
C553
1
2
2
1
12
1 2
R155 0_0402_5%~D3@
1 2
R157 0_0402_5%~D3@
1 2
R144 0_0402_5%~D1@
1 2
R145 0_0402_5%~D1@
C
100K_0402_5%~D
1 2
2
B
Q43
E
PMBT3904_SOT23~D
3 1
DVI_DETECT_L
12
R164
10K_0402_5%~D
PEG_MRX_GTX_P[0..15]
PEG_MRX_GTX_N0
PEG_MRX_GTX_N1
PEG_MRX_GTX_N2
PEG_MRX_GTX_N3
PEG_MRX_GTX_N4
PEG_MRX_GTX_N5
PEG_MRX_GTX_N6
PEG_MRX_GTX_N7
PEG_MRX_GTX_N8
PEG_MRX_GTX_N9
PEG_MRX_GTX_N10
PEG_MRX_GTX_N11
PEG_MRX_GTX_N12
PEG_MRX_GTX_N13
PEG_MRX_GTX_N14
PEG_MRX_GTX_N15
BIA_PWM <12,20,38>
+GFX_PWR_SRC
SIO_GFX_PWR
R160
0_0402_5%~D@
1 2
R163
DVI_DETECT
DVI_DETECT_L <36>
SIO_GFX_PWR <37>
ACAV_IN <16,38,49>
2
SBAT_SMBCLK <20,38>
SBAT_SMBDAT <20,38>
SDVO_CTRLCLK <12>
SDVO_CTRLDATA <12>
PEG_MRX_GTX_P[0..15] <12>
PEG_MRX_GTX_N[0..15]
2
DVI_TX2DVI_TX2+
DVI_SCLK
DVI_SDAT
DVI_TX1DVI_TX1+
+5V_RUN
PEG_MRX_GTX_N[0..15] <12>
1
+5V_RUN
1
2
3
4
5
6
7
9
10
11
12
8
26
27
29
31
R88
1 2
100K_0402_5%~D
DVI_SCLK_L
DVI_SDAT_L
2N7002_SOT23~D
0.1U_0603_50V4Z~D
C542
2
1
RUN_ON<38,40,45,46,47>
2 1
RB500V_SOD323~D
JDVI
DATA2#
DATA2
SHIELD24
DATA4#
DATA4
DDCCLK
DDCDATA
DATA1#
DATA1
SHIELD13
SHIELDCLK
DATA3#
CRT_VSYNC
G1
G3
G5
NC1
JAE_DV2R024NDA~D
G
2
S
G
2
13
D
S
Q22
+PWR_SRC
0.1U_0603_50V4Z~D
100K_0402_5%~D
C555
2
1
RUN_ON
D25
DATA3
VCC5
GND5
HPDET
DATA0#
DATA0
SHIELD5
DATA5#
DATA5
CLK
CLK#
NC2
Q23
2N7002_SOT23~D
13
D
R615
1 2
BLM31AJ260SN1L~D
13
14
15
16
17
18
19
20
21
22
23
24
25
G2
28
G4
30
G6
32
1
C103
220P_0402_50V7K~D
2
1
C104
220P_0402_50V7K~D
2
1
2
3
4
GPWR_SRC_ON
12
R617
100K_0402_5%~D
PEG_PWRON#
13
D
2
G
S
L6
12
DVI_DETECT
DVI_TX0DVI_TX0+
DVI_CLK+
DVI_CLK-
DVI_SCLK
DVI_SDAT
+GFX_PWR_SRC
8
7
6
5
Q92
FDS4435_NL_SO8~D
Q93
2N7002_SOT23~D
DELL CONFIDENTIAL/PROPRIETARY
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
VGA and DVI connector
LA-2881P
1
+5V_RUN
5.6K_0402_5%~D
12
19 62Tuesday, December 13, 2005
10U_0805_10V4Z~D
0.1U_0402_16V4Z~D
R93
C89
C94
1
1
2
2
5.6K_0402_5%~D
12
R94
2.0
of
Page 20
TXUCLKUT-
TXUCLKUT+
GND1
TXUOUT2-
TXUOUT2+
GND2
TXUOUT1-
TXUOUT1+
GND3
TXUOUT0-
TXUOUT0+
GND4
TXLCLKOUT-
TXLCLKOUT+
GND5
TXLOUT2TXLOUT2+
GND6
TXLOUT1TXLOUT1+
GND7
TXLOUT0TXLOUT0+
GND8
PANEL_I2C_CLK
PANEL_I2C_DAT
GND9
VEDID
GND10
LCDVDD1
LCDVDD2
PNL_SLFTST
LCDPWR_SRC
LCDPWR_SRC
LCDPWR_SRC
GND11
FPBACK
GND12
PBAT_SMBCLK
PBAT_SMBDAT
GND13
+5V_ALWF
LAMP_START
GND14
ENVDD
2
R107 0_0402_5%~D1@
R595 0_0402_5%~D3@
R104 0_0402_5%~D1@
R594 0_0402_5%~D3@
R105 0_0402_5%~D1@
R593 0_0402_5%~D3@
5
R133 0_0402_5%~D1@
+15V_SUS
12
I
5
LCD_BCLK-
44
LCD_BCLK+
43
42
LCD_B2-
41
LCD_B2+
40
39
LCD_B1-
38
LCD_B1+
37
36
LCD_B0-
35
LCD_B0+
34
33
LCD_ACLK-
32
LCD_ACLK+
31
30
LCD_A2-
29
LCD_A2+
28
27
LCD_A1-
26
LCD_A1+
25
24
LCD_A0-
23
LCD_A0+
22
21
LDDC_CLK
20
LDDC_DATA
19
18
17
16
+LCDVDD
15
14
LCD_TST
13
12
11
10
9
8
7
SBAT_SMBCLK
6
SBAT_SMBDAT
5
4
3
2
1
1
C548
M'07 inverter support - Depop D7.
2
D'05 inverter support - Populate D7.
1 2
12
R131
100K_0402_5%~D1@
R165
100K_0402_5%~D1@
2
G
1
Q44
Q42
O
G
DTC124EKA_SC59~D1@
3
TV_C DAT_DDC2
12
12
TV_CVBS
12
12
TV_Y
12
12
LCD_BCLK- <12>
LCD_BCLK+ <12>
LCD_B2- <12>
LCD_B2+ <12>
LCD_B1- <12>
LCD_B1+ <12>
LCD_B0- <12>
LCD_B0+ <12>
LCD_ACLK- <12>
LCD_ACLK+ <12>
LCD_A2- <12>
LCD_A2+ <12>
LCD_A1- <12>
LCD_A1+ <12>
LCD_A0- <12>
LCD_A0+ <12>
LDDC_CLK <12>
LDDC_DATA <12>
LCD_TST <23>
BACKLITEON
SBAT_SMBCLK <19,38>
SBAT_SMBDAT <19,38>
LAMP_D_STAT#
+GFX_PWR_SRC
0.1U_0603_50V4Z~D1@
+15V_SUS +3.3V_RUN
FPBACK_EN
PANEL_BKEN
12
R166
1@
100K_0402_5%~D
2N7002_SOT23~D1@
13
D
R172
S
RB751V_SOD323~D@
+LCDVDD
100K_0402_5%~D1@
12
DAT_DDC2_NB<12>
DAT_DDC2_VGA<19>
CLK_DDC2_NB<12>
CLK_DDC2_VGA<19>
1
IN1
2
IN2
S
4 5
0.1U_0402_16V4Z~D1@
+3.3V_RUN
1
1
C540
C547
2
2
0.1U_0402_16V4Z~D1@
0.1U_0402_16V4Z~D1@
21
D7
LAMP_STAT#
+3.3V_RUN
C706
0.1U_0402_16V4Z~D@
1 2
5
U10
P
BACKLITEON
4
O
G
74AHC1G08GW_SOT353-5~D@
3
D
6
2
1
G
Q91
1@
SI3456BDV-T1-E3_TSOP6~D
3
C545
1
2
VSYNC_VGA<19>
HSYNC_VGA<19>
BLU_NB<12>
BLU_VGA<19>
GRN_NB<12>
GRN_VGA<19>
RED_NB<12>
RED_VGA<19>
JLVDS
45
MGND1
46
MGND2
47
MGND3
48
MGND4
49
MGND5
50
MGND6
51
MGND7
56
MGND8
57
MGND9
54
MGND10
55
MGND11
D D
+LCDVDD
D
S
ENVDD<12>
TV_C_NB<12>
TV_C_VGA<19>
TV_CVBS_NB<12>
TV_CVBS_VGA<19>
TV_Y_NB<12>
TV_Y_VGA<19>
IPEX_20330-044E-11F~D1@
FPBACK_EN<19,37>
PANEL_BKEN<12>
12
R605
470_0402_5%~D1@
13
2
G
Q45
2N7002_SOT23~D1@
C C
M'07 inverter support - Populate R152, R133, Depop U10, C706.
D'05 inverter support - Populate U10, C706. Depop R152, R133.
B B
A A
+LCDVDD
+5V_ALW
1
C541
0.1U_0402_16V4Z~D1@
2
VSYNC_NB<12>
HSYNC_NB<12>
1 2
R91 0_0402_5%~D1@
R95 0_0402_5%~D3@
1 2
R97 0_0402_5%~D1@
R98 0_0402_5%~D3@
R84 0_0402_5%~D1@
R87 0_0402_5%~D3@
R78 0_0402_5%~D1@
R81 0_0402_5%~D3@
R73 0_0402_5%~D1@
R75 0_0402_5%~D3@
4
R152
1 2
0_0402_5%~D1@
LAMP_STAT# <23>
1
C539
0.1U_0402_16V4Z~D1@
2
1 2
R67 0_0402_5%~D1@
R68 0_0402_5%~D3@
1 2
R57 0_0402_5%~D1@
R64 0_0402_5%~D3@
12
CLK_DDC2
12
BLUE
12
12
GREEN
12
12
RED
12
12
4
TV_C<36>
TV_CVBS<36>
TV_Y<36>
BIA_PWM <12,19,38>
VSYNC
12
HSYNC
12
HSYNC
VSYNC
TV_C
TV_CVBS
TV_Y
RED<36>
GREEN<36>
BLUE<36>
150_0402_1%
150_0402_1%
150_0402_1%
RED
GREEN
BLUE
1 2
39_0402_5%~D
1 2
39_0402_5%~D
1 2
R707 0_0402_5%~D@
3
C709
12
R497
1
2
12
R503
1
2
12
R504
1
2
0.1U_0402_16V4Z~D
150_0402_1%
150_0402_1%
12
R17
To place the 0-ohm strapping options
for HSYNC and VSYNC (R67, R68, R57,
R64) close to the buffers (U4 , U5) to
minimize the stub lengths.
1 2
R713 0_0402_5%~D@
+CRT_VCC
R41
R42
1 2
0.47UH_CIL10NR47KNC_10%_0603~D
C414
47P_0402_50V8J~D
22P_0402_50V8J~D@
1 2
0.47UH_CIL10NR47KNC_10%_0603~D
C417
47P_0402_50V8J~D
1 2
0.47UH_CIL10NR47KNC_10%_0603~D
C422
47P_0402_50V8J~D
2
C318
1
150_0402_1%
12
12
R26
R22
DAT_DDC2<36>
CLK_DDC2<36>
1
5
P
OE#
A2Y
G
SN74AHCT1G125GW_SC70-5~D
3
5
P
A2Y
G
3
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
22P_0402_50V8J~D@
L43
C710
L44
C711
22P_0402_50V8J~D@
L45
+5V_RUN
1
5
U27
P
4
OE#
A2Y
G
SN74AHCT1G125GW_SC70-5~D
3
22P_0402_50V8J~D@
22P_0402_50V8J~D@
1
1
C23
2
2
DAT_DDC2
CLK_DDC2
1 2
1K_0402_5%~D
U4
4
0_0402_5%~D
1
U5
R756
0_0402_5%~D
4
OE#
SN74AHCT1G125GW_SC70-5~D
3
C413
C416
C421
SPDIF<26>
SPDIF_DOCKSPDIF
BLM18BB600SN1D_0603~D
BLM18BB600SN1D_0603~D
BLM18BB600SN1D_0603~D
22P_0402_50V8J~D@
1
C22
C30
2
R38
R755
47P_0402_50V8J~D
1
2
47P_0402_50V8J~D
1
2
47P_0402_50V8J~D
1
2
L1
1 2
L2
1 2
L3
1 2
C653
+3.3V_RUN
1
2
CLOSE TO JSVID
SVIDEO_C
SVIDEO_CVBS
SVIDEO_Y
+5V_RUN
0.1U_0402_16V4Z~D
2
C321
1
1
5
P
OE#
A2Y
G
SPDIF
SPDIF_DOCK <36>SPDIF<26>
U28
3
SN74AHCT1G125GW_SC70-5~D
D20
DA204U_SOT323~D@
10P_0402_50V8J~D@
C24
1
2
BLM18AG121SN1D_0603~D
BLM18AG121SN1D_0603~D
33P_0402_50V8J~D@
33P_0402_50V8J~D@
C656
1
2
2
1 2
1 2
2
D12
DA204U_SOT323~D@
1
2
+3.3V_RUN
C413,C414,C416,C417,C421,C422 pop
82pF and L43,L44,L45 pop 1.8uH for UMA
SPDIF_SHDN
1
3
L4
L5
SP_DIF
4
+CRT_VCC
SPDIF_SHDN <26,37>
R419
220_0603_1%~D
D19
DA204U_SOT323~D@
10P_0402_50V8J~D@
C25
1
2
1K_0402_5%~D@
12
R39
22P_0402_50V8J~D
C40
1
2
2
1K_0402_5%~D@
22P_0402_50V8J~D
SP_DIFB
12
1
3
2.2K_0402_5%~D
12
R32
C33
1
2
2
3
C319
12
0.01U_0402_16V7K~D
D18
DA204U_SOT323~D@
1
2
3
10P_0402_50V8J~D@
C29
1
2
2.2K_0402_5%~D
R18
1 2
1 2
HSYNC_DOCK <36>
VSYNC_DOCK <36>
Place R755 near U4 and R756 near U5.
D11
DA204U_SOT323~D@
1
2
SP_DIF_C
R43
110_0603_1%~D
12
R417
POPULATE R387 WHEN COMPONENT VIDEO IS ENABLED.
DE-POPULA T E R397 WHEN COMPONENT VIDEO IS ENABLED.
3
R416
1 2
0_0805_5%~D
300P_1808_3000V8K~D@
+5V_RUN
D10
DA204U_SOT323~D@
1
2
SP_DIF_D
C304
21
D17
RB500V_SOD323~D
+CRT_VCC
0.01U_0402_16V7K~D
1
2
R
DAT_DDC2
G
JVGA_HS
B
JVGA_VS
M_ID2#
CLK_DDC2
T23 PAD~D
1
C654
0.1U_0402_16V4Z~D
2
3
C655
1
JSVID
2
4
6
7
5
3
1
8
9
FOX_MH11777-BUR6-7F~D
+3.3V_RUN
10K_0402_5%~D
12
R602
R387
1 2
12
0_0805_5%~D3@
1
R397
0_0805_5%~D1@
2
YPRPB_DET# <19,37>
JCRT
6
11
1
7
12
2
8
13
3
9
14
4
10
15
5
FOX_DZ11A91-ND201-7F~D
DELL CONFIDENTIAL/PROPRIETARY
Title
Interval LVDS, TV_OUT and CRT connector
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
LA-2881P
20 62Tuesday, December 13, 2005
1
18
19
2.0
of
Page 21
5
+3.3V_RUN
D D
C C
1 2
R332 8.2K_0402_5%~D
1 2
R352 8.2K_0402_5%~D
1 2
R333 8.2K_0402_5%~D
1 2
R334 8.2K_0402_5%~D
1 2
R331 8.2K_0402_5%~D
1 2
R328 8.2K_0402_5%~D
1 2
R349 8.2K_0402_5%~D
1 2
R330 8.2K_0402_5%~D
+3.3V_RUN
1 2
R344 8.2K_0402_5%~D
1 2
R327 8.2K_0402_5%~D
1 2
R346 8.2K_0402_5%~D
1 2
R345 8.2K_0402_5%~D
1 2
R533 8.2K_0402_5%~D
1 2
R536 8.2K_0402_5%~D
1 2
R532 8.2K_0402_5%~D
1 2
R535 8.2K_0402_5%~D
1 2
R347 8.2K_0402_5%~D
1 2
R353 8.2K_0402_5%~D
1 2
R335 8.2K_0402_5%~D
1 2
R350 8.2K_0402_5%~D
1 2
R351 8.2K_0402_5%~D
1 2
R348 8.2K_0402_5%~D
PCI_DEVSEL#
PCI_STOP#
PCI_TRDY#
PCI_FRAME#
PCI_PLOCK#
PCI_IRDY#
PCI_SERR#
PCI_PERR#
PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#
ICH_GPIO2_PIRQE#
ICH_GPIO3_PIRQF#
ICH_GPIO4_PIRQG#
ICH_GPIO5_PIRQH#
PCI_REQ0#
PCI_REQ1#
PCI_REQ2#
PCI_REQ3#
PCI_REQ4#
PCI_REQ5#
PCI_AD[0..31]<30,31,33,35>
4
PCI_AD0 PCI_REQ0#
PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD6
PCI_AD7
PCI_AD8
PCI_AD9
PCI_AD10
PCI_AD11
PCI_AD12
PCI_AD13
PCI_AD14
PCI_AD15
PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20
PCI_AD21
PCI_AD22
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30
PCI_AD31
PCI_PIRQA#<35>
PCI_PIRQB#<31>
PCI_PIRQC#<33>
PCI_PIRQD#<33>
PCI_PIRQA# ICH_GPIO2_PIRQE#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#
U19B
E18
AD0
C18
AD1
A16
AD2
F18
AD3
E16
AD4
A18
AD5
E17
AD6
A17
AD7
A15
AD8
C14
AD9
E14
AD10
D14
AD11
B12
AD12
C13
AD13
G15
AD14
G13
AD15
E12
AD16
C11
AD17
D11
AD18
A11
AD19
A10
AD20
F11
AD21
F10
AD22
E9
AD23
D9
AD24
B9
AD25
A8
AD26
A6
AD27
C7
AD28
B6
AD29
E6
AD30
D6
AD31
Interrupt I/F
A3
PIRQA#
B4
PIRQB#
C5
PIRQC#
B5
PIRQD#
AE5
RSVD[1]
AD5
RSVD[2]
AG4
RSVD[3]
AH4
RSVD[4]
AD9
RSVD[5]
PCI
REQ4# / GPIO22
GNT4# / GPIO48
GPIO1 / REQ5#
GPIO17 / GNT5#
GPIO2 / PIRQE#
GPIO3 / PIRQF#
GPIO4 / PIRQG#
GPIO5 / PIRQH#
MISC
MCH_SYNC#
ICH7M B0_BGA 6 52~D
REQ0#
GNT0#
REQ1#
GNT1#
REQ2#
GNT2#
REQ3#
GNT3#
C/BE0#
C/BE1#
C/BE2#
C/BE3#
IRDY#
PCIRST#
DEVSEL#
PERR#
PLOCK#
SERR#
STOP#
TRDY#
FRAME#
PLTRST#
PCICLK
PME#
RSVD[6]
RSVD[7]
RSVD[8]
RSVD[9]
PAR
D7
E7
C16
D16
C17
D17
E13
F13
A13
A14
C8
D8
B15
C12
D12
C15
A7
E10
B18
A12
C9
E11
B10
F15
F14
F16
C26
A9
B19
G8
ICH_GPIO3_PIRQF#
F7
ICH_GPIO4_PIRQG#
F8
ICH_GPIO5_PIRQH#
G7
AE9
AG8
AH8
F21
MCH_ICH_SYNC#
AH20
3
PCI_GNT0#
PCI_REQ1#
PCI_REQ2#
PCI_GNT2#
PCI_REQ3#
PCI_GNT3#
PCI_REQ4#
PCI_GNT4#
PCI_REQ5#
PCI_GNT5#
PCI_C_BE0#
PCI_C_BE1#
PCI_C_BE2#
PCI_C_BE3#
PCI_IRDY#
PCI_PAR
PCI_PCIRST#
PCI_DEVSEL#
PCI_PERR#
PCI_PLOCK#
PCI_SERR#
PCI_STOP#
PCI_TRDY#
PCI_FRAME#
PCI_PLTRST#
CLK_PCI_ICH
ICH_PME#
PCI_REQ0# <36>
PCI_GNT0# <35,36>
PCI_REQ2# <33>
PCI_GNT2# <33>
PCI_REQ3# <31>
PCI_GNT3# <31>
PCI_C_BE0# <31,33,35>
PCI_C_BE1# <30,33,35>
PCI_C_BE2# <31,33,35>
PCI_C_BE3# <31,33,35>
PCI_IRDY# <31,33,35,36>
PCI_PAR <30,33,35>
PCI_DEVSEL# <31,33,35>
PCI_PERR# <31,33,35>
PCI_PLOCK# <35>
PCI_SERR# <31,33,35>
PCI_STOP# <30,33,35>
PCI_TRDY# <31,33,35>
PCI_FRAME# <31,33,35,36>
CLK_PCI_ICH <6>
ICH_PME# <37>
MCH_ICH_SYNC# <10>
2
PCI_PCIRST#
PCI_PLTRST#
+3.3V_SUS
14
U22A
1
P
IN1
OUT
2
IN2
G
74VHC08MTCX_NL_TSSOP14~D
7
+3.3V_SUS
14
U22B
4
P
IN1
OUT
5
IN2
G
74VHC08MTCX_NL_TSSOP14~D
7
+3.3V_SUS
14
U22C
10
P
IN1
OUT
9
IN2
G
74VHC08MTCX_NL_TSSOP14~D
7
+3.3V_SUS
14
U22D
13
P
IN1
OUT
12
IN2
G
74VHC08MTCX_NL_TSSOP14~D
7
C295
0.1U_0402_16V4Z~D
PCI_RST#
3
PLTRST1#
6
PLTRST2#
8
PLTRST3#
11
1
PCI_RST# <30,33,34,35>
PLTRST1# <10,23,30>
PLTRST2# <34,37,38>
PLTRST3# <34>
B B
+COINCELL
12
R40
1K_0402_5%~D
C46
1 2
0.1U_0402_16V4Z~D@
12
R322
1K_0402_5%~D
ICH Boot BIOS select
+COINCELL
A A
+COINCELL
JCOIN
1
1
2
2
MOLEX_53398-0290~D
+3.3V_RTC_LDO
3
COINCELL_R
2
1
D1
BAT54C-7-F_SOT23~D
1
2
C44
1U_0603_10V4Z~D
+RTC_CELL
LPC
PCI
SPI
*
11
10
01
GNT5#
R322
unstuff
unstuff stuff
stuff
PCI_GNT4#PCI_GNT5#
GNT4#
R323
unstuff
unstuff
12
R323
1K_0402_5%~D@
Place closely pin U19.A9
CLK_PCI_ICH
R329
10_0402_5%~D@
1 2
CLK_ICH_TERM
1
C285
8.2P_0402_50V8J~D@
2
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
ICH7-M(1/4)
LA-2881P
21 62Tuesday, December 13, 2005
1
2.0
of
Page 22
5
4
3
2
1
D D
+RTC_CELL
12
R557
1M_0402_5%~D
INTRUDER#
ICH_INTVRMEN
12
R548
0_0402_1%@
C C
+3.3V_RUN
R591
SATA_ACT#
12
10K_0402_5%~D@
B B
+3.3V_RUN
R197
8.2K_0402_5%~D
R36
1 2
4.7K_0402_5%~D
Place near ICH7 side.
IDE_IRQ
12
IDE_DIORDY
Package
9.6X4.06 mm
32.768K_12.5PF_Q13MC30610003~D
ICH_AZ_MDC_BITCLK<28>
ICH_AZ_MDC_SYNC<28>
ICH_AZ_MDC_RST#<28>
ICH_AZ_CODEC_SDIN0<26>
ICH_AZ_MDC_SDIN1<28>
ICH_AZ_MDC_SDOUT<28>
SATA_TX0-<25>
SATA_TX0+<25>
C257
12P_0402_50V8J~D
C256
12P_0402_50V8J~D
+RTC_CELL
1
CMOS_CLR @SHORT PADS~D
SATA_ACT#<39>
SATA_RX0-<25>
SATA_RX0+<25>
C233 3900P_0402_50V7K~D
C234 3900P_0402_50V7K~D
CLK_PCIE_SATA#<6>
CLK_PCIE_SATA<6>
IDE_DIORDY<25>
IDE_IRQ<25>
IDE_DDACK#<25>
IDE_DIOW#<25>
IDE_DIOR#<25>
12
Y2
12
1 2
20K_0402_5%~D
INTRUDER#
1
C562
1 2
1U_0603_10V4Z~D
C259
27P_0402_50V8J~D@
12
12
ICH_RTCX1
1 4
2 3
R266
1 2
R560
2
12
0_0402_5%~D
1 2
R549 332K_0402_1%~D
2
R274
33_0402_5%~D
1 2
1 2
R545 33_0402_5%~D
1 2
R299 33_0402_5%~D
1 2
R297 33_0402_5%~D
1 2
R184 24.9_0402_1%~D
Within 500 mils
12
R267
10M_0402_5%~D
ICH_RTCX2
ICH_RTCRST#
ICH_INTVRMEN
ICH_AZ_BITCLK_R
ICH_AZ_SYNC_R
ICH_AZ_RST_R#
ICH_AZ_CODEC_SDIN0
ICH_AZ_MDC_SDIN1
ICH_AZ_SDOUT_R
SATA_ACT#
SATA_RX0SATA_RX0+
SATA_TX0-_N0
SATA_TX0+_P0
CLK_PCIE_SATA#
CLK_PCIE_SATA
IDE_DIORDY
IDE_IRQ
IDE_DDACK#
IDE_DIOW#
IDE_DIOR#
AB1
AB2
AA3
AF18
AF3
AE3
AG2
AH2
AF7
AE7
AG6
AH6
AF1
AE1
AH10
AG10
AG16
AH16
AF16
AH15
AF15
W4
Y5
W1
Y1
Y2
W3
V3
U3
U5
V4
T5
U7
V6
V7
U1
R6
R5
T2
T3
T1
T4
U19A
RTCX1
RTCX2
RTCRST#
INTVRMEN
INTRUDER#
EE_CS
EE_SHCLK
EE_DOUT
EE_DIN
LAN_CLK
LAN_RSTSYNC
LAN_RXD0
LAN_RXD1
LAN_RXD2
LAN_TXD0
LAN_TXD1
LAN_TXD2
ACZ_BCLK
ACZ_SYNC
ACZ_RST#
ACZ_SDIN0
ACZ_SDIN1
ACZ_SDIN2
ACZ_SDOUT
SATALED#
SATA0RXN
SATA0RXP
SATA0TXN
SATA0TXP
SATA2RXN
SATA2RXP
SATA2TXN
SATA2TXP
SATA_CLKN
SATA_CLKP
SATARBIASN
SATARBIASP
IORDY
IDEIRQ
DDACK#
DIOW#
DIOR#
RTC
LAD0
LAD1
LAD2
LAD3
LDRQ0#
LPCCPU
LDRQ1# / GPIO23
LFRAME#
LAN
A20GATE
A20M#
CPUSLP#
TP1 / DPRSTP#
TP2 / DPSLP#
FERR#
GPIO49 / CPUPWRGD
IGNNE#
INIT3_3V#
INIT#
INTR
AC-97/AZALIA
RCIN#
SMI#
STPCLK#
THERMTRIP#
DCS1#
DCS3#
SATA
DD10
DD11
DD12
DD13
IDE
DD14
DD15
DDREQ
ICH7M B0_BGA 6 52~D
NMI
DA0
DA1
DA2
DD0
DD1
DD2
DD3
DD4
DD5
DD6
DD7
DD8
DD9
AA6
AB5
AC4
Y6
AC3
AA5
AB3
AE22
AH28
AG27
AF24
AH25
AG26
AG24
AG22
AG21
AF22
AF25
AG23
AF23
AH24
AH22
AF26
AH17
AE17
AF17
AE16
AD16
AB15
AE14
AG13
AF13
AD14
AC13
AD12
AC12
AE12
AF12
AB13
AC14
AF14
AH13
AH14
AC15
AE15
LPC_LAD0
LPC_LAD1
LPC_LAD2
LPC_LAD3
LPC_LDRQ0#
LPC_LDRQ1#
LPC_LFRAME#
SIO_A20GATE
H_A20M#
H_DPRSTP_R#
H_DPSLP#
H_FERR#
H_PWRGOOD
H_IGNNE#
H_INIT#
H_INTR
SIO_RCIN#
H_SMI#
H_NMI
H_STPCLK#
THRMTRIP_ICH#
IDE_DA0
IDE_DA1
IDE_DA2
IDE_DCS1#
IDE_DCS3#
IDE_DD0
IDE_DD1
IDE_DD2
IDE_DD3
IDE_DD4
IDE_DD5
IDE_DD6
IDE_DD7
IDE_DD8
IDE_DD9
IDE_DD10
IDE_DD11
IDE_DD12
IDE_DD13
IDE_DD14
IDE_DD15
IDE_DDREQ
LPC_LAD0 <30,37,38>
LPC_LAD1 <30,37,38>
LPC_LAD2 <30,37,38>
LPC_LAD3 <30,37,38>
LPC_LDRQ0# <37>
LPC_LDRQ1# <37>
LPC_LFRAME# <30,37,38>
SIO_A20GATE <38>
H_A20M# <7>
R587 0_0402_5%~D@
R586 0_0402_5%~D
H_DPSLP# <7>
H_FERR# <7>
H_PWRGOOD <7>
H_IGNNE# <7>
H_INIT# <7>
H_INTR <7>
SIO_RCIN# <38>
H_SMI# <7>
H_NMI <7>
H_STPCLK# <7>
IDE_DA0 <25>
IDE_DA1 <25>
IDE_DA2 <25>
IDE_DCS1# <25>
IDE_DCS3# <25>
IDE_DD[0..15]
IDE_DDREQ <25>
12
12
H_CPUSLP#H_CPUSLP_R#
H_DPRSTP#
H_CPUSLP# <7,10>
H_DPRSTP# <7,48>
56_0402_5%~D
1 2
1
C535
@
0.1U_0402_16V4Z~D
2
IDE_DD[0..15] <25>
R584
H_DPRSTP# daisy
ICH7-M -- > Yonah --> IMVP6
SIO_A20GATE
+1.05V_VCCP
SIO_RCIN#
H_FERR#
R186
10K_0402_5%~D
R187
10K_0402_5%~D
R577
56_0402_5%~D
+3.3V_RUN
12
12
+1.05V_VCCP
12
ICH_AZ_CODEC_SDOUT<26>
ICH_AZ_CODEC_SYNC<26>
A A
5
ICH_AZ_CODEC_RST#<26>
ICH_AZ_CODEC_BITCLK<26>
27P_0402_50V8J~D@
R286 33_0402_5%~D
R544 33_0402_5%~D
R300 33_0402_5%~D
1
C260
2
Close to U19
1 2
1 2
1 2
R275
1 2
33_0402_5%~D
ICH_AZ_SDOUT_R
ICH_AZ_SYNC_R
ICH_AZ_RST_R#
ICH_AZ_BITCLK_R
4
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
DELL CONFIDENTIAL/PROPRIETARY
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
ICH7-M(2/4)
LA-2881P
22 62Tuesday, December 13, 2005
1
of
2.0
Page 23
5
+3.3V_RUN
SIO_THRM#
IRQ_SERIRQ
BT_RADIO_DIS#
LAMP_STAT#
SIO_EXT_SMI#
SIO_EXT_SCI#
SIO_SLP_S3#
12
LINKALERT#
SMBALERT#
ICH_BATLOW#
ICH_PCIE_W AKE#
LED_FAULT_DET
+3.3V_SUS
CLKRUN#
12
R198
10_0402_5%~D@
R326
10K_0402_5%~D
1 2
(PCI Express Wake Event)
Reserved for Rikers Use Only
R343
10K_0402_5%~D
1 2
SIO_EXT_WAKE#<38>
1 2
R598 8.2K_0402_5%~D@
1 2
R185 10K_0402_5%~D
1 2
D D
C C
R597 8.2K_0402_5%~D
1 2
R562 10K_0402_5%~D
1 2
R554 10K_0402_5%~D
+3.3V_SUS
1 2
R354 10K_0402_5%~D
1 2
R336 10K_0402_5%~D
R325 10K_0402_5%~D@
1 2
R339 10K_0402_5%~D
1 2
R357 10K_0402_5%~D
1 2
R355 8.2K_0402_5%~D
1 2
R337 680_0402_5%~D
1 2
R338 10K_0402_5%~D@
ICH_SMBCLK<6,30,34>
ICH_SMBDATA<6,30,34>
4
+3.3V_SUS
12
12
R356
2.2K_0402_5%~D
+3.3V_SUS
LED_FAULT_DET<41>
1 2
R340 8.2K_0402_5%~D
SPKR<27>
ITP_DBRESET#<7,38>
PM_BMBUSY#<10>
H_STP_PCI#<6>
H_STP_CPU#<6>
LCD_TST<20>
IDE_RST_MOD<25>
CLKRUN#<31,33,37,38>
BT_RADIO_DIS#<28>
ICH_PCIE_WAKE#<37>
IRQ_SERIRQ<30,33,37,38>
SIO_THRM#<38>
IMVP_PWRGD<40,48>
R181 0_0402_5%~D
1 2
LAMP_STAT#<20>
SIO_EXT_SMI#<38>
R324
2.2K_0402_5%~D
ICH_SMBCLK
ICH_SMBDATA
LINKALERT#
ICH_SMLINK0
ICH_SMLINK1
ICH_RI#
SPKR
ITP_DBRESET#
PM_BMBUSY#
SMBALERT#
H_STP_PCI#
H_STP_CPU#
LCD_TST
LED_FAULT_DET
IDE_RST_MOD
CLKRUN#
BT_RADIO_DIS#
ICH_PCIE_W AKE#
IRQ_SERIRQ
SIO_THRM#
IMVP_PWRGD
LAMP_STAT#
SIO_EXT_SMI#
U19C
C22
SMBCLK
B22
SMBDATA
A26
LINKALERT#
B25
SMLINK0
A25
SMLINK1
A28
RI#
A19
SPKR
A27
SUS_STAT#
A22
SYS_RST#
AB18
GPIO0 / BM_BUSY#
B23
GPIO11 / SMBALERT#
AC20
GPIO18 / STPPCI#
AF21
GPIO20 / STPCPU#
A21
GPIO26
B21
GPIO27
E23
GPIO28
AG18
GPIO32 / CLKRUN#
AC19
GPIO33 / AZ_DOCK_EN#
U2
GPIO34 / AZ_DOCK_RST#
F20
WAKE#
AH21
SERIRQ
AF20
THRM#
AD22
VRMPWRGD
AC21
GPIO6
AC18
GPIO7
E21
GPIO8
3
SMB
SYS
GPIO
GPIO
GPIO21 / SATA0GP
GPIO19 / SATA1GP
GPIO36 / SATA2GP
GPIO37 / SATA3GP
SATA
GPIO
Clocks
GPIO16 / DPRSLPVR
TP0 / BATLOW#
POWER MGT
SATACLKREQ#/GPIO35
ICH7M B0_BGA 6 52~D
CLK14
CLK48
SUSCLK
SLP_S3#
SLP_S4#
SLP_S5#
PWROK
PWRBTN#
LAN_RST#
RSMRST#
GPIO9
GPIO10
GPIO12
GPIO13
GPIO14
GPIO15
GPIO24
GPIO25
GPIO38
GPIO39
AF19
AH18
AH19
AE19
AC1
B2
C20
B24
D23
F22
AA4
AC22
C21
C23
C19
Y4
E20
A20
F19
E19
R4
E22
R3
D20
AD21
AD20
AE20
+3.3V_RUN
12
R580
SATA0GP
CLK_ICH_14M
CLK_ICH_48M
ICH_SUSCLK
SIO_SLP_S3#
SIO_SLP_S5#
ICH_PWRGD
DPRSLPVR
ICH_BATLOW#
SIO_PWRBTN#
PLTRST1#
SUSPWROK
SIO_EXT_SCI#
RSVD_HDD_DET#
HDDC_EN#
MODC_EN#
GPIO24
SATA_CLKREQ#
PLTRST_DELAY#
8.2K_0402_5%~D
CLK_ICH_14M <6>
CLK_ICH_48M <6>
T7 PAD~D
SIO_SLP_S3# <38>
T8 PAD~D
SIO_SLP_S5# <38>
ICH_PWRGD <10,40>
DPRSLPVR <10,48>
SIO_PWRBTN# <38>
PLTRST1# <10,21,30>
SUSPWROK <16,40>
SIO_EXT_SCI# <38>
T9 PAD~D
HDDC_EN# <25>
MODC_EN# <25>
T10 PAD~D
SATA_CLKREQ# <6>
PLTRST_DELAY# <19>
2
HDDC_EN#
MODC_EN#
R559
1 2
10K_0402_5%~D
R553
1 2
10K_0402_5%~D
1 2
R783 100K_0402_5%~D@
1 2
R784 100K_0402_5%~D@
+3.3V_SUS
1
Place closely pin U19.AC1
CLK_ICH_14M
12
R561
10_0402_5%~D@
1
C515
4.7P_0402_50V8C~D@
2
Place closely pin U19.B2
CLK_ICH_48M
12
R526
10_0402_5%~D@
1
C448
4.7P_0402_50V8C~D@
2
U19D
F26
PERn1
F25
DPRSLPVR
12
R567
100K_0402_5%~D
B B
IMVP_PWRGD
1
C713
0.1U_0402_16V4Z~D
2
Mini Card--->
GIGA LA N--->
Express Card--->
Place close to pin AD22 of U19
+3.3V_SUS
USB_OC3#
USB_OC0#
A A
USB_OC1#
USB_OC2#
USB_OC6#
USB_OC7#
USB_OC4#
USB_OC5#
4 5
3 6
2 7
1 8
10K_1206_8P4R_5%~D
4 5
3 6
2 7
1 8
10K_1206_8P4R_5%~D
5
RP7
RP8
PCIE_RX2-<34>
PCIE_RX2+<34>
PCIE_TX2-<34>
PCIE_TX2+<34>
PCIE_RX3-<30>
PCIE_RX3+<30>
PCIE_TX3-<30>
PCIE_TX3+<30>
PCIE_RX4-<34>
PCIE_RX4+<34>
PCIE_TX4-<34>
PCIE_TX4+<34>
ICH_EC_SPI_CLK<38>
SPI_CS#<38>
ICH_EC_SPI_DO<38>
ICH_EC_SPI_DIN<38>
C274 0.1U_0402_16V4Z~D
1 2
C275 0.1U_0402_16V4Z~D
1 2
C269 0.1U_0402_16V4Z~D
1 2
C272 0.1U_0402_16V4Z~D
1 2
C266 0.1U_0402_16V4Z~D
1 2
C267 0.1U_0402_16V4Z~D
1 2
R542
ICH_EC_SPI_CLK
SPI_CS#
ICH_EC_SPI_DO
ICH_EC_SPI_DIN
1 2
4
R546
47_0402_5%~D
10K_0402_5%~D
1 2
1 2
R541 47_0402_5%~D
USB_OC1#<29>
USB_OC2#<29>
USB_OC3#<29>
USB_OC4#<29>
USB_OC5#<29>
USB_OC6#<29>
PCIE_RX2PCIE_RX2+
PCIE_TX2-_N2
PCIE_TX2+_P2
PCIE_RX3PCIE_RX3+
PCIE_TX3-_N3
PCIE_TX3+_P3
PCIE_RX4PCIE_RX4+
PCIE_TX4-_N4
PCIE_TX4+_P4
+3.3V_SUS+3.3V_SUS +3.3V_SUS
R538
R537
10K_0402_5%~D
1 2
USB_OC0#
USB_OC1#
USB_OC2#
USB_OC3#
USB_OC4#
USB_OC5#
USB_OC6#
USB_OC7#
PERp1
E28
PETn1
E27
PETp1
H26
PERn2
H25
PERp2
G28
PETn2
G27
PETp2
K26
PERn3
K25
PERp3
J28
PETn3
J27
PETp3
M26
PERn4
M25
PERp4
L28
PETn4
L27
PETp4
P26
PERn5
P25
PERp5
N28
PETn5
N27
PETp5
T25
PERn6
T24
PERp6
R28
PETn6
R27
PETp6
10K_0402_5%~D
1 2
R2
SPI_CLK
P6
SPI_CS#
P1
SPI_ARB
P5
SPI_MOSI
P2
SPI_MISO
D3
OC0#
C4
OC1#
D5
OC2#
D4
OC3#
E5
OC4#
C3
OC5# / GPIO29
A2
OC6# / GPIO30
B3
OC7# / GPIO31
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
DMI0RXN
DMI0RXP
DMI0TXN
DMI0TXP
DMI1RXN
DMI1RXP
DMI1TXN
DMI1TXP
PCI-EXPRESS
DMI2RXN
DMI2RXP
DMI2TXN
DMI2TXP
DMI3RXN
DMI3RXP
DMI3TXN
DMI3TXP
DMI_CLKN
DMI_CLKP
DIRECT MEDIA INTERFACE
DMI_ZCOMP
DMI_IRCOMP
SPI
USB
USBRBIAS#
USBRBIAS
ICH7M B0_BGA 6 52~D
3
USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4N
USBP4P
USBP5N
USBP5P
USBP6N
USBP6P
USBP7N
USBP7P
V26
V25
U28
U27
Y26
Y25
W28
W27
AB26
AB25
AA28
AA27
AD25
AD24
AC28
AC27
AE28
AE27
C25
D25
F1
F2
G4
G3
H1
H2
J4
J3
K1
K2
L4
L5
M1
M2
N4
N3
D2
D1
DMI_MTX_IRX_N0
DMI_MTX_IRX_P0
DMI_MRX_ITX_N0
DMI_MRX_ITX_P0
DMI_MTX_IRX_N1
DMI_MTX_IRX_P1
DMI_MRX_ITX_N1
DMI_MRX_ITX_P1
DMI_MTX_IRX_N2
DMI_MTX_IRX_P2
DMI_MRX_ITX_N2
DMI_MRX_ITX_P2
DMI_MTX_IRX_N3
DMI_MTX_IRX_P3
DMI_MRX_ITX_N3
DMI_MRX_ITX_P3
CLK_PCIE_ICH#
CLK_PCIE_ICH
DMI_IRCOMP
USBP0-
USBP0+
USBP1USBP1+
USBP2USBP2+
USBP3USBP3+
USBP4USBP4+
USBP5USBP5+
USBP6USBP6+
USBP7USBP7+
USBRBIAS
DMI_MTX_IRX_N0 <10>
DMI_MTX_IRX_P0 <10>
DMI_MRX_ITX_N0 <10>
DMI_MRX_ITX_P0 <10>
DMI_MTX_IRX_N1 <10>
DMI_MTX_IRX_P1 <10>
DMI_MRX_ITX_N1 <10>
DMI_MRX_ITX_P1 <10>
DMI_MTX_IRX_N2 <10>
DMI_MTX_IRX_P2 <10>
DMI_MRX_ITX_N2 <10>
DMI_MRX_ITX_P2 <10>
DMI_MTX_IRX_N3 <10>
DMI_MTX_IRX_P3 <10>
DMI_MRX_ITX_N3 <10>
DMI_MRX_ITX_P3 <10>
CLK_PCIE_ICH# <6>
CLK_PCIE_ICH <6>
USBP0- <37>
USBP0+ <37>
USBP1- <29>
USBP1+ <29>
USBP2- <29>
USBP2+ <29>
USBP3- <29>
USBP3+ <29>
USBP4- <29>
USBP4+ <29>
USBP5- <29>
USBP5+ <29>
USBP6- <29>
USBP6+ <29>
USBP7- <36>
USBP7+ <36>
R317 22.6_0402_1%~D
1 2
Within 500 mils
R534 24.9_0402_1%~D
1 2
Within 500 mils
2
+1.5V_RUN
DELL CONFIDENTIAL/PROPRIETARY
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
ICH7-M(3/4)
LA-2881P
23 62Tuesday, December 13, 2005
1
2.0
of
Page 24
5
4
3
2
1
ICH_V5REF_RUN
L49
1 2
@
L14
1 2
0.1U_0402_16V4Z~D
C518
1
2
+3.3V_SUS
0.1U_0402_16V4Z~D
+1.5VRUN_L
1
+
C494
2
220U_D2_4VM~D
1
C533
0.1U_0402_16V4Z~D
2
+1.5V_DMIPLL
C516
1
+3.3V_RUN
2
0.1U_0402_16V4Z~D
C465
+1.5VRUN_L
0.1U_0402_16V4Z~D
C495
1
2
0.1U_0402_16V4Z~D
+1.5V_DMIPLL
10U_0805_4VAM~D
0.01U_0402_16V7K~D
C251
1
2
+VCCSATAPLL
C527
1
+1.5V_RUN
2
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
C474
1
2
+3.3V_RUN
1
C280
2
C254
1
2
0.1U_0402_16V4Z~D
+VCCSATAPLL
1
2
1U_0603_10V4Z~D
1
C452
2
0.1U_0402_16V4Z~D
ICH_V5REF_SUS
0.1U_0402_16V4Z~D
C483
1
2
+1.5V_RUN
1
C514
2
+1.5V_RUN
1
C519
2
+3.3V_SUS
1
C498
2
ICH_V5REF_RUN
@
@
+1.5V_DMIPLLR
10U_LB2012T100MR_20%_0805~D
1 2
L50
+1.5V_RUN
BLM21PG600SN1D_0805~D
1
C471
0.1U_0402_16V4Z~D
2
1
C469
0.1U_0402_16V4Z~D
2
BLM18AG601SN1D_0603~D
10U_0805_4VAM~D
D D
+3.3V_RUN+5V_RUN
21
12
12
+1.5V_RUN
+VCCSATAPLLR
D16
RB751V_SOD323~D
1
C480
1U_0603_10V4Z~D
2
+3.3V_SUS+5V_SUS
21
D9
RB751V_SOD323~D
ICH_V5REF_SUS
1
C284
1U_0603_10V4Z~D
2
R269
1 2
0.5_0805_1%~D
R596
100_0402_5%~D
C C
B B
+1.5V_RUN
A A
R342
10_0402_5%~D
R581
1 2
0.5_0805_1%~D
U19F
G10
V5REF[1]
AD17
V5REF[2]
F6
V5REF_Sus
AA22
Vcc1_5_B[1]
AA23
Vcc1_5_B[2]
AB22
Vcc1_5_B[3]
AB23
Vcc1_5_B[4]
AC23
Vcc1_5_B[5]
AC24
Vcc1_5_B[6]
AC25
Vcc1_5_B[7]
AC26
Vcc1_5_B[8]
AD26
Vcc1_5_B[9]
AD27
Vcc1_5_B[10]
AD28
Vcc1_5_B[11]
D26
Vcc1_5_B[12]
D27
Vcc1_5_B[13]
D28
Vcc1_5_B[14]
E24
Vcc1_5_B[15]
E25
Vcc1_5_B[16]
E26
Vcc1_5_B[17]
F23
Vcc1_5_B[18]
F24
Vcc1_5_B[19]
G22
Vcc1_5_B[20]
G23
Vcc1_5_B[21]
H22
Vcc1_5_B[22]
H23
Vcc1_5_B[23]
J22
Vcc1_5_B[24]
J23
Vcc1_5_B[25]
K22
Vcc1_5_B[26]
K23
Vcc1_5_B[27]
L22
Vcc1_5_B[28]
L23
Vcc1_5_B[29]
M22
Vcc1_5_B[30]
M23
Vcc1_5_B[31]
N22
Vcc1_5_B[32]
N23
Vcc1_5_B[33]
P22
Vcc1_5_B[34]
P23
Vcc1_5_B[35]
R22
Vcc1_5_B[36]
R23
Vcc1_5_B[37]
R24
Vcc1_5_B[38]
R25
Vcc1_5_B[39]
R26
Vcc1_5_B[40]
T22
Vcc1_5_B[41]
T23
Vcc1_5_B[42]
T26
Vcc1_5_B[43]
T27
Vcc1_5_B[44]
T28
Vcc1_5_B[45]
U22
Vcc1_5_B[46]
U23
Vcc1_5_B[47]
V22
Vcc1_5_B[48]
V23
Vcc1_5_B[49]
W22
Vcc1_5_B[50]
W23
Vcc1_5_B[51]
Y22
Vcc1_5_B[52]
Y23
Vcc1_5_B[53]
B27
Vcc3_3[1]
AG28
VccDMIPLL
AB7
Vcc1_5_A[1]
AC6
Vcc1_5_A[2]
AC7
Vcc1_5_A[3]
AD6
Vcc1_5_A[4]
AE6
Vcc1_5_A[5]
AF5
Vcc1_5_A[6]
AF6
Vcc1_5_A[7]
AG5
Vcc1_5_A[8]
AH5
Vcc1_5_A[9]
AD2
VccSATAPLL
AH11
Vcc3_3[2]
AB10
Vcc1_5_A[10]
AB9
Vcc1_5_A[11]
AC10
Vcc1_5_A[12]
AD10
Vcc1_5_A[13]
AE10
Vcc1_5_A[14]
AF10
Vcc1_5_A[15]
AF9
Vcc1_5_A[16]
AG9
Vcc1_5_A[17]
AH9
Vcc1_5_A[18]
E3
VccSus3_3[19]
C1
VccUSBPLL
AA2
VccSus1_05/VccLAN1_05[1]
Y7
VccSus1_05/VccLAN1_05[2]
V5
VccSus3_3/VccLAN3_3[1]
V1
VccSus3_3/VccLAN3_3[2]
W2
VccSus3_3/VccLAN3_3[3]
W7
VccSus3_3/VccLAN3_3[4]
Vcc1_05[1]
Vcc1_05[2]
Vcc1_05[3]
Vcc1_05[4]
Vcc1_05[5]
Vcc1_05[6]
Vcc1_05[7]
Vcc1_05[8]
Vcc1_05[9]
Vcc1_05[10]
Vcc1_05[11]
Vcc1_05[12]
Vcc1_05[13]
Vcc1_05[14]
Vcc1_05[15]
Vcc1_05[16]
Vcc1_05[17]
Vcc1_05[18]
Vcc1_05[19]
Vcc1_05[20]
Vcc3_3 / VccHDA
VccSus3_3/VccSusHDA
V_CPU_IO[1]
V_CPU_IO[2]
V_CPU_IO[3]
Vcc3_3[3]
Vcc3_3[4]
Vcc3_3[5]
Vcc3_3[6]
Vcc3_3[7]
Vcc3_3[8]
Vcc3_3[9]
Vcc3_3[10]
Vcc3_3[11]
Vcc3_3[12]
Vcc3_3[13]
Vcc3_3[14]
Vcc3_3[15]
Vcc3_3[16]
Vcc3_3[17]
Vcc3_3[18]
Vcc3_3[19]
Vcc3_3[20]
Vcc3_3[21]
VccRTC
VccSus3_3[1]
VccSus3_3[2]
VccSus3_3[3]
VccSus3_3[4]
VccSus3_3[5]
VccSus3_3[6]
VccSus3_3[7]
VccSus3_3[8]
VccSus3_3[9]
VccSus3_3[10]
VccSus3_3[11]
VccSus3_3[12]
VccSus3_3[13]
VccSus3_3[14]
VccSus3_3[15]
VccSus3_3[16]
VccSus3_3[17]
VccSus3_3[18]
Vcc1_5_A[19]
Vcc1_5_A[20]
Vcc1_5_A[21]
Vcc1_5_A[22]
Vcc1_5_A[23]
Vcc1_5_A[24]
Vcc1_5_A[25]
VccSus1_05[1]
VccSus1_05[2]
VccSus1_05[3]
Vcc1_5_A[26]
Vcc1_5_A[27]
Vcc1_5_A[28]
Vcc1_5_A[29]
Vcc1_5_A[30]
ICH7M B0_BGA 6 52~D
L11
L12
L14
L16
L17
L18
M11
M18
P11
P18
T11
T18
U11
U18
V11
V12
V14
V16
V17
V18
U6
R7
AE23
AE26
AH26
AA7
AB12
AB20
AC16
AD13
AD18
AG12
AG15
AG19
A5
B13
B16
B7
C10
D15
F9
G11
G12
G16
W5
P7
A24
C24
D19
D22
G19
K3
K4
K5
K6
L1
L2
L3
L6
L7
M6
M7
N7
AB17
AC17
T7
F17
G17
AB8
AC8
K7
C28
G20
A1
H6
H7
J6
J7
+1.05V_VCCP
+3.3V_SUS
+3.3V_RUN
1
2
C470
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
+1.5V_RUN
1
C477
0.1U_0402_16V4Z~D
2
0.1U_0402_16V4Z~D
1U_0603_10V4Z~D
C481
1
2
+1.05V_VCCP
4.7U_0603_6.3V6M~D
C517
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
1
1
C278
2
2
+3.3V_SUS
1
2
+3.3V_SUS
C485
1
2
+1.5V_RUN
+1.5V_RUN
+1.5V_RUN
1
C497
1
+
2
2
C493
0.1U_0402_16V4Z~D
1
1
2
2
+3.3V_RUN
0.1U_0402_16V4Z~D
1
C476
C475
2
0.1U_0402_16V4Z~D
1
C279
0.1U_0402_16V4Z~D
2
1
C488
0.1U_0402_16V4Z~D
2
+1.5V_RUN
1
C510
0.1U_0402_16V4Z~D
2
330U_D2E_2.5VM~D
C507
CRB is 270uF
+3.3V_RUN
C487
0.1U_0402_16V4Z~D
C486
1
2
C500
1
C496
0.1U_0402_16V4Z~D
2
+RTC_CELL
1
1
C505
0.1U_0402_16V4Z~D
2
2
U19E
A4
VSS[0]
A23
VSS[1]
B1
VSS[2]
B8
VSS[3]
B11
VSS[4]
B14
VSS[5]
B17
VSS[6]
B20
VSS[7]
B26
VSS[8]
B28
VSS[9]
C2
VSS[10]
C6
VSS[11]
C27
VSS[12]
D10
VSS[13]
D13
VSS[14]
D18
VSS[15]
D21
VSS[16]
D24
VSS[17]
E1
VSS[18]
E2
VSS[19]
E4
VSS[21]
E8
VSS[22]
E15
VSS[23]
F3
VSS[24]
F4
VSS[25]
F5
VSS[26]
F12
VSS[27]
F27
VSS[28]
F28
VSS[29]
G1
VSS[30]
G2
VSS[31]
G5
VSS[32]
G6
VSS[33]
G9
VSS[34]
G14
VSS[35]
G18
VSS[36]
G21
VSS[37]
G24
VSS[38]
G25
VSS[39]
G26
VSS[40]
H3
VSS[41]
H4
VSS[42]
H5
VSS[43]
H24
VSS[44]
H27
VSS[45]
H28
VSS[46]
J1
VSS[47]
J2
VSS[48]
J5
VSS[49]
J24
VSS[50]
J25
VSS[51]
J26
VSS[52]
K24
VSS[53]
K27
VSS[54]
K28
VSS[55]
L13
VSS[56]
L15
VSS[57]
L24
VSS[58]
L25
VSS[59]
L26
VSS[60]
M3
VSS[61]
M4
VSS[62]
M5
VSS[63]
M12
VSS[64]
M13
VSS[65]
M14
VSS[66]
M15
VSS[67]
M16
VSS[68]
M17
VSS[69]
M24
VSS[70]
M27
VSS[71]
M28
VSS[72]
N1
VSS[73]
N2
VSS[74]
N5
VSS[75]
N6
VSS[76]
N11
VSS[77]
N12
VSS[78]
N13
VSS[79]
N14
VSS[80]
N15
VSS[81]
N16
VSS[82]
N17
VSS[83]
N18
VSS[84]
N24
VSS[85]
N25
VSS[86]
N26
VSS[87]
P3
VSS[88]
P4
VSS[89]
P12
VSS[90]
P13
VSS[91]
P14
VSS[92]
P15
VSS[93]
P16
VSS[94]
P17
VSS[95]
P24
VSS[96]
P27
VSS[97]
ICH7M B0_BGA 6 52~D
VSS[98]
VSS[99]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
VSS[159]
VSS[160]
VSS[161]
VSS[162]
VSS[163]
VSS[164]
VSS[165]
VSS[166]
VSS[167]
VSS[168]
VSS[169]
VSS[170]
VSS[171]
VSS[172]
VSS[173]
VSS[174]
VSS[175]
VSS[176]
VSS[177]
VSS[178]
VSS[179]
VSS[180]
VSS[181]
VSS[182]
VSS[183]
VSS[184]
VSS[185]
VSS[186]
VSS[187]
VSS[188]
VSS[189]
VSS[190]
VSS[191]
VSS[192]
VSS[193]
VSS[194]
P28
R1
R11
R12
R13
R14
R15
R16
R17
R18
T6
T12
T13
T14
T15
T16
T17
U4
U12
U13
U14
U15
U16
U17
U24
U25
U26
V2
V13
V15
V24
V27
V28
W6
W24
W25
W26
Y3
Y24
Y27
Y28
AA1
AA24
AA25
AA26
AB4
AB6
AB11
AB14
AB16
AB19
AB21
AB24
AB27
AB28
AC2
AC5
AC9
AC11
AD1
AD3
AD4
AD7
AD8
AD11
AD15
AD19
AD23
AE2
AE4
AE8
AE11
AE13
AE18
AE21
AE24
AE25
AF2
AF4
AF8
AF11
AF27
AF28
AG1
AG3
AG7
AG11
AG14
AG17
AG20
AG25
AH1
AH3
AH7
AH12
AH23
AH27
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
ICH7-M(4/4)
LA-2881P
24 62Tuesday, December 13, 2005
1
2.0
of
Page 25
A
B
C
D
E
F
G
H
SATA Connector
CD-ROM Connector
JSATA
S1
1 1
IDE_RST_MOD<23>
+5V_MOD
IDE_DIOW#<22>
R711
510_0402_5%~D
2 2
IDE_DIORDY<22>
IDE_IRQ<22>
IDE_DA1<22>
IDE_DA0<22>
1 2
IDE_DCS1#<22>
+5V_MOD
IDE_RST_MOD
IDE_DD7
IDE_DD6
IDE_DD5
IDE_DD4
IDE_DD3
IDE_DD2
IDE_DD1
IDE_DD0
IDE_DIOW#
IDE_DIORDY
IDE_IRQ
IDE_DA1
IDE_DA0
IDE_DCS1#
IDE_LED#
PRI_CSEL
R710
470_0402_5%~D
1 2
JODD
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
SUYIN_80095AR-050G1T~D
2
1
2
4
3
4
6
5
6
8
7
8
10
9
10
12
11
12
14
13
14
16
15
16
18
17
18
20
19
20
22
21
22
24
23
24
26
25
26
28
27
28
30
29
30
32
31
32
34
33
34
36
35
36
38
37
38
40
39
40
42
41
42
44
43
44
46
45
46
48
47
48
50
49
50
IDE_DD8
IDE_DD9
IDE_DD10
IDE_DD11
IDE_DD12
IDE_DD13
IDE_DD14
IDE_DD15
IDE_DDREQ
IDE_DIOR#
RPDDACK#
PDIAG#
IDE_DA2
IDE_DCS3#
C36
1 2
0.1U_0402_16V4Z~D
IDE_DDREQ <22>
IDE_DIOR# <22>
IDE_DDACK#
1 2
R33 22_0402_5%~D
R34 100K_0402_5%~D
1 2
IDE_DA2 <22>
IDE_DCS3# <22>
+5V_MOD
Layout Note: W=80 mils
SATA_RX0-<22>
SATA_RX0+<22>
close SATA connector
IDE_DDACK# <22>
+5V_MOD
C451
3900P_0402_50V7K~D
3900P_0402_50V7K~D
12
12
C450
SATA_TX0+<22>
SATA_TX0-<22>
SATA_RX0-_N0
SATA_RX0+_P0
SATA_TX0+
SATA_TX0-
+3.3V_RUN
+5V_HDD
GND
S2
RX+
S3
RX-
S4
GND
S5
TX-
S6
TX+
S7
GND
P1
3.3V
P2
3.3V
P3
3.3V
P4
GND
P5
GND
P6
GND
P7
5V
P8
5V
P9
5V
P10
GND
P11
Reserved
P12
GND
P13
12V
P14
12V
P15
12V
TYCO_1770615-2_RV~D
GND1
GND2
1
2
Main SATA +5V Default
C460
+5V_HDD
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
C458
1
2
1U_0603_10V4Z~D
C463
1
2
C457
1
1
2
2
10U_0805_10V4Z~D
1000P_0402_50V7K~D@
C466
1
2
Pleace near HD CONN
+15V_SUS
12
R527
100K_0402_5%~D
HDD_EN
13
47K
2
47K
Q87
PDTC144EK_SOT23~D
C453
0.01U_0402_25V7K~D
1
2
Layout Note: Place close to CD-ROM CONN
+5V_MOD
1U_0603_10V4Z~D
0.1U_0402_16V4Z~D
1000P_0402_50V7K~D
C35
C41
1
1
2
2
3 3
10U_0805_10V4Z~D
C42
C49
1
1
2
2
IDE_DD0
IDE_DD1
IDE_DD2
IDE_DD3
IDE_DD4
IDE_DD5
IDE_DD6
IDE_DD7
IDE_DD8
IDE_DD9
IDE_DD10
IDE_DD11
IDE_DD12
IDE_DD13
IDE_DD14
IDE_DD15
IDE_DD[0..15] <22>
C459
1000P_0402_50V7K~D
1
2
+5V_HDD Source
+5V_MOD Source
@
C652
+5V_SUS
@
6
2
1
Q18
D
SI3456BDV-T1_TSOP6~D
G
3
S
0.01U_0402_25V7K~D
1
2
+5V_MOD +5V_RUN
4 5
4.7U_1206_16V6K~D
C45
100K_0402_5%~D
12
R37
1
2
PJP20
1 2
PAD-OPEN 4x4m
Shorted
HDDC_EN#<23>
HDDC_EN#
+15V_SUS
12
R706
100K_0402_5%~D
@
MOD_EN
13
Q100
@
MODC_EN#
MODC_EN#<23>
4 4
2
DTC144EKA_SOT23~D
3
C454
1
2
+5V_SUS
2
1
G
4.7U_1206_16V6K~D
C456
4 5
+3.3V_RUN
0.1U_0402_16V4Z~D@
0.1U_0402_16V4Z~D@
C462
1
2
6
D
Q88
SI3456BDV-T1_TSOP6~D
S
+5V_HDD
100K_0402_5%~D
12
R528
1
2
1U_0603_10V4Z~D@
C461
1
2
PJP19
1 2
PAD-OPEN 4x4m
10U_0805_10V4Z~D@
C455
1
2
+5V_RUN
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
A
B
C
D
E
F
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
SATA HDD and CD-ROM CONN.
LA-2881P
G
25 62Tuesday, December 13, 2005
H
2.0
of
Page 26
5
4
3
2
1
U32
1
0.1U_0402_16V4Z~D
0.01U_0402_16V7K~D
1U_0603_10V4Z~D
10U_0805_6.3V6M~D
C358
1
2
U31
8
RESET#
7
SYNC
2
SDATA_OUT
3
BIT_CLK
5
SDATA_IN
19
VREF_OUT
18
VREF_IN
20
CAP2
21
GPIO0
22
GPIO1
30
GPIO2
31
SPDIF _ IN/EAPD /GPIO3
32
SPDIF _OUT
1
NC1
11
NC2
AUDIO_AVDD_ON
+3.3V_RUN
C365
C366
D D
1
2
C364
1
2
AUDIO_AVDD_ON<37>
2
1
W=30 mil
0.1U_0402_10V7K~D
1U_0603_10V6K~D
C C
ICH_AZ_CODEC_RST#<22>
ICH_AZ_CODEC_SYNC<22>
ICH_AZ_CODEC_SDOUT<22>
HP_NB_SENSE<27,28,37>
C380
ICH_AZ_CODEC_BITCLK<22>
1 2
R454 33_0402_5%~D
R476 0_0402_5%~D@
SPDIF_SHDN<20,37>
DOCK_HP_MUTE#<37>
SPDIF<20>
DOCK_HP_MUTE#
VREFOUT<27>
ICH_AZ_CODEC_SDIN0<22>
Close to U31.3
ICH_AZ_CODEC_BITCLK
12
R456
10_0402_5%~D@
1
C360
10P_0402_50V8J~D@
B B
2
Close to U31.5
ICH_AZ_CODEC_SDOUT
12
R455
47_0402_5%~D@
1
C359
22P_0402_50V8J~D@
2
ICH_AZ_CODEC_SDIN0
Close to U31.18
AC97VREFI
1
C381
1U_0603_10V6K~D
2
Close to U31.20
CAP2
A A
5
1U_0603_10V6K~D
0.1U_0402_10V7K~D
C382
1
1
2
2
ICH_AZ_CODEC_RST#
ICH_AZ_CODEC_SYNC
ICH_AZ_CODEC_SDOUT
ICH_AZ_CODEC_BITCLK
12
EAPD<27,28>
SPDIF
+3.3V_RUN
4
C362
1
1
2
2
ICH_AZ_SDIN0_R
VREFOUT
AC97VREFI
CAP2
SPDIF_SHDN
DOCK_HP_MUTE#
EAPD
R460
12
0_0402_5%~D
12
R701
100K_0402_5%~D
C363
IN
2
GND
3
BYPASS
EN
TPS793475DBVR_SOT23-5~D
+VDDA
C374
6
26
AVDD
DVDD
STAC9200
AVSS117AVSS2
4
DVSS
STAC9200X5NAEB1XR_QFN32~D
29
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
OUT
0.1U_0402_10V7K~D
1
2
LINE_IN_L
LINE_IN_R
LOUT_L
LOUT_R
MONO_OUT
SENSE_A
3
VDDA=4.75V
5
TPS793475_BYPASS
4
10U_0805_6.3V6M~D
C379
1
2
15
16
10
CD_L
12
CD_R
13
MIC1
14
MIC2
27
HP_L
28
HP_R
23
24
25
9
Removed internal MICs
+VDDA+5V_SUS +5V_RUN
0.1U_0402_16V4Z~D
2.2U_0805_10V6K~D
C377
C378
1
1
0.1U_0402_16V4Z~D
C372
1
2
HP_OUT_L
HP_OUT_R
AUD_MONO_OUT
SENSE_A
HP_NB_SENSE
2
2N7002_SOT23~D
2
2
G
Q79
L35
1 2
0.047U_0402_16V4Z~D
BLM31A260SPT_1206~D@
C376
1
2
NB_MICIN_L <27>
NB_MICIN_R <27>
HP_OUT_L <27>
HP_OUT_R <27>
AUD_LINE_OUT_L <27>
AUD_LINE_OUT_R <27>
AUD_MONO_OUT <28>
39.2K_0402_1%~D
20K_0402_1%~D
12
12
R457
R458
13
13
D
D
S
S
2N7002_SOT23~D
Trace width is 5mil for all analog signals.
+VDDA
R461
5.1K_0402_1%~D
12
Place R461, R457, R458 close to U31 Pin9
MIC_SWITCH
2
G
Q80
MIC_SWITCH <27>
DELL CONFIDENTIAL/PROPRIETARY
Title
Size Document Number Rev
2
Date: Sheet
Compal Electronics, Inc.
Azalia CODEC
LA-2881P
26 62Tuesday, December 13, 2005
1
2.0
of
Page 27
5
4
3
2
1
+3.3V_RUN
12
R467
10K_0402_5%~D
D D
C383
1U_0603_10V6K~D
1 2
SPKR<23>
BEEP<37>
AUD_LINE_OUT_R<26>
AUD_LINE_OUT_L<26>
NB_MUTE<28,37>
1 2
C384
1U_0603_10V6K~D
1
2
HP_OUT_R<26>
HP_OUT_L<26>
C C
B B
A A
HP_NB_SENSE
AUD_LINE_IN_R
AUD_LINE_IN_L
1
1
C386
C385
2
2
47P_0402_50V8J~D
47P_0402_50V8J~D
+VDDA
L34
BLM18AG121SN1D_0603~D
1 2
+Z2401
1
2
5
U33
P
A
4
Y
B
G
3
74AHCT1G86GW SOT353-5~D
C369
0.012U_0402_16V7K~D
1 2
1 2
0.012U_0402_16V7K~D
C343
+3.3V_RUN
100K_0402_5%~D
R459
1 2
13
D
2
G
Q82
S
2N7002_SOT23~D
5
1
C395
2
1U_0603_10V6K~D
1U_0603_10V6K~D
C375
0.1U_0402_16V4Z~D
10K_0402_5%~D
1 2
47P_0402_50V8J~D@
C368
C348
1
2
14
18
15
13
R463
1
2
1
3
@
47P_0402_50V8J~D
U34
C396
SHDNR#
SHDNL#
INR
INL
C1P
C1N
C346
+3.3V_RUN_4411
19
PVDD
PVss
5
7
1
2
2.2K_0402_5%~D
PC_BEEP
0.047U_0402_10V7K~D
C344
2
1
1
2
EAPD<26,28>
1
2
10
SVDD
PGND
SVss
2
R462
47P_0402_50V8J~D@
C351
L36
1 2
BLM18AG601SN1D_0603~D
C390
1U_0603_10V6K~D
11
OUTR
9
OUTL
4
NC-4
6
NC-6
8
NC-8
12
NC-12
16
NC-16
20
NC-20
SGND
MAX4411ETP+_TQFN20~D
17
HP_SPK_R1
HP_SPK_L1
+3.3V_RUN
L40
BLM18AG121SN1D_0603~D
12
12
L39
BLM18AG121SN1D_0603~D
Trace width is 5mil for HP_SPK_R1/R2
HP_SPK_L1/L2
C373
0.1U_0402_16V4Z~D
1 2
12
0.047U_0402_10V7K~D
C341
2
1
13
D
2
G
S
RINLIN-
47P_0402_50V8J~D@
1
2
Q104
2N7002_SOT23~D
@
4
PC_BEEPZ2402 Z2404
1
C349
1U_0603_10V4Z~D
2
7
17
9
5
19
W=40mils
U30
RIN+
RIN-
LIN+
LIN-
SHUTDOWN
16
15
VDD
PVDD1
GND41GND311GND213GND1
20
HP_SPK_R2
HP_SPK_L2
2
2
C394
C393
1
1
100P_0402_50V8J~D
100P_0402_50V8J~D
L33
BLM21PG600SN1D_0805~D
1 2
+5VAMPVCC
6
PVDD2
2
GAIN0
3
GAIN1
18
ROUT+
14
ROUT-
4
LOUT+
8
LOUT-
12
NC
10
BYPASS
TPA6017A2PWP_TSSOP20~D
VREFOUT<26>
4.7K_0402_5%~D
4.7K_0402_5%~D
12
12
R466
R468
R464
NB_MICIN_L<26>
NB_MICIN_R<26>
+5V_SUS
3
1
C367
0.1U_0402_16V4Z~D
2
1
C371
10U_0805_10V4Z~D
2
AUD_GAIN0
AUD_GAIN1
INT_SPK_R1
INT_SPK_R2
INT_SPK_L1
INT_SPK_L2
BYPASS
1
C350
0.47U_0603_16V7K~D
2
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
1 2
4.99_0402_1%~D
R465
1 2
4.99_0402_1%~D
C388
2.2U_0805_10V6K~D
C389
2.2U_0805_10V6K~D
1
C370
0.1U_0402_16V4Z~D
2
AUD_GAIN0
AUD_GAIN1
MIC_SWITCH<26>
12
12
R470
+5VAMPVCC
12
20K_0402_1%~D
12
R469
INT_SPK_R1
INT_SPK_R2
INT_SPK_L1
INT_SPK_L2
12
R448
10K_0402_5%~D
12
R452
10K_0402_5%~D@
BLM18AG121SN1D_0603~D
BLM18AG121SN1D_0603~D
20K_0402_1%~D
+3.3V_RUN
C387
1
1000P_0402_50V7K~D
2
L38
L37
12
R471
100K_0402_5%~D
1
2
3
4
Gain Setting
2
HP_NB_SENSE<26,28,37>
MICIN_L
12
MICIN_R
12
2
C391
C392
1
100P_0402_50V8J~D
JSPK
1
2
3
4
MOLEX_53398-0490~D
12
R449
10K_0402_5%~D
12
R453
10K_0402_5%~D@
HP_SPK_L2
HP_SPK_R2
100P_0402_50V8J~D
HP_NB_SENSE
2
1
A1
A2
A6
A3
A4
A5
B1
B2
B6
B3
B4
B5
Place close to connector
INT_SPK_L2
INT_SPK_L1
INT_SPK_R2
INT_SPK_R1
C98
GAIN0
0
0
1
*
0
1
0
11
@
1
2
AV(inv)GAIN1
6dB
10dB
15.6dB
21.6dB
@
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
1
C96
C93
2
DELL CONFIDENTIAL/PROPRIETARY
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
Amplifier and Phone Jack
LA-2881P
1
JAUDO
123
FOX_JA8333L-B2P4-7F~D
@
@
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
1
1
C91
2
2
INPUT
IMPEDANCE
90K ohm
70K ohm
45K ohm
25K ohm
27 62Tuesday, December 13, 2005
of
2.0
Page 28
5
4
3
2
1
+3.3V_RUN
1
1
2
33P_0402_50V8J~D
1
2
1U_0805_25V6K~D
12
0.22U_0603_10V7K~D
C263
2
JBT
1
1
2
2
3
3
4
4
5
11
5
11
6
12
6
COEX3
100P_0402_50V8J~D@
C261
1
2
1 2
33_0402_5%~D
Place near Pin22
0.1U_0603_25V7K~D
1
C636
C618
2
U47
3
VDD
4
VDD
21
VDD
22
VDD
7
CHOLD
5
C1N
6
C1P
14
SHDN#
15
G1
16
G2
18
FS1
19
FS2
11
IN-
12
IN+
1
PGND
2
PGND
33
GND
MAX9713ETJ_TQFN-EP32~D
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
7
7
8
8
9
9
10
10
JST_BM10B-SRSS-TB~D
ICH_AZ_MDC_SDOUT<22>
ICH_AZ_MDC_SYNC<22>
R381
10U_1206_25V6M~D
0.1U_0603_25V7K~D
1
1
C76
2
2
3
12
+15V_SUS
1
C70
2
ICH_AZ_MDC_SDOUT
ICH_AZ_MDC_RST1#
Apply lead free P/N
10U_1206_25V6M~D
27
OUT-
28
OUT-
29
OUT+
30
OUT+
8
NC
17
NC
20
NC
25
NC
26
NC
31
NC
32
NC
13
SS
9
REG
10
AGND
23
PGND
24
PGND
ICH_AZ_MDC_RST#<22>
MDC_SDIN
0.01U_0402_16V7K~D
MDC_RST_DIS#<37>
1
3
5
7
9
11
L58
1 2
BLM21PG600SN1D_0805~D
L57
1 2
BLM21PG600SN1D_0805~D
1
1
C69
C625
2
2
0.47U_0603_16V7K~D
JMDC
GND1
IAC_SDATA_OUT
GND2
IAC_SYNC
IAC_SDATA_IN
IAC_RESET#
TYCO_1-1734054-2~D
2
+5V_SUS
12
1 2
R370
10K_0402_5%~D
RES0
RES1
3.3V
GND3
GND4
IAC_BITCLK
1
C643
2
1
C642
2
R372
0_0402_5%~D@
Q61
BSS138_SOT23~D
D
1 3
2
S
G
ICH_AZ_MDC_RST1#
12
R373
100K_0402_5%~D
PWR / GND Minimum Spacing W=20 mil
2
4
6
8
10
ICH_AZ_MDC_BITCLK
12
SUB_OUT1
1000P_0402_50V7K~D
1000P_0402_50V7K~D
SUB_OUT2
SUB_OUT1
SUB_OUT2
DELL CONFIDENTIAL/PROPRIETARY
Title
SUBWOOFER,BT PORT and MDC
Size Document Number Rev
LA-2881P
Date: Sheet
D D
COEX2_WLAN_ACTIVE<34>
COEX1_BT_ACTIVE<34>
COEX2_WLAN_ACTIVE
COEX1_BT_ACTIVE
ECE_USBP4-<37>
ECE_USBP4+<37>
BT_ACTIVE<34,39>
BT_RADIO_DIS#<23>
ECE_USBP4ECE_USBP4+
Place near JBT.
1 2
1 2
JWIRE1
1
G1
22G2
Av dB(TYP)
22.1
19.1
16
12
R696
0_0402_5%~D
0_0402_5%~D
12
R691
@
0_0402_5%~D
0_0402_5%~D
5
L47
L46
1
1
C449
3
4
C464
2
2
1000P_1808_3KV7K~D
1000P_1808_3KV7K~D
@
@
JPHON
1
1
2
2
3
GND1
4
GND2
JM34613-L002-TR~D
Oscillator frequency selection
Freq Hz
FS2
FS1
L
L 335
13
D
Q84
2N7002_SOT23~D
S
460
236L
335 +/- 7%
13
D
2
G
S
C620
1 2
0.033U_0603_16V7K~D
EAPD<26,27>
Q83
2N7002_SOT23~D
L H
H
H
H
*
13
D
2
G
S
12
MAX9713_G1
MAX9713_G2
MAX9713_FS1
MAX9713_FS2
12
Q81
2N7002_SOT23~D
@
2
G
AUD_MONO_OUT<26>
(ss mode)
R685
1 2
0_0603_5%~D
4
+3.3V_RUN
2
G
R531
100K_0402_5%~D
13
D
Q105
2N7002_SOT23~D
S
@
0.22U_0603_10V7K~D@
C632
1
2
C73
RJ_TIP
RJ_RING
C C
RJ_RING
RJ_TIP
FBMA-L11-160808-301LMA20T_0603~D
FBMA-L11-160808-301LMA20T_0603~D
1
MOLEX_48227-0201~D
Voltage Gain selection
G1
G2
L
L
*
L
H
H
L13
H
H
B B
SUB_SHDN_ON_BATT<37>
NB_MUTE<27,37>
HP_NB_SENSE<26,27,37>
+5V_RUN
12
12
R699
R698
R697
@
0_0402_5%~D
A A
R694
0_0402_5%~D
@
0_0402_5%~D
12
12
R692
R693
@
0_0402_5%~D
0.1U_0402_16V4Z~D
BT_RADIO_DIS#
T1 PAD~D
12
C262
R298
10K_0402_5%~D
ICH_AZ_MDC_SDIN1<22>
Place near Pin3
C82
C619
0.1U_0603_25V7K~D
SUB_SHUTDOWN#
MAX9713_G1
MAX9713_G2
MAX9713_FS1
MAX9713_FS2
1000P_0402_50V7K~D
1
1
C77
2
2
ICH_AZ_MDC_SDOUT
ICH_AZ_MDC_BITCLK
R385
R540
1 2
10_0402_5%~D@
MDC_AC_BITCLK_TERM
10P_0402_50V8J~D@
C489
1
2
ICH_AZ_MDC_BITCLK <22>
JWOFR
1
1
2
2
MOLEX_53398-0290~D
@
2
C644
1
100P_0402_50V8J~D
@
2
C647
1
100P_0402_50V8J~D
Compal Electronics, Inc.
28 62Tuesday, December 13, 2005
1
10_0402_5%~D@
C300
+3.3V_SUS
C307
4.7U_0603_6.3V6M~D
of
ICH_AC_SDOUT_MDCTERM
1 2
10P_0402_50V8J~D@
1
2
1
1
C306
2
2
0.1U_0402_16V4Z~D
2.0
Page 29
5
4
3
2
1
Ext Back Right USB Port
+5V_SUS
C559
1
2
USBP3USBP3+
USBP1USBP1+
0.1U_0402_16V4Z~D
C554
+USB_R_PWR
OC1#
OUT1
OUT2
OC2#
+USB_R_PWR
8
7
6
5
USB_OC1#
USB_OC3#
USB_OC1# <23>
USB_OC3# <23>
U43
1
GND
2
IN
3
EN1#
4
10U_1206_16V4Z~D@
1
2
EN2#
TPS2062DR_SO8~D
150U_D2_6.3VM~D
1
C544
+
2
C235
C543
0.1U_0402_16V4Z~D
1
2
USBP3USBP3+
USBP1-
0.1U_0402_16V4Z~D
USBP1+
1
2
JUSB_R
A1
A_VCC
A2
A_D-
A3
A_D+
A4
A_GND
B1
B_VCC
B2
B_D-
B3
B_D+
B4
B_GND
9
G1
10
G2
11
G3
12
G4
FOX_UB11123-8Z4-HT~D
USB IO PORT#
1
2
3
4
5
6
DESTINATION
JUSB_R (Ext Back Right Bottom)
JUSB_S (Ext Side Bottom)
JUSB_R (Ext Back Right Top)
JUSB_L (Ext Back Left Top)
JUSB_S (Ext Side Top)
JUSB_L (Ext Back Left Bottom)
USBP3-<23>
USBP3+<23>
USBP1-<23>
D D
USB_BACK_EN#<37>
USBP1+<23>
USB_BACK_EN#
Ext Back Left USB Port
+5V_SUS
C218
1
2
+5V_SUS
C679
1
2
USBP4USBP4+
USBP6USBP6+
0.1U_0402_16V4Z~D
USBP2USBP2+
USBP5USBP5+
0.1U_0402_16V4Z~D
C217
C680
+USB_L_PWR
OC1#
OUT1
OUT2
OC2#
OC1#
OUT1
OUT2
OC2#
+USB_L_PWR
8
7
6
5
+USB_S_PWR
8
7
6
5
USB_OC4#
USB_OC6#
USB_OC5#
USB_OC2#
USB_OC4# <23>
USB_OC6# <23>
+USB_S_PWR
USB_OC5# <23>
USB_OC2# <23>
U12
1
GND
2
IN
3
EN1#
4
10U_1206_16V4Z~D@
1
2
10U_1206_16V4Z~D@
1
2
EN2#
TPS2062DR_SO8~D
U48
1
GND
2
IN
3
EN1#
4
EN2#
TPS2062DR_SO8~D
C210
150U_D2_6.3VM~D
1
+
2
0.1U_0402_16V4Z~D
C164
1
USBP2USBP2+
USBP5USBP5+
JUSB_L
A1
A_VCC
A2
A_D-
A3
A_D+
A4
A_GND
B1
B_VCC
B2
B_D-
B3
B_D+
B4
B_GND
9
G1
10
G2
11
G3
12
G4
FOX_UB11123-8Z4-HT~D
JUSB_S
8
8
7
7
6
6
5
5
10
9
4
4
3
3
2
2
1
1
JST_SM8B-SRSS~D
10
9
2
USBP4USBP4+
USBP6-
0.1U_0402_16V4Z~D
C211
150U_D2_6.3VM~D
1
C2
+
2
USBP6+
1
2
0.1U_0402_16V4Z~D
C693
1
2
0.1U_0402_16V4Z~D
C3
1
2
Place U189, U190, U191 as close as USB connector.
+USB_R_PWR
USBP3+
USBP1-
USBP4+
USBP6-
USBP2+
USBP5-
U14
1
D2+
D1+
2
VCC
GND
3
D1-
D2-
IP4220CZ6_SO6@
U11
1
D2+
D1+
2
VCC
GND
3
D1-
D2-
IP4220CZ6_SO6@
U1
1
D2+
D1+
2
VCC
GND
3
D1-
D2-
IP4220CZ6_SO6@
4
5
6
+USB_L_PWR
4
5
6
+USB_S_PWR
4
5
6
USBP1+
USBP3-
USBP6+
USBP4-
USBP5+
USBP2-
C C
USB_BACK_EN#<37>
B B
Ext Side USB Port
USB_SIDE_EN#<37>
A A
USBP4-<23>
USBP4+<23>
USBP6-<23>
USBP6+<23>
USB_BACK_EN#
USBP2-<23>
USBP2+<23>
USBP5-<23>
USBP5+<23>
USB_SIDE_EN#
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
USB 2.0 PORT
LA-2881P
29 62Tuesday, December 13, 2005
1
2.0
of
Page 30
5
4
3
2
1
SPROM_DOUT_TPM_GPIO0
SPROM_DIN_TPM_GPIO1
PCI_C_BE0_TPM_GPIO2_R#
PCI_SERR_ATTN_BTTN_R#
5@
R404
R495
P/N: SA00000o71L (5752KFB2); 5@
SA00000oD0L (4401E) ; 4@
D D
LAN_TPM_EN#<37>
+3.3V_LAN
R498
10K_0402_5%~D@
1 2
LAN_TPM_EN_EXT_POR#
LAN_TPM_EN# LAN_TPM_EN_EXT_POR#
For Rikers:
No POP R612 and POP R498
C C
for disabling TPM
POP option for 5752 NVRAM
CLK_PCI_LAN_LPC<6>
LAN_LOW_PWR<37>
1 2
R612 0_0402_5%~D
R618
12
4.7K_0402_5%~D @
PCI_C_BE3_GPIO3_R#<31>
LOM_CABLE_DETECT<37>
ICH_SMBDATA<6,23,34>
ICH_SMBCLK<6,23,34>
+3.3V_LAN
5@
R407
@
R408
1 2
4.7K_0402_5%~D
LPC_LFRAME#<22,37,38>
IRQ_SERIRQ<23,33,37,38>
1 2
(Default EEPROM is ST )
LINK_10#<32>
+PCIE_PLLVDD
+GPHY_PLLVDD
+1.2V_1.8V_LAN
LINK_100#<32>
LINK_1000#<32>
LAN_ACT#<32>
PCI_C_BE3_GPIO3_R#
LAN_GPIO2
LAN_GPIO0
LAN_GPIO1
R399
R403
R400
R516
1 2
@
B B
+2.5V_LAN
A A
+2.5V_3.3V_LAN
10K_0402_5%~D
R362
@
5@
12
+2.5V_3.3V_LAN
1 2
10K_0402_5%~D
0_0603_5%~D
1 2
@
+3.3V_LAN
4@
12
R361
1 2
10K_0402_5%~D
10K_0402_5%~D
@
3.3V for 4401E
2.5V for 5752
L28
0_0603_5%~D
BLM18AG601SN1D_0603~D
BLM18AG601SN1D_0603~D
BLM18AG601SN1D_0603~D
12
C430
0.1U_0402_16V4Z~D
L22
5@
12
C445
0.1U_0402_16V4Z~D
L21
BIASVDD
12
C444
0.1U_0402_16V4Z~D
5
+XTALVDD
1
2
1
5@
2
1
2
+AVDD
CLK_PCI_LAN_LPC
LPC_LAD0
LPC_LAD0<22,37,38>
LPC_LAD1
LPC_LAD1<22,37,38>
LPC_LAD2
LPC_LAD2<22,37,38>
LPC_LAD3
LPC_LAD3<22,37,38>
LPC_LFRAME#
PLTRST1#
PLTRST1#<10,21,23>
IRQ_SERIRQ
R363
SPROM_DOUT_TPM_GPIO0
PCI_C_BE0_TPM_GPIO2_R#
SPROM_DIN_TPM_GPIO1
LAN_GPIO0
LAN_GPIO1
LAN_GPIO2
PCI_C_BE3_GPIO3_R#
R522
ICH_SMBDATA
ICH_SMBCLK
LAN_SCLK
LAN_SI
LAN_SO
LAN_CS#
4.7K_0402_5%~D
PCI_AD11_NVS1_R
PCI_AD12_NVS0_R
BIASVDD
LINK_10#
LINK_100#
LINK_1000#
LAN_ACT#
XTALI
XTALO
+AVDD
+AVDDL
1.8V for 4401E
1.2V for 5752
L26
BLM18AG601SN1D_0603~D
BLM18AG601SN1D_0603~D
BLM18AG601SN1D_0603~D
12
C302
4.7U_0805_10V4Z~D
L27
12
C303
4.7U_0805_10V4Z~D
L30
5@
12
C315
4.7U_0805_10V4Z~D
5@
1
2
1
2
1
2
0_0402_5%~D4@
0_0402_5%~D@
1
C432
2
0.1U_0402_16V4Z~D
+GPHY_PLLVDD
1
C431
2
0.1U_0402_16V4Z~D
1
C419
0.1U_0402_16V4Z~D
2
5@
U23A
K10
DC/LCLK
M11
DC/LAD0
L11
DC/LAD1
K9
DC/LAD2
L5
DC/LAD3
H11
DC/LFRAME#
M9
DC/LRESET#
L8
DC/SERIRQ
L9
EXT_POR/TPM_EN#
J11
SPROM_DOUT/TPM_GPIO0
M4
CBE0#/TPM_GPIO2
N13
SPROM_DIN/TPM_GPIO1
G12
GPIO0
H13
GPIO1
G13
DC/GPIO2
C4
CBE3#/GPIO3
D9
DC/SMB_DATA
D10
DC/SMB_CLK
E11
EECLK_PXE/SCLK
E12
EEDATA_PXE/SI
F11
DC/SO
C12
DC/CS#
M1
AD11/NV_STRAP1
M2
AD12/NV_STRAP0
A14
BIASVDD
A11
LINK_LED10#/LINKLED#
B11
LINK_LED100#/SPD100LED#
A12
COL_LED#/SPD1000LED#
B10
ACT_LED#/TRAFFICLED#
P12
XTALI
N12
XTALO
A13
DC/AVDD_0
F14
DC/AVDD_1
F12
EPHY_AVDD/AVDDL_0
F13
EPHY_AVDD/AVDDL_1
M8
DC/PCIE_PLLVDD
G14
PLLVDD/GPHY_PLLVDD
BCM5752KFB2G_A2_FPBGA196~D
+AVDDL
+PCIE_PLLVDD
4
BCM4401E/BCM5752
LPC/TPM
Media
TEST_MODE/LOW_PWR
SERR#/ATTN_BTTN#
CBE1#/VMAINPRSNT
Power
Control
GPIO
REGSUP18/REGSUP12
REG18OUT/REGSEN12
SMBUS
Control
Regulator
SPI
PCI-E
BIAS
LED
Clock
TEST
Analog
Power
PLL
Bias
Layout Notice : No high
speed signal should be
routed near RDAC or on
adjacent layer to RDAC
470 ohm(P/N: SD02847008L) for 5752
750 ohm(P/N: SD02875008L) for 4401E
R410
12
470_0402_5%~D
X1
1 2
25MHZ_18PF_1BX25000CK1D~D
2
C313
1
22P_0402_50V8J~D
TRD0+
TRD0-
TRD1+
TRD1-
DC/TRD2+
DC/TRD2-
DC/TRD3+
DC/TRD3-
VAUXPRSNT
DC/REGCTL12
VREF/REGCTL25
DC/REGSEN25
NC/PCIE_TXDP
NC/PCIE_TXDN
RSVD/PCIE_RXDP
RSVD/PCIE_RXDN
PME#/WAKE#
RSVD/REFCLK+
RSVD/REFCLK-
DC/REFCLK_SEL
PCI_RST#/PERST#
TDO
TMS
TRST#
AD16/SERIAL_DI
AD14/SERIAL_DO
DC/GPHY_TVCOI
RDAC
XTALO
XTALI
2
C314
1
22P_0402_50V8J~D
B13
B14
C13
C14
D13
D14
E13
E14
L6
A2
L3
J12
K14
J13
J14
K13
M14
N6
P6
P10
N10
A6
N8
P8
F4
C2
D7
TCK
H12
TDI
D6
C11
D12
K1
L1
D8
A10
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
R493
1 2
1 2
1 2
10K_0402_5%~D 5@
10K_0402_5%~D 5@
10K_0402_5%~D
LAN_TX0+
LAN_TX0LAN_TX1+
LAN_TX1LAN_TX2+
LAN_TX2LAN_TX3+
LAN_TX3-
R508
1 2
0_0402_5%~D5@
R506
1 2
0_0402_5%~D@
PCI_SERR_ATTN_BTTN_R#
PCI_C_BE1_VMAIN_R#
R494
12
1K_0402_5%~D
REGCTL_PNP12
REGCTL_PNP25
PCIE_RX3+_P3
PCIE_RX3-_N3
R523
4@
1 2
0_0402_5%~D
CLK_PCIE_LOM
CLK_PCIE_LOM#
4.7K_0402_5%~D
4@
5@
4@
0_0402_5%~D
R511
4.7K_0402_5%~D
R512
4.7K_0402_5%~D
1 2
0_0402_5%~D 5@
R510
@
12
R514
1 2
0_0402_5%~D
R513
1 2
0_0402_5%~D
R368
1 2
12
@
12
R524
1.15K (P/N: SD01411518L) for 5752
1.24K(P/N: SD01412418L) for 4401E
R515
1 2
1.24K_0603_1%~D
+3.3V_LAN
LAN_SI
5@
1
C426
2
0.1U_0402_16V4Z~D
3
POP R845,R846,R847 for 5752 only
LAN_TX0+ <32>
LAN_TX0- <32>
LAN_TX1+ <32>
LAN_TX1- <32>
LAN_TX2+ <32>
LAN_TX2- <32>
LAN_TX3+ <32>
LAN_TX3- <32>
LAN_LOW_PWR <37>
+3.3V_LAN
+3.3V_LAN
+1.2V_1.8V_LAN
+2.5V_3.3V_LAN
5@
C312
0.1U_0402_16V4Z~D
1 2
PCIE_RX3+ <23>
1 2
C311
PCIE_RX3- <23>
0.1U_0402_16V4Z~D
5@
PCIE_TX3+ <23>
PCIE_TX3- <23>
SYS_PME# <33,35,37>
PCIE_WAKE# <34,37>
CLK_PCIE_LOM <6>
CLK_PCIE_LOM# <6>
PCI_RST# <21,33,34,35>
PLTRST1# <10,21,23>
PCI_AD16_SDI_R
PCI_AD14_SD0_R
U50
8
Q
7
VSS
6
VCC
5
W#
M45PE20-VMN6TP_SO8~D5@
U24
8
SO
7
GND
6
VCC
5
WP#
AT45BCM021B-SU_SO8~D@
SPROM_DOUT_TPM_GPIO0 <31>
SPROM_DIN_TPM_GPIO1 <31>
PCI_C_BE0_TPM_GPIO2_R# <31>
PCI_SERR_ATTN_BTTN_R# <31>
+3.3V_LAN
R402
*
LAN_SO
1
D
LAN_SCLK
2
C
3
RESET#
RESET#
SCK
CS#
LAN_CS#
4
S#
1
SI
2
3
4
R517
+3.3V_LAN
5@
4.7K_0402_5%~D
1 2
5@
1 2
+3.3V_RUN
R396
4.7K_0402_5%~D
R507
1 2
1K_0402_5%~D 5@
@
4.7K_0402_5%~D
12
+3.3V_SRC
ENAB_3VLAN<40>
PCI_AD16_SDI_R <31>
Q55
SI3456DV-T1-E3_TSOP6~D
D
6
S
45
2
1
G
3
REGCTL_PNP12
REGCTL_PNP25
+2.5V_LAN
5752 NVRAM , See NVRAM table, Set ST_45PE20 as default
5752 NVRAM table
Atmel AT45BCM021B
ST M45PE20
4.7K_0402_5%~D5@
R509
(Default)
+3.3V_LAN
12
1 2
4.7K_0402_5%~D@
12
4.7K_0402_5%~D
R505
+3.3V_LAN
R757
NV_STRAP1 SO CS#
@
2
NV_STRAP0
0
0
1
PCI_AD14<21,33,35>
PCI_AD12<21,33,35>
PCI_AD11<21,33,35>
PCI_AD10<21,33,35>
PCI_STOP#<21,33,35>
PCI_PAR<21,33,35>
PCI_C_BE1#<21,33,35>
PCI_AD15<21,33,35>
+3.3V_LAN
12
12
2
R358
R341
C283
MMJT9435T1G_SOT223~D5@
1
1
4@
4@
2_1210_5%~D
0.1U_0402_16V4Z~D
1
2
PCI_PAR_R
PCI_AD15_RPCI_AD15
1
2_1210_5%~D
5@
5@
1
Q58
2 3
4
3
1
2
00
0
+3.3V_LAN
0.1U_0402_16V4Z~D5@
1 8
2 7
3 6
4 5
1 8
2 7
3 6
4 5
C282
41
Q59
5@
MBT35200MT1G_TSOP6~D
256
SCLK
1
0
RN5
0_1206_8P4R_5%~D
RN4
0_1206_8P4R_5%~D
0.1U_0402_16V4Z~D
10U_0805_10V4Z~D5@
1
C271
C268
2
SI
1
1
PCI_AD14 PCI _ AD14_SD0_R
PCI_AD12 PCI _ AD12_NVS0_R
PCI_AD11 PCI _ AD11_NVS1_R
PCI_AD10 PCI _ AD10_R
PCI_STOP# PCI_STOP_R#
PCI_PAR
PCI_C_BE1# PCI_C_BE1_VMAIN_R#
1
2
+3.3V_LAN
2
C287
1
4.7U_0805_10V4Z~D
+1.2V_1.8V_LAN
C286
10U_0805_10V4Z~D
0.1U_0402_16V4Z~D5@
C277
1
2
4.7U_0603_6.3V6M~D 5@
C281
1
2
PCI_AD10_R <31>
PCI_STOP_R# <31>
PCI_PAR_R <31>
PCI_AD15_R <31>
DELL CONFIDENTIAL/PROPRIETARY
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
BCM5752/4401E
LA-2881P
30 62Tuesday, December 13, 2005
1
of
2.0
Page 31
5
+1.2V_1.8V_LAN
1.8V for 4401E
1.2V for 5752
+1.2V_1.8V_LAN
D D
C C
B B
A A
PCI_AD20<21,33,35>
PCI_REQ3#<21>
PCI_AD24<21,33,35>
PCI_C_BE3#<21,33,35>
PCI_AD21<21,33,35>
PCI_AD18<21,33,35>
PCI_AD19<21,33,35>
PCI_AD17<21,33,35>
PCI_FRAME#<21,33,35,36>
PCI_C_BE2#<21,33,35>
PCI_IRDY#<21,33,35,36>
PCI_TRDY#<21,33,35>
PCI_PIRQB#<21>
PCI_DEVSEL#<21,33,35>
PCI_PERR#<21,33,35>
PCI_GNT3#<21>
L31
5@
+PCIE_SDS_VDD
BLM18AG601SN1D_0603~D
4.7U_0805_10V4Z~D
12
1
1
C316
5@
PCI_REQ3# PCI_REQ3_R#
PCI_C_BE3# PCI_C_BE3_GPIO3_R#
PCI_AD21 PC I _ AD 21_R
PCI_AD18
PCI_AD19
PCI_C_BE2# PCI_C_BE2_R#
PCI_IRDY# PCI_IRDY_R#
PCI_DEVSEL#
PCI_GNT3#
5
C420
0.1U_0402_16V4Z~D
2
2
+3.3V_LAN
PCI_STOP_R#<30>
PCI_AD10_R<30>
RN11
4@
1 8
2 7
3 6
4 5
0_1206_8P4R_5%~D
RN1
4@
1 8
2 7
3 6
4 5
0_1206_8P4R_5%~D
RN2
4@
1 8
2 7
3 6
4 5
0_1206_8P4R_5%~D
RN3
4@
1 8
2 7
3 6
4 5
0_1206_8P4R_5%~D
5@
+3.3V_LAN
+2.5V_LAN
+PCIE_SDS_VDD
PCI_PAR_R<30>
PCI_AD15_R<30>
PCI_AD20_RPCI_AD20
PCI_AD24_RPCI_AD24
PCI_AD18_R
PCI_AD19_R
PCI_AD17_RPCI_AD17
PCI_FRAME_R#PCI_FRAME#
PCI_TRDY_R#PCI_TRDY#
PCI_PIRQB_R#PCI_PIRQB#
PCI_DEVSEL_R#
PCI_PERR_R#PCI_PERR#
PCI_GNT3_R#
+XTALVDD
+3.3V_LAN
PCI_AD24_R
PCI_AD17_R
PCI_TRDY_R#
PCI_STOP_R#
PCI_DEVSEL_R#
CLKRUN_R#
PCI_PAR_R
PCI_GNT3_R#
PCI_AD15_R
PCI_AD13_R
PCI_AD5_R
PCI_AD0_R
PCI_AD10_R
PCI_AD9_R
PCI_AD7_R
PCI_AD4_R
PCI_AD1_R
PCI_AD8_R
PCI_AD6_R
PCI_AD3_R
PCI_AD2_R
E10
F10
J10
D11
G11
K12
L14
P13
H14
M12
N14
P14
PCI_C_BE3_GPIO3_R# <30>
4
P/N: SA00000o70L (5752KFB2), 5@
SA00000oD0L (4401E), 4@
U23B
BCM4401E/BCM5752
B8
VDDC_0
E5
VDDC_1
E6
VDDC_2
E7
VDDC_3
E8
VDDC_4
E9
VDDC_5
VDDC_6
F5
VDDC_7
VDDC_8
G4
VDDC_9
J4
VDDC_10
J5
VDDC_11
VDDC_12
K4
VDDC_13
K5
VDDC_14
K6
VDDC_15
K7
VDDC_16
K8
VDDC_17
VDDIO_0
VDDIO_1
VDDIO_2
REGSUP18/VDDIO_3
A8
DC/VDDP_0
D5
DC/VDDP_1
DC/VDDP_2
XTALVDD
M6
DC/PCIE_SDSVDD
A1
VESD3/DC_0
A7
VDDIOPCI/DC_1
B3
VDDIOPCI/DC_2
C5
VDDIOPCI/DC_3
D4
AD24/DC_4
E1
VDDIOPCI/DC_5
E3
AD17/DC_6
E4
VDDIOPCI/DC_7
G1
VDDIOPCI/DC_8
G2
VESD2/DC_9
G3
TRDY#/DC_10
H1
STOP#/DC_11
H3
DEVSEL#/DC_12
H4
CLKRUN#/DC_13
J1
PAR/DC_14
J3
GNT#/DC_15
K3
VDDIOPCI/DC_16
L2
AD15/DC_17
L4
VDDIOPCI/DC_18
M3
AD13/DC_19
M5
AD05/DC_20
M7
AD00/DC_21
DC_22
N2
AD10/DC_23
N3
AD09/DC_24
N4
AD07/DC_25
N5
AD04/DC_26
N7
AD01/DC_27
DC_28
P1
VESD1/DC_29
P2
VDDIOPCI/DC_30
P3
AD08/DC_31
P4
AD06/DC_32
P5
AD03/DC_33
P7
AD02/DC_34
DC_35
BCM5752KFB2G_A2_FPBGA196~D
Digial power
4
VSS_10
VSS_11
GND
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
PCI_CLK/NC_0
IDSEL/NC_1
AD25/NC_2
DC/NC_3
AD22/NC_4
AD23/NC_5
AD26/NC_6
AD27/NC_7
DC/NC_8
Don't Care connections
AD21/NC_9
REQ#/NC_10
AD28/NC_11
AD29/NC_12
AD30/NC_13
AD31/NC_14
DC/NC_15
AD18/NC_16
AD19/NC_17
AD20/NC_18
Disconnected
IRDY#/NC_19
FRAME#/NC_20
CBE2#/NC_21
INTA#/NC_22
PERR#/NC_23
SRPOM_CLK/NC_24
DC/NC_25
SPROM_CS/NC_26
DC/NC_27
DC/NC_28
DC/NC_29
DC/NC_30
DC/NC_31
DC/NC_32
VSS_0
VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
B4
B7
B12
E2
F6
F7
F8
F9
G5
G6
G7
G8
G9
G10
H5
H6
H7
H8
H9
H10
J6
J7
J8
J9
K2
N1
N9
P9
A3
A4
A5
A9
B1
B2
B5
B6
B9
C1
C3
C6
C7
C8
C9
C10
D1
D2
D3
F1
F2
F3
H2
J2
K11
L7
L10
L12
L13
M10
M13
N11
P11
PCI_AD25<21,33,35>
PCI_AD26<21,33,35>
PCI_AD27<21,33,35>
PCI_AD29<21,33,35>
PCI_AD28<21,33,35>
PCI_AD30<21,33,35>
PCI_AD31<21,33,35>
PCI_SERR#<21,33,35>
PCI_AD22<21,33,35>
PCI_AD23<21,33,35>
PCI_C_BE0#<21,33,35>
PCI_AD13<21,33,35>
PCI_AD8<21,33,35>
PCI_AD9<21,33,35>
3
Place as close as to U22B, Pin A1 , A7 , B3 , C5 , E1 , E4 , G1, G2, K3, L4, P1, P2
+3.3V_LAN
+3.3V_LAN
4.7U_0805_10V4Z~D
10U_0805_10V4Z~D
C290
C291
2
1
4@
4@
CLK_PCI_LAN
PCI_AD16_R
PCI_AD25_R
PCI_AD22_R
PCI_AD23_R
PCI_AD26_R
PCI_AD27_R
PCI_AD21_R
PCI_REQ3_R#
PCI_AD28_R
PCI_AD29_R
PCI_AD30_R
PCI_AD31_R
PCI_AD18_R
PCI_AD19_R
PCI_AD20_R
PCI_IRDY_R#
PCI_FRAME_R#
PCI_C_BE2_R#
PCI_PIRQB_R#
PCI_PERR_R#
SPROM_CLK_EECLK
SPROM_CS_EEDATA
R496
@
@
@
PCI_AD25 PCI _ AD25_R
PCI_AD27
PCI_AD30
12
0_0402_5%~D
R413
12
0_0402_5%~D
R412
12
0_0402_5%~D
RN10
1 8
2 7
3 6
4 5
0_1206_8P4R_5%~D
RN9
1 8
2 7
3 6
4 5
0_1206_8P4R_5%~D
PCI_SERR# PCI_SERR_ATTN_BTTN_R#
1 8
PCI_AD23 PC I _ AD 23_R
PCI_C_BE0# PCI_C_BE0_TPM_GPIO2_R#
2 7
3 6
4 5
1 8
2 7
3 6
4 5
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
0.1U_0402_16V4Z~D
C441
2
2
1
1
4@
CLK_PCI_LAN <6>
4@
PCI_AD26_RPCI_AD26
PCI_AD27_R
4@
PCI_AD29_RPCI_AD29
PCI_AD28_RPCI_AD28
PCI_AD30_R
PCI_AD31_RPCI_AD31
RN12
4@
PCI_AD22_RPCI_AD22
0_1206_8P4R_5%~D
RN8
4@
PCI_AD13_RPCI_AD13
PCI_AD8_RPCI_AD8
PCI_AD9_RPCI_AD9
0_1206_8P4R_5%~D
3
C438
4@
PCI_AD16<21,33,35>
2
1
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
C423
C435
2
1
4@
PCI_AD16
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
C439
C418
2
2
1
4@
2
1
1
4@
4@
(When CLKRUN# is support in system)
CLKRUN#<23,33,37,38>
R394
4@
4@
PCI_SERR_ATTN_BTTN_R# <30>
12
0_0402_5%~D
R369
12
100_0402_5%~D
PCI_C_BE0_TPM_GPIO2_R# <30>
2
For 4401E
SPROM_DOUT_TPM_GPIO0<30>
SPROM_DIN_TPM_GPIO1<30>
0.1U_0402_16V4Z~D
No POP R868
4@
R388
1 2
R393
0_0402_5%~D
1K_0402_5%~D
PCI_AD16_SDI_R <30>
2
CLKRUN# CLKRUN_R#
@
PCI_AD16_SDI_R
PCI_AD16_R
12
PCI_AD2<21,33,35>
PCI_AD1<21,33,35>
PCI_AD0<21,33,35>
PCI_AD5<21,33,35>
PCI_AD3<21,33,35>
PCI_AD4<21,33,35>
PCI_AD7<21,33,35>
PCI_AD6<21,33,35>
SPROM_CS_EEDATA
SPROM_CLK_EECLK
SPROM_DOUT_TPM_GPIO0
SPROM_DIN_TPM_GPIO1
+1.2V_1.8V_LAN
1
C427
0.1U_0402_16V4Z~D
2
1
C424
2
0.1U_0402_16V4Z~D
+2.5V_LAN
1
C415
2
0.1U_0402_16V4Z~D
+2.5V_LAN
C294
1
2
4.7U_0805_10V4Z~D
Reserve R894,R891,R895,R893,R892,R890,R887,R888,R889 as NO POP .
Isolate the PCIE signals from others when 5752 is populated.
See 5752 Pinout Diagram.
PCI_AD2
PCI_AD1
PCI_AD0
PCI_AD5
PCI_AD3 PCI_AD3_R
PCI_AD4 PCI_AD4_R
PCI_AD7 PCI_AD7_R
1 8
2 7
3 6
4 5
1 8
2 7
3 6
4 5
1
U25
1
CS
2
SK
3
DI
4
DO
AT93C46-10SU-2.7_SO8~D4@
VCC
ORG
GND
8
7
NC
6
10K_0402_5%~D@
5
R405
12
+3.3V_LAN
2
1
0.1U_0402_16V4Z~D4@
C308
Layout Notice : Place Caps as close as to chip
C429
1
1
C425
2
2
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
C428
1
1
C434
2
2
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
C436
1
1
2
0.1U_0402_16V4Z~D
C437
1
C433
2
2
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
Place as close as to chip
U22,Pin A8,D5,P13
1
5@
5@
C443
2
0.1U_0402_16V4Z~D
RN6
4@
PCI_AD2_R
PCI_AD1_R
PCI_AD0_R
PCI_AD5_R
0_1206_8P4R_5%~D
RN7
4@
PCI_AD6_RPCI_AD6
0_1206_8P4R_5%~D
R499
R491
@
0_0402_5%~D
0_0402_5%~D
0_0402_5%~D
R500
1 2
@
0_0402_5%~D
R492
1 2
0_0402_5%~D
R501
R502
1 2
1 2
1 2
@
@
@
0_0402_5%~D
@
1 2
DELL CONFIDENTIAL/PROPRIETARY
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
BCM5752/4401E
LA-2881P
31 62Tuesday, December 13, 2005
1
of
2.0
Page 32
5
Layout Notice : Place
terminatio n a s close as
chip as possible
LAN_TX0+
D D
C C
LAN_TX0-
LAN_TX1+
LAN_TX1-
LAN_TX2+
LAN_TX2-
LAN_TX3+
LAN_TX3-
R375
C299
5@
48.7_0603_1%
R382
1 2
0.1U_0402_10V7K~D5@
2
1
5@
48.7_0603_1%
R371
1 2
C298
5@
5@
48.7_0603_1%
R374
1 2
0.1U_0402_10V7K~D5@
2
1
48.7_0603_1%
48.7_0603_1%
R366
R364
1 2
1 2
0.1U_0402_10V7K~D
2
C293
1
R359, R360, R364, R366 pop 49.9_1%
ohm resistor for 4401E LOM
48.7_0603_1%
R359
1 2
C288
48.7_0603_1%
1 2
0.1U_0402_10V7K~D
2
1
R360
48.7_0603_1%
1 2
Apply lead free P/N
LAN_TX0- LAN_TX0-R
LAN_TX0-<30>
B B
LAN_TX0LAN_TX0+
LAN_TX1LAN_TX1+
A A
LAN_ACT# NB_LAN_ACTLED_YEL#
LINK_10#
LINK_100#
R521 0_0402_5%~D
12
4@
R520 0_0402_5%~D
12
4@
R519 0_0402_5%~D
12
4@
R518 0_0402_5%~D
12
4@
R386 0_0402_5%~D
12
4@
R380 0_0402_5%~D
12
4@
R320 0_0402_5%~D
12
4@
5
LAN_TX0+<30>
LAN_TX1-<30>
LAN_TX1+<30>
LAN_TX2-<30>
LAN_TX2+<30>
LAN_TX3-<30>
LAN_TX3+<30>
DOCKED<36,37>
SW_LANTX0SW_LANTX0+
SW_LANTX1SW_LANTX1+
LED_10_GRN#
LED_100_ORG#
1 2
36NH_0603CS-360EJTS_5%_0603~D
LAN_TX0+ LAN_TX0+R
1 2
36NH_0603CS-360EJTS_5%_0603~D
LAN_TX1- LAN_TX1-R
1 2
36NH_0603CS-360EJTS_5%_0603~D
LAN_TX1+ LAN_TX1+R
1 2
36NH_0603CS-360EJTS_5%_0603~D
LAN_TX2- LAN_TX2-R
1 2
36NH_0603CS-360EJTS_5%_0603~D
LAN_TX2+ LAN_TX2+R
1 2
36NH_0603CS-360EJTS_5%_0603~D
LAN_TX3- LAN_TX3-R
1 2
36NH_0603CS-360EJTS_5%_0603~D
LAN_TX3+
1 2
36NH_0603CS-360EJTS_5%_0603~D
DOCKED
LAN_ACT#<30>
LINK_10#<30>
LINK_100#<30>
4
LAN_ACT#<30>
10K_0402_5%~D
LINK_1000#
56
LINK_10#
+3.3V_LAN
12
R318
@
10K_0402_5%~D
1
D8
RB495D_SOT23~D
10K_0402_5%~D
LINK_100#
LAN ANALOG SWITCH
0B1
VDD04VDD110VDD218VDD327VDD438VDD550VDD6
1B1
2B1
3B1
4B1
5B1
6B1
7B1
0LED1
1LED1
2LED1
0B2
1B2
2B2
3B2
4B2
5B2
6B2
7B2
0LED2
1LED2
2LED2
55
LINK_10#<30>
LINK_1000#<30>
LINK_100#<30>
+3.3V_LAN
5@
U21
L16
5@
L17
5@
L18
5@
L19
5@
L20
5@
L23
5@
L24
5@
5@
LAN_ACT#
LINK_10#
LINK_100#
LAN_TX3+R
L25
2
A0
3
A1
7
A2
8
A3
11
A4
12
A5
14
A6
15
A7
17
SEL
19
LED0
20
LED1
54
LED2
5
NC
GND01GND16GND29GND313GND416GND521GND624GND728GND833GND939GND1044GND1149GND1253GND13
FROM NIC
1: TO DOCK
DOCKED
0: TO RJ45
4
3
+3.3V_LAN
R376
10K_0402_5%~D
LAN_ACT#
+3.3V_LAN
R316
+3.3V_LAN
R319
48
47
43
42
37
36
32
31
22
23
52
46
45
41
40
35
34
30
29
25
26
51
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
@
1 2
@
1 2
3
@
2
@
1 2
SW_LANTX0SW_LANTX0+
SW_LANTX1SW_LANTX1+
SW_LANTX2SW_LANTX2+
SW_LANTX3SW_LANTX3+
NB_LAN_ACTLED_YEL#
LED_10_GRN#
LED_100_ORG#
DOCK_LOM_TRD0DOCK_LOM_TRD0+
DOCK_LOM_TRD1DOCK_LOM_TRD1+
DOCK_LOM_TRD2DOCK_LOM_TRD2+
DOCK_LOM_TRD3DOCK_LOM_TRD3+
DOCK_LAN_ACTLED_YEL#
DOCK_LED_10#
DOCK_LED_100#
PI3L500E_TQFN56~D
3
NB_LAN_ACTLED_YEL#
LED_10_GRN#
LED_100_ORG#
DOCK_LOM_TRD0- <36>
DOCK_LOM_TRD0+ <36>
DOCK_LOM_TRD1- <36>
DOCK_LOM_TRD1+ <36>
DOCK_LOM_TRD2- <36>
DOCK_LOM_TRD2+ <36>
DOCK_LOM_TRD3- <36>
DOCK_LOM_TRD3+ <36>
DOCK_LAN_ACTLED_YEL# <36>
DOCK_LED_10# <36>
DOCK_LED_100# <36>
TO
RJ45
+2.5V_3.3V_LAN
1
C447
C442
0.1U_0402_16V4Z~D
2
TO
DOCK
0.1U_0402_16V4Z~D
0_0402_5%~D
@
1
C446
0.1U_0402_16V4Z~D
2
1
C440
2
@
0.1U_0402_16V4Z~D
2
+3.3V_LAN
R379
1
2
2
12
12
R321
150_0402_5%~D
JLOM
13
YELLOW
14
LR10#
LR100#
COMMON0
11
TRD1P
12
TRCT1
10
TRD1N
4
TRD2P
6
TRCT2
5
TRD2N
3
TRD3P
1
TRCT3
2
TRD3N
8
TRD4P
7
TRCT4
9
TRD4N
16
COMMON1
17
GREEN
15
ORANGE
TYCO_1368398-2~D
SW_LANTX0+
SW_LANTX0SW_LANTX1+
SW_LANTX1SW_LANTX2+
SW_LANTX2SW_LANTX3+
SW_LANTX3-
150_0402_5%~D
R384
12
12
R383 150_0402_5%~D
Place these caps as close
to the center tap pins
of the mag/connector.
1
TYCO_1368458-1 & Belfuse_L830-1J1C-47 / 4401E
TYCO_1368938-2 & Belfuse_L830-1J1C-43 /5752
1CT:1CT
1CT:1CT
1CT:1CT
1CT:1CT
4 X 75 OHMS
1000pF 2KV
TRP1P
TRP1N
TRP2P
TRP2N
TRP3P
TRP3N
TRP4P
TRP4N
SHIELD018SHIELD1
19
DELL CONFIDENTIAL/PROPRIETARY
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
LAN Transfomer and RJ45
LA-2881P
1
32 62Tuesday, December 13, 2005
of
2.0
Page 33
5
PCI_AD[0..31]<21,30,31,35>
+3.3V_R5C832
100K_0402_5%~D
D D
R427
CLKRUN#<23,31,37,38>
+3.3V_R5C832
1 2
0_0402_5%~D@
PCI_AD17
PCI_PIRQD#<21>
PCI_PIRQC#<21>
R438 0_0402_5%~D@
CBUS_GRST#<37>
CLK_PCI_PCCARD
@
10_0402_5%~D
12
10P_0402_50V8J~D@
1
C330
2
C C
CB_HWSPND#<37>
B B
R439
R435
C401
CLK_PCI_PCCARD<6>
R429 0_0402_5%~D
1 2
SYS_PME#<30,35,37>
1 2
R437
1 2
10K_0402_5%~D
12
BUS_GRST#
1U_0603_10V4Z~D
1
2
PCI_C_BE3#<21,31,35>
PCI_C_BE2#<21,31,35>
PCI_C_BE1#<21,30,35>
PCI_C_BE0#<21,31,35>
PCI_PAR<21,30,35>
PCI_FRAME#<21,31,35,36>
PCI_TRDY#<21,31,35>
PCI_IRDY#<21,31,35,36>
PCI_STOP#<21,30,35>
PCI_DEVSEL#<21,31,35>
1 2
PCI_PERR#<21,31,35>
PCI_SERR#<21,31,35>
PCI_REQ2#<21>
PCI_GNT2#<21>
PCI_RST#<21,30,34,35>
R426100_0402_5%~D
R441
1 2
0_0402_5%~D@
T6
R482
PCI_AD31
PCI_AD30
PCI_AD29
PCI_AD28
PCI_AD27
PCI_AD26
PCI_AD25
PCI_AD24
PCI_AD23
PCI_AD22
PCI_AD21
PCI_AD20
PCI_AD19
PCI_AD18
PCI_AD17
PCI_AD16
PCI_AD15
PCI_AD14
PCI_AD13
PCI_AD12
PCI_AD11
PCI_AD10
PCI_AD9
PCI_AD8
PCI_AD7
PCI_AD6
PCI_AD5
PCI_AD4
PCI_AD3
PCI_AD2
PCI_AD1
PCI_AD0
PCI_C_BE3#
PCI_C_BE2#
PCI_C_BE1#
PCI_C_BE0#
PCI_PAR
PCI_FRAME#
PCI_TRDY#
PCI_IRDY#
PCI_STOP#
PCI_DEVSEL#
PCI_IDSEL
PCI_PERR#
PCI_SERR#
PCI_REQ2#
PCI_GNT2#
PCI_RST#
BUS_GRST#
100K_0402_5%~D
1 2
Layout Note: Place close to R5C832 Chip
TPBIAS0
TPA0+
TPA0TPB0+
TPB0-
A A
R481
12
R479
C397
56.2_0603_1%~D
R480
56.2_0603_1%~D
12
270P_0402_50V7K~D
2
1
0.01U_0402_16V7K~D
56.2_0603_1%~D
12
C399
R478
R477
5
0.33U_0603_10V7K~D
C398
1
1
2
2
56.2_0603_1%~D
12
1 2
5.1K_0603_1%~D
U36
125
AD31
126
AD30
127
AD29
1
AD28
2
AD27
3
AD26
5
AD25
6
AD24
9
AD23
11
AD22
12
AD21
14
AD20
15
AD19
17
AD18
18
AD17
19
AD16
36
AD15
37
AD14
38
AD13
39
AD12
40
AD11
42
AD10
43
AD9
44
AD8
46
AD7
47
AD6
48
AD5
49
AD4
50
AD3
51
AD2
52
AD1
53
AD0
7
C/BE3#
21
C/BE2#
35
C/BE1#
45
C/BE0#
33
PAR
23
FRAME#
25
TRDY#
24
IRDY#
29
STOP#
26
DEVSEL#
8
IDSEL
30
PERR#
31
SERR#
124
REQ#
123
GNT#
121
PCICLK
119
PCIRST#
71
GBRST#
117
CLKRUN#
70
PME#
115
INTA#
116
INTB#
69
HWSPND#
66
TEST
111
AGND
107
AGND
103
AGND
102
AGND
99
AGND
97
NC
R5C832_TQFP128P~D
Layout Note: Place close to 1394 connector
L41 DLW21SN121SQ2_0805~D@
4
4
1
1
4
4
1
1
L42 DLW21SN121SQ2_0805~D@
R473
0_0402_5%~D
1 2
R472
0_0402_5%~D
1 2
R474
0_0402_5%~D
1 2
R475
0_0402_5%~D
1 2
R5C832
3
2
3
2
4
10
VCC_PCI3V
20
VCC_PCI3V
27
VCC_PCI3V
32
VCC_PCI3V
41
VCC_PCI3V
128
VCC_PCI3V
61
VCC_RIN
VCC_ROUT
VCC_ROUT
VCC_ROUT
VCC_ROUT
VCC_ROUT
VCC_3V
VCC_MD3V
AVCC_PHY3V
AVCC_PHY3V
AVCC_PHY3V
AVCC_PHY3V
TPBIAS0
TPAP0
TPAN0
TPBP0
TPBN0
MDIO00
MDIO01
MDIO02
MDIO03
MDIO04
MDIO05
MDIO06
MDIO07
MDIO08
MDIO09
MDIO10
MDIO11
MDIO12
MDIO13
MDIO14
MDIO15
MDIO16
MDIO17
MDIO18
MDIO19
MSEN
XDEN
XI
XO
FIL0
REXT
VREF
UDIO0/SERIRQ#
UDIO1
UDIO2
UDIO3
UDIO4
UDIO5
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
TPA0_D+
3
TPA0_D-
2
TPB0_D+
3
TPB0_D-
2
+3.3V_R5C832
CARD_EN
4
16
34
64
114
120
67
86
+3.3V_RUN_PHY
98
106
110
112
113
109
108
105
104
80
79
78
77
76
75
74
73
88
84
82
81
93
90
91
89
92
87
85
83
58
55
94
95
96
101
100
72
60
56
65
59
57
4
13
22
28
54
62
63
68
118
122
J1394
4
4
G1
3
3
2
2
1
1
G2
TYCO_1775260-1~D
U29
5
4
AAT4250IGV-T1_SOT23-5~D
1
C339
0.1U_0402_16V4Z~D
2
+VCC_ROUT
+3.3V_R5C832
C403
0.01U_0402_16V7K~D
1
2
TPBIAS0
TPA0+
TPA0TPB0+
TPB0SDCD#_XDCD0#
MSCD#_XDCD1
XD_CE#
SDWP#_XDRB#
CARD_EN
XDWP#
TP_SD/MMC/MS/XD_LED#
SDCMD_MSBS_XDWE#
SDCLK_MSCLK_XDRE#
SDDATA0_MSDATA0_XDD0
SDDATA1_MSDATA1_XDD1
SDDATA2_MSDATA2_XDD2
SDDATA3_MSDATA3_XDD3
XDD4
XDD5
XDD6
XDD7
XDCLE
XDALE
R5C832XI
R5C832XO
IRQ_SERIRQ
5
6
IN
ON/OFF#
10K_0402_5%~D
1 2
1 2
100K_0402_5%~D
MSCD#_XDCD1
OUT
GND
N.C
UDIO4
UDIO5
0.01U_0402_16V7K~D
C335
C409
1
2
C336
10U_0805_6.3V6M~D
1
2
+3.3V_RUN_CARD
C357
T5
Layout Note:
Place C340,C338,R436 close to R5C832
C3400.01U_0402_16V7K~D
1 2
IRQ_SERIRQ <23,30,37,38>
+3.3V_R5C832
R440
R487
D13
RB751V_SOD323~D
2 1
D14
RB751V_SOD323~D
2 1
D22
RB751V_SOD323~D
2 1
R750 0_0402_5%~D@
1 2
XD_SW#
SDWP#_XDRB#
SDCLK_MSCLK_XDRE#
XD_CE#
XDCLE
XDALE
SDCMD_MSBS_XDWE#
XDWP#
SDDATA0_MSDATA0_XDD0
SDDATA1_MSDATA1_XDD1
SDDATA2_MSDATA2_XDD2
SDDATA3_MSDATA3_XDD3
XDD4
XDD5
XDD6
XDD7
+3.3V_RUN_XD
+3.3V_RUN_CARD
1
2
3
1U_0603_10V4Z~D
C342
1
2
3
+3.3V_R5C832
0.01U_0402_16V7K~D
0.1U_0402_16V4Z~D
C407
C334
1
1
2
1
2
1
2
2
0.01U_0402_16V7K~D
0.01U_0402_16V7K~D
C356
C355
1
1
2
2
Place close to J5IN1
0.01U_0402_16V7K~D
C338
R436
2
1
MS_INS#
1
C361
2
10U_0805_6.3V6M~D
0.01U_0402_16V7K~D
1 2
2.2U_0805_10V6K~D
C328
R445
10K_0402_1%~D
2
G
0.01U_0402_16V7K~D
C323
1
1
2
2
150K_0402_5%~D
+3.3V_R5C832
13
D
S
J5IN1
2
XD1_CD
3
XD2_R/B#
4
XD3_RE#
5
XD4_CE#
6
XD5_CLE
7
XD6_ALE
8
XD7_WE#
9
XD8_WP#
11
XD10_D0
12
XD11_D1
13
XD12_D2
14
XD13_D3
15
XD14_D4
16
XD15_D5
17
XD16_D6
18
XD17_D7
19
XD18_VCC
1
XD0_GND
10
XD9_GND
42
GND0
43
GND1
44
GND2
MOLEX_480001002~D
0.01U_0402_16V7K~D
C324
1
2
22P_0402_50V8J~D
22P_0402_50V8J~D
12
Q77
2N7002_SOT23~D
+3.3V_R5C832
0.01U_0402_16V7K~D
0.01U_0402_16V7K~D
0.01U_0402_16V7K~D
C325
BLM21AG601SN1D_0805~D
C404
1 2
1 2
C405
R749
0_0402_5%~D@
4 IN 1 CONN
Interface
C329
C326
1
1
2
2
+VCC_ROUT
L32
1 2
Layout Note: Place close to R5C832
and Shield GND
X2
24.576MHz_16P_1BG24576CKIA~D
1 2
R446
10K_0402_5%~D
12
12
R117
10K_0402_5%~D
MS4_DATA0
MS3_DATA1
xD Card
MS5_DATA2
MS7_DATA3
MS8_SCLK
MS Card
MS10_VSS
Interface
SD7_DAT0
SD8_DAT1
SD9_DAT2
SD1_CD/DAT3
SD_SW/WP
SD Card
Interface
10U_0805_6.3V6M~D
1
2
C322
1
2
C333
1
2
1 2
220_0402_5%~D
MS2_BS
MS6_INS
MS9_VCC
MS1_VSS
SD5_CLK
SD2_CMD
SD_SW
SD4_VDD
SD3_VSS
SD6_VSS
SD_GND
+3.3V_R5C832
0.01U_0402_16V7K~D
0.01U_0402_16V7K~D
C411
1
2
10U_0805_6.3V6M~D
0.01U_0402_16V7K~D
C331
1
2
R5C832XI
R5C832XO
R486
+3.3V_R5C832
+3.3V_RUN_CARD
23
22
24
26
27
21
25
28
20
29
36
37
38
30
34
31
40
41
33
32
35
39
2
R434
1 2
0_0805_5%~D
0.47U_0402_10V4Z~D
C406
C327
1
2
+3.3V_RUN_PHY
0.1U_0402_16V4Z~D
C332
C337
1
2
SDDATA0_MSDATA0_XDD0
SDDATA1_MSDATA1_XDD1
SDDATA2_MSDATA2_XDD2
SDDATA3_MSDATA3_XDD3
SDCMD_MSBS_XDWE#
MS_INS#
SDDATA0_MSDATA0_XDD0
SDDATA1
SDDATA2
SDDATA3_MSDATA3_XDD3
SDCMD_MSBS_XDWE#
SDCD#_XDCD0#
SDWP#_XDRB#
4 IN 1 CardReader CONN.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
+3.3V_RUN
0.47U_0402_10V4Z~D
1
2
1000P_0402_50V7K~D
1
2
SDDATA1_MSDATA1_XDD1
SDDATA2_MSDATA2_XDD2
+3.3V_RUN_CARD
+15V_SUS
1 2
SDCD#_XDCD0#
Media I/F
MDIO00
MDIO01
MDIO02
MDIO03
MDIO04
MDIO05
MDIO06
MDIO07
MDIO08
MDIO09
MDIO10
MDIO11
MDIO12
MDIO13
MDIO14
MDIO15
MDIO16
MDIO17
MDIO18
MDIO19
Pull-up
R447
10K_0402_5%~D
0_0402_5%~D
1 2
0_0402_5%~D
1
SD,MMC,MS,XD muti-function pin define
SD Card
SDCD#
SDWP#
SDPWR0
SDPWR1
SDLED#
SDEXTCK
SDCCMD
SDCCLK
SDCDAT0
SDCDAT1
SDCDAT2
SDCDAT3
Function set pin define
UDIO4UDIO3 XDEN
R747 0_0402_5%~D@
1 2
D
1 3
2
G
R484
SDCLK_MSCLK_XDRE#MSCLK
R485
SDCLK_MSCLK_XDRE#SDCLK
12
MMC Card
MMCCD#
MMCPWR
MMCLED#
MMCCMD
MMCCLK
MMCDAT
MSEN
Pull-upPull-up
G
2
13
D
Q75
S
2N7002_SOT23~D
Pull-up
Solve MS Duo Adaptor short problem
Q85
S
2N7002_SOT23~D
R748 0_0402_5%~D@
1 2
Q78
2N7002_SOT23~D
D
S
1 3
R451 0_0805_5%~D@
G
2
XD_CDSW#XD_CDSW#SDCD#_XDCD0#
Note:
If countermeasure
circuit is needed,
please populate D22,
R446, R117, R447,
Q75-Q78, Q85 and
no-stuff R451,
R747-R750.
If countermeasure
circuit is NOT needed,
please no-stuff D22,
R446, R117, R447,
Q75-Q78, Q85 and stuff
R451, R747-R750.
MS Card
MSCD#
MSWR
MSLED#
MSEXTCK
MSBS
MSCCLK
MSCDAT0
MSCDAT1
MSCDAT2
MSCDAT3
Function
Enable
SD,XD,MS,MMC Card
SDDATA1
SDDATA2
1 2
D
S
13
Q76
SI2303BDS-T1-E3_SOT23-3~D
G
2
XD Card
XDCD0#
XDCD1#
XDCE#
XDR/B#
XDPWR
XDWP#
XDLED#
XDWE#
XDRE#
XDCDAT0
XDCDAT1
XDCDAT2
XDCDAT3
XDCDAT4
XDCDAT5
XDCDAT6
XDCDAT7
XDCLE
XDALE
+3.3V_RUN_XD
DELL CONFIDENTIAL/PROPRIETARY
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
R5C832-1394 and 5 IN 1
LA-2881P
33 62Tuesday, December 13, 2005
1
of
2.0
Page 34
5
MINI Wireless LAN Card
D D
C C
PCIE_WAKE#<30,37>
COEX2_WLAN_ACTIVE<28>
COEX1_BT_ACTIVE<28>
MINICLK_REQ#<6>
CLK_PCIE_MINI#<6>
CLK_PCIE_MINI<6>
HOST_DEBUG_RX<38>
PCIE_RX2-<23>
PCIE_RX2+<23>
PCIE_TX2-<23>
PCIE_TX2+<23>
JCLIP
1
1
2
2
3
3
4
4
MOLEX_48099-5200~D
8051TX<38>
PCIE_WAKE#
COEX2_WLAN_ACTIVE
COEX1_BT_ACTIVE
MINICLK_REQ#
CLK_PCIE_MINI#
CLK_PCIE_MINI
HOST_DEBUG_RX
8051TX
PCIE_RX2PCIE_RX2+
PCIE_TX2PCIE_TX2+
+3.3V_RUN
C296
0.1U_0402_16V4Z~D
0.047U_0402_16V4Z~D
C297
1
1
2
2
JMINI
1
1
3
3
5
5
7
7
9
9
11
11
13
13
15
15
17
17
19
19
21
21
23
23
25
25
27
27
29
29
31
31
33
33
35
35
37
37
39
39
41
41
43
43
45
45
47
47
49
49
51
51
53
GND1
TYCO_1775838-1~D
GND2
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
SMART CARD
MODE1
LOW
HIGH
B B
Place closely pin 3
CLK_SMCARD_48M
A A
ECE_USBP2-<37>
ECE_USBP2+<37>
CLOCK INPUT
48MHz
6MHz Crystal
+3.3V_RUN
12
R234
PCI_RST#<21,30,33,35>
CLK_SMCARD_48M<6>
@
10_0402_5%~D
12
R189
@
4.7P_0402_50V8C~D
C229
1
2
5
+5V_RUN
5@
5@
C249
C230
1.5K_0402_5%~D5@
0.1U_0402_16V4Z~D
4.7U_0805_10V4Z~D
1
1
2
2
MD0
12
R183
U15
5
VCC5V_IN
28
VCC5V_IN
17
UPD-
16
UPD+
14
RST#
30
NC
31
NC
3
XI/48M_IN
4
XO
32
MODE0/SC_LED#
1
MODE1
2
MODE2
11
4.7K_0402_5%~D5@
GND
13
GND
26
GND
C244
12
1U_0603_10V4Z~D5@
VR_CPR6VR_CPR
+3.3V_OUT
EGATEDEGATED+
SC_VCC
SC_RST#
SC_CLK
SC_C4
SC_IO
SC_DET#
RF_OUT
RF_IN/RX
RF_CLK
RF_AUX
OZ77C6LN-B1_QFN32~D5@
12
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
DPD-
DPD+
4
+3.3V_RUN
0.047U_0402_16V4Z~D
0.047U_0402_16V4Z~D
C239
1
2
+3.3V_LAN
C309
1
2
1
2
5@
C292
R525
0.1U_0402_16V4Z~D
1
2
0.047U_0402_16V4Z~D
4.7U_0805_10V4Z~D
+1.5V_RUN
5@
HOST_DEBUG_TX <38>
WLAN_RADIO_DIS# <37>
PLTRST3# <21>
ICH_SMBCLK <6,23,30>
ICH_SMBDATA <6,23,30>
8051RX <38>
LED_WLAN# <39>
1 2
5@
0.1U_0402_16V4Z~D
C289
C317
1
2
HOST_DEBUG_TX
WLAN_RADIO_DIS#
PLTRST3#
ICH_SMBCLK
ICH_SMBDATA
ECE_USBP1ECE_USBP1+
8051RX
LED_WLAN#
LED_BT_OUT
C310
1
2
+3.3V_OUT
5@
4.7U_0805_10V4Z~D
C238
1
2
29
R245 15K_0402_5%~D
19
18
21
20
27
24
23
22
25
15
8
7
9
10
1 2
R246 15K_0402_5%~D
1 2
SCCDSCCD+
SC_RST#
SC_CLK
SC_C4
SC_IO
SC_DET#
Layout Notes
SCCD-/SCCD+ msut be kept equal length
with a differ en ti al impedance of 90 ohms
4
+3.3V_LAN
C301
ECE_USBP1- <37>
ECE_USBP1+ <37>
BT_ACTIVE <28,39>
0_0402_5%~D@
R261 220_0402_5%~D5@
R251 33_0402_5%~D5@
R564 220_0402_5%~D5@
R250 220_0402_5%~D5@
R565 15K_0402_5%~D5@
1 2
R244 15K_0402_5%~D5@
1 2
3
C490
0.1U_0402_16V4Z~D
1
2
EXPRCRD_STBY#<37>
ECE_USBP3-<37>
ECE_USBP3+<37>
+3.3V_SUS
R543 100K_0402_5%~D
1 2
R539 0_0402_5%~D@
1 2
R530 100K_0402_5%~D
1 2
R529 100K_0402_5%~D
1 2
CPPE#<37>
R314
0_0402_5%~D
1 2
R315
0_0402_5%~D
1 2
4
4
1
1
L15 DLW21SN900SQ2_0805~D@
3
2
USB SMARTCARD READER.
TYPE A (5V), B (3V), AB (5V/3V)
& USB SMARTCARDS ARE SUPPORTED.
C252
SC_DET#<37>
1
2
12
12
12
12
+SC_VCC
5@
0.1U_0402_16V4Z~D
C255
5@
1
2
SCCD+
SCCD-
4.7U_0805_10V4Z~D
+SC_VCC
5@
10K_0402_5%~D
12
R303
5@
47K_0402_5%~D
12
R243
0.1U_0402_16V4Z~D
5@
C276
1
2
Layout Note: Place R509~R513 and C631 closely JSC
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
C265
+SC_VCC
5@
5@
0.1U_0402_16V4Z~D
1U_0603_10V4Z~D
C264
1
1
2
2
JSMART
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
MOLEX_52610-1075~D5@
+3.3V_SUS
0.1U_0402_16V4Z~D
1
2
PLTRST2#<21,37,38>
3
2
C482
+3.3V_RUN
0.1U_0402_16V4Z~D
1
2
2
+1.5V_RUN
0.1U_0402_16V4Z~D
C484
1
2
PLTRST2#
EXPRCRD_STBY_R#
CPPE#
CPUSB#
U37
12
1.5Vin
14
1.5Vin
2
3.3Vin
4
3.3Vin
AUX_IN17AUX_OUT
6
SYSRST#
20
SHDN#
1
STBY#
10
CPPE#
9
CPUSB#
18
RCLKEN
R5538D001_ES4_QFN20~D
1.5Vout
1.5Vout
3.3Vout
3.3Vout
PERST#
OC#
GND
+1.5V_CARD
11
13
3
5
15
19
8
16
NC
7
+1.5V_CARD: Max. 650mA, Average 500mA
+3.3V_CA R D: Max. 1300mA, Average 1000mA
ECE_USBP3_D-
ECE_USBP3_D+
JEXP
112
334
ICH_SMBCLK<6,23,30>
CLK_PCIE_EXPCARD#<6>
CLK_PCIE_EXPCARD<6>
PCIE_RX4-<23>
PCIE_RX4+<23>
PCIE_TX4-<23>
PCIE_TX4+<23>
CPUSB#
GND5GND
778
9910
111112
131314
151516
171718
191920
212122
232324
GND25GND
272728
292930
31
GND
GND
FOX_QTS0030A-3121-9F~D
DELL CONFIDENTIAL/PROPRIETARY
Title
Size Document Number Rev
LA-2881P
2
Date: Sheet
1
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
C473
1
2
+3.3V_CARDAUX
0.1U_0402_16V4Z~D
+1.5V_CARD
+3.3V_CARDAUX
+3.3V_CARD
C273
+3.3V_CARD
C478
1
2
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
1
1
C491
2
2
PCIE_WAKE#
EXPR_CARD_RST#
CARD_CLK_REQ#
CPPE#
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
C472
1
2
C467
PCIE_WAKE# <30,37>ICH_SMBDATA<6,23,30>
CARD_CLK_REQ# <6>
C479
1
2
C492
1
2
EXPR_CARD_RST#
0.1U_0402_16V4Z~D
1
2
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
Compal Electronics, Inc.
SMART/EXPRESS/MINI CARD
34 62Tuesday, December 13, 2005
1
10U_0805_6.3V6M~D
C468
1
2
2.0
of
Page 35
5
+5V_RUN
D5
2 1
D D
C C
PCI_AD[0..31]<21,30,31,33>
B B
A A
RB751V_SOD323~D5@
QUIETE#
QUIETE#
PCI_RST#<21,30,33,34>
PCI_GNT0#<21,36>
SYS_PME#<30,33,37>
PCI_C_BE3#<21,31,33>
PCI_PIRQA#<21>
PCI_STOP#<21,30,33>
PCI_TRDY#<21,31,33>
PCI_FRAME#<21,31,33,36>
PCI_C_BE2#<21,31,33>
PCI_PERR#<21,31,33>
PCI_PLOCK#<21>
PCI_IRDY#<21,31,33,36>
PCI_C_BE1#<21,30,33>
PCI_PAR<21,30,33>
PCI_SERR#<21,31,33>
PCI_DEVSEL#<21,31,33>
PCI_C_BE0#<21,31,33>
+VCC_QBUFD
PCI_AD31
PCI_AD30
PCI_AD29
PCI_AD28
PCI_AD27
PCI_AD26
PCI_AD24
PCI_AD25
PCI_AD23
PCI_AD20
PCI_AD22
PCI_AD19
PCI_AD21
PCI_AD16
PCI_AD18
PCI_AD17
PCI_AD15
PCI_AD14
PCI_AD13
PCI_AD11
PCI_AD12
PCI_AD10
PCI_AD9
PCI_AD8
PCI_AD7
PCI_AD6
PCI_AD4
PCI_AD5
PCI_AD3
PCI_AD2
PCI_AD0
PCI_AD1
PCI_RST#
PCI_GNT0#
SYS_PME#
PCI_C_BE3#
PCI_PIRQA#
PCI_STOP#
PCI_TRDY#
PCI_FRAME#
PCI_C_BE2#
PCI_PERR#
PCI_PLOCK#
PCI_IRDY#
PCI_C_BE1#
PCI_PAR
PCI_SERR#
PCI_DEVSEL#
PCI_C_BE0# DOCK_C_BE0#
PCI_AD24 DOCK_PCI_IDSEL
4
U46
1
NC1
2
A1
3
A2
4
A3
5
A4
6
A5
7
A6
8
A7
9
A8
10
GND1
11
NC2
12
A9
13
A10
14
A11
15
A12
16
A13
17
A14
18
A15
19
A16
20
GND2
21
NC3
22
A17
23
A18
24
A19
25
A20
26
A21
27
A22
28
A23
29
A24
30
GND3
31
NC4
32
A25
33
A26
34
A27
35
A28
36
A29
37
A30
38
A31
39
A32
40
GND4
47
2
3
4
5
6
7
8
9
10
11
14
15
16
17
18
19
20
21
22
23
1
13
D6
2 1
RB751V_SOD323~D5@
PI5C34X2245BE_BQSOP80~D5@
U45
OE1
OE235VCC2
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
NC1
NC2
PI5C162861BE_BQSOP48~D5@
VCC4
OE1#
VCC3
OE2#
VCC2
OE3#
VCC1
OE4#
VCC1
GND1
GND2
3
+VCC_QBUF
0.047U_0402_16V4Z~D5@
0.1U_0402_16V4Z~D5@
4.7K_0402_5%~D5@
12
C150
R103
80
79
78
B1
77
B2
76
B3
75
B4
74
B5
73
B6
72
B7
71
B8
70
69
68
B9
67
B10
66
B11
65
B12
64
B13
63
B14
62
B15
61
B16
60
59
58
B17
57
B18
56
B19
55
B20
54
B21
53
B22
52
B23
51
B24
50
49
48
B25
47
B26
46
B27
45
B28
44
B29
43
B30
42
B31
41
B32
36
48
46
B0
45
B1
44
B2
43
B3
42
B4
41
B5
40
B6
39
B7
38
B8
37
B9
34
B10
33
B11
32
B12
31
B13
30
B14
29
B15
28
B16
27
B17
26
B18
25
B19
12
24
DOCK_AD31
DOCK_AD30
DOCK_AD29
DOCK_AD28
DOCK_AD27
DOCK_AD26
DOCK_AD24
DOCK_AD25
DOCK_AD23
DOCK_AD20
DOCK_AD22
DOCK_AD19
DOCK_AD21
DOCK_AD16
DOCK_AD18
DOCK_AD17
DOCK_AD15
DOCK_AD14
DOCK_AD13
DOCK_AD11
DOCK_AD12
DOCK_AD10
DOCK_AD9
DOCK_AD8
DOCK_AD7
DOCK_AD6
DOCK_AD4
DOCK_AD5
DOCK_AD3
DOCK_AD2
DOCK_AD0
DOCK_AD1
C157
0.1U_0402_16V4Z~D5@
1 2
DOCK_PCIRST#
DOCK_GNT0#
DOCK_PME#
DOCK_C_BE3#
DOCK_PIRQA#
DOCK_STOP#
DOCK_TRDY#
DOCK_FRAME#
DOCK_C_BE2#
DOCK_PERR#
DOCK_LOCK#
DOCK_IRDY#
DOCK_C_BE1#
DOCK_PAR
DOCK_SERR#
DOCK_DEVSEL#
C124
1
2
0.047U_0402_16V4Z~D5@
0.1U_0402_16V4Z~D5@
C144
C134
1
1
1
2
2
2
+3.3V_RUN
100K_0402_5%~D5@
R620
DOCK_PCI_EN#<36>
QBUFEN#<37>
DOCK_PCI_EN#
QBUFEN#
1 2
5
1
P
INA
2
INB
G
3
2
DOCK_AD0
DOCK_AD1
DOCK_AD2
DOCK_AD3
DOCK_AD4
DOCK_AD5
DOCK_AD6
DOCK_AD7
DOCK_AD8
DOCK_AD9
DOCK_AD10
DOCK_AD11
DOCK_AD12
DOCK_AD13
DOCK_AD14
DOCK_AD15
DOCK_AD16
DOCK_AD17
DOCK_AD18
DOCK_AD19
DOCK_AD20
DOCK_AD21
DOCK_AD22
DOCK_AD23
DOCK_AD24
DOCK_AD25
0.1U_0402_16V4Z~D5@
C563
1
2
U44
QUIETE#
4
O
74AHC1G32GW_SOT353-5~D5@
DOCK_AD26
DOCK_AD27
DOCK_AD28
DOCK_AD29
DOCK_AD30
DOCK_AD31
DOCK_C_BE0#
DOCK_C_BE1#
DOCK_C_BE2#
DOCK_C_BE3#
DOCK_DEVSEL#
DOCK_STOP#
DOCK_PIRQA#
DOCK_FRAME#
DOCK_SERR#
DOCK_IRDY#
DOCK_PERR#
DOCK_TRDY#
DOCK_PAR
DOCK_GNT0#
DOCK_PME#
DOCK_LOCK#
DOCK_PCIRST#
DOCK_PCI_IDSEL
1
DOCK_AD[0..31] <36>
DOCK_C_BE0# <36>
DOCK_C_BE1# <36>
DOCK_C_BE2# <36>
DOCK_C_BE3# <36>
DOCK_DEVSEL# <36>
DOCK_STOP# <36>
DOCK_PIRQA# <36>
DOCK_FRAME# <36>
DOCK_SERR# <36>
DOCK_IRDY# <36>
DOCK_PERR# <36>
DOCK_TRDY# <36>
DOCK_PAR <36>
DOCK_GNT0# <36>
DOCK_PME# <36>
DOCK_LOCK# <36>
DOCK_PCIRST# <36>
DOCK_PCI_IDSEL <36>
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
DOCKING BUFFER
LA-2881P
35 62Tuesday, December 13, 2005
1
2.0
of
Page 36
5
JDOCKA
1
S1
2
DVI2_CLK-
DVI2_CLK-<19>
DVI2_CLK+<19>
D D
DVI2_TX2+<19>
DVI2_TX2-<19>
DVI2_TX1+<19>
DVI2_TX1-<19>
DVI2_TX0+<19>
DVI2_TX0-<19>
CLK_PCI_DOCK<6>
DOCK_PIRQA#<35>
DOCK_SMB_CLK<38>
DOCK_SMB_DAT<38>
CLK_DOCK<38>
DAT_DOCK<38>
C C
DVI2_CLK+
DVI_TDVI_T+
DVI_T+
DVI_T-
DOCK_PSID
DVI_T+
DVI_T-
DVI2_TX2+
DVI2_TX2-
DVI2_TX1+
DVI2_TX1-
DVI2_TX0+
DVI2_TX0-
DOCK_AD31
CLK_PCI_DOCK DOCK_PCIRST#
DOCK_PIRQA#
DOCK_SMB_CLK
DOCK_SMB_DAT
CLK_DOCK
DAT_DOCK
Place closely pin 35
CLK_PCI_DOCK
33_0402_5%~D@
12
R116
C151
22P_0402_50V8J~D@
1
2
B B
+3.3V_ALW
12
R29
+5V_ALW
12
R30
100K_0402_5%~D
5@
DOCK_DET#
A A
47K
2
DOCK_PWR_EN<37>
100K_0402_5%~D5@
13
Q16
PDTC144EK_SOT23~D
5@
47K
5
3
4
5
6
7
8
9
10
11
12
13
15
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
45
47
48
49
50
51
52
53
54
55
DOCK_PWR_EN
S2
S3
S4
S5
S6
S7
S8
S9
S10
S11
S12
S13
S15
S17
S18
S19
S20
S21
S22
S23
S24
S25
S26
S27
S28
S29
S30
S31
S32
S33
S34
S35
S36
S37
S38
S39
S40
S41
S42
S43
S45
S47
S48
S49
S50
S51
S52
S53
S54
S55
S69
S70
S71
S72
S73
S74
S75
S76
S77
S78
S79
S80
S81
S82
S83
S84
S85
S86
S87
S88
S89
S90
S91
S92
S93
S94
S95
S96
S97
S98
S99
S100
S101
S102
S103
S104
S105
S106
S107
S108
S109
S110
S111
S112
S113
S114
S115
S116
S117
S118
S119
S120
S121
S122
S125
S126
S127
S128
M136
AMP_1473681~D5@
+PWR_SRC
2
1
+3.3V_SUS
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
125
126
127
128
136
C52
5@
0.47U_0805_25V7k
DOCKED <32,37>
D3
2
3
SM05_SOT23@
U3
3
74AHCT1G08GW_SOT353-5~D5@
G
B
4
Y
A
P
5
0.1U_0603_50V4Z~D5@
1 2
RED
D_SERIRQ
DOCK_PCI_IDSEL
D_DLDRQ1#
D_LFRAME#
DVI_SCLK_L
DVI_SDAT_L
DVI_DETECT_L
DOCK_AD8
DOCK_C_BE0#
DOCK_AD14
DOCK_AD15
DOCK_DEVSEL#
DOCK_IRDY#
DOCK_AD19
DOCK_AD20
DOCK_AD27
DOCK_AD28
DOCK_AD30
USBP7USBP7+
DOCK_SMB_INT#
CLK_KBD
DAT_KBD
+2.5V_3.3V_LAN
R53
100K_0603_5%~D
1 2
5@
+G_DOC_PWRSRC
1
Z3308
C47
4
RED <20>
D_SERIRQ <37>
DOCK_PCI_IDSEL <35>
D_DLDRQ1# <37>
D_LFRAME# <37>
DVI_SCLK_L <19>
DVI_SDAT_L <19>
DVI_DETECT_L <19>DOCK_PSID<43>
DOCK_C_BE0# <35>
DOCK_PAR<35>
DOCK_SERR#<35>
DOCK_LOCK#<35>
DOCK_FRAME#<35>
DOCK_C_BE2#<35>
DOCK_PME#<35>
DOCK_PCI_EN#<35>
SPDIF_DOCK<20>
DOCK_LED_10#<32>
DOCK_LED_100#<32>
+3.3V_RUN
C168
5@
0.01U_0402_16V7K~D
C174
0.01U_0402_16V7K~D5@
DOCK_LOM_TRD1-<32>
DOCK_LOM_TRD1+<32>
DOCK_LOM_TRD0-<32>
DOCK_LOM_TRD0+<32>
R142
0_0402_5%~D5@
12
DOCK_LOM_TRD3- <32>
DOCK_LOM_TRD3+ <32>
DOCK_LOM_TRD2- <32>
DOCK_LOM_TRD2+ <32>
DOCK_DEVSEL# <35>
DOCK_IRDY# <35>
DOCK_GNT0# <35>
USBP7- <23>
USBP7+ <23>
DOCK_SMB_INT# <38>
CLK_KBD <38>
DAT_KBD <38>
C166
5@
0.01U_0402_16V7K~D
1 2
C171
0.01U_0402_16V7K~D5@
1 2
DOCK_RING
+2.5V_LAN_R
PLACE TERMINATIONS CLOSE TO DOCK CONNECTOR
8
+DOCK_PW R_SRC
7
1
2
3
2
G
100K_0402_5%~D5@
12
R28
4
6
5
4
12
R46
100K_0402_5%~D
5@
Z3307
13
D
Q15
2N7002_SOT23~D
5@
S
Q19
FDS4435_NL_SO8~D5@
+3.3V_RUN
12
R71
12
R72
3
DOCK_DET# DOCK_DET#
GREEN
GREEN<20>
BLUE
BLUE<20>
TV_C<20>
R125 100K_0402_5%~D@
DVI_T+
D_LAD1
D_LAD2
D_LAD3
DOCK_AD1
DOCK_AD0
DOCK_AD3
DOCK_AD4
DOCK_AD7
DOCK_AD9
DOCK_AD10
DOCK_AD11
DOCK_PAR
DOCK_SERR#
DOCK_LOCK#
DOCK_FRAME#
DOCK_C_BE2#
DOCK_AD16
DOCK_AD22
DOCK_AD23
DOCK_AD24
DOCK_AD29
DOCK_PME#
TV_C
DOCK_PCI_EN#
SPDIF_DOCK
DOCK_LED_10#
DOCK_LED_100#
DOCK_OWNS_PCI
12
DOCK_TIP
+3.3V_RUN
12
R70
12
R69
22K_0402_5%~D@
DVI_T-
10K_0402_5%~D@
D_LAD1<37>
D_LAD2<37>
D_LAD3<37>
12
12
10K_0402_5%~D@
22K_0402_5%~D@
JDOCKB
137
S137
138
S138
139
S139
140
S140
141
S141
142
S142
143
S143
144
S144
145
S145
146
S146
147
S147
148
S148
149
S149
150
S150
151
S151
152
S152
153
S153
154
S154
155
S155
156
S156
157
S157
158
S158
159
S159
160
S160
161
S161
162
S162
163
S163
164
S164
165
S165
166
S166
167
S167
168
S168
169
S169
170
S170
171
S171
172
S172
173
S173
174
S174
175
S175
176
S176
177
S177
178
S178
179
S179
180
S180
181
S181
182
S182
183
S183
184
S184
185
S185
186
S186
187
S187
188
S188
189
S189
190
S190
193
S193
194
S194
195
S195
196
S196
204
M204
PCI_GNT0#<21,35>
PCI_IRDY#<21,31,33,35>
PCI_FRAME#<21,31,33,35>
S205
S206
S207
S208
S209
S210
S211
S212
S213
S214
S215
S216
S217
S218
S220
S222
S223
S224
S225
S226
S227
S228
S229
S230
S231
S232
S233
S234
S235
S236
S237
S238
S239
S240
S241
S242
S243
S244
S245
S246
S247
S248
S250
S252
S253
S254
S255
S256
S257
S258
S259
AMP_1473681~D5@
DOCK_TIP
DOCK_RING
205
206
207
208
209
210
211
212
213
214
215
216
217
218
220
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
250
252
253
254
255
256
257
258
259
PCI_GNT0#
PCI_IRDY#
PCI_FRAME#
DAT_DDC2
CLK_DDC2
HSYNC_DOCK
VSYNC_DOCK
D_CLKRUN#
D_LAD0
DOCK_SIO_ALERT#
DOCK_AD2
DOCK_AD5
DOCK_AD6
DOCK_AD12
DOCK_AD13
DOCK_C_BE1#
DOCK_PERR#
DOCK_STOP#
DOCK_TRDY#
DOCK_AD17
DOCK_AD18
DOCK_AD21
DOCK_C_BE3#
DOCK_AD25
DOCK_AD26
PCI_REQ0#
TV_CVBS
TV_Y
DOCK_LAN_ACTLED_YEL#
HDD_LED
U8
1
NC
2
IN A
3
GND
1
2
3
MC74VHC1G04DFT2G_SC70-5~D5@
+3.3V_RUN
1
IN1
2
IN2
JWIRE2
1
2
3
44G2
OUT Y
0.1U_0402_16V4Z~D5@
5
U7
P
O
G
3
5
G1
6
MOLEX_48227-0401~D5@
2
DAT_DDC2 <20>
CLK_DDC2 <20>
HSYNC_DOCK <20>
VSYNC_DOCK <20>
D_CLKRUN# <37>
D_LAD0 <37>
DOCK_SIO_ALERT# <37>
DOCK_C_BE1# <35>
DOCK_PERR# <35>
DOCK_STOP# <35>
DOCK_TRDY# <35>
DOCK_C_BE3# <35>
PCI_REQ0# <21>
DOCK_PCIRST# <35>
TV_CVBS <20>
TV_Y <20>
DOCK_LAN_ACTLED_YEL# <32>
HDD_LED <39>
+3.3V_RUN
0.1U_0402_16V4Z~D5@
5
VCC
4
C162
1 2
Z3306
4
74AHC1G08GW_SOT353-5~D5@
1 2
Z3305
C64
C159
+DOCK_PW R_SRC
0.1U_0603_50V4Z~D5@
1000P_0402_50V7K~D5@
C67
1
1
2
2
+3.3V_RUN
0.1U_0402_16V4Z~D5@
5
U9
1
P
IN1
O
2
IN2
G
3
P1
P2
P3
P4
MH1
MH5
MH6
MH9
MH10
MH3
MH13
MH15
C163
1 2
DOCK_OWNS_PCI
4
74AHC1G08GW_SOT353-5~D5@
JDOCKC
P1
P2
P3
P4
MH1
SHLD1
SHLD2
SHLD5
SHLD6
MH3
MH13
MH15
AMP_1473681~D5@
P5
P6
P7
P8
MH2
SHLD3
SHLD4
SHLD7
SHLD8
MH4
MH14
MH16
DOCK_AD0
DOCK_AD1
DOCK_AD2
DOCK_AD3
DOCK_AD4
DOCK_AD5
DOCK_AD6
DOCK_AD7
DOCK_AD8
DOCK_AD9
DOCK_AD10
DOCK_AD11
DOCK_AD12
DOCK_AD13
DOCK_AD14
DOCK_AD15
DOCK_AD16
DOCK_AD17
DOCK_AD18
DOCK_AD19
DOCK_AD20
DOCK_AD21
DOCK_AD22
DOCK_AD23
DOCK_AD24
DOCK_AD25
DOCK_AD26
DOCK_AD27
DOCK_AD28
DOCK_AD29
DOCK_AD30
DOCK_AD31
NB
PWR_SRC
P5
P6
P7
P8
MH2
MH7
MH8
MH11
MH12
MH4
MH14
MH16
1
+DC_IN
C74
1
2
no power dock
self power dock
+DC_IN
0.1U_0805_50V7M~D5@
1000P_0402_50V7K~D5@
C79
1
2
DOCK_AD[0..31] <35>
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
DOCKING CONNECTOR
LA-2881P
36 62Tuesday, December 13, 2005
1
2.0
of
Page 37
5
4
3
2
1
+3.3V_ALW
1 2
R570 10K_0402_5%~D
1 2
R568 10K_0402_5%~D
1 2
R150 10K_0402_5%~D
1 2
R569 10K_0402_5%~D
+3.3V_RUN
D D
C C
Note: For system debug
pin4 connect to serial port pin3
B B
+5V_SUS
5
T11
4
SYSOPT straps are
sampled at power up.
R444
INSTANT_ON#<38>
NB_MUTE<27,28>
R573
U41
VCC
OUT Y
MC74VHC1G04DFT2G_SC70-5~D@
DOCK_SIO_ALERT#
PCIE_WAKE#
PBAT_ALARM#
SYS_PME#
IMVP6_PROCHOT#
100K_0402_5%~D
PCIE_WAKE#<30,34>
SYS_PME#<30,33,35>
DOCK_SIO_ALERT#<36>
PBAT_PRES#<44>
DOCKED<32,36>
QBUFEN#<35>
DOCK_PWR_EN<36>
BC_INT#<38>
BC_DAT<38>
BC_CLK<38>
INSTANT_ON# INSTANT_ON_R2#
+RTC_CELL
@
12
10K_0402_5%~D
1
NC
2
IN A
3
GND
M_LED_BK<39>
1 2
R753 0_0402_5%~D6@
R779
1 2
100K_0402_5%~D7@
MDC_RST_DIS#<28>
ADAPT_OC<49>
EXPRCRD_STBY#<34>
SIO_GFX_PWR<19>
YPRPB_DET#<19,20>
AC_OFF<43,49>
LOM_CABLE_DETECT<30>
SPDIF_SHDN<20,26>
IMVP6_PROCHOT#<48>
5V_CAL_SIO#<16>
SUB_SHDN_ON_BATT<28>
5V_CAL_SIO2#<16>
DOCK_HP_MUTE#<26>
HP_NB_SENSE<26,27,28>
PBAT_ALARM#<44>
LAN_TPM_EN#<30>
LAN_LOW_PWR<30>
AUDIO_AVDD_ON<26>
BEEP<27>
SC_DET#<34>
ICH_PCIE_WAKE#<23>
ICH_PME#<21>
THERMTRIP_SIO<16>
CBUS_GRST#<33>
CPPE#<34>
FPBACK_EN<19,20>
CB_HWSPND#<33>
CPU_PROCHOT#<7>
TXD0
R572
USB_SIDE_EN#<29>
USB_BACK_EN#<29>
+3.3V_ALW
12
PCIE_WAKE#
SYS_PME#
DOCK_SIO_ALERT#
PBAT_PRES#
DOCKED
QBUFEN#
DOCK_PWR_EN
BC_INT#
BC_DAT
BC_CLK
M_LED_BK
TXD0
MDC_RST_DIS#
ADAPT_OC
EXPRCRD_STBY#
SIO_GFX_PWR
YPRPB_DET#
NB_MUTE
AC_OFF
SPDIF_SHDN
IMVP6_PROCHOT#
5V_CAL_SIO#
SUB_SHDN_ON_BATT
5V_CAL_SIO2#
DOCK_HP_MUTE#
HP_NB_SENSE
PBAT_ALARM#
LAN_TPM_EN#
LAN_LOW_PWR
AUDIO_AVDD_ON
BEEP
SC_DET#
ICH_PCIE_W AKE#
ICH_PME# D_LAD2
THERMTRIP_SIO
CBUS_GRST#
CPPE#
FPBACK_EN
CB_HWSP ND#
CPU_PROCHOT#
GPIOH2
@
BID3
10K_0402_5%~D
BID2
BID1
BID0
USB_SIDE_EN#
USB_BACK_EN#
U39
97
GPIOA[0]
98
GPIOA[1]
99
GPIOA[2]
100
GPIOA[3]
101
GPIOA[4]
102
GPIOA[5]
103
GPIOA[6]
104
GPIOA[7]
24
GPIOH[0]
25
GPIOH[1]
26
GPIOH[4]
27
GPIOH[5]
58
BC_INT#
59
BC_DAT
60
BC_CLK
1
GPIOE[0]/RXD
2
GPIOE[1]/TXD
3
GPIOE[2]/RTS#
4
GPIOE[3]/DSR#
5
GPIOE[4]/CTS#
84
GPIOE[5]/DTR#
83
GPIOE[6]/RI#
6
GPIOE[7]/DCD#
65
GPIOB[0]/INIT#
66
GPIOB[1]/SLCTIN#
67
GPIOC[2]/SCLT
68
GPIOC[3]/PE
69
GPIOC[4]/BUSY
70
GPIOC[5]/ACK#
71
GPIOC[6]/ERROR#
73
GPIOC[7]/ALF#
74
GPIOD[0]/STROBE#
75
GPIOC[1]/PD7
76
GPIOC[0]/PD6
77
GPIOB[7]/PD5
78
GPIOB[6]/PD4
79
GPIOB[5]/PD3
80
GPIOB[4]/PD2
81
GPIOB[3]/PD1
82
GPIOB[2]/PD0
61
GPIOD[1]
62
GPIOD[2]
63
GPIOD[3]/VBUS_DET
28
GPIOD[4]/OCS1_N
29
GPIOD[5]/OCS2_N
30
GPIOD[6]/OCS3_N
31
GPIOD[7]/OCS4_N
32
GPIOH[6]
33
GPIOH[7]
88
GPIOG[0]
89
GPIOG[1]
90
GPIOG[2]
91
GPIOG[3]
92
GPIOG[4]
93
GPIOG[5]
94
GPIOG[6]
95
GPIOG[7]
106
SYSOPT1/GPIOH[2]
107
SYSOPT0/GPIOH[3]
109
GPIOF[7]
110
GPIOF[6]
111
GPIOF[5]
112
GPIOF[4]
113
IRTX
114
IRRX
115
GPIOF[3]/IRMODE/IRRX3B
116
GPIOF[2]/IRTX2
117
GPIOF[1]/IRRX2
118
GPIOF[0]/IRMODE/IRRX3A
ECE5018 A0_VTQFP128~D
BID2 BID1
A A
BID0
BID1
BID2
BID3
R221
1 2
10K_0402_5%~D
R218
R219
R220
10K_0402_5%~D
@
1 2
1 2
1 2
10K_0402_5%~D
10K_0402_5%~D
@
R212 10K_0402_5%~D@
1 2
R211 10K_0402_5%~D
1 2
R210 10K_0402_5%~D@
1 2
R209 10K_0402_5%~D
1 2
5
0
0M00
0
0
0
0
00
01 A00
4
+3.3V_ALW
34
57
85
108
VCC1
VCC1
VCC1
VCC1
ECE5018
GPIO
TEST
CLK
BID0BID3
00
1
0
1
0
11
00
USB
LPC
DLPC
VDDA33
VDDA33
VDDA33
USBDP0
USBDN0
USBDP1
USBDN1
USBDP2
USBDN2
USBDP3
USBDN3
USBDP4
USBDN4
VDDA33PLL
VDDA18PLL
CAP_LDO
TEST_PIN
XTAL1/CLKIN
LFRAME#
LRESET#
PCICLK
CLKRUN#
LDRQ0#
LDRQ1#
SER_IRQ
CLKI (14.318 MHz)
DLFRAME#
DCLK_RUN#
DLDRQ1#
DSER_IRQ
PWRGD
REV
X00
X01
X02
A010011
1
C250
0.1U_0402_16V4Z~D
2
1
2
8
14
20
119
VCC1
VDD18
RBIAS
ATEST
XTAL2
LAD0
LAD1
LAD2
LAD3
DLAD0
DLAD1
DLAD2
DLAD3
OUT65
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
USBP0+
9
USBP0-
10
ECE_USBP1+
13
ECE_USBP1-
12
ECE_USBP2+
15
ECE_USBP2-
16
ECE_USBP3+
19
ECE_USBP3-
18
ECE_USBP4+
21
ECE_USBP4-
22
125
124
120
86
127
TEST_PIN is a No Connect
35
126
123
122
54
52
49
47
42
41
56
37
46
44
39
64
96
55
53
50
48
43
38
45
40
7
105
11
17
23
36
51
72
87
121
128
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
RBIAS
12
ECE5018_XTAL1
ECE5018_XTAL2LOM_CABLE_DETECT
LPC_LAD0
LPC_LAD1
LPC_LAD2
LPC_LAD3
LPC_LFRAME#
PLTRST2#
CLK_PCI_5018
CLKRUN#
LPC_LDRQ0#
LPC_LDRQ1#
IRQ_SERIRQ
CLK_SIO_14M
D_LAD0
D_LAD1
D_LAD3
D_LFRAME#
D_CLKRUN#
D_DLDRQ1#
D_SERIRQ
RUNPWROK
1
1
C536
2
2
4.7U_0805_10V4Z~D
3
USBP0+ <23>
USBP0- <23>
ECE_USBP1+ <34>
ECE_USBP1- <34>
ECE_USBP2+ <34>
ECE_USBP2- <34>
ECE_USBP3+ <34>
ECE_USBP3- <34>
ECE_USBP4+ <28>
ECE_USBP4- <28>
Route RBIAS and its
R235
return to pin 128 very
short.
12K_0402_1%~D
R249 0_0402_5%~D
LPC_LAD0 <22,30,38>
LPC_LAD1 <22,30,38>
LPC_LAD2 <22,30,38>
LPC_LAD3 <22,30,38>
1
C237
C241
2
4.7U_0805_10V4Z~D
0.1U_0402_16V4Z~D
1
C522
0.1U_0402_16V4Z~D
2
C213
0.1U_0402_16V4Z~D
+SIO_VDDA
<---Mini Card
<---Smart Card
<---Express Card
<---Blue Tooth
+REG_EN
1 2
LPC_LFRAME# <22,30,38>
PLTRST2# <21,34,38>
CLK_PCI_5018 <6>
CLKRUN# <23,31,33,38>
LPC_LDRQ0# <22>
LPC_LDRQ1# <22>
IRQ_SERIRQ <23,30,33,38>
CLK_SIO_14M <6>
D_LAD0 <36>
D_LAD1 <36>
D_LAD2 <36>
D_LAD3 <36>
D_LFRAME# <36>
D_CLKRUN# <36>
D_DLDRQ1# <36>
D_SERIRQ <36>
RUNPW ROK <19,38,40,48>
D24
1 2
C253
4.7U_0805_10V4Z~D
21
RB751V_SOD323~D
R780 0_0402_5%~D@
1
2
1
C226
2
0.1U_0402_16V4Z~D
+3.3V_ALW
12
R240
10K_0402_5%~D
1
C222
2
0.1U_0402_16V4Z~D
1
C537
0.1U_0402_16V4Z~D
2
1
2
1
C231
2
0.1U_0402_16V4Z~D
12
R574
1 2
1M_0402_5%~D
WLAN_RADIO_DIS# <34>
2
1
2
+3.3V_ALW
L11
BLM18PG181SN1_0603~D
1 2
C245
10U_0805_6.3V6M~D
C524
1 2
22P_0402_50V8J~D
Y3
24MHZ_20PF_1BX24000BK1A~D
C523
1 2
22P_0402_50V8J~D
DELL CONFIDENTIAL/PROPRIETARY
Title
Size Document Number Rev
Date: Sheet
C214
0.1U_0402_16V4Z~D
D_CLKRUN#
D_DLDRQ1#
D_SERIRQ
R610 100K_0402_5%~D
R608 100K_0402_5%~D
R609 100K_0402_5%~D
Place closely pin 56
Place closely pin 64
Compal Electronics, Inc.
SUPPER IO ECE5018
LA-2881P
1 2
1 2
1 2
CLK_PCI_5018
22_0402_5%~D @
22P_0402_50V8J~D@
CLK_SIO_14M
22_0402_5%~D @
22P_0402_50V8J~D@
+3.3V_RUN
12
R613
1
C558
2
12
R611
1
C557
2
37 62Tuesday, December 13, 2005
1
2.0
of
Page 38
5
R227
KSO17
KSO16
KSO15
KSO14
KSO13
KSO12
KSO11
KSO10
KSO9
KSO8
KSO7
KSO6
KSO5
KSO4
KSO3
KSO2
KSO1
KSO0
KSI7
KSI6
KSI5
KSI4
KSI3
KSI2
KSI1
KSI0
BC_CLK
BC_DAT
BC_INT#
KB_XOSEL
12
10K_0402_5%~D
+RTC_CELL
0.1U_0402_16V4Z~D
U40
12
13
14
15
16
17
18
19
20
23
24
25
27
28
29
30
31
32
33
34
35
36
37
38
39
40
92
50
75
76
77
78
79
80
81
82
57
58
59
60
61
62
63
64
56
102
105
107
103
106
108
109
110
87
86
85
122
124
123
1 2
KSO17/GPIOA1
KSO16/GPIOA0
GPIO5/KSO15
GPIO4/KSO14
KSO13/GPIO18
KSO12/OUT8
KSO11/GPIOC7
KSO10/GPIOC6
KSO9/GPIOC5
KSO8/GPIOC4
KSO7/GPIO3
KSO6/GPIO2
KSO5/GPIO1
KSO4/GPIO0
KSO3/GPIOC3
KSO2/GPIOC2
KSO1/GPIOC1
KSO0/GPIOC0
KSI7/GPIO19
KSI6/GPIO17
KSI5/GPIO10
KSI4/GPIO9
KSI3/GPIO8
KSI2/GPIO7
KSI1/GPIO6
KSI0/SGPIO30
SGPIO34/A20M
OUT5/KBRST
GPIO94/IMCLK
GPIO95/IMDAT
KCLK
KDAT
EMCLK
EMDAT
GPIO20/PS2CLK/8051RX
GPIO21/PS2DAT/8051TX
LRESET#
PCICLK
LFRAME#
LAD0
LAD1
LAD2
LAD3
CLKRUN#
SER_IRQ
HSTCLK
HSTDATAIN
HSTDATAOUT
FLCLK
FLDATAIN
FLDATAOUT
FLCS0
FLCS1
BC_CLK
BC_DAT
BC_INT
XTAL1
XTAL2
XOSEL
+5V_RUN
1 2
R161 4.7K_0402_5%~D
1 2
R162 4.7K_0402_5%~D
1 2
R167 4.7K_0402_5%~D
1 2
R168 4.7K_0402_5%~D
D D
CLK_KBD
DAT_KBD
CLK_DOCK
DAT_DOCK
Place closely pin 58
SIO_A20GATE<22>
SIO_THRM#<23>
CLK_TP_SIO<39>
DAT_TP_SIO<39>
CLK_KBD<36>
DAT_KBD<36>
CLK_DOCK<36>
DAT_DOCK<36>
DEBUG_ENABLE#
CLK_PCI_5004<6>
LPC_LFRAME#<22,30,37>
LPC_LAD0<22,30,37>
LPC_LAD1<22,30,37>
LPC_LAD2<22,30,37>
LPC_LAD3<22,30,37>
CLKRUN#<23,31,33,37>
IRQ_SERIRQ<23,30,33,37>
ICH_EC_SPI_CLK<23>
ICH_EC_SPI_DIN<23>
ICH_EC_SPI_DO<23>
SIO_PWRBTN#<23>
BC_DAT<37>
BC_INT#<37>
C513
1 2
Y4
1 2
C521
KSO[0..17]<39>
PLTRST2#<21,34,37>
BC_CLK<37>
KSI[0..7]<39>
R571
1 4
2 3
LID_CL# <39>
SIO_A20GATE
SIO_THRM#
CLK_TP_SIO
DAT_TP_SIO
CLK_KBD
DAT_KBD
CLK_DOCK
DAT_DOCK
8051RX
8051TX
PLTRST2#
CLK_PCI_5004
LPC_LFRAME#
LPC_LAD0
LPC_LAD1
LPC_LAD2
LPC_LAD3
CLKRUN#
IRQ_SERIRQ
ICH_EC_SPI_CLK
ICH_EC_SPI_DIN
ICH_EC_SPI_DO
EC_FLASH_SPI_CLK
EC_FLASH_SPI_DO
SIO_PWRBTN#
32K_XTAL1
32K_XTAL2
0_0402_5%~D
12
CLK_PCI_5004
C C
8051RX<34>
8051TX<34>
+3.3V_ALW
JDEBG1
5
5
4
4
3
3
2
1 2
2
R268 0_0402_5%~D
1
1
MOLEX_53398-0571~D@
B B
32.768K_12.5PF_Q13MC30610003~D
+3.3V_ALW
12
R606
A A
LID_CL_SIO# LID_CL#
1
C546
2
10K_0402_5%~D
R169
100K_0402_5%~D
0.047U_0402_10V7K~D
22_0402_5%~D@
12
R614
22P_0402_50V8J~D@
C556
1
2
+3.3V_ALW
10K_0402_5%~D
12
12
R153
22P_0402_50V8J~D
22P_0402_50V8J~D
R607
1 2
10_0402_5%~D
5
R193
0_0402_5%~D
C240
BLM18AG121SN1D_0603~D
4
1
2
121
VCC0
Keyboard and Mouse Interface
LPC Interface
Host/8051
BC Bus
VSS
VSS
VSS
AGND
26
51
74
125
12
L13
C219
4
+3.3V_ALW
21
VCC1
VSS
VSS
88
113
4.7U_0805_10V4Z~D
1
2
44
65
VCC1
VCC1
C227
83
116
VCC1
VCC1
PWR SW
VR_CAP
22
0.1U_0402_16V4Z~D
10U_0805_6.3V6M~D
C243
C215
1
1
2
SGPIO45/MSDATA/SPDOUT2
SGPIO44/MSCLK/SPCLK2
SGPIO31/TIN1/SPCLK1
SYSOPT0/SGPIO32/LPC_TX
SYSOPT1/SGPIO33/LPC_RX
VSS_PLL
101
C242
0.1U_0402_16V4Z~D
VR_CAP
1
2
2
ALWON
POWER_ SW_IN2#
POWER_ SW_IN1#
POWER_ SW_IN0#
ACAV_IN
BGPO0
AB1B_CLK
AB1B_DATA
AB1A_CLK
AB1A_DATA
GPIO11/AB2A_DATA
GPIO12/AB2A_CLK
GPIO13/AB2B_DATA
GPIO14/AB2B_CLK
GPIO87/AB1C_DATA
GPIO86/AB1C_CLK
GPIO85/AB1D_DATA
GPIO84/AB1D_CLK
GPIO93/AB1F_DATA
GPIO92/AB1F_CLK
GPIO91/AB1E_DATA
GPIO90/AB1E_CLK
GPIO82/FAN_TACH3
GPIO16/FAN_TACH2
GPIO15/FAN_TACH1
OUT2/PWM3
OUT9/PWM2
OUT11/PWM1
OUT10/PWM0
nEC_SCI/SPDIN2
SGPIO46/SPDIN1
SGPIO47/SPDOUT1
SGPIO40
SGPIO41
SGPIO42
SGPIO43
SGPIO35
SGPIO36 (SFPI_EN)
SGPIO37
GPIO96/TOUT1
OUT7/nSMI
nPWR_LED
nBAT_LED
nFWP
GPIOA3/WINDMON
GPIO83/32KHZ_OUT
PWRGD
nRESET_OUT/OUT6
TEST_PIN
VCC_PLL
MEC5004_D_VTQFP128~D
104
BLM18AG121SN1D_0603~D
12
1 2
3
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
L12
C216
C221
1
1
2
2
120
119
126
127
128
118
8
7
6
5
93
94
95
96
111
112
9
10
97
98
99
100
43
42
41
48
47
46
45
66
55
54
69
68
67
70
71
91
90
89
4
1
2
3
52
11
115
114
84
73
117
49
53
72
+RTC_CELL
+RTC_CELL
100K_0402_5%~D
12
R192
12
R781
100K_0402_5%~D6@
ALWON
INSTANT_ON_R1#
POWER_SW_IN#
ACAV_IN
PBAT_SMBCLK
PBAT_SMBDAT
DOCK_SMB_CLK
DOCK_SMB_DAT
VAUX_EN
SUS_ON
RUN_ON
ITP_DBRESET#
SBAT_SMBDAT
SBAT_SMBCLK
DAT_SMB
CLK_SMB
SIO_SLP_S5#
SIO_SLP_S3#
SIO_RCIN#
SIO_EXT_WAKE#
FAN2_TACH
FAN1_TACH
BREATH_LED
SIO_EXT_SCI#
RUN_ON_D
PS_ID
VGA_IDENTIFY
LID_CL_SIO#
DEBUG_ENABLE#
HOST_DEBUG_TX
HOST_DEBUG_RX
CAP_LED#
SRL_LED#
NUM_LED#
SPI_CS#
DOCK_SMB_INT#
SFPI_EN
PS_ID_DISABLE#
ATF_INT#
SIO_EXT_SMI#EC_FLASH_SPI_DIN
BAT2_ORG_LED#
BAT1_GRN_LED#
FWP#
BIA_PWM
RUNPWROK
RESET_OUT#
+3.3V_ALW
ALWON
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
1 2
RB751V_SOD323~D@
3
ALWON <45>
ACAV_IN <16,19,49>
PBAT_SMBCLK <41,44,49>
PBAT_SMBDAT <41,44,49>
DOCK_SMB_CLK <36>
DOCK_SMB_DAT <36>
VAUX_EN <40,45>
SUS_ON <40,45>
RUN_ON <19,40,45,46,47>
ITP_DBRESET# <7,23>
SBAT_SMBDAT <19,20>
SBAT_SMBCLK <19,20>
DAT_SMB <16>
CLK_SMB <16>
SIO_SLP_S5# <23>
SIO_SLP_S3# <23>
SIO_RCIN# <22>
SIO_EXT_WAKE# <23>
FAN2_TACH <16>
FAN1_TACH <16>
BREATH_LED <39>
SIO_EXT_SCI# <23>
T12
PS_ID <43>
CAP_LED# <39>
SRL_LED# <39>
NUM_LED# <39>
SPI_CS# <23>
DOCK_SMB_INT# <36>
PS_ID_DISABLE# <43>
ATF_INT# <16>
SIO_EXT_SMI# <23>
BAT2_ORG_LED# <39>
BAT1_GRN_LED# <39>
BIA_PWM <12,19,20>
RUNPW ROK <19,37,40,48>
RESET_OUT# <40>
R782
0_0402_5%~D
D23
21
HOST_DEBUG_TX <34>
HOST_DEBUG_RX <34>
R776
1 2
10K_0402_5%~D@
1 2
R754 0_0402_5%~D7@
1 = Discrete Gfx
0 = UMA
VGA_IDENTIFY
@
10K_0402_5%~D
12
12
R603
R604
Bat2 = Orange LED
Bat1 = Green LED
100K_0402_5%~D@
12
R775
B
2
@
10K_0402_5%~D
+3.3V_ALW
12
E
3
Q110
C
MMBT3906_SOT23~D@
1
1 2
100K_0402_5%~D@
+3.3V_ALW
R774
10K_0402_5%~D@
1
2
R778
R154
R156
3
2
1
C712
12
12
JDEBG2
3
2
1
4.7U_0603_6.3V6M~D@
2
DOCK_SMB_DAT
DOCK_SMB_CLK
DOCK_SMB_INT#
INSTANT_ON#<37>
INSTANT_ON#
10K_0402_5%~D3@
10K_0402_5%~D1@
SPI_CS#
EC_FLASH_SPI_DIN
1.5mm SMT~D@
13
D
2
G
S
2
+5V_ALW +3.3V_ALW
R262
47_0402_5%~D
12
12
12
+RTC_CELL
12
R194
1
2
+RTC_CELL
12
R195
1
2
R256
12
100K_0402_5%~D
R179
1 2
10K_0402_5%~D
C228
1U_0603_10V4Z~D
100K_0402_5%~D
R207
1 2
10K_0402_5%~D
C246
1U_0603_10V4Z~D
10K_0402_5%~D
12
U18
1
2
3
4
MX25L8005MC-15G_SOP8~D@
Flash ROM
150 MIL SO8
U17
1
2
3
4
MX25L8005M2C-15G_SO8~D
CS#
SO
WP#
GND
S#
Q
W#
VSS
R208 8.2K_0402_5%~D
R196 8.2K_0402_5%~D
R214 100K_0402_5%~D
INSTANT_ON# INSTANT_ON_SW#
POWER_SW_IN# POWER_SW#
200 MIL SO8
Note:
Pop R601, depop R600 for development
Depop R601, pop R600 for production
+3.3V_ALW
12
R601
FWP#
12
R600
R777
1 2
0_0402_5%~D@
Q111
2N7002_SOT23~D@
VR_CAP
Low = write protected
Flash write protect bottom 4K
of internal bo otblock flash
DELL CONFIDENTIAL/PROPRIETARY
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
LA-2881P
DAT_SMB
CLK_SMB
PBAT_SMBDAT
PBAT_SMBCLK
SBAT_SMBDAT
SBAT_SMBCLK
ATF_INT#
VCC
HOLD#
SCLK
SI
VCC
HOLD#
C
D
100K_0402_5%~D@
100K_0402_5%~D
1
1 2
R182 2.2K_0402_5%~D
1 2
R177 2.2K_0402_5%~D
1 2
R592 2.2K_0402_5%~D
1 2
R599 2.2K_0402_5%~D
1 2
R216 2.2K_0402_5%~D
1 2
R217 2.2K_0402_5%~D
R616 10K_0402_5%~D
INSTANT_ON_SW# <39>
POWER_SW# <16,39>
+3.3V_SUS+3.3V_SUS
8
7
6
5
8
7
6
5
C258
1 2
0.1U_0402_16V4Z~D
12
R263
10K_0402_5%~D
EC_FLASH_SPI_CLK
EC_FLASH_SPI_DO
1=Flash Recovery Enabled
0=Flash Recov e r y Disabled
SFPI_EN
EMC5004
38 62Tuesday, December 13, 2005
1
12
+3.3V_SUS
+3.3V_ALW
12
R555
12
R550
of
1K_0402_5%~D@
1K_0402_5%~D
2.0
Page 39
5
+3.3V_ALW
OUT
IN
2
GND
1
3
DTA114YKA
R126
D D
BREATH_LED<38>
BT_ACTIVE<28,34>
C C
LED_WLAN#<34>
1 2
10K_0402_5%~D
R127
1 2
10K_0402_5%~D
+3.3V_RUN
47K
10K
2
BREATH_LED_B
BT_MPCI_ACTIVE
Q32
DTA114YKA_SOT23~D
1 3
R_LED_WLAN_OUT LED_WLAN_OUT
R121
1 2
Z3901
C
2
B
E
3 1
R_BT_MPCI_ACT_R
C
2
B
E
3 1
R120
150_0402_5%~D
56_0402_5%~D
Q31
PMBT3904_SOT23~D
R_BREATH_LED
Q30
PMBT3904_SOT23~D
12
DAT_TP_SIO<38>
CLK_TP_SIO<38>
+5V_RUN
47K
10K
2
4
+5V_RUN
4.7K_0402_5%~D
4.7K_0402_5%~D
12
12
R123
R129
L9
DAT_TP_SIO TP_DATA
CLK_TP_SIO
Q109
DTA114YKA_SOT23~D
1 3
R_BT_MPCI_ACT
SATA_ACT#<22>
C154
10P_0402_50V8J~D
1
2
10K
2
BLM18AG601SN1D_0603~D
1 2
1 2
L10
10P_0402_50V8J~D
BLM18AG601SN1D_0603~D
C167
1
2
+3.3V_RUN
47K
Q33
DTA114YKA_SOT23~D
1 3
HDD_LED ACTLED
R122
100_0402_5%~D
10P_0402_50V8J~D
C161
1
2
12
3
TP_CLK
10P_0402_50V8J~D
C165
1
2
HDD_LED <36>
Touch PAD and Multi Media
KSO17
M_LED_BK<37>
LID_CL#<38>
12
12
+5V_ALW
R1430_0402_5%~D
R1410_0402_5%~D
2
LID_CL#
TP_CLK
TP_DATA
C155
1
JTP
112
334
556
778
9910
11
12
11
13
14
13
151516
17
17
18
19
19
0.1U_0402_16V4Z~D
1
2
20
JST_BM20B-SRDS-G-TFC
BAT2_ORG_LED#<38>
BAT1_GRN_LED#<38>
CAP_LED#<38>
NUM_LED#<38>
SRL_LED#<38>
POWER_SW#<16,38>
INSTANT_ON_SW#<38>
LED_TP_B
2
R137 0_0402_5%~D
4
R136 0_0402_5%~D
6
R135 0_0402_5%~D
8
R134 0_0402_5%~D
10
R132 0_0402_5%~D
12
R128 0_0402_5%~D
14
R124 0_0402_5%~D
16
18
20
C158
1
2
R_BT_MPCI_ACT
BAT2_ORG_LED#
BAT1_GRN_LED#
R_BREATH_LED
ACTLED
CAP_LED#
NUM_LED#
SRL_LED#
LED_WLAN_OUT
POWER_SW#
INSTANT_ON_SW#
+3.3V_ALW
1 2
1 2
1 2
1 2
1 2
1 2
1 2
0.1U_0402_16V4Z~D
LED_TP_B <41>
JSW
15
GND2
14
GND1
13
13
12
12
11
11
10
10
9
9
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
MOLEX_53398-1371~D
+5V_RUN
KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI[0..7]<38>
B B
KSO[0..17]<38>
A A
KSI7
KSI6
KSI5
KSI4
KSI3
KSI2
KSI1
KSI0
KSO17
KSO16
KSO15
KSO14
KSO13
KSO12
KSO11
KSO10
KSO9
KSO8
KSO7
KSO6
KSO5
KSO4
KSO3
KSO2
KSO1
KSO0
KSI7
KSI6
KSI4
KSI2
KSI5
KSI1
KSI3
KSI0
KSO5
KSO4
KSO7
KSO6
KSO8
KSO3
KSO1
KSO2
KSO0
KSO12
KSO16
KSO15
KSO13
KSO14
KSO9
KSO11
KSO10
@
100P_0402_50V8J~D
C65
C63
1
2
@
@
100P_0402_50V8J~D
100P_0402_50V8J~D
C62
1
1
2
2
@
@
100P_0402_50V8J~D
100P_0402_50V8J~D
C115
C60
C112
1
1
2
2
@
@
100P_0402_50V8J~D
100P_0402_50V8J~D
C107
1
1
2
2
@
@
100P_0402_50V8J~D
100P_0402_50V8J~D
C100
C101
1
1
2
2
@
@
100P_0402_50V8J~D
100P_0402_50V8J~D
C92
C95
C97
1
1
2
2
@
@
100P_0402_50V8J~D
1
2
@
100P_0402_50V8J~D
C90
C88
1
2
@
100P_0402_50V8J~D
100P_0402_50V8J~D
C86
1
1
2
2
@
@
100P_0402_50V8J~D
100P_0402_50V8J~D
C83
C84
C80
1
1
2
2
@
@
100P_0402_50V8J~D
100P_0402_50V8J~D
C78
C75
1
1
2
2
@
@
100P_0402_50V8J~D
100P_0402_50V8J~D
C72
1
1
2
2
@
@
100P_0402_50V8J~D
C71
1
2
@
100P_0402_50V8J~D
100P_0402_50V8J~D
C68
C56
C66
1
1
2
2
@
100P_0402_50V8J~D
1
2
JKYBD
25
24
23
22
21
20
19
18
17
16
15
14
13
27
12
26
11
10
9
8
7
6
5
4
3
2
1
HRS_FH28D-25SB-1SH~D
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
LED/INT KB/Touch Pad and Swithch CONN.
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
LA-2881P
39 62Tuesday, December 13, 2005
1
2.0
of
Page 40
5
+5V_SUS
Run Planes Enable
RUN_ENABLE<45>
+15V_SUS
D D
+5V_ALW
100K_0402_5%~D
12
R11
RUN_ON_5V#
13
D
RUN_ON<19,38,45,46,47>
2
G
S
22.2uA leakage current at S3
C C
+5V_RUN
200K_0402_5%~D@
R307
B
2
+5V_SUS
E
3
1
Q54
MMBT3906_SOT23~D@
C
R306
4.7K_0402_5%~D@
13.7uA leakage current at S3
+3.3V_SUS
+3.3V_RUN
R302
200K_0402_5%~D@
B B
A A
B
2
2.5V_RUN_PWRGD<16>
1.5V_RUN_PWRGD<46>
1.05V_RUN_PWRGD<46,48>
0.9V_DDR_PWRGD<47>
E
3
Q53
MMBT3906_SOT23~D@
C
1
4.7K_0402_5%~D@
5V_3V_RUN_PW RGD
5
R301
100K_0402_5%~D
12
R74
RUN_ENABLE
C81
13
D
2
G
S
Q21
2N7002_SOT23~D
Q20
2N7002_SOT23~D
1
2
Depoplated following
BITS issue ID : CR29440
C
Q56
2
B
PMBT3904_SOT23~D
@
E
3 1
C
Q57
2
B
PMBT3904_SOT23~D
@
E
3 1
20K_0402_5%~D
R311
1 2
R310
1 2
0_0402_5%~D
0_0402_5%~D
SUSPWROK_1P8V
R312
R313
1 2
0_0402_5%~D
0_0402_5%~D
SUSPWROK_1P8V<47>
R583
1 2
4700P_0402_25V7K~D
1
200K_0402_5%~D
+3.3V_RUN
C529
R159
C220
D26
MMBD4148-7-F_SOT23-3~D
12
1
2
Q89
SI4810DY-T1-E3_SO8~D
8
7
5
+3.3V_SRC
8
7
5
3
2
R785
VAUX_EN<38,45>
+3.3V_SUS
8
P
A1Y
0.1U_0402_16V4Z~D
G
4
10K_0402_5%~D
1 2
2
B
0.1U_0402_16V4Z~D
2
1
4
1
2
36
4.7U_0805_10V4Z~D
C502
4
Q41
SI4810DY-T1-E3_SO8~D
1
2
36
4
+3.3V_RUN Source
470P_0402_50V7K~D
C85
1
2
VAUX_EN
C526
1 2
0.1U_0402_16V4Z~D
U38A
7
74LVC3G14DC_VSSOP8~D
+3.3V_ALW
100K_0402_5%~D
R148
1 2
C
Q39
PMBT3904_SOT23~D
E
3 1
4
+5V_RUN
12
1
2
4.7U_0805_10V4Z~D
1
C223
2
+PWR_SRC
12
R149
100K_0402_5%~D
13
D
2
G
S
+3.3V_SUS
A6Y
RUN_ON<19,38,45,46,47>
+3.3V_SUS
8
U38C
P
A3Y
G
4
74LVC3G14DC_VSSOP8~D
+5V_RUN Source
R558
20K_0402_5%~D
+3.3V_RUN
Q38
2N7002_SOT23~D
8
U38B
P
G
74LVC3G14DC_VSSOP8~D
4
RUN_ON
5
12
R170
20K_0402_5%~D
2
0_0402_5%~D
1 2
SUS_ON<38,45>
RUN_ON_5V#
SUSPWROK_5V<45,47>
R151
R744
3
+VCC_CORE +0.9V_DDR_VTT +3.3V_RUN
12
R10
30_0805_5%
@
Z4005
Q8
13
D
2N7002_SOT23~D@
2
G
S
SUSPWROK_5V
+PWR_SRC
12
R147
100K_0402_5%~D
ENAB_3VLAN
13
D
Q37
2N7002_SOT23~D
2
G
200K_0402_5%~D
S
12
+3.3V_SUS
0.1U_0402_16V4Z~D
14
1
P
IN1
OUT
2
IN2
G
7
74VHC08MTCX_NL_TSSOP14~D
+3.3V_SUS
14
10
P
SUS_ON
IN1
9
IN2
G
7
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
R146
C538
1 2
U42A
3
4
5
U42C
SUSPWROK
8
OUT
74VHC08MTCX_NL_TSSOP14~D
3
12
Z4006
Q99
13
D
2
G
S
+5V_ALW
12
R101
100K_0402_5%~D@
SUSPWROK_5V#
13
D
Q24
2
2N7002_SOT23~D@
G
S
ENAB_3VLAN <30>
470K_0402_5%~D
12
+3.3V_SUS
14
U42B
P
IN1
IN2
RUNPWROK
6
OUT
G
74VHC08MTCX_NL_TSSOP14~D
7
R704
30_0805_5%
@
2N7002_SOT23~D@
SUSPWROK <16,23>
12
R708
30_0805_5%
@
Z4007
Q101
13
D
2N7002_SOT23~D@
2
G
S
+1.8V_SUS
12
R102
22_0805_5%~D@
Z4018
13
D
Q26
2
2N7002_SOT23~D@
G
S
+3.3V_SUS Source
IMVP_PWRGD<23,48>
RUNPWROK <19,37,38,48>
RESET_OUT#<38>
2
+1.5V_RUN +1.05V_VCCP +GFX_PWR_SRC
12
R12
30_0805_5%
@
Z4008
Q9
13
D
2N7002_SOT23~D@
2
G
S
SUS_ON_5V#
12
R19
30_0805_5%
@
Z4009
Q11
13
D
2N7002_SOT23~D@
2
G
S
+1.8V_SUS +5V_SUS +3.3V_SUS
12
13
D
2
G
S
12
Z4010
13
D
2
G
S
R47
30_0805_5%
Q106
2N7002_SOT23~D
Maximum Rds on value for Q41, Q89 and Q90 should 15 mohm
+15V_SUS
12
13
D
2
G
S
ICH_PWRGD<10,23>
U42D
ICH_PWRGD
11
74VHC08MTCX_NL_TSSOP14~D
SUS_ON<38,45>
SUS_ON
2
2N7002_SOT23~D
IMVP_PWRGD
RESET_OUT#
+5V_ALW
G
Q40
12
R174
100K_0402_5%~D
SUS_ON_5V#
13
D
S
+3.3V_SUS
14
13
IN1
12
IN2
7
P
OUT
G
DELL CONFIDENTIAL/PROPRIETARY
Title
Size Document Number Rev
LA-2881P
2
Date: Sheet
1
R619
150_0805_5%~D
Q94
2N7002_SOT23~D
2
G
R178
100K_0402_5%~D
SUS_ENABLE
Q47
2N7002_SOT23~D
2
G
+2.5V_RUN
12
Z4011
13
2
G
12
R745
30_0805_5%
@
13
D
Q107
2N7002_SOT23~D
S
@
+3.3V_SRC
+3.3V_SUS
12
R215
100K_0402_5%~D
13
D
Q48
2N7002_SOT23~D
S
R621
30_0805_5%
@
Q95
D
2N7002_SOT23~D@
S
SI4810DY-T1-E3_SO8~D
8
7
5
ICH_PWRGD#
2
G
Q90
4
C503
1
2
+5V_RUN
12
Z4012
Q112
13
D
2
G
S
12
R746
30_0805_5%
@
13
D
Q108
2N7002_SOT23~D
S
@
1
2
36
C501
0.1U_0402_16V4Z~D
ICH_PWRGD# <16>
R786
30_0805_5%
@
2N7002_SOT23~D@
+3.3V_SUS
4.7U_0805_10V4Z~D
1
2
Compal Electronics, Inc.
POWER CONTROL AND SEQUENCE
40 62Tuesday, December 13, 2005
1
of
2.0
Page 41
5
R8
2
G
2
G
2
G
+5V_RUN
2
G
2
G
2
G
+5V_RUN
10K_0402_5%~D2@
1 2
LED#R0
13
D
Q6
S
R5
10K_0402_5%~D2@
1 2
LED#R1
13
D
Q4
S
R2
10K_0402_5%~D2@
1 2
LED#R2
13
D
Q2
S
R430
10K_0402_5%~D2@
1 2
LED#R3
13
D
Q71
S
R432
10K_0402_5%~D2@
1 2
LED#R4
13
D
Q72
S
R423
10K_0402_5%~D2@
1 2
LED#R5
13
D
Q69
S
R_FANLED_R
R_FANLED_G
R_FANLED_B
C354
2N7002_SOT23~D2@
2N7002_SOT23~D2@
2N7002_SOT23~D2@
L_FANLED_R
L_FANLED_G
L_FANLED_B
C684
1
2
2N7002_SOT23~D2@
2N7002_SOT23~D2@
2N7002_SOT23~D2@
C353
1U_0603_10V4Z~D2@
1
2
L_FAN_R
13
D
2
G
S
L_FAN_G
13
D
2
G
S
L_FAN_B
13
D
2
G
S
100P_0402_50V8K~D@
C6
C1
1U_0603_10V4Z~D2@
1
1
2
2
R_FAN_R R_FANLED_R
13
D
2
G
S
R_FAN_G
13
D
2
G
S
13
D
2
G
S
100P_0402_50V8K~D@
100P_0402_50V8K~D@
C347
C345
1
1
2
2
LEFT FAN
+5V_RUN
D D
+5V_RUN
+5V_RUN
C C
RIGHT FAN
+5V_RUN
B B
+5V_RUN
+5V_RUN
A A
LED_L_FAN_R#
1 2
R9
10K_0402_5%~D2@
LED_L_FAN_G#
1 2
R6
10K_0402_5%~D2@
LED_L_FAN_B#
1 2
R3
10K_0402_5%~D2@
LED_R_FAN_R#
1 2
R431
10K_0402_5%~D2@
LED_R_FAN_G#
1 2
R433
10K_0402_5%~D2@
LED_R_FAN_B#
1 2
R424
10K_0402_5%~D2@
+5V_RUN
+5V_RUN
+5V_RUN
+5V_RUN
+5V_RUN
+5V_RUN
1 2
Q5
BSS138_SOT23~D
2@
1 2
Q3
BSS138_SOT23~D
2@
1 2
Q1
BSS138_SOT23~D
2@
100P_0402_50V8K~D@
100P_0402_50V8K~D@
C9
1
2
1 2
Q73
BSS138_SOT23~D
2@
1 2
Q74
BSS138_SOT23~D
2@
1 2
Q70
BSS138_SOT23~D
2@
5
4
3
2
1
100P_0402_50V8K~D@
1
2
R7
0_0805_5%~D2@
R4
0_0805_5%~D2@
R1
0_0805_5%~D2@
5
4
3
2
1
R442
0_0805_5%~D2@
R443
0_0805_5%~D2@
R428
0_0805_5%~D2@
JRFLED
5
4
3
2
1
JST_BM05B-SRSS-TB~D2@
JLFLED
5
4
3
2
1
JST_BM05B-SRSS-TB~D2@
7
6
7
7
6
6
7
6
L_FANLED_R
L_FANLED_G
L_FANLED_B
R_FANLED_G
R_FANLED_BR_FAN_B
4
SPKR LED
+5V_RUN
+5V_RUN
+5V_RUN
PANEL LED
+5V_RUN
+5V_RUN
+5V_RUN
LED_SPKR_R#
1 2
R111
10K_0402_5%~D2@
LED_SPKR_G#
1 2
R100
10K_0402_5%~D2@
LED_SPKR_B#
1 2
R139
10K_0402_5%~D2@
LED_PANEL_R#
1 2
R377
10K_0402_5%~D2@
LED_PANEL_G#
1 2
R389
10K_0402_5%~D2@
LED_PANEL_B#
1 2
R391
10K_0402_5%~D2@
+5V_RUN
+5V_RUN
+5V_RUN
+5V_RUN
+5V_RUN
+5V_RUN
2
G
2
G
2
G
2
G
2
G
2
G
+5V_RUN
LED#9
13
D
S
LED#10
13
D
S
LED#11
13
D
S
R110
10K_0402_5%~D2@
1 2
LED#6
13
D
Q28
S
R99
10K_0402_5%~D2@
1 2
LED#7
13
D
Q25
S
R138
10K_0402_5%~D2@
1 2
LED#8
13
D
Q35
S
SPKRLED_R
SPKRLED_G
SPKRLED_B
C160
R378
10K_0402_5%~D2@
1 2
Q60
2N7002_SOT23~D2@
R390
10K_0402_5%~D2@
1 2
Q62
2N7002_SOT23~D2@
R392
10K_0402_5%~D2@
1 2
Q63
2N7002_SOT23~D2@
+5V_RUN
3
Q29
BSS138_SOT23~D
2@
Q27
BSS138_SOT23~D
2@
Q34
BSS138_SOT23~D
2@
100P_0402_50V8K~D@
C152
1
2
R225
1 2
0_0805_5%~D2@
R173
1 2
0_0805_5%~D2@
R226
1 2
0_0805_5%~D2@
0_0402_5%~D@
1 2
100P_0402_50V8K~D@
C225
1
1
2
2
R119
1 2
0_0805_5%~D2@
R109
1 2
0_0805_5%~D2@
R130
1 2
0_0805_5%~D2@
JSPLED
5
5
4
4
7
3
3
2
2
6
1
1
JST_BM05B-SRSS-TB~D2@
R365
100P_0402_50V8K~D@
C247
1
2
SPKRLED_R
SPKRLED_G
SPKRLED_B
7
6
PANEL_LED_R
PANEL_LED_GPANEL_G
PANEL_LED_B
LED Fault
Detection
100P_0402_50V8K~D@
12
R367
TP LED
+5V_RUN
JPALED
5
5
4
7
4
7
3
3
2
6
2
6
1
1
JST_BM05B-SRSS-TB~D2@
0_0603_5%~D2@
SPKR_R
13
D
2
G
2
G
2
G
100P_0402_50V8K~D@
C153
1
2
2
G
2
G
2
G
PANEL_LED_R
PANEL_LED_G
PANEL_LED_B
C212
1
2
S
SPKR_G
13
D
S
SPKR_B
13
D
S
100P_0402_50V8K~D@
1
2
PANEL_R
13
D
Q49
BSS138_SOT23~D
S
2@
13
D
Q46
BSS138_SOT23~D
S
2@
PANEL_B
13
D
Q50
BSS138_SOT23~D
S
2@
1U_0603_10V4Z~D2@
C248
2N7002_SOT23~D2@
2N7002_SOT23~D2@
2N7002_SOT23~D2@
C156
1U_0603_10V4Z~D2@
1
2
LED_FAULT_DET<23>
2
LED_TP_B#
1 2
R422
10K_0402_5%~D2@
PBAT_SMBDAT<38,44,49>
PBAT_SMBCLK<38,44,49>
+5V_RUN
1
R418
10K_0402_5%~D2@
1 2
LED#R12
13
D
Q68
2
G
S
2N7002_SOT23~D2@
+3.3V_RUN
12
R398
R395
10K_0402_5%~D
@
@
LED_L_FAN_R#
LED_R_FAN_R#
LED_SPKR_R#
LED_L_FAN_G#
LED_R_FAN_G#
2
G
12
10K_0402_5%~D
TP_B
13
D
Q64
BSS138_SOT23~D
S
2@
1
2
3
23
22
4
5
6
7
8
9
12
R406
1 2
0_0805_5%~D2@
U26
VDD
RESET#
LED8
LED7
LED6
LED9
LED10
LED11
LED12
LED13
LED14
LED15
PCA9532_TSSOP24~D
2@
A0
A1
A2
SDA
SCL
LED0
LED1
LED2
LED3
LED4
LED5
GND
LED_TP_B
24
21
13
11
10
14
15
16
17
18
19
20
+3.3V_RUN
C305
PCA_INT
LED_L_FAN_B#
LED_SPKR_G#
LED_R_FAN_B#
LED_SPKR_B#
LED_PANEL_R#
LED_PANEL_G#
LED_PANEL_B#
LED_TP_B#
LED_TP_B <39>
0.1U_0402_16V4Z~D2@
1
2
R401
10K_0402_5%~D2@
12
+3.3V_RUN
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
Rikers LEDs for FAN/Speaker/Panel/TP
LA-2881P
41 62Tuesday, December 13, 2005
1
of
2.0
Page 42
5
HEX STANDOFF
STAND1
1
HEX_STANDOFF~D@
D D
1
HEX_STANDOFF~D@
STAND2
1
HEX_STANDOFF~D@
STAND3
1
HEX_STANDOFF~D@
STAND4
Fiducial Mark
FD13
1
SMD40M80
FD6
1
SMD40M80
H5
C315D126@
C C
FD1
1
SMD40M80
H6
C315D126@
1
1
FD14
1
SMD40M80
FD3
1
SMD40M80
H18
C315D126@
1
1
SMD40M80
1
SMD40M80
H27
C315D126@
1
FD15
FD16
FD9
1
SMD40M80
FD11
1
FIDUCAL
H30
C315D126@
1
1
SMD40M80
1
FIDUCAL
H26
C315D126@
1
FD10
FD2
H7
TC236BC315D118@
1
SMD40M80
1
FIDUCAL
1
FD7
FD4
4
FD8
1
SMD40M80
FD17
1
FIDUCAL
H1
C315D91@
1
1
SMD40M80
1
FIDUCAL
H9
C315D91@
1
FD5
FD12
H2
C315D91@
FIDUCAL
1
3
MY1
MYLAR(ZZZ)
1
NC
MYLAR_DIMMA~D@
MY3
MYLAR(ZZZ)
1
NC
MYLAR_DIMMB~D@
MY4
MYLAR(ZZZ)
1
NC
MYLAR_MINIPCI~D@
FD18
1
H3
H10
C315D110@
C315D91@
1
1
1
CABLE2
NC
BlueTooth Cable@
Cable
MY2
MYLAR(ZZZ)
1
NC
SD_MINIPCI~D@
TAPE1
CONDUCTIVE
TAPE(ZZZ)
1
NC
CONDUCTIVE_TAPE~D@
ZZZ1
LOG LOW
GASKET(ZZZ)
1
NC
LOG_LOW_GASKET~D@
CABLE3
Cable
1
NC
Switch Board Cable@
2
BRKT1
IO BRACKET(ZZZ)
1
NC
IO_BRACKET~D@
RUBER1
SD_RUBBER (ZZZ)
1
NC
SD_RUBBER~D@
COVER1
RJ11_RUBBER (ZZZ)
1
NC
RJ11_RUBBER~D@
CABLE5
Cable
1
NC
Media Board Cable@
1
PCB
BARE PCB
1
NC
ZRS_LA-2881P _REV2_M/B~D
CABLE1
Cable
1
NC
17" LCD Caxil Cable@
CABLE4
Cable
1
NC
RJ11 MDC Cable@
CABLE6
Cable
1
NC
LED FFC Cable@
H13
C276D126@
1
MDC Standoff
H11
H22
C276D126@
1
H19
C354D126@
O531X571D452X492@
1
1
R612 No-POP P OP
HW POP option control table
ZUMA Zanzibar Rikers Suva
No-POP No-POP
R498 No-POP No-POP POP No-POP
(SD01412418L)
R515 1.24K 1. 24K 1.15K 1.15K
H21
C276D146
1
H12
C315D102
Keyboard
Standoff for
Zanzibar
Power SW Support
Standoff
H23
C275D102
1@
1
1@
1
H31
TP276@
1
R410 750 ohm 750 ohm 470 ohm 470 ohm
C414, C417, C422
C413, C416, C421
47 pF82 pF 47 pF 47 pF
L43, L44, L45 1.8 uH 0.47 uH 0.47 uH 0.47 uH
U6(MCH)
UMA Discrete Discrete Discrete
U23(LOM) 4401E 4401E 5752 5752
R359, R360
R364, R366
49.9_1% ohm 49.9_1% ohm 48.7_1% ohm 48.7_1% ohm
R205 1 5 ohm 15 ohm 33 ohm 33 ohm
1.24K P/N
(SD01411518L)
1.15K P/N
750 ohm P/N (SD02875008L)
470 ohm P/N (SD02847008L)
82 pF P/N (SE071820J8L)
(SE071470J8L)47 pF P/N
1.8 uH P/N
0.47 uH P/N
(SHI0118AK8L)
(SHI00002C0L)
UMA P/N (SA0000059GL)
Dis P/N (SA00000KDBL)
4401E P/N (SA00000oD0L)
5752 P/N (SA00000o71L)
49.9_1% ohm (SD014499A8L)
48.7_1% ohm (SD014487A8L)
15 ohm P/N (SD028150A8L)
33 ohm P/N (SD028330A8L)
H17
C276D110
3@
1
H29
C276D110@
1
H4
C134D134N@
1
H16
C276D110@
1
H8
O531X571D452X492@
1
H24
B B
C276D110
3@
1
C276D110@
1
H25
C276D110
3@
1
TC315BC197D110@
1
H28
O236X134D236X134N@
1
H14
C276D110
3@
1
H15
H20
VGA Standoffs
A A
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
PAD and Standoff
LA-2881P
42 62Tuesday, December 13, 2005
1
2.0
of
Page 43
5
4
3
2
1
D D
DOCK_PSID PS_ID
PR3
2
3
PD53
SM24_SOT23
@
1
C C
1 2
100K_0402_1%~D
PR7
1 2
15K_0402_1%~D
PS_ID Detector
PR151
0_0402_5%~D@
1 2
PQ1
FDV301N_SOT23
D
S
1 3
G
2
C
PQ2
2
B
PMBT3904_SOT23~D
E
3 1
PR2
33_0402_5%~D
1 2
PD1
+5V_ALW
3
DA204U_SOT323~D
+5V_ALW
PR5
10K_0402_1%~D
+3.3V_ALW
2
PR1
2.2K_0402_5%~D
PD2
@
1 2
+5V_ALW
DA204U_SOT323~D
PS_I D <38>
2
3
1
PS_ID_DISABLE# <38>
1
12
PR6
100_0402_5%~D@
1 2
+PWR_SRC
12
PC2
1U_0805_25V4Z~D
3.3V RTC Power
PU1
MAX1615EUK+_SOT23-5~D
1
IN
3
OUT
5
#SHDN
4
5/3+
GND
2
+3.3V_RTC_LDO
12
PC1
1U_0805_10V7K~D
+DC_IN Source
PQ3
FDS6679Z_SO8~D5@
8
7
5
4
PQ4
SI4825DY_SO8~D4@
8
7
5
4
12
0.1U_0603_25V7K~D
THE POINT
12
PC6
0.1U_0603_25V7K~D
12
PC5
PC4
12
47K_0402_5%~D
0.01U_0402_25V7K~D
NOTE: "THE POINT LOCATED
AT PS MODULE
+DC_IN_SS
12
1
PC7
PR9
2
10K_0603_1%~D
10U_1206_25V6M~D
1 2
G
2
12
PR8
240K_0402_5%~D
D
13
PQ35
SI2301DS_SOT23~D@
1
2
3 6
1
2
3 6
PQ_G
PR10
+DC_IN
PL1
BLM11B102S 0603~D
12
@
PC168
0.01U_0402_25V7K~D
DOCK _PSID <36>
12
12
PR180
100K_0402_1%~D
@
PC3
0.47U_0805_25V7k
S
PWR_ID
PJDCIN
B B
FOX_JPD113D-509-TR~D
9
GND_4
8
GND_3
7
GND_2
6
GND_1
MH1
Change PL2, PL21 filter from 6A to 9A
for rated current concern
MH2
Low_PWR
DC+_1
DC+_2
DC-_1
DC-_2
1
2
3
4
5
KC FBMA-L18-453215-900LMA90T _1812~D
+DCIN_JACK
KC FBMA- L18-453215-900LM A90T_1812~D
-DCIN_JACK
PL2
1 2
PL21
1 2
13
AC_OFF<37,49>
A A
2
PQ36
DTC115EUA_SC70~D@
DELL CONFIDENTIAL/PROPRIETARY
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R &D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INF ORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WR ITT EN CO NSE NT OF COMPAL ELECTRONICS, INC.
3
2
Title
Size Do c um e n t N u mb er Re v
Date: Sheet
Compal Electronics, Inc.
+DCIN
1
43 62Tuesday, De ce mber 13, 2005
2.0
of
Page 44
5
4
3
2
1
+3.3V_ALW
D D
3
+PBATT
Z4304
Z4305
Z4306
Z4307
+PBATT
PD3
DA204U_SOT323~D@
PR12
100_0402_5%~D
1 2
1
100_0402_5%~D
Battery Connector
PJBAT
SUYIN_200028MR009G502ZL~D
12
PC9
2200P_0402_50V7K~D
C C
BATT_PRES#
10
GND
11
GND
BATT1+
BATT2+
SMB_CLK
SMB_DAT
SYSPRES#
BATT_VOLT
BATT1BATT2-
1
2
3
4
5
6
7
8
9
2
PD4
DA204U_SOT323~D@
PR13
1 2
ESD Diodes
2
3
1
PR14
100_0402_5%~D
1 2
3
100_0402_5%~D
1 2
Change PL3 from 6A to 9A
Pop PL4 needed for ZRS/ ZUMA for discharge current concern
2
PD5
1
DA204U_SOT323~D@
PR15
2
3
PL3
KC FBMA-L18-453215-900LMA90T _1812~D
PD6
1
DA204U_SOT323~D@
PBAT_SMBCLK <38,41,49>
PBAT_SMBDAT <38,41,49>
PBAT_ALARM# <37>
1 2
PL4
KC FBMA-L18-453215-900LMA90T _1812~D
1 2
12
PC8
0.1U_0603_25V7K~D
+VCHGR
+3.3V_ALW
12
PR11
10K_0402_1%~D
PBAT_PRES# <37>
9
8
7
6
5
4
3
2
1
SUYIN_200028MR009G502ZL
TOP view
B B
A A
DELL CONFIDENTIAL/PROPRIETARY
Title
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
Battery Conn
44 62Tuesday, December 13, 2005
1
2.0
of
Page 45
5
4
3
2
1
DC +3.3V/ +5V
PL5
FBM-L11-453215-900LMAT_1812~D
1
+
2
330U_D3L_6.3VM_R25~D
PR184
0_0603_5%~D
+15V_SUSP
+5V_SUSP
+3.3V_SRCP
1 2
PAD-OPEN 4x4m
1 2
12
PC25
0.1U_0402_10V7K~D
12
GNDA_3V5V
+3.3V_SRCP
S
D
6
+3.3V_ALW
5
PJP4
PR20
0_0402_5%~D
@
PR22
PR175
0_0603_5%~D
0_0402_5%~D
1 2
@
GNDA_3V5V
NC_TEST1
3
G
PQ39
2451
FDC655BN_NL_SSOT-6~D
PJP5
1 2
PAD-OPEN 4x4m
PJP6
1 2
PAD-OPEN 4x4m
PJP7
1 2
PAD-OPEN 4x4m
1 2
1 2
+PWR_SRC
D D
3.3 Volt +/-5%
Typical current: 4.67A
Max current: 6.67A
Min OCP: 7.4A
C C
B B
A A
+3.3V_SRCP
PC24
Output Caps ESR
= 25mohms
+DCDC_PWR_SRC
1
PC11
PC10
2
0.1U_0603_25V7K~D
10U_1206_25V6M~D
Place these CAPs
close to FETs
VAUX_EN<38,40>
SUS_ON<38,40>
+15V_SUS
+5V_SUS
+3.3V_SRC
PL6
1 2
3.2U_CEP125NP-3R2MC_9.9A_20%~D
RUN_ENABLE <40>
12
PC12
2200P_0402_50V7K~D
0.1U_0603_25V7K~D
12
578
PQ5
SI4800BDY-T1_SO8~D
3 6
241
578
PQ7
3 6
241
FDS6690AS_NL_SO8~D
PR181
0_0402_5%~D@
1
I1
2
I0
PC171
12
+3.3V_RTC_LDO
SUS_ON<38,40>
ALWON<38>
THERM_STP#<16>
PR16
0_1206_5%~D
1 2
12
PC19
4.7U_1206_25V6K~D
@
0.1U_0603_25V7K~D
12
3
G
4
O
P
PU16
5
SN74AHC1G32DCKR_SSOP5~D
2K_0402_1%~D
PR32
1 2
240K_0402_5%~D
Return to original design due to
SMSC issue already be fixed.
4
PR152
1 2
10_1206_5%~D
@
12
PC20
0.1U_0603_25V7K~D
PC22
PR30
1 2
PR163
1K_0402_1%~D
1 2
12
PC32
@
+VCC_MAX8734
PR19
0_0603_5%~D
1 2
MAX8734_DH3
MAX8734_LX3
MAX8734_DL3
MAX8734_FB3
MAX8734_ON3
MAX8734_ON5
12
1000P_0402_50V7K~D
+VCC_MAX8734
PR17
47_0603_5%~D
12
PC16
GNDA_3V5V
1U_0603_10V6K~D
MAX8734_BST3B MAX8734_BST5B
PC30
PU2
20
V+
17
VCC
6
SHDN
28
BST3
26
DH3
27
LX3
24
DL3
22
OUT3
7
FB3
3
ON3
4
ON5
25
LDO3
+3.3V_ALW
12
4.7U_1206_10V7K~D
MAX8734_V+
12
1
PD7
2
3
RB717F_SOT323~D
LDO5
BST5
OUT5
PRO
ILIM5
ILIM3
GND
PGOOD
SKIP
MAX8734AEEI+_QSOP28~D
12
MAX1999_SKIP#
PR29
0_0402_5%~D@
PR31
0_0402_5%~D@
12
Enable Skip Mode
PR33
0_0402_5%~D
+5V_SUSP
1
PC34
2
22U_1206_6.3V6K~D
Leverage Sullivan
12
PC14
PC15
0.1U_0603_25V7K~D
PL7
1 2
1
2
10U_1206_25V6M~D
MAX8734_ILIM5
MAX8734_ILIM3
MAX8734_PRO#
MAX8734_TON
2
PC145
10U_1206_25V6M~D
PC17
DH5
LX5
DL5
N.C.
FB5
REF
TON
12
1U_0603_10V6K~D
18
0_0603_5%~D
14
16
15
19
21
1
9
10
11
5
8
13
23
2
12
12
+5V_ALW
12
PC18
4.7U_1206_10V7K~D
PR18
PC21
0.1U_0603_25V7K~D
1 2
1 2
MAX8734_DH5
MAX8734_LX5
MAX8734_DL5
MAX8734_FB5
MAX8734_PRO#
MAX8734_ILIM5
MAX8734_ILIM3
MAX8734_REF
MAX8734_TON
12
PC29
+3.3V_SRCP
1U_0603_10V6K~D
GNDA_3V5V
+VCC_MAX8734
RUN_ON <19,38,40,46,47>
PR24
12
PC13
2200P_0402_50V7K~D
Place these CAPs
close to FETs
578
PQ6
PQ8
L-S Rds-on (max)
=20m ohms
1 2
100K_0402_1%~D
SUSPWROK_5V < 40,47>
SI4800BDY-T1_SO8~D
3 6
241
5.6U_CEP125NP-5R6M_8.8A_20%~D
578
3 6
241
SI4810BDY_SO8~D
1
+15V_SUSP
PC33
1000P_0402_50V7K~D@
1 2
PR39
30.9K_0402_1%~D
1 2
PJ3800CS_IN PJ3800CS_FB
PJ3800CS_SCP
12
PR40
1 2
PC38
1.07K_0402_1%~D
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R &D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INF ORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WR ITT EN CO NSE NT OF COMPAL ELECTRONICS, INC.
3
PR42
150_0603_1%~D
0.1U_0603_25V7K~D
PU4
1
FB
-IN
2
SCP
OSC
3
VCC
MAX8731_BR PJ3800CS_OUT
1 2
GND
4
OUT
BR/CTL
MB3800PNF-EFE1 SOL-8 PWM~D
PL8
22U_SPC_06704_22R0GP_1.3A_30%~D
8
7
6
5
PJ3800CS_OSC
12
PR41
PC39
270P_0402_50V7K~D
2
12
1 2
3.92K_0402_1%~D
PC40
12
0.1U_0603_25V7K~D
PR21
0_0402_5%~D
1 2
@
PR23
1 2
0_0402_5%~D
GNDA_3V5V
NC_TEST2
MAX8734_REF
PR25
19.1K_0402_1%~D
1 2
PR34
1 2
150K_0402_1%~D
6
2
1
D
G
3
S
4 5
SI3442BDV-T1-E3_TS O P 6~ D
5 Volt +/-5%
Typical current: 4A
Max current: 5.6A
Min OCP: 8.5A
+5V_SUSP
1
12
PC28
PR176
0_0603_5%~D
1 2
@
PR26
71.5K_0402_1%~D
PR35
100K_0402_1%~D
GNDA_3V5V
PD8
SKUL30-02AT_SMA
2 1
PQ9
+
PC26
2
0.1U_0402_10V7K~D
330U_D3L_6.3VM_R25~D
Output Caps ESR
= 25mohms
+VCC_MAX8734
12
12
PR28
PR27
1 2
1 2
@
PR36
0_0402_5%~D
100K_0402_5%~D
12
12
0_0402_5%~D
PC35
@
13
D
2
PR37
@
1
+
2
15U_D2_25M_R90~D
G
PQ31
S
RHU002N06_SOT323@
0_0402_5%~D
1
1
+
PC36
PC37
2
2
100U_25VM_R340m
10U_1206_25V6M~D
DELL CONFIDENTIAL/PROPRIETARY
Title
Size Do c um e n t N u mb er Re v
Date: Sheet
Compal Electronics, Inc.
+3.3V/+5V/+15V
1
THERM_STP# <16>
+15V_SUSP
1
+
PC172
2
100U_25VM_R340m
45 62Tuesday, De ce mber 13, 2005
2.0
of
Page 46
A
B
C
D
PL9
FBM-L11-453215-900LMAT_1812~D
1 2
+PWR_SRC
1 1
PAD-OPEN 4x4m
1 2
PJP8
+1.5V_1P05VP_PWRSRC
PC169
10U_1206_25V6M~D
@
1
1
PC41
PC42
2
2
10U_1206_25V6M~D
Place these CAPs
close to FETs
12
12
PC43
0.1U_0603_25V7K~D
2200P_0402_50V7K~D
ISL6227_BOOT2B ISL6227_BOOT1B
1.5 Volt +/-5%
Thermal Design Current: 4.6A
Maximum current: 6.5A
OCP min: 7.2A, max: 13.1A
2 2
3 3
PR51=0, PR5 8 Nopop, PWM/ HYS
PR51 Nopop, PR58=0, froce PWM
4 4
+VCCP_1P05VP +1.05V_VCCP
Output Caps ESR
= 9mohms
+1.5V_RUNP
+1.5V_RUNP
12
PC58
10U_0805_6.3V5K~D
@
1
+
PC55
2
330U_D2E_2.5VM_R9~D
PAD-OPEN 4x4m
1 2
PAD-OPEN 4x4m
1 2
PAD-OPEN 4x4m
1 2
PAD-OPEN 4x4m
1 2
PJP9
PJP10
PJP11
PJP12
1 2
12
19.6K_0402_1%~D
12
28.7K_0603_1%~D
+1.5V_RUN
PL10
3
PR161
1 2
1K_0603_1%~D
@
L-S Rds-on (max)
ISL6227_VSEN2
Use PR48 and PR52
for voltage margining
RUN_ON<19,38,40,45,47>
Layut notes:
Place PC49 need very close Pin1 of PU5, and Pin28 of PU5.
Place PR147 need very close Pin1 of PU5.
Minimize loop including PQ33, PQ34, PL10, PC58, PC55 and PR147.
Minimize loop including PQ10, PQ12, PL11, PC57, PC53, PC54, PC55 and PR147.
Route GNDA_D C2 using 25mil trace width.
Minimize GNDA _ D C 2 t r a c e length.
Place PC52, PR48 and PR52 near Pin19 of PU5.
Place PR51 and PR58 near Pin20 of PU5.
Place PC56, PR49 and PR53 near Pin10 of PU5.
Place PR50 and PR59 near Pin9 of PU5.
Place PR54, PC60, PR55, PC59 near Pin 18, 17, 11, 12 of PU5.
Place PR46, PR47 near Pin7, 22 of PU5.
Place PR44, PC50 near Pin23, 25 of PU5.
Place PR45, PC51 near Pin6, 4 of PU5.
Route 1.05V Boot and 1.5V Boot using 25m il trace width and minim ze length.
Need large copper fill areas to PQ33, PQ34, PQ10 and PQ12 for thermal inprovment.
Minize length of 1.5V phase node and 1.05V phase node.
PC41, PC42 and PC43 need close Pin5, 6, 7, 8 of PQ33.
PC44, PC45, PC46 and PC47 need close Pin5, 6, 7, 8 of PQ10.
Route +1.5V _ 1 P 0 5 V P _ P WRSRC using 50 mil trace width and minimize length.
Route VSEN1 and VSEN2 away from inductor and switch node,
sense Vout directly at output bulk caps.
=11.5m ohms
3.2UH_CDEP12D38NP-3R2MC-88_8.5A_20%~D
12
PC52
PR48
0.01U_0402_25V7K~D
PR51
0_0402_5%~D
1 2
PR58
0_0402_5%~D
1 2
@
GNDA_DC2
A
PR52
PR177
0_0603_5%~D
1 2
@
GNDA_DC2
NC_TEST3 NC_TEST4
PQ33
FDS8880_SO8~D
PQ34
FDS6670AS_SO8~D
1K_0402_1%~D
578
3 6
241
578
3 6
241
PR173
1 2
PC50
1 2
0.1U_0603_25V7K~D
B
+1.5V_RUNP / +VCCP_1P05VP
+5V_SUS
PR43
1 2
10_0805_5%~D
ISL6227_VCC
12
12
PC49
PR44
0_0603_5%~D
PR46
1.43K_0402_1%~D
1 2
PR54
124K_0402_1%
GNDA_DC2 G NDA_DC2 GNDA_DC2 GNDA_DC2 GNDA_DC2
GNDA_DC2
2.2U_0805_10V6K~D
ISL6227_BOOT2 ISL6227_BOOT1
ISL6227_PHASE2
ISL6227_LGATE2
ISL6227_ISEN2 ISL6227_ISEN1
ISL6227_EN2
ISL6227_OCSET2
ISL6227_SOFT2
1 2
PC60
1 2
0.01U_0402_25V7K~D
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PU5
28
VCC
23
BOOT2
24
UGATE2
25
PHASE2
27
LGATE2
22
ISEN2
26
PGND2
19
VSEN2
20
VOUT2
21
EN2
18
OCSET2
17
SOFT2
16
PG2/REF
ISL6227CA-T_SSOP28~D
PD9
BAT54A-7-F_SOT23~L
1
12
PC48
1U_0603_10V6K~D
13
DDR
14
VIN
6
BOOT1
5
UGATE1
4
PHASE1
2
LGATE1
7
ISEN1
3
PGND1
10
VSEN1
9
VOUT1
ISL6227_EN1
8
EN1
ISL6227CA-T
OCSET1
SOFT1
GND
PG1
+3.3V_RUN
PR183
@
11
12
15
1
12
100K_0402_1%~D
ISL6227_OCSET1
ISL6227_SOFT1
32
PR174
0_0402_5%~D
ISL6227_UGATE1ISL6227_UGATE2
ISL6227_PHASE1
ISL6227_LGATE1
1 2
12
PC151
0.01U_0402_25V7K~D
12
PR45
0_0603_5%~D
PR47
1.87K_0402_1%~D
1 2
PC59
1 2
0.01U_0402_25V7K~D
1K_0402_1%~D
1 2
+3.3V_RUN
12
PR60
100K_0402_1%~D
@
1.5V_RUN_PWRGD <40>
C
PR55
PR57
1
10U_1206_25V6M~D
1
PC47
2
2
10U_1206_25V6M~D
@
12
PC45
PC44
2200P_0402_50V7K~D
Place these CAPs
close to FETs
12
PC46
0.1U_0603_25V7K~D
1.05 Volt +/-5%
578
PC51
1 2
0.1U_0603_25V7K~D
1 2
124K_0402_1%~D
PQ10
FDS8880_SO8~D
PQ12
FDS6670AS_SO8~D
L-S Rds-on (max)
=9.3m ohms
1.05V_RUN_PWRGD <40,48>
3 6
241
1.5uH_SIL104-1R5_10A_30%~D
1 2
578
PR160
1 2
1K_0603_1%~D
3 6
241
@
ISL6227_VSEN1
Use PR49 and PR53
for voltage margining
RUN_ON <19,38,40,45,47>
PL11
PC56
0.01U_0402_25V7K~D
Thermal Design Current: 6A
Maximum current: 8.6A
OCP min: 9.5A, max: 18.2A
12
12
GNDA_DC2
PR49
5.11K_0402_1%~D
12
PR53
30.1K_0603_1%~D
PR147
0_0603_5%~D
PR178
0_0603_5%~D
1 2
@
GNDA_DC2GND
12
12
PC57
10U_0805_6.3V5K~D
@
PR50
1 2
0_0402_5%~D
PR50=0, PR5 9 Nopop, PWM/ HYS
PR50 Nopop, PR59=0, froce PWM
PR59
0_0402_5%~D
1 2
@
GNDA_DC2
GNDA_DC2
+VCCP_1P05VP
1
+
PC54
PC53
2
330U_D2E_2.5VM_R9~D
330U_D2E_2.5VM_R9~D
@
Output Caps ESR
= 9mohms
1
+
2
DELL CONFIDENTIAL/PROPRIETARY
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
+1.5VRUNP /+VCCP_1P05VP
46 62Tuesday, December 13, 2005
D
of
2.0
Page 47
5
4
+1.8V_SUSP/ +0.9V_DDR_VTTP
DDR2 Termination
3
2
1
GNDA_DDR
MAX8632_OVP
2
OVP/ UVP
SKIP
25
PR146
0_0402_5%~D@
28
TP0
GND
24
GNDA_DDR
PR63
PC83
+5V_SUS
1 2
10_1206_5%~D
12
MAX8632_AVDD
26
AVDD
REFIN
PGND2
SS
8
12
1000P_0402_50V7K~D
GNDA_DDR
POK1
POK2
SHDN
STBY
VTTI
VTTS
VTTR
VIN
VTT
29
GND
PR145
0_0402_5%~D
12
PC68
1U_0603_10V6K~D
GNDA_DDR
17
5
6
27
7
13
14
11
12
9
10
12
+DDR_PWR_SRC
MAX8632_REFIN
PC76
12
PC84
1U_0603_10V6K~D
GNDA_DDR
SUSPWROK_5V
20_0603_1%~D
12
GNDA_DDR
0.1U_0402_10V7K~D
PR70
+3.3V_SUS
PR65
100K_0402_1%~D
PC77
PR66
1 2
1 2
100K_0402_1%~D
@
12
12
0.1U_0402_10V7K~D
+1.8V_SUSP
SUSPW ROK_1P8V <40>
0.9V_DDR_PWRGD <40>
SUSPWR OK_5V < 40,45>
RUN_ON <19,38,40,45,46>
1
PC70
2
10U_0805_6.3V5K~D
1
PC78
1
2
10U_0805_6.3V5K~D
1
PC79
PC80
2
2
10U_0805_6.3V5K~D
10U_0805_6.3V5K~D
@
+0.9V_DD R_REF <10,17,18>
0.9 Volt
VTTR current limit: +-32mA typ
0.9 Volt +/-5%
Design current 1.05A for +0.9V_DDR_VTTP
Peak current 1.5A for +0.9V_DDR_VTTP
+1.8V_SUSP
+0.9V_DDR_VTTP
PL12
1
+
PC73
2
330U_D2E_2.5VM~D
0.1U_0402_10V7K~D
FBM-L11-453215-900LMAT_1812~D
1 2
PJP13
PAD-OPE N 4x4m
1 2
12
PR179
0_0603_5%~D
1 2
@
NC_TEST5
+PWR_SRC
D D
1.8 Volt +/-5%
Design Current: 7.3A
Maximum Current: 10.5A
OCP min: 10.5A
+1.8V_SUSP
C C
1
+
PC71
PC72
2
330U_D2E_2.5VM~D
Output Caps ESR
= 15mohms/ each
B B
12
PR71
27.4K_0603_1%~D
@
12
PR75
17.4K_0402_1%~D
@
GNDA_DDR
+DDR_PWR_SRC
1
PC63
PC64
2
10U_1206_25V6M~D
1.4UH_HMU1356-1R4_15.5A_+-20%~D
2 1
1
12
PC65
2
0.1U_0603_25V7K~D
10U_1206_25V6M~D
Place these CAPs
close to FETs
PL13
3
PR69
4.7_1206_5%~D
@
PC75
1000P_0603_50V7K~D
@
MAX8632_AVDD
+5V_SUS
12
PC66
2200P_0402_50V7K~D
21
PD11
RB751V-40_SOD323~D
578
12
12
PC82
0.22U_0603_10V7M~D
PR67
1_0603_5%~D
12
MAX8632_DH
MAX8632_LX
MAX8632_DL
MAX8632_FB
PR72
0_0402_5%~D @
No pop, f= 300KHz
MAX8632_REF
PR73
1 2
100K_0402_1%~D
12
PR76
36.5K_0402_1%~D
GNDA_DDR
PC69
0.1U_0603_25V7K~D
IRF7821_SO8~D
IRF7832_SO8~D
PR74
0_0402_5%~D
3 6
241
578
3 6
241
L-S Rds-on (max)
=4.8m ohms
12
PQ13
12
PQ15
12
12
PR186
0_0402_5%~D
@
12
PC67
4.7U_1206_10V7K~D
20
18
19
21
23
16
15
1
12
3
MAX8632_ILIM
PU6
BST
DH
LX
DL
PGND1
VOUT
FB
TON
REF
+5V_SUS+5V_ALW
PR187
0_0402_5%~D
12
22
VDD
MAX8632ETI+_TQFN28~D
ILIM
4
PJP14
PAD-OPE N 4x4m
1 2
PJP15
PAD-OPE N 4x4m
+1.8V_SUSP
+0.9V_DDR_VTTP
A A
1 2
PJP16
1 2
PAD-OPE N 4x4m
5
+1.8V_SUS
(10A,320mils ,Via NO.=20)
+0.9V_DDR_VTT
(2A,200mils ,Via NO.=4)
PR148
0_0603_5%~D
GNDA_DDRGND
12
4
GNDA_DDR
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
DELL CONFIDENTIAL/PROPRIETARY
Title
+1.8VSUSP/ +0.9 V _ DDR_VT
Size Do c um e n t N u mb er Re v
LA-2881P
Date: Sheet
1
47 62Tuesday, De ce m ber 13, 2005
of
2.0
Page 48
8
H H
G G
F F
PR86
0_0402_5%~D
IMVP6_PROCHOT#<37>
PR88
H_DPRSTP#<7,22>
GNDA_VCORE
DPRSLPVR<10,23>
1.05V_RUN_PWRGD<40,46>
CLK_ENABLE#<6>
VCCSENSE<8>
VID0<8>
VID1<8>
VID2<8>
VID3<8>
VID4<8>
VID5<8>
VID6<8>
H_PSI#<8>
RUNPWROK<19,37,38,40>
VSSSENSE<8>
0_0402_5%~D @
220P_0402_50V8J~D
8
GNDA_VCORE
E E
D D
GNDA_VCORE
C C
B B
A A
147K_0402_1%~D
12
0.01U_0402_25V7K~D
PR182
0_0402_5%~D
1 2
PR102
0_0402_5%~D@
1000P_0402_50V7K~D
1000P_0402_50V7K~D
PR109
332_0402_1%~D
1500P_0402_50V7K~D
PC116
1 2
PR87
PC100
PR91
0_0402_5%~D
PR93
0_0402_5%~D
PR95
0_0402_5%~D
0_0402_5%~D
12
0_0402_5%~D @
PR105
0_0402_5%~D
PR106
0_0402_5%~D
PC104
12
PC105
12
680P_0402_50V7K~D
12
PR110
2.21K_0402_1%~D
PC114
1 2
PR149
0_0805_5%~D
12
470KB_0402_5%_NCP15WM474J03RB~D@
12
PR90
0_0402_5%~D
12
PR92
0_0402_5%~D
12
PR94
0_0402_5%~D
12
PR97
PR99
0_0402_5%~D
12
PR104
12
12
12
PC106
1 2
12
PC117
1000P_0402_50V7K~D
PR116
6.34K_0402_1%~D
GNDA_VCOREGND
12
499_0402_1%
GNDA_VCORE
12
PH1
12
12
12
12
12
PR100
12
PR185
0_0402_5%~D
1 2
PR107
0_0603_1%~D
PR113
82.5K_0402_1%~D
12
12
GNDA_VCORE
7
+VCC_CORE IMVP-6
+5V_RUN
PR81
1 2
10_0603_5%~D
12
PC94
1U_0603_10V6K~D
ISL6260_VR_TT#
ISL6260_RBIAS
ISL6260_NTC
ISL6260_SOFT
ISL6260_VID0
ISL6260_VID1
ISL6260_VID2
ISL6260_VID3
ISL6260_VID4
ISL6260_VID5
ISL6260_VID6
ISL6260_DPRSTP#
ISL6260_DPRSLPVR
ISL6260_PSI#
ISL6260_PGD_IN
ISL6260_CLK_EN#
ISL6260_VR_ON
ISL6260_FB
12
ISL6260_COMP
ISL6260_VM
12
10.5K_0402_1%~D
ISL6260_DROOP
7
+CPU_PWR_SRC
PR77
10_0603_5%~D
12
PC91
0.01U_0402_25V7K~D
GNDA_VCORE
ISL6260_VDD
19
41
20
VSS
VSS
VDD
4
VR_TT#
3
RBIAS
5
NTC
6
SOFT
PU8
ISL6260CRZ-T_QFN40~D
28
VID0
29
VID1
30
VID2
31
VID3
32
VID4
33
VID5
34
VID6
37
DPRSTP#
36
DPRSLPVR
1
PSI#
2
PGD_IN
38
CLK_EN#
35
VR_ON
12
VSEN
13
RTN
11
VDIFF
10
FB
9
COMP
8
VW
DROOP
14
PR119
12
PC121
330P_0402_50V7K~D
1 2
ISL6260_VIN
39
18
VIN
DFB15VO
ISL6260_DFB
1K_0402_1%~D
12
3V3
PWM1
ISEN1
PWM2
ISEN2
FCCM
PWM3
ISEN3
OCSET
VSUM
+3.3V_RUN
PR84
1.91K_0603_1%~D
40
PGOOD
27
23
26
22
24
25
21
7
17
16
ISL6260_VO
PR120
GNDA_VCORE
6
1 2
ISL6260_PWM1
ISL6260_ISEN1
ISL6260_PWM2
ISL6260_ISEN2
ISL6260_FCCM
ISL6260_PWM3
ISL6260_ISEN3
ISL6260_OCSET
ISL6260_VSUM
12
PR112
4.53K_0402_1%~D
12
PC170
1 2
0.1U_0603_25V7K~D
6
PC112
0.33U_0603_10V7K~D
IMVP_PWRGD <23,40>
11.5K_0402_1%~D
2
PC113
1
1
PC118
2
0.012U_0402_16V7K~D
5
+5V_RUN
12
PC89
PC99
1U_0603_10V6K~D
1U_0603_10V6K~D
+5V_RUN
12
PU7
5
VCC
6
FCCM
UGATE
2
PWM
PHASE
3
LGATE
GND
ISL6208CRZ-T_QFN8~D
PU9
5
VCC
6
FCCM
UGATE
2
PWM
PHASE
3
LGATE
GND
ISL6208CRZ-T_QFN8~D
BOOT
BOOT
PR78
0_0603_5%~D
1
8
7
4
PR89
0_0603_5%~D
1
8
7
4
4
PC90
0.22U_0603_10V7K~D
12
1 2
ISL6208_UGATE1
ISL6208_PHASE1
ISL6208_LGATE1
0.22U_0603_10V7K~D
12
1 2
ISL6208_UGATE2
ISL6208_PHASE2
ISL6208_LGATE2
L-S Rds-on (max)
=3.3m ohms
PC101
PQ16
PQ17
PQ18
PQ19
3
+CPU_PWR_SRC
1
12
12
578
IRF7821_SO8~D
3 6
241
3
D
2
G
S
FDS7088SN3_SO8~D
1
578
IRF7821_SO8~D
3 6
241
3
D
2
G
S
FDS7088SN3_SO8~D
1
PC85
PC95
PC86
0.1U_0603_25V7K~D
2200P_0402_50V7K~D
12
PC93
1500P_0805_50V7K
@
12
12
PC96
0.1U_0603_25V7K~D
2200P_0402_50V7K~D
12
PC103
1500P_0805_50V7K
@
1
PC87
PC88
2
2
10U_1206_25VAK~D
10U_1206_25VAK~D
0.45U_ETQP4LR45XFC_25A_20%~D
PR82
10K_0402_1%~D
1 2
PR83
1 2
7.68K_0805_1%~D
ISL6260_VSUMISL6260_VSUMISL6260_VSUM
1
1
PC97
PC98
2
2
10U_1206_25VAK~D
10U_1206_25VAK~D
0.45U_ETQP4LR45XFC_25A_20%~D
DCR2_SEN1 DCR2_SEN2
PR101
10K_0402_1%~D
1 2
PR103
1 2
7.68K_0805_1%~D
2
+CPU_PWR_SRC
Place these CAPs
close to FETs
PL15
1
2
0.22U_0603_10V7K~D
Place these CAPs
close to FETs
PL16
1
2
0.22U_0603_10V7K~D
1
Reserve PC173
Double footprint with PC150.
PL14
FBM-L11-453215-900LMAT_1812~D
1 2
PJP17
PAD-OPE N 4x4m
1 2
PJP18
PAD-OPE N 4x4m
1 2
4
DCR1_SEN2DCR1_SEN1
3
PC92
+CPU_PWR_SRC
4
3
PC102
Output Caps=330uF*6Pcs/ 7mOhms
PR79
1 2
10_0402_1%~D
12
ISL6260_VO
PR96
1 2
10_0402_1%~D
12
ISL6260_VO
NEC MPC1040LR45
DCR=1.1+-7% mohms
PC150
220U_CE-AX_25V_M ~D
+VCC_CORE
+VCC_CORE
+PWR_SRC
1
1
+
+
PC173
2
2
100U_25VM_R340m@
ESR <= 1.5m ohm
PR108
12
12
2
PR111
1
2.43K_0402_1%~D
0.033U_0402_16V7K~D
12
12
PH2
PR117
15K_0402_1%~D
6.8KB_0603_5%_ERTJ1VR682J~D
+5V_RUN
578
12
PC111
1U_0603_10V6K~D
5
6
2
3
PU10
VCC
FCCM
PWM
GND
ISL6208CRZ-T_QFN8~D
BOOT
UGATE
PHASE
LGATE
1
8
7
4
PR114
0_0603_5%~D
ISL6208_UGATE3
ISL6208_PHASE3
ISL6208_LGATE3
0.22U_0603_10V7K~D
12
1 2
PC115
PQ20
PQ21
IRF7821_SO8~D
3 6
241
3
D
2
G
S
FDS7088SN3_SO8~D
1
12
12
PC108
2200P_0402_50V7K~D
PC120
1500P_0805_50V7K
@
PC109
0.1U_0603_25V7K~D
12
PC107
Place these CAPs
close to FETs
1
1
PC110
2
2
10U_1206_25VAK~D
10U_1206_25VAK~D
0.45U_ETQP4LR45XFC_25A_20%~D
1
DCR3_SEN1 DCR3_SEN2
2
PR121
10K_0402_1%~D
1 2
PR122
1 2
7.68K_0805_1%~D
+CPU_PWR_SRC
PL17
4
3
PC119
0.22U_0603_10V7K~D
12
PR115
10_0402_1%~D
1 2
ISL6260_VO
+VCC_CORE
DELL CONFIDENTIAL/PROPRIETARY
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R &D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INF ORMATION IT CONTAINS
5
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WR ITT EN CO NSE NT OF COMPAL ELECTRONICS, INC.
4
3
Title
Size Do c um e n t N u mb er Re v
Date: Sheet
2
Compal Electronics, Inc.
+VCORE
48 62Tuesday, De ce mber 13, 2005
1
2.0
of
Page 49
5
+DC_IN discharge path
D D
+DC_IN_SS
1
PC122
2
10U_1206_25V6M~D
PR131
1 2
365K_0402_1%~D
C C
GNDA_CHGR
B B
A A
PR133
49.9K_0402_1%~D
PC130
0.01U_0402_25V7K~D
PBAT_SMBCLK<38,41,44>
PBAT_SMBDAT<38,41,44>
PR150
0_0603_5%~D
GND
12
12
12
AC_OFF<37,43>
GNDA_CHGR
GNDA_CHGR
RHU002N06_SOT323
ACAV_IN
15.8K_0402_1%~D
+5V_ALW
0.1U_0402_10V7K~D
GNDA_CHGR
DTC115EUA_SC70~D@
+PWR_SRC
N657586
PU17 for back up.
ACAV_IN<16,19,38>
PR129
PC132
PQ38
PQ27
13
D
2
G
S
ACAV_IN
12
12
13
2
+5V_ALW
PR124
10K_0402_1%~D
2
G
PR132
10K_0402_1%~D
1 2
0_0402_5%~D
1 2
12
PR140
10K_0402_1%~D
12
PC174
100P_0402_50V8K
@
PU17
5
4
3
12
13
D
PQ26
RHU002N06_SOT323
S
10K_0402_1%~D
MAX8731_LDO
PR135
12
PC142
0.1U_0402_10V7K~D
12
PC175
0.01U_0402_25V8K
@
V+
VINVIN+
INA194 SOT23-5~D@
Pop Option notes:
Reserve PR169 and PR172 for 90W
5@. For Ricker/ Suva for 130W
5
PR127
PR139
PC143
8
7
5
8
7
5
4.7K_0402_5%~D
0.01U_0402_25V7K~D
OUT
GND
4
PQ23
FDS6679Z_SO8~D5@
4
PQ25
SI4825DY_SO8~D4@
12
GNDA_CHGR
12
12
12
PC139
0.01U_0402_25V7K~D
MAX8731_IINP
1
2
4
1
2
36
1
2
36
4
PR128
100K_0402_1%~D
PC123
1U_0805_25V4Z~D
MAX8731_ACIN
MAX8731_ACOK
MAX8731_IINP
MAX8731_CCV
MAX8731_CCI
MAX8731_CCS
12
PC140
0.01U_0402_25V7K~D
MAX8731_REF
PR170
0_0402_5%~D5@
1 2
PR188
80.6K_0402_1%@
1 2
12
PC141
1U_0603_10V6K~D
12
MAX8731_REF
12
MAX8731_DAC
PC144
0.1U_0402_10V7K~D
GNDA_CHGR
12
PC160
0.01U_0402_25V8K
@
Smart Charger
N657586
PR126
PR130
0_0402_5%~D
1 2
GNDA_CHGR
PU11
22
DCIN
2
ACIN
13
ACOK
11
VDD
10
SCL
9
SDA
14
BATSEL
8
IINP
6
CCV
5
CCI
4
CCS
3
REF
7
DAC
12
GND
12
12
PR189
PR169
49.9K_0402_1%@
12
13.3K_0402_1% 5@
PR171
12
PR172
PR190
9.31K_0402_1%~D@
3
PL18
PR123
0.01_2512_1%~D
1
2
0_0402_5%~D
1 2
@
MAX8731_CSSP
MAX8731_ACSNS
1
29
GND
GND
MAX8731_TQFN28~D
12
33.2K_0402_1%5@
12
15K_0402_1%5@
+PWR_SRC
4
3
Change PL18 from 6A to 9A
Pop PL19 needed for ZRS/ ZUMA for discharge rated current concern
MAX8731_CSSN
27
28
MAX8731_VCC
26
VCC
CSSP
CSSN
PGND
CSIP
CSIN
FBSA
FBSB
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
BST
LDO
DHI
LX
DLO
25
MAX8731_LDO
21
MAX8731_DHI
24
MAX8731_LX
23
MAX8731_DLO
20
19
18
17
15
16
PC176
0.01U_0603_25V7K~D
@
GNDA_CHGR
12
PC163
0.01U_0402_25V8K 5@
0_0603_5%~D
1 2
12
KC FBMA-L18-453215-900LMA90T _1812~D
1 2
KC FBMA-L18-453215-900LMA90T _1812~D
1 2
PR134
MAX8731_BSTB
12
PC131
PD12
2 1
0.1U_0603_25V7K~D
RB751V-40_SOD323~D
1 2
PR165 1_0805_5%~D
PR191
0_0402_5%~D@
1 2
12
PR192
100_0402_5%~D
12
PC161
100P_0402_50V8K 5@
3
PL19
1U_0603_10V6K~D
PR136
1 2
33_0603_1%~D
1U_0603_10V6K~D
PC158
MAX8731_CSIP
MAX8731_CSIN
+PBATT
+VCHGR
12
PC162
100P_0402_50V8K 5@
PC124
1 2
PC133
1 2
1 2
200P_0603_50V8J~D
2
3
+5V_ALW
ININ+
GNDA_CHGR
976K_0402_1%~D 5@
1 2
4
G
O
P
8
PC164
PC177
PR166
1
100P_0402_50V8K 5@
CHRG_IN
PQ28
12
3300PF_0402_50V7K~D
PQ30
PU12A
LM393DR_SO8~D 5@
12
SI4800BDY-T1_SO8~D
SI4810BDY_SO8~D
PC165
578
3 6
578
3 6
12
0.01U_0402_25V8K 5@
241
241
PQ29
2
PQ22
FDS6679Z_SO8~D5@
1
2
3 6
4
PQ24
SI4825DY_SO8~D4@
1
2
3 6
4
12
PR125
470K_0402_5%~D
578
SI4800BDY-T1_SO8~D
3 6
241
5.6U_CEP125NP-5R6M_8.8A_20%~D
+5V_ALW +3.3V_ALW
12
PR167
100K_0402_1%~D 5@
12
PC159
10P_0402_50V8J~D 5@
2
8
7
5
8
7
5
+DC_IN_SS
Change to 1206 size
12
PC125
2200P_0402_50V7K~D
PL20
1 2
12
PR168
100K_0402_5%~D 5@
13
D
2
G
S
PC126
+VCHGR_L
1
12
PC127
2
10U_1206_25VAK~D
0.1U_0805_50V7M~D
Place these CAPs
close to FETs
PR138
0.01_2512_1%~D
1
2
Maximum Battery Charge current = 6.2A
when system off, S3, S4.
ADAPT_OC <37>
PQ32
RHU002N06_SOT323 5@
DELL CONFIDENTIAL/PROPRIETARY
Title
Size Document Number Rev
Date: Sheet
1
+VCHGR
+5V_ALW
21
1
PC128
2
10U_1206_25VAK~D
4
3
12
PC134
0.1U_0805_50V7M~D
PD54
1SS355_SOD323~D
PR193
1K_0603_1%~D
1 2
1
1
PC136
PC135
2
2
10U_1206_25VAK~D
10U_1206_25VAK~D
Need double confirm
+5V_ALW
8
5
P
IN+
O
6
IN-
G
4
Compal Electronics, Inc.
Charger
1
7
PU12B
LM393DR_SO8~D 5@
+VCHGR
PC137
@
49 62Tuesday, December 13, 2005
1
2
10U_1206_25VAK~D
2.0
of
Page 50
5
4
Version Change List ( P. I. R. List )
3
2
1
Item Issue DescriptionDate
D D
1
2
3
4
5
6
7
8
C C
9
10
11
12
13
14
15
42 Rikers LED 06/22/2005 Dell Reserved LCM and Backlight circuit and depop on Rikers. X00
20 CRT 06/27/2005 Compal X00Added R967,R968,C923,C924
20 CRT
38 EMC5004 07/06/2005 Compal
37 ECE5018 07/06/2005 Compal +3VRUN leakage at AC mode in S5 Change R533 pull up from +3.3V_SRC to +3.3V_RUN
37 ECE5018 07/08/2005 Compal Pop R545Internal speaker no sound.
07 CPU
07
40
06
16
19 & 37
34 Added C925
Title
CPU
POWER
SEQUENCE
CLOCK
GENERATOR
Docking
Connector
Thermal
sensor
GFX CONN.
ECE5018
Owner
06/22/200537 SIO Compal BID change to X00. Pop R549, depop R553. X00
Depop Q104~Q107, R913~R918, C910, C920,
Buffers are duplicated on the video card, so added by pass
resistors on Discrete mode.
06/27/2005 Compal X00
Connected HSYNC and VSYNC to docking connector from the
output of U194 and U195.
Added a DIP switch for the Flash recovery
disable/enable function at develop phase.
07/11/2005
07/11/2005
07/11/2005
Dell
Dell
Dell
07/12/2005 Dell
Updated ITP pullup resistor values as
M07-discrete-A03 Ref. Sch.
Updated H_PROCHOT# pullup resistor values as
M07-discrete-A03 Ref. Sch.
Updated Power Good circuit as M07-discrete-A03 Ref. Sch.
Updated clock GEN. resistor values as
COE X04 Ref. Sch.
07/12/2005 Dell Update docking circuit as COE A03 ref. sch. Made R899,R900,R901,R902 no stuff.
07/12/2005 Dell Change R701 location.
07/12/2005
Dell
Change R701 so that C158 and C159 are between LDO_IN and
R701.
Dell07/12/2005MINI card No filtering on +3.3V_LAN
JLMLED and JKBLED.
Added SW1 and pop R591.
Added R622, R623 reserved for bypass SW1.
Change R81~R86, R77, R196 value.
Change R548 to 75 ohm.
Added R617, R619, R620, R621, Q51, Q52, Q53, Q64.
Change R36,R37,R43,R45,R49,R919,R33,R35 value to 15 ohm. X00
Change the net name of pin1 of U5 to SIO_GFX_ENFollow COE graphic card A05 ref. sch.
Solution Description Rev.Page#
X00
X00
X00
X00
X00
X00
X0036
X00
X00
X00
Request
16
B B
17
18
19
20
21
22
23
24
A A
07 CPU 07/12/2005 Dell Added pull down R969 for TEST1Per Intel checklist rev 1.3 and CRB rev 1.4
40
POWER
SEQUENCE
07/12/2005 Dell X00Added RUN_ENABLE off-page connectionFollow COE graphic card A05 ref. sch.
14 Calistoga-PWR 07/12/2005 Dell Per Intel checklist rev 1.3 and CRB rev 1.4 Added C926 and C927. X00
40
16
POWER
SEQUENCE
Thermal
sensor
33 R5C832 07/13/2005 Dell Added R976 and no stuff. X00
26 CODEC 07/13/2005 Dell
26 & 27
CODEC
Amplifier
27 Amplifier 07/13/2005 Dell
07/13/2005 Dell X00Follow COE UMA A07 and Core discrete A04 ref. sch. Added R970~R975, C928, Q118 and U40C.
07/13/2005 Dell Added 2.5V_RUN_PWRGD off-page connection on pin 31 of U4Follow COE UMA A07 and Core discrete A04 ref. sch. X00
May potentially have leakage current into R5C832.
07/13/2005 Dell
Change GPIO0 control to HP_NB_SENSE, internal EQ will be
controlled by codec jack sence.
Move PC BEEP circuit from CD inputs of codec to internal
speaker amplifier.
Add place holders for 47pF caps on positive inputs of
Connected HP_NB_SENSE to pin 21 of U188,
and added R977 no stuff.
C414 depop and change R381 value to 2.2K ohm. X00
Added C929,C930 no stuff.
speaker amplifier.
Change GPRS immunity caps to no stuff by default.
Signal removed to allow BEEP while headphones plugged in.
Depop C885,C886.
Remove Q29.
X00
X00
X00
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
Changed-List History
LA-2881P
50 62Tuesday, December 13, 2005
1
2.0
of
Page 51
5
4
Version Change List ( P. I. R. List )
3
2
1
Item Issue DescriptionDate
D D
25
26
27
28
29
30
31
32
C C
33
34
35
36
37
34 EXPRESS CARD 07/13/2005 Dell
24 ICH7-M 07/14/2005 Dell Depop C349, C350, C359.Follow COE ICH A03 ref. sch.
23 ICH7-M 07/14/2005 Dell Change R711 from 8.2K no stuff to 10K stuff.Follow COE ICH A03 ref. sch.
38 EMC5004 07/14/2005 Dell Swapped ITP_DBRESET# and RUN_ON_D.ITP_DBRESET# not on wake pin.
37 ECE5018 07/14/2005 Dell SPDIF_SHDN at the codec is +5V. X00Connected SPDIF_SHDN to pin 76 of U36.
37 ECE5018 07/14/2005 Dell Follow COE Latitude EC A02 ref. sch. Added GPIOs AC_OFF and LOM_CABLE_DETECT.
37 ECE5018 07/14/2005 Dell Missing series resistor on Xtal.
3 Index 07/14/2005 Compal Update PCI table. X00
16 07/14/2005 Dell Change decoupling for VDD_5V Swap location of C160 and C161. X00
37 ECE5018 07/15/2005 Dell X00Removed level shift circuit. Delete R546, R547, Q42
40 07/15/2005 Dell
39/41/42 TP LED Will use tri-color TP LED on Rikers.
Title
Thermal
sensor
POWER
SEQUENCE
07/13/200533 1394
07/15/2005
Owner
Dell
Dell
Reserved common mode chokes for EMI and added 0 ohm
resistors to bypass 1394 signals for cost saving.
Reserved common mode chokes for EMI and added 0 ohm
resistors to bypass USB signals for cost saving.
Added R978~R981 and L90, L91 depop. X00
Added R982, R983 and L92 depop.
Added R988, Q121 and no stuff.Add +2.5V_RUN bleed of ckt as UMA A07 schematic.
Added R985,R986,R987,Q119,Q120.
Remove LCM circuit and connected TP LED control signal.
Connected the pin 1 of R645 to +5V_ALW and pin 1 of R644
38
40
39
B B
40
41
42
43
44
POWER
CONTROL
Calistoga13
07/15/2005
07/19/2005LOM/ECE501830/37
Dell
Compal07/19/2005 Changed R168, R169, R182, R183. X00
Dell Added R228 (5@) X00
Dell07/19/2005LOM30 Added R231 (4@)
Follow COE UMA A07 ref. schematic.
Changed resistor package from 0402 to 0603 for
Increasing VCCD_LVDS Power Rating.
5752M Hooks not in place. Need to connect Pin C04 (Energy
Detect to pin 75 GPIOC1 of the champion chip)
LOM_LOW_PWR signal must be connected to 4401 Export#
signal also.
Rename +3V_PHY to +3VRUN_PHY per ref schematic.Dell07/19/2005R5C83233 Changed Net Name X00
Dell07/19/2005R5C83233 Deleted R487, R488, R489. X00
UDIO3, UDIO4, XDEN, MSEN pins can be pulled up to
+3V_R5C832 through a single 10k resistor.
Rename +XD_VCC to +3VRUN_XD per ref schematicDell07/19/2005R5C83233 Changed Net Name X00
to +15V_SUS.
R646,R647 no stuff and change R644 value to 100K.
Solution Description Rev.Page#
X00
X00
X00
X00
X00
X00Added R984.
X00
X00
X00
X00
Request
45
46
Dell07/19/2005R5C83233 Added R501 X00
150k-ohm pull-down to GND is needed on +VCC_5IN1 for media
card detection per Ricoh. This is R21 on M07 ref schematic
X00Rename +VCC_5IN1 to +3VRUN_CARD per ref schematicDell07/19/2005R5C83233 Changed Net Name
Rename H_PROCHOT# to CPU_PROCHOT# on page 7. Rename
47
A A
Dell07/20/2005CPU/ECE50187/37 X00
H_PROCHOT# to IMVP6_PROCHOT# on page 49, and route to
ECE5018 pin 77. Add 100k ohm pull-up on IMPV6_PROCHOT# to
+3.3V_RUN on page 37. Rename PROCHOT_SIO# (page 37) to
Added R60 (100K Pull Up).
CPU_PROCHOT# and route to cpu pin D21 (leave pull-up)
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
Changed-List History
LA-2881P
51 62Tuesday, December 13, 2005
1
2.0
of
Page 52
5
4
Version Change List ( P. I. R. List )
3
2
1
Item Issue DescriptionDate
D D
48
49
50
51
52
53
54
55
C C
56
57
58
59
60
61
62
63
B B
64
65
66
67
68
69
70
71
A A
72
23 ICH7M 07/20/2005 Dell Moved R365 to left of R713SPI pullup location doesn't match DG (M07_ICH7_A04)
23 Renamed GPIO12 to RSVD_HDD_DET#Dell07/20/2005ICH7M HDD_DET# not needed (M07_ICH7_A04) X00
26 CODEC 07/20/2005
37 ECE5018 07/21/2005 Dell Media button LED always ON issue. X00Connected M_LED_BK to pin 1 of U36.
22 ICH7M 07/21/2005 Dell
23
23
23
24 ICH7M 07/21/2005 Dell Per ICH M07 Ref Schematics Rev A04. Add R991,R992 and pop C534,C362. X00
33 1394 07/22/2005 Compal X00
16
24 ICH7M 07/24/2005
Title
07/20/2005ICH7M
07/20/2005 Dell33 R5C832 U26 changed to AAT4250 X00
DOCK36 DOCK can't be enabled
07/20/2005 X00
Owner
Dell
Change SATAGP[0-3] to pullup as M07_ICH7_A04 CoE Ref
Schematic
Power switch follows up the recommended switch in ref
schematic. Use the AAT4250
Deleted R345, R961~R966.Dell23 X00
Changed DOCK pin 238 connection to ICH7M
PCI_REQ0# directly from PCI Buffer (U31).
Dell X00Remove C414.Follow COE AUDIO A03 ref.sch.
07/21/2005CLOCK6 X00Changed C7
ECE501837 Dell
07/21/2005 X00Changed connection
Dell
07/21/2005ICH7M
ICH7M R711 tied to +3V_SUS.
ICH7M
ICH7M
07/21/2005
07/21/2005
07/21/2005
Dell
Dell
Dell
DellECE501837
DellECE501837
Thermal
sensor
07/23/2005 Dell
Calistoga 07/23/200513 Dell X00Add note to place C100/C99/C96 close to pin AB1/D2/A6.
Dell
07/24/2005 Populated R140.
Dell10 Calistoga
Item Id: CR03833
Title: Change 0.1uF cap to 10uF cap
Need to move the NB_MUTE GPIO to C7 ( pin 73 ). The original
GPIO CANNOT be programmed to drive.( SMSC Silicon issue)
Per the ICH reference schematic A04, need to move the
pull-up on ICH_EC_SPI_DO to the other side of R713.
ICH_INTVRMEN is missing the NP 0 ohm pulldown at pin 2
of R323.
R365 has been moved to the left of R713Dell23 X00
Add R989 no stuff.
LAMP_STAT# pullup resistor should be tied to +3V_SUS.
Per ICH M07 Ref Schematics Rev A04.
SIO_EXT_WAKE needs a 0 ohm series resistor at the
ICH Pin AC21.
Per ICH M07 Ref Schematics Rev A04Dell07/21/200525 CD-ROM
Changed R358 value to 680 ohms.
Add R990.
Changed R375 value to 510 ohms and JMOD name to JODD.
Change the JMOD pin 37 name to IDE_LED#
SYS_PME# is pulled up to 3VRUN. It is pulled up to 3VALW
in the M07 EC Ref Schematics Rev. A02
SIO_GFX_EN is named differently from the Ref Schematics. It
is named SIO_GFX_PWR in the M07 EC Ref Schematics Rev. A02
For 1394 TPB0+ and TPB0- layout routing smooth.
EC debug requirement for design phase, will be removed
after MP.
Follow GuardianII X03 reference schematics. X00
Swap L91, R980 and R981.
Pop JDEBG1 connector.38 EMC5004 07/22/2005 Compal
Add a note to U4 that states "Solder thermal pad
to plane. Add 9 ground vias to pad."
Per the UMA reference schematic A07.
C341 should be 330uF. It is currently 220uF. Per ICH M07
Ref Schematics Rev A04. (Item Id: DF04040)
Change C341 value to 330uF. X00
Need to POP R140 to enable testing C4
Latency.(Item Id: DF04038)
Solution Description Rev.Page#
X00
X00
X00
X00
X00
X00
X0007/22/2005 Changed R533 pulled up[ to +3.3V_ALW.
X00Changed Netname.07/22/2005
X00
X00
X01All Pages 08/02/2005 CompalN/A Renamed all parts Reference All Parts but Connector
Request
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
Changed-List History
LA-2881P
52 62Tuesday, December 13, 2005
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2.0
of
Page 53
5
4
Version Change List ( P. I. R. List )
3
2
1
Item Issue DescriptionDate
D D
73
74
75
76
08/03/2005
08/03/200517/18 X01
Owner
Avoid running clk_pci_lan throun RN8 as Layout
Issues list request.
Dell08/02/2005 Changed BID
Add 0.1uF cap to +CK_VDD_MAIN so that each VDD pin has
a cap (CoE CLOCK Ref Sch X05)
Connected pin 50 of DIMMA to pin 50 of DIMMB and named net
DellMemory
PM_EXTTS#0_R. Remove No Stuff attribute from R118(Old Ref
R213).Delete R118(Old Ref R218), 0 ohm, and connection to
Changed R221, R211 as @.
Changed R220, R212 as pop.
Deleted R117(Old Ref R218).
Populated R118(Old Ref R213)
PM_EXTTS#1. (CoE Memory Ref X03)
77
08/03/2005
Removed pull-up at LDO_POK. Pullup is on power
sequence.(CoE Guardian II Ref X04)
78
79
C C
80
81
82
83
20
LVDS/ TV_OUT/
CRT
08/03/2005ICH7M21
08/03/2005
ATF_INT# pullup should be +3.3V_SUS(CoE Latitude EC Ref
A03)
Dell08/03/2005GMCH10
Dell08/04/2005
Remove PM_EXTS#1 connection options to the SODIMM. Use
this to implement C4E implementaion Only(CoE UMA Ref A08)
Item Id: CR03751
Title: Add note to place 0-ohm resistors close to buffer
84
85
86
87
B B
88
89
90
91
92
93
94
A A
95
7 Yonah 08/08/2005 Dell X01
Dell08/12/2005R5C83233 X01
Dell08/12/2005R5C83233 X01
Dell08/12/2005AUDIO/SIO26/37 X01
26/27/28
AUDIO/
Amplifier
Dell X0108/12/2005
Dell08/12/2005GMCH12
Dell08/12/2005GMCH/Power19/20/40
Dell08/12/2005LVDS20
Dell08/12/2005Power40
5
Change 22uF Caps from X5R to X6S
Updated the electrical countermeasure circuit for the MS
Duo Adapter short issue (CoE 1394 Ref A06)
Changed part for the common mode choke since the proper
impedance for 1394 is 110 to 200-ohms(CoE 1394 Ref A06)
Add GPIO to control internal speaker mute when docked and
HP plugged in.
Add EAPD signal back in for future power savings
opportunities. Default NP. Added EAPD to GPIO3, also
2N7002 control to speaker and sub shutdown pins. A04
NO STUFF Resistor for the CFG11 (CoE Ref Sch.
945PM_GM_M07_A00)
Changed net name INV_PWRSRC to GFX_PWR_SRC (CoE
CRT_LVDS_SVIDEO M07_A00)
Adding SVIDEO with SPDIF option Note (CoE
CRT_LVDS_SVIDEO M07_A00)
Added Power Down Ckt (CoE M07
System POWER SEQUENCE A01)
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
4
3
Changed C4, C5, C7, C8, C10~C13, C15~C18, C662~C664,
C658, C668~C675, C677, C678, C681, C682, C686~C689
Added D22, R117.
Changed Q76 to P MOSFET.
Changed L90, L91 to DLW21N121SQ2 as nopop.
Added DOCK_HP_MUTE# signal and 100K pullup (R701).
Added Q104, Q105 as Nopop.
Solution Description Rev.Page# Title
X016/31 CLOCK/LOM 08/02/2005 Dell Changed R206 as 4@. Changed CLK_PCI_LAN connection.
X01SIO37
X01Added C699.DellCLOCK6
X01Deleted R47(Old Ref R227)DellGuardian II16
X01Added R737Add voltage margin circuit(CoE Guardian II Ref X04)Dell08/03/2005Guardian II16
X01Added R738~R743. C700, C701, Q102, Q103.Add additional thermistor circuit(CoE Guardian II Ref X04)Dell08/03/2005Guardian II16
X01Unpoped C46 (Old ref C892)Component not required.(CoE Latitude EC Ref A03)Dell
X01Change R616(Old ref R570) pullup to +3.3V_SUS.DellKBC38
X01Deleted R701(Old ref R139)
X01Added Note.
X01Added +3V_ALW BlockCompalPower Rails4 Update Power Rails08/08/2005
X01Modified +3V_ALW instead of +3.3V_SRCCompal Update SMBUS Pull-Up Power Rail08/08/2005SMBUS4
X01Depopulated R735 as CoE Ref Schematic.Update ITP port resistor pop option.Compal08/08/2005Yonah77
X01Nopop R678
X01Changed Netname +G_PWR_SRC to +GFX_PWR_SRC
X01Added Note
X01Changed R170, R558 to 20K as Populated
DELL CONFIDENTIAL/PROPRIETARY
Title
Size Document Number Rev
2
Date: Sheet
Compal Electronics, Inc.
Changed-List History
LA-2881P
53 62Tuesday, December 13, 2005
1
2.0
of
Request
Page 54
5
4
Version Change List ( P. I. R. List )
3
2
1
Item Issue DescriptionDate
D D
96
97
98
99
100
101
102
103
C C
104
105
106
107
108
109
110
111
B B
112
113
114
115
116
117
118
119
A A
120
40
20 LVDS 08/15/2005 Dell
10/12 Calistoga 08/16/2005 Dell X01Adding notes for discrete implementation and depop R683.Follow CoE Core/945PM_GM_M07_A01 schematic.
29 USB 08/16/2005 Dell 10uF caps at USB switches are optional. X01Depop C554, C217 and C680.
23 ICH 08/16/2005 Dell
16
Thermal
sensor
08/16/2005 Dell
37 ECE5018 X01Added HP_NB_SENSE back to pin 82 of U36.
40
Power
Sequence
GMCH10
2
23/29/37
Block
Diagram
USB Swapped the ICH USB port0 and port5.
08/23/2005
08/23/2005 Compal
38 EMC5004 08/24/2005 Dell
23 ICH 08/24/2005
33 X0108/24/20054-in-1
10/40
GMCH/Power
Sequence
5
08/24/2005
Owner
Patch for the Yonah ICCP issue
(CoE M07 System POWER SEQUENCE A01)
Support M07 inverter on ZUMA.
Duplicate pull down on PANEL_BKEN.
SIO_EXT_SCI and SIO_EXT_SMI# causing leakage to +3.3V_RUN
on S3 mode.
Follow D05, ALWON is driven high and pull up is on
VR reference design.
Add new GPIOs(CoE Latitude EC ref A04)Dell08/16/2005
Dell08/20/2005
Dell08/20/2005
Dell08/20/2005
Dell08/20/2005GMCH10
Dell08/20/2005GMCH10
Dell08/20/2005ECE501837
Change disable fet to lower Vgs. Corrects circuit
issues(CoE M07_MDC_A03)
Adding Clamp Ckt for 1.8VSUS, 3.3VUS and 5VSUS X01
Delete 40.2ohm pull down resistors for M_OCDOCMP0/1 and
replace them with Test Points. Per Intel DG 1.0(CoE 945_a02)
Add 0.1 uf (402) for the DDR VREF at Calistoge for better
noise immunity (CoE 945_a02)
Remove H_DPRSTP# and H_DPSLP#. Previously they
No Stuff. Per Intel (CoE yonah_m07_a01)
NB_MUTE Pull down Resistor Reserved as Nopop as CoE Ref
Sch (EC_A03).
Update Lead Free Layout Library.Compal08/22/20054-in-1/LED33/41/42
Dell X01
LAMP_STAT# causing leakage to +3.3V_RUN and +5V_RUN
on S3 mode.
FWP# should be pulled high for development and pulled down
for production.
Dell
Dell
Dell
Dell
Dell
Dell
DellICH7M23
BITS item ID: CR05958
Change value of SPI pull-ups.
Adding bypass MS Duo short circuits in the event that the
connector would be corrected
TeamTrack: BITS Item Id: CR06800
Title: Calistoga Filter Issues page 13
TeamTrack: BITS Item Id: DF06790
Title: Power Sequence Circuit, and C4-E and SPDIF Issues
TeamTrack: Item Id: DF06789
Title: BIA_PWM for UMA need to add AND GATE
TeamTrack: Item Id: CR05951
Title: Move C535 to other side of R584
TeamTrack: Item Id: CR05955
Title: Depop pull-up on SIO_THRM#
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
4
3
Changed R476, R477, R483, R484 to 0 ohm as Populated.
Added R744 as populated.
Changed pull up power rail from +3.3V_RUN to +3.3V_SUS. X01
Added R47, R745, R746, Q106~Q108. Deleted R171, R188.
Changed bleed resistors from 22 to 30 ohm.
Updated U29, Q76, Q5, Q3, Q1, Q73, Q74, Q70, Q29,
Q27, Q34, Q49, Q46, Q50, Q36, Q12, Q64, Q66.
Change pop option for FWP# for development
and production.
Added R747~R750 as no pop (@).
Added R751, R752, C703, C704.
Populated R302, R307, Q54, Q53, R306, R301,
Q56, Q57, R683. Depoped R623.
Solution Description Rev.Page# Title
X01Power 08/12/2005 Dell
X01Depop D7, U10 and pop R152, R133.
X01Depop R702.
X01Q61 changed to BSS138.MDC28
X01Deleted R663, R682. Added T24, T25.
X01Added C702 and pop C146.
X01Deleted R720, R724.
X01Depoped R573.
X01Update LOM 4401E from PCIe to PCI BusDell08/20/2005
X01
X01Depoped R554.23 ICH
X01
X01Change R537, R538, R542 value from 1K to 10K ohms.
X0108/24/2005GMCH13
X01
X01Added U49, C705, C706.08/24/2005LVDS20
X01Moved C535.08/24/2005ICH7M22
X01Depoped R598.08/24/2005
DELL CONFIDENTIAL/PROPRIETARY
Title
Size Document Number Rev
2
Date: Sheet
Compal Electronics, Inc.
Changed-List History
LA-2881P
54 62Tuesday, December 13, 2005
1
2.0
of
Request
Page 55
5
4
Version Change List ( P. I. R. List )
3
2
1
Item Issue DescriptionDate
121
D D
23/30/34 ICH7M/PCIe 08/24/2005 Dell BITS CR05959: Rename PCI-E nets Renamed PCI-E Nets.
122
123
13 GMCH 08/26/2005 Added C707, C708. Deleted R665, R679, R671, R675.Dell
ICH7M/SATA22/25 Dell08/24/2005 Renamed SATA Rx/Tx Nets.BITS CR05950: Rename SATA Rx / Tx lanes X01
Owner
TeamTrack: BITS Item Id: CR06800
Title: Calistoga Filter Issues page 13
It is part of the Intel Filter ckt, for now you could
124
Dell08/26/2005GMCH13
place 0 ohm 805 package. The key is to reserve a placement
for this component, in case you got an issue with your
Changed Value of R751, R752 to 0 ohm.
platform that related to this power rail noise. "
125
126
127
128
C C
129
130
4 X01
7 CPU 08/26/2005 Dell X01Chnage R714 to 1K, R723 to 51ohm.Per Intel DG rev 1.0 and M07 Ref Schematic.
39 08/26/2005 Compal Swapped JTP pin1 and pin2.For TP cable is compatible with Sullivan. X01Touch Pad
12
5
131
132
133
1 Dell08/29/2005 X01Cover page
20 SPDIF 08/30/2005 Dell X01Removed L29.Remove the transformer for SPDIF ckt.
134
135
20/43 TV_OUT 08/30/2005 Dell X01
136
B B
GMCH13 X01
08/29/2005 Dell X01Removed R631.PANEL_BKEN has twice pull down.Calistoga
SMBus
Topology
ECE5018
EMC5004
08/29/2005 Compal Update SMBus Diagram. X01
08/29/2005 Dell
CRT
Dell08/26/2005
Dell08/31/2005Guardian II16 X01Populated C410.
137
138
139
140
141
142
143
144
A A
30 LOM 08/31/2005 Dell X01
34/38
12/20
39 LED
MINI card
EMC5004
Calistoga
LVDS CONN
Guardian II16
09/02/2005 Dell
09/02/2005
09/02/2005
09/02/2005
Dell
Dell
Dell
33 09/05/2005 Dell X01Change R487 value from 10K to 100K.BITS DF20288: CoE5 Design review feedback from Arin Lin.R5C832
30/43 LOM 09/05/2005 Dell
Updated the schematic notes for the MS-Duo Adapter
Countermeasure Circuit.
Added +2.5V_RUN Rail DiagramCompal08/26/2005Power Rails
Media direct button don't power on the system for Suva.37/38
Add 6@ for Suva used only and 7@ for Zanzibar/ZUMA/Rikers
used only.
Added 39 ohm series resistors at HSYNC and VSYNC
after the Buffer.
Modified TV OUT filters for resolution support.
BITS CR20056: This is to address a D05 acoustic
noise issue on the 5V Run rail.
BITS CR20058: The comms teams recommedns that R507 and
R522 be de-populated for all configurations.
BITS CR07184 and CR07190
Include support for ST-Micro Flash M45PE20 for the 5752 LOM
Debug Signals Routed to WLAN mCard connector.
Updated backlight control circuit.
Resistors package change for temperature/voltage
margining test.
BITS: CR03757
Updated bluetooth control circuit.
BITS CR20884:Based on IEEE testing, need to update RDAC
value. This is ONLY for Zanzibar/Zuma using 4401E LOM.
Add R754 for Zanzibar/ZUMA/Rikers only and R753 for Suva
only.
Added R755 and R756.
Added C709~C711 no stuff. C414,C417,C422,C413,C416,C421
pop 47P for discrete and 82P for UMA.
Depopulated R507, R522.
Added U50 and depop U24, R505.
Added R757 nopop and pop R407, R509 for Rikers/Suva.
Route HOST_DEBUG_TX/HOST_DEBUG_TX/8051TX/8051RX/ to
JMINI pin16/17/19/42.
Moved U49 and C705 to page 12.
Pop R152 for UMA only.
Change R737 and R703 from 0402 to 0603.
Added Q109.
Change R515 value from 1.27K 1% ohm to 1.24K 1% ohm.
This change is for Zanzibar/ZUMA 4401E LOM only.
Solution Description Rev.Page# Title
X01
X01
X01
X01
X01Dell08/30/200520
X01Dell08/31/2005LOM30
X01
X01
X01
X01
X01
Request
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
Changed-List History
LA-2881P
55 62Tuesday, December 13, 2005
1
2.0
of
Page 56
5
4
Version Change List ( P. I. R. List )
3
2
1
Item Issue DescriptionDate
145
D D
6/30/33
146
5/38 09/07/2005 CompalSMBUS X01Fine tune SMBus pull-up resistors value. Change R177/R182/R216/R217/R592/R599 value to 2.2K.
147
43 Config.table 09/09/2005 Compal Nopop R612 on ZUMA and Zanzibar. X0 14401E don't support TPM function.
148
149
40
150
37 09/23/2005 Dell Board ID change. Pop R221, depop R212. X02ECE5018
3/23/
151
28/36
3/23/
152
34/37
153
C C
38
154
155
156
157
20 CRT 10/15/2005 Dell X02Change D17 to RB500.
158
40
159
13 Calistoga 10/15/2005 Dell
160
161
B B
A A
13
162
34 Minicard 10/15/2005 Dell
163
23 ICH7-M 10/15/2005 Dell Follow COE ref. sch. ICH7_A06.
164
30 LOM Compal Change Q59 from BCP69 to MBT352000MT1G.
165
38 EMC5004 10/17/2005 Dell
166
37/38
167
37
168
38
169
32
CLOCK/LOM
/R5C832
TV_OUT/CRT
Power
control
09/16/2005 Dell X01Pop R47 and Q106.Poplated +1.8V_SUS clamp circuit.
USB 09/29/2005 Dell Added 0 ohm pop option for BT port
USB 10/11/2005 Dell Added 0 ohm pop option for express card.
EMC5004 10/14/2005
ECE501837 10/14/2005
10/15/2005 DellEMC500438
Power
sequence
10/15/2005 Dell
10/15/2005 DellR5C83233
Calistoga 10/15/2005 Dell
10/15/2005 Per broadcom ref. schematic.
EMC5004
ECE5018
10/18/2005 Dell Added R779, R781.
ECE5018 10/18/2005 Dell Added D24 and R780 depoplated.
EMC5004 10/18/2005 Dell
LAN
Transfomer
10/19/2005 Dell
Owner
Compal09/06/2005
Crystal circuit evaluation.
TV out filter circuit and termination changes for graphics.Dell
Compal
Compal X02
Compal10/15/2005Rikers LED39/41 X02Remove page 42 and update intersheet references.
only, will remove for MP.
We can read system debug code from JDEBG2, so depop serial
port inverter for cost saving.
Backlite Keyboard will not be supported and TP will only
support single color LED on Rikers.
BITS item ID: CR29479
The MEC5004 boot block needs to be write protected.
BITS item ID CR29469 : Per the VESA requitrement,change the
VCC CRT diode to RB500 rated at Io = 100 mA Max.
BITS item ID: CR29440
These are causing backdrive issue.
BITS item ID: CR29472
R751,R752 are not needed, replace these resistors by copper
BITS item ID: DF20275
Follow Ricoh and M07 ref. schematic.
Follow COE ref. sch. M07_minicard_A06 to remove resistors
on COEX1_BT_ACTIVE and COEX2_WLAN_ACTIVE.
Added a work around proposed by SMSC for the flash
corruption issue.
Added pull up resistors to +RTC_CELL on INSTANT_ON_R1# and
INSTANT_ON_R2# for Rikers/Suva.
Fixed a potential backdrive issue on the WLAN_RADIO_DIS#
signal when we start doing Wake on WLAN.
SMSC work around proposed for the flash
corruption issue.
BITS DF06679:IEEE Return loss failures on Gig and 100 with
Transpower DDOCK,these changes are just for Rikers/Suva only
Change C313,C314 value to 22pF and R199,R486 value to
220 ohm.
R410 pop 750 ohm for 4401E, 470 ohm for 5752.
Change R497,R503,R504,R17,R22,R26 value to 150 ohm.
Change R755 and R756 from 39 ohm to 33 ohm.
Useing ICH7-M port 7 for BT on Zanzibar/ZUMA.
Added R758~R765.
Useing ICH7-M port 0 for express card on Zanzibar/ZUMA.
Added R766~R773.
Remove SW1, R551, R552 and depop R555.Dip switch and JDEBG1connector are for development debug
Depop JDEBG1.
Depop U41.
Deopulated R302, R307, Q54, Q53, R306, R301,
Q56,Q57.
Remove R483.
Removed R409 and R411. X02
Moved LAMP_STAT# pull up resistor from +3.3V_SUS
to +3.3V_RUN and pop R554.
Added D23,Q110,Q111,C712,R774~R778.
Added R782 connected TEST_PIN to GND.Change C219 value
to 22uF and 0805 package for REV C parts.
Change R359,R360,R364,R366,R371,R374,R375,R382 to 48.7_1%
ohm and L16~L20,L23~L25 to 36nH for Rikers/Suva only.
Solution Description Rev.Page# Title
X01
X0109/13/200520/43
X02
X02
X02
X02Pop R600 and depop R601.
X02
X02Remove R751, R752.
X02
X02Follow COE ref. sch. 945PM_GM_PM_M07_A04 Added notes for 3GPLL and 1.5V PCI-E power rails.
X02
X02
X02
X02
X02
X02
X02
Request
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
Changed-List History
LA-2881P
56 62Tuesday, December 13, 2005
1
2.0
of
Page 57
5
4
Version Change List ( P. I. R. List )
3
2
1
Item Issue DescriptionDate
170
D D
40
171
23
172
19
173
20 CRT 10/21/2005 Dell Poplated CRT HSYNC and VSYNC buffer on discrete mode. X02
3/23/
174
28/34
175
16 Thermal 10/26/2005 Dell Follow COE M07_GUARDIANII_X05 ref. schematic. X02
176
177
178
C C
27 Amplifier 11/01/2005 Dell X02
179
28 Subwoofer
Power
sequence
ICH
DVI
10/19/2005 Dell X02
10/20/2005
10/20/2005
USB 10/24/2005 Dell Using the same USB mapping for Zuma,Zanzibar,Riker,and Suva X02Update USB pop options.
Thermal
5-in1 10/28/2005 Dell
11/01/2005
Owner
5V_3V_RUN_PWRGD ckt values update to minimize
the leakage current.
Dell
Dell Reserved a 0805 pad for DVI safety issue.
Dell
Added 0.1uF cap as a short-term solution for IMVP_PWRGD
glitch issue.
BITS item ID: CR20057
Change layout note for VCP thermistors
BITS item ID: DF20280 Layout for pins FIL0/REXT/VREF -the ref designators need to be updated
Set gain of TPA60017A2 to 21.6dB
Set gain of MAX9713 to 22 dB.
Change R302/R307 to 200K ohm, R301/R306 to 4.7K ohm.
Change pop options on U4,U5,C653,C656,R41,R42,R38,
R755,R756,R713,R707.
Change R489,R490 to 120K and R488 to 78.7K 1%.
Change C400,C694 to 22U and C412 to 0.22U.
Updated Note. X02Dell10/28/200516
Updated Note. X0233
Populate R449 and depop R453.
Populate R693 and depop R698.
Change R685 to 0 ohm and C369, C343 from 0.015uF to
180
27/28 AUDIO Depop C632 and change C383,C384 to 1U_10V_X5R.
11/01/2005
Dell
Audio filter fine tune.
0.012uF.
Change C620 from 0.056uF to 0.033uF.
181
38 X02EMC5004 11/11/2005 Dell Depop SMSC work around proposed on EMC5004 revision D chip
182
37 ECE5018 11/12/2005 Dell
183
19 DVI 11/12/2005 Dell A00Change 0 ohm(R783) to RB500V(D25).To fix the overloading test failed issue on DVI port.
184
23 ICH
B B
185
40
POWER
SEQUENCE
11/12/2005
11/12/2005
Dell
Dell
Board ID change to A00.
Follow COE ref. schematic ICH7_A07.
HDDC_EN# and MODC_EN# floats at initial power up.
Follow COE ref. schematic system power sequence_A05.
Added +3.3V_RUN delay RC CKT to fix IMVP_PWRGD glitch issue
Added diode bleed off for +3.3V_RUN GFX power down sequence
adjustment.
186
187
16 Thermal 11/22/2005 Dell A00
188
23 11/22/2005 Dell
189
26/27 AUDIO 11/22/2005 Dell M07 cap change recommendations for audio. A00
190
39 LED 11/22/2005 Dell Follow COE ref. schematic bluetooth_A06. A00Change Q30 from PMBT3904 to BSS138.
191
23/28/34 USB 11/24/2005 Dell A00
192
A A
28 Subwoofer 11/24/2005 Dell A00
POWER
SEQUENCE
ICH
Compal11/12/200540
BITS item ID: CR20057
Change layout note for VCP thermistors
BITS item ID: CR05952
Change schematic notes on page 23.
Since BIOS can fix bluetooth and express card issue on ST
build. Remove 0 ohm pop options resistors for cost saving.
Depop R774~R778, C712, Q110, Q111 and D23.
Change C219 from 22uF to 4.7uF
Depop R221, R220, R210.
Pop R211, R212, R219.
Added R783 and R784.
Added R785 and D26.
Change C81 from 0.01U to 4700P and C85 from
0.022U to 470P.
Updated Note.
Updated Note. A00
Change C390,C395,C396,C362,C381,C382,C379 from Y5V to
X5R and C363,C374,C380 from Y5V to X7R.
Remove R758~R773.
Change C69 value from 0.22uF to 0.47uF.Improveing the "BO, BO" sound in DOS after system post.
Solution Description Rev.Page# Title
X02Added C713.
X02Added R783.
X02
X02
A00
A00
A00
A00Added clamp ckt for +5V_RUN. Added R786 and Q112 but no stuff.
Request
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
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Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
Changed-List History
LA-2881P
57 62Tuesday, December 13, 2005
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Version Change List ( P. I. R. List )
3
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Item Issue DescriptionDate
193
D D
23 ICH 12/01/2005 Dell A00To fix HDD parking sound issue when system warm boot. R783 and R784 no stuff.
194
33 R5C832-1394 12/01/2005 Dell A00
195
39 A00Change Q30 from BSS138 to PMBT3904.Dell12/02/2005LED
196
20 CRT 12/05/2005 Dell A00Change R755 and R756 value from 33 ohm to 0 ohm.H&V SYNC rise/fall times improvement.
Owner
Since the AAT4250 doesn't provide current
limited capablility.
Per Bo's requirement, keep original circuit that the same
as ST build.
Change U29 from AAT4250IGV-T1 to G5240B1T1U.
Change Vcore MLCC CAPs from 22uf *32pcs to 10uf * 32pcs;
197
9 CPU Bypass 12/05/2005 Dell A00
These changes improved buzzing noise.
change output SP caps from 330u/ 7mohms * 6pcs
to 330u/ 6mohms *4pcs.
198
33 R5C832-1394 12/13/2005 Dell
199
37 ECE5018 12/02/2005 Board ID change. A01Pop R221 and depop R212.Dell
C C
Solution Description Rev.Page# Title
A00Change G5240B1T1U U29 go back to AAT4250IGV-T1.The curent switch G5240B1T1U is not on Dell PSL.
Request
B B
A A
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
Changed-List History
LA-2881P
58 62Tuesday, December 13, 2005
1
2.0
of
Page 59
5
4
Version Change List ( P. I. R. List ) for Power Circuit
3
2
1
Request
TitleItem Issue DescriptionDate
1 Charger 06/20/2005 Compal M00P50 Schematic issue on Charger: The RC filiter should be connected
D D
2
3
ChargerP50 06/20/2005 Compal Add 1 ohm_0402, 200pf RC filter to Charger LX pin as shown
P46
+3.3V/+5V/+15V
P47
+1.5VRUNP /+VCCP_1P05VP
P48
+1.8VSUSP/ +0.9V_DDR_VT
06/22/2005 Compal Voltage margining test. X00
Owner
on Charger LX Pin, not L-S gate Pin.
in attached schematic.
Change PR165 f r o m 1 ohm to 0 ohm
No POP PC158 200pF.
PC158 200pF_0603.
Reserve PR17 5 , P R 17 6 , P R1 7 7 , PR178 and PR79 for voltage
margining test.
4 +DCINP44 07/04/2005 Dell Under power Adapter disable. Add PQ35, P Q 2 6 an d PR180 (No pop). X00
P50 Charger 07/04/2005 Dell Need capability for controlling the Adapter input. Add PQ 3 8 (No pop). X00
5
P46 +3.3V/+5V/+15V 07/06/2005 Dell Return to original due to SMSC EC issue already be fixed. Add PQ39, P U 1 6, P C 1 71 and PR181 (No POP)
6
P44
7
C C
8
9
10
+DCIN
P45
Battery Conn
P50
Charger
P49 +VCC_CORE 07/06/2005 Dell Follow Coe ref sch: change to A02.
+VCC_COREP49
07/06/2005+1.8VSUSP/ +0.9V_DDR_VTP48 Follow Coe ref sch: change to A02 Change ne t n a me f r o m + 0 . 9 V_PWRGD to 0.9V_DDR_PWRGD. X00
Dell
Rename pull high net from +3.3V_SRC to +3.3V_ALW.Dell07/06/2005
Delete PR162 , P C 1 57, PU14 and PR164.
PR1-Pin2, PR1 1- P I N1 , B at ter y E SD diode, PC30-Pin1 and PR168-Pin1. X0 0
Change PR77-P in 2 n et fr om +PWR_SRC to +CPU_PWR_SRC
Change PR87 f r o m 150k to 147k.
Change PR100 f ro m 0 to 499 for Intel require
Add PR182, No POP PR102 for POP option for PU5-Pin15 PG.
Change net nam e f ro m P GD_IN to 1.05V_RUN_PWRGD
No Pop PH1 and PR88
Change RC phas e n od e t o C sn ubber, delete PR80, PR98 and PR118
Change PC93, PC103 and PC120 from 0.01u to 1500pF.
Solution Description Rev.Page#
X00PR165 1 ohm_0805
X00
X00
X0007/06/2005 Dell Follow Coe ref sch: change to A03.
11
B B
13
14
15
16
17
18
19
A A
20
P47 +1.5VRUNP /+VCCP_1P05VP 07/06/2005 Dell Fo llow Coe ref sch: change to A02
Need independent PGs and update Layout notes.
07/20/2005 Dell ILIM5 set point is too high for 6.5A OCP. Chang e P R2 5 to 69.8K.+3.3V/+5V/+15VP46
07/20/2005 Dell ILIM3 set point is too high for 6.9A OCP. Change PR26 to 82.5K.P46 +3.3V/+5V/+15V
P50 Charger Dell It is recommended to connect the ground pins of the following
07/20/2005
analog components with a separate analog ground:
P48 +1.8VSUSP/ +0.9V_DDR_VT Dell Update 1.8V output notes Modified 1.8V : M in OC P= 12.7A, not design current.07/20/2005 X00
P48 +1.8VSUSP/ +0.9V_DDR_VT Dell PC69 need change to 0603 size. Change PC69 to 0.1uF _25 V_ 0603 from 0.1uF_50V_0805.07/20/2005 X00
ChargerP50 07/20/2005 Dell Two 10uF 1210 caps are recommended for input ripple current
+VCC_
COREP49 Dell Change PC87, P C 8 8 , P C 9 7 , P C 9 8 , PC109 and PC110 to X6S from X5R.Recommend using X6S filtering capacitors for VCORE decoupling
07/20/2005 X00
at the 6.2A charge rate will be over 3A.
Follow Team track (BITS): no: CR03709
Dell to match latest VCore reference schematic A03. Depop PR104 and a d d P R1 8 5 r es istor to jumper pin 2 to pin 3807/20/2005P49 +VCC_CORE X00
Change PG name fr om PG D_IN to 1.05V_RUN_PWRGD
Use 1.5V PG: Ad d P R1 83 for 1.5V_RUN_PWRGD
Update Layout notes.
PR22, PC16, PC29, PR23, PR34, PR35, PU2_pin23. Add PR184
Short this ana lo g g ro un d w ith th e power ground plane at PU2_pin23.
Change PC127 a n d P C 1 2 8 to 1210 from 1206 size. X00
X00
X0012 P48 +1.8VSUSP/ +0.9V_DDR_VT 07/13/2005 Compal Change 0.9V input power to 1.8VSUS. Install P JP 2 1 f or 0.9V input power.
X00
X00
X00
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
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Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
Power-Changed-List History
LA-2881P
1
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Request
TitleItem Issue DescriptionDate
D D
21
22
23
24
25
26
C C
27
28
ChargerP50 Compal Improve current sense accuracy Update PR12 3 a nd PR1 38 Sy mb ol Pin define for layout dimension
P49 +VCC_CORE 07/20/2005 Compal Improve Inductor DCR sense accuracy Update PL15, PL1 6 a nd PL 17 Symbol Pin define for layout
P50 Charger Compal Set power limit to 130W/ 90W for ZRS.
P50 Charger 07/22/2005 Compal Follow COE charger A02 ref. schematic. X00Connected PC 1 3 1 p in2 to PR165 pin2.
P49 +VCC_CORE 08/22/2005 Compal Cost Down:Change CPU L-S MOSFET from BSC022N03S to FDS7088SN3. Change PQ17, P Q 19 a n d PQ21 to FDS7088SN3. X01
P49
+VCC_CORE 08/22/2005 De ll
P47 +1.5VRUNP /+VCCP_1P05VP Dell Follow Coe ref sch: change to A03.
29
P50 Charger Follow COE charger A03 ref. schematic.08/23/2005 Dell
30
31
32
B B
33
+1.8VSUSP/ +0.9V_DDR_VTP48 08/26/2005 Dell To fix the 1.8VSUS bleed off issue at Power Down
+3.3V/+5V/+15V
P46 08/26/2005 Compal
+VCC_COREP49 08/29/2005 Compal
07/20/2005
07/21/2005 X00
08/22/2005 X01
Owner
DellP49 +VCC_CORE 07/20/2005 Change net name from H_PROCHOT# to IMVP6_PROCHOT# Change net n a m e f ro m H _ PR O C H O T # to IMVP6_PROCHOT# on PR86 Pin2. X00
pin define changed.
dimension pin define changed.
Change PR169 t o 28.7K from 200K.
Add Pop Option notes.
For Z/ ZUMA pop PR169: 28K, depop PR186
For R/ S pop PR1 86 : 100K, depop PR169.
BITS ID: CR04364. Change ISL6260 VSUM resistors to 0805
package to reduce offset error; and DROOP reisstor value
To fix the PC36 AL-Caps can not meet lead free reflow
spec isse.
To fix the PC150 AL-Caps can not meet lead free reflow
spec isse.
Change PR83, P R 1 0 3 a n d PR 122 to 0805 size from 0402.
Chang loadli n e s l op e r e si s t or PR119 from 9.53k to 10.5k
Change PL10 to 3. 2U H_ CD EP 12D 38 NP_8.5A from 3.8UH_SIL104-3R8_6A.
Change PR47 to 1.87K from 2.1K.
Delete PJP21 a n d PJ P 2 2 Ju m p e r . VTTI only need 1.8V, no 1.5V.Dell+1.8VSUSP/ +0.9V_DDR_VTP48 Follow Coe ref sch: change to A03.08/22/2005 X01
Change PR169 t o 3 01 k , P R1 7 0 t o 0, PR171 to 59k, PR172 to 33.2k.
Delete PR186, PC 16 6, PC 167 and PU15; depop PR166.
2 of 0ohm re s i t o rs ( P R 1 86 a nd PR187) at PU6 pin 22 (VDD)
to either 5VSUS and 5VALW.
Add PC172 and c ha ng e P C3 6 fr om C_ 25CV220AX to NIPPON, MVY25VC100MF80
due to SANYO A L C ap c a n n o t meet lead free reflow spec
Reserve PC17 3 ( 1 0 0U ) a n d d o u b le footprint with PC150 (220U)
Pop PC173 if ne ed ed fo r b uz z no is e, Reserve PC150 for SANYO Vendor
ready AL-Caps re fl ow sp ec . an d it is enough capacity (220U)
to against buzz noise.
Solution Description Rev.Page#
X00
X00
X01
X01
X01
X01
X01
34
P48 +1.8VSUSP/ +0.9V_DDR_VT 08/30/2005 Dell
35
36
+VCC_COREP49 08/30/2005 Dell
ChargerP50 08/30/2005 Dell
37
A A
38
ChargerP50 08/31/2005 Dell
BITS issue: CR20063: This is not on the reference schematic
and is not asked for by Maxim.
BITS issue: CR07318:
Intersil X01 ZRS Schematic Review - Vcore
BITS issue: DF20383 :
Maxim ZRS X01 MAX8731 Schematic Review
BITS issue: CR20060 :
Power Good Pull Up Removed
Delete PC74. X01
Set PC100=0.0 15 uF (d ec rease soft-start time)
Set PR108=11 . 5 K (set OCP=55A)
Nopop PC158, set PR165=0.
De-populate PR183 and PR60Dell08/31/2005 X01+1.5VRUNP /+VCCP_1P05VPP47
Reserve INA194 as a Buck up. No POP P U 1 7, P C 1 74 , PC175 and PR188.
X01
X01
X01
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
5
4
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
Power-Changed-List History
LA-2881P
1
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3
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Request
Owner
39
D D
ChargerP50 09/16/2005 Dell Up date ADAPT_OC, add note.
40 ChargerP50 09/26/2005 Compal Change filter for derating is not enough.
Charger41 09/29/2005P50 Adapter OC setting update. Dell X02
ChargerP5042 10/05/2005 Dell
P48 +1.8VSUSP/ +0.9V_DDR_VT 10/11/2005 Dell43
C C
+VCC_COREP4944 10/14/2005 Dell Follow Coe schematic Change PC100 f r o m 0.015u to 0.01uF. X02
+VCC_COREP4945 10/14/2005 Dell
P49 +VCC_CORE 10/14/200546 Dell
47
48 10/17/2005 Dell Follow Coe schematic
49 10/17/2005 Dell Ch
B B
51 10/25/2005 Dell Update 3V, 5V and 1.8V OC to meet power Budgets
+VCC_CORE 10/14/2005 De ll Follow Coe schematicP49 PR182 Pin 1 cha ng e f rom H_DPRSTP# to A_GND X02
ChargerP50
+1.5VRUNP /+VCCP_1P05VP
P47
P46
+3.3V/+5V/+15V
+VCC_COREP4850 10/18/2005
P46
+3.3V/+5V/+15V
P48
+1.8VSUSP/ +0.9V_DDR_VT
Dell Change CPU L-S Layout dimension
dV/dt issue with the FBSA pin of Charger,
recommend an RC filter at the pin.
Modified BST resistor to protection BOOT diode.
Depop 0.9V pull high.
Improve the temperature compensation
of output voltage regulation
Improve the time constant match between
L/DCR and droop circuit R*C
ange input MLCC cap.
Use combination footprint
Change PR169 : 2 8 K f o r R/S, 100K for Z/ZUMA
Change PR171 t o 1 21 K ; Change PR172 to 3.01K
1. Change PL2, PL21, PL3, PL4, PL18 and PL19
from 453215-9 00 LM AT 1812_6A to 1812_9A;
2. Pop PL3 and PL18.
Pop Option notes:
1. 4@. For Z a n z i b ar / Z U MA p o p PR 1 6 9 , PR172 for 90W, no pop PR189, PR190.
2. 5@. For Rick er / S uv a p op PR1 89 , PR190 for 130W, no pop PR169, PR172.
3. PC160 no pop.
Add PR191 and PC176 filter
Add PR192 (No pop)
Change PR67 from 0 to 1.
Depop PR66.
Change PR111 f r o m 3.57K to 2.43K X02
Change PC113 from 0.01uF_NC to 0.033uF
Pop PR192 , No pop PR191
Connect FBSA a nd FB SB (pins 15 and 16) together
Pop PC145 , No pop PC47.
Layout dimens io n f ro m F DS 708 8SN3_SO8 to FDS7088SN3_SO8_3P X02
Change PR76 fr om 48.7k to 36.5k
Change PR26 fr om 82.5k to 71.5k
Change PR25 fr om 69.8k to 19.1k
Solution Description Rev.Page# Tit leItem Issue DescriptionDate
X01
X02
X02
X02
X02
X02
X02
X02
ChargerP50 10/26/2005 Add 1 ohm, 200pf RC filter to Charger LX pin same as Travis. Chan ge P R 1 6 5 f r o m 0 t o 1, Pop PC158 220pF. X02Compal52
1. change PR169 from 4@301k to 4@49.9k
2. change PR17 2 f ro m 4@71.5k to 4@9.31k
53 P50 Charger 10/27/2005 Dell Adapter OC UL circuit update
P47 +1.8VSUSP/ +0.9V_DDR_VT 11/11/200554 Dell Follow Coe A05 schematic
A A
P49 Charger55 11/11/2005 Dell Change Charger input caps size due to material EOL. Change PC1 2 7 a n d P C 128 from 1210 to 1206. A00
3. change PR17 1 f rom 68.1k to 13.3k
4. change PR189 from 5@215k to 5@33.2k
5. change PR 1 9 0 f rom 5@121k to 5@15k
6. change PR16 6 f rom @499k to 976k
Delete PR68 0 o hm s o n pin7 drived by RUN_ON.
X02
A00
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
Power-Changed-List History
LA-2881P
1
61 62Tuesday, December 13, 2005
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Page 62
5
4
Version Change List ( P. I. R. List ) for Power Circuit
3
2
1
Request
Owner
D D
57 All All 1812 size bead 11/23/2005 Compal Use co-dimension bead for shortage issue
58 P49 Charger 11/24/2005 Dell ADAPT_OC Circuit update.
59 11/29/2005P49 A00Change Indu c t o r fr o m N EC - T O K I N M P C1040LR45 to PANASONIC ETQP4LR45XFCV_CORE rusted issue
+VCC_CORE
Dell
60 11/29/2005P49 V_CORE Aduio buzzing noise Pop PC150 220UF. A00+VCC_CORE Compal
C C
P49 Charger 12/1/2005 De ll62 Deeply dischargered battery problem. Add PR193, PD54. A01
Change to new dimension:
PL2, PL21, P L 3 , P L4 , P L 5, P L9, PL12, PL14, PL18 and PL19
Keep use for Ricker/ Suva #130W;
Delete these c i r c ui t for Zanzibar/ ZUMA.
Update notes on Page49.
Solution Description Rev.Page# Tit leItem Issue DescriptionDate
A00P4956 Charger 11/21/2005 Dell Follow Coe A09 schematic No pop P C 1 76 , Add PC177 pop
A00
A00
A0061 P43 PR9 should be 10K ohms to meet derating.+DCIN 12/05/2005 Dell Change P R 9 v a l u e from 4.7K to 10K.
B B
A A
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
Power-Changed-List History
LA-2881P
1
62 62Tuesday, December 13, 2005
2.0
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