Compal LA-2841, Pavilion dv5000 Schematic

A

1 1

2 2

B

C

D

E

Compal confidential

Schematics Document

Mobile Yonah uFCPGA with Intel

3 3

4 4

A

Calistoga_GM/PM+ICH7-M core logic

2005-12-15

REV:1.0

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

B

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2005/03/10 2006/03/10

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

D

Date: Sheet

Compal Electronics, Inc.

Cover Sheet

LA-2841

160Thursday, December 15, 2005

E

1.0

of

A

Compal confidential

File Name : LA-2841

ZZZ

B

C

D

E

PCB

1 1

VRAM
128/256MB

page 22,23,24,25

Thermal Sensor
ADM1032

page 4

Fan Control

page 4

uFCBGA-479/uFCPGA-478 CPU

Nvidia
NV71/72M

page 18,19,20,21,26

PCI-E x 16

Intel Calistoga GMCH

LVDS Panel
Interface

2 2

page 16

CRT & TV OUT

page 17

LAN I/F

3.3V 33 MHz

10/100 LAN

3 3

page 35

CardBus Controller

PCI BUS

TI PCI7412

page 32

RTC CKT.

page 29

RJ45 CONN

page 35

Slot 0

page 33

1394

page 32

Card reader

page 32

Touch Pad

Power On/Off CKT.

page 42

Mobile Yonah

page 4, 5, 6

H_A#(3..31)
H_D#(0..63)

FSB

533/667MHz

PCBGA 1466

page 7, 8, 9, 10,11,12

DMI

Intel ICH7-M

mBGA-652

page 27, 28, 29, 30

LPC BUS

ENE KB910/L

page 44

page 42

Int.KBD

BIOS

DDR2 -400/533/667

Dual Channel

PCIE x3

USB2.0

AC-LINK

page 42

page 45

DDR2-SO-DIMM X2

BANK 0, 1, 2, 3

page 13,14

Mini-PCIE Card

New Card
Connector x2

USB conn X3

BT Conn

Audio CKT
AMOM

SATA HDD
Connector x2

PATA CDROM
Connector

page 37

page 34

page 41

page 41

page 38

page 31

page 31

Clock Generator
ICS 954306

page 15

MODEM
AMOM

page 39

AMP & Audio Jack

page 40

SPR CONN.

*RJ45 CONN
*MIC IN JACK
*LINE OUT JACK
*1394 CONN
*SPDIF CONN
*DC JACK
*TVOUT CONN

DC/DC Int erface CKT.

4 4

page 47

*USB CONN x1
*CIR x1

page 46

Power Circuit DC/DC

page 48~56

A

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

B

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2005/03/10 2006/03/10

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

D

Date: Sheet

Compal Electronics, Inc.

Block Diagram

LA-2841

E

1.0

of

260Thursday, December 15, 2005

Voltage Rails

power
plane

State

+B
LDO3
LDO5

+5VALW
+3VALW

+1.8V
+5V

A

+5VS
+3VS
+2.5VS
+1.8VS
+1.5VS
+1.2VS
+VGA_CORE
+0.9VS
+CPU_CORE
+VCCP

S0

S1

S3

S5 S4/AC

S5 S4/ Battery only

S5 S4/AC & Battery
don't exist

O MEANS ON

X MEANS OFF

1 1

O

O
O
O

O

X

O

O
O
O

X

O

XX

X

OO

OO

X

X

XX X

PCI Devices

EXTERNAL

CARD BUS & 1394

IDSEL# REQ/GNT# PIRQ
AD22 2 C,D,E,G

Load BOM check item

1.U31 GM/PM/GML part number

2.U6 ICH7 part number

3.VRAM part number and Page26 RAM_CFG[0:3]/PCI_DEVID[0:3] modify check

4.For NV73 R510/R75/R533/R168 change to 499ohm

5.U33 NV7x part number

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

2005/03/10 2006/03/10

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

Notes List

LA-2841

360Thursday, December 15, 2005

of

1.0

5

H_A#[3..31]<7>

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8

D D

H_REQ#[0..4]<7>

H_ADSTB#0<7>

C C

R17

56_0402_5%

1 2

+VCCP

B B

H_PROCHOT#<53>

1 2

+VCCP

75_0402_5%

H_THERMDA, H_THERMDC routing together.
Trace width / Spacing = 10 / 10 mil

A A

H_PROCHOT# OCP#

H_ADSTB#1<7>

CLK_CPU_BCLK<15>

CLK_CPU_BCLK#<15>

H_BPRI#<7>

H_DEFER#<7>

H_DRDY#<7>

H_HITM#<7>

H_LOCK#<7>

H_RESET#<7>

H_RS#[0..2]<7>

H_TRDY#<7>

ITP_DBRESET#<29>

H_DBSY#<7>

H_DPSLP#<28>

H_DPRSTP#<28,53>

H_DPWR#<7>

R18

H_PWRGOOD<28>

H_CPUSLP#<7>

R456 1K_0402_5%@

1 2

R455 51_0402_5%

1 2

H_THERMTRIP#<7,28>

+VCCP

12

R457

56_0402_5%@

B

2

E

3 1

C

Q35

MMBT3904_SOT23@

5

H_ADS#<7>
H_BNR#<7>

H_BR0#<7>

H_HIT#<7>

H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

H_ADSTB#0
H_ADSTB#1

CLK_CPU_BCLK
CLK_CPU_BCLK#

H_ADS#
H_BNR#
H_BPRI#
H_BR0#
H_DEFER#
H_DRDY#
H_HIT#
H_HITM#
H_IERR#
H_LOCK#
H_RESET#

H_RS#0
H_RS#1
H_RS#2
H_TRDY#

ITP_BPM#0
ITP_BPM#1
ITP_BPM#2
ITP_BPM#3

ITP_DBRESET#

H_DBSY#
H_DPSLP#
H_DPRSTP#
H_DPWR#
ITP_BPM#4
ITP_BPM#5
H_PROCHOT#

H_PWRGOOD
H_CPUSLP#
ITP_TCK
ITP_TDI
ITP_TDO
TEST1
TEST2 H_INIT#
ITP_TMS
ITP_TRST#

H_THERMDA
H_THERMDC
H_THERMTRIP#

OCP# <29>

JP16A

J4

A3#

L4

A4#

M3

A5#

K5

A6#

M1

A7#

N2

A8#

J1

A9#

N3

A10#

P5

A11#

P2

A12#

L1

A13#

P4

A14#

P1

A15#

R1

A16#

Y2

A17#

U5

A18#

R3

A19#

W6

A20#

U4

A21#

Y5

A22#

U2

A23#

R4

A24#

T5

ADDR GROUP

A25#

T3

A26#

W3

A27#

W5

A28#

Y4

A29#

W2

A30#

Y1

A31#

K3

REQ0#

H2

REQ1#

K2

REQ2#

J3

REQ3#

L5

REQ4#

L2

ADSTB0#

V4

ADSTB1#

A22

BCLK0

A21

H1

E2

G5

F1

H5

F21

G6

E4

D20

H4

B1

F3

F4
G3
G2

AD4
AD3
AD1
AC4

C20

E1

B5

E5

D24
AC2
AC1
D21

D6
D7

AC5
AA6
AB3
C26
D25
AB5
AB6

A24
A25

C7

HOST CLK

BCLK1

ADS#
BNR#
BPRI#
BR0#
DEFER#
DRDY#
HIT#

CONTROL

HITM#
IERR#
LOCK#
RESET#

RS0#
RS1#
RS2#
TRDY#

BPM0#
BPM1#
BPM2#
BPM3#

DBR#
DBSY#
DPSLP#
DPRSTP#
DPWR#
PRDY#
PREQ#
PROCHOT#

PWRGOOD
SLP#
TCK
TDI
TDO
TEST1
TEST2
TMS
TRST#

THERMAL

THERMDA

DIODE

THERMDC
THERMTRIP#

FOX_PZ47903-2741-42_YONAH

H_DPSLP#

H_DPRSTP#

YONAH

MISC

R437

1 2

56_0402_5%@

R436

1 2

56_0402_5%@

4

DATA GROUP

LEGACY CPU

+VCCP

4

D10#
D11#
D12#
D13#
D14#
D15#
D16#
D17#
D18#
D19#
D20#
D21#
D22#
D23#
D24#
D25#
D26#
D27#
D28#
D29#
D30#
D31#
D32#
D33#
D34#
D35#
D36#
D37#
D38#
D39#
D40#
D41#
D42#
D43#
D44#
D45#
D46#
D47#
D48#
D49#
D50#
D51#
D52#
D53#
D54#
D55#
D56#
D57#
D58#
D59#
D60#
D61#
D62#
D63#

DINV0#
DINV1#
DINV2#
DINV3#

DSTBN0#
DSTBN1#
DSTBN2#
DSTBN3#
DSTBP0#
DSTBP1#
DSTBP2#
DSTBP3#

A20M#
FERR#

IGNNE#

INIT#
LINT0
LINT1

STPCLK#

SMI#

3

This shall place near CPU

H_D#[0..63] <7>

H_D#0

E22

D0#

H_D#1

F24

D1#

H_D#2

E26

D2#

H_D#3

H22

D3#

H_D#4

F23

D4#

H_D#5

G25

D5#

H_D#6

E25

D6#

H_D#7

E23

D7#

H_D#8

K24

D8#

H_D#9

G24

D9#

H_D#10

J24

H_D#11

J23
H26
F26
K22
H25
N22
K25
P26
R23
L25
L22
L23
M23
P25
P22
P23
T24
R24
L26
T25
N24
AA23
AB24
V24
V26
W25
U23
U25
U22
AB25
W22
Y23
AA26
Y26
Y22
AC26
AA24
AC22
AC23
AB22
AA21
AB21
AC25
AD20
AE22
AF23
AD24
AE21
AD21
AE25
AF25
AF22
AF26

J26
M26
V23
AC20

H23
M24
W24
AD23
G22
N25
Y25
AE24

A6
A5
C4
B3
C6
B4

D5
A3

H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63

H_DINV#0
H_DINV#1
H_DINV#2
H_DINV#3

H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3
H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3

H_A20M#
H_FERR#
H_IGNNE#

H_INTR
H_NMI

H_STPCLK#
H_SMI#

H_DINV#0 <7>
H_DINV#1 <7>
H_DINV#2 <7>
H_DINV#3 <7>

H_DSTBN#[0..3] <7>

H_DSTBP#[0..3] <7>

H_A20M# <28>
H_FERR# <28>
H_IGNNE# <28>
H_INIT# <28>
H_INTR <28>
H_NMI <28>

H_STPCLK# <28>
H_SMI# <28>

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

ITP_DBRESET#

R181 200_0402_5%@

1 2

2005/03/10 2006/03/10

ITP_TDI
ITP_TMS
ITP_TDO
ITP_BPM#5
ITP_TRST#
ITP_TCK

ITP_BPM#0
ITP_BPM#1
ITP_BPM#2
ITP_BPM#3
ITP_BPM#4

Thermal Sensor ADM1032AR

2200P_0402_50V7K

+3VS

FAN control

Compal Secret Data

Deciphered Date

2

R6 56_0402_5%

1 2

R3 56_0402_5%

1 2

R2 56_0402_5%

1 2

R1 56_0402_5%

1 2

R4 56_0402_5%

1 2

R5 56_0402_5%

1 2

T27

PAD

T5

PAD

T4

PAD

T3

PAD

T1

PAD

T2

PAD

+3VS

2

C598

0.1U_0402_16V4Z

C592

1 2

R458

1 2

10K_0402_5%

BAS16_SOT23

EN_FAN1<44>

1

H_THERMDA
H_THERMDC

THERM#

+5VS

FAN1

FAN1

D22

3

2

+VCCP

U30

1

VDD

2

D+

3

D­THERM#4GND

ADM1032AR_SOP8

SCLK

SDATA

ALERT#

EC_SMC_2

8

EC_SMD_2

7
6
5

Address:100_1100

EC_SMC_2<44>

EC_SMD_2<44>

C765 10U_1206_16V4Z

1 2

U40

1

VEN

2

VIN

3

VO

4

VSET

G993P1UF_SOP8

+5VS +3VS

12

1SS355_SOD323
D28

1

2

FAN_SPEED1<44>

EC_SMC_2
EC_SMD_2

8

GND

7

GND

6

GND

5

GND

1

1

2

2

1000P_0402_50V7K

C761

C763 10U_0805_10V4Z

C762

1000P_0402_50V7K

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

Yonah CPU in mFCPGA479

LA-2841

R551
10K_0402_5%

1 2

ACES_85205-0300

1

2

JP30

1

1
2
3

1.0

of

460Thursday, December 15, 2005

1

5

4

3

2

1

V_CPU_GTLREF

+VCCP

12

R454
1K_0402_1%

12

R451
2K_0402_1%

+CPU_CORE

R442
100_0402_1%

1 2

R441
100_0402_1%

1 2

VCCSENSE

VSSSENSE

Close to CPU pin
within 500mils.

CPU_BSEL CPU_BSEL2 CPU_BSEL1

133

166

00

0

12

12

R452

54.9_0402_1%

R439

R453

27.4_0402_1%

D D

Close to CPU pin AD26
within 500mils.

C C

B B

Length match within 25 mils
The trace width 18 mils space
7 mils

+1.5VS

1

C586

C587

2

0.01U_0402_16V7K

CPU_BSEL0

1

1

Resistor placed within

0.5" of CPU pin.Trace
should be at least 25
mils away from any
other toggling signal.

12

27.4_0402_1%

1

R438

12

54.9_0402_1%

1

2

10U_0805_10V4Z

VCCSENSE<53>
VSSSENSE<53>

H_PSI#<53>

CPU_VID0<53>
CPU_VID1<53>
CPU_VID2<53>
CPU_VID3<53>
CPU_VID4<53>
CPU_VID5<53>
CPU_VID6<53>

V_CPU_GTLREF

CPU_BSEL0<15>
CPU_BSEL1<15>
CPU_BSEL2<15>

+CPU_CORE

+VCCP

VCCSENSE
VSSSENSE

H_PSI#
CPU_VID0

CPU_VID1
CPU_VID2
CPU_VID3
CPU_VID4
CPU_VID5
CPU_VID6

CPU_BSEL0
CPU_BSEL1
CPU_BSEL2

COMP0
COMP1
COMP2
COMP3

JP16B

AF7

VCCSENSE

AE7

VSSSENSE

B26

VCCA

K6

VCCP

J6

VCCP

M6

VCCP

N6

VCCP

YONAH

VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP

PSI#
VID0

VID1
VID2
VID3
VID4
VID5
VID6

GTLREF
BSEL0

BSEL1
BSEL2

COMP0
COMP1
COMP2
COMP3

VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC

RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD

FOX_PZ47903-2741-42_YONAH

W21

AD26

AB20
AA20
AF20
AE20
AB18
AB17
AA18
AA17
AD18
AD17
AC18
AC17
AF18
AF17

T6

R6

K21

J21
M21
N21
T21
R21
V21

V6

G21

AE6
AD6

AF5
AE5
AF4
AE3
AF2
AE2

B22
B23
C21

R26
U26

U1

V1

E7

D2

F6
D3
C1

AF1
D22
C23
C24
AA1
AA4
AB2
AA3

M4
N5

T2

V3

B2
C3

T22
B25

AB26

VSS

AA25

VSS

AD25

VSS

AE26

VSS

AB23

VSS

AC24

VSS

AF24

VSS

AE23

VSS

AA22

VSS

AD22

VSS

AC21

VSS

AF21

VSS

AB19

VSS

AA19

VSS

AD19

VSS

AC19

VSS

AF19

VSS

AE19

VSS

AB16

VSS

AA16

VSS

AD16

VSS

AC16

VSS

AF16

VSS

AE16

VSS

AB13

VSS

AA14

VSS

AD13

VSS

AC14

VSS

AF13

VSS

AE14

VSS

AB11

VSS

AA11

VSS

AD11

VSS

AC11

VSS

AF11

VSS

AE11

VSS

AB8

VSS

AA8

VSS

AD8

VSS

AC8

VSS

AF8

VSS

AE8

VSS

AA5

VSS

AD5

VSS

AC6

VSS

AF6

VSS

AB4

VSS

AC3

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

AF3
AE4
AB1
AA2
AD2
AE1
B6
C5
F5
E6
H6
J5
M5
L6
P6
R5
V5
U6
Y6
A4
D4
E3
H3
G4
K4
L3
P3
N4
T4
U3
Y3
W4
D1
C2
F2
G1

POWER, GROUNG, RESERVED SIGNALS AND NC

+CPU_CORE

JP16C

AE18

VCC

AE17

VCC

AB15

VCC

AA15

VCC

AD15

VCC

AC15

VCC

AF15

VCC

AE15

VCC

AB14

VCC

AA13

VCC

AD14

VCC

AC13

VCC

AF14

VCC

AE13

VCC

AB12

VCC

AA12

VCC

AD12
AC12
AF12
AE12
AB10

AB9

AA10

AA9

AD10

AD9

AC10

AC9

AF10

AF9

AE10

AE9
AB7
AA7
AD7
AC7
B20
A20
F20
E20
B18
B17
A18
A17
D18
D17
C18
C17
F18
F17
E18
E17
B15
A15
D15
C15
F15
E15
B14
A13
D14
C13
F14
E13
B12
A12
D12
C12
F12
E12
B10

A10
D10
C10
F10
E10

B9
A9
D9
C9

F9

E9
B7
A7

F7

YONAH

VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC

POWER, GROUND

VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC

FOX_PZ47903-2741-42_YONAH

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

K1
J2
M2
N1
T1
R2
V2
W1
A26
D26
C25
F25
B24
A23
D23
E24
B21
C22
F22
E21
B19
A19
D19
C19
F19
E19
B16
A16
D16
C16
F16
E16
B13
A14
D13
C14
F13
E14
B11
A11
D11
C11
F11
E11
B8
A8
D8
C8
F8
E8
G26
K26
J25
M25
N26
T26
R25
V25
W26
H24
G23
K23
L24
P24
N23
T23
U24
Y24
W23
H21
J22
M22
L21
P21
R22
V22
U21
Y21

A A

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/03/10 2006/03/10

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

Compal Electronics, Inc.

Yonah CPU in mFCPGA479

LA-2841

560Thursday, December 15, 2005

1

1.0

of

5

4

3

2

1

D D

Place these capacitors on L8
(North side,Secondary Layer)

Place these capacitors on L8
(North side,Secondary Layer)

Place these capacitors on L8
(Sorth side,Secondary Layer)

C C

Place these capacitors on L8
(Sorth side,Secondary Layer)

South Side Secondary

B B

+CPU_CORE

+CPU_CORE

+CPU_CORE

+CPU_CORE

+CPU_CORE

1

+

C37

2

330U_V_2.5VK_R9

1

C13
10U_0805_6.3V6M

2

1

C33
10U_0805_6.3V6M

2

1

C40
10U_0805_6.3V6M

2

1

C26
10U_0805_6.3V6M

2

C47

330U_V_2.5VK_R9

C584

330U_V_2.5VK_R9

1

2

1

2

1

2

1

2

1

+

2

C23
10U_0805_6.3V6M

C35
10U_0805_6.3V6M

C22
10U_0805_6.3V6M

C10
10U_0805_6.3V6M

1

+

C585

2

330U_V_2.5VK_R9@

1

C14
10U_0805_6.3V6M

2

1

C39
10U_0805_6.3V6M

2

1

C32
10U_0805_6.3V6M

2

1

C21
10U_0805_6.3V6M

2

1

1

+

+

C8

@

2

2

330U_V_2.5VK_R9

C583

@

820U_E9_2_5V_M_R7

1

2

+

1

C28
10U_0805_6.3V6M

2

1

C42
10U_0805_6.3V6M

2

1

C27
10U_0805_6.3V6M

2

1

C15
10U_0805_6.3V6M

2

1

+

C576

2

330U_V_2.5VK_R9

1

C34
10U_0805_6.3V6M

2

1

C38
10U_0805_6.3V6M

2

1

C16
10U_0805_6.3V6M

2

1

C1
10U_0805_6.3V6M

2

1

+

North Side Secondary

C578

2

@

820U_E9_2_5V_M_R7

1

C18
10U_0805_6.3V6M

2

1

C41
10U_0805_6.3V6M

2

1

C11
10U_0805_6.3V6M

2

1

C6
10U_0805_6.3V6M

2

1

2

1

2

1

2

1

2

ESR <= 1.5m ohm
Capacitor > 1980uF

C19
10U_0805_6.3V6M

C2
10U_0805_6.3V6M

C36
10U_0805_6.3V6M

C24
10U_0805_6.3V6M

1

C30
10U_0805_6.3V6M

2

1

C48
10U_0805_6.3V6M

2

1

C31
10U_0805_6.3V6M

2

1

C12
10U_0805_6.3V6M

2

Mid Frequence Decoupling

+VCCP

1

+

C591

220U_D2_4VM

A A

5

2

1

C43

0.1U_0402_16V4Z

2

1

C44

0.1U_0402_16V4Z

2

4

1

C45

0.1U_0402_16V4Z

2

1

C3

0.1U_0402_16V4Z

2

1

C4

0.1U_0402_16V4Z

2

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

1

C5

0.1U_0402_16V4Z

2

3

Place these inside
socket cavity on L8
(North side
Secondary)

2005/03/10 2006/03/10

Compal Secret Data

Deciphered Date

2

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

CPU Bypass capacitors

LA-2841

1

of

660Thursday, December 15, 2005

1.0

5

4

3

2

1

H_D#[0..63]<4>

D D

C C

+VCCP

12

12

R462

54.9_0402_1%

+VCCP

R45

R42

12

R466

24.9_0402_1%

12

100_0402_1%

12

200_0402_1%

R461

54.9_0402_1%

B B

A A

H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63

H_VREF
H_XRCOMP
H_XSCOMP
H_YRCOMP
H_YSCOMP
H_SWNG0
H_SWNG1

12

R464

24.9_0402_1%

Layout Note:
H_XRCOMP / H_YRCOMP / H_VREF / H_SWNG0 /
H_SWNG1 trace width and spacing is 10/20.

H_VREF

1

C87

2

0.1U_0402_16V4Z

5

H1
H3
G1

G2

H4

K11

G4

T10

W11

U7

U9
U11
T11

W9

W7

U5

W6
AB7

AA9

W4

W3

W5
Y10
AB8

W2
AA4
AA7
AA2
AA6

AA10

AA1
AB4
AC9

AB11
AC11

AB3
AC2
AD1
AD9
AC1
AD7
AC6
AB5

AD10

AD4
AC8

J13
K13

U1

W1

U31A

F1

HD0#

J1

HD1#
HD2#

J6

HD3#
HD4#

K2

HD5#
HD6#
HD7#

K9

HD8#

K1

HD9#

K7

HD10#

J8

HD11#
HD12#

J3

HD13#
HD14#
HD15#
HD16#
HD17#

T3

HD18#
HD19#
HD20#
HD21#
HD22#
HD23#

T1

HD24#

T8

HD25#

T4

HD26#
HD27#
HD28#

T9

HD29#
HD30#

T5

HD31#
HD32#
HD33#
HD34#
HD35#

Y3

HD36#

Y7

HD37#
HD38#
HD39#
HD40#
HD41#
HD42#
HD43#
HD44#
HD45#
HD46#

Y8

HD47#
HD48#
HD49#
HD50#
HD51#
HD52#
HD53#
HD54#
HD55#
HD56#
HD57#
HD58#
HD59#
HD60#
HD61#
HD62#
HD63#

HVREF0
HVREF1

E1

HXRCOMP

E2

HXSCOMP

Y1

HYRCOMP
HYSCOMP

E4

HXSWING
HYSWING

CALISTOGA_FCBGA1466~D

HA3#
HA4#
HA5#
HA6#
HA7#
HA8#

HA9#
HA10#
HA11#
HA12#
HA13#
HA14#
HA15#
HA16#
HA17#
HA18#
HA19#
HA20#
HA21#
HA22#
HA23#
HA24#
HA25#
HA26#
HA27#
HA28#
HA29#
HA30#
HA31#

HREQ#0
HREQ#1
HREQ#2
HREQ#3
HREQ#4

HADSTB#0
HADSTB#1

HOST

HCLKN
HCLKP

HDSTBN#0
HDSTBN#1
HDSTBN#2
HDSTBN#3
HDSTBP#0
HDSTBP#1
HDSTBP#2
HDSTBP#3

HDINV#0
HDINV#1
HDINV#2
HDINV#3

HCPURST#

HADS#

HTRDY#

HDPWR#

HDRDY#

HDEFER#

HHITM#

HHIT#

HLOCK#

HBREQ0#

HBNR#
HBPRI#

HDBSY#

HCPUSLP#

HRS0#
HRS1#
HRS2#

12

R38

221_0603_1%

12

R37

100_0402_1%

H9
C9
E11
G11
F11
G12
F9
H11
J12
G14
D9
J14
H13
J15
F14
D12
A11
C11
A12
A13
E13
G13
F12
B12
B14
C12
A14
C14
D14

D8
G8
B8
F8
A8

B9
C13

AG1
AG2

K4
T7
Y5
AC4
K3
T6
AA5
AC5

J7
W8
U3
AB10

B7
E8
E7
J9
H8
C3
D4
D3
B3
C7
C6
F6
A7
E3

B4
E6
D6

H_SWNG0

1

2

4

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

H_ADSTB#0
H_ADSTB#1

CLK_MCH_BCLK#
CLK_MCH_BCLK

H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3
H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3

H_DINV#0
H_DINV#1
H_DINV#2
H_DINV#3

H_RESET#
H_ADS#
H_TRDY#
H_DPWR#
H_DRDY#
H_DEFER#
H_HITM#
H_HIT#
H_LOCK#
H_BR0#
H_BNR#
H_BPRI#
H_DBSY#
H_CPUSLP#

H_RS#0
H_RS#1
H_RS#2

C82

0.1U_0402_16V4Z

+VCCP+VCCP

12

R463

12

R465

H_A#[3..31] <4>

H_REQ#[0..4] <4>

H_ADSTB#0 <4>
H_ADSTB#1 <4>

CLK_MCH_BCLK# <15>
CLK_MCH_BCLK <15>
H_DSTBN#[0..3] <4>

H_DSTBP#[0..3] <4>

H_DINV#0 <4>
H_DINV#1 <4>
H_DINV#2 <4>
H_DINV#3 <4>

H_RESET# <4>
H_ADS# <4>
H_TRDY# <4>
H_DPWR# <4>
H_DRDY# <4>
H_DEFER# <4>
H_HITM# <4>
H_HIT# <4>
H_LOCK# <4>
H_BR0# <4>
H_BNR# <4>
H_BPRI# <4>
H_DBSY# <4>
H_CPUSLP# <4>

H_RS#[0..2] <4>

221_0603_1%

H_SWNG1

1

C601

2

100_0402_1%

0.1U_0402_16V4Z

U31B

AE35
AF39
AG35
AH39

AC35
AE39
AF35
AG39

AE37
AF41
AG37
AH41

AC37
AE41
AF37
AG41

AY35

AR1

AW7

AW40
AW35

AT1
AY7

AY40
AU20

AT20
BA29
AY29

AW13
AW12

AY21

AW21

AL20
AF10

BA13
BA12
AY20
AU21

AV9
AT9

AK1

AK41

G28

F25

H26

G6
AH33
AH34

K28

CALISTOGA_FCBGA1466~D

Deciphered Date

DMIRXN0
DMIRXN1
DMIRXN2
DMIRXN3

DMIRXP0
DMIRXP1
DMIRXP2
DMIRXP3

DMITXN0
DMITXN1
DMITXN2
DMITXN3

DMITXP0
DMITXP1
DMITXP2
DMITXP3

SM_CK0
SM_CK1
SM_CK2
SM_CK3

SM_CK0#
SM_CK1#
SM_CK2#
SM_CK3#

SM_CKE0
SM_CKE1
SM_CKE2
SM_CKE3

SM_CS0#
SM_CS1#
SM_CS2#
SM_CS3#

SM_OCDCOMP0
SM_OCDCOMP1

SM_ODT0
SM_ODT1
SM_ODT2
SM_ODT3

SM_RCOMPN
SM_RCOMPP

SM_VREF0
SM_VREF1

PM_BMBUSY#
PM_EXTTS0#
PM_EXTTS1#
PM_THERMTRIP#
PWROK
RSTIN#

ICH_SYNC#

DMI

DDR MUXING

PM

2

PAD
PAD

1

2

DMI_TXN0
DMI_TXN1
DMI_TXN2
DMI_TXN3

DMI_TXP0
DMI_TXP1
DMI_TXP2
DMI_TXP3

DMI_RXN0
DMI_RXN1
DMI_RXN2
DMI_RXN3

DMI_RXP0
DMI_RXP1
DMI_RXP2
DMI_RXP3

M_CLK_DDR0
M_CLK_DDR1
M_CLK_DDR2
M_CLK_DDR3

M_CLK_DDR#0
M_CLK_DDR#1
M_CLK_DDR#2
M_CLK_DDR#3

DDR_CKE0_DIMMA
DDR_CKE1_DIMMA
DDR_CKE2_DIMMB
DDR_CKE3_DIMMB

DDR_CS0_DIMMA#
DDR_CS1_DIMMA#
DDR_CS2_DIMMB#
DDR_CS3_DIMMB#

M_OCDOCMP0
M_OCDOCMP1

M_ODT0
M_ODT1
M_ODT2
M_ODT3

SMRCOMPN
SMRCOMPP

PM_BMBUSY#
PM_EXTTS#0
DPRSLPVR
H_THERMTRIP#
ICH_POK
PLTRST_R#

12

+1.8V

12

R483

12

R481

Compal Secret Data

100_0402_1%

100_0402_1%

DMI_TXN0<29>
DMI_TXN1<29>
DMI_TXN2<29>
DMI_TXN3<29>

DMI_TXP0<29>
DMI_TXP1<29>
DMI_TXP2<29>
DMI_TXP3<29>

DMI_RXN0<29>
DMI_RXN1<29>
DMI_RXN2<29>
DMI_RXN3<29>

DMI_RXP0<29>
DMI_RXP1<29>
DMI_RXP2<29>
DMI_RXP3<29>

M_CLK_DDR0<13>
M_CLK_DDR1<13>
M_CLK_DDR2<14>
M_CLK_DDR3<14>

M_CLK_DDR#0<13>
M_CLK_DDR#1<13>
M_CLK_DDR#2<14>
M_CLK_DDR#3<14>

DDR_CKE0_DIMMA<13>
DDR_CKE1_DIMMA<13>
DDR_CKE2_DIMMB<14>
DDR_CKE3_DIMMB<14>

DDR_CS0_DIMMA#<13>
DDR_CS1_DIMMA#<13>
DDR_CS2_DIMMB#<14>
DDR_CS3_DIMMB#<14>

T17
T11

+1.8V

R40 80.6_0402_1%
R41 80.6_0402_1%

PLT_RST#<27,31,32,34,37>

V_DDR_MCH_REF<13,14>

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

M_ODT0<13>
M_ODT1<13>
M_ODT2<14>
M_ODT3<14>

1 2
1 2

V_DDR_MCH_REF

PM_BMBUSY#<29>
PM_EXTTS#0<13,14>
DPRSLPVR<29,53>

H_THERMTRIP#<4,28>

ICH_POK<29,44>

R98 100_0402_1%

MCH_ICH_SYNC#<27>

Layout Note:
V_DDR_MCH_REF
trace width and
spacing is 20/20.

V_DDR_MCH_REF

C663

0.1U_0402_16V4Z

2005/03/10 2006/03/10

CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8

CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG16

CFG

CFG17
CFG18
CFG19
CFG20

G_CLKP

G_CLKN

D_REF_CLKN

D_REF_CLKP

CLKNC

D_REF_SSCLKN
D_REF_SSCLKP

CLK_REQ#

NC0
NC1
NC2
NC3
NC4
NC5
NC6
NC7
NC8

NC9
NC10
NC11
NC12
NC13
NC14
NC15
NC16
NC17
NC18

RESERVED1
RESERVED2
RESERVED3
RESERVED4
RESERVED5
RESERVED6
RESERVED7
RESERVED8

RESERVED9
RESERVED10
RESERVED11
RESERVED12
RESERVED13

RESERVED

Title

Size Document Number Rev

Custom

Date: Sheet

Description at page15.

MCH_CLKSEL0

K16

MCH_CLKSEL1

K18

MCH_CLKSEL2

J18

CFG3

F18

CFG4

E15

CFG5

F15

CFG6

E18

CFG7

D19

CFG8

D16

CFG9

G16

CFG10

E16

CFG11

D15

CFG12

G15

CFG13

K15

CFG14

C15

CFG15

H16

CFG16

G18

CFG17

H15

CFG18

J25

CFG19

K27

CFG20

J26

CLK_MCH_3GPLL

AG33

CLK_MCH_3GPLL#

AF33

CLK_MCH_DREFCLK#

A27

CLK_MCH_DREFCLK

A26

MCH_SSCDREFCLK#

C40

MCH_SSCDREFCLK

D41

CLKREQB#

H32

A3
A39
A4
A40
AW1
AW41
AY1
BA1
BA2
BA3
BA39
BA40
BA41
C1
AY41
B2
B41
C41
D1

T32
R32
F3
F7
AG11
AF11
H7
J19
A41
A34
D28
D27
A35

PM_EXTTS#0

DPRSLPVR

PAD
PAD

PAD
PAD
PAD

PAD
PAD

PAD

R71

10K_0402_5%

R79

10K_0402_5%@

1 2

MCH_CLKSEL0 <15>
MCH_CLKSEL1 <15>

MCH_CLKSEL2 <15>

T6
T9

CFG5 <11>

T7

CFG7 <11>

T12

CFG9 <11>

T10

CFG11 <11>

CFG12 <11>

CFG13 <11>

T8

T16

CFG16 <11>

T14

CFG18 <11>

CFG19 <11>

CFG20 <11>

CLKREQB# <15>

12

Compal Electronics, Inc.

Calistoga (1/6)

LA-2841

1

CLK_MCH_3GPLL <15>
CLK_MCH_3GPLL# <15>

CLK_MCH_DREFCLK# <15>
CLK_MCH_DREFCLK <15>

MCH_SSCDREFCLK# <15>
MCH_SSCDREFCLK <15>

+3VS

of

760Friday, Decemb er 16, 2005

1.0

5

D D

4

3

2

1

DDR_A_BS#0<13>
DDR_A_BS#1<13>
DDR_A_BS#2<13>

DDR_A_DM[0..7]<13>

DDR_A_DQS[0..7]<13>

C C

DDR_A_DQS#[0..7]<13>

DDR_A_MA[0..13]<13>

B B

DDR_A_CAS#<13>
DDR_A_RAS#<13>

DDR_A_WE#<13>

T18 P AD
T19 P AD

DDR_A_BS#0
DDR_A_BS#1
DDR_A_BS#2

DDR_A_DM0
DDR_A_DM1
DDR_A_DM2
DDR_A_DM3
DDR_A_DM4
DDR_A_DM5
DDR_A_DM6
DDR_A_DM7

DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7

DDR_A_DQS#0
DDR_A_DQS#1
DDR_A_DQS#2
DDR_A_DQS#3
DDR_A_DQS#4
DDR_A_DQS#5
DDR_A_DQS#6
DDR_A_DQS#7

DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5

DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11 DDR_B_MA11
DDR_A_MA12
DDR_A_MA13

DDR_A_CAS#
DDR_A_RAS#
DDR_A_WE#
SA_RCVENIN#
SA_RCVENOUT#

U31D

AU12

SA_BS0

AV14

SA_BS1

BA20

SA_BS2

AJ33

SA_DM0

AM35

SA_DM1

AL26

SA_DM2

AN22

SA_DM3

AM14

SA_DM4

AL9

SA_DM5

AR3

SA_DM6

AH4

SA_DM7

AK33

SA_DQS0

AT33

SA_DQS1

AN28

SA_DQS2

AM22

SA_DQS3

AN12

SA_DQS4

AN8

SA_DQS5

AP3

SA_DQS6

AG5

SA_DQS7

AK32

SA_DQS0#

AU33

SA_DQS1#

AN27

SA_DQS2#

AM21

SA_DQS3#

AM12

SA_DQS4#

AL8

SA_DQS5#

AN3

SA_DQS6#

AH5

SA_DQS7#

AY16

SA_MA0

AU14

SA_MA1

AW16

SA_MA2

BA16

SA_MA3

BA17

SA_MA4

AU16

SA_MA5

AV17

SA_MA6

AU17

SA_MA7

AW17

SA_MA8

AT16

SA_MA9

AU13

SA_MA10

AT17

SA_MA11

AV20

SA_MA12

AV12

SA_MA13

AY13

SA_CAS#

AW14

SA_RAS#

AY14

SA_WE#

AK23

SA_RCVENIN#

AK24

SA_RCVENOUT#

CALISTOGA_FCBGA1466~D

SA_DQ0
SA_DQ1
SA_DQ2
SA_DQ3
SA_DQ4
SA_DQ5
SA_DQ6
SA_DQ7
SA_DQ8

SA_DQ9
SA_DQ10
SA_DQ11
SA_DQ12
SA_DQ13
SA_DQ14
SA_DQ15
SA_DQ16
SA_DQ17
SA_DQ18
SA_DQ19
SA_DQ20
SA_DQ21
SA_DQ22
SA_DQ23
SA_DQ24
SA_DQ25
SA_DQ26
SA_DQ27
SA_DQ28
SA_DQ29
SA_DQ30
SA_DQ31
SA_DQ32
SA_DQ33
SA_DQ34
SA_DQ35
SA_DQ36
SA_DQ37
SA_DQ38
SA_DQ39

DDR SYS MEMORY A

SA_DQ40
SA_DQ41
SA_DQ42
SA_DQ43
SA_DQ44
SA_DQ45
SA_DQ46
SA_DQ47
SA_DQ48
SA_DQ49
SA_DQ50
SA_DQ51
SA_DQ52
SA_DQ53
SA_DQ54
SA_DQ55
SA_DQ56
SA_DQ57
SA_DQ58
SA_DQ59
SA_DQ60
SA_DQ61
SA_DQ62
SA_DQ63

AJ35
AJ34
AM31
AM33
AJ36
AK35
AJ32
AH31
AN35
AP33
AR31
AP31
AN38
AM36
AM34
AN33
AK26
AL27
AM26
AN24
AK28
AL28
AM24
AP26
AP23
AL22
AP21
AN20
AL23
AP24
AP20
AT21
AR12
AR14
AP13
AP12
AT13
AT12
AL14
AL12
AK9
AN7
AK8
AK7
AP9
AN9
AT5
AL5
AY2
AW2
AP1
AN2
AV2
AT3
AN1
AL2
AG7
AF9
AG4
AF6
AG9
AH6
AF4
AF8

DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63

DDR_A_D[0..63] <13> DDR_B_D[0..63] <14>

DDR_B_BS#0<14>
DDR_B_BS#1<14>
DDR_B_BS#2<14>

DDR_B_DM[0..7]<14>

DDR_B_DQS[0..7]<14>

DDR_B_DQS#[0..7]<14>

DDR_B_MA[0..13]<14>

DDR_B_CAS#<14>

DDR_B_RAS#<14>

DDR_B_WE#<14>

T13 PAD
T15 PAD

DDR_B_BS#0
DDR_B_BS#1
DDR_B_BS#2

DDR_B_DM0
DDR_B_DM1
DDR_B_DM2
DDR_B_DM3
DDR_B_DM4
DDR_B_DM5
DDR_B_DM6
DDR_B_DM7

DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4
DDR_B_DQS5
DDR_B_DQS6
DDR_B_DQS7

DDR_B_DQS#0
DDR_B_DQS#1
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS#4
DDR_B_DQS#5
DDR_B_DQS#6
DDR_B_DQS#7

DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6DDR_A_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10

DDR_B_MA12
DDR_B_MA13

DDR_B_CAS#
DDR_B_RAS#
DDR_B_WE#
SB_RCVENIN#
SB_RCVENOUT#

U31E

AT24

SB_BS0

AV23

SB_BS1

AY28

SB_BS2

AK36

SB_DM0

AR38

SB_DM1

AT36

SB_DM2

BA31

SB_DM3

AL17

SB_DM4

AH8

SB_DM5

BA5

SB_DM6

AN4

SB_DM7

AM39

SB_DQS0

AT39

SB_DQS1

AU35

SB_DQS2

AR29

SB_DQS3

AR16

SB_DQS4

AR10

SB_DQS5

AR7

SB_DQS6

AN5

SB_DQS7

AM40

SB_DQS0#

AU39

SB_DQS1#

AT35

SB_DQS2#

AP29

SB_DQS3#

AP16

SB_DQS4#

AT10

SB_DQS5#

AT7

SB_DQS6#

AP5

SB_DQS7#

AY23

SB_MA0

AW24

SB_MA1

AY24

SB_MA2

AR28

SB_MA3

AT27

SB_MA4

AT28

SB_MA5

AU27

SB_MA6

AV28

SB_MA7

AV27

SB_MA8

AW27

SB_MA9

AV24

SB_MA10

BA27

SB_MA11

AY27

SB_MA12

AR23

SB_MA13

AR24

SB_CAS#

AU23

SB_RAS#

AR27

SB_WE#

AK16

SB_RCVENIN#

AK18

SB_RCVENOUT#

CALISTOGA_FCBGA1466~D

AK39

SB_DQ0

AJ37

SB_DQ1

AP39

SB_DQ2

AR41

SB_DQ3

AJ38

SB_DQ4

AK38

SB_DQ5

AN41

SB_DQ6

AP41

SB_DQ7

AT40

SB_DQ8

AV41

SB_DQ9

AU38

SB_DQ10

AV38

SB_DQ11

AP38

SB_DQ12

AR40

SB_DQ13

AW38

SB_DQ14

AY38

SB_DQ15

BA38

SB_DQ16

AV36

SB_DQ17

AR36

SB_DQ18

AP36

SB_DQ19

BA36

SB_DQ20

AU36

SB_DQ21

AP35

SB_DQ22

AP34

SB_DQ23

AY33

SB_DQ24

BA33

SB_DQ25

AT31

SB_DQ26

AU29

SB_DQ27

AU31

SB_DQ28

AW31

SB_DQ29

AV29

SB_DQ30

AW29

SB_DQ31

AM19

SB_DQ32

AL19

SB_DQ33

AP14

SB_DQ34

AN14

SB_DQ35

AN17

SB_DQ36

AM16

SB_DQ37

AP15

SB_DQ38

AL15

SB_DQ39
SB_DQ40
SB_DQ41
SB_DQ42
SB_DQ43
SB_DQ44
SB_DQ45
SB_DQ46
SB_DQ47
SB_DQ48
SB_DQ49
SB_DQ50
SB_DQ51
SB_DQ52
SB_DQ53
SB_DQ54
SB_DQ55
SB_DQ56
SB_DQ57
SB_DQ58
SB_DQ59
SB_DQ60
SB_DQ61
SB_DQ62
SB_DQ63

AJ11
AH10
AJ9
AN10
AK13
AH11
AK10
AJ8
BA10
AW10
BA4
AW4
AY10
AY9
AW5
AY5
AV4
AR5
AK4
AK3
AT4
AK5
AJ5
AJ3

DDR SYS MEMORY B

DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63

A A

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/03/10 2006/03/10

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

Compal Electronics, Inc.

Calistoga (2/6)

LA-2841

1

1.0

of

860Friday, Decemb er 16, 2005

5

D D

LVDSA0+<16>
LVDSA1+<16>

LVDSA2+<16>
LVDSA0-<16>

LVDSA1-<16>

LVDSA2-<16>

LVDSB0+<16>
LVDSB1+<16>
LVDSB2+<16>

LVDSB0-<16>
LVDSB1-<16>
LVDSB2-<16>

LVDSAC+<16>

LVDSAC-<16>
LVDSBC+<16>
LVDSBC-<16>

C C

B B

GMCH_ENBKL<16>

EDID_CLK_LCD<16>
EDID_DAT_LCD<16>

GMCH_LVDDEN<16>

TV_COMPS<17>
TV_LUMA<17>
TV_CRMA<17>

3VDDCCL<17>

3VDDCDA<17>

CRT_VSYNC<17>
CRT_HSYNC<17>

CRT_B<17>
CRT_G<17>
CRT_R<17>

R482 1.5K_0402_1%

TV_COMPS
TV_LUMA
TV_CRMA

4

LVDSA0+
LVDSA1+
LVDSA2+

LVDSA0­LVDSA1­LVDSA2-

LVDSB0+
LVDSB1+
LVDSB2+

LVDSB0­LVDSB1­LVDSB2-

LVDSAC+
LVDSAC­LVDSBC+
LVDSBC-

GMCH_ENBKL

EDID_CLK_LCD
EDID_DAT_LCD

GMCH_LVDDEN

12

R58

12

4.99K_0402_1%

3VDDCCL
3VDDCDA

CRT_VSYNC
CRT_HSYNC
CRT_B

CRT_G
CRT_R

R65

12

255_0402_1%

U31C

H27

SDVOCTRL_DATA

H28

SDVOCTRL_CLK

B37

LA_DATA0

B34

LA_DATA1

A36

LA_DATA2

C37

LA_DATA#0

B35

LA_DATA#1

A37

LA_DATA#2

F30

LB_DATA0

D29

LB_DATA1

F28

LB_DATA2

G30

LB_DATA#0

D30

LB_DATA#1

F29

LB_DATA#2

A32

LA_CLK

A33

LA_CLK#

E26

LB_CLK

E27

LB_CLK#

D32

LBKLT_CTL

J30

LBKLT_EN

H30

LCTLA_CLK

H29

LCTLB_DATA

G26

LDDC_CLK

G25

LDDC_DATA

F32

LVDD_EN

B38

LIBG

C35

LVBG

C33

LVREFH

C32

LVREFL

A16

TVDAC_A

C18

TVDAC_B

A19

TVDAC_C

J20

TV_IREF

B16

TV_IRTNA

B18

TV_IRTNB

B19

TV_IRTNC

J29

TV_DCONSEL1

K30

TV_DCONSEL0

C26

DDCCLK

C25

DDCDATA

H23

VSYNC

G23

HSYNC

E23

BLUE

D23

BLUE#

C22

GREEN

B22

GREEN#

A21

RED

B21

RED#

J22

CRT_IREF

CALISTOGA_FCBGA1466~D

3

+1.5VS_PCIE

R89

PEGCOMP

D40

EXP_COMPI

EXP_RXN0
EXP_RXN1
EXP_RXN2
EXP_RXN3
EXP_RXN4
EXP_RXN5
EXP_RXN6
EXP_RXN7
EXP_RXN8

EXP_RXN9
EXP_RXN10
EXP_RXN11
EXP_RXN12
EXP_RXN13
EXP_RXN14
EXP_RXN15

EXP_RXP0

EXP_RXP1

EXP_RXP2

EXP_RXP3

EXP_RXP4

EXP_RXP5

EXP_RXP6

EXP_RXP7

EXP_RXP8

EXP_RXP9
EXP_RXP10
EXP_RXP11
EXP_RXP12
EXP_RXP13
EXP_RXP14
EXP_RXP15

EXP_TXN0

EXP_TXN1

EXP_TXN2

EXP_TXN3

EXP_TXN4

EXP_TXN5

EXP_TXN6

EXP_TXN7

EXP_TXN8

EXP_TXN9
EXP_TXN10
EXP_TXN11
EXP_TXN12
EXP_TXN13
EXP_TXN14
EXP_TXN15

EXP_TXP0

EXP_TXP1

EXP_TXP2

EXP_TXP3

EXP_TXP4

EXP_TXP5

EXP_TXP6

EXP_TXP7

EXP_TXP8

EXP_TXP9

EXP_TXP10
EXP_TXP11
EXP_TXP12
EXP_TXP13
EXP_TXP14
EXP_TXP15

D38
F34

G38
H34
J38
L34
M38
N34
P38
R34
T38
V34
W38
Y34
AA38
AB34
AC38

D34
F38
G34
H38
J34
L38
M34
N38
P34
R38
T34
V38
W34
Y38
AA34
AB38

F36
G40
H36
J40
L36
M40
N36
P40
R36
T40
V36
W40
Y36
AA40
AB36
AC40

D36
F40
G36
H40
J36
L40
M36
N40
P36
R40
T36
V40
W36
Y40
AA36
AB40

PEG_RXN0
PEG_RXN1
PEG_RXN2
PEG_RXN3
PEG_RXN4
PEG_RXN5
PEG_RXN6
PEG_RXN7
PEG_RXN8
PEG_RXN9
PEG_RXN10
PEG_RXN11
PEG_RXN12
PEG_RXN13
PEG_RXN14
PEG_RXN15

PEG_RXP0
PEG_RXP1
PEG_RXP2
PEG_RXP3
PEG_RXP4
PEG_RXP5
PEG_RXP6
PEG_RXP7
PEG_RXP8
PEG_RXP9
PEG_RXP10
PEG_RXP11
PEG_RXP12
PEG_RXP13
PEG_RXP14
PEG_RXP15

PEG_TXN0
PEG_TXN1
PEG_TXN2
PEG_TXN3
PEG_TXN4
PEG_TXN5
PEG_TXN6
PEG_TXN7
PEG_TXN8
PEG_TXN9
PEG_TXN10
PEG_TXN11
PEG_TXN12
PEG_TXN13
PEG_TXN14
PEG_TXN15

PEG_TXP0
PEG_TXP1
PEG_TXP2
PEG_TXP3
PEG_TXP4
PEG_TXP5
PEG_TXP6
PEG_TXP7
PEG_TXP8
PEG_TXP9
PEG_TXP10
PEG_TXP11
PEG_TXP12
PEG_TXP13
PEG_TXP14
PEG_TXP15

EXP_COMPO

LVDS

TV CRT

PCI-EXPRESS GRAPHICS

24.9_0402_1%

1 2

C231 0.1U_0402_16V4ZG71@
C661 0.1U_0402_16V4ZG71@
C230 0.1U_0402_16V4ZG71@
C659 0.1U_0402_16V4ZG71@
C228 0.1U_0402_16V4ZG71@
C657 0.1U_0402_16V4ZG71@
C237 0.1U_0402_16V4ZG71@
C655 0.1U_0402_16V4ZG71@
C238 0.1U_0402_16V4ZG71@
C653 0.1U_0402_16V4ZG71@
C239 0.1U_0402_16V4ZG71@
C651 0.1U_0402_16V4ZG71@
C250 0.1U_0402_16V4ZG71@
C649 0.1U_0402_16V4ZG71@
C677 0.1U_0402_16V4ZG71@
C648 0.1U_0402_16V4ZG71@

C229 0.1U_0402_16V4ZG71@
C662 0.1U_0402_16V4ZG71@
C232 0.1U_0402_16V4ZG71@
C660 0.1U_0402_16V4ZG71@
C233 0.1U_0402_16V4ZG71@
C658 0.1U_0402_16V4ZG71@
C234 0.1U_0402_16V4ZG71@
C656 0.1U_0402_16V4ZG71@
C235 0.1U_0402_16V4ZG71@
C654 0.1U_0402_16V4ZG71@
C236 0.1U_0402_16V4ZG71@
C652 0.1U_0402_16V4ZG71@
C249 0.1U_0402_16V4ZG71@
C650 0.1U_0402_16V4ZG71@
C678 0.1U_0402_16V4ZG71@
C664 0.1U_0402_16V4ZG71@

PEG_RXP[0..15] <18>

PEG_RXN[0..15] <18>

PEG_M_TXN0
PEG_M_TXN1
PEG_M_TXN2
PEG_M_TXN3
PEG_M_TXN4
PEG_M_TXN5
PEG_M_TXN6
PEG_M_TXN7
PEG_M_TXN8
PEG_M_TXN9
PEG_M_TXN10
PEG_M_TXN11
PEG_M_TXN12
PEG_M_TXN13
PEG_M_TXN14
PEG_M_TXN15

PEG_M_TXP0
PEG_M_TXP1
PEG_M_TXP2
PEG_M_TXP3
PEG_M_TXP4
PEG_M_TXP5
PEG_M_TXP6
PEG_M_TXP7
PEG_M_TXP8
PEG_M_TXP9
PEG_M_TXP10
PEG_M_TXP11
PEG_M_TXP12
PEG_M_TXP13
PEG_M_TXP14
PEG_M_TXP15

2

PEG_M_TXP[0..15] <18>

PEG_M_TXN[0..15] <18>

1

A A

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/03/10 2006/03/10

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

Compal Electronics, Inc.

Calistoga (3/6)

LA-2841

1

1.0

of

960Friday, Decemb er 16, 2005

5

+VCCP

21

D D

C C

B B

A A

D5

CH751H-40_SC76@

CH751H-40_SC76@

12

+2.5VS

R80

10_0402_5%@

+1.5VS

21

D19

12

+3VS

R520

10_0402_5%@

1

C613

C612

2

4.7U_0805_10V4Z

1

C81

2

1

0.22U_0603_10V7K

2

1

+

C610

220U_D2_4VM

2

1

2

2.2U_0805_16V4Z

MCH_A6

1

C607

2

MCH_D2

C597

0.22U_0603_10V7K

C596

+1.5VS

+VCCP

0.47U_0603_10V7K

MCH_AB1

1

2

0.47U_0603_10V7K

U31H

AC14

VTT0

AB14

VTT1

W14

VTT2

V14

VTT3

T14

VTT4

R14

VTT5

P14

VTT6

N14

VTT7

M14

VTT8

L14

VTT9

AD13

VTT10

AC13

VTT11

AB13

VTT12

AA13

VTT13

Y13

VTT14

W13

VTT15

V13

VTT16

U13

VTT17

T13

VTT18

R13

VTT19

N13

VTT20

M13

VTT21

L13

VTT22

AB12

VTT23

AA12

VTT24

Y12

VTT25

W12

VTT26

V12

VTT27

U12

VTT28

T12

VTT29

R12

VTT30

P12

VTT31

N12

VTT32

M12

VTT33

L12

VTT34

R11

VTT35

P11

VTT36

N11

VTT37

M11

VTT38

R10

VTT39

P10

VTT40

N10

VTT41

M10

VTT42

P9

VTT43

N9

VTT44

M9

VTT45

R8

VTT46

P8

VTT47

N8

VTT48

M8

VTT49

P7

VTT50

N7

VTT51

M7

VTT52

R6

VTT53

P6

VTT54

M6

VTT55

A6

VTT56

R5

VTT57

P5

VTT58

N5

VTT59

M5

VTT60

P4

VTT61

N4

VTT62

M4

VTT63

R3

VTT64

P3

VTT65

N3

VTT66

M3

VTT67

R2

VTT68

P2

VTT69

M2

VTT70

D2

VTT71

AB1

VTT72

R1

VTT73

P1

VTT74

N1

VTT75

M1

VTT76

AG14

VCCAUX32

AF14

VCCAUX33

AE14

VCCAUX34

Y14

VCCAUX35

AF13

VCCAUX36

AE13

VCCAUX37

AF12

VCCAUX38

AE12

VCCAUX39

AD12

VCCAUX40

CALISTOGA_FCBGA1466~D

P O W E R

4

VCCA_CRTDAC0
VCCA_CRTDAC1
VSSA_CRTDAC2

VCCA_TVDACA0
VCCA_TVDACA1
VCCA_TVDACB0
VCCA_TVDACB1
VCCA_TVDACC0
VCCA_TVDACC1

VCCDQ_TVDAC

VCC_SYNC

VCCTX_LVDS0
VCCTX_LVDS1
VCCTX_LVDS2

VCC3G0
VCC3G1
VCC3G2
VCC3G3
VCC3G4
VCC3G5
VCC3G6

VCCA_3GPLL

VCCA_3GBG
VSSA_3GBG

VCCA_DPLLA
VCCA_DPLLB

VCCA_HPLL

VCCA_LVDS

VSSA_LVDS

VCCA_MPLL
VCCA_TVBG

VSSA_TVBG

VCCD_HMPLL0
VCCD_HMPLL1

VCCD_LVDS0
VCCD_LVDS1
VCCD_LVDS2

VCCD_TVDAC

VCCHV0
VCCHV1
VCCHV2

VCCAUX0
VCCAUX1
VCCAUX2
VCCAUX3
VCCAUX4
VCCAUX5
VCCAUX6
VCCAUX7
VCCAUX8

VCCAUX9
VCCAUX10
VCCAUX11
VCCAUX12
VCCAUX13
VCCAUX14
VCCAUX15
VCCAUX16
VCCAUX17
VCCAUX18
VCCAUX19
VCCAUX20
VCCAUX21
VCCAUX22
VCCAUX23
VCCAUX24
VCCAUX25
VCCAUX26
VCCAUX27
VCCAUX28
VCCAUX29
VCCAUX30
VCCAUX31

H22

B30
C30
A30

AB41
AJ41
L41
N41
R41
V41
Y41

AC33
G41
H41

E21
F21
G21

B26
C39
AF1

A38
B39

AF2
H20

G20

E19
F19
C20
D20
E20
F20

AH1
AH2

A28
B28
C28

D21
H19

A23
B23
B25

AK31
AF31
AE31
AC31
AL30
AK30
AJ30
AH30
AG30
AF30
AE30
AD30
AC30
AG29
AF29
AE29
AD29
AC29
AG28
AF28
AE28
AH22
AJ21
AH21
AJ20
AH20
AH19
P19
P16
AH15
P15
AH14

+2.5VS

1 2

C162

0.1U_0402_16V4Z

+2.5VS

W=40 mils

+1.5VS_3GPLL
+2.5VS

+2.5VS_CRTDAC

+1.5VS_DPLLA
+1.5VS_DPLLB
+1.5VS_HPLL

+2.5VS

+1.5VS_MPLL
+3VS_TVBG

+3VS_TVDACA
+3VS_TVDACB
+3VS_TVDACC

+1.5VS

+1.5VS_TVDAC

1

2

C124

0.1U_0402_16V4Z

+1.5VS

1

C163

2

+1.5VS_PCIE

1

+

C682

2

1

2

C615

10U_1206_6.3V6M

0.1U_0402_16V4Z

220U_D2_4VM

1

2

+3VS

1

C666

2

C115

3

0_0805_5%

1

C665

2

10U_1206_6.3V6M

10U_1206_6.3V6M

L7 BLM11A601S_0603

1 2

1

C116

2

2200P_0402_50V7K

0.1U_0402_16V4Z

1

2

R490

12

+1.5VS

+2.5VS

CRTDAC: Route caps within
250mil of Alviso. Route FB
within 3" of Calistoga

+2.5VS

1

1

C215

C160

2

2

0.1U_0402_16V4Z

0.01U_0402_16V7K

close pin A38

R39

12

0_0805_5%

C117

0.1U_0402_16V4Z

C112

2200P_0402_50V7K

1

2

+2.5VS

1

C225

2

0.1U_0402_16V4Z

close pin G41

1

2

+3VS+3VS_TVBG

2

C110

2200P_0402_50V7K

1

2

0_0805_5%

C111

0.1U_0402_16V4Z

+1.5VS_DPLLA +1.5VS_DPLLB

0.1U_0402_16V4Z

C138

1

2

R52

12

MBK160808_0603

330U_V_2.5VK_R9

UMA@

1

C616

+

2

1

C114

2

L28

1

2

2200P_0402_50V7K

12

R55

0_0805_5%

C109

0.1U_0402_16V4Z

PCI-E/MEM/PSB PLL decoupling

+1.5VS+1.5VS_3GPLL

R99
0_0603_5%

12

1

1

C248

C174

2

2

0.1U_0402_16V4Z

10U_1206_6.3V6M

+1.5VS_MPLL

45mA Max. 45mA Max.

C604

1

2

0.1U_0402_16V4Z

R459
0_0603_5%

1

C593

2

10U_1206_6.3V6M

12

1

C280

2

0.1U_0402_16V4Z

@

1

L29

MBK160808_0603

0.1U_0402_16V4Z

330U_V_2.5VK_R9

UMA@

1

C226

C645

1

+

2

2

12

+1.5VS_TVDAC +1.5VS

C113

1

C614

2

0.1U_0402_16V4Z

+1.5VS_HPLL

1

2

1

2

2200P_0402_50V7K

1

C605

2

0.1U_0402_16V4Z

1

C107

2

2200P_0402_50V7K

R46
0_0603_5%

1

C594

2

C106

0.1U_0402_16V4Z

12

C105

R460
0_0603_5%

10U_1206_6.3V6M

0_0805_5%

@

12

R44

1

2

0.1U_0402_16V4Z

12

+1.5VS+1.5VS

+3VS+3VS_TVDACA+3VS+3VS_TVDACB+3VS+3VS _TVDACC

12

+1.5VS+1.5VS

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETE NT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/03/10 2006/03/10

Compal Secret Data

Deciphered Date

Title

Size Docum ent Number Rev

Custom

2

Date: Sheet

Compal Electronics, Inc.

Calistoga (4/6)

LA-2841

1

1.0

of

10 60Friday, December 16, 2005

5

4

3

2

1

Strap Pin Table

CFG[3:17] have internal pull up

+VCCP

D D

1

C86

2

0.22U_0603_10V7K

1

C173

2

10U_1206_6.3V6M

C C

B B

C164

C600

C595

C606

1

1

C85

2

2

0.22U_0603_10V7K

0.22U_0603_10V7K

1

1

C139

2

2

1U_0603_10V4Z

10U_1206_6.3V6M

1

+

220U_D2_4VM@

2

1

+

220U_D2_4VM@

2

+VCCP

U31F

AD27

VCC_NCTF0

AC27

VCC_NCTF1

AB27

VCC_NCTF2

AA27

VCC_NCTF3

Y27

VCC_NCTF4

W27

VCC_NCTF5

V27

VCC_NCTF6

U27

VCC_NCTF7

T27

VCC_NCTF8

R27

VCC_NCTF9

AD26

VCC_NCTF10

AC26

VCC_NCTF11

AB26

VCC_NCTF12

AA26

VCC_NCTF13

Y26

VCC_NCTF14

W26

VCC_NCTF15

V26

VCC_NCTF16

U26

VCC_NCTF17

T26

VCC_NCTF18

R26

VCC_NCTF19

AD25

VCC_NCTF20

AC25

VCC_NCTF21

AB25

VCC_NCTF22

AA25

VCC_NCTF23

Y25

VCC_NCTF24

W25

VCC_NCTF25

V25

VCC_NCTF26

U25

VCC_NCTF27

T25

VCC_NCTF28

R25

VCC_NCTF29

AD24

VCC_NCTF30

AC24

VCC_NCTF31

AB24

VCC_NCTF32

AA24

VCC_NCTF33

Y24

VCC_NCTF34

W24

VCC_NCTF35

V24

VCC_NCTF36

U24

VCC_NCTF37

T24

VCC_NCTF38

R24

VCC_NCTF39

AD23

VCC_NCTF40

V23

VCC_NCTF41

U23

VCC_NCTF42

T23

VCC_NCTF43

R23

VCC_NCTF44

AD22

VCC_NCTF45

V22

VCC_NCTF46

U22

VCC_NCTF47

T22

VCC_NCTF48

R22

VCC_NCTF49

AD21

VCC_NCTF50

V21

VCC_NCTF51

U21

VCC_NCTF52

T21

VCC_NCTF53

R21

VCC_NCTF54

AD20

VCC_NCTF55

V20

VCC_NCTF56

U20

VCC_NCTF57

T20

VCC_NCTF58

R20

VCC_NCTF59

AD19

VCC_NCTF60

V19

VCC_NCTF61

U19

VCC_NCTF62

T19

VCC_NCTF63

AD18

VCC_NCTF64

AC18

VCC_NCTF65

AB18

VCC_NCTF66

AA18

VCC_NCTF67

Y18

VCC_NCTF68

W18

VCC_NCTF69

V18

VCC_NCTF70

U18

VCC_NCTF71

T18

VCC_NCTF72

M19

VCC100

L19

VCC101

N18

VCC102

M18

VCC103

L18

VCC104

P17

VCC105

N17

VCC106

M17

VCC107

N16

VCC108

M16

VCC109

L16

VCC110

CALISTOGA_FCBGA1466~D

VCCAUX_NCTF0
VCCAUX_NCTF1
VCCAUX_NCTF2
VCCAUX_NCTF3
VCCAUX_NCTF4
VCCAUX_NCTF5
VCCAUX_NCTF6
VCCAUX_NCTF7
VCCAUX_NCTF8

VCCAUX_NCTF9
VCCAUX_NCTF10
VCCAUX_NCTF11
VCCAUX_NCTF12
VCCAUX_NCTF13
VCCAUX_NCTF14
VCCAUX_NCTF15
VCCAUX_NCTF16
VCCAUX_NCTF17
VCCAUX_NCTF18
VCCAUX_NCTF19
VCCAUX_NCTF20
VCCAUX_NCTF21
VCCAUX_NCTF22
VCCAUX_NCTF23
VCCAUX_NCTF24
VCCAUX_NCTF25
VCCAUX_NCTF26
VCCAUX_NCTF27
VCCAUX_NCTF28
VCCAUX_NCTF29
VCCAUX_NCTF30
VCCAUX_NCTF31
VCCAUX_NCTF32
VCCAUX_NCTF33
VCCAUX_NCTF34
VCCAUX_NCTF35
VCCAUX_NCTF36

P O W E R

VCCAUX_NCTF37
VCCAUX_NCTF38
VCCAUX_NCTF39
VCCAUX_NCTF40
VCCAUX_NCTF41
VCCAUX_NCTF42
VCCAUX_NCTF43
VCCAUX_NCTF44
VCCAUX_NCTF45
VCCAUX_NCTF46
VCCAUX_NCTF47
VCCAUX_NCTF48
VCCAUX_NCTF49
VCCAUX_NCTF50
VCCAUX_NCTF51
VCCAUX_NCTF52
VCCAUX_NCTF53
VCCAUX_NCTF54
VCCAUX_NCTF55
VCCAUX_NCTF56
VCCAUX_NCTF57

VSS_NCTF0
VSS_NCTF1
VSS_NCTF2
VSS_NCTF3
VSS_NCTF4
VSS_NCTF5
VSS_NCTF6
VSS_NCTF7
VSS_NCTF8

VSS_NCTF9
VSS_NCTF10
VSS_NCTF11
VSS_NCTF12

VCC_SM100

VCC_SM101

VCC_SM102

VCC_SM103

VCC_SM104

VCC_SM105

VCC_SM106

VCC_SM107

AG27
AF27
AG26
AF26
AG25
AF25
AG24
AF24
AG23
AF23
AG22
AF22
AG21
AF21
AG20
AF20
AG19
AF19
R19
AG18
AF18
R18
AG17
AF17
AE17
AD17
AB17
AA17
W17
V17
T17
R17
AG16
AF16
AE16
AD16
AC16
AB16
AA16
Y16
W16
V16
U16
T16
R16
AG15
AF15
AE15
AD15
AC15
AB15
AA15
Y15
W15
V15
U15
T15
R15

AE27
AE26
AE25
AE24
AE23
AE22
AE21
AE20
AE19
AE18
AC17
Y17
U17

AR6
AP6
AN6
AL6
AK6
AJ6
AV1
AJ1

+1.5VS

C603

+1.8V

0.47U_0603_10V7K

1

1

C602

2

2

0.47U_0603_10V7K

Place near pin AV1 & AJ1

A A

+VCCP

U31G

AA33

VCC0

W33

VCC1

P33

VCC2

N33

VCC3

L33

VCC4

J33

VCC5

AA32

VCC6

Y32

VCC7

W32

VCC8

V32

VCC9

P32

VCC10

N32

VCC11

M32

VCC12

L32

VCC13

J32

VCC14

AA31

VCC15

W31

VCC16

V31

VCC17

T31

VCC18

R31

VCC19

P31

VCC20

N31

VCC21

M31

VCC22

AA30

VCC23

Y30

VCC24

W30

VCC25

V30

VCC26

U30

VCC27

T30

VCC28

R30

VCC29

P30

VCC30

N30

VCC31

M30

VCC32

L30

VCC33

AA29

VCC34

Y29

VCC35

W29

VCC36

V29

VCC37

U29

VCC38

R29

VCC39

P29

VCC40

M29

VCC41

L29

VCC42

AB28

VCC43

AA28

VCC44

Y28

VCC45

V28

VCC46

U28

VCC47

T28

VCC48

R28

VCC49

P28

VCC50

N28

VCC51

M28

VCC52

L28

VCC53

P27

VCC54

N27

VCC55

M27

VCC56

L27

VCC57

P26

VCC58

N26

VCC59

L26

VCC60

N25

VCC61

M25

VCC62

L25

VCC63

P24

VCC64

N24

VCC65

M24

VCC66

AB23

VCC67

AA23

VCC68

Y23

VCC69

P23

VCC70

N23

VCC71

M23

VCC72

L23

VCC73

AC22

VCC74

AB22

VCC75

Y22

VCC76

W22

VCC77

P22

VCC78

N22

VCC79

M22

VCC80

L22

VCC81

AC21

VCC82

AA21

VCC83

W21

VCC84

N21

VCC85

M21

VCC86

L21

VCC87

AC20

VCC88

AB20

VCC89

Y20

VCC90

W20

VCC91

P20

VCC92

N20

VCC93

M20

VCC94

L20

VCC95

AB19

VCC96

AA19

VCC97

Y19

VCC98

N19

VCC99

CALISTOGA_FCBGA1466~D

P O W E R

VCC_SM0
VCC_SM1
VCC_SM2
VCC_SM3
VCC_SM4
VCC_SM5
VCC_SM6
VCC_SM7
VCC_SM8

VCC_SM9
VCC_SM10
VCC_SM11
VCC_SM12
VCC_SM13
VCC_SM14
VCC_SM15
VCC_SM16
VCC_SM17
VCC_SM18
VCC_SM19
VCC_SM20
VCC_SM21
VCC_SM22
VCC_SM23
VCC_SM24
VCC_SM25
VCC_SM26
VCC_SM27
VCC_SM28
VCC_SM29
VCC_SM30
VCC_SM31
VCC_SM32
VCC_SM33
VCC_SM34
VCC_SM35
VCC_SM36
VCC_SM37
VCC_SM38
VCC_SM39
VCC_SM40
VCC_SM41
VCC_SM42
VCC_SM43
VCC_SM44
VCC_SM45
VCC_SM46
VCC_SM47
VCC_SM48
VCC_SM49
VCC_SM50
VCC_SM51
VCC_SM52
VCC_SM53
VCC_SM54
VCC_SM55
VCC_SM56
VCC_SM57
VCC_SM58
VCC_SM59
VCC_SM60
VCC_SM61
VCC_SM62
VCC_SM63
VCC_SM64
VCC_SM65
VCC_SM66
VCC_SM67
VCC_SM68
VCC_SM69
VCC_SM70
VCC_SM71
VCC_SM72
VCC_SM73
VCC_SM74
VCC_SM75
VCC_SM76
VCC_SM77
VCC_SM78
VCC_SM79
VCC_SM80
VCC_SM81
VCC_SM82
VCC_SM83
VCC_SM84
VCC_SM85
VCC_SM86
VCC_SM87
VCC_SM88
VCC_SM89
VCC_SM90
VCC_SM91
VCC_SM92
VCC_SM93
VCC_SM94
VCC_SM95
VCC_SM96
VCC_SM97
VCC_SM98
VCC_SM99

AU41
AT41
AM41
AU40
BA34
AY34
AW34
AV34
AU34
AT34
AR34
BA30
AY30
AW30
AV30
AU30
AT30
AR30
AP30
AN30
AM30
AM29
AL29
AK29
AJ29
AH29
AJ28
AH28
AJ27
AH27
BA26
AY26
AW26
AV26
AU26
AT26
AR26
AJ26
AH26
AJ25
AH25
AJ24
AH24
BA23
AJ23
BA22
AY22
AW22
AV22
AU22
AT22
AR22
AP22
AK22
AJ22
AK21
AK20
BA19
AY19
AW19
AV19
AU19
AT19
AR19
AP19
AK19
AJ19
AJ18
AJ17
AH17
AJ16
AH16
BA15
AY15
AW15
AV15
AU15
AT15
AR15
AJ15
AJ14
AJ13
AH13
AK12
AJ12
AH12
AG12
AK11
BA8
AY8
AW8
AV8
AT8
AR8
AP8
BA6
AY6
AW6
AV6
AT6

+1.8V

MCH_AT41
MCH_AM41

C669

1

1

C668

2

2

0.47U_0603_10V7K

0.47U_0603_10V7K

Place near pin AT41 & AM41

1

1

C83

C222

2

C125

2

0.1U_0402_16V4Z

1

2

0.47U_0603_10V7K

Place near pin BA23

1

1

C641

C609

C104

2

2

10U_1206_6.3V6M

10U_1206_6.3V6M

1

2

0.47U_0603_10V7K

Place near pin BA15

CFG[2:0]

CFG5

CFG7

CFG9

CFG6

PSB 4X CLK Enable 1 = Calistoga

CFG[13:12]

CFG16

0.1U_0402_16V4Z

CFG10 CFG18

CFG19

SDVO_CTRLDATA

1

1

C84

C128

2

0.1U_0402_16V4Z

2

0.1U_0402_16V4Z

CFG20

(PCIE/SDVO select)

1

+

C599

2

330U_V_2.5VK_R9

CFG[19:18] have internal pull down

011 = 667MT/s FSB
001 = 533MT/s FSB

0 = DMI x 2
1 = DMI x 4

0 = Reserved
1 = Mobile Yonah CPU

0 = Lane Reversal Enable
1 = Normal Operation

(Default)

*

(Default)

*

(Default)

0 = Reserved

*

00 = Reserved
01 = XOR Mode Enabled
10 = All Z Mode Enabled
11 = Normal Operation

0 = Dynamic ODT Disabled
1 = Dynamic ODT Enabled (Default)

10 = 1.05V
01 = 1.5V

0 = Normal Operation
1 = DMI Lane Reversal Enable

0 = No SDVO Device Present

*

(Default)

(Default)

1 = SDVO Device Present

0 = Only PCIE or SDVO is
operational.
1 = PCIE/SDVO are operating
simu.

R48 2.2K_0402_5%@

CFG5<7>

R54 2.2K_0402_5%@

CFG7<7>

R51 2.2K_0402_5%@

CFG9<7>
CFG11<7>
CFG12<7>
CFG13<7>
CFG16<7>

CFG18<7>
CFG19<7>
CFG20<7>

R47 2.2K_0402_5%@
R49 2.2K_0402_5%@
R50 2.2K_0402_5%@
R53 2.2K_0402_5%@

R74 1K_0402_5%@
R82 1K_0402_5%@
R87 1K_0402_5%@

*

1 2
1 2
1 2
1 2
1 2
1 2
1 2

1 2
1 2
1 2

*

*

(Default)

*

(Default)

*

(Default)

*

+3VS

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/03/10 2006/03/10

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

Compal Electronics, Inc.

Calistoga (5/6)

LA-2841

1

1.0

of

11 60F r ida y, D ec em be r 1 6, 2005

5

4

3

2

1

U31I

AC41

VSS0

AA41

VSS1

W41

VSS2

T41

VSS3

P41

VSS4

M41

D D

C C

B B

A A

VSS5

J41

VSS6

F41

VSS7

AV40

VSS8

AP40

VSS9

AN40

VSS10

AK40

VSS11

AJ40

VSS12

AH40

VSS13

AG40

VSS14

AF40

VSS15

AE40

VSS16

B40

VSS17

AY39

VSS18

AW39

VSS19

AV39

VSS20

AR39

VSS21

AN39

VSS22

AJ39

VSS23

AC39

VSS24

AB39

VSS25

AA39

VSS26

Y39

VSS27

W39

VSS28

V39

VSS29

T39

VSS30

R39

VSS31

P39

VSS32

N39

VSS33

M39

VSS34

L39

VSS35

J39

VSS36

H39

VSS37

G39

VSS38

F39

VSS39

D39

VSS40

AT38

VSS41

AM38

VSS42

AH38

VSS43

AG38

VSS44

AF38

VSS45

AE38

VSS46

C38

VSS47

AK37

VSS48

AH37

VSS49

AB37

VSS50

AA37

VSS51

Y37

VSS52

W37

VSS53

V37

VSS54

T37

VSS55

R37

VSS56

P37

VSS57

N37

VSS58

M37

VSS59

L37

VSS60

J37

VSS61

H37

VSS62

G37

VSS63

F37

VSS64

D37

VSS65

AY36

VSS66

AW36

VSS67

AN36

VSS68

AH36

VSS69

AG36

VSS70

AF36

VSS71

AE36

VSS72

AC36

VSS73

C36

VSS74

B36

VSS75

BA35

VSS76

AV35

VSS77

AR35

VSS78

AH35

VSS79

AB35

VSS80

AA35

VSS81

Y35

VSS82

W35

VSS83

V35

VSS84

T35

VSS85

R35

VSS86

P35

VSS87

N35

VSS88

M35

VSS89

L35

VSS90

J35

VSS91

H35

VSS92

G35

VSS93

F35

VSS94

D35

VSS95

AN34

VSS96

AK34

VSS97

AG34

VSS98

AF34

VSS99

CALISTOGA_FCBGA1466~D

P O W E R

VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS140
VSS141
VSS142
VSS143
VSS144
VSS145
VSS146
VSS147
VSS148
VSS149
VSS150
VSS151
VSS152
VSS153
VSS154
VSS155
VSS156
VSS157
VSS158
VSS159
VSS160
VSS161
VSS162
VSS163
VSS164
VSS165
VSS166
VSS167
VSS168
VSS169
VSS170
VSS171
VSS172
VSS173
VSS174
VSS175
VSS176
VSS177
VSS178
VSS179
VSS180
VSS181
VSS182
VSS183
VSS184
VSS185
VSS186
VSS187
VSS188
VSS189
VSS190
VSS191
VSS192
VSS193
VSS194
VSS195
VSS196
VSS197
VSS198
VSS199

AE34
AC34
C34
AW33
AV33
AR33
AE33
AB33
Y33
V33
T33
R33
M33
H33
G33
F33
D33
B33
AH32
AG32
AF32
AE32
AC32
AB32
G32
B32
AY31
AV31
AN31
AJ31
AG31
AB31
Y31
AB30
E30
AT29
AN29
AB29
T29
N29
K29
G29
E29
C29
B29
A29
BA28
AW28
AU28
AP28
AM28
AD28
AC28
W28
J28
E28
AP27
AM27
AK27
J27
G27
F27
C27
B27
AN26
M26
K26
F26
D26
AK25
P25
K25
H25
E25
D25
A25
BA24
AU24
AL24
AW23
AT23
AN23
AM23
AH23
AC23
W23
K23
J23
F23
C23
AA22
K22
G22
F22
E22
D22
A22
BA21
AV21
AR21

U31J

AN21

VSS200

AL21

VSS201

AB21

VSS202

Y21

VSS203

P21

VSS204

K21

VSS205

J21

VSS206

H21

VSS207

C21

VSS208

AW20

VSS209

AR20

VSS210

AM20

VSS211

AA20

VSS212

K20

VSS213

B20

VSS214

A20

VSS215

AN19

VSS216

AC19

VSS217

W19

VSS218

K19

VSS219

G19

VSS220

C19

VSS221

AH18

VSS222

P18

VSS223

H18

VSS224

D18

VSS225

A18

VSS226

AY17

VSS227

AR17

VSS228

AP17

VSS229

AM17

VSS230

AK17

VSS231

AV16

VSS232

AN16

VSS233

AL16

VSS234

J16

VSS235

F16

VSS236

C16

VSS237

AN15

VSS238

AM15

VSS239

AK15

VSS240

N15

VSS241

M15

VSS242

L15

VSS243

B15

VSS244

A15

VSS245

BA14

VSS246

AT14

VSS247

AK14

VSS248

AD14

VSS249

AA14

VSS250

U14

VSS251

K14

VSS252

H14

VSS253

E14

VSS254

AV13

VSS255

AR13

VSS256

AN13

VSS257

AM13

VSS258

AL13

VSS259

AG13

VSS260

P13

VSS261

F13

VSS262

D13

VSS265

B13

VSS264

AY12

VSS263

AC12

VSS266

K12

VSS267

H12

VSS268

E12

VSS269

AD11

VSS270

AA11

VSS271

Y11

VSS272

J11

VSS273

D11

VSS274

B11

VSS275

AV10

VSS276

AP10

VSS277

AL10

VSS278

AJ10

VSS279

CALISTOGA_FCBGA1466~D

P O W E R

VSS280
VSS281
VSS282
VSS283
VSS284
VSS285
VSS286
VSS287
VSS288
VSS289
VSS290
VSS292
VSS291
VSS293
VSS294
VSS295
VSS296
VSS297
VSS298
VSS299
VSS300
VSS301
VSS302
VSS303
VSS304
VSS305
VSS306
VSS307
VSS308
VSS309
VSS310
VSS311
VSS312
VSS313
VSS314
VSS315
VSS316
VSS317
VSS318
VSS319
VSS320
VSS321
VSS322
VSS323
VSS324
VSS325
VSS326
VSS327
VSS328
VSS329
VSS330
VSS331
VSS332
VSS333
VSS334
VSS335
VSS336
VSS337
VSS338
VSS339
VSS340
VSS341
VSS342
VSS343
VSS344
VSS345
VSS346
VSS347
VSS348
VSS349
VSS350
VSS351
VSS352
VSS353
VSS354
VSS355
VSS356
VSS357
VSS358
VSS359
VSS360

AG10
AC10
W10
U10
BA9
AW9
AR9
AH9
AB9
Y9
R9
G9
E9
A9
AG8
AD8
AA8
U8
K8
C8
BA7
AV7
AP7
AL7
AJ7
AH7
AF7
AC7
R7
G7
D7
AG6
AD6
AB6
Y6
U6
N6
K6
H6
B6
AV5
AF5
AD5
AY4
AR4
AP4
AL4
AJ4
Y4
U4
R4
J4
F4
C4
AY3
AW3
AV3
AL3
AH3
AG3
AF3
AD3
AC3
AA3
G3
AT2
AR2
AP2
AK2
AJ2
AD2
AB2
Y2
U2
T2
N2
J2
H2
F2
C2
AL1

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/03/10 2006/03/10

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

Compal Electronics, Inc.

Calistoga (6/6)

LA-2841

1

1.0

of

12 60F r ida y, D ec em be r 1 6, 2005

5

DDR_A_DQS#[0..7]<8>

DDR_A_D[0..63]<8>

DDR_A_DM[0..7]<8>
DDR_A_DQS[0..7]<8>
DDR_A_MA[0..13]<8>

D D

Layout Note:
Place near JP41

+1.8V

0.1U_0402_16V4Z

2.2U_0805_16V4Z

1

2

C642

5

C129

1

2

0.1U_0402_16V4Z

1

2

RP25

1 4
2 3

RP24

56_0404_4P2R_5%

1 4
2 3

RP6

56_0404_4P2R_5%

1 4
2 3

RP23

56_0404_4P2R_5%

1 4
2 3

RP22

56_0404_4P2R_5%

1 4
2 3

RP21

56_0404_4P2R_5%

2 3
1 4

56_0404_4P2R_5%

2.2U_0805_16V4Z

C640

C131

1

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

2

C639

+0.9VS

C206

C204

1

1

2

2

0.1U_0402_16V4Z

1

1

2

2

C175

C192

RP27 56_0404_4P2R_5%

14
23

RP15 56_0404_4P2R_5%

14
23

RP26 56_0404_4P2R_5%

14
23

RP12 56_0404_4P2R_5%

14
23

RP9 56_0404_4P2R_5%

14
23

RP3 56_0404_4P2R_5%

14
23

RP18 56_0404_4P2R_5%

14
23

2.2U_0805_16V4Z

2.2U_0805_16V4Z

2.2U_0805_16V4Z
C130

1

2

C C

B B

A A

Layout Note:
Place one cap close to every 2 pullup
resistors terminated to +0.9VS

+0.9VS

0.1U_0402_16V4Z

1

2

C643

DDR_A_MA5
DDR_A_MA8

DDR_A_MA1
DDR_A_MA3

DDR_A_RAS#
DDR_CS0_DIMMA#

DDR_A_BS#0
DDR_A_MA10

DDR_A_CAS#
DDR_A_WE#

DDR_CS1_DIMMA#
M_ODT1

0.1U_0402_16V4Z

0.1U_0402_16V4Z
C180

1

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

2

2

C166

C630

DDR_A_BS#2
DDR_CKE0_DIMMA

DDR_A_MA7
DDR_A_MA6

DDR_A_MA9
DDR_A_MA12

DDR_A_MA4
DDR_A_MA2

DDR_A_MA0
DDR_A_BS#1

M_ODT0
DDR_A_MA13

DDR_CKE1_DIMMA
DDR_A_MA11

1

2

0.1U_0402_16V4Z

C143

1

2

0.1U_0402_16V4Z

1

2

0.1U_0402_16V4Z

C629

4

0.1U_0402_16V4Z
C187

C193

1

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

2

2

C145

C158

Layout Note:
Place these resistor
closely JP41,all
trace length Max=1.5"

4

1

2

C136

3

+1.8V

JP21

1

VREF

3

DDR_A_D4
DDR_A_D1

DDR_A_DQS#0
DDR_A_DQS0

DDR_A_D2
DDR_A_D3

DDR_A_D8
DDR_A_D14

DDR_A_DQS#1
DDR_A_DQS1

DDR_A_D9 DDR_A_D11
DDR_A_D15 DDR_A_D10

DDR_A_D16
DDR_A_D17

DDR_A_DQS#2
DDR_A_DQS2

DDR_A_D18
DDR_A_D19

DDR_A_DM3

DDR_A_D26
DDR_A_D27

DDR_CKE0_DIMMA<7>

DDR_A_BS#2<8>

DDR_A_BS#0<8>

DDR_A_WE#<8>

DDR_A_CAS#<8>

0.1U_0402_16V4Z

1

2

C628

DDR_CS1_DIMMA#<7>

M_ODT1<7>

CLK_SMBDATA<14,15>

CLK_SMBCLK<14,15>

DDR_CKE0_DIMMA

DDR_A_BS#2
DDR_A_MA12

DDR_A_MA9 DDR_A_MA7
DDR_A_MA8

DDR_A_MA5
DDR_A_MA3
DDR_A_MA1

DDR_A_MA10
DDR_A_BS#0
DDR_A_WE#

DDR_A_CAS#
DDR_CS1_DIMMA#

M_ODT1
DDR_A_D37

DDR_A_D36
DDR_A_DQS#4

DDR_A_DQS4
DDR_A_D35

DDR_A_D32
DDR_A_D40

DDR_A_D44
DDR_A_DM5
DDR_A_D41

DDR_A_D46
DDR_A_D49

DDR_A_D48

DDR_A_DQS#6
DDR_A_DQS6

DDR_A_D50
DDR_A_D61 DDR_A_D57

DDR_A_D60
DDR_A_DM7
DDR_A_D59

DDR_A_D58
CLK_SMBDATA

CLK_SMBCLK

+3VS

1

C80

0.1U_0402_16V4Z

2

VSS

5

DQ0

7

DQ1

9

VSS

11

DQS0#

13

DQS0

15

VSS

17

DQ2

19

DQ3

21

VSS

23

DQ8

25

DQ9

27

VSS

29

DQS1#

31

DQS1

33

VSS

35

DQ10

37

DQ11

39

VSS

41

VSS

43

DQ16

45

DQ17

47

VSS

49

DQS2#

51

DQS2

53

VSS

55

DQ18

57

DQ19

59

VSS

61

DQ24

63

DQ25

65

VSS

67

DM3

69

NC

71

VSS

73

DQ26

75

DQ27

77

VSS

79

CKE0

81

VDD

83

NC

85

BA2

87

VDD

89

A12

91

A9

93

A8

95

VDD

97

A5

99

A3

101

A1

103

VDD

105

A10/AP

107

BA0

109

WE#

111

VDD

113

CAS#

115

NC/S1#

117

VDD

119

NC/ODT1

121

VSS

123

DQ32

125

DQ33

127

VSS

129

DQS4#

131

DQS4

133

VSS

135

DQ34

137

DQ35

139

VSS

141

DQ40

143

DQ41

145

VSS

147

DM5

149

VSS

151

DQ42

153

DQ43

155

VSS

157

DQ48

159

DQ49

161

VSS

163

NC,TEST

165

VSS

167

DQS6#

169

DQS6

171

VSS

173

DQ50

175

DQ51

177

VSS

179

DQ56

181

DQ57

183

VSS

185

DM7

187

VSS

189

DQ58

191

DQ59

193

VSS

195

SDA

197

SCL

199

VDDSPD

FOX_ASOA426-M4R-TR

CONN@

SO-DIMM A

REVERSE

DQ4
DQ5

DM0
DQ6

DQ7

DQ12
DQ13

DM1

CK0#

DQ14
DQ15

DQ20
DQ21

DM2

DQ22
DQ23

DQ28
DQ29

DQS3#

DQS3
DQ30

DQ31

NC/CKE1

VDD
NC/A15
NC/A14

VDD

VDD

VDD

RAS#

VDD

ODT0

NC/A13

VDD

DQ36
DQ37

DM4

DQ38
DQ39

DQ44
DQ45

DQS5#

DQS5
DQ46

DQ47
DQ52

DQ53

CK1#

DM6

DQ54
DQ55

DQ60
DQ61

DQS7#

DQS7
DQ62

DQ63

SAO

VSS

VSS
VSS

VSS

VSS
VSS

CK0
VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

A11

BA1
S0#

VSS

VSS
VSS

VSS

VSS

VSS

VSS

VSS
CK1

VSS
VSS

VSS

VSS

VSS

VSS
SA1

2

+1.8V

V_DDR_MCH_REF

2

DDR_A_D6

4

DDR_A_D0

6
8

DDR_A_DM0

10
12

DDR_A_D5

14

DDR_A_D7

16
18

DDR_A_D13

20

DDR_A_D12

22
24

DDR_A_DM1

26
28

M_CLK_DDR0

30

M_CLK_DDR#0

32
34
36
38
40

42

DDR_A_D20

44

DDR_A_D21

46
48
50

NC

A7
A6

A4
A2
A0

NC

52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200

DDR_A_DM2
DDR_A_D23

DDR_A_D22
DDR_A_D28DDR_A_D29

DDR_A_D25DDR_A_D24
DDR_A_DQS#3

DDR_A_DQS3
DDR_A_D31

DDR_A_D30
DDR_CKE1_DIMMA

DDR_A_MA11
DDR_A_MA6
DDR_A_MA4

DDR_A_MA2
DDR_A_MA0

DDR_A_BS#1
DDR_A_RAS#
DDR_CS0_DIMMA#

M_ODT0
DDR_A_MA13

DDR_A_D39
DDR_A_D38

DDR_A_DM4
DDR_A_D34

DDR_A_D33
DDR_A_D45

DDR_A_D43
DDR_A_DQS#5

DDR_A_DQS5
DDR_A_D47

DDR_A_D42
DDR_A_D52

DDR_A_D53
M_CLK_DDR1

M_CLK_DDR#1
DDR_A_DM6
DDR_A_D51DDR_A_D54

DDR_A_D55

DDR_A_D56
DDR_A_DQS#7

DDR_A_DQS7
DDR_A_D62

DDR_A_D63

12

R35

R33

10K_0402_5%

10K_0402_5%

12

2.2U_0805_16V4Z
C368

1

2

M_CLK_DDR0 <7>
M_CLK_DDR#0 <7>

PM_EXTTS#0 <7,14>

DDR_CKE1_DIMMA <7>

DDR_A_BS#1 <8>
DDR_A_RAS# <8>
DDR_CS0_DIMMA# <7>

M_ODT0 <7>

M_CLK_DDR1 <7>
M_CLK_DDR#1 <7>

1

0.1U_0402_16V4Z

1

2

V_DDR_MCH_REF <7,14>

C369

Top side

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/03/10 2006/03/10

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

Compal Electronics, Inc.

DDRII-SODIMM SLOT1

LA-2841

1

1.0

of

13 60Thursday, December 15, 2005

5

DDR_B_DQS#[0..7]<8>

DDR_B_D[0..63]<8>

DDR_B_DM[0..7]<8>
DDR_B_DQS[0..7]<8>
DDR_B_MA[0..13]<8>

D D

C C

B B

A A

Layout Note:
Place near JP42

+1.8V

1

2

C202

2.2U_0805_16V4Z

1

2

0.1U_0402_16V4Z

1

2

+0.9VS

2.2U_0805_16V4Z

C159

0.1U_0402_16V4Z

C179

RP16 56_0404_4P2R_5%

RP17 56_0404_4P2R_5%

RP13 56_0404_4P2R_5%

RP14 56_0404_4P2R_5%

RP11 56_0404_4P2R_5%

RP2 56_0404_4P2R_5%

RP19

56_0404_4P2R_5%

2.2U_0805_16V4Z
C132

1

2

Layout Note:
Place one cap close to every 2 pullup
resistors terminated to +0.9VS

+0.9VS

0.1U_0402_16V4Z

1

2

C156

DDR_B_MA1
DDR_B_MA3

DDR_B_BS#0
DDR_B_MA10

DDR_B_BS#1
DDR_B_MA0

DDR_CS2_DIMMB#
DDR_B_RAS#

DDR_B_CAS#
DDR_B_WE#

DDR_CS3_DIMMB#
M_ODT3

0.1U_0402_16V4Z

2.2U_0805_16V4Z

1

2

1

2

C146

RP10

RP7

RP8

RP5

RP4

RP1

C214

0.1U_0402_16V4Z

1 4
2 3

1 4
2 3

1 4
2 3

1 4
2 3

1 4
2 3

2 3
1 4

5

2.2U_0805_16V4Z
C205

1

2

0.1U_0402_16V4Z

1

2

C137

56_0404_4P2R_5%

56_0404_4P2R_5%

56_0404_4P2R_5%

56_0404_4P2R_5%

56_0404_4P2R_5%

56_0404_4P2R_5%

C157

1

2

1

2

C170

14
23

14
23

14
23

14
23

14
23

14
23

14
23

0.1U_0402_16V4Z
C169

1

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

2

2

C165

DDR_B_MA9
DDR_B_MA12

DDR_B_MA11
DDR_CKE3_DIMMB

DDR_B_MA5
DDR_B_MA8

DDR_B_MA6
DDR_B_MA7

DDR_B_MA2
DDR_B_MA4

DDR_B_MA13
M_ODT2

DDR_B_BS#2
DDR_CKE2_DIMMB

0.1U_0402_16V4Z

0.1U_0402_16V4Z

C142

1

2

0.1U_0402_16V4Z

1

2

C144

C147

0.1U_0402_16V4Z

C141

1

1

2

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

2

2

C191

C133

Layout Note:
Place these resistor
closely JP42,all
trace length Max=1.5"

4

C140

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

2

2

C168

C176

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

4

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

+1.8V

JP24

1

VREF

3

DDR_B_D0
DDR_B_D1

DDR_B_DQS#0
DDR_B_DQS0

DDR_B_D2
DDR_B_D3

DDR_B_D8
DDR_B_D9

DDR_B_DQS#1
DDR_B_DQS1

DDR_B_D10
DDR_B_D11

DDR_B_D20
DDR_B_DQS#2

DDR_B_DQS2
DDR_B_D18

DDR_B_D19
DDR_B_D28

DDR_B_DM3

DDR_B_D30
DDR_B_D31

DDR_CKE2_DIMMB<7>

DDR_B_BS#2<8>

DDR_B_BS#0<8>
DDR_B_WE#<8>

DDR_B_CAS#<8>

DDR_CS3_DIMMB#<7>

M_ODT3<7>

CLK_SMBDATA<13,15>

CLK_SMBCLK<13,15>

3

DDR_CKE2_DIMMB

DDR_B_BS#2
DDR_B_MA12

DDR_B_MA9
DDR_B_MA8

DDR_B_MA5
DDR_B_MA3
DDR_B_MA1

DDR_B_MA10
DDR_B_BS#0
DDR_B_WE#

DDR_B_CAS#
DDR_CS3_DIMMB#

M_ODT3
DDR_B_D32

DDR_B_D33
DDR_B_DQS#4

DDR_B_DQS4
DDR_B_D34

DDR_B_D35
DDR_B_D40

DDR_B_D41
DDR_B_DM5
DDR_B_D42

DDR_B_D43
DDR_B_D48

DDR_B_D49

DDR_B_DQS#6
DDR_B_DQS6

DDR_B_D51
DDR_B_D50

DDR_B_D56
DDR_B_D61 DDR_B_D57

DDR_B_DM7
DDR_B_D59

DDR_B_D58
CLK_SMBDATA

CLK_SMBCLK

+3VS

1

C79

0.1U_0402_16V4Z

2005/03/10 2006/03/10

2

Compal Secret Data

VSS

5

DQ0

7

DQ1

9

VSS

11

DQS0#

13

DQS0

15

VSS

17

DQ2

19

DQ3

21

VSS

23

DQ8

25

DQ9

27

VSS

29

DQS1#

31

DQS1

33

VSS

35

DQ10

37

DQ11

39

VSS

41

VSS

43

DQ16

45

DQ17

47

VSS

49

DQS2#

51

DQS2

53

VSS

55

DQ18

57

DQ19

59

VSS

61

DQ24

63

DQ25

65

VSS

67

DM3

69

NC

71

VSS

73

DQ26

75

DQ27

77

VSS

79

CKE0

81

VDD

83

NC

85

BA2

87

VDD

89

A12

91

A9

93

A8

95

VDD

97

A5

99

A3

101

A1

103

VDD

105

A10/AP

107

BA0

109

WE#

111

VDD

113

CAS#

115

NC/S1#

117

VDD

119

NC/ODT1

121

VSS

123

DQ32

125

DQ33

127

VSS

129

DQS4#

131

DQS4

133

VSS

135

DQ34

137

DQ35

139

VSS

141

DQ40

143

DQ41

145

VSS

147

DM5

149

VSS

151

DQ42

153

DQ43

155

VSS

157

DQ48

159

DQ49

161

VSS

163

NC,TEST

165

VSS

167

DQS6#

169

DQS6

171

VSS

173

DQ50

175

DQ51

177

VSS

179

DQ56

181

DQ57

183

VSS

185

DM7

187

VSS

189

DQ58

191

DQ59

193

VSS

195

SDA

197

SCL

199

VDDSPD

FOX_ASOA426-M4R-TR

CONN@

SO-DIMM B
STANDARD

Bottom side

Deciphered Date

DQ4
DQ5

DM0
DQ6

DQ7

DQ12
DQ13

DM1

CK0#

DQ14
DQ15

DQ20
DQ21

DM2

DQ22
DQ23

DQ28
DQ29

DQS3#

DQS3
DQ30

DQ31

NC/CKE1

VDD
NC/A15
NC/A14

VDD

VDD

VDD

RAS#

VDD

ODT0

NC/A13

VDD

DQ36
DQ37

DM4

DQ38
DQ39

DQ44
DQ45

DQS5#

DQS5
DQ46

DQ47
DQ52

DQ53

CK1#

DM6

DQ54
DQ55

DQ60
DQ61

DQS7#

DQS7
DQ62

DQ63

SAO

VSS

VSS
VSS

VSS

VSS
VSS

CK0
VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

A11

BA1
S0#

VSS

VSS
VSS

VSS

VSS

VSS

VSS

VSS
CK1

VSS
VSS

VSS

VSS

VSS

VSS
SA1

2

+1.8V

V_DDR_MCH_REF

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

42
44
46
48
50

NC

52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92

A7

94

A6

96
98

A4

100

A2

102

A0

104
106
108
110
112
114
116
118
120

NC

122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200

2

DDR_B_D5
DDR_B_D4

DDR_B_DM0
DDR_B_D6

DDR_B_D7
DDR_B_D12

DDR_B_D13
DDR_B_DM1
M_CLK_DDR3

M_CLK_DDR#3
DDR_B_D14

DDR_B_D15

DDR_B_D21DDR_B_D17
DDR_B_D16

DDR_B_DM2
DDR_B_D22

DDR_B_D23
DDR_B_D26

DDR_B_D24DDR_B_D25
DDR_B_DQS#3

DDR_B_DQS3
DDR_B_D29

DDR_B_D27
DDR_CKE3_DIMMB

DDR_B_MA11
DDR_B_MA7
DDR_B_MA6

DDR_B_MA4
DDR_B_MA2
DDR_B_MA0

DDR_B_BS#1
DDR_B_RAS#
DDR_CS2_DIMMB#

M_ODT2
DDR_B_MA13

DDR_B_D36
DDR_B_D37

DDR_B_DM4
DDR_B_D39

DDR_B_D38
DDR_B_D44

DDR_B_D45
DDR_B_DQS#5

DDR_B_DQS5
DDR_B_D46

DDR_B_D47
DDR_B_D52

DDR_B_D53
M_CLK_DDR2

M_CLK_DDR#2
DDR_B_DM6
DDR_B_D54

DDR_B_D55
DDR_B_D60

DDR_B_DQS#7
DDR_B_DQS7

DDR_B_D62
DDR_B_D63

10K_0402_5%

12

R34

2.2U_0805_16V4Z

0.1U_0402_16V4Z

1

1

C366

2

2

M_CLK_DDR3 <7>
M_CLK_DDR#3 <7>

PM_EXTTS#0 <7,13>

DDR_CKE3_DIMMB <7>

DDR_B_BS#1 <8>
DDR_B_RAS# <8>
DDR_CS2_DIMMB# <7>

M_ODT2 <7>

M_CLK_DDR2 <7>
M_CLK_DDR#2 <7>

R32

1 2

10K_0402_5%

Title

Size Document Number Rev

Date: Sheet

+3VS

Compal Electronics, Inc.

DDRII-SODIMM SLOT2

LA-2841

1

V_DDR_MCH_REF <7,13>

C367

1

1.0

of

14 60Thursday, December 15, 2005

5

PCI

SRC

CPU

CLKSEL1

0

1

FSLA

CLKSEL0

Stuff

No Stuff

Stuff

No Stuff

Stuff

No Stuff

MHz

133

166

CLK_Ra

CLK_Rd

CLK_Rd

CLK_Ra

CLK_Rd

CLK_Ra

MHz

1000

100

CLK_Rb

CLK_Re

CLK_Re

CLK_Rb

CLK_Rf

CLK_Rb

MHz

33.31

33.3

CLK_Rc

CLK_Rf

CLK_Rf

CLK_Rc

CLK_Rc

ICH_SMBDATA<29,34,37>

ICH_SMBCLK<29,34,37>

FSLC1FSLB

CLKSEL2

0

Table : ICS954306

D D

FSB Frequency Selet:

CPU Driven

(Default)

*

533MHz

667MHz

CLK_Re

+VCCP

R232

@

R237

8.2K_0402_5%

C C

B B

A A

FSA

CLKREF1

1 2

R231

0_0402_5%

CLK_Ra

FSB

1 2

R191

0_0402_5%

CLK_Rb

R205

8.2K_0402_5%

1 2

R177

0_0402_5%

CLK_Rc

10K_0402_5%

CLK_ENABLE#

CPU_BSEL0<5>

CPU_BSEL1<5>

CPU_BSEL2<5>

56_0402_5%

CLK_Rd

1 2

12

1 2

R227

1K_0402_5%

12

R228
1K_0402_5%@

+VCCP

R201
1K_0402_5%@

1 2

1 2

R200

1K_0402_5%

12

R199

@

0_0402_5%

CLK_Re

+VCCP

R202
1K_0402_5%@

1 2

12

1 2

R184

R235

1K_0402_5%

12

R183

@

0_0402_5%

CLK_Rf

+3VS

12

5

MCH_CLKSEL0 <7> CLK_48M_CB<32>

MCH_CLKSEL1 <7>

+3VS

12

R589
100K_0402_5%

PCI_PCM

CLK_MCH_DREFCLK<7>

CLK_MCH_DREFCLK#<7>

MCH_CLKSEL2 <7>

LCD clock select

+3VS +3VS

12

R233

10K_0402_5%@

PCI_ICH PCI_MINI

12

R238
10K_0402_5%

High:Pin18/19 = 100MHz
Low:Pin18/19 = 96MHz Low:Pin44/45 = CPUCLK2_ITP

4

2.2K_0402_5%
Q12
2N7002_SOT23

D

1 3

+3VS

CLK_48M_ICH<29>

CLK_14M_ICH<29>

H_STP_CPU#<29>

H_STP_PCI#<29>

CLK_ENABLE#<53>

CLK_PCI_ICH<27>

CLK_PCI_MINI<36>

CLK_PCI_EC<44>

CLK_PCI_SIO<42>

CLK_PCI_PCM<32>

CLK_SMBDATA<13,14>

CLK_SMBCLK<13,14>

2

2

1 3

D

2N7002_SOT23

Q15

CLK_MCH_DREFCLK
CLK_MCH_DREFCLK#

Pin44/45 function select

High:Pin44/45 = CLKREQ

**

4

+3VS

R299

S

G

G

S

0.1U_0402_16V4Z

0.1U_0402_16V4Z

CLK_48M_ICH
CLK_48M_CB

CLK_14M_ICH

H_STP_CPU#
H_STP_PCI#
CLK_ENABLE#

CLK_PCI_ICH PCI_ICH

CLK_SMBDATA
CLK_SMBCLK

1 2

R246 10_0402_5%UMA@

1 2

R253 10_0402_5%UMA@

C424

C425

R236 12_0402_5%

R243 12_0402_5%

R230 33_0402_5%

1 2

12

R312
10K_0402_5%

12

R308

10K_0402_5%@

R323

2.2K_0402_5%

CLK_SMBDATA

CLK_SMBCLK

+CK_VDD_48

1

2

1

2

+CK_VDD_REF

R2662.4K_0402_1%

R229

33_0402_5%

R20633_0402_5%

12

R21610K_0402_5%

12

R21533_0402_5%

12

R22533_0402_5%@

12

R22433_0402_5%

12

MCH_DREFCLK
MCH_DREFCLK#

+CK_VDD_MAIN1

12
12

12

12

3

+CK_VDD_MAIN1

1 2

+3VS

FSA
FSB
CLKREF1

CLKIREF

PCI_MINI

PCI_EC
PCI_SIO
PCI_PCM

+3VS

16
10

24
33
41
50
55

11
15
59

46
61

60
62

54
53

13
14

12
17
58
47
25
40
32

R324 0_0805_5%

R174 0_0805_5%

5

8
9
7

1
2
3
6

4

1 2

U13

VDD
VDD48
VDDPCI
VDDSRC
VDDSATA
VDDSRC
VDDCPU
VDDREF

FSLA/USB_48MHz
FSLB/TEST_MODE
FSLC/TEST_SEL/REF1

IREF
CPU_STOP#
PCI/SRC_STOP#
Vtt_PwrGd#/PD
**SEL_LCDCLK#/PCICLK_F1

REF0/PCICLK1
*REQ_SEL/PCICLK2
*SEL_PCI1/PCICLK3
**SEL_SATA1/PCICLK4
**SEL_SATA2/PCICLK5
PCICLK6

SDATA
SCLK

DOTT_96MHz
DOTC_96MHz

GND
GND
GND
GND
GNDCPU
GNDSRC
GNDSRC
GNDSATA

ICS954306_TSSOP64

1

C456
10U_0805_10V4Z

2

+CK_VDD_MAIN2

1

C416
10U_0805_10V4Z

2

LCDCLK_SST/SRCCLKT0
LCDCLK_SSC/SRCCLKC0

*CPUCLKT2_ITP/CLKREQC#

*CPUCLKC2_ITP/CLKREQD#

* Internal Pull-Up Resistor
** Internal Pull-Down Resistor

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

1

C422

0.1U_0402_16V4Z

2

1

C418

0.1U_0402_16V4Z

2

X1
X2

SATACLKT

SATACLKC

CPUCLKT0

CPUCLKC0

CPUCLKT1

CPUCLKC1

*CLKREQA#

SRCCLKT2

SRCCLKC2

SATA1/SRCCLKT4
SATA1/SRCCLKC4

*CLKREQB#

SRCCLKT1

SRCCLKC1

SRCCLKT3

SRCCLKC3

SATA2/SRCCLKT5
SATA2/SRCCLKC5

SRCCLKT6

SRCCLKC6

SRCCLKT8

SRCCLKC8

SRCCLKT7

SRCCLKC7

2005/03/10 2006/03/10

1

C431

0.1U_0402_16V4Z

2

1

C417

0.1U_0402_16V4Z

2

C419 22P_0402_50V8J

12

Y2

CLK_XTAL_IN

57

CLK_XTAL_OUT

56

28

1 2

R305 0_0402_5%9LP@

29

1 2

R311 0_0402_5%9LP@

CPU_BCLK

52

CPU_BCLK#

51

MCH_BCLK

49

MCH_BCLK#

48

64

SSCDREFCLK

18

SSCDREFCLK#

19

PCIE_MCARD

22

PCIE_MCARD#

23

PCIE_SATA

30

PCIE_SATA#

31

63

PCIE_VGA CLK_PCIE_VGA

20
21

MCH_3GPLL

26

MCH_3GPLL#

27

35
34

CPU_XDP

45
37

PCIE_NC1#

36

43
42

CPU_XDP# CLK_CPU_XDP#

44
39
38

14.31818MHZ_20P_1BX14318BE1A

C421 22P_0402_50V8J

1 2

R239 10_0402_5%

1 2

R247 10_0402_5%

1 2

R254 10_0402_5%

1 2

R258 10_0402_5%

R218 10K_0402_5%@

1 2

R257 10_0402_5%UMA@

1 2

R270 10_0402_5%UMA@

1 2

R282 10_0402_5%

1 2

R284 10_0402_5%

1 2

R297 10_0402_5%

1 2

R304 10_0402_5%
R226 10K_0402_5%@

1 2

R268 10_0402_5%G71@

1 2

R276 10_0402_5%G71@

1 2

R288 10_0402_5%

1 2

R292 10_0402_5%

1 2

R294 10_0402_5%

1 2

R301 10_0402_5%

R273 10K_0402_5%

1 2

R278 10_0402_5%@

1 2

R285 10_0402_5%17@

1 2

R289 10_0402_5%17@

R277 10K_0402_5%

1 2

R271 10_0402_5%@

1 2

R309 10_0402_5%15.4@

1 2

R310 10_0402_5%15.4@

Compal Secret Data

Deciphered Date

2

1

C440

0.1U_0402_16V4Z

2

1 2

R188

1_0805_1%

1 2

R187

2.2_0805_1%

12

12

CLK_CPU_BCLK
CLK_CPU_BCLK#

CLK_MCH_BCLK
CLK_MCH_BCLK#

12

CLKREQA#
MCH_SSCDREFCLK
MCH_SSCDREFCLK#

CLK_PCIE_MCARD

CLK_PCIE_MCARD#

CLK_PCIE_SATA

CLK_PCIE_SATA#

12

CLKREQB#

CLK_PCIE_VGA#PCIE_VGA#

CLK_MCH_3GPLL

CLK_MCH_3GPLL#

CLK_PCIE_ICHPCIE_ICH

CLK_PCIE_ICH#PCIE_ICH#

CLKREQC#

12

CLK_CPU_XDP

CLK_PCIE_NC1PCIE_NC1

CLK_PCIE_NC1#

CLKREQD#

12

CLK_PCIE_NC2PCIE_NC2

CLK_PCIE_NC2#PCIE_NC2#

2

1

C450

0.1U_0402_16V4Z

2

+CK_VDD_REF

+CK_VDD_48

1

1

C441

0.1U_0402_16V4Z

2

Place crystal within
500 mils of CK410

1

C430

0.1U_0402_16V4Z

2

Place near U54

Place these components
near each pin within 40
mils.

CLK_CPU_BCLK <4>
CLK_CPU_BCLK# <4>

CLK_MCH_BCLK <7>
CLK_MCH_BCLK# <7>

+3VS

CLKREQA# <37>
MCH_SSCDREFCLK <7>
MCH_SSCDREFCLK# <7>

CLK_PCIE_MCARD <37>
CLK_PCIE_MCARD# <37>

CLK_PCIE_SATA <28>
CLK_PCIE_SATA# <28>

+3VS

CLKREQB# <7>
CLK_PCIE_VGA <18>
CLK_PCIE_VGA# <18>

CLK_MCH_3GPLL <7>
CLK_MCH_3GPLL# <7>

CLK_PCIE_ICH <29>
CLK_PCIE_ICH# <29>

CLKREQC# <34>

CLK_PCIE_NC1 <34>
CLK_PCIE_NC1# <34>

CLKREQD# <34>

CLK_PCIE_NC2 <34>
CLK_PCIE_NC2# <34>

Title

Size Document Number Rev

Date: Sheet

CLK_CPU_BCLK
CLK_CPU_BCLK#

CLK_MCH_BCLK
CLK_MCH_BCLK#

MCH_SSCDREFCLK
MCH_SSCDREFCLK#

CLK_PCIE_MCARD

CLK_PCIE_MCARD#
CLK_MCH_3GPLL
CLK_MCH_3GPLL#
CLK_PCIE_VGA
CLK_PCIE_VGA#

CLK_PCIE_ICH

CLK_PCIE_ICH#
CLK_MCH_DREFCLK
CLK_MCH_DREFCLK#

CLK_PCIE_SATA

CLK_PCIE_SATA#

CLK_CPU_XDP

CLK_CPU_XDP#

CLK_PCIE_NC1

CLK_PCIE_NC1#

CLK_PCIE_NC2

CLK_PCIE_NC2#

CLKREQA#
CLKREQB#
CLKREQC#
CLKREQD#

R240 49.9_0402_1%@
R248 49.9_0402_1%@

R255 49.9_0402_1%@
R259 49.9_0402_1%@

R256 49.9_0402_1%@
R269 49.9_0402_1%@

R281 49.9_0402_1%@
R283 49.9_0402_1%@
R287 49.9_0402_1%@

R291 49.9_0402_1%@
R267 49.9_0402_1%@
R275 49.9_0402_1%@

R295 49.9_0402_1%@

R302 49.9_0402_1%@
R245 49.9_0402_1%@
R252 49.9_0402_1%@

R296 49.9_0402_1%@

R303 49.9_0402_1%@

R279 49.9_0402_1% @

R272 49.9_0402_1%@
R286 49.9_0402_1%@
R290 49.9_0402_1%@

R318 49.9_0402_1%@

R319 49.9_0402_1%@

C802 1000P_0402_50V7K

1 2

C803 1000P_0402_50V7K

1 2

C804 1000P_0402_50V7K

1 2

C805 1000P_0402_50V7K

1 2

1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2

1 2
1 2

Compal Electronics, Inc.

Clock generator

LA-2841

1

12
12

12
12

12
12
12
12

1.0

of

15 60Thursday, December 15, 2005

A

B

C

D

E

F

G

H

LCD Panel & inverter Connector

1 1

2 2

+3VS

R434

1 2

10K_0402_5%

R435

1 2

10K_0402_5%

EDID_CLK_LCD

EDID_DAT_LCD

WL_LED#<37,42>

INVT_PWM<44>
DAC_BRIG<44>

EDID_CLK_LCD<9>
EDID_DAT_LCD<9>

LCD_I2C_CLK_C< 18>
LCD_I2C_DAT_C<18>

+LCDVDD

+5VS
+3VS

+LCDVDD

+5VS
+3VS

WL_LED#

EDID_CLK_LCD
EDID_DAT_LCD

INVPWR_B+

WL_LED#
DISPOFF#
INVT_PWM
DAC_BRIG

LCD_I2C_CLK_C
LCD_I2C_DAT_C

INVPWR_B+

DISPOFF#
INVT_PWM
DAC_BRIG

JP2

UMA

39

40

37

38

35

36

33

34

31

32

29

30

27

28

25

26

23

24

21

22

19

20

17

18

15

16

13

14

11

12

9

10

7

8

5

6

3

4

1

2

ACES_88107-4000G

JP1

Discrete

39

40

37

38

35

36

33

34

31

32

29

30

27

28

25

26

23

24

21

22

19

20

17

18

15

16

13

14

11

12

9

10

7

8

5

6

3

4

1

2

ACES_88107-4000G

LVDSAC+
LVDSAC-

LVDSA1­LVDSA1+

LVDSBC+
LVDSBC-

LVDSB1­LVDSB1+
LVDSB0+
LVDSB0­LVDSB2+
LVDSB2-

LVDSA0­LVDSA0+
LVDSA2­LVDSA2+

LVDS_AC­LVDS_AC+

LVDS_A2+
LVDS_A2­LVDS_A1+
LVDS_A1­LVDS_A0+
LVDS_A0-

LVDS_B1­LVDS_B1+
LVDS_B2+
LVDS_B2­LVDS_B0+
LVDS_B0-

LVDS_BC+
LVDS_BC-

LVDSAC+ <9>

LVDSAC- <9>

LVDSA1- <9>

LVDSA1+ <9>

LVDSBC+ <9>

LVDSBC- <9>

LVDSB1- <9>
LVDSB1+ <9>
LVDSB0+ <9>

LVDSB0- <9>
LVDSB2+ <9>

LVDSB2- <9>

LVDSA0- <9>
LVDSA0+ <9>
LVDSA2- <9>

LVDSA2+ <9>

LVDS_AC- <18>

LVDS_AC+ <18>
LVDS_A2+ <18>

LVDS_A2- <18>
LVDS_A1+ <18>

LVDS_A1- <18>
LVDS_A0+ <18>

LVDS_A0- <18>

LVDS_B1- <18>
LVDS_B1+ <18>

LVDS_B2+ <18>

LVDS_B2- <18>
LVDS_B0+ <18>

LVDS_B0- <18>
LVDS_BC+ <18>

LVDS_BC- <18>

+3VS

R430

D17

BKOFF#<44>

GMCH_ENBKL<9>

CH751H-40_SC76

D16
CH751H-40_SC76UMA@

R431

100K_0402_5%UMA@

1 2

L25 FBMA-L10-201209-301LMT

1 2

L24 FBMA-L10-201209-301LMT@

1 2

0.1U_0402_16V4Z

4.7K_0402_5%

1 2

21

21

DISPOFF#

INVPWR_B+B+

1

1

C806

C807

2

2

68P_0402_50V8K

3 3

+LCDVDD +5VALW

12

R429

100_0402_1%

2N7002_SOT23

ENVDD

R433

0_0402_5%UMA@

GMCH_LVDDEN<9>

ENVDD<18>

4 4

13

D

Q32

S

12

R428
100K_0402_5%

1 2

2

G

13

2

0.047U_0402_16V4Z

Q31
DTC124EK_SC59

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

C

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

D

1

C572

2

0.1U_0402_16V4Z

+LCDVDD

1

2

C574

Q33
SI2301BDS_SOT23

1 3

D

1

C575

4.7U_0805_10V4Z

2

2005/03/10 2006/03/10

E

+3VS

S

G

2

1

C573

4.7U_0805_10V4Z

2

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

F

Date: Sheet

Compal Electronics, Inc.

LVDS Connector

LA-2841

G

1.0

of

16 60Thursday, December 15, 2005

H

A

R15

M_RED<18>

M_GRN<18>

1 1

R449

CRT_HSYNC<9>

M_HSYNC<18>

2 2

CRT_VSYNC<9>

M_VSYNC<18>

1 2

R450

1 2

R447

1 2

R448

1 2

C580

1 2

0.1U_0402_16V4Z

CRTHSYNC

0_0402_5%UMA@

0_0402_5%G71@

CRTVSYNC

0_0402_5%UMA@

0_0402_5%G71@

M_BLU<18>

CRT_R<9>

CRT_G<9>

CRT_B<9>

+5VS

5

A2Y

3

5

A2Y

3

1 2

0_0402_5%G71@

R11

1 2

0_0402_5%G71@

R8

1 2

0_0402_5%G71@

R13

1 2

0_0402_5%UMA@

R12

1 2

0_0402_5%UMA@

R9

1 2

0_0402_5%UMA@

EMI

1

U29

P

4

OE#

G

1

U28

P

4

OE#

G

74AHCT1G125GW_SOT353-5

74AHCT1G125GW_SOT353-5

R14

1 2

75_0402_5%

B

1

2

C29

10P_0402_50V8K

@

CRT_HSYNC_R

CRT_VSYNC_R

R10

1 2

75_0402_5%

C

RB411D_SOT23

CRT CONNECTOR

EMI

L3

CRTR CRTL_R

CRTG

CRTB

1

R7

2

75_0402_5%

C20

10P_0402_50V8K

@

MBK2012800YZF

1 2

L2
MBK2012800YZF

1 2

L1
MBK2012800YZF

1 2

1

2

C9

1 2

10P_0402_50V8K

@

EMI

1

1

2

2

C25

C17

33P_0402_25V8K

33P_0402_25V8K

1 2

L27
FBM-L11-160808-800LMT_0603

1 2

L26
FBM-L11-160808-800LMT_0603

+R_CRT_VCC , +CRTVDD (40mils)

1

2

R16 4.7K_0402_5%

1

2

+CRTVDD

C579 10P_0402_50V8K

+CRTVDD

R443 4.7K_0402_5%

1

2

C46 220P_0402_25V8K

+5VS

+R_CRT_VCC

D1

2 1

1

2

C7

33P_0402_25V8K

CRT_HSYNCRFL

CRT_VSYNCRFL

F1

1.1A_6VDC_FUSE

0.1U_0402_16V4Z

M_SEN#

CRTL_G

CRTL_B

C581

21

C582

1

2

10P_0402_50V8K

D

JP3
ALLTO_C10510-115A5-L_15P-s

6

11

1
7

12

16

2

17

8

13

3
9

14

4
10
15

5

Q1
2N7002_SOT23

D

S

1 3

Q34

2N7002_SOT23

G

2

D

1

2

1 3

C577 220P_0402_25V8K

S

R19

G

2

2.2K_0402_5%

3V_DDCDA

3V_DDCCL

R444

2.2K_0402_5%

+3VS

R20

1 2

R446

1 2

R21

1 2

R445

1 2

E

NZQA5V6AXV5T1_SOT533-5

2

1 5

D46

CLOSE TO JP3

0_0402_5%G71@

0_0402_5%G71@

0_0402_5%UMA@

0_0402_5%UMA@

M_DDCDATA <18>

M_DDCCLK <18>

3VDDCDA <9>

3VDDCCL <9>

43

R25

M_LUMA<18>

M_CRMA<18>

M_COMP<18>

TV_LUMA<9>

3 3

4 4

A

TV_CRMA<9>

TV_COMPS<9>

1 2

R30

1 2

R27

1 2

R24

1 2

R31

1 2

R26

1 2

0_0402_5%G71@

0_0402_5%G71@

0_0402_5%G71@

0_0402_5%UMA@

0_0402_5%UMA@

0_0402_5%UMA@

TVCRMA

TVCOMPS

R28

TVLUMA

12

R29

75_0402_5%

B

TVLUMA
TVCRMA
TVCOMPS

12

R23

75_0402_5%

12

75_0402_5%

C75

270P_0402_50V7K

TVLUMA <46>
TVCRMA <46>
TVCOMPS <46>

1

C77

2

270P_0402_50V7K

TV-Out Connector
S-Video

EMI

L4
MBC1608121YZF_0603

1 2

L6
MBC1608121YZF_0603

1 2

L5
MBC1608121YZF_0603

1 2

1

1

C49

2

2

270P_0402_50V7K

R22

1 2

0_0805_5%

TVGND

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

LUMA_CL

CRMA_CL

COMPS_CL

1

C74

2

330P_0402_50V7K

2005/03/10 2006/03/10

1

1

2

C50

C76

2

330P_0402_50V7K

Compal Secret Data

Deciphered Date

330P_0402_50V7K

JP17

1

1

2

2

3

3

4

4

5

5

6

6

GND

7

7

GND

SUYIN_030107FR007G317ZR

D

8
9

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

CRT & TVout Connector

LA-2841

E

1.0

of

17 60Thursday, December 15, 2005

5

PEG_M_TXP0
PEG_M_TXN0
PEG_M_TXP1
PEG_M_TXN1
PEG_M_TXP2
PEG_M_TXN2
PEG_M_TXP3

PEG_M_TXN3
PEG_M_TXP4
PEG_M_TXN4
PEG_M_TXP5
PEG_M_TXN5

OUT

GND

PEG_M_TXP6
PEG_M_TXN6
PEG_M_TXP7
PEG_M_TXN7
PEG_M_TXP8
PEG_M_TXN8
PEG_M_TXP9
PEG_M_TXN9

PEG_M_TXP10

PEG_M_TXN10

PEG_M_TXP11

PEG_M_TXN11

PEG_M_TXP12

PEG_M_TXN12

PEG_M_TXP13

PEG_M_TXN13

PEG_M_TXP14

PEG_M_TXN14

PEG_M_TXP15

PEG_M_TXN15

1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2

CLK_PCIE_VGA<15>
CLK_PCIE_VGA#<15>

VGA_RST#<27>

R512 10K_0402_5%128@

1 2

R113 10K_0402_5%128@

1 2

R81 10K_0402_5%

1 2

R57 10K_0402_5%@

1 2

R56 10K_0402_5%@

1 2

R77 10K_0402_5%

1 2

C152

1 2

C161

1 2

3
2

1

C646

128@

22P_0402_50V8J

2

PEG_DTXP0

C1220.1U_0402_16V4Z128@

PEG_DTXN0

C1230.1U_0402_16V4Z128@

PEG_DTXP1

C6260.1U_0402_16V4Z128@

PEG_DTXN1

C6250.1U_0402_16V4Z128@

PEG_DTXP2

C880.1U_0402_16V4Z128@

PEG_DTXN2

C890.1U_0402_16V4Z128@

PEG_DTXP3

C900.1U_0402_16V4Z128@

PEG_DTXN3

C910.1U_0402_16V4Z128@

PEG_DTXP4

C920.1U_0402_16V4Z128@

PEG_DTXN4

C930.1U_0402_16V4Z128@

PEG_DTXP5

C6240.1U_0402_16V4Z128@

PEG_DTXN5

C6230.1U_0402_16V4Z128@

PEG_DTXP6

C940.1U_0402_16V4Z128@

PEG_DTXN6

C950.1U_0402_16V4Z128@

PEG_DTXP7

C960.1U_0402_16V4Z128@

PEG_DTXN7

C970.1U_0402_16V4Z128@

PEG_DTXP8

C6220.1U_0402_16V4Z128@

PEG_DTXN8

C6210.1U_0402_16V4Z128@

PEG_DTXP9

C980.1U_0402_16V4Z128@

PEG_DTXN9

C990.1U_0402_16V4Z128@

PEG_DTXP10

C1000.1U_0402_16V4Z128@

PEG_DTXN10

C1010.1U_0402_16V4Z128@

PEG_DTXP11

C6200.1U_0402_16V4Z128@

PEG_DTXN11

C6190.1U_0402_16V4Z128@

PEG_DTXP12

C1020.1U_0402_16V4Z128@

PEG_DTXN12

C1030.1U_0402_16V4Z128@

PEG_DTXP13

C1260.1U_0402_16V4Z128@

PEG_DTXN13

C1270.1U_0402_16V4Z128@

PEG_DTXP14

C6180.1U_0402_16V4Z128@

PEG_DTXN14

C6170.1U_0402_16V4Z128@

PEG_DTXP15

C1340.1U_0402_16V4Z128@

PEG_DTXN15

C1350.1U_0402_16V4Z128@

CLK_PCIE_VGA
CLK_PCIE_VGA#

VGA_RST#

0.1U_0402_16V4Z128@

0.1U_0402_16V4Z@

XTALIN

XTALOUT

1 2

R492
10K_0402_5%@

D D

PEG_RXP0
PEG_RXN0
PEG_RXP1
PEG_RXN1
PEG_RXP2
PEG_RXN2
PEG_RXP3
PEG_RXN3
PEG_RXP4
PEG_RXN4
PEG_RXP5
PEG_RXN5

C C

PEG_RXP6
PEG_RXN6
PEG_RXP7
PEG_RXN7
PEG_RXP8
PEG_RXN8
PEG_RXP9
PEG_RXN9
PEG_RXP10
PEG_RXN10
PEG_RXP11
PEG_RXN11
PEG_RXP12
PEG_RXN12
PEG_RXP13
PEG_RXN13
PEG_RXP14
PEG_RXN14
PEG_RXP15
PEG_RXN15

B B

1

2

A A

Y5

4

GND

1

IN

27MHz_16PF_6P27000126128@

C680

128@

22P_0402_50V8J

+3VS

AK13

AK14
AM14
AM15

AL15

AL16
AK16
AK17

AL17

AL18

AM18
AM19

AK19
AK20

AL20

AL21

AM21
AM22

AK22
AK23

AL23

AL24

AM24
AM25

AK25
AK26

AL26

AL27

AM27
AM28

AL28

AL29

AJ15
AK15
AH16
AG16
AG17
AH17
AG18
AH18
AK18

AJ18

AJ19
AH19
AG20
AH20
AG21
AH21
AK21

AJ21

AJ22
AH22
AG23
AH23
AK24

AJ24

AJ25
AH25
AH26
AG26
AK27

AJ27

AJ28
AH27

AH14

AJ14
AH15

AM12
AM11

A26

H2

AJ11
AK12

AL12
AK11

AL13

AM4

AK3

U1
U2

T2

T1

1 2

R496

128@

22_0402_5%

U33A

PEX_RX0
PEX_RX0_N
PEX_RX1
PEX_RX1_N
PEX_RX2
PEX_RX2_N
PEX_RX3
PEX_RX3_N
PEX_RX4
PEX_RX4_N
PEX_RX5
PEX_RX5_N
PEX_RX6
PEX_RX6_N
PEX_RX7
PEX_RX7_N
PEX_RX8
PEX_RX8_N
PEX_RX9
PEX_RX9_N
PEX_RX10
PEX_RX10_N
PEX_RX11
PEX_RX11_N
PEX_RX12
PEX_RX12_N
PEX_RX13
PEX_RX13_N
PEX_RX14
PEX_RX14_N
PEX_RX15
PEX_RX15_N

PEX_TX0
PEX_TX0_N
PEX_TX1
PEX_TX1_N
PEX_TX2
PEX_TX2_N
PEX_TX3
PEX_TX3_N
PEX_TX4
PEX_TX4_N
PEX_TX5
PEX_TX5_N
PEX_TX6
PEX_TX6_N
PEX_TX7
PEX_TX7_N
PEX_TX8
PEX_TX8_N
PEX_TX9
PEX_TX9_N
PEX_TX10
PEX_TX10_N
PEX_TX11
PEX_TX11_N
PEX_TX12
PEX_TX12_N
PEX_TX13
PEX_TX13_N
PEX_TX14
PEX_TX14_N
PEX_TX15
PEX_TX15_N

PEX_REFCLK
PEX_REFCLK_N

PEX_RST_N

PEX_TSTCLK_OUT
PEX_TSTCLK_OUT_N

TESTMEMCLK
TESTMODE

JTAG_TCK
JTAG_TDI
JTAG_TDO
JTAG_TMS
JTAG_N

IFPAB_VPROBE
IFPCD_VPROBE

XTALIN
XTALOUT

XTALOUTBUFF

XTALSSIN

NV72/73M_BGA820G71@

1 2

Part 1 of 6

OSC_SPREAD <26>
OSC_OUT <26>

R489
10K_0402_5% @

If Spread spectrum not stuff than stuff resistor

DVO / GPIO

MIOA_CLKOUT

MIOA_CLKOUT_N

PCI EXPRESS

MIOB_CLKOUT

MIOB_CLKOUT_N

DACsI2C

TEST

CLK

4

GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8

GPIO9
GPIO10
GPIO11
GPIO12

MIOAD0
MIOAD1
MIOAD2
MIOAD3
MIOAD4
MIOAD5
MIOAD6
MIOAD7
MIOAD8

MIOAD9
MIOAD10
MIOAD11

MIOA_HSYNC
MIOA_VSYNC

MIOA_DE

MIOA_CTL3

MIOA_CLKIN

MIOA_VREF

MIOBD0

MIOBD1

MIOBD2

MIOBD3

MIOBD4

MIOBD5

MIOBD6

MIOBD7

MIOBD8

MIOBD9
MIOBD10
MIOBD11

MIOB_HSYNC
MIOB_VSYNC

MIOB_DE

MIOB_CTL3

MIOB_CLKIN

MIOB_VREF

DACA_HSYNC
DACA_VSYNC

DACA_RED

DACA_BLUE

DACA_GREEN

DACA_IDUMP

DACA_RSET
DACA_VREF

DACC_HSYNC

DACC_VSYNC

DACC_RED

DACC_BLUE

DACC_GREEN

DACC_IDUMP

DACC_RSET
DACC_VREF

DACB_RED

DACB_BLUE

DACB_GREEN

DACB_IDUMP

DACB_RSET
DACB_VREF

I2CA_SCL

I2CA_SDA

I2CB_SCL

I2CB_SDA
I2CC_SCL
I2CC_SDA
I2CH_SCL
I2CH_SDA

K3
H1
K5
G5
E2
J5
G6
K6
E1
D2
H5
F4
E3

P2
N2
N1
N3
M1
M3
P5
N6
N5
M4
L4
L5

R3
R1
P1
P3

M5
R4
P4

L2
AC3

AC1
AC2
AB2
AB1
AA1
AB3
AA3
AC5
AB5
AB4
AA5

AF3
AE3
AD1
AD3

AE4
AD4
AD5

Y2
AF10

AK10
AH11
AH12
AJ12
AG9
AH9

AH10
AG7

AG5
AF6
AE5
AG6
AG4
AF5

AH4
R6

T6
T5
V7
R7

R5
K2

J3
H4
J4
G2
G1
G3
H3

GPIO11

PEX_PLL_TERM
SUB_VENDOR

PEX_CFG0
PEX_CFG1

PEX_CFG2

R115

10K_0402_5%128@

R90 10K_0402_5%128@

M_HSYNC
M_VSYNC
M_RED
M_BLU
M_GRN

R85

DACAVREF

M_CRMA
M_COMP
M_LUMA

DACB_RSET

DACBVREF

M_DDCCLK
M_DDCDATA
DVI_SCLK
DVI_SDATA

I2CH_SCL
I2CH_SDA

ENVDD
NV_ENBKL

THER_ALERT#

12

RAM_CFG0
RAM_CFG1
CRYSTAL_0
PCI_DEVID2
PCI_DEVID0
PCI_DEVID1
CRYSTAL_1
MOBILE_MODE
RAM_CFG2
RAM_CFG3

PCI_DEVID3

12

1 2

124_0402_5%

1 2

C171 0.01U_0402_16V7K128@

C270

LCD_I2C_CLK_C
LCD_I2C_DAT_C

GPIO11

1 2

R101 2K_0402_5%@

1 2

R100 2K_0402_5%@

128@

1 2

0.01U_0402_16V7K128@

2

3

ENVDD <16>
NV_ENBKL <44>

For VDD_CORE voltage select

PEX_PLL_TERM <26>
SUB_VENDOR <26>

PEX_CFG0 <26>
PEX_CFG1 <26>

PEX_CFG2 <26>

MIOA_VDDQ

RAM_CFG0 <26>
RAM_CFG1 <26>
CRYSTAL_0 <26>
PCI_DEVID2 <26>
PCI_DEVID0 <26>
PCI_DEVID1 <26>
CRYSTAL_1 <26>
MOBILE_MODE <26>
RAM_CFG2 <26>
RAM_CFG3 <26>

PCI_DEVID3 <26>

M_HSYNC <17>
M_VSYNC <17>
M_RED <17>
M_BLU <17>
M_GRN <17>

M_CRMA <17>
M_COMP <17>
M_LUMA <17>

M_DDCCLK <17>
M_DDCDATA <17>

LCD_I2C_CLK_C <16>
LCD_I2C_DAT_C <16>

316_0402_1%@

1 2

316_0402_1%@

13

D

Q6

G

S

1 2

2N7002_SOT23@

PEG_RXP[0:15]
PEG_RXN[0:15]
PEG_M_TXP[0..15]
PEG_M_TXN[0..15]

LVDS_AC+<16>
LVDS_AC-<16>
LVDS_A0+<16>
LVDS_A0-<16>
LVDS_A1+<16>
LVDS_A1-<16>
LVDS_A2+<16>
LVDS_A2-<16>

LVDS_BC+<16>
LVDS_BC-<16>
LVDS_B0+<16>
LVDS_B0-<16>
LVDS_B1+<16>
LVDS_B1-<16>
LVDS_B2+<16>
LVDS_B2-<16>

128@

2.2K_0402_5%

D+

1

D-

2

C683

128@

2200P_0402_25V7K

Close to Sensor

R139

R140

R503

124_0402_5%128@

1 2

1 2

+3VS

12

R467

R88 1K_0402_5%@

12

R504
200_0402_5%

128@

R145

1K_0402_5%@

U34

1

VDD

2

D+

3

D-

4

OVERT#

MAX6649MUA_8UMAX128@

12

PEG_RXP[0:15] <9>
PEG_RXN[0:15] <9>
PEG_M_TXP[0..15] <9>
PEG_M_TXN[0..15] <9>

U33D

AK9

IFPA_TXC

AJ9

IFPA_TXC_N

AH6

IFPA_TXD0

AJ6

IFPA_TXD0_N

AH8

IFPA_TXD1

AH7

IFPA_TXD1_N

AJ8

IFPA_TXD2

AK8

IFPA_TXD2_N

AJ5

IFPA_TXD3

AH5

IFPA_TXD3_N

AK4

IFPB_TXC

AL4

IFPB_TXC_N

AM6

IFPB_TXD4

AM5

IFPB_TXD4_N

AM7

IFPB_TXD5

AL7

IFPB_TXD5_N

AK6

IFPB_TXD6

AK5

IFPB_TXD6_N

AK7

IFPB_TXD7

AL8

IFPB_TXD7_N

AL5

IFPAB_RSET

AM2

IFPC_TXC

AM3

IFPC_TXC_N

AE2

IFPC_TXD0

AE1

IFPC_TXD0_N

AF1

IFPC_TXD1

AF2

IFPC_TXD1_N

AG1

IFPC_TXD2

AH1

IFPC_TXD2_N

AG3

IFPD_TXC

AH2

IFPD_TXC_N

AK1

IFPD_TXD4

AJ1

IFPD_TXD4_N

AL2

IFPD_TXD5

AL1

IFPD_TXD5_N

AJ2

IFPD_TXD6

AJ3

IFPD_TXD6_N

AH3

IFPCD_RSET

NV72/73M_BGA820G71@

1

C686

0.1U_0402_16V4Z

2

128@

8

SCLK

7

SDATA

6

ALERT#

5

GND

I2C address
1001 100x

DACB_RSET

12

R146

88.7_0402_1%

@

2

NC

BUFRST_N
MEMSTRAPSEL0
MEMSTRAPSEL1
MEMSTRAPSEL2
MEMSTRAPSEL3

SWAPRDY_A

THERMDN
THERMDP

ROM_SCLK

ROMCS_N

NC_0
NC_1
NC_2
NC_3
NC_4
NC_5
NC_6
NC_7
NC_8

NC_9
NC_10
NC_11
NC_12
NC_13
NC_14
NC_15
NC_16
NC_17
NC_18
NC_19
NC_20
NC_21
NC_22
NC_23
NC_24
NC_25

STEREO

STRAP

ROM_SI

ROM_SO

Part 4 of 6

LVDS/TMDS

GENERAL

SERIAL

Thermal sensor

+3VS

LCD_I2C_CLK_C
LCD_I2C_DAT_C

1 2

R501 0_0402_5%128@

12

R499

2.2K_0402_5%

128@

THER_ALERT#

R1178 R1180 are optional

、

trim resistor to provide finer
control of the RSET value

B32
C20
D1
J6
U3
U4
U5
U6
V1
V3
V4
V5
V6
W1
W3
W4
W5
Y5
Y6
Y30
AC26
AG12
AH13
AM8
AM9
AM10

F3
AE26

FAE recommand 6/29

AD26
AH31
AH32
T3
F1
M6
J1
K1

AA7
W2
AA6
AA4

LCD_I2C_DAT_C
LCD_I2C_CLK_C
DVI_SCLK
DVI_SDATA
I2CH_SCL
I2CH_SDA

D­D+

R105

1 2

10K_0402_5%

128@

DVI pull-high close to GPU

R502 2.2K_0402_5%128@

1 2

R500 2.2K_0402_5%128@

1 2

R110 2.2K_0402_5%128@

1 2

R106 2.2K_0402_5%128@

1 2

R130 2.2K_0402_5%128@

1 2

R128 2.2K_0402_5%128@

1 2

1

+3VS

+3VS

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/03/10 2006/03/10

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

Compal Electronics, Inc.

G72/73VGA Board

LA-2841

1

1.0

of

18 60Thursday, December 15, 2005

5

FBAD[63..0]

FBAA[12..0]

FBBA[2..5]

DQSA#[7..0]

D D

DQSA[7..0]

DQMA#[7..0]

FBAD[63..0] <22,23>

FBAA[12..0] <22,23>

FBBA[2..5] <23>

DQSA#[7..0] <22,23>

DQSA[7..0] <22,23>

DQMA#[7..0] <22,23>

4

+1.8VS

12

R487

ODTA0

10K_0402_5%@

12

R484

10K_0402_5%128@

3

FBCD[63..0]

FBCA[12..0]

FBDA[2..5]

DQSC#[7..0]

DQSC[7..0]

DQMC#[7..0]

FBCD[63..0] <24,25>

FBCA[12..0] <24,25>

FBDA[2..5] <25>

DQSC#[7..0] <24,25>

DQSC[7..0] <24,25>

DQMC#[7..0] <24,25>

2

+1.8VS

12

R161

ODTC0

10K_0402_5%@

12

R160

10K_0402_5%256@

1

U33C

B7

FBCD0

A7

FBCD1

C7

FBCD2

A2

FBCD3

B2

FBCD4

C4

FBCD5

A5

FBCD6

B5

FBCD7

F9

FBCD8

F10

FBCD9

D12

FBCD10

D9

FBCD11

E12

FBCD12

D11

FBCD13

E8

FBCD14

D8

FBCD15

E7

FBCD16

F7

FBCD17

D6

FBCD18

D5

FBCD19

D3

FBCD20

E4

FBCD21

C3

FBCD22

B4

FBCD23

C10

FBCD24

B10

FBCD25

C8

FBCD26

A10

FBCD27

C11

FBCD28

C12

FBCD29

A11

FBCD30

B11

FBCD31

B28

FBCD32

C27

FBCD33

C26

FBCD34

B26

FBCD35

C30

FBCD36

B31

FBCD37

C29

FBCD38

A31

FBCD39

D28

FBCD40

D27

FBCD41

F26

FBCD42

D24

FBCD43

E23

FBCD44

E26

FBCD45

E24

FBCD46

F23

FBCD47

B23

FBCD48

A23

FBCD49

C25

FBCD50

C23

FBCD51

A22

FBCD52

C22

FBCD53

C21

FBCD54

B22

FBCD55

E22

FBCD56

D22

FBCD57

D21

FBCD58

E21

FBCD59

E18

FBCD60

D19

FBCD61

D18

FBCD62

E19

FBCD63

NV72/73M_BGA820G71@

Part 3 of 6

FBC_CMD0
FBC_CMD1
FBC_CMD2
FBC_CMD3
FBC_CMD4
FBC_CMD5
FBC_CMD6
FBC_CMD7
FBC_CMD8

FBC_CMD9
FBC_CMD10
FBC_CMD11
FBC_CMD12
FBC_CMD13
FBC_CMD14
FBC_CMD15
FBC_CMD16
FBC_CMD17
FBC_CMD18
FBC_CMD19
FBC_CMD20
FBC_CMD21
FBC_CMD22
FBC_CMD23
FBC_CMD24
FBC_CMD25
FBC_CMD26

FBCDQM0
FBCDQM1
FBCDQM2
FBCDQM3
FBCDQM4
FBCDQM5
FBCDQM6
FBCDQM7

FBCDQS_RN0
FBCDQS_RN1
FBCDQS_RN2
FBCDQS_RN3
FBCDQS_RN4
FBCDQS_RN5
FBCDQS_RN6
FBCDQS_RN7

MEMORY INTERFACE B

FBCDQS_WP0
FBCDQS_WP1
FBCDQS_WP2
FBCDQS_WP3
FBCDQS_WP4
FBCDQS_WP5
FBCDQS_WP6
FBCDQS_WP7

FB_VREF2
FBC_CLK0

FBC_CLK0_N

FBC_CLK1

FBC_CLK1_N

FBC_REFCLK

FBC_REFCLK_N

FBC_DEBUG

C13
A16
A13
B17
B20
A19
B19
B14
E16
A14
C15
B16
F17
C19
D15
C17
A17
C16
D14
F16
C14
C18
E14
B13
E15
F15
A20

A4
E11
F5
C9
C28
F24
C24
E20

C6
E9
E6
A8
B29
E25
A25
F21

C5
E10
E5
B8
A29
D25
B25
F20

A28
E13

F13
F18
E17
B1
C1
F12

FBCA3
FBCA0
FBCA2
FBCA1
FBDA3
FBDA4
FBDA5
FBCCS1#
FBCCS0#
FBCWE#
FBC_BA0
FBC_CKE

R142

1 2

FBDA2
FBCRAS#

FBCA11
FBCA10
FBC_BA1
FBCA8
FBCA9
FBCA6
FBCA5
FBCA7
FBCA4
FBCCAS#

DQMC#0
DQMC#1
DQMC#2
DQMC#3
DQMC#4
DQMC#5
DQMC#6
DQMC#7

DQSC#0
DQSC#1
DQSC#2
DQSC#3
DQSC#4
DQSC#5
DQSC#6
DQSC#7

DQSC0
DQSC1
DQSC2
DQSC3
DQSC4
DQSC5
DQSC6
DQSC7

FBA_VREF2
CLKC0

CLKC0#
CLKC1
CLKC1#

1 2

R141 0_0402_5%@

T24

PAD

FBCCS0# <24,25>
FBCWE# <24,25>
FBC_BA0 <24,25>

0_0402_5%256@

FBCRAS# <24,25>

FBC_BA1 <24,25>

FBCCAS# <24,25>

10mil

CLKC0 <24>
CLKC0# <24>
CLKC1 <25>
CLKC1# <25>

12

R135
10K_0402_5%

256@

C355

@

0.1U_0402_16V4Z

FBC_CKE <24,25>

+1.8VS

1

2

12

R138
1K_0402_1%

@

12

R143
1K_0402_1%

@

AD29
AE29
AD28
AC28
AB29
AA30

AB30

AM30

AF30

AJ31
AJ30
AJ32

AK29

AM31

AL30
AE32
AE30
AE31
AD30
AC31
AC32
AB32
AB31
AG27
AF28
AH28
AG28
AG29
AD27
AF27
AE28

U33B

N27

FBAD0

M27

FBAD1

N28

FBAD2

L29

FBAD3

K27

FBAD4

K28

FBAD5

J29

FBAD6

J28

FBAD7

P30

FBAD8

N31

FBAD9

N30

FBAD10

N32

FBAD11

L31

FBAD12

L30

FBAD13

J30

FBAD14

L32

FBAD15

H30

FBAD16

K30

FBAD17

H31

FBAD18

F30

FBAD19

H32

FBAD20

E31

FBAD21

D30

FBAD22

E30

FBAD23

H28

FBAD24

H29

FBAD25

E29

FBAD26

J27

FBAD27

F27

FBAD28

E27

FBAD29

E28

FBAD30

F28

FBAD31
FBAD32
FBAD33
FBAD34
FBAD35
FBAD36
FBAD37

Y28

FBAD38
FBAD39
FBAD40
FBAD41
FBAD42
FBAD43
FBAD44
FBAD45
FBAD46
FBAD47
FBAD48
FBAD49
FBAD50
FBAD51
FBAD52
FBAD53
FBAD54
FBAD55
FBAD56
FBAD57
FBAD58
FBAD59
FBAD60
FBAD61
FBAD62
FBAD63

NV72/73M_BGA820G71@

Part 2 of 6

MEMORY INTERFACE A

FBA_CMD0
FBA_CMD1
FBA_CMD2
FBA_CMD3
FBA_CMD4
FBA_CMD5
FBA_CMD6
FBA_CMD7
FBA_CMD8

FBA_CMD9
FBA_CMD10
FBA_CMD11
FBA_CMD12
FBA_CMD13
FBA_CMD14
FBA_CMD15
FBA_CMD16
FBA_CMD17
FBA_CMD18
FBA_CMD19
FBA_CMD20
FBA_CMD21
FBA_CMD22
FBA_CMD23
FBA_CMD24
FBA_CMD25
FBA_CMD26

FBADQM0
FBADQM1
FBADQM2
FBADQM3
FBADQM4
FBADQM5
FBADQM6
FBADQM7

FBADQS_RN0
FBADQS_RN1
FBADQS_RN2
FBADQS_RN3
FBADQS_RN4
FBADQS_RN5
FBADQS_RN6
FBADQS_RN7

FBADQS_WP0
FBADQS_WP1
FBADQS_WP2
FBADQS_WP3
FBADQS_WP4
FBADQS_WP5
FBADQS_WP6
FBADQS_WP7

FB_VREF1

FBA_CLK0

FBA_CLK0_N

FBA_CLK1

FBA_CLK1_N

FBA_REFCLK

FBA_REFCLK_N

FBA_DEBUG

FBAD0
FBAD1
FBAD2
FBAD3
FBAD4
FBAD5
FBAD6
FBAD7
FBAD8
FBAD9
FBAD10
FBAD11
FBAD12
FBAD13
FBAD14
FBAD15
FBAD16
FBAD17

C C

FBAD18
FBAD19
FBAD20
FBAD21
FBAD22
FBAD23
FBAD24
FBAD25
FBAD26
FBAD27
FBAD28
FBAD29
FBAD30
FBAD31
FBAD32
FBAD33 DQMA#5
FBAD34
FBAD35
FBAD36
FBAD37
FBAD38
FBAD39
FBAD40
FBAD41
FBAD42
FBAD43
FBAD44
FBAD45
FBAD46
FBAD47
FBAD48
FBAD49

B B

FBAD50
FBAD51
FBAD52
FBAD53
FBAD54
FBAD55
FBAD56
FBAD57
FBAD58
FBAD59
FBAD60
FBAD61
FBAD62
FBAD63

FBAA3

P32

FBAA0

U27

FBAA2

P31

FBAA1

U30

FBBA3

Y31

FBBA4

W32

FBBA5

W31

FBACS1#

T32

FBACS0#

V27

FBAWE#

T28

FBA_BA0

T31

FBA_CKE

U32
W29
W30
T27
V28
V30
U31
R27
V29
T30
W28
R29
R30
P29
U28
Y32

M29
M30
G30
F29
AA29
AK30
AC30
AG30

M28
K32
G31
G27
AA28
AL31
AF31
AH29

L28
K31
G32
G28
AB28
AL32
AF32
AH30

E32
P28

R28
Y27
AA27
D32
D31
AC27

R96

1 2

FBBA2
FBAA12 FBCA12
FBARAS#
FBAA11
FBAA10
FBA_BA1
FBAA8
FBAA9
FBAA6
FBAA5
FBAA7
FBAA4
FBACAS#

DQMA#0
DQMA#1
DQMA#2
DQMA#3
DQMA#4

DQMA#6
DQMA#7

DQSA#0
DQSA#1
DQSA#2
DQSA#3
DQSA#4
DQSA#5
DQSA#6
DQSA#7

DQSA0
DQSA1
DQSA2
DQSA3
DQSA4
DQSA5
DQSA6
DQSA7

FBA_VREF1

CLKA0
CLKA0#
CLKA1
CLKA1#

1 2

R94 0_0402_5%@

T21

PAD

FBACS0# <22,23>
FBAWE# <22,23>
FBA_BA0 <22,23>

ODTA0 ODTC0

0_0402_5%128@

FBARAS# <22,23>

FBA_BA1 <22,23>

FBACAS# <22,23>

10mil

CLKA0 <22>
CLKA0# <22>
CLKA1 <23>
CLKA1# <23>

ODTA0 ODTC0

ODTA0 <22,23> ODTC0 <24,25>

12

R97
10K_0402_5%

128@

FBA_CKE <22,23>

C687

0.1U_0402_16V4Z

1

2

10mil

+1.8VS

12

R506
1K_0402_1%

12

R505
1K_0402_1%

FBCD0
FBCD1
FBCD2
FBCD3
FBCD4
FBCD5
FBCD6
FBCD7
FBCD8
FBCD9
FBCD10
FBCD11
FBCD12
FBCD13
FBCD14
FBCD15
FBCD16
FBCD17
FBCD18
FBCD19
FBCD20
FBCD21
FBCD22
FBCD23
FBCD24
FBCD25
FBCD26
FBCD27
FBCD28
FBCD29
FBCD30
FBCD31
FBCD32
FBCD33
FBCD34
FBCD35
FBCD36
FBCD37
FBCD38
FBCD39
FBCD40
FBCD41
FBCD42
FBCD43
FBCD44
FBCD45
FBCD46
FBCD47
FBCD48
FBCD49
FBCD50
FBCD51
FBCD52
FBCD53
FBCD54
FBCD55
FBCD56
FBCD57
FBCD58
FBCD59
FBCD60
FBCD61
FBCD62
FBCD63

A A

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/03/10 2006/03/10

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

Compal Electronics, Inc.

G72/73VGA Board

LA-2841

1

1.0

of

19 60Thursday, December 15, 2005

5

VID_PLLVDD

40mA

1

128@

470P_0402_50V7K

2

PLLVDD

40mA

1

128@

470P_0402_50V7K

2

FBA_PLLAVDD

1

128@

4700P_0402_25V7K

2

FBA_PLLVDD

1

4700P_0402_25V7K@

2

FBC_PLLAVDD

1

C788
4700P_0402_25V7K

2

128@

1

2

L9

1 2

C199

L8

1 2

C261

(+1.1VS)

+VGA_CORE

0.1U_0402_16V4Z
C265

128@

220P_0402_50V7K
C243

128@

220P_0402_50V7K

1U_0603_10V4Z

1

C286

2

128@

0.1U_0402_16V4Z

1

C264

2

128@

220P_0402_50V7K

C321

128@

+3VS

C181

128@

4700P_0402_25V7K

C290

128@

+1.8VS

+3VS

0.1U_0402_16V4Z
C289

1

1

128@

2

2

100P_0402_50V8J

C281

1

128@

2

220P_0402_50V7K

C320

1

128@

2

10U_0805_10V4Z

4700P_0402_25V7K

C209

1

1

128@

2

2

1

1

C340

2

2

128@

0.1U_0402_16V4Z

R95

1 2

0_0603_5%

128@

+1.2VS

C269

128@

0.1U_0402_16V4Z

1

2

100P_0402_50V8J

1

2

220P_0402_50V7K

C254

128@

C219

128@

0.022U_0402_16V7K

0.1U_0402_16V4Z
C322

128@

VID_PLLVDD、PLLVDD
IFPAB_PLLVDD at G71/72
is +2.5VS

+2.5VS

L17

1 2

D D

BLM11A121SPT_0603

128@

4700P_0402_25V7K

+2.5VS

1 2

BLM11A121SPT_0603

128@

4700P_0402_25V7K

+1.2VS

BLM11A121SPT_0603

128@

2.2U_0603_6.3V6K

C C

+3VS

BLM11A121SPT_0603@

2.2U_0603_6.3V6K@

+1.2VS

BLM11A121SPT_0603

128@

2.2U_0603_6.3V6K

+3VS

B B

BLM11A121SPT_0603@

DACA_VDD

470P_0402_50V7K

DACB_VDD

470P_0402_50V7K

A A

C278

128@

L16

C247

128@

L19

1 2

C306

128@

L21

1 2

C294

L22

1 2

C332

128@

L20

1 2

2.2U_0603_6.3V6K@

1

C200

128@

2

1

C252

128@

2

1

2

1

2

C317

2.2U_0603_6.3V6K

2.2U_0603_6.3V6K

1

C267

2

128@

2.2U_0603_6.3V6K

1

C227

2

128@

2.2U_0603_6.3V6K

1

C336

2

128@

4700P_0402_25V7K

1

C339

2

4700P_0402_25V7K@

1

C334

2

128@

4700P_0402_25V7K

1

C344

2

128@

1

C120

2

128@

1

C119

2

、

1

2

1

2

1

2

1

2

4700P_0402_25V7K@

C279

C255

C335

C346

FBC_PLLVDD

C337 4700P_0402_25V7K@

1

2

1

2

BLM11A121SPT_0603

128@
128@

4700P_0402_25V7K

BLM11A121SPT_0603

128@
128@

4700P_0402_25V7K

0.1U_0402_16V4Z
C287

1

128@

2

100P_0402_50V8J

1

C263

2

128@

1

C245

2

128@

1

2

0.022U_0402_16V7K

1

2

1

2

C262

128@

L12

1 2

BLM11A121SPT_0603128@

4

1

C266

2

128@

0.1U_0402_16V4Z

C257

1

128@

C241

2

128@

100P_0402_50V8J

220P_0402_50V7K

C284

1

128@

2

100P_0402_50V8J

C258

1

128@

C244

2

128@

0.1U_0402_16V4Z

C296

1

128@

C288

2

128@

0.022U_0402_16V7K

+1.8VS

0.022U_0402_16V7K
C223

1

1

128@

2

2

0.1U_0402_16V4Z

330U_V_2.5VK_R9

1

C706

1

+

128@

2

2

R104

1 2

1

2

1

2

1

2

R102

C256 4700P_0402_25V7K

128@

2

C207

4.7U_0603_6.3V6M128@

1

0_0402_5%@

1

C251

2

128@

220P_0402_50V7K

0.022U_0402_16V7K
C291

1

128@

2

FBA_PLLAVDD
FBC_PLLAVDD
FBA_PLLVDD
FBC_PLLVDD

1 2

40.2_0603_1%128@

+VGA_FBVTT

1

2

T33

PAD

NV

VID_PLLVDD
PLLVDD

1

2

K16

K17
N13
N14
N16
N17
N19
N20

P13

P14

P16

P17

P19
R16
R17

NV

T13

T14

T15

T18

T19
U13
U14
U15
U19

V16

V17

W13
W14
W16
W17
W19

Y13

Y14

Y16

Y17

Y19

Y20
U18

P20

T20

T23
U20
U23

W20

H7

J7

K7

L7
L8

L10
M10

AC11
AC12
AC24
AD24
AE11
AE12

T10

T9

G25
G10
G23

G8

K26
H16

H17

J9
J10
J23
J24

K9
K11
K12
K21
K22
K24
L23

M23

T25

U25
AA23
AB23

F6

C283

0.022U_0402_16V7K

128@

U33E

VDD_0
VDD_1
VDD_2
VDD_3
VDD_4
VDD_5
VDD_6
VDD_7
VDD_8
VDD_9
VDD_10
VDD_11
VDD_12
VDD_13
VDD_14
VDD_15
VDD_16
VDD_17
VDD_18
VDD_19
VDD_20
VDD_21
VDD_22
VDD_23
VDD_24
VDD_25
VDD_26
VDD_27
VDD_28
VDD_29
VDD_30
VDD_31
VDD_32
VDD_33
VDD_34
VDD_35
VDD_36
VDD_37

VDD_LP_0
VDD_LP_1
VDD_LP_2
VDD_LP_3
VDD_LP_4
VDD_LP_5

VDD33_0
VDD33_1
VDD33_2
VDD33_3
VDD33_4
VDD33_5
VDD33_6
VDD33_7
VDD33_8
VDD33_9
VDD33_10
VDD33_11
VDD33_12

VID_PLLVDD
PLLVDD

FBA_PLLAVDD
FBC_PLLAVDD
FBA_PLLVDD
FBC_PLLVDD
FBCAL_PD_VDDQ

FBVTT_0
FBVTT_1
FBVTT_2
FBVTT_3
FBVTT_4
FBVTT_5
FBVTT_6
FBVTT_7
FBVTT_8
FBVTT_9
FBVTT_10
FBVTT_11
FBVTT_12
FBVTT_13
FBVTT_14
FBVTT_15
FBVTT_16
FBVTT_17

CLAMP

NV72/73M_BGA820G71@

Part 5 of 6

POWER

3

PEX_IOVDD_0
PEX_IOVDD_1
PEX_IOVDD_2
PEX_IOVDD_3
PEX_IOVDD_4
PEX_IOVDD_5

PEX_IOVDDQ_0
PEX_IOVDDQ_1
PEX_IOVDDQ_2
PEX_IOVDDQ_3
PEX_IOVDDQ_4
PEX_IOVDDQ_5
PEX_IOVDDQ_6
PEX_IOVDDQ_7
PEX_IOVDDQ_8
PEX_IOVDDQ_9

PEX_IOVDDQ_10

PEX_PLLAVDD
PEX_PLLDVDD

MIOA_VDDQ_0
MIOA_VDDQ_1
MIOA_VDDQ_2
MIOA_VDDQ_3
MIOA_VDDQ_4
MIOB_VDDQ_0
MIOB_VDDQ_1
MIOB_VDDQ_2
MIOB_VDDQ_3

MIOB_VDDQ_4
MIOACAL_PD_VDDQ
MIOBCAL_PD_VDDQ

IFPA_IOVDD
IFPB_IOVDD
IFPC_IOVDD
IFPD_IOVDD

IFPAB_PLLVDD
IFPCD_PLLVDD

DACA_VDD
DACB_VDD
DACC_VDD

FBVDD_0
FBVDD_1
FBVDD_2
FBVDD_3
FBVDD_4
FBVDD_5
FBVDD_6
FBVDD_7
FBVDD_8

FBVDD_9
FBVDD_10
FBVDD_11
FBVDD_12
FBVDD_13
FBVDD_14
FBVDD_15
FBVDD_16
FBVDD_17
FBVDD_18
FBVDD_19

FBVDDQ_0
FBVDDQ_1
FBVDDQ_2
FBVDDQ_3
FBVDDQ_4
FBVDDQ_5
FBVDDQ_6
FBVDDQ_7
FBVDDQ_8

FBVDDQ_9
FBVDDQ_10
FBVDDQ_11
FBVDDQ_12
FBVDDQ_13
FBVDDQ_14
FBVDDQ_15
FBVDDQ_16
FBVDDQ_17
FBVDDQ_18
FBVDDQ_19
FBVDDQ_20
FBVDDQ_21
FBVDDQ_22
FBVDDQ_23

AD23
AF23
AF24
AF25
AG24
AG25

AC16
AC17
AC21
AC22
AE18
AE21
AE22
AF12
AF18
AF21
AF22

AF15
AE15

M7
M8
R8
T8
U9
AA8
AB7
AB8
AC6
AC7

MIOACAL_PD_VDDQ

L1

MIOBCAL_PD_VDDQ

Y1

120mA

AF9
AF8
AD6
AE7

40mA

AC9

40mA

AA10

1 2

10K_0402_5%128@

AD10
V8
AD7

10K_0402_5%128@

A3
A6
A9
A12
A15
A18
A21
A24
A27
A30
C32
F32
J32
M32
R32
V32
AA32
AD32
AG32
AK32

G11
G12
G15
G18
G21
G22
H11
H12
H15
H18
H21
L25
L26
M25
M26
R25
R26
V25
V26
AA25
AA26
AB25
AB26
H22

1808mA

0.022U_0402_16V7K
C197

128@

1

C178

2

128@

0.022U_0402_16V7K

0.01U_0402_16V7K

C184

1

128@

2

C198

128@

0.01U_0402_16V7K

PEX_PLLAVDD
PEX_PLLDVDD

MIOA_VDDQ

MIOB_VDDQ

IFPA_IOVDD
IFPB_IOVDD

R61 10K_0402_5%128@

1 2

R62 10K_0402_5%128@

1 2

IFPAB_PLLVDD

R93

DACA_VDD
DACB_VDD

R91

0.022U_0402_16V7K

180mA

20mA

C185

128@

T22
PAD
T20
PAD

70mA
140mA

C213

128@

12

IFPA_IOVDD IFPB_IOVDD
at G71/72 is +1.8VS
at NV43/44 is +LCDVDD

4700P_0402_25V7K

C276

1

128@

C293

2

128@

4700P_0402_25V7K

0.022U_0402_16V7K
C326

1

128@

C324

2

128@

1

1

C172

2

2

128@

0.022U_0402_16V7K

1

1

2

2

C212

128@

0.01U_0402_16V7K

2.2U_0603_6.3V6K
C121

1

1

128@

2

2

470P_0402_50V7K

2.2U_0603_6.3V6K
C201

1

128@

2

470P_0402_50V7K

、

4700P_0402_25V7K

1

1

C253

2

2

128@

4700P_0402_25V7K

1

1

C325

2

2

128@

0.1U_0402_16V4Z

2

0.022U_0402_16V7K
C195

128@

1

2

0.022U_0402_16V7K

0.01U_0402_16V7K
C177

1

128@

2

C182

128@

0.01U_0402_16V7K

128@

1 2

BLM11A121SPT_0603

1

C186

2

128@

4700P_0402_25V7K

1

C208

2

128@

4700P_0402_25V7K

C217

1

128@

C319

2

128@

4700P_0402_25V7K

0.1U_0402_16V4Z

C342

1

128@

C343

2

128@

0.1U_0402_16V4Z

1

C220

2

128@

0.01U_0402_16V7K
C183

1

128@

2

L10

L13

1 2

BLM11A121SPT_0603

1

128@

2

0.022U_0402_16V7K
C282

1

128@

2

0.1U_0402_16V4Z
C240

1

128@

2

1

C190

128@

2

2.2U_0603_6.3V6K

1

1

2

2

C242

128@

10U_0805_10V4Z
470P_0402_50V7K

+1.8VS

1

2

C210

128@

470P_0402_50V7K

+2.5VS

0.022U_0402_16V7K

1

1

C271

2

2

128@

0.022U_0402_16V7K

1

1

C216

2

2

128@

0.1U_0402_16V4Z

10U_0805_10V4Z
C260

1

128@

2

PEX_PLLAVDD

C189

1

1

128@

C188

2

2

128@

4700P_0402_25V7K

4700P_0402_25V7K

C203

1

128@

2

MIOA_VDDQ

MIOB_VDDQ

C338

1

128@

C285

2

128@

4.7U_0805_10V4Z

0.1U_0402_16V4Z
C292

1

128@

C345

2

128@

0.1U_0402_16V4Z

+1.2VS

1

C277

128@

10U_0805_10V4Z

2

1 2

BLM11A121SPT_0603

128@

1

C221

128@

2

2.2U_0603_6.3V6K

1 2

BLM11A121SPT_0603

128@

1

C196

128@

2

2.2U_0603_6.3V6K

MIOA_VDDQ

1 2

BLM11A121SPT_0603

128@

1

128@

0.1U_0402_16V4Z

2

MIOB_VDDQ

1 2

BLM11A121SPT_0603

128@

1

128@

0.1U_0402_16V4Z

2

+1.8VS

4.7U_0805_10V4Z
C667

1

128@

2

1

2

L14

L15

L18

C268

L11

C211

1

C627

2

128@

330U_V_2.5VK_R9

+3VS

1

+

2

1

+1.2VS

1

C218

128@

2.2U_0603_6.3V6K

2

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/03/10 2006/03/10

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

Compal Electronics, Inc.

G72/73VGA Board

LA-2841

1

1.0

of

20 60Thursday, December 15, 2005

5

U33F

B3

GND_0

B6

GND_1

B9

GND_2

B12

GND_3

B15

GND_4

B18

D D

C C

B B

GND_5

B21

GND_6

B24

GND_7

B27

GND_8

B30

GND_9

C2

GND_10

C31

GND_11

D4

GND_12

D7

GND_13

D10

GND_14

D13

GND_15

D17

GND_16

D20

GND_17

D23

GND_18

D26

GND_19

D29

GND_20

F2

GND_21

F8

GND_22

F11

GND_23

F14

GND_24

F19

GND_25

F22

GND_26

F25

GND_27

F31

GND_28

G4

GND_29

G7

GND_30

G26

GND_31

G29

GND_32

H27

GND_33

H6

GND_34

J2

GND_35

J16

GND_36

J17

GND_37

J31

GND_38

K10

GND_39

K23

GND_40

K29

GND_41

K4

GND_42

L6

GND_43

L27

GND_44

M2

GND_45

M12

GND_46

M21

GND_47

M31

GND_48

N4

GND_49

N15

GND_50

N18

GND_51

N29

GND_52

P6

GND_53

P15

GND_54

P18

GND_55

P27

GND_56

R2

GND_57

R13

GND_58

R14

GND_59

R15

GND_60

R18

GND_61

R19

GND_62

R20

GND_63

R31

GND_64

T4

GND_65

T16

GND_66

T17

GND_67

T24

GND_68

T29

GND_69

U8

GND_70

U16

GND_71

U17

GND_72

U24

GND_73

U29

GND_74

V2

GND_75

V13

GND_76

V14

GND_77

V15

GND_78

V18

GND_79

V19

GND_80

V20

GND_81

V31

GND_82

W6

GND_83

NV72/73M_BGA820G71@

Part 6 of 6

GND

MIOACAL_PU_GND
MIOBCAL_PU_GND

FBCAL_TERM_GND

IFPAB_PLLGND
IFPCD_PLLGND

PEX_PLLGND

FBA_PLLGND
FBC_PLLGND

FBCAL_PU_GND

GND_85
GND_86
GND_87
GND_88
GND_89
GND_90
GND_91
GND_92
GND_93
GND_94
GND_95
GND_96
GND_97
GND_98

GND_99
GND_100
GND_101
GND_102
GND_103
GND_104
GND_105
GND_106
GND_107
GND_108
GND_109
GND_110
GND_111
GND_112
GND_113
GND_114
GND_115
GND_116
GND_117
GND_118
GND_119
GND_120
GND_121
GND_122
GND_123
GND_124
GND_125
GND_126
GND_127
GND_128
GND_129
GND_130
GND_131
GND_132
GND_133
GND_134
GND_135
GND_136
GND_137
GND_138
GND_139
GND_140
GND_141
GND_142
GND_143
GND_144
GND_145
GND_146
GND_147
GND_148
GND_149
GND_150
GND_151
GND_152
GND_153
GND_154

PLLGND

W18
Y4
Y15
Y18
Y29
AA2
AA12
AA21
AA31
AB6
AB27
AC4
AC10
AC23
AC29
AD2
AD16
AD17
AD31
AE6
AE17
AE27
AF4
AF7
AF11
AF26
AF29
AG2
AG8
AG10
AG11
AG13
AG14
AG15
AG19
AG22
AG31
AH24
AJ4
AJ7
AJ10
AJ13
AJ16
AJ17
AJ20
AJ23
AJ26
AJ29
AK2
AL3
AL6
AL9
AL10
AK28
AK31
AL11
AL14
AL19
AL22
AL25
AM13
AM16
AM17
AM20
AM23
AM26
AM29
D16
W27
W15

AD9
AB10

L3
Y3

AE16
U10
G24

G9
H26

J26

4

3

For NV73 R116 change to 40.2_0603_1%(SD014402A80)

R116 30_0603_1%128@

1 2

R103 40.2_0402_1%128@

1 2

2

1

A A

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/03/10 2006/03/10

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

Compal Electronics, Inc.

G72/73VGA Board

LA-2841

1

1.0

of

21 60Thursday, December 15, 2005

5

4

3

2

1

FBA_BA0

D D

C C

+1.8VS

VRAM_VREFA VRAM_VREFA

R486

1K_0402_1%

128@

R485
1K_0402_1%

128@

C672

0.047U_0402_16V4Z

128@

Close to U76 Close to U77

FBA_BA1
FBAA12

FBAA11
FBAA10
FBAA9
FBAA8
FBAA7
FBAA6
FBAA5
FBAA4
FBAA3
FBAA2
FBAA1
FBAA0

CLKA0#
CLKA0

FBA_CKE

FBACS0#
FBAWE#
FBARAS#
FBACAS#
DQMA#2

DQMA#0

ODTA0

DQSA2 DQSA1
DQSA#2 DQSA#1

DQSA0
DQSA#0

(SSTL-1.8) VREF = .5*VDDQ

U35

L2

BA0

L3

BA1

R2

A12

P7

A11

M2

A10/AP

P3

A9

P8

A8

P2

A7

N7

A6

N3

A5

N8

A4

N2

A3

M7

A2

M3

A1

M8

A0

K8

CK

J8

CK

K2

CKE

L8

CS

K3

WE

K7

RAS

L7

CAS

F3

LDM

B3

UDM

K9

ODT

F7

LDQS

E8

LDQS

B7

UDQS

A8

UDQS

J2

VREF

A2

NC#A2

E2

NC#E2

L1

NC#L1

R3

NC#R3

R7

NC#R7

R8

NC#R8

HY5PS561621F-25128@

DQ15
DQ14
DQ13
DQ12
DQ11
DQ10

DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0

VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9

VDDQ10

VDD1
VDD2
VDD3
VDD4
VDD5

VDDL

VSSDL

VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8
VSSQ9

VSSQ10

VSS1
VSS2
VSS3
VSS4
VSS5

FBAD5

B9

FBAD1

B1

FBAD7

D9

FBAD0

D1

FBAD3

D3

FBAD6

D7

FBAD2

C2

FBAD4

C8

FBAD21

F9

FBAD19

F1

FBAD18

H9

FBAD17

H1

FBAD16

H3

FBAD22

H7

FBAD23

G2

FBAD20

G8

A9
C1
C3
C7
C9
E9
G1
G3
G7
G9

A1
E1
J9
M9
R1

J1
J7

A7
B2
B8
D2
D8
E7
F2
F8
H2
H8

A3
E3
J3
N1
P9

1

C675

0.1U_0402_16V4Z

2

128@

+1.8VS

1

C676
1U_0402_6.3V4Z

2

128@

C362

0.047U_0402_16V4Z

128@

FBA_BA0
FBA_BA1

FBAA12
FBAA11
FBAA10
FBAA9
FBAA8
FBAA7
FBAA6
FBAA5
FBAA4
FBAA3
FBAA2
FBAA1
FBAA0

CLKA0#
CLKA0

FBA_CKE

FBACS0#
FBAWE#
FBARAS#
FBACAS#

DQMA#3

ODTA0

DQSA3
DQSA#3

(SSTL-1.8) VREF = .5*VDDQ

U2

L2

BA0

L3

BA1

R2

A12

P7

A11

M2

A10/AP

P3

A9

P8

A8

P2

A7

N7

A6

N3

A5

N8

A4

N2

A3

M7

A2

M3

A1

M8

A0

K8

CK

J8

CK

K2

CKE

L8

CS

K3

WE

K7

RAS

L7

CAS

F3

LDM

B3

UDM

K9

ODT

F7

LDQS

E8

LDQS

B7

UDQS

A8

UDQS

J2

VREF

A2

NC#A2

E2

NC#E2

L1

NC#L1

R3

NC#R3

R7

NC#R7

R8

NC#R8

HY5PS561621F-25128@

DQ15
DQ14
DQ13
DQ12
DQ11
DQ10

DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0

VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9

VDDQ10

VDD1
VDD2
VDD3
VDD4
VDD5

VDDL

VSSDL

VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8
VSSQ9

VSSQ10

VSS1
VSS2
VSS3
VSS4
VSS5

FBAD25

B9

FBAD27

B1

FBAD26

D9

FBAD30

D1

FBAD29

D3

FBAD24

D7

FBAD28

C2

FBAD31

C8

FBAD11

F9

FBAD14

F1

FBAD8

H9

FBAD12

H1

FBAD13

H3

FBAD10

H7

FBAD15

G2

FBAD9

G8

A9
C1
C3
C7
C9
E9
G1
G3
G7
G9

A1
E1
J9
M9
R1

J1
J7

A7
B2
B8
D2
D8
E7
F2
F8
H2
H8

A3
E3
J3
N1
P9

1

C359

0.1U_0402_16V4Z

2

128@

+1.8VS

1

C358
1U_0402_6.3V4Z

2

128@

CLKA0<19>

CLKA0#<19>

R510

120_0402_5%

128@

FBAD[63..0]<19,23>

FBAA[12..0]<19,23>

DQSA#[7..0]<19,23>

DQSA[7..0]<19,23>

DQMA#[7..0]<19,23>

FBA_BA[1..0]<19,23>

ODTA0<19,23>
FBA_CKE<19,23>
FBARAS#<19,23>
FBACAS#<19,23>
FBAWE#<19,23>
FBACS0#<19,23>

Close to U10

12

12

1 2

R513

120_0402_5%@

R515
120_0402_5%

@

FBAD[63..0]

FBAA[12..0]

DQSA#[7..0]

DQSA[7..0]

DQMA#[7..0]

FBA_BA[1..0]

+1.8VS

1

2

ODTA0

FBA_CKE
FBARAS#
FBACAS#

FBAWE#DQMA#1

FBACS0#

CLKA0

C365

0.1U_0402_16V4Z

@

CLKA0#

For NV73 R510 change to 481_0402_1%(SD00000CA80)

128@

0.01U_0402_16V7K

1

2

C684

DDR2 BGA MEMORY

C692

1

2

1U_0402_6.3V4Z

1

2

C671

128@

0.1U_0402_16V4Z

128@

1

2

C705

1

2

C704

128@

0.1U_0402_16V4Z

C703

128@

0.1U_0402_16V4Z

1

2

1

C702

0.01U_0402_16V7K

2

128@

128@

C360

1000P_0402_50V7K

1

2

128@

0.01U_0402_16V7K

1

2

B B

+1.8VS +1.8VS

1

128@

C674

1000P_0402_50V7K

2

128@

0.01U_0402_16V7K

C363

128@

0.01U_0402_16V7K

1

2

C361

DDR2 BGA MEMORY

C274

128@

1U_0402_6.3V4Z

1

1

2

2

C364

128@

0.1U_0402_16V4Z

0.1U_0402_16V4Z

128@

1

2

C323

128@

0.01U_0402_16V7K

1

2

C673

1

C354

0.01U_0402_16V7K

2

128@

A A

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/03/10 2006/03/10

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

Compal Electronics, Inc.

G72/73VGA Board

LA-2841

1

1.0

of

22 60Thursday, December 15, 2005

5

D D

FBA_BA0
FBA_BA1

FBAA12
FBAA11
FBAA10
FBAA9
FBAA8
FBAA7
FBAA6
FBBA5
FBBA4
FBBA3
FBBA2
FBAA1
FBAA0

CLKA1#
CLKA1

FBA_CKE

FBACS0#

C C

+1.8VS

VRAM_VREFB

R575

1K_0402_1%

128@

B B

R574
1K_0402_1%

128@

C636

0.047U_0402_16V4Z

128@

Close to U78 Close to U79

FBAWE#
FBARAS#
FBACAS#

ODTA0

DQSA5
DQSA#5

DQSA#4

(SSTL-1.8) VREF = .5*VDDQ

U32

L2
L3

R2

P7

M2

P3
P8
P2

N7
N3
N8
N2
M7
M3
M8

K8
J8

K2

L8
K3
K7
L7
F3

B3

K9

F7
E8

B7
A8

J2
A2

E2
L1

R3
R7
R8

HY5PS561621F-25128@

BA0
BA1

A12
A11
A10/AP
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0

CK
CK

CKE

CS
WE
RAS
CAS
LDM

UDM

ODT

LDQS
LDQS

UDQS
UDQS

VREF
NC#A2

NC#E2
NC#L1
NC#R3
NC#R7
NC#R8

4

DQ15
DQ14
DQ13
DQ12
DQ11
DQ10

DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0

VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9

VDDQ10

VDD1
VDD2
VDD3
VDD4
VDD5

VDDL

VSSDL

VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8
VSSQ9

VSSQ10

VSS1
VSS2
VSS3
VSS4
VSS5

3

FBAD39

B9

FBAD35

B1

FBAD38

D9

FBAD34

D1

FBAD32

D3

FBAD37

D7

FBAD33

C2

FBAD36

C8

FBAD45

F9

FBAD46

F1

FBAD41

H9

FBAD40

H1

FBAD47 FBAD52

H3

FBAD42

H7

FBAD44 FBAD53

G2

FBAD43

G8

A9
C1
C3
C7
C9
E9
G1
G3
G7
G9

A1
E1
J9
M9
R1

J1
J7

A7
B2
B8
D2
D8
E7
F2
F8
H2
H8

A3
E3
J3
N1
P9

1

C633

0.1U_0402_16V4Z

2

128@

+1.8VS

C632

1

1U_0402_6.3V4Z

128@

2

VRAM_VREFB

C670

0.047U_0402_16V4Z

128@

FBA_BA0
FBA_BA1

FBAA12
FBAA11
FBAA10
FBAA9
FBAA8
FBAA7
FBAA6
FBBA5
FBBA4
FBBA3
FBBA2
FBAA1
FBAA0

CLKA1#
CLKA1

FBA_CKE

FBACS0#

FBAWE#
FBARAS#
FBACAS#

DQMA#6DQMA#5
DQMA#7DQMA#4

ODTA0

DQSA6
DQSA#6

DQSA7DQSA4
DQSA#7

(SSTL-1.8) VREF = .5*VDDQ

U1

L2

BA0

L3

BA1

R2

A12

P7

A11

M2

A10/AP

P3

A9

P8

A8

P2

A7

N7

A6

N3

A5

N8

A4

N2

A3

M7

A2

M3

A1

M8

A0

K8

CK

J8

CK

K2

CKE

L8

CS

K3

WE

K7

RAS

L7

CAS

F3

LDM

B3

UDM

K9

ODT

F7

LDQS

E8

LDQS

B7

UDQS

A8

UDQS

J2

VREF

A2

NC#A2

E2

NC#E2

L1

NC#L1

R3

NC#R3

R7

NC#R7

R8

NC#R8

HY5PS561621F-25128@

DQ15
DQ14
DQ13
DQ12
DQ11
DQ10

DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0

VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9

VDDQ10

VDD1
VDD2
VDD3
VDD4
VDD5

VDDL

VSSDL

VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8
VSSQ9

VSSQ10

VSS1
VSS2
VSS3
VSS4
VSS5

2

FBAD57

B9

FBAD56

B1

FBAD58

D9

FBAD63

D1

FBAD61

D3

FBAD59

D7

FBAD60

C2

FBAD62

C8

FBAD51

F9

FBAD55

F1

FBAD50

H9

FBAD54

H1
H3

FBAD48

H7
G2

FBAD49

G8

A9
C1
C3
C7
C9
E9
G1
G3
G7
G9

A1
E1
J9
M9
R1

J1
J7

A7
B2
B8
D2
D8
E7
F2
F8
H2
H8

A3
E3
J3
N1
P9

1

C272

0.1U_0402_16V4Z

2

128@

+1.8VS

1

C273
1U_0402_6.3V4Z

2

128@

CLKA1<19>

CLKA1#<19>

R75

120_0402_5%

128@

FBAD[63..0]<19,22>

FBAA[12..0]<19,22>

FBBA[2..5]<19>

DQSA#[7..0]<19,22>

DQSA[7..0]<19,22>

DQMA#[7..0]<19,22>

FBA_BA[1..0]<19,22>

ODTA0<19,22>
FBA_CKE<19,22>
FBARAS#<19,22>
FBACAS#<19,22>
FBAWE#<19,22>
FBACS0#<19,22>

12

R70
120_0402_5%

@

12

R69

1 2

120_0402_5%

@

Close to U11

FBAD[63..0]

FBAA[12..0]

DQSA#[7..0]

DQSA[7..0]

DQMA#[7..0]

FBA_BA[1..0]

ODTA0

FBA_CKE
FBARAS#
FBACAS#

FBAWE#

FBACS0#

+1.8VS

1

2

1

FBBA[2..5]

CLKA1

C154

0.1U_0402_16V4Z

@

CLKA1#

For NV73 R75 change to 481_0402_1%(SD00000CA80)

+1.8VS

C631

128@

1000P_0402_50V7K

1

2

128@

0.01U_0402_16V7K

128@

0.01U_0402_16V7K

1

2

C635

DDR2 BGA MEMORY

C634

1

2

128@

1U_0402_6.3V4Z

1

2

C638

128@

0.1U_0402_16V4Z

C259

1

2

128@

0.1U_0402_16V4Z

1

2

C194

128@

0.1U_0402_16V4Z

C246

1

1

2

128@

0.01U_0402_16V7K

2

C224

+1.8VS

C155

128@

1000P_0402_50V7K

1

2

128@

0.01U_0402_16V7K

1

2

C275

DDR BGA MEMORY

C637

128@

0.01U_0402_16V7K

1

2

128@

0.1U_0402_16V4Z

1

2

C151

C153

128@

1U_0402_6.3V4Z

1

2

128@

0.1U_0402_16V4Z

128@

0.01U_0402_16V7K

1

2

C149

C150

1

2

1

128@

0.01U_0402_16V7K

2

C148

A A

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/03/10 2006/03/10

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

Compal Electronics, Inc.

G72/73VGA Board

LA-2841

1

1.0

of

23 60Thursday, December 15, 2005

5

4

3

2

1

U7

L2

BA0

L3

D D

C C

+1.8VS

R163

VRAM_VREFC VRAM_VREFC

R162
1K_0402_1%

256@

1K_0402_1%

256@

C388

0.047U_0402_16V4Z

256@

Close to U80

FBCA12
FBCA11
FBCA10
FBCA9
FBCA8
FBCA7
FBCA6
FBCA5
FBCA4
FBCA3
FBCA2
FBCA1
FBCA0

CLKC0#
CLKC0

FBC_CKE

FBCCS0#

FBCWE#
FBCRAS#
FBCCAS#

DQMC#1 DQMC#2

ODTC0

DQSC0
DQSC#0

DQSC1
DQSC#1

BA1

R2

A12

P7

A11

M2

A10/AP

P3

A9

P8

A8

P2

A7

N7

A6

N3

A5

N8

A4

N2

A3

M7

A2

M3

A1

M8

A0

K8

CK

J8

CK

K2

CKE

L8

CS

K3

WE

K7

RAS

L7

CAS

F3

LDM

B3

UDM

K9

ODT

F7

LDQS

E8

LDQS

B7

UDQS

A8

UDQS

J2

VREF

A2

NC#A2

E2

NC#E2

L1

NC#L1

R3

NC#R3

R7

NC#R7

R8

NC#R8

HY5PS561621F-25256@

DQ15
DQ14
DQ13
DQ12
DQ11
DQ10

DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0

VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9

VDDQ10

VDD1
VDD2
VDD3
VDD4
VDD5

VDDL

VSSDL

VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8
VSSQ9

VSSQ10

VSS1
VSS2
VSS3
VSS4
VSS5

FBCD13

B9

FBCD10

B1

FBCD11

D9

FBCD14

D1

FBCD15

D3

FBCD12

D7

FBCD9

C2

FBCD8

C8

FBCD4

F9

FBCD1

F1

FBCD7

H9

FBCD0

H1

FBCD3

H3

FBCD6

H7

FBCD2

G2

FBCD5

G8

A9
C1
C3
C7
C9
E9
G1
G3
G7
G9

A1
E1
J9
M9
R1

J1
J7

A7
B2
B8
D2
D8
E7
F2
F8
H2
H8

A3
E3
J3
N1
P9

1

C385

0.1U_0402_16V4Z

2

256@

+1.8VS

C384

1

1U_0402_6.3V4Z

256@

2

C728

0.047U_0402_16V4Z

256@

Close to U81

FBC_BA0FBC_BA0
FBC_BA1FBC_BA1

FBCA12
FBCA11
FBCA10
FBCA9
FBCA8
FBCA7
FBCA6
FBCA5
FBCA4
FBCA3
FBCA2
FBCA1
FBCA0

CLKC0#
CLKC0

FBC_CKE

FBCCS0#

FBCWE#
FBCRAS#
FBCCAS#

DQMC#3DQMC#0

ODTC0

DQSC3
DQSC#3

DQSC2
DQSC#2

(SSTL-1.8) VREF = .5*VDDQ(SSTL-1.8) VREF = .5*VDDQ

U37

L2

BA0

L3

BA1

R2

A12

P7

A11

M2

A10/AP

P3

A9

P8

A8

P2

A7

N7

A6

N3

A5

N8

A4

N2

A3

M7

A2

M3

A1

M8

A0

K8

CK

J8

CK

K2

CKE

L8

CS

K3

WE

K7

RAS

L7

CAS

F3

LDM

B3

UDM

K9

ODT

F7

LDQS

E8

LDQS

B7

UDQS

A8

UDQS

J2

VREF

A2

NC#A2

E2

NC#E2

L1

NC#L1

R3

NC#R3

R7

NC#R7

R8

NC#R8

HY5PS561621F-25256@

DQ15
DQ14
DQ13
DQ12
DQ11
DQ10

VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9

VDDQ10

VDD1
VDD2
VDD3
VDD4
VDD5

VDDL

VSSDL

VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8
VSSQ9

VSSQ10

VSS1
VSS2
VSS3
VSS4
VSS5

DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0

FBCD19

B9

FBCD18

B1

FBCD17

D9

FBCD22

D1

FBCD20

D3

FBCD23

D7

FBCD21

C2

FBCD16

C8

FBCD27

F9

FBCD31

F1

FBCD25

H9

FBCD30

H1

FBCD29

H3

FBCD26

H7

FBCD28

G2

FBCD24

G8

A9
C1
C3
C7
C9
E9
G1
G3
G7
G9

A1
E1
J9
M9
R1

J1
J7

A7
B2
B8
D2
D8
E7
F2
F8
H2
H8

A3
E3
J3
N1
P9

1

C725

0.1U_0402_16V4Z

2

256@

+1.8VS

C726

1

1U_0402_6.3V4Z

256@

2

CLKC0<19>

CLKC0#<19>

R533

481_0402_1%

256@

FBC_BA[1..0]<19,25>

FBCD[63..0]<19,25>

FBCA[12..0]<19,25>

DQSC#[7..0]<19,25>

DQSC[7..0]<19,25>

DQMC#[7..0]<19,25>

ODTC0<19,25>
FBC_CKE<19,25>
FBCRAS#<19,25>
FBCCAS#<19,25>
FBCWE#<19,25>
FBCCS0#<19,25>

Close to U14

1 2

12

R531
120_0402_5%

@

12

R534
120_0402_5%

@

FBC_BA[1..0]

FBCD[63..0]

FBCA[12..0]

DQSC#[7..0]

DQSC[7..0]

DQMC#[7..0]

ODTC0

FBC_CKE
FBCRAS#
FBCCAS#

FBCWE#

FBCCS0#

+1.8VS

1

2

CLKC0

C733

0.1U_0402_16V4Z

@

CLKC0#

For NV73 R533 change to 481_0402_1%(SD00000CA80)

B B

+1.8VS

1

1

C398

256@

1000P_0402_50V7K

A A

5

2

256@

0.01U_0402_16V7K

2

C383

DDR2 BGA MEMORY

C412

256@

0.01U_0402_16V7K

1

2

256@

0.1U_0402_16V4Z

1

2

C411

C413

256@

1U_0402_6.3V4Z

1

2

256@

0.1U_0402_16V4Z

256@

0.1U_0402_16V4Z

1

2

C395

4

C382

1

1

C410

256@

2

0.01U_0402_16V7K

2

+1.8VS

C735

256@

1000P_0402_50V7K

1

2

256@

0.01U_0402_16V7K

1

2

C718

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

DDR BGA MEMORY

C716

256@

0.01U_0402_16V7K

1

2

256@

0.1U_0402_16V4Z

3

C753

C751

256@

1U_0402_6.3V4Z

1

1

2

2

C750

2005/03/10 2006/03/10

256@

0.01U_0402_16V7K

1

1

2

2

C752

256@

0.1U_0402_16V4Z

Compal Secret Data

Deciphered Date

1

256@

0.01U_0402_16V7K

2

C717

2

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

G71/72VGA Board

LA-2841

1

of

24 60Thursday, December 15, 2005

1.0

5

4

3

2

1

FBCD[63..0]

DQSC#[7..0]

DQMC#[7..0]

FBC_BA[1..0]

R168

256@

1 2

Close to U15

FBDA[2..5]

FBCA[12..0]

DQSC[7..0]

ODTC0

FBC_CKE
FBCRAS#
FBCCAS#

FBCWE#

FBCCS0#

12

12

R167
120_0402_5%

@

R169
120_0402_5%

@

+1.8VS

CLKC1

1

C710

0.1U_0402_16V4Z

2

@

CLKC1#

U8

L2

BA0

L3

D D

C C

+1.8VS

VRAM_VREFD

R577

1K_0402_1%

256@

B B

R576
1K_0402_1%

256@

C392

0.047U_0402_16V4Z

256@

Close to U82 Close to U83

C406

256@

1000P_0402_50V7K

+1.8VS

FBCA12
FBCA11
FBCA10
FBCA9
FBCA8
FBCA7
FBCA6
FBDA5
FBDA4
FBDA3
FBDA2
FBCA1
FBCA0

CLKC1#
CLKC1

FBC_CKE

FBCCS0#

FBCWE#
FBCRAS#
FBCCAS#

ODTC0

DQSC4

1

2

256@

0.01U_0402_16V7K

1

2

C407

R2

P7

M2

P3
P8

P2
N7
N3
N8
N2
M7
M3
M8

K8

J8

K2

L8

K3

K7

L7

F3

B3

K9

F7

E8

B7

A8

J2

A2

E2

L1
R3
R7
R8

HY5PS561621F-25256@

DDR2 BGA MEMORY

C409

256@

0.01U_0402_16V7K

1

2

256@

0.1U_0402_16V4Z

BA1
A12

A11
A10/AP
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0

CK
CK

CKE

CS
WE
RAS
CAS
LDM

UDM

ODT

LDQS
LDQS

UDQS
UDQS

VREF
NC#A2

NC#E2
NC#L1
NC#R3
NC#R7
NC#R8

1

2

C402

DQ15
DQ14
DQ13
DQ12
DQ11
DQ10

DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0

VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9

VDDQ10

VDD1
VDD2
VDD3
VDD4
VDD5

VDDL

VSSDL

VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8
VSSQ9

VSSQ10

VSS1
VSS2
VSS3
VSS4
VSS5

C378

256@

1U_0402_6.3V4Z

1

2

FBCD36

B9

FBCD33

B1
D9

FBCD34

D1

FBCD35

D3

FBCD37

D7

FBCD32

C2

FBCD38

C8

FBCD45

F9

FBCD43

F1

FBCD42

H9

FBCD46

H1

FBCD47

H3

FBCD40

H7

FBCD44

G2

FBCD41 FBCD60

G8

A9
C1
C3
C7
C9
E9
G1
G3
G7
G9

A1
E1
J9
M9
R1

J1
J7

A7
B2
B8
D2
D8
E7
F2
F8
H2
H8

A3
E3
J3
N1
P9

256@

0.1U_0402_16V4Z

1

2

C374

256@

0.1U_0402_16V4Z

1

C386

0.1U_0402_16V4Z

2

256@

C403

1

2

+1.8VS

1

256@

0.01U_0402_16V7K

2

C405

C390

1

1U_0402_6.3V4Z

256@

2

VRAM_VREFD

C724

0.047U_0402_16V4Z

256@

256@

1000P_0402_50V7K

FBC_BA0FBC_BA0
FBC_BA1FBC_BA1

FBCA12
FBCA11
FBCA10
FBCA9
FBCA8
FBCA7
FBCA6
FBDA5
FBDA4
FBDA3
FBDA2
FBCA1
FBCA0

CLKC1#
CLKC1

FBC_CKE

FBCCS0#

FBCWE#
FBCRAS#
FBCCAS#

DQMC#7DQMC#5
DQMC#6DQMC#4

ODTC0

DQSC7DQSC5
DQSC#7DQSC#5

DQSC6
DQSC#6DQSC#4

(SSTL-1.8) VREF = .5*VDDQ(SSTL-1.8) VREF = .5*VDDQ

+1.8VS

1

C745

2

U36

L2
L3

R2
P7

M2

P3
P8
P2
N7
N3
N8
N2

M7
M3
M8

K8

J8

K2

L8
K3
K7
L7
F3

B3

K9

F7
E8

B7
A8

J2

A2
E2
L1
R3
R7
R8

HY5PS561621F-25256@

256@

0.01U_0402_16V7K

1

2

C744

256@

0.01U_0402_16V7K

BA0
BA1

A12
A11
A10/AP
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0

CK
CK

CKE

CS
WE
RAS
CAS
LDM

UDM

ODT

LDQS
LDQS

UDQS
UDQS

VREF
NC#A2

NC#E2
NC#L1
NC#R3
NC#R7
NC#R8

DQ15
DQ14
DQ13
DQ12
DQ11
DQ10

VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9

VDDQ10

VDD1
VDD2
VDD3
VDD4
VDD5

VDDL

VSSDL

VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8
VSSQ9

VSSQ10

VSS1
VSS2
VSS3
VSS4
VSS5

DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0

DDR2 BGA MEMORY

C748

1

1

2

2

C747

256@

0.1U_0402_16V4Z

B9
B1
D9
D1
D3
D7
C2
C8
F9
F1
H9
H1
H3
H7
G2
G8

A9
C1
C3
C7
C9
E9
G1
G3
G7
G9

A1
E1
J9
M9
R1

J1
J7

A7
B2
B8
D2
D8
E7
F2
F8
H2
H8

A3
E3
J3
N1
P9

C749

256@

1U_0402_6.3V4Z

1

2

256@

0.1U_0402_16V4Z

FBCD54
FBCD49
FBCD52FBCD39
FBCD48
FBCD51
FBCD53
FBCD50
FBCD55
FBCD62
FBCD56
FBCD61
FBCD57
FBCD58
FBCD63
FBCD59

1

2

1

2

C746

+1.8VS

C722

0.1U_0402_16V4Z

256@

C713

256@

0.01U_0402_16V7K

1

2

1

2

1

256@

0.01U_0402_16V7K

2

FBDA[2..5]<19>

FBCD[63..0]<19,24>

FBCA[12..0]<19,24>

DQSC#[7..0]<19,24>

DQSC[7..0]<19,24>

DQMC#[7..0]<19,24>

FBC_BA[1..0]<19,24>

ODTC0<19,24>
FBC_CKE<19,24>
FBCRAS#<19,24>
FBCCAS#<19,24>
FBCWE#<19,24>
FBCCS0#<19,24>

C719
1U_0402_6.3V4Z

256@

CLKC1<19>

481_0402_1%

CLKC1#<19>

For NV73 R168 change to 481_0402_1%(SD00000CA80)

C404

A A

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/03/10 2006/03/10

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

Compal Electronics, Inc.

G71/72VGA Board

LA-2841

1

1.0

of

25 60Thursday, December 15, 2005

5

4

3

2

1

STRAPS PIN DESCRIPTION

+3VS

CRYSTAL[1:0] 10

ROM_TYPE[1:0]

D D

CRYSTAL_1<18>

CRYSTAL_0<18>

CRYSTAL_1

CRYSTAL_0

1 2

R78 2K_0402_5%@

1 2

R468 2K_0402_5%@

SUB_VENDOR

PEX_PLL_TERM MIOAD0

PEX_CFG[2:0]

MIOBD[6,2]
MIOBD

[11:10]

MIOAD1

MIOAD
[9,8,6]

RAM_CFG[3:0]

27MHz=10, 14.318MHz=01, 13.5MHz=00
Parallel=00, SERIAL M25P10=01,

Serial SST45VF=10
VBIOS on card (pull high)

VBIOS with system BIOS (pull down)

Overridden

16Mx16 (1.8V or 2.5V)Hynix X 4pcs
16Mx16 (1.8V or 2.5V)Infineon X 4pcs 0010

Value

01

0

0

001

0011

16Mx16 (1.8V or 2.5V)Samsung X 4pcs 0001
16Mx16 (1.8V or 2.5V)Hynix X 8pcs
16Mx16 (1.8V or 2.5V)Infineon X 8pcs
16Mx16 (1.8V or 2.5V)Samsung X 8pcs

A01

PCI_DEVID[3:0]

+3VS

C C

RAM_CFG0<18>
RAM_CFG1<18>
RAM_CFG2<18>
RAM_CFG3<18>
PCI_DEVID0<18>
PCI_DEVID1<18>
PCI_DEVID2<18>
PCI_DEVID3<18>
PEX_CFG0<18>
PEX_CFG1<18>

PEX_CFG2<18>
PEX_PLL_TERM<18>
MOBILE_MODE<18>

SUB_VENDOR<18>

RAM_CFG0
RAM_CFG1
RAM_CFG2
RAM_CFG3
PCI_DEVID0
PCI_DEVID1
PCI_DEVID2
PCI_DEVID3
PEX_CFG0
PEX_CFG1
PEX_CFG2
PEX_PLL_TERM
MOBILE_MODE
SUB_VENDOR

R73

128@

2K_0402_5%

2K_0402_5%@

R72

12

R472

128@

2K_0402_5%

12

R473

12

R60
2K_0402_5%@

R59

12

128@

2K_0402_5%

12

12

R64
2K_0402_5%@

R63

12

R474

2K_0402_5%@

R475

12

@

2K_0402_5%

12

R476

12

R477

2K_0402_5%@

12

R469

2K_0402_5%@

R470

12

@

2K_0402_5%

12

R67

128@

2K_0402_5%

12

R66

12

R108

128@

2K_0402_5%

R107

12

@

2K_0402_5%

12

R112

@

2K_0402_5%

12

R111

12

R118

2K_0402_5%@

R117

12

@

2K_0402_5%

12

12

R493

2K_0402_5%@

12

12

@

2K_0402_5%

R494

12

12

R497

2K_0402_5%@

R84
2K_0402_5%@

R83

12

12

R498

VIPD[5:3]

MIOA_HSYNC

NV72M
NV73M

1011
1010
1001

1000
1000

2K_0402_5%@

B B

C376

128@

0.1U_0402_16V4Z

128@

2K_0402_5%

+3VS

1

2

2K_0402_5%@

Spread spectrum

U3

7

REF

VDD

1

MODOUT

XIN

8

XOUT

NC

2

PD#

VSS

ASM3P1819N-SR_SO8

128@

2K_0402_5%@

5

R133 22_0402_5%128@

4

1 2

R134 10K_0402_5%@

3

R148 10K_0402_5%@

6

OSC_SPREAD <18>OSC_OUT<18>

128@

2K_0402_5%

2K_0402_5%@

12
12

128@

2K_0402_5%

EMI request 6/7

A A

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/03/01 2006/03/01

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

G71/72 VGA Board

Size Document Number Rev

Custom

LA-2841

Thursday, D ecember 15, 2005

2

Date: Sheet

26 60

1

1.0

of

5

4

3

2

1

D D

C C

B B

+3VS

R179 8.2K_0402_5%

1 2

R529 8.2K_0402_5%

1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2

1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2

R528 8.2K_0402_5%
R530 8.2K_0402_5%
R526 8.2K_0402_5%
R540 8.2K_0402_5%
R538 8.2K_0402_5%
R213 8.2K_0402_5%
R178 8.2K_0402_5%
R527 8.2K_0402_5%

+3VS

R195 8.2K_0402_5%
R196 8.2K_0402_5%
R194 8.2K_0402_5%
R193 8.2K_0402_5%
R197 8.2K_0402_5%
R524 8.2K_0402_5%
R525 8.2K_0402_5%
R198 8.2K_0402_5%
R192 8.2K_0402_5%
R211 8.2K_0402_5%
R210 8.2K_0402_5%
R212 8.2K_0402_5%

PCI_DEVSEL#
PCI_STOP#
PCI_TRDY#
PCI_FRAME#
PCI_PLOCK#
PCI_IRDY#
PCI_SERR#
PCI_PERR#
PCI_REQ4#
PCI_REQ3#

PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#
PCI_PIRQE#
PCI_PIRQF#
PCI_PIRQG#
PCI_PIRQH#
PCI_REQ0#
PCI_REQ1#
PCI_REQ2#
PCI_REQ5#

PCI_AD[0..31]<32,36>

PCI_PIRQD#<32>

PCI_AD0
PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD6
PCI_AD7
PCI_AD8
PCI_AD9
PCI_AD10
PCI_AD11
PCI_AD12
PCI_AD13
PCI_AD14
PCI_AD15
PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20
PCI_AD21
PCI_AD22
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30
PCI_AD31

PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#

U6B

E18

AD0

C18

AD1

A16

AD2

F18

AD3

E16

AD4

A18

AD5

E17

AD6

A17

AD7

A15

AD8

C14

AD9

E14

AD10

D14

AD11

B12

AD12

C13

AD13

G15

AD14

G13

AD15

E12

AD16

C11

AD17

D11

AD18

A11

AD19

A10

AD20

F11

AD21

F10

AD22

E9

AD23

D9

AD24

B9

AD25

A8

AD26

A6

AD27

C7

AD28

B6

AD29

E6

AD30

D6

AD31

Interrupt I/F

A3

PIRQA#

B4

PIRQB#

C5

PIRQC#

B5

PIRQD#

AE5

RSVD[1]

AD5

RSVD[2]

AG4

RSVD[3]

AH4

RSVD[4]

AD9

RSVD[5]

ICH7_BGA652~D

PCI

REQ4# / GPIO22
GNT4# / GPIO48

GPIO1 / REQ5#

GPIO17 / GNT5#

GPIO2 / PIRQE#
GPIO3 / PIRQF#
GPIO4 / PIRQG#
GPIO5 / PIRQH#

MISC

MCH_SYNC#

REQ0#
GNT0#
REQ1#
GNT1#
REQ2#
GNT2#
REQ3#
GNT3#

C/BE0#
C/BE1#
C/BE2#
C/BE3#

IRDY#

PAR

PCIRST#

DEVSEL#

PERR#

PLOCK#

SERR#
STOP#
TRDY#

FRAME#

PLTRST#

PCICLK

PME#

RSVD[6]
RSVD[7]
RSVD[8]
RSVD[9]

D7
E7
C16
D16
C17
D17
E13
F13
A13
A14
C8
D8

B15
C12
D12
C15

A7
E10
B18
A12
C9
E11
B10
F15
F14
F16

C26
A9
B19

G8
F7
F8
G7

AE9
AG8
AH8
F21
AH20

PCI_REQ0#
PCI_REQ1#
PCI_REQ2#

PCI_GNT2#
PCI_REQ3#

PCI_REQ4#
PCI_REQ5#

PCI_CBE#0
PCI_CBE#1
PCI_CBE#2
PCI_CBE#3

PCI_IRDY#
PCI_PAR
PCI_PCIRST#
PCI_DEVSEL#
PCI_PERR#
PCI_PLOCK#
PCI_SERR#
PCI_STOP#
PCI_TRDY#
PCI_FRAME#

PCI_PLTRST#
CLK_PCI_ICH
PCI_PME#

PCI_PIRQE#
PCI_PIRQF#
PCI_PIRQG#
PCI_PIRQH#

PCI_REQ2# <32>
PCI_GNT2# <32>

PCI_CBE#0 <32,36>
PCI_CBE#1 <32,36>
PCI_CBE#2 <32,36>
PCI_CBE#3 <32,36>

PCI_IRDY# <32>
PCI_PAR <32>

PCI_DEVSEL# <32>
PCI_PERR# <32>

PCI_SERR# <32>
PCI_STOP# <32>
PCI_TRDY# <32,36>
PCI_FRAME# <32,36>

CLK_PCI_ICH <15>
PCI_PME# <32,44>

PCI_PIRQE# <32>
PCI_PIRQG# <32>PCI_PIRQC#<32>

MCH_ICH_SYNC# <7>

PCI_PCIRST#

PCI_PLTRST#

+3VS

5

U10

1

P

B

Y

2

A

G

TC7SH08FU_SSOP5@
R186
0_0402_5%

R185
0_0402_5%

3

12

+3VS

5

U11

1

P

B

Y

2

A

G

TC7SH08FU_SSOP5@

3

12

Place closely pin A9

CLK_PCI_ICH

R176

10_0402_5% @

1 2
1

C415

8.2P_0402_50V@

2

4

4

PCI_RST#

PLT_RST#

PCI_RST# <32,33,36,42,44>

R203

12

0_0402_5%

VGA_RST# <18>

PLT_RST# <7,31,32,34,37>

A A

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/03/10 2006/03/10

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

2

Date: Sheet

Compal Electronics, Inc.

ICH7-M(1/4)

LA-2841

27 60Thursday, December 15, 2005

1

1.0

of

5

C370

18P_0402_50V8J

32.768KHZ_12.5P_1TJS125BJ4A421P

C356

18P_0402_50V8J

D D

0.1U_0402_16V4Z@

C C

+RTCVCC

12

R516
1M_0402_5%

SM_INTRUDER#

+RTCVCC

12

R519
332K_0402_1%

B B

A A

ICH_INTVRMEN

47K_0402_5%@

EC_RTCRESET<44>

+RTCVCC

C828

R608

R517
20K_0402_5%

CLRP1

SHORT PADS

1U_0603_10V4Z

1 2

EC_RTCRESET

+3VS

PSATA_ITX_DRX_N0<31>

PSATA_ITX_DRX_P0<31>

SSATA_ITX_DRX_N0<31>

SSATA_ITX_DRX_P0<31>

1 2

1 2

C707

1 2

Q52

2N7002_SOT23@

S

G

12

0.1U_0402_16V4Z

D

13

2

4

12

Y1

2

NC

3

OUT

NC

12

+3VALW

1

C372

2

R1264.7K_0402_5%

12

R1258.2K_0402_5%

12

PSATA_ITX_DRX_N0

PSATA_ITX_DRX_P0

SSATA_ITX_DRX_N0

SSATA_ITX_DRX_P0

ICH_RTCX1

1

IN

4

ICH_RTCX2

U4

8

VCC

7

NC

6

NC

5

GND

AT93C46-10SI-2.7_SO8

LAN_TXD0<35>
LAN_TXD1<35>
LAN_TXD2<35>

ACZ_BITCLK<38>

ACZ_SYNC<38>

ACZ_RST#<38,44>

ACZ_SDIN0<38>

ACZ_SDOUT<38>

IDE_LED#<43>

PSATA_IRX_DTX_N0_C<31>
PSATA_IRX_DTX_P0_C<31>

SSATA_IRX_DTX_N0_C<31>
SSATA_IRX_DTX_P0_C<31>

CLK_PCIE_SATA#<15>
CLK_PCIE_SATA<15>

PD_IORDY
PD_IRQ

1 2

C353 3900P_0402_50V7K

1 2

C351 3900P_0402_50V7K

1 2

C348 3900P_0402_50V7K

1 2

C341 3900P_0402_50V7K

close ICH7

12

R144

10M_0402_5%

1

CS

2

SK

3

DI

4

DO

LAN_RSTSYNC<35>

LAN_RXD0<35>
LAN_RXD1<35>
LAN_RXD2<35>

C381 10P_0402_25V8K@

33_0402_5%

PD_IORDY<31>

PD_IRQ<31>

PD_DACK#<31>

PD_IOW#<31>
PD_IOR#<31>

PSATA_ITX_DRX_N0_C

PSATA_ITX_DRX_P0_C

SSATA_ITX_DRX_N0_C

SSATA_ITX_DRX_P0_C

EEP_CS
EEP_SK
EEP_DOUT
EEP_DIN

LAN_JCLK<35>

ACZ_BITCLK
ACZ_SYNC

ACZ_SDIN0

ACZ_SDOUT

IDE_LED#

ICH_RTCRST#
ICH_INTVRMEN

SM_INTRUDER#

LAN_RSTSYNC
LAN_RXD0

LAN_RXD1
LAN_RXD2

LAN_TXD0
LAN_TXD1
LAN_TXD2

R150

1 2

12

10_0402_5%@

R155

1 2

PSATA_IRX_DTX_N0_C
PSATA_IRX_DTX_P0_C
PSATA_ITX_DRX_N0_C
PSATA_ITX_DRX_P0_C

SSATA_IRX_DTX_N0_C
SSATA_IRX_DTX_P0_C
SSATA_ITX_DRX_N0_C
SSATA_ITX_DRX_P0_C

CLK_PCIE_SATA#
CLK_PCIE_SATA

R127

1 2

24.9_0402_1%

PD_IORDY
PD_IRQ
PD_DACK#
PD_IOW#
PD_IOR#

LAN_JCLK

ACZRST#

AF18

AG2

AG6

AH10
AG10

AG16
AH16
AF16
AH15
AF15

AB1
AB2

AA3

W4

Y5

W1

Y1
Y2

W3

V3
U3
U5

V4

T5
U7

V6

V7

U1
R6

R5

T2

T3

T1

T4

AF3
AE3

AH2
AF7

AE7
AH6
AF1

AE1

3

U6A

RTXC1
RTCX2

RTCRST#
INTVRMEN

INTRUDER#

EE_CS
EE_SHCLK
EE_DOUT
EE_DIN

LAN_CLK
LAN_RSTSYNC
LAN_RXD0

LAN_RXD1
LAN_RXD2

LAN_TXD0
LAN_TXD1
LAN_TXD2

ACZ_BCLK
ACZ_SYNC

ACZ_RST#
ACZ_SDIN0

ACZ_SDIN1
ACZ_SDIN2

ACZ_SDOUT

SATALED#

SATA0RXN
SATA0RXP
SATA0TXN
SATA0TXP

SATA2RXN
SATA2RXP
SATA2TXN
SATA2TXP

SATA_CLKN
SATA_CLKP

SATARBIASN
SATARBIASP

IORDY
IDEIRQ
DDACK#
DIOW#
DIOR#

ICH7_BGA652~D

RTC

LAD0
LAD1
LAD2
LAD3

LDRQ0#

LPCCPU

LDRQ1# / GPIO23

LFRAME#

LAN

A20GATE

A20M#

CPUSLP#

TP1 / DPRSTP#

TP2 / DPSLP#

FERR#

GPIO49 / CPUPWRGD

IGNNE#

INIT3_3V#

INIT#

INTR

AC-97/AZALIA

RCIN#

SMI#

STPCLK#

THERMTRIP#

DCS1#
DCS3#

SATA

DD10
DD11
DD12
DD13

IDE

DD14
DD15

DDREQ

+RTCVCC

2

1

AA6
AB5
AC4
Y6

AC3
AA5

AB3

AE22
AH28

AG27
AF24

AH25
AG26
AG24
AG22

AG21
AF22
AF25

AG23
AF23

AH24

NMI

AH22
AF26

AH17

DA0

AE17

DA1

AF17

DA2

AE16
AD16

AB15

DD0

AE14

DD1

AG13

DD2

AF13

DD3

AD14

DD4

AC13

DD5

AD12

DD6

AC12

DD7

AE12

DD8

AF12

DD9

AB13
AC14
AF14
AH13
AH14
AC15

AE15

DAN202U_SC70

C679
1U_0603_10V4Z

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3

LPC_DRQ0#

LPC_FRAME#

GATEA20
H_A20M#

H_CPUSLP_R#
DPRSLP#

H_DPSLP#
H_FERR#
H_PWRGOOD
H_IGNNE#
H_INIT#

H_INTR

KB_RST#
H_SMI#

H_NMI
H_STPCLK#
THRMTRIP_ICH#

PD_A0
PD_A1
PD_A2

PD_CS#1
PD_CS#3

PD_D0
PD_D1
PD_D2
PD_D3
PD_D4
PD_D5
PD_D6
PD_D7
PD_D8
PD_D9
PD_D10
PD_D11
PD_D12
PD_D13
PD_D14
PD_D15

PD_DREQ

PD_D[0..15]

D26

1

LDO3

2

R488

3

1 2

1K_0402_5%

LPC_AD[0..3] <42,44>

LPC_DRQ#0 <42>

LPC_FRAME# <42,44>

R122 10K_0402_5%

12

GATEA20 <44>
H_A20M# <4>

T23

PAD

R121 0_0402_5%

12

H_DPSLP# <4>

12

H_FERR# <4>
H_PWRGOOD <4>
H_IGNNE# <4>
H_INIT# <4>

H_INTR <4>

R508 10K_0402_5%

12

KB_RST# <44>
H_SMI# <4>

H_NMI <4>
H_STPCLK# <4>

R120

1 2

24.9_0402_1%

PD_A0 <31>
PD_A1 <31>
PD_A2 <31>

PD_CS#1 <31>
PD_CS#3 <31>

PD_DREQ <31>

PD_D[0..15] <31>

BATT1.1

W=20mils

2

+3VS

1

H_DPRSTP# <4,53>

+VCCP

+3VS

JP23

+

56_0402_5%
R114

+-

SUYIN_060003FA002TX00NL~D

+VCCP

-

12

R119
56_0402_5%

2

1

H_THERMTRIP# <4,7>

BATT1

CR2032 RTC BATTERY

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/03/10 2006/03/10

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

Compal Electronics, Inc.

ICH7-M(2/4)

LA-2841

1

1.0

of

28 60Thursday, December 15, 2005

5

+3VS

10K_0402_5%

1 2

8.2K_0402_5%

1 2

10K_0402_5%

1 2

150_0402_5%

1 2

10K_0402_5%

1 2

10K_0402_5%

1 2

10K_0402_5%

1 2

10K_0402_5%

1 2

1K_0402_5%

1 2

8.2K_0402_5%
10K_0402_5%

1 2

10K_0402_5%

1 2

10K_0402_5%

1 2

SIRQ

PCI_CLKRUN#

LINKALERT#

ITP_DBRESET#

OCP#

SPI_MISO

SPI_CS#

BT_DET#

ICH_PCIE_W AKE#

ICH_LOW_BAT#

12

WL_ON

SPI_MOSI

PCBEEP

R208

10K_0402_5%

R207
10K_0402_5%

1 2

1 2

R123

R124

D D

+3VALW

R173

R221

R219

R156

R159

R223

R182

R209

C C

R153

R578

R590

4

3

2

1

Place closely pin B2 Place closely pin AC1

CLK_14M_ICH

12

R136

10_0402_5%@

1

C350

4.7P_0402_50V8C@

2

12

R509

100K_0402_5%@

+3VALW+3VALW

12

12

R222

R220

SB_SPKR<38>

H_STP_PCI#<15>

EC_SMI#<44>

2.2K_0402_5%

R172

1 2

8.2K_0402_5%

T25PAD

OCP#<4>

SIRQ<32,42,44>

VGATE<44,53>

ICH_SMBCLK
ICH_SMBDATA
LINKALERT#
ICH_SMLINK0
ICH_SMLINK1

ICH_RI#
SB_SPKR

SUS_STAT#
ITP_DBRESET#

PM_BMBUSY#
OCP#
H_STP_PCI#

H_STP_CPU#

EC_FLASH#
PCI_CLKRUN#

ICH_PCIE_W AKE#

SIRQ
EC_THERM#

VGATE

EC_SMI#

2.2K_0402_5%

ICH_SMBCLK<15,34,37>

ICH_SMBDATA<15,34,37>

+3VALW

ITP_DBRESET#<4>

PM_BMBUSY#<7>

H_STP_CPU#<15>

EC_FLASH#<45>

PCI_CLKRUN#<32>

ICH_PCIE_W AKE#<34,37>

EC_THERM#<44>

U6C

C22

SMBCLK

B22

SMBDATA

A26

LINKALERT#

B25

SMLINK0

A25

SMLINK1

A28

RI#

A19

SPKR

A27

SUS_STAT#

A22

SYS_RST#

AB18

GPIO0 / BM_BUSY#

B23

GPIO11 / SMBALERT#

AC20

GPIO18 / STPPCI#

AF21

GPIO20 / STPCPU#

A21

GPIO26

B21

GPIO27

E23

GPIO28

AG18

GPIO32 / CLKRUN#

AC19

GPIO33 / AZ_DOCK_EN#

U2

GPIO34 / AZ_DOCK_RST#

F20

WAKE#

AH21

SERIRQ

AF20

THRM#

AD22

VRMPWRGD

AC21

GPIO6

AC18

GPIO7

E21

GPIO8

ICH7_BGA652~D

GPIO21 / SATA0GP

SMB

GPIO19 / SATA1GP
GPIO36 / SATA2GP
GPIO37 / SATA3GP

SATA

GPIO

SYS

Clocks

GPIO

GPIO16 / DPRSLPVR

TP0 / BATLOW#

POWER MGT

GPIO

GPIO35 / SATAREQ#

Need update symbol

CLK14
CLK48

SUSCLK
SLP_S3#

SLP_S4#
SLP_S5#

PWROK

PWRBTN#

LAN_RST#

RSMRST#

GPIO9
GPIO10
GPIO12
GPIO13
GPIO14
GPIO15
GPIO24
GPIO25

GPIO38
GPIO39

AF19
AH18
AH19
AE19

AC1
B2

C20
B24

D23
F22

AA4
AC22
C21
C23
C19
Y4

E20
A20
F19
E19
R4
E22
R3
D20
AD21
AD20
AE20

1 2

100_0402_5%

CLK_14M_ICH
CLK_48M_ICH

ICH_SUSCLK

SLP_S3#
SLP_S4#
SLP_S5#

ICH_POK
DPRSLPVR
ICH_LOW_BAT#
PWRBTN_OUT#
LAN_RST#
EC_RSMRST#

R514 10K_0402_5%

1 2

EC_SCI#
BT_DET#
PCBEEP
LID_OUT#

CPUSB#
WL_ON
BT_ON#

R507

CLK_14M_ICH <15>
CLK_48M_ICH <15>

T28 PAD

SLP_S3# <44>
SLP_S4# <44>
SLP_S5# <44>

ICH_POK <7,44>

1 2

DPRSLPVR <7,53>

PWRBTN_OUT# <44>

LAN_RST# <44>

EC_RSMRST# <44>

EC_SCI# <44>
BT_DET# <41>
PCBEEP <40>
LID_OUT# <44>

CPUSB# <34,44>
WL_ON <37>
BT_ON# <41>

12

R539

1

C740

2

R511
10K_0402_5%

CLK_48M_ICH

10_0402_5%@

4.7P_0402_50V8C@

DPRSLPVR

PCIE_RXN1<34>
PCIE_RXP1<34>
PCIE_TXN1<34>

PCIE_TXP1<34>

PCIE_RXN2<34>
PCIE_RXP2<34>
PCIE_TXN2<34>

PCIE_TXP2<34>

PCIE_RXN3<37>
PCIE_RXP3<37>
PCIE_TXN3<37>

PCIE_TXP3<37>

B B

A A

USB_OC#0<41>

USB_OC#3<41>
USB_OC#4<42>
USB_OC#5<42>

PCIE_RXN1
PCIE_RXP1
PCIE_C_TXN1

C3990.1U_0402_16V4Z

12

PCIE_C_TXP1

C3960.1U_0402_16V4Z

12

PCIE_RXN2
PCIE_RXP2
PCIE_C_TXN2

C3910.1U_0402_16V4Z

12

PCIE_C_TXP2

C3930.1U_0402_16V4Z

12

PCIE_RXN3
PCIE_RXP3
PCIE_C_TXN3

C3890.1U_0402_16V4Z

12

PCIE_C_TXP3

C3870.1U_0402_16V4Z

12

SPI_CS#

SPI_MOSI
SPI_MISO

USB_OC#0
USB_OC#1
USB_OC#2
USB_OC#3
USB_OC#4
USB_OC#5
USB_OC#6
USB_OC#7

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

U6D

F26
F25
E28
E27

H26
H25
G28
G27

K26
K25
J28
J27

M26
M25

L28
L27

P26
P25
N28
N27

T25
T24
R28
R27

R2

P6
P1

P5
P2

D3
C4
D5
D4

E5

C3

A2
B3

ICH7_BGA652~D

3

PCI-EXPRESS

SPI

USB

DMI0RXN
DMI0RXP
DMI0TXN

DMI0TXP

DMI1RXN
DMI1RXP
DMI1TXN

DMI1TXP

DMI2RXN
DMI2RXP
DMI2TXN

DMI2TXP

DMI3RXN
DMI3RXP
DMI3TXN

DMI3TXP

DMI_CLKN
DMI_CLKP

DIRECT MEDIA INTERFACE

DMI_ZCOMP

DMI_IRCOMP

USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4N
USBP4P
USBP5N
USBP5P
USBP6N
USBP6P
USBP7N
USBP7P

USBRBIAS#

USBRBIAS

Compal Secret Data

PERn1
PERp1
PETn1
PETp1

PERn2
PERp2
PETn2
PETp2

PERn3
PERp3
PETn3
PETp3

PERn4
PERp4
PETn4
PETp4

PERn5
PERp5
PETn5
PETp5

PERn6
PERp6
PETn6
PETp6

SPI_CLK
SPI_CS#
SPI_ARB

SPI_MOSI
SPI_MISO

OC0#
OC1#
OC2#
OC3#
OC4#
OC5# / GPIO29
OC6# / GPIO30
OC7# / GPIO31

2005/03/10 2006/03/10

V26
V25
U28
U27

Y26
Y25
W28
W27

AB26
AB25
AA28
AA27

AD25
AD24
AC28
AC27

AE28
AE27

C25
D25

F1
F2
G4
G3
H1
H2
J4
J3
K1
K2
L4
L5
M1
M2
N4
N3

D2
D1

Deciphered Date

DMI_RXN0
DMI_RXP0
DMI_TXN0
DMI_TXP0

DMI_RXN1
DMI_RXP1
DMI_TXN1
DMI_TXP1

DMI_RXN2
DMI_RXP2
DMI_TXN2
DMI_TXP2

DMI_RXN3
DMI_RXP3
DMI_TXN3
DMI_TXP3

CLK_PCIE_ICH#
CLK_PCIE_ICH

DMI_IRCOMP
USB20_N0

USB20_P0
USB20_N1
USB20_P1

USB20_N3
USB20_P3
USB20_N4
USB20_P4
USB20_N5
USB20_P5
USB20_N6
USB20_P6
USB20_N7
USB20_P7

USBRBIAS

DMI_RXN0 <7>
DMI_RXP0 <7>
DMI_TXN0 <7>
DMI_TXP0 <7>

DMI_RXN1 <7>
DMI_RXP1 <7>
DMI_TXN1 <7>
DMI_TXP1 <7>

DMI_RXN2 <7>
DMI_RXP2 <7>
DMI_TXN2 <7>
DMI_TXP2 <7>

DMI_RXN3 <7>
DMI_RXP3 <7>
DMI_TXN3 <7>
DMI_TXP3 <7>

CLK_PCIE_ICH# <15>
CLK_PCIE_ICH <15>

R166 24.9_0402_1%

1 2

USB20_N0 <41>
USB20_P0 <41>
USB20_N1 <46>
USB20_P1 <46>

USB20_N3 <41>
USB20_P3 <41>
USB20_N4 <42>
USB20_P4 <42>
USB20_N5 <42>
USB20_P5 <42>
USB20_N6 <41>
USB20_P6 <41>
USB20_N7 <34>
USB20_P7 <34>

R165 22.6_0402_1%

1 2

Within 500 mils

2

Within 500 mils

+1.5VS

Title

Size Document Number Rev

Custom

Date: Sheet

USB_OC#7
USB_OC#1
USB_OC#2
USB_OC#4

USB_OC#6

RP20

4 5
3 6
2 7
1 8

10K_1206_8P4R_5%

R175
10K_0402_5%

1 2

Compal Electronics, Inc.

ICH7-M(3/4)

LA-2841

1

+3VALW

29 60Thursday, December 15, 2005

1.0

of

5

4

3

2

1

ICH_V5REF_RUN

+1.5VS

D D

100_0402_5%

10_0402_5%

C C

B B

A A

R518

R164

12

12

+3VS+5VS

21

1

2

+3VALW+5VALW

21

1

2

D18
CH751H-40_SC76

ICH_V5REF_RUN

C697

0.1U_0402_16V4Z

D8
CH751H-40_SC76

ICH_V5REF_SUS

C732

0.1U_0402_16V4Z

+1.5VS

1

C729

0.1U_0402_16V4Z

2

Place closely pin AG28 within 100mlis.

R109

1 2

0.5_0805_1%

0.1U_0402_16V4Z

+1.5VS_DMIPLLR

+1.5VS

+3VALW

C734

1 2

0_0805_5%

1

C698

2

1

2

R129

+3VS

0.1U_0402_16V4Z

+1.5VS

0.1U_0402_16V4Z

C349

1

+

C693

2

+1.5VS_DMIPLL

1

C352

2

10U_0805_10V4Z

1

2

C742

1

C714

2

220U_D2_4VM

0.1U_0402_16V4Z

Place closely pin
D28,T28,AD28.

1

2

0.01U_0402_16V7K

Place closely pin AG5.

C688

0.1U_0402_16V4Z

Place closely pin AG9.

1

2

0.1U_0402_16V4Z

1

C715

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

+1.5VS

C691

0.1U_0402_16V4Z

+1.5VS

C696

1U_0603_10V4Z

T30 PAD
T31 PAD

+3VALW

ICH_V5REF_SUS

1

C739

2

+3VS

1

C743

2

+1.5VS_DMIPLL

1

2

1

2

ICH_AA2
ICH_Y7

G10

AD17

F6

AA22
AA23
AB22
AB23
AC23
AC24
AC25
AC26
AD26
AD27
AD28

D26
D27
D28
E24
E25
E26
F23
F24
G22
G23
H22
H23

J22

J23
K22
K23

L22

L23
M22
M23
N22
N23
P22
P23
R22
R23
R24
R25
R26
T22
T23
T26
T27
T28
U22
U23
V22
V23

W22
W23

Y22
Y23

B27

AG28

AB7
AC6
AC7
AD6
AE6
AF5
AF6

AG5

AH5
AD2

AH11
AB10

AB9

AC10
AD10
AE10
AF10

AF9

AG9

AH9

E3

C1

AA2

Y7
V5

V1
W2
W7

1

C375

0.1U_0402_16V4Z

2

U6F

V5REF[1]
V5REF[2]
V5REF_Sus
Vcc1_5_B[1]

Vcc1_5_B[2]
Vcc1_5_B[3]
Vcc1_5_B[4]
Vcc1_5_B[5]
Vcc1_5_B[6]
Vcc1_5_B[7]
Vcc1_5_B[8]
Vcc1_5_B[9]
Vcc1_5_B[10]
Vcc1_5_B[11]
Vcc1_5_B[12]
Vcc1_5_B[13]
Vcc1_5_B[14]
Vcc1_5_B[15]
Vcc1_5_B[16]
Vcc1_5_B[17]
Vcc1_5_B[18]
Vcc1_5_B[19]
Vcc1_5_B[20]
Vcc1_5_B[21]
Vcc1_5_B[22]
Vcc1_5_B[23]
Vcc1_5_B[24]
Vcc1_5_B[25]
Vcc1_5_B[26]
Vcc1_5_B[27]
Vcc1_5_B[28]
Vcc1_5_B[29]
Vcc1_5_B[30]
Vcc1_5_B[31]
Vcc1_5_B[32]
Vcc1_5_B[33]
Vcc1_5_B[34]
Vcc1_5_B[35]
Vcc1_5_B[36]
Vcc1_5_B[37]
Vcc1_5_B[38]
Vcc1_5_B[39]
Vcc1_5_B[40]
Vcc1_5_B[41]
Vcc1_5_B[42]
Vcc1_5_B[43]
Vcc1_5_B[44]
Vcc1_5_B[45]
Vcc1_5_B[46]
Vcc1_5_B[47]
Vcc1_5_B[48]
Vcc1_5_B[49]
Vcc1_5_B[50]
Vcc1_5_B[51]
Vcc1_5_B[52]
Vcc1_5_B[53]

Vcc3_3[1]
VccDMIPLL
Vcc1_5_A[1]

Vcc1_5_A[2]
Vcc1_5_A[3]
Vcc1_5_A[4]
Vcc1_5_A[5]
Vcc1_5_A[6]
Vcc1_5_A[7]
Vcc1_5_A[8]
Vcc1_5_A[9]

VccSATAPLL
Vcc3_3[2]
Vcc1_5_A[10]

Vcc1_5_A[11]
Vcc1_5_A[12]
Vcc1_5_A[13]
Vcc1_5_A[14]
Vcc1_5_A[15]
Vcc1_5_A[16]
Vcc1_5_A[17]
Vcc1_5_A[18]

VccSus3_3[19]
VccUSBPLL
VccSus1_05/VccLAN1_05[1]

VccSus1_05/VccLAN1_05[2]
VccSus3_3/VccLAN3_3[1]

VccSus3_3/VccLAN3_3[2]
VccSus3_3/VccLAN3_3[3]
VccSus3_3/VccLAN3_3[4]

ICH7_BGA652~D

Vcc1_05[1]
Vcc1_05[2]
Vcc1_05[3]
Vcc1_05[4]
Vcc1_05[5]
Vcc1_05[6]
Vcc1_05[7]
Vcc1_05[8]

Vcc1_05[9]
Vcc1_05[10]
Vcc1_05[11]
Vcc1_05[12]
Vcc1_05[13]
Vcc1_05[14]
Vcc1_05[15]
Vcc1_05[16]
Vcc1_05[17]
Vcc1_05[18]
Vcc1_05[19]
Vcc1_05[20]

Vcc3_3 / VccHDA

VccSus3_3/VccSusHDA

V_CPU_IO[1]
V_CPU_IO[2]
V_CPU_IO[3]

Vcc3_3[3]
Vcc3_3[4]
Vcc3_3[5]
Vcc3_3[6]
Vcc3_3[7]
Vcc3_3[8]

Vcc3_3[9]
Vcc3_3[10]
Vcc3_3[11]

Vcc3_3[12]
Vcc3_3[13]
Vcc3_3[14]
Vcc3_3[15]
Vcc3_3[16]
Vcc3_3[17]
Vcc3_3[18]
Vcc3_3[19]
Vcc3_3[20]
Vcc3_3[21]

VccRTC
VccSus3_3[1]
VccSus3_3[2]

VccSus3_3[3]
VccSus3_3[4]
VccSus3_3[5]
VccSus3_3[6]

VccSus3_3[7]
VccSus3_3[8]
VccSus3_3[9]

VccSus3_3[10]
VccSus3_3[11]
VccSus3_3[12]
VccSus3_3[13]
VccSus3_3[14]
VccSus3_3[15]
VccSus3_3[16]
VccSus3_3[17]
VccSus3_3[18]

Vcc1_5_A[19]
Vcc1_5_A[20]

Vcc1_5_A[21]
Vcc1_5_A[22]
Vcc1_5_A[23]

Vcc1_5_A[24]
Vcc1_5_A[25]

VccSus1_05[1]
VccSus1_05[2]

VccSus1_05[3]

Vcc1_5_A[26]
Vcc1_5_A[27]
Vcc1_5_A[28]
Vcc1_5_A[29]
Vcc1_5_A[30]

L11
L12
L14
L16
L17
L18
M11
M18
P11
P18
T11
T18
U11
U18
V11
V12
V14
V16
V17
V18

U6
R7
AE23

AE26
AH26

AA7
AB12
AB20
AC16
AD13
AD18
AG12
AG15
AG19

A5
B13
B16
B7
C10
D15
F9
G11
G12
G16

W5
P7
A24

C24
D19
D22
G19

K3
K4
K5
K6
L1
L2
L3
L6
L7
M6
M7
N7

AB17
AC17

T7
F17
G17

AB8
AC8

K7
C28

G20
A1

H6
H7
J6
J7

+VCCP

0.1U_0402_16V4Z

1

C711

C721

2

1U_0603_10V4Z

1

C731

2

0.1U_0402_16V4Z

1

C741

0.1U_0402_16V4Z

2

1

C723

0.1U_0402_16V4Z

2

+1.5VS

1 2

C699 0.1U_0402_16V4Z

ICH_K7
ICH_C28

ICH_G20

+1.5VS

1

C727

0.1U_0402_16V4Z

2

1

2

+3VALW

+3VS

1

C700

0.1U_0402_16V4Z

2

1

1

C737

2

2

0.1U_0402_16V4Z

1

C738

0.1U_0402_16V4Z

2

1

C720

0.1U_0402_16V4Z

2

1

+

C708
220U_D2_4VM

2

C730

0.1U_0402_16V4Z

T32PAD
T26PAD

T29PAD

+VCCP

+3VS

+3VALW

+3VALW

C695

1 2

0.1U_0402_16V4Z

1 2

C694

0.1U_0402_16V4Z

1 2

C690

4.7U_0805_10V4Z

C712

0.1U_0402_16V4Z

U6E

A4

VSS[0]

A23

VSS[1]

B1

VSS[2]

B8

VSS[3]

B11

VSS[4]

B14

VSS[5]

B17

VSS[6]

B20

VSS[7]

B26

VSS[8]

B28

VSS[9]

C2

VSS[10]

C6

VSS[11]

C27

VSS[12]

D10

VSS[13]

D13

VSS[14]

D18

VSS[15]

D21

VSS[16]

D24

VSS[17]

E1

VSS[18]

E2

VSS[19]

E4

VSS[21]

E8

VSS[22]

+3VS

1

C701

0.1U_0402_16V4Z

2

+RTCVCC

1

1

C709

2

2

0.1U_0402_16V4Z

E15

F3
F4

F5
F12
F27
F28

G1
G2
G5
G6

G9
G14
G18
G21
G24
G25
G26

H3

H4

H5

H24
H27
H28

J1
J2

J5
J24
J25
J26

K24
K27
K28
L13
L15
L24
L25
L26

M3
M4

M5
M12
M13
M14
M15
M16
M17
M24
M27
M28

N1

N2

N5

N6

N11
N12
N13
N14
N15
N16
N17
N18
N24
N25
N26

P3

P4
P12
P13
P14
P15
P16
P17
P24
P27

ICH7_BGA652~D

VSS[23]
VSS[24]
VSS[25]
VSS[26]
VSS[27]
VSS[28]
VSS[29]
VSS[30]
VSS[31]
VSS[32]
VSS[33]
VSS[34]
VSS[35]
VSS[36]
VSS[37]
VSS[38]
VSS[39]
VSS[40]
VSS[41]
VSS[42]
VSS[43]
VSS[44]
VSS[45]
VSS[46]
VSS[47]
VSS[48]
VSS[49]
VSS[50]
VSS[51]
VSS[52]
VSS[53]
VSS[54]
VSS[55]
VSS[56]
VSS[57]
VSS[58]
VSS[59]
VSS[60]
VSS[61]
VSS[62]
VSS[63]
VSS[64]
VSS[65]
VSS[66]
VSS[67]
VSS[68]
VSS[69]
VSS[70]
VSS[71]
VSS[72]
VSS[73]
VSS[74]
VSS[75]
VSS[76]
VSS[77]
VSS[78]
VSS[79]
VSS[80]
VSS[81]
VSS[82]
VSS[83]
VSS[84]
VSS[85]
VSS[86]
VSS[87]
VSS[88]
VSS[89]
VSS[90]
VSS[91]
VSS[92]
VSS[93]
VSS[94]
VSS[95]
VSS[96]
VSS[97]

VSS[98]

VSS[99]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
VSS[159]
VSS[160]
VSS[161]
VSS[162]
VSS[163]
VSS[164]
VSS[165]
VSS[166]
VSS[167]
VSS[168]
VSS[169]
VSS[170]
VSS[171]
VSS[172]
VSS[173]
VSS[174]
VSS[175]
VSS[176]
VSS[177]
VSS[178]
VSS[179]
VSS[180]
VSS[181]
VSS[182]
VSS[183]
VSS[184]
VSS[185]
VSS[186]
VSS[187]
VSS[188]
VSS[189]
VSS[190]
VSS[191]
VSS[192]
VSS[193]
VSS[194]

P28
R1
R11
R12
R13
R14
R15
R16
R17
R18
T6
T12
T13
T14
T15
T16
T17
U4
U12
U13
U14
U15
U16
U17
U24
U25
U26
V2
V13
V15
V24
V27
V28
W6
W24
W25
W26
Y3
Y24
Y27
Y28
AA1
AA24
AA25
AA26
AB4
AB6
AB11
AB14
AB16
AB19
AB21
AB24
AB27
AB28
AC2
AC5
AC9
AC11
AD1
AD3
AD4
AD7
AD8
AD11
AD15
AD19
AD23
AE2
AE4
AE8
AE11
AE13
AE18
AE21
AE24
AE25
AF2
AF4
AF8
AF11
AF27
AF28
AG1
AG3
AG7
AG11
AG14
AG17
AG20
AG25
AH1
AH3
AH7
AH12
AH23
AH27

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/03/10 2006/03/10

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

Compal Electronics, Inc.

ICH7-M(4/4)

LA-2841

1

1.0

of

30 60Thursday, December 15, 2005

5

4

3

2

1

+5VS +3VS

0.1U_0402_16V4Z

1

C439

C453

2

D D

22U_1206_6.3V6M

1000P_0402_50V7K

PSATA_IRX_DTX_N0_C<28>

PSATA_IRX_DTX_P0_C<28>

1

1

2

C449

2

1U_0603_10V4Z

Pleace near HD CONN

C505

3900P_0402_50V7K

C503

3900P_0402_50V7K

1

1

C445

2

C457

2

0.1U_0402_16V4Z

PSATA_ITX_DRX_P0<28>
PSATA_ITX_DRX_N0<28> SSATA_ITX_DRX_P0<28>

12

12

close SATA connector

C C

C434

+3VS

+5VS

1

2

22U_1206_6.3V6M

PSATA_ITX_DRX_P0
PSATA_ITX_DRX_N0

PSATA_IRX_DTX_N0

PSATA_IRX_DTX_P0

0.1U_0402_16V4Z

1

1

C468

1000P_0402_50V7K

2

2

Pleace near HD CONN

1

C464

C447

2

1U_0603_10V4Z

JP33

1

GND

2

A+

3

A-

4

GND

5

B-

6

B+

7

GND

8

V33

9

V33

10

V33

11

GND

12

GND

13

GND

14

V5

15

V5

16

V5

17

GND

18

Reserved

19

GND

20

V12

21

V12

22

V12

SUYIN_127059FR022S305ZL

1

C460

2

0.1U_0402_16V4Z

C500

Main HDD

Need update symbol

Main SATA +5V Default

+5VS +3VS

0.1U_0402_16V4Z

1

1

C514

2

2

22U_1206_6.3V6M

1000P_0402_50V7K

Pleace near HD CONN

SSATA_IRX_DTX_N0_C<28>

SSATA_IRX_DTX_P0_C<28>

3900P_0402_50V7K

1

1

C518

2

2

1U_0603_10V4Z

C480

C484

3900P_0402_50V7K

C513

1

C524

2

0.1U_0402_16V4Z

SSATA_ITX_DRX_N0<28>

12

12

close SATA connector

1

C465

2

22U_1206_6.3V6M

SSATA_ITX_DRX_P0
SSATA_ITX_DRX_N0

SSATA_IRX_DTX_N0

SSATA_IRX_DTX_P0

+3VS

+5VS

0.1U_0402_16V4Z

1

1

C482

1000P_0402_50V7K

2

2

Pleace near HD CONN

1
2
3
4
5
6
7

8

9
10
11
12
13
14
15
16
17
18
19
20
21
22

SUYIN_127059FR022S305ZL

Need update symbol

Main SATA +5V Default

C485

1U_0603_10V4Z

JP31

GND
A+
A­GND
B­B+
GND

V33
V33
V33
GND
GND
GND
V5
V5
V5
GND
Reserved
GND
V12
V12
V12

2nd HDD

1

1

C473

C486

2

2

0.1U_0402_16V4Z

PD_D[0..15]

B B

JP25

CDROM_L<38>

PLT_RST#<7,27,32,34,37>

A A

PLT_RST#

PD_IOW#<28>

PD_IORDY<28>

PD_IRQ<28>
PD_A1<28>
PD_A0<28>

PD_CS#1<28>

ACT_LED#<43>

R217 33_0402_5%

12

PD_D7
PD_D6
PD_D5
PD_D4
PD_D3
PD_D2
PD_D1
PD_D0

PD_IOW#
PD_IORDY
PD_IRQ
PD_A1
PD_A0
PD_CS#1
ACT_LED#

+5VS

PRI_CSEL

R147
470_0402_5%

1 2

1

1

3

3

5

5

7

7
9910
111112
131314
151516
171718
191920
212122
232324
252526
272728
292930
313132
333334
353536
373738
393940
414142
434344
454546
474748
494950
GND51GND

53

GND

GND

SUYIN_800059MR050S119ZL

CD-ROM Connector

5

4

2
4
6
8

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54

PD_D[0..15] <28>

CD_AGND <38>

PD_D8
PD_D9
PD_D10
PD_D11
PD_D12
PD_D13
PD_D14
PD_D15

PD_DREQ

PD_IOR#
PD_DACK#
PDIAG#

PD_A2

PD_CS#3

0.1U_0402_16V4Z

CDROM_R <38>

PD_DREQ <28>
PD_IOR# <28>

PD_DACK# <28>

PD_A2 <28>
PD_CS#3 <28>

12

C380

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

1 2

+5VS

3

R157
100K_0402_5%

+5VS

2005/03/10 2006/03/10

Compal Secret Data

+5VS

1

2

Deciphered Date

C371
1U_0603_10V4Z

1

2

2

C357
10U_0805_10V4Z

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

HDD & CDROM

LA-2841

1

of

31 60Thursday, December 15, 2005

1.0

5

+3VS_CBPLL

+3VS

R234

0_0805_5%7412@

1 2

22_0402_5%CR@

12

C426

1U_0603_10V4Z

1394@

12

R264

56.2_0603_1%

1394@

1

C427

2

270P_0603_50V8J

1394@

12

R251

7412@

56.2_0603_1%

12

R260

56.2_0603_1%

7412@

1

R244

2

7412@

270P_0603_50V8J

5

PCI_AD[0..31]
PCI_CBE#[0..3]

R360

1

C825

15P_0402_50V8J

XD_CD#/SM_PHYS_WP#

R263

1394@

56.2_0603_1%

R265

1394@

R242

1394@

12

R250

7412@

12

56.2_0603_1%

12

5.1K_0603_1%

CLK_48M_CB<15>

12

R262

1394@

56.2_0603_1%

12

56.2_0603_1%

12

5.1K_0603_1%

56.2_0603_1%

2

+3VS

+3VS

XTPBIAS1
XTPA1+
XTPA1­XTPB1+
XTPB1-

MC_PWRON#
PWR_CTRL_1/SM_R/B#

SD_CD#
MS_CD#
SM_CD#

MSBS_SDCMD_SMWE#
MSD3_SDD3_SMD3
MSD2_SDD2_SMD2
MSD1_SDD1_SMD1
MSD0_SDD0_SMD0

SDCLK_SMRE#
SDCMD_SMALE
SDD0_SMD4
SDD1_SMD5
SDD2_SMD6
SDD3_SMD7
SDWP#_SMCE#

SMCLE

1 2

R607 10_0402_5%

1 2

C827 10P_0402_50V8J@

CLK_48M_CB

1 2

4.7K_0402_5%7412@

R280 6.34K_0402_1%7412@

1 2

XTPBIAS0
XTPA0+
XTPA0­XTPB0+
XTPB0­XTPBIAS1
XTPA1+
XTPA1­XTPB1+
XTPB1­CPS

R342

1 2

4.7K_0402_5%7412@

C451

1 2
7412@

10P_0402_50V8J

R298

1M_0402_5%@

C444

1 2
7412@

10P_0402_50V8J

SM_RB#/SC_RFU<33>

PCI_AD[0..31]<27,36>

PCI_CBE#[0..3]<27,36>

D D

MSCLK_SDCLK_SMELWP#

C C

2

8

JP28

SUYIN_020204FR004S506ZL

B B

1

4

4

3

3

2

GND15GND26GND37GND4

2

1

1

CLOSE TO CHIP

CLOSE TO CHIP

2

C423

1

7412@

XTPA1+<46>
XTPA1-<46>
XTPB1+<46>
XTPB1-<46>

A A

1U_0603_10V4Z

R261

7412@

C428

7412@

1

1

C429

C432

2

2

10U_0805_10V4Z

7412@

U18B

C8

MC_PWR_CTRL_0

F8

MC_PWR_CTRL_1/SM_R/B#

E9

SD_CD#

A8

MS_CD#

B8

SM_CD#

A7

MS_CLK/SD_CLK/SM_EL_WP#

E8

MS_BS/SD_CMD/SM_WE#

B6

MS_DATA3/SD_DAT3/SM_D3

A6

MS_DATA2/SD_DAT2/SM_D2

C7

MS_DATA1/SD_DAT1/SM_D1

B7

MS_SDIO(DATA0)/SD_DAT0/SM_D0

A4

SD_CLK/SM_RE#

C5

SD_CMD/SM_ALE

C6

SD_DAT0/SM_D4

A5

SD_DAT1/SM_D5

B5

SD_DAT2/SM_D6

E6

SD_DAT3/SM_D7

E7

SD_WP/SM_CE#

G5

SC_PWR_CTRL

B4

SM_CLE

A3

XD_CD#/SM_PHYS_WP#

P12

TEST0

F1

CLK_48

R316

P17

PHY_TEST_MA

T18

R0

T19

R1

R13

TPBIAS0

V14

TPA0P

W14

TPA0N

V13

TPB0P

W13

TPB0N

W17

TPBIAS1

V16

TPA1P

W16

TPA1N

V15

TPB1P

W15

TPB1N

R12

X_OUT
X_IN

CPS

R18

XO

R19

XI

CPS

X_OUT

12

Y3

7412@

24.576MHZ_16P_1BG24576CK1A

X_IN

SM_RB#/SC_RFU

XD_CD#

1U_0603_10V4Z

7412@

C433

R349

R362
R361

1

2

0.01U_0402_16V7K

7412@

1 2

1 2
1 2

4

L23

1 2

MBK160808_06037412@

+VDDPLL+VDD_PLL

12

P13

AVDD_33

P14

U15

AVDD_33

AVDD_33

U19

P15

VDDPLL_33

7412@

VDDPLL_15

1

2

C452 1U_0603_10V4Z

K19

VR_PORTK1VR_PORT

C458 0.1U_0402_16V4Z7412@

1

2

7412@

7412@

C4671U_0603_10V4Z

0.1U_0402_16V4Z

W8

VCCPP1VCCP

+3VS_CBVCCP

1

C435

2

PCI7412

RI_OUT#/PME#

SUSPEND#

SPKROUT

VSSPLL

AGND

AGND

AGND

R17

R14

U13

U14

+VDDPLL

SM_RB# PWR_CTRL_1/SM_R/B#

R352

1 2

0_0402_5%@

SM_PHYS_WP#

0_0402_5%CR@
0_0402_5%@

4

SM_CD#

R363

0_0402_5%CR@

1 2

0_0402_5%CR@

+3VS

+3VS

R293

0_0805_5%7412@

1

C448

7412@

2

0.1U_0402_16V4Z

M1

AD31

M2

AD30

M3

AD29

M6

AD28

M5

AD27

N1

AD26

N2

AD25

N3

AD24

P3

AD23

R1

AD22

R2

AD21

P5

AD20

R3

AD19

T1

AD18

T2

AD17

W4

AD16

W7

AD15

R8

AD14

U8

AD13

V8

AD12

W9

AD11

V9

AD10

U9

AD9

R9

AD8

V10

AD7

U10

AD6

R10

AD5

W11

AD4

V11

AD3

U11

AD2

P11

AD1

R11

AD0

P2

C/BE3#

U5

C/BE2#

V7

C/BE1#

W10

C/BE0#

U7

PAR

R6

FRAME#

W5

TRDY#

V5

IRDY#

V6

STOP#

U6

DEVSEL#

N5

IDSEL

R7

PERR#

W6

SERR#

L3

REQ#

L2

GNT#

L1

PCLK

K3

PRST#

K5

GRST#

L5
J5
H3
G1

MFUNC0

H5

MFUNC1

H2

MFUNC2

H1

MFUNC3

J1

MFUNC4

J2

MFUNC5

J3

MFUNC6

G2

SCL

G3

SDA

K2

VR_EN#

PCI7412ZHK_PBGA257

7412@

XD_CD#/SM_PHYS_WP#

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

PCI_AD31
PCI_AD30
PCI_AD29
PCI_AD28
PCI_AD27
PCI_AD26
PCI_AD25
PCI_AD24
PCI_AD23
PCI_AD22
PCI_AD21
PCI_AD20
PCI_AD19
PCI_AD18
PCI_AD17
PCI_AD16
PCI_AD15
PCI_AD14
PCI_AD13
PCI_AD12
PCI_AD11
PCI_AD10
PCI_AD9
PCI_AD8
PCI_AD7
PCI_AD6
PCI_AD5
PCI_AD4
PCI_AD3
PCI_AD2
PCI_AD1
PCI_AD0

PCI_CBE#3
PCI_CBE#2
PCI_CBE#1
PCI_CBE#0

CLK_PCI_PCM
PCI_RST#
GRST#
CB_PME#

R329

43K_0402_5%7412@

R314 0_0402_5%7412@
R190 0_0402_5%7412@
R204 0_0402_5%7412@
R313 0_0402_5%7412@
R189 0_0402_5%7412@

CARD_LED

R328 220_0402_5%7412@
R344 220_0402_5%7412@

R320 220_0402_5%7412@

R249
100_0402_5%7412@

R321

3

CB_PME#

12

1 2

+3VS

CARD_LED <43>

100K_0402_5%CR@

R554

MSBS_SDCMD_SMWE#

SDCLK_SMRE#

SDWP#_SMCE#

SM_RB#

+VCC_SD +VCC_SM_XD

+3VS

12

R241

10K_0402_5%@

PCI_AD22

0_0402_5%@

12
12
12
12
12

12
12

12

CLK_48M_CB

12

R334

10_0402_5%@

2

C470

10P_0402_50V8J@

1

2005/03/10 2006/03/10

G

2

13

D

S

Q8
2N7002_SOT23@

MSCLK_SDCLK_SMELWP#

PCI_PAR <27>
PCI_FRAME# <27,36>
PCI_TRDY# <27,36>

PCI_IRDY# <27>

PCI_STOP# <27>

PCI_DEVSEL# <27>
PCI_PERR# <27>

PCI_SERR# <27>
PCI_REQ2# <27>

PCI_GNT2# <27>

CLK_PCI_PCM <15>
PCI_RST# <27,33,36,42,44>
PLT_RST# <7,27,31,34,37>

PCM_SPK <38>

PCI_PIRQC# <27>
PCI_PIRQD# <27>
PCI_PIRQG# <27>

SIRQ <29,42,44>

PCI_PIRQE# <27>

PCI_CLKRUN# <29>

CLK_PCI_PCM

12

R214

10_0402_5%@

1

C420

15P_0402_50V8J@

2

Compal Secret Data

+VCC_SM_XD

C771

CR@

0.1U_0402_16V4Z

PCM_SPK

Deciphered Date

1 2

C823

2

1000P_0402_50V7K

near JP32 pin

1

PCI_PME# <27,44>

MSD0_SDD0_SMD0

MSD1_SDD1_SMD1

MSD2_SDD2_SMD2
MSD3_SDD3_SMD3
SDD0_SMD4
SDD1_SMD5
SDD2_SMD6
SDD3_SMD7

SM_PHYS_WP#
MSBS_SDCMD_SMWE#
SDCMD_SMALE

SM_CD#
SM_RB#

SDCLK_SMRE#

1

SDWP#_SMCE#

2

SMCLE

R315

1 2

0_0402_5%7412@

CARD_LED

R588

1 2

1 2

43K_0402_5%7412@

+VCC_MS

100K_0402_5%CR@

R557

1 2

R602

2

2

1

GRST#PCI_RST#

10K_0402_5%7412@

2

R556

1 2

C824
1000P_0402_50V7K

100K_0402_5%CR@

+VCC_MS +VCC_SD +VCC_MS +VCC_SM_XD

S

D

13

G

R374

2

G

1

2

C779

2

10U_0805_10V4ZCR@

+3VS +3VS

G

2

1 2

S

13

D

Q23
2N7002_SOT23@

S

2 1

D9 CH751H-40_SC76@

2 1

D10 CH751H-40_SC76@

+VCC_MS

5 IN 1 CONN

+VCC_MS

1 2
13

D

Q24
2N7002_SOT23@

S

U42

1

GND

2

IN

3

IN

4

EN#

TPS2041BDR_SO8CR@
C781 10U_0805_10V4ZCR@
C778 0.01U_0402_16V7KCR@

Title

PCI7412

Size Document Number Rev

Custom

LA-2841

Date: Sheet

Q44

CR@

R565

SI2301BDS_SOT23

47K_0402_5% @

1 2

+3VS

1 2

13

D

Q22
2N7002_SOT23CR@

D29 CH751H-40_SC76
D30 CH751H-40_SC76
D31 CH751H-40_SC76
D32 CH751H-40_SC76

11

SD-DAT3

12

SD-DAT2

6

SD-DAT1

7

SD-DAT0

5

SD-WP-SW

10

SD-CMD

8

SD_CLK

9

SD-VCC

4

NC

42

SD-CD-SW

41

SD-CD-COM

15

MS-DATA0

14

MS-DATA1

16

MS-DATA2

18

MS-DATA3

19

MS-SCLK

17

MS-INS

13

MS-BS

20

MS-VCC

40

XD-VCC

39

XD-CD

1

GND

44

GND

8

OUT

7

OUT

6

OUT

5

OC#

12
12

Compal Electronics, Inc.

22K_0402_5%CR@

R559

1 2

34
33
32
31
21
22
23
24

35
43
36
37

25

3
29
26
27
28
30

2
38
45
46

MC_PWRON#

MC_PWRON#

Q43

CR@

SI2301BDS_SOT23

10K_0402_5%CR@

MC_PWRON#

CARD_LED

JP32

SM-D0
SM-D1 / XD-D1
SM-D2 / XD-D2
SM-D3 / XD-D3
SM-D4 / XD-D4
SM-D5 / XD-D5
SM-D6 / XD-D6
SM-D7 / XD-D7

SM_WP-IN / XD_WP-IN
SM-WP-SW
#SM_-WE / XD_-WE
#SM-ALE / XD-ALE

SM-LVD
SM-CD-SW
SM_-VCC / XD_-VCC
#SM_R/-B / XD_R/-B
#SM_-RE / XD_-RE
#SM_-CE / XD_-CE
#SM_-CD
SM-CD-COM
SM-CLE / XD-CLE
GND
GND

TAITN_R007-N3P-15-S

R389

470_0402_5%@

2

G

+3VS

1

S

D

13

G

R564

G

S

SD_CD#
SM_CD#

R595 33_0402_5%CR@
R596 33_0402_5%CR@
R597 33_0402_5%CR@
R598 33_0402_5%CR@

SDWP#_SMCE#

R599 33_0402_5%CR@

MSCLK_SDCLK_SMELWP#

SD_CD#

MSD0_SDD0_SMD0
MSD1_SDD1_SMD1
MSD2_SDD2_SMD2
MSD3_SDD3_SMD3
MSCLK_SDCLK_SMELWP#
MS_CD#
MSBS_SDCMD_SMWE#

XD_CD#

+VCC_MS

2

C782

10U_0805_10V4ZCR@

10K_0402_5%CR@

SD_CD#MS_CD#

2

13

D

Q19

2N7002_SOT23CR@

D33 CH751H-40_SC76

21

D34 CH751H-40_SC76

21

D35 CH751H-40_SC76

21

D36 CH751H-40_SC76

21

1 2
1 2
1 2
1 2

1 2

C826 1000P_0402_50V7K

1 2

+3VS

R567

1 2

1

1

2

R566
47K_0402_5% @

1 2

R358

10K_0402_5%CR@

1 2

MSD3_SDD3_SMD3
MSD2_SDD2_SMD2
MSD1_SDD1_SMD1
MSD0_SDD0_SMD0

MSBS_SDCMD_SMWE#

+VCC_MS

+VCC_SM_XD

10K_0402_5%CR@

of

32 60Thursday, December 15, 2005

21
21
21
21

+VCC_SD

1.0

5

4

3

2

1

CardBus Power Switch

+S1_VCC

D D

S1_D10
S1_D9
S1_D1
S1_D8
S1_D0
S1_A0
S1_A1
S1_A2
S1_A3
S1_A4
S1_A5
S1_A6
S1_A25
S1_A7
S1_A24
S1_A17
S1_IOWR#
S1_A9
S1_IORD#
S1_A11
S1_OE#
S1_CE2#
S1_A10
S1_D15

R343

1 2

33_0402_5%7412@

S1_CD1#

S1_CD2#

S1_D7
S1_D13
S1_D6
S1_D12
S1_D5
S1_D11
S1_D4
S1_D3

S1_REG#
S1_A12
S1_A8
S1_CE1#

S1_A13
S1_A23
S1_A22
S1_A15
S1_A20
S1_A21
S1_A19
S1_A14
S1_WAIT#
S1_INPACK#
S1_WE#
S1_BVD1
S1_WP
S1_A16
S1_RDY#

S1_RST
S1_BVD2
S1_CD1#

S1_CD2#
S1_VS1
S1_VS2

C C

S1_A16_C

B B

C443

12

100P_0402_50V8J7412@
C488

12

100P_0402_50V8J7412@

C487

7412@

0.1U_0402_16V4Z

U18A

C10

CAD31/D10

A10

CAD30/D9

F11

CAD29/D1

E11

CAD28/D8

C11

CAD27/D0

B13

CAD26/A0

C13

CAD25/A1

A14

CAD24/A2

B14

CAD23/A3

B15

CAD22/A4

E14

CAD21/A5

A16

CAD20/A6

D19

CAD19/A25

E17

CAD18/A7

F15

CAD17/A24

H19

CAD16/A17

J17

CAD15/IOWR#

J15

CAD14/A9

J18

CAD13/IORD#

K15

CAD12/A11

K17

CAD11/OE#

K18

CAD10/CE2#

L15

CAD9/A10

L18

CAD8/D15

L19

CAD7/D7

M17

CAD6/D13

M18

CAD5/D6

N19

CAD4/D12

M15

CAD3/D5

N17

CAD2/D11

N18

CAD1/D4

P19

CAD0/D3

E13

CC/BE3#/REG#

E18

CC/BE2#/A12

H18

CC/BE1#/A8

L17

CC/BE0#/CE1#

H14

CPAR/A13

E19

CFRAME#/A23

G15

CTRDY#/A22

F17

CIRDY#/A15

G18

CSTOP#/A20

F19

CDEVSEL#/A21

H15

CBLOCK#/A19

G19

CPERR#/A14

C12

CSERR#/WAIT#

C14

CREQ#/INPACK#

G17

CGNT#/WE#

A12

CSTSCHG/BVD1(STSCHG#/RI#)

A11

CCLKRUN#/WP(IOIS16#)

F18

CCLK/A16

E12

CINT#/READY(IREQ#)

C15

CRST#/RESET

B12

CAUDIO/BVD2(SPKR#)

N15

CCD1#/CD1#

B11

CCD2#/CD2#

A13

CVS1/VS1#

B16

CVS2/VS2#

E10

A_USB_EN#

1

C461

2

1

2

7412@

0.1U_0402_16V4Z

A15

J19

VCCB

PCI 7412

VCCB

GNDF7GND

F10

VCCF6VCCF9VCC

GND

F13

G14

F12

F14

GND

GNDH6GNDK6GND

VCC

VCCJ6VCC

K14

J14

GND

M14

L14

VCCL6VCC

VCCP6VCCP8VCC

GNDN6GNDP7GND

P9

C780

10U_0805_10V4Z7412@

P10

1

1

C489

2

2

0.1U_0402_16V4Z

7412@

DATA/VD2/VPPD1

CLOCK/VD1/VCCD0#

LATCH/VD3/VPPD0

RSVD/VD0/VCCD1#

PCI7412ZHK_PBGA2577412@

1

C490

2

RSVD/D2

0.1U_0402_16V4Z

7412@

RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD

NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC

C483

1

2

C481

0.1U_0402_16V4Z

7412@

CB_DAT

B9

CB_CLK

A9

CB_LATCH

C9

S1_D2

B10
C4

SM_RB#/SC_RFU

D1
E1
E2
E3
F2
F3
F5
G6

S1_A18

H17

S1_D14

M19

A2
A17
A18
B1
B2
B3
B17
B18
B19
C1
C2
C3
C16
C17
C18
C19
D2
D3
D17
D18
E5
N14
P18
T3
T17
U1
U2
U3
U4
U12
U16
U17
U18
V1
V2
V3
V4
V12
V17
V18
V19
W2
W3
W12
W18

1

2

7412@

1

1

C436

C478

2

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

7412@

7412@

+3VS

1

C469

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

7412@

SM_RB#/SC_RFU <32>

+3VS

PCI_RST#<27,32,36,42,44>

R350
R351

+S1_VPP

+S1_VCC

43K_0402_5%

1 2

43K_0402_5%@

1 2

7412@

CB_DAT
CB_CLK
CB_LATCH
PCI_RST#

+3VS

U20

3

DATA

4

CLOCK

5

LATCH

12

RESET#

15

OC#

21

SHDN#

8

AVPP

19

NC0

9

AVCC

10

AVCC

17

NC1

18

NC2

TPS2220ADBRG4_SSOP247412@

Near to PCMCIA slot.

+S1_VCC

1

C491

7412@

10U_0805_10V4Z

2

+S1_VPP

1

C494

7412@

10U_0805_10V4Z

2

20

12V

7

12V

14

NC3

13

3.3V

24

NC4

2

5V

1

5V

11

GND

23

NC5

22

NC6

16

NC7

6

NC8

1

C492

7412@

0.1U_0402_16V4Z

2

1

C493

7412@

0.1U_0402_16V4Z

2

+3VS

+5VS

C523

1

C495

2

0.1U_0402_16V4Z7412@

JP10

GND
GND

DATA3

CD1#

DATA4

DATA11

DATA5

DATA12

DATA6

DATA13

DATA7

DATA14

CE1#

DATA15

ADD10

CE2#

OE#

VS1#

ADD11

IORD#

ADD9

IOWR#

ADD8
ADD17
ADD13
ADD18
ADD14
ADD19

WE#
ADD20
READY
ADD21

VCC
VCC
VPP

VPP
ADD16
ADD22
ADD15
ADD23
ADD12
ADD24

ADD7

ADD25

ADD6

VS2#

ADD5

RESET

ADD4

WAIT#

ADD3

INPACK#

ADD2
REG#
ADD1
BVD2
ADD0

BVD1
DATA0
DATA8
DATA1

69

DATA9

GND

70

DATA2

GND

71

DATA10

GND

72

GND

CD2#

GND
GND

SANTA_130609-1_LT

1

2

0.1U_0402_16V4Z7412@

1
35

S1_D3

2

S1_CD1#

36

S1_D4

3

S1_D11

37

S1_D5

4

S1_D12

38

S1_D6

5

S1_D13

39

S1_D7

6

S1_D14

40

S1_CE1#

7

S1_D15

41

S1_A10

8

S1_CE2#

42

S1_OE#

9

S1_VS1

43

S1_A11

10

S1_IORD#

44

S1_A9

11

S1_IOWR#

45

S1_A8

12

S1_A17

46

S1_A13

13

S1_A18

47

S1_A14

14

S1_A19

48

S1_WE#

15

S1_A20

49

S1_RDY#

16

S1_A21

50

S1_VCC

17
51
18

S1_VPP

52

S1_A16_C

19

S1_A22

53

S1_A15

20

S1_A23

54

S1_A12

21

S1_A24

55

S1_A7

22

S1_A25

56

S1_A6

23

S1_VS2

57

S1_A5

24

S1_RST

58

S1_A4

25

S1_WAIT#

59

S1_A3

26

S1_INPACK#

60

S1_A2

27

S1_REG#

61

S1_A1

28

S1_BVD2

62

S1_A0

29

S1_BVD1

63

S1_D0

30

S1_D8

64

S1_D1

31

S1_D9

65

S1_D2

32

S1_D10

66

S1_WP

33

WP

S1_CD2#

67
34
68

+S1_VCC

+S1_VPP

A A

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/03/10 2006/03/10

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

Compal Electronics, Inc.

PCI7412

LA-2841

1

1.0

of

33 60Thursday, December 15, 2005

A

B

C

D

E

Express Card Power Switch

C471

EXP@

0.1U_0402_16V4Z

1 1

+3VS

G

2

13

D

PLT_RST#<7,27,31,32,37>

S

2N7002_SOT23EXP@

Q51

EXP@

0.1U_0402_16V4Z

EXP@

0.1U_0402_16V4Z

+3VALW

CPUSB#<29,44>
SUSP#<44,45,47,51,52,54>

SYSON<44,47,51>

C454

C466

12

12

12

+3VS

+3VALW

+1.5VS

R180 100K_0402_5%EXP@

12

SUSP#
SYSON
PLTRST#

close to JP36

R391

R413
R412

ICH_SMBCLK<15,29,37>

ICH_SMBDATA<15,29,37>

1 2

CLKREQC#<15>

CLK_PCIE_NC1#<15>

CLK_PCIE_NC1<15>

PCIE_RXN1<29>
PCIE_RXP1<29>

PCIE_TXN1<29>

PCIE_TXP1<29>

0_0402_5%17_EXP@

1 2
1 2

0_0402_5%17_EXP@

+3V_PEC
+3VS_PEC

+1.5VS_PEC
+1.5VS_PEC

USB7­USB7+
CPUSB#

ICH_SMBCLK
ICH_SMBDATA

PCIE_PME#_R

PERST#

CLKREQC#
CPUSB#
CLK_PCIE_NC1#
CLK_PCIE_NC1

PCIE_RXN1
PCIE_RXP1

PCIE_TXN1
PCIE_TXP1

USB20_N7<29>

2 2

USB20_P7<29>

ICH_PCIE_WAKE#<29,37>

USB20_N7
USB20_P7

17_EXP@

0_0402_5%

U16

5

3.3Vin1

6

3.3Vin2

21

3.3Vaux_in

18

1.5Vin1

19

1.5Vin2

14

CPUSB#

15

CPPE#

4

STBY#
SHDN#3RCLKEN

2

SYSRST#

11

JP14

1

GND

2

USB_D-

3

USB_D+

4

CPUSB#

5

RSV

6

RSV

7

SMB_CLK

8

SMB_DATA

9

+1.5V

10

+1.5V

11

WAKE#

12

+3.3VAUX

13

PERST#

14

+3.3V

15

+3.3V

16

CLKREQ#

17

CPPE#

18

REFCLK-

19

REFCLK+

20

GND

21

PERn0

22

PERp0

23

GND

24

PETn0

25

PETp0

26

GND

27

GND

28

GND

FOX_1CH4110C

GND

3.3Vout1

3.3Vout2

1.5Vout1

1.5Vout2

PERST#

NC11NC210NC312NC413NC5

24

7
8

20

Aux_out

16
17

23

OC#

22
9

EXP@

TPS2231PWPR_PWP24

+3VS_PEC

+3V_PEC

+1.5VS_PEC

R307 0_0402_5%@

PERST#

12

17_EXP@

0.1U_0402_16V4Z

17_EXP@

0.1U_0402_16V4Z

EXPCRD_RST#

EXPCRD_RST# <44>

Near to Express Card slot. 17

+3VS_PEC

4.7U_0805_10V4Z

C530

C558

1

2

+1.5VS_PEC

1

2

1

C532

2

4.7U_0805_10V4Z

1

C555

2

17_EXP@

17_EXP@

17_EXP@

0.1U_0402_16V4Z

C542

+3V_PEC

1

2

1

C543

17_EXP@

4.7U_0805_10V4Z

2

3 3

USB20_N7
USB20_P7
CPUSB#

ICH_SMBCLK

+1.5VS_PEC

+1.5VS_PEC
+3V_PEC
+3VS_PEC

CLKREQD#<15>

CLK_PCIE_NC2#<15>

CLK_PCIE_NC2<15>

PCIE_RXN2<29>
PCIE_RXP2<29>

PCIE_TXN2<29>

PCIE_TXP2<29>

4 4

A

B

ICH_SMBDATA

PCIE_PME#_R

PERST#

CLKREQD#
CPUSB#
CLK_PCIE_NC2#
CLK_PCIE_NC2

PCIE_RXN2
PCIE_RXP2

PCIE_TXN2
PCIE_TXP2

JP13

1

GND

2

USB_D-

3

USB_D+

4

CPUSB#

5

RSV

6

RSV

7

SMB_CLK

8

SMB_DATA

9

+1.5V

10

+1.5V

11

WAKE#

12

+3.3VAUX

13

PERST#

14

+3.3V

15

+3.3V

16

CLKREQ#

17

CPPE#

18

REFCLK-

19

REFCLK+

20

GND

21

PERn0

22

PERp0

23

GND

24

PETn0

25

PETp0

26

GND

27

GND

28

GND

FOX_1CH4110C

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

15_EXP@

0.1U_0402_16V4Z

15_EXP@

0.1U_0402_16V4Z

2005/03/10 2006/03/10

Near to Express Card slot. 15.4

+3VS_PEC

4.7U_0805_10V4Z

1

C528

2

+1.5VS_PEC

1

C554

2

Compal Secret Data

Deciphered Date

1

C529

2

4.7U_0805_10V4Z

1

C553

2

15_EXP@

15_EXP@

D

15_EXP@

0.1U_0402_16V4Z

C537

+3V_PEC

1

2

1

C545

15_EXP@

4.7U_0805_10V4Z

2

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

Express Card

LA-2841

E

1.0

of

34 60Thursday, December 15, 2005

5

D D

+3VLAN

C C

1

+3VLAN

R555

0_0603_5%

C768

0.1U_0402_16V4Z

B B

C767

12

1

2

2

0.1U_0402_16V4Z

10U_0805_6.3V4Z

+3V_LAN

1

C766

C769

2

10U_0805_6.3V4Z

0.1U_0402_16V4Z

C774

1

2

1

C772

1

1

C773

2

0.1U_0402_16V4Z

C775

2

0.1U_0402_16V4Z

1 2

R558 200_0402_5%

2

1

2

0.1U_0402_16V4Z

4

+3VLAN+3VALW

15 mil

L31
BLM11A121SPT_0603

U41

1

VCC

25

VCC

36

1

C770

2

0.1U_0402_16V4Z

VCCP

40

VCCP

2

VCCA

7

VCCA2

9

VCCT

12

VCCT

14

VCCT

17

VCCT

19

VCCR

23

VCCR

8

VSS

13

VSS

18

VSS

24

VSS

48

VSS

33

VSSP

38

VSSP

3

VSSA

6

VSSA2

20

VSSR

22

VSSR

28

ISOL_TI

30

ISOL_TCK

29

ISOL_EXEC

21

TESTEN

41

ADV10

82562GT_SSOP48

12

TDP
TDN
RDP
RDN

SPDLED#
ACTLED#

LILED#

JRXD2
JRXD1
JRXD0

JRSTSYNC

JTXD2
JTXD1
JTXD0

JCLK

TOUT

RBIAS100

RBIAS10

TDP

10

TDN

11

RDP

15

RDN

16
31

ACTLED#

32

LINK_LED100#

27

LAN_RXD2

37

LAN_RXD1

35

LAN_RXD0

34

LAN_RSTSYNC

42

LAN_TXD2

45

LAN_TXD1

44

LAN_TXD0

43

LAN_JCLK

39
26

R562 619_0402_1%

5

R563 619_0402_1%

4

46

X1

47

X2

LAN1_XO

LAN1_XI

3

close to U41chip(Intel rule)

TDP

TDN

close to U41chip(Intel rule)

RDP

RDN

LAN_RXD2 <28>
LAN_RXD1 <28>
LAN_RXD0 <28>
LAN_RSTSYNC <28>

LAN_TXD2 <28>
LAN_TXD1 <28>
LAN_TXD0 <28>
LAN_JCLK <28>

1 2
1 2

C777

1 2

22P_0402_50V8J

Y6
25MHZ_20P_1BG25000CK1A

C776

1 2

1 2

22P_0402_50V8J

R561
110_0402_1%

1 2

R606

110_0402_1%@

1 2

C756 0.01U_0402_16V7K

@

+3VLAN

@

1 2

1

2

R582
0_0402_5%

C757 0.01U_0402_16V7K

@

1

2

2

RJ45_GND

TDN
TDP

RDN
RDP

R36
300_0603_5%

ACTLED#

LINK_LED100#

U12

TD-8TX­TD+
CT

CT
RD­RD+

NS0013_16P

1 2

R43
300_0603_5%

1 2

+3VALW

TX+

CT

CT

RX-

RX+

R583
75_0402_5%

1 2

R584
75_0402_5%

1 2

7
6

3
2
1

close to U12

RDP

1 2

RDN

+3VALW

MDO1-

MDO1+
MDO0­MDO0+

MDO0-

9

MDO0+

10

MCT0 RJ45_GND

11

MCT1

14

MDO1-

15

MDO1+

16

R560
110_0402_1%

JP19

12

Amber LED-

11

Amber LED+

8

PR4-

7

PR4+

6

PR2-

5

PR3-

4

PR3+

3

PR2+

2

PR1-

1

PR1+

10

Green LED-

9

Green LED+

SUYIN_100073FR012S100ZLCONN@

MDO0- <46>
MDO0+ <46>

MDO1- <46>
MDO1+ <46>

R171
75_0402_5%

R170
75_0402_5%

1

SHLD4
SHLD3

SHLD2
SHLD1

12

12

16
15

14
13

C414

12

1000P_1206_2KV7K

A A

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/03/10 2006/03/10

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

Compal Electronics, Inc.

82562EZ LAN

LA-2841

1

1.0

of

35 60Thursday, December 15, 2005

5

Port 80 Debug Card Connector

4

3

2

1

D D

C C

+5VS

PCI_CBE#0<27,32>

PCI_AD6<27,32>
PCI_AD4<27,32>
PCI_AD2<27,32>
PCI_AD0<27,32>
PCI_AD1<27,32>
PCI_AD3<27,32>
PCI_AD5<27,32>
PCI_AD7<27,32>

PCI_AD8<27,32>
PCI_CBE#1<27,32>
PCI_CBE#2<27,32>
PCI_CBE#3<27,32>

CLK_PCI_MINI<15>

PCI_RST#<27,32,33,42,44>

PCI_FRAME#<27,32>

PCI_TRDY#<27,32>

PCI_AD9<27,32>

JP27

20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

HEADER 20@

B B

A A

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/03/10 2006/03/10

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

Compal Electronics, Inc.

Debug port

LA-2841

1

1.0

of

36 60Thursday, December 15, 2005

A

B

C

D

E

Mini-Express Card(Slot 1-WLAN)

C608

12

0.1U_0402_16V4Z

R600 100_0402_5%

1 2

JP18

112
334
556
778
9910
111112
131314
151516

171718
191920
212122
232324
252526
272728
292930
313132
333334
353536
373738
393940
414142
434344
454546
474748
494950
515152
535354
555556

MOLEX_67910-0002

2
4
6
8
10
12
14
16

18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56

C797

0.1U_0402_16V4Z@

PLT_RST#

+3VALW

ICH_SMBCLK

ICH_SMBDATA

LED_WLAN_OUT#

1 2

C78

WL_ON <29>
PLT_RST# <7,27,31,32,34>

ICH_SMBCLK <15,29,34>
ICH_SMBDATA <15,29,34>

D2

1

BAS16_SOT23

1

2

0.1U_0402_16V4Z

2

3

+3VS
+1.5VS

1

C167

2

0.1U_0402_16V4Z

LED_WLANOUT#

DTA114YKA_SC59

WIRELESS_LED_BT<41>

10K

2

Q48

R593

100K_0402_5%

100K_0402_5%

+3VS

47K

1 3

12

R594

2

G

Q49

2N7002_SOT23

12

2N7002_SOT23

WLED#

13

D

S

13

D

2

G

Q50

S

12

WL_LED# <16,42>

R592

470_0402_5%

1 1

2 2

ICH_PCIE_WAKE#<29,34>

WL_PRIORITY<41>

BT_PRIORITY<41>

CLKREQA#<15>

CLK_PCIE_MCARD#<15>
CLK_PCIE_MCARD<15>

PCIE_RXN3<29>
PCIE_RXP3<29>

PCIE_TXN3<29>
PCIE_TXP3<29>

CLK_PCIE_MCARD#
CLK_PCIE_MCARD

3 3

4 4

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2005/03/10 2006/03/10

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

D

Date: Sheet

Compal Electronics, Inc.

Mini Card

LA-2841

E

1.0

of

37 60Thursday, December 15, 2005

A

B

C

D

E

+3VAMP_CODEC

W=40Mil

MONO_INR <40>

1

2

+5VS

1

C526

C504

2

10U_0805_10V4Z

0.1U_0402_16V4Z

For Layout:

Place decoupling caps near the
power pins of SmartAMC
device.

U27

1

12

9

DVDD1

DVDD3
RST#
DIBN

DIBP
PWRCLKP
PWRCLKN

BCLK
SYNC
SDI
SDO

PCBEEP

XTALIN
XTALOUT

VREF_FILT
VREF
VC

DVDD2

DVSS1

DVSS3

DVSS2

2

5

46

R393

0_0402_5%

6

VSUB

11
47

48

3
4

13
10

8
7

43

15
16

23
19
18

1

2

10K_0402_5%

14

VDDCK

VSSCK

17

12

12

R408
10K_0402_1%

C560

ACZ_RST#<28,44>

10U_0805_10V4Z

1

2

R409

5.1K_0402_5%

1 2

SB_SPKR <29>PCM_SPK<32>

1

2

C566

0.1U_0402_16V4Z

R149

C549

0.1U_0402_16V4Z

C563
1U_0603_10V4Z

1 2

1

1

2

2

C569

0.1U_0402_16V4Z

R418 0_0402_5%
R417 0_0402_5%
R420 0_0402_5%
R419 0_0402_5%

R407 33_0402_5%
R158 33_0402_5%
R421 33_0402_5%
R151 33_0402_5%

12

12

R152
10K_0402_5%

1

C562

2

0.1U_0402_16V4Z

C568

0.1U_0402_16V4Z

1 2
1 2
1 2
1 2

1 2
1 2
1 2
1 2

MONO_INR

+3VDD_CODEC

1

2

C567

0.1U_0402_16V4Z

ACZ_RST#

REF_FILT

VREF
VC

R411
0_0402_5%

MONO_IN MONO_IN1 MONO_INR

1 2

R422
560_0402_5%

Q28

2

1 2

3 1

R401
0_0805_5%

1 2

+3VALW

2

C571

C570

1

2

1

1

2

DIB_DATAN<39>
DIB_DATAP<39>

ACZ_BITCLK<28>

ACZ_SYNC<28> CDROM_R <31>

ACZ_SDIN0<28>
ACZ_SDOUT<28>

10K_0402_5%

1

C548

C547

2

1U_0603_10V4Z

0.1U_0402_16V4Z

Q29
MMBT3904_SOT23
MMBT3904_SOT23

3 1

150P_0402_50V8J

150P_0402_50V8J

1 1

R416
560_0402_5%

1 2

2

2 2

PWRCLKP<39>
PWRCLKN<39>

3 3

4

12

2

R385

8

C564

0.1U_0402_16V4Z

25

35

AVDD1

AVDD2

MIC_R

MIC_L

MICBIAS_F

MICBIAS_C

MICBIAS_B

CD_L

CD_GND

CD_R

PORT-A_L
PORT-A_R

PORT-B_L
PORT-B_R

PORT-C_L
PORT-C_R

PORT-D_L
PORT-D_R

EAPD

SPDIF_OUT

SENSEA
SENSEB

AVSS1

AVSS2

24

36

CX20551-22_TQFP48

U26

VIN

SENSE or ADJ

DELAY
ERROR7CNOISE
SD

SI9182DH-AD_MSOP8

1

1

2

2

C546

0.1U_0402_16V4Z

MIC_INR

26

MIC_INL

27
20
21
22

CDROM_RC_L CDROM_R_L

28

CDGNDA

29

CDROM_RC_R

30

LINE_OUTL

40

LINE_OUTR

39

DOCK_LOUTL

38

DOCK_LOUTR

37

DOCKMIC DOCK_MICR

34
33

32
31

EAPD

45

SPDIFO

44

SENSEA

41

SENSEB

42

SENSEA

SENSEB

250mA

5

VOUT

6
1
3

GND

0.01U_0402_16V7K

+3VAMP_CODEC

1

2

1U_0603_10V4Z

C559

C539 10U_0805_10V4Z
C540 10U_0805_10V4Z

+CODEC_REFF
+CODEC_REFC

C536 2.2U_0603_6.3V4Z
C535 2.2U_0603_6.3V4Z
C534 2.2U_0603_6.3V4Z

C541

1 2

10U_0805_10V4Z

SPDIFO <42,46>

R410

1.5K_0402_5%

1 2

1

C565

2

R404
0_0805_5%

1 2

1 2
1 2

LINE_OUTL <40>
LINE_OUTR <40>

R414

1 2

20K_0402_5%

R415

1 2

10K_0402_5%

R405

1 2

5.1K_0402_5%

18K_0402_5%

00

0

NC OFF
NC 0
NC NC

4 4

MIC_DET

PORT-C P ORT-F

0

ON

NC

OFF

1 2

R392

12

47K_0603_1%
R403

27K_0603_1%

2.2K_0402_5%

12
12
12

R380

R384

2K_0402_5%

OFF

ON

+VDDA_CODEC

+VDDA_CODEC

+CODEC_REFF

R386

12

12

HP_DET# <40>

JACK_DET# <46>

MIC_DET <42>

ON
ON

OFF

ON

1

C533
1U_0603_10V4Z

2

12

12

R387

2.2K_0402_5%

CD_GNA
CDROM_R_R

DOCK_MIC <46>

DOCK_MICR

DOCK_LOUTR

DOCK_LOUTL

PORT-BPORT-AJACK_DET#HP_DET#

OFF

ON

OFF

(3.33V)

1

2

MIC_R <42>
MIC_L <42>

12

R378

6.8K_0402_5%

R388

1 2

C538

@

0.1U_0402_16V4Z

12

0_0402_5%

R379

6.8K_0402_5%

R381

2.2K_0402_5%

C521

1 2

150U_D2_6.3VM

C520

1 2

150U_D2_6.3VM

EQ

Disable
Disable
Disable

Enable

R377 6.8K_0402_5%@

1 2

R376 0_0402_5%

1 2

R375 6.8K_0402_5%@

1 2

R356

1 2

33_0805_5%
R355

1 2

33_0805_5%

12

+CODEC_REFC

+

+

C502

@

0.1U_0402_16V4Z

1 2

C519

@

0_0402_5%

1 2

C516

@

0.1U_0402_16V4Z

1 2

R423
0_1206_5%

1 2

R300

@

0_1206_5%

1 2

DOCK_LOUT_R

DOCK_LOUT_L

R354

1K_0402_5%

EAPD

2

G

GNDAGND

12

+3VS

R591

100_0402_5%

1 2
13

D

Q47

S

2N7002_SOT23

CDROM_L <31>
CD_AGND <31>

12

R357

1K_0402_5%

GNDA <40,42,46>

DOCK_LOUT_R <46>

DOCK_LOUT_L <46>

MUTE_LED <42,46>

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2005/03/10 2006/03/10

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

D

Date: Sheet

Compal Electronics, Inc.

AMOM_codec

LA-2841

E

1.0

of

38 60Thursday, December 15, 2005

MTP28

MC930

2.2U_0805_10V6K

MC926
10P_0402_50V8J

1 2

MFB906

MTP60

1

DIB_P2

DIB_N2DIB_N1

1

Vc_LSD
Vref_LSD

1

1

MC976

2

2

1

CLK

PWR+

MTP62

MTP63

MTP30

1

1

2

1

1

VDD

1

2

AGND_LSD

MU902

26

CLK

7

PWR+

27

DIB_P

28

DIB_N

3

Vc

4

VRef

8

NC1

22

NC2

25

NC3

29

PADDLE

AGND_LSD

0.1U_0402_10V6K
MC928

MTP58

2

AVdd

AGnd

DC_GND

6

15

DGND_LSD AGND_LSD

MTP59

1

VDD

MC978

0.1U_0402_10V6K

1 2

1

DVdd

23

RAC1
TAC1

RAC2
TAC2

TRDC

GPIO1

RBias

DGnd

DGND_LSD

21
20

MTP34

19
18

12
11

EIC

9

RXI

1
5

10

VZ

17

EIO

16

EIF

14

TXO

13

TXF

CX20493-58_QFN28

24

1

MTP36

1

MTP35

MR902
1M_0805_5%

RAC1

1 2

TAC1

1M_0805_5%
MR904

1

TRDC

MTP33

1

MC958

EIC

1 2

0.015U_0603_25V7K
MR910
237K_0805_1%

RXI

1 2

1

MTP70

RBias

MR954

1 2

59K_0402_1%
MTP69

1

MR908

1 2

348K_0805_1%
MTP68

1

EIO

Use 59K_0402_1% for MR954

EIF

TXO

TXF

1

MTP37

1

MTP38

MC902

RAC1/RING
TAC1/TIP

12

MR906 6.8M_0805_5%

1

2

AGND_LSD

RXI-1

AGND_LSD

1

1

MC904

1 2

MC918

0.1U_0603_16V7K

1

1 2

0.047U_1206_100V7K

MTP67

MTP65

1 2
1 2

MTP40

MTP71

MC910

2

B

1

0.033U_1206_100V7K

0.033U_1206_100V7K

1

1

MTP32

C

MQ906

PMBTA42_SOT23

E

3 1

1

MTP64

12

MR938
110_0603_5%

AGND_LSD

MTP39

2

B

TIP_2

1 2

BRIDGE_CCVZ

C

MQ902
PMBTA42_SOT23

E

3 1

MTP31

1

3
3

1

MC966

0.01U_0805_100V7M

1

1

C906 and C908 must be Y3 type
Capacitors for Nordic
Countries only

MFB902

1 2

MMZ1608D301BT_0603

MBR904
MMBD3004S_SOT23

TIP_2

2
2

AGND_LSD

MBR906
MMBD3004S_SOT23

MFB904

1 2

MMZ1608D301BT_0603

2

4

MQ904

FZT458TA_SOT223

MTP66

3

1

12

MR928
27_0805_5%

1

AGND_LSD

MTP49

MOD_RINGRING_2

MC906

1

470P_1808_3KV

2

GND

1

MC908
470P_1808_3KV

2

AGND_LSD

TB3100M-13-01_SMB

1

1
2

2

MOD_TIP

1

MTP41

MJ2

MRV902

E&T_3800-02

1

MTP42

2
1

MTP52

1

MTP26

1

MTP22

1

PWRCLKN<38>

PWRCLKP<38>

DIB_DATAP<38>

DIB_DATAN<38>

MJ1

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

HEADER8@

MJ1B

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

HEADER8@

MTP23

1

2 3

MTP24

1

MT902

30U_82154R_1%_1:1.67

MTP25

GND

BR908_AC1

41

1

MC962
47P_0603_50V8J

2

PCLK

SECPRI

Check 0.047u or 10p cap

MTP27

1

MC922 10P_1808_3KV

MC924 10P_1808_3KV

1

MT922

2 3

30U_82154R_1%_1:1.67@

1 2

1 2

BR908_CC

MBR908A

6

BAV99DW-7_SOT363

1

2

4

5

MBR908B

3

BAV99DW-7_SOT363

41

SECPRI

0.001U_0402_50V7M@

1

MC974

MR932
15K_0402_5%

MTP72

1

MC944

2

AGND_LSD

MTP29

CLK2

1 2

MMZ1608D301BT_0603

1

MC970

0.1U_0402_10V6K

2

AGND_LSD

DIB_P1

1 2

1 2

MTP73

1

MC940
1U_0603_6.3V6M

1

2

0.1U_0402_10V6K

1

1 2

MR922
0_0402_5%

0_0402_5%
MR924

MTP61

0.001U_0402_50V7M

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2005/03/10 2006/03/10

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

AMOM_modem

LA-2841

39 60Thursday, December 15, 2005

1.0

A

1 1

C475 0.047U_0603_16V7K

LINE_OUTR<38>

LINE_OUTL<38>

+5VS

1
2

MONO_INR<38>

PCBEEP<29>

2 2

3 3

1 2

C476 0.47U_0603_16V7K

1 2

C509 0.47U_0603_16V7K

C510 0.47U_0603_16V7K

C508 0.47U_0603_16V7K

1 2

C507 0.047U_0603_16V7K

1 2

U45

IN
V+
GND3NC

PI5A4599ACEX

COM

NO

HP_DET#<38>

C477 0.47U_0603_16V7K

6
5
4

10K_0402_5%

HP_DET

Q13

2N7002_SOT23

1 2

1 2

1 2

EC_MUTE#<44>

12

R353

74AHCT1G125GW_SOT353-5

R345

10K_0402_5%

13

D

2

G

S

4

U44

LINE_C_OUTR
HP_C_OUTR

HP_C_OUTL
LINE_C_OUTL

+5V+5VS

12

+5V

1

OE#

A2Y

B

23
20

8

10

6
5

14
22

1 2

5

P

G

3

19

U21

VDD

RLINEIN
RHPIN
RIN

LIN
LHPIN
LLINEIN

PC-BEEP
SHUTDOWN#

GND424GND3

GND212GND1

1

13

TPA0312PWPRG4_TSSOP24

HPDET#

C785

0.1U_0402_16V4Z

C462

10U_0805_10V4Z

18

PVDD17PVDD2

LOUT+
ROUT-

ROUT+

SE/BTL#

HP/LINE#

BYPASS

HPDET# <42>

LOUT-

GAIN1
GAIN0

0.1U_0402_16V4Z

1

C479

2

9
4
16
21

15
17

3
2

11

1

C501

2

0.1U_0402_16V4Z

SPKL­SPKL+
SPKR­SPKR+

2

C511

0.1U_0402_16V4Z

1

1

2

HP_DET

R322
0_1206_5%

1 2

SPKL+ <42>
SPKR+ <42>

C

+5VS+5VAMP

R371

100K_0402_5%

R373

@

100K_0402_5%

12

12

10 dB

+5VS

12

R368

@

100K_0402_5%

12

R364
100K_0402_5%

GAIN0

0
0
1 0
1

D

HEADPHONE OUT/LINE OUT

Gain Settings

0
1

SE/BTL#

0
0

GAIN1

0

1

0
1XX

SPKL+
SPKL­SPKR+
SPKR-

1

C496

C497

2

@

@

47P_0402_50V8J

1

1

C498

C499

2

2

@

@

47P_0402_50V8J

47P_0402_50V8J

47P_0402_50V8J

* 10 dB

1

2

Av(inv)

6 dB

15.6 dB

21.6 dB

4.1 dB

JP11

1

1

2

2

3

3

4

4

ACES_85205-0400

E

4 4

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2005/03/10 2006/03/10

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

D

Date: Sheet

Compal Electronics, Inc.

AMP & Audio Jack

LA-2841

E

1.0

of

40 60Thursday, December 15, 2005

C754

12

0.1U_0402_16V4Z

+5V

U38

3

VIN

VOUT

4

VIN/CE

VOUT

2

GND

RT9701PBL_SOT25

1
5

+USB_VCCB

R542

10K_0402_5%

R544

20K_0402_5%

12

USB_OC#0
USB_OC#3

R543

1 2

12

0_0402_5%

USB_OC#0 <29>
USB_OC#3 <29>

USB CONNECTOR (Left side)

JP26

1

5

1

R535 0_0603_5%

USB20_P0<29>

USB20_N0<29>

+USB_VCCB +USB_VCCB

C789

@

R537 0_0603_5%

1

+

+

C736

2

100U_6.3V_M

150U_D_6.3VM

@

1 2
1 2

1

C401

2

0.1U_0402_16V4Z

1

2

USBP0+USB20_P0
USBP0-USB20_N0

W=40mils W=40mils

1

C400

2

1000P_0402_50V7K

SUYIN_020122MR008S573ZR

5

USBP3+ USB20_P3

2

6

2

6

3

7

3

7

4

8

4

8

9

GND

10

GND

11

GND

12

GND

R523 0_0603_5%

USBP3- USB20_N3

1 2

R532 0_0603_5%

1 2

1

C394

C397

2

0.1U_0402_16V4Z

1000P_0402_50V7K

1

1

+

C408

2

2

100U_D2_10VM

USB20_P3 <29>
USB20_N3 <29>

USBP0+

USBP3+ USBP0-

U9

1

D1+

2

VCC

GND

3

D2-

IP4220CZ6_SO6@

USBP3-

4

D2+

5
6

D1-

+USB_VCCB

WIRELESS_LED_BT<37>

BT_ON#<29>

+3VALW

USB20_P6<29>

USB20_N6<29>

WL_PRIORITY<37>

12

C118

1U_0603_10V4Z

1 2

BT_PRIORITY<37>

BT_DET#<29>

R541
100K_0402_5%

R601 100_0402_5%

0.1U_0402_16V4Z@

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

BT CONNECTOR

G

2

S

1

AO3419_SOT23
Q2

2

USB20_P6
USB20_N6
WIRELESS_LED_BT

BT_DET#

1

C808

2

2005/03/10 2006/03/10

13

D

+3V_BT

1

2

C108
1U_0603_10V4Z

1 2

JP6

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

ACES_87213-0800

C611

0.1U_0402_16V4Z

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

Bluetooth & U S B CONN.

LA-2841

of

41 60Thursday, December 15, 2005

1.0

5

D38

KSO2

1 5

INT_KBD CONN.( TYPE "D" KB)

KSI[0..7]

D D

C C

KSO[0..16]

KSO_D_17<44>

KSI7
KSI0
KSI5
KSI1
KSI4
KSI6
KSI3
KSI2
KSO1
KSO2
KSO4
KSO0
KSO16
KSO5
KSO6
KSO3
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15
KSO_D_17

KSI[0..7] <44>

KSO[0..16] <44>

JP4

26

26

25

25

24

24

23

23

22

22

21

21

20

20

19

19

18

18

17

17

16

16

15

15

14

14

13

13

12

12

11

11

10

10

9

9

8

8

7

7

6

6

5

5

4

4

3

3

2

2

1

1

ACES_85201-2605

CONN@

2

KSO4

NZQA5V6AXV5T1_SOT533-5
D40

KSO6 KSO0

1 5

2

KSO3

NZQA5V6AXV5T1_SOT533-5
D42

1 5

2

KSO11

NZQA5V6AXV5T1_SOT533-5
D44

KSO16

1 5

2

KSO_D_17

NZQA5V6AXV5T1_SOT533-5

4

D39

KSI1

43

43

43

43

KSO7

KSO8

KSO12

KSO13

KSO15KSO14

KSO10

1 5

2

KSI7 KSI6

NZQA5V6AXV5T1_SOT533-5
D41

KSI4

1 5

2

KSI5 KSI2

NZQA5V6AXV5T1_SOT533-5
D43

KSI3

1 5

2

KSO5

NZQA5V6AXV5T1_SOT533-5

KSO9

43

15.4 ( TYPE "C" KB)

43

KSO1

KSI0

43

3

KSI1
KSI7
KSI6
KSO9
KSI4
KSI5
KSO0
KSI2
KSI3
KSO5
KSO1
KSI0
KSO2
KSO4
KSO7
KSO8
KSO6
KSO3
KSO12
KSO13
KSO14
KSO11
KSO10
KSO15

ACES_85201-2405

2

1

Power BTN

D11
DAN202U_SC70

ON/OFFBTN#

0.1U_0402_16V4Z

JP8

24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

ESD

EC_ON<44,50>

EC_ON

D

Q25

2N7002_SOT23@

S

C809

LDO3

12

13

R383

4.7K_0402_5%

0_0402_5%

2

G

1

1

2

Q26
DTC124EK_SC59

R603

12

12

@

TP to MB CONN(15.4)

+5V

1

TP_DATA<44>
TP_CLK<44>

2

@

C442

0.1U_0402_10V6K

TP_DATA
TP_CLK

1
2
3
4
5
6
7
8

JP7

ACES_87152-0807

CIR@

10U_0805_10V4Z

3

2

1

O

I

2

R604
0_0402_5%

Consumer IR

1

C784

2

LDO3

R396 100K_0402_5%

1 2

ON/OFF#

1

C544

G

2

3

1000P_0402_50V7K

WHEN R=0,Vbe=1.35V
WHEN R=33K,Vb e =0.8V

1

C783

CIR@

0.1U_0402_10V6K

2

R612

10K_0402_5%

1 2

CIR_IN

CIR_IN<44,46>

LDO3

ON/OFF# <44>

EC_PWR_ON# <48>

12

D12
RLZ20A_LL34

LDO5

12

CIR@

100_0402_5%

U43

4

TSOP36236TR_4P

R569

CIR@

Vs3GND
OUT

GND

1
2

Switch board conn

1

3

JP5

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

11

11

12

12

13

13

14

14

15

15

16

16

17

17

18

18

19

19

20

20

21

21

22

22

23

23

24

24

25

25

ACES_85201-2505

2005/03/10 2006/03/10

B B

JP15

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

+5VS

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
LPC_FRAME#
LPC_DRQ#0
PCI_RST#

SIRQ

+3VS

LPC_AD[0..3] <28,44>

LPC_FRAME# <28,44>
LPC_DRQ#0 <28>

PCI_RST# <27,32,33,36,44>
CLK_PCI_SIO <15>

SIRQ <29,32,44>

5

FOR LPC SIO DEBUG PORT

R424

@

10K_0402_5%

12

4

1
2
3
4
5
6
7
8
9

A A

10
11
12
13
14
15
16
17
18
19
20

ACES_85201-2005

PWR_ACTIVE#<44>

VOL_UP#
VOL_DWN#

VOL_DWN#<44>

PA_LED_ALW<43,44>
PR_LED_ALW<43>

PA_LED<43>
PR_LED<43>

PA_LED_VS<43>
PR_LED_VS<43>

KSI0<44>
KSI1<44>
KSI3<44>
KSI4<44>

WL_LED#<16,37>
VOL_UP#<44>

LID_SW#<44>
NUMLED#<44>
MUTE_LED<38,46>

+3VALW

ESD

+5VALW

+5VS

ON/OFFBTN#
KSI0
KSI1
KSI3
KSI4
KSO_D_17
WL_LED#
VOL_UP#
VOL_DWN#
LID_SW#
NUMLED#
MUTE_LED

PWR_ACTIVE#
PA_LED_ALW

PR_LED_ALW

+5V

PA_LED
PR_LED

PA_LED_VS
PR_LED_VS

D47

2
3

SM05_SOT23

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

D45

KSI0

1 6

2

KSI1

NUP5120X6T1_SOT563-6

NUMLED#

C795 100P_0402_50V8J

1 2

C796 100P_0402_50V8J

+5VALW +5VS

WL_LED#

LID_SW#
MUTE_LED
PWR_ACTIVE#
PA_LED_ALW
PR_LED_ALW
PA_LED
PR_LED
PA_LED_VS
PR_LED_VS

1 2

C810 0.1U_0402_16V4Z

1 2

C813 0.1U_0402_16V4Z

1 2

C814 0.1U_0402_16V4Z

1 2

C815 0.1U_0402_16V4Z

1 2

C816 0.1U_0402_16V4Z

1 2

C817 0.1U_0402_16V4Z

1 2

C818 0.1U_0402_16V4Z

1 2

C819 0.1U_0402_16V4Z

1 2

C820 0.1U_0402_16V4Z

1 2

C821 0.1U_0402_16V4Z

1 2

KSI3

KSI4

5

KSO_D_17

43

USB_OC#5<29>

USB_OC#4<29>

SPDIFO<38,46>

Compal Secret Data

Deciphered Date

2

USB_OC#5

0_0402_5%

1 2

FBMA-L10-201209-301LMT

220P_0402_25V8K

Title

Size Document Number Rev

Custom

Date: Sheet

Audio board conn

12

+5V

R274

2

G

Q10

1 3

D

S

1

MIC_L<38>

MIC_R<38>

2

MIC_DET<38>
HPDET#<40>
SPKR+<40>
SPKL+<40>

L32

C822

2N7002_SOT23

Compal Electronics, Inc.

KBD,ON/OFF,T/P,LED/B,DEBUG

LA-2841

USB20_P4<29>
USB20_N4<29>

USB20_P5<29>
USB20_N5<29>

SPDIFO_R

MIC_L

MIC_R
MIC_DET

HPDET#
SPKR+
SPKL+

1

+5V

USB20_P4
USB20_N4
OVCUR#4USB_OC#4

USB20_P5
USB20_N5

ACES_87213-2000

42 60Thursday, December 15, 2005

JP9

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

11

11

12

12

13

13

14

14

15

15

16

16

17

17

18

18

19

19

20

20

1.0

of

5

4

3

2

1

For PA For PR

FOR POWER BUTTON B A CKLIGHT SYSTEM POWER FOR POWER BUTTON B A CKLIGHT SYSTEM POWER

D D

C C

PMLED_1#<44>

BATLED_0#<44>

IDE_ACT_LED#

CAPSLED#<44>

R573
220_0402_5%PALED@

PMLED_1#

1 2

R572
220_0402_5%PALED@

BATLED_0#

CAPSLED# CAPSLED# PR_LED_VSPA_LED_VS

CAPSLED# PA_LED_VS

R571
220_0402_5%PALED@

1 2

R86
470_0402_5%D@

1 2

R76
470_0402_5%PALED@

1 2

12

D23

21

HT-170NBQA_0805

D25

21

HT-170NBQA_0805

D24

21

HT-170NBQA_0805

D6

21

HT-170NBQA_0805D@

D4

21

HT-170NBQA_080515.4@

PA_LED_ALW <42,44>

PA_LED_VS <42>

IDE_LED#<28>
ACT_LED#<31>

+5VS

R570
20K_0402_5%

1 2

10K_0402_5%

IDE_LED#
ACT_LED#

+3VS

R568

1 2

0.1U_0402_16V4Z

C830

+5VS

5

U48

1

P

A

2

B

1

2

IDE_ACT_LED#

4

O

G

SN74AHCT1G08DCKR_SC70

3

PMLED_1#

BATLED_0#

R425
560_0402_5%PRLED@

1 2

R426
560_0402_5%PRLED@

R427
560_0402_5%PRLED@

1 2

R92
560_0402_5%PRLED@

1 2

"Right Angle""Vertical"

D13

2

1

3

12-21UYOC/S530-A2/TR8_YEL15.4@

D14

2

1

12

3

12-21UYOC/S530-A2/TR8_YEL15.4@

D15

2

1

3

12-21UYOC/S530-A2/TR8_YEL15.4@

D7

21

17-21UYOC/S530-A2/TR8_ORG15.4@

PR_LED <42>PA_LED <42>

PR_LED_ALW <42>

PR_LED_VS <42>

PR_LED_VS
PA_LED_VS

21

21

1 2

1 2

Q39
MMBT3904_SOT23

3 1

4

D21
HT-110NBQA_0805

R548
330_0402_5%

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/03/10 2006/03/10

Compal Secret Data

Deciphered Date

2

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

INDICATE LED

LA-2841

1

of

43 60Thursday, December 15, 2005

1.0

D20

15.4@

15.4@

560_0402_5%

12

R547

2

B B

CARD_LED<32>

A A

5

17-21UYOC/S530-A2/TR8_ORG

R550
1K_0402_5%

CARD_LED

5

4

3

2

1

LDO3

4.7U_0805_6.3V6K

1

5

CD

RESET

1

R611

TP_DATA

TP_CLK

12

C51
2200P_0603_50V7K~D@

2

12

1 2

J1
JOPEN

10K_0402_5%UMA@

10P_0402_50V8K

R586

1

2

C525

C517

0.1U_0402_16V4Z

12

GM_PM#DET

R587

1

2

4

EC_SMD_2

12

EC_SMC_2

12
12

10K_0402_5%@

12

10K_0402_5%@

EC_SMD_1

12

EC_SMC_1

12

12
12
12

R372
10K_0402_5%

1 2

R402
10K_0402_5%

1 2

R331
10K_0402_5%

1 2

R330
10K_0402_5%

1 2

U47

EC_SMI#
EC_SCI#

FSEL#
FRD#
LID_SW#

N.C.

VCC2GND

3

R382

1 2

47K_0402_5%

100K_0402_5% @

+3VALW

12
12

VOL_UP#

VOL_DWN#

DOCK_VOL_UP#

DOCK_VOL_DWN#

5

D D

G696L263T1UF_SOT23-5@

LDO3

C C

CLK_PCI_EC

12

R399

@

10_0402_5%

1

C556

@

15P_0402_50V8J

2

+3VALW

R337

10K_0402_5%

R338

10K_0402_5%

R400
R397

+5VALW

B B

A A

LDO3

+5V

+3VS

R339

10K_0402_5%

R340

10K_0402_5%

R394

10K_0402_5%

R390

10K_0402_5%

R585

10K_0402_5%@

R335
10K_0402_5%
R336
10K_0402_5%

0.1U_0402_16V4Z

1

C527

C472

2

GATEA20<28>

KB_RST#<28>

SIRQ<29,32,42>

LPC_FRAME#<28,42>

LPC_AD3<28,42>
LPC_AD2<28,42>
LPC_AD1<28,42>
LPC_AD0<28,42>

CLK_PCI_EC<15>

PCI_RST#<27,32,33,36,42>

EC_SCI#<29>

KSI[0..7]<42>

KSO[0..16]<42>

100K_0402_5%G71@

KSO_D_17<42>

EC_SMD_2<4>
EC_SMC_2<4>
EC_SMD_1<45,56>
EC_SMC_1<45,56>

SLP_S4#<29>

PMLED_1#<43>

NUMLED#<42>

BATLED_0#<43>

CAPSLED#<43>

CPUSB#<29,34>

SYSON<34,47,51>

EC_RSMRST#<29>

BKOFF#<16>

SLP_S3#<29>

LID_OUT#<29>

SLP_S5#<29>
EC_SMI#<29>
LAN_RST#<29>
LID_SW#<42>

SUSP#<34,45,47,51,52,54>

PWRBTN_OUT#<29>

PCI_PME#<27,32>

Y7

23
14

32.768KHZ_12.5P_MC-146

CRY1
CRY2

1

2

1

2

KSI[0..7]

KSO[0..16]

C522
10P_0402_50V8K

0.01U_0402_16V7K

1

C512

C551

2

GATEA20
KB_RST#
SIRQ
LPC_FRAME#
LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0
CLK_PCI_EC
PCI_RST#

EC_RST#
EC_SCI#
PA_PR#DET

KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7

KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15
KSO16

KSO_D_17

EC_SMD_2
EC_SMC_2
EC_SMD_1
EC_SMC_1

UTXD
SLP_S4#
PMLED_1#
NUMLED#
BATLED_0#
GM_PM#DET
CAPSLED#

CPUSB#

SYSON
EC_RSMRST#

BKOFF#
SLP_S3#
LID_OUT#
SLP_S5#
EC_SMI#
LAN_RST#
LID_SW#
SUSP#
PWRBTN_OUT#
PCI_PME#

CRY2
CRY1

0.1U_0402_16V4Z

EC DEBUG port

ACES_85205-0400

4

1

1

C550

2

2

0.1U_0402_16V4Z

U24

1

GA20/ GPIO00/GA20

2

KBRST#/GPIO01/KBRST#

3

SERIRQ

5

LPC_FRAME# / LFRAME#

6

LPC AD3/LAD3

9

LPC AD2/LAD2

10

LPC AD1/LAD1

12

LPC AD0/LAD0

14

CLK_PCI_EC/PCICLK

15

PCIRST#

42

EC RST#/ ECRST#

24

EC SCI#/SCI#/GPIO0E

44

PM_CLKRUN#/ CLKRUN#

63

KSI0/GPIO30

64

KSI1/GPIO31

65

KSI2/GPI032

66

KSI3/GPIO33

67

KSI4/GPIO34

68

KSI5/GPI035

69

KSI6/GPIO36

70

KSI7/GPIO37

47

KSO0/GPIO20

48

KSO1/GPIO21

49

KSO2/GPIO22

50

KSO3/GPIO23

51

KSO4/GPIO24

52

KSO5/GPIO25

53

KSO6/GPIO26

54

KSO7/GPIO27

55

KSO8/GPIO28

56

KSO9/GPIO29

57

KSO10/GPIO2A

58

KSO11/GPIO2B

59

KSO12/GPIO2C

60

KSO13/GPIO2D

61

KSO14/GPIO2E

62

KSO15/GPIO2F

89

EC URXD/KSO16/GPIO48

90

EC UTXD/KSO17/GPIO49

88

EC SMD2/ GPIO47/SDA2

87

EC SMC2/GPIO46/SCL2

86

EC SMD1/GPIO44/SDA1

85

EC SMC1/GPIO44/SCL1

34

PCM_SPK#/EMAIL_LED#/ GPIO16

35

SB_SPKR/PWR_SUSP_LED#/ GPIO17

38

PWRLED#/ GPIO19

40

NUMLED#/ GPIO1A

99

BATT CHGI LED#/ E51CS#

101

BATT LOW LED#/ E51MR0

100

CAPS LED#/ E51TMR1

102

ARROW LED#/ E51 INT0

104

SYSON/GPIO56/ E51 INT1

4

EC_RSMRST#/ GPIO02

7

BKOFF#/GPIO03

8

PM SLP S3#/GPIO04

16

EC LID OUT#/GPIO06

17

PM SLP S05#/ GPIO07

18

EC SMI#/GPIO08

19

EC SWI#/GPIO09

20

LID SW#/ GPIO0A

21

SUSP#/GPIO0B

22

PBTN_OUT#/GPIO0C

23

EC PME#/GPIO0D

140

XCLKO

138

XCLKI

KB910LQF_LQFP144

JP20

1
2
3
4

INTERFACE

key Matrix

1
2

UTXD

3
4

Host

scan

LDO5

11

26

VCC/ EC VCC

VCC / EC VCC

SM BUS

GND

GND

129

139

0_0603_5%

VCC / EC VCC37VCC / EC VCC

GND

103

PA_LED_ALW<42,43>

+EC_AVCCLDO3

75

105

127

141

BATTEMP/AD0/GPIO38

VCC

VCC

BATT OVP/AD1/GPIO39

ADP_I/AD2/GPIO3A

AD BID0/AD3/GPIO3B

AD INtput or GPI

EC_AVCC / AVCC

DAC_BRIG/DA0/GPIO3D

PWR

EN DFAN1/DA1/GPIO3D

IREF2/DA2

EN DFAN2/DA3/ GPIO3F

DA output or GPO

FAN/PWM

INVT_PWM/GPIO0F/PWM1

BEEP#/GPIO10/PWM2

OUT BEEP/GPIO12/PWM3

ACOFF/GPIO18/PWM4
FAN SPEED1/GPIO14/FANFB1
FAN SPEED2/GPIO15/FANFB2

PSCLK1
PSDAT1

ADB3/ D3

KBA10/A10
KBA11/A11
KBA12/A12
KBA13/A13
KBA14/A14
KBA15/A15
KBA16/A16
KBA17/A17
KBA18/A18
KBA19/A19

SELIO2#/ GPIO43

SELIO#/ GPIO50

FRD#/RD#

FWR#/WR#

FSEL#/SELMEM#

EC ON/ GPIO1B

AC IN/ GPIO1C

ECTHERM#/GPIO11

ONOFF/GPIO18

PCMRST#/GPIO1E

WL OFF#/GPIO1F

ALI/MH#/GPIO40

FSTCHG/GPIO41

VR ON/ GPIO42
GPIO57/GPIO57
GPIO58/GPIO58
GPIO59/GPIO59

AGND

77

0_0603_5%

ECAGND

0.1U_0402_16V4Z

PSCLK2
PSDAT2
PSCLK3
PSDAT3

ADB0/D0
ADB1/D1
ADB2/D2

ADB4/D4
ADB5/D5
ADB6/D6
ADB7/D7
KBA0/A0
KBA1/A1
KBA2/A2
KBA3/A3
KBA4/A4
KBA5/A5
KBA6/A6
KBA7/A7
KBA8/A8
KBA9/A9

C474

1 2

PS2 interface

Data
BUS

Address

BUS

GND13GND28GND

39

R326

12

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

BATT_TEMP

71

BATT_OVP

72

ADP_IR

73

BID

74

DAC_BRIG

76

EN_FAN1

78

IREF

79
80

INVT_PWM

25

CONA#

27

PGD_IN

30

ACOFF

31

FAN_SPEED1

32

VOL_DWN#

33

91

EXPCRD_RST#

92

PWR_ACTIVE#

93

DOCK_VOL_UP#

94

TP_CLK

95

TP_DATA

96

ADB0

125

ADB1

126

ADB2

128

ADB3

130

ADB4

131

ADB5

132

ADB6

133

ADB7

134

KBA0

111

KBA1

112

KBA2

113

KBA3

114

KBA4

115

KBA5

116

KBA6

117

KBA7

118

KBA8

119

KBA9

120

KBA10

121

KBA11

122

KBA12

123

KBA13

124

KBA14

110

KBA15

109

KBA16

108

KBA17

107

KBA18

106

KBA19

98

NV_ENBKL

84

DOCK_VOL_DWN#

97

FRD#

135

FWR#

136

FSEL#

144

EC_ON

41

ACIN

43

EC_THERM#

29

ON/OFF#

36

VOL_UP#

45

ICH_POK

46

AIR_ACIN

81

FSTCHG

82

VR_ON

83

R365 0_0402_5%

137

CIR_IN

142

EC_MUTE#

143

LDO3

12

+EC_AVCC

R327

2005/03/10 2006/03/10

1 2

1K_0402_5%

ADB[0..7]

KBA[0..19]

12

Compal Secret Data

PA_PR#DET

R579

12

R580
2K_0402_5%

BATT_TEMP <56>
BATT_OVP <49>

DAC_BRIG <16>
EN_FAN1 <4>
IREF <49>
EC_RTCRESET <28>

INVT_PWM <16>

CONA# <46>

PGD_IN <53>
ACOFF <49>
FAN_SPEED1 <4>

VOL_DWN# <42>

ACZ_RST# <28,38>
EXPCRD_RST# <34>
PWR_ACTIVE# <42>

DOCK_VOL_UP# <46>

TP_CLK <42>
TP_DATA <42>

ADB[0..7] <45>

KBA[0..19] <45>

NV_ENBKL <18>

DOCK_VOL_DWN# <46>
FRD# <45>
FWR# <45>

FSEL# <45>
EC_ON <42,50>

ACIN <48,50>
EC_THERM# <29>
ON/OFF# <42>

VOL_UP# <42>

ICH_POK <7,29>

AIR_ACIN <49>

FSTCHG <49>

VR_ON <53>

VGATE <29,53>

CIR_IN <42,46>

EC_MUTE# <40>

Deciphered Date

1 2

R332
10K_0402_5%

1

C463

0.22U_0603_10V7K

2

2

NV_ENBKL

BID definition,
High (3.3V): Before SI2 type D KB(17")
Low (0V): Before SI2 type C KB(15")

2.2V(R325=1K,R333=2K): After PV type D KB(17")

1.65V(R605=2K,R333=2K): After PV type C KB(15")

+3VALW

12

12

R325

R605

C@

ADP_I <49>

R581
100K_0402_5%

1 2

Title

Size Document Number Rev

Custom

Date: Sheet

2K_0402_5%

BID

Compal Electronics, Inc.

EC KB910L(LPC)

LA-2841

D@

1K_0402_5%

12

R333
2K_0402_5%

1

of

44 60Thursday, December 15, 2005

1.0

ADB[0..7]<44>

KBA[0..19]<44>

ADB[0..7]
KBA[0..19]

KBA16
KBA15
KBA14
KBA13
KBA12
KBA11
KBA9
KBA8
FWR#
RESET#

KBA18
KBA7
KBA6
KBA5

KBA3
KBA1

ADB0
ADB1
ADB2
ADB3
ADB4
ADB5
ADB6
ADB7

RESET#

LDO3

1 2

R370

100K_0402_5%

2

C437

0.1U_0402_16V4Z

1

LDO3

LDO3

0.1U_0402_16V4Z @

SN74AHC1G32DCKR_SC70-5 @

2

FWE#

1

C829

KBA0
KBA1
KBA2
KBA3
KBA4
KBA5
KBA6
KBA7
KBA8
KBA9
KBA10
KBA11
KBA12
KBA13
KBA14
KBA15
KBA16
KBA17
KBA18
KBA19

FSEL#<44>

FRD#<44>

FSEL#
FRD#
FWE#

U14

21

A0

20

A1

19

A2

18

A3

17

A4

16

A5

15

A6

14

A7

8

A8

7

A9

36

A10

6

A11

5

A12

4

A13

3

A14

2

A15

1

A16

READY/BUSY#

40

A17

13

A18

37

A19

22

CE#

24

OE#

9

WE#

SST39VF080-70_TSOP40

VCC0
VCC1

RP#

NC0
NC1

GND0
GND1

31
30

25

D0

26

D1

27

D2

28

D3

32

D4

33

D5

34

D6

35

D7

10
11

NC

12
29
38

23
39

JP12

1 2
3 4
5 6
7 8
9 10
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
29 30
31 32
33 34
35 36
37 38
39 40

SUYIN-80065A-040G2T

LDO3

5

U46

1

P

A

4

Y

2

B

G

3

KBA17

KBA19
KBA10
ADB7
ADB6
ADB5
ADB4

ADB3
ADB2
ADB1
ADB0
FRD#KBA4

FSEL#KBA2
KBA0

1 2

R609

LDO3

+3VALW+3VALW

0.1U_0402_16V4Z

EC_SMC_1<44,56>
EC_SMD_1<44,56>

10K_0402_5%@

SUSP#

2

Q53 2N7002_SOT23@

1 3

D

G

EC_FLASH#

S

FWR#

SUSP# <34,44,47,51,52,54>

EC_FLASH# <29>

FWR# <44>

2

U22

8

VCC

7

WP

6

SCL

5

SDA

GND

AT24C16AN-10SI-2.7_SO8

1

C531

12

R366
100K_0402_5%

1

A0

2

A1

3

A2

4

12

R367
100K_0402_5%

1 2

0_0402_5%

R610

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2005/03/10 2006/03/10

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

BIOS & EC I/O Port

LA-2841

of

45 60Thursday, December 15, 2005

1.0

A

1 1

B

DOCK@

1000P_0402_50V7K

C

L30

DOCK@

KC FBM-L18-453215-900LMA90T_1812

1 2

1

C689

2

DOCKVINDOCK_VIN

1

C685

DOCK@

1000P_0402_50V7K

2

D

E

Tampa 2

JP22

1

1

3

3

5

5

7

7

9

9

11

11

13

13

15

15

17

17

19

19

21

21

23

23

25

25

27

27

29

29

31

31

33

33

35

35

37

37

39

39

41

41

43

43

45

45

47

47

49

49

51

51

53

53

55

55

57

57

59

GND

GND

FOX_QL11293-H212CR-FR

1 2

MDO1+
MDO1­JACK_DET#
SPDIFO_L

MUTE_LED
XTPA1+
XTPA1­XTPB1+
XTPB1-

R478

DOCK@

22_0402_5%

SPDIFO<38,42>

1 2

C644

@

1000P_0402_50V7K

+5VS

1

2

MDO1+<35>
MDO1-<35> MDO0+ <35>

JACK_DET#<38>

R479 100_0402_5% DOCK@

MUTE_LED<38,42>

XTPA1+<32>
XTPA1-<32>
XTPB1+<32>
XTPB1-<32>

EMI

2 2

+5V +5V

+3VALW

12

R471

DOCK@

10K_0402_5%

CONA#<44>

DOCK_PRESENT

DOCK_PRES_GND

3 3

2

Q36
MMBT3904_SOT23

3 1

DOCK@

C318

DOCK@

0.1U_0402_16V4Z

+5V

C333
10U_0805_10V4Z

1

2

DOCK@

1

2

1

C295

@

1000P_0402_50V7K

2

DOCK_PRESENT

need change to reverse type connector

2
4
6

8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60

DOCK_PRES_GND

MDO0+
MDO0-

DOCK_MIC
DOCK_LOUT_R

DOCK_LOUT_L
USB20_N1

USB20_P1

TVCOMPS
TVLUMA
TVCRMA

CIR_IN

V_Bat

TVCOMPS <17>
TVLUMA <17>
TVCRMA <17>

CIR_IN <42,44>

DOCKVINDOCKVIN

MDO0- <35>
DOCK_MIC <38>

DOCK_LOUT_R <38>
DOCK_LOUT_L <38>

USB20_N1 <29>
USB20_P1 <29>

V_Bat <48,49>

12

DOCK@

R4951K_0402_5%

R480
200_0402_5%

1 2

1

C647
1000P_0402_50V7K

2

R491
200_0402_5%

1

C681
1000P_0402_50V7K

2

DOCK@

DOCK@

DOCK@

DOCK@

DOCK_VOL_UP# <44>

12

DOCK_VOL_DWN# <44>

4 4

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2005/03/10 2006/03/10

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

D

Date: Sheet

Compal Electronics, Inc.

DOCK CONN

LA-2841

E

1.0

of

46 60Thursday, December 15, 2005

A

1 1

B+

10U_0805_10V4Z

12

R545
330K_0402_5%

2 2

SYSON#

2N7002_SOT23

13

D

2

G

S

Q40

3 3

B+

10U_0805_10V4Z

12

4 4

SUSP

2N7002_SOT23

R398
330K_0402_5%

13

D

2

G

Q21

S

5 5

+2.5VS +1.8V

12

R137

6 6

2N7002_SOT23

470_0402_5%

13

D

SUSP SYSON# SUSP SUSP

2

G

Q5

S

7 7

B

+5VALW to +5V Transfer

+5VALW

U39

8

C758

12

R546
470_0402_5%

1

C755

0.01U_0402_16V7K

2

D

7

1

D

6

D

5

D

2

SI4800DY_SO8

SUSON

+5VALW to +5VS Transfer

+5VALW +5VS

U25

8

1

2

R131
470_0402_5%

2

G

Q4
2N7002_SOT23

R536
470_0402_5%

SUSP

2

G

Q38
2N7002_SOT23

D

7

D

6

D

5

D

SI4800DY_SO8

RUNON

C515

12

R395
470_0402_5%

1

C557

0.01U_0402_16V7K

2

12

13

D

S

+VGA_CORE

12

13

D

S

C

+5V

1

C760
10U_0805_10V4Z

2

1

C561
10U_0805_10V4Z

2

2

G

2

G

0.1U_0402_16V4Z

0.1U_0402_16V4Z

SUSP

1

S

2

S

3

S

4

G

1

S

2

S

3

S

4

G

+1.5VS +VCCP

12

R522
470_0402_5%

13

D

Q37

S

2N7002_SOT23

+0.9VS

12

R68
470_0402_5%

13

D

Q3

S

2N7002_SOT23

D

S

1

C759

2

D

S

1

C552

2

D

S

12

R346
470_0402_5%

13

2

G

Q17
2N7002_SOT23

12

R549
470_0402_5%

13

2

G

Q41
2N7002_SOT23

12

R347
470_0402_5%

13

2

G

Q18
2N7002_SOT23

D

SYSON#

SUSP

C438

10U_0805_10V4Z

C373

G71@

10U_0805_10V4Z

E

+3VALW to +3VS Transfer

+3VALW

U17

8

S

D

7

1

2

D

6

D

5

D

SI4800DY_SO8

S
S

G

+1.8V to +1.8VS Transfer

+1.8V

U5

8

S

D

7

1

2

S

D

6

S

D

5

G

D

SI4800DY_SO8G71@

F

+3VS

1

C459
10U_0805_10V4Z

2

+1.8VS

1

C379

G71@

10U_0805_10V4Z

2

0.1U_0402_16V4Z

G71@

0.1U_0402_16V4Z

1
2
3
4

1
2
3
4

G

12

1

R306

C455

470_0402_5%

2

13

D

SUSPRUNON

2

G

Q11

S

2N7002_SOT23

12

1

R154

C377

G71@

470_0402_5%

2

13

D

SUSPRUNON

2

G

Q7

S

G71@

2N7002_SOT23

1

CF3

CF10

H15
HOLEA

H11
HOLEA

H5
HOLEA

H17
HOLEA

H

FM3

FM1

CF4

CF9

H18
HOLEA

1

CF6

1

CF2

1

H16
HOLEA

1

H4
HOLEA

1

FM2

1

CF12

1

1

CF11

1

1

H19
HOLEA

1

H9
HOLEA

1

1

CF8

1

1

CF5

1

1

H3
HOLEA

1

1

H2
HOLEA

1

1

H10
HOLEA

1

1

1

SYSON<34,44,51>

SUSP<52,55>

SUSP#<34,44,45,51,52,54>

1

CF14

FM5

1

H20
HOLEA

1

H6
HOLEA

CF7

1

1

1

H12
HOLEA

CF1

1

I

FM6

SYSON#

2

G

SUSP

2

G

1

CF13

1

H7
HOLEA

1

H21
HOLEA

B+

B+

FM4

1

1

12

R341
330K_0402_5%

13

D

Q16
2N7002_SOT23

S

12

R406
330K_0402_5%

13

D

Q27
2N7002_SOT23

S

H14
HOLEA

1

H23
HOLEA

H22
HOLEA

1

1

H13
HOLEA

1

H24
HOLEA

1

J

H8
HOLEA

1

8 8

A

B

C

D

Security Classification

Issued Date

THIS SHEET OF EN GINEE RING D RAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

E

2005/03/10 2006/03/10

F

Compal Secret Data

Deciphered Date

G

Title

Size Document Number Rev

Custom

H

Date: Sheet

Compal Electronics, Inc.

DC/DC Circuit

LA-2841

I

1.0

of

47 60Thursday, December 15, 2005

J

5

4

3

2

1

PD27

SBM1040-13_POWERMITE3@

2

DOCK_VIN

12

12

0.22U_1206_25V7K

3.3V

12

PC11

4.7U_0805_6.3V6K

+2.5VSP

+1.5VSP

+1.2VSP

+VGA_COREP

ADPIN

FBM-L18-453215-900LMA90T_1812

12

PC2

PC1

100P_0402_50V8J

1000P_0402_50V7K

PJP27

JUMP_43X39

@

2

112

2

N6

PQ1

TP0610K-T1-E3_SOT23

PU2
G920AT24U_SOT89

3

OUT

PL1

1 2

N58

47_1206_5%

13

GND

1

PJP4
JUMP_43X39@

2

PJP7
JUMP_43X118@

112

PJP9
JUMP_43X118@

112

PJP11
JUMP_43X118@

112

PJP13
JUMP_43X118@

112

PR215

IN

112

2

2

2

2

2

PC3

VIN

12

N5

1 2

12

12

N8

ADPIN2

12

PC4

100P_0402_50V8J

PR11
47_1206_5%

PD4
1N4148_SOD80

PC9

0.1U_0603_25V7K

12

PR17
200_0603_5%

12

PC10
1U_0805_50V4Z

+2.5VS

+1.5VS

+1.2VS

+VGA_CORE

4

PD1
SBM1040-13_POWERMITE3@

12

1000P_0402_50V7K

PR8

1 2

1K_1206_5%

PR10

1 2

1K_1206_5%

PR12

1 2

1K_1206_5%

VS

+1.8VSP

D D

4

3

2

1

PCN1

ACES_88290-0400M

C C

1N4148_SOD80

BATT+

CHGRTCP

100K_0603_1%

PR14

112

112

112

112

112

112

22K_0603_1%

510_0603_5%@

N7

1 2

2

2

2

2

2

2

5

1 2

PR20

47K_0603_1%

EC_PWR_ON#<42>

B B

CHGRTC

+0.9VGAP

+5VALWP

+3VALWP

A A

+1.8VP

+1.05VSP

+0.9VSP

PR19

510_0603_5%@

1 2

PJP5
JUMP_43X118@

PJP6
JUMP_43X118@

PJP8
JUMP_43X118@

PJP10
JUMP_43X118@

PJP12
JUMP_43X118@

PJP14
JUMP_43X118@

PD3

12

PR13

PR256

+0.9VGA

+5VALW

+3VALW

+1.8V

+VCCP

+0.9VS

ADPIN

12

PC8

RTCVREF

12

3

PJP1
JUMP_43X118@

112

PJP2
JUMP_43X118@

112

2
3

PJP15
JUMP_43X118@

112

1

1

2

1

2

PD2

1N4148_SOD80

ACON<49>

+

220U_D2_4VM

PC151

VIN

Vin Detector : Titan

18.234 17.841 17.449

PD31
EC31QS04

B+

12

VL

MAINPWON<50,56>

+1.8VS

12

PC152

4.7U_0805_6.3V6K

V_Bat <46,49>

12

12

PC6

Titan: PR5= 2 2K; PR6= 19.6K
Altima:PR5= 47K; PR6= 27K

0.047U_0603_50V7K

PR15
10K_0402_5%

1 2

PD5

12

RB751V_SOD323

PD6

12

RB751V_SOD323

PR6

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

17.597 17.210 16.813

PR1
1M_0603_0.5%

VIN

12

PR2

82.5K_0603_0.1%
PR5

22K_0603_1%

1 2

12

12

PC7
1000P_0402_50V7K

19.6K_0603_0.1%

2005/03/22 2006/03/22

N9

12

PC13

0.1U_0603_25V7K

LM393M_SO8

VL

Compal Secret Data

1 2

N2N1

3

N3

2

PR9

10K_0402_5%

PR16

1M_0603_0.5%

12

VS

8

5

P

+

7

O

6

-

G

PU1B

4

PR24
10K_0402_5%

Titan: PR21= 200K
Altima:PR21= 300K

Deciphered Date

VS

8

+

-

4

12

N10
N11

12

12

PC5

P

O

G

PU1A
LM393M_SO8

PC14

1000P_0402_50V7K

2N7002_SOT23

12

0.01U_0402_25V7Z

1

RTCVREF

3.3V

2

PZD1

RLZ4.3B_LL34

12

PR21
200K_0603_1%

N12

13

D

S

PQ2

Vin Detector : Altima

14.698 14.285 13.879

13.818 13.411 13.000

VIN

12

PR3
10K_0805_5%

12

B+

12

12

PR23
47K_0402_5%

N13

2

G

13

PR4
1K_0402_5%

1 2

PACIN

12

PR7
10K_0402_5%

PR18
280K_0603_1%

PR22

1.5M_0603_1%

PACIN

12

+5VALWP

2

PQ3
DTC115EUA_SC70

Title

Size Document Number Rev

Custom

Date: Sheet

12

PC12

DCIN / Precharge

LA-2841 1.0

2

2

N4

Detector/Precharge

ACIN <44,50>

PACIN <49>

ACIN: Titan

Precharge detector

14.724 14.333 13.945

13.280 12.933 12.531

ACIN: Altima

Precharge detector

12.384 12.000 11.624

10.927 10.600 10.223

1000P_0402_50V7K

BATT

Precharge detector

7.558 7.333 7.112

6.108 5.933 5.704

1

of

48 60Thursday, December 15, 2005

5

PQ49

AO4407_SO8

VIN

D D

12

PR27

15K_0603_5%

C C

ACON<48>

12

PR248
47K_0402_5%

N65

13

D

2

G

S

PQ52

2N7002_SOT23

2

DTA144EUA_SC70

N64

13

PQ53
DTC115EUA_SC70

PACIN<48>

IREF<44>

IREF=1.096*Icharge

PQ54

ACOFF#

PACIN

47K

2

47K

1 2

174K_0603_1%

8
7

5

1 3

1 2

PD9
1SS355_SOD323

1 2

PR37
3K_0603_5%

PR43

IREF=0.438~3.069V

4

150K_0402_1%

100K_0603_1%

Battery OVP voltage :
4S2P : 18V--> BATT_OVP= 2.0V

B B

(BAT_OVP=0.1112*VMB)

3S2P/3S4P : 13.5V--> BATT_OVP= 2.0V

(BAT_OVP=0.14753 *BATT+)

VS

PU4A
LM358A_SO8

8

P

+

1

22K_0402_5%

0

-

G

4

BATT_OVP<44>

12

A A

PR56

BATT++

12

PR47
340K_0603_1%

12

3
2

N20

12

PC32

PR49
499K_0603_1%

0.01U_0402_25V7Z

N22

12

PR55
105K_0603_0.5%

N21

12

PR57
0_0603_5%

BATT_OVP Select
4S2P PR57 = 0_0603_5%
3S2P/3S4P PR57 = 40.2K_0603_1%

5

4

P2

PQ4
AO4407_SO8

12

1
2
3 6

12

PR28

200K_0402_5%

1
2
36

PC206

0.1U_0603_25V7K

65W==>1.202V
90W==>1.667V

12

PR33

N15

PC22

13

D

2

G

S

PQ8

2N7002_SOT23

65W PR34=31.6K
90W PR34=20.0K

12

PR44

12

PC33

0.01U_0402_25V7Z

4

V_Bat<46,48>

1 2

65W Iadp=0~3.0A
90W Iadp=0~4.2A

P3

8
7

5

4

65W:1.40V(-1 level); 1.30V (+1 level)
90W:2.05V(-1 levle); 1.83V (+1 level)

12

12

10K_0402_1%

PR36

ADP_I<44>

12

2200P_0402_25V7K

PR34

31.6K_0603_1%

5.0V

12

PC24

0.1U_0402_16V7K

12

PC31

0.1U_0402_16V7K

PQ9

DTC115EUA_SC70

N14

0.1U_0402_16V7K

PR26

0.02_2512_1%

PR32

10K_0402_1%

PC21

N16

1 2

1 2

N17

1 2

1 2

PC25
1500P_0402_50V7K

PR41
10K_0603_1%

AIR_ACIN<44>

3887CS

13

12

PR38
1K_0603_1%

PD32

EC31QS04

12

3887+INE2

3887-INE2

3887FB2

PR35

6.8K_0402_1%

3887VREF

3887FB1

3887-INE1

3887+INE1

3887OUTC1

12

3887OUTD

PU3

1

-INC2

2

OUTC2

3

+INE2

4

-INE2

5

FB2

6

VREF

7

FB1

8

-INE1

9

+INE1

10

OUTC1

11

OUTD

12

-INC1

MB3887_SSOP24

PR45

49.9K_0603_0.1%

3

B+

PL18

FBM-L18-453215-900LMA90T_1812

1 2

24

+INC2

23

GND

3887CS

22

CS

3887VCC

21

VCC(o)

3887OUT

20

OUT

3887VH

19

VH

0.1U_0603_25V7K

18

VCC

3887RT

17

RT

3887-INE3

16

-INE3

3887FB3

15

FB3

ACON

14

CTL

3887+INC1

13

+INC1

12

PC23

1 2

PR39

1 2

68K_0603_5%

1 2

47K_0603_1%

12

PC15

PR30

2.2_0603_5%

1 2

1 2

1 2

PC20

0.1U_0603_25V7K

PC26 0.1U_0603_25V7K

1 2

PR42

N18

1 2

PC27

1500P_0402_50V7K

4.2V

12

12

PC16

4.7U_1206_25V6K

4.7U_1206_25V6K

PC19 2200P_0402_50V7K

12

PC17

0.1U_0603_25V7K

PD10

EC31QS04

PR46
150K_0603_0.1%

2

B++

PC18

2200P_0402_50V7K

36

241

PQ6
AO4407_SO8

578

N19

15U_PLFC1045P-150A_3.7A_20%

1 2

12

12

12

PD11
EC31QS04

CC=0.4~2.8A

BATT_Charge Voltage Select
4S2P CV=16.8V PR45 = 49.9K_0603_0.1% PR46 =150K_0603_0.1%
3S2P/3S4P CV=12.6V PR45 = 150K_0603_0.1% PR46=300K_0603_0.1%

PU4B

PR51

4.22K_0603_1%

PR53
10K_0603_5%

N24

12

2

12

12

PZD2

RLZ4.3B_LL34

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

LM358A_SO8

+

7

0

-

2005/03/22 2006/03/22

5
6

N23
N25

PR54

10.2K_0603_1%

1 2

PR50
10K_0603_5%

12
12

PR52

(17V+-5%)

42.2K_0603_1%

Compal Secret Data

RTCVREF
VIN

FSTCHG<44>

Deciphered Date

2

1

+

2

PL2

1

Charger

PC209

100U_25V_M

+3VALWP

2

1
2
3 6

ACOFF#

12

PR40

0.02_2512_1%

12

PR48
47K_0603_5%

N26

2

13

Title

Size Document Number Rev

Custom

Date: Sheet

G

PQ11
DTC115EUA_SC70

Charger

LA-2841 1.0

PQ5

4

AO4407_SO8

DIS

12

PR31
10K_0603_5%

13

PC28

4.7U_1206_25V6K

13

D

S

8
7

5

PR29

1 2

47K_0603_5%

2

PQ7
DTC115EUA_SC70

12

12

PC30

PC29

4.7U_1206_25V6K

3887CS

PQ10
2N7002_SOT23

1

VIN

ACOFF <44>

12

4.7U_1206_25V6K

BATT+

of

49 60Thursday, December 15, 2005

5

4

3

2

1

B+

D D

C C

B B

A A

1

PJP25

1

JUMP_43X118

@

2

2

B+++

12

PC181

4.7U_1206_25V6K

12

12

PC183

PC182

2200P_0402_50V7K

4.7U_1206_25V6K

10U_LF919AS-100M-P3_4.5A_20%

PL16

PQ41

1

G2

D2

2

D2

D1/S2/K

3

G1

D1/S2/K

4

D1/S2/K

S1/A

AO4912_SO8

12

+5VALWP

1999_V+

1

+

PC192

2

2 1

150U_D2E_6.3VM_R18

PR226

10.2K_0402_1%@

1 2

PD25

PR227

SKUL30-02AT_SMA@

PR229

0_0402_5%

1 2

47K_0402_5%

MAINPWON<48,56>

0.1U_0603_25V7K

8
7
6
5

DL5

12

12

PC193
1U_1206_25V7K

@

PR234

0_0402_5%

PC179

0_0402_5%

DH5A

1 2

12

0.047U_0603_16V7K

12

PR216

LX5

1999_SHDN

BST5B BST3B

LDO5

DH5

PR217
0_0402_5%

1 2

PR241

0_0805_5%

VL

12

PC190

4.7U_0805_6.3V6K

BST5A

PR258 0_0402_5%@

2REF_1999

1 2

1 2

ACIN<44,48>

PR257 0_0402_5%

PR228

10K_0402_5%

ACIN

2VREF_1999

1 2

1999_SKIP

2REF_1999

VL

12

1999_ON

PR233

806K_0603_1%

12

PC197

13

D

2

G

S

PQ46

RHU002N06_SOT323

12

PR251

PQ47

RHU002N06_SOT323

12

0_0805_5%

@

+5VALWP

FB5

PC195

LDO3P

1 2

13

D

S

VS

PR255

0_0805_5%@

1 2

12

PR239

10_1206_5%

PC188

14

BST5

16

DH5

15

LX5

19

DL5

21

OUT5

9

FB5

1

N.C.

6

SHDN#

4

ON5

3

ON3

12

SKIP#

8

REF

12

0.22U_0603_16V7K

PR242
100K_0402_5%

N60

ACIN

2

G

P2

DAP202U_SOT323

PR254

0_0805_5%

1 2

1999_V++

12

PR219

12

1999_V+

4.7U_1206_25V6K

20

18

V+

LD05

PU5

MAX8734EEI_QSOP28

GND

23

D

S

PQ48

RHU002N06_SOT323

10_1206_5%

0.1U_0603_25V7K

PC191

12

13

TON

LDO3

25

LDO3P

12

PC196

13

G

1 2

1999_VCC

17

VCC

PGOOD

PRO#

10

4.7U_0805_6.3V6K

2

PD24

PR218

47_0402_5%

1 2

ILIM3

ILIM5
BST3

DH3

DL3
LX3

OUT3

FB3

1999_PRO

2

3

1

12

PC184

0.1U_0402_16V7K

2VREF_1999

PC189

1U_0603_10V6K

ILIM3

5

ILIM5

11
28

26
24
27
22

FB3

7
2

PR231

0_0402_5%

1 2

+3VALWP

EC_ON <42,44>

VL

PR221

1 2

1 2

118K_0402_1%

PR224

1 2

1 2

499K_0402_1%

BST3A

1 2

PR240

0_0805_5%

1 2

PR252

0_0805_5%@

PR222

200K_0402_1%

PR225

499K_0402_1%

1 2

PC180

0.1U_0603_25V7K

12

PR220
0_0402_5%

DH3

LDO3

B+++

12

12

12

PC186

4.7U_1206_25V6K

PR223

0_0402_5%

PC187

2200P_0402_50V7K

1 2

DL3

PC185

4.7U_1206_25V6K

+3.3VALWP/+5VALWP

PQ42

1

D2

2

D2

3

G1

4

S1/A

AO4912_SO8

DH3A

LX3

1 2

1 2

D1/S2/K
D1/S2/K
D1/S2/K

PR230

3.57K_0402_1%@

PR232

0_0402_5%

8

G2

7
6
5

12

PL17

10U_LF919AS-100M-P3_4.5A_20%

1

+

PD26

PC194

2

2 1

SKUL30-02AT_SMA@

150U_D2E_6.3VM_R18

+3VALWP

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/03/22 2006/03/22

Compal Secret Data

Deciphered Date

Title

+3V/+5V

Size Document Number Rev

LA-2841 1.0

Custom

2

Date: Sheet

1

of

50 60Thursday, December 15, 2005

5

4

3

2

1

D D

12

PC60

4.7U_1206_25V6K

UG1.8A

12

PC61

2200P_0402_50V7K

PC65

0.1U_0603_25V7K

0.1U_0402_16V7K@

4.7U_0805_6.3V6K

12

PC70

VOUT1.8
VSEN1.8

EN1.8

2

BOOT1.8A

12

1 2

PR87
0_0402_5%

1 2

PR93

2.43K_0603_1%

1 2

PC78

1

PD17

DAP202U_SOT323

3

BOOT1.5A

PC68

0.01U_0402_25V7Z

SOFT1.8

12

12

PR85
0_0402_5%

BO0T1.8

6

UG1.8 UG1.5

5

PHASE1.8

12

4

ISEN1.8

7

LG1.8

2

3

9

10

8

15

OC1.8 OC1.5

11

12

PR101

73.2K_0603_1%

12

PC59

4.7U_1206_25V6K

D8D7D6D

S1S2S3G

D8D7D6D

S1S2S3G

5

4

5

4

1 2

0_0402_5%

PR95

PQ16

C C

B B

+1.8VP

4.7UH_PLC1045P-4R7A_5.5A_30%

1

12

+

PC75

4.7U_0805_6.3V6K

2

PC74

220U_D2_4VM_R25

PR89

10.5K_0402_1%

PR97

10K_0402_1%

12

12

PC76

0.01U_0402_25V7Z

12

1 2

12

PR90

0_0402_5%

PR98

0_0402_5%@

PL4

1 2

SI4800BDY_SO8

PQ17

SI4800BDY_SO8

SYSON<34,44,47> SUSP# <34,44,45,47,52,54>

PR83

51_1206_5%

12

PC66

0.1U_0603_25V7K

PU6

SOFT1

BOOT1

UGATE1
PHASE1

ISEN1
LGATE1

PGND1

VOUT1
VSEN1
EN1
PG1A

OCSET1

12

ISL6227A_VIN

14

VIN

GND

1

+5VALWP

1 2

ISL6227A_VCC

28

ISL6227BCA-T_SSOP28

13

IS6227A_B+

PR84

2.2_0603_5%

SOFT2

VCC

BOOT2

UGATE2
PHASE2

ISEN2

LGATE2

PGND2

VOUT2

VSEN2

EN2

PG2/REFA

OCSET2

DDR

PC67

2.2U_0805_10V6K

1 2

0.01U_0402_25V7Z

SOFT1.5

17

BOOT1.5

23

24

PHASE1.5

25

ISEN1.5

22

LG1.5

27

26

20
19
21
16

18

PC69

PR86
0_0402_5%

1 2

1 2

2.43K_0603_1%

1 2

VOUT1.5
VSEN1.5
EN1.5

12

PR102

73.2K_0603_1%

12

PR88
0_0402_5%

PR94

PC71

0.1U_0603_25V7K

12

UG1.5A

12

PC79

0.1U_0402_16V7K@

1 2

PR96

0_0402_5%

5

4

5

4

+1.8VP/+1.5VALWP/+2.5VS

PJP18

JUMP_43X118@

2

112

12

12

PC62

4.7U_1206_25V6K

PQ58

D8D7D6D

SI4800BDY_SO8

S1S2S3G

PL5

3.3UH_PLC1045P-3R3A_6.1A_30%

1 2

D8D7D6D

PQ59

SI4810DY-T1-E3_SO8

S1S2S3G

PC63

4.7U_1206_25V6K

PC64

12

PR91

0_0402_5%@

12

PR99

0_0402_5%

12

2200P_0402_50V7K

12

12

PC77

PR92

0.01U_0402_25V7Z

6.81K_0402_1%

12

PR100

10K_0402_1%

B+

+1.5VSP

1

12

+

2

PC73

220U_D2_4VM

PC72

4.7U_0805_6.3V6K

(400mA,40mils ,Via NO.= 1)

PJP19

JUMP_43X39@

6
2

1

N32SUSP#

PC83

112

PQ18

D

2

S

45

G

3

12

+3VS

SI3456DV-T1_TSOP6@

PR103

A A

47K_0603_5%@

1 2

0.1U_0603_25V7K@

5

VIN2.5

APL5508_SOT89

PU7

2

IN

12

PC80

1U_0603_10V6K

OUT

GND

1

4

+2.5VSP

3

12

12

PC82

PC81

10U_1206_25VAK

4.7U_0805_6.3V6K

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/03/22 2006/03/22

Compal Secret Data

Deciphered Date

Title

1.8V/1.5V/2.5V

Size Document Number Rev

LA-2841 1.0

Custom

2

Date: Sheet

1

of

51 60Thursday, December 15, 2005

5

4

3

MAX8575_B+

2

FBM-L18-453215-900LMA90T_1812

PL6

1 2

1

B+

+1.05V_VCCPP/+0.9VSP

12

PC88

+1.8VP

12

12

PR115
1K_0402_1%

12

PC86

0.01U_0402_25V7Z

MAX8575_SS

12

FB1.05

MAX8578_VCC

PC91

4.7U_0805_6.3V6K

VIN0.9

VREF0.9

PR104

6.81K_0402_1%

MAX8575_OCSET

PU8

10

OCSET

2

SS

1

FB

3

VCC

4

12

GND

MAX8578EUB_10UMAX

12

PC96

0.1U_0402_16V7K

Security Classification

PD18

1SS355_SOD323

PU9

VIN1VCNTL

2

GND

3

VREF

4

VOUT

APL5331KAC-TR_SO8

12

D D

3300P_0402_50V7K

1 2

+5VS

2

2

1

1

12

13

D

PQ21
2N7002_SOT23

S

PR107
0_0402_5%

PJP20

JUMP_43X118@

PR113

1K_0402_1%

C C

12

PR110

866_0402_1%

B B

PR114

510K_0402_5%

SUSP<47,55>

A A

1 2

PR253

12

510K_0402_5%

PC94

10U_1206_6.3V7K

2

G

12

PC97

@

0.1U_0402_16V7K

+1.8V

BST

12

PC98

DH

IN

LX
DL

10U_1206_6.3V7K

9
8
7
5
6

MAX8575_IN

DH1.05
LX1.05
DL1.05
BST1.05

NC
NC
NC

TP

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

PR105
0_0402_5%

1 2

12

PC87

0.1U_0603_16V7K@

PR106
0_0402_5%

1 2

PC89

0.1U_0603_25V7K

6
5
7
8
9

+0.9VSP

DH1.05A

12

1 2

4.7_0402_5%

1 2

SUSP# <34,44,45,47,51,54>

PQ19

PQ20

DL1.05A

PR111

+3VALW

PC95

1U_0603_16V6K

SI4810BDY_SO8

5

SI4800BDY_SO8

4

5

4

Compal Secret Data

2005/03/22 2006/03/22

3

Deciphered Date

1

12

PC85

PC84

10U_1206_25V6M

D8D7D6D

S1S2S3G

D8D7D6D

S1S2S3G

0.1U_0603_25V7K

2

3.3UH_PLC1045P-3R3A_6.1A_30%

12

PR108

7.15K_0402_1%

0.047U_0603_25V7M

PL7

1 2

1 2

PC92

1 2

PR112

750_0603_1%

2

12

PR109

30_0402_5%

N33

12

PC93

0.1U_0402_10V6K

+1.05VSP

1

12

+

PC90

PC201

4.7U_0805_6.3V6K

Title

Size Document Number Rev

Date: Sheet

2

330U_D2_2.5VM

1.05V/0.9V

of

52 60Thursday, December 15, 2005

1

1.0

8

7

6

5

4

3

2

1

+CPU_B+

H H

+CPU_B+

PR116
10_0603_5%

4
3
5
6

28
29
30
31
32
33
34

37
36

1

2
38
35
12
13

11

10

9

8

VR_TT#
RBIAS
NTC
SOFT

VID0
VID1
VID2
VID3
VID4
VID5
VID6

DPRSTP#
DPRSLPVR
PSI#
PGD_IN
CLK_EN#
VR_ON
VSEN
RTN

VDIFF

FB

COMP

VW

12

0.01U_0402_25V7K
PC106

19

20

VSS

VDD

PU11

DROOP

14

ISL6260_DROOP

PR166

12

PC136

330P_0402_50V7K

1 2

ISL6260_VIN

39

18

VIN

DFB15VO

ISL6260_DFB

1K_0402_1%

12

6

+3VS

PR124

1.91K_0603_1%

1 2

ISL6260_PGOOD

40

ISL6260CRZ-T_QFN40

3V3

PGOOD

PWM1

ISEN1

PWM2

ISEN2

FCCM

PWM3

ISEN3

OCSET

VSUM

16

VO

PR167

PR236

0_0402_5%@

27

23

26

22

24

25

21

7

17

PR159

4.53K_0402_1%

12

12

12

PC208

1U_0603_10V6K@

ISL6260_PWM1

ISL6260_ISEN1

ISL6260_PWM2

ISL6260_ISEN2

ISL6260_FCCM

ISL6260_PWM3

ISL6260_ISEN3

ISL6260_OCSET

VSUM

12

1 2

PC130

0.22U_0603_16V7K

12

PC200

0.1U_0402_16V7K

12

PC134

VGATE <29,44>

PR147

0_0402_5%

12

12

PR151

0_0402_5%

PR152

11.5K_0402_1%

PC129

1 2

1000P_0402_50V7K

@

12

0.1U_0402_16V7K

PH2

10KB_0603_5%_ERTJ1VR103J

+5VS

12

12

PR158

3K_0402_1%

N35

12

PR165

1K_0402_1%@

5

G G

+5VS

10_0603_5%

PR121

1 2

ISL6260_VDD

12

PH1

12
12
12
12

PR141

PR145

PR148

12

PC199

12

68.1K_0402_1%

12

PC133

12

7

PC109

1U_0603_10V6K

ISL6260_VRTT
ISL6260_RBIAS
ISL6260_NTC

12

ISL6260_SOFT

ISL6260_VID0
ISL6260_VID1
ISL6260_VID2
ISL6260_VID3
ISL6260_VID4
ISL6260_VID5

ISL6260_VID6
ISL6260_DPRSTP
ISL6260_DPRSLPVR

12

ISL6260_PSI
ISL6260_PGD

12

ISL6260_CLK
ISL6260_VRON

12

ISL6260_VSEN

1 2

PR156

0_0402_5%

12

PR160

12

12

PR125

ISL6260_RTN

ISL6260_VCIFF

12

ISL6260_FB

ISL6260_COMP

N59

0_0402_5%

ISL6260_VW

6.19K_0603_1%

F F

PC110

0.01U_0402_25V7Z

ISL6260_NTC

12

H_PROCHOT#<4>

E E

CPU_VID0<5>
CPU_VID1<5>
CPU_VID2<5>
CPU_VID3<5>
CPU_VID4<5>
CPU_VID5<5>
CPU_VID6<5>

H_DPRSTP#<4,28>

DPRSLPVR<7,29>

PR154

CLK_ENABLE#<15>

+CPU_CORE

PR150 10_0402_1%@

0_0402_5%

12

8

H_PSI#<5>

PGD_IN<44>

VR_ON<44>

PR149 0_0402_5%

PR153

D D

VCCSENSE<5>

VSSSENSE<5>

C C

10_0402_1%@

B B

A A

PR128

4.22K_0402_1%

12

12

12

12

PR155

180_0603_1%

1 2

220P_0402_25V8K

150K_0402_5%

12

0.022U_0402_16V7K

1800P_0402_50V7K

N45

PC132

PR127

12

N56

PC116

12

PR131

0_0402_5%

PR133

0_0402_5%

PR135

0_0402_5%

PR139

0_0402_5%

PR142

0_0402_5%

PR146

0_0402_5%

1000P_0402_50V7K

PC126

1 2

1 2

0.022U_0402_16V7K

0_0402_5%

12
12
12

0.082U_0603_25V7K

1000P_0402_50V7K

PC128

PR126

470KB_0402_5%_ERTJ1VR103J

PR130

0_0402_5%

PR132

0_0402_5%

PR134

0_0402_5%

PR137

0_0402_5%

12

499_0402_1%

12

0_0402_5%

12

0_0402_5%

PC120

PC121

N34

PR157

1 2

1.2K_0402_1%

N57

1000P_0402_50V7K

PR164

6.98K_0402_1%

+5VS

12

PC104

PU10

1U_0603_16V6K

5

VCC

6

FCCM

2

PWM

3

GND

ISL6208CRZ-T_QFN8

+5VS

PC115

PU12

5

VCC

6

FCCM

2

PWM

3

GND

ISL6208CRZ-T_QFN8

Security Cl assification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVIS ION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INF ORMATION IT CONT AINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WR ITT EN CO NSE NT OF COMPAL ELECTRONICS, INC.

PR117

2.2_0603_5%

N36

1

BOOT

8

UGATE

7

PHASE

4

LGATE

12

1U_0603_16V6K

N38

1

BOOT

8

UGATE

7

PHASE

4

LGATE

4

PC105

0.22U_0603_10V7K

N37

1 2

12

PR235

0_0603_5%

12

6208A_LG

N39

12

PR237

0_0603_5%

6208B_LG

PC117

0.22U_0603_10V7K

1 2

12

PR129

2.2_0603_5%

2005/03/22 2006/03/22

PQ22

6208A_UGA6208A_UG

5

PQ23

4

SI4856ADY-T1-E3_SO8

6208B_UGA6208B_UG

5

PQ26

4

SI4856ADY-T1-E3_SO8

Compal Secret Data

5

S

4

2

SI4684DY-T1-E3_SO8

D8D7D6D

S1S3G

S

2

5

PQ25

4

SI4684DY-T1-E3_SO8

D8D7D6D

S1S3G

S

2

Deciphered Date

PQ24

2

D8D7D6D

S1S3G

S

3

SI4856ADY-T1-E3_SO8

PQ27

PQ43

SI4684DY-T1-E3_SO8

5

4

2

D8D7D6D

PQ45

S1S3G

5

4

SI4856ADY-T1-E3_SO8

12

12

PC100

PC101

0.1U_0603_25V7K
2200P_0402_50V7K

5

D8D7D6D

S1S3G

S

4

2

CPU_PHASE1

D8D7D6D

4.7_1206_5%

PR119

1 2

S1S3G

S

N42

12

PC108

680P_0603_50V8J

5

D8D7D6D

PC111

S1S3G

S

4

2

SI4684DY-T1-E3_SO8

CPU_PHASE2

D8D7D6D

4.7_1206_5%

PR138

1 2

S1S3G

S

2

N43

12

PC119

680P_0603_50V8J

12

PC102

4.7U_1206_25V6K

12

PC112

0.1U_0603_25V7K

12

PC103

10U_1206_25VAK

0.36UH_MPC1040LR36_24A_20%

10K_0402_1%

1 2

PR122

5.11K_0603_1%

1 2

VSUM

12

PC113

4.7U_1206_25V6K

2200P_0402_50V7K

1 2

PL8

FBM-L18-453215-900LMA90T_1812

1 2

1

+

PL9

1 2

PR120

12

12

PC114

10U_1206_25VAK

0.36UH_MPC1040LR36_24A_20%

PR140

10K_0402_1%

1 2

PR143

5.11K_0603_1%

VSUM

Title

Size Docu me n t N u m ber Re v

C

Date: Sheet

2

2

PC107

0.22U_0603_10V7K

12

PR123

12

NC@

+CPU_B+

PL10

1 2

PC118

0.22U_0603_10V7K

PR144

NC@

Compal Electronics, Inc.

CPU CORE

B+

PC99

100U_25V_M

PR118
10_0402_1%

1 2

VO

1 2

12

12

VO

CPU_CORE

PR136
10_0402_1%

1

+CPU_CORE

+CPU_CORE

53 60Thursday, D e cember 15, 2005

1.0

of

5

4

3

2

1

+VGA_COREP/+1.8VSP

D D

PJP21

JUMP_43X118@

2

12

12

PC143

2200P_0402_50V7K

12

12

PC157

PR179

0_0402_5%

PR180

0.01U_0402_25V7Z

12

PR188

0_0402_5%@

PR189

SUSP# <34,44,45,47,51,52>

112

12

10.2K_0402_1%

12

10K_0402_1%

B+

+1.8VSP

+1.8VS

12

12

PC138

4.7U_1206_25V6K

12

PC140

PC139

2200P_0402_50V7K

4.7U_1206_25V6K

PR171

51_1206_5%

12

12

1

PC144

5

D8D7D6D

S1S2S3G

4

C C

+VGA_COREP

1.4UH_SSF-13056-1R4_15.5A_+-20%

PL12

PQ32

SI4800DY-T1-E3_SO8

32

5

D8D7D6D

S1S2S3G

4

PQ33

SI4810DY-T1-E3_SO8

EN_VGA

1 2

12

PR178

0_0402_5%@

PR187

0_0402_5%

1

12

PC155

4.7U_0805_6.3V6K

B B

1

+

+

PC153

PC154

2

2

330U_D2_2.5VM

330U_D2_2.5VM@

PR177

2.26K_0402_1%

PR186

12

12

PC156

0.01U_0402_25V7Z

12

10K_0402_1%

5

D8D7D6D

PQ34

SI4810DY-T1-E3_SO8

S1S2S3G

4

SUSP# EN_VGACORE

1 2

PR184

0_0402_5%@

EN_VGA

1 2

PR192

0_0402_5%

4.7U_0805_6.3V6K

PC149

0.1U_0603_25V7K

0.1U_0402_16V7K@

2

BOOT_VGA

12

VOUT_VGA
VSEN_VGA

PC158

PD22

DAP202U_SOT323

3

PC147

0.01U_0402_25V7Z

12

PR173
0_0402_5%

1 2

PR175
0_0402_5%

1 2

PHASE_VGA

PR181

1.33K_0603_1%

1 2

12

BOOT_V1.8

SOFT_VGA

N49 N50

UG_VGA

ISEN_VGA
LG_VGA

OC_VGA

12

PR190
68K_0603_1%

12

PC145

0.1U_0603_25V7K

ISL6227B_VIN

14

PU14

12

SOFT1

VIN

6

BOOT1

5

UGATE1

4

PHASE1

7

ISEN1

2

LGATE1

3

PGND1

9

VOUT1

10

VSEN1

8

EN1

15

PG1B

11

OCSET1

GND

1

+5VALWP

1 2

ISL6227B_VCC

28

ISL6227BCA-T_SSOP28

13

IS6227B_B+

PR172

2.2_0603_5%

SOFT2

VCC

BOOT2

UGATE2

PHASE2

ISEN2

LGATE2

PGND2

VOUT2
VSEN2

PG2/REFB

OCSET2

DDR

PC146

2.2U_0805_10V6K

1 2

17

23

24
25

22
27

26

20
19
21

EN2

16
18

68K_0603_1%

PC148

0.01U_0402_25V7Z

SOFT_V1.8

PR174
0_0402_5%

1 2

UG_V1.8

1 2

PHASE_V1.8

1.33K_0603_1%

ISEN_V1.8

1 2

LG_V1.8

VOUT_V1.8
VSEN_V1.8

1 2

OC_V1.8

12

PR191

12

PR176
0_0402_5%

PR182

PR250

0_0402_5%@

PC150

0.1U_0603_25V7K

12

UG_V1.8AUG_VGAA

EN_VGA

13

D

G

S

PQ55

RHU002N06_SOT323

12

PC141

PC142

4.7U_1206_25V6K

4.7U_1206_25V6K

PQ31

AO4912_SO8

8

G2

7

D1/S2/K

6

D1/S2/K

5

D1/S2/K

S1/A

1

D2

2

D2

3

G1

4

PL13

3.3UH_PLFC0745-3R3_4.8A_30%

1 2

1 2

PR183

0_0402_5%@

1 2

PR185

100K_0402_5%

SUSP# <34,44,45,47,51,52>

+3VALWP

EN_VGA# <55>

2

1 2

PR249

100K_0402_5%

13

D

2

G

S

PQ56

12

RHU002N06_SOT323

1 2

0_0402_5%

PC159

0.1U_0402_16V7K@

+3VALWP

PR193

A A

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/03/22 2006/03/22

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

LA-2841 1.0

Custom

2

Date: Sheet

1

of

54 60Thursday, December 15, 2005

5

4

3

2

1

+5VALW

2

2

PJP22

D D

1

2

PC161

2200P_0402_50V7K

C C

JUMP_43X39@

1

1

1

2

PC162

22U_1206_6.3V6M

PC203

PQ51

2SA1036K_SOT23

1 2

1 2

N63

22U_1206_6.3V6M

12

31

E

C

PD28
RB751V_SOD323

PR245

1K_0603_5%

N61

2

B

LM393M_SO8

VIN_V1.2

PU15B

7

12

1

C

2

B

E

O

3

N62

VS

8

4

PR244

PQ50

10K_0402_5%

HMBT2222A_SOT23

PU15A

LM393M_SO8

5

P

+

6

-

G

D

S

4 5

G

3

D

S

4 5

1

6
2

1

G

PQ57

3

SI3445DV_TSOP6

VS

8

P

+

O

-

G

4

PC205

4700P_0402_25V7K

6

PQ36

SI3445DV_TSOP6@

2
1

PL14

PHASE_V1.2

PD29

EC31QS04

12

PC204

0.1U_0603_25V7K

3
2

12

12

PC210

5UH_SPC-06704-5R0A GP_2.9A_30%

1 2

12

12

PD30

EC31QS04

@

FB_V1.2
REF_V1.2

12

PR247
499K_0402_1%

22P_0402_50V8J

12

PQ37

SN7002N_SOT23

13

D

S

12

PR243

191K_0402_1%

N46

2

G

PC202

470P_0402_50V8J@

PR246

330K_0402_1%

1 2

1 2

PR196

0_0402_5%

12

+1.2VSP/+0.9VSP

+1.2VSP

1

+

PC166

2

10U_1206_6.3V7K

2VREF_1999

220U_D2_4VM

PC165

EN_VGA# <54>

+1.8VS

B B

2

PJP24

2

JUMP_43X118@

1

1

12

PC169

10U_1206_6.3V7K@

PR202

0_0402_5%@

SUSP<47,52>

A A

1 2

0.1U_0402_16V7K@

PC172

N48SUSP

2

G

12

PR201

1K_0402_1%@

13

D

PQ39

S

2N7002_SOT23@

VIN_V0.9

12

VREF_V0.9

12

PR203

12

PC171

1K_0402_1%@

0.1U_0402_16V7K@

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

APL5331KAC-TR_SO8@

VIN1VCNTL

2

GND

3

VREF

4

VOUT

12

PC173

PU16

10U_1206_6.3V7K@

6
5

NC

7

NC

8

NC

9

TP

+0.9VGAP

2005/03/2 2006/03/22

3

+3VALW

1 2

PC170

1U_0603_16V6K@

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

Compal Electronics, Inc.

VGA1.2V/VGA0.9V

55 60Thursday, December 15, 2005

1

1.0

of

5

D D

BATT++ BATT+

4

3

2

1

Battery Connect/OTP

BATT+

12

PC175

0.01U_0402_25V7Z

EC_SMD_1 <44,45>
EC_SMC_1 <44,45>

BATT_TEMP <44>

+3VALWP

PC177

0.22U_0603_16V7K

CPU

PR210

0_0402_5%

12

PH1 under CPU botten side :

CPU thermal protection at 90 +-3 degree C
Recovery at 50 +-3 degree C

VL

12

PH3
100K_0603_1%_TH11-4H104FT

N53

12

PR211

215K_0603_1%

N52

1 2
1 2

VL

PR212

470K_0402_1%

12

PR213
20K_0603_1%

470K_0402_1%

PR214

470K_0402_1%

N54

OTPREF

12

PR208

1 2

3

+

2

-

12

PC178
1000P_0402_50V7K

VS

8

PU17A

P

O

G

LM393M_SO8

4

12

PC176

0.1U_0603_25V7K

1

VS

VL

<48,50>

MAINPWON

12

PR209
470K_0402_1%

13

N55

D

PQ40

2

2N7002_SOT23

G

S

1 2

PR206

1K_0402_5%

1 2

PR207

6.49K_0402_1%

12

BATT_TEMP

PL15
FBM-L18-453215-900LMA90T_1812

12

PC174
1000P_0402_50V7K

PCN2

1

BATT+

SMD
SMC

Res

8

Temp

C C

G

7

GND6G

SUYIN_200045MR006G110ZR

SMD

2

SMC

3
4

TS

5

PR204

100_0402_5%

1 2
1 2

PR205

100_0402_5%

PJPB1 battery connector

SMART
Battery:

1.BATT+

2.SMBD

3.SMBC

4.Res

5.Temp

6.GND

B B

8

PU17B

5

P

+

7

O

6

-

G

LM393M_SO8

4

A A

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/03/01 2006/03/01

Compal Secret Data

Deciphered Date

Title

BATTERY CONN

Size Document Number Rev

LA-2841 1.0

Custom

2

Date: Sheet of

1

56 60Thursday, December 15, 2005

1

2

3

4

5

Version change list (P.I.R. List) Page 1 of 1

Modify listItem

Add R579 and R580 for EC PA/PR detec EC team request P44

1

BOM del C591 220U_D2 for +VCCP bypass capacitance Cost down P6Rev0.2

2

U44 pin5 change from +5VAMP to +5V Design modify

3

U44 pin3 change from GNDA to GND Design modify

4

1 1

10
11
12
13
14
15
16
17
18
19
20

2 2

21
22
23
24
25
26
27
28
29
30
31

32
33
34
35
36

3 3

37
38

39
40
41
42
43
44
45
46
47
48
49

50
51

4 4

52
53

JP21 50pin contact to U31 F25pin

5

JP24 50pin contact to U31 H26pin

6

Add D26 Add RTC Battery life Rev0.2 P28

7

BOM del R51

8

Change R562 from 649K_0402 to 649_0402_1% BOM error fix LAN can't link Rev0.2 P35

9

Change R558 from3.3K_0402 to 200_0402_5%
U24 contact to CPUSB#
BOM del R307 no need EC control new card reset
Add R582 @0_0402 Reserve Rev0.2 P35
Cancel U12 pin3 contact to +3VLAN Design modify for LAN function fix LAN can't link Rev0.2 P35
IFPAB_PLLVDD PLLVDD VID_PLLVDD change from 3.3V to 2
PEX_CFG 0~2 change from 100 to 001
Add JP34 for mini-PCIE card ME update Rev0.2 P37 6/6 '05
Del BOM R359,R349,R361,D9,D10,Q23 For TI 7412 modify request Rev0.2 P32 6/7 '05
Change MSBS_SDCMD_SMWE_FIXED# to MSBS_SDCMD_SMWE# For TI 7412 modify request
Change SDCLK_SMRE_FIXED# to SDCLK_SMRE# For TI 7412 modify request
Change SDWP#_SMCE_FIXED# to SDWP#_SMCE# For TI 7412 modify request
Change SM_RB_FIXED# to SM_RB# For TI 7412 modify request
Change R554,R556,R557,R559 from 10K to 2.2K For TI 7412 modify request
Del R369,Q20,Q9,C446,JP29,JOPEN1,JOPEN2 Cancel TV tuner function Rev0.2 P41 6/7 '05
Change LINK_LED100# contact to U41 pin27 Customer request for LAN link LED state Re v0.2 P 35 6/ 8 '05
Add R583,R584 75 ohm contact to JP19 and RJ45_GND LAN modify Rev0.2 P35 6/8 '05
Swap DQSA0~7/DQSA#0~7 and DQSC0~7/DQSC#0~7 Schematic error modify Rev0.2 P19 6/8 '05
Add R585 LID_SW# 10K pull-high reserve L ID_SW# floating Rev0.2 P44 6/13 '05
U6 pin D23 SLP_S4# contact to U24 pin35 EC need detect SLP_S4# for S4 state Rev0.2 P4 4 6/13 '05
BOM update add R388 DOCK_MICR need pull-high to +CODEC_REFC Re v0.2 P 38 6/ 13 '05
Change WL_PRIORITY contact to JP18 pin3 and BT_PRIORITY contact

to JP18 pin5.
BOM add R587,R588,R589,R590 0 ohm for NV72 CLK swap pin rework Rev0.2
JP17 footprint update DB1 footprint error, fix can't TV-out
Del R587,R588,R589,R590 0 ohm for NV72 chipset modify Rev0.3 6/17 '05
Add R586,R587 UMA or Discrrte PCBA detect Rev0.3 6/27 '05
Change R145,R146 from 88.7K to 88.7 ohm BOM error Rev0.3 6/28 '05
Change C419,C421 form 33P to 22P_0402 improve TV out quility. Rev0.3 6/28 '05
Add R588 TI recommend(It can avoid the small noise

JP26 footprint update ME change new USB connector Rev0.3 P41 6/30 '05
JP3 footprint update ME change new CRT connector Rev0.3 P17
Add R589 Dual layout for 9LP306 and SLG8LP462. Rev0.3
BOM add C591 220U_D2 for +VCCP bypass capacitance
BOM del C595 220U_D2 for +VCCP bypass capacitance
U24(EC) pin91 add ACZ_RST# input
Add C790,C791,C792,C793,C794,C795,C796 100P_0402
Add R590,Q46 Switch PCBEEP path
Add C797 reserve For EMI Rev0.3 P37 7/07 '05
Change R94,R141 to @ and change R96,R142 form @ to 128@ For NVDIA change request Rev0.3 P19 7/08 '05
Change R139,Q6 to @ and change R145 form 87_0402 to 124_0402,

R84 from 130_0402 change to 124_0402
Add screw hold H23, H24 ME drawing modify Rev0.3 P47 7/08 '05

R36 pin1 change contact to ACTLED#,R43 pin1 change contact to
LINK_LED100#

Add R591 10K_0402 and Q47 fix mute LED power on turn on Rev0.3 P38 7/11 '05
BOM del R383 4.7K pull-high EC program this pin as push-pull output Re v0.3 P 42 7/ 13 '05

、、

1

.5V

Reason for change Rev. P G #

Rev0.2

Rev0.2

support system memory throttling
support system memory throttling

Change NB strap pin CFG9 to Normal Operation Rev0.2 P11

BOM error fix LAN can't link Rev0.2 P35
Reserve new card detect input

G72 G73 power modify

、

Overridden CFG modify

pin define swap

form this SPKROUT pin)

change 220U location with C595
For cost down
fix into xp codec out popo noise Rev0.3 P44 7/06 '05
For EMI

For NVDIA change request Rev0.3 P18 7/08 '05

Change LAN LED state, Amber LED indicates activity,
Green LED indicates the link is present

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

2

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev0.2
Rev0.2
Rev0.2

Rev0.2
Rev0.2

Rev0.2
Rev0.2

Rev0.2
Rev0.2
Rev0.2
Rev0.2
Rev0.2

Rev0.2 P37 6/14 '05

Rev0.2 6/14 '05

Rev0.3

Rev0.3
Rev0.3

Rev0.3
Rev0.3 P29,40

Rev0.3 P35 7/09 '05

3

Modify by

6/6 '05
6/6 '05
6/6 '05

P40

6/6 '05

P40

6/6 '05

P13

6/6 '05

P14

6/6 '05
6/6 '05
6/6 '05
6/6 '05

P44

6/6 '05

P44

6/6 '05
6/6 '05
6/6 '05

P20

6/6 '05

P26

6/6 '05

P32

6/7 '05

P32

6/7 '05

P32

6/7 '05

P32

6/7 '05

P32

6/7 '05

P19

6/14 '05

P17
P19
P44
P18
P15

6/30 '05

P32

P15 7/05 '05
P06

7/06 '05

P11 7/06 '05

P42

7/06 '05
7/07 '05

2005/03/10 2006/03/10

Compal Secret Data

Deciphered Date

4

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

H/W2 EE Dept. PIR SHEET

LA-2841

5

of

57 60Thursday, December 15, 2005

1.0

1

2

3

4

5

Version change list (P.I.R. List)

54
55
56
57

1 1

58
59

60
61
62
63
64
65
66
67

68
69
70
71

72

2 2

73
74
75
76
77
78
79
80
81

82
83
84
85
86

87

3 3

88
89
90
91

92
93
94
95
96
97
98
99
100
101
102

4 4

103
104
105

BOM del R101,C161,R467,R88 nvdia recommend P18
BOM del R78,R468,R111,R117,R63,R475,R477 nvdia recommend Rev0.3 P26 7/13 '05
BOM del R108,add R112 nvdia recommend(change to PEX_CFG[2..0]=0x010b) Rev0.3 P26 7/18 '05
BOM add C599 add 220U cap for 1.8V power decoupling Rev0.4 P11 8/ 18 '05
BOM add R455 add 51_0402 resister for intel Yonah B0 sightings

Add Q48,Q49,Q50,R593,R594 modify WLED control circuit for OTS:0164892 issue Rev0.4 P37 8/22 '05
Del D3
Del R440,R432,Q30 modify WLED control circuit for OTS:0164892 issue
Add R592
JP9 Pin 14 contact to +5VS change SPDIF LED power from +5V to +5VS
Add Q51 Prevent TPS2231 pin2 +3VALW leakage to +3VS
JP5 Pin 25 contact to +3VALW switch board need +3VALW provide lie switch power
BOM change R554/R557/R556 to 100K, change R559 to 22K TI 7412 pull-high recommend Rev0.4 P32 8/23 '05
JP3 change new part change CRT conn from top side to bottom side for

Del C764,R552,R553, Add D28,change U40 to G993 fan control Fan control circuit change to G993 Re v0.4 P 04 8/24 '05
BOM del R47 Rev0.4 P11 8/29 '05Intel WW31 document update
Add R595/R596/R597/R598/R599 SD card signal add 33 ohm damping resister Rev0.4 P32 8/30 '05
Add R81/R77 10K_0402 NV72 A1 chip recommend JTAG_TCK pull-high and

Del clock generators difference clock 49.9ohm termination ICS9LP306 clock generators update Rev0.4 P15 8/29 '05
Change clock generators difference clock 33ohm damping to 10ohm ICS9LP306 clock generators update Re v0.4 P 15 8/29 '05
Change R266 from 475 ohm to 2.4K ohm ICS9LP306 clock generators update Rev0.4 P15 8/29 '05
Add D29/D30/D31/D32/D33/D34/D35/D36 SD card signal add diode for Voltage clamp Rev0.4 P32 8/ 30 '05
Move C8/C11/C10/C3/C4/C5/C2/C13/C14/C34/C35/C1 for layout ME update limit area for CPU Re v0.4 P06 8/30 '05
Change R591 from 10K ohm to 100 ohm Fix OTS:163350 calgary's mute LED can't display R ev0.4 P38 8/30 '05
JP34 pin50 change contact from PM_EXTTS#1 to PM_EXTTS#0 Intel WW31 document update Rev0.4 P14 8/30 '05
U31 pinH6 change contact from PM_EXTTS#1 to DPRSLPVR Intel WW31 document update Rev0.4 P07 8/30 '05
D26 pin2 change contact from +3VALW to LDO3 Add RTC battery life Rev0.4 P28 8/30 '05
BOM change R562 from 649 ohm to 619 ohm and change U12 to new

part
Add R600 100 ohm and DEL C608 @ HP recommend Rev0.4 P37 8/ 30 '05
Add R601 100 ohm HP recommend Rev0.4 P41 8/30 '05
Reserve C810~C821 0.1u cap For EMI Rev0.4 P4 2 8/30 '05
Add L32 and C822 on SPDIF signal For EMI Rev0.4 P42 8/30 '05
Add C802 /C803 /C804 /C805 1000P for

CLKREQA#/CLKREQB#/CLKREQC#/CLKREQD#
U40 pin5,6,7,8 contact to GND schematic update for SI2 fan can't full trun on

change C599 from 220U to 330U Steady the 1.8V Rev0.5 P11 10/26 '05
Add R103 40.2ohm nvdia recommend P21Rev0.5 10 /28 '05
change R510,R75,R533,R168 from 120ohm to 499ohm for NV73 only nvdia recommend Rev0.5 P22~25 10/26 '05
straps table PEX_CFG[2:0] from 010 to 001 and PCI_DEVID[3:0]

NV73M from 1010 to 1011
Add C825 15P_0402 for MSCLK_SDCLK_SMELWP# signal For EMI Rev0.5 P32 1 0/26 '05
Add C823 1000P_0402 for +VCC_SD For EMI Rev0.5 P32 10 /26 '05
Add C824 1000P_0402 for +VCC_SM_XD For EMI Rev0.5 P32 10/26 '05
Add C826 1000P_0402 for JP32 pin4 For EMI Rev0.5 P32 10/26 '05
change PCM_SPK pull down R588 from 43K to 10K TI recommend Rev0.5 P32 10/26 '05
D29,D30,D31,D32 pin1 contact to +VCC_MS schematic update for SI2 MS card can't work issue Rev0.5 P32 10/26 '05
Add R607 22ohm and @ C827 10P Rev0.5 P32 10/26 '05Reserve
U18 pinG6 contact to +3VS TI recommend Rev0.5 P33 10 /26 '05
Add @ R606 110ohm
Change Q46 to U45 analog switch design change Rev0.5 P40 10/26 '05
Change U38 pin3,4 form +5VALW to +5V design change Re v0.5 P41 10/26 '05
Change Q2 from AO3413 to AO3419 Rev0.5 P41 10/26 '05
Add D38~D45 for KB ESD solution For ESD request Rev0.5 P42 10/26 '05
AIR_ACIN change contact to U24 pin81 and add R605 for BID

define, add D37.

1

update

modify WLED control circuit for OTS:0164892 issue Rev0.4 P4 1 8/22 '05

add R592 150 ohm for WLED# current limit

DFX request

JTAG_N pull-down

LAN performance modify Rev0.4 P35 8 /30 '05

For EMI Rev0.4 P15 8/30 '05

issue

nvdia recommend Rev0.5 P26 10/26 '05

Reserve Rev0.5 P35 10/26 '05

design change Rev0.5 P44 10/26 '05

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

2

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev0.3

Rev0.4 P04 8/18 '05

Rev0.4 P16 8/22 '05
Rev0.4 P37 8/22 '05
Rev0.4 P42 8/22 '05
Rev0.4 P34 8/29 '05
Rev0.4 P42 8/23 '05

Rev0.4 P17 8/24 '05

Rev0.4 P18 8/29 '05

Rev0.5 P04 10/26 '05

3

Reason for change Rev. P G #Modify listItem

Modify by

7/13 '05

2005/03/10 2006/03/10

Compal Secret Data

Deciphered Date

4

Title

Size Document Number Rev

Date: Sheet

Page 2 of 3

Compal Electronics, Inc.

H/W2 EE Dept. PIR SHEET

LA-2841

5

of

58 60Thursday, December 15, 2005

1.0

1

2

3

4

5

Version change list (P.I.R. List) Page 3 of 3

P42
P42
P43
P44

Modify by

12/08 '05

12/08 '05

12/08 '05

12/08 '05

12/08 '05

12/08 '05

12/08 '05

Add D46 ESD P17

106

RESERVE Q52 / C828 / R608 CONTROL RTC RESET P28Rev1.0

107

ADD R612 CIR OUTPUT IS OPEN-DRAIN

108

CANCEL C811 / C812 AND ADD D47 ESD

109

1 1

2 2

CANCEL Q45 AND ADD U48 / C830

110

CANCEL D37 AND RESERVE U47 / C51 / R611

111

RESERVE U46 / C829 / R609 / Q53 / R610 CONTROL WRITE SIGNAL OF FLASH ROM Rev1.0 P45

112

FIX ODD CAUSE BOOT LATE ISSUE
IMPROVE EC RESET SIGNAL

Rev1.0

Rev1.0
Rev1.0
Rev1.0
Rev1.0

Reason for change Rev. P G #Modify listItem

3 3

4 4

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

1

2

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/03/10 2006/03/10

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

4

Date: Sheet

Compal Electronics, Inc.

H/W2 EE Dept. PIR SHEET

LA-2841

5

of

59 60Thursday, December 15, 2005

1.0

5

4

3

2

1

Version change list (P.I.R. List) Page 1 of 1

Reason for change PG# Modify List B.Ver#Item

1 Solve the oscillate of +3VALWP when plug adapter. 48 Change PC11 from 10U_0805_10V to 0.1U_0603_25V. 2005.06.01

D D

2

Adjust VGA power rail sequence. 54 Add PQ55, PQ56 and PR249 2005.06.21

Power section

Date

3 To protect PQ21, because SUSP change to 18.5V from 5V. 52 Add PR253 and change PR114 to 510K_0402_5%. 2005.08.10

4 To save S5 power consumption. 50,48 Add PR254, PR13, PR14, PQ1 and PC8.

5 To solve EMI issue. 53,49 Add PR117,PR129,PR119,PR138,PC108 and PC119.

Reserve PR255.

Change PJP16 to PL18 and PR30 from 0_0402 to 2.2_0603.

2005.08.15

2005.08.15

6 49To speed up CP mode response. Change PR32 to 10K; PR35 to 6.8K and PC21 to 2200P. 2005.08.23

7 Reserve capacitor to reduce noise. 49 Reserve PC209. 2005.08.27

8 To speed up C4 return to C0. follow Intel recommend. 53 Change PR141 from 0_0402_5% to 499_0402_1%. 2005.08.29

C C

9 To pull up +1.8V power plan to 1.846V. 51 Change PR89 from 10.2K to 10.5K. 2005.10.01

10 To filter high frequency from AirCard. 55 Add PC210 22P_0402_50V. 2005.11.25

B B

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPER TY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2005/03/22 2006/03/22

3

Compal Secret Data

Deciphered Date

Title

Power PIR

Size Do c ument Number R e v

LA-2841 1.0

Custom

2

Date: Sheet

1

of

60 60Thursday, December 15, 2005