Compal LA-2831 HAR00 WT2 Schematic

A

1 1

2 2

B

C

D

E

WT2
HAR00 LA-2831 Schematic

3 3

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITT EN CON SENT O F COMPAL ELECTRONICS, INC.

C

2005/03/11 2006/03/11

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

D

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, M/B LA-2831

401362

,

星期一

06, 2006

三月

E

D

of

159

5

4

3

2

1

Compal confidential

Block Diagram

15.4" LCD
Dothan

D D

DDR333
8Mx16x2

page 45

Flash
memory
1Mx8

page 40

Image Processor LVDS Rx

PW172A-10VL THC63LVDF84B

SBUS video

EXT IO
TE7782

C C

LVDS

Video Engine

Chromakey

XILINX XC3S400

RGB:8:8:8 RGB:6:6:6

page 38,39

page 41

page 43,44,47

MPEG4 DECODER

EM8475

page 35,36,46

page 42

SDRAM
2Mx32

page 37

CRT CONN.

& TV-OUT/D Conn.

LVDS

3.3V 33MHz

uFCPGA CPU

HA#(3..31)

System Bus

400 / 533MHz

Alviso Intel 915 GM

GMCH-M

1257 FC-BGA

page 5,6,7

HD#(0..63)

page 8,9,10,11,12

Memory
BUS(DDR II)
Dual Channel

1.8V 400MHz

Channel A

1.8V 400MHz

Channel B

SO-DIMM X 1

BANK 0, 1

SO-DIMM X 1

BANK 0, 1

page 13

page 14

Clock Generator

ICS

page 17

Fan Control X1

LED/B

SW LED BD

T/P

DMI

TV Module

PCI-IF

page 26

+3VS
+2.5VS
+1.5VS

IDSEL:AD17
(PIRQA/B#,GNT#2,REQ#2)

CardBus
Controller

B B

1394
CONN.

page 25

R5C841

SDIO
CONN.

SD/MS/xD
Combo Slot

page 25

MINI PCI

page 24,25

Slot 0

page 25

page 26

3.3V 33MHz

PCI BUS

10/100 LAN Ctrl.

RTL 8100CL

page 23

Transformer

& RJ45

page 23

3.3V 33MHz

PCIE
Card

page 24

PCI-E

LPC BUS

3.3V 33MHz

X BUS

SST39VF080

A A

5

page 31

4

1.5V
100MHz

KB910

Int.KBD

ICH6M

609 BGA

page 18,19,20,21,22

page 30

3.3V 24.576MHz

PATA100
SATA

SATA

SATA TO PATA SATA TO PATA

page 22 page 22

CDROM

page 22

1st. HDD

page 22 page 22

48MHz / 480Mb

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

USB2.0

2005/03/11 2006/03/11

3

2nd. HDD

USBPORT 0
USBPORT 1
USBPORT 2
USBPORT 3
USBPORT 4
USBPORT 5
USBPORT 6
USBPORT 7

Compal Secret Data

Deciphered Date

JUSBP0
JUSBP1
JUSBP2
JUSBP3
PCIE Card

Video Engine

Touch Pad
Remote Ctr.

2

page 24

page 42

page 31

page 29

MDC

page 32

AC-LINK

AC97 CODEC

AD1981B

page 27

AMP &

Phone/ MIC

page 28

Jack

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, M/B LA-2831

401362

星@, 06, 2006

薑三月

DC IN

BATT IN/+2.5V

1.5V/1.05V(+VCCP)

5V/3.3V/15V

1.8V / 0.9V

VCORE

CHARGER

of

1

259

D

5

4

3

2

1

I2C / SMBUS ADDRESSING

External PCI Devices

D D

LAN
CARD BUS

IDSEL
#

AD17
AD20

0

1
Cardreader
1394
Wireless LAN(MINI PCI)

AD16 2
AD18

3

PIRQREQ/GNT #DEVICE

F
A
B
E
G,H

Power Managment table

Signal

State

S0

S1

S3

S5 S4/AC

S5 S4/AC don't exist

+12VALW +3V
+3VALW
+5VALW

ON

+2.5V
+5V

+12V

ON ON

ON ON ON

ON ON

ON OFF

OFF OFF OFF

+CPU_CORE
+VCCP
+5VS

+3VS
+2.5VS
+1.8VS
+1.25VS
+1.5VS

OFF

OFF

PCB Rev

Bringup-Build

ES-Build

PP-Build

MP1-Build

MP-Build

0.1

SCHEMATICS VERSION LIST

Data

VERSION ISSUE DATE REMARK

C C

Ceramic Capacitor Spec
Guide:

Temperature Characteristics:

9

C0G

Z5V

1

Z5P

A

BJ

Symbol

CODE

0

Z5U

8

NP0 SH

3

2

Y5U X7R

C

B

CH

4

Y5V Y5P

CJ

5

E

D

CK

X5R

0.0A

6

7

F

G

SJ

First Release

I

H

UK

UJ

J

SL

Tolerance:

Symbol

B B

SMBUS Control Table

SOURCE

SMB_EC_CK1
SMB_EC_DA1

SMB_EC_CK2
SMB_EC_DA2

ICH_SMBCLK
ICH_SMBDATA

A A

LCD_DDCCLK
LCD_DDCDATA

PC87591L

PC87591L

ICH6-M

Alviso
GM-GP

5

INVERTER BATT

SERIAL SENSOR
EEPROM

THERMAL
(CPU)

4

THERMAL
SENSOR
(LM75)

SODIMM CLK CHIP

CODE

+-10%

A

+-0.05PF

M

KQ

+-20%

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

B

+-0.1PF

N

+-30%

MINI PCI

C

+-0.25PF

+100,-0%

2005/03/11 2006/03/11

3

+-0.5PF +-1PF

P

+30,-10%

LCD

D

VGA Thermal

F

V

+20,-10%

ADM1032

Compal Secret Data

G

+-2%

X

+40,-20%

Deciphered Date

H

+-3%

Z

+80,-20%

J

+-5%

2

Title

Size Document Number Rev

Date: Sheet

SCHEMATIC, M /B LA-2831

, 06, 2006

三月

401362

星期一

359

1

of

Compal Electronics, Inc.

D

ACIN

5

4

3

2

1

+3/5/12VALW

D D

32ms

ON/OFF#

8.5/2.44/3.792ms

t<=10 ms

EC_ON

t=100 ms

PWRBTN_OUT#

438ms

364us

t=109 ms

SYSON

+12/3/5V

3/5V 400us 2.5V(1.8ms)

C C

RSMRST#

7.856ms
t<110 ms

117ms

PM_SLP_S3/4/5#

SUSP#

1.5/1.8/2.5/3/5VS

+VCCP

VR_ON#

1.25VS(104us) 1.5VS(2.64ms) 3VS(7.044ms) 5VS(10.26ms) 2.5VS(4.966ms)

92.88ms

t>0

2.166ms

1.3ms PGD

5.6ms

B B

CPU_VID

+CPU_CORE

Vgate

SYSPOK(ICH_PWRGD)
PCIRST/PLTRST#

726us

815.2us

t<110 ms

99ms

t<100 us

1.036ms

2<t<3 RTCCLK

61us

CPU_RST#(H_RESET#)

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2005/03/11 2006/03/11

3

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

2

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, M /B LA-2831

, 06, 2006

三月

401362

星期一

459

1

D

of

5

4

3

2

1

H_A#[3..31]8

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8

CLK_CPU_BCLK
CLK_CPU_BCLK#

ITP_DBRESET#

H_PROCHOT#

R634

1 2

1K_0402_5%@

R707

1 2

1K_0402_5%@

H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

H_ADSTB#0
H_ADSTB#1

CPU_CK_ITP
CPU_CK_ITP#

H_ADS#
H_BNR#
H_BPRI#
H_BR0#
H_DEFER#
H_DRDY#
H_HIT#
H_HITM#
H_IERR#
H_LOCK#
H_RESET#

H_RS#0
H_RS#1
H_RS#2
H_TRDY#

ITP_BPM#0
ITP_BPM#1
ITP_BPM#2
ITP_BPM#3

H_DBSY#
H_DPSLP#
H_DPRSLP#

ITP_BPM#4
ITP_BPM#5

H_CPUSLP#
ITP_TCK
ITP_TDI
ITP_TDO
TEST1
TEST2
ITP_TMS
ITP_TRST#

H_THERMDA
H_THERMDC

D D

H_REQ#[0..4]8

CLK_ITP_R#

R664 0_0402_5%
R662 0_0402_5%

CLK_ITP17
CLK_ITP#17

1 2
1 2

@
@

1 2

CLK_ITP
CLK_ITP#

R71056_0402_5%

H_RS#[0..2]8

H_ADSTB#08
H_ADSTB#18

R661 0_0402_5%@

1 2

R663 0_0402_5%@

1 2

CLK_CPU_BCLK17
CLK_CPU_BCLK#17

H_ADS#8
H_BNR#8
H_BPRI#8
H_BR0#8
H_DEFER#8
H_DRDY#8
H_HIT#8
H_HITM#8

H_LOCK#8
H_RESET#8

H_TRDY#8

H_DBSY#8
H_DPSLP#19
H_DPRSLP#19
H_DPWR#8

H_PWRGOOD19

H_CPUSLP#8,19

T72 PAD
T34 PAD

H_THERMDA32
H_THERMDC32
H_THERMTRIP#8,19

TEST2

TEST1

CLK_ITP_R

C C

+VCCP

B B

A A

JCPU1A

P4

A3#

U4

A4#

V3

A5#

R3

A6#

V2

A7#

W1

A8#

T4

A9#

W2

A10#

Y4

A11#

Y1

A12#

U1

A13#

AA3

A14#

Y3

A15#

AA2

A16#

AF4

A17#

AC4

A18#

AC7

A19#

AC3

A20#

AD3

A21#

AE4

A22#

AD2

A23#

AB4

A24#

AC6

ADDR GROUP

A25#

AD5

A26#

AE2

A27#

AD6

A28#

AF3

A29#

AE1

A30#

AF1

A31#

R2

REQ0#

P3

REQ1#

T2

REQ2#

P1

REQ3#

T1

REQ4#

U3

ADSTB0#

AE5

ADSTB1#

A16

ITP_CLK0

A15

ITP_CLK1

B15

BCLK0

B14

BCLK1

N2

ADS#

L1

BNR#

J3

BPRI#

N4

BR0#

L4

DEFER#

H2

DRDY#

K3

HIT#

K4

HITM#

A4

IERR#

J2

LOCK#

B11

RESET#

H1

RS0#

K1

RS1#

L2

RS2#

M3

TRDY#

C8

BPM0#

B8

BPM1#

A9

BPM2#

C9

BPM3#

A7

DBR#

M2

DBSY#

B7

DPSLP#

G1

DPRSTP#

C19

DPWR#

A10

PRDY#

B10

PREQ#

B17

PROCHOT#

E4

PWRGOOD

A6

SLP#

A13

TCK

C12

TDI

A12

TDO

C5

TEST1

F23

TEST2

C11

TMS

B13

TRST#

B18

THERMDA

A18

THERMDC

C17

THERMTRIP#

TYCO_1612365-1_Dothan

Dothan

DATA GROUP

HOST CLK

CONTROL GROUP

MISC

THERMAL
DIODE

LEGACY CPU

D10#
D11#
D12#
D13#
D14#
D15#
D16#
D17#
D18#
D19#
D20#
D21#
D22#
D23#
D24#
D25#
D26#
D27#
D28#
D29#
D30#
D31#
D32#
D33#
D34#
D35#
D36#
D37#
D38#
D39#
D40#
D41#
D42#
D43#
D44#
D45#
D46#
D47#
D48#
D49#
D50#
D51#
D52#
D53#
D54#
D55#
D56#
D57#
D58#
D59#
D60#
D61#
D62#
D63#

DINV0#
DINV1#
DINV2#
DINV3#

DSTBN0#
DSTBN1#
DSTBN2#
DSTBN3#
DSTBP0#
DSTBP1#
DSTBP2#
DSTBP3#

A20M#
FERR#

IGNNE#

INIT#
LINT0
LINT1

STPCLK#

SMI#

D0#
D1#
D2#
D3#
D4#
D5#
D6#
D7#
D8#
D9#

A25
A22
B21
A24
B26
A21
B20
C20
B24
D24
E24
C26
B23
E23
C25
H23
G25
L23
M26
H24
F25
G24
J23
M23
J25
L26
N24
M25
H26
N25
K25
Y26
AA24
T25
U23
V23
R24
R26
R23
AA23
U26
V24
U25
V26
Y23
AA26
Y25
AB25
AC23
AB24
AC20
AC22
AC25
AD23
AE22
AF23
AD24
AF20
AE21
AD21
AF25
AF22
AF26

D25
J26
T24
AD20

C23
K24
W25
AE24
C22
L24
W24
AE25

C2
D3
A3
B5
D1
D4

C6
B4

H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63

H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3
H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3

H_A20M#
H_FERR#
H_IGNNE#
H_INIT#
H_INTR
H_NMI

H_STPCLK#

H_SMI#

H_DINV#0 8
H_DINV#1 8
H_DINV#2 8
H_DINV#3 8

H_A20M# 19
H_FERR# 19
H_IGNNE# 19
H_INIT# 19
H_INTR 19
H_NMI 19

H_STPCLK# 19
H_SMI# 19

H_D#0

A19

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

H_D#[0..63] 8

Test pad as closed as posible

ITP_DBRESET# ITP_TDO
ITP_BPM#0
ITP_BPM#1

Place near JITP 0.5"

H_RESET#

ITP_TDO

R678

22.6_0402_1%
1 2

R673

22.6_0402_1%
1 2

ITP_BPM#2
ITP_BPM#3
ITP_BPM#4
ITP_BPM#5
ITP_TCK

CLK_ITP_R

ITP_TRST#
ITP_TMS
ITP_TDI

Check ITP connector.

R646
56_0402_5%

H_DSTBN#[0..3] 8

H_DSTBP#[0..3] 8

R715
200_0402_5%

1 2

+VCCP

2005/03/11 2006/03/11

Compal Secret Data

Add pullups for PWRGOOD and THERMTRIP per INTEL

H_PWRGOOD

Deciphered Date

2

T73PAD
T71PAD
T70PAD
T69PAD
T66PAD
T64PAD
T65PAD

T63PAD
T58PAD

T55PAD
T61PAD

T59PAD
T67PAD
T62PAD

+VCCP

12

R647
56_0402_5%

12

H_PROCHOT#

Date: Sheet

+3V

R708

150_0402_5%

1 2

+VCCP

54.9_0603_1%

1 2

R692 56_0402_5%

+VCCP

37.4_0402_1%

1 2

150_0402_5%

1 2

680_0402_5%

1 2

27.4_0402_1%

1 2

+3VS

12

R640
1K_0402_5%

1

C

Q42

2

B

2SC2411K_SC59

E

3

Title

Size Document Number Rev

Compal Electronics, Inc.

SCHEMATIC, M/B LA-2831

星@, 06, 2006

薑三月

R674

R679

54.9_0603_1%

1 2
1 2

R693

R675

This shall place near CPU

R669

R668

401362

ITP_DBRESET#

H_RESET#
ITP_BPM#5

39.4

ITP_TMS

ITP_TDI

ITP_TRST#

ITP_TCK

1

PROCHOT# 30

of

559

D

5

D D

For test onl y ,Cmos output

CPU Voltage ID

H_VID0
H_VID1
H_VID2
H_VID3
H_VID4
H_VID5

C C

B B

R727 0_0402_5%
R732 0_0402_5%
R731 0_0402_5%
R730 0_0402_5%
R729 0_0402_5%
R728 0_0402_5%

12
12
12
12
12
12

1 2

@

+VCCP

R737 10K_0402_5%

R738 10K_0402_5%

R227
0_0402_5%

@

12

1 2

R736 10K_0402_5%

@

R228
0_0402_5%

R739 10K_0402_5%

@

@

@

12

12

12

12

R229
0_0402_5%

1 2

@

OPEN OPEN OPEN OPEN OPEN OPEN

+VCCP

R_A

12

+V_CPU_GTLREF

R631
1K_0402_1%

R_B

12

R630
2K_0402_1%

4

R740 10K_0402_5%

R735 10K_0402_5%

@

@

12

R230
0_0402_5%

1 2

@

Layout close CPU

Layout Note:
500 mil max length

R633

1 2

@

20 mils

12

27.4_0402_1%
R632

+1.5VS

R231
0_0402_5%

5 mils

12

54.9_0402_1%

1 2

@

20 mils

12

27.4_0402_1%

R717

R232
0_0402_5%

54.9_0402_1%

R718

VCCSENSE56

VSSSENSE56

+VCCA_PROC

1

C605

2

0.01U_0402_16V7K

VID0 56
VID1 56
VID2 56
VID3 56
VID4 56
VID5 56

H_PSI#56

5 mils

12

Resistor placed within

0.5" of CPU pin.Trace
should be at least 25
miles away from any
other toggling signal.

3

R697 0_0402_5%

12

R709 0_0402_5%

12

R701

54.9_0402_1%@

54.9_0402_1%@

1

C607

2

10U_1206_6.3V6M

CPU_BSEL017
CPU_BSEL117

1 2
1 2

R705

+CPU_CORE

+V_CPU_GTLREF

VCCSENSEC
VSSSENSEC

+VCCP

T79 PAD
T80 PAD
T35 PAD
T68 PAD
T84 PAD

H_PSI#
H_VID0

H_VID1
H_VID2
H_VID3
H_VID4
H_VID5

CPU_BSEL0
CPU_BSEL1

COMP0
COMP1
COMP2
COMP3

JCPU1B

AE7

VCCSENSE

AF6

VSSSENSE

F26

VCCA0

B1

VCCA1

N1

VCCA2

AC26

VCCA3

P23

VCCQ0

W4

VCCQ1

D10

VCCP

D12

VCCP

D14

VCCP

D16

VCCP

E11

VCCP

E13

VCCP

E15

VCCP

F10

VCCP

F12

VCCP

F14

VCCP

F16

VCCP

K6

VCCP

L5

VCCP

L21

VCCP

M6

VCCP

M22

VCCP

N5

VCCP

N21

VCCP

P6

VCCP

P22

VCCP

R5

VCCP

R21

VCCP

T6

VCCP

T22

VCCP

U21

VCCP

D6

VCC

D8

VCC

D18

VCC

D20

VCC

D22

VCC

E5

VCC

E7

VCC

E9

VCC

E17

VCC

E19

VCC

E21

VCC

F6

VCC

F8

VCC

F18

VCC

E1

PSI#

E2

VID0

F2

VID1

F3

VID2

G3

VID3

G4

VID4

H4

VID5

AD26

GTLREF

C16

BSEL0

C14

BSEL1

P25

COMP0

P26

COMP1

AB2

COMP2

AB1

COMP3

B2

RSVD

C3

RSVD

E26

RSVD

AF7

RSVD

AC1

RSVD

TYCO_1612365-1_Dothan

Dothan

POWER, GROUNG, RESERVED SIGNALS AND NC

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

2

+CPU_CORE

A2
A5
A8
A11
A14
A17
A20
A23
A26
B3
B6
B9
B12
B16
B19
B22
B25
C1
C4
C7
C10
C13
C15
C18
C21
C24
D2
D5
D7
D9
D11
D13
D15
D17
D19
D21
D23
D26
E3
E6
E8
E10
E12
E14
E16
E18
E20
E22
E25
F1
F4
F5
F7
F9
F11
F13
F15
F17
F19
F21
F24
G2
G6
G22
G23
G26
H3
H5
H21
H25
J1
J4
J6
J22
J24
K2
K5
K21
K23
K26
L3
L6
L22
L25
M1

JCPU1C

F20

VCC

F22

VCC

G5

VCC

G21

VCC

H6

VCC

H22

VCC

J5

VCC

J21

VCC

K22

VCC

U5

VCC

V6

VCC

V22

VCC

W5

VCC

W21

VCC

Y6

VCC

Y22

VCC

AA5

VCC

AA7

VCC

AA9

VCC

AA11

VCC

AA13

VCC

AA15

VCC

AA17

VCC

AA19

VCC

AA21

VCC

AB6

VCC

AB8

VCC

AB10

VCC

AB12

VCC

AB14

VCC

AB16

VCC

AB18

VCC

AB20

VCC

AB22

VCC

AC9

VCC

AC11

VCC

AC13

VCC

AC15

VCC

AC17

VCC

AC19

VCC

AD8

VCC

AD10

VCC

AD12

VCC

AD14

VCC

AD16

VCC

AD18

VCC

AE9

VCC

AE11

VCC

AE13

VCC

AE15

VCC

AE17

VCC

AE19

VCC

AF8

VCC

AF10

VCC

AF12

VCC

AF14

VCC

AF16

VCC

AF18

VCC

M4

VSS

M5

VSS

M21

VSS

M24

VSS

N3

VSS

N6

VSS

N22

VSS

N23

VSS

N26

VSS

P2

VSS

P5

VSS

P21

VSS

P24

VSS

R1

VSS

R4

VSS

R6

VSS

R22

VSS

R25

VSS

T3

VSS

T5

VSS

T21

VSS

T23

VSS

TYCO_1612365-1_Dothan

Dothan

POWER, GROUND

1

T26

VSS

U2

VSS

U6

VSS

U22

VSS

U24

VSS

V1

VSS

V4

VSS

V5

VSS

V21

VSS

V25

VSS

W3

VSS

W6

VSS

W22

VSS

W23

VSS

W26

VSS

Y2

VSS

Y5

VSS

Y21

VSS

Y24

VSS

AA1

VSS

AA4

VSS

AA6

VSS

AA8

VSS

AA10

VSS

AA12

VSS

AA14

VSS

AA16

VSS

AA18

VSS

AA20

VSS

AA22

VSS

AA25

VSS

AB3

VSS

AB5

VSS

AB7

VSS

AB9

VSS

AB11

VSS

AB13

VSS

AB15

VSS

AB17

VSS

AB19

VSS

AB21

VSS

AB23

VSS

AB26

VSS

AC2

VSS

AC5

VSS

AC8

VSS

AC10

VSS

AC12

VSS

AC14

VSS

AC16

VSS

AC18

VSS

AC21

VSS

AC24

VSS

AD1

VSS

AD4

VSS

AD7

VSS

AD9

VSS

AD11

VSS

AD13

VSS

AD15

VSS

AD17

VSS

AD19

VSS

AD22

VSS

AD25

VSS

AE3

VSS

AE6

VSS

AE8

VSS

AE10

VSS

AE12

VSS

AE14

VSS

AE16

VSS

AE18

VSS

AE20

VSS

AE23

VSS

AE26

VSS

AF2

VSS

AF5

VSS

AF9

VSS

AF11

VSS

AF13

VSS

AF15

VSS

AF17

VSS

AF19

VSS

AF21

VSS

AF24

VSS

A A

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/03/11 2006/03/11

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

2

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, M/B LA-2831

401362

星@, 06, 2006

薑三月

1

659

D

of

5

4

3

2

1

+CPU_CORE

1

C687
10U_0805_6.3V6M

2

+CPU_CORE

1

2

+CPU_CORE

1

2

+CPU_CORE

1

2

C125
10U_0805_6.3V6M

C715
10U_0805_6.3V6M

C679
10U_0805_6.3V6M

D D

C C

1

C148
10U_0805_6.3V6M

2

1

C121
10U_0805_6.3V6M

2

1

C680
10U_0805_6.3V6M

2

1

C673
10U_0805_6.3V6M

2

1

C132
10U_0805_6.3V6M

2

1

C174
10U_0805_6.3V6M

2

1

C700
10U_0805_6.3V6M

2

1

C672
10U_0805_6.3V6M

2

1

C183
10U_0805_6.3V6M

2

1

C172
10U_0805_6.3V6M

2

1

C671
10U_0805_6.3V6M

2

1

C724
10U_0805_6.3V6M

2

1

C126
10U_0805_6.3V6M

2

1

C157
10U_0805_6.3V6M

2

1

C685
10U_0805_6.3V6M

2

1

C185
10U_0805_6.3V6M

2

+CPU_CORE

1

2

+CPU_CORE

1

2

+CPU_CORE

1

2

C123
10U_0805_6.3V6M

C120
10U_0805_6.3V6M

C723
10U_0805_6.3V6M

1

C695
10U_0805_6.3V6M

2

1

C173
10U_0805_6.3V6M

2

1

C717
10U_0805_6.3V6M

2

10uF 1206 X5R -> 85 degree

1

C165
10U_0805_6.3V6M

2

1

C184
10U_0805_6.3V6M

2

1

C701
10U_0805_6.3V6M

2

1

C143
10U_0805_6.3V6M

2

1

C697
10U_0805_6.3V6M

2

1

C696
10U_0805_6.3V6M

2

X7R

High Frequence Decoupling

1

C725
10U_0805_6.3V6M

2

1

C688
10U_0805_6.3V6M

2

1

C686
10U_0805_6.3V6M

2

Near VCORE regulator.

+CPU_CORE

@

330U_D2E_2.5VM_R9

330U_D2E_2.5VM_R9

@

1

C648

C710

B B

+

2

1

1

C140

+

+

2

2

330U_D2E_2.5VM_R9

330U_D2E_2.5VM_R9

1

C139

+

2

ESR <= 3m ohm
Capacitor > 880 uF

+VCCP

1

C195

0.1U_0402_10V6K

2

+VCCP

1

+

C669
150U_D2_6.3VM

2

A A

1

C100

0.1U_0402_10V6K

2

1

C196

0.1U_0402_10V6K

2

1

C101

0.1U_0402_10V6K

2

1

C197

0.1U_0402_10V6K

2

1

C102

0.1U_0402_10V6K

2

1

C198

0.1U_0402_10V6K

2

1

C103

0.1U_0402_10V6K

2

1

C199

0.1U_0402_10V6K

2

1

C164

0.1U_0402_10V6K

2

1

C200

0.1U_0402_10V6K

2

1

C155

0.1U_0402_10V6K

2

1

C201

0.1U_0402_10V6K

2

1

C150

0.1U_0402_10V6K

2

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

1

C99

0.1U_0402_10V6K

2

1

C144

0.1U_0402_10V6K

2

2005/03/11 2006/03/11

1

C98

0.1U_0402_10V6K

2

1

C137

0.1U_0402_10V6K

2

Compal Secret Data

Deciphered Date

1

C97

0.1U_0402_10V6K

2

1

C129

0.1U_0402_10V6K

2

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, M/B LA-2831

401362

星@, 06, 2006

薑三月

of

1

759

D

5

H_A#[3..31]5

D D

H_REQ#[0..4]5

C C

Layout Guide will show
these signals routed
differentially.

B B

A A

H_DSTBN#[0..3]5

H_DSTBP#[0..3]5

H_RS#[0..2]5

H_CPUSLP#5,19

T3 PAD

H_ADSTB#05
H_ADSTB#15

CLK_MCH_BCLK#17
CLK_MCH_BCLK17

H_DINV#05
H_DINV#15
H_DINV#25
H_DINV#35

H_RESET#5
H_ADS#5

H_TRDY#5
H_DPWR#5
H_DRDY#5
H_DEFER#5

T2 PAD
H_HITM#5
H_HIT#5
H_LOCK#5

H_BR0#5
H_BNR#5
H_BPRI#5
H_DBSY#5

R127
0_0402_5%

H_CPUSLP# H_R_CPUSLP#

1 2

Note:
"Do not install R for Dothan-A,
Install R97 for Dothan-B"

5

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31

TP_H_PCREQ#

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
H_ADSTB#0
H_ADSTB#1

H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3
H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3

H_RESET#
H_ADS#

H_TRDY#
H_DRDY#

H_DEFER#
TP_H_EDRDY#

@

H_HITM#
H_HIT#
H_LOCK#
H_BR0#
H_BNR#
H_BPRI#
H_DBSY#

H_R_CPUSLP#

H_RS#0
H_RS#1
H_RS#2

U48A

G9

HA3#

C9

HA4#

E9

HA5#

B7

HA6#

A10

HA7#

F9

HA8#

D8

HA9#

B10

HA10#

E10

HA11#

G10

HA12#

D9

HA13#

E11

HA14#

F10

HA15#

G11

HA16#

G13

HA17#

C10

HA18#

C11

HA19#

D11

HA20#

C12

HA21#

B13

HA22#

A12

HA23#

F12

HA24#

G12

HA25#

E12

HA26#

C13

HA27#

B11

HA28#

D13

HA29#

A13

HA30#

F13

HA31#

A11

HPCREQ#

A7

HREQ#0

D7

HREQ#1

B8

HREQ#2

C7

HREQ#3

A8

HREQ#4

B9

HADSTB#0

E13

HADSTB#1

AB1

HCLKN

AB2

HCLKP

G4

HDSTBN#0

K1

HDSTBN#1

R3

HDSTBN#2

V3

HDSTBN#3

G5

HDSTBP#0

K2

HDSTBP#1

R2

HDSTBP#2

W4

HDSTBP#3

H8

HDINV#0

K3

HDINV#1

T7

HDINV#2

U5

HDINV#3

H10

HCPURST#

F8

HADS#

B5

HTRDY#

G6

HDPWR#

F7

HDRDY#

E6

HDEFER#

F6

HEDRDY#

D6

HHITM#

D4

HHIT#

B3

HLOCK#

E7

HBREQ0#

A5

HBNR#

D5

HBPRI#

C6

HDBSY#

G8

HCPUSLP#

A4

HRS0#

C5

HRS1#

B4

HRS2#

ALVISO_BGA1257

Alviso

HOST

H_SWNG0

C644

0.1U_0402_16V4Z

HXRCOMP
HXSCOMP
HYRCOMP
HYSCOMP

HXSWING
HYSWING

1

2

HD0#
HD1#
HD2#
HD3#
HD4#
HD5#
HD6#
HD7#
HD8#

HD9#
HD10#
HD11#
HD12#
HD13#
HD14#
HD15#
HD16#
HD17#
HD18#
HD19#
HD20#
HD21#
HD22#
HD23#
HD24#
HD25#
HD26#
HD27#
HD28#
HD29#
HD30#
HD31#
HD32#
HD33#
HD34#
HD35#
HD36#
HD37#
HD38#
HD39#
HD40#
HD41#
HD42#
HD43#
HD44#
HD45#
HD46#
HD47#
HD48#
HD49#
HD50#
HD51#
HD52#
HD53#
HD54#
HD55#
HD56#
HD57#
HD58#
HD59#
HD60#
HD61#
HD62#
HD63#

HVREF

R638

221_0603_1%

R642

100_0402_1%

4

@

R158

40.2_0402_1%

12

R643

24.9_0402_1%

24.9_0402_1%

+SDREF_DIMM

H_D#[0..63] 5

Layout Note:
Rote as short
as possible

12

12

@

R136

40.2_0402_1%

+VCCP

12

R644

R639

54.9_0402_1%

54.9_0402_1%

12

10/20 mils

M_OCDOCMP0
M_OCDOCMP1

12

+1.8V

1 2

1 2

H_D#0

E4

H_D#1

E1

H_D#2

F4

H_D#3

H7

H_D#4

E2

H_D#5

F1

H_D#6

E3

H_D#7

D3

H_D#8

K7

H_D#9

F2

H_D#10

J7

H_D#11

J8

H_D#12

H6

H_D#13

F3

H_D#14

K8

H_D#15

H5

H_D#16

H1

H_D#17

H2

H_D#18

K5

H_D#19

K6

H_D#20

J4

H_D#21

G3

H_D#22

H3

H_D#23

J1

H_D#24

L5

H_D#25

K4

H_D#26

J5

H_D#27

P7

H_D#28

L7

H_D#29

J3

H_D#30

P5

H_D#31

L3

H_D#32

U7

H_D#33

V6

H_D#34

R6

H_D#35

R5

H_D#36

P3

H_D#37

T8

H_D#38

R7

H_D#39

R8

H_D#40

U8

H_D#41

R4

H_D#42

T4

H_D#43

T5

H_D#44

R1

H_D#45

T3

H_D#46

V8

H_D#47

U6

H_D#48

W6

H_D#49

U3

H_D#50

V5

H_D#51

W8

H_D#52

W7

H_D#53

U2

H_D#54

U1

H_D#55

Y5

H_D#56

Y2

H_D#57

V4

H_D#58

Y7

H_D#59

W1

H_D#60

W3

H_D#61

Y3

H_D#62

Y6

H_D#63

W2

H_VREF

J11

H_XRCOMP

C1

H_XSCOMP

C2

H_YRCOMP

T1

H_YSCOMP

L1

H_SWNG0

D1

H_SWNG1

P1

R636

+VCCP+VCCP

12

H_SWNG1

12

C646

4

12

R82

221_0603_1%

12

1

R641

2

0.1U_0402_16V4Z

100_0603_1%

3

Layout Guide
will show these
signals routed
differentially.

DMI_TXN020
DMI_TXN120
DMI_TXN220
DMI_TXN320

DMI_TXP020
DMI_TXP120
DMI_TXP220
DMI_TXP320

DMI_RXN020
DMI_RXN120
DMI_RXN220
DMI_RXN320

DMI_RXP020
DMI_RXP120
DMI_RXP220
DMI_RXP320

DDR_CLK013
DDR_CLK113

DDR_CLK314
DDR_CLK414

DDR_CLK0#13
DDR_CLK1#13

DDR_CLK3#14
DDR_CLK4#14

DDR_CKE0_DIMMA13
DDR_CKE1_DIMMA13
DDR_CKE2_DIMMB14
DDR_CKE3_DIMMB14

DDR_SCS#013
DDR_SCS#113
DDR_SCS#214
DDR_SCS#314

M_ODT013
M_ODT113

1 2

+SDREF_DIMM

M_ODT214
M_ODT314

+1.8V

R125 80.6_0402_1%

12

R126

80.6_0402_1%

+VCCP

12

R680

100_0402_1%

1

R681

C718

2

200_0402_1%

0.1U_0402_16V7K

CFG[2:0]

12

CFG5

CFG6

CFG7

CFG9

R219
1K_0402_5%

R220
1K_0402_5%

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

CFG[13:12]
CFG16

(FSB Dynamic
ODT)

CFG18
(VCC Select)

CFG19
(VTT Select)

2005/03/11 2006/03/11

DMI_TXN0
DMI_TXN1
DMI_TXN2
DMI_TXN3

DMI_TXP0
DMI_TXP1
DMI_TXP2
DMI_TXP3

DMI_RXN0
DMI_RXN1
DMI_RXN2
DMI_RXN3

DMI_RXP0
DMI_RXP1
DMI_RXP2
DMI_RXP3

DDR_CLK0
DDR_CLK1

DDR_CLK3
DDR_CLK4

DDR_CLK0#
DDR_CLK1#

DDR_CLK3#
DDR_CLK4#

DDR_CKE0_DIMMA
DDR_CKE1_DIMMA
DDR_CKE2_DIMMB
DDR_CKE3_DIMMB

DDR_SCS#0
DDR_SCS#1
DDR_SCS#2
DDR_SCS#3

M_OCDOCMP0
M_OCDOCMP1

SMRCOMPN
SMRCOMPP

1

1

C792

C640

Refer to sheet 6 for FSB
frequency select

2

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

Low = DMI x 2
High = DMI x 4
Low = DDR-II
High = DDR-I
Low = DT/Transportable CPU
High = Mobile CPU
Low = Reverse Lane
High = Normal Operation

00 = Reserved
01 = XOR Mode Enabled
10 = All Z Mode Enabled
11 = Normal Operation (Default)

Low = Disabled
High = Enabled
Low = 1.05V (Default)
High = 1.5V
Low = 1.05V (Default)

High = 1.2V

Compal Secret Data

Deciphered Date

*

AA31
AB35
AC31
AD35

AA35
AB31
AC35

AA33
AB37
AC33
AD37

AA37
AB33
AC37

AM33
AE11

AJ34
AC10
AN33
AE10

AJ33
AD10
AP21

AM21
AH21
AK21

AN16
AM14
AH15
AG16

AF22
AF16
AP14

AL15
AM11
AN10

AK10
AK11
AF37

AE27
AE28

AF10

*

*

Y31

Y33

AL1

AF6

AK1

AF5

AD1

AF9

*

2

U48B

DMIRXN0
DMIRXN1
DMIRXN2
DMIRXN3

DMIRXP0
DMIRXP1
DMIRXP2
DMIRXP3

DMITXN0
DMITXN1
DMITXN2
DMITXN3

DMITXP0
DMITXP1
DMITXP2
DMITXP3

SM_CK0
SM_CK1
SM_CK2
SM_CK3
SM_CK4
SM_CK5

SM_CK0#
SM_CK1#
SM_CK2#
SM_CK3#
SM_CK4#
SM_CK5#

SM_CKE0
SM_CKE1
SM_CKE2
SM_CKE3

SM_CS0#
SM_CS1#
SM_CS2#
SM_CS3#

SM_OCDCOMP0
SM_OCDCOMP1
SM_ODT0
SM_ODT1
SM_ODT2
SM_ODT3

SMRCOMPN
SMRCOMPP
SMVREF0
SMVREF1
SMXSLEWIN
SMXSLEWOUT
SMYSLEWIN
SMYSLEWOUT

ALVISO_BGA1257

*

*

*

*

2

DMIDDR MUXING

PM

DREF_SSCLKP

CLK

DREF_SSCLKN

NC

Alviso CFG[1 7 : 3 ] has internal pull-up

CFG0

G16

CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8

CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG16
CFG17
CFG18
CFG19
CFG20

RSVD21
RSVD22

CFG/RSVD

RSVD23
RSVD24
RSVD25
RSVD26
RSVD27

BM_BUSY#

EXT_TS0#
EXT_TS1#

THRMTRIP#

PWROK

RSTIN#

DREF_CLKN
DREF_CLKP

NC10
NC11

MCH_CLKSEL1

H13

MCH_CLKSEL0

G14
F16
F15
G15
E16
D17
J16
D15
E15
D14
E14
H12
C14
H15
J15
H14
G22
G23
D23
G25
G24
J17
A31
A30
D26
D25

J23

PM_EXTTS#0

J21

PM_EXTTS#1

H22
F5
AD30

PLTRST_R#

AE29

R719 10K_0402_5%@
A24
A23
D37
C37

R251 10K_0402_5%
AP37

NC1

AN37

NC2

AP36

NC3

AP2

NC4

AP1

NC5

AN1

NC6

B1

NC7

A2

NC8

B37

NC9

A36
A37

CFG[17:3] hav e i n t e r n a l p u l l-up

3.5 k reserve for choose

Title

Size Document Number Rev

Date: Sheet

@

T6PAD

@

T7PAD

CFG5
CFG6
CFG7

CFG9

CFG12
CFG13

CFG16
CFG18

CFG19

H_THERMTRIP#

1 2

R185 100_0402_1%

12

12

@

CFG0

CFG5
CFG7
CFG9
CFG6
CFG12
CFG13
CFG16

CFG18
CFG19

R1642.2K_0402_5%@

12

R1722.2K_0402_5%@

12

Compal Electronics, Inc.

SCHEMATIC, M/B LA-2831

星@, 06, 2006

薑三月

R637
56_0402_5%

1 2

@

PM_EXTTS#0

PM_EXTTS#1

R134 10K_0402_5%

R131 2.2K_0402_5%@
R133 2.2K_0402_5%@
R132 2.2K_0402_5%@
R135 2.2K_0402_5%
R128 2.2K_0402_5%@
R129 2.2K_0402_5%@
R130 2.2K_0402_5%@

R165 1K_0402_5%@
R173 1K_0402_5%@

CFG[19:18] have internal pull-down

401362

1

MCH_CLKSEL1 17
MCH_CLKSEL0 17

+VCCP

PM_BMBUSY# 20

H_THERMTRIP# 5,19
VGATE 17,20,30,56

DREFCLK# 17

DREFCLK 17
SSC_DREFCLK 17
SSC_DREFCLK# 17

R189

10K_0402_5%

R190

10K_0402_5%

12

1 2
1 2
1 2
1 2
1 2
1 2
1 2

3.5 k reserve for choose

1 2
1 2

1

PLTRST_MCH# 18

+2.5VS

12

12

+VCCP

+2.5VS

D

of

859

5

D D

4

3

2

1

DDR_A_BS#013
DDR_A_BS#113

DDR_A_DM[0..7]13

DDR_A_DQS[0..7]13

DDR_A_DQS#[0..7]13

C C

DDR_A_MA[0..13]13

DDR_A_CAS#13
DDR_A_RAS#13

T9 PAD
T8 PAD

DDR_A_WE#13

B B

DDR_A_BS#0
DDR_A_BS#1
DDR_A_BS#2

DDR_A_DM0
DDR_A_DM1
DDR_A_DM2
DDR_A_DM3
DDR_A_DM4
DDR_A_DM5
DDR_A_DM6
DDR_A_DM7

DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7

DDR_A_DQS#0
DDR_A_DQS#1
DDR_A_DQS#2
DDR_A_DQS#3
DDR_A_DQS#4
DDR_A_DQS#5
DDR_A_DQS#6
DDR_A_DQS#7

DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13

DDR_A_CAS#
DDR_A_RAS#

TP_MA_RCVENIN#

TP_MA_RCVENOUT#

DDR_A_WE#

AK15
AK16

AL21
AJ37

AP35

AL29

AP24

AK36
AP33
AN29
AP23

AM8
AM4

AK35
AP34
AN30
AN23

AM5

AL17
AP17
AP18

AM17

AN18

AM18

AL19
AP20

AM19

AL20

AM16

AN20

AM20
AM15

AN15
AP16
AF29
AF28
AP15

AP9
AP4
AJ2
AD3

AJ1
AE5

AN8
AH1

AE4

U48C

SA_BS0#
SA_BS1#
SA_BS2#

SA_DM0
SA_DM1
SA_DM2
SA_DM3
SA_DM4
SA_DM5
SA_DM6
SA_DM7

SA_DQS0
SA_DQS1
SA_DQS2
SA_DQS3
SA_DQS4
SA_DQS5
SA_DQS6
SA_DQS7

SA_DQS0#
SA_DQS1#
SA_DQS2#
SA_DQS3#
SA_DQS4#
SA_DQS5#
SA_DQS6#
SA_DQS7#

SA_MA0
SA_MA1
SA_MA2
SA_MA3
SA_MA4
SA_MA5
SA_MA6
SA_MA7
SA_MA8
SA_MA9
SA_MA10
SA_MA11
SA_MA12
SA_MA13

SA_CAS#
SA_RAS#
SA_RCVENIN#
SA_RCVENOUT#
SA_WE#

ALVISO_BGA1257

SADQ0
SADQ1
SADQ2
SADQ3
SADQ4
SADQ5
SADQ6
SADQ7
SADQ8

SADQ9
SADQ10
SADQ11
SADQ12
SADQ13
SADQ14
SADQ15
SADQ16
SADQ17
SADQ18
SADQ19
SADQ20
SADQ21
SADQ22
SADQ23
SADQ24
SADQ25
SADQ26
SADQ27
SADQ28
SADQ29
SADQ30
SADQ31
SADQ32
SADQ33
SADQ34
SADQ35
SADQ36
SADQ37
SADQ38
SADQ39
SADQ40
SADQ41
SADQ42
SADQ43

DDR MEMORY SYSTEM A

SADQ44
SADQ45
SADQ46
SADQ47
SADQ48
SADQ49
SADQ50
SADQ51
SADQ52
SADQ53
SADQ54
SADQ55
SADQ56
SADQ57
SADQ58
SADQ59
SADQ60
SADQ61
SADQ62
SADQ63

AH35
AL35
AL37
AH36
AJ35
AK37
AL34
AM36
AN35
AP32
AM31
AM34
AM35
AL32
AM32
AN31
AP31
AN28
AP28
AL30
AM30
AM28
AL28
AP27
AM27
AM23
AM22
AL23
AM24
AN22
AP22
AM9
AL9
AL6
AP7
AP11
AP10
AL7
AM7
AN5
AN6
AN3
AP3
AP6
AM6
AL4
AM3
AK2
AK3
AG2
AG1
AL3
AM2
AH3
AG3
AF3
AE3
AD6
AC4
AF2
AF1
AD4
AD5

DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63

DDR_A_D0

AG35

DDR_A_D[0..63] 13

This Symbol as same
as Intel CRB
schematic, So Layout
Guide will show these
signals routed
differentially.

T5 PAD
T4 PAD

DDR_B_BS#014
DDR_B_BS#114
DDR_B_BS#214DDR_A_BS#213
DDR_B_DM[0..7]14

DDR_B_DQS[0..7]14

DDR_B_DQS#[0..7]14

DDR_B_MA[0..13]14

DDR_B_CAS#14
DDR_B_RAS#14

DDR_B_WE#14

DDR_B_BS#0
DDR_B_BS#1
DDR_B_BS#2

DDR_B_DM0
DDR_B_DM1
DDR_B_DM2
DDR_B_DM3
DDR_B_DM4
DDR_B_DM5
DDR_B_DM6
DDR_B_DM7

DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4
DDR_B_DQS5
DDR_B_DQS6
DDR_B_DQS7

DDR_B_DQS#0
DDR_B_DQS#1
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS#4
DDR_B_DQS#5
DDR_B_DQS#6
DDR_B_DQS#7

DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13

DDR_B_CAS#
DDR_B_RAS#

TP_MB_RCVENIN#

TP_MB_RCVENOUT#

DDR_B_WE#

AJ15
AG17
AG21

AF32
AK34
AK27
AK24

AJ10

AF34
AK32

AJ28

AK23

AM10

AF35
AK33
AK28

AJ23

AL10

AH17
AK17
AH18

AJ18

AK18

AJ19

AK19
AH19

AJ20

AH20

AJ16
AG18
AG20
AG15

AH14
AK14
AF15
AF14
AH16

AK5
AE7
AB7

AH6
AF8
AB4

AH7
AF7
AB5

U48D

SB_BS0#
SB_BS1#
SB_BS2#

SB_DM0
SB_DM1
SB_DM2
SB_DM3
SB_DM4
SB_DM5
SB_DM6
SB_DM7

SB_DQS0
SB_DQS1
SB_DQS2
SB_DQS3
SB_DQS4
SB_DQS5
SB_DQS6
SB_DQS7

SB_DQS0#
SB_DQS1#
SB_DQS2#
SB_DQS3#
SB_DQS4#
SB_DQS5#
SB_DQS6#
SB_DQS7#

SB_MA0
SB_MA1
SB_MA2
SB_MA3
SB_MA4
SB_MA5
SB_MA6
SB_MA7
SB_MA8
SB_MA9
SB_MA10
SB_MA11
SB_MA12
SB_MA13

SB_CAS#
SB_RAS#
SB_RCVENIN#
SB_RCVENOUT#
SB_WE#

ALVISO_BGA1257

SBDQ0
SBDQ1
SBDQ2
SBDQ3
SBDQ4
SBDQ5
SBDQ6
SBDQ7
SBDQ8

SBDQ9
SBDQ10
SBDQ11
SBDQ12
SBDQ13
SBDQ14
SBDQ15
SBDQ16
SBDQ17
SBDQ18
SBDQ19
SBDQ20
SBDQ21
SBDQ22
SBDQ23
SBDQ24
SBDQ25
SBDQ26
SBDQ27
SBDQ28
SBDQ29
SBDQ30
SBDQ31
SBDQ32
SBDQ33
SBDQ34
SBDQ35
SBDQ36
SBDQ37
SBDQ38
SBDQ39
SBDQ40
SBDQ41
SBDQ42

DDR SYSTEM MEMORY B

SBDQ43
SBDQ44
SBDQ45
SBDQ46
SBDQ47
SBDQ48
SBDQ49
SBDQ50
SBDQ51
SBDQ52
SBDQ53
SBDQ54
SBDQ55
SBDQ56
SBDQ57
SBDQ58
SBDQ59
SBDQ60
SBDQ61
SBDQ62
SBDQ63

AE32
AG32
AG36
AE34
AE33
AF31
AF30
AH33
AH32
AK31
AG30
AG34
AG33
AH31
AJ31
AK30
AJ30
AH29
AH28
AK29
AH30
AH27
AG28
AF24
AG23
AJ22
AK22
AH24
AH23
AG22
AJ21
AG10
AG9
AG8
AH8
AH11
AH10
AJ9
AK9
AJ7
AK6
AJ4
AH5
AK8
AJ8
AJ5
AK4
AG5
AG4
AD8
AD9
AH4
AG6
AE8
AD7
AC5
AB8
AB6
AA8
AC8
AC7
AA4
AA5

DDR_B_D1D DR_B_D1
DDR_B_D2D DR_B_D2
DDR_B_D3D DR_B_D3
DDR_B_D4D DR_B_D4
DDR_B_D5D DR_B_D5
DDR_B_D6D DR_B_D6
DDR_B_D7D DR_B_D7
DDR_B_D8D DR_B_D8
DDR_B_D9D DR_B_D9
DDR_B_D10DDR_B_D10
DDR_B_D11DDR_B_D11
DDR_B_D12DDR_B_D12
DDR_B_D13DDR_B_D13
DDR_B_D14DDR_B_D14
DDR_B_D15DDR_B_D15
DDR_B_D16DDR_B_D16
DDR_B_D17DDR_B_D17
DDR_B_D18DDR_B_D18
DDR_B_D19DDR_B_D19
DDR_B_D20DDR_B_D20
DDR_B_D21DDR_B_D21
DDR_B_D22DDR_B_D22
DDR_B_D23DDR_B_D23
DDR_B_D24DDR_B_D24
DDR_B_D25DDR_B_D25
DDR_B_D26DDR_B_D26
DDR_B_D27DDR_B_D27
DDR_B_D28DDR_B_D28
DDR_B_D29DDR_B_D29
DDR_B_D30DDR_B_D30
DDR_B_D31DDR_B_D31
DDR_B_D32DDR_B_D32
DDR_B_D33DDR_B_D33
DDR_B_D34DDR_B_D34
DDR_B_D35DDR_B_D35
DDR_B_D36DDR_B_D36
DDR_B_D37DDR_B_D37
DDR_B_D38DDR_B_D38
DDR_B_D39DDR_B_D39
DDR_B_D40DDR_B_D40
DDR_B_D41DDR_B_D41
DDR_B_D42DDR_B_D42
DDR_B_D43DDR_B_D43
DDR_B_D44DDR_B_D44
DDR_B_D45DDR_B_D45
DDR_B_D46DDR_B_D46
DDR_B_D47DDR_B_D47
DDR_B_D48DDR_B_D48
DDR_B_D49DDR_B_D49
DDR_B_D50DDR_B_D50
DDR_B_D51DDR_B_D51
DDR_B_D52DDR_B_D52
DDR_B_D53DDR_B_D53
DDR_B_D54DDR_B_D54
DDR_B_D55DDR_B_D55
DDR_B_D56DDR_B_D56
DDR_B_D57DDR_B_D57
DDR_B_D58DDR_B_D58
DDR_B_D59DDR_B_D59
DDR_B_D60DDR_B_D60
DDR_B_D61DDR_B_D61
DDR_B_D62DDR_B_D62
DDR_B_D63DDR_B_D63

DDR_B_D0D DR_B_D0

AE31

DDR_B_D[0..63] 14

A A

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/03/11 2006/03/11

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

2

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, M/B LA-2831

401362

星@, 06, 2006

薑三月

1

959

D

of

5

CRT_BLU
CRT_GRN

@

R100375_0402_1%

R100275_0402_1%

1 2

CRT_RED

@

R100175_0402_1%

1 2

R186 100K_0402_1%

1 2
1 2

R187100K_0402_1%

R2491.5K_0402_1%

@

1 2

D D

COMP/B_VGA16

Y/G_VGA16

C/R_VGA16

CRT_BLU16
CRT_GRN16
CRT_RED16

C C

B B

12

R694

150_0402_1%

BK_EN15

R1001~R1003

要W 150 ohm

CLK_MCH_3GPLL#17
CLK_MCH_3GPLL17

12

R699

150_0402_1%

CLK_DDC216
DAT_DDC216

VSYNC16
HSYNC16

LCD_CLK15
LCD_DAT15
LCD_EN30

12

LVDS_AC-42
LVDS_AC+42

LVDS_A0-42
LVDS_A1-42
LVDS_A2-42

LVDS_A0+42
LVDS_A1+42
LVDS_A2+42

時值為

+2.5VS

12

R704

150_0402_1%

為預留

R157

4.99K_0603_1%

LBKLT_CTL
BK_EN

R200 3K_0402_5%@
1 2
1 2

12

0_0402_5%

1 2

CLK_DDC2
DAT_DDC2

1 2

R149

255_0402_1%

LCTLA_CLK
LCTLB_DAT
LCD_CLK
LCD_DAT
LCD_EN

LVDS_AC­LVDS_AC+

LVDS_A0­LVDS_A1­LVDS_A2-

LVDS_A0+
LVDS_A1+
LVDS_A2+

R199

3K_0402_5%@

R689

AB29
AC29

H24
H25

A15
C16
A17

J18
B15
B16
B17

E24
E23
E21
D21
C20
B20
A19
B19
H21
G21

J20

E25
F25
C23
C22
F23
F22
F26
C33
C31
F28
F27

B30
B29
C25
C24

B34
B33
B32

A34
A33
B31

C29
D28
C27

C28
D27
C26

4

U48G

SDVOCTRL_DATA
SDVOCTRL_CLK
GCLKN
GCLKP

TVDAC_A
TVDAC_B
TVDAC_C
TV_REFSET
TV_IRTNA
TV_IRTNB
TV_IRTNC

DDCCLK
DDCDATA
BLUE
BLUE#
GREEN
GREEN#
RED
RED#
VSYNC
HSYNC
REFSET

LBKLT_CTL
LBKLT_EN
LCTLA_CLK
LCTLB_DATA
LDDC_CLK
LDDC_DATA
LVDD_EN
LIBG
LVBG
LVREFH
LVREFL

LACLKN
LACLKP
LBCLKN
LBCLKP

LADATAN0
LADATAN1
LADATAN2

LADATAP0
LADATAP1
LADATAP2

LBDATAN0
LBDATAN1
LBDATAN2

LBDATAP0
LBDATAP1
LBDATAP2

ALVISO_BGA1257

EXP_RXN0/SDVO_TVCLKIN#

MISCTVVGALVDS

EXP_RXN1/SDVO_INT#

EXP_RXN2/SDVO_FLDSTALL#

EXP_RXP0/SDVO_TVCLKIN

EXP_RXP1/SDVO_INT

EXP_RXP2/SDVO_FLDSTALL

EXP_TXN0/SDVOB_RED#

EXP_TXN1/SDVOB_GREEN#

EXP_TXN2/SDVOB_BLUE#

EXP_TXN3/SDVOB_CLKN
EXP_TXN4/SDVOC_RED#

EXP_TXN5/SDVOC_GREEN#

EXP_TXN6/SDVOC_BLUE#

EXP_TXN7/SDVOC_CLKN

PCI - EXPRESS GRAPHICS

EXP_TXP0/SDVOB_RED

EXP_TXP1/SDVOB_GREEN

EXP_TXP2/SDVOB_BLUE
EXP_TXP3/SDVOB_CLKP

EXP_TXP4/SDVOC_RED

EXP_TXP5/SDVOC_GREEN

EXP_TXP6/SDVOC_BLUE
EXP_TXP7/SDVOC_CLKP

EXP_COMPI

EXP_ICOMPO

EXP_RXN3
EXP_RXN4
EXP_RXN5
EXP_RXN6
EXP_RXN7
EXP_RXN8

EXP_RXN9
EXP_RXN10
EXP_RXN11
EXP_RXN12
EXP_RXN13
EXP_RXN14
EXP_RXN15

EXP_RXP3

EXP_RXP4

EXP_RXP5

EXP_RXP6

EXP_RXP7

EXP_RXP8

EXP_RXP9

EXP_RXP10
EXP_RXP11
EXP_RXP12
EXP_RXP13
EXP_RXP14
EXP_RXP15

EXP_TXN8

EXP_TXN9

EXP_TXN10
EXP_TXN11
EXP_TXN12
EXP_TXN13
EXP_TXN14
EXP_TXN15

EXP_TXP8

EXP_TXP9

EXP_TXP10
EXP_TXP11
EXP_TXP12
EXP_TXP13
EXP_TXP14
EXP_TXP15

D36
D34

E30
F34
G30
H34
J30
K34
L30
M34
N30
P34
R30
T34
U30
V34
W30
Y34

D30
E34
F30
G34
H30
J34
K30
L34
M30
N34
P30
R34
T30
U34
V30
W34

E32
F36
G32
H36
J32
K36
L32
M36
N32
P36
R32
T36
U32
V36
W32
Y36

D32
E36
F32
G36
H32
J36
K32
L36
M32
N36
P32
R36
T32
U36
V32
W36

PEGCOMP

3

R250

24.9_0603_1%~D
1 2

LBKLT_CTL

+1.5VS

+3VS

2

A

R854

@

1 2

0_0402_5%

5

U58

P

4

Y

G

NC7SZ14M5X_SOT23-5

3

+2.5VS

1 2
1 2
1 2
1 2
1 2
1 2

BIA 30

2

LCD_CLK

R154 2.2K_0402_5%

LCD_DAT

R153 2.2K_0402_5%

LCTLA_CLK

R160 2.2K_0402_5%

LCTLB_DAT

R159 2.2K_0402_5%

CLK_DDC2

R182 2.2K_0402_5%

DAT_DDC2

R181 2.2K_0402_5%

1

A A

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/03/11 2006/03/11

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

2

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, M/B LA-2831

401362

星@, 06, 2006

薑三月

1

10 59

D

of

5

U48F

K13

VTT0

J13

VTT1

K12

VTT2

W11

VTT3

V11

VTT4

U11

VTT5

T11

VTT6

R11

VTT7

P11

POWER

VTT8

N11

VTT9

M11

D D

+VCCP

1

1

+

C936 150U_D2_6.3VM

C C

B B

1

+

2

2

2

C250 2.2U_0805_10V6K

C635 4.7U_0805_6.3V6K

C937 150U_D2_6.3VM

1

C692

0.47U_0603_16V7K

2

1

1

C634

C632

2

2

0.47U_0603_16V7K

0.1U_0402_16V4Z

1

@

C159

C192

2

VTT10

L11

VTT11

K11

VTT12

W10

VTT13

V10

VTT14

U10

VTT15

T10

VTT16

R10

VTT17

P10

VTT18

N10

VTT19

M10

VTT20

K10

VTT21

J10

1

VTT22

Y9

VTT23

W9

VTT24

U9

VTT25

2

R9

VTT26

P9

VTT27

N9

VTT28

M9

VTT29

L9

VTT30

J9

VTT31

N8

VTT32

M8

VTT33

N7

VTT34

M7

VTT35

N6

VTT36

M6

VTT37

A6

VTT38

N5

VTT39

M5

VTT40

N4

VTT41

M4

VTT42

N3

VTT43

M3

VTT44

N2

VTT45

M2

VTT46

B2

VTT47

V1

VTT48

N1

VTT49

M1

VTT50

G1

VTT51

1

C633

2

0.22U_0603_10V7K

0.22U_0603_10V7K

ALVISO_BGA1257

+VCCP

0.1U_0402_16V4Z

1

@

@

C189

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z
1

1

@

@

C211

C210

2

2

VCCSM0
VCCSM1
VCCSM2
VCCSM3
VCCSM4
VCCSM5
VCCSM6
VCCSM7
VCCSM8

VCCSM9
VCCSM10
VCCSM11
VCCSM12
VCCSM13
VCCSM14
VCCSM15
VCCSM16
VCCSM17
VCCSM18
VCCSM19
VCCSM20
VCCSM21
VCCSM22
VCCSM23
VCCSM24
VCCSM25
VCCSM26
VCCSM27
VCCSM28
VCCSM29
VCCSM30
VCCSM31
VCCSM32
VCCSM33
VCCSM34
VCCSM35
VCCSM36
VCCSM37
VCCSM38
VCCSM39
VCCSM40
VCCSM41
VCCSM42
VCCSM43
VCCSM44
VCCSM45
VCCSM46
VCCSM47
VCCSM48
VCCSM49
VCCSM50
VCCSM51
VCCSM52
VCCSM53
VCCSM54
VCCSM55
VCCSM56
VCCSM57
VCCSM58
VCCSM59
VCCSM60
VCCSM61
VCCSM62
VCCSM63
VCCSM64

0.1U_0402_16V4Z

1

2

AM37
AH37
AP29
AD28
AD27
AC27
AP26
AN26
AM26
AL26
AK26
AJ26
AH26
AG26
AF26
AE26
AP25
AN25
AM25
AL25
AK25
AJ25
AH25
AG25
AF25
AE25
AE24
AE23
AE22
AE21
AE20
AE19
AE18
AE17
AE16
AE15
AE14
AP13
AN13
AM13
AL13
AK13
AJ13
AH13
AG13
AF13
AE13
AP12
AN12
AM12
AL12
AK12
AJ12
AH12
AG12
AF12
AE12
AD11
AC11
AB11
AB10
AB9
AP8
AM1
AE1

V1.8_DDR_CAP1
V1.8_DDR_CAP2
V1.8_DDR_CAP5

V1.8_DDR_CAP6
V1.8_DDR_CAP4
V1.8_DDR_CAP3

C163

V1.8_DDR_CAP1
V1.8_DDR_CAP2
V1.8_DDR_CAP5

Note : All VCCSM pin
shorted internally.

V1.8_DDR_CAP6
V1.8_DDR_CAP4
V1.8_DDR_CAP3

Note: Place near chip.

10U_1206_6.3V6M

C729

C757

1

1

2

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

C175

2

2

C641

10U_1206_6.3V6M

C194

+1.8V

C767

4

W=20 mils

U48E

+VCCP

C794

+1.8V

C228

0.1U_0402_16V7K

1

2

1

C623

2

10U_1206_6.3V6M

+1.5VS_DPLLA
+1.5VS_DPLLB

+1.5VS_HPLL
+1.5VS_MPLL

0.1U_0402_16V4Z

C266

0.1U_0402_16V4Z

+1.5VS

1

1

2

0.1U_0402_16V7K

1

2

1

+

2

0.1U_0402_16V4Z

1

2

1

C793

C775

2

2

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K
C702

C642

1

1

2

2

330U_D2E_2.5VM

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

C209

C214

2

2

T29

VCC0

R29

VCC1

N29

VCC2

M29

VCC3

K29

VCC4

J29

1

2

VCC5

V28

VCC6

U28

VCC7

T28

VCC8

R28

VCC9

P28

VCC10

N28

VCC11

M28

VCC12

L28

VCC13

K28

VCC14

J28

VCC15

H28

VCC16

G28

VCC17

V27

VCC18

U27

VCC19

T27

VCC20

R27

VCC21

P27

VCC22

N27

VCC23

M27

VCC24

L27

VCC25

K27

VCC26

J27

VCC27

H27

VCC28

K26

VCC29

H26

VCC30

K25

VCC31

J25

VCC32

K24

VCC33

K23

VCC34

K22

VCC35

K21

VCC36

W20

VCC37

U20

VCC38

T20

VCC39

K20

VCC40

V19

VCC41

U19

VCC42

K19

VCC43

W18

VCC44

V18

VCC45

T18

VCC46

K18

VCC47

K17

VCC48

AC1

VCCD_HMPLL1

AC2

VCCD_HMPLL2

B23

VCCA_DPLLA

C35

VCCA_DPLLB

AA1

VCCA_HPLL

AA2

VCCA_MPLL

ALVISO_BGA1257

VCC_SYNC

1

C740

2

10U_1206_6.3V6M

POWER

+2.5VS

1

C224

2

0.1U_0402_16V4Z

3

VCCA_TVDACA0
VCCA_TVDACA1
VCCA_TVDACB0
VCCA_TVDACB1
VCCA_TVDACC0
VCCA_TVDACC1

VCCA_TVBG

VSSA_TVBG

VCCD_TVDAC

VCCDQ_TVDAC

VCCD_LVDS0
VCCD_LVDS1
VCCD_LVDS2

VCCA_LVDS

VCCHV0
VCCHV1
VCCHV2

VCCTX_LVDS0
VCCTX_LVDS1
VCCTX_LVDS2

VCCA_SM0
VCCA_SM1
VCCA_SM2
VCCA_SM3

VCC3G0
VCC3G1
VCC3G2
VCC3G3
VCC3G4
VCC3G5
VCC3G6

VCCA_3GPLL0
VCCA_3GPLL1
VCCA_3GPLL2

VCCA_3GBG
VSSA_3GBG

VCC_SYNC

VCCA_CRTDAC0
VCCA_CRTDAC1

VSSA_CRTDAC

12

R144
0_0402_5%

12

R145

0_0402_5%@

F17
E17
D18
C18
F18
E18

H18
G18

D19
H17

B26
B25
A25

A35
B22

B21
A21

B28
A28
A27

AF20
AP19
AF19
AF18

AE37
W37
U37
R37
N37
L37
J37

Y29
Y28
Y27

F37
G37

H20
F19

E19
G19

1

C212

2

0.1U_0402_16V4Z

+1.5VS_PM

R722 0_0603_5%

+2.5VS_PM

R745 0_0603_5%

+2.5VS

4.7U_0805_6.3V6K

1

C225

2

0.1U_0402_16V4Z

VCC_SYNC

C743

0.1U_0402_16V4Z
1

1

C237

C229

2

2

1

2

C731

1

C732

2

0.1U_0402_16V4Z

1 2

1 2

C774

1

+

C739

2

100U_D2_6.3VM

1

1

2

2

0.1U_0402_16V4Z

0.022U_0402_16V7K

0.1U_0402_16V4Z
1

C235

2

+3VS

0.022U_0402_16V7K

1

2

C217

1

2

C804

220U_D2_4VM

+2.5VS_CRTDAC

C744

GND_CRTDAC

0.1U_0402_16V4Z
1

C158

2

1

1

2

2

C218

0.022U_0402_16V7K

0.1U_0402_16V4Z
C208 0.022U_0402_16V7K

+1.5VS

+2.5VS

R724 0_0603_5%

1 2

1

C773

0.1U_0402_16V4Z

2

1

1

+

C798

C797

2

2

10U_1206_6.3V6M

CHB1608U301_0603

1 2

+VCCP

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
1

1

C190

C149

2

2

2

C639

0.1U_0402_16V4Z
+2.5VS

1

2

10U_1206_6.3V6M

L81

Close B26,B25,A25

+1.5VS

1

1

2

2

C759

C638 0.022U_0402_16V7K

1

C791

C267

2

0.1U_0402_16V4Z

10U_1206_6.3V6M

0.5--->1.0 ADD

+1.5VS_PM

0.1U_0402_16V4Z

1

2

L50

L26

R753

1 2

0.5_0805_1%

1

2

Route VSSA3GBG gnd from GMCH to
decoupling cap ground lead and
then connect to the gnd plane.

10U_1206_6.3V6M

1

2

C783

12

0_0603_5%

12

0_0603_5%

3GRLL_R

CHB1608U301_0603

1

C790

0.1U_0402_16V4Z

2

+2.5VS_PM

1

2

0.01U_0402_16V7K

L57

0_0603_5%

C782

1

2

0.1U_0402_16V4Z

+1.5VS+1.5VS_3GPLL

L59

12

C805

12

C233

10U_1206_6.3V6M

1

2

0.1U_0402_16V4Z
+2.5VS+2.5VS_3GBG

+2.5VS

1

1

C220

2

2

0.1U_0402_16V4Z

+1.5VS

1

C364

2

0.1U_0402_16V4Z

1

C801

0.1U_0402_16V4Z

2

1

1

+

C965

+1.5VS

C745

0.1U_0402_16V4Z

2

330U_D2E_2.5VM

1

2

L58

CHB1608U301_0603

+1.5VS

A A

1 2

C803

+VCCP +VCCP+2.5VS +3VS

R148

1 2

10K_0402_5%

@

330U_D2E_2.5VM

1

C789

+

2

D3

1N4148_SOD80

@

5

0.1U_0402_16V4Z

1

2

12

+1.5VS

CHB1608U301_0603

1 2

L15

C612

R140

1 2

10K_0402_5%

@

+1.5VS_HPLL

330U_D2E_2.5VM

1

C636

+

2

1N4148_SOD80

CHB1608U301_0603

0.1U_0402_16V4Z

+1.5VS

1

2

D2

12

@

1 2

4

+1.5VS_MPLL

L16

1

1

+

C613

C637

2

2

0.1U_0402_16V4Z

330U_D2E_2.5VM

+1.5VS

CHB1608U301_0603

1 2

+1.5VS_DPLLA+1.5VS_DPLLB

L48

0.1U_0402_16V4Z

330U_D2E_2.5VM

1

C749

C748

1

+

2

2

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

+2.5VS +2.5VS_CRTDAC

2005/03/11 2006/03/11

L80

CHB1608U301_0603

1 2

0.5--->1.0 ADD

Compal Secret Data

Deciphered Date

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, M/B LA-2831

401362

星@, 06, 2006

薑三月

of

1

11 59

D

5

4

3

2

1

+VCCP

W12

W13

AA12
AA13

W14

AA14
AB14

W15

AA15
AB15

W16

AA16
AB16

AA17
AB17
AA18
AB18
AA19
AB19
AA20
AB20

AA21
AB21

AA22
AB22

AA23
AB23

AA24
AB24

AA25
AB25

AA26
AB26

W25

W26

L12
M12
N12
P12
R12

T12
U12
V12

L13
M13
N13
P13
R13

T13
U13
V13

Y12
Y13

L14
M14
N14
P14
R14

T14
U14
V14

Y14

L15
M15
N15
P15
R15

T15
U15
V15

Y15

L16
M16
N16
P16
R16

T16
U16
V16

Y16

R17
Y17

R21
Y21

Y22

Y23

Y24

Y25

Y26

V25

L26
M26
N26
P26
R26

T26
U26
V26

5

U48H

VTT_NCTF17
VTT_NCTF16
VTT_NCTF15
VTT_NCTF14
VTT_NCTF13
VTT_NCTF12
VTT_NCTF11
VTT_NCTF10
VTT_NCTF9
VTT_NCTF8
VTT_NCTF7
VTT_NCTF6
VTT_NCTF5
VTT_NCTF4
VTT_NCTF3
VTT_NCTF2
VTT_NCTF1
VTT_NCTF0

VSS_NCTF68
VSS_NCTF67
VSS_NCTF66
VSS_NCTF65
VSS_NCTF64
VSS_NCTF63
VSS_NCTF62
VSS_NCTF61
VSS_NCTF60
VSS_NCTF59
VSS_NCTF58
VSS_NCTF57
VSS_NCTF56
VSS_NCTF55
VSS_NCTF54
VSS_NCTF53
VSS_NCTF52
VSS_NCTF51
VSS_NCTF50
VSS_NCTF49
VSS_NCTF48
VSS_NCTF47
VSS_NCTF46
VSS_NCTF45
VSS_NCTF44
VSS_NCTF43
VSS_NCTF42
VSS_NCTF41
VSS_NCTF40
VSS_NCTF39
VSS_NCTF38
VSS_NCTF37
VSS_NCTF36
VSS_NCTF35
VSS_NCTF34
VSS_NCTF33
VSS_NCTF32
VSS_NCTF31
VSS_NCTF30
VSS_NCTF29
VSS_NCTF28
VSS_NCTF27
VSS_NCTF26
VSS_NCTF25
VSS_NCTF24
VSS_NCTF23
VSS_NCTF22
VSS_NCTF21
VSS_NCTF20
VSS_NCTF19
VSS_NCTF18
VSS_NCTF17
VSS_NCTF16
VSS_NCTF15
VSS_NCTF14
VSS_NCTF13
VSS_NCTF12
VSS_NCTF11
VSS_NCTF10
VSS_NCTF9
VSS_NCTF8
VSS_NCTF7
VSS_NCTF6
VSS_NCTF5
VSS_NCTF4
VSS_NCTF3
VSS_NCTF2
VSS_NCTF1
VSS_NCTF0

VCC_NCTF10
VCC_NCTF9
VCC_NCTF8
VCC_NCTF7
VCC_NCTF6
VCC_NCTF5
VCC_NCTF4
VCC_NCTF3
VCC_NCTF2
VCC_NCTF1
VCC_NCTF0

ALVISO_BGA1257

VCCSM_NCTF31
VCCSM_NCTF30
VCCSM_NCTF29
VCCSM_NCTF28
VCCSM_NCTF27
VCCSM_NCTF26
VCCSM_NCTF25
VCCSM_NCTF24
VCCSM_NCTF23
VCCSM_NCTF22
VCCSM_NCTF21
VCCSM_NCTF20
VCCSM_NCTF19
VCCSM_NCTF18
VCCSM_NCTF17
VCCSM_NCTF16
VCCSM_NCTF15
VCCSM_NCTF14
VCCSM_NCTF13
VCCSM_NCTF12
VCCSM_NCTF11
VCCSM_NCTF10

VCCSM_NCTF9
VCCSM_NCTF8
VCCSM_NCTF7
VCCSM_NCTF6
VCCSM_NCTF5
VCCSM_NCTF4
VCCSM_NCTF3
VCCSM_NCTF2
VCCSM_NCTF1
VCCSM_NCTF0

VCC_NCTF78
VCC_NCTF77
VCC_NCTF76
VCC_NCTF75
VCC_NCTF74
VCC_NCTF73
VCC_NCTF72
VCC_NCTF71
VCC_NCTF70

NCTF

VCC_NCTF69
VCC_NCTF68
VCC_NCTF67
VCC_NCTF66
VCC_NCTF65
VCC_NCTF64
VCC_NCTF63
VCC_NCTF62
VCC_NCTF61
VCC_NCTF60
VCC_NCTF59
VCC_NCTF58
VCC_NCTF57
VCC_NCTF56
VCC_NCTF55
VCC_NCTF54
VCC_NCTF53
VCC_NCTF52
VCC_NCTF51
VCC_NCTF50
VCC_NCTF49
VCC_NCTF48
VCC_NCTF47
VCC_NCTF46
VCC_NCTF45
VCC_NCTF44
VCC_NCTF43
VCC_NCTF42
VCC_NCTF41
VCC_NCTF40
VCC_NCTF39
VCC_NCTF38
VCC_NCTF37
VCC_NCTF36
VCC_NCTF35
VCC_NCTF34
VCC_NCTF33
VCC_NCTF32
VCC_NCTF31
VCC_NCTF30
VCC_NCTF29
VCC_NCTF28
VCC_NCTF27
VCC_NCTF26
VCC_NCTF25
VCC_NCTF24
VCC_NCTF23
VCC_NCTF22
VCC_NCTF21
VCC_NCTF20
VCC_NCTF19
VCC_NCTF18
VCC_NCTF17
VCC_NCTF16
VCC_NCTF15
VCC_NCTF14
VCC_NCTF13
VCC_NCTF12
VCC_NCTF11

D D

C C

B B

A A

AB12
AC12
AD12
AB13
AC13
AD13
AC14
AD14
AC15
AD15
AC16
AD16
AC17
AD17
AC18
AD18
AC19
AD19
AC20
AD20
AC21
AD21
AC22
AD22
AC23
AD23
AC24
AD24
AC25
AD25
AC26
AD26

L17
M17
N17
P17
T17
U17
V17
W17
L18
M18
N18
P18
R18
Y18
L19
M19
N19
P19
R19
Y19
L20
M20
N20
P20
R20
Y20
L21
M21
N21
P21
T21
U21
V21
W21
L22
M22
N22
P22
R22
T22
U22
V22
W22
L23
M23
N23
P23
R23
T23
U23
V23
W23
L24
M24
N24
P24
R24
T24
U24
V24
W24
L25
M25
N25
P25
R25
T25
U25

+1.8V

C236

+VCCP

C191

0.1U_0402_10V6K

0.1U_0402_10V6K

1

1

C178

C241

2

2

0.1U_0402_10V6K

0.1U_0402_10V6K

1

1

C223

C188

2

2

0.1U_0402_10V6K
1

1

C275

C274

2

2

0.1U_0402_10V6K

0.1U_0402_10V6K

0.1U_0402_10V6K
1

1

C255

C726

2

2

0.1U_0402_10V6K

0.1U_0402_10V6K

1

1

C272

C242

2

2

+VCCP

0.1U_0402_10V6K

0.1U_0402_10V6K
1

1

C276

C156

2

2

4

0.1U_0402_10V6K

1

1

C754

2

2

U48I

Y1

VSS271

D2

VSS270

G2

VSS269

J2

VSS268

L2

VSS260

P2

VSS259

T2

VSS258

V2

VSS257

AD2

VSS256

AE2

VSS255

AH2

VSS254

AL2

VSS253

AN2

VSS252

A3

C3
AA3
AB3

AC3

AJ3

C4

H4

L4

P4

U4

Y4
AF4

AN4

E5

W5
AL5
AP5

B6
J6
L6
P6
T6

AA6

AC6

AE6
AJ6

G7

V7

AA7

AG7

AK7

AN7

C8
E8
L8
P8
Y8

AL8

A9
H9
K9
T9
V9

AA9

AC9

AE9

AH9
AN9

D10

L10
Y10

AA10

F11
H11

+VCCP

0.1U_0402_10V6K

1

1

C273

2

2

0.1U_0402_10V6K
1

+

C606

2

330U_D2E_2.5VM_R9

Y11

C610

10U_0805_10V4Z

2

1

C609

@

ALVISO_BGA1257

22U_1206_6.3V6M

0.1U_0402_10V6K

2

1

VSS

VSS251
VSS250
VSS249
VSS248
VSS247
VSS246
VSS245
VSS244
VSS243
VSS242
VSS241
VSS240
VSS239
VSS238
VSS237
VSS236
VSS235
VSS234
VSS233
VSS232
VSS231
VSS230
VSS229
VSS228
VSS227
VSS226
VSS225
VSS224
VSS223
VSS222
VSS221
VSS220
VSS219
VSS218
VSS217
VSS216
VSS215
VSS214
VSS213
VSS212
VSS211
VSS210
VSS209
VSS208
VSS207
VSS206
VSS205
VSS204
VSS203
VSS202
VSS201
VSS200
VSS199
VSS198
VSS197
VSS196

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

B36

VSSALVDS

AA11

VSS195

AF11

VSS194

AG11

VSS193

AJ11

VSS192

AL11

VSS191

AN11

VSS190

B12

VSS189

D12

VSS188

J12

VSS187

A14

VSS186

B14

VSS185

F14

VSS184

J14

VSS183

K14

VSS182

AG14

VSS181

AJ14

VSS180

AL14

VSS179

AN14

VSS178

C15

VSS177

K15

VSS176

A16

VSS175

D16

VSS174

H16

VSS173

K16

VSS172

AL16

VSS171

C17

VSS170

G17

VSS169

AF17

VSS168

AJ17

VSS167

AN17

VSS166

A18

VSS165

B18

VSS164

U18

VSS163

AL18

VSS162

C19

VSS161

H19

VSS160

J19

VSS159

T19

VSS158

W19

VSS157

AG19

VSS156

AN19

VSS155

A20

VSS154

D20

VSS153

E20

VSS152

F20

VSS151

G20

VSS150

V20

VSS149

AK20

VSS148

C21

VSS147

F21

VSS146

AF21

VSS145

AN21

VSS144

A22

VSS143

D22

VSS142

E22

VSS141

J22

VSS140

AH22

VSS139

AL22

VSS138

H23

VSS137

AF23

VSS136

B24

VSS135

D24

VSS134

F24

VSS133

J24

VSS132

AG24

VSS131

AJ24

VSS130

2005/03/01 2006/03/01

Compal Secret Data

Deciphered Date

U48J

AL24

VSS267

AN24

VSS266

A26

VSS265

E26

VSS264

G26

VSS263

J26

VSS262

B27

VSS261

E27

VSS129

G27

VSS128

W27

VSS127

AA27

VSS126

AB27

VSS125
VSS124
VSS123
VSS122
VSS121
VSS120
VSS119
VSS118
VSS117
VSS116
VSS115
VSS114
VSS113
VSS112
VSS111
VSS110
VSS109
VSS108
VSS107
VSS106
VSS105
VSS104
VSS103
VSS102
VSS101
VSS100
VSS99
VSS98
VSS97
VSS96
VSS95
VSS94
VSS93
VSS92
VSS91
VSS90
VSS89
VSS88
VSS87
VSS86
VSS85
VSS84
VSS83
VSS82
VSS81
VSS80
VSS79
VSS78
VSS77
VSS76
VSS75
VSS74
VSS73
VSS72
VSS71
VSS70
VSS69
VSS68

VSS

Title

Size Document Number Rev

星@, 06, 2006

Date: Sheet

AF27

AG27

AJ27
AL27
AN27

E28

W28
AA28
AB28
AC28

A29
D29
E29
F29
G29
H29

L29
P29
U29
V29

W29
AA29
AD29

AG29

AJ29

AM29

C30

Y30
AA30
AB30
AC30
AE30
AP30

D31

E31

F31

G31

H31

J31

K31

L31

M31

N31

P31

R31

T31

U31

V31

W31

AD31

AG31

AL31

A32

C32

Y32
AA32
AB32

ALVISO_BGA1257

2

AC32

VSS67

AD32

VSS66

AJ32

VSS65

AN32

VSS64

D33

VSS63

E33

VSS62

F33

VSS61

G33

VSS60

H33

VSS59

J33

VSS58

K33

VSS57

L33

VSS56

M33

VSS55

N33

VSS54

P33

VSS53

R33

VSS52

T33

VSS51

U33

VSS50

V33

VSS49

W33

VSS48

AD33

VSS47

AF33

VSS46

AL33

VSS45

C34

VSS44

AA34

VSS43

AB34

VSS42

AC34

VSS41

AD34

VSS40

AH34

VSS39

AN34

VSS38

B35

VSS37

D35

VSS36

E35

VSS35

F35

VSS34

G35

VSS33

H35

VSS32

J35

VSS31

K35

VSS30

L35

VSS29

M35

VSS28

N35

VSS27

P35

VSS26

R35

VSS25

T35

VSS24

U35

VSS23

V35

VSS22

W35

VSS21

Y35

VSS20

AE35

VSS19

C36

VSS18

AA36

VSS17

AB36

VSS16

AC36

VSS15

AD36

VSS14

AE36

VSS13

AF36

VSS12

AJ36

VSS11

AL36

VSS10

AN36

VSS9

E37

VSS8

H37

VSS7

K37

VSS6

M37

VSS5

P37

VSS4

T37

VSS3

V37

VSS2

Y37

VSS1

AG37

VSS0

Compal Electronics, Inc.

SCHEMATIC, M/B LA-2831

401362

薑三月

1

12 59

D

of

A

DDR_A_D[0..63]9
DDR_A_DM[0..7]9
DDR_A_DQS[0..7]9
DDR_A_MA[0..13]9
DDR_A_DQS#[0..7]9

1 1

2 2

3 3

4 4

+1.8V

+0.9VS

0.1U_0402_16V4Z~D

2.2U_0805_10V6K~D
1

2

0.1U_0402_16V4Z~D

1

2

C320

DDR_A_BS#2
DDR_A_MA12
DDR_A_MA9
DDR_A_MA8

DDR_A_MA5
DDR_A_MA1
DDR_A_MA10
DDR_A_BS#0

DDR_A_WE#
DDR_A_CAS#
DDR_SCS#1
M_ODT1

2.2U_0805_10V6K~D

C277

0.1U_0402_16V4Z~D
1

2

1

2

C314

56_0804_8P4R_5%

56_0804_8P4R_5%

DDR_A_D[0..63]
DDR_A_DM[0..7]
DDR_A_DQS[0..7]
DDR_A_MA[0..13]
DDR_A_DQS#[0..7]

2.2U_0805_10V6K~D

C319

1

1

2

2

0.1U_0402_16V4Z~D
C335

C313

1

2

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

1

2

C294

RP59

RP52

56_0804_8P4R_5%

RP50

2.2U_0805_10V6K~D

C347

1

2

0.1U_0402_16V4Z~D
C303

1

2

0.1U_0402_16V4Z~D

1

2

C268

+0.9VS

18
27
36
45

56_0804_8P4R_5%

18
27
36
45

56_0804_8P4R_5%

18
27
36
45

56_0804_8P4R_5%

1 2

R236 56_0402_5%

1 2

R747 56_0402_5%

C253

0.1U_0402_16V4Z~D

1

2

C787

RP16

RP14

RP12

2.2U_0805_10V6K~D
C334

1

2

C285

1

2

0.1U_0402_16V4Z~D

1

2

C766

DDR_A_MA4

18

DDR_A_MA6

27

DDR_A_MA7

36

DDR_CKE1_DIMMA

45

DDR_A_BS#1

18

DDR_A_MA0

27

DDR_A_MA3

36

DDR_A_MA2

45

DDR_A_MA13

18

M_ODT0

27

DDR_SCS#0

36

DDR_A_RAS#

45

DDR_A_MA11
DDR_CKE0_DIMMA

1

+

C349
330U_D2E_2.5VM_R9

2

0.1U_0402_16V4Z~D

1

2

C772

B

@

DDR_CLK0

10P_0402_50V8J~D

1

C376

2

DDR_CLK0#

@

DDR_CLK1

10P_0402_50V8J~D

1

C203

2

DDR_CLK1#

0.1U_0402_16V4Z~D

1

2

C781

C

DDR_A_D0
DDR_A_D1

DDR_A_DQS#0
DDR_A_DQS0

DDR_A_D2
DDR_A_D3

DDR_A_D8
DDR_A_D9

DDR_A_DQS#1 DDR_CLK0
DDR_A_DQS1

DDR_A_D10
DDR_A_D11

DDR_A_D16
DDR_A_D17

DDR_A_DQS#2
DDR_A_DQS2

DDR_A_D18
DDR_A_D19

DDR_A_D24
DDR_A_D25

DDR_A_DM3

DDR_A_D26
DDR_A_D27

DDR_CKE0_DIMMA8

DDR_A_BS#29

DDR_A_BS#09
DDR_A_WE#9

DDR_A_CAS#9

DDR_SCS#18

M_ODT18

CK_SDATA14,17
CK_SCLK14,17

DDR_CKE0_DIMMA

DDR_A_BS#2
DDR_A_MA12

DDR_A_MA9 DDR_A_MA7
DDR_A_MA8

DDR_A_MA5
DDR_A_MA3
DDR_A_MA1

DDR_A_MA10
DDR_A_BS#0
DDR_A_WE#

DDR_A_CAS#
DDR_SCS#1

M_ODT1
DDR_A_D32

DDR_A_D33
DDR_A_DQS#4

DDR_A_DQS4
DDR_A_D34

DDR_A_D35
DDR_A_D40

DDR_A_D41
DDR_A_DM5
DDR_A_D42

DDR_A_D43
DDR_A_D48

DDR_A_D49

DDR_A_DQS#6
DDR_A_DQS6

DDR_A_D50
DDR_A_D51

DDR_A_D56
DDR_A_D57

DDR_A_DM7
DDR_A_D58

DDR_A_D59
CK_SDATA

CK_SCLK

+3VS

+1.8V +1.8V

JDIM1
1
3
5
7
9

11
13
15
17
19
21
23
25
27
29
31
33
35
37
39

41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97

99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199

0.1U_0402_16V4Z~D
C90

1

2

201

2.2U_0805_10V6K~D
C92

1

2

FOX_ASOA426-M2R-TR

VREF
VSS
DQ0
DQ1
VSS
DQS0#
DQS0
VSS
DQ2
DQ3
VSS
DQ8
DQ9
VSS
DQS1#
DQS1
VSS
DQ10
DQ11
VSS

VSS
DQ16
DQ17
VSS
DQS2#
DQS2
VSS
DQ18
DQ19
VSS
DQ24
DQ25
VSS
DM3
NC
VSS
DQ26
DQ27
VSS
CKE0
VDD
NC
BA2
VDD
A12
A9
A8
VDD
A5
A3
A1
VDD
A10/AP
BA0
WE#
VDD
CAS#
NC/S1#
VDD
NC/ODT1
VSS
DQ32
DQ33
VSS
DQS4#
DQS4
VSS
DQ34
DQ35
VSS
DQ40
DQ41
VSS
DM5
VSS
DQ42
DQ43
VSS
DQ48
DQ49
VSS
NC,TEST
VSS
DQS6#
DQS6
VSS
DQ50
DQ51
VSS
DQ56
DQ57
VSS
DM7
VSS
DQ58
DQ59
VSS
SDA
SCL
VDDSPD
GND

DIMMA

D

DQ4
DQ5
VSS
DM0
VSS
DQ6
DQ7

VSS
DQ12
DQ13

VSS

DM1

VSS

CK0

CK0#

VSS
DQ14
DQ15

VSS

VSS
DQ20
DQ21

VSS

DM2

VSS
DQ22
DQ23

VSS
DQ28
DQ29

VSS

DQS3#

DQS3

VSS
DQ30
DQ31

VSS

NC/CKE1

VDD

NC/A15
NC/A14

VDD

VDD

VDD
RAS#

VDD
ODT0

NC/A13

VDD

VSS
DQ36
DQ37

VSS

DM4

VSS
DQ38
DQ39

VSS
DQ44
DQ45

VSS

DQS5#

DQS5

VSS
DQ46
DQ47

VSS
DQ52
DQ53

VSS

CK1

CK1#

VSS

DM6

VSS
DQ54
DQ55

VSS
DQ60
DQ61

VSS

DQS7#

DQS7

VSS
DQ62
DQ63

VSS

SAO

GND

VSS

A11

BA1
S0#

SA1

E

V_DDR_MCH_REF

2

DDR_A_D4

4

DDR_A_D5

6
8

DDR_A_DM0

10
12

DDR_A_D6

14

DDR_A_D7

16
18

DDR_A_D12

20

DDR_A_D13

22
24

DDR_A_DM1

26
28
30

DDR_CLK0#

32
34

DDR_A_D14

36

DDR_A_D15

38
40

42

DDR_A_D20

44

DDR_A_D21

46
48
50

NC

A7
A6

A4
A2
A0

NC

52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202

DDR_A_DM2
DDR_A_D22

DDR_A_D23
DDR_A_D28

DDR_A_D29
DDR_A_DQS#3

DDR_A_DQS3
DDR_A_D30

DDR_A_D31
DDR_CKE1_DIMMA

DDR_A_MA11
DDR_A_MA6
DDR_A_MA4

DDR_A_MA2
DDR_A_MA0

DDR_A_BS#1
DDR_A_RAS#
DDR_SCS#0

M_ODT0
DDR_A_MA13

DDR_A_D36
DDR_A_D37

DDR_A_DM4
DDR_A_D38

DDR_A_D39
DDR_A_D44

DDR_A_D45
DDR_A_DQS#5

DDR_A_DQS5
DDR_A_D46

DDR_A_D47
DDR_A_D52

DDR_A_D53
DDR_CLK1

DDR_CLK1#
DDR_A_DM6
DDR_A_D54

DDR_A_D55
DDR_A_D60

DDR_A_D61
DDR_A_DQS#7

DDR_A_DQS7
DDR_A_D62

DDR_A_D63

10K_0402_5%~D

10K_0402_5%~D

12

R118

R111

1 2

0.1U_0402_16V4Z~D

2.2U_0805_10V6K~D

1

C400

2

DDR_CLK0 8
DDR_CLK0# 8

DDR_CKE1_DIMMA 8

DDR_A_BS#1 9
DDR_A_RAS# 9

DDR_SCS#0 8

M_ODT0 8

DDR_CLK1 8
DDR_CLK1# 8

1

2

V_DDR_MCH_REF 14

C398

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2005/03/11 2006/03/11

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

星@, 06, 2006

薑三月

D

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, M/B LA-2831

401362

13 59

E

D

of

A

DDR_B_D[0..63]9
DDR_B_DM[0..7]9
DDR_B_DQS[0..7]9
DDR_B_MA[0..13]9
DDR_B_DQS#[0..7]9

1 1

2 2

3 3

4 4

+1.8V

2.2U_0805_10V6K~D

0.1U_0402_16V4Z~D

+0.9VS

0.1U_0402_16V4Z~D

DDR_B_BS#0
DDR_B_MA10
DDR_B_MA1
DDR_B_MA3

DDR_B_RAS#
DDR_SCS#2
M_ODT2
DDR_B_MA13

M_ODT3
DDR_SCS#3
DDR_B_CAS#
DDR_B_WE#

1

2

1

2

1

2

C770

56_0804_8P4R_5%

A

DDR_B_D[0..63]
DDR_B_DM[0..7]
DDR_B_DQS[0..7]
DDR_B_MA[0..13]
DDR_B_DQS#[0..7]

2.2U_0805_10V6K~D

C337

C256

1

2

0.1U_0402_16V4Z~D

C283

C304

1

2

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

1

1

2

2

C308

RP15

56_0804_8P4R_5%

RP51
1 8
2 7
3 6
4 5

RP13

56_0804_8P4R_5%

2.2U_0805_10V6K~D
1

2

0.1U_0402_16V4Z~D
1

2

0.1U_0402_16V4Z~D

1

2

C776

+0.9VS

18
27
36
45

56_0804_8P4R_5%

18
27
36
45

56_0804_8P4R_5%

R237 56_0402_5%
R244 56_0402_5%

2.2U_0805_10V6K~D

C321

0.1U_0402_16V4Z~D

C271

0.1U_0402_16V4Z~D

C780

1 8
2 7
3 6
4 5

56_0804_8P4R_5%

1 2
1 2

RP60

RP53

1

2

1

2

1

2

RP17

C784

C344

C310

2.2U_0805_10V6K~D

0.1U_0402_16V4Z~D

1

2

18
27
36
45

18
27
36
45

B

1

C257

1

+

2

2

0.1U_0402_16V4Z~D

1

2

C295

C270

DDR_B_MA5
DDR_B_MA8
DDR_B_MA9
DDR_B_MA12

DDR_CKE3_DIMMB
DDR_B_MA11
DDR_B_MA7
DDR_B_MA6

DDR_B_MA4
DDR_B_MA2
DDR_B_MA0
DDR_B_BS#1

DDR_B_BS#2
DDR_CKE2_DIMMB

B

C299
330U_D2E_2.5VM_R9

0.1U_0402_16V4Z~D

1

2

C316

C

@

DDR_CLK3

10P_0402_50V8J~D

1

C380

2

DDR_CLK3#

@

DDR_CLK4

10P_0402_50V8J~D

1

C204

2

DDR_CLK4#

Layout Note:
Place these resistor
closely JDIM1,all
trace length<750 mil

Layout Note:
Place these resistor
closely JDIM1,all
trace length
Max=1.3"

C

D

DDR_CKE2_DIMMB8

DDR_B_BS#29

DDR_B_BS#09
DDR_B_WE#9

DDR_B_CAS#9

DDR_SCS#38

CK_SDATA13,17
CK_SCLK13,17

E

DDR_B_D0
DDR_B_D1

DDR_B_DQS#0
DDR_B_DQS0

DDR_B_D2
DDR_B_D3

DDR_B_D8
DDR_B_D9

DDR_B_DQS#1
DDR_B_DQS1

DDR_B_D10
DDR_B_D11

DDR_B_D16
DDR_B_D17

DDR_B_DQS#2
DDR_B_DQS2

DDR_B_D18
DDR_B_D19

DDR_B_D24
DDR_B_D25

DDR_B_DM3

DDR_B_D26
DDR_B_D27

DDR_CKE2_DIMMB

DDR_B_BS#2
DDR_B_MA12

DDR_B_MA9
DDR_B_MA8

DDR_B_MA5
DDR_B_MA3
DDR_B_MA1

DDR_B_MA10
DDR_B_BS#0
DDR_B_WE#

DDR_B_CAS#

M_ODT38

M_ODT3
DDR_B_D32

DDR_B_D33
DDR_B_DQS#4

DDR_B_DQS4
DDR_B_D34

DDR_B_D35
DDR_B_D40

DDR_B_D41
DDR_B_DM5
DDR_B_D42

DDR_B_D43
DDR_B_D48

DDR_B_D49

DDR_B_DQS#6
DDR_B_DQS6

DDR_B_D50
DDR_B_D51

DDR_B_D56
DDR_B_D57

DDR_B_DM7
DDR_B_D58

DDR_B_D59
CK_SDATA

CK_SCLK

+3VS

+1.8V +1.8V

2.2U_0805_10V6K~D

0.1U_0402_16V4Z~D
C93

C91

1

1

2

2

F

JDIM2

1

VREF

3

VSS

5

DQ0

7

DQ1

9

VSS

11

DQS0#

13

DQS0

15

VSS

17

DQ2

19

DQ3

21

VSS

23

DQ8

25

DQ9

27

VSS

29

DQS1#

31

DQS1

33

VSS

35

DQ10

37

DQ11

39

VSS

41

VSS

43

DQ16

45

DQ17

47

VSS

49

DQS2#

51

DQS2

53

VSS

55

DQ18

57

DQ19

59

VSS

61

DQ24

63

DQ25

65

VSS

67

DM3

69

NC

71

VSS

73

DQ26

75

DQ27

77

VSS

79

CKE0

81

VDD

83

NC

85

BA2

87

VDD

89

A12

91

A9

93

A8

95

VDD

97

A5

99

A3

101

A1

103

VDD

105

A10/AP

107

BA0

109

WE#

111

VDD

113

CAS#

115

NC/S1#

117

VDD

119

NC/ODT1

121

VSS

123

DQ32

125

DQ33

127

VSS

129

DQS4#

131

DQS4

133

VSS

135

DQ34

137

DQ35

139

VSS

141

DQ40

143

DQ41

145

VSS

147

DM5

149

VSS

151

DQ42

153

DQ43

155

VSS

157

DQ48

159

DQ49

161

VSS

163

NC,TEST

165

VSS

167

DQS6#

169

DQS6

171

VSS

173

DQ50

175

DQ51

177

VSS

179

DQ56

181

DQ57

183

VSS

185

DM7

187

VSS

189

DQ58

191

DQ59

193

VSS

195

SDA

197

SCL

199

VDDSPD

201

GND

FOX_ASOA426-M2R-TR

DIMMB

DQ12
DQ13

DQ14
DQ15

DQ20
DQ21

DQ22
DQ23

DQ28
DQ29

DQS3#

DQS3
DQ30

DQ31

NC/CKE1

NC/A15
NC/A14

ODT0

NC/A13

DQ36
DQ37

DQ38
DQ39

DQ44
DQ45

DQS5#

DQS5
DQ46

DQ47
DQ52

DQ53

DQ54
DQ55

DQ60
DQ61

DQS7#

DQS7
DQ62

DQ63

STANDARD

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

D

2005/03/11 2006/03/11

E

Compal Secret Data

Deciphered Date

F

VSS
DQ4
DQ5
VSS
DM0
VSS
DQ6
DQ7
VSS

VSS
DM1
VSS
CK0

CK0#

VSS

VSS

VSS

VSS
DM2

VSS

VSS

VSS

VSS

VSS
VDD

VDD

A11

VDD

VDD

BA1

RAS#

S0#
VDD

VDD
VSS

VSS
DM4
VSS

VSS

VSS

VSS

VSS

VSS
CK1

CK1#

VSS
DM6
VSS

VSS

VSS

VSS

VSS
SAO

SA1

GND

G

V_DDR_MCH_REF

2

DDR_B_D4

4

DDR_B_D5

6
8

DDR_B_DM0

10
12

DDR_B_D6

14

DDR_B_D7

16
18

DDR_B_D12

20

DDR_B_D13

22
24

DDR_B_DM1

26
28

M_CLK_DDR3

30

M_CLK_DDR#3

32
34

DDR_B_D14

36

DDR_B_D15

38
40

42

DDR_B_D20

44

DDR_B_D21

46
48
50

NC

A7
A6

A4
A2
A0

NC

52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202

DDR_B_DM2
DDR_B_D22

DDR_B_D23
DDR_B_D28

DDR_B_D29
DDR_B_DQS#3

DDR_B_DQS3
DDR_B_D30

DDR_B_D31
DDR_CKE3_DIMMB

DDR_B_MA11
DDR_B_MA7
DDR_B_MA6

DDR_B_MA4
DDR_B_MA2
DDR_B_MA0

DDR_B_BS#1
DDR_B_RAS#
DDR_SCS#2

M_ODT2
DDR_B_MA13DDR_SCS#3

DDR_B_D36
DDR_B_D37

DDR_B_DM4
DDR_B_D38

DDR_B_D39
DDR_B_D44

DDR_B_D45
DDR_B_DQS#5

DDR_B_DQS5
DDR_B_D46

DDR_B_D47
DDR_B_D52

DDR_B_D53
M_CLK_DDR4

M_CLK_DDR#4
DDR_B_DM6
DDR_B_D54

DDR_B_D55
DDR_B_D60

DDR_B_D61
DDR_B_DQS#7

DDR_B_DQS7
DDR_B_D62

DDR_B_D63

10K_0402_5%~D

12

Title

Size Document Number Rev

Date: Sheet

G

R84

1 2

10K_0402_5%~D

R112

星@, 06, 2006

薑三月

2.2U_0805_10V6K~D

0.1U_0402_16V4Z~D

1

C401

2

DDR_CLK3 8

DDR_CLK3# 8

12

V_DDR_MCH_REF

12

DDR_CKE3_DIMMB 8

DDR_B_BS#1 9
DDR_B_RAS# 9

DDR_SCS#2 8

M_ODT2 8

DDR_CLK4 8

DDR_CLK4# 8

+3VS

Compal Electronics, Inc.

SCHEMATIC, M/B LA-2831

401362

1

C399

2

+1.8V

R329
1K_0402_5%

R340
1K_0402_5%

H

V_DDR_MCH_REF 13

1

C394

0.1U_0402_16V4Z

2

1

C397

0.1U_0402_16V4Z

2

of

14 59

H

D

5

G

G

R607

2
2

L72

L73

L76

R839

1 2

0_0402_5%

+3VS

12

D

13

LCDP_DAT

13

D

4

1

4

1

3

2

3

2

4

1

12

2.2K_0402_5%

LCDP_CLK

WCM-2012-670T

WCM-2012-670T

WCM-2012-670T

2.2K_0402_5%

Q33

BSS138_SOT23

Q34

BSS138_SOT23

3

3

2

2

3

3

2

2

L74

4

4

1

1

WCM-2012-670T

L75

4

4

1

1

WCM-2012-670T

3

3

2

2

S

S

TX_A0+43

TX_A0-43

D D

C C

B B

TX_A1+43

TX_A1-43

TX_A2-43

TX_A2+43

TX_AC-43

TX_AC+43

TX_A3-43

TX_A3+43

INVT_PWM30

LCD_CLK10

LCD EEPROM

LCD_DAT10

+2.5VS

4

1

4

1

3

2

3

2

4

1

LTX_A0+

LTX_A0-

LTX_A1+

LTX_A1-

LTX_A2-

LTX_A2+

LTX_AC-

LTX_AC+

LTX_A3-

LTX_A3+

PWM

R606

C47

+LCDVDD

1 2

+3VS

1

2

0.047U_0402_16V4Z

4

R9

0_0805_5%

1

C39

2

0.047U_0402_16V4Z

1

C21

2

0.1U_0402_16V4Z

1

C916

2

0.047U_0402_16V4Z

1

C22

2

0.1U_0402_16V4Z

B+I

2

C589

1

0.1U_0603_50V4Z

LTX_A0­LTX_A0+

LTX_A1­LTX_A1+

LTX_A2­LTX_A2+

LTX_AC­LTX_AC+

LTX_A3­LTX_A3+

BK_EN10

BKOFF#30

2

C588

1

0.1U_0603_50V4Z

3

JLVDS1

1

21

2

22

3

23

4

24

5

25

6

26

7

27

8

28

9

29

10

30

11

31

12

32

13

33

14

34

15

35

16

36

17

37

18

38

19

39

20

40

ACES_88107-4000G

+3VS

5

U39

1

P

A

2

O

B

G

3

NC7ST08P5X_SC70-5

DISPLAYOFF#
PWR_LED1#

BATT_LED1#
CHARGE_LED1#

DISPLAYOFF#

4

LCD_VDD_EN30

0.1U_0603_50V4Z

PWM

CIR_OUT#

LCDP_CLK
LCDP_DAT

LCD_INVB+

C11

DAC_BRIG 30

CIR_OUT# 29

2N7002_SOT23

1

2

1

C1

2

1000P_0402_50V7K

+LCDVDD

13

D

Q7

S

F2

21

2.5A_32V

2

1

470_0402_5%

R48

2

G

2

2

PWR_LED#30,31

+5VALW

C579

0.1U_0402_10V6K

BATT_LED#30,31

CHARGE_LED#30,31

R49
100K_0402_5%

LCD_VDD_EN#

13

Q6
DTC124EK_SC59

INVPWR_B+

B+_BIAS

2

G

PWR_LED1#

R947
330_0603_5%

1 2

Power LED Color:White

BATT_LED1#

R948
330_0603_5%

1 2

Battery low LED Color:Amber

CHARGE_LED1#

CHARGE LED Color :Amber

R608

1 2

330_0603_5%

R609

1 2

330_0603_5%

1 2

R949
330_0603_5%

1 2

+LCDVDD +3VS

80mil 80mil

R50
100K_0402_5%

13

D

Q5
2N7002_SOT23

S

LCD_VDD_ENL#

C40

0.1U_0402_16V4Z

R611

1 2

1M_0603_1%

R612

1 2

1M_0603_1%

R610

330_0603_5%

R613

1 2

1M_0603_1%

SI2302DS_SOT23

S

G

1

2

B

E

2

B

E

2

B

E

Q3

D

13

2

R34
150K_0402_5%

C

Q37
MMBT3904_SOT23

3 1

C

Q38
MMBT3904_SOT23

3 1

C

Q39
MMBT3904_SOT23

3 1

C37

0.1U_0402_16V4Z

1 2

R975 10K_0402_5%@

8
7

5

C13

INVPWR_B+

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2005/03/11 2006/03/11

3

Compal Secret Data

Deciphered Date

2

+5VALW

12

R978

@

100K_0402_5%

LCD_VDD_EN# LCD_VDD_ENL#

10K_0402_5%

1 2

R979

@

2

1

0.01U_0402_16V7K

C951

@

Compal Electronics, Inc.

Title

Size Document Number Rev

星期一

Date: Sheet

SCHEMATIC, M /B LA-2831

401362

, 06, 2006

三月

1

of

15 59

D

B+I

1
2
3 6

2N7002_SOT23

+5VS

Q2
FDS4435_SO8

4

Q40

D

1 3

2

4

0.1U_0603_50V4Z

S

G

B+

R1

1 2

C43

0.1U_0603_50V4Z

A A

0_0805_5%

5

L9

FBM-L11-322513-151LMAT_1210

1 2

1

C585

C38

10U_1206_25V6M

2

0.1U_0603_50V4Z

B+I

R617
100K_0402_5%

R616

75K_0402_5%

5

4

3

2

1

SMBDAT_VGA

13

D

Q35
2N7002_SOT23

SMBCLK_VGA

13

D

Q36
2N7002_SOT23

C/R_VGA

Y/G_VGA

COMP/B_VGA

12

R23

150_0402_1%

12

R21

150_0402_1%

12

R22

150_0402_1%

D D

C C

DAT_DDC210
CLK_DDC210

DAT_DDC2
CLK_DDC2

C/R_VGA10

Y/G_VGA10

COMP/B_VGA10

+3VS

+3VS

R910

G

2

4.7K_0402_5%

S

+3VS

+3VS

R911

G

2

4.7K_0402_5%

S

DVI Interface

CRT_RED10

B B

HSYNC10

VSYNC10

A A

CRT_GRN10

CRT_BLU10

HSYNC_VGA

VSYNC_VGA

0.1U_0402_16V4Z

R1004

1 2

R1006

1 2

+5VS

C30

0_0402_5%

0_0402_5%

+5VS

1

2

5

5

R20
1K_0402_5%

1 2

1

P

4

OE#

A2Y

G

U1

3

SN74AHCT1G125GW_SOT353-5

1

P

4

OE#

A2Y

G

U2

3

SN74AHCT1G125GW_SOT353-5

1

2

1

2

1

2

1 2

L8
CHB1608U301_0603

C25
82P_0402_50V8J

1 2

L6
CHB1608U301_0603

C23
82P_0402_50V8J

1 2

L7
CHB1608U301_0603

C24
82P_0402_50V8J

DDC_MONID0

MSEN#30

C19

10P_0402_50V8J

1 2

33_0402_5%

1 2

10P_0402_50V8J

1

2

12

R8

75_0402_1%

R1005

R1007

33_0402_5%

C18

R7

12

12

12

MSEN#

1

2

12

R6

75_0402_1%

C16
82P_0402_50V8J

C14
82P_0402_50V8J

C15
82P_0402_50V8J

1

C17
10P_0402_50V8J

2

1 2

L1
FCM2012C-800_0805

1 2

L2
FCM2012C-800_0805

1 2

L3

12

FCM2012C-800_0805

75_0402_1%

SVIDEO_C

SVIDEO_Y
SVIDEO_COMP/B

D14

DAN217_SC59@

2

CRTR

CRTG

CRTB

12

C3

3.3P_0402_50V8J

1 2

L4
CHB1608U301_0603

1 2

L5
CHB1608U301_0603

12

12

R3

2K_0402_5%

1

1

C10

2

2

SUYIN_030001FR007T200FU

8

7 8
6

9
5
4
3
2
1

JTV1

W=40mils

100P_0402_50V8J

TV-OUT Connector

9

F1

1.1A_6VDC_FUSE

1

C12

0.1U_0402_16V4Z

2

SMBDAT_VGA
SMBCLK_VGA

JCRT1

6

11

1
7

12

2
8

13

3
9

14

4

10

17

15

16

5

SUYIN_7849S-15G2T-HC

+CRT_VCCF+CRT_VCC

21

D20
RB751V_SOD323

CRT Connector

21

+5VS

1

C584

0.1U_0402_16V4Z

2

R842

@

1 2

0_0402_5%

1

D18

2

3

DAN217_SC59@

1

3

1

C6

2

27P_0402_50V8J

D17

DAN217_SC59@

D15

DAN217_SC59@

1

2

3

12

C4

3.3P_0402_50V8J

1

C7

2

27P_0402_50V8J

2

1

3

D19

D16

DAN217_SC59@

1

2

3

12

C5

3.3P_0402_50V8J

1

2

3

+3VS

DAN217_SC59@

+CRT_VCC

R2

2K_0402_5%

+3VS

1

C2

100P_0402_50V8J

1

C8

2

C9

2

100P_0402_50V8J

100P_0402_50V8J

DA204U

K1 A2

A1 K2

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/03/11 2006/03/11

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

星@, 06, 2006

薑三月

2

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, M/B LA-2831

401362

1

16 59

D

of

5

+3VS

ICH_SMBDATA20,24

D D

ICH_SMBCLK20,24

ICH_SMBDATA

+3VS

ICH_SMBCLK

D

1 3

1 3

D

D
1

3

G

S

2

2N7002

12

12

R756

10K_0402_5%

S

Q45
2N7002_SOT23

G

2

2

G

Q46
2N7002_SOT23

S

CK_VDD_A CK_VDD_REF

C811

R759

10K_0402_5%

1

2

4.7U_0805_6.3V6K

CK_SDATA

CK_SCLK

0 0 1 for Dothan-A 533Mhz
1 0 1 for Dothan-A 400Mhz

FSC FSB FSA CPU

CLKSEL0 CLKSEL1 CLKSEL2

C C

*

0
0
0
1
1
1

00
0

1
0

1
11
0

0

0

1
0

1

0

11
Table : ICS 954201 / Cypress CY28411

+VCCP

R346
10K_0402_5%

R347

@

1K_0402_5%

1 2

1 2

R344
10K_0402_5%
@

1 2

R758

1 2

R295
10K_0402_5%
@

1 2

B B

R912

CLKSEL0

1 2

8.2K_0402_5%

CPU_BSEL06

+VCCP

A A

CPU_BSEL16

CLKSEL1

5

MHz

266
133
200
166
333
100
400

RESERVED

10K_0402_5%@

1 2

R288
1K_0402_5%

SRC
MHz

100 33.30
100
100
100
100
100
100

PCI
MHz

33.3

33.3

33.3

33.3

33.3

33.3

MCH_CLKSEL1 8

CLK_48M_CBUF47
CLK_48M_ICH20

CLK_14M_CODEC27

CLK_33M_CBS24,26
CLK_33M_LPCSIO47
CLK_33M_MPCI26
CLK_33M_LAN23
CLK_33M_ICH18,31
CLK_33M_LPCEC30

MCH_CLKSEL0 8

1

2

C812

0.047U_0402_16V7K

33P_0402_50V8J

33P_0402_50V8J

+3VS

4

CK_VDD_48

C828

C377

C382

R343
10K_0402_5%

1 2

CLKSEL2

R345
10K_0402_5%
@

1 2

4

CK_SDATA 13,14

CK_SCLK 13,14

1

1

2

4.7U_0805_6.3V6K

12

12

2

C827

0.047U_0402_16V7K

Place crystal within
500 mils of CK410

12

X4 14.318MHZ_20P_1BX14318CC1A

CLK_48M_CBUF

CLKSEL1
CLK_14M_CODEC
CLKSEL0

CLK_33M_CBS
CLK_33M_LPCSIO
CLK_33M_MPCI
CLK_33M_LAN
CLK_33M_ICH
CLK_33M_LPCEC

+3VS

+3VS

1

C830

2

0.1U_0402_16V4Z

L64

1 2

CHB1608U301_0603

+CK_VDD_MAIN2

L29

1 2

CHB1608U301_0603

1

2

C819

0.047U_0402_16V7K

CK_XTAL_IN

CK_XTAL_OUT

12

R962 12.1_0402_1%

12

R320 12.1_0402_1%

12

R29633_0402_1%

@

12

R317 12.1_0402_1%

12

R330 12.1_0402_1%

12

R316 33_0402_5%

12

R315 33_0402_5%

12

R308 33_0402_5%

12

R319 33_0402_5%

12

R331 33_0402_5%

1 2

R318 10K_0402_5%

PCICLKF0

CK_SCLK

CK_SDATA

1 2

R294 475_0603_1%

Security Classification

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

+CK_VDD_MAIN

1 2

R771
1_0603_5%

1 2

R774

2.2_0603_5%

CLKSEL2CLK_48M_ICH

PCICLK5
PCICLK4
PCICLK3
PCICLK2
PCICLKF1

Issued Date

3

CK_VDD_REF

CK_VDD_48

CLKIREF

3

2

C829
10U_0805_10V4Z

1

2

C387
10U_0805_10V4Z

1

U24

21

VDD_SRC0

28

VDD_SRC1

34

VDD_SRC2

1

VDD_PCI0

7

VDD_PCI1

42

VDD_CPU

48

VDD_REF

11

VDD_48

50

XTAL_IN

49

XTAL_OUT

12

FSA/USB_48

16

FSB/TEST_MODE

53

FSC/TEST_SEL

5

PCI5

4

PCI4

3

PCI3

56

PCI2

9

PCIF1

8

PCIF0/ITP_EN

46

SCLOCK

47

SDATA

39

IREF

13

VSS_48

29

VSS_SRC

2

VSS_PCI0

45

VSS_CPU

51

VSS_REF

6

VSS_PCI1

ICS954206AG

1

C825

0.047U_0402_16V7K
2

1

C388

0.047U_0402_16V7K
2

2005/03/11 2006/03/11

1

C820

0.047U_0402_16V7K
2

1

C389

0.047U_0402_16V7K
2

R770

2.2_0603_5%

VDD_A

VSS_A

PCI_STOP#

CPU_STOP#

CPU1

CPU1#

CPU0

CPU0#

SRC6

SRC6#

SRC5

SRC5#

SRC4

SRC4#

SRC3

SRC3#

SRC2

SRC2#

SRC1

SRC1#

SRC0

SRC0#

DOT96

DOT96#

VTT_PWRGD#/PD

REF

CK_VDD_A

1 2

CPU_2_ITP/SRC_7
CPU_2_ITP/SRC7#

Compal Secret Data

Deciphered Date

37
38

55
54

41
40

44
43

36
35

33
32

31
30

26
27

24
25

22
23

19
20

17
18

14
15

10
52

2

1

C821

0.047U_0402_16V7K
2

1

C826

0.047U_0402_16V7K

2

Place near each pin
W>40 mil

Place near CK410M

H_STP_PCI#
H_STP_CPU#

CK_CPU1

1 2

R301 33_0402_5%

CK_CPU1#

1 2

R302 33_0402_5%

CK_CPU0
CK_CPU0#

CK_CPU2
CK_CPU2#

SCR5
SRC5#

SRC4
SRC4#

SRC2
SRC2# CLK_PCIE_SATA#

SRC1
SRC1# CLK_PCIE_ICH#

SRC0
SRC0# SSC_DREFCLK#

CLK_DOT96
CLK_DOT96#

CLKREF

1 2

R299 33_0402_5%

1 2

R300 33_0402_5%

1 2

R303 33_0402_5%

1 2

R304 33_0402_5%

1 2

R305 33_0402_5%

1 2

R306 33_0402_5%

1 2

R327 33_0402_5%

1 2

R328 33_0402_5%

1 2

R388 33_0402_5%

1 2

R398 33_0402_5%

1 2

R325 33_0402_5%

1 2

R326 33_0402_5%

1 2

R323 33_0402_5%

1 2

R324 33_0402_5%

1 2

R321 33_0402_5%

1 2

R322 33_0402_5%

1 2

R915 49.9_0402_1%

1 2

R916 49.9_0402_1%

CLK_14M_ICH

1 2

R297 12.1_0402_1%

CLK_14M_SIO

1 2

R298 12.1_0402_1%

2

H_STP_PCI# 20
H_STP_CPU# 20,56

CLK_MCH_BCLK
CLK_MCH_BCLK#

CLK_CPU_BCLK
CLK_CPU_BCLK#

CLK_ITP
CLK_ITP#

CLK_MCH_3GPLL
CLK_MCH_3GPLL#

CLK_PCIE_CARD
CLK_PCIE_CARD#

CLK_PCIE_SATA

CLK_PCIE_ICH

SSC_DREFCLK

DREFCLK
DREFCLK#

CLK_14M_ICH 20

CLK_14M_SIO 31

Size Document Number Rev

Date: Sheet

BSS138_SOT23

Title

CLK_MCH_BCLK
CLK_MCH_BCLK#
CLK_CPU_BCLK
CLK_CPU_BCLK#
CLK_ITP
CLK_ITP#
CLK_PCIE_CARD
CLK_PCIE_CARD#
CLK_PCIE_ICH
CLK_PCIE_ICH#
CLK_MCH_3GPLL
CLK_MCH_3GPLL#
CLK_PCIE_SATA
CLK_PCIE_SATA#

SSC_DREFCLK
SSC_DREFCLK#
DREFCLK
DREFCLK#

CLK_PCIE_CARD 24
CLK_PCIE_CARD# 24

CLK_PCIE_SATA 19
CLK_PCIE_SATA# 19

CLK_PCIE_ICH 20
CLK_PCIE_ICH# 20

SSC_DREFCLK 8
SSC_DREFCLK# 8

DREFCLK 8
DREFCLK# 8

+3VS

12

R342

10K_0402_5%

13

D

Q12

S

Compal Electronics, Inc.

星@, 06, 2006

薑三月

1

12

R282 49.9_0402_1%

12

R283 49.9_0402_1%

12

R280 49.9_0402_1%

12

R281 49.9_0402_1%

12

R284 49.9_0402_1%

12

R285 49.9_0402_1%

1 2

R338 49.9_0402_1%

1 2

R339 49.9_0402_1%

1 2

R336 49.9_0402_1%

1 2

R337 49.9_0402_1%

1 2

R286 49.9_0402_1%

1 2

R287 49.9_0402_1%

1 2

R558 49.9_0402_1%

1 2

R555 49.9_0402_1%

1 2

R334 49.9_0402_1%

1 2

R335 49.9_0402_1%

1 2

R332 49.9_0402_1%

1 2

R333 49.9_0402_1%

CLK_MCH_BCLK 8
CLK_MCH_BCLK# 8

CLK_CPU_BCLK 5
CLK_CPU_BCLK# 5

CLK_ITP 5
CLK_ITP# 5

CLK_MCH_3GPLL 10
CLK_MCH_3GPLL# 10

R348 10K_0402_5%

1 2

2

G

1

C405

2

0.047U_0402_16V4Z

SCHEMATIC, M/B LA-2831

401362

1

17 59

VGATE 8,20,30,56

D

of

5

RP38

+3VS

D D

+3VS

+3VS

+3VS

C C

+3VS

+3VALW

B B

A A

1 8
2 7
3 6
4 5

8.2K_0804_8P4R_5%

RP39

1 8
2 7
3 6
4 5

8.2K_0804_8P4R_5%
RP37

1 8
2 7
3 6
4 5

8.2K_0804_8P4R_5%

PCI_SERR#
PCI_FRAME#
PCI_TRDY#
PCI_STOP#

PCI_IRDY#
PCI_PLOCK#
PCI_DEVSEL#
PCI_PERR#

PCI_PIRQD#
PCI_PIRQB#
PCI_PIRQH#
PCI_PIRQC#

R8518.2K_0402_5%

1 2

R8528.2K_0402_5%

1 2

R8538.2K_0402_5%

1 2

R5328.2K_0402_5%

1 2

R8148.2K_0402_5%

1 2

R5538.2K_0402_5%

1 2

R5528.2K_0402_5%

1 2

R8198.2K_0402_5%

1 2

R8108.2K_0402_5%

1 2

R8598.2K_0402_5%

1 2

R5618.2K_0402_5%

1 2
1 2

R467 10K_0402_1%

ICH_PME#

RTC Battery

JRTC1

2

-

MAXELL_1220G

PCI_PIRQE#
PCI_PIRQF#

PCI_PIRQA#

PCI_REQ0#
PCI_REQ1#
PCI_REQ3#
PCI_REQ4#

PCI_REQ2#
PCI_REQ5#
PCI_REQ6#

PCI_AD[0..31]23,24,26,35

CHGRTC

2

1

+

+RTCVCC

3

1

PCI_FRAME#23,24,26,35

PCI_PIRQA#24
PCI_PIRQB#26
PCI_PIRQC#35

BAS40-04_SOT23
D6

4

PCI_AD0
PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD6
PCI_AD7
PCI_AD8
PCI_AD9
PCI_AD10
PCI_AD11
PCI_AD12
PCI_AD13
PCI_AD14
PCI_AD15
PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20
PCI_AD21
PCI_AD22
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27PCI_PIRQG#
PCI_AD28
PCI_AD29
PCI_AD30
PCI_AD31

PCI_FRAME#

PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#

PLTRST#

PCI_PCIRST#

U33B

E2

AD[0]

E5

AD[1]

C2

AD[2]

F5

AD[3]

F3

AD[4]

E9

AD[5]

F2

AD[6]

D6

AD[7]

E6

AD[8]

D3

AD[9]

A2

AD[10]

D2

AD[11]

D5

AD[12]

H3

AD[13]

B4

AD[14]

J5

AD[15]

K2

AD[16]

K5

AD[17]

D4

AD[18]

L6

AD[19]

G3

AD[20]

H4

AD[21]

H2

AD[22]

H5

AD[23]

B3

AD[24]

M6

AD[25]

B2

AD[26]

K6

AD[27]

K3

AD[28]

A5

AD[29]

L1

AD[30]

K4

AD[31]

J3

FRAME#

Interrupt I/F

N2

PIRQ[A]#

L2

PIRQ[B]#

M1

PIRQ[C]#

L3

PIRQ[D]#

AC5

SATA[1]RXN/RSVD[1]

AD5

SATA[1]RXP/RSVD[2]

AF4

SATA[1]TXN/RSVD[3]

AG4

SATA[1]TXP/RSVD[4]

AC9

SATA[3]RXN/RSVD[5]

AD9

SATA[3]RXP/RSVD[6]

AF8

SATA[3]TXN/RSVD[7]

AG8

SATA[3]TXP/RSVD[8]

U3

TP[3]/RSVD[9]

ICH6_BGA609

+3V

PCI

REQ[4]#/GPI[40]

GNT[4]#/GPO[48]

REQ[5]#/GPI[1]

GNT[5]#/GPO[17]

REQ[6]#/GPI[0]

GNT[6]#/GPO[16]

PIRQ[E]#/GPI[2]
PIRQ[F]#/GPI[3]

PIRQ[G]#GPI[4]

PIRQ[H]#/GPI[5]

RESERVED

14

4

P

A

5

B

G

7

+3V

14

10

P

A

9

B

G

7

R804

@
33_0402_5%

1 2

+3V

13

A

12

B

L5

REQ[0]#

C1

GNT[0]#

B5

REQ[1]#

B6

GNT[1]#

M5

REQ[2]#

F1

GNT[2]#

B8

REQ[3]#

C8

GNT[3]#

F7
E7
E8
F6
B7
D8

J6

C/BE[0]#

H6

C/BE[1]#

G4

C/BE[2]#

G2

C/BE[3]#

A3

IRDY#

E1

PAR

R2

PCIRST#

C3

DEVSEL#

E3

PERR#

C5

PLOCK#

G5

SERR#

J1

STOP#

J2

TRDY#

R5

PLTRST#

G6

PCICLK

P6

PME#

D9
C7
C6
M3

U53B

6

O

74VHC08MTC_TSSOP14

R812

@

1 2

33_0402_5%

R807

@

1 2

33_0402_5%

U53C

8

O

74VHC08MTC_TSSOP14

14

U53D

P

11

O

G

74VHC08MTC_TSSOP14

7

3

PCI_REQ0#
PCI_GNT0#
PCI_REQ1#
PCI_GNT1#
PCI_REQ2#
PCI_GNT2#
PCI_REQ3#
PCI_GNT3#
PCI_REQ4#
PCI_GNT4#
PCI_REQ5#

PCI_REQ6#

PCI_C_BE0#
PCI_C_BE1#
PCI_C_BE2#
PCI_C_BE3#

PCI_IRDY#
PCI_PAR
PCI_PCIRST#
PCI_DEVSEL#
PCI_PERR#
PCI_PLOCK#
PCI_SERR#
PCI_STOP#
PCI_TRDY#

PLTRST#
CLK_33M_ICH

PCI_PIRQE#
PCI_PIRQF#
PCI_PIRQG#
PCI_PIRQH#

C881

0.1U_0402_16V4Z
12

PCI_REQ0# 23

PCI_GNT0# 23

PCI_REQ1# 24

PCI_GNT1# 24

PCI_REQ2# 26

PCI_GNT2# 26

PCI_REQ3# 26

PCI_GNT3# 26

PCI_REQ4# 35

PCI_GNT4# 35

PCI_C_BE0# 23,24,26,35
PCI_C_BE1# 23,24,26,35
PCI_C_BE2# 23,24,26,35
PCI_C_BE3# 23,24,26,35

PCI_ I RDY# 23,24,26,35
PCI_PAR 23,24,26,35

PCI_DEVSEL# 23,24,26,35
PCI_PERR# 23,24,26

PCI_SERR# 23,24,26
PCI_STOP# 23,24,26,35
PCI_TRDY# 23,24,26,35

PLTRST# 20
CLK_33M_ICH 17,31

PCI_PIRQE# 24
PCI_PIRQF# 23
PCI_PIRQG# 24,26
PCI_PIRQH# 26

PLTRST_MCH# 8

PLTRST_SIO# 25

PCIRST# 20,23,24,26,30,31,35,47

R535

1 2

0_0402_5%

Q18

2N7002_SOT23

D

S

13

G

2

R530

12

10K_0402_5%

@

@

ICH_PME#

+3V

2

ICH_PME# 23,24,26,30

CLK_33M_ICH

R817
10_0402_5%
@

1 2

CLK_ICH_TERM

1

C887

8.2P_0402_50V8J~D@

2

1

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/03/11 2006/03/11

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

2

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, M/B LA-2831

401362

星@, 06, 2006

薑三月

1

18 59

D

of