COMPAL LA-2821P Schematics

A

11

22

B

C

D

E

Compal confidential

Schematics Document

Mobile Yonah uFCPGA with Intel
Calistoga_PM+ICH7-M core logic

33

44

A

B

2005-11-24

REV:0.5

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2005/03/102006/03/10

Compal Secret Data

Deciphered Date

D

Title

SizeDocument NumberRev

Custom

Date:Sheet of

Compal Electronics, Inc.

Cover Sheet

LA-2821P

E

152Friday, November 25, 2005

0.5

A

Compal confidential

File Name : LA-2821P

B

C

D

E

AngelFire 3.0

11

Accelerometer
LIS3LV02DQ

page 27

Fan Control

page 4

Mobile Yonah

uFCPGA-478 CPU

Thermal Sensor
ADM1032AR

page 4page 4,5,6

Clock Generator

ICS954306

page 15

Accelerometer
LIS3LV02DQ

page 27

FSB

H_A#(3..31)

MXM III connector

page 18

PCI-E x 16

Intel Calistoga MCH

CRT / TV-OUT

page 16

22

LCD CONN

page 17

PCI-E BUS

PCI BUS

10/100/1000 LAN

LED

33

page 32

RTC CKT.

page 20

BCM5753M

page 25,26

RJ45/11 CONN

page 26

Mini-Card

page 27

1394 port

CardBus Controller

TI PCI7612

Slot 0/Smart Card

page 23

page 23,24

6in1 Slot

page 24

Power OK CKT.

page 37

Power On/Off CKT.

page 34

44

DC/DC Interface CKT.

page 36

Security Module

Touch Pad CONN.

TrackPoint CONN.

SMSC KBC 1021

page 34

Power Circuit DC/DC

Page 38,39,40,41,42,43,44,45,46,47

A

B

533/667MHz

H_D#(0..63)

DDR2 -400/533/667

DDR2-SO-DIMM X2

BANK 0, 1, 2, 3

Dual Channel

945PM

PCBGA 1466

page 7,8,9,10,11,12

USB conn x2
(Docking)

USB2.0 HUB /
FP Conn

USB2.0

DMI

USB conn x2

BT Conn

page 30

USB conn x2
(Sub Board)

Audio CKTAMP & Audio Jack

AD1981HD

SATA HDD Connector

PATA ODD Connector

Intel ICH7-M

mBGA-652

page 19,20,21,22

SPI ROM

page 23

SST25LF080A

AC-LINK/Azalia

SPI

page 23

SATA Master

PATA Slave

LPC BUS

SMSC Super I/O

page 33

LPC47N217

Int.KBD

page 34page 34

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

COM1 LPT
( Docking )( Docking )

page 35page 35

2005/03/102006/03/10

Compal Secret Data

page 31page 32

Deciphered Date

Flash ROM

SST49LF008A

D

page 13,14

page 35

FingerPrinter AES2501

page 30

page 30

page 29

page 28page 29

page 20

page 20

page 32

Title

SizeDocument NumberRev

Date:Sheet of

USBx1

New Card USBx1

MAX9710ETP

Docking CONN.

*RJ-45(LED*2)
*RJ-11(Pass Through)
*CRT
*COMPOSITE Video Out
*TVOUT
*DVI
*LINE IN
*LINE OUT
*PCI-E x2
*Serial Port
*Parallel Port
*PS/2 x2
*USB x2
*DC JACK

MDC1.5

page 34

page 24

Compal Electronics, Inc.

Block Diagram

LA-2821P

E

page 30

page 34

0.5

252Friday, November 25, 2005

5

4

3

2

1

Voltage Rails

Power Plane

VIN

DD

CC

B+
+CPU_CORE
+VCCP
+0.9VS

+1.5VS
+1.8V

+2.5VS

+3VALW

+5VALW
+5VS
+RTC_VCC

Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.

Description

Adapter power supply (18.5V)
AC or battery power rail for power circuit
Core voltage for CPU

1.05V power rail for Processor I/O and MCH/ICH core power

0.9V switched power rail for DDRII Vtt

1.5V switched power rail for PCI-E interface

1.8V power rail for DDRII

3.3V always on power rail+2.5VALWONONON*

3.3V always on power rail

3.3V switched power rail+3VS
5V always on power rail
5V switched power rail
RTC powerONON

S3

S0-S1

N/A

N/A

N/A
ONOFF
ON

OFF
ON

OFF

ON

OFF
ON

ON
ON+1.8VSOFFOFF1.8V switched power rail
ONOFF

ON

ON
ONOFFOFF
ON

ON
ON

OFF

ON

S5

N/A
N/AN/A
OFF
OFF
OFF

OFF
OFF

OFF2.5V switched power rail for MCH video PLL

ON*

ON*
OFF

Internal PCI Devices

DEVICE

LAN
AzaliaD27

USB1.1/2.0
PCI to PCI (DMI to PCI)
AC97 MODEM
AC97 Audio
PATA/SATA
LPC I/F
SMBUS
CPU I/F

BB

Bus

1
0
0
0
0
0
0
0
0
0
0
0
0

PCI Device ID

D8

D28PCI-E
D29
D30
D30
D30
D31
D31
D31

D31AD15DMA
D31AD15PMU

IDSEL #

AD24
AD11
AD12
AD13
AD14
AD14
AD14
AD15
AD15
AD15
AD15D31

External PCI Devices

DEVICE

Mini-PCI
CARD BUS

PCI Device ID

D4
D6

IDSEL #

AD20
AD22

REQ/GNT #

0
2

PIRQ

F
C D E G

Symbol Note :

: means Digital Ground

: means Analog Ground

Note: Layout Related Memo

L

: Layout Note related Area Mark.

: Question Area Mark.(Wait check)

: Modified Area Mark.

9/15

: C-BOM impact

: Modified Area Mark(Compare with EAL60).

@ : means just reserve , no build
SPI@ : means just build when SPI I/F BIOS function reserve.

*

FWH@ : means just build when FWH I/F BIOS function reserve.

*

NOXDP@ : means just build when XDP function disable.

*

XDP@ : means just build when XDP function enable. When this time, docking PCI express will not work.
TPM1.2@ : means just build when TPM1.2 function enable.

*

TPM@ : means just build when TPM function enable.

*

SC@ : means just build when SmartCard function enable.

*

SATA@ : means just build when SATA I/F HDD enable.

*

NOSATA@ : means just build when SATA I/F HDD disable.
NC@ : means just build when New Card function enable.

*

NONC@ : means just build when New Card function disable.
MDC1.5@ : means just build when MDC1.5 function enable.

*

7612@ : means just build when TI PCI7612 chip selected.

*

7611@ : means just build when TI PCI7611MLS chip selected.
250@ : means just build when SMsC LPC47N250 chip selected.
1021@ : means just build when SMsC KBC1021 chip selected.

*

1981HD@ : means just build when AD1981HD chip selected.

*

45@ : means need be mounted when 45 level assy or rework stage.
ACCEL@ : means just build when Accelerometer chip LIS3LV02DQ selected.

*

NODP@ : means just build when No DP design Clock Gen. selected.

*

DP@ : means just build when DP design Clock Gen. selected.
LPNO@ : means just build when No LP design ICS Clock Gen. selected.
LP@ : means just build when LP design ICS Clock Gen. selected.

*

DB@ : means just build when Mini-PCI E Debug Card function enable.

*

* : means define for SMT build when this stage

I2C / SMBUS ADDRESSING

DEVICE

AA

DDR SO-DIMM 0
DDR SO-DIMM 1
CLOCK GENERATOR (EXT.)
USB HUB5C0 1 0 1 1 1 0 0

5

HEX

A0
A4
D2

ADDRESS

1 0 1 0 0 0 0 0
1 0 1 0 0 1 0 0
1 1 0 1 0 0 1 0

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/03/102006/03/10

Compal Secret Data

Deciphered Date

Title

SizeDocument NumberRev

2

Date:Sheet of

Compal Electronics, Inc.

Notes List

LA-2821P

352Friday, November 25, 2005

1

0.5

5

4

3

2

1

H_A#[3..31]7

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8

CLK_CPU_BCLK
CLK_CPU_BCLK#

OCP#21,47

H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

H_ADSTB#0
H_ADSTB#1

H_ADS#
H_BNR#
H_BPRI#
H_BR0#
H_DEFER#
H_DRDY#
H_HIT#
H_HITM#
H_IERR#
H_LOCK#
H_RESET#

H_RS#0
H_RS#1
H_RS#2
H_TRDY#

XDP_BPM#0
XDP_BPM#1
XDP_BPM#2
XDP_BPM#3

XDP_DBRESET#

H_DBSY#
H_DPSLP#
H_DPRSTP#
H_DPWR#
XDP_BPM#4
XDP_BPM#5
H_PROCHOT#

H_PWRGOOD
H_CPUSLP#
XDP_TCK
XDP_TDI
XDP_TDO
TEST1
TEST2
XDP_TMS
XDP_TRST#

H_THERMDA
H_THERMDC
H_THERMTRIP#

DD

H_REQ#[0..4]7

H_ADSTB#07

CC

R448

56_0402_5%

1 2

+VCCP

BB

H_PROCHOT#45

1 2

+VCCP

56_0402_5%

H_THERMDA, H_THERMDC routing together.
Trace width / Spacing = 10 / 10 mil

AA

H_PROCHOT# OCP#

H_ADSTB#17

CLK_CPU_BCLK15

CLK_CPU_BCLK#15

H_ADS#7
H_BNR#7

H_BPRI#7

H_BR0#7

H_DEFER#7

H_DRDY#7

H_HIT#7

H_HITM#7

H_LOCK#7

H_RESET#7

H_RS#[0..2]7

H_TRDY#7

XDP_DBRESET#21

H_DBSY#7

H_DPSLP#20

H_DPRSTP#20,45

H_DPWR#7

R447

H_PWRGOOD20

H_CPUSLP#7

R271K_0402_5%@

1 2

R2851_0402_5%

1 2

H_THERMTRIP#7,20

+VCCP

12

R30

56_0402_5%@

B

2

E

3 1

C

Q6

MMBT3904_SOT23@

5

JP8A

J4

A3#

L4

A4#

M3

A5#

K5

A6#

M1

A7#

N2

A8#

J1

A9#

N3

A10#

P5

A11#

P2

A12#

L1

A13#

P4

A14#

P1

A15#

R1

A16#

Y2

A17#

U5

A18#

R3

A19#

W6

A20#

U4

A21#

Y5

A22#

U2

A23#

R4

A24#

T5

ADDR GROUP

A25#

T3

A26#

W3

A27#

W5

A28#

Y4

A29#

W2

A30#

Y1

A31#

K3

REQ0#

H2

REQ1#

K2

REQ2#

J3

REQ3#

L5

REQ4#

L2

ADSTB0#

V4

ADSTB1#

A22

BCLK0

A21

F21

D20

AD4
AD3
AD1
AC4

C20

D24
AC2
AC1
D21

AC5
AA6
AB3
C26
D25
AB5
AB6

A24
A25

HOST CLK

BCLK1

H1

ADS#

E2

BNR#

G5

BPRI#

F1

BR0#

H5

DEFER#
DRDY#

G6

HIT#

E4

CONTROL

HITM#
IERR#

H4

LOCK#

B1

RESET#

F3

RS0#

F4

RS1#

G3

RS2#

G2

TRDY#

BPM0#
BPM1#
BPM2#
BPM3#

DBR#

E1

DBSY#

B5

DPSLP#

E5

DPRSTP#
DPWR#
PRDY#
PREQ#
PROCHOT#

D6

PWRGOOD

D7

SLP#
TCK
TDI
TDO
TEST1
TEST2
TMS
TRST#

THERMAL
DIODE

THERMDA
THERMDC

C7

THERMTRIP#

FOX_PZ47903-2741-42_YONAH

H_DPSLP#

H_DPRSTP#

YONAH

MISC

R439

1 2

56_0402_5%@

R440

1 2

56_0402_5%@

DATA GROUP

LEGACY CPU

4

D10#
D11#
D12#
D13#
D14#
D15#
D16#
D17#
D18#
D19#
D20#
D21#
D22#
D23#
D24#
D25#
D26#
D27#
D28#
D29#
D30#
D31#
D32#
D33#
D34#
D35#
D36#
D37#
D38#
D39#
D40#
D41#
D42#
D43#
D44#
D45#
D46#
D47#
D48#
D49#
D50#
D51#
D52#
D53#
D54#
D55#
D56#
D57#
D58#
D59#
D60#
D61#
D62#
D63#

DINV0#
DINV1#
DINV2#
DINV3#

DSTBN0#
DSTBN1#
DSTBN2#
DSTBN3#
DSTBP0#
DSTBP1#
DSTBP2#
DSTBP3#

A20M#
FERR#

IGNNE#

INIT#
LINT0
LINT1

STPCLK#

SMI#

H_D#0

E22

D0#

H_D#1

F24

D1#

H_D#2

E26

D2#

H_D#3

H22

D3#

H_D#4

F23

D4#

H_D#5

G25

D5#

H_D#6

E25

D6#

H_D#7

E23

D7#

H_D#8

K24

D8#

H_D#9

G24

D9#

H_D#10

J24

H_D#11

J23

H_D#12

H26

H_D#13

F26

H_D#14

K22

H_D#15

H25

H_D#16

N22

H_D#17

K25

H_D#18

P26

H_D#19

R23

H_D#20

L25

H_D#21

L22

H_D#22

L23

H_D#23

M23

H_D#24

P25

H_D#25

P22

H_D#26

P23

H_D#27

T24

H_D#28

R24

H_D#29

L26

H_D#30

T25

H_D#31

N24

H_D#32

AA23

H_D#33

AB24

H_D#34

V24

H_D#35

V26

H_D#36

W25

H_D#37

U23

H_D#38

U25

H_D#39

U22

H_D#40

AB25

H_D#41

W22

H_D#42

Y23

H_D#43

AA26

H_D#44

Y26

H_D#45

Y22

H_D#46

AC26

H_D#47

AA24

H_D#48

AC22

H_D#49

AC23

H_D#50

AB22

H_D#51

AA21

H_D#52

AB21

H_D#53

AC25

H_D#54

AD20

H_D#55

AE22

H_D#56

AF23

H_D#57

AD24

H_D#58

AE21

H_D#59

AD21

H_D#60

AE25

H_D#61

AF25

H_D#62

AF22

H_D#63

AF26

H_DINV#0

J26

H_DINV#1

M26

H_DINV#2

V23

H_DINV#3

AC20

H_DSTBN#0

H23

H_DSTBN#1

M24

H_DSTBN#2

W24

H_DSTBN#3

AD23

H_DSTBP#0

G22

H_DSTBP#1

N25

H_DSTBP#2

Y25

H_DSTBP#3

AE24

H_A20M#

A6

H_FERR#

A5

H_IGNNE#

C4

H_INIT#

B3

H_INTR

C6

H_NMI

B4

H_STPCLK#

D5

H_SMI#

A3

H_D#[0..63]7

ITP-XDP Connector

JP31

1

XDP_BPM#5
XDP_BPM#4

XDP_BPM#3
XDP_BPM#2

XDP_BPM#1
XDP_BPM#0

R442

H_PWRGOOD_RH_PWRGOOD CLK_CPU_XDP

12

1K_0402_5%

+VCCP +VCCP

12

C5390.1U_0402_16V4Z

ICH_SMBDATA
ICH_SMBCLK

XDP_TCK

GND0

3

OBSFN_A0

5

OBSFN_A1

7

GND2

9

OBSDATA_A0

11

OBSDATA_A1

13

GND4

15

OBSDATA_A2

17

OBSDATA_A3

19

GND6

21

OBSFN_B0

23

OBSFN_B1

25

GND8

27

OBSDATA_B0

29

OBSDATA_B1

31

GND10

33

OBSDATA_B2

35

OBSDATA_B3

37

GND12

39

PWRGOOD/HOOK0

41

HOOK1

43

VCC_OBS_AB

45

HOOK2

47

HOOK3

49

GND14

51

SDA

53

SCL

55

TCK1

57

TCK0

59

GND16

OBSDATA_C0
OBSDATA_C1

OBSDATA_C2
OBSDATA_C3

OBSDATA_D0
OBSDATA_D1

OBSDATA_D2
OBSDATA_D3

ITPCLK/HOOK4

ITPCLK#/HOOK5

VCC_OBS_CD

RESET#/HOOK6

DBR#/HOOK7

SAMTE_BSH-030-01-L-D-A

GND1
OBSFN_C0
OBSFN_C1

GND3

GND5

GND7
OBSFN_D0
OBSFN_D1

GND9

GND11

GND13

GND15

TRST#

TMS

GND17

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

TD0

54
56

TDI

58
60

Thermal Sensor ADM1032AR-2

+3VS

2

C69

0.1U_0402_16V4Z

C68

1 2

2200P_0402_50V7K

H_DINV#07
H_DINV#17
H_DINV#27
H_DINV#37

H_DSTBN#[0..3]7

H_DSTBP#[0..3]7

+3VS

R25

1 2

10K_0402_5%

PWM Fan Control circuit

H_A20M#20
H_FERR#20
H_IGNNE#20
H_INIT#20
H_INTR20
H_NMI20

H_STPCLK#20
H_SMI#20

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/03/102006/03/10

FAN_PWM33

Compal Secret Data

Deciphered Date

THERM#

1
2

H_THERMDA
H_THERMDC

+3VS

5

U31

P

INB

O

INA

G

TC7SH00FUF_SSOP5

3

2

1

THERM#

CH751H-40_SC76

4

U5

1

VDD

2

D+

3

D­THERM#4GND

ADM1032AR-2_MSOP8

Address:1001_101

ICH_SMBCLK13,14,15,18,21,25,27

ICH_SMBDATA13,14,15,18,21,25,27

+5VS

D1

2 1

6

2

1

D

G

3

S

4 5

SDATA

ALERT#

Q69
AO6402_TSOP6

XDP_DBRESET#_R

XDP_TDI
XDP_TMS
XDP_TDO
XDP_BPM#5
XDP_TRST#
XDP_TCK

CLK_CPU_XDP#

XDP_TDO
XDP_TRST#
XDP_TDI
XDP_TMS
XDP_PRE

SCLK

Title

SizeDocument NumberRev

Date:Sheet of

1 2

R1910_0402_5%

1 2

ICH_SMBCLK

8

ICH_SMBDATA

7

THERM_SCI#

6
5

ICH_SMBCLK
ICH_SMBDATA

1

C65

4.7U_0805_10V4Z

2

Yonah CPU in mFCPGA479

R443

1 2

This shall place near CPU

R52456_0402_5%

1 2

R52356_0402_1%

1 2

R52556_0402_5%

1 2

R52656_0402_5%

1 2

R52156_0402_5%

1 2

R52256_0402_5%

1 2

1K_0402_1%

H_RESET#H_RESET#_R

R441
R444

XDP_DBRESET#XDP_DBRESET#_R

12

200_0402_1%

12

R24
10K_0402_5%

1

C63

0.1U_0402_16V4Z

2

FAN

12

ZD1

@

RLZ5.1B_LL34

Compal Electronics, Inc.

LA-2821P

5/10

1K_0402_5%@

CLK_CPU_XDP15
CLK_CPU_XDP#15

THERM_SCI#21

1

+3VS

+VCCP

JP6

1
2

ACES_85205-0200

452Friday, November 25, 2005

0.5

5

4

3

2

1

V_CPU_GTLREF

+VCCP

12

R37
1K_0402_1%

12

R39
2K_0402_1%

+VCC_CORE

R42
100_0402_1%

1 2

R41
100_0402_1%

1 2

Close to CPU pin
within 500mils.

VCCSENSE

VSSSENSE

CPU_BSELCPU_BSEL2CPU_BSEL1

133

166

00

0

12

12

R35

R36

R470

27.4_0402_1%

54.9_0402_1%

DD

Close to CPU pin AD26
within 500mils.

CC

BB

Length match within 25 mils
The trace width 18 mils space
7 mils

+1.5VS

1

C70

2

0.01U_0402_16V7K

CPU_BSEL0

1

1

Resistor placed within

0.5" of CPU pin.Trace
should be at least 25
mils away from any
other toggling signal.

12

R473

27.4_0402_1%

1

12

54.9_0402_1%

C72

10U_0805_10V4Z

1

2

CPU_VID045
CPU_VID145
CPU_VID245
CPU_VID345
CPU_VID445
CPU_VID545
CPU_VID645

V_CPU_GTLREF

CPU_BSEL015
CPU_BSEL115
CPU_BSEL215

VCCSENSE45
VSSSENSE45

H_PSI#45

+VCCP

+VCC_CORE

VCCSENSE
VSSSENSE

H_PSI#
CPU_VID0

CPU_VID1
CPU_VID2
CPU_VID3
CPU_VID4
CPU_VID5
CPU_VID6

CPU_BSEL0
CPU_BSEL1
CPU_BSEL2

COMP0
COMP1
COMP2
COMP3

JP8B

AF7

VCCSENSE

AE7

VSSSENSE

B26

VCCA

K6

VCCP

J6

VCCP

M6

VCCP

N6

VCCP

YONAH

T6

VCCP

R6

VCCP

K21

VCCP

J21

VCCP

M21

VCCP

N21

VCCP

T21

VCCP

R21

VCCP

V21

VCCP

W21

VCCP

V6

VCCP

G21

VCCP

AE6

PSI#

AD6

VID0

AF5

VID1

AE5

VID2

AF4

VID3

AE3

VID4

AF2

VID5

AE2

VID6

AD26

GTLREF

B22

BSEL0

B23

BSEL1

C21

BSEL2

R26

COMP0

U26

COMP1

U1

COMP2

V1

COMP3

E7

VCC

AB20

VCC

AA20

VCC

AF20

VCC

AE20

VCC

AB18

VCC

AB17

VCC

AA18

VCC

AA17

VCC

AD18

VCC

AD17

VCC

AC18

VCC

AC17

VCC

AF18

VCC

AF17

VCC

D2

RSVD

F6

RSVD

D3

RSVD

C1

RSVD

AF1

RSVD

D22

RSVD

C23

RSVD

C24

RSVD

AA1

RSVD

AA4

RSVD

AB2

RSVD

AA3

RSVD

M4

RSVD

N5

RSVD

T2

RSVD

V3

RSVD

B2

RSVD

C3

RSVD

T22

RSVD

B25

RSVD

FOX_PZ47903-2741-42_YONAH

AB26

VSS

AA25

VSS

AD25

VSS

AE26

VSS

AB23

VSS

AC24

VSS

AF24

VSS

AE23

VSS

AA22

VSS

AD22

VSS

AC21

VSS

AF21

VSS

AB19

VSS

AA19

VSS

AD19

VSS

AC19

VSS

AF19

VSS

AE19

VSS

AB16

VSS

AA16

VSS

AD16

VSS

AC16

VSS

AF16

VSS

AE16

VSS

AB13

VSS

AA14

VSS

AD13

VSS

AC14

VSS

AF13

VSS

AE14

VSS

AB11

VSS

AA11

VSS

AD11

VSS

AC11

VSS

AF11

VSS

AE11

VSS

AB8

VSS

AA8

VSS

AD8

VSS

AC8

VSS

AF8

VSS

AE8

VSS

AA5

VSS

AD5

VSS

AC6

VSS

AF6

VSS

AB4

VSS

AC3

VSS

POWER, GROUNG, RESERVED SIGNALS AND NC

AF3

VSS

AE4

VSS

AB1

VSS

AA2

VSS

AD2

VSS

AE1

VSS

B6

VSS

C5

VSS

F5

VSS

E6

VSS

H6

VSS

J5

VSS

M5

VSS

L6

VSS

P6

VSS

R5

VSS

V5

VSS

U6

VSS

Y6

VSS

A4

VSS

D4

VSS

E3

VSS

H3

VSS

G4

VSS

K4

VSS

L3

VSS

P3

VSS

N4

VSS

T4

VSS

U3

VSS

Y3

VSS

W4

VSS

D1

VSS

C2

VSS

F2

VSS

G1

VSS

+VCC_CORE

JP8C

AE18

VCC

AE17

VCC

AB15

VCC

AA15

VCC

AD15

VCC

AC15

VCC

AF15

VCC

AE15

VCC

AB14

VCC

AA13

VCC

AD14

VCC

AC13

VCC

AF14

VCC

AE13

VCC

AB12

VCC

AA12

VCC

AD12

VCC

AC12

VCC

AF12

VCC

AE12

VCC

AB10

VCC

AB9

VCC

AA10

VCC

AA9

VCC

AD10

VCC

AD9

VCC

AC10

VCC

AC9

VCC

AF10

VCC

AF9

VCC

AE10

POWER, GROUND

VCC

AE9

VCC

AB7

VCC

AA7

VCC

AD7

VCC

AC7

VCC

B20

VCC

A20

VCC

F20

VCC

E20

VCC

B18

VCC

B17

VCC

A18

VCC

A17

VCC

D18

VCC

D17

VCC

C18

VCC

C17

VCC

F18

VCC

F17

VCC

E18

VCC

E17

VCC

B15

VCC

A15

VCC

D15

VCC

C15

VCC

F15

VCC

E15

VCC

B14

VCC

A13

VCC

D14

VCC

C13

VCC

F14

VCC

E13

VCC

B12

VCC

A12

VCC

D12

VCC

C12

VCC

F12

VCC

E12

VCC

B10

VCC

B9

VCC

A10

VCC

A9

VCC

D10

VCC

D9

VCC

C10

VCC

C9

VCC

F10

VCC

F9

VCC

E10

VCC

E9

VCC

B7

VCC

A7

VCC

F7

VCC

FOX_PZ47903-2741-42_YONAH

YONAH

K1

VSS

J2

VSS

M2

VSS

N1

VSS

T1

VSS

R2

VSS

V2

VSS

W1

VSS

A26

VSS

D26

VSS

C25

VSS

F25

VSS

B24

VSS

A23

VSS

D23

VSS

E24

VSS

B21

VSS

C22

VSS

F22

VSS

E21

VSS

B19

VSS

A19

VSS

D19

VSS

C19

VSS

F19

VSS

E19

VSS

B16

VSS

A16

VSS

D16

VSS

C16

VSS

F16

VSS

E16

VSS

B13

VSS

A14

VSS

D13

VSS

C14

VSS

F13

VSS

E14

VSS

B11

VSS

A11

VSS

D11

VSS

C11

VSS

F11

VSS

E11

VSS

B8

VSS

A8

VSS

D8

VSS

C8

VSS

F8

VSS

E8

VSS

G26

VSS

K26

VSS

J25

VSS

M25

VSS

N26

VSS

T26

VSS

R25

VSS

V25

VSS

W26

VSS

H24

VSS

G23

VSS

K23

VSS

L24

VSS

P24

VSS

N23

VSS

T23

VSS

U24

VSS

Y24

VSS

W23

VSS

H21

VSS

J22

VSS

M22

VSS

L21

VSS

P21

VSS

R22

VSS

V22

VSS

U21

VSS

Y21

VSS

AA

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/03/102006/03/10

Compal Secret Data

Deciphered Date

Title

SizeDocument NumberRev

2

Date:Sheet of

Compal Electronics, Inc.

Yonah CPU in mFCPGA479

LA-2821P

552Friday, November 25, 2005

1

0.5

5

4

3

2

1

DD

Place these capacitors on L8
(North side,Secondary Layer)

Place these capacitors on L8
(North side,Secondary Layer)

Place these capacitors on L8
(Sorth side,Secondary Layer)

CC

Place these capacitors on L8
(Sorth side,Secondary Layer)

South Side Secondary

BB

330U_D2E_2.5VM_R9@

+VCC_CORE

+VCC_CORE

+VCC_CORE

+VCC_CORE

+VCC_CORE

1

C408

2

1

C412
10U_0805_6.3V6M

2

1

C411
10U_0805_6.3V6M

2

1

C441
10U_0805_6.3V6M

2

1

C442
10U_0805_6.3V6M

2

+

C409

330U_D2E_2.5VM_R9@

330U_D2E_2.5VM_R7

1

+

C67

2

1

C413
10U_0805_6.3V6M

2

1

C481
10U_0805_6.3V6M

2

1

C423
10U_0805_6.3V6M

2

1

C435
10U_0805_6.3V6M

2

1

+

C66

2

330U_D2E_2.5VM_R7

1

+

2

1

C414
10U_0805_6.3V6M

2

1

C480
10U_0805_6.3V6M

2

1

C432
10U_0805_6.3V6M

2

1

C436
10U_0805_6.3V6M

2

330U_D2E_2.5VM_R7

1

+

C125

C117

2

330U_D2E_2.5VM_R7

1

2

1

2

1

2

1

2

1

+

2

C415
10U_0805_6.3V6M

C486
10U_0805_6.3V6M

C422
10U_0805_6.3V6M

C443
10U_0805_6.3V6M

820U_E9_2_5V_M_R7@

1

+

C119

2

1

C416
10U_0805_6.3V6M

2

1

C418
10U_0805_6.3V6M

2

1

C446
10U_0805_6.3V6M

2

1

C444
10U_0805_6.3V6M

2

North Side Secondary

1

+

C120

820U_E9_2_5V_M_R7@

2

1

C417
10U_0805_6.3V6M

2

1

C482
10U_0805_6.3V6M

2

1

C424
10U_0805_6.3V6M

2

1

C427
10U_0805_6.3V6M

2

1

2

1

2

1

2

1

2

ESR <= 1.5m ohm
Capacitor > 1980uF

C425
10U_0805_6.3V6M

C483
10U_0805_6.3V6M

C445
10U_0805_6.3V6M

C426
10U_0805_6.3V6M

1

C479
10U_0805_6.3V6M

2

1

C484
10U_0805_6.3V6M

2

1

C485
10U_0805_6.3V6M

2

1

C431
10U_0805_6.3V6M

2

Mid Frequence Decoupling

+VCCP

1

1

220U_D2_2VK_R9

AA

2

+

C434

C437

0.1U_0402_10V6K

2

1

C429

0.1U_0402_10V6K

2

1

C421

0.1U_0402_10V6K

2

1

C438

0.1U_0402_10V6K

2

1

C428

0.1U_0402_10V6K

2

1

C433

0.1U_0402_10V6K

2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

Place these inside
socket cavity on L8
(North side
Secondary)

2005/03/102006/03/10

Compal Secret Data

Deciphered Date

2

Title

SizeDocument NumberRev

Date:Sheet of

Compal Electronics, Inc.

CPU Bypass capacitors

LA-2821P

652Friday, November 25, 2005

1

0.5

5 4 3 2

1

H_D#[0..63]4

DD

CC

+VCCP

12

12

R350

R381

54.9_0402_1%

54.9_0402_1%

H_XSCOMP/H_YSCOMP trace

L

width and spacing is 5/20.

BB

R339

24.9_0402_1%

+VCCP

12

AA

R360

12

R348

H_VREF
H_XRCOMP
H_XSCOMP
H_YRCOMP
H_YSCOMP
H_SWNG0
H_SWNG1

12

12

R395

24.9_0402_1%

Layout Note:
H_XRCOMP / H_YRCOMP / H_VREF / H_SWNG0 /
H_SWNG1 trace width and spacing is 18/20.

100_0402_1%

H_VREF

1

C330

2

200_0402_1%

0.1U_0402_16V4Z

H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63

U4A

F1

HD0#

J1

HD1#

H1

HD2#

J6

HD3#

H3

HD4#

K2

HD5#

G1

HD6#

G2

HD7#

K9

HD8#

K1

HD9#

K7

HD10#

J8

HD11#

H4

HD12#

J3

HD13#

K11

HD14#

G4

HD15#

T10

HD16#

W11

HD17#

T3

HD18#

U7

HD19#

U9

HD20#

U11

HD21#

T11

HD22#

W9

HD23#

T1

HD24#

T8

HD25#

T4

HD26#

W7

HD27#

U5

HD28#

T9

HD29#

W6

HD30#

T5

HD31#

AB7

HD32#

AA9

HD33#

W4

HD34#

W3

HD35#

Y3

HD36#

Y7

HD37#

W5

HD38#

Y10

HD39#

AB8

HD40#

W2

HD41#

AA4

HD42#

AA7

HD43#

AA2

HD44#

AA6

HD45#

AA10

HD46#

Y8

HD47#

AA1

HD48#

AB4

HD49#

AC9

HD50#

AB11

HD51#

AC11

HD52#

AB3

HD53#

AC2

HD54#

AD1

HD55#

AD9

HD56#

AC1

HD57#

AD7

HD58#

AC6

HD59#

AB5

HD60#

AD10

HD61#

AD4

HD62#

AC8

HD63#

J13

HVREF0

K13

HVREF1

E1

HXRCOMP

E2

HXSCOMP

Y1

HYRCOMP

U1

HYSCOMP

E4

HXSWING

W1

HYSWING

CALISTOGA_A2_FCBGA1466

HOST

HA3#
HA4#
HA5#
HA6#
HA7#
HA8#

HA9#
HA10#
HA11#
HA12#
HA13#
HA14#
HA15#
HA16#
HA17#
HA18#
HA19#
HA20#
HA21#
HA22#
HA23#
HA24#
HA25#
HA26#
HA27#
HA28#
HA29#
HA30#
HA31#

HREQ#0
HREQ#1
HREQ#2
HREQ#3
HREQ#4

HADSTB#0
HADSTB#1

HCLKN

HCLKP

HDSTBN#0
HDSTBN#1
HDSTBN#2
HDSTBN#3

HDSTBP#0
HDSTBP#1
HDSTBP#2
HDSTBP#3

HDINV#0
HDINV#1
HDINV#2
HDINV#3

HCPURST#

HADS#

HTRDY#

HDPWR#

HDRDY#

HDEFER#

HHITM#

HHIT#

HLOCK#

HBREQ0#

HBNR#
HBPRI#

HDBSY#

HCPUSLP#

HRS0#
HRS1#
HRS2#

12

R351

12

R344

H_A#3

H9

H_A#4

C9

H_A#5

E11

H_A#6

G11

H_A#7

F11

H_A#8

G12

H_A#9

F9

H_A#10

H11

H_A#11

J12

H_A#12

G14

H_A#13

D9

H_A#14

J14

H_A#15

H13

H_A#16

J15

H_A#17

F14

H_A#18

D12

H_A#19

A11

H_A#20

C11

H_A#21

A12

H_A#22

A13

H_A#23

E13

H_A#24

G13

H_A#25

F12

H_A#26

B12

H_A#27

B14

H_A#28

C12

H_A#29

A14

H_A#30

C14

H_A#31

D14

H_REQ#0

D8

H_REQ#1

G8

H_REQ#2

B8

H_REQ#3

F8

H_REQ#4

A8

H_ADSTB#0

B9

H_ADSTB#1

C13

CLK_MCH_BCLK#

AG1

CLK_MCH_BCLK

AG2

H_DSTBN#0

K4

H_DSTBN#1

T7

H_DSTBN#2

Y5

H_DSTBN#3

AC4

H_DSTBP#0

K3

H_DSTBP#1

T6

H_DSTBP#2

AA5

H_DSTBP#3

AC5

H_DINV#0

J7

H_DINV#1

W8

H_DINV#2

U3

H_DINV#3

AB10

H_RESET#

B7

H_ADS#

E8

H_TRDY#

E7

H_DPWR#

J9

H_DRDY#

H8

H_DEFER#

C3

H_HITM#

D4

H_HIT#

D3

H_LOCK#

B3

H_BR0#

C7

H_BNR#

C6

H_BPRI#

F6

H_DBSY#

A7

H_CPUSLP#

E3

H_RS#0

B4

H_RS#1

E6

H_RS#2

D6

221_0603_1%

H_SWNG0

1

C328

2

100_0402_1%

0.1U_0402_16V4Z

+VCCP+VCCP

12

R17

12

R18

H_A#[3..31]4

H_REQ#[0..4]4

H_ADSTB#04
H_ADSTB#14

CLK_MCH_BCLK#15
CLK_MCH_BCLK15
H_DSTBN#[0..3]4

H_DSTBP#[0..3]4

H_DINV#04
H_DINV#14
H_DINV#24
H_DINV#34

H_RESET#4
H_ADS#4
H_TRDY#4
H_DPWR#4
H_DRDY#4
H_DEFER#4
H_HITM#4
H_HIT#4
H_LOCK#4
H_BR0#4
H_BNR#4
H_BPRI#4
H_DBSY#4
H_CPUSLP#4

H_RS#[0..2]4

221_0603_1%

H_SWNG1

1

C359

2

100_0402_1%

0.1U_0402_16V4Z

U4B

AE35
AF39
AG35
AH39

AC35
AE39
AF35
AG39

AE37
AF41
AG37
AH41

AC37
AE41
AF37
AG41

AY35

AR1

AW7

AW40
AW35

AT1
AY7

AY40
AU20

AT20
BA29
AY29

AW13
AW12

AY21

AW21

AL20
AF10

BA13
BA12
AY20
AU21

AV9
AT9

AK1

AK41

G28

F25

H26

G6
AH33
AH34

K28

CALISTOGA_A2_FCBGA1466

Layout Note:
Route as short
as possible

12

R412

40.2_0402_1%

DMIRXN0
DMIRXN1
DMIRXN2
DMIRXN3

DMIRXP0
DMIRXP1
DMIRXP2
DMIRXP3

DMITXN0
DMITXN1
DMITXN2
DMITXN3

DMITXP0
DMITXP1
DMITXP2
DMITXP3

SM_CK0
SM_CK1
SM_CK2
SM_CK3

SM_CK0#
SM_CK1#
SM_CK2#
SM_CK3#

SM_CKE0
SM_CKE1
SM_CKE2
SM_CKE3

SM_CS0#
SM_CS1#
SM_CS2#
SM_CS3#

SM_OCDCOMP0
SM_OCDCOMP1

SM_ODT0
SM_ODT1
SM_ODT2
SM_ODT3

SM_RCOMPN
SM_RCOMPP

SM_VREF0
SM_VREF1

PM_BMBUSY#
PM_EXTTS0#
PM_EXTTS1#
PM_THERMTRIP#
PWROK
RSTIN#

ICH_SYNC#

12

R400

40.2_0402_1%

DMI

DDR MUXING

M_OCDOCMP0
M_OCDOCMP1

PM

DDR_THERM#13,14

+1.8V

12

12

R409

100_0402_1%@

12

R411

100_0402_1%@

DMI_TXN0
DMI_TXN1
DMI_TXN2
DMI_TXN3

DMI_TXP0
DMI_TXP1
DMI_TXP2
DMI_TXP3

DMI_RXN0
DMI_RXN1
DMI_RXN2
DMI_RXN3

DMI_RXP0
DMI_RXP1
DMI_RXP2
DMI_RXP3

M_CLK_DDR0
M_CLK_DDR1
M_CLK_DDR2
M_CLK_DDR3

M_CLK_DDR#0
M_CLK_DDR#1
M_CLK_DDR#2
M_CLK_DDR#3

DDR_CKE0_DIMMA
DDR_CKE1_DIMMA
DDR_CKE2_DIMMB
DDR_CKE3_DIMMB

DDR_CS0_DIMMA#
DDR_CS1_DIMMA#
DDR_CS2_DIMMB#
DDR_CS3_DIMMB#

M_OCDOCMP0
M_OCDOCMP1

M_ODT0
M_ODT1
M_ODT2
M_ODT3

SMRCOMPN
SMRCOMPP

PM_BMBUSY#
PM_EXTTS#0
PM_EXTTS#1
H_THERMTRIP#
PWROK
PLTRST_R#

PWROK

DMI_TXN021
DMI_TXN121
DMI_TXN221
DMI_TXN321

DMI_TXP021
DMI_TXP121
DMI_TXP221
DMI_TXP321

DMI_RXN021
DMI_RXN121
DMI_RXN221
DMI_RXN321

DMI_RXP021
DMI_RXP121
DMI_RXP221
DMI_RXP321

M_CLK_DDR013
M_CLK_DDR113
M_CLK_DDR214
M_CLK_DDR314

M_CLK_DDR#013
M_CLK_DDR#113
M_CLK_DDR#214
M_CLK_DDR#314

DDR_CKE0_DIMMA13
DDR_CKE1_DIMMA13
DDR_CKE2_DIMMB14
DDR_CKE3_DIMMB14

DDR_CS0_DIMMA#13
DDR_CS1_DIMMA#13
DDR_CS2_DIMMB#14
DDR_CS3_DIMMB#14

+1.8V

R41980.6_0402_1%
R41380.6_0402_1%

DPRSLPVR21,45

VGATE_INTEL21,45

V_DDR_MCH_REF13,14,44

R650_0402_5%

PLT_RST#19,20,21,23,25,27,32,33

PM_POK21,33

R5970_0402_5%@
R5900_0402_5%

M_ODT013
M_ODT113
M_ODT214
M_ODT314

1 2
1 2

V_DDR_MCH_REF

PM_BMBUSY#21

1 2

H_THERMTRIP#4,20

R408100_0402_1%

MCH_ICH_SYNC#19

1 2
1 2

Layout Note:
V_DDR_MCH_REF
trace width and
spacing is 20/20.

V_DDR_MCH_REF

1

C385

2

0.1U_0402_16V4Z

Stuff R1202 & R1203 for A1 Calistoga

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2005/03/102006/03/10

Compal Secret Data

Deciphered Date

2

CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8

CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG16

CFG

CFG17
CFG18
CFG19
CFG20

G_CLKP

G_CLKN

D_REF_CLKN
D_REF_CLKP

CLKNC

D_REF_SSCLKN
D_REF_SSCLKP

CLK_REQ#

NC0
NC1
NC2
NC3
NC4
NC5
NC6
NC7
NC8

NC9
NC10
NC11
NC12
NC13
NC14
NC15
NC16
NC17
NC18

RESERVED1
RESERVED2
RESERVED3
RESERVED4
RESERVED5
RESERVED6
RESERVED7
RESERVED8

RESERVED9
RESERVED10
RESERVED11
RESERVED12
RESERVED13

RESERVED

PM_EXTTS#0

PM_EXTTS#1

GMCH_A27

GMCH_A26

GMCH_C40

GMCH_D41

Title

SizeDocument NumberRev

Date:Sheet of

Description at page11.

MCH_CLKSEL0

K16

MCH_CLKSEL1

K18

MCH_CLKSEL2

J18

CFG3

F18

CFG4

E15

CFG5

F15

CFG6

E18

CFG7

D19

CFG8

D16

CFG9

G16

CFG10

E16

CFG11

D15

CFG12

G15

CFG13

K15

CFG14

C15

CFG15

H16

CFG16

G18

CFG17

H15

CFG18

J25

CFG19

K27

CFG20

J26

CLK_MCH_3GPLL

AG33

CLK_MCH_3GPLL#

AF33

GMCH_A27

A27

GMCH_A26

A26

GMCH_C40

C40

GMCH_D41

D41

CLKREQC#

H32

A3
A39
A4
A40
AW1
AW41
AY1
BA1
BA2
BA3
BA39
BA40
BA41
C1
AY41
B2
B41
C41
D1

T32
R32
F3
F7
AG11
AF11
H7
J19
A41
A34
D28
D27
A35

R353

10K_0402_5%

R362

10K_0402_5%@

R15

10K_0402_5%

R14

10K_0402_5%

R338

10K_0402_5%

R342

10K_0402_5%

R343

0_0402_5%

5/16

PAD
PAD

PAD
PAD
PAD

PAD
PAD

PAD

12

12

8/24

12

12

12

12

PM_EXTTS#0DDR_THERM#

12

MCH_CLKSEL015
MCH_CLKSEL115

MCH_CLKSEL215

T1
T2

CFG511

T4

CFG711

T3

CFG911

T7

CFG1111

CFG1211

CFG1311

T6
T5

CFG1611

T8

CFG1811

CFG1911

CFG2011

CLK_MCH_3GPLL15

CLK_MCH_3GPLL#15

CLKREQC#15

+3VS

Compal Electronics, Inc.

Calistoga (1/6)

LA-2821P

752Friday, November 25, 2005

1

0.5

5

DD

4

3

2

1

DDR_A_BS#013
DDR_A_BS#113
DDR_A_BS#213

DDR_A_DM[0..7]13

DDR_A_DQS[0..7]13

CC

DDR_A_DQS#[0..7]13

DDR_A_MA[0..13]13

BB

DDR_A_CAS#13
DDR_A_RAS#13

DDR_A_WE#13

T11PAD
T12PAD T10PAD

DDR_A_BS#0
DDR_A_BS#1
DDR_A_BS#2

DDR_A_DM0
DDR_A_DM1
DDR_A_DM2
DDR_A_DM3
DDR_A_DM4
DDR_A_DM5
DDR_A_DM6
DDR_A_DM7

DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7

DDR_A_DQS#0
DDR_A_DQS#1
DDR_A_DQS#2
DDR_A_DQS#3
DDR_A_DQS#4
DDR_A_DQS#5
DDR_A_DQS#6
DDR_A_DQS#7

DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5

DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11 DDR_B_MA11
DDR_A_MA12
DDR_A_MA13

DDR_A_CAS#
DDR_A_RAS#
DDR_A_WE#
SA_RCVENIN#
SA_RCVENOUT#

U4D

AU12

SA_BS0

AV14

SA_BS1

BA20

SA_BS2

AJ33

SA_DM0

AM35

SA_DM1

AL26

SA_DM2

AN22

SA_DM3

AM14

SA_DM4

AL9

SA_DM5

AR3

SA_DM6

AH4

SA_DM7

AK33

SA_DQS0

AT33

SA_DQS1

AN28

SA_DQS2

AM22

SA_DQS3

AN12

SA_DQS4

AN8

SA_DQS5

AP3

SA_DQS6

AG5

SA_DQS7

AK32

SA_DQS0#

AU33

SA_DQS1#

AN27

SA_DQS2#

AM21

SA_DQS3#

AM12

SA_DQS4#

AL8

SA_DQS5#

AN3

SA_DQS6#

AH5

SA_DQS7#

AY16

SA_MA0

AU14

SA_MA1

AW16

SA_MA2

BA16

SA_MA3

BA17

SA_MA4

AU16

SA_MA5

AV17

SA_MA6

AU17

SA_MA7

AW17

SA_MA8

AT16

SA_MA9

AU13

SA_MA10

AT17

SA_MA11

AV20

SA_MA12

AV12

SA_MA13

AY13

SA_CAS#

AW14

SA_RAS#

AY14

SA_WE#

AK23

SA_RCVENIN#

AK24

SA_RCVENOUT#

CALISTOGA_A2_FCBGA1466

SA_DQ0
SA_DQ1
SA_DQ2
SA_DQ3
SA_DQ4
SA_DQ5
SA_DQ6
SA_DQ7
SA_DQ8

SA_DQ9
SA_DQ10
SA_DQ11
SA_DQ12
SA_DQ13
SA_DQ14
SA_DQ15
SA_DQ16
SA_DQ17
SA_DQ18
SA_DQ19
SA_DQ20
SA_DQ21
SA_DQ22
SA_DQ23
SA_DQ24
SA_DQ25
SA_DQ26
SA_DQ27
SA_DQ28
SA_DQ29
SA_DQ30
SA_DQ31
SA_DQ32
SA_DQ33
SA_DQ34
SA_DQ35
SA_DQ36
SA_DQ37
SA_DQ38
SA_DQ39

DDR SYS MEMORY A

SA_DQ40
SA_DQ41
SA_DQ42
SA_DQ43
SA_DQ44
SA_DQ45
SA_DQ46
SA_DQ47
SA_DQ48
SA_DQ49
SA_DQ50
SA_DQ51
SA_DQ52
SA_DQ53
SA_DQ54
SA_DQ55
SA_DQ56
SA_DQ57
SA_DQ58
SA_DQ59
SA_DQ60
SA_DQ61
SA_DQ62
SA_DQ63

AJ35
AJ34
AM31
AM33
AJ36
AK35
AJ32
AH31
AN35
AP33
AR31
AP31
AN38
AM36
AM34
AN33
AK26
AL27
AM26
AN24
AK28
AL28
AM24
AP26
AP23
AL22
AP21
AN20
AL23
AP24
AP20
AT21
AR12
AR14
AP13
AP12
AT13
AT12
AL14
AL12
AK9
AN7
AK8
AK7
AP9
AN9
AT5
AL5
AY2
AW2
AP1
AN2
AV2
AT3
AN1
AL2
AG7
AF9
AG4
AF6
AG9
AH6
AF4
AF8

DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63

DDR_A_D[0..63]13 DDR_B_D[0..63]14

DDR_B_BS#014
DDR_B_BS#114
DDR_B_BS#214

DDR_B_DM[0..7]14

DDR_B_DQS[0..7]14

DDR_B_DQS#[0..7]14

DDR_B_MA[0..13]14

DDR_B_CAS#14

DDR_B_RAS#14

DDR_B_WE#14

T9PAD

DDR_B_BS#0
DDR_B_BS#1
DDR_B_BS#2

DDR_B_DM0
DDR_B_DM1
DDR_B_DM2
DDR_B_DM3
DDR_B_DM4
DDR_B_DM5
DDR_B_DM6
DDR_B_DM7

DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4
DDR_B_DQS5
DDR_B_DQS6
DDR_B_DQS7

DDR_B_DQS#0
DDR_B_DQS#1
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS#4
DDR_B_DQS#5
DDR_B_DQS#6
DDR_B_DQS#7

DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6DDR_A_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10

DDR_B_MA12
DDR_B_MA13

DDR_B_CAS#
DDR_B_RAS#
DDR_B_WE#
SB_RCVENIN#
SB_RCVENOUT#

U4E

AT24

SB_BS0

AV23

SB_BS1

AY28

SB_BS2

AK36

SB_DM0

AR38

SB_DM1

AT36

SB_DM2

BA31

SB_DM3

AL17

SB_DM4

AH8

SB_DM5

BA5

SB_DM6

AN4

SB_DM7

AM39

SB_DQS0

AT39

SB_DQS1

AU35

SB_DQS2

AR29

SB_DQS3

AR16

SB_DQS4

AR10

SB_DQS5

AR7

SB_DQS6

AN5

SB_DQS7

AM40

SB_DQS0#

AU39

SB_DQS1#

AT35

SB_DQS2#

AP29

SB_DQS3#

AP16

SB_DQS4#

AT10

SB_DQS5#

AT7

SB_DQS6#

AP5

SB_DQS7#

AY23

SB_MA0

AW24

SB_MA1

AY24

SB_MA2

AR28

SB_MA3

AT27

SB_MA4

AT28

SB_MA5

AU27

SB_MA6

AV28

SB_MA7

AV27

SB_MA8

AW27

SB_MA9

AV24

SB_MA10

BA27

SB_MA11

AY27

SB_MA12

AR23

SB_MA13

AR24

SB_CAS#

AU23

SB_RAS#

AR27

SB_WE#

AK16

SB_RCVENIN#

AK18

SB_RCVENOUT#

CALISTOGA_A2_FCBGA1466

SB_DQ0
SB_DQ1
SB_DQ2
SB_DQ3
SB_DQ4
SB_DQ5
SB_DQ6
SB_DQ7
SB_DQ8

SB_DQ9
SB_DQ10
SB_DQ11
SB_DQ12
SB_DQ13
SB_DQ14
SB_DQ15
SB_DQ16
SB_DQ17
SB_DQ18
SB_DQ19
SB_DQ20
SB_DQ21
SB_DQ22
SB_DQ23
SB_DQ24
SB_DQ25
SB_DQ26
SB_DQ27
SB_DQ28
SB_DQ29
SB_DQ30
SB_DQ31
SB_DQ32
SB_DQ33
SB_DQ34
SB_DQ35
SB_DQ36
SB_DQ37
SB_DQ38
SB_DQ39

DDR SYS MEMORY B

SB_DQ40
SB_DQ41
SB_DQ42
SB_DQ43
SB_DQ44
SB_DQ45
SB_DQ46
SB_DQ47
SB_DQ48
SB_DQ49
SB_DQ50
SB_DQ51
SB_DQ52
SB_DQ53
SB_DQ54
SB_DQ55
SB_DQ56
SB_DQ57
SB_DQ58
SB_DQ59
SB_DQ60
SB_DQ61
SB_DQ62
SB_DQ63

AJ37
AP39
AR41
AJ38
AK38
AN41
AP41
AT40
AV41
AU38
AV38
AP38
AR40
AW38
AY38
BA38
AV36
AR36
AP36
BA36
AU36
AP35
AP34
AY33
BA33
AT31
AU29
AU31
AW31
AV29
AW29
AM19
AL19
AP14
AN14
AN17
AM16
AP15
AL15
AJ11
AH10
AJ9
AN10
AK13
AH11
AK10
AJ8
BA10
AW10
BA4
AW4
AY10
AY9
AW5
AY5
AV4
AR5
AK4
AK3
AT4
AK5
AJ5
AJ3

DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63

DDR_B_D0

AK39

AA

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/03/102006/03/10

Compal Secret Data

Deciphered Date

Title

SizeDocument NumberRev

2

Date:Sheet of

Compal Electronics, Inc.

Calistoga (2/6)

LA-2821P

852Friday, November 25, 2005

1

0.5

5

DD

CC

R36310K_0402_5%

BB

R35510K_0402_5%

+VCCP

4

U4C

H27

SDVOCTRL_DATA

H28

SDVOCTRL_CLK

B37

LA_DATA0

B34

LA_DATA1

A36

LA_DATA2

C37

LA_DATA#0

B35

LA_DATA#1

A37

LA_DATA#2

F30

LB_DATA0

D29

LB_DATA1

F28

LB_DATA2

G30

LB_DATA#0

D30

LB_DATA#1

F29

LB_DATA#2

A32

LA_CLK

A33

LA_CLK#

E26

LB_CLK

E27

LB_CLK#

D32

LBKLT_CTL

J30

LBKLT_EN

H30

LCTLA_CLK

H29

LCTLB_DATA

G26

LDDC_CLK

G25

LDDC_DATA

F32

LVDD_EN

B38

LIBG

C35

LVBG

C33

LVREFH

C32

LVREFL

+1.5VS

A16

TVDAC_A

C18

TVDAC_B

A19

TVDAC_C

J20

TV_IREF

B16

TV_IRTNA

B18

TV_IRTNB

B19

TV_IRTNC

J29

TV_DCONSEL1

K30

TV_DCONSEL0

C26

DDCCLK

C25

DDCDATA

12
12

H23

VSYNC

G23

HSYNC

E23

BLUE

D23

BLUE#

C22

GREEN

B22

GREEN#

A21

RED

B21

RED#

J22

CRT_IREF

CALISTOGA_A2_FCBGA1466

LVDS

TV CRT

PCI-EXPRESS GRAPHICS

3

PEGCOMP trace width

L

and spacing is 18/25 mils.

D40

EXP_COMPI

D38

EXP_COMPO

F34

EXP_RXN0

G38

EXP_RXN1

H34

EXP_RXN2

J38

EXP_RXN3

L34

EXP_RXN4

M38

EXP_RXN5

N34

EXP_RXN6

P38

EXP_RXN7

R34

EXP_RXN8

T38

EXP_RXN9

V34

EXP_RXN10

W38

EXP_RXN11

Y34

EXP_RXN12

AA38

EXP_RXN13

AB34

EXP_RXN14

AC38

EXP_RXN15

D34

EXP_RXP0

F38

EXP_RXP1

G34

EXP_RXP2

H38

EXP_RXP3

J34

EXP_RXP4

L38

EXP_RXP5

M34

EXP_RXP6

N38

EXP_RXP7

P34

EXP_RXP8

R38

EXP_RXP9

T34

EXP_RXP10

V38

EXP_RXP11

W34

EXP_RXP12

Y38

EXP_RXP13

AA34

EXP_RXP14

AB38

EXP_RXP15

F36

EXP_TXN0

G40

EXP_TXN1

H36

EXP_TXN2

J40

EXP_TXN3

L36

EXP_TXN4

M40

EXP_TXN5

N36

EXP_TXN6

P40

EXP_TXN7

R36

EXP_TXN8

T40

EXP_TXN9

V36

EXP_TXN10

W40

EXP_TXN11

Y36

EXP_TXN12

AA40

EXP_TXN13

AB36

EXP_TXN14

AC40

EXP_TXN15

D36

EXP_TXP0

F40

EXP_TXP1

G36

EXP_TXP2

H40

EXP_TXP3

J36

EXP_TXP4

L40

EXP_TXP5

M36

EXP_TXP6

N40

EXP_TXP7

P36

EXP_TXP8

R40

EXP_TXP9

T36

EXP_TXP10

V40

EXP_TXP11

W36

EXP_TXP12

Y40

EXP_TXP13

AA36

EXP_TXP14

AB40

EXP_TXP15

PEGCOMP

PEG_RXP15
PEG_RXP14
PEG_RXP13
PEG_RXP12
PEG_RXP11
PEG_RXP10
PEG_RXP9
PEG_RXP8
PEG_RXP7
PEG_RXP6
PEG_RXP5
PEG_RXP4
PEG_RXP3
PEG_RXP2
PEG_RXP1
PEG_RXP0

PEG_RXN15
PEG_RXN14
PEG_RXN13
PEG_RXN12
PEG_RXN11
PEG_RXN10
PEG_RXN9
PEG_RXN8
PEG_RXN7
PEG_RXN6
PEG_RXN5
PEG_RXN4
PEG_RXN3
PEG_RXN2
PEG_RXN1
PEG_RXN0

PEG_TXP15
PEG_TXP14
PEG_TXP13
PEG_TXP12
PEG_TXP11
PEG_TXP10
PEG_TXP9
PEG_TXP8
PEG_TXP7
PEG_TXP6
PEG_TXP5
PEG_TXP4
PEG_TXP3
PEG_TXP2
PEG_TXP1
PEG_TXP0

PEG_TXN15
PEG_TXN14
PEG_TXN13
PEG_TXN12
PEG_TXN11
PEG_TXN10
PEG_TXN9
PEG_TXN8
PEG_TXN7
PEG_TXN6
PEG_TXN5
PEG_TXN4
PEG_TXN3
PEG_TXN2
PEG_TXN1
PEG_TXN0

+1.5VS_PCIE

R331

24.9_0402_1%

1 2

C220.1U_0402_16V4Z
C240.1U_0402_16V4Z
C260.1U_0402_16V4Z
C300.1U_0402_16V4Z
C320.1U_0402_16V4Z
C340.1U_0402_16V4Z
C370.1U_0402_16V4Z
C410.1U_0402_16V4Z
C450.1U_0402_16V4Z
C470.1U_0402_16V4Z
C490.1U_0402_16V4Z
C510.1U_0402_16V4Z
C530.1U_0402_16V4Z
C560.1U_0402_16V4Z
C580.1U_0402_16V4Z
C610.1U_0402_16V4Z

C200.1U_0402_16V4Z
C230.1U_0402_16V4Z
C250.1U_0402_16V4Z
C280.1U_0402_16V4Z
C310.1U_0402_16V4Z
C330.1U_0402_16V4Z
C350.1U_0402_16V4Z
C380.1U_0402_16V4Z
C430.1U_0402_16V4Z
C460.1U_0402_16V4Z
C480.1U_0402_16V4Z
C500.1U_0402_16V4Z
C520.1U_0402_16V4Z
C540.1U_0402_16V4Z
C570.1U_0402_16V4Z
C600.1U_0402_16V4Z

PEG_RXP[0..15]18

PEG_RXN[0..15]18

PEG_M_TXP15
PEG_M_TXP14
PEG_M_TXP13
PEG_M_TXP12
PEG_M_TXP11
PEG_M_TXP10
PEG_M_TXP9
PEG_M_TXP8
PEG_M_TXP7
PEG_M_TXP6
PEG_M_TXP5
PEG_M_TXP4
PEG_M_TXP3
PEG_M_TXP2
PEG_M_TXP1
PEG_M_TXP0

PEG_M_TXN15
PEG_M_TXN14
PEG_M_TXN13
PEG_M_TXN12
PEG_M_TXN11
PEG_M_TXN10
PEG_M_TXN9
PEG_M_TXN8
PEG_M_TXN7
PEG_M_TXN6
PEG_M_TXN5
PEG_M_TXN4
PEG_M_TXN3
PEG_M_TXN2
PEG_M_TXN1
PEG_M_TXN0

2

PEG_M_TXP[0..15]18

PEG_M_TXN[0..15]18

1

AA

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/03/102006/03/10

Compal Secret Data

Deciphered Date

Title

SizeDocument NumberRev

2

Date:Sheet of

Compal Electronics, Inc.

Calistoga (3/6)

LA-2821P

952Friday, November 25, 2005

1

0.5

5

4

3

2

1

DD

1

+

C42

220U_D2_2VK_R9

CC

BB

AA

2

1

C339

2

4.7U_0805_10V4Z

1

C336

2

1

0.22U_0603_10V7K

2

+VCCP

1

C368

2

2.2U_0805_16V4Z

MCH_A6

1

C317

2

0.47U_0603_10V7K

MCH_D2

C318

MCH_AB1

1

C55

0.22U_0603_10V7K

2

0.47U_0603_10V7K

+1.5VS

U4H

AC14

VTT0

AB14

VTT1

W14

VTT2

V14

VTT3

T14

VTT4

R14

VTT5

P14

VTT6

N14

VTT7

M14

VTT8

L14

VTT9

AD13

VTT10

AC13

VTT11

AB13

VTT12

AA13

VTT13

Y13

VTT14

W13

VTT15

V13

VTT16

U13

VTT17

T13

VTT18

R13

VTT19

N13

VTT20

M13

VTT21

L13

VTT22

AB12

VTT23

AA12

VTT24

Y12

VTT25

W12

VTT26

V12

VTT27

U12

VTT28

T12

VTT29

R12

VTT30

P12

VTT31

N12

VTT32

M12

VTT33

L12

VTT34

R11

VTT35

P11

VTT36

N11

VTT37

M11

VTT38

R10

VTT39

P10

VTT40

N10

VTT41

M10

VTT42

P9

VTT43

N9

VTT44

M9

VTT45

R8

VTT46

P8

VTT47

N8

VTT48

M8

VTT49

P7

VTT50

N7

VTT51

M7

VTT52

R6

VTT53

P6

VTT54

M6

VTT55

A6

VTT56

R5

VTT57

P5

VTT58

N5

VTT59

M5

VTT60

P4

VTT61

N4

VTT62

M4

VTT63

R3

VTT64

P3

VTT65

N3

VTT66

M3

VTT67

R2

VTT68

P2

VTT69

M2

VTT70

D2

VTT71

AB1

VTT72

R1

VTT73

P1

VTT74

N1

VTT75

M1

VTT76

AG14

VCCAUX32

AF14

VCCAUX33

AE14

VCCAUX34

Y14

VCCAUX35

AF13

VCCAUX36

AE13

VCCAUX37

AF12

VCCAUX38

AE12

VCCAUX39

AD12

VCCAUX40

CALISTOGA_A2_FCBGA1466

P O W E R

VCC_SYNC

VCCTX_LVDS0
VCCTX_LVDS1
VCCTX_LVDS2

VCC3G0
VCC3G1
VCC3G2
VCC3G3
VCC3G4
VCC3G5
VCC3G6

VCCA_3GPLL

VCCA_3GBG

VSSA_3GBG

VCCA_CRTDAC0
VCCA_CRTDAC1
VSSA_CRTDAC2

VCCA_DPLLA
VCCA_DPLLB

VCCA_HPLL

VCCA_LVDS
VSSA_LVDS

VCCA_MPLL

VCCA_TVBG

VSSA_TVBG

VCCA_TVDACA0
VCCA_TVDACA1
VCCA_TVDACB0

VCCA_TVDACB1
VCCA_TVDACC0
VCCA_TVDACC1

VCCD_HMPLL0
VCCD_HMPLL1

VCCD_LVDS0
VCCD_LVDS1
VCCD_LVDS2

VCCD_TVDAC

VCCDQ_TVDAC

VCCHV0
VCCHV1
VCCHV2

VCCAUX0
VCCAUX1
VCCAUX2
VCCAUX3
VCCAUX4
VCCAUX5
VCCAUX6
VCCAUX7
VCCAUX8

VCCAUX9
VCCAUX10
VCCAUX11
VCCAUX12
VCCAUX13
VCCAUX14
VCCAUX15
VCCAUX16
VCCAUX17
VCCAUX18
VCCAUX19
VCCAUX20
VCCAUX21
VCCAUX22
VCCAUX23
VCCAUX24
VCCAUX25
VCCAUX26
VCCAUX27
VCCAUX28
VCCAUX29
VCCAUX30
VCCAUX31

H22

B30
C30
A30

AB41
AJ41
L41
N41
R41
V41
Y41

AC33
G41
H41

E21
F21
G21

B26
C39
AF1

A38
B39

AF2
H20

G20

E19
F19
C20
D20
E20
F20

AH1
AH2

A28
B28
C28

D21
H19

A23
B23
B25

AK31
AF31
AE31
AC31
AL30
AK30
AJ30
AH30
AG30
AF30
AE30
AD30
AC30
AG29
AF29
AE29
AD29
AC29
AG28
AF28
AE28
AH22
AJ21
AH21
AJ20
AH20
AH19
P19
P16
AH15
P15
AH14

W=40 mils

220U_D2_4VM_R25

+1.5VS_3GPLL
+2.5VS

MCH_CRTDAC

PAD-No SHORT 2x2m

R333

1 2

0_0805_5% @

+1.5VS_HPLL

1 2

R356

0_0805_5%

+1.5VS_MPLL
+1.5VS

+1.5VS

+1.5VS

+1.5VS_TVDAC

+1.5VS

1

C377

2

C297

9/15

J5

2 1

PAD-SHORT 2x2m

J4

2 1

1

2

C322

0.1U_0402_16V4Z

0.1U_0402_16V4Z

+1.5VS_PCIE

10U_0805_6.3V6M

1

+

2

+VCCP

+2.5VS

+3VS

1

C320
10U_0805_6.3V6M

2

1

2

C315

R410

0_0805_5%

C380

1

10U_0805_6.3V6M

2

12

+1.5VS

+2.5VS

1

C329

2

0.1U_0402_16V4Z

close pin G41

PCI-E/MEM/PSB PLL decoupling

R398

1 2

0.5_0805_1%

1

1

C371

0.1U_0402_16V4Z

2

C378
10U_0805_6.3V6M

2

+1.5VS_MPLL

45mA Max.45mA Max.

1

C373

0.1U_0402_16V4Z

2

R23

0_0805_5%

1

C62
10U_0805_6.3V6M

2

R396

0_0805_5%

0.1U_0402_16V4Z@

12

12

C387

+1.5VS+1.5VS_3GPLL

+1.5VS_TVDAC +1.5VS

0.022U_0402_16V7K@

1

2

0.1U_0402_16V4Z

1

2

+1.5VS_HPLL

1

C374

2

C324

10U_0805_6.3V6M@

0_0805_5%

1

C316

2

0_0805_5%

1

C59
10U_0805_6.3V6M

2

R332

R22

12

1

C319

0.022U_0402_16V7K@

2

12

+1.5VS+1.5VS

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2005/03/102006/03/10

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

SizeDocument NumberRev

2

Date:Sheet of

Calistoga (4/6)

LA-2821P

1052Friday, November 25, 2005

1

0.5

5 4 3 2

1

Strap Pin Table

CFG[3:17] have internal pull up

+VCCP

DD

1

1

C367

2

0.22U_0603_10V7K

10U_0805_6.3V6M

1

C337

2

10U_0805_6.3V6M

CC

330U_D2E_2.5VM_R9@

BB

C333

C375

2

0.22U_0603_10V7K

1

C338

C343

2

C64

220U_D2_2VK_R9

1

C386

+

2

0.22U_0603_10V7K

1U_0603_10V4Z

1

2

1

2

+VCCP

1

+

2

U4F

AD27

VCC_NCTF0

AC27

VCC_NCTF1

AB27

VCC_NCTF2

AA27

VCC_NCTF3

Y27

VCC_NCTF4

W27

VCC_NCTF5

V27

VCC_NCTF6

U27

VCC_NCTF7

T27

VCC_NCTF8

R27

VCC_NCTF9

AD26

VCC_NCTF10

AC26

VCC_NCTF11

AB26

VCC_NCTF12

AA26

VCC_NCTF13

Y26

VCC_NCTF14

W26

VCC_NCTF15

V26

VCC_NCTF16

U26

VCC_NCTF17

T26

VCC_NCTF18

R26

VCC_NCTF19

AD25

VCC_NCTF20

AC25

VCC_NCTF21

AB25

VCC_NCTF22

AA25

VCC_NCTF23

Y25

VCC_NCTF24

W25

VCC_NCTF25

V25

VCC_NCTF26

U25

VCC_NCTF27

T25

VCC_NCTF28

R25

VCC_NCTF29

AD24

VCC_NCTF30

AC24

VCC_NCTF31

AB24

VCC_NCTF32

AA24

VCC_NCTF33

Y24

VCC_NCTF34

W24

VCC_NCTF35

V24

VCC_NCTF36

U24

VCC_NCTF37

T24

VCC_NCTF38

R24

VCC_NCTF39

AD23

VCC_NCTF40

V23

VCC_NCTF41

U23

VCC_NCTF42

T23

VCC_NCTF43

R23

VCC_NCTF44

AD22

VCC_NCTF45

V22

VCC_NCTF46

U22

VCC_NCTF47

T22

VCC_NCTF48

R22

VCC_NCTF49

AD21

VCC_NCTF50

V21

VCC_NCTF51

U21

VCC_NCTF52

T21

VCC_NCTF53

R21

VCC_NCTF54

AD20

VCC_NCTF55

V20

VCC_NCTF56

U20

VCC_NCTF57

T20

VCC_NCTF58

R20

VCC_NCTF59

AD19

VCC_NCTF60

V19

VCC_NCTF61

U19

VCC_NCTF62

T19

VCC_NCTF63

AD18

VCC_NCTF64

AC18

VCC_NCTF65

AB18

VCC_NCTF66

AA18

VCC_NCTF67

Y18

VCC_NCTF68

W18

VCC_NCTF69

V18

VCC_NCTF70

U18

VCC_NCTF71

T18

VCC_NCTF72

M19

VCC100

L19

VCC101

N18

VCC102

M18

VCC103

L18

VCC104

P17

VCC105

N17

VCC106

M17

VCC107

N16

VCC108

M16

VCC109

L16

VCC110

CALISTOGA_A2_FCBGA1466

VCCAUX_NCTF0
VCCAUX_NCTF1
VCCAUX_NCTF2
VCCAUX_NCTF3
VCCAUX_NCTF4
VCCAUX_NCTF5
VCCAUX_NCTF6
VCCAUX_NCTF7
VCCAUX_NCTF8

VCCAUX_NCTF9
VCCAUX_NCTF10
VCCAUX_NCTF11
VCCAUX_NCTF12
VCCAUX_NCTF13
VCCAUX_NCTF14
VCCAUX_NCTF15
VCCAUX_NCTF16
VCCAUX_NCTF17
VCCAUX_NCTF18
VCCAUX_NCTF19
VCCAUX_NCTF20
VCCAUX_NCTF21
VCCAUX_NCTF22
VCCAUX_NCTF23
VCCAUX_NCTF24
VCCAUX_NCTF25
VCCAUX_NCTF26
VCCAUX_NCTF27
VCCAUX_NCTF28
VCCAUX_NCTF29
VCCAUX_NCTF30
VCCAUX_NCTF31
VCCAUX_NCTF32
VCCAUX_NCTF33
VCCAUX_NCTF34
VCCAUX_NCTF35
VCCAUX_NCTF36

P O W E R

VCCAUX_NCTF37
VCCAUX_NCTF38
VCCAUX_NCTF39
VCCAUX_NCTF40
VCCAUX_NCTF41
VCCAUX_NCTF42
VCCAUX_NCTF43
VCCAUX_NCTF44
VCCAUX_NCTF45
VCCAUX_NCTF46
VCCAUX_NCTF47
VCCAUX_NCTF48
VCCAUX_NCTF49
VCCAUX_NCTF50
VCCAUX_NCTF51
VCCAUX_NCTF52
VCCAUX_NCTF53
VCCAUX_NCTF54
VCCAUX_NCTF55
VCCAUX_NCTF56
VCCAUX_NCTF57

VSS_NCTF0
VSS_NCTF1
VSS_NCTF2
VSS_NCTF3
VSS_NCTF4
VSS_NCTF5
VSS_NCTF6
VSS_NCTF7
VSS_NCTF8

VSS_NCTF9
VSS_NCTF10
VSS_NCTF11
VSS_NCTF12

VCC_SM100

VCC_SM101

VCC_SM102

VCC_SM103

VCC_SM104

VCC_SM105

VCC_SM106

VCC_SM107

AG27
AF27
AG26
AF26
AG25
AF25
AG24
AF24
AG23
AF23
AG22
AF22
AG21
AF21
AG20
AF20
AG19
AF19
R19
AG18
AF18
R18
AG17
AF17
AE17
AD17
AB17
AA17
W17
V17
T17
R17
AG16
AF16
AE16
AD16
AC16
AB16
AA16
Y16
W16
V16
U16
T16
R16
AG15
AF15
AE15
AD15
AC15
AB15
AA15
Y15
W15
V15
U15
T15
R15

AE27
AE26
AE25
AE24
AE23
AE22
AE21
AE20
AE19
AE18
AC17
Y17
U17

AR6
AP6
AN6
AL6
AK6
AJ6
AV1
AJ1

+1.5VS

VCCSM_LF2
VCCSM_LF1

+1.8V

1

1

C398

C390

2

2

0.47U_0603_10V7K

0.47U_0603_10V7K

Place near pin AV1 & AJ1

AA

+VCCP

AA33

AA32

AA31

AA30

AA29

AB28
AA28

AB23
AA23

AC22
AB22

AC21
AA21

AC20
AB20

AB19
AA19

U4G

VCC0

W33

VCC1

P33

VCC2

N33

VCC3

L33

VCC4

J33

VCC5
VCC6

Y32

VCC7

W32

VCC8

V32

VCC9

P32

VCC10

N32

VCC11

M32

VCC12

L32

VCC13

J32

VCC14
VCC15

W31

VCC16

V31

VCC17

T31

VCC18

R31

VCC19

P31

VCC20

N31

VCC21

M31

VCC22
VCC23

Y30

VCC24

W30

VCC25

V30

VCC26

U30

VCC27

T30

VCC28

R30

VCC29

P30

VCC30

N30

VCC31

M30

VCC32

L30

VCC33
VCC34

Y29

VCC35

W29

VCC36

V29

VCC37

U29

VCC38

R29

VCC39

P29

VCC40

M29

VCC41

L29

VCC42
VCC43
VCC44

Y28

VCC45

V28

VCC46

U28

VCC47

T28

VCC48

R28

VCC49

P28

VCC50

N28

VCC51

M28

VCC52

L28

VCC53

P27

VCC54

N27

VCC55

M27

VCC56

L27

VCC57

P26

VCC58

N26

VCC59

L26

VCC60

N25

VCC61

M25

VCC62

L25

VCC63

P24

VCC64

N24

VCC65

M24

VCC66
VCC67
VCC68

Y23

VCC69

P23

VCC70

N23

VCC71

M23

VCC72

L23

VCC73
VCC74
VCC75

Y22

VCC76

W22

VCC77

P22

VCC78

N22

VCC79

M22

VCC80

L22

VCC81
VCC82
VCC83

W21

VCC84

N21

VCC85

M21

VCC86

L21

VCC87
VCC88
VCC89

Y20

VCC90

W20

VCC91

P20

VCC92

N20

VCC93

M20

VCC94

L20

VCC95
VCC96
VCC97

Y19

VCC98

N19

VCC99

CALISTOGA_A2_FCBGA1466

P O W E R

VCC_SM0
VCC_SM1
VCC_SM2
VCC_SM3
VCC_SM4
VCC_SM5
VCC_SM6
VCC_SM7
VCC_SM8

VCC_SM9
VCC_SM10
VCC_SM11
VCC_SM12
VCC_SM13
VCC_SM14
VCC_SM15
VCC_SM16
VCC_SM17
VCC_SM18
VCC_SM19
VCC_SM20
VCC_SM21
VCC_SM22
VCC_SM23
VCC_SM24
VCC_SM25
VCC_SM26
VCC_SM27
VCC_SM28
VCC_SM29
VCC_SM30
VCC_SM31
VCC_SM32
VCC_SM33
VCC_SM34
VCC_SM35
VCC_SM36
VCC_SM37
VCC_SM38
VCC_SM39
VCC_SM40
VCC_SM41
VCC_SM42
VCC_SM43
VCC_SM44
VCC_SM45
VCC_SM46
VCC_SM47
VCC_SM48
VCC_SM49
VCC_SM50
VCC_SM51
VCC_SM52
VCC_SM53
VCC_SM54
VCC_SM55
VCC_SM56
VCC_SM57
VCC_SM58
VCC_SM59
VCC_SM60
VCC_SM61
VCC_SM62
VCC_SM63
VCC_SM64
VCC_SM65
VCC_SM66
VCC_SM67
VCC_SM68
VCC_SM69
VCC_SM70
VCC_SM71
VCC_SM72
VCC_SM73
VCC_SM74
VCC_SM75
VCC_SM76
VCC_SM77
VCC_SM78
VCC_SM79
VCC_SM80
VCC_SM81
VCC_SM82
VCC_SM83
VCC_SM84
VCC_SM85
VCC_SM86
VCC_SM87
VCC_SM88
VCC_SM89
VCC_SM90
VCC_SM91
VCC_SM92
VCC_SM93
VCC_SM94
VCC_SM95
VCC_SM96
VCC_SM97
VCC_SM98
VCC_SM99

AU41
AT41
AM41
AU40
BA34
AY34
AW34
AV34
AU34
AT34
AR34
BA30
AY30
AW30
AV30
AU30
AT30
AR30
AP30
AN30
AM30
AM29
AL29
AK29
AJ29
AH29
AJ28
AH28
AJ27
AH27
BA26
AY26
AW26
AV26
AU26
AT26
AR26
AJ26
AH26
AJ25
AH25
AJ24
AH24
BA23
AJ23
BA22
AY22
AW22
AV22
AU22
AT22
AR22
AP22
AK22
AJ22
AK21
AK20
BA19
AY19
AW19
AV19
AU19
AT19
AR19
AP19
AK19
AJ19
AJ18
AJ17
AH17
AJ16
AH16
BA15
AY15
AW15
AV15
AU15
AT15
AR15
AJ15
AJ14
AJ13
AH13
AK12
AJ12
AH12
AG12
AK11
BA8
AY8
AW8
AV8
AT8
AR8
AP8
BA6
AY6
AW6
AV6
AT6

+1.8V

VCCSM_LF4
VCCSM_LF5

1

C389

2

0.47U_0603_10V7K

Place near pin AT41 & AM41

1

C382

2

0.1U_0402_16V4Z

1

C406

2

0.47U_0603_10V7K

Place near pin BA23

1

C407

2

10U_0805_6.3V6M

10U_0805_6.3V6M

1

C404

2

0.47U_0603_10V7K

Place near pin BA15

C395

C405

1

2

0.47U_0603_10V7K

CFG[13:12]

CFG[2:0]

+1.8V

1

C381

2

0.1U_0402_16V4Z

1

1

C388

C384

2

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

SDVO_CTRLDATA

(PCIE/SDVO select)

1

1

+

C402

220U_D2_4VM@

2

2

@wait DB-1 test verify

L

CFG[19:18] have internal pull down

011 = 667MT/s FSB
001 = 533MT/s FSB

CFG5

CFG7

CFG9

CFG11

CFG16

CFG18

CFG19

0 = DMI x 2
1 = DMI x 4

0 = Reserved
1 = Mobile Yonah CPU

0 = Lane Reversal Enable
1 = Normal Operation

1 = Calistoga

(According to Intel Napa Schematic Checklist & CRB
Rev1.502 document 2.2Kohm pull-down resistor no request)

0 = Reserved

00 = Reserved
01 = XOR Mode Enabled
10 = All Z Mode Enabled
11 = Normal Operation

0 = Dynamic ODT Disabled
1 = Dynamic ODT Enabled(Default)

0 = 1.05V
1 = 1.5V

0 = Normal Operation
1 = DMI Lane Reversal Enable

0 = No SDVO Device Present

(Default)

1 = SDVO Device Present

CFG20

0 = Only PCIE or SDVO is
operational.
1 = PCIE/SDVO are operating
simu.

R3492.2K_0402_5%@

CFG57

R3402.2K_0402_5%@

CFG77

R3542.2K_0402_5%@

CFG97
CFG117
CFG127
CFG137
CFG167

CFG187
CFG197
CFG207

R3412.2K_0402_5%@
R3652.2K_0402_5%@
R3712.2K_0402_5%@
R3592.2K_0402_5%@

R3701K_0402_5%@
R3681K_0402_5%@
R3691K_0402_5%@

(Default)

*

*

(Default)

*

*

1 2
1 2
1 2
1 2
1 2
1 2
1 2

1 2
1 2
1 2

(Default)

*

(Default)

*

(Default)

*

(Default)

*

*

(Default)

*

+3VS

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2005/03/102006/03/10

Compal Secret Data

Deciphered Date

2

Title

SizeDocument NumberRev

Date:Sheet of

Compal Electronics, Inc.

Calistoga (5/6)

LA-2821P

1152Friday, November 25, 2005

1

0.5

5 4 3 2

1

U4I

AC41

VSS0

AA41

VSS1

W41

VSS2

T41

VSS3

P41

VSS4

M41

DD

CC

BB

AA

VSS5

J41

VSS6

F41

VSS7

AV40

VSS8

AP40

VSS9

AN40

VSS10

AK40

VSS11

AJ40

VSS12

AH40

VSS13

AG40

VSS14

AF40

VSS15

AE40

VSS16

B40

VSS17

AY39

VSS18

AW39

VSS19

AV39

VSS20

AR39

VSS21

AN39

VSS22

AJ39

VSS23

AC39

VSS24

AB39

VSS25

AA39

VSS26

Y39

VSS27

W39

VSS28

V39

VSS29

T39

VSS30

R39

VSS31

P39

VSS32

N39

VSS33

M39

VSS34

L39

VSS35

J39

VSS36

H39

VSS37

G39

VSS38

F39

VSS39

D39

VSS40

AT38

VSS41

AM38

VSS42

AH38

VSS43

AG38

VSS44

AF38

VSS45

AE38

VSS46

C38

VSS47

AK37

VSS48

AH37

VSS49

AB37

VSS50

AA37

VSS51

Y37

VSS52

W37

VSS53

V37

VSS54

T37

VSS55

R37

VSS56

P37

VSS57

N37

VSS58

M37

VSS59

L37

VSS60

J37

VSS61

H37

VSS62

G37

VSS63

F37

VSS64

D37

VSS65

AY36

VSS66

AW36

VSS67

AN36

VSS68

AH36

VSS69

AG36

VSS70

AF36

VSS71

AE36

VSS72

AC36

VSS73

C36

VSS74

B36

VSS75

BA35

VSS76

AV35

VSS77

AR35

VSS78

AH35

VSS79

AB35

VSS80

AA35

VSS81

Y35

VSS82

W35

VSS83

V35

VSS84

T35

VSS85

R35

VSS86

P35

VSS87

N35

VSS88

M35

VSS89

L35

VSS90

J35

VSS91

H35

VSS92

G35

VSS93

F35

VSS94

D35

VSS95

AN34

VSS96

AK34

VSS97

AG34

VSS98

AF34

VSS99

CALISTOGA_A2_FCBGA1466

P O W E R

VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS140
VSS141
VSS142
VSS143
VSS144
VSS145
VSS146
VSS147
VSS148
VSS149
VSS150
VSS151
VSS152
VSS153
VSS154
VSS155
VSS156
VSS157
VSS158
VSS159
VSS160
VSS161
VSS162
VSS163
VSS164
VSS165
VSS166
VSS167
VSS168
VSS169
VSS170
VSS171
VSS172
VSS173
VSS174
VSS175
VSS176
VSS177
VSS178
VSS179
VSS180
VSS181
VSS182
VSS183
VSS184
VSS185
VSS186
VSS187
VSS188
VSS189
VSS190
VSS191
VSS192
VSS193
VSS194
VSS195
VSS196
VSS197
VSS198
VSS199

AE34
AC34
C34
AW33
AV33
AR33
AE33
AB33
Y33
V33
T33
R33
M33
H33
G33
F33
D33
B33
AH32
AG32
AF32
AE32
AC32
AB32
G32
B32
AY31
AV31
AN31
AJ31
AG31
AB31
Y31
AB30
E30
AT29
AN29
AB29
T29
N29
K29
G29
E29
C29
B29
A29
BA28
AW28
AU28
AP28
AM28
AD28
AC28
W28
J28
E28
AP27
AM27
AK27
J27
G27
F27
C27
B27
AN26
M26
K26
F26
D26
AK25
P25
K25
H25
E25
D25
A25
BA24
AU24
AL24
AW23
AT23
AN23
AM23
AH23
AC23
W23
K23
J23
F23
C23
AA22
K22
G22
F22
E22
D22
A22
BA21
AV21
AR21

U4J

AN21

VSS200

AL21

VSS201

AB21

VSS202

Y21

VSS203

P21

VSS204

K21

VSS205

J21

VSS206

H21

VSS207

C21

VSS208

AW20

VSS209

AR20

VSS210

AM20

VSS211

AA20

VSS212

K20

VSS213

B20

VSS214

A20

VSS215

AN19

VSS216

AC19

VSS217

W19

VSS218

K19

VSS219

G19

VSS220

C19

VSS221

AH18

VSS222

P18

VSS223

H18

VSS224

D18

VSS225

A18

VSS226

AY17

VSS227

AR17

VSS228

AP17

VSS229

AM17

VSS230

AK17

VSS231

AV16

VSS232

AN16

VSS233

AL16

VSS234

J16

VSS235

F16

VSS236

C16

VSS237

AN15

VSS238

AM15

VSS239

AK15

VSS240

N15

VSS241

M15

VSS242

L15

VSS243

B15

VSS244

A15

VSS245

BA14

VSS246

AT14

VSS247

AK14

VSS248

AD14

VSS249

AA14

VSS250

U14

VSS251

K14

VSS252

H14

VSS253

E14

VSS254

AV13

VSS255

AR13

VSS256

AN13

VSS257

AM13

VSS258

AL13

VSS259

AG13

VSS260

P13

VSS261

F13

VSS262

D13

VSS265

B13

VSS264

AY12

VSS263

AC12

VSS266

K12

VSS267

H12

VSS268

E12

VSS269

AD11

VSS270

AA11

VSS271

Y11

VSS272

J11

VSS273

D11

VSS274

B11

VSS275

AV10

VSS276

AP10

VSS277

AL10

VSS278

AJ10

VSS279

CALISTOGA_A2_FCBGA1466

P O W E R

VSS280
VSS281
VSS282
VSS283
VSS284
VSS285
VSS286
VSS287
VSS288
VSS289
VSS290
VSS292
VSS291
VSS293
VSS294
VSS295
VSS296
VSS297
VSS298
VSS299
VSS300
VSS301
VSS302
VSS303
VSS304
VSS305
VSS306
VSS307
VSS308
VSS309
VSS310
VSS311
VSS312
VSS313
VSS314
VSS315
VSS316
VSS317
VSS318
VSS319
VSS320
VSS321
VSS322
VSS323
VSS324
VSS325
VSS326
VSS327
VSS328
VSS329
VSS330
VSS331
VSS332
VSS333
VSS334
VSS335
VSS336
VSS337
VSS338
VSS339
VSS340
VSS341
VSS342
VSS343
VSS344
VSS345
VSS346
VSS347
VSS348
VSS349
VSS350
VSS351
VSS352
VSS353
VSS354
VSS355
VSS356
VSS357
VSS358
VSS359
VSS360

AG10
AC10
W10
U10
BA9
AW9
AR9
AH9
AB9
Y9
R9
G9
E9
A9
AG8
AD8
AA8
U8
K8
C8
BA7
AV7
AP7
AL7
AJ7
AH7
AF7
AC7
R7
G7
D7
AG6
AD6
AB6
Y6
U6
N6
K6
H6
B6
AV5
AF5
AD5
AY4
AR4
AP4
AL4
AJ4
Y4
U4
R4
J4
F4
C4
AY3
AW3
AV3
AL3
AH3
AG3
AF3
AD3
AC3
AA3
G3
AT2
AR2
AP2
AK2
AJ2
AD2
AB2
Y2
U2
T2
N2
J2
H2
F2
C2
AL1

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2005/03/102006/03/10

Compal Secret Data

Deciphered Date

2

Title

SizeDocument NumberRev

Date:Sheet of

Compal Electronics, Inc.

Calistoga (6/6)

LA-2821P

1252Friday, November 25, 2005

1

0.5

5

DDR_A_DQS#[0..7]8

DDR_A_D[0..63]8

DDR_A_DM[0..7]8
DDR_A_DQS[0..7]8
DDR_A_MA[0..13]8

DD

Layout Note:
Place near JP34

+1.8V

2.2U_0805_16V4Z

2.2U_0805_16V4Z

1

2

CC

Layout Note:
Place one cap close to every 2 pullup
resistors terminated to +0.9V

+0.9V

0.1U_0402_16V4Z

1

2

C83

BB

AA

DDR_A_MA5
DDR_A_MA8

DDR_A_MA1
DDR_A_MA3

DDR_A_RAS#
DDR_CS0_DIMMA#

DDR_A_BS#0
DDR_A_MA10

DDR_A_CAS#
DDR_A_WE#

DDR_CS1_DIMMA#
M_ODT1

2.2U_0805_16V4Z

2.2U_0805_16V4Z

C467

0.1U_0402_16V4Z

1

2

5

1

2

C79

RP11

RP7

RP15

RP10

RP9

RP8

C461

0.1U_0402_16V4Z

1 4
2 3

1 4
2 3

1 4
2 3

1 4
2 3

1 4
2 3

2 3
1 4

C463

1

2

0.1U_0402_16V4Z

1

2

C78

56_0404_4P2R_5%

56_0404_4P2R_5%

56_0404_4P2R_5%

56_0404_4P2R_5%

56_0404_4P2R_5%

56_0404_4P2R_5%

1

2

0.1U_0402_16V4Z

1

1

2

2

C80

+0.9V

0.1U_0402_16V4Z

2.2U_0805_16V4Z

C462

C464

1

1

2

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

2

2

C84

C82

C81

RP1356_0404_4P2R_5%

DDR_A_BS#2

14

DDR_CKE0_DIMMA

23

RP1856_0404_4P2R_5%

DDR_A_MA7

14

DDR_A_MA6

23

RP1256_0404_4P2R_5%

DDR_A_MA9

14

DDR_A_MA12

23

RP1756_0404_4P2R_5%

DDR_A_MA4

14

DDR_A_MA2

23

RP1656_0404_4P2R_5%

DDR_A_MA0

14

DDR_A_BS#1

23

RP1456_0404_4P2R_5%

M_ODT0

14

DDR_A_MA13

23

RP1956_0404_4P2R_5%

DDR_CKE1_DIMMA

14

DDR_A_MA11

23

0.1U_0402_16V4Z

C105

1

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

2

C115

4

0.1U_0402_16V4Z

0.1U_0402_16V4Z

C91

1

1

2

2

0.1U_0402_16V4Z

1

1

2

2

C110

Layout Note:
Place these resistor
closely JP34,all
trace length Max=1.5"

C95

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

2

2

C113

C112

C114

C93

0.1U_0402_16V4Z

1

2

C111

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

DDR_CKE0_DIMMA7

DDR_CS1_DIMMA#7

Issued Date

3

+1.8V

JP9

1

VREF

3

DDR_A_D0
DDR_A_D4

DDR_A_DQS#0
DDR_A_DQS0

DDR_A_D2
DDR_A_D3

DDR_A_D8
DDR_A_D14

DDR_A_DQS#1
DDR_A_DQS1

DDR_A_D10
DDR_A_D11

DDR_A_D21
DDR_A_D17

DDR_A_DQS#2
DDR_A_DQS2

DDR_A_D22
DDR_A_D19 DDR_A_D23

DDR_A_D25
DDR_A_D24

DDR_A_DM3

DDR_A_D27
DDR_A_D30

DDR_CKE0_DIMMA

DDR_A_BS#28

DDR_A_BS#08

DDR_A_WE#8

DDR_A_CAS#8

M_ODT17

ICH_SMBDATA4,14,15,18,21,25,27

ICH_SMBCLK4,14,15,18,21,25,27

DDR_A_BS#2
DDR_A_MA12

DDR_A_MA9 DDR_A_MA7
DDR_A_MA8

DDR_A_MA5
DDR_A_MA3
DDR_A_MA1

DDR_A_MA10
DDR_A_BS#0
DDR_A_WE#

DDR_A_CAS#
DDR_CS1_DIMMA#

M_ODT1
DDR_A_D34

DDR_A_D38
DDR_A_DQS#4

DDR_A_DQS4
DDR_A_D39

DDR_A_D35
DDR_A_D45

DDR_A_D41
DDR_A_DM5
DDR_A_D42

DDR_A_D43
DDR_A_D52

DDR_A_D53

DDR_A_DQS#6
DDR_A_DQS6

DDR_A_D55
DDR_A_D56

DDR_A_D61
DDR_A_DM7
DDR_A_D58

DDR_A_D59
ICH_SMBDATA

ICH_SMBCLK

+3VS

1

C96

0.1U_0402_16V4Z

2

VSS

5

DQ0

7

DQ1

9

VSS

11

DQS0#

13

DQS0

15

VSS

17

DQ2

19

DQ3

21

VSS

23

DQ8

25

DQ9

27

VSS

29

DQS1#

31

DQS1

33

VSS

35

DQ10

37

DQ11

39

VSS

41

VSS

43

DQ16

45

DQ17

47

VSS

49

DQS2#

51

DQS2

53

VSS

55

DQ18

57

DQ19

59

VSS

61

DQ24

63

DQ25

65

VSS

67

DM3

69

NC

71

VSS

73

DQ26

75

DQ27

77

VSS

79

CKE0

81

VDD

83

NC

85

BA2

87

VDD

89

A12

91

A9

93

A8

95

VDD

97

A5

99

A3

101

A1

103

VDD

105

A10/AP

107

BA0

109

WE#

111

VDD

113

CAS#

115

NC/S1#

117

VDD

119

NC/ODT1

121

VSS

123

DQ32

125

DQ33

127

VSS

129

DQS4#

131

DQS4

133

VSS

135

DQ34

137

DQ35

139

VSS

141

DQ40

143

DQ41

145

VSS

147

DM5

149

VSS

151

DQ42

153

DQ43

155

VSS

157

DQ48

159

DQ49

161

VSS

163

NC,TEST

165

VSS

167

DQS6#

169

DQS6

171

VSS

173

DQ50

175

DQ51

177

VSS

179

DQ56

181

DQ57

183

VSS

185

DM7

187

VSS

189

DQ58

191

DQ59

193

VSS

195

SDA

197

SCL

199

VDDSPD

FOX_ASOA426-M4R-TR

SO-DIMM A

REVERSE

DQ4
DQ5

DM0
DQ6

DQ7

DQ12
DQ13

DM1

CK0#

DQ14
DQ15

DQ20
DQ21

DM2

DQ22
DQ23

DQ28
DQ29

DQS3#

DQS3
DQ30

DQ31

NC/CKE1

VDD
NC/A15
NC/A14

VDD

VDD

VDD

RAS#

VDD

ODT0

NC/A13

VDD

DQ36
DQ37

DM4

DQ38
DQ39

DQ44
DQ45

DQS5#

DQS5
DQ46

DQ47
DQ52

DQ53

CK1#

DM6

DQ54
DQ55

DQ60
DQ61

DQS7#

DQS7
DQ62

DQ63

SAO

2

+1.8V

V_DDR_MCH_REF

2

VSS

VSS
VSS

VSS

VSS
VSS

CK0
VSS

VSS

VSS

VSS

NC

VSS

VSS

VSS

VSS

VSS

A11

A7
A6

A4
A2

A0
BA1
S0#

NC

VSS

VSS
VSS

VSS

VSS

VSS

VSS

VSS
CK1

VSS
VSS

VSS

VSS

VSS

VSS
SA1

DDR_A_D7

4

DDR_A_D1

6
8

DDR_A_DM0

10
12

DDR_A_D5

14

DDR_A_D6

16
18

DDR_A_D12

20

DDR_A_D13

22
24

DDR_A_DM1

26
28

M_CLK_DDR0

30

M_CLK_DDR#0

32
34

DDR_A_D9

36

DDR_A_D15

38
40

42

DDR_A_D20

44

DDR_A_D16

46
48

DDR_THERM#

50

DDR_A_DM2

52
54

DDR_A_D18

56
58
60

DDR_A_D29

62

DDR_A_D28

64
66

DDR_A_DQS#3

68

DDR_A_DQS3

70
72

DDR_A_D26

74

DDR_A_D31

76
78

DDR_CKE1_DIMMA

80
82
84
86
88

DDR_A_MA11

90
92

DDR_A_MA6

94
96

DDR_A_MA4

98

DDR_A_MA2

100

DDR_A_MA0

102
104

DDR_A_BS#1

106

DDR_A_RAS#

108

DDR_CS0_DIMMA#

110
112

M_ODT0

114

DDR_A_MA13

116
118
120
122

DDR_A_D36

124

DDR_A_D33

126
128

DDR_A_DM4

130
132

DDR_A_D37

134

DDR_A_D32

136
138

DDR_A_D40

140

DDR_A_D44

142
144

DDR_A_DQS#5

146

DDR_A_DQS5

148
150

DDR_A_D47

152

DDR_A_D46

154
156

DDR_A_D48

158

DDR_A_D49

160
162

M_CLK_DDR1

164

M_CLK_DDR#1

166
168

DDR_A_DM6

170
172

DDR_A_D50DDR_A_D51

174

DDR_A_D54

176
178

DDR_A_D60

180

DDR_A_D57

182
184

DDR_A_DQS#7

186

DDR_A_DQS7

188
190

DDR_A_D62

192

DDR_A_D63

194
196
198
200

12

12

R40

R38

10K_0402_5%

10K_0402_5%

2.2U_0805_16V4Z
C97

1

2

M_CLK_DDR07
M_CLK_DDR#07

DDR_THERM#7,14

DDR_CKE1_DIMMA7

DDR_A_BS#18
DDR_A_RAS#8
DDR_CS0_DIMMA#7

M_ODT07

M_CLK_DDR17
M_CLK_DDR#17

1

0.1U_0402_16V4Z

1

2

V_DDR_MCH_REF7,14,44

C92

Top side

2005/03/102006/03/10

3

Compal Secret Data

Deciphered Date

2

Title

SizeDocument NumberRev

Date:Sheet of

Compal Electronics, Inc.

DDRII-SODIMM SLOT1

LA-2821P

1352Friday, November 25, 2005

1

0.5

5

DDR_B_DQS#[0..7]8

DDR_B_D[0..63]8

DDR_B_DM[0..7]8
DDR_B_DQS[0..7]8
DDR_B_MA[0..13]8

DD

CC

BB

AA

Layout Note:
Place near JP34

+1.8V

2.2U_0805_16V4Z

1

2

Layout Note:
Place one cap close to every 2 pullup
resistors terminated to +0.9V

+0.9V

0.1U_0402_16V4Z

1

2

C85

DDR_B_MA1
DDR_B_MA3

DDR_B_BS#0
DDR_B_MA10

DDR_B_MA0
DDR_B_BS#1

DDR_B_RAS#
DDR_CS2_DIMMB#

DDR_B_CAS#
DDR_B_WE#

DDR_CS3_DIMMB# M_ODT2
M_ODT3

2.2U_0805_16V4Z

2.2U_0805_16V4Z

2.2U_0805_16V4Z

C109

C108

1

1

2

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

2

2

C86

C87

RP34

1 4
2 3

RP35

56_0404_4P2R_5%

1 4
2 3

RP3

56_0404_4P2R_5%

1 4
2 3

RP2

56_0404_4P2R_5%

1 4
2 3

56_0404_4P2R_5%

RP36

1 4
2 3

RP37

56_0404_4P2R_5%

2 3
1 4

56_0404_4P2R_5%

5

C460

0.1U_0402_16V4Z

1

2

C88

+0.9V

2.2U_0805_16V4Z

C466

C107

1

1

2

2

0.1U_0402_16V4Z

1

1

2

2

C89

C90

RP3256_0404_4P2R_5%

14
23

RP656_0404_4P2R_5%

14
23

RP3356_0404_4P2R_5%

14
23

RP556_0404_4P2R_5%

14
23

RP456_0404_4P2R_5%

14
23

RP156_0404_4P2R_5%

14
23

RP31

14
23

56_0404_4P2R_5%

0.1U_0402_16V4Z
C94

1

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

2

C477

DDR_B_MA9
DDR_B_MA12

DDR_B_MA7
DDR_CKE3_DIMMB

DDR_B_MA5
DDR_B_MA8

DDR_B_MA6
DDR_B_MA11

DDR_B_MA4
DDR_B_MA2

DDR_B_MA13

DDR_B_BS#2
DDR_CKE2_DIMMB

0.1U_0402_16V4Z

0.1U_0402_16V4Z
C455

1

2

0.1U_0402_16V4Z

1

1

2

2

C476

C475

5/16

5/16

0.1U_0402_16V4Z

C106

1

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

2

C474

Layout Note:
Place these resistor
closely JP10,all
trace length Max=1.5"

4

C454

1

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

2

C473

1

1

2

2

C471

C472

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

DDR_CKE2_DIMMB7

DDR_CS3_DIMMB#7

Issued Date

3

+1.8V

JP29

1

VREF

3

DDR_B_D0
DDR_B_D5

DDR_B_DQS#0
DDR_B_DQS0

DDR_B_D7
DDR_B_D3

DDR_B_D8
DDR_B_D9

DDR_B_DQS#1
DDR_B_DQS1

DDR_B_D10
DDR_B_D11

DDR_B_D20
DDR_B_DQS#2

DDR_B_DQS2
DDR_B_D22

DDR_B_D23
DDR_B_D24

DDR_B_D25
DDR_B_DM3

DDR_B_D30
DDR_B_D31

DDR_CKE2_DIMMB

DDR_B_BS#28

DDR_B_BS#08
DDR_B_WE#8

DDR_B_CAS#8

M_ODT37

ICH_SMBDATA4,13,15,18,21,25,27

ICH_SMBCLK4,13,15,18,21,25,27

3

DDR_B_BS#2
DDR_B_MA12

DDR_B_MA9
DDR_B_MA8

DDR_B_MA5
DDR_B_MA3
DDR_B_MA1

DDR_B_MA10
DDR_B_BS#0
DDR_B_WE#

DDR_B_CAS#
DDR_CS3_DIMMB#

M_ODT3
DDR_B_D37

DDR_B_D36
DDR_B_DQS#4

DDR_B_DQS4
DDR_B_D35

DDR_B_D34
DDR_B_D40

DDR_B_D41
DDR_B_DM5
DDR_B_D42

DDR_B_D47
DDR_B_D48

DDR_B_D53

DDR_B_DQS#6
DDR_B_DQS6

DDR_B_D51
DDR_B_D50

DDR_B_D60
DDR_B_D61

DDR_B_DM7
DDR_B_D58

DDR_B_D59
ICH_SMBDATA

ICH_SMBCLK

+3VS

1

C453

0.1U_0402_16V4Z

2005/03/102006/03/10

2

Compal Secret Data

VSS

5

DQ0

7

DQ1

9

VSS

11

DQS0#

13

DQS0

15

VSS

17

DQ2

19

DQ3

21

VSS

23

DQ8

25

DQ9

27

VSS

29

DQS1#

31

DQS1

33

VSS

35

DQ10

37

DQ11

39

VSS

41

VSS

43

DQ16

45

DQ17

47

VSS

49

DQS2#

51

DQS2

53

VSS

55

DQ18

57

DQ19

59

VSS

61

DQ24

63

DQ25

65

VSS

67

DM3

69

NC

71

VSS

73

DQ26

75

DQ27

77

VSS

79

CKE0

81

VDD

83

NC

85

BA2

87

VDD

89

A12

91

A9

93

A8

95

VDD

97

A5

99

A3

101

A1

103

VDD

105

A10/AP

107

BA0

109

WE#

111

VDD

113

CAS#

115

NC/S1#

117

VDD

119

NC/ODT1

121

VSS

123

DQ32

125

DQ33

127

VSS

129

DQS4#

131

DQS4

133

VSS

135

DQ34

137

DQ35

139

VSS

141

DQ40

143

DQ41

145

VSS

147

DM5

149

VSS

151

DQ42

153

DQ43

155

VSS

157

DQ48

159

DQ49

161

VSS

163

NC,TEST

165

VSS

167

DQS6#

169

DQS6

171

VSS

173

DQ50

175

DQ51

177

VSS

179

DQ56

181

DQ57

183

VSS

185

DM7

187

VSS

189

DQ58

191

DQ59

193

VSS

195

SDA

197

SCL

199

VDDSPD

FOX_ASOA426-M2RN-7F

SO-DIMM B
STANDARD

Bottom side

Deciphered Date

DM0

DQ12
DQ13

DM1

CK0#

DQ14
DQ15

DQ20
DQ21

DM2

DQ22
DQ23

DQ28
DQ29

DQS3#

DQS3
DQ30

DQ31

NC/CKE1

NC/A15
NC/A14

RAS#

ODT0

NC/A13

DQ36
DQ37

DM4

DQ38
DQ39

DQ44
DQ45

DQS5#

DQS5
DQ46

DQ47
DQ52

DQ53

CK1#

DM6

DQ54
DQ55

DQ60
DQ61

DQS7#

DQS7
DQ62

DQ63

VSS
DQ4
DQ5
VSS

VSS
DQ6
DQ7
VSS

VSS
VSS

CK0
VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS
VDD

VDD

VDD

VDD
BA1

VDD

VDD
VSS

VSS
VSS

VSS

VSS

VSS

VSS

VSS
CK1

VSS
VSS

VSS

VSS

VSS

VSS
SA0
SA1

2

+1.8V

V_DDR_MCH_REF

2

DDR_B_D4

4

DDR_B_D1

6
8

DDR_B_DM0

10
12

DDR_B_D6

14

DDR_B_D2

16
18

DDR_B_D12

20

DDR_B_D13

22
24

DDR_B_DM1

26
28

M_CLK_DDR3

30

M_CLK_DDR#3

32
34

DDR_B_D14

36

DDR_B_D15

38
40

42

DDR_B_D16DDR_B_D21

44

DDR_B_D18

46
48

DDR_THERM#

50

NC

A11

A7
A6

A4
A2
A0

S0#

NC

2

DDR_B_DM2

52
54

DDR_B_D17

56

DDR_B_D19

58
60

DDR_B_D26

62

DDR_B_D28

64
66

DDR_B_DQS#3

68

DDR_B_DQS3

70
72

DDR_B_D29

74

DDR_B_D27

76
78

DDR_CKE3_DIMMB

80
82
84
86
88

DDR_B_MA11

90

DDR_B_MA7

92

DDR_B_MA6

94
96

DDR_B_MA4

98

DDR_B_MA2

100

DDR_B_MA0

102
104

DDR_B_BS#1

106

DDR_B_RAS#

108

DDR_CS2_DIMMB#

110
112

M_ODT2

114

DDR_B_MA13

116
118
120
122

DDR_B_D33

124

DDR_B_D32

126
128

DDR_B_DM4

130
132

DDR_B_D38

134

DDR_B_D39

136
138

DDR_B_D44

140

DDR_B_D45

142
144

DDR_B_DQS#5

146

DDR_B_DQS5

148
150

DDR_B_D43

152

DDR_B_D46

154
156

DDR_B_D49

158

DDR_B_D52

160
162

M_CLK_DDR2

164

M_CLK_DDR#2

166
168

DDR_B_DM6

170
172

DDR_B_D54

174

DDR_B_D55

176
178

DDR_B_D56

180

DDR_B_D57

182
184

DDR_B_DQS#7

186

DDR_B_DQS7

188
190

DDR_B_D62

192

DDR_B_D63

194
196
198
200

10K_0402_5%

12

2.2U_0805_16V4Z

0.1U_0402_16V4Z

1

C99

2

M_CLK_DDR37
M_CLK_DDR#37

DDR_THERM#7,13

DDR_CKE3_DIMMB7

DDR_B_BS#18
DDR_B_RAS#8
DDR_CS2_DIMMB#7

M_ODT27

M_CLK_DDR27
M_CLK_DDR#27

R33

1 2

10K_0402_5%

R34

Title

SizeDocument NumberRev

Date:Sheet of

+3VS

Compal Electronics, Inc.

DDRII-SODIMM SLOT2

LA-2821P

V_DDR_MCH_REF7,13,44

1

C103

2

1

1452Friday, November 25, 2005

1

0.5

5 4 3 2

PCI

SRC

CPU

FSLC1FSLB

CLKSEL2

0

Table : ICS954306

DD

FSB Frequency Selet:

CPU Driven

(Default)

*

533MHz

667MHz

CC

CPU_BSEL05

CPU_BSEL15

BB

CPU_BSEL25

AA

FSLA

CLKSEL1

0

1

Stuff

No Stuff

Stuff

No Stuff

Stuff

No Stuff

CLKSEL0

MHz

133

166

CLK_Ra

CLK_Rd

CLK_Rd

CLK_Ra

CLK_Rd

CLK_Ra

MHz

1000

100

CLK_Rb

CLK_Re

CLK_Re

CLK_Rb

CLK_Rf

CLK_Rb

MHz

33.31

33.3

CLK_Rc

CLK_Rf

CLK_Rf

CLK_Rc

CLK_Rc

CLK_Re

+VCCP

R560

@

12

FSB

12

R537

10K_0402_5%@

R549

300_0402_5%

J14

+VCCP

+VCCP

+3VS

56_0402_5%

CLK_Rd

1 2

1 2

R576

1K_0402_5%

12

R561
1K_0402_5%

R566
1K_0402_5%

1 2

1 2

R564

1K_0402_5%

12

R539

@

0_0402_5%

CLK_Re

R490
1K_0402_5%

1 2

1 2

R491

1K_0402_5%

12

R493

@

0_0402_5%

CLK_Rf

12

12

2 1

R550

8.2K_0402_5%

FSA CLK_48M_CB

1 2

R575

0_0402_5%

CLK_Ra

1 2

R565

0_0402_5%

CLK_Rb

R494

8.2K_0402_5%

CLKREF1

1 2

R492

0_0402_5%

CLK_Rc

CLK_ENABLE#

PAD-No SHORT 2x2m@

0.1U_0402_16V4ZDP@

MCH_CLKSEL07 CLK_48M_CB24

MCH_CLKSEL17

MCH_CLKSEL27

NOXDP@ : means just build when XDP function disable.
XDP@ : means just build when XDP function enable.

When this time, docking PCI express will not work.

LCD(Low)/SRC(High)
clock select

+3VS +3VS

High:Pin18/19 = 100MHz

*

Low:Pin18/19 = 96MHzLow:Pin44/45 = CPUCLK2_ITP

+3VS

R5020_0805_5%

+3VS

R4530_0805_5%

+3VS

+VCCP

+CK_VDD_DP

R474
0_0402_5%DP@

1

C447

2

CLK_48M_ICH21

CLK_14M_ICH21

H_STP_CPU#21

H_STP_PCI#21

CLK_ENABLE#37,45

CLK_PCI_ICH19

CLK_14M_KBC33

CLK_14M_SIO31

CLK_PCI_EC33
CLK_PCI_TCG32
CLK_PCI_PCM23

ICH_SMBDATA4,13,14,18,21,25,27

ICH_SMBCLK4,13,14,18,21,25,27

CLK_PCI_SIO31
CLK_PCI_DB27

12

R535
10K_0402_5%

PCI_ICH PCI_MINI

12

R536

10K_0402_5%@

+CK_VDD_MAIN1

1 2

1 2

R506

1 2

0_0805_5%NODP@

R508

1 2

0_0805_5%DP@

0.1U_0402_16V4Z

CLKIREF

12

0.1U_0402_16V4Z

+3VS

R51812_0402_5%
R53112_0402_5%DB@

1

C452
10U_0805_10V4Z

2

+CK_VDD_MAIN2

1

C496
10U_0805_10V4Z

2

+CK_VDD_DP

1

C457
10U_0805_10V4Z

2

+CK_VDD_DP

1

C469

2
1

C448

2

CLK_48M_ICH

CLK_14M_ICH

H_STP_CPU#
H_STP_PCI#

CLK_ENABLE#
CLK_PCI_ICH PCI_ICH

CLK_14M_KBC
CLK_14M_SIO

ICH_SMBDATA
ICH_SMBCLK

R53812_0402_5%

R55112_0402_5%

33_0402_5%

1 2

R49612_0402_5%

R49812_0402_5%

12
12

33_0402_5%

Pin44/45 function select

12

R501

10K_0402_5%NOXDP@

12

R504

10K_0402_5%XDP@

High:Pin44/45 = CLKREQ

*

CK_VDD_48

CK_VDD_REF

R489

12

R4724.7K_0402_1%LPNO@

R534

R51310K_0402_5%

12

R53210K_0402_5%@

12

R52833_0402_5%

12

R51933_0402_5%

12

R53333_0402_5%

12

1

C451
.01U_0402_16V7K

2

1

C430

0.1U_0402_16V4Z

2

1

C470

0.1U_0402_16V4Z

2

+CK_VDD_MAIN1

12

FSA

12

FSB
CLKREF1

CLKIREF

12

CLKREF0

12
12

PCI_MINI
PCI_CLK3

PCI_EC
PCI_CLK5
PCI_PCM

PCI_CLK3

1

C449
.01U_0402_16V7K

2

1

C495

0.1U_0402_16V4Z

2

1

C465

0.1U_0402_16V4Z

2

U30

16

VDD

10

VDD48

5

VDDPCI

24

VDDSRC

33

VDDSATA

41

VDDSRC

50

VDDCPU

55

VDDREF

11

FSLA/USB_48MHz

15

FSLB/TEST_MODE

59

FSLC/TEST_SEL/REF1

46

IREF

61

CPU_STOP#

8

PCI/SRC_STOP#

9

Vtt_PwrGd#/PD

7

**SEL_LCDCLK#/PCICLK_F1

60

REF0/PCICLK1

62

*REQ_SEL/PCICLK2

1

*SEL_PCI1/PCICLK3

2

**SEL_SATA1/PCICLK4

3

**SEL_SATA2/PCICLK5

6

PCICLK6

54

SDATA

53

SCLK

13

DOTT_96MHz

14

DOTC_96MHz

4

GND

12

GND

17

GND

58

GND

47

GNDCPU

25

GNDSRC

40

GNDSRC

32

GNDSATA

ICS954306BGLFT_TSSOP64

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

1

C468
.01U_0402_16V7K

2

R454

1 2

1_0805_1%

1 2

R548

2.2_0805_1%

1

C450

0.1U_0402_16V4Z

2

SATACLKT
SATACLKC

CPUCLKT0
CPUCLKC0

CPUCLKT1
CPUCLKC1

*CLKREQA#

LCDCLK_SST/SRCCLKT0

LCDCLK_SSC/SRCCLKC0

SRCCLKT2
SRCCLKC2

SATA1/SRCCLKT4
SATA1/SRCCLKC4

*CLKREQB#

SRCCLKT1
SRCCLKC1

SRCCLKT3
SRCCLKC3

SATA2/SRCCLKT5
SATA2/SRCCLKC5

*CPUCLKT2_ITP/CLKREQC#

*CPUCLKC2_ITP/CLKREQD#

* Internal Pull-Up Resistor
** Internal Pull-Down Resistor

SRCCLKT6
SRCCLKC6

SRCCLKT8
SRCCLKC8

SRCCLKT7
SRCCLKC7

2005/03/102006/03/10

CK_VDD_REF

CK_VDD_48

X1
X2

Place crystal within
500 mils of CK410

C43927P_0402_50V8J

12

12

Y6

CLK_XTAL_IN

57

CLK_XTAL_OUT

56

28
29

52
51

49
48

64
18
19

22
23

30
31

63
20
21

26
27

35
34

45
37
36

43
42

44
39
38

Routing the trace at least 10mil

L

R5270_0402_5%
R5170_0402_5%

Routing the trace at least 10mil

L

CPU_BCLK
CPU_BCLK#

MCH_BCLK
MCH_BCLK#

PCIE_MXM
PCIE_MXM#

11/14

PCIE_LOM
PCIE_LOM#

PCIE_SATA
PCIE_SATA# CLK_PCIE_SATA#

11/14

PCIE_DOCK CLK_PCIE_DOCK

R4790_0402_5%NOXDP@

CPU_XDP
MCH_3GPLL
MCH_3GPLL#

R4550_0402_5%NOXDP@

CPU_XDP#
PCIE_MCARD
PCIE_MCARD#

14.31818MHZ_20P_6X1430004201

C44027P_0402_50V8J

12

1 2
1 2

1 2

R47524_0402_5%

1 2

R47624_0402_5%

1 2

R47724_0402_5%

1 2

R47824_0402_5%

11/21

R51010K_0402_5%@

1 2

R55224_0402_5%

1 2

R55324_0402_5%

1 2

R54024_0402_5%

1 2

R54124_0402_5%

1 2

R55824_0402_5%

1 2

R55924_0402_5%

R50710K_0402_5%

1 2

R54224_0402_5%

1 2

R54324_0402_5%

1 2

R48624_0402_5%

1 2

R48724_0402_5%

1 2

R48033_0402_5%XDP@

1 2

R48424_0402_5%

1 2

R48524_0402_5%

1 2

R48133_0402_5%XDP@

1 2

R48224_0402_5%

1 2

R48324_0402_5%

CLK_CPU_BCLK
CLK_CPU_BCLK#

CLK_MCH_BCLK
CLK_MCH_BCLK#

12

CLKREQA#
CLK_PCIE_MXM
CLK_PCIE_MXM#

CLK_PCIE_LOM
CLK_PCIE_LOM#

CLK_PCIE_SATA CLK_PCIE_SATA

CPPE#CLKREQB#

12

CLK_PCIE_DOCK#PCIE_DOCK#

CLK_PCIE_ICHPCIE_ICH
CLK_PCIE_ICH#PCIE_ICH#

R46110K_0402_5%NOXDP@

CLKREQC#

12

CLK_CPU_XDP
CLK_MCH_3GPLL
CLK_MCH_3GPLL#

R45110K_0402_5%NOXDP@

CLKREQD#

12

CLK_CPU_XDP#
CLK_PCIE_MCARD
CLK_PCIE_MCARD#

Compal Secret Data

Deciphered Date

2

CLK_CPU_BCLK4
CLK_CPU_BCLK#4

CLK_MCH_BCLK7
CLK_MCH_BCLK#7

+3VS

CLKREQA#18,25
CLK_PCIE_MXM18
CLK_PCIE_MXM#18

CLK_PCIE_LOM25
CLK_PCIE_LOM#25

CLK_PCIE_SATA20
CLK_PCIE_SATA#20

CPPE#19,35

CLK_PCIE_DOCK35
CLK_PCIE_DOCK#35

CLK_PCIE_ICH21

12

12

CLK_PCIE_ICH#21

CLKREQC#7
CLK_CPU_XDP4
CLK_MCH_3GPLL7
CLK_MCH_3GPLL#7

CLKREQD#27
CLK_CPU_XDP#4
CLK_PCIE_MCARD27
CLK_PCIE_MCARD#27

Place near U25

Place these components
near each pin within 40
mils.

+3VS

+3VS

L

Title

SizeDocument NumberRev

Date:Sheet of

Compal Electronics, Inc.

LA-2821P

1

CLK_CPU_BCLK
CLK_CPU_BCLK#

CLK_MCH_BCLK
CLK_MCH_BCLK#

CLK_PCIE_MXM
CLK_PCIE_MXM#

CLK_PCIE_LOM
CLK_PCIE_LOM#

CLK_PCIE_SATA#

CLK_MCH_3GPLL
CLK_MCH_3GPLL#

CLK_PCIE_MCARD
CLK_PCIE_MCARD#

CLK_PCIE_ICH
CLK_PCIE_ICH#

CLK_CPU_XDP
CLK_CPU_XDP#
CLK_PCIE_DOCK
CLK_PCIE_DOCK#

If LP Chip stuff, all 49.9_0402
could be removed .

R45749.9_0402_1%@
R45849.9_0402_1%@

R45949.9_0402_1%@
R46049.9_0402_1%@

1 2

R56249.9_0402_1%@

1 2

R56349.9_0402_1%@

1 2

R55449.9_0402_1%@

1 2

R55549.9_0402_1%@

1 2

R56749.9_0402_1%@

1 2

R56849.9_0402_1%@

1 2

R46649.9_0402_1%@

1 2

R46749.9_0402_1%@

1 2

R46449.9_0402_1%@

1 2

R46549.9_0402_1%@

1 2

R46849.9_0402_1%@

1 2

R46949.9_0402_1%@

R46249.9_0402_1%@
R46349.9_0402_1%@
R55649.9_0402_1%@
R55749.9_0402_1%@

12
12

12
12

12
12
12
12

Clock generator

1552Friday, November 25, 2005

1

0.5

A B C D

+5VS

C76

1

2

D_DDCDATA35

D_DDCCLK35

F1

1.1A_6VDC_FUSE

1

C75

18P_0402_50V8J@

2

D_HSYNC35

D_VSYNC35

CRT Connector

R312

1 2

0_0603_5%

R310

1 2

0_0603_5%

C326

BLUE
GREEN
RED

C77

@

1

2

1

2

R31

1 2

0_0603_5%

R29

1 2

0_0603_5%

R26

18P_0402_50V8J@

1 2

C74

1

2

C325

0_0603_5%

1

5P_0402_50V8C

@

2

5P_0402_50V8C@

1

C73

C71

2

5P_0402_50V8C

@

18P_0402_50V8J@

5P_0402_50V8C

1

2

BLUE35

11

+5VS

5

R308

1 2

51K_0402_5%

P

A2Y

G

3

1 2

M_HSYNC18

M_VSYNC18

R306

22

51K_0402_5%

+5VS

C293

1 2

0.1U_0402_16V4Z

1

U24
SN74AHCT1G125GW_SOT353-5

4

OE#

1

5

P

OE#

A2Y

G

U23
SN74AHCT1G125GW_SOT353-5

3

Place cloce to MXM connector JP39

L

GREEN35

RED35

C294

1 2

0.1U_0402_16V4Z

HSYNC D_HSYNC

VSYNC D_VSYNC

4

5P_0402_50V8C@

D3

21

2 1

CH491D_SC59

0.1U_0402_16V4Z

C420

RED_R

GREEN_R

BLUE_R

1

2

2.2K_0402_5%

D_DDCDATA

D_DDCCLK

+CRTVDD+RCRT_VCC

W=40mils

JP7

6

11

1
7

12

2
8

13

3
9

14

4
10
15

5

FOX_DZ11A91-L7

+CRTVDD +CRTVDD

12

R446

BLUE
GREEN
RED

11/17

150_0402_1%

16
17

+3VS

R450

1 2

2

G

2

G

1 3

DS

2.2K_0402_5%

12

R445

2.2K_0402_5%

1 3

Q68

DS

BSS138_SOT23

Q67
BSS138_SOT23

Place cloce to MXM connector JP39

L

R449

1 2

2.2K_0402_5%

12

R665

M_DDCDATA

M_DDCCLK

12

R666

150_0402_1%

12

M_DDCDATA18

M_DDCCLK18

E

R664
150_0402_1%

TV-Out Connector

Place cloce to TV-Out connector JP1

33

R5450_0603_5%

M_LUMA18,35

M_CRMA18,35
M_COMP18,35

44

M_CRMA
M_COMP

C459

1

1

C488

18P_0402_50V8J@

2

2

18P_0402_50V8J@

1

C478

18P_0402_50V8J@

2

1 2

R5160_0603_5%

1 2

R5290_0603_5%

1 2

Place cloce to TV-Out connector JP1

L

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

L

D7
DAN217_SC59@

D6
DAN217_SC59@

1

2

2005/03/102006/03/10

1

2

3

3

M_LUMA_RM_LUMA
M_CRMA_R

M_COMP_R

Compal Secret Data

D8
DAN217_SC59@

1

2

3

SUYIN_33007SR-07T1-C

Deciphered Date

+3VS

JP10

1
2
3
4
5
6
7

Title

SizeDocument NumberRev

D

Date:Sheet of

Compal Electronics, Inc.

CRT & TVout Connector

LA-2821P

1652Friday, November 25, 2005

E

0.5

5 4 3 2

DD

1

LCD POWER CIRCUITMXM LVDS CONN

B+_LCD

C286

12

0.1U_0603_50V4Z
C287

12

68P_0402_50V8J

L13

1 2

B+

KC FBM-L11-201209-221LMA30T_0805

+3VS

+5VS_INV
M_LCD_CLK18
M_LCD_DAT18

LCDVDD

LID_SW#21,34

ALS_EN19

LID_SW#
ALS_EN

J1

CC

M_PWM18

INV_PWM33

2 1

PAD-SHORT 2x2m

J2

2 1

PAD-No SHORT 2x2m@

JP3

2

2

4

4

6

6

8

8

10

10

12

12

14

14

16

16

18

18

20

20

22

22

24

24

26

26

28

28

30

30

32

32

34

34

36

36

38

38

40

40

42
44
46
48
50

ACES_87216-5002

1

1

3

3

5

5

7

7

9

9

11

11

13

13

15

15

17

17

19

19

21

21

23

23

25

25

27

27

29

29

31

31

33

33

35

35

37

37

39

39
414142
434344
454546
474748
494950

M_TXBCLK+18
M_TXBCLK-18

M_TXB2+18
M_TXB2-18

M_TXB1+18
M_TXB1-18

M_TXB0+18
M_TXB0-18

M_TXACLK+18
M_TXACLK-18

M_TXA2+18
M_TXA2-18

M_TXA1+18
M_TXA1-18

M_TXA0+18
M_TXA0-18

M_ENAVDD18

R307

100_0402_1%

Q55

2N7002_SOT23

M_ENAVDD

LCDVDD

D

S

12

13

2

G

2

13

R315

1 2

47K_0402_5%

Q56
DTC124EK_SC59

1

2

0.1U_0402_16V4Z

C288

Q1

AO3413_SOT23

DS

1 3

2

1

C12

4.7U_0805_10V4Z

2

G

R309

1 2

1M_0402_5%

C298

1 2

0.047U_0402_16V7K

+3VALWLCDVDD

1

C289

4.7U_0805_10V4Z@

2

Q10
DTA114YKA_SC59

13

Q13
BSS138_SOT23

+5VS_INV

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2005/03/102006/03/10

Compal Secret Data

Deciphered Date

2

Title

SizeDocument NumberRev

Date:Sheet of

Compal Electronics, Inc.

LCD CONN.

LA-2821P

1752Friday, November 25, 2005

1

0.5

BB

LID_SW#

1

M_ENBLT18

100K_0402_5%

AA

2

R86

1 2

+5VS

+3VS

U11A
SN74LVC08APW_TSSOP14

14

P

A

3

O

B

G

R80

7

100K_0402_5%

47K

10K

2

13

D

2

G

S

1 2

5 4 3 2

PEG_RXN[0..15]9

PEG_RXP[0..15]9
PEG_M_TXN[0..15]9
PEG_M_TXP[0..15]9

+1.8VS

+5VS

+3VS

R303

8.2K_0402_5%@

1 2

PEG_M_TXN15
PEG_M_TXP15

PEG_M_TXN14
PEG_M_TXP14

PEG_M_TXN13
PEG_M_TXP13

PEG_M_TXN12
PEG_M_TXP12

PEG_M_TXN11
PEG_M_TXP11

PEG_M_TXN10
PEG_M_TXP10

PEG_M_TXN9
PEG_M_TXP9

PEG_M_TXN8
PEG_M_TXP8

PEG_M_TXN7
PEG_M_TXP7

PEG_M_TXN6
PEG_M_TXP6

PEG_M_TXN5
PEG_M_TXP5

PEG_M_TXN4
PEG_M_TXP4

PEG_M_TXN3
PEG_M_TXP3

PEG_M_TXN2
PEG_M_TXP2

+1.8VS

1

C292

4.7U_0805_10V4Z

2

PWR_GD33,36,37,45,47

CLKREQA#15,25

ICH_SMBDATA4,13,14,15,21,25,27

ICH_SMBCLK4,13,14,15,21,25,27

MXM_CD1#21,47

R311

ICH_SMBDATA
ICH_SMBCLK

CLK_PCIE_MXM#15

CLK_PCIE_MXM15

1 2

0_0402_5%@

VGA_RST#21

R3200_0402_5%
R3190_0402_5%

ADP_PRES25,33,40,41,42,47

MXM Address:100_1100

1 2
1 2

MXM_THERM#21

M_HSYNC16

M_VSYNC16

M_DDCCLK16

M_DDCDATA16

+5VALW

SLP_S3#21,25,27,28,29,33,35,36,40,43,44

R3130_0402_5%

DVI_DETECT35

DVI_CLK-35

DVI_CLK+35

DVI_TX2-35

DVI_TX2+35

DVI_TX1-35

DVI_TX1+35

DVI_TX0-35

DVI_TX0+35

PEG_RXN1
PEG_RXP1

PEG_RXN0
PEG_RXP0

CLK_PCIE_MXM#
CLK_PCIE_MXM

VGA_RST#

MXM_SMBDATA
MXM_SMBCLK
MXM_THERM#
M_HSYNC
M_VSYNC
M_DDCCLK
M_DDCDATA

SLP_S3#

1 2

DVI_DETECT
DVI_CLK­DVI_CLK+

DVI_TX2­DVI_TX2+

DVI_TX1­DVI_TX1+

DVI_TX0­DVI_TX0+

JP5B

109

PEX_RX1#

111

PEX_RX1

113

GND

115

PEX_RX0#

117

PEX_RX0

119

GND

121

PEX_REFCLK#

123

PEX_REFCLK

125

CLK_REQ#

127

PEX_RST#

129

RSVD

131

RSVD

133

SMB_DAT

135

SMB_CLK

137

THERM#

139

VGA_HSYNC

141

VGA_VSYNC

143

DDCA_CLK

145

DDCA_DAT

147

IGP_UCLK#

149

IGP_UCLK

151

GND

153

RSVD

155

RSVD

157

RSVD

159

IGP_UTX2#

161

IGP_UTX2

163

GND

165

IGP_UTX1#

167

IGP_UTX1

169

GND

171

IGP_UTX0#

173

IGP_UTX0

175

GND

177

IGP_LCLK#/DVI_B_CLK#

179

IGP_LCLK/DVI_B_CLK

181

DVI_B_HPD/GND

183

RSVD

185

RSVD

187

GND

189

IGP_LTX2#/DVI_B_TX2#

191

IGP_LTX2/DVI_B_TX2

193

GND

195

IGP_LTX1#/DVI_B_TX1#

197

IGP_LTX1/DVI_B_TX1

199

GND

201

IGP_LTX0#/DVI_B_TX0#

203

IGP_LTX0/DVI_B_TX0

205

DVI_A_HPD

207

DVI_A_CLK#

209

DVI_A_CLK

211

GND

213

DVI_A_TX2#

215

DVI_A_TX2

217

GND

219

DVI_A_TX1#

221

DVI_A_TX1

223

GND

225

DVI_A_TX0#

227

DVI_A_TX0

229

GND

ACES_88990-2D28_GF

GND

PEX_TX1#

PEX_TX1

GND

PEX_TX0#

PEX_TX0
PRSNT1#

TV_C/HDTV_Pr

GND

TV_Y/HDTV_Y

GND

TV_CVBS/HDTV_Pb

GND

VGA_RED

GND

VGA_GRN

GND

VGA_BLU

GND

LVDS_UCLK#

LVDS_UCLK

GND

LVDS_UTX3#

LVDS_UTX3

GND

LVDS_UTX2#

LVDS_UTX2

GND

LVDS_UTX1#

LVDS_UTX1

GND

LVDS_UTX0#

LVDS_UTX0

GND

LVDS_LCLK#

LVDS_LCLK

GND

LVDS_LTX3#

LVDS_LTX3

GND

LVDS_LTX2#

LVDS_LTX2

GND

LVDS_LTX1#

LVDS_LTX1

GND

LVDS_LTX0#

LVDS_LTX0

GND
DDCC_DAT
DDCC_CLK

LVDS_PPEN

LVDS_BL_BRGHT

LVDS_BLEN

DDCB_DAT
DDCB_CLK

2V5RUN

GND

3V3RUN
3V3RUN
3V3RUN

MXM_CD0#

110

PEG_M_TXN1

112

PEG_M_TXP1

114
116

PEG_M_TXN0

118

PEG_M_TXP0

120

MXM_CD0#

122

MXM_CRMA

124
126

MXM_LUMA

128
130

MXM_COMP

132
134

M_RED

136
138

M_GRN

140
142

M_BLU

144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204
206
208
210
212
214
216
218
220
222
224
226
228
230

1

C4

4.7U_0805_10V4Z

2

DD

1

+

C9

100U_25V_M

2

9/15

PEG_RXN15
PEG_RXP15

PEG_RXN14
PEG_RXP14

PEG_RXN13
PEG_RXP13

PEG_RXN12

CC

BB

PEG_RXP12
PEG_RXN11

PEG_RXP11
PEG_RXN10

PEG_RXP10
PEG_RXN9

PEG_RXP9
PEG_RXN8

PEG_RXP8
PEG_RXN7

PEG_RXP7
PEG_RXN6

PEG_RXP6
PEG_RXN5

PEG_RXP5
PEG_RXN4

PEG_RXP4
PEG_RXN3

PEG_RXP3
PEG_RXN2

PEG_RXP2

0.1U_0603_50V4Z

1

C11

2

B+

JP5A

1

PWR_SRC

3

PWR_SRC

5

PWR_SRC

7

PWR_SRC

9

PWR_SRC

11

PWR_SRC

13

PWR_SRC

15

PWR_SRC

17

GND

19

GND

21

GND

23

GND

25

PEX_RX15#

27

PEX_RX15

29

GND

31

PEX_RX14#

33

PEX_RX14

35

GND

37

PEX_RX13#

39

PEX_RX13

41

GND

43

PEX_RX12#

45

PEX_RX12

47

GND

49

PEX_RX11#

51

PEX_RX11

53

GND

55

PEX_RX10#

57

PEX_RX10

59

GND

61

PEX_RX9#

63

PEX_RX9

65

GND

67

PEX_RX8#

69

PEX_RX8

71

GND

73

PEX_RX7#

75

PEX_RX7

77

GND

79

PEX_RX6#

81

PEX_RX6

83

GND

85

PEX_RX5#

87

PEX_RX5

89

GND

91

PEX_RX4#

93

PEX_RX4

95

GND

97

PEX_RX3#

99

PEX_RX3

101

GND

103

PEX_RX2#

105

PEX_RX2

107

GND

ACES_88990-2D28_GF

1V8RUN
1V8RUN
1V8RUN
1V8RUN
1V8RUN
1V8RUN
1V8RUN

RUNPWROK

5VRUN

GND
GND
GND

PRSNT2#

PEX_TX15#

PEX_TX15

GND

PEX_TX14#

PEX_TX14

GND

PEX_TX13#

PEX_TX13

GND

PEX_TX12#

PEX_TX12

GND

PEX_TX11#

PEX_TX11

GND

PEX_TX10#

PEX_TX10

GND

PEX_TX9#

PEX_TX9

GND

PEX_TX8#

PEX_TX8

GND

PEX_TX7#

PEX_TX7

GND

PEX_TX6#

PEX_TX6

GND

PEX_TX5#

PEX_TX5

GND

PEX_TX4#

PEX_TX4

GND

PEX_TX3#

PEX_TX3

GND

PEX_TX2#

PEX_TX2

2
4
6
8
10
12
14
16
18
20
22
24

26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108

MXM_CD0#21

R305

1 2

8.2K_0402_5%@

M_TXBCLK-17
M_TXBCLK+17

M_TXB2-17
M_TXB2+17

M_TXB1-17
M_TXB1+17

M_TXB0-17
M_TXB0+17

M_TXACLK-17
M_TXACLK+17

M_TXA2-17
M_TXA2+17

M_TXA1-17
M_TXA1+17

M_TXA0-17
M_TXA0+17

M_LCD_DAT17
M_LCD_CLK17
M_ENAVDD17
M_PWM17
M_ENBLT17
DVI_DDC_DAT35
DVI_DDC_CLK35

+2.5VS
+3VS

1

+3VS

Place those components as close as

L

MXMIII connector within 500 mils.

MXM_LUMA

MXM_CRMA

MXM_COMP

12

R316
150_0402_1%

AA

12

R314
150_0402_1%

12

TV-Out Termination/EMI Filter

MXM_LUMA M_LUMA

MXM_CRMA

MXM_COMP

R317
150_0402_1%

82P_0402_50V8J

Place cloce to MXM connector JP39

1

C17

2

L

82P_0402_50V8J

C18

1

1

C19

2

2

82P_0402_50V8J

L8

1 2

CHB1608U301_0603
L9

1 2

CHB1608U301_0603
L7

1 2

CHB1608U301_0603

82P_0402_50V8J

C13

1

1

C15

2

2

82P_0402_50V8J

M_CRMA

M_COMP

1

C14
82P_0402_50V8J

2

M_LUMA16,35

M_CRMA16,35

M_COMP16,35

M_RED RED_LL

M_GRN

M_BLU BLUE_LL

12

12

R10
150_0402_1%@

CRT Termination/EMI Filter

L4

1 2

HLC0603CSCC39NJT_0603

R11
150_0402_1%@

L5

1 2

HLC0603CSCC39NJT_0603

L2

1 2

HLC0603CSCC39NJT_0603

12

R2
150_0402_1%@

GREEN_LL

1

C3

2

18P_0402_50V8J

1

2

C7
18P_0402_50V8J

L1

1 2

HLC0603CSCCR11JT_0603

L6

1 2

HLC0603CSCCR11JT_0603

L3

1 2

HLC0603CSCCR11JT_0603

1

C2
18P_0402_50V8J

2

D_RED

D_GREEN

D_BLUE

Place those components as close

D_RED35

D_GREEN35

D_BLUE35

as MXMIII connector within 500 mils.

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2005/03/102006/03/10

Compal Secret Data

Deciphered Date

Title

SizeDocument NumberRev

2

Date:Sheet of

Compal Electronics, Inc.

MXM III CONN

LA-2821P

1852Friday, November 25, 2005

1

0.5

5

4

3

2

1

DD

CC

BB

+3VS

R6178.2K_0402_5%

1 2

R6138.2K_0402_5%

1 2

R6168.2K_0402_5%

1 2

R6118.2K_0402_5%

1 2

R6198.2K_0402_5%

1 2

R6258.2K_0402_5%

1 2

R6228.2K_0402_5%

1 2

R6238.2K_0402_5%

1 2

R6158.2K_0402_5%

1 2

R6188.2K_0402_5%

1 2

+3VS

R1068.2K_0402_5%

1 2

R1078.2K_0402_5%

1 2

R1058.2K_0402_5%

1 2

R6358.2K_0402_5%

1 2

R6268.2K_0402_5%

1 2

R6288.2K_0402_5%

1 2

R6248.2K_0402_5%

1 2

R6328.2K_0402_5%@

1 2

9/2

R6318.2K_0402_5%

1 2

R6108.2K_0402_5%

1 2

R6078.2K_0402_5%

1 2

R6278.2K_0402_5%

1 2

R6128.2K_0402_5%

1 2

PCI_DEVSEL#
PCI_STOP#
PCI_TRDY#
PCI_FRAME#
PCI_PLOCK#
PCI_IRDY#
PCI_SERR#
PCI_PERR#
PCI_REQ4#
PCI_REQ3#

PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#
PCI_PIRQE#
PCI_PIRQF#
PCI_PIRQG#
PCI_PIRQH#
PCI_REQ0#
PCI_REQ1#
PCI_REQ2#
CPPE#
ICH_GPIO48

PCI_AD[0..31]23

PCI_PIRQC#23
PCI_PIRQD#23

PCI_AD0
PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD6
PCI_AD7
PCI_AD8
PCI_AD9
PCI_AD10
PCI_AD11
PCI_AD12
PCI_AD13
PCI_AD14
PCI_AD15
PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20
PCI_AD21
PCI_AD22
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30
PCI_AD31

PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#

U10B

E18

AD0

C18

AD1

A16

AD2

F18

AD3

E16

AD4

A18

AD5

E17

AD6

A17

AD7

A15

AD8

C14

AD9

E14

AD10

D14

AD11

B12

AD12

C13

AD13

G15

AD14

G13

AD15

E12

AD16

C11

AD17

D11

AD18

A11

AD19

A10

AD20

F11

AD21

F10

AD22

E9

AD23

D9

AD24

B9

AD25

A8

AD26

A6

AD27

C7

AD28

B6

AD29

E6

AD30

D6

AD31

Interrupt I/F

A3

PIRQA#

B4

PIRQB#

C5

PIRQC#

B5

PIRQD#

AE5

RSVD[1]

AD5

RSVD[2]

AG4

RSVD[3]

AH4

RSVD[4]

AD9

RSVD[5]

ICH7M_B0_BGA652

PCI

REQ4# / GPIO22
GNT4# / GPIO48

GPIO1 / REQ5#

GPIO17 / GNT5#

GPIO2 / PIRQE#
GPIO3 / PIRQF#
GPIO4 / PIRQG#
GPIO5 / PIRQH#

MISC

MCH_SYNC#

REQ0#

GNT0#

REQ1#

GNT1#

REQ2#

GNT2#

REQ3#

GNT3#

C/BE0#
C/BE1#
C/BE2#
C/BE3#

IRDY#

PAR

PCIRST#

DEVSEL#

PERR#

PLOCK#

SERR#

STOP#
TRDY#

FRAME#

PLTRST#

PCICLK

PME#

RSVD[6]
RSVD[7]
RSVD[8]
RSVD[9]

D7
E7
C16
D16
C17
D17
E13
F13
A13
A14
C8
D8

B15
C12
D12
C15

A7
E10
B18
A12
C9
E11
B10
F15
F14
F16

C26
A9
B19

G8
F7
F8
G7

AE9
AG8
AH8
F21
AH20

PCI_REQ0#
PCI_GNT0#
PCI_REQ1#

PCI_REQ2#
PCI_GNT2#
PCI_REQ3#

PCI_REQ4#
ICH_GPIO48
CPPE#
ALS_EN#

PCI_CBE#0
PCI_CBE#1
PCI_CBE#2
PCI_CBE#3

PCI_IRDY#
PCI_PAR
PCI_PCIRST#
PCI_DEVSEL#
PCI_PERR#
PCI_PLOCK#
PCI_SERR#
PCI_STOP#
PCI_TRDY#

PCI_FRAME#

PCI_PLTRST#
CLK_PCI_ICH
PCI_PME#

PCI_PIRQE#
PCI_PIRQF#
PCI_PIRQG#
PCI_PIRQH#

PCI_REQ2#23
PCI_GNT2#23

CPPE#15,35

PCI_CBE#023
PCI_CBE#123
PCI_CBE#223
PCI_CBE#323

PCI_IRDY#23
PCI_PAR23

PCI_DEVSEL#23
PCI_PERR#23

PCI_SERR#23,33
PCI_STOP#23
PCI_TRDY#23
PCI_FRAME#23

CLK_PCI_ICH15
PCI_PME#23

PCI_PIRQE#23
PCI_PIRQG#23

R636

12

0_0402_5%

MCH_ICH_SYNC#7

PCI_PCIRST#

PCI_PLTRST#

ACCEL_INT27

11/23

R675

1 2

0_0402_5%

Place closely pin A9

CLK_PCI_ICH

R621

10_0402_5% @

1 2
1

C145

8.2P_0402_50V@

2

12

ALS_EN#

R83

1K_0402_5%SPI@

ALS_EN#

R71
0_0402_5%

R66
0_0402_5%@

+5VS

R89
330_0402_5%

1 2

ALS_EN

13

D

2

G

S

+3VS

5

U9

1

P

B

2

A

G

TC7SH08FU_SSOP5@

3

12

+3VS

14

12

P

A

13

B

G

U11D

7

SN74LVC08APW_TSSOP14

12

Q15
2N7002_SOT23

4

Y

11

1 2

O

PCI_RST#

R676

0_0402_5%

PLT_RST#

ALS_EN17

PCI_RST#23,24

PLT_RST#7,20,21,23,25,27,32,33

AA

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/03/102006/03/10

Compal Secret Data

Deciphered Date

Title

SizeDocument NumberRev

2

Date:Sheet of

Compal Electronics, Inc.

ICH7-M(1/4)

LA-2821P

1952Friday, November 25, 2005

1

0.5

5 4 3 2

1

12

12

12
12

R430

R10033_0402_5%
R11333_0402_5%

R26933_0402_5%
R25333_0402_5%

12
12

R24033_0402_5%

R63033_0402_5%

R24533_0402_5%
R24733_0402_5%

BATT1

12

R96
10M_0402_5%

IDE_LED#

SATA_RXN0_C
SATA_RXP0_C
SATA_TXN0_C
SATA_TXP0_C

CLK_PCIE_SATA#
CLK_PCIE_SATA

R620

1 2

24.9_0402_1%

PD_IORDY

R6094.7K_0402_5%
R6088.2K_0402_5%

PD_IRQ
PD_DACK#
PD_IOW#
PD_IOR#

7/6

ICH_RTCX1

ICH_RTCX2
ICH_RTCRST#
ICH_INTVRMEN

SM_INTRUDER#

AC97_BITCLK
AC97_SYNC

AC97_RST#
AC97_SDIN0

AC97_SDIN1

AC97_SDOUT

D32

1

DAN202U_SC70

AF18

AH10

AG10

AG16

AH16
AF16
AH15
AF15

L

AB1
AB2

AA3

W4

W1

W3

U3
U5

U7

U1
R6

R5

AF3
AE3
AG2
AH2

AF7
AE7
AG6
AH6

AF1
AE1

3

2

Y5

Y1
Y2

V3

V4
T5

V6
V7

T2
T3
T1

T4

ZZZ

PCB-MB

U10A

RTXC1
RTCX2

RTCRST#
INTVRMEN

INTRUDER#

EE_CS
EE_SHCLK
EE_DOUT
EE_DIN

LAN_CLK
LAN_RSTSYNC
LAN_RXD0

LAN_RXD1
LAN_RXD2

GPIO49 / CPUPWRGD
LAN_TXD0
LAN_TXD1
LAN_TXD2

ACZ_BCLK
ACZ_SYNC

ACZ_RST#
ACZ_SDIN0

ACZ_SDIN1
ACZ_SDIN2

ACZ_SDOUT

SATALED#

SATA0RXN
SATA0RXP
SATA0TXN
SATA0TXP

SATA2RXN
SATA2RXP
SATA2TXN
SATA2TXP

SATA_CLKN
SATA_CLKP

SATARBIASN
SATARBIASP

IORDY
IDEIRQ
DDACK#
DIOW#
DIOR#

ICH7M_B0_BGA652

R423

1 2

1K_0402_5%

W=20mils

RTC

LPCCPU

LDRQ1# / GPIO23

LAN

TP1 / DPRSTP#

TP2 / DPSLP#

AC-97/AZALIA

THERMTRIP#

SATA

IDE

LPC_AD0

AA6

LAD0

LPC_AD1

AB5

LAD1

LPC_AD2

AC4

LAD2

LPC_AD3

Y6

LAD3

LPC_DRQ#0

AC3

LDRQ0#

LFRAME#

A20GATE

A20M#

CPUSLP#

FERR#

IGNNE#

INIT3_3V#

RCIN#

STPCLK#

DCS1#
DCS3#

DDREQ

RTC2RTC1

AA5
AB3

AE22
AH28

AG27
AF24

AH25
AG26
AG24
AG22

AG21
AF22

INIT#

AF25

INTR

AG23
AF23

SMI#

AH24

NMI

AH22
AF26

AH17

DA0

AE17

DA1

AF17

DA2

AE16
AD16

AB15

DD0

AE14

DD1

AG13

DD2

AF13

DD3

AD14

DD4

AC13

DD5

AD12

DD6

AC12

DD7

AE12

DD8

AF12

DD9

AB13

DD10

AC14

DD11

AF14

DD12

AH13

DD13

AH14

DD14

AC15

DD15

AE15

JP28

E&T_7651

PLT_RST#7,19,21,23,25,27,32,33

SN74LVC08APW_TSSOP14

LPC_DRQ#1
LPC_FRAME#

GATEA20
H_A20M#

H_CPUSLP_R#
DPRSLP#

H_DPSLP#
H_FERR#
H_PWRGOOD
H_IGNNE#

FWH_INIT#
H_INIT#
H_INTR

KB_RST#
H_SMI#

H_NMI

R598

0_0402_5%

THRMTRIP_ICH#

PD_A0
PD_A1
PD_A2

PD_CS#1
PD_CS#3

PD_D0
PD_D1
PD_D2
PD_D3
PD_D4
PD_D5
PD_D6
PD_D7
PD_D8
PD_D9
PD_D10
PD_D11
PD_D12
PD_D13
PD_D14
PD_D15

PD_DREQ

21

-+

U11B

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

LPC_AD[0..3]27,31,32,33

LPC_DRQ#031
LPC_DRQ#1

LPC_FRAME#27,31,32,33

R6110K_0402_5%

12

GATEA2033
H_A20M#4

T14

PAD

R580_0402_5%
R5456_0402_5%

R6010K_0402_5%

4
5

12
12

H_FERR#4
H_PWRGOOD4
H_IGNNE#4

T26

PAD

9/8

H_INIT#4
H_INTR4

12

KB_RST#33
H_SMI#4

H_NMI4

H_STPCLK#

12

R591

1 2

24.9_0402_1%

R1031 must be placed close to U26.AF26

L

within 2" and R1030 must be placed close
to R1031 within 2".

H_STPCLK#

IDE_LED#32

+3VS

1

C147

0.1U_0402_16V4Z

2

14

P

A

6

O

G

7

R8833_0402_5%

B

2005/03/102006/03/10

H_DPRSTP#4,45
H_DPSLP#4

+VCCP

+VCCP

+3VS

12

2 1

CH751H-40_SC76

12

Compal Secret Data

+3VS

R592
56_0402_5%

H_STPCLK#4

D35

+5VS

PLT_RST_B#27,31

Deciphered Date

H_THERMTRIP#4,7

11/18

+5VS

12

R512

10K_0402_5%

1 2

R4994.7K_0402_5%@
R503470_0402_5%

ODD_RST#

12

8/24

2

+5VS

1

2

+5VS

1

2

SATA CONN

JP20

24

GND

S1

GND

S2

A+

S3

A-

S4

GND

S5

B-

S6

B+

S7

GND

P1

V33

P2

V33

P3

V33

P4

GND

P5

GND

P6

GND

P7

V5

P8

V5

P9

V5

P10

GND

P11

RSVD

P12

GND

P13

V12

P14

V12

P15

V12

23

GND

OCTEK_SAT-22DN1G_NR

C148
10U_0805_10V4Z

ODD_RST#
PD_D7
PD_D6
PD_D5
PD_D4
PD_D3
PD_D2
PD_D1
PD_D0

PD_IOW#
PD_IORDY
PD_IRQ
PD_A1
PD_A0
PD_CS#1
IDE_DSP#

+5VS
+5VS

SEC_CSEL

C98
10U_0805_10V4Z

1

C153

0.1U_0402_16V4Z

2

Place component's closely IDE CONN. JP45

L

ODD CONN

JP13

112
334
556
778
9910
111112
131314
151516
171718
191920
212122
232324
252526
272728
292930
313132
333334
353536
373738
393940
414142
434344
454546
474748
494950

OCTEK_CDR-50DU1

1

C100

0.1U_0402_16V4Z

2

Place component's closely IDE CONN. JP37

L

Title

SizeDocument NumberRev

Date:Sheet of

SATA_TXP0
SATA_TXN0

SATA_RXN0
SATA_RXP0

+5VS

1

C151

0.1U_0402_16V4Z

2

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50

1

C101

0.1U_0402_16V4Z

2

1

C156

0.1U_0402_16V4Z

2

PD_D8
PD_D9
PD_D10
PD_D11
PD_D12
PD_D13
PD_D14
PD_D15
PD_DREQ
PD_IOR#

PD_DACK#
PDIAG#

R509100K_0402_5%

PD_A2
PD_CS#3

1 2

W=80mils

12

C1040.1U_0402_16V4Z

1

C102

0.1U_0402_16V4Z

2

Compal Electronics, Inc.

ICH7-M(2/4)

LA-2821P

1

+5VS
+5VS
+5VS

+5VS

0.5

2052Friday, November 25, 2005

C15818P_0402_50V8J

12

Y1

2
3

32.768KHZ_12.5P_1TJS125BJ2A251

DD

CC

BB

+RTCVCC

+3VALW

12

R102
332K_0402_1%@

SATA_TXP0_C SATA_TXP0

L

AA

SATA_RXN0_C

SATA_RXP0_C

L

R645

1 2

20K_0402_5%

CMOS_CLR1

1 2

SHORT PADS

C159

1U_0603_10V4Z

1 2

AC97_BITCLK_MDC34

AC97_BITCLK_CODEC28

AC97_SYNC_MDC34

AC97_SYNC_CODEC28

AC97_RST#_MDC34

AC97_RST#_CODEC28

AC97_SDOUT_CODEC28

AC97_SDOUT_MDC34

+RTCVCC

12

R103
332K_0402_1%

ICH_INTVRMEN

12

R101

0_0402_5%@

C1503900P_0402_50V7K

1 2

C1493900P_0402_50V7K

1 2

Near ICH7(U26) side.

C1753900P_0402_50V7K

1 2

C1733900P_0402_50V7K

1 2

Near Device(JP45) side.

C15718P_0402_50V8J

+RTCVCC

+3VS

SATA_TXN0SATA_TXN0_C

SATA_RXN0

SATA_RXP0

1

IN

NC

4

OUT

NC

12

R629

1 2

1M_0402_5%

1 2
1 2
1 2

1 2

AC97_SDIN028
AC97_SDIN134

CLK_PCIE_SATA#15
CLK_PCIE_SATA15

+RTCVCC +3VL

1 2

100_0402_5%

1

C403
1U_0603_10V4Z

2

45@

CR2025 RTC BATTERY

5 4 3 2

1

Place closely pin B2 Place closely pin AC1

+3VALW

R593

R595

DD

ICH_SMBDATA4,13,14,15,18,25,27

ICH_SMBCLK4,13,14,15,18,25,27

+3VS

10K_0402_5%@

R68

R63

CC

BB

AA

R73

+3VALW

R589

R596

R594

R606

VGA_RST#18

THERM_SCI#

1 2

10K_0402_5%

SIRQ

1 2

8.2K_0402_5%

PM_CLKRUN#

1 2

10K_0402_5%

LINKALERT#

1 2

10K_0402_5%

XDP_DBRESET#

1 2

10K_0402_5%

OCP#

1 2

10K_0402_5%

LID_SW#

1 2

+3VALW +3VS

11/21

12

R78

10K_0402_5%

PREP#26,35

PREP#

8

+3VALW

R97

1 2

R110

1 2

R111

1 2

R1284,R1285 and R1286 should

L

be placed close to U26.

D14

CH751H-40_SC76

+3VS

14

P

A

O

B

G

7

10K_0402_5%SPI@

10K_0402_5%SPI@

10K_0402_5%SPI@

10K_0402_5%

+3VS

R79

2.2K_0402_5%@

ICH_SMBCLK ICH_SMB_CLK

LOM_PCIE_WAKE#25

PCIE_WAKE#27

12

R76
10K_0402_5%

ISO_PREP#

21

M24_RST#

9

PLT_RST#

10

U11C
SN74LVC08APW_TSSOP14

SPI_CS#

SPI_SI

SPI_SO

10K_0402_5%

1 2

1 2

12

12

R84

2.2K_0402_5%@
2N7002_SOT23@

Q11

D

S

13

S

G

2

G

2

+3VALW

V_3P3_LAN

VGATE_INTEL7,45

PM_POK7,33

PLT_RST#7,19,20,23,25,27,32,33

ICH_SMBCLK
ICH_SMBDATA

ICH_SMB_DATAICH_SMBDATA

D

13

Q14

2N7002_SOT23@

+5VS

R604

1K_0402_5%

1 2

S

Q8

G

BSS138_SOT23

R603

1 2

0_0402_5%

R640_0402_5%
R590_0402_5%@

PCIE_RXN125
PCIE_RXP125
PCIE_TXN125

PCIE_TXP125

PCIE_RXN227
PCIE_RXP227
PCIE_TXN227

PCIE_TXP227

PCIE_RXN435
PCIE_RXP435
PCIE_TXN435

PCIE_TXP435

2

D

13

1 2
1 2

MXM_CD1#18,47

2.2K_0402_5%

R82

0_0402_5%

1 2

0_0402_5%

1 2

R77

+3VALW

11/14

M24_RST#

+3VALW

R600

R1292/R1293 should be placed

L

less than 100 mils from U26.

SPI_CLK32
SPI_CS#32

SPI_SI32

SPI_SO32

MXM_CD1# MXM_CD1#_R

SB_SPKR28
LPC_PD#32,33

XDP_DBRESET#4

PM_BMBUSY#7

H_STP_PCI#15

H_STP_CPU#15

R586

PM_CLKRUN#23,31,32,33

THERM_SCI#4

RUNSCI_EC#33

ISO_PREP#35

1 2

10K_0402_5%

SPI_CLK
SPI_CS#

SPI_SI
SPI_SO

R75

LP_EN#25

PWROK_ICH7

11/22

USB_OC#1
USB_OC#229
USB_OC#329
USB_OC#430
USB_OC#530

MXM_CD0#18

+3VALW

12

12

R81

2.2K_0402_5%

ICH_SMB_CLK
ICH_SMB_DATA
LINKALERT#
ICH_SMLINK0
ICH_SMLINK1

R587

OCP#4,47

T27PAD
T49PAD

1 2

0_0402_5%

T31PAD
T32PAD

SIRQ23,31,32,33

C1330.1U_0402_16V4Z

12

C1340.1U_0402_16V4Z

12

C1270.1U_0603_16V7K

12

C1280.1U_0603_16V7K

12

C1290.1U_0402_16V4Z

12

C1300.1U_0402_16V4Z

12

R98

R99

1 2

ICH_RI#
SB_SPKR

LPC_PD#
XDP_DBRESET#

PM_BMBUSY#
OCP#

H_STP_PCI#
H_STP_CPU#

GPIO26_SB
GPIO27_SB
GPIO28_SB
PM_CLKRUN#
FWH_WP#

FWH_TBL#
ICH_PCIE_WAKE#

SIRQ
THERM_SCI#

PWROK_ICH7

RUNSCI_EC#
ISO_PREP#
LP_EN#

PCIE_RXN1
PCIE_RXP1
PCIE_C_TXN1
PCIE_C_TXP1

PCIE_RXN2
PCIE_RXP2
PCIE_C_TXN2
PCIE_C_TXP2

PCIE_RXN4
PCIE_RXP4
PCIE_C_TXN4
PCIE_C_TXP4

1 2

1 2

1 2

8.2K_0402_5%

R6390_0402_5%

R213,R233 change from 2.2Kohm to

L

10Kohm when Q23,Q24,R206,R204 stuffed.

U10C

C22

SMBCLK

B22

SMBDATA

A26

LINKALERT#

B25

SMLINK0

A25

SMLINK1

A28

RI#

A19

SPKR

A27

SUS_STAT#

A22

SYS_RST#

AB18

GPIO0 / BM_BUSY#

B23

GPIO11 / SMBALERT#

AC20

GPIO18 / STPPCI#

AF21

GPIO20 / STPCPU#

A21

GPIO26

B21

GPIO27

E23

GPIO28

AG18

GPIO32 / CLKRUN#

AC19

GPIO33 / AZ_DOCK_EN#

U2

GPIO34 / AZ_DOCK_RST#

F20

WAKE#

AH21

SERIRQ

AF20

THRM#

AD22

VRMPWRGD

AC21

GPIO6

AC18

GPIO7

E21

11/14

47_0402_5%SPI@

47_0402_5%SPI@

USB_OC#0
USB_OC#1
USB_OC#2
USB_OC#3
USB_OC#4
USB_OC#5
MXM_CD0#

GPIO8

ICH7M_B0_BGA652

MXM_THERM#18

U10D

F26

PERn1

F25

PERp1

E28

PETn1

E27

PETp1

H26

PERn2

H25

PERp2

G28

PETn2

G27

PETp2

K26

PERn3

K25

PERp3

J28

PETn3

J27

PETp3

M26

PERn4

M25

PERp4

L28

PETn4

L27

PETp4

P26

PERn5

P25

PERp5

N28

PETn5

N27

PETp5

T25

PERn6

T24

PERp6

R28

PETn6

R27

PETp6

R2

SPI_CLK

P6

SPI_CS#

P1

SPI_ARB

P5

SPI_MOSI

P2

SPI_MISO

D3

OC0#

C4

OC1#

D5

OC2#

D4

OC3#

E5

OC4#

C3

OC5# / GPIO29

A2

OC6# / GPIO30

B3

OC7# / GPIO31

ICH7M_B0_BGA652

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

GPIO

1 2

0_0402_5%

PCI-EXPRESS

SPI

USB

2005/03/102006/03/10

GPIO21 / SATA0GP

SMB

GPIO19 / SATA1GP
GPIO36 / SATA2GP
GPIO37 / SATA3GP

SATA

GPIO

SYS

Clocks

GPIO

GPIO16 / DPRSLPVR

TP0 / BATLOW#

POWER MGT

GPIO35 / SATAREQ#

Need update symbol

THERM_SCI#

R67

DIRECT MEDIA INTERFACE

DMI0RXN
DMI0RXP

DMI0TXN
DMI0TXP

DMI1RXN
DMI1RXP

DMI1TXN
DMI1TXP

DMI2RXN
DMI2RXP

DMI2TXN
DMI2TXP

DMI3RXN
DMI3RXP

DMI3TXN
DMI3TXP

DMI_CLKN

DMI_CLKP

DMI_ZCOMP

DMI_IRCOMP

USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4N
USBP4P
USBP5N
USBP5P
USBP6N
USBP6P
USBP7N
USBP7P

USBRBIAS#

USBRBIAS

Compal Secret Data

V26
V25
U28
U27

Y26
Y25
W28
W27

AB26
AB25
AA28
AA27

AD25
AD24
AC28
AC27

AE28
AE27

C25
D25

F1
F2
G4
G3
H1
H2
J4
J3
K1
K2
L4
L5
M1
M2
N4
N3

D2
D1

CLK14
CLK48

SUSCLK

SLP_S3#
SLP_S4#
SLP_S5#

PWROK

PWRBTN#
LAN_RST#

RSMRST#

GPIO9
GPIO10
GPIO12
GPIO13
GPIO14
GPIO15
GPIO24
GPIO25

GPIO38
GPIO39

DMI_RXN0
DMI_RXP0
DMI_TXN0
DMI_TXP0

DMI_RXN1
DMI_RXP1
DMI_TXN1
DMI_TXP1

DMI_RXN2
DMI_RXP2
DMI_TXN2
DMI_TXP2

DMI_RXN3
DMI_RXP3
DMI_TXN3
DMI_TXP3

CLK_PCIE_ICH#
CLK_PCIE_ICH

DMI_IRCOMP
USB20_N0

USB20_P0
USB20_N1
USB20_P1
USB20_N2
USB20_P2
USB20_N3
USB20_P3
USB20_N4
USB20_P4
USB20_N5
USB20_P5
USB20_N6
USB20_P6
USB20_N7
USB20_P7

USBRBIAS

Deciphered Date

AF19
AH18
AH19
AE19

CLK_14M_ICH

AC1

CLK_48M_ICH

B2

ICH_SUSCLK

C20

SLP_S3#

B24

SLP_S4#

D23

SLP_S5#

F22

PM_POK

AA4

DPRSLPVR

AC22

ICH_LOW_BAT#

C21

ON/OFFBTN#

C23

PLT_RST#

C19

PM_RSMRST#

Y4

R63410K_0402_5%

1 2

GPIO9_SB

E20

CB_IN#

A20

GPIO12_SB

F19

LID_SW#

E19

LANLINK_STATUS#_SB

R4

GPIO15_SB

E22

XMIT_OFF

R3

BT_OFF

D20

NPCI_RST#

AD21
AD20
AE20

GPIO39_SB

R58824.9_0402_1%

R64122.6_0402_1%

Within 500 mils

1 2

100_0402_5%

R605

1 2

1 2

2

HDD_STP32

R72

CLK_14M_ICH15
CLK_48M_ICH15

T16PAD

SLP_S3#18,25,27,28,29,33,35,36,40,43,44
SLP_S4#44
SLP_S5#36,44

PM_POK7,33

1 2

DPRSLPVR7,45

ON/OFFBTN#34

PM_RSMRST#33

T28PAD
T30PAD

LID_SW#17,34
LANLINK_STATUS#_SB25

T25PAD

XMIT_OFF27
BT_OFF30
NPCI_RST#31,33

1 2

0_0402_5%@

T29PAD

DMI_RXN07
DMI_RXP07
DMI_TXN07
DMI_TXP07

DMI_RXN17
DMI_RXP17
DMI_TXN17
DMI_TXP17

DMI_RXN27
DMI_RXP27
DMI_TXN27
DMI_TXP27

DMI_RXN37
DMI_RXP37
DMI_TXN37
DMI_TXP37

CLK_PCIE_ICH#15
CLK_PCIE_ICH15

USB20_N030
USB20_P030
USB20_N132
USB20_P132
USB20_N229
USB20_P229
USB20_N329
USB20_P329
USB20_N430
USB20_P430
USB20_N530
USB20_P530
USB20_N635
USB20_P635
USB20_N735
USB20_P735

R1015 need be removed when ICH7M ES2 samples used,

L

but need be stuffed when ICH7M ES1 samples used.

Within 500 mils

+1.5VS

CLK_48M_ICH

12

R637

10_0402_5%@

1

C541

4.7P_0402_50V8C@

2

R633
10K_0402_5%

DOCK_ID35

Title

SizeDocument NumberRev

Date:Sheet of

R601

8.2K_0402_5%

D13

2 1

CH751H-40_SC76

DPRSLPVR

12

R6020_0402_5%@

J16

2 1

PAD-SHORT 2x2m

RP20

USB_OC#3

4 5

USB_OC#0

3 6

USB_OC#1

2 7

USB_OC#2

1 8

10K_1206_8P4R_5%

R638
10K_0402_5%

USB_OC#4

1 2

R644
10K_0402_5%

USB_OC#5

1 2

R642
10K_0402_5%

MXM_CD0#

1 2

R643
100K_0402_5%

MXM_CD1#_R

1 2

9/14

Compal Electronics, Inc.

ICH7-M(3/4)

LA-2821P

12

R640

1

C542

2

12

+3VALW

LOW_BAT#33

R74

10K_0402_5%

R599

100K_0402_5%@

LOM_LOW_PWR25

CABLE_DETECT25,26

1

CLK_14M_ICH

10_0402_5%@

4.7P_0402_50V8C@

12
12

+3VALW

2152Friday, November 25, 2005

+3VL

0.5

5

4

3

2

1

ICH_V5REF_RUN

220U 6.3V M

9/15

C503

+3VS

+1.5VS

0.1U_0402_16V4Z

C132

10U_0805_10V4Z

C543

+1.5VS

+1.5VS_DMIPLL+1.5VS_DMIPLLR

1

2

1

2

1

+

C506

2

0.1U_0402_16V4Z

1

C504

2

0.01U_0402_16V7K

C521

0.1U_0402_16V4Z

1

2

+3VALW

+3VS

1

2

Place closely pin
D28,T28,AD28.

Place closely pin AG5.

Place closely pin AG9.

DD

100_0402_5%

10_0402_5%

CC

BB

R614

R90

12

12

+3VS+5VS

+3VALW+5VALW

21

D15
CH751H-40_SC76

ICH_V5REF_RUN

1

C517

0.1U_0402_16V4Z

2

21

D17
CH751H-40_SC76

ICH_V5REF_SUS

1

C532

0.1U_0402_16V4Z

2

+1.5VS

1

C515

0.1U_0402_16V4Z

2

Place closely pin AG28 within 100mlis.

R584

1 2

0.5_0805_1%

+1.5VS

R585

1 2

0_0805_5%

1

C527

2

0.1U_0402_16V4Z

+3VALW

0.1U_0402_16V4Z

AA

C537

1

2

ICH_V5REF_SUS

0.1U_0402_16V4Z

1

C505

C507

2

0.1U_0402_16V4Z

C508

0.1U_0402_16V4Z

+1.5VS_DMIPLL

+1.5VS

C534

0.1U_0402_16V4Z

+1.5VS

C146

1U_0603_10V4Z

T18PAD
T17PAD

J18

21

PAD-SHORT 2x2m

J17

21

PAD-No SHORT 2x2m

1

2

+3VS

1

2

1

2

1

2

ICH_SUSLAN

ICH_AA2
ICH_Y7

G10

AD17

F6

AA22
AA23
AB22
AB23
AC23
AC24
AC25
AC26
AD26
AD27
AD28

D26
D27
D28
E24
E25
E26
F23
F24
G22
G23
H22
H23
J22
J23
K22
K23
L22

L23
M22
M23
N22
N23

P22

P23
R22
R23
R24
R25
R26

T22

T23

T26

T27

T28
U22
U23

V22

V23
W22
W23

Y22

Y23

B27

AG28

AB7
AC6
AC7
AD6
AE6
AF5
AF6
AG5
AH5

AD2

AH11
AB10

AB9

AC10
AD10
AE10
AF10

AF9
AG9
AH9

E3

C1

AA2

Y7
V5

V1
W2
W7

1

C540

0.1U_0402_16V4Z

2

U10F

V5REF[1]
V5REF[2]
V5REF_Sus
Vcc1_5_B[1]

Vcc1_5_B[2]
Vcc1_5_B[3]
Vcc1_5_B[4]
Vcc1_5_B[5]
Vcc1_5_B[6]
Vcc1_5_B[7]
Vcc1_5_B[8]
Vcc1_5_B[9]
Vcc1_5_B[10]
Vcc1_5_B[11]
Vcc1_5_B[12]
Vcc1_5_B[13]
Vcc1_5_B[14]
Vcc1_5_B[15]
Vcc1_5_B[16]
Vcc1_5_B[17]
Vcc1_5_B[18]
Vcc1_5_B[19]
Vcc1_5_B[20]
Vcc1_5_B[21]
Vcc1_5_B[22]
Vcc1_5_B[23]
Vcc1_5_B[24]
Vcc1_5_B[25]
Vcc1_5_B[26]
Vcc1_5_B[27]
Vcc1_5_B[28]
Vcc1_5_B[29]
Vcc1_5_B[30]
Vcc1_5_B[31]
Vcc1_5_B[32]
Vcc1_5_B[33]
Vcc1_5_B[34]
Vcc1_5_B[35]
Vcc1_5_B[36]
Vcc1_5_B[37]
Vcc1_5_B[38]
Vcc1_5_B[39]
Vcc1_5_B[40]
Vcc1_5_B[41]
Vcc1_5_B[42]
Vcc1_5_B[43]
Vcc1_5_B[44]
Vcc1_5_B[45]
Vcc1_5_B[46]
Vcc1_5_B[47]
Vcc1_5_B[48]
Vcc1_5_B[49]
Vcc1_5_B[50]
Vcc1_5_B[51]
Vcc1_5_B[52]
Vcc1_5_B[53]

Vcc3_3[1]
VccDMIPLL
Vcc1_5_A[1]

Vcc1_5_A[2]
Vcc1_5_A[3]
Vcc1_5_A[4]
Vcc1_5_A[5]
Vcc1_5_A[6]
Vcc1_5_A[7]
Vcc1_5_A[8]
Vcc1_5_A[9]

VccSATAPLL
Vcc3_3[2]
Vcc1_5_A[10]

Vcc1_5_A[11]
Vcc1_5_A[12]
Vcc1_5_A[13]
Vcc1_5_A[14]
Vcc1_5_A[15]
Vcc1_5_A[16]
Vcc1_5_A[17]
Vcc1_5_A[18]

VccSus3_3[19]
VccUSBPLL
VccSus1_05/VccLAN1_05[1]

VccSus1_05/VccLAN1_05[2]
VccSus3_3/VccLAN3_3[1]

VccSus3_3/VccLAN3_3[2]
VccSus3_3/VccLAN3_3[3]
VccSus3_3/VccLAN3_3[4]

ICH7M_B0_BGA652

Vcc1_05[1]
Vcc1_05[2]
Vcc1_05[3]
Vcc1_05[4]
Vcc1_05[5]
Vcc1_05[6]
Vcc1_05[7]
Vcc1_05[8]

Vcc1_05[9]
Vcc1_05[10]
Vcc1_05[11]
Vcc1_05[12]
Vcc1_05[13]
Vcc1_05[14]
Vcc1_05[15]
Vcc1_05[16]
Vcc1_05[17]
Vcc1_05[18]
Vcc1_05[19]
Vcc1_05[20]

Vcc3_3 / VccHDA

VccSus3_3/VccSusHDA

V_CPU_IO[1]
V_CPU_IO[2]
V_CPU_IO[3]

Vcc3_3[3]
Vcc3_3[4]
Vcc3_3[5]
Vcc3_3[6]
Vcc3_3[7]
Vcc3_3[8]

Vcc3_3[9]
Vcc3_3[10]
Vcc3_3[11]

Vcc3_3[12]
Vcc3_3[13]
Vcc3_3[14]
Vcc3_3[15]
Vcc3_3[16]
Vcc3_3[17]
Vcc3_3[18]
Vcc3_3[19]
Vcc3_3[20]
Vcc3_3[21]

VccRTC
VccSus3_3[1]
VccSus3_3[2]

VccSus3_3[3]
VccSus3_3[4]
VccSus3_3[5]
VccSus3_3[6]

VccSus3_3[7]
VccSus3_3[8]
VccSus3_3[9]

VccSus3_3[10]
VccSus3_3[11]
VccSus3_3[12]
VccSus3_3[13]
VccSus3_3[14]
VccSus3_3[15]
VccSus3_3[16]
VccSus3_3[17]
VccSus3_3[18]

Vcc1_5_A[19]
Vcc1_5_A[20]

Vcc1_5_A[21]
Vcc1_5_A[22]
Vcc1_5_A[23]

Vcc1_5_A[24]
Vcc1_5_A[25]

VccSus1_05[1]
VccSus1_05[2]

VccSus1_05[3]

Vcc1_5_A[26]
Vcc1_5_A[27]
Vcc1_5_A[28]
Vcc1_5_A[29]
Vcc1_5_A[30]

L11
L12
L14
L16
L17
L18
M11
M18
P11
P18
T11
T18
U11
U18
V11
V12
V14
V16
V17
V18

U6
R7
AE23

AE26
AH26

AA7
AB12
AB20
AC16
AD13
AD18
AG12
AG15
AG19

A5
B13
B16
B7
C10
D15
F9
G11
G12
G16

W5
P7
A24

C24
D19
D22
G19

K3
K4
K5
K6
L1
L2
L3
L6
L7
M6
M7
N7

AB17
AC17

T7
F17
G17

AB8
AC8

K7
C28

G20
A1

H6
H7
J6
J7

+VCCP

0.1U_0402_16V4Z

1

C519

C513

2

1U_0603_10V4Z

1

C522

2

0.1U_0402_16V4Z

1

C533

0.1U_0402_16V4Z

2

1

C529

0.1U_0402_16V4Z

2

1 2

C5300.1U_0402_16V4Z

ICH_K7
ICH_C28

ICH_G20

1

C516

0.1U_0402_16V4Z

2

1

C131

2

220U 6.3V M

1

C511

0.1U_0402_16V4Z

2

1

C525

2

+1.5VS

+1.5VS

1

+

2

9/15

+3VS

+3VS

1

C535

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

C528

0.1U_0402_16V4Z

2

1

C538

0.1U_0402_16V4Z

2

T19PAD
T13PAD

T15PAD

+3VS

+3VALW

+3VALW

+VCCP

0.1U_0402_16V4Z

0.1U_0402_16V4Z

4.7U_0805_10V4Z

C523

1 2

1 2

C512

1 2

C520

U10E

A4

VSS[0]

A23

VSS[1]

B1

VSS[2]

B8

VSS[3]

B11

VSS[4]

B14

VSS[5]

B17

VSS[6]

B20

VSS[7]

B26

VSS[8]

B28

VSS[9]

C2

VSS[10]

C6

VSS[11]

C27

VSS[12]

D10

VSS[13]

D13

VSS[14]

D18

VSS[15]

D21

VSS[16]

D24

VSS[17]

E1

VSS[18]

E2

VSS[19]

E4

VSS[21]

E8

VSS[22]

+3VS

1

C518

0.1U_0402_16V4Z

2

+RTCVCC

1

1

C536

C531

2

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

E15

VSS[23]

F3

VSS[24]

F4

VSS[25]

F5

VSS[26]

F12

VSS[27]

F27

VSS[28]

F28

VSS[29]

G1

VSS[30]

G2

VSS[31]

G5

VSS[32]

G6

VSS[33]

G9

VSS[34]

G14

VSS[35]

G18

VSS[36]

G21

VSS[37]

G24

VSS[38]

G25

VSS[39]

G26

VSS[40]

H3

VSS[41]

H4

VSS[42]

H5

VSS[43]

H24

VSS[44]

H27

VSS[45]

H28

VSS[46]

J1

VSS[47]

J2

VSS[48]

J5

VSS[49]

J24

VSS[50]

J25

VSS[51]

J26

VSS[52]

K24

VSS[53]

K27

VSS[54]

K28

VSS[55]

L13

VSS[56]

L15

VSS[57]

L24

VSS[58]

L25

VSS[59]

L26

VSS[60]

M3

VSS[61]

M4

VSS[62]

M5

VSS[63]

M12

VSS[64]

M13

VSS[65]

M14

VSS[66]

M15

VSS[67]

M16

VSS[68]

M17

VSS[69]

M24

VSS[70]

M27

VSS[71]

M28

VSS[72]

N1

VSS[73]

N2

VSS[74]

N5

VSS[75]

N6

VSS[76]

N11

VSS[77]

N12

VSS[78]

N13

VSS[79]

N14

VSS[80]

N15

VSS[81]

N16

VSS[82]

N17

VSS[83]

N18

VSS[84]

N24

VSS[85]

N25

VSS[86]

N26

VSS[87]

P3

VSS[88]

P4

VSS[89]

P12

VSS[90]

P13

VSS[91]

P14

VSS[92]

P15

VSS[93]

P16

VSS[94]

P17

VSS[95]

P24

VSS[96]

P27

VSS[97]

ICH7M_B0_BGA652

VSS[98]

VSS[99]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
VSS[159]
VSS[160]
VSS[161]
VSS[162]
VSS[163]
VSS[164]
VSS[165]
VSS[166]
VSS[167]
VSS[168]
VSS[169]
VSS[170]
VSS[171]
VSS[172]
VSS[173]
VSS[174]
VSS[175]
VSS[176]
VSS[177]
VSS[178]
VSS[179]
VSS[180]
VSS[181]
VSS[182]
VSS[183]
VSS[184]
VSS[185]
VSS[186]
VSS[187]
VSS[188]
VSS[189]
VSS[190]
VSS[191]
VSS[192]
VSS[193]
VSS[194]

P28
R1
R11
R12
R13
R14
R15
R16
R17
R18
T6
T12
T13
T14
T15
T16
T17
U4
U12
U13
U14
U15
U16
U17
U24
U25
U26
V2
V13
V15
V24
V27
V28
W6
W24
W25
W26
Y3
Y24
Y27
Y28
AA1
AA24
AA25
AA26
AB4
AB6
AB11
AB14
AB16
AB19
AB21
AB24
AB27
AB28
AC2
AC5
AC9
AC11
AD1
AD3
AD4
AD7
AD8
AD11
AD15
AD19
AD23
AE2
AE4
AE8
AE11
AE13
AE18
AE21
AE24
AE25
AF2
AF4
AF8
AF11
AF27
AF28
AG1
AG3
AG7
AG11
AG14
AG17
AG20
AG25
AH1
AH3
AH7
AH12
AH23
AH27

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/03/102006/03/10

Compal Secret Data

Deciphered Date

Title

SizeDocument NumberRev

2

Date:Sheet of

Compal Electronics, Inc.

ICH7-M(4/4)

LA-2821P

2252Friday, November 25, 2005

1

0.5

A

+3VS_CBPLL

XTPBIAS0
XTPA0+
XTPA0­XTPB0+
XTPB0-

XTPBIAS1

XTPB1+
XTPB1-

+3VS

X_OUT
X_IN

MC_PWRON#
PWR_CTRL_1/SM_R/B#

SD_CD#
MS_CD#
SM_CD#

R175

MSBS_SDCMD_SMWE#
MSD3_SDD3_SMD3
MSD2_SDD2_SMD2
MSD1_SDD1_SMD1
MSD0_SDD0_SMD0

SDCLK_SMRE#
SDCMD_SMALE
SDD0_SMD4
SDD1_SMD5
SDD2_SMD6
SDD3_SMD7
SDWP#_SMCE#

SMCLE
SC_CD#

R117

1 2

0_0402_5%

SC_RST
SC_DATA

SC_OC#
SM_PHYS_WP#/SC_FCB

SM_RB#/SC_RFU

10_0402_5%@

15P_0402_50V8J@

R152

R159
R182

+3VS

R229

1 2

0_0805_5%

R2286.34K_0402_1%

1 2

R230

1 2

4.7K_0402_5%@

22_0402_5%

SC_CLK_R

1 2

R141

1 2

0_0402_5%

R142

1 2

0_0402_5%7611@

R140

1 2

0_0402_5%

1 2

0_0402_5%@

1 2

0_0402_5%7612@

1 2

0_0402_5%7611@

T18
T19

R13
V14

W14

V13

W13
W17

V16

W16

V15

W15

P17

R18
R19

R1430_0402_5%

P12

SC_RFU

SC_FCB
SM_PHYS_WP#

XD_CD#/SM_PHYS_WP#
SM_CD#XD_CD#

PCI_AD[0..31]19

PCI_CBE#[0..3]19

11

C242

10P_0402_50V8J

22

33

C241

10P_0402_50V8J

PCI_AD[0..31]
PCI_CBE#[0..3]

1 2

1M_0402_5%@

1 2

24.576MHZ_16P_1BG24576CK1A

9/10

+3VS

9/10

X_IN

12

R237

Y2

X_OUT

MSCLK_SDCLK_SMELWP#

SC_CD#24

SC_CLK24

SC_RST24

+SC_PWR

SC_DATA24

R12910K_0402_5%@
R13010K_0402_5%@

1 2

SC_CLK

CLK_PCI_PCM

12

R149

1

C168

2

SM_RB#/SC_RFU

SM_PHYS_WP#/SC_FCB

44

A

B

1

1

1

C227

C219

2

10U_0805_10V4Z

U16B

R0
R1

TPBIAS0
TPA0P
TPA0N
TPB0P
TPB0N

TPBIAS1
TPA1P
TPA1N
TPB1P
TPB1N

C230

2

2

1U_0603_10V4Z

0.01U_0402_16V7K

PHY_TEST_MA

XO
XI

C8

MC_PWR_CTRL_0

F8

MC_PWR_CTRL_1/SM_R/B#

E9

SD_CD#

A8

MS_CD#

B8

SM_CD#

A7

MS_CLK/SD_CLK/SM_EL_WP#

E8

MS_BS/SD_CMD/SM_WE#

B6

MS_DATA3/SD_DAT3/SM_D3

A6

MS_DATA2/SD_DAT2/SM_D2

C7

MS_DATA1/SD_DAT1/SM_D1

B7

MS_SDIO(DATA0)/SD_DAT0/SM_D0

A4

SD_CLK/SM_RE#/SC_GPIO1

C5

SD_CMD/SM_ALE/SC_GPIO2

C6

SD_DAT0/SM_D4/SC_GPIO6

A5

SD_DAT1/SM_D5/SC_GPIO5

B5

SD_DAT2/SM_D6/SC_GPIO4

E6

SD_DAT3/SM_D7/SC_GPIO3

E7

SD_WP/SM_CE#

B4

SM_CLE/SC_GPIO0

F3

SC_CD#

E2

SC_CLK

F5

SC_RST

G6

SC_VCC_5V

E1

SC_DATA

F2

SC_OC#

G5

SC_PWR_CTRL

E3

SC_FCB

D1

SC_RFU

TEST0

R131

1 2

0_0402_5%7612@

R153

1 2

0_0402_5%7612@

B

C

+3VS_CBVCCP

0.1U_0402_16V4Z

1

C174

1

C2341U_0603_10V4Z

2

2

1

2

P13

AVDD_33

C169 1U_0603_10V4Z

P14

U15

AVDD_33

AVDD_33

U19

P15

K19

W8

VCCPP1VCCP

VR_PORTK1VR_PORT

VDDPLL_33

VDDPLL_15

DEVSEL#

PCI7612/7412

RI_OUT#/PME#

SUSPEND#

SPKROUT

VSSPLL

AGND

AGND

AGND

R14

U13

U14

PWR_CTRL_1/SM_R/B#SM_RB#

PCI7612ZHK_PBGA257

R17

+VDDPLL

SC_RFU24

SC_FCB24

XD_CD#/SM_PHYS_WP#24

+3VS

R173

1 2

0_0805_5%

1

C185

0.1U_0402_16V4Z

2

L12

1 2

CHB1608U301_0603

12

C2320.1U_0402_16V4Z

Keep +VDD_PLL33/+VDDPLL33/+VDD_PLL

L

/+VDDPLL at least 10 mils

PCI_AD31

M1

AD31
AD30
AD29
AD28
AD27
AD26
AD25
AD24
AD23
AD22
AD21
AD20
AD19
AD18
AD17
AD16
AD15
AD14
AD13
AD12
AD11
AD10

C/BE3#
C/BE2#
C/BE1#
C/BE0#

FRAME#

TRDY#
IRDY#
STOP#

IDSEL
PERR#
SERR#

REQ#

GNT#
PCLK

PRST#

GRST#

MFUNC0
MFUNC1
MFUNC2
MFUNC3
MFUNC4
MFUNC5
MFUNC6

VR_EN#

PCI_AD30

M2

PCI_AD29

M3

PCI_AD28

M6

PCI_AD27

M5

PCI_AD26

N1

PCI_AD25

N2

PCI_AD24

N3

PCI_AD23

P3

PCI_AD22

R1

PCI_AD21

R2

PCI_AD20

P5

PCI_AD19

R3

PCI_AD18

T1

PCI_AD17

T2

PCI_AD16

W4

PCI_AD15

W7

PCI_AD14

R8

PCI_AD13

U8

PCI_AD12

V8

PCI_AD11

W9

PCI_AD10

V9

PCI_AD9

U9

AD9

PCI_AD8

R9

AD8

PCI_AD7

V10

AD7

PCI_AD6

U10

AD6

PCI_AD5

R10

AD5

PCI_AD4

W11

AD4

PCI_AD3

V11

AD3

PCI_AD2

U11

AD2

PCI_AD1

P11

AD1

PCI_AD0

R11

AD0

PCI_CBE#3

P2

PCI_CBE#2

U5

PCI_CBE#1

V7

PCI_CBE#0

W10
U7

PAR

R6
W5
V5
V6
U6

R161

N5
R7
W6
L3
L2

CLK_PCI_PCM

L1

PRST#

K3

GRST#

K5

CB_PME#

L5

R151

J5

43K_0402_5%

PCM_SPK

H3
G1

H5
H2
H1
J1

FM_LED#

J2
J3

G2

SCL

G3

SDA

K2

PCM_SPK

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

+VDDPLL33+VDD_PLL33
+VDDPLL+VDD_PLL

100_0402_5%

C

+3VS

10K_0402_5%@

CB_PME#

PCI_AD22

12

0_0402_5%

R150

1 2

R136

1 2

0_0402_5%@

+3VS

12
12
12
12
12

12
12

12

R231

1 2

43K_0402_5%

2005/03/102006/03/10

+3VS

12

R148

2N7002_SOT23@

R1450_0402_5%
R1330_0402_5%
R1320_0402_5%
R1440_0402_5%
R1370_0402_5%

R146220_0402_5%
R134220_0402_5%

R135220_0402_5%

PAD-No SHORT 2x2m

Q20

0.1U_0402_16V4Z

PCI_PAR19
PCI_FRAME#19
PCI_TRDY#19
PCI_IRDY#19

PCI_STOP#19
PCI_DEVSEL#19

PCI_PERR#19
PCI_SERR#19,33
PCI_REQ2#19
PCI_GNT2#19

CLK_PCI_PCM15

PCI_RST#19,24
PLT_RST#7,19,20,21,25,27,32,33

PCM_SPK28

PCI_PIRQC#19
PCI_PIRQD#19
PCI_PIRQG#19

SIRQ21,31,32,33

PCI_PIRQE#19

PM_CLKRUN#21,31,32,33

MC_PWRON#

+VCC_MS +VCC_SD

J6

2 1

100K_0402_5%

SDWP#_SMCE#
SM_RB#
MSBS_SDCMD_SMWE#
SDCLK_SMRE#

G

2

13

D

S

R116

MSCLK_SDCLK_SMELWP#

1 2

33_0402_5%7611@

MSBS_SDCMD_SMWE#

+VCC_SM_XD

1

C164

2

U12

1

GND

2

IN

3

IN

4

EN#

TPS2061IDGN_MSOP8~N
C15210U_0805_10V4Z
C1540.01U_0402_16V7K

Compal Secret Data

Deciphered Date

2 1

22K_0402_5%

R125

R114

1 2

PCI_PME#19

MSD0_SDD0_SMD0
MSD1_SDD1_SMD1
MSD2_SDD2_SMD2
MSD3_SDD3_SMD3
SDD0_SMD4
SDD1_SMD5
SDD2_SMD6
SDD3_SMD7

SM_PHYS_WP#
SDCMD_SMALE

SM_CD#
SM_RB#

SDCLK_SMRE#
SDWP#_SMCE#
SM_CD#

SMCLE

OUT
OUT
OUT
OC#

12
12

D

J7

PAD-SHORT 2x2m

R115

1 2

100K_0402_5%

34
33
32
31
21
22
23
24

35
43
36
37

25

3
29
26
27
28
30

2
38

R124

1 2

0_0402_5%

8
7
6
5

D

100K_0402_5%

R126

9/6

1 2

1 2

JP24

SM-D0 / XD-D0
SM-D1 / XD-D1
SM-D2 / XD-D2
SM-D3 / XD-D3
SM-D4 / XD-D4
SM-D5 / XD-D5
SM-D6 / XD-D6
SM-D7 / XD-D7

SM_WP-IN / XD_WP-IN
SM-WP-SW
#SM_-WE / XD_-WE
#SM-ALE / XD-ALE

SM-LVD
SM-CD-SW
SM_-VCC / XD_-VCC
#SM_R/-B / XD_R/-B
#SM_-RE / XD_-RE
#SM_-CE / XD_-CE
#SM_-CD
SM-CD-COM
SM-CLE / XD-CLE

TAITW_R007-010-N3

GRST#PRST#

+3VS+VCC_MS+3VS

R91
10K_0402_5%

1 2

E

+VCC_MS +VCC_SD +VCC_MS +VCC_SM_XD

SI2301BDS_SOT23
Q21

S

D

13

G

1

2

C165

2

10U_0805_10V4Z

+3VS +3VS

R164

G

G

Q30

SD-WP-SW

SD-CD-SW

SD-CD-COM

MS-DATA0
MS-DATA1
MS-DATA2
MS-DATA3

XTPBIAS0
XTPB0­XTPB0+
XTPA0­XTPA0+

SD-DAT3
SD-DAT2
SD-DAT1
SD-DAT0

MS-SCLK

2

1 2

S

13

D

Q22
2N7002_SOT23

S

2 1

D21RB751V_SOD323@

2 1

D22RB751V_SOD323@

11
12
6
7
5
10

SD-CMD

8

SD_CLK

9

SD-VCC

4

N/C

42
41

15
14
16
18
19
17

MS-INS

13

MS-BS

20

MS-VCC

40

XD-VCC

39

XD-CD

1

GND

44

GND

56.2_0603_1%

R195

R187

56.2_0603_1%

C189

270P_0603_50V8J

13

D

10K_0402_5%

MC_PWRON#

FM_LED#

2

2N7002_SOT23@

5 IN 1 CONN

L
L

XTPBIAS1
XTPB1+
XTPB1-

R193

1K_0402_5%

Title

SizeDocument NumberRev

Date:Sheet of

Compal Electronics, Inc.

TI PCI7612 PCI/CardReader

LA-2821P

SI2301BDS_SOT23
Q28

S

G

R128
47K_0402_5% @

1 2

SD_DAT3
SD_DAT2
SD_DAT1
SD_DAT0
SDWP#_SMCE#

SD_CD#

MSD0_SDD0_SMD0
MSD1_SDD1_SMD1
MSD2_SDD2_SMD2
MSD3_SDD3_SMD3
MSCLK_SDCLK_SMELWP#
MS_CD#
MSBS_SDCMD_SMWE#

XD_CD#

12

R201

56.2_0603_1%

2

+3VS

R127
10K_0402_5%

1 2

SD_CD#MS_CD#

G

2

S

Q27
2N7002_SOT23

SD_CD#
SM_CD#

1 2
1 2
1 2
1 2

1 2
1 2

Place the parts close to JP41

12

1

C207
1U_0603_10V4Z

2

12

12

R183

56.2_0603_1%

12

1

R186

5.1K_0603_1%

2

CLOSE TO CHIP

CLOSE TO CHIP

1K_0402_5%

1

R200

C212
1U_0603_10V4Z

2

1 2

1 2

E

D

13

1

C178

2

10U_0805_10V4Z

13

D

MSD3_SDD3_SMD3

R1220_0402_5%

MSD2_SDD2_SMD2

R1230_0402_5%
R1190_0402_5%

MSD1_SDD1_SMD1
MSD0_SDD0_SMD0

R1200_0402_5%

MSBS_SDCMD_SMWE#

R1210_0402_5%

MSCLK_SDCLK_SMELWP#

R1180_0402_5%

+VCC_MS+VCC_SM_XD

AMP_440168-2

2352Friday, November 25, 2005

R154
47K_0402_5% @

1 2

R165
10K_0402_5%

1 2

+VCC_SD

JP17

1
2
3
4

L

0.5

A B C D

U19

3

DATA

4

CLOCK

5

LATCH

12

RESET#

15

OC#

21

SHDN#

8

AVPP

19

BVPP

9

AVCC

10

AVCC

17

BVCC

18

BVCC

TPS2224ADBR_HTSSOP24

JP23

1

GND

2

GND

3

CD2#

4

WP

5

D10

6

D2

7

D9

8

D1

9

GND

10

D8

11

D0

12

STSCHG#

13

A0

14

SPKR#

15

A1

16

REG#

17

GND

18

A2

19

INPACK#

20

A3

21

WAIT#

22

A4

23

RESET

24

A5

25

GND

26

VS2#

27

A6

28

A25

29

A7

30

A24

31

A12

32

A23

33

GND

34

A15

35

A22

36

A16

37

A52/A18/VCCP

38

NONE

39

A51/A17/VCC

40

READY

41

A21

42

WE#

43

GND

44

A20

45

A14

46

A19

47

A13

48

A18

49

A8

50

A17

51

GND

52

A9

53

IOWR#

54

A11

55

IORD#

56

OE#

57

VS1#

58

A10

59

GND

60

CE2#

61

CE1#

62

D15

63

D7

64

D14

65

D6

66

D13

67

GND

68

D5

69

D12

70

D4

71

D11

72

D3

73

CD1#

74

GND

75

GND

TYCO_1123088-1_LT

20

12V

7

12V

14

3.3V

13

3.3V

GND

5V
5V
5V

NC
NC
NC
NC

+5VS

24
2
1

11

23
22
16
6

1

C258

2

9/8

76

NONE

77

NONE

78

NONE

79

NONE

80

NONE

81

NONE

82

NONE

83

NONE

84

GND

85

NONE

86

NONE

87

NONE

88

NONE

89

NONE

90

NONE

91

NONE

92

GND

93

NONE

94

NONE

95

NONE

96

NONE
NONE

NONE

GND

VCC
NONE
NONE
NONE
NONE

DET2

GND

NONE

GND
NONE
NONE

DET1
RFU4

NONE

GND

RFU8
NONE
NONE
NONE
NONE
NONE
NONE

GND
NONE
NONE
NONE
NONE
NONE
NONE
NONE

GND
NONE
NONE
NONE
NONE
NONE
NONE
NONE

GND
NONE
NONE
NONE
NONE
NONE
NONE

GND

GND

RST

VPP
CLK

SC_DATA

97

I/O

98
99
100
101
102
103
104
105

SC_RST

106
107
108
109

SC_CLK

110
111
112
113
114

SC_CD#

115

SC_FCB

116
117
118

SC_RFU

119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150

C228

0.1U_0402_16V4Z

RSVD/D2
RSVD/A18
RSVD/D14

1

C202

2

NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC

+S1_VCC+3VS

A2
A17
A18
B1

+S1_VCC

B2
B3
B17
B18
B19
C1
C2
C3
C16
C17
C18
C19
D2
D3

+S1_VPP

D17
D18
N14
P18
T3
T17
U1
U2
U3
U4
U12
U16
U17
U18
V1
V2
V3
V4
V12
V17
V18
V19
W2
W3
W12
W18
E5

S1_D2

B10

S1_A18

H17

S1_D14

M19

R160

C4

R166

XD_CD#/SM_PHYS_WP#

A3

CB_DAT

B9

CB_CLK

A9

CB_LATCH

C9

R208

10K_0402_5%@

C199

100P_0402_50V8J@

Near to PCMCIA slot.

1

C211
10U_0805_10V4Z

2

1

C201
10U_0805_10V4Z

2

S1_CD1#

S1_CD2#

43K_0402_5%

1 2

43K_0402_5%@

1 2

+SC_PWR

12

1

2

100P_0402_50V8J

100P_0402_50V8J

1

C218

0.1U_0402_16V4Z

2

12

R190

22K_0402_5%@

C231

1 2

C197

1 2

1

C210

0.1U_0402_16V4Z

2

1

C200

0.1U_0402_16V4Z

2

+3VS

XD_CD#/SM_PHYS_WP#23

CB_CLK33

PCI_RST#19,23

+S1_VPP
+S1_VCC

12

R176

1

C184

470P_0402_50V7K@

22K_0402_5%@

2

1

C179

C182

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z
U16A

C10
A10
F11
E11
C11
B13
C13
A14
B14
B15
E14
A16
D19
E17
F15
H19
J17
J15
J18
K15
K17
K18
L15
L18

L19
M17
M18

N19
M15

N17

N18

P19

E13

E18

H18

L17

H14

E19

F17

G18

F19

H15

G19

C12

C14

G17

A12

A11

F18

E12

R12

F1
G15
B12
C15

N15
B11
A13
B16

E10

1

1

1

C203

C229

2

CAD31/D10
CAD30/D9
CAD29/D1
CAD28/D8
CAD27/D0
CAD26/A0
CAD25/A1
CAD24/A2
CAD23/A3
CAD22/A4
CAD21/A5
CAD20/A6
CAD19/A25
CAD18/A7
CAD17/A24
CAD16/A17
CAD15/IOWR#
CAD14/A9
CAD13/IORD#
CAD12/A11
CAD11/OE#
CAD10/CE2#
CAD9/A10
CAD8/D15
CAD7/D7
CAD6/D13
CAD5/D6
CAD4/D12
CAD3/D5
CAD2/D11
CAD1/D4
CAD0/D3

CC/BE3#/REG#
CC/BE2#/A12
CC/BE1#/A8
CC/BE0#/CE1#

CPAR/A13
CFRAME#/A23
CIRDY#/A15
CSTOP#/A20
CDEVSEL#/A21
CBLOCK#/A19
CPERR#/A14
CSERR#/WAIT#
CREQ#/INPACK#
CGNT#/WE#
CSTSCHG/BVD1(STSCHG#/RI#)
CCLKRUN#/WP(IOIS16#)
CCLK/A16
CINT#/READY(IREQ#)
CPS
CLK_48
CTRDY#/A22
CAUDIO/BVD2(SPKR#)
CRST#/RESET

CCD1#/CD1#
CCD2#/CD2#
CVS1/VS1#
CVS2/VS2#

C235

2

2

10U_0805_10V4Z

0.1U_0402_16V4Z

A_USB_EN#

GNDF7GND

F10

F12

F14

J14

L14

P10

VCCF6VCCF9VCC

VCC

VCCJ6VCC

VCCL6VCC

VCCP6VCCP8VCC

PCI7612/7412

GND

GND

GNDH6GNDK6GND

GND

GNDN6GNDP7GND

PCI7612ZHK_PBGA257

F13

P9

K14

G14

M14

SC_CLK SC_DATA SC_RST

56P_0402_50V8J@

A15

J19

VCCB

VCCB

XD_CD#/SM_PHYS_WP#

+SC_PWR

1

C180

2

1

2

0.1U_0402_16V4Z

RSVD/VD0/VCCD1#

DATA/VD2/VPPD1

CLOCK/VD1/VCCD0#

LATCH/VD3/VPPD0

12

R168

22K_0402_5%@

12

R169

22K_0402_5%@

R227

1

C195

2

0.1U_0402_16V4Z

S1_D10
S1_D9
S1_D1
S1_D8
S1_D0
S1_A0
S1_A1
S1_A2
S1_A3
S1_A4
S1_A5
S1_A6
S1_A25
S1_A7
S1_A24
S1_A17
S1_IOWR#
S1_A9
S1_IORD#
S1_A11
S1_OE#
S1_CE2#
S1_A10
S1_D15
S1_D7
S1_D13
S1_D6
S1_D12
S1_D5
S1_D11
S1_D4
S1_D3

S1_REG#
S1_A12
S1_A8
S1_CE1#

S1_A13
S1_A23
S1_A15
S1_A20
S1_A21
S1_A19
S1_A14
S1_WAIT#
S1_INPACK#
S1_WE#
S1_BVD1
S1_WP
S1_A16S1_A16_C
S1_RDY#
CPS

CLK_48M_CB

S1_A22
S1_BVD2
S1_RST

S1_CD1#
S1_CD2#
S1_VS1
S1_VS2

1

C187

2

0.1U_0402_16V4Z

1

C170

2

0.1U_0402_16V4Z

1

2

0.1U_0402_16V4Z

11

22

1 2

+3VS

R189

1 2

4.7K_0402_5%

CLK_48M_CB

12

R147

33

10_0402_5%@

2

C166

10P_0402_50V8J@

1

44

33_0402_5%

CLK_48M_CB15

CPS

+S1_VPP

+SC_PWR

+S1_VCC

S1_CD2#
S1_WP
S1_D10
S1_D2
S1_D9
S1_D1

S1_D8
S1_D0
S1_BVD1
S1_A0
S1_BVD2
S1_A1
S1_REG#

S1_A2
S1_INPACK#
S1_A3
S1_WAIT#
S1_A4
S1_RST
S1_A5

S1_VS2
S1_A6
S1_A25
S1_A7
S1_A24
S1_A12
S1_A23

S1_A15
S1_A22
S1_A16_C

S1_RDY#
S1_A21
S1_WE#

S1_A20
S1_A14
S1_A19
S1_A13
S1_A18
S1_A8
S1_A17

S1_A9
S1_IOWR#
S1_A11
S1_IORD#
S1_OE#
S1_VS1
S1_A10

S1_CE2#
S1_CE1#
S1_D15
S1_D7
S1_D14
S1_D6
S1_D13

S1_D5
S1_D12
S1_D4
S1_D11
S1_D3
S1_CD1#

CB_DAT
CB_CLK
CB_LATCH
PCI_RST#

E

+3VS

1

C233

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

SC_DATA23

+SC_PWR

SC_RST23

SC_CLK23

SC_CD#23
SC_FCB23

SC_RFU23

Place the parts close to JP9

L

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2005/03/102006/03/10

Compal Secret Data

Deciphered Date

D

Title

SizeDocument NumberRev

Date:Sheet of

Compal Electronics, Inc.

TI PCI7612 CB/SmartCard

LA-2821P

2452Friday, November 25, 2005

E

0.5

5 4 3 2

1

PLT_RST#7,19,20,21,23,27,32,33

SI2301BDS_SOT23

S

12

Q57

G

2

1

D

1 3

C544

2

0.1U_0402_16V7K@

NIC_PD

ADP_PRES18,33,40,41,42,47

SLP_S3#18,21,27,28,29,33,35,36,40,43,44

R658

0_0402_5%@

NIC_PD

CLKREQA#15,18

220K_0402_5%

R329

11/21

2N7002_SOT23

10K_0402_5%

LOM_WAKE#

12

Compal Secret Data

V_3P3_LAN

R3661K_0402_5%@

1 2

R3371K_0402_5%@

1 2

DD

9/7

R391

1 2

10K_0402_5%

5751_GPIO1
ICH_LAN_SMBCLK

ICH_LAN_SMBDATA
5751_EECLK

5751_EEDAT

11/23

V_3P3_LAN

+3VALW

CC

LANLINK_STATUS#_SB21

BB

AA

R678

10K_0402_5%

LANLINK_STATUS#26,35

LAN_ACT#26,35

R347200_0402_1%

Y4

1 2

25MHZ_16P_XSL025000FK1H

2

C331
27P_0402_50V8J

1

0.1U_0402_16V4Z

U28

1

A0

2

A1

3

NC

4

GND

AT24C256_SO8

+3VS

R334

2.2K_0402_5%@

ICH_SMBDATA

V_3P3_LAN

10K_0402_5%

12

12

R663

R673

2

G

10K_0402_5%

1 3

DS

Q782N7002_SOT23

R680

1 2

0_0402_5%@

V_3P3_LAN

12

2

C334
27P_0402_50V8J

1

C376

12

8

VCC

7

WP

6

SCL

5

SDA

12

12

R361

2.2K_0402_5%@

S

G

2

R335

12

4.7K_0402_5%

LANLINK_STATUS#

LANLINK_STATUS#

LAN_ACT#

R679

1 2

10K_0402_5%

XTALO

XTALI

R404

1K_0402_5%

5751_GPIO1
5751_EECLK
5751_EEDAT

2N7002_SOT23@
Q60

D

13

D

S

13

Q65

2N7002_SOT23@

G

2

+5VS

V_3P3_LAN

12

12

12

R405

1K_0402_5%

ICH_LAN_SMBDATA
ICH_LAN_SMBCLKICH_SMBCLK

ICH_LAN_SMBCLK
ICH_LAN_SMBDATA

U25A

J10

GPIO0_TST_CLKOUT

J12

GPIO1

D9

SMB_CLK

D8

SMB_DATA

H10

EECLK

J11

EEDATA

F11

SI

E10

SO

D10

SCLK

D11

CS#

H2

PWR_IND#

J2

ATTN_IND#

B3

ATTN_BTTN#

B10

LINKLED#

C10

SPD100LED#

B11

SPD1000LED#

C9

TRAFFICLED#

N10

XTALO

M10

XTALI

BCM5753KFBG C0_FPBGA196~D

V_3P3_LAN

12

R406

1K_0402_5%

5/16

R3670_0402_5%

1 2

R3360_0402_5%

1 2

BCM5753

Media

Misc

LOW_PWR

Power

Control

REGSUP12
REGCTL12

REGSEN12
REGOUT25
REGSUP25

Control

Regulator

Hot Plug

Support

LED

Clock

PCIE_TXDN
PCIE_TXDP
PCIE_RXDN
PCIE_RXDP

REFCLK-

REFCLK+

PCI-ETEST

REFCLK_SEL

PCIE_TST

Bias

Layout Notice : No high
speed signal should be
routed near RDAC or on
adjacent layer to RDAC

11/21

NIC_PD_N

ICH_SMBCLK
ICH_SMBDATA

TRD3+

TRD3-

TRD2+

TRD2-

TRD1+

TRD1-

TRD0+

TRD0-

WAKE#

PERST#

TCK

TDI
TDO
TMS

TRST#

RDAC

D341N4148_SOD80

R662121K_0402_1%

C12
C13
D12
D13
E12
E13
F12
F13

J5

L13
K12
K13

N13
M13

N4
M4
M8
N8
B5

M6
N6
C4

D7
C2

C6
G4
C5
F4
E5

B9

1 2
1 2

0.1U_0402_16V7K

ICH_SMBCLK4,13,14,15,18,21,27
ICH_SMBDATA4,13,14,15,18,21,27

LAN_TX3+
LAN_TX3­LAN_TX2+
LAN_TX2­LAN_TX1+
LAN_TX1­LAN_TX0+
LAN_TX0-

LOM_LOW_PWR

REGSUP12
VAUX_1.2_CTL

PCIE_C_RXN1
PCIE_C_RXP1

LOM_WAKE#
CLK_PCIE_LOM#
CLK_PCIE_LOM

PLT_RST#_LAN

C342

0.1U_0402_16V4Z
C344

0.1U_0402_16V4Z

12

R3284.7K_0402_5%

11/15

11/18

R326

4.7K_0402_5%@

1 2

R373

1.2K_0402_1%

11/18

1 2

R660

0_0402_5%@

2

1

C550

2

LAN_TX3+26
LAN_TX3-26
LAN_TX2+26
LAN_TX2-26
LAN_TX1+26
LAN_TX1-26
LAN_TX0+26
LAN_TX0-26

R407

1 2

4.7K_0402_5%

9/13

V_1P2_LAN
V_2P5_LAN
V_3P3_LAN

1 2
1 2

V_3P3_LAN

12

R646
10K_0402_5%

V_3P3_LAN +3VS

12

5

3

PCIE_RXN121

PCIE_RXP121
PCIE_TXN121
PCIE_TXP121

12

11/18

R659

0_0402_5%

P

R661

O4I

1

NC

G

U38
SN74LVC1G17DBVR_SOT23-5

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

0_0402_5%@

PLT_RST#_LAN

CLK_PCIE_LOM#15
CLK_PCIE_LOM15

12

R364

4.7K_0402_5%

1 2

0_0402_5%

R330

9/7

NIC_PD26

11/14

2005/03/102006/03/10

+3VALW

12

D36

2 1

RB751V_SOD323 @

12

D

R21

0_0402_5%@

S

13

D

Q5

2

G

S

2

G

V_3P3_LAN

12

R345

1 3

D

Q107

BSS84_SOT23@

R6540_0402_5%

1 2

NIC_PD_N

R656

1 2

13

D

Q108

2

BSS84_SOT23@

G

S

R6550_0402_5%@

1 2

R6570_0402_5%@

2

G

1 2

R64810K_0402_5%@

1 2

13

D

Q76

2N7002_SOT23@

S

LOM_LOW_PWR21

NIC_PD#

CKT Notice : CABLE IN, CABLE_DETECT=0

Deciphered Date

J10

12

SI2301BDS_SOT23

R20

4.7K_0402_5%
R19

47K_0402_5%

13

Q3

LP_EN#

2

G

2N7002_SOT23

13

D

Q4
2N7002_SOT23

S

11/21

NIC_PD

2

G

S

100K_0402_5%@

CABLE OUT, CABLE_DETECT=1

CABLE_DETECT21,26

2

21

PAD-NO SHORT 2x2m

S

D

13

Q2

G

2

12

4.7U_0805_10V4Z

LOM_PCIE_WAKE#21

+3VS V_3P3_LAN

11/21

LOM_LOW_PWR

SN74LVC1G17DBVR_SOT23-5@

0.1U_0402_16V4Z

Layout Notice : Place as close
chip as possible.

2

2

2

C357

C308

C366

1

4.7U_0805_10V4Z

Must having maximized

L

copper under pin 2 & 4 of Q13

V_3P3_LAN

C304

V_3P3_LAN

U27

O4I

1

NC

+3VALW

CABLE_DETECT

C400

1

1

0.1U_0402_16V4Z

0.1U_0402_16V4Z

REGSUP12

2

2

C303

0.1U_0402_16V4Z

1

1

11/21

C379

1 2

0.1U_0402_16V4Z@

5

P

2

G

3

1

C396

0.1U_0402_16V4Z@

2

12

R425
10K_0402_5%

R426

1 2

0_0402_5%@

1

2

Title

SizeDocument NumberRev

Date:Sheet of

V_3P3_LAN

2

2

C358

C307

1

1

VAUX_1.2_CTL

0.1U_0402_16V4Z

1 2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

BCP69_SOT223
Q54

3

1

0.1U_0402_16V4Z

V_3P3_LAN

C306

4.7U_0805_10V4Z

Place close U6 pin M13

L

V_2P5_LAN

2

C352

1

Place close U6 pin N13

L

R416

100K_0402_5%@

13

D

S

4
2

2

C309

1

2

2

1

1

10U_1206_6.3V6M@

1

C364

2

11/18

R667

10K_0402_5%@

R424

10K_0402_5%

R668

1 2

0_0402_5%

LP_EN#

2

G

Q66
2N7002_SOT23

V_1P2_LAN

1

C300
10U_0805_6.3V6M

2

C299

0.1U_0402_16V4Z

1

+

C372
68U_B2_4VM

2

V_3P3_LAN

12

12

NIC_PD_N

Compal Electronics, Inc.

BCM5753M

LA-2821P

2552Friday, November 25, 2005

1

+3VS

LP_EN#21

0.5

5

T22

LAN_TX0-

R672

V_2P5_LAN

DD

CC

1 2

0_0603_5%

C348

0.1U_0402_16V7K

11/22

C345

0.1U_0402_16V7K

C346

0.1U_0402_16V7K

C347

0.1U_0402_16V7K

12

12

12

12

12

TD4-

LAN_TX0+

11

TRM_CT
LAN_TX1-

LAN_TX1+
TRM_CT
LAN_TX2-

LAN_TX2+
TRM_CT
LAN_TX3-

LAN_TX3+
TRM_CT

TD4+

10

TCT4

9

TD3-

8

TD3+

7

TCT3

6

TD2-

5

TD21+

4

TCT2

3

TD1-

2

TD1+

1

TCT1

24HST1041A-3B_24P

C3630.1U_0402_16V4Z

1 2

C3620.1U_0402_16V4Z

1 2

C3610.1U_0402_16V4Z

1 2

C3600.1U_0402_16V4Z

1 2

Layout Notice : Place
termination as close as
BCM5753M as possible

1:1

1:1

1:1

1:1

R38949.9_0402_1%

1 2

R38849.9_0402_1%

1 2

R38749.9_0402_1%

1 2

R38649.9_0402_1%

1 2

R38549.9_0402_1%

1 2

R38449.9_0402_1%

1 2

R38349.9_0402_1%

1 2

R38249.9_0402_1%

1 2

To RJ-45 CONN.

V_3P3_LAN_LED

CABLE_DETECT21,25

LAN_ACT#
LANLINK_STATUS#

MDO3+35
MDO3-35
MDO2+35
MDO2-35
MDO1+35
MDO1-35
MDO0+35
MDO0-35

LAN_ACT#25,35

LANLINK_STATUS#25,35

BB

AA

Keep JP5.1/2/3 at least 10mils

L

1 2
1 2

R12150_0402_5%

MDO3+
MDO3­MDO2+
MDO2­MDO1+
MDO1­MDO0+
MDO0-

CABLE_DETECT

0.1U_0402_16V4Z

100K_0402_5%

PREP#21,35

1

C10

2

V_3P3_LAN V_3P3_LAN_LED

S

12

G

R380

2

G

R13150_0402_5%

LANLINK_STATUS#_R

D

13

Q64
FDN338P_SOT23

2

13

D

Q63

S

2N7002_SOT23

LAN_ACT#_R

MX4-

MX4+
MCT4

MX3-

MX3+
MCT3

MX2-

MX2+
MCT2

MX1-

MX1+
MCT1

4

13

14
15
16

17
18
19

20
21
22

23
24

LAN_TX0­LAN_TX0+
LAN_TX1­LAN_TX1+
LAN_TX2­LAN_TX2+
LAN_TX3­LAN_TX3+

JP4

1
2
3
4
5
6
7
8

9
10
11
12
13
14

ACES_87212-1400

MDO0-

MDO0+
MCT0
MDO1-

MDO1+
MCT1
MDO2-

MDO2+
MCT2
MDO3-

MDO3+
MCT3

1
2
3
4
5
6
7
8
9
10
11
12
13
14

R323

75_0402_1%

R318

75_0402_1%

R322

75_0402_1%

R321

75_0402_1%

LAN_TX0-25
LAN_TX0+25
LAN_TX1-25
LAN_TX1+25
LAN_TX2-25
LAN_TX2+25
LAN_TX3-25
LAN_TX3+25

12

9/10

C301

12

1 2

1000P_1808_3KV7K

12

C302

1 2

12

1000P_1808_3KV7K

3

+3VS

12

NIC_PD25

2

V_2P5_LAN

V_1P2_LAN

BLM11A601S_0603

BLM11A601S_0603

BLM11A601S_0603

BLM11A601S_0603

VMAINPRSNT VMAINPRSNT_R

R6530_0402_5%

Layout Notice : Filter place as close
chip as possible.

R393

12

0_0603_5%

0.1U_0402_16V4Z

R376

12

0_0603_5%

0.1U_0402_16V4Z

R392

12

0_0603_5%

0.1U_0402_16V4Z

L17

12

2

C370

4.7U_0805_10V4Z

4.7U_0805_10V4Z

4.7U_0805_10V4Z

4.7U_0805_10V4Z

1

L18

12

2

C369

1

L10

L15

12

2

C36

1

12

1

C313

2

1 3

Q106

1 2

2

C353

1

2

C340

1

2

C356

1

2

1

2

1

2

1

2

1

G

D

S

BSS84_SOT23

@

11/14

XTALVDD

AVDD1

AVDD2

AVDDL

C355

0.1U_0402_16V4Z

GPHY_PLLVDD

C354

0.1U_0402_16V4Z

PCIE_PLLVDD

C39

0.1U_0402_16V4Z

PCIE_SDS_VDD

C321

0.1U_0402_16V4Z

R325
10K_0402_5%

V_3P3_LAN

PCIE_SDS_VDD

4.7K_0402_5%@

T20

PAD

T59 , T60 place together

L

V_3P3_LAN

R3274.7K_0402_5%@

R164.7K_0402_5%@

R3744.7K_0402_5%@

2

V_2P5_LAN V_1P2_LAN

0.1U_0402_16V4Z

0.1U_0402_16V4Z
C323

C327

2

2

1

R3581K_0402_5%

1 2

11/14

V_3P3_LAN

R324

1 2

1 2

T21
PAD

1 2

1 2

PCIE_PLLVDD

GPHY_PLLVDD

1

V_1P2_LAN

V_3P3_LAN

V_2P5_LAN XTALVDD

LAN_AUXPWR
VMAINPRSNT

AVDDL
AVDD1

AVDD2

2

C27

1

4.7U_0805_10V4Z

U25B

E6
E7
E8
E9
J6
J7
J9
K5

A2
A6

A10

B4

D3

E11

G2

H11

K3

M2

P12

B6

H4

M12

J13

C7

H12

L5
A1

A4
A5
A7
A9
B2
B7

B8
C8
D1
D2
D4
D5

E1

E2

E4

F2

F3
G1
G3
H1
H3

J3

J4

K1

K2

K11

L1

L2

L3

L4

L8

L9

L11

M1
M5
M9
N2
N3
N9

P1

P2

G11
G12

B12

G13

L7

H13

Layout Notice : 1.2V decoupling CAP.
Place as close chip as possible.

2

2

2

C16

C44

C40

1

0.1U_0402_16V4Z

VDDC_0
VDDC_1
VDDC_2
VDDC_3
VDDC_4
VDDC_5
VDDC_6
VDDC_7

VDDIO_0
VDDIO_1
VDDIO_2
VDDIO_3
VDDIO_4
VDDIO_5
VDDIO_6
VDDIO_7
VDDIO_8
VDDIO_9
VDDIO_10

VDDP_0
VDDP_1
VDDP_2
XTALVDD
VAUXPRSNT
VMAINPRSNT
PCIE_SDSVDD

NC_0
NC_1
NC_2
NC_3
NC_4
NC_5
NC_6
NC_7
NC_8
NC_9
NC_10
NC_11
NC_12
NC_13
NC_14
NC_15
NC_16
NC_17
NC_18
NC_19
NC_20
NC_21
NC_22
NC_23
NC_24
NC_25
NC_26
NC_27
NC_28
NC_29
NC_30
NC_31
NC_32
NC_33
NC_34
NC_35
NC_36
NC_37
NC_38
NC_39
NC_40
NC_41

AVDDL_0
AVDDL_1
AVDD_0
AVDD_1

PCIE_PLLVDD
GPHY_PLLVDD

1

1

0.1U_0402_16V4Z

0.1U_0402_16V4Z

BCM5753

Digial power

Disconnected

Analog
power

PLL

BIAS

BCM5753KFBG C0_FPBGA196~D

C312

GND

1

2

C332

VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31

BIASVDD

0.1U_0402_16V4Z

VSS_0
VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9

DC_0
DC_1
DC_2
DC_3
DC_4
DC_5
DC_6
DC_7
DC_8

DC_9
DC_10
DC_11
DC_12
DC_13
DC_14
DC_15
DC_16
DC_17
DC_18
DC_19
DC_20
DC_21
DC_22
DC_23
DC_24
DC_25
DC_26
DC_27
DC_28
DC_29
DC_30
DC_31
DC_32
DC_33
DC_34
DC_35
DC_36
DC_37
DC_38
DC_39

2

C21

1

1

0.1U_0402_16V4Z

A3
A8
A12
A14
B1
C1
C3
C11
F1
F5
F6
F7
F8
F9
F10
G5
G6
G7
G8
G9
G10
H6
H7
H8
H9
J1
M3
M7
N1
N7
P11
P14

A11
A13
B14
C14
D6
D14
E3
E14
F14
G14
H5
H14
J8
J14
K4
K6
K7
K8
K9
K10
K14
L6
L10
L12
L14
M11
M14
N5
N11
N12
N14
P3
P4
P5
P6
P7
P8
P9
P10
P13

B13

2

1

0.1U_0402_16V4Z

Don't care

2

C310

1

0.1U_0402_16V4Z

1 2

BLM11A601S_0603

1

C351

0.1U_0402_16V4Z

2

C335

L16

2

1

0.1U_0402_16V4Z

V_2P5_LAN

2

C311

1

0.1U_0402_16V4Z

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/03/102006/03/10

Compal Secret Data

Deciphered Date

Title

SizeDocument NumberRev

2

Date:Sheet of

Compal Electronics, Inc.

Magnetic & RJ45/RJ11

LA-2821P

2652Friday, November 25, 2005

1

0.5

A B C D

C494

4.7U_0805_10V4Z

+1.5VS+3VS

1

2

+3VS_MINI

9/12

1

C167

0.01U_0402_16V7K

11

0.01U_0402_16V7K

2

C214

1

0.01U_0402_16V7K

2

C217

1

0.1U_0402_16V4Z

2

C171

1

4.7U_0805_10V4Z

2

C493

1

0.01U_0402_16V7K

2

C492

1

0.1U_0402_16V4Z

2

C489

1

2

C491

0.1U_0402_16V4Z

+3VALW

+3VALW +3VS_MINI

1

2

SLP_S3#

SLP_S3#18,21,25,28,29,33,35,36,40,43,44

+3VS

1 2

100K_0402_5% @

2N7002_SOT23@

1 2

R515

2

G

Q71

E

R505

0_0805_5%

S

G

2

13

D

S

D

13

Q70

SI2301BDS_SOT23@

9/8

+3VS +3VS_ACL

R56

1 2

0_0805_5%@

R44

R45

10U_0805_6.3V6MACCEL@

0_0402_5%ACCEL@

0_0402_5%ACCEL@

0_0402_5%ACCEL@

+3VS_ACL

C135

2 1

D11

CH751H-40_SC76ACCEL@

12

12

12

R50

1

2

18

20

14
15
21
22
23
24
25
26
27
28

4

1
7
8

U6

Reserved2

Reserved3

Reserved1

NC1
NC2
NC3
NC4
NC5
NC6
NC7
NC8
NC9
NC10
NC11
NC12
NC13

3

Vdd

PADDLE

29

5/26

Must be placed in the center of the system.

L

pin29 is the center EMI pad which STMicro
recommended not to be connected

12

R92
10K_0402_5%@

R104

9/16

0_0402_5%

XMIT_OFF21

2

+3VS_ACL_IO

+3VS_ACL

22

1

1

C121

C136

0.01U_0402_16V7K@

33

2

2

0.1U_0402_16V4ZACCEL@

19

2

+3VALW

12

G

1 2

11

Vdd

Vdd_IO

SDA/SDI/SDO

GND

5

12

R112

13

D

S

+3VS_ACL_IO

R55

0_0603_5%ACCEL@

RDY/INT

SDO

SCL/SPC

GND17GND

100K_0402_5%@

XMIT_OFF#

Q17

2N7002_SOT23@

6

9

10

12

13

CS

16

CK

LIS3LV02DQ_QFN28ACCEL@

ACCEL_INT19

ICH_SMBDATA4,13,14,15,18,21,25
ICH_SMBCLK4,13,14,15,18,21,25

R48

1 2

10K_0402_5%ACCEL@

12

R430_0402_5%

+3VS_ACL

Mini-Express Card

JP30

1

1

3

3

5

5

7

7

9

9

11

11

13

13

15

15

17

17

19

19

21

21

23

23

25

25

27

27

29

29

31

31

33

33

35

35

37

37

39

39

41

41

43

43

45

45

47

47

49

49

51

51

53

GND1

GND2

FOX_AS0B226-S40N-7F

H29

H28

HOLE_MC

HOLE_MC

1

2
4
6

8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

1

2
4
6

DB_LPC_FRAME#

8

DB_LPC_AD3

10

DB_LPC_AD2

12

DB_LPC_AD1

14

DB_LPC_AD0

16
18

XMIT_OFF#

20
22
24
26
28
30
32
34
36
38
40

WW_LED#

42

WL_LED#

44

WP_LED#

46
48
50
52

54

WW_LED#
WP_LED#

J12

2 1

PAD-No SHORT 2x2m

J11

2 1

PAD-SHORT 2x2m

ICH_SMBCLK4,13,14,15,18,21,25
ICH_SMBDATA4,13,14,15,18,21,25PCIE_TXN221

USB20_N1_R_MC32
USB20_P1_R_MC32

9/8

WL_LED#32

R4970_0402_5%@

1 2

R5000_0402_5%@

1 2

0_0402_5%

R546

1 2
1 2

R5470_0402_5%

8/30

PCIE_WAKE#
CH_DATA
CH_CLK
CLKREQD#

CLK_PCIE_MCARD#
CLK_PCIE_MCARD

DB_LPC_RST#
CLK_PCI_DB

PCIE_C_RXN2PCIE_RXN2
PCIE_C_RXP2

PCIE_TXN2
PCIE_TXP2

DB_PWR
DB_PWR_LED#
DB_NUM_LED#
DB_CAPS_LED#

PCIE_WAKE#21

CH_DATA30

CH_CLK30

CLKREQD#15

CLK_PCIE_MCARD#15

CLK_PCIE_MCARD15

PCIE_RXN221
PCIE_RXP221

CLK_PCI_DB15

PCIE_RXP2

PCIE_TXP221

+1.5VS +3VS_MINI

PLT_RST#7,19,20,21,23,25,32,33

11/22

+3VS

+3VALW

WL_LED#

Mini-Card Stand Off

Must be placed close to JP44.

L

LPC_FRAME#20,31,32,33

LPC_AD320,31,32,33
LPC_AD220,31,32,33
LPC_AD120,31,32,33
LPC_AD020,31,32,33

PLT_RST_B#20,31

NUM_LED#33,34

CAPS_LED#33,34

STB_LED#32,33,35

LPC_FRAME#
LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0
PLT_RST_B#

CAPS_LED#
STB_LED#

+3VL

R4520_0402_5%DB@

1 2

R4710_0402_5%DB@

1 2

R4560_0402_5%DB@

1 2

R4880_0402_5%DB@

1 2

R4950_0402_5%DB@

1 2

R5440_0402_5%DB@

1 2

R5300_0402_5%DB@

1 2

R5200_0402_5%DB@

1 2

R5140_0402_5%DB@

1 2

R5110_0603_5%DB@

1 2

DB_LPC_FRAME#
DB_LPC_AD3
DB_LPC_AD2
DB_LPC_AD1
DB_LPC_AD0
DB_LPC_RST#
DB_NUM_LED#NUM_LED#
DB_CAPS_LED#
DB_PWR_LED#
DB_PWR

9/12

44

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2005/03/102006/03/10

Compal Secret Data

Deciphered Date

Title

SizeDocument NumberRev

D

Date:Sheet of

Compal Electronics, Inc.

Mini-Card/Mini-PCI/Accelerometer

LA-2821P

2752Friday, November 25, 2005

E

0.5

A B C D E F

VDDA_CODEC

12

R287
10K_0402_5%

C276

R277

1 2

C279

1 2

1 2

1 2

12
12

13

D

0.1U_0402_16V4Z

11

22

33

PCM_SPK23

SB_SPKR21

DLINE_IN_L35
DLINE_IN_R35

2

G

Q48

S

2N7002_SOT23

VDDA_CODEC

12

R288
10K_0402_5%

13

D

0.1U_0402_16V4Z

2

G

Q51

S

2N7002_SOT23

INT_MIC29

R2904.7K_0402_5%
R2894.7K_0402_5%

1 2

R2914.7K_0402_5%
R2924.7K_0402_5%

1 2

Place close to U14

12

C5450.1U_0805_25V7M

11/17

12

C2590.1U_0805_25V7M

12

44

C2060.1U_0805_25V7M

12

C2840.1U_0805_25V7M

R219

12

0_1206_5%@

10K_0402_5%

150K_0402_1%

R279

150K_0402_1%

DLINE_IN_R_L
DLINE_IN_R_R

VDDA_CODEC

R2972.67K_0402_1%

R2362.2K_0402_5%

AC97_RST#_CODEC20

AC97_SYNC_CODEC20

AC97_SDOUT_CODEC20

12

2

C269

R283

0.01U_0402_16V7K

1

VDDA_CODEC

C265

0.1U_0402_16V4Z

C2831U_0603_10V4Z

1 2

C2701U_0603_10V4Z

1 2

C2741U_0603_10V4Z

1 2

C2751U_0603_10V4Z

1 2

MIC129
MIC229

1 2

1 2

EAPD29,33

1

2

MONO_IN_HD

1 2

C2640.1U_0402_16V4Z1981HD@

0.1U_0402_16V4Z

1

1

C224

C225

2

2

0.1U_0402_16V4Z

1 2

C2721U_0603_10V4Z

1 2

C2731U_0603_10V4Z

R2840_0402_5%@

L11

1 2

FBM-L10-160808-301-T_0603

0.1U_0402_16V4Z

1

C266

C222

2

10U_1206_16V4Z

T48PAD

T44PAD

INT_MICL_C
INT_MICR_C
DLINE_IN_RC_L
DLINE_IN_RC_R

T47PAD

T45PAD

T46PAD

MIC1_C
MIC2_C
SENSE_A

SENSE_B

12

T35PAD

2

1

U21

14

AUX_L

15

AUX_R

16

MIC3

17

MIC4

23

LINE_IN_L

24

LINE_IN_R

18

CD_L

20

CD_R

19

CD_GND

21

MIC1

22

MIC2

13

SENSEA

34

SENSEB

11

RESET#

10

SYNC

5

SDATA_OUT

47

EAPD

48

SPDIFO

4

DVSS1

7

DVSS2

AD1981HDJSTZ-REEL_LQFP48

38

AVDD125AVDD2

GNDAGND

+5VAMP

1

2

DVDD11DVDD2

LINE_OUT_L

LINE_OUT_R

MONO_OUT
HP_LOUT_L
HP_LOUT_R

BIT_CLK

SDATA_IN

GPIO_0
GPIO_1
GPIO_2
GPIO_3

VREF

MIC_BIAS_B
MIC_BIAS_C
MIC_BIAS_F
MIC_BIAS_D

PCBEEP

AVSS1
AVSS2

+

2

9

N/C
N/C
N/C

NC
NC

C193

C198

1U_0603_10V4Z

22U_B_10V

1

0.1U_0402_16V4Z

C251

+3VS_CODEC

1

1

C239

2

2

0.1U_0402_16V4Z

35
36
37
39
41

C24710P_0402_25V8K

6
8

43
44
2
3

27
28

29
30
32
12

31
33
40
45
46

26
42

1 2

10_0402_5%@

R248

AC97_SDIN0_CODEC

R2264.7K_0402_5%@

PIN44

R2244.7K_0402_5%@
R21810K_0402_5%
R2414.7K_0402_5%@

1 2

AUD_REF
CODEC_REF

AFILT1
AFILT2
AFILT4
MONO_IN_HD

AFILT3
PIN33
PIN40

T36PAD
T37PAD

PIN42

1 2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

SLP_S3#18,21,25,27,29,33,35,36,40,43,44

2

C194
100P_0402_50V8J

1

R198

1 2

0_1206_5%

R225

1 2

0_0805_5%

1

C238
10U_1206_16V4Z

2

LINE_OUTL29
LINE_OUTR29

T33PAD

L_HP29
R_HP29

AC97_BITCLK_CODEC20

10P_0402_25V8K@

1 2

12

C249

R252

12

33_0402_5%

12

12

T41PAD

T43PAD
T42PAD
T38PAD

T40PAD
T39PAD
T34PAD

2005/03/102006/03/10

Compal Secret Data

U17

1

IN

OUT

3

EN

ADJ

2

GND

MIC5205BM5_SOT23-5

0.01U_0402_16V7K

Place R258 between DGND & AGND & close to U14

+3VS

SENSE_A SENSE_A_A

1U_0603_10V4Z

AC97_SDIN020

PORT_A_SNS

PR_INSERT#

1

C256
1U_0603_10V4Z

2

Deciphered Date

PORT_A_SNS29

1

C250

0.1U_0402_16V4Z

2

5
4

F

C282

C205

1 2

39.2K_0402_1%

1 2

20K_0402_1%

1 2

10K_0402_1%

1

2

VDDA_CODEC

2

1

R293
R294
R286

12

R213

49.9K_0402_1%

12

R206
143K_0402_1%

SENSE_A_B
SENSE_A_C

Q52

2N7002_SOT23

G

1

1

+

C216

C213

0.1U_0402_16V4Z

22U_B_10V

2

2

SENSE_A_A29
SENSE_A_B29

VDDA_CODEC

12

R296

13

D

S

100K_0402_5%

Title

SizeDocument NumberRev

Date:Sheet of

10K_0402_5%@

LINE_IN_SENSE

2

G

12

1

R295

C285

0.1U_0603_50V

2

Compal Electronics, Inc.

AC97 CODEC AD1981HD

LA-2821P

G

H

LINE_IN_SENSE35

2852Friday, November 25, 2005

H

0.5

A B C D

E

AMP. FOR INTERNAL SPEAKER

R220

11

10U_1206_6.3V6M@

10 dB

C261

LINE_C_OUTR LINE_C_R_OUTR

LINE_OUTR28

LINE_OUTL28

22

1 2

0.1U_0402_16V4Z
C260

LINE_C_OUTL LINE_C_R_OUTL

1 2

0.1U_0402_16V4Z

SLP_S3#18,21,25,27,28,33,35,36,40,43,44

MUTE_LED#34

EAPD28,33
A_SD33

R272

1 2

10K_0402_5%

R270

1 2

10K_0402_5%

10 dB

R20310K_0402_5%

1 2

R6490_0402_5%

1 2

12

11/14

R650

1K_0402_5%

C208

R271

0_0402_5%

13

D

2

G

Q40

S

2N7002_SOT23@

2

G

Q39

2N7002_SOT23

1

2

12

1 2

0_1206_5%

150U_D_6.3VM@

13

D

S

+5VAMP+5VALW

10U_1206_6.3V6M@

1

+

C252

2

5

INR

1

INL

4

MUTE

14

SHDN

1

C246

2

12

8

18

U20

VDD

PVDD1

PVDD2

OUTR+
OUTR-

OUTL+

OUTL-

PGND1

PGND211PGND315PGND4

EP

MAX9710ETP_QFN20

6

21

20

1

1

C248

C240

0.1U_0402_16V4Z

2

2

1U_0603_10V4Z@

Keep 10 mil width

L

C2621U_0603_10V4Z

BIAS

2

7
9

19
17

3

NC1

10

NC2

13

NC3

16

NC4

R257

R_SPK+
R_SPK-

R256

L_SPK+
L_SPK-

1 2

1 2

16.5K_0402_1%

1 2

16.5K_0402_1%

LINE_C_R_OUTR

10 dB

LINE_C_R_OUTL

10 dB

PACDN042_SOT23~D@

100P_0402_50V8J

GAIN0

1

D18

2

3

L_SPK+
L_SPK­R_SPK+
R_SPK-

100P_0402_50V8J

1

1

C160

C161

C162

2

2

100P_0402_50V8J

U39 Gain Settings

GAIN11Av(inv)

00

0

1

1

0

1

1

3

1

2

6 dB

10 dB

15.6 dB

21.6 dB

D19

PACDN042_SOT23~D@

2

1

C163
100P_0402_50V8J

2

JP19

1

1

2

2

3

3

4

4

E&T_3801-04

VDDA_CODEC

PORT_A_SNS28

SENSE_A_A28

33

44

2N7002_SOT23

D

Q49

S

DOCK_HPS#35

13

G

2N7002_SOT23

0.1U_0603_25V7K_V1

12

R285

2

100K_0402_5%

13

D

2

G

Q50

S

1

C281

2

VDDA_CODEC

Q47

2N7002_SOT23

12

R278
100K_0402_5%

13

D

S

2

G

1

C278

2.2U_0603_6.3V6K

2

SENSE_A_B28

R273

1 2

100K_0402_5%

2N7002_SOT23

VDDA_CODEC

12

R258
100K_0402_5%

13

D

Q37

S

2

G

DLINE_OUT_L

0.1U_0402_16V4Z

MIC_SENSE

To Audio / USB Board CONN

USB20_N221
USB20_P221

USB20_N321
USB20_P321

USB_OC#221
USB_OC#321

SLP_S530,35,36

DLINE_OUT_L35

DLINE_OUT_R35

INT_MIC28

C188

+5VALW

1

2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

USB20_N2
USB20_P2

USB20_N3
USB20_P3

SLP_S5

MIC_SENSE
DLINE_OUT_L

R_HP28

L_HP28
MIC128
MIC228

1 2
1 2

2005/03/102006/03/10

0_0402_5%
R162
R170
0_0402_5%
R174
R180

0_0402_5%

+

C191
100U_D2_6.3VM

+

C192
100U_D2_6.3VM

Compal Secret Data

12
12

0_0402_5%

12
12

+5VALW

VDDA_CODEC

Deciphered Date

USB20_N2_R
USB20_P2_R

USB20_N3_R
USB20_P3_R

12
12

R207
15_0805_5%
R217
15_0805_5%

JP25

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

11

11

12

12

13

13

14

14

15

15

16

16

17

17

18

18

19

19

20

20

21

21

22

22

ACES_87212-2200

D

Title

SizeDocument NumberRev

Date:Sheet of

Compal Electronics, Inc.

AMP & Audio Jack

LA-2821P

2952Friday, November 25, 2005

E

0.5

5 4 3 2

USB CONNECTOR 1

1

U36

1

GND

2

DD

4.7U_0805_10V4Z

CC

C137

+5VALW

1

2

SLP_S5

IN

3

IN
EN#4OC#

TPS2041BDR_SO8

U35

1

GND

2

IN

3

IN
EN#4OC#

G548A2P1U_SO8

8

OUT

7

OUT

6

OUT

5

USB_OC#4

USB_VCCA USB_VCCB

OUT
OUT
OUT

8
7
6
5

PAD-OPEN 3x3m

1 2

J13

USB_OC#4 USB_OC#5

W=40mils

1

+

2

R490_0402_5%

USB_VCCA+5VALW +5VALWUSB_VCCB

USB20_N421

1

USB20_P421

C498

2

1000P_0402_50V7K

C118

220U 6.3V M

1

C499

2

0.1U_0402_16V4Z

USB_OC#421

(4A,160mils ,Via NO.=8)

12

1

2

JP16

1

VCC

2

D0-

3

D0+

4

VSS
G210G1

12

TYCO_1-1734062-1

11/17

VCC

VSS

5
6

D1-

7

D1+

8
9

G311G4

R530_0402_5%

D12

USB20_N4_R

12

USB20_P4_R

12

R570_0402_5%

3

USB20_N4
USB20_P4

USB20_N4
USB20_P4 USB20_P5

PACDN042_SOT23~D@

USB20_N5_R
USB20_P5_R

USB20_N5

PACDN042_SOT23~D@

R510_0402_5%

USB20_N5

12

USB20_P5

12

R520_0402_5%

2

3

D10

1

USB20_N521
USB20_P521

USB_OC#5SLP_S5

U7

8

OUT

7

OUT

6

OUT

5

OC#

TPS2041BDR_SO8

GND

1
2

IN

3

IN

SLP_S5

4

EN#

SLP_S529,35,36

USB_OC#521

W=40mils

1

C123

2

1000P_0402_50V7K

1

1

+

C122

2

2

C126

220U 6.3V M

0.1U_0402_16V4Z

BT Connector

JP18

1
2

USB20_P0_R

3

USB20_N0_R

BB

4
5
6
7
8

ACES_87212-0800

R674100_0402_5%
R677100_0402_5%

1 2
1 2

R85

R87

11/23

0_0402_5%

12

0_0402_5%

12

3

+3VAUX_BT

USB20_P0
USB20_N0

BT_LED32
CH_DATA27

CH_CLK27

2

D16

PACDN042_SOT23~D@

1

USB20_P021
USB20_N021

Q12SI2301BDS_SOT23

S

D

13

1

C140
1U_0603_10V4Z

2

AA

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

AY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2005/03/102006/03/10

Compal Secret Data

Deciphered Date

2

BT_OFF21

12

G

1

R69
100K_0402_5%

1 2

47K_0402_5%

2

2

0.01U_0402_16V7K

1

R70

Title

SizeDocument NumberRev

Date:Sheet of

C138

0.1U_0402_16V4Z

@

2

9/14

Compal Electronics, Inc.

USB I/O & BT Connector

LA-2821P

0.1U_0402_16V4Z

1

C144

2

1

C143

+3VAUX_BT+3VALW

1

C142

4.7U_0805_10V4Z

2

3052Friday, November 25, 2005

0.5

A B C D

E

11

DCD#1
RI#1
CTS#1
DSR#1

4.7K_1206_8P4R_5%

IRRX

U29

10

LAD0

12

LAD1

13

LAD2

14

LAD3

15

LFRAME#

16

LDRQ#

17

PCI_RESET#

18

LPCPD#

19

CLKRUN#

20

PCI_CLK

21

SER_IRQ

6

IO_PME#

9

CLK14

CLOCK

23

GPIO40

24

GPIO41

25

GPIO42

27

GPIO43

28

GPIO44

29

GPIO45

30

GPIO46

31

GPIO47

32

GPIO10

33

GPIO11/SYSOPT

34

GPIO12/IO_SMI#

35

GPIO13/IRQIN1

36

GPIO14/IRQIN2

40

GPIO23

8

VSS

22

VSS

43

VSS

52

VSS

LPC47N217_STQFP64

Base I/O Address

0 = 02Eh
1 = 04Eh*

12

R434
10_0402_5%@

1

C410
18P_0402_50V8K

@

2

GPIO

POWER

9/8

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3

LPC_FRAME#
LPC_DRQ#0

SIO_RST#
SIO_PD#

PM_CLKRUN#
CLK_PCI_SIO
SIRQ
SIO_PME#

CLK_14M_SIO
SIO_GPIO40

PID0
PID1
SIO_GPIO43
SIO_GPIO44
SIO_DPIO45
CARD_ID#
SER_SHD
SIO_GPIO10
SIO_GPIO11
SIO_GPIO12
SIO_IRQ

SW_EXPCRD_RST#

LPC_AD020,27,32,33
LPC_AD120,27,32,33
LPC_AD220,27,32,33

RP30

SIO_GPIO12

18

SIO_GPIO10

27

SIO_GPIO44

36

SIO_GPIO43

22

+3VS

+3VS

33

10K_1206_8P4R_5%

R428

1 2

R437

1 2

R8

1 2

10K_0402_5%

R422

1 2

10K_0402_5%

R435

1 2

10K_0402_5%

R436

1 2

10K_0402_5%

R429

1 2

10K_0402_5%

R438

1 2

10K_0402_5%

45

10K_0402_5%
10K_0402_5%

SIO_IRQ
SIO_DPIO45

CARD_ID#

R421

1 2

0_0402_5%

PID0

PID1

SIO_GPIO11

SIO_GPIO40

EXPCRD_RST#35

NPCI_RST#21,33

PLT_RST_B#20,27

+3VS

R4310_0402_5%

1 2

R4320_0402_5%@

1 2

R43310K_0402_5%

1 2

+3VS

High : Compal MXM
Low : Standard MXM

1 2

R41710K_0402_5%

LPC_AD320,27,32,33

LPC_FRAME#20,27,32,33

LPC_DRQ#020

PM_CLKRUN#21,23,32,33

CLK_PCI_SIO15

SIRQ21,23,32,33

CLK_14M_SIO15

SER_SHD35

RP29

1 8
2 7
3 6
4 5

1 2

R427
1K_0402_5%

SERIAL I/F

FIR

LPC I/F

IRMODE/IRRX3

PARALLEL I/F

CLK_14M_SIOCLK_PCI_SIO

12

1

2

+3VS

RXD1

TXD1
DSR1#
RTS1#
CTS1#
DTR1#

RI1#

DCD1#

IRRX2

IRTX2

INIT#

SLCTIN#

PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7

SLCT

PE
BUSY
ACK#

ERROR#

ALF#

STROBE#

VTR
VCC
VCC
VCC
VCC

R420
10_0402_5%@

C399
10P_0402_25V8K

@

62
63
64
1
2
3
4
5

37
38
39

41
42
44
46
47
48
49
50
51
53
55
56
57
58
59
60
61

7
11
26
45
54

RXD1
TXD1
DSR#1
RTS#1
CTS#1
DTR#1
RI#1
DCD#1

IRRX

LPTINIT#
LPTSLCTIN#
LPD0
LPD1
LPD2
LPD3
LPD4
LPD5
LPD6
LPD7
LPTSLCT
LPTPE
LPTBUSY
LPTACK#
LPTERR#
LPTAFD#
LPTSTB#

1

C391

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

RXD135

R4031K_0402_5%

1 2

TXD135
DSR#135
RTS#135
CTS#135
DTR#135
RI#135
DCD#135

LPTINIT#35
LPTSLCTIN#35
LPD035
LPD135
LPD235
LPD335
LPD435
LPD535
LPD635
LPD735
LPTSLCT35
LPTPE35
LPTBUSY35
LPTACK#35
LPTERR#35
LPTAFD#35
LPTSTB#35

1

1

C383

C397

2

2

0.1U_0402_16V4Z

4.7U_0805_10V4Z

+5VS

21

D31
CH751H-40_SC76

+5VS_PRN

LPD3
LPD2
LPD1
LPD0

LPD7
LPD6
LPD5
LPD4

LPTACK#
LPTBUSY
LPTPE
LPTSLCT

LPTSTB#
LPTAFD#
LPTERR#

LPTSLCTIN#SW_EXPCRD_RST#

+3VS

1

C401

LPTINIT#

RP28

1 8
2 7
3 6
4 5

4.7K_1206_8P4R_5%
RP27

1 8
2 7
3 6
4 5

4.7K_1206_8P4R_5%
RP26

1 8
2 7
3 6
4 5

4.7K_1206_8P4R_5%
RP25

1 8
2 7
3 6
4 5

4.7K_1206_8P4R_5%
R414

1 2

4.7K_0402_5%
R418

1 2

4.7K_0402_5%

2

44

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

AY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2005/03/102006/03/10

Compal Secret Data

Deciphered Date

Title

SizeDocument NumberRev

D

Date:Sheet of

Compal Electronics, Inc.

SUPER I/O LPC47N217

LA-2821P

3152Friday, November 25, 2005

E

0.5

5 4 3 2

+5VS

BIOS ROM

+3VALW

U14

DD

0.1U_0402_16V4ZSPI@

CC

BB

LPC_PD#21,33

AA

C172

SPI_CS#21
SPI_CLK21

4.7K_0402_5%@

+3VALW

8/26

1

SPI_WP#

2

SPI_HOLD#
SPI_CS#
SPI_CLK

R379

R375

+3VS

+3VS

12

12

SPI_SI

R402

1 2

R401

SPI_SI21

0_0402_5%TPM1.2@

U13

8

VCC

VSS

3

W

7

HOLD

1

S

6

C

5

D

MX25L8005MI-15G_SO8-150mil@

LPC_AD020,27,31,33
LPC_AD120,27,31,33
LPC_AD220,27,31,33
LPC_AD320,27,31,33

LPC_FRAME#20,27,31,33

10K_0402_5%TPM1.2@
0_0402_5%TPM1.2@

Place R1447 close to Y8.1

L

CLK_TPM33

PLT_RST#7,19,20,21,23,25,27,33

12

SIRQ21,23,31,33

CLK_PCI_TCG15

C392

10P_0402_50V8K@

PM_CLKRUN#21,23,31,33

R397

18P_0402_50V8JTPM1.2@

C365

32.768KHZ_12.5P_1TJS125BJ2A251TPM1.2@

2

NC

3

NC

Y5

C341

18P_0402_50V8JTPM1.2@

4

2

Q

L

1

C349

2

0.1U_0402_16V4ZTPM1.2@

12

1 2

0_0402_5%@

9/13

12

IN

OUT

12

1 2

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
LPC_FRAME#
PLT_RST#

SIRQ
CLK_PCI_TCGLPC_PD#

R415
10_0402_5%@

PM_CLKRUN#

1
4

8/26

8

VCC

SPI_WP#
SPI_HOLD#
SPI_CS#
SPI_CLK
SPI_SI

R109

SPI_SO

47_0402_5%SPI@

R1291 should be placed less
than 100 mils from U61 & U65.

VSS

3

W

7

HOLD

1

S

6

C

5

D

SST25LF080A_SO8-200milSPI@

SPI_SO21

TPM1.2 on board

0.1U_0402_16V4ZTPM1.2@

1

C393

2

12

TPM_XTALO
TPM_XTALI

12

TPM_XTALI

R394

TPM_XTALO

1

0.1U_0402_16V4ZTPM1.2@

2

26
23
20
17
22
16
28
27
21

15

14
13

10M_0402_5%TPM1.2@

C394

U26

LAD0
LAD1
LAD2
LAD3
LFRAME#
LRESET#
LPCPD#
SERIRQ
LCLK

SLB 9635 TT 1.2

CLKRUN#

7

PP

XTALO
XTALI/32K IN

+3VS +3VALW

19

24

VDD

VDD

TESTB1/BADD

GND

GND

18

25

4

+3VALW

8/26

R108

SPI_WP#

1 2

3.3K_0402_5%SPI@

R155

2

Q

The chip must be placed on PCB easily

L

rework place for debug.

1

C350

0.1U_0402_16V4ZTPM1.2@

2

5

10

VSB

VDD

TPM_GPIO

6

GPIO

TPM_GPIO2

2

GPIO2

Base I/O Address

0 = 02Eh

*1 = 04Eh

R390

8

TEST1

9

3

NC

12

NC

1

NC

GND

GND

SLB 9635 TT 1.2_TSSOP28TPM1.2@

4

11

1 2

3.3K_0402_5%SPI@

12

0_0402_5%TPM1.2@

SPI_HOLD#

T23PAD
T24PAD

R377

4.7K_0402_5%@

AMBER_BATLED#33

GREEN_BATLED#33

+3VS

12

R378

4.7K_0402_5%TPM1.2@

12

Finger printer

USB20_N121
USB20_P121

L

USB20_N1_R
USB20_P1_R

Wireless LED

LTST-S110TBKT-5A

BT_LED

2N7002_SOT23

WL_LED

9/12

AMBER_BATLED#

DTA114YKA_SC59

GREEN_BATLED#

Battery LED

19-22SOVGC/TR8_GRN/ORG

D9

BLUE LED

2N7002_SOT23

R46
R47

3

1

USB20_N1_R_MC

12

USB20_P1_R_MC

12

WL/BT_LED34

BT_LED30

9/8

USB20_N1
USB20_P1

PACDN042_SOT23~D@

Place R1365/R1366 close to JP38.2/JP38.3
and minimize the stub length.

R5700_0402_5%@

R5690_0402_5%@

12

R221
150_0402_5%

21

D28

13

D

2

G

Q35

S

13

D

2

G

Q36

S

+3VL

HDD_STP21

47K

10K

2

Q44

1 3

2

Q45

DTA114YKA_SC59

12

R233

150_0402_5%

150_0402_5%

D30

AMBER GREEN

+3VS

C124

0.1U_0402_16V4Z

9/8

0_0402_5%

USB20_N1_R

12

USB20_P1_R

12

0_0402_5%

2

9/8

+3VL

47K

10K

R234

21

1

2

USB20_N1_R_MC27
USB20_P1_R_MC27

+3VS

47K

10K

1 3

Mini-PCIE Card LED

BT_LED

WL_LED

HDD_STP

12

IDE_LED#20

1 3
12

34

JP15

1
2
3
4
5
6
7
8

ACES_87212-0800

2

Q34
DTA114YKA_SC59

WL_LED

1 2

100K_0402_5%

1 2

100K_0402_5%

8/23

R212

1 2

0_0402_5%@

2N7002_SOT23
Q41

13

D

2

G

S

R211
100K_0402_5%

R199
R95

HDD_STP#

DTA114YKA_SC59

IDE_LED#

1

WL_LED#27

+3VS

9/6

47K

10K

2

Q42

1 3

DTA114YKA_SC59

12

R243

150_0402_5%

150_0402_5%

9/2

HDD LED

19-22SOVGC/TR8_GRN/ORG

D27

STB_LED#27,33,35

DTA114YKA_SC59

STB_LED34

POWER LED

17-21SYGC/S530-E1/TR8_GRN

2

Q46

STB_LED#

+3VS

47K

10K

R242

21

2

Q38

150_0402_5%

GREEN

1 3
12

34

GREENAMBER

+3VL

47K

10K

1 3
12

R222

21

D29

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2005/03/102006/03/10

Compal Secret Data

Deciphered Date

2

Title

SizeDocument NumberRev

Date:Sheet of

Compal Electronics, Inc.

TCG/BIOS ROM/PS2/LED/SW

LA-2821P

3252Friday, November 25, 2005

1

0.5

5 4 3 2

+3VL

+3VS

1

C215

TP_CLK34
TP_DATA34
KBD_CLK35

KBD_DATA35

PS2_CLK35

PS2_DATA35

SIRQ21,23,31,32

CLK_PCI_EC15

LPC_AD320,27,31,32
LPC_AD220,27,31,32
LPC_AD120,27,31,32
LPC_AD020,27,31,32

12

1U_0603_10V4Z

1

0.1U_0402_16V4Z

2

KSO[0..13]

+RTCVCC

2

C263

1

1

C196

+3VL

DD

CC

BB

AA

RP21

KSI3

1 8

KSI2

2 7

KSI1

3 6

KSI0

4 5

10K_1206_8P4R_5%

RP22

KSI7

1 8

KSI6

2 7

KSI5

3 6

KSI4

4 5

10K_1206_8P4R_5%

+5VS

R192

TP_CLK

1 2

10K_0402_5%

R197

TP_DATA

1 2

10K_0402_5%

RP23

KBD_CLK

1 8

KBD_DATA

2 7

PS2_CLK

3 6

PS2_DATA

4 5

10K_1206_8P4R_5%

Note: R94 must be removed when

+3VS

L

R1354 stuff and R87 remove.

R216

LPCPD#

1 2

10K_0402_5%

R262

RUNSCI_EC#

1 2

10K_0402_5%

Pin34 250 -- LPCPD#

CLK_PCI_EC

12

R232

10_0402_5%@

2

C237

10P_0402_50V8J@

1

1021@

250@
R127

R129

R128

R131

R977

R78

NPCI_RST#21,31

PLT_RST#7,19,20,21,23,25,27,32

LPC_PD#21,32

10P_0402_50V8J

0.1U_0402_16V4Z

11/14

NPCI_RST#
PLT_RST#

ADP_EN

R2652M_0402_5%@

1 2

1

IN

1

C267

2

2

32.768KHZ_12.5P_1TJS125DJ2A073

0.1U_0402_16V4Z

2

KSO[0..13]34

Pin3 250 : KSO12/OUT8/KBRST

KSI[0..7]34

PM_CLKRUN#21,23,31,32

RUNSCI_EC#21

LPC_FRAME#20,27,31,32

R6510_0402_5%

1 2

R6520_0402_5%@

1 2

R2150_0402_5%@

1 2

R2230_0402_5%@

1 2

R266

120K_0402_5%

4

Y3

1

OUT

C268
10P_0402_50V8J

NC3NC

2

R62

1

C243

0.1U_0402_16V4Z

2

KSO0

17

KSO1

16

KSO2

15

KSO3

14

KSO4

13

KSO5

12

KSO6

10

KSO7

9

KSO8

7

KSO9 FWP#

6

KSO10

5

KSO11

4
3

KSO13

2

KSI0

25

KSI1

24

KSI2

23

KSI3

22

KSI4

21

KSI5

20

KSI6

19

KSI7

18

TP_CLK

26

TP_DATA

27

KBD_CLK

29

KBD_DATA

31

PS2_CLK

32

PS2_DATA

33

PM_CLKRUN#

44

SIRQ

46

CLK_PCI_EC

43

RUNSCI_EC#

59

LPC_AD3

40

LPC_AD2

39

LPC_AD1

37

LPC_AD0

35

LPC_FRAME#

41
42
34

LPCPD#
CRY1

53

CRY2

54
51

1

C253

0.1U_0402_16V4Z

2

1

C255

2

U18

KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12/GPIO00/KBRST
KSO13/GPIO18

KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7

IMCLK
IMDAT
KCLK
KDAT
EMCLK
EMDAT

CLKRUN#
SER_IRQ
PCI_CLK
EC_SCI#

LAD[3]
LAD[2]
LAD[1]
LAD[0]

LFRAME#
LRESET#
LPCPD#/GPIO23

XTAL1
XTAL2

VCC0

C257

4.7U_0805_10V4Z

Power Mgmt/SIRQ

LPC

Bus

Keyboard/Mouse Interface

AGND

55

1

2

VCC111VCC167VCC181VCC194VCC230VCC238VCC2

SMSC_LPC47N250_TQFP-100P

GND92GND79GND65GND45GND36GND28GND

AGND FILTER

C254

1 2

0.1U_0402_16V4Z

PWR_GD_EC

R6700_0402_5%

1 2

R6690_0402_5%@

1 2

11/21

PWR_GD
PGD_IN

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

1

2

47

Access Bus Interface

24MHZ_OUT/GPIO19/WINDMON

Miscellaneous

8

PWR_GD18,36,37,45,47
PGD_IN37,45

C244

0.1U_0402_16V4Z

General Purpos e I/O Interface

EA Strap#/GPIO26/KSO17

2005/03/102006/03/10

1

2

OUT0

OUT1/IRQ8#

OUT7/SMI#

OUT8/KBRST

OUT9/PWM2
OUT10/PWM0
OUT11/PWM1

GPIO01
GPIO02

GPIO03
GPIO04/KSO14
GPIO05/KSO15

GPIO07/PWM3

GPIO08/RXD

GPIO09/TXD

GPIO11/AB2A_DATA

GPIO12/AB2A_CLK

GPIO13/AB2B_DATA

GPIO14/AB2B_CLK
GPIO15/FAN_TACH1
GPIO16/FAN_TACH2

GPIO17/A20M

GPIO20/PS2CLK

GPIO21/PS2DAT

GPIO24/KSO16

GPIO27

AB1A_DATA

AB1A_CLK

AB1B_DATA

AB1B_CLK

PGM Strap/GPIO25

CLOCK

32KHZ_OUT/GPIO22

RESET_OUT#/GPIO06

PWRGD

VCC1_PWRGD

TEST PIN

DMS_LED#/GPIO10

BAT_LED#
PWR_LED#/8051TX
FDD_LED#/8051RX

KBC1021_TQFP100

C226

0.1U_0402_16V4Z

Compal Secret Data

1

C209

0.1U_0402_16V4Z

2

KBC_PWR_ON

99

GREEN_BATLED#

100

BATSELB_A#

98

KBRST#

97

INV_PWM

96

FAN_PWM

95

CHGCTRL

93
82

ON/OFFBTN_KBC#

62

LOW_BAT#

63

KSO14KSO12

64

KSO15

66

PM_RSMRST#

68

GPIO8

69
70

71
72
73
74
75
76
77

78
80
1
57

86
87

84
85

56
83

48
58
49
61
60
50

52

91
88
90
89

R2800_0402_5%250@

GPIO9

R2810_0402_5%250@

BATCON
EC_GPIO12
EC_GPIO13
THM_MBAY#
PCI_SERR#
THM_MAIN#
A20M

NUM_LED#
SLP_S3#

R185

1 2

MODE

Pin57 250 -- MODEPin1 250 -- TEST Pin ( NC !! )

R2020_0402_5%

1 2

AB1A_DATA
AB1A_CLK

AB1B_DATA
AB1B_CLK

R2040_0402_5%

1 2

PGM
EA#

CLK_14M_KBC
S_CLK
PM_POK
PWR_GD_EC
VCC1_PWRGD
EC_GPIO19

Pin50 250 -- 24MHz_Out

TEST

Pin52 250 -- XOSEL

EC_GPIO10
AMBER_BATLED#
STB_LED#
CAPS_LED#

EC_GPIO19

R251
R264

EC_GPIO12

R214

EC_GPIO10

R260

S_CLK

R261
R399

MODE

R268

J9

1 2

R267

R276

R282

R275
R254
R235

1 2

PGM
FWP#

PGM

NO SHORT PADS

FWP#
TEST
EA#

Deciphered Date

1

2

KBC_PWR_ON42
GREEN_BATLED#32

BATSELB_A#41
INV_PWM17

FAN_PWM4
CHGCTRL40,41

ON/OFFBTN_KBC#34
LOW_BAT#21
KSO1434
KSO1534
PM_RSMRST#21

1 2
1 2

BATCON41

THM_MBAY#46
PCI_SERR#19,23
THM_MAIN#46

Pin56 250 -- PGM
Pin83 250 -- nEA ( pull up !! )

CLK_14M_KBC15

VCC1_PWRGD37

1 2

R249300_0402_5%

Pin91 250 -- nDMS_LED

AMBER_BATLED#32
STB_LED#27,32,35
CAPS_LED#27,34

R647

1 2

100K_0402_5%

1 2

0_0402_5%

1 2

0_0402_5%

1 2

0_0402_5%

1 2

33_0402_5%@

1 2

0_0402_5%

1 2

0_0402_5%@

10K_0402_5%250@

1 2

1K_0402_5%@

1 2

1K_0402_5%@

+3VL

1 2

1K_0402_5%

12

1K_0402_5%@

12

1K_0402_5%@

12

1K_0402_5%

2

C236

4.7U_0805_10V4Z

+3VL

12

R205
10K_0402_5%

D25

21

CH751H-40_SC76

Pin82 250 -- nFWP

KSO16 EC_GPIO12
KSO17

D24

2 1

CH751H-40_SC76

R255

12

10K_0402_5%

D26

CH751H-40_SC76

0_0402_5%1021@

1 2

+3VL

ADP_ID47
ADP_PS147
ADP_PS047
CB_CLK24

ADP_EN

CLK_TPM32

1. For normal operation:

Un-install R29,R65

2. For KBC internal ROM flash:

Install R29,R65

21

NUM_LED#27,34
SLP_S3#18,21,25,27,28,29,35,36,40,43,44
KSO1634

EAPD28,29
AB1A_DATA46

AB1A_CLK46
AB1B_DATA46

AB1B_CLK46
A_SD29

R238
0_0402_5%1021@

ADP_EN47

Title

SizeDocument NumberRev

Date:Sheet of

BIOS debug port
Place under KB area

KB_RST#20

ADP_PRES18,25,40,41,42,47

+3VL

GATEA2020

KSO1734

PM_POK7,21

Pin58 250 -- 32KHz_OUT
Pin49 250 -- Reset Out

CLK_14M_KBC

For KBC debugging used.

Compal Electronics, Inc.

LPC47N1021

LA-2821P

+3VL

JP21

4.7K_1206_8P4R_5%

R246

1 2

10_0402_5%

@

R274

1 2

10K_0402_5%

EC_GPIO12

+3VL

1
2
3
4
5
6

ACES_85201-0602@

R259

1 2

210K_0402_1%

R263

1 2

100K_0402_5%

R194

1 2

100K_0402_5%

RP24

1 8
2 7
3 6
4 5

R250

1 2

100K_0402_5%

C245

1 2

10P_0402_50V8K

@

JP22

1
2
3
4
5
6

ACES_85201-0602@

3352Friday, November 25, 2005

VCC1_PWRGD
GPIO9

GPIO8

THM_MAIN#

EC_GPIO13

AB1A_CLK
AB1A_DATA
AB1B_CLK
AB1B_DATA

NUM_LED#

FWP# PM_POK

VCC1_PWRGD
NUM_LED#
STB_LED#
CAPS_LED#

1

+3VL

+3VL

0.5

SWITCH BOARD.

+3VS +3VL +5VS

MUTE_LED#29

ON/OFF#
MUTE_LED#
KSO2
KSI6
KSI7
KSI5

LID_SW#_2nd

JP1

1

1

3

3

5

5

7

7

9

9

11

11

13

13

15

15

17

17

19

19

21

21

23

23

25

25

27

27

29

29

ACES_88028-3000

R10_0402_5%

1 2

LID_SW#

2
4
6

8
10
12
14
16
18
20
22
24
26
28
30

2

STB_LED

4

KSI0

6

NUM_LED#

8

CAPS_LED#

10

KSI1

12

WL/BT_LED

14

LID_SW#_2nd

16

KSI2

18
20

KSI4

22
24
26
28
30

LID_SW#17,21

STB_LED32
NUM_LED#27,33

CAPS_LED#27,33
WL/BT_LED32

MDC 1.5 Conn.

JP26

1

GND1

3

IAC_SDATA_OUT

5

GND2

7

IAC_SYNC

9

IAC_SDATA_IN

11

IAC_RESET#

4.7U_0805_10V4Z@

IAC_BITCLK

131314141515161617171818191920

1 2

1

C220

2

AC97_SDOUT_MDC
AC97_SYNC_MDC

AC97_SDIN1_MDC
AC97_RST#_MDC

+3VS

1

C223

2

0.1U_0402_16V4ZMDC1.5@

1

C204

2

AC97_SDOUT_MDC20

AC97_SYNC_MDC20

AC97_SDIN120

R239

33_0402_5%

1000P_0402_50V7K MDC1.5@

+3VS

2

RES0

4

RES1

6

3.3V

8

GND3

10

GND4

AC97_BITCLK_MDC

12

R209

10_0402_5%@

TYCO_1-179396-2~DMDC1.5@

20

Connector for MDC Rev1.5

AC97_BITCLK_MDC20AC97_RST#_MDC20

12

1 2

C221
10P_0402_25V8K@

INT_KBD CONN.

KSO[0..17]33
KSI[0..7]33

KSO0
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO14
KSO11
KSO12
KSO1
KSO17
KSO13
KSO15
KSO16
KSI2
KSI3
KSI6
KSI4
KSI1
KSI5
KSI0
KSI7

Update to 18x8 angelfire keyboard matrix

CP1

KSO0

4 5

KSO2

3

KSO3

2

KSO4

100P_1206_8P4C_50V8

CP2

KSO5

4 5

KSO6

3

KSO7

2

KSO8

100P_1206_8P4C_50V8

CP3

KSO9

4 5

KSO10

3

KSO14

2

KSO11

100P_1206_8P4C_50V8

KSO[0..17]
KSI[0..7]

JP12

27

27

28

28

29

29

30

30

31

31

32

32

33

33

34

34

35

35

36

36

37

37

38

38

39

39

40

40

41

41

42

42

43

43

44

44

45

45

46

46

47

47

48

48

49

49

50

50

51

51

52

52

ACES_85203-26021

6
7
81

6
7
81

6
7
81

10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26

1
2
3
4
5
6
7
8
9

KSO12
KSO1
KSO17
KSO13

KSO15
KSO16
KSI2
KSI3

KSI6
KSI4
KSI1
KSI5

KSI0
KSI7

11/3

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26

KSO0
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO14
KSO11
KSO12
KSO1
KSO17
KSO13
KSO15
KSO16
KSI2
KSI3
KSI6
KSI4
KSI1
KSI5
KSI0
KSI7

CP4

4 5
3
2

100P_1206_8P4C_50V8

CP5

4 5
3
2

100P_1206_8P4C_50V8

CP6

4 5
3
2

100P_1206_8P4C_50V8

CP7

4 5
3
2

100P_1206_8P4C_50V8

6
7
81

6
7
81

6
7
81

6
7
81

Power button

+3VL

+3VL

12

R167

100K_0402_5%

ON/OFF#

C177

13

1

2

ON/OFF#35

1U_0603_10V4Z

U15F

14

SN74LVC14APWLE_TSSOP14

R172

P

1 2

O12I

G

100K_0402_5%

7

1U_0603_10V4Z

C183

+3VL

12

R163
100K_0402_5%

ON/OFFBTN_KBC#

13

D

Q29

2

2N7002_SOT23

G

S

1

2

ON/OFFBTN_KBC#33

D23

RB751V_SOD323

21

R179

1 2

100K_0402_5%

ON/OFFBTN#

+3VALW

ON/OFFBTN#21

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

TrackPoint CONN.T/P BOARD.

JP11

7

8

7

8

5

6

5

SP_DATA

2005/03/102006/03/10

6

3

4

3

4

1

2

1

2

E&T_6700-Q08N-00R

11/3

Compal Secret Data

Deciphered Date

+5VS +5VS

SP_CLK

+5VS

1

C116

0.1U_0402_16V4Z

2

TP_DATA33

TP_CLK33

+5VS

JP14

TP_DATA
TP_CLK

SP_DATA
SP_CLK

Title

SizeDocument NumberRev

Date:Sheet of

1
2
3
4
5
6
7
8

ACES_87212-0800

Compal Electronics, Inc.

MDC/KBD/ON_OFF/LID

LA-2821P

1

C490

0.1U_0402_16V4Z

2

3452Friday, November 25, 2005

0.5

A B C D

+5VALW

12

DOCK CONN. 184PIN

11/18

L14

KC FBM-L18-453215-900LMA90T_1812

11

MDO2+26
MDO2-26

MDO0+26
MDO0-26

M_LUMA16,18

DCD#131

RI#131

DTR#131

CTS#131
RTS#131

DSR#131

TXD131

RXD131

ON/OFF#
MDO2+

MDO2­MDO0+

MDO0­LAN_ACT#_DOCK

LANLINK_STATUS#_DOCK

D_DDCDATA
D_DDCCLK
DVI_DETECT

D_RED
D_GREEN
D_BLUE

DCD#1
RI#1
DTR#1
CTS#1
RTS#1
DSR#1
TXD1
RXD1

LPTSTB#
LPTAFD#
LPTERR#

Place them close to U50/U51/U52

ON/OFF#34

D_VSYNC16

D_HSYNC16

D_DDCDATA16

D_DDCCLK16

DVI_DETECT18

22

M_COMP16,18
M_CRMA16,18

LINE_IN_SENSE28

ACOCP_EN#47

LPTSTB#31
LPTAFD#31

LPTERR#31

33

C314

1000P_0402_50V7K

JAE_SP03-14588-PCL03

12

DOCKVINVIN

JP27A

1

C305
1000P_0402_50V7K

2

1

2

P1G1

83

1

84

2

85

3

86

4

87

5

88

6

89

7

90

8

91

9

92

10

93

11

94

12

95

13

96

14

97

15

98

16

99

17

100

18

101

19

102

20

103

21

104

22

105

23

106

24

107

25

108

26

109

27

110

28

111

29

112

30

113

31

114

32

115

33

116

34

117

35

118

36

119

37

120

38

121

39

122

40

123

41

124

42

125

43

126

44

127

45

DETECT
MDO3+

MDO3­MDO1+

MDO1­PWR_LED

1 2

R34610K_0402_5%

DVI_DDC_CLK
DVI_DDC_DAT

DVI_TX2­DVI_TX2+

DVI_TX1­DVI_TX1+

DVI_CLK­DVI_CLK+

DVI_TX0­DVI_TX0+

DOCK_ADP_SIGNAL

DOCK_ID

DOCK_ID

5/24

SLP_S529,30,36

DOCKVIN

MDO3+26
MDO3-26

MDO1+26
MDO1-26

SLP_S5#_5R

DVI_DDC_CLK18
DVI_DDC_DAT18

DVI_TX2-18
DVI_TX2+18

DVI_TX1-18
DVI_TX1+18

DVI_CLK-18
DVI_CLK+18

DVI_TX0-18
DVI_TX0+18
DOCK_ADP_SIGNAL

DOCK_ID21

R9

1 2

10K_0402_5%@

DOCK_ADP_SIGNAL

2N7002_SOT23

11/22

11/22

2

G

Q62

+3VS

R299

1 2

1K_0402_1%

R357
220K_0402_5%

SLP_S5#_5R

13

D

S

2N7002_SOT23@

ADP_SIGNAL

D

Q77

S

1U_0603_10V6K

@

DOCK_MOD_RING

LPTACK#
LPTBUSY
LPTPE
LPTSLCT
LPD7
LPD6
LPD5
LPD4
LPD3
LPD2
LPD1
LPD0
LPTSLCTIN#
LPTINIT#

USB20_N6_R

12

USB20_P6_R

12

USB20_N7_R

12

USB20_P7_R

12

SER_SHD
EXPCRD_RST#
DETECT

DOCK_MOD_TIP

13

USB20_N621
USB20_P621
USB20_N721
USB20_P721

G

C546

R671

2

1 2

22K_0402_5%@

11/23

1

2

USB20_N6
USB20_P6
USB20_N7
USB20_P7

PREP#

LPTACK#31

LPTBUSY31

LPTPE31

LPTSLCT31

LPD731
LPD631
LPD531
LPD431
LPD331
LPD231
LPD131
LPD031

LPTSLCTIN#31

LPTINIT#31

R301

0_0402_5%

R300

0_0402_5%

R304

0_0402_5%

R298

0_0402_5%

SER_SHD31

EXPCRD_RST#31

JP2

1
2

ACES_85205-0200

JP27B

46

46

47

47

48

48

49

49

50

50

51

51

52

52

53

53

54

54

55

55

56

56

57

57

58

58

59

59

60

60

61

61

62

62

63

63

64

64

65

65

66

66

67

67

68

68

69

69

70

70

71

71

72

72

73

73

74

74

75

75

76

76

77

77

78

78

79

79

80

80

81

81

82

82

165

GND

166

GND

167

GND

168

GND

169

GND

170

GND

G2

G2

RING

RING

JAE_SP03-14588-PCL03

128

128

129

129

130

130

131

131

132

132

133

133

134

134

135

135

136

136

137

137

138

138

139

139

140

140

141

141

142

142

143

143

144

144

145

145

146

146

147

147

148

148

149

149

150

150

151

151

152

152

153

153

PCIE_C_RXP4

154

154

155

155

PCIE_C_RXN4 PCIE_RXN4

156

156

157

157

158

158

159

159

160

160

161

161

162

162

163

163

164

164

171

GND

172

GND

173

GND

174

GND

175

GND

176

GND

P2

P2

DOCK_MOD_TIPDOCK_MOD_RING

TIP

TIP

L

KBD_DATA
KBD_CLK
CPPE#
PS2_DATA
PS2_CLK
DOCK_HPS#

DLINE_IN_L
DLINE_IN_R

DLINE_OUT_L
DLINE_OUT_R

PCIE_TXP4
PCIE_TXN4

R3

1 2

0_0402_5%

R4

1 2

0_0402_5%

CLK_PCIE_DOCK
CLK_PCIE_DOCK#
PREP#

VA_ON#

+5VS

C1

1 2

22U_0805_6.3V4Z@

9/15

PCIE_RXP4

12

R302
1K_0402_5%

KBD_DATA33
KBD_CLK33
CPPE#15,19
PS2_DATA33
PS2_CLK33
DOCK_HPS#29

DLINE_IN_L28
DLINE_IN_R28

DLINE_OUT_L29
DLINE_OUT_R29

PCIE_TXP421
PCIE_TXN421

CLK_PCIE_DOCK15
CLK_PCIE_DOCK#15
PREP#21,26

1

2

Note: Place C1 close to JP27.P2 pin

E

PCIE_RXP421
PCIE_RXN421

C291

0.1U_0402_16V4Z

D_RED RED

R7

1 2

0_0402_5%@

D_GREEN

R5
R6

D_BLUE

C8

1 2

0.1U_0402_16V4Z

D_BLUE18

ISO_PREP#21

44

D_BLUE
BLUE

BLUE16

ISO_PREP#

U3

5

VCC

1

A

2

B

4

OE

3

GND

FSA66P5X_SC70-5

C5

1 2

0.1U_0402_16V4Z

D_GREEN18

GREEN16

1 2

0_0402_5% @

1 2

0_0402_5% @

+3VS

D_GREEN
GREEN

ISO_PREP#

GREEN
BLUE

U2

5

VCC

1

A

2

B

4

OE

3

GND

FSA66P5X_SC70-5

D_RED18

RED16

C6

1 2

0.1U_0402_16V4Z

D_RED
RED

ISO_PREP#

+3VS+3VS

+3VALW V_3P3_LAN

12

R352

U1

5

VCC

1

A

2

B

4

OE

3

GND

FSA66P5X_SC70-5

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

STB_LED#27,32,33

SLP_S3#18,21,25,27,28,29,33,36,40,43,44

2005/03/102006/03/10

Compal Secret Data

10K_0402_5%

PWR_LED

13

D

Q61

2

G

2N7002_SOT23

S

Deciphered Date

D

R372

10K_0402_5%

LAN_ACT#_DOCK

13

D

12

Q58

2

2N7002_SOT23

G

S

LAN_ACT#

LANLINK_STATUS#_DOCK

13

D

Q59

2

G

2N7002_SOT23

S

LANLINK_STATUS#

Title

SizeDocument NumberRev

Date:Sheet of

LAN_ACT#25,26

LANLINK_STATUS#25,26

Compal Electronics, Inc.

Docking CONN.

LA-2821P

E

3552Friday, November 25, 2005

0.5

A B C D

E

+5VALW to +5VS Transfer

S
S
S
G

RUNON

+5VS+5VALW

1
2
3
4

0.1U_0402_16V4Z

U37

8

D

7

D

6

D

5

D

SI4800DY_SO8

RUNON

12

R583
470_0402_5%

1

C501

0.01UF_0402_25V7K

2

1

C271

2

S
S
S
G

+3VS+3VALW

1
2
3
4

0.1U_0402_16V4Z

1

C280
10U_0805_10V4Z

2

10U_0805_10V4Z

1

1

C510

2

2

C509

U22

8

D

7

D

6

11

22

1

2

+3VALW to +3VS Transfer

B+

J3

PAD-SHORT 2x2m

R582

330K_0402_5%

J15

PAD-SHORT 2x2m

SLP_S3

2

G

C277

5

10U_0805_10V4Z

21

12

2 1
13

D

Q75
2N7002_SOT23

S

D
D

SI4800DY_SO8

1

C514

2

10U_0805_10V4Z

+2.5VALW to +2.5VS Transfer

S
S
S
G

RUNON

+2.5VS+2.5VALW

1
2
3
4

0.1U_0402_16V4Z

1

1

C487

C458

2

10U_0805_10V4Z

2

U32

8

D

7

D

6

1

2

33

C456

5

10U_0805_10V4Z

D
D

SI4800DY_SO8

+1.8V to +1.8VS Transfer

C295

1U_0603_10V4Z

+1.8V

SI2306DS-T1 1N_SOT23

1

2

RUNON

Q53

DS

1 3

G

2

+1.8VS

1

2

C296
1U_0603_10V4Z

C290.1U_0603_50V4Z

+VCCP +3VS
+VCCP +3VALW

+3VS +3VALW
+3VS +5VS
+3VS +5VS

+1.5VS +3VS

+3VALW

+3VS

1 2

C5260.1U_0603_50V4Z@

1 2

C1550.1U_0603_50V4Z@

1 2

C1410.1U_0603_50V4Z@

1 2

C1390.1U_0603_50V4Z@

1 2

C5240.1U_0603_50V4Z@

1 2

C4190.1U_0402_16V4Z

1 2

C2900.1U_0402_16V4Z

1 2

+5VALW

12

R62
100K_0402_5%

SLP_S529,30,35

SLP_S5#21,44

SLP_S3#18,21,25,27,28,29,33,35,40,43,44

SLP_S5

SLP_S5#

SLP_S3

SLP_S3#

2

2

G

G

13

D

S

+3VL

12

R244
100K_0402_5%

13

D

S

Q9
2N7002_SOT23

Q43
2N7002_SOT23

Discharge circuit

+0.9V +1.5VS+1.8V

12

R571
470_0402_5%

13

D

R573

1 2

0_0402_5%@

SLP_S3

R572

1 2

0_0402_5%

44

Q73

2

2N7002_SOT23

G

S

12

R574
470_0402_5%

13

D

Q74

2

2N7002_SOT23

G

S

+1.8VS

12

R138
470_0402_5%

13

D

SLP_S3 SLP_S3 SLP_S3 SLP_S3

Q19

2

2N7002_SOT23

G

S

+2.5VS

12

R32
470_0402_5%

13

D

Q7

2

2N7002_SOT23

G

S

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

+3VS

12

R94
470_0402_5%

13

D

Q18

2

2N7002_SOT23

G

S

2005/03/102006/03/10

PWR_GD18,33,37,45,47

+5VS

12

470_0402_5%

13

D

2

G

S

Compal Secret Data

Deciphered Date

R93

Q16
2N7002_SOT23

12

R577
470_0402_5%

13

D

SLP_S3SLP_S5SLP_S5

2

Q72

G

2N7002_SOT23

S

Title

SizeDocument NumberRev

D

Date:Sheet of

Compal Electronics, Inc.

DC/DC Circuits

LA-2821P

3652Friday, November 25, 2005

E

0.5

R139

1K_0402_5%

+1.8VS

330_0402_5%

1 2

R158

2

B

330_0402_5%

1 2

C

Q26
MMBT3904_SOT23

E

3 1

R181

560K_0402_5%

R157

2

+3VS+3VS

B

12

1 2

C

Q25
MMBT3904_SOT23

E

3 1

+5VS

1

12

R177
180K_0402_5%

1

C190

0.1U_0402_16V4Z

2

14

U15A

P

G

SN74LVC14APWLE_TSSOP14

7

O2I

+3VL

14

P

5

G

7

1 2

47K_0402_5%

1

2

U15C

O6I

SN74LVC14APWLE_TSSOP14

R171

C176

0.1U_0402_16V4Z

+3VL+3VL

14

U15B

P

3

G

SN74LVC14APWLE_TSSOP14

1

7

C181

0.1U_0402_16V4Z

2

13

D

2

G

S

O4I

Q23
2N7002_SOT23

D20

21

RB751V_SOD323

J8

PAD-SHORT 2x2m

+3VL

+3VL

12

R184
100K_0402_5%

+3VS

12

R156
10K_0402_5%

PWR_GD

21

PWR_GD18,33,36,45,47

1

C186

0.1U_0402_16V4Z

2

+3VL

14

U15D

P

9

O8I

G

SN74LVC14APWLE_TSSOP14

7

12

R188
10K_0402_5%

13

D

Q33

2

2N7002_SOT23

G

S

VCC1_PWRGD33

UNUSED PARTS

CLK_ENABLE#15,45

VCCP_POK43

R578

1 2

0_0402_5%

R579

1 2

0_0402_5%@

R196

1K_0402_5%

PGD_IN_1

11/21

CLK_ENABLE#

+1.5VS

330_0402_5%

1 2

C502

0.1U_0402_16V4Z

PGD_IN_145

1 2

0_0402_5%@

R178

R581

1 2

C

2

B

E

3 1

+3VS

1

2

2

+2.5VS+2.5VS

R210

330_0402_5%

1 2

C

Q31

2

B

MMBT3904_SOT23

E

Q32
MMBT3904_SOT23

3 1

L

D33RB751V_SOD323

5

U33

P

O4I

1

NC

G

SN74LVC1G17DBVR_SOT23-5

3

11

Need be tune to
3msec time delay

21

R580

1 2

100K_0402_5%

C497

0.1U_0603_16V7K

+3VL

14

U15E

P

O10I

G

SN74LVC14APWLE_TSSOP14

7

+3VS

5

U34

P

2

NC

G

1

SN74LVC1G17DBVR_SOT23-5

3

2

1

C500

0.1U_0402_16V4Z

2

O4I

1

H1

H3

HOLEA

FM1

CF1

M2
HOLEA

1

HOLEA

1

FM3

FM2

1

1

1

1

CF2

CF3

1

1

H11
HOLEA

13

D

Q24

2

2N7002_SOT23

G

S

1

PGD_INPWR_GD

PGD_IN33,45

PAD1

PAD-R118x71

11/21

1

M1
HOLEA

1

1

H4

H2

HOLEA

HOLEA

1

1

FM4

CF4

H25
HOLEA

1

1

H12
HOLEA

1

1

1

FM5

CF5

H23
HOLEA

1

H26
HOLEA

1

1

1

1

FM6

CF6

H21
HOLEA

1

1

H5
HOLEA

1

H16
HOLEA

1

H8

H19

H27

1

H14
HOLEA

1

CF12

HOLEA

1

H20
HOLEA

1

1

H9
HOLEA

1

CF8

H24
HOLEA

H17
HOLEA

1

H15
HOLEA

1

1

CF10

1

H6

HOLEA

HOLEA

HOLEA

1

1

H13

H18

HOLEA

HOLEA

1

1

CF11

CF9

CF7

1

H10
HOLEA

1

1

1

CPU

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2005/03/102006/03/10

Compal Secret Data

Deciphered Date

Title

SizeDocument NumberRev

Date:Sheet of

Compal Electronics, Inc.

POK CKT

LA-2821P

3752Friday, November 25, 2005

0.5

5 4 3 2

DD

1

APL5508
AC
Adapter
in

VIN

LM358
Thermal
Protector

+3VALWP

LDO

(2.5V)

SWITCHADP_EN#

B+B+

CC

MAINPWON

ENBL2ENBL1

TPS51020
DC/DC

VL

+3VALWP

VL

(3V/5V)

VIN

+5VALWP

APL5151
LDO
(3V)

SHDN#

VL

+3VLP 0.1A

+2.5VALWP 0.4A

+5VS

VCCSHDN#

ISL6260&ISL6208

PWR_GD

DC/DC
(CPU_CORE)

BQ24703
Charger

B+

MAX8743
DC/DC
(1.05V/1.5V)

+1.5VSP 4.2A

CPU_CORE
( 44A)

BB

Battery

BATSELB_A

SLP_S3#

ENBL1/ENBL2

+1.05V_VCCP 6.4A

+5VALWP

Selector
Circuit

BATSELB_A#

Battery A
8 Cell

Battery B
8 Cell

B+

TPS51116
DC/DC

VCC

+1.8VP 7A

(+1.8VP/+0.9VSP)

SWITCH

AA

BATT

SWITCHSWITCH

Battery
Connector
A

BATT_A

BATT_B

Battery
Connector
B

SLP_S3#/SLP_S5#

Title

SizeDocument NumberRev

Date:Sheet of

S3/S5

POWER BLOCK DIAGRAM

2

+0.9VP 2A

3852Friday, November 25, 2005

1

A B C

11

D

12

PR1
15K_0402_5%

VIN

PJP13

3

GND1

4

GND2

6

GND_1

7

GND_2

8

GND_3

9

GND_4

FOX_JPD113E-LB103-7F

22

33

SINGAL

PWR1

PWR2

5

1

2

ADP_SIGNAL

ADPIN

12

12

PC1

100P_0402_50V8J

PC2
1000P_0402_50V7K

PL1

FBMA-L18-453215-900LMA90T_1812

1 2

12

12

PC4

PC3

1000P_0402_50V7K

100P_0402_50V8J

44

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2005/03/102006/03/10

Compal Secret Data

Deciphered Date

C

Title

SizeDocument NumberRev

Custom
Date:Sheet of

Compal Electronics, Inc.

DCIN

LA-2821

D

3952Friday, November 25, 2005

A B C

D

11

22

33

44

1 2

PR16 47K_0402_5%

SLP_S3#

VIN

PQ6

DTA144EUA_SC70

47K

47K

2

1 2

PC10

+3VL

47P_0402_50V8J

G

S

PQ91

@

RHU002N06_SOT323

PR62

13

2

@

1N4148_SOD80

13

D

12

PR55
130K_0402_1%

12

10K_0603_1%

12

PC138

PD32

1 2

P2

12

PR44

100K_0603_1%

PR240

2.15K_0402_1%

1 2

12

PR49

12.4K_0603_0.1%

12

PC26

0.022U_0402_16V7K

1
2
3 6

12

PR14
200K_0402_5%

0.1U_0603_16V7K

PR20
150K_0402_5%

1 2

1N4148_SOD80

12

PR376

0_0402_5% @

PQ4
AO4407_SO8

4

PD33

ADP_EN#47

12

CHGLIM47

CHGCTRL33,41

ACDET

PR42

1 2

330K_0402_5%

VL

8

3

P

+

2

-

G

4

PR56

1 2

1M_0402_5%

8

PU5B

5

P

+

O

6

-

G

LM393DG_SO8

4

PR67

1 2

33K_0402_1%

4

REF

5

ANODE

LMV431ACM5X_SOT23-5

8
7

5

PU5A

1

O

LM393DG_SO8

7

VL

PU6

CATHODE

NC
NC

P2

ACDRV#

PR31

1 2

191K_0402_1%

3
2
1

8
7

5

ADP_PRES

+3VL

12

PR45

+3VL

AC_CHG

1.24VREF

PC15

10K_0402_1%

2

PQ5

AO4407_SO8

1
2
36

4

PR17

0_0402_5%

1 2

12

PR35

1 2

100K_0402_1%

1U_0603_6.3V6M

PC20

+3VL

12

PC22

0.1U_0402_10V6K

5

PU4
SN74LVC1G17DBVR_SOT23-5

P

O4I

1

NC

G

3

12

PC24

@

0.1U_0402_16V7K

12

PR63

47K_0402_1%@

RHU002N06_SOT323

+3VL

12

1U_0603_6.3V6M

AC_CHG41

PQ12

2

G

AC_CHG

BQ24703VREF

12

12

13

D

S

P4

B+

PR372

0.015_2512_1%

1 2

12

PR338
100_0402_1%

1 2

PC198

1U_0603_6.3V6M

1 2

PR339
1K_0402_1%

PR29

12

1K_0402_1%

ALARM

PR32

12

100K_0402_5%

PR36

100K_0402_1%

12

PC18

PR41

4.7U_0805_6.3V6K

80.6K_0402_1%

PC21

150P_0402_50V8J

ADP_PRES18,25,33,41,42,47

+3VL

12

PR52

4.7K_0402_5%
PR58

1 2

100K_0402_5%

BQ24703VREF

12

PR61
100_0402_5%

13

D

PQ13

2

RHU002N06_SOT323

G

S

PL2

FBM-L11-322513-151LMAT_1210

1 2

ACN47

PU2

8

ACN
ACP
ACDET

ENABLE
ACSEL
ALARM
SRSET
ACSET
ACPRES27VHSP
IBAT
VREF

COMP
NC1
NC2

BQ24703_QFN28

12

PR43
150_0402_1%

12

PC23

4.7U_0805_10V6K

ALARM41

ACDRV#

BATDRV#

BATSET

BATDEP

9

26

5
28
19

2

3
13

4

7
10
11

12

PQ3
AO4407_SO8

1
2
3 6

P2

PR15

0_0402_5%

1 2

12

12

PC12

PC11

VCC

PWM#

SRN

BATP

GND

10U_1206_25VAK

RLZ16B_LL34

ACDRV#

25
22
21
16

SRP

15
12
24

18

VS

20
6

1
17
23

NC4

14

NC3

12

4.7U_1206_25V6K
PD6

PC14

2 1

DH_CHG

BATT BATT

1U_0805_25V4Z

12

12

12

75K_0402_1%

12

PC25

100P_0402_50V8J

15K_0402_1%

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

8
7

5

4

CHG_B+

PR26

0_0402_5%

12

16

243

PQ8
SI4835BDY-T1-E3_SO8

578

LX_CHG

1 2

15U_PLC1045P-150A_3.7A_20%

12

PD8
EC31QS04

SE_CHG+

SE_CHG-

CV=16.8V (8 CELLS LI-ION)
CC=3A

12

PR47
604K_0603_0.1%

PR51

604K_0402_1%

PR59

PR64

2005/03/102006/03/10

12

12

12

PC205

470P_0402_50V7K

PR50
10K_0603_0.1%

PR57
47K_0603_0.5%

Compal Secret Data

Deciphered Date

C

BATT

PL3

PR33

0.015_2512_1%

1 2

12

PR38

3K_0402_1%

PC19

1 2

0.1U_0402_16V7K

BATT

12

12

12

PR39

PC17

PC16

3K_0402_1%

10U_1206_25VAK

4.7U_1206_25V6K

Title

SizeDocument NumberRev

Custom

Date:Sheet of

Compal Electronics, Inc.

Charger

LA-2821

D

4052Friday, November 25, 2005

A B C

+3VL

D

11

+3VL

BATSELB_A

BATSELB_A#

22

PC28

1 2

1000P_0402_50V7K

PC30

1 2

1000P_0402_50V7K

PR72

1 2

22K_0402_5%

RHU002N06_SOT323

PR73

1 2

22K_0402_5%

PQ17

PQ18

2

G

2

G

13

D

RHU002N06_SOT323

S

13

D

S

PR70

47K_0402_5%

1 2

RHU002N06_SOT323

ALARM40

PQ19

+3VL

13

D

S

5NC1

BATSELB_A#33

BATSELB_A#

A2Y

3

PR83

1 2

470K_0402_5%

+3VL

5

P

2

G

3

100K_0402_5%

+3VL

5

SN74LVC1G17DBVR_SOT23-5

PU12

P

2

O4I

1

NC

G

3

AC_CHG40

PU14

O4I

1

NC

SN74LVC1G17DBVR_SOT23-5

PR84

10K_0402_1%

1 2

BATCON33

33

CHGCTRL33,40

44

CFET_A
CFET_B

PD14

1N4148_SOD80

PD17

2
3

RB715F_SOT323

12

12

PC31

0.22U_0402_10V4Z

1

12

PR237

5

PU8

1

P

INB

2

INA

G

74LVC1G02_04_SOT353

3

2

ADP_PRES18,25,33,40,42,47

G

PU10

P

G

BATSELB_A

4

SN74LVC1G14DCKR_SC70-5

PQ30

RHU002N06_SOT323

S

G

ADP_PRES

4

O

+3VL

5NC1

PU9

P

4

A2Y

G

SN74LVC1G14DCKR_SC70-5

3

D

13

2

12

PC197

220P_0402_50V7K

PR82

BATSELB_A#

1

INB

2

INA

1 2

220K_0402_5%

PC27

5

PU7

P

4

O

G

74LVC1G02_04_SOT353

3

+3VL

PU11

5

1

P

IN1

O

2

IN2

G

3

+3VL

PU13

5

1

P

IN1

O

2

IN2

G

3

12

0.1U_0402_10V6K @

BATT_B

RHU002N06_SOT323

+3VL

4

SN74AHC1G08DCKR_SC70

RHU002N06_SOT323

4

SN74AHC1G08DCKR_SC70

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

S

PR78

1 2

10K_0402_5%

BATT_IN

1 2

BATT_IN

Issued Date

BATT_A

PQ16

D

13

G

2

CFET_A

PQ26

2

G

PR88

10K_0402_5%

CFET_B

PQ34

2

G

PD9

2
3

RB715F_SOT323

1

PR68

1 2

100_0402_5%

12

PC29

RHU002N06_SOT323

12

PR71

1.5M_0402_5%

0.1U_0603_50V4Z

BATT

12

PR74
470K_0402_5%

1

2

PQ21

3

12

PD12

PR76

1 2

10K_0402_5%

1N4148_SOD80

13

D

RHU002N06_SOT323

S

BATT

12

PR81
470K_0402_5%

12

10K_0402_5%

13

D

RHU002N06_SOT323

S

2

PD16

1 2

1N4148_SOD80

1

3

2

13

D

S

13

D

S

PQ23

G

PR87

PQ31

2

G

RHU002N06_SOT323

2005/03/102006/03/10

PR75

PMBT2222A_SOT23-3

470K_0402_5%

1 2

PR85

Deciphered Date

C

1 2

470K_0402_5%

PQ29

PMBT2222A_SOT23-3

Compal Secret Data

PQ15

DS

1 2

1 3

G

2

PD13

21

B540C_SMC
PQ24

AO4407_SO8

1
2
3 6

4

PQ27

AO4407_SO8

1
2
3 6

4

PD15

B540C_SMC

PR69

0_0402_5%

PD11
RLZ6.2C_LL34

2 1

RHU002N06_SOT323

RHU002N06_SOT323

8

8

7

7

5

5

8

8

7

7

5

5

21

RHU002N06_SOT323

RHU002N06_SOT323

1 2

BATT_IN

AO4407_SO8

AO4407_SO8

BATT_IN

BATT_IN

PD10
1N4148_SOD80

PQ20

13

D

2

G

S

PQ22

13

D

12

S

PR77

4.7K_0402_5%

12

1

PR79

2
36

470K_0402_5%

BATT_A

PQ25

2

G

4

PQ28

PQ32

PQ33

4

2

G

2

G

12

PR80

1

470K_0402_5%

2
36

BATT_B

12

PR86

4.7K_0402_5%

13

D

S

13

D

S

Title

SizeDocument NumberRev

Custom

Date:Sheet of

Compal Electronics, Inc.

Battery selector

LA-2821

D

4152Friday, November 25, 2005

5 4 3 2

1

+5VALWP

+3VALWP

B++

PL4

FBM-L11-322513-151LMAT_1210

12

B+

12

PC32

12

DD

VL

ADP_PRES

2

PQ40

2

+3VALW_POK

12

PC40

1 2

PR103

@

0_0402_5%

1 2

PC46

820P_0603_50V7K

13

D

S

+3VLP

12

PR369

100K_0402_5%

RHU002N06_SOT323

4.7U_0805_10V4Z

12

12

PR105

1M_0402_5%@

KBC_PWR_ON33

2

G

PQ41

RHU002N06_SOT323

PQ42
SI2301BDS-T1-E3_SOT23-3

12

PR365

100K_0402_5%

2

G

PQ98

PR101

0_0402_5%

VL

PC42

+5VALWP

PR187
154K_0603_1%

1 2

12

CC

MAINPWON46

0.47U_0603_10V7K

1 2

+5VALWP

VL

12

PR107

13

D

100K_0402_5%

S

12

PC53

0.33U_06 03_10V7 K@

2

G

13

D

G

S

RHU002N06_SOT323

PQ101
SI2301BDS-T1-E3_SOT23-3

1 3

12

PC52

1U_0603_10V6K

+3VALW_POK

PQ39

RHU002N06_SOT323

APL5151_SOT23-5

1

Vin

SHDN#3BP

PU16

5

Vout

4

GND

2

BB

VL

12

PC51

1U_0603_10V6K

VL

12

PR115

AA

100K_0402_5%

PR90

PR99

PR335
0_0402_5%

1 2

PC47

820P_0603_50V7K

2

13

D

S

4700P_0603_50V7K

1 2

49.9K_0402_1%

1 2

10K_0402_1%

PC37

4700P_0603_50V7K

1 2

B++

PC410.1U_0402_16V7K

12

PR106

1M_0402_5%

13

+3VALWP

330_0402_5%

PR91

12

2.7K_0402_1%

PR96

12

PR102

100K_0402_5%

1 2

12

PC48

12

PR110

PQ37

8

G2

7

D1/S2/K

6

D1/S2/K

5

D1/S2/K

12

12

PR97

17.4K_0402_1%

23

25

PU15

1

INV1

2

TRIP1

COMP1

12

PGOOD

22

VREG5

21

REG5_IN

6

DDR#

TPS51020DBTR_TSSOP30

8

REF_X

9

ENBL1

10

ENBL2

3

SSTRT1

13

SSTRT2

14

COMP2

15

INV2

SKIP#

4

4700P_0402_25V7K

3.9K_0402_1%

PR108

0_0402_5%

1 2

1 2

@

12

PC35

12.7K_0402_1%

7

10K_0402_5%

24

VBST1

VIN

OUT1_U

OUT1_D

VO1_VDDQ

OUTGND1

OUT2_U

OUT2_D

VBST2

OUTGND2

GND

2.2U_1206_25V7K

30
29
28

LL1

27
5
26

17
18

LL2

19
16
11

VO2

20

PR98

TRIP2

PR109

ADP_PRES18,25,33,40,41,47

BST_5V

DH_5V_1

DL_5V

DH_3.3V_1

DL_3.3V

BST_3.3V

PC43

0.1U_0603_50V4Z

PR100

0_0402_5%

1 2

12

PC36

0.1U_0603_50V4Z

12

DH_5V_2

12

LX_3.3V

PR104
0_0402_5%

DH_3.3V_2

LX_5V

8
7
6
5

S1/A

AO4912_SO8

G2
D1/S2/K
D1/S2/K
D1/S2/K

AO4912_SO8

D2
D2
G1

LX_5V47

PQ38

D2
D2
G1

S1/A

1
2
3
4

10U_PLC1045-100_3.6A_20%

1
2
3
4

12

PC50

1 2

12

3300P_0603_50V7K

29.4K_0402_1%

PR111

PR112

330_0402_5%

PR113

1 2

10K_0402_1%

12

12

PC34

PC33

10U_1206_25VAK

2200P_0402_50V7K

PL5

1 2

12

12

PC44

PC45

4.7U_1206_25V6K
2200P_0402_50V7K

PL6

10U_PLC1045-100_3.6A_20%

1 2

1

1

+

+

PC39

PC38

2

2

220U_D3L_6.3M_R40

150U_D2_6.3VM_R45

1

+

2

PC199

220U_D3L_6.3M_R40

12

PC120

@

1500P_0402_50V7K

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2005/03/102006/03/10

Compal Secret Data

Deciphered Date

2

Title

SizeDocument NumberRev

Custom

Date:Sheet of

Compal Electronics, Inc.

3.3VALW/5VALW

LA-2821

1

4252Friday, November 25, 2005

A B C

MAX8743_B+

12

12

PC57

11

5

PQ79

AO4404_SO8

PL22

12

PC145

12

4.7U_0805_6.3V6K
PR329

12

PR257
100K_0402_1%

12

PC72

3.3UH_PCMB104E-3R3MS_11A_20%

5.1K_0402_1%

12

AO4702_SO8

PU20

APL5508-25DC-TRL_SOT89-3

2

IN

GND

1

1U_0603_10V6K

+1.05V_VCCP

1

+

PC191

2

22

33

330U_D2E_2.5VM

+3VALWP

D8D7D6D

S1S2S3G

4

5

D8D7D6D

PQ78

S1S2S3G

4

(400mA,40mils ,Via NO.= 1)

+2.5VALWP

3

OUT

12

SLP_S3#18,21,25,27,28,29,33,35,36,40,44

PC189

2200P_0402_50V7K

DH_1.05V_2

DL_1.05V

SLP_S3#

PC73

4.7U_0805_6.3V6K

+5VALW

1 2

PR342

0_0402_5%

1.5VSP/ +1.05V_VCCP/+2.5VALWP

4.7U_1206_25V6K

CHP202UPT_SOT323-3

PC192

0.1U_0603_50V4Z

PR370

0_0402_5%@

1 2

PR260

100K_0402_5%

PR343

47K_0402_5%

1 2

2

G

12

PC201

0.001U_0402_50V7M@

PD31

12

1 2

PR331
0_0402_5%

12

2

G

13

D

S

RHU002N06_SOT323

1

2

3

1 2

BST_1.05V_2

PR330

0_0402_5%

DH_1.05V_1
LX_1.05V LX_1.5V

MAX8743EEI+T_QSOP28~N

VCC_MAX8743

13

D

S

PQ95

RHU002N06_SOT323

PQ94

1U_0805_50V4Z

BST_1.05V_1

25
26
27

24
28

11

0_0402_5%

PC190

PC194

0.1U_0603_50V4Z

PU28

1
2

0_0402_5% @

PR328

12

BST1
DH1
LX1

DL1
CS1

OUT1
FB1

ON1

PR265

12

OVP

8

12

PR268

0_0402_5%

1 2

VCC_MAX8743

12

4

1U_0805_16V7K

V+

GND

23

20_0603_5%

PC195

22

VCC

SKIP

6

2VREF

12

12

PR332

9

VDD

UVP

BST2

DH2

LX2
DL2

CS2

OUT2

FB2

ON2

PGOOD

TON

ILIM2
ILIM1

REF

PR262

10

20K_0402_1%

PR263

0_0402_5%

12

PC147

0.22U_0603_10V7K

+5VALW

BST_1.5V_1

21
19

18
17
20
16

15
14
12

7
5

13
3

12
12

PR266

100K_0402_1%

12

BST_1.5V_2

PR327

0_0402_5%

1 2

DH_1.5V_1

12

PC186

4.7U_1206_16V4Z

1 2

12

PR267

100K_0402_1%

PC144

0.1U_0603_50V4Z

12

PR333
0_0402_5%

PR319

0_0402_5%

DL_1.5V

12

AO4912_SO8

1

D2

2

D2

D1/S2/K

3

G1

D1/S2/K

4

D1/S2/K

S1/A

DH_1.5V_2

VCCP_POK37

RHU002N06_SOT323

8

G2

7
6
5

PQ86

13

D

S

PQ93

RHU002N06_SOT323

3.3UH_PCMC063T-3R3MN_6A_20%

1 2

PR371

0_0402_5%@

12

2

G

13

D

PQ92

S

PL23

FBM-L11-322513-151LMAT_1210

PL21

SLP_S3#

PR259

100K_0402_5%

12

PR341

47K_0402_5%

12

2

G

PR340
0_0402_5%

12

PC200

0.001U_0402_50V7M@

12

D

12

12

4.7U_1206_25V6K

PC188

2200P_0402_50V7K

12

PR258

PC185

1

+

PC203

2

220U_B2_2.5VM

5.1K_0402_1%

12

PR261

10K_0402_1%

+5VALW

12

SLP_S3#18,21,25,27,28,29,33,35,36,40,44

B+

+1.5VSP

PJP1

+1.5VSP

+1.8VP

+1.05V_VCCP

44

+0.9VP

1 2

PAD-OPEN 3x3m
PJP3

PAD-OPEN 4x4m

1 2

PJP5

PAD-OPEN 4x4m

1 2

PJP12

PAD-OPEN 4x4m

1 2

PJP7

1 2

PAD-OPEN 3x3m

+1.5VS

(4A,160mils ,Via NO.=8)

(7A,280mils ,Via NO.= 14)

+1.8V

(6A,240mils ,Via NO.= 12)

+VCCP

(2A,80mils ,Via NO.= 4)

+0.9V

+5VALWP

+3VALWP

+3VLP

+2.5VALWP

PJP2

1 2

PAD-OPEN 4x4m
PJP4

1 2

PAD-OPEN 4x4m

PJP6

2 1

PAD-OPEN 2x2m

PJP11

2 1

PAD-OPEN 2x2m

+5VALW

(4.5A,180mils ,Via NO.= 9)

+3VALW

(3A,120mils ,Via NO.= 6)

(100mA,20mils ,Via NO.= 1)

+3VL

(400mA,40mils ,Via NO.= 1)

+2.5VALW

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2005/03/102006/03/10

Compal Secret Data

Deciphered Date

C

Title

SizeDocument NumberRev

Custom

Date:Sheet of

Compal Electronics, Inc.

2.5VALW/1.5VS/1.05VCCP

LA-2821

D

4352Friday, November 25, 2005

5

DD

+1.5VS

12

PR242

0_1206_5%

12

PC127

10U_0805_10V4Z

CC

+0.9VP

V_DDR_MCH_REF7,13,14

12

12

PC129
22U_1206_6.3V6M

PR324

0_0402_5%

1 2

PC128

10U_0805_10V4Z

12

+5VALWP

BB

4

1

VLDOIN

2

VTT

3

VTTGND

4

VTTSNS

5

GND

6

MODE

7

VTTREF

8

PC130

0.033U_0402_16V7K

COMP

9

VDDQSNS

10

VDDQSET

TPS51116_HTSSOP20

VBST

DRVH

DRVL

PGND

PGOOD

3

PU27

BST_1.8V_1 BST_1.8V_2

20

DH_1.8V_1

19

18

LL

17

16

15

CS

14

V5IN

13

12

S5

11

S3

PR231

0_0402_5%

1 2

PR230

0_0402_5%

1 2

LX_1.8V

DL_1.8V

12

PC122

4.7U_0805_10V6K

PR234

0_0402_5%

PR314

0_0402_5%

@

PR236

0_0402_5%

PR323

0_0402_5%@

PC121

0.1U_0603_50V4Z

1 2

DH_1.8V_2

12

PC123

0.001U_0402_50V7M

12

12

12

12

2

5

D8D7D6D

PQ63
AO4404_SO8

S1S2S3G

4

1 2

PQ64
AO4702_SO8

12

PL16

1.8U_D104C-919AS-1R8N_9.5A_30%

5

D8D7D6D

S1S2S3G

4

12

PR233

20K_0603_1%

PR232

3_0402_5%

SLP_S5#21,36

SLP_S4#21

SLP_S3#18,21,25,27,28,29,33,35,36,40,43

SLP_S5#21,36

DDR_B+

PC125

2200P_0402_50V7K

FBM-L11-322513-151LMAT_1210

12

12

PC124
10U_1206_25VAK

1

+

2

+5VALWP

1

PL15

12

B+

+1.8VP

12

PR388
0_0402_5%

PC204

220U_D2_4VM

12

@

PC133

22P_0402_50V8J

1 2

PR389

0_0402_5%

12

14.3K_0603_0.1%
PR238

+1.8V

12

12

PC136

AA

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2005/03/102006/03/10

3

12

PC137

0.001U_0402_50V7M

@

@

Compal Secret Data

Deciphered Date

0.001U_0402_50V7M

Title

SizeDocument NumberRev

B

2

Date:Sheet of

Compal Electronics, Inc.

1.8V/0.9VS

LA-2821

10K_0603_0.1%
PR239

4452Friday, November 25, 2005

1

8 7 6 5 4 3

2

1

+CPU_B+

HH

PQ80

FDS6688S_SO8

3 5

PQ81

PQ84

FDS6688S_SO8

SI7840DP-T1-E3_SO8

241

5

D8D7D6D

S1S3G

S

4

2

3 5

241

5

D8D7D6D

S1S3G

S

4

2

D8D7D6D

PQ82

S1S3G

S

FDS6688S_SO8

2

PQ83
SI7840DP-T1-E3_SO8

D8D7D6D

S1S3G

S

2

+CPU_B+

PR269
10_0603_5%

0.01U_0402_25V7K
PC156

19

VSS

4

VR_TT#

3

RBIAS

5

NTC

6

SOFT

28

VID0

29

VID1

30

VID2

31

VID3

32

VID4

33

VID5

34

VID6

37

DPRSTP#

36

DPRSLPVR

1

PSI#

2

PGD_IN

38

CLK_EN#

35

VR_ON

12

VSEN

13

RTN

11

VDIFF

10

FB

9

COMP

8

VW

DROOP

14

PR310

6.19K_0603_1%

330P_0402_50V7K

1 2

12

+3VS

PR275

1.91K_0603_1%

1 2

20

VDD

PC183

PU31

12

18

VIN

DFB15VO

12

40

39

3V3

PGOOD

PWM1

ISEN1

PWM2

ISEN2

FCCM

PWM3

ISEN3

OCSET

VSUM

16

PR311

1K_0402_1%

1 2

PR326
0_0402_5%

ISL6260CRZ-T_QFN40

27

23

26

22

24

25

21

7

17

PR303

VO

12

VSUM

4.53K_0402_1%

PWM1

ISEN1

PWM2

ISEN2

12

PC178

VGATE_INTEL7,21

PR312

12

0_0402_5%

1 2

0.22U_0603_16V7K

12

PC182

1 2

0.1U_0402_16V7K

+5VS

PR297

11.5K_0402_1%

PC177

1000P_0402_50V7K

12

PH3

12

12

PR301

3K_040 2_1%

12

PR308

1K_0402_1%

@

10KB_0603_5%_ERTJ1VR103J

GG

+5VS

10_0603_5%

PR273

1 2

FF

PC184

NTC

12

0.01U_0402_16V7K

H_PROCHOT#4

EE

H_DPRSTP#4,20

DD

PGD_IN_137

DPRSLPVR7,21

CLK_ENABLE#15,37

PR279

4.22K_0603_1%

CPU_VID05
CPU_VID15
CPU_VID25
CPU_VID35
CPU_VID45
CPU_VID55
CPU_VID65

H_PSI#5

PGD_IN33,37

0.015U_0402_16V7K

0_0402_5%
0_0402_5%

0_0402_5%

PWR_GD18,33,36,37,47

PR278

147K_0402_1%

12

PC164

PR282
PR284
PR286

PR289

0_0402_5%

PR292

0_0402_5%

PR295

0_0402_5%

PR277

0_0402_5%

12

12

12

PR283

12

PR285

12

PR288

0_0402_5%

12

12

PR294

12

VCCSENSE5

+VCC_CORE

PR315

100_0402_1%

VSSSENSE5

CC

BB

100_0402_1%

12

12

PR316

PR298

180_0603_1%

PC179

1 2

220P_0402_25V8K

PC173

1800P_0402_50V7K

1 2

12

1000P_0402_50V7K

1.2K_0402_1%

1 2

PC176

0.022U_0402_16V7K

1000P_0402_50V7K
PR307

6.98K_0402_1%

12

PC158

1U_0603_10V6K

12

PH2

12

470KB_0402_5%_ERTJ0EV474J

PR281

12

0_0402_5%

12

0_0402_5%

12

0_0402_5%

12

PR291

12

499_0402_1%

0_0402_5%

12

PR296

12

0_0402_5%

PC167

12

PC168

51K_0603_1%

PC180

12

12

0_0402_5%

PR304

PR299

12

12

1000P_0402_50V7K

PR300

12

NTC

12

+5VS

12

PC154

1U_0603_10V6K

PU30

5
6
2
3

ISL6208CRZ-T_QFN8

+5VS

VCC
FCCM
PWM
GND

12

PC163

1U_0603_10V6K

PU32

5

VCC

6

FCCM

2

PWM

3

GND

ISL6208CRZ-T_QFN8

BOOT
UGATE
PHASE
LGATE

BOOT
UGATE
PHASE
LGATE

PR270

0_0402_5%

12

BST_C PU1_2

BST_C PU1_1

1

DH_CPU1

8

LX_CPU1

7
4

0_0402_5%

BST_C PU2_1

1

DH_CPU2

8

LX_CPU2

7
4

DL_CPU1

PR280

DL_CPU2

PC155

0.22U_0603_16V7K

1 2

12

BST_C PU2_2

0.22U_0603_16V7K

1 2

PC165

12

PC152

PC151

10U_1206_25VAK

2200P_0402_50V7K

12

12

PC153

10U_1 206_2 5VAK

0.36UH_MPC1040LR36_24A_20%

1 2

12

PC150

0.01U_0402_50V4Z

5

PR272

10K_0402_1%

4

1 2

PR274

5.11K_0402_1%

1 2

VSUM

12

12

PC159

0.01U_0402_50V4Z

12

PC162

PC161

PC160

10U_1206_25VAK

10U_1206_25VAK

2200P_0402_50V7K

0.36UH_MPC1040LR36_24A_20%

5

PQ85

4

FDS6688S_SO8

10K_0402_1%

1 2

PR293

5.11K_0402_1%

1 2

VSUM

PL24

FBMA-L18-453215-900LMA90T_1812

1 2

PL19

PC157

0.22U_0603_16V7K

12

12

PR317

@

0_0402_5%

+CPU_B+

12

PL20

1 2

PR290

PC166

0.22U_0603_16V7K

PR318

@

0_0402_5%

B+

1

+

PC196

68U_25V_M

2

+VCC_CORE

PR271
10_0402_1%

1 2

VO

+VCC_CORE

PR287
10_0402_1%

1 2

12

12

VO

AA

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

2005/03/102006/03/10

RIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Compal Secret Data

Deciphered Date

3

Compal Electronics, Inc.

Title

SizeDocument NumberRev

C

LA-2821

Date:Sheet of

2

CPU_CORE

4552Friday, November 25, 2005

1

A B C

PH1 under CPU botten side :

CPU thermal protection at 90 +-3 degree C

11

PCN2

1

BATT+

SMD
SMC

RES

GND

TYCO_C-1746706_6P

22

TS

2
3
4
5

6

100_0402_5%

EC_SMD_A

EC_SMC_A

PR188

12

PR189

100_0402_5%

PR334

12

330K_0402_5%@

3

1

2

PD27

12

@SM05_SOT23

PR186
1K_0402_5%

12

EC_SMD_A1
EC_SMC_A1

2

3

1

THM_MAIN#33

PD26
SM24_SOT23 @

VMB_A

PL13

FBMA-L18-453215-900LMA90T_1812

1 2

12

PC104
1000P_0402_50V7K

AB1A_DATA33
AB1A_CLK33

12

PC105

0.01U_0402_50V4Z

0.22U_0603_10V7K

BATT_A

PC107

Recovery at 43 +-3 degree C

+5VALW

12

CPU

PH1

10K_TH11-3H103FT_0603_1%

PR190
15K_0603_1%

1 2

PR192

2.55K_0603_1%

1 2

PR191
150K_0402_1%

PR193

150K_0402_1%

+5VALW

12

12

12

12

PC108
1000P_0402_50V7K

PR185

47K_0402_1%

1 2

5

+

6

-

8

PU21B

P

0

G

LM358ADR_SO8

4

7

2

G

D

13

D

S

PQ56
RHU002N06_SOT323

1

0

+5VALW

12

PC106

8

PU21A

3

P

+

2

-

G

LM358ADR_SO8

4

MAINPWON42

0.1U_0402_10V6K

VMB_B

PCN3

1

BATT+

33

44

SUYIN_20163S-06G1-K

SMD
SMC

GND

B/I
TS

EC_SMD_B

2

EC_SMC_B

3

AB/I_B

4

TS_B

5
6

PR200

100_0402_5%

2

+3VL

3

PD19
SM24_SOT23 @

1

PR194

12

1K_0402_5%

1 2

PR195
PR197
1K_0402_5%

1 2

12

12

PR201

@SM05_SOT23

100_0402_5%

PD20

3
2

EC_SMD_B1

EC_SMC_B1

210K_0402_1%

1

PL14

FBMA-L18-453215-900LMA90T_1812

1 2

12

PC109
1000P_0402_50V7K

THM_MBAY#33

AB1B_DATA33
AB1B_CLK33

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

12

PC110

0.01U_0402_50V4Z

BATT_B

2005/03/102006/03/10

Compal Secret Data

Deciphered Date

C

Title

SizeDocument NumberRev

Custom
Date:Sheet of

Compal Electronics, Inc.

BATTERY CONN

LA-2821

D

4652Friday, November 25, 2005

5 4 3 2

DD

8

PU24A

3

P

+

1

0

2

-

G

LM358ADR_SO8

4

PR210

0_0402_5%

1 2

PR209

12

PC118

1U_0805_50V4Z

CC

ADP_SIGNAL

BB

12

PR344
137K_0402_1%

PR346
1M_0402_5%

1 2

12

PR345
10K_0603_1%

12

PR379

AA

442K_0402_1%

13

D

G

PQ103

S

RHU002N06_SOT323

12

PR367

0_0402_5%

2

MXM_CD1#18,21

PQ100

@

RHU002N06_SOT323

13

D

S

2

G

VIN

12

12

PR348

10K_0402_1%

10K_0402_1%

RHU002N06_SOT323@

PR347

22.6K_0402_1%

VIN

12

PR381

40.2K_0402_1%

12

PR349

12

2

G

PQ104

B+

0_0402_5%

NDS0610_SOT23

12

PR386

29.4K_0402_1%

13

D

@

S

P4

1 2

PR213

10K_0402_1%

12

PC119

0.1U_0402_16V7K

12

PR226
0_0402_5%

PQ96

S

G

12

PR382

13

D

PQ106

S

@

RHU002N06_SOT323

1 2

D

2

5

+

6

-

68K_0402_5%

@

2

G

PR211

6.81K_0402_1%

1 2

PR214

100K_0603_0.5%

4

REF

5

ANODE

ADP_PRES18,25,33,40,41,42

13

VIN

8

PU33A

3

P

+

O

2

-

G

LM393DG_SO8

4

PR350

1M_0402_5%

1 2

8

PU33B

P

7

O

G

LM393DG_SO8

4

+3VALW

5
6

0.22U_0603_16V7K

PU26

3

CATHODE

2

NC

1

NC

LMV431ACM5X_SOT23-5

1 2

2

B

PR373

124K_0402_1%

E

1

12

PR351

47K_0402_5%
PD34

1 2

1N4148_SOD80

ADP_EN#40

8

PU24B

P

+

0

-

G

LM358ADR_SO8

4

1 2

PC116

C

PQ102

MMBT3904_SOT23

3 1

12

PR354
10K_0402_5%

VIN

12

PR352
220K_0402_5%

PR212

7

1 2

0_0402_5%

12

PR220

7.87K_0402_1%

12

PR222

422_0603_1%

MMBT3906_SOT23

PQ59

12

PR216

2K_0402_5%

E

3

B

12

2

PR252

C

3.9K_0402_5%

1

12

PR249

PD38

CH355PT_SOD323-2

+3VALW

12

13

D

2

G

12

S

PR368

220K_0402_5%

12

ADP_ID33

PR353
47K_0402_5%

ADP_EN33

PQ97
RHU002N06_SOT323

3.9K_0402_5%

PR224

100K_0402_5%

1 2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

PR251

330K_0402_5%

12

8

PU25B

5

P

+

7

O

6

-

G

LM393DG_SO8

4

PR206

1 2

0_0402_5%

CH751H-40PT_SOD323-2@

PWR_GD18,33,36,37,45

12

PC206
3900P_0402_50V7K

CHGLIM40

2

B

2005/03/102006/03/10

HOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

+3VS

12

PR377
10K_0402_5%

PD30

21

PR227

1 2

470K_0402_5%

ACN40

PR225
100K_0402_5%

@

1 2

C

PQ62

MMBT3904_SOT23

E

3 1

Compal Secret Data

Deciphered Date

PR218

2

12

PR390
47K_0402_5%

12

470K_0402_5%

PC207
1U_0603_10V6K

12

PR207
133K_0402_1%

12

G

PR355

80.6K_0402_1%

13

D

S

12

12

12

12

+5VS

3

+

2

-

12

PC117

0.027U_0603_16V7K

PR223

1 2

0_0402_5%

PQ61
RHU002N06_SOT323

12

+3VS

PR356

71.5K_0402_1%

PR357
21K_0402_1%

PR358

3.48K_0402_1%

2

PR208

1 2

100K_0402_5%

8

PU25A

P

1

O

G

LM393DG_SO8

4

1 2

PR217
604K_0603_1%

OCP#4,21

ACOCP_EN#35

PC202

0.1U_0805_50V7M

PD21

CH751H-40PT_SOD323-2

PQ108

DTA144EUA_SC70

13

47K

2
12

PR383

221K_0603_1%

150K_0402_5%

PD37
1N4148_SOD80

PD35

1 2

1 2

1N4148_SOD80

+5VS

PR360

8

3

P

+

2

-

G

1 2

1K_0402_5%

PR359

10K_0402_5%

1 2

+5VS

VIN

PR380

12

PR378
10K_0402_5%

47K

PR385

1M_0402_5%

1 2

4

+5VS

PR362

1M_0402_5%

1 2

PR361

21K_0402_1%

1 2

8

5

P

+

6

-

G

4

Title

SizeDocument NumberRev

Custom

Date:Sheet of

Compal Electronics, Inc.

LA-2821

1

CH751H-40PT_SOD323-2

21

12

PC115

12

12

PR221
10_0402_5%

ADP_SIGNAL

PU34A

1

O

LM393DG_SO8

PU34B

7

O

LM393DG_SO8

ADP_OCP

1

PD22

1U_0805_16V7K

+3VS

12

+3VS

12

1 3

21

PR387

LX_5V42

+3VS

ADP_PRES18,25,33,40,41,42

PR363
10K_0402_5%

ADP_PS033

PR364
10K_0402_5%

ADP_PS133

4752Friday, November 25, 2005

PQ105
NDS0610_SOT23

DS

G

2

12

12

220K_0402_5%

PD36

CH355PT_SOD323-2

1 2
13

D

2

G

S

+5VS

PR384

PQ107

220K_0402_5%

RHU002N06_SOT323

1

EAL80 from Pre DB-1 Step to DB-1 Step LA-2821 REV:0.0 -> 0.1 Modify <94.03.26.~94.04.08. >

1. Change +0.9V discharge circuit control signal from SLP_S3 to SLP_S5. <Page 36> 94.03.26.

-Change Q27.2(2N7002) connection from SLP_S3 to SLP_S5. (Modify CKT&Layout)

2. Just reserve a test pad for TPM_GPIO directly. <Page 32> 94.03.28.

-Del R1248 and connect TP62 to JP33.8 directly. (Modify CKT&Layout)

3. Change TPM1.2 +3VL Power Rail to +3VALW by Customer request. <Page 32> 94.03.28.

-Change +3VL that connects to R1242.1 to +3VALW. (Modify CKT&Layout)

11

4. Correct U25.39/38's net name from CLK_PCIE_NC/NC# to PCIE_NC/NC# . <Page 15> 94.03.28.

-Change U25.39/38 connection from CLK_PCIE_NC/CLK_PCIE_NC# to PCIE_NC/PCIE_NC#. (Modify CKT&Layout)

5. Change the RC parts for POK Time delay request. <Page 37> 94.03.29.

-Change R117 from 100K_0402_5% to 150K_0402_1%. (Modify CKT&BOM)

-Change C87 from 0.1U_0402 to 0.47U_0603_X7R. (Modify CKT,BOM&Layout)

6. Update the PCI7611MLS/PCI7612 related schematic by Vendor recommend. <Page 23,24> 94.03.29.

-Change R93,R97 from 7612@0_0402 to 0_0402; R103 from 7611@0_0402 to @0_0402. (Modify CKT&BOM)

-Add R1308(0_0402) between U42.K3 and U42.K5; change R106 from 0_0402 to @0_0402. (Modify CKT,BOM&Layout)

-Change R1299 from 43K_0402 to @43K_0402. (Modify CKT&BOM)

7. Reserve a 68UF Cap. by LAN Chip Vendor request. <Page 25> 94.03.29.

-Reserve C976(@68U_B2_4VM) close to U6.M14. (Modify CKT,BOM&Layout)

8. Reserve two resistors(@0_0402) to isolate VGATE and VGATE_INTEL. <Page 37> 94.03.29.

-Reserve R1306(@0_0402) between PU31.40 and U45.2. (Modify CKT,BOM&Layout)

-Reserve R1307(@0_0402) between U48.4 and PR326.2. (Modify CKT,BOM&Layout)

9. Change Calistoga LVDS function power source to GND for disabling by customer recommend. <Page 10> 94.03.29.

-Change U15.B30/C30/A30 connection from +2.5VS to GND. (Modify CKT&Layout)

22

-Change U15.A28/B28/C28 connection from +1.5VS to GND. (Modify CKT&Layout)

10. Remove DPRSLPVR Pull-down resistor by customer recommend. <Page 21> 94.03.29.

2

3

4

5

24. Remove the R1153 2.2Kohm pull-high resistor for leverage AF1.0 CFG9 setup. <Page 11> 94.04.01.

-Remove R1153(@2.2K_0402). (Modify CKT&BOM)

25. Add net name for USB signals layout rule create. <Page 30> 94.04.04.

-Add net names USB20_N1_R, USB20_P1_R, USB20_N4_R, USB20_P4_R, USB20_HUB_N1_R,
USB20_HUB_P1_R on JP16.6/7/2/3 JP22.4/3. (Modify CKT&Layout)

4th Netin

26. Remove the R555,R612 8.2Kohm pull-high resistors because the signals be double pulled up.
<Page 18> 94.04.04.

-Remove R555,R612(@8.2K_0402). (Modify CKT&BOM)

27. Reserve Audio mute control signals on KBC to leverage AF1.0 designing. <Page 33> 94.04.04.

-Reserve R140,R141(@0_0402) onU47.57/56 for EAPD/A_SD. (Modify CKT&Layout)

28. Correct net name for USB signals layout rule create. <Page 29,35> 94.04.04.

-Correct net names to USB20_N2_R, USB20_P2_R, USB20_N3_R, USB20_P3_R, USB20_N6_R,
USB20_P6_R, USB20_N7_R, USB20_P7_R, on JP27.1/2/4/5 JP30.2/4/6/8. (Modify CKT&Layout)

29. Add (NC@0_0402) to connect CP_USB# and NC_CPPE# for New Card function usage. <Page 24>

94.04.04.

-Add R1316(NC@0_0402) to connect CP_USB# and NC_CPPE#. (Modify CKT,BOM&Layout)

-Change R1272,R1273 from @10K_0402 to @100K_0402. (Modify CKT&BOM)
5th Netin

30. Del JP39.157's ADP_PRES connection to leverage AF1.0 and standard MXM pin definition. <Page 18>

94.04.04.

-Del JP39.157's ADP_PRES connection. (Modify CKT&Layout)

31. Reserve the circuit to control the mute to block the speaker pop on power up by customer recommend.
<Page 29> 94.04.04.

-Reserve D59(@RB751V), R613(@1M_0402), R431(@10K_0402), C93(@2.2U_0805), R439(@10K_0402),

R438(@10_0402) and the related circuit on U39.19. (Modify CKT,BOM&Layout)

-Change R1015 from 100K_0402_5% to @100K_0402_5%. (Modify CKT&BOM)

11. Stuff SPI related function Pull-High resistors by customer/Intel recommend. <Page 21,32> 94.03.29.

-Change R1284~R1286 from @10K_0402_5% to 10K_0402_5%. (Modify CKT&BOM)

12. Reserve 0 ohm resistor for PM_EXTTS#1 and DPRSLPVR connection by Customer/Intel recommend. <Page 7,21>

94.03.29.

-Reserve R1309(@0_0402_5%) between PM_EXTTS#1 and DPRSLPVR connection. (Modify CKT&Layout)

13. Add +1.8V discharge circuit. <Page 36> 94.03.30.

-Add R1310(470_0402_5%) and Q90(2N7002_SOT23) for +1.8V discharge schematic related. (Modify CKT,BOM&Layout)

14. Change ICH7 HD function power source to +3VS for wake on ring function from Azalia modem disabling by
customer recommend. <Page 22> 94.03.30.

-Change U26.R7 connection from +3VALW to +3VS. (Modify CKT&Layout)

15. Change TPM1.2 +3VL Power Rail to +3VALW by Customer request. <Page 32> 94.03.30.

-Change +3VL that connects to C193.1 to +3VALW. (Modify CKT&Layout)

16. Update ICH7M HD Audio, Codec Chip and MDC related Schematic. <Page 20,34,36> 94.03.30.

33

-Add R1313,R1314,R1315(33_0402) for ICH7/MDC/Codec related update. (Modify CKT,BOM&Layout)

-Create net name AC97_RST#_MDC, AC97_RST#_CODEC, AC97_SYNC_MDC, AC97_SYNC_CODEC,
AC97_SDOUT_MDC, AC97_SDOUT_CODEC, AC97_BITCLK_MDC, AC97_BITCLK_CODEC, AC97_SDIN0_CODEC,
AC97_SDIN1_MDC for ICH7/MDC/Codec related update. (Modify CKT&Layout)

17. Reserve 0ohm option resistors for +0.9V discharge circuit control signal SLP_S3 and SLP_S5 selecting . <Page 36>

94.03.30.

-Reserve R1311(@0_0402) to connect SLP_S5 to Q27.2. (Modify CKT&Layout)

Gerber Out 4/14

-Add R1312(0_0402) to connect SLP_S3 to Q27.2. (Modify CKT,BOM&Layout)

18. Populate the 68UF Cap. and reserve 10UF Cap. by LAN Chip Vendor/Customer request. <Page 25> 94.03.30.

-Change C976 from @68U_B2_4VM to 68U_B2_4VM, remove C243(@10U_1206_6.3V). (Modify CKT&BOM)

19. Swapping DDR2 SO-DIMM Data Group pin definition for Layout routing smoothly. <Page 13,14> 94.03.31.

-Swapping JP34 and JP10 Data Group pin definition. (Modify CKT&Layout)
3th Netin

20. Correct Calistoga chip power pin connection base on CRB Rev:1.301 recommend. <Page 11> 94.04.01.

-Disconnect U15.AV1 and U15.AJ1 to +1.8V and modify the related schematic. (Modify CKT&Layout)

-Change U15.AT41/AM41 net name from MCH_AT41/MCH_AM41 to VCCSM_LF4/VCCSM_LF5. (Modify CKT&Layout)

44

21. Change C899~C930 from 10U_1206_X5R to 10U_00805_X5R to meet Intel Napa ESL request. <Page 6> 94.04.01.

-Change C899~C930 from 10U_1206_X5R to 10U_00805_X5R. (Modify CKT,BOM&Layout)

22. Change C940~C945 from 0.1U_0402_Y5V to 0.1U_0402_X5R to meet Intel request, avoid thermal risk. <Page 6>

94.04.01.

-Change C940~C945 from 0.1U_0402_Y5V to 0.1U_0402_X5R. (Modify CKT&BOM)

23. Update ICS954306 PCB Footprint for Layout routing. <Page 15> 94.04.01.

-Change U25 PCB Footprint from ICS954306_TSSOP64 to ICS954306BGLFT_TSSOP64.

(Modify CKT,BOM&Layout)

1

2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/03/102006/03/10

Compal Secret Data

Deciphered Date

4

Title

SizeDocument NumberRev

Date:Sheet of

Compal Electronics, Inc.

H/W2 EE Dept. PIR SHEET(1)

LA-2821P

4852Friday, November 25, 2005

5

0.5

1 2 3 4

EAL80 from DB-1 Step to DB-2 Step LA-2821 REV:0.1 -> 0.2 Modify <94.05.10.~94.05.27. >

1. Change HDD I/F from PATA to SATA. <Page 20> 94.05.10.

-Change U26.AF18 from NC to IDE_LED#. (Modify CKT&Layout)

-Change U26.AF3 from GND to SATA_RXN0_C. (Modify CKT&Layout)

-Change U26.AE3 from GND to SATA_RXP0_C. (Modify CKT&Layout)

-Change U26.AG2 from NC to SATA_TXN0_C. (Modify CKT&Layout)

-Change U26.AH2 from NC to SATA_TXP0_C. (Modify CKT&Layout)

11

-Add R1256(24.9_0402_1%) between U26.AH10/AG10 and GND. (Modify CKT,BOM&Layout)

-Del R1326,R1327(NOSATA@0_0402). (Modify CKT,BOM&Layout)

-Add JP45, C955~C958(3900P_0402) and related schematic for SATA connector. (Modify CKT,BOM&Layout)

2. Remove R1294(1K_0402) Pull-High to +3VS to avoid double Pull-High risk. <Page 20> 94.05.10.

-Remove R1294(@1K_0402). (Modify CKT&BOM)

3. Add the accelerometer device LIS3LV02DQ and modify the related schematic . <Page 02,21,27,33> 94.05.11.

-Add U64(LIS3LV02DQ_QFN28),R1355(0_0805_5%),R1356(0_0603_5%),R1357~R1361(0_0402_5%),

R1362(10K_0402_5%),C994(0.01U_0402_16V7K),C995(0.1U_0402_16V4Z) and C996(4.7U_0805_10V4Z)
at the center of the system . (Modify CKT,BOM&Layout)

-Add R1364(0_0402_5%) between "ACCEL_INT#" and U26.E20(SB_GPIO9); Reserve R1363(@0_0402_5%) between

"ADP_PWRID" and U26.E20(SB_GPIO9) . (Modify CKT,BOM&Layout)

-Reserve R1354(@0_0402_5%) between "ACCEL_INT#" and U47.34(KBC_GPIO23) . (Modify CKT,BOM&Layout)

4. Change USB port assignments as customer request . <Page 02,21,24,30,32> 94.05.11.

-Change R1317(NC@0_0402_5%) connection Net from "USB20_P0_HUB" to "USB20_P1_HUB" and from "USB20_P0" to

"USB20_P1" . (Modify CKT&Layout)

-Change R1318(NC@0_0402_5%) connection Net from "USB20_N0_HUB" to "USB20_N1_HUB" and from "USB20_N0" to

22

"USB20_N1" . (Modify CKT&Layout)

-Change R562(0_0402_5%) connection Net from "USB20_HUB_P1_R" to "USB20_P0_R" and from "USB20_HUB_P1" to

"USB20_P0" . (Modify CKT&Layout)

-Change R586(0_0402_5%) connection Net from "USB20_HUB_N1_R" to "USB20_N0_R" and from "USB20_HUB_N1" to

"USB20_N0" . (Modify CKT&Layout)

-Change R983(NONC@0_0402_5%) connection Net from "USB20_P0" to "USB20_P1" . (Modify CKT&Layout)

-Change R982(NONC@0_0402_5%) connection Net from "USB20_N0" to "USB20_N1" . (Modify CKT&Layout)

-Change R1335(0_0402_5%) connection Net from "USB20_HUB_P2_R" to "USB20_HUB_P1_R" and from

"USB20_HUB_P2" to "USB20_HUB_P1" . (Modify CKT&Layout)

-Change R1334(0_0402_5%) connection Net from "USB20_HUB_N2_R" to "USB20_HUB_N1_R" and from

"USB20_HUB_N2" to "USB20_HUB_N1" . (Modify CKT&Layout)

-Change R1276(NC@0_0402_5%) connection Net from "USB20_P5_R" to "USB20_HUB_P2_R" and from

"USB20_P5" to "USB20_HUB_P2" . (Modify CKT&Layout)

-Change R1274(NC@0_0402_5%) connection Net from "USB20_N5_R" to "USB20_HUB_N2_R" and from

"USB20_N5" to "USB20_HUB_N2" . (Modify CKT&Layout)

-Change R607(0_0402_5%),D51.3 connection Net from "USB20_P1_R" to "USB20_P5_R" and from

33

"USB20_P1" to "USB20_P5" . (Modify CKT&Layout)

-Change R606(0_0402_5%),D51.2 connection Net from "USB20_N1_R" to "USB20_N5_R" and from

"USB20_N1" to "USB20_N5" . (Modify CKT&Layout)

-Change U53(NC@USB2502) pin15 connection from Net "USB_OC#0" to "USB_OC#1" . (Modify CKT&Layout)

-Change U41(TPS2041B) pin5 connection from Net "USB_OC#1" to "USB_OC#5" . (Modify CKT&Layout)

5. Change PCIE port assignments as customer request . <Page 02,21,24,25,27,35> 94.05.12.

-Change U26.K26/K25/J28/J27 to NC . (Modify CKT&Layout)

-Change C712 connection from PCIE_C_TXN3 to PCIE_C_TXN4 ; from PCIE_TXN3 to PCIE_TXN4 . (Modify CKT&Layout)

-Change C713 connection from PCIE_C_TXP3 to PCIE_C_TXP4 ; from PCIE_TXP3 to PCIE_TXP4 . (Modify CKT&Layout)

-Change C952 connection from PCIE_C_TXN4 to PCIE_C_TXN5 ; from PCIE_TXN4 to PCIE_TXN5 . (Modify CKT&Layout)

-Change C953 connection from PCIE_C_TXP4 to PCIE_C_TXP5 ; from PCIE_TXP4 to PCIE_TXP5 . (Modify CKT&Layout)

-Change C959 connection from PCIE_C_RXN3 to PCIE_C_RXN4 ; from PCIE_RXN3 to PCIE_RXN4 . (Modify CKT&Layout)

-Change C960 connection from PCIE_C_RXP3 to PCIE_C_RXP4 ; from PCIE_RXP3 to PCIE_RXP4 . (Modify CKT&Layout)

-Change JP9.A24 connection from PCIE_TXN3 to PCIE_TXN4 . (Modify CKT&Layout)

-Change JP9.A25 connection from PCIE_TXP3 to PCIE_TXP4 . (Modify CKT&Layout)

-Change R1347 connection from PCIE_C_RXN4 to PCIE_C_RXN5 ; from PCIE_RXN4 to PCIE_RXN5 . (Modify CKT&Layout)

44

-Change R1346 connection from PCIE_C_RXP4 to PCIE_C_RXP5 ; from PCIE_RXP4 to PCIE_RXP5 . (Modify CKT&Layout)

-Change JP30.151 connection from PCIE_TXN4 to PCIE_TXN5 . (Modify CKT&Layout)

6. Change SRC clock assignments as customer request . <Page 15> 94.05.13.

-Change U25.20 connection from "MCH_3GPLL" to "PCIE_LOM". (Modify CKT&Layout)

-Change U25.21 connection from "MCH_3GPLL#" to "PCIE_LOM#". (Modify CKT&Layout)

-Change U25.22 connection from "PCIE_LOM" to "PCIE_NC". (Modify CKT&Layout)

-Change U25.23 connection from "PCIE_LOM#" to "PCIE_NC#". (Modify CKT&Layout)

-Change U25.26 connection from "PCIE_MCARD" to "PCIE_DOCK". (Modify CKT&Layout)

-Change U25.27 connection from "PCIE_MCARD#" to "PCIE_DOCK#". (Modify CKT&Layout)

-Change U25.37 connection from "PCIE_DOCK" to "MCH_3GPLL". (Modify CKT&Layout)

-Change U25.36 connection from "PCIE_DOCK#" to "MCH_3GPLL#". (Modify CKT&Layout)

-Change U25.39 connection from "PCIE_NC" to "PCIE_MCARD". (Modify CKT&Layout)

-Change U25.38 connection from "PCIE_NC#" to "PCIE_MCARD#". (Modify CKT&Layout)

7. Change CLKREQ assignments as customer request . <Page 07,15,24,27> 94.05.13.

-Change R1344.2 connection from "CLKREQB#" to "CLKREQC#". (Modify CKT&Layout)

-Change R1279.1/R1280.1/C961.1 connection from "CLKREQD#" to "CLKREQA#". (Modify CKT&Layout)

-Change R1336 connection from "CLKREQB#" to "CLKREQD#"; from "CLKREQB#_MC" to "CLKREQD#_MC".
(Modify CKT&Layout)

-Add R1120(NOXDP@10K_0402) from net "CLKREQC#" to +3VS pull-high . (Modify CKT,BOM&Layout)

-Change R1142 from NOXDP@10K_0402 to NOXDP@0_0402 . (Modify CKT&BOM)

-Add R1147(NOXDP@10K_0402) from net "CLKREQD#" to +3VS pull-high . (Modify CKT,BOM&Layout)

-Change R1254 from NOXDP@10K_0402 to NOXDP@0_0402 . (Modify CKT&BOM)

-Change R1106(10K_0402) connection from +3VS pull-high to between CLKREQB# and CPPE# .
(Modify CKT&Layout)

8. Reserve test Mini-Card that supports USB interface as customer request . <Page 27,32> 94.05.13.

-Add R1365(@0_0402) between JP38.2 and JP44.36 . (Modify CKT&Layout)

-Add R1366(@0_0402) between JP38.3 andto JP44.38 . (Modify CKT&Layout)

9. Del R1344 & R1336 and short directly because of double reserved . <Page 07,27> 94.05.16.

-Del R1344(@0_0402_5%) and short directly . (Modify CKT&Layout)

-Del R1336(0_0402_5%) and short directly . (Modify CKT,BOM&Layout)

10. Update LAN Controller schematic related caused by chipset changed from BCM5751M to BCM5753M .
<Page 25,26> 94.05.16.

-Update the related schematic. (Modify CKT&Layout)

-Change R275,R289 from 47K_0402 to 1K_0402 . (Modify CKT,BOM&Layout)

-Change R276 from 4.7K_0402 to 1K_0402 . (Modify CKT,BOM&Layout)

-Add R1370,R1371(0_0402) and reserve R1372,R1373(@2.2K_0402),Q92,Q93(@2N7002) for SMBus
connection . (Modify CKT,BOM&Layout)

-Add R1367(1K_0402) from U6.H12 to +3VS . (Modify CKT,BOM&Layout)

11. Remove U37,D32,R504, and C577. Remove CLKREQA# connection from NIC to CK clock by customer
recommend . <Page 25> 94.05.16.

-Remove U37,D32,R504, and C577 . (Modify CKT,BOM&Layout)

12. Update Accelerometer related schematic by Vendor STMicro recommend . <Page 27> 94.05.16.

-Remove C994(@0.01U_0402), Change C996 from 4.7U_0805 to 10U_0805 . (Modify CKT,BOM&Layout)

13. Modify ICH7 Power_OK connection to be able to be enable same as NB . <Page 21> 94.05.16.

-Add R1368(0_0402) and reserve R1369(@0_0402) for U26.AD22 connection . (Modify CKT,BOM&Layout)

14. Swap RP11,RP13 pin connection for DDR2 shift trace routing issue improving . <Page 14> 94.05.16.

-Change RP11.2 connection from DDR_B_MA11 to DDR_CKE3_DIMMB . (Modify CKT&Layout)

-Change RP11.1 connection from DDR_CKE3_DIMMB to DDR_B_MA7 . (Modify CKT&Layout)

-Change RP13.2 connection from DDR_B_MA6 to DDR_B_MA11 . (Modify CKT&Layout)

-Change RP13.1 connection from DDR_B_MA7 to DDR_B_MA6 . (Modify CKT&Layout)

15. Update the SATA supported related . <Page 20> 94.05.17.

-Delete JP23,R458,R1324,R1325,R300 . (Modify CKT,BOM&Layout)

-Add C997(10U_0805),C998~C1000(0.1U_0402) close to JP45 +3VS pins . (Modify CKT,BOM&Layout)

16. Dual design SPI ROM for SOP8-150mil/200mil package . <Page 32> 94.05.17.

-Add U65(SPI@SST25LF080A-200mil) . (Modify CKT,BOM&Layout)

17. TPM1.2 on board designing reserve related . <Page 32> 94.05.17.

-Add U66(TPM1.2@SLB9635TT),C1001~C1004(0.1U_0402),C1005,C1006(18P_0402),Y8(32.768KHz),
R1375~R1381 and related schematic update . (Modify CKT,BOM&Layout)

-Change JP30.149 connection from PCIE_TXP4 to PCIE_TXP5 . (Modify CKT&Layout)

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2005/03/102006/03/10

Compal Secret Data

Deciphered Date

Title

SizeDocument NumberRev

4

Date:Sheet of

Compal Electronics, Inc.

H/W2 EE Dept. PIR SHEET(2)

LA-2821P

5

1st Netin

2nd Netin

5

4952Friday, November 25, 2005

0.5

1 2 3 4

EAL80 from DB-1 Step to DB-2 Step LA-2821 REV:0.1 -> 0.2 Modify <94.05.10.~94.05.27. >

18. Update TPM1.2 on board designing schematic. <Page 32,36> 94.05.18.

-Change pin5 (VSB) to +3VALW and move C1004 to connect to pin5 . (Modify CKT&Layout)

-Delete SMBus connection with R1380,R1381 on U66.2 & U66.6; Connect U66.6 to JP33.8, U66.2 to T87 .

(Modify CKT,BOM&Layout)

-Delete +3V power from JP33.4 . (Modify CKT&Layout)

-Delete +3V power reserved schematic and parts include Q91,C977,C978 . (Modify CKT,BOM&Layout)

11

19. Add DC/DC schematic about +2.5VALW to +2.5VS for power sequence fail issue fixed. <Page 36> 94.05.18.

-Add U67(SI4800DY_SO8),C1007,C1008,C1009 . (Modify CKT,BOM&Layout)

20. Delete MDC 1.0 Connector reserved related to save layout space . <Page 34> 94.05.18.

-Del JP25(MDC1.0 Conn),C13(0.1U_0402) . (Modify CKT,BOM&Layout)

21. Change the power source designing from +3VALW to +3VS for DB-2 LS-2712 issue fixed . <Page 34> 94.05.18.

-Change JP18.1 and JP18.3 connection from +3VALW to +3VS . (Modify CKT&Layout)

22. Change the ICH7 RTC Cap. Value for SVTP measure fail issue fixed . <Page 20> 94.05.19.

-Change C516,C528 from 18P_0402 to 10P_0402 . (Modify CKT&BOM)

23. Update LAN chip schematic related by customer recommend . <Page 25> 94.05.19.

-Change R275,R289 from 1K_0402 to @1K_0402 . (Modify CKT&BOM)

-Del D32,R504,C577,U37 . (Modify CKT,BOM&Layout)

-Add R1380(0_0402) and reserve R1381(@0_0402) . (Modify CKT,BOM&Layout)

-Del C40,C45,C53,C62,C64 for +3VS power rail cancel . (Modify CKT,BOM&Layout)

24. Update KBC related designing by customer recommend . <Page 33> 94.05.20.

-Add ADP_EN to S_CLK(GPIO22) by R1385(0_0402) . (Modify CKT,BOM&Layout)

22

-Add ADP_ID to EC_GPIO19 by R1382(0_0402) . (Modify CKT,BOM&Layout)

-Add ADP_PS1 to EC_GPIO12 by R1383(0_0402) . (Modify CKT,BOM&Layout)

-Add ADP_PS0 to EC_GPIO10 by R1384(0_0402) . (Modify CKT,BOM&Layout)

-Remove R87(@0_0402) . (Modify CKT&BOM)

25. Update ICH7 related designing by customer recommend . <Page 21,35> 94.05.20.

-Change R1363 from 0_0402 to ACCEL@0_0402 . (Modify CKT&BOM)

-Change R1363.2 connection from ADP_PWRID to ADP_ID . (Modify CKT&Layout)

-Reserve R1386(@0_0402) from PREP2# to U26.AD20(ICH7_GPIO38) . (Modify CKT&Layout)

-Reserve R1387(@10K_0402) from PREP2# to +3VS . (Modify CKT&Layout)

26. Update LAN chip schematic related by customer recommend . <Page 25> 94.05.20.

-Change R73.1 and R36.1 connection from +3VS to V_3P3_LAN . (Modify CKT&Layout)

27. Update CardReader chip schematic related by customer recommend . <Page 23> 94.05.20.

-Del U46 and related net . (Modify CKT,BOM&Layout)

-Del R591,R593 . (Modify CKT,BOM&Layout)

-Change R594 connection to between +VCC_SD and SDWP#_SMCE# . (Modify CKT&Layout)

-Change R602 connection to between +VCC_SD and SM_RB# . (Modify CKT&Layout)

33

-Change JP41.36 connection to MSBS_SDCMD_SMWE# . (Modify CKT&Layout)

-Change JP41.27 connection to SDCLK_SMRE# . (Modify CKT&Layout)

-Change JP41.28 connection to SDWP#_SMCE# . (Modify CKT&Layout)

-Change JP41.26 connection to SM_RB# . (Modify CKT&Layout)

-Add R1388(0_0402) between MC_PWRON# and MC_PWRON . (Modify CKT,BOM&Layout)

-Remove Q77,D45,D46,R595,D48 . (Modify CKT&BOM)

28. Update Clock Gen. schematic related by customer recommend . <Page 15> 94.05.20.

-Del R1328,R1329,R1330,R1331,R1332 and related net . (Modify CKT,BOM&Layout)

-Change U25.15 connection to FSB . (Modify CKT&Layout)

-Change U25.16,24,41 connection to +CK_VDD_DP . (Modify CKT&Layout)

-Change C734,C735,C736 connection to +CK_VDD_DP . (Modify CKT&Layout)

-Add R1389(NODP@0_0805),R1390(DP@0_0805),C1010(10U_0805) and related net . (Modify CKT,BOM&Layout)

-Change R1352,R1333 from @0_0402 to 0_0402 . (Modify CKT,BOM&Layout)

29. Update MXM schematic related by customer recommend . <Page 18> 94.05.23.

-Reserve R1391(@0_0402) from JP39.125 to CLKREQA# . (Modify CKT&Layout)

-Add R1392(0_0402) from JP39.157 to ADP_PRES . (Modify CKT,BOM&Layout)

44

30. Update LAN chip schematic related by customer recommend . <Page 25> 94.05.23.

3rd Netin

31. Update Clock Gen. schematic related by customer recommend . <Page 15> 94.05.23.

-Reserve R1393(@0_0402_5%) from U25.46(CLKIREF) to +CK_VDD_DP . (Modify CKT&Layout)

-Reserve C1011(@0.1U_0402) from U25.46(CLKIREF) to GND . (Modify CKT&Layout)

-Reserve R1394(@10K_0402) from U25.2(PCI_EC) to +3VS . (Modify CKT&Layout)

-Remove R1353,R1333(@0_0402_5%) . (Modify CKT&BOM)

32. Update AC97 Codec to keep AD1981HD only schematic related by customer recommend and DFx issue
improved . <Page 15,28> 94.05.23.

-Del C391,R403,R406,R388,R158,R159,C410,C408,C401,C398,R415,R364,C397,R1085(CLK_14M_CODEC)
,R418 and short U14.42 to GNDA . (Modify CKT,BOM&Layout)

-Add T88~T101 test point on the bottom side . (Modify CKT&Layout)

33. Update ICH7 SPI I/F related schematic by customer recommend . <Page 21> 94.05.24.

-Change R1284.1,R1285.1 and R1286.1 connection from +3VS to +3VALW . (Modify CKT&Layout)

34. Update TI PCI7611MLS/PCI7612 related schematic by customer recommend . <Page 23> 94.05.24.

-Change R594.2 and R602.2 connection from +VCC_SD to +VCC_SM_XD . (Modify CKT&Layout)

35. Update ICH7 SATA I/F related schematic by customer recommend . <Page 20> 94.05.24.

-Del JP45 pin8,9,10 +3VS connection . (Modify CKT&Layout)

-Del C997~C1000 . (Modify CKT,BOM&Layout)

36. Update ICH7 PATA I/F related schematic for SATA HDD support . <Page 20> 94.05.24.

-Add R556(100K_0402) . (Modify CKT&BOM)

37. Change some Capacitors for Lead Free designing . <Page 6,18,22,30> 94.05.25.

-Remove C939(@220U_C6_6.3V) and add C983(330U_D2E_2.5V) . (Modify CKT&BOM)

-Remove C633(@47U_25V_M) and add C1013~C1017(10U_1206_25V6M) . (Modify CKT,BOM&Layout)

-Remove C671(@100U_6.3V_M) and add C1012(150U_D_6.3VM) . (Modify CKT,BOM&Layout)

-Remove C670(@220U_C6_6.3V) and add C979(330U_DD2E_2.5V) . (Modify CKT&BOM)

-Remove C1,C527(@100U_6.3V) and add CC568,C567(150U_D_6.3V) . (Modify CKT&BOM)

38. Update the Accelerometer related and install the related BOM for Accelerometer enable . <Page 19,21,27,33>

-Change the net name from ACCEL_INT# to ACCEL_INT, ACCEL#_SB to ACCEL_SB, ACCEL_INT#_KBC
to ACCEL_INT_KBC . (Modify CKT&Layout)

-Note R94 must be removed when R1354 stuff and R87 remove . (Modify CKT&BOM)

-Reserve D61,C1018,R1395,Q95 between ACCEL_INT and Q78.1 . (Modify CKT&Layout)

-Remove R1358,R1360 . (Modify CKT&BOM)

39. Update Docking related schematic for Customer Smart Adaptor new function request . <Page 21,35>

-Change JP30.118 and R1387.1 net name to DOCK_ID . (Modify CKT&Layout)

-Add JP30.117(DOCK_ADP_SIGNAL) to ADP_SIGNAL by R1401(1K_0402_1%) . (Modify CKT,BOM&Layout)

40. Update AD1981HD related schematic for Vendor ADI review result . <Page 28>

-Change U18.2 connection from GND to AGND, move R258 between C551.1 and U18.2 . (Modify CKT&Layout)

-Change C409,C427,C431 from 0.1U_0402 to 0.1U_0805 . (Modify CKT,BOM&Layout)

-Add R1400(0_1206) between GND and AGND close to Codec area . (Modify CKT,BOM&Layout)

-Disconnect U14.14 and U14.15, disconnect U14.40 and U14.33 to AGND and add T102,T103,T104 on pin 14,40,33 .
(Modify CKT&Layout)

-Add R1399(0_0805) replace L36(CHB2012U121(0805)) . (Modify CKT&BOM)

-Add C1019(10P_0402) to GND . (Modify CKT,BOM&Layout)

41. Update Accelerometer related schematic for Customer review result . <Page 27>

-Remove R1355(@0_0805), add D62(ACCEL@CH751H) between U64.3/19 and +3VS . (Modify CKT,BOM&Layout)

-Del R1358 and R1360 pull-down resistors . (Modify CKT,BOM&Layout)

-Add R1398(0_0402) to GND, del U64.29 to GND connection . (Modify CKT,BOM&Layout)

42. Change the Audio Amp chip from TI TPA6017A2_TSSP20 to MAXIM MAX9710_QFN20 and update related
schematic for Customer Spec modified request . <Page 29>

-Change U39 from TPA6017A2_TSSOP20 to MAX9710ETP_QFN20 . (Modify CKT,BOM&Layout)

-Del D59,R613,R431,C93,R439,R438,C663,C664,R971~R974,C661 . (Modify CKT,BOM&Layout)

-Change C503,C502 from 0.047U to 0.1U . (Modify CKT,BOM&Layout)

-Add R1403(10K_0402) from U39.5 to C503.2, R1404(10K_0402) from U39.5 to U39.7 . (Modify CKT,BOM&Layout)

-Add R1405(10K_0402) from U39.1 to C502.2, R1406(10K_0402) from U39.1 to U39.19 . (Modify CKT,BOM&Layout)

-Add R1407(0ohm) from U39.4 to AGND;Add C1020(10U_1206) from +5VALW and GND . (Modify CKT,BOM&Layout)

-Add C1021(1U_0603) from U39.2 to AGND . (Modify CKT,BOM&Layout)

-Change C662 from @100U_6.3V to @150U_D_6.3V . (Modify CKT&Layout)

5

9rd Netin/BOM Transfer

-Reserve R284(@4.7K_0402_5%) from U6.L3 to V_3P3_LAN . (Modify CKT&Layout)

-Add T59 on U6.L3 . (Modify CKT&Layout)

-Add T60 on U6.M5 . (Modify CKT&Layout)

-Reserve Q94(@2N7002_SOT23) and change R1380 connection as update schematic . (Modify

CKT&Layout)

-Del R1381 and short Q29.3 to GND directly . (Modify CKT&Layout)

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2005/03/102006/03/10

Compal Secret Data

Deciphered Date

4

Title

SizeDocument NumberRev

Date:Sheet of

Compal Electronics, Inc.

H/W2 EE Dept. PIR SHEET(3)

LA-2821P

5052Friday, November 25, 2005

5

0.5

1 2 3 4

EAL80 from DB-1 Step to DB-2 Step LA-2821 REV:0.1 -> 0.2 Modify <94.05.10.~94.05.30. >

43. Reserve a 0ohm resistor for time delay pass through schematic by Customer request. <Page 37> 94.05.27.

-Reserve R1402(@0_0402) between PWR_GD and PGD_IN . (Modify CKT&Layout)

44. Change the resistor value to tune the delay schematic by Customer request. <Page 37> 94.05.27.

-Change R38 from 100K_0402 to 47K_0402 . (Modify CKT&BOM)

45. Change BOM option for Intel chipset ver:A1 by Customer recommend . <Page 7,21> 94.05.27.

-Change R1309 from @0_0402 to 0_0402, remove R1015(@100K_0402) . (Modify CKT&BOM)

11

46. Add a 0ohm resistor for debug by Customer recommend . <Page 4,20> 94.05.27.

-Add R1408(0_0402) between U26.H22 and H_STPCLK# . (Modify CKT,BOM&Layout)

47. Add a 0.1UF CAP to improve Cut Moat issue for RGB signals . <Page 36> 94.05.27.

-Add C1022(0.1U_0603) between +3VS and +VCCP . (Modify CKT,BOM&Layout)

48. Add 10Kohm pull-high to +VCC_SM_XD for TI FAE recommend . <Page 23> 94.05.27.

-Add R1396 and R1397(10K_0402) Pull-High to +VCC_SM_XD for MSBS_SDCMD_SMWE# and SDCLK_SMRE# .

(Modify CKT,BOM&Layout)

49. Update TPM related schematic for Vendor review result . <Page 32> 94.05.27.

-Add R1409(TPM1.2@0_0402) from U66.7 to GND, remove R1379(@4.7K_0402) . (Modify CKT,BOM&Layout)

-Change C193.1 connection from +3V to +3VALW for TPM1.2 . (Modify CKT&Layout)

EAL80 from SI-1 Step to SI-2 Step LA-2821 REV:0.3 -> 0.4 Modify <94.08.23.~94.09.21. >

1. Add discharge circuit for BT_LED and WL_LED to solve the LED always light on issue. <Page 32> 94.08.23.

-Add R1440 and R1441(100K_0402) for BT_LED and WL_LED discharge . (Modify CKT,BOM&Layout)

2. Remove DPRSLPVR NB side PullHigh resistor for Intel document update. <Page 7> 94.08.24.

-Remove R1209(@10K_0402) for DPRSLPVR . (Modify CKT&BOM)

22

3. Keep TPM1.2 on Board and Delete TPM1.1 Module Connector designing. <Page 32> 94.08.24.

-Del JP33,R1236,R1242,R1253,C191,C192,C193 and related schematic. (Modify CKT,BOM&Layout)

4. Update TPM1.2 chip PCB layout footprint. <Page 32> 94.08.24.

-Change U66 PCB Footprint from SLD9630TT_TSSOP28 to SLB-9635-TT-1P2_TSSOP28. (Modify CKT&Layout)

5. Correct ODD CSEL option setting. <Page 20> 94.08.24.

-Remove R460(@4.7K_0402) and add R557(470_0402). (Modify CKT&BOM)

6. Correct SPI I/F Power Source for Capell_Valley_CRB_Schematics_Rev1_502.pdf update . <Page 32> 94.08.26.

-Change U61.8, U65.8, R1287.1 and R1288.1 Power Rail from +3VS to +3VALW. (Modify CKT&Layout)

7. Modify Mini-Card debug interface design for customer update . <Page 27> 94.08.30.

-Move +3VALW from pin 39 to pin 45 and move CAPS_LED# from pin 41 to pin 51. (Modify CKT&Layout)

8. Update ADI1981HD CIS symbol and PCB Footprint . <Page 28> 94.08.30.

-Update U14 CIS symbol and change PCB Footprint from AD1981B_LQFP48 to AD1981HDJSTZ-REEL_LQFP48.

(Modify CKT&Layout)

9. Change PCI-E Ports for ICH7 modify . <Page 21,24,35> 94.08.31.

-Change ExpressCard (NC) connection to port 3, Change Docking connection to port 4. (Modify CKT&Layout)

10. Update Accelerometer related design for customer request . <Page 19,21,33,36> 94.09.02.

33

-Del D61, C1018, R1395 & Q95. (Modify CKT&Layout)

-Add Q75, R187; change D12 to Dual LED. (Modify CKT,BOM&Layout)

-Add net HDD_STP# from GPIO19 of ICH7 to Q75. (Modify CKT&Layout)

-Install R1374 and change R1060 to no-stuff. (Modify CKT&BOM)

-Del R1363 and R1364; Add SB GPIO test pad T80,T89,T99,T106. (Modify CKT,BOM&Layout)

11. Modify Mini-Card debug interface design for customer update . <Page 27> 94.09.02.

-Remove R1435 and R1436(@0_0402). (Modify CKT&BOM)

12. Modify TI PCI7612 designing for vendor request . <Page 23> 94.09.06.

-Change R573 from 10K_0402 to 0_0402. (Modify CKT&BOM)

-Change R594,R1396 and R1397 from 10K_0402 to 100K_0402. (Modify CKT&BOM)

-Change R602 from 10K_0402 to 22K_0402. (Modify CKT&BOM)

13. Update Accelerometer related design for customer request . <Page 19,21,33,36> 94.09.02.

-Add net HDD_STP from GPIO19 of ICH7 to Q84.2. (Modify CKT&Layout)

-Add Q84(2N7002) and R1442(100K_0402) for HDD_STP. (Modify CKT,BOM&Layout)

-Reserve R1443(@0_0402) for HDD_STP#. (Modify CKT&Layout)

14. Update ICH7 GPIO related design for customer request . <Page 21> 94.09.06.

44

-Del R1321 and R1323 related reserved schematic. (Modify CKT&Layout)

15. Modify LAN controller related for customer request . <Page 25> 94.09.07.

-Add and change R277 from @0_0402 to 10K_0402. (Modify CKT&BOM)

-Remove R1380(@0_0402) and add Q94(2N7002). (Modify CKT&BOM)

-Change R506 pull-up to +3VALW from V_3P3_LAN. (Modify CKT&Layout)

-Add Q100(SI2301BDS), reserve R83(@0_0402) and related schematic. (Modify CKT,BOM&Layout)

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

16. Modify PCMCIA Connector design for M/E team request . <Page 24> 94.09.08.

-Change JP9 PCBFootprint from SLINK_AFH-1000-17A0-3_104P to TYCO_C-PT05-023-D1_150P_LT.
(Modify CKT,BOM&Layout)

17. Delete New Card, USB HUB related design for customer Spec update . <Page 15,21,24,30,31> 94.09.08.

-Delete R1272,R1273,R1274,R1275,R1276,R1277,R1278,R1279,R1280,R1282,R1316,C959,C960,C961,C962,
C963,C964,C965,C966,C967,C968,C969,C970,C971,C972,C973,U60,R535,C541,L34,C521,C529,C535,C517,
C558,C540,C559,R981,U53,Y6,R984,C22,C27,L37,R1353,R537,R539,R523,R1317,R1318,R1099,R1102,
R1100,R1103,C712,C713; Add T107. (Modify CKT,BOM&Layout)

-Delete R982,R983 reserve. (Modify CKT&Layout)

18. Modify MiniCard related design for customer request. <Page 27> 94.09.08.

-Add Q101,Q102,R1445; Reserve R1444(@0_0805). (Modify CKT,BOM&Layout)

19. Delete FWH I/F BIOS related design for customer request. <Page 15,19,20,21,32> 94.09.08.

-Del &U21(SST49LF008A-33-4C-NH),U21,U20,R273,R278,RP42,R1125,C42,C333. (Modify CKT,BOM&Layout)

-Del R279,C43 reserve. (Modify CKT&Layout)

-Add T108,T109,T110. (Modify CKT&Layout)

-Delete BIOS_SEL1 and replace with short to GND directly. (Modify CKT&Layout)

20. Wire VGA Thermal inform signal with System side for function workable. <Page 21> 94.09.09.

-Add R252(0_0402). (Modify CKT&BOM)

21. Modify MiniCard related design for customer. <Page 27> 94.09.10.

-Add J44(JUMP_43X39) and reserve J45(@JUMP_43X39) for Power Source option. (Modify CKT&Layout)

-Change R1444.1 connection from +3VALW to +3VS. (Modify CKT&Layout)

-Remove Q101,Q102,R1445 and add R1444. (Modify CKT&BOM)

22. Modify TI PCI7612 designing for vendor request . <Page 23> 94.09.10.

-Change R573.1 power connection to +SC_PWR from +5VS. (Modify CKT&Layout)

-Change power rail to R615 & R616 to +3VS from +5VS and remove both R615 & R616. (Modify CKT,BOM&Layout)

23. Modify LAN Transformer designing for customer request . <Page 26> 94.09.10.

-Change R270,R271 connection by add C333 between ground and R270/R271 . (Modify CKT,BOM&Layout)

24. Create an option to use the 32KHz clock from KBC for TPM1.2 for customer request . <Page 32,33> 94.09.10.

-Reserve R1446(@0_0402) to connect U47.58 and U66.13. (Modify CKT&Layout)

25. Delete MiniPCI Debug I/F reserve for Layout space free . <Page 19,27,32> 94.09.12.

-Del R1117,R235,R441,R447,R451,R452 and JP20. (Modify CKT,BOM&Layout)

-Del R448,C537,R437 and Q49 reserve. (Modify CKT&Layout)

-Change R1420.1 connection from +3VALW to +3VL. (Modify CKT&Layout)

-Change C292,C538,C542 power source from +3VS to +3VS_MINI. (Modify CKT&Layout)

-Add H29,H30(H_C236D157)(MiniCard Stand Off). (Modify CKT,BOM&Layout)

26. Change Jopen PAD for CIC DFx request . <Page 15> 94.09.12.

-Change J29 PCBfootprint to JUMP_43X39. (Modify CKT&Layout)

27. Change LAN chip desgin to switch LAN power with LP_EN# for customer request . <Page 25> 94.09.13.

-Install R15(4.7K_0402_5%) and no-stuff U36(@SN74LVC1G17DBVR_SOT23-5). (Modify CKT&BOM)

28. Modify TPM1.2 related design about the ADP_EN for customer request . <Page 32,33> 94.09.13.

-Reserve R1447(@0_0402) close to Y8.1. (Modify CKT&Layout)

-Reserve R1448(@0_0402) for ADP_EN. (Modify CKT&Layout)

29. Modify BT related design for customer request . <Page 30> 94.09.14.

-Change R454 to 47K from 1K. (Modify CKT&BOM)

-Reserve a 0.1uF cap (no-stuff) from R454.2 to ground. (Modify CKT&Layout)

30. Modify LAN chip related design for customer request . <Page 25> 94.09.14.

-Add R458(0_0402) between Q100.2 and Q94.1. (Modify CKT,BOM&Layout)

31. Modify BITCLK related design for EMI request . <Page 20,28,34> 94.09.14.

-Reserve R1032,C722 close to U14.6. (Modify CKT&Layout)

-Move R1028, C721 close to JP32.12; R1314,R371 close to U26.U1. (Modify CKT&Layout)

32. Modify LID_SW# related design for M/E request . <Page 34> 94.09.14.

-Add R1449 close to JP18.16. (Modify CKT,BOM&Layout)

33. Modify Clock Gen. related design for Vendor request . <Page 15> 94.09.14.

-Change R1092 from 475_0402_1% to 4.7K_0402_1%. (Modify CKT&BOM)

34. Modify NB chip CFG11 related design for Intel CRB Rev1_502 update . <Page 11> 94.09.14.

-Remove R1154(@2.2K_0402_5%). (Modify CKT&BOM)

35. Modify Smart AC Adaptor related design for customer request . <Page 11> 94.09.14.

-Change R1237 from 10K_0402 to 100K_0402. (Modify CKT&BOM)

2005/03/102006/03/10

Compal Secret Data

Deciphered Date

4

Title

SizeDocument NumberRev

Date:Sheet of

Compal Electronics, Inc.

H/W2 EE Dept. PIR SHEET(4)

LA-2821P

5

5152Friday, November 25, 2005

5

0.5

1 2 3 4

5

EAL80 from SI-1 Step to SI-2 Step LA-2821 REV:0.3 -> 0.4 Modify <94.08.23.~94.09.21. >

36. Add DDR2 Module Thermal inform function to NB for customer request. <Page 7,13,14> 94.09.15.

-Add R1450(0_0402) between DDR_THERM# and PM_EXTTS#0 . (Modify CKT,BOM&Layout)

37. Reserve a cap at JP30.P2 pin for +5VS of Docking for customer request. <Page 35> 94.09.15.

-Reserve C1033(@22U_0805_6.3V4Z) close to JP30.P2. (Modify CKT&Layout)

38. Delete Bulk Cap. Daul Layout design reserve for DFx request. <Page 18> 94.09.15.

-Change C633 from @47U_25V(Non-LF) to 100U_25V(250',10sec,LF); Del C1013~C1017 . (Modify CKT,BOM&Layout)

11

-Del C823(100U 6.3V M B (6.3X6.0) CV-AX),C939,C830,C806(220U_C6_6.3V_M_R15) . (Modify CKT&Layout)

-Del C979(220U_D2_2VK_R9); Change C670 to SF22001M300. (Modify CKT,BOM&Layout)

-Del C1012(150U_D_6.3VM); Change C671 to SF22001M300. (Modify CKT,BOM&Layout)

-Del C567,C568(150U_D_6.3VM); Change C1,C527 to SF22001M300. (Modify CKT,BOM&Layout)

39. Remove all Clock Gen. pairs Pull-Down Resistors for LP design recommend. <Page 15> 94.09.15.

-Remove R1071,R1073,R1076,R1082,R1119,R1122,R1094,R1096,R1258,R1260,R1112,R1116,R1250,R1252,

R1124,R1127,R1134,R1137,R1238,R1239. (Modify CKT&BOM)

40. Modify XMIT_OFF related design for S/W request. <Page 27> 94.09.16.

-Add R1424(0_0402) between XMIT_OFF and XMIT_OFF#. (Modify CKT,BOM&Layout)

41. Modify TI PCMCIA Controller related design for Vendor request. <Page 23,24> 94.09.16.

-Add R591(0_0402) close to U42.E2. (Modify CKT,BOM&Layout)

-Add R617~R620,R623,R624(0_0402) close to JP41. (Modify CKT,BOM&Layout)

-Reserve C369,C372,C373,R593,R599,R613,R614 close to JP9. (Modify CKT&Layout)

-Remove R565. (Modify CKT&BOM)

42. Modify Audio Codec related design to avoid a small amount of noise on pin 2 could cause the codec to power
up in a test mode. <Page 28> 94.09.21.

22

-Change R422 from @0_0402 to 10K_0402. (Modify CKT&BOM)

43. Modify ICH7 related design for ICH7M & 3945abg Host Interface auto-detect sequence Issue (Sighting# 80332).
<Page 21> 94.09.21.

-Change decoupling caps (C710 & C711) from 0.1uF_0402 to 0.15uF_0603). (Modify CKT,BOM&Layout)

44. Modify Clock Gen. all series termination resistors for the differential signals related design for ICS recommend.
<Page 15> 94.09.21.

-Change R1070,R1072,R1075,R1081,R1118,R1121,R1257,R1259,R1093,R1095,R1144,R1145,R1123,R1126,R1111,

R1115,R1249,R1251 from 33_0402 to 24_0402. (Modify CKT&BOM)

33

44

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2005/03/102006/03/10

Compal Secret Data

Deciphered Date

Title

SizeDocument NumberRev

4

Date:Sheet of

Compal Electronics, Inc.

H/W2 EE Dept. PIR SHEET(5)

LA-2821P

5252Friday, November 25, 2005

5

0.5