Compal LA-2821 AngelFire 3.0, Compaq nw9440, Compaq nx9420 Schematic
A
1 1
2 2
B
C
D
E
Compal confidential
Schematics Document
Mobile Yonah uF CPGA with Intel
Calis toga_PM+ICH7-M core logic
3 3
4 4
A
B
2006-01-13
REV:1.0
Security Classification
Issued Date
THIS SHEET OF ENGINEERI NG DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATIO N. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUT HORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DIS CLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2005/03/10 2006/03/10
Compal Secret Data
Deciphered Date
Title
Size Document Number Rev
Custom
D
Date: Sheet of
Compal Electronics, Inc.
Cover Sheet
LA-2821P
1 52Saturday, January 14, 2006
E
1.0
A
Compal confidential
File Name : LA-2821P
B
C
D
E
Ang elFire 3.0
1 1
A ccelerometer
LIS3LV02DQ
page 27
Fan Control
page 4
Mobile Yonah
uFCPGA-478 CPU
Th ermal Sensor
A DM1032AR
page 4page 4,5,6
Clock Generator
I CS954306
page 15
A ccelerometer
LIS3LV02DQ
page 27
FSB
H_A#( 3..31)
MXM III connector
page 18
P CI-E x 16
Intel Calistoga MCH
CRT / TV-OUT
page 16
2 2
LCD CONN
page 17
P CI-E BUS
P CI BUS
10/100/1000 LAN
L ED
3 3
page 32
RTC CKT.
page 20
BCM5753M
page 25,26
RJ45/11 CONN
page 26
Min i-Card
page 27
1 394 port
CardBus Controller
TI PCI7612
Slo t 0/Smart Card
page 23
page 23,24
6 in1 Slot
page 24
Power OK CKT.
page 37
Power On/Off CKT.
page 34
4 4
DC/DC Interface CKT.
page 36
Security Module
Touch Pad CONN.
TrackPoint CONN.
SMSC KBC 1021
page 34
Power Circuit DC/DC
Page 38,39,40,41,42,43,44,45,46,47
A
B
533/667MHz
H_D#(0..63)
DDR2 -400/533/667
9 45PM
P CBGA 1466
page 7,8,9,10,11,12
Dual Channel
USB2.0
D MI
Intel ICH7-M
AC-LINK/Azalia
mBGA-652
page 19,20,21,22
page 23
SPI
SPI ROM
SST25LF080A
page 23
SATA Master
PATA Slave
LPC BUS
SMSC Super I/O
page 33
LPC47N217
I nt.KBD
page 34page 34
Security Classification
Issued Date
THIS SHEET OF ENGINEERI NG DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATIO N. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUT HORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DIS CLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
COM1 L PT
( Docking ) ( Docking )
page 35 page 35
2005/03/10 2006/03/10
Compal Secret Data
page 31page 32
Deciphered Date
DDR2-SO-DIMM X2
BANK 0, 1, 2, 3
page 13,14
U SB conn x2
( Docking)
USB2.0 HUB /
F P Conn
U SB conn x2
BT Conn
USB conn x2
(Sub Board)
Audio CKT A MP & Audio Jack
AD1981HD
page 35
FingerPrinter AES2501
page 30
page 30
page 30
page 29
page 28 page 29
U SBx1
New Card USBx1
MDC1.5
page 34
MAX9710ETP
page 30
page 24
SATA HDD Connector
page 20
PATA ODD Connector
page 20
F lash ROM
SST49LF008A
D
page 32
Title
Size Document Number Rev
Date: Sheet of
Docking CONN.
*RJ-45(LED*2)
*RJ-11(Pass Through)
*CRT
*COMPOSITE Video Out
*TVOUT
*DVI
*LINE IN
*LINE OUT
*PCI-E x2
*Serial Port
*Parallel Port
*PS/2 x2
*USB x2
*DC JACK
Compal Electronics, Inc.
Block Diagram
LA-2821P
E
page 34
1.0
2 52Saturday, January 14, 2006
5
4
3
2
1
Voltage Rails
Power Plane
VIN
D D
C C
B+
+CPU_CORE
+ VCCP
+0.9VS
+1.5VS
+ 1.8V
+2.5VS
+3VALW
+5VALW
+ 5VS
+RT C_VCC
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.
Description
Adapter power supply (18.5V)
AC or battery power rail for power circuit
Core voltage for CPU
1.05V power rail for Processor I/O and MCH/ICH core power
0.9V switched power rail for DDRII Vtt
1.5V switched power rail for PCI-E interface
1.8V power rail for DDRII
3.3V al ways on power rail+2. 5VALW ON ON O N*
3.3V al ways on power rail
3.3V sw itched power rail+ 3VS
5V always on power rail
5V switched power rail
RT C power ONON
S3
S0-S1
N/A
N/A
N/A
ON OFF
ON
OFF
ON
OFF
ON
OFF
ON
ON
ON+1.8VS OFF OFF1.8V sw itched power rail
ON OFF
ON
ON
ON OFF OFF
ON
ON
ON
OFF
ON
S5
N/A
N/AN/A
OFF
OFF
OFF
OFF
OFF
OFF2.5V switched power rail for MCH video PLL
O N*
O N*
OFF
Inte rnal PCI Devices
DEVI CE
L AN
A zalia D27
USB1.1/2.0
PCI to PCI (DMI to PCI)
AC97 MODEM
AC97 Audio
PATA/SATA
LPC I/F
S MBUS
CPU I/F
B B
PCI Device ID
Bus
1
0
0
0
0
0
0
0
0
0
0
0
0
D8
D28PCI-E
D29
D30
D30
D30
D31
D31
D31
D31 AD15D MA
D31 AD15P MU
I DSEL #
AD24
AD11
AD12
AD13
AD14
AD14
AD14
AD15
AD15
AD15
AD15D31
External PCI Devices
DEVI CE
Mini-PCI
CARD BUS
PCI Device ID
D4
D6
I DSEL #
AD20
AD22
REQ/GNT #
0
2
PI RQ
F
C D E G
Symbol Note :
: means Digital Ground
: means Analog Ground
Note: Layout Related Memo
L
: Layout Note related Area Mark.
: Question Area Mark.(Wait check)
: Modified Area Mark.
12/12
: C-BOM impact
: Modified Area Mark(Compare with EAL60).
@ : means just reserve , no build
SPI@ : means just build when SPI I/F BIOS function reserve.
*
FWH@ : means just build when FWH I/F BIOS function reserve.
*
NOXDP@ : means just build when XDP function disable.
*
XDP@ : means just build when XDP function enable. When this time, docking PCI express will not work.
TPM1.2@ : means just build when TPM1.2 function enable.
*
TPM@ : means just build when TPM function enable.
*
SC@ : means just build when SmartCard function enable.
*
SATA@ : means just build when SATA I/F HDD enable.
*
NOSATA@ : means just build when SATA I/F HDD disable.
NC@ : means just build when New Card function enable.
*
NONC@ : means just build when New Card function disable.
MDC1.5@ : means just build when MDC1.5 function enable.
*
7612@ : means just build when TI PCI7612 chip selected.
*
7611@ : means just build when TI PCI7611MLS chip selected.
250@ : means just build when SMsC LPC47N250 chip selected.
1021@ : means just build when SMsC KBC1021 chip selected.
*
1981HD@ : means just build when AD1981HD chip selected.
*
45@ : means need be mounted when 45 level assy or rework stage.
ACCEL@ : means just build when Accelerometer chip LIS3LV02DQ selected.
*
NODP@ : means just build when No DP design Clock Gen. selected.
*
DP@ : means just build when DP design Clock Gen. selected.
LPNO@ : means just build when No LP design ICS Clock Gen. selected.
LP@ : means just build when LP design ICS Clock Gen. selected.
*
DB@ : means just build when Mini-PCI E Debug Card function enable.
*
* : means define for SMT build when this stage
I2C / SMBUS ADDRESSING
DEVI CE
A A
DDR SO-DIMM 0
DDR SO-DIMM 1
CLOCK GENERATOR (EXT.)
US B HUB 5C 0 1 0 1 1 1 0 0
5
HEX
A0
A4
D2
ADDRESS
1 0 1 0 0 0 0 0
1 0 1 0 0 1 0 0
1 1 0 1 0 0 1 0
Security Classification
Issued Date
THIS SHEET OF ENGINEERI NG DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATIO N. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUT HORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
4
MAY BE USED BY OR DIS CLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2005/03/10 2006/03/10
Compal Secret Data
Deciphered Date
Title
Size Document Number Rev
2
Date: Sheet of
Compal Electronics, Inc.
Notes List
LA-2821P
3 52Saturday, January 14, 2006
1
1.0
5
H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
D D
H_REQ#[0..4]7
H_ADSTB#07
C C
R448
56_0402_5%
+VCCP
B B
H_PROCHOT#45
+VCCP
56_0402_5%
H_THERMDA, H_THERMDC routing together.
Trace width / Spacing = 10 / 10 mil
A A
H_ADSTB#17
CLK_CPU_BCLK15
CLK_CPU_BCLK#15
H_ADS#7
H_BNR#7
H_BPRI#7
H_BR0#7
H_DEFER#7
H_DRDY#7
H_HIT#7
H_HITM#7
H_LOCK#7
H_RESET#7
H_RS#[0..2]7
H_TRDY#7
XDP_DBRESET#21
H_DBSY#7
H_DPSLP#20
H_DPRSTP#20,45
H_DPWR#7
R447
H_PWRGOOD20
H_CPUSLP#7
R27 1K_0402_5%@
R28 51_0402_5%
H_THERMTRIP#7,20
+VCCP
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
H_ADSTB#0
H_ADSTB#1
CLK_CPU_BCLK
CLK_CPU_BCLK#
H_ADS#
H_BNR#
H_BPRI#
H_BR0#
H_DEFER#
H_DRDY#
H_HIT#
H_HITM#
H_IERR#
H_LOCK#
H_RESET#
H_RS#0
H_RS#1
H_RS#2
H_TRDY#
XDP_BPM#0
XDP_BPM#1
XDP_BPM#2
XDP_BPM#3
XDP_DBRESET#
H_DBSY#
H_DPSLP#
H_DPRSTP#
H_DPWR#
XDP_BPM#4
XDP_BPM#5
H_PROCHOT#
H_PWRGOOD
H_CPUSLP#
XDP_TCK
XDP_TDI
XDP_TDO
TEST1
TEST2
XDP_TMS
XDP_TRST#
H_THERMDA
H_THERMDC
H_THERMTRIP#
JP8A
ADDR GROUP
HOST CLK
CONTROL
FOX_PZ47903-2741-42_YONAH
YONAH
MISC
THERMAL
DIODE
4
DATA GROUP
LEGACY CPU
H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
H_DINV#0
H_DINV#1
H_DINV#2
H_DINV#3
H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3
H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3
H_A20M#
H_FERR#
H_IGNNE#
H_INIT#
H_INTR
H_NMI
H_STPCLK#
H_SMI#
H_D#[0..63] 7H_A#[3..31]7
H_DINV#0 7
H_DINV#1 7
H_DINV#2 7
H_DINV#3 7
H_DSTBN#[0..3] 7
H_DSTBP#[0..3] 7
H_A20M# 20
H_FERR# 20
H_IGNNE# 20
H_INIT# 20
H_INTR 20
H_NMI 20
H_STPCLK# 20
H_SMI# 20
3
2
ITP-XDP Connector
XDP_BPM#5
XDP_BPM#4
XDP_BPM#3
XDP_BPM#2
XDP_BPM#1
XDP_BPM#0
R442
H_PWRGOOD_RH_PWRGOOD CLK_CPU_XDP
1K_0402_5%
+VCCP +VCCP
C539 0.1U_0402_16V4Z
ICH_SMBDATA
ICH_SMBCLK
XDP_TCK
JP31
SAMTE_BSH-030-01-L-D-A
Thermal Sensor ADM1032AR-2
+3VS
C69
0.1U_0402_16V4Z
H_THERMDA
C68
H_THERMDC
2200P_0402_50V7K
+3VS
THERM#
R25
10K_0402_5%
PWM Fan Control circuit
D1
CH751H-40_SC76
+3VS
FAN_PWM33
THERM#
U31
TC7SH00FUF_SSOP5
G
CLK_CPU_XDP#
XDP_TDO
XDP_TRST#
XDP_TDI
XDP_TMS
XDP_PRE
U5
ADM1032AR-2_MSOP8
Address:1001_101
ICH_SMBCLK13,14,15,18,21,25,27
ICH_SMBDATA13,14,15,18,21,25,27
+5VS
D
Q69
AO6402_TSOP6
S
XDP_DBRESET#_R
This shall place nea r CPU
XDP_TDI
XDP_TMS
XDP_TDO
XDP_BPM#5
XDP_TRST#
XDP_TCK
1K_0402_1%
R441
R444
200_0402_1%
R191 0_0402_5%
ICH_SMBCLK
ICH_SMBDATA
THERM_SCI#
ICH_SMBCLK
ICH_SMBDATA
C65
4.7U_0805_10V4Z
FAN
1
5/10
R443
1K_0402_5%@
+VCCP
R524 56_0402_5%
R523 56_0402_1%
R525 56_0402_5%
R526 56_0402_5%
R521 56_0402_5%
R522 56_0402_5%
CLK_CPU_XDP 15
H_RESET#H_RESET#_R
XDP_DBRESET#XDP_DBRESET#_R
C63
0.1U_0402_16V4Z
@
RLZ5.1B_LL34
CLK_CPU_XDP# 15
R24
10K_0402_5%
THERM_SCI# 21
ACES_85205-0200
ZD1
+3VS
JP6
R30
56_0402_5%@
B
E
H_PROCHOT# OCP#
C
Q6
MMBT3904_SOT23@
5
OCP# 21,47
H_DPSLP#
H_DPRSTP#
R439
56_0402_5%@
R440
56_0402_5%@
4
Security Classification
Issued Date
THIS SHEET OF ENGINEERI NG DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATIO N. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUT HORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DIS CLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2005/03/10 2006/03/10
Compal Secret Data
Deciphered Date
2
Title
Size Document Number Rev
Date: Sheet of
Compal Electronics, Inc.
Yonah CPU in mFCPGA479
LA-2821P
4 52Saturday, January 14, 2006
1
1.0
5
4
3
2
1
V_CPU_GTLREF
+VCCP
R37
1K_0402_1%
R39
2K_0402_1%
+VCC_CORE
R42
100_0402_1%
VCCSENSE
R41
100_0402_1%
VSSSENSE
Close to CPU pin
within 500mils.
CPU_BSEL CPU_BSEL2 CPU_BSEL1
133
166
R35
27.4_0402_1%
0 0
0
R36
54.9_0402_1%
D D
Close to CPU pin AD26
within 500mils.
C C
B B
Length match within 25 mils
The trace width 18 mils space
7 mils
+1.5VS
C70
0.01U_0402_16V7K
CPU_BSEL0
1
1
Resistor placed within
0.5" of CPU pin.Trace
should be at least 25
mils away from any
other toggling signal.
R470
27.4_0402_1%
1
R473
54.9_0402_1%
C72
10U_0805_10V4Z
CPU_VID045
CPU_VID145
CPU_VID245
CPU_VID345
CPU_VID445
CPU_VID545
CPU_VID645
V_CPU_GTLREF
CPU_BSEL015
CPU_BSEL115
CPU_BSEL215
VCCSENSE45
VSSSENSE45
H_PSI#45
+VCCP
+VCC_CORE
VCCSENSE
VSSSENSE
H_PSI#
CPU_VID0
CPU_VID1
CPU_VID2
CPU_VID3
CPU_VID4
CPU_VID5
CPU_VID6
CPU_BSEL0
CPU_BSEL1
CPU_BSEL2
COMP0
COMP1
COMP2
COMP3
JP8B
YONAH
POWER, GROUNG, RESERVED SIGNALS AND NC
+VCC_CORE
JP8C
YONAH
POWER, GROUND
FOX_PZ47903-2741-42_YONAH
A A
Security Classification
Issued Date
THIS SHEET OF ENGINEERI NG DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATIO N. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUT HORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DIS CLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2005/03/10 2006/03/10
Compal Secret Data
Deciphered Date
2
FOX_PZ47903-2741-42_YONAH
Title
Size Document Number Rev
Date: Sheet of
Compal Electronics, Inc.
Yonah CPU in mFCPGA479
LA-2821P
5 52Saturday, January 14, 2006
1
1.0
5
4
3
2
1
D D
Place these capacitors on L8
(North side,Secondary Layer)
Place these capacitors on L8
(North side,Secondary Layer)
Place these capacitors on L8
(Sorth side,Secondary Layer)
C C
Place these capacitors on L8
(Sorth side,Secondary Layer)
+VCC_CORE
C412
10U_0805_6.3V6M
+VCC_CORE
C411
10U_0805_6.3V6M
+VCC_CORE
C441
10U_0805_6.3V6M
+VCC_CORE
C442
10U_0805_6.3V6M
C413
10U_0805_6.3V6M
C481
10U_0805_6.3V6M
C423
10U_0805_6.3V6M
C435
10U_0805_6.3V6M
C414
10U_0805_6.3V6M
C480
10U_0805_6.3V6M
C432
10U_0805_6.3V6M
C436
10U_0805_6.3V6M
C415
10U_0805_6.3V6M
C486
10U_0805_6.3V6M
C422
10U_0805_6.3V6M
C443
10U_0805_6.3V6M
C416
10U_0805_6.3V6M
C418
10U_0805_6.3V6M
C446
10U_0805_6.3V6M
C444
10U_0805_6.3V6M
C417
10U_0805_6.3V6M
C482
10U_0805_6.3V6M
C424
10U_0805_6.3V6M
C427
10U_0805_6.3V6M
C425
10U_0805_6.3V6M
C483
10U_0805_6.3V6M
C445
10U_0805_6.3V6M
C426
10U_0805_6.3V6M
C479
10U_0805_6.3V6M
C484
10U_0805_6.3V6M
C485
10U_0805_6.3V6M
C431
10U_0805_6.3V6M
Mid Frequence Decoupling
+VCC_CORE
South Side Secondary
+
C408
B B
330U_D2E_2.5VM_R9@
C409
330U_D2E_2.5VM_R9@
330U_D2E_2.5VM_R7
+
C67
+
C66
330U_D2E_2.5VM_R7
330U_D2E_2.5VM_R7
+
C117
+
820U_E9_2_5V_M_R7@
+
C119
C125
330U_D2E_2.5VM_R7
+
North Side Secondary
+
C120
820U_E9_2_5V_M_R7@
ESR <= 1.5m ohm
Capacitor > 1980uF
+VCCP
+
C434
220U_D2_2VK_R9
A A
5
C437
0.1U_0402_10V6K
C429
0.1U_0402_10V6K
C421
0.1U_0402_10V6K
4
C438
0.1U_0402_10V6K
C428
0.1U_0402_10V6K
Security Classification
Issued Date
THIS SHEET OF ENGINEERI NG DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATIO N. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUT HORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DIS CLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C433
0.1U_0402_10V6K
3
Place these in side
socket cavity o n L8
(North side
Secondary)
2005/03/10 2006/03/10
Compal Secret Data
Deciphered Date
2
Title
Size Document Number Rev
Date: Sheet of
Compal Electronics, Inc.
CPU Bypass capacitors
LA-2821P
6 52Saturday, January 14, 2006
1
1.0
5
4
3
2
1
H_D#[0..63]4
D D
C C
+VCCP
R350
R381
54.9_0402_1%
54.9_0402_1%
H_XSCOMP/H_YSCOMP trace
L
width and spacing is 5/20.
B B
R339
24.9_0402_1%
+VCCP
A A
R360
R348
H_VREF
H_XRCOMP
H_XSCOMP
H_YRCOMP
H_YSCOMP
H_SWNG0
H_SWNG1
R395
24.9_0402_1%
Layout Note:
H_XRCOMP / H_YRCOMP / H_VREF / H_SWNG0 /
H_SWNG1 trace width and spacing is 18/20.
100_0402_1%
H_VREF
C330
200_0402_1%
0.1U_0402_16V4Z
5
H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
U4A
HOST
CALISTOGA_A2_FCBGA1466
R351
R344
221_0603_1%
H_SWNG0
100_0402_1%
4
H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
H_ADSTB#0
H_ADSTB#1
CLK_MCH_BCLK#
CLK_MCH_BCLK
H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3
H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3
H_DINV#0
H_DINV#1
H_DINV#2
H_DINV#3
H_RESET#
H_ADS#
H_TRDY#
H_DPWR#
H_DRDY#
H_DEFER#
H_HITM#
H_HIT#
H_LOCK#
H_BR0#
H_BNR#
H_BPRI#
H_DBSY#
H_CPUSLP#
H_RS#0
H_RS#1
H_RS#2
C328
0.1U_0402_16V4Z
+VCCP+VCCP
R17
R18
H_A#[3..31] 4
H_REQ#[0..4] 4
H_ADSTB#0 4
H_ADSTB#1 4
CLK_MCH_BCLK# 15
CLK_MCH_BCLK 15
H_DSTBN#[0..3] 4
H_DSTBP#[0..3] 4
H_DINV#0 4
H_DINV#1 4
H_DINV#2 4
H_DINV#3 4
H_RESET# 4
H_ADS# 4
H_TRDY# 4
H_DPWR# 4
H_DRDY# 4
H_DEFER# 4
H_HITM# 4
H_HIT# 4
H_LOCK# 4
H_BR0# 4
H_BNR# 4
H_BPRI# 4
H_DBSY# 4
H_CPUSLP# 4
H_RS#[0..2] 4
221_0603_1%
H_SWNG1
C359
100_0402_1%
0.1U_0402_16V4Z
U4B
CALISTOGA_A2_FCBGA1466
Layout Note:
Route as short
as possible
R412
40.2_0402_1%
+1.8V
DMI_TXN0
DMI_TXN1
DMI_TXN2
DMI_TXN3
DMI_TXP0
DMI_TXP1
DMI_TXP2
DMI_TXP3
DMI_RXN0
DMI_RXN1
DMI_RXN2
DMI_RXN3
DMI_RXP0
DMI_RXP1
DMI_RXP2
DMI_RXP3
M_CLK_DDR0
M_CLK_DDR1
M_CLK_DDR2
M_CLK_DDR3
M_CLK_DDR#0
M_CLK_DDR#1
M_CLK_DDR#2
M_CLK_DDR#3
DDR_CKE0_DIMMA
DDR_CKE1_DIMMA
DDR_CKE2_DIMMB
DDR_CKE3_DIMMB
DDR_CS0_DIMMA#
DDR_CS1_DIMMA#
DDR_CS2_DIMMB#
DDR_CS3_DIMMB#
M_OCDOCMP0
M_OCDOCMP1
M_ODT0
M_ODT1
M_ODT2
M_ODT3
SMRCOMPN
SMRCOMPP
PM_BMBUSY#
PM_EXTTS#0
PM_EXTTS#1
H_THERMTRIP#
PWROK
PLTRST_R#
PWROK
R409
100_0402_1%@
R411
100_0402_1%@
DMI_TXN021
DMI_TXN121
DMI_TXN221
DMI_TXN321
DMI_TXP021
DMI_TXP121
DMI_TXP221
DMI_TXP321
DMI_RXN021
DMI_RXN121
DMI_RXN221
DMI_RXN321
DMI_RXP021
DMI_RXP121
DMI_RXP221
DMI_RXP321
M_CLK_DDR013
M_CLK_DDR113
M_CLK_DDR214
M_CLK_DDR314
M_CLK_DDR#013
M_CLK_DDR#113
M_CLK_DDR#214
M_CLK_DDR#314
DDR_CKE0_DIMMA13
DDR_CKE1_DIMMA13
DDR_CKE2_DIMMB14
DDR_CKE3_DIMMB14
DDR_CS0_DIMMA#13
DDR_CS1_DIMMA#13
DDR_CS2_DIMMB#14
DDR_CS3_DIMMB#14
+1.8V
R419 80.6_0402_1%
R413 80.6_0402_1%
DPRSLPVR21,45
VGATE_INTEL21,45
V_DDR_MCH_REF13,14,44
R65 0_0402_5%
PLT_RST#19,20,21,23,25,27,32,33
R597 0_0402_5%@
PM_POK21,33
R590 0_0402_5%
M_ODT013
M_ODT113
M_ODT214
M_ODT314
V_DDR_MCH_REF
PM_BMBUSY#21
H_THERMTRIP#4,20
R408 100_0402_1%
MCH_ICH_SYNC#19
Layout Note:
V_DDR_MCH_REF
trace width and
spacing is 20/20.
V_DDR_MCH_REF
C385
0.1U_0402_16V4Z
Stuff R1202 & R1203 for A1 Calistoga
Security Classification
Issued Date
THIS SHEET OF ENGINEERI NG DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATIO N. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUT HORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DIS CLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2005/03/10 2006/03/10
Compal Secret Data
Deciphered Date
2
DMI
DDR MUXING
PM
M_OCDOCMP0
M_OCDOCMP1
R400
40.2_0402_1%
CFG
CLKNC
RESERVED
PM_EXTTS#0
PM_EXTTS#1
GMCH_A27
GMCH_A26
GMCH_C40
GMCH_D41
DDR_THERM#13,14
Title
Size Document Number Rev
Date: Sheet of
Description at page11.
MCH_CLKSEL0
MCH_CLKSEL1
MCH_CLKSEL2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG16
CFG17
CFG18
CFG19
CFG20
CLK_MCH_3GPLL
CLK_MCH_3GPLL#
GMCH_A27
GMCH_A26
GMCH_C40
GMCH_D41
CLKREQC#
R353
10K_0402_5%
R362
10K_0402_5%@
R15
10K_0402_5%
R14
10K_0402_5%
R338
10K_0402_5%
R342
10K_0402_5%
R343
0_0402_5%
5/16
PAD
PAD
PAD
PAD
PAD
8/24
PM_EXTTS#0DDR_THERM#
MCH_CLKSEL0 15
MCH_CLKSEL1 15
MCH_CLKSEL2 15
T1
T2PAD
CFG5 11
T4PAD
CFG7 11
T3
CFG9 11
T7
CFG11 11
CFG12 11
CFG13 11
T6PAD
T5
CFG16 11
T8
CFG18 11
CFG19 11
CFG20 11
CLK_MCH_3GPLL 15
CLK_MCH_3GPLL# 15
CLKREQC# 15
+3VS
Compal Electronics, Inc.
Calistoga (1/6)
LA-2821P
7 52Saturday, January 14, 2006
1
1.0
5
D D
4
3
2
1
DDR_A_BS#013
DDR_A_BS#113
DDR_A_BS#213
DDR_A_DM[0..7]13
DDR_A_DQS[0..7]13
C C
DDR_A_DQS#[0..7]13
DDR_A_MA[0..13]13
B B
DDR_A_CAS#13
DDR_A_RAS#13
DDR_A_WE#13
T11 PAD
T12 PAD T10 PAD
DDR_A_BS#0
DDR_A_BS#1
DDR_A_BS#2
DDR_A_DM0
DDR_A_DM1
DDR_A_DM2
DDR_A_DM3
DDR_A_DM4
DDR_A_DM5
DDR_A_DM6
DDR_A_DM7
DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7
DDR_A_DQS#0
DDR_A_DQS#1
DDR_A_DQS#2
DDR_A_DQS#3
DDR_A_DQS#4
DDR_A_DQS#5
DDR_A_DQS#6
DDR_A_DQS#7
DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11 DDR_B_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_CAS#
DDR_A_RAS#
DDR_A_WE#
SA_RCVENIN#
SA_RCVENOUT#
U4D
DDR SYS MEMORY A
CALISTOGA_A2_FCBGA1466
DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63
DDR_A_D[0..63] 13 DDR_B_D[0..63] 14
DDR_B_BS#014
DDR_B_BS#114
DDR_B_BS#214
DDR_B_DM[0..7]14
DDR_B_DQS[0..7]14
DDR_B_DQS#[0..7]14
DDR_B_MA[0..13]14
DDR_B_CAS#14
DDR_B_RAS#14
DDR_B_WE#14
T9 PAD
DDR_B_BS#0
DDR_B_BS#1
DDR_B_BS#2
DDR_B_DM0
DDR_B_DM1
DDR_B_DM2
DDR_B_DM3
DDR_B_DM4
DDR_B_DM5
DDR_B_DM6
DDR_B_DM7
DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4
DDR_B_DQS5
DDR_B_DQS6
DDR_B_DQS7
DDR_B_DQS#0
DDR_B_DQS#1
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS#4
DDR_B_DQS#5
DDR_B_DQS#6
DDR_B_DQS#7
DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6DDR_A_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA12
DDR_B_MA13
DDR_B_CAS#
DDR_B_RAS#
DDR_B_WE#
SB_RCVENIN#
SB_RCVENOUT#
U4E
DDR SYS MEMORY B
CALISTOGA_A2_FCBGA1466
DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63
A A
Security Classification
Issued Date
THIS SHEET OF ENGINEERI NG DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATIO N. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUT HORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DIS CLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2005/03/10 2006/03/10
Compal Secret Data
Deciphered Date
Title
Size Document Number Rev
2
Date: Sheet of
Compal Electronics, Inc.
Calistoga (2/6)
LA-2821P
8 52Saturday, January 14, 2006
1
1.0
5
D D
C C
R363 10K_0402_5%
B B
R355 10K_0402_5%
+VCCP
4
U4C
LVDS
+1.5VS
TV CRT
PCI-EXPRESS GRAPHICS
CALISTOGA_A2_FCBGA1466
3
PEGCOMP trace width
L
and spacing is 18/25 mils.
PEGCOMP
PEG_RXP15
PEG_RXP14
PEG_RXP13
PEG_RXP12
PEG_RXP11
PEG_RXP10
PEG_RXP9
PEG_RXP8
PEG_RXP7
PEG_RXP6
PEG_RXP5
PEG_RXP4
PEG_RXP3
PEG_RXP2
PEG_RXP1
PEG_RXP0
PEG_RXN15
PEG_RXN14
PEG_RXN13
PEG_RXN12
PEG_RXN11
PEG_RXN10
PEG_RXN9
PEG_RXN8
PEG_RXN7
PEG_RXN6
PEG_RXN5
PEG_RXN4
PEG_RXN3
PEG_RXN2
PEG_RXN1
PEG_RXN0
PEG_TXP15
PEG_TXP14
PEG_TXP13
PEG_TXP12
PEG_TXP11
PEG_TXP10
PEG_TXP9
PEG_TXP8
PEG_TXP7
PEG_TXP6
PEG_TXP5
PEG_TXP4
PEG_TXP3
PEG_TXP2
PEG_TXP1
PEG_TXP0
PEG_TXN15
PEG_TXN14
PEG_TXN13
PEG_TXN12
PEG_TXN11
PEG_TXN10
PEG_TXN9
PEG_TXN8
PEG_TXN7
PEG_TXN6
PEG_TXN5
PEG_TXN4
PEG_TXN3
PEG_TXN2
PEG_TXN1
PEG_TXN0
+1.5VS_PCIE
R331
24.9_0402_1%
PEG_RXP[0..15] 18
PEG_RXN[0..15] 18
C22 0.1U_0402_16V4Z
C24 0.1U_0402_16V4Z
C26 0.1U_0402_16V4Z
C30 0.1U_0402_16V4Z
C32 0.1U_0402_16V4Z
C34 0.1U_0402_16V4Z
C37 0.1U_0402_16V4Z
C41 0.1U_0402_16V4Z
C45 0.1U_0402_16V4Z
C47 0.1U_0402_16V4Z
C49 0.1U_0402_16V4Z
C51 0.1U_0402_16V4Z
C53 0.1U_0402_16V4Z
C56 0.1U_0402_16V4Z
C58 0.1U_0402_16V4Z
C61 0.1U_0402_16V4Z
C20 0.1U_0402_16V4Z
C23 0.1U_0402_16V4Z
C25 0.1U_0402_16V4Z
C28 0.1U_0402_16V4Z
C31 0.1U_0402_16V4Z
C33 0.1U_0402_16V4Z
C35 0.1U_0402_16V4Z
C38 0.1U_0402_16V4Z
C43 0.1U_0402_16V4Z
C46 0.1U_0402_16V4Z
C48 0.1U_0402_16V4Z
C50 0.1U_0402_16V4Z
C52 0.1U_0402_16V4Z
C54 0.1U_0402_16V4Z
C57 0.1U_0402_16V4Z
C60 0.1U_0402_16V4Z
2
PEG_M_TXP15
PEG_M_TXP14
PEG_M_TXP13
PEG_M_TXP12
PEG_M_TXP11
PEG_M_TXP10
PEG_M_TXP9
PEG_M_TXP8
PEG_M_TXP7
PEG_M_TXP6
PEG_M_TXP5
PEG_M_TXP4
PEG_M_TXP3
PEG_M_TXP2
PEG_M_TXP1
PEG_M_TXP0
PEG_M_TXN15
PEG_M_TXN14
PEG_M_TXN13
PEG_M_TXN12
PEG_M_TXN11
PEG_M_TXN10
PEG_M_TXN9
PEG_M_TXN8
PEG_M_TXN7
PEG_M_TXN6
PEG_M_TXN5
PEG_M_TXN4
PEG_M_TXN3
PEG_M_TXN2
PEG_M_TXN1
PEG_M_TXN0
1
PEG_M_TXP[0..15] 18
PEG_M_TXN[0..15] 18
A A
Security Classification
Issued Date
THIS SHEET OF ENGINEERI NG DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATIO N. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUT HORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DIS CLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2005/03/10 2006/03/10
Compal Secret Data
Deciphered Date
Title
Size Document Number Rev
2
Date: Sheet of
Compal Electronics, Inc.
Calistoga (3/6)
LA-2821P
9 52Saturday, January 14, 2006
1
1.0
5
4
3
2
1
D D
+
C42
220U_D2_2VK_R9
C C
C339
C368
4.7U_0805_10V4Z
2.2U_0805_16V4Z
MCH_A6
C317
B B
C336
0.22U_0603_10V7K
0.47U_0603_10V7K
MCH_D2
C318
MCH_AB1
C55
0.22U_0603_10V7K
0.47U_0603_10V7K
+VCCP
U4H
P O W E R
W=40 mils
220U_D2_4VM_R25
+1.5VS_3GPLL
+2.5VS
MCH_CRTDAC
PAD-No SHORT 2x2m
R333
0_0805_5%@
+1.5VS_HPLL
R356
0_0805_5%
+1.5VS_MPLL
+1.5VS
+1.5VS
+1.5VS
+1.5VS_TVDAC
+1.5VS
C377
C297
9/ 15
J5
PAD-SHORT 2x2m
J4
C322
0.1U_0402_16V4Z
0.1U_0402_16V4Z
+1.5VS_PCIE
10U_0805_6.3V6M
C315
+
+VCCP
+2.5VS
+3VS
C320
10U_0805_6.3V6M
R410
0_0805_5%
C380
10U_0805_6.3V6M
+1.5VS
+2.5VS
C329
0.1U_0402_16V4Z
close pin G41
PCI-E/MEM/PSB PLL decoupling
R398
0.5_0805_1%
C371
0.1U_0402_16V4Z
45mA Max. 45mA Max.
0.1U_0402_16V4Z
C378
10U_0805_6.3V6M
+1.5VS_MPLL +1.5VS_HPLL
C373
R23
0_0805_5%
C62
10U_0805_6.3V6M
R396
0_0805_5%
0.1U_0402_16V4Z@
+1.5VS+1.5VS_3GPLL
C387
0.1U_0402_16V4Z
+1.5VS_TVDAC +1.5VS
0.022U_0402_16V7K@
C374
C324
10U_0805_6.3V6M@
R332
0_0805_5%
C316
R22
0_0805_5%
C59
10U_0805_6.3V6M
C319
0.022U_0402_16V7K@
+1.5VS+1.5VS
+1.5VS
CALISTOGA_A2_FCBGA1466
A A
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MA Y BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2005/03/10 2006/03/10
3
Compal Secret Data
D eciphered Date
Compal Electronics, Inc.
Calistoga (4/6)
2
Date: Sheet of
LA-2821P
10 52Saturday, January 14, 2006
1
1.0
5
+VCCP
D D
C333
C367
C337
10U_0805_6.3V6M
C C
B B
C375
0.22U_0603_10V7K
0.22U_0603_10V7K
10U_0805_6.3V6M
C338
C343
C64
220U_D2_2VK_R9
C386
+
330U_D2E_2.5VM_R9@
0.22U_0603_10V7K
1U_0603_10V4Z
+
+VCCP
U4F
P O W E R
CALISTOGA_A2_FCBGA1466
4
+1.5VS
VCCSM_LF2
VCCSM_LF1
+1.8V
C398
C390
0.47U_0603_10V7K
0.47U_0603_10V7K
+VCCP
U4G
P O W E R
3
+1.8V
VCCSM_LF4
VCCSM_LF5
C389
C395
0.47U_0603_10V7K
0.47U_0603_10V7K
Place near pin AT41 & AM41
C381
C382
0.1U_0402_16V4Z
C406
0.47U_0603_10V7K
Place near pin BA23
C405
C407
10U_0805_6.3V6M
10U_0805_6.3V6M
C404
0.47U_0603_10V7K
2
C384
0.1U_0402_16V4Z
0.1U_0402_16V4Z
+
C402
220U_D2_4VM@
L
CFG[2:0]
CFG5
CFG7
CFG9
CFG11
CFG[13:12]
+1.8V
CFG16
CFG18
C388
0.1U_0402_16V4Z
CFG19
SDVO_CTRLDATA
CFG20
(PCIE/SDVO select)
@wait DB-1 test verify
1
Strap Pin Table
CFG[3:17] have internal pull up
CFG[19:18] have internal pull down
011 = 667MT/s FSB
001 = 533MT/s FSB
0 = DMI x 2
1 = DMI x 4
0 = Reserved
1 = Mobile Yonah CPU
0 = Lane Reversal Enable
1 = Normal Operation
1 = Calistoga
(Accor ding to Intel Napa Schematic Checklist & CRB
Rev1.502 document 2.2Kohm pull-down resistor no request)
0 = Reserved
00 = Reserved
01 = XOR Mode Enabled
10 = All Z Mode Enabled
11 = Normal Operation
0 = Dynamic ODT Disabled
1 = Dynamic ODT Enabled (Default)
0 = 1.05V
1 = 1.5V
0 = Normal Operation
1 = DMI Lane Reversal Enable
0 = No SDVO Device Present
*
(Default)
(Default)
*
*
(Default)
(Default)
*
(Default)
(Default)
*
*
(Default)
*
1 = SDVO Device Present
0 = Only PCIE or SDVO is
operational.
1 = PCIE/SDVO are operating
simu.
R349 2.2K_0402_5%@
CFG57
R340 2.2K_0402_5%@
CFG77
R354 2.2K_0402_5%@
CFG97
R341 2.2K_0402_5%@
CFG117
R365 2.2K_0402_5%@
CFG127
R371 2.2K_0402_5%@
CFG137
R359 2.2K_0402_5%@
CFG167
R370 1K_0402_5%@
CFG187
R368 1K_0402_5%@
CFG197
R369 1K_0402_5%@
CFG207
(Default)
*
*
*
+3VS
Place near pin BA15
Place near pin AV1 & AJ1
A A
5
4
CALISTOGA_A2_FCBGA1466
Security Classification
Issued Date
THIS SHEET OF ENGINEERI NG DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATIO N. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUT HORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DIS CLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2005/03/10 2006/03/10
Compal Secret Data
Deciphered Date
Title
Size Document Number Rev
2
Date: Sheet of
Compal Electronics, Inc.
Calistoga (5/6)
LA-2821P
11 52Saturday, January 14, 2006
1
1.0
5
4
3
2
1
U4I
D D
U4J
P O W E R
P O W E R
C C
B B
CALISTOGA_A2_FCBGA1466
A A
5
CALISTOGA_A2_FCBGA1466
4
Security Classification
Issued Date
THIS SHEET OF ENGINEERI NG DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATIO N. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUT HORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DIS CLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2005/03/10 2006/03/10
Compal Secret Data
Deciphered Date
2
Title
Size Document Number Rev
Date: Sheet of
Compal Electronics, Inc.
Calistoga (6/6)
LA-2821P
12 52Saturday, January 14, 2006
1
1.0
5
DDR_A_DQS#[0..7]8
DDR_A_D[0..63]8
DDR_A_DM[0..7]8
DDR_A_DQS[0..7]8
DDR_A_MA[0..13]8
D D
Layout Note:
Place near JP34
+1.8V
2.2U_0805_16V4Z
2.2U_0805_16V4Z
C467
C461
0.1U_0402_16V4Z
0.1U_0402_16V4Z
C79
RP11
RP7
RP15
RP10
RP9
RP8
5
2.2U_0805_16V4Z
C463
0.1U_0402_16V4Z
C78
C80
+0.9V
56_0404_4P2R_5%
56_0404_4P2R_5%
56_0404_4P2R_5%
56_0404_4P2R_5%
56_0404_4P2R_5%
56_0404_4P2R_5%
2.2U_0805_16V4Z
C462
C464
0.1U_0402_16V4Z
0.1U_0402_16V4Z
C82
C81
RP13 56_0404_4P2R_5%
RP18 56_0404_4P2R_5%
RP12 56_0404_4P2R_5%
RP17 56_0404_4P2R_5%
RP16 56_0404_4P2R_5%
RP14 56_0404_4P2R_5%
RP19 56_0404_4P2R_5%
0.1U_0402_16V4Z
0.1U_0402_16V4Z
C105
0.1U_0402_16V4Z
0.1U_0402_16V4Z
C84
C115
DDR_A_BS#2
DDR_CKE0_DIMMA
DDR_A_MA7
DDR_A_MA6
DDR_A_MA9
DDR_A_MA12
DDR_A_MA4
DDR_A_MA2
DDR_A_MA0
DDR_A_BS#1
M_ODT0
DDR_A_MA13
DDR_CKE1_DIMMA
DDR_A_MA11
0.1U_0402_16V4Z
2.2U_0805_16V4Z
C C
B B
A A
Layout Note:
Place one cap close to every 2 pullup
resistors terminated to +0.9V
+0.9V
0.1U_0402_16V4Z
C83
DDR_A_MA5
DDR_A_MA8
DDR_A_MA1
DDR_A_MA3
DDR_A_RAS#
DDR_CS0_DIMMA#
DDR_A_BS#0
DDR_A_MA10
DDR_A_CAS#
DDR_A_WE#
DDR_CS1_DIMMA#
M_ODT1
0.1U_0402_16V4Z
C93
0.1U_0402_16V4Z
C111
4
0.1U_0402_16V4Z
C91
C95
0.1U_0402_16V4Z
C112
C113
0.1U_0402_16V4Z
0.1U_0402_16V4Z
C110
Layout Note:
Place these resistor
closely JP34,all
trace length Max=1.5"
4
C114
3
+1.8V
JP9
DDR_A_D0
DDR_A_D4
DDR_A_DQS#0
DDR_A_DQS0
DDR_A_D2
DDR_A_D3
DDR_A_D8
DDR_A_D14
DDR_A_DQS#1
DDR_A_DQS1
DDR_A_D10
DDR_A_D11
DDR_A_D21
DDR_A_D17
DDR_A_DQS#2
DDR_A_DQS2
DDR_A_D22
DDR_A_D19 DDR_A_D23
DDR_A_D25
DDR_A_D24
DDR_A_DM3
DDR_A_D27
DDR_A_D30
DDR_CKE0_DIMMA7
DDR_A_BS#28
DDR_A_BS#08
DDR_A_WE#8
DDR_A_CAS#8
DDR_CS1_DIMMA#7
M_ODT17
ICH_SMBDATA4,14,15,18,21,25,27
ICH_SMBCLK4,14,15,18,21,25,27
DDR_CKE0_DIMMA
DDR_A_BS#2
DDR_A_MA12
DDR_A_MA9 DDR_A_MA7
DDR_A_MA8
DDR_A_MA5
DDR_A_MA3
DDR_A_MA1
DDR_A_MA10
DDR_A_BS#0
DDR_A_WE#
DDR_A_CAS#
DDR_CS1_DIMMA#
M_ODT1
DDR_A_D34
DDR_A_D38
DDR_A_DQS#4
DDR_A_DQS4
DDR_A_D39
DDR_A_D35
DDR_A_D45
DDR_A_D41
DDR_A_DM5
DDR_A_D42
DDR_A_D43
DDR_A_D52
DDR_A_D53
DDR_A_DQS#6
DDR_A_DQS6
DDR_A_D55
DDR_A_D56
DDR_A_D61
DDR_A_DM7
DDR_A_D58
DDR_A_D59
ICH_SMBDATA
ICH_SMBCLK
+3VS
C96
0.1U_0402_16V4Z
FOX_ASOA426-M4R-TR
SO-DIMM A
2
REVERSE
Security Classification
Issued Date
THIS SHEET OF ENGINEERI NG DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATIO N. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUT HORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DIS CLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2005/03/10 2006/03/10
Compal Secret Data
Top side
Deciphered Date
2
+1.8V
V_DDR_MCH_REF
DDR_A_D7
DDR_A_D1
DDR_A_DM0
DDR_A_D5
DDR_A_D6
DDR_A_D12
DDR_A_D13
DDR_A_DM1
M_CLK_DDR0
M_CLK_DDR#0
DDR_A_D9
DDR_A_D15
DDR_A_D20
DDR_A_D16
DDR_THERM#
DDR_A_DM2
DDR_A_D18
DDR_A_D29
DDR_A_D28
DDR_A_DQS#3
DDR_A_DQS3
DDR_A_D26
DDR_A_D31
DDR_CKE1_DIMMA
DDR_A_MA11
DDR_A_MA6
DDR_A_MA4
DDR_A_MA2
DDR_A_MA0
DDR_A_BS#1
DDR_A_RAS#
DDR_CS0_DIMMA#
M_ODT0
DDR_A_MA13
DDR_A_D36
DDR_A_D33
DDR_A_DM4
DDR_A_D37
DDR_A_D32
DDR_A_D40
DDR_A_D44
DDR_A_DQS#5
DDR_A_DQS5
DDR_A_D47
DDR_A_D46
DDR_A_D48
DDR_A_D49
M_CLK_DDR1
M_CLK_DDR#1
DDR_A_DM6
DDR_A_D50DDR_A_D51
DDR_A_D54
DDR_A_D60
DDR_A_D57
DDR_A_DQS#7
DDR_A_DQS7
DDR_A_D62
DDR_A_D63
R40
R38
10K_0402_5%
1
2.2U_0805_16V4Z
0.1U_0402_16V4Z
C97
M_CLK_DDR0 7
M_CLK_DDR#0 7
DDR_THERM# 7,14
DDR_CKE1_DIMMA 7
DDR_A_BS#1 8
DDR_A_RAS# 8
DDR_CS0_DIMMA# 7
M_ODT0 7
M_CLK_DDR1 7
M_CLK_DDR#1 7
10K_0402_5%
Title
Size Document Number Rev
Date: Sheet of
Compal Electronics, Inc.
DDRII-SODIMM SLOT1
LA-2821P
V_DDR_MCH_REF 7,14,44
C92
1
13 52Saturday, January 14, 2006
1.0
5
DDR_B_DQS#[0..7]8
DDR_B_D[0..63]8
DDR_B_DM[0..7]8
DDR_B_DQS[0..7]8
DDR_B_MA[0..13]8
D D
C C
B B
A A
Layout Note:
Place near JP34
+1.8V
2.2U_0805_16V4Z
Layout Note:
Place one cap close to every 2 pullup
resistors terminated to +0.9V
+0.9V
0.1U_0402_16V4Z
C85
DDR_B_MA1
DDR_B_MA3
DDR_B_BS#0
DDR_B_MA10
DDR_B_MA0
DDR_B_BS#1
DDR_B_RAS#
DDR_CS2_DIMMB#
DDR_B_CAS#
DDR_B_WE#
DDR_CS3_DIMMB# M_ODT2
M_ODT3
2.2U_0805_16V4Z
C109
C108
0.1U_0402_16V4Z
0.1U_0402_16V4Z
C86
RP34
RP35
RP3
RP2
RP36
RP37
5
2.2U_0805_16V4Z
2.2U_0805_16V4Z
C460
0.1U_0402_16V4Z
C87
C88
+0.9V
56_0404_4P2R_5%
56_0404_4P2R_5%
56_0404_4P2R_5%
56_0404_4P2R_5%
56_0404_4P2R_5%
56_0404_4P2R_5%
2.2U_0805_16V4Z
C466
C107
0.1U_0402_16V4Z
0.1U_0402_16V4Z
C89
C90
RP32 56_0404_4P2R_5%
RP6 56_0404_4P2R_5%
RP33 56_0404_4P2R_5%
RP5 56_0404_4P2R_5%
RP4 56_0404_4P2R_5%
RP1 56_0404_4P2R_5%
RP31
56_0404_4P2R_5%
0.1U_0402_16V4Z
DDR_B_MA9
DDR_B_MA12
DDR_B_MA7
DDR_CKE3_DIMMB
DDR_B_MA5
DDR_B_MA8
DDR_B_MA6
DDR_B_MA11
DDR_B_MA4
DDR_B_MA2
DDR_B_MA13
DDR_B_BS#2
DDR_CKE2_DIMMB
0.1U_0402_16V4Z
0.1U_0402_16V4Z
C94
0.1U_0402_16V4Z
C476
C477
5/16
5/16
0.1U_0402_16V4Z
C455
0.1U_0402_16V4Z
C475
4
0.1U_0402_16V4Z
C106
C454
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
C473
C474
Layout Note:
Place these resistor
closely JP10,all
trace length Max=1.5"
4
0.1U_0402_16V4Z
C471
C472
3
+1.8V
JP29
DDR_B_D0
DDR_B_D5
DDR_B_DQS#0
DDR_B_DQS0
DDR_B_D7
DDR_B_D3
DDR_B_D8
DDR_B_D9
DDR_B_DQS#1
DDR_B_DQS1
DDR_B_D10
DDR_B_D11
DDR_B_D20
DDR_B_DQS#2
DDR_B_DQS2
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_DM3
DDR_B_D30
DDR_B_D31
DDR_CKE2_DIMMB7
DDR_B_BS#28
DDR_B_BS#08
DDR_B_WE#8
DDR_B_CAS#8
DDR_CS3_DIMMB#7
M_ODT37
ICH_SMBDATA4,13,15,18,21,25,27
ICH_SMBCLK4,13,15,18,21,25,27
Security Classification
Issued Date
THIS SHEET OF ENGINEERI NG DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATIO N. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUT HORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DIS CLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
DDR_CKE2_DIMMB
DDR_B_BS#2
DDR_B_MA12
DDR_B_MA9
DDR_B_MA8
DDR_B_MA5
DDR_B_MA3
DDR_B_MA1
DDR_B_MA10
DDR_B_BS#0
DDR_B_WE#
DDR_B_CAS#
DDR_CS3_DIMMB#
M_ODT3
DDR_B_D37
DDR_B_D36
DDR_B_DQS#4
DDR_B_DQS4
DDR_B_D35
DDR_B_D34
DDR_B_D40
DDR_B_D41
DDR_B_DM5
DDR_B_D42
DDR_B_D47
DDR_B_D48
DDR_B_D53
DDR_B_DQS#6
DDR_B_DQS6
DDR_B_D51
DDR_B_D50
DDR_B_D60
DDR_B_D61
DDR_B_DM7
DDR_B_D58
DDR_B_D59
ICH_SMBDATA
ICH_SMBCLK
+3VS
C453
0.1U_0402_16V4Z
2005/03/10 2006/03/10
FOX_ASOA426-M2RN-7F
SO- DIMM B
STANDA RD
Compal Secret Data
Bottom side
Deciphered Date
2
2
+1.8V
V_DDR_MCH_REF
DDR_B_D4
DDR_B_D1
DDR_B_DM0
DDR_B_D6
DDR_B_D2
DDR_B_D12
DDR_B_D13
DDR_B_DM1
M_CLK_DDR3
M_CLK_DDR#3
DDR_B_D14
DDR_B_D15
DDR_B_D16DDR_B_D21
DDR_B_D18
DDR_THERM#
DDR_B_DM2
DDR_B_D17
DDR_B_D19
DDR_B_D26
DDR_B_D28
DDR_B_DQS#3
DDR_B_DQS3
DDR_B_D29
DDR_B_D27
DDR_CKE3_DIMMB
DDR_B_MA11
DDR_B_MA7
DDR_B_MA6
DDR_B_MA4
DDR_B_MA2
DDR_B_MA0
DDR_B_BS#1
DDR_B_RAS#
DDR_CS2_DIMMB#
M_ODT2
DDR_B_MA13
DDR_B_D33
DDR_B_D32
DDR_B_DM4
DDR_B_D38
DDR_B_D39
DDR_B_D44
DDR_B_D45
DDR_B_DQS#5
DDR_B_DQS5
DDR_B_D43
DDR_B_D46
DDR_B_D49
DDR_B_D52
M_CLK_DDR2
M_CLK_DDR#2
DDR_B_DM6
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_DQS#7
DDR_B_DQS7
DDR_B_D62
DDR_B_D63
1
V_DDR_MCH_REF 7,13,44
0.1U_0402_16V4Z
2.2U_0805_16V4Z
C103
C99
M_CLK_DDR3 7
M_CLK_DDR#3 7
DDR_THERM# 7,13
DDR_CKE3_DIMMB 7
DDR_B_BS#1 8
DDR_B_RAS# 8
DDR_CS2_DIMMB# 7
M_ODT2 7
M_CLK_DDR2 7
M_CLK_DDR#2 7
R33
10K_0402_5%
10K_0402_5%
R34
Title
Size Document Number Rev
Date: Sheet of
+3VS
Compal Electronics, Inc.
DDRII-SODIMM SLOT2
LA-2821P
1
14 52Saturday, January 14, 2006
1.0
5
PCI
SRC
CPU
CLKSEL1
0
1
FSLA
CLKSEL0
MHz
133
166
MHz
1000
100
MHz
33.31
33.3
FSLC1FSLB
CLKSEL2
0
Table : ICS954306
D D
FSB Frequency Selet:
CLK_Ra
CLK_Rb
CPU Driven
(Default)
*
533MHz
667MHz
Stuff
No Stuff
Stuff
No Stuff
Stuff
No Stuff
CLK_Rd
CLK_Rd
CLK_Ra
CLK_Rd
CLK_Ra
CLK_Re
+VCCP
R560
@
R550
8.2K_0402_5%
C C
B B
FSA CLK_48M_CB
CPU_BSEL05
CPU_BSEL15
CPU_BSEL25
CLKREF1
R575
0_0402_5%
CLK_Ra
R565
0_0402_5%
CLK_Rb
R494
8.2K_0402_5%
R492
0_0402_5%
CLK_Rc
56_0402_5%
CLK_Rd
R576
1K_0402_5%
FSB
+VCCP
+VCCP
R561
1K_0402_5%
R566
1K_0402_5%
R564
1K_0402_5%
R539
@
0_0402_5%
CLK_Re
R490
1K_0402_5%
R491
1K_0402_5%
R493
@
0_0402_5%
CLK_Rf
CLK_Rc
CLK_Rf
CLK_Re
CLK_Rf
CLK_Re
CLK_Rb
CLK_Rc
+VCCP
CLK_Rf
CLK_Rc
CLK_Rb
MCH_CLKSEL0 7 CLK_48M_CB24
MCH_CLKSEL1 7
MCH_CLKSEL2 7
+CK_VDD_DP
C447
0.1U_0402_16V4ZDP@
CLK_PCI_SIO31
CLK_PCI_DB27
NOXDP@ : means just build when XDP function disable.
XDP@ : means just build when XDP function enable.
When this time, docking PCI express will not work.
+3VS
R537
10K_0402_5%@
A A
CLK_ENABLE#
R549
300_0402_5%
J14
PAD-No SHORT 2x2m@
5
LCD(Low)/SRC(High)
clock select
+3VS +3VS
R535
10K_0402_5%
PCI_ICH PCI_MINI
R536
10K_0402_5%@
High:Pin18/19 = 100MHz
*
Low:Pin18/19 = 96MHz Low:Pin44/45 = CPUCLK2_ITP
+3VS
+3VS
+3VS
R474
0_0402_5%DP@
CLK_48M_ICH21
CLK_14M_ICH21
H_STP_CPU#21
H_STP_PCI#21
CLK_ENABLE#37,45
CLK_PCI_ICH19
CLK_14M_KBC33
CLK_14M_SIO31
CLK_PCI_EC33
CLK_PCI_TCG32
CLK_PCI_PCM23
ICH_SMBDATA4,13,14,18,21,25,27
ICH_SMBCLK4,13,14,18,21,25,27
4
+CK_VDD_MAIN1
R502 0_0805_5%
R453 0_0805_5%
R506
0_0805_5%NODP@
R508
0_0805_5%DP@
0.1U_0402_16V4Z
CLKIREF
0.1U_0402_16V4Z
+3VS
R518 12_0402_5%
R531 12_0402_5%DB@
C452
10U_0805_10V4Z
+CK_VDD_MAIN2
C496
10U_0805_10V4Z
+CK_VDD_DP
C457
10U_0805_10V4Z
+CK_VDD_DP
C469
C448
CLK_48M_ICH
CLK_14M_ICH
H_STP_CPU#
H_STP_PCI#
CLK_ENABLE#
CLK_PCI_ICH PCI_ICH
CLK_14M_KBC
CLK_14M_SIO
ICH_SMBDATA
ICH_SMBCLK
R538 12_0402_5%
R551 12_0402_5%
33_0402_5%
R496 12_0402_5%
R498 12_0402_5%
Pin44/45 function select
R501
R504
10K_0402_5%XDP@
High:Pin44/45 = CLKREQ
*
4
CK_VDD_48
CK_VDD_REF
R489
R4724.7K_0402_1%LPNO@
R534
33_0402_5%
R51310K_0402_5%
R53210K_0402_5%@
R52833_0402_5%
R51933_0402_5%
R53333_0402_5%
10K_0402_5%NOXDP@
C451
.01U_0402_16V7K
C430
0.1U_0402_16V4Z
C470
0.1U_0402_16V4Z
+CK_VDD_MAIN1
FSA
FSB
CLKREF1
CLKIREF
CLKREF0
PCI_MINI
PCI_CLK3
PCI_EC
PCI_CLK5
PCI_PCM
PCI_CLK3
C449
.01U_0402_16V7K
C495
0.1U_0402_16V4Z
C465
0.1U_0402_16V4Z
U30
3
C468
.01U_0402_16V7K
R454
CK_VDD_REF
1_0805_1%
CK_VDD_48
R548
2.2_0805_1%
C450
0.1U_0402_16V4Z
Place crystal within
500 mils of CK410
CLK_XTAL_IN
CLK_XTAL_OUT
Routing the trace at least 10mil
L
R527 0_0402_5%
R517 0_0402_5%
Routing the trace at least 10mil
L
CPU_BCLK
R475 24_0402_5%
CPU_BCLK#
R476 24_0402_5%
MCH_BCLK
MCH_BCLK#
PCIE_MXM
PCIE_MXM#
11/14
PCIE_LOM
PCIE_LOM#
PCIE_SATA
PCIE_SATA# CLK_PCIE_SATA#
R477 24_0402_5%
R478 24_0402_5%
11/21
R510 10K_0402_5%@
R552 24_0402_5%
R553 24_0402_5%
R540 24_0402_5%
R541 24_0402_5%
R558 24_0402_5%
R559 24_0402_5%
R507 10K_0402_5%
2
C439 27P_0402_50V8J
Y6
14.31818MHZ_20P_6X1430004201
C440 27P_0402_50V8J
CLK_CPU_BCLK
CLK_CPU_BCLK#
CLK_MCH_BCLK
CLK_MCH_BCLK#
CLKREQA#
CLK_PCIE_MXM
CLK_PCIE_MXM#
CLK_PCIE_LOM
CLK_PCIE_LOM#
CLK_PCIE_SATA CLK_PCIE_SATA
CPPE#CLKREQB#
11/14
PCIE_DOCK CLK_PCIE_DOCK
R542 24_0402_5%
R543 24_0402_5%
R486 24_0402_5%
R487 24_0402_5%
R479 0_0402_5%NOXDP@
CPU_XDP
R480 33_0402_5%XDP@
MCH_3GPLL
R484 24_0402_5%
MCH_3GPLL#
R485 24_0402_5%
R455 0_0402_5%NOXDP@
CPU_XDP#
R481 33_0402_5%XDP@
PCIE_MCARD
R482 24_0402_5%
PCIE_MCARD#
R483 24_0402_5%
ICS954306BGLFT_TSSOP64
* Internal Pull-Up Re sistor
** Internal Pull-Down Re sistor
Security Classification
Issued Date
THIS SHEET OF ENGINEERI NG DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATIO N. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUT HORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DIS CLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2005/03/10 2006/03/10
Compal Secret Data
Deciphered Date
CLK_PCIE_DOCK#PCIE_DOCK#
CLK_PCIE_ICHPCIE_ICH
CLK_PCIE_ICH#PCIE_ICH#
R461 10K_0402_5%NOXDP@
CLKREQC#
CLK_CPU_XDP
CLK_MCH_3GPLL
CLK_MCH_3GPLL#
R451 10K_0402_5%NOXDP@
CLKREQD#
CLK_CPU_XDP#
CLK_PCIE_MCARD
CLK_PCIE_MCARD#
2
1
Place near U25
Place these components
near each pin within 40
mils.
CLK_CPU_BCLK 4
CLK_CPU_BCLK# 4
CLK_MCH_BCLK 7
CLK_MCH_BCLK# 7
+3VS
CLKREQA# 18,25
CLK_PCIE_MXM 18
CLK_PCIE_MXM# 18
CLK_PCIE_LOM 25
CLK_PCIE_LOM# 25
CLK_PCIE_SATA 20
CLK_PCIE_SATA# 20
CPPE# 19,35
CLK_PCIE_DOCK 35
CLK_PCIE_DOCK# 35
CLK_PCIE_ICH 21
CLK_PCIE_ICH# 21
+3VS
CLKREQC# 7
CLK_CPU_XDP 4
CLK_MCH_3GPLL 7
CLK_MCH_3GPLL# 7
+3VS
CLKREQD# 27
CLK_CPU_XDP# 4
CLK_PCIE_MCARD 27
CLK_PCIE_MCARD# 27
Title
Size Document Number Rev
Date: Sheet of
CLK_CPU_BCLK
R457 49.9_0402_1%@
CLK_CPU_BCLK#
R458 49.9_0402_1%@
CLK_MCH_BCLK
R459 49.9_0402_1%@
CLK_MCH_BCLK#
R460 49.9_0402_1%@
CLK_PCIE_MXM
R562 49.9_0402_1%@
CLK_PCIE_MXM#
R563 49.9_0402_1%@
CLK_PCIE_LOM
R554 49.9_0402_1%@
CLK_PCIE_LOM#
R555 49.9_0402_1%@
R567 49.9_0402_1%@
CLK_PCIE_SATA#
R568 49.9_0402_1%@
CLK_MCH_3GPLL
R466 49.9_0402_1%@
CLK_MCH_3GPLL#
R467 49.9_0402_1%@
CLK_PCIE_MCARD
R464 49.9_0402_1%@
CLK_PCIE_MCARD#
R465 49.9_0402_1%@
CLK_PCIE_ICH
R468 49.9_0402_1%@
CLK_PCIE_ICH#
R469 49.9_0402_1%@
CLK_CPU_XDP
R462 49.9_0402_1%@
CLK_CPU_XDP#
R463 49.9_0402_1%@
CLK_PCIE_DOCK
R556 49.9_0402_1%@
CLK_PCIE_DOCK#
R557 49.9_0402_1%@
If LP Chip stuff, all 49.9_0402
L
could be removed .
Compal Electronics, Inc.
Clock generator
LA-2821P
1
15 52Saturday, January 14, 2006
1.0
A
CRT Connector
1 1
+5VS
M_HSYNC18
M_VSYNC18
R306
R308
2 2
51K_0402_5%
51K_0402_5%
B
GREEN35
+5VS
C293
0.1U_0402_16V4Z
U24
SN74AHCT1G125GW_SOT353-5
Place cloce to MXM connector JP39
L
C294
0.1U_0402_16V4Z
HSYNC D_HSYNC
VSYNC D_VSYNC
U23
SN74AHCT1G125GW_SOT353-5
BLUE35
RED35
R312
0_0603_5%
R310
0_0603_5%
5P_0402_50V8C@
C326
BLUE
GREEN
RED
C77
5P_0402_50V8C
@
C325
C74
5P_0402_50V8C
@
5P_0402_50V8C@
R31
0_0603_5%
R29
0_0603_5%
R26
0_0603_5%
C73
C71
5P_0402_50V8C
@
18P_0402_50V8J@
C
C76
18P_0402_50V8J@
D_DDCDATA35
+5VS
F1
1.1A_6VDC_FUSE
C75
18P_0402_50V8J@
D_HSYNC 35
D_VSYNC 35
D_DDCCLK35
D3
CH491D_SC59
C420
0.1U_0402_16V4Z
RED_R
GREEN_R
BLUE_R
W=40mils
+CRTVDD +CRTVDD
R446
2.2K_0402_5%
D_DDCDATA
D_DDCCLK
+CRTVDD+RCRT_VCC
JP7
FOX_DZ11A91-L7
R445
2.2K_0402_5%
L
D
BLUE
GREEN
RED
R666
R665
12/02
150_0402_1%@
150_0402_1%@
+3VS
R450
R449
2.2K_0402_5%
2.2K_0402_5%
DSQ68
BSS138_SOT23
Q67
BSS138_SOT23
G
D
M_DDCDATA
G
M_DDCCLK
S
Place cloce to MXM connector JP39
E
R664
150_0402_1%@
M_DDCDATA 18
M_DDCCLK 18
TV-Out Connector
Place cloce to TV-Out connector JP1
3 3
M_LUMA18,35
M_CRMA
M_CRMA18,35
M_COMP
M_COMP18,35
C478
18P_0402_50V8J@
4 4
A
B
C459
18P_0402_50V8J@
R545 0_0603_5%
R516 0_0603_5%
R529 0_0603_5%
C488
18P_0402_50V8J@
Place cloce to TV-Out connector JP1
L
Security Classification
Issued Date
THIS SHEET OF ENGINEERI NG DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATIO N. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUT HORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DIS CLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
L
D7
DAN217_SC59@
C
D6
DAN217_SC59@
M_LUMA_RM_LUMA
M_CRMA_R
M_COMP_R
2005/03/10 2006/03/10
Compal Secret Data
D8
DAN217_SC59@
SUYIN_33007SR-07T1-C
Deciphered Date
+3VS
JP10
Title
Size Document Number Rev
D
Date: Sheet of
Compal Electronics, Inc.
CRT & TVout Connector
LA-2821P
16 52Saturday, January 14, 2006
E
1.0
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