Compal LA-2821 AngelFire 3.0, Compaq nw9440, Compaq nx9420 Schematic

A

1 1

2 2

B

C

D

E

Compal confidential

Schematics Document

Mobile Yonah uF CPGA with Intel
Calis toga_PM+ICH7-M core logic

3 3

4 4

A

B

2006-01-13

REV:1.0

Security Classification

Issued Date

THIS SHEET OF ENGINEERI NG DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATIO N. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUT HORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DIS CLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2005/03/10 2006/03/10

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

D

Date: Sheet of

Compal Electronics, Inc.

Cover Sheet

LA-2821P

1 52Saturday, January 14, 2006

E

1.0

A

Compal confidential

File Name : LA-2821P

B

C

D

E

Ang elFire 3.0

1 1

A ccelerometer
LIS3LV02DQ

page 27

Fan Control

page 4

Mobile Yonah

uFCPGA-478 CPU

Th ermal Sensor
A DM1032AR

page 4page 4,5,6

Clock Generator

I CS954306

page 15

A ccelerometer
LIS3LV02DQ

page 27

FSB

H_A#( 3..31)

MXM III connector

page 18

P CI-E x 16

Intel Calistoga MCH

CRT / TV-OUT

page 16

2 2

LCD CONN

page 17

P CI-E BUS

P CI BUS

10/100/1000 LAN

L ED

3 3

page 32

RTC CKT.

page 20

BCM5753M

page 25,26

RJ45/11 CONN

page 26

Min i-Card

page 27

1 394 port

CardBus Controller

TI PCI7612

Slo t 0/Smart Card

page 23

page 23,24

6 in1 Slot

page 24

Power OK CKT.

page 37

Power On/Off CKT.

page 34

4 4

DC/DC Interface CKT.

page 36

Security Module

Touch Pad CONN.

TrackPoint CONN.

SMSC KBC 1021

page 34

Power Circuit DC/DC

Page 38,39,40,41,42,43,44,45,46,47

A

B

533/667MHz

H_D#(0..63)

DDR2 -400/533/667

9 45PM

P CBGA 1466

page 7,8,9,10,11,12

Dual Channel

USB2.0

D MI

Intel ICH7-M

AC-LINK/Azalia

mBGA-652

page 19,20,21,22

page 23

SPI

SPI ROM
SST25LF080A

page 23

SATA Master

PATA Slave

LPC BUS

SMSC Super I/O

page 33

LPC47N217

I nt.KBD

page 34page 34

Security Classification

Issued Date

THIS SHEET OF ENGINEERI NG DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATIO N. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUT HORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DIS CLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

COM1 L PT
( Docking ) ( Docking )

page 35 page 35

2005/03/10 2006/03/10

Compal Secret Data

page 31page 32

Deciphered Date

DDR2-SO-DIMM X2

BANK 0, 1, 2, 3

page 13,14

U SB conn x2
( Docking)

USB2.0 HUB /
F P Conn

U SB conn x2

BT Conn

USB conn x2
(Sub Board)

Audio CKT A MP & Audio Jack

AD1981HD

page 35

FingerPrinter AES2501

page 30

page 30

page 30

page 29

page 28 page 29

U SBx1

New Card USBx1

MDC1.5

page 34

MAX9710ETP

page 30

page 24

SATA HDD Connector

page 20

PATA ODD Connector

page 20

F lash ROM

SST49LF008A

D

page 32

Title

Size Document Number Rev

Date: Sheet of

Docking CONN.

*RJ-45(LED*2)
*RJ-11(Pass Through)
*CRT
*COMPOSITE Video Out
*TVOUT
*DVI
*LINE IN
*LINE OUT
*PCI-E x2
*Serial Port
*Parallel Port
*PS/2 x2
*USB x2
*DC JACK

Compal Electronics, Inc.

Block Diagram

LA-2821P

E

page 34

1.0

2 52Saturday, January 14, 2006

5

4

3

2

1

Voltage Rails

Power Plane

VIN

D D

C C

B+
+CPU_CORE
+ VCCP
+0.9VS

+1.5VS
+ 1.8V

+2.5VS

+3VALW

+5VALW
+ 5VS
+RT C_VCC

Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.

Description

Adapter power supply (18.5V)
AC or battery power rail for power circuit
Core voltage for CPU

1.05V power rail for Processor I/O and MCH/ICH core power

0.9V switched power rail for DDRII Vtt

1.5V switched power rail for PCI-E interface

1.8V power rail for DDRII

3.3V al ways on power rail+2. 5VALW ON ON O N*

3.3V al ways on power rail

3.3V sw itched power rail+ 3VS
5V always on power rail
5V switched power rail
RT C power ONON

S3

S0-S1

N/A

N/A

N/A
ON OFF
ON

OFF
ON

OFF

ON

OFF
ON

ON
ON+1.8VS OFF OFF1.8V sw itched power rail
ON OFF

ON

ON
ON OFF OFF
ON

ON
ON

OFF

ON

S5

N/A
N/AN/A
OFF
OFF
OFF

OFF
OFF

OFF2.5V switched power rail for MCH video PLL

O N*

O N*
OFF

Inte rnal PCI Devices

DEVI CE

L AN
A zalia D27

USB1.1/2.0
PCI to PCI (DMI to PCI)
AC97 MODEM
AC97 Audio
PATA/SATA
LPC I/F
S MBUS
CPU I/F

B B

PCI Device ID

Bus

1
0
0
0
0
0
0
0
0
0
0
0
0

D8

D28PCI-E
D29
D30
D30
D30
D31
D31
D31

D31 AD15D MA
D31 AD15P MU

I DSEL #

AD24
AD11
AD12
AD13
AD14
AD14
AD14
AD15
AD15
AD15
AD15D31

External PCI Devices

DEVI CE

Mini-PCI
CARD BUS

PCI Device ID

D4
D6

I DSEL #

AD20
AD22

REQ/GNT #

0
2

PI RQ

F
C D E G

Symbol Note :

: means Digital Ground

: means Analog Ground

Note: Layout Related Memo

L

: Layout Note related Area Mark.

: Question Area Mark.(Wait check)

: Modified Area Mark.

12/12

: C-BOM impact

: Modified Area Mark(Compare with EAL60).

@ : means just reserve , no build
SPI@ : means just build when SPI I/F BIOS function reserve.

*

FWH@ : means just build when FWH I/F BIOS function reserve.

*

NOXDP@ : means just build when XDP function disable.

*

XDP@ : means just build when XDP function enable. When this time, docking PCI express will not work.
TPM1.2@ : means just build when TPM1.2 function enable.

*

TPM@ : means just build when TPM function enable.

*

SC@ : means just build when SmartCard function enable.

*

SATA@ : means just build when SATA I/F HDD enable.

*

NOSATA@ : means just build when SATA I/F HDD disable.
NC@ : means just build when New Card function enable.

*

NONC@ : means just build when New Card function disable.
MDC1.5@ : means just build when MDC1.5 function enable.

*

7612@ : means just build when TI PCI7612 chip selected.

*

7611@ : means just build when TI PCI7611MLS chip selected.
250@ : means just build when SMsC LPC47N250 chip selected.
1021@ : means just build when SMsC KBC1021 chip selected.

*

1981HD@ : means just build when AD1981HD chip selected.

*

45@ : means need be mounted when 45 level assy or rework stage.
ACCEL@ : means just build when Accelerometer chip LIS3LV02DQ selected.

*

NODP@ : means just build when No DP design Clock Gen. selected.

*

DP@ : means just build when DP design Clock Gen. selected.
LPNO@ : means just build when No LP design ICS Clock Gen. selected.
LP@ : means just build when LP design ICS Clock Gen. selected.

*

DB@ : means just build when Mini-PCI E Debug Card function enable.

*

* : means define for SMT build when this stage

I2C / SMBUS ADDRESSING

DEVI CE

A A

DDR SO-DIMM 0
DDR SO-DIMM 1
CLOCK GENERATOR (EXT.)
US B HUB 5C 0 1 0 1 1 1 0 0

5

HEX

A0
A4
D2

ADDRESS

1 0 1 0 0 0 0 0
1 0 1 0 0 1 0 0
1 1 0 1 0 0 1 0

Security Classification

Issued Date

THIS SHEET OF ENGINEERI NG DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATIO N. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUT HORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

4

MAY BE USED BY OR DIS CLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/03/10 2006/03/10

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

2

Date: Sheet of

Compal Electronics, Inc.

Notes List

LA-2821P

3 52Saturday, January 14, 2006

1

1.0

5

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8

D D

H_REQ#[0..4]7

H_ADSTB#07

C C

R448

56_0402_5%

+VCCP

B B

H_PROCHOT#45

+VCCP

56_0402_5%

H_THERMDA, H_THERMDC routing together.
Trace width / Spacing = 10 / 10 mil

A A

H_ADSTB#17

CLK_CPU_BCLK15

CLK_CPU_BCLK#15

H_ADS#7
H_BNR#7
H_BPRI#7

H_BR0#7

H_DEFER#7

H_DRDY#7

H_HIT#7

H_HITM#7

H_LOCK#7

H_RESET#7

H_RS#[0..2]7

H_TRDY#7

XDP_DBRESET#21

H_DBSY#7

H_DPSLP#20

H_DPRSTP#20,45

H_DPWR#7

R447

H_PWRGOOD20

H_CPUSLP#7

R27 1K_0402_5%@
R28 51_0402_5%

H_THERMTRIP#7,20

+VCCP

H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

H_ADSTB#0
H_ADSTB#1

CLK_CPU_BCLK
CLK_CPU_BCLK#

H_ADS#
H_BNR#
H_BPRI#
H_BR0#
H_DEFER#
H_DRDY#
H_HIT#
H_HITM#
H_IERR#
H_LOCK#
H_RESET#

H_RS#0
H_RS#1
H_RS#2
H_TRDY#

XDP_BPM#0
XDP_BPM#1
XDP_BPM#2
XDP_BPM#3

XDP_DBRESET#

H_DBSY#
H_DPSLP#
H_DPRSTP#
H_DPWR#
XDP_BPM#4
XDP_BPM#5
H_PROCHOT#

H_PWRGOOD
H_CPUSLP#
XDP_TCK
XDP_TDI
XDP_TDO
TEST1
TEST2
XDP_TMS
XDP_TRST#

H_THERMDA
H_THERMDC
H_THERMTRIP#

JP8A

ADDR GROUP

HOST CLK

CONTROL

FOX_PZ47903-2741-42_YONAH

YONAH

MISC

THERMAL
DIODE

4

DATA GROUP

LEGACY CPU

H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63

H_DINV#0
H_DINV#1
H_DINV#2
H_DINV#3

H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3
H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3

H_A20M#
H_FERR#
H_IGNNE#
H_INIT#
H_INTR
H_NMI

H_STPCLK#
H_SMI#

H_D#[0..63] 7H_A#[3..31]7

H_DINV#0 7
H_DINV#1 7
H_DINV#2 7
H_DINV#3 7

H_DSTBN#[0..3] 7

H_DSTBP#[0..3] 7

H_A20M# 20
H_FERR# 20
H_IGNNE# 20
H_INIT# 20
H_INTR 20
H_NMI 20

H_STPCLK# 20
H_SMI# 20

3

2

ITP-XDP Connector

XDP_BPM#5
XDP_BPM#4

XDP_BPM#3
XDP_BPM#2

XDP_BPM#1
XDP_BPM#0

R442

H_PWRGOOD_RH_PWRGOOD CLK_CPU_XDP

1K_0402_5%

+VCCP +VCCP

C539 0.1U_0402_16V4Z

ICH_SMBDATA
ICH_SMBCLK

XDP_TCK

JP31

SAMTE_BSH-030-01-L-D-A

Thermal Sensor ADM1032AR-2

+3VS

C69

0.1U_0402_16V4Z

H_THERMDA

C68

H_THERMDC

2200P_0402_50V7K

+3VS

THERM#

R25

10K_0402_5%

PWM Fan Control circuit

D1

CH751H-40_SC76

+3VS

FAN_PWM33

THERM#

U31

TC7SH00FUF_SSOP5

G

CLK_CPU_XDP#

XDP_TDO
XDP_TRST#
XDP_TDI
XDP_TMS
XDP_PRE

U5

ADM1032AR-2_MSOP8

Address:1001_101

ICH_SMBCLK13,14,15,18,21,25,27

ICH_SMBDATA13,14,15,18,21,25,27

+5VS

D

Q69
AO6402_TSOP6

S

XDP_DBRESET#_R

This shall place nea r CPU

XDP_TDI
XDP_TMS
XDP_TDO
XDP_BPM#5
XDP_TRST#
XDP_TCK

1K_0402_1%

R441
R444

200_0402_1%

R191 0_0402_5%

ICH_SMBCLK
ICH_SMBDATA
THERM_SCI#

ICH_SMBCLK
ICH_SMBDATA

C65

4.7U_0805_10V4Z

FAN

1

5/10

R443

1K_0402_5%@

+VCCP

R524 56_0402_5%
R523 56_0402_1%
R525 56_0402_5%
R526 56_0402_5%
R521 56_0402_5%
R522 56_0402_5%

CLK_CPU_XDP 15

H_RESET#H_RESET#_R
XDP_DBRESET#XDP_DBRESET#_R

C63

0.1U_0402_16V4Z

@

RLZ5.1B_LL34

CLK_CPU_XDP# 15

R24
10K_0402_5%

THERM_SCI# 21

ACES_85205-0200

ZD1

+3VS

JP6

R30

56_0402_5%@

B

E

H_PROCHOT# OCP#

C

Q6

MMBT3904_SOT23@

5

OCP# 21,47

H_DPSLP#

H_DPRSTP#

R439

56_0402_5%@

R440

56_0402_5%@

4

Security Classification

Issued Date

THIS SHEET OF ENGINEERI NG DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATIO N. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUT HORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DIS CLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/03/10 2006/03/10

Compal Secret Data

Deciphered Date

2

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

Yonah CPU in mFCPGA479

LA-2821P

4 52Saturday, January 14, 2006

1

1.0

5

4

3

2

1

V_CPU_GTLREF

+VCCP

R37
1K_0402_1%

R39
2K_0402_1%

+VCC_CORE

R42
100_0402_1%

VCCSENSE

R41
100_0402_1%

VSSSENSE

Close to CPU pin
within 500mils.

CPU_BSEL CPU_BSEL2 CPU_BSEL1

133

166

R35

27.4_0402_1%

0 0

0

R36

54.9_0402_1%

D D

Close to CPU pin AD26
within 500mils.

C C

B B

Length match within 25 mils
The trace width 18 mils space
7 mils

+1.5VS

C70

0.01U_0402_16V7K

CPU_BSEL0

1

1

Resistor placed within

0.5" of CPU pin.Trace
should be at least 25
mils away from any
other toggling signal.

R470

27.4_0402_1%

1

R473

54.9_0402_1%

C72

10U_0805_10V4Z

CPU_VID045
CPU_VID145
CPU_VID245
CPU_VID345
CPU_VID445
CPU_VID545
CPU_VID645

V_CPU_GTLREF

CPU_BSEL015
CPU_BSEL115
CPU_BSEL215

VCCSENSE45

VSSSENSE45

H_PSI#45

+VCCP

+VCC_CORE

VCCSENSE
VSSSENSE

H_PSI#
CPU_VID0

CPU_VID1
CPU_VID2
CPU_VID3
CPU_VID4
CPU_VID5
CPU_VID6

CPU_BSEL0
CPU_BSEL1
CPU_BSEL2

COMP0
COMP1
COMP2
COMP3

JP8B

YONAH

POWER, GROUNG, RESERVED SIGNALS AND NC

+VCC_CORE

JP8C

YONAH

POWER, GROUND

FOX_PZ47903-2741-42_YONAH

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERI NG DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATIO N. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUT HORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DIS CLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/03/10 2006/03/10

Compal Secret Data

Deciphered Date

2

FOX_PZ47903-2741-42_YONAH

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

Yonah CPU in mFCPGA479

LA-2821P

5 52Saturday, January 14, 2006

1

1.0

5

4

3

2

1

D D

Place these capacitors on L8
(North side,Secondary Layer)

Place these capacitors on L8
(North side,Secondary Layer)

Place these capacitors on L8
(Sorth side,Secondary Layer)

C C

Place these capacitors on L8
(Sorth side,Secondary Layer)

+VCC_CORE

C412
10U_0805_6.3V6M

+VCC_CORE

C411
10U_0805_6.3V6M

+VCC_CORE

C441
10U_0805_6.3V6M

+VCC_CORE

C442
10U_0805_6.3V6M

C413
10U_0805_6.3V6M

C481
10U_0805_6.3V6M

C423
10U_0805_6.3V6M

C435
10U_0805_6.3V6M

C414
10U_0805_6.3V6M

C480
10U_0805_6.3V6M

C432
10U_0805_6.3V6M

C436
10U_0805_6.3V6M

C415
10U_0805_6.3V6M

C486
10U_0805_6.3V6M

C422
10U_0805_6.3V6M

C443
10U_0805_6.3V6M

C416
10U_0805_6.3V6M

C418
10U_0805_6.3V6M

C446
10U_0805_6.3V6M

C444
10U_0805_6.3V6M

C417
10U_0805_6.3V6M

C482
10U_0805_6.3V6M

C424
10U_0805_6.3V6M

C427
10U_0805_6.3V6M

C425
10U_0805_6.3V6M

C483
10U_0805_6.3V6M

C445
10U_0805_6.3V6M

C426
10U_0805_6.3V6M

C479
10U_0805_6.3V6M

C484
10U_0805_6.3V6M

C485
10U_0805_6.3V6M

C431
10U_0805_6.3V6M

Mid Frequence Decoupling

+VCC_CORE

South Side Secondary

+

C408

B B

330U_D2E_2.5VM_R9@

C409

330U_D2E_2.5VM_R9@

330U_D2E_2.5VM_R7

+

C67

+

C66

330U_D2E_2.5VM_R7

330U_D2E_2.5VM_R7

+

C117

+

820U_E9_2_5V_M_R7@

+

C119

C125

330U_D2E_2.5VM_R7

+

North Side Secondary

+

C120

820U_E9_2_5V_M_R7@

ESR <= 1.5m ohm
Capacitor > 1980uF

+VCCP

+

C434

220U_D2_2VK_R9

A A

5

C437

0.1U_0402_10V6K

C429

0.1U_0402_10V6K

C421

0.1U_0402_10V6K

4

C438

0.1U_0402_10V6K

C428

0.1U_0402_10V6K

Security Classification

Issued Date

THIS SHEET OF ENGINEERI NG DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATIO N. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUT HORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DIS CLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C433

0.1U_0402_10V6K

3

Place these in side
socket cavity o n L8
(North side
Secondary)

2005/03/10 2006/03/10

Compal Secret Data

Deciphered Date

2

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

CPU Bypass capacitors

LA-2821P

6 52Saturday, January 14, 2006

1

1.0

5

4

3

2

1

H_D#[0..63]4

D D

C C

+VCCP

R350

R381

54.9_0402_1%

54.9_0402_1%

H_XSCOMP/H_YSCOMP trace

L

width and spacing is 5/20.

B B

R339

24.9_0402_1%

+VCCP

A A

R360

R348

H_VREF
H_XRCOMP
H_XSCOMP
H_YRCOMP
H_YSCOMP
H_SWNG0
H_SWNG1

R395

24.9_0402_1%

Layout Note:
H_XRCOMP / H_YRCOMP / H_VREF / H_SWNG0 /
H_SWNG1 trace width and spacing is 18/20.

100_0402_1%

H_VREF

C330

200_0402_1%

0.1U_0402_16V4Z

5

H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63

U4A

HOST

CALISTOGA_A2_FCBGA1466

R351

R344

221_0603_1%

H_SWNG0

100_0402_1%

4

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

H_ADSTB#0
H_ADSTB#1

CLK_MCH_BCLK#
CLK_MCH_BCLK

H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3
H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3

H_DINV#0
H_DINV#1
H_DINV#2
H_DINV#3

H_RESET#
H_ADS#
H_TRDY#
H_DPWR#
H_DRDY#
H_DEFER#
H_HITM#
H_HIT#
H_LOCK#
H_BR0#
H_BNR#
H_BPRI#
H_DBSY#
H_CPUSLP#

H_RS#0
H_RS#1
H_RS#2

C328

0.1U_0402_16V4Z

+VCCP+VCCP

R17

R18

H_A#[3..31] 4

H_REQ#[0..4] 4

H_ADSTB#0 4
H_ADSTB#1 4

CLK_MCH_BCLK# 15
CLK_MCH_BCLK 15
H_DSTBN#[0..3] 4

H_DSTBP#[0..3] 4

H_DINV#0 4
H_DINV#1 4
H_DINV#2 4
H_DINV#3 4

H_RESET# 4
H_ADS# 4
H_TRDY# 4
H_DPWR# 4
H_DRDY# 4
H_DEFER# 4
H_HITM# 4
H_HIT# 4
H_LOCK# 4
H_BR0# 4
H_BNR# 4
H_BPRI# 4
H_DBSY# 4
H_CPUSLP# 4

H_RS#[0..2] 4

221_0603_1%

H_SWNG1

C359

100_0402_1%

0.1U_0402_16V4Z

U4B

CALISTOGA_A2_FCBGA1466

Layout Note:
Route as short
as possible

R412

40.2_0402_1%

+1.8V

DMI_TXN0
DMI_TXN1
DMI_TXN2
DMI_TXN3

DMI_TXP0
DMI_TXP1
DMI_TXP2
DMI_TXP3

DMI_RXN0
DMI_RXN1
DMI_RXN2
DMI_RXN3

DMI_RXP0
DMI_RXP1
DMI_RXP2
DMI_RXP3

M_CLK_DDR0
M_CLK_DDR1
M_CLK_DDR2
M_CLK_DDR3

M_CLK_DDR#0
M_CLK_DDR#1
M_CLK_DDR#2
M_CLK_DDR#3

DDR_CKE0_DIMMA
DDR_CKE1_DIMMA
DDR_CKE2_DIMMB
DDR_CKE3_DIMMB

DDR_CS0_DIMMA#
DDR_CS1_DIMMA#
DDR_CS2_DIMMB#
DDR_CS3_DIMMB#

M_OCDOCMP0
M_OCDOCMP1

M_ODT0
M_ODT1
M_ODT2
M_ODT3

SMRCOMPN
SMRCOMPP

PM_BMBUSY#
PM_EXTTS#0
PM_EXTTS#1
H_THERMTRIP#
PWROK
PLTRST_R#

PWROK

R409

100_0402_1%@

R411

100_0402_1%@

DMI_TXN021
DMI_TXN121
DMI_TXN221
DMI_TXN321

DMI_TXP021
DMI_TXP121
DMI_TXP221
DMI_TXP321

DMI_RXN021
DMI_RXN121
DMI_RXN221
DMI_RXN321

DMI_RXP021
DMI_RXP121
DMI_RXP221
DMI_RXP321

M_CLK_DDR013
M_CLK_DDR113
M_CLK_DDR214
M_CLK_DDR314

M_CLK_DDR#013
M_CLK_DDR#113
M_CLK_DDR#214
M_CLK_DDR#314

DDR_CKE0_DIMMA13
DDR_CKE1_DIMMA13
DDR_CKE2_DIMMB14
DDR_CKE3_DIMMB14

DDR_CS0_DIMMA#13
DDR_CS1_DIMMA#13
DDR_CS2_DIMMB#14
DDR_CS3_DIMMB#14

+1.8V

R419 80.6_0402_1%
R413 80.6_0402_1%

DPRSLPVR21,45

VGATE_INTEL21,45

V_DDR_MCH_REF13,14,44

R65 0_0402_5%

PLT_RST#19,20,21,23,25,27,32,33

R597 0_0402_5%@

PM_POK21,33

R590 0_0402_5%

M_ODT013
M_ODT113
M_ODT214
M_ODT314

V_DDR_MCH_REF

PM_BMBUSY#21

H_THERMTRIP#4,20

R408 100_0402_1%

MCH_ICH_SYNC#19

Layout Note:
V_DDR_MCH_REF
trace width and
spacing is 20/20.

V_DDR_MCH_REF

C385

0.1U_0402_16V4Z

Stuff R1202 & R1203 for A1 Calistoga

Security Classification

Issued Date

THIS SHEET OF ENGINEERI NG DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATIO N. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUT HORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DIS CLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/03/10 2006/03/10

Compal Secret Data

Deciphered Date

2

DMI

DDR MUXING

PM

M_OCDOCMP0
M_OCDOCMP1

R400

40.2_0402_1%

CFG

CLKNC

RESERVED

PM_EXTTS#0

PM_EXTTS#1

GMCH_A27

GMCH_A26

GMCH_C40

GMCH_D41

DDR_THERM#13,14

Title

Size Document Number Rev

Date: Sheet of

Description at page11.

MCH_CLKSEL0
MCH_CLKSEL1
MCH_CLKSEL2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG16
CFG17
CFG18
CFG19
CFG20

CLK_MCH_3GPLL
CLK_MCH_3GPLL#

GMCH_A27
GMCH_A26

GMCH_C40
GMCH_D41

CLKREQC#

R353

10K_0402_5%

R362

10K_0402_5%@

R15

10K_0402_5%

R14

10K_0402_5%

R338

10K_0402_5%

R342

10K_0402_5%

R343

0_0402_5%

5/16

PAD

PAD
PAD

PAD
PAD

8/24

PM_EXTTS#0DDR_THERM#

MCH_CLKSEL0 15
MCH_CLKSEL1 15
MCH_CLKSEL2 15

T1
T2PAD

CFG5 11

T4PAD

CFG7 11

T3

CFG9 11

T7

CFG11 11
CFG12 11

CFG13 11

T6PAD
T5

CFG16 11

T8

CFG18 11

CFG19 11

CFG20 11

CLK_MCH_3GPLL 15

CLK_MCH_3GPLL# 15

CLKREQC# 15

+3VS

Compal Electronics, Inc.

Calistoga (1/6)

LA-2821P

7 52Saturday, January 14, 2006

1

1.0

5

D D

4

3

2

1

DDR_A_BS#013
DDR_A_BS#113
DDR_A_BS#213

DDR_A_DM[0..7]13

DDR_A_DQS[0..7]13

C C

DDR_A_DQS#[0..7]13

DDR_A_MA[0..13]13

B B

DDR_A_CAS#13
DDR_A_RAS#13

DDR_A_WE#13

T11 PAD
T12 PAD T10 PAD

DDR_A_BS#0
DDR_A_BS#1
DDR_A_BS#2

DDR_A_DM0
DDR_A_DM1
DDR_A_DM2
DDR_A_DM3
DDR_A_DM4
DDR_A_DM5
DDR_A_DM6
DDR_A_DM7

DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7

DDR_A_DQS#0
DDR_A_DQS#1
DDR_A_DQS#2
DDR_A_DQS#3
DDR_A_DQS#4
DDR_A_DQS#5
DDR_A_DQS#6
DDR_A_DQS#7

DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5

DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11 DDR_B_MA11
DDR_A_MA12
DDR_A_MA13

DDR_A_CAS#
DDR_A_RAS#
DDR_A_WE#
SA_RCVENIN#
SA_RCVENOUT#

U4D

DDR SYS MEMORY A

CALISTOGA_A2_FCBGA1466

DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63

DDR_A_D[0..63] 13 DDR_B_D[0..63] 14

DDR_B_BS#014
DDR_B_BS#114
DDR_B_BS#214

DDR_B_DM[0..7]14

DDR_B_DQS[0..7]14

DDR_B_DQS#[0..7]14

DDR_B_MA[0..13]14

DDR_B_CAS#14

DDR_B_RAS#14

DDR_B_WE#14

T9 PAD

DDR_B_BS#0
DDR_B_BS#1
DDR_B_BS#2

DDR_B_DM0
DDR_B_DM1
DDR_B_DM2
DDR_B_DM3
DDR_B_DM4
DDR_B_DM5
DDR_B_DM6
DDR_B_DM7

DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4
DDR_B_DQS5
DDR_B_DQS6
DDR_B_DQS7

DDR_B_DQS#0
DDR_B_DQS#1
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS#4
DDR_B_DQS#5
DDR_B_DQS#6
DDR_B_DQS#7

DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6DDR_A_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10

DDR_B_MA12
DDR_B_MA13

DDR_B_CAS#
DDR_B_RAS#
DDR_B_WE#
SB_RCVENIN#
SB_RCVENOUT#

U4E

DDR SYS MEMORY B

CALISTOGA_A2_FCBGA1466

DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERI NG DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATIO N. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUT HORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DIS CLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/03/10 2006/03/10

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

2

Date: Sheet of

Compal Electronics, Inc.

Calistoga (2/6)

LA-2821P

8 52Saturday, January 14, 2006

1

1.0

5

D D

C C

R363 10K_0402_5%

B B

R355 10K_0402_5%

+VCCP

4

U4C

LVDS

+1.5VS

TV CRT

PCI-EXPRESS GRAPHICS

CALISTOGA_A2_FCBGA1466

3

PEGCOMP trace width

L

and spacing is 18/25 mils.

PEGCOMP

PEG_RXP15
PEG_RXP14
PEG_RXP13
PEG_RXP12
PEG_RXP11
PEG_RXP10
PEG_RXP9
PEG_RXP8
PEG_RXP7
PEG_RXP6
PEG_RXP5
PEG_RXP4
PEG_RXP3
PEG_RXP2
PEG_RXP1
PEG_RXP0

PEG_RXN15
PEG_RXN14
PEG_RXN13
PEG_RXN12
PEG_RXN11
PEG_RXN10
PEG_RXN9
PEG_RXN8
PEG_RXN7
PEG_RXN6
PEG_RXN5
PEG_RXN4
PEG_RXN3
PEG_RXN2
PEG_RXN1
PEG_RXN0

PEG_TXP15
PEG_TXP14
PEG_TXP13
PEG_TXP12
PEG_TXP11
PEG_TXP10
PEG_TXP9
PEG_TXP8
PEG_TXP7
PEG_TXP6
PEG_TXP5
PEG_TXP4
PEG_TXP3
PEG_TXP2
PEG_TXP1
PEG_TXP0

PEG_TXN15
PEG_TXN14
PEG_TXN13
PEG_TXN12
PEG_TXN11
PEG_TXN10
PEG_TXN9
PEG_TXN8
PEG_TXN7
PEG_TXN6
PEG_TXN5
PEG_TXN4
PEG_TXN3
PEG_TXN2
PEG_TXN1
PEG_TXN0

+1.5VS_PCIE

R331

24.9_0402_1%

PEG_RXP[0..15] 18

PEG_RXN[0..15] 18

C22 0.1U_0402_16V4Z
C24 0.1U_0402_16V4Z
C26 0.1U_0402_16V4Z
C30 0.1U_0402_16V4Z
C32 0.1U_0402_16V4Z
C34 0.1U_0402_16V4Z
C37 0.1U_0402_16V4Z
C41 0.1U_0402_16V4Z
C45 0.1U_0402_16V4Z
C47 0.1U_0402_16V4Z
C49 0.1U_0402_16V4Z
C51 0.1U_0402_16V4Z
C53 0.1U_0402_16V4Z
C56 0.1U_0402_16V4Z
C58 0.1U_0402_16V4Z
C61 0.1U_0402_16V4Z

C20 0.1U_0402_16V4Z
C23 0.1U_0402_16V4Z
C25 0.1U_0402_16V4Z
C28 0.1U_0402_16V4Z
C31 0.1U_0402_16V4Z
C33 0.1U_0402_16V4Z
C35 0.1U_0402_16V4Z
C38 0.1U_0402_16V4Z
C43 0.1U_0402_16V4Z
C46 0.1U_0402_16V4Z
C48 0.1U_0402_16V4Z
C50 0.1U_0402_16V4Z
C52 0.1U_0402_16V4Z
C54 0.1U_0402_16V4Z
C57 0.1U_0402_16V4Z
C60 0.1U_0402_16V4Z

2

PEG_M_TXP15
PEG_M_TXP14
PEG_M_TXP13
PEG_M_TXP12
PEG_M_TXP11
PEG_M_TXP10
PEG_M_TXP9
PEG_M_TXP8
PEG_M_TXP7
PEG_M_TXP6
PEG_M_TXP5
PEG_M_TXP4
PEG_M_TXP3
PEG_M_TXP2
PEG_M_TXP1
PEG_M_TXP0

PEG_M_TXN15
PEG_M_TXN14
PEG_M_TXN13
PEG_M_TXN12
PEG_M_TXN11
PEG_M_TXN10
PEG_M_TXN9
PEG_M_TXN8
PEG_M_TXN7
PEG_M_TXN6
PEG_M_TXN5
PEG_M_TXN4
PEG_M_TXN3
PEG_M_TXN2
PEG_M_TXN1
PEG_M_TXN0

1

PEG_M_TXP[0..15] 18

PEG_M_TXN[0..15] 18

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERI NG DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATIO N. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUT HORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DIS CLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/03/10 2006/03/10

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

2

Date: Sheet of

Compal Electronics, Inc.

Calistoga (3/6)

LA-2821P

9 52Saturday, January 14, 2006

1

1.0

5

4

3

2

1

D D

+

C42

220U_D2_2VK_R9

C C

C339

C368

4.7U_0805_10V4Z

2.2U_0805_16V4Z

MCH_A6

C317

B B

C336

0.22U_0603_10V7K

0.47U_0603_10V7K

MCH_D2

C318

MCH_AB1

C55

0.22U_0603_10V7K

0.47U_0603_10V7K

+VCCP

U4H

P O W E R

W=40 mils

220U_D2_4VM_R25

+1.5VS_3GPLL
+2.5VS

MCH_CRTDAC

PAD-No SHORT 2x2m
R333
0_0805_5%@

+1.5VS_HPLL

R356

0_0805_5%

+1.5VS_MPLL

+1.5VS

+1.5VS

+1.5VS

+1.5VS_TVDAC

+1.5VS

C377

C297

9/ 15

J5

PAD-SHORT 2x2m

J4

C322

0.1U_0402_16V4Z

0.1U_0402_16V4Z

+1.5VS_PCIE

10U_0805_6.3V6M

C315

+

+VCCP

+2.5VS

+3VS

C320

10U_0805_6.3V6M

R410

0_0805_5%

C380

10U_0805_6.3V6M

+1.5VS

+2.5VS

C329

0.1U_0402_16V4Z

close pin G41

PCI-E/MEM/PSB PLL decoupling

R398

0.5_0805_1%

C371

0.1U_0402_16V4Z

45mA Max. 45mA Max.

0.1U_0402_16V4Z

C378

10U_0805_6.3V6M

+1.5VS_MPLL +1.5VS_HPLL

C373

R23

0_0805_5%

C62

10U_0805_6.3V6M

R396

0_0805_5%

0.1U_0402_16V4Z@

+1.5VS+1.5VS_3GPLL

C387

0.1U_0402_16V4Z

+1.5VS_TVDAC +1.5VS

0.022U_0402_16V7K@

C374

C324

10U_0805_6.3V6M@

R332

0_0805_5%

C316

R22

0_0805_5%

C59

10U_0805_6.3V6M

C319

0.022U_0402_16V7K@

+1.5VS+1.5VS

+1.5VS

CALISTOGA_A2_FCBGA1466

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MA Y BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2005/03/10 2006/03/10

3

Compal Secret Data

D eciphered Date

Compal Electronics, Inc.

Calistoga (4/6)

2

Date: Sheet of

LA-2821P

10 52Saturday, January 14, 2006

1

1.0

5

+VCCP

D D

C333

C367

C337

10U_0805_6.3V6M

C C

B B

C375

0.22U_0603_10V7K

0.22U_0603_10V7K

10U_0805_6.3V6M

C338

C343

C64

220U_D2_2VK_R9

C386

+

330U_D2E_2.5VM_R9@

0.22U_0603_10V7K

1U_0603_10V4Z

+

+VCCP

U4F

P O W E R

CALISTOGA_A2_FCBGA1466

4

+1.5VS

VCCSM_LF2
VCCSM_LF1

+1.8V

C398

C390

0.47U_0603_10V7K

0.47U_0603_10V7K

+VCCP

U4G

P O W E R

3

+1.8V

VCCSM_LF4
VCCSM_LF5

C389

C395

0.47U_0603_10V7K

0.47U_0603_10V7K

Place near pin AT41 & AM41

C381

C382

0.1U_0402_16V4Z

C406

0.47U_0603_10V7K

Place near pin BA23

C405

C407

10U_0805_6.3V6M

10U_0805_6.3V6M

C404

0.47U_0603_10V7K

2

C384

0.1U_0402_16V4Z

0.1U_0402_16V4Z

+

C402

220U_D2_4VM@

L

CFG[2:0]

CFG5

CFG7

CFG9

CFG11

CFG[13:12]

+1.8V

CFG16

CFG18

C388

0.1U_0402_16V4Z

CFG19

SDVO_CTRLDATA

CFG20

(PCIE/SDVO select)

@wait DB-1 test verify

1

Strap Pin Table

CFG[3:17] have internal pull up
CFG[19:18] have internal pull down

011 = 667MT/s FSB
001 = 533MT/s FSB

0 = DMI x 2
1 = DMI x 4

0 = Reserved
1 = Mobile Yonah CPU

0 = Lane Reversal Enable
1 = Normal Operation

1 = Calistoga

(Accor ding to Intel Napa Schematic Checklist & CRB
Rev1.502 document 2.2Kohm pull-down resistor no request)

0 = Reserved

00 = Reserved
01 = XOR Mode Enabled
10 = All Z Mode Enabled
11 = Normal Operation

0 = Dynamic ODT Disabled
1 = Dynamic ODT Enabled (Default)

0 = 1.05V
1 = 1.5V

0 = Normal Operation
1 = DMI Lane Reversal Enable

0 = No SDVO Device Present

*

(Default)

(Default)

*

*

(Default)

(Default)

*

(Default)

(Default)

*

*

(Default)

*

1 = SDVO Device Present

0 = Only PCIE or SDVO is
operational.
1 = PCIE/SDVO are operating
simu.

R349 2.2K_0402_5%@

CFG57

R340 2.2K_0402_5%@

CFG77

R354 2.2K_0402_5%@

CFG97

R341 2.2K_0402_5%@

CFG117

R365 2.2K_0402_5%@

CFG127

R371 2.2K_0402_5%@

CFG137

R359 2.2K_0402_5%@

CFG167

R370 1K_0402_5%@

CFG187

R368 1K_0402_5%@

CFG197

R369 1K_0402_5%@

CFG207

(Default)

*

*

*

+3VS

Place near pin BA15

Place near pin AV1 & AJ1

A A

5

4

CALISTOGA_A2_FCBGA1466

Security Classification

Issued Date

THIS SHEET OF ENGINEERI NG DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATIO N. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUT HORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DIS CLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/03/10 2006/03/10

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

2

Date: Sheet of

Compal Electronics, Inc.

Calistoga (5/6)

LA-2821P

11 52Saturday, January 14, 2006

1

1.0

5

4

3

2

1

U4I

D D

U4J

P O W E R

P O W E R

C C

B B

CALISTOGA_A2_FCBGA1466

A A

5

CALISTOGA_A2_FCBGA1466

4

Security Classification

Issued Date

THIS SHEET OF ENGINEERI NG DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATIO N. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUT HORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DIS CLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/03/10 2006/03/10

Compal Secret Data

Deciphered Date

2

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

Calistoga (6/6)

LA-2821P

12 52Saturday, January 14, 2006

1

1.0

5

DDR_A_DQS#[0..7]8

DDR_A_D[0..63]8

DDR_A_DM[0..7]8

DDR_A_DQS[0..7]8

DDR_A_MA[0..13]8

D D

Layout Note:
Place near JP34

+1.8V

2.2U_0805_16V4Z

2.2U_0805_16V4Z

C467

C461

0.1U_0402_16V4Z

0.1U_0402_16V4Z

C79

RP11

RP7

RP15

RP10

RP9

RP8

5

2.2U_0805_16V4Z
C463

0.1U_0402_16V4Z

C78

C80

+0.9V

56_0404_4P2R_5%

56_0404_4P2R_5%

56_0404_4P2R_5%

56_0404_4P2R_5%

56_0404_4P2R_5%

56_0404_4P2R_5%

2.2U_0805_16V4Z

C462

C464

0.1U_0402_16V4Z

0.1U_0402_16V4Z

C82

C81

RP13 56_0404_4P2R_5%

RP18 56_0404_4P2R_5%

RP12 56_0404_4P2R_5%

RP17 56_0404_4P2R_5%

RP16 56_0404_4P2R_5%

RP14 56_0404_4P2R_5%

RP19 56_0404_4P2R_5%

0.1U_0402_16V4Z

0.1U_0402_16V4Z

C105

0.1U_0402_16V4Z

0.1U_0402_16V4Z

C84

C115

DDR_A_BS#2
DDR_CKE0_DIMMA

DDR_A_MA7
DDR_A_MA6

DDR_A_MA9
DDR_A_MA12

DDR_A_MA4
DDR_A_MA2

DDR_A_MA0
DDR_A_BS#1

M_ODT0
DDR_A_MA13

DDR_CKE1_DIMMA
DDR_A_MA11

0.1U_0402_16V4Z

2.2U_0805_16V4Z

C C

B B

A A

Layout Note:
Place one cap close to every 2 pullup
resistors terminated to +0.9V

+0.9V

0.1U_0402_16V4Z

C83

DDR_A_MA5
DDR_A_MA8

DDR_A_MA1
DDR_A_MA3

DDR_A_RAS#
DDR_CS0_DIMMA#

DDR_A_BS#0
DDR_A_MA10

DDR_A_CAS#
DDR_A_WE#

DDR_CS1_DIMMA#
M_ODT1

0.1U_0402_16V4Z

C93

0.1U_0402_16V4Z

C111

4

0.1U_0402_16V4Z

C91

C95

0.1U_0402_16V4Z

C112

C113

0.1U_0402_16V4Z

0.1U_0402_16V4Z

C110

Layout Note:
Place these resistor
closely JP34,all
trace length Max=1.5"

4

C114

3

+1.8V

JP9

DDR_A_D0
DDR_A_D4

DDR_A_DQS#0
DDR_A_DQS0

DDR_A_D2
DDR_A_D3

DDR_A_D8
DDR_A_D14

DDR_A_DQS#1
DDR_A_DQS1

DDR_A_D10
DDR_A_D11

DDR_A_D21
DDR_A_D17

DDR_A_DQS#2
DDR_A_DQS2

DDR_A_D22
DDR_A_D19 DDR_A_D23

DDR_A_D25
DDR_A_D24

DDR_A_DM3

DDR_A_D27
DDR_A_D30

DDR_CKE0_DIMMA7

DDR_A_BS#28

DDR_A_BS#08

DDR_A_WE#8

DDR_A_CAS#8

DDR_CS1_DIMMA#7

M_ODT17

ICH_SMBDATA4,14,15,18,21,25,27

ICH_SMBCLK4,14,15,18,21,25,27

DDR_CKE0_DIMMA

DDR_A_BS#2
DDR_A_MA12

DDR_A_MA9 DDR_A_MA7
DDR_A_MA8

DDR_A_MA5
DDR_A_MA3
DDR_A_MA1

DDR_A_MA10
DDR_A_BS#0
DDR_A_WE#

DDR_A_CAS#
DDR_CS1_DIMMA#

M_ODT1
DDR_A_D34

DDR_A_D38
DDR_A_DQS#4

DDR_A_DQS4
DDR_A_D39

DDR_A_D35
DDR_A_D45

DDR_A_D41
DDR_A_DM5
DDR_A_D42

DDR_A_D43
DDR_A_D52

DDR_A_D53

DDR_A_DQS#6
DDR_A_DQS6

DDR_A_D55
DDR_A_D56

DDR_A_D61
DDR_A_DM7
DDR_A_D58

DDR_A_D59
ICH_SMBDATA

ICH_SMBCLK

+3VS

C96

0.1U_0402_16V4Z

FOX_ASOA426-M4R-TR

SO-DIMM A

2

REVERSE

Security Classification

Issued Date

THIS SHEET OF ENGINEERI NG DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATIO N. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUT HORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DIS CLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/03/10 2006/03/10

Compal Secret Data

Top side

Deciphered Date

2

+1.8V

V_DDR_MCH_REF

DDR_A_D7
DDR_A_D1

DDR_A_DM0
DDR_A_D5

DDR_A_D6
DDR_A_D12

DDR_A_D13
DDR_A_DM1
M_CLK_DDR0

M_CLK_DDR#0
DDR_A_D9

DDR_A_D15

DDR_A_D20
DDR_A_D16

DDR_THERM#
DDR_A_DM2

DDR_A_D18

DDR_A_D29
DDR_A_D28

DDR_A_DQS#3
DDR_A_DQS3

DDR_A_D26
DDR_A_D31

DDR_CKE1_DIMMA

DDR_A_MA11
DDR_A_MA6
DDR_A_MA4

DDR_A_MA2
DDR_A_MA0

DDR_A_BS#1
DDR_A_RAS#
DDR_CS0_DIMMA#

M_ODT0
DDR_A_MA13

DDR_A_D36
DDR_A_D33

DDR_A_DM4
DDR_A_D37

DDR_A_D32
DDR_A_D40

DDR_A_D44
DDR_A_DQS#5

DDR_A_DQS5
DDR_A_D47

DDR_A_D46
DDR_A_D48

DDR_A_D49
M_CLK_DDR1

M_CLK_DDR#1
DDR_A_DM6
DDR_A_D50DDR_A_D51

DDR_A_D54
DDR_A_D60

DDR_A_D57
DDR_A_DQS#7

DDR_A_DQS7
DDR_A_D62

DDR_A_D63

R40

R38

10K_0402_5%

1

2.2U_0805_16V4Z

0.1U_0402_16V4Z

C97

M_CLK_DDR0 7
M_CLK_DDR#0 7

DDR_THERM# 7,14

DDR_CKE1_DIMMA 7

DDR_A_BS#1 8
DDR_A_RAS# 8
DDR_CS0_DIMMA# 7

M_ODT0 7

M_CLK_DDR1 7
M_CLK_DDR#1 7

10K_0402_5%

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

DDRII-SODIMM SLOT1

LA-2821P

V_DDR_MCH_REF 7,14,44

C92

1

13 52Saturday, January 14, 2006

1.0

5

DDR_B_DQS#[0..7]8

DDR_B_D[0..63]8

DDR_B_DM[0..7]8

DDR_B_DQS[0..7]8

DDR_B_MA[0..13]8

D D

C C

B B

A A

Layout Note:
Place near JP34

+1.8V

2.2U_0805_16V4Z

Layout Note:
Place one cap close to every 2 pullup
resistors terminated to +0.9V

+0.9V

0.1U_0402_16V4Z

C85

DDR_B_MA1
DDR_B_MA3

DDR_B_BS#0
DDR_B_MA10

DDR_B_MA0
DDR_B_BS#1

DDR_B_RAS#
DDR_CS2_DIMMB#

DDR_B_CAS#
DDR_B_WE#

DDR_CS3_DIMMB# M_ODT2
M_ODT3

2.2U_0805_16V4Z

C109

C108

0.1U_0402_16V4Z

0.1U_0402_16V4Z

C86

RP34

RP35

RP3

RP2

RP36

RP37

5

2.2U_0805_16V4Z

2.2U_0805_16V4Z

C460

0.1U_0402_16V4Z

C87

C88

+0.9V

56_0404_4P2R_5%

56_0404_4P2R_5%

56_0404_4P2R_5%

56_0404_4P2R_5%

56_0404_4P2R_5%

56_0404_4P2R_5%

2.2U_0805_16V4Z

C466

C107

0.1U_0402_16V4Z

0.1U_0402_16V4Z

C89

C90

RP32 56_0404_4P2R_5%

RP6 56_0404_4P2R_5%

RP33 56_0404_4P2R_5%

RP5 56_0404_4P2R_5%

RP4 56_0404_4P2R_5%

RP1 56_0404_4P2R_5%

RP31

56_0404_4P2R_5%

0.1U_0402_16V4Z

DDR_B_MA9
DDR_B_MA12

DDR_B_MA7
DDR_CKE3_DIMMB

DDR_B_MA5
DDR_B_MA8

DDR_B_MA6
DDR_B_MA11

DDR_B_MA4
DDR_B_MA2

DDR_B_MA13

DDR_B_BS#2
DDR_CKE2_DIMMB

0.1U_0402_16V4Z

0.1U_0402_16V4Z

C94

0.1U_0402_16V4Z

C476

C477

5/16

5/16

0.1U_0402_16V4Z

C455

0.1U_0402_16V4Z

C475

4

0.1U_0402_16V4Z

C106

C454

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

C473

C474

Layout Note:
Place these resistor
closely JP10,all
trace length Max=1.5"

4

0.1U_0402_16V4Z

C471

C472

3

+1.8V

JP29

DDR_B_D0
DDR_B_D5

DDR_B_DQS#0
DDR_B_DQS0

DDR_B_D7
DDR_B_D3

DDR_B_D8
DDR_B_D9

DDR_B_DQS#1
DDR_B_DQS1

DDR_B_D10
DDR_B_D11

DDR_B_D20
DDR_B_DQS#2

DDR_B_DQS2
DDR_B_D22

DDR_B_D23
DDR_B_D24

DDR_B_D25
DDR_B_DM3

DDR_B_D30
DDR_B_D31

DDR_CKE2_DIMMB7

DDR_B_BS#28

DDR_B_BS#08
DDR_B_WE#8

DDR_B_CAS#8

DDR_CS3_DIMMB#7

M_ODT37

ICH_SMBDATA4,13,15,18,21,25,27

ICH_SMBCLK4,13,15,18,21,25,27

Security Classification

Issued Date

THIS SHEET OF ENGINEERI NG DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATIO N. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUT HORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DIS CLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

DDR_CKE2_DIMMB

DDR_B_BS#2
DDR_B_MA12

DDR_B_MA9
DDR_B_MA8

DDR_B_MA5
DDR_B_MA3
DDR_B_MA1

DDR_B_MA10
DDR_B_BS#0
DDR_B_WE#

DDR_B_CAS#
DDR_CS3_DIMMB#

M_ODT3
DDR_B_D37

DDR_B_D36
DDR_B_DQS#4

DDR_B_DQS4
DDR_B_D35

DDR_B_D34
DDR_B_D40

DDR_B_D41
DDR_B_DM5
DDR_B_D42

DDR_B_D47
DDR_B_D48

DDR_B_D53

DDR_B_DQS#6
DDR_B_DQS6

DDR_B_D51
DDR_B_D50

DDR_B_D60
DDR_B_D61

DDR_B_DM7
DDR_B_D58

DDR_B_D59
ICH_SMBDATA

ICH_SMBCLK

+3VS

C453

0.1U_0402_16V4Z

2005/03/10 2006/03/10

FOX_ASOA426-M2RN-7F

SO- DIMM B
STANDA RD

Compal Secret Data

Bottom side

Deciphered Date

2

2

+1.8V

V_DDR_MCH_REF

DDR_B_D4
DDR_B_D1

DDR_B_DM0
DDR_B_D6

DDR_B_D2
DDR_B_D12

DDR_B_D13
DDR_B_DM1
M_CLK_DDR3

M_CLK_DDR#3
DDR_B_D14

DDR_B_D15

DDR_B_D16DDR_B_D21
DDR_B_D18

DDR_THERM#
DDR_B_DM2

DDR_B_D17
DDR_B_D19

DDR_B_D26
DDR_B_D28

DDR_B_DQS#3
DDR_B_DQS3

DDR_B_D29
DDR_B_D27

DDR_CKE3_DIMMB

DDR_B_MA11
DDR_B_MA7
DDR_B_MA6

DDR_B_MA4
DDR_B_MA2
DDR_B_MA0

DDR_B_BS#1
DDR_B_RAS#
DDR_CS2_DIMMB#

M_ODT2
DDR_B_MA13

DDR_B_D33
DDR_B_D32

DDR_B_DM4
DDR_B_D38

DDR_B_D39
DDR_B_D44

DDR_B_D45
DDR_B_DQS#5

DDR_B_DQS5
DDR_B_D43

DDR_B_D46
DDR_B_D49

DDR_B_D52
M_CLK_DDR2

M_CLK_DDR#2
DDR_B_DM6
DDR_B_D54

DDR_B_D55
DDR_B_D56

DDR_B_D57
DDR_B_DQS#7

DDR_B_DQS7
DDR_B_D62

DDR_B_D63

1

V_DDR_MCH_REF 7,13,44

0.1U_0402_16V4Z

2.2U_0805_16V4Z

C103

C99

M_CLK_DDR3 7
M_CLK_DDR#3 7

DDR_THERM# 7,13

DDR_CKE3_DIMMB 7

DDR_B_BS#1 8
DDR_B_RAS# 8
DDR_CS2_DIMMB# 7

M_ODT2 7

M_CLK_DDR2 7
M_CLK_DDR#2 7

R33

10K_0402_5%

10K_0402_5%

R34

Title

Size Document Number Rev

Date: Sheet of

+3VS

Compal Electronics, Inc.

DDRII-SODIMM SLOT2

LA-2821P

1

14 52Saturday, January 14, 2006

1.0

5

PCI

SRC

CPU

CLKSEL1

0

1

FSLA

CLKSEL0

MHz

133

166

MHz

1000

100

MHz

33.31

33.3

FSLC1FSLB

CLKSEL2

0

Table : ICS954306

D D

FSB Frequency Selet:

CLK_Ra

CLK_Rb

CPU Driven

(Default)

*

533MHz

667MHz

Stuff

No Stuff

Stuff

No Stuff

Stuff

No Stuff

CLK_Rd

CLK_Rd

CLK_Ra

CLK_Rd

CLK_Ra
CLK_Re

+VCCP

R560

@

R550

8.2K_0402_5%

C C

B B

FSA CLK_48M_CB

CPU_BSEL05

CPU_BSEL15

CPU_BSEL25

CLKREF1

R575

0_0402_5%

CLK_Ra

R565

0_0402_5%

CLK_Rb

R494

8.2K_0402_5%

R492

0_0402_5%

CLK_Rc

56_0402_5%

CLK_Rd

R576

1K_0402_5%

FSB

+VCCP

+VCCP

R561
1K_0402_5%

R566
1K_0402_5%

R564

1K_0402_5%

R539

@

0_0402_5%

CLK_Re

R490
1K_0402_5%

R491

1K_0402_5%

R493

@

0_0402_5%

CLK_Rf

CLK_Rc

CLK_Rf

CLK_Re

CLK_Rf

CLK_Re

CLK_Rb

CLK_Rc

+VCCP

CLK_Rf

CLK_Rc

CLK_Rb

MCH_CLKSEL0 7 CLK_48M_CB24

MCH_CLKSEL1 7

MCH_CLKSEL2 7

+CK_VDD_DP

C447

0.1U_0402_16V4ZDP@

CLK_PCI_SIO31
CLK_PCI_DB27

NOXDP@ : means just build when XDP function disable.
XDP@ : means just build when XDP function enable.

When this time, docking PCI express will not work.

+3VS

R537

10K_0402_5%@

A A

CLK_ENABLE#

R549

300_0402_5%

J14

PAD-No SHORT 2x2m@

5

LCD(Low)/SRC(High)
clock select

+3VS +3VS

R535
10K_0402_5%

PCI_ICH PCI_MINI

R536

10K_0402_5%@

High:Pin18/19 = 100MHz

*

Low:Pin18/19 = 96MHz Low:Pin44/45 = CPUCLK2_ITP

+3VS

+3VS

+3VS

R474
0_0402_5%DP@

CLK_48M_ICH21

CLK_14M_ICH21

H_STP_CPU#21

H_STP_PCI#21

CLK_ENABLE#37,45

CLK_PCI_ICH19

CLK_14M_KBC33

CLK_14M_SIO31

CLK_PCI_EC33

CLK_PCI_TCG32

CLK_PCI_PCM23

ICH_SMBDATA4,13,14,18,21,25,27

ICH_SMBCLK4,13,14,18,21,25,27

4

+CK_VDD_MAIN1

R502 0_0805_5%

R453 0_0805_5%

R506

0_0805_5%NODP@

R508

0_0805_5%DP@

0.1U_0402_16V4Z

CLKIREF

0.1U_0402_16V4Z

+3VS

R518 12_0402_5%
R531 12_0402_5%DB@

C452
10U_0805_10V4Z

+CK_VDD_MAIN2

C496
10U_0805_10V4Z

+CK_VDD_DP

C457
10U_0805_10V4Z

+CK_VDD_DP

C469

C448

CLK_48M_ICH

CLK_14M_ICH

H_STP_CPU#
H_STP_PCI#

CLK_ENABLE#
CLK_PCI_ICH PCI_ICH

CLK_14M_KBC
CLK_14M_SIO

ICH_SMBDATA
ICH_SMBCLK

R538 12_0402_5%

R551 12_0402_5%

33_0402_5%

R496 12_0402_5%

R498 12_0402_5%

Pin44/45 function select

R501

R504

10K_0402_5%XDP@

High:Pin44/45 = CLKREQ

*

4

CK_VDD_48

CK_VDD_REF

R489

R4724.7K_0402_1%LPNO@

R534

33_0402_5%

R51310K_0402_5%
R53210K_0402_5%@
R52833_0402_5%

R51933_0402_5%
R53333_0402_5%

10K_0402_5%NOXDP@

C451
.01U_0402_16V7K

C430

0.1U_0402_16V4Z

C470

0.1U_0402_16V4Z

+CK_VDD_MAIN1

FSA
FSB
CLKREF1

CLKIREF

CLKREF0

PCI_MINI
PCI_CLK3

PCI_EC
PCI_CLK5
PCI_PCM

PCI_CLK3

C449
.01U_0402_16V7K

C495

0.1U_0402_16V4Z

C465

0.1U_0402_16V4Z

U30

3

C468
.01U_0402_16V7K

R454

CK_VDD_REF

1_0805_1%

CK_VDD_48

R548

2.2_0805_1%

C450

0.1U_0402_16V4Z

Place crystal within
500 mils of CK410

CLK_XTAL_IN
CLK_XTAL_OUT

Routing the trace at least 10mil

L

R527 0_0402_5%
R517 0_0402_5%

Routing the trace at least 10mil

L

CPU_BCLK

R475 24_0402_5%

CPU_BCLK#

R476 24_0402_5%

MCH_BCLK
MCH_BCLK#

PCIE_MXM
PCIE_MXM#

11/14

PCIE_LOM
PCIE_LOM#

PCIE_SATA
PCIE_SATA# CLK_PCIE_SATA#

R477 24_0402_5%

R478 24_0402_5%

11/21

R510 10K_0402_5%@

R552 24_0402_5%

R553 24_0402_5%

R540 24_0402_5%

R541 24_0402_5%

R558 24_0402_5%

R559 24_0402_5%

R507 10K_0402_5%

2

C439 27P_0402_50V8J

Y6

14.31818MHZ_20P_6X1430004201

C440 27P_0402_50V8J

CLK_CPU_BCLK
CLK_CPU_BCLK#

CLK_MCH_BCLK
CLK_MCH_BCLK#

CLKREQA#
CLK_PCIE_MXM
CLK_PCIE_MXM#

CLK_PCIE_LOM
CLK_PCIE_LOM#

CLK_PCIE_SATA CLK_PCIE_SATA

CPPE#CLKREQB#

11/14

PCIE_DOCK CLK_PCIE_DOCK

R542 24_0402_5%

R543 24_0402_5%

R486 24_0402_5%

R487 24_0402_5%

R479 0_0402_5%NOXDP@

CPU_XDP

R480 33_0402_5%XDP@

MCH_3GPLL

R484 24_0402_5%

MCH_3GPLL#

R485 24_0402_5%

R455 0_0402_5%NOXDP@

CPU_XDP#

R481 33_0402_5%XDP@

PCIE_MCARD

R482 24_0402_5%

PCIE_MCARD#

R483 24_0402_5%

ICS954306BGLFT_TSSOP64

* Internal Pull-Up Re sistor
** Internal Pull-Down Re sistor

Security Classification

Issued Date

THIS SHEET OF ENGINEERI NG DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATIO N. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUT HORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DIS CLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/03/10 2006/03/10

Compal Secret Data

Deciphered Date

CLK_PCIE_DOCK#PCIE_DOCK#

CLK_PCIE_ICHPCIE_ICH
CLK_PCIE_ICH#PCIE_ICH#

R461 10K_0402_5%NOXDP@

CLKREQC#
CLK_CPU_XDP
CLK_MCH_3GPLL
CLK_MCH_3GPLL#

R451 10K_0402_5%NOXDP@

CLKREQD#
CLK_CPU_XDP#
CLK_PCIE_MCARD
CLK_PCIE_MCARD#

2

1

Place near U25

Place these components
near each pin within 40
mils.

CLK_CPU_BCLK 4
CLK_CPU_BCLK# 4

CLK_MCH_BCLK 7
CLK_MCH_BCLK# 7

+3VS

CLKREQA# 18,25
CLK_PCIE_MXM 18
CLK_PCIE_MXM# 18

CLK_PCIE_LOM 25
CLK_PCIE_LOM# 25

CLK_PCIE_SATA 20
CLK_PCIE_SATA# 20

CPPE# 19,35

CLK_PCIE_DOCK 35
CLK_PCIE_DOCK# 35

CLK_PCIE_ICH 21
CLK_PCIE_ICH# 21

+3VS

CLKREQC# 7
CLK_CPU_XDP 4
CLK_MCH_3GPLL 7
CLK_MCH_3GPLL# 7

+3VS
CLKREQD# 27
CLK_CPU_XDP# 4
CLK_PCIE_MCARD 27
CLK_PCIE_MCARD# 27

Title

Size Document Number Rev

Date: Sheet of

CLK_CPU_BCLK

R457 49.9_0402_1%@

CLK_CPU_BCLK#

R458 49.9_0402_1%@

CLK_MCH_BCLK

R459 49.9_0402_1%@

CLK_MCH_BCLK#

R460 49.9_0402_1%@

CLK_PCIE_MXM

R562 49.9_0402_1%@

CLK_PCIE_MXM#

R563 49.9_0402_1%@

CLK_PCIE_LOM

R554 49.9_0402_1%@

CLK_PCIE_LOM#

R555 49.9_0402_1%@

R567 49.9_0402_1%@

CLK_PCIE_SATA#

R568 49.9_0402_1%@

CLK_MCH_3GPLL

R466 49.9_0402_1%@

CLK_MCH_3GPLL#

R467 49.9_0402_1%@

CLK_PCIE_MCARD

R464 49.9_0402_1%@

CLK_PCIE_MCARD#

R465 49.9_0402_1%@

CLK_PCIE_ICH

R468 49.9_0402_1%@

CLK_PCIE_ICH#

R469 49.9_0402_1%@

CLK_CPU_XDP

R462 49.9_0402_1%@

CLK_CPU_XDP#

R463 49.9_0402_1%@

CLK_PCIE_DOCK

R556 49.9_0402_1%@

CLK_PCIE_DOCK#

R557 49.9_0402_1%@

If LP Chip stuff, all 49.9_0402

L

could be removed .

Compal Electronics, Inc.

Clock generator

LA-2821P

1

15 52Saturday, January 14, 2006

1.0

A

CRT Connector

1 1

+5VS

M_HSYNC18

M_VSYNC18

R306

R308

2 2

51K_0402_5%

51K_0402_5%

B

GREEN35

+5VS

C293

0.1U_0402_16V4Z

U24
SN74AHCT1G125GW_SOT353-5

Place cloce to MXM connector JP39

L

C294

0.1U_0402_16V4Z

HSYNC D_HSYNC

VSYNC D_VSYNC

U23
SN74AHCT1G125GW_SOT353-5

BLUE35

RED35

R312

0_0603_5%

R310

0_0603_5%

5P_0402_50V8C@

C326

BLUE
GREEN
RED

C77

5P_0402_50V8C

@

C325

C74

5P_0402_50V8C

@

5P_0402_50V8C@

R31

0_0603_5%

R29

0_0603_5%

R26

0_0603_5%

C73

C71

5P_0402_50V8C

@

18P_0402_50V8J@

C

C76

18P_0402_50V8J@

D_DDCDATA35

+5VS

F1

1.1A_6VDC_FUSE

C75

18P_0402_50V8J@

D_HSYNC 35

D_VSYNC 35

D_DDCCLK35

D3

CH491D_SC59

C420

0.1U_0402_16V4Z

RED_R

GREEN_R

BLUE_R

W=40mils

+CRTVDD +CRTVDD

R446

2.2K_0402_5%

D_DDCDATA

D_DDCCLK

+CRTVDD+RCRT_VCC

JP7

FOX_DZ11A91-L7

R445

2.2K_0402_5%

L

D

BLUE
GREEN
RED

R666

R665

12/02

150_0402_1%@

150_0402_1%@

+3VS

R450

R449

2.2K_0402_5%

2.2K_0402_5%

DSQ68

BSS138_SOT23

Q67
BSS138_SOT23

G

D

M_DDCDATA

G

M_DDCCLK

S

Place cloce to MXM connector JP39

E

R664
150_0402_1%@

M_DDCDATA 18

M_DDCCLK 18

TV-Out Connector

Place cloce to TV-Out connector JP1

3 3

M_LUMA18,35

M_CRMA

M_CRMA18,35

M_COMP

M_COMP18,35

C478

18P_0402_50V8J@

4 4

A

B

C459

18P_0402_50V8J@

R545 0_0603_5%
R516 0_0603_5%

R529 0_0603_5%

C488

18P_0402_50V8J@

Place cloce to TV-Out connector JP1

L

Security Classification

Issued Date

THIS SHEET OF ENGINEERI NG DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATIO N. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUT HORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DIS CLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

L

D7
DAN217_SC59@

C

D6
DAN217_SC59@

M_LUMA_RM_LUMA
M_CRMA_R

M_COMP_R

2005/03/10 2006/03/10

Compal Secret Data

D8
DAN217_SC59@

SUYIN_33007SR-07T1-C

Deciphered Date

+3VS

JP10

Title

Size Document Number Rev

D

Date: Sheet of

Compal Electronics, Inc.

CRT & TVout Connector

LA-2821P

16 52Saturday, January 14, 2006

E

1.0

5

D D

4

3

2

1

LCD POWER CIRCUITMXM LVDS CONN

B+_LCD

C286

0.1U_0603_50V4Z
C287

68P_0402_50V8J

L13

B+

KC F BM-L11-201209-221LMA30T_0805

+3VS

C C

M_PWM18

INV_PWM33

J1

PAD-SHORT 2x2m

J2

PAD-No SHORT 2x2m@

LCDVDD

LID_SW#21,34

ALS_EN19

+5VS_INV
M_LCD_CLK18
M_LCD_DAT18

LID_SW#
ALS_EN

JP3

ACES_87216-5002

M_TXBCLK+ 18
M_TXBCLK- 18

M_TXB2+ 18
M_TXB2- 18

M_TXB1+ 18
M_TXB1- 18

M_TXB0+ 18
M_TXB0- 18

M_TXACLK+ 18
M_TXACLK- 18

M_TXA2+ 18
M_TXA2- 18

M_TXA1+ 18
M_TXA1- 18

M_TXA0+ 18
M_TXA0- 18

M_ENAVDD18

R307

100_0402_1%

Q55

2N7002_SOT23

M_ENAVDD

LCDVDD

D

S

G

R315

47K_0402_5%

Q56
DTC124EK_SC59

0.1U_0402_16V4Z

C288

Q1

AO3413_SOT23

D

S

G

C12

4.7U_0805_10V4Z

R309

1M_0402_5%

C298

0.047U_0402_16V7K

+3VALWLCDVDD

C289

4.7U_0805_10V4Z@

Q10
DTA114YKA_SC59

B B

+3VS

U11A

LID_SW#

M_ENBLT18

R86

100K_0402_5%

A A

5

SN74LVC08APW_TSSOP14

100K_0402_5%

47K

10K

D

G

R80

4

S

Q13
BSS138_SOT23

+5VS_INV+5VS

Security Classification

Issued Date

THIS SHEET OF ENGINEERI NG DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATIO N. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUT HORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DIS CLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/03/10 2006/03/10

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

2

Date: Sheet of

Compal Electronics, Inc.

LCD CONN.

LA-2821P

17 52Saturday, January 14, 2006

1

1.0

5

PEG_RXN[0..15]9

PEG_RXP[0..15]9
PEG_M_TXN[0..15]9
PEG_M_TXP[0..15]9

D D

C9

100U_25V_M

B+ +1.8VS

0.1U_0603_50V4Z

+

C11

JP5A

9/15

PEG_RXN15
PEG_RXP15

PEG_RXN14
PEG_RXP14

PEG_RXN13
PEG_RXP13

PEG_RXN12

C C

B B

PEG_RXP12
PEG_RXN11

PEG_RXP11
PEG_RXN10

PEG_RXP10
PEG_RXN9

PEG_RXP9
PEG_RXN8

PEG_RXP8
PEG_RXN7

PEG_RXP7
PEG_RXN6

PEG_RXP6
PEG_RXN5

PEG_RXP5
PEG_RXN4

PEG_RXP4
PEG_RXN3

PEG_RXP3
PEG_RXN2

PEG_RXP2

ACES_88990-2D28_GF

4

+1.8VS

+5VS

+3VS

R303

8.2K_0402_5%@

PEG_M_TXN15
PEG_M_TXP15

PEG_M_TXN14
PEG_M_TXP14

PEG_M_TXN13
PEG_M_TXP13

PEG_M_TXN12
PEG_M_TXP12

PEG_M_TXN11
PEG_M_TXP11

PEG_M_TXN10
PEG_M_TXP10

PEG_M_TXN9
PEG_M_TXP9

PEG_M_TXN8
PEG_M_TXP8

PEG_M_TXN7
PEG_M_TXP7

PEG_M_TXN6
PEG_M_TXP6

PEG_M_TXN5
PEG_M_TXP5

PEG_M_TXN4
PEG_M_TXP4

PEG_M_TXN3
PEG_M_TXP3

PEG_M_TXN2
PEG_M_TXP2

C292

4.7U_0805_10V4Z

PWR_GD 33,36,37,45,47

CLKREQA#15,25

ICH_SMBDATA4,13,14,15,21,25,27

ICH_SMBCLK4,13,14,15,21,25,27

MXM_CD1# 21,47

R311

ICH_SMBDATA
ICH_SMBCLK

ADP_PRES25,33,40,41,42,47

3

CLK_PCIE_MXM#15

CLK_PCIE_MXM15

0_0402_5%@

VGA_RST#21

R320 0_0402_5%
R319 0_0402_5%

MXM Address:100_1100

MXM_THERM#21

M_HSYNC16

M_VSYNC16

M_DDCCLK16

M_DDCDATA16

+5VALW

SLP_S3#21,25,28,29,33,35,36,40,43,44

R313 0_0402_5%

DVI_DETECT35

DVI_CLK-35

DVI_CLK+35

DVI_TX2-35

DVI_TX2+35

DVI_TX1-35

DVI_TX1+35

DVI_TX0-35

DVI_TX0+35

PEG_RXN1
PEG_RXP1

PEG_RXN0
PEG_RXP0

CLK_PCIE_MXM#
CLK_PCIE_MXM

VGA_RST#

MXM_SMBDATA
MXM_SMBCLK
MXM_THERM#
M_HSYNC
M_VSYNC
M_DDCCLK
M_DDCDATA

SLP_S3#

DVI_DETECT
DVI_CLK­DVI_CLK+

DVI_TX2­DVI_TX2+

DVI_TX1­DVI_TX1+

DVI_TX0­DVI_TX0+

2

JP5B

ACES_88990-2D28_GF

MXM_CD0#

PEG_M_TXN1
PEG_M_TXP1

PEG_M_TXN0
PEG_M_TXP0
MXM_CD0#
MXM_CRMA

MXM_LUMA
MXM_COMP
M_RED
M_GRN
M_BLU

C4

4.7U_0805_10V4Z

MXM_CD0# 21

R305

8.2K_0402_5%@

M_TXBCLK- 17
M_TXBCLK+ 17

M_TXB2- 17
M_TXB2+ 17

M_TXB1- 17
M_TXB1+ 17

M_TXB0- 17
M_TXB0+ 17

M_TXACLK- 17
M_TXACLK+ 17

M_TXA2- 17
M_TXA2+ 17

M_TXA1- 17
M_TXA1+ 17

M_TXA0- 17
M_TXA0+ 17

M_LCD_DAT 17
M_LCD_CLK 17
M_ENAVDD 17
M_PWM 17
M_ENBLT 17
DVI_DDC_DAT 35
DVI_DDC_CLK 35

+2.5VS
+3VS

1

+3VS

Place those components as close as

L

MXMIII connector within 500 mils.

MXM_LUMA

MXM_CRMA

MXM_COMP

R316

R314

150_0402_1%

150_0402_1%

A A

5

TV-Out Termination/EMI Filter

MXM_LUMA M_LUMA

MXM_CRMA

MXM_COMP

R317
150_0402_1%

82P_0402_50V8J

Place cloce to MXM connector JP39

L

82P_0402_50V8J

C17

C18

L8
CHB1608U301_0603

L9
CHB1608U301_0603

L7
CHB1608U301_0603

C19

82P_0402_50V8J

4

82P_0402_50V8J

C13

C15

82P_0402_50V8J

M_LUMA 16,35

M_CRMA

M_COMP

C14
82P_0402_50V8J

M_CRMA 16,35

M_COMP 16,35

Security Classification

Issued Date

THIS SHEET OF ENGINEERI NG DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATIO N. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUT HORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DIS CLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

M_RED RED_LL

M_GRN

M_BLU BLUE_LL

R10
150_0402_1%

2005/03/10 2006/03/10

Compal Secret Data

Deciphered Date

R11
150_0402_1%

CRT Termination/EMI Filter

L4

HLC0603CSCC39NJT_0603

L5

HLC0603CSCC39NJT_0603

L2

HLC0603CSCC39NJT_0603

R2
150_0402_1%

2

GREEN_LL

C3

18P_0402_50V8J

C7
18P_0402_50V8J

Title

Size Document Number Rev

Date: Sheet of

L1

HLC0603CSCCR11JT_0603

L6

HLC0603CSCCR11JT_0603

L3

HLC0603CSCCR11JT_0603

C2
18P_0402_50V8J

Place those components as close
as MXMIII connector within 500 mils.

Compal Electronics, Inc.

MXM III CONN

LA-2821P

D_RED

D_GREEN

D_BLUE

1

D_RED 35

D_GREEN 35

D_BLUE 35

1.0

18 52Saturday, January 14, 2006

5

4

3

2

1

D D

C C

B B

+3VS

R617 8.2K_0402_5%
R613 8.2K_0402_5%
R616 8.2K_0402_5%
R611 8.2K_0402_5%
R619 8.2K_0402_5%
R625 8.2K_0402_5%
R622 8.2K_0402_5%
R623 8.2K_0402_5%
R615 8.2K_0402_5%
R618 8.2K_0402_5%

+3VS

R106 8.2K_0402_5%
R107 8.2K_0402_5%
R105 8.2K_0402_5%
R635 8.2K_0402_5%
R626 8.2K_0402_5%
R628 8.2K_0402_5%
R624 8.2K_0402_5%
R632 8.2K_0402_5%@

9/2

R631 8.2K_0402_5%
R610 8.2K_0402_5%
R607 8.2K_0402_5%
R627 8.2K_0402_5%
R612 8.2K_0402_5%

PCI_DEVSEL#
PCI_STOP#
PCI_TRDY#
PCI_FRAME#
PCI_PLOCK#
PCI_IRDY#
PCI_SERR#
PCI_PERR#
PCI_REQ4#
PCI_REQ3#

PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#
PCI_PIRQE#
PCI_PIRQF#
PCI_PIRQG#
PCI_PIRQH#
PCI_REQ0#
PCI_REQ1#
PCI_REQ2#
CPPE#
ICH_GPIO48

PCI_AD[0..31]23

PCI_PIRQC#23
PCI_PIRQD#23

PCI_AD0
PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD6
PCI_AD7
PCI_AD8
PCI_AD9
PCI_AD10
PCI_AD11
PCI_AD12
PCI_AD13
PCI_AD14
PCI_AD15
PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20
PCI_AD21
PCI_AD22
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30
PCI_AD31

PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#

U10B

P CI

Interrupt I/F

MISC

ICH7M_B0_BGA652

PCI_REQ0#
PCI_GNT0#
PCI_REQ1#

PCI_REQ2#
PCI_GNT2#
PCI_REQ3#

PCI_REQ4#
ICH_GPIO48
CPPE#
ALS_EN#

PCI_CBE#0
PCI_CBE#1
PCI_CBE#2
PCI_CBE#3

PCI_IRDY#
PCI_PAR
PCI_PCIRST#
PCI_DEVSEL#
PCI_PERR#
PCI_PLOCK#
PCI_SERR#
PCI_STOP#
PCI_TRDY#

PCI_FRAME#

PCI_PLTRST#
CLK_PCI_ICH
PCI_PME#

PCI_PIRQE#
PCI_PIRQF#
PCI_PIRQG#
PCI_PIRQH#

PCI_REQ2# 23
PCI_GNT2# 23

CPPE# 15,35

PCI_CBE#0 23
PCI_CBE#1 23
PCI_CBE#2 23
PCI_CBE#3 23

PCI_IRDY# 23
PCI_PAR 23

PCI_DEVSEL# 23
PCI_PERR# 23

PCI_SERR# 23,33
PCI_STOP# 23
PCI_TRDY# 23
PCI_FRAME# 23

CLK_PCI_ICH 15
PCI_PME# 23

PCI_PIRQE# 23
PCI_PIRQG# 23

R636
0_0402_5%

MCH_ICH_SYNC# 7

PCI_PCIRST#

PCI_PLTRST#

ACCEL_INT 27

11/23

R675

0_0402_5%

Place closely pin A9

CLK_PCI_ICH

R621

10_0402_5%@

C145

8.2P_0402_50V@

ALS_EN#

R83

1K_0402_5%SPI@

ALS_EN#

R71
0_0402_5%

R66
0_0402_5%@

+5VS

R89
330_0402_5%

ALS_EN

D

Q15

G

2N7002_SOT23

S

+3VS

U9

TC7SH08FU_SSOP5@

+3VS

U11D
SN74LVC08APW_TSSOP14

ALS_EN 17

PCI_RST#

R676

0_0402_5%

PLT_RST#

PCI_RST# 23,24

PLT_RST# 7,20,21,23,25,27,32,33

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERI NG DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATIO N. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUT HORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DIS CLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/03/10 2006/03/10

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

2

Date: Sheet of

Compal Electronics, Inc.

ICH7-M(1/4)

LA-2821P

19 52Saturday, January 14, 2006

1

1.0

5

4

3

2

1

C158 18P_0402_50V8J

Y1

32.768KHZ_12.5P_1TJS125BJ2A251

D D

C C

B B

+RTCVCC

+3VALW

R102
332K_0402_1%@

SATA_TXP0_C SATA_TXP0

L

A A

SATA_RXN0_C

SATA_RXP0_C

R645
20K_0402_5%

CMOS_CLR1

SHORT PADS

C159

1U_0603_10V4Z

AC97_BITCLK_MDC34

AC97_BITCLK_CODEC28

AC97_SYNC_MDC34

AC97_SYNC_CODEC28

AC97_RST#_MDC34

AC97_RST#_CODEC28

AC97_SDOUT_CODEC28

AC97_SDOUT_MDC34

+RTCVCC

R103
332K_0402_1%

ICH_INTVRMEN

R101

0_0402_5%@

C150 3900P_0402_50V7K

C149 3900P_0402_50V7K

Near ICH7(U26) side.

C175 3900P_0402_50V7K

C173 3900P_0402_50V7K

C157 18P_0402_50V8J

+RTCVCC

1M_0402_5%

CLK_PCIE_SATA#15
CLK_PCIE_SATA15

+3VS

SATA_TXN0SATA_TXN0_C

SATA_RXN0

SATA_RXP0

R629

AC97_SDIN028
AC97_SDIN134

+RTCVCC +3VL

C403
1U_0603_10V4Z

45@

ICH_RTCX1

R96
10M_0402_5%

ICH_RTCX2
ICH_RTCRST#
ICH_INTVRMEN

SM_INTRUDER#

R10033_0402_5%
R11333_0402_5%

R24033_0402_5%

R26933_0402_5%

AC97_BITCLK

AC97_SYNC

R25333_0402_5%

AC97_RST#

R63033_0402_5%

AC97_SDIN0
AC97_SDIN1

AC97_SDOUT

R24533_0402_5%
R24733_0402_5%

IDE_LED#

SATA_RXN0_C
SATA_RXP0_C
SATA_TXN0_C
SATA_TXP0_C

CLK_PCIE_SATA#
CLK_PCIE_SATA

R620

24.9_0402_1%

PD_IORDY

R6094.7K_0402_5%

PD_IRQ

R6088.2K_0402_5%

PD_DACK#
PD_IOW#
PD_IOR#

7/6

R430

100_0402_5%

D32

DAN202U_SC70

BATT1

CR2025 RTC BATTERY

U10A

ICH7M_B0_BGA652

W =20mils

L

ZZZ

PCB- MB

R TC

L AN

I DE

R423

1K_0402_5%

L PCC PU

AC-97/AZALIA

SATA

RTC2RTC1

PLT_RST#7,19,21,23,25,27,32,33

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3

LPC_DRQ#0
LPC_DRQ#1

LPC_FRAME#

GATEA20
H_A20M#

H_CPUSLP_R#
DPRSLP#

R58 0_0402_5%

H_DPSLP#

R54 56_0402_5%

H_FERR#
H_PWRGOOD
H_IGNNE#

FWH_INIT#
H_INIT#
H_INTR

R60 10K_0402_5%

KB_RST#
H_SMI#

H_NMI

R598

0_0402_5%

THRMTRIP_ICH#

PD_A0
PD_A1
PD_A2

PD_CS#1
PD_CS#3

PD_D0
PD_D1
PD_D2
PD_D3
PD_D4
PD_D5
PD_D6
PD_D7
PD_D8
PD_D9
PD_D10
PD_D11
PD_D12
PD_D13
PD_D14
PD_D15

PD_DREQ

JP28

E&T_7651

SN74LVC08APW_TSSOP14

-+

U11B

LPC_AD[0..3] 27,31,32,33

LPC_DRQ#0 31
LPC_DRQ#1

LPC_FRAME# 27,31,32,33

R61 10K_0402_5%

GATEA20 33
H_A20M# 4

T14PAD

H_FERR# 4
H_PWRGOOD 4
H_IGNNE# 4

9/8

T26PAD

H_INIT# 4
H_INTR 4

KB_RST# 33
H_SMI# 4

H_NMI 4

H_STPCLK#

R591

24.9_0402_1%

R1031 must be placed close to U26.AF26

L

within 2" and R1030 must be placed close
to R1031 within 2".

H_STPCLK#

IDE_LED#32

+3VS

C147

0.1U_0402_16V4Z

R88 33_0402_5%

+3VS

IDE_LED#

+3VS

H_DPRSTP# 4,45
H_DPSLP# 4

+VCCP

+VCCP

R592
56_0402_5%

H_STPCLK# 4

D35

CH751H-40_SC76

H_THERMTRIP# 4,7

10K_0402_5%

+5VS

ODD_RST#

PLT_RST_B# 27,31

+5VS

C148
10U_0805_10V4Z

ODD_RST#
PD_D7
PD_D6
PD_D5
PD_D4
PD_D3

11/18

8/24

PD_D2
PD_D1
PD_D0

PD_IOW#
PD_IORDY
PD_IRQ
PD_A1
PD_A0
PD_CS#1
IDE_DSP#

+5VS
+5VS

SEC_CSEL

+5VS

C98
10U_0805_10V4Z

+5VS

R512

R499 4.7K_0402_5%@
R503 470_0402_5%

SATA CONN

JP20

SATA_TXP0
SATA_TXN0

SATA_RXN0
SATA_RXP0

+5VS

OCTEK_SAT-22DN1G_NR

C153

0.1U_0402_16V4Z

Place component's closely IDE CONN. JP45

L

C151

0.1U_0402_16V4Z

ODD CONN

JP13

PD_D8
PD_D9
PD_D10
PD_D11
PD_D12
PD_D13
PD_D14
PD_D15
PD_DREQ
PD_IOR#

PD_DACK#
PDIAG#

PD_A2
PD_CS#3

W=80mils

C104 0.1U_0402_16V4Z

OCTEK_CDR-50DU1

C100

0.1U_0402_16V4Z

Place component's closely IDE CONN. JP37

L

C101

0.1U_0402_16V4Z

C156

0.1U_0402_16V4Z

R509 100K_0402_5%

+5VS
+5VS
+5VS

C102

0.1U_0402_16V4Z

+5VS

Near Device(JP45) side.

L

5

Security Classification

Issued Date

THIS SHEET OF ENGINEERI NG DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATIO N. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUT HORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

4

MAY BE USED BY OR DIS CLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/03/10 2006/03/10

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

2

Date: Sheet of

Compal Electronics, Inc.

ICH7-M(2/4)

LA-2821P

20 52Saturday, January 14, 2006

1

1.0

5

4

3

2

1

Place closely pin B2 Place closely pin AC1

+3VALW

R593

R595

D D

ICH_SMBDATA4,13,14,15,18,25,27

ICH_SMBCLK4,13,14,15,18,25,27

+3VS

10K_0402_5%@

R68

R63

C C

B B

A A

R73

+3VALW

R589

R596

R594

R606

VGA_RST#18

THERM_SCI#

10K_0402_5%

SIRQ

8.2K_0402_5%

PM_CLKRUN#

10K_0402_5%

LINKALERT#

10K_0402_5%

XDP_DBRESET#

10K_0402_5%

OCP#

10K_0402_5%

LID_SW#

+3VALW +3VS

11/21

R78

10K_0402_5%

PREP#26,35

L

PREP#

CH751H-40_SC76

+3VS

+3VALW

R97

10K_0402_5%SPI@

R110

10K_0402_5%SPI@

R111

10K_0402_5%SPI@

R1284,R1285 and R1286 should
be placed close to U26.

5

D14

10K_0402_5%

+3VS

R79

2.2K_0402_5%@

ICH_SMBCLK ICH_SMB_CLK

LOM_PCIE_WAKE#25

PCIE_WAKE#27

R76
10K_0402_5%

ISO_PREP#

M24_RST#
PLT_RST#

U11C
SN74LVC08APW_TSSOP14

SPI_CS#

SPI_SI

SPI_SO

10K_0402_5%

2N7002_SOT23@
Q11

D

S

G

+3VALW

BSS138_SOT23

V_3P3_LAN

PM_POK7,33

MXM_CD1#18,47

ICH_SMBCLK
ICH_SMBDATA

ICH_SMB_DATAICH_SMBDATA

Q14

2N7002_SOT23@

+3VS

1/4

R604

1K_0402_5%

S

Q8

R603
0_0402_5%

R64 0_0402_5%
R59 0_0402_5%@

PCIE_RXN125

PCIE_RXP125
PCIE_TXN125
PCIE_TXP125

PCIE_RXN227

PCIE_RXP227
PCIE_TXN227
PCIE_TXP227

PCIE_RXN435

PCIE_RXP435
PCIE_TXN435
PCIE_TXP435

R84

2.2K_0402_5%@

D

S

G

VGATE_INTEL7,45

PLT_RST# 7,19,20,23,25,27,32,33

D

G

MXM_CD1#

+3VALW

4

2.2K_0402_5%

R82

0_0402_5%
0_0402_5%

R77

11/14

M24_RST#

+3VALW

R600

R1292/R1293 should be placed

L

less than 100 mils from U26.

SPI_CLK32
SPI_CS#32

SPI_SI32

SPI_SO32

R639 0_0402_5%@

D

Q109

G

1/4

+3VALW

XDP_DBRESET#4

PM_BMBUSY#7

H_STP_PCI#15

H_STP_CPU#15

R586

PM_CLKRUN#23,31,32,33

THERM_SCI#4

RUNSCI_EC#33

ISO_PREP#35

10K_0402_5%

SPI_CLK
SPI_CS#

SPI_SI
SPI_SO

S

2N7002_SOT23@

+3VALW

R75

R587

8.2K_0402_5%

SB_SPKR28
LPC_PD#32,33

OCP#4,47

T27PAD
T49PAD

0_0402_5%

T31PAD
T32PAD

SIRQ23,31,32,33

LP_EN#25

PWROK_ICH7

C1330.1U_0402_16V4Z
C1340.1U_0402_16V4Z

C1270.1U_0603_16V7K
C1280.1U_0603_16V7K

11/22

C1290.1U_0402_16V4Z
C1300.1U_0402_16V4Z

R98

R99

USB_OC#1
USB_OC#229
USB_OC#329
USB_OC#430
USB_OC#530

MXM_CD0#18

R81

2.2K_0402_5%

MXM_CD1#_R

R213,R233 change from 2.2Kohm to

L

10Kohm when Q23,Q24,R206,R204 stuffed.

ICH_SMB_CLK
ICH_SMB_DATA
LINKALERT#
ICH_SMLINK0
ICH_SMLINK1

ICH_RI#
SB_SPKR

LPC_PD#
XDP_DBRESET#

PM_BMBUSY#
OCP#

H_STP_PCI#
H_STP_CPU#

GPIO26_SB
GPIO27_SB
GPIO28_SB
PM_CLKRUN#
FWH_WP#

FWH_TBL#
ICH_PCIE_WAKE#

SIRQ
THERM_SCI#

PWROK_ICH7

RUNSCI_EC#
ISO_PREP#
LP_EN#

11/14

PCIE_RXN1
PCIE_RXP1
PCIE_C_TXN1
PCIE_C_TXP1

PCIE_RXN2
PCIE_RXP2
PCIE_C_TXN2
PCIE_C_TXP2

PCIE_RXN4
PCIE_RXP4
PCIE_C_TXN4
PCIE_C_TXP4

47_0402_5%SPI@

47_0402_5%SPI@

USB_OC#0
USB_OC#1
USB_OC#2
USB_OC#3
USB_OC#4
USB_OC#5
MXM_CD0#

Security Classification

Issued Date

THIS SHEET OF ENGINEERI NG DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATIO N. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUT HORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DIS CLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

U10C

ICH7M_B0_BGA652

MXM_THERM#18

U10D

ICH7M_B0_BGA652

3

SMB

SATA

GPIO

S YS

Clocks

GPIO

POWER MGT

GPIO

Need update symbol

THERM_SCI#

R67

0_0402_5%

PCI-EXPRESS

DIRECT MEDIA INTERFACE

S PI

U SB

2005/03/10 2006/03/10

Compal Secret Data

DMI_RXN0
DMI_RXP0
DMI_TXN0
DMI_TXP0

DMI_RXN1
DMI_RXP1
DMI_TXN1
DMI_TXP1

DMI_RXN2
DMI_RXP2
DMI_TXN2
DMI_TXP2

DMI_RXN3
DMI_RXP3
DMI_TXN3
DMI_TXP3

CLK_PCIE_ICH#
CLK_PCIE_ICH

DMI_IRCOMP
USB20_N0

USB20_P0
USB20_N1
USB20_P1
USB20_N2
USB20_P2
USB20_N3
USB20_P3
USB20_N4
USB20_P4
USB20_N5
USB20_P5
USB20_N6
USB20_P6
USB20_N7
USB20_P7

USBRBIAS

Deciphered Date

R72

100_0402_5%

CLK_14M_ICH
CLK_48M_ICH

ICH_SUSCLK

SLP_S3#
SLP_S4#
SLP_S5#

PM_POK
DPRSLPVR
ICH_LOW_BAT#
ON/OFFBTN#
PLT_RST#
PM_RSMRST#

R634 10K_0402_5%

GPIO9_SB
CB_IN#
GPIO12_SB
LID_SW#

LANLINK_STATUS#_SB

GPIO15_SB
XMIT_OFF
BT_OFF
NPCI_RST#

R605

GPIO39_SB

DMI_RXN0 7
DMI_RXP0 7
DMI_TXN0 7
DMI_TXP0 7

DMI_RXN1 7
DMI_RXP1 7
DMI_TXN1 7
DMI_TXP1 7

DMI_RXN2 7
DMI_RXP2 7
DMI_TXN2 7
DMI_TXP2 7

DMI_RXN3 7
DMI_RXP3 7
DMI_TXN3 7
DMI_TXP3 7

CLK_PCIE_ICH# 15
CLK_PCIE_ICH 15

R588 24.9_0402_1%

USB20_N0 30
USB20_P0 30
USB20_N1 32
USB20_P1 32
USB20_N2 29
USB20_P2 29
USB20_N3 29
USB20_P3 29
USB20_N4 30
USB20_P4 30
USB20_N5 30
USB20_P5 30
USB20_N6 35
USB20_P6 35
USB20_N7 35
USB20_P7 35

R641 22.6_0402_1%

Within 500 mils

2

HDD_STP 32

CLK_14M_ICH 15
CLK_48M_ICH 15

T16 PAD

SLP_S3# 18,25,28,29,33,35,36,40,43,44
SLP_S4# 44
SLP_S5# 36,44

PM_POK 7,33
DPRSLPVR 7,45

ON/OFFBTN# 34

PM_RSMRST# 33

T28 PAD
T30 PAD

LID_SW# 17,34
LANLINK_STATUS#_SB 25

T25 PAD

XMIT_OFF 27
BT_OFF 30
NPCI_RST# 31,33

0_0402_5%@

T29 PAD

R1015 need be removed when ICH7M ES2 samples used,
but need be stuffed when ICH7M ES1 samples used.

L

Within 500 mils

+1.5VS

CLK_48M_ICH

R637

10_0402_5%@

C541

4.7P_0402_50V8C@

R601
R633
10K_0402_5%

DOCK_ID 35

Title

Size Document Number Rev

Date: Sheet of

8.2K_0402_5%

D13

CH751H-40_SC76

DPRSLPVR

R602 0_0402_5%@

J16

PAD-SHORT 2x2m

RP20

USB_OC#3
USB_OC#0
USB_OC#1
USB_OC#2

10K_1206_8P4R_5%

R638

10K_0402_5%

USB_OC#4

R644

10K_0402_5%

USB_OC#5

R642

10K_0402_5%

MXM_CD0#

R643

22K_0402_5%

MXM_CD1#_R

1/4

Compal Electronics, Inc.

ICH7-M(3/4)

LA-2821P

CLK_14M_ICH

R640

10_0402_5%@

C542

4.7P_0402_50V8C@

+3VALW

LOW_BAT# 33

R74

10K_0402_5%

R599

100K_0402_5%@

LOM_LOW_PWR 25

CABLE_DETECT 25,26

+3VALW

21 52Saturday, January 14, 2006

1

+3VL

1.0

5

4

3

2

1

ICH_V5REF_RUN

C132

220U 6.3V M

9/15

C503

22U_0805_6.3V

+3VS

+1.5VS

C543

0.1U_0402_16V4Z

+1.5VS

+

C506

0.1U_0402_16V4Z

+1.5VS_DMIPLL+1.5VS_DMIPLLR

C504

0.01U_0402_16V7K

C521

0.1U_0402_16V4Z

+3VALW

+3VS

D D

100_0402_5%

10_0402_5%

C C

B B

A A

R614

R90

+3VS+5VS

D15
CH751H-40_SC76

C517

0.1U_0402_16V4Z

+3VALW+5VALW

D17
CH751H-40_SC76

C532

0.1U_0402_16V4Z

ICH_V5REF_RUN

ICH_V5REF_SUS

+1.5VS

C515

0.1U_0402_16V4Z

Place closely pin AG28 within 100mlis.

R584

0.5_0805_1%

+3VALW

0.1U_0402_16V4Z

+1.5VS

C537

R585

0_0805_5%

C527

0.1U_0402_16V4Z

ICH_V5REF_SUS

0.1U_0402_16V4Z

C505

C507

0.1U_0402_16V4Z

Place closely pin
D 28,T28,AD28.

+3VS

C508

0.1U_0402_16V4Z

+1.5VS

0.1U_0402_16V4Z

+1.5VS_DMIPLL

C534

Place closely pin AG5.

+1.5VS

C146

1U_0603_10V4Z

Place closely pin AG9.

T18 PAD
T17 PAD

J18

PAD-SHORT 2x2m

J17

PAD-No SHORT 2x2m

ICH_AA2
ICH_Y7

ICH_SUSLAN

U10F

ICH7M_B0_BGA652

C540

0.1U_0402_16V4Z

+VCCP

0.1U_0402_16V4Z

C519

1U_0603_10V4Z

C533

0.1U_0402_16V4Z

C529

0.1U_0402_16V4Z

C530 0.1U_0402_16V4Z

ICH_K7
ICH_C28

ICH_G20

C131

C513

220U 6.3V M

C511

0.1U_0402_16V4Z

C525

C522

0.1U_0402_16V4Z

0.1U_0402_16V4Z

+1.5VS

+1.5VS

C516

0.1U_0402_16V4Z

+

9/15

+3VS

+3VS

C535

0.1U_0402_16V4Z

C528

0.1U_0402_16V4Z

C538

0.1U_0402_16V4Z

T19PAD
T13PAD

T15PAD

+VCCP

+3VS

+3VALW

+3VALW

C523

0.1U_0402_16V4Z

C512

0.1U_0402_16V4Z

C520

22U_0805_6.3V

C536

0.1U_0402_16V4Z

C518

0.1U_0402_16V4Z

C531

0.1U_0402_16V4Z

U10E

+3VS

+RTCVCC

ICH7M_B0_BGA652

Security Classification

Issued Date

THIS SHEET OF ENGINEERI NG DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATIO N. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUT HORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DIS CLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/03/10 2006/03/10

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

2

Date: Sheet of

Compal Electronics, Inc.

ICH7-M(4/4)

LA-2821P

22 52Saturday, January 14, 2006

1

1.0

A

+3VS_CBPLL

XTPBIAS0
XTPA0+
XTPA0­XTPB0+
XTPB0-

XTPBIAS1

XTPB1+
XTPB1-

+3VS

X_OUT
X_IN

MC_PWRON#
PWR_CTRL_1/SM_R/B#

SD_CD#
MS_CD#
SM_CD#

R175

MSBS_SDCMD_SMWE#
MSD3_SDD3_SMD3
MSD2_SDD2_SMD2
MSD1_SDD1_SMD1
MSD0_SDD0_SMD0

SDCLK_SMRE#
SDCMD_SMALE
SDD0_SMD4
SDD1_SMD5
SDD2_SMD6
SDD3_SMD7
SDWP#_SMCE#

SMCLE
SC_CD#

R117

0_0402_5%

SC_RST
SC_DATA

SC_OC#
SM_PHYS_WP#/SC_FCB

SM_RB#/SC_RFU

10_0402_5%@

15P_0402_50V8J@

R141
R142

R140

R152

R159
R182

+3VS

R229

0_0805_5%

R228 6.34K_0402_1%

R230

4.7K_0402_5%@

22_0402_5%

SC_CLK_R

R1430_0402_5%

SC_RFU

0_0402_5%
0_0402_5%@

SC_FCB

0_0402_5%

SM_PHYS_WP#

0_0402_5%@

XD_CD#/SM_PHYS_WP#

0_0402_5%7612@

SM_CD#XD_CD#

0_0402_5%@

PCI_AD[0..31]19

PCI_CBE#[0..3]19

1 1

C242

10P_0402_50V8J

2 2

3 3

4 4

C241

10P_0402_50V8J

PCI_AD[0..31]
PCI_ CBE#[0..3]

X_IN

R237

1M_0402_5%@

+3VS

9/10

9/10

Y2

X_OUT

24.576MHZ_16P_1BG24576CK1A

MSCLK_SDCLK_SMELWP#

SC_CD#24

SC_CLK24

SC_RST24

+SC_PWR

SC_DATA24

R129 10K_0402_5%@
R130 10K_0402_5%@

SM_RB#/SC_RFU

SM_PHYS_WP#/SC_FCB

A

SC_CLK

CLK_PCI_PCM

R149

C168

B

C227

C219

1U_0603_10V4Z

10U_0805_10V4Z

U16B

R131

R153

B

C230

0.01U_0402_16V7K

0_0402_5%7612@

0_0402_5%7612@

C

+3VS_CBVCCP

0.1U_0402_16V4Z
C174

C2341U_0603_10V4Z

C169 1U_0603_10V4Z

PCI7612/7412

PCI7612ZHK_PBGA257

+VDDPLL

PWR_CTRL_1/SM_R/B#SM_RB#

SC_RFU 24

SC_FCB 24

XD_CD#/SM_PHYS_WP# 24

+3VS

R173

0_0805_5%

C185

0.1U_0402_16V4Z

L12

CHB1608U301_0603

C232 0.1U_0402_16V4Z

Keep +VDD_PLL33/+VDDPLL33/+VDD_PLL

L

/+VDDPLL at least 10 mils

PCI_AD31
PCI_AD30
PCI_AD29
PCI_AD28
PCI_AD27
PCI_AD26
PCI_AD25
PCI_AD24
PCI_AD23
PCI_AD22
PCI_AD21
PCI_AD20
PCI_AD19
PCI_AD18
PCI_AD17
PCI_AD16
PCI_AD15
PCI_AD14
PCI_AD13
PCI_AD12
PCI_AD11
PCI_AD10
PCI_AD9
PCI_AD8
PCI_AD7
PCI_AD6
PCI_AD5
PCI_AD4
PCI_AD3
PCI_AD2
PCI_AD1
PCI_AD0

PCI_CBE#3
PCI_CBE#2
PCI_CBE#1
PCI_CBE#0

R161

CLK_PCI_PCM
PRST#
GRST#
CB_PME#

43K_0402_5%

PCM_SPK

FM_LED#

PCM_SPK

Security Classification

Issued Date

THIS SHEET OF ENGINEERI NG DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATIO N. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUT HORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DIS CLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

+VDDPLL33+VDD_PLL33
+VDDPLL+VDD_PLL

100_0402_5%

R151

C

+3VS

10K_0402_5%@

CB_PME#

PCI_AD22

0_0402_5%
R150
R136

0_0402_5%@

+3VS

R231

43K_0402_5%

2005/03/10 2006/03/10

PAD-No SHORT 2x2m

+3VS

R148

Q20

2N7002_SOT23@

0.1U_0402_16V4Z

PCI_PAR 19
PCI_FRAME# 19
PCI_TRDY# 19

PCI_IRDY# 19

PCI_STOP# 19

PCI_DEVSEL# 19
PCI_PERR# 19

PCI_SERR# 19,33

PCI_REQ2# 19
PCI_GNT2# 19

CLK_PCI_PCM 15
PCI_RST# 19,24
PLT_RST# 7,19,20,21,25,27,32,33

PCM_SPK 28

R1450_0402_5%

PCI_PIRQC# 19

R1330_0402_5%

PCI_PIRQD# 19

R1320_0402_5%

PCI_PIRQG# 19

R1440_0402_5%

SIRQ 21,31,32,33

R1370_0402_5%

PCI_PIRQE# 19

PM_CLKRUN# 21,31,32,33

R146220_0402_5%
R134220_0402_5%

R135220_0402_5%

MC_PWRON#

+VCC_MS +VCC_SD

J6

100K_0402_5%

SDWP#_SMCE#
SM_RB#
MSBS_SDCMD_SMWE#
SDCLK_SMRE#

G

D

S

MSCLK_SDCLK_SMELWP#

R116

MSBS_SDCMD_SMWE#

33_0402_5%@

+VCC_SM_XD

C164

U12

TPS2061IDGN_MSOP8~N
C152 10U_0805_10V4Z
C154 0.01U_0402_16V7K

Compal Secret Data

Deciphered Date

D

J7

PAD-SHORT 2x2m

22K_0402_5%

R125

R114

PCI_PME# 19

MSD0_SDD0_SMD0
MSD1_SDD1_SMD1
MSD2_SDD2_SMD2
MSD3_SDD3_SMD3
SDD0_SMD4
SDD1_SMD5
SDD2_SMD6
SDD3_SMD7

SM_PHYS_WP#
SDCMD_SMALE

SM_CD#
SM_RB#

SDCLK_SMRE#
SDWP#_SMCE#
SM_CD#

SMCLE

R116,R142,R182

L

Stuff when 7611 used

R124
0_0402_5%

D

100K_0402_5%

R115

R126

100K_0402_5%

JP24

TAITW_R007-010-N3

GRST#PRST#

+3VS+VCC_MS+3VS

E

+VCC_MS +VCC_SD +VCC_MS +VCC_SM_XD

SI2301BDS_SOT23
Q21

S

D

G

C165

10U_0805_10V4Z

9/6

+3VS +3VS

R164

G

Q30

G

S

D

S

D21 RB751V_SOD323@
D22 RB751V_SOD323@

D

Q22
2N7002_SOT23

10K_0402_5%

MC_PWRON#

FM_LED#

2N7002_SOT23@

5 IN 1 CONN

56.2_0603_1%

R195

XTPBIAS0
XTPB0­XTPB0+
XTPA0­XTPA0+

R187

56.2_0603_1%

C189

270P_0603_50V8J

L

L

R91
10K_0402_5%

XTPBIAS1
XTPB1+
XTPB1-

R193

1K_0402_5%

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

TI PCI7612 PCI/CardReader

LA-2821P

SI2301BDS_SOT23
Q28

S

1/13

G

R128

4.7K_0402_5%

+3VS

R127
10K_0402_5%

SD_CD#MS_CD#

G

D

S

Q27
2N7002_SOT23

SD_CD#
SM_CD#

SD_DAT3
SD_DAT2
SD_DAT1
SD_DAT0
SDWP#_SMCE#

Place the parts close to JP41

SD_CD#

MSD0_SDD0_SMD0
MSD1_SDD1_SMD1
MSD2_SDD2_SMD2
MSD3_SDD3_SMD3
MSCLK_SDCLK_SMELWP#
MS_CD#
MSBS_SDCMD_SMWE#

XD_CD#

R201

56.2_0603_1%

C207
1U_0603_10V4Z

R183

56.2_0603_1%

R186

5.1K_0603_1%

CLOSE TO CHIP

CLOSE TO CHIP

1K_0402_5%

R200

C212
1U_0603_10V4Z

E

D

12/8

R154

C178

47K_0402_5%

10U_0805_10V4Z

R165
10K_0402_5%

MSD3_SDD3_SMD3

R1220_0402_5%

MSD2_SDD2_SMD2

R1230_0402_5%

MSD1_SDD1_SMD1

R1190_0402_5%

MSD0_SDD0_SMD0

R1200_0402_5%

MSBS_SDCMD_SMWE#

R1210_0402_5%

MSCLK_SDCLK_SMELWP#

R1180_0402_5%

+VCC_SD

+VCC_MS+VCC_SM_XD

12/15

JP17

AMP_440168-2

23 52Saturday, January 14, 2006

L

1.0

A

C195

0.1U_0402_16V4Z

0.1U_0402_16V4Z

S1_D10
S1_D9
S1_D1
S1_D8
S1_D0
S1_A0
S1_A1
S1_A2
S1_A3
S1_A4
S1_A5
S1_A6
S1_A25
S1_A7
S1_A24
S1_A17
S1_IOWR#
S1_A9
S1_IORD#
S1_A11
S1_OE#
S1_CE2#
S1_A10
S1_D15
S1_D7
S1_D13
S1_D6
S1_D12
S1_D5
S1_D11
S1_D4
S1_D3

S1_REG#
S1_A12
S1_A8
S1_CE1#

S1_A13
S1_A23
S1_A15
S1_A20
S1_A21
S1_A19
S1_A14
S1_WAIT#
S1_INPACK#
S1_WE#
S1_BVD1
S1_WP
S1_A16S1_A16_C
S1_RDY#
CPS

CLK_48M_CB

S1_A22
S1_BVD2
S1_RST

S1_CD1#
S1_CD2#
S1_VS1
S1_VS2

C187

C179

0.1U_0402_16V4Z

C170

0.1U_0402_16V4Z

1 1

2 2

R227

+3VS

R189

4.7K_0402_5%

CLK_48M_CB

R147

3 3

10_0402_5%@

C166

10P_0402_50V8J@

4 4

33_0402_5%

CLK_48M_CB15

CPS

C182

0.1U_0402_16V4Z

0.1U_0402_16V4Z
U16A

C203

C229

0.1U_0402_16V4Z

B

C235

10U_0805_10V4Z

PCI7612/7412

C

+S1_VCC+3VS

C228

C202

0.1U_0402_16V4Z

0.1U_0402_16V4Z

Near to PCMCIA slot.

+S1_VCC

C211
10U_0805_10V4Z

+S1_VPP

C201
10U_0805_10V4Z

S1_CD1#

S1_CD2#

S1_D2
S1_A18
S1_D14

43K_0402_5%

R160

43K_0402_5%@

R166

XD_CD#/SM_PHYS_WP#

CB_DAT
CB_CLK
CB_LATCH

PCI7612ZHK_PBGA257

+SC_PWR

R168

R169

22K_0402_5%@

22K_0402_5%@

100P_0402_50V8J@

SC_CLK SC_DATA SC_RST

C180

56P_0402_50V8J@

+SC_PWR

R208

10K_0402_5%@

C199

C210

0.1U_0402_16V4Z

C200

0.1U_0402_16V4Z

C231

100P_0402_50V8J

C197

100P_0402_50V8J

+3VS

XD_CD#/SM_PHYS_WP# 23

CB_CLK 33

C218

0.1U_0402_16V4Z

R190

22K_0402_5%@

470P_0402_50V7K@

C184

R176

22K_0402_5%@

PCI_RST#19,23

+S1_VPP

+S1_VCC

+S1_VPP

+SC_PWR

+S1_VCC

S1_CD2#
S1_WP
S1_D10
S1_D2
S1_D9
S1_D1

S1_D8
S1_D0
S1_BVD1
S1_A0
S1_BVD2
S1_A1
S1_REG#

S1_A2
S1_INPACK#
S1_A3
S1_WAIT#
S1_A4
S1_RST
S1_A5

S1_VS2
S1_A6
S1_A25
S1_A7
S1_A24
S1_A12
S1_A23

S1_A15
S1_A22
S1_A16_C

S1_RDY#
S1_A21
S1_WE#

S1_A20
S1_A14
S1_A19
S1_A13
S1_A18
S1_A8
S1_A17

S1_A9
S1_IOWR#
S1_A11
S1_IORD#
S1_OE#
S1_VS1
S1_A10

S1_CE2#
S1_CE1#
S1_D15
S1_D7
S1_D14
S1_D6
S1_D13

S1_D5
S1_D12
S1_D4
S1_D11
S1_D3
S1_CD1#

D

CB_DAT
CB_CLK
CB_LATCH
PCI_RST#

U19

TPS2224ADBR_HTSSOP24

9/8

JP23

TYCO_1123088-1_LT

+5VS

C258

SC_DATA

SC_RST

SC_CLK

SC_CD#
SC_FCB

SC_RFU

+3VS

C233

0.1U_0402_16V4Z

0.1U_0402_16V4Z

SC_DATA 23

+SC_PWR

SC_RST 23

SC_CLK 23

SC_CD# 23
SC_FCB 23

SC_RFU 23

E

Place the parts close to JP9

L

Security Classification

Issued Date

THIS SHEET OF ENGINEERI NG DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATIO N. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUT HORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DIS CLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2005/03/10 2006/03/10

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

D

Date: Sheet of

Compal Electronics, Inc.

TI PCI7612 CB/SmartCard

LA-2821P

24 52Saturday, January 14, 2006

E

1.0

5

4

3

2

1

PLT_RST#7,19,20,21,23,27,32,33

SI2301BDS_SOT23

S

Q57

G

V_3P3_LAN

R366 1K_0402_5%@
R337 1K_0402_5%@

D D

9/7

R391

10K_0402_5%

5751_GPIO1
ICH_LAN_SMBCLK

ICH_LAN_SMBDATA
5751_EECLK

5751_EEDAT

ICH_LAN_SMBCLK
ICH_LAN_SMBDATA

U25A

11/23

V_3P3_LAN

R663

G

10K_0402_5%

LANLINK_STATUS#

S

LANLINK_STATUS#

LAN_ACT#

R679

10K_0402_5%

XTALO

XTALI

C334
27P_0402_50V8J

R404

5751_GPIO1
5751_EECLK
5751_EEDAT

2N7002_SOT23@
Q60

D

D

S

Q65

G

V_3P3_LAN

R335

4.7K_0402_5%

R405

1K_0402_5%

1K_0402_5%

ICH_LAN_SMBDATA

ICH_LAN_SMBCLKICH_SMBCLK

2N7002_SOT23@

+5VS

BCM5753KFBG C0_FPBGA196~D

V_3P3_LAN

R406

1K_0402_5%

V_3P3_LAN

+3VALW

10K_0402_5%

C C

LANLINK_STATUS#_SB21

B B

A A

R678

R673

10K_0402_5%

Q78 2N7002_SOT23

LANLINK_STATUS#26,35

LAN_ACT#26,35

V_3P3_LAN

R347 200_0402_1%

Y4

25MHZ_16P_XSL025000FK1H

C331
27P_0402_50V8J

C376

0.1U_0402_16V4Z

U28

AT24C256_SO8

+3VS

R334

2.2K_0402_5%@

ICH_SMBDATA

5

0_0402_5%@

R361

S

D

R680

2.2K_0402_5%@

G

5/16

R367 0_0402_5%
R336 0_0402_5%

BCM5753

Media

Misc

Power

Control

Control

Regulator

Hot Plug

Support

PCI-ET EST

LED

Clock

Bias

Layout Notice : No high
speed signal should be
r outed near RDAC or on
adjacent layer to RDAC

11/21

NIC_PD_N

4

ICH_SMBCLK
ICH_SMBDATA

LAN_TX3+
LAN_TX3­LAN_TX2+
LAN_TX2­LAN_TX1+
LAN_TX1­LAN_TX0+
LAN_TX0-

LOM_LOW_PWR

REGSUP12
VAUX_1.2_CTL

PCIE_C_RXN1

0.1U_0402_16V4Z

PCIE_C_RXP1

0.1U_0402_16V4Z

LOM_WAKE#
CLK_PCIE_LOM#
CLK_PCIE_LOM

R328 4.7K_0402_5%

PLT_RST#_LAN

11/15

11/18

R326

R373

1.2K_0402_1%

11/18

D34 1N4148_SOD80

R662 121K_0402_1%

C550

0.1U_0402_16V7K

ICH_SMBCLK 4,13,14,15,18,21,27
ICH_SMBDATA 4,13,14,15,18,21,27

LAN_TX3+ 26
LAN_TX3- 26
LAN_TX2+ 26
LAN_TX2- 26
LAN_TX1+ 26
LAN_TX1- 26
LAN_TX0+ 26
LAN_TX0- 26

R407

4.7K_0402_5%

9/13

V_1P2_LAN
V_2P5_LAN
V_3P3_LAN

C342
C344

V_3P3_LAN

R646
10K_0402_5%

4.7K_0402_5%@

V_3P3_LAN +3VS

R660

0_0402_5%@

PCIE_RXN1 21

PCIE_RXP1 21
PCIE_TXN1 21
PCIE_TXP1 21

11/18

R659

0_0402_5%

R661

U38
SN74LVC1G17DBVR_SOT23-5

Security Classification

Issued Date

THIS SHEET OF ENGINEERI NG DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATIO N. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUT HORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DIS CLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

0_0402_5%@

9/7

PLT_RST#_LAN

NIC_PD26

CLK_PCIE_LOM# 15
CLK_PCIE_LOM 15

R364

4.7K_0402_5%

0_0402_5%

3

R330

11/14

220K_0402_5%

R329

D

11/21

C544

0.1U_0402_16V7K@

NIC_PD

ADP_PRES18,33,40,41,42,47

2N7002_SOT23

SLP_S3#18,21,28,29,33,35,36,40,43,44

10K_0402_5%

LOM_WAKE#

R658

0_0402_5%@

NIC_PD

CLKREQA# 15,18

2005/03/10 2006/03/10

Compal Secret Data

+3VALW

D36

RB751V_SOD323@

D

R21

0_0402_5%@

S

D

Q5

G

S

G

V_3P3_LAN

R345

D

Q107
BSS84_SOT23@

R654 0_0402_5%

NIC_PD_N

R656

100K_0402_5%@

D

Q108

G

BSS84_SOT23@

S

R655 0_0402_5%@
R657 0_0402_5%@

NIC_PD#

R648 10K_0402_5%@

D

Q76

G

2N7002_SOT23@

S

LOM_LOW_PWR21

CKT Notice : CABLE IN, CABLE_DETECT=0

Deciphered Date

J10

PAD-NO SHORT 2x2m

S

D

Q2

SI2301BDS_SOT23

R19

47K_0402_5%

LP_EN#

G

L

4.7U_0805_10V4Z

R20

4.7K_0402_5%

Q3

G

2N7002_SOT23

D

Q4
2N7002_SOT23

S

11/21

NIC_PD

G

S

LOM_PCIE_WAKE# 21

+3VS V_3P3_LAN

11/21

LOM_LOW_PWR

SN74LVC1G17DBVR_SOT23-5@

CABLE OUT, CABLE_DETECT=1

CABLE_DETECT21,26

2

CABLE_DETECT

0.1U_0402_16V4Z

Layout Notice : Place as close
chip as possible.

V_3P3_LAN

C358

C357

C308

C366

0.1U_0402_16V4Z

4.7U_0805_10V4Z

Must having maximized
copper under pin 2 & 4 of Q13

V_3P3_LAN

REGSUP12

C304

V_3P3_LAN

C379

0.1U_0402_16V4Z@

U27

+3VALW

R425
10K_0402_5%

C400

Title

Size Document Number Rev

Date: Sheet of

C307

0.1U_0402_16V4Z

C303

0.1U_0402_16V4Z

VAUX_1.2_CTL

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

BCP69_SOT223
Q54

C309

0.1U_0402_16V4Z

V_3P3_LAN

C306

4.7U_0805_10V4Z

L

L

Place close U6 pin M13

V_2P5_LAN

10U_1206_6.3V6M@

C352

C364

Place close U6 pin N13

11/21

R416

100K_0402_5%@

C396

0.1U_0402_16V4Z@

R426

0_0402_5%@

D

G

Q66

S

2N7002_SOT23

11/18

R667

10K_0402_5%@

R424

10K_0402_5%

R668

0_0402_5%

LP_EN#

Compal Electronics, Inc.

BCM5753M

LA-2821P

1

V_1P2_LAN

C299

0.1U_0402_16V4Z

+

C300
10U_0805_6.3V6M

1/9

C372
100U_B_6.3VM

V_3P3_LAN

+3VS

NIC_PD_N

LP_EN# 21

25 52Saturday, January 14, 2006

1.0

5

T22

V_2P5_LAN

D D

C C

R672

0_0603_5%

C348

0.1U_0402_16V7K

11/22

C345

0.1U_0402_16V7K

C346

0.1U_0402_16V7K

C347

0.1U_0402_16V7K

LAN_TX0-

LAN_TX0+
TRM_CT
LAN_TX1-

LAN_TX1+
TRM_CT
LAN_TX2-

LAN_TX2+
TRM_CT
LAN_TX3-

LAN_TX3+
TRM_CT

24HST1041A-3B_24P

C3630.1U_0402_16V4Z
C3620.1U_0402_16V4Z
C3610.1U_0402_16V4Z
C3600.1U_0402_16V4Z

Layout Notice : Place
termin ation as close as
BCM5753M as possible

1:1

1:1

1:1

1:1

R389 49.9_0402_1%
R388 49.9_0402_1%
R387 49.9_0402_1%
R386 49.9_0402_1%
R385 49.9_0402_1%
R384 49.9_0402_1%
R383 49.9_0402_1%
R382 49.9_0402_1%

To RJ-45 CONN.

V_3P3_LAN_LED

CABLE_DETECT21,25

LAN_ACT#
LANLINK_STATUS#

MDO3+35
MDO3-35
MDO2+35
MDO2-35
MDO1+35
MDO1-35
MDO0+35
MDO0-35

LAN_ACT#25,35

LANLINK_STATUS#25,35

B B

A A

Keep JP5.1/2/3 at least 10mils

L

R12 150_0402_5%

MDO3+
MDO3­MDO2+
MDO2­MDO1+
MDO1­MDO0+
MDO0-

CABLE_DETECT

0.1U_0402_16V4Z

V_3P3_LAN V_3P3_LAN_LED

S

G

R380

100K_0402_5%

PREP#21,35

D

G

S

LAN_ACT#_R

R13150_0402_5%

LANLINK_STATUS#_R

D

Q64
FDN338P_SOT23

Q63
2N7002_SOT23

4

MDO0-

MDO0+
MCT0
MDO1-

MDO1+
MCT1
MDO2-

MDO2+
MCT2
MDO3-

MDO3+
MCT3

LAN_TX0­LAN_TX0+
LAN_TX1­LAN_TX1+
LAN_TX2­LAN_TX2+
LAN_TX3­LAN_TX3+

JP4

ACES_87212-1400C10

R323

75_0402_1%

R318

75_0402_1%

R322

75_0402_1%

R321

75_0402_1%

LAN_TX0- 25
LAN_TX0+ 25
LAN_TX1- 25
LAN_TX1+ 25
LAN_TX2- 25
LAN_TX2+ 25
LAN_TX3- 25
LAN_TX3+ 25

9/10

C301

1000P_1808_3KV7K

C302

1000P_1808_3KV7K

3

VMAINPRSNT VMAINPRSNT_R

Layo ut Notice : Filter place as close
ch ip as possible.

V_2P5_LAN

R393

0_0603_5%

0.1U_0402_16V4Z

R376

0_0603_5%

0.1U_0402_16V4Z

R392

0_0603_5%

0.1U_0402_16V4Z

V_1P2_LAN

L17

BLM11A601S_0603

C370

4.7U_0805_10V4Z

L18

BLM11A601S_0603

C369

4.7U_0805_10V4Z

L10

BLM11A601S_0603

C36

4.7U_0805_10V4Z
L15

BLM11A601S_0603

C313

4.7U_0805_10V4Z

NIC_PD 25

G

D

S

Q106

BSS84_SOT23

@

R653 0_0402_5%

11/14

XTALVDD

C353

AVDD1

C340

AVDD2

C356

AVDDL

C355

0.1U_0402_16V4Z

GPHY_PLLVDD

C354

0.1U_0402_16V4Z

PCIE_PLLVDD

C39

0.1U_0402_16V4Z

PCIE_SDS_VDD

C321

0.1U_0402_16V4Z

+3VS

L

V_2P5_LAN V_1P2_LAN

R325
10K_0402_5%

C327

V_3P3_LAN

R3581K_0402_5%

11/14

PCIE_SDS_VDD

V_3P3_LAN

R324

4.7K_0402_5%@

T20

PAD

T59 , T6 0 place together

V_3P3_LAN

R327 4.7K_0402_5%@

R16 4.7K_0402_5%@

R374 4.7K_0402_5%@

GPHY_PLLVDD

2

0.1U_0402_16V4Z
C323

V_3P3_LAN

V_2P5_LAN XTALVDD

T21
PAD

AVDDL
AVDD1

AVDD2

PCIE_PLLVDD

0.1U_0402_16V4Z

V_1P2_LAN

LAN_AUXPWR
VMAINPRSNT

C16

C27

0.1U_0402_16V4Z

4.7U_0805_10V4Z

U25B

1

Layout Notice : 1.2V decoupling CAP.
Place as close chip as possible.

C44

0.1U_0402_16V4Z

C40

C312

0.1U_0402_16V4Z

C332

0.1U_0402_16V4Z

0.1U_0402_16V4Z

C21

C310

0.1U_0402_16V4Z

0.1U_0402_16V4Z

BCM5753

Digial power

GND

Disconnected

Don't care

Analog
power

PLL

BIAS

BCM5753KFBG C0_FPBGA196~D

BLM11A601S_0603

C351

0.1U_0402_16V4Z

C335

0.1U_0402_16V4Z

V_2P5_LAN

L16

C311

0.1U_0402_16V4Z

Security Classification

Issued Date

THIS SHEET OF ENGINEERI NG DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATIO N. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUT HORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DIS CLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/03/10 2006/03/10

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

2

Date: Sheet of

Compal Electronics, Inc.

Magnet ic & RJ45/RJ11

LA-2821P

26 52Saturday, January 14, 2006

1

1.0

A

B

C

D

E

+3VS

1/6

1 1

+3VS +3VS_ACL

R56

0_0402_5%ACCEL@

0_0402_5%ACCEL@

0_0402_5%ACCEL@

+3VS_ACL

C135

0_0805_5%@

D11

CH751H-40_SC76ACCEL@

U6

R50

5/26

Must be placed in the center of the system.

L

pin29 is the center EMI pad which STMicro
recommended not to be connected

+3VS_ACL_IO

R44

+3VS_ACL

R45

2 2

10U_0805_6.3V6MACCEL@

C121

C136

0.01U_0402_16V7K@

0.1U_0402_16V4ZACCEL@

+3VALW

R55

0_0603_5%ACCEL@

+3VS_ACL_IO

LIS3LV02DQ_QFN28ACCEL@

ACCEL_INT 19

ICH_SMBDATA 4,13,14,15,18,21,25
ICH_SMBCLK 4,13,14,15,18,21,25

R48

10K_0402_5%ACCEL@

R43 0_0402_5%

+3VS_ACL

C167

0.01U_0402_16V7K

C214

0.01U_0402_16V7K

0.01U_0402_16V7K

PCIE_RXN221
PCIE_RXP221

C217

CLK_PCIE_MCARD#15

CLK_PCIE_MCARD15

PCIE_RXP2

0.1U_0402_16V4Z

PCIE_WAKE#21

CH_DATA30

CH_CLK30

CLKREQD#15

CLK_PCI_DB15

PCIE_TXP221

C171

4.7U_0805_10V4Z

PCIE_WAKE#
CH_DATA
CH_CLK
CLKREQD#

CLK_PCIE_MCARD#
CLK_PCIE_MCARD

DB_LPC_RST#
CLK_PCI_DB

0_0402_5%

PCIE_C_RXN2PCIE_RXN2

R546

PCIE_C_RXP2

R547 0_0402_5%

PCIE_TXN2
PCIE_TXP2

DB_PWR
DB_PWR_LED#
DB_NUM_LED#

8/30

DB_CAPS_LED#

C493

C492

0.01U_0402_16V7K

C489

0.1U_0402_16V4Z

Mini-Express Card

JP30

DB_LPC_FRAME#
DB_LPC_AD3
DB_LPC_AD2
DB_LPC_AD1
DB_LPC_AD0

XMIT_OFF#

WW_LED#
WL_LED#
WP_LED#

WW_LED#

FOX_AS0B226-S40N-7F

H29

H28

HOLE_MC

HOLE_MC

WP_LED#

+1.5VS+3VS

C494

4.7U_0805_10V4Z

PLT_RST# 7,19,20,21,23,25,32,33

1/4

J12

PAD-SHORT 2x2m

J11

PAD-No SHORT 2x2m

ICH_SMBCLK 4,13,14,15,18,21,25
ICH_SMBDATA 4,13,14,15,18,21,25PCIE_TXN221

USB20_N1_R_MC 32
USB20_P1_R_MC 32

9/8

WL_LED# 32

R497 0_0402_5%@
R500 0_0402_5%@

+3VALW

C491

0.1U_0402_16V4Z

+1.5VS

V_3P3_LAN

+3VALW

WL_LED#

1/6

+3VS

3 3

XMIT_OFF21

4 4

A

9/16

R92
10K_0402_5%@

0_0402_5%

R104

R112

100K_0402_5%@

XMIT_OFF#

D

Q17

G

2N7002_SOT23@

S

Security Classification

Issued Date

THIS SHEET OF ENGINEERI NG DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATIO N. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUT HORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

B

MAY BE USED BY OR DIS CLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2005/03/10 2006/03/10

Must be placed close to JP44.

L

LPC_FRAME#20,31,32,33

LPC_AD320,31,32,33
LPC_AD220,31,32,33
LPC_AD120,31,32,33
LPC_AD020,31,32,33

PLT_RST_B#20,31

NUM_LED#33,34

CAPS_LED#33,34

STB_LED#32,33,35

Compal Secret Data

Deciphered Date

Mini-Card Stand Off

LPC_FRAME#

R452 0_0402_5%DB@

LPC_AD3

R471 0_0402_5%DB@

LPC_AD2

R456 0_0402_5%DB@

LPC_AD1

R488 0_0402_5%DB@

LPC_AD0

R495 0_0402_5%DB@

PLT_RST_B#

R544 0_0402_5%DB@
R530 0_0402_5%DB@

CAPS_LED#

R520 0_0402_5%DB@

STB_LED#

R514 0_0402_5%DB@
R511 0_0603_5%DB@

+3VL

9/12

D

DB_LPC_FRAME#
DB_LPC_AD3
DB_LPC_AD2
DB_LPC_AD1
DB_LPC_AD0
DB_LPC_RST#
DB_NUM_LED#NUM_LED#
DB_CAPS_LED#
DB_PWR_LED#
DB_PWR

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

Mini-Card/Mini-PCI/Accelerometer

LA-2821P

27 52Saturday, January 14, 2006

E

1.0

A

B

C

D

E

F

G

H

VDDA_CODEC

R287
10K_0402_5%

C276

R277

D

1 1

PCM_SPK23

G

0.1U_0402_16V4Z

S

Q48
2N7002_SOT23

150K_0402_1%

10K_0402_5%

R283

C269

0.01U_0402_16V7K

MONO_IN_HD

C264 0.1U_0402_16V4Z

+5VAMP

+

C198
22U_B_10V

C193
1U_0603_10V4Z

VDDA_CODEC

SLP_S3#18,21,25,29,33,35,36,40,43,44

C194
100P_0402_50V8J

R198

0_1206_5%

R288
10K_0402_5%

D

SB_SPKR21

2 2

INT_MIC29

DLINE_IN_L35

DLINE_IN_R35

3 3

0.1U_0402_16V4Z

G

Q51

S

2N7002_SOT23

R290 4.7K_0402_5%
R289 4.7K_0402_5%
R291 4.7K_0402_5%
R292 4.7K_0402_5%

Place close to U14

C545 0.1U_0805_25V7M

11/17

C259 0.1U_0805_25V7M

4 4

C206 0.1U_0805_25V7M

C284 0.1U_0805_25V7M

R219

0_1206_5%@

GNDAGND

A

C279

R279

150K_0402_1%

0.1U_0402_16V4Z

DLINE_IN_R_L
DLINE_IN_R_R

VDDA_CODEC

R297 2.67K_0402_1%

R236 2.2K_0402_5%

AC97_RST#_CODEC20

AC97_SYNC_CODEC20

AC97_SDOUT_CODEC20

B

VDDA_CODEC

0.1U_0402_16V4Z

C224

C265

C225

0.1U_0402_16V4Z

C283 1U_0603_10V4Z
C270 1U_0603_10V4Z
C274 1U_0603_10V4Z
C275 1U_0603_10V4Z

MIC129

C272 1U_0603_10V4Z

MIC229

C273 1U_0603_10V4Z

R284 0_0402_5%@

EAPD29,33

L11
FBM-L10-160808-301-T_0603

C

0.1U_0402_16V4Z

C266

C222

10U_1206_16V4Z

T48PAD

T44PAD

INT_MICL_C
INT_MICR_C
DLINE_IN_RC_L
DLINE_IN_RC_R

T47PAD

T45PAD

T46PAD

MIC1_C
MIC2_C
SENSE_A

SENSE_B

T35PAD

U21

AD1981HDJSTZ-REEL_LQFP48

Security Classification

THIS SHEET OF ENGINEERI NG DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATIO N. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUT HORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DIS CLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

D

0.1U_0402_16V4Z

Issued Date

+3VS_CODEC

C239

C251

0.1U_0402_16V4Z

C247 10P_0402_25V8K

10_0402_5%@

R248

AC97_SDIN0_CODEC

R226 4.7K_0402_5%@

PIN44

R224 4.7K_0402_5%@
R218 10K_0402_5%
R241 4.7K_0402_5%@

AUD_REF
CODEC_REF

AFILT1
AFILT2
AFILT4
MONO_IN_HD

AFILT3
PIN33
PIN40

T36 PAD
T37 PAD

PIN42

2005/03/10 2006/03/10

R225

0_0805_5%
C238
10U_1206_16V4Z

LINE_OUTL 29

LINE_OUTR 29

T33 PAD

L_HP 29

R_HP 29

AC97_BITCLK_CODEC 20

10P_0402_25V8K@

C249

R252

33_0402_5%

T41 PAD
T43 PAD
T42 PAD

T38 PAD

T40 PAD
T39 PAD
T34 PAD

Compal Secret Data

E

+3VS

PORT_A_SNS

C256
1U_0603_10V4Z

12/02

U17

MIC5205YM5_SOT23-5

0.01U_0402_16V7K

Place R198 between DGND & AGND & close to U17

SENSE_A SENSE_A_A

1U_0603_10V4Z

AC97_SDIN0 20

PORT_A_SNS 29

PR_INSERT#

C250

0.1U_0402_16V4Z

Deciphered Date

C282

F

VDDA_CODEC

C205

R293

39.2K_0402_1%
R294

20K_0402_1%

R286

10K_0402_1%

R213

49.9K_0402_1%

R206
143K_0402_1%

SENSE_A_B
SENSE_A_C

Q52

2N7002_SOT23

+

C216

C213

0.1U_0402_16V4Z

22U_B_10V

SENSE_A_A 29
SENSE_A_B 29

VDDA_CODEC

R296

D

S

100K_0402_5%

Title

Size Document Number Rev

Date: Sheet of

10K_0402_5%@

LINE_IN_SENSE

G

R295

C285

0.1U_0603_50V

Compal Electronics, Inc.

AC97 CODEC AD1981HD

LA-2821P

G

LINE_IN_SENSE 35

28 52Saturday, January 14, 2006

H

1.0

A

B

C

D

E

AMP. FOR INTERNAL SPEAKER

C208

R271

0_0402_5%

D

G

S

Q40

G

Q39

R220

0_1206_5%

150U_D_6.3VM@

D

S

1 1

10U_1206_6.3V6M@

10 dB

C261

LINE_OUTR28

LINE_OUTL28

2 2

LINE_C_OUTR LINE_C_R_OUTR

0.1U_0402_16V4Z
C260

LINE_C_OUTL LINE_C_R_OUTL

0.1U_0402_16V4Z

SLP_S3#18,21,25,28,33,35,36,40,43,44

MUTE_LED#34

EAPD28,33
A_SD33

R272

10K_0402_5%

R270

10K_0402_5%

10 dB

R203 10K_0402_5%
R649 0_0402_5%

11/14

R650

1K_0402_5%

2N7002_SOT23@

2N7002_SOT23

C252

+5VAMP+5VALW

10U_1206_6.3V6M@

+

C246

1U_0603_10V4Z@

U20

C248

C240

0.1U_0402_16V4Z

Keep 10 mil width

L

C262 1U_0603_10V4Z

R257

16.5K_0402_1%

R_SPK+
R_SPK-

R256

16.5K_0402_1%

L_SPK+
L_SPK-

LINE_C_R_OUTR

10 dB

LINE_C_R_OUTL

10 dB

PACDN042_SOT23~D@

L_SPK+
L_SPK­R_SPK+
R_SPK-

100P_0402_50V8J

D18

100P_0402_50V8J

C160

C161

C162

100P_0402_50V8J

D19

PACDN042_SOT23~D@

JP19

E&T_3801-04

C163
100P_0402_50V8J

U39 Gain Settings

GAIN11Av(inv)

GAIN0

MAX9710ETP_QFN20

00

0

1

1

0

1

6 dB

10 dB

15.6 dB

21.6 dB

VDDA_CODEC

PORT_A_SNS28

SENSE_A_A28

3 3

4 4

Q49

2N7002_SOT23

A

D

G

S

2N7002_SOT23

DOCK_HPS#35

0.1U_0603_25V7K_V1

Q50

C281

R285
100K_0402_5%

D

G

S

VDDA_CODEC

Q47

2N7002_SOT23

R278
100K_0402_5%

D

G

S

SENSE_A_B28

B

VDDA_CODEC

R273

100K_0402_5%

C278

2.2U_0603_6.3V6K

Q37

2N7002_SOT23

R258
100K_0402_5%

D

G

S

DLINE_OUT_L

0.1U_0402_16V4Z

MIC_SENSE

To Audio / USB Board CONN

0_0402_5% JP25

USB20_N2

USB20_N221

+5VALW

C188

Security Classification

Issued Date

THIS SHEET OF ENGINEERI NG DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATIO N. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUT HORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DIS CLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

USB20_P221

USB20_N321

USB20_P321

USB_OC#221
USB_OC#321

SLP_S530,35,36

DLINE_OUT_L35

DLINE_OUT_R35

R_HP28

INT_MIC28

L_HP28
MIC128
MIC228

2005/03/10 2006/03/10

C

USB20_P2
USB20_N3

USB20_P3

SLP_S5

MIC_SENSE
DLINE_OUT_L

+

+

R162
R170
0_0402_5%
R174
R180

C191
100U_D2_6.3VM
C192
100U_D2_6.3VM

Compal Secret Data

0_0402_5%

0_0402_5%

+5VALW

VDDA_CODEC

Deciphered Date

USB20_N2_R
USB20_P2_R

USB20_N3_R
USB20_P3_R

R207
15_0805_5%
R217
15_0805_5%

ACES_87212-2200

D

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

AMP & Audio Jack

LA-2821P

29 52Saturday, January 14, 2006

E

1.0

5

4

3

2

1

USB CONNECTOR 1

U36

D D

4.7U_0805_10V4Z

+5VALW

SLP_S5

C C

TPS2041BDR_SO8

U35

G548A2P1U_SO8

USB_VCCA USB_VCCB

W=40mils

+

USB_OC#4

PAD-OPEN 3x3m

J13

USB_OC#4 USB_OC#5

R49 0_0402_5%

USB_VCCA+5VALW +5VALWUSB_VCCB

USB20_N421

C118

220U 6.3V M

C499

0.1U_0402_16V4Z

USB_OC#4 21

USB20_P421

C498

1000P_0402_50V7K

(4A,160mils ,Via NO.=8)

R530_0402_5%

D12

USB20_N4_R
USB20_P4_R

R570_0402_5%

USB20_N4
USB20_P4

USB20_N4
USB20_P4 USB20_P5

PACDN042_SOT23~D@

JP16

TYCO_1-1734062-1

11/17

USB20_N5_R
USB20_P5_R

USB20_N5

PACDN042_SOT23~D@

R51 0_0402_5%

USB20_N5
USB20_P5

R52 0_0402_5%C137

D10

USB20_N5 21
USB20_P5 21

W=40mils

C123

C122

0.1U_0402_16V4Z

1000P_0402_50V7K

+

C126

220U 6.3V M

USB_OC#5SLP_S5

U7

TPS2041BDR_SO8

SLP_S5

SLP_S5 29,35,36

USB_OC#5 21

BT Connector

JP18

USB20_P0_R

B B

ACES_87212-0800

USB20_N0_R

R674 100_0402_5%
R677 100_0402_5%

R85

0_0402_5%
0_0402_5%

R87

11/23

D16

PACDN042_SOT23~D@

+3VAUX_BT

USB20_P0
USB20_N0

BT_LED 32

CH_DATA 27

CH_CLK 27

USB20_P0 21
USB20_N0 21

Q12 SI2301BDS_SOT23

S

D

C140
1U_0603_10V4Z

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERI NG DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATIO N. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUT HORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DIS CLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/03/10 2006/03/10

Compal Secret Data

Deciphered Date

2

BT_OFF21

G

R69
100K_0402_5%

0.01U_0402_16V7K

R70

47K_0402_5%

Title

Size Document Number Rev

Date: Sheet of

C138

0.1U_0402_16V4Z

@

9/14

Compal Electronics, Inc.

USB I/O & BT Connector

LA-2821P

0.1U_0402_16V4Z

C143

C144

1

+3VAUX_BT+3VALW

C142

4.7U_0805_10V4Z

1.0

30 52Saturday, January 14, 2006

A

B

C

D

E

1 1

DCD#1
RI#1
CTS#1
DSR#1

4.7K_1206_8P4R_5%

IRRX

U29

CLOCK

GPIO

POWER

LPC47N217_STQFP64

Base I/O Address

0 = 02Eh
1 = 04Eh*

R434
10_0402_5%@

9/8

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3

LPC_FRAME#
LPC_DRQ#0

SIO_RST#
SIO_PD#

PM_CLKRUN#
CLK_PCI_SIO
SIRQ
SIO_PME#

CLK_14M_SIO
SIO_GPIO40

PID0
PID1
SIO_GPIO43
SIO_GPIO44
SIO_DPIO45
CARD_ID#
SER_SHD
SIO_GPIO10
SIO_GPIO11
SIO_GPIO12
SIO_IRQ

SW_EXPCRD_RST#

LPC_AD020,27,32,33
LPC_AD120,27,32,33
LPC_AD220,27,32,33

RP30

SIO_GPIO12
SIO_GPIO10
SIO_GPIO44

2 2

3 3

10K_1206_8P4R_5%

+3VS

+3VS

R428
R437

R8

10K_0402_5%

R422

10K_0402_5%

R435

10K_0402_5%

R436

10K_0402_5%

R429

10K_0402_5%

R438

10K_0402_5%

SIO_GPIO43

SIO_IRQ

10K_0402_5%

SIO_DPIO45

10K_0402_5%

CARD_ID#

R421

0_0402_5%

PID0

PID1

SIO_GPIO11

SIO_GPIO40

EXPCRD_RST# 35

NPCI_RST#21,33

PLT_RST_B#20,27

R431 0_0402_5%
R432 0_0402_5%@
R433 10K_0402_5%

+3VS

High : Compal MXM
Low : Standard MXM

+3VS

R417 10K_0402_5%

LPC_AD320,27,32,33

LPC_FRAME#20,27,32,33

LPC_DRQ#020

PM_CLKRUN#21,23,32,33

CLK_PCI_SIO15

SIRQ21,23,32,33

CLK_14M_SIO15

SER_SHD35

RP29

R427
1K_0402_5%

SERIAL I/F

FIR

LPC I/F

PARALLEL I/F

CLK_14M_SIOCLK_PCI_SIO

R420
10_0402_5%@

+3VS

RXD1
TXD1
DSR#1
RTS#1
CTS#1
DTR#1
RI#1
DCD#1

IRRX

LPTINIT#
LPTSLCTIN#
LPD0
LPD1
LPD2
LPD3
LPD4
LPD5
LPD6
LPD7
LPTSLCT
LPTPE
LPTBUSY
LPTACK#
LPTERR#
LPTAFD#
LPTSTB#

C391

0.1U_0402_16V4Z

0.1U_0402_16V4Z

RXD1 35

R403 1K_0402_5%

TXD1 35
DSR#1 35
RTS#1 35
CTS#1 35
DTR#1 35
RI#1 35
DCD#1 35

LPTINIT# 35
LPTSLCTIN# 35
LPD0 35
LPD1 35
LPD2 35
LPD3 35
LPD4 35
LPD5 35
LPD6 35
LPD7 35
LPTSLCT 35
LPTPE 35
LPTBUSY 35
LPTACK# 35
LPTERR# 35
LPTAFD# 35
LPTSTB# 35

+3VS

C401

C383

C397

0.1U_0402_16V4Z

4.7U_0805_10V4Z

LPD3
LPD2
LPD1
LPD0

LPD7
LPD6
LPD5
LPD4

LPTACK#
LPTBUSY
LPTPE
LPTSLCT

LPTSTB#
LPTAFD#
LPTERR#

LPTSLCTIN#SW_EXPCRD_RST#

LPTINIT#

+5VS_PRN

RP28

4.7K_1206_8P4R_5%
RP27

4.7K_1206_8P4R_5%
RP26

4.7K_1206_8P4R_5%
RP25

4.7K_1206_8P4R_5%
R414

4.7K_0402_5%
R418

4.7K_0402_5%

+5VS

D31
CH751H-40_SC76

C410
18P_0402_50V8K

@

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERI NG DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATIO N. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUT HORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DIS CLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2005/03/10 2006/03/10

C399
10P_0402_25V8K

@

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

D

Date: Sheet of

Compal Electronics, Inc.

SUPER I/O LPC47N217

LA-2821P

31 52Saturday, January 14, 2006

E

1.0

5

4

3

2

1

+5VS

B IOS ROM

+3VALW

U14

D D

0.1U_0402_16V4ZSPI@

C C

B B

LPC_PD#21,33

A A

+3VALW

8/26

C172

SPI_CS#21
SPI_CLK21

SPI_SI21 SPI_SO 21

4.7K_0402_5%@

0_0402_5%TPM1.2@

SPI_WP#
SPI_HOLD#
SPI_CS#
SPI_CLK
SPI_SI

+3VS

R402
R401

+3VS

R379

R375

U13

MX25L8005MI-15G_SO8-150mil@ R212

LPC_FRAME#20,27,31,33

10K_0402_5%TPM1.2@
0_0402_5%TPM1.2@

L

CLK_PCI_TCG15

PM_CLKRUN#21,23,31,33

Place R1447 close to Y8.1

CLK_TPM33

C365

32.768KHZ_12.5P_1TJS125BJ2A251TPM1.2@

Y5

C341

PLT_RST#7,19,20,21,23,25,27,33

C392

R397

L

C349

0.1U_0402_16V4ZTPM1.2@

LPC_AD020,27,31,33
LPC_AD120,27,31,33
LPC_AD220,27,31,33
LPC_AD320,27,31,33

10P_0402_50V8K@

18P_0402_50V8JTPM1.2@

18P_0402_50V8JTPM1.2@

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
LPC_FRAME#
PLT_RST#

SIRQ

SIRQ21,23,31,33

CLK_PCI_TCGLPC_PD#

R415
10_0402_5%@

PM_CLKRUN#

0_0402_5%@

9/13

8/26

SPI_WP#
SPI_HOLD#
SPI_CS#
SPI_CLK
SPI_SI

R109
47_0402_5%SPI@

R1291 should be placed less
than 100 mils from U61 & U65.

SST25LF080A_SO8-200milSPI@

SPI_SO

TPM1.2 on board

0.1U_0402_16V4ZTPM1.2@
C393

0.1U_0402_16V4ZTPM1.2@

TPM_XTALO
TPM_XTALI

TPM_XTALI

R394

10M_0402_5%TPM1.2@

TPM_XTALO

+3VS +3VALW

C394

U26

SLB 9635 TT 1.2

+3VALW

8/26

R108

SPI_WP#

3.3K_0402_5%SPI@

R155

SPI_HOLD#

3.3K_0402_5%SPI@

The chip must be placed on PCB easily

L

rework place for debug.

C350

0.1U_0402_16V4ZTPM1.2@

SLB 9635 TT 1.2_TSSOP28TPM1.2@

TPM_GPIO
TPM_GPIO2

Base I/O Address

0 = 02Eh

* 1 = 04Eh

R390

T23PAD
T24PAD

4.7K_0402_5%TPM1.2@

0_0402_5%TPM1.2@

R377

4.7K_0402_5%@

R378

+3VS

Wireless LED

WL/BT_LED34

BT_LED30

AMBER_BATLED#33

GREEN_BATLED#33

BT_LED

WL_LED

9/12

AMBER_BATLED#

DTA114YKA_SC59

GREEN_BATLED#

Battery LED

19-22UYSYGC/S530-A2/TR8_ G/Y

Finger printer

9/8

USB20_N121

USB20_P121

L

USB20_N1
USB20_P1

D9

PACDN042_SOT23~D@

Place R1365/R1366 close to JP38.2/JP38.3
and minimize the stub length.

R570 0_0402_5%@

USB20_N1_R
USB20_P1_R

R569 0_0402_5%@

12/8

2.2K_0402_5%

LTST-S110TBKT-5A

BLUE LED

G

Q35

2N7002_SOT23

2N7002_SOT23

Q44

150_0402_5%

R46
R47

USB20_N1_R_MC
USB20_P1_R_MC

R221

D28

D

S

D

G

S

Q36

+3VL

HDD_STP21

47K

10K

DTA114YKA_SC59

R233

+3VL

47K

10K

Q45

R234

150_0402_5%

D30

AMBER GREEN

+3VS

C124

0.1U_0402_16V4Z

9/8

0_0402_5%

USB20_N1_R
USB20_P1_R

0_0402_5%

USB20_N1_R_MC 27

9/8

USB20_P1_R_MC 27

+3VS

47K

10K

Q34
DTA114YKA_SC59

WL_LED

Mini-PCIE Card LED

BT_LED

R199

100K_0402_5%

R95

WL_LED

100K_0402_5%

8/23

0_0402_5%@

2N7002_SOT23
Q41

HDD_STP

ACES_87212-0800

D

G

S

R211
100K_0402_5%

IDE_LED#20

19-22UYSYGC/S530-A2/TR8_ G/Y

1/4

JP15

HDD_STP#

DTA114YKA_SC59

IDE_LED#

WL_LED# 27

+3VS

9/6

47K

10K

Q42

DTA114YKA_SC59

R243

150_0402_5%

HDD LED

STB_LED#27,33,35

STB_LED34

17-21SYGC/S530-E1/TR8_GRN

+3VS

47K

10K

Q46

R242

150_0402_5%

D27

STB_LED#

Q38

DTA114YKA_SC59

150_0402_5%

POWER LED

GREEN

GREENAMBER

+3VL

47K

10K

R222

D29

Security Classification

Issued Date

THIS SHEET OF ENGINEERI NG DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATIO N. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUT HORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DIS CLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/03/10 2006/03/10

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

2

Date: Sheet of

Compal Electronics, Inc.

TCG/BIOS ROM/PS2/LED/SW

LA-2821P

32 52Saturday, January 14, 2006

1

1.0

5

4

+3VL

3

+3VS

2

1

0.1U_0402_16V4Z

KSO[0..13]

+RTCVCC

C263

C243

KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9 FWP#
KSO10
KSO11

KSO13

KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7

TP_CLK
TP_DATA
KBD_CLK
KBD_DATA
PS2_CLK
PS2_DATA

PM_CLKRUN#
SIRQ
CLK_PCI_EC
RUNSCI_EC#

LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0
LPC_FRAME#

LPCPD#
CRY1

CRY2

C253

0.1U_0402_16V4Z

C255

0.1U_0402_16V4Z

U18

C257

4.7U_0805_10V4Z

Keyboard/Mouse Inte rface

Power Mgmt/SIRQ

LPC

Bus

SMSC_LPC47N250_TQFP-100P

AGND FILTER

0.1U_0402_16V4Z

PWR_GD_EC

4

R670 0_0402_5%
R669 0_0402_5%@

11/21

PWR_GD
PGD_IN

Security Classification

Issued Date

THIS SHEET OF ENGINEERI NG DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATIO N. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUT HORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DIS CLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C196

+3VL

D D

C C

B B

A A

RP21

KSI3
KSI2
KSI1
KSI0

10K_1206_8P4R_5%

RP22

KSI7
KSI6
KSI5
KSI4

10K_1206_8P4R_5%

+5VS

R192

TP_CLK

10K_0402_5%

R197

TP_DATA

10K_0402_5%

RP23

KBD_CLK
KBD_DATA
PS2_CLK
PS2_DATA

10K_1206_8P4R_5%

Note: R94 must be removed when
R1354 stuff and R87 remove.

+3VS

L

R216

LPCPD#

10K_0402_5%

R262

RUNSCI_EC#

10K_0402_5%

Pin34 250 -- LP CPD#

CLK_PCI_EC

R232

10_0402_5%@

C237

10P_0402_50V8J@

1021@

250@
R127

R129

R128

R131

R977

R78

NPCI_RST#21,31

PLT_RST#7,19,20,21,23,25,27,32

LPC_PD#21,32

10P_0402_50V8J

0.1U_0402_16V4Z

11/14

NPCI_RST#

R651 0_0402_5%

PLT_RST#

R652 0_0402_5%@
R215 0_0402_5%@

ADP_EN

R223 0_0402_5%@

R265 2M_0402_5%@

Y3

C267

32.768KHZ_12.5P_1TJS125DJ2A073

C215

0.1U_0402_16V4Z

KSO[0..13]34

Pin3 250 : KSO12/OUT8 /KBRST

KSI[0..7]34

TP_CLK34

TP_DATA34

KBD_CLK35

KBD_DATA35

PS2_CLK35

PS2_DATA35

PM_CLKRUN#21,23,31,32

SIRQ21,23,31,32

CLK_PCI_EC15

RUNSCI_EC#21

LPC_AD320,27,31,32
LPC_AD220,27,31,32
LPC_AD120,27,31,32
LPC_AD020,27,31,32

LPC_FRAME#20,27,31,32

R266

120K_0402_5%

C268
10P_0402_50V8J

1U_0603_10V4Z

R62

5

C244

0.1U_0402_16V4Z

General Purpose I/O Int erface

Access Bus Inter face

Miscellane ous

PWR_GD 18,36,37,45,47
PGD_IN 37,45

2005/03/10 2006/03/10

3

C226

0.1U_0402_16V4Z

KBC1021_TQFP100

R249 300_0402_5%

Pin91 250 -- nDM S_LED

R647

100K_0402_5%

0_0402_5%
0_0402_5%

0_0402_5%
33_0402_5%@
0_0402_5%
0_0402_5%@
R268

10K_0402_5%@ C254
1K_0402_5%@

R276
1K_0402_5%@

R282
1K_0402_5%

R275

1K_0402_5%@

R254

1K_0402_5%@

R235

1K_0402_5%

C236

4.7U_0805_10V4Z

KBC_PWR_ON 42

GREEN_BATLED# 32
BATSELB_A# 41
INV_PWM 17

FAN_PWM 4
CHGCTRL 40,41

ON/OFFBTN_KBC# 34
LOW_BAT# 21

KSO14 34
KSO15 34

PM_RSMRST# 21

BATCON 41

THM_MBAY# 46
PCI_SERR# 19,23
THM_MAIN# 46

CLK_14M_KBC 15

VCC1_PWRGD 37

AMBER_BATLED# 32
STB_LED# 27,32,35
CAPS_LED# 27,34

ADP_EN

+3VL

C209

0.1U_0402_16V4Z

KBC_PWR_ON
GREEN_BATLED#

BATSELB_A#
KBRST#
INV_PWM
FAN_PWM
CHGCTRL

ON/OFFBTN_KBC#
LOW_BAT#
KSO14KSO12
KSO15

PM_RSMRST#
GPIO8

R280 0_0402_5%@

GPIO9

R281 0_0402_5%@

BATCON
EC_GPIO12
EC_GPIO13
THM_MBAY#
PCI_SERR#
THM_MAIN#
A20M

NUM_LED#
SLP_S3#

R185 0_0402_5%

MODE

Pin57 250 -- MODE Pin1 250 -- TEST Pin ( N C !! )

R202 0_0402_5%

AB1A_DATA
AB1A_CLK

AB1B_DATA
AB1B_CLK

R204 0_0402_5%

PGM

Pin56 250 -- PGM
Pin83 250 -- nEA ( pull up !! )

EA#
CLK_14M_KBC
S_CLK
PM_POK
PWR_GD_EC
VCC1_PWRGD
EC_GPIO19

Pin50 250 -- 24MH z_Out

TEST

Pin52 250 -- X OSEL

EC_GPIO10
AMBER_BATLED#
STB_LED#
CAPS_LED#

EC_GPIO19

R251

EC_GPIO12

R264

EC_GPIO10

R214

R260

S_CLK

R261
R399

MODE
PGM

R267

FWP#

J9

PGM

NO SHORT PADS

FWP#
TEST
EA#

Compal Secret Data

Deciphered Date

2

+3VL

R205
10K_0402_5%

D25

CH751H-40_SC76

Pin82 250 -- nFWP

KSO16 EC_GPIO12
KSO17

D24

CH751H-40_SC76

R255

10K_0402_5%

CH751H-40_SC76

+3VL

ADP_ID 47
ADP_PS1 47
ADP_PS0 47
CB_CLK 24

CLK_TPM 32

L

D26

NUM_LED# 27,34
SLP_S3# 18,21,25,28,29,35,36,40,43,44
KSO16 34

EAPD 28,29
AB1A_DATA 46

AB1A_CLK 46
AB1B_DATA 46

AB1B_CLK 46
A_SD 29

R238
0_0402_5%

ADP_EN 47

R268,R280,R281
stuff when KBC LPC47N250 used

1. For normal operation:

Un-install R29,R65

2. For KBC internal ROM flash:

Install R29,R65

KB_RST# 20

ADP_PRES 18,25,40,41,42,47

+3VL

GATEA20 20

KSO17 34

PM_POK 7,21

Pin58 250 -- 32KH z_OUT
Pin49 250 -- Rese t Out

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

LA-2821P

BIOS debug port
Place under KB area

+3VL

ACES_85201-0602@

R259

210K_0402_1%

R263

100K_0402_5%

R194

100K_0402_5%

4.7K_1206_8P4R_5%

100K_0402_5%

R246

10_0402_5%

@

R274

10K_0402_5%

EC_GPIO12

+3VL

ACES_85201-0602@

JP21

RP24

R250

C245

10P_0402_50V8K

@

JP22

VCC1_PWRGD
GPIO9

GPIO8

THM_MAIN#

EC_GPIO13

AB1A_CLK
AB1A_DATA
AB1B_CLK
AB1B_DATA

NUM_LED#

CLK_14M_KBC

FWP# PM_POK

VCC1_PWRGD
NUM_LED#
STB_LED#
CAPS_LED#

For KBC debugging used.

LPC47N1021

33 52Saturday, January 14, 2006

1

+3VL

+3VL

1.0

SWITCH BOARD.

+3VS +3VL +5VS

MUTE_LED#29

ON/OFF#
MUTE_LED#
KSO2
KSI6
KSI7
KSI5

LID_SW#_2nd

JP1

ACES_88028-3000

R1 0_0402_5%

LID_SW#

STB_LED
KSI0
NUM_LED#
CAPS_LED#
KSI1
WL/BT_LED
LID_SW#_2nd
KSI2

KSI4

LID_SW# 17,21

STB_LED 32
NUM_LED# 27,33

CAPS_LED# 27,33
WL/BT_LED 32

MDC 1.5 Conn.

JP26

AC97_SDOUT_MDC20

AC97_SYNC_MDC20

AC97_SDIN120

1000P_0402_50V7KMDC1.5@

R239

33_0402_5%

AC97_SDOUT_MDC
AC97_SYNC_MDC

AC97_SDIN1_MDC
AC97_RST#_MDC

+3VS

C220

C223

C204

4.7U_0805_10V4Z@

0.1U_0402_16V4ZMDC1.5@ CP6

+3VS

AC97_BITCLK_MDC

R209

TYC O_1-179396-2~DMDC1.5@

C221

10_0402_5%@

10P_0402_25V8K@

Connector for MDC Rev1.5

AC97_BITCLK_MDC 20AC97_RST#_MDC20

INT_KBD CONN.

KSO[0..17]33
KSI[0..7]33

KSO0
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO14
KSO11
KSO12
KSO1
KSO17
KSO13
KSO15
KSO16
KSI2
KSI3
KSI6
KSI4
KSI1
KSI5
KSI0
KSI7

Update to 18x8 angelfire keyboard matrix

CP1

KSO0
KSO2
KSO3
KSO4

100P_1206_8P4C_50V8

CP2

KSO5
KSO6
KSO7
KSO8

100P_1206_8P4C_50V8

CP3

KSO9
KSO10
KSO14
KSO11

100P_1206_8P4C_50V8

KSO[0..17]
KSI[0..7]

11/3

JP12

ACES_85203-26021

KSO12
KSO1
KSO17
KSO13

KSO15
KSO16
KSI2
KSI3

KSI6
KSI4
KSI1
KSI5

KSI0
KSI7

KSO0
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO14
KSO11
KSO12
KSO1
KSO17
KSO13
KSO15
KSO16
KSI2
KSI3
KSI6
KSI4
KSI1
KSI5
KSI0
KSI7

CP4

100P_1206_8P4C_50V8

CP5

100P_1206_8P4C_50V8

100P_1206_8P4C_50V8

CP7

100P_1206_8P4C_50V8

Power button

+3VL

+3VL

R167

100K_0402_5%

ON/OFF#35

ON/OFF#

1U_0603_10V4Z

C177

U15F
SN74LVC14APWLE_TSSOP14

R172

100K_0402_5%

1U_0603_10V4Z

C183

+3VL

G

R163
100K_0402_5%

ON/OFFBTN_KBC#

D

Q29
2N7002_SOT23

S

ON/OFFBTN_KBC# 33

D23

RB751V_SOD323

+3VALW

R179

100K_0402_5%

ON/OFFBTN#

TrackPoint CONN. T/P BOARD.

JP11

SP_DATA

ON/OFFBTN# 21

Security Classification

Issued Date

THIS SHEET OF ENGINEERI NG DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATIO N. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUT HORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DIS CLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2005/03/10 2006/03/10

E&T_6700-Q08N-00R

11/3

Compal Secret Data

Deciphered Date

+5VS +5VS

SP_CLK

+5VS

C116

0.1U_0402_16V4Z

TP_DATA33

TP_CLK33

TP_DATA
TP_CLK

SP_DATA
SP_CLK

Title

Size Document Number Rev

Date: Sheet of

+5VS

JP14

ACES_87212-0800

Compal Electronics, Inc.

MDC/KBD/ON_OFF/LID

LA-2821P

C490

0.1U_0402_16V4Z

1.0

34 52Saturday, January 14, 2006

A

DOCK CONN. 184PIN

11/18

L14

KC FBM-L18-453215-900LMA90T_1812

1 1

ON/OFF#34

D_VSYNC16

D_HSYNC16

D_DDCDATA16

D_DDCCLK16

DVI_DETECT18

2 2

LINE_IN_SENSE28

ACOCP_EN#47

LPTSTB#31
LPTAFD#31

LPTERR#31

3 3

ON/OFF#
MDO2+

MDO2-

MDO2-26

MDO0+

MDO0+26

MDO0-

MDO0-26

LAN_ACT#_DOCK
LANLINK_STATUS#_DOCK

D_DDCDATA
D_DDCCLK
DVI_DETECT

D_RED
D_GREEN
D_BLUE

M_COMP16,18
M_CRMA16,18

M_LUMA16,18

DCD#1

DCD#131

RI#1

RI#131

DTR#1

DTR#131

CTS#1

CTS#131

RTS#1

RTS#131

DSR#1

DSR#131

TXD1

TXD131

RXD1

RXD131

LPTSTB#
LPTAFD#
LPTERR#

Place them close to U50/U51/U52

C314

1000P_0402_50V7K

JP27A

JAE_SP03-14588-PCL03

B

DOCKVINVIN

C305
1000P_0402_50V7K

DETECT
MDO3+

MDO3­MDO1+

MDO1­PWR_LED

R346 10K_0402_5%

DVI_DDC_CLK
DVI_DDC_DAT

DVI_TX2­DVI_TX2+

DVI_TX1­DVI_TX1+

DVI_CLK­DVI_CLK+

DVI_TX0­DVI_TX0+

DOCK_ADP_SIGNAL

DOCK_ID

DOCK_ID

5/24

SLP_S529,30,36

DOCKVIN

MDO3+ 26MDO2+26
MDO3- 26

MDO1+ 26
MDO1- 26

SLP_S5#_5R

DVI_DDC_CLK 18
DVI_DDC_DAT 18

DVI_TX2- 18
DVI_TX2+ 18

DVI_TX1- 18
DVI_TX1+ 18

DVI_CLK- 18
DVI_CLK+ 18

DVI_TX0- 18
DVI_TX0+ 18
DOCK_ADP_SIGNAL

DOCK_ID 21

R9

10K_0402_5%@

DOCK_ADP_SIGNAL

11/22

G

Q62

2N7002_SOT23

11/22

+3VS

R299

1K_0402_1%

+5VALW

D

S

R357
220K_0402_5%

SLP_S5#_5R

Q77

2N7002_SOT23@

ADP_SIGNAL

C

DOCK_MOD_RING

D

S

1U_0603_10V6K@

USB20_N621

USB20_P621

USB20_N721

USB20_P721

G

C546

22K_0402_5%@

11/23

USB20_N6
USB20_P6
USB20_N7
USB20_P7

R671

PREP#

LPTACK#31

LPTBUSY31

LPTPE31

LPTSLCT31

LPD731
LPD631
LPD531
LPD431
LPD331
LPD231
LPD131
LPD031

LPTSLCTIN#31

LPTINIT#31

R301

0_0402_5%

R300

0_0402_5%

R304

0_0402_5%

R298

0_0402_5%

SER_SHD31

EXPCRD_RST#31

DOCK_MOD_TIP

LPTACK#
LPTBUSY
LPTPE
LPTSLCT
LPD7
LPD6
LPD5
LPD4
LPD3
LPD2
LPD1
LPD0
LPTSLCTIN#
LPTINIT#

USB20_N6_R
USB20_P6_R
USB20_N7_R
USB20_P7_R

SER_SHD
EXPCRD_RST#
DETECT

D

JP2

ACES_85205-0200

JP27B

JAE_SP03-14588-PCL03

KBD_DATA
KBD_CLK
CPPE#
PS2_DATA
PS2_CLK
DOCK_HPS#

DLINE_IN_L
DLINE_IN_R

DLINE_OUT_L
DLINE_OUT_R

PCIE_TXP4
PCIE_TXN4

PCIE_C_RXP4
PCIE_C_RXN4 PCIE_RXN4

+5VS

DOCK_MOD_TIPDOCK_MOD_RING

L

PCIE_RXP4

R3

0_0402_5%

R4

0_0402_5%

CLK_PCIE_DOCK
CLK_PCIE_DOCK#
PREP#

VA_ON#

R302
1K_0402_5%

C1

22U_0805_6.3V4Z@

9/15

Note: Place C1 close to JP27.P2 pin

E

KBD_DATA 33
KBD_CLK 33

CPPE# 15,19
PS2_DATA 33
PS2_CLK 33
DOCK_HPS# 29

DLINE_IN_L 28
DLINE_IN_R 28

DLINE_OUT_L 29
DLINE_OUT_R 29

PCIE_TXP4 21

PCIE_TXN4 21

PCIE_RXP4 21
PCIE_RXN4 21

CLK_PCIE_DOCK 15
CLK_PCIE_DOCK# 15
PREP# 21,26

C291

0.1U_0402_16V4Z

D_RED RED

R7

0_0402_5%@

D_GREEN

R5

D_BLUE

R6

D_GREEN18

C5

0.1U_0402_16V4Z

GREEN16

C8

0.1U_0402_16V4Z

D_BLUE18

ISO_PREP#21

4 4

D_BLUE
BLUE

BLUE16

ISO_PREP#

U3

FSA66P5X_SC70-5

A

0_0402_5%@
0_0402_5%@

+3VS

D_GREEN
GREEN

ISO_PREP#

GREEN
BLUE

U2

FSA66P5X_SC70-5

B

D_RED18

RED16

+3VS+3VS

C6

0.1U_0402_16V4Z

D_RED
RED

ISO_PREP#

+3VALW V_3P3_LAN

U1

STB_LED#27,32,33

FSA66P5X_SC70-5

Security Classification

Issued Date

THIS SHEET OF ENGINEERI NG DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATIO N. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUT HORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DIS CLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

SLP_S3#18,21,25,28,29,33,36,40,43,44

2005/03/10 2006/03/10

Compal Secret Data

D

G

S

Deciphered Date

R352
10K_0402_5%

PWR_LED

Q61
2N7002_SOT23

LAN_ACT#_DOCK

R372

10K_0402_5%

D

D

Q58

G

2N7002_SOT23

S

LAN_ACT#

LANLINK_STATUS#_DOCK

D

Q59

G

2N7002_SOT23

S

LANLINK_STATUS#

Title

Size Document Number Rev

Date: Sheet of

LAN_ACT# 25,26

LANLINK_STATUS# 25,26

Compal Electronics, Inc.

Docking CONN.

LA-2821P

35 52Saturday, January 14, 2006

E

1.0

A

B

C

D

E

+5VALW to +5VS Transfer

RUNON

+5VS+5VALW

C271

0.1U_0402_16V4Z

U37

SI4800DY_SO8

RUNON

R583
470_0402_5%

C501

0.01UF_0402_25V7K

C280
10U_0805_10V4Z

+3VS+3VALW

10U_0805_10V4Z

C510

0.1U_0402_16V4Z

C509

U22

1 1

2 2

PAD-SHORT 2x2m

C277

SI4800DY_SO8

10U_0805_10V4Z

+3VALW to +3VS Transfer

B+

J3

PAD-SHORT 2x2m

R582

330K_0402_5%

J15

SLP_S3

G

D

Q75
2N7002_SOT23

S

C514

10U_0805_10V4Z

+2.5VALW to +2.5VS Transfer

RUNON

+2.5VS+2.5VALW

C487

0.1U_0402_16V4Z

C458
10U_0805_10V4Z

U32

C456

SI4800DY_SO8

10U_0805_10V4Z

3 3

+1.8V to +1.8VS Transfer

+1.8V

SI2306DS-T1 1N_SOT23

C295

1U_0603_10V4Z

RUNON

+1.8VS

Q53

D

S

C296

G

1U_0603_10V4Z

C29 0.1U_0603_50V4Z

+VCCP +3VS

C526 0.1U_0603_50V4Z@

+VCCP +3VALW

C155 0.1U_0603_50V4Z@

+3VS +3VALW

C141 0.1U_0603_50V4Z@

+3VS +5VS

C139 0.1U_0603_50V4Z@

+3VS +5VS

C524 0.1U_0603_50V4Z@

+1.5VS +3VS

C419 0.1U_0402_16V4Z

+3VALW

C290 0.1U_0402_16V4Z

+3VS

+5VALW

R62
100K_0402_5%

SLP_S529,30,35

SLP_S5#21,44

SLP_S3#18,21,25,28,29,33,35,40,43,44

SLP_S5

SLP_S5#

SLP_S3

SLP_S3#

G

G

D

Q9
2N7002_SOT23

S

+3VL

R244
100K_0402_5%

D

Q43
2N7002_SOT23

S

Discharge circuit

+0.9V +1.5VS+1.8V

G

R574
470_0402_5%

D

Q74
2N7002_SOT23

S

B

R571
470_0402_5%

D

R573

0_0402_5%@

SLP_S3

R572

0_0402_5%

4 4

A

G

Q73
2N7002_SOT23

S

+1.8VS

R138
470_0402_5%

D

SLP_S3 SLP_S3 SLP_S3 SLP_S3

G

Q19
2N7002_SOT23

S

+2.5VS

R32
470_0402_5%

D

Q7

G

2N7002_SOT23

S

Security Classification

Issued Date

THIS SHEET OF ENGINEERI NG DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATIO N. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUT HORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DIS CLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

+3VS

R94
470_0402_5%

D

Q18

G

2N7002_SOT23

S

2005/03/10 2006/03/10

PWR_GD 18,33,37,45,47

+5VS

R93

470_0402_5%

D

Q16

G

2N7002_SOT23

S

Compal Secret Data

Deciphered Date

R577
470_0402_5%

D

SLP_S3SLP_S5SLP_S5

G

Q72

S

2N7002_SOT23

Title

Size Document Number Rev

D

Date: Sheet of

Compal Electronics, Inc.

DC/DC Circuits

LA-2821P

36 52Saturday, January 14, 2006

E

1.0

+1.8VS

R139

1K_0402_5%

R158

330_0402_5%

B

330_0402_5%

C

Q26

MMBT3904_SOT23

E

R181

560K_0402_5%

R157

B

+3VS+3VS

C

Q25

MMBT3904_SOT23

E

+5VS

R177
180K_0402_5%

C190

0.1U_0402_16V7K

U15A

SN74LVC14APWLE_TSSOP14

R171

47K_0402_5%

0.1U_0402_16V7K

+3VL

C176

0.1U_0402_16V4Z

U15C

SN74LVC14APWLE_TSSOP14

C181

+3VL+3VL

U15B

SN74LVC14APWLE_TSSOP14

D

Q23

G

2N7002_SOT23

S

D20

RB751V_SOD323

J8

PAD-SHORT 2x2m

+3VS

R156
10K_0402_5%

PWR_GD

+3VL

PWR_GD 18,33,36,45,47

R184
100K_0402_5%

C186

0.1U_0402_16V7K

+3VL

U15D

SN74LVC14APWLE_TSSOP14

UNUSED PARTS

G

+3VL

R188
10K_0402_5%

D

S

Q33
2N7002_SOT23

VCC1_PWRGD 33

CLK_ENABLE#15,45

VCCP_POK43

R578

0_0402_5%

R579

0_0402_5%@

+1.5VS +2.5VS+2.5VS

R196

1K_0402_5%

0.1U_0402_16V4Z

PGD_IN_1

11/21

CLK_ENABLE#

R178

330_0402_5%

B

C502

PGD_IN_1 45

R581

0_0402_5%@

R210

330_0402_5%

B

C

E

+3VS

E

Q32

MMBT3904_SOT23

D33 RB751V_SOD323

U33

SN74LVC1G17DBVR_SOT23-5

C

Q31

MMBT3904_SOT23

Need be tune to
3msec time delay

L

R580

100K_0402_5%

0.1U_0603_16V7K

+3VL

U15E

SN74LVC14APWLE_TSSOP14

+3VS

C497

D

Q24

G

2N7002_SOT23

S

C500

0.1U_0402_16V4Z

U34

SN74LVC1G17DBVR_SOT23-5

PGD_INPWR_GD

FM1

M1
HOLEA

CF1

M2
HOLEA

PGD_IN 33,45

PAD1

PAD-R118x63

1/4

Security Classification

Issued Date

THIS SHEET OF ENGINEERI NG DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATIO N. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUT HORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DIS CLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2005/03/10 2006/03/10

Compal Secret Data

Deciphered Date

FM3

CF2

H3
HOLEA

FM2

CF3

H1
HOLEA

H11
HOLEA

H4

H2

HOLEA

HOLEA

H26

H25

HOLEA

HOLEA

FM4

CF4 CF11

FM6

FM5

CF6

CF5

H21

H23

H12

HOLEA

HOLEA

HOLEA

Title

Size Document Number Rev

Date: Sheet of

H8

H5
HOLEA

H16
HOLEA

CF7

H6
HOLEA

H13
HOLEA

CF9

HOLEA

H18
HOLEA

H10
HOLEA

H19
HOLEA

H14
HOLEA

CF12

H27
HOLEA

H20
HOLEA

H9
HOLEA

CPU

Compal Electronics, Inc.

POK CKT

LA-2821P

CF8

37 52Saturday, January 14, 2006

H24
HOLEA

H17
HOLEA

H15
HOLEA

CF10

1.0

5

D D

4

3

2

1

A PL5508

AC
A dapter
in

VIN

L M358
T hermal
P rotector

+ 3VALWP

LDO
( 2.5V)

SWITCHADP_EN#

B+ B+

C C

MAINPWON

ENBL2 ENBL1

T PS51020
D C/DC

VL

+ 3VALWP

VL

( 3V/5V)

VIN

+ 5VALWP

A PL5151
LDO
(3V)

S HDN#

VL

+3VLP 0.1A

+2.5VALWP 0.4A

+5VS

V CC SHDN#

ISL6260&ISL6208

PWR_GD

D C/DC
(CPU_CORE)

B Q24703
C harger

B+

B B

B attery

B ATSELB_A

SLP_S3#

M AX8743
D C/DC
(1.05V/1.5V)

ENBL1/ENBL2

+1.5VSP 4.2A

+1.05V_VCCP 6.4A

C PU_CORE
( 44A)

+5VALWP

S elector
C ircuit

BATSELB_A#

B attery A
8 Cell

B attery B
8 Cell

B+

T PS51116
D C/DC

VCC

+ 1.8VP 7A

(+1.8VP/+0.9VSP)

SWITCH

A A

SWITCHSWITCH

B attery
C onnector
A

B attery
C onnector
B

SLP_S3#/SLP_S5#

S 3/S5

+ 0.9VP 2A

BATT

BATT_A

BATT_B

Title

POWER BLOCK DIAGRAM

S ize Document Number Rev

Date: Sheet of

5

4

3

2

38 52Saturday, January 14, 2006

1

A

1 1

B

C

D

12

PR1
15K_0402_5%

VIN

PJP13

FOX_JPD113E-LB103-7F

2 2

3 3

ADP_SIGNAL

ADPIN

12

PC1

100P_0402_50V8J

12

PC2
1000P_0402_50V7K

PL1

C8B BPH 853025_2P

12

PC3

100P_0402_50V8J

12

PC4

1000P_0402_50V7K

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPAR TMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

B

2005/03/10 2006/03/10

Compal Secret Data

Deciphered Date

C

T itle

Size Document Number R ev

Custom

Date: Sh eet of

Compal Electronics, Inc.

DCIN

LA-2821

D

39 52Saturday, January 14, 2006

A

B

C

D

1 1

2 2

3 3

4 4

47K

PR16 47K_0402_5%

PC10

47P_0402_50V8J

@

RHU002N06_SOT323

SLP_S3#

VIN

PQ6

DTA144EUA_SC70

47K

+3VL

G

@

1N4148_SOD80

D

S

PQ91

PR55
130K_0402_1%

PR62

10K_0603_1%

PC138

PD32

P2

PR44

100K_0603_1%

PR240

2.15K_0402_1%

PR49

12.4K_0603_0.1%

PC26

0.022U_0402_16V7K

PQ4
AO4407_SO8

PR14
200K_0402_5%

0.1U_0603_16V7K

PR20
150K_0402_5%

PD33

1N4148_SOD80

PR376

0_0402_5% @

ACDET

PR67

33K_0402_1%

LMV431ACM5X_SOT23-5

A

ADP_EN# 47

CHGLIM47

CHGCTRL33,41

PR42

330K_0402_5%

VL

PU5A

LM393DG_SO8

PR56
1M_0402_5%

PU5B

LM393DG_SO8

VL

PU6

P2

ACDRV#

PR31
191K_0402_1%

ADP_PRES

PC15

+3VL

PR45

10K_0402_1%

+3VL

AC_CHG

1.24VREF

AO4407_SO8

PR17

1U_0603_6.3V6M

+3VL

PR63

RHU002N06_SOT323

PQ5

0_0402_5%

AC_CHG

ALARM

+3VL

BQ24703VREF

PR35

PC20

100K_0402_1%

PR36

100K_0402_1%

PR41

80.6K_0402_1%

1U_0603_6.3V6M

PC22

0.1U_0402_10V6K

PU4
SN74LVC1G17DBVR_SOT23-5

PC24

0.1U_0402_16V7K @

ADP_PRES 18,25,33,41,42,47

AC_CHG 41

47K_0402_1%@

PQ12

G

D

S

P4

PR372

0.015_2512_1%

PR338
100_0402_1%

PC198

1U_0603_6.3V6M
PR339

1K_0402_1%

PR29

1K_0402_1%

PR32

100K_0402_5%

PC18

4.7U_0805_6.3V6K

+3VL

PR52

4.7K_0402_5%
PR58

100K_0402_5%

BQ24703VREF

D

PQ13

G

S

B+

FBM-L11-322513-151LMAT_1210

ACN 47

PC21

150P_0402_50V8J

PR61
100_0402_5%

RHU002N06_SOT323

B

PL2

PU2

BQ24703_QFN28

PR43
150_0402_1%

PC23

ALARM 41

4.7U_0805_10V6K

BATT

PR33

PL3

0.015_2512_1%

PR38

0.1U_0402_16V7K

P2

PC12

PC11

10U_1206_25VAK

RLZ16B_LL34

ACDRV#

PR15

0_0402_5%

4.7U_1206_25V6K
PD6

PQ3
AO4407_SO8

PC14

1U_0805_25V4Z

DH_CHG

CHG_B+

PR26

0_0402_5%

PQ8
SI4835BDY-T1-E3_SO8

LX_CHG

16UH_SIL104R-160PF_3.6A_30%

PD8
EC31QS04

SE_CHG+

SE_CHG-

CV=16.8V (8 CELLS LI-ION)
C C=3A

BATT BATT

PR47
604K_0603_0.1%

PR51

604K_0402_1%

PR59

75K_0402_1%

PC25

100P_0402_50V8J

PR64

15K_0402_1%

Security Classification

Issued Date

THIS SHEET OF ENGINEERI NG DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATIO N. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUT HORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DIS CLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2005/03/10 2006/03/10

PR50
10K_0603_0.1%

PR57
47K_0603_0.5%

PC205

470P_0402_50V7K

Compal Secret Data

Deciphered Date

C

3K_0402_1%

PC19

PR39

3K_0402_1%

B ATT

PC17

PC16

10U_1206_25VAK

4.7U_1206_25V6K

Compal Electronics, Inc.

Size Document Number Rev

Custom

LA-2821

Charger

D

40 52Saturday, January 14, 2006

A

B

C

D

+3VL

1 1

BATSELB_A

PC28

1000P_0402_50V7K

PR72

+3VL

PQ17

D

RHU002N06_SOT323

G

S

PR70

47K_0402_5%

ALARM40

22K_0402_5%

BATSELB_A#

2 2

PC30

1000P_0402_50V7K

PQ18

RHU002N06_SOT323

PR73

22K_0402_5%

D

G

S

RHU002N06_SOT323

PQ19

D

S

PU8

74LVC1G02_04_SOT353

ADP_PRES 18,25,33,40,42,47

G

+3VL

PU9

SN74LVC1G14DCKR_SC70-5

+3VL

PU10

BATSELB_A#33

BATSELB_A#

BATSELB_A

SN74LVC1G14DCKR_SC70-5

PC197

220P_0402_50V7K

PR82

220K_0402_5%

BATSELB_A#

PR83

470K_0402_5%

+3VL

SN74LVC1G17DBVR_SOT23-5

PU12

AC_CHG40

PR84

10K_0402_1%

RHU002N06_SOT323

ADP_PRES

PQ30

D

S

G

3 3

CHGCTRL33,40

PD14

1N4148_SOD80

PC31

0.22U_0402_10V4Z

+3VL

PD17

CFET_A

4 4

CFET_B

RB715F_SOT323

SN74LVC1G17DBVR_SOT23-5

PR237

PU14

BATCON 33

100K_0402_5%

A

B

PC27

PU7

74LVC1G02_04_SOT353

+3VL

PU11

SN74AHC1G08DCKR_SC70

+3VL

PU13

SN74AHC1G08DCKR_SC70

0.1U_0402_10V6K @

BATT_B

RHU002N06_SOT323

+3VL

BATT_A

PD9

PR68

RB715F_SOT323

PQ16

S

D

100_0402_5%

G

PC29

0.1U_0603_50V4Z

RHU002N06_SOT323

BATT

PR74
470K_0402_5%

PQ21

PD12

PR76

CFET_A

PR78

10K_0402_5%

D

PQ26

BATT_IN

G

RHU002N06_SOT323

S

PR88

10K_0402_5%

CFET_B

PQ34

BATT_IN

D

G

S

Security Classification

Issued Date

THIS SHEET OF ENGINEERI NG DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATIO N. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUT HORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DIS CLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

10K_0402_5%

1N4148_SOD80

D

PQ23

G

RHU002N06_SOT323

S

BATT

PR81
470K_0402_5%

PD16

PR87

10K_0402_5%

1N4148_SOD80

D

PQ31

G

RHU002N06_SOT323

S

RHU002N06_SOT323

2005/03/10 2006/03/10

PR75

PMBT2222A_SOT23-3

470K_0402_5%

PR85

PQ29

PMBT2222A_SOT23-3

Compal Secret Data

470K_0402_5%

Deciphered Date

C

PQ15

D

PR71

1.5M_0402_5%

PD13

B540C_SMC
PQ24

AO4407_SO8

AO4407_SO8

S

G

PQ27

PD15

B540C_SMC

PR69

0_0402_5%

PD11
RLZ6.2C_LL34

RHU002N06_SOT323

BATT_IN

RHU002N06_SOT323

AO4407_SO8

AO4407_SO8

RHU002N06_SOT323

RHU002N06_SOT323

BATT_IN

BATT_IN

PD10
1N4148_SOD80

PQ20

D

G

S

PQ22

D

G

S

PR77

4.7K_0402_5%

PQ25

PR79
470K_0402_5%

BATT_A

PQ28

PR80
470K_0402_5%

BATT_B

PR86

4.7K_0402_5%

PQ32

D

G

S

PQ33

D

G

S

Compal Electronics, Inc.

Size Document Number Rev

Custom

LA-2821

Battery selector

D

41 52Saturday, January 14, 2006

5

4

3

2

1

+5VALWP

+3VALWP

B++

PL4

FBM-L11-322513-151LMAT_1210

B+

PC32

D D

VL

ADP_PRES

G

PQ40

+3VALW_POK

PC40

4.7U_0805_10V6K

PR103

0_0402_5%@

PC46

820P_0603_50V7K

D

S

RHU002N06_SOT323

+3VLP

PR369

100K_0402_5%

RHU002N06_SOT323

PR105

1M_0402_5%@

KBC_PWR_ON33

G

PQ41

PQ42
SI2301BDS-T1-E3_SOT23-3

PR365

100K_0402_5%

G

PQ98

PR101

0_0402_5%

VL

PC42

+5VALWP

PR187
154K_0603_1%

+5VALWP

C C

MAI NPWON46

0.47U_0603_10V7K

VL

PR107

100K_0402_5%

D

PQ39

RHU002N06_SOT323

B B

VL

PC51

1U_0603_10V6K

PU16

APL5151_SOT23-5

VL

PR115

A A

100K_0402_5%

G

S

D

S

PQ101
SI2301BDS-T1-E3_SOT23-3

PC52

1U_0603_10V6K

PC53

0.33U_0603_10V7K@

+3VALW_POK

RHU002N06_SOT323

PR90

49.9K_0402_1%

PR99

10K_0402_1%

PC37

B++

PC41 0.1U_0402_16V7K

PR335
0_0402_5%

PC47

PR106

1M_0402_5%

820P_0603_50V7K

+3VALWP

D

S

4700P_0603_50V7K

330_0402_5%

PR91

PR96

2.7K_0402_1%

4700P_0603_50V7K

PR102

100K_0402_5%

PC48

4700P_0402_25V7K

3.9K_0402_1%

PR110

PU15

PR97

PR98

17.4K_0402_1%

TPS51020DBTR_TSSOP30

PR108

PR109

0_0402_5%

@

29.4K_0402_1%

PR111

PR113

10K_0402_1%

PC35

12.7K_0402_1%

10K_0402_5%

BST_5V

2.2U_1206_25V7K

DH_5V_1

DL_5V

DH_3.3V_1

DL_3.3V

BST_3.3V

0.1U_0603_50V4Z

ADP_PRES 18,25,33, 40,41,47

PC50

3300P_0603_50V7K

PR112

330_0402_5%

PC43

DH_5V_2

PR100

0_0402_5%

PC36

0.1U_0603_50V4Z

LX_3.3V

LX_5V

PR104
0_0402_5%

DH_3.3V_2

PQ37

AO4912_SO8

LX_5V 47

AO4912_SO8

10UH_SIL104R-100PF_4.4A_30%

PQ38

PC33

PC34

10U_1206_25VAK

2200P_0402_50V7K

PL5

PC45

PC44

4.7U_1206_25V6K
2200P_0402_50V7K

PL6

10UH_SIL104R-100PF_4.4A_30%

+

PC39

220U_D3L_6.3M_R40

+

PC199

220U_D3L_6.3M_R40

PC120

@

1500P_0402_50V7K

Security Classification

Issued Date

THIS SHEET OF ENGINEERI NG DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATIO N. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUT HORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DIS CLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/03/10 2006/03/10

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet of

Compal Electronics, Inc.

3.3VALW/5VALW

LA-2821

1

42 52Saturday, January 14, 2006

A

PC189

2200P_0402_50V7K

DH_1.05V_2

DL_1.05V

SLP_S3#

+5VALW

PR342

0_0402_5%

CHP202UPT_SOT323-3

0.1U_0603_50V4Z

PR260

100K_0402_5%

PR343

47K_0402_5%

1 1

PQ79

AO4404_SO8

PL22

+1.05V_VCCP

+

PC191

330U_D2E_2.5VM

2 2

+3VALWP

3 3

3.3UH_PCMB104E-3R3MS_11A_20%

PC145

4.7U_0805_6.3V6K
PR329

5.1K_0402_1%

PR257
100K_0402_1%

PC72

1U_0603_10V6K

PU20

APL 5508-25DC-TRL_SOT89-3

PQ78

AO4702_SO8

(400mA,40mils ,Via NO.= 1)

+2.5VALWP

PC73

4.7U_0805_6.3V6K

SLP_S3#18,21,25,28,29, 33,35,36,40,44

1.5VSP/ +1.05V_VCCP/+2.5VALWP

PC57

4.7U_1206_25V6K

PD31

PC192

PR331
0_0402_5%

PR370

0_0402_5%@

G

D

G

S

RHU002N06_SOT323

PC201

0.001U_0402_50V7M@

B

MAX8743_B+

PR332

PR262

20K_0402_1%

PR263

0_0402_5%

100K_0402_1%

PC147

0.22U_0603_10V7K

+5VALW

PR266

BST_1.5V_2

PR327

0_0402_5%

BST_1.5V_1

DH_1.5V_1

PC186

4.7U_1206_16V4Z

PR328

0_0402_5%

1U_0805_50V4Z

PC190

PR265

0_0402_5%

20_0603_5%

VCC_MAX8743

1U_0805_16V7K

2VREF

PR268

PC195

BST_1.05V_2

PQ94

BST_1.05V_1

PR330

0_0402_5%

PC194

0.1U_0603_50V4Z

PU28

DH_1.05V_1
LX_1.05V LX_1.5V

MAX8743EEI+T_QSOP28~N

VCC_MAX8743

D

S

PQ95

RHU002N06_SOT323

0_0402_5% @

0.1U_0603_50V4Z

PR333
0_0402_5%

0_0402_5%

PR267

100K_0402_1%

PC144

PR319

C

PL23

FBM-L11-322513-151LMAT_1210

AO4912_SO8

PQ86

DL_1.5V

DH_1.5V_2

VCCP_POK 37

D

S

PQ93

RHU002N06_SOT323

RHU002N06_SOT323

PL21

3.3UH_PCMC063T-3R3MN_6A_20%

PR371

0_0402_5%@

G

PQ92

D

S

SLP_S3#

PR259

100K_0402_5%

PR341

47K_0402_5%

G

PC200

0.001U_0402_50V7M@

PR340
0_0402_5%

D

PC188

2200P_0402_50V7K

PR258

PR261

+5VALW

5.1K_0402_1%

10K_0402_1%

PC185

4.7U_1206_25V6K

+

PC203

220U_B2_2.5VM

SLP_S3# 18,21,25,28,29, 33,35,36,40,44

B+

+1. 5VSP

+1.5VSP

+1.8VP

+1.05V_VCCP

4 4

PJP1

PAD-OPEN 3x3m
PJP3

PAD-OPEN 4x4m

PJP5

PAD-OPEN 4x4m

PJP12

PAD-OPEN 4x4m

PJP7

PAD-OPEN 3x3m

+1.5VS

(4A,160mils ,Via NO.=8)

(7A,280mils ,Via NO.= 14)

+1.8V

(6A,240mils ,Via NO.= 12)

+VCCP

(2A,80mils ,Via NO.= 4)

+0.9V+0.9VP

A

+5VALWP

+3VALWP

+3VLP

+2.5VALWP

PJP2

PAD-OPEN 4x4m
PJP4

PAD-OPEN 4x4m

PJP6

PAD-OPEN 2x2m

PJP11

PAD-OPEN 2x2m

B

+5VALW

(4.5A,180mils ,Via NO.= 9)

+3VALW

(3A,120mils ,Via NO.= 6)

(100mA,20mils ,Via NO.= 1)

+3VL

(400mA,40mils ,Via NO.= 1)

+2.5VALW

Security Classification

Issued Date

THIS SHEET OF ENGINEERI NG DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATIO N. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUT HORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DIS CLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2005/03/10 2006/03/10

Compal Secret Data

Deciphered Date

C

Compal Electronics, Inc.

2.5VALW/1.5VS/1.05VCCP

Size Document Number Rev

Custom

LA-2821

D

43 52Saturday, January 14, 2006

5

D D

+1.5VS

12

P R242

0_1206 _5%

12

12

P C127

10U_0805_10V4Z

C C

+0.9VP

V_DDR_MCH_REF7,13,14

12

P C129
22U_1206_6.3V6M

P R324

0_0402_5%

P C128

10U_0805_1 0V4Z

12

+5VALWP

B B

P C130

0.033U_0402_ 16V7K

4

TPS51116_HTSSOP20

3

P U27

BST_1.8V_1 BST_1.8V_2

D H_1.8V_1

P R231

0_0402_5%

P R230

0_0402_5%

LX_1.8V

DL_1.8V

12

P C122

4.7U_0805_1 0V6K

P R234

0_0402_5%

P R314

0_0402_5%

@

P R236

0_0402_5%

P C121

0.1U_0603_50V4Z

D H_1.8V_2

12

P C123

0.001U_0402_ 50V7M

12

P R233

20K_060 3_1%

2

5

D8D7D6D

PQ63

AO4404_SO8

S1S2S3G

4

1.8U_SIL104R-1R8PF_9.5A_30%

5

D8D7D6D

PQ64
AO4702_SO8

S1S2S3G

4

P R232

3_0402_5%

SLP_S5# 21,36

SLP_S4# 21

PL16

DDR_B+

12

P C125

2200P_0402 _50V7K

PL15

FBM-L11-322513-151LMAT_1210

12

P C124
10U_1206_25VAK

1

+

2

P C204

220U_D2_4 VM

+5VALWP

1

B+

+1.8VP

12

P R388
0_0402_5%

@

P R389

0_0402_5%

12

12

14.3K_0603_0.1%
P R238

P C133

22P_0402_ 50V8J

+1.8V

SLP_S3# 18,21,25,28,29,33,35,36,40,43

P R323

0_0402_5%@

SLP_S5# 21,36

12

12

P C136

A A

S ecurity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

2005/03/10 2006/03/10

3

12

P C137

0.001U_0402_ 50V7M

@

Compal Secret Data

Deciphered Date

0.001U_0402_ 50V7M

@

Title

Size Document Number Rev

B

2

D ate: Sheet of

Compal Electronics, Inc.

1.8V/0.9VS

L A-2821

10K_0603_0.1%
P R239

44 52Saturday, January 14, 2006

1

8

7

6

5

4

3

2

1

+CPU_B+

H H

PQ 82

IRF78 32PBF_SO8

PQ83

PC 150

0.01U_0 402_50V4Z

IRF78 32PBF_SO8

PQ80
SI7840DP-T1-E3_SO8

+ 5VS

PR269
10_0603_5%

G G

10_060 3_5%

F F

1U_06 03_10V6K

PC184

NTC

0.01U _0402_16V7K

H_PROCHOT#4

E E

H_DPRSTP#4,20

D D

PGD_IN_137

CLK_ENABLE#15,37

DPR SLPVR7,21

CPU_VID15
CPU_VID25
CPU_VID35
CPU_VID45

CPU_VID65

H_PSI#5

PGD_IN33,37

PWR_GD18,33,36,37,47

PR279

4.22K _0603_1%

0.015U _0402_16V7K

0_0402_5%

0_0402_5%

VCCSENSE5

PR316

100_0402_1%

100_0402_1%

VSSSENSE5

C C

B B

PR298

180_0603_1%

PC179

220P_0402_25V8K

PR277

0_0402_5%

PR278

147K_0402_1%

PH2

470KB_0402_5%_ERTJ0EV474J

PR283

PR284

PR285

PR286

0_0402_5%

PR289

0_0402_5%

1800P _0402_50V7K

PR292

0_0402_5%

0_0402_5%

1000P_0402_50V7K

PC173

PC176

0.022U _0402_16V7K

PR294

1.2K_0402_1%

1000P_0402_50V7K
PR307

PR281

0_0402_5%

PR291

499_0402_1%

PR296

0_0402_5%

PC167

1000P _0402_50V7K

PR304

51K_0603_1%

PC180

NTC

PR299

6.19K_0603_1%

0.01U _0402_25V7K
PC 156

PU31

1K_0402_1%

PC183

330P_0402_50V7K

+3VS

1.91K _0603_1%

PR326
0_0402_5%

ISL6260CRZ-T_QFN40

I SEN1

I SEN2

PR 303

4.53K _0402_1%

VO

VGATE_INTEL 7,21

0_0402_5%

0.22U_ 0603_16V7K

PC 182

+ 5VS

PC 177

1000P_ 0402_50V7K

0.1U_ 0402_16V7K

PR297

PR 301

PH3

@

10KB_0603 _5%_ERTJ1VR103J

1U_06 03_10V6K

ISL6208CRZ-T_QFN8

+5VS

PC1 63

1U_06 03_10V6K

PU32

PR270

0_0402_5%

BST _CPU1_1

LX _CPU1

PR280

0_0402_5%

BST _CPU2_1

DH_CPU2
LX _CPU2PWM2

PC155

0.22U _0603_16V7K

DL_ CPU2

IRF78 32PBF_SO8

IRF78 32PBF_SO8

PC 153

PC 152

PC1 51

10U_1 206_25VAK

10U_1 206_25VAK

2200P_ 0402_50V7K

0.36UH_MPC1040LR36_24A_20%

10K_0402_1%

PR274

5.11K _0402_1%

V SUM

PC 162

PC 161

PC 160

10U_1 206_25VAK

10U_1 206_25VAK

0.36UH_MPC1040LR36_24A_20%

10K_0402_1%

PR293

5.11K_0402_1%

PL24

FBMA-L18- 453215-900LMA90T_1812

+

PL19

PC166

PR318

0_0402_5%

PR271
10_0402_1%

VO

PC157

0.22U_0603_16V7K

PR317

@

+CPU_B+

PL20

PR290

0.22U_0603_16V7K

PC 196

68U_ 25V_M

PR287

+VCC_CORE

A A

8

7

6

5

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PART Y WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4

2005/03/10 2006/03/10

Compal Secret Data

Deciphered Date

3

Compal Electronics, Inc.

LA-2821

2

CPU_ CORE

1

45 52Saturday, January 14, 2006

A

1 1

PCN2

EC_SMD_A

EC_SMC_A

TYCO_C-1746706_6P

12

PR186
1K_ 0402_5%

12

PR189

100_0402_5%

12

PR188

100_0402_5%

2 2

PD27

@SM05_SOT23

EC_SMD_A1

EC_SMC_A1

PR334
330K_0402_5%@

2

3

1

THM_MAIN# 33

PD26
SM24_SOT23 @

B

VMB_A

PL13

FBMA-L18-453215-900LMA90T_1812

12

PC104
1000P_0402_50V7K

AB1A_ DATA 33

AB1A_CLK 33

12

PC105

0.01U_0402_50V4Z

0.22U_0603_10V7K

BATT_A

PC107

C

PH1 under CPU botten side :

CPU thermal protection at 90 +-3 degree C
Recovery at 43 +-3 degree C

PR185

47K_0402_1%

CPU

12

+5VALW

12

PH1

+5VALW

12

PR192

2.55K_0603_1%

10K_TH11 -3H103FT_0603_1%

PR190
15K_0603_1%

PR191
150K_0402_1%

PR193

150K_0402_1%

12

12

PC108
1000P_0402_50V7K

8

PU21B

P
G

LM358ADR_SO8

4

G

D

D

13

S

PQ56
RHU002N06_SOT323

+5VALW

12

PC1 06

0.1U_0402_10V6K

8

PU21A

P
G

LM358ADR_SO8

4

MAINPWON 42

VMB_B

PCN3

EC_SMD_B
EC_SMC_B

AB/I_B
TS_B

SUYIN_20163S-06G1-K

3 3

12

PR200

100_0402_5%

4 4

12

PR201

100_0402_5%

1K_ 0402_5%

PR197
1K_ 0402_5%

1 2

@SM05_SOT23

EC_SMC_B1

PR194

PD20

EC_SMD_B1

PR195

210K_0402_1%

+3VL

2

3

PD19
SM24_SOT23 @

1

PL14

FBMA-L18-453215-900LMA90T_1812

12

PC109
1000P_0402_50V7K

THM_MBAY# 33

AB1B_ DATA 33

AB1B_CLK 33

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPAR TMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

B

BATT_B

12

PC110

0.01U_0402_50V4Z

2005/03/10 2006/03/10

Compal Secret Data

Deciphered Date

C

T itle

Size Document Number R ev

Custom

Date: Sh eet of

Compal Electronics, Inc.

BATTERY CONN

LA-2821

D

46 52Saturday, January 14, 2006

5

D D

8

PU24A

PR210

1 2

0_0402_5%

P

G

LM358ADR_SO8

4

PR209

12

0_0402_5%

P4

10K_0402_1%

PR213

PR211

6.81K_0402_1%

12

PC1 18

1U_0805_50V4Z

C C

12

PC119

0.1U_0402_16V7K

12

PR226
0_0402_5%

PQ96

NDS0 610_SOT23

S

12

PR382

29.4 K_0402_1%

D

D

13

@

S

S

@

D

G

2

1M_0402_5%

8

4

68K_0402_5%

@

G

PQ106
RHU002N06_SOT323

B+

ADP_SIGNAL

B B

12

PR344
100K_0402_1%

PR346
1M_0402_5%

12

PR345
10K_0603_1%

12

PR3 79

A A

442K_0402_1%@

D

13

G

S

PQ103

@

RHU002N06_SOT323

12

D

13

PR3 67

0_0402_5%

S

MXM_CD1# 18,21

PQ100

@

RHU002N06_SOT323

G

5

VIN

12

12

PR3 48

100K_0402_1%

PR349

10K_ 0402_1%

RHU002N06_SOT323@

PR347
226K_0402_1%

12

VIN

12

PR381

40.2K_0402_1%

12

G

PQ104

PR391
287K_0402_1%

12

PR3 86

13

4

PR214

100K_ 0603_0.5%

LMV431ACM5X_SOT23-5

ADP_ PRES 18,25,33,40,41,42

PR373

124K_0402_1%

VIN

8

PU33A

P
G

LM393DG_SO8

4

PR350

PU33B

P
G

LM393DG_SO8

+3VALW

12

4

PC116

0.22U_0603_16V7K

PU26

C

PQ102

B

MMBT3904_SOT23

E

3 1

VIN

PR3 51

47K_ 0402_5%

PD34

1N4148_SOD80

ADP_ EN# 40

8

PU24B

P
G

LM358ADR_SO8

4

12

PR2 20

12

PR2 22

12

PR354
10K_0402_5%

12

PR352
220K_0402_5%

12

PR368

3

+3VS

PR377

10K_0402_5%

12

PR390
47K_0402_5%

12

PC207
1U_0603_10V6K

12

PR207
133K_0402_1%

12

PR218

G

PR355

470K_0402_5%

PR251

330K_0402_5%

8

PU25B

PR212
0_0402_5%

MMBT3906_SOT23

7.87K_0402_1%

422_0603_1%

PQ59

PR216

2K_ 0402_5%

B

12

E

1 3

C

12

PR252

3.9K_ 0402_5%

12

PR2 49

PD38

CH355PT_SOD323-2

+3VALW

ADP_ ID 33

12

PR353
47K_ 0402_5%

ADP_ EN 33

D

13

PQ97

G

RHU002N06_SOT323

S

220K_0402_5%

3.9K_0402_5%

PR224

100K_0402_5%

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPAR TMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

P
G

LM393DG_SO8

4

PR206

0_0402_5%

CH751H-40PT_SOD323-2@

PWR_GD 18,33,36,37,45

12

PC206
3900P_0402_50V7K

CHGLIM40

B

E

2005/03/10 2006/03/10

12

PD30

PR227

1 2

470K_0402_5%

ACN 40

PR225
100K_0402_5%

@

1 2

C

PQ62

MMBT3904_SOT23

3 1

Compal Secret Data

Deciphered Date

12

80.6 K_0402_1%

PC1 17

PR223

0_0402_5%

D

13

PQ61
RHU002N06_SOT323

S

+3VS

12

PR356

71.5 K_0402_1%

12

PR357
21K_ 0402_1%

12

PR358

3.48K_0402_1%

2

+5VS

8

4

0.027U_0603_16V7K

12

2

PC202

0.1U_0805_50V7M

PR208

100K_0402_5%

PU25A

P
G

LM393DG_SO8

PR217
604K_0603_1%

OCP# 4,21

ACOCP_EN#35

1

PQ105

+3VS

+3VS

12

PR363
10K_0402_5%

+3VS

12

PR364
10K_0402_5%

NDS0 610_SOT23

D

PR387

220K_0402_5%

LX_5V 42

ADP_PRES18,25,33,40,41,42

ADP_ PS0 33

ADP_ PS1 33

47 52Saturday, January 14, 2006

CH751H-40PT_SOD323-2

+5VS

12

PR378
10K_ 0402_5%

VIN

47K

PR3 85

PR380

1K_ 0402_5%

1M_0402_5%

PR359

10K_0402_5%

PR361

21K_0402_1%

1M_0402_5%

T itle

Size Document Number R ev

Custom

LA-2821

Date: Sh eet of

PD21

CH751H-40PT_SOD323-2

PQ108

DTA144EUA_SC70

47K

12
2
12

PR3 83

221K_0603_1%

PD37
1N4148_SOD80

1 2

PR362

ADP_SIGNAL

PD35

1N4148_SOD80

+5VS

8

PU34A

P
G

LM393DG_SO8

4

+5VS

8

PU34B

P
G

LM393DG_SO8

4

150K_0402_5%

PR360

PD22

12

PC1 15

1U_0805_16V7K

12

PR221
10_0402_5%

Compal Electronics, Inc.

ADP_OCP

1

S

G

2

12

12

PD36

CH355PT_SOD323-2

1 2

D

13

G

S

+5VS

PR384

220K_0402_5%

PQ107

RHU002N0 6_SOT323

1

EAL80 from Pre DB-1 Step to DB-1 Step LA-2821 REV:0.0 -> 0.1 Modify <94.03.26.~94.04.08. >

1. Change +0.9V discharge circuit control signal fr om SLP_S3 to SLP_S5. <Page 36> 94.03.26.

-Change Q27.2(2N7002) connection from SLP_S3 to SLP_S5. (Modify CKT&La yout)

2. Just reserve a test pad for TPM_GPIO directly. <Page 32> 94.03.28.

-Del R1248 and connect TP62 to JP33.8 directly. (Modify CKT& Layout)

3. Change TPM1.2 +3VL Power Rail to +3VALW by Custo mer request. <Page 32> 94.03.28.

-Change +3VL that connects to R1242.1 to +3VALW. (Modify CKT&L ayout)

1 1

4. Correct U25.39/38's net name from CLK_PCIE_NC/NC# to PCIE_NC/NC# . <Page 15> 94.03.28.

- Change U25.39/38 connection from CLK_PCIE_NC/CLK_PCIE_NC# to PCIE_NC/PCIE_NC#. (Modify CKT&Layout)

5. Change the RC parts for POK Time delay request. <Page 37> 94.03.29.

- Change R117 from 100K_0402_5% to 150K_0402_1%. (Modify CKT&BOM)

-Change C87 from 0.1U_0402 to 0.47U_0603_X7R. (Modify CKT,BOM&Layou t)

6. Update the PCI7611MLS/PCI7612 related schematic by Vendor recommend. <Page 23,24> 94.03.29.

-Change R93,R97 from 7612@0_0402 to 0_0402; R103 from 7611@0_0402 to @0_0402. (Modify CKT&B OM)

-Add R1308(0_0402) between U42.K3 and U42.K5; change R106 from 0_0402 to @0_0402. (Modify CKT,BOM &Layout)

-Change R1299 from 43K_0402 to @43K_0402. (Modify CKT&BOM)

7. Reserve a 68UF Cap. by LAN Chip Vendor request. <Page 25> 94.03.29.

-Reserve C976(@68U_B2_4VM) close to U6.M14. (Modify CKT,BOM&Layout)

8. Reserve two resistors(@0_0402) to isolate VGATE and VG ATE_INTEL. <Page 37> 94.03.29.

-Reserve R1306(@0_0402) between PU31.40 and U45.2. (Modify CKT,BOM&Layo ut)

-Reserve R1307(@0_0402) between U48.4 and PR326.2. (Modify CKT,BOM&Layo ut)

9. Change Calistoga LVDS function power source to GND for di sabling by customer recommend. <Page 10> 94.03.29.

-Change U15.B30/C30/A30 connection from +2.5VS to GND. (Modify CKT&La yout)

2 2

-Change U15.A28/B28/C28 connection from +1.5VS to GND. (Modify CKT&La yout)

10. Remove DPRSLPVR Pull-down resistor by customer recommend. <Page 21> 94.03.29.

2

3

4

5

24. Remove the R1153 2.2Kohm pull-high resistor for lever age AF1.0 CFG9 setup. <Page 11> 94.04.01.

-Remove R1153(@2.2K_0402). (Modify CKT&BOM)

25. Add net name for USB signals layout rule create. <Page 30> 94.04.04.

-Add net names USB20_N1_R, USB20_P1_R, USB20_N4_R, USB20_P4_R, USB20_HUB_N1_R,
USB20_HUB_P1_R on JP16.6/7/2/3 JP22.4/3. (Modify CKT&Layo ut)

26. Remove the R555,R612 8.2Kohm pull-high resistors because the signals be double pulled up.
<Page 18> 94.04.04.

4th Netin

-Remove R555,R612(@8.2K_0402). (Modify CKT&BOM)

27. Reserve Audio mute control signals on KBC to lev erage AF1.0 designing. <Page 33> 94.04.04.

-Reserve R140,R141(@0_0402) onU47.57/56 for EAPD/A_SD. (Modify CKT&Layou t)

28. Correct net name for USB signals layout rule create. <Page 29,35> 94.04.04.

-Correct net names to USB20_N2_R, USB20_P2_R, USB20_N3_R, USB20_P3_R, USB20_N6_R,
USB20_P6_R, USB20_N7_R, USB20_P7_R, on JP27.1/2/4/5 JP30.2/4/6/8. (Modify CKT&La yout)

29. Add (NC@0_0402) to connect CP_USB# and NC_CPPE# f or New Card function usage. <Page 24>

94.04.04.

-Add R1316(NC@0_0402) to connect CP_USB# and NC_CPPE#. (Modify CKT,BOM&Layout)

- Change R1272,R1273 from @10K_0402 to @100K_0402. (Modify CKT&BOM)

30. Del JP39.157's ADP_PRES connection to leverage AF1.0 an d standard MXM pin definition. <Page 18>

94.04.04.

5th Netin

-Del JP39.157's ADP_PRES connection. (Modify CKT&Layou t)

31. Reserve the circuit to control the mute to block the speaker pop on power up by customer recommend.
<Page 29> 94.04.04.

-Reserve D59(@RB751V), R613(@1M_0402), R431(@10K_0402), C93(@2.2U_0805), R439(@10K_0402),
R438(@10_0402) and the related circuit on U39.19. (Modify CKT,BOM& Layout)

-Change R1015 from 100K_0402_5% to @100K_0402_5%. (Modify CKT&BOM)

11. Stuff SPI related function Pull-High resistors by customer/Intel recommend. <Page 21,32> 94.03.29.

-Change R1284~R1286 from @10K_0402_5% to 10K_0402_5%. (Modify CKT&BOM)

12. Reserve 0 ohm resistor for PM_EXTTS#1 and DPRSLPVR connection by Customer/Intel recommend. <Page 7,21>

94.03.29.

-Reserve R1309(@0_0402_5%) between PM_EXTTS#1 and DPRSLPVR connection. (Modify CKT&Layout)

13. Add +1.8V discharge circuit. <Page 36> 94.03.30.

-Add R1310(470_0402_5%) and Q90(2N7002_SOT23) for +1.8V discharge schematic related. (Modify CKT,BOM&Layout)

14. Change ICH7 HD function power source to +3VS for wake on ring function from Azalia modem disabling by
customer recommend. <Pag e 22> 94.03.30.

-Change U26.R7 connection from +3VALW to +3VS. (Modify CKT&Layout)

15. Change TPM1.2 +3VL Power Rail to +3VALW by Custo mer request. <Page 32> 94.03.30.

-Change +3VL that connects to C193.1 to +3VALW. (Modify CKT&L ayout)

16. Update ICH7M HD Audio, Codec Chip and MDC related Schematic. <Page 20,34,36> 94.03.30.

3 3

-Add R1313,R1314,R1315(33_0402) for ICH7/MDC/Codec related update. (Modify CKT,BOM&Layout)

-Create net name AC97_RST#_MDC, AC97_RST#_CODEC, AC97_SYNC_MDC, AC97_SYNC_CODEC,
AC97_SDOUT_MDC, AC97_SDOUT_CODEC, AC97_BITCLK_MDC, AC97_BITCLK_CODEC, AC97_SDIN0_CODEC,
AC97_SDIN1_MDC for ICH7/MDC/Codec related update. (Modify CKT&Layou t)

17. Reserve 0ohm option resistors for +0.9V discharge circuit co ntrol signal SLP_S3 and SLP_S5 selecting . <Page 36>

94.03.30.

-Reserve R1311(@0_0402) to connect SLP_S5 to Q27.2. (Modify CKT&Layout)

Gerber Out 4/14

-Add R1312(0_0402) to connect SLP_S3 to Q27.2. (Modify CKT,BOM&La yout)

18. Populate the 68UF Cap. and reserve 10UF Cap. by LAN Chip Vendor/Customer request. <Page 25> 94.03.30.

-Change C976 from @68U_B2_4VM to 68U_B2_4VM, remove C243(@10U_1206_6.3V). (Modify CKT&BOM)

19. Swapping DDR2 SO-DIMM Data Group pin definition for Layout routing smoothly. <Page 13,14> 94.03.31.

-Swapping JP34 and JP10 Data Group pin definition. (Modify CKT&Layout)
3th Netin

20. Correct Calistoga chip power pin connection base on CRB Rev:1.301 recommend. <Page 11> 94.04.01.

-Disconnect U15.AV1 and U15.AJ1 to +1.8V and modify the related schematic. (Modify C KT&Layout)

-Change U15.AT41/AM41 net name from MCH_AT41/MCH_AM41 to VCCSM_LF4/VCCSM_LF5. (Modify CKT&Layout)

4 4

21. Change C899~C930 from 10U_1206_X5R to 10U_00805_X5R to meet Intel N apa ESL request. <Page 6> 94.04.01.

-Change C899~C930 from 10U_1206_X5R to 10U_00805_X5R. (Modify CKT,BOM&Layout)

22. Change C940~C945 from 0.1U_0402_Y5V to 0.1U_0402_X5R to meet Int el request, avoid thermal risk. <Page 6>

94.04.01.

- Change C940~C945 from 0.1U_0402_Y5V to 0.1U_0402_X5R. (Modify CKT&BOM)

23. Update ICS954306 PCB Footprint for Layout routing. <Page 15> 94.04.01.

- Change U25 PCB Footprint from ICS954306_TSSOP64 to ICS954306BGLFT_TSSOP64.

(M odify CKT,BOM&Layout)

1

2

Security Classification

Issued Date

THIS SHEET OF ENGINEERI NG DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATIO N. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUT HORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DIS CLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/03/10 2006/03/10

Compal Secret Data

Deciphered Date

4

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

H/W2 EE Dept. PIR SHEET(1)

LA-2821P

48 52Saturday, January 14, 2006

5

1.0

1

EAL80 from DB-1 Step to DB-2 Step LA-2821 REV:0.1 -> 0.2 Modify <94.05.10.~94.05.27. >

1. Change HDD I/F from PATA to SATA. <Page 20> 94.05.10.

-Change U26.AF18 from NC to IDE_LED#. (Modify CKT&Layou t)

-Change U26.AF3 from GND to SATA_RXN0_C. (Modify CKT&Layout)

- Change U26.AE3 from GND to SATA_RXP0_C. (Modify CKT&Layout)

- Change U26.AG2 from NC to SATA_TXN0_C. (Modify CKT&Layout)

- Change U26.AH2 from NC to SATA_TXP0_C. (Modify CKT&Layout)

1 1

-Add R1256(24.9_0402_1%) between U26.AH10/AG10 and GND. (Modify CKT,BOM&Layou t)

-Del R1326,R1327(NOSATA@0_0402). (Modify CKT,BOM&Layout)

-Add JP45, C955~C958(3900P_0402) and related schematic for SATA connector. (Modify CKT,BOM&La yout)

2. Remove R1294(1K_0402) Pull-High to +3VS to avoid do uble Pull-High risk. <Page 20> 94.05.10.

-Remove R1294(@1K_0402). (Modify CKT&BOM)

3. Add the accelerometer device LIS3LV02DQ and modify the rela ted schematic . <Page 02,21,27,33> 94.05.11.

-Add U64(LIS3LV02DQ_QFN28),R1355(0_0805_5%),R1356(0_0603_5%),R1357~R1361(0_0402_5%),

R1362(10K_0402_5%),C994(0.01U_0402_16V7K),C995(0.1U_0402_16V4Z) and C996(4.7U_0805_10V4Z)
at the center of the system . (Modify CKT,BOM& Layout)

-Add R1364(0_0402_5%) between "ACCEL_INT#" and U26.E20(SB_GPIO9); Reserve R1363(@0_0402_5%) between

"ADP_PWRID" and U26.E20(SB_GPIO9) . (Modify CKT,BOM&Layout)

-Reserve R1354(@0_0402_5%) between "ACCEL_INT#" and U47.34(KBC_GPIO23) . (Modify CKT,BOM&Layout)

4. Change USB port assignments as customer request . <Page 02,21,24,30,32> 94.05.11.

-Change R1317(NC@0_0402_5%) connection Net from "USB20_P0_HUB" to "USB20_P1_HUB" and from "USB20_P0" to

" USB20_P1" . (Modify CKT&Layout)

-Change R1318(NC@0_0402_5%) connection Net from "USB20_N0_HUB" to "USB20_N1_HUB" and from "USB20_N0" to

2 2

" USB20_N1" . (Modify CKT&Layout)

-Change R562(0_0402_5%) connection Net from "USB20_HUB_P1_R" to "USB20_P0_R" and from "USB20_HUB_P1" to

" USB20_P0" . (Modify CKT&Layout)

-Change R586(0_0402_5%) connection Net from "USB20_HUB_N1_R" to "USB20_N0_R" and from "USB20_HUB_N1" to

" USB20_N0" . (Modify CKT&Layout)

-Change R983(NONC@0_0402_5%) connection Net from "USB20_P0" to "USB20_P1" . (Modify CKT&Layout)

-Change R982(NONC@0_0402_5%) connection Net from "USB20_N0" to "USB20_N1" . (Modify CKT&Layout)

-Change R1335(0_0402_5%) connection Net from "USB20_HUB_P2_R" to "USB20_HUB_P1_R" and from

"USB20_HUB_P2" to "USB20_HUB_P1" . (Modify CKT&Layout)

-Change R1334(0_0402_5%) connection Net from "USB20_HUB_N2_R" to "USB20_HUB_N1_R" and from

"USB20_HUB_N2" to "USB20_HUB_N1" . (Modify CKT&Layout)

-Change R1276(NC@0_0402_5%) connection Net from "USB20_P5_R" to "USB20_HUB_P2_R" and from

"U SB20_P5" to "USB20_HUB_P2" . (Modify CKT&Layout)

-Change R1274(NC@0_0402_5%) connection Net from "USB20_N5_R" to "USB20_HUB_N2_R" and from

"USB20_N5" to "USB20_HUB_N2" . (Modify CKT&Layout)

-Change R607(0_0402_5%),D51.3 connection Net from "USB20_P1_R" to "USB20_P5_R" and fro m

3 3

"USB20_P1" to "USB20_P5" . (Modify CKT&Layout)

-Change R606(0_0402_5%),D51.2 connection Net from "USB20_N1_R" to "USB20_N5_R" and from

"U SB20_N1" to "USB20_N5" . (Modify CKT&Layout)

-Change U53(NC@USB2502) pin15 connection from Net "USB_OC#0" to "USB_OC#1" . (Modify CKT&Layout)

-Change U41(TPS2041B) pin5 connection from Net "USB_OC#1" to "USB_OC#5" . (Modify CKT&Layout)

5. Change PCIE port assignments as customer request . <Page 02,21,24,25,27,35> 94.05.12.

-Change U26.K26/K25/J28/J27 to NC . (Modify CKT&Layout)

-Change C712 connection from PCIE_C_TXN3 to PCIE_C_TXN4 ; from PCIE_TXN3 to PCIE_TXN4 . (Modify CKT&Layo ut)

-Change C713 connection from PCIE_C_TXP3 to PCIE_C_TXP4 ; from PCIE_TXP3 to PCIE_TXP4 . (Modify CKT&La yout)

-Change C952 connection from PCIE_C_TXN4 to PCIE_C_TXN5 ; from PCIE_TXN4 to PCIE_TXN5 . (Modify CKT&Layo ut)

-Change C953 connection from PCIE_C_TXP4 to PCIE_C_TXP5 ; from PCIE_TXP4 to PCIE_TXP5 . (Modify CKT&La yout)

-Change C959 connection from PCIE_C_RXN3 to PCIE_C_RXN4 ; from PCIE_RXN3 to PCIE_RXN4 . (Modify CKT&Layo ut)

-Change C960 connection from PCIE_C_RXP3 to PCIE_C_RXP4 ; from PCIE_RXP3 to PCIE_RXP4 . (Modify CKT&La yout)

-Change JP9.A24 connection from PCIE_TXN3 to PCIE_TXN4 . (Modify CKT&Layout)

-Change JP9.A25 connection from PCIE_TXP3 to PCIE_TXP4 . (Modify CKT&La yout)

-Change R1347 connection from PCIE_C_RXN4 to PCIE_C_RXN5 ; from PCIE_RXN4 to PCIE_RXN5 . (Modify CKT&Layo ut)

4 4

-Change R1346 connection from PCIE_C_RXP4 to PCIE_C_RXP5 ; from PCIE_RXP4 to PCIE_RXP5 . (Modify CKT&La yout)

-Change JP30.151 connection from PCIE_TXN4 to PCIE_TXN5 . (Modify CKT&Layout)

-Change JP30.149 connection from PCIE_TXP4 to PCIE_TXP5 . (Modify CKT&La yout)

1

2

3

4

5

6. Change SRC clock assignments as customer request . <Page 15> 94.05.13.

- Change U25.20 connection from "MCH_3GPLL" to "PCIE_LOM". (Modify CKT&Layout)

- Change U25.21 connection from "MCH_3GPLL#" to "PCIE_LOM#". (Modify CKT&Layout)

-Change U25.22 connection from "PCIE_LOM" to "PCIE_NC". (Modify CKT&Layout)

-Change U25.23 connection from "PCIE_LOM#" to "PCIE_NC#". (Modify CKT&Layout)

-Change U25.26 connection from "PCIE_MCARD" to "PCIE_DOCK". (Modify CKT&Layout)

-Change U25.27 connection from "PCIE_MCARD#" to "PCIE_DOCK#". (Modify CKT&Layout)

-Change U25.37 connection from "PCIE_DOCK" to "MCH_3GPLL". (Modify CKT&Layout)

-Change U25.36 connection from "PCIE_DOCK#" to "MCH_3GPLL#". (Modify CKT&Layout)

- Change U25.39 connection from "PCIE_NC" to "PCIE_MCARD". (Modify CKT&Layout)

- Change U25.38 connection from "PCIE_NC#" to "PCIE_MCARD#". (Modify CKT&Layout)

7. Change CLKREQ assignments as customer request . <Page 07,15,24,27> 94.05.13.

-Change R1344.2 connection from "CLKREQB#" to "CLKREQC#". (Modify CKT&Layout)

- Change R1279.1/R1280.1/C961.1 connection from "CLKREQD#" to "CLKREQA#". (Modify CKT&Layout)

-Change R1336 connection from "CLKREQB#" to "CLKREQD#"; from "CLKREQB#_MC" to "CLKREQD#_MC".
( Modify CKT&Layout)

-Add R1120(NOXDP@10K_0402) from net "CLKREQC#" to +3VS pull-high . (Modify CKT,BOM&Layou t)

-Change R1142 from NOXDP@10K_0402 to NOXDP@0_0402 . (Modify CKT&BOM)

-Add R1147(NOXDP@10K_0402) from net "CLKREQD#" to +3VS pull-high . (Modify CKT,BOM&Layou t)

-Change R1254 from NOXDP@10K_0402 to NOXDP@0_0402 . (Modify CKT&BOM)

-Change R1106(10K_0402) connection from +3VS pull-high to between CLKREQB# and CPPE# .
( Modify CKT&Layout)

8. Reserve test Mini-Card that supports USB interface as customer request . <Page 27,32> 94.05.13.

-Add R1365(@0_0402) between JP38.2 and JP44.36 . (Modify CKT&L ayout)

-Add R1366(@0_0402) between JP38.3 andto JP44.38 . (Modify CKT& Layout)

9. Del R1344 & R1336 and short directly because of dou ble reserved . <Page 07,27> 94.05.16.

-Del R1344(@0_0402_5%) and short directly . (Modify CKT&La yout)

-Del R1336(0_0402_5%) and short directly . (Modify CKT,BOM&La yout)

10. Update LAN Controller schematic related caused by ch ipset changed from BCM5751M to BCM5753M .
<Page 25,26> 94.05.16.

-Update the related schematic. (Modify CKT&La yout)

-Change R275,R289 from 47K_0402 to 1K_0402 . (Modify CKT,BOM&Layout)

-Change R276 from 4.7K_0402 to 1K_0402 . (Modify CKT,BOM&La yout)

-Add R1370,R1371(0_0402) and reserve R1372,R1373(@2.2K_0402),Q92,Q93(@2N7002) for SMBus
connection . (Modify CKT,BOM&Layout)

-Add R1367(1K_0402) from U6.H12 to +3VS . (Modify CKT,BOM&Layout)

11. Remove U37,D32,R504, and C577. Remove CLKREQA# connect ion from NIC to CK clock by customer
recommend . <Page 25> 94.05.16.

-Remove U37,D32,R504, and C577 . (Modify CKT,BOM&Layout)

12. Update Accelerometer related schematic by Vendor S TMicro recommend . <Page 27> 94.05.16.

-Remove C994(@0.01U_0402), Change C996 from 4.7U_0805 to 10U_0805 . (Modify CKT,BOM&Layou t)

13. Modify ICH7 Power_OK connection to be able to be enable same as NB . <Page 21> 94.05.16.

-Add R1368(0_0402) and reserve R1369(@0_0402) for U26.AD22 connection . (Modify CKT,BOM&Layout)

14. Swap RP11,RP13 pin connection for DDR2 shift trace routing issue improving . <Page 14> 94.05.16.

-Change RP11.2 connection from DDR_B_MA11 to DDR_CKE3_DIMMB . (Modify CKT&Layout)

-Change RP11.1 connection from DDR_CKE3_DIMMB to DDR_B_MA7 . (Modify CKT&Layout)

- Change RP13.2 connection from DDR_B_MA6 to DDR_B_MA11 . (Modify CKT&Layout)

- Change RP13.1 connection from DDR_B_MA7 to DDR_B_MA6 . (Modify CKT&Layout)
1st Netin

15. Update the SATA supported related . <Page 20> 94.05.17.

-Delete JP23,R458,R1324,R1325,R300 . (Modify CKT,BOM&Layout)

-Add C997(10U_0805),C998~C1000(0.1U_0402) close to JP45 +3VS pins . (Modify CKT,BOM&Layo ut)

16. Dual design SPI ROM for SOP8-150mil/200mil package . <Page 32> 94.05.17.

- Add U65(SPI@SST25LF080A-200mil) . (Modify CKT,BOM&Layout)

17. TPM1.2 on board designing reserve related . <Page 32> 94.05.17.

-Add U66(TPM1.2@SLB9635TT),C1001~C1004(0.1U_0402),C1005,C1006(18P_0402),Y8(32.768KHz),

R1375~R1381 and related schematic update . (Modify CKT,BOM&Layout)

2nd Netin

Security Classification

Issued Date

THIS SHEET OF ENGINEERI NG DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATIO N. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUT HORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

2

MAY BE USED BY OR DIS CLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/03/10 2006/03/10

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

4

Date: Sheet of

Compal Electronics, Inc.

H/W2 EE Dept. PIR SHEET(2)

LA-2821P

49 52Saturday, January 14, 2006

5

1.0

1

EAL80 from DB-1 Step to DB-2 Step LA-2821 REV:0.1 -> 0.2 Modify <94.05.10.~94.05.27. >

18. Update TPM1.2 on board designing schematic. <Page 32,36> 94.05.18.

-Change pin5 (VSB) to +3VALW and move C1004 to connect to pin5 . (Modify CK T&Layout)

-Delete SMBus connection with R1380,R1381 on U66.2 & U66.6; Connect U66.6 to JP33.8, U66.2 to T87 .
(M odify CKT,BOM&Layout)

-Delete +3V power from JP33.4 . (Modify CKT& Layout)

-Delete +3V power reserved schematic and parts include Q91,C977,C978 . (Modify CKT,BOM &Layout)

1 1

19. Add DC/DC schematic about +2.5VALW to +2.5VS for power sequence fail issue fixed. <Page 36> 94.05.18.

- Add U67(SI4800DY_SO8),C1007,C1008,C1009 . (Modify CKT,BOM&Layout)

20. Delete MDC 1.0 Connector reserved related to save layout space . <Page 34> 94.05.18.

-Del JP25(MDC1.0 Conn),C13(0.1U_0402) . (Modify CKT,BOM&Layout)

21. Change the power source designing from +3VALW to +3VS f or DB-2 LS-2712 issue fixed . <Page 34> 94.05.18.

-Change JP18.1 and JP18.3 connection from +3VALW to +3VS . (Modify CKT& Layout)

22. Change the ICH7 RTC Cap. Value for SVTP measure f ail issue fixed . <Page 20> 94.05.19.

-Change C516,C528 from 18P_0402 to 10P_0402 . (Modify CKT&B OM)

23. Update LAN chip schematic related by cust omer recommend . <Page 25> 94.05.19.

-Change R275,R289 from 1K_0402 to @1K_0402 . (Modify CKT&BOM)

-Del D32,R504,C577,U37 . (Modify CKT,BOM&Layout)

-Add R1380(0_0402) and reserve R1381(@0_0402) . (Modify CKT,BOM&Layout)

-Del C40,C45,C53,C62,C64 for +3VS power rail cancel . (Modify CKT,BOM &Layout)

24. Update KBC related designing by customer recommend . <Page 33> 94.05.20.

-Add ADP_EN to S_CLK(GPIO22) by R1385(0_0402) . (Modify CKT,BOM&Layout)

2 2

-Add ADP_ID to EC_GPIO19 by R1382(0_0402) . (Modify CKT,BOM&Layou t)

-Add ADP_PS1 to EC_GPIO12 by R1383(0_0402) . (Modify CKT,BOM&Layou t)

-Add ADP_PS0 to EC_GPIO10 by R1384(0_0402) . (Modify CKT,BOM&Layou t)

-Remove R87(@0_0402) . (Modify CKT&BOM)

25. Update ICH7 related designing by customer recommend . <Page 21,35> 94.05.20.

- Change R1363 from 0_0402 to ACCEL@0_0402 . (Modify CKT&BOM)

-Change R1363.2 connection from ADP_PWRID to ADP_ID . (Modify CKT&Layo ut)

- Reserve R1386(@0_0402) from PREP2# to U26.AD20(ICH7_GPIO38) . (Modify CKT&Layout)

-Reserve R1387(@10K_0402) from PREP2# to +3VS . (Modify CKT&Layou t)

26. Update LAN chip schematic related by cust omer recommend . <Page 25> 94.05.20.

-Change R73.1 and R36.1 connection from +3VS to V_3P3_LAN . (Modify CKT& Layout)

27. Update CardReader chip schematic related by c ustomer recommend . <Page 23> 94.05.20.

-Del U46 and related net . (Modify CKT,BOM&L ayout)

-Del R591,R593 . (Modify CKT,BOM&Layout)

-Change R594 connection to between +VCC_SD and SDWP#_SMCE# . (Modify CKT&Layou t)

-Change R602 connection to between +VCC_SD and SM_RB# . (Modify CKT&Layout)

3 3

-Change JP41.36 connection to MSBS_SDCMD_SMWE# . (Modify CKT&Layout)

-Change JP41.27 connection to SDCLK_SMRE# . (Modify CKT&Layou t)

-Change JP41.28 connection to SDWP#_SMCE# . (Modify CKT&Layout)

-Change JP41.26 connection to SM_RB# . (Modify CKT&Layout)

-Add R1388(0_0402) between MC_PWRON# and MC_PWRON . (Modify CKT,BOM&Layout)

-Remove Q77,D45,D46,R595,D48 . (Modify CKT&BOM)

28. Update Clock Gen. schematic related by cust omer recommend . <Page 15> 94.05.20.

-Del R1328,R1329,R1330,R1331,R1332 and related net . (Modify CKT,BOM&L ayout)

-Change U25.15 connection to FSB . (Modify CKT&La yout)

-Change U25.16,24,41 connection to +CK_VDD_DP . (Modify CKT&Layout)

-Change C734,C735,C736 connection to +CK_VDD_DP . (Modify CKT&Layout)

- Add R1389(NODP@0_0805),R1390(DP@0_0805),C1010(10U_0805) and related net . (Modify CKT,BOM&Layout)

-Change R1352,R1333 from @0_0402 to 0_0402 . (Modify CKT,BOM&Layo ut)

29. Update MXM schematic related by customer recommend . <Page 18> 94.05.23.

-Reserve R1391(@0_0402) from JP39.125 to CLKREQA# . (Modify CKT&Layout)

-Add R1392(0_0402) from JP39.157 to ADP_PRES . (Modify CKT,BOM&Layo ut)

4 4

30. Update LAN chip schematic related by cust omer recommend . <Page 25> 94.05.23.

2

3

4

5

31. Update Clock Gen. schematic related by cust omer recommend . <Page 15> 94.05.23.

-Reserve R1393(@0_0402_5%) from U25.46(CLKIREF) to +CK_VDD_DP . (Modify CKT&Layout)

-Reserve C1011(@0.1U_0402) from U25.46(CLKIREF) to GND . (Modify CKT&Layout)

-Reserve R1394(@10K_0402) from U25.2(PCI_EC) to +3VS . (Modify CKT&Layo ut)

-Remove R1353,R1333(@0_0402_5%) . (Modify CKT&BOM)

32. Update AC97 Codec to keep AD1981HD only schematic rel ated by customer recommend and DFx issue
improved . <Page 15,28> 94.05.23.

-Del C391,R403,R406,R388,R158,R159,C410,C408,C401,C398,R415,R364,C397,R1085(CLK_14M_CODEC)
,R418 and short U14.42 to GNDA . (Modify CKT,BOM&Layout)

-Add T88~T101 test point on the bottom side . (Modify C KT&Layout)

33. Update ICH7 SPI I/F related schematic by custo mer recommend . <Page 21> 94.05.24.

-Change R1284.1,R1285.1 and R1286.1 connection from +3VS to +3VALW . (Modify CKT& Layout)

34. Update TI PCI7611MLS/PCI7612 related schematic by custom er recommend . <Page 23> 94.05.24.

3rd Netin

-Change R594.2 and R602.2 connection from +VCC_SD to +VCC_SM_XD . (Modify CKT&Layou t)

35. Update ICH7 SATA I/F related schematic by cust omer recommend . <Page 20> 94.05.24.

-Del JP45 pin8,9,10 +3VS connection . (Modify CKT& Layout)

-Del C997~C1000 . (Modify CKT,BOM&Layout)

36. Update ICH7 PATA I/F related schematic for SATA HDD support . <Page 20> 94.05.24.

- Add R556(100K_0402) . (Modify CKT&BOM)

37. Change some Capacitors for Lead Free designing . <Page 6,18,22,30> 94.05.25.

-Remove C939(@220U_C6_6.3V) and add C983(330U_D2E_2.5V) . (Modify CKT&BOM)

-Remove C633(@47U_25V_M) and add C1013~C1017(10U_1206_25V6M) . (Modify CKT,BOM&Layout)

-Remove C671(@100U_6.3V_M) and add C1012(150U_D_6.3VM) . (Modify CKT,BOM&Layout)

-Remove C670(@220U_C6_6.3V) and add C979(330U_DD2E_2.5V) . (Modify CKT&BOM)

-Remove C1,C527(@100U_6.3V) and add CC568,C567(150U_D_6.3V) . (Modify CKT&BOM)

38. Update the Accelerometer related and install the related BOM for Accelerometer enable . <Page 19,21,27,33>

- Change the net name from ACCEL_INT# to ACCEL_INT, ACCEL#_SB to ACCEL_SB, ACCEL_INT#_KBC
to ACCEL_INT_KBC . (Modify CKT&Layout)

-Note R94 must be removed when R1354 stuff and R87 remove . (Modify CKT &BOM)

-Reserve D61,C1018,R1395,Q95 between ACCEL_INT and Q78.1 . (Modify CKT&Layo ut)

-Remove R1358,R1360 . (Modify CKT&BOM)
9rd Netin/BOM Transf er

39. Update Docking related schematic for Customer Smart Adaptor new function request . <Page 21,35>

-Change JP30.118 and R1387.1 net name to DOCK_ID . (Modify CKT&La yout)

-Add JP30.117(DOCK_ADP_SIGNAL) to ADP_SIGNAL by R1401(1K_0402_1%) . (Modify CKT,BOM&Layout)

40. Update AD1981HD related schematic for Vendor ADI review result . <Page 28>

-Change U18.2 connection from GND to AGND, move R258 between C551.1 and U18.2 . (Modify CKT& Layout)

-Change C409,C427,C431 from 0.1U_0402 to 0.1U_0805 . (Modify CKT,BOM&Layout)

-Add R1400(0_1206) between GND and AGND close to Codec area . (Modify CKT,BOM&Lay out)

-Disconnect U14.14 and U14.15, disconnect U14.40 and U14.33 to AGND and add T102,T103,T104 on pi n 14,40,33 .

( Modify CKT&Layout)

- Add R1399(0_0805) replace L36(CHB2012U121(0805)) . (Modify CKT&BOM)

-Add C1019(10P_0402) to GND . (Modify CKT,BOM&Layout)

41. Update Accelerometer related schematic f or Customer review result . <Page 27>

- Remove R1355(@0_0805), add D62(ACCEL@CH751H) between U64.3/19 and +3VS . (Modify CKT,BOM&Layout)

-Del R1358 and R1360 pull-down resistors . (Modify CKT,BOM& Layout)

-Add R1398(0_0402) to GND, del U64.29 to GND connection . (Modify CKT,BOM&L ayout)

42. Change the Audio Amp chip from TI TPA6017A2_TSSP20 to MAXI M MAX9710_QFN20 and update related
schematic for Customer Spec modified request . <Page 29>

-Change U39 from TPA6017A2_TSSOP20 to MAX9710ETP_QFN20 . (Modify CKT,BOM&Layout)

- Del D59,R613,R431,C93,R439,R438,C663,C664,R971~R974,C661 . (Modify CKT,BOM&Layout)

-Change C503,C502 from 0.047U to 0.1U . (Modify CKT,BOM&Layout)

-Add R1403(10K_0402) from U39.5 to C503.2, R1404(10K_0402) from U39.5 to U39.7 . (Modify CKT,BO M&Layout)

-Add R1405(10K_0402) from U39.1 to C502.2, R1406(10K_0402) from U39.1 to U39.19 . (Modify CKT,BO M&Layout)

-Add R1407(0ohm) from U39.4 to AGND;Add C1020(10U_1206) from +5VALW and GND . (Modify CKT,BOM&Layout)

-Add C1021(1U_0603) from U39.2 to AGND . (Modify CKT,BOM&Layou t)

-Change C662 from @100U_6.3V to @150U_D_6.3V . (Modify CKT&Layou t)

-Reserve R284(@4.7K_0402_5%) from U6.L3 to V_3P3_LAN . (Modify CKT&Layou t)

-Add T59 on U6.L3 . (Modify CKT&Layout)

-Add T60 on U6.M5 . (Modify CKT&Layo ut)

-Reserve Q94(@2N7002_SOT23) and change R1380 connection as update schematic . (Modi fy
CKT&Layout)

-Del R1381 and short Q29.3 to GND directly . (Modify CKT& Layout)

1

2

Security Classification

Issued Date

THIS SHEET OF ENGINEERI NG DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATIO N. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUT HORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DIS CLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/03/10 2006/03/10

Compal Secret Data

Deciphered Date

4

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

H/W2 EE Dept. PIR SHEET(3)

LA-2821P

50 52Saturday, January 14, 2006

5

1.0

1

EAL80 from DB-1 Step to DB-2 Step LA-2821 REV:0.1 -> 0.2 Modify <94.05.10.~94.05.30. >

43. Reserve a 0ohm resistor for time delay pass through schem atic by Customer request. <Page 37> 94.05.27.

-Reserve R1402(@0_0402) between PWR_GD and PGD_IN . (Modify CKT&Layout)

44. Change the resistor value to tune the delay schemat ic by Customer request. <Page 37> 94.05.27.

-Change R38 from 100K_0402 to 47K_0402 . (Modify CKT&B OM)

45. Change BOM option for Intel chipset ver:A1 by C ustomer recommend . <Page 7,21> 94.05.27.

-Change R1309 from @0_0402 to 0_0402, remove R1015(@100K_0402) . (Modify CKT&BOM)

1 1

46. Add a 0ohm resistor for debug by Customer recommend . <Page 4,20> 94.05.27.

-Add R1408(0_0402) between U26.H22 and H_STPCLK# . (Modify CKT,BOM&Layo ut)

47. Add a 0.1UF CAP to improve Cut Moat issue for RGB signals . <Page 36> 94.05.27.

-Add C1022(0.1U_0603) between +3VS and +VCCP . (Modify CKT,BOM&Layout)

48. Add 10Kohm pull-high to +VCC_SM_XD for TI FAE recommend . <Page 23> 94.05.27.

-Add R1396 and R1397(10K_0402) Pull-High to +VCC_SM_XD for MSBS_SDCMD_SMWE# and SDCLK_SMRE# .
(M odify CKT,BOM&Layout)

49. Update TPM related schematic for Vendor review result . <Page 32> 94.05.27.

-Add R1409(TPM1.2@0_0402) from U66.7 to GND, remove R1379(@4.7K_0402) . (Modify CKT,BOM&Layout)

-Change C193.1 connection from +3V to +3VALW for TPM1.2 . (Modify CKT& Layout)

EAL80 from SI-1 Step to SI-2 Step LA-2821 REV:0.3 -> 0.4 Modify <94.08.23.~94.09.21. >

1. Add discharge circuit for BT_LED and WL_LED to solve t he LED always light on issue. <Page 32> 94.08.23.

-Add R1440 and R1441(100K_0402) for BT_LED and WL_LED discharge . (Modify CKT,BOM&Layou t)

2. Remove DPRSLPVR NB side PullHigh resistor for I ntel document update. <Page 7> 94.08.24.

-Remove R1209(@10K_0402) for DPRSLPVR . (Modify CKT&BOM)

2 2

3. Keep TPM1.2 on Board and Delete TPM1.1 Module Conn ector designing. <Page 32> 94.08.24.

-Del JP33,R1236,R1242,R1253,C191,C192,C193 and related schematic. (Modify CKT,BOM&Layo ut)

4. Update TPM1.2 chip PCB layout footprint. <Page 32> 94.08.24.

- Change U66 PCB Footprint from SLD9630TT_TSSOP28 to SLB-9635-TT-1P2_TSSOP28. (Modify CKT&Layout)

5. Correct ODD CSEL option setting. <Page 20> 94.08.24.

-Remove R460(@4.7K_0402) and add R557(470_0402). (Modify CKT&BOM)

6. Correct SPI I/F Power Source for Capell_Valley_CRB_Schematics_ Rev1_502.pdf update . <Page 32> 94.08.26.

-Change U61.8, U65.8, R1287.1 and R1288.1 Power Rail from +3VS to +3VALW. (Modify CKT&Layout)

7. Modify Mini-Card debug interface design for customer update . <Page 27> 94.08.30.

-Move +3VALW from pin 39 to pin 45 and move CAPS_LED# from pin 41 to pin 51. (Modify CKT&Layout)

8. Update ADI1981HD CIS symbol and PCB Footprint . <Page 28> 94.08.30.

-Update U14 CIS symbol and change PCB Footprint from AD1981B_LQFP48 to AD1981HDJSTZ-REEL_LQFP48.
( Modify CKT&Layout)

9. Change PCI-E Ports for ICH7 modify . <Page 21,24,35> 94.08.31.

-Change ExpressCard (NC) connection to port 3, Change Docking connection to port 4. (Modify C KT&Layout)

10. Update Accelerometer related design for custome r request . <Page 19,21,33,36> 94.09.02.

3 3

-Del D61, C1018, R1395 & Q95. (Modify CKT&Layout)

-Add Q75, R187; change D12 to Dual LED. (Modify CKT,BOM&Layout)

-Add net HDD_STP# from GPIO19 of ICH7 to Q75. (Modify CKT&Layout)

-Install R1374 and change R1060 to no-stuff. (Modify C KT&BOM)

-Del R1363 and R1364; Add SB GPIO test pad T80,T89,T99,T106. (Modify CKT,BOM&L ayout)

11. Modify Mini-Card debug interface design for customer update . <Page 27> 94.09.02.

-Remove R1435 and R1436(@0_0402). (Modify CKT&BOM)

12. Modify TI PCI7612 designing for vendor request . <Page 23> 94.09.06.

-Change R573 from 10K_0402 to 0_0402. (Modify CKT&BOM)

-Change R594,R1396 and R1397 from 10K_0402 to 100K_0402. (Modify CKT&BOM)

-Change R602 from 10K_0402 to 22K_0402. (Modify CKT&BOM)

13. Update Accelerometer related design for custome r request . <Page 19,21,33,36> 94.09.02.

-Add net HDD_STP from GPIO19 of ICH7 to Q84.2. (Modify CKT&La yout)

- Add Q84(2N7002) and R1442(100K_0402) for HDD_STP. (Modify CKT,BOM&Layout)

-Reserve R1443(@0_0402) for HDD_STP#. (Modify CKT&Layout)

14. Update ICH7 GPIO related design for customer request . <Page 21> 94.09.06.

4 4

-Del R1321 and R1323 related reserved schematic. (Modify CKT&La yout)

15. Modify LAN controller related for cu stomer request . <Page 25> 94.09.07.

-Add and change R277 from @0_0402 to 10K_0402. (Modify CKT&B OM)

-Remove R1380(@0_0402) and add Q94(2N7002). (Modify CKT&BOM)

-Change R506 pull-up to +3VALW from V_3P3_LAN. (Modify CKT&Layout)

-Add Q100(SI2301BDS), reserve R83(@0_0402) and related schematic. (Modify CKT,BOM&Layo ut)

1

2

3

4

5

16. Modify PCMCIA Connector design for M/E team request . <Page 24> 94.09.08.

- Change JP9 PCBFootprint from SLINK_AFH-1000-17A0-3_104P to TYCO_C-PT05-023-D1_150P_LT.

(M odify CKT,BOM&Layout)

17. Delete New Card, USB HUB related design for customer S pec update . <Page 15,21,24,30,31> 94.09.08.

- Delete R1272,R1273,R1274,R1275,R1276,R1277,R1278,R1279,R1280,R1282,R1316,C959,C960,C961,C962,

C 963,C964,C965,C966,C967,C968,C969,C970,C971,C972,C973,U60,R535,C541,L34,C521,C529,C535,C517,
C 558,C540,C559,R981,U53,Y6,R984,C22,C27,L37,R1353,R537,R539,R523,R1317,R1318,R1099,R1102,
R1100,R1103,C712,C713; Add T107. (Modify CKT,BOM&Layout)

-Delete R982,R983 reserve. (Modify CKT&Layo ut)

18. Modify MiniCard related design for customer request. <Page 27> 94.09.08.

-A dd Q101,Q102,R1445; Reserve R1444(@0_0805). (Modify CKT,BOM&Layout)

19. Delete FWH I/F BIOS related design for customer r equest. <Page 15,19,20,21,32> 94.09.08.

-Del &U21(SST49LF008A-33-4C-NH),U21,U20,R273,R278,RP42,R1125,C42,C333. (Modify CKT,BOM&Layout)

-Del R279,C43 reserve. (Modify CKT&Layout)

-Add T108,T109,T110. (Modify CKT&Layout)

-Delete BIOS_SEL1 and replace with short to GND directly. (Modify CKT&Layout)

20. Wire VGA Thermal inform signal with System side for function workable. <Page 21> 94.09.09.

- Add R252(0_0402). (Modify CKT&BOM)

21. Modify MiniCard related design for customer. <Page 27> 94.09.10.

-Add J44(JUMP_43X39) and reserve J45(@JUMP_43X39) for Power Source option. (Modify CKT&Layo ut)

-Change R1444.1 connection from +3VALW to +3VS. (Modify CKT&Layout)

-Remove Q101,Q102,R1445 and add R1444. (Modify CKT&BOM)

22. Modify TI PCI7612 designing for vendor request . <Page 23> 94.09.10.

-Change R573.1 power connection to +SC_PWR from +5VS. (Modify CKT&La yout)

-Change power rail to R615 & R616 to +3VS from +5VS and remove both R615 & R616. (Modify CKT, BOM&Layout)

23. Modify LAN Transformer designing for cu stomer request . <Page 26> 94.09.10.

-Change R270,R271 connection by add C333 between ground and R270/R271 . (Modify CKT,BOM&L ayout)

24. Create an option to use the 32KHz clock from KBC for TP M1.2 for customer request . <Page 32,33> 94.09.10.

-Reserve R1446(@0_0402) to connect U47.58 and U66.13. (Modify CKT&Layo ut)

25. Delete MiniPCI Debug I/F reserve for Layout space free . <Page 19,27,32> 94.09.12.

-Del R1117,R235,R441,R447,R451,R452 and JP20. (Modify CKT,BOM&Layout)

-Del R448,C537,R437 and Q49 reserve. (Modify CKT&Layou t)

-Change R1420.1 connection from +3VALW to +3VL. (Modify CKT&Layout)

-Change C292,C538,C542 power source from +3VS to +3VS_MINI. (Modify CKT&La yout)

-Add H29,H30(H_C236D157)(MiniCard Stand Off). (Modify CKT,BOM&Layou t)

26. Change Jopen PAD for CIC DFx req uest . <Page 15> 94.09.12.

-Change J29 PCBfootprint to JUMP_43X39. (Modify CKT&Layout)

27. Change LAN chip desgin to switch LAN power with LP_ EN# for customer request . <Page 25> 94.09.13.

-Install R15(4.7K_0402_5%) and no-stuff U36(@SN74LVC1G17DBVR_SOT23-5). (Modify CKT&BOM)

28. Modify TPM1.2 related design about the ADP_EN for c ustomer request . <Page 32,33> 94.09.13.

-Reserve R1447(@0_0402) close to Y8.1. (Modify CKT&Layo ut)

- Reserve R1448(@0_0402) for ADP_EN. (Modify CKT&Layout)

29. Modify BT related design for cust omer request . <Page 30> 94.09.14.

-Change R454 to 47K from 1K. (Modify CKT&B OM)

-Reserve a 0.1uF cap (no-stuff) from R454.2 to ground. (Modify CK T&Layout)

30. Modify LAN chip related design for customer request . <Page 25> 94.09.14.

-Add R458(0_0402) between Q100.2 and Q94.1. (Modify CKT,BOM&La yout)

31. Modify BITCLK related design for EMI req uest . <Page 20,28,34> 94.09.14.

-Reserve R1032,C722 close to U14.6. (Modify CKT&Layo ut)

-Move R1028, C721 close to JP32.12; R1314,R371 close to U26.U1. (Modify CKT&L ayout)

32. Modify LID_SW# related design for M/E request . <Page 34> 94.09.14.

-Add R1449 close to JP18.16. (Modify CKT,BOM&Layo ut)

33. Modify Clock Gen. related design for Vendor request . <Page 15> 94.09.14.

-Change R1092 from 475_0402_1% to 4.7K_0402_1%. (Modify CKT&BOM)

34. Modify NB chip CFG11 related design for Intel CRB Rev1_502 update . <Page 11> 94.09.14.

-Remove R1154(@2.2K_0402_5%). (Modify CKT&BOM)

35. Modify Smart AC Adaptor related design f or customer request . <Page 11> 94.09.14.

-Change R1237 from 10K_0402 to 100K_0402. (Modify CKT&BOM)

Security Classification

Issued Date

THIS SHEET OF ENGINEERI NG DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATIO N. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUT HORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

2

MAY BE USED BY OR DIS CLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/03/10 2006/03/10

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

4

Date: Sheet of

Compal Electronics, Inc.

H/W2 EE Dept. PIR SHEET(4)

LA-2821P

51 52Saturday, January 14, 2006

5

1.0

1

2

3

4

5

EAL80 from SI-1 Step to SI-2 Step LA-2821 REV:0.3 -> 0.4 Modify <94.08.23.~94.09.21. >

36. Add DDR2 Module Thermal inform function to NB for customer request. <Page 7,13,14> 94.09.15.

-Add R1450(0_0402) between DDR_THERM# and PM_EXTTS#0 . (Modify CKT,BOM&Layout)

37. Reserve a cap at JP30.P2 pin for +5VS of Docking for customer request. <Page 35> 94.09.15.

-Reserve C1033(@22U_0805_6.3V4Z) close to JP30.P2. (Modify CKT&Layout)

38. Delete Bulk Cap. Daul Layout design reserve for DFx request. <Page 18> 94.09.15.

-Change C633 from @47U_25V(Non-LF) to 100U_25V(250',10sec,LF); Del C1013~C1017 . (Modify CKT,BOM&Layout)

1 1

-Del C823(100U 6.3V M B (6.3X6.0) CV-AX),C939,C830,C806(220U_C6_6.3V_M_R15) . (Modify CKT&Layo ut)

-Del C979(220U_D2_2VK_R9); Change C670 to SF22001M300. (Modify CKT,BOM&Layout)

- Del C1012(150U_D_6.3VM); Change C671 to SF22001M300. (Modify CKT,BOM&Layout)

- Del C567,C568(150U_D_6.3VM); Change C1,C527 to SF22001M300. (Modify CKT,BOM&Layout)

39. Remove all Clock Gen. pairs Pull-Down Resistors for LP design recommend. <Page 15> 94.09.15.

-Remove R1071,R1073,R1076,R1082,R1119,R1122,R1094,R1096,R1258,R1260,R1112,R1116,R1250,R1252,
R1124,R1127,R1134,R1137,R1238,R1239. (Modify CKT&BOM)

40. Modify XMIT_OFF related design for S/W request. <Page 27> 94.09.16.

- Add R1424(0_0402) between XMIT_OFF and XMIT_OFF#. (Modify CKT,BOM&Layout)

41. Modify TI PCMCIA Controller related design for Vendor request. <Page 23,24> 94.09.16.

-Add R591(0_0402) close to U42.E2. (Modify CKT,BOM&Layo ut)

-Add R617~R620,R623,R624(0_0402) close to JP41. (Modify CKT,BOM&Layou t)

-Reserve C369,C372,C373,R593,R599,R613,R614 close to JP9. (Modify CKT&Layou t)

-Remove R565. (Modify CKT&BOM)

42. Modify Audio Codec related design to avoid a small amount of noise on pin 2 could cause the codec to power
up in a test mode. <Page 28> 94.09.21.

2 2

-Change R422 from @0_0402 to 10K_0402. (Modify CKT&BOM)

43. Modify ICH7 related design for ICH7M & 3945abg Host Interf ace auto-detect sequence Issue (Sighting# 80332).
<Page 21> 94.09.21.

-Change decoupling caps (C710 & C711) from 0.1uF_0402 to 0.15uF_0603). (Modify CKT,BOM&L ayout)

44. Modify Clock Gen. all series termination resistors for the differential signals related design for ICS recommend.
<Page 15> 94.09.21.

-Change R1070,R1072,R1075,R1081,R1118,R1121,R1257,R1259,R1093,R1095,R1144,R1145,R1123,R1126,R1111,
R1115,R1249,R1251 from 33_0402 to 24_0402. (Modify CKT&BOM)

3 3

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERI NG DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATIO N. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUT HORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

1

2

MAY BE USED BY OR DIS CLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/03/10 2006/03/10

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

4

Date: Sheet of

Compal Electronics, Inc.

H/W2 EE Dept. PIR SHEET(5)

LA-2821P

52 52Saturday, January 14, 2006

5

1.0