Compal LA-2792 HAL00 Travis DIS, Latitude D620 Schematic

A

B

COMPAL CONFIDENTIAL

C

D

E

1 1

PCB NO :

LA-2792

COMPAL P/N :

2 2

MODEL NAME :

HAL00

45135731L01

Travis (DIS) Schematics Document

uFCPGA Mobile Yonah
Intel Calistoga + ICH7M

2006-01-20

3 3

4 4

REV : 1.0 (DELL: A00)

DELL CONFIDENTIAL/PROPRIETARY

MB PCB

Part Number Description

DAA0000050L

PCB ZJX LA-2792
REV0 MB DIS

A

BOM NO. 45135731L01
PCB P/N: DAA0000051L

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

B

C

D

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

Cover Sheet
LA-2792

170Tuesday, Feb ru ar y 07, 2006

E

1.0

of

A

Compal confidential

Model : HAL00

B

C

D

E

Block Diagram

FAN

RGB

DVI

FAN1_VOUT

page 18

LVDS CONN

+INV_PWR_SRC

+LCDVDD

page 19

1 1

Thermal

GUARDIAN II
EMC4000

+3.3V_SUS

CRT CONN

+5V_RUN

NVG72-M-V

+1.2VRUN
+VDD_CORE(1.1V)

page 52,53,54,55,56,57,58

page 18

page 20

PCI-E 16X

+1.05V_VCCP (1.05V)
+VCC_CORE

+1.5V_RUN
+1.8V_SUS
+1.05V_VCCP (1.05V)
+3.3V_RUN
+2.5V_RUN

TV

2 2

PCI BUS

DOCKING
PORT

PAGE 36

Mini Card2

WLAN

+3.3V_RUN

3 3

page 34

DOCKING
BUFFER

+5V_RUN

PAGE 35

+3.3V_RUN/ +1.5V_RUN 100MHz

Mini Card 1

WWAN

+3.3V_RUN
+1.5V_RUN+1.5V_RUN

page 34

HUB USB[2]USB[0]

CardBus

OZ601 TQFP

+3.3V_RUN

HUB USB[1]USB[7]

GIGA Enthernet

BCM5752

+3VLAN

RJ45

IO/B

+3.3V_RUN 33MHz

page 30

page 29

IDSEL:AD17
(PIRQC,D#,GNT#1,REQ#1)

PCI Express BUS

USB[1]

HUB USB[4]

+3.3V_RUN
+3.3V_SUS
+1.5V_RUN
+1.05V_VCCP

+3.3V_ALW

Pentium-M

Yonah-2M

uFCPGA CPU

FSB 533/667 MHz

Calistoga

1466pin BGA

DMI

+1.5V_RUN
100MHz

652pin BGA

+3.3V_RUN
33MHz

SMSC SIO
ECE5018

page 38

478pin

System Bus

page 7,8

H_D#(0..63)H_A#(3..31)

INTEL

page 10,11,12,13,14,15

INTEL

ICH7-M

page 21,22,23,24

LPC BUS

HUB USB[1]
HUB USB[2]
HUB USB[3]

SPI

CPU ITP Port

+1.05V_VCCP

Memory BUS
(DDR2)

48MHz

SATA

S-HDD

+5VHDD

+1.8V_SUS 533 / 667MHz

HUB USB[3]

USB[5,6]

USB[3,4]

Azalia I/F

ATA100

REAR

SIDE

USB[2]

D Moudle

page 25 page 25 page 26

+5V_RUN

Azalia Codec

Clock Generator

SLG84450VTR

+3.3V_RUN

DDRII-DIMM X2

BANK 0, 1, 2, 3, 4 ,5 ,6 ,7 ,8

+0.9V_DDR_VTT
+1.8V_SUS

Smart Card

OZ77C6

+3.3V_RUN

USB Ports X2

+5V_SUS

USB Ports X2

+5V_SUS

STAC9200

+3.3V_RUN
+VDDA

page 16,17

page 31

page 32

IO/B

MDC

+3.3V_SUS

page 33

RJ11

page6page 7

SLOT

USB5 on right side of
connector, USB6 on left side

USB3 on the top of connector,
USB4 on the bottom

Cable

IO/B

1.8V/0.9V

page 48

VCORE (IMVP-6)

page 49

1.5V/1.05V

DC IN

page 47

page 44

Power Sequence

page 42

Power On/Off

CHARGER

4 4

page 50

BATT SELECT

page 51

BATT IN

page 45

3V/5V/15V

page 46

A

SW & LED

page 43

DC/DC Interface

page 41

B

Bluetooth

+3.3V_RUN

page 33

COM

FIR

+3.3V_RUN

page 37

page 37

Int.KBD &

page 40

Stick

Stick

C

MEC5004

+RTC_CELL
+3.3V_ALW

Touch Pad

+5V_RUN

page 39

page 40

SMSC KBC

SPI

ST M25P80

+3.3V_ALW

page 39

D

AMP & INT.
Speaker

+5V_SUS

page 27

INT MIC

IO/B

+5V_SUS

HeadPhone &
MIC Jack

+3.3V_RUN

page 27

DELL CONFIDENTIAL/PROPRIETARY

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

Block Diagram
LA-2792

270Tuesday, Feb ru ar y 07, 2006

E

of

1.0

5

Ceramic Capacitors :

4

3

TABLE

PCI

2

1

0.1U_0402_6.3VXX

D D

Tolerance
Temperatur e Characteristics

PCI DEVICE

CARD BUS

IDSEL

AD17

REQ#/GNT#

1

PIRQ

C

Rated Voltage
Package Size
Value

PM TABLE

Tantalum or Polymer Capacitors :

10U_D2_10VX_R45

C C

Low ESR Mark : 45 m ohm
Tolerance
Rated Voltage
Package Size
Value

State

S0

S1

S3

S5 S4/AC

S5 S4/AC don't exist

power
plane

+5V_ALW
+3.3V_ALW

ON

ON

ON

ON

+3.3V_SRC
+15V_SUS
+5V_SUS
+3.3V_SUS
+1.8V_SUS

ON

ON

ON

OFF

OFF

+5V_RUN
+3.3V_RUN
+1.8V_RUN
+0.9V_DDR_VTT
+1.5V_RUN
+VCC_CORE
+1.05V_VCCP
+2.5V_RUN

ON

ON

OFF

OFF

OFFOFF

Capacitor Spec Guide:
Temperature Characteristics:

B B

A A

Symbol

CODE

Tolerance:

Symbol
CODE

Z5U

8

9

COG SJ

HI J

UK

UJ

A

+-0.05PF

+-0.1PF

M

K

+-20%

+-10%

+-30%

Z5V

X6SNPO

SL

N

A

1

B

2

Z5P

B

BJ

K
X5S

C

+-0.25PF

P

+100,-0%

4

5

G

X

6

X5R

SH

H

+-3%

Z

+80,-20%

30

Y5V

Y5U X7R

C
CH

D

+-0.5PF +-1PF

Q

+20,-10%

+30,-10%

Y5P

DEFG
CJ

CK

F

+-2%

V

+40,-20%

7

J

+-5%

NOTE1:

USB

@XX : Depop component

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

TABLE

USB PORT#

0
1
2
3,4
5,6
7

3

DESTINATION

Mini 2(WLAN)

USB Hub (5018)

D Moudle

SIDE Blue tooth

USB H U B DESTINATION

1
2
3

PC Card Bay

Mini 1(WWAN)

Smart Card --> BIO

4

REAR

Docking

DELL CONFIDENTIAL/PROPRIETARY

Title

Size Document Number Rev

2

Date: Sheet

Compal Electronics, Inc.

Index and Config.
LA-2792

1

370Tuesday, Feb ru ar y 07, 2006

1.0

of

5

D D

4

3

2

1

ADAPTER

+PWR_SRC

FDS4435 +INV_PWR_SRC

RUN_ON

MAX8632

RUN_ON

RUN_ON

+1.2VRUNP +VCC_GFX_CORE

BATTERY

ALWON

C C

SUS_ON

MAX8734

+5V_SUS

B B

SI3456

HDDC_EN#

SI3456

RUN_ON

793475

PL8

AUDIO_AVDD_ON

(Option)

SI4800

RUN_ON

ALWON

SUS_ON

+3.3V_SRC

SI3456

ENAB_3VLAN

+5V_ALW

+3.3V_ALW

SI4800

ISL6260

RUNPWROK

+VCC_CORE

RUNPWROK

+1.5V_RUN

ISL6227

MAX88550

RUN_ON

SI4800

RUN_ON

SUSPWROK_5V

+0.9V_DDR_VTT

RUNPWROK

+1.8V_SUS+1.05V_VCCP

+5V_SATA +5V_RUN +VDDA

MODC_EN#

+15V_SUS

+3.3V_RUN

+3VLAN

+3.3V_SUS

+1.8V_RUN

SI3456

L47

MOD
(+5V_RUN)

A A

5

4

EMC4000

+2.5V_RUN

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

2

DELL CONFIDENTIAL/PROPRIETARY

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

Power Rail
LA-2792

470Tuesday, Feb ru ar y 07, 2006

1

of

1.0

5

4

3

2

1

+3.3V_SUS

2.2K 2.2K 2.2K 2. 2K

ICH_SMBCLK

D D

ICH7-M

C C

SIO

Macallan IV

B B

C22

ICH_SMBDATA

B22

CLK_SMB

6

DAT_SMB

5

DOCK_SMB_CLK

10

DOCK_SMB_DAT

9

112

111

SBAT_SMBCLK
SBAT_SMBDAT

+3.3V_ALW

10K 10K

+3.3V_ALW

8.2K 8. 2K

+3.3V_ALW

4.7K 4. 7K

+3.3V_ALW

+3.3V_SUS

WWAN

SMBUS Address [TBD]

+3.3V_ALW

+3.3V_ALW

+3.3V_ALW

2N7002

2N7002

3032

5752M
LOM

SMBUS Address [C8]

100

C8C7

WLAN

SMBUS Address [TBD]

8

GUARDIAN

7

39

DOCKING

40

3

2'nd

4

BATTERY

100

6

INV

5

3032

SMBUS Address [2F]

SMBUS Address [C4, 72, 70, 48]

SMBUS Address [16]

Inverter

SMBUS Address [58]

CLK_SCLK

CLK_SDATA

+3.3V_RUN

197

195

197

195

16

CLK GEN.

17

SMBUS Address [D2]

DIMM0

SMBUS Address [A0]

DIMM1

SMBUS Address [A2]

8.2K8.2K

8

7

A A

PBAT_SMBCLK
PBAT_SMBDAT +3.3V_ALW

100

100

3

BATTERY

4

CONN

9

CHARGER

10

SMBUS Address [16]

SMBUS Address [12]

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

SMBUS TOPOLOGY
LA-2792

570Tuesday, Feb ru ar y 07, 2006

1

1.0

of

5

D
1

3

G S

2

2N7002

ICH_SMBDATA23,28,34 CLK_SDATA 16,17

D D

+3.3V_RUN

ICH_SMBCLK23,28,34

FSC FSB FSA CPU

CLKSEL2 CLKSEL0CLKSEL1

ICH_SMBDATA

ICH_SMBCLK

000

1

*

C C

00

1

0

11

0

1

1

0

1

1

11

0

00

1

0

1

CPU_BSEL CPU_BSEL2(FSC) CPU_BSEL1(FSB)

133

166

B B

R531

8.2K_0402_5%~D

FSC

CPU_BSEL28 CPU_BSEL18

A A

12

0

0

+3.3V_RUN

5

1 2
12

+3.3V_RUN

Q36

2N7002W-7-F_SOT323~D

D

S

1 3

G

2

2

G

2N7002W-7-F_SOT323~D

1 3

D

S

SRC

MHz

MHz

100

266

100

133

100

200

100

166

100

333

100

100

100

400

Reserve

Table : ICS954305AK

0

1

CLK_NV_27M52

91_0402_5%~D

1 2

R330

0_0402_5%~D

R271
10K_0402_5%~D

FSA

R278

@

10K_0402_5%~D

FCTSEL1 PIN43 PIN44 PIN47 PIN48

0

1

*

12

12

R275

2.2K_0402_5%~D

R270

2.2K_0402_5%~D

Q38

PCI
MHz

CLK_SDATA

CLK_SCLK

1

2

C68

33.3

33.3

33.3

33.3

4.7U_0603_6.3V4Z~D

NOTE: Place Decoupling as close as
physically possilble to the VDD pins

33.3

33.3

Place crystal within

33.3

500 mils of CK410

CLK_ICH_48M23

CLK_SMC_48M31

CLK_PCI_500439

CLK_PCI_501838
CLK_PCI_LOM28

CLK_PCI_PCM30

CLK_DOCKPCI_33M36

CLK_ICH_14M23
CLK_SIO_14M38

12

R73

MCH_CLKSEL2 10 MCH_CLKSEL1 10

DOT96T DOT96C 96/100M_T 96/100M_C

(UMA)

27M_out 27M SSout SRCT0 SRCC0

(DIS)

CLK_NVSS_27M52

CLK_PCI_ICH21
CLK_ENABLE#49

4

+3.3V_RUN

1 2

L40

BLM21PG600SN1D_0805~D

1

C326

0.1U_0402_16V4Z~D

CLK_SCLK 16,17

+CK_VDD_48+CK_VDD_A +CK_VDD_REF

1

2

C61

0.047U_0402_16V4Z~D

27P_0402_50V8J~D

FSB

1

2

C50

4.7U_0603_6.3V4Z~D

C329

14.31818MHz_20P_1BX14318CC1A~D

12

C333

27P_0402_50V8J~D

12

CLK_ICH_48M FSA
CLK_SMC_48M

CLK_PCI_5004
CLK_PCI_5018
CLK_PCI_LOM PCI_LOM
CLK_PCI_PCM PCI_PCM

CLK_PCI_ICH PCI_ICH
CLK_ENABLE#

2

1

2

12

CLK_SIO_14M

1 2

R354
0_0402_5%~D

BLM21PG600SN1D_0805~D

C51

0.047U_0402_16V4Z~D

X2

R298 12.1_0402_1%~D

R1589 12.1_0402_1%~D

R1619 12.1_0402_1%~D
R1438 12.1_0402_1%~D
R331 33_0402_5%~D
R302 33_0402_5%~D
R294 33_0402_5%~D

33_0402_5%~D

+CK_VDD_MAIN2

1 2

L32

1

2

C52

0.047U_0402_16V4Z~D

R32

470_0402_5%~D

1 2

12

1 2

12
12
12
12
12

1 2

R266 12.1_0402_1%~D

1 2

R250 12.1_0402_1%~D

R1621 150_0402_5%~D

1 2

R345 33_0402_5%~D

R1582

+3.3V_RUN

12

1 2

R362 475_0402_1%~D

+3.3V_RUN

R290
10K_0402_5%~D

1 2

FCTSEL1

R274
1_0603_5%~D

1 2
1 2

12

Solder Thermal Pad to GND. Add min. 4 vias.

4

+CK_VDD_MAIN

+CK_VDD_REF
+CK_VDD_48

R273

2.2_0603_5%~D

CLK_XTAL_IN

CLK_XTAL_OUT

FSB
FSC

FCTSEL1

DOCKPCI_33MCLK_DOCKPCI_33M

CLKREFCLK_ICH_14M

CLK_NVCLK_NV_27M

CLK_NVSSCLK_NVSS_27M

R316

1 2

10K_0402_5%~D

CLKIREF

CLK_SCLK

CLK_SDATA

3

+CK_VDD_MAIN

1

C402
10U_0805_10V4Z~D

2

1

C308
10U_0805_10V4Z~D

2

49
54
65

30
36

12
18
40

20

19

41
45
23

34
33
32
27

22

43
44

37

39

16

17

15
21
31
35
42
68

73
74
75
76

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

1

2

1

2

U16

1

VDDSRC
VDDSRC
VDDSRC
VDDSRC

VDDPCI
VDDPCI

VDDCPU
VDDREF
VDD48

X1

X2

USB_48MHz/FSLA
FSLB/TEST_MODE
REF0/FSLC/TEST_SEL

PCICLK4/FCTSEL1
PCICLK3
PCICLK2
PCICLK1

REF1

DOTT_96MHz/27MHz
DOTC_96MHz/27MHz(SS)

ITP_EN/PCICLK_F0

Vtt_PwrGd#/PD

9

IREF

SMBCLK

SMBDAT

4

GNDSRC
GNDCPU
GNDREF
GNDPCI
GNDPCI
GND48
GNDSRC

THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD

SLG84450VTR_QFN72~D

5.1

C384

0.1U_0402_16V4Z~D

C344

0.1U_0402_16V4Z~D

R401

2.2_0603_5%~D

1 2

1

C58

0.1U_0402_16V4Z~D

2

1

C330

0.1U_0402_16V4Z~D

2

+CK_VDD_A

VDDA
GNDA

PCI_SRC_STOP#

CPU_STOP#

CPUT1
CPUC1

CPUT0
CPUC0

CPUT_ITP/SRCT10

CPUC_ITP/SRCC10

SRCT9
SRCC9

CLKREQ9#

SRCT8
SRCC8

CLKREQ8#

SRCT7
SRCC7

CLKREQ7#

SRCT6
SRCC6

CLKREQ6#

SRCT5
SRCC5

CLKREQ5#

SRCT4
SRCC4

CLKREQ4#

SRCT3
SRCC3

CLKREQ3#

SRCT2
SRCC2

CLKREQ2#

SRCT1
SRCC1

CLKREQ1#

LCD100/96/SRC0_T

LCD100/96/SRC0_C

7
8

25
24

11
10

14
13

6
5

3
2
72
70
69
71
66
67
38
63
64
62
60
61
29
58
59
57
55
56
28
52
53
26
50
51
46
47
48

2

1

C64

0.1U_0402_16V4Z~D

2

1

C389

0.1U_0402_16V4Z~D

2

Place near each pin
W>40 mil

Place near CK410+

H_STP_PCI#
H_STP_CPU#

1 2

R348 33_0402_5%~D

1 2

R359 33_0402_5%~D

CPU_BCLK

CPU_ITP
CPU_ITP#

PCIE_SATA

PCIE_ICH
PCIE_ICH#

MCH_3GPLL CLK_MCH_3GPLL

PCIE_VGA

PCIE_MINI2
PCIE_MINI2#

PCIE_MINI1
PCIE_MINI1#

1 2

R321 33_0402_5%~D

1 2

R337 33_0402_5%~D

1 2

R368 33_0402_5%~D

1 2

R376 33_0402_5%~D

1 2

R394 33_0402_5%~D

1 2

R400 33_0402_5%~D

R292 10K_0402_5%~D

1 2

1 2

R366 33_0402_5%~D

1 2

R375 33_0402_5%~D

1 2

R1761 10K_0402_5%~D@

1 2

R397 33_0402_5%~D

1 2

R402 33_0402_5%~D

R299 10K_0402_5%~D

1 2
1 2

R1435 33_0402_5%~D

1 2

R1436 33_0402_5%~D

R1762 10K_0402_5%~D

1 2
1 2

R370 33_0402_5%~D

1 2

R390 33_0402_5%~D

1 2

R1763 10K_0402_5%~D

1 2

R1393 33_0402_5%~D

1 2

R1394 33_0402_5%~D

R1395 10K_0402_5%~D

1 2
1 2

R1638 33_0402_5%~D

1 2

R1639 33_0402_5%~D

1 2

R1640 10K_0402_5%~D

2

1

2

CLK_MCH_BCLKMCH_BCLK
CLK_MCH_BCLK#MCH_BCLK#

CLK_CPU_BCLK
CLK_CPU_BCLK#CPU_BCLK#

CLK_CPU_ITP
CLK_CPU_ITP#

CLK_PCIE_SATA
CLK_PCIE_SATA#PCIE_SATA#

CLK_PCIE_ICH
CLK_PCIE_ICH#

CLK_MCH_3GPLL#MCH_3GPLL#

CLK_PCIE_LOMPCIE_LOM
CLK_PCIE_LOM#PCIE_LOM#

CLK_PCIE_VGA
CLK_PCIE_VGA#PCIE_VGA#

CLK_PCIE_MINI2
CLK_PCIE_MINI2#

CLK_PCIE_MINI1
CLK_PCIE_MINI1#

1

C70

0.1U_0402_16V4Z~D

H_STP_PCI# 23

H_STP_CPU# 23

CLK_MCH_BCLK 10
CLK_MCH_BCLK# 10

CLK_CPU_BCLK 7
CLK_CPU_BCLK# 7

CLK_CPU_ITP 7
CLK_CPU_ITP# 7

+3.3V_RUN

+3.3V_RUN

+3.3V_RUN

+3.3V_RUN

+3.3V_RUN

+3.3V_RUN

+3.3V_RUN

CLK_PCIE_SATA 22

CLK_PCIE_SATA# 22

SATA_CLKREQ# 23

CLK_PCIE_ICH 23
CLK_PCIE_ICH# 23

CLK_MCH_3GPLL 10

CLK_MCH_3GPLL# 10

CLK_3GPLLREQ# 10

CLK_PCIE_LOM 28

CLK_PCIE_LOM# 28
LOM_CLKREQ# 28

CLK_PCIE_VGA 52
CLK_PCIE_VGA# 52

CLK_PCIE_MINI2 34
CLK_PCIE_MINI2# 34

MINI2CLK_REQ# 34

CLK_PCIE_MINI1 34

CLK_PCIE_MINI1# 34

MINI1CLK_REQ# 34

CLK_CPU_ITP
CLK_CPU_ITP#
CLK_MCH_BCLK
CLK_MCH_BCLK#
CLK_CPU_BCLK
CLK_CPU_BCLK#
CLK_MCH_3GPLL
CLK_MCH_3GPLL#
CLK_PCIE_SATA
CLK_PCIE_SATA#
CLK_PCIE_ICH
CLK_PCIE_ICH#
CLK_PCIE_LOM
CLK_PCIE_LOM#

CLK_PCIE_VGA
CLK_PCIE_VGA#
CLK_PCIE_MINI2
CLK_PCIE_MINI2#
CLK_PCIE_MINI1
CLK_PCIE_MINI1#

R369 49.9_0402_1%~D
R377 49.9_0402_1%~D
R349 49.9_0402_1%~D
R360 49.9_0402_1%~D
R322 49.9_0402_1%~D
R338 49.9_0402_1%~D
R392 49.9_0402_1%~D
R403 49.9_0402_1%~D
R381 49.9_0402_1%~D
R385 49.9_0402_1%~D
R365 49.9_0402_1%~D
R374 49.9_0402_1%~D
R393 49.9_0402_1%~D
R399 49.9_0402_1%~D

R542 49.9_0402_1%~D
R543 49.9_0402_1%~D
R544 49.9_0402_1%~D
R545 49.9_0402_1%~D
R1641 49.9_0402_1%~D
R1642 49.9_0402_1%~D

1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2

1 2
1 2
1 2
1 2
1 2
1 2

12
12
12
12
12
12

DELL CONFIDENTIAL/PROPRIETARY

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

Clock Generator
LA-2792

670Tuesday, Feb ru ar y 07, 2006

1

of

1.0

5

4

3

2

1

H_A#[3..31]10

H_A#4
H_A#5
H_A#6
H_A#7
H_A#8

D D

H_REQ#[0..4]10

H_ADSTB#010

H_RS#[0..2]10

H_ADSTB#110

CLK_CPU_BCLK6
CLK_CPU_BCLK#6

H_ADS#10

H_BNR#10

H_BPRI#10

H_BR0#10

H_DEFER#10

H_DRDY#10

H_HIT#10
H_HITM#10

H_LOCK#10
H_RESET#10

H_TRDY#10

ITP_DBRESET#23,39

H_DBSY#10

H_DPSLP#22
H_DPRSTP#22,49

H_DPWR#10

CPU_PROCHOT#38

H_PWRGOOD22

H_CPUSLP#10,22

R1387

@

1K_0603_1%~D

R1378

51_0603_1%~D

H_THERMTRIP#18

12
12

C C

R422

56_0402_5%~D

+1.05V_VCCP

B B

Pop R1378 required by
Intel for B0 Yonah.
Backward compatible for
A0 and A1 Yonah

H_THERMDA18
H_THERMDC18

H_THERMDA, H_THERMDC routing together.
Trace width / Spacing = 10 / 10 mil

A A

1 2

H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22

H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

H_ADSTB#0
H_ADSTB#1

CLK_CPU_BCLK
CLK_CPU_BCLK#

H_ADS#
H_BNR#
H_BPRI#
H_BR0#
H_DEFER#
H_DRDY#
H_HIT#
H_HITM#
H_IERR#
H_LOCK#
H_RESET#

H_RS#0
H_RS#1
H_RS#2
H_TRDY#

ITP_BPM#0
ITP_BPM#1
ITP_BPM#2
ITP_BPM#3

ITP_DBRESET#

H_DBSY#
H_DPSLP#
H_DPRSTP#
H_DPWR#
ITP_BPM#4
ITP_BPM#5

H_CPUSLP#
ITP_TCK
ITP_TDI
ITP_TDO
TEST1
TEST2
ITP_TMS
ITP_TRST#

H_THERMDA
H_THERMDC

H_THERMTRIP#

JCPUA

J4

A3#

L4

A4#

M3

A5#

K5

A6#

M1

A7#

N2

A8#

J1

A9#

N3

A10#

P5

A11#

P2

A12#

L1

A13#

P4

A14#

P1

A15#

R1

A16#

Y2

A17#

U5

A18#

R3

A19#

W6

A20#

U4

A21#

Y5

A22#

U2

A23#

R4

A24#

T5

ADDR GROUP

A25#

T3

A26#

W3

A27#

W5

A28#

Y4

A29#

W2

A30#

Y1

A31#

K3

REQ0#

H2

REQ1#

K2

REQ2#

J3

REQ3#

L5

REQ4#

L2

ADSTB0#

V4

ADSTB1#

A22

BCLK0

A21

H1

E2

G5

F1

H5

F21

G6

E4

D20

H4

B1

F3

F4
G3
G2

AD4
AD3
AD1
AC4

C20

E1

B5

E5

D24
AC2
AC1
D21

D6
D7

AC5
AA6
AB3
C26
D25
AB5
AB6

A24
A25

C7

HOST CLK

BCLK1

ADS#
BNR#
BPRI#
BR0#
DEFER#
DRDY#
HIT#

CONTROL

HITM#
IERR#
LOCK#
RESET#

RS0#
RS1#
RS2#
TRDY#

BPM0#
BPM1#
BPM2#
BPM3#

DBR#
DBSY#
DPSLP#
DPRSTP#
DPWR#
PRDY#
PREQ#
PROCHOT#

PWRGOOD
SLP#
TCK
TDI
TDO
TEST1
TEST2
TMS
TRST#

THERMAL

THERMDA

DIODE

THERMDC
THERMTRIP#

TYCO_1-1674770-2_Yonah~D

+1.05V_VCCP

YONAH

MISC

DATA GROUP

LEGACY CPU

R398
56_0402_5%~D

1 2

D0#
D1#
D2#
D3#
D4#
D5#
D6#
D7#
D8#

D9#
D10#
D11#
D12#
D13#
D14#
D15#
D16#
D17#
D18#
D19#
D20#
D21#
D22#
D23#
D24#
D25#
D26#
D27#
D28#
D29#
D30#
D31#
D32#
D33#
D34#
D35#
D36#
D37#
D38#
D39#
D40#
D41#
D42#
D43#
D44#
D45#
D46#
D47#
D48#
D49#
D50#
D51#
D52#
D53#
D54#
D55#
D56#
D57#
D58#
D59#
D60#
D61#
D62#
D63#

DINV0#
DINV1#
DINV2#
DINV3#

DSTBN0#
DSTBN1#
DSTBN2#
DSTBN3#
DSTBP0#
DSTBP1#
DSTBP2#
DSTBP3#

A20M#
FERR#

IGNNE#

INIT#

LINT0
LINT1

STPCLK#

SMI#

H_THERMTRIP#

E22
F24
E26
H22
F23
G25
E25
E23
K24
G24
J24
J23
H26
F26
K22
H25
N22
K25
P26
R23
L25
L22
L23
M23
P25
P22
P23
T24
R24
L26
T25
N24
AA23
AB24
V24
V26
W25
U23
U25
U22
AB25
W22
Y23
AA26
Y26
Y22
AC26
AA24
AC22
AC23
AB22
AA21
AB21
AC25
AD20
AE22
AF23
AD24
AE21
AD21
AE25
AF25
AF22
AF26

J26
M26
V23
AC20

H23
M24
W24
AD23
G22
N25
Y25
AE24

A6
A5
C4
B3
C6
B4

D5
A3

H_D#0H_A#3
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20H_A#23
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63

H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3
H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3

H_A20M#
H_FERR#
H_IGNNE#
H_INIT#
H_INTR
H_NMI

H_STPCLK#

H_SMI#

H_DINV#0 10
H_DINV#1 10
H_DINV#2 10
H_DINV#3 10

H_A20M# 22

H_FERR# 22

H_IGNNE# 22

H_INIT# 22

H_INTR 22

H_NMI 22

H_STPCLK# 22

H_SMI# 22

H_D#[0..63] 10

ITP_TDO

H_DSTBN#[0..3] 10

H_DSTBP#[0..3] 10

H_RESET#

R434

22.6_0402_1%~D

1 2

1

C71

2

@

1

C72

2

@

0.01U_0402_16V7K~D

0.01U_0402_16V7K~D

R424

22.6_0402_1%~D

1 2

CLK_CPU_ITP6
CLK_CPU_ITP#6

+1.05V_VCCP

ITP_DBRESET#

ITP_BPM#0
ITP_BPM#1
ITP_BPM#2
ITP_BPM#3
ITP_BPM#4
ITP_BPM#5
ITP_TCK
CLK_CPU_ITP

CLK_CPU_ITP#

ITP_TCK

ITP_TRST#

ITP_TMS
ITP_TDI

29

JITP

29

28

VTT1

27

VTT0

26

VTAP

25

DBR#

24

DBA#

23

BPM0#

22

GND5

21

BPM1#

20

GND4

19

BPM2#

18

GND3

17

BPM3#

16

GND2

15

BPM4#

14

GND1

13

BPM5#

12

RESET#

11

FBO

10

GND0

9

BCLKP

8

BCLKN

7

TDO

6

NC2

5

TCK

4

NC1

3

TRST#

2

TMS

1

TDI

30

MOLEX_52435-2891_28P~D@

30

+3.3V_SUS

+1.05V_VCCP

+1.05V_VCCP

R367

150_0402_1%~D

1 2

R415

51_0402_5%~D

1 2

R416

51_0402_5%~D

1 2

R33

54.9_0402_1%~D

1 2

R387

39.2_0402_1%~D

1 2

R417

150_0402_5%~D

1 2

This shall place near CPU

R391

680_0402_5%~D

1 2

R436

27.4_0402_1%~D

1 2

ITP_DBRESET#

ITP_TDO

H_RESET#

ITP_BPM#5

ITP_TMS

ITP_TDI

ITP_TRST#

ITP_TCK

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.
Yonah in mFCPGA479

LA-2792

770Tuesday, Feb ru ar y 07, 2006

1

1.0

of

5

4

3

2

1

Length match within 25 mils

+VCC_CORE

AE18
AE17
AB15
AA15
AD15
AC15
AF15
AE15
AB14
AA13
AD14
AC13
AF14
AE13
AB12
AA12
AD12
AC12
AF12
AE12
AB10

AA10
AD10
AC10
AF10
AE10

JCPUC

VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC

AB9

VCC
VCC

AA9

VCC
VCC

AD9

VCC
VCC

AC9

VCC
VCC

AF9

VCC
VCC

AE9

VCC

AB7

VCC

AA7

VCC

AD7

VCC

AC7

VCC

B20

VCC

A20

VCC

F20

VCC

E20

VCC

B18

VCC

B17

VCC

A18

VCC

A17

VCC

D18

VCC

D17

VCC

C18

VCC

C17

VCC

F18

VCC

F17

VCC

E18

VCC

E17

VCC

B15

VCC

A15

VCC

D15

VCC

C15

VCC

F15

VCC

E15

VCC

B14

VCC

A13

VCC

D14

VCC

C13

VCC

F14

VCC

E13

VCC

B12

VCC

A12

VCC

D12

VCC

C12

VCC

F12

VCC

E12

VCC

B10

VCC

B9

VCC

A10

VCC

A9

VCC

D10

VCC

D9

VCC

C10

VCC

C9

VCC

F10

VCC

F9

VCC

E10

VCC

E9

VCC

B7

VCC

A7

VCC

F7

VCC

YONAH

POWER, GROUND

TYCO_1-1674770-2_Yonah~D

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

K1
J2
M2
N1
T1
R2
V2
W1
A26
D26
C25
F25
B24
A23
D23
E24
B21
C22
F22
E21
B19
A19
D19
C19
F19
E19
B16
A16
D16
C16
F16
E16
B13
A14
D13
C14
F13
E14
B11
A11
D11
C11
F11
E11
B8
A8
D8
C8
F8
E8
G26
K26
J25
M25
N26
T26
R25
V25
W26
H24
G23
K23
L24
P24
N23
T23
U24
Y24
W23
H21
J22
M22
L21
P21
R22
V22
U21
Y21

W21

AD26

AB20
AA20
AF20
AE20
AB18
AB17
AA18
AA17
AD18
AD17
AC18
AC17
AF18
AF17

AF7
AE7

B26

K21

J21
M21
N21
T21
R21
V21

G21

AE6
AD6

AF5
AE5
AF4
AE3
AF2
AE2

B22
B23
C21

R26
U26

AF1
D22
C23
C24
AA1
AA4
AB2
AA3

T22
B25

K6

J6
M6
N6

T6
R6

V6

U1

V1

E7

D2

F6
D3
C1

M4
N5

T2

V3

B2
C3

JCPUB

VCCSENSE
VSSSENSE

VCCA
VCCP

VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP

PSI#
VID0

VID1
VID2
VID3
VID4
VID5
VID6

GTLREF
BSEL0

BSEL1
BSEL2

COMP0
COMP1
COMP2
COMP3

VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC

RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

YONAH

TYCO_1-1674770-2_Yonah~D

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

POWER, GROUNG, RESERVED SIGNALS AND NC

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

AB26
AA25
AD25
AE26
AB23
AC24
AF24
AE23
AA22
AD22
AC21
AF21
AB19
AA19
AD19
AC19
AF19
AE19
AB16
AA16
AD16
AC16
AF16
AE16
AB13
AA14
AD13
AC14
AF13
AE14
AB11
AA11
AD11
AC11
AF11
AE11
AB8
AA8
AD8
AC8
AF8
AE8
AA5
AD5
AC6
AF6
AB4
AC3
AF3
AE4
AB1
AA2
AD2
AE1
B6
C5
F5
E6
H6
J5
M5
L6
P6
R5
V5
U6
Y6
A4
D4
E3
H3
G4
K4
L3
P3
N4
T4
U3
Y3
W4
D1
C2
F2
G1

+1.05V_VCCP

+VCC_CORE

VCCSENSE
VSSSENSE

H_PSI#

CPU_BSEL0
CPU_BSEL1
CPU_BSEL2

VID0
VID1
VID2
VID3
VID4
VID5
VID6

COMP0
COMP1
COMP2
COMP3

VCCSENSE49
VSSSENSE49

+1.5V_RUN

D D

+1.05V_VCCP

R_A

12

V_CPU_GTLREF

R140
1K_0402_1%~D

R_B

12

R147
2K_0402_1%~D

Layout close CPU PIN AD26

0.5 inch (max)

C C

B B

+VCC_CORE

R555
100_0402_1%~D

1 2

R556
100_0402_1%~D

1 2

VCCSENSE

VSSSENSE

Layout close CPU

12

R129

R124

27.4_0402_1%~D

CPU_BSEL CPU_BSEL2 CPU_BSEL1

133

166

00

0

12

12

R465

27.4_0402_1%~D

54.9_0402_1%~D

1

Resistor placed within

0.5" of CPU pin.Trace
should be at least 25

12

mils away from any
other toggling signal.

R457

54.9_0402_1%~D

CPU_BSEL0

1

1

1

1

C87

C88

2

2

10U_0805_4VAM~D

0.01U_0402_16V7K~D

H_PSI#49
VID049

VID149
VID249
VID349
VID449
VID549
VID649

V_CPU_GTLREF

CPU_BSEL010
CPU_BSEL16
CPU_BSEL26

A A

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

Yonah in mFCPGA479

LA-2792

1

870Tuesday, Feb ru ar y 07, 2006

1.0

of

5

+VCC_CORE

Place these inside
socket cavity on L8
(North side
Secondary)

D D

Place these inside
socket cavity on L8
(Sorth side
Secondary)

Place these inside
socket cavity on L8
(North side
Primary)

Place these inside
socket cavity on L8
(Sorth side
Primary)

C C

1

2

+VCC_CORE

1

2

+VCC_CORE

1

2

+VCC_CORE

1

2

C100
10U_0805_4VAM~D

C428
10U_0805_4VAM~D

C468
10U_0805_4VAM~D

C448
10U_0805_4VAM~D

1

C429
10U_0805_4VAM~D

2

1

C138
10U_0805_4VAM~D

2

1

C140
10U_0805_4VAM~D

2

1

C432
10U_0805_4VAM~D

2

1

C98
10U_0805_4VAM~D

2

1

C447
10U_0805_4VAM~D

2

1

C139
10U_0805_4VAM~D

2

1

C426
10U_0805_4VAM~D

2

1

C430
10U_0805_4VAM~D

2

1

C470
10U_0805_4VAM~D

2

1

C446
10U_0805_4VAM~D

2

1

C427
10U_0805_4VAM~D

2

4

1

2

1

2

1

2

1

2

C99
10U_0805_4VAM~D

C469
10U_0805_4VAM~D

C466
10U_0805_4VAM~D

C431
10U_0805_4VAM~D

1

C472
10U_0805_4VAM~D

2

1

C467
10U_0805_4VAM~D

2

1

C137
10U_0805_4VAM~D

2

1

C120
10U_0805_4VAM~D

2

1

C473
10U_0805_4VAM~D

2

1

C471
10U_0805_4VAM~D

2

22uF 0805 X5R -> 85 degree C

3

1

C119
10U_0805_4VAM~D

2

1

C97
10U_0805_4VAM~D

2

1

C142
10U_0805_4VAM~D

2

1

C102
10U_0805_4VAM~D

2

1

C141
10U_0805_4VAM~D

2

1

C433
10U_0805_4VAM~D

2

2

1

High Frequence Decoupling

Near VCORE regulator.

+VCC_CORE

1

+

C365

2

7mOhm
PS CAP

1

C451

0.1U_0402_10V7K~D

2

North Side Secondary

1

+

2

330U_D_2.5VM_R6M~D

1

C416

0.1U_0402_10V7K~D

2

ESR <= 1.5m ohm
Capacitor > 1980uF

1

C462

0.1U_0402_10V7K~D

2

1

C414

0.1U_0402_10V7K~D

2

South Side Secondary

C352

B B

+1.05V_VCCP

1

C372

@

2

CRB was 270uF

A A

330U_D2E_2.5VM_R9~D

330U_D_2.5VM_R6M~D

7mOhm
PS CAP

+

1

+

2

1

+

C496

2

330U_D_2.5VM_R6M~D

7mOhm
PS CAP

1

C415

0.1U_0402_10V7K~D

2

C354

@

330U_D_2.5VM_R6M~D

7mOhm
PS CAP

1

+

2

1

2

1

+

C618

C497

2

@

330U_D_2.5VM_R6M~D

330U_D_2.5VM_R6M~D

7mOhm

7mOhm

PS CAP

PS CAP

C439

0.1U_0402_10V7K~D

The caps need change to ESR=6m ohms

Place these inside
socket cavity on L8
(North side
Secondary)

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

CPU Bypass

LA-2792

970Tuesday, Feb ru ar y 07, 2006

1

1.0

of

5

4

3

2

1

Description at page12

Note :
CFG3:17 has
internal pullup,

+1.05V_VCCP

U40B

AE35

DMIRXN0

AF39

DMIRXN1

AG35

DMIRXN2

AH39

DMIRXN3

AC35

DMIRXP0

AE39

DMIRXP1

AF35

DMIRXP2

AG39

DMIRXP3

AE37

DMITXN0

AF41

DMITXN1

AG37

DMITXN2

AH41

DMITXN3

AC37

DMITXP0

AE41

DMITXP1

AF37

DMITXP2

AG41

DMITXP3

AY35

SM_CK0

AR1

SM_CK1

AW7

SM_CK2

AW40

SM_CK3

AW35

SM_CK0#

AT1

SM_CK1#

AY7

SM_CK2#

AY40

SM_CK3#

AU20

SM_CKE0

AT20

SM_CKE1

BA29

SM_CKE2

AY29

SM_CKE3

AW13

SM_CS0#

AW12

SM_CS1#

AY21

SM_CS2#

AW21

SM_CS3#

AL20

SM_OCDCOMP0

AF10

SM_OCDCOMP1

BA13

SM_ODT0

BA12

SM_ODT1

AY20

SM_ODT2

AU21

SM_ODT3

AV9

SM_RCOMPN

AT9

SM_RCOMPP

AK1

SM_VREF0

AK41

SM_VREF1

G28

PM_BMBUSY#

F25

PM_EXTTS0#

H26

PM_EXTTS1#

G6

PM_THERMTRIP#

AH33

PWROK

AH34

RSTIN#

K28

ICH_SYNC#

CALISTOGA_FCBGA1466~D

Layout Note:
Route as short
as possible

12

R437

R435

@

@

40.2_0402_1%~D

40.2_0402_1%~D

2

12

HA3#
HA4#
HA5#
HA6#
HA7#
HA8#

HA9#
HA10#
HA11#
HA12#
HA13#
HA14#
HA15#
HA16#
HA17#
HA18#
HA19#
HA20#
HA21#
HA22#
HA23#
HA24#
HA25#
HA26#
HA27#
HA28#
HA29#
HA30#
HA31#

HREQ#0
HREQ#1
HREQ#2
HREQ#3
HREQ#4

HADSTB#0
HADSTB#1

HCLKN
HCLKP

HDSTBN#0
HDSTBN#1
HDSTBN#2
HDSTBN#3
HDSTBP#0
HDSTBP#1
HDSTBP#2
HDSTBP#3

HDINV#0
HDINV#1
HDINV#2
HDINV#3

HCPURST#

HADS#

HTRDY#

HDPWR#

HDRDY#

HDEFER#

HHITM#

HHIT#

HLOCK#

HBREQ0#

HBNR#

HBPRI#

HDBSY#

HCPUSLP#

HRS0#
HRS1#
HRS2#

A

H9
C9
E11
G11
F11
G12
F9
H11
J12
G14
D9
J14
H13
J15
F14
D12
A11
C11
A12
A13
E13
G13
F12
B12
B14
C12
A14
C14
D14

D8
G8
B8
F8
A8

B9
C13

AG1
AG2

K4
T7
Y5
AC4
K3
T6
AA5
AC5

J7
W8
U3
AB10

B7
E8
E7
J9
H8
C3
D4
D3
B3
C7
C6
F6
A7
E3

B4
E6
D6

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8

H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

H_ADSTB#0

H_ADSTB#1

H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3

H_DSTBP#0

H_DSTBP#1

H_DSTBP#2
H_DSTBP#3

H_RESET#

H_ADS#

H_TRDY#

H_DRDY#

H_DEFER#

H_HITM#

H_HIT#

H_LOCK#

H_BR0#
H_BNR#

H_BPRI#

H_DBSY#

H_CPUSLP#

H_RS#0
H_RS#1
H_RS#2

4

H_A#[3..31] 7

H_ADSTB#0 7
H_ADSTB#1 7

CLK_MCH_BCLK# 6

CLK_MCH_BCLK 6

H_DSTBN#[0..3] 7

H_DSTBP#[0..3] 7

H_DINV#0 7
H_DINV#1 7
H_DINV#2 7
H_DINV#3 7

H_RESET# 7

H_ADS# 7

H_TRDY# 7
H_DPWR# 7
H_DRDY# 7

H_DEFER# 7

H_HITM# 7
H_HIT# 7
H_LOCK# 7

H_BR0# 7
H_BNR# 7
H_BPRI# 7

H_DBSY# 7
H_CPUSLP# 7,22

H_RS#[0..2] 7

H_REQ#[0..4] 7

D D

H_D#[0..63]7

C C

+1.05V_VCCP

12

12

B B

R80

R52

54.9_0402_1%~D

54.9_0402_1%~D

12

12

R57

24.9_0402_1%~D

A A

Layout Note:
H_XRCOMP & H_YRCOMP trace width
and spacing is 10/20

H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8

H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60

H_D#61
H_D#62
H_D#63

H_VREF
H_XRCOMP
H_XSCOMP

H_YRCOMP

H_YSCOMP

H_SWNG0

H_SWNG1

R90

24.9_0402_1%~D

5

U40A

F1

HD0#

J1

HD1#

H1

HD2#

J6

HD3#

H3

HD4#

K2

HD5#

G1

HD6#

G2

HD7#

K9

HD8#

K1

HD9#

K7

HD10#

J8

HD11#

H4

HD12#

J3

HD13#

K11

HD14#

G4

HD15#

T10

HD16#

W11

HD17#

T3

HD18#

U7

HD19#

U9

HD20#

U11

HD21#

T11

HD22#

W9

HD23#

T1

HD24#

T8

HD25#

T4

HD26#

W7

HD27#

U5

HD28#

T9

HD29#

W6

HD30#

T5

HD31#

AB7

HD32#

AA9

HD33#

W4

HD34#

W3

HD35#

Y3

HD36#

Y7

HD37#

W5

HD38#

Y10

HD39#

AB8

HD40#

W2

HD41#

AA4

HD42#

AA7

HD43#

AA2

HD44#

AA6

HD45#

AA10

HD46#

Y8

HD47#

AA1

HD48#

AB4

HD49#

AC9

HD50#

AB11

HD51#

AC11

HD52#

AB3

HD53#

AC2

HD54#

AD1

HD55#

AD9

HD56#

AC1

HD57#

AD7

HD58#

AC6

HD59#

AB5

HD60#

AD10

HD61#

AD4

HD62#

AC8

HD63#

J13

HVREF0

K13

HVREF1

E1

HXRCOMP

E2

HXSCOMP

Y1

HYRCOMP

U1

HYSCOMP

E4

HXSWING

W1

HYSWING

CALISTOGA_FCBGA1466~D

HOST

+1.05V_VCCP

+1.05V_VCCP

R325

12

R85

H_SWNG1

221_0402_1%~D

12

1

R86

2

C65

100_0402_1%~D

0.1U_0402_16V4Z~D

12

R64

H_SWNG0

221_0402_1%~D

12

1

R65

2

C48

100_0402_1%~D

0.1U_0402_16V4Z~D

12

R326

H_VREF

100_0402_1%~D

12

1

C363

2

200_0402_1%~D

+1.8V_SUS

0.1U_0402_16V4Z~D

V_DDR_MCH_REF16,17,48

DMI_MRX_ITX_N023
DMI_MRX_ITX_N123
DMI_MRX_ITX_N223
DMI_MRX_ITX_N323

DMI_MRX_ITX_P023
DMI_MRX_ITX_P123
DMI_MRX_ITX_P223
DMI_MRX_ITX_P323

DMI_MTX_IRX_N023
DMI_MTX_IRX_N123
DMI_MTX_IRX_N223
DMI_MTX_IRX_N323

DMI_MTX_IRX_P023
DMI_MTX_IRX_P123
DMI_MTX_IRX_P223
DMI_MTX_IRX_P323

M_CLK_DDR016
M_CLK_DDR116
M_CLK_DDR217
M_CLK_DDR317

M_CLK_DDR#016
M_CLK_DDR#116
M_CLK_DDR#217
M_CLK_DDR#317

DDR_CKE0_DIMMA16
DDR_CKE1_DIMMA16
DDR_CKE2_DIMMB17
DDR_CKE3_DIMMB17

DDR_CS0_DIMMA#16
DDR_CS1_DIMMA#16
DDR_CS2_DIMMB#17
DDR_CS3_DIMMB#17

R142 80.6_0402_1%~D

1 2
1 2

R141 80.6_0402_1%~D

MCH_ICH_SYNC#21

V_DDR_MCH_REF

PM_BMBUSY#23
PM_EXTTS#016
PM_EXTTS#123

THERMTRIP_MCH#18

ICH_PWRGD23,42

PLTRST#21,23,28,34

V_DDR_MCH_REF

1

C425

2

@

0.1U_0402_16V4Z~D

M_ODT016
M_ODT116
M_ODT217
M_ODT317

DMI_MRX_ITX_N0
DMI_MRX_ITX_N1
DMI_MRX_ITX_N2
DMI_MRX_ITX_N3

DMI_MRX_ITX_P0
DMI_MRX_ITX_P1
DMI_MRX_ITX_P2
DMI_MRX_ITX_P3

DMI_MTX_IRX_N0
DMI_MTX_IRX_N1
DMI_MTX_IRX_N2
DMI_MTX_IRX_N3

DMI_MTX_IRX_P0
DMI_MTX_IRX_P1
DMI_MTX_IRX_P2
DMI_MTX_IRX_P3

M_CLK_DDR0
M_CLK_DDR1
M_CLK_DDR2
M_CLK_DDR3

M_CLK_DDR#0
M_CLK_DDR#1
M_CLK_DDR#2
M_CLK_DDR#3

DDR_CKE0_DIMMA
DDR_CKE1_DIMMA
DDR_CKE2_DIMMB
DDR_CKE3_DIMMB

DDR_CS0_DIMMA#
DDR_CS1_DIMMA#
DDR_CS2_DIMMB#
DDR_CS3_DIMMB#

M_OCDOCMP0
M_OCDOCMP1

M_ODT0
M_ODT1
M_ODT2
M_ODT3

SMRCOMPN
SMRCOMPP

PM_EXTTS#0
PM_EXTTS#1

ICH_PWRGD
PLTRST_R#

12

R441100_0402_1%~D

Stuff R435 & R4 37 for A1 Calistoga

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

CFG18:19 has
internal pulldown

DMI

DDR MUXING

PM

M_OCDOCMP0
M_OCDOCMP1

CPU_BSEL0

CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG16

CFG

CFG17
CFG18
CFG19
CFG20

G_CLKP
G_CLKN

D_REF_CLKN
D_REF_CLKP

CLKNC

D_REF_SSCLKN
D_REF_SSCLKP

CLK_REQ#

RESERVED1
RESERVED2
RESERVED3
RESERVED4
RESERVED5
RESERVED6
RESERVED7
RESERVED8

RESERVED9
RESERVED10
RESERVED11
RESERVED12
RESERVED13

RESERVED

PM_EXTTS#0

PM_EXTTS#1

THERMTRIP_MCH#

CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9

NC0
NC1
NC2
NC3
NC4
NC5
NC6
NC7
NC8

NC9
NC10
NC11
NC12
NC13
NC14
NC15
NC16
NC17
NC18

K16
K18
J18
F18
E15
F15
E18
D19
D16
G16
E16
D15
G15
K15
C15
H16
G18
H15
J25
K27
J26

AG33
AF33

A27
A26

C40
D41

H32

A3
A39
A4
A40
AW1
AW41
AY1
BA1
BA2
BA3
BA39
BA40
BA41
C1
AY41
B2
B41
C41
D1

T32
R32
F3
F7
AG11
AF11
H7
J19
A41
A34
D28
D27
A35

10K_0402_5%~D

@

MCH_CLKSEL1
MCH_CLKSEL2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG16
CFG17
CFG18
CFG19
CFG20

R336

R253

10K_0402_5%~D

R335
75_0402_5%~D

1 2

CLK_MCH_3GPLL# 6

+1.5V_RUN

+3.3V_RUN

12

12

CPU_BSEL0 8
MCH_CLKSEL1 6

MCH_CLKSEL2 6

T34PAD~D

T35PAD~D

CFG5 12
CFG6 12
CFG7 12

T41PAD~D

CFG9 12

T42PAD~D

CFG11 12
CFG12 12
CFG13 12

T43PAD~D

T44PAD~D

CFG16 12

T45PAD~D

CFG18 12
CFG19 12
CFG20 12

CLK_MCH_3GPLL 6

CLK_3GPLLREQ# 6

+1.05V_VCCP

DELL CONFIDENTIAL/PROPRIETARY

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

Calistoga(1 of 6)

LA-2792

1

10 70Tuesday, Feb ru ar y 07, 2006

of

1.0

5

4

3

2

1

D D

U40D

DDR_A_BS016
DDR_A_BS116
DDR_A_BS216 DDR_B_BS217

DDR_A_DM[0..7]16

DDR_A_DQS[0..7]16

C C

B B

DDR_A_DQS#[0..7]16

DDR_A_MA[0..13]16

DDR_A_CAS#16
DDR_A_RAS#16
DDR_A_WE#16

T2022 PAD~D
T2024 PAD~D

DDR_A_BS0
DDR_A_BS1
DDR_A_BS2

DDR_A_DM0
DDR_A_DM1
DDR_A_DM2
DDR_A_DM3
DDR_A_DM4
DDR_A_DM5
DDR_A_DM6
DDR_A_DM7

DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7

DDR_A_DQS#0
DDR_A_DQS#1
DDR_A_DQS#2
DDR_A_DQS#3
DDR_A_DQS#4
DDR_A_DQS#5
DDR_A_DQS#6
DDR_A_DQS#7

DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5

DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11 DDR_B_MA11
DDR_A_MA12
DDR_A_MA13

DDR_A_CAS#
DDR_A_RAS#
DDR_A_WE#
SA_RCVENIN#

SA_RCVENOUT#

AU12

SA_BS0

AV14

SA_BS1

BA20

SA_BS2

AJ33

SA_DM0

AM35

SA_DM1

AL26

SA_DM2

AN22

SA_DM3

AM14

SA_DM4

AL9

SA_DM5

AR3

SA_DM6

AH4

SA_DM7

AK33

SA_DQS0

AT33

SA_DQS1

AN28

SA_DQS2

AM22

SA_DQS3

AN12

SA_DQS4

AN8

SA_DQS5

AP3

SA_DQS6

AG5

SA_DQS7

AK32

SA_DQS0#

AU33

SA_DQS1#

AN27

SA_DQS2#

AM21

SA_DQS3#

AM12

SA_DQS4#

AL8

SA_DQS5#

AN3

SA_DQS6#

AH5

SA_DQS7#

AY16

SA_MA0

AU14

SA_MA1

AW16

SA_MA2

BA16

SA_MA3

BA17

SA_MA4

AU16

SA_MA5

AV17

SA_MA6

AU17

SA_MA7

AW17

SA_MA8

AT16

SA_MA9

AU13

SA_MA10

AT17

SA_MA11

AV20

SA_MA12

AV12

SA_MA13

AY13

SA_CAS#

AW14

SA_RAS#

AY14

SA_WE#

AK23

SA_RCVENIN#

AK24

SA_RCVENOUT#

CALISTOGA_FCBGA1466~D

DDR SYS MEMORY A

D

SA_DQ0
SA_DQ1
SA_DQ2
SA_DQ3
SA_DQ4
SA_DQ5
SA_DQ6
SA_DQ7
SA_DQ8

SA_DQ9
SA_DQ10
SA_DQ11
SA_DQ12
SA_DQ13
SA_DQ14
SA_DQ15
SA_DQ16
SA_DQ17
SA_DQ18
SA_DQ19
SA_DQ20
SA_DQ21
SA_DQ22
SA_DQ23
SA_DQ24
SA_DQ25
SA_DQ26
SA_DQ27
SA_DQ28
SA_DQ29
SA_DQ30
SA_DQ31
SA_DQ32
SA_DQ33
SA_DQ34
SA_DQ35
SA_DQ36
SA_DQ37
SA_DQ38
SA_DQ39
SA_DQ40
SA_DQ41
SA_DQ42
SA_DQ43
SA_DQ44
SA_DQ45
SA_DQ46
SA_DQ47
SA_DQ48
SA_DQ49
SA_DQ50
SA_DQ51
SA_DQ52
SA_DQ53
SA_DQ54
SA_DQ55
SA_DQ56
SA_DQ57
SA_DQ58
SA_DQ59
SA_DQ60
SA_DQ61
SA_DQ62
SA_DQ63

AJ35
AJ34
AM31
AM33
AJ36
AK35
AJ32
AH31
AN35
AP33
AR31
AP31
AN38
AM36
AM34
AN33
AK26
AL27
AM26
AN24
AK28
AL28
AM24
AP26
AP23
AL22
AP21
AN20
AL23
AP24
AP20
AT21
AR12
AR14
AP13
AP12
AT13
AT12
AL14
AL12
AK9
AN7
AK8
AK7
AP9
AN9
AT5
AL5
AY2
AW2
AP1
AN2
AV2
AT3
AN1
AL2
AG7
AF9
AG4
AF6
AG9
AH6
AF4
AF8

DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63

DDR_B_DQS[0..7]17

DDR_B_DQS#[0..7]17

DDR_B_MA[0..13]17

DDR_B_BS017
DDR_B_BS117

DDR_B_DM[0..7]17

DDR_B_CAS#17
DDR_B_RAS#17
DDR_B_WE#17

T2023 PAD~D
T2025 PAD~D

DDR_B_BS0
DDR_B_BS1
DDR_B_BS2

DDR_B_DM0
DDR_B_DM1
DDR_B_DM2
DDR_B_DM3
DDR_B_DM4
DDR_B_DM5
DDR_B_DM6
DDR_B_DM7

DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4
DDR_B_DQS5
DDR_B_DQS6
DDR_B_DQS7

DDR_B_DQS#0
DDR_B_DQS#1
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS#4
DDR_B_DQS#5
DDR_B_DQS#6
DDR_B_DQS#7

DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6DDR_A_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10

DDR_B_MA12
DDR_B_MA13

DDR_B_CAS#
DDR_B_RAS#
DDR_B_WE#
SB_RCVENIN#
SB_RCVENOUT#

E

U40E

AT24

SB_BS0

AV23

SB_BS1

AY28

SB_BS2

AK36

SB_DM0

AR38

SB_DM1

AT36

SB_DM2

BA31

SB_DM3

AL17

SB_DM4

AH8

SB_DM5

BA5

SB_DM6

AN4

SB_DM7

AM39

SB_DQS0

AT39

SB_DQS1

AU35

SB_DQS2

AR29

SB_DQS3

AR16

SB_DQS4

AR10

SB_DQS5

AR7

SB_DQS6

AN5

SB_DQS7

AM40

SB_DQS0#

AU39

SB_DQS1#

AT35

SB_DQS2#

AP29

SB_DQS3#

AP16

SB_DQS4#

AT10

SB_DQS5#

AT7

SB_DQS6#

AP5

SB_DQS7#

AY23

SB_MA0

AW24

SB_MA1

AY24

SB_MA2

AR28

SB_MA3

AT27

SB_MA4

AT28

SB_MA5

AU27

SB_MA6

AV28

SB_MA7

AV27

SB_MA8

AW27

SB_MA9

AV24

SB_MA10

BA27

SB_MA11

AY27

SB_MA12

AR23

SB_MA13

AR24

SB_CAS#

AU23

SB_RAS#

AR27

SB_WE#

AK16

SB_RCVENIN#

AK18

SB_RCVENOUT#

CALISTOGA_FCBGA1466~D

AK39

SB_DQ0

AJ37

SB_DQ1

AP39

SB_DQ2

AR41

SB_DQ3

AJ38

SB_DQ4

AK38

SB_DQ5

AN41

SB_DQ6

AP41

SB_DQ7

AT40

SB_DQ8

AV41

SB_DQ9

AU38

SB_DQ10

AV38

SB_DQ11

AP38

SB_DQ12

AR40

SB_DQ13

AW38

SB_DQ14

AY38

SB_DQ15

BA38

SB_DQ16

AV36

SB_DQ17

AR36

SB_DQ18

AP36

SB_DQ19

BA36

SB_DQ20

AU36

SB_DQ21

AP35

SB_DQ22

AP34

SB_DQ23

AY33

SB_DQ24

BA33

SB_DQ25

AT31

SB_DQ26

AU29

SB_DQ27

AU31

SB_DQ28

AW31

SB_DQ29

AV29

SB_DQ30

AW29

SB_DQ31

AM19

SB_DQ32

AL19

SB_DQ33

AP14

SB_DQ34

AN14

SB_DQ35

AN17

SB_DQ36

AM16

SB_DQ37

AP15

SB_DQ38

AL15

SB_DQ39
SB_DQ40
SB_DQ41
SB_DQ42
SB_DQ43
SB_DQ44
SB_DQ45
SB_DQ46
SB_DQ47
SB_DQ48
SB_DQ49
SB_DQ50
SB_DQ51
SB_DQ52
SB_DQ53
SB_DQ54
SB_DQ55
SB_DQ56
SB_DQ57
SB_DQ58
SB_DQ59
SB_DQ60
SB_DQ61
SB_DQ62
SB_DQ63

AJ11
AH10
AJ9
AN10
AK13
AH11
AK10
AJ8
BA10
AW10
BA4
AW4
AY10
AY9
AW5
AY5
AV4
AR5
AK4
AK3
AT4
AK5
AJ5
AJ3

DDR SYS MEMORY B

DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63

DDR_B_D[0..63] 17DDR_A_D[0..63] 16

A A

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

Calistogo(2 of 6)

LA-2792

11 70Tuesday, Feb ru ar y 07, 2006

1

1.0

of

5

4

3

2

1

Strap Pin Table

C

U40C

H27

SDVOCTRL_DATA

H28

SDVOCTRL_CLK

B37

D D

+1.5V_RUN

C C

+1.05V_VCCP

B B

A A

5

LA_DATA0

B34

LA_DATA1

A36

LA_DATA2

C37

LA_DATA#0

B35

LA_DATA#1

A37

LA_DATA#2

F30

LB_DATA0

D29

LB_DATA1

F28

LB_DATA2

G30

LB_DATA#0

D30

LB_DATA#1

F29

LB_DATA#2

A32

LA_CLK

A33

LA_CLK#

E26

LB_CLK

E27

LB_CLK#

D32

LBKLT_CTL

J30

LBKLT_EN

H30

LCTLA_CLK

H29

LCTLB_DATA

G26

LDDC_CLK

G25

LDDC_DATA

F32

LVDD_EN

B38

LIBG

C35

LVBG

C33

LVREFH

C32

LVREFL

A16

TVDAC_A

C18

TVDAC_B

A19

TVDAC_C

J20

TV_IREF

B16

TV_IRTNA

B18

TV_IRTNB

B19

TV_IRTNC

J29

TV_DCONSEL1

K30

TV_DCONSEL0

C26

DDCCLK

C25

DDCDATA

H23

VSYNC

G23

HSYNC

E23

BLUE

D23

BLUE#

C22

GREEN

B22

GREEN#

A21

RED

B21

RED#

J22

CRT_IREF

CALISTOGA_FCBGA1466~D

LVDS

TV CRT

4

EXP_COMPI

EXP_COMPO

EXP_RXN0
EXP_RXN1
EXP_RXN2
EXP_RXN3
EXP_RXN4
EXP_RXN5
EXP_RXN6
EXP_RXN7
EXP_RXN8

EXP_RXN9
EXP_RXN10
EXP_RXN11
EXP_RXN12
EXP_RXN13
EXP_RXN14
EXP_RXN15

EXP_RXP0

EXP_RXP1

EXP_RXP2

EXP_RXP3

EXP_RXP4

EXP_RXP5

EXP_RXP6

EXP_RXP7

EXP_RXP8

EXP_RXP9
EXP_RXP10
EXP_RXP11
EXP_RXP12
EXP_RXP13
EXP_RXP14
EXP_RXP15

EXP_TXN0

EXP_TXN1

EXP_TXN2

EXP_TXN3

EXP_TXN4

EXP_TXN5

EXP_TXN6

EXP_TXN7

EXP_TXN8

PCI-EXPRESS GRAPHICS

EXP_TXN9
EXP_TXN10
EXP_TXN11
EXP_TXN12
EXP_TXN13
EXP_TXN14
EXP_TXN15

EXP_TXP0

EXP_TXP1

EXP_TXP2

EXP_TXP3

EXP_TXP4

EXP_TXP5

EXP_TXP6

EXP_TXP7

EXP_TXP8

EXP_TXP9

EXP_TXP10
EXP_TXP11
EXP_TXP12
EXP_TXP13
EXP_TXP14
EXP_TXP15

PEGCOMP

D40
D38

PEG_MRX_GTX_N0

F34

PEG_MRX_GTX_N1

G38

PEG_MRX_GTX_N2

H34

PEG_MRX_GTX_N3

J38

PEG_MRX_GTX_N4

L34

PEG_MRX_GTX_N5

M38

PEG_MRX_GTX_N6

N34

PEG_MRX_GTX_N7

P38

PEG_MRX_GTX_N8

R34

PEG_MRX_GTX_N9

T38

PEG_MRX_GTX_N10

V34

PEG_MRX_GTX_N11

W38

PEG_MRX_GTX_N12

Y34

PEG_MRX_GTX_N13

AA38

PEG_MRX_GTX_N14

AB34

PEG_MRX_GTX_N15

AC38

PEG_MRX_GTX_P0

D34

PEG_MRX_GTX_P1

F38

PEG_MRX_GTX_P2

G34

PEG_MRX_GTX_P3

H38

PEG_MRX_GTX_P4

J34

PEG_MRX_GTX_P5

L38

PEG_MRX_GTX_P6

M34

PEG_MRX_GTX_P7

N38

PEG_MRX_GTX_P8

P34

PEG_MRX_GTX_P9

R38

PEG_MRX_GTX_P10

T34

PEG_MRX_GTX_P11

V38

PEG_MRX_GTX_P12

W34

PEG_MRX_GTX_P13

Y38

PEG_MRX_GTX_P14

AA34

PEG_MRX_GTX_P15

AB38

PEG_MTX_GRX_C_N0

F36

PEG_MTX_GRX_C_N1

G40

PEG_MTX_GRX_C_N2

H36

PEG_MTX_GRX_C_N3

J40

PEG_MTX_GRX_C_N4

L36

PEG_MTX_GRX_C_N5

M40

PEG_MTX_GRX_C_N6

N36

PEG_MTX_GRX_C_N7

P40

PEG_MTX_GRX_C_N8

R36

PEG_MTX_GRX_C_N9

T40

PEG_MTX_GRX_C_N10

V36

PEG_MTX_GRX_C_N11

W40

PEG_MTX_GRX_C_N12

Y36

PEG_MTX_GRX_C_N13

AA40

PEG_MTX_GRX_C_N14

AB36

PEG_MTX_GRX_C_N15

AC40

PEG_MTX_GRX_C_P0

D36

PEG_MTX_GRX_C_P1

F40

PEG_MTX_GRX_C_P2

G36

PEG_MTX_GRX_C_P3

H40

PEG_MTX_GRX_C_P4

J36

PEG_MTX_GRX_C_P5

L40

PEG_MTX_GRX_C_P6

M36

PEG_MTX_GRX_C_P7

N40

PEG_MTX_GRX_C_P8

P36

PEG_MTX_GRX_C_P9

R40

PEG_MTX_GRX_C_P10

T36

PEG_MTX_GRX_C_P11

V40

PEG_MTX_GRX_C_P12

W36

PEG_MTX_GRX_C_P13

Y40

PEG_MTX_GRX_C_P14

AA36

PEG_MTX_GRX_C_P15

AB40

R1493

24.9_0402_1%~D

1 2

+1.5VRUN_PCIE

PEG_MTX_GRX_C_P0
PEG_MTX_GRX_C_N0

PEG_MTX_GRX_C_P1
PEG_MTX_GRX_C_N1

PEG_MTX_GRX_C_P2
PEG_MTX_GRX_C_N2

PEG_MTX_GRX_C_P3
PEG_MTX_GRX_C_N3

PEG_MTX_GRX_C_P4
PEG_MTX_GRX_C_N4

PEG_MTX_GRX_C_P5
PEG_MTX_GRX_C_N5

PEG_MTX_GRX_C_P6
PEG_MTX_GRX_C_N6

PEG_MTX_GRX_C_P7
PEG_MTX_GRX_C_N7

PEG_MTX_GRX_C_P8
PEG_MTX_GRX_C_N8

PEG_MTX_GRX_C_P9
PEG_MTX_GRX_C_N9

PEG_MTX_GRX_C_P10
PEG_MTX_GRX_C_N10

PEG_MTX_GRX_C_P11
PEG_MTX_GRX_C_N11

PEG_MTX_GRX_C_P12
PEG_MTX_GRX_C_N12

PEG_MTX_GRX_C_P13
PEG_MTX_GRX_C_N13

PEG_MTX_GRX_C_P14
PEG_MTX_GRX_C_N14

PEG_MTX_GRX_C_P15
PEG_MTX_GRX_C_N15

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

CFG5

CFG6

CFG7

CFG9

CFG11

CFG[13:12]

CFG16

(FSB Dynamic ODT)

CFG18

(VCC Select)

CFG19

(DMI Lane Reversal)

SDVO_CTRLDATA

CFG20

(PCIE/SDVO select)

C1561 0.1U_0402_16V4Z~D

1 2

C1563 0.1U_0402_16V4Z~D

C1565 0.1U_0402_16V4Z~D

C1567 0.1U_0402_16V4Z~D

C1569 0.1U_0402_16V4Z~D

C1571 0.1U_0402_16V4Z~D

C1573 0.1U_0402_16V4Z~D

C1575 0.1U_0402_16V4Z~D

C1577 0.1U_0402_16V4Z~D

C1579 0.1U_0402_16V4Z~D

C1581 0.1U_0402_16V4Z~D

C1583 0.1U_0402_16V4Z~D

C1585 0.1U_0402_16V4Z~D

C1587 0.1U_0402_16V4Z~D

C1589 0.1U_0402_16V4Z~D

C1591 0.1U_0402_16V4Z~D

C1562 0.1U_0402_16V4Z~D

1 2

C1564 0.1U_0402_16V4Z~D

1 2

C1566 0.1U_0402_16V4Z~D

1 2

C1568 0.1U_0402_16V4Z~D

1 2

C1570 0.1U_0402_16V4Z~D

1 2

C1572 0.1U_0402_16V4Z~D

1 2

C1574 0.1U_0402_16V4Z~D

1 2

C1576 0.1U_0402_16V4Z~D

1 2

C1578 0.1U_0402_16V4Z~D

1 2

C1580 0.1U_0402_16V4Z~D

1 2

C1582 0.1U_0402_16V4Z~D

1 2

C1584 0.1U_0402_16V4Z~D

1 2

C1586 0.1U_0402_16V4Z~D

1 2

C1588 0.1U_0402_16V4Z~D

1 2

C1590 0.1U_0402_16V4Z~D

1 2

C1592 0.1U_0402_16V4Z~D

Low = DMI x 2
High = DMI x 4
LOW = Moby Dick
HIGH = Calistoga
Low = DT/Transportable CPU
High = Mobile CPU
Low = Reverse Lane
High = Normal Operation

00 = Reserved
01 = XOR Mode Enabled
10 = All Z Mode Enabled
11 = Normal Operation

(Default)

Low = Disabled
High = Enabled

Low = 1.05V (Default)
High = 1.5V
Low = Normal

Operation (Default):
Lane number in Order

High = Reverse Lane

Low = No SDVO Device Present
High = SDVO Device Present

Low = Only PCIE or SDVO is
operational.

High = PCIE/SDVO are operating
simu.

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

(Default)

PEG_MTX_GRX_P0
PEG_MTX_GRX_N0

PEG_MTX_GRX_P1
PEG_MTX_GRX_N1

PEG_MTX_GRX_P2
PEG_MTX_GRX_N2

PEG_MTX_GRX_P3
PEG_MTX_GRX_N3

PEG_MTX_GRX_P4
PEG_MTX_GRX_N4

PEG_MTX_GRX_P5
PEG_MTX_GRX_N5

PEG_MTX_GRX_P6
PEG_MTX_GRX_N6

PEG_MTX_GRX_P7
PEG_MTX_GRX_N7

PEG_MTX_GRX_P8
PEG_MTX_GRX_N8

PEG_MTX_GRX_P9
PEG_MTX_GRX_N9

PEG_MTX_GRX_P10
PEG_MTX_GRX_N10

PEG_MTX_GRX_P11
PEG_MTX_GRX_N11

PEG_MTX_GRX_P12
PEG_MTX_GRX_N12

PEG_MTX_GRX_P13
PEG_MTX_GRX_N13

PEG_MTX_GRX_P14
PEG_MTX_GRX_N14

PEG_MTX_GRX_P15
PEG_MTX_GRX_N15

2

*

*

*

*

*

*

(Default)

R307 2.2K_0402_5%~D@

*

*

CFG510
CFG610
CFG710
CFG910
CFG1110
CFG1210
CFG1310
CFG1610

1 2

R67 2.2K_0402_5%~D@

1 2

R281 2.2K_0402_5%~D@

1 2

R282 2.2K_0402_5%~D@

1 2

R357 2.2K_0402_5%~D@

1 2

R288 2.2K_0402_5%~D@

1 2

R323 2.2K_0402_5%~D @

1 2

R346 2.2K_0402_5%~D@

1 2

CFG[3:17] have internal pullup

*

1 2
1 2

1 2

@

R308 1K_0402_5%~D

CFG1810
CFG1910

R306 1K_0402_5%~D@

CFG2010

R310 1K_0402_5%~D@

+3.3V_RUN

CFG[18:20] have internal pulldown

*

PEG_MRX_GTX_P[0:15]
PEG_MRX_GTX_N[0:15]

PEG_MTX_GRX_P[0:15]
PEG_MTX_GRX_N[0:15]

PEG_MRX_GTX_P[0:15] 52
PEG_MRX_GTX_N[0:15] 52

PEG_MTX_GRX_P[0:15] 52
PEG_MTX_GRX_N[0:15] 52

DELL CONFIDENTIAL/PROPRIETARY

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

Calistoga(3 of 6)

LA-2792

12 70Tuesday, Feb ru ar y 07, 2006

1

1.0

of

5

H

+1.05V_VCCP

CRB 270uF

D D

C391

C C

C118

0.22U_0402_10V4Z~D

B B

1

+

C411

2

220U_V_4VM_R45~D

1

1

C390

2

2

4.7U_0603_6.3V4Z~D

2.2U_0603_6.3V6K~D

U40_A6

1

C316

2

0.47U_0402_16V4Z~D

1

U40_D2

2

1

C164

U40_AB1

2

1

C435

0.22U_0402_10V4Z~D

2

0.47U_0402_16V4Z~D

+1.5V_RUN

U40H

AC14

VTT0

AB14

VTT1

W14

VTT2

V14

VTT3

T14

VTT4

R14

VTT5

P14

VTT6

N14

VTT7

M14

VTT8

L14

VTT9

AD13

VTT10

AC13

VTT11

AB13

VTT12

AA13

VTT13

Y13

VTT14

W13

VTT15

V13

VTT16

U13

VTT17

T13

VTT18

R13

VTT19

N13

VTT20

M13

VTT21

L13

VTT22

AB12

VTT23

AA12

VTT24

Y12

VTT25

W12

VTT26

V12

VTT27

U12

VTT28

T12

VTT29

R12

VTT30

P12

VTT31

N12

VTT32

M12

VTT33

L12

VTT34

R11

VTT35

P11

VTT36

N11

VTT37

M11

VTT38

R10

VTT39

P10

VTT40

N10

VTT41

M10

VTT42

P9

VTT43

N9

VTT44

M9

VTT45

R8

VTT46

P8

VTT47

N8

VTT48

M8

VTT49

P7

VTT50

N7

VTT51

M7

VTT52

R6

VTT53

P6

VTT54

M6

VTT55

A6

VTT56

R5

VTT57

P5

VTT58

N5

VTT59

M5

VTT60

P4

VTT61

N4

VTT62

M4

VTT63

R3

VTT64

P3

VTT65

N3

VTT66

M3

VTT67

R2

VTT68

P2

VTT69

M2

VTT70

D2

VTT71

AB1

VTT72

R1

VTT73

P1

VTT74

N1

VTT75

M1

VTT76

AG14

VCCAUX32

AF14

VCCAUX33

AE14

VCCAUX34

Y14

VCCAUX35

AF13

VCCAUX36

AE13

VCCAUX37

AF12

VCCAUX38

AE12

VCCAUX39

AD12

VCCAUX40

CALISTOGA_FCBGA1466~D

P O W E R

VCC_SYNC

VCCTX_LVDS0
VCCTX_LVDS1
VCCTX_LVDS2

VCC3G0
VCC3G1
VCC3G2
VCC3G3
VCC3G4
VCC3G5
VCC3G6

VCCA_3GPLL

VCCA_3GBG
VSSA_3GBG

VCCA_CRTDAC0
VCCA_CRTDAC1
VSSA_CRTDAC2

VCCA_DPLLA
VCCA_DPLLB

VCCA_HPLL

VCCA_LVDS
VSSA_LVDS

VCCA_MPLL

VCCA_TVBG

VSSA_TVBG

VCCA_TVDACA0
VCCA_TVDACA1
VCCA_TVDACB0
VCCA_TVDACB1
VCCA_TVDACC0
VCCA_TVDACC1

VCCD_HMPLL0
VCCD_HMPLL1

VCCD_LVDS0
VCCD_LVDS1
VCCD_LVDS2

VCCD_TVDAC

VCCDQ_TVDAC

VCCHV0
VCCHV1
VCCHV2

VCCAUX0
VCCAUX1
VCCAUX2
VCCAUX3
VCCAUX4
VCCAUX5
VCCAUX6
VCCAUX7
VCCAUX8

VCCAUX9
VCCAUX10
VCCAUX11
VCCAUX12
VCCAUX13
VCCAUX14
VCCAUX15
VCCAUX16
VCCAUX17
VCCAUX18
VCCAUX19
VCCAUX20
VCCAUX21
VCCAUX22
VCCAUX23
VCCAUX24
VCCAUX25
VCCAUX26
VCCAUX27
VCCAUX28
VCCAUX29
VCCAUX30
VCCAUX31

H22

B30
C30
A30

AB41
AJ41
L41
N41
R41
V41
Y41

AC33
G41
H41

E21
F21
G21

B26
C39
AF1

A38
B39

AF2
H20

G20

E19
F19
C20
D20
E20
F20

AH1
AH2

A28
B28
C28

D21
H19

A23
B23
B25

AK31
AF31
AE31
AC31
AL30
AK30
AJ30
AH30
AG30
AF30
AE30
AD30
AC30
AG29
AF29
AE29
AD29
AC29
AG28
AF28
AE28
AH22
AJ21
AH21
AJ20
AH20
AH19
P19
P16
AH15
P15
AH14

4

Should be placed on top

+1.5V_RUN

1

2

C49

C437

0.1U_0402_16V4Z~D

+1.5VRUN_PCIE

1

+

2

220U_V_4VM_R45~D

C336

0.1U_0402_16V4Z~D

BLM21PG600SN1D_0805~D

1

1

C59

C53

2

2

10U_0805_4VAM~D

C37

0.022U_0402_16V7K~D

+3.3V_RUN

1

1

C385

2

2

10U_0805_4VAM~D

W=30 mils

+1.5VRUN_3GPLL
+2.5V_RUN

+1.05V_VCCP

+1.5VRUN_DPLLA
+1.5VRUN_DPLLB
+1.5VRUN_HPLL

+1.5VRUN_MPLL
+1.5V_RUN

+1.5V_RUN

+1.5VRUN_QTVDAC

C404 should be placed in cavity

+1.5VRUN_3GPLL

C404

0.1U_0402_16V4Z~D

1

2

0.5_0805_1%~D

1

C311

2

10U_0805_4VAM~D

R267

1 2

12

L35

10U_0805_4VAM~D

BLM18PG181SN1_0603~D

1

1

C24

2

2

0.1U_0402_16V4Z~D

L34

BLM18PG181SN1_0603~D

3

+2.5V_RUN

1

+1.5V_RUN

L11

+1.5V_RUN

12

1

C332

2

0.1U_0402_16V4Z~D

12

C345

0.1U_0402_16V4Z~D

2

Route +2.5VRUN from GMCH pinG41 to
decoupling cap (C345)<200mil to the edge.

+1.5V_RUN+1.5VRUN_QTVDAC

+1.5VRUN_DPLLA +1.5VRUN_DPLLB

1

C413

2

1

2

L39

BLM18AG121SN1D_0603~D

1

C94
22U_0805_6.3VAM~D

2

0.1U_0402_16V4Z~D

R1748

0_0805_5%~D

C322

0.1U_0402_16V4Z~D

2

+1.5VRUN_MPLL+1.5VRUN_HPLL

12

+1.5V_RUN

12

+1.5V_RUN

45mA Max.45mA Max.

1

C418

2

0.1U_0402_16V4Z~D

40mA Max.40mA Max.

1

2

BLM18AG121SN1D_0603~D

1

C419
22U_0805_6.3VAM~D

2

0_0805_5%~D

C331

0.1U_0402_16V4Z~D

L38

12

R1749

12

1

+1.5V_RUN

+1.5V_RUN

A A

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

Calistoga(4 of 6)

LA-2792

13 70Tuesday, February 07, 2006

1

1.0

of

5

4

3

2

1

F

+1.05V_VCCP

D D

1

1

1

C383

C358

C379

2

0.22U_0402_10V4Z~D

1

C366

C C

2

10U_0805_4VAM~D

C367

C423

0.22U_0402_10V4Z~D

10U_0805_4VAM~D

220U_V_4VM_R45~D

2

2

0.22U_0402_10V4Z~D

1

1

C368

2

2

1U_0603_10V4Z~D

1

+

2

CRB 270uF

1

B B

A A

C620

+

2

220U_V_4VM_R45~D

+1.05V_VCCP

U40F

AD27

VCC_NCTF0

AC27

VCC_NCTF1

AB27

VCC_NCTF2

AA27

VCC_NCTF3

Y27

VCC_NCTF4

W27

VCC_NCTF5

V27

VCC_NCTF6

U27

VCC_NCTF7

T27

VCC_NCTF8

R27

VCC_NCTF9

AD26

VCC_NCTF10

AC26

VCC_NCTF11

AB26

VCC_NCTF12

AA26

VCC_NCTF13

Y26

VCC_NCTF14

W26

VCC_NCTF15

V26

VCC_NCTF16

U26

VCC_NCTF17

T26

VCC_NCTF18

R26

VCC_NCTF19

AD25

VCC_NCTF20

AC25

VCC_NCTF21

AB25

VCC_NCTF22

AA25

VCC_NCTF23

Y25

VCC_NCTF24

W25

VCC_NCTF25

V25

VCC_NCTF26

U25

VCC_NCTF27

T25

VCC_NCTF28

R25

VCC_NCTF29

AD24

VCC_NCTF30

AC24

VCC_NCTF31

AB24

VCC_NCTF32

AA24

VCC_NCTF33

Y24

VCC_NCTF34

W24

VCC_NCTF35

V24

VCC_NCTF36

U24

VCC_NCTF37

T24

VCC_NCTF38

R24

VCC_NCTF39

AD23

VCC_NCTF40

V23

VCC_NCTF41

U23

VCC_NCTF42

T23

VCC_NCTF43

R23

VCC_NCTF44

AD22

VCC_NCTF45

V22

VCC_NCTF46

U22

VCC_NCTF47

T22

VCC_NCTF48

R22

VCC_NCTF49

AD21

VCC_NCTF50

V21

VCC_NCTF51

U21

VCC_NCTF52

T21

VCC_NCTF53

R21

VCC_NCTF54

AD20

VCC_NCTF55

V20

VCC_NCTF56

U20

VCC_NCTF57

T20

VCC_NCTF58

R20

VCC_NCTF59

AD19

VCC_NCTF60

V19

VCC_NCTF61

U19

VCC_NCTF62

T19

VCC_NCTF63

AD18

VCC_NCTF64

AC18

VCC_NCTF65

AB18

VCC_NCTF66

AA18

VCC_NCTF67

Y18

VCC_NCTF68

W18

VCC_NCTF69

V18

VCC_NCTF70

U18

VCC_NCTF71

T18

VCC_NCTF72

M19

VCC100

L19

VCC101

N18

VCC102

M18

VCC103

L18

VCC104

P17

VCC105

N17

VCC106

M17

VCC107

N16

VCC108

M16

VCC109

L16

VCC110

CALISTOGA_FCBGA1466~D

VCCAUX_NCTF0
VCCAUX_NCTF1
VCCAUX_NCTF2
VCCAUX_NCTF3
VCCAUX_NCTF4
VCCAUX_NCTF5
VCCAUX_NCTF6
VCCAUX_NCTF7
VCCAUX_NCTF8

VCCAUX_NCTF9
VCCAUX_NCTF10
VCCAUX_NCTF11
VCCAUX_NCTF12
VCCAUX_NCTF13
VCCAUX_NCTF14
VCCAUX_NCTF15
VCCAUX_NCTF16
VCCAUX_NCTF17
VCCAUX_NCTF18
VCCAUX_NCTF19
VCCAUX_NCTF20
VCCAUX_NCTF21
VCCAUX_NCTF22
VCCAUX_NCTF23
VCCAUX_NCTF24
VCCAUX_NCTF25
VCCAUX_NCTF26
VCCAUX_NCTF27
VCCAUX_NCTF28
VCCAUX_NCTF29
VCCAUX_NCTF30
VCCAUX_NCTF31
VCCAUX_NCTF32
VCCAUX_NCTF33
VCCAUX_NCTF34
VCCAUX_NCTF35
VCCAUX_NCTF36

P O W E R

VCCAUX_NCTF37
VCCAUX_NCTF38
VCCAUX_NCTF39
VCCAUX_NCTF40
VCCAUX_NCTF41
VCCAUX_NCTF42
VCCAUX_NCTF43
VCCAUX_NCTF44
VCCAUX_NCTF45
VCCAUX_NCTF46
VCCAUX_NCTF47
VCCAUX_NCTF48
VCCAUX_NCTF49
VCCAUX_NCTF50
VCCAUX_NCTF51
VCCAUX_NCTF52
VCCAUX_NCTF53
VCCAUX_NCTF54
VCCAUX_NCTF55
VCCAUX_NCTF56
VCCAUX_NCTF57

VSS_NCTF0
VSS_NCTF1
VSS_NCTF2
VSS_NCTF3
VSS_NCTF4
VSS_NCTF5
VSS_NCTF6
VSS_NCTF7
VSS_NCTF8

VSS_NCTF9
VSS_NCTF10
VSS_NCTF11
VSS_NCTF12

VCC_SM100

VCC_SM101

VCC_SM102

VCC_SM103

VCC_SM104

VCC_SM105

VCC_SM106

VCC_SM107

+1.5V_RUN

AG27
AF27
AG26
AF26
AG25
AF25
AG24
AF24
AG23
AF23
AG22
AF22
AG21
AF21
AG20
AF20
AG19
AF19
R19
AG18
AF18
R18
AG17
AF17
AE17
AD17
AB17
AA17
W17
V17
T17
R17
AG16
AF16
AE16
AD16
AC16
AB16
AA16
Y16
W16
V16
U16
T16
R16
AG15
AF15
AE15
AD15
AC15
AB15
AA15
Y15
W15
V15
U15
T15
R15

AE27
AE26
AE25
AE24
AE23
AE22
AE21
AE20
AE19
AE18
AC17
Y17
U17

VCCSM_LF2
VCCSM_LF1

+1.8V_SUS

1

C613

2

0.47U_0402_16V4Z~D

C614

1

2

0.47U_0402_16V4Z~D

AR6
AP6
AN6
AL6
AK6
AJ6
AV1
AJ1

Place near U40.AV1 & AJ1

G

+1.05V_VCCP

AA33

W33

P33
N33

AA32

Y32

W32

V32
P32
N32

M32

AA31

W31

V31
T31
R31
P31
N31

M31

AA30

Y30

W30

V30
U30
T30
R30
P30
N30

M30

AA29

Y29

W29

V29
U29
R29
P29

M29

AB28
AA28

Y28
V28
U28
T28
R28
P28
N28

M28

P27
N27

M27

P26
N26

N25

M25

P24
N24

M24
AB23
AA23

Y23
P23
N23

M23
AC22

AB22

Y22

W22

P22
N22

M22
AC21

AA21

W21

N21

M21
AC20

AB20

Y20

W20

P20
N20

M20
AB19

AA19

Y19
N19

U40G

VCC0
VCC1
VCC2
VCC3

L33

VCC4

J33

VCC5
VCC6
VCC7
VCC8
VCC9
VCC10
VCC11
VCC12

L32

VCC13

J32

VCC14
VCC15
VCC16
VCC17
VCC18
VCC19
VCC20
VCC21
VCC22
VCC23
VCC24
VCC25
VCC26
VCC27
VCC28
VCC29
VCC30
VCC31
VCC32

L30

L29

L28

L27

L26

L25

L23

L22

L21

L20

P O W E R

VCC33
VCC34
VCC35
VCC36
VCC37
VCC38
VCC39
VCC40
VCC41
VCC42
VCC43
VCC44
VCC45
VCC46
VCC47
VCC48
VCC49
VCC50
VCC51
VCC52
VCC53
VCC54
VCC55
VCC56
VCC57
VCC58
VCC59
VCC60
VCC61
VCC62
VCC63
VCC64
VCC65
VCC66
VCC67
VCC68
VCC69
VCC70
VCC71
VCC72
VCC73
VCC74
VCC75
VCC76
VCC77
VCC78
VCC79
VCC80
VCC81
VCC82
VCC83
VCC84
VCC85
VCC86
VCC87
VCC88
VCC89
VCC90
VCC91
VCC92
VCC93
VCC94
VCC95
VCC96
VCC97
VCC98
VCC99

CALISTOGA_FCBGA1466~D

VCC_SM0
VCC_SM1
VCC_SM2
VCC_SM3
VCC_SM4
VCC_SM5
VCC_SM6
VCC_SM7
VCC_SM8

VCC_SM9
VCC_SM10
VCC_SM11
VCC_SM12
VCC_SM13
VCC_SM14
VCC_SM15
VCC_SM16
VCC_SM17
VCC_SM18
VCC_SM19
VCC_SM20
VCC_SM21
VCC_SM22
VCC_SM23
VCC_SM24
VCC_SM25
VCC_SM26
VCC_SM27
VCC_SM28
VCC_SM29
VCC_SM30
VCC_SM31
VCC_SM32
VCC_SM33
VCC_SM34
VCC_SM35
VCC_SM36
VCC_SM37
VCC_SM38
VCC_SM39
VCC_SM40
VCC_SM41
VCC_SM42
VCC_SM43
VCC_SM44
VCC_SM45
VCC_SM46
VCC_SM47
VCC_SM48
VCC_SM49
VCC_SM50
VCC_SM51
VCC_SM52
VCC_SM53
VCC_SM54
VCC_SM55
VCC_SM56
VCC_SM57
VCC_SM58
VCC_SM59
VCC_SM60
VCC_SM61
VCC_SM62
VCC_SM63
VCC_SM64
VCC_SM65
VCC_SM66
VCC_SM67
VCC_SM68
VCC_SM69
VCC_SM70
VCC_SM71
VCC_SM72
VCC_SM73
VCC_SM74
VCC_SM75
VCC_SM76
VCC_SM77
VCC_SM78
VCC_SM79
VCC_SM80
VCC_SM81
VCC_SM82
VCC_SM83
VCC_SM84
VCC_SM85
VCC_SM86
VCC_SM87
VCC_SM88
VCC_SM89
VCC_SM90
VCC_SM91
VCC_SM92
VCC_SM93
VCC_SM94
VCC_SM95
VCC_SM96
VCC_SM97
VCC_SM98
VCC_SM99

AU41
AT41
AM41
AU40
BA34
AY34
AW34
AV34
AU34
AT34
AR34
BA30
AY30
AW30
AV30
AU30
AT30
AR30
AP30
AN30
AM30
AM29
AL29
AK29
AJ29
AH29
AJ28
AH28
AJ27
AH27
BA26
AY26
AW26
AV26
AU26
AT26
AR26
AJ26
AH26
AJ25
AH25
AJ24
AH24
BA23
AJ23
BA22
AY22
AW22
AV22
AU22
AT22
AR22
AP22
AK22
AJ22
AK21
AK20
BA19
AY19
AW19
AV19
AU19
AT19
AR19
AP19
AK19
AJ19
AJ18
AJ17
AH17
AJ16
AH16
BA15
AY15
AW15
AV15
AU15
AT15
AR15
AJ15
AJ14
AJ13
AH13
AK12
AJ12
AH12
AG12
AK11
BA8
AY8
AW8
AV8
AT8
AR8
AP8
BA6
AY6
AW6
AV6
AT6

+1.8V_SUS

VCCSM_LF4
VCCSM_LF5

C615

1

1

C612

2

2

0.47U_0402_16V4Z~D

0.47U_0402_16V4Z~D

Place near U40.AT41 & AM41

1

0.47U_0402_16V4Z~D

C441

2

0.1U_0402_16V4Z~D

1

2

C438

C616

Place near U40.BA23

1

C160

C617

C158

2

10U_0805_4VAM~D

0.47U_0402_16V4Z~D

10U_0805_4VAM~D

1

2

Place near U40.BA15

1

2

1

2

1

C444

2

0.1U_0402_16V4Z~D

1

+

C165

2

@

330U_D2E_2.5VM_R9~D

1

C452

2

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

Calistoga(5 of 6)

LA-2792

14 70Tuesday, Feb ru ar y 07, 2006

1

1.0

of

5

4

3

2

1

U40I

AC41

VSS0

AA41

VSS1

W41

VSS2

T41

VSS3

P41

D D

C C

B B

A A

VSS4

M41

VSS5

J41

VSS6

F41

VSS7

AV40

VSS8

AP40

VSS9

AN40

VSS10

AK40

VSS11

AJ40

VSS12

AH40

VSS13

AG40

VSS14

AF40

VSS15

AE40

VSS16

B40

VSS17

AY39

VSS18

AW39

VSS19

AV39

VSS20

AR39

VSS21

AN39

VSS22

AJ39

VSS23

AC39

VSS24

AB39

VSS25

AA39

VSS26

Y39

VSS27

W39

VSS28

V39

VSS29

T39

VSS30

R39

VSS31

P39

VSS32

N39

VSS33

M39

VSS34

L39

VSS35

J39

VSS36

H39

VSS37

G39

VSS38

F39

VSS39

D39

VSS40

AT38

VSS41

AM38

VSS42

AH38

VSS43

AG38

VSS44

AF38

VSS45

AE38

VSS46

C38

VSS47

AK37

VSS48

AH37

VSS49

AB37

VSS50

AA37

VSS51

Y37

VSS52

W37

VSS53

V37

VSS54

T37

VSS55

R37

VSS56

P37

VSS57

N37

VSS58

M37

VSS59

L37

VSS60

J37

VSS61

H37

VSS62

G37

VSS63

F37

VSS64

D37

VSS65

AY36

VSS66

AW36

VSS67

AN36

VSS68

AH36

VSS69

AG36

VSS70

AF36

VSS71

AE36

VSS72

AC36

VSS73

C36

VSS74

B36

VSS75

BA35

VSS76

AV35

VSS77

AR35

VSS78

AH35

VSS79

AB35

VSS80

AA35

VSS81

Y35

VSS82

W35

VSS83

V35

VSS84

T35

VSS85

R35

VSS86

P35

VSS87

N35

VSS88

M35

VSS89

L35

VSS90

J35

VSS91

H35

VSS92

G35

VSS93

F35

VSS94

D35

VSS95

AN34

VSS96

AK34

VSS97

AG34

VSS98

AF34

VSS99

CALISTOGA_FCBGA1466~D

P O W E R

VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS140
VSS141
VSS142
VSS143
VSS144
VSS145
VSS146
VSS147
VSS148
VSS149
VSS150
VSS151
VSS152
VSS153
VSS154
VSS155
VSS156
VSS157
VSS158
VSS159
VSS160
VSS161
VSS162
VSS163
VSS164
VSS165
VSS166
VSS167
VSS168
VSS169
VSS170
VSS171
VSS172
VSS173
VSS174
VSS175
VSS176
VSS177
VSS178
VSS179
VSS180
VSS181
VSS182
VSS183
VSS184
VSS185
VSS186
VSS187
VSS188
VSS189
VSS190
VSS191
VSS192
VSS193
VSS194
VSS195
VSS196
VSS197
VSS198
VSS199

AE34
AC34
C34
AW33
AV33
AR33
AE33
AB33
Y33
V33
T33
R33
M33
H33
G33
F33
D33
B33
AH32
AG32
AF32
AE32
AC32
AB32
G32
B32
AY31
AV31
AN31
AJ31
AG31
AB31
Y31
AB30
E30
AT29
AN29
AB29
T29
N29
K29
G29
E29
C29
B29
A29
BA28
AW28
AU28
AP28
AM28
AD28
AC28
W28
J28
E28
AP27
AM27
AK27
J27
G27
F27
C27
B27
AN26
M26
K26
F26
D26
AK25
P25
K25
H25
E25
D25
A25
BA24
AU24
AL24
AW23
AT23
AN23
AM23
AH23
AC23
W23
K23
J23
F23
C23
AA22
K22
G22
F22
E22
D22
A22
BA21
AV21
AR21

I

J

U40J

AN21

VSS200

AL21

VSS201

AB21

VSS202

Y21

VSS203

P21

VSS204

K21

VSS205

J21

VSS206

H21

VSS207

C21

VSS208

AW20

VSS209

AR20

VSS210

AM20

VSS211

AA20

VSS212

K20

VSS213

B20

VSS214

A20

VSS215

AN19

VSS216

AC19

VSS217

W19

VSS218

K19

VSS219

G19

VSS220

C19

VSS221

AH18

VSS222

P18

VSS223

H18

VSS224

D18

VSS225

A18

VSS226

AY17

VSS227

AR17

VSS228

AP17

VSS229

AM17

VSS230

AK17

VSS231

AV16

VSS232

AN16

VSS233

AL16

VSS234

J16

VSS235

F16

VSS236

C16

VSS237

AN15

VSS238

AM15

VSS239

AK15

VSS240

N15

VSS241

M15

VSS242

L15

VSS243

B15

VSS244

A15

VSS245

BA14

VSS246

AT14

VSS247

AK14

VSS248

AD14

VSS249

AA14

VSS250

U14

VSS251

K14

VSS252

H14

VSS253

E14

VSS254

AV13

VSS255

AR13

VSS256

AN13

VSS257

AM13

VSS258

AL13

VSS259

AG13

VSS260

P13

VSS261

F13

VSS262

D13

VSS265

B13

VSS264

AY12

VSS263

AC12

VSS266

K12

VSS267

H12

VSS268

E12

VSS269

AD11

VSS270

AA11

VSS271

Y11

VSS272

J11

VSS273

D11

VSS274

B11

VSS275

AV10

VSS276

AP10

VSS277

AL10

VSS278

AJ10

VSS279

CALISTOGA_FCBGA1466~D

P O W E R

VSS280
VSS281
VSS282
VSS283
VSS284
VSS285
VSS286
VSS287
VSS288
VSS289
VSS290
VSS292
VSS291
VSS293
VSS294
VSS295
VSS296
VSS297
VSS298
VSS299
VSS300
VSS301
VSS302
VSS303
VSS304
VSS305
VSS306
VSS307
VSS308
VSS309
VSS310
VSS311
VSS312
VSS313
VSS314
VSS315
VSS316
VSS317
VSS318
VSS319
VSS320
VSS321
VSS322
VSS323
VSS324
VSS325
VSS326
VSS327
VSS328
VSS329
VSS330
VSS331
VSS332
VSS333
VSS334
VSS335
VSS336
VSS337
VSS338
VSS339
VSS340
VSS341
VSS342
VSS343
VSS344
VSS345
VSS346
VSS347
VSS348
VSS349
VSS350
VSS351
VSS352
VSS353
VSS354
VSS355
VSS356
VSS357
VSS358
VSS359
VSS360

AG10
AC10
W10
U10
BA9
AW9
AR9
AH9
AB9
Y9
R9
G9
E9
A9
AG8
AD8
AA8
U8
K8
C8
BA7
AV7
AP7
AL7
AJ7
AH7
AF7
AC7
R7
G7
D7
AG6
AD6
AB6
Y6
U6
N6
K6
H6
B6
AV5
AF5
AD5
AY4
AR4
AP4
AL4
AJ4
Y4
U4
R4
J4
F4
C4
AY3
AW3
AV3
AL3
AH3
AG3
AF3
AD3
AC3
AA3
G3
AT2
AR2
AP2
AK2
AJ2
AD2
AB2
Y2
U2
T2
N2
J2
H2
F2
C2
AL1

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

Calistoga(6 of 6)

LA-2792

15 70Tuesday, Feb ru ar y 07, 2006

1

1.0

of

5

DDR_A_DQS#[0..7]11

DDR_A_D[0..63]11
DDR_A_DM[0..7]11
DDR_A_DQS[0..7]11

DDR_A_MA[0..13]11

D D

+1.8V_SUS

2.2U_0603_6.3V6K~D

2.2U_0603_6.3V6K~D

C213

C214

1

1

2

2

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D
C212

1

2

C C

+0.9V_DDR_VTT

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

1

2

B B

A A

C221

DDR_A_MA1
DDR_A_MA3

56_0404_4P2R_5%~D

DDR_A_BS0
DDR_A_MA10

56_0404_4P2R_5%~D

DDR_A_RAS#
DDR_CS0_DIMMA#

56_0404_4P2R_5%~D

DDR_A_CAS#
DDR_A_WE#

56_0404_4P2R_5%~D

M_ODT1
DDR_CS1_DIMMA#

56_0404_4P2R_5%~D

DDR_CKE0_DIMMA
DDR_A_BS2

56_0404_4P2R_5%~D

Layout Note:
Place one cap close to every 2 pullup
resistors terminated to +0.9V_DDR_VTT

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

1

1

1

2

2

2

C220

C218

C219

RN25

1 4
2 3

RN24

1 4
2 3

RN16

1 4
2 3

RN23

1 4
2 3

RN22

1 4
2 3

RN21

2 3
1 4

5

2.2U_0603_6.3V6K~D

1

2

C215

1

2

0.1U_0402_16V4Z~D

1

2

C217

+0.9V_DDR_VTT

C222

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

2.2U_0603_6.3V6K~D

1

2

C223

1

2

0.1U_0402_16V4Z~D

1

2

C216

RN27

RN19

RN26

RN18

RN17

RN15

RN20

C225

0.1U_0402_16V4Z~D

1

2

1

2

C231

14
23

56_0404_4P2R_5%~D

14
23

56_0404_4P2R_5%~D

14
23

56_0404_4P2R_5%~D

14
23

56_0404_4P2R_5%~D

14
23

56_0404_4P2R_5%~D

14
23

56_0404_4P2R_5%~D

14
23

56_0404_4P2R_5%~D

2.2U_0603_6.3V6K~D
C229

1

2

C227

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

1

2

C232

DDR_A_MA9
DDR_A_MA12

DDR_A_MA7
DDR_A_MA6

DDR_A_MA5
DDR_A_MA8

DDR_A_MA4
DDR_A_MA2

DDR_A_MA0
DDR_A_BS1

M_ODT0
DDR_A_MA13

DDR_CKE1_DIMMA
DDR_A_MA11

Layout Note:
Place near JDIM1

0.1U_0402_16V4Z~D

1

1

2

2

C233

C235

4

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

1

1

2

2

C237

C236

Layout Note:
Place these resistor
closely DIMM0,all
trace length<750 mil

Layout Note:
Place these resistor
closely DIMM0,all
trace length
Max=1.3"

4

3

+1.8V_SUS +1.8V_SUS

ON TOP SIDE

JDIM2

1

VREF

3

2.2U_0603_6.3V6K~D
C230

VSS

5

DQ0

7

DQ1

9

VSS

11

DQS0#

13

DQS0

15

VSS

17

DQ2

19

DQ3

21

VSS

23

DQ8

25

DQ9

27

VSS

29

DQS1#

31

DQS1

33

VSS

35

DQ10

37

DQ11

39

VSS

41

VSS

43

DQ16

45

DQ17

47

VSS

49

DQS2#

51

DQS2

53

VSS

55

DQ18

57

DQ19

59

VSS

61

DQ24

63

DQ25

65

VSS

67

DM3

69

NC

71

VSS

73

DQ26

75

DQ27

77

VSS

79

CKE0

81

VDD

83

NC

85

BA2

87

VDD

89

A12

91

A9

93

A8

95

VDD

97

A5

99

A3

101

A1

103

VDD

105

A10/AP

107

BA0

109

WE#

111

VDD

113

CAS#

115

NC/S1#

117

VDD

119

NC/ODT1

121

VSS

123

DQ32

125

DQ33

127

VSS

129

DQS4#

131

DQS4

133

VSS

135

DQ34

137

DQ35

139

VSS

141

DQ40

143

DQ41

145

VSS

147

DM5

149

VSS

151

DQ42

153

DQ43

155

VSS

157

DQ48

159

DQ49

161

VSS

163

NC,TEST

165

VSS

167

DQS6#

169

DQS6

171

VSS

173

DQ50

175

DQ51

177

VSS

179

DQ56

181

DQ57

183

VSS

185

DM7

187

VSS

189

DQ58

191

DQ59

193

VSS

195

SDA

197

SCL

199

VDDSPD

201

GND

TYCO_1470815-2~D

RESERVE

DDR_A_D0
DDR_A_D1

DDR_A_DQS#0
DDR_A_DQS0

DDR_A_D3
DDR_A_D2

DDR_A_D14
DDR_A_D8

DDR_A_DQS#1
DDR_A_DQS1

DDR_A_D11
DDR_A_D10

DDR_A_D20
DDR_A_D17

DDR_A_DQS#2
DDR_A_DQS2

DDR_A_D22
DDR_A_D23

DDR_A_D24
DDR_A_D29

DDR_A_DM3

DDR_A_D31 DDR_A_D26
DDR_A_D27

DDR_CKE0_DIMMA10

DDR_A_BS211

DDR_A_BS011
DDR_A_WE#11

DDR_A_CAS#11

DDR_CS1_DIMMA#10

M_ODT110

0.1U_0402_16V4Z~D

1

2

C234

CLK_SDATA6,17

CLK_SCLK6,17

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

DDR_CKE0_DIMMA

DDR_A_BS2
DDR_A_MA12

DDR_A_MA9 DDR_A_MA7
DDR_A_MA8

DDR_A_MA5
DDR_A_MA3
DDR_A_MA1

DDR_A_MA10
DDR_A_BS0
DDR_A_WE#

DDR_A_CAS#
DDR_CS1_DIMMA#

M_ODT1
DDR_A_D35

DDR_A_D32
DDR_A_DQS#4

DDR_A_DQS4
DDR_A_D34

DDR_A_D33
DDR_A_D43

DDR_A_D45
DDR_A_DM5

DDR_A_D47
DDR_A_D48

DDR_A_D52

DDR_A_DQS#6
DDR_A_DQS6

DDR_A_D55
DDR_A_D51

DDR_A_D60
DDR_A_D61

DDR_A_DM7
DDR_A_D58

DDR_A_D59
CLK_SDATA

CLK_SCLK

+3.3V_RUN

0.1U_0402_16V4Z~D
C228

1

1

2

2

DIMMA

2

VSS
DQ4
DQ5
VSS
DM0
VSS
DQ6
DQ7

VSS
DQ12
DQ13

VSS

DM1

VSS

CK0

CK0#

VSS
DQ14
DQ15

VSS

VSS
DQ20
DQ21

VSS

DM2

VSS
DQ22
DQ23

VSS
DQ28
DQ29

VSS

DQS3#

DQS3

VSS
DQ30
DQ31

VSS

NC/CKE1

VDD

NC/A15
NC/A14

VDD

A11

VDD

VDD

BA1

RAS#

S0#

VDD
ODT0

NC/A13

VDD

VSS
DQ36
DQ37

VSS

DM4

VSS
DQ38
DQ39

VSS
DQ44
DQ45

VSS

DQS5#

DQS5

VSS
DQ46
DQ47

VSS
DQ52
DQ53

VSS

CK1

CK1#

VSS

DM6

VSS
DQ54
DQ55

VSS
DQ60
DQ61

VSS

DQS7#

DQS7

VSS
DQ62
DQ63

VSS

SAO

SA1

GND

2

1

V_DDR_MCH_REF

2

DDR_A_D7

4

DDR_A_D4

6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

42
44
46
48
50

NC

52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92

A7

94

A6

96
98

A4

100

A2

102

A0

104
106
108
110
112
114
116
118
120

NC

122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200

202

DDR_A_DM0

DDR_A_D6
DDR_A_D5

DDR_A_D13
DDR_A_D12

DDR_A_DM1
M_CLK_DDR0

M_CLK_DDR#0
DDR_A_D15

DDR_A_D9

DDR_A_D16
DDR_A_D21

PM_EXTTS#0_R
DDR_A_DM2

DDR_A_D18
DDR_A_D19

DDR_A_D28
DDR_A_D25

DDR_A_DQS#3
DDR_A_DQS3

DDR_A_D30
DDR_CKE1_DIMMA

DDR_A_MA11
DDR_A_MA6
DDR_A_MA4

DDR_A_MA2
DDR_A_MA0

DDR_A_BS1
DDR_A_RAS#
DDR_CS0_DIMMA#

M_ODT0
DDR_A_MA13

DDR_A_D36
DDR_A_D37

DDR_A_DM4
DDR_A_D39

DDR_A_D38
DDR_A_D44

DDR_A_D40
DDR_A_DQS#5

DDR_A_DQS5
DDR_A_D41DDR_A_D46

DDR_A_D42
DDR_A_D49

DDR_A_D53
M_CLK_DDR1

M_CLK_DDR#1
DDR_A_DM6
DDR_A_D50

DDR_A_D54
DDR_A_D57

DDR_A_D56
DDR_A_DQS#7

DDR_A_DQS7
DDR_A_D62

DDR_A_D63

R175 100K_0402_5%~D

1 2

R176 100K_0402_5%~D

1 2

2.2U_0603_6.3V6K~D

1

C226

2

M_CLK_DDR0 10

M_CLK_DDR#0 10

1 2

R177
0_0402_5%~D

DDR_CKE1_DIMMA 10

DDR_A_BS1 11

DDR_A_RAS# 11
DDR_CS0_DIMMA# 10

M_ODT0 10

M_CLK_DDR1 10

M_CLK_DDR#1 10

0.1U_0402_16V4Z~D

1

2

C224

12

PM_EXTTS#0_R 17
PM_EXTTS#0 10

V_DDR_MCH_REF 10,17,48

R51
100K_0402_5%~D

DELL CONFIDENTIAL/PROPRIETARY

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.
DDRII-SODIMM SLOT1

LA-2792

16 70Tuesday, Feb ru ar y 07, 2006

1

1.0

of

5

DDR_B_DQS#[0..7]11

DDR_B_D[0..63]11
DDR_B_DM[0..7]11
DDR_B_DQS[0..7]11

DDR_B_MA[0..13]11

D D

C C

B B

A A

+1.8V_SUS

+0.9V_DDR_VTT

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

1

2

C248

DDR_B_MA1
DDR_B_MA3

56_0404_4P2R_5%~D

DDR_B_BS0
DDR_B_MA10

56_0404_4P2R_5%~D

DDR_B_MA0
DDR_B_BS1

56_0404_4P2R_5%~D

DDR_B_RAS#
DDR_CS2_DIMMB#

56_0404_4P2R_5%~D

DDR_B_CAS#
DDR_B_WE#

56_0404_4P2R_5%~D

DDR_CS3_DIMMB#
M_ODT3

56_0404_4P2R_5%~D

2.2U_0603_6.3V6K~D

2.2U_0603_6.3V6K~D

1

2

0.1U_0402_16V4Z~D

C239

RN13

RN7

RN12

RN6

RN5

RN2

RN14

C261

1

2

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

1

2

C244

2.2U_0603_6.3V6K~D
C242

1

2

0.1U_0402_16V4Z~D

C251

1

2

0.1U_0402_16V4Z~D

1

2

C243

DDR_B_MA9

14

DDR_B_MA12

23

56_0404_4P2R_5%~D

DDR_CKE3_DIMMB

14

DDR_B_MA11

23

56_0404_4P2R_5%~D

DDR_B_MA5

14

DDR_B_MA8

23

56_0404_4P2R_5%~D

DDR_B_MA7

14

DDR_B_MA6

23

56_0404_4P2R_5%~D

DDR_B_MA4

14

DDR_B_MA2

23

56_0404_4P2R_5%~D

M_ODT2

14

DDR_B_MA13

23

56_0404_4P2R_5%~D

DDR_B_BS2

14

DDR_CKE2_DIMMB

23

56_0404_4P2R_5%~D

2.2U_0603_6.3V6K~D

1

2

C247

1 4
2 3

1 4
2 3

1 4
2 3

1 4
2 3

1 4
2 3

2 3
1 4

C254

C249

1

1

2

2

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D
C240

1

2

Layout Note:
Place one cap close to every 2 pullup
resistors terminated to +0.9V_DDR_VTT

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

1

1

2

2

C245

C246

+0.9V_DDR_VTT

RN11

RN10

RN4

RN3

RN9

RN8

5

2.2U_0603_6.3V6K~D
C241

1

2

C255

1

2

0.1U_0402_16V4Z~D

1

1

2

2

C269

Layout Note:
Place near JDIM2

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

1

2

C268

C267

4

0.1U_0402_16V4Z~D

1

2

C266

Layout Note:
Place these resistor
closely DIMM0,all
trace length<750 mil

Layout Note:
Place these resistor
closely DIMM0,all
trace length
Max=1.3"

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

1

1

2

2

C265

C264

4

3

ON BOTTOM SIDE

DDR_B_D0
DDR_B_DQS#0

DDR_B_DQS0
DDR_B_D6

DDR_B_D7
DDR_B_D8

DDR_B_D9
DDR_B_DQS#1

DDR_B_DQS1
DDR_B_D14

DDR_B_D15

DDR_B_D16
DDR_B_D21

DDR_B_DQS#2
DDR_B_DQS2

DDR_B_D19
DDR_B_D18

DDR_B_D26
DDR_B_D28

DDR_B_DM3

DDR_B_D29
DDR_B_D27

+3.3V_RUN

DDR_CKE2_DIMMB

DDR_B_BS2
DDR_B_MA12

DDR_B_MA9
DDR_B_MA8

DDR_B_MA5
DDR_B_MA3
DDR_B_MA1

DDR_B_MA10
DDR_B_BS0
DDR_B_WE#

DDR_B_CAS#
DDR_CS3_DIMMB#

M_ODT3
DDR_B_D33

DDR_B_D32
DDR_B_DQS#4

DDR_B_DQS4

DDR_B_D34
DDR_B_D41

DDR_B_D40
DDR_B_DM5
DDR_B_D43

DDR_B_D46
DDR_B_D49

DDR_B_D48

DDR_B_DQS#6
DDR_B_DQS6

DDR_B_D55
DDR_B_D50

DDR_B_D56
DDR_B_DM7
DDR_B_D58

DDR_B_D59
CLK_SDATA

CLK_SCLK

0.1U_0402_16V4Z~D

C549

1

2

2.2U_0603_6.3V6K~D

1

2

DDR_CKE2_DIMMB10

DDR_B_BS211

DDR_B_BS011
DDR_B_WE#11

DDR_B_CAS#11

DDR_CS3_DIMMB#10

1

2

C263

M_ODT310

CLK_SDATA6,16

CLK_SCLK6,16

C548

JDIM1

1

VREF

3

VSS

5

DQ0

7

DQ1

9

VSS

11

DQS0#

13

DQS0

15

VSS

17

DQ2

19

DQ3

21

VSS

23

DQ8

25

DQ9

27

VSS

29

DQS1#

31

DQS1

33

VSS

35

DQ10

37

DQ11

39

VSS

41

VSS

43

DQ16

45

DQ17

47

VSS

49

DQS2#

51

DQS2

53

VSS

55

DQ18

57

DQ19

59

VSS

61

DQ24

63

DQ25

65

VSS

67

DM3

69

NC

71

VSS

73

DQ26

75

DQ27

77

VSS

79

CKE0

81

VDD

83

NC

85

BA2

87

VDD

89

A12

91

A9

93

A8

95

VDD

97

A5

99

A3

101

A1

103

VDD

105

A10/AP

107

BA0

109

WE#

111

VDD

113

CAS#

115

NC/S1#

117

VDD

119

NC/ODT1

121

VSS

123

DQ32

125

DQ33

127

VSS

129

DQS4#

131

DQS4

133

VSS

135

DQ34

137

DQ35

139

VSS

141

DQ40

143

DQ41

145

VSS

147

DM5

149

VSS

151

DQ42

153

DQ43

155

VSS

157

DQ48

159

DQ49

161

VSS

163

NC,TEST

165

VSS

167

DQS6#

169

DQS6

171

VSS

173

DQ50

175

DQ51

177

VSS

179

DQ56

181

DQ57

183

VSS

185

DM7

187

VSS

189

DQ58

191

DQ59

193

VSS

195

SDA

197

SCL

199

VDDSPD

201

GND

TYCO_1565917-4~D

DIMMB

STANDARD

VSS
DQ4
DQ5

VSS
DM0

VSS
DQ6
DQ7

VSS

DQ12
DQ13

VSS
DM1

VSS

CK0

CK0#

VSS

DQ14
DQ15

VSS

VSS

DQ20
DQ21

VSS
DM2

VSS

DQ22
DQ23

VSS

DQ28
DQ29

VSS

DQS3#

DQS3

VSS

DQ30
DQ31

VSS

NC/CKE1

VDD

NC/A15
NC/A14

VDD

VDD

VDD

BA1

RAS#

VDD

ODT0

NC/A13

VDD

VSS

DQ36
DQ37

VSS
DM4

VSS

DQ38
DQ39

VSS

DQ44
DQ45

VSS

DQS5#

DQS5

VSS

DQ46
DQ47

VSS

DQ52
DQ53

VSS

CK1

CK1#

VSS
DM6

VSS

DQ54
DQ55

VSS

DQ60
DQ61

VSS

DQS7#

DQS7

VSS

DQ62
DQ63

VSS
SAO

SA1
GND

NC

A11

A7
A6

A4
A2
A0

S0#

NC

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200

202

2

+1.8V_SUS+1.8V_SUS

DDR_B_D5
DDR_B_D4DDR_B_D1

DDR_B_DM0
DDR_B_D2

DDR_B_D3
DDR_B_D12

DDR_B_D13
DDR_B_DM1
M_CLK_DDR3

M_CLK_DDR#3
DDR_B_D10

DDR_B_D11

DDR_B_D17
DDR_B_D20

PM_EXTTS#0_R
DDR_B_DM2

DDR_B_D22
DDR_B_D23

DDR_B_D24
DDR_B_D25

DDR_B_DQS#3
DDR_B_DQS3

DDR_B_D30
DDR_B_D31

DDR_CKE3_DIMMB

DDR_B_MA11
DDR_B_MA7
DDR_B_MA6

DDR_B_MA4
DDR_B_MA2
DDR_B_MA0

DDR_B_BS1
DDR_B_RAS#
DDR_CS2_DIMMB#

M_ODT2
DDR_B_MA13

DDR_B_D36
DDR_B_D37

DDR_B_DM4
DDR_B_D38

DDR_B_D39DDR_B_D35
DDR_B_D44

DDR_B_D45
DDR_B_DQS#5

DDR_B_DQS5
DDR_B_D42

DDR_B_D47
DDR_B_D52

DDR_B_D53
M_CLK_DDR2

M_CLK_DDR#2
DDR_B_DM6
DDR_B_D54

DDR_B_D51
DDR_B_D60DDR_B_D61

DDR_B_D57
DDR_B_DQS#7

DDR_B_DQS7
DDR_B_D62

DDR_B_D63

100K_0402_5%~D

12

R173

V_DDR_MCH_REF

2.2U_0603_6.3V6K~D

1

C253

2

M_CLK_DDR3 10

M_CLK_DDR#3 10

PM_EXTTS#0_R 16

DDR_CKE3_DIMMB 10

DDR_B_BS1 11

DDR_B_RAS# 11
DDR_CS2_DIMMB# 10

M_ODT2 10

M_CLK_DDR2 10

M_CLK_DDR#2 10

+3.3V_RUN

12

R174

10K_0402_5%~D

1

1

C252

2

V_DDR_MCH_REF 10,16,48

0.1U_0402_16V4Z~D

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

DDRII-SODIMM SLOT2

LA-2792

17 70Tuesday, Feb ru ar y 07, 2006

1

1.0

of

5

4

3

2

1

FAN1 Control and Tachometer

+3.3V_RUN

12

VCP
VCP

DN1
DP1

LDO_SET

LDO_IN
LDO_IN

VDD_5V

R476

2.21K_0402_1%~D

R481

2.21K_0603_1%~D

17

3
40

41

31

36
37

30
4

22

24
25

27

26
28

5

1

C1777

0.1U_0402_16V4Z~D

2

VCP1
VCP2

REM_DIODE1_N
REM_DIODE1_P

LDO_SET

+3V_LDOIN

+5V_RUN

D D

2 1

C41

12

R249
332K_0402_1%~D

12

R262
118K_0402_1%~D

1

C210

C1779

2

@

22U_0805_6.3VAM~D

1

C341

2

1

2

1

C44

0.1U_0402_16V4Z~D

2

1 2

R41 8.2K_0402_5%~D

VGA_THERMDP53

VGA_THERMDN53

D35

RB751S40T1_SOD523-2~D

C C

DP2, DN2 routing together. Trace
width / Spacing = 10 / 10 mil

+3.3V_SUS

12

R241

8.2K_0402_5%~D

2

B

2

B

C

E

3 1

12

C

E

3 1

THERMATRIP1#

1

Q39

C42

0.1U_0402_16V4Z~D

2

MMST3904-7-F_SOT323~D

R239

8.2K_0402_5%~D

THERMATRIP2#

1

Q34

C43

0.1U_0402_16V4Z~D

2

MMST3904-7-F_SOT323~D

0.1U_0402_16V4Z~D

VGA_THERMDN, VGA_THERMDP routing together.
Trace width / Spacing = 10 / 10 mil

Place cap close to the
Guardian pins as possible.

+1.05V_VCCP

R40

1 2

2.2K_0402_5%~D

H_THERMTRIP#7

B B

+1.05V_VCCP

THERMTRIP_MCH#10

A A

R39

1 2

2.2K_0402_5%~D

5

+3.3V_SUS

@

Place C341 close to the Guardian
pins as possible

H_THERMDA7

2200P_0402_50V7K~D

H_THERMDC7

+3.3V_SUS

+3.3V_SUS

C303

R50

49.9_0603_1%~D

1 2

0.1U_0402_16V4Z~D

+RTC_CELL

THERMTRIP_VGA#52

1

2

4

R413
10K_0402_5%~D

1

C1778
100P_0402_50V8J~D

@

2

+FAN1_VOUT
FAN1_TACH

1

2

22U_0805_6.3VAM~D

+3.3V_SUS

+3VSUS_THRM

SUSPWROK23,42

ICH_PWRGD#42
POWER_SW#39,40

1

2

R61

1 2

C317

SNIFFER_GREEN#43
SNIFFER_YELLOW#43

1K_0402_5%~D

2200P_0402_50V7K~D

C1773

2200P_0402_50V7K~D

Place C1773 close to the
Guardian pins as possible

FAN1_TACH 39

JFAN1

1

1

2

2

3

3

MOLEX_53398-0371~D

VSET=

VSET =

R262

R249+R262

Tp-70

x 3.3V

21

U15

R136

1 2

1

2

SNIFFER_GREEN#
SNIFFER_YELLOW#

DAT_SMB39
CLK_SMB39

7.5K_0402_5%~D

1 2

R42 1K_0402_5%~D

1 2

R38 1K_0402_5%~D

THERMATRIP1#
THERMATRIP2#
THERMATRIP3#

VGA_THERMDP
VGA_THERMDN

+FAN1_VOUT

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

7

SMDATA

8

SMBCLK

23

LDO_SHDN#_ADDR

35

DP2

34

DN2

12

+3V_SUS

21

VSUS_PWRGD

18

+RTC_PWR3V

13

+3V_PWROK#

38

POWER_SW#

14

THERMTRIP1#

15

THERMTRIP2#

16

THERMTRIP3#

39

VSET

29

HW_LOCK#

9

VSS

1

DP3

2

DN3

6

FAN_OUT

33

FAN_DAC

10

GPIO1

11

GPIO2

19

GPIO3

20

GPIO4

32

GPIO5

EMC4000 C_QFN40~D

SMBUS ADDRESS : 2F

ATF_INT#

PAD_GND

LDO_POK

THERMTRIP_SIO

ACAV_CLR

SYS_SHDN#

LDO_OUT
LDO_OUT

1

C1776

2

10U_0805_10V4Z~D

Place near t h e bottom SODIMM

+5V_SUS +5V_SUS

12

VCP1

1

C66
2200P_0402_50V7K~D

2

R477

1 2

10K_0603_1%_TSM1A103F34D3RZ~D

13

D

S

G

2N7002W-7-F_SOT323~D

R477 place near the bottom SODIMM

Place near the bottom SODIMM

12

VCP2

1

C36
2200P_0402_25V7K~D

2

R479 place on bottom side
next to SoDIMM connector

Place C47 clos e to the Guardian
pins as possible

+3.3V_ALW

1

1

C1774

2

2

10U_0805_10V4Z~D

1

C571

2

1U_0603_10V4Z~D

2

R479

1 2

10K_0603_1%_TSM1A103F34D3RZ~D

2N7002W-7-F_SOT323~D

12

R60

10K_0402_5%~D

C150

0.1U_0402_16V4Z~D

@

0.27_1210_5%~D

1

C152

0.1U_0402_16V4Z~D

2

@

Q21

ATF_INT# 39

REM_DIODE1_N , R E M _D I O D E1_P routing together.
Trace width / S p a cing = 10 / 10 mil

2.5V_RUN_PWRGD 42

1

C47

2

2200P_0402_50V7K~D

THERMTRIP_SIO 38

ACAV_IN 39,50,51

+2.5V_RUN

R1643

12

DELL CONFIDENTIAL/PROPRIETARY

Title

Size Document Number Rev

Date: Sheet

13

D

2

G

S

Place under CPU

+3.3V_RUN

Compal Electronics, Inc.

FAN & Thermal Sensor

2

Q15

+5V_SUS+5V_SUS

E

31

B

2

C

@

LA-2792

12

R478
10K_0402_5%~D

12

R480
10K_0402_5%~D

5V_CAL_SIO2# 38

1

Q12

2

MMST3904-7-F_SOT323~D

R1634

10K_0402_5%~D

12

@

31.6K_0402_1%~D

LDO_SET

1

5V_CAL_SIO# 38

C1803

@

2200P_0402_50V7K~D

+RTC_CELL

THERM_STP# 46

+2.5V_RUN

12

R1800

12

R1789

1K_0402_5%~D

18 70Tuesday, Feb ru ar y 07, 2006

1.0

of

5

D D

JLVDS

45

MGND1

46

MGND2

47

MGND3

48

MGND4

49

MGND5

50

MGND6

51

MGND7

52

MGND8

53

MGND9

54

MGND10

55

MGND11

56

NC

57

C C

B B

TXLCLKOUT-

NC

TXLCLKOUT+

PANEL_I2C_CLK
PANEL_I2C_DAT

PNL_SLFTST
LCDPWR_SRC
LCDPWR_SRC
LCDPWR_SRC

PBAT_SMBCLK
PBAT_SMBDAT

LAMP_START

IPEX_20330-044E-11F~D

TXUCLKUT-

TXUCLKUT+

GND1

TXUOUT2-

TXUOUT2+

GND2

TXUOUT1-

TXUOUT1+

GND3

TXUOUT0-

TXUOUT0+

GND4

GND5
TXLOUT2­TXLOUT2+

GND6
TXLOUT1-

TXLOUT1+

GND7
TXLOUT0­TXLOUT0+

GND8

GND9

VEDID

GND10
LCDVDD1
LCDVDD2

GND11

FPBACK

GND12

GND13

+5V_ALWF

GND14

44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

LCD_BCLK­LCD_BCLK+

LCD_B2­LCD_B2+

LCD_B1­LCD_B1+

LCD_B0­LCD_B0+

LCD_ACLK­LCD_ACLK+

LCD_A2­LCD_A2+

LCD_A1­LCD_A1+

LCD_A0­LCD_A0+

LCD_DDCCLK
LCD_DDCDATA

LCD_TST

LAMP_D_STAT#

1

2

LCD_TST 23

C296

0.1U_0603_50V4Z~D

4

LCD_BCLK- 53
LCD_BCLK+ 53

LCD_B2- 53
LCD_B2+ 53

LCD_B1- 53
LCD_B1+ 53

LCD_B0- 53
LCD_B0+ 53

LCD_ACLK- 53
LCD_ACLK+ 53

LCD_A2- 53
LCD_A2+ 53

LCD_A1- 53
LCD_A1+ 53

LCD_A0- 53
LCD_A0+ 53

LCD_DDCCLK 52
LCD_DDCDATA 52

0.1U_0402_16V4Z~D

SBAT_SMBCLK 39,45
SBAT_SMBDAT 39,45

D2

RB751S40T1_SOD523-2~D

@

+INV_PWR_SRC

FPBACK_EN38

PANEL_BKEN52

+3.3V_RUN

C26

0.1U_0402_16V4Z~D

BACKLITEON

1 2

1

2

LAMP_STAT#

R1760
100K_0402_5%~D

+LCDVDD

C27

1

1

2

2

R520 0_0402_5%~D

21

M'07 inverter support - Depop D2.
D'05 inverter support - Populate D2

1 2

R1767 0_0402_5%~D

12

+3.3V_RUN

12

+5V_ALW

C28

0.1U_0402_16V4Z~D

LAMP_STAT# 23

FPBACK_EN
PANEL_BKEN

1
2

X01 support M07 inverter

R92
10K_0402_5%~D

BIA_PWM 39,52

+3.3V_RUN

5

U7

P

IN1

4

O

IN2

G

74AHC1G08GW_SOT353-5~D

3

@

3

+LCDVDD

ENVDD52

BACKLITEON for D'05;
BIA_PWM for M'07

BACKLITEON

12

R35
470_0402_5%~D

13

D

Q37

2

G

2N7002W-7-F_SOT323~D

S

2

1

2

+15V_SUS

I

40mil

C290

1000P_0402_50V7K~D

2

12

R54
100K_0402_5%~D

2

G

1

O

Q8

G

DDTC124EUA-7-F_SOT323~D

3

+PWR_SRC

12

R235
100K_0402_5%~D

1 2

100K_0402_5%~D

+15V_SUS

12

13

D

S

R236

RUN_ON37,39,41,42,46,47,48,58

+LCDVDD

R272
100K_0402_5%~D

1

Q10

2

2N7002W-7-F_SOT323~D

Q32

FDS4435_NL_SO8~D

8
7

1

6

2

5

3

4

D

S

1 3

G

2

Q9

SI3456BDV-T1-E3_TSOP6~D

D

S

4 5

G

3

12

R79

@

100K_0402_5%~D

C315

0.1U_0603_50V4Z~D

+INV_PWR_SRC

40mil

1

C289

0.1U_0603_50V4Z~D

2

Q29
2N7002W-7-F_SOT323~D

FDS4435: P CHANNAL

1

6
2

1

+3.3V_RUN

1

C29

2

0.1U_0402_16V4Z~D

M'07 inverter support - Populate R520,R1767 Depop U7.
D'05 inverter support - Populate U7, Depop R520,R1767

A A

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

Internal LVDS

LA-2792

19 70Tuesday, Feb ru ar y 07, 2006

1

1.0

of

5

D D

4

3

2

1

D29
DA204U_SOT323~D

1

@

+3.3V_RUN

2

3

L78

VGA_RED36,52

VGA_GRN36,52

C C

VGA_BLU36,52

VGA_RED

VGA_GRN

VGA_BLU

12

75_0402_1%

R1396

12

75_0402_1%

R1397

12

75_0402_1%

R1398

22P_0402_50V8J~D

1

2

C1408

@

1

2

C1406

@

22P_0402_50V8J~D

1

2

C1407

@

Evaluate Package

DAT_DDC236,52

CLK_DDC236,52

+5V_RUN

B B

VGA_HSYNC52

VGA_VSYNC52

D2005 SDM10U45-7_SOD523-2~D

2 1

R1404

1 2

39_0402_5%~D

R1405

1 2

39_0402_5%~D

SN74AHCT1G125GW_SC70-5~D

R1403

1K_0402_5%~D

1 2

1

5

U190

P

4

OE#

A2Y

G

3

5

P

A2Y

G

3

R101
0_0402_5%~D

1

4

OE#

R114

0_0402_5%~D

U191

SN74AHCT1G125GW_SC70-5~D

1 2

1 2

BLM18BB600SN1D_0603~D

1 2

BLM18BB600SN1D_0603~D

1 2

BLM18BB600SN1D_0603~D

1 2

22P_0402_50V8J~D

L81

BLM18AG121SN1D_0603~D

1 2

HSYNC_R 36

VSYNC_R 36

L82

BLM18AG121SN1D_0603~D

1 2

CRT_VCC

R1399

1K_0402_5%~D

C1414

L79

L80

@

22P_0402_50V8J~D

1

C1409
10P_0402_50V8J~D

2

@

12

1

2

12

@

R1400

1K_0402_5%~D

1

2

C1415

22P_0402_50V8J~D

R1401

1 2

R1402

2.2K_0402_5%~D

1 2

2.2K_0402_5%~D

0.1U_0402_16V4Z~D

2

1

C1410
10P_0402_50V8J~D

2

@

T46 PAD~D

D30
DA204U_SOT323~D

1

@

3

1

C1413

2

1

2

D31
DA204U_SOT323~D

1

@

2

3

C1411
10P_0402_50V8J~D

@

D32

SDM10U45-7_SOD523-2~D

+5V_RUN

21

C1412

0.01U_0402_16V7K~D

RED
DAT_DDC2

GREEN
JVGA_HS

BLUE
CRT_VCC
JVGA_VS

M_ID2#

CLK_DDC2

1

2

CRT_VCC

JCRT

6

11

1
7

12

2
8

16

13

17
3
9

14

4

10
15

5

SUYIN_070915FR015S201CU~D

A A

DA204U

K1

A2

DELL CONFIDENTIAL/PROPRIETARY

A1 K2

5

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

4

3

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

CRT

LA-2792

20 70Tuesday, Feb ru ar y 07, 2006

1

1.0

of

5

PCI_AD[0..31]30,35

D D

C C

B B

+3.3V_RUN

1 2

R254 8.2K_0402_5%~D

1 2

R46 8.2K_0402_5%~D

1 2

R47 8.2K_0402_5%~D

1 2

R258 8.2K_0402_5%~D

1 2

R327 8.2K_0402_5%~D

1 2

R69 8.2K_0402_5%~D

1 2

R257 8.2K_0402_5%~D

1 2

R255 8.2K_0402_5%~D

+3.3V_RUN

1 2

R43 8.2K_0402_5%~D

1 2

R45 8.2K_0402_5%~D

1 2

R44 8.2K_0402_5%~D

1 2

R286 8.2K_0402_5%~D

1 2

R350 8.2K_0402_5%~D

1 2

R324 8.2K_0402_5%~D

1 2

R309 8.2K_0402_5%~D

1 2

R315 8.2K_0402_5%~D

1 2

R317 8.2K_0402_5%~D

1 2

R72 8.2K_0402_5%~D

1 2

R340 8.2K_0402_5%~D

1 2

R77 8.2K_0402_5%~D

1 2

R256 8.2K_0402_5%~D

1 2

R339 8.2K_0402_5%~D

PCI_DEVSEL#
PCI_STOP#
PCI_TRDY#
PCI_FRAME#

PCI_PLOCK#
PCI_IRDY#
PCI_SERR#
PCI_PERR#

PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#

ICH_GPIO2_PIRQE#
ICH_GPIO3_PIRQF#
ICH_GPIO4_PIRQG#
ICH_GPIO5_PIRQH#

PCI_REQ0#
PCI_REQ1#
PCI_REQ2#
PCI_REQ3#
PCI_REQ4#
PCI_REQ5#

4

PCI_AD0
PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD6
PCI_AD7
PCI_AD8
PCI_AD9
PCI_AD10
PCI_AD11
PCI_AD12
PCI_AD13
PCI_AD14
PCI_AD15
PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20
PCI_AD21
PCI_AD22
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30
PCI_AD31

PCI_PIRQA#35
PCI_PIRQC#30

PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#

U45B

E18

AD0

C18

AD1

A16

AD2

F18

AD3

E16

AD4

A18

AD5

E17

AD6

A17

AD7

A15

AD8

C14

AD9

E14

AD10

D14

AD11

B12

AD12

C13

AD13

G15

AD14

G13

AD15

E12

AD16

C11

AD17

D11

AD18

A11

AD19

A10

AD20

F11

AD21

F10

AD22

E9

AD23

D9

AD24

B9

AD25

A8

AD26

A6

AD27

C7

AD28

B6

AD29

E6

AD30

D6

AD31

Interrupt I/F

A3

PIRQA#

B4

PIRQB#

C5

PIRQC#

B5

PIRQD#

AE5

RSVD[1]

AD5

RSVD[2]

AG4

RSVD[3]

AH4

RSVD[4]

AD9

RSVD[5]

PCI

REQ4# / GPIO22
GNT4# / GPIO48

GPIO1 / REQ5#

GPIO17 / GNT5#

GPIO2 / PIRQE#
GPIO3 / PIRQF#

GPIO4 / PIRQG#

GPIO5 / PIRQH#

MISC

MCH_SYNC#

ICH7M A0_BGA 6 52~D

REQ0#
GNT0#
REQ1#
GNT1#
REQ2#
GNT2#
REQ3#
GNT3#

C/BE0#
C/BE1#
C/BE2#
C/BE3#

IRDY#

PAR
PCIRST#
DEVSEL#

PERR#

PLOCK#

SERR#
STOP#
TRDY#

FRAME#

PLTRST#

PCICLK

PME#

RSVD[6]
RSVD[7]
RSVD[8]
RSVD[9]

D7
E7
C16
D16
C17
D17
E13
F13
A13
A14
C8
D8

B15
C12
D12
C15

A7
E10
B18
A12
C9
E11
B10
F15
F14
F16

C26
A9
B19

G8
F7
F8
G7

AE9
AG8
AH8
F21
AH20

3

PCI_REQ0#
PCI_GNT0#
PCI_REQ1#
PCI_GNT1#
PCI_REQ2#

PCI_REQ3#
PCI_REQ4#

PCI_GNT4#
PCI_REQ5#
PCI_GNT5#

PCI_C_BE0#
PCI_C_BE1#
PCI_C_BE2#
PCI_C_BE3#

PCI_IRDY#
PCI_PAR
PCI_PCIRST#
PCI_DEVSEL#
PCI_PERR#
PCI_PLOCK#
PCI_SERR#
PCI_STOP#
PCI_TRDY#

PCI_FRAME#

PCI_PLTRST#
CLK_PCI_ICH
ICH_PME#

ICH_GPIO2_PIRQE#
ICH_GPIO3_PIRQF#
ICH_GPIO4_PIRQG#
ICH_GPIO5_PIRQH#

MCH_ICH_SYNC# 10

PCI_REQ0# 36
PCI_GNT0# 35,36
PCI_REQ1# 30
PCI_GNT1# 30

PCI_C_BE0# 30,35
PCI_C_BE1# 30,35
PCI_C_BE2# 30,35
PCI_C_BE3# 30,35

PCI_ I RDY# 30,35,36
PCI_PAR 30,35

PCI_DEVSEL# 30,35
PCI_PERR# 30,35
PCI_PLOCK# 35

PCI_SERR# 35

PCI_STOP# 30,35

PCI_TRDY# 30,35

PCI_FRAME# 30,35,36

CLK_PCI_ICH 6

ICH_PME# 38

PCI_PCIRST#

PCI_PLTRST#

2

+3.3V_SUS

14

U21A

1

P

IN1

3

OUT

2

IN2

G

74VHC08MTCX_NL_TSSOP14~D

7

+3.3V_SUS

14

U21C

10

P

9

13
12

4
5

IN1

OUT

IN2

G

7

+3.3V_SUS

14

P

IN1

OUT

IN2

G

7

+3.3V_SUS

14

P

IN1

OUT

IN2

G

7

PCI_RST#

8

74VHC08MTCX_NL_TSSOP14~D

U21D

PLTRST#

11

74VHC08MTCX_NL_TSSOP14~D

U21B

PLTRST2#

6

74VHC08MTCX_NL_TSSOP14~D

PCI_RST# 30,31,35

PLTRST# 10,23,28,34

PLTRST2# 38,39

1

Place closely pin U45.A9

CLK_PCI_ICH

R332

@

10_0402_5%~D

C349

@

8.2P_0402_50V8J~D

1 2
1

2

LPC

12

(11)

PCI_GNT5#PCI_GNT4#

R347
1K_0402_5%~D@

GNT5#
R328

unstuffunstuff

12

R328
1K_0402_5%~D

GNT4#
R347

PCI

(10)

SPI

(01)

A A

unstuff stuff

stuff

unstuff

*

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.
ICH7(1/4)

LA-2792

21 70Tuesday, Feb ru ar y 07, 2006

1

1.0

of

5

C38

2.2P_0402_50V8C

12

Package

D D

C C

PSATA_ITX_DRX_N025
PSATA_ITX_DRX_P025

+3.3V_RUN

B B

9.6X4.06 mm

+RTC_CELL

Place near ICH7 side.

R414

IDE_IRQ

12

8.2K_0402_5%~D

C40

2.2P_0402_50V8C

12

CMOS

@SHORT PADS~D

1

1U_0603_10V4Z~D

MDC_AC_BITCLK33
ICH_SYNC_MDC33

ICH_RST_MDC#33

ICH_AC_SDIN026
ICH_AC_SDIN133

ICH_SDOUT_MDC33

12

C270 3900P_0402_50V7K~D

12

C271

3900P_0402_50V7K~D

32.768KHZ_6PF_1TJS060BJ4A376P~D
X1

1 4

2 3

ICH_RTCX2

1 2

R297 20K_0402_5%~D

1 2

R301 332K_0402_1%~D

1 2

R276 1M_0402_5%~D

1

C348

1 2

SATA_ACT#43

2

2

C499 27P_0402_50V8J~D@

PSATA_IRX_DTX_N0_C25
PSATA_IRX_DTX_P0_C25

0_0402_5%~D

12

CLK_PCIE_SATA#6
CLK_PCIE_SATA6

IDE_DIORDY25
IDE_IRQ25
IDE_DDACK#25

IDE_DIOW#25

IDE_DIOR#25

R12

1 2

1 2
1 2

1 2

R371

1 2

33_0402_5%~D

R380 24.9_0402_1%~D

1 2

Within 500 mils

4

ICH_RTCX1

R36

ICH_RTCRST#
ICH_INTVRMEN
SM_INTRUDER#

R55333_0402_5%~D
R8133_0402_5%~D

R8333_0402_5%~D

ICH_AC_SDOUT_R

SATA_ACT#

PSATA_IRX_DTX_N0_C
PSATA_IRX_DTX_P0_C
PSATA_ITX_DRX_N0_C
PSATA_ITX_DRX_P0_C

CLK_PCIE_SATA#
CLK_PCIE_SATA

IDE_DIORDY
IDE_IRQ
IDE_DDACK#
IDE_DIOW#
IDE_DIOR#

12

10M_0402_5%~D

ICH_AC_BITCLK_R

ICH_AC_SYNC_R
ICH_AC_RST_R#

ICH_AC_SDIN0
ICH_AC_SDIN1

AF18

AG2
AH2

AG6
AH6

AH10
AG10

AG16
AH16
AF16
AH15
AF15

AB1
AB2

AA3

W4

Y5

W1

Y1
Y2

W3

V3
U3
U5

V4

T5
U7

V6

V7

U1
R6

R5

T2

T3

T1

T4

AF3
AE3

AF7
AE7

AF1
AE1

U45A

RTCX1
RTCX2

RTCRST#
INTVRMEN

INTRUDER#

EE_CS
EE_SHCLK
EE_DOUT
EE_DIN

LAN_CLK
LAN_RSTSYNC
LAN_RXD0

LAN_RXD1
LAN_RXD2

LAN_TXD0
LAN_TXD1
LAN_TXD2

ACZ_BCLK
ACZ_SYNC

ACZ_RST#
ACZ_SDIN0

ACZ_SDIN1
ACZ_SDIN2

ACZ_SDOUT

SATALED#

SATA0RXN
SATA0RXP
SATA0TXN
SATA0TXP

SATA2RXN
SATA2RXP
SATA2TXN
SATA2TXP

SATA_CLKN
SATA_CLKP

SATARBIASN
SATARBIASP

IORDY
IDEIRQ
DDACK#
DIOW#
DIOR#

RTC

GPIO49 / CPUPWRGD

ICH7M A0_BGA 6 52~D

LPCCPU

LDRQ1# / GPIO23

LFRAME#

LAN

A20GATE

CPUSLP#

TP1 / DPRSTP#

TP2 / DPSLP#

INIT3_3V#

STPCLK#

THERMTRIP#

SATA

IDE

LAD0
LAD1
LAD2
LAD3

LDRQ0#

A20M#

FERR#

IGNNE#

INIT#
INTR

AC-97/AZALIA

RCIN#

SMI#

DCS1#
DCS3#

DD10
DD11
DD12
DD13
DD14
DD15

DDREQ

NMI

DA0
DA1
DA2

DD0
DD1
DD2
DD3
DD4
DD5
DD6
DD7
DD8
DD9

AA6
AB5
AC4
Y6

AC3
AA5

AB3

AE22
AH28

AG27
AF24

AH25
AG26
AG24
AG22

AG21
AF22
AF25

AG23
AF23

AH24
AH22
AF26

AH17
AE17
AF17

AE16
AD16

AB15
AE14
AG13
AF13
AD14
AC13
AD12
AC12
AE12
AF12
AB13
AC14
AF14
AH13
AH14
AC15

AE15

3

LPC_LAD0
LPC_LAD1
LPC_LAD2
LPC_LAD3

LPC_LDRQ0#
LPC_LDRQ1#

LPC_LFRAME#

H_CPUSLP_R#

DPRSLP#

H_FERR#

THRMTRIP_ICH#

IDE_DA0
IDE_DA1
IDE_DA2

IDE_DCS1#
IDE_DCS3#

IDE_DD0
IDE_DD1
IDE_DD2
IDE_DD3
IDE_DD4
IDE_DD5
IDE_DD6
IDE_DD7
IDE_DD8
IDE_DD9
IDE_DD10
IDE_DD11
IDE_DD12
IDE_DD13
IDE_DD14
IDE_DD15

IDE_DDREQ

LPC_LAD[0..3] 28,38,39

LPC_LDRQ0# 38
LPC_LDRQ1# 38

LPC_LFRAME# 28,38,39

R438 0_0402_5%~D@
R121 0_0402_5%~D

IDE_DA[0..2] 25

IDE_DCS1# 25
IDE_DCS3# 25

IDE_DD[0..15]

IDE_DDREQ 25

12
12

1

0.1U_0402_16V4Z~D

2

IDE_DD[0..15] 25

SIO_A20GATE
H_A20M#
H_CPUSLP#

H_DPRSTP#
H_DPSLP#

H_PWRGOOD
H_IGNNE#
H_INIT#

H_INTR

SIO_RCIN#
H_SMI#

H_NMI
H_STPCLK#

1 2

C69

@

2

R115

56_0402_5%~D

SIO_A20GATE 39
H_A20M# 7
H_CPUSLP# 7,10

H_DPRSTP# 7,49
H_DPSLP# 7
H_FERR# 7
H_PWRGOOD 7
H_IGNNE# 7
H_INIT# 7

H_INTR 7

SIO_RCIN# 39
H_SMI# 7

H_NMI 7
H_STPCLK# 7

+1.05V_VCCP

1

H_DPRSTP# daisy

ICH7-M --> Yonah --> IMVP6

+1.05V_VCCP

12

+3.3V_RUN

12

12

H_FERR#

SIO_RCIN#

SIO_A20GATE

R118

56_0402_5%~D

R277

10K_0402_5%~D

R1631

10K_0402_5%~D

Close to U45

R378
33_0402_5%~D

ICH_AC_SDOUT_R

ICH_SDOUT_AUDIO26

ICH_SYNC_AUDIO26

ICH_RST_AUDIO#26

A A

ICH_AC_BITCLK26

5

1 2

R82
33_0402_5%~D

1 2

R84
33_0402_5%~D

1 2

R189
33_0402_5%~D

1 2

1

C503
27P_0402_50V8J~D

2

@

ICH_AC_SYNC_R

ICH_AC_RST_R#

ICH_AC_BITCLK_R

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

4

3

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.
ICH7(2/4)

LA-2792

22 70Tuesday, Feb ru ar y 07, 2006

1

1.0

of

5

+3.3V_RUN

1 2

R428 8.2K_0402_5%~D@

1 2

R432 10K_0402_5%~D

1 2

R111 8.2K_0402_5%~D

D D

+3.3V_SUS

C C

1 2

R1755 10K_0402_5%~D

1 2

R1756 10K_0402_5%~D

1 2

R75 10K_0402_5%~D

1 2

R1633 10K_0402_5%~D

1 2

R1632 10K_0402_5%~D

1 2

R373 10K_0402_5%~D

1 2

R372 10K_0402_5%~D

1 2

R269 8.2K_0402_5%~D

1 2

R318 680_0402_5%~D

1 2

SIO_THRM#

IRQ_SERIRQ

CLKRUN#

BT_RADIO_DIS#

WWAN_RADIO_DIS#

LAMP_STAT#

SIO_EXT_SCI#

SIO_EXT_SMI#

LINKALERT#

SMBALERT#

ICH_BATLOW#

ICH_PCIE_W AKE#

(PCI Express Wake Event)

R554
100K_0402_5%~D

DPRSLPVR

MiniWLAN (Mini Card 2)--->

MiniWWAN (Mini Card 1) --->

GIGA LAN --->

B B

A A

+3.3V_SUS

R341

1 2

10K_0402_5%~D

R363

1 2

10K_0402_5%~D

ICH_SMLINK1 ICH_SMLINK1

PCIE_IRX_WANTX_N134
PCIE_IRX_WANTX_P134
PCIE_ITX_WANRX_N1_C34

PCIE_ITX_WANRX_P1_C34
PCIE_IRX_WLANTX_N234
PCIE_IRX_WLANTX_P234
PCIE_ITX_WLANRX_N2_C34

PCIE_ITX_WLANRX_P2_C34

PCIE_IRX_LOMTX_N328
PCIE_IRX_LOMTX_P328

PCIE_ITX_LOMRX_N3_C28
PCIE_ITX_LOMRX_P3_C28

ICH_EC_SPI_CLK39
SPI_CS#39

ICHO_ECI_SPI_DATA39

ICHI_ECO_SPI_DATA39

4

ICH_SMBCLK6,28,34

ICH_SMBDATA6,28,34

+3.3V_SUS

+3.3V_SUS

12

R351

2.2K_0402_5%~D

R303

1 2

8.2K_0402_5%~D

SPKR26
ITP_DBRESET#7,39

PM_BMBUSY#10

H_STP_PCI#6
H_STP_CPU#6

LCD_TST19

IDE_RST_MOD25

CLKRUN#30,38,39

BT_RADIO_DIS#40

ICH_PCIE_W AKE#38

IRQ_SERIRQ28,30,38,39

SIO_THRM#39

IMVP_PWRGD42,49

SIO_EXT_WAKE#39

LAMP_STAT#19
SIO_EXT_SMI#39

close to ICH7-M

C1 0.1U_0402_16V4Z~D

1 2

C2 0.1U_0402_16V4Z~D

1 2

C602 0.1U_0402_16V4Z~D

1 2

C603 0.1U_0402_16V4Z~D

1 2

C281 0.1U_0402_16V4Z~D

1 2

C282 0.1U_0402_16V4Z~D

1 2

ICH_EC_SPI_CLK
SPI_CS#

ICHO_ECI_ SPI_ DATA
ICHI_ECO_ SPI_ DATA

12

R352

2.2K_0402_5%~D

R384

1 2

10K_0402_5%~D

1 2

ICH_SMBCLK
ICH_SMBDATA
LINKALERT#
ICH_SMLINK0ICH_SMLINK0

ICH_RI#
SPKR
ITP_DBRESET#
PM_BMBUSY#
SMBALERT#
H_STP_PCI#

H_STP_CPU#
LCD_TST

IDE_RST_MOD
CLKRUN#
BT_RADIO_DIS#

ICH_PCIE_W AKE#
IRQ_SERIRQ
SIO_THRM#

IMVP_PWRGD

12

C82 0.1U_0402_16V4Z~D

SIO_EXT_WAKE#
LAMP_STAT#
SIO_EXT_SMI#

PCIE_IRX_WANTX_N1
PCIE_IRX_WANTX_P1
PCIE_ITX_WANRX_N1
PCIE_ITX_WANRX_P1

PCIE_IRX_WLANTX_N2
PCIE_IRX_WLANTX_P2
PCIE_ITX_WLANRX_N2
PCIE_ITX_WLANRX_P2

PCIE_IRX_LOMTX_N3
PCIE_IRX_LOMTX_P3
PCIE_ITX_LOMRX_N3
PCIE_ITX_LOMRX_P3

+3.3V_SUS+3.3V_SUS +3.3V_SUS

R389

R388

1 2

47_0402_5%~D

10K_0402_5%~D

10K_0402_5%~D

USB_OC0#
USB_OC1#
USB_OC2#
USB_OC3#
USB_OC4#
USB_OC5#
USB_OC6#
USB_OC7#

1 2

47_0402_5%~D

1 2

U45C

C22

SMBCLK

B22

SMBDATA

A26

LINKALERT#

B25

SMLINK0

A25

SMLINK1

A28

RI#

A19

SPKR

A27

SUS_STAT#

A22

SYS_RST#

AB18

GPIO0 / BM_BUSY#

B23

GPIO11 / SMBALERT#

AC20

GPIO18 / STPPCI#

AF21

GPIO20 / STPCPU#

A21

GPIO26

B21

GPIO27

E23

GPIO28

AG18

GPIO32 / CLKRUN#

AC19

GPIO33 / AZ_DOCK_EN#

U2

GPIO34 / AZ_DOCK_RST#

F20

WAKE#

AH21

SERIRQ

AF20

THRM#

AD22

VRMPWRGD

AC21

GPIO6

AC18

GPIO7

E21

GPIO8

R1786

R1787

3

F26
F25
E28
E27

H26
H25
G28
G27

K26
K25

J28
J27

M26
M25

L28
L27

P26
P25
N28
N27

T25
T24
R28
R27

R2

P6
P1

P5
P2

D3
C4
D5
D4

E5

C3

A2
B3

U45D

PERn1
PERp1
PETn1
PETp1

PERn2
PERp2
PETn2
PETp2

PERn3
PERp3
PETn3
PETp3

PERn4
PERp4
PETn4
PETp4

PERn5
PERp5
PETn5
PETp5

PERn6
PERp6
PETn6
PETp6

SPI_CLK
SPI_CS#
SPI_ARB

SPI_MOSI
SPI_MISO

OC0#
OC1#
OC2#
OC3#
OC4#
OC5# / GPIO29
OC6# / GPIO30
OC7# / GPIO31

SMB

SATA

SYS

GPIO

GPIO

USB

GPIO21 / SATA0GP
GPIO19 / SATA1GP
GPIO36 / SATA2GP
GPIO37 / SATA3GP

GPIO

Clocks

GPIO16 / DPRSLPVR

TP0 / BATLOW#

PWRBTN#

LAN_RST#

POWER MGT

PCI-EXPRESS

SPI

ICH7M A0_BGA652~D

RSMRST#

SATACLKREQ#/GPIO35

ICH7M A0_BGA652~D

DMI0RXN
DMI0RXP
DMI0TXN

DMI0TXP

DMI1RXN
DMI1RXP
DMI1TXN

DMI1TXP

DMI2RXN
DMI2RXP
DMI2TXN

DMI2TXP

DMI3RXN
DMI3RXP
DMI3TXN

DMI3TXP

DMI_CLKN

DMI_CLKP

DIRECT MEDIA INTERFACE

DMI_ZCOMP

DMI_IRCOMP

USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4N
USBP4P
USBP5N
USBP5P
USBP6N
USBP6P
USBP7N
USBP7P

USBRBIAS#

USBRBIAS

CLK14
CLK48

SUSCLK
SLP_S3#

SLP_S4#
SLP_S5#

PWROK

GPIO9
GPIO10
GPIO12
GPIO13
GPIO14
GPIO15
GPIO24
GPIO25

GPIO38
GPIO39

V26
V25
U28
U27

Y26
Y25
W28
W27

AB26
AB25
AA28
AA27

AD25
AD24
AC28
AC27

AE28
AE27

C25
D25

F1
F2
G4
G3
H1
H2
J4
J3
K1
K2
L4
L5
M1
M2
N4
N3

D2
D1

AF19
AH18
AH19
AE19

AC1
B2

C20
B24

D23
F22

AA4
AC22
C21
C23
C19
Y4

E20
A20
F19
E19
R4
E22
R3
D20
AD21
AD20
AE20

+3.3V_RUN

PLTRST#

SUSPWROK

1 2

R296 10K_0402_5%~D

SIO_EXT_SCI#

PLTRST_DELAY#
WWAN_RADIO_DIS#

DMI_MTX_IRX_N0
DMI_MTX_IRX_P0
DMI_MRX_ITX_N0
DMI_MRX_ITX_P0

DMI_MTX_IRX_N1
DMI_MTX_IRX_P1
DMI_MRX_ITX_N1
DMI_MRX_ITX_P1

DMI_MTX_IRX_N2
DMI_MTX_IRX_P2
DMI_MRX_ITX_N2
DMI_MRX_ITX_P2

DMI_MTX_IRX_N3
DMI_MTX_IRX_P3
DMI_MRX_ITX_N3
DMI_MRX_ITX_P3

CLK_PCIE_ICH#
CLK_PCIE_ICH

DMI_IRCOMP
USBP0-

USBP0+
USBP1­USBP1+
USBP2­USBP2+
USBP3­USBP3+
USBP4­USBP4+
USBP5­USBP5+
USBP6­USBP6+
USBP7­USBP7+

USBRBIAS

2

R425

8.2K_0402_5%~D

1 2

CLK_ICH_14M
CLK_ICH_48M

ICH_SUSCLK

SIO_SLP_S3#
SIO_SLP_S5#
ICH_PWRGD
DPRSLPVR
ICH_BATLOW#
SIO_PWRBTN#

USB_IDE#
SATA_DET#

GPIO24

DMI_MTX_IRX_N0 10
DMI_MTX_IRX_P0 10
DMI_MRX_ITX_N0 10
DMI_MRX_ITX_P0 10

DMI_MTX_IRX_N1 10
DMI_MTX_IRX_P1 10
DMI_MRX_ITX_N1 10
DMI_MRX_ITX_P1 10

DMI_MTX_IRX_N2 10
DMI_MTX_IRX_P2 10
DMI_MRX_ITX_N2 10
DMI_MRX_ITX_P2 10

DMI_MTX_IRX_N3 10
DMI_MTX_IRX_P3 10
DMI_MRX_ITX_N3 10
DMI_MRX_ITX_P3 10

CLK_PCIE_ICH# 6
CLK_PCIE_ICH 6

R427 24.9_0402_1%~D

1 2

R113 20_0402_1%~D

1 2

Within 500 mils

CLK_ICH_14M 6
CLK_ICH_48M 6

T36

PAD~D

SIO_SLP_S3# 39
SIO_SLP_S5# 39

PLTRST# 10,21,28,34

SUSPWROK 18 ,42

SIO_EXT_SCI# 39

USB_IDE# 25

T39 PAD~D

SATA_CLKREQ# 6
WWAN_RADIO_DIS# 34

USBP0- 34

USBP0+ 34

USBP1- 38

USBP1+ 38

USBP2- 25

USBP2+ 25

USBP3- 32

USBP3+ 32

USBP4- 32

USBP4+ 32

USBP5- 32

USBP5+ 32

USBP6- 32

USBP6+ 32

USBP7- 36

USBP7+ 36

ICH_PWRGD 10,42

DPRSLPVR 49

SIO_PWRBTN# 39

10K_0402_5%~D

Within 500 mils

+1.5V_RUN

<---Mini2 WLAN
<---SIO USB Hub
<---BT Moudle
<---SIDE TOP
<---SIDE BOTTOM
<---REAR
<---REAR
<---Docking

10K_0402_5%~D

1 2

1 2

R1799 0_0402_5%~D

12

R74

USB_OC3#
USB_OC0#
USB_OC1#
USB_OC2#
USB_OC7#

USB_OC5#

USB_OC6#
USB_OC4#

R280

+3.3V_SUS

R784

100K_0402_5%~D

1 2

1

Place closely pin U45.AC1

CLK_ICH_14M

12

R379
10_0402_5%~D

@

1

C380

@

2

4.7P_0402_50V8C~D

PM_EXTTS#1 10

SATA_DET# 25

PLTRST_DELAY# 52

1 2

R1622 10K_0402_5%~D

1 2

R1623 10K_0402_5%~D

1 2

R1624 10K_0402_5%~D

1 2

R1625 10K_0402_5%~D

1 2

R1626 10K_0402_5%~D

1 2

R1627 10K_0402_5%~D

1 2

R1628 10K_0402_5%~D

1 2

R1629 10K_0402_5%~D

Place closely pin U45.B2

CLK_ICH_48M

12

R126
10_0402_5%~D

@

1

C124

4.7P_0402_50V8C~D

2

@

USB_OC2# 25
USB_OC3# 32

USB_OC4# 32
USB_OC6# 32
USB_OC5# 32

+3.3V_SUS

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.
ICH7(3/4)

LA-2792

23 70Tuesday, Feb ru ar y 07, 2006

1

1.0

of

5

4

3

2

1

ICH_V5REF_RUN

+3.3V_RUN

+1.5V_DMIPLL

1

C458

2

0.01U_0402_16V7K~D

1

2

C422

+1.5VRUN_L

1

+

C151

2

220U_V_4VM_R45~D

1

C460

2

10U_0805_4VAM~D

+VCCSATAPLL

C374

0.1U_0402_16V4Z~D

1

2

+3.3V_SUS

0.1U_0402_16V4Z~D

+1.5VRUN_L

C454

1

C449

2

+1.5V_RUN

0.1U_0402_16V4Z~D

+1.5V_RUN

1U_0603_10V4Z~D

+1.5V_RUN

0.1U_0402_16V4Z~D

D D

R535

100_0402_5%~D

10_0402_5%~D

C C

B B

+1.5V_RUN

A A

R537

12

12

1 2

0.5_0603_1%

+3.3V_RUN+5 V _RUN

+3.3V_SUS+5V_SUS

R59

21

D16
RB751S40T1_SOD523-2~D

ICH_V5REF_RUN

1

C370

0.1U_0402_16V4Z~D

2

21

D17
RB751S40T1_SOD523-2~D

ICH_V5REF_SUS

1

C436

0.1U_0402_16V4Z~D

2

+1.5V_RUN

L107

10UH_LB2012T100MR_20%_0805~D

1 2

+1.5V_RUN

R37

0.5_0603_1%

1 2

1

C286

2

10U_0805_4VAM~D

L41

1 2

BLM21PG600SN1D_0805~D

L42

BLM18AG601SN1D_0603~D

1 2

+VCCSATAPLL

1

+3.3V_RUN

C337

2

0.1U_0402_16V4Z~D

+3.3V_SUS

0.1U_0402_16V4Z~D

ICH_V5REF_SUS

1

1

2

0.1U_0402_16V4Z~D

C461

1

C453

C459

2

2

C353

0.1U_0402_16V4Z~D

1

2

1

2

1

2

1

2

0.1U_0402_16V4Z~D

+1.5V_DMIPLL

0.1U_0402_16V4Z~D

C455

C382

U45F

G10

V5REF[1]

AD17

V5REF[2]

F6

V5REF_Sus

AA22

Vcc1_5_B[1]

AA23

Vcc1_5_B[2]

AB22

Vcc1_5_B[3]

AB23

Vcc1_5_B[4]

AC23

Vcc1_5_B[5]

AC24

Vcc1_5_B[6]

AC25

Vcc1_5_B[7]

AC26

Vcc1_5_B[8]

AD26

Vcc1_5_B[9]

AD27

Vcc1_5_B[10]

AD28

Vcc1_5_B[11]

D26

Vcc1_5_B[12]

D27

Vcc1_5_B[13]

D28

Vcc1_5_B[14]

E24

Vcc1_5_B[15]

E25

Vcc1_5_B[16]

E26

Vcc1_5_B[17]

F23

Vcc1_5_B[18]

F24

Vcc1_5_B[19]

G22

Vcc1_5_B[20]

G23

Vcc1_5_B[21]

H22

Vcc1_5_B[22]

H23

Vcc1_5_B[23]

J22

Vcc1_5_B[24]

J23

Vcc1_5_B[25]

K22

Vcc1_5_B[26]

K23

Vcc1_5_B[27]

L22

Vcc1_5_B[28]

L23

Vcc1_5_B[29]

M22

Vcc1_5_B[30]

M23

Vcc1_5_B[31]

N22

Vcc1_5_B[32]

N23

Vcc1_5_B[33]

P22

Vcc1_5_B[34]

P23

Vcc1_5_B[35]

R22

Vcc1_5_B[36]

R23

Vcc1_5_B[37]

R24

Vcc1_5_B[38]

R25

Vcc1_5_B[39]

R26

Vcc1_5_B[40]

T22

Vcc1_5_B[41]

T23

Vcc1_5_B[42]

T26

Vcc1_5_B[43]

T27

Vcc1_5_B[44]

T28

Vcc1_5_B[45]

U22

Vcc1_5_B[46]

U23

Vcc1_5_B[47]

V22

Vcc1_5_B[48]

V23

Vcc1_5_B[49]

W22

Vcc1_5_B[50]

W23

Vcc1_5_B[51]

Y22

Vcc1_5_B[52]

Y23

Vcc1_5_B[53]

B27

Vcc3_3[1]

AG28

VccDMIPLL

AB7

Vcc1_5_A[1]

AC6

Vcc1_5_A[2]

AC7

Vcc1_5_A[3]

AD6

Vcc1_5_A[4]

AE6

Vcc1_5_A[5]

AF5

Vcc1_5_A[6]

AF6

Vcc1_5_A[7]

AG5

Vcc1_5_A[8]

AH5

Vcc1_5_A[9]

AD2

VccSATAPLL

AH11

Vcc3_3[2]

AB10

Vcc1_5_A[10]

AB9

Vcc1_5_A[11]

AC10

Vcc1_5_A[12]

AD10

Vcc1_5_A[13]

AE10

Vcc1_5_A[14]

AF10

Vcc1_5_A[15]

AF9

Vcc1_5_A[16]

AG9

Vcc1_5_A[17]

AH9

Vcc1_5_A[18]

E3

VccSus3_3[19]

C1

VccUSBPLL

AA2

VccSus1_05/VccLAN1_05[1]

Y7

VccSus1_05/VccLAN1_05[2]

V5

VccSus3_3/VccLAN3_3[1]

V1

VccSus3_3/VccLAN3_3[2]

W2

VccSus3_3/VccLAN3_3[3]

W7

VccSus3_3/VccLAN3_3[4]

Vcc1_05[1]
Vcc1_05[2]
Vcc1_05[3]
Vcc1_05[4]
Vcc1_05[5]
Vcc1_05[6]
Vcc1_05[7]
Vcc1_05[8]

Vcc1_05[9]
Vcc1_05[10]
Vcc1_05[11]
Vcc1_05[12]
Vcc1_05[13]
Vcc1_05[14]
Vcc1_05[15]
Vcc1_05[16]
Vcc1_05[17]
Vcc1_05[18]
Vcc1_05[19]
Vcc1_05[20]

Vcc3_3 / VccHDA

VccSus3_3/VccSusHDA

V_CPU_IO[1]
V_CPU_IO[2]
V_CPU_IO[3]

Vcc3_3[3]
Vcc3_3[4]
Vcc3_3[5]
Vcc3_3[6]
Vcc3_3[7]
Vcc3_3[8]

Vcc3_3[9]
Vcc3_3[10]
Vcc3_3[11]

Vcc3_3[12]
Vcc3_3[13]
Vcc3_3[14]
Vcc3_3[15]
Vcc3_3[16]
Vcc3_3[17]
Vcc3_3[18]
Vcc3_3[19]
Vcc3_3[20]
Vcc3_3[21]

VccRTC
VccSus3_3[1]
VccSus3_3[2]

VccSus3_3[3]
VccSus3_3[4]
VccSus3_3[5]
VccSus3_3[6]

VccSus3_3[7]
VccSus3_3[8]
VccSus3_3[9]

VccSus3_3[10]
VccSus3_3[11]
VccSus3_3[12]
VccSus3_3[13]
VccSus3_3[14]
VccSus3_3[15]
VccSus3_3[16]
VccSus3_3[17]
VccSus3_3[18]

Vcc1_5_A[19]
Vcc1_5_A[20]

Vcc1_5_A[21]
Vcc1_5_A[22]
Vcc1_5_A[23]

Vcc1_5_A[24]
Vcc1_5_A[25]

VccSus1_05[1]
VccSus1_05[2]

VccSus1_05[3]

Vcc1_5_A[26]
Vcc1_5_A[27]
Vcc1_5_A[28]
Vcc1_5_A[29]
Vcc1_5_A[30]

ICH7M A0_BGA652~D

+1.05V_VCCP

L11
L12
L14
L16
L17
L18
M11
M18
P11
P18
T11
T18
U11
U18
V11
V12
V14
V16
V17
V18

U6
R7
AE23

AE26
AH26

AA7
AB12
AB20
AC16
AD13
AD18
AG12
AG15
AG19

A5
B13
B16
B7
C10
D15
F9
G11
G12
G16

W5
P7
A24

C24
D19
D22

0.1U_0402_16V4Z~D

G19
K3

K4
K5
K6
L1
L2
L3
L6
L7
M6
M7
N7

AB17
AC17

T7
F17
G17

AB8
AC8

K7

C474 0.1U_0402_16V4Z~D

C28
G20

A1
H6
H7
J6
J7

1

2

1

2

C393

1 2

C387

1

2

1

2

1

C392

2

0.1U_0402_16V4Z~D

1U_0603_10V4Z~D

+3.3V_SUS

1

2

1

1

C412

C388

2

2

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

1

2

0.1U_0402_16V4Z~D

1

1

C406

2

2

0.1U_0402_16V4Z~D

+1.5V_RUN

+1.5V_RUN
+1.5V_RUN
+1.5V_RUN

+1.5V_RUN

C1444

0.1U_0402_16V4Z~D

1

+

C450

2

CRB is 270uF

C407

330U_D2E_2.5VM_R9~D

+1.05V_VCCP

+3.3V_RUN

C361

0.1U_0402_16V4Z~D

C338

0.1U_0402_16V4Z~D

+3.3V_SUS

+3.3V_SUS

C405

0.1U_0402_16V4Z~D

C442

0.1U_0402_16V4Z~D

1 2

1 2

C445

0.1U_0402_16V4Z~D

1 2

C424

4.7U_0603_6.3V4Z~D

+3.3V_RUN

U45E

A4

VSS[0]

A23

VSS[1]

B1

VSS[2]

B8

VSS[3]

B11

VSS[4]

B14

VSS[5]

B17

VSS[6]

B20

VSS[7]

B26

VSS[8]

B28

VSS[9]

C2

VSS[10]

C6

VSS[11]

C27

VSS[12]

D10

VSS[13]

D13

VSS[14]

D18

VSS[15]

D21

VSS[16]

D24

VSS[17]

E1

VSS[18]

E2

VSS[19]

E4

VSS[21]

+3.3V_RUN

1

C339

0.1U_0402_16V4Z~D

2

+RTC_CELL

1

1

2

2

C347

C328

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

E8

VSS[22]

E15

VSS[23]

F3

VSS[24]

F4

VSS[25]

F5

VSS[26]

F12

VSS[27]

F27

VSS[28]

F28

VSS[29]

G1

VSS[30]

G2

VSS[31]

G5

VSS[32]

G6

VSS[33]

G9

VSS[34]

G14

VSS[35]

G18

VSS[36]

G21

VSS[37]

G24

VSS[38]

G25

VSS[39]

G26

VSS[40]

H3

VSS[41]

H4

VSS[42]

H5

VSS[43]

H24

VSS[44]

H27

VSS[45]

H28

VSS[46]

J1

VSS[47]

J2

VSS[48]

J5

VSS[49]

J24

VSS[50]

J25

VSS[51]

J26

VSS[52]

K24

VSS[53]

K27

VSS[54]

K28

VSS[55]

L13

VSS[56]

L15

VSS[57]

L24

VSS[58]

L25

VSS[59]

L26

VSS[60]

M3

VSS[61]

M4

VSS[62]

M5

VSS[63]

M12

VSS[64]

M13

VSS[65]

M14

VSS[66]

M15

VSS[67]

M16

VSS[68]

M17

VSS[69]

M24

VSS[70]

M27

VSS[71]

M28

VSS[72]

N1

VSS[73]

N2

VSS[74]

N5

VSS[75]

N6

VSS[76]

N11

VSS[77]

N12

VSS[78]

N13

VSS[79]

N14

VSS[80]

N15

VSS[81]

N16

VSS[82]

N17

VSS[83]

N18

VSS[84]

N24

VSS[85]

N25

VSS[86]

N26

VSS[87]

P3

VSS[88]

P4

VSS[89]

P12

VSS[90]

P13

VSS[91]

P14

VSS[92]

P15

VSS[93]

P16

VSS[94]

P17

VSS[95]

P24

VSS[96]

P27

VSS[97]

ICH7M A0_BGA652~D

VSS[98]

VSS[99]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
VSS[159]
VSS[160]
VSS[161]
VSS[162]
VSS[163]
VSS[164]
VSS[165]
VSS[166]
VSS[167]
VSS[168]
VSS[169]
VSS[170]
VSS[171]
VSS[172]
VSS[173]
VSS[174]
VSS[175]
VSS[176]
VSS[177]
VSS[178]
VSS[179]
VSS[180]
VSS[181]
VSS[182]
VSS[183]
VSS[184]
VSS[185]
VSS[186]
VSS[187]
VSS[188]
VSS[189]
VSS[190]
VSS[191]
VSS[192]
VSS[193]
VSS[194]

P28
R1
R11
R12
R13
R14
R15
R16
R17
R18
T6
T12
T13
T14
T15
T16
T17
U4
U12
U13
U14
U15
U16
U17
U24
U25
U26
V2
V13
V15
V24
V27
V28
W6
W24
W25
W26
Y3
Y24
Y27
Y28
AA1
AA24
AA25
AA26
AB4
AB6
AB11
AB14
AB16
AB19
AB21
AB24
AB27
AB28
AC2
AC5
AC9
AC11
AD1
AD3
AD4
AD7
AD8
AD11
AD15
AD19
AD23
AE2
AE4
AE8
AE11
AE13
AE18
AE21
AE24
AE25
AF2
AF4
AF8
AF11
AF27
AF28
AG1
AG3
AG7
AG11
AG14
AG17
AG20
AG25
AH1
AH3
AH7
AH12
AH23
AH27

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.
ICH7(4/4)

LA-2792

24 70Tuesday, Feb ru ar y 07, 2006

1

1.0

of

5

4

3

+5VMOD

2

1

1

JMOD

72

G71G

1

8.3

G69G

1

3

3

5

5

7

7

9

9

11

11

13

13

15

15

17

17

19

19

21

21

23

23

25

25

27

27

29

29

31

31

33

33

35

35

37

37

39

39

41

41

43

43

45

45

47

47

49

49

51

51

53

53

55

55

57

57

59

59

61

61

63

63

65

65

67

67

TYCO_1770530-1~D

70

SATA_DET#
USB_OC2#

USBP2+
USBP2-

DASP#

IDE_DCS1#

PDIAG#

IDE_IRQ
IDE_DDACK#
IDE_DIORDY

IDE_DDREQ
IDE_DD0
IDE_DD14
IDE_DD13

IDE_DD3
IDE_DD4
IDE_DD10
IDE_DD9

IDE_DD7

2

D D

IDE_DD[0..15]22

IDE_DD0
IDE_DD1
IDE_DD2
IDE_DD3
IDE_DD4
IDE_DD5

IDE_DD7
IDE_DD8
IDE_DD9
IDE_DD10
IDE_DD11

USB_IDE#23

IDE_DD12
IDE_DD13
IDE_DD14
IDE_DD15

IDE_DA0
IDE_DA1
IDE_DA2

IDE_DCS1#
IDE_DCS3#

IDE_DDACK#
IDE_DIOR#

IDE_DIOW#
IDE_DIORDY
IDE_DDREQ
IDE_IRQ

IDE_RST_MOD

R1330

100K_0402_5%~D

1 2

+3.3V_ALW

BAY_MODPRES#38

R1328

1 2

470_0402_5%~D

R1329

33_0402_5%~D

1 2

1 2

100K_0402_5%~D

R1331

C C

IDE_DA[0..2]22

IDE_DCS1#22
IDE_DCS3#22

IDE_DDACK#22
IDE_DIOR#22

IDE_DIOW#22
IDE_DIORDY22
IDE_DDREQ22

IDE_IRQ22

IDE_RST_MOD23

B B

+3.3V_SUS

IDE_DCS3#
IDE_DA2IDE_DD6
IDE_DA0
IDE_DA1

CSEL2
IDE_DIOR#
IDE_DIOW#
IDE_DD15

IDE_DD1
IDE_DD2
IDE_DD12
IDE_DD11

IDE_DD5
IDE_DD6
IDE_DD8
MOD_RST
USB_IDE#

BAY_MODPRES#

2

4

4

6

6

8

8

10

10

12

12

14

14

16

16

18

18

20

20

22

22

24

24

26

26

28

28

30

30

32

32

34

34

36

36

38

38

40

40

42

42

44

44

46

46

48

48

50

50

52

52

54

54

56

56

58

58

60

60

62

62

64

64

66

66

68

68

C1302

1

2

4.7U_0603_6.3V4Z~D

1

2

C1303

0.1U_0402_16V4Z~D

USB_OC2# 23

USBP2+ 23
USBP2- 23

1

2

C1305

C1304

0.1U_0402_16V4Z~D

SATA_DET# 23

1

2

0.1U_0402_16V4Z~D

+5VHDD +3.3V_RUN

1

1

1

C1312

C1311

C1310

10U_0805_10V4Z~D

2

2

1000P_0402_50V7K~D

PSATA_IRX_DTX_N0_C22
PSATA_IRX_DTX_P0_C22

2

1U_0603_10V4Z~D

0.1U_0402_16V4Z~D

Pleace near HD CONN

C1319

3900P_0402_50V7K~D

3900P_0402_50V7K~D

12
12

C1323

1

2

C1313

1

2

PSATA_ITX_DRX_N022

C1314

PSATA_ITX_DRX_P022

0.1U_0402_16V4Z~D

PSATA_IRX_DTX_N0
PSATA_IRX_DTX_P0

+3.3V_RUN

C1315

@

10U_0805_10V4Z~D

+5VHDD

close SATA connector

+3.3V_RUN

R512 4.7K_0402_5%~D

1 2

IDE_DIORDY

2

6

1

1

C1316

@

2

2

1000P_0402_50V7K~D

PSATA_ITX_DRX_P0
PSATA_ITX_DRX_N0

TOP VIEW

1

C1317

@

0.1U_0402_16V4Z~D

Pleace near HD CONN

1

2

2

1U_0603_10V4Z~D

JSATA

1

GND

2

RX+

3

RX-

4

GND

5

TX-

6

TX+

7

GND

8

3.3V

9

3.3V

10

3.3V

11

GND

12

GND

13

GND

14

5V

15

5V

16

5V

17

GND

18

Reserved

19

GND

20

12V

21

12V

22

12V

TYCO_1775191-1_RV~D

C1318

@

GND1
GND2

3

4

WF1F068N1A

5

1

C1345

2

@

0.1U_0402_16V4Z~D

23
24

A A

Main SATA +5V Default

DELL CONFIDENTIAL/PROPRIETARY

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

DVD MODULE

Size Document Number Rev

Date: Sheet

LA-2792

25 70Tuesday, Fe b r u a r y 07, 2006

1

of

1.0

5

4

3

2

1

45

D D

+5V_SUS

C498

0.1U_0402_16V4Z~D

U22

1

1

2

C486

C492

2

0.047U_0402_16V4Z~D

1U_0603_10V4Z~D

AUDIO_AVDD_ON38

From SIO

2

AUDIO_AVDD_ON TPS793475_BYPASS

1

1

2
3

Default POP the LDO U22
When U22 is popped, no pop L47.

5

OUT

IN
GND

4

BYPASS

EN

TPS793475DBVRG4_SOT23-5~D

+VDDA=4.75V

C523

0.1U_0402_16V4Z~D

+VDDA

1

C500

1

2

1

C505

C169

2

2

0.1U_0402_16V4Z~D

2.2U_0603_6.3V6K~D

0.047U_0402_16V4Z~D

@

1 2

1

2

W=30 mil

C C

ICH_RST_AUDIO#22
ICH_SYNC_AUDIO22
ICH_SDOUT_AUDIO22

ICH_AC_BITCLK22

ICH_AC_SDIN022

1 2

R160 33_0402_5%~D

VREFOUT

Close to U10.3

ICH_AC_BITCLK

12

R361
22_0402_5%~D

@

1

C362
22P_0402_50V8J~D

B B

2

@

Close to U10.5

ICH_SDOUT_AUDIO

12

R488
47_0402_5%~D

@

1

C495
22P_0402_50V8J~D

2

@

HP_NB_SENSE27,38

HP_NB_SENSE

SPDIF_SHDN38

DOCK_HP_MUTE#38

EAPD27

SPDIF_DOCK36

1

C176

2

1U_0603_10V4Z~D

ICH_AC_SDIN0_R

AC97VREFI
CAP2

R48

@

0_0402_5%~D

1 2

SPDIF_SHDN

DOCK_HP_MUTE#

EAPD

SPDIF_DOCK

C506

Close to U10.18 Close to U10.20

C491

5

1U_0603_10V4Z~D

1

2

AC97VREFI

A A

C181

CAP2

1

1

C510

2

1U_0603_10V4Z~D

2

0.1U_0402_16V4Z~D

4

1

1

C487

2

2

0.1U_0402_16V4Z~D

2.2U_0603_6.3V6K~D

19
18
20

21

22

30

31

32

11

+5V_RUN

L47

BLM18AG601SN1D_0603~D

SPKR23
BEEP38

+VDDA

+3.3V_RUN

1

1

2

2

26

U10

8
7
2
3
5

1

6

RESET#
SYNC
SDATA_OUT
BIT_CLK
SDATA_IN
VREF_OUT
VREF_IN
CAP2

STAC9200

GPIO0

GPIO1

GPIO2

SPDIF _ IN/EAPD /GPIO3

SPDIF _OUT

NC1
NC2

PAD_GND

33

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

4

DVDD

DVSS

AVDD

AVSS117AVSS2

29

STAC9200X5NAEB1XR_QFN32~D

C1825

0.1U_0402_16V4Z~D

LINE_IN_L

LINE_IN_R

CD_L

CD_R

MIC1

MIC2

HP_L

HP_R

LOUT_L

LOUT_R

MONO_OUT

SENSE_A

C1826

10U_0805_10V4Z~D

15

16

10

12

13

14

27

28

C189 0.1U_0402_16V4Z~D

23

24

0.1U_0402_16V4Z~D

25

9

+VDDA

+Z2401

1

2

5

U28

1

P

A

4

Y

2

B

G

SN74AHCT1G86DCKR_SC70-5~D

3

Note:U28,R496,R162,C529
place as close as U19

HP_OUT_L 27

HP_OUT_R 27

1 2

C179

1 2

1 2

R89 2.2K_0402_5%~D

1 2

R96 2.2K_0402_5%~D

SENSE_A

HP_NB_SENSE

2N7002W-7-F_SOT323~D

Q44

C1780 1000P_0402_50V7K~D
C1781 1000P_0402_50V7K~D

2

G

2

C539

0.1U_0402_16V4Z~D

R496

10K_0402_5%~D

1 2

INT_MIC 27

NB_MICIN_L 27

NB_MICIN_R 27

1 2
1 2

12

R22

39.2K_0402_1%~D

13

D

S

2.2K_0402_5%~D

20K_0402_1%~D

12

R109

13

D

2

G

Q54

S

2N7002W-7-F_SOT323~D

2

31

single gate TTL

C529

0.1U_0402_16V4Z~D

12

R162

STAC9200 Rev.

AUD_LINE_OUT 27

R1768

5.1K_0402 _1%~D

12

MIC_SWITCH 27

1 2

CA1

B1

+VDDA

PC_BEEPZ2402 Z2404

TRACE>15 mil

5.11K 10K

39.2K 20K

PC_BEEP 27

R22 R109

DELL CONFIDENTIAL/PROPRIETARY

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.
Azalia (HD) Codec

LA-2792

26 70Tuesday, Feb ru ar y 07, 2006

1

of

1.0

5

+3VRUN_4411

1

19

PVDD

7

10

SVDD

SVss

2

C114

2.2U_0603_6.3V6K~D

2

OUTR
OUTL

NC-4
NC-6

NC-8
NC-12
NC-16
NC-20

PGND

SGND

MAX4411ETP+_TQFN20~D

17

+3.3V_RUN

1 2
1 2

C493

47P_0402_50V8J~D

12

1

1

2

2

R132
100K_0402_5%~D

HP_NB_SENSE

AUD_LINE_IN_R
AUD_LINE_IN_L

C501

C146

2.2U_0603_6.3V6K~D

47P_0402_50V8J~D

U5

14
18

15
13

C1P

1

1
3

2

C1N

C113

2.2U_0603_6.3V6K~D

SHDNR#
SHDNL#

INR
INL

C1P
C1N

PVss

5

PVSS

1

2

D D

HP_OUT_R26
HP_OUT_L26

C C

C148 1U_0603_10V4Z~D

C147

1U_0603_10V4Z~D

Speaker Connector

INT_SPK_R1
INT_SPK_R2

15 mils trace

1

1

C566

@

1000P_0402_50V7K~D

C565

2

@

1000P_0402_50V7K~D

0.022U_0402_16V7K~D

SPK_SHUTDOWN#

2

B B

AUD_LINE_OUT26

+3.3V_RUN

R156

100K_0402_5%~D

1 2

13

A A

NB_MUTE38

5

D

2

G

S

Q43
2N7002W-7-F_SOT323~D

11
9

4
6
8
12
16
20

PC_BEEP26

C199

12

EAPD26

4

L52
BLM18AG601SN1D_0603~D

1 2

HP_SPK_R1
HP_SPK_L1

JSPK

1

1

2

2

MOLEX_53398-0271~D

1

1

C1793

2

2

47P_0402_50V8J~D

13

D

2

G

S

4

+3.3V_RUN

C1800

2.2U_0603_6.3V6K~D

INT_MIC+

INT_MIC+32

INT_MIC-

INT_MIC-32

C1801

2.2U_0603_6.3V6K~D

1

C293

C536

2

47P_0402_50V8J~D

0.047U_0402_16V4Z~D

Q11

@

2N7002W-7-F_SOT323~D

LM358DR2G_SOIC8~D

+VDDA

12

12

12

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

12

12

12

C1791

0.047U_0402_16V4Z~D
C1792

0.047U_0402_16V4Z~D

U9B

7

R1781
1K_0402_5%~D

R1780
1K_0402_5%~D

C1798

1 2
1 2

C1799

R1782
1K_0402_5%~D

R1783
1K_0402_5%~D

1

2

PC_BEEP

RIN-

12

12

3

+VDDA

+VDDA

O

C534
1U_0603_10V4Z~D

17

19

12

R1775
100K_0402_5%~D

8

P

IN+

IN-

G

4

10K_0402_5%~D

1 2
1 2

10K_0402_5%~D

U19

7

9

5

5
6

12

1

C1796

2.2U_0603_6.3V6K~D

R1776

2

100K_0402_5%~D

R1784

100K_0402_5%~D

1 2

R1777

R1778

3

IN+

2

IN-

1 2

100K_0402_5%~D

W=40mils

16

15

6

VDD

PVDD1

RIN+

RIN-

LIN+

LIN-

SHUTDOWN

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

PVDD2

GND41GND311GND213GND1

20

TPA6017A2PWP_TSSOP20~D

3

+VDDA

U9A

8

LM358DR2G_SOIC8~D

P

1

O

G

4

R1779

+5VAMPVCC

GAIN0
GAIN1

ROUT+

ROUT-

LOUT+

LOUT-

NC

BYPASS

PAD_GND

MIC_BIAS

1 2

C1797

0.1U_0402_16V4Z~D

L45

1 2

BLM21PG600SN1D_0805~D

2
3

18

14

4

8

12
10

21

1

C485
10U_0805_10V4Z~D

2

AUD_GAIN0
AUD_GAIN1

INT_SPK_R1

INT_SPK_R2

BYPASS

1

2

NB_MICIN_L26

NB_MICIN_R26

MIC_SWITCH26

INT_MIC 26

HP_SPK_L1 HP_SPK_L2

+5V_SUS

1

C502

0.1U_0402_16V4Z~D

2

NOTE: SPEAKER TRACE WIDTH
SHOULD BE MINIMUM 10 MILS

C537

0.47U_0402_16V4Z~D

2

VREFOUT

R1770

4.99_0402_1%~D

R2140

4.99_0402_1%~D

+3.3V_RUN

12

BLM18AG121SN1D_0603~D

BLM18AG121SN1D_0603~D

C1775

2.2U_0603_6.3V6K~D

MIC_L1

12

MIC_R1 MIC_R2

12

2.2U_0603_6.3V6K~D

R1769

100K_0402_5%~D

L16

12
12

L15

+5VAMPVCC

1

2

2

R1771

4.7K_0402_5%~D

MIC_L2MIC_BIAS

1 2

C1794

1 2

R1774

20K_0402_1%~D

1

C109

C108

2

100P_0402_50V8J~D

C494

0.1U_0402_16V4Z~D

1

C177

2

100P_0402_50V8J~D

+5VAMPVCC

12

12

1

Gain Setting

R165
1K_0402_5%~D

R171
1K_0402_5%~D@

6dB

10dB

15.6dB

21.6dB

JMIC

1
2
6
3

4
5

7
8

FOX_JA9033L-B1N6-7F~D

JAUDIO

1
2
6
3

4
5

7
8

FOX_JA9033L-B1N6-7F~D

12

12

IMPEDANCE

90K ohm

70K ohm

45K ohm

25K ohm

C1795

1 2

1U_0603_10V4Z~D

12

12

R1772

4.7K_0402_5%~D

BLM18AG121SN1D_0603~D

L108

BLM18AG121SN1D_0603~D

12

12

R1773

20K_0402_1%~D

1

2

100P_0402_50V8J~D

GAIN0 INPUTAV(inv)GAIN1

0

0

1

*

L17

HP_SPK_R2HP_SPK_R1

HP_NB_SENSE26,38

AUD_GAIN0
AUD_GAIN1

12

12

1

C153

2

100P_0402_50V8J~D

0

1

0

11

DELL CONFIDENTIAL/PROPRIETARY

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.
AMP and PHONE JACK

LA-2792

27 70Tuesday, Feb ru ar y 07, 2006

1

R164
1K_0402_5%~D

R170
1K_0402_5%~D

@

of

1.0

5

Layout Notice : Place as close
chip as possible.

+3.3V_SRC

D D

ENAB_3VLAN41

C C

LAN_TPM_EN#38

B B

A A

Q62

SI3456BDV-T1-E3_TSOP6~D

D

6

S

45
2
1

CLK_PCI_LOM6

LPC_LAD[0..3]22,38,39

LPC_LFRAME#22,38,39
PLTRST#10,21,23,34
IRQ_SERIRQ23,30,38,39

R1585 10K_0402_5%~D
R1584 10K_0402_5%~D
R1583 10K_0402_5%~D

LOM_CABLE_DETECT38

+3VLAN

4.7K_0402_5%~D

R1268 4.7K_0402_5%~D@

C1393

G

3

12
12
12
12

R17 0_0402_5%~D

12

R1586 4.7K_0402_5%~D@

ICH_SMBCLK6,23,34
ICH_SMBDATA6,23,34

LOM_SCLK
LOM_SI

LINK_10#29

LINK_100#29
LAN_ACT#29

R1367

200_0402_1%~D

X4

1 2

LOM_SO
LOM_CS#
NV_STRAP0
NV_STRAP1

R1267

1 2
1 2

25MHZ_18PF_1BX25000CK1D~D

2

1

27P_0402_50V8J~D

Atmel AT45BCM021B

ST M45PE20

5

C1363

CLK_PCI_LOM

LPC_LAD0
LPC_LAD1
LPC_LAD2
LPC_LAD3

LPC_LFRAME#
PLTRST#
IRQ_SERIRQ

TPM_GPIO0
TPM_GPIO1
TPM_GPIO2

LOM_CABLE_DETECT

LINK_10#
LINK_100#

LAN_ACT#

12

2

C1394

1

27P_0402_50V8J~D

2

2

2

1

1

C1364

0.1U_0402_16V4Z~D

4.7U_0603_6.3V4Z~D

U214A

J8
J7

L10

J5
K9

J9

M10

H7
G4

J3

H3

J6

H9

H11

C5
C4

C8
C7

C9

E10

D9

C10

M2
M1

A9
B9

A10

B8

XTALO

M9

XTALI

L9

BCM5752KFBG A2_FPBGA144~D

NV_STRAP1

0

000

2

2

1

1

1

C1367

C1366

C1365

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

BCM5752

LCLK
LAD0

LAD1
LAD2
LAD3

LFRAME
LRESET
SERIRQ

TPM_GPIO0
TPM_GPIO1
TPM_GPIO2
TPM_EN

GPIO0
GPIO1
GPIO2
GPIO3

SMB_CLK
SMB_DATA

SCLK
SI
SO
CS
NV_STRAP0
NV_STRAP1

LINKLED
SPD100LED
SPD1000LED
TRAFFICLED

XTALO

XTALI

NV_STRAP0 SO SI CS# SCLK

LPC/TPM

GPIO

SMBUS

SPI

LED

Clock

Layout Notice : No high
speed signal should be
routed near RDAC or on
adjacent layer to RDAC

00

1

1

1

4

MMJT9435

C

2

B

1C4

+3VLAN

R7, R9 are 1/2 W rating

Power

Media

LOW_PWR

ATTN_BTTN

VMAINPRSNT

VAUXPRSNT

Control

REGSUP12

REGCTL12

REGSEN12

REGCTL25

REGSEN25

Control

Regulator

PCIE_TXDN
PCIE_TXDP
PCIE_RXDN
PCIE_RXDP

PCI-ETEST

REFCLK_SEL

SERIAL_DI

SERIAL_DO

GPHY_TVCOI

Bias

11

REFCLK­REFCLK+

REGCTL_PNP12

Pop C1375 for 5752-A0,
De-pop for 5752-A1

B11

TRD3+

B12

TRD3-

C11

TRD2+

C12

TRD2-

D11

TRD1+

D12

TRD1-

E11

TRD0+

E12

TRD0-

H4
A2

G11
B6

K12
J11

J12
M11
M12

PCIE_IRX_LOMTX_N3_C

M3

PCIE_IRX_LOMTX_P3_C

L3
L7
M7
A4

WAKE

L5
M5
B3

B1

PERST

B5

TCK

F3

TDI

B4

TDO

E3

TMS

D4

TRST

J1
M4
C6

A8

RDAC

R1364

1

4

E

+3VLAN

3

12

12

R9

2_1210_5%~D

Q63

1

MMJT9435T1G_SOT223~D

2 3

4

1

C1375
470P_0402_50V7K~D

2

@

LAN_TX3+

LAN_TX3+ 29

LAN_TX3-

LAN_TX3- 29

LAN_TX2+

LAN_TX2+ 29

LAN_TX2-

LAN_TX2- 29

LAN_TX1+

LAN_TX1+ 29

LAN_TX1-

LAN_TX1- 29

LAN_TX0+

LAN_TX0+ 29

LAN_TX0-

LAN_TX0- 29

LAN_LOW_PWR 38

R1439 4.7K_0402_5%~D

R11 1K_0402_5%~D
R10 1K_0402_5%~D

REGCTL_PNP12

REGCTL_PNP25

0.1U_0402_16V4Z~D

PCIE_WAKE#
CLK_PCIE_LOM#
CLK_PCIE_LOM

1 2

R18 4.7K_0402_5%~D@

PLTRST#

R1360

@

4.7K_0402_5%~D

1 2
1 2

R13 4.7K_0402_5%~D@

1 2

R14 4.7K_0402_5%~D

1 2

R16 0_0402_5%~D@

+3VLAN

1.18K_0402_1%~D

1 2

0.1U_0402_16V4Z~D

12
12

12

C1377

0.1U_0402_16V4Z~D

1 2
1 2

C1379

PCIE_WAKE# 34,38
CLK_PCIE_LOM# 6
CLK_PCIE_LOM 6

PLTRST# 10,21,23,34

LOM_SI

C1392

2

1

+3VLAN

0.1U_0402_16V4Z~D

1

C1368

R7

2

2_1210_5%~D

+1.2VLAN

0.1U_0402_16V4Z~D

1

C1361

2

+3VLAN
+3.3V_RUN

+3VLAN

+1.2VLAN

+2.5VLAN

PCIE_IRX_LOMTX_N3 23
PCIE_IRX_LOMTX_P3 23
PCIE_ITX_LOMRX_N3_C 23
PCIE_ITX_LOMRX_P3_C 23

U3

8

Q

7

VSS

6

RESET#

VCC

5

W#

M45PE20-VMN6TP_SO8~D

8
7
6
5

AT45BCM021B-SU_SO8~D

U188

@

SO

SCK

GND

RESET#

VCC

CS#

WP#

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

C1362

C1369

D
C

S#

SI

4.7U_0603_6.3V4Z~D

1

2

10U_0805_10V4Z~D

1

2

1
2
3
4

1
2
3
4

3

REGCTL_PNP25

Place closely pin J8

CLK_PCI_LOM

22_0402_5%~D

22P_0402_50V8J~D

R1365

LOM_SO
LOM_SCLK

LOM_CS#

3

4.7K_0402_5%~D

R78

+3VLAN

12

0_0603_5%~D

12

@

1

C78

2

@

12

R1366

@

4.7K_0402_5%~D

+3VLAN

1 2

@

4.7K_0402_5%~D

R120

1 2

+2.5VLAN

BLM18AG601SN1D_0603~D

BLM18AG601SN1D_0603~D

BLM18AG601SN1D_0603~D

0.1U_0402_16V4Z~D

+1.2VLAN

BLM18AG601SN1D_0603~D

4.7U_0603_6.3V4Z~D

BLM18AG601SN1D_0603~D

4.7U_0603_6.3V4Z~D

BLM18AG601SN1D_0603~D

4.7U_0603_6.3V4Z~D

0_0603_5%~D

4.7U_0603_6.3V4Z~D

R53

1

C80

0.1U_0402_16V4Z~D

2

@

L60

12

C1378

0.1U_0402_16V4Z~D

L61

12

C1376

0.1U_0402_16V4Z~D

L62

12

C1382

L63

12

1

C1387

2

L64

12

1

C1385

2

L65

12

1

C1383

2

R1368

12

1

C1390

@

2

1

2

3

+2.5VLAN

C1370

1

2

1

2

1

2

1

2

1

2

1

2

2

+3VLAN

41

Q68

MBT35200MT1G_TSOP6~D

256

0.1U_0402_16V4Z~D

1

1

C1371

2

2

XTALVDD

BIASVDD

AVDD

AVDDL

C1388

0.1U_0402_16V4Z~D

GPHY_PLLVDD

C1386

0.1U_0402_16V4Z~D

PCIE_PLLVDD

C1384

0.1U_0402_16V4Z~D

PCIE_SDS_VDD

C1391

@

0.1U_0402_16V4Z~D

2

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

1

2

1

C1742

2

PCIE_PLLVDD
GPHY_PLLVDD

1

C1741

C1740

2

+2.5VLAN

0.1U_0402_16V4Z~D

1

C1743

2

+3VLAN

+2.5VLAN

XTALVDD

PCIE_SDS_VDD

BIASVDD

AVDDL

AVDD

1

Layout Notice : 1.2V filter. Place as close

4.7U_0603_6.3V4Z~D

10U_0805_10V4Z~D

+1.2VLAN

chip as possible.

+1.2VLAN

2

2

2

1

1

C1352

C1351

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

U214B

D5

VDDC_0

D6

VDDC_1

D7

VDDC_2

D8

VDDC_3

H5

VDDC_4

H6

VDDC_5

H8

VDDC_6

J4

VDDC_7

Digial power

A3

VDDIO_0

C2

VDDIO_1

D10

VDDIO_2

F1

VDDIO_3

G10

VDDIO_4

J2

VDDIO_5

L1

VDDIO_6

L12

VDDIO_7

A5

VDDP_0

G3

VDDP_1

L11

VDDP_2

H12

XTALVDD

K4

PCIE_SDSVDD

A12

BIASVDD

F10

AVDDL_0

F11

AVDDL_1

A11

AVDD_0

F12

AVDD_1

K6

PCIE_PLLVDD

G12

GPHY_PLLVDD

LAN_LOW_PWR38

LOM_CLKREQ#6

DELL CONFIDENTIAL/PROPRIETARY

Title

Size Document Number Rev

Date: Sheet

@

20K_0402_5%~D

BCM5751M

1

C1353

C1354

0.1U_0402_16V4Z~D

BCM5752

BIAS

Analog
power

PLL

BCM5752KFBG A2_FPBGA144~D

1 2

R68

LOM_CLKREQ#

LA-2792

2

1

0.1U_0402_16V4Z~D

2

1

C1355

0.1U_0402_16V4Z~D

GND

1 2

R70

@

39K_0402_5%~D

@

R58

0_0402_5%~D

1

C1356

2

1

0.1U_0402_16V4Z~D

VSS_0
VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8

VSS_9
VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20

NC_10

NC_11

NC_12

NC_13

NC_14

NC_15

NC_16

NC_17

NC_18

NC_19

NC_20

NC_21

NC_22

NC_23

NC_24

NC_25

NC_26

NC_27

NC_28

NC_29

12

NC_0
NC_1
NC_2
NC_3
NC_4
NC_5
NC_6
NC_7
NC_8
NC_9

28 70Tuesday, Fe b r u a r y 07, 2006

C1357

0.1U_0402_16V4Z~D

B2
B10
E4
E5
E6
E7
E8
E9
F4
F5
F6
F7
F8
F9
G5
G6
G7
G8
L2
L6
M6

A1
A6
A7
B7
C1
C3
D1
D2
D3
E1
E2
F2
G1
G2
G9
H1
H2
H10
J10
K1
K2
K3
K5
K7
K8
K10
K11
L4
L8
M8

2

2

1

1

C1358

0.1U_0402_16V4Z~D

1.0

of

5

4

3

2

1

VDD04VDD110VDD218VDD327VDD438VDD550VDD6

+3VLAN

@

12

LAN ANALOG
SWITCH

48

0B1

47

1B1

43

2B1

42

3B1

37

4B1

36

5B1

32

6B1

31

7B1

22

0LED1

23

1LED1

52

2LED1

46

0B2

45

1B2

41

2B2

40

3B2

35

4B2

34

5B2

30

6B2

29

7B2

25

0LED2

26

1LED2

51

2LED2

PI3L500E_TQFN56~D

55

@

SW_LAN_TX0­SW_LAN_TX0+

SW_LAN_TX1­SW_LAN_TX1+

SW_LAN_TX2­SW_LAN_TX2+

SW_LAN_TX3­SW_LAN_TX3+

LAN_LEDACT#
LINK_LED10#
LINK_LED100#

DOCK_LAN_TX0­DOCK_LAN_TX0+

DOCK_LAN_TX1­DOCK_LAN_TX1+

DOCK_LAN_TX2­DOCK_LAN_TX2+

DOCK_LAN_TX3­DOCK_LAN_TX3+

DOCK_LAN_ACTLED_YEL#
DOCK_LED_10#
DOCK_LED_100#

SW_LAN_TX0- 32
SW_LAN_TX0+ 32

SW_LAN_TX1- 32
SW_LAN_TX1+ 32

SW_LAN_TX2- 32
SW_LAN_TX2+ 32

SW_LAN_TX3- 32
SW_LAN_TX3+ 32

DOCK_LAN_TX0- 36
DOCK_LAN_TX0+ 36

DOCK_LAN_TX1- 36
DOCK_LAN_TX1+ 36

DOCK_LAN_TX2- 36
DOCK_LAN_TX2+ 36

DOCK_LAN_TX3- 36
DOCK_LAN_TX3+ 36

DOCK_LAN_ACTLED_YEL# 36
DOCK_LED_10# 36
DOCK_LED_100# 36

TO

DOCK

+3VLAN

C1395 0.1U_0402_16V4Z~D

1 2

C1398 0.1U_0402_16V4Z~D

1 2

C1399 0.1U_0402_16V4Z~D

1 2

C1400 0.1U_0402_16V4Z~D

D D

C C

1 2

R1370 49.9_0402_1%~D

1 2

R1371 49.9_0402_1%~D

1 2

R1372 49.9_0402_1%~D

1 2
1 2
1 2
1 2
1 2
1 2

Layout Notice : Place
terminatio n a s close as
ASIC as possible

The resistors need at
least 1/16W

R1373 49.9_0402_1%~D
R1374 49.9_0402_1%~D
R1375 49.9_0402_1%~D
R1376 49.9_0402_1%~D
R1377 49.9_0402_1%~D

LAN_TX0­LAN_TX0+
LAN_TX1­LAN_TX1+
LAN_TX2­LAN_TX2+
LAN_TX3­LAN_TX3+

LAN_TX0-28
LAN_TX0+28

LAN_TX1-28
LAN_TX1+28

LAN_TX2-28
LAN_TX2+28

LAN_TX3-28
LAN_TX3+28

Layout Notice : Place bead as
close PI3L500 as possible

LAN_TX0- LAN_TX0-R

L68 36NH_0603CS-360EJTS_5%_0603~D

LAN_TX0+ LAN_TX0+R

L69 36NH_0603CS-360EJTS_5%_0603~D

LAN_TX1- LAN_TX1-R

L70 36NH_0603CS-360EJTS_5%_0603~D

LAN_TX1+ LAN_TX1+R

L71 36NH_0603CS-360EJTS_5%_0603~D

LAN_TX2- LAN_TX2-R

L72 36NH_0603CS-360EJTS_5%_0603~D

LAN_TX2+ LAN_TX2+R

L73 36NH_0603CS-360EJTS_5%_0603~D

LAN_TX3- LAN_TX3-R

L74 36NH_0603CS-360EJTS_5%_0603~D

LAN_TX3+ LAN_TX3+R

L75 36NH_0603CS-360EJTS_5%_0603~D

DOCKED

DOCKED36,38

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

LAN_ACT#28
LINK_10#28
LINK_100#28

FROM NIC DOCKED

1: TO DOCK
0: TO RJ45

56

U189

2

A0

3

A1

7

A2

8

A3

11

A4

12

A5

14

A6

15

A7

17

SEL

19

LED0

20

LED1

54

LED2

5

NC

57

PAD_GND

GND01GND16GND29GND313GND416GND521GND624GND728GND833GND939GND1044GND1149GND1253GND13

@

12

12

R1380

R1379

LAN_ACT#
LINK_10#
LINK_100#

B B

LAN_LEDACT# LAN_ACTLED_YEL_R#

LINK_LED10#

LINK_LED100#

A A

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

10K_0402_5%~D

R1382

1 2

150_0402_5%~D

R1384

1 2

150_0402_5%~D

R1385

1 2

150_0402_5%~D

2

R1381

10K_0402_5%~D

10K_0402_5%~D

LED_10_GRN_R#

LED_100_ORG_R#

LAN_ACTLED_YEL_R# 32

LED_10_GRN_R# 32

LED_100_ORG_R# 32

DELL CONFIDENTIAL/PROPRIETARY

Title

Size Document Number Rev

Date: Sheet

LAN TRANSFOMER

LA-2792

1

29 70Tuesday, Fe b r u a r y 07, 2006

of

1.0

8

NOTE:
THIS PAGE SHOWS THE OZ601B CONFIGURED WITH
EXTERNAL IDSEL AND WITHOUT 12V VPP SUPPORT.

+3.3V_RUN

D D

+3.3V_RUN

1

2

C1418

C1419

0.1U_0402_16V4Z~D

4.7U_0603_6.3V4Z~D

1

2

C1424

C1425

0.1U_0402_16V4Z~D

4.7U_0603_6.3V4Z~D

NOTE: IDSEL SELECTION!

THIS DEVICE UTILIZES A "SELECTABLE IDSEL" SCHEME.
IDSEL CAN BE CONNECTED INTERNALLY TO ONE OF THREE
PCI AD LINES OR EXTERNAL IDSEL SIGNAL.

22K TO 47K PULL-UP & PULL-DOWN RESISTORS ARE
REQUIRED TO BE CONNECTED TO PINS 123 & 124 TO
SELECT ONE OF THE 4 POSSIBLE IDSEL CONNECTIONS.
THE TABLE BELOW SHOWS THE 4 POSSIBLE COMBINATIONS.

C C

CONFIGURING IDSEL TO BE INTERNALLY CONNECTED ALLOWS
FOR A FULL PARALLEL POWER MODE. IF AN EXTERNALLY
CONNECTED IDSEL IS REQUIRED THEN AN INVERTER MUST
BE CONNECTED TO VPP_PGM TO CREATE VPP_VCC.

VCC5# VPP_PGM IDSEL SELECT
(124) (123)

DOWN DOWN AD18

DOWN UP AD20

UP DOWN AD25

UP UP PIN 127

PCI_DEVSEL#21,35
PCI_FRAME#21,35,36
PCI_IRDY#21,35,36
PCI_TRDY#21,35
PCI_STOP#21,35

B B

22K TO 47K PULL-UPS MUST BE PLACED
ON INTA#, PME#, SERIRQ# & CLKRUN#.

Place closely pin 26

CLK_PCI_PCM

22_0402_5%~D

A A

22P_0402_50V8J~D

8

PCI_PAR21,35

R88

@

C81

@

1

2

1

2

PCI_PERR#21,35
PCI_REQ1#21

PCI_GNT1#21
PCI_RST#21,31,35

12

1

2

CLK_PCI_PCM6

IRQ_SERIRQ23,28,38,39

PCI_PIRQC#21

C1420

0.1U_0402_16V4Z~D

C1448

0.1U_0402_16V4Z~D

PCI_AD17

SYS_PME#35,38

CLKRUN#23,38,39

7

1

1

2

2

C1421

0.1U_0402_16V4Z~D

1

2

PCI_AD[0..31]21,35

7

R1307

100_0402_5%~D

1 2

PCI_C_BE3#21,35
PCI_C_BE2#21,35
PCI_C_BE1#21,35
PCI_C_BE0#21,35

CLK_PCI_PCM
PCI_DEVSEL#
PCI_FRAME#
PCI_IRDY#
PCI_TRDY#
PCI_STOP#
PCI_PAR

PCI_PERR#
PCI_REQ1#

PCI_GNT1#
PCI_RST#

R71 0_0402_5%~D@

CLKRUN#
IRQ_SERIRQ

PCI_PIRQC#

1 2

PCI_AD31
PCI_AD30
PCI_AD29
PCI_AD28
PCI_AD27
PCI_AD26
PCI_AD25
PCI_AD24
PCI_AD23
PCI_AD22
PCI_AD21
PCI_AD20
PCI_AD19
PCI_AD18
PCI_AD17
PCI_AD16
PCI_AD15
PCI_AD14
PCI_AD13
PCI_AD12
PCI_AD11
PCI_AD10
PCI_AD9
PCI_AD8
PCI_AD7
PCI_AD6
PCI_AD5
PCI_AD4
PCI_AD3
PCI_AD2
PCI_AD1

PCI_AD0
CBS_IDSEL
PCI_C_BE3#
PCI_C_BE2#
PCI_C_BE1#
PCI_C_BE0#

6

U193

64

CORE_VCC

77

CORE_VCC

97

CORE_VCC

115

CORE_VCC

1

PCI_VCC

20

PCI_VCC

33

PCI_VCC

4

AD31

5

AD30

6

AD29

7

AD28

8

AD27

9

AD26

10

AD25

13

AD24

14

AD23

15

AD22

16

AD21

17

AD20

18

AD19

19

AD18

21

AD17

22

AD16

28

AD15

29

AD14

30

AD13

31

AD12

34

AD11

35

AD10

36

AD9

37

AD8

38

AD7

39

AD6

40

AD5

41

AD4

42

AD3

43

AD2

44

AD1

46

AD0

127

VPP_VCC/VPPD1/IDSEL

11

C/BE3#

12

C/BE2#

49

C/BE1#

50

C/BE0#

26

PCI_CLK

27

DEVSEL#

23

FRAME#

24

IRDY#

25

TRDY#

47

STOP#

48

PAR

51

PERR#/SPKR_OUT

2

REQ#

3

GNT#

126

RST#

120

PME#/RI_OUT#

55

MF6

54

MF4

53

MF3

52

MF0

GND32GND45GND65GND96GND

6

IDSEL SELECT POWER-ON-STRAPPING
(SEE NOTE & TABLE FOR OPTIONS)

VCC5#/VCCD0#/SDATA

VCC3#/VCCD1#/SCLK

VPP_PGM/VPPD0/SLATCH

IORD#/CAD13

A23/CFRAME#

A21/CDEVSEL#

WAIT#/CSERR#

INPACK#/CREQ#

RDY/IREQ#/CINT#

A19/CBLOCK#

WP/CCLKRUN#

RESET/CRST#

BVD2/LED/CAUDIO

BVD1/STSCHG#/RI#/CSTSCHG

128

REG#CCBE3#

OZ601TN_TQFP128~D

5

D10/CAD31

D9/CAD30
D1/CAD29
D8/CAD28
D0/CAD27
A0/CAD26
A1/CAD25
A2/CAD24
A3/CAD23
A4/CAD22
A5/CAD21
A6/CAD20

A25/CAD19

A7/CAD18
A24/CAD17
A17/CAD16

IOW#/CAD15

A9/CAD14
A11/CAD12

OE#/CAD11

CE2#/CAD10

A10/CAD9

D15/CAD8

D7/CAD7

D13/CAD6

D6/CAD5

D12/CAD4

D5/CAD3

D11/CAD2

D4/CAD1
D3/CAD0

A16/CCLK

A15/CIRDY#

A22/CTRDY#
A20/CSTOP#

A13/CPAR

A14/CPERR#

WE#/CGNT#

D2/RFU
D14/RFU
A18/RFU

VS1/CVS1

VS2/CVS2
CD1#/CCD1#
CD2#/CCD2#

A12/CCBE2#

A8/CCBE1#

CE1/CCBE0#

5

4

+5V_RUN

+3.3V_RUN

12

12

R1407

R1406

33K_0402_5%~D

124
125
123

103
102
101
100
99
110
109
108
106
105
104
118
95
94
93
75
73
74
71
72
70
69
68
85
84
82
83
80
81
78
79
76

107
114
117
116
113
61
58
60
91
89
62
88
59
87
119
98
86
63
57
121
56
122
92
90

111
112
66
67

CBS_SATA
CBS_SCLK
CBS_SLATCH

CBS_CAD31
CBS_CAD30
CBS_CAD29
CBS_CAD28
CBS_CAD27
CBS_CAD26
CBS_CAD25
CBS_CAD24
CBS_CAD23
CBS_CAD22
CBS_CAD21
CBS_CAD20
CBS_CAD19
CBS_CAD18
CBS_CAD17
CBS_CAD16
CBS_CAD15
CBS_CAD14
CBS_CAD13
CBS_CAD12
CBS_CAD11
CBS_CAD10
CBS_CAD9
CBS_CAD8
CBS_CAD7
CBS_CAD6
CBS_CAD5
CBS_CAD4
CBS_CAD3
CBS_CAD2
CBS_CAD1
CBS_CAD0

R4 33_0402_5%~D

CBS_CFRAME#

CBS_CIRDY#

CBS_CTRDY#

CBS_CDEVSEL#

CBS_CSTOP#

CBS_CPAR
CBS_CPERR#
CBS_CSERR#

CBS_CREQ#
CBS_CGNT#

CBS_CINT#

CBS_CBLOCK#

CBS_CCLKRUN#

CBS_CRST#

CBS_RSVD/D2
CBS_RSVD/D14
CBS_RSVD/A18

CBS_CVS1

CBS_CVS2
CBS_CCD1#
CBS_CCD2#

CBS_CAUDIO

CBS_CSTSCHNG

CBS_CC/BE3#
CBS_CC/BE2#
CBS_CC/BE1#
CBS_CC/BE0#

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

+3.3V_RUN

33K_0402_5%~D

1

2

C1416

4.7U_0603_6.3V4Z~D

1

2

C1422

4.7U_0603_6.3V4Z~D

CBS_CCLK

+CBS_VCC +CBS_VCC

4

1

2

C1417

1

2

C1423

PCI_RST#

C1426

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

1

2

CBS_CAD0
CBS_CAD1
CBS_CAD3
CBS_CAD5
CBS_CAD7
CBS_CC/BE0#

CBS_CAD9
CBS_CAD11
CBS_CAD12

CBS_CAD14
CBS_CC/BE1#
CBS_CPAR

CBS_CPERR#
CBS_CGNT#
CBS_CINT#

CBS_CCLK
CBS_CIRDY#
CBS_CC/BE2#
CBS_CAD18
CBS_CAD20

CBS_CAD21
CBS_CAD22
CBS_CAD23
CBS_CAD24

CBS_CAD25
CBS_CAD26
CBS_CAD27

CBS_CAD29
CBS_RSVD/D2
CBS_CCLKRUN#

3

U2

19

+5V

20

+5V

21

+5V

3

+3.3V

4

+3.3V

5

+3.3V

1

DATA

2

CLK

6

LATCH

32

RESET#

18

HOST_CLK

22

SC_CLK

11

HOST_RST

12

SC_RST

9

HOST_I/O

10

SC_I/O

7

GND

OZ2522LN-A1_QFN32~D

3

AVCC
AVCC
AVCC

AVPP

BVCC

CD1#
CD2#

VS1
VS2

HOST_DN
HOST_DP

CARD_DN
CARD_DP

NC
NC

JCBUS

1

GND1

2

A_CAD0

3

A_CAD1

4

A_CAD3

5

A_CAD5

6

A_CAD7

7

A_PCI_C/BE0#

8

GND2

9

A_CAD9

10

A_CAD11

11

A_CAD12

12

GND3

13

A_CAD14

14

A_PCI_C/BE1#

15

A_CPAR

16

GND4

17

A_CPERR#

18

A_CGNT#

19

A_CINT#

20

+AVCC0

21

+AVPP0

22

A_CCLK

23

A_CIRDY

24

A_PCI_C/BE2#

25

A_CAD18

26

A_CAD20

27

GND5

28

A_CAD21

29

A_CAD22

30

A_CAD23

31

A_CAD24

32

GND6

33

A_CAD25

34

A_CAD26

35

A_CAD27

36

GND7

37

A_CAD29

38

CB_A_D2

39

A_CCLKRUN#

40

GND8

TYCO_1734648-1~D

29
30
31

28
13
14

15
16
17

24
27

23
26

8
25

2

+CBS_VCC

CBS_CCD1#
CBS_CCD2#
CBS_CVS1
CBS_CVS2

USB_HUBP1- 38

CBS_CAD15
CBS_CAD13

CB_A_D14

CB_A_A18

A_CBLOCK#

A_CSTOP#

A_CDEVSEL#

A_CTRDY#

A_CFRAME#

A_CSERR#

A_CREQ#

A_PCI_C/BE3#

A_CAUDIO

A_CSTSCHG

USB_HUBP1+ 38

41

GND9

42

A_CCD1#

43

A_CAD2

44

A_CAD4

45

A_CAD6

46
47

A_CAD8

48

GND10

49

A_CAD10

50

A_CVS1

51

A_CAD13

52

GND11

53

A_CAD15

54

A_CAD16

55
56

GND12

57
58
59
60

+AVCC1

61

+AVPP1

62
63
64

A_CAD17

65

A_CAD19

66

A_CVS2

67

GND13

68

A_CRST#

69
70
71
72

GND14

73
74
75

A_CAD28

76

GND15

77

A_CAD30

78

A_CAD31

79

A_CCD2#

80

GND16

DELL CONFIDENTIAL/PROPRIETARY

Title

Size Document Number Rev

Date: Sheet

2

CBS_CCD1#
CBS_CAD2
CBS_CAD4
CBS_CAD6
CBS_RSVD/D14
CBS_CAD8

CBS_CAD10
CBS_CVS1
CBS_CAD13

CBS_CAD15
CBS_CAD16
CBS_RSVD/A18

CBS_CBLOCK#
CBS_CSTOP#
CBS_CDEVSEL#

CBS_CTRDY#
CBS_CFRAME#
CBS_CAD17
CBS_CAD19
CBS_CVS2

CBS_CRST#
CBS_CSERR#
CBS_CREQ#
CBS_CC/BE3#

CBS_CAUDIO
CBS_CSTSCHNG
CBS_CAD28

CBS_CAD30
CBS_CAD31
CBS_CCD2#

Card Bus OZ601

LA-2792

1

1

2

C1447

0.1U_0402_16V4Z~D

30 70Tuesday, Fe b r u a r y 07, 2006

1

1.0

of

8

D D

C C

MODE1 CLOCK INPUT

LOW 48MHz

B B

HIGH 6MHz Crystal

7

6

USB SMARTCARD READER.
TYPE A (5V), B (3V), AB (5V/3V)
& USB SMARTCARDS ARE SUPPORTED.

+5V_RUN

+3.3V_RUN

12

R1597

USB_HUBP3-38
USB_HUBP3+38

PCI_RST#21,30,35

1.5K_0402_1%~D

CLK_SMC_48M6

1

C457

2

USB_HUBP3­USB_HUBP3+

PCI_RST#

1

C1433

2

4.7U_0603_6.3V4Z~D

CLK_SMC_48M

12

R1425

0.1U_0402_16V4Z~D

MD0

4.7K_0402_5%~D

U1

5

VCC5V_IN

28

VCC5V_IN

17

UPD-

16

UPD+

14

RST#

30

NC

31

NC

3

XI/48M_IN

4

XO

32

MODE0/SC_LED#

1

MODE1

2

MODE2

11

GND

13

GND

26

GND

VR_CPR6VR_CPR

OZ77C6LN-A1_QFN32~D

12

C1443

10.1

VRCPR

12

1U_0603_10V4Z~D

+3.3V_OUT

DPD-

DPD+

EGATED-

EGATED+

SC_VCC

SC_RST#

SC_CLK

SC_C4

SC_IO

SC_DET#

RF_OUT

RF_IN/RX

RF_CLK
RF_AUX

5

+3V_PWR

1

1

C1749

C1748

2

2

29

19
18

21
20

27
24

23
22
25
15

8
7
9
10

4.7U_0603_6.3V4Z~D

USB_BIO_L­USB_BIO_L+

SCCD­SCCD+

+SC_PWR

4

R122 33_0402_5%~D

1 2

R123 33_0402_5%~D

1 2

L5

@

4

4

1

1

DLW21SN900SQ2_0805~D

12

12

R1596

R1595

15K_0402_5%~D

15K_0402_5%~D

0.1U_0402_16V4Z~D

C1437

1

2

0.1U_0402_16V4Z~D

SC_RST#
SC_CLK
SC_C4

SC_IO
SC_DET#

SC_DET#

12

1

R1336

C1436

2

4.7U_0603_6.3V4Z~D

3

3

3

2

2

1

2

47P_0402_50V8J~D

C84

10K_0402_5%~D

R1420 220_0402_5%~D
R1421 33_0402_5%~D
R1423 220_0402_5%~D

R1424 330_0402_5%~D

SC_DET# 38

2

USB_BIO- 40

USB_BIO+ 40

1

2

12

12

R1416

R1417

15K_0402_5%~D

15K_0402_5%~D

47P_0402_50V8J~D

C83

1

1

C1439

2

0.1U_0402_16V4Z~D

12
12
12

12

12

C1440

2

R1419

1U_0603_10V4Z~D

+SC_PWR

47K_0402_5%~D

SCCD+

SCCD-

1

C76

2

0.1U_0402_16V4Z~D

JSC

12

GND

11

GND

10

10

9

9

8

8

7

7

6

6

5

5

4

4

3

3

2

2

1

1

MOLEX_52207-1085~D

1

Place closely pin 3

CLK_SMC_48M

12

@

R133

10_0402_5%~D

@

1

C135

4.7P_0402_50V8C~D

A A

2

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

8

7

6

5

4

3

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.
Smart Card OZ77C6

LA-2792

2

31 70Tuesday, Feb ru ar y 07, 2006

1

1.0

of

5

D D

4

3

2

1

L8 DLW21SN900SQ2_0805~D@

USBP5+23

USBP5-23

USBP6+23

USBP6-23

C C

+5V_SUS

1

C9

B B

0.1U_0402_16V4Z~D

C343

0.1U_0402_16V4Z~D

2

+5V_SUS

1

2

4

1

4

1

USB_BACK_EN#38

1

C13
10U_0805_10V4Z~D

2

USB_SIDE_EN#38

1

C342
10U_0805_10V4Z~D

2

4

1

1 2

1 2

L7 DLW21SN900SQ2_0805~D@

4

1

1 2

1 2

0_0402_5%~D

0_0402_5%~D

0_0402_5%~D

0_0402_5%~D

R29

R28

R27

R26

3

3

2

2

3

3

2

2

USB_BACK_EN#

USB_SIDE_EN#

1
2
3
4

1
2
3
4

USBP5_D+

USBP5_D-

USBP6_D+

USBP6_D-

U14

GND

OC1#

IN

OUT1

EN1#

OUT2

EN2#

OC2#

TPS2062DR_SO8~D

U17

GND

OC1#

IN

OUT1

EN1#

OUT2

EN2#

OC2#

TPS2062DR_SO8~D

USB Port

+USB_BACK_PWR

8
7
6
5

+USB_SIDE_PWR

8
7
6
5

USB_OC5#

USB_OC6#

USB_OC3#

USB_OC4#

USB_OC5# 23

USB_OC6# 23

USB_OC3# 23

USB_OC4# 23

USBP3-23
USBP3+23

USBP4-23

USBP4+23
BREATH_GREEN_LED43
BATT_GREEN_LED43
BATT_AMBER_LED43
R_BT_ACT43
R_MPCI_ACT43

INT_MIC+27

INT_MIC-27

USBP3­USBP3+

USBP4­USBP4+
BREATH_GREEN_LED
BATT_GREEN_LED
BATT_AMBER_LED
R_BT_ACT
R_MPCI_ACT
INT_MIC+
INT_MIC-

USBP3+

USBP4-

+USB_BACK_PWR

+USB_SIDE_PWR

1

C1745

2

0.1U_0402_16V4Z~D

U186

@

1

D1+

2

GND

3

D2-

IP4220CZ6_SO6~D

D2+

VCC

D1-

JIO

2

112

4

334

6

556

8

778

10

9910

11
13

27
29

31
32
33

+USB_SIDE_PWR +USB_BACK_PWR

USBP4+

4
5

USBP3-

6

12

12

11

14

14

13

16

151516

18

171718

20

191920

22

212122

24

232324

26

252526

28

27

28

30

29

30

34

GND

GND

35

GND

GND

36

GND

GND

TYCO_3-1775014-0~D

LAN_ACTLED_YEL_R#
SW_LAN_TX0+

SW_LAN_TX0­SW_LAN_TX1+
SW_LAN_TX1-

SW_LAN_TX2+
SW_LAN_TX2­SW_LAN_TX3+
SW_LAN_TX3-

LED_10_GRN_R#
LED_100_ORG_R#
R_SATA_ACT

Place ESD diodes as close as USB connector.

1

+

C18

2

150U_D2_6.3VM~D

1

C19

2

USBP6_D-

0.1U_0402_16V4Z~D

C292

0.1U_0402_16V4Z~D

USBP6_D+

USBP5_D­USBP5_D+

1

2

USBP5+

USBP6-

LAN_ACTLED_YEL_R# 29

+3VLAN

+2.5VLAN

LED_10_GRN_R# 29
LED_100_ORG_R# 29

U187

@

1

D1+

2

GND

3

D2-

IP4220CZ6_SO6~D

JUSB1

1

A_VCC

2

A_D-

3

A_D+

4

A_GND

5

B_VCC

6

B_D-

7

B_D+

8

B_GND

9

G1

10

G2

11

G3

12

G4

FOX_UB9112C-SB201-4F~D

SW_LAN_TX0+ 29
SW_LAN_TX0- 29
SW_LAN_TX1+ 29
SW_LAN_TX1- 29

SW_LAN_TX2+ 29
SW_LAN_TX2- 29
SW_LAN_TX3+ 29
SW_LAN_TX3- 29

R_SATA_ACT 43

4

D2+

5

VCC

6

D1-

USBP6+

USBP5-

A A

Rear USB Ports

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.
USB 2.0 Port

LA-2792

32 70Tuesday, Feb ru ar y 07, 2006

1

1.0

of

5

D D

C C

4

ICH_RST_MDC#22

+5V_SUS

MDC_RST_DIS#38

12

R1441
10K_0402_5%~D

3

@

0_0402_5%~D

1 2

1 3

D

R1442

S

Q64
BSS138W-7-F_SOT323~D

G

2

ICH_RST_MDC_R#

12

R1443
100K_0402_5%~D

2

1

New MDC connector.

1

GND

3

IAC_SDATA0

5

GND

7

IAC_SYNC

9

IAC_SDATAIN

11 12

IAC_RESET#

IAC_BITCLK

RES
RES

3.3V
GND
GND

2
4
6
8
10

B B

JMDC

1

ICH_SDOUT_MDC22

ICH_AC_SDIN122

A A

1 2

33_0402_5%~D

ICH_SYNC_MDC22

R91

ICH_SDOUT_MDC
ICH_SYNC_MDC

MDC_SDIN
ICH_RST_MDC_R#

GND1

3

IAC_SDATA_OUT

5

GND2

7

IAC_SYNC

9

IAC_SDATA_IN

11

IAC_RESET#

GND13GND14GND15GND16GND17GND

2

RES0

4

RES1

6

3.3V

8

GND3

10

GND4

12

IAC_BITCLK

TYCO_1-1775149-2~D

18

Connector for MDC Rev1.5

W=20 mil

MDC_AC_BITCLK

+3.3V_SUS

C403

4.7U_0603_6.3V4Z~D

ICH_SDOUT_MDC

MDC_AC_BITCLK22

1

1

C89

2

2

0.1U_0402_16V4Z~D

MDC_AC_BITCLK

C396

@

10P_0402_50V8J~D

R406

R98

1 2

1 2

10_0402_5%~D@

10_0402_5%~D@

MDC_AC_BITCLK_TERM

ICH_AC_SDOUT_MDCTERM

1

1

C86
10P_0402_50V8J~D

2

2

@

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.
BT PORT and MDC

LA-2792

33 70Tuesday, Feb ru ar y 07, 2006

1

1.0

of

5

D D

USB_HUBP2-38

USB_HUBP2+38

JCLIP2

1

GND1

2

GND2

3

GND3

4

GND4

TYCO_1775837-1~D

C C

L101 DLW21SN900SQ2_0805~D

1

4

1

4

0_0402_5%~D

1 2

0_0402_5%~D

1 2

@

R1577

R1578

2

2

3

3

Mini-Card Latch

Mini Card

Wire less LAN

+3.3V_RUN

JMINI2

PCIE_WAKE#28,38
COEX2_WLAN_ACTIVE40
COEX1_BT_ACTIVE40

MINI2CLK_REQ#6
CLK_PCIE_MINI2#6

CLK_PCIE_MINI26

PCIE_IRX_WLANTX_N223
PCIE_IRX_WLANTX_P223

B B

A A

PCIE_ITX_WLANRX_N2_C23
PCIE_ITX_WLANRX_P2_C23

1

C159

2

0.1U_0402_16V4Z~D

R1609 0_0402_5%~D
R1610 0_0402_5%~D

PCIE_IRX_WLANTX_N2
PCIE_IRX_WLANTX_P2

PCIE_ITX_WLANRX_N2_C
PCIE_ITX_WLANRX_P2_C

+1.5V_RUN+3VLAN

1

C463

C117

2

0.047U_0402_16V4Z~D

5

1 2
1 2

1

2

0.047U_0402_16V4Z~D

+3.3V_RUN

1

2

1

1

3

3

5

5

7

7

9

9

11

11

13

13

15

15

17

17

19

19

21

21

23

23

25

25

27

27

29

29

31

31

33

33

35

35

37

37

39

39

41

41

43

43

45

45

47

47

49

49

51

51

53

GND1

TYCO_1775838-1~D

C168

0.047U_0402_16V4Z~D

2
4
6

8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

GND2

1

C464

0.047U_0402_16V4Z~D

2

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

54

+3.3V_RUN

4

USB_HUBP2_D-

USB_HUBP2_D+

+1.5V_RUN

WLAN_RADIO_DIS#_R
PLTRST#

USBP0­USBP0+

LED_WLAN_OUT#

1 2

R1603 0_0402_5%~D@

1

C170

0.1U_0402_16V4Z~D

2

4

R24

1 2

0_0402_5%~D

+3VLAN

@

21

D2003
RB751S40T1_SOD523-2~D

PLTRST# 10,21,23,28

ICH_SMBCLK 6,23,28
ICH_SMBDATA 6,23,28

USBP0- 23
USBP0+ 23

LED_WLAN_OUT# 43
BT_ACTIVE 40,43

1

C77

0.1U_0402_16V4Z~D

2

WLAN_RADIO_DIS#_R

1

C1790

4.7U_0603_6.3V4Z~D

2

3

2

Mini Card

Wire less WAN

+3.3V_RUN+3.3V_RUN

2

2

4

4

6

6

8

8

10

10

12

12

14

14

16

16

18

18

20

20

22

22

24

24

26

26

28

28

30

30

32

32

34

34

36

36

38

38

40

40

42

42

44

44

46

46

48

48

50

50

52

52

54

GND2

JSIM

1

VCC

2

RST

3

CLK

7

NC

SUYIN_254020MA006G502ZL~D

5

1

C136
33P_0402_50V8J~D

2

2

C1747

1

2

1U_0603_10V4Z~D

1

2

JMINI1

1

1

3

3

5

5

7

7

9

9

11

11

13

13

15

15

17

17

19

19

21

21

23

23

25

25

27

27

29

29

31

31

33

33

35

35

37

37

39

39

41

41

43

43

45

45

47

47

49

49

51

51

53

GND1

TYCO_1775838-1~D

+SIM_PWR

1

C55

2

33P_0402_50V8J~D

Primary Power Aux P ower

Peak Normal Normal

1000 750

330

500

PCIE_IRX_WANTX_N1
PCIE_IRX_WANTX_P1

PCIE_ITX_WANRX_N1_C
PCIE_ITX_WANRX_P1_C

+3.3V_RUN

1

C166

0.047U_0402_16V4Z~D

2

PCIE_WAKE#

MINI1CLK_REQ#
CLK_PCIE_MINI1#

CLK_PCIE_MINI1

PWR
Rail

+3.3V

+3.3Vaux

+1.5V

UIM_CLK

C56

33P_0402_50V8J~D

1

C440

0.047U_0402_16V4Z~D

2

Voltage
Tolerance

+-9%

+-9%

+-5%

PCIE_WAKE#28,38

MINI1CLK_REQ#6
CLK_PCIE_MINI1#6

CLK_PCIE_MINI16

8051_TX39

PCIE_IRX_WANTX_N123
PCIE_IRX_WANTX_P123

PCIE_ITX_WANRX_N1_C23
PCIE_ITX_WANRX_P1_C23

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

+1.5V_RUN

UIM_DATA
UIM_CLK
UIM_RESET
UIM_VPP

WWAN_RADIO_DIS#
PLTRST#

+3VLAN

ICH_SMBCLK
ICH_SMBDATA

USB_HUBP2_D­USB_HUBP2_D+

4

GND

5

VPP

6

I/O

8

NC

231

D5
NNCD5.6LG~D

4

1

C131
22U_0805_6.3VAM~D

2

250 (Wake enable)

250

5 (Not wake enable)

375

NA

1

JCLIP1

1

GND1

2

GND2

3

GND3

4

GND4

TYCO_1775837-1~D

Mini-Card Latch

+SIM_PWR

WWAN_RADIO_DIS# 23
PLTRST# 10,21,23,28

ICH_SMBCLK 6,23,28
ICH_SMBDATA 6,23,28

8051_RX 39WLAN_RADIO_DIS#38

UIM_VPPUIM_RESET
UIM_DATA

1

1

C60

C57

2

2

@

33P_0402_50V8J~D

33P_0402_50V8J~D

+1.5V_RUN+3VLAN

1

1

+

C143

2

330U_V_6.3VM_R25~D

1

2

C1785

0.1U_0402_16V4Z~D

1

C1787

2

2

C1786

@

@

0.047U_0402_16V4Z~D

0.047U_0402_16V4Z~D

DELL CONFIDENTIAL/PROPRIETARY

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

Mini Card

LA-2792

34 70Tuesday, Fe b r u a r y 07, 2006

1

of

1.0

5

4

3

2

1

+5V_RUN

D26

2 1

RB751S40T1_SOD523-2~D

D D

C C

QUIETE#

PCI_AD31
PCI_AD30
PCI_AD29
PCI_AD28
PCI_AD27
PCI_AD26
PCI_AD25
PCI_AD24

PCI_AD23
PCI_AD22
PCI_AD21
PCI_AD20
PCI_AD19
PCI_AD18
PCI_AD17
PCI_AD16

PCI_AD15
PCI_AD14
PCI_AD13
PCI_AD12
PCI_AD11
PCI_AD10
PCI_AD8
PCI_AD9

PCI_AD7
PCI_AD6
PCI_AD5
PCI_AD4
PCI_AD3
PCI_AD2
PCI_AD1
PCI_AD0

+VCC_QBUFD

D27

2 1

RB751S40T1_SOD523-2~D

U194

1

NC1

2

A1

3

A2

4

A3

5

A4

6

A5

7

A6

8

A7

9

A8

10

GND1

11

NC2

12

A9

13

A10

14

A11

15

A12

16

A13

17

A14

18

A15

19

A16

20

GND2

21

NC3

22

A17

23

A18

24

A19

25

A20

26

A21

27

A22

28

A23

29

A24

30

GND3

31

NC4

32

A25

33

A26

34

A27

35

A28

36

A29

37

A30

38

A31

39

A32

40

GND4

PI5C34X2245BE_BQSOP80~D

VCC4

OE1#

VCC3

OE2#

VCC2

OE3#

VCC1

OE4#

+VCC_QBUF

1

2

C1822

0.1U_0402_16V4Z~D

C1325

80
79
78

B1

77

B2

76

B3

75

B4

74

B5

73

B6

72

B7

71

B8

70
69
68

B9

67

B10

66

B11

65

B12

64

B13

63

B14

62

B15

61

B16

60
59
58

B17

57

B18

56

B19

55

B20

54

B21

53

B22

52

B23

51

B24

50
49
48

B25

47

B26

46

B27

45

B28

44

B29

43

B30

42

B31

41

B32

0.1U_0402_16V4Z~D

1 2

DOCK_AD31
DOCK_AD30
DOCK_AD29
DOCK_AD28
DOCK_AD27
DOCK_AD26
DOCK_AD25
DOCK_AD24

DOCK_AD23
DOCK_AD22
DOCK_AD21
DOCK_AD20
DOCK_AD19
DOCK_AD18
DOCK_AD17
DOCK_AD16

DOCK_AD15
DOCK_AD14
DOCK_AD13
DOCK_AD12
DOCK_AD11
DOCK_AD10
DOCK_AD8
DOCK_AD9

DOCK_AD7
DOCK_AD6
DOCK_AD5
DOCK_AD4
DOCK_AD3
DOCK_AD2
DOCK_AD1
DOCK_AD0

12

1

2

C1823

R1332
10K_0402_5%~D

0.47U_0402_16V4Z~D

DOCK_AD[0..31] 36

PCI_AD[0..31]21,30

C1824

0.47U_0402_16V4Z~D

1 2

C1328

B B

A A

PCI_PIRQA#21

PCI_GNT0#21,36

PCI_RST#21,30,31

SYS_PME#30,38
PCI_C_BE3#21,30
PCI_C_BE2#21,30
PCI_C_BE1#21,30
PCI_C_BE0#21,30
PCI_IRDY#21,30,36
PCI_FRAME#21,30,36

PCI_TRDY#21,30
PCI_STOP#21,30
PCI_PLOCK#21
PCI_DEVSEL#21,30
PCI_PERR#21,30
PCI_SERR#21
PCI_PAR21,30

PCI_PIRQA#
PCI_GNT0#
PCI_RST#
SYS_PME#
PCI_C_BE3#
PCI_C_BE2#
PCI_C_BE1#
PCI_C_BE0#
PCI_IRDY#
PCI_FRAME#

PCI_TRDY#
PCI_STOP#
PCI_PLOCK#
PCI_DEVSEL#
PCI_PERR#
PCI_SERR#
PCI_PAR
PCI_AD24

QUIETE#

U184

47

OE1

VCC1

OE235VCC2

2

A0

3
4
5
6
7
8

9
10
11

14
15
16
17
18
19
20
21
22
23

1
13

PI5C162861BE_BQSOP48~D

B0

A1

B1

A2

B2

A3

B3

A4

B4

A5

B5

A6

B6

A7

B7

A8

B8

A9

B9

A10

B10

A11

B11

A12

B12

A13

B13

A14

B14

A15

B15

A16

B16

A17

B17

A18

B18

A19

B19

GND1

NC1

GND2

NC2

0.1U_0402_16V4Z~D

36
48

46
45
44
43
42
41
40
39
38
37

34
33
32
31
30
29
28
27
26
25

12
24

1 2

DOCK_PIRQA#
DOCK_GNT0#
DOCK_PCIRST#
DOCK_SPME#
DOCK_C_BE3#
DOCK_C_BE2#
DOCK_C_BE1#
DOCK_C_BE0#
DOCK_IRDY#
DOCK_FRAME#

DOCK_TRDY#
DOCK_STOP#
DOCK_LOCK#
DOCK_DEVSEL#
DOCK_PERR#
DOCK_SERR#
DOCK_PAR
DOCK_PCI_IDSEL

DOCK_PIRQA# 36
DOCK_GNT0# 36
DOCK_PCIRST# 36
DOCK_SPME# 36
DOCK_C_BE3# 36
DOCK_C_BE2# 36
DOCK_C_BE1# 36
DOCK_C_BE0# 36
DOCK_IRDY# 36
DOCK_FRAME# 36

DOCK_TRDY# 36
DOCK_STOP# 36
DOCK_LOCK# 36
DOCK_DEVSEL# 36
DOCK_PERR# 36
DOCK_SERR# 36
DOCK_PAR 36
DOCK_PCI_IDSEL 36

1 2

DOCK_PCI_EN#36
QBUFEN#38

DOCK_PCI_EN#
QBUFEN#

R1335
100K_0402_5%~D

1
2

+3.3V_RUN

5

U185

P

INA
INB

G

SN74AHC1G32DCKR_SC70-5~D

3

QUIETE#

4

O

1

C1329

0.1U_0402_16V4Z~D

2

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

DOCKING BUFFER

Size Document Number Rev

Date: Sheet

LA-2792

35 70Tuesday, Fe b r u a r y 07, 2006

1

of

1.0

5

4

3

2

1

JDOCKA

1

S1

2

S2

DVI_CLK-53

DVI_CLK+53

DVI_TX4-

D D

PS_ID_IN44

CLK_DOCKPCI_33M6

DOCK_PIRQA#35

DOCK_SMB_CLK39

DOCK_SMB_DAT39

C C

B B

A A

CLK_DOCK39
DAT_DOCK39

CLK_DOCKPCI_33M

12

@

R1334
33_0402_5%~D

1

@

C1327
22P_0402_50V8J~D

2

DVI_TX4+

DVI_TX3+
DVI_TX3-

DVI_TX5+
DVI_TX5-

DVI_TX2+53

DVI_TX2-53

DVI_TX1+53

DVI_TX1-53

DVI_TX0+53

DVI_TX0-53

DOCK_AD31

PCI_GNT0#21,35

TV_C52

TV_Y52

TV_CVBS52

VGA_RED20,52

VGA_GRN20,52

VGA_BLU20,52

5

3
4
5
6
7
8

9
10
11
12
13

15
17

18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43

45
47

48
49
50
51
52
53
54
55

TYCO_2-1612415-1~D

PCI_GNT0#

PCI_IRDY#21,30,35

PCI_FRAME#21,30,35

S3
S4
S5
S6
S7
S8
S9
S10
S11
S12
S13

S15
S17

S18
S19
S20
S21
S22
S23
S24
S25
S26
S27
S28
S29
S30
S31
S32
S33
S34
S35
S36
S37
S38
S39
S40
S41
S42
S43

S45
S47

S48
S49
S50
S51
S52
S53
S54
S55

69

S69

70

S70

71

S71

72

S72

73

S73

74

S74

75

S75

76

S76

77

S77

78

S78

79

S79

80

S80

81

S81

82

S82

83

S83

84

S84

85

S85

86

S86

87

S87

88

S88

89

S89

90

S90

91

S91

92

S92

93

S93

94

S94

95

S95

96

S96

97

S97

98

S98

99

S99

100

S100

101

S101

102

S102

103

S103

104

S104

105

S105

106

S106

107

S107

108

S108

109

S109

110

S110

111

S111

112

S112

113

S113

114

S114

115

S115

116

S116

117

S117

118

S118

119

S119

120

S120

121

S121

122

S122

125

S125

126

S126

127

S127

128

S128

136

M136

+3.3V_RUN

1

C1820

0.1U_0402_16V4Z~D

2

1

5

P

NC

4

A2Y

G

U177

NC7SZ04P5X_NL_SC70-5~D

3

PCI_IRDY#
PCI_FRAME#

TV_C

TV_Y

TV_CVBS

VGA_RED

VGA_GRN

VGA_BLU

VGA_RED

DOCK_AD8
DOCK_C_BE0#

DOCK_AD14
DOCK_AD15

DOCK_AD19
DOCK_AD20

DOCK_AD27
DOCK_AD28
DOCK_AD30

USBP7­USBP7+

+3.3V_RUN

5

1

IN1

2

IN2

3

D_SERIRQ 38
DOCK_PCI_IDSEL 35

D_DLRQ1# 38 D_LAD0 38
D_LFRAME# 38

DVI_SCLK 52
DVI_SDATA 52
DVI_DETECT 52

DOCK_C_BE0# 35

DOCK_DEVSEL# 35
DOCK_IRDY# 35

DOCK_GNT0# 35
USBP7- 23

USBP7+ 23

DOCK_SMB_INT# 39

CLK_KBD 39
DAT_KBD 39

+2.5VLAN

C1297

0.01U_0402_16V7K~D

1 2

C1299

0.01U_0402_16V7K~D

1 2

DOCK_LAN_TX3- 29
DOCK_LAN_TX3+ 29
DOCK_LAN_TX2- 29
DOCK_LAN_TX2+ 29

DOCK_RING

D_LAD138
D_LAD238
D_LAD338

DOCK_PAR35
DOCK_SERR#35
DOCK_LOCK#35

DOCK_FRAME#35

DOCK_C_BE2#35

DOCK_SPME#35

DOCK_PCI_EN#35

SPDIF_DOCK26

DOCK_LED_10#29
DOCK_LED_100#29

C1298

0.01U_0402_16V7K~D

12

C1300

0.01U_0402_16V7K~D

12

DOCK_LAN_TX1-29
DOCK_LAN_TX1+29
DOCK_LAN_TX0-29
DOCK_LAN_TX0+29

PLACE TERMINATIONS CLOSE TO DOCK CONNECTOR

+3.3V_RUN

1

C1818

0.1U_0402_16V4Z~D

2

Z3305

C1819

1 2

0.1U_0402_16V4Z~D

U179

P

Z3306

4

O

G

74AHC1G08GW_SOT353-5~D

DOCK_RING
DOCK_TIP

4

5

1

P

IN1

2

IN2

G

3

U178

DOCK_OWNS_PCI

4

O

74AHC1G08GW_SOT353-5~D

JWIRE

1

1

2

2

3

3

4

4

MOLEX_53398-0471~D

DOCK_DET# DOCK_DET#
VGA_GRN

VGA_BLU
D_LAD1

D_LAD2
D_LAD3

DOCK_AD1
DOCK_AD0

DOCK_AD3
DOCK_AD4
DOCK_AD7

DOCK_AD9
DOCK_AD10
DOCK_AD11

DOCK_C_BE2#
DOCK_AD16

DOCK_AD22
DOCK_AD23
DOCK_AD24

DOCK_AD29

TV_C

SPDIF_DOCK
DOCK_LED_10#

DOCK_LED_100#

DOCK_OWNS_PCI

DOCK_TIP

+5V_ALW

R1324
100K_0402_5%~D

1 2

DOCK_DET#

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

DOCK_PWR_EN38

JDOCKB

137

S137

138

S138

139

S139

140

S140

141

S141

142

S142

143

S143

144

S144

145

S145

146

S146

147

S147

148

S148

149

S149

150

S150

151

S151

152

S152

153

S153

154

S154

155

S155

156

S156

157

S157

158

S158

159

S159

160

S160

161

S161

162

S162

163

S163

164

S164

165

S165

166

S166

167

S167

168

S168

169

S169

170

S170

171

S171

172

S172

173

S173

174

S174

175

S175

176

S176

177

S177

178

S178

179

S179

180

S180

181

S181

182

S182

183

S183

184

S184

185

S185

186

S186

187

S187

188

S188

189

S189

190

S190

193

S193

194

S194

195

S195

196

S196

204

M204

TYCO_2-1612415-1~D

2

3

205

S205

206

S206

207

S207

208

S208

209

S209

210

S210

211

S211

212

S212

213

S213

214

S214

215

S215

216

S216

217

S217

218

S218

220

S220

222

S222

223

S223

224

S224

225

S225

226

S226

227

S227

228

S228

229

S229

230

S230

231

S231

232

S232

233

S233

234

S234

235

S235

236

S236

237

S237

238

S238

239

S239

240

S240

241

S241

242

S242

243

S243

244

S244

245

S245

246

S246

247

S247

248

S248

250

S250

252

S252

253

S253

254

S254

255

S255

256

S256

257

S257

258

S258

259

S259

+3.3V_ALW

R1322
100K_0402_5%~D

1 2

13

Q60
DDTC144EUA-7-F_SOT323~D

DOCK_PWR_EN

HSYNC_R
VSYNC_R

D_LAD0
DOCK_SIO_ALERT#

DOCK_AD2
DOCK_AD5
DOCK_AD6

DOCK_AD12
DOCK_AD13
DOCK_C_BE1#

DOCK_PERR#
DOCK_STOP#
DOCK_TRDY#

DOCK_AD17
DOCK_AD18
DOCK_AD21

DOCK_C_BE3#
DOCK_AD25
DOCK_AD26

PCI_REQ0#
DOCK_PCIRST#

TV_CVBS
TV_Y

DOCK_LAN_ACTLED_YEL#
R_PIDEACT

+PWR_SRC

0.1U_0603_50V4Z~D

C1301

2
1

C1817

12

0.1U_0402_16V4Z~D

CLK_DDC2 20,52

HSYNC_R 20
VSYNC_R 20

DOCK_SIO_ALERT# 38

DOCK_PERR# 35
DOCK_STOP# 35
DOCK_TRDY# 35

PCI_REQ0# 21

DOCK_PCIRST# 35

R_PIDEACT 43

2

1

2

3

@

SM05TCT_SOT23-3~D

1

U180

3

74AHC1G08GW_SOT353-5~D

G

IN2

4

O

IN1

P

5

+3.3V_SUS

1 2

R1326

0_0402_5%~D@

DAT_DDC2 20,52

D_CLKRUN# 38

DOCK_C_BE1# 35

DOCK_C_BE3# 35

DOCK_LAN_ACTLED_YEL# 29

R1321
100K_0402_5%~D

1 2

G_DOC_PWRSRC

DOCKED 29,38

D25

Z3308

1 2

R1325

100K_0402_5%~D

2

+DOCK_PW R_SRC

2

C1296

1

0.1U_0603_50V4Z~D

Q59

FDS4435_NL_SO8~D

8
7

1

6

2

5

3

4

12

R1323
100K_0402_5%~D

Z3307

13

D

Q61

2

2N7002W-7-F_SOT323~D

G

S

DOCK_AD0
DOCK_AD1
DOCK_AD2
DOCK_AD3
DOCK_AD4
DOCK_AD5
DOCK_AD6
DOCK_AD7
DOCK_AD8
DOCK_AD9
DOCK_AD10
DOCK_AD11
DOCK_AD12
DOCK_AD13
DOCK_AD14
DOCK_AD15
DOCK_AD16
DOCK_AD17
DOCK_AD18
DOCK_AD19
DOCK_AD20
DOCK_AD21
DOCK_AD22
DOCK_AD23
DOCK_AD24
DOCK_AD25
DOCK_AD26
DOCK_AD27
DOCK_AD28
DOCK_AD29
DOCK_AD30
DOCK_AD31

JDOCKC

P1

P1

P2

P2

P3

P3

P4

P4

MH1

MH1

MH5

SHLD1

SHLD3

SHLD2

SHLD4

SHLD5

SHLD7

SHLD6

SHLD8

MH13
MH15

TYCO_2-1612415-1~D

+DOCK_PW R_SRC

C1821
1000P_0402_50V7K~D

DELL CONFIDENTIAL/PROPRIETARY

Title

DOCKING CONN.

Size Document Number Rev

Date: Sheet

MH10

MH13
MH15

1

2

MH6
MH9

MH14
MH16

MH2

P5
P6
P7
P8

TV_C
TV_CVBS
TV_Y

DOCK_DC_IN

P5
P6
P7
P8

MH2
MH7
MH8
MH11
MH12

MH14
MH16

R1790 75_0402_1%
R1791 75_0402_1%
R1792 75_0402_1%

DOCK_AD[0..31] 35

NB

PWR_SRC

LA-2792

2

C291

1

1 2
1 2
1 2

1

0.1U_0603_50V4Z~D

DOCK_DC_IN 44

1

C1827

2

1000P_0402_50V7K~D

no power dock

self powe r dock

36 70Tuesday, Fe b r u a r y 07, 2006

1.0

of

5

+3.3V_SUS

4

3

2

1

26

VCC

INVALID#

1

C1254

0.1U_0402_16V4Z~D

2

27

V+

3

V-

9

T1OUT

10

T2OUT

11

T3OUT

4

R1IN

5

R2IN

6

R3IN

7

R4IN

8

R5IN

21
25

GND

3243V+
3243V-

TXD0#
RTS0
DTR0
DCD0
RI0
RXD0#
CTS0
DSR0

C1255

0.47U_0402_16V4Z~D

1 2

C1257

0.47U_0402_16V4Z~D

1 2

DCD0
DSR0
RXD0#
RTS0
TXD0#
CTS0
DTR0
RI0

JSIO

1

DCD0

6

DSR0

2

RXD0#

7

RTS0F

3

TXD0F#

8

CTS0

4

DTR0F

9

RI0

5

GND0

10

GND1

11

GND2

1

1

1

2

@

1

1

C238

C256

2

2

@

@

270P_0402_50V7K~D

270P_0402_50V7K~D

1

C258

C257

2

2

@

@

270P_0402_50V7K~D

270P_0402_50V7K~D

1

1

C259

270P_0402_50V7K~D

C262

C260

2

2

2

@

@

270P_0402_50V7K~D

270P_0402_50V7K~D

SUYIN_070921MR009S203BR~D

C272

@

270P_0402_50V7K~D

D D

C1256

0.1U_0402_16V4Z~D

C1258

0.47U_0402_16V4Z~D

1 2

C C

1 2

TXD038
RTS0#38
DTR0#38
DCD0#38

RI0#38
RXD038
CTS0#38
DSR0#38

+3.3V_SUS

RUN_ON19,39,41,42,46,47,48,58

3243C1+

3243C1­3243C2+

3243C2-

TXD0

RTS0#
DTR0#
DCD0#
RI0#
RXD0
CTS0#
DSR0#

U173

28

C1+

24

C1-

1

C2+

2

C2-

14

T1IN

13

T2IN

12

T3IN

19

R1OUT

18

R2OUT

17

R3OUT

16

R4OUT

15

R5OUT

20

R2OUTB

23

FORCEON

22

FORCEOFF#

MAX3243ECUI+T_TSSOP28~D

FIR

R1287

47_0805_5%~D

IRVCC

+3.3V_RUN

R1289

0_0402_5%~D

D_IRMODE38

B B

1 2

SD_MODE

12

R1290

10K_0402_5%~D

IRTX38

12

U175

6

VCC

5
2
3

TFDU6102-TR3_8P~D

2

C1260

C1261

1

0.1U_0402_16V4Z~D

1

2

4.7U_0603_6.3V4Z~D

IRED_ANODE
SD_MODE
IRED_CATHODE
TXD

RXD

MODE

GND

1
4
7
8

+3.3V_RUN

IRRX 38

12

1

R1291

10K_0402_5%~D

C1259

2

4.7U_0603_6.3V4Z~D

A A

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

Serial & FIR

LA-2792

37 70Tuesday, Fe b r u a r y 07, 2006

1

1.0

of

5

4

+3.3V_ALW

3

2

1

+3.3V_ALW

1 2

R1620 10K_0402_5%~D

1 2

D D

+3.3V_RUN

C C

Place closely pin 64

22P_0402_50V8J~D

B B

A A

R1361 10K_0402_5%~D

1 2

R1363 10K_0402_5%~D

1 2

R1369 10K_0402_5%~D

1 2

R34 100K_0402_5%~D

1 2

R87 100K_0402_5%~D@

CLK_SIO_14M

12

R135

22_0402_5%~D

@

1

C145

2

@

R94

R405

1 2

10K_0402_5%~D

@

BID0
BID1
BID2
BID3

IMVP6_PROCHOT#

DOCK_HP_MUTE#

10K_0402_5%~D

R95

R404

1 2

1 2

10K_0402_5%~D

10K_0402_5%~D

10K_0402_5%~D

@

5

DOCK_SIO_ALERT#

PCIE_WAKE#

SBAT_ALARM#
PBAT_ALARM#

+3.3V_SUS

R1171

RI0#37

LOM_CABLE_DETECT28

1 2

R419 10K_0402_5%~D@
R107 10K_0402_5%~D
R108 10K_0402_5%~D @
R418 10K_0402_5%~D

SNIFFER_WIRELESS_ON/OFF#43

12

+3.3V_ALW

1 2
1 2
1 2
1 2

+3.3V_ALW

R1362 10K_0402_5%~D

PCIE_WAKE#28,34
SYS_PME#30,35
DOCK_SIO_ALERT#36

PBAT_PRES#45
SBAT_PRES#45,51

CHG_PBATT51
CHG_SBATT51

SBAT_LOW51
DOCKED29,36

QBUFEN#35
DOCK_PWR_EN36

BC_INT39

BC_DAT39
BC_CLK39

DCD0#37

MDC_RST_DIS#33
ADAPT_OC50

NB_MUTE27

R55 0_0402_5%~D@

SPDIF_SHDN26

IMVP6_PROCHOT#49

5V_CAL_SIO#18

5V_CAL_SIO2#18
DOCK_HP_MUTE#26

HP_NB_SENSE26,27

SBAT_ALARM#45
PBAT_ALARM#45

LAN_TPM_EN#28
LAN_LOW_PWR28
AUDIO_AVDD_ON26

BEEP26

BAY_MODPRES#25
SC_DET#31

ICH_PCIE_W AKE#23

ICH_PME#21

THERMTRIP_SIO18

FPBACK_EN19

CPU_PROCHOT#7

HDDC_EN#41
MODC_EN#41

USB_SIDE_EN#32
USB_BACK_EN#32

1 2

RXD037

TXD037

RTS0#37

DSR0#37

CTS0#37

DTR0#37

IRRX37

D_IRMODE37

12

IRTX37

SYS_PME#

PCIE_WAKE#
SYS_PME#
DOCK_SIO_ALERT#
PBAT_PRES#
SBAT_PRES#
CHG_PBATT
CHG_SBATT
SBAT_LOW

DOCKED
QBUFEN#
DOCK_PWR_EN

SNIFFER_WIRELESS_ON/OFF#

BC_INT
BC_DAT
BC_CLK

RXD0
TXD0
RTS0#
DSR0#
CTS0#
DTR0#
RI0#
DCD0#

MDC_RST_DIS#
ADAPT_OC

NB_MUTE

SPDIF_SHDN
IMVP6_PROCHOT#
5V_CAL_SIO#

DOCK_HP_MUTE#

HP_NB_SENSE
SBAT_ALARM#

PBAT_ALARM#
LAN_TPM_EN#

LAN_LOW_PWR
AUDIO_AVDD_ON
BEEP

BAY_MODPRES#
SC_DET#

ICH_PCIE_W AKE#
ICH_PME#
THERMTRIP_SIO

FPBACK_EN
CPU_PROCHOT#

HDDC_EN#
MODC_EN#

BID3
BID2
BID1
BID0

IRTX
IRRX

D_IRMODE
USB_SIDE_EN#
USB_BACK_EN#

BID2 BID1

0

0

0

0

0

0

00

4

34

57

85

U215

97

GPIOA[0]

98

GPIOA[1]

99

GPIOA[2]

100

GPIOA[3]

101

GPIOA[4]

102

GPIOA[5]

103

GPIOA[6]

104

GPIOA[7]

24

GPIOH[0]

25

GPIOH[1]

26

GPIOH[4]

27

GPIOH[5]

58

BC_INT#

59

BC_DAT

60

BC_CLK

1

GPIOE[0]/RXD

2

GPIOE[1]/TXD

3

GPIOE[2]/RTS#

4

GPIOE[3]/DSR#

5

GPIOE[4]/CTS#

84

GPIOE[5]/DTR#

83

GPIOE[6]/RI#

6

GPIOE[7]/DCD#

65

GPIOB[0]/INIT#

66

GPIOB[1]/SLCTIN#

67

GPIOC[2]/SCLT

68

GPIOC[3]/PE

69

GPIOC[4]/BUSY

70

GPIOC[5]/ACK#

71

GPIOC[6]/ERROR#

73

GPIOC[7]/ALF#

74

GPIOD[0]/STROBE#

75

GPIOC[1]/PD7

76

GPIOC[0]/PD6

77

GPIOB[7]/PD5

78

GPIOB[6]/PD4

79

GPIOB[5]/PD3

80

GPIOB[4]/PD2

81

GPIOB[3]/PD1

82

GPIOB[2]/PD0

61

GPIOD[1]

62

GPIOD[2]

63

GPIOD[3]/VBUS_DET

28

GPIOD[4]/OCS1_N

29

GPIOD[5]/OCS2_N

30

GPIOD[6]/OCS3_N

31

GPIOD[7]/OCS4_N

32

GPIOH[6]

33

GPIOH[7]

88

GPIOG[0]

89

GPIOG[1]

90

GPIOG[2]

91

GPIOG[3]

92

GPIOG[4]

93

GPIOG[5]

94

GPIOG[6]

95

GPIOG[7]

106

SYSOPT1/GPIOH[2]

107

SYSOPT0/GPIOH[3]

109

GPIOF[7]

110

GPIOF[6]

111

GPIOF[5]

112

GPIOF[4]

113

IRTX

114

IRRX

115

GPIOF[3]/IRMODE/IRRX3B

116

GPIOF[2]/IRTX2

117

GPIOF[1]/IRRX2

118

GPIOF[0]/IRMODE/IRRX3A

ECE5018 A0_VTQFP128~D

BID0BID3

00
1

0
1X00

0

108

VCC1

VCC1

VCC1

VCC1

ECE5018

GPIO

REV
M00

M01

TEST

CLK

X0111

00

X0201
X031001

1

C1750

0.1U_0402_16V4Z~D

2

1

C1754

0.1U_0402_16V4Z~D

2

USBP1+ 23
USBP1- 23
USB_HUBP1+ 30
USB_HUBP1- 30
USB_HUBP2+ 34
USB_HUBP2- 34
USB_HUBP3+ 31
USB_HUBP3- 31
USB_HUBP4+ 40
USB_HUBP4- 40

Route RBIAS and its
return to pin 128 very
short.

RUNPWR OK 39,42,49,54

1

2

C1761

4.7U_0603_6.3V4Z~D

SIO_VDDA

REG_EN

LPC_LAD[0..3] 22,28,39

LPC_LFRAME# 22,28,39
PLTRST2# 21,39
CLK_PCI_5018 6

CLKRUN# 23,30,39

LPC_LDRQ0# 22

LPC_LDRQ1# 22

IRQ_SERIRQ 23,28,30,39

CLK_SIO_14M 6

D_LAD0 36

D_LAD1 36

D_LAD2 36

D_LAD3 36

D_LFRAME# 36

D_CLKRUN# 36

D_DLRQ1# 36

D_SERIRQ 36

WLAN_RADIO_DIS# 34

1

2

C1762

4.7U_0603_6.3V4Z~D

2

8

VDDA33

14

VDDA33

20

VDDA33

119

VCC1

USBDP0
USBDN0
USBDP1
USBDN1
USBDP2

USB

LPC

DLPC

USBDN2
USBDP3
USBDN3
USBDP4
USBDN4

VDDA33PLL
VDDA18PLL

VDD18

CAP_LDO

RBIAS

TEST_PIN

ATEST

XTAL1/CLKIN

XTAL2

LAD0
LAD1
LAD2
LAD3

LFRAME#

LRESET#

PCICLK

CLKRUN#

LDRQ0#
LDRQ1#

SER_IRQ

CLKI (14.318 MHz)

VSS

DLAD0
DLAD1
DLAD2
DLAD3

DLFRAME#

DCLK_RUN#

DLDRQ1#

DSER_IRQ

PWRGD

OUT65

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

USBP1+

9

USBP1-

10

USB_HUBP1+

13

USB_HUBP1-

12

USB_HUBP2+

15

USB_HUBP2-

16

USB_HUBP3+

19

USB_HUBP3-

18

USB_HUBP4+

21

USB_HUBP4-

22
125

124
120
86
127

TEST_PIN is a No Connect

35

126
123

122

54
52
49
47
42
41
56
37
46
44
39

64
96
55

53
50
48
43
38
45
40

7
105

11
17
23
36
51
72
87
121
128

LPC_LAD0
LPC_LAD1
LPC_LAD2
LPC_LAD3
LPC_LFRAME#
PLTRST2#
CLK_PCI_5018
CLKRUN#
LPC_LDRQ0#
LPC_LDRQ1#
IRQ_SERIRQ

CLK_SIO_14M

D_LAD0
D_LAD1
D_LAD2
D_LAD3
D_LFRAME#
D_CLKRUN#
D_DLRQ1#
D_SERIRQ

RUNPWROK
WLAN_RADIO_DIS#

1

2

C1759

4.7U_0603_6.3V4Z~D

RBIAS

12

R1598

12K_0402_1%~D

1

2

C1760

0.1U_0402_16V4Z~D

1

C1751

0.1U_0402_16V4Z~D

2

1

1

2

2

C1755

0.1U_0402_16V4Z~D

<---PC Card Bay
<---Mini1 WWAN
<---Smart Card
<---Blue Tooth

+3.3V_ALW

12

R1599
10K_0402_5%~D

ECE5018_XTAL1
ECE5018_XTAL2

1

C1752

0.1U_0402_16V4Z~D

2

BLM18PG181SN1_0603~D

1 2

1

2

C1756

0.1U_0402_16V4Z~D

0_0402_5%~D

1

1

C67

2

C1757

0.1U_0402_16V4Z~D

12

R66

2

4.7U_0603_6.3V4Z~D

12

R1600

1M_0402_5%~D

1

C1753

0.1U_0402_16V4Z~D

2

+3.3V_ALW

L104

C1758

4.7U_0603_6.3V4Z~D

D_CLKRUN#
D_SERIRQ
D_DLRQ1#

LAN_TPM_EN#

C1451

15P_0402_50V8J~D

1 2

12

Y1

24MHZ_12PF_1BX24000CE1B~D

C1452

1 2

15P_0402_50V8J~D

Place closely pin 56

CLK_PCI_5018

R134

22_0402_5%~D

C144

12
12
12

12

@

@

R1645 100K_0402_5%~D
R1646 100K_0402_5%~D
R1437 100K_0402_5%~D

R1440 100K_0402_5%~D@

22P_0402_50V8J~D

+3.3V_RUN

+3.3V_ALW

12

1

2

DELL CONFIDENTIAL/PROPRIETARY

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.
ECE5018

LA-2792

38 70Tuesday, Feb ru ar y 07, 2006

1

1.0

of

5

+3.3V_ALW

D D

+5V_RUN

C C

Molex_53261

JDEBUG

@

Place closely pin 58

22P_0402_50V8J~D

B B

R93

BAT_SEL#

1 2

10K_0402_5%~D

+3.3V_ALW

8051_RX
8051_TX

1 2

R1752 0_0402_5%~D

12

@

1

2

@

CLK_KBD

DAT_KBD

CLK_DOCK

DAT_DOCK

+3.3V_ALW

12

1 2

R468 4.7K_0402_5%~D

1 2

R469 4.7K_0402_5%~D

1 2

R1607 4.7K_0402_5%~D

1 2

R1608 4.7K_0402_5%~D

5

5

4

4

3

3

2

2

1

1

R1752 no stuff when doing
flash recovery

CLK_PCI_5004

R130

22_0402_5%~D

C134

32 KHz Clock

+3.3V_ALW

12

R103

10K_0402_5%~D

SIO_A20GATE22
SIO_THRM#23

R1636

10K_0402_5%~D

DEBUG_ENABLE#

PLTRST2#21,38

CLK_PCI_50046

LPC_LFRAME#22,28,38

LPC_LAD[0..3]22,28, 38

CLKRUN#23,30,38
IRQ_SERIRQ23, 28,30, 38

ICH_EC_ SP I_C LK23
ICHI_ECO_SPI_D AT A23
ICHO_ECI_SPI_D AT A23

SIO_PWRBTN#23

KSO[0..17]40

KSI[0..7]40

SIO_A20GATE
SIO_THRM#

CLK_TP_SIO40
DAT_TP_SIO40
CLK_KBD36
DAT_KBD36
CLK_DOCK36
DAT_DOCK36

8051_RX34

8051_TX34

LPC_LAD[0..3]

BAT_SEL#50

BC_CLK38
BC_DAT38
BC_INT38

MEC5004_XTAL2

CLK_TP_SIO
DAT_TP_SIO
CLK_KBD
DAT_KBD
CLK_DOCK
DAT_DOCK

PLTRST2#
CLK_PCI_5004
LPC_LFRAME#
LPC_LAD0
LPC_LAD1
LPC_LAD2
LPC_LAD3
CLKRUN#
IRQ_SERIRQ

ICH_EC_ S PI _CLK
ICHI_ECO_SP I_DA T A
ICHO_ECI_SP I_DA T A

FCLK
ICHI_FDATAOUT
ICHO_FDATAIN

SIO_PWRBTN#
BAT_SEL#

BC_CLK
BC_DAT
BC_INT

MEC5004_XTAL1

R1785 0_0402_5%~D

MEC5004_XOSEL

12

R1606
10K_0402_5%~D

Same as Laguna

MEC5004_XTAL1

Y2

MEC5004_XTAL2

A A

32.768K_12.5PF_Q13MC30610003~D

C1450

22P_0402_50V8J~D

14
23

1

2

1

2

5

C1449

22P_0402_50V8J~D

Work Around

R104

ALWON

10K_0402_5%~D

21

@

1 2

D2002
RB751S40T1_SOD523-2~D

4

+RTC_CELL

0_0402_5%~D

KSO17
KSO16
KSO15
KSO14
KSO13
KSO12
KSO11
KSO10
KSO9
KSO8
KSO7
KSO6
KSO5
KSO4
KSO3
KSO2
KSO1
KSO0

KSI7
KSI6
KSI5
KSI4
KSI3
KSI2
KSI1
KSI0

12

L106
BLM18AG121SN1D_0603~D

12

@

@

PMST3906_SOT323-3~D

4

1 2

R62

U216

12

KSO17/GPIOA1

13

KSO16/GPIOA0

14

GPIO5/KSO15

15

GPIO4/KSO14

16

KSO13/GPIO18

17

KSO12/OUT8

18

KSO11/GPIOC7

19

KSO10/GPIOC6

20

KSO9/GPIOC5

23

KSO8/GPIOC4

24

KSO7/GPIO3

25

KSO6/GPIO2

27

KSO5/GPIO1

28

KSO4/GPIO0

29

KSO3/GPIOC3

30

KSO2/GPIOC2

31

KSO1/GPIOC1

32

KSO0/GPIOC0

33

KSI7/GPIO19

34

KSI6/GPIO17

35

KSI5/GPIO10

36

KSI4/GPIO9

37

KSI3/GPIO8

38

KSI2/GPIO7

39

KSI1/GPIO6

40

KSI0/SGPIO30

92

SGPIO34/A20M

50

OUT5/KBRST

75

GPIO94/IMCLK

76

GPIO95/IMDAT

77

KCLK

78

KDAT

79

EMCLK

80

EMDAT

81

GPIO20/PS2CLK/8051RX

82

GPIO21/PS2DAT/8051TX

57

LRESET#

58

PCICLK

59

LFRAME#

60

LAD0

61

LAD1

62

LAD2

63

LAD3

64

CLKRUN#

56

SER_IRQ

102

HSTCLK

105

HSTDATAIN

107

HSTDATAOUT

103

FLCLK

106

FLDATAIN

108

FLDATAOUT

109

FLCS0

110

FLCS1

87

BC_CLK

86

BC_DAT

85

BC_INT

122

XTAL1

124

XTAL2

123

XOSEL

+3.3V_ALW

12

R97
10K_0402_5%~D

R102

100K_0402_5%~D

E

3

B

2

C

@

1

Q19

@

1 2

R25 100K_0402_5%~D

1

C105

0.1U_0402_16V4Z~D

2

AGND

125
12

@

4.7U_0603_6.3V6M~D

1 2

C22

@

13

D

2

G

S

+3.3V_ALW

21

44

65

121

VCC1

VCC1

VCC1

VCC0

LPC InterfaceHost/8051 Keyboard and Mouse InterfaceBC Bus

VSS

VSS

VSS

VSS

VSS

26

51

74

88

113

R23

@

1 2

0_0402_5%~D

Q20

@

2N7002W-7-F_SOT323~D

83

116

VCC1

VCC1

PWR SW

SGPIO45/MSDATA/SPDOUT2

SGPIO44/MSCLK/SPCLK2

SYSOPT0/SGPIO32/LPC_TX

SYSOPT1/SGPIO33/LPC_RX

VR_CAP

VSS_PLL

22

101

0.1U_0402_16V4Z~D

1

C1769

4.7U_0603_6.3V4Z~D

2

1

C1763

0.1U_0402_16V4Z~D

2

ALWON
POWER_ SW_IN2#
POWER_ SW_IN1#
POWER_ SW_IN0#

ACAV_IN

BGPO0

AB1B_CLK

AB1B_DATA

AB1A_CLK

AB1A_DATA

GPIO11/AB2A_DATA

GPIO12/AB2A_CLK

GPIO13/AB2B_DATA

GPIO14/AB2B_CLK

GPIO87/AB1C_DATA

GPIO86/AB1C_CLK

GPIO85/AB1D_DATA

GPIO84/AB1D_CLK

GPIO93/AB1F_DATA

GPIO92/AB1F_CLK

GPIO91/AB1E_DATA

GPIO90/AB1E_CLK

GPIO82/FAN_TACH3
GPIO16/FAN_TACH2
GPIO15/FAN_TACH1

OUT2/PWM3

OUT9/PWM2
OUT11/PWM1
OUT10/PWM0

nEC_SCI/SPDIN2

SGPIO46/SPDIN1

SGPIO47/SPDOUT1

SGPIO31/TIN1/SPCLK1

SGPIO40
SGPIO41
SGPIO42
SGPIO43

SGPIO35

SGPIO36 (SFPI_EN)

SGPIO37

GPIO96/TOUT1

OUT7/nSMI
nPWR_LED

nBAT_LED

nFWP

GPIOA3/WINDMON

GPIO83/32KHZ_OUT

PWRGD

nRESET_OUT/OUT6

TEST_PIN

VCC_PLL

MEC5004_VTQFP128~D

104

L105 BLM18AG121SN1D_0603~D

C1768

1 2

12

3

1

2

120
119
126
127
128
118

8
7
6
5
93
94
95
96
111
112
9
10
97
98
99
100

43
42
41

48
47
46
45

66
55
54
69
68
67

70
71

91
90
89
4

1
2
3

52
11

115
114

84
73
117
49
53
72

3

2

C1764

0.1U_0402_16V4Z~D

SNIFFER_LED_OFF#

SPI_CS_L#

R110
0_0402_5%~D

1

C1765
10U_0805_10V4Z~D

2

ALWON
SNIFFER_PWR_SW#
POWER_SW_IN1#
POWER_SW_IN#
ACAV_IN

PBAT_SMBCLK
PBAT_SMBDAT
DOCK_SMB_CLK
DOCK_SMB_DAT
VAUX_EN
SUS_ON

RUN_ON
ITP_DBRESET#
SBAT_SMBDAT
SBAT_SMBCLK
DAT_SMB
CLK_SMB
SIO_SLP_S5#
SIO_SLP_S3#
SIO_RCIN#
SIO_EXT_WAKE#

FAN1_TACH

BREATH_LED
SIO_EXT_SCI#
PS_ID

VGA_IDENTIFY
LID_CL_SIO #
DEBUG_ENABLE#

HOST_DEBUG_TX
HOST_DEBUG_RX

CAP_LED#
SCRL_LED#
NUM_LED#

1 2

DOCK_SMB_INT#
SFPI_EN
PS_ID_DISABLE#

ATF_INT#
SIO_EXT_SMI#

BAT2_LED#
BAT1_LED#

FWP#
SIO_BIAPWM

RUNPWROK
RESET_OUT#

1 2

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

R63 0_0402_5%~D@

+3.3V_ALW

FWP#

Flash write protect bottom 4K
of internal bootblock flash

1

C1766

0.1U_0402_16V4Z~D

2

ALWON 46

ACAV_IN 18,50,51

PBAT_SMBCLK 45, 50
PBAT_SMBDAT 45,50
DOCK_SMB_CLK 36
DOCK_SMB_DAT 36
VAUX_EN 4 1,46
SUS_ON 41,42,46
RUN_ON 19,37,41,42,46,47,4 8,58

ITP_DBRESET# 7,23

SBAT_SMBDAT 19,45
SBAT_SMBCLK 19, 45
DAT_SMB 18
CLK_SMB 18

SIO_SLP_S5# 23

SIO_SLP_S3# 23

SIO_RCIN# 22

SIO_EXT_WAKE# 23

SNIFFER_LED_OFF# 43

FAN1_TACH 18

BREATH_LED 43

SIO_EXT_SCI# 23

PS_ID 44

CAP_LED# 43
SCRL_LED# 43
NUM_LED# 43

SIO_EXT_SMI# 23
BAT2_LED# 43
BAT1_LED# 43

RUNPWROK 38,42,49,54
RESET_OUT# 42

R1120_0402_5%~D

DOCK_SMB_INT# 36

PS_ID_DISABLE# 44

ATF_INT# 18

12

+3.3V_ALW

12

R138
100K_0402_5%~D

@

12

R139
100K_0402_5%~D

SPI_CS_R#

Bat2 = Amber LED
Bat1 = Green LED

20mA drive pins

low=write protected

BIA_PWM 19,52

1

2

SNIFFER_PWR_SW#

+3.3V_ALW

LID_CL_SIO #

12

R1604

10K_0402_5%~D

@

SPI_CS#23

C1767

0.1U_0402_16V4Z~D

+RTC_CELL

12

1 2

1

2

12

R482
1M_0402_5%~D

1

C482

0.047U_0402_16V4Z~D

2

12

R1605

10K_0402_5%~D

@

R127 47_0402_5%~D

2

R30
100K_0402_5%~D

R31

10K_0402_5%~D

SNIFFER#

C46
1U_0603_10V4Z~D

R473

10_0402_5%~D

1 2

LID_CL#

12

T6PAD~D
T7PAD~D

VGA_IDENTIFY

SPI_CS_R#

ICHI_FDATAOUT

47_0402_5%~D

+RTC_CELL

12

R119
100K_0402_5%~D

C130

1U_0603_10V4Z~D

12

R470
100K_0402_5%~D

12

1
2
3
4

10K_0402_5%~D

1 2

1

2

POWER_SW_IN1#

DOCK_SMB_DAT
DOCK_SMB_CLK
DOCK_SMB_INT#

U213

S#
Q
W#
VSS

M25P80-VMW6TP_SO8~D

Flash ROM

POWER_SW_IN# POWER_SW#

SNIFFER# 43

LID_CL# 40

+3.3V_ALW

1 = Discrete Gfx
0 = UMA

+3.3V_SUS

R1579

10K_0402_5%~D

1 2

R1788

1

R125

R1637 100K_0402_5%~D

R99 8.2K_0402_5%~D

R1618 10K_0402_5%~D

DAT_SMB
CLK_SMB
SBAT_SMBDAT
SBAT_SMBCLK
PBAT_SMBDAT
PBAT_SMBCLK

ATF_INT#

1=Flash Recovery Enabled
0=Flash Recovery Disabled

8

VCC

7

HOLD#

6

C

5

D

R100 8.2K_0402_5%~D

R106 10K_0402_5%~D
R105 10K_0402_5%~D
R444 2.2K_0402_5%~D
R131 2.2K_0402_5%~D
R449 4.7K_0402_5%~D
R447 4.7K_0402_5%~D

SFPI_EN

+3.3V_SUS

ICHO_FDATAIN

150 MIL SO8

U217

@

1

S#

2

Q

3

W#

4

VSS

M25P80-VMW6TP_SO8~D

HOLD#

8

VCC

7
6

C

5

D

200 MIL SO8

DELL CONFIDENTIAL/PROPRIETARY

Title

Size Doc u m en t N u m be r Re v

Date: Sheet

Compal Electronics, Inc.
EMC5004

LA-2792

1

POWER_SW# 18,40

12

12
12
12

1 2
1 2
1 2
1 2
1 2
1 2

R1635

10K_0402_5%~D

12

+3.3V_ALW

1

C1739

2

0.1U_0402_16V4Z~D

FCLK

12

R475
10K_0402_5%~D

@

12

R474
10K_0402_5%~D

12

10K_0402_5%~D

39 70Tuesday, F e br ua ry 07, 2006

+RTC_CELL

+5V_ALW

+3.3V_ALW

+3.3V_SUS

R1753

of

1.0

5

4

3

2

1

Touch PAD

JTPAD

2

112

COEX1_BT_ACTIVE34

USB_HUBP4-38
USB_HUBP4+38

1

C570

2

COEX2_WLAN_ACTIVE

LID_CL#39

33P_0402_50V8J~D

C54

0.1U_0402_16V4Z~D

COEX2_WLAN_ACTIVE34

D D

KSO[0..17]39

KSI[0..7]39

C C

B B

POWER_SW#18,39
R_NUM_LED#43
R_CAP_LED#43
R_SCRL_LED#43

+3.3V_RUN

KSO17
KSO16
KSO15
KSO14
KSO13
KSO12
KSO11
KSO10
KSO9
KSO8
KSO7
KSO6
KSO5
KSO4
KSO3
KSO2
KSO1
KSO0

KSI7
KSI6
KSI5
KSI4
KSI3
KSI2
KSI1
KSI0

KSO10
KSO11
KSO9
KSO14
KSO13
KSO15
KSO16
KSO12
KSO0
KSO2
KSO1
KSO3
KSO8
KSO6
KSO7
KSO4
KSO5
KSI0
KSI3
KSI1
KSI5
KSI2
KSI4
KSI6
KSI7
POWER_SW#
R_NUM_LED#
R_CAP_LED#
R_SCRL_LED#
KSO17 POWER_SW#

12

R518

10K_0402_5%~D

USB_BIO-31

USB_BIO+31

+3.3V_RUN

+3.3V_ALW

1

2

USB_HUBP4­USB_HUBP4+

LID_CL#

1

1

C63

2

0.047U_0402_16V4Z~D

JST_BM30B-SRDS-G-TFC~D

C62

2

0.1U_0402_16V4Z~D

4

334

6

556

8

7

8

7

10

9

10

9

12

11

12

11

14

13

14

13

16

15

16

15

18

17

18

17

20

19

20

19

22

21

22

21

24

23

24

23

26

25

26

25

28

27

28

27

30

29

30

29

32

G131G2

BT_RADIO_DIS#
COEX3

SP_GND
SP_X
SP_Y
SP_V+

TP_CLK
TP_DATA

1

2

12

R6

10K_0402_5%~D

+5V_RUN

C561

0.1U_0402_16V4Z~D

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

11

11

12

12

13

13

14

14

15

15

16

16

17

17

18

18

19

19

20

20

21

21

22

22

23

23

24

24

25

25

26

26

27

27

28

28

29

29

30

30

31

31

32

32

33

33

34

34

FOX_GS12403-0001K-8F~D

T31 PAD~D

BT_ACTIVE 34,43

JKYBRD

35

35

36

36

37

37

38

38

39

39

40

40

41

GND

42

GND

SP_GND

SP_X
SP_V+
SP_Y

1

2

TP_DATA
TP_CLK

BT_RADIO_DIS# 23

C596

@

100P_0402_50V8J~D

1

2

10P_0402_50V8J~D

C562

BLM18AG601SN1D_0603~D

+3.3V_RUN

L1

1 2
1 2

L2
BLM18AG601SN1D_0603~D

1

C560

2

10P_0402_50V8J~D

1

2

C564

0.1U_0402_16V4Z~D

12

1

2

+5V_RUN

12

R515

4.7K_0402_5%~D

1

C23

2

10P_0402_50V8J~D

100P_0402_50V8J~D

R517

4.7K_0402_5%~D

DAT_TP_SIO
CLK_TP_SIO

C35

C1802

@

FAN

Part Number Description

DC28A000800

Speak

Part Number Description

PK230003Q0L

DAT_TP_SIO 39
CLK_TP_SIO 39

10P_0402_50V8J~D

Power Switch

1

2

FAN SET DAQ20 DC5V AB7405HB-HB3 ADDA

SPK PACK ZJX 2.0W 4 OHM FG

SM CARD BODY

Part Number Description

112

PWR_SW

@SHORT PADS~D

S SOCKET TYCO 1770551-1

SP070007V0L

10P H5.9 SMART

PCMCIA BODY

Part Number Description

DC000001Q0L

Bluetooth wire set cable

Part Number Description

DC020004A0L

MDC wire set cable

Part Number Description

DC020003Z0L

T/P wire set cable

Part Number Description

DC020004T0L

LVDS cable

Part Number Description

DC020003Y0L

RTC BATT

Part Number Description

GC20323MX00

2

PCMCIA TYCO
1759096-1

H-CONN SET ZJX
MB-B/T MODU

H-CONN SET ZJX
MB-MDC

H-CONN SET ZJX
MB-TP

H-CONN SET ZJX
MB-LCD 14 WXGA+

BATT CR2032 3V
220MAH MAXELL

1

1

1

1

A A

2

2

100P_0402_50V8J~D

100P_0402_50V8J~D

@

@

C34

C33

5

1

2

2

2

100P_0402_50V8J~D

100P_0402_50V8J~D

@

C32

100P_0402_50V8J~D

@

@

C31

C30

1

1

1

2

2

2

@

C25

100P_0402_50V8J~D

100P_0402_50V8J~D

100P_0402_50V8J~D

@

@

C75

C45

1

1

1

2

100P_0402_50V8J~D

@

C74

1

2

2

2

100P_0402_50V8J~D

100P_0402_50V8J~D

100P_0402_50V8J~D

@

@

@

C20

C21

C17

4

1

1

1

1

1

2

2

2

@

C16

100P_0402_50V8J~D

100P_0402_50V8J~D

100P_0402_50V8J~D

@

@

C14

C15

1

2

2

2

100P_0402_50V8J~D

100P_0402_50V8J~D

@

C12

100P_0402_50V8J~D

@

@

C11

C10

1

1

2

100P_0402_50V8J~D

@

C8

1

1

2

2

2

100P_0402_50V8J~D

100P_0402_50V8J~D

100P_0402_50V8J~D

@

@

@

C6

C5

C7

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

1

1

1

2

100P_0402_50V8J~D

@

C4

3

1

2

2

2

100P_0402_50V8J~D

100P_0402_50V8J~D

100P_0402_50V8J~D

@

@

@

C3

C39

C1789

2

DELL CONFIDENTIAL/PROPRIETARY

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.
INT KB

LA-2792

40 70Tuesday, Feb ru ar y 07, 2006

1

of

1.0

5

4

3

2

1

DC/DC Interface

+15V_SUS

+5V_ALW

12

D D

SUS_ON39,42,46

C C

B B

SUS_ON

RUN_ON19,37,39,42,46,47,48,58

2

G

R1758
100K_0402_5%~D

SUS_ON_5V#

13

D

Q85

2

2N7002W-7-F_SOT323~D

G

S

12

R202
100K_0402_5%~D

RUN_ON_5V#

2N7002W-7-F_SOT323~D

13

D

Q17

S

2N7002W-7-F_SOT323~D

Q22

2

G

2

G

+15V_SUS+5V_ALW

12

R223
100K_0402_5%~D

13

D

S

12

R1759
100K_0402_5%~D

13

D

Q86
2N7002W-7-F_SOT323~D

S

RUN_ENABLE46

RUN_ENABLE

1

C284

2

4700P_0402_25V7K~D

SUS_ENABLE

+3.3V_SRC

+5V_SUS

+3.3V_SRC

1 2

R1765
0_0402_5%~D

+1.8V_SUS

Q23

SI3456BDV-T1-E3_TSOP6~D

D

6

S

45
2
1

1A Rating

G

C285

3

10U_0805_10V4Z~D

Run Planes Enable

Q24

SI4800BDY-T1-E3_SO8~D

8
7

5

Q6

SI4800BDY-T1-E3_SO8~D

8
7

5

Q14

SI4800BDY-T1-E3_SO8~D

8
7

5

1
2
36

4

C283

1
2
36

4

C1782

1

C1804
470P_0402_50V7K~D

2

@

1
2
36

C172

4

10U_0805_10V4Z~D

10U_0805_10V4Z~D

1

2

1

2

1

2

1

2

+3.3V_SUS

12

R222
20K_0402_5%~D

+5VRUN Source

+5V_RUN

12

R215
20K_0402_5%~D

+3VRUN Source

+3.3V_RUN

12

R1757
20K_0402_5%~D

+1.8VRUN Source

+1.8V_RUN

12

R148
20K_0402_5%~D

+3VSUS Source

10K_0402_5%~D

MODC_EN#38

DDTC144EUA-7-F_SOT323~D

+5VMOD Source

+3.3V_ALW

R2149

10K_0402_5%~D

HDDC_EN#38

DDTC144EUA-7-F_SOT323~D

+5V_HDD Source

MOD_EN

C1262

0.1U_0603_50V4Z~D

+5V_SUS

6

2

1

D

Q57

G

S

4 5

1

C1263

2

10U_0805_10V4Z~D

SI3456BDV-T1-E3_TSOP6~D

+5VMOD

1 2

12

R1295
100K_0402_5%~D

PJP22

@PAD-OPEN 4x4m

+5V_RUN

3

1

2

R2148

+3.3V_ALW

12

2

Q58

+15V_SUS

12

R1293
100K_0402_5%~D

2

13

HDD PWR

C547

@

+5V_SUS

6

2

1

D

Q50

C546

10U_0805_10V4Z~D

S

4 5

1

2

SI3456BDV-T1-E3_TSOP6~D

+5VHDD

12

R504

100K_0402_5%~D

PJP24

1 2

PAD-OPEN 4x4m

@

+5V_RUN

G

3

1

2

0.1U_0603_50V4Z~D

+15V_SUS

12

Q51

12

R507
100K_0402_5%~D

HDD_EN_5V

13

2

1 2

R1764
100K_0402_5%~D

+PWR_SRC+PWR_SRC

12

12

R1614
100K_0402_5%~D

N21917830

13

D

VAUX_EN39,46

A A

2

G

5

R1616

S

Q82

200K_0402_5%~D

2N7002W-7-F_SOT323~D

R1615
100K_0402_5%~D

ENAB_3VLAN 28

2N7002W-7-F_SOT323~D

12

R1617
470K_0402_5%~D

SUS_ON_5V#

4

13

D

2

G

12

S

Q83

+1.8V_SUS

2

G

12

13

D

S

10U_0805_10V4Z~D

2

C1788

0.047U_0402_16V4Z~D

1

R1795

30_0603_5%

Q89

2N7002W-7-F_SOT323~D

GFX_RUN_ON 58

+VDD_CORE+1.8V_RUN

12

R1803

@

30_0603_5%

13

RUN_ON_5V#

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

D

2

G

Q28

S

@

2N7002W-7-F_SOT323~D

12

R1766

30_0603_5%

13

D

2

G

S

2

G

Q26

2N7002W-7-F_SOT323~D

Discharg Circuit

+5V_RUN +3.3V_RUN + 1 . 5V_RUN +0.9V_DDR_VTT +2.5V_RUN

12

R1793

@

1K_0402_5%~D

13

D

Q87

S

@

2N7002W-7-F_SOT323~D

12

R1794

@

1K_0402_5%~D

13

D

2

G

Q88

S

@

2N7002W-7-F_SOT323~D

12

R1796

@

1K_0402_5%~D

13

D

2

G

Q90

S

@

2N7002W-7-F_SOT323~D

12

R1797

@

1K_0402_5%~D

13

D

2

G

Q91

S

@

2N7002W-7-F_SOT323~D

12

@

13

D

2

G

S

DELL CONFIDENTIAL/PROPRIETARY

Title

Size Document Number Rev

2

Date: Sheet

Compal Electronics, Inc.
POWER CONTROL

LA-2792

41 70Tuesday, Feb ru ar y 07, 2006

1

R1798

1K_0402_5%~D

Q92

@

2N7002W-7-F_SOT323~D

1.0

of

5

For EMI

4

3

2

1

+3.3V_RUN +1.8V_SUS

+3.3V_RUN +3.3V_SUS

D D

+3.3V_RUN +1.5V_RUN

+1.5V_RUN +1.05V_VCCP

+3.3V_RUN

+3.3V_RUN

+3.3V_RUN

C C

+3.3V_RUN

+PWR_SRC

B B

A A

C1806

@
1 2

0.047U_0402_16V4Z~D

C1807

@
1 2

0.047U_0402_16V4Z~D

C1808

@
1 2

0.047U_0402_16V4Z~D

C1809

@

1 2

0.047U_0402_16V4Z~D

C1814

@
1 2

0.047U_0402_16V4Z~D

C1812

@

1 2

0.047U_0402_16V4Z~D

C1813

@

1 2

0.047U_0402_16V4Z~D

C1810

1 2

0.047U_0402_25V4Z~D

C1811

1 2

0.047U_0402_25V4Z~D

+SDC_IN

+SDC_IN

+3.3V_SUS

IMVP_PWRGD23,49
RESET_OUT#39

IMVP_PWRGD
RESET_OUT#

ICH_PWRGD

100K_0402_5%~D

+3.3V_RUN

12

R494
20K_0402_5%~D

R49 0_0402_5%~D

2.5V_RUN_PWRGD18

1.5V_RUN_PWRGD47

1.05V_RUN_PWRGD47

0.9V_DDR_PWRGD48

GFX_CORE_PWRGD58

GFX_PCIE_PWRGD58

+3.3V_SUS

14

U26B

4

P

IN1

6

OUT

5

IN2

G

74VHC08MTCX_NL_TSSOP14~D

7

+3.3V_SUS

12

R453

ICH_PWRGD# COINCELL

13

D

Q41

2

2N7002W-7-F_SOT323~D

G

S

R463
0_0402_5%~D

1 2

R313 0_0402_5%~D

R319 0_0402_5%~D

R334 0_0402_5%~D

R2170 0_0402_5%~D

@

R2171 0_0402_5%~D

ICH_PWRGD# 18

12
12

12

12

12

12

ICH_PWRGD 10,23

SUSPWROK_1P8V48

3VRUNRC

1

C520

0.01U_0402_16V7K~D

2

10K_0402_5%~D

0.1U_0402_16V4Z~D

R1386

C1816

+3.3V_SUS

C483

0.1U_0402_16V4Z~D

1 2

8

U24A

P

A1Y

G

74LVC3G14DC_VSSOP8~D

4

+3.3V_ALW

12

12

13

2

G

1

2

+COINCELL

+3.3VX

2

D15

1

BAT54CW_SOT323~D

7

R1383
100K_0402_5%~D

D

Q7
2N7002W-7-F_SOT323~D

S

12

R471
1K_0402_5%~D

Z4012

3

+RTC_CELL

1

C528
1U_0603_10V4Z~D

2

+3.3V_SUS

8

U24B

P

A6Y

G

74LVC3G14DC_VSSOP8~D

4

RUN_ON19,37,39,41,46,47,48,58

SUS_ON39,41,46

+3.3V_SUS

8

U24C

P

A3Y

G

74LVC3G14DC_VSSOP8~D

4

2

5

COIN RTC Battery

10

+COINCELL

+3.3V_SUS

1 2

14

U26A
74VHC08MTCX_NL_TSSOP14~D

1

P

IN1

OUT

2

IN2

G

7

+3.3V_SUS

14

U26C

P

IN1

OUT

9

IN2

G

74VHC08MTCX_NL_TSSOP14~D

7

C480

0.1U_0402_16V4Z~D

3

13
12

8

JCOIN

1

1

2

2

MOLEX_53398-0271~D

+3.3V_SUS

14

U26D

P

IN1

11

OUT

IN2

G

74VHC08MTCX_NL_TSSOP14~D

7

RUNPWROK

RUNPWR OK 38,39,49,54

SUSPWROK 18,23

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.
Power Good

LA-2792

42 70Tuesday, Feb ru ar y 07, 2006

1

1.0

of

H1

H_T146B217D91

1

H11
@H_T315B237D118

1

D D

H31

@H_C24D24N

1

H2
H_T146B217D91

1

H12
@H_C315D118

1

H32

@H_C24D24N

1

5

H3

@H_C315D110

1

H13

@H_C315D118

1

H14

@H_T315B237D118

1

H4

H_T256B63D47

1

@H_C472D376

H26

1

H5
@H_C315D110

H15
@H_C315D118

1

1

H27

@H_C472D431X376

H6

@H_C236B256D110

1

H16
@H_T217B315D98

1

1

H7
@H_C315D110

1

H17
@H_T217B315D98

1

@H_O115X31D115X31N

H28

@H_O115X31D115X31N

1

4

H8

@H_T217B315D98

1

H18

@H_C217D91

1

H29

1

@H_C315D110

H19

@H_C217D91

1

H9

H10

@H_C315D110

1

1

H20

@H_T217B315D98

1

H30

@H_O115X31D115X31N

1

CLIP1
EMI_CLIP

CLIP4
EMI_CLIP

CLIP5
EMI_CLIP

3

EMI CLIP

@

1

GND

@

1

GND

@

1

GND

1

1

1

CLIP2
EMI_CLIP

GND

CLIP3
EMI_CLIP

GND

CLIP6
EMI_CLIP

GND

2

FD1

1

@

@

@

FIDUCIAL MARK~D

FD7

1

FIDUCIAL MARK~D

FD13

1

FIDUCIAL MARK~D

FD19

1

FIDUCIAL MARK~D

CAP_LED#39

NUM_LED#39

SCRL_LED#39

Fiducial Mark

FD2

1

FIDUCIAL MARK~D

FD8

1

FIDUCIAL MARK~D

FD14

1

FIDUCIAL MARK~D

FD20

1

FIDUCIAL MARK~D

R231

330_0402_5%~D

R237

330_0402_5%~D

R21

330_0402_5%~D

FD3

1

FIDUCIAL MARK~D

FD9

1

FIDUCIAL MARK~D

FD15

1

FIDUCIAL MARK~D

FD21

1

FIDUCIAL MARK~D

R_CAP_LED#

12

R_NUM_LED#

12

R_SCRL_LED#

12

FIDUCIAL MARK~D

FIDUCIAL MARK~D

1

FIDUCIAL MARK~D

1

FIDUCIAL MARK~D

FD4

1

FD10

1

FD16

FD22

R_CAP_LED# 40

R_NUM_LED# 40

R_SCRL_LED# 40

1

FD5

1

FIDUCIAL MARK~D

FD11

1

FIDUCIAL MARK~D

FD17

1

FIDUCIAL MARK~D

FD23

1

FIDUCIAL MARK~D

FD6

1

FIDUCIAL MARK~D

FD12

1

FIDUCIAL MARK~D

FD18

1

FIDUCIAL MARK~D

FD24

1

FIDUCIAL MARK~D

FD25

1

FIDUCIAL MARK~D

Disable HDD LED

C C

B B

A A

SATA_ACT#22

SNIFFER_LED_OFF#39

SNIFFER_YELLOW#18

SNIFFER_GREEN#18

+3.3V_RUN +3.3V_RUN

12

R76

10K_0402_5%~D

SATA_ACT# SATA_ACT#_R

+3.3V_ALW

12

SNIFFER_YELLOW#

DDTA114EUA-7-F_SOT323~D

SNIFFER_GREEN#

DDTA114EUA-7-F_SOT323~D

5

R1449
10K_0402_5%~D

@

R1448
0_0402_5%~D @

1 2

S

G

2

2

Q16

2

Q13

D

13

Q66
BSS138W-7-F_SOT323~D

+3.3V_SUS

1 3

+3.3V_SUS

1 3

1 2

R20 220_0402_5%~D

1 2

R19 220_0402_5%~D

2

LED_WLAN_OUT#34

4

SNIFFER_WIRELESS_ON/OFF#38

SNIFFER_Y
SNIFFER_G

Q1
DDTA114EUA-7-F_SOT323~D

1 3

SNIFFER#39

D4

Y

3
2

G

12-22AUYSYGC/530-A2/TR8_G/Y~D

R2

1 2

330_0402_5%~D

SNIFFER_WIRELESS_ON/OFF#

SNIFFER#

1

R_SATA_ACT 32

R_PIDEACT 36

+3.3V_RUN

2

Q5
DDTA114EUA-7-F_SOT323~D

1 3

R15

1 2

100_0402_5%~D

+3.3V_ALW

12

R56
10K_0402_5%~D

JSNIFF

4
3
2
1

1BS008-13130-7F_4P~D

3

R1434

10K_0402_5%~D

BT_ACTIVE

BT_ACTIVE34,40

SNIFFER_LED_OFF#39

4
3
2
1

R_MPCI_ACT

R_MPCI_ACT 32

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

1 2

B

2

2

G

E

3

Q65
PMST3906_SOT323-3~D

C

1

BREATH_LED39

BAT1_LED#39

BAT2_LED#39

13

D

S

BAT1_LED#

BAT2_LED#

+5V_RUN

2

1 3

Q4

BSS138W-7-F_SOT323~D

R3

10K_0402_5%~D

BREATH_LED_B

1 2

2

2

2

Q18
DDTA114EUA-7-F_SOT323~D

R8
1K_0402_5%~D

1 2

+3.3V_ALW

Q2
DDTA114EUA-7-F_SOT323~D

1 3

+3.3V_ALW

Q35
DDTA114EUA-7-F_SOT323~D

1 3

R_BT_ACT

+3.3V_SUS

C

Q3

2

B

MMST3904-7-F_SOT323~D

E

3 1

R5

1 2

R265

1 2

R_BT_ACT 32

R1

1 2

56_0402_5%~D

BATT_GREEN_LED

220_0402_5%~D

BATT_AMBER_LED

330_0402_5%~D

BREATH_GREEN_LED

BATT_GREEN_LED 32

BATT_AMBER_LED 32

DELL CONFIDENTIAL/PROPRIETARY

Title

Size Doc u m en t N u m be r Re v

Date: Sheet

Compal Electronics, Inc.
PAD and Standoff

LA-2792

1

BREATH_GREEN_LED 32

43 70Tuesday, F e br ua ry 07, 2006

of

1.0

5

4

3

2

1

D D

PR346

@

1 2

0_0402_5%~D

PS_ID_IN

PS_ID_IN36

PR6

2

3

@

1 2

PD53

100K_0402_1%~D

SM24_SOT23

1

C C

PR10

1 2

15K_0402_1%~D

Z-series AC Adaptor
Connctor

B B

D

1 3

G

2

C

PQ2

2

B

MMST3904-7-F_SOT323~D

E

3 1

PJPDC1
TYCO_1566065-2~D

9

GND_4

8

GND_3

7

GND_2

6

GND_1

MH1

MH2

S

PQ1
FDV301N_SOT23~D

Low_PWR

33_0402_5%~D

1 2

DC+_1
DC+_2

DC-_1
DC-_2

PR184

1
2
3
4
5

+5V_ALW

2

3

PD2

DA204U_SOT323~D

1

+5V_ALW

12

FBM-L11-160808-601LMT 0603~D

PWR_ID

FBMA-L18-453215-900LMA90T_1812~D

+ADP_DCIN

+3.3V_ALW

PR2

1 2

2.2K_0402_5%~D

+5V_ALW

3

PD41

PR7

@

DA204U_SOT323~D

10K_0402_1%~D

PR299

@

1 2

100_0402_5%~D

PL1

FBMA-L18-453215-900LMA90T_1812~D

DOCK_DC_IN36

12

PL2

1 2

PL34

1 2

1

PS_ID_IN

2

PS_ID 39

PS_ID_DISABLE# 39

DOCK_DC_IN

PC2

1 2

0.47U_0805_25V7k

DC_IN+ Source

PQ3

FDS6679Z_SO8~D

1
2
3 6

12

4

PR11

150K_0402_1%~D

12

PR13

100K_0402_1%~D

+PWR_SRC

PC1

1U_0805_25V4Z~D

8
7

5

12

12

PC4

PC3

1000P_0402_50V7K~D

12

PR12

PC5

@

0.1U_0603_25V7K~D

4.7K_0603_5%~D

0.1U_0603_25V7K~D

12

12

+3.3VX Source

PU1

1

IN

5

OUT

3

EN

4

NC

GND

MIC5235-3.3BM5_SOT23-5~D

2

+DC_IN

1

PC6

2

10U_1206_25V6M~D

+3.3VX

1

PC7

2.2U_0603_6.3V6K~D

2

THESE CAPS MUST BE
NEXT TO JCHG

A A

DELL CONFIDENTIAL/PROPRIETARY

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONF IDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVIS ION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INF ORMATION IT CON TAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WR ITT EN CO NSE NT OF COMPAL ELECTRONICS, INC.

3

2

Title

Size Doc u m en t N u m be r Re v

Date: Sheet

Compal Electronics, Inc.
+DCIN

LA-2792

1

44 70Tuesday, F e br ua ry 07, 2006

1.0

of

5

4

+3.3V_ALW

3

2

1

ESD Diodes

2

3

D D

PC231

2200P_0402_50V7K~D

Secondary Battery Connector

PJP1

BATT1+
BATT2+

12

SMB_CLK
SMB_DAT

BATT_PRES#

SYSPRES#

BATT_VOLT

10

GND

11

GND

TYCO_1734077-1~D

BATT1­BATT2-

1
2
3
4
5
6
7
8
9

Z4301
Z4302
Z4303

PD42

DA204U_SOT323~D @

PR301

100_0402_5%~D

1 2

+3.3V_ALW

1

PR302

100_0402_5%~D

1 2

DA204U_SOT323~D @

PD43

2

3

1

100_0402_5%~D

1 2

PR303

3

PD44

1

DA204U_SOT323~D @

100_0402_5%~D

1 2

2

PR304

ESD Diodes

2

3

C C

Primary Battery Connector

PBATT1

12

PC10

2200P_0402_50V7K~D

BATT_PRES#

10

GND

11

GND

SUYIN_200277MR009G506ZR~D

BATT1+

BATT2+
SMB_CLK
SMB_DAT

SYSPRES#

BATT_VOLT

BATT1­BATT2-

1
2
3
4
5
6
7
8
9

Z4304
Z4305
Z4306

PD9

DA204U_SOT323~D @

PR20

100_0402_5%~D

1 2

1

PR21

100_0402_5%~D

1 2

PD10
DA204U_SOT323~D @

2

3

1

PR22

100_0402_5%~D

1 2

3

PD11

1

DA204U_SOT323~D @

100_0402_5%~D

1 2

2

PR23

2

3

+3.3V_ALW

PD45

1

DA204U_SOT323~D @

SBAT_SMBCLK 19,39
SBAT_SMBDAT 19,39

DA204U_SOT323~D @

SBAT_ALARM# 38

PBAT_SMBCLK 39,50
PBAT_SMBDAT 39,50

PBAT_ALARM# 38

2

3

PD12

1

FBMA-L18-453215-900LMA90T_1812~D

12

PC230

0.1U_0603_25V7K~D

FBMA-L18-453215-900LMA90T_1812~D

PC9

0.1U_0603_25V7K~D

12

1 2

PL6

1 2

PL32

SBATT+

PBATT+

12

PR300

10K_0402_5%~D

+3.3V_ALW

12

PR19

10K_0402_1%~D

SBAT_PRES# 38,51

PBAT_PRES# 38

9

8

7

6

5

4

3

2

1

SUYIN_20175A-09G1
TOP view

B B

A A

DELL CONFIDENTIAL/PROPRIETARY

Title

THIS SHEET OF EN GINEE RING D RAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.
Battery Conn.

LA-2792

45 70Tuesday, Feb ru ar y 07, 2006

1

1.0

of

5

PJP25

1 2

PAD-OPE N 4x4m

PL22

FBM-L11-453215-900LMAT_1812~D

1

+

2

100U_25V_M

12

0.1U_0402_10V7K~D

PC251

RUN_ENABLE 41

12

@

PR355

0_0603_5%~D

12

2
1

PR343

@

0_0402_5%~D

1 2

+3.3VX

I0
I1

12

1

1

PC17

PC16

2

2

@

10U_1206_25V6M~D

10U_1206_25V6M~D

Place these CAPs
close to FETs

SI4800BDY-T1_SO8~D

4.7U_SPC-1205P-4R7B_+40-20%~D

12

@

PR344
0_0402_5%~D

12

PR345
0_0402_5%~D

PU17

5

TC7SH32FU_SSOP5~D

P

4

O

G

3

PL9

1 2

1

2

PC268

10U_1206_25V6M~D

SI4810BDY_SO8~D

+PWR_SRC

D D

Typical:4A Typical:5A
Peak current:8A Peak current:7A
OCP point is from 8.2A to 10.5A OCP point is from 8A to 11.2A

1

2

PC244

@

330U_D3L_6.3V_R25~D

C C

SUS_ON39,41,42
VAUX_EN39,41

+3.3V_SRC

B B

S

D

6

+3.3V_ALW

+3.3V_SRCP

1

+

+

PC31

2

330U_D3L_6.3V_R25~D

PQ82

FDC655BN_NL_SSOT-6~D

3

G

2451

PC252

PC32

NC_TEST1

0.1U_0603_25V7K~D

4

DC/DC +3V/ +5V/ +15V

+DC1_PWR_SRC

PR27

0_1206_5%~D

12

PC20

4.7U_1206_25V6K~D

0.1U_0603_25V7K~D

2K_0402_1%~D

1 2

1 2

240K_0402_5%~D

PR49

1K_0402_1%~D

1 2

1 2

12

PC21

0.1U_0603_25V7K~D

PC28

12

PR41

12

12

PC26

PC25

0.1U_0603_25V7K~D

2200P_0402_50V7K~D

578

PQ77

PQ5

ALWON39

THERM_STP#18

@

3 6

241

578

3 6

241

SUS_ON39,41,42

PR47

PC36

@

1000P_0402_50V7K~D

PR32

2.2_0603_5%~D

1 2

12

+VCC_MAX1999

47_0603_5%~D

12

PC24

1U_0603_10V6K~D

20
17

6
28
26
27
24
22

7

3

4
25

+3.3V_ALW

12

PC34

4.7U_1206_10V7K~D

PR28

PU3

V+
VCC
SHDN
BST3
DH3
LX3
DL3
OUT3
FB3
ON3

ON5
LDO3

PR51

12

1

PD14

2

3

RB717F_SOT323~D

LDO5
BST5

OUT5

ILIM5
ILIM3

PGOOD

SKIP

MAX8734AEEI_QSOP28~D

12

PR48

MAX1999_SKIP#

0_0402_5%~D

@

PR50

@

0_0402_5%~D

12

0_0402_5%~D

3

Place these CAPs
close to FETs

MAX8734_REF

12

1U_0603_10V6K~D

12

PR349

0_0402_5%~D

PC18

578

578

0.1U_0603_25V7K~D

3 6

3 6

PR37

PR188

12

241

241

1 2

45.3K_0402_1%~D

1 2

453K_0402_1%~D

PC19

PQ78
SI4800BDY-T1_SO8~D

PQ6
SI4810BDY_SO8~D

+5V_ALW

12

12

PC22

4.7U_1206_25V6K~D

PR29

18

0_0603_5%~D

14

1 2

16

DH5

15

LX5

19

DL5

21
1

N.C.

9

FB5

10

PRO

11
5
8

REF

13

TON

23

GND

2

+3.3V_SRCP

PR42

100K_0402_1%~D

12

+VCC_MAX1999

12

RUN_ON 19,37,39,41,42,47, 48,58

PC27

0.1U_0603_25V7K~D

1 2

1 2

SUSPWROK_5V 48

PC23

1U_0603_10V6K~D

PC33

2

PR203

100_0805_5%~D

+15VS_L

1 2

PD13

EC11FS2_SOD106~D

1 2

1 2

2 1

+15VS

1 4

MAX8734_REF

12

PC15

2.2U_1206_25V7M~D

PL8

4.7U_STQB125A-4722_8A_30%~D

3 2

+VCC_MAX1999

12

PR347

@

1 2

100K_0402_1%~D

13

D

2

G

PQ80

@

S

RHU002N06_SOT323

PR46
0_0402_5%~D

12

2200P_0402_50V7K~D

PR38

12.7K_0402_1%~D

PR44

243K_0402_1%~D

+15V_SUSP

1

2

PD35

3

PC30

12

@

PR353

0_0402_5%~D

12

PR354
0_0402_5%~D

12

MMBZ5245B_SOT23~D

12

PC29

0.1U_0402_10V7K~D

THERM_STP# 1 8

PC156

2.2U_1206_25V7M~D

+5V_SUSP

1

+

2

330U_D3L_6.3V_R25~D

12

@

0_0603_5%~D

@

PR356

1

+

2

PC245

330U_D3L_6.3V_R25~D

NC_TEST2

1

+15V_SUSP

+5V_SUSP

+3.3V_SRCP

A A

PJP4

1 2

PAD-OPEN 4x4m

PJP5

1 2

PAD-OPEN 4x4m

PJP6

1 2

PAD-OPEN 4x4m

+15V_SUS

+5V_SUS

+3.3V_SRC

DELL CONFIDENTIAL/PROPRIETARY

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONF IDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVIS ION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INF ORMATION IT CON TAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WR ITT EN CO NSE NT OF COMPAL ELECTRONICS, INC.

3

2

Title

Size Doc u m en t N u m be r Re v

Date: Sheet

Compal Electronics, Inc.
+3.3V/+5V/+15V

LA-2792

1

46 70Tuesday, F e br ua ry 07, 2006

1.0

of

A

B

C

D

+1.5VRUNP / +VCCP_1P05VP

+PWR_SRC

1 1

2 2

+1.5V_RUNP +VCCP_1P05VP

12

3 3

+1.5V_RUNP +1.5V_RUN

4 4

+VCCP_1P05VP +1.05V_VCCP

1

+

PC168

2

PC208

@

10U_0805_6.3V5K~D

330U_D2E_2.5VM_R9~D

@

PR279

1 2

0_0402_5%~D

PR281

@

1 2

PJP19

1 2

PAD-OPEN 4x4m

PJP23

1 2

PAD-OPEN 4x4m
PJP21

1 2

PAD-OPEN 4x4m

PJP20

1 2

PAD-OPEN 4x4m

PL25

FBM-L11-453215-900LMAT_1812~D

1 2

Max current:5A
OCP=7.08~11.96A

3.8uH_SIL104-3R8_6A_30%~D

12

12

PR221

PC169

0.01U_0402_25V7K~D

12

PC264

100P_0402_50V8K

0_0402_5%~D

A

19.6K_0402_1%~D

12

PR225

28.7K_0603_1%~D

12

@

PC210

1000P_0402_50V7K~D

1

2

PL26

1 2

1

2

PC159

PC160

10U_1206_25V6M~D

10U_1206_25V6M~D

12

12

PC161

PC262

2200P_0402_50V7K~D

0.1U_0603_25V7K~D

21

PD36

RB751V_SOD323~D

578

PQ8

FDS8880_SO8~D

PQ83

FDS6670AS_SO8~D

1 2

PC166

3 6

241

578

3 6

241

RUN_ON19,37,39,41,42,46,48,58

0.1U_0603_25V7K~D

+1.5VRUNP_L +VCCP_1P05VP_L

12

PR227
1K_0402_1%~D

1.5V_RUN_PWRGD42

B

+DC2_PWR_SRC

+5V_SUS

PR216
10_0805_5%~D

1 2
12

PC165

2.2U_0805_10V6K~D

PR278

0_0603_5%~D

12

PR219

1.43K_0402_1%~D

1 2

PR223

1 2

124K_0402_1%

1 2

PC172

0.01U_0402_25V7K~D

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

12

28

VCC

23

BOOT2

24

UGATE2

25

PHASE2

27

LGATE2

22

ISEN2

26

PGND2

19

VSEN2

20

VOUT2

21

EN2

18

OCSET2

17

SOFT2

16

PG2/REF

ISL6227CA-T_SSOP28~D

PC205

1U_0603_10V6K~D

PU9

13

DDR

14

VIN

6

BOOT1

5

UGATE1

4

PHASE1

2

LGATE1

7

ISEN1

3

PGND1

10

VSEN1

9

VOUT1

8

EN1

ISL6227CA-T

11

OCSET1

12

SOFT1

15

PG1

1

GND

12

PC261

0.01U_0402_25V7K~D

PR277

0_0603_5%~D

PR220

2.1K_0402_1%~D

1 2

PR224

1 2

124K_0402_1%

1 2

PC173

0.01U_0402_25V7K~D

12

PR272
1K_0402_1%~D

RUN_O N 19,37,39,41,42,46,48,58

C

21

PD37

12

RB751V_SOD323~D

PC167

1 2

1.05V_RUN_PWRGD 42

1

1

12

2

2

PC162

PC163

10U_1206_25V6M~D

10U_1206_25V6M~D

578

PQ38

FDS8880_SO8~D

12

PC164

PC263

0.1U_0603_25V7K~D
2200P_0402_50V7K~D

Typical:8A
Peak current:10A

3 6

241

0.1U_0603_25V7K~D

578

3 6

241

PL27

1.5uH_SIL104-1R5_10A_30%~D

1 2

PC170

0.01U_0402_25V7K~D

PQ40

FDS6670AS_SO8~D

PC265

@

100P_0402_50V8K

12

12

12

12

12

PC211

@

OCP=14.23~18.39A

PR222

5.11K_0402_1%~D

PR226

30.1K_0603_1%~D
PR280

0_0402_5%~D

1 2

PR282

@

1 2

1000P_0402_50V7K~D

0_0402_5%~D

1

12

+

PC206

2

PC207

@

10U_0805_6.3V5K~D

330U_D2E_2.5VM_R9~D

DELL CONFIDENTIAL/PROPRIETARY

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.
+1.5VSUSP /+VCCP_1P05VP

LA-2792

D

47 70Tuesday, Feb ru ar y 07, 2006

of

1.0

5

4

3

2

1

D D

PC58

12

2200P_0402_50V7K~D

PQ34

IRF7821_SO8~D

PQ11

IRF7832_SO8~D

88550_AVDD

+DDR_PWR_SRC

D8D7D6D

S1S2S3G

3 6

241

5

4

578

PC68

0.22U_0603_10V7K~D

1 2

PC155

0.22U_0402_6.3V 5K~D

PL24

+PWR_SRC

Design current 8A for +1.8V_SUSP
Peak current 10.1A for +1.8VSUSP
OCP point is 12.7A for +1.8VSUSP

C C

+1.8V_SUSP

1

1

+

+

PC71

PC70

2

2

330U_D2E_2.5VM~D

330U_D2E_2.5VM~D

B B

FBM-L11-453215-900LMAT_1812~D

1 2

PJP32

PAD-OPEN 4x4m

1 2

12

PC72

0.1U_0402_10V7K~D

1

1

PC55

2

10U_1206_25V6M~D

3

1 2

PL14

1.4UH_HMU1350-1R4PF_15A_20%~D

PC56

10U_1206_25V6M~D

2

0_0402_5%~D

12

PC57

0.1U_0603_25V7K~D

PR348

1 2

+1.8VSUSP_L

+1.8VSUSP/ +0.9V_DDR_VTT

PR193, PD20 are only used with the second-source MAX8632.

21

PD20

RB751V-40_SOD323~D

@

PR73

12

1_0603_5%~D

PR84

0_0402_5%~D @

12

PR200

1 2

12

100K_0402_1%~D

12

DDR2 Termination

+5V_SUS

12

PC62

4.7U_1206_10V7K~D

PU6

20

BST

18

DH

19

LX

21

DL

23

PGND1

16

VOUT

15

FB

1

TON

3

REF

PR202

48.7K_0402_1%~D

PR193

@

10_1206_5%~D

88550_AVDD

2

22

VDD

OVP/ UVP

ISL88550A_TQFN28~D

SKIP

ILIM

4

25

12

28

TP0

GND

24

12

26

17

VIN

AVDD

5

POK1

6

POK2

27

SHDN

7

STBY

13

VTTI

14

REFIN

11

PGND2

12

VTT

9

VTTS

10

VTTR

SS

GND

8

29

12

PC66

1000P_0402_50V7K~D

PC63

1U_0603_10V6K~D

12

PR213

0_0402_5%~D

PR204

20_0603_1%~D

12

PC77

0.1U_0402_10V7K~D

12

PC64
1U_0603_10V6K~D

+3.3V_SUS

PR194

100K_0402_1%~D

1 2

12

PC74

0.1U_0402_10V7K~D

+3.3V_RUN

PR195

@

100K_0402_1%~D

+1.8V_SUSP

12

1 2

SUSPWROK_5V 46

1

PC146
10U_0805_6.3V6M~D

2

SUSPWROK_1P8V 42

0.9V_DDR_PWRGD 42

PR212

0_0402_5%~D

12

+1.8V_SUSP

1

PC154

PC153

2

10U_0805_6.3V6M~D

10U_0805_6.3V6M~D

V_DDR_MCH_REF 10,16,17

RUN_ON 19 ,37,39 ,41,42,46,47,58

+0.9V_DDR_VTTP

1

1

2

Design current 1.05A for +0.9V_DDR_VTTP

PC157

Peak current 1.5A for +0.9V_DDR_VTTP

2

10U_0805_6.3V6M~D

PJP9
PAD-OPE N 4x4m

1 2

PJP10
PAD-OPE N 4x4m

+1.8V_SUSP

A A

+0.9V_DDR_VTTP

1 2

PJP11

1 2

PAD-OPE N 4x4m

5

+1.8V_SUS

+0.9V_DDR_VTT

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD

4

PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

2

Title

Size Doc u m en t N u m be r Re v

Date: Sheet

Compal Electronics, Inc.

+1.8VSUSP/ +0.9V_DDR_VT

LA-2792

1

48 70Tuesday, F e br ua ry 07, 2006

1.0

of

8

7

6

5

4

3

2

1

+CPU_PWR_SRC

H H

+CPU_PWR_SRC

+5V_RUN

PR228
10_0603_5%~D

G G

1 2

12

PC180

0.01U_0402_25V7K~D

+5V_RUN

PR233

1 2

10_0603_5%~D

F F

12

PC182

1U_0603_10V6K~D

GNDA_VCORE

12

PR290

0_0603_5%~D

IMVP6_PROCHOT#38

PR238

147K_0402_1%~D

12

0.01U_0402_16V7K~D
PR240

0_0402_5%~D

PR242

0_0402_5%~D

PR244

0_0402_5%~D

PR249

@

12

PR372

12

GNDA_VCORE

1 2

12

PC190

680P_0402_50V7K~D

1500P_0402_50V7K~D

12

PH1

@

12

PC187

CLK_ENABLE#6

12
12
12

RUNPWROK38,39,42,54

RUNPWROK38,39,42,54

VCCSENSE8

1 2

12

470KB_0402_5%_NCP15WM474J03RB~D

PR239

12

0_0402_5%~D

PR241

12

0_0402_5%~D

PR243

12

0_0402_5%~D

PR245

12

0_0402_5%~D

PR248

12

499_0402_1%~D

PR253

0_0402_5%~D

PC213

12

1000P_0402_50V7K~D

PR258

12

82.5K_0402_1%~D

PC197

12

12

PR259

PC214

PR287
0_0603_5%~D

1000P_0402_50V7K~D

2.21K_0402_1%~D

PC250

1000P_0402_50V7K~D

PR264

6.34K_0402_1%~D

PR252

0_0402_5%~D

12

PR254

0_0402_5%~D

12

12

12

GNDA_VCORE

12

12

E E

GNDA_VCORE

DPRSLPVR23

D D

@

PR284

0_0402_5%~D

VID08
VID18
VID28
VID38
VID48
VID58
VID68

H_DPRSTP#7,22

H_PSI#8

0_0402_5%~D

0_0402_5%~D

GNDA_VCORE

C C

VSSSENSE8

332_0402_1%~D

PR257

PC195

220P_0402_50V8J~D

1 2

B B

GNDA_VCORE

19

20

VSS

4

VR_TT#

3

RBIAS

5

NTC

6

SOFT

ISL6260CRZ-T_QFN40~D

28

VID0

29

VID1

30

VID2

31

VID3

32

VID4

33

VID5

34

VID6

37

DPRSTP#

36

DPRSLPVR

1

PSI#

2

PGD_IN

38

CLK_EN#

35

VR_ON

12

VSEN

13

RTN

11

VDIFF

10

FB

9

COMP

8

VW

41

GND

DROOP

14

PR267

10.5K_0402_1%

PC201

330P_0402_50V7K~D

18

VDD

PU11

12

12

VIN

DFB15VO

+3.3V_RUN

PR234

1.91K_0603_1%~D

1 2

39

40

3V3

PGOOD

PWM1

ISEN1

PWM2

ISEN2

FCCM

PWM3

ISEN3

OCSET

VSUM

16

VO

PR268

1K_0402_1%~D

IMVP_PWRGD 23,42

27

23

26

22

24

25

21

PR260

7

VSUM

17

12

PR263

4.53K_0402_1%~D

12

11.5K_0402_1%~D

12

12

PR261

2

2

1

1

PC191

0.33U_0603_10V7K
PC229

1

2

0.01U_0402_16V7K~D

PC215

2.43K_0402_1%~D

0.068U_0402_10V7K~D

12

12

PH2

PR266

15K_0402_1%~D

6.8KB_0603_5%_ERTJ1VR682J~D

12

PC178

1U_0603_10V6K~D

PU10

5

VCC

6

FCCM

2

PWM

3

GND

ISL6208CRZ-T_QFN8~D

BOOT
UGATE
PHASE
LGATE

1
8
7
4

PR229

0_0603_5%~D

0.22U_0603_10V7K~D

12

1 2

PC179

+5V_RUN

12

PC241

1U_0603_10V6K~D

5
6
2
3

PU16

VCC
FCCM
PWM
GND

ISL6208CRZ-T_QFN8~D

BOOT
UGATE
PHASE

LGATE

1
8
7
4

PR328

0_0603_5%~D

0.22U_0603_10V7K~D

12

1 2

+5V_RUN

12

PC196

PU13

5

VCC

1U_0603_10V6K~D

6

FCCM

2

PWM

3

GND

ISL6208CRZ-T_QFN8~D

BOOT
UGATE
PHASE
LGATE

PR262

0_0603_5%~D

1
8
7
4

PC198

0.22U_0603_10V7K~D

12

1 2

PC242

PQ42

IRF7821_SO8~D

PQ56

FDS7088SN3_SO8~D

PQ57

IRF7821_SO8~D

PQ60

FDS7088SN3_SO8~D

PQ50

IRF7821_SO8~D

PQ61

FDS7088SN3_SO8~D

D8D7D6D

S1S2S3G

3

D

S

1

D8D7D6D

S1S2S3G

3

1

D8D7D6D

S1S2S3G

3

D

S

1

12

PC249

5

0.1U_0603_25V7K~D

12

PC223

0.1U_0603_25V7K~D

12

12

PC175

PC224

4.7U_1206_25V6K~D

2200P_0402_50V7K~D

4

PHASE1

12

2

G

PC246

@

1500P_0805_50V7K

10K_0402_1%~D

1 2

PR231

7.68K_0805_1%~D

1 2

VSUM

5

4

12

12

PC239

PC194

PC240

0.1U_0603_25V7K~D

4.7U_1206_25V6K~D

2200P_0402_50V7K~D

PHASE2

D

G

S

12

2

PC247

@

1500P_0805_50V7K

1 2

VSUM

+CPU_PWR_SRC

5

4

12

PC272

@

PC192

4.7U_1206_25V6K~D

PHASE3

12

PC248

@

2

G

1500P_0805_50V7K

10K_0402_1%~D

1 2

PR270

7.68K_0805_1%~D

1 2

VSUM

1

1

PC270

PC176

@

2

2

10U_1206_25V6M~D

10U_1206_25V6M~D

PL29

0.45UH_MPC1040LR45_27A_20%~D

1

4
3

2

PR230

12

10K_0402_1%~D

PR331

7.68K_0805_1%~D

PC181

0.22U_0603_10V7K~D

+CPU_PWR_SRC

1

1

PC177

PC271

@

2

2

10U_1206_25V6M~D

10U_1206_25V6M~D

0.45UH_MPC1040LR45_27A_20%~D

4
3

PR330

1 2

1

1

12

PC227

PC193

2

2

10U_1206_25V6M~D

10U_1206_25V6M~D

0.1U_0603_25V7K~D

PL31

0.45UH_MPC1040LR45_27A_20%~D

1

4
3

2

PR269

PC200

0.22U_0603_10V7K~D

PL28

FBMA-L18-453215-900LMA90T_1812~D

1 2

PJP30

1 2

PAD-OPE N 4x4m

PJP31

1 2

PAD-OPE N 4x4m

PR232
10_0402_1%~D

1 2

12

VO

PL33

1
2

PR329

PC243

0.22U_0603_10V7K~D

12

10_0402_1%~D

1 2

VO

12

PC228

2200P_0402_50V7K~D

+VCC_CORE

PR271
10_0402_1%~D

1 2

12

VO

+PWR_SRC

+VCC_CORE

+VCC_CORE

PC260

1 2

A A

8

7

0.1U_0603_25V7K~D

GNDA_VCORE

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONF IDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVIS ION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INF ORMATION IT CON TAINS

6

5

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WR ITT EN CO NSE NT OF COMPAL ELECTRONICS, INC.

4

3

DELL CONFIDENTIAL/PROPRIETARY

Title

Size Doc u m en t N u m be r Re v

Date: Sheet

2

Compal Electronics, Inc.
+VCORE

LA-2792

49 70Tuesday, F e br ua ry 07, 2006

1

of

1.0

5

4

3

2

1

+DC_IN discharge path

+SDC_IN

PR138

0.01_2512_1%~D

+DC_IN

D D

1

PC99

2

10U_1206_25V6M~D

PR142
150K_0402_1%~D

1 2

@

PR337
0_0402_5%~D

1 2

1
2

4
3

FBMA-L18-453215-900LMA90T_1812~D

PL19

1 2

12

12

PC127

PC128

0.1U_0603_25V7K~D

2200P_0402_50V7K~D

CHAGER_SRC

LDO

12

ACAV_IN18,39,51

+5V_ALW

PR149

10K_0402_1%~D

12

PR341

15.8K_0402_1%~D

PC221

0.1U_0402_10V7K~D

12

PR150

10K_0402_1%~D

MAX8731_IINP

PR143
20K_0402_1%~D

12

C C

B B

A A

PC110

12

0.01U_0402_25V7K~D

Vin Detector
High 17.9 V
Low 17.24 V

PBAT_SMBCLK39,45

PBAT_SMBDAT39,45

5

12

PR342
806K_0402_1%~D

PR146

1 2

0_0402_5%~D

BAT_SEL#39

12

PC121

PR148

12

PC118

0.1U_0402_10V7K~D

PR361

1 2

0_0402_5%~D

12

4.7K_0402_5%~D

12

0.01U_0402_25V7K~D

MAX8731_REF

PC254

12

12

PC119

PC212

0.01U_0402_25V7K~D

0.01U_0402_25V7K~D

12

PR362

301K_0402_1%~D

12

12

PR363

59K_0402_1%~D

0.01U_0402_25V7K~D

12

PR364

27.4K_0402_1%~D

4

1U_0805_25V4Z~D

PR335

1 2

0_0402_5%~D

PC122

1U_0603_10V6K~D

12

PC255

PC102

12

100P_0402_50V8K

12

MAX8731_IINP

MAX8731_REF

PC120

PC256

PR336
0_0402_5%~D

1 2

12

0.1U_0402_10V7K~D

2

IN-

3

IN+

12

100P_0402_50V8K

+5V_ALW

PU8

22

DCIN

2

ACIN

13

ACOK

11

VDD

10

SCL

9

SDA

14

BATSEL

8

IINP

6

CCV

5

CCI

4

CCS

3

REF

7

DAC

12

GND

29

GND

4.32M_0402_1%~D

1 2

4

G

O

P

8

PC257

1

27

28

26

VCC

GND

CSSP

CSSN

BST

LDO

DHI

DLO

PGND

CSIP
CSIN
FBSA
FBSB

MAX8731_TQFN28~D

PR365

PU19A
LM393DR_SO8~D

1

12

100P_0402_50V8K

12

PC258

0.01U_0402_25V7K~D

THIS SHEET OF EN GINEE RING D RAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

0_0603_5%~D

25

1 2

21

24
23

LX

1

2

20

19
18

17
15
16

@

3

PR275

12

PC203

PR360

12

1 2

100_0402_5%~D

1

2

12

12

0.1U_0603_25V7K~D

PR368

2

G

LDO

1_0603_1%~D

PC253
220P_0402_50V7K~D

PC266

0.01U_0603_50V7K~D

+5V_ALW +3.3V_ALW

PR366

100K_0402_1%~D

PC259

10P_0402_50V8J~D

PD40

PR367

1U_0603_10V6K~D

PR274
33_0603_1%~D

1 2

PC204

1U_0603_10V6K~D

2 1

RB751V_SOD323~D

1 2

+VCHGR

12

100K_0402_5%~D

13

D

PQ81

S

RHU002N06_SOT323

PC202

1 2

ADAPT_OC 38

578

3 6

241

12

PC267

3300PF_0402_50V7K~D

5

@

PQ75

+VCHGR_B +VCHGR_L

578

+5V_ALW

5

IN+

6

IN-

D8D7D6D

SI4800BDY-T1_SO8~D

3 6

241

8

4

PQ79

S1S2S3G

IRF7821_SO8~D

4

5.6U_HMU1356-5R6_8.8A_20%~D

PQ76
SI4810BDY_SO8~D

P

7

O

G

PU19B
LM393DR_SO8~D

PL20

PC103

2200P_0402_50V7K~D

12

12

12

PC104

0.1U_0603_25V7K~D

PR145

0.01_2512_1%~D

1
2

1 2

1K_0603_1%~D

1

2

PR373

+5V_ALW

21

PD54

1SS355_SOD323~D

1

1

2

PC106

PC105

10U_1206_25V6M~D

4
3

12

PC112

0.1U_0603_25V7K~D

10U_1206_25V6M~D

2

@

+VCHGR

PC113

10U_1206_6.3V7K~D

1

2

PC273

10U_1206_25V6M~D

1

2

PC114

10U_1206_6.3V7K~D

DELL CONFIDENTIAL/PROPRIETARY

Title

Size Document Number Rev

2

Date: Sheet

Compal Electronics, Inc.
Charger

LA-2792

50 70Tuesday, Feb ru ar y 07, 2006

1

1.0

of

5

4

3

2

1

+DC_IN discharge path

PQ62

SI4835BDY_SO8~D

8

D D

PQ65

D2

S2

G2

D2

S1

D1
D1

G1

FDS4935_SO8~D

12

0.1U_0603_25V7K~D

100K_0402_5%~D

12

PQ71

4

PR321

147K_0402_1%~D

1 2

8

P

IN+

O

IN-

G

4

CHG_SBAT

1

CHG_SBATT_N

2
3
4

PR310

100K_0402_5%~D

12

PC234

0.1U_0603_25V7K~D

1 2

CHG_SBATT_N

PC235

1 2

PR313

12

CHG_PBAT

36
2
1

PC237

1 2

PD51

0.1U_0603_25V7K~D

7

1

LM393DR_SO8~D
PU14B

RB715F_SOT323

CHG_PBATT_N

2
3

3 6
2
1

8
7

PR309

10K_0402_5%~D

PR312

10K_0402_5%~D

SI4835BDY_SO8~D

5
7

8

+3.3V_ALW

4

6
5

PBATT+

5
6

+VCHGR

CHG_SBAT_N

13

D

PQ67

CHG_SBATT38

C C

CHG_PBATT38

B B

SBATT+

PC236

+3.3V_ALW

PU15

5

TC7SH32FU_SSOP5~D

2

A A

SBAT_LOW38
SBAT_PRES#38,45

P

I0

O

1

I1

G

3

5

@

4

RHU002N06_SOT323

2

PQ74

0.1U_0603_25V7K~D

G

2

RHU002N06_SOT323

G

S

S

G

RHU002N06_SOT323

2

PQ68

D

1 3

CHG_PBAT_N

+VCHGR

1 2

13

D

S

PR323

1 2

42.2K_0402_1%~D
PR324

10K_0402_5%~D

1 2

1 2

PR325

100K_0402_5%~D

PR326

1 2

32.4K_0402_1%~D

ACAV_IN18,39,50

PBATT+

PQ72

4

SI4835BDY_SO8~D

5
7

8

PR314

470K_0402_5%~D

1 2

PR319

47K_0402_1%~D

1 2

PR322

100K_0402_5%~D

1 2

+3.3V_ALW

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3
2

3

PBATT+

IN+
IN-

@

100K_0402_5%~D

SBATT+

12

PR315

470K_0402_5%~D

PU14A

8

LM393DR_SO8~D

P

1

O

G

4

PR320

+SDC_IN

2

PR308

G

12

PQ69

SI4835BDY_SO8~D

1
2
3 6

4

PR316

47K_0402_1%~D

1 2

12

PR317

10K_0402_5%~D

13

D

2

G

12

S

470K_0402_5%~D

13

D

PQ63
RHU002N06_SOT323

S

8
7

5

PQ73
RHU002N06_SOT323

PR305

10K_0402_5%~D

2

G

2
3

2
3

1 2
13

D

S

PD48

RB715F_SOT323

PD50

RB715F_SOT323

2

7
5

PR306

10K_0402_5%~D

8
7

5

SBAT_G

1

8
7

5

PBAT_G

1

2 1

SI4835BDY_SO8~D

B540C~D

2 1

SI4835BDY_SO8~D

PQ64
RHU002N06_SOT323

12

PD47

B540C~D

PQ66

PR311

PD49

PQ70

PR318

1
2
36

4

PR307

100K_0402_5%~D

12

1
2
36

4

1 2

33K_0402_5%~D

1
2
36

4

1 2

33K_0402_5%~D

DELL CONFIDENTIAL/PROPRIETARY

Title

Size Document Number Rev

Date: Sheet

+PWR_SRC

12

PC232

PC233

2200P_0402_50V7K~D

+PWR_SRC

Selector

LA-2792

12

0.1U_0603_25V7K~D

51 70Tuesday, Fe b r u a r y 07, 2006

1

1.0

of

5

PEG_MTX_GRX_P0
PEG_MTX_GRX_N0
PEG_MTX_GRX_P1
PEG_MTX_GRX_N1
PEG_MTX_GRX_P2
PEG_MTX_GRX_N2

R2133

PEG_MTX_GRX_P3
PEG_MTX_GRX_N3
PEG_MTX_GRX_P4
PEG_MTX_GRX_N4
PEG_MTX_GRX_P5
PEG_MTX_GRX_N5
PEG_MTX_GRX_P6
PEG_MTX_GRX_N6
PEG_MTX_GRX_P7
PEG_MTX_GRX_N7
PEG_MTX_GRX_P8
PEG_MTX_GRX_N8
PEG_MTX_GRX_P9
PEG_MTX_GRX_N9
PEG_MTX_GRX_P10
PEG_MTX_GRX_N10
PEG_MTX_GRX_P11
PEG_MTX_GRX_N11
PEG_MTX_GRX_P12
PEG_MTX_GRX_N12
PEG_MTX_GRX_P13
PEG_MTX_GRX_N13
PEG_MTX_GRX_P14
PEG_MTX_GRX_N14
PEG_MTX_GRX_P15
PEG_MTX_GRX_N15

PEG_MRX_GTX_C_P0
PEG_MRX_GTX_C_N0
PEG_MRX_GTX_C_P1
PEG_MRX_GTX_C_N1
PEG_MRX_GTX_C_P2
PEG_MRX_GTX_C_N2
PEG_MRX_GTX_C_P3
PEG_MRX_GTX_C_N3
PEG_MRX_GTX_C_P4
PEG_MRX_GTX_C_N4
PEG_MRX_GTX_C_P5
PEG_MRX_GTX_C_N5
PEG_MRX_GTX_C_P6
PEG_MRX_GTX_C_N6
PEG_MRX_GTX_C_P7
PEG_MRX_GTX_C_N7
PEG_MRX_GTX_C_P8
PEG_MRX_GTX_C_N8
PEG_MRX_GTX_C_P9
PEG_MRX_GTX_C_N9
PEG_MRX_GTX_C_P10
PEG_MRX_GTX_C_N10
PEG_MRX_GTX_C_P11
PEG_MRX_GTX_C_N11
PEG_MRX_GTX_C_P12
PEG_MRX_GTX_C_N12
PEG_MRX_GTX_C_P13
PEG_MRX_GTX_C_N13
PEG_MRX_GTX_C_P14
PEG_MRX_GTX_C_N14
PEG_MRX_GTX_C_P15
PEG_MRX_GTX_C_N15

CLK_PCIE_VGA
CLK_PCIE_VGA#

1 2

R2131

0_0402_5%~D

XTALIN

XTALOUT
XTALOUTBUFF

XTALSSIN_R

PEG_MTX_GRX_P[0:15]12
PEG_MTX_GRX_N[0:15]12

D D

C C

B B

PEG_MRX_GTX_P[0:15]12
PEG_MRX_GTX_N[0:15]12

PEG_MRX_GTX_P0
PEG_MRX_GTX_N0

PEG_MRX_GTX_P1
PEG_MRX_GTX_N1

PEG_MRX_GTX_P2
PEG_MRX_GTX_N2

PEG_MRX_GTX_P3
PEG_MRX_GTX_N3

PEG_MRX_GTX_P4
PEG_MRX_GTX_N4

PEG_MRX_GTX_P5
PEG_MRX_GTX_N5

PEG_MRX_GTX_P6
PEG_MRX_GTX_N6

PEG_MRX_GTX_P7
PEG_MRX_GTX_N7

PEG_MRX_GTX_P8
PEG_MRX_GTX_N8

PEG_MRX_GTX_P9
PEG_MRX_GTX_N9

PEG_MRX_GTX_P10
PEG_MRX_GTX_N10

PEG_MRX_GTX_P11
PEG_MRX_GTX_N11

PEG_MRX_GTX_P12
PEG_MRX_GTX_N12

PEG_MRX_GTX_P13
PEG_MRX_GTX_N13

PEG_MRX_GTX_P14
PEG_MRX_GTX_N14

PEG_MRX_GTX_P15
PEG_MRX_GTX_N15

C2205

1

C2204

2

@

18P_0402_50V8J~D

PEG_MTX_GRX_P[0:15]
PEG_MTX_GRX_N[0:15]
PEG_MRX_GTX_P[0:15]
PEG_MRX_GTX_N[0:15]

12

C20030.1U_0402_10V7K~D

12

C20050.1U_0402_10V7K~D

12

C20070.1U_0402_10V7K~D

12

C20090.1U_0402_10V7K~D

12

C20110.1U_0402_10V7K~D

12

C20130.1U_0402_10V7K~D

12

C20150.1U_0402_10V7K~D

12

C20170.1U_0402_10V7K~D

12

C20190.1U_0402_10V7K~D

12

C20210.1U_0402_10V7K~D

12

C20230.1U_0402_10V7K~D

12

C20250.1U_0402_10V7K~D

12

C20270.1U_0402_10V7K~D

12

C20290.1U_0402_10V7K~D

12

C20310.1U_0402_10V7K~D

12

C20330.1U_0402_10V7K~D

PLTRST_DELAY#23

@

18P_0402_50V8J~D

12

Y2001

@

4

GND

1

IN

27MHz_16PF_6P27000126~D

3

OUT

2

GND

XTALSSIN57

CLK_NVSS_27M6

C20020.1U_0402_10V7K~D

12

C20040.1U_0402_10V7K~D

12

C20060.1U_0402_10V7K~D

12

C20080.1U_0402_10V7K~D

12

C20100.1U_0402_10V7K~D

12

C20120.1U_0402_10V7K~D

12

C20140.1U_0402_10V7K~D

12

C20160.1U_0402_10V7K~D

12

C20180.1U_0402_10V7K~D

12

C20200.1U_0402_10V7K~D

12

C20220.1U_0402_10V7K~D

12

C20240.1U_0402_10V7K~D

12

C20260.1U_0402_10V7K~D

12

C20280.1U_0402_10V7K~D

12

C20300.1U_0402_10V7K~D

12

C20320.1U_0402_10V7K~D

12

CLK_NV_27M6

PEG_MRX_GTX_C_P0
PEG_MRX_GTX_C_N0

PEG_MRX_GTX_C_P1
PEG_MRX_GTX_C_N1

PEG_MRX_GTX_C_P2
PEG_MRX_GTX_C_N2

PEG_MRX_GTX_C_P3
PEG_MRX_GTX_C_N3

PEG_MRX_GTX_C_P4
PEG_MRX_GTX_C_N4

PEG_MRX_GTX_C_P5
PEG_MRX_GTX_C_N5

PEG_MRX_GTX_C_P6
PEG_MRX_GTX_C_N6

PEG_MRX_GTX_C_P7
PEG_MRX_GTX_C_N7

PEG_MRX_GTX_C_P8
PEG_MRX_GTX_C_N8

PEG_MRX_GTX_C_P9
PEG_MRX_GTX_C_N9

PEG_MRX_GTX_C_P10
PEG_MRX_GTX_C_N10

PEG_MRX_GTX_C_P11
PEG_MRX_GTX_C_N11

PEG_MRX_GTX_C_P12
PEG_MRX_GTX_C_N12

PEG_MRX_GTX_C_P13
PEG_MRX_GTX_C_N13

PEG_MRX_GTX_C_P14
PEG_MRX_GTX_C_N14

PEG_MRX_GTX_C_P15
PEG_MRX_GTX_C_N15

CLK_PCIE_VGA6
CLK_PCIE_VGA#6

PLTRST_DELAY#

XTALOUTBUFF57

@

1 2

0_0402_5%~D

1 2

R2132 0_0402_5%~D

4

AF1
AG2
AG3
AG4
AF4
AF5
AG6
AG7
AF7
AF8

AG9
AG10
AF10
AF11
AG12
AG13
AG15
AG16
AF16
AF17
AG18
AG19
AF19
AF20
AG21
AG22
AF22
AF23
AG24
AG25
AG26
AF27

AD5

AD6

AE6

AE7

AD7

AC7

AE9
AE10
AD10
AC10
AE12
AE13
AD13
AC13
AC15
AD15
AE15
AE16
AC18
AD18
AE18
AE19
AC21
AD21
AE21
AE22
AD22
AD23
AF25
AE25
AE24
AD24

AE3

AE4

AC6

U2001A

PEX_RX0
PEX_RX0_N
PEX_RX1
PEX_RX1_N
PEX_RX2
PEX_RX2_N
PEX_RX3
PEX_RX3_N
PEX_RX4
PEX_RX4_N
PEX_RX5
PEX_RX5_N
PEX_RX6
PEX_RX6_N
PEX_RX7
PEX_RX7_N
PEX_RX8
PEX_RX8_N
PEX_RX9
PEX_RX9_N
PEX_RX10
PEX_RX10_N
PEX_RX11
PEX_RX11_N
PEX_RX12
PEX_RX12_N
PEX_RX13
PEX_RX13_N
PEX_RX14
PEX_RX14_N
PEX_RX15
PEX_RX15_N

PEX_TX0
PEX_TX0_N
PEX_TX1
PEX_TX1_N
PEX_TX2
PEX_TX2_N
PEX_TX3
PEX_TX3_N
PEX_TX4
PEX_TX4_N
PEX_TX5
PEX_TX5_N
PEX_TX6
PEX_TX6_N
PEX_TX7
PEX_TX7_N
PEX_TX8
PEX_TX8_N
PEX_TX9
PEX_TX9_N
PEX_TX10
PEX_TX10_N
PEX_TX11
PEX_TX11_N
PEX_TX12
PEX_TX12_N
PEX_TX13
PEX_TX13_N
PEX_TX14
PEX_TX14_N
PEX_TX15
PEX_TX15_N

PEX_REFCLK
PEX_REFCLK_N

PEX_RST_N

B1

XTALIN

C2

XTALOUT

C3

XTALOUTBUFF

C1

XTALSSIN

Part 1 of 5

MIOBD0
MIOBD1
MIOBD2
MIOBD3
MIOBD4
MIOBD5
MIOBD6
MIOBD7

DVO / GPIO

MIOBD8

MIOBD9
MIOBD10
MIOBD11

MIOB_HSYNC
MIOB_VSYNC

MIOB_DE

MIOB_CTL3

MIOB_CLKIN

MIOB_CLKOUT

MIOB_CLKOUT_N

MIOB_VREF

PCI EXPRESS

DACA_HSYNC
DACA_VSYNC

DACA_RED

DACA_BLUE

DACA_GREEN

DACA_IDUMP

DACA_RSET
DACA_VREF

DACB_HSYNC
DACB_VSYNC

DACB_RED

DACB_BLUE

DACsI2C

DACB_GREEN

DACB_IDUMP

DACB_RSET
DACB_VREF

I2CA_SCL
I2CA_SDA
I2CB_SCL
I2CB_SDA
I2CC_SCL

I2CC_SDA

I2CH_SCL

I2CH_SDA

IFPAB_VPROBE

IFPCD_VPROBE

JTAG_TCK

JTAG_TDI
JTAG_TDO
JTAG_TMS

CLK

JTAG_TRST_N

TEST

TESTMODE

PEX_TSTCLK_OUT

PEX_TSTCLK_OUT_N

G72M-V-N-A2_BGA533~D

GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8

GPIO9
GPIO10
GPIO11
GPIO12

3

A9
D9
A10
B10
C10
C12
B12
A12
A13
B13
B15
A15
B16

G2
G3
J2
J1
K4
K1
M2
M1
N1
N2
N3
R3

G4
F1
G1
F2

R2
K2
K3

J4

AD4
AC4
AE1
AD2
AD1
U9
AD3

AB4

E6
F5
F4
D5
E4
L9
D6

E7

D10
E10
F9
F10
E9
D8
C7
B7

N6
M5

AE27
AD27
AE26
AD26
AD25
D7

AF13
AF14

DVI_DETECT
BIA_PWM

ENVDD
PANEL_BKEN
GFX_CORE_CNTRL

RAM_CFG0
RAM_CFG1

PCI_DEVID2
PCI_DEVID0
PCI_DEVID1

RAM_CFG2
RAM_CFG3

PCI_DEVID3

R2127

1 2

10K_0402_5%~D

VGA_HSYNC
VGA_VSYNC
VGA_RED
VGA_BLU
VGA_GRN

R2009 124_0402_1%~D

1 2

DACAVREF

1 2

C2001 0.01U_0402_16V7K~D

TV_C
TV_CVBS
TV_Y

DACB_RSET
DACBVREF

R2010 124_0402_1%~D
C2174 0.01U_0402_16V7K~D

VGADDCCLK
VGADDCDAT
DVI_SCLK
DVI_SDATA
LCD_DDCCLK
LCD_DDCDATA
I2CH_SCL
I2CH_SDA

T2020 PAD
T2021 PAD

12

12

R2125
10K_0402_5%~D

R116

10K_0402_5%~D

DVI_DETECT 36
BIA_PWM 19,39

ENVDD 19
PANEL_BKEN 19
GFX_CORE_CNTRL 58

RAM_CFG0 57
RAM_CFG1 57

PCI_DEVID2 57
PCI_DEVID0 57
PCI_DEVID1 57

T2026 PAD

RAM_CFG2 57
RAM_CFG3 57

PCI_DEVID3 57

VGA_HSYNC 20
VGA_VSYNC 20
VGA_RED 20,36
VGA_BLU 20,36
VGA_GRN 20,36

TV_C 36
TV_CVBS 36
TV_Y 36

1 2
1 2

DVI_SCLK 36
DVI_SDATA 36
LCD_DDCCLK 19
LCD_DDCDATA 19

+3.3V_RUN

S

<---CRT
<---DVI
<---SVIDEO

2

G

1 3

D

S

Q2008
2N7002W-7-F_SOT323~D

G

2

13

D

@

Q25
2N7002W-7-F_SOT323~D

12

R2100

4.7K_0402_5%~D

2

THERMTRIP_VGA# 18

LCD_DDCCLK
LCD_DDCDATA
DVI_SCLK
DVI_SDATA

I2CH_SCL
I2CH_SDA

1

+3.3V_RUN

1 2

R2002 2.2K_0402_5%~D

1 2

R2003 2.2K_0402_5%~D

1 2

R2005 2.2K_0402_5%~D

1 2

R2006 2.2K_0402_5%~D

1 2

R2128 10K_0402_5%~D

1 2

R2129 10K_0402_5%~D

+3.3V_RUN+3.3V_RUN

12

R2101

2

1 3

D

G

DAT_DDC220,36CLK_DDC220,36

DAT_DDC2VGADDCCLKCLK_DDC2

4.7K_0402_5%~D

S

Q2009
2N7002W-7-F_SOT323~D

VGADDCDAT

A A

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

NVG72M PCIE,GPIO,CLK

LA-2792

52 70Tuesday, Fe b r u a r y 07, 2006

1

1.0

of

5

4

3

2

1

FBAD[0:63]

FBAA[0:11]

FBBA[2:5]

DQSA[0:7]

D D

AB23
AB24

AB22
AC24
AC22
AA23
AA22

AA24
AA27
AA26
AB25
AB26
AB27
AA25

W25

U2001B

A26

FBAD0

C24

FBAD1

B24

FBAD2

A24

FBAD3

C22

FBAD4

A25

FBAD5

B25

FBAD6

D23

FBAD7

G22

FBAD8

J23

FBAD9

E24

FBAD10

F23

FBAD11

J24

FBAD12

F24

FBAD13

G23

FBAD14

H24

FBAD15

D16

FBAD16

E16

FBAD17

D17

FBAD18

F18

FBAD19

E19

FBAD20

E18

FBAD21

D20

FBAD22

D19

FBAD23

A18

FBAD24

B18

FBAD25

A19

FBAD26

B19

FBAD27

D18

FBAD28

C19

FBAD29

C16

FBAD30

C18

FBAD31

N26

FBAD32

N25

FBAD33

R25

FBAD34

R26

FBAD35

R27

FBAD36

T25

FBAD37

T27

FBAD38

T26

FBAD39
FBAD40

Y24

FBAD41
FBAD42
FBAD43
FBAD44
FBAD45
FBAD46
FBAD47

T24

FBAD48

T23

FBAD49

R24

FBAD50

R23

FBAD51

R22

FBAD52

T22

FBAD53

N23

FBAD54

P24

FBAD55
FBAD56
FBAD57
FBAD58
FBAD59
FBAD60
FBAD61
FBAD62
FBAD63

FBAD0
FBAD1
FBAD2
FBAD3
FBAD4
FBAD5
FBAD6
FBAD7
FBAD8
FBAD9
FBAD10
FBAD11
FBAD12
FBAD13
FBAD14
FBAD15
FBAD16
FBAD17
FBAD18
FBAD19
FBAD20
FBAD21
FBAD22
FBAD23
FBAD24
FBAD25
FBAD26

C C

B B

FBAD27
FBAD28
FBAD29
FBAD30
FBAD31
FBAD32
FBAD33
FBAD34
FBAD35
FBAD36
FBAD37
FBAD38
FBAD39
FBAD40
FBAD41
FBAD42
FBAD43
FBAD44
FBAD45
FBAD46
FBAD47
FBAD48
FBAD49
FBAD50
FBAD51
FBAD52
FBAD53
FBAD54
FBAD55
FBAD56
FBAD57
FBAD58
FBAD59
FBAD60
FBAD61
FBAD62
FBAD63

DQMA#[0:7]

Part 2 of 5

MEMORY INTERFACE

G72M-V-N-A2_BGA533~D

FBA_CMD0
FBA_CMD1
FBA_CMD2
FBA_CMD3
FBA_CMD4
FBA_CMD5
FBA_CMD6
FBA_CMD7
FBA_CMD8

FBA_CMD9
FBA_CMD10
FBA_CMD11
FBA_CMD12
FBA_CMD13
FBA_CMD14
FBA_CMD15
FBA_CMD16
FBA_CMD17
FBA_CMD18
FBA_CMD19
FBA_CMD20
FBA_CMD21
FBA_CMD22
FBA_CMD23
FBA_CMD24
FBA_CMD25
FBA_CMD26

FBADQM0
FBADQM1
FBADQM2
FBADQM3
FBADQM4
FBADQM5
FBADQM6
FBADQM7

FBADQS_RN0
FBADQS_RN1
FBADQS_RN2
FBADQS_RN3
FBADQS_RN4
FBADQS_RN5
FBADQS_RN6
FBADQS_RN7

FBADQS_WP0
FBADQS_WP1
FBADQS_WP2
FBADQS_WP3
FBADQS_WP4
FBADQS_WP5
FBADQS_WP6
FBADQS_WP7

FB_VREF

FBA_CLK0

FBA_CLK0_N

FBA_CLK1

FBA_CLK1_N

FBA_REFCLK

FBA_REFCLK_N

FBA_DEBUG

FBAD[0:63] 56

FBAA[0:11] 56

FBBA[2:5] 56

DQSA[0:7] 56

DQMA#[0:7] 56

G27
D25
F26
F25
G25
J25
J27
M26
C27
C25
D24
N27
G24
J26
M27
C26
M25
D26
D27
K26
K25
K24
F27
K27
G26
B27
N24

D21
F22
F20
A21
V27
W22
V22
V24

A22
E22
F21
B21
V26
W23
V23
W27

B22
D22
E21
C21
V25
W24
U24
W26

A16
L24

K23
M22
N22
M23
M24
K22

FBAA3
FBAA0
FBAA2
FBAA1
FBBA3
FBBA4
FBBA5
FBACS1#
FBACS0#
FBAWE#
FBA_BA0
FBA_CKE

FBBA2
FBARAS#

FBAA11
FBAA10
FBA_BA1
FBAA8
FBAA9
FBAA6
FBAA5
FBAA7
FBAA4
FBACAS#

DQMA#0
DQMA#1
DQMA#2
DQMA#3
DQMA#4
DQMA#5
DQMA#6
DQMA#7

DQSA0
DQSA1
DQSA2
DQSA3
DQSA4
DQSA5
DQSA6
DQSA7

FBA_VREF1

CLKA0
CLKA0#
CLKA1
CLKA1#

FBACS1# 56
FBACS0# 56
FBAWE# 56
FBA_BA0 56

FBARAS# 56

FBA_BA1 56

FBACAS# 56

10mil

CLKA0 56
CLKA0# 56
CLKA1 56
CLKA1# 56

12

R2001
10K_0402_5%~D

FBA_CKE 56

10mil

1

2

C2036

0.022U_0402_16V7K~D

+1.8V_RUN

12

R2021
10K_0402_1%~D

12

R2022
10K_0402_1%~D

LCD_ACLK+19
LCD_ACLK-19
LCD_A0+19
LCD_A0-19
LCD_A1+19
LCD_A1-19
LCD_A2+19
LCD_A2-19

LCD_BCLK+19
LCD_BCLK-19
LCD_B0+19
LCD_B0-19
LCD_B1+19
LCD_B1-19
LCD_B2+19
LCD_B2-19

DVI_CLK+36
DVI_CLK-36
DVI_TX0+36
DVI_TX0-36
DVI_TX1+36
DVI_TX1-36
DVI_TX2+36
DVI_TX2-36

LCD_ACLK+
LCD_ACLK­LCD_A0+
LCD_A0­LCD_A1+
LCD_A1­LCD_A2+
LCD_A2-

LCD_BCLK+
LCD_BCLK­LCD_B0+
LCD_B0­LCD_B1+
LCD_B1­LCD_B2+
LCD_B2-

R2018

1K_0402_5%~D

DVI_CLK+
DVI_CLK­DVI_TX0+
DVI_TX0­DVI_TX1+
DVI_TX1­DVI_TX2+
DVI_TX2-

R2019

1K_0402_5%~D

U2001C

T4

IFPA_TXC

U4

IFPA_TXC_N

N4

IFPA_TXD0

N5

IFPA_TXD0_N

R5

IFPA_TXD1

R4

IFPA_TXD1_N

T5

IFPA_TXD2

T6

IFPA_TXD2_N

R6

IFPA_TXD3

P6

IFPA_TXD3_N

W5

IFPB_TXC

W6

IFPB_TXC_N

W3

IFPB_TXD4

W2

IFPB_TXD4_N

AA2

IFPB_TXD5

AA3

IFPB_TXD5_N

AB1

IFPB_TXD6

AA1

IFPB_TXD6_N

AB3

IFPB_TXD7

AB2

IFPB_TXD7_N

U6

12

IFPAB_RSET

V1

IFPC_TXC

W1

IFPC_TXC_N

T1

IFPC_TXD0

R1

IFPC_TXD0_N

T3

IFPC_TXD1

T2

IFPC_TXD1_N

V2

IFPC_TXD2

V3

IFPC_TXD2_N

J3

IFPCD_RSET

12

Part 3 of 5

LVDS/TMDS

MIO_A_D0
MIO_A_D1
MIO_A_D2
MIO_A_D3
MIO_A_D4
MIO_A_D5
MIO_A_D6
MIO_A_D7
MIO_A_D8
MIO_A_D9

MIO_A_D10

NC

MIO_A_HSYNC

NC_0
NC_1
NC_2
NC_3

BUFRST_N

STEREO

SWAPRDY

THERMDN
THERMDP

GENERAL

ROM_SCLK

ROM_SI

DVI_CLK+
DVI_CLK­DVI_TX0+

DVI_TX0-

DVI_TX1+

DVI_TX1­DVI_TX2+
DVI_TX2-

ROM_SO

ROMCS_N

SERIAL

G72M-V-N-A2_BGA533~D

R2092 49.9_0402_1%~D
R2093 49.9_0402_1%~D
R2094 49.9_0402_1%~D
R2095 49.9_0402_1%~D
R2096 49.9_0402_1%~D
R2097 49.9_0402_1%~D
R2098 49.9_0402_1%~D
R2099 49.9_0402_1%~D

A2
B3
A3
D4
A4
B4
B6
P4
C6
G5
V4

C4

D12
E12
F12
C13

A6

F7
A7

C9
B9

D2
F3
D3
D1

PEX_PLL_EN_TERM100
SUB_VENDOR

3GIO_ADR_0
3GIO_ADR_1

3GIO_ADR_2

MIOA_HSYNC

+3.3V_RUN

R2017

10K_0402_5%~D

VGA_THERMDN
VGA_THERMDP

IFPC_IOVDD

12
12
12
12
12
12
12
12

12

R2034

12

10K_0402_5%~D

1 2

C2176 0.01U_0402_16V7K~D

1 2

C2177 0.01U_0402_16V7K~D

1 2

C2178 0.01U_0402_16V7K~D

1 2

C2179 0.01U_0402_16V7K~D

PEX_PLL_EN_TERM100 57
SUB_VENDOR 57

3GIO_ADR_0 57
3GIO_ADR_1 57

3GIO_ADR_2 57

Strap for G72

VGA_THERMDN 18
VGA_THERMDP 18

T2001
PAD

A A

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

NVG72M Memory Interface

LA-2792

53 70Tuesday, Fe b r u a r y 07, 2006

1

1.0

of

5

4

3

2

1

+1.2VRUN

1

2

10U_0805_10V4Z~D

1

C2056

2

10U_0805_10V4Z~D

L2002

4.7U_0603_6.3V4Z~D

DACA_VDD

C2122

470P_0402_50V7K~D

DACB_VDD

C2126

470P_0402_50V7K~D

+1.2VRUN

12

+1.8V_RUN

L2127

1 2

1 2

+3.3V_RUN

+2.5V_RUN

+2.5V_RUN

L2128

L2009

BLM18AG121SN1D_0603~D

L2010

BLM18AG121SN1D_0603~D

C2075

1

2

12

12

C2063

0.01U_0402_16V7K~D

0.01U_0402_16V7K~D

C2120

4700P_0402_25V7K~D

C2124

4700P_0402_25V7K~D

PEX_PLLAVDD

1

C2064

2

C2076

1U_0603_10V4Z~D

1

2

1

2

BLM18PG181SN1_0603~D

1

1

2

2

0.1U_0402_10V7K~D

1

2

1

C2121

2

2.2U_0603_6.3V6K~D

1

C2125

2

2.2U_0603_6.3V6K~D

C2065

1

2

1

2

DELL CONFIDENTIAL/PROPRIETARY

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

NVG72M Power

LA-2792

54 70Tuesday, Fe b r u a r y 07, 2006

1

of

1.0

W17
W18
AB10
AB11
AB14
AB15
AB20
AB21
AA4
AB5
AB6
AB7
AB8
AB9
AB12
AB13
AB16
AB17
AB18
AB19
AC9
AC11
AC12
AC16
AC17
AC19
AC20

Y6
AA5

K5
K6
L6

J5

F6
G6
J6

W4
Y4
L4

V5
M4
AE2

F8

H4
D13
D14
D15

D11

1808mA

PEX_PLLAVDD
PEX_PLLDVDD

MIOBCAL_PD_VDDQ

IFPAB_IOVDD
IFPC_IOVDD

40mA

IFPAB_PLLVDD

40mA

IFPCD_PLLVDD
DACA_VDD

DACB_VDD

PLLVDD
FBA_PLLAVDD

R2032

40.2_0402_1%~D

BLM18AG121SN1D_0603~D

1

C2037

2

0.022U_0402_16V7K~D

1

C2098

0.1U_0402_10V7K~D

2

70mA
140mA

12

L2012

12

C2050

0.1U_0402_10V7K~D

C2038

0.022U_0402_16V7K~D

180mA

20mA

+1.8V_RUN

1

C2051

2

1

C2039

2

T2003
PAD

+3.3V_RUN

1

C2175

2

0.1U_0402_16V4Z~D

1

C2052

2

2

0.1U_0402_10V7K~D

1

2

0.1U_0402_10V7K~D

C2069

1

2

C2040

1

2

470P_0402_50V7K~D

C2214

470P_0402_50V7K~D

0.1U_0402_10V7K~D

1

2

0.1U_0402_10V7K~D

1

C2127

0.1U_0402_10V7K~D

2

C2070

C2203

1

C2215

2

4.7U_0603_6.3V4Z~D

2

C2053

4.7U_0603_6.3V4Z~D

C2085

470P_0402_50V7K~D

C2041

0.1U_0402_10V7K~D

1

2

0.1U_0402_10V7K~D

+3.3V_RUN

1

2

1

2

470P_0402_50V7K~D

1

2

C2042

2

2

4.7U_0603_6.3V4Z~D

1

C2054

2

0.1U_0402_10V7K~D

L2004

1 2

BLM18AG121SN1D_0603~D

1

C2071

2

4700P_0402_25V7K~D

1

C2086

2

4.7U_0603_6.3V4Z~D

1

C2201

C2202

2

4.7U_0603_6.3V4Z~D

IFPC_IOVDD

C2057

1

C2055

2

4.7U_0603_6.3V4Z~D

BLM18AG121SN1D_0603~D

1

C2087

2

4700P_0402_25V7K~D

1

BLM18AG121SN1D_0603~D

2

4700P_0402_25V7K~D

1

1

1

+VDD_CORE

+3.3V_RUN

1

2

1U_0603_10V4Z~D

1

2

0.022U_0402_16V7K~D

1

2

0.1U_0402_10V7K~D

C2043

C2073

C2072

C2091

C2105

C2117

1

2

C2044

10U_0805_4VAM~D

1

2

10U_0805_4VAM~D

1

2

10U_0805_4VAM~D

1

C2092

2

0.1U_0402_10V7K~D

1

C2104

2

0.022U_0402_16V7K~D

1

C2116

2

0.1U_0402_10V7K~D

+2.5V_RUN

D D

1 2

L2126

BLM18AG121SN1D_0603~D

+1.2VRUN

L2125

BLM18AG121SN1D_0603~D

1 2

C C

B B

+1.2VRUN

A A

1

C2066

C2067

2

2.2U_0603_6.3V6K~D

4700P_0402_25V7K~D

1

1

C2082

C2083

2

2

0.1U_0402_10V7K~D

4.7U_0603_6.3V4Z~D

+1.8V_RUN

1

2

4.7U_0603_6.3V4Z~D

+1.8V_RUN

1

2

4.7U_0603_6.3V4Z~D

L2129

BLM18AG121SN1D_0603~D

12

5

1

2

C2084

1000P_0402_50V7K~D

C2109

C2108

G72_PLLVDD

1

C2206

2

PLLVDD

1

C2068

2

470P_0402_50V7K~D

FBA_PLLAVDD

1

2

1

C2114

2

0.1U_0402_10V7K~D

1

C2119

2

0.1U_0402_10V7K~D

1

2

0.1U_0402_10V7K~D

40mA

1

2

1

2

C2207

C2097

C2113

0.1U_0402_10V7K~D

C2118

0.1U_0402_10V7K~D

4.7U_0603_6.3V4Z~D

1

1

2

C2045

0.1U_0402_10V7K~D

1

C2059

2

0.1U_0402_10V7K~D

1

2

C2048

0.1U_0402_10V7K~D

1

C2079

2

0.1U_0402_16V4Z~D

1

C2093

2

0.1U_0402_10V7K~D

1

C2107

2

0.022U_0402_16V7K~D

1

C2115

2

0.1U_0402_10V7K~D

1

2

2

C2046

2200P_0402_50V7K~D

0.022U_0402_16V7K~D

1

1

2

C2061

C2060

0.1U_0402_10V7K~D

1

C2058

2

C2047

2200P_0402_50V7K~D

1

C2080

C2081

2

0.022U_0402_16V7K~D

1

C2088

2

0.1U_0402_10V7K~D
4700P_0402_25V7K~D

1

C2106

2

0.022U_0402_16V7K~D

1

C2112

2

0.022U_0402_16V7K~D

1

2

C2062

0.1U_0402_10V7K~D

1

2

C2180

0.1U_0402_10V7K~D

1

2

220P_0402_50V7K~D

1

C2089

2

4700P_0402_25V7K~D

1

C2101

2

4700P_0402_25V7K~D

1

C2111

2

0.022U_0402_16V7K~D

4

G72_PLLVDD

2

0.022U_0402_16V7K~D

1

2

0.022U_0402_16V7K~D

1

1

C2090

2

2

4700P_0402_25V7K~D

1

C2100

2

4700P_0402_25V7K~D

1

1

C2102

C2103

2

2

4700P_0402_25V7K~D

4700P_0402_25V7K~D

RUNPWROK38,39,42,49

U2001D

J9
J10
J11
L12
L13
L15
L16

M9
M11
M12
M13
M14
M15
M16
M17

N9
N11
N17

R9
R11
R17

T9
T11
T12
T13
T14
T15
T16
T17
U12
U13
U15
U16

W13
W15
W16

W9
W10
W11
W12

F13
F14

J12

J13

J15

J16

E15
F15
F16

J17

J18

L19

N19
R19
U19

W19

F17
F19

J19

J22

L22

M19
P22
T19
U22
Y22

RUNPWROK

VDD_0
VDD_1
VDD_2
VDD_3
VDD_4
VDD_5
VDD_6
VDD_7
VDD_8
VDD_9
VDD_10
VDD_11
VDD_12
VDD_13
VDD_14
NV_PLLAVDD
VDD_16
VDD_17
VDD_18
VDD_19
VDD_20
VDD_21
VDD_22
VDD_23
VDD_24
VDD_25
VDD_26
VDD_27
VDD_28
VDD_29
VDD_30
VDD_31
VDD_32
VDD_33
VDD_34
VDD_35

VDD_LP_0
VDD_LP_1
VDD_LP_2
VDD_LP_3

VDD33_0
VDD33_1
VDD33_2
VDD33_3
VDD33_4
VDD33_5

FBVTT_0
FBVTT_1
FBVTT_2
FBVTT_3
FBVTT_4
FBVTT_5
FBVTT_6
FBVTT_7
FBVTT_8
FBVTT_9

FBVDDQ_0
FBVDDQ_1
FBVDDQ_2
FBVDDQ_3
FBVDDQ_4
FBVDDQ_5
FBVDDQ_6
FBVDDQ_7
FBVDDQ_8
FBVDDQ_9

PEX_IOVDD_0

Part 4 of 5

PEX_IOVDD_1
PEX_IOVDD_2
PEX_IOVDD_3
PEX_IOVDD_4
PEX_IOVDD_5
PEX_IOVDD_6

PEX_IOVDD_7
PEX_IOVDDQ_0
PEX_IOVDDQ_1
PEX_IOVDDQ_2
PEX_IOVDDQ_3
PEX_IOVDDQ_4
PEX_IOVDDQ_5
PEX_IOVDDQ_6
PEX_IOVDDQ_7
PEX_IOVDDQ_8
PEX_IOVDDQ_9

PEX_IOVDDQ_10
PEX_IOVDDQ_11
PEX_IOVDDQ_12
PEX_IOVDDQ_13
PEX_IOVDDQ_14
PEX_IOVDDQ_15
PEX_IOVDDQ_16
PEX_IOVDDQ_17
PEX_IOVDDQ_18

PEX_PLLAVDD
PEX_PLLDVDD

POWER

MIOB_VDDQ_0
MIOB_VDDQ_1
MIOB_VDDQ_2

MIOBCAL_PD_VDDQ

MIO_A_VDDQ_0
MIO_A_VDDQ_1
MIO_A_VDDQ_2

IFPA_IOVDD
IFPB_IOVDD

IFPC_IOVDD

IFPAB_PLLVDD
IFPCD_PLLVDD

DACA_VDD
DACB_VDD

PLLVDD

FBA_PLLAVDD

FBA_PLLVDD

FBCAL_PD_VDDQ

CLAMP

G72M-V-N-A2_BGA533~D

+3.3V_RUN

13

D

Q2012

2

SI1303DL-T1-E3_SOT323-3~D

G

S

1 2

R2143

10K_0402_5%~D

13

D

2

G

Q2013

S

2N7002W-7-F_SOT323~D

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

5

U2001E

B2

GND_0

B5

GND_1

B8

GND_2

B11

GND_3

B14

GND_4

B17

D D

C C

GND_5

B20

GND_6

B23

GND_7

B26

GND_8

E2

GND_9

E5

GND_10

E8

GND_11

E11

GND_12

E14

GND_13

E17

GND_14

E20

GND_15

E23

GND_16

E26

GND_17

F11

GND_18

H2

GND_19

H6

GND_20

H23

GND_21

H26

GND_22

J14

GND_23

K9

GND_24

K19

GND_25

L2

GND_26

L5

GND_27

L11

GND_28

L14

GND_29

L17

GND_30

L23

GND_31

L26

GND_32

N12

GND_33

N13

GND_34

N14

GND_35

N15

GND_36

N16

GND_37

P2

GND_38

P5

GND_39

P9

GND_40

P11

GND_41

P12

GND_42

P13

GND_43

P14

GND_44

P15

GND_45

P16

GND_46

P17

GND_47

P19

GND_48

P23

GND_49

P26

GND_50

R12

GND_51

R13

GND_52

R14

GND_53

R15

GND_54

R16

GND_55

U2

GND_56

U5

GND_57

U11

GND_58

U14

GND_59

Part 5 of 5

G72M-V-N-A2_BGA533~D

GND_60
GND_61
GND_62
GND_63
GND_64
GND_65
GND_66
GND_67
GND_68
GND_69
GND_70
GND_71
GND_72
GND_73
GND_74
GND_75
GND_76
GND_77
GND_78
GND_79
GND_80
GND_81
GND_82
GND_83
GND_84
GND_85
GND_86
GND_87

GND

GND_88
GND_89
GND_90
GND_91
GND_92
GND_93
GND_94

IFPAB_PLLGND

IFPCD_PLLGND

MIOBCAL_PU_GND

PEX_PLLGND

PLLGND

FBA_PLLGND

FBCAL_PU_GND

FBCAL_TERM_GND

U17
U23
U26
V9
V19
W14
Y2
Y5
Y23
Y26
AC2
AC8
AC14
AC23
AC26
AD8
AD9
AD11
AD12
AD14
AD16
AD17
AD19
AD20
AC5
AF2
AF3
AF6
AF9
AF12
AF15
AF18
AF21
AF24
AF26

V6
M6

M3
AA6
H5

C15

E13
H22

4

12

R2104
30_0402_1%~D

3

2

1

B B

A A

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

NVG72M Ground

LA-2792

55 70Tuesday, Fe b r u a r y 07, 2006

1

1.0

of

5

B11

D10

D11

F10

U2003

VSSQB4VSSQ

FBAA0
FBAA1
FBAA2
FBAA3

R2037

0_0402_5%~D

10mil

12

FBAA4
FBAA5
FBAA6
FBAA7
FBAA8
FBAA9
FBAA10
FBAA11
FBA_BA0
FBA_BA1

DQMA#0
DQMA#3
DQMA#1
DQMA#2

DQSA0
DQSA3
DQSA1
DQSA2

FBA_VREF

FBARAS#
FBACAS#
FBAWE#
FBACS0#

FBA_CKE
CLKA0

CLKA0#

R_FBACS1#

D D

+1.8V_RUN

12

R2035

1K_0402_1%~D

12

R2036

1K_0402_1%~D

C C

FBACS1#53

B B

FBA_BA053
FBA_BA153

1

C2128

2

0.1U_0402_10V7K~D

FBARAS#53
FBACAS#53
FBAWE#53
FBACS0#53

FBA_CKE53

CLKA053
CLKA0#53

Reserve for Hynix 8Mx32

CLKA053

VSSQD4VSSQD5VSSQD6VSSQD9VSSQ

N5

A0

N6

A1

M6

A2

N7

A3

N8

A4

M9

A5

N9

A6

N10

A7

N11

A8/AP

M8

A9

L6

A10

M7

A11

N4

BA0

M5

BA1

B3

DM0

H12

DM1

H3

DM2

B12

DM3

B2

DQS0

H13

DQS1

H2

DQS2

B13

DQS3

N13

VREF

M13

MCL

L9

RFU1

M10

RFU2

M2

RAS#

L2

CAS#

L3

WE#

N2

CS0#

N12

CKE

M11

CK

M12

CK#

C4

NC

C11

NC

H4

NC

H11

NC

L12

NC

L13

NC

M3

NC

M4

NC

N3

NC

E7

VSS

E8

VSS

E10

VSS

K6

VSS

K7

VSS

K8

VSS

K9

VSS

L5

VSS

L10

VSS

E5

VSS

VSS THF6VSS THF7VSS THF8VSS THF9VSS THG6VSS THG7VSS THG8VSS THG9VSS THH6VSS THH7VSS THH8VSS THH9VSS THJ6VSS THJ7VSS THJ8VSS TH

CLKA0

Close to U2003

R2039

120_0402_5%~D

1 2

CLKA0#53

CLKA153

CLKA0#

CLKA1

Close to U2004

R2042

120_0402_5%~D

A A

1 2

CLKA1#53

5

CLKA1#

G10

VSSQ

VSSQE6VSSQE9VSSQF5VSSQ

VSSQG5VSSQ

VSSQH5VSSQ

+1.8V_RUN

1

C2135

2

0.1U_0402_10V7K~D

+1.8V_RUN

1

C2146

2

0.1U_0402_10V7K~D

Place close to U2003

4

H10

J10

K10

VSSQJ5VSSQ

VSSQK5VSSQ

B7

DQ0

C6

DQ1

B6

DQ2

B5

DQ3

C2

DQ4

D3

DQ5

D2

DQ6

E2

DQ7

K13

DQ8

K12

DQ9

J13

DQ10

J12

DQ11

G13

DQ12

G12

DQ13

F13

DQ14

F12

DQ15

F3

DQ16

F2

DQ17

G3

DQ18

G2

DQ19

J3

DQ20

J2

DQ21

K2

DQ22

K3

DQ23

E13

DQ24

D13

DQ25

D12

DQ26

C13

DQ27

B10

DQ28

B9

DQ29

C9

DQ30

B8

DQ31

C3

VDDQ

C5

VDDQ

C7

VDDQ

C8

VDDQ

C10

VDDQ

C12

VDDQ

E3

VDDQ

E12

VDDQ

F4

VDDQ

F11

VDDQ

G4

VDDQ

G11

VDDQ

J4

VDDQ

J11

VDDQ

K4

VDDQ

K11

VDDQ

D7

VDD

D8

VDD

E4

VDD

E11

VDD

L4

VDD

L7

VDD

L8

VDD

L11

VDD

K4D553235F-VC33_FBGA144~D

J9

1

C2136

2

0.1U_0402_10V7K~D

1

C2147

2

0.1U_0402_10V7K~D

4

3

B11

D10

D11

F10

G10

H10

J10

VSSQG5VSSQ

VSSQH5VSSQ

VSSQJ5VSSQ

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8

DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

J9

K10

VSSQK5VSSQ

B7
C6
B6
B5
C2
D3
D2
E2
K13
K12
J13
J12
G13
G12
F13
F12
F3
F2
G3
G2
J3
J2
K2
K3
E13
D13
D12
C13
B10
B9
C9
B8

C3
C5
C7
C8
C10
C12
E3
E12
F4
F11
G4
G11
J4
J11
K4
K11

D7
D8
E4
E11
L4
L7
L8
L11

K4D553235F-VC33_FBGA144~D

U2004

VSSQB4VSSQ

VSSQD4VSSQD5VSSQD6VSSQD9VSSQ

VSSQ

FBAD4
FBAD3
FBAD5
FBAD0
FBAD7
FBAD6
FBAD1
FBAD2
FBAD31
FBAD30
FBAD29
FBAD28
FBAD24
FBAD25
FBAD26
FBAD27
FBAD13
FBAD11
FBAD10
FBAD14
FBAD15
FBAD8
FBAD12
FBAD9
FBAD17
FBAD16
FBAD18
FBAD19
FBAD21
FBAD20
FBAD23
FBAD22

+1.8V_RUN

+1.8V_RUN +1.8V_RUN

1

C2137

2

1000P_0402_50V7K~D

1

C2148

2

1000P_0402_50V7K~D

1

C2138

2

0.01U_0402_16V7K~D

1

C2149

2

0.01U_0402_16V7K~D

2

C2129

1

0.1U_0402_10V7K~D

CLKA153
CLKA1#53

1

C2139

2

22U_0805_6.3VAM~D

1

C2150

2

22U_0805_6.3VAM~D

FBAA0
FBAA1
FBBA2
FBBA3
FBBA4
FBBA5
FBAA6
FBAA7
FBAA8
FBAA9
FBAA10
FBAA11
FBA_BA0
FBA_BA1

DQMA#7
DQMA#4
DQMA#5
DQMA#6

DQSA7
DQSA4
DQSA5
DQSA6

FBA_VREF

FBARAS#
FBACAS#
FBAWE#
FBACS0#

FBA_CKE
CLKA1

CLKA1#

R_FBACS1#

N5

A0

N6

A1

M6

A2

N7

A3

N8

A4

M9

A5

N9

A6

N10

A7

N11

A8/AP

M8

A9

L6

A10

M7

A11

N4

BA0

M5

BA1

B3

DM0

H12

DM1

H3

DM2

B12

DM3

B2

DQS0

H13

DQS1

H2

DQS2

B13

DQS3

N13

VREF

M13

MCL

L9

RFU1

M10

RFU2

M2

RAS#

L2

CAS#

L3

WE#

N2

CS0#

N12

CKE

M11

CK

M12

CK#

C4

NC

C11

NC

H4

NC

H11

NC

L12

NC

L13

NC

M3

NC

M4

NC

N3

NC

E7

VSS

E8

VSS

E10

VSS

K6

VSS

K7

VSS

K8

VSS

K9

VSS

L5

VSS

L10

VSS

E5

VSS

VSSQE6VSSQE9VSSQF5VSSQ

VSS THF6VSS THF7VSS THF8VSS THF9VSS THG6VSS THG7VSS THG8VSS THG9VSS THH6VSS THH7VSS THH8VSS THH9VSS THJ6VSS THJ7VSS THJ8VSS TH

2

FBAA[0:11]53
FBBA[2:5]53

FBAD63
FBAD57
FBAD58
FBAD61
FBAD56
FBAD62
FBAD59
FBAD60
FBAD33
FBAD32
FBAD35
FBAD34
FBAD36
FBAD37
FBAD39
FBAD38
FBAD47
FBAD42
FBAD41
FBAD46
FBAD44
FBAD40
FBAD43
FBAD45
FBAD54
FBAD55
FBAD52
FBAD51
FBAD50
FBAD49
FBAD48
FBAD53

+1.8V_RUN

C2130

0.1U_0402_10V7K~D

+1.8V_RUN

C2141

0.1U_0402_10V7K~D

+1.8V_RUN

1

2

1

2

C2131

C2142

DQMA#[0:7]53
DQSA[0:7]53
FBAD[0:63]53

1

2

0.1U_0402_10V7K~D

1

2

0.1U_0402_10V7K~D

1

C2132

2

1000P_0402_50V7K~D

1

C2143

2

1000P_0402_50V7K~D

Place close to U2004

1

FBAA[0:11]
FBBA[2:5]
DQMA#[0:7]
DQSA[0:7]

FBAD[0:63]

1

C2133

2

0.01U_0402_16V7K~D

1

C2144

2

0.01U_0402_16V7K~D

1

C2134

2

22U_0805_6.3VAM~D

1

C2145

2

22U_0805_6.3VAM~D

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

NVG72M External DDR

LA-2792

56 70Tuesday, Fe b r u a r y 07, 2006

1

1.0

of

5

4

3

2

1

NV44M

STRAPS PIN DESCRIPTION

+3.3V_RUN

12

D D

RAM_CFG052
RAM_CFG152
RAM_CFG252

RAM_CFG352
SUB_VENDOR53
3GIO_ADR_053
3GIO_ADR_153
3GIO_ADR_253

PEX_PLL_EN_TERM10053
PCI_DEVID352
PCI_DEVID252
PCI_DEVID152
PCI_DEVID052

C C

RAM_CFG0
RAM_CFG1
RAM_CFG2
RAM_CFG3
SUB_VENDOR
3GIO_ADR_0
3GIO_ADR_1
3GIO_ADR_2

PEX_PLL_EN_TERM100
PCI_DEVID3
PCI_DEVID2
PCI_DEVID1
PCI_DEVID0

12

R2045

R2044

@

@

2K_0402_5%~D

2K_0402_5%~D

12

12

R2058

R2059

@

10K_0402_5%~D

10K_0402_5%~D

12

12

R2047

R2046

@

2K_0402_5%~D

2K_0402_5%~D

12

12

R2061

R2060

10K_0402_5%~D

10K_0402_5%~D

12

R2049

@

2K_0402_5%~D

12

R2130

2K_0402_5%~D

12

12

R2051

R2050

@

2K_0402_5%~D

2K_0402_5%~D

12

12

R2055

R2056

@

@

2K_0402_5%~D

2K_0402_5%~D

12

R2069

10K_0402_5%~D

12

12

R2135

2K_0402_5%~D

12

R2136

2K_0402_5%~D

R2137

2K_0402_5%~D

ROM_TYPE[1:0]

SUB_VENDOR

PEX_PLL_TERM MIOAD0

RAM_CFG[3:0]

MIOBD10 Parallel=00, SERIAL AT25F=01 DEFAULT,
MIOB_VSYNC

MIOAD1

MIOBD0
MIOBD1
MIOBD8

Serial SST45VF=10, LPC=11
VBIOS on card (pull high)

VBIOS with system BIOS (pull down)

8Mx32 DDR monolithic (64bit NV44 )

8Mx32 DDR monolithic (32bit NV44 )

MIOBD9

4Mx32 DDR generic (64bit NV44)

4Mx32 DDR generic (32bit NV44)

Value

01

0

0

0001

1001

00108Mx32 DDR (Samsung K4D55323QF-GC)

0100

1100

*

STRAPS DESCRIPTION

CONFIG

Reserved

RAM_CFG[3:0]

8Mx32 DDR

300MHz, 1.8V
Reserved
350MHz, 1.8V

1.8V I/O
Reserved

4Mx32 DDR

2.5V I/O
Reserved

B B

U2010

XTALOUTBUFF52

12

@

XTALSSIN52

R117

R2120

10K_0402_5%~D

0_0402_5%~D

12

1
2
3

@

XIN/CLKIN

XOUT

VSS

VDD

D_C

PD#

ModOUT4REFCLK

P1819GF-08SR_SO8~D

8
7
6
5

@

R2123

+3.3V_RUN

12

10K_0402_5%~D

+3VL

12

@

R2124

10K_0402_5%~D

1

C2196

2

@

10U_0805_10V4Z~D

Value

0000
0001
0010
0011
01004Mx32 DDR
0101
0110
0111

@

BLM18AG121SN1D_0603~D

1 2

1

2

C2197

@

0.1U_0402_10V7K~D

L2123

+3.3V_RUN

S0

-1.75% (DOWN)

A A

±0.875% (CENTER)01

S0 Internal pull up

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

NVG72M Spread Spectrum & Strapping

LA-2792

57 70Tuesday, Fe b r u a r y 07, 2006

1

of

1.0

5

D D

12

R2152

61.9K_0402_1%~D

De-pop R2152 for ISL88550

GFX_CORE_PWRGD42

EC

C C

B B

A A

GFX_PCIE_PWRGD42

GFX_RUN_ON41

+VCC_GFX_CORE

5

RUN_ON19,37,39,41,42,46,47,48

+1.8V_SUS

+1.2VRUNP

R1801 0_0402_5%~D

R1802
0_0402_5%~D

@

C2216

10U_0805_10V4Z~D

PJP2001

1 2

PAD-OPEN 43X118

PJP2002

1 2

PAD-OPEN 43X79

12

12

1

2

1

2

GFX_REF

1

2

C2233

C2232

22U_0805_6.3VAM~D

R2162

100K_0402_5%~D

+1.2VRUN+1.2 V R UNP

22U_0805_6.3VAM~D

12

1

2

+VDD_CORE

C2230

0.01U_0402_16V7K~D

4

GFX_+5V_RUN

C2217

1

2

R2161

1.21K_0402_1%~D

1 2

4

1

2

1U_0603_10V4Z~D

26

17

VIN

AVDD

5

POK1

6

POK2

27

SHDN#

7

STBY#

13

VTTI

MAX8632ETI+_TQFN28~D

14

REFIN

11

PGND2

12

VTT

9

VTTS

10

VTTR

GND29SS8GND24SKIP#25ILIM

1

C2231

2

1U_0603_10V4Z~D

R2163

12

4.99K_0402_1%~D

3

+GPU_PWR_SRC

1

20

18

DH

19

LX

21

DL

23

16

15

FB

1

3

GFX_CORE_CNTRL

+5V_SUS

1

C2222

2

R2155

1 2

1_0603_5%~D

R2153

@

0_0402_5%~D

GFX_REF

12

R2156
511K_0402_1%~D

R2154

@

12

0_0402_5%~D

R2150
511K_0402_1%~D

2.2U_0603_6.3V6K~D

12

12

+3.3V_RUN

1 2

10K_0402_5%~D

21

D2001

De-pop D2 for ISL88550

C2223

0.22U_0603_10V7K~D

1 2

1

C2227

2

0.22U_0402_10V4Z~D

R2168
10K_0402_5%~D

@

R2167

@

RB751V_SOD323~D

12

8

D6D5D7D

4

G

S

S

1

2

3

786

5

4

123

12

1

R2166

2

C2235

@

100K_0402_5%~D

@

R2151

10_0805_5%~D

1 2

2

28

TP0

C2229

0.047U_0402_16V4Z~D

GFX_CORE_CNTRL52

OVP/UVP

22

VDD

PGND1

4

U2008

BST

VOUT

TON

REF

2

C2218

S

Q2010
HAT2198R-EL-E_SO8~D

L2001

1UH_MPLC0730L1R0_11A_20%~D

1 2

Q2011
FDS6676AS_NL_SO8~D

12

R2165

@

301_0402_1%~D

13

D

@

Q2014

2

BSS138W-7-F_SOT323~D

G

S

0.01U_0402_16V7K~D

10U_1206_25V6M~D

output voltage adjustable network

2

1

2

C2219

10U_1206_25V6M~D

C2228

12

R2164
118K_0402_1%~D

@

1

@

100P_0402_50V8J~D

2

Place near GND pin 24

1

2

1000P_0402_50V7K~D

C2234

1

2

C2220

2

1

0.1U_0603_50V4Z~D

12

12

FBMA-L11-453215-900LMA60T_1812~D

C2221

2200P_0402_50V7K~D

1

2

C2226

0.1U_0402_10V7K~D

R2157

24.9K_0402_1%~D

R2160

57.6K_0402_1%~D

L2013

1 2

1

+

2

C2224

330U_D2E_2.5VM_R9~D

+PWR_SRC

Design specs:
TDC: 7A
Peak: 9A
OCP: 12A

+VCC_GFX_CORE

1

+

2

C2225

@

330U_D2E_2.5VM_R9~D

1

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.
NVG72M VDD_CORE

LA-2792

58 70Tuesday, Feb ru ar y 07, 2006

1

1.0

of

5

4

Version Change List ( P. I. R. List )

3

2

1

Item Issue DescriptionDate

D D

1 0.2

31 H/W 05/27 Roger

Title

Owner

Smart card pin definition not match the
cage pin define

Change JSC pin connection, pin1 connect to GND, pin2 connect to
SC_DET# ~ pin10 connect to +SC_PWR

2 52 H/W 05/27 Roger TV out no out put Add R1790, R1791, R1792 for 75 ohms 0.2

3 40 H/W 05/27 Roger

4 20 H/W 05/27 Roger

Remove power switch to save placement
spacing

Docking CRT HSYNC, VSYNC connect to the
out put side of buffer

DOCK_HSYNC connect from U190 pin4 to docking connector pin 209,
DOCK_VSYNC connect from U191 pin4 to docking connector pin 210

5 32 H/W 05/27 Roger Improve RJ45 center tap driving Connect +2.5VLAN to JIO pin 14 for RJ45 center tap 0.2

6 39 H/W 05/27 Roger SPI ROM pass trough mode connect error

Change FDATAIN to ICHO_FDATAIN and connect from U216 pin 106 to U213
pin5. Chagne FDATAOUT to ICHI_FDATAOUT and connect from U216 pin 108 to
R1788 pin1

7 39 H/W 05/27 Roger Flash Recovery strapping issue Change R474, R475 from 100K to 10K 0.2
8 H/W 05/30 Brike Change net from +3VALW to +3VSRCTo fix MEC5004 VCC1 power lading 0.2

C C

ALL

43 H/W 05/30 Brike None Delete H21 and change H4 footprint from H_C176D122to H_C176D102 0.29

10 58 H/W 05/30 Brike To meet VGA core power rating Change footprint to JUMP_43X118 0.2

11 39 H/W 06/01 Will For delay MEC5004 internal 1.8V reg. Modified C1769 from 4.7UF to 22UF. 0.2

12 0.2Will06/01H/W23 Modified R389 from 10K to 1K..

To improve rise time of serial DO
from SPI ROM.

None13 0.2Will06/01H/W41 Add pullup R2149 to HDDC_EN# and R2148 MODC_EN#.

39 H/W 06/01 Will None14 Change power on SPI ROM (pins 3 and 8) from +3VALW to +3VSUS

15 58 H/W 06/01 Brike None U2008 pin 16 change pull-up panle to +3VRUN

Solution Description Rev.Page#

0.2Remove SW1. Reseve R1793 pad for power switch

0.2

0.2

0.2

0.2

Request

16 13 H/W 06/01 Lester L34 value change to BLM18PG181SN1_0603~D 0.2Intel Checklist recommends a 1 nH ferrite

B B

17 06 H/W 06/01 Lester Add resistor for cystal drive current

which calculates to 200 ohm.

Add R32 0 ohm resistor 0.2

limiting

18 39 H/W 06/01 Will Correct SPI connection for SMSC recommand

Roger06/02H/W3819 Add R1440 100K for LAN_TPM_EN# (VBUS_DET)

SMSC recommond add VBUS_DET pull up
resistor

ICH7M.P5 connect to MEC 5004.107, MEC5004.108 connect to SPI ROM.5.
ICH7M.P2 connect to MEC 5004.105, MEC5004.106 connect to SPI ROM.2

0.2

0.2

33 H/W 06/02 Roger20 Add MDC disable circuit Add R1441, R1442, R1443, Q64. ECE5018 pin 67 program MDC_RST_DIS# 0.2

21 34 H/W 06/06 Roger 0.2Change U8 NNCD6.8RL-A to D5 NNCD5.6LGNone

NoneRoger06/06H/W323 Fixed USB table

24 27 H/W 06/14 Roger

A A

U10 (STAC9200) pin21 (GPIO0) is anlog
power plane

0.2

0.3Change R156 pull up from +3VSUS to +VDDA

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Changed-List History 1

Size Document Number Rev

Date: Sheet

LA-2792

59 70Tuesday, Fe b r u a r y 07, 2006

1

of

1.0

5

4

Version Change List ( P. I. R. List )

3

2

1

Item Issue DescriptionDate

D D

25 0.3

7 H/W 06/14 Roger

Title

Owner

Change ITP debug to XDP debug definition
for Yonah CPU

Change R387, R417, R391, R436, R416, R415 to 56 ohms. Add R33 56 ohms.
Change R424 to 1K ohms.

26 39 H/W 06/14 Roger For easier flash EC code Add short pad and change R475 to 1K ohms 0.3

27 40 H/W 06/14 Roger For easier power switch Change R1793 to a pad like CMOS pad 0.3

28 34 H/W 06/14 Roger ME change mini card stand off to Latch Remove H22,H23,H24,H25. Add JCLIP1,JCLIP2 0.3

Roger06/14H/W4229 Add C1806,C1807,C1808,C1809,C1810,C1811

Roger30 41 H/W 06/16

EMI reqest add caps for the splite power
plane that PCI bus routed

Reserve discharg circuit for +5VRUN,+3VRUN,
+1.8VRUN,+1.5VRUN,+0.9V_DDR_VTT,+2.5VRUN

Add R1793,R1794,R1795,R1796,R1797,R1798,Q87,Q88,Q89,Q90,Q91,Q92 0.3

power rails

31 58 H/W 06/20 Roger

32 28 H/W 06/21 Gautam Reserve ST M45PE20 for LOM EEPROM Add U3 (ST M45PE20) co-layout with U188 (AT45BCM021B) 0.3

C C

33 42 H/W 06/23 Gary

Replace ISL6269 and MAX1510 circuits with
MAX8632 solution

EMI reqest add caps for the splite power
plane that PCI bus routed

Remove ISL6269 and MAX1510 circuit. Add MAX8632 circuit 0.3

Add C1812~C184 0.047uF_0402. Change C1810, C1811 from 0603 to 0402
package

34 38 H/W 06/23 Roger +3VRUN leakage at AC mode in S5 Change R1362 pull up from +3VSRC to +3VRUN 0.3

35 All H/W 06/24 Roger Follow Dell USB assignment recommendation Update USB table, block diagram and connection 0.3

06/24H/W36 39 0.3Change C1769 for 22uF 0805 size to 4.7uF 0603 size4.7uF cap for VR_Cap pin of REV B 5504Will

H/WAll37

Will06/24 0.3Change +3VSRC to +3VALW except for LOM

Change +3V/+5V design to follow Dell
recommendation

IEEE testing the voltage level are closer
to the higher end of IEEE range

Change R1364 from 1.15K to 1.18K_0402_1% 0.3Gautam06/24H/W2838

39 Required by Intel for B0 Yonah.Lester06/24H/W7 0.3Add R1378 (51_0603_1%) for TEST2 pulldown

Solution Description Rev.Page#

0.3

0.3

Request

40 39 H/W 06/24 Lester Required by Intel for B0 Yonah. Populate R1752 and add note "No stuff when doing flash recovery" 0.3

B B

41 58 H/W 06/27 Joey

Change Gfx VDD_CORE controller power
source

Change +5VSUS to +5VRUN. Change +3VSUS to +3VRUN. Depop C2225 0.3

42 33 H/W 06/28 Rossana MDC signal by pass caps not require Delete C93, C82, C73 0.3

43 31,40 H/W 06/28 Rossana

Reseved USB port of OZ77C6 for Biometrics
reader

Change JTPAD from 10 pins to 20 pins. Add USB_BIO+/- on U1 pin18,19
connect to JPAD pin9,11

0.3

44 30 H/W 06/28 Rossana Gerber Gate List issue Remove C1783, C1784 0.3

45 34 H/W 06/28 Rossana Gerber Gate List issue Remove L18, R149, and R144 - direct connect USB to Wireless LAN card 0.3

46 34 H/W 06/28 Rossana Gerber Gate List issue Add R1603 connect to JMINI2 pin46, outgoing signal BT_ACTIVE 0.3

47 34 H/W 06/28 Rossana Gerber Gate List issue Add series 0-ohms R1609, R1610 for pins 3 and 5 of JMINI2 0.3

A A

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Changed-List History 2

Size Document Number Rev

Date: Sheet

LA-2792

60 70Tuesday, Fe b r u a r y 07, 2006

1

of

1.0

5

4

Version Change List ( P. I. R. List )

3

2

1

Item Issue DescriptionDate

D D

48 0.3

34 H/W 06/28 Change C159 and C1785 from 10uF to 0.1uFGerber Gate List issueRossana

Title

Owner

49 34 H/W 06/28 Gerber Gate List issueRossana Add T1 test point for JMINI1 pin 42 0.3

50 36 H/W 06/28 Rossana Gerber Gate List issue Add C1817~1820 for U180,U178,U179,U177 0.3

3951 Change R30 pull up from +3VSRC to +3VALWGerber Gate List issueRossana06/28H/W 0.3

52 43 06/28 Rossana

H/W 0.3

Change sniffer switch type, the active
direction swap

WIRELESS_ON/OFF# connection from pin1 to pin 4 of JSNIFF, pin3 connect
to GND, pin2 NC, pin 1 connect to SNIFFER#

53 36 06/28 Rossana Gerber Gate List issue Add C1821 1000pF for +DOCK_PWR_SRC, add C1827 1000pF for DOCK_DC_INH/W 0.3

54 Add C1822 0.1uF_0402 and C1823,C1824 .47uF_0402 for QBUF powerRossana06/28H/W35 0.3Gerber Gate List issue

55 26,27 H/W 06/29 Rossana

C C

56 39 H/W 06/29 Will Gerber Gate List issue 0.3Change L4 form MURATA BLM11A121S to BLM18PG181SN1

Gerber Gate List issue 0.3Follow Dell "Travis_Audio_0628" reference circut design

57 24 H/W 06/30 Will Gerber Gate List issue Remove C375, C37 for ICH_V5REF_RUN, remove C420 for ICH_V5REF_SUS 0.3

58 24 H/W 06/30 Will Gerber Gate List issue Add R37 0.5 ohm 0603 resistor connect to L42 pin1 0.3

59 Scott24 H/W 06/30 Gerber Gate List issue Populate C347 and C442 0.3

Change C450 for 220uF to 330uF poly cap 0.3Scott60 Gerber Gate List issue06/3024 H/W

61 Roger Match Dell JTPAD pinout definition 0.3

40 H/W 06/30

62 26,27 H/W 06/30 Gerber Gate List issue

63 26 H/W 06/30 Gerber Gate List issueRossana

B B

64 7 H/W 07/07 Roger Support A1 Yanah CPU 0.3De-pop R513, R514 for A1 yanah CPU

Match Dell JTPAD pinout definition, add C62, C63 for BIO power rail
bypass

R162 change from 8.2K to 2.2K, remove D33, D34, Change C1800, C1801
from 1uF to 2.2uF, change C534 from 0.1uF to 1uF, del C533.

HP_NB_SENSE move from GPIO2 to GPIO0 of U10, add series resistor 0 ohm
for this signal

Solution Description Rev.Page#

0.3Rossana

0.3

Request

65 56 H/W 07/25 Roger Set VRAM VREF to 50% of VDDQ 0.4Change R2035, R2036 to 1K_0402_1%

66 54 H/W 07/25 Roger Nvidia G72 design change 0.4De-pop L2008, C2094, C2095, C2096 for FBA_PLLVDD

67 54 H/W 07/25 Roger

68

54 H/W 07/25 Roger Nvidia G72 power design change 0.4Remove L2003, L2006, L2007, L2124, L2008, C2094, C2095, C2096

69 54 H/W 07/25 Roger Nvidia G72 power design change 0.4

70 7 H/W 08/01 Roger

71 38 H/W 08/01

A A

72 43 H/W 08/01

Roger Gerber Gate List issue item 9

Nvidia G72 design change 0.4Remove C2110 and NC for CLAMP (D11)

Pop L2129, C2206, C2207 for G72_PLLVDD

Gerber Gate List issue item 6 0.4

Change Change R417 to 150 ohm, R415 to 51 ohm, R387 to 39.2 ohm, R436
to 27.4 ohm, R391 to 680 ohm, R424 to 22.6 ohm

0.4Change R110 from 68 ohm to 75 ohm for H_PROCHOT# pull upRoger Gerber Gate List issue item 8

Change the voltage rail on sniffer LED pull-ups (at Q13 and Q16) from
+3VALW to +3VSUS

0.4

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Changed-List History 2

Size Document Number Rev

Date: Sheet

LA-2792

61 70Tuesday, Fe b r u a r y 07, 2006

1

of

1.0

5

4

Version Change List ( P. I. R. List )

3

2

1

Item Issue DescriptionDate

D D

74 18 H/W 08/01

Owner

Roger None 0.4Remove unnecessary capacitor C1805773 08/01H/W

Roger Gerber Gate List issue item 12 0.4

Remove Q84, C1804. Connect U15 pin1 to VGA_THERMDP, U15 pin2
to VGA_THERMDN

75 H/W 08/01 Roger 0.4Depop U46 and C5440 Hall switch design on touch pad moudle

76 H/W18 08/01 Roger

77

78 38 H/W 08/01

79 16,17

80

C C

81

57 H/W 08/01 Roger Gerber Gate List issue item 15 Remove Gxf thermal sensor U2007 (ADM1032), C2181, C2182 0.4

Roger 0.4Move NB_MUTE from U215 pin 107 to pin73Gerber Gate List issue item 19

H/W 08/01 Roger 0.4Gerber Gate List issue item 20,21 Remove R178, pop R177

10,23 H/W 08/01 Roger Gerber Gate List issue item 22,23 Depop R253, populate R1799 0.4

38 H/W 08/01 Roger Change board ID for X01 0.4Depop R419 and populate R405

Gerber Gate List issue item 13

Add a thermistor circuit to VCP input (pin 3) for the SODIMM temp
sensor. Add Q15, R476, R477, R478, C66

Add R1800 31.6K ohm resistor for Vmargin circuit.83 18 08/02 0.4H/W Roger Gerber Gate List issue item11

84 23 Change R389 from 1K to 10KH/W 08/02 Roger Gerber Gate List issue item5 0.4

85 33, 40 H/W 08/04 Delete JBT and move components to JTAP. 0.4Steven Conbine the BT and TP in 30 PIN connector.

86 42 H/W 08/04 Steven Gerber Gate List issue item3 Add Depop resister R2169, R2170, R2171. 0.4

87 22, 23 H/W 08/04 Steven

For intel NAPA platform check list 1.5
request.

Chnage R425 from 33Ohm pull-down to 8.2KOhm pull-up. And add pull-up
resister R227 in SIO_RCIN#.

88 16 H/W 08/09 Roger V_DDR_MCH_REF discharge issue 0.4Add R51 (100K_0402) connect to V_DDR_MCH_REF

B B

23 H/W89 08/09 Roger Leakage issue when system into S3

Change SIO_EXT_SMI#, SIO_EXT_SCI# pull up to +3VSUS 0.4

Solution Description Rev.Page# Title

0.4

0.4Connect 2.5V_RUN_PWRGD net to LDO_POK pin. Add depop R4982 42 08/02H/W Roger Gerber Gate List issue item3

0.4

Request

90 36 H/W 08/09

91 12

92 38

93

94

95

96

A A

97

28 H/W 08/10 Roger Gerber Gate List issue item 30 0.4Add R53 4.7K resistor for LOM_SO pull down

28 H/W 08/10 Roger Gerber Gate List issue item 33 0.4

24 H/W 08/10 Roger Gerber Gate List issue item 37 0.4

38 H/W 08/10 Roger Gerber Gate List issue item 39 0.4R1171 change pull up from +3VRUN to +3VSUS

38 H/W 08/10 Roger Gerber Gate List issue item 42 Add a 4.7uF cap for ECE5018 VDDA33 coupling 0.4

H/W 08/09 Depop R357Roger Gerber Gate List issue item 28 0.4

H/W 08/09 Roger Move SPDIF_SHDN from pin31 to pin76, remove R1601, R1602, net SYSOPT0Follow Dell EC GPIO assignment 0.4

Remove R1320, R1319Roger Refer Dell docking reference circuit 0.4

Connect BCM5752 pin C4 to ECE5018 pin75 net name LOM_CABLE_DETECT.
Series no stuff resistor R55

Connect BCM5752 pin C4 to ECE5018 pin75 net name LOM_CABLE_DETECT.
Series no stuff resistor R55

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Changed-List History 2

Size Document Number Rev

Date: Sheet

LA-2792

62 70Tuesday, Fe b r u a r y 07, 2006

1

of

1.0

5

4

Version Change List ( P. I. R. List )

3

2

1

Item Issue DescriptionDate

D D

100 39 H/W 08/10

3998 08/10H/W

Owner

Roger 0.4

Roger 0.4R513, R514 pull up to +VCCP99 7 H/W 08/10

Gerber Gate List issue item 43

Follow Intel CRB circuit

Gerber Gate List issue item 46

Add a 0 Ohm 0402 resistor R62 in series with the RTC_CELL and EMC5004
pin 121

Add resistor R63 (0_0402_5%) between the BIA_PWM signal and MEC5004
pin 73

RogerH/W22102 Add no stuff C69 (0.1U_0402_16V4Z) between THRMTRIP_ICH# and GND 0.4Gerber Gate List issue item 5008/10

103 41 H/W Roger08/10 None 0.4Change R1795 pin 1 connect from +1.8VRUN to +1.8VSUS for discharge

Roger08/10H/W23104 Move pull-up R388 to pin 1 side of R1787 0.4Gerber Gate List issue item 51

105 6 H/W 08/10 Roger

C C

106 7 H/W

107

42 H/W 08/11 Roger Gerber Gate List issue item 65 0.4Populate 0ohm for R49, R313, R319, R334

08/11 Roger 0.4Remove R513 and R514 platform no longer use Yonah A00Gerber Gate List issue item 68

Gerber Gate List issue item 29

Add C70 (0.1U_0402_16V4Z) for +CK_VDD_MAIN decoupling. Remove R291,
R343, R329 to save spacing

108 41 H/W 08/11 Roger Gerber Gate List issue item 67 0.4Change R494 to 20K

109 7 0.4Add no stuff C71 and C72 for +VCCP of JITP H/W 08/11 Roger Gerber Gate List issue item 69

110 7 Roger Gerber Gate List issue item 70

111 12 Roger

112 28 0.4H/W 08/11 Roger Gerber Gate List issue item 34

113 26,27,38 H/W 0.408/12 Roger Gerber Gate List issue item 75

B B

114 38 H/W 08/15 0.4Roger Gerber Gate List issue item 38 Chnge SYS_PME# pull up from +3VRUN to +3VALW. Add no stuff R71 in series

H/W 08/11 Change R416 and R33 from 56 ohm to 54.9 ohm 0.4

H/W 08/11 Gerber Gate List issue item 72 0.4Delete R333 to follow reference schematics

Add R68 (20K_0402_5%) and R70 (39K_0402_1%) for LAN_LOW_PWR voltage
divider connect to pin K5

DOCK_HP_MUTE# for GPIO2 of codec connect to ECE5018 pin 81. EAPD for
GPIO3 of codec connect to additional Q11 gate

Solution Description Rev.Page# Title

0.4Roger

0.4RogerH/W39101 Change ITP_DBRESET# connection from EMC5004 pin 55 to pin96Gerber Gate List issue item 4708/10

0.4

Request

115 38 H/W 08/15 Roger Gerber Gate List issue item 41 0.4Remove HP_NB_SENSE from ECE5018 pin 106 to pin 82

106 23

107

108

6 H/W Roger NVidia 27MHz clock has to be 1.2V max 0.4Add R73 150 ohms for CLK_NV_27M voltage divider08/15

52 H/W Roger Gerber Gate List issue item 211 0.4Add R74 0 ohms in series to PLTRST_DELAY#08/15

109 40

110

111

A A

112 0.439 H/W 08/16 Roger Add pull up for open drain out put Add R93 pull up to +3VALW for BAT_SEL#

40 H/W 0.408/16 Roger Gerber Gate List issue item 48 Change R1750 and R1751 to L1 and L2

39 H/W 08/16 Roger Gerber Gate List issue item 217 0.4Remove R166. Move R1635 for AFT_INT# move to page 39

0.4H/W Roger Gerber Gate List issue item 188,189 Depop R428,Change value of R75 to 10k ohms08/15

0.4H/W Roger Gerber Gate List issue item 48 Change R1750 and R1751 to L1 and L208/16

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Changed-List History 2

Size Document Number Rev

Date: Sheet

LA-2792

63 70Tuesday, Fe b r u a r y 07, 2006

1

of

1.0

5

4

Version Change List ( P. I. R. List )

3

2

1

Item Issue DescriptionDate

D D

113 38 H/W 08/16 0.4Roger

114 58 H/W 09/07 Roger 0.4G72MV VDDCORE fixed to 1.0 V

Owner

Mute internal speaker when docking aduio
jack plug in

Add pull down resistor for DOCK_HP_MUTE#
Depop R2164,R2165,R2166,R2167,R2168,Q2014,C2235. Change R2160 from 69.8K

ohms to 57.6K ohms

115 06 H/W 09/07 Roger Follow Dell CoE schematics 0.5Change C329, C333 from 33pF to 27pF

116 43 H/W 09/14 Roger Blue tooth LED too bright Change R8 from 3.3K to 1K ohms

117 41 H/W 09/14 Roger +1.8VSUS discharge low issue Populate Q89, R1795

H/W39118

119 39 H/W 09/14 Roger

120

34, 39

C C

121 22 H/W 10/15 Steven

H/W 10/13 Steven

LID_CL# can't assert lowRoger09/14 Change R482 from 100K to 1M ohms
R470 from 10K to 100K is

for save the pull up current.
Connect 8051TX to WWAN Pin 19 and Connect

8051RX to WWAN Pin 42.
Gerber Gate List issue item 60. Per M07

ICH reference schematics rev A05.

R470 from 10K to 100K

Modified.

Add R12 0-ohm tuning resistor between R36 pin2 and X1 pin1 0.5

122 41 H/W 10/17 Steven Gerber Gate List issue item 66 Change R1795 to a 30 ohm 0603 resistor 0.5

123 52 H/W 10/17 Steven

124 19 H/W 10/17 Steven

125 39 H/W 10/18 Steven

Gerber Gate List issue item 67. Use 27MHz
clock from CK410.

Gerber Gate List issue item 65. Make sure
BIA_PWM logic high level is at +3.3V.

MEC5004 per SMSC recommendations to add
circuit for improving POR issue.

Pop R2131, R2132, and depop Y2001, C2204, C2205, and R2133 0.5

Add R92 pullup to +3VRUN on BIA_PWM 0. 5
Add de-pop components R23, R25, R97, R102, R104, Q20, Q19, C22, D2002.

And change C1769 to 22U.

126 38 H/W 10/18 Steven change board ID to X02 Pop R95, R419 and De-pop R108, R405. 0.5

127 23 H/W 10/18 Steven

128 40 H/W 10/18 Steven

B B

129 6 H/W 10/19 Steven

130 23 H/W 10/19 Steven

Gerber Gate List issue item 78. Pull up
LAMP_STAT# to +3VRUN

Gerber Gate List issue item 77. add 10pF
cap between GND and pin2 of L1/L2.

Gerber Gate List issue item 72. Inductor
design follow M07 design on L40,L32
(Size:0805).

Gerber Gate List issue item 79.
SATA_DET# is pull up to +3.3V_SUS.

Change R75 pull-up to +3.3V_RUN. 0.5

Add capacitor C23, C35. 0.5

Change L32, L40 from 0603 to 0805. 0.5

Change R784 pull up to +3.3V_SUS.
Change the 32 high frequency decoupling caps, 0805 X5R, from 22uF

131

9

H/W

10/2010/20

Steven

Gerber Gate List issue item 84

to 10uF.
Depop C354 and C618.Change C352, C496, C497, and C365 from 330uF/7mOhm
to 330uF/6mOhm SP caps.

132

34

H/W

10/20

Steven

Gerber Gate List issue item 82 Connect PLTRST# instead of PLTRST_DELAY# to WLAN and WWAN connectors. 0.5

Solution Description Rev.Page# Title

0.5

0.5

0.5

0.5

0.5

0.5

0.5

0.5

Request

23128 10/20H/W IMVP_PWRGD glitch issue Add C82 0.1uF cap on IMVP_PWRGD to filter the glitch 0.5Steven

10/21 Steven Q68 surge currentH/W28129 Add R120 (0603) and C80 0.1uF cap Q68 pin1 for reduce surge current 0.5

40,43 H/W 10/21 Steven

130 0.5

A A

BT & HDD LED is on when the SNIFFER is
turned on.

Added a circuit (FET and Resistors) to keep the BT LED & HDD LED off
when the SNIFFER is turned on

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Changed-List History 2

Size Document Number Rev

Date: Sheet

LA-2792

64 70Tuesday, Fe b r u a r y 07, 2006

1

of

1.0

5

4

Version Change List ( P. I. R. List )

3

2

1

Item Issue DescriptionDate

D D

18 H/W 10/24 0.5133 Steven

39 H/W134 10/24 Steven

135 39 H/W 10/24 Steven

136 52 H/W 10/24 Steven

Owner

Gerber Gate List issue item 89. Change
OTP trip temperature to 88 deg C.

Gerber Gate List issue item 90. Pop SMSC
workround circuit for 11/7 build.

Gerber Gate List issue item 91. Add a 0
ohm pulldown resistor on TEST_PIN.

Gerber Gate List issue item 94. Connect
GPIO9 of G72 to THERMTRIP3# of EMC4000.

Change R249 to 332K and R262 to 118K.

Add R110 0Ohm resister. 0.5

Add 0 Ohm resister R112 and connect to EMC4000. 0.5

137 58 H/W 10/24 Steven Gerber Gate List issue item 95. Change R2155 from 0 to 1 Ohm. 0.5

138 58 H/W 10/24 Steven Gerber Gate List issue item 96. Change +5V_RUN to +5V_SUS at VDD. 0.5

C C

139 58 H/W 10/24 Steven Gerber Gate List issue item 97. Change +3.3V_RUN to +3.3V_SUS at R2158. 0.5

140 58 H/W 10/24 Steven Gerber Gate List issue item 98. Change +1.8V_RUN to +1.8V_SUS at pin 13. 0.5

141 52 H/W 10/24 Steven

142 43 H/W 10/24 Steven

Gerber Gate List issue item 113. Add a
10K pull-down to TESTMODE pin on G72.

Gerber Gate List issue item 111. Remove
one of the pull-ups on SNIFFER_LED_OFF#.

Add 10K Ohm resister R116. 0.5

Remove Pull up resister R1447. 0.5

143 43 H/W 10/24 Steven Gerber Gate List issue item 111. More R76 to pin 1 of Q66 and populate 0.5

Gerber Gate List issue item 109. Add 39
ohm resistors at output of U190 and U191.

Gerber Gate List issue item 93. Add

B B

18 H/W 10/24 0.5146 Steven

54 H/W 10/24 0.5147 Steven

54 H/W 10/24 0.5148 Steven

149 43 H/W 10/24 0.5Steven

150 58 H/W 10/25 0.5Steven

151 40 H/W 10/25 Steven

152 43 H/W 10/25 Steven

153 34 H/W 10/25 Steven

A A

154 58 H/W 10/25 Steven

5

thermistor circuit to VCP2 (pin 40) of
EMC4000. Please route to 5V_CAL_SIO2#
(pin 80, GPIO B4 on ECE5018).

Gerber Gate List issue item 106. Change
FBCAL_PD_VDDQ terminating resistor.

Gerber Gate List issue item 105. Change
FBCAL_PU_GND terminating resistor.

Gerber Gate List issue item 114.
Modified SATA_ACT# LED sniffer disable
circuit.

Gerber Gate List issue item 120. Pull up
R2159 to +3.3V_SUS.

Gerber Gate List issue item 119. For fix
the IMVP_PWRGOOD glitch issue.

Gerber Gate List issue item 104. Modified
the SATA_ACT# circuit.

Gerber Gate List issue item 115. Change
LTRST_DELAY# to PLTRST# on WLAN.

Gerber Gate List issue item 117. Modified
Vcore voltage switching circuit.

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

4

3

Add thermistor circuit R479, R480, R481, C36, Q21.

Change R2032 from 37.4 to 40.2 ohms.

Change R2104 from 37.4 to 30 ohms.

Modified the circuit and Add and D2004. Chnage Q1 to 3904,
R1149/1448 change to 10K and 1K.

Change R2159 to pull up +3V_SUS.
Change delay circuit R1764 from 200KOhm, C1788 to 470PF to +1.8V_run

and +3V_run.
Modified the circuit Pull up R1449 to +5V_SUS and R1445 to +5V_run.

R2 move to Q1 pin 3, SNIFFER_LED change to GPIO82.
Chnage PLTRST_DELAY# to PLTRST# on the WLAN connector. 0.5

Change R2168 to +3.3V_SUS. 0.5

Solution Description Rev.Page# Title

0.538 H/W 10/21 Steven Depop R1440Gerber Gate List issue item 81131

0.534 H/W 10/22 Steven Add Intel WoWLAN Support Circuit Add pop components Q21 and R101, and un-pop componet R24.132

0.5Pop R23, R25, R97, R102, R104, Q20, Q19, C22, D2002.

0.534 H/W 10/24 Steven Add Intel WoWLAN Support Circuit144 Replace Q21 and R101 to D2003.

0.520 H/W 10/24 Steven145 Add resister R101 and R114.

0.5

0.5

DELL CONFIDENTIAL/PROPRIETARY

Title

Changed-List History 2

Size Document Number Rev

2

Date: Sheet

LA-2792

65 70Tuesday, Fe b r u a r y 07, 2006

1

1.0

of

Request

5

4

Version Change List ( P. I. R. List )

3

2

1

Item Issue DescriptionDate

D D

155

20

157 H/W 10/25 Steven Change 0Ohm resister to Q25.

158

159 40, 43

161

162 58

C C

163 41

164 31

165 43

166 27

167 39

168 56

169 39

170 42

B B

171 43

172 28

173 20

174 27

18 0.5

58

H/W 10/25 Steven

H/W 10/26 Steven

58160

41

H/W

H/W

10/29 Steven

H/W 10/29 Steven

H/W 11/03

H/W 11/03

H/W 11/03

H/W 11/03

H/W 11/11

H/W 11/11

H/W 11/11

H/W 11/11

H/W 11/11

H/W 11/12

H/W 11/12

H/W 11/12

Owner

Gerber Gate List issue item 118. Depop
the discrete spread spectrum circuit.

Gerber Gate List issue item 116. Add
diode HSYNC and VSYNC buffers.

For improving Gerber Gate List issue item
94 leakage issue.

Cancelled Gerber Gate List issue item 97.

Modified HDD/BT disable circuit.

Steven10/26

Gerber Gate List issue item 121. Delete
resistors R2158 and R2159 on sheet 58.

For improving power sequence add RC
delay and Discharge circuit.

For pop option 8632 shutdown pin source
Add two resister.

Steven Populate the HDD power switch circuit Pop Q51, R507, Q50 and Depop PJP24. 0.5

Steven For passing EMVCo test. Change R1424 from 220 to 330Ohm. 0.5

Steven SNIFFER_LED_OFF# is a push/pull signal. De-pop R1449. 0.5

Steven To improve audio quality Change C199 to 0.022uF and pop R164, depop R170. 0.5

Steven Change SMSC MEC5004 from version C to D.

Steven

Steven

Steven

Change VRAM parts to K4D553235F-VC33 as
DELL request.

Change DOCK_SMB_CLK and DOCK_SMB_DAT for
consistent with other M07 platforms.

Provide pull-up resister to
GFX_CORE_PWRGD for 1.2Vrun power used.

Steven For improve LED brightness issue.

Steven

Steven

For Q68 broken issue. Modified R120 value
for protect base pin.

For DELL request change D32 and D2005 to
RB500.

Steven For improve Audio THD+n performance. Change C113, C114 and C146 from 1UF to 2.2U. 0.5

Depop R2120, U2010, R2123, R2124, C2196, C2197 and L2123.Add R117 10K
pull down resister.

Change +3.3V_SUS to +3.3V_RUN at R2159. 0.5

Move 40 BT Disable circuit to 43. 0.5

Add R1765, C1804 for delay +3V_run circuit. Add non-populate
component. Q26, Q28, R1803, R1766.

Add Non-populate R1802 and Populate component R1801. For Pop option
8632 Enable source.

Change U216 P/N to D version. Depop R102, R97, R25, R23, R104, D2002,
Q19, Q20, C22. And chnage C1769 value from 22UF to 4.7UF.

Change VRAM P/N to K4D553235F-VC33 (SA55323000L). 0.5
Change R99 and R100 resister from 100K to 8.2K Ohm. And R1618 change

to 10K.
Pop R2170 for provide pull-up resister. 0.5
Change R2 value from 56Ohm to 330Ohm. And modified R15 from 150Ohm to

100Ohm.
Change R120 from 0Ohm to 2KOhm. 0.5

Change D32 and D2005 from RB751 to RB500. 0.5

Solution Description Rev.Page# Title

0.557 H/W 10/25 Steven

0.5156 H/W 10/25 Steven Add D2005 (RB751) in U190, U191 Pin 5.

0.5Remove R2158 and R2159.

0.5

0.5

0.5

0.5

0.5

Request

175 27

42176

177 23, 38

178 7

A A

179 39

H/W 11/22

H/W 12/06

H/W 12/06

H/W 12/06

H/W 12/07

Steven For adjust Audio gain to 15.6DB. Pop R170, De-pop R164. 0.5

For improving SUSPWROK turn on issue. Modified Q7 to 2N7002. 0.6Steven

Steven

For solving HD warn boot parking sound
issue.

Change HDDC_EN#, MODC_EN# from ICH7 to ECE5018 Pin 106, 107 (GPIOH2/3),
and Depop R2148, R2149.

0.6

Steven Add a De-pop resister for CPU test 1 PIN. Add De-pop resister R1387. 0.6

Add an damping resister for improving
SPI_CS# overshoot issue.

Add 47Ohm resister R127. 0.6Steven

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Changed-List History 2

Size Document Number Rev

Date: Sheet

LA-2792

66 70Tuesday, Fe b r u a r y 07, 2006

1

of

1.0

5

4

Version Change List ( P. I. R. List )

3

2

1

Item Issue DescriptionDate

D D

179

180 6 H/W 12/12 Steven

181

38 H/W 12/12 Steven

Owner

For solving SBAT_SMBDAT rising time over
spec issue.

For Gerber Gating list item 14 Depop
pullup resistor on ICH_CLKREQ#.

For Gerber Gating list item 17 Update
board ID to A00

Depop resister R1761. 0.6

Pop R405, depop R419. 0.6

For Gerber Gating list item 11 add 47pF

182

31 H/W 12/12 Steven

41 H/W 12/14 Steven

41 H/W 12/15184 Steven

185 39 H/W 12/19 Steven

186 31 H/W 12/19 Steven For improving USB BIO sensor EMI issue. Add Pop L5, and depop resister R122, R123. 0.6

C C

187 40 H/W 12/20 Steven

188 28 H/W 12/30 Steven

189 7 H/W 12/30 Steven

H/W190 39 01/04 Steven

191 27 For adjust Audio gain to 21.6 DB. DePop R170, pop R164.

192 28

193 58

H/W 01/07

H/W 01/09

H/W 01/09

Benson 0.6

Steven

Steven For avoiding GPU leakage issue. Change R2168 pull-up from +3.3V_run to +3.3V_sus. 0.6

capacitors to the USB_BIO+/- pins to
fix bio sensor ESD issue.

For GPIOH[3:2] need, chnage pullup
resister power plane to always.

For Gerber Gating list item 18. Change
pullup resister to 10K.

For Gerber Gating list item 21. Add 0 ohm
series resistor to SPI_CS# at MEC5004.

For DELL EMI request for add a 0.1uF
capacitor in JTPAD.

For Q68 damage issue change form BCP69 to
MBT35200 as ZRS solution.

Intel Design Guide 1.0 to change H_RESET
pull-up resister to 51Ohm.

For enable MEC5004 BIOS write protect
function.

For Q68 issue to reserve soft start
circuit.

Add 2 capaciotr C83, C84 in USB_BIO+/-. 0.6

Change pullup resister R2148, R2149 for +3.3V_SUS to +3.3V_ALW. 0.6183

Change pullup resister R2148, R2149 for 100K to 10KOhm. 0.6

Add series resister R112 at MEC5004 side. 0.6

Add 0.1uF capacitor C54. 0.6

Use MBT35200 to replace Q68. Modified. 0.6

Change resister R416 to 51Ohm. 0 .6

Pop R139 and de-pop R138. 0.6

Change R120 to 0Ohm, and depop C80. 0. 6

Solution Description Rev.Page# Title

0.639 H/W 12/09 Steven Change R444 to 4.7KOhm resister.

Request

194 20 H/W 01/20 Steven

B B

195 19 H/W 01/20 Steven

196

6 H/W 01/20 Steven The Drive Level too high Change R32 from 0 ohm to 470 ohm

For fixing issue with projector using
long cable.

For stronger the VGS driving in
Battery Mode

22197 H/W 01/20 Steven The Negative Resistance too low

38198

199 H/W 01/20 Steven None Depop L5 ,pop R122,R123 33 ohm

31

H/W 01/20 Steven

The Frequency too high & Drive Level too
high

200 H/W 01/20 Steven Change R74 from 0 ohm to 10K ohm and pull-down itTo fix PLTRST_DELAY# glitch23

201 23 H/W 02/06 Steven For solving USB strength issue. Change R113 from 22.6Ohm to 22Ohm.

A A

202

H/W 02/073 9 Steven For solving primary battery hand issue. Change R447, R449 to 4.7KOHm; R444, R131 to 2.2KOhm.

Change R101,R114 from 39 ohm to 0 ohm

Change R235 from 200K ohm to 100K ohm

Change X1 spec from CL=20pF to 6 pF and C38,C40 from 12pF to 2.2pF

Change Y1 spec from CL=20pF to 12pF and C1451,C1452 from 22P to 15P

0.6

0.6

0.6

0.6

0.6

0.6

1.0

0.6

0.6

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Changed-List History 2

Size Document Number Rev

Date: Sheet

LA-2792

67 70Tuesday, Fe b r u a r y 07, 2006

1

of

1.0

5

4

Version Change List ( P. I. R. List )

3

2

1

Item Issue DescriptionDate

D D

1 0.2

46 PWR 06/01 Saha

Title

Owner

M4 input current more than MAX8734 LDO3
output 100mA

Delete PU17 SN74AHC1G32DCKR OR GATE(SA00732018L),
PR49 1K_0402_1%(SD03410018L)
Add PR350 0_0402_5%(SD02800008L) connact LDO3 to ON3
PU18 74AHCT1G08GW AND GATE(SA00000L30L)
PR352 1K_0402_1%(SD03410018L)
PR351 0_0402_5%(SD02800008L)

2 46 PWR 06/01

3 46 PWR PWR_SRC noise issue Un-pop PC252 100U_25V_M(SF10004M008) 0.2

4 44/45 PWR +3VALW change to +3VSRC

5 47 PWR VCCP high/low side MOSFET change from

C C

06/01 Saha

06/01 Saha

06/01 Saha

Saha

MAX8734 LDO soft start issue. Delete PR27 4.7_1210_5%(SD000007E8L)

Un-pop PC20 4.7U_1206_25V6K(SE093106M8L)

Rename net +3VALW to +3VSRC

PQ38 change from IR7821(SB57821008L) to BSO072N03S(SB00000418L)
IR to Infineon
No-stuff PC207 and PC208

PQ40 change from IR7832(SB57832008L) to BSO072N03S(SB00000418L)

Un-pop PC207 and PC208 10U_0805_6.3V5K(SE093106M8L)

6 PWR 06/01 Saha VCCP_1P05VP OCP issue(5A)47 PR224 change from 124K_0402_1%(SD03412438L) to 60.4K_0402_1%(SD03460428L) 0.2

7 PWR 06/01 Saha Choke height issue.(5.6mm change to 5.0mm)47/48 PL14 and PL27 change from 1.4U_HMU1356-1R4_15.5A H5.6mm(SH04814AM8L)

to 1.4U_HMU1350-1R4_15A H5.0mm(SH000004H8L)

8 PWR 06/01 Saha44 PSID materiel change by Dell PQ1 change from BSS138_SOT23(SB50138008L) to FDV301_SOT23(SB50301008L)

PWR9 50 06/01 Saha New version MAX8731 PIN1 define GND Un-pop PR337 0_0402_5%(SD02800008L),Pop PR336 0_0402_5%(SD02800008L)

10 PWR50 06/02 Saha Add RC filter at pin 23 of MAX8731 Add PR360 1_0603_1%(SD014100B8L)

PC253 220P_0402_50V7K(SE074221K8L)

Solution Description Rev.Page#

0.2

0.2

0.2

0.2

0.2

0.2

0.2

0.2

Request

11 PWR46/48 06/02 Saha Add support for Reliability voltage

B B

12 06/1648 PC70 and PC71 change from 330U_D3L_6.3V_R25(SGA00000N8L)

PWR

Saha

margining tests

Change output capactior rating voltage
from 6.3V to 2.5V

49 Change VCORE DPRSLPVR input resistor value PR248 change from 0_0402_5%(SD02800008L) to 499_0402_1%(SD03449900L)Saha 0.3

14 PWR 06/22

50 Add power limit schematic Depop PR361 80.6K_0402_1%, PR362 200K_0402_1%, PR363 121K_0402_1%,

PWR13 06/22

Saha 0.3

Add PR356, PR355 and PR359 0_0603_5%(SD01300008L)

PR353 and PR354 0_0402_5%(SD02800008L)

to 330U_D2E_2.5VM_R15(SGA19331D0L)

0.2

0.3

PR364 3.01K_0402_1%, PR365 499K_0402_1%, PR366 100K_0402_1%,

PR367 100K_0402_1%, PC254 0.01U_0402_25V8K, PC255 100P_0402_50V8K,

PC256 100P_0402_50V8K, PC257 100P_0402_50V8K, PC258 0.01U_0402_25V8K,

PC259 10P_0402_50J8K, PQ81 RHU002N06_SOT323, PU19 LM393DR_SO8

15 PWR 06/2946 Discreate 3VALW and 3VSRC.

Saha 0.3

Add PU17 SN74AHC1G32DCKR OR GATE(SA00732018L),

PR49 1K_0402_1%(SD03410018L)

PQ82 FDC655BN_NL(SB000004P8L )

Delete PR352 1K_0402_1%(SD03410018L)

A A

PR351 0_0402_5%(SD02800008L)

PR350 0_0402_5%(SD02800008L)

PU18 74AHCT1G08GW AND GATE(SA00000L30L)

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Changed-List History 1

Size Document Number Rev

Date: Sheet

LA-2792

68 70Tuesday, Fe b r u a r y 07, 2006

1

of

1.0

5

4

Version Change List ( P. I. R. List )

3

2

1

Item Issue DescriptionDate

D D

16 PWR 06/29 0.3Add PR27 0_1206_5%(SD00100000L)

17 PWR 06/2945/51 Saha Rename +3VSRC to +3VALW

46 Saha Add V+ input Resistor

Owner

Battery conn. and battery selector +3VSRC
change to +3VALW

18 47 PWR ISL6227 Issue

06/29

Saha

change 1.05V/1.5VHigh/Low side MOSFET
change 1.05V choke
adjust OCP and ISEN value

VCC Change from +5VRUN to +5VSUS.

EN1 and EN2 change from RUNPWROK to RUN_ON.

PR221 change from 20K_04-2_1%(SD03420028L ) to 19.6K_0402_1%(SD00000358L)

PQ8 change from FDS6994S(SB56994008L) to FDS8880(SB000004U8L)

Add PQ83 FDS6670AS(SB000004T8L)

PQ38 change from BSO072N03S(SB00000418L) to FDS8880(SB000004U8L)

PQ40 change from BSO072N03S(SB00000418L) to FDS6670AS(SB000004T8L)

PL27 change from 1.4U_HMU1350(SH000004H8L) to 1.5U_SIL104(SH04215A08L)

Add PC261 0.01U_0402(SE068103K8)

Add PC262 and PC263 2200P_0402(SE074222K8L)

PR219 change from 825_0402_1%(SD03482508L) to 1.43K_0402_1%(SD03414318L)

C C

PR220 change from 825_0402_1%(SD03482508L) to 2.1K_0402_1%(SD03421018L)

PR223 change from 69.8K_0402_1%(SD03469828L) to 124K_0402_1%(SD03412438L)

PR224 change from 60.4K_0402_1%(SD03460428L) to 124K_0402_1%(SD03412438L)

19 PWR Saha49 ISL6260 Issue

06/29

Delete PR338, PR339 and PR340 2.7_0603_5%

Change PC246, PC247, PC248 to 1500P_0805-----Unpop

Change PH1 from ERTJ1VR103J(SL20000020L) to NCP15WM474J03RB(SL20000098L)

PR284 change from 15.8K_0402_1%(SD03415828L) to 0_0402_5%(SD02800008L)

Add PC260 0.1U_0603(SE042104K8L)

20 PWR50 Saha Change +VCHGR output CAP from 1206 to 1210 0.3

06/29 PC113 and PC114 change from 10U_1206(SE142106M8L) to 10U_1210(SE056106K8L)

08/1221 PWR47 Saha Add VSEN capacitor 0.4Add PC265 and PC264 100P_0402_50V8K(SE071101K8L)

Solution Description Rev.Page# Title

0.3

0.3

0.3

Request

22 08/12

B B

23 48 08/12

24 49 08/12

47 PWR Saha Delete PGOOD pull high resistor 0.4Delete PR283 100K_0402_1%(SD03410038L)

De-pop PR195 100K_0402_1%(SD03410038L)

PWR Saha Delete reliability test resistor Delete PR283 110K_0603_1%, PR359 0_0603_1%, and PR82 59.6K_0603_1% 0.4

PWR Saha Adjust VCORE load line PR267 change from 7.87K_0402_1%(SD03478718L) to 9.09K_0402_1%(SD034909100)

0.4

PR231, PR331, and PR270 change from 7.68K_0402_1%(SD00000238L) to

7.68K_0805_1%(SD00000B08L)

25 49 08/12PWR

26 50 PWR 10/17 Saha Add RC filter in FBSA/B PIN Add PR368 and PR369 100_0402_5%(SD02810008L)

Saha Delete H_PROCHOT# resistor Delete PR235 0_0402_5%(SD02800008L ) 0.4

0.5
Add PC266 and PC267 0.01U_0603_50V7K(SE025103K8L)
Un-pop PR371 and PR370 0_0402_5%

27

28

A A

46 PWR 10/17 Saha EMI request: change BST3 resestor Change PR32 from 0_0603_5%(SD01300008L) to 2.2_0603_5%(SD013220B8L) 0.5

46 PWR 10/17 Saha change 3V out put CAP height change PC31 from 330U_6.3V_R25 H1.9(SGA00001C8L ) to

330U_6.3V_R25 H2.8(SGA0000089L)

0.5

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Changed-List History 2

Size Document Number Rev

Date: Sheet

LA-2792

69 70Tuesday, Fe b r u a r y 07, 2006

1

of

1.0

5

4

Version Change List ( P. I. R. List )

3

2

1

Item Issue DescriptionDate

D D

29 PWR 10/17 0.5Populate PR361-PR367, PC254-259, PU19, PQ81.

50 Saha Populate UL circuit

Owner

Change PR361 from 80.6k to 0. Change PR362 from 200k to 301k.
Change PR363 from 121k to 59k. Change PR364 from 3.01k to 27.4k.
Change PR365k from 499k to 4.32Meg.

30 PWR 10/2049 Saha Change VCC_CORE OCP, SOFT,

and DPRSTP# value

PR260 change from 20K_0402_1%(SD03420028L) to 11.5K_0402_1%(SD03411520L)
PC187 change from 0.022U_0402_16V7K(SE076223K8L) to

0.01U_0402_16V7K(SE076103K8L)
Add PR372 0_0402_5%(SD02800008L)
Delete PR246 0_0402_5%(SD02800008L)
Un-pop PR249 0_0402_5%(SD02800008L)

PWR31 Change PU6 BST resistorSaha10/2048 0.5PR73 change from 0_0603_5%(SD01300008L) to 1_0603_5%(SD013100B8L)

32 PWR Change PQ2 from RUH002N06 to 390444 10/20 Saha PQ2 change from RHU002N06(SB50206008L) to MMST3904(SB000002R0L) 0.5

C C

33 49 PWR 11/12 Adjust CPU Load LineSaha

PR267 change from 9.09K_0402_1%(SD03490918L) to 10.5K_0402 _1%(SD03410528L)
PR261 change from 3.57K_0402_1%(SD03435718L) to 2.47K_0402 _1%(SD03424318L)
Add PC252 100U_25V_(6.3X7.7)(SF10004M08L)
Add PC215 0.068U_10VX7R_0402 (SE102683K8L)

34 50 PWR 12/6 Saha Deeply dischargered battery problem.

5035 Add PC267 3300PF_0402_50V7K(SE074332K8L)

Follow Coe A09 schematicSaha12/6PWR

Add PD54 1SS355_sod323(SC1SS35500L)
Add PR373 1K_0603_1%(SD01410018L)

Depop PC266 0.01U_0603_50V7K(SE025103K8L)

36 47 PWR 12/15 Saha Follow GGL 1214 item19. Depop PR12 0.6

37 49 50 46 PWR 1/7 Saha Add PC270~PC273 and PC268 10U_1206_25V6M(SE142106M8L)For acoustical issue 0.6

Solution Description Rev.Page# Title

0.5

0.5

0.5

0.5

Request

B B

A A

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Changed-List History 2

Size Document Number Rev

Date: Sheet

LA-2792

70 70Tuesday, Fe b r u a r y 07, 2006

1

of

1.0