Compal LA-2792 HAL00 Travis DIS, Latitude D620 Schematic
A
B
COMPAL CONFIDENTIAL
C
D
E
1 1
PCB NO :
LA-2792
COMPAL P/N :
2 2
MODEL NAME :
HAL00
45135731L01
Travis (DIS) Schematics Document
uFCPGA Mobile Yonah
Intel Calistoga + ICH7M
2006-01-20
3 3
4 4
REV : 1.0 (DELL: A00)
DELL CONFIDENTIAL/PROPRIETARY
MB PCB
Part Number Description
DAA0000050L
PCB ZJX LA-2792
REV0 MB DIS
A
BOM NO. 45135731L01
PCB P/N: DAA0000051L
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
B
C
D
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
Cover Sheet
LA-2792
170Tuesday, Feb ru ar y 07, 2006
E
1.0
of
A
Compal confidential
Model : HAL00
B
C
D
E
Block Diagram
FAN
RGB
DVI
FAN1_VOUT
page 18
LVDS CONN
+INV_PWR_SRC
+LCDVDD
page 19
1 1
Thermal
GUARDIAN II
EMC4000
+3.3V_SUS
CRT CONN
+5V_RUN
NVG72-M-V
+1.2VRUN
+VDD_CORE(1.1V)
page 52,53,54,55,56,57,58
page 18
page 20
PCI-E 16X
+1.05V_VCCP (1.05V)
+VCC_CORE
+1.5V_RUN
+1.8V_SUS
+1.05V_VCCP (1.05V)
+3.3V_RUN
+2.5V_RUN
TV
2 2
PCI BUS
DOCKING
PORT
PAGE 36
Mini Card2
WLAN
+3.3V_RUN
3 3
page 34
DOCKING
BUFFER
+5V_RUN
PAGE 35
+3.3V_RUN/ +1.5V_RUN 100MHz
Mini Card 1
WWAN
+3.3V_RUN
+1.5V_RUN+1.5V_RUN
page 34
HUB USB[2]USB[0]
CardBus
OZ601 TQFP
+3.3V_RUN
HUB USB[1]USB[7]
GIGA Enthernet
BCM5752
+3VLAN
RJ45
IO/B
+3.3V_RUN 33MHz
page 30
page 29
IDSEL:AD17
(PIRQC,D#,GNT#1,REQ#1)
PCI Express BUS
USB[1]
HUB USB[4]
+3.3V_RUN
+3.3V_SUS
+1.5V_RUN
+1.05V_VCCP
+3.3V_ALW
Pentium-M
Yonah-2M
uFCPGA CPU
FSB 533/667 MHz
Calistoga
1466pin BGA
DMI
+1.5V_RUN
100MHz
652pin BGA
+3.3V_RUN
33MHz
SMSC SIO
ECE5018
page 38
478pin
System Bus
page 7,8
H_D#(0..63)H_A#(3..31)
INTEL
page 10,11,12,13,14,15
INTEL
ICH7-M
page 21,22,23,24
LPC BUS
HUB USB[1]
HUB USB[2]
HUB USB[3]
SPI
CPU ITP Port
+1.05V_VCCP
Memory BUS
(DDR2)
48MHz
SATA
S-HDD
+5VHDD
+1.8V_SUS 533 / 667MHz
HUB USB[3]
USB[5,6]
USB[3,4]
Azalia I/F
ATA100
REAR
SIDE
USB[2]
D Moudle
page 25 page 25 page 26
+5V_RUN
Azalia Codec
Clock Generator
SLG84450VTR
+3.3V_RUN
DDRII-DIMM X2
BANK 0, 1, 2, 3, 4 ,5 ,6 ,7 ,8
+0.9V_DDR_VTT
+1.8V_SUS
Smart Card
OZ77C6
+3.3V_RUN
USB Ports X2
+5V_SUS
USB Ports X2
+5V_SUS
STAC9200
+3.3V_RUN
+VDDA
page 16,17
page 31
page 32
IO/B
MDC
+3.3V_SUS
page 33
RJ11
page6page 7
SLOT
USB5 on right side of
connector, USB6 on left side
USB3 on the top of connector,
USB4 on the bottom
Cable
IO/B
1.8V/0.9V
page 48
VCORE (IMVP-6)
page 49
1.5V/1.05V
DC IN
page 47
page 44
Power Sequence
page 42
Power On/Off
CHARGER
4 4
page 50
BATT SELECT
page 51
BATT IN
page 45
3V/5V/15V
page 46
A
SW & LED
page 43
DC/DC Interface
page 41
B
Bluetooth
+3.3V_RUN
page 33
COM
FIR
+3.3V_RUN
page 37
page 37
Int.KBD &
page 40
Stick
Stick
C
MEC5004
+RTC_CELL
+3.3V_ALW
Touch Pad
+5V_RUN
page 39
page 40
SMSC KBC
SPI
ST M25P80
+3.3V_ALW
page 39
D
AMP & INT.
Speaker
+5V_SUS
page 27
INT MIC
IO/B
+5V_SUS
HeadPhone &
MIC Jack
+3.3V_RUN
page 27
DELL CONFIDENTIAL/PROPRIETARY
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
Block Diagram
LA-2792
270Tuesday, Feb ru ar y 07, 2006
E
of
1.0
5
Ceramic Capacitors :
4
3
TABLE
PCI
2
1
0.1U_0402_6.3VXX
D D
Tolerance
Temperatur e Characteristics
PCI DEVICE
CARD BUS
IDSEL
AD17
REQ#/GNT#
1
PIRQ
C
Rated Voltage
Package Size
Value
PM TABLE
Tantalum or Polymer Capacitors :
10U_D2_10VX_R45
C C
Low ESR Mark : 45 m ohm
Tolerance
Rated Voltage
Package Size
Value
State
S0
S1
S3
S5 S4/AC
S5 S4/AC don't exist
power
plane
+5V_ALW
+3.3V_ALW
ON
ON
ON
ON
+3.3V_SRC
+15V_SUS
+5V_SUS
+3.3V_SUS
+1.8V_SUS
ON
ON
ON
OFF
OFF
+5V_RUN
+3.3V_RUN
+1.8V_RUN
+0.9V_DDR_VTT
+1.5V_RUN
+VCC_CORE
+1.05V_VCCP
+2.5V_RUN
ON
ON
OFF
OFF
OFFOFF
Capacitor Spec Guide:
Temperature Characteristics:
B B
A A
Symbol
CODE
Tolerance:
Symbol
CODE
Z5U
8
9
COG SJ
HI J
UK
UJ
A
+-0.05PF
+-0.1PF
M
K
+-20%
+-10%
+-30%
Z5V
X6SNPO
SL
N
A
1
B
2
Z5P
B
BJ
K
X5S
C
+-0.25PF
P
+100,-0%
4
5
G
X
6
X5R
SH
H
+-3%
Z
+80,-20%
30
Y5V
Y5U X7R
C
CH
D
+-0.5PF +-1PF
Q
+20,-10%
+30,-10%
Y5P
DEFG
CJ
CK
F
+-2%
V
+40,-20%
7
J
+-5%
NOTE1:
USB
@XX : Depop component
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
TABLE
USB PORT#
0
1
2
3,4
5,6
7
3
DESTINATION
Mini 2(WLAN)
USB Hub (5018)
D Moudle
SIDE Blue tooth
USB H U B DESTINATION
1
2
3
PC Card Bay
Mini 1(WWAN)
Smart Card --> BIO
4
REAR
Docking
DELL CONFIDENTIAL/PROPRIETARY
Title
Size Document Number Rev
2
Date: Sheet
Compal Electronics, Inc.
Index and Config.
LA-2792
1
370Tuesday, Feb ru ar y 07, 2006
1.0
of
5
D D
4
3
2
1
ADAPTER
+PWR_SRC
FDS4435 +INV_PWR_SRC
RUN_ON
MAX8632
RUN_ON
RUN_ON
+1.2VRUNP +VCC_GFX_CORE
BATTERY
ALWON
C C
SUS_ON
MAX8734
+5V_SUS
B B
SI3456
HDDC_EN#
SI3456
RUN_ON
793475
PL8
AUDIO_AVDD_ON
(Option)
SI4800
RUN_ON
ALWON
SUS_ON
+3.3V_SRC
SI3456
ENAB_3VLAN
+5V_ALW
+3.3V_ALW
SI4800
ISL6260
RUNPWROK
+VCC_CORE
RUNPWROK
+1.5V_RUN
ISL6227
MAX88550
RUN_ON
SI4800
RUN_ON
SUSPWROK_5V
+0.9V_DDR_VTT
RUNPWROK
+1.8V_SUS+1.05V_VCCP
+5V_SATA +5V_RUN +VDDA
MODC_EN#
+15V_SUS
+3.3V_RUN
+3VLAN
+3.3V_SUS
+1.8V_RUN
SI3456
L47
MOD
(+5V_RUN)
A A
5
4
EMC4000
+2.5V_RUN
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
DELL CONFIDENTIAL/PROPRIETARY
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
Power Rail
LA-2792
470Tuesday, Feb ru ar y 07, 2006
1
of
1.0
5
4
3
2
1
+3.3V_SUS
2.2K 2.2K 2.2K 2. 2K
ICH_SMBCLK
D D
ICH7-M
C C
SIO
Macallan IV
B B
C22
ICH_SMBDATA
B22
CLK_SMB
6
DAT_SMB
5
DOCK_SMB_CLK
10
DOCK_SMB_DAT
9
112
111
SBAT_SMBCLK
SBAT_SMBDAT
+3.3V_ALW
10K 10K
+3.3V_ALW
8.2K 8. 2K
+3.3V_ALW
4.7K 4. 7K
+3.3V_ALW
+3.3V_SUS
WWAN
SMBUS Address [TBD]
+3.3V_ALW
+3.3V_ALW
+3.3V_ALW
2N7002
2N7002
3032
5752M
LOM
SMBUS Address [C8]
100
C8C7
WLAN
SMBUS Address [TBD]
8
GUARDIAN
7
39
DOCKING
40
3
2'nd
4
BATTERY
100
6
INV
5
3032
SMBUS Address [2F]
SMBUS Address [C4, 72, 70, 48]
SMBUS Address [16]
Inverter
SMBUS Address [58]
CLK_SCLK
CLK_SDATA
+3.3V_RUN
197
195
197
195
16
CLK GEN.
17
SMBUS Address [D2]
DIMM0
SMBUS Address [A0]
DIMM1
SMBUS Address [A2]
8.2K8.2K
8
7
A A
PBAT_SMBCLK
PBAT_SMBDAT +3.3V_ALW
100
100
3
BATTERY
4
CONN
9
CHARGER
10
SMBUS Address [16]
SMBUS Address [12]
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
SMBUS TOPOLOGY
LA-2792
570Tuesday, Feb ru ar y 07, 2006
1
1.0
of
5
D
1
3
G S
2
2N7002
ICH_SMBDATA23,28,34 CLK_SDATA 16,17
D D
+3.3V_RUN
ICH_SMBCLK23,28,34
FSC FSB FSA CPU
CLKSEL2 CLKSEL0CLKSEL1
ICH_SMBDATA
ICH_SMBCLK
000
1
*
C C
00
1
0
11
0
1
1
0
1
1
11
0
00
1
0
1
CPU_BSEL CPU_BSEL2(FSC) CPU_BSEL1(FSB)
133
166
B B
R531
8.2K_0402_5%~D
FSC
CPU_BSEL28 CPU_BSEL18
A A
12
0
0
+3.3V_RUN
5
1 2
12
+3.3V_RUN
Q36
2N7002W-7-F_SOT323~D
D
S
1 3
G
2
2
G
2N7002W-7-F_SOT323~D
1 3
D
S
SRC
MHz
MHz
100
266
100
133
100
200
100
166
100
333
100
100
100
400
Reserve
Table : ICS954305AK
0
1
CLK_NV_27M52
91_0402_5%~D
1 2
R330
0_0402_5%~D
R271
10K_0402_5%~D
FSA
R278
@
10K_0402_5%~D
FCTSEL1 PIN43 PIN44 PIN47 PIN48
0
1
*
12
12
R275
2.2K_0402_5%~D
R270
2.2K_0402_5%~D
Q38
PCI
MHz
CLK_SDATA
CLK_SCLK
1
2
C68
33.3
33.3
33.3
33.3
4.7U_0603_6.3V4Z~D
NOTE: Place Decoupling as close as
physically possilble to the VDD pins
33.3
33.3
Place crystal within
33.3
500 mils of CK410
CLK_ICH_48M23
CLK_SMC_48M31
CLK_PCI_500439
CLK_PCI_501838
CLK_PCI_LOM28
CLK_PCI_PCM30
CLK_DOCKPCI_33M36
CLK_ICH_14M23
CLK_SIO_14M38
12
R73
MCH_CLKSEL2 10 MCH_CLKSEL1 10
DOT96T DOT96C 96/100M_T 96/100M_C
(UMA)
27M_out 27M SSout SRCT0 SRCC0
(DIS)
CLK_NVSS_27M52
CLK_PCI_ICH21
CLK_ENABLE#49
4
+3.3V_RUN
1 2
L40
BLM21PG600SN1D_0805~D
1
C326
0.1U_0402_16V4Z~D
CLK_SCLK 16,17
+CK_VDD_48+CK_VDD_A +CK_VDD_REF
1
2
C61
0.047U_0402_16V4Z~D
27P_0402_50V8J~D
FSB
1
2
C50
4.7U_0603_6.3V4Z~D
C329
14.31818MHz_20P_1BX14318CC1A~D
12
C333
27P_0402_50V8J~D
12
CLK_ICH_48M FSA
CLK_SMC_48M
CLK_PCI_5004
CLK_PCI_5018
CLK_PCI_LOM PCI_LOM
CLK_PCI_PCM PCI_PCM
CLK_PCI_ICH PCI_ICH
CLK_ENABLE#
2
1
2
12
CLK_SIO_14M
1 2
R354
0_0402_5%~D
BLM21PG600SN1D_0805~D
C51
0.047U_0402_16V4Z~D
X2
R298 12.1_0402_1%~D
R1589 12.1_0402_1%~D
R1619 12.1_0402_1%~D
R1438 12.1_0402_1%~D
R331 33_0402_5%~D
R302 33_0402_5%~D
R294 33_0402_5%~D
33_0402_5%~D
+CK_VDD_MAIN2
1 2
L32
1
2
C52
0.047U_0402_16V4Z~D
R32
470_0402_5%~D
1 2
12
1 2
12
12
12
12
12
1 2
R266 12.1_0402_1%~D
1 2
R250 12.1_0402_1%~D
R1621 150_0402_5%~D
1 2
R345 33_0402_5%~D
R1582
+3.3V_RUN
12
1 2
R362 475_0402_1%~D
+3.3V_RUN
R290
10K_0402_5%~D
1 2
FCTSEL1
R274
1_0603_5%~D
1 2
1 2
12
Solder Thermal Pad to GND. Add min. 4 vias.
4
+CK_VDD_MAIN
+CK_VDD_REF
+CK_VDD_48
R273
2.2_0603_5%~D
CLK_XTAL_IN
CLK_XTAL_OUT
FSB
FSC
FCTSEL1
DOCKPCI_33MCLK_DOCKPCI_33M
CLKREFCLK_ICH_14M
CLK_NVCLK_NV_27M
CLK_NVSSCLK_NVSS_27M
R316
1 2
10K_0402_5%~D
CLKIREF
CLK_SCLK
CLK_SDATA
3
+CK_VDD_MAIN
1
C402
10U_0805_10V4Z~D
2
1
C308
10U_0805_10V4Z~D
2
49
54
65
30
36
12
18
40
20
19
41
45
23
34
33
32
27
22
43
44
37
39
16
17
15
21
31
35
42
68
73
74
75
76
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
1
2
1
2
U16
1
VDDSRC
VDDSRC
VDDSRC
VDDSRC
VDDPCI
VDDPCI
VDDCPU
VDDREF
VDD48
X1
X2
USB_48MHz/FSLA
FSLB/TEST_MODE
REF0/FSLC/TEST_SEL
PCICLK4/FCTSEL1
PCICLK3
PCICLK2
PCICLK1
REF1
DOTT_96MHz/27MHz
DOTC_96MHz/27MHz(SS)
ITP_EN/PCICLK_F0
Vtt_PwrGd#/PD
9
IREF
SMBCLK
SMBDAT
4
GNDSRC
GNDCPU
GNDREF
GNDPCI
GNDPCI
GND48
GNDSRC
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
SLG84450VTR_QFN72~D
5.1
C384
0.1U_0402_16V4Z~D
C344
0.1U_0402_16V4Z~D
R401
2.2_0603_5%~D
1 2
1
C58
0.1U_0402_16V4Z~D
2
1
C330
0.1U_0402_16V4Z~D
2
+CK_VDD_A
VDDA
GNDA
PCI_SRC_STOP#
CPU_STOP#
CPUT1
CPUC1
CPUT0
CPUC0
CPUT_ITP/SRCT10
CPUC_ITP/SRCC10
SRCT9
SRCC9
CLKREQ9#
SRCT8
SRCC8
CLKREQ8#
SRCT7
SRCC7
CLKREQ7#
SRCT6
SRCC6
CLKREQ6#
SRCT5
SRCC5
CLKREQ5#
SRCT4
SRCC4
CLKREQ4#
SRCT3
SRCC3
CLKREQ3#
SRCT2
SRCC2
CLKREQ2#
SRCT1
SRCC1
CLKREQ1#
LCD100/96/SRC0_T
LCD100/96/SRC0_C
7
8
25
24
11
10
14
13
6
5
3
2
72
70
69
71
66
67
38
63
64
62
60
61
29
58
59
57
55
56
28
52
53
26
50
51
46
47
48
2
1
C64
0.1U_0402_16V4Z~D
2
1
C389
0.1U_0402_16V4Z~D
2
Place near each pin
W>40 mil
Place near CK410+
H_STP_PCI#
H_STP_CPU#
1 2
R348 33_0402_5%~D
1 2
R359 33_0402_5%~D
CPU_BCLK
CPU_ITP
CPU_ITP#
PCIE_SATA
PCIE_ICH
PCIE_ICH#
MCH_3GPLL CLK_MCH_3GPLL
PCIE_VGA
PCIE_MINI2
PCIE_MINI2#
PCIE_MINI1
PCIE_MINI1#
1 2
R321 33_0402_5%~D
1 2
R337 33_0402_5%~D
1 2
R368 33_0402_5%~D
1 2
R376 33_0402_5%~D
1 2
R394 33_0402_5%~D
1 2
R400 33_0402_5%~D
R292 10K_0402_5%~D
1 2
1 2
R366 33_0402_5%~D
1 2
R375 33_0402_5%~D
1 2
R1761 10K_0402_5%~D@
1 2
R397 33_0402_5%~D
1 2
R402 33_0402_5%~D
R299 10K_0402_5%~D
1 2
1 2
R1435 33_0402_5%~D
1 2
R1436 33_0402_5%~D
R1762 10K_0402_5%~D
1 2
1 2
R370 33_0402_5%~D
1 2
R390 33_0402_5%~D
1 2
R1763 10K_0402_5%~D
1 2
R1393 33_0402_5%~D
1 2
R1394 33_0402_5%~D
R1395 10K_0402_5%~D
1 2
1 2
R1638 33_0402_5%~D
1 2
R1639 33_0402_5%~D
1 2
R1640 10K_0402_5%~D
2
1
2
CLK_MCH_BCLKMCH_BCLK
CLK_MCH_BCLK#MCH_BCLK#
CLK_CPU_BCLK
CLK_CPU_BCLK#CPU_BCLK#
CLK_CPU_ITP
CLK_CPU_ITP#
CLK_PCIE_SATA
CLK_PCIE_SATA#PCIE_SATA#
CLK_PCIE_ICH
CLK_PCIE_ICH#
CLK_MCH_3GPLL#MCH_3GPLL#
CLK_PCIE_LOMPCIE_LOM
CLK_PCIE_LOM#PCIE_LOM#
CLK_PCIE_VGA
CLK_PCIE_VGA#PCIE_VGA#
CLK_PCIE_MINI2
CLK_PCIE_MINI2#
CLK_PCIE_MINI1
CLK_PCIE_MINI1#
1
C70
0.1U_0402_16V4Z~D
H_STP_PCI# 23
H_STP_CPU# 23
CLK_MCH_BCLK 10
CLK_MCH_BCLK# 10
CLK_CPU_BCLK 7
CLK_CPU_BCLK# 7
CLK_CPU_ITP 7
CLK_CPU_ITP# 7
+3.3V_RUN
+3.3V_RUN
+3.3V_RUN
+3.3V_RUN
+3.3V_RUN
+3.3V_RUN
+3.3V_RUN
CLK_PCIE_SATA 22
CLK_PCIE_SATA# 22
SATA_CLKREQ# 23
CLK_PCIE_ICH 23
CLK_PCIE_ICH# 23
CLK_MCH_3GPLL 10
CLK_MCH_3GPLL# 10
CLK_3GPLLREQ# 10
CLK_PCIE_LOM 28
CLK_PCIE_LOM# 28
LOM_CLKREQ# 28
CLK_PCIE_VGA 52
CLK_PCIE_VGA# 52
CLK_PCIE_MINI2 34
CLK_PCIE_MINI2# 34
MINI2CLK_REQ# 34
CLK_PCIE_MINI1 34
CLK_PCIE_MINI1# 34
MINI1CLK_REQ# 34
CLK_CPU_ITP
CLK_CPU_ITP#
CLK_MCH_BCLK
CLK_MCH_BCLK#
CLK_CPU_BCLK
CLK_CPU_BCLK#
CLK_MCH_3GPLL
CLK_MCH_3GPLL#
CLK_PCIE_SATA
CLK_PCIE_SATA#
CLK_PCIE_ICH
CLK_PCIE_ICH#
CLK_PCIE_LOM
CLK_PCIE_LOM#
CLK_PCIE_VGA
CLK_PCIE_VGA#
CLK_PCIE_MINI2
CLK_PCIE_MINI2#
CLK_PCIE_MINI1
CLK_PCIE_MINI1#
R369 49.9_0402_1%~D
R377 49.9_0402_1%~D
R349 49.9_0402_1%~D
R360 49.9_0402_1%~D
R322 49.9_0402_1%~D
R338 49.9_0402_1%~D
R392 49.9_0402_1%~D
R403 49.9_0402_1%~D
R381 49.9_0402_1%~D
R385 49.9_0402_1%~D
R365 49.9_0402_1%~D
R374 49.9_0402_1%~D
R393 49.9_0402_1%~D
R399 49.9_0402_1%~D
R542 49.9_0402_1%~D
R543 49.9_0402_1%~D
R544 49.9_0402_1%~D
R545 49.9_0402_1%~D
R1641 49.9_0402_1%~D
R1642 49.9_0402_1%~D
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
12
12
12
12
12
12
DELL CONFIDENTIAL/PROPRIETARY
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
Clock Generator
LA-2792
670Tuesday, Feb ru ar y 07, 2006
1
of
1.0
5
4
3
2
1
H_A#[3..31]10
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
D D
H_REQ#[0..4]10
H_ADSTB#010
H_RS#[0..2]10
H_ADSTB#110
CLK_CPU_BCLK6
CLK_CPU_BCLK#6
H_ADS#10
H_BNR#10
H_BPRI#10
H_BR0#10
H_DEFER#10
H_DRDY#10
H_HIT#10
H_HITM#10
H_LOCK#10
H_RESET#10
H_TRDY#10
ITP_DBRESET#23,39
H_DBSY#10
H_DPSLP#22
H_DPRSTP#22,49
H_DPWR#10
CPU_PROCHOT#38
H_PWRGOOD22
H_CPUSLP#10,22
R1387
@
1K_0603_1%~D
R1378
51_0603_1%~D
H_THERMTRIP#18
12
12
C C
R422
56_0402_5%~D
+1.05V_VCCP
B B
Pop R1378 required by
Intel for B0 Yonah.
Backward compatible for
A0 and A1 Yonah
H_THERMDA18
H_THERMDC18
H_THERMDA, H_THERMDC routing together.
Trace width / Spacing = 10 / 10 mil
A A
1 2
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
H_ADSTB#0
H_ADSTB#1
CLK_CPU_BCLK
CLK_CPU_BCLK#
H_ADS#
H_BNR#
H_BPRI#
H_BR0#
H_DEFER#
H_DRDY#
H_HIT#
H_HITM#
H_IERR#
H_LOCK#
H_RESET#
H_RS#0
H_RS#1
H_RS#2
H_TRDY#
ITP_BPM#0
ITP_BPM#1
ITP_BPM#2
ITP_BPM#3
ITP_DBRESET#
H_DBSY#
H_DPSLP#
H_DPRSTP#
H_DPWR#
ITP_BPM#4
ITP_BPM#5
H_CPUSLP#
ITP_TCK
ITP_TDI
ITP_TDO
TEST1
TEST2
ITP_TMS
ITP_TRST#
H_THERMDA
H_THERMDC
H_THERMTRIP#
JCPUA
J4
A3#
L4
A4#
M3
A5#
K5
A6#
M1
A7#
N2
A8#
J1
A9#
N3
A10#
P5
A11#
P2
A12#
L1
A13#
P4
A14#
P1
A15#
R1
A16#
Y2
A17#
U5
A18#
R3
A19#
W6
A20#
U4
A21#
Y5
A22#
U2
A23#
R4
A24#
T5
ADDR GROUP
A25#
T3
A26#
W3
A27#
W5
A28#
Y4
A29#
W2
A30#
Y1
A31#
K3
REQ0#
H2
REQ1#
K2
REQ2#
J3
REQ3#
L5
REQ4#
L2
ADSTB0#
V4
ADSTB1#
A22
BCLK0
A21
H1
E2
G5
F1
H5
F21
G6
E4
D20
H4
B1
F3
F4
G3
G2
AD4
AD3
AD1
AC4
C20
E1
B5
E5
D24
AC2
AC1
D21
D6
D7
AC5
AA6
AB3
C26
D25
AB5
AB6
A24
A25
C7
HOST CLK
BCLK1
ADS#
BNR#
BPRI#
BR0#
DEFER#
DRDY#
HIT#
CONTROL
HITM#
IERR#
LOCK#
RESET#
RS0#
RS1#
RS2#
TRDY#
BPM0#
BPM1#
BPM2#
BPM3#
DBR#
DBSY#
DPSLP#
DPRSTP#
DPWR#
PRDY#
PREQ#
PROCHOT#
PWRGOOD
SLP#
TCK
TDI
TDO
TEST1
TEST2
TMS
TRST#
THERMAL
THERMDA
DIODE
THERMDC
THERMTRIP#
TYCO_1-1674770-2_Yonah~D
+1.05V_VCCP
YONAH
MISC
DATA GROUP
LEGACY CPU
R398
56_0402_5%~D
1 2
D0#
D1#
D2#
D3#
D4#
D5#
D6#
D7#
D8#
D9#
D10#
D11#
D12#
D13#
D14#
D15#
D16#
D17#
D18#
D19#
D20#
D21#
D22#
D23#
D24#
D25#
D26#
D27#
D28#
D29#
D30#
D31#
D32#
D33#
D34#
D35#
D36#
D37#
D38#
D39#
D40#
D41#
D42#
D43#
D44#
D45#
D46#
D47#
D48#
D49#
D50#
D51#
D52#
D53#
D54#
D55#
D56#
D57#
D58#
D59#
D60#
D61#
D62#
D63#
DINV0#
DINV1#
DINV2#
DINV3#
DSTBN0#
DSTBN1#
DSTBN2#
DSTBN3#
DSTBP0#
DSTBP1#
DSTBP2#
DSTBP3#
A20M#
FERR#
IGNNE#
INIT#
LINT0
LINT1
STPCLK#
SMI#
H_THERMTRIP#
E22
F24
E26
H22
F23
G25
E25
E23
K24
G24
J24
J23
H26
F26
K22
H25
N22
K25
P26
R23
L25
L22
L23
M23
P25
P22
P23
T24
R24
L26
T25
N24
AA23
AB24
V24
V26
W25
U23
U25
U22
AB25
W22
Y23
AA26
Y26
Y22
AC26
AA24
AC22
AC23
AB22
AA21
AB21
AC25
AD20
AE22
AF23
AD24
AE21
AD21
AE25
AF25
AF22
AF26
J26
M26
V23
AC20
H23
M24
W24
AD23
G22
N25
Y25
AE24
A6
A5
C4
B3
C6
B4
D5
A3
H_D#0H_A#3
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20H_A#23
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3
H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3
H_A20M#
H_FERR#
H_IGNNE#
H_INIT#
H_INTR
H_NMI
H_STPCLK#
H_SMI#
H_DINV#0 10
H_DINV#1 10
H_DINV#2 10
H_DINV#3 10
H_A20M# 22
H_FERR# 22
H_IGNNE# 22
H_INIT# 22
H_INTR 22
H_NMI 22
H_STPCLK# 22
H_SMI# 22
H_D#[0..63] 10
ITP_TDO
H_DSTBN#[0..3] 10
H_DSTBP#[0..3] 10
H_RESET#
R434
22.6_0402_1%~D
1 2
1
C71
2
@
1
C72
2
@
0.01U_0402_16V7K~D
0.01U_0402_16V7K~D
R424
22.6_0402_1%~D
1 2
CLK_CPU_ITP6
CLK_CPU_ITP#6
+1.05V_VCCP
ITP_DBRESET#
ITP_BPM#0
ITP_BPM#1
ITP_BPM#2
ITP_BPM#3
ITP_BPM#4
ITP_BPM#5
ITP_TCK
CLK_CPU_ITP
CLK_CPU_ITP#
ITP_TCK
ITP_TRST#
ITP_TMS
ITP_TDI
29
JITP
29
28
VTT1
27
VTT0
26
VTAP
25
DBR#
24
DBA#
23
BPM0#
22
GND5
21
BPM1#
20
GND4
19
BPM2#
18
GND3
17
BPM3#
16
GND2
15
BPM4#
14
GND1
13
BPM5#
12
RESET#
11
FBO
10
GND0
9
BCLKP
8
BCLKN
7
TDO
6
NC2
5
TCK
4
NC1
3
TRST#
2
TMS
1
TDI
30
MOLEX_52435-2891_28P~D@
30
+3.3V_SUS
+1.05V_VCCP
+1.05V_VCCP
R367
150_0402_1%~D
1 2
R415
51_0402_5%~D
1 2
R416
51_0402_5%~D
1 2
R33
54.9_0402_1%~D
1 2
R387
39.2_0402_1%~D
1 2
R417
150_0402_5%~D
1 2
This shall place near CPU
R391
680_0402_5%~D
1 2
R436
27.4_0402_1%~D
1 2
ITP_DBRESET#
ITP_TDO
H_RESET#
ITP_BPM#5
ITP_TMS
ITP_TDI
ITP_TRST#
ITP_TCK
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
Yonah in mFCPGA479
LA-2792
770Tuesday, Feb ru ar y 07, 2006
1
1.0
of
5
4
3
2
1
Length match within 25 mils
+VCC_CORE
AE18
AE17
AB15
AA15
AD15
AC15
AF15
AE15
AB14
AA13
AD14
AC13
AF14
AE13
AB12
AA12
AD12
AC12
AF12
AE12
AB10
AA10
AD10
AC10
AF10
AE10
JCPUC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
AB9
VCC
VCC
AA9
VCC
VCC
AD9
VCC
VCC
AC9
VCC
VCC
AF9
VCC
VCC
AE9
VCC
AB7
VCC
AA7
VCC
AD7
VCC
AC7
VCC
B20
VCC
A20
VCC
F20
VCC
E20
VCC
B18
VCC
B17
VCC
A18
VCC
A17
VCC
D18
VCC
D17
VCC
C18
VCC
C17
VCC
F18
VCC
F17
VCC
E18
VCC
E17
VCC
B15
VCC
A15
VCC
D15
VCC
C15
VCC
F15
VCC
E15
VCC
B14
VCC
A13
VCC
D14
VCC
C13
VCC
F14
VCC
E13
VCC
B12
VCC
A12
VCC
D12
VCC
C12
VCC
F12
VCC
E12
VCC
B10
VCC
B9
VCC
A10
VCC
A9
VCC
D10
VCC
D9
VCC
C10
VCC
C9
VCC
F10
VCC
F9
VCC
E10
VCC
E9
VCC
B7
VCC
A7
VCC
F7
VCC
YONAH
POWER, GROUND
TYCO_1-1674770-2_Yonah~D
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
K1
J2
M2
N1
T1
R2
V2
W1
A26
D26
C25
F25
B24
A23
D23
E24
B21
C22
F22
E21
B19
A19
D19
C19
F19
E19
B16
A16
D16
C16
F16
E16
B13
A14
D13
C14
F13
E14
B11
A11
D11
C11
F11
E11
B8
A8
D8
C8
F8
E8
G26
K26
J25
M25
N26
T26
R25
V25
W26
H24
G23
K23
L24
P24
N23
T23
U24
Y24
W23
H21
J22
M22
L21
P21
R22
V22
U21
Y21
W21
AD26
AB20
AA20
AF20
AE20
AB18
AB17
AA18
AA17
AD18
AD17
AC18
AC17
AF18
AF17
AF7
AE7
B26
K21
J21
M21
N21
T21
R21
V21
G21
AE6
AD6
AF5
AE5
AF4
AE3
AF2
AE2
B22
B23
C21
R26
U26
AF1
D22
C23
C24
AA1
AA4
AB2
AA3
T22
B25
K6
J6
M6
N6
T6
R6
V6
U1
V1
E7
D2
F6
D3
C1
M4
N5
T2
V3
B2
C3
JCPUB
VCCSENSE
VSSSENSE
VCCA
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
PSI#
VID0
VID1
VID2
VID3
VID4
VID5
VID6
GTLREF
BSEL0
BSEL1
BSEL2
COMP0
COMP1
COMP2
COMP3
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
YONAH
TYCO_1-1674770-2_Yonah~D
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
POWER, GROUNG, RESERVED SIGNALS AND NC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AB26
AA25
AD25
AE26
AB23
AC24
AF24
AE23
AA22
AD22
AC21
AF21
AB19
AA19
AD19
AC19
AF19
AE19
AB16
AA16
AD16
AC16
AF16
AE16
AB13
AA14
AD13
AC14
AF13
AE14
AB11
AA11
AD11
AC11
AF11
AE11
AB8
AA8
AD8
AC8
AF8
AE8
AA5
AD5
AC6
AF6
AB4
AC3
AF3
AE4
AB1
AA2
AD2
AE1
B6
C5
F5
E6
H6
J5
M5
L6
P6
R5
V5
U6
Y6
A4
D4
E3
H3
G4
K4
L3
P3
N4
T4
U3
Y3
W4
D1
C2
F2
G1
+1.05V_VCCP
+VCC_CORE
VCCSENSE
VSSSENSE
H_PSI#
CPU_BSEL0
CPU_BSEL1
CPU_BSEL2
VID0
VID1
VID2
VID3
VID4
VID5
VID6
COMP0
COMP1
COMP2
COMP3
VCCSENSE49
VSSSENSE49
+1.5V_RUN
D D
+1.05V_VCCP
R_A
12
V_CPU_GTLREF
R140
1K_0402_1%~D
R_B
12
R147
2K_0402_1%~D
Layout close CPU PIN AD26
0.5 inch (max)
C C
B B
+VCC_CORE
R555
100_0402_1%~D
1 2
R556
100_0402_1%~D
1 2
VCCSENSE
VSSSENSE
Layout close CPU
12
R129
R124
27.4_0402_1%~D
CPU_BSEL CPU_BSEL2 CPU_BSEL1
133
166
00
0
12
12
R465
27.4_0402_1%~D
54.9_0402_1%~D
1
Resistor placed within
0.5" of CPU pin.Trace
should be at least 25
12
mils away from any
other toggling signal.
R457
54.9_0402_1%~D
CPU_BSEL0
1
1
1
1
C87
C88
2
2
10U_0805_4VAM~D
0.01U_0402_16V7K~D
H_PSI#49
VID049
VID149
VID249
VID349
VID449
VID549
VID649
V_CPU_GTLREF
CPU_BSEL010
CPU_BSEL16
CPU_BSEL26
A A
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
Yonah in mFCPGA479
LA-2792
1
870Tuesday, Feb ru ar y 07, 2006
1.0
of
5
+VCC_CORE
Place these inside
socket cavity on L8
(North side
Secondary)
D D
Place these inside
socket cavity on L8
(Sorth side
Secondary)
Place these inside
socket cavity on L8
(North side
Primary)
Place these inside
socket cavity on L8
(Sorth side
Primary)
C C
1
2
+VCC_CORE
1
2
+VCC_CORE
1
2
+VCC_CORE
1
2
C100
10U_0805_4VAM~D
C428
10U_0805_4VAM~D
C468
10U_0805_4VAM~D
C448
10U_0805_4VAM~D
1
C429
10U_0805_4VAM~D
2
1
C138
10U_0805_4VAM~D
2
1
C140
10U_0805_4VAM~D
2
1
C432
10U_0805_4VAM~D
2
1
C98
10U_0805_4VAM~D
2
1
C447
10U_0805_4VAM~D
2
1
C139
10U_0805_4VAM~D
2
1
C426
10U_0805_4VAM~D
2
1
C430
10U_0805_4VAM~D
2
1
C470
10U_0805_4VAM~D
2
1
C446
10U_0805_4VAM~D
2
1
C427
10U_0805_4VAM~D
2
4
1
2
1
2
1
2
1
2
C99
10U_0805_4VAM~D
C469
10U_0805_4VAM~D
C466
10U_0805_4VAM~D
C431
10U_0805_4VAM~D
1
C472
10U_0805_4VAM~D
2
1
C467
10U_0805_4VAM~D
2
1
C137
10U_0805_4VAM~D
2
1
C120
10U_0805_4VAM~D
2
1
C473
10U_0805_4VAM~D
2
1
C471
10U_0805_4VAM~D
2
22uF 0805 X5R -> 85 degree C
3
1
C119
10U_0805_4VAM~D
2
1
C97
10U_0805_4VAM~D
2
1
C142
10U_0805_4VAM~D
2
1
C102
10U_0805_4VAM~D
2
1
C141
10U_0805_4VAM~D
2
1
C433
10U_0805_4VAM~D
2
2
1
High Frequence Decoupling
Near VCORE regulator.
+VCC_CORE
1
+
C365
2
7mOhm
PS CAP
1
C451
0.1U_0402_10V7K~D
2
North Side Secondary
1
+
2
330U_D_2.5VM_R6M~D
1
C416
0.1U_0402_10V7K~D
2
ESR <= 1.5m ohm
Capacitor > 1980uF
1
C462
0.1U_0402_10V7K~D
2
1
C414
0.1U_0402_10V7K~D
2
South Side Secondary
C352
B B
+1.05V_VCCP
1
C372
@
2
CRB was 270uF
A A
330U_D2E_2.5VM_R9~D
330U_D_2.5VM_R6M~D
7mOhm
PS CAP
+
1
+
2
1
+
C496
2
330U_D_2.5VM_R6M~D
7mOhm
PS CAP
1
C415
0.1U_0402_10V7K~D
2
C354
@
330U_D_2.5VM_R6M~D
7mOhm
PS CAP
1
+
2
1
2
1
+
C618
C497
2
@
330U_D_2.5VM_R6M~D
330U_D_2.5VM_R6M~D
7mOhm
7mOhm
PS CAP
PS CAP
C439
0.1U_0402_10V7K~D
The caps need change to ESR=6m ohms
Place these inside
socket cavity on L8
(North side
Secondary)
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
CPU Bypass
LA-2792
970Tuesday, Feb ru ar y 07, 2006
1
1.0
of
5
4
3
2
1
Description at page12
Note :
CFG3:17 has
internal pullup,
+1.05V_VCCP
U40B
AE35
DMIRXN0
AF39
DMIRXN1
AG35
DMIRXN2
AH39
DMIRXN3
AC35
DMIRXP0
AE39
DMIRXP1
AF35
DMIRXP2
AG39
DMIRXP3
AE37
DMITXN0
AF41
DMITXN1
AG37
DMITXN2
AH41
DMITXN3
AC37
DMITXP0
AE41
DMITXP1
AF37
DMITXP2
AG41
DMITXP3
AY35
SM_CK0
AR1
SM_CK1
AW7
SM_CK2
AW40
SM_CK3
AW35
SM_CK0#
AT1
SM_CK1#
AY7
SM_CK2#
AY40
SM_CK3#
AU20
SM_CKE0
AT20
SM_CKE1
BA29
SM_CKE2
AY29
SM_CKE3
AW13
SM_CS0#
AW12
SM_CS1#
AY21
SM_CS2#
AW21
SM_CS3#
AL20
SM_OCDCOMP0
AF10
SM_OCDCOMP1
BA13
SM_ODT0
BA12
SM_ODT1
AY20
SM_ODT2
AU21
SM_ODT3
AV9
SM_RCOMPN
AT9
SM_RCOMPP
AK1
SM_VREF0
AK41
SM_VREF1
G28
PM_BMBUSY#
F25
PM_EXTTS0#
H26
PM_EXTTS1#
G6
PM_THERMTRIP#
AH33
PWROK
AH34
RSTIN#
K28
ICH_SYNC#
CALISTOGA_FCBGA1466~D
Layout Note:
Route as short
as possible
12
R437
R435
@
@
40.2_0402_1%~D
40.2_0402_1%~D
2
12
HA3#
HA4#
HA5#
HA6#
HA7#
HA8#
HA9#
HA10#
HA11#
HA12#
HA13#
HA14#
HA15#
HA16#
HA17#
HA18#
HA19#
HA20#
HA21#
HA22#
HA23#
HA24#
HA25#
HA26#
HA27#
HA28#
HA29#
HA30#
HA31#
HREQ#0
HREQ#1
HREQ#2
HREQ#3
HREQ#4
HADSTB#0
HADSTB#1
HCLKN
HCLKP
HDSTBN#0
HDSTBN#1
HDSTBN#2
HDSTBN#3
HDSTBP#0
HDSTBP#1
HDSTBP#2
HDSTBP#3
HDINV#0
HDINV#1
HDINV#2
HDINV#3
HCPURST#
HADS#
HTRDY#
HDPWR#
HDRDY#
HDEFER#
HHITM#
HHIT#
HLOCK#
HBREQ0#
HBNR#
HBPRI#
HDBSY#
HCPUSLP#
HRS0#
HRS1#
HRS2#
A
H9
C9
E11
G11
F11
G12
F9
H11
J12
G14
D9
J14
H13
J15
F14
D12
A11
C11
A12
A13
E13
G13
F12
B12
B14
C12
A14
C14
D14
D8
G8
B8
F8
A8
B9
C13
AG1
AG2
K4
T7
Y5
AC4
K3
T6
AA5
AC5
J7
W8
U3
AB10
B7
E8
E7
J9
H8
C3
D4
D3
B3
C7
C6
F6
A7
E3
B4
E6
D6
H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
H_ADSTB#0
H_ADSTB#1
H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3
H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3
H_RESET#
H_ADS#
H_TRDY#
H_DRDY#
H_DEFER#
H_HITM#
H_HIT#
H_LOCK#
H_BR0#
H_BNR#
H_BPRI#
H_DBSY#
H_CPUSLP#
H_RS#0
H_RS#1
H_RS#2
4
H_A#[3..31] 7
H_ADSTB#0 7
H_ADSTB#1 7
CLK_MCH_BCLK# 6
CLK_MCH_BCLK 6
H_DSTBN#[0..3] 7
H_DSTBP#[0..3] 7
H_DINV#0 7
H_DINV#1 7
H_DINV#2 7
H_DINV#3 7
H_RESET# 7
H_ADS# 7
H_TRDY# 7
H_DPWR# 7
H_DRDY# 7
H_DEFER# 7
H_HITM# 7
H_HIT# 7
H_LOCK# 7
H_BR0# 7
H_BNR# 7
H_BPRI# 7
H_DBSY# 7
H_CPUSLP# 7,22
H_RS#[0..2] 7
H_REQ#[0..4] 7
D D
H_D#[0..63]7
C C
+1.05V_VCCP
12
12
B B
R80
R52
54.9_0402_1%~D
54.9_0402_1%~D
12
12
R57
24.9_0402_1%~D
A A
Layout Note:
H_XRCOMP & H_YRCOMP trace width
and spacing is 10/20
H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
H_VREF
H_XRCOMP
H_XSCOMP
H_YRCOMP
H_YSCOMP
H_SWNG0
H_SWNG1
R90
24.9_0402_1%~D
5
U40A
F1
HD0#
J1
HD1#
H1
HD2#
J6
HD3#
H3
HD4#
K2
HD5#
G1
HD6#
G2
HD7#
K9
HD8#
K1
HD9#
K7
HD10#
J8
HD11#
H4
HD12#
J3
HD13#
K11
HD14#
G4
HD15#
T10
HD16#
W11
HD17#
T3
HD18#
U7
HD19#
U9
HD20#
U11
HD21#
T11
HD22#
W9
HD23#
T1
HD24#
T8
HD25#
T4
HD26#
W7
HD27#
U5
HD28#
T9
HD29#
W6
HD30#
T5
HD31#
AB7
HD32#
AA9
HD33#
W4
HD34#
W3
HD35#
Y3
HD36#
Y7
HD37#
W5
HD38#
Y10
HD39#
AB8
HD40#
W2
HD41#
AA4
HD42#
AA7
HD43#
AA2
HD44#
AA6
HD45#
AA10
HD46#
Y8
HD47#
AA1
HD48#
AB4
HD49#
AC9
HD50#
AB11
HD51#
AC11
HD52#
AB3
HD53#
AC2
HD54#
AD1
HD55#
AD9
HD56#
AC1
HD57#
AD7
HD58#
AC6
HD59#
AB5
HD60#
AD10
HD61#
AD4
HD62#
AC8
HD63#
J13
HVREF0
K13
HVREF1
E1
HXRCOMP
E2
HXSCOMP
Y1
HYRCOMP
U1
HYSCOMP
E4
HXSWING
W1
HYSWING
CALISTOGA_FCBGA1466~D
HOST
+1.05V_VCCP
+1.05V_VCCP
R325
12
R85
H_SWNG1
221_0402_1%~D
12
1
R86
2
C65
100_0402_1%~D
0.1U_0402_16V4Z~D
12
R64
H_SWNG0
221_0402_1%~D
12
1
R65
2
C48
100_0402_1%~D
0.1U_0402_16V4Z~D
12
R326
H_VREF
100_0402_1%~D
12
1
C363
2
200_0402_1%~D
+1.8V_SUS
0.1U_0402_16V4Z~D
V_DDR_MCH_REF16,17,48
DMI_MRX_ITX_N023
DMI_MRX_ITX_N123
DMI_MRX_ITX_N223
DMI_MRX_ITX_N323
DMI_MRX_ITX_P023
DMI_MRX_ITX_P123
DMI_MRX_ITX_P223
DMI_MRX_ITX_P323
DMI_MTX_IRX_N023
DMI_MTX_IRX_N123
DMI_MTX_IRX_N223
DMI_MTX_IRX_N323
DMI_MTX_IRX_P023
DMI_MTX_IRX_P123
DMI_MTX_IRX_P223
DMI_MTX_IRX_P323
M_CLK_DDR016
M_CLK_DDR116
M_CLK_DDR217
M_CLK_DDR317
M_CLK_DDR#016
M_CLK_DDR#116
M_CLK_DDR#217
M_CLK_DDR#317
DDR_CKE0_DIMMA16
DDR_CKE1_DIMMA16
DDR_CKE2_DIMMB17
DDR_CKE3_DIMMB17
DDR_CS0_DIMMA#16
DDR_CS1_DIMMA#16
DDR_CS2_DIMMB#17
DDR_CS3_DIMMB#17
R142 80.6_0402_1%~D
1 2
1 2
R141 80.6_0402_1%~D
MCH_ICH_SYNC#21
V_DDR_MCH_REF
PM_BMBUSY#23
PM_EXTTS#016
PM_EXTTS#123
THERMTRIP_MCH#18
ICH_PWRGD23,42
PLTRST#21,23,28,34
V_DDR_MCH_REF
1
C425
2
@
0.1U_0402_16V4Z~D
M_ODT016
M_ODT116
M_ODT217
M_ODT317
DMI_MRX_ITX_N0
DMI_MRX_ITX_N1
DMI_MRX_ITX_N2
DMI_MRX_ITX_N3
DMI_MRX_ITX_P0
DMI_MRX_ITX_P1
DMI_MRX_ITX_P2
DMI_MRX_ITX_P3
DMI_MTX_IRX_N0
DMI_MTX_IRX_N1
DMI_MTX_IRX_N2
DMI_MTX_IRX_N3
DMI_MTX_IRX_P0
DMI_MTX_IRX_P1
DMI_MTX_IRX_P2
DMI_MTX_IRX_P3
M_CLK_DDR0
M_CLK_DDR1
M_CLK_DDR2
M_CLK_DDR3
M_CLK_DDR#0
M_CLK_DDR#1
M_CLK_DDR#2
M_CLK_DDR#3
DDR_CKE0_DIMMA
DDR_CKE1_DIMMA
DDR_CKE2_DIMMB
DDR_CKE3_DIMMB
DDR_CS0_DIMMA#
DDR_CS1_DIMMA#
DDR_CS2_DIMMB#
DDR_CS3_DIMMB#
M_OCDOCMP0
M_OCDOCMP1
M_ODT0
M_ODT1
M_ODT2
M_ODT3
SMRCOMPN
SMRCOMPP
PM_EXTTS#0
PM_EXTTS#1
ICH_PWRGD
PLTRST_R#
12
R441100_0402_1%~D
Stuff R435 & R4 37 for A1 Calistoga
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
CFG18:19 has
internal pulldown
DMI
DDR MUXING
PM
M_OCDOCMP0
M_OCDOCMP1
CPU_BSEL0
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG16
CFG
CFG17
CFG18
CFG19
CFG20
G_CLKP
G_CLKN
D_REF_CLKN
D_REF_CLKP
CLKNC
D_REF_SSCLKN
D_REF_SSCLKP
CLK_REQ#
RESERVED1
RESERVED2
RESERVED3
RESERVED4
RESERVED5
RESERVED6
RESERVED7
RESERVED8
RESERVED9
RESERVED10
RESERVED11
RESERVED12
RESERVED13
RESERVED
PM_EXTTS#0
PM_EXTTS#1
THERMTRIP_MCH#
CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
NC0
NC1
NC2
NC3
NC4
NC5
NC6
NC7
NC8
NC9
NC10
NC11
NC12
NC13
NC14
NC15
NC16
NC17
NC18
K16
K18
J18
F18
E15
F15
E18
D19
D16
G16
E16
D15
G15
K15
C15
H16
G18
H15
J25
K27
J26
AG33
AF33
A27
A26
C40
D41
H32
A3
A39
A4
A40
AW1
AW41
AY1
BA1
BA2
BA3
BA39
BA40
BA41
C1
AY41
B2
B41
C41
D1
T32
R32
F3
F7
AG11
AF11
H7
J19
A41
A34
D28
D27
A35
10K_0402_5%~D
@
MCH_CLKSEL1
MCH_CLKSEL2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG16
CFG17
CFG18
CFG19
CFG20
R336
R253
10K_0402_5%~D
R335
75_0402_5%~D
1 2
CLK_MCH_3GPLL# 6
+1.5V_RUN
+3.3V_RUN
12
12
CPU_BSEL0 8
MCH_CLKSEL1 6
MCH_CLKSEL2 6
T34PAD~D
T35PAD~D
CFG5 12
CFG6 12
CFG7 12
T41PAD~D
CFG9 12
T42PAD~D
CFG11 12
CFG12 12
CFG13 12
T43PAD~D
T44PAD~D
CFG16 12
T45PAD~D
CFG18 12
CFG19 12
CFG20 12
CLK_MCH_3GPLL 6
CLK_3GPLLREQ# 6
+1.05V_VCCP
DELL CONFIDENTIAL/PROPRIETARY
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
Calistoga(1 of 6)
LA-2792
1
10 70Tuesday, Feb ru ar y 07, 2006
of
1.0
5
4
3
2
1
D D
U40D
DDR_A_BS016
DDR_A_BS116
DDR_A_BS216 DDR_B_BS217
DDR_A_DM[0..7]16
DDR_A_DQS[0..7]16
C C
B B
DDR_A_DQS#[0..7]16
DDR_A_MA[0..13]16
DDR_A_CAS#16
DDR_A_RAS#16
DDR_A_WE#16
T2022 PAD~D
T2024 PAD~D
DDR_A_BS0
DDR_A_BS1
DDR_A_BS2
DDR_A_DM0
DDR_A_DM1
DDR_A_DM2
DDR_A_DM3
DDR_A_DM4
DDR_A_DM5
DDR_A_DM6
DDR_A_DM7
DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7
DDR_A_DQS#0
DDR_A_DQS#1
DDR_A_DQS#2
DDR_A_DQS#3
DDR_A_DQS#4
DDR_A_DQS#5
DDR_A_DQS#6
DDR_A_DQS#7
DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11 DDR_B_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_CAS#
DDR_A_RAS#
DDR_A_WE#
SA_RCVENIN#
SA_RCVENOUT#
AU12
SA_BS0
AV14
SA_BS1
BA20
SA_BS2
AJ33
SA_DM0
AM35
SA_DM1
AL26
SA_DM2
AN22
SA_DM3
AM14
SA_DM4
AL9
SA_DM5
AR3
SA_DM6
AH4
SA_DM7
AK33
SA_DQS0
AT33
SA_DQS1
AN28
SA_DQS2
AM22
SA_DQS3
AN12
SA_DQS4
AN8
SA_DQS5
AP3
SA_DQS6
AG5
SA_DQS7
AK32
SA_DQS0#
AU33
SA_DQS1#
AN27
SA_DQS2#
AM21
SA_DQS3#
AM12
SA_DQS4#
AL8
SA_DQS5#
AN3
SA_DQS6#
AH5
SA_DQS7#
AY16
SA_MA0
AU14
SA_MA1
AW16
SA_MA2
BA16
SA_MA3
BA17
SA_MA4
AU16
SA_MA5
AV17
SA_MA6
AU17
SA_MA7
AW17
SA_MA8
AT16
SA_MA9
AU13
SA_MA10
AT17
SA_MA11
AV20
SA_MA12
AV12
SA_MA13
AY13
SA_CAS#
AW14
SA_RAS#
AY14
SA_WE#
AK23
SA_RCVENIN#
AK24
SA_RCVENOUT#
CALISTOGA_FCBGA1466~D
DDR SYS MEMORY A
D
SA_DQ0
SA_DQ1
SA_DQ2
SA_DQ3
SA_DQ4
SA_DQ5
SA_DQ6
SA_DQ7
SA_DQ8
SA_DQ9
SA_DQ10
SA_DQ11
SA_DQ12
SA_DQ13
SA_DQ14
SA_DQ15
SA_DQ16
SA_DQ17
SA_DQ18
SA_DQ19
SA_DQ20
SA_DQ21
SA_DQ22
SA_DQ23
SA_DQ24
SA_DQ25
SA_DQ26
SA_DQ27
SA_DQ28
SA_DQ29
SA_DQ30
SA_DQ31
SA_DQ32
SA_DQ33
SA_DQ34
SA_DQ35
SA_DQ36
SA_DQ37
SA_DQ38
SA_DQ39
SA_DQ40
SA_DQ41
SA_DQ42
SA_DQ43
SA_DQ44
SA_DQ45
SA_DQ46
SA_DQ47
SA_DQ48
SA_DQ49
SA_DQ50
SA_DQ51
SA_DQ52
SA_DQ53
SA_DQ54
SA_DQ55
SA_DQ56
SA_DQ57
SA_DQ58
SA_DQ59
SA_DQ60
SA_DQ61
SA_DQ62
SA_DQ63
AJ35
AJ34
AM31
AM33
AJ36
AK35
AJ32
AH31
AN35
AP33
AR31
AP31
AN38
AM36
AM34
AN33
AK26
AL27
AM26
AN24
AK28
AL28
AM24
AP26
AP23
AL22
AP21
AN20
AL23
AP24
AP20
AT21
AR12
AR14
AP13
AP12
AT13
AT12
AL14
AL12
AK9
AN7
AK8
AK7
AP9
AN9
AT5
AL5
AY2
AW2
AP1
AN2
AV2
AT3
AN1
AL2
AG7
AF9
AG4
AF6
AG9
AH6
AF4
AF8
DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63
DDR_B_DQS[0..7]17
DDR_B_DQS#[0..7]17
DDR_B_MA[0..13]17
DDR_B_BS017
DDR_B_BS117
DDR_B_DM[0..7]17
DDR_B_CAS#17
DDR_B_RAS#17
DDR_B_WE#17
T2023 PAD~D
T2025 PAD~D
DDR_B_BS0
DDR_B_BS1
DDR_B_BS2
DDR_B_DM0
DDR_B_DM1
DDR_B_DM2
DDR_B_DM3
DDR_B_DM4
DDR_B_DM5
DDR_B_DM6
DDR_B_DM7
DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4
DDR_B_DQS5
DDR_B_DQS6
DDR_B_DQS7
DDR_B_DQS#0
DDR_B_DQS#1
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS#4
DDR_B_DQS#5
DDR_B_DQS#6
DDR_B_DQS#7
DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6DDR_A_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA12
DDR_B_MA13
DDR_B_CAS#
DDR_B_RAS#
DDR_B_WE#
SB_RCVENIN#
SB_RCVENOUT#
E
U40E
AT24
SB_BS0
AV23
SB_BS1
AY28
SB_BS2
AK36
SB_DM0
AR38
SB_DM1
AT36
SB_DM2
BA31
SB_DM3
AL17
SB_DM4
AH8
SB_DM5
BA5
SB_DM6
AN4
SB_DM7
AM39
SB_DQS0
AT39
SB_DQS1
AU35
SB_DQS2
AR29
SB_DQS3
AR16
SB_DQS4
AR10
SB_DQS5
AR7
SB_DQS6
AN5
SB_DQS7
AM40
SB_DQS0#
AU39
SB_DQS1#
AT35
SB_DQS2#
AP29
SB_DQS3#
AP16
SB_DQS4#
AT10
SB_DQS5#
AT7
SB_DQS6#
AP5
SB_DQS7#
AY23
SB_MA0
AW24
SB_MA1
AY24
SB_MA2
AR28
SB_MA3
AT27
SB_MA4
AT28
SB_MA5
AU27
SB_MA6
AV28
SB_MA7
AV27
SB_MA8
AW27
SB_MA9
AV24
SB_MA10
BA27
SB_MA11
AY27
SB_MA12
AR23
SB_MA13
AR24
SB_CAS#
AU23
SB_RAS#
AR27
SB_WE#
AK16
SB_RCVENIN#
AK18
SB_RCVENOUT#
CALISTOGA_FCBGA1466~D
AK39
SB_DQ0
AJ37
SB_DQ1
AP39
SB_DQ2
AR41
SB_DQ3
AJ38
SB_DQ4
AK38
SB_DQ5
AN41
SB_DQ6
AP41
SB_DQ7
AT40
SB_DQ8
AV41
SB_DQ9
AU38
SB_DQ10
AV38
SB_DQ11
AP38
SB_DQ12
AR40
SB_DQ13
AW38
SB_DQ14
AY38
SB_DQ15
BA38
SB_DQ16
AV36
SB_DQ17
AR36
SB_DQ18
AP36
SB_DQ19
BA36
SB_DQ20
AU36
SB_DQ21
AP35
SB_DQ22
AP34
SB_DQ23
AY33
SB_DQ24
BA33
SB_DQ25
AT31
SB_DQ26
AU29
SB_DQ27
AU31
SB_DQ28
AW31
SB_DQ29
AV29
SB_DQ30
AW29
SB_DQ31
AM19
SB_DQ32
AL19
SB_DQ33
AP14
SB_DQ34
AN14
SB_DQ35
AN17
SB_DQ36
AM16
SB_DQ37
AP15
SB_DQ38
AL15
SB_DQ39
SB_DQ40
SB_DQ41
SB_DQ42
SB_DQ43
SB_DQ44
SB_DQ45
SB_DQ46
SB_DQ47
SB_DQ48
SB_DQ49
SB_DQ50
SB_DQ51
SB_DQ52
SB_DQ53
SB_DQ54
SB_DQ55
SB_DQ56
SB_DQ57
SB_DQ58
SB_DQ59
SB_DQ60
SB_DQ61
SB_DQ62
SB_DQ63
AJ11
AH10
AJ9
AN10
AK13
AH11
AK10
AJ8
BA10
AW10
BA4
AW4
AY10
AY9
AW5
AY5
AV4
AR5
AK4
AK3
AT4
AK5
AJ5
AJ3
DDR SYS MEMORY B
DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63
DDR_B_D[0..63] 17DDR_A_D[0..63] 16
A A
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
Calistogo(2 of 6)
LA-2792
11 70Tuesday, Feb ru ar y 07, 2006
1
1.0
of
5
4
3
2
1
Strap Pin Table
C
U40C
H27
SDVOCTRL_DATA
H28
SDVOCTRL_CLK
B37
D D
+1.5V_RUN
C C
+1.05V_VCCP
B B
A A
5
LA_DATA0
B34
LA_DATA1
A36
LA_DATA2
C37
LA_DATA#0
B35
LA_DATA#1
A37
LA_DATA#2
F30
LB_DATA0
D29
LB_DATA1
F28
LB_DATA2
G30
LB_DATA#0
D30
LB_DATA#1
F29
LB_DATA#2
A32
LA_CLK
A33
LA_CLK#
E26
LB_CLK
E27
LB_CLK#
D32
LBKLT_CTL
J30
LBKLT_EN
H30
LCTLA_CLK
H29
LCTLB_DATA
G26
LDDC_CLK
G25
LDDC_DATA
F32
LVDD_EN
B38
LIBG
C35
LVBG
C33
LVREFH
C32
LVREFL
A16
TVDAC_A
C18
TVDAC_B
A19
TVDAC_C
J20
TV_IREF
B16
TV_IRTNA
B18
TV_IRTNB
B19
TV_IRTNC
J29
TV_DCONSEL1
K30
TV_DCONSEL0
C26
DDCCLK
C25
DDCDATA
H23
VSYNC
G23
HSYNC
E23
BLUE
D23
BLUE#
C22
GREEN
B22
GREEN#
A21
RED
B21
RED#
J22
CRT_IREF
CALISTOGA_FCBGA1466~D
LVDS
TV CRT
4
EXP_COMPI
EXP_COMPO
EXP_RXN0
EXP_RXN1
EXP_RXN2
EXP_RXN3
EXP_RXN4
EXP_RXN5
EXP_RXN6
EXP_RXN7
EXP_RXN8
EXP_RXN9
EXP_RXN10
EXP_RXN11
EXP_RXN12
EXP_RXN13
EXP_RXN14
EXP_RXN15
EXP_RXP0
EXP_RXP1
EXP_RXP2
EXP_RXP3
EXP_RXP4
EXP_RXP5
EXP_RXP6
EXP_RXP7
EXP_RXP8
EXP_RXP9
EXP_RXP10
EXP_RXP11
EXP_RXP12
EXP_RXP13
EXP_RXP14
EXP_RXP15
EXP_TXN0
EXP_TXN1
EXP_TXN2
EXP_TXN3
EXP_TXN4
EXP_TXN5
EXP_TXN6
EXP_TXN7
EXP_TXN8
PCI-EXPRESS GRAPHICS
EXP_TXN9
EXP_TXN10
EXP_TXN11
EXP_TXN12
EXP_TXN13
EXP_TXN14
EXP_TXN15
EXP_TXP0
EXP_TXP1
EXP_TXP2
EXP_TXP3
EXP_TXP4
EXP_TXP5
EXP_TXP6
EXP_TXP7
EXP_TXP8
EXP_TXP9
EXP_TXP10
EXP_TXP11
EXP_TXP12
EXP_TXP13
EXP_TXP14
EXP_TXP15
PEGCOMP
D40
D38
PEG_MRX_GTX_N0
F34
PEG_MRX_GTX_N1
G38
PEG_MRX_GTX_N2
H34
PEG_MRX_GTX_N3
J38
PEG_MRX_GTX_N4
L34
PEG_MRX_GTX_N5
M38
PEG_MRX_GTX_N6
N34
PEG_MRX_GTX_N7
P38
PEG_MRX_GTX_N8
R34
PEG_MRX_GTX_N9
T38
PEG_MRX_GTX_N10
V34
PEG_MRX_GTX_N11
W38
PEG_MRX_GTX_N12
Y34
PEG_MRX_GTX_N13
AA38
PEG_MRX_GTX_N14
AB34
PEG_MRX_GTX_N15
AC38
PEG_MRX_GTX_P0
D34
PEG_MRX_GTX_P1
F38
PEG_MRX_GTX_P2
G34
PEG_MRX_GTX_P3
H38
PEG_MRX_GTX_P4
J34
PEG_MRX_GTX_P5
L38
PEG_MRX_GTX_P6
M34
PEG_MRX_GTX_P7
N38
PEG_MRX_GTX_P8
P34
PEG_MRX_GTX_P9
R38
PEG_MRX_GTX_P10
T34
PEG_MRX_GTX_P11
V38
PEG_MRX_GTX_P12
W34
PEG_MRX_GTX_P13
Y38
PEG_MRX_GTX_P14
AA34
PEG_MRX_GTX_P15
AB38
PEG_MTX_GRX_C_N0
F36
PEG_MTX_GRX_C_N1
G40
PEG_MTX_GRX_C_N2
H36
PEG_MTX_GRX_C_N3
J40
PEG_MTX_GRX_C_N4
L36
PEG_MTX_GRX_C_N5
M40
PEG_MTX_GRX_C_N6
N36
PEG_MTX_GRX_C_N7
P40
PEG_MTX_GRX_C_N8
R36
PEG_MTX_GRX_C_N9
T40
PEG_MTX_GRX_C_N10
V36
PEG_MTX_GRX_C_N11
W40
PEG_MTX_GRX_C_N12
Y36
PEG_MTX_GRX_C_N13
AA40
PEG_MTX_GRX_C_N14
AB36
PEG_MTX_GRX_C_N15
AC40
PEG_MTX_GRX_C_P0
D36
PEG_MTX_GRX_C_P1
F40
PEG_MTX_GRX_C_P2
G36
PEG_MTX_GRX_C_P3
H40
PEG_MTX_GRX_C_P4
J36
PEG_MTX_GRX_C_P5
L40
PEG_MTX_GRX_C_P6
M36
PEG_MTX_GRX_C_P7
N40
PEG_MTX_GRX_C_P8
P36
PEG_MTX_GRX_C_P9
R40
PEG_MTX_GRX_C_P10
T36
PEG_MTX_GRX_C_P11
V40
PEG_MTX_GRX_C_P12
W36
PEG_MTX_GRX_C_P13
Y40
PEG_MTX_GRX_C_P14
AA36
PEG_MTX_GRX_C_P15
AB40
R1493
24.9_0402_1%~D
1 2
+1.5VRUN_PCIE
PEG_MTX_GRX_C_P0
PEG_MTX_GRX_C_N0
PEG_MTX_GRX_C_P1
PEG_MTX_GRX_C_N1
PEG_MTX_GRX_C_P2
PEG_MTX_GRX_C_N2
PEG_MTX_GRX_C_P3
PEG_MTX_GRX_C_N3
PEG_MTX_GRX_C_P4
PEG_MTX_GRX_C_N4
PEG_MTX_GRX_C_P5
PEG_MTX_GRX_C_N5
PEG_MTX_GRX_C_P6
PEG_MTX_GRX_C_N6
PEG_MTX_GRX_C_P7
PEG_MTX_GRX_C_N7
PEG_MTX_GRX_C_P8
PEG_MTX_GRX_C_N8
PEG_MTX_GRX_C_P9
PEG_MTX_GRX_C_N9
PEG_MTX_GRX_C_P10
PEG_MTX_GRX_C_N10
PEG_MTX_GRX_C_P11
PEG_MTX_GRX_C_N11
PEG_MTX_GRX_C_P12
PEG_MTX_GRX_C_N12
PEG_MTX_GRX_C_P13
PEG_MTX_GRX_C_N13
PEG_MTX_GRX_C_P14
PEG_MTX_GRX_C_N14
PEG_MTX_GRX_C_P15
PEG_MTX_GRX_C_N15
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
CFG5
CFG6
CFG7
CFG9
CFG11
CFG[13:12]
CFG16
(FSB Dynamic ODT)
CFG18
(VCC Select)
CFG19
(DMI Lane Reversal)
SDVO_CTRLDATA
CFG20
(PCIE/SDVO select)
C1561 0.1U_0402_16V4Z~D
1 2
C1563 0.1U_0402_16V4Z~D
C1565 0.1U_0402_16V4Z~D
C1567 0.1U_0402_16V4Z~D
C1569 0.1U_0402_16V4Z~D
C1571 0.1U_0402_16V4Z~D
C1573 0.1U_0402_16V4Z~D
C1575 0.1U_0402_16V4Z~D
C1577 0.1U_0402_16V4Z~D
C1579 0.1U_0402_16V4Z~D
C1581 0.1U_0402_16V4Z~D
C1583 0.1U_0402_16V4Z~D
C1585 0.1U_0402_16V4Z~D
C1587 0.1U_0402_16V4Z~D
C1589 0.1U_0402_16V4Z~D
C1591 0.1U_0402_16V4Z~D
C1562 0.1U_0402_16V4Z~D
1 2
C1564 0.1U_0402_16V4Z~D
1 2
C1566 0.1U_0402_16V4Z~D
1 2
C1568 0.1U_0402_16V4Z~D
1 2
C1570 0.1U_0402_16V4Z~D
1 2
C1572 0.1U_0402_16V4Z~D
1 2
C1574 0.1U_0402_16V4Z~D
1 2
C1576 0.1U_0402_16V4Z~D
1 2
C1578 0.1U_0402_16V4Z~D
1 2
C1580 0.1U_0402_16V4Z~D
1 2
C1582 0.1U_0402_16V4Z~D
1 2
C1584 0.1U_0402_16V4Z~D
1 2
C1586 0.1U_0402_16V4Z~D
1 2
C1588 0.1U_0402_16V4Z~D
1 2
C1590 0.1U_0402_16V4Z~D
1 2
C1592 0.1U_0402_16V4Z~D
Low = DMI x 2
High = DMI x 4
LOW = Moby Dick
HIGH = Calistoga
Low = DT/Transportable CPU
High = Mobile CPU
Low = Reverse Lane
High = Normal Operation
00 = Reserved
01 = XOR Mode Enabled
10 = All Z Mode Enabled
11 = Normal Operation
(Default)
Low = Disabled
High = Enabled
Low = 1.05V (Default)
High = 1.5V
Low = Normal
Operation (Default):
Lane number in Order
High = Reverse Lane
Low = No SDVO Device Present
High = SDVO Device Present
Low = Only PCIE or SDVO is
operational.
High = PCIE/SDVO are operating
simu.
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
(Default)
PEG_MTX_GRX_P0
PEG_MTX_GRX_N0
PEG_MTX_GRX_P1
PEG_MTX_GRX_N1
PEG_MTX_GRX_P2
PEG_MTX_GRX_N2
PEG_MTX_GRX_P3
PEG_MTX_GRX_N3
PEG_MTX_GRX_P4
PEG_MTX_GRX_N4
PEG_MTX_GRX_P5
PEG_MTX_GRX_N5
PEG_MTX_GRX_P6
PEG_MTX_GRX_N6
PEG_MTX_GRX_P7
PEG_MTX_GRX_N7
PEG_MTX_GRX_P8
PEG_MTX_GRX_N8
PEG_MTX_GRX_P9
PEG_MTX_GRX_N9
PEG_MTX_GRX_P10
PEG_MTX_GRX_N10
PEG_MTX_GRX_P11
PEG_MTX_GRX_N11
PEG_MTX_GRX_P12
PEG_MTX_GRX_N12
PEG_MTX_GRX_P13
PEG_MTX_GRX_N13
PEG_MTX_GRX_P14
PEG_MTX_GRX_N14
PEG_MTX_GRX_P15
PEG_MTX_GRX_N15
2
*
*
*
*
*
*
(Default)
R307 2.2K_0402_5%~D@
*
*
CFG510
CFG610
CFG710
CFG910
CFG1110
CFG1210
CFG1310
CFG1610
1 2
R67 2.2K_0402_5%~D@
1 2
R281 2.2K_0402_5%~D@
1 2
R282 2.2K_0402_5%~D@
1 2
R357 2.2K_0402_5%~D@
1 2
R288 2.2K_0402_5%~D@
1 2
R323 2.2K_0402_5%~D @
1 2
R346 2.2K_0402_5%~D@
1 2
CFG[3:17] have internal pullup
*
1 2
1 2
1 2
@
R308 1K_0402_5%~D
CFG1810
CFG1910
R306 1K_0402_5%~D@
CFG2010
R310 1K_0402_5%~D@
+3.3V_RUN
CFG[18:20] have internal pulldown
*
PEG_MRX_GTX_P[0:15]
PEG_MRX_GTX_N[0:15]
PEG_MTX_GRX_P[0:15]
PEG_MTX_GRX_N[0:15]
PEG_MRX_GTX_P[0:15] 52
PEG_MRX_GTX_N[0:15] 52
PEG_MTX_GRX_P[0:15] 52
PEG_MTX_GRX_N[0:15] 52
DELL CONFIDENTIAL/PROPRIETARY
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
Calistoga(3 of 6)
LA-2792
12 70Tuesday, Feb ru ar y 07, 2006
1
1.0
of
5
H
+1.05V_VCCP
CRB 270uF
D D
C391
C C
C118
0.22U_0402_10V4Z~D
B B
1
+
C411
2
220U_V_4VM_R45~D
1
1
C390
2
2
4.7U_0603_6.3V4Z~D
2.2U_0603_6.3V6K~D
U40_A6
1
C316
2
0.47U_0402_16V4Z~D
1
U40_D2
2
1
C164
U40_AB1
2
1
C435
0.22U_0402_10V4Z~D
2
0.47U_0402_16V4Z~D
+1.5V_RUN
U40H
AC14
VTT0
AB14
VTT1
W14
VTT2
V14
VTT3
T14
VTT4
R14
VTT5
P14
VTT6
N14
VTT7
M14
VTT8
L14
VTT9
AD13
VTT10
AC13
VTT11
AB13
VTT12
AA13
VTT13
Y13
VTT14
W13
VTT15
V13
VTT16
U13
VTT17
T13
VTT18
R13
VTT19
N13
VTT20
M13
VTT21
L13
VTT22
AB12
VTT23
AA12
VTT24
Y12
VTT25
W12
VTT26
V12
VTT27
U12
VTT28
T12
VTT29
R12
VTT30
P12
VTT31
N12
VTT32
M12
VTT33
L12
VTT34
R11
VTT35
P11
VTT36
N11
VTT37
M11
VTT38
R10
VTT39
P10
VTT40
N10
VTT41
M10
VTT42
P9
VTT43
N9
VTT44
M9
VTT45
R8
VTT46
P8
VTT47
N8
VTT48
M8
VTT49
P7
VTT50
N7
VTT51
M7
VTT52
R6
VTT53
P6
VTT54
M6
VTT55
A6
VTT56
R5
VTT57
P5
VTT58
N5
VTT59
M5
VTT60
P4
VTT61
N4
VTT62
M4
VTT63
R3
VTT64
P3
VTT65
N3
VTT66
M3
VTT67
R2
VTT68
P2
VTT69
M2
VTT70
D2
VTT71
AB1
VTT72
R1
VTT73
P1
VTT74
N1
VTT75
M1
VTT76
AG14
VCCAUX32
AF14
VCCAUX33
AE14
VCCAUX34
Y14
VCCAUX35
AF13
VCCAUX36
AE13
VCCAUX37
AF12
VCCAUX38
AE12
VCCAUX39
AD12
VCCAUX40
CALISTOGA_FCBGA1466~D
P O W E R
VCC_SYNC
VCCTX_LVDS0
VCCTX_LVDS1
VCCTX_LVDS2
VCC3G0
VCC3G1
VCC3G2
VCC3G3
VCC3G4
VCC3G5
VCC3G6
VCCA_3GPLL
VCCA_3GBG
VSSA_3GBG
VCCA_CRTDAC0
VCCA_CRTDAC1
VSSA_CRTDAC2
VCCA_DPLLA
VCCA_DPLLB
VCCA_HPLL
VCCA_LVDS
VSSA_LVDS
VCCA_MPLL
VCCA_TVBG
VSSA_TVBG
VCCA_TVDACA0
VCCA_TVDACA1
VCCA_TVDACB0
VCCA_TVDACB1
VCCA_TVDACC0
VCCA_TVDACC1
VCCD_HMPLL0
VCCD_HMPLL1
VCCD_LVDS0
VCCD_LVDS1
VCCD_LVDS2
VCCD_TVDAC
VCCDQ_TVDAC
VCCHV0
VCCHV1
VCCHV2
VCCAUX0
VCCAUX1
VCCAUX2
VCCAUX3
VCCAUX4
VCCAUX5
VCCAUX6
VCCAUX7
VCCAUX8
VCCAUX9
VCCAUX10
VCCAUX11
VCCAUX12
VCCAUX13
VCCAUX14
VCCAUX15
VCCAUX16
VCCAUX17
VCCAUX18
VCCAUX19
VCCAUX20
VCCAUX21
VCCAUX22
VCCAUX23
VCCAUX24
VCCAUX25
VCCAUX26
VCCAUX27
VCCAUX28
VCCAUX29
VCCAUX30
VCCAUX31
H22
B30
C30
A30
AB41
AJ41
L41
N41
R41
V41
Y41
AC33
G41
H41
E21
F21
G21
B26
C39
AF1
A38
B39
AF2
H20
G20
E19
F19
C20
D20
E20
F20
AH1
AH2
A28
B28
C28
D21
H19
A23
B23
B25
AK31
AF31
AE31
AC31
AL30
AK30
AJ30
AH30
AG30
AF30
AE30
AD30
AC30
AG29
AF29
AE29
AD29
AC29
AG28
AF28
AE28
AH22
AJ21
AH21
AJ20
AH20
AH19
P19
P16
AH15
P15
AH14
4
Should be placed on top
+1.5V_RUN
1
2
C49
C437
0.1U_0402_16V4Z~D
+1.5VRUN_PCIE
1
+
2
220U_V_4VM_R45~D
C336
0.1U_0402_16V4Z~D
BLM21PG600SN1D_0805~D
1
1
C59
C53
2
2
10U_0805_4VAM~D
C37
0.022U_0402_16V7K~D
+3.3V_RUN
1
1
C385
2
2
10U_0805_4VAM~D
W=30 mils
+1.5VRUN_3GPLL
+2.5V_RUN
+1.05V_VCCP
+1.5VRUN_DPLLA
+1.5VRUN_DPLLB
+1.5VRUN_HPLL
+1.5VRUN_MPLL
+1.5V_RUN
+1.5V_RUN
+1.5VRUN_QTVDAC
C404 should be placed in cavity
+1.5VRUN_3GPLL
C404
0.1U_0402_16V4Z~D
1
2
0.5_0805_1%~D
1
C311
2
10U_0805_4VAM~D
R267
1 2
12
L35
10U_0805_4VAM~D
BLM18PG181SN1_0603~D
1
1
C24
2
2
0.1U_0402_16V4Z~D
L34
BLM18PG181SN1_0603~D
3
+2.5V_RUN
1
+1.5V_RUN
L11
+1.5V_RUN
12
1
C332
2
0.1U_0402_16V4Z~D
12
C345
0.1U_0402_16V4Z~D
2
Route +2.5VRUN from GMCH pinG41 to
decoupling cap (C345)<200mil to the edge.
+1.5V_RUN+1.5VRUN_QTVDAC
+1.5VRUN_DPLLA +1.5VRUN_DPLLB
1
C413
2
1
2
L39
BLM18AG121SN1D_0603~D
1
C94
22U_0805_6.3VAM~D
2
0.1U_0402_16V4Z~D
R1748
0_0805_5%~D
C322
0.1U_0402_16V4Z~D
2
+1.5VRUN_MPLL+1.5VRUN_HPLL
12
+1.5V_RUN
12
+1.5V_RUN
45mA Max.45mA Max.
1
C418
2
0.1U_0402_16V4Z~D
40mA Max.40mA Max.
1
2
BLM18AG121SN1D_0603~D
1
C419
22U_0805_6.3VAM~D
2
0_0805_5%~D
C331
0.1U_0402_16V4Z~D
L38
12
R1749
12
1
+1.5V_RUN
+1.5V_RUN
A A
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
Calistoga(4 of 6)
LA-2792
13 70Tuesday, February 07, 2006
1
1.0
of
5
4
3
2
1
F
+1.05V_VCCP
D D
1
1
1
C383
C358
C379
2
0.22U_0402_10V4Z~D
1
C366
C C
2
10U_0805_4VAM~D
C367
C423
0.22U_0402_10V4Z~D
10U_0805_4VAM~D
220U_V_4VM_R45~D
2
2
0.22U_0402_10V4Z~D
1
1
C368
2
2
1U_0603_10V4Z~D
1
+
2
CRB 270uF
1
B B
A A
C620
+
2
220U_V_4VM_R45~D
+1.05V_VCCP
U40F
AD27
VCC_NCTF0
AC27
VCC_NCTF1
AB27
VCC_NCTF2
AA27
VCC_NCTF3
Y27
VCC_NCTF4
W27
VCC_NCTF5
V27
VCC_NCTF6
U27
VCC_NCTF7
T27
VCC_NCTF8
R27
VCC_NCTF9
AD26
VCC_NCTF10
AC26
VCC_NCTF11
AB26
VCC_NCTF12
AA26
VCC_NCTF13
Y26
VCC_NCTF14
W26
VCC_NCTF15
V26
VCC_NCTF16
U26
VCC_NCTF17
T26
VCC_NCTF18
R26
VCC_NCTF19
AD25
VCC_NCTF20
AC25
VCC_NCTF21
AB25
VCC_NCTF22
AA25
VCC_NCTF23
Y25
VCC_NCTF24
W25
VCC_NCTF25
V25
VCC_NCTF26
U25
VCC_NCTF27
T25
VCC_NCTF28
R25
VCC_NCTF29
AD24
VCC_NCTF30
AC24
VCC_NCTF31
AB24
VCC_NCTF32
AA24
VCC_NCTF33
Y24
VCC_NCTF34
W24
VCC_NCTF35
V24
VCC_NCTF36
U24
VCC_NCTF37
T24
VCC_NCTF38
R24
VCC_NCTF39
AD23
VCC_NCTF40
V23
VCC_NCTF41
U23
VCC_NCTF42
T23
VCC_NCTF43
R23
VCC_NCTF44
AD22
VCC_NCTF45
V22
VCC_NCTF46
U22
VCC_NCTF47
T22
VCC_NCTF48
R22
VCC_NCTF49
AD21
VCC_NCTF50
V21
VCC_NCTF51
U21
VCC_NCTF52
T21
VCC_NCTF53
R21
VCC_NCTF54
AD20
VCC_NCTF55
V20
VCC_NCTF56
U20
VCC_NCTF57
T20
VCC_NCTF58
R20
VCC_NCTF59
AD19
VCC_NCTF60
V19
VCC_NCTF61
U19
VCC_NCTF62
T19
VCC_NCTF63
AD18
VCC_NCTF64
AC18
VCC_NCTF65
AB18
VCC_NCTF66
AA18
VCC_NCTF67
Y18
VCC_NCTF68
W18
VCC_NCTF69
V18
VCC_NCTF70
U18
VCC_NCTF71
T18
VCC_NCTF72
M19
VCC100
L19
VCC101
N18
VCC102
M18
VCC103
L18
VCC104
P17
VCC105
N17
VCC106
M17
VCC107
N16
VCC108
M16
VCC109
L16
VCC110
CALISTOGA_FCBGA1466~D
VCCAUX_NCTF0
VCCAUX_NCTF1
VCCAUX_NCTF2
VCCAUX_NCTF3
VCCAUX_NCTF4
VCCAUX_NCTF5
VCCAUX_NCTF6
VCCAUX_NCTF7
VCCAUX_NCTF8
VCCAUX_NCTF9
VCCAUX_NCTF10
VCCAUX_NCTF11
VCCAUX_NCTF12
VCCAUX_NCTF13
VCCAUX_NCTF14
VCCAUX_NCTF15
VCCAUX_NCTF16
VCCAUX_NCTF17
VCCAUX_NCTF18
VCCAUX_NCTF19
VCCAUX_NCTF20
VCCAUX_NCTF21
VCCAUX_NCTF22
VCCAUX_NCTF23
VCCAUX_NCTF24
VCCAUX_NCTF25
VCCAUX_NCTF26
VCCAUX_NCTF27
VCCAUX_NCTF28
VCCAUX_NCTF29
VCCAUX_NCTF30
VCCAUX_NCTF31
VCCAUX_NCTF32
VCCAUX_NCTF33
VCCAUX_NCTF34
VCCAUX_NCTF35
VCCAUX_NCTF36
P O W E R
VCCAUX_NCTF37
VCCAUX_NCTF38
VCCAUX_NCTF39
VCCAUX_NCTF40
VCCAUX_NCTF41
VCCAUX_NCTF42
VCCAUX_NCTF43
VCCAUX_NCTF44
VCCAUX_NCTF45
VCCAUX_NCTF46
VCCAUX_NCTF47
VCCAUX_NCTF48
VCCAUX_NCTF49
VCCAUX_NCTF50
VCCAUX_NCTF51
VCCAUX_NCTF52
VCCAUX_NCTF53
VCCAUX_NCTF54
VCCAUX_NCTF55
VCCAUX_NCTF56
VCCAUX_NCTF57
VSS_NCTF0
VSS_NCTF1
VSS_NCTF2
VSS_NCTF3
VSS_NCTF4
VSS_NCTF5
VSS_NCTF6
VSS_NCTF7
VSS_NCTF8
VSS_NCTF9
VSS_NCTF10
VSS_NCTF11
VSS_NCTF12
VCC_SM100
VCC_SM101
VCC_SM102
VCC_SM103
VCC_SM104
VCC_SM105
VCC_SM106
VCC_SM107
+1.5V_RUN
AG27
AF27
AG26
AF26
AG25
AF25
AG24
AF24
AG23
AF23
AG22
AF22
AG21
AF21
AG20
AF20
AG19
AF19
R19
AG18
AF18
R18
AG17
AF17
AE17
AD17
AB17
AA17
W17
V17
T17
R17
AG16
AF16
AE16
AD16
AC16
AB16
AA16
Y16
W16
V16
U16
T16
R16
AG15
AF15
AE15
AD15
AC15
AB15
AA15
Y15
W15
V15
U15
T15
R15
AE27
AE26
AE25
AE24
AE23
AE22
AE21
AE20
AE19
AE18
AC17
Y17
U17
VCCSM_LF2
VCCSM_LF1
+1.8V_SUS
1
C613
2
0.47U_0402_16V4Z~D
C614
1
2
0.47U_0402_16V4Z~D
AR6
AP6
AN6
AL6
AK6
AJ6
AV1
AJ1
Place near U40.AV1 & AJ1
G
+1.05V_VCCP
AA33
W33
P33
N33
AA32
Y32
W32
V32
P32
N32
M32
AA31
W31
V31
T31
R31
P31
N31
M31
AA30
Y30
W30
V30
U30
T30
R30
P30
N30
M30
AA29
Y29
W29
V29
U29
R29
P29
M29
AB28
AA28
Y28
V28
U28
T28
R28
P28
N28
M28
P27
N27
M27
P26
N26
N25
M25
P24
N24
M24
AB23
AA23
Y23
P23
N23
M23
AC22
AB22
Y22
W22
P22
N22
M22
AC21
AA21
W21
N21
M21
AC20
AB20
Y20
W20
P20
N20
M20
AB19
AA19
Y19
N19
U40G
VCC0
VCC1
VCC2
VCC3
L33
VCC4
J33
VCC5
VCC6
VCC7
VCC8
VCC9
VCC10
VCC11
VCC12
L32
VCC13
J32
VCC14
VCC15
VCC16
VCC17
VCC18
VCC19
VCC20
VCC21
VCC22
VCC23
VCC24
VCC25
VCC26
VCC27
VCC28
VCC29
VCC30
VCC31
VCC32
L30
L29
L28
L27
L26
L25
L23
L22
L21
L20
P O W E R
VCC33
VCC34
VCC35
VCC36
VCC37
VCC38
VCC39
VCC40
VCC41
VCC42
VCC43
VCC44
VCC45
VCC46
VCC47
VCC48
VCC49
VCC50
VCC51
VCC52
VCC53
VCC54
VCC55
VCC56
VCC57
VCC58
VCC59
VCC60
VCC61
VCC62
VCC63
VCC64
VCC65
VCC66
VCC67
VCC68
VCC69
VCC70
VCC71
VCC72
VCC73
VCC74
VCC75
VCC76
VCC77
VCC78
VCC79
VCC80
VCC81
VCC82
VCC83
VCC84
VCC85
VCC86
VCC87
VCC88
VCC89
VCC90
VCC91
VCC92
VCC93
VCC94
VCC95
VCC96
VCC97
VCC98
VCC99
CALISTOGA_FCBGA1466~D
VCC_SM0
VCC_SM1
VCC_SM2
VCC_SM3
VCC_SM4
VCC_SM5
VCC_SM6
VCC_SM7
VCC_SM8
VCC_SM9
VCC_SM10
VCC_SM11
VCC_SM12
VCC_SM13
VCC_SM14
VCC_SM15
VCC_SM16
VCC_SM17
VCC_SM18
VCC_SM19
VCC_SM20
VCC_SM21
VCC_SM22
VCC_SM23
VCC_SM24
VCC_SM25
VCC_SM26
VCC_SM27
VCC_SM28
VCC_SM29
VCC_SM30
VCC_SM31
VCC_SM32
VCC_SM33
VCC_SM34
VCC_SM35
VCC_SM36
VCC_SM37
VCC_SM38
VCC_SM39
VCC_SM40
VCC_SM41
VCC_SM42
VCC_SM43
VCC_SM44
VCC_SM45
VCC_SM46
VCC_SM47
VCC_SM48
VCC_SM49
VCC_SM50
VCC_SM51
VCC_SM52
VCC_SM53
VCC_SM54
VCC_SM55
VCC_SM56
VCC_SM57
VCC_SM58
VCC_SM59
VCC_SM60
VCC_SM61
VCC_SM62
VCC_SM63
VCC_SM64
VCC_SM65
VCC_SM66
VCC_SM67
VCC_SM68
VCC_SM69
VCC_SM70
VCC_SM71
VCC_SM72
VCC_SM73
VCC_SM74
VCC_SM75
VCC_SM76
VCC_SM77
VCC_SM78
VCC_SM79
VCC_SM80
VCC_SM81
VCC_SM82
VCC_SM83
VCC_SM84
VCC_SM85
VCC_SM86
VCC_SM87
VCC_SM88
VCC_SM89
VCC_SM90
VCC_SM91
VCC_SM92
VCC_SM93
VCC_SM94
VCC_SM95
VCC_SM96
VCC_SM97
VCC_SM98
VCC_SM99
AU41
AT41
AM41
AU40
BA34
AY34
AW34
AV34
AU34
AT34
AR34
BA30
AY30
AW30
AV30
AU30
AT30
AR30
AP30
AN30
AM30
AM29
AL29
AK29
AJ29
AH29
AJ28
AH28
AJ27
AH27
BA26
AY26
AW26
AV26
AU26
AT26
AR26
AJ26
AH26
AJ25
AH25
AJ24
AH24
BA23
AJ23
BA22
AY22
AW22
AV22
AU22
AT22
AR22
AP22
AK22
AJ22
AK21
AK20
BA19
AY19
AW19
AV19
AU19
AT19
AR19
AP19
AK19
AJ19
AJ18
AJ17
AH17
AJ16
AH16
BA15
AY15
AW15
AV15
AU15
AT15
AR15
AJ15
AJ14
AJ13
AH13
AK12
AJ12
AH12
AG12
AK11
BA8
AY8
AW8
AV8
AT8
AR8
AP8
BA6
AY6
AW6
AV6
AT6
+1.8V_SUS
VCCSM_LF4
VCCSM_LF5
C615
1
1
C612
2
2
0.47U_0402_16V4Z~D
0.47U_0402_16V4Z~D
Place near U40.AT41 & AM41
1
0.47U_0402_16V4Z~D
C441
2
0.1U_0402_16V4Z~D
1
2
C438
C616
Place near U40.BA23
1
C160
C617
C158
2
10U_0805_4VAM~D
0.47U_0402_16V4Z~D
10U_0805_4VAM~D
1
2
Place near U40.BA15
1
2
1
2
1
C444
2
0.1U_0402_16V4Z~D
1
+
C165
2
@
330U_D2E_2.5VM_R9~D
1
C452
2
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
Calistoga(5 of 6)
LA-2792
14 70Tuesday, Feb ru ar y 07, 2006
1
1.0
of
5
4
3
2
1
U40I
AC41
VSS0
AA41
VSS1
W41
VSS2
T41
VSS3
P41
D D
C C
B B
A A
VSS4
M41
VSS5
J41
VSS6
F41
VSS7
AV40
VSS8
AP40
VSS9
AN40
VSS10
AK40
VSS11
AJ40
VSS12
AH40
VSS13
AG40
VSS14
AF40
VSS15
AE40
VSS16
B40
VSS17
AY39
VSS18
AW39
VSS19
AV39
VSS20
AR39
VSS21
AN39
VSS22
AJ39
VSS23
AC39
VSS24
AB39
VSS25
AA39
VSS26
Y39
VSS27
W39
VSS28
V39
VSS29
T39
VSS30
R39
VSS31
P39
VSS32
N39
VSS33
M39
VSS34
L39
VSS35
J39
VSS36
H39
VSS37
G39
VSS38
F39
VSS39
D39
VSS40
AT38
VSS41
AM38
VSS42
AH38
VSS43
AG38
VSS44
AF38
VSS45
AE38
VSS46
C38
VSS47
AK37
VSS48
AH37
VSS49
AB37
VSS50
AA37
VSS51
Y37
VSS52
W37
VSS53
V37
VSS54
T37
VSS55
R37
VSS56
P37
VSS57
N37
VSS58
M37
VSS59
L37
VSS60
J37
VSS61
H37
VSS62
G37
VSS63
F37
VSS64
D37
VSS65
AY36
VSS66
AW36
VSS67
AN36
VSS68
AH36
VSS69
AG36
VSS70
AF36
VSS71
AE36
VSS72
AC36
VSS73
C36
VSS74
B36
VSS75
BA35
VSS76
AV35
VSS77
AR35
VSS78
AH35
VSS79
AB35
VSS80
AA35
VSS81
Y35
VSS82
W35
VSS83
V35
VSS84
T35
VSS85
R35
VSS86
P35
VSS87
N35
VSS88
M35
VSS89
L35
VSS90
J35
VSS91
H35
VSS92
G35
VSS93
F35
VSS94
D35
VSS95
AN34
VSS96
AK34
VSS97
AG34
VSS98
AF34
VSS99
CALISTOGA_FCBGA1466~D
P O W E R
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS140
VSS141
VSS142
VSS143
VSS144
VSS145
VSS146
VSS147
VSS148
VSS149
VSS150
VSS151
VSS152
VSS153
VSS154
VSS155
VSS156
VSS157
VSS158
VSS159
VSS160
VSS161
VSS162
VSS163
VSS164
VSS165
VSS166
VSS167
VSS168
VSS169
VSS170
VSS171
VSS172
VSS173
VSS174
VSS175
VSS176
VSS177
VSS178
VSS179
VSS180
VSS181
VSS182
VSS183
VSS184
VSS185
VSS186
VSS187
VSS188
VSS189
VSS190
VSS191
VSS192
VSS193
VSS194
VSS195
VSS196
VSS197
VSS198
VSS199
AE34
AC34
C34
AW33
AV33
AR33
AE33
AB33
Y33
V33
T33
R33
M33
H33
G33
F33
D33
B33
AH32
AG32
AF32
AE32
AC32
AB32
G32
B32
AY31
AV31
AN31
AJ31
AG31
AB31
Y31
AB30
E30
AT29
AN29
AB29
T29
N29
K29
G29
E29
C29
B29
A29
BA28
AW28
AU28
AP28
AM28
AD28
AC28
W28
J28
E28
AP27
AM27
AK27
J27
G27
F27
C27
B27
AN26
M26
K26
F26
D26
AK25
P25
K25
H25
E25
D25
A25
BA24
AU24
AL24
AW23
AT23
AN23
AM23
AH23
AC23
W23
K23
J23
F23
C23
AA22
K22
G22
F22
E22
D22
A22
BA21
AV21
AR21
I
J
U40J
AN21
VSS200
AL21
VSS201
AB21
VSS202
Y21
VSS203
P21
VSS204
K21
VSS205
J21
VSS206
H21
VSS207
C21
VSS208
AW20
VSS209
AR20
VSS210
AM20
VSS211
AA20
VSS212
K20
VSS213
B20
VSS214
A20
VSS215
AN19
VSS216
AC19
VSS217
W19
VSS218
K19
VSS219
G19
VSS220
C19
VSS221
AH18
VSS222
P18
VSS223
H18
VSS224
D18
VSS225
A18
VSS226
AY17
VSS227
AR17
VSS228
AP17
VSS229
AM17
VSS230
AK17
VSS231
AV16
VSS232
AN16
VSS233
AL16
VSS234
J16
VSS235
F16
VSS236
C16
VSS237
AN15
VSS238
AM15
VSS239
AK15
VSS240
N15
VSS241
M15
VSS242
L15
VSS243
B15
VSS244
A15
VSS245
BA14
VSS246
AT14
VSS247
AK14
VSS248
AD14
VSS249
AA14
VSS250
U14
VSS251
K14
VSS252
H14
VSS253
E14
VSS254
AV13
VSS255
AR13
VSS256
AN13
VSS257
AM13
VSS258
AL13
VSS259
AG13
VSS260
P13
VSS261
F13
VSS262
D13
VSS265
B13
VSS264
AY12
VSS263
AC12
VSS266
K12
VSS267
H12
VSS268
E12
VSS269
AD11
VSS270
AA11
VSS271
Y11
VSS272
J11
VSS273
D11
VSS274
B11
VSS275
AV10
VSS276
AP10
VSS277
AL10
VSS278
AJ10
VSS279
CALISTOGA_FCBGA1466~D
P O W E R
VSS280
VSS281
VSS282
VSS283
VSS284
VSS285
VSS286
VSS287
VSS288
VSS289
VSS290
VSS292
VSS291
VSS293
VSS294
VSS295
VSS296
VSS297
VSS298
VSS299
VSS300
VSS301
VSS302
VSS303
VSS304
VSS305
VSS306
VSS307
VSS308
VSS309
VSS310
VSS311
VSS312
VSS313
VSS314
VSS315
VSS316
VSS317
VSS318
VSS319
VSS320
VSS321
VSS322
VSS323
VSS324
VSS325
VSS326
VSS327
VSS328
VSS329
VSS330
VSS331
VSS332
VSS333
VSS334
VSS335
VSS336
VSS337
VSS338
VSS339
VSS340
VSS341
VSS342
VSS343
VSS344
VSS345
VSS346
VSS347
VSS348
VSS349
VSS350
VSS351
VSS352
VSS353
VSS354
VSS355
VSS356
VSS357
VSS358
VSS359
VSS360
AG10
AC10
W10
U10
BA9
AW9
AR9
AH9
AB9
Y9
R9
G9
E9
A9
AG8
AD8
AA8
U8
K8
C8
BA7
AV7
AP7
AL7
AJ7
AH7
AF7
AC7
R7
G7
D7
AG6
AD6
AB6
Y6
U6
N6
K6
H6
B6
AV5
AF5
AD5
AY4
AR4
AP4
AL4
AJ4
Y4
U4
R4
J4
F4
C4
AY3
AW3
AV3
AL3
AH3
AG3
AF3
AD3
AC3
AA3
G3
AT2
AR2
AP2
AK2
AJ2
AD2
AB2
Y2
U2
T2
N2
J2
H2
F2
C2
AL1
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
Calistoga(6 of 6)
LA-2792
15 70Tuesday, Feb ru ar y 07, 2006
1
1.0
of
5
DDR_A_DQS#[0..7]11
DDR_A_D[0..63]11
DDR_A_DM[0..7]11
DDR_A_DQS[0..7]11
DDR_A_MA[0..13]11
D D
+1.8V_SUS
2.2U_0603_6.3V6K~D
2.2U_0603_6.3V6K~D
C213
C214
1
1
2
2
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
C212
1
2
C C
+0.9V_DDR_VTT
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
1
2
B B
A A
C221
DDR_A_MA1
DDR_A_MA3
56_0404_4P2R_5%~D
DDR_A_BS0
DDR_A_MA10
56_0404_4P2R_5%~D
DDR_A_RAS#
DDR_CS0_DIMMA#
56_0404_4P2R_5%~D
DDR_A_CAS#
DDR_A_WE#
56_0404_4P2R_5%~D
M_ODT1
DDR_CS1_DIMMA#
56_0404_4P2R_5%~D
DDR_CKE0_DIMMA
DDR_A_BS2
56_0404_4P2R_5%~D
Layout Note:
Place one cap close to every 2 pullup
resistors terminated to +0.9V_DDR_VTT
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
1
1
1
2
2
2
C220
C218
C219
RN25
1 4
2 3
RN24
1 4
2 3
RN16
1 4
2 3
RN23
1 4
2 3
RN22
1 4
2 3
RN21
2 3
1 4
5
2.2U_0603_6.3V6K~D
1
2
C215
1
2
0.1U_0402_16V4Z~D
1
2
C217
+0.9V_DDR_VTT
C222
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
2.2U_0603_6.3V6K~D
1
2
C223
1
2
0.1U_0402_16V4Z~D
1
2
C216
RN27
RN19
RN26
RN18
RN17
RN15
RN20
C225
0.1U_0402_16V4Z~D
1
2
1
2
C231
14
23
56_0404_4P2R_5%~D
14
23
56_0404_4P2R_5%~D
14
23
56_0404_4P2R_5%~D
14
23
56_0404_4P2R_5%~D
14
23
56_0404_4P2R_5%~D
14
23
56_0404_4P2R_5%~D
14
23
56_0404_4P2R_5%~D
2.2U_0603_6.3V6K~D
C229
1
2
C227
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
1
2
C232
DDR_A_MA9
DDR_A_MA12
DDR_A_MA7
DDR_A_MA6
DDR_A_MA5
DDR_A_MA8
DDR_A_MA4
DDR_A_MA2
DDR_A_MA0
DDR_A_BS1
M_ODT0
DDR_A_MA13
DDR_CKE1_DIMMA
DDR_A_MA11
Layout Note:
Place near JDIM1
0.1U_0402_16V4Z~D
1
1
2
2
C233
C235
4
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
1
1
2
2
C237
C236
Layout Note:
Place these resistor
closely DIMM0,all
trace length<750 mil
Layout Note:
Place these resistor
closely DIMM0,all
trace length
Max=1.3"
4
3
+1.8V_SUS +1.8V_SUS
ON TOP SIDE
JDIM2
1
VREF
3
2.2U_0603_6.3V6K~D
C230
VSS
5
DQ0
7
DQ1
9
VSS
11
DQS0#
13
DQS0
15
VSS
17
DQ2
19
DQ3
21
VSS
23
DQ8
25
DQ9
27
VSS
29
DQS1#
31
DQS1
33
VSS
35
DQ10
37
DQ11
39
VSS
41
VSS
43
DQ16
45
DQ17
47
VSS
49
DQS2#
51
DQS2
53
VSS
55
DQ18
57
DQ19
59
VSS
61
DQ24
63
DQ25
65
VSS
67
DM3
69
NC
71
VSS
73
DQ26
75
DQ27
77
VSS
79
CKE0
81
VDD
83
NC
85
BA2
87
VDD
89
A12
91
A9
93
A8
95
VDD
97
A5
99
A3
101
A1
103
VDD
105
A10/AP
107
BA0
109
WE#
111
VDD
113
CAS#
115
NC/S1#
117
VDD
119
NC/ODT1
121
VSS
123
DQ32
125
DQ33
127
VSS
129
DQS4#
131
DQS4
133
VSS
135
DQ34
137
DQ35
139
VSS
141
DQ40
143
DQ41
145
VSS
147
DM5
149
VSS
151
DQ42
153
DQ43
155
VSS
157
DQ48
159
DQ49
161
VSS
163
NC,TEST
165
VSS
167
DQS6#
169
DQS6
171
VSS
173
DQ50
175
DQ51
177
VSS
179
DQ56
181
DQ57
183
VSS
185
DM7
187
VSS
189
DQ58
191
DQ59
193
VSS
195
SDA
197
SCL
199
VDDSPD
201
GND
TYCO_1470815-2~D
RESERVE
DDR_A_D0
DDR_A_D1
DDR_A_DQS#0
DDR_A_DQS0
DDR_A_D3
DDR_A_D2
DDR_A_D14
DDR_A_D8
DDR_A_DQS#1
DDR_A_DQS1
DDR_A_D11
DDR_A_D10
DDR_A_D20
DDR_A_D17
DDR_A_DQS#2
DDR_A_DQS2
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D29
DDR_A_DM3
DDR_A_D31 DDR_A_D26
DDR_A_D27
DDR_CKE0_DIMMA10
DDR_A_BS211
DDR_A_BS011
DDR_A_WE#11
DDR_A_CAS#11
DDR_CS1_DIMMA#10
M_ODT110
0.1U_0402_16V4Z~D
1
2
C234
CLK_SDATA6,17
CLK_SCLK6,17
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
DDR_CKE0_DIMMA
DDR_A_BS2
DDR_A_MA12
DDR_A_MA9 DDR_A_MA7
DDR_A_MA8
DDR_A_MA5
DDR_A_MA3
DDR_A_MA1
DDR_A_MA10
DDR_A_BS0
DDR_A_WE#
DDR_A_CAS#
DDR_CS1_DIMMA#
M_ODT1
DDR_A_D35
DDR_A_D32
DDR_A_DQS#4
DDR_A_DQS4
DDR_A_D34
DDR_A_D33
DDR_A_D43
DDR_A_D45
DDR_A_DM5
DDR_A_D47
DDR_A_D48
DDR_A_D52
DDR_A_DQS#6
DDR_A_DQS6
DDR_A_D55
DDR_A_D51
DDR_A_D60
DDR_A_D61
DDR_A_DM7
DDR_A_D58
DDR_A_D59
CLK_SDATA
CLK_SCLK
+3.3V_RUN
0.1U_0402_16V4Z~D
C228
1
1
2
2
DIMMA
2
VSS
DQ4
DQ5
VSS
DM0
VSS
DQ6
DQ7
VSS
DQ12
DQ13
VSS
DM1
VSS
CK0
CK0#
VSS
DQ14
DQ15
VSS
VSS
DQ20
DQ21
VSS
DM2
VSS
DQ22
DQ23
VSS
DQ28
DQ29
VSS
DQS3#
DQS3
VSS
DQ30
DQ31
VSS
NC/CKE1
VDD
NC/A15
NC/A14
VDD
A11
VDD
VDD
BA1
RAS#
S0#
VDD
ODT0
NC/A13
VDD
VSS
DQ36
DQ37
VSS
DM4
VSS
DQ38
DQ39
VSS
DQ44
DQ45
VSS
DQS5#
DQS5
VSS
DQ46
DQ47
VSS
DQ52
DQ53
VSS
CK1
CK1#
VSS
DM6
VSS
DQ54
DQ55
VSS
DQ60
DQ61
VSS
DQS7#
DQS7
VSS
DQ62
DQ63
VSS
SAO
SA1
GND
2
1
V_DDR_MCH_REF
2
DDR_A_D7
4
DDR_A_D4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
NC
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
A7
94
A6
96
98
A4
100
A2
102
A0
104
106
108
110
112
114
116
118
120
NC
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
DDR_A_DM0
DDR_A_D6
DDR_A_D5
DDR_A_D13
DDR_A_D12
DDR_A_DM1
M_CLK_DDR0
M_CLK_DDR#0
DDR_A_D15
DDR_A_D9
DDR_A_D16
DDR_A_D21
PM_EXTTS#0_R
DDR_A_DM2
DDR_A_D18
DDR_A_D19
DDR_A_D28
DDR_A_D25
DDR_A_DQS#3
DDR_A_DQS3
DDR_A_D30
DDR_CKE1_DIMMA
DDR_A_MA11
DDR_A_MA6
DDR_A_MA4
DDR_A_MA2
DDR_A_MA0
DDR_A_BS1
DDR_A_RAS#
DDR_CS0_DIMMA#
M_ODT0
DDR_A_MA13
DDR_A_D36
DDR_A_D37
DDR_A_DM4
DDR_A_D39
DDR_A_D38
DDR_A_D44
DDR_A_D40
DDR_A_DQS#5
DDR_A_DQS5
DDR_A_D41DDR_A_D46
DDR_A_D42
DDR_A_D49
DDR_A_D53
M_CLK_DDR1
M_CLK_DDR#1
DDR_A_DM6
DDR_A_D50
DDR_A_D54
DDR_A_D57
DDR_A_D56
DDR_A_DQS#7
DDR_A_DQS7
DDR_A_D62
DDR_A_D63
R175 100K_0402_5%~D
1 2
R176 100K_0402_5%~D
1 2
2.2U_0603_6.3V6K~D
1
C226
2
M_CLK_DDR0 10
M_CLK_DDR#0 10
1 2
R177
0_0402_5%~D
DDR_CKE1_DIMMA 10
DDR_A_BS1 11
DDR_A_RAS# 11
DDR_CS0_DIMMA# 10
M_ODT0 10
M_CLK_DDR1 10
M_CLK_DDR#1 10
0.1U_0402_16V4Z~D
1
2
C224
12
PM_EXTTS#0_R 17
PM_EXTTS#0 10
V_DDR_MCH_REF 10,17,48
R51
100K_0402_5%~D
DELL CONFIDENTIAL/PROPRIETARY
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
DDRII-SODIMM SLOT1
LA-2792
16 70Tuesday, Feb ru ar y 07, 2006
1
1.0
of
5
DDR_B_DQS#[0..7]11
DDR_B_D[0..63]11
DDR_B_DM[0..7]11
DDR_B_DQS[0..7]11
DDR_B_MA[0..13]11
D D
C C
B B
A A
+1.8V_SUS
+0.9V_DDR_VTT
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
1
2
C248
DDR_B_MA1
DDR_B_MA3
56_0404_4P2R_5%~D
DDR_B_BS0
DDR_B_MA10
56_0404_4P2R_5%~D
DDR_B_MA0
DDR_B_BS1
56_0404_4P2R_5%~D
DDR_B_RAS#
DDR_CS2_DIMMB#
56_0404_4P2R_5%~D
DDR_B_CAS#
DDR_B_WE#
56_0404_4P2R_5%~D
DDR_CS3_DIMMB#
M_ODT3
56_0404_4P2R_5%~D
2.2U_0603_6.3V6K~D
2.2U_0603_6.3V6K~D
1
2
0.1U_0402_16V4Z~D
C239
RN13
RN7
RN12
RN6
RN5
RN2
RN14
C261
1
2
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
1
2
C244
2.2U_0603_6.3V6K~D
C242
1
2
0.1U_0402_16V4Z~D
C251
1
2
0.1U_0402_16V4Z~D
1
2
C243
DDR_B_MA9
14
DDR_B_MA12
23
56_0404_4P2R_5%~D
DDR_CKE3_DIMMB
14
DDR_B_MA11
23
56_0404_4P2R_5%~D
DDR_B_MA5
14
DDR_B_MA8
23
56_0404_4P2R_5%~D
DDR_B_MA7
14
DDR_B_MA6
23
56_0404_4P2R_5%~D
DDR_B_MA4
14
DDR_B_MA2
23
56_0404_4P2R_5%~D
M_ODT2
14
DDR_B_MA13
23
56_0404_4P2R_5%~D
DDR_B_BS2
14
DDR_CKE2_DIMMB
23
56_0404_4P2R_5%~D
2.2U_0603_6.3V6K~D
1
2
C247
1 4
2 3
1 4
2 3
1 4
2 3
1 4
2 3
1 4
2 3
2 3
1 4
C254
C249
1
1
2
2
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
C240
1
2
Layout Note:
Place one cap close to every 2 pullup
resistors terminated to +0.9V_DDR_VTT
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
1
1
2
2
C245
C246
+0.9V_DDR_VTT
RN11
RN10
RN4
RN3
RN9
RN8
5
2.2U_0603_6.3V6K~D
C241
1
2
C255
1
2
0.1U_0402_16V4Z~D
1
1
2
2
C269
Layout Note:
Place near JDIM2
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
1
2
C268
C267
4
0.1U_0402_16V4Z~D
1
2
C266
Layout Note:
Place these resistor
closely DIMM0,all
trace length<750 mil
Layout Note:
Place these resistor
closely DIMM0,all
trace length
Max=1.3"
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
1
1
2
2
C265
C264
4
3
ON BOTTOM SIDE
DDR_B_D0
DDR_B_DQS#0
DDR_B_DQS0
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_DQS#1
DDR_B_DQS1
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D21
DDR_B_DQS#2
DDR_B_DQS2
DDR_B_D19
DDR_B_D18
DDR_B_D26
DDR_B_D28
DDR_B_DM3
DDR_B_D29
DDR_B_D27
+3.3V_RUN
DDR_CKE2_DIMMB
DDR_B_BS2
DDR_B_MA12
DDR_B_MA9
DDR_B_MA8
DDR_B_MA5
DDR_B_MA3
DDR_B_MA1
DDR_B_MA10
DDR_B_BS0
DDR_B_WE#
DDR_B_CAS#
DDR_CS3_DIMMB#
M_ODT3
DDR_B_D33
DDR_B_D32
DDR_B_DQS#4
DDR_B_DQS4
DDR_B_D34
DDR_B_D41
DDR_B_D40
DDR_B_DM5
DDR_B_D43
DDR_B_D46
DDR_B_D49
DDR_B_D48
DDR_B_DQS#6
DDR_B_DQS6
DDR_B_D55
DDR_B_D50
DDR_B_D56
DDR_B_DM7
DDR_B_D58
DDR_B_D59
CLK_SDATA
CLK_SCLK
0.1U_0402_16V4Z~D
C549
1
2
2.2U_0603_6.3V6K~D
1
2
DDR_CKE2_DIMMB10
DDR_B_BS211
DDR_B_BS011
DDR_B_WE#11
DDR_B_CAS#11
DDR_CS3_DIMMB#10
1
2
C263
M_ODT310
CLK_SDATA6,16
CLK_SCLK6,16
C548
JDIM1
1
VREF
3
VSS
5
DQ0
7
DQ1
9
VSS
11
DQS0#
13
DQS0
15
VSS
17
DQ2
19
DQ3
21
VSS
23
DQ8
25
DQ9
27
VSS
29
DQS1#
31
DQS1
33
VSS
35
DQ10
37
DQ11
39
VSS
41
VSS
43
DQ16
45
DQ17
47
VSS
49
DQS2#
51
DQS2
53
VSS
55
DQ18
57
DQ19
59
VSS
61
DQ24
63
DQ25
65
VSS
67
DM3
69
NC
71
VSS
73
DQ26
75
DQ27
77
VSS
79
CKE0
81
VDD
83
NC
85
BA2
87
VDD
89
A12
91
A9
93
A8
95
VDD
97
A5
99
A3
101
A1
103
VDD
105
A10/AP
107
BA0
109
WE#
111
VDD
113
CAS#
115
NC/S1#
117
VDD
119
NC/ODT1
121
VSS
123
DQ32
125
DQ33
127
VSS
129
DQS4#
131
DQS4
133
VSS
135
DQ34
137
DQ35
139
VSS
141
DQ40
143
DQ41
145
VSS
147
DM5
149
VSS
151
DQ42
153
DQ43
155
VSS
157
DQ48
159
DQ49
161
VSS
163
NC,TEST
165
VSS
167
DQS6#
169
DQS6
171
VSS
173
DQ50
175
DQ51
177
VSS
179
DQ56
181
DQ57
183
VSS
185
DM7
187
VSS
189
DQ58
191
DQ59
193
VSS
195
SDA
197
SCL
199
VDDSPD
201
GND
TYCO_1565917-4~D
DIMMB
STANDARD
VSS
DQ4
DQ5
VSS
DM0
VSS
DQ6
DQ7
VSS
DQ12
DQ13
VSS
DM1
VSS
CK0
CK0#
VSS
DQ14
DQ15
VSS
VSS
DQ20
DQ21
VSS
DM2
VSS
DQ22
DQ23
VSS
DQ28
DQ29
VSS
DQS3#
DQS3
VSS
DQ30
DQ31
VSS
NC/CKE1
VDD
NC/A15
NC/A14
VDD
VDD
VDD
BA1
RAS#
VDD
ODT0
NC/A13
VDD
VSS
DQ36
DQ37
VSS
DM4
VSS
DQ38
DQ39
VSS
DQ44
DQ45
VSS
DQS5#
DQS5
VSS
DQ46
DQ47
VSS
DQ52
DQ53
VSS
CK1
CK1#
VSS
DM6
VSS
DQ54
DQ55
VSS
DQ60
DQ61
VSS
DQS7#
DQS7
VSS
DQ62
DQ63
VSS
SAO
SA1
GND
NC
A11
A7
A6
A4
A2
A0
S0#
NC
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
2
+1.8V_SUS+1.8V_SUS
DDR_B_D5
DDR_B_D4DDR_B_D1
DDR_B_DM0
DDR_B_D2
DDR_B_D3
DDR_B_D12
DDR_B_D13
DDR_B_DM1
M_CLK_DDR3
M_CLK_DDR#3
DDR_B_D10
DDR_B_D11
DDR_B_D17
DDR_B_D20
PM_EXTTS#0_R
DDR_B_DM2
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_DQS#3
DDR_B_DQS3
DDR_B_D30
DDR_B_D31
DDR_CKE3_DIMMB
DDR_B_MA11
DDR_B_MA7
DDR_B_MA6
DDR_B_MA4
DDR_B_MA2
DDR_B_MA0
DDR_B_BS1
DDR_B_RAS#
DDR_CS2_DIMMB#
M_ODT2
DDR_B_MA13
DDR_B_D36
DDR_B_D37
DDR_B_DM4
DDR_B_D38
DDR_B_D39DDR_B_D35
DDR_B_D44
DDR_B_D45
DDR_B_DQS#5
DDR_B_DQS5
DDR_B_D42
DDR_B_D47
DDR_B_D52
DDR_B_D53
M_CLK_DDR2
M_CLK_DDR#2
DDR_B_DM6
DDR_B_D54
DDR_B_D51
DDR_B_D60DDR_B_D61
DDR_B_D57
DDR_B_DQS#7
DDR_B_DQS7
DDR_B_D62
DDR_B_D63
100K_0402_5%~D
12
R173
V_DDR_MCH_REF
2.2U_0603_6.3V6K~D
1
C253
2
M_CLK_DDR3 10
M_CLK_DDR#3 10
PM_EXTTS#0_R 16
DDR_CKE3_DIMMB 10
DDR_B_BS1 11
DDR_B_RAS# 11
DDR_CS2_DIMMB# 10
M_ODT2 10
M_CLK_DDR2 10
M_CLK_DDR#2 10
+3.3V_RUN
12
R174
10K_0402_5%~D
1
1
C252
2
V_DDR_MCH_REF 10,16,48
0.1U_0402_16V4Z~D
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
DDRII-SODIMM SLOT2
LA-2792
17 70Tuesday, Feb ru ar y 07, 2006
1
1.0
of
5
4
3
2
1
FAN1 Control and Tachometer
+3.3V_RUN
12
VCP
VCP
DN1
DP1
LDO_SET
LDO_IN
LDO_IN
VDD_5V
R476
2.21K_0402_1%~D
R481
2.21K_0603_1%~D
17
3
40
41
31
36
37
30
4
22
24
25
27
26
28
5
1
C1777
0.1U_0402_16V4Z~D
2
VCP1
VCP2
REM_DIODE1_N
REM_DIODE1_P
LDO_SET
+3V_LDOIN
+5V_RUN
D D
2 1
C41
12
R249
332K_0402_1%~D
12
R262
118K_0402_1%~D
1
C210
C1779
2
@
22U_0805_6.3VAM~D
1
C341
2
1
2
1
C44
0.1U_0402_16V4Z~D
2
1 2
R41 8.2K_0402_5%~D
VGA_THERMDP53
VGA_THERMDN53
D35
RB751S40T1_SOD523-2~D
C C
DP2, DN2 routing together. Trace
width / Spacing = 10 / 10 mil
+3.3V_SUS
12
R241
8.2K_0402_5%~D
2
B
2
B
C
E
3 1
12
C
E
3 1
THERMATRIP1#
1
Q39
C42
0.1U_0402_16V4Z~D
2
MMST3904-7-F_SOT323~D
R239
8.2K_0402_5%~D
THERMATRIP2#
1
Q34
C43
0.1U_0402_16V4Z~D
2
MMST3904-7-F_SOT323~D
0.1U_0402_16V4Z~D
VGA_THERMDN, VGA_THERMDP routing together.
Trace width / Spacing = 10 / 10 mil
Place cap close to the
Guardian pins as possible.
+1.05V_VCCP
R40
1 2
2.2K_0402_5%~D
H_THERMTRIP#7
B B
+1.05V_VCCP
THERMTRIP_MCH#10
A A
R39
1 2
2.2K_0402_5%~D
5
+3.3V_SUS
@
Place C341 close to the Guardian
pins as possible
H_THERMDA7
2200P_0402_50V7K~D
H_THERMDC7
+3.3V_SUS
+3.3V_SUS
C303
R50
49.9_0603_1%~D
1 2
0.1U_0402_16V4Z~D
+RTC_CELL
THERMTRIP_VGA#52
1
2
4
R413
10K_0402_5%~D
1
C1778
100P_0402_50V8J~D
@
2
+FAN1_VOUT
FAN1_TACH
1
2
22U_0805_6.3VAM~D
+3.3V_SUS
+3VSUS_THRM
SUSPWROK23,42
ICH_PWRGD#42
POWER_SW#39,40
1
2
R61
1 2
C317
SNIFFER_GREEN#43
SNIFFER_YELLOW#43
1K_0402_5%~D
2200P_0402_50V7K~D
C1773
2200P_0402_50V7K~D
Place C1773 close to the
Guardian pins as possible
FAN1_TACH 39
JFAN1
1
1
2
2
3
3
MOLEX_53398-0371~D
VSET=
VSET =
R262
R249+R262
Tp-70
x 3.3V
21
U15
R136
1 2
1
2
SNIFFER_GREEN#
SNIFFER_YELLOW#
DAT_SMB39
CLK_SMB39
7.5K_0402_5%~D
1 2
R42 1K_0402_5%~D
1 2
R38 1K_0402_5%~D
THERMATRIP1#
THERMATRIP2#
THERMATRIP3#
VGA_THERMDP
VGA_THERMDN
+FAN1_VOUT
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
7
SMDATA
8
SMBCLK
23
LDO_SHDN#_ADDR
35
DP2
34
DN2
12
+3V_SUS
21
VSUS_PWRGD
18
+RTC_PWR3V
13
+3V_PWROK#
38
POWER_SW#
14
THERMTRIP1#
15
THERMTRIP2#
16
THERMTRIP3#
39
VSET
29
HW_LOCK#
9
VSS
1
DP3
2
DN3
6
FAN_OUT
33
FAN_DAC
10
GPIO1
11
GPIO2
19
GPIO3
20
GPIO4
32
GPIO5
EMC4000 C_QFN40~D
SMBUS ADDRESS : 2F
ATF_INT#
PAD_GND
LDO_POK
THERMTRIP_SIO
ACAV_CLR
SYS_SHDN#
LDO_OUT
LDO_OUT
1
C1776
2
10U_0805_10V4Z~D
Place near t h e bottom SODIMM
+5V_SUS +5V_SUS
12
VCP1
1
C66
2200P_0402_50V7K~D
2
R477
1 2
10K_0603_1%_TSM1A103F34D3RZ~D
13
D
S
G
2N7002W-7-F_SOT323~D
R477 place near the bottom SODIMM
Place near the bottom SODIMM
12
VCP2
1
C36
2200P_0402_25V7K~D
2
R479 place on bottom side
next to SoDIMM connector
Place C47 clos e to the Guardian
pins as possible
+3.3V_ALW
1
1
C1774
2
2
10U_0805_10V4Z~D
1
C571
2
1U_0603_10V4Z~D
2
R479
1 2
10K_0603_1%_TSM1A103F34D3RZ~D
2N7002W-7-F_SOT323~D
12
R60
10K_0402_5%~D
C150
0.1U_0402_16V4Z~D
@
0.27_1210_5%~D
1
C152
0.1U_0402_16V4Z~D
2
@
Q21
ATF_INT# 39
REM_DIODE1_N , R E M _D I O D E1_P routing together.
Trace width / S p a cing = 10 / 10 mil
2.5V_RUN_PWRGD 42
1
C47
2
2200P_0402_50V7K~D
THERMTRIP_SIO 38
ACAV_IN 39,50,51
+2.5V_RUN
R1643
12
DELL CONFIDENTIAL/PROPRIETARY
Title
Size Document Number Rev
Date: Sheet
13
D
2
G
S
Place under CPU
+3.3V_RUN
Compal Electronics, Inc.
FAN & Thermal Sensor
2
Q15
+5V_SUS+5V_SUS
E
31
B
2
C
@
LA-2792
12
R478
10K_0402_5%~D
12
R480
10K_0402_5%~D
5V_CAL_SIO2# 38
1
Q12
2
MMST3904-7-F_SOT323~D
R1634
10K_0402_5%~D
12
@
31.6K_0402_1%~D
LDO_SET
1
5V_CAL_SIO# 38
C1803
@
2200P_0402_50V7K~D
+RTC_CELL
THERM_STP# 46
+2.5V_RUN
12
R1800
12
R1789
1K_0402_5%~D
18 70Tuesday, Feb ru ar y 07, 2006
1.0
of
5
D D
JLVDS
45
MGND1
46
MGND2
47
MGND3
48
MGND4
49
MGND5
50
MGND6
51
MGND7
52
MGND8
53
MGND9
54
MGND10
55
MGND11
56
NC
57
C C
B B
TXLCLKOUT-
NC
TXLCLKOUT+
PANEL_I2C_CLK
PANEL_I2C_DAT
PNL_SLFTST
LCDPWR_SRC
LCDPWR_SRC
LCDPWR_SRC
PBAT_SMBCLK
PBAT_SMBDAT
LAMP_START
IPEX_20330-044E-11F~D
TXUCLKUT-
TXUCLKUT+
GND1
TXUOUT2-
TXUOUT2+
GND2
TXUOUT1-
TXUOUT1+
GND3
TXUOUT0-
TXUOUT0+
GND4
GND5
TXLOUT2ÂTXLOUT2+
GND6
TXLOUT1-
TXLOUT1+
GND7
TXLOUT0ÂTXLOUT0+
GND8
GND9
VEDID
GND10
LCDVDD1
LCDVDD2
GND11
FPBACK
GND12
GND13
+5V_ALWF
GND14
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
LCD_BCLKÂLCD_BCLK+
LCD_B2ÂLCD_B2+
LCD_B1ÂLCD_B1+
LCD_B0ÂLCD_B0+
LCD_ACLKÂLCD_ACLK+
LCD_A2ÂLCD_A2+
LCD_A1ÂLCD_A1+
LCD_A0ÂLCD_A0+
LCD_DDCCLK
LCD_DDCDATA
LCD_TST
LAMP_D_STAT#
1
2
LCD_TST 23
C296
0.1U_0603_50V4Z~D
4
LCD_BCLK- 53
LCD_BCLK+ 53
LCD_B2- 53
LCD_B2+ 53
LCD_B1- 53
LCD_B1+ 53
LCD_B0- 53
LCD_B0+ 53
LCD_ACLK- 53
LCD_ACLK+ 53
LCD_A2- 53
LCD_A2+ 53
LCD_A1- 53
LCD_A1+ 53
LCD_A0- 53
LCD_A0+ 53
LCD_DDCCLK 52
LCD_DDCDATA 52
0.1U_0402_16V4Z~D
SBAT_SMBCLK 39,45
SBAT_SMBDAT 39,45
D2
RB751S40T1_SOD523-2~D
@
+INV_PWR_SRC
FPBACK_EN38
PANEL_BKEN52
+3.3V_RUN
C26
0.1U_0402_16V4Z~D
BACKLITEON
1 2
1
2
LAMP_STAT#
R1760
100K_0402_5%~D
+LCDVDD
C27
1
1
2
2
R520 0_0402_5%~D
21
M'07 inverter support - Depop D2.
D'05 inverter support - Populate D2
1 2
R1767 0_0402_5%~D
12
+3.3V_RUN
12
+5V_ALW
C28
0.1U_0402_16V4Z~D
LAMP_STAT# 23
FPBACK_EN
PANEL_BKEN
1
2
X01 support M07 inverter
R92
10K_0402_5%~D
BIA_PWM 39,52
+3.3V_RUN
5
U7
P
IN1
4
O
IN2
G
74AHC1G08GW_SOT353-5~D
3
@
3
+LCDVDD
ENVDD52
BACKLITEON for D'05;
BIA_PWM for M'07
BACKLITEON
12
R35
470_0402_5%~D
13
D
Q37
2
G
2N7002W-7-F_SOT323~D
S
2
1
2
+15V_SUS
I
40mil
C290
1000P_0402_50V7K~D
2
12
R54
100K_0402_5%~D
2
G
1
O
Q8
G
DDTC124EUA-7-F_SOT323~D
3
+PWR_SRC
12
R235
100K_0402_5%~D
1 2
100K_0402_5%~D
+15V_SUS
12
13
D
S
R236
RUN_ON37,39,41,42,46,47,48,58
+LCDVDD
R272
100K_0402_5%~D
1
Q10
2
2N7002W-7-F_SOT323~D
Q32
FDS4435_NL_SO8~D
8
7
1
6
2
5
3
4
D
S
1 3
G
2
Q9
SI3456BDV-T1-E3_TSOP6~D
D
S
4 5
G
3
12
R79
@
100K_0402_5%~D
C315
0.1U_0603_50V4Z~D
+INV_PWR_SRC
40mil
1
C289
0.1U_0603_50V4Z~D
2
Q29
2N7002W-7-F_SOT323~D
FDS4435: P CHANNAL
1
6
2
1
+3.3V_RUN
1
C29
2
0.1U_0402_16V4Z~D
M'07 inverter support - Populate R520,R1767 Depop U7.
D'05 inverter support - Populate U7, Depop R520,R1767
A A
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
Internal LVDS
LA-2792
19 70Tuesday, Feb ru ar y 07, 2006
1
1.0
of
5
D D
4
3
2
1
D29
DA204U_SOT323~D
1
@
+3.3V_RUN
2
3
L78
VGA_RED36,52
VGA_GRN36,52
C C
VGA_BLU36,52
VGA_RED
VGA_GRN
VGA_BLU
12
75_0402_1%
R1396
12
75_0402_1%
R1397
12
75_0402_1%
R1398
22P_0402_50V8J~D
1
2
C1408
@
1
2
C1406
@
22P_0402_50V8J~D
1
2
C1407
@
Evaluate Package
DAT_DDC236,52
CLK_DDC236,52
+5V_RUN
B B
VGA_HSYNC52
VGA_VSYNC52
D2005 SDM10U45-7_SOD523-2~D
2 1
R1404
1 2
39_0402_5%~D
R1405
1 2
39_0402_5%~D
SN74AHCT1G125GW_SC70-5~D
R1403
1K_0402_5%~D
1 2
1
5
U190
P
4
OE#
A2Y
G
3
5
P
A2Y
G
3
R101
0_0402_5%~D
1
4
OE#
R114
0_0402_5%~D
U191
SN74AHCT1G125GW_SC70-5~D
1 2
1 2
BLM18BB600SN1D_0603~D
1 2
BLM18BB600SN1D_0603~D
1 2
BLM18BB600SN1D_0603~D
1 2
22P_0402_50V8J~D
L81
BLM18AG121SN1D_0603~D
1 2
HSYNC_R 36
VSYNC_R 36
L82
BLM18AG121SN1D_0603~D
1 2
CRT_VCC
R1399
1K_0402_5%~D
C1414
L79
L80
@
22P_0402_50V8J~D
1
C1409
10P_0402_50V8J~D
2
@
12
1
2
12
@
R1400
1K_0402_5%~D
1
2
C1415
22P_0402_50V8J~D
R1401
1 2
R1402
2.2K_0402_5%~D
1 2
2.2K_0402_5%~D
0.1U_0402_16V4Z~D
2
1
C1410
10P_0402_50V8J~D
2
@
T46 PAD~D
D30
DA204U_SOT323~D
1
@
3
1
C1413
2
1
2
D31
DA204U_SOT323~D
1
@
2
3
C1411
10P_0402_50V8J~D
@
D32
SDM10U45-7_SOD523-2~D
+5V_RUN
21
C1412
0.01U_0402_16V7K~D
RED
DAT_DDC2
GREEN
JVGA_HS
BLUE
CRT_VCC
JVGA_VS
M_ID2#
CLK_DDC2
1
2
CRT_VCC
JCRT
6
11
1
7
12
2
8
16
13
17
3
9
14
4
10
15
5
SUYIN_070915FR015S201CU~D
A A
DA204U
K1
A2
DELL CONFIDENTIAL/PROPRIETARY
A1 K2
5
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
4
3
2
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
CRT
LA-2792
20 70Tuesday, Feb ru ar y 07, 2006
1
1.0
of
5
PCI_AD[0..31]30,35
D D
C C
B B
+3.3V_RUN
1 2
R254 8.2K_0402_5%~D
1 2
R46 8.2K_0402_5%~D
1 2
R47 8.2K_0402_5%~D
1 2
R258 8.2K_0402_5%~D
1 2
R327 8.2K_0402_5%~D
1 2
R69 8.2K_0402_5%~D
1 2
R257 8.2K_0402_5%~D
1 2
R255 8.2K_0402_5%~D
+3.3V_RUN
1 2
R43 8.2K_0402_5%~D
1 2
R45 8.2K_0402_5%~D
1 2
R44 8.2K_0402_5%~D
1 2
R286 8.2K_0402_5%~D
1 2
R350 8.2K_0402_5%~D
1 2
R324 8.2K_0402_5%~D
1 2
R309 8.2K_0402_5%~D
1 2
R315 8.2K_0402_5%~D
1 2
R317 8.2K_0402_5%~D
1 2
R72 8.2K_0402_5%~D
1 2
R340 8.2K_0402_5%~D
1 2
R77 8.2K_0402_5%~D
1 2
R256 8.2K_0402_5%~D
1 2
R339 8.2K_0402_5%~D
PCI_DEVSEL#
PCI_STOP#
PCI_TRDY#
PCI_FRAME#
PCI_PLOCK#
PCI_IRDY#
PCI_SERR#
PCI_PERR#
PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#
ICH_GPIO2_PIRQE#
ICH_GPIO3_PIRQF#
ICH_GPIO4_PIRQG#
ICH_GPIO5_PIRQH#
PCI_REQ0#
PCI_REQ1#
PCI_REQ2#
PCI_REQ3#
PCI_REQ4#
PCI_REQ5#
4
PCI_AD0
PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD6
PCI_AD7
PCI_AD8
PCI_AD9
PCI_AD10
PCI_AD11
PCI_AD12
PCI_AD13
PCI_AD14
PCI_AD15
PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20
PCI_AD21
PCI_AD22
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30
PCI_AD31
PCI_PIRQA#35
PCI_PIRQC#30
PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#
U45B
E18
AD0
C18
AD1
A16
AD2
F18
AD3
E16
AD4
A18
AD5
E17
AD6
A17
AD7
A15
AD8
C14
AD9
E14
AD10
D14
AD11
B12
AD12
C13
AD13
G15
AD14
G13
AD15
E12
AD16
C11
AD17
D11
AD18
A11
AD19
A10
AD20
F11
AD21
F10
AD22
E9
AD23
D9
AD24
B9
AD25
A8
AD26
A6
AD27
C7
AD28
B6
AD29
E6
AD30
D6
AD31
Interrupt I/F
A3
PIRQA#
B4
PIRQB#
C5
PIRQC#
B5
PIRQD#
AE5
RSVD[1]
AD5
RSVD[2]
AG4
RSVD[3]
AH4
RSVD[4]
AD9
RSVD[5]
PCI
REQ4# / GPIO22
GNT4# / GPIO48
GPIO1 / REQ5#
GPIO17 / GNT5#
GPIO2 / PIRQE#
GPIO3 / PIRQF#
GPIO4 / PIRQG#
GPIO5 / PIRQH#
MISC
MCH_SYNC#
ICH7M A0_BGA 6 52~D
REQ0#
GNT0#
REQ1#
GNT1#
REQ2#
GNT2#
REQ3#
GNT3#
C/BE0#
C/BE1#
C/BE2#
C/BE3#
IRDY#
PAR
PCIRST#
DEVSEL#
PERR#
PLOCK#
SERR#
STOP#
TRDY#
FRAME#
PLTRST#
PCICLK
PME#
RSVD[6]
RSVD[7]
RSVD[8]
RSVD[9]
D7
E7
C16
D16
C17
D17
E13
F13
A13
A14
C8
D8
B15
C12
D12
C15
A7
E10
B18
A12
C9
E11
B10
F15
F14
F16
C26
A9
B19
G8
F7
F8
G7
AE9
AG8
AH8
F21
AH20
3
PCI_REQ0#
PCI_GNT0#
PCI_REQ1#
PCI_GNT1#
PCI_REQ2#
PCI_REQ3#
PCI_REQ4#
PCI_GNT4#
PCI_REQ5#
PCI_GNT5#
PCI_C_BE0#
PCI_C_BE1#
PCI_C_BE2#
PCI_C_BE3#
PCI_IRDY#
PCI_PAR
PCI_PCIRST#
PCI_DEVSEL#
PCI_PERR#
PCI_PLOCK#
PCI_SERR#
PCI_STOP#
PCI_TRDY#
PCI_FRAME#
PCI_PLTRST#
CLK_PCI_ICH
ICH_PME#
ICH_GPIO2_PIRQE#
ICH_GPIO3_PIRQF#
ICH_GPIO4_PIRQG#
ICH_GPIO5_PIRQH#
MCH_ICH_SYNC# 10
PCI_REQ0# 36
PCI_GNT0# 35,36
PCI_REQ1# 30
PCI_GNT1# 30
PCI_C_BE0# 30,35
PCI_C_BE1# 30,35
PCI_C_BE2# 30,35
PCI_C_BE3# 30,35
PCI_ I RDY# 30,35,36
PCI_PAR 30,35
PCI_DEVSEL# 30,35
PCI_PERR# 30,35
PCI_PLOCK# 35
PCI_SERR# 35
PCI_STOP# 30,35
PCI_TRDY# 30,35
PCI_FRAME# 30,35,36
CLK_PCI_ICH 6
ICH_PME# 38
PCI_PCIRST#
PCI_PLTRST#
2
+3.3V_SUS
14
U21A
1
P
IN1
3
OUT
2
IN2
G
74VHC08MTCX_NL_TSSOP14~D
7
+3.3V_SUS
14
U21C
10
P
9
13
12
4
5
IN1
OUT
IN2
G
7
+3.3V_SUS
14
P
IN1
OUT
IN2
G
7
+3.3V_SUS
14
P
IN1
OUT
IN2
G
7
PCI_RST#
8
74VHC08MTCX_NL_TSSOP14~D
U21D
PLTRST#
11
74VHC08MTCX_NL_TSSOP14~D
U21B
PLTRST2#
6
74VHC08MTCX_NL_TSSOP14~D
PCI_RST# 30,31,35
PLTRST# 10,23,28,34
PLTRST2# 38,39
1
Place closely pin U45.A9
CLK_PCI_ICH
R332
@
10_0402_5%~D
C349
@
8.2P_0402_50V8J~D
1 2
1
2
LPC
12
(11)
PCI_GNT5#PCI_GNT4#
R347
1K_0402_5%~D@
GNT5#
R328
unstuffunstuff
12
R328
1K_0402_5%~D
GNT4#
R347
PCI
(10)
SPI
(01)
A A
unstuff stuff
stuff
unstuff
*
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
ICH7(1/4)
LA-2792
21 70Tuesday, Feb ru ar y 07, 2006
1
1.0
of
5
C38
2.2P_0402_50V8C
12
Package
D D
C C
PSATA_ITX_DRX_N025
PSATA_ITX_DRX_P025
+3.3V_RUN
B B
9.6X4.06 mm
+RTC_CELL
Place near ICH7 side.
R414
IDE_IRQ
12
8.2K_0402_5%~D
C40
2.2P_0402_50V8C
12
CMOS
@SHORT PADS~D
1
1U_0603_10V4Z~D
MDC_AC_BITCLK33
ICH_SYNC_MDC33
ICH_RST_MDC#33
ICH_AC_SDIN026
ICH_AC_SDIN133
ICH_SDOUT_MDC33
12
C270 3900P_0402_50V7K~D
12
C271
3900P_0402_50V7K~D
32.768KHZ_6PF_1TJS060BJ4A376P~D
X1
1 4
2 3
ICH_RTCX2
1 2
R297 20K_0402_5%~D
1 2
R301 332K_0402_1%~D
1 2
R276 1M_0402_5%~D
1
C348
1 2
SATA_ACT#43
2
2
C499 27P_0402_50V8J~D@
PSATA_IRX_DTX_N0_C25
PSATA_IRX_DTX_P0_C25
0_0402_5%~D
12
CLK_PCIE_SATA#6
CLK_PCIE_SATA6
IDE_DIORDY25
IDE_IRQ25
IDE_DDACK#25
IDE_DIOW#25
IDE_DIOR#25
R12
1 2
1 2
1 2
1 2
R371
1 2
33_0402_5%~D
R380 24.9_0402_1%~D
1 2
Within 500 mils
4
ICH_RTCX1
R36
ICH_RTCRST#
ICH_INTVRMEN
SM_INTRUDER#
R55333_0402_5%~D
R8133_0402_5%~D
R8333_0402_5%~D
ICH_AC_SDOUT_R
SATA_ACT#
PSATA_IRX_DTX_N0_C
PSATA_IRX_DTX_P0_C
PSATA_ITX_DRX_N0_C
PSATA_ITX_DRX_P0_C
CLK_PCIE_SATA#
CLK_PCIE_SATA
IDE_DIORDY
IDE_IRQ
IDE_DDACK#
IDE_DIOW#
IDE_DIOR#
12
10M_0402_5%~D
ICH_AC_BITCLK_R
ICH_AC_SYNC_R
ICH_AC_RST_R#
ICH_AC_SDIN0
ICH_AC_SDIN1
AF18
AG2
AH2
AG6
AH6
AH10
AG10
AG16
AH16
AF16
AH15
AF15
AB1
AB2
AA3
W4
Y5
W1
Y1
Y2
W3
V3
U3
U5
V4
T5
U7
V6
V7
U1
R6
R5
T2
T3
T1
T4
AF3
AE3
AF7
AE7
AF1
AE1
U45A
RTCX1
RTCX2
RTCRST#
INTVRMEN
INTRUDER#
EE_CS
EE_SHCLK
EE_DOUT
EE_DIN
LAN_CLK
LAN_RSTSYNC
LAN_RXD0
LAN_RXD1
LAN_RXD2
LAN_TXD0
LAN_TXD1
LAN_TXD2
ACZ_BCLK
ACZ_SYNC
ACZ_RST#
ACZ_SDIN0
ACZ_SDIN1
ACZ_SDIN2
ACZ_SDOUT
SATALED#
SATA0RXN
SATA0RXP
SATA0TXN
SATA0TXP
SATA2RXN
SATA2RXP
SATA2TXN
SATA2TXP
SATA_CLKN
SATA_CLKP
SATARBIASN
SATARBIASP
IORDY
IDEIRQ
DDACK#
DIOW#
DIOR#
RTC
GPIO49 / CPUPWRGD
ICH7M A0_BGA 6 52~D
LPCCPU
LDRQ1# / GPIO23
LFRAME#
LAN
A20GATE
CPUSLP#
TP1 / DPRSTP#
TP2 / DPSLP#
INIT3_3V#
STPCLK#
THERMTRIP#
SATA
IDE
LAD0
LAD1
LAD2
LAD3
LDRQ0#
A20M#
FERR#
IGNNE#
INIT#
INTR
AC-97/AZALIA
RCIN#
SMI#
DCS1#
DCS3#
DD10
DD11
DD12
DD13
DD14
DD15
DDREQ
NMI
DA0
DA1
DA2
DD0
DD1
DD2
DD3
DD4
DD5
DD6
DD7
DD8
DD9
AA6
AB5
AC4
Y6
AC3
AA5
AB3
AE22
AH28
AG27
AF24
AH25
AG26
AG24
AG22
AG21
AF22
AF25
AG23
AF23
AH24
AH22
AF26
AH17
AE17
AF17
AE16
AD16
AB15
AE14
AG13
AF13
AD14
AC13
AD12
AC12
AE12
AF12
AB13
AC14
AF14
AH13
AH14
AC15
AE15
3
LPC_LAD0
LPC_LAD1
LPC_LAD2
LPC_LAD3
LPC_LDRQ0#
LPC_LDRQ1#
LPC_LFRAME#
H_CPUSLP_R#
DPRSLP#
H_FERR#
THRMTRIP_ICH#
IDE_DA0
IDE_DA1
IDE_DA2
IDE_DCS1#
IDE_DCS3#
IDE_DD0
IDE_DD1
IDE_DD2
IDE_DD3
IDE_DD4
IDE_DD5
IDE_DD6
IDE_DD7
IDE_DD8
IDE_DD9
IDE_DD10
IDE_DD11
IDE_DD12
IDE_DD13
IDE_DD14
IDE_DD15
IDE_DDREQ
LPC_LAD[0..3] 28,38,39
LPC_LDRQ0# 38
LPC_LDRQ1# 38
LPC_LFRAME# 28,38,39
R438 0_0402_5%~D@
R121 0_0402_5%~D
IDE_DA[0..2] 25
IDE_DCS1# 25
IDE_DCS3# 25
IDE_DD[0..15]
IDE_DDREQ 25
12
12
1
0.1U_0402_16V4Z~D
2
IDE_DD[0..15] 25
SIO_A20GATE
H_A20M#
H_CPUSLP#
H_DPRSTP#
H_DPSLP#
H_PWRGOOD
H_IGNNE#
H_INIT#
H_INTR
SIO_RCIN#
H_SMI#
H_NMI
H_STPCLK#
1 2
C69
@
2
R115
56_0402_5%~D
SIO_A20GATE 39
H_A20M# 7
H_CPUSLP# 7,10
H_DPRSTP# 7,49
H_DPSLP# 7
H_FERR# 7
H_PWRGOOD 7
H_IGNNE# 7
H_INIT# 7
H_INTR 7
SIO_RCIN# 39
H_SMI# 7
H_NMI 7
H_STPCLK# 7
+1.05V_VCCP
1
H_DPRSTP# daisy
ICH7-M --> Yonah --> IMVP6
+1.05V_VCCP
12
+3.3V_RUN
12
12
H_FERR#
SIO_RCIN#
SIO_A20GATE
R118
56_0402_5%~D
R277
10K_0402_5%~D
R1631
10K_0402_5%~D
Close to U45
R378
33_0402_5%~D
ICH_AC_SDOUT_R
ICH_SDOUT_AUDIO26
ICH_SYNC_AUDIO26
ICH_RST_AUDIO#26
A A
ICH_AC_BITCLK26
5
1 2
R82
33_0402_5%~D
1 2
R84
33_0402_5%~D
1 2
R189
33_0402_5%~D
1 2
1
C503
27P_0402_50V8J~D
2
@
ICH_AC_SYNC_R
ICH_AC_RST_R#
ICH_AC_BITCLK_R
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
4
3
2
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
ICH7(2/4)
LA-2792
22 70Tuesday, Feb ru ar y 07, 2006
1
1.0
of
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