Compal LA-2761, Aspire 3600, Aspire 5500, Aspire 5500Z, TravelMate 2400 Schematic

A

B

C

D

E

Page Index

===============

P01-Cover Page
P02-Block Diagram
P03-Notes List
P04-Dothan(1/2)

1 1

Compal Confidential

EFL50/ EFT51 Schematics Document

2 2

Intel Dothan/ Celeron M/ Alviso GM(PM) / DDR-2 / ICH6-M

(Daughter Card: ATi M24P/ M26P)

2005 / 03 / 08 (B-Test EVT)

Rev:0.2

3 3

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2005/03/08 2006/03/08

C

Compal Secret Data

Deciphered Date

Custom

D

P05-Dothan(2/2)
P06-Alviso HOST(1/5)
P07-Alviso DDR(2/5)
P08-Alviso PCI-E(3/5)
P09-Alviso POWER(4/5)
P10-Alviso POWER(5/5)
P11-DDRI-SODIMM0
P12-DDRI-SODIMM1
P13-DDR Decoupling
P14-Clock Generator
P15-CRT Conn.
P16-VGA / LCD Conn.
P17-ICH6(1/4)_HUB,PCI,HOST
P18-ICH6(2/4)_CPU,AC97,IDE,LPC
P19-ICH6(3/4)_USB,PM,LAN,GPIO
P20-ICH6(4/4)_POWER&GND
P21-HDD/CDROM
P22-DVI / TV_Out Conn
P23-PCMCIA ENE CB1410 & CB714
P24-PCMCIA SOCKET
P25-TI 1394A TSB43AB21A
P26-LAN BCM5788M
P27-LAN Magnetic & RJ45/RJ11
P28-Mimi-PCI Slot
P29-AC97 Codec_ALC250D
P30-Audio Line in Switch
P31-AMP & Audio Jack
P32-Super IO SMC217
P33-ENE-KB910
P34-MDC / BT / KBD / TP Conn.
P35-BIOS & I/O Port & SATA HDD
P36-RJ11/LID Switch / Fan / FIR
P37-USB2.0 Conn
P38-Docking Conn.
P39-PWR_OK / RTC
P40-DC INTERFACE
P41-Screws
P42-PWR-DCIN / Precharge
P43-PWR-Charger
P44-PWR-Battery Select
P45-PWR-3V/5V/12V
P46-PWR-GMCH_CORE/1.8V/0.9V
P47-PWR-1.5V/2.5V
P48-PWR-CPU_CORE
P49-PWR-OTP
P50-PWR-PIR

Title

Cover Sheet

Size Document Number Rev

EFL50 LA-2761

Date: Sheet

151Wednesday, April 20, 2005

E

of

0.2

A

Compal confidential

B

C

D

E

Project Code: EFL50/ EFT51

Intel Dothan/ Celeron M CPU

File Name : LA-2761

CRT & TV-OUT

1 1

page 15

H_A#(3..31)

FSB

400 / 533 Mhz

page 4,5

H_D#(0..63)

Thermal Se nsor
ADM1032ARM

page 4

Clock Generator
ICS954226AGT

page 14

Daughter Card Slot
PCI-Express x16

page 15

PCI-E BUS

Intel Alviso GM(PM)

DDR-2

DDRII-SO-DIMM X2

BANK 0, 1, 2, 3

page 11,12,13

PCBGA 1257

ATi M24P/ M26P

VGA Board

page 16

page 6,7,8,9,10

Two Channel DDR-2

DMI

LCD CONN

page 16

2 2

Intel ICH6-M

PCI BUS

Mini PCI
Socket

page 28

3 3

BroadCOM
BCM4401KFB
BCM57 88M

page 26

RJ45 CONN

page 27

ENE Controller

CB712

Slot 0

page 24

3in1 CardReader
Slot

page 23,24

page 24

1394 Controller
TSB43AB21

page 25

1394
Conn.

page 25

LPC BUS

Power On/Off CKT.

page 39

SMsC LPC47N217

DC/DC Interface CKT.

page 40

RTC CKT.

page 39

page 32

mBGA-609

page 17,18,19,20

ENE KB910Q

USB 2.0

USB 2.0

AC-LINK

SATA

PATA

page 33

USB conn x 3

BT Conn

page 37

page 34

Audio CKT
ALC250-D

MDC Conn.

page 29

page 36

SATA HDD Conn.

page 21

HDD Conn.
CDROM Conn.

page 21

AMP & Audio Jack

RJ11 CONN

page 31

page 36

Docking Conn.
PCI-E Bridge

RJ45
VGA
DVI
TV-Out
HP-Out/ Line-Out
Mic-in/ Line-in
SPDIF
Parallel Port

Jack x2

page 36

Serial Port

Int. KBD

Power Circuit DC/DC

4 4

page 42~49

Power OK CKT.

page 39

Parellel Port

page 38

Serial Port

DOCKING CONNDOCKING CONN

page 38

Touch Pad
CONN.

page 34

Button

LED

page 38

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2005/03/08 2006/03/08

C

Compal Secret Data

Deciphered Date

page 34

BIOS

page 35

Title

Size Document Number Rev

Custom

D

Date: Sheet

KB/ Mouse (PS/2)

Block Diagrams

EFL50 LA-2761

page 39

0.2

251Wednesday, April 20, 2005

E

of

A

Voltage Rails

Power Plane Description

1 1

2 2

VIN
B+
+CPU_CORE
+1.05VS
+DDRVTT 0.9V switched power rail for DDR terminator
+1.5VALW 1.5V always on power rail
+1.5VS
+1.8VS 1.8V switched power rail
+DDRVCC
+2.5VS
+3VALW
+3V
+3VS
+5VALW
+5VS
+5VMO D 5 V sw i tc he d po we r rail for Module Bay
+12VALW 12V always on power rail
+RTC V C C RTC power

Adapter power supply (19V)
AC or batte ry power rail for power circuit.
Core voltage for CPU

1.05V switched power rail

1.5V switched power rail

1.8V power rail for DDR

2.5V switched power rail

3.3V always on power rail

3.3V power rail

3.3V switched power rail
5V always on power rail
5V switched power rail

B

S1 S3 S4/ S5

N/A N/A N/A

ON OFF
ON OFF
ON OFF OF F
ON
ON OFF OF F
ON OFF OF F
ON
ON
ON
ON
ON
ON

ON ONON

N/AN/AN/A
OFF
OFF

ON*ON

OFF

ON

OFF

OFF
ON ON*

OFF

ON
OFF

OFF

ON

ON*

OFF

OFFON
OFF OFFON
ONON ON*

C

STATE

Full ON

S1(Power On Suspend)

S3 (Suspend to RAM)

S4 (Suspend to Disk)

S5 (Soft OFF)

SIGNAL

SLP_S1# SLP_S3#

HIGH HIGH HIGH HIGH

LOW

LOW

LOW LOW LOW LOW

D

LOW

Board ID / SKU ID Table for AD channel

Vcc 3.3V +/- 5%

Board ID

0
1
2
3
4
5
6
7 NC

100K +/- 5%Ra / Rc

Rb / Rd V min

AD_BID

0

8.2K +/- 5%
18K +/- 5%
33K +/- 5%
56K +/- 5%
100K +/- 5%
200K +/- 5%

0.216 V 0.250 V 0.289 V

0.436 V

0.712 V

1.036 V

1.453 V 1.650 V 1.759 V

1.935 V

2.500 V

E

SLP_S4# SLP_S5# +VA LW +V +VS Clock

0 V

HIGH

LOWLOWLOW

ON

HIGHHIGHHIGH

HIGH

HIGH

Vtyp

ON

ON

ON

ON

AD_BID

0 V 0 V

0.503 V

0.819 V

ON

ON

ON

OFF

OFF

V

AD_BID

0.538 V

0.875 V

ON ON

ON

OFF

OFF

OFF

max

1.185 V 1.264 V

2.200 V

3.300 V

2.341 V

3.300 V

LOW

OFF

OFF

OFF

Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.

External PCI Devices

Device IDSEL # REQ # / GNT # Interrupts

CardBus

1394
SD

Mini-PCI

LAN

3 3

AD20
AD16 0
AD20
AD18
AD17 3

2

2
1

PIRQA/PIRQB
PIRQE
PIRQA/PIRQB
PIRQG/PIRQH
PIRQF

BOARD ID Table

Board ID

0
1
2
3
4
5
6
7

PCB Revision

0.1

0.2

BTO Item BOM Structure

UMA
Discrete
LAN 10/100
LAN GIGA
1 Spindle 1S@
2 Spindle 2S@
2 Spindle with SATA

1 Spindle with SATA

EC SM Bus1 address

Device

Smart Battery
EEPROM(24C16/02)

(24C04)

Address Address

1010 000X b
1011 000Xb

EC SM Bus2 address

Device

ADM1032

1001 110X b0001 011X b

SKU ID Table

SKU ID

0
1
2

SKU

1 Spindle with PATA
With Docking
Without Docking
With 1394
With 1394 4pin
With 1394 6pin

BTO Option Table

GM@
PM@
4401@
5788@

2SS@
2SP@2 Spindle with PATA
1SS@
1SP@
WD@
ND@
1394@
1394<4>@

1394<6>@

3
4
5

ICH6M SM Bus address

Device

4 4

Clock Generator
(ICS 954226AGT)

DDRII DIMM0
DDRII DIMM2

A

Address

1101 001Xb

1001 000Xb
1001 010Xb

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2005/03/08 2006/03/08

C

6
7

Compal Secret Data

Deciphered Date

Title

Notes

Size Document Number Rev

Custom

EFL50 LA-2761

D

Date: Sheet

351Wednesday, April 20, 2005

E

0.2

of

5

H_A#[3..31]6

H_REQ#[0..4]6

H_RS#[0..2]6
H_D#[0..63]6

D D

C C

B B

A A

H_A#[3..31]
H_REQ#[0..4]
H_RS#[0..2]
H_D#[0..63]

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

H_ADSTB#06
H_ADSTB#16

CLK_CPU_BCLK13

CLK_CPU_BCLK#13

H_ADS#6
H_BNR#6

H_BPRI#6

H_BR0#6

H_DEFER#6

H_DRDY#6

H_HIT#6
H_HITM#6

H_LOCK#6

H_CPURST#6

H_TRDY#6

H_DBSY#6
H_DPSLP#17
H_DPRSTP#17
H_DPWR#6

H_PWRGOOD17

H_CPUSLP#6,17

H_THERMTRIP#6,17

H_ADSTB#0
H_ADSTB#1

CLK_CPU_BCLK
CLK_CPU_BCLK#

H_ADS#
H_BNR#
H_BPRI#
H_BR0#
H_DEFER#
H_DRDY#
H_HIT#
H_HITM#
H_IERR#
H_LOCK#
H_CPURST#

H_RS#0
H_RS#1
H_RS#2
H_TRDY#

ITP_DBRRESET#
H_DBSY#
H_DPSLP#
H_DPRSTP#
H_DPWR#

PRO_CHOT#
H_PWRGOOD

H_CPUSLP#
ITP_TCK
ITP_TDI
ITP_TDO
TEST1
TEST2
ITP_TMS
ITP_TRST#

THERMDA
THERMDC
H_THERMTRIP#

4

JP20A

P4

A3#

U4

A4#

V3

A5#

R3

A6#

V2

A7#

W1

A8#

T4

A9#

W2

A10#

Y4

A11#

Y1

A12#

U1

A13#

AA3

A14#

Y3

A15#

AA2

A16#

AF4

A17#

AC4

A18#

AC7

A19#

AC3

A20#

AD3

A21#

AE4

A22#

AD2

A23#

AB4

A24#

AC6

ADDR GROUP

A25#

AD5

A26#

AE2

A27#

AD6

A28#

AF3

A29#

AE1

A30#

AF1

A31#

R2

REQ0#

P3

REQ1#

T2

REQ2#

P1

REQ3#

T1

REQ4#

U3

ADSTB0#

AE5

ADSTB1#

A16

ITP_CLK0

A15

ITP_CLK1

B15

BCLK0

B14

BCLK1

N2

ADS#

L1

BNR#

J3

BPRI#

N4

BR0#

L4

DEFER#

H2

DRDY#

K3

HIT#

K4

HITM#

A4

IERR#

J2

LOCK#

B11

RESET#

H1

RS0#

K1

RS1#

L2

RS2#

M3

TRDY#

C8

BPM0#

B8

BPM1#

A9

BPM2#

C9

BPM3#

A7

DBR#

M2

DBSY#

B7

DPSLP#

G1

DPRSTP#

C19

DPWR#

A10

PRDY#

B10

PREQ#

B17

PROCHOT#

E4

PWRGOOD

A6

SLP#

A13

TCK

C12

TDI

A12

TDO

C5

TEST1

F23

TEST2

C11

TMS

B13

TRST#

B18

THERMDA

A18

THERMDC

C17

THERMTRIP#

TYCO_1612365-1_Dothan

Dothan

DATA GROUP

HOST CLK

CONTROL GROUP

MISC

THERMAL
DIODE

LEGACY CPU

D0#
D1#
D2#
D3#
D4#
D5#
D6#
D7#
D8#

D9#
D10#
D11#
D12#
D13#
D14#
D15#
D16#
D17#
D18#
D19#
D20#
D21#
D22#
D23#
D24#
D25#
D26#
D27#
D28#
D29#
D30#
D31#
D32#
D33#
D34#
D35#
D36#
D37#
D38#
D39#
D40#
D41#
D42#
D43#
D44#
D45#
D46#
D47#
D48#
D49#
D50#
D51#
D52#
D53#
D54#
D55#
D56#
D57#
D58#
D59#
D60#
D61#
D62#
D63#

DINV0#
DINV1#
DINV2#
DINV3#

DSTBN0#
DSTBN1#
DSTBN2#
DSTBN3#
DSTBP0#
DSTBP1#
DSTBP2#
DSTBP3#

A20M#
FERR#

IGNNE#

INIT#

LINT0
LINT1

STPCLK#

SMI#

A19
A25
A22
B21
A24
B26
A21
B20
C20
B24
D24
E24
C26
B23
E23
C25
H23
G25
L23
M26
H24
F25
G24
J23
M23
J25
L26
N24
M25
H26
N25
K25
Y26
AA24
T25
U23
V23
R24
R26
R23
AA23
U26
V24
U25
V26
Y23
AA26
Y25
AB25
AC23
AB24
AC20
AC22
AC25
AD23
AE22
AF23
AD24
AF20
AE21
AD21
AF25
AF22
AF26

D25
J26
T24
AD20

C23
K24
W25
AE24
C22
L24
W24
AE25

C2
D3
A3
B5
D1
D4

C6
B4

H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63

H_DINV#0
H_DINV#1
H_DINV#2
H_DINV#3

H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3
H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3

H_A20M#
H_FERR#
H_IGNNE#
H_INIT#
H_INTR
H_NMI

H_STPCLK#
H_SMI#

3

C402

2200P_0402_50V7K

EC_SMB_CK233
EC_SMB_DA233

1

2

2

THERMDA

THERMDC
EC_SMB_CK2
EC_SMB_DA2

U29

2

D+

3

D-

8

SCLK

7

SDATA

ADM1032ARM_RM8

+3VS

1

C401

0.1U_0402_16V4Z

2

VDD1

ALERT#

THERM#

GND

1

12

R379

10K_0402_5%@

1
6
4
5

SMBus Address: 1001110X (b)

+1.05VS

H_DINV#0 6
H_DINV#1 6
H_DINV#2 6
H_DINV#3 6

H_DSTBN#0 6
H_DSTBN#1 6
H_DSTBN#2 6
H_DSTBN#3 6
H_DSTBP#0 6
H_DSTBP#1 6
H_DSTBP#2 6
H_DSTBP#3 6

H_A20M# 17
H_FERR# 17
H_IGNNE# 17
H_INIT# 17
H_INTR 17
H_NMI 17

H_STPCLK# 17
H_SMI# 17

ITP_TDI
ITP_TDO
H_CPURST#
ITP_TMS
PRO_CHOT#
H_PWRGOOD
H_IERR#

ITP_DBRRESET#

ITP_TRST#

ITP_TCK
TEST1
TEST2

0415

H_INIT#

H_NMI

H_SMI#

H_CPURST#

R53 150_0402_5%
R383 54.9_0402_1%@
R382 54.9_0402_1%@
R54 40.2_0402_1%
R386 56_0402_5%
R56 200_0402_5%
R380 56_0402_5%

R381 150_0402_5%

R384 680_0402_5%
R385 27.4_0402_1%
R55 1K_0402_5%@
R401 1K_0402_5%@

C685 47P_0402_50V8J

1 2

C686 47P_0402_50V8J

1 2

C687 47P_0402_50V8J

1 2

C688 47P_0402_50V8J

1 2

12
12
12
12
12
12
12

12

12
12
12
12

+3VS

THERMDA & THERMDC Trace / Space = 10 / 10 mil

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2005/03/08 2006/03/08

3

Compal Secret Data

Deciphered Date

Title

Dothon Processor in mFCPGA479

Size Document Number Rev

Custom

EFL50 LA-2761

2

Date: Sheet

451Wednesday, April 20, 2005

1

0.2

of

5

JP20B

+1.05VS

VCCSENSE
VSSSENSE

VCCA0
VCCA1
VCCA2
VCCA3

PSI#
CPU_VID0

CPU_VID1
CPU_VID2
CPU_VID3
CPU_VID4
CPU_VID5

GTL_REF0

CPU_BSEL0
CPU_BSEL1

COMP0
COMP1
COMP2
COMP3

AE7

VCCSENSE

AF6

VSSSENSE

F26

VCCA0

B1

VCCA1

N1

VCCA2

AC26

VCCA3

P23

VCCQ0

W4

VCCQ1

D10

VCCP

D12

VCCP

D14

VCCP

D16

VCCP

E11

VCCP

E13

VCCP

E15

VCCP

F10

VCCP

F12

VCCP

F14

VCCP

F16

VCCP

K6

VCCP

L5

VCCP

L21

VCCP

M6

VCCP

M22

VCCP

N5

VCCP

N21

VCCP

P6

VCCP

P22

VCCP

R5

VCCP

R21

VCCP

T6

VCCP

T22

VCCP

U21

VCCP

D6

VCC

D8

VCC

D18

VCC

D20

VCC

D22

VCC

E5

VCC

E7

VCC

E9

VCC

E17

VCC

E19

VCC

E21

VCC

F6

VCC

F8

VCC

F18

VCC

E1

PSI#

E2

VID0

F2

VID1

F3

VID2

G3

VID3

G4

VID4

H4

VID5

AD26

GTLREF

C16

BSEL0

C14

BSEL1

P25

COMP0

P26

COMP1

AB2

COMP2

AB1

COMP3

B2

RSVD

C3

RSVD

E26

RSVD

AF7

RSVD

AC1

RSVD

TYCO_1612365-1_Dothan

R144 54.9_0402_1%@

1 2

R141 54.9_0402_1%@

1 2

30 mils

R393 0_0603_5%

1 2

R388 0_0603_5%@

+VCCA

D D

1.8V FOR DOTHAN-A

1 2

+1.8VS

R419 0_1206_5%@

1 2

R387 0_0603_5%@

1 2

R417 0_0603_5%@

1 2

1.5V FOR DOTHAN-B

1 2

+1.5VS

R399 0_1206_5%

Trace Width>= 40 mils

C C

B B

+VCCA

0.01U_0402_16V7K

C405

R422
1K_0402_1%

1 2

R420 2K_0402_1%

1

2

+1.05VS

12

CPU_BSEL013
CPU_BSEL113

1

C463

2

10U_0805_10V4Z

+CPU_CORE

PSI#46
CPU_VID046

CPU_VID146
CPU_VID246
CPU_VID346
CPU_VID446
CPU_VID546

500 mils

R408 27.4_0402_1%

A A

50 mils

1 2

R407 54.9_0402_1%

1 2

R424 27.4_0402_1%

1 2

R425 54.9_0402_1%

1 2

COMP0
COMP1
COMP2
COMP3

TRACE CLOSELY CPU > 50 mils

COMP0, COMP2 layout : Width 18mils and Space 25mils
COMP1, COMP3 layout : Space 25mils

5

4

A2

VSS

A5

VSS

A8

VSS

A11

VSS

A14

VSS

A17

VSS

A20

VSS

A23

VSS

A26

VSS

B3

VSS

B6

VSS

B9

VSS

B12

Dothan

VSS

B16

VSS

B19

VSS

B22

VSS

B25

VSS

C1

VSS

C4

VSS

C7

VSS

C10

VSS

C13

VSS

C15

VSS

C18

VSS

C21

VSS

C24

VSS

D2

VSS

D5

VSS

D7

VSS

D9

VSS

D11

VSS

D13

VSS

D15

VSS

D17

VSS

D19

VSS

D21

VSS

D23

VSS

D26

VSS

E3

VSS

E6

VSS

E8

VSS

E10

VSS

E12

VSS

E14

VSS

E16

VSS

E18

VSS

E20

VSS

E22

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

E25
F1
F4
F5
F7
F9
F11
F13
F15
F17
F19
F21
F24
G2
G6
G22
G23
G26
H3
H5
H21
H25
J1
J4
J6
J22
J24
K2
K5
K21
K23
K26
L3
L6
L22
L25
M1

POWER, GROUNG, RESERVED SIGNALS AND NC

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

+1.05VS

1

+

2

150U_D2_6.3VM

Issued Date

+CPU_CORE

220U_D2_4VM_R12

1

+

C49

2

220U_D2_4VM_R12

+CPU_CORE

10U_0805_10V4Z

1

C455

2

10U_0805_10V4Z

+CPU_CORE

10U_0805_10V4Z

1

C423

2

10U_0805_10V4Z

+CPU_CORE

10U_0805_10V4Z

1

C60

2

10U_0805_10V4Z

+CPU_CORE

10U_0805_10V4Z

1

C71

2

10U_0805_10V4Z

+CPU_CORE

10U_0805_10V4Z

1

C667

2

10U_0805_10V4Z

Vcc-core
Decoupling

SPCAP,Polymer
MLCC 0805 X5R

0.1U_0402_16V4Z

1

C404

C63

2

3

220U_D2_4VM_R12

1

+

C50

2

220U_D2_4VM_R12

1

C456

2

10U_0805_10V4Z

1

C112

2

10U_0805_10V4Z

1

C57

2

10U_0805_10V4Z

1

C81

2

10U_0805_10V4Z

1

C668

2

10U_0805_10V4Z

1

C150

2

10U_0805_10V4Z

1

C424

2

10U_0805_10V4Z

1

C421

2

10U_0805_10V4Z

1

C61

2

10U_0805_10V4Z

1

C452

2

10U_0805_10V4Z

1

C669

2

+

1

C435

2

1

C420

2

1

C72

2

1

C113

2

1

C670

2

1

+

C151

2

10U_0805_10V4Z

1

C443

2

10U_0805_10V4Z

10U_0805_10V4Z

1

C434

2

10U_0805_10V4Z

10U_0805_10V4Z

1

C82

2

10U_0805_10V4Z

10U_0805_10V4Z

1

C96

2

10U_0805_10V4Z

10U_0805_10V4Z

1

C671

2

10U_0805_10V4Z

1

C448

2

1

C442

2

1

C97

2

1

C108

2

1

C672

2

1

C453

2

10U_0805_10V4Z

1

C447

2

10U_0805_10V4Z

1

C109

2

10U_0805_10V4Z

1

C58

2

10U_0805_10V4Z

1

C673

2

10U_0805_10V4Z

0331

C,uF ESR, mohm ESL,nH

3X330uF 9m ohm/3 3.5nH/4
35X10uF 5m ohm/35 0.6nH/35

1

C75

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

C43

C85

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

C68

2

2

0.1U_0402_16V4Z

2005/03/08 2006/03/08

3

0.1U_0402_16V4Z

1

C78

C90

2

0.1U_0402_16V4Z

Compal Secret Data

1

2

Deciphered Date

2

0.1U_0402_16V4Z

1

C42

2

2

1

C41

2

1

+CPU_CORE

1

C98

2

0.1U_0402_16V4Z

Custom

JP20C

F20

VCC

F22

VCC

G5

VCC

G21

VCC

H6

VCC

H22

VCC

J5

VCC

J21

VCC

K22

VCC

U5

VCC

V6

VCC

V22

VCC

W5

VCC

W21

VCC

Y6

VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC

POWER, GROUND

VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

Dothan

Y22
AA5
AA7

AA9
AA11
AA13
AA15
AA17
AA19
AA21

AB6

AB8
AB10
AB12
AB14
AB16
AB18
AB20
AB22

AC9
AC11
AC13
AC15
AC17
AC19

AD8
AD10
AD12
AD14
AD16
AD18

AE9
AE11
AE13
AE15
AE17
AE19

AF8

AF10
AF12
AF14
AF16
AF18

M4

M5
M21
M24

N3

N6
N22
N23
N26

P2

P5
P21
P24

R1

R4

R6
R22
R25

T3

T5

T21
T23

TYCO_1612365-1_Dothan

Title

Dothan Processor in mFCPGA479

Size Document Number Rev

EFL50 LA-2761

Date: Sheet

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

1

T26
U2
U6
U22
U24
V1
V4
V5
V21
V25
W3
W6
W22
W23
W26
Y2
Y5
Y21
Y24
AA1
AA4
AA6
AA8
AA10
AA12
AA14
AA16
AA18
AA20
AA22
AA25
AB3
AB5
AB7
AB9
AB11
AB13
AB15
AB17
AB19
AB21
AB23
AB26
AC2
AC5
AC8
AC10
AC12
AC14
AC16
AC18
AC21
AC24
AD1
AD4
AD7
AD9
AD11
AD13
AD15
AD17
AD19
AD22
AD25
AE3
AE6
AE8
AE10
AE12
AE14
AE16
AE18
AE20
AE23
AE26
AF2
AF5
AF9
AF11
AF13
AF15
AF17
AF19
AF21
AF24

551Wednesday, April 20, 2005

0.2

of

5

H_RS#[0..2]

H_A#[3..31]4
H_REQ#[0..4]4

D D

C C

CLK_MCH_BCLK#13
CLK_MCH_BCLK13

B B

H_A#[3..31]

H_ADSTB#04
H_ADSTB#14

H_DSTBN#04
H_DSTBN#14
H_DSTBN#24
H_DSTBN#34
H_DSTBP#04
H_DSTBP#14
H_DSTBP#24
H_DSTBP#34
H_DINV#04
H_DINV#14
H_DINV#24
H_DINV#34

H_CPURST#4

H_ADS#4
H_TRDY#4

H_DPWR#4

H_DRDY#4
H_DEFER#4

H_HITM#4
H_HIT#4
H_LOCK#4
H_BR0#4
H_BNR#4
H_BPRI#4
H_DBSY#4

CLK_MCH_BCLK#
CLK_MCH_BCLK

H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3
H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3
H_DINV#0
H_DINV#1
H_DINV#2
H_DINV#3

H_CPURST#
H_ADS#

H_TRDY#
H_DPWR#
H_DRDY#
H_DEFER#

H_HITM#
H_HIT#
H_LOCK#
H_BR0#
H_BNR#
H_BPRI#
H_DBSY#

Un-pop for Dothan-A

H_CPUSLP#4,17

A A

(5mil:15mil) (12mil:10mil)

H_VREF H_XSWING

1

C138

0.1U_0402_16V4Z

2

H_CPUSLP# CPU_SLP#

+1.05VS

12

R405
100_0603_1%

12

R406
200_0603_1%

5

H_RS#[0..2] 4

U31A

H_A#3

G9

HA3#

A10

B10
E10
G10

E11
G11

G13
C10
C11
D11
C12
B13
A12

G12
E12
C13
B11
D13
A13

A11

E13
AB1

AB2

H10

C9

E9
B7

F9

D8

D9

F10

F12

F13

A7

D7

B8

C7

A8
B9

G4

K1

R3

V3

G5

K2
R2
W4
H8

K3

T7
U5

F8

B5
G6

F7

E6

F6
D6
D4

B3

E7

A5
D5
C6
G8

A4
C5

B4

Alviso

HA4#
HA5#
HA6#
HA7#
HA8#
HA9#
HA10#
HA11#
HA12#
HA13#
HA14#
HA15#
HA16#
HA17#
HA18#
HA19#
HA20#
HA21#
HA22#
HA23#
HA24#
HA25#
HA26#
HA27#
HA28#
HA29#
HA30#
HA31#

HPCREQ#
HREQ#0
HREQ#1
HREQ#2
HREQ#3
HREQ#4
HADSTB#0
HADSTB#1

HCLKN
HCLKP

HDSTBN#0
HDSTBN#1
HDSTBN#2
HDSTBN#3
HDSTBP#0
HDSTBP#1
HDSTBP#2
HDSTBP#3
HDINV#0
HDINV#1
HDINV#2
HDINV#3

HCPURST#
HADS#

HTRDY#
HDPWR#
HDRDY#
HDEFER#
HEDRDY#
HHITM#
HHIT#
HLOCK#
HBREQ0#
HBNR#
HBPRI#
HDBSY#
HCPUSLP#
HRS0#
HRS1#
HRS2#

1

C459

0.1U_0402_16V4Z

2

H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3

H_REQ#4
H_ADSTB#0
H_ADSTB#1

CPU_SLP#
H_RS#0
H_RS#1
H_RS#2

R130 0_0402_5%

1 2

HD0#
HD1#
HD2#
HD3#
HD4#
HD5#
HD6#
HD7#
HD8#

HD9#
HD10#
HD11#
HD12#
HD13#
HD14#
HD15#
HD16#
HD17#
HD18#
HD19#
HD20#
HD21#
HD22#
HD23#
HD24#
HD25#
HD26#
HD27#
HD28#
HD29#
HD30#
HD31#
HD32#
HD33#

HOST

HD34#
HD35#
HD36#
HD37#
HD38#
HD39#
HD40#
HD41#
HD42#
HD43#
HD44#
HD45#
HD46#
HD47#
HD48#
HD49#
HD50#
HD51#
HD52#
HD53#
HD54#
HD55#
HD56#
HD57#
HD58#
HD59#
HD60#
HD61#
HD62#
HD63#

HVREF
HXRCOMP
HXSCOMP
HYRCOMP
HYSCOMP

HXSWING
HYSWING

ALVISO_BGA1257

+1.05VS

12

R409
221_0603_1%

12

R411
100_0603_1%

E4
E1
F4
H7
E2
F1
E3
D3
K7
F2
J7
J8
H6
F3
K8
H5
H1
H2
K5
K6
J4
G3
H3
J1
L5
K4
J5
P7
L7
J3
P5
L3
U7
V6
R6
R5
P3
T8
R7
R8
U8
R4
T4
T5
R1
T3
V8
U6
W6
U3
V5
W8
W7
U2
U1
Y5
Y2
V4
Y7
W1
W3
Y3
Y6
W2

J11
C1
C2
T1
L1
D1
P1

4

H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63

H_VREF
H_XRCOMP
H_XSCOMP
H_YRCOMP
H_YSCOMP
H_XSWING
H_YSWING

H_D#[0..63]H_REQ#[0..4]

+1.8V

R120 24.9_0402_1%
R111 54.9_0402_1%
R151 24.9_0402_1%
R145 54.9_0402_1%

1 2
1 2

12
12

H_D#[0..63] 4

R162 40.2_0402_1%

1 2

R163 40.2_0402_1%

1 2

R165 80.6_0402_1%

1 2

R166 80.6_0402_1%

1 2

+1.05VS

3

DMI_ITX_MRX_N018
DMI_ITX_MRX_N118
DMI_ITX_MRX_N218
DMI_ITX_MRX_N318

DMI_ITX_MRX_P018
DMI_ITX_MRX_P118
DMI_ITX_MRX_P218
DMI_ITX_MRX_P318

DMI_MTX_IRX_N018
DMI_MTX_IRX_N118
DMI_MTX_IRX_N218
DMI_MTX_IRX_N318

DMI_MTX_IRX_P018
DMI_MTX_IRX_P118
DMI_MTX_IRX_P218
DMI_MTX_IRX_P318

M_CLK_DDR011
M_CLK_DDR111

M_CLK_DDR312
M_CLK_DDR412

M_CLK_DDR#011
M_CLK_DDR#111

M_CLK_DDR#312
M_CLK_DDR#412

DDR_CKE0_DIMMA11
DDR_CKE1_DIMMA11
DDR_CKE2_DIMMB12
DDR_CKE3_DIMMB12

DDR_CS0_DIMMA#11
DDR_CS1_DIMMA#11
DDR_CS2_DIMMB#12
DDR_CS3_DIMMB#12

10mils

10mils

(10mil:20mil)

H_XRCOMP & H_YRCOMP Trace / Space = 10 / 20 mil

+1.05VS

12

R421
221_0603_1%

4

H_YSWING

1

C149

0.1U_0402_16V4Z

2

(12mil:10mil)

12

R423
100_0603_1%

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

U31B

DMI_ITX_MRX_N0
DMI_ITX_MRX_N1
DMI_ITX_MRX_N2
DMI_ITX_MRX_N3

DMI_ITX_MRX_P0
DMI_ITX_MRX_P1
DMI_ITX_MRX_P2
DMI_ITX_MRX_P3

DMI_MTX_IRX_N0
DMI_MTX_IRX_N1
DMI_MTX_IRX_N2
DMI_MTX_IRX_N3

DMI_MTX_IRX_P0
DMI_MTX_IRX_P1
DMI_MTX_IRX_P2
DMI_MTX_IRX_P3

M_CLK_DDR0
M_CLK_DDR1

M_CLK_DDR3
M_CLK_DDR4

M_CLK_DDR#0
M_CLK_DDR#1

M_CLK_DDR#3
M_CLK_DDR#4

DDR_CKE0_DIMMA
DDR_CKE1_DIMMA
DDR_CKE2_DIMMB
DDR_CKE3_DIMMB

DDR_CS0_DIMMA#
DDR_CS1_DIMMA#
DDR_CS2_DIMMB#
DDR_CS3_DIMMB#

M_OCDCOMP0
M_OCDCOMP1

M_ODT011
M_ODT111
M_ODT212
M_ODT312

M_RCOMPN
M_RCOMPP
SMVREF

M_XSLEW
M_YSLEW

10mils

R164

1K_0402_1%

R158

1K_0402_1%

2005/03/08 2006/03/08

AA31

DMIRXN0

AB35

DMIRXN1

AC31

DMIRXN2

AD35

DMIRXN3

Y31

DMIRXP0

AA35

DMIRXP1

AB31

DMIRXP2

AC35

DMIRXP3

AA33

DMITXN0

AB37

DMITXN1

AC33

DMITXN2

AD37

DMITXN3

Y33

DMITXP0

AA37

DMITXP1

AB33

DMITXP2

AC37

DMITXP3

AM33

SM_CK0

AL1

SM_CK1

AE11

SM_CK2

AJ34

SM_CK3

AF6

SM_CK4

AC10

SM_CK5

AN33

SM_CK0#

AK1

SM_CK1#

AE10

SM_CK2#

AJ33

SM_CK3#

AF5

SM_CK4#

AD10

SM_CK5#

AP21

SM_CKE0

AM21

SM_CKE1

AH21

SM_CKE2

AK21

SM_CKE3

AN16

SM_CS0#

AM14

SM_CS1#

AH15

SM_CS2#

AG16

SM_CS3#

AF22

SM_OCDCOMP0

AF16

AP14

AL15
AM11
AN10

AK10
AK11

AF37

AD1
AE27
AE28

AF9

AF10

12

0.1U_0402_16V4Z

12

C185

SM_OCDCOMP1
SM_ODT0
SM_ODT1
SM_ODT2
SM_ODT3

SMRCOMPN
SMRCOMPP
SMVREF0
SMVREF1
SMXSLEWIN
SMXSLEWOUT
SMYSLEWIN
SMYSLEWOUT

ALVISO_BGA1257

1

2

M_ODT0
M_ODT1
M_ODT2
M_ODT3

+1.8V

Compal Secret Data

Deciphered Date

CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8

CFG9
CFG10
CFG11
CFG12

DMIDDR MUXING

1

2

CFG13
CFG14
CFG15
CFG16
CFG17
CFG18
CFG19
CFG20

RSVD21
RSVD22

CFG/RSVD

RSVD23
RSVD24
RSVD25
RSVD26
RSVD27

BM_BUSY#

EXT_TS0#
EXT_TS1#

THRMTRIP#

PWROK

RSTIN#

PM

DREF_CLKN

DREF_CLKP

DREF_SSCLKP

CLK

DREF_SSCLKN

NC

SMVREF

C179

0.1U_0402_16V4Z

2

NC1
NC2
NC3
NC4
NC5
NC6
NC7
NC8

NC9
NC10
NC11

CLK_DREF_SSC
CLK_DREF_SSC#

CFG0

G16

MCH_CLKSEL1

H13

MCH_CLKSEL0

G14
F16
F15

CFG5

G15

CFG6

E16

CFG7

D17
J16

CFG9

D15
E15
D14

CFG12

E14

CFG13

H12
C14
H15

CFG16 CFG6

J15
H14

CFG18

G22

CFG19

G23
D23
G25
G24
J17
A31
A30
D26
D25

PM_BMBUSY#

J23

EXT_TS#0

J21

EXT_TS#1

H22

H_THERMTRIP#

F5

VGATE

AD30

PLT_RST#

AE29

CLK_DREF_96M#

A24

CLK_DREF_96M

A23

CLK_DREF_SSC

D37

CLK_DREF_SSC#

C37

AP37
AN37
AP36
AP2
AP1
AN1
B1
A2
B37
A36
A37

CFG[2:0]
CFG5
CFG6
CFG7

CFG9

CFG[13:12]

CFG16
(FSB Dynamic
ODT)

CFG18
(VCC Select)

CFG19
(VTT Select)

Title

Size Document Number Rev

Custom

Date: Sheet

R114 0_0402_5%PM@

1 2

R122 0_0402_5%PM@

1 2

MCH_CLKSEL1 13
MCH_CLKSEL0 13

CFG0

R131 10K_0402_5%

1 2

CFG0

R132 1K_0402_5%@

CFG5

CFG7
CFG9
CFG12
CFG13
CFG16

1 2

R127 1K_0402_5%@

1 2

R124 1K_0402_5%

1 2

R117 1K_0402_5%@

1 2

R119 1K_0402_5%@

1 2

R125 1K_0402_5%@

1 2

R137 1K_0402_5%@

1 2

R140 1K_0402_5%@

1 2

CFG[17:3]: internal pull-up

CFG18

R128 1K_0402_5%@

CFG19

1 2

R135 1K_0402_5%@

1 2

CFG[19:18]: internal pull-down

PM_BMBUSY# 18

H_THERMTRIP# 4,17

VGATE 13,18,46
PLT_RST# 16,18,20,32,33,41

CLK_DREF_96M# 13
CLK_DREF_96M 13
CLK_DREF_SSC 13
CLK_DREF_SSC# 13

EXT_TS#0

R139 10K_0402_5%

EXT_TS#1

1 2

R136 10K_0402_5%

1 2

Refer to sheet 6 for FSB
frequency select
Low = DMI x 2

High = DMI x 4
Low = DDR-II

High = DDR-I
Low = DT/Transportable CPU

High = Mobile CPU
Low = Reverse Lane

High = Normal Operation
00 = Reserved

01 = XOR Mode Enabled
10 = All Z Mode Enabled
11 = Normal Operation (Default)

Low = Disabled
High = Enabled

Low = 1.05V (Default)
High = 1.5V

Low = 1.05V (Default)
High = 1.2V

Alviso HOST (1/5)

EFL50 LA-2761

1

+1.5VS

+1.05VS

+2.5VS

+2.5VS

*
*

*

*

*

*

*

*

0.2

651Wednesday, April 20, 2005

1

of

5

D D

4

3

2

1

DDR_A_BS#011
DDR_A_BS#111
DDR_A_BS#211

DDR_A_DM[0..7]11

DDR_A_DQS[0..7]11

C C

B B

DDR_A_DQS#[0..7]11

DDR_A_MA[0..13]11

DDR_A_CAS#11
DDR_A_RAS#11

DDR_A_WE#11 DDR_B_WE#12

DDR_A_BS#0
DDR_A_BS#1
DDR_A_BS#2

DDR_A_DM0
DDR_A_DM1
DDR_A_DM2
DDR_A_DM3
DDR_A_DM4
DDR_A_DM5
DDR_A_DM6
DDR_A_DM7

DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7

DDR_A_DQS#0
DDR_A_DQS#1
DDR_A_DQS#2
DDR_A_DQS#3
DDR_A_DQS#4
DDR_A_DQS#5
DDR_A_DQS#6
DDR_A_DQS#7

DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13

DDR_A_CAS#
DDR_A_RAS#

DDR_A_WE# DDR_B_WE#

AK15
AK16

AL21
AJ37

AP35

AL29

AP24

AP9
AP4

AJ2

AD3

AK36
AP33
AN29
AP23

AM8
AM4

AJ1

AE5

AK35
AP34
AN30
AN23

AN8
AM5
AH1

AE4

AL17
AP17
AP18
AM17
AN18
AM18

AL19
AP20
AM19

AL20
AM16
AN20
AM20
AM15

AN15
AP16

AF29

AF28
AP15

SA_BS0#
SA_BS1#
SA_BS2#

SA_DM0
SA_DM1
SA_DM2
SA_DM3
SA_DM4
SA_DM5
SA_DM6
SA_DM7

SA_DQS0
SA_DQS1
SA_DQS2
SA_DQS3
SA_DQS4
SA_DQS5
SA_DQS6
SA_DQS7

SA_DQS0#
SA_DQS1#
SA_DQS2#
SA_DQS3#
SA_DQS4#
SA_DQS5#
SA_DQS6#
SA_DQS7#

SA_MA0
SA_MA1
SA_MA2
SA_MA3
SA_MA4
SA_MA5
SA_MA6
SA_MA7
SA_MA8
SA_MA9
SA_MA10
SA_MA11
SA_MA12
SA_MA13

SA_CAS#
SA_RAS#
SA_RCVENIN#
SA_RCVENOUT#
SA_WE#

U31C

SADQ0
SADQ1
SADQ2
SADQ3
SADQ4
SADQ5
SADQ6
SADQ7
SADQ8

SADQ9
SADQ10
SADQ11
SADQ12
SADQ13
SADQ14
SADQ15
SADQ16
SADQ17
SADQ18
SADQ19
SADQ20
SADQ21
SADQ22
SADQ23
SADQ24
SADQ25
SADQ26
SADQ27
SADQ28
SADQ29
SADQ30
SADQ31
SADQ32
SADQ33
SADQ34
SADQ35
SADQ36
SADQ37
SADQ38
SADQ39
SADQ40
SADQ41
SADQ42
SADQ43

DDR MEMORY SYSTEM A

SADQ44
SADQ45
SADQ46
SADQ47
SADQ48
SADQ49
SADQ50
SADQ51
SADQ52
SADQ53
SADQ54
SADQ55
SADQ56
SADQ57
SADQ58
SADQ59
SADQ60
SADQ61
SADQ62
SADQ63

ALVISO_BGA1257

AG35
AH35
AL35
AL37
AH36
AJ35
AK37
AL34
AM36
AN35
AP32
AM31
AM34
AM35
AL32
AM32
AN31
AP31
AN28
AP28
AL30
AM30
AM28
AL28
AP27
AM27
AM23
AM22
AL23
AM24
AN22
AP22
AM9
AL9
AL6
AP7
AP11
AP10
AL7
AM7
AN5
AN6
AN3
AP3
AP6
AM6
AL4
AM3
AK2
AK3
AG2
AG1
AL3
AM2
AH3
AG3
AF3
AE3
AD6
AC4
AF2
AF1
AD4
AD5

DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63

DDR_B_BS#012
DDR_B_BS#112
DDR_B_BS#212

DDR_B_DM[0..7]12

DDR_B_DQS[0..7]12

DDR_B_DQS#[0..7]12

DDR_B_MA[0..13]12

DDR_B_CAS#12
DDR_B_RAS#12

DDR_B_BS#0
DDR_B_BS#1
DDR_B_BS#2

DDR_B_DM0
DDR_B_DM1
DDR_B_DM2
DDR_B_DM3
DDR_B_DM4
DDR_B_DM5
DDR_B_DM6
DDR_B_DM7

DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4
DDR_B_DQS5
DDR_B_DQS6
DDR_B_DQS7

DDR_B_DQS#0
DDR_B_DQS#1
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS#4
DDR_B_DQS#5
DDR_B_DQS#6
DDR_B_DQS#7

DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13

DDR_B_CAS#
DDR_B_RAS#

AJ15
AG17
AG21

AF32
AK34
AK27
AK24

AJ10

AK5
AE7
AB7

AF34
AK32

AJ28
AK23
AM10

AH6
AF8
AB4

AF35
AK33
AK28

AJ23

AL10

AH7
AF7
AB5

AH17
AK17
AH18

AJ18
AK18

AJ19
AK19
AH19

AJ20
AH20

AJ16
AG18
AG20
AG15

AH14
AK14

AF15

AF14
AH16

SB_BS0#
SB_BS1#
SB_BS2#

SB_DM0
SB_DM1
SB_DM2
SB_DM3
SB_DM4
SB_DM5
SB_DM6
SB_DM7

SB_DQS0
SB_DQS1
SB_DQS2
SB_DQS3
SB_DQS4
SB_DQS5
SB_DQS6
SB_DQS7

SB_DQS0#
SB_DQS1#
SB_DQS2#
SB_DQS3#
SB_DQS4#
SB_DQS5#
SB_DQS6#
SB_DQS7#

SB_MA0
SB_MA1
SB_MA2
SB_MA3
SB_MA4
SB_MA5
SB_MA6
SB_MA7
SB_MA8
SB_MA9
SB_MA10
SB_MA11
SB_MA12
SB_MA13

SB_CAS#
SB_RAS#
SB_RCVENIN#
SB_RCVENOUT#
SB_WE#

U31D

SBDQ0
SBDQ1
SBDQ2
SBDQ3
SBDQ4
SBDQ5
SBDQ6
SBDQ7
SBDQ8

SBDQ9
SBDQ10
SBDQ11
SBDQ12
SBDQ13
SBDQ14
SBDQ15
SBDQ16
SBDQ17
SBDQ18
SBDQ19
SBDQ20
SBDQ21
SBDQ22
SBDQ23
SBDQ24
SBDQ25
SBDQ26
SBDQ27
SBDQ28
SBDQ29
SBDQ30
SBDQ31
SBDQ32
SBDQ33
SBDQ34
SBDQ35
SBDQ36
SBDQ37
SBDQ38
SBDQ39
SBDQ40
SBDQ41
SBDQ42

DDR SYSTEM MEMORY B

SBDQ43
SBDQ44
SBDQ45
SBDQ46
SBDQ47
SBDQ48
SBDQ49
SBDQ50
SBDQ51
SBDQ52
SBDQ53
SBDQ54
SBDQ55
SBDQ56
SBDQ57
SBDQ58
SBDQ59
SBDQ60
SBDQ61
SBDQ62
SBDQ63

ALVISO_BGA1257

AE31
AE32
AG32
AG36
AE34
AE33
AF31
AF30
AH33
AH32
AK31
AG30
AG34
AG33
AH31
AJ31
AK30
AJ30
AH29
AH28
AK29
AH30
AH27
AG28
AF24
AG23
AJ22
AK22
AH24
AH23
AG22
AJ21
AG10
AG9
AG8
AH8
AH11
AH10
AJ9
AK9
AJ7
AK6
AJ4
AH5
AK8
AJ8
AJ5
AK4
AG5
AG4
AD8
AD9
AH4
AG6
AE8
AD7
AC5
AB8
AB6
AA8
AC8
AC7
AA4
AA5

DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63

DDR_B_D[0..63] 12DDR_A_D[0..63] 11

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2005/03/08 2006/03/08

3

Compal Secret Data

Deciphered Date

Title

Alviso DDR (2/5)

Size Document Number Rev

Custom

EFL50 LA-2761

2

Date: Sheet

751Wednesday, April 20, 2005

1

0.2

of

5

+3VS +2.5VS

12

R92

2.2K_0402_5%GM@

+2.5VS

S

GMCH_TV_COMPS21
GMCH_TV_LUMA21
GMCH_TV_CRMA21

G

2

GMCH_ENBKL

GMCH_LCD_CLK

13

D

Q9

2N7002_SOT23GM@

GMCH_CRT_CLK14
GMCH_CRT_DATA14
GMCH_CRT_B14

GMCH_CRT_G14
GMCH_CRT_R14

GMCH_CRT_VSYNC14
GMCH_CRT_HSYNC14

GMCH_ENBKL15,33

D D

C C

+2.5VS

R97 4.7K_0402_5%

1 2

R98 4.7K_0402_5%

1 2

R100 2.2K_0402_5%

1 2

R99 2.2K_0402_5%

1 2

R134 100K_0402_5%

1 2

R112 1.5K_0402_1%

B B

GM@

4.7K_0402_5%

LDDC_CLK

1 2

R109 150_0402_5%PM@

1 2

R118 150_0402_5%PM@

1 2

R101 150_0402_5%PM@

1 2

R104

1 2

2

G

1 3

D

S

Q10

R88 0_0402_5%@

GMCH_TV_COMPS
GMCH_TV_LUMA
GMCH_TV_CRMA

GMCH_CRT_CLK
GMCH_CRT_DATA
LCTLB_DATA
LCTLA_CLK

LBKLT_EN
LIBG
GMCH_TV_COMPS
GMCH_TV_LUMA
GMCH_TV_CRMA

+3VS

R87

4.7K_0402_5%GM@

1 2

BSS138_SOT23GM@

LBKLT_EN

12

R143 4.99K_0603_1%

GMCH_CRT_CLK
GMCH_CRT_DATA

R121 150_0402_5%PM@
R107 150_0402_5%PM@
R403 150_0402_5%PM@

GMCH_LCD_CLK 15

4

SDVO_SDAT15,41
SDVO_SCLK15,41
CLK_MCH_3GPLL#13
CLK_MCH_3GPLL13

12

12
12
12

GMCH_ENVDD15

GMCH_TXCLK-15
GMCH_TXCLK+15
GMCH_TZCLK-15
GMCH_TZCLK+15

GMCH_TXOUT0-15
GMCH_TXOUT1-15
GMCH_TXOUT2-15

GMCH_TXOUT0+15
GMCH_TXOUT1+15
GMCH_TXOUT2+15

GMCH_TZOUT0-15
GMCH_TZOUT1-15
GMCH_TZOUT2-15

GMCH_TZOUT0+15
GMCH_TZOUT1+15
GMCH_TZOUT2+15

SDVO_SDAT
SDVO_SCLK
CLK_MCH_3GPLL#
CLK_MCH_3GPLL

TV_REFSET

12

R108 0_0402_5%

GMCH_CRT_B
GMCH_CRT_G
GMCH_CRT_R
GMCH_CRT_VSYNC

GMCH_CRT_HSYNC

1 2

R142 255_0402_1%

REFSET

LBKLT_EN
LCTLA_CLK
LCTLB_DATA
LDDC_CLK
LDDC_DATA
GMCH_ENVDD
LIBG

GMCH_TXCLK­GMCH_TXCLK+
GMCH_TZCLK­GMCH_TZCLK+

GMCH_TXOUT0­GMCH_TXOUT1­GMCH_TXOUT2-

GMCH_TXOUT0+
GMCH_TXOUT1+
GMCH_TXOUT2+

GMCH_TZOUT0­GMCH_TZOUT1­GMCH_TZOUT2-

GMCH_TZOUT0+
GMCH_TZOUT1+
GMCH_TZOUT2+

U31G

H24

H25
AB29
AC29

A15

C16

A17

J18
B15
B16
B17

E24
E23
E21
D21
C20
B20
A19
B19
H21
G21

J20

E25

F25
C23
C22

F23

F22

F26
C33
C31

F28

F27
B30

B29
C25
C24

B34
B33
B32

A34
A33
B31

C29
D28
C27

C28
D27
C26

ALVISO_BGA1257

SDVOCTRL_DATA
SDVOCTRL_CLK
GCLKN
GCLKP

TVDAC_A
TVDAC_B
TVDAC_C
TV_REFSET
TV_IRTNA
TV_IRTNB
TV_IRTNC

DDCCLK
DDCDATA
BLUE
BLUE#
GREEN
GREEN#
RED
RED#
VSYNC
HSYNC
REFSET

LBKLT_CTL
LBKLT_EN
LCTLA_CLK
LCTLB_DATA
LDDC_CLK
LDDC_DATA
LVDD_EN
LIBG
LVBG
LVREFH
LVREFL

LACLKN
LACLKP
LBCLKN
LBCLKP

LADATAN0
LADATAN1
LADATAN2

LADATAP0
LADATAP1
LADATAP2

LBDATAN0
LBDATAN1
LBDATAN2

LBDATAP0
LBDATAP1
LBDATAP2

3

EXP_RXN0/SDVO_TVCLKIN#

MISCTVVGALVDS

EXP_RXN1/SDVO_INT#

EXP_RXN2/SDVO_FLDSTALL#

EXP_RXP0/SDVO_TVCLKIN

EXP_RXP1/SDVO_INT

EXP_RXP2/SDVO_FLDSTALL

EXP_TXN0/SDVOB_RED#

EXP_TXN1/SDVOB_GREEN#

EXP_TXN2/SDVOB_BLUE#

EXP_TXN3/SDVOB_CLKN
EXP_TXN4/SDVOC_RED#

EXP_TXN5/SDVOC_GREEN#

EXP_TXN6/SDVOC_BLUE#

EXP_TXN7/SDVOC_CLKN

PCI - EXPRESS GRAPHICS

EXP_TXP0/SDVOB_RED

EXP_TXP1/SDVOB_GREEN

EXP_TXP2/SDVOB_BLUE
EXP_TXP3/SDVOB_CLKP

EXP_TXP4/SDVOC_RED

EXP_TXP5/SDVOC_GREEN

EXP_TXP6/SDVOC_BLUE
EXP_TXP7/SDVOC_CLKP

EXP_COMPI

EXP_ICOMPO

EXP_RXN3
EXP_RXN4
EXP_RXN5
EXP_RXN6
EXP_RXN7
EXP_RXN8

EXP_RXN9
EXP_RXN10
EXP_RXN11
EXP_RXN12
EXP_RXN13
EXP_RXN14
EXP_RXN15

EXP_RXP3

EXP_RXP4

EXP_RXP5

EXP_RXP6

EXP_RXP7

EXP_RXP8

EXP_RXP9
EXP_RXP10
EXP_RXP11
EXP_RXP12
EXP_RXP13
EXP_RXP14
EXP_RXP15

EXP_TXN8

EXP_TXN9

EXP_TXN10
EXP_TXN11
EXP_TXN12
EXP_TXN13
EXP_TXN14
EXP_TXN15

EXP_TXP8

EXP_TXP9
EXP_TXP10
EXP_TXP11
EXP_TXP12
EXP_TXP13
EXP_TXP14
EXP_TXP15

2

PCIE_MTX_C_GRX_N[0..15]15,41

PCIE_MTX_C_GRX_P[0..15]15,41
PCEI_GTX_C_MRX_N[0..15]15,41
PCEI_GTX_C_MRX_P[0..15]15,41

PEG_COMP

D36
D34

PCEI_GTX_C_MRX_N0

E30

PCEI_GTX_C_MRX_N1

F34

PCEI_GTX_C_MRX_N2

G30

PCEI_GTX_C_MRX_N3

H34

PCEI_GTX_C_MRX_N4

J30

PCEI_GTX_C_MRX_N5

K34

PCEI_GTX_C_MRX_N6

L30

PCEI_GTX_C_MRX_N7

M34

PCEI_GTX_C_MRX_N8

N30

PCEI_GTX_C_MRX_N9

P34

PCEI_GTX_C_MRX_N10

R30

PCEI_GTX_C_MRX_N11

T34

PCEI_GTX_C_MRX_N12

U30

PCEI_GTX_C_MRX_N13

V34

PCEI_GTX_C_MRX_N14

W30

PCEI_GTX_C_MRX_N15

Y34

PCEI_GTX_C_MRX_P0

D30

PCEI_GTX_C_MRX_P1

E34

PCEI_GTX_C_MRX_P2

F30

PCEI_GTX_C_MRX_P3

G34

PCEI_GTX_C_MRX_P4

H30

PCEI_GTX_C_MRX_P5

J34

PCEI_GTX_C_MRX_P6

K30

PCEI_GTX_C_MRX_P7

L34

PCEI_GTX_C_MRX_P8

M30

PCEI_GTX_C_MRX_P9

N34

PCEI_GTX_C_MRX_P10

P30

PCEI_GTX_C_MRX_P11

R34

PCEI_GTX_C_MRX_P12

T30

PCEI_GTX_C_MRX_P13

U34

PCEI_GTX_C_MRX_P14

V30

PCEI_GTX_C_MRX_P15

W34

PCIE_MTX_GRX_N0

E32

PCIE_MTX_GRX_N1

F36

PCIE_MTX_GRX_N2

G32

PCIE_MTX_GRX_N3

H36

PCIE_MTX_GRX_N4 PCIE_MTX_C_GRX_N4

J32

PCIE_MTX_GRX_N5

K36

PCIE_MTX_GRX_N6

L32

PCIE_MTX_GRX_N7

M36

PCIE_MTX_GRX_N8

N32

PCIE_MTX_GRX_N9

P36

PCIE_MTX_GRX_N10

R32

PCIE_MTX_GRX_N11

T36

PCIE_MTX_GRX_N12

U32

PCIE_MTX_GRX_N13

V36

PCIE_MTX_GRX_N14

W32

PCIE_MTX_GRX_N15

Y36

PCIE_MTX_GRX_P0

D32

PCIE_MTX_GRX_P1

E36

PCIE_MTX_GRX_P2

F32

PCIE_MTX_GRX_P3

G36

PCIE_MTX_GRX_P4

H32

PCIE_MTX_GRX_P5

J36

PCIE_MTX_GRX_P6

K32

PCIE_MTX_GRX_P7

L36

PCIE_MTX_GRX_P8

M32

PCIE_MTX_GRX_P9

N36

PCIE_MTX_GRX_P10

P32

PCIE_MTX_GRX_P11

R36

PCIE_MTX_GRX_P12

T32

PCIE_MTX_GRX_P13

U36

PCIE_MTX_GRX_P14

V32

PCIE_MTX_GRX_P15

W36

1 2

R115 24.9_0402_1%

C422 0.1U_0402_16V4Z

1 2

C437 0.1U_0402_16V4Z

1 2

C445 0.1U_0402_16V4Z

1 2

C451 0.1U_0402_16V4Z

1 2

C460 0.1U_0402_16V4Z

1 2

C465 0.1U_0402_16V4Z

1 2

C469 0.1U_0402_16V4Z

1 2

C476 0.1U_0402_16V4Z

1 2

C418 0.1U_0402_16V4Z

1 2

C430 0.1U_0402_16V4Z

1 2

C444 0.1U_0402_16V4Z

1 2

C450 0.1U_0402_16V4Z

1 2

C458 0.1U_0402_16V4Z

1 2

C464 0.1U_0402_16V4Z

1 2

C468 0.1U_0402_16V4Z

1 2

C475 0.1U_0402_16V4Z

1 2

PCIE_MTX_C_GRX_N[0..15]

PCIE_MTX_C_GRX_P[0..15]
PCEI_GTX_C_MRX_N[0..15]
PCEI_GTX_C_MRX_P[0..15]

+1.5VS

C416 0.1U_0402_16V4Z

1 2

C428 0.1U_0402_16V4Z

1 2

C440 0.1U_0402_16V4Z

1 2

C449 0.1U_0402_16V4Z

1 2

C457 0.1U_0402_16V4Z

1 2

C462 0.1U_0402_16V4Z

1 2

C467 0.1U_0402_16V4Z

1 2

C474 0.1U_0402_16V4Z

1 2

C413 0.1U_0402_16V4Z

1 2

C425 0.1U_0402_16V4Z

1 2

C438 0.1U_0402_16V4Z

1 2

C446 0.1U_0402_16V4Z

1 2

C454 0.1U_0402_16V4Z

1 2

C461 0.1U_0402_16V4Z

1 2

C466 0.1U_0402_16V4Z

1 2

C470 0.1U_0402_16V4Z

1 2

1

PCIE_MTX_C_GRX_N0
PCIE_MTX_C_GRX_N1
PCIE_MTX_C_GRX_N2
PCIE_MTX_C_GRX_N3

PCIE_MTX_C_GRX_N5
PCIE_MTX_C_GRX_N6
PCIE_MTX_C_GRX_N7
PCIE_MTX_C_GRX_N8
PCIE_MTX_C_GRX_N9
PCIE_MTX_C_GRX_N10
PCIE_MTX_C_GRX_N11
PCIE_MTX_C_GRX_N12
PCIE_MTX_C_GRX_N13
PCIE_MTX_C_GRX_N14
PCIE_MTX_C_GRX_N15

PCIE_MTX_C_GRX_P0
PCIE_MTX_C_GRX_P1
PCIE_MTX_C_GRX_P2
PCIE_MTX_C_GRX_P3
PCIE_MTX_C_GRX_P4
PCIE_MTX_C_GRX_P5
PCIE_MTX_C_GRX_P6
PCIE_MTX_C_GRX_P7
PCIE_MTX_C_GRX_P8
PCIE_MTX_C_GRX_P9
PCIE_MTX_C_GRX_P10
PCIE_MTX_C_GRX_P11
PCIE_MTX_C_GRX_P12
PCIE_MTX_C_GRX_P13
PCIE_MTX_C_GRX_P14
PCIE_MTX_C_GRX_P15

A A

GM@

4.7K_0402_5%

LDDC_DATA

R105

+2.5VS

G

2

1 2

S

GMCH_LCD_DATA

13

D

Q32

5

2N7002_SOT23GM@

+3VS

R404

4.7K_0402_5%GM@

1 2

GMCH_LCD_DATA 15

4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2005/03/08 2006/03/08

3

Compal Secret Data

Deciphered Date

2

Title

Alviso PCI-E (3/5)

Size Document Number Rev

B

EFL50 LA-2761

Date: Sheet

851Wednesday, April 20, 2005

1

of

0.2

5

4

3

2

1

10U_1206_16V4Z

0.1U_0402_16V4Z

1

C188

2

+1.5VS

1

C93

2

+1.05VS

1

C165

2

2.2U_0603_6.3V6K

+3VS_TVDAC

+1.05VS

1

2

VCCHV(Ball A21,B21,B22)

C104

0.1U_0402_16V4Z

1000P_0402_50V7K@

U31E

+1.05VS

D D

C C

+1.5VS

+1.5VS_DPLLA
+1.5VS_DPLLB
+1.5VS_HPLL
+1.5VS_MPLL

B B

+1.5VS_DPLLA

1

2

+1.5VS_HPLL

A A

1

2

+1.5VS_DPLLA
+1.5VS_DPLLB
+1.5VS_HPLL
+1.5VS_MPLL

150U_D2_6.3VM TV@

60mA

+1.5VS_DPLLA

1

C59

C70

2

10U_1206_16V4Z
1000P_0402_50V7K@

60mA

+1.5VS_HPLL

1

C481

C478

2

10U_1206_16V4Z
1000P_0402_50V7K@

T29

VCC0

R29

VCC1

N29

VCC2

M29

VCC3

K29

VCC4

J29

VCC5

V28

VCC6

U28

VCC7

T28

R28

P28
N28
M28

L28

K28

J28
H28
G28

V27
U27

T27
R27

P27
N27
M27

L27

K27

J27
H27

K26
H26

K25

J25

K24

K23

K22

K21

W20

U20

T20

K20

V19
U19

K19

W18

V18

T18

K18

K17

AC1
AC2

B23
C35
AA1
AA2

Please Closed to U31-H20

1

+

C663

2

L15
CHB1608U301_0603

1 2

1

C77

2

0.1U_0402_16V4Z

L31
CHB1608U301_0603

1 2

1

C477

2

0.1U_0402_16V4Z

5

POWER

VCC8
VCC9
VCC10
VCC11
VCC12
VCC13
VCC14
VCC15
VCC16
VCC17
VCC18
VCC19
VCC20
VCC21
VCC22
VCC23
VCC24
VCC25
VCC26
VCC27
VCC28
VCC29
VCC30
VCC31
VCC32
VCC33
VCC34
VCC35
VCC36
VCC37
VCC38
VCC39
VCC40
VCC41
VCC42
VCC43
VCC44
VCC45
VCC46
VCC47
VCC48

VCCD_HMPLL1
VCCD_HMPLL2
VCCA_DPLLA
VCCA_DPLLB
VCCA_HPLL
VCCA_MPLL

ALVISO_BGA1257

1

C664

2

0.1U_0402_16V4Z

+1.5VS_DPLLB

+1.5VS

+1.5VS_MPLL

+1.5VS

1000P_0402_50V7K@

1

2

1

2

C73

10U_1206_16V4Z
1000P_0402_50V7K@

C161

10U_1206_16V4Z
1000P_0402_50V7K@

VCCA_TVDACA0
VCCA_TVDACA1
VCCA_TVDACB0
VCCA_TVDACB1
VCCA_TVDACC0
VCCA_TVDACC1

VCCA_TVBG

VSSA_TVBG

VCCD_TVDAC

VCCDQ_TVDAC

VCCD_LVDS0
VCCD_LVDS1
VCCD_LVDS2

VCCA_LVDS

VCCHV0
VCCHV1
VCCHV2

VCCTX_LVDS0
VCCTX_LVDS1
VCCTX_LVDS2

VCCA_SM0
VCCA_SM1
VCCA_SM2
VCCA_SM3

VCC3G0
VCC3G1
VCC3G2
VCC3G3
VCC3G4
VCC3G5
VCC3G6

VCCA_3GPLL0
VCCA_3GPLL1
VCCA_3GPLL2

VCCA_3GBG

VSSA_3GBG

VCC_SYNC

VCCA_CRTDAC0
VCCA_CRTDAC1

VSSA_CRTDAC

1

C665

2

60mA

+1.5VS_DPLLB

1

C87

2

60mA

+1.5VS_MPLL

1

C167

2

0307

120mA

F17
E17
D18
C18
F18
E18

H18
G18

D19
H17

24mA

B26
B25
A25

60mA

A35

10mA

B22
B21

2mA

A21
B28

A28

60mA

A27
AF20

AP19
AF19
AF18

AE37
W37
U37
R37

1500mA

N37
L37
J37

Y29
Y28
Y27

F37

0.15mA

G37
H20
F19

E19
G19

L16
CHB1608U301_0603

1 2

1

C80

2

0.1U_0402_16V4Z

L21
CHB1608U301_0603

1 2

1

C155

2

0.1U_0402_16V4Z

+3VS_TVDAC

1

+

C55

2

+1.5VS

+2.5VS

+1.5VS_DDRDLL

+1.5VS_PEG

0.47U_0603_16V4Z

+1.5VS_3GPLL

+2.5VS_3GBG

+2.5VS

70mA

0.47U_0603_16V4Z

+2.5VS

+1.5VS_DDRDLL

+1.5VS

+1.5VS_3GPLL

+1.5VS

4

150U_D2_6.3VMTV@

C432

C431

0.22U_0402_10V4Z

0.22U_0402_10V4Z

+1.5VS_DDRDLL

1

C183

2

10U_1206_16V4Z

1000P_0402_50V7K@

+1.5VS_3GPLL

1

C184

2

10U_1206_16V4Z
1000P_0402_50V7K@

+1.05VS

1

2

1

2

C163

1

2

1

2

1

C131

2

1

1

C181

2

2

R159

0.5_0603_1%

1 2

1

C171

C170

2

0.1U_0402_16V4Z

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

U31F

K13

VTT0

J13

VTT1

K12

VTT2

W11

VTT3

V11

VTT4

U11

VTT5

T11

VTT6

R11

VTT7

P11

VTT8

N11

VTT9

M11

VTT10

L11

VTT11

K11

VTT12

W10

VTT13

V10

VTT14

U10

VTT15

T10

VTT16

R10

VTT17

P10

VTT18

N10

VTT19

M10

VTT20

K10

VTT21

J10

VTT22

Y9

VTT23

W9

VTT24

U9

VTT25

R9

VTT26

P9

VTT27

N9

VTT28

M9

VTT29

L9

VTT30

J9

VTT31

N8

VTT32

M8

VTT33

N7

VTT34

M7

VTT35

N6

VTT36

M6

VTT37

A6

VTT38

N5

VTT39

M5

VTT40

N4

VTT41

M4

VTT42

N3

VTT43

M3

VTT44

N2

VTT45

M2

VTT46

B2

VTT47

V1

VTT48

N1

VTT49

M1

VTT50

G1

VTT51

ALVISO_BGA1257

R160
0_0603_5%

1 2

C186

0.1U_0402_16V4Z

+3GPLL

Issued Date

POWER

+1.5VS_PEG

+1.5VS

1

C146

2

10U_1206_16V4Z

L24
CHB1608U301_0603

1 2

0.1U_0402_16V4Z

3

VCCSM0
VCCSM1
VCCSM2
VCCSM3
VCCSM4
VCCSM5
VCCSM6
VCCSM7
VCCSM8

VCCSM9
VCCSM10
VCCSM11
VCCSM12
VCCSM13
VCCSM14
VCCSM15
VCCSM16
VCCSM17
VCCSM18
VCCSM19
VCCSM20
VCCSM21
VCCSM22
VCCSM23
VCCSM24
VCCSM25
VCCSM26
VCCSM27
VCCSM28
VCCSM29
VCCSM30
VCCSM31
VCCSM32
VCCSM33
VCCSM34
VCCSM35
VCCSM36
VCCSM37
VCCSM38
VCCSM39
VCCSM40
VCCSM41
VCCSM42
VCCSM43
VCCSM44
VCCSM45
VCCSM46
VCCSM47
VCCSM48
VCCSM49
VCCSM50
VCCSM51
VCCSM52
VCCSM53
VCCSM54
VCCSM55
VCCSM56
VCCSM57
VCCSM58
VCCSM59
VCCSM60
VCCSM61
VCCSM62
VCCSM63
VCCSM64

+1.5VS_PEG

+2.5VS_3GBG

+1.5VS

1

2

2005/03/08 2006/03/08

V1.8_DDR_CAP2

AH37

V1.8_DDR_CAP5

AP29
AD28
AD27
AC27
AP26
AN26
AM26
AL26
AK26
AJ26
AH26
AG26
AF26
AE26
AP25
AN25
AM25
AL25
AK25
AJ25
AH25
AG25
AF25
AE25
AE24
AE23
AE22
AE21
AE20
AE19
AE18
AE17
AE16
AE15
AE14
AP13
AN13
AM13
AL13
AK13
AJ13
AH13
AG13
AF13
AE13
AP12
AN12
AM12
AL12
AK12
AJ12
AH12
AG12
AF12
AE12
AD11
AC11
AB11
AB10
AB9

V1.8_DDR_CAP6

AP8

V1.8_DDR_CAP4

AM1

V1.8_DDR_CAP3

AE1

1

C153

2

4.7U_0805_10V4Z
1000P_0402_50V7K@

+2.5VS_3GBG

1

C129

2

1000P_0402_50V7K@

Compal Secret Data

V1.8_DDR_CAP1

AM37

C195

0.1U_0402_16V4Z

+1.8V

C200

330U_D2E_2.5VM

C199

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

C157

C141

2

2

4.7U_0805_10V4Z

1 2

R123 0_0603_5%

C128

Deciphered Date

C189

0.1U_0402_16V4Z

12

12

C198

0.1U_0402_16V4Z

+1.8V

2200mA

0.1U_0402_16V4Z

1

2

+2.5VS

1

2

+

C174

C101

0.1U_0402_16V4Z

1

C175

2

0.1U_0402_16V4Z

1

C100

2

0.01U_0402_16V7K

VCCA_LVDS (Ball A35)

+2.5VS

1

C91

2

4.7U_0805_10V4Z

1

C133

2

0.1U_0402_16V4Z

VCC_SYNC(Ball H20)

C197

0.1U_0402_16V4Z

12

12

C182

R153

1 2

0_0805_5%

12

+3VS

+2.5VS

1

+

2

4.7U_0805_10V4Z

+1.5VS

C168

470U_D2_2.5VM

L17

CHB1608U301_0603

1 2

1

C65

2

10U_1206_16V4Z

2

12

1000P_0402_50V7K

4000mA

2.2U_0603_6.3V6K

1

C169

C160

2

1

C176

2

0.1U_0402_16V4Z

1

C94

2

4.7U_0805_10V4Z

1

2

0.1U_0402_16V4Z

1

C154

2

2.2U_0603_6.3V6K

1

C172

2

0.1U_0402_16V4Z

1

C107

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

C144

2

0.1U_0402_16V4Z

1

C178

2

1

C92

2

4.7U_0805_10V4Z

0.1U_0402_16V4Z

C177

1

C152

2

1

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

C143

2

1

C187

2

1

C102

2

0.1U_0402_16V4Z

VCCTX_LVDS(Ball A27,A28,B28)

VCCA_CRTD AC(Ball F19 ,E19)

1

C126

2

0.1U_0402_16V4Z

1

C103

2

0.022U_0402_16V7K

VCCD_TVDAC (Ball D19)

0.1U_0402_16V4Z

1

C140

2

1

C134

2

0.022U_0402_16V7K

1

2

0.1U_0402_16V4Z

1

C120

2

1

C122

2

0.022U_0402_16V7K

VCCDQ_TVDAC (Ball H17)VCCD_LVDS(Ball A25,B25,B26)

950mA

1

C166

2

1

C158

2

2.2U_0603_6.3V6K

1

C159

2

2.2U_0603_6.3V6K

1

C132

2

2.2U_0603_6.3V6K

VCCA_TVDAC VCCA_TVBG (Ball H18)

1

1

C74

2

1

C139

C123

2

2

1000P_0402_50V7K

0.1U_0402_16V4Z

1

C136

2

0.1U_0402_16V4Z

0.022U_0402_16V7K

1

2

120mA

Title

Alviso POWER (4/5)

Size Document Number Rev

Custom

EFL50 LA-2761

Date: Sheet

951Wednesday, April 20, 2005

1

of

C130

0.2

5

4

3

2

1

U31H

+1.05VS

D D

C C

B B

+1.05VS

A A

L12

VTT_NCTF17

M12

VTT_NCTF16

N12

VTT_NCTF15

P12

VTT_NCTF14

R12

VTT_NCTF13

T12

VTT_NCTF12

U12

VTT_NCTF11

V12

VTT_NCTF10

W12

VTT_NCTF9

L13

VTT_NCTF8

M13

VTT_NCTF7

N13

VTT_NCTF6

P13

VTT_NCTF5

R13

VTT_NCTF4

T13

VTT_NCTF3

U13

VTT_NCTF2

V13

VTT_NCTF1

W13

VTT_NCTF0

Y12

VSS_NCTF68

AA12

VSS_NCTF67

Y13

VSS_NCTF66

AA13

VSS_NCTF65

L14

VSS_NCTF64

M14

VSS_NCTF63

N14

VSS_NCTF62

P14

VSS_NCTF61

R14

VSS_NCTF60

T14

VSS_NCTF59

U14

VSS_NCTF58

V14

VSS_NCTF57

W14

VSS_NCTF56

Y14

VSS_NCTF55

AA14

VSS_NCTF54

AB14

VSS_NCTF53

L15

VSS_NCTF52

M15

VSS_NCTF51

N15

VSS_NCTF50

P15

VSS_NCTF49

R15

VSS_NCTF48

T15

VSS_NCTF47

U15

VSS_NCTF46

V15

VSS_NCTF45

W15

VSS_NCTF44

Y15

VSS_NCTF43

AA15

VSS_NCTF42

AB15

VSS_NCTF41

L16

VSS_NCTF40

M16

VSS_NCTF39

N16

VSS_NCTF38

P16

VSS_NCTF37

R16

VSS_NCTF36

T16

VSS_NCTF35

U16

VSS_NCTF34

V16

VSS_NCTF33

W16

VSS_NCTF32

Y16

VSS_NCTF31

AA16

VSS_NCTF30

AB16

VSS_NCTF29

R17

VSS_NCTF28

Y17

VSS_NCTF27

AA17

VSS_NCTF26

AB17

VSS_NCTF25

AA18

VSS_NCTF24

AB18

VSS_NCTF23

AA19

VSS_NCTF22

AB19

VSS_NCTF21

AA20

VSS_NCTF20

AB20

VSS_NCTF19

R21

VSS_NCTF18

Y21

VSS_NCTF17

AA21

VSS_NCTF16

AB21

VSS_NCTF15

Y22

VSS_NCTF14

AA22

VSS_NCTF13

AB22

VSS_NCTF12

Y23

VSS_NCTF11

AA23

VSS_NCTF10

AB23

VSS_NCTF9

Y24

VSS_NCTF8

AA24

VSS_NCTF7

AB24

VSS_NCTF6

Y25

VSS_NCTF5

AA25

VSS_NCTF4

AB25

VSS_NCTF3

Y26

VSS_NCTF2

AA26

VSS_NCTF1

AB26

VSS_NCTF0

V25

VCC_NCTF10

W25

VCC_NCTF9

L26

VCC_NCTF8

M26

VCC_NCTF7

N26

VCC_NCTF6

P26

VCC_NCTF5

R26

VCC_NCTF4

T26

VCC_NCTF3

U26

VCC_NCTF2

V26

VCC_NCTF1

W26

VCC_NCTF0

ALVISO_BGA1257

5

VCCSM_NCTF31
VCCSM_NCTF30
VCCSM_NCTF29
VCCSM_NCTF28
VCCSM_NCTF27
VCCSM_NCTF26
VCCSM_NCTF25
VCCSM_NCTF24
VCCSM_NCTF23
VCCSM_NCTF22
VCCSM_NCTF21
VCCSM_NCTF20
VCCSM_NCTF19
VCCSM_NCTF18
VCCSM_NCTF17
VCCSM_NCTF16
VCCSM_NCTF15
VCCSM_NCTF14
VCCSM_NCTF13
VCCSM_NCTF12
VCCSM_NCTF11
VCCSM_NCTF10

VCCSM_NCTF9
VCCSM_NCTF8
VCCSM_NCTF7
VCCSM_NCTF6
VCCSM_NCTF5
VCCSM_NCTF4
VCCSM_NCTF3
VCCSM_NCTF2
VCCSM_NCTF1
VCCSM_NCTF0

VCC_NCTF78
VCC_NCTF77
VCC_NCTF76
VCC_NCTF75
VCC_NCTF74
VCC_NCTF73
VCC_NCTF72
VCC_NCTF71
VCC_NCTF70

NCTF

VCC_NCTF69
VCC_NCTF68
VCC_NCTF67
VCC_NCTF66
VCC_NCTF65
VCC_NCTF64
VCC_NCTF63
VCC_NCTF62
VCC_NCTF61
VCC_NCTF60
VCC_NCTF59
VCC_NCTF58
VCC_NCTF57
VCC_NCTF56
VCC_NCTF55
VCC_NCTF54
VCC_NCTF53
VCC_NCTF52
VCC_NCTF51
VCC_NCTF50
VCC_NCTF49
VCC_NCTF48
VCC_NCTF47
VCC_NCTF46
VCC_NCTF45
VCC_NCTF44
VCC_NCTF43
VCC_NCTF42
VCC_NCTF41
VCC_NCTF40
VCC_NCTF39
VCC_NCTF38
VCC_NCTF37
VCC_NCTF36
VCC_NCTF35
VCC_NCTF34
VCC_NCTF33
VCC_NCTF32
VCC_NCTF31
VCC_NCTF30
VCC_NCTF29
VCC_NCTF28
VCC_NCTF27
VCC_NCTF26
VCC_NCTF25
VCC_NCTF24
VCC_NCTF23
VCC_NCTF22
VCC_NCTF21
VCC_NCTF20
VCC_NCTF19
VCC_NCTF18
VCC_NCTF17
VCC_NCTF16
VCC_NCTF15
VCC_NCTF14
VCC_NCTF13
VCC_NCTF12
VCC_NCTF11

AB12
AC12
AD12
AB13
AC13
AD13
AC14
AD14
AC15
AD15
AC16
AD16
AC17
AD17
AC18
AD18
AC19
AD19
AC20
AD20
AC21
AD21
AC22
AD22
AC23
AD23
AC24
AD24
AC25
AD25
AC26
AD26

L17
M17
N17
P17
T17
U17
V17
W17
L18
M18
N18
P18
R18
Y18
L19
M19
N19
P19
R19
Y19
L20
M20
N20
P20
R20
Y20
L21
M21
N21
P21
T21
U21
V21
W21
L22
M22
N22
P22
R22
T22
U22
V22
W22
L23
M23
N23
P23
R23
T23
U23
V23
W23
L24
M24
N24
P24
R24
T24
U24
V24
W24
L25
M25
N25
P25
R25
T25
U25

+1.8V

+1.05VS

1

C?

2

0.1U_0603_16V7K

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

U31I

Y1

VSS271

D2

VSS270

G2

VSS269

J2

VSS268

L2

VSS260

P2

VSS259

T2

VSS258

V2

VSS257

AD2

VSS256

AE2

VSS255

AH2

VSS254

AL2

VSS253

AN2

VSS252

A3

VSS251

C3

VSS250

AA3

VSS249

AB3

VSS248

AC3

VSS247

AJ3

VSS246

C4

VSS245

H4

VSS244

L4

VSS243

P4

VSS242

U4

VSS241

Y4

VSS240

AF4

VSS239

AN4

VSS238

E5

VSS237

W5

VSS236

AL5

VSS235

AP5

VSS234

B6

VSS233

J6

VSS232

L6

VSS231

P6

VSS230

T6

VSS229

AA6

VSS228

AC6

VSS227

AE6

VSS226

AJ6

VSS225

G7

VSS224

V7

VSS223

AA7

VSS222

AG7

VSS221

AK7

VSS220

AN7

VSS219

C8

VSS218

E8

VSS217

L8

VSS216

P8

VSS215

Y8

VSS214

AL8

VSS213

A9

VSS212

H9

VSS211

K9

VSS210

T9

VSS209

V9

VSS208

AA9

VSS207

AC9

VSS206

AE9

VSS205

AH9

VSS204

AN9

VSS203

D10

VSS202

L10

VSS201

Y10

VSS200

AA10

VSS199

F11

VSS198

H11

VSS197

Y11

VSS196

ALVISO_BGA1257

1

C?

2

0.1U_0603_16V7K

VSSALVDS

VSS

1

C?

2

0.1U_0603_16V7K

2005/03/08 2006/03/08

3

Compal Secret Data

B36
AA11

VSS195

AF11

VSS194

AG11

VSS193

AJ11

VSS192

AL11

VSS191

AN11

VSS190

B12

VSS189

D12

VSS188

J12

VSS187

A14

VSS186

B14

VSS185

F14

VSS184

J14

VSS183

K14

VSS182

AG14

VSS181

AJ14

VSS180

AL14

VSS179

AN14

VSS178

C15

VSS177

K15

VSS176

A16

VSS175

D16

VSS174

H16

VSS173

K16

VSS172

AL16

VSS171

C17

VSS170

G17

VSS169

AF17

VSS168

AJ17

VSS167

AN17

VSS166

A18

VSS165

B18

VSS164

U18

VSS163

AL18

VSS162

C19

VSS161

H19

VSS160

J19

VSS159

T19

VSS158

W19

VSS157

AG19

VSS156

AN19

VSS155

A20

VSS154

D20

VSS153

E20

VSS152

F20

VSS151

G20

VSS150

V20

VSS149

AK20

VSS148

C21

VSS147

F21

VSS146

AF21

VSS145

AN21

VSS144

A22

VSS143

D22

VSS142

E22

VSS141

J22

VSS140

AH22

VSS139

AL22

VSS138

H23

VSS137

AF23

VSS136

B24

VSS135

D24

VSS134

F24

VSS133

J24

VSS132

AG24

VSS131

AJ24

VSS130

+1.5VS+1.05VS

1

C689

2

0.1U_0402_16V4Z

Deciphered Date

1

C690

2

0.1U_0402_16V4Z

U31J

AL24

VSS267

AN24

VSS266

A26

VSS265

E26

VSS264

G26

VSS263

J26

VSS262

B27

VSS261

E27

VSS129

G27

VSS128

W27

VSS127

AA27

VSS126

AB27

VSS125

AF27

VSS124

AG27

VSS123

AJ27

VSS122

AL27

VSS121

AN27

VSS120

E28

VSS119

W28

VSS118

AA28

VSS117

AB28

VSS116

AC28

VSS115

A29

VSS114

D29

VSS113

E29

VSS112

F29

VSS111

G29

VSS110

H29

VSS109

L29

VSS108

P29

VSS107

U29

VSS106

V29

VSS105

W29

VSS104

AA29

VSS103

AD29

VSS102

AG29

VSS101

AJ29

VSS100

AM29

VSS99

C30

VSS98

Y30

VSS97

AA30

VSS96

AB30

VSS95

AC30

VSS94

AE30

VSS93

AP30

VSS92

D31

VSS91

E31

VSS90

F31

VSS89

G31

VSS88

H31

VSS87

J31

VSS86

K31

VSS85

L31

VSS84

M31

VSS83

N31

VSS82

P31

VSS81

R31

VSS80

T31

VSS79

U31

VSS78

V31

VSS77

W31

VSS76

AD31

VSS75

AG31

VSS74

AL31

VSS73

A32

VSS72

C32

VSS71

Y32

VSS70

AA32

VSS69

AB32

VSS68

ALVISO_BGA1257

1

C691

2

0.1U_0402_16V4Z

2

VSS

1

C692

2

0.1U_0402_16V4Z

Title

Alviso POWER (5/5)

Size Document Number Rev

B

EFL50 LA-2761

Date: Sheet

1

C693

2

0.1U_0402_16V4Z

VSS67
VSS66
VSS65
VSS64
VSS63
VSS62
VSS61
VSS60
VSS59
VSS58
VSS57
VSS56
VSS55
VSS54
VSS53
VSS52
VSS51
VSS50
VSS49
VSS48
VSS47
VSS46
VSS45
VSS44
VSS43
VSS42
VSS41
VSS40
VSS39
VSS38
VSS37
VSS36
VSS35
VSS34
VSS33
VSS32
VSS31
VSS30
VSS29
VSS28
VSS27
VSS26
VSS25
VSS24
VSS23
VSS22
VSS21
VSS20
VSS19
VSS18
VSS17
VSS16
VSS15
VSS14
VSS13
VSS12
VSS11
VSS10

VSS9
VSS8
VSS7
VSS6
VSS5
VSS4
VSS3
VSS2
VSS1
VSS0

1

AC32
AD32
AJ32
AN32
D33
E33
F33
G33
H33
J33
K33
L33
M33
N33
P33
R33
T33
U33
V33
W33
AD33
AF33
AL33
C34
AA34
AB34
AC34
AD34
AH34
AN34
B35
D35
E35
F35
G35
H35
J35
K35
L35
M35
N35
P35
R35
T35
U35
V35
W35
Y35
AE35
C36
AA36
AB36
AC36
AD36
AE36
AF36
AJ36
AL36
AN36
E37
H37
K37
M37
P37
T37
V37
Y37
AG37

1

C694

2

0.1U_0402_16V4Z

10 51Wednesday, April 20, 2005

of

0.2

5

+1.8V +1.8V

12

C658

+1.8V +1.8V

D D

12

C660

+1.8V

12

C662

0304 EMI

C C

B B

A A

12

C659

@680P_0402_50V7K

12

C661

@680P_0402_50V7K

@680P_0402_50V7K

DDR_CKE0_DIMMA6

DDR_A_BS#27

DDR_A_BS#07
DDR_A_WE#7

DDR_A_CAS#7

DDR_CS1_DIMMA#6

D_CK_SDATA12,13,38
D_CK_SCLK1 2 ,13,38

@680P_0402_50V7K

@680P_0402_50V7K

M_ODT16

DDR_A_D0
DDR_A_D1

DDR_A_DQS#0
DDR_A_DQS0

DDR_A_D2
DDR_A_D3

DDR_A_D8
DDR_A_D9

DDR_A_DQS#1 M_CLK_DDR0
DDR_A_DQS1

DDR_A_D10
DDR_A_D11

DDR_A_D16
DDR_A_D17

DDR_A_DQS#2
DDR_A_DQS2

DDR_A_D18
DDR_A_D19

DDR_A_D24
DDR_A_D25

DDR_A_DM3

DDR_A_D26
DDR_A_D27

DDR_CKE0_DIMMA

DDR_A_BS#2
DDR_A_MA12

DDR_A_MA9 DDR_A_MA7
DDR_A_MA8

DDR_A_MA5
DDR_A_MA3
DDR_A_MA1

DDR_A_MA10
DDR_A_BS#0
DDR_A_WE#

DDR_A_CAS#
DDR_CS1_DIMMA#

M_ODT1
DDR_A_D32

DDR_A_D33
DDR_A_DQS#4

DDR_A_DQS4
DDR_A_D34

DDR_A_D35
DDR_A_D40

DDR_A_D41
DDR_A_DM5
DDR_A_D42

DDR_A_D43
DDR_A_D48

DDR_A_D49

DDR_A_DQS#6
DDR_A_DQS6

DDR_A_D50
DDR_A_D51

DDR_A_D56
DDR_A_D57

DDR_A_DM7
DDR_A_D58

DDR_A_D59
D_CK_SDATA

D_CK_SCLK

+3VS

+1.8V +1.8V

JP31

1

VREF

3

VSS

5

DQ0

7

DQ1

9

VSS

11

DQS0#

13

DQS0

15

VSS

17

DQ2

19

DQ3

21

VSS

23

DQ8

25

DQ9

27

VSS

29

DQS1#

31

DQS1

33

VSS

35

DQ10

37

DQ11

39

VSS

41

VSS

43

DQ16

45

DQ17

47

VSS

49

DQS2#

51

DQS2

53

VSS

55

DQ18

57

DQ19

59

VSS

61

DQ24

63

DQ25

65

VSS

67

DM3

69

NC

71

VSS

73

DQ26

75

DQ27

77

VSS

79

CKE0

81

VDD

83

NC

85

BA2

87

VDD

89

A12

91

A9

93

A8

95

VDD

97

A5

99

A3

101

A1

103

VDD

105

A10/AP

107

BA0

109

WE#

111

VDD

113

CAS#

115

NC/S1#

117

VDD

119

NC/ODT1

121

VSS

123

DQ32

125

DQ33

127

VSS

129

DQS4#

131

DQS4

133

VSS

135

DQ34

137

DQ35

139

VSS

141

DQ40

143

DQ41

145

VSS

147

DM5

149

VSS

151

DQ42

153

DQ43

155

VSS

157

DQ48

159

DQ49

161

VSS

163

NC,TEST

165

VSS

167

DQS6#

169

DQS6

171

VSS

173

DQ50

175

DQ51

177

VSS

179

DQ56

181

DQ57

183

VSS

185

DM7

187

VSS

189

DQ58

191

DQ59

193

VSS

195

SDA

197

SCL

199

1 2

C278

0.1U_0402_16V4Z

VDDSPD

P-TWO_A5640C-A0G16-N

Address: 1001 000X b

4

VSS
DQ4
DQ5
VSS
DM0
VSS
DQ6
DQ7

VSS
DQ12
DQ13

VSS

DM1

VSS

CK0

CK0#

VSS
DQ14
DQ15

VSS

VSS
DQ20
DQ21

VSS

DM2

VSS
DQ22
DQ23

VSS
DQ28
DQ29

VSS

DQS3#

DQS3

VSS
DQ30
DQ31

VSS

NC/CKE1

VDD

NC/A15
NC/A14

VDD

VDD

VDD

BA1

RAS#

VDD
ODT0

NC/A13

VDD

VSS
DQ36
DQ37

VSS

DM4

VSS
DQ38
DQ39

VSS
DQ44
DQ45

VSS

DQS5#

DQS5

VSS
DQ46
DQ47

VSS
DQ52
DQ53

VSS

CK1

CK1#

VSS

DM6

VSS
DQ54
DQ55

VSS
DQ60
DQ61

VSS

DQS7#

DQS7

VSS
DQ62
DQ63

VSS

SAO

SA1

3

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

42
44
46
48
50

NC

52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90

A11

92

A7

94

A6

96
98

A4

100

A2

102

A0

104
106
108
110

S0#

112
114
116
118
120

NC

122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200

DDR_A_D4
DDR_A_D5

DDR_A_DM0
DDR_A_D6

DDR_A_D7
DDR_A_D12

DDR_A_D13
DDR_A_DM1

M_CLK_DDR#0
DDR_A_D14

DDR_A_D15

DDR_A_D20
DDR_A_D21

DDR_A_DM2
DDR_A_D22

DDR_A_D23
DDR_A_D28

DDR_A_D29
DDR_A_DQS#3

DDR_A_DQS3
DDR_A_D30

DDR_A_D31
DDR_CKE1_DIMMA

DDR_A_MA11
DDR_A_MA6
DDR_A_MA4

DDR_A_MA2
DDR_A_MA0

DDR_A_BS#1
DDR_A_RAS#
DDR_CS0_DIMMA#

M_ODT0
DDR_A_MA13

DDR_A_D36
DDR_A_D37

DDR_A_DM4
DDR_A_D38

DDR_A_D39
DDR_A_D44

DDR_A_D45
DDR_A_DQS#5

DDR_A_DQS5
DDR_A_D46

DDR_A_D47
DDR_A_D52

DDR_A_D53
M_CLK_DDR1

M_CLK_DDR#1
DDR_A_DM6
DDR_A_D54

DDR_A_D55
DDR_A_D60

DDR_A_D61
DDR_A_DQS#7

DDR_A_DQS7
DDR_A_D62

DDR_A_D63

R242 10K_0402_5%

1 2

R243 10K_0402_5%

1 2

C273

M_CLK_DDR0 6
M_CLK_DDR#0 6

DDR_CKE1_DIMMA 6

DDR_A_BS#1 7
DDR_A_RAS# 7
DDR_CS0_DIMMA# 6

M_ODT0 6

M_CLK_DDR1 6
M_CLK_DDR#1 6

0.1U_0402_16V4Z

1

2

4.7U_0805_10V4Z

10U_0805_10V4Z

@

1

2

C272

+1.8V

+0.9VS

+1.8V+DIMM_VREF

12

12

@

10U_0805_10V4Z

1

1

C292

2

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

2

C303

DDR_A_MA2
DDR_A_MA4

DDR_A_MA5
DDR_A_MA8

DDR_A_MA10
DDR_A_MA11

DDR_A_BS#0
DDR_A_BS#2

DDR_A_RAS#
DDR_CKE0_DIMMA

DDR_CKE1_DIMMA
M_ODT1

R228

1K_0402_1%

R226

1K_0402_1%

@

10U_0805_10V4Z

1

1

C294

C293

10U_0805_10V4Z

@

0.1U_0402_16V4Z

1

2

C302

Layout Note:
Place one cap close to every 2 pullup
resistors terminated to +0.9VS

C295

2

2

10U_0805_10V4Z

@

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

2

C301

R264 56_0402_5%
R263 56_0402_5%

R247 56_0402_5%
R246 56_0402_5%

R248 56_0402_5%
R262 56_0402_5%

R249 56_0402_5%
R245 56_0402_5%

R265 56_0402_5%
R244 56_0402_5%

R261 56_0402_5%
R250 56_0402_5%

1

2

C300

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

1

2

C299

@

10U_0805_10V4Z

1

C296

2

0.1U_0402_16V4Z

1

2

C321

+0.9VS

2

DDR_A_D[0..63]7

DDR_A_DM[0..7]7

DDR_A_DQS[0..7]7

DDR_A_MA[0..13]7

DDR_A_DQS#[0..7]7

1

1

C298

C297

2

2

10U_0805_10V4Z

@

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

1

2

2

C316

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

2

C305

C317

R269 56_0402_5%
R254 56_0402_5%

R253 56_0402_5%
R268 56_0402_5%

R267 56_0402_5%
R252 56_0402_5%

R251 56_0402_5%
R273 56_0402_5%

R270 56_0402_5%
R255 56_0402_5%

R256 56_0402_5%
R271 56_0402_5%

R257 56_0402_5%
R272 56_0402_5%

DDR_A_D[0..63]
DDR_A_DM[0..7]
DDR_A_DQS[0..7]
DDR_A_MA[0..13]
DDR_A_DQS#[0..7]

+1.8V

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

2

C304

1

C310

C312

2

4.7U_0805_10V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

2

2

C318

DDR_A_MA0
DDR_A_MA1

DDR_A_MA3
DDR_A_MA6

DDR_A_MA7
DDR_A_MA9

DDR_A_MA12
DDR_A_MA13

DDR_A_BS#1
DDR_A_WE#

DDR_A_CAS#

DDR_CS0_DIMMA#
DDR_CS1_DIMMA#

M_ODT0

1

Layout Note:
Place near DIMM

1

1

1

2

4.7U_0805_10V4Z

C260

1

2

0.1U_0402_16V4Z

C319

C311

C313

2

4.7U_0805_10V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
C277

1

1

2

2

1

2

C320

Layout Note:
Place these resistor
closely DIMM0,all
trace length<750 mil

Layout Note:
Place these resistor
closely DIMM0,all
trace length
Max=1.3"

1

C314

2

2

4.7U_0805_10V4Z

4.7U_0805_10V4Z

0.1U_0402_16V4Z

C276

C275

1

2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS , INC . AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITT EN CON SENT O F COMPAL ELECTRONICS, INC.

2005/03/08 200 6/03/08

3

Compal Secret Data

Deciphered Date

Title

DDRII- SODIMM SLOT0

Size Document Number Rev

Custom

EFL50 LA-2761

2

Date: Sheet

11 51Wednesda y, Ap r il 20, 2005

1

0.2

of

A

+1.8V

JP26

1

VREF

3

DDR_B_D0
DDR_B_D1

DDR_B_DQS#0
DDR_B_DQS0

1 1

2 2

3 3

4 4

DDR_CKE2_DIMMB6

DDR_B_BS#27

DDR_B_BS#07
DDR_B_WE#7

DDR_B_CAS#7

DDR_CS3_DIMMB#6

M_ODT36

D_CK_SDATA11,13,38
D_CK_SCLK1 1 ,13,38

A

DDR_B_D2
DDR_B_D3

DDR_B_D8
DDR_B_D9

DDR_B_DQS#1
DDR_B_DQS1

DDR_B_D10
DDR_B_D11

DDR_B_D16
DDR_B_D17

DDR_B_DQS#2
DDR_B_DQS2

DDR_B_D18
DDR_B_D19

DDR_B_D24
DDR_B_D25

DDR_B_DM3

DDR_B_D26
DDR_B_D27

DDR_CKE2_DIMMB

DDR_B_BS#2
DDR_B_MA12

DDR_B_MA9
DDR_B_MA8

DDR_B_MA5
DDR_B_MA3
DDR_B_MA1

DDR_B_MA10
DDR_B_BS#0
DDR_B_WE#

DDR_B_CAS#
DDR_CS3_DIMMB#

M_ODT3
DDR_B_D32

DDR_B_D33
DDR_B_DQS#4

DDR_B_DQS4
DDR_B_D34

DDR_B_D35
DDR_B_D40

DDR_B_D41
DDR_B_DM5
DDR_B_D42

DDR_B_D43
DDR_B_D48

DDR_B_D49

DDR_B_DQS#6
DDR_B_DQS6

DDR_B_D50
DDR_B_D51

DDR_B_D56
DDR_B_D57

DDR_B_DM7
DDR_B_D58

DDR_B_D59
D_CK_SDATA

D_CK_SCLK

+3VS

C244

0.1U_0402_16V4Z

1 2

VSS

5

DQ0

7

DQ1

9

VSS

11

DQS0#

13

DQS0

15

VSS

17

DQ2

19

DQ3

21

VSS

23

DQ8

25

DQ9

27

VSS

29

DQS1#

31

DQS1

33

VSS

35

DQ10

37

DQ11

39

VSS

41

VSS

43

DQ16

45

DQ17

47

VSS

49

DQS2#

51

DQS2

53

VSS

55

DQ18

57

DQ19

59

VSS

61

DQ24

63

DQ25

65

VSS

67

DM3

69

NC

71

VSS

73

DQ26

75

DQ27

77

VSS

79

CKE0

81

VDD

83

NC

85

BA2

87

VDD

89

A12

91

A9

93

A8

95

VDD

97

A5

99

A3

101

A1

103

VDD

105

A10/AP

107

BA0

109

WE#

111

VDD

113

CAS#

115

NC/S1#

117

VDD

119

NC/ODT1

121

VSS

123

DQ32

125

DQ33

127

VSS

129

DQS4#

131

DQS4

133

VSS

135

DQ34

137

DQ35

139

VSS

141

DQ40

143

DQ41

145

VSS

147

DM5

149

VSS

151

DQ42

153

DQ43

155

VSS

157

DQ48

159

DQ49

161

VSS

163

NC,TEST

165

VSS

167

DQS6#

169

DQS6

171

VSS

173

DQ50

175

DQ51

177

VSS

179

DQ56

181

DQ57

183

VSS

185

DM7

187

VSS

189

DQ58

191

DQ59

193

VSS

195

SDA

197

SCL

199

VDDSPD

SUPER_AKH-110A-092-3 2S@

Address: 1001 010X b

VSS
DQ4
DQ5
VSS
DM0
VSS
DQ6
DQ7

VSS
DQ12
DQ13

VSS

DM1

VSS

CK0
CK0#

VSS
DQ14
DQ15

VSS

VSS
DQ20
DQ21

VSS

DM2

VSS
DQ22
DQ23

VSS
DQ28
DQ29

VSS

DQS3#

DQS3

VSS
DQ30
DQ31

VSS

NC/CKE1

VDD
NC/A15
NC/A14

VDD

VDD

VDD

BA1

RAS#

VDD

ODT0

NC/A13

VDD

VSS
DQ36
DQ37

VSS

DM4

VSS
DQ38
DQ39

VSS
DQ44
DQ45

VSS

DQS5#

DQS5

VSS
DQ46
DQ47

VSS
DQ52
DQ53

VSS

CK1
CK1#

VSS

DM6

VSS
DQ54
DQ55

VSS
DQ60
DQ61

VSS

DQS7#

DQS7

VSS
DQ62
DQ63

VSS

SAO

SA1

B

+1.8V

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

42
44
46
48
50

NC

52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90

A11

92

A7

94

A6

96
98

A4

100

A2

102

A0

104
106
108
110

S0#

112
114
116
118
120

NC

122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200

DDR_B_D4
DDR_B_D5

DDR_B_DM0
DDR_B_D6

DDR_B_D7
DDR_B_D12

DDR_B_D13
DDR_B_DM1
M_CLK_DDR3

M_CLK_DDR#3
DDR_B_D14

DDR_B_D15

DDR_B_D20
DDR_B_D21

DDR_B_DM2
DDR_B_D22

DDR_B_D23
DDR_B_D28

DDR_B_D29
DDR_B_DQS#3

DDR_B_DQS3
DDR_B_D30

DDR_B_D31
DDR_CKE3_DIMMB

DDR_B_MA11
DDR_B_MA7
DDR_B_MA6

DDR_B_MA4
DDR_B_MA2
DDR_B_MA0

DDR_B_BS#1
DDR_B_RAS#
DDR_CS2_DIMMB#

M_ODT2
DDR_B_MA13

DDR_B_D36
DDR_B_D37

DDR_B_DM4
DDR_B_D38

DDR_B_D39
DDR_B_D44

DDR_B_D45
DDR_B_DQS#5

DDR_B_DQS5
DDR_B_D46

DDR_B_D47
DDR_B_D52

DDR_B_D53
M_CLK_DDR4

M_CLK_DDR#4
DDR_B_DM6
DDR_B_D54

DDR_B_D55
DDR_B_D60

DDR_B_D61
DDR_B_DQS#7

DDR_B_DQS7
DDR_B_D62

DDR_B_D63

+DIMM_VREF

M_CLK_DDR3 6
M_CLK_DDR#3 6

DDR_CKE3_DIMMB 6

DDR_B_BS#1 7
DDR_B_RAS# 7
DDR_CS2_DIMMB# 6

M_ODT2 6

M_CLK_DDR4 6
M_CLK_DDR#4 6

R222 10K_0402_5%

1 2

R223 10K_0402_5%

1 2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS , INC . AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITT EN CON SENT O F COMPAL ELECTRONICS, INC.

C252

C

0.1U_0402_16V4Z

1

1

2

2

4.7U_0805_10V4Z

+1.8V

1

C250

0.1U_0402_16V4Z

2

+0.9VS

0.1U_0402_16V4Z

+3VS

2005/03/08 200 6/03/08

C

DDR_B_D[0..63]7

DDR_B_DM[0..7]7

DDR_B_DQS[0..7]7

C251

DDR_B_MA[0..13]7

DDR_B_DQS#[0..7]7

+1.8V

1

C289

0.1U_0402_16V4Z

2

1

C249

0.1U_0402_16V4Z

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

2

C282

1

2

2

C285

C284

Layout Note:
Place one cap close to every 2 pullup
resistors terminated to +0.9VS

DDR_B_BS#2
DDR_CKE2_DIMMB

DDR_B_MA5
DDR_B_MA8

DDR_B_BS#0
DDR_B_MA10

M_ODT3
DDR_CS3_DIMMB#

DDR_B_MA7
DDR_B_MA6

DDR_B_RAS#
DDR_CS2_DIMMB#

Compal Secret Data

DDR_B_D[0..63]
DDR_B_DM[0..7]
DDR_B_DQS[0..7]
DDR_B_MA[0..13]
DDR_B_DQS#[0..7]

1

C288

0.1U_0402_16V4Z

2

1

C248

0.1U_0402_16V4Z

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

2

2

C259

R203 56_0402_5%

1 2

R202 56_0402_5%

1 2

R205 56_0402_5%

1 2

R204 56_0402_5%

1 2

R207 56_0402_5%

1 2

R206 56_0402_5%

1 2

R209 56_0402_5%

1 2

R208 56_0402_5%

1 2

R229 56_0402_5%

1 2

R230 56_0402_5%

1 2

R231 56_0402_5%

1 2

R232 56_0402_5%

1 2

Deciphered Date

0.1U_0402_16V4Z

C283

Layout Note:
Place near DIMM

1

C286

0.1U_0402_16V4Z

2

1

C247

0.1U_0402_16V4Z

2

0.1U_0402_16V4Z

1

1

2

2

C254

C253

D

1

C287

0.1U_0402_16V4Z

2

1

C246

0.1U_0402_16V4Z

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

2

2

C255

C256

+0.9VS

R211 56_0402_5%

1 2

R210 56_0402_5%

1 2

R213 56_0402_5%

1 2

R212 56_0402_5%

1 2

R215 56_0402_5%

1 2

R214 56_0402_5%

1 2

R233 56_0402_5%

1 2

R234 56_0402_5%

1 2

R235 56_0402_5%

1 2

R236 56_0402_5%

1 2

R237 56_0402_5%

1 2

R238 56_0402_5%

1 2

R239 56_0402_5%

1 2

R240 56_0402_5%

1 2

D

E

+1.8V

1

C325

2

4.7U_0805_10V4Z

4.7U_0805_10V4Z

0.1U_0402_16V4Z

C262

1

2

1

0.1U_0402_16V4Z

2

0.1U_0402_16V4Z

1

1

2

2

C258

C257

DDR_B_MA9
DDR_B_MA12

DDR_B_MA1
DDR_B_MA3

DDR_B_CAS#
DDR_B_WE#

DDR_CKE3_DIMMB
DDR_B_MA11

DDR_B_MA4
DDR_B_MA2

DDR_B_MA0
DDR_B_BS#1

M_ODT2
DDR_B_MA13

C261

1

2

C274

C322

0.1U_0402_16V4Z

1

2

+1.8V

C323

0.1U_0402_16V4Z

1

2

1

C245

0.1U_0402_16V4Z

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

2

2

C280

C281

Title

DDRII-SODIMM SLOT1

Size Document Number Rev

Custom

EFL50 LA-2761

Date: Sheet

1

1

C324

2

2

4.7U_0805_10V4Z

4.7U_0805_10V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

C264

C263

1

2

1

C291

0.1U_0402_16V4Z

2

1

+

C328
150U_D2_6.3VM

2

Layout Note:
Place these resistor
closely DIMM0,all
trace length<750 mil

Layout Note:
Place these resistor
closely DIMM0,all
trace length
Max=1.3"

E

C326

1

2

4.7U_0805_10V4Z

C265

1

2

1

2

0.1U_0402_16V4Z

1

+

C306
150U_D2_6.3VM

2

of

12 51Wednesda y, Ap r il 20, 2005

C290

0.2

A

FSC FSB FSA CPU

CLKSEL0 CLKSEL1 CLKSEL2

*

1 1

0
0

0
0
1
1

+3VS

A

CLKSEL2

CLK_PCI2

CLK_PCI0

CLK_PCI1

CK_SCLK

CK_SDATA

+1.05VS

R522

1 2

R512
0_0402_5%

1 2

R495 10K_0402_5%

1 2

R523 10K_0402_5%

1 2

R500 10K_0402_5%

1 2

R492 10K_0402_5%

2 2

CLK_PCI0 = 0, Pin 35,36
are PCIe CLK pair

CLK_PCI1 = 0, Pin 17,18
are 96Mhz

3 3

CK_SCLK18

CK_SDATA18

R519

4.7K_0402_5%

CLKSEL0

4 4

1 2
1 2

R526
0_0402_5%@

11
1
1
00

CLK_PCI2 = 1, Pin 32,33
are PEREQ# pin

CLK_ICH_48M18
CLK_SD_48M22

CLK_14M_CODEC29

CLK_PCI_PCM22
CLK_PCI_LAN25
CLK_PCI_MINI127
CLK_PCI_MINI228
CLK_PCI_SIO32
CLK_PCI_139424
CLK_PCI_LPC33
CLK_PCI_ICH16

D_CK_SCLK11,12,38

D_CK_SDATA11,12,38

+3VS

2

G

1 3

D

S

Q33
2N7002_SOT23

+3VS

2

G

1 3

D

S

Q34
2N7002_SOT23

1K_0402_5%@
R518

0_0402_5%

1 2

MCH_CLKSEL0
CPU_BSEL0

12

22P_0402_50V8J

R503

4.7K_0402_5%

1 2

R502

4.7K_0402_5%

1 2

B

+CLK_VDD48 +CLK_VDDREF

1

C541

2

2.2U_0603_6.3V6K

+CLK_VDD2

MHz

100
133
166
200

SRC

PCI

MHz

MHz

100 33.3
100

33.3

100

33.3

100

33.3

Table : ICS 954206B

C544

1 2

C542

22P_0402_50V8J

1 2

D_CK_SCLK

D_CK_SDATA

Y3

14.318MHZ_16PF_DSX840GA

12

CLK_ICH_48M

CLK_14M_CODEC CLKSEL0

CLK_PCI_PCM

CLK_PCI_MINI1 CLK_PCI4
CLK_PCI_MINI2

CLK_PCI_1394
CLK_PCI_LPC
CLK_PCI_ICH
D_CK_SCLK

D_CK_SDATA

+3VS

+3VS

MCH_CLKSEL0 6

CPU_BSEL0 5

B

R494 12_0402_5%
R499 12_0402_5%
R520 33_0402_5%

1 2

R506

1 2

R507 12_0402_5%

1 2

R510 33_0402_5%2S@

1 2

R511 33_0402_5%1S@

1 2

R516 33_0402_5%

1 2

R524 33_0402_5%

1 2

R493 33_0402_5%

1 2

R501 33_0402_5%

R515

4.7K_0402_5%

CLKSEL1 MCH_CLKSEL1

1 2
1 2

R521
0_0402_5%@

1 2
1 2

12_0402_5%

+1.05VS

1 2

1 2

R508 1_0402_5%

1 2

R517 2.2_0402_5%

12

R475 475_0402_1%

R525

R509
0_0402_5%

C

CLK_PCI3
CLK_PCI2
CLK_PCI1

1 2

1K_0402_5%@
R505

0_0402_5%

1 2

C

1

C537

2

0.047U_0402_16V7K

+CLK_VDD1

+CLK_VDD1

+CLK_VDDREF

+CLK_VDD48

XTALIN
XTALOUT

CLKSEL2CLK_SD_48M

CLKSEL1

CLK_PCI5CLK_PCI_LAN

CLK_PCI0

CLKIREF

CPU_BSEL1

12

1

C539

0.047U_0402_16V7K

2

U33

21

VDDPCIEX_0

28

VDDPCIEX_1

34

VDDPCIEX_2

1

VDDPCI_0

7

VDDPCI_1

42

VDDCPU

48

VDDREF

15mil

11

VDD48

15mil

50

X1

49

X2

12

FS_A/USB_48MHz

53

REF1/FSLC/TEST_SEL

16

FSLB/TEST_MODE

5

PCICLK5

4

PCICLK4

3

PCICLK3

56

PCICLK2/REQ_SEL

9

SELPCIEX_LCDCLK#/PCICLK_F1

8

ITP_EN/PCICLK_F0

46

SCLK

47

SDATA

39

IREF

15mil

13

GND_0

29

GND_1

2

GND_2

45

GND_3

51

GND_4

6

GND_5

ICS954226AGT_TSSOP56

MCH_CLKSEL1 6

CPU_BSEL1 5

D

L32
KC FBM-L11-201209-221LMAT_0805

1 2

+3VS

VDDA
GNDA

PCI/SRC_STOP#

CPU_STOP#

CPUCLKT1
CPUCLKC1

CPUCLKT0
CPUCLKC0

CPUCLKT2_ITP/PCIEXT6

CPUCLKC2_ITP/PCIEXC6

PEREQ1#/PCIEXT5
PEREQ2#/PCIEXC5

PCIEXT4
PCIEXC4

SATACLKT
SATACLKC

PCIEXT3
PCIEXC3

PCIEXT2
PCIEXC2

PCIEXT1
PCIEXC1

LCDCLK_SS/PCIEX0T

LCDCLK_SS/PCIEX0C

DOTT_96MHz
DOTC_96MHz

VTT_PWRGD#/PD

REF0

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SE CRET INFO RMATI ON. THIS SHEET MAY NO T BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

D

E

1

C524

2.2U_0603_6.3V6K

2

1

37
38

55
54

41
40

44
43

36
35

33
32

31
30

26
27

24
25

22
23

19
20

17
18

14
15

10
52

2

PM_STP_PCI#
PM_STP_CPU#

CLK_CPU1
CLK_CPU1#

CLK_CPU0
CLK_CPU0#

CLK_SRC3
CLK_SRC3# CLK_MCH_3GPLL#

PEREQ2#
PEREQ1#

CLK_SRC2#

CLK_SRC4
CLK_SRC4#

CLK_SRC6
CLK_SRC6#

CLK_SRC7
CLK_SRC7#

CLK_SRC1
CLK_SRC1#

CLK_SRC0
CLK_SRC0#

CLK_DOT
CLK_DOT#

CLK_REF CLK_14M_SIO

E

1

C525

0.047U_0402_16V7K

2

+CLK_VCCA

40mil

C523

2.2U_0603_6.3V6K

R485 33_0402_5%
R478 33_0402_5%

R497 33_0402_5%
R490 33_0402_5%

R468 33_0402_5%
R463 33_0402_5%

R455 0_0402_5%
R456 0_0402_5%

R450 33_0402_5%
R446 33_0402_5%

R447 33_0402_5%
R442 33_0402_5%

R453 33_0402_5%
R451 33_0402_5%

R460 33_0402_5%
R457 33_0402_5%

R470 33_0402_5%
R465 33_0402_5%

R479 33_0402_5%
R473 33_0402_5%

R486 33_0402_5%
R481 33_0402_5%

1 2

R513 12_0402_5%

1 2

R514 12_0402_5%

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

1

2

F

1 2

R472

2.2_0402_5%

C532

0.047U_0402_16V7K

PM_STP_PCI# 18
PM_STP_CPU# 18,46

CLK_ICH_14M

F

1

C536

0.047U_0402_16V7K

2

+CLK_VDD1

CLK_MCH_BCLK
CLK_MCH_BCLK#

CLK_CPU_BCLK
CLK_CPU_BCLK#

CLK_MCH_3GPLL

PE_REQ2#
PE_REQ1#

CLK_PCIE_VGACLK_SRC2
CLK_PCIE_VGA#

CLK_EZ_CLK2
CLK_EZ_CLK2#

CLK_EZ_CLK1
CLK_EZ_CLK1#

CLK_PCIE_ICH
CLK_PCIE_ICH#

CLK_PCIE_SATA
CLK_PCIE_SATA#

CLK_DREF_SSC
CLK_DREF_SSC#

CLK_DREF_96M
CLK_DREF_96M#

1 2

+3VS

R488 10K_0402_5%

VTT_POWERGD#

CLK_14M_SIO 32

CLK_ICH_14M 18

+3VS

G

40mil

1

C529

0.047U_0402_16V7K

2

L33

KC FBM-L11-201209-221LMAT_0805

1 2

CLK_MCH_BCLK 6
CLK_MCH_BCLK# 6

CLK_CPU_BCLK 4
CLK_CPU_BCLK# 4

CLK_MCH_3GPLL 8
CLK_MCH_3GPLL# 8

PE_REQ2# 33
PE_REQ1# 33

CLK_PCIE_VGA 15
CLK_PCIE_VGA# 15

CLK_EZ_CLK2 38
CLK_EZ_CLK2# 38

CLK_EZ_CLK1 38
CLK_EZ_CLK1# 38

CLK_PCIE_ICH 18
CLK_PCIE_ICH# 18

CLK_PCIE_SATA 17
CLK_PCIE_SATA# 17

CLK_DREF_SSC 6
CLK_DREF_SSC# 6

CLK_DREF_96M 6
CLK_DREF_96M# 6

Title

Size Document Number Rev

Date: Sheet

+CLK_VDD1

+CLK_VDD1

1

C546

2

2.2U_0603_6.3V6K

1 3

Wednesday, April 20, 2005

G

1

C533

0.047U_0402_16V7K

2

VGATE

2

G

D

S

Q35
2N7002_SOT23

Compal Electronics, Inc.

Clock Generator

40mil

+CLK_VDD2

1

C545

2

0.047U_0402_16V7K

CLK_MCH_BCLK
CLK_MCH_BCLK#
CLK_CPU_BCLK
CLK_CPU_BCLK#
CLK_EZ_CLK1
CLK_EZ_CLK1#

CLK_PCIE_SATA
CLK_PCIE_SATA#
CLK_MCH_3GPLLCLK_PCI_SIO
CLK_MCH_3GPLL#
CLK_PCIE_VGA
CLK_PCIE_VGA#
CLK_PCIE_ICH
CLK_PCIE_ICH#
CLK_DREF_SSC
CLK_DREF_SSC#
CLK_DREF_96M
CLK_DREF_96M#
CLK_EZ_CLK2
CLK_EZ_CLK2#

VGATE 6,18,46

Clock Generator

EFL50 LA-2761

H

+CLK_VDD2

1

C538

2

0.047U_0402_16V7K

1 2

R484 49.9_0402_1%

1 2

R477 49.9_0402_1%

1 2

R496 49.9_0402_1%

1 2

R489 49.9_0402_1%

1 2

R454 49.9_0402_1%

1 2

R452 49.9_0402_1%

1 2

R471 49.9_0402_1%

1 2

R466 49.9_0402_1%

1 2

R467 49.9_0402_1%

1 2

R462 49.9_0402_1%

1 2

R449 49.9_0402_1%

1 2

R445 49.9_0402_1%

1 2

R461 49.9_0402_1%

1 2

R458 49.9_0402_1%

1 2

R480 49.9_0402_1%

1 2

R474 49.9_0402_1%

1 2

R487 49.9_0402_1%

1 2

R482 49.9_0402_1%

1 2

R448 49.9_0402_1%

1 2

R443 49.9_0402_1%

13 51

H

0.2

of

A

CRT Connector

CRT_RQ
CRT_GQ
CRT_BQ

1 1

VGA_CRT_R
GMCH_CRT_R

VGA_CRT_G
GMCH_CRT_G

VGA_CRT_B
GMCH_CRT_B

VGA_CRT_R15
GMCH_CRT_R8

VGA_CRT_G15
GMCH_CRT_G8

VGA_CRT_B15
GMCH_CRT_B8

2 2

R40 0_0402_5%PM@

1 2
1 2

R39 0_0402_5%GM@
R37 0_0402_5%PM@

1 2
1 2

R38 0_0402_5%GM@
R59 0_0402_5%PM@

1 2
1 2

R60 0_0402_5%GM@

VGA_CRT_R
GMCH_CRT_R

VGA_CRT_G
GMCH_CRT_G

VGA_CRT_B
GMCH_CRT_B

1 2

R375 0_0402_5%ND@

1 2

R376 0_0402_5%ND@

1 2

R389 0_0402_5%ND@

DOCKIN#21,26,33,38

VGA_CRT_HSYNC15
GMCH_CRT_HSYNC8

CRT_R
CRT_G
CRT_B

DOCKIN#

CRT_RQ
CRT_GQ
CRT_BQ

VGA_CRT_HSYNC
GMCH_CRT_HSYNC

VGA_CRT_VSYNC15
GMCH_CRT_VSYNC8

U4

1

SEL

15

OE#

4

1A

7

2A

9

3A

12

4A

8

GND

FSAV330MTC_TSSOP16WD@

B

16

VCC

2

1B1

5

2B1

11

3B1

14

4B1

3

1B2

6

2B2

10

3B2

13

4B2

150_0402_5%

1 2

R373 0_0402_5%PM@

1 2

R372 39_0402_5%GM@

VGA_CRT_VSYNC
GMCH_CRT_VSYNC

+5VS

1 2

C22

D_CRT_R
D_CRT_G
D_CRT_B

12

12

R32

R30

150_0402_5%

1 2

C399 0.1U_0402_16V4Z

1 2

R377 0_0402_5%PM@

1 2

R378 39_0402_5%GM@

C

0.1U_0402_16V4Z

+3VS

D_CRT_R 38
D_CRT_G 38
D_CRT_B 38

CRT_R CRT_R_L

CRT_G

CRT_B

12

R25

150_0402_5%

CRT_HSYNC D_CRT_HSYNC

1

C5

2

8P_0402_50V8K

+CRT_VCC

1

5

P

4

OE#

A2Y

G

U27

SN74AHCT1G125GW_SOT353-5

3

1 2

C400 0.1U_0402_16V4Z

1

C10

2

8P_0402_50V8K

+CRT_VCC

5

CRT_VSYNC D_CRT_VSYNC

P

A2Y

G

3

1 2

L5

FCM2012C-800_0805

1 2

L4

FCM2012C-800_0805

1 2

L2

FCM2012C-800_0805

1

C14

2

R370 10K_0402_5%

8P_0402_50V8K

8P_0402_50V8K

10P for GMCH

12

1

4

OE#

U28
SN74AHCT1G125GW_SOT353-5

CRT_G_L

CRT_B_L

C16

D21

DAN217_SC59@

1

2

3

1

C11

2

8P_0402_50V8K

1 2

L3 FCM1608C-121T_0603

1 2

L1 FCM1608C-121T_0603

D

D20

DAN217_SC59@

1

2

3

1

2

10P_0402_50V8J

33P for GMCH

1

D19

DAN217_SC59@

2

3

1

C8

8P_0402_50V8K

2

HSYNC_L

VSYNC_L

1

C9

2

D_CRT_HSYNC 38

D_CRT_VSYNC 38

+5VS

RB411D_SOT23

1

C6
10P_0402_50V8J

2

D18

2 1

W=40mils

F1

1.1A_6VDC_FUSE

0.1U_0402_16V4Z

DDC_MD2

C4

100P_0402_25V8K

1

2

C13
68P_0402_50V8K

21

C398

E

W=40mils

1

2

6

11

1
7

12

2
8

13

3
9

14

4
10
15

5

SUYIN_070112FR015S2227U

D_DDC_DATA

D_DDC_CLK

1

C3
68P_0402_50V8K

2

+CRT_VCC+R_CRT_VCC

JP3

(CL55)

3 3

D_DDC_DATA38

D_DDC_CLK38

4 4

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SE CRET INFO RMATI ON. THIS SHEET MAY NO T BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

4.7K_0402_5%

D_DDC_CLK

+CRT_VCC

R371

12

4.7K_0402_5%

12

R374

Q3
2N7002_SOT23

D

R43 0_0402_5%PM@

1 2

R48 0_0402_5%GM@

1 2

2

G

1 3

D

S

2

1 3

D

Q4
2N7002_SOT23

+3VS

+2.5VS

R41 0_0402_5%GM@

G

S

R47

Title

Size Document Number Rev

Date: Sheet

GMCH_CRT_DATA

12

VGA_DDC_DATAD_DDC_DATA

VGA_DDC_CLK

GMCH_CRT_CLK

12

0_0402_5%GM@

Compal Electronics, Inc.

CRT & TVout Connector

Wednesday, April 20, 2005

EFL50 LA-2761

GMCH_CRT_DATA 8

VGA_DDC_DATA 15

VGA_DDC_CLK 15

GMCH_CRT_CLK 8

14 51

E

of

0.2

5

4

3

2

1

PCEI_GTX_C_MRX_N[0..15]8,41

LCD POWER CIRCUIT

D D

2

G

12

INVT_PWM

1U_0603_10V4Z@

2

G

+3V

R63
1K_0402_5%

1 2

13

D

S

Q43
BSS138_SOT23

BKOFF#33

+3VS

R624

12

1

C29

2

0.047U_0402_16V7KGM@

D3
RB751V_SOD323

21

100K_0402_5%

GM@

R65

100K_0402_5%GM@

1 2

BKOFF# DISPO FF#

GMCH_ENBKL8,33

G

2

1 3

1

4.7U_0805_10V4ZGM@

2

+3VS

12

R57

4.7K_0402_5%

1 2

R86 0_0402_5%GM@

W=60mils

S

Q6

W=60mils

D

+LCDVDD

C21

SI2301BDS_SOT23GM@

+LCDVDD

1

C27

0.1U_0402_16V4ZGM@

2

ENBKLGMCH_ENBKL

+LCDVDD

12

R61

300_0603_1%GM@

13

D

Q7

2N7002_SOT23GM@

GMCH_ENVDD8

C C

+3VS

1

C25

2

D5

1N4148_SOT23@

B B

GMCH_ENVDD

10K_0402_5%

0.1U_0402_16V4Z@

12

S

R625

1

C33

2

LCD/PANEL BD. Conn.

B+

+3VS

GMCH_LCD_CLK8

GMCH_LCD_DATA8

GMCH_TZOUT0-8
GMCH_TZOUT0+8

GMCH_TZOUT1+8
GMCH_TZOUT1-8

GMCH_TZOUT2+8
GMCH_TZOUT2-8

GMCH_TZCLK-8

A A

GMCH_TZCLK+8

GMCH_LCD_CLK
GMCH_LCD_DATA

GMCH_TZOUT0-

GMCH_TZOUT1+
GMCH_TZOUT1-

GMCH_TZOUT2+
GMCH_TZOUT2-

GMCH_TZCLK­GMCH_TZCLK+

LCD_ID

JP16

1

21

2

22

3

23

4

24

5

25

6

26

7

27

8

28

9

29

10

30

11

31

12

32

13

33

14

34

15

35

16

36

17

37

18

38

19

39

20

40

ACES_88107-4000G

GM@

DAC_BRIG
INVT_PWM
DISPOFF#

GMCH_TXOUT0­GMCH_TXOUT0+GMCH_TZOUT0+

GMCH_TXOUT1­GMCH_TXOUT1+

GMCH_TXOUT2+
GMCH_TXOUT2-

GMCH_TXCLK­GMCH_TXCLK+

DAC_BRIG 33
INVT_PWM 33

+LCDVDD

GMCH_TXOUT0- 8
GMCH_TXOUT0+ 8

GMCH_TXOUT1- 8
GMCH_TXOUT1+ 8

GMCH_TXOUT2+ 8
GMCH_TXOUT2- 8

GMCH_TXCLK- 8
GMCH_TXCLK+ 8

PCEI_GTX_C_MRX_P[0..15]8,41

PCIE_MTX_C_GRX_N[0..15]8,41
PCIE_MTX_C_GRX_P[0..15]8,41

VGA_CRT_R14
VGA_CRT_G14

VGA_CRT_B14
VGA_CRT_VSYNC14
VGA_CRT_HSYNC14

VGA_DDC_CLK14
VGA_DDC_DATA14

DVI_TXC+41
DVI_TXC-41
DVI_TXD0+41
DVI_TXD0-41

DVI_TXD1+41
DVI_TXD1-41
DVI_TXD2+41
DVI_TXD2-41

CLK_PCIE_VGA13
CLK_PCIE_VGA#13

+5VALW

+5VS

+3VALW

+2.5VS
+1.8VS

PCEI_GTX_C_MRX_N[0..15]
PCEI_GTX_C_MRX_P[0..15]

PCIE_MTX_C_GRX_N[0..15]

PCIE_MTX_C_GRX_P[0..15]

VGA_CRT_R
VGA_CRT_G
VGA_CRT_B
VGA_CRT_VSYNC
VGA_CRT_HSYNC

PCIE_MTX_C_GRX_P0
PCIE_MTX_C_GRX_N0

PCIE_MTX_C_GRX_P1
PCIE_MTX_C_GRX_N1

PCIE_MTX_C_GRX_P2
PCIE_MTX_C_GRX_N2

PCIE_MTX_C_GRX_P3
PCIE_MTX_C_GRX_N3

PCIE_MTX_C_GRX_P4
PCIE_MTX_C_GRX_N4

PCIE_MTX_C_GRX_P5
PCIE_MTX_C_GRX_N5

PCIE_MTX_C_GRX_P6
PCIE_MTX_C_GRX_N6

PCIE_MTX_C_GRX_P7
PCIE_MTX_C_GRX_N7

PCIE_MTX_C_GRX_P8
PCIE_MTX_C_GRX_N8

PCIE_MTX_C_GRX_P9
PCIE_MTX_C_GRX_N9

PCIE_MTX_C_GRX_P10
PCIE_MTX_C_GRX_N10

PCIE_MTX_C_GRX_P11
PCIE_MTX_C_GRX_N11

PCIE_MTX_C_GRX_P12
PCIE_MTX_C_GRX_N12

PCIE_MTX_C_GRX_P13
PCIE_MTX_C_GRX_N13

PCIE_MTX_C_GRX_P14
PCIE_MTX_C_GRX_N14

PCIE_MTX_C_GRX_P15
PCIE_MTX_C_GRX_N15

VGA_DDC_CLK
VGA_DDC_DATA

DVI_TXC+
DVI_TXC­DVI_TXD0+
DVI_TXD0-

DVI_TXD1+
DVI_TXD1­DVI_TXD2+
DVI_TXD2-

CLK_PCIE_VGA
CLK_PCIE_VGA#

VGA BOARD Conn.

JP22

1 2
3 4
5 6
7 8
9 10
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
29 30
31 32
33 34
35 36
37 38
39 40
41 42
43 44
45 46
47 48
49 50
51 52
53 54
55 56
57 58
59 60
61 62
63 64
65 66
67 68
69 70
71 72
73 74
75 76
77 78
79 80
81 82
83 84
85 86
87 88
89 90
91 92
93 94
95 96
97 98
99 100
101 102
103 104
105 106
107 108
109 110
111 112
113 114
115 116
117 118
119 120
121 122
123 124
125 126
127 128
129 130
131 132
133 134
135 136
137 138
139 140
141 142
143 144
145 146
147 148
149 150
151 152
153 154
155 156
157 158
159 160

ACES_88081-1600PM@

Reverse for Layout

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SE CRET INFO RMATI ON. THIS SHEET MAY NO T BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

VGA_CRT_R
VGA_CRT_G
VGA_CRT_B
VGA_TV_LUMA
VGA_TV_CRMA
VGA_TV_COMPS

R618 150_0402_5%

1 2

R619 150_0402_5%

1 2

R620 150_0402_5%

1 2

R621 150_0402_5%

1 2

R622 150_0402_5%

1 2

R623 150_0402_5%

1 2

2005/01/24

B+

VGA_TV_LUMA
VGA_TV_CRMA
VGA_TV_COMPS

PCEI_GTX_C_MRX_P0
PCEI_GTX_C_MRX_N0

PCEI_GTX_C_MRX_P1
PCEI_GTX_C_MRX_N1

PCEI_GTX_C_MRX_P2
PCEI_GTX_C_MRX_N2

PCEI_GTX_C_MRX_P3
PCEI_GTX_C_MRX_N3

PCEI_GTX_C_MRX_P4
PCEI_GTX_C_MRX_N4

PCEI_GTX_C_MRX_P5
PCEI_GTX_C_MRX_N5

PCEI_GTX_C_MRX_P6
PCEI_GTX_C_MRX_N6

PCEI_GTX_C_MRX_P7
PCEI_GTX_C_MRX_N7

PCEI_GTX_C_MRX_P8
PCEI_GTX_C_MRX_N8

PCEI_GTX_C_MRX_P9
PCEI_GTX_C_MRX_N9

PCEI_GTX_C_MRX_P10
PCEI_GTX_C_MRX_N10

PCEI_GTX_C_MRX_P11
PCEI_GTX_C_MRX_N11

PCEI_GTX_C_MRX_P12
PCEI_GTX_C_MRX_N12

PCEI_GTX_C_MRX_P13
PCEI_GTX_C_MRX_N13

PCEI_GTX_C_MRX_P14
PCEI_GTX_C_MRX_N14

PCEI_GTX_C_MRX_P15
PCEI_GTX_C_MRX_N15

SDVO_SCLK
SDVO_SDAT
DVI_DET
DVI_SCLK
DVI_SDATA
DAC_BRIG
DISPOFF#
INVT_PWM
PLTRST_VGA#
SUSP#
ENBKL
LCD_ID

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

EFL50 LA-2761

Wednesday, April 20, 2005

VGA_TV_LUMA 21
VGA_TV_CRMA 21

VGA_TV_COMPS 21

SDVO_SCLK 8,41
SDVO_SDAT 8,41
DVI_DET 38,41
DVI_SCLK 38,41
DVI_SDATA 38,41

PLTRST_VGA# 18,41

SUSP# 33,35,40
ENBKL 33
LCD_ID 18

+1.5VS
+3VS

+1.8VS

VGA / LCD CONN.

1

15 51

0.2

of

5

4

3

2

1

RP14

+3VS

D D

+3VS

+3VS

+3VS

C C

+3VS

+3VS

1 8
2 7
3 6
4 5

8.2K_1206_8P4R_5%

RP11

1 8
2 7
3 6
4 5

8.2K_1206_8P4R_5%

RP15

1 8
2 7
3 6
4 5

8.2K_1206_8P4R_5%

RP12

1 8
2 7
3 6
4 5

8.2K_1206_8P4R_5%

RP13

1 8
2 7
3 6
4 5

8.2K_1206_8P4R_5%

RP23

1 8
2 7
3 6
4 5

8.2K_1206_8P4R_5%

PCI_SERR#
PCI_TRDY#
PCI_FRAME#
PCI_STOP#

PCI_PLOCK#
PCI_IRDY#
PCI_PERR#
PCI_DEVSEL#

PCI_PIRQD#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQA#

PCI_PIRQE#
PCI_PIRQF#
D_USB_SMI#2
PCI_PIRQG#

PCI_REQ#3
D_USB_SMI#1
PCI_REQ#4
PCI_REQ#1

PCI_GNT#6
PCI_REQ#0
PCI_REQ#2
PCI_PIRQH#

PCI_AD[0..31]22,24,25,27,28

PCI_FRAME#22,24,25,27,28

PCI_PIRQA#22
PCI_PIRQB#22

PCI_AD0
PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD6
PCI_AD7
PCI_AD8
PCI_AD9
PCI_AD10
PCI_AD11
PCI_AD12
PCI_AD13
PCI_AD14
PCI_AD15
PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20
PCI_AD21
PCI_AD22
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30
PCI_AD31

PCI_FRAME#

PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#

U13B

E2

AD[0]

E5

AD[1]

C2

AD[2]

F5

AD[3]

F3

AD[4]

E9

AD[5]

F2

AD[6]

D6

AD[7]

E6

AD[8]

D3

AD[9]

A2

AD[10]

D2

AD[11]

D5

AD[12]

H3

AD[13]

B4

AD[14]

J5

AD[15]

K2

AD[16]

K5

AD[17]

D4

AD[18]

L6

AD[19]

G3

AD[20]

H4

AD[21]

H2

AD[22]

H5

AD[23]

B3

AD[24]

M6

AD[25]

B2

AD[26]

K6

AD[27]

K3

AD[28]

A5

AD[29]

L1

AD[30]

K4

AD[31]

J3

FRAME#

Interrupt I/F

N2

PIRQ[A]#

L2

PIRQ[B]#

M1

PIRQ[C]#

L3

PIRQ[D]#

AC5

SATA[1]RXN/RSVD[1]

AD5

SATA[1]RXP/RSVD[2]

AF4

SATA[1]TXN/RSVD[3]

AG4

SATA[1]TXP/RSVD[4]

AC9

SATA[3]RXN/RSVD[5]

AD9

SATA[3]RXP/RSVD[6]

AF8

SATA[3]TXN/RSVD[7]

AG8

SATA[3]TXP/RSVD[8]

U3

TP[3]/RSVD[9]

ICH6_BGA609

PCI

REQ[4]#/GPI[40]

GNT[4]#/GPO[48]

REQ[5]#/GPI[1]

GNT[5]#/GPO[17]

REQ[6]#/GPI[0]

GNT[6]#/GPO[16]

PIRQ[E]#/GPI[2]
PIRQ[F]#/GPI[3]
PIRQ[G]#GPI[4]

PIRQ[H]#/GPI[5]

RESERVED

REQ[0]#
GNT[0]#
REQ[1]#
GNT[1]#
REQ[2]#
GNT[2]#
REQ[3]#
GNT[3]#

C/BE[0]#
C/BE[1]#
C/BE[2]#
C/BE[3]#

IRDY#

PAR

PCIRST#

DEVSEL#

PERR#

PLOCK#

SERR#
STOP#
TRDY#

PLTRST#

PCICLK

PME#

L5
C1
B5
B6
M5
F1
B8
C8
F7
E7
E8
F6
B7
D8

J6
H6
G4
G2

A3
E1
R2
C3
E3
C5
G5
J1
J2

R5
G6
P6

D9
C7
C6
M3

PCI_REQ#0
PCI_GNT#0
PCI_REQ#1
PCI_GNT#1
PCI_REQ#2
PCI_GNT#2
PCI_REQ#3
PCI_GNT#3
PCI_REQ#4

D_USB_SMI#1
PCI_GNT#5
D_USB_SMI#2
PCI_GNT#6

PCI_CBE#0
PCI_CBE#1
PCI_CBE#2
PCI_CBE#3

PCI_IRDY#
PCI_PAR
PCI_RST#
PCI_DEVSEL#
PCI_PERR#
PCI_PLOCK#
PCI_SERR#
PCI_STOP#
PCI_TRDY#

PLT_RST#
CLK_ICH_PCI

PCI_PIRQE#
PCI_PIRQF#
PCI_PIRQG#
PCI_PIRQH#

PCI_REQ#0 24
PCI_GNT#0 24
PCI_REQ#1 27,28
PCI_GNT#1 27,28
PCI_REQ#2 22
PCI_GNT#2 22
PCI_REQ#3 25
PCI_GNT#3 25

D_USB_SMI#1 38
D_USB_SMI#2 38

PCI_C/BE#0 22,24,25,27,28
PCI_C/BE#1 22,24,25,27,28
PCI_C/BE#2 22,24,25,27,28
PCI_C/BE#3 22,24,25,27,28

PCI_IRDY# 22,24,25,27,28
PCI_PAR 2 2 ,2 4,25,27,28
PCI_RST# 22,24, 25,27,28,32,33
PCI_DEVSEL# 22, 24 ,25,27,28
PCI_PERR # 22,24,25,27,28

PCI_SERR # 22,24,25,27,28
PCI_STOP# 22,24,25,27,28
PCI_T R D Y # 22,24,25,27,28

PLT_RST# 6,18,20,32,33,41
CLK_PCI_ICH 13

PCI_PIRQE# 24
PCI_PIRQF# 25
PCI_PIRQG# 27,28
PCI_PI R QH# 27,28

Internal Pull-up.
Sample hi g h de stina tion is LPC.

PCI_GNT#5

12

R154

0_0402_5%@

CLK_PCI_ICH

R157

10_0402_5%@

1 2
1

C173

10P_0402_50V8J@

2

B B

A A

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SE CRET INFO RMATI ON. THIS SHEET MAY NO T BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

ICH6(1/4)

EFL50 LA-2761

16 51Wednesday, April 20, 2005

1

0.2

of