Compal LA-2691 EAL30 Fortworth Alviso, Satellite M40X Schematic

A

B

C

D

E

Compal Confidential

Model Name : EAL30

Fan Control

File Name : LA-2691

1 1

LCD Conn.

page 20

CRT Conn.

TV-OUT Conn.

page 21

page 21

ATI M24/M22
Ver A23

with 32/64/128MB
On Board VRAM

page 13,14,15,16,17,18

page 4

16X PCI-E

Intel Dothan CPU

uFCPGA-478 CPU

H_A#(3..31) H_D#(0..63)

FSB

400 / 533 Mhz

page 4,5

Intel Alviso GM(PM)

PCBGA 1257

page 6,7,8,9

DMI

Thermal Sensor
ADI ADM1032AR

page 4

Memory BUS(DDR)

2.5V DDR200/266/333

Clock Generator

ICS954226

page 12

200pin DDR-SO-DIMM X2

BANK 0, 1, 2, 3

USB conn
x 2

Port 2,3

page 35

page 10,11

2 2

IDSEL:AD18
(PIRQ[G..H]#,
GNT#3/4,
REQ#3/4)

Mini PCI
socket

page 30

IDSEL:AD17
(PIRQB#,
GNT#1,
REQ#1)

LAN
RTL8100CL

page 26

RJ45/RJ11

page 26

3 3

RTC CKT.

page 24

Power On/Off CKT.

page 37

page 19

3.3V 33 MHz

IDSEL:AD20
(PIRQA#,B#,C#,D#,
GNT#2, REQ#2)

TI Controller

1394
Conn.

page 24

Touch Pad

Slot 0

page 26

PCI BUS

PCI7411

page 23,24

5in1 CardReader
Slot

ENE KB910
ENE KB910L

page 34,34

page 25

Int.KBD

Intel ICH6-M

LPC BUS

page 36

mBGA-609

page 22,23,24

3.3V 33MHz

SMsC LPC47N217

Super I/O

PARALLEL

page 33

USB 2.0

3.3V 48MHz

3.3V 24.57 6MHz

3.3V ATA-100

IDE

SATA

page 33

FIR

page 33

AC-LINK

CDROM
Conn.

page 25

SATA to PATA

88SA8040

page 25

HDD Conn.

USB conn
x 1

Port 4

page 35

AC97 Codec

ALC250 Ver.D

AMP
TPA0232

Audio Board
Conn

LS-2691

page 31

page 32

MDC Conn

page 32

page 31

EAL30 Sub Board

LED/SW Board
Conn
LS-2462

page 36

T/P Board
Conn
LS-2461

page 36

WL-KSW Board

LS-2692

DC/DC Int erface CKT.

4 4

page 38

1MB BIOS

page 35

Power Circuit DC/DC

page 38,39,40,41
42,43,44,45

A

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

B

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2005/03/01 2006/03/01

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

D

Date: Sheet

Compal Electro ni cs, Inc.

Block Diagram

星|, 03, 2005

薔三月

EAL30 LA-2691

E

1.0

of

152

A

1 1

B

C

D

E

Compal Confidential

2 2

Fortworth Alviso
EAL30 LA-2691 Schematic

uFC-PGA Dothan / 915 PM/GM/910GML

3 3

ATI M24/M24C/M22 Ver A23 with 64M/128M VRAM / ICH6-M

2005-03-01

REV:1.0

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITT EN CON SENT O F COMPAL ELECTRONICS, INC.

2005/03/01 2006/03/01

C

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

D

Date: Sheet

Compal Electronics, Inc.

Cover Sheet

, 04, 2005

五三月

EAL30 LA-2691

星期

E

1.0

of

152

A

Voltage Rails

Symbol note:

:means digital ground.

Power Plane

VIN
B+
+CPU_CORE
+1.05VS
+1.25VS
+VGA_CORE
+1.2VS
+1.5VALW
+1.5VS
+1.8VS
+2.5V
+3VALW
+3V
+3VS
+5VALW
+5VS
+12VALW
RTCVCC

Note : ON * m e a n s t h a t t hi s p ow e r pl a ne is ON only with AC power available, otherwise it is OFF.

1 1

ICH6-M I2C / SMB US ADDRESSING

DEVICE

DDR SO-DIMM 0
DDR SO-DIMM 1
CLOCK GENERATOR (EXT.)

Description

Adapter power supply (19V)
AC or battery power rail for power circuit
Core voltage for CPU

1.05V rail for Processor I/O

1.25V switched power ra il for DDR Vtt

1.2V/1.0V switched power rail for VGA core power

1.2V for VGA PCIE power ON O FF O FF

1.5V always on power rail

1.5V switched power rail

1.8V switched power rail for VGA frame buffer

2.5V power rail for system DDR

3.3V always on power rail

3.3V switched power rail

3.3V switched power rail
5V always on power rail
5V switched power rail
12V always on power rail
RTC power

HEX

A0
A2
D2

ADDRESS

1 0 1 0 0 0 0 X
1 0 1 0 0 0 1 X
1 1 0 1 0 0 1 X

S0-S1

N/A

ON OFF
ON
ON
ON

ON
ON
ON
ON
ON
ON
ON OFF
ON
ON
ON
ON

S5

S3

N/A

N/A
N/AN/A

N/A

OFF
OFF

OFF

OFF

OFF
OFF

OFF

ON*

ON

OFF

OFF
OFF

OFF
OFF

ON
ON ON*

OFF

ON
OFF

ON*ON

OFF

OFF
ON ON*
ON

ON*

:means analog ground.
:means reserved.@

Fortworth Alviso Comparison Table

Item

VGA
VRAM

*

Descrite PageUMA

ATi M22P/24P

128MB/64MB

UMA

N/A

Board ID Tabl e for AD channel

Vcc 3.3V +/- 5%

BID/PID

0
1
2
3
4
5 3.465 V3.135 V

10K +/- 5%Ra

Rb/Rc V min

0

8.2K +/- 5%

AD_BID

0 V

1.412 V 1.560 V
18K +/- 5%
33K +/- 5%
56K +/- 5%

NC 3.300 V

15 ~ 18

19 ~ 20

V typ

AD_BID

0 V 0.1 V

1.486 V

2.121 V

2.533 V

2.800 V

V

AD_BID

max

2.227 V2.015 V

2.659 V2.406 V

2.940 V2.660 V

KB910 I2C / SMBUS ADDRESSING

DEVICE

SM1 24C16
SM1 SMART BATTERY
SM2 ADM0132

CPU THERMAL MONITOR
SM2 ALC250 codec 00H 0 0 0 0 0 0 0 X b

HEX

A0H

98H

External PCI Devices

DEVICE

1394 AD20
LAN
CARD BUS

Mini-PCI

PCI Device ID

D0
D1
D4

D2

IDSEL #

AD17
AD20

AD18

ADDRESS

1 0 1 0 0 0 0 X b
0 0 0 1 0 1 1 X b16H
1 0 0 1 1 0 0 X b

REQ/GNT #

Board ID

0

*

1

PCB Revision

0.1

2
3
4
5

PIRQ

2
3
2
25IN1 D4 AD20
1

A,B,C,D
F
A,B,C,D
A,B,C,D
G,H

6
7

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITT EN CON SENT O F COMPAL ELECTRONICS, INC.

A

Compal Secret Data

Deciphered Date

2006/03/012005/03/01

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

Notes List
EAL30 LA-2691

星期

, 03, 2005

四三月

of

352

1.0

A

H_A#[3..31]6

4 4

H_REQ#[0..4]6

3 3

H_RS#[0..2]6

2 2

1 1

H_A#[3..31]

H_REQ#[0..4]

H_RS#[0..2]

H_ADSTB#06
H_ADSTB#16

CLK_CPU_BCLK14

CLK_CPU_BCLK#14

H_ADS#6
H_BNR#6

H_BPRI#6

H_BR0#6

H_DEFER#6

H_DRDY#6

H_HIT#6
H_HITM#6

H_LOCK#6

H_CPURST#6

H_TRDY#6

H_DBSY#6
H_DPSLP#24
H_DPRSTP#24
H_DPWR#6

H_PWRGOOD24

H_CPUSLP#6,24

H_THERMTRIP#6,24

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

H_IERR#
H_CPURST#

H_RS#0
H_RS#1
H_RS#2

ITP_DBRRESET#

PRO_CHOT#
H_PWRGOOD

H_CPUSLP#
ITP_TCK
ITP_TDI
ITP_TDO
TEST1
TEST2
ITP_TMS
ITP_TRST#

THERMDA
THERMDC

P4
U4
V3
R3
V2

W1

T4

W2

Y4
Y1
U1

AA3

Y3
AA2
AF4
AC4
AC7
AC3
AD3
AE4
AD2
AB4
AC6
AD5
AE2
AD6
AF3
AE1
AF1

R2

P3

T2

P1

T1

U3
AE5

A16
A15

B15
B14

N2

L1

J3

N4

L4

H2

K3

K4

A4

J2
B11

H1

K1

L2

M3

C8

B8

A9

C9

A7

M2

B7

G1
C19
A10
B10
B17

E4

A6
A13
C12
A12

C5
F23
C11
B13

B18
A18
C17

THERMDA & THERMDC Trace / Space = 10 / 10 mil

B

U7A

A3#
A4#
A5#
A6#
A7#
A8#
A9#
A10#
A11#
A12#
A13#
A14#
A15#
A16#
A17#
A18#
A19#
A20#
A21#
A22#
A23#
A24#
A25#
A26#
A27#
A28#
A29#
A30#
A31#

REQ0#
REQ1#
REQ2#
REQ3#
REQ4#

ADSTB0#
ADSTB1#

ITP_CLK0
ITP_CLK1

BCLK0
BCLK1

ADS#
BNR#
BPRI#
BR0#
DEFER#
DRDY#
HIT#
HITM#
IERR#
LOCK#
RESET#

RS0#
RS1#
RS2#
TRDY#

BPM0#
BPM1#
BPM2#
BPM3#

DBR#
DBSY#
DPSLP#
DPRSTP#
DPWR#
PRDY#
PREQ#
PROCHOT#

PWRGOOD
SLP#
TCK
TDI
TDO
TEST1
TEST2
TMS
TRST#

THERMDA
THERMDC
THERMTRIP#

TYCO_1612365-1_Dothan

Dothan

ADDR GROUP

HOST CLK

CONTROL GROUP

MISC

THERMAL
DIODE

DATA GROUP

LEGACY CPU

D10#
D11#
D12#
D13#
D14#
D15#
D16#
D17#
D18#
D19#
D20#
D21#
D22#
D23#
D24#
D25#
D26#
D27#
D28#
D29#
D30#
D31#
D32#
D33#
D34#
D35#
D36#
D37#
D38#
D39#
D40#
D41#
D42#
D43#
D44#
D45#
D46#
D47#
D48#
D49#
D50#
D51#
D52#
D53#
D54#
D55#
D56#
D57#
D58#
D59#
D60#
D61#
D62#
D63#

DINV0#
DINV1#
DINV2#
DINV3#

DSTBN0#
DSTBN1#
DSTBN2#
DSTBN3#
DSTBP0#
DSTBP1#
DSTBP2#
DSTBP3#

A20M#
FERR#

IGNNE#

INIT#
LINT0
LINT1

STPCLK#

SMI#

C

H_D#[0..63]

H_D#0

A19

D0#
D1#
D2#
D3#
D4#
D5#
D6#
D7#
D8#
D9#

A25
A22
B21
A24
B26
A21
B20
C20
B24
D24
E24
C26
B23
E23
C25
H23
G25
L23
M26
H24
F25
G24
J23
M23
J25
L26
N24
M25
H26
N25
K25
Y26
AA24
T25
U23
V23
R24
R26
R23
AA23
U26
V24
U25
V26
Y23
AA26
Y25
AB25
AC23
AB24
AC20
AC22
AC25
AD23
AE22
AF23
AD24
AF20
AE21
AD21
AF25
AF22
AF26

D25
J26
T24
AD20

C23
K24
W25
AE24
C22
L24
W24
AE25

C2
D3
A3
B5
D1
D4

C6
B4

H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63

H_DINV#0 6
H_DINV#1 6
H_DINV#2 6
H_DINV#3 6

H_DSTBN#0 6
H_DSTBN#1 6
H_DSTBN#2 6
H_DSTBN#3 6
H_DSTBP#0 6
H_DSTBP#1 6
H_DSTBP#2 6
H_DSTBP#3 6

H_A20M# 24
H_FERR# 24
H_IGNNE# 24
H_INIT# 24
H_INTR 24
H_NMI 24

H_STPCLK# 24
H_SMI# 24

EN_DFAN139

H_D#[0..63] 6

1 2

R45
10K_0402_5%

D

ITP_TDI
ITP_TDO
H_CPURST#
ITP_TMS
PRO_CHOT#
H_PWRGOOD
H_IERR#

ITP_DBRRESET#
ITP_TRST#

ITP_TCK
TEST1
TEST2

R426 150_0402_5%
R423 54.9_0402_1%@
R424 54.9_0402_1%@
R427 40.2_0402_1%
R23 56_0402_5%
R422 200_0402_5%
R418 56_0402_5%

R415 150_0402_5%@
R22 680_0402_5%
R21 27.4_0402_1%
R421 1K_0402_5%@
R414 1K_0402_5%@

12
12
12
12
12
12
12

12
12
12
12
12

Reserve For Testability

H_FERR#
H_CPUSLP#
H_DPSLP#
H_STPCLK#
H_INIT#
H_SMI#
H_IGNNE#
H_NMI

Thermal Sensor ADI ADM1032AR

+3VS

2

12

C457

R18

@

1

1

C20

2

2200P_0402_25V7K

10K_0402_5%

0.1U_0402_16V4Z

W=15mil

THERMDA
THERMDC

C44 100P_0402_50V8J@

1 2

C32 100P_0402_50V8J@

1 2

C46 100P_0402_50V8J@

1 2

C41 100P_0402_50V8J@

1 2

C34 100P_0402_50V8J@

1 2

C33 100P_0402_50V8J@

1 2

C29 100P_0402_50V8J@

1 2

C49 100P_0402_50V8J@

1 2

U31

1

VDD

2

D+

3

D­THERM#4GND

ADM1032AR_SOP8

Address:1001_100X

SCLK

SDATA

ALERT#

Fan Control circuit

PU5B

LM358A_SO8

5

+

FAN1_ON

7

0

6

-

P@

1 2

R46 8.2K_0402_5%

1 2

R47 100_0402_5%

C64

0.1U_0402_16V4Z

FANSPEED139

+3VS

2

B

1

2

+1.05VS

+3VS

8
7
6
5

+5VS

1

C

Q3
FMMT619_SOT23

E

3
12

D8
1N4148_SOD80

1 2

R362 10K_0402_5%

1

@

C444
1000P_0402_50V7K

2

E

12

D7
1SS355_SOD323

FAN1_VOUT

1

@

2

EC_SMC_2 36,39
EC_SMD_2 36,39

1

C43
10U_0805_10V4Z

2

JP7

1
2
3

ACES_85205-0300

C448
1000P_0402_50V7K

Close to Fan Conn.

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

Compal Secret Data

Deciphered Date

2006/03/012005/03/01

D

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

INTEL Dothan(1/2)
EAL30 LA-2691

星期四 三月

, 03, 2005

E

452

1.0

of

A

U7B

AE7

VCCSENSE

AF6

VSSSENSE

F26

VCCA0

B1

VCCA1

N1

VCCA2

AC26

VCCA3

P23

VCCQ0

W4

VCCQ1

D10

VCCP

D12

VCCP

D14

VCCP

D16

VCCP

E11

VCCP

E13

VCCP

E15

VCCP

F10

VCCP

F12

VCCP

F14

VCCP

F16

VCCP

K6

VCCP

L5

VCCP

L21

VCCP

M6

VCCP

M22

VCCP

N5

VCCP

N21

VCCP

P6

VCCP

P22

VCCP

R5

VCCP

R21

VCCP

T6

VCCP

T22

VCCP

U21

VCCP

D6

VCC

D8

VCC

D18

VCC

D20

VCC

D22

VCC

E5

VCC

E7

VCC

E9

VCC

E17

VCC

E19

VCC

E21

VCC

F6

VCC

F8

VCC

F18

VCC

E1

PSI#

E2

VID0

F2

VID1

F3

VID2

G3

VID3

G4

VID4

H4

VID5

AD26

GTLREF

C16

BSEL0

C14

BSEL1

P25

COMP0

P26

COMP1

AB2

COMP2

AB1

COMP3

B2

RSVD

C3

RSVD

E26

RSVD

AF7

RSVD

AC1

RSVD

TYCO_1612365-1_Dothan

COMP0
COMP1
COMP2
COMP3

+1.05VS

VCCSENSE
VSSSENSE

R83 54.9_0402_1%@

1 2

R82 54.9_0402_1%@

1 2

+VCCA

1 1

1.8V FOR DOTHAN-A

1 2

+1.8VS

R301 0_1206_5%@

1.5V FOR DOTHAN-B

1 2

+1.5VS

R302 0_1206_5%

1

1

C30

0.01U_0402_16V7K

2 2

+1.05VS

12

R62
1K_0402_1%

1 2

R59 2K_0402_1%

3 3

R44 27.4_0402_1%
R42 54.9_0402_1%
R81 27.4_0402_1%

4 4

R80 54.9_0402_1%

2

10U_0805_6.3V6M

+CPU_CORE

PSI#50
CPU_VID050

CPU_VID150
CPU_VID250
CPU_VID350
CPU_VID450
CPU_VID550

CPU_BSEL014
CPU_BSEL114

1 2
1 2
1 2
1 2

C24

2

GTL_REF0

COMP0
COMP1
COMP2
COMP3

B

A2

VSS

A5

VSS

A8

VSS

A11

VSS

A14

VSS

A17

VSS

A20

VSS

A23

VSS

A26

VSS

B3

VSS

B6

VSS

B9

VSS

B12

Dothan

VSS

B16

VSS

B19

VSS

B22

VSS

B25

VSS

C1

VSS

C4

VSS

C7

VSS

C10

VSS

C13

VSS

C15

VSS

C18

VSS

C21

VSS

C24

VSS

D2

VSS

D5

VSS

D7

VSS

D9

VSS

D11

VSS

D13

VSS

D15

VSS

D17

VSS

D19

VSS

D21

VSS

D23

VSS

D26

VSS

E3

VSS

E6

VSS

E8

VSS

E10

VSS

E12

VSS

E14

VSS

E16

VSS

E18

VSS

E20

VSS

E22

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

E25
F1
F4
F5
F7
F9
F11
F13
F15
F17
F19
F21
F24
G2
G6
G22
G23
G26
H3
H5
H21
H25
J1
J4
J6
J22
J24
K2
K5
K21
K23
K26
L3
L6
L22
L25
M1

POWER, GROUNG, RESERVED SIGNALS AND NC

+1.05VS

1

+

2

150U_D2_6.3VM

0.1U_0402_16V4Z

1

C104

2

330U_D_2VM

+CPU_CORE

10U_0805_6.3V6M

1

C35

2

10U_0805_6.3V6M

+CPU_CORE

10U_0805_6.3V6M

1

C65

C52

2

10U_0805_6.3V6M

+CPU_CORE

10U_0805_6.3V6M

1

C74

C73

2

10U_0805_6.3V6M

+CPU_CORE

10U_0805_6.3V6M

1

C540

C541

2

10U_0805_6.3V6M

+CPU_CORE

10U_0805_6.3V6M

1

C585

C569

2

10U_0805_6.3V6M

Vcc-core
Decoupling
SPCAP,Polymer

MLCC 0805 X5R

0.1U_0402_16V4Z

1

C520

C519

2

0.1U_0402_16V4Z

C

+CPU_CORE

330U_D_2VM

1

1

+

C475

2

1

1

C36

C37

2

2

10U_0805_6.3V6M

10U_0805_6.3V6M

1

1

C48

2

2

10U_0805_6.3V6M

10U_0805_6.3V6M

1

1

C75

2

2

10U_0805_6.3V6M

10U_0805_6.3V6M

1

1

C539

2

2

10U_0805_6.3V6M

10U_0805_6.3V6M

1

1

C612

2

2

10U_0805_6.3V6M

C,uF ESL,nH

1

+

C474

@

2

2

330U_D_2VM

10U_0805_6.3V6M

1

C38

C39

2

10U_0805_6.3V6M

1

C53

C66

2

10U_0805_6.3V6M

1

C76

C544

2

10U_0805_6.3V6M

1

C564

C570

2

10U_0805_6.3V6M

1

C611

C610

2

10U_0805_6.3V6M

ESR, mohm

+

C473

10U_0805_6.3V6M

1

2

10U_0805_6.3V6M

1

2

10U_0805_6.3V6M

1

2

10U_0805_6.3V6M

1

2

10U_0805_6.3V6M

1

2

C40

C71

C543

C586

C609

1

2

1

2

1

2

1

2

1

2

3X330uF 9m ohm/3 3.5nH/4

1

2

35X10uF

1

C518

2

0.1U_0402_16V4Z

5m ohm/35 0.6nH/35

0.1U_0402_16V4Z

1

C517

2

1

C554

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

C575

1

2

1

C47

2

10U_0805_6.3V6M

1

C72

2

10U_0805_6.3V6M

1

C542

2

10U_0805_6.3V6M

1

C563

2

10U_0805_6.3V6M

1

C608

2

10U_0805_6.3V6M

0.1U_0402_16V4Z

1

C591

C560

2

0.1U_0402_16V4Z

1

C584

2

D

+CPU_CORE

1

C602

2

0.1U_0402_16V4Z

U7C

F20

VCC

F22

VCC

G5

VCC

G21

VCC

H6

VCC

H22

VCC

J5

VCC

J21

VCC

K22

VCC

U5

VCC

V6

VCC

V22

VCC

W5

VCC

W21

VCC

Y6

VCC

Y22

VCC

AA5

VCC

AA7

VCC

AA9

VCC

AA11

VCC

AA13

VCC

AA15

VCC

AA17

VCC

AA19

VCC

AA21

VCC

AB6

VCC

AB8

VCC

AB10

VCC

AB12

VCC

AB14

VCC

AB16

VCC

AB18

VCC

AB20

VCC

AB22

VCC

AC9

VCC

AC11

VCC

AC13

VCC

AC15

VCC

AC17

VCC

AC19

VCC

AD8

VCC

AD10

VCC

AD12

VCC

AD14

VCC

AD16

VCC

AD18

VCC

AE9

VCC

AE11

VCC

AE13

VCC

AE15

VCC

AE17

VCC

AE19

VCC

AF8

VCC

AF10

VCC

AF12

VCC

AF14

VCC

AF16

VCC

AF18

VCC

M4

VSS

M5

VSS

M21

VSS

M24

VSS

N3

VSS

N6

VSS

N22

VSS

N23

VSS

N26

VSS

P2

VSS

P5

VSS

P21

VSS

P24

VSS

R1

VSS

R4

VSS

R6

VSS

R22

VSS

R25

VSS

T3

VSS

T5

VSS

T21

VSS

T23

VSS

TYCO_1612365-1_Dothan

Dothan

POWER, GROUND

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

E

T26
U2
U6
U22
U24
V1
V4
V5
V21
V25
W3
W6
W22
W23
W26
Y2
Y5
Y21
Y24
AA1
AA4
AA6
AA8
AA10
AA12
AA14
AA16
AA18
AA20
AA22
AA25
AB3
AB5
AB7
AB9
AB11
AB13
AB15
AB17
AB19
AB21
AB23
AB26
AC2
AC5
AC8
AC10
AC12
AC14
AC16
AC18
AC21
AC24
AD1
AD4
AD7
AD9
AD11
AD13
AD15
AD17
AD19
AD22
AD25
AE3
AE6
AE8
AE10
AE12
AE14
AE16
AE18
AE20
AE23
AE26
AF2
AF5
AF9
AF11
AF13
AF15
AF17
AF19
AF21
AF24

TRACE CLOSELY CPU < 0.5'

COMP0, COMP2 layout : Width 18mils and Space 25mils
COMP1, COMP3 layout : Space 25mils

A

B

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITT EN CON SENT O F COMPAL ELECTRONICS, INC.

C

Compal Secret Data

Deciphered Date

2005/03/012006/03/01

D

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

INTEL Dothan(2/2)
EAL30 LA-2691

星期

, 03, 2005

四三月

E

of

552

1.0

5

4

3

2

1

H_RS#[0..2]

H_A#[3..31]4
H_REQ#[0..4]4

D D

C C

CLK_MCH_BCLK#14
CLK_MCH_BCLK14

B B

(5mil:15mil) (12mil:10mil)

A A

H_VREF

1

C148

0.1U_0402_16V4Z

2

H_A#[3..31]

H_REQ#[0..4]

H_ADSTB#04
H_ADSTB#14

H_DSTBN#04
H_DSTBN#14
H_DSTBN#24
H_DSTBN#34
H_DSTBP#04
H_DSTBP#14
H_DSTBP#24
H_DSTBP#34
H_DINV#04
H_DINV#14
H_DINV#24
H_DINV#34

H_CPURST#4

H_ADS#4
H_TRDY#4

H_DPWR#4

H_DRDY#4
H_DEFER#4

H_HITM#4
H_HIT#4
H_LOCK#4
H_BR0#4
H_BNR#4
H_BPRI#4
H_DBSY#4

H_CPUSLP#4,24

12

R108
100_0603_1%

12

R111
200_0603_1%

5

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

H_RS#0
H_RS#1
H_RS#2

H_RS#[0..2] 4

U44A

G9

HA3#

Alviso

C9

HA4#

E9

HA5#

B7

HA6#

A10

HA7#

F9

HA8#

D8

HA9#

B10

HA10#

E10

HA11#

G10

HA12#

D9

HA13#

E11

HA14#

F10

HA15#

G11

HA16#

G13

HA17#

C10

HA18#

C11

HA19#

D11

HA20#

C12

HA21#

B13

HA22#

A12

HA23#

F12

HA24#

G12

HA25#

E12

HA26#

C13

HA27#

B11

HA28#

D13

HA29#

A13

HA30#

F13

HA31#

A11

HPCREQ#

A7

HREQ#0

D7

HREQ#1

B8

HREQ#2

C7

HREQ#3

A8

HREQ#4

B9

HADSTB#0

E13

HADSTB#1

AB1

HCLKN

AB2

HCLKP

G4

HDSTBN#0

K1

HDSTBN#1

R3

HDSTBN#2

V3

HDSTBN#3

G5

HDSTBP#0

K2

HDSTBP#1

R2

HDSTBP#2

W4

HDSTBP#3

H8

HDINV#0

K3

HDINV#1

T7

HDINV#2

U5

HDINV#3

H10

HCPURST#

F8

HADS#

B5

HTRDY#

G6

HDPWR#

F7

HDRDY#

E6

HDEFER#

F6

HEDRDY#

D6

HHITM#

D4

HHIT#

B3

HLOCK#

E7

HBREQ0#

A5

HBNR#

D5

HBPRI#

C6

HDBSY#

G8

HCPUSLP#

A4

HRS0#

C5

HRS1#

B4

HRS2#

82915PM-C0

HOST

ALVISO_BGA1257915PM@

(R3:SA009150180)
(R1:SA009150160)

H_XSWING

1

C686

0.1U_0402_16V4Z

2

HD0#
HD1#
HD2#
HD3#
HD4#
HD5#
HD6#
HD7#
HD8#

HD9#
HD10#
HD11#
HD12#
HD13#
HD14#
HD15#
HD16#
HD17#
HD18#
HD19#
HD20#
HD21#
HD22#
HD23#
HD24#
HD25#
HD26#
HD27#
HD28#
HD29#
HD30#
HD31#
HD32#
HD33#
HD34#
HD35#
HD36#
HD37#
HD38#
HD39#
HD40#
HD41#
HD42#
HD43#
HD44#
HD45#
HD46#
HD47#
HD48#
HD49#
HD50#
HD51#
HD52#
HD53#
HD54#
HD55#
HD56#
HD57#
HD58#
HD59#
HD60#
HD61#
HD62#
HD63#

HVREF
HXRCOMP
HXSCOMP
HYRCOMP
HYSCOMP

HXSWING
HYSWING

E4
E1
F4
H7
E2
F1
E3
D3
K7
F2
J7
J8
H6
F3
K8
H5
H1
H2
K5
K6
J4
G3
H3
J1
L5
K4
J5
P7
L7
J3
P5
L3
U7
V6
R6
R5
P3
T8
R7
R8
U8
R4
T4
T5
R1
T3
V8
U6
W6
U3
V5
W8
W7
U2
U1
Y5
Y2
V4
Y7
W1
W3
Y3
Y6
W2

J11
C1
C2
T1
L1
D1
P1

H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63

H_VREF
H_XRCOMP

R473 24.9_0402_1%

H_XSCOMP

R474 54.9_0402_1%

H_YRCOMP

R480 24.9_0402_1%

H_YSCOMP

R484 54.9_0402_1%

H_XSWING
H_YSWING

H_D#[0..63]

1 2
1 2

12
12

H_D#[0..63] 4

+2.5V

+1.05VS

H_XRCOMP & H_YRCOMP Trace / Space = 10 / 20 mil

+1.05VS +1.05VS+1.05VS

12

R470
221_0603_1%

12

R462
100_0603_1%

4

H_YSWING

1

C694

0.1U_0402_16V4Z

2

12

R467
221_0603_1%

(12mil:10mil)

12

R483
100_0603_1%

CLK_DREF_SSC

2

G16
H13
G14
F16
F15
G15
E16
D17
J16
D15
E15
D14
E14
H12
C14
H15
J15
H14
G22
G23
D23
G25
G24
J17
A31
A30
D26
D25

J23
J21
H22
F5
AD30
AE29

A24
A23
D37
C37

AP37
AN37
AP36
AP2
AP1
AN1
B1
A2
B37
A36
A37

2006/03/012005/03/01

CLK_DREF_SSC#

EXT_TS#0
EXT_TS#1

H_THERMTRIP#

CLK_DREF_96M#
CLK_DREF_96M
CLK_DREF_SSC
CLK_DREF_SSC#

DMI_ITX_MRX_N025
DMI_ITX_MRX_N125
DMI_ITX_MRX_N225
DMI_ITX_MRX_N325

DMI_ITX_MRX_P025
DMI_ITX_MRX_P125
DMI_ITX_MRX_P225
DMI_ITX_MRX_P325

DMI_MTX_IRX_N025
DMI_MTX_IRX_N125
DMI_MTX_IRX_N225
DMI_MTX_IRX_N325

DMI_MTX_IRX_P025
DMI_MTX_IRX_P125
DMI_MTX_IRX_P225
DMI_MTX_IRX_P325

DDRA_CLK111
DDRA_CLK211

DDRB_CLK112
DDRB_CLK212

DDRA_CLK1#11
DDRA_CLK2#11

DDRB_CLK1#12
DDRB_CLK2#12

DDRA_CKE011
DDRA_CKE111
DDRB_CKE012
DDRB_CKE112

DDRA_SCS#011
DDRA_SCS#111
DDRB_SCS#012
DDRB_SCS#112

R135 40.2_0402_1%@

1 2

R120 40.2_0402_1%@

1 2

DMI_ITX_MRX_N0
DMI_ITX_MRX_N1
DMI_ITX_MRX_N2
DMI_ITX_MRX_N3

DMI_ITX_MRX_P0
DMI_ITX_MRX_P1
DMI_ITX_MRX_P2
DMI_ITX_MRX_P3

DMI_MTX_IRX_N0
DMI_MTX_IRX_N1
DMI_MTX_IRX_N2
DMI_MTX_IRX_N3

DMI_MTX_IRX_P0
DMI_MTX_IRX_P1
DMI_MTX_IRX_P2
DMI_MTX_IRX_P3

DDRA_CKE0
DDRA_CKE1
DDRB_CKE0
DDRB_CKE1

DDRA_SCS#0
DDRA_SCS#1
DDRB_SCS#0
DDRB_SCS#1

M_OCDCOMP0
M_OCDCOMP1

Intel new update

R106 80.6_0402_1%

1 2

R105 80.6_0402_1%

1 2

M_RCOMPN
M_RCOMPP
SMVREF

M_XSLEW
M_YSELW

(10mil:20mil)

+2.5V

12

R466

1K_0402_1%

12

R475

1K_0402_1%

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITT EN CON SENT O F COMPAL ELECTRONICS, INC.

3

U44B

AA31

DMIRXN0

AB35

DMIRXN1

AC31

DMIRXN2

AD35

DMIRXN3

Y31

DMIRXP0

AA35

DMIRXP1

AB31

DMIRXP2

AC35

DMIRXP3

AA33

DMITXN0

AB37

DMITXN1

AC33

DMITXN2

AD37

DMITXN3

Y33

DMITXP0

AA37

DMITXP1

AB33

DMITXP2

AC37

DMITXP3

AM33

SM_CK0

AL1

SM_CK1

AE11

SM_CK2

AJ34

SM_CK3

AF6

SM_CK4

AC10

SM_CK5

AN33

SM_CK0#

AK1

SM_CK1#

AE10

SM_CK2#

AJ33

SM_CK3#

AF5

SM_CK4#

AD10

SM_CK5#

AP21

SM_CKE0

AM21

SM_CKE1

AH21

SM_CKE2

AK21

SM_CKE3

AN16

SM_CS0#

AM14

SM_CS1#

AH15

SM_CS2#

AG16

SM_CS3#

AF22

SM_OCDCOMP0

AF16

SM_OCDCOMP1

AP14

SM_ODT0

AL15

SM_ODT1

AM11

SM_ODT2

AN10

SM_ODT3

AK10

SMRCOMPN

AK11

SMRCOMPP

AF37

SMVREF0

AD1

SMVREF1

AE27

SMXSLEWIN

AE28

SMXSLEWOUT

AF9

SMYSLEWIN

AF10

SMYSLEWOUT

ALVISO_BGA1257915PM@

0.1U_0402_16V4Z

1

C236

2

Compal Secret Data

DMIDDR MUXING

SMVREF

1

C691

0.1U_0402_16V4Z

2

Deciphered Date

CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8

CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG16
CFG17
CFG18
CFG19
CFG20

RSVD21
RSVD22

CFG/RSVD

RSVD23
RSVD24
RSVD25
RSVD26
RSVD27

BM_BUSY#

EXT_TS0#
EXT_TS1#

THRMTRIP#

PWROK

RSTIN#

PM

DREF_CLKN

DREF_CLKP

DREF_SSCLKP

CLK

DREF_SSCLKN

NC1
NC2
NC3
NC4
NC5
NC6
NC7
NC8
NC9

NC10

NC

NC11

CFG0
MCH_CLKSEL1
MCH_CLKSEL0

CFG5
CFG6
CFG7

CFG9

CFG12
CFG13

CFG16
CFG18

CFG19

CFG[2:0]
CFG5
CFG6
CFG7

CFG9

CFG[13:12]

CFG16
(FSB Dynamic
ODT)

CFG18
(VCC Select)

CFG19
(VTT Select)

R158 0_0402_5%PM@

1 2

R157 0_0402_5%PM@

1 2

MCH_CLKSEL1 14
MCH_CLKSEL0 14

CFG0

R121 10K_0402_5%

1 2

CFG5

R115 1K_0402_5%@

1 2

CFG6

R117 1K_0402_5%@

CFG7
CFG9
CFG12
CFG13
CFG16

1 2

R122 1K_0402_5%@

1 2

R113 1K_0402_5%@

1 2

R114 1K_0402_5%@

1 2

R107 1K_0402_5%@

1 2

R116 1K_0402_5%@

1 2

CFG[17:3]: internal pull-up

CFG18

R140 1K_0402_5%@

CFG19

1 2

R137 1K_0402_5%@

1 2

CFG[19:18]: internal pull-down

PM_BMBUSY# 25

H_THERMTRIP# 4,24
VGATE 14,25,50
PLT_RST# 15,23,25,27,28,31,35,39

CLK_DREF_96M# 14
CLK_DREF_96M 14
CLK_DREF_SSC 14
CLK_DREF_SSC# 14

EXT_TS#0

R134 10K_0402_5%

EXT_TS#1

Title

Size Document Number Rev

Date: Sheet

1 2

R139 10K_0402_5%

1 2

Refer to sheet 6 for FSB
frequency select
Low = DMI x 2

High = DMI x 4
Low = DDR-II

High = DDR-I
Low = DT/Transportable CPU

High = Mobile CPU
Low = Reverse Lane

High = Normal Operation
00 = Reserved

01 = XOR Mode Enabled
10 = All Z Mode Enabled
11 = Normal Operation (Default)

Low = Disabled
High = Enabled

Low = 1.05V (Default)
High = 1.5V

Low = 1.05V (Default)
High = 1.2V

Compal Electronics, Inc.

INTEL Alviso HOST(1/5)
EAL30 LA-2691

星期

, 03, 2005

四三月

+1.5VS

+1.05VS

+2.5VS

+2.5VS

*
*

*

*

*

*

*

*

1.0

of

652

1

5

4

3

2

1

PCIE_MTX_C_GRX_N[0..15]15

PCIE_MTX_C_GRX_P[0..15]15
PCIE_GTX_C_MRX_N[0..15]15
PCIE_GTX_C_MRX_P[0..15]15

R142 3K_0402_1%@

D D

GMCH_TV_LUMA22
GMCH_TV_CRMA22

GMCH_CRT_CLK22
GMCH_CRT_DATA22
GMCH_CRT_B22

GMCH_CRT_G22
GMCH_CRT_R22

GMCH_CRT_VSYNC22
GMCH_CRT_HSYNC22

C C

+2.5VS

R130 4.7K_0402_5%

1 2

R126 4.7K_0402_5%

1 2

R133 2.2K_0402_5%GM@

1 2

R141 2.2K_0402_5%GM@

1 2

Intel Recommand

R146 100K_0402_5%

1 2

R152 1.5K_0402_1%

1 2

R529 75_0402_1%

1 2

R531 150_0402_1%

1 2

R532 150_0402_1%

1 2

B B

+2.5VS

+3VS

GMCH_TV_LUMA
GMCH_TV_CRMA

GMCH_CRT_CLK
GMCH_CRT_DATA
LCTLB_DATA
LCTLA_CLK

LBKLT_EN
LIBG
GMCH_TV_COMPS
GMCH_TV_LUMA
GMCH_TV_CRMA

GMCH_CRT_CLK
GMCH_CRT_DATA

+2.5VS

CLK_MCH_3GPLL#14
CLK_MCH_3GPLL14

GMCH_TV_COMPS

R125 4.99K_0402_1%

12

R124 150_0402_1%
R127 150_0402_1%
R119 150_0402_1%

12
12
12

GMCH_ENVDD21

GMCH_TXCLK-21
GMCH_TXCLK+21
GMCH_TZCLK-21
GMCH_TZCLK+21

GMCH_TXOUT0-21
GMCH_TXOUT1-21
GMCH_TXOUT2-21

GMCH_TXOUT0+21
GMCH_TXOUT1+21
GMCH_TXOUT2+21

GMCH_TZOUT0-21
GMCH_TZOUT1-21
GMCH_TZOUT2-21

GMCH_TZOUT0+21
GMCH_TZOUT1+21
GMCH_TZOUT2+21

1 2

R143 3K_0402_1%@

1 2

R527 0_0402_5%

12

1 2

R131 255_0402_1%

LBKLT_EN
LCTLA_CLK
LCTLB_DATA
LDDC_CLK
LDDC_DATA
GMCH_ENVDD
LIBG

GMCH_TXCLK­GMCH_TXCLK+
GMCH_TZCLK­GMCH_TZCLK+

GMCH_TXOUT0­GMCH_TXOUT1­GMCH_TXOUT2-

GMCH_TXOUT0+
GMCH_TXOUT1+
GMCH_TXOUT2+

GMCH_TZOUT0­GMCH_TZOUT1­GMCH_TZOUT2-

GMCH_TZOUT0+
GMCH_TZOUT1+
GMCH_TZOUT2+

TV_REFSET

REFSET

H24

H25
AB29
AC29

A15

C16

A17

B15

B16

B17

E24

E23

E21

D21

C20

B20

A19

B19

H21

G21

E25

F25

C23

C22

F23

F22

F26

C33

C31

F28

F27

B30

B29

C25

C24

B34

B33

B32

A34

A33

B31

C29

D28

C27

C28

D27

C26

J18

J20

U44G

SDVOCTRL_DATA
SDVOCTRL_CLK
GCLKN
GCLKP

TVDAC_A
TVDAC_B
TVDAC_C
TV_REFSET
TV_IRTNA
TV_IRTNB
TV_IRTNC

DDCCLK
DDCDATA
BLUE
BLUE#
GREEN
GREEN#
RED
RED#
VSYNC
HSYNC
REFSET

LBKLT_CTL
LBKLT_EN
LCTLA_CLK
LCTLB_DATA
LDDC_CLK
LDDC_DATA
LVDD_EN
LIBG
LVBG
LVREFH
LVREFL

LACLKN
LACLKP
LBCLKN
LBCLKP

LADATAN0
LADATAN1
LADATAN2

LADATAP0
LADATAP1
LADATAP2

LBDATAN0
LBDATAN1
LBDATAN2

LBDATAP0
LBDATAP1
LBDATAP2

ALVISO_BGA1257915PM@

EXP_RXN0/SDVO_TVCLKIN#

MISCTVVGALVDS

EXP_RXN1/SDVO_INT#

EXP_RXN2/SDVO_FLDSTALL#

EXP_RXP0/SDVO_TVCLKIN

EXP_RXP1/SDVO_INT

EXP_RXP2/SDVO_FLDSTALL

EXP_TXN0/SDVOB_RED#

EXP_TXN1/SDVOB_GREEN#

EXP_TXN2/SDVOB_BLUE#

EXP_TXN3/SDVOB_CLKN
EXP_TXN4/SDVOC_RED#

EXP_TXN5/SDVOC_GREEN#

EXP_TXN6/SDVOC_BLUE#

EXP_TXN7/SDVOC_CLKN

PCI - EXPRESS GRAPHICS

EXP_TXP0/SDVOB_RED

EXP_TXP1/SDVOB_GREEN

EXP_TXP2/SDVOB_BLUE
EXP_TXP3/SDVOB_CLKP

EXP_TXP4/SDVOC_RED

EXP_TXP5/SDVOC_GREEN

EXP_TXP6/SDVOC_BLUE
EXP_TXP7/SDVOC_CLKP

EXP_COMPI

EXP_ICOMPO

EXP_RXN3
EXP_RXN4
EXP_RXN5
EXP_RXN6
EXP_RXN7
EXP_RXN8

EXP_RXN9
EXP_RXN10
EXP_RXN11
EXP_RXN12
EXP_RXN13
EXP_RXN14
EXP_RXN15

EXP_RXP3

EXP_RXP4

EXP_RXP5

EXP_RXP6

EXP_RXP7

EXP_RXP8

EXP_RXP9
EXP_RXP10
EXP_RXP11
EXP_RXP12
EXP_RXP13
EXP_RXP14
EXP_RXP15

EXP_TXN8

EXP_TXN9
EXP_TXN10
EXP_TXN11
EXP_TXN12
EXP_TXN13
EXP_TXN14
EXP_TXN15

EXP_TXP8

EXP_TXP9
EXP_TXP10
EXP_TXP11
EXP_TXP12
EXP_TXP13
EXP_TXP14
EXP_TXP15

D36
D34

PCIE_GTX_C_MRX_N0

E30

PCIE_GTX_C_MRX_N1

F34

PCIE_GTX_C_MRX_N2

G30

PCIE_GTX_C_MRX_N3

H34

PCIE_GTX_C_MRX_N4

J30

PCIE_GTX_C_MRX_N5

K34

PCIE_GTX_C_MRX_N6

L30

PCIE_GTX_C_MRX_N7

M34

PCIE_GTX_C_MRX_N8

N30

PCIE_GTX_C_MRX_N9

P34

PCIE_GTX_C_MRX_N10

R30

PCIE_GTX_C_MRX_N11

T34

PCIE_GTX_C_MRX_N12

U30

PCIE_GTX_C_MRX_N13

V34

PCIE_GTX_C_MRX_N14

W30

PCIE_GTX_C_MRX_N15

Y34

PCIE_GTX_C_MRX_P0

D30

PCIE_GTX_C_MRX_P1

E34

PCIE_GTX_C_MRX_P2

F30

PCIE_GTX_C_MRX_P3

G34

PCIE_GTX_C_MRX_P4

H30

PCIE_GTX_C_MRX_P5

J34

PCIE_GTX_C_MRX_P6

K30

PCIE_GTX_C_MRX_P7

L34

PCIE_GTX_C_MRX_P8

M30

PCIE_GTX_C_MRX_P9

N34

PCIE_GTX_C_MRX_P10

P30

PCIE_GTX_C_MRX_P11

R34

PCIE_GTX_C_MRX_P12

T30

PCIE_GTX_C_MRX_P13

U34

PCIE_GTX_C_MRX_P14

V30

PCIE_GTX_C_MRX_P15

W34

PCIE_MTX_GRX_N0

E32

PCIE_MTX_GRX_N1

F36

PCIE_MTX_GRX_N2

G32

PCIE_MTX_GRX_N3

H36

PCIE_MTX_GRX_N4

J32

PCIE_MTX_GRX_N5

K36

PCIE_MTX_GRX_N6

L32

PCIE_MTX_GRX_N7

M36

PCIE_MTX_GRX_N8

N32

PCIE_MTX_GRX_N9

P36

PCIE_MTX_GRX_N10

R32

PCIE_MTX_GRX_N11

T36

PCIE_MTX_GRX_N12

U32

PCIE_MTX_GRX_N13

V36

PCIE_MTX_GRX_N14

W32

PCIE_MTX_GRX_N15

Y36

PCIE_MTX_GRX_P0

D32

PCIE_MTX_GRX_P1

E36

PCIE_MTX_GRX_P2

F32

PCIE_MTX_GRX_P3

G36

PCIE_MTX_GRX_P4

H32

PCIE_MTX_GRX_P5

J36

PCIE_MTX_GRX_P6

K32

PCIE_MTX_GRX_P7

L36

PCIE_MTX_GRX_P8

M32

PCIE_MTX_GRX_P9

N36

PCIE_MTX_GRX_P10

P32

PCIE_MTX_GRX_P11

R36

PCIE_MTX_GRX_P12

T32

PCIE_MTX_GRX_P13

U36

PCIE_MTX_GRX_P14

V32

PCIE_MTX_GRX_P15

W36

PEG_COMP

1 2

R156 24.9_0402_1%

C132 0.1U_0402_16V4ZPM@

1 2

C134 0.1U_0402_16V4ZPM@

1 2

C136 0.1U_0402_16V4ZPM@

1 2

C138 0.1U_0402_16V4ZPM@

1 2

C140 0.1U_0402_16V4ZPM@

1 2

C142 0.1U_0402_16V4ZPM@

1 2

C144 0.1U_0402_16V4ZPM@

1 2

C146 0.1U_0402_16V4ZPM@

1 2

C131 0.1U_0402_16V4ZPM@

1 2

C133 0.1U_0402_16V4ZPM@

1 2

C135 0.1U_0402_16V4ZPM@

1 2

C137 0.1U_0402_16V4ZPM@

1 2

C139 0.1U_0402_16V4ZPM@

1 2

C141 0.1U_0402_16V4ZPM@

1 2

C143 0.1U_0402_16V4ZPM@

1 2

C145 0.1U_0402_16V4ZPM@

1 2

+1.5VS

C153 0.1U_0402_16V4ZPM@

1 2

C155 0.1U_0402_16V4ZPM@

1 2

C157 0.1U_0402_16V4ZPM@

1 2

C159 0.1U_0402_16V4ZPM@

1 2

C161 0.1U_0402_16V4ZPM@

1 2

C163 0.1U_0402_16V4ZPM@

1 2

C165 0.1U_0402_16V4ZPM@

1 2

C167 0.1U_0402_16V4ZPM@

1 2

C152 0.1U_0402_16V4ZPM@

1 2

C154 0.1U_0402_16V4ZPM@

1 2

C156 0.1U_0402_16V4ZPM@

1 2

C158 0.1U_0402_16V4ZPM@

1 2

C160 0.1U_0402_16V4ZPM@

1 2

C162 0.1U_0402_16V4ZPM@

1 2

C164 0.1U_0402_16V4ZPM@

1 2

C166 0.1U_0402_16V4ZPM@

1 2

PCIE_MTX_C_GRX_N[0..15]

PCIE_MTX_C_GRX_P[0..15]
PCIE_GTX_C_MRX_N[0..15]
PCIE_GTX_C_MRX_P[0..15]

PCIE_MTX_C_GRX_N0
PCIE_MTX_C_GRX_N1
PCIE_MTX_C_GRX_N2

PCIE_MTX_C_GRX_N3

PCIE_MTX_C_GRX_N4
PCIE_MTX_C_GRX_N5
PCIE_MTX_C_GRX_N6
PCIE_MTX_C_GRX_N7
PCIE_MTX_C_GRX_N8
PCIE_MTX_C_GRX_N9
PCIE_MTX_C_GRX_N10
PCIE_MTX_C_GRX_N11
PCIE_MTX_C_GRX_N12
PCIE_MTX_C_GRX_N13
PCIE_MTX_C_GRX_N14
PCIE_MTX_C_GRX_N15

PCIE_MTX_C_GRX_P0
PCIE_MTX_C_GRX_P1
PCIE_MTX_C_GRX_P2
PCIE_MTX_C_GRX_P3
PCIE_MTX_C_GRX_P4
PCIE_MTX_C_GRX_P5
PCIE_MTX_C_GRX_P6
PCIE_MTX_C_GRX_P7
PCIE_MTX_C_GRX_P8
PCIE_MTX_C_GRX_P9
PCIE_MTX_C_GRX_P10
PCIE_MTX_C_GRX_P11
PCIE_MTX_C_GRX_P12
PCIE_MTX_C_GRX_P13
PCIE_MTX_C_GRX_P14
PCIE_MTX_C_GRX_P15

+3VS

R154

4.7K_0402_5%GM@

1 2

1 2

R150

GMCH_LCD_CLK 21

ENBKL15,39

4.7K_0402_5%GM@

GMCH_LCD_DATA 21

4

+3VS +2.5VS

12

R144

2.2K_0402_5%GM@

2

1 3

D

Q8

G

LBKLT_EN

S

BSS138_SOT23GM@

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITT EN CON SENT O F COMPAL ELECTRONICS, INC.

3

Compal Secret Data

Deciphered Date

2006/03/012005/03/01

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

INTEL Alviso PCI-E(2/5)
EAL30 LA-2691

星期

, 03, 2005

四三月

1

of

752

1.0

GM@

A A

GM@

R155

4.7K_0402_5%

LDDC_CLK

R153

4.7K_0402_5%

LDDC_DATA

G

2

1 2

1 2

5

S

+2.5VS

S

G

2

GMCH_LCD_CLK

13

D

Q10

2N7002_SOT23GM@

GMCH_LCD_DATA

13

D

Q9

2N7002_SOT23GM@

5

D D

DDRA_SDQ[0..63]11

DDRA_SDM[0..7]11

DDRA_SDQS[0..7]11

DDRA_SMA[0..13]11 DDRB_SMA[0..13]12

DDRA_SDQ[0..63]
DDRA_SDM[0..7]
DDRA_SDQS[0..7]
DDRA_SMA[0..13]

4

3

DDRB_SMA[0..13]

2

1

DDRA_SBS011
DDRA_SBS111

DDRA_SDM0
DDRA_SDM1
DDRA_SDM2
DDRA_SDM3
DDRA_SDM4
DDRA_SDM5
DDRA_SDM6
DDRA_SDM7

DDRA_SDQS0
DDRA_SDQS1

C C

B B

DDRA_SCAS#11
DDRA_SRAS#11

DDRA_SWE#11 DDRB_SWE#12

DDRA_SDQS2
DDRA_SDQS3
DDRA_SDQS4
DDRA_SDQS5
DDRA_SDQS6
DDRA_SDQS7

DDRA_SMA0
DDRA_SMA1
DDRA_SMA2
DDRA_SMA3
DDRA_SMA4
DDRA_SMA5
DDRA_SMA6
DDRA_SMA7
DDRA_SMA8
DDRA_SMA9
DDRA_SMA10
DDRA_SMA11
DDRA_SMA12
DDRA_SMA13 DDRB_SMA13

AK15
AK16
AL21

AJ37
AP35
AL29
AP24

AP9
AP4
AJ2
AD3

AK36
AP33
AN29
AP23

AM8
AM4

AJ1

AE5

AK35
AP34
AN30
AN23

AN8
AM5
AH1
AE4

AL17
AP17
AP18
AM17
AN18
AM18
AL19
AP20
AM19
AL20
AM16
AN20
AM20
AM15

AN15
AP16
AF29
AF28
AP15

SA_BS0#
SA_BS1#
SA_BS2#

SA_DM0
SA_DM1
SA_DM2
SA_DM3
SA_DM4
SA_DM5
SA_DM6
SA_DM7

SA_DQS0
SA_DQS1
SA_DQS2
SA_DQS3
SA_DQS4
SA_DQS5
SA_DQS6
SA_DQS7

SA_DQS0#
SA_DQS1#
SA_DQS2#
SA_DQS3#
SA_DQS4#
SA_DQS5#
SA_DQS6#
SA_DQS7#

SA_MA0
SA_MA1
SA_MA2
SA_MA3
SA_MA4
SA_MA5
SA_MA6
SA_MA7
SA_MA8
SA_MA9
SA_MA10
SA_MA11
SA_MA12
SA_MA13

SA_CAS#
SA_RAS#
SA_RCVENIN#
SA_RCVENOUT#
SA_WE#

U44C

SADQ0
SADQ1
SADQ2
SADQ3
SADQ4
SADQ5
SADQ6
SADQ7
SADQ8

SADQ9
SADQ10
SADQ11
SADQ12
SADQ13
SADQ14
SADQ15
SADQ16
SADQ17
SADQ18
SADQ19
SADQ20
SADQ21
SADQ22
SADQ23
SADQ24
SADQ25
SADQ26
SADQ27
SADQ28
SADQ29
SADQ30
SADQ31
SADQ32
SADQ33
SADQ34
SADQ35
SADQ36
SADQ37
SADQ38
SADQ39
SADQ40
SADQ41
SADQ42
SADQ43

DDR MEMORY SYSTEM A

SADQ44
SADQ45
SADQ46
SADQ47
SADQ48
SADQ49
SADQ50
SADQ51
SADQ52
SADQ53
SADQ54
SADQ55
SADQ56
SADQ57
SADQ58
SADQ59
SADQ60
SADQ61
SADQ62
SADQ63

ALVISO_BGA1257915PM@

AG35
AH35
AL35
AL37
AH36
AJ35
AK37
AL34
AM36
AN35
AP32
AM31
AM34
AM35
AL32
AM32
AN31
AP31
AN28
AP28
AL30
AM30
AM28
AL28
AP27
AM27
AM23
AM22
AL23
AM24
AN22
AP22
AM9
AL9
AL6
AP7
AP11
AP10
AL7
AM7
AN5
AN6
AN3
AP3
AP6
AM6
AL4
AM3
AK2
AK3
AG2
AG1
AL3
AM2
AH3
AG3
AF3
AE3
AD6
AC4
AF2
AF1
AD4
AD5

DDRA_SDQ0
DDRA_SDQ1
DDRA_SDQ2
DDRA_SDQ3
DDRA_SDQ4
DDRA_SDQ5
DDRA_SDQ6
DDRA_SDQ7
DDRA_SDQ8
DDRA_SDQ9
DDRA_SDQ10
DDRA_SDQ11
DDRA_SDQ12
DDRA_SDQ13
DDRA_SDQ14
DDRA_SDQ15
DDRA_SDQ16
DDRA_SDQ17
DDRA_SDQ18
DDRA_SDQ19
DDRA_SDQ20
DDRA_SDQ21
DDRA_SDQ22
DDRA_SDQ23
DDRA_SDQ24
DDRA_SDQ25
DDRA_SDQ26
DDRA_SDQ27
DDRA_SDQ28
DDRA_SDQ29
DDRA_SDQ30
DDRA_SDQ31
DDRA_SDQ32
DDRA_SDQ33
DDRA_SDQ34
DDRA_SDQ35
DDRA_SDQ36
DDRA_SDQ37
DDRA_SDQ38
DDRA_SDQ39
DDRA_SDQ40
DDRA_SDQ41
DDRA_SDQ42
DDRA_SDQ43
DDRA_SDQ44
DDRA_SDQ45
DDRA_SDQ46
DDRA_SDQ47
DDRA_SDQ48
DDRA_SDQ49
DDRA_SDQ50
DDRA_SDQ51
DDRA_SDQ52
DDRA_SDQ53
DDRA_SDQ54
DDRA_SDQ55
DDRA_SDQ56
DDRA_SDQ57
DDRA_SDQ58
DDRA_SDQ59
DDRA_SDQ60
DDRA_SDQ61
DDRA_SDQ62
DDRA_SDQ63

DDRB_SBS012
DDRB_SBS112

DDRB_SMA0
DDRB_SMA1
DDRB_SMA2
DDRB_SMA3
DDRB_SMA4
DDRB_SMA5
DDRB_SMA6
DDRB_SMA7
DDRB_SMA8
DDRB_SMA9
DDRB_SMA10
DDRB_SMA11
DDRB_SMA12

DDRB_SCAS#12
DDRB_SRAS#12

AJ15
AG17
AG21

AF32

AK34

AK27

AK24

AJ10

AF34

AK32

AJ28

AK23
AM10

AF35

AK33

AK28

AJ23

AL10

AH17

AK17
AH18

AJ18

AK18

AJ19

AK19
AH19

AJ20
AH20

AJ16
AG18
AG20
AG15

AH14

AK14

AF15

AF14
AH16

AK5
AE7
AB7

AH6
AF8
AB4

AH7
AF7
AB5

SB_BS0#
SB_BS1#
SB_BS2#

SB_DM0
SB_DM1
SB_DM2
SB_DM3
SB_DM4
SB_DM5
SB_DM6
SB_DM7

SB_DQS0
SB_DQS1
SB_DQS2
SB_DQS3
SB_DQS4
SB_DQS5
SB_DQS6
SB_DQS7

SB_DQS0#
SB_DQS1#
SB_DQS2#
SB_DQS3#
SB_DQS4#
SB_DQS5#
SB_DQS6#
SB_DQS7#

SB_MA0
SB_MA1
SB_MA2
SB_MA3
SB_MA4
SB_MA5
SB_MA6
SB_MA7
SB_MA8
SB_MA9
SB_MA10
SB_MA11
SB_MA12
SB_MA13

SB_CAS#
SB_RAS#
SB_RCVENIN#
SB_RCVENOUT#
SB_WE#

U44D

AE31

SBDQ0

AE32

SBDQ1

AG32

SBDQ2

AG36

SBDQ3

AE34

SBDQ4

AE33

SBDQ5

AF31

SBDQ6

AF30

SBDQ7

AH33

SBDQ8

AH32

SBDQ9

AK31

SBDQ10

AG30

SBDQ11

AG34

SBDQ12

AG33

SBDQ13

AH31

SBDQ14

AJ31

SBDQ15

AK30

SBDQ16

AJ30

SBDQ17

AH29

SBDQ18

AH28

SBDQ19

AK29

SBDQ20

AH30

SBDQ21

AH27

SBDQ22

AG28

SBDQ23

AF24

SBDQ24

AG23

SBDQ25

AJ22

SBDQ26

AK22

SBDQ27

AH24

SBDQ28

AH23

SBDQ29

AG22

SBDQ30

AJ21

SBDQ31

AG10

SBDQ32

AG9

SBDQ33

AG8

SBDQ34

AH8

SBDQ35

AH11

SBDQ36

AH10

SBDQ37

AJ9

SBDQ38

AK9

SBDQ39

AJ7

SBDQ40

AK6

SBDQ41

AJ4

SBDQ42
SBDQ43
SBDQ44
SBDQ45
SBDQ46
SBDQ47
SBDQ48
SBDQ49
SBDQ50
SBDQ51
SBDQ52
SBDQ53
SBDQ54
SBDQ55
SBDQ56
SBDQ57
SBDQ58
SBDQ59
SBDQ60
SBDQ61
SBDQ62
SBDQ63

AH5
AK8
AJ8
AJ5
AK4
AG5
AG4
AD8
AD9
AH4
AG6
AE8
AD7
AC5
AB8
AB6
AA8
AC8
AC7
AA4
AA5

DDR SYSTEM MEMORY B

ALVISO_BGA1257915PM@

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITT EN CON SENT O F COMPAL ELECTRONICS, INC.

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

2006/03/012005/03/01

2

Title

Size Document Number Rev

Date: Sheet

INTEL Alviso DDR(3/5)
EAL30 LA-2691

星期

, 03, 2005

四三月

1

of

852

1.0

5

4

3

2

1

+1.05VS

12

C129

22U_1206_16V4Z_V1

0.1U_0402_16V4Z

1

1

C204

2

2

VCCHV(Ball A21,B21,B22)

+1.5VS

1

C220

C218

2

0.1U_0402_16V4Z

+1.05VS

1

C130

2

2.2U_0603_6.3V6K

U44E

+1.05VS

3900mA

D D

C C

+1.5VS_DPLLA
+1.5VS_DPLLB
+1.5VS_HPLL
+1.5VS_MPLL

+1.5VS

+1.5VS_DPLLA
+1.5VS_DPLLB
+1.5VS_HPLL
+1.5VS_MPLL

180mA

B B

60mA

1

C208

2

22U_1206_16V4Z_V1

T29
R29

N29
M29
K29

J29
V28
U28

T28
R28
P28
N28
M28

L28
K28

J28
H28
G28
V27
U27

T27
R27
P27
N27
M27

L27
K27

J27
H27
K26
H26
K25

J25
K24
K23
K22
K21

W20

U20

T20
K20
V19
U19
K19

W18

V18

T18
K18
K17

AC1
AC2

B23
C35
AA1
AA2

L11
0_0603_5%

1 2

1

C209

2

0.1U_0402_16V4Z

VCC0
VCC1
VCC2
VCC3
VCC4
VCC5
VCC6
VCC7
VCC8
VCC9
VCC10
VCC11
VCC12
VCC13
VCC14
VCC15
VCC16
VCC17
VCC18
VCC19
VCC20
VCC21
VCC22
VCC23
VCC24
VCC25
VCC26
VCC27
VCC28
VCC29
VCC30
VCC31
VCC32
VCC33
VCC34
VCC35
VCC36
VCC37
VCC38
VCC39
VCC40
VCC41
VCC42
VCC43
VCC44
VCC45
VCC46
VCC47
VCC48

VCCD_HMPLL1
VCCD_HMPLL2
VCCA_DPLLA
VCCA_DPLLB
VCCA_HPLL
VCCA_MPLL

ALVISO_BGA1257915PM@

+1.5VS +1.5VS

POWER

+1.5VS_DPLLB+1.5VS_DPLLA

1

C235

2

22U_1206_16V4Z_V1

VCCA_TVDACA0
VCCA_TVDACA1
VCCA_TVDACB0
VCCA_TVDACB1
VCCA_TVDACC0
VCCA_TVDACC1

VCCA_TVBG
VSSA_TVBG

VCCD_TVDAC

VCCDQ_TVDAC

VCCD_LVDS0
VCCD_LVDS1
VCCD_LVDS2

VCCA_LVDS

VCCTX_LVDS0
VCCTX_LVDS1
VCCTX_LVDS2

VCCA_3GPLL0
VCCA_3GPLL1
VCCA_3GPLL2

VCCA_3GBG
VSSA_3GBG

VCCA_CRTDAC0
VCCA_CRTDAC1

VSSA_CRTDAC

60mA

VCCHV0
VCCHV1
VCCHV2

VCCA_SM0
VCCA_SM1
VCCA_SM2
VCCA_SM3

VCC3G0
VCC3G1
VCC3G2
VCC3G3
VCC3G4
VCC3G5
VCC3G6

VCC_SYNC

F17
E17
D18
C18
F18
E18

H18
G18

D19
H17

B26
B25
A25

A35
B22

B21
A21

B28
A28
A27

AF20
AP19
AF19
AF18

AE37
W37
U37
R37
N37
L37
J37

Y29
Y28
Y27

F37

15mA

G37
H20
F19

E19
G19

L14
0_0603_5%

1 2

1

C233

2

0.1U_0402_16V4Z

120mA

24mA

60mA

20mA
10mA

60mA

1000mA

70mA

+3VS_DAC

+1.5VS

+2.5VS

+1.5VS_DDRDLL

+1.5VS_PEG

0.47U_0603_16V4Z

+1.5VS_3GPLL

+2.5VS_3GBG

+2.5VS

0.47U_0603_16V4Z

+1.5VS_DDRDLL

+1.05VS

810mA

C715

1

2

1

C682

2

C693

0.22U_0402_10V4Z

0.22U_0402_10V4Z

1

C190

2

22U_1206_16V4Z_V1

1

2

C688

K13

J13

K12

W11

V11
U11
T11
R11
P11
N11
M11
L11
K11

W10

V10
U10
T10
R10
P10
N10
M10
K10

J10

Y9

W9

U9
R9
P9
N9
M9

L9

J9
N8
M8
N7
M7
N6
M6
A6
N5
M5
N4
M4
N3
M3
N2
M2
B2
V1
N1
M1
G1

1

2

R129
0_0603_5%

1 2

1

C196

2

0.1U_0402_16V4Z

U44F

VTT0
VTT1
VTT2
VTT3
VTT4
VTT5
VTT6
VTT7
VTT8
VTT9
VTT10
VTT11
VTT12
VTT13
VTT14
VTT15
VTT16
VTT17
VTT18
VTT19
VTT20
VTT21
VTT22
VTT23
VTT24
VTT25
VTT26
VTT27
VTT28
VTT29
VTT30
VTT31
VTT32
VTT33
VTT34
VTT35
VTT36
VTT37
VTT38
VTT39
VTT40
VTT41
VTT42
VTT43
VTT44
VTT45
VTT46
VTT47
VTT48
VTT49
VTT50
VTT51

ALVISO_BGA1257915PM@

POWER

+1.5VS_PEG

+1.5VS

1

2

VCCSM0
VCCSM1
VCCSM2
VCCSM3
VCCSM4
VCCSM5
VCCSM6
VCCSM7
VCCSM8

VCCSM9
VCCSM10
VCCSM11
VCCSM12
VCCSM13
VCCSM14
VCCSM15
VCCSM16
VCCSM17
VCCSM18
VCCSM19
VCCSM20
VCCSM21
VCCSM22
VCCSM23
VCCSM24
VCCSM25
VCCSM26
VCCSM27
VCCSM28
VCCSM29
VCCSM30
VCCSM31
VCCSM32
VCCSM33
VCCSM34
VCCSM35
VCCSM36
VCCSM37
VCCSM38
VCCSM39
VCCSM40
VCCSM41
VCCSM42
VCCSM43
VCCSM44
VCCSM45
VCCSM46
VCCSM47
VCCSM48
VCCSM49
VCCSM50
VCCSM51
VCCSM52
VCCSM53
VCCSM54
VCCSM55
VCCSM56
VCCSM57
VCCSM58
VCCSM59
VCCSM60
VCCSM61
VCCSM62
VCCSM63
VCCSM64

C243

22U_1206_16V4Z_V1

AM37
AH37
AP29
AD28
AD27
AC27
AP26
AN26
AM26
AL26
AK26
AJ26
AH26
AG26
AF26
AE26
AP25
AN25
AM25
AL25
AK25
AJ25
AH25
AG25
AF25
AE25
AE24
AE23
AE22
AE21
AE20
AE19
AE18
AE17
AE16
AE15
AE14
AP13
AN13
AM13
AL13
AK13
AJ13
AH13
AG13
AF13
AE13
AP12
AN12
AM12
AL12
AK12
AJ12
AH12
AG12
AF12
AE12
AD11
AC11
AB11
AB10
AB9

V1.8_DDR_CAP6

AP8

V1.8_DDR_CAP4

AM1

V1.8_DDR_CAP3

AE1

1

C242

2

4.7U_0805_10V4Z

V1.8_DDR_CAP1
V1.8_DDR_CAP2
V1.8_DDR_CAP5

C238

0.1U_0402_16V4Z

+2.5V

2200mA

+2.5V

C745

330U_D2E_2.5VM

VCCA_LVDS (Ball A35)

VCC_SYNC(Ball H20)

C127

0.1U_0402_16V4Z

12

0.1U_0402_16V4Z

1

C244

2

4.7U_0805_10V4Z

12

2200mA

0.1U_0402_16V4Z

1

+

C128

2

+2.5VS

1

C231

2

0.1U_0402_16V4Z

+2.5VS

1

C189

2

4.7U_0805_10V4Z

C120

0.1U_0402_16V4Z

12

12

C689

R160
0_0805_5%

1 2

C237

0.1U_0402_16V4Z

12

C227

0.1U_0402_16V4Z

1

C168

2

0.1U_0402_16V4Z

1

C232

2

0.01U_0402_16V7K

1

C194

2

0.1U_0402_16V4Z

4.7U_0805_10V4Z

+1.5VS

1

+

C234

2

470U_D2_2.5VM

2.2U_0603_6.3V6K

1

C212

2

1

C213

2

0.1U_0402_16V4Z

1

C202

2

4.7U_0805_10V4Z

4000mA

1

2

0.1U_0402_16V4Z

C222

0.1U_0402_16V4Z

1

C214

2

2.2U_0603_6.3V6K

1

C180

2

0.1U_0402_16V4Z

1

C206

2

0.1U_0402_16V4Z

C126

VCCA_CRTDAC(Ball F19,E19)

1

C200

2

0.1U_0402_16V4Z

1

2

1

C205

2

0.022U_0402_16V7K

VCCD_TVDAC (Ball D19)

0.1U_0402_16V4Z

1

C184

C185

2

0.022U_0402_16V7K

1

2

950mA

1

C170

2

2.2U_0603_6.3V6K

1

2

0.1U_0402_16V4Z

1

1

1

C224

C179

2

2

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

C217

2

1

C225

2

4.7U_0805_10V4Z

C147

2

0.1U_0402_16V4Z

1

2

1

C223

2

0.1U_0402_16V4Z

VCCTX_LVDS(Ball A27,A28,B28)

0.1U_0402_16V4Z

1

1

C181

C178

2

2

0.022U_0402_16V7K

VCCDQ_TVDAC (Ball H17)VCCD_LVDS(Ball A25,B25,B26)

1

C198

2.2U_0603_6.3V6K

C173

2

2.2U_0603_6.3V6K

VCCA_TVDAC

L38

C855

CHB1608U301_0603

1 2

1

+

2

4.7U_0805_10V4Z
22U_1206_16V4Z_V1

+1.5VS_HPLL

A A

60mA

1

C690

2

22U_1206_16V4Z_V1

L27
0_0603_5%

1 2

1

C692

2

0.1U_0402_16V4Z

+1.5VS_MPLL +1.5VS_3GPLL

+1.5VS

60mA

1

C112

2

22U_1206_16V4Z_V1

L7
0_0603_5%

1 2

1

C114

2

0.1U_0402_16V4Z

+1.5VS

1

C221

2

10U_1206_16V4Z

R145

0.5_0603_1%

1 2

1

C226

2

0.1U_0402_16V4Z

+3GPLL

L13
0_0603_5%

1 2

+1.5VS

+2.5VS_3GBG

1

2

1 2

R159 0_0603_5%

C241

0.1U_0402_16V4Z

+2.5VS

+3VS

150U_D2_6.3VM

+3VS_DAC

C856

1

2

C857

1

C177

2

0.1U_0402_16V4Z

1

2

1

2

VCCA_TVBG (Ball H18)

C188

0.022U_0402_16V7K

1

C187

2

0.1U_0402_16V4Z

1

C195

2

0.022U_0402_16V7K

120mA

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITT EN CON SENT O F COMPAL ELECTRONICS, INC.

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

2006/03/012005/03/01

2

Title

Size Document Number Rev

Date: Sheet

INTEL Alviso POWER(4/5)
EAL30 LA-2691

星期

, 03, 2005

四三月

1

of

952

1.0

5

4

3

2

1

U44H

+1.05VS

D D

C C

B B

+1.05VS

A A

L12

VTT_NCTF17

M12

VTT_NCTF16

N12

VTT_NCTF15

P12

VTT_NCTF14

R12

VTT_NCTF13

T12

VTT_NCTF12

U12

VTT_NCTF11

V12

VTT_NCTF10

W12

VTT_NCTF9

L13

VTT_NCTF8

M13

VTT_NCTF7

N13

VTT_NCTF6

P13

VTT_NCTF5

R13

VTT_NCTF4

T13

VTT_NCTF3

U13

VTT_NCTF2

V13

VTT_NCTF1

W13

VTT_NCTF0

Y12

VSS_NCTF68

AA12

VSS_NCTF67

Y13

VSS_NCTF66

AA13

VSS_NCTF65

L14

VSS_NCTF64

M14

VSS_NCTF63

N14

VSS_NCTF62

P14

VSS_NCTF61

R14

VSS_NCTF60

T14

VSS_NCTF59

U14

VSS_NCTF58

V14

VSS_NCTF57

W14

VSS_NCTF56

Y14

VSS_NCTF55

AA14

VSS_NCTF54

AB14

VSS_NCTF53

L15

VSS_NCTF52

M15

VSS_NCTF51

N15

VSS_NCTF50

P15

VSS_NCTF49

R15

VSS_NCTF48

T15

VSS_NCTF47

U15

VSS_NCTF46

V15

VSS_NCTF45

W15

VSS_NCTF44

Y15

VSS_NCTF43

AA15

VSS_NCTF42

AB15

VSS_NCTF41

L16

VSS_NCTF40

M16

VSS_NCTF39

N16

VSS_NCTF38

P16

VSS_NCTF37

R16

VSS_NCTF36

T16

VSS_NCTF35

U16

VSS_NCTF34

V16

VSS_NCTF33

W16

VSS_NCTF32

Y16

VSS_NCTF31

AA16

VSS_NCTF30

AB16

VSS_NCTF29

R17

VSS_NCTF28

Y17

VSS_NCTF27

AA17

VSS_NCTF26

AB17

VSS_NCTF25

AA18

VSS_NCTF24

AB18

VSS_NCTF23

AA19

VSS_NCTF22

AB19

VSS_NCTF21

AA20

VSS_NCTF20

AB20

VSS_NCTF19

R21

VSS_NCTF18

Y21

VSS_NCTF17

AA21

VSS_NCTF16

AB21

VSS_NCTF15

Y22

VSS_NCTF14

AA22

VSS_NCTF13

AB22

VSS_NCTF12

Y23

VSS_NCTF11

AA23

VSS_NCTF10

AB23

VSS_NCTF9

Y24

VSS_NCTF8

AA24

VSS_NCTF7

AB24

VSS_NCTF6

Y25

VSS_NCTF5

AA25

VSS_NCTF4

AB25

VSS_NCTF3

Y26

VSS_NCTF2

AA26

VSS_NCTF1

AB26

VSS_NCTF0

V25

VCC_NCTF10

W25

VCC_NCTF9

L26

VCC_NCTF8

M26

VCC_NCTF7

N26

VCC_NCTF6

P26

VCC_NCTF5

R26

VCC_NCTF4

T26

VCC_NCTF3

U26

VCC_NCTF2

V26

VCC_NCTF1

W26

VCC_NCTF0

ALVISO_BGA1257915PM@

5

VCCSM_NCTF31
VCCSM_NCTF30
VCCSM_NCTF29
VCCSM_NCTF28
VCCSM_NCTF27
VCCSM_NCTF26
VCCSM_NCTF25
VCCSM_NCTF24
VCCSM_NCTF23
VCCSM_NCTF22
VCCSM_NCTF21
VCCSM_NCTF20
VCCSM_NCTF19
VCCSM_NCTF18
VCCSM_NCTF17
VCCSM_NCTF16
VCCSM_NCTF15
VCCSM_NCTF14
VCCSM_NCTF13
VCCSM_NCTF12
VCCSM_NCTF11
VCCSM_NCTF10

VCCSM_NCTF9
VCCSM_NCTF8
VCCSM_NCTF7
VCCSM_NCTF6
VCCSM_NCTF5
VCCSM_NCTF4
VCCSM_NCTF3
VCCSM_NCTF2
VCCSM_NCTF1
VCCSM_NCTF0

VCC_NCTF78
VCC_NCTF77
VCC_NCTF76
VCC_NCTF75
VCC_NCTF74
VCC_NCTF73
VCC_NCTF72
VCC_NCTF71
VCC_NCTF70

NCTF

VCC_NCTF69
VCC_NCTF68
VCC_NCTF67
VCC_NCTF66
VCC_NCTF65
VCC_NCTF64
VCC_NCTF63
VCC_NCTF62
VCC_NCTF61
VCC_NCTF60
VCC_NCTF59
VCC_NCTF58
VCC_NCTF57
VCC_NCTF56
VCC_NCTF55
VCC_NCTF54
VCC_NCTF53
VCC_NCTF52
VCC_NCTF51
VCC_NCTF50
VCC_NCTF49
VCC_NCTF48
VCC_NCTF47
VCC_NCTF46
VCC_NCTF45
VCC_NCTF44
VCC_NCTF43
VCC_NCTF42
VCC_NCTF41
VCC_NCTF40
VCC_NCTF39
VCC_NCTF38
VCC_NCTF37
VCC_NCTF36
VCC_NCTF35
VCC_NCTF34
VCC_NCTF33
VCC_NCTF32
VCC_NCTF31
VCC_NCTF30
VCC_NCTF29
VCC_NCTF28
VCC_NCTF27
VCC_NCTF26
VCC_NCTF25
VCC_NCTF24
VCC_NCTF23
VCC_NCTF22
VCC_NCTF21
VCC_NCTF20
VCC_NCTF19
VCC_NCTF18
VCC_NCTF17
VCC_NCTF16
VCC_NCTF15
VCC_NCTF14
VCC_NCTF13
VCC_NCTF12
VCC_NCTF11

AB12
AC12
AD12
AB13
AC13
AD13
AC14
AD14
AC15
AD15
AC16
AD16
AC17
AD17
AC18
AD18
AC19
AD19
AC20
AD20
AC21
AD21
AC22
AD22
AC23
AD23
AC24
AD24
AC25
AD25
AC26
AD26

L17
M17
N17
P17
T17
U17
V17
W17
L18
M18
N18
P18
R18
Y18
L19
M19
N19
P19
R19
Y19
L20
M20
N20
P20
R20
Y20
L21
M21
N21
P21
T21
U21
V21
W21
L22
M22
N22
P22
R22
T22
U22
V22
W22
L23
M23
N23
P23
R23
T23
U23
V23
W23
L24
M24
N24
P24
R24
T24
U24
V24
W24
L25
M25
N25
P25
R25
T25
U25

+2.5V

+1.05VS

4

U44I

Y1

VSS271

D2

VSS270

G2

VSS269

J2

VSS268

L2

VSS260

P2

VSS259

T2

VSS258

V2

VSS257

AD2

VSS256

AE2

VSS255

AH2

VSS254

AL2

VSS253

AN2

VSS252
VSS251
VSS250
VSS249
VSS248
VSS247
VSS246
VSS245
VSS244
VSS243
VSS242
VSS241
VSS240
VSS239
VSS238
VSS237
VSS236
VSS235
VSS234
VSS233
VSS232
VSS231
VSS230
VSS229
VSS228
VSS227
VSS226
VSS225
VSS224
VSS223
VSS222
VSS221
VSS220
VSS219
VSS218
VSS217
VSS216
VSS215
VSS214
VSS213
VSS212
VSS211
VSS210
VSS209
VSS208
VSS207
VSS206
VSS205
VSS204
VSS203
VSS202
VSS201
VSS200
VSS199
VSS198
VSS197
VSS196

VSS

AA3
AB3
AC3

AF4
AN4

AP5

AA6
AC6
AE6

AA7
AG7
AK7
AN7

AA9
AC9
AE9
AH9
AN9
D10

AA10

H11

A3

C3

AJ3

C4
H4

L4
P4

U4

Y4

E5
W5
AL5

B6

J6

L6

P6

T6

AJ6

G7

V7

C8

E8

L8

P8

Y8
AL8

A9

H9

K9

T9

V9

L10
Y10

F11
Y11

ALVISO_BGA1257915PM@

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITT EN CON SENT O F COMPAL ELECTRONICS, INC.

3

VSSALVDS

VSS195
VSS194
VSS193
VSS192
VSS191
VSS190
VSS189
VSS188
VSS187
VSS186
VSS185
VSS184
VSS183
VSS182
VSS181
VSS180
VSS179
VSS178
VSS177
VSS176
VSS175
VSS174
VSS173
VSS172
VSS171
VSS170
VSS169
VSS168
VSS167
VSS166
VSS165
VSS164
VSS163
VSS162
VSS161
VSS160
VSS159
VSS158
VSS157
VSS156
VSS155
VSS154
VSS153
VSS152
VSS151
VSS150
VSS149
VSS148
VSS147
VSS146
VSS145
VSS144
VSS143
VSS142
VSS141
VSS140
VSS139
VSS138
VSS137
VSS136
VSS135
VSS134
VSS133
VSS132
VSS131
VSS130

B36
AA11

AF11
AG11
AJ11
AL11
AN11
B12
D12
J12
A14
B14
F14
J14
K14
AG14
AJ14
AL14
AN14
C15
K15
A16
D16
H16
K16
AL16
C17
G17
AF17
AJ17
AN17
A18
B18
U18
AL18
C19
H19
J19
T19
W19
AG19
AN19
A20
D20
E20
F20
G20
V20
AK20
C21
F21
AF21
AN21
A22
D22
E22
J22
AH22
AL22
H23
AF23
B24
D24
F24
J24
AG24
AJ24

Compal Secret Data

Deciphered Date

AL24

AN24

A26
E26
G26

B27
E27
G27

W27
AA27
AB27
AF27
AG27

AJ27
AL27

AN27

E28

W28
AA28
AB28
AC28

A29
D29
E29

G29
H29

P29
U29
V29

W29
AA29
AD29
AG29

AJ29

AM29

C30

Y30
AA30
AB30
AC30
AE30
AP30

D31

E31

G31

H31

K31

M31

N31

P31

R31

U31

V31

W31
AD31
AG31

AL31

A32
C32

Y32
AA32
AB32

2

U44J

VSS267
VSS266
VSS265
VSS264
VSS263

J26

VSS262
VSS261
VSS129
VSS128
VSS127
VSS126
VSS125

VSS

VSS124
VSS123
VSS122
VSS121
VSS120
VSS119
VSS118
VSS117
VSS116
VSS115
VSS114
VSS113
VSS112

F29

VSS111
VSS110
VSS109

L29

VSS108
VSS107
VSS106
VSS105
VSS104
VSS103
VSS102
VSS101
VSS100
VSS99
VSS98
VSS97
VSS96
VSS95
VSS94
VSS93
VSS92
VSS91
VSS90

F31

VSS89
VSS88
VSS87

J31

VSS86
VSS85

L31

VSS84
VSS83
VSS82
VSS81
VSS80

T31

VSS79
VSS78
VSS77
VSS76
VSS75
VSS74
VSS73
VSS72
VSS71
VSS70
VSS69
VSS68

ALVISO_BGA1257915PM@

Title

Size Document Number Rev

星期

Date: Sheet

AC32

VSS67

AD32

VSS66

AJ32

VSS65

AN32

VSS64

D33

VSS63

E33

VSS62

F33

VSS61

G33

VSS60

H33

VSS59

J33

VSS58

K33

VSS57

L33

VSS56

M33

VSS55

N33

VSS54

P33

VSS53

R33

VSS52

T33

VSS51

U33

VSS50

V33

VSS49

W33

VSS48

AD33

VSS47

AF33

VSS46

AL33

VSS45

C34

VSS44

AA34

VSS43

AB34

VSS42

AC34

VSS41

AD34

VSS40

AH34

VSS39

AN34

VSS38

B35

VSS37

D35

VSS36

E35

VSS35

F35

VSS34

G35

VSS33

H35

VSS32

J35

VSS31

K35

VSS30

L35

VSS29

M35

VSS28

N35

VSS27

P35

VSS26

R35

VSS25

T35

VSS24

U35

VSS23

V35

VSS22

W35

VSS21

Y35

VSS20

AE35

VSS19

C36

VSS18

AA36

VSS17

AB36

VSS16

AC36

VSS15

AD36

VSS14

AE36

VSS13

AF36

VSS12

AJ36

VSS11

AL36

VSS10

AN36

VSS9

E37

VSS8

H37

VSS7

K37

VSS6

M37

VSS5

P37

VSS4

T37

VSS3

V37

VSS2

Y37

VSS1

AG37

VSS0

Compal Electronics, Inc.

INTEL Alviso POWER(5/5)
EAL30 LA-2691

, 03, 2005

四三月

1

of

10 52

1.0

5

4

3

2

1

+2.5V

DDRA_DQ1

D D

DDRA_CLK16
DDRA_CLK1#6

C C

DDRA_CKE16

DDRA_SBS08
DDRA_SWE#8
DDRA_SCS#06 DDRA_SCS#1 6

B B

A A

D_CK_SDATA12,14
D_CK_SCLK12,14

DDRA_DQ5
DDRA_DQS0

DDRA_DQ7
DDRA_DQ3

DDRA_DQ13
DDRA_DQ9

DDRA_DQS1
DDRA_DQ15

DDRA_DQ11

DDRA_DQ16
DDRA_DQ20

DDRA_DQS2
DDRA_DQ18

DDRA_DQ22
DDRA_DQ25

DDRA_DQ29
DDRA_DQS3

DDRA_DQ27
DDRA_DQ30

DDRA_CKE1
DDRA_SMA12

DDRA_SMA9
DDRA_SMA7

DDRA_SMA5
DDRA_SMA3
DDRA_SMA1

DDRA_SMA10
DDRA_SBS0
DDRA_SWE#

DDRA_SMA13
DDRA_DQ36

DDRA_DQ33
DDRA_DQS4

DDRA_DQ38
DDRA_DQ35

DDRA_DQ41
DDRA_DQ44

DDRA_DQS5
DDRA_DQ46

DDRA_DQ47

DDRA_DQ52
DDRA_DQ53

DDRA_DQS6
DDRA_DQ54

DDRA_DQ50
DDRA_DQ60

DDRA_DQ56
DDRA_DQS7

DDRA_DQ57
DDRA_DQ62

D_CK_SDATA
D_CK_SCLK

5

+3VS

JP25

1

VREF

3

VSS

5

DQ0

7

DQ1

9

VDD

11

DQS0

13

DQ2

15

VSS

17

DQ3

19

DQ8

21

VDD

23

DQ9

25

DQS1

27

VSS

29

DQ10

31

DQ11

33

VDD

35

CK0

37

CK0#

39

VSS

41

DQ16

43

DQ17

45

VDD

47

DQS2

49

DQ18

51

VSS

53

DQ19

55

DQ24

57

VDD

59

DQ25

61

DQS3

63

VSS

65

DQ26

67

DQ27

69

VDD

71

CB0

73

CB1

75

VSS

77

DQS8

79

CB2

81

VDD

83

CB3

85

DU

87

VSS

89

CK2

91

CK2#

93

VDD

95

CKE1

97

DU/A13

99

A12

101

A9

103

VSS

105

A7

107

A5

109

A3

111

A1

113

VDD

115

A10/AP

117

BA0

119

WE#

121

S0#

123

DU

125

VSS

127

DQ32

129

DQ33

131

VDD

133

DQS4

135

DQ34

137

VSS

139

DQ35

141

DQ40

143

VDD

145

DQ41

147

DQS5

149

VSS

151

DQ42

153

DQ43

155

VDD

157

VDD

159

VSS

161

VSS

163

DQ48

165

DQ49

167

VDD

169

DQS6

171

DQ50

173

VSS

175

DQ51

177

DQ56

179

VDD

181

DQ57

183

DQS7

185

VSS

187

DQ58

189

DQ59

191

VDD

193

SDA

195

SCL

197

VDD_SPD

199

VDD_ID

AMP_1565917-1

DIMM0

VREF

VDD

DQ12

VDD

DQ13

DQ14
DQ15

VDD
VDD

DQ20
DQ21

VDD
DQ22
DQ23

DQ28

VDD
DQ29

DQ30
DQ31

VDD

VDD

DU/RESET#

VDD

VDD

CKE0

DU/BA2

VDD

RAS#
CAS#

DQ36
DQ37

VDD
DQ38
DQ39

DQ44

VDD
DQ45

DQ46
DQ47

VDD
CK1#

DQ52
DQ53

VDD
DQ54
DQ55

DQ60

VDD
DQ61

DQ62
DQ63

VDD

VSS
DQ4
DQ5

DM0
DQ6
VSS
DQ7

DM1
VSS

VSS
VSS

DM2
VSS

DM3
VSS

CB4
CB5
VSS
DM8
CB6

CB7
VSS

VSS

VSS

BA1

VSS

DM4
VSS

DM5
VSS

CK1
VSS

DM6
VSS

DM7
VSS

SA0
SA1
SA2

A11

A8
A6

A4
A2
A0

S1#

DU

DU

+2.5V +2.5V

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200

4

DDRA_DQ0
DDRA_DQ4

DDRA_DM0
DDRA_DQ6

DDRA_DQ2
DDRA_DQ8

DDRA_DQ12
DDRA_DM1

DDRA_DQ14
DDRA_DQ10

DDRA_DQ17
DDRA_DQ21

DDRA_DM2
DDRA_DQ19

DDRA_DQ23
DDRA_DQ24

DDRA_DQ28
DDRA_DM3

DDRA_DQ26
DDRA_DQ31

DDRA_CKE0
DDRA_SMA11

DDRA_SMA8
DDRA_SMA6

DDRA_SMA4
DDRA_SMA2
DDRA_SMA0

DDRA_SBS1
DDRA_SRAS#
DDRA_SCAS#
DDRA_SCS#1DDRA_SCS#0

DDRA_DQ37
DDRA_DQ32

DDRA_DM4
DDRA_DQ39

DDRA_DQ34
DDRA_DQ45

DDRA_DQ40
DDRA_DM5

DDRA_DQ42
DDRA_DQ43

DDRA_DQ49
DDRA_DQ48

DDRA_DM6
DDRA_DQ55

DDRA_DQ51
DDRA_DQ61

DDRA_DQ58
DDRA_DM7

DDRA_DQ63
DDRA_DQ59

+DIMM_VREF

1

2

C250

0.1U_0402_16V4Z

RP35

10_0404_4P2R_5%

RP34

10_0404_4P2R_5%

RP33

10_0404_4P2R_5%

RP32

10_0404_4P2R_5%

RP31

10_0404_4P2R_5%

RP30

10_0404_4P2R_5%

RP29

10_0404_4P2R_5%

RP28

10_0404_4P2R_5%

RP27

10_0404_4P2R_5%

RP26

10_0404_4P2R_5%

RP15

10_0404_4P2R_5%

RP14

10_0404_4P2R_5%

RP13

10_0404_4P2R_5%

RP12

10_0404_4P2R_5%

RP11

10_0404_4P2R_5%

RP10

10_0404_4P2R_5%

RP9

10_0404_4P2R_5%

RP8

10_0404_4P2R_5%

RP7

10_0404_4P2R_5%

RP6

10_0404_4P2R_5%

DDRA_DQ0

14

DDRA_DQ4

23

DDRA_DM0DDRA_SDM0

14

DDRA_DQ6

23

DDRA_DQ2

14

DDRA_DQ8DDRA_SDQ8

23

DDRA_DQ12

14

DDRA_DM1

23

DDRA_DQ14

14

DDRA_DQ10

23

DDRA_DQ17

14

DDRA_DQ21

23

DDRA_DM2

14

DDRA_DQ19

23

DDRA_DQ23DDRA_SDQ23

14

DDRA_DQ24

23

DDRA_DQ28

14

DDRA_DM3

23

DDRA_DQ26

14

DDRA_DQ31DDRA_SDQ31

23

DDRA_DQ37

14

DDRA_DQ32

23

DDRA_DM4

14

DDRA_DQ39

23

DDRA_DQ34

14

DDRA_DQ45

23

DDRA_DQ40

14

DDRA_DM5

23

DDRA_DQ42

14

DDRA_DQ43

23

DDRA_DQ49

14

DDRA_DQ48

23

DDRA_DM6

14

DDRA_DQ55

23

DDRA_DQ51

14

DDRA_DQ61

23

DDRA_DQ58

14

DDRA_DM7

23

DDRA_DQ63

14

DDRA_DQ59

23

Compal Secret Data

12

R168

1K_0402_1%

12

R170

1K_0402_1%

DDRA_CKE0 6

DDRA_SBS1 8
DDRA_SRAS# 8
DDRA_SCAS# 8

DDRA_CLK2# 6
DDRA_CLK2 6

Security Classification

DDRA_SDQ0
DDRA_SDQ4

DDRA_SDQ6

DDRA_SDQ2

DDRA_SDQ12
DDRA_SDM1

DDRA_SDQ14
DDRA_SDQ10

DDRA_SDQ17
DDRA_SDQ21

DDRA_SDM2
DDRA_SDQ19

DDRA_SDQ24

DDRA_SDQ28
DDRA_SDM3

DDRA_SDQ26

DDRA_SDQ37
DDRA_SDQ32

DDRA_SDM4
DDRA_SDQ39

DDRA_SDQ34
DDRA_SDQ45

DDRA_SDQ40
DDRA_SDM5

DDRA_SDQ42
DDRA_SDQ43

DDRA_SDQ49
DDRA_SDQ48

DDRA_SDM6
DDRA_SDQ55

DDRA_SDQ51
DDRA_SDQ61

DDRA_SDQ58
DDRA_SDM7

DDRA_SDQ63
DDRA_SDQ59

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITT EN CON SENT O F COMPAL ELECTRONICS, INC.

3

DDRA_SDQ1
DDRA_SDQ5

DDRA_SDQS0
DDRA_SDQ7

DDRA_SDQ3
DDRA_SDQ13

DDRA_SDQ9
DDRA_SDQS1

DDRA_SDQ15
DDRA_SDQ11

DDRA_SDQ16
DDRA_SDQ20

DDRA_SDQS2
DDRA_SDQ18

DDRA_SDQ22
DDRA_SDQ25

DDRA_SDQ29
DDRA_SDQS3

DDRA_SDQ27
DDRA_SDQ30

DDRA_SDQ36
DDRA_SDQ33

DDRA_SDQS4
DDRA_SDQ38

DDRA_SDQ35
DDRA_SDQ41

DDRA_SDQ44
DDRA_SDQS5

DDRA_SDQ46
DDRA_SDQ47

DDRA_SDQ52
DDRA_SDQ53

DDRA_SDQS6
DDRA_SDQ54

DDRA_SDQ50
DDRA_SDQ60

DDRA_SDQ56
DDRA_SDQS7

DDRA_SDQ57
DDRA_SDQ62

Deciphered Date

1 4
2 3

1 4
2 3

1 4
2 3

1 4
2 3

1 4
2 3

1 4
2 3

1 4
2 3

1 4
2 3

1 4
2 3

1 4
2 3

1 4
2 3

1 4
2 3

1 4
2 3

1 4
2 3

1 4
2 3

1 4
2 3

1 4
2 3

1 4
2 3

1 4
2 3

1 4
2 3

RP118

DDRA_DQ1
DDRA_DQ5

10_0404_4P2R_5%

RP115

DDRA_DQS0
DDRA_DQ7

10_0404_4P2R_5%

RP112

DDRA_DQ3
DDRA_DQ13

10_0404_4P2R_5%

RP109

DDRA_DQ9
DDRA_DQS1

10_0404_4P2R_5%

RP106

DDRA_DQ15
DDRA_DQ11

10_0404_4P2R_5%

RP102

DDRA_DQ16
DDRA_DQ20

10_0404_4P2R_5%

RP99

DDRA_DQS2
DDRA_DQ18

10_0404_4P2R_5%

RP97

DDRA_DQ22
DDRA_DQ25

10_0404_4P2R_5%

RP94

DDRA_DQ29
DDRA_DQS3

10_0404_4P2R_5%

RP91

DDRA_DQ27
DDRA_DQ30

10_0404_4P2R_5%

RP77

DDRA_DQ36
DDRA_DQ33

10_0404_4P2R_5%

RP74

DDRA_DQS4
DDRA_DQ38

10_0404_4P2R_5%

RP72

DDRA_DQ35
DDRA_DQ41

10_0404_4P2R_5%

RP69

DDRA_DQ44
DDRA_DQS5

10_0404_4P2R_5%

RP66

DDRA_DQ46
DDRA_DQ47

10_0404_4P2R_5%

RP62

DDRA_DQ52
DDRA_DQ53

10_0404_4P2R_5%

RP60

DDRA_DQS6
DDRA_DQ54

10_0404_4P2R_5%

RP57

DDRA_DQ50
DDRA_DQ60

10_0404_4P2R_5%

RP54

DDRA_DQ56
DDRA_DQS7

10_0404_4P2R_5%

RP51

DDRA_DQ57
DDRA_DQ62

10_0404_4P2R_5%

2006/03/012005/03/01

2

+1.25VS

DDRA_SMA11
DDRA_SMA8

DDRA_SMA6
DDRA_SMA4

DDRA_SMA2
DDRA_SMA0

DDRA_SBS1
DDRA_SRAS#

DDRA_SCAS#
DDRA_SCS#1

DDRA_SMA12
DDRA_SMA9

DDRA_SMA7
DDRA_SMA5

DDRA_SMA3
DDRA_SMA1

DDRA_SMA10
DDRA_SBS0

DDRA_SWE#
DDRA_SCS#0

DDRA_SMA13
DDRA_CKE1
DDRA_CKE0

DDRA_DQ[0..63]
DDRA_DM[0..7]
DDRA_DQS[0..7]

DDRA_SDQ[0..63]8

DDRA_SDM[0..7]8

DDRA_SDQS[0..7]8

DDRA_SMA[0..13]8

Title

Size Document Number Rev

星期

, 03, 2005

四三月

Date: Sheet

RP87

1 4
2 3

56_0404_4P2R_5%

RP86

1 4
2 3

56_0404_4P2R_5%

RP84

1 4
2 3

56_0404_4P2R_5%

RP82

1 4
2 3

56_0404_4P2R_5%

RP80

1 4
2 3

56_0404_4P2R_5%

RP24

2 3
1 4

56_0404_4P2R_5%

RP22

2 3
1 4

56_0404_4P2R_5%

RP20

2 3
1 4

56_0404_4P2R_5%

RP18

2 3
1 4

56_0404_4P2R_5%

RP16

2 3
1 4

56_0404_4P2R_5%

1 2

R112 56_0402_5%

1 2

R138 56_0402_5%

1 2

R544 56_0402_5%

DDRA_DQ[0..63] 12
DDRA_DM[0..7] 12
DDRA_DQS[0..7] 12

DDRA_SDQ[0..63]
DDRA_SDM[0..7]
DDRA_SDQS[0..7]
DDRA_SMA[0..13]

Compal Electronics, Inc.

DDR-SODIMM0

EAL30 LA-2691

1

11 52

of

1.0

5

4

3

2

1

+2.5V

+1.25VS

+1.25VS

56_0404_4P2R_5%

56_0404_4P2R_5%

56_0404_4P2R_5%

56_0404_4P2R_5%

56_0404_4P2R_5%

56_0404_4P2R_5%

56_0404_4P2R_5%

56_0404_4P2R_5%

DDRA_DQ[0..63]11

DDRA_DM[0..7]11

DDRA_DQS[0..7]11

DDRB_SMA[0..13]8

12

R29456_0402_5%

12

R54556_0402_5%

12

R13656_0402_5%

RP58

14
23

RP55

14
23

RP52

14
23

RP49

14
23

14
23

RP59

14
23

RP56

14
23

RP53

14
23

RP50

DDRA_DQ0
DDRA_DQ4

D D

C C

B B

A A

DDRA_DM0
DDRA_DQ6

DDRA_DQ2
DDRA_DQ8

DDRA_DQ12
DDRA_DM1

DDRA_DQ14
DDRA_DQ10

DDRA_DQ17
DDRA_DQ21

DDRA_DM2
DDRA_DQ19

DDRA_DQ23
DDRA_DQ24

DDRA_DQ28
DDRA_DM3

DDRA_DQ26
DDRA_DQ31

DDRB_SMA11
DDRB_SMA8

DDRB_SMA6
DDRB_SMA4

DDRB_SMA2
DDRB_SMA0

DDRB_SBS1
DDRB_SRAS#

DDRB_SCAS#
DDRB_SCS#1

DDRA_DQ37
DDRA_DQ32

DDRA_DM4
DDRA_DQ39

DDRA_DQ34
DDRA_DQ45

DDRA_DQ40
DDRA_DM5

DDRA_DQ42
DDRA_DQ43

DDRA_DQ49
DDRA_DQ48

RP117

1 4
2 3

56_0404_4P2R_5%

RP114

1 4
2 3

56_0404_4P2R_5%

RP111

1 4
2 3

56_0404_4P2R_5%

RP108

1 4
2 3

56_0404_4P2R_5%

RP105

1 4
2 3

56_0404_4P2R_5%

RP101

1 4
2 3

56_0404_4P2R_5%

RP98

1 4
2 3

56_0404_4P2R_5%

RP95

1 4
2 3

56_0404_4P2R_5%

RP92

1 4
2 3

56_0404_4P2R_5%

RP89

1 4
2 3

56_0404_4P2R_5%

RP25

1 4
2 3

56_0404_4P2R_5%

RP23

1 4
2 3

56_0404_4P2R_5%

RP21

1 4
2 3

56_0404_4P2R_5%

RP19

1 4
2 3

56_0404_4P2R_5%

RP17

1 4
2 3

56_0404_4P2R_5%

RP76

1 4
2 3

56_0404_4P2R_5%

RP73

1 4
2 3

56_0404_4P2R_5%

RP70

1 4
2 3

56_0404_4P2R_5%

RP67

1 4
2 3

56_0404_4P2R_5%

RP64

1 4
2 3

56_0404_4P2R_5%

RP61

1 4
2 3

56_0404_4P2R_5%

56_0404_4P2R_5%

RP116

56_0404_4P2R_5%

RP113

56_0404_4P2R_5%

RP110

56_0404_4P2R_5%

RP107

56_0404_4P2R_5%

RP104

56_0404_4P2R_5%

RP103

56_0404_4P2R_5%

RP100

56_0404_4P2R_5%

RP96

56_0404_4P2R_5%

RP93

56_0404_4P2R_5%

RP90

56_0404_4P2R_5%

RP88

56_0404_4P2R_5%

RP85

56_0404_4P2R_5%

RP83

56_0404_4P2R_5%

RP81

56_0404_4P2R_5%

RP79

56_0404_4P2R_5%

RP78

56_0404_4P2R_5%

RP75

56_0404_4P2R_5%

RP71

56_0404_4P2R_5%

RP68

56_0404_4P2R_5%

RP65

56_0404_4P2R_5%

RP63

14
23

14
23

14
23

14
23

14
23

14
23

14
23

14
23

14
23

14
23

14
23

14
23

14
23

14
23

14
23

14
23

14
23

14
23

14
23

14
23

14
23

DDRA_DQ1
DDRA_DQ5

DDRA_DQS0
DDRA_DQ7

DDRA_DQ3
DDRA_DQ13

DDRA_DQ9
DDRA_DQS1

DDRA_DQ15
DDRA_DQ11

DDRA_DQ16
DDRA_DQ20

DDRA_DQS2
DDRA_DQ18

DDRA_DQ22
DDRA_DQ25

DDRA_DQ29
DDRA_DQS3

DDRA_DQ27
DDRA_DQ30

DDRB_SMA12
DDRB_SMA9

DDRB_SMA7
DDRB_SMA5

DDRB_SMA3
DDRB_SMA1

DDRB_SBS0
DDRB_SWE#

DDRB_SCS#0
DDRB_SMA13

DDRA_DQ36
DDRA_DQ33

DDRA_DQS4
DDRA_DQ38

DDRA_DQ35
DDRA_DQ41

DDRA_DQ44
DDRA_DQS5

DDRA_DQ46
DDRA_DQ47

DDRA_DQ52
DDRA_DQ53

DDRB_SMA10
DDRB_CKE1
DDRB_CKE0

DDRA_DM6
DDRA_DQ55

DDRA_DQ51
DDRA_DQ61

DDRA_DQ58
DDRA_DM7

DDRA_DQ63
DDRA_DQ59

DDRA_DQS6
DDRA_DQ54

DDRA_DQ50
DDRA_DQ60

DDRA_DQ56
DDRA_DQS7

DDRA_DQ57
DDRA_DQ62

DDRA_DQ[0..63]
DDRA_DM[0..7]
DDRA_DQS[0..7]
DDRB_SMA[0..13]

DDRB_CLK16
DDRB_CLK1#6

DDRB_CKE16

DDRB_SBS08
DDRB_SWE#8
DDRB_SCS#06 DDRB_SCS#1 6

D_CK_SDATA11,14
D_CK_SCLK11,14

DDRA_DQ1
DDRA_DQ5

DDRA_DQS0
DDRA_DQ7

DDRA_DQ3
DDRA_DQ13

DDRA_DQ9
DDRA_DQS1

DDRA_DQ15
DDRA_DQ11

DDRA_DQ16
DDRA_DQ20

DDRA_DQS2
DDRA_DQ18

DDRA_DQ22
DDRA_DQ25

DDRA_DQ29
DDRA_DQS3

DDRA_DQ27
DDRA_DQ30

DDRB_CKE1
DDRB_SMA12

DDRB_SMA9
DDRB_SMA7

DDRB_SMA5
DDRB_SMA3
DDRB_SMA1

DDRB_SMA10
DDRB_SBS0
DDRB_SWE#

DDRB_SMA13
DDRA_DQ36

DDRA_DQ33
DDRA_DQS4

DDRA_DQ38
DDRA_DQ35

DDRA_DQ41
DDRA_DQ44

DDRA_DQS5
DDRA_DQ46

DDRA_DQ47

DDRA_DQ52
DDRA_DQ53

DDRA_DQS6
DDRA_DQ54

DDRA_DQ50
DDRA_DQ60

DDRA_DQ56
DDRA_DQS7

DDRA_DQ57
DDRA_DQ62

D_CK_SDATA
D_CK_SCLK

+3VS

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITT EN CON SENT O F COMPAL ELECTRONICS, INC.

3

JP12

1

VREF

3

VSS

5

DQ0

7

DQ1

9

VDD

11

DQS0

13

DQ2

15

VSS

17

DQ3

19

DQ8

21

VDD

23

DQ9

25

DQS1

27

VSS

29

DQ10

31

DQ11

33

VDD

35

CK0

37

CK0#

39

VSS

41

DQ16

43

DQ17

45

VDD

47

DQS2

49

DQ18

51

VSS

53

DQ19

55

DQ24

57

VDD

59

DQ25

61

DQS3

63

VSS

65

DQ26

67

DQ27

69

VDD

71

CB0

73

CB1

75

VSS

77

DQS8

79

CB2

81

VDD

83

CB3

85

DU

87

VSS

89

CK2

91

CK2#

93

VDD

95

CKE1

97

DU/A13

99

A12

101

A9

103

VSS

105

A7

107

A5

109

A3

111

A1

113

VDD

115

A10/AP

117

BA0

119

WE#

121

S0#

123

DU

125

VSS

127

DQ32

129

DQ33

131

VDD

133

DQS4

135

DQ34

137

VSS

139

DQ35

141

DQ40

143

VDD

145

DQ41

147

DQS5

149

VSS

151

DQ42

153

DQ43

155

VDD

157

VDD

159

VSS

161

VSS

163

DQ48

165

DQ49

167

VDD

169

DQS6

171

DQ50

173

VSS

175

DQ51

177

DQ56

179

VDD

181

DQ57

183

DQS7

185

VSS

187

DQ58

189

DQ59

191

VDD

193

SDA

195

SCL

197

VDD_SPD

199

VDD_ID

DU/RESET#

AMP_1565917-1

Compal Secret Data

Deciphered Date

VREF

VSS
DQ4
DQ5
VDD
DM0
DQ6
VSS
DQ7

DQ12

VDD

DQ13

DM1

VSS
DQ14
DQ15

VDD

VDD

VSS

VSS

DQ20
DQ21

VDD

DM2
DQ22

VSS
DQ23
DQ28

VDD
DQ29

DM3

VSS
DQ30
DQ31

VDD

CB4

CB5

VSS

DM8

CB6

VDD

CB7

VSS

VSS

VDD

VDD

CKE0

DU/BA2

VSS

VDD

BA1

RAS#
CAS#

VSS
DQ36
DQ37

VDD

DM4
DQ38

VSS
DQ39
DQ44

VDD
DQ45

DM5

VSS
DQ46
DQ47

VDD
CK1#

CK1

VSS
DQ52
DQ53

VDD

DM6
DQ54

VSS
DQ55
DQ60

VDD
DQ61

DM7

VSS
DQ62
DQ63

VDD

SA0

SA1

SA2

A11

A8
A6

A4
A2
A0

S1#

DU

DU

+2.5V +DIMM_VREF

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200

DDRA_DQ0
DDRA_DQ4

DDRA_DM0
DDRA_DQ6

DDRA_DQ2
DDRA_DQ8

DDRA_DQ12
DDRA_DM1

DDRA_DQ14
DDRA_DQ10

DDRA_DQ17
DDRA_DQ21

DDRA_DM2
DDRA_DQ19

DDRA_DQ23
DDRA_DQ24

DDRA_DQ28
DDRA_DM3

DDRA_DQ26
DDRA_DQ31

DDRB_CKE0
DDRB_SMA11

DDRB_SMA8
DDRB_SMA6

DDRB_SMA4
DDRB_SMA2
DDRB_SMA0

DDRB_SBS1
DDRB_SRAS#
DDRB_SCAS#
DDRB_SCS#1DDRB_SCS#0

DDRA_DQ37
DDRA_DQ32

DDRA_DM4
DDRA_DQ39

DDRA_DQ34
DDRA_DQ45

DDRA_DQ40
DDRA_DM5

DDRA_DQ42
DDRA_DQ43

DDRA_DQ49
DDRA_DQ48

DDRA_DM6
DDRA_DQ55

DDRA_DQ51
DDRA_DQ61

DDRA_DQ58
DDRA_DM7

DDRA_DQ63
DDRA_DQ59

2006/03/012005/03/01

2

1

C263

0.1U_0402_16V4Z

2

DDRB_CKE0 6

DDRB_SBS1 8
DDRB_SRAS# 8
DDRB_SCAS# 8

DDRB_CLK2# 6
DDRB_CLK2 6

+3VS

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

DDR-SODIMM1

, 03, 2005

四三月

EAL30 LA-2691

1

星期

12 52

1.0

of

A

B

C

D

E

Layout note :

Distribute as close as possible
to DDR-SODIMM.

1 1

+2.5V

1

2

1

2

C110

0.1U_0402_16V4Z

C705

0.1U_0402_16V4Z

1

C119

0.1U_0402_16V4Z

2

1

C762

0.1U_0402_16V4Z

2

1

C123

0.1U_0402_16V4Z

2

1

C783

0.1U_0402_16V4Z

2

1

C216

0.1U_0402_16V4Z

2

1

C795

0.1U_0402_16V4Z

2

1

C230

0.1U_0402_16V4Z

2

+2.5V+2.5V

1

+

C684
150U_D2_6.3VM

2

1

C248

0.1U_0402_16V4Z

2

1

+

C799
150U_D2_6.3VM

2

1

C324

0.1U_0402_16V4Z

2

1

C680

0.1U_0402_16V4Z

2

1

C683

0.1U_0402_16V4Z

2

2 2

3 3

4 4

Layout note :

Place one cap close to every 2 pull up resistors termination to
+1.25V

+1.25VS

1

2

+1.25VS

1

2

+1.25VS

1

2

+1.25VS

1

2

+1.25VS

1

2

C737

0.1U_0402_16V4Z

C717

0.1U_0402_16V4Z

C767

0.1U_0402_16V4Z

C701

0.1U_0402_16V4Z

C782

0.1U_0402_16V4Z

1

C695

0.1U_0402_16V4Z

2

1

C721

0.1U_0402_16V4Z

2

1

C771

0.1U_0402_16V4Z

2

1

C720

0.1U_0402_16V4Z

2

1

C797

0.1U_0402_16V4Z

2

1

C697

0.1U_0402_16V4Z

2

1

C724

0.1U_0402_16V4Z

2

1

C780

0.1U_0402_16V4Z

2

1

C723

0.1U_0402_16V4Z

2

1

C808

0.1U_0402_16V4Z

2

1

C183

0.1U_0402_16V4Z

2

1

C734

0.1U_0402_16V4Z

2

1

C768

0.1U_0402_16V4Z

2

1

C725

0.1U_0402_16V4Z

2

1

C814

0.1U_0402_16V4Z

2

1

C191

0.1U_0402_16V4Z

2

1

C741

0.1U_0402_16V4Z

2

1

C798

0.1U_0402_16V4Z

2

1

C731

0.1U_0402_16V4Z

2

1

C818

0.1U_0402_16V4Z

2

1

C700

0.1U_0402_16V4Z

2

1

C746

0.1U_0402_16V4Z

2

1

C811

0.1U_0402_16V4Z

2

1

C712

0.1U_0402_16V4Z

2

1

C169

0.1U_0402_16V4Z

2

1

C703

0.1U_0402_16V4Z

2

1

C203

0.1U_0402_16V4Z

2

1

C816

0.1U_0402_16V4Z

2

1

C744

0.1U_0402_16V4Z

2

1

C174

0.1U_0402_16V4Z

2

1

C711

0.1U_0402_16V4Z

2

1

C763

0.1U_0402_16V4Z

2

1

C823

0.1U_0402_16V4Z

2

1

C772

0.1U_0402_16V4Z

2

1

C150

0.1U_0402_16V4Z

2

+1.25VS

1

2

C199

0.1U_0402_16V4Z

1

C685

0.1U_0402_16V4Z

2

1

C696

0.1U_0402_16V4Z

2

1

C698

0.1U_0402_16V4Z

2

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

Compal Secret Data

Deciphered Date

2006/03/012005/03/01

D

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

DDR SODIMM Decoupling

EAL30 LA-2691

星期四 三月

, 03, 2005

E

of

13 52

1.0

A

B

C

D

E

F

G

H

change 0 ohm

L6

+CLK_VDD48

FSC FSB FSA CPU

CLKSEL0 CLKSEL1 CLKSEL2

0

1 1

0
0

+3VS

1 2

R499 10K_0402_5%

1 2

R508 10K_0402_5%

1 2

R101 10K_0402_5%

1 2

R502 10K_0402_5%

2 2

3 3

4 4

CLKSEL0

R94

4.7K_0402_5%

1 2

1 2

R90
0_0402_5%@

CLKSEL2

CLK_PCI0

CLK_PCI2

CLK_PCI1

CK_SCLK25

CK_SDATA25

+1.05VS +1.05VS

1 2

0
1
1

R92

1K_0402_5%@
R85

0_0402_5%

1 2

R86
0_0402_5%

CLK_ICH_48M25
CLK_SD_48M31

CLK_14M_CODEC36

11
1
1
00

+3VS

2

1 3

D

+3VS

2

1 3

D

12

SRC

MHz

100
133
166
200

C716

33P_0402_50V8J

33P_0402_50V8J

CLK_PCI_LAN29
CLK_PCI_MINI34
CLK_PCI_SIO35
CLK_PCI_PCM31
CLK_PCI_LPC39

CLK_PCI_ICH23

D_CK_SCLK11,12

D_CK_SDATA11,12

R97

4.7K_0402_5%

G

1 2

D_CK_SCLK

S

Q5
2N7002_SOT23

R103

4.7K_0402_5%

G

1 2

D_CK_SDATA

S

Q7
2N7002_SOT23

MCH_CLKSEL0 6 MCH_CLKSEL1 6

CPU_BSEL0 5

PCI

MHz

MHz

100 33.3
100

33.3

100

33.3

100

33.3

Y6

14.318MHZ_16PF_DSX840GA

1 2

C713

1 2

12

CLK_ICH_48M

CLK_SD_48M

CLK_PCI_LAN CLK_PCI5
CLK_PCI_MINI

CLK_PCI_PCM CLK_PCI2

CLK_PCI_ICH
D_CK_SCLK

D_CK_SDATA

+3VS

+3VS

CLKSEL1

1

C117

2

2.2U_0603_6.3V6K

+CLK_VDD2

R498 12_0402_5%

1 2

R497 12_0402_5%5IN1@

1 2

R800 33_0402_5%

1 2

1 2

R520 33_0402_5%

1 2

R521 33_0402_5%

1 2

R522 33_0402_5%

1 2

R515 33_0402_5%

1 2

R501 33_0402_5%

1 2

R507 33_0402_5%

R93

4.7K_0402_5%

1 2

1 2

R96
0_0402_5%@

1

C115

2

0.047U_0402_16V7K

+CLK_VDD1

+CLK_VDD1

+CLK_VDDREF

1 2

R100 1_0402_5%

+CLK_VDD48

1 2

R99 2.2_0402_5%

R461 475_0402_1%

1 2

R91

1K_0402_5%@
R95

0_0402_5%

1 2

1 2

R89
0_0402_5%

CLK_X1
CLK_X2

CLKSEL2
CLKSEL0

CLKSEL1

CLK_PCI4
CLK_PCI3CLK_PCI_SIO

CLK_PCI1CLK_PCI_LPC

CLK_PCI0

CLKIREF

12

15mil
15mil

15mil

CPU_BSEL1 5

+CLK_VDDREF

1

C118

0.047U_0402_16V7K

2

U40

21

VDDPCIEX_0

28

VDDPCIEX_1

34

VDDPCIEX_2

1

VDDPCI_0

7

VDDPCI_1

42

VDDCPU

48

VDDREF

11

VDD48

50

X1

49

X2

12

FS_A/USB_48MHz

53

REF1/FSLC/TEST_SEL

16

FSLB/TEST_MODE

5

PCICLK5

4

PCICLK4

3

PCICLK3

56

PCICLK2/REQ_SEL

9

SELPCIEX_LCDCLK#/PCICLK_F1

8

ITP_EN/PCICLK_F0

46

SCLK

47

SDATA

39

IREF

13

GND_0

29

GND_1

2

GND_2

45

GND_3

51

GND_4

6

GND_5

ICS954226AGT_TSSOP56

Security Classification

CPUCLKT2_ITP/PCIEXT6

CPUCLKC2_ITP/PCIEXC6

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

C

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITT EN CON SENT O F COMPAL ELECTRONICS, INC.

D

KC FBM-L11-201209-221LMAT_0805

1 2

+3VS

VDDA

GNDA

PCI/SRC_STOP#

CPU_STOP#

CPUCLKT1
CPUCLKC1

CPUCLKT0
CPUCLKC0

PEREQ1#/PCIEXT5

PEREQ2#/PCIEXC5

PCIEXT4
PCIEXC4

SATACLKT
SATACLKC

PCIEXT3
PCIEXC3

PCIEXT2
PCIEXC2

PCIEXT1
PCIEXC1

LCDCLK_SS/PCIEX0T

LCDCLK_SS/PCIEX0C

DOTT_96MHz
DOTC_96MHz

VTT_PWRGD#/PD

REF0

37
38

55
54

41
40

44
43

36
35

33
32

31
30

26
27

24
25

22
23

19
20

17
18

14
15

10
52

1

C107

2.2U_0603_6.3V6K

2

STP_PCI#
STP_CPU#

CLK_CPU1
CLK_CPU1#

CLK_CPU0
CLK_CPU0#

1

C116

0.047U_0402_16V7K

2

+CLK_VCCA

40mil

1

C111

2

2.2U_0603_6.3V6K

R479 33_0402_5%
R472 33_0402_5%

R493 33_0402_5%
R489 33_0402_5%

1

2

1 2
1 2

1 2
1 2

1

2

1 2

R88

2.2_0402_5%

C108

0.047U_0402_16V7K

PM_STP_PCI# 25
PM_STP_CPU# 25,50

CLK_MCH_BCLK
CLK_MCH_BCLK#

CLK_CPU_BCLK
CLK_CPU_BCLK#

delete ITP clock

delete pci E clock for Lan

CLK_SRC4

R443 33_0402_5%

CLK_SRC4#

R440 33_0402_5%

CLK_SRC3

R453 33_0402_5%

CLK_SRC3#

R445 33_0402_5%

CLK_SRC2

R463 33_0402_5%

CLK_SRC2#

R457 33_0402_5%

CLK_SRC1

R476 33_0402_5%

CLK_SRC1#

R468 33_0402_5%

CLK_SRC0

R486 33_0402_5%

CLK_SRC0#

R481 33_0402_5%

CLK_DOT

R495 33_0402_5%

CLK_DOT#

R490 33_0402_5%

CLK_REF

1 2

R500 12_0402_5%

1 2

R505 12_0402_5%

Compal Secret Data

E

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

Deciphered Date

1.0

CLK_14M_SIO

CLK_ICH_14M

CLK_PCIE_SATA
CLK_PCIE_SATA#

CLK_MCH_3GPLL
CLK_MCH_3GPLL#

CLK_PCIE_VGA
CLK_PCIE_VGA#

CLK_PCIE_ICH
CLK_PCIE_ICH#

CLK_DREF_SSC
CLK_DREF_SSC#

CLK_DREF_96M
CLK_DREF_96M#

C109

0.047U_0402_16V7K

+3VS

F

40mil

1

C105

0.047U_0402_16V7K

2

+3VS

1 2

2006/03/012005/03/01

change 0 ohm

L28
KC FBM-L11-201209-221LMAT_0805

1 2

CLK_MCH_BCLK 6
CLK_MCH_BCLK# 6

CLK_CPU_BCLK 4
CLK_CPU_BCLK# 4

CLK_PCIE_SATA 24
CLK_PCIE_SATA# 24

CLK_MCH_3GPLL 7
CLK_MCH_3GPLL# 7

CLK_PCIE_VGA 15
CLK_PCIE_VGA# 15

CLK_PCIE_ICH 25
CLK_PCIE_ICH# 25

CLK_DREF_SSC 6
CLK_DREF_SSC# 6

CLK_DREF_96M 6
CLK_DREF_96M# 6

+CLK_VDD1

R98 10K_0402_5%

VTT_POWERGD#

CLK_14M_SIO 35

CLK_ICH_14M 25

+CLK_VDD1

1

C106

0.047U_0402_16V7K

2

1

C122

2

2.2U_0603_6.3V6K

Clock Generator

+CLK_VDD2

40mil

1

C124

2

0.047U_0402_16V7K

CLK_MCH_BCLK
CLK_MCH_BCLK#
CLK_CPU_BCLK
CLK_CPU_BCLK#

1 2

R478 49.9_0402_1%

1 2

R471 49.9_0402_1%

1 2

R492 49.9_0402_1%

1 2

R488 49.9_0402_1%

1

C125

2

0.047U_0402_16V7K

delete ITP clock

delete pci E clock for Lan

CLK_PCIE_SATA
CLK_PCIE_SATA#
CLK_MCH_3GPLL
CLK_MCH_3GPLL#
CLK_PCIE_VGA
CLK_PCIE_VGA#
CLK_PCIE_ICH
CLK_PCIE_ICH#
CLK_DREF_SSC
CLK_DREF_SSC#
CLK_DREF_96M
CLK_DREF_96M#

2

G

1 3

D

S

Q6
2N7002_SOT23

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

星期

, 03, 2005

四三月

G

1 2

R444 49.9_0402_1%

1 2

R441 49.9_0402_1%

1 2

R454 49.9_0402_1%

1 2

R446 49.9_0402_1%

1 2

R464 49.9_0402_1%

1 2

R458 49.9_0402_1%

1 2

R477 49.9_0402_1%

1 2

R469 49.9_0402_1%

1 2

R487 49.9_0402_1%

1 2

R482 49.9_0402_1%

1 2

R496 49.9_0402_1%

1 2

R491 49.9_0402_1%

VGATE 6,25,50

Clock Generator
EAL30 LA-2691

of

14 52

H

5

8

D D

C C

100K_0402_5%

B B

R268

PLTRST_VGA#25

PLT_RST#

,31,35,39

A A

1 2

0_0402_5%PM@

R272

1 2

0_0402_5%@

PCIE_GTX_C_MRX_N[0..15]7

PCIE_GTX_C_MRX_P[0..15]7
PCIE_MTX_C_GRX_N[0:15]7
PCIE_MTX_C_GRX_P[0:15]7

PCIE_GTX_C_MRX_P0
PCIE_GTX_C_MRX_N0
PCIE_GTX_C_MRX_P1
PCIE_GTX_C_MRX_N1
PCIE_GTX_C_MRX_P2
PCIE_GTX_C_MRX_N2
PCIE_GTX_C_MRX_P3
PCIE_GTX_C_MRX_N3
PCIE_GTX_C_MRX_P4
PCIE_GTX_C_MRX_N4
PCIE_GTX_C_MRX_P5
PCIE_GTX_C_MRX_N5
PCIE_GTX_C_MRX_P6
PCIE_GTX_C_MRX_N6
PCIE_GTX_C_MRX_P7
PCIE_GTX_C_MRX_N7
PCIE_GTX_C_MRX_P8
PCIE_GTX_C_MRX_N8
PCIE_GTX_C_MRX_P9
PCIE_GTX_C_MRX_N9
PCIE_GTX_C_MRX_P10
PCIE_GTX_C_MRX_N10
PCIE_GTX_C_MRX_P11
PCIE_GTX_C_MRX_N11
PCIE_GTX_C_MRX_P12
PCIE_GTX_C_MRX_N12
PCIE_GTX_C_MRX_P13
PCIE_GTX_C_MRX_N13
PCIE_GTX_C_MRX_P14
PCIE_GTX_C_MRX_N14
PCIE_GTX_C_MRX_P15
PCIE_GTX_C_MRX_N15

12

PM@

R260

Q30

13

D

2

G

S

2N7002_SOT23

PM@

Voltage divider
Reduce Voltage from 3.3V to 1.2V

Q29

2

G

+3VS

12

R261
100K_0402_5%

PM@

13

D

S

OSC_IN

2N7002_SOT23

PM@

C666 0.1U_0402_10V6KPM@
C665 0.1U_0402_10V6KPM@
C644 0.1U_0402_10V6KPM@
C643 0.1U_0402_10V6KPM@
C664 0.1U_0402_10V6KPM@
C663 0.1U_0402_10V6KPM@
C642 0.1U_0402_10V6KPM@
C641 0.1U_0402_10V6KPM@
C662 0.1U_0402_10V6KPM@
C661 0.1U_0402_10V6KPM@
C640 0.1U_0402_10V6KPM@
C639 0.1U_0402_10V6KPM@
C660 0.1U_0402_10V6KPM@
C659 0.1U_0402_10V6KPM@
C638 0.1U_0402_10V6KPM@
C637 0.1U_0402_10V6KPM@
C658 0.1U_0402_10V6KPM@
C657 0.1U_0402_10V6KPM@
C636 0.1U_0402_10V6KPM@
C635 0.1U_0402_10V6KPM@
C656 0.1U_0402_10V6KPM@
C655 0.1U_0402_10V6KPM@
C634 0.1U_0402_10V6KPM@
C633 0.1U_0402_10V6KPM@
C654 0.1U_0402_10V6KPM@
C653 0.1U_0402_10V6KPM@
C646 0.1U_0402_10V6KPM@
C645 0.1U_0402_10V6KPM@
C652 0.1U_0402_10V6KPM@
C651 0.1U_0402_10V6KPM@
C632 0.1U_0402_10V6KPM@
C631 0.1U_0402_10V6KPM@

1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2

+1.2VS

VGA_TV_LUMA22

VGA_TV_CRMA22

R79

1 2

121_0603_1%

PM@

R71

PM@

71.5_0402_1%

+3VS

CLK_PCIE_VGA14
CLK_PCIE_VGA#14

1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2

12

Reserve for M26 test

VGA_CRT_VSYNC

5

4

R258 150_0402_1%PM@

1 2

R259 100_0402_1%PM@

1 2

R262 10K_0402_1%PM@
R263 10K_0402_5%

1 2

1 2

R264 1K_0402_5%
R266 715_0402_1%

PM@

1 2

R269 75_0402_5%

VGA_TV_LUMA

R273150_0402_1% PM @

12

VGA_TV_CRMA

12

R274150_0402_1% PM @

R280 1K_0402_5%

R282 10K_0402_5%PM@

12

R283 10K_0402_5%@

4

PCIE_MTX_C_GRX_P0
PCIE_MTX_C_GRX_N0
PCIE_MTX_C_GRX_P1
PCIE_MTX_C_GRX_N1
PCIE_MTX_C_GRX_P2
PCIE_MTX_C_GRX_N2
PCIE_MTX_C_GRX_P3
PCIE_MTX_C_GRX_N3
PCIE_MTX_C_GRX_P4
PCIE_MTX_C_GRX_N4
PCIE_MTX_C_GRX_P5
PCIE_MTX_C_GRX_N5
PCIE_MTX_C_GRX_P6
PCIE_MTX_C_GRX_N6
PCIE_MTX_C_GRX_P7
PCIE_MTX_C_GRX_N7
PCIE_MTX_C_GRX_P8
PCIE_MTX_C_GRX_N8
PCIE_MTX_C_GRX_P9
PCIE_MTX_C_GRX_N9
PCIE_MTX_C_GRX_P10
PCIE_MTX_C_GRX_N10
PCIE_MTX_C_GRX_P11
PCIE_MTX_C_GRX_N11
PCIE_MTX_C_GRX_P12
PCIE_MTX_C_GRX_N12
PCIE_MTX_C_GRX_P13
PCIE_MTX_C_GRX_N13
PCIE_MTX_C_GRX_P14
PCIE_MTX_C_GRX_N14
PCIE_MTX_C_GRX_P15
PCIE_MTX_C_GRX_N15

PCIE_GTX_MRX_P0

PCIE_GTX_MRX_N0

PCIE_GTX_MRX_P1

PCIE_GTX_MRX_N1

PCIE_GTX_MRX_P2

PCIE_GTX_MRX_N2

PCIE_GTX_MRX_P3

PCIE_GTX_MRX_N3

PCIE_GTX_MRX_P4

PCIE_GTX_MRX_N4

PCIE_GTX_MRX_P5

PCIE_GTX_MRX_N5

PCIE_GTX_MRX_P6

PCIE_GTX_MRX_N6

PCIE_GTX_MRX_P7

PCIE_GTX_MRX_N7

PCIE_GTX_MRX_P8

PCIE_GTX_MRX_N8

PCIE_GTX_MRX_P9

PCIE_GTX_MRX_N9

PCIE_GTX_MRX_P10

PCIE_GTX_MRX_N10

PCIE_GTX_MRX_P11

PCIE_GTX_MRX_N11

PCIE_GTX_MRX_P12

PCIE_GTX_MRX_N12

PCIE_GTX_MRX_P13

PCIE_GTX_MRX_N13

PCIE_GTX_MRX_P14

PCIE_GTX_MRX_N14

PCIE_GTX_MRX_P15

PCIE_GTX_MRX_N15

CLK_PCIE_VGA
CLK_PCIE_VGA#

12

@

R_PLTRST_VGA#

PM@
PM@

12

VGA_TV_LUMA
VGA_TV_CRMA

VGA_COMPS

12

PM@

XTALIN

PM@

12

12

+3VS

R27710K_0402_5%

U6A

AH30

PCIE_RX0P

AG30

PCIE_RX0N

AG29

PCIE_RX1P

AF29

PCIE_RX1N

AE29

PCIE_RX2P

AE30

PCIE_RX2N

AD30

PCIE_RX3P

AD29

PCIE_RX3N

AC29

PCIE_RX4P

AB29

PCIE_RX4N

AB30

PCIE_RX5P

AA30

PCIE_RX5N

AA29

PCIE_RX6P

Y29

PCIE_RX6N

W29

PCIE_RX7P

W30

PCIE_RX7N

V30

PCIE_RX8P

V29

PCIE_RX8N

U29

PCIE_RX9P

T29

PCIE_RX9N

T30

PCIE_RX10P

R30

PCIE_RX10N

R29

PCIE_RX11P

P29

PCIE_RX11N

N29

PCIE_RX12P

N30

PCIE_RX12N

M30

PCIE_RX13P

M29

PCIE_RX13N

L29

PCIE_RX14P

K29

PCIE_RX14N

K30

PCIE_RX15P

J30

PCIE_RX15N

AF26

PCIE_TX0P

AE26

PCIE_TX0N

AC25

PCIE_TX1P

AB25

PCIE_TX1N

AC27

PCIE_TX2P

AB27

PCIE_TX2N

AC26

PCIE_TX3P

AB26

PCIE_TX3N

Y25

PCIE_TX4P

W25

PCIE_TX4N

Y27

PCIE_TX5P

W27

PCIE_TX5N

Y26

PCIE_TX6P

W26

PCIE_TX6N

U25

PCIE_TX7P

T25

PCIE_TX7N

U27

PCIE_TX8P

T27

PCIE_TX8N

U26

PCIE_TX9P

T26

PCIE_TX9N

P25

PCIE_TX10P

N25

PCIE_TX10N

P27

PCIE_TX11P

N27

PCIE_TX11N

P26

PCIE_TX12P

N26

PCIE_TX12N

L25

PCIE_TX13P

K25

PCIE_TX13N

L27

PCIE_TX14P

K27

PCIE_TX14N

L26

PCIE_TX15P

K26

PCIE_TX15N

AF27

PCIE_REFCLKP

AE27

PCIE_REFCLKN

AC23

PCIE_CALRP

AB24

PCIE_CALRN

AB23

PCIE_CALI

AE25

PCIE_TESTIN

AD25

PWRGD

AD24

PWRGD_MASK

AH21

R2SET

AK21

Y_G

AJ22

C_R_PR

AK22

COMP_B_PB

AJ24

H2SYNC

AK24

V2SYNC

AG22

DDC3CLK

AG23

DDC3DATA

AJ23

SSIN

AH24

SSOUT

AH28

XTALIN

AJ29

XTALOUT

AH27

TESTEN

E8

TEST_YCLK

B6

TEST_MCLK

AF25

PLLTEST

AH25

STEREOSYNC

M24P_BGA708 M24@

3

Part 1 of 5

GPIO_PWRCNTL

PCI EXPRESS

DAC2CLK

SS

GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8

GPIO9
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14

GPIO_MEMSSIN

DVOMODE

DVPDATA_0
DVPDATA_1
DVPDATA_2
DVPDATA_3
DVPDATA_4
DVPDATA_5
DVPDATA_6
DVPDATA_7
DVPDATA_8

DVPDATA_9
DVPDATA_10
DVPDATA_11
DVPDATA_12
DVPDATA_13
DVPDATA_14
DPVDATA_15

DVO / EXT TMDS / GPIOTMDSDAC1

DVPDATA_16
DVPDATA_17
DVPDATA_18
DVPDATA_19
DVPDATA_20
DVPDATA_21
DVPDATA_22
DVPDATA_23

DVPCNTL_0

DVPCNTL_1

DVPCNTL_2

DVPCNTL_3

VREFG

TXOUT_L0N

TXOUT_L0P

TXOUT_L1N

TXOUT_L1P

TXOUT_L2N

TXOUT_L2P

TXOUT_L3N

TXOUT_L3P

TXCLK_LN

TXCLK_LP
TXOUT_U0N
TXOUT_U0P
TXOUT_U1N
TXOUT_U1P
TXOUT_U2N

LVDS

TXOUT_U2P
TXOUT_U3N
TXOUT_U3P

TXCLK_UN
TXCLK_UP

DIGON

BLON
TX0M

TX0P

TX1M

TX1P

TX2M

TX2P
TXCM
TXCP

DDC2CLK

DDC2DATA

HPD1

HSYNC
VSYNC

RSET

DDC1DATA

DDC1CLK

GPIO_AUXWIN

DPLUS

DMINUS

THERM

R
G
B

VGA_GPIO1

AH5

VGA_GPIO2

AJ4

VGA_GPIO3

AK4

VGA_GPIO4

AH4

VGA_GPIO5

AF4

VGA_GPIO6

AJ3
AK3
AH3
AJ2
AH2

POWER_SEL(High 3.3V):VDDC=1.05V

AH1

(Low 0V ):VDDC=1.20V

AG3
AG1
AG2

POWER_SEL

AF3
AF2

AE10

MEM_ID0

AH6

MEM_ID1

AJ6

MEM_ID2

AK6
AH7
AK7
AJ7
AH8
AJ8
AH9
AJ9
AK9
AH10
AE6
AG6
AF6
AE7
AF7
AE8
AG8
AF8
AE9
AF9
AG10
AF10

AJ10
AK10
AJ11
AH11

+VREFG

AG4

(15mils)

AH15
AH16
AJ16
AJ17
AJ18
AK18
AJ20
AJ21
AK19
AJ19
AG16
AG17
AF16
AF17
AE18
AE19
AF19
AF20
AG19
AG20

AE12
AG12

R265 10K_0402_5%

AK13
AJ13
AJ14
AJ15
AK15
AK16
AJ12
AK12

AE13
AE14
AF12

AK27
AJ27
AJ26
AJ25
AK25

DAC_RSET

AH26
AG25
AF24
AG24

AF11
AE11

+3VS
+3VS

VGA_GPIO0

AJ5

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITT EN CON SENT O F COMPAL ELECTRONICS, INC.

3

1 2

R243 10K_0402_5%PM@

1 2

R244 10K_0402_5%@

1 2

R245 10K_0402_5%@

1 2

R246 10K_0402_5%@

1 2

R247 10K_0402_5%@

1 2

R248 10K_0402_5%@

1 2

R249 10K_0402_5%@

1 2

R20 10K_0402_5%PM@

R250 10K_0402_5%@

1 2

R251 10K_0402_5%@

1 2

R252 10K_0402_5%@

1 2

R253 4.7K_0402_5%PM@

1 2

R254 4.7K_0402_5%PM@

1 2

R255 10K_0402_5%@

1 2

RESRRVED FOR M24 TEST

1 8
2 7
3 6
4 5

RP36 10K_0804_8P4R_5%

ENVDD

1 2

PM@

VGA_CRT_R
VGA_CRT_G
VGA_CRT_B

VGA_CRT_R
VGA_CRT_G
VGA_CRT_B

R279 499_0402_1%PM@

R281 10K_0402_5%

+3VS

PM@

VGA_TXOUT0- 21
VGA_TXOUT0+ 21
VGA_TXOUT1- 21
VGA_TXOUT1+ 21
VGA_TXOUT2- 21
VGA_TXOUT2+ 21

VGA_TXCLK- 21

VGA_TXCLK+ 21

VGA_TZOUT0- 21

VGA_TZOUT0+ 21

VGA_TZOUT1- 21

VGA_TZOUT1+ 21

VGA_TZOUT2- 21

VGA_TZOUT2+ 21

VGA_TZCLK- 21

VGA_TZCLK+ 21

R267 150_0402_1%
R270 150_0402_1%
R271 150_0402_1%

1 2

12

PM@

VGA_DDC_DATA

R8054.7K_0402_5% PM@

12

VGA_DDC_CLK

R8064.7K_0402_5% PM@

12

Compal Secret Data

Deciphered Date

OSC_SPREAD

VGA_LCD_DATA 21
VGA_LCD_CLK 21

ENVDD 21
ENBKL 7,39

PM@

1 2

PM@

1 2

PM@

1 2

2

+3VS

POWER_SEL 47

+3VS

+3VS

+3VS

Place +VREFG divider Res
and decoupling Cap close
to Ball AG4

VGA_CRT_R 22
VGA_CRT_G 22
VGA_CRT_B 22
VGA_CRT_HSYNC 22
VGA_CRT_VSYNC 22

VGA_DDC_DATA 22
VGA_DDC_CLK 22

If GPIO_AUXWIN not used,
pulled it to GND.

2006/03/012005/03/01

2

+3VS

+VREFG

MEM_ID0

1K_0402_1%

PM@

1

General Straping (VGA Internal PD) 0:Disable, 1:Enable

Full Transmitter Output Swing Power

GPIO0
GPIO1

Transmitter De-emphasis Enable

GPIO(3:2)

00: PCI Express 1.0A mode
01: Kyrene-compatible mode
10: PCI Express 1. 0 mode
11: PCI Express 1.0A mode and short-circuit internal
loopback mode (Rx connected directly to Tx of PHY)

GPIO4

Transmitter Extra Current
PCI-E Lane Reversal Enable

GPIO5

Force chip to go to compliance state quickly
for test purposes

Reduced PLL bandwidth

GPIO6

Vedio Memory Config. (VGA Internal PD) 1.8V only

0
0
1
1
0
0
1
1

MEM_ID2

MEM_ID1

1

1 128MB

1

Default

1

0

1

1

0

0

0

1

0

0

0

1

64MB 0

64MB
128MB
32MB
64MB
32MB
64MB

DEFAULT : 1
DEFAULT : 0
DEFAULT : 00

DEFAULT : 0

DEFAULT : 0

DEFAULT : 0

Size Vendor Chips

8Mx32 Samsung x2
8Mx32 Samsung x4
8Mx32 Hynix x2
8Mx32 Hynix x4
4Mx32 Samsung x2
4Mx32 Samsung x4
4Mx32 Hynix x2
4Mx32 Hynix x4

M22 Core speed MAX 300MHz
M24 Core speed MAX 400MHz

R256

1 2

PM@

1

2

0.1U_0402_16V4Z

PM@

PM@

Keep away from other signal at last 25mils

ATI suggest 100 ohm
Current Value same as EAT10

12

R257

C360

PM@

1K_0402_1%

+3VS

C361

12

12

0.1U_0402_16V4Z

C865

12

10U_0805_10V4Z

Spread spectrum

L19
CHB1608U301_0603

PM@

U22

7

REF

VDD

1

MODOUT

XIN

8

XOUT

NC

2

PD#

VSS

ASM3P1819N-SR_SO8

PM@

Y1

PM@

4

GND

OUT

1

IN

1

2

Title

Size Document Number Rev

Custom

星期

Date: Sheet

GND

27MHz_16PF_6P27000126
C385
16P_0603_50V8J

PM@

Compal Electronics, Inc.

M22P/24P PCIE,LVDS,GPIO,CLK
EAL30 LA-2691

, 03, 2005

四三月

OSC_IN

5

1 2

4

R275 22_0402_5%

3

R276 10K_0402_5%@

6

R278 10K_0402_5%@

3
2

1

PM@

12
12

1

C383
16P_0603_50V8J

2

PM@

OSC_SPREAD

15 52

1.0

of

5

4

3

2

1

MDA[0..63]

D D

C C

B B

A A

DQSA[0..7]
DQMA#[0..7]
MAA[0..13]

MDA0
MDA1
MDA2
MDA3
MDA4
MDA5
MDA6
MDA7
MDA8
MDA9
MDA10
MDA11
MDA12
MDA13
MDA14
MDA15
MDA16
MDA17
MDA18
MDA19
MDA20
MDA21
MDA22
MDA23
MDA24
MDA25
MDA26
MDA27
MDA28
MDA29
MDA30
MDA31
MDA32
MDA33
MDA34
MDA35
MDA36
MDA37
MDA38
MDA39
MDA40
MDA41
MDA42
MDA43
MDA44
MDA45
MDA46
MDA47
MDA48
MDA49
MDA50
MDA51
MDA52
MDA53
MDA54
MDA55
MDA56
MDA57
MDA58
MDA59
MDA60
MDA61
MDA62
MDA63

MDA[0..63] 19
DQSA[0..7] 19
DQMA#[0..7] 19
MAA[0..13] 19

U6B

H28

DQA0

H29

DQA1

J28

DQA2

J29

DQA3

J26

DQA4

H25

DQA5

H26

DQA6

G26

DQA7

G30

DQA8

D29

DQA9

D28

DQA10

E28

DQA11

E29

DQA12

G29

DQA13

G28

DQA14

F28

DQA15

G25

DQA16

F26

DQA17

E26

DQA18

F25

DQA19

E24

DQA20

F23

DQA21

E23

DQA22

D22

DQA23

B29

DQA24

C29

DQA25

C25

DQA26

C27

DQA27

B28

DQA28

B25

DQA29

C26

DQA30

B26

DQA31

F17

DQA32

E17

DQA33

D16

DQA34

F16

DQA35

E15

DQA36

F14

DQA37

E14

DQA38

F13

DQA39

C17

DQA40

B18

DQA41

B17

DQA42

B15

DQA43

C13

DQA44

B14

DQA45

C14

DQA46

C16

DQA47

A13

DQA48

A12

DQA49

C12

DQA50

B12

DQA51

C10

DQA52

C9

DQA53

B9

DQA54

B10

DQA55

E13

DQA56

E12

DQA57

E10

DQA58

F12

DQA59

F11

DQA60

E9

DQA61

F9

DQA62

F8

DQA63

M24P_BGA708

M24@

MDB[0..63]
DQSB[0..7]
DQMB#[0..7]
MAB[0..13]

Part 2 of 5

MEMORY INTERFACE A

MAA0
MAA1
MAA2
MAA3
MAA4
MAA5
MAA6
MAA7
MAA8

MAA9
MAA10
MAA11
MAA12
MAA13
MAA14

DQMA#0
DQMA#1
DQMA#2
DQMA#3
DQMA#4
DQMA#5
DQMA#6
DQMA#7

QSA0

QSA1

QSA2

QSA3

QSA4

QSA5

QSA6

QSA7
RASA#
CASA#

WEA#

CSA0#
CSA1#

CKEA

CLKA0

CLKA0#

CLKA1

CLKA1#

MVREFD
MVREFS

DIMA_0
DIMA_1

MDB[0..63] 20
DQSB[0..7] 20
DQMB#[0..7] 20
MAB[0..13] 20

MAA0

E22

MAA1

B22

MAA2

B23

MAA3

B24

MAA4

C23

MAA5

C22

MAA6

F22

MAA7

F21

MAA8

C21

MAA9

A24

MAA10

C24

MAA11

A25

MAA12

E21

MAA13

B20
C19

DQMA#0

J25

DQMA#1

F29

DQMA#2

E25

DQMA#3

A27

DQMA#4

F15

DQMA#5

C15

DQMA#6

C11

DQMA#7

E11

DQSA0

J27

DQSA1

F30

DQSA2

F24

DQSA3

B27

DQSA4

E16

DQSA5

B16

DQSA6

B11

DQSA7

F10

MRASA#

A19

MCASA#

E18

MWEA#

E19

MCSA0#

E20
F20

MCKEA

B19

MCLKA0

B21

MCLKA0#

C20

MCLKA1

C18

MCLKA1#

A18

(15mils)

+MVREFD

B7
B8

D30
B13

(15mils) (15mils)

0.1U_0402_16V4Z

+MVREFS

PM@

C528

(15mils)

1

2

Memory speed MAX200MHz

MRASA# 19
MCASA# 19
MWEA# 19
MCSA0# 19

MCKEA 19

MCLKA0 19
MCLKA0# 19

MCLKA1 19
MCLKA1# 19

+1.8VS +1.8VS

12

PM@

R410
100_0402_1%

12

R413

PM@

100_0402_1%

+MVREFD+MVREFS

C500

PM@

0.1U_0402_16V4Z

R405

1 2

R403

+1.8VS

12

MEMVMODE0 MEMVMODE1

NC

R409

47_0402_1%

Default

MRASB# 20
MCASB# 20
MWEB# 20
MCSB0# 20

MCKEB 20
MCLKB0 20

MCLKB0# 20
MCLKB1 20

MCLKB1# 20

PM@

1 2

MEMVMODE1

MEMVMODE0

PM@

4.7K_0402_5%

PM@

4.7K_0402_5%

Pull-high

MAB0

N5

MAB1

M1

MAB2

M3

MAB3

L3

MAB4

L2

MAB5

M2

MAB6

M5

MAB7

P6

MAB8

N3

MAB9

K2

MAB10

K3

MAB11

J2

MAB12

P5

MAB13

P3
P2

DQMB#0

E6

DQMB#1

B2

DQMB#2

J5

DQMB#3

G3

DQMB#4

W6

DQMB#5

W2

DQMB#6

AC6

DQMB#7

AD2

DQSB0

F6

DQSB1

B3

DQSB2

K6

DQSB3

G1

DQSB4

V5

DQSB5

W1

DQSB6

AC5

DQSB7

AD1

MRASB#

R2

MCASB#

T5

MWEB#

T6

MCSB0#

R5
R6

MCKEB

R3

MCLKB0

N1

MCLKB0#

N2

MCLKB1

T2

MCLKB1#

T3

E3
AA3

AF5

MEMVMODE0

C6

MEMVMODE1

C7

MEMTEST

C8

(15mil)

change to 240 ohm when use M26

MAB0
MAB1
MAB2
MAB3
MAB4
MAB5
MAB6
MAB7
MAB8

MAB9
MAB10
MAB11
MAB12
MAB13
MAB14

DQMB#0
DQMB#1
DQMB#2
DQMB#3
DQMB#4
DQMB#5
DQMB#6
DQMB#7

QSB0

QSB1

QSB2

QSB3

QSB4

QSB5

QSB6

QSB7
RASB#
CASB#

WEB#
CSB0#
CSB1#

CKEB
CLKB0

CLKB0#

CLKB1

CLKB1#

DIMB_0
DIMB_1

ROMCS#

MEMVMODE_0
MEMVMODE_1

MEMTEST

Pull-low

NC

M22/24(1.8V VRAM)

M26(1.8V VRAM)

AD6
AD5

AC2
AC3
AD3

D7

F7

E7
G6
G5

F5

E5
C4

B5
C5

A4

B4
C2
D3
D1
D2
G4
H6
H5

J6

K5

K4

L6

L5
G2

F3
H2

E2

F2

J3

F1
H3
U6
U5
U3

V6

W5
W4

Y6

Y5
U2

V2

V1

V3

W3

Y2

Y3

AA2
AA6
AA5
AB6
AB5

AE5
AE4
AB2
AB3

AE1
AE2
AE3

U6C

DQB0
DQB1
DQB2
DQB3
DQB4
DQB5
DQB6
DQB7
DQB8
DQB9
DQB10
DQB11
DQB12
DQB13
DQB14
DQB15
DQB16
DQB17
DQB18
DQB19
DQB20
DQB21
DQB22
DQB23
DQB24
DQB25
DQB26
DQB27
DQB28
DQB29
DQB30
DQB31
DQB32
DQB33
DQB34
DQB35
DQB36
DQB37
DQB38
DQB39
DQB40
DQB41
DQB42
DQB43
DQB44
DQB45
DQB46
DQB47
DQB48
DQB49
DQB50
DQB51
DQB52
DQB53
DQB54
DQB55
DQB56
DQB57
DQB58
DQB59
DQB60
DQB61
DQB62

DQB63

M24P_BGA708

M24@

Part 3 of 5

MEMORY INTERFACE B

MDB0
MDB1
MDB2
MDB3
MDB4
MDB5
MDB6
MDB7
MDB8
MDB9
MDB10
MDB11
MDB12
MDB13
MDB14
MDB15
MDB16
MDB17
MDB18
MDB19
MDB20
MDB21
MDB22
MDB23
MDB24
MDB25
MDB26
MDB27
MDB28
MDB29
MDB30
MDB31
MDB32
MDB33
MDB34
MDB35
MDB36
MDB37
MDB38
MDB39
MDB40
MDB41
MDB42
MDB43
MDB44
MDB45
MDB46
MDB47
MDB48
MDB49
MDB50
MDB51
MDB52
MDB53
MDB54
MDB55
MDB56
MDB57
MDB58
MDB59
MDB60
MDB61
MDB62
MDB63

12

R408

PM@

100_0402_1%

12

1

R404
100_0402_1%PM@

2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

Custom

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITT EN CON SENT O F COMPAL ELECTRONICS, INC.

3

Compal Secret Data

Deciphered Date

2006/03/012005/03/01

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

M22P/24P Memory Interface
EAL30 LA-2691

星期

, 03, 2005

四三月

1.0

of

16 52

1