Compal LA-2601 Dunlin, TravelMate 4150, TravelMate 4650 Schematic
A
B
C
D
E
Page Index
===============
P01-Cover Page
P02-Block Diagram
P03-Notes List
P04-Dothan(1/2)
1 1
Dunlin LA-2601 Schematics Document
2 2
Intel Dothan / Alviso GM(PM) / DDR-1(DDR-2) / ICH6-M
(NV43/44M)
2004 / 11 / 15 (For A-TEST)
Rev:0.1
3 3
4 4
P05-Dothan(2/2)
P06-Alviso HOST(1/5)
P07-Alviso DDR(2/5)
P08-Alviso PCI-E(3/5)
P09-Alviso POWER(4/5)
P10-Alviso POWER(5/5)
P11-DDRI-SODIMM0
P12-DDRI-SODIMM1
P13-DDR Decoupling
P14-Clock Generator
P15-CRT Conn.
P16-VGA / LCD Conn.
P17-ICH6(1/4)_HUB,PCI,HOST
P18-ICH6(2/4)_CPU,AC97,IDE,LPC
P19-ICH6(3/4)_USB,PM,LAN,GPIO
P20-ICH6(4/4)_POWER&GND
P21-HDD/CDROM
P22-DVI / TV_Out Conn
P23-PCMCIA ENE CB1410 & CB714
P24-PCMCIA SOCKET
P25-TI 1394A TSB43AB21A
P26-LAN BCM5788M
P27-LAN Magnetic & RJ45/RJ11
P28-Mimi-PCI Slot
P29-AC97 Codec_ALC250D
P30-Audio Line in Switch
P31-AMP & Audio Jack
P32-Super IO SMC217
P33-ENE-KB910
P34-MDC / BT / KBD / TP Conn.
P35-BIOS & I/O Port & SATA HDD
P36-RJ11/LID Switch / Fan / FIR
P37-USB2.0 Conn
P38-Docking Conn.
P39-PWR_OK / RTC
P40-DC INTERFACE
P41-Screws
P42-PWR-DCIN / Precharge
P43-PWR-Charger
P44-PWR-Battery Select
P45-PWR-3V/5V/12V
P46-PWR-GMCH_CORE/1.8V/0.9V
P47-PWR-1.5V/2.5V
P48-PWR-CPU_CORE
P49-PWR-OTP
P50-PWR-PIR
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SE CRET INFO RMATI ON. THIS SHEET MAY NO T BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
D
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
Cover Sheet
EDL00 LA-2601
151Tuesday, November 16, 2004
E
0.1
of
A
B
C
D
E
Compal confidential
File Name : LA-2601
CRT/TV-OUT
1 1
page 15
H_A#(3..31)
Intel Dothan CPU
page 4,5
FSB
400 / 533 Mhz
H_D#(0..63)
Thermal Se nsor
ADM1032ARM
page 4
Clock Generator
ICS954226AGT
page 14
MV43 / MV44
VGA Board
page 16
Intel Alviso GM(PM)
DDR-2
DDR-SO-DIMM X2
BANK 0, 1, 2, 3
page 11,12,13
PCBGA 1257
LCD CONN
page 16
page 6,7,8,9,10
Signal Channel DDR-1
Two Channel DDR-2
DMI
2 2
Intel ICH6-M
PCI-E BUS
PCI BUS
Mini PCI
socket
page 28
3 3
BROADCOM
BCM57 88M
BCM4401
page 26
RJ45 CONN
page 27
ENE Controller
CB714
5in1 CardReader
Slot 0
page 24
Slot
page 23,24
page 24
1394 Controller
TSB43AB21
page 25
1394
Conn.
page 25
LPC BUS
Power On/Off CKT.
page 39
SMsC LPC47N217
DC/DC Interface CKT.
page 40
Power Circuit DC/DC
4 4
page 42~49
A
RTC CKT.
page 39
Power OK CKT.
page 39
Parellel Port
page 38
B
page 32
Serial Port
DOCKING CONNDOCKING CONN
page 38
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SE CRET INFO RMATI ON. THIS SHEET MAY NO T BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
mBGA-609
page 17,18,19,20
ENE KB910/910L
Touch Pad
CONN.
C
page 34
USB 2.0
USB 2.0
AC-LINK
SATA
PATA
page 33
USB conn x 4
Audio CKT
ALC250-D
PATA HDD
SATA HDD
Int. KBD
page 34
BIOS
page 35
BT Conn
page 29
MODULE
Connector
D
page 37
page 34
conn
page 21
page 21
RJ11 CONN
page 36
AMP & Audio Jack
page 31
Docking CONN.
*RJ-11 / 45(LED*2)
*COMPOSITE Video Out
*TVOUT
*LINE IN / OUT
*PS/2
*Print port
*1394
*USB
*DC JACK
page 39
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
Block Diagrams
EDL00 LA-2601
251Monday, November 15, 2004
E
of
0.1
A
Voltage Rails
Power Plane Description
1 1
2 2
VIN
B+
+CPU_CORE
+1.05VS
+DDRVTT 1.25V switched power rail for DDR terminator
+1.5VALW 1.5V always on power rail
+1.5VS
+1.8VS 1.8V switched power rail
+DDRVCC
+2.5VS
+3VALW
+3V
+3VS
+5VALW
+5VS
+5VMO D 5 V sw i tc he d po we r rail for Module Bay
+12VALW 12V always on power rail
+RTC V C C RTC power
Adapter power supply (19V)
AC or batte ry power rail for power circuit.
Core voltage for CPU
1.05V switched power rail
1.5V switched power rail
2.5V power rail for DDR
2.5V switched power rail
3.3V always on power rail
3.3V power rail
3.3V switched power rail
5V always on power rail
5V switched power rail
B
S1 S3 S5
N/A N/A N/A
ON OFF
ON OFF
ON OFF OF F
ON
ON OFF OF F
ON OFF OF F
ON
ON
ON
ON
ON
ON
ON ONON
N/AN/AN/A
OFF
OFF
ON*ON
OFF
ON
OFF
OFF
ON ON*
OFF
ON
OFF
OFF
ON
ON*
OFF
OFFON
OFF OFFON
ONON ON*
C
STATE
Full ON
S1(Power On Suspend)
S3 (Suspend to RAM)
SIGNAL
SLP_S1# SLP_S3#
HIGH HIGH HIGH HIGH
LOW
LOW
D
LOW
S4 (Suspend to Disk)
S5 (Soft OFF)
LOW LOW LOW LOW
Board ID / SKU ID Table for AD channel
Vcc 3.3V +/- 5%
Board ID
0
1
2
3
4
5
6
7 NC
100K +/- 5%Ra / Rc
Rb / Rd V min
AD_BID
0
8.2K +/- 5%
18K +/- 5%
33K +/- 5%
56K +/- 5%
100K +/- 5%
200K +/- 5%
0.216 V 0.250 V 0.289 V
0.436 V
0.712 V
1.036 V
1.453 V 1.650 V 1.759 V
1.935 V
2.500 V
E
SLP_S4# SLP_S5# +VALW +V +VS Clock
0 V
HIGH
LOWLOWLOW
ON
HIGHHIGHHIGH
HIGH
HIGH
ON
ON
ON
ON
Vtyp
AD_BID
0 V 0 V
0.503 V
0.819 V
ON
ON
ON
OFF
OFF
V
AD_BID
0.538 V
0.875 V
ON ON
ON
OFF
OFF
OFF
max
1.185 V 1.264 V
2.200 V
3.300 V
2.341 V
3.300 V
LOW
OFF
OFF
OFF
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.
External PCI Devices
Device IDSEL # REQ # / GNT # Interrupts
CardBus
1394
SD
Mini-PCI
LAN
3 3
AD20
AD16 0
AD20
AD18
AD17 3
EC SM Bus1 address
Device
Smart Battery
EEPROM(24C16/02)
(24C04)
Address Address
1010 000X b
1011 000Xb
2
2
1
PIRQA/PIRQB
PIRQE
PIRQA/PIRQB
PIRQG/PIRQH
PIRQF
EC SM Bus2 address
Device
ADM1032
2'nd Battery
1001 110X b0001 011X b
1001 011X b
BOARD ID Table
Board ID
0
1
2
3
4
5
6
7
PCB Revision
0.1
ICH6M SM Bus address
Device
4 4
Clock Generator
( ICS 952623)
DDR DIMM0
DDR DIMM2
A
Address
1101 001Xb
1010 000Xb
1010 010Xb
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SE CRET INFO RMATI ON. THIS SHEET MAY NO T BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
D
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
Notes
EDL00 LA-2601
351Monday, November 15, 2004
E
0.1
of
5
4
3
2
1
H_D#[0..63]
H_A#[3..31]<6>
D D
H_REQ#[0..4]<6>
C C
H_RS#[0..2]<6>
B B
A A
H_A#[3..31]
H_REQ#[0..4]
H_RS#[0..2]
H_ADSTB#0<6>
H_ADSTB#1<6>
CLK_CPU_BCLK<14>
CLK_CPU_BCLK#<14>
H_ADS#<6>
H_BNR#<6>
H_BPRI#<6>
H_BR0#<6>
H_DEFER#<6>
H_DRDY#<6>
H_HIT#<6>
H_HITM#<6>
H_LOCK#<6>
H_CPURST#<6>
H_TRDY#<6>
H_DBSY#<6>
H_DPSLP#<18>
H_DPRSTP#<18>
H_DPWR#<6>
H_PWRGOOD<18>
H_CPUSLP#<6,18>
H_THERMTRIP#<6,18>
H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
H_IERR#
H_CPURST#
H_RS#0
H_RS#1
H_RS#2
ITP_DBRRESET#
PRO_CHOT#
H_PWRGOOD
H_CPUSLP#
ITP_TCK
ITP_TDI
ITP_TDO
TEST1
TEST2
ITP_TMS
ITP_TRST#
THERMDA
THERMDC
THERMDA & THERMDC Trace / Space = 10 / 10 mil
5
JP7A
P4
A3#
U4
A4#
V3
A5#
R3
A6#
V2
A7#
W1
A8#
T4
A9#
W2
A10#
Y4
A11#
Y1
A12#
U1
A13#
AA3
A14#
Y3
A15#
AA2
A16#
AF4
A17#
AC4
A18#
AC7
A19#
AC3
A20#
AD3
A21#
AE4
A22#
AD2
A23#
AB4
A24#
AC6
ADDR GROUP
A25#
AD5
A26#
AE2
A27#
AD6
A28#
AF3
A29#
AE1
A30#
AF1
A31#
R2
REQ0#
P3
REQ1#
T2
REQ2#
P1
REQ3#
T1
REQ4#
U3
ADSTB0#
AE5
ADSTB1#
A16
ITP_CLK0
A15
ITP_CLK1
B15
BCLK0
B14
BCLK1
N2
ADS#
L1
BNR#
J3
BPRI#
N4
BR0#
L4
DEFER#
H2
DRDY#
K3
HIT#
K4
HITM#
A4
IERR#
J2
LOCK#
B11
RESET#
H1
RS0#
K1
RS1#
L2
RS2#
M3
TRDY#
C8
BPM0#
B8
BPM1#
A9
BPM2#
C9
BPM3#
A7
DBR#
M2
DBSY#
B7
DPSLP#
G1
DPRSTP#
C19
DPWR#
A10
PRDY#
B10
PREQ#
B17
PROCHOT#
E4
PWRGOOD
A6
SLP#
A13
TCK
C12
TDI
A12
TDO
C5
TEST1
F23
TEST2
C11
TMS
B13
TRST#
B18
THERMDA
A18
THERMDC
C17
THERMTRIP#
TYCO_1612365-1_Dothan
4
Dothan
DATA GROUP
HOST CLK
CONTROL GROUP
MISC
THERMAL
DIODE
LEGACY CPU
D0#
D1#
D2#
D3#
D4#
D5#
D6#
D7#
D8#
D9#
D10#
D11#
D12#
D13#
D14#
D15#
D16#
D17#
D18#
D19#
D20#
D21#
D22#
D23#
D24#
D25#
D26#
D27#
D28#
D29#
D30#
D31#
D32#
D33#
D34#
D35#
D36#
D37#
D38#
D39#
D40#
D41#
D42#
D43#
D44#
D45#
D46#
D47#
D48#
D49#
D50#
D51#
D52#
D53#
D54#
D55#
D56#
D57#
D58#
D59#
D60#
D61#
D62#
D63#
DINV0#
DINV1#
DINV2#
DINV3#
DSTBN0#
DSTBN1#
DSTBN2#
DSTBN3#
DSTBP0#
DSTBP1#
DSTBP2#
DSTBP3#
A20M#
FERR#
IGNNE#
INIT#
LINT0
LINT1
STPCLK#
SMI#
H_D#0
A19
H_D#1
A25
H_D#2
A22
H_D#3
B21
H_D#4
A24
H_D#5
B26
H_D#6
A21
H_D#7
B20
H_D#8
C20
H_D#9
B24
H_D#10
D24
H_D#11
E24
H_D#12
C26
H_D#13
B23
H_D#14
E23
H_D#15
C25
H_D#16
H23
H_D#17
G25
H_D#18
L23
H_D#19
M26
H_D#20
H24
H_D#21
F25
H_D#22
G24
H_D#23
J23
H_D#24
M23
H_D#25
J25
H_D#26
L26
H_D#27
N24
H_D#28
M25
H_D#29
H26
H_D#30
N25
H_D#31
K25
H_D#32
Y26
H_D#33
AA24
H_D#34
T25
H_D#35
U23
H_D#36
V23
H_D#37
R24
H_D#38
R26
H_D#39
R23
H_D#40
AA23
H_D#41
U26
H_D#42
V24
H_D#43
U25
H_D#44
V26
H_D#45
Y23
H_D#46
AA26
H_D#47
Y25
H_D#48
AB25
H_D#49
AC23
H_D#50
AB24
H_D#51
AC20
H_D#52
AC22
H_D#53
AC25
H_D#54
AD23
H_D#55
AE22
H_D#56
AF23
H_D#57
AD24
H_D#58
AF20
H_D#59
AE21
H_D#60
AD21
H_D#61
AF25
H_D#62
AF22
H_D#63
AF26
D25
J26
T24
AD20
C23
K24
W25
AE24
C22
L24
W24
AE25
C2
D3
A3
B5
D1
D4
C6
B4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SE CRET INFO RMATI ON. THIS SHEET MAY NO T BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
H_DINV#0 <6>
H_DINV#1 <6>
H_DINV#2 <6>
H_DINV#3 <6>
H_DSTBN#0 <6>
H_DSTBN#1 <6>
H_DSTBN#2 <6>
H_DSTBN#3 <6>
H_DSTBP#0 <6>
H_DSTBP#1 <6>
H_DSTBP#2 <6>
H_DSTBP#3 <6>
H_A20M# <18>
H_FERR# <18>
H_IGNNE# <18>
H_INIT# <18>
H_INTR <18>
H_NMI <18>
H_STPCLK# <18>
H_SMI# <18>
3
H_D#[0..63] <6>
2200P_0402_50V7K
EC_SMB_CK2<33,44>
EC_SMB_DA2<33,44>
C17
1
2
THERMDA
THERMDC
ITP_TDI
ITP_TDO
H_CPURST#
ITP_TMS
PRO_CHOT#
H_PWRGOOD
H_IERR#
ITP_DBRRESET#
ITP_TRST#
ITP_TCK
TEST1
TEST2
2
+3VS
1
C12
0.1U_0402_16V4Z
2
U3
2
3
8
7
R508 150_0402_5%
R29 54.9_0402_1%@
R28 54.9_0402_1%@
R27 40.2_0402_1%
R31 56_0402_5%
R24 200_0402_5%
R23 56_0402_5%
R26 150_0402_5%
R509 680_0402_5%
R30 27.4_0402_1%
R25 1K_0402_5%@
R46 1K_0402_5%@
VDD1
D+
ALERT#
D-
THERM#
SCLK
SDATA
GND
ADM1032ARM_RM8
12
12
12
12
12
12
12
12
12
12
12
12
Title
Size Document Number Rev
Date: Sheet
12
R20
10K_0402_5%@
1
6
4
5
+1.05VS
+3VS
Compal Electronics, Inc.
Dothan Processor in mFCPGA479
EDL00 LA-2601
451Monday, November 15, 2004
1
0.1
of
5
JP7B
1
2
+1.05VS
C26
VCCSENSE
VSSSENSE
GTL_REF0
COMP0
COMP1
COMP2
COMP3
AE7
VCCSENSE
AF6
VSSSENSE
F26
VCCA0
B1
VCCA1
N1
VCCA2
AC26
VCCA3
P23
VCCQ0
W4
VCCQ1
D10
VCCP
D12
VCCP
D14
VCCP
D16
VCCP
E11
VCCP
E13
VCCP
E15
VCCP
F10
VCCP
F12
VCCP
F14
VCCP
F16
VCCP
K6
VCCP
L5
VCCP
L21
VCCP
M6
VCCP
M22
VCCP
N5
VCCP
N21
VCCP
P6
VCCP
P22
VCCP
R5
VCCP
R21
VCCP
T6
VCCP
T22
VCCP
U21
VCCP
D6
VCC
D8
VCC
D18
VCC
D20
VCC
D22
VCC
E5
VCC
E7
VCC
E9
VCC
E17
VCC
E19
VCC
E21
VCC
F6
VCC
F8
VCC
F18
VCC
E1
PSI#
E2
VID0
F2
VID1
F3
VID2
G3
VID3
G4
VID4
H4
VID5
AD26
GTLREF
C16
BSEL0
C14
BSEL1
P25
COMP0
P26
COMP1
AB2
COMP2
AB1
COMP3
B2
RSVD
C3
RSVD
E26
RSVD
AF7
RSVD
AC1
RSVD
TYCO_1612365-1_Dothan
COMP0
COMP1
COMP2
COMP3
Dothan
R85 54.9_0402_1%@
1 2
R84 54.9_0402_1%@
1 2
+VCCA
D D
1.8V FOR DOTHAN-A
1 2
+1.8VS
R63 0_1206_5%@
1.5V FOR DOTHAN-B
1 2
+1.5VS
R56 0_1206_5%
1
C25
2
0.01U_0402_16V7K
C C
+1.05VS
R75
1K_0402_1%
B B
A A
1 2
R78 2K_0402_1%
10U_0805_10V4Z
+CPU_CORE
PSI#<48>
CPU_VID0<48>
CPU_VID1<48>
CPU_VID2<48>
12
CPU_VID3<48>
CPU_VID4<48>
CPU_VID5<48>
CPU_BSEL0<14>
CPU_BSEL1<14>
R69 27.4_0402_1%
1 2
R70 54.9_0402_1%
1 2
R83 27.4_0402_1%
1 2
R82 54.9_0402_1%
1 2
TRACE CLOSELY CPU < 0.5'
COMP0, COMP2 layout : Width 18mils and Space 25mils
COMP1, COMP3 layout : Space 25mils
5
4
A2
VSS
A5
VSS
A8
VSS
A11
VSS
A14
VSS
A17
VSS
A20
VSS
A23
VSS
A26
VSS
B3
VSS
B6
VSS
B9
VSS
B12
VSS
B16
VSS
B19
VSS
B22
VSS
B25
VSS
C1
VSS
C4
VSS
C7
VSS
C10
VSS
C13
VSS
C15
VSS
C18
VSS
C21
VSS
C24
VSS
D2
VSS
D5
VSS
D7
VSS
D9
VSS
D11
VSS
D13
VSS
D15
VSS
D17
VSS
D19
VSS
D21
VSS
D23
VSS
D26
VSS
E3
VSS
E6
VSS
E8
VSS
E10
VSS
E12
VSS
E14
VSS
E16
VSS
E18
VSS
E20
VSS
E22
VSS
POWER, GROUNG, RESERVED SIGNALS AND NC
E25
VSS
F1
VSS
F4
VSS
F5
VSS
F7
VSS
F9
VSS
F11
VSS
F13
VSS
F15
VSS
F17
VSS
F19
VSS
F21
VSS
F24
VSS
G2
VSS
G6
VSS
G22
VSS
G23
VSS
G26
VSS
H3
VSS
H5
VSS
H21
VSS
H25
VSS
J1
VSS
J4
VSS
J6
VSS
J22
VSS
J24
VSS
K2
VSS
K5
VSS
K21
VSS
K23
VSS
K26
VSS
L3
VSS
L6
VSS
L22
VSS
L25
VSS
M1
VSS
4
+1.05VS
1
+
2
150U_D2_6.3VM
3
+CPU_CORE
220U_D2_4VM_R12
1
C441
2
220U_D2_4VM_R12
+CPU_CORE
1
2
10U_0805_10V4Z
+CPU_CORE
1
2
10U_0805_10V4Z
+CPU_CORE
1
2
10U_0805_10V4Z
+CPU_CORE
1
2
10U_0805_10V4Z
+CPU_CORE
1
2
10U_0805_10V4Z
Vcc-core
Decoupling
SPCAP,Polymer
MLCC 0805 X5R
0.1U_0402_16V4Z
1
1
C435
C445
2
2
0.1U_0402_16V4Z
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SE CRET INFO RMATI ON. THIS SHEET MAY NO T BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
+
10U_0805_10V4Z
C47
10U_0805_10V4Z
C33
10U_0805_10V4Z
C454
10U_0805_10V4Z
C69
10U_0805_10V4Z
C509
0.1U_0402_16V4Z
C16
3
1
+
C472
2
220U_D2_4VM_R12
1
C46
2
10U_0805_10V4Z
1
C42
2
10U_0805_10V4Z
1
C455
2
10U_0805_10V4Z
1
C70
2
10U_0805_10V4Z
1
C510
2
10U_0805_10V4Z
C,uF ESR, mohm ESL,nH
3X330uF 9m ohm/3 3.5nH/4
35X10uF 5m ohm/35 0.6nH/35
1
C458
2
220U_D2_4VM_R12
1
+
C427
2
10U_0805_10V4Z
1
1
C45
2
2
10U_0805_10V4Z
1
1
C40
2
2
10U_0805_10V4Z
1
1
C64
2
2
10U_0805_10V4Z
1
1
C429
2
2
10U_0805_10V4Z
1
1
C511
2
2
0.1U_0402_16V4Z
1
1
C13
2
2
0.1U_0402_16V4Z
1
+
C460
2
C48
10U_0805_10V4Z
C41
10U_0805_10V4Z
C65
10U_0805_10V4Z
C470
10U_0805_10V4Z
C512
10U_0805_10V4Z
C15
0.1U_0402_16V4Z
10U_0805_10V4Z
1
C30
2
10U_0805_10V4Z
1
C39
2
10U_0805_10V4Z
1
C66
2
10U_0805_10V4Z
1
C430
2
10U_0805_10V4Z
1
C513
2
0.1U_0402_16V4Z
1
C14
2
1
C31
2
1
C444
2
1
C67
2
1
C471
2
1
C514
2
1
C461
2
1
2
10U_0805_10V4Z
1
2
10U_0805_10V4Z
1
2
10U_0805_10V4Z
1
2
10U_0805_10V4Z
1
2
10U_0805_10V4Z
1
2
0.1U_0402_16V4Z
2
C32
C443
C68
C516
C515
0.1U_0402_16V4Z
1
C453
2
2
C448
0.1U_0402_16V4Z
1
2
+CPU_CORE
C442
1
JP7C
F20
VCC
F22
VCC
G5
VCC
G21
VCC
H6
VCC
H22
VCC
J5
VCC
J21
VCC
K22
VCC
U5
VCC
V6
VCC
V22
VCC
W5
VCC
W21
VCC
Y6
VCC
Y22
AA5
AA7
AA9
AA11
AA13
AA15
AA17
AA19
AA21
AB6
AB8
AB10
AB12
AB14
AB16
AB18
AB20
AB22
AC9
AC11
AC13
AC15
AC17
AC19
AD8
AD10
AD12
AD14
AD16
AD18
AE9
AE11
AE13
AE15
AE17
AE19
AF8
AF10
AF12
AF14
AF16
AF18
M4
M5
M21
M24
N3
N6
N22
N23
N26
P2
P5
P21
P24
R1
R4
R6
R22
R25
T3
T5
T21
T23
TYCO_1612365-1_Dothan
Title
Size Document Number Rev
Date: Sheet of
Dothan
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
POWER, GROUND
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
Compal Electronics, Inc.
Dothan Processor in mFCPGA479
EDL00 LA-2601
T26
VSS
U2
VSS
U6
VSS
U22
VSS
U24
VSS
V1
VSS
V4
VSS
V5
VSS
V21
VSS
V25
VSS
W3
VSS
W6
VSS
W22
VSS
W23
VSS
W26
VSS
Y2
VSS
Y5
VSS
Y21
VSS
Y24
VSS
AA1
VSS
AA4
VSS
AA6
VSS
AA8
VSS
AA10
VSS
AA12
VSS
AA14
VSS
AA16
VSS
AA18
VSS
AA20
VSS
AA22
VSS
AA25
VSS
AB3
VSS
AB5
VSS
AB7
VSS
AB9
VSS
AB11
VSS
AB13
VSS
AB15
VSS
AB17
VSS
AB19
VSS
AB21
VSS
AB23
VSS
AB26
VSS
AC2
VSS
AC5
VSS
AC8
VSS
AC10
VSS
AC12
VSS
AC14
VSS
AC16
VSS
AC18
VSS
AC21
VSS
AC24
VSS
AD1
VSS
AD4
VSS
AD7
VSS
AD9
VSS
AD11
VSS
AD13
VSS
AD15
VSS
AD17
VSS
AD19
VSS
AD22
VSS
AD25
VSS
AE3
VSS
AE6
VSS
AE8
VSS
AE10
VSS
AE12
VSS
AE14
VSS
AE16
VSS
AE18
VSS
AE20
VSS
AE23
VSS
AE26
VSS
AF2
VSS
AF5
VSS
AF9
VSS
AF11
VSS
AF13
VSS
AF15
VSS
AF17
VSS
AF19
VSS
AF21
VSS
AF24
VSS
551Monday, November 15, 2004
1
0.1
5
H_RS#[0..2]
H_A#[3..31]<4>
H_REQ#[0..4]<4>
D D
C C
CLK_MCH_BCLK#<14>
CLK_MCH_BCLK<14>
B B
H_A#[3..31]
H_ADSTB#0<4>
H_ADSTB#1<4>
H_DSTBN#0<4>
H_DSTBN#1<4>
H_DSTBN#2<4>
H_DSTBN#3<4>
H_DSTBP#0<4>
H_DSTBP#1<4>
H_DSTBP#2<4>
H_DSTBP#3<4>
H_DINV#0<4>
H_DINV#1<4>
H_DINV#2<4>
H_DINV#3<4>
H_CPURST#<4>
H_ADS#<4>
H_TRDY#<4>
H_DPWR#<4>
H_DRDY#<4>
H_DEFER#<4>
H_HITM#<4>
H_HIT#<4>
H_LOCK#<4>
H_BR0#<4>
H_BNR#<4>
H_BPRI#<4>
H_DBSY#<4>
Un-pop for Dothan-A
R54 0_0402_5%
H_CPUSLP#<4,18>
A A
(5mil:15mil) (12mil:10mil)
H_VREF H_XSWING H_YSWING
1
C436
0.1U_0402_16V4Z
2
1 2
12
R388
100_0603_1%
12
R387
200_0603_1%
5
H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
CPU_SLP#
H_RS#0
H_RS#1
H_RS#2
H_RS#[0..2] <4>
U5A
G9
HA3#
C9
HA4#
E9
HA5#
B7
HA6#
A10
HA7#
F9
HA8#
D8
HA9#
B10
HA10#
E10
HA11#
G10
HA12#
D9
HA13#
E11
HA14#
F10
HA15#
G11
HA16#
G13
HA17#
C10
HA18#
C11
HA19#
D11
HA20#
C12
HA21#
B13
HA22#
A12
HA23#
F12
HA24#
G12
HA25#
E12
HA26#
C13
HA27#
B11
HA28#
D13
HA29#
A13
HA30#
F13
HA31#
A11
HPCREQ#
A7
HREQ#0
D7
HREQ#1
B8
HREQ#2
C7
HREQ#3
A8
HREQ#4
B9
HADSTB#0
E13
HADSTB#1
AB1
HCLKN
AB2
HCLKP
G4
HDSTBN#0
K1
HDSTBN#1
R3
HDSTBN#2
V3
HDSTBN#3
G5
HDSTBP#0
K2
HDSTBP#1
R2
HDSTBP#2
W4
HDSTBP#3
H8
HDINV#0
K3
HDINV#1
T7
HDINV#2
U5
HDINV#3
H10
HCPURST#
F8
HADS#
B5
HTRDY#
G6
HDPWR#
F7
HDRDY#
E6
HDEFER#
F6
HEDRDY#
D6
HHITM#
D4
HHIT#
B3
HLOCK#
E7
HBREQ0#
A5
HBNR#
D5
HBPRI#
C6
HDBSY#
G8
HCPUSLP#
A4
HRS0#
C5
HRS1#
B4
HRS2#
CPU_SLP#
Alviso
ALVISO_BGA1257
1
C423
0.1U_0402_16V4Z
2
HOST
HXRCOMP
HXSCOMP
HYRCOMP
HYSCOMP
HXSWING
HYSWING
+1.05VS +1.05VS+1.05VS
HD10#
HD11#
HD12#
HD13#
HD14#
HD15#
HD16#
HD17#
HD18#
HD19#
HD20#
HD21#
HD22#
HD23#
HD24#
HD25#
HD26#
HD27#
HD28#
HD29#
HD30#
HD31#
HD32#
HD33#
HD34#
HD35#
HD36#
HD37#
HD38#
HD39#
HD40#
HD41#
HD42#
HD43#
HD44#
HD45#
HD46#
HD47#
HD48#
HD49#
HD50#
HD51#
HD52#
HD53#
HD54#
HD55#
HD56#
HD57#
HD58#
HD59#
HD60#
HD61#
HD62#
HD63#
HVREF
HD0#
HD1#
HD2#
HD3#
HD4#
HD5#
HD6#
HD7#
HD8#
HD9#
12
R406
221_0603_1%
12
R405
100_0603_1%
E4
E1
F4
H7
E2
F1
E3
D3
K7
F2
J7
J8
H6
F3
K8
H5
H1
H2
K5
K6
J4
G3
H3
J1
L5
K4
J5
P7
L7
J3
P5
L3
U7
V6
R6
R5
P3
T8
R7
R8
U8
R4
T4
T5
R1
T3
V8
U6
W6
U3
V5
W8
W7
U2
U1
Y5
Y2
V4
Y7
W1
W3
Y3
Y6
W2
J11
C1
C2
T1
L1
D1
P1
4
H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
H_VREF
H_XRCOMP
H_XSCOMP
H_YRCOMP
H_YSCOMP
H_XSWING
H_YSWING
H_D#[0..63]H_REQ#[0..4]
+DDRVCC
R50 24.9_0402_1%
R47 54.9_0402_1%
R72 24.9_0402_1%
R68 54.9_0402_1%
1 2
1 2
12
12
H_D#[0..63] <4>
R426 40.2_0402_1%
1 2
R427 40.2_0402_1%
1 2
R429 80.6_0402_1%
1 2
R430 80.6_0402_1%
1 2
+1.05VS
3
DMI_ITX_MRX_N0<19>
DMI_ITX_MRX_N1<19>
DMI_ITX_MRX_N2<19>
DMI_ITX_MRX_N3<19>
DMI_ITX_MRX_P0<19>
DMI_ITX_MRX_P1<19>
DMI_ITX_MRX_P2<19>
DMI_ITX_MRX_P3<19>
DMI_MTX_IRX_N0<19>
DMI_MTX_IRX_N1<19>
DMI_MTX_IRX_N2<19>
DMI_MTX_IRX_N3<19>
DMI_MTX_IRX_P0<19>
DMI_MTX_IRX_P1<19>
DMI_MTX_IRX_P2<19>
DMI_MTX_IRX_P3<19>
M_CLK_DDR0<11>
M_CLK_DDR1<11>
M_CLK_DDR3<12>
M_CLK_DDR4<12>
M_CLK_DDR#0<11>
M_CLK_DDR#1<11>
M_CLK_DDR#3<12>
M_CLK_DDR#4<12>
DDR_CKE0_DIMMA<11>
DDR_CKE1_DIMMA<11>
DDR_CKE2_DIMMB<12>
DDR_CKE3_DIMMB<12>
DDR_CS0_DIMMA#<11>
DDR_CS1_DIMMA#<11>
DDR_CS2_DIMMB#<12>
DDR_CS3_DIMMB#<12>
(10mil:20mil)
H_XRCOMP & H_YRCOMP Trace / Space = 10 / 20 mil
12
R420
221_0603_1%
(12mil:10mil)
1
C459
0.1U_0402_16V4Z
2
4
12
R419
100_0603_1%
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SE CRET INFO RMATI ON. THIS SHEET MAY NO T BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
M_ODT0<11>
M_ODT1<11>
M_ODT2<12>
M_ODT3<12>
1K_0402_1%
1K_0402_1%
DMI_ITX_MRX_N0
DMI_ITX_MRX_N1
DMI_ITX_MRX_N2
DMI_ITX_MRX_N3
DMI_ITX_MRX_P0
DMI_ITX_MRX_P1
DMI_ITX_MRX_P2
DMI_ITX_MRX_P3
DMI_MTX_IRX_N0
DMI_MTX_IRX_N1
DMI_MTX_IRX_N2
DMI_MTX_IRX_N3
DMI_MTX_IRX_P0
DMI_MTX_IRX_P1
DMI_MTX_IRX_P2
DMI_MTX_IRX_P3
DDR_CKE0_DIMMA
DDR_CKE1_DIMMA
DDR_CKE2_DIMMB
DDR_CKE3_DIMMB
DDR_CS0_DIMMA#
DDR_CS1_DIMMA#
DDR_CS2_DIMMB#
DDR_CS3_DIMMB#
M_OCDCOMP0
M_OCDCOMP1
M_ODT0
M_ODT1
M_ODT2
M_ODT3
M_RCOMPN
M_RCOMPP
SMVREF
M_XSLEW
M_YSLEW
+DDRVCC
12
R423
0.1U_0402_16V4Z
12
R421
C488
U5B
AA31
AB35
AC31
AD35
Y31
AA35
AB31
AC35
AA33
AB37
AC33
AD37
Y33
AA37
AB33
AC37
AM33
AL1
AE11
AJ34
AF6
AC10
AN33
AK1
AE10
AJ33
AF5
AD10
AP21
AM21
AH21
AK21
AN16
AM14
AH15
AG16
AF22
AF16
AP14
AL15
AM11
AN10
AK10
AK11
AF37
AD1
AE27
AE28
AF9
AF10
ALVISO_BGA1257
1
2
DMIRXN0
DMIRXN1
DMIRXN2
DMIRXN3
DMIRXP0
DMIRXP1
DMIRXP2
DMIRXP3
DMITXN0
DMITXN1
DMITXN2
DMITXN3
DMITXP0
DMITXP1
DMITXP2
DMITXP3
SM_CK0
SM_CK1
SM_CK2
SM_CK3
SM_CK4
SM_CK5
SM_CK0#
SM_CK1#
SM_CK2#
SM_CK3#
SM_CK4#
SM_CK5#
SM_CKE0
SM_CKE1
SM_CKE2
SM_CKE3
SM_CS0#
SM_CS1#
SM_CS2#
SM_CS3#
SM_OCDCOMP0
SM_OCDCOMP1
SM_ODT0
SM_ODT1
SM_ODT2
SM_ODT3
SMRCOMPN
SMRCOMPP
SMVREF0
SMVREF1
SMXSLEWIN
SMXSLEWOUT
SMYSLEWIN
SMYSLEWOUT
SMVREF
1
C489
0.1U_0402_16V4Z
2
2
CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
DMIDDR MUXING
CFG13
CFG14
CFG15
CFG16
CFG17
CFG18
CFG19
CFG20
RSVD21
RSVD22
CFG/RSVD
RSVD23
RSVD24
RSVD25
RSVD26
RSVD27
BM_BUSY#
EXT_TS0#
EXT_TS1#
THRMTRIP#
PWROK
RSTIN#
PM
DREF_CLKN
DREF_CLKP
DREF_SSCLKP
CLK
DREF_SSCLKN
NC1
NC2
NC3
NC4
NC5
NC6
NC7
NC8
NC9
NC10
NC
NC11
2
CLK_DREF_SSC
CLK_DREF_SSC#
CFG0
G16
MCH_CLKSEL1
H13
MCH_CLKSEL0
G14
F16
F15
CFG5
G15
CFG6
E16
CFG7
D17
J16
CFG9
D15
E15
D14
CFG12
E14
CFG13
H12
C14
H15
CFG16 CFG6
J15
H14
CFG18
G22
CFG19
G23
D23
G25
G24
J17
A31
A30
D26
D25
J23
EXT_TS#0
J21
EXT_TS#1
H22
H_THERMTRIP#
F5
AD30
AE29
CLK_DREF_96M#
A24
CLK_DREF_96M
A23
CLK_DREF_SSC
D37
CLK_DREF_SSC#
C37
AP37
AN37
AP36
AP2
AP1
AN1
B1
A2
B37
A36
A37
CFG[2:0]
CFG5
CFG6
CFG7
CFG9
CFG[13:12]
CFG16
(FSB Dynamic
ODT)
CFG18
(VCC Select)
CFG19
(VTT Select)
Title
Size Document Number Rev
Date: Sheet
R51 0_0402_5%PM@
1 2
R52 0_0402_5%PM@
1 2
MCH_CLKSEL1 <14>
MCH_CLKSEL0 <14>
CFG0
R40 10K_0402_5%
1 2
CFG5
R413 1K_0402_5%@
1 2
R407 1K_0402_5%
CFG7
CFG9
CFG12
CFG13
CFG16
1 2
R408 1K_0402_5%@
1 2
R404 1K_0402_5%@
1 2
R409 1K_0402_5%@
1 2
R412 1K_0402_5%@
1 2
R417 1K_0402_5%@
1 2
CFG[17:3]: internal pull-up
CFG18
R41 1K_0402_5%@
CFG19
1 2
R42 1K_0402_5%@
1 2
CFG[19:18]: internal pull-down
PM_BMBUSY# <19>
H_THERMTRIP# <4,18>
VGATE <14,19,48>
PLT_RST# <17,19,21,32,33>
CLK_DREF_96M# <14>
CLK_DREF_96M <14>
CLK_DREF_SSC <14>
CLK_DREF_SSC# <14>
EXT_TS#0
R416 10K_0402_5%
EXT_TS#1
1 2
R411 10K_0402_5%
1 2
Refer to sheet 6 for FSB
frequency select
Low = DMI x 2
High = DMI x 4
Low = DDR-II
High = DDR-I
Low = DT/Transportable CPU
High = Mobile CPU
Low = Reverse Lane
High = Normal Operation
00 = Reserved
01 = XOR Mode Enabled
10 = All Z Mode Enabled
11 = Normal Operation (Default)
Low = Disabled
High = Enabled
Low = 1.05V (Default)
High = 1.5V
Low = 1.05V (Default)
High = 1.2V
Compal Electronics, Inc.
Alviso HOST(1/5)
EDL00 LA-2601
1
+1.5VS
+1.05VS
+2.5VS
+2.5VS
*
*
*
*
*
*
*
*
0.1
of
651Monday, November 15, 2004
1
5
D D
4
3
2
1
DDR_A_BS#0<11>
DDR_A_BS#1<11>
DDR_A_BS#2<11>
DDR_A_DM[0..7]<11>
DDR_A_DQS[0..7]<11>
C C
B B
DDR_A_DQS#[0..7]<11>
DDR_A_MA[0..13]<11>
DDR_A_CAS#<11>
DDR_A_RAS#<11>
DDR_A_WE#<11> DDR_B_WE#<12>
DDR_A_DM0
DDR_A_DM1
DDR_A_DM2
DDR_A_DM3
DDR_A_DM4
DDR_A_DM5
DDR_A_DM6
DDR_A_DM7
DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7
DDR_A_DQS#0
DDR_A_DQS#1
DDR_A_DQS#2
DDR_A_DQS#3
DDR_A_DQS#4
DDR_A_DQS#5
DDR_A_DQS#6
DDR_A_DQS#7
DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
AK15
AK16
AL21
AJ37
AP35
AL29
AP24
AP9
AP4
AJ2
AD3
AK36
AP33
AN29
AP23
AM8
AM4
AJ1
AE5
AK35
AP34
AN30
AN23
AN8
AM5
AH1
AE4
AL17
AP17
AP18
AM17
AN18
AM18
AL19
AP20
AM19
AL20
AM16
AN20
AM20
AM15
AN15
AP16
AF29
AF28
AP15
SA_BS0#
SA_BS1#
SA_BS2#
SA_DM0
SA_DM1
SA_DM2
SA_DM3
SA_DM4
SA_DM5
SA_DM6
SA_DM7
SA_DQS0
SA_DQS1
SA_DQS2
SA_DQS3
SA_DQS4
SA_DQS5
SA_DQS6
SA_DQS7
SA_DQS0#
SA_DQS1#
SA_DQS2#
SA_DQS3#
SA_DQS4#
SA_DQS5#
SA_DQS6#
SA_DQS7#
SA_MA0
SA_MA1
SA_MA2
SA_MA3
SA_MA4
SA_MA5
SA_MA6
SA_MA7
SA_MA8
SA_MA9
SA_MA10
SA_MA11
SA_MA12
SA_MA13
SA_CAS#
SA_RAS#
SA_RCVENIN#
SA_RCVENOUT#
SA_WE#
U5C
SADQ0
SADQ1
SADQ2
SADQ3
SADQ4
SADQ5
SADQ6
SADQ7
SADQ8
SADQ9
SADQ10
SADQ11
SADQ12
SADQ13
SADQ14
SADQ15
SADQ16
SADQ17
SADQ18
SADQ19
SADQ20
SADQ21
SADQ22
SADQ23
SADQ24
SADQ25
SADQ26
SADQ27
SADQ28
SADQ29
SADQ30
SADQ31
SADQ32
SADQ33
SADQ34
SADQ35
SADQ36
SADQ37
SADQ38
SADQ39
SADQ40
SADQ41
SADQ42
SADQ43
DDR MEMORY SYSTEM A
SADQ44
SADQ45
SADQ46
SADQ47
SADQ48
SADQ49
SADQ50
SADQ51
SADQ52
SADQ53
SADQ54
SADQ55
SADQ56
SADQ57
SADQ58
SADQ59
SADQ60
SADQ61
SADQ62
SADQ63
ALVISO_BGA1257
AG35
AH35
AL35
AL37
AH36
AJ35
AK37
AL34
AM36
AN35
AP32
AM31
AM34
AM35
AL32
AM32
AN31
AP31
AN28
AP28
AL30
AM30
AM28
AL28
AP27
AM27
AM23
AM22
AL23
AM24
AN22
AP22
AM9
AL9
AL6
AP7
AP11
AP10
AL7
AM7
AN5
AN6
AN3
AP3
AP6
AM6
AL4
AM3
AK2
AK3
AG2
AG1
AL3
AM2
AH3
AG3
AF3
AE3
AD6
AC4
AF2
AF1
AD4
AD5
DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63
DDR_B_BS#0<12>
DDR_B_BS#1<12>
DDR_B_BS#2<12>
DDR_B_DM[0..7]<12>
DDR_B_DQS[0..7]<12>
DDR_B_DQS#[0..7]<12>
DDR_B_MA[0..13]<12>
DDR_B_CAS#<12>
DDR_B_RAS#<12>
DDR_B_DM0
DDR_B_DM1
DDR_B_DM2
DDR_B_DM3
DDR_B_DM4
DDR_B_DM5
DDR_B_DM6
DDR_B_DM7
DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4
DDR_B_DQS5
DDR_B_DQS6
DDR_B_DQS7
DDR_B_DQS#0
DDR_B_DQS#1
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS#4
DDR_B_DQS#5
DDR_B_DQS#6
DDR_B_DQS#7
DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13
AJ15
AG17
AG21
AF32
AK34
AK27
AK24
AJ10
AK5
AE7
AB7
AF34
AK32
AJ28
AK23
AM10
AH6
AF8
AB4
AF35
AK33
AK28
AJ23
AL10
AH7
AF7
AB5
AH17
AK17
AH18
AJ18
AK18
AJ19
AK19
AH19
AJ20
AH20
AJ16
AG18
AG20
AG15
AH14
AK14
AF15
AF14
AH16
SB_BS0#
SB_BS1#
SB_BS2#
SB_DM0
SB_DM1
SB_DM2
SB_DM3
SB_DM4
SB_DM5
SB_DM6
SB_DM7
SB_DQS0
SB_DQS1
SB_DQS2
SB_DQS3
SB_DQS4
SB_DQS5
SB_DQS6
SB_DQS7
SB_DQS0#
SB_DQS1#
SB_DQS2#
SB_DQS3#
SB_DQS4#
SB_DQS5#
SB_DQS6#
SB_DQS7#
SB_MA0
SB_MA1
SB_MA2
SB_MA3
SB_MA4
SB_MA5
SB_MA6
SB_MA7
SB_MA8
SB_MA9
SB_MA10
SB_MA11
SB_MA12
SB_MA13
SB_CAS#
SB_RAS#
SB_RCVENIN#
SB_RCVENOUT#
SB_WE#
U5D
SBDQ0
SBDQ1
SBDQ2
SBDQ3
SBDQ4
SBDQ5
SBDQ6
SBDQ7
SBDQ8
SBDQ9
SBDQ10
SBDQ11
SBDQ12
SBDQ13
SBDQ14
SBDQ15
SBDQ16
SBDQ17
SBDQ18
SBDQ19
SBDQ20
SBDQ21
SBDQ22
SBDQ23
SBDQ24
SBDQ25
SBDQ26
SBDQ27
SBDQ28
SBDQ29
SBDQ30
SBDQ31
SBDQ32
SBDQ33
SBDQ34
SBDQ35
SBDQ36
SBDQ37
SBDQ38
SBDQ39
SBDQ40
SBDQ41
SBDQ42
DDR SYSTEM MEMORY B
SBDQ43
SBDQ44
SBDQ45
SBDQ46
SBDQ47
SBDQ48
SBDQ49
SBDQ50
SBDQ51
SBDQ52
SBDQ53
SBDQ54
SBDQ55
SBDQ56
SBDQ57
SBDQ58
SBDQ59
SBDQ60
SBDQ61
SBDQ62
SBDQ63
ALVISO_BGA1257
AE31
AE32
AG32
AG36
AE34
AE33
AF31
AF30
AH33
AH32
AK31
AG30
AG34
AG33
AH31
AJ31
AK30
AJ30
AH29
AH28
AK29
AH30
AH27
AG28
AF24
AG23
AJ22
AK22
AH24
AH23
AG22
AJ21
AG10
AG9
AG8
AH8
AH11
AH10
AJ9
AK9
AJ7
AK6
AJ4
AH5
AK8
AJ8
AJ5
AK4
AG5
AG4
AD8
AD9
AH4
AG6
AE8
AD7
AC5
AB8
AB6
AA8
AC8
AC7
AA4
AA5
DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63
DDR_B_D[0..63] <12>DDR_A_D[0..63] <11>
A A
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SE CRET INFO RMATI ON. THIS SHEET MAY NO T BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
Alviso DDR(2/5)
EDL00 LA-2601
751Monday, November 15, 2004
1
0.1
of
5
+3VS +2.5VS
12
R402
2.2K_0402_5%GM@
D D
C C
+2.5VS
B B
4.7K_0402_5%
LDDC_CLK
GMCH_ENBKL<16,33>
GMCH_TV_COMPS<22>
GMCH_TV_LUMA<22>
GMCH_TV_CRMA<22>
R381 4.7K_0402_5%
1 2
R382 4.7K_0402_5%
1 2
R400 2.2K_0402_5%
1 2
R39 2.2K_0402_5%
1 2
R398 100K_0402_5%
1 2
R403 1.5K_0402_1%
1 2
R44 150_0402_5%
1 2
R515 150_0402_5%
1 2
R516 150_0402_5%
1 2
+2.5VS
R45
G
2
1 2
S
GMCH_LCD_CLK
13
D
Q6
2N7002_SOT23GM@
GMCH_CRT_CLK<15>
GMCH_CRT_DATA<15>
GMCH_CRT_B<15>
GMCH_CRT_G<15>
GMCH_CRT_R<15>
GMCH_CRT_VSYNC<15>
GMCH_CRT_HSYNC<15>
2
G
1 3
D
S
Q44
BSS138_SOT23GM@
GMCH_TV_COMPS
GMCH_TV_LUMA
GMCH_TV_CRMA
GMCH_CRT_CLK
GMCH_CRT_DATA
LCTLB_DATA
LCTLA_CLK
LBKLT_EN
LIBG
GMCH_TV_COMPS
GMCH_TV_LUMA
GMCH_TV_CRMA
+3VS
R49
1 2
LBKLT_EN
R418 4.99K_0603_1%
GMCH_CRT_CLK
GMCH_CRT_DATA
R384 150_0402_5%
R385 150_0402_5%
R386 150_0402_5%
4.7K_0402_5%GM@
GMCH_LCD_CLK <16>
4
SDVO_SDAT<16>
SDVO_SCLK<16>
CLK_MCH_3GPLL#<14>
CLK_MCH_3GPLL<14>
12
SDVO_SDAT
SDVO_SCLK
TV_REFSET
12
R399 0_0402_5%
12
12
12
1 2
R414 255_0402_1%
GMCH_ENVDD<16>
GMCH_TXCLK-<16>
GMCH_TXCLK+<16>
GMCH_TZCLK-<16>
GMCH_TZCLK+<16>
GMCH_TXOUT0-<16>
GMCH_TXOUT1-<16>
GMCH_TXOUT2-<16>
GMCH_TXOUT0+<16>
GMCH_TXOUT1+<16>
GMCH_TXOUT2+<16>
GMCH_TZOUT0-<16>
GMCH_TZOUT1-<16>
GMCH_TZOUT2-<16>
GMCH_TZOUT0+<16>
GMCH_TZOUT1+<16>
GMCH_TZOUT2+<16>
REFSET
LBKLT_EN
LCTLA_CLK
LCTLB_DATA
LDDC_CLK
LDDC_DATA
GMCH_ENVDD
LIBG
GMCH_TXCLKGMCH_TXCLK+
GMCH_TZCLKGMCH_TZCLK+
GMCH_TXOUT0GMCH_TXOUT1GMCH_TXOUT2-
GMCH_TXOUT0+
GMCH_TXOUT1+
GMCH_TXOUT2+
GMCH_TZOUT0GMCH_TZOUT1GMCH_TZOUT2-
GMCH_TZOUT0+
GMCH_TZOUT1+
GMCH_TZOUT2+
U5G
H24
H25
AB29
AC29
A15
C16
A17
J18
B15
B16
B17
E24
E23
E21
D21
C20
B20
A19
B19
H21
G21
J20
E25
F25
C23
C22
F23
F22
F26
C33
C31
F28
F27
B30
B29
C25
C24
B34
B33
B32
A34
A33
B31
C29
D28
C27
C28
D27
C26
ALVISO_BGA1257
SDVOCTRL_DATA
SDVOCTRL_CLK
GCLKN
GCLKP
TVDAC_A
TVDAC_B
TVDAC_C
TV_REFSET
TV_IRTNA
TV_IRTNB
TV_IRTNC
DDCCLK
DDCDATA
BLUE
BLUE#
GREEN
GREEN#
RED
RED#
VSYNC
HSYNC
REFSET
LBKLT_CTL
LBKLT_EN
LCTLA_CLK
LCTLB_DATA
LDDC_CLK
LDDC_DATA
LVDD_EN
LIBG
LVBG
LVREFH
LVREFL
LACLKN
LACLKP
LBCLKN
LBCLKP
LADATAN0
LADATAN1
LADATAN2
LADATAP0
LADATAP1
LADATAP2
LBDATAN0
LBDATAN1
LBDATAN2
LBDATAP0
LBDATAP1
LBDATAP2
3
EXP_RXN0/SDVO_TVCLKIN#
MISCTVVGALVDS
EXP_RXN1/SDVO_INT#
EXP_RXN2/SDVO_FLDSTALL#
EXP_RXP0/SDVO_TVCLKIN
EXP_RXP1/SDVO_INT
EXP_RXP2/SDVO_FLDSTALL
EXP_TXN0/SDVOB_RED#
EXP_TXN1/SDVOB_GREEN#
EXP_TXN2/SDVOB_BLUE#
EXP_TXN3/SDVOB_CLKN
EXP_TXN4/SDVOC_RED#
EXP_TXN5/SDVOC_GREEN#
EXP_TXN6/SDVOC_BLUE#
EXP_TXN7/SDVOC_CLKN
PCI - EXPRESS GRAPHICS
EXP_TXP0/SDVOB_RED
EXP_TXP1/SDVOB_GREEN
EXP_TXP2/SDVOB_BLUE
EXP_TXP3/SDVOB_CLKP
EXP_TXP4/SDVOC_RED
EXP_TXP5/SDVOC_GREEN
EXP_TXP6/SDVOC_BLUE
EXP_TXP7/SDVOC_CLKP
EXP_COMPI
EXP_ICOMPO
EXP_RXN3
EXP_RXN4
EXP_RXN5
EXP_RXN6
EXP_RXN7
EXP_RXN8
EXP_RXN9
EXP_RXN10
EXP_RXN11
EXP_RXN12
EXP_RXN13
EXP_RXN14
EXP_RXN15
EXP_RXP3
EXP_RXP4
EXP_RXP5
EXP_RXP6
EXP_RXP7
EXP_RXP8
EXP_RXP9
EXP_RXP10
EXP_RXP11
EXP_RXP12
EXP_RXP13
EXP_RXP14
EXP_RXP15
EXP_TXN8
EXP_TXN9
EXP_TXN10
EXP_TXN11
EXP_TXN12
EXP_TXN13
EXP_TXN14
EXP_TXN15
EXP_TXP8
EXP_TXP9
EXP_TXP10
EXP_TXP11
EXP_TXP12
EXP_TXP13
EXP_TXP14
EXP_TXP15
2
PCIE_MTX_C_GRX_N[0..15]<16>
PCIE_MTX_C_GRX_P[0..15]<16>
PCEI_GTX_C_MRX_N[0..15]<16>
PCEI_GTX_C_MRX_P[0..15]<16>
PEG_COMP
D36
D34
PCEI_GTX_C_MRX_N0
E30
PCEI_GTX_C_MRX_N1
F34
PCEI_GTX_C_MRX_N2
G30
PCEI_GTX_C_MRX_N3
H34
PCEI_GTX_C_MRX_N4
J30
PCEI_GTX_C_MRX_N5
K34
PCEI_GTX_C_MRX_N6
L30
PCEI_GTX_C_MRX_N7
M34
PCEI_GTX_C_MRX_N8
N30
PCEI_GTX_C_MRX_N9
P34
PCEI_GTX_C_MRX_N10
R30
PCEI_GTX_C_MRX_N11
T34
PCEI_GTX_C_MRX_N12
U30
PCEI_GTX_C_MRX_N13
V34
PCEI_GTX_C_MRX_N14
W30
PCEI_GTX_C_MRX_N15
Y34
PCEI_GTX_C_MRX_P0
D30
PCEI_GTX_C_MRX_P1
E34
PCEI_GTX_C_MRX_P2
F30
PCEI_GTX_C_MRX_P3
G34
PCEI_GTX_C_MRX_P4
H30
PCEI_GTX_C_MRX_P5
J34
PCEI_GTX_C_MRX_P6
K30
PCEI_GTX_C_MRX_P7
L34
PCEI_GTX_C_MRX_P8
M30
PCEI_GTX_C_MRX_P9
N34
PCEI_GTX_C_MRX_P10
P30
PCEI_GTX_C_MRX_P11
R34
PCEI_GTX_C_MRX_P12
T30
PCEI_GTX_C_MRX_P13
U34
PCEI_GTX_C_MRX_P14
V30
PCEI_GTX_C_MRX_P15
W34
PCIE_MTX_GRX_N0
E32
PCIE_MTX_GRX_N1
F36
PCIE_MTX_GRX_N2
G32
PCIE_MTX_GRX_N3
H36
PCIE_MTX_GRX_N4 PCIE_MTX_C_GRX_N4
J32
PCIE_MTX_GRX_N5
K36
PCIE_MTX_GRX_N6
L32
PCIE_MTX_GRX_N7
M36
PCIE_MTX_GRX_N8
N32
PCIE_MTX_GRX_N9
P36
PCIE_MTX_GRX_N10
R32
PCIE_MTX_GRX_N11
T36
PCIE_MTX_GRX_N12
U32
PCIE_MTX_GRX_N13
V36
PCIE_MTX_GRX_N14
W32
PCIE_MTX_GRX_N15
Y36
PCIE_MTX_GRX_P0
D32
PCIE_MTX_GRX_P1
E36
PCIE_MTX_GRX_P2
F32
PCIE_MTX_GRX_P3
G36
PCIE_MTX_GRX_P4
H32
PCIE_MTX_GRX_P5
J36
PCIE_MTX_GRX_P6
K32
PCIE_MTX_GRX_P7
L36
PCIE_MTX_GRX_P8
M32
PCIE_MTX_GRX_P9
N36
PCIE_MTX_GRX_P10
P32
PCIE_MTX_GRX_P11
R36
PCIE_MTX_GRX_P12
T32
PCIE_MTX_GRX_P13
U36
PCIE_MTX_GRX_P14
V32
PCIE_MTX_GRX_P15
W36
1 2
R48 24.9_0402_1%
C59 0.1U_0402_16V4Z
1 2
C71 0.1U_0402_16V4Z
1 2
C76 0.1U_0402_16V4Z
1 2
C80 0.1U_0402_16V4Z
1 2
C91 0.1U_0402_16V4Z
1 2
C100 0.1U_0402_16V4Z
1 2
C109 0.1U_0402_16V4Z
1 2
C116 0.1U_0402_16V4Z
1 2
C58 0.1U_0402_16V4Z
1 2
C63 0.1U_0402_16V4Z
1 2
C75 0.1U_0402_16V4Z
1 2
C79 0.1U_0402_16V4Z
1 2
C89 0.1U_0402_16V4Z
1 2
C98 0.1U_0402_16V4Z
1 2
C105 0.1U_0402_16V4Z
1 2
C115 0.1U_0402_16V4Z
1 2
PCIE_MTX_C_GRX_N[0..15]
PCIE_MTX_C_GRX_P[0..15]
PCEI_GTX_C_MRX_N[0..15]
PCEI_GTX_C_MRX_P[0..15]
+1.5VS
C57 0.1U_0402_16V4Z
1 2
C62 0.1U_0402_16V4Z
1 2
C74 0.1U_0402_16V4Z
1 2
C78 0.1U_0402_16V4Z
1 2
C87 0.1U_0402_16V4Z
1 2
C97 0.1U_0402_16V4Z
1 2
C104 0.1U_0402_16V4Z
1 2
C114 0.1U_0402_16V4Z
1 2
C56 0.1U_0402_16V4Z
1 2
C60 0.1U_0402_16V4Z
1 2
C73 0.1U_0402_16V4Z
1 2
C77 0.1U_0402_16V4Z
1 2
C83 0.1U_0402_16V4Z
1 2
C92 0.1U_0402_16V4Z
1 2
C101 0.1U_0402_16V4Z
1 2
C110 0.1U_0402_16V4Z
1 2
1
PCIE_MTX_C_GRX_N0
PCIE_MTX_C_GRX_N1
PCIE_MTX_C_GRX_N2
PCIE_MTX_C_GRX_N3
PCIE_MTX_C_GRX_N5
PCIE_MTX_C_GRX_N6
PCIE_MTX_C_GRX_N7
PCIE_MTX_C_GRX_N8
PCIE_MTX_C_GRX_N9
PCIE_MTX_C_GRX_N10
PCIE_MTX_C_GRX_N11
PCIE_MTX_C_GRX_N12
PCIE_MTX_C_GRX_N13
PCIE_MTX_C_GRX_N14
PCIE_MTX_C_GRX_N15
PCIE_MTX_C_GRX_P0
PCIE_MTX_C_GRX_P1
PCIE_MTX_C_GRX_P2
PCIE_MTX_C_GRX_P3
PCIE_MTX_C_GRX_P4
PCIE_MTX_C_GRX_P5
PCIE_MTX_C_GRX_P6
PCIE_MTX_C_GRX_P7
PCIE_MTX_C_GRX_P8
PCIE_MTX_C_GRX_P9
PCIE_MTX_C_GRX_P10
PCIE_MTX_C_GRX_P11
PCIE_MTX_C_GRX_P12
PCIE_MTX_C_GRX_P13
PCIE_MTX_C_GRX_P14
PCIE_MTX_C_GRX_P15
A A
4.7K_0402_5%
LDDC_DATA
R397
+2.5VS
G
2
1 2
S
GMCH_LCD_DATA
13
D
Q43
5
2N7002_SOT23GM@
+3VS
R401
4.7K_0402_5%GM@
1 2
GMCH_LCD_DATA <16>
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SE CRET INFO RMATI ON. THIS SHEET MAY NO T BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
Alviso PCI-E(3/5)
EDL00 LA-2601
851Monday, November 15, 2004
1
0.1
of
5
4
3
2
1
U5E
+1.05VS
D D
C C
+1.5VS
+1.5VS_DPLLA
+1.5VS_DPLLB
+1.5VS_HPLL
+1.5VS_MPLL
B B
+1.5VS_DPLLA
1
2
+1.5VS_DPLLA
+1.5VS_DPLLB
+1.5VS_HPLL
+1.5VS_MPLL
60mA
C412
22U_1206_16V4Z_V1
T29
R29
N29
M29
K29
J29
V28
U28
T28
R28
P28
N28
M28
L28
K28
J28
H28
G28
V27
U27
T27
R27
P27
N27
M27
L27
K27
J27
H27
K26
H26
K25
J25
K24
K23
K22
K21
W20
U20
T20
K20
V19
U19
K19
W18
V18
T18
K18
K17
AC1
AC2
B23
C35
AA1
AA2
ALVISO_BGA1257
L6
CHB1608U301_0603
1 2
1
C418
2
0.1U_0402_16V4Z
VCC0
VCC1
VCC2
VCC3
VCC4
VCC5
VCC6
VCC7
POWER
VCC8
VCC9
VCC10
VCC11
VCC12
VCC13
VCC14
VCC15
VCC16
VCC17
VCC18
VCC19
VCC20
VCC21
VCC22
VCC23
VCC24
VCC25
VCC26
VCC27
VCC28
VCC29
VCC30
VCC31
VCC32
VCC33
VCC34
VCC35
VCC36
VCC37
VCC38
VCC39
VCC40
VCC41
VCC42
VCC43
VCC44
VCC45
VCC46
VCC47
VCC48
VCCD_HMPLL1
VCCD_HMPLL2
VCCA_DPLLA
VCCA_DPLLB
VCCA_HPLL
VCCA_MPLL
+1.5VS
+1.5VS_DPLLB
1
C426
2
22U_1206_16V4Z_V1
VCCA_TVDACA0
VCCA_TVDACA1
VCCA_TVDACB0
VCCA_TVDACB1
VCCA_TVDACC0
VCCA_TVDACC1
VCCA_TVBG
VSSA_TVBG
VCCD_TVDAC
VCCDQ_TVDAC
VCCD_LVDS0
VCCD_LVDS1
VCCD_LVDS2
VCCA_LVDS
VCCTX_LVDS0
VCCTX_LVDS1
VCCTX_LVDS2
VCCA_SM0
VCCA_SM1
VCCA_SM2
VCCA_SM3
VCCA_3GPLL0
VCCA_3GPLL1
VCCA_3GPLL2
VCCA_3GBG
VSSA_3GBG
VCC_SYNC
VCCA_CRTDAC0
VCCA_CRTDAC1
VSSA_CRTDAC
60mA
VCCHV0
VCCHV1
VCCHV2
VCC3G0
VCC3G1
VCC3G2
VCC3G3
VCC3G4
VCC3G5
VCC3G6
F17
E17
D18
C18
120mA
F18
E18
H18
G18
D19
H17
24mA
B26
B25
A25
60mA
A35
10mA
B22
B21
2mA
A21
B28
A28
60mA
A27
AF20
AP19
AF19
AF18
AE37
W37
U37
R37
1500mA
N37
L37
J37
Y29
Y28
Y27
F37
0.15mA
G37
H20
F19
E19
G19
L25
CHB1608U301_0603
1 2
1
C420
2
0.1U_0402_16V4Z
+3VS
+1.5VS
+2.5VS
+1.5VS_DDRDLL
+1.5VS_PEG
0.47U_0603_16V4Z
+1.5VS_3GPLL
+2.5VS_3GBG
+2.5VS
70mA
0.47U_0603_16V4Z
+1.5VS_DDRDLL
+1.5VS
+1.05VS
C23
1
2
1
C24
2
C49
0.22U_0402_10V4Z
0.22U_0402_10V4Z
1
C84
2
22U_1206_16V4Z_V1
C34
1
2
1
2
1
2
U5F
K13
VTT0
J13
VTT1
K12
VTT2
W11
VTT3
V11
VTT4
U11
VTT5
T11
VTT6
R11
VTT7
P11
VTT8
N11
VTT9
M11
VTT10
L11
VTT11
K11
VTT12
W10
VTT13
V10
VTT14
U10
VTT15
T10
VTT16
R10
VTT17
P10
VTT18
N10
VTT19
M10
VTT20
K10
VTT21
J10
VTT22
Y9
VTT23
W9
VTT24
U9
VTT25
R9
VTT26
P9
VTT27
N9
VTT28
M9
VTT29
L9
VTT30
J9
VTT31
N8
VTT32
M8
VTT33
N7
VTT34
M7
VTT35
N6
VTT36
M6
VTT37
A6
VTT38
N5
VTT39
M5
VTT40
N4
VTT41
M4
VTT42
N3
VTT43
M3
VTT44
N2
VTT45
M2
VTT46
B2
VTT47
V1
VTT48
N1
VTT49
M1
VTT50
G1
VTT51
ALVISO_BGA1257
R86
0_0603_5%
1 2
C496
0.1U_0402_16V4Z
POWER
+1.5VS_PEG
+1.5VS
1
2
VCCSM0
VCCSM1
VCCSM2
VCCSM3
VCCSM4
VCCSM5
VCCSM6
VCCSM7
VCCSM8
VCCSM9
VCCSM10
VCCSM11
VCCSM12
VCCSM13
VCCSM14
VCCSM15
VCCSM16
VCCSM17
VCCSM18
VCCSM19
VCCSM20
VCCSM21
VCCSM22
VCCSM23
VCCSM24
VCCSM25
VCCSM26
VCCSM27
VCCSM28
VCCSM29
VCCSM30
VCCSM31
VCCSM32
VCCSM33
VCCSM34
VCCSM35
VCCSM36
VCCSM37
VCCSM38
VCCSM39
VCCSM40
VCCSM41
VCCSM42
VCCSM43
VCCSM44
VCCSM45
VCCSM46
VCCSM47
VCCSM48
VCCSM49
VCCSM50
VCCSM51
VCCSM52
VCCSM53
VCCSM54
VCCSM55
VCCSM56
VCCSM57
VCCSM58
VCCSM59
VCCSM60
VCCSM61
VCCSM62
VCCSM63
VCCSM64
C446
22U_1206_16V4Z_V1
AM37
AH37
AP29
AD28
AD27
AC27
AP26
AN26
AM26
AL26
AK26
AJ26
AH26
AG26
AF26
AE26
AP25
AN25
AM25
AL25
AK25
AJ25
AH25
AG25
AF25
AE25
AE24
AE23
AE22
AE21
AE20
AE19
AE18
AE17
AE16
AE15
AE14
AP13
AN13
AM13
AL13
AK13
AJ13
AH13
AG13
AF13
AE13
AP12
AN12
AM12
AL12
AK12
AJ12
AH12
AG12
AF12
AE12
AD11
AC11
AB11
AB10
AB9
V1.8_DDR_CAP6
AP8
V1.8_DDR_CAP4
AM1
V1.8_DDR_CAP3
AE1
1
C449
2
4.7U_0805_10V4Z
V1.8_DDR_CAP1
V1.8_DDR_CAP2
V1.8_DDR_CAP5
C519
0.1U_0402_16V4Z
+DDRVCC
+DDRVCC
C88
330U_D2E_2.5VM
VCCA_LVDS (Ball A35)
VCC_SYNC(Ball H20)
C82
0.1U_0402_16V4Z
12
0.1U_0402_16V4Z
1
C439
2
4.7U_0805_10V4Z
12
2200mA
0.1U_0402_16V4Z
1
+
C494
2
+2.5VS
1
C417
2
0.1U_0402_16V4Z
+2.5VS
1
C22
2
4.7U_0805_10V4Z
C517
0.1U_0402_16V4Z
12
12
C490
R415
1 2
0_0805_5%
C505
0.1U_0402_16V4Z
12
C520
0.1U_0402_16V4Z
1
C487
2
0.1U_0402_16V4Z
1
C419
2
0.01U_0402_16V7K
1
C434
2
0.1U_0402_16V4Z
4.7U_0805_10V4Z
+1.5VS
1
+
C53
2
470U_D2_2.5VM
12
+1.05VS
C450
22U_1206_16V4Z_V1
0.1U_0402_16V4Z
1
2
C86
1
2
VCCHV(Ball A21,B21,B22)
+1.5VS
1
C20
C415
2
0.1U_0402_16V4Z
+1.05VS
1
C462
2
2.2U_0603_6.3V6K
VCCA_TVDAC VCCA_TVBG (Ball H18)
+3VS
4000mA
2.2U_0603_6.3V6K
1
C457
2
1
C498
2
0.1U_0402_16V4Z
1
C413
2
4.7U_0805_10V4Z
1
2
2.2U_0603_6.3V6K
0.1U_0402_16V4Z
C81
1
2
0.1U_0402_16V4Z
1
C451
C456
2
1
C481
2
0.1U_0402_16V4Z
C416
0.1U_0402_16V4Z
VCCA_CRTD AC(Ball F19 ,E19)
1
C424
2
0.1U_0402_16V4Z
1
C431
2
0.022U_0402_16V7K
VCCD_TVDAC (Ball D19)
0.1U_0402_16V4Z
C421
1
2
1
2
1
C425
2
0.022U_0402_16V7K
950mA
1
C463
2
2.2U_0603_6.3V6K
1
2
0.1U_0402_16V4Z
1
2
0.1U_0402_16V4Z
1
2
1
C21
2
4.7U_0805_10V4Z
1
C447
2
0.1U_0402_16V4Z
1
C483
2
0.1U_0402_16V4Z
C452
1
C486
2
1
C414
2
0.1U_0402_16V4Z
1
2
VCCTX_LVDS(Ball A27,A28,B28)
0.1U_0402_16V4Z
C440
1
2
1
C437
2
0.022U_0402_16V7K
VCCDQ_TVDAC (Ball H17)VCCD_LVDS(Ball A25,B25,B26)
1
C474
2.2U_0603_6.3V6K
C469
2
2.2U_0603_6.3V6K
1
+1.5VS_HPLL
A A
60mA
1
C50
2
22U_1206_16V4Z_V1
L7
CHB1608U301_0603
1 2
1
C478
2
0.1U_0402_16V4Z
5
+1.5VS
+1.5VS_MPLL
1
C52
2
22U_1206_16V4Z_V1
60mA
L8
CHB1608U301_0603
1 2
1
C482
2
0.1U_0402_16V4Z
+1.5VS
4
+1.5VS_3GPLL
1
C55
2
10U_1206_16V4Z
R79
0.5_0603_1%
1 2
1
C475
2
0.1U_0402_16V4Z
+1.5VS
+2.5VS_3GBG
1
2
1 2
R410 0_0603_5%
C428
0.1U_0402_16V4Z
+2.5VS
2
L9
CHB1608U301_0603
+3GPLL
1 2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SE CRET INFO RMATI ON. THIS SHEET MAY NO T BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
C432
2
0.1U_0402_16V4Z
1
C422
2
0.022U_0402_16V7K
1
C433
2
0.1U_0402_16V4Z
1
C438
2
0.022U_0402_16V7K
120mA
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
Alviso POWER(4/5)
EDL00 LA-2601
951Monday, November 15, 2004
1
of
0.1
5
4
3
2
1
U5H
+1.05VS
D D
C C
B B
+1.05VS
A A
L12
VTT_NCTF17
M12
VTT_NCTF16
N12
VTT_NCTF15
P12
VTT_NCTF14
R12
VTT_NCTF13
T12
VTT_NCTF12
U12
VTT_NCTF11
V12
VTT_NCTF10
W12
VTT_NCTF9
L13
VTT_NCTF8
M13
VTT_NCTF7
N13
VTT_NCTF6
P13
VTT_NCTF5
R13
VTT_NCTF4
T13
VTT_NCTF3
U13
VTT_NCTF2
V13
VTT_NCTF1
W13
VTT_NCTF0
Y12
VSS_NCTF68
AA12
VSS_NCTF67
Y13
VSS_NCTF66
AA13
VSS_NCTF65
L14
VSS_NCTF64
M14
VSS_NCTF63
N14
VSS_NCTF62
P14
VSS_NCTF61
R14
VSS_NCTF60
T14
VSS_NCTF59
U14
VSS_NCTF58
V14
VSS_NCTF57
W14
VSS_NCTF56
Y14
VSS_NCTF55
AA14
VSS_NCTF54
AB14
VSS_NCTF53
L15
VSS_NCTF52
M15
VSS_NCTF51
N15
VSS_NCTF50
P15
VSS_NCTF49
R15
VSS_NCTF48
T15
VSS_NCTF47
U15
VSS_NCTF46
V15
VSS_NCTF45
W15
VSS_NCTF44
Y15
VSS_NCTF43
AA15
VSS_NCTF42
AB15
VSS_NCTF41
L16
VSS_NCTF40
M16
VSS_NCTF39
N16
VSS_NCTF38
P16
VSS_NCTF37
R16
VSS_NCTF36
T16
VSS_NCTF35
U16
VSS_NCTF34
V16
VSS_NCTF33
W16
VSS_NCTF32
Y16
VSS_NCTF31
AA16
VSS_NCTF30
AB16
VSS_NCTF29
R17
VSS_NCTF28
Y17
VSS_NCTF27
AA17
VSS_NCTF26
AB17
VSS_NCTF25
AA18
VSS_NCTF24
AB18
VSS_NCTF23
AA19
VSS_NCTF22
AB19
VSS_NCTF21
AA20
VSS_NCTF20
AB20
VSS_NCTF19
R21
VSS_NCTF18
Y21
VSS_NCTF17
AA21
VSS_NCTF16
AB21
VSS_NCTF15
Y22
VSS_NCTF14
AA22
VSS_NCTF13
AB22
VSS_NCTF12
Y23
VSS_NCTF11
AA23
VSS_NCTF10
AB23
VSS_NCTF9
Y24
VSS_NCTF8
AA24
VSS_NCTF7
AB24
VSS_NCTF6
Y25
VSS_NCTF5
AA25
VSS_NCTF4
AB25
VSS_NCTF3
Y26
VSS_NCTF2
AA26
VSS_NCTF1
AB26
VSS_NCTF0
V25
VCC_NCTF10
W25
VCC_NCTF9
L26
VCC_NCTF8
M26
VCC_NCTF7
N26
VCC_NCTF6
P26
VCC_NCTF5
R26
VCC_NCTF4
T26
VCC_NCTF3
U26
VCC_NCTF2
V26
VCC_NCTF1
W26
VCC_NCTF0
ALVISO_BGA1257
5
VCCSM_NCTF31
VCCSM_NCTF30
VCCSM_NCTF29
VCCSM_NCTF28
VCCSM_NCTF27
VCCSM_NCTF26
VCCSM_NCTF25
VCCSM_NCTF24
VCCSM_NCTF23
VCCSM_NCTF22
VCCSM_NCTF21
VCCSM_NCTF20
VCCSM_NCTF19
VCCSM_NCTF18
VCCSM_NCTF17
VCCSM_NCTF16
VCCSM_NCTF15
VCCSM_NCTF14
VCCSM_NCTF13
VCCSM_NCTF12
VCCSM_NCTF11
VCCSM_NCTF10
VCCSM_NCTF9
VCCSM_NCTF8
VCCSM_NCTF7
VCCSM_NCTF6
VCCSM_NCTF5
VCCSM_NCTF4
VCCSM_NCTF3
VCCSM_NCTF2
VCCSM_NCTF1
VCCSM_NCTF0
VCC_NCTF78
VCC_NCTF77
VCC_NCTF76
VCC_NCTF75
VCC_NCTF74
VCC_NCTF73
VCC_NCTF72
VCC_NCTF71
VCC_NCTF70
NCTF
VCC_NCTF69
VCC_NCTF68
VCC_NCTF67
VCC_NCTF66
VCC_NCTF65
VCC_NCTF64
VCC_NCTF63
VCC_NCTF62
VCC_NCTF61
VCC_NCTF60
VCC_NCTF59
VCC_NCTF58
VCC_NCTF57
VCC_NCTF56
VCC_NCTF55
VCC_NCTF54
VCC_NCTF53
VCC_NCTF52
VCC_NCTF51
VCC_NCTF50
VCC_NCTF49
VCC_NCTF48
VCC_NCTF47
VCC_NCTF46
VCC_NCTF45
VCC_NCTF44
VCC_NCTF43
VCC_NCTF42
VCC_NCTF41
VCC_NCTF40
VCC_NCTF39
VCC_NCTF38
VCC_NCTF37
VCC_NCTF36
VCC_NCTF35
VCC_NCTF34
VCC_NCTF33
VCC_NCTF32
VCC_NCTF31
VCC_NCTF30
VCC_NCTF29
VCC_NCTF28
VCC_NCTF27
VCC_NCTF26
VCC_NCTF25
VCC_NCTF24
VCC_NCTF23
VCC_NCTF22
VCC_NCTF21
VCC_NCTF20
VCC_NCTF19
VCC_NCTF18
VCC_NCTF17
VCC_NCTF16
VCC_NCTF15
VCC_NCTF14
VCC_NCTF13
VCC_NCTF12
VCC_NCTF11
AB12
AC12
AD12
AB13
AC13
AD13
AC14
AD14
AC15
AD15
AC16
AD16
AC17
AD17
AC18
AD18
AC19
AD19
AC20
AD20
AC21
AD21
AC22
AD22
AC23
AD23
AC24
AD24
AC25
AD25
AC26
AD26
L17
M17
N17
P17
T17
U17
V17
W17
L18
M18
N18
P18
R18
Y18
L19
M19
N19
P19
R19
Y19
L20
M20
N20
P20
R20
Y20
L21
M21
N21
P21
T21
U21
V21
W21
L22
M22
N22
P22
R22
T22
U22
V22
W22
L23
M23
N23
P23
R23
T23
U23
V23
W23
L24
M24
N24
P24
R24
T24
U24
V24
W24
L25
M25
N25
P25
R25
T25
U25
+DDRVCC
+1.05VS
4
U5I
Y1
VSS271
D2
VSS270
G2
VSS269
J2
VSS268
L2
VSS260
P2
VSS259
T2
VSS258
V2
VSS257
AD2
VSS256
AE2
VSS255
AH2
VSS254
AL2
VSS253
AN2
VSS252
A3
VSS251
C3
VSS250
AA3
VSS249
AB3
VSS248
AC3
VSS247
AJ3
VSS246
C4
VSS245
H4
VSS244
L4
VSS243
P4
VSS242
U4
VSS241
Y4
VSS240
AF4
VSS239
AN4
VSS238
E5
VSS237
W5
VSS236
AL5
VSS235
AP5
VSS234
B6
VSS233
J6
VSS232
L6
VSS231
P6
VSS230
T6
VSS229
AA6
VSS228
AC6
VSS227
AE6
VSS226
AJ6
VSS225
G7
VSS224
V7
VSS223
AA7
VSS222
AG7
VSS221
AK7
VSS220
AN7
VSS219
C8
VSS218
E8
VSS217
L8
VSS216
P8
VSS215
Y8
VSS214
AL8
VSS213
A9
VSS212
H9
VSS211
K9
VSS210
T9
VSS209
V9
VSS208
AA9
VSS207
AC9
VSS206
AE9
VSS205
AH9
VSS204
AN9
VSS203
D10
VSS202
L10
VSS201
Y10
VSS200
AA10
VSS199
F11
VSS198
H11
VSS197
Y11
VSS196
ALVISO_BGA1257
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SE CRET INFO RMATI ON. THIS SHEET MAY NO T BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
VSS
3
VSSALVDS
VSS195
VSS194
VSS193
VSS192
VSS191
VSS190
VSS189
VSS188
VSS187
VSS186
VSS185
VSS184
VSS183
VSS182
VSS181
VSS180
VSS179
VSS178
VSS177
VSS176
VSS175
VSS174
VSS173
VSS172
VSS171
VSS170
VSS169
VSS168
VSS167
VSS166
VSS165
VSS164
VSS163
VSS162
VSS161
VSS160
VSS159
VSS158
VSS157
VSS156
VSS155
VSS154
VSS153
VSS152
VSS151
VSS150
VSS149
VSS148
VSS147
VSS146
VSS145
VSS144
VSS143
VSS142
VSS141
VSS140
VSS139
VSS138
VSS137
VSS136
VSS135
VSS134
VSS133
VSS132
VSS131
VSS130
B36
AA11
AF11
AG11
AJ11
AL11
AN11
B12
D12
J12
A14
B14
F14
J14
K14
AG14
AJ14
AL14
AN14
C15
K15
A16
D16
H16
K16
AL16
C17
G17
AF17
AJ17
AN17
A18
B18
U18
AL18
C19
H19
J19
T19
W19
AG19
AN19
A20
D20
E20
F20
G20
V20
AK20
C21
F21
AF21
AN21
A22
D22
E22
J22
AH22
AL22
H23
AF23
B24
D24
F24
J24
AG24
AJ24
2
AL24
AN24
A26
E26
G26
B27
E27
G27
W27
AA27
AB27
AF27
AG27
AJ27
AL27
AN27
E28
W28
AA28
AB28
AC28
A29
D29
E29
G29
H29
P29
U29
V29
W29
AA29
AD29
AG29
AJ29
AM29
C30
Y30
AA30
AB30
AC30
AE30
AP30
D31
E31
G31
H31
K31
M31
N31
P31
R31
U31
V31
W31
AD31
AG31
AL31
A32
C32
Y32
AA32
AB32
J26
F29
L29
F31
J31
L31
T31
U5J
VSS267
VSS266
VSS265
VSS264
VSS263
VSS262
VSS261
VSS129
VSS128
VSS127
VSS126
VSS125
VSS124
VSS123
VSS122
VSS121
VSS120
VSS119
VSS118
VSS117
VSS116
VSS115
VSS114
VSS113
VSS112
VSS111
VSS110
VSS109
VSS108
VSS107
VSS106
VSS105
VSS104
VSS103
VSS102
VSS101
VSS100
VSS99
VSS98
VSS97
VSS96
VSS95
VSS94
VSS93
VSS92
VSS91
VSS90
VSS89
VSS88
VSS87
VSS86
VSS85
VSS84
VSS83
VSS82
VSS81
VSS80
VSS79
VSS78
VSS77
VSS76
VSS75
VSS74
VSS73
VSS72
VSS71
VSS70
VSS69
VSS68
ALVISO_BGA1257
VSS
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
Alviso POWER(5/5)
EDL00 LA-2601
VSS67
VSS66
VSS65
VSS64
VSS63
VSS62
VSS61
VSS60
VSS59
VSS58
VSS57
VSS56
VSS55
VSS54
VSS53
VSS52
VSS51
VSS50
VSS49
VSS48
VSS47
VSS46
VSS45
VSS44
VSS43
VSS42
VSS41
VSS40
VSS39
VSS38
VSS37
VSS36
VSS35
VSS34
VSS33
VSS32
VSS31
VSS30
VSS29
VSS28
VSS27
VSS26
VSS25
VSS24
VSS23
VSS22
VSS21
VSS20
VSS19
VSS18
VSS17
VSS16
VSS15
VSS14
VSS13
VSS12
VSS11
VSS10
VSS9
VSS8
VSS7
VSS6
VSS5
VSS4
VSS3
VSS2
VSS1
VSS0
1
AC32
AD32
AJ32
AN32
D33
E33
F33
G33
H33
J33
K33
L33
M33
N33
P33
R33
T33
U33
V33
W33
AD33
AF33
AL33
C34
AA34
AB34
AC34
AD34
AH34
AN34
B35
D35
E35
F35
G35
H35
J35
K35
L35
M35
N35
P35
R35
T35
U35
V35
W35
Y35
AE35
C36
AA36
AB36
AC36
AD36
AE36
AF36
AJ36
AL36
AN36
E37
H37
K37
M37
P37
T37
V37
Y37
AG37
10 51Monday, November 15, 2004
0.1
of
5
DDR_A_D0
DDR_A_D1
DDR_A_DQS#0
DDR_A_DQS0
D D
C C
DDR_CKE0_DIMMA<6>
DDR_A_BS#2<7>
DDR_A_BS#0<7>
DDR_A_WE#<7>
DDR_A_CAS#<7>
DDR_CS1_DIMMA#<6>
M_ODT1<6>
B B
A A
D_CK_SDATA<12,14,38>
D_CK_SCLK<12,14,38>
5
DDR_A_D2
DDR_A_D3
DDR_A_D8
DDR_A_D9
DDR_A_DQS#1 M_CLK_DDR0
DDR_A_DQS1
DDR_A_D10
DDR_A_D11
DDR_A_D16
DDR_A_D17
DDR_A_DQS#2
DDR_A_DQS2
DDR_A_D18
DDR_A_D19
DDR_A_D24
DDR_A_D25
DDR_A_DM3
DDR_A_D26
DDR_A_D27
DDR_CKE0_DIMMA
DDR_A_BS#2
DDR_A_MA12
DDR_A_MA9 DDR_A_MA7
DDR_A_MA8
DDR_A_MA5
DDR_A_MA3
DDR_A_MA1
DDR_A_MA10
DDR_A_BS#0
DDR_A_WE#
DDR_A_CAS#
DDR_CS1_DIMMA#
M_ODT1
DDR_A_D32
DDR_A_D33
DDR_A_DQS#4
DDR_A_DQS4
DDR_A_D34
DDR_A_D35
DDR_A_D40
DDR_A_D41
DDR_A_DM5
DDR_A_D42
DDR_A_D43
DDR_A_D48
DDR_A_D49
DDR_A_DQS#6
DDR_A_DQS6
DDR_A_D50
DDR_A_D51
DDR_A_D56
DDR_A_D57
DDR_A_DM7
DDR_A_D58
DDR_A_D59
D_CK_SDATA
D_CK_SCLK
+3VS
C857
0.1U_0402_16V4Z
+DDRVCC +DDRVCC
JP24
1
VREF
3
VSS
5
DQ0
7
DQ1
9
VSS
11
DQS0#
13
DQS0
15
VSS
17
DQ2
19
DQ3
21
VSS
23
DQ8
25
DQ9
27
VSS
29
DQS1#
31
DQS1
33
VSS
35
DQ10
37
DQ11
39
VSS
41
VSS
43
DQ16
45
DQ17
47
VSS
49
DQS2#
51
DQS2
53
VSS
55
DQ18
57
DQ19
59
VSS
61
DQ24
63
DQ25
65
VSS
67
DM3
69
NC
71
VSS
73
DQ26
75
DQ27
77
VSS
79
CKE0
81
VDD
83
NC
85
BA2
87
VDD
89
A12
91
A9
93
A8
95
VDD
97
A5
99
A3
101
A1
103
VDD
105
A10/AP
107
BA0
109
WE#
111
VDD
113
CAS#
115
NC/S1#
117
VDD
119
NC/ODT1
121
VSS
123
DQ32
125
DQ33
127
VSS
129
DQS4#
131
DQS4
133
VSS
135
DQ34
137
DQ35
139
VSS
141
DQ40
143
DQ41
145
VSS
147
DM5
149
VSS
151
DQ42
153
DQ43
155
VSS
157
DQ48
159
DQ49
161
VSS
163
NC,TEST
165
VSS
167
DQS6#
169
DQS6
171
VSS
173
DQ50
175
DQ51
177
VSS
179
DQ56
181
DQ57
183
VSS
185
DM7
187
VSS
189
DQ58
191
DQ59
193
VSS
195
SDA
197
SCL
199
1 2
VDDSPD
JAE_MM50-200B1-1R~D
4
VSS
DQ4
DQ5
VSS
DM0
VSS
DQ6
DQ7
VSS
DQ12
DQ13
VSS
DM1
VSS
CK0
CK0#
VSS
DQ14
DQ15
VSS
VSS
DQ20
DQ21
VSS
DM2
VSS
DQ22
DQ23
VSS
DQ28
DQ29
VSS
DQS3#
DQS3
VSS
DQ30
DQ31
VSS
NC/CKE1
VDD
NC/A15
NC/A14
VDD
VDD
VDD
BA1
RAS#
VDD
ODT0
NC/A13
VDD
VSS
DQ36
DQ37
VSS
DM4
VSS
DQ38
DQ39
VSS
DQ44
DQ45
VSS
DQS5#
DQS5
VSS
DQ46
DQ47
VSS
DQ52
DQ53
VSS
CK1
CK1#
VSS
DM6
VSS
DQ54
DQ55
VSS
DQ60
DQ61
VSS
DQS7#
DQS7
VSS
DQ62
DQ63
VSS
SAO
SA1
4
A11
S0#
3
1
2
4.7U_0805_10V4Z
0.1U_0402_16V4Z
1
2
3
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
NC
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
A7
94
A6
96
98
A4
100
A2
102
A0
104
106
108
110
112
114
116
118
120
NC
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
DDR_A_D4
DDR_A_D5
DDR_A_DM0
DDR_A_D6
DDR_A_D7
DDR_A_D12
DDR_A_D13
DDR_A_DM1
M_CLK_DDR#0
DDR_A_D14
DDR_A_D15
DDR_A_D20
DDR_A_D21
DDR_A_DM2
DDR_A_D22
DDR_A_D23
DDR_A_D28
DDR_A_D29
DDR_A_DQS#3
DDR_A_DQS3
DDR_A_D30
DDR_A_D31
DDR_CKE1_DIMMA
DDR_A_MA11
DDR_A_MA6
DDR_A_MA4
DDR_A_MA2
DDR_A_MA0
DDR_A_BS#1
DDR_A_RAS#
DDR_CS0_DIMMA#
M_ODT0
DDR_A_MA13
DDR_A_D36
DDR_A_D37
DDR_A_DM4
DDR_A_D38
DDR_A_D39
DDR_A_D44
DDR_A_D45
DDR_A_DQS#5
DDR_A_DQS5
DDR_A_D46
DDR_A_D47
DDR_A_D52
DDR_A_D53
M_CLK_DDR1
M_CLK_DDR#1
DDR_A_DM6
DDR_A_D54
DDR_A_D55
DDR_A_D60
DDR_A_D61
DDR_A_DQS#7
DDR_A_DQS7
DDR_A_D62
DDR_A_D63
R692 10K_0402_5%
1 2
R693 10K_0402_5%
1 2
C840
M_CLK_DDR0 <6>
M_CLK_DDR#0 <6>
DDR_CKE1_DIMMA <6>
DDR_A_BS#1 <7>
DDR_A_RAS# <7>
DDR_CS0_DIMMA# <6>
M_ODT0 <6>
M_CLK_DDR1 <6>
M_CLK_DDR#1 <6>
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SE CRET INFO RMATI ON. THIS SHEET MAY NO T BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
+DDRVCC+DIMM_VREF
12
R92
C121
1K_0402_1%
12
R91
1K_0402_1%
+0.9V_DDR_VTT
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
2
C804
DDR_A_MA8
DDR_A_MA5
DDR_A_MA3
DDR_A_MA1
DDR_A_RAS#
DDR_CS0_DIMMA#
56_0404_4P2R_5%
DDR_A_MA10
DDR_A_BS#0
56_0404_4P2R_5%
DDR_A_WE#
DDR_A_CAS#
56_0404_4P2R_5%
M_ODT1
DDR_CS1_DIMMA#
56_0404_4P2R_5%
+DDRVCC
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
2
C806
1
2
C807
RP30
1 4
2 3
RP29
1 4
2 3
RP28
1 4
2 3
RP27
1 4
2 3
RP26
1 4
2 3
RP31
2 3
1 4
1
2
C805
Layout Note:
Place one cap close to every 2 pullup
resistors terminated to +0.9V_DDR_VTT
56_0404_4P2R_5%
56_0404_4P2R_5%
2
DDR_A_D[0..63]<7>
DDR_A_DM[0..7]<7>
DDR_A_DQS[0..7]<7>
DDR_A_MA[0..13]<7>
DDR_A_DQS#[0..7]<7>
C795
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
2
C808
+0.9V_DDR_VTT
2
1
C796
2
4.7U_0805_10V4Z
0.1U_0402_16V4Z
1
2
0.1U_0402_16V4Z
1
1
2
2
C809
RP59
RP58
RP57
RP35
RP34
RP33
RP32
1
C797
2
4.7U_0805_10V4Z
0.1U_0402_16V4Z
C800
1
2
0.1U_0402_16V4Z
1
2
C810
C811
DDR_CKE0_DIMMA
14
DDR_A_BS#2
23
56_0404_4P2R_5%
DDR_A_MA7
14
DDR_A_MA6
23
56_0404_4P2R_5%
DDR_A_MA12
14
DDR_A_MA9
23
56_0404_4P2R_5%
DDR_A_MA4
14
DDR_A_MA2
23
56_0404_4P2R_5%
DDR_A_MA0
14
DDR_A_BS#1
23
56_0404_4P2R_5%
M_ODT0
14
DDR_A_MA13
23
56_0404_4P2R_5%
DDR_CKE1_DIMMA
14
DDR_A_MA11
23
56_0404_4P2R_5%
1
DDR_A_D[0..63]
DDR_A_DM[0..7]
DDR_A_DQS[0..7]
DDR_A_MA[0..13]
DDR_A_DQS#[0..7]
Layout Note:
1
1
C798
2
4.7U_0805_10V4Z
4.7U_0805_10V4Z
0.1U_0402_16V4Z
C801
1
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
2
C812
Title
Size Document Number Rev
Date: Sheet
1
C799
2
2
4.7U_0805_10V4Z
0.1U_0402_16V4Z
C802
C803
1
2
0.1U_0402_16V4Z
1
1
2
2
C814
C813
Compal Electronics, Inc.
Place near DIMM
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
1
2
2
C815
C816
Layout Note:
Place these resistor
closely DIMM0,all
trace length<750 mil
Layout Note:
Place these resistor
closely DIMM0,all
trace length
Max=1.3"
DDR-SODIMM SLOT0
EDL00 LA-2601
1
of
11 51Monday, November 15, 2004
0.1
A
B
C
D
E
+DDRVCC
JP25
1
VREF
3
DDR_B_D0
DDR_B_D1
DDR_B_DQS#0
1 1
2 2
DDR_CKE2_DIMMB<6>
DDR_B_BS#2<7>
DDR_B_BS#0<7>
DDR_B_WE#<7>
DDR_B_CAS#<7>
DDR_CS3_DIMMB#<6>
M_ODT3<6>
3 3
4 4
D_CK_SDATA<11,14,38>
D_CK_SCLK<11,14,38>
A
DDR_B_DQS0
DDR_B_D2
DDR_B_D3
DDR_B_D8
DDR_B_D9
DDR_B_DQS#1
DDR_B_DQS1
DDR_B_D10
DDR_B_D11
DDR_B_D16
DDR_B_D17
DDR_B_DQS#2
DDR_B_DQS2
DDR_B_D18
DDR_B_D19
DDR_B_D24
DDR_B_D25
DDR_B_DM3
DDR_B_D26
DDR_B_D27
DDR_CKE2_DIMMB
DDR_B_BS#2
DDR_B_MA12
DDR_B_MA9
DDR_B_MA8
DDR_B_MA5
DDR_B_MA3
DDR_B_MA1
DDR_B_MA10
DDR_B_BS#0
DDR_B_WE#
DDR_B_CAS#
DDR_CS3_DIMMB#
M_ODT3
DDR_B_D32
DDR_B_D33
DDR_B_DQS#4
DDR_B_DQS4
DDR_B_D34
DDR_B_D35
DDR_B_D40
DDR_B_D41
DDR_B_DM5
DDR_B_D42
DDR_B_D43
DDR_B_D48
DDR_B_D49
DDR_B_DQS#6
DDR_B_DQS6
DDR_B_D50
DDR_B_D51
DDR_B_D56
DDR_B_D57
DDR_B_DM7
DDR_B_D58
DDR_B_D59
D_CK_SDATA
D_CK_SCLK
+3VS
C858
0.1U_0402_16V4Z
1 2
VSS
5
DQ0
7
DQ1
9
VSS
11
DQS0#
13
DQS0
15
VSS
17
DQ2
19
DQ3
21
VSS
23
DQ8
25
DQ9
27
VSS
29
DQS1#
31
DQS1
33
VSS
35
DQ10
37
DQ11
39
VSS
41
VSS
43
DQ16
45
DQ17
47
VSS
49
DQS2#
51
DQS2
53
VSS
55
DQ18
57
DQ19
59
VSS
61
DQ24
63
DQ25
65
VSS
67
DM3
69
NC
71
VSS
73
DQ26
75
DQ27
77
VSS
79
CKE0
81
VDD
83
NC
85
BA2
87
VDD
89
A12
91
A9
93
A8
95
VDD
97
A5
99
A3
101
A1
103
VDD
105
A10/AP
107
BA0
109
WE#
111
VDD
113
CAS#
115
NC/S1#
117
VDD
119
NC/ODT1
121
VSS
123
DQ32
125
DQ33
127
VSS
129
DQS4#
131
DQS4
133
VSS
135
DQ34
137
DQ35
139
VSS
141
DQ40
143
DQ41
145
VSS
147
DM5
149
VSS
151
DQ42
153
DQ43
155
VSS
157
DQ48
159
DQ49
161
VSS
163
NC,TEST
165
VSS
167
DQS6#
169
DQS6
171
VSS
173
DQ50
175
DQ51
177
VSS
179
DQ56
181
DQ57
183
VSS
185
DM7
187
VSS
189
DQ58
191
DQ59
193
VSS
195
SDA
197
SCL
199
VDDSPD
JAE_MM50-200B1-1~D
DQS3#
DQS3
NC/CKE1
NC/A15
NC/A14
RAS#
ODT0
NC/A13
DQS5#
DQS5
DQS7#
DQS7
VSS
DQ4
DQ5
VSS
DM0
VSS
DQ6
DQ7
VSS
DQ12
DQ13
VSS
DM1
VSS
CK0
CK0#
VSS
DQ14
DQ15
VSS
VSS
DQ20
DQ21
VSS
DM2
VSS
DQ22
DQ23
VSS
DQ28
DQ29
VSS
VSS
DQ30
DQ31
VSS
VDD
VDD
VDD
VDD
BA1
VDD
VDD
VSS
DQ36
DQ37
VSS
DM4
VSS
DQ38
DQ39
VSS
DQ44
DQ45
VSS
VSS
DQ46
DQ47
VSS
DQ52
DQ53
VSS
CK1
CK1#
VSS
DM6
VSS
DQ54
DQ55
VSS
DQ60
DQ61
VSS
VSS
DQ62
DQ63
VSS
SAO
SA1
A11
S0#
B
+DDRVCC
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
NC
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
A7
94
A6
96
98
A4
100
A2
102
A0
104
106
108
110
112
114
116
118
120
NC
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
DDR_B_D4
DDR_B_D5
DDR_B_DM0
DDR_B_D6
DDR_B_D7
DDR_B_D12
DDR_B_D13
DDR_B_DM1
M_CLK_DDR3
M_CLK_DDR#3
DDR_B_D14
DDR_B_D15
DDR_B_D20
DDR_B_D21
DDR_B_DM2
DDR_B_D22
DDR_B_D23
DDR_B_D28
DDR_B_D29
DDR_B_DQS#3
DDR_B_DQS3
DDR_B_D30
DDR_B_D31
DDR_CKE3_DIMMB
DDR_B_MA11
DDR_B_MA7
DDR_B_MA6
DDR_B_MA4
DDR_B_MA2
DDR_B_MA0
DDR_B_BS#1
DDR_B_RAS#
DDR_CS2_DIMMB#
M_ODT2
DDR_B_MA13
DDR_B_D36
DDR_B_D37
DDR_B_DM4
DDR_B_D38
DDR_B_D39
DDR_B_D44
DDR_B_D45
DDR_B_DQS#5
DDR_B_DQS5
DDR_B_D46
DDR_B_D47
DDR_B_D52
DDR_B_D53
M_CLK_DDR4
M_CLK_DDR#4
DDR_B_DM6
DDR_B_D54
DDR_B_D55
DDR_B_D60
DDR_B_D61
DDR_B_DQS#7
DDR_B_DQS7
DDR_B_D62
DDR_B_D63
R695 10K_0402_5%
1 2
R694 10K_0402_5%
1 2
+DIMM_VREF
0.1U_0402_16V4Z
1
1
C841
2
4.7U_0805_10V4Z
M_CLK_DDR3 <6>
M_CLK_DDR#3 <6>
DDR_CKE3_DIMMB <6>
DDR_B_BS#1 <7>
DDR_B_RAS# <7>
DDR_CS2_DIMMB# <6>
M_ODT2 <6>
M_CLK_DDR4 <6>
M_CLK_DDR#4 <6>
+3VS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SE CRET INFO RMATI ON. THIS SHEET MAY NO T BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C843
2
+0.9V_DDR_VTT
0.1U_0402_16V4Z
1
2
56_0404_4P2R_5%
56_0404_4P2R_5%
56_0404_4P2R_5%
56_0404_4P2R_5%
56_0404_4P2R_5%
56_0404_4P2R_5%
C
+DDRVCC
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
2
C827
Layout Note:
Place one cap close to every 2 pullup
resistors terminated to +0.9V_DDR_VTT
DDR_B_MA3
DDR_B_MA1
DDR_B_MA10
DDR_B_BS#0
DDR_B_MA0
DDR_B_BS#1
DDR_B_RAS#
DDR_CS2_DIMMB#
DDR_B_WE#
DDR_B_CAS#
M_ODT3
DDR_CS3_DIMMB#
0.1U_0402_16V4Z
C828
1
2
C829
1 4
2 3
1 4
2 3
1 4
2 3
1 4
2 3
1 4
2 3
2 3
1 4
0.1U_0402_16V4Z
DDR_B_D[0..63]<7>
DDR_B_DM[0..7]<7>
DDR_B_DQS[0..7]<7>
DDR_B_MA[0..13]<7>
DDR_B_DQS#[0..7]<7>
C817
4.7U_0805_10V4Z
C822
1
2
1
2
C830
+0.9V_DDR_VTT
RP71
RP70
RP69
RP68
RP67
RP56
1
C818
2
4.7U_0805_10V4Z
0.1U_0402_16V4Z
1
2
0.1U_0402_16V4Z
1
2
C831
D
1
1
C819
2
2
4.7U_0805_10V4Z
0.1U_0402_16V4Z
C823
C824
1
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
1
2
2
C832
RP66
14
23
56_0404_4P2R_5%
RP65
14
23
56_0404_4P2R_5%
RP64
14
23
56_0404_4P2R_5%
RP63
14
23
56_0404_4P2R_5%
RP62
14
23
56_0404_4P2R_5%
RP61
14
23
56_0404_4P2R_5%
RP60
14
23
56_0404_4P2R_5%
DDR_B_D[0..63]
DDR_B_DM[0..7]
DDR_B_DQS[0..7]
DDR_B_MA[0..13]
DDR_B_DQS#[0..7]
1
2
0.1U_0402_16V4Z
C825
0.1U_0402_16V4Z
C834
1
C821
4.7U_0805_10V4Z
C826
1
2
Layout Note:
Place near DIMM
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
1
2
2
C838
C837
Layout Note:
Place these resistor
closely DIMM0,all
trace length<750 mil
Layout Note:
Place these resistor
closely DIMM0,all
trace length
Max=1.3"
1
2
C835
0.1U_0402_16V4Z
1
2
C836
Compal Electronics, Inc.
DDR-SODIMM SLOT1
EDL00 LA-2601
0.1U_0402_16V4Z
1
2
C839
E
of
12 51Monday, November 15, 2004
C820
4.7U_0805_10V4Z
0.1U_0402_16V4Z
1
2
0.1U_0402_16V4Z
1
2
C833
DDR_B_MA12
DDR_B_MA9
DDR_CKE3_DIMMB
DDR_B_MA11
DDR_B_MA8
DDR_B_MA5
DDR_B_MA7
DDR_B_MA6
DDR_B_MA4
DDR_B_MA2
M_ODT2
DDR_B_MA13
DDR_CKE2_DIMMB
DDR_B_BS#2
Title
Size Document Number Rev
Date: Sheet
0.1
A
B
C
D
E
Layout note :
Distribute as clo se as possible
to DDR-SODIMM.
+DDRVCC
1 1
1
C117
0.1U_0402_16V4Z
2
1
C103
0.1U_0402_16V4Z
2
1
C122
0.1U_0402_16V4Z
2
1
C102
0.1U_0402_16V4Z
2
1
C99
0.1U_0402_16V4Z
2
+DDRVCC+DDRVCC
1
C118
0.1U_0402_16V4Z
2
1
C136
0.1U_0402_16V4Z
2
1
C119
0.1U_0402_16V4Z
2
1
C138
0.1U_0402_16V4Z
2
1
C137
0.1U_0402_16V4Z
2
2 2
3 3
1
C135
0.1U_0402_16V4Z
2
1
C124
0.1U_0402_16V4Z
2
1
C123
0.1U_0402_16V4Z
2
1
+
C85
150U_D2_6.3VM
2
1
+
C139
150U_D2_6.3VM
2
4 4
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SE CRET INFO RMATI ON. THIS SHEET MAY NO T BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
D
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
DDR SODIMM Decoupling
EDL00 LA-2601
Monday, November 15, 2004
E
of
13 51
0.1
A
FSC FSB FSA CPU
CLKSEL0 CLKSEL1 CLKSEL2
*
1 1
0
0
0
0
1
1
+3VS
1 2
R139 10K_0402_5%
1 2
R153 10K_0402_5%
1 2
R145 10K_0402_5%
1 2
R141 10K_0402_5%
2 2
CLK_PCI0 = 0, Pin 35,36
are PCIe CLK pair
CLK_PCI1 = 0, Pin 17,18
are 96Mhz
3 3
4 4
R460
4.7K_0402_5%
CLKSEL0 CLKSEL1
1 2
1 2
R458
0_0402_5%@
CLKSEL2
CLK_PCI2
CLK_PCI0
CLK_PCI1
CK_SCLK<19>
CK_SDATA<19>
+1.05VS +1.05VS
R456
1 2
R459
0_0402_5%
A
11
1
1
00
CLK_PCI2 = 1, Pin 32,33
are PEREQ# pin
CLK_ICH_48M<19>
CLK_SD_48M<23>
CLK_14M_CODEC<29>
+3VS
2
1 3
D
+3VS
2
1 3
D
1K_0402_5%@
R457
0_0402_5%
1 2
12
33P_0402_50V8J
CLK_PCI_PCM<23>
CLK_PCI_LAN<26>
CLK_PCI_MINI<28>
CLK_PCI_SIO<32>
CLK_PCI_1394<25>
CLK_PCI_LPC<33>
CLK_PCI_ICH<17>
G
G
B
SRC
MHz
MHz
100
100 33.3
100
133
100
166
100
200
Table : ICS 954206B
C162
14.318MHZ_16PF_DSX840GA
1 2
C161
33P_0402_50V8J
1 2
CLK_ICH_48M
CLK_14M_CODEC CLKSEL0
D_CK_SCLK<11,12,38>
D_CK_SDATA<11,12,38>
R462
4.7K_0402_5%
1 2
S
Q16
2N7002_SOT23
R461
4.7K_0402_5%
1 2
D_CK_SDATA
S
Q17
2N7002_SOT23
MCH_CLKSEL0 <6>
+3VS
D_CK_SCLK
+3VS
B
C
+CLK_VDD48 +CLK_VDDREF
PCI
MHz
1
C555
2
2.2U_0603_6.3V6K
1
C157
2
0.047U_0402_16V7K
33.3
33.3
33.3
Y1
12
CLK_PCI_MINI CLK_PCI4
CLK_PCI_ICH
D_CK_SCLK
D_CK_SDATA
+CLK_VDD2
1 2
R135 1_0402_5%
1 2
R455 2.2_0402_5%
R143 12_0402_5%
1 2
R147 12_0402_5%
1 2
R151 12_0402_5%
R451
0_0402_5%@
12
R77 12_0402_5%
1 2
1 2
R71 12_0402_5%
1 2
R150 33_0402_5%
1 2
R149 33_0402_5%
1 2
R154 33_0402_5%
1 2
R142 33_0402_5%
1 2
R146 33_0402_5%
1 2
R452 475_0402_1%
R454
R453
4.7K_0402_5%
1 2
1 2
1 2
R448
0_0402_5%
+CLK_VDDREF
+CLK_VDD48
1K_0402_5%@
R450
0_0402_5%
1 2
C
+CLK_VDD1
+CLK_VDD1
XTALIN
XTALOUT
CLKSEL2CLK_SD_48M
CLKSEL1
CLK_PCI5CLK_PCI_LAN
CLK_PCI3CLK_PCI_SIO
CLK_PCI2CLK_PCI_1394
CLK_PCI1CLK_PCI_LPC
CLK_PCI0
CLKIREF
12
1
C156
0.047U_0402_16V7K
2
U8
21
VDDPCIEX_0
28
VDDPCIEX_1
34
VDDPCIEX_2
1
VDDPCI_0
7
VDDPCI_1
42
VDDCPU
48
VDDREF
15mil
11
VDD48
15mil
50
X1
49
X2
12
FS_A/USB_48MHz
53
REF1/FSLC/TEST_SEL
16
FSLB/TEST_MODE
5
PCICLK5
4
PCICLK4
3
PCICLK3
56
PCICLK2/REQ_SEL
9
SELPCIEX_LCDCLK#/PCICLK_F1
8
ITP_EN/PCICLK_F0
46
SCLK
47
SDATA
39
IREF
15mil
13
GND_0
29
GND_1
2
GND_2
45
GND_3
51
GND_4
6
GND_5
ICS954226AGT_TSSOP56
MCH_CLKSEL1 <6>
CPU_BSEL1 <5>CPU_BSEL0 <5>
D
L10
KC FBM-L11-201209-221LMAT_0805
1 2
+3VS
VDDA
GNDA
PCI/SRC_STOP#
CPU_STOP#
CPUCLKT1
CPUCLKC1
CPUCLKT0
CPUCLKC0
CPUCLKT2_ITP/PCIEXT6
CPUCLKC2_ITP/PCIEXC6
PEREQ1#/PCIEXT5
PEREQ2#/PCIEXC5
PCIEXT4
PCIEXC4
SATACLKT
SATACLKC
PCIEXT3
PCIEXC3
PCIEXT2
PCIEXC2
PCIEXT1
PCIEXC1
LCDCLK_SS/PCIEX0T
LCDCLK_SS/PCIEX0C
DOTT_96MHz
DOTC_96MHz
VTT_PWRGD#/PD
REF0
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SE CRET INFO RMATI ON. THIS SHEET MAY NO T BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
D
E
1
C144
2.2U_0603_6.3V6K
2
1
37
38
55
54
41
40
44
43
36
35
33
32
31
30
26
27
24
25
22
23
19
20
17
18
14
15
10
52
2
STP_PCI#
STP_CPU#
CLK_CPU1
CLK_CPU1#
CLK_CPU0
CLK_CPU0#
CLK_SRC3
CLK_SRC3# CLK_MCH_3GPLL#
PEREQ1#
PEREQ2# PE_REQ2#
CLK_SRC2#
CLK_SRC4
CLK_SRC4#
CLK_SRC6
CLK_SRC6#
CLK_SRC7
CLK_SRC7#
CLK_SRC1
CLK_SRC1#
CLK_SRC0
CLK_SRC0#
CLK_DOT
CLK_DOT#
CLK_REF CLK_14M_SIO
E
1
C149
0.047U_0402_16V7K
2
+CLK_VCCA
40mil
C553
2.2U_0603_6.3V6K
R124 33_0402_5%
R120 33_0402_5%
R134 33_0402_5%
R128 33_0402_5%
R106 33_0402_5%
R102 33_0402_5%
R684 0_0402_5%
R685 0_0402_5%
R114 33_0402_5%
R110 33_0402_5%
R100 33_0402_5%
R96 33_0402_5%
R678 33_0402_5%
R679 33_0402_5%
R113 33_0402_5%
R109 33_0402_5%
R121 33_0402_5%
R117 33_0402_5%
R129 33_0402_5%
R125 33_0402_5%
R136 33_0402_5%
R131 33_0402_5%
1 2
R144 12_0402_5%
1 2
R148 12_0402_5%
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1
2
F
1 2
R449
2.2_0402_5%
C150
0.047U_0402_16V7K
PM_STP_PCI# <19>
PM_STP_CPU# <19,48>
CLK_ICH_14M
F
1
C145
0.047U_0402_16V7K
2
+CLK_VDD1
CLK_MCH_BCLK
CLK_MCH_BCLK#
CLK_CPU_BCLK
CLK_CPU_BCLK#
CLK_MCH_3GPLL
PE_REQ1#
CLK_PCIE_VGACLK_SRC2
CLK_PCIE_VGA#
CLK_PCIE_SATA
CLK_PCIE_SATA#
CLK_EZ_CLK2
CLK_EZ_CLK2#
CLK_EZ_CLK1
CLK_EZ_CLK1#
CLK_PCIE_ICH
CLK_PCIE_ICH#
CLK_DREF_SSC
CLK_DREF_SSC#
CLK_DREF_96M
CLK_DREF_96M#
1 2
+3VS
R138 10K_0402_5%
VTT_POWERGD#
CLK_14M_SIO <32>
CLK_ICH_14M <19>
+3VS
G
40mil
+CLK_VDD1
1
C147
0.047U_0402_16V7K
2
L11
KC FBM-L11-201209-221LMAT_0805
1 2
CLK_MCH_BCLK <6>
CLK_MCH_BCLK# <6>
CLK_CPU_BCLK <4>
CLK_CPU_BCLK# <4>
CLK_MCH_3GPLL <8>
CLK_MCH_3GPLL# <8>
PE_REQ1# <33>
PE_REQ2# <33>
CLK_PCIE_VGA <16>
CLK_PCIE_VGA# <16>
CLK_PCIE_SATA <18>
CLK_PCIE_SATA# <18>
CLK_EZ_CLK2 <38>
CLK_EZ_CLK2# <38>
CLK_EZ_CLK1 <38>
CLK_EZ_CLK1# <38>
CLK_PCIE_ICH <19>
CLK_PCIE_ICH# <19>
CLK_DREF_SSC <6>
CLK_DREF_SSC# <6>
CLK_DREF_96M <6>
CLK_DREF_96M# <6>
Title
Size Document Number Rev
Date: Sheet
1
C152
0.047U_0402_16V7K
2
1
C165
2
2.2U_0603_6.3V6K
2
G
1 3
D
S
Q14
2N7002_SOT23
Compal Electronics, Inc.
Monday, November 15, 2004
G
Clock Generator
40mil
1
C159
2
0.047U_0402_16V7K
CLK_MCH_BCLK
CLK_MCH_BCLK#
CLK_CPU_BCLK
CLK_CPU_BCLK#
CLK_EZ_CLK1
CLK_EZ_CLK1#
CLK_PCIE_SATA
CLK_PCIE_SATA#
CLK_MCH_3GPLL
CLK_MCH_3GPLL#
CLK_PCIE_VGA
CLK_PCIE_VGA#
CLK_PCIE_ICH
CLK_PCIE_ICH#
CLK_DREF_SSC
CLK_DREF_SSC#
CLK_DREF_96M
CLK_DREF_96M#
CLK_EZ_CLK2
CLK_EZ_CLK2#
VGATE <6,19,48>
Clock Generator
EDL00 LA-2601
H
+CLK_VDD2
1
C163
2
0.047U_0402_16V7K
1 2
R123 49.9_0402_1%
1 2
R119 49.9_0402_1%
1 2
R133 49.9_0402_1%
1 2
R127 49.9_0402_1%
1 2
R112 49.9_0402_1%
1 2
R108 49.9_0402_1%
1 2
R101 49.9_0402_1%
1 2
R97 49.9_0402_1%
1 2
R107 49.9_0402_1%
1 2
R103 49.9_0402_1%
1 2
R115 49.9_0402_1%
1 2
R111 49.9_0402_1%
1 2
R122 49.9_0402_1%
1 2
R118 49.9_0402_1%
1 2
R130 49.9_0402_1%
1 2
R126 49.9_0402_1%
1 2
R137 49.9_0402_1%
1 2
R132 49.9_0402_1%
1 2
R680 49.9_0402_1%
1 2
R681 49.9_0402_1%
14 51
H
0.1
of
A
CRT Connector
U4
1 1
R34 0_0402_5%PM@
VGA_CRT_R<16>
GMCH_CRT_R<8>
VGA_CRT_G< 16>
GMCH_CRT_G<8>
VGA_CRT_B<16>
GMCH_CRT_B<8>
2 2
1 2
1 2
R33 0_0402_5%GM@
R32 0_0402_5%PM@
1 2
1 2
R21 0_0402_5%GM@
R19 0_0402_5%PM@
1 2
1 2
R18 0_0402_5%GM@
DOCKIN#<22,27,33,38>
DOCKIN#
VGA_CRT_HSYNC<16>
GMCH_CRT_HSYNC<8>
1
SEL
15
OE#
4
1A
7
2A
9
3A
12
4A
8
GND
FSAV330MTC_TSSOP16
VCC
1B1
2B1
3B1
4B1
1B2
2B2
3B2
4B2
1 2
R8 0_0402_5%PM@
1 2
R7 39_0402_5%GM@
VGA_CRT_VSYNC<16>
GMCH_CRT_VSYNC<8>
B
+5VS
1 2
C18
16
D_CRT_R
2
D_CRT_G
5
D_CRT_B
11
14
3
6
10
13
R1
150_0402_5%
C10 0.1U_0402_16V4Z
C
0.1U_0402_16V4Z
D_CRT_R <38>
D_CRT_G <38>
D_CRT_B <38>
CRT_R CRT_R_L
CRT_G
CRT_B
12
12
R2
150_0402_5%
1 2
1 2
R377 0_0402_5%PM@
1 2
R378 39_0402_5%GM@
12
R3
150_0402_5%
CRT_HSYNC D_CRT_HSYNC
1
C9
2
8P_0402_50V8K
+CRT_VCC
1
5
P
4
OE#
A2Y
G
U1
SN74AHCT1G125GW_SOT353-5
3
1 2
C410 0.1U_0402_16V4Z
1
C8
2
8P_0402_50V8K
R6 10K_0402_5%
+CRT_VCC
1
5
CRT_VSYNC D_CRT_VSYNC
P
4
OE#
A2Y
G
U35
SN74AHCT1G125GW_SOT353-5
3
+3VS
1 2
L3
FCM2012C-800_0805
1 2
L4
FCM2012C-800_0805
1 2
L5
FCM2012C-800_0805
1
C7
8P_0402_50V8K
2
8P_0402_50V8K
10P for GMCH
12
CRT_G_L
CRT_B_L
C1
D23
DAN217_SC59@
1
2
3
1
C2
2
8P_0402_50V8K
1 2
L1 FCM1608C-121T_0603
1 2
L2 FCM1608C-121T_0603
D
D22
DAN217_SC59@
1
2
3
1
2
10P_0402_50V8J
33P for GMCH
D_CRT_HSYNC <38>
D_CRT_VSYNC <38>
1
2
3
1
C3
8P_0402_50V8K
2
1
C5
2
D21
DAN217_SC59@
HSYNC_L
VSYNC_L
+5VS
RB411D_SOT23
1
C6
10P_0402_50V8J
2
D1
2 1
W=40mils
POLYSWITCH_1A
0.1U_0402_16V4Z
DDC_MD2
C408
100P_0402_25V8K
1
2
C409
68P_0402_50V8K
F1
C4
E
W=40mils
1
2
DSUB_12
DSUB_15
1
C407
68P_0402_50V8K
2
6
11
1
7
12
2
8
13
3
9
14
4
10
15
5
+CRT_VCC+R_CRT_VCC
JP1
CRT-15P
(CL55)
3 3
D_DDC_DATA<38>
D_DDC_CLK<38>
4 4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SE CRET INFO RMATI ON. THIS SHEET MAY NO T BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
4.7K_0402_5%
DSUB_15
+CRT_VCC
R4
12
4.7K_0402_5%
12
R5
Q1
BSS138_SOT23
D
R9 0_0402_5%PM@
1 2
R10 0_0402_5%GM@
1 2
2
G
1 3
D
S
2
1 3
D
Q2
BSS138_SOT23
+3VS
+2.5VS
R11 0_0402_5%GM@
12
VGA_DDC_DATADSUB_12
G
VGA_DDC_CLK
S
12
R12
0_0402_5%GM@
Title
Size Document Number Rev
Date: Sheet
Monday, November 15, 2004
GMCH_CRT_DATA <8>
VGA_DDC_DATA <16>
VGA_DDC_CLK <16>
GMCH_CRT_CLK <8>
Compal Electronics, Inc.
CRT & TVout Connector
EDL00 LA-2601
E
15 51
of
0.1
5
LCD POWER CIRCUIT
GMCH_ENVDD<8>
D D
C C
B B
+LCDVDD
12
R53
301_0402_1%GM@
13
D
Q8
2N7002_SOT23GM@
S
0.01U_0402_16V7KGM@
2
G
BKOFF#<33>
GMCH_ENVDD
+3VALW
C860
1
2
5
P
A2Y
G
3
U33
1
SN74AHCT1G125GW_SOT353-5GM@
4
OE#
R62
100_0402_5%GM@
1
+3VS
R55
100K_0402_5%GM@
1 2
C27
2
0.047U_0402_16V7KGM@
1
C19
0.1U_0402_16V4Z@
2
BKOFF# DISPO FF#
D32
RB751V_SOD323
21
LCD/PANEL BD. Conn.
JP6
B+
+3VS
GMCH_LCD_CLK<8>
GMCH_LCD_DATA<8>
GMCH_TZOUT0-<8>
GMCH_TZOUT0+<8>
GMCH_TZOUT1+<8>
GMCH_TZOUT1-<8>
GMCH_TZOUT2+<8>
GMCH_TZOUT2-<8>
GMCH_TZCLK-<8>
A A
GMCH_TZCLK+<8>
GMCH_LCD_CLK
GMCH_LCD_DATA
GMCH_TZOUT0-
GMCH_TZOUT1+
GMCH_TZOUT1GMCH_TZOUT2+
GMCH_TZOUT2-
GMCH_TZCLKGMCH_TZCLK+
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
2
1
2
4
3
4
6
5
6
8
7
8
10
9
10
12
11
12
14
13
14
16
15
16
18
17
18
20
19
20
22
21
22
24
23
24
26
25
26
28
27
28
30
29
30
32
31
32
34
33
34
36
35
36
38
37
38
40
39
40
ACES_87216-4012GM@
1 2
4
+3VS
2
1 3
1
C28
2
+3VS
12
R477
4.7K_0402_5%
DAC_BRIG
INVT_PWM
DISPOFF#
GMCH_TXOUT0GMCH_TXOUT0+GMCH_TZOUT0+
GMCH_TXOUT1GMCH_TXOUT1+
GMCH_TXOUT2+
GMCH_TXOUT2-
GMCH_TXCLKGMCH_TXCLK+
Q9
SI2301DS_SOT23GM@
4.7U_0805_10V4ZGM@
DAC_BRIG <33>
INVT_PWM <33>
B+
0.1U_0402_25V4K
1
C866
2
+LCDVDD
1
C29
2
+LCDVDD
GMCH_TXOUT0- <8>
GMCH_TXOUT0+ <8>
GMCH_TXOUT1- <8>
GMCH_TXOUT1+ <8>
GMCH_TXOUT2+ <8>
GMCH_TXOUT2- <8>
GMCH_TXCLK- <8>
GMCH_TXCLK+ <8>
3
1
C867
2
0.1U_0402_25V4K
0.1U_0402_25V4K
1
2
0.1U_0402_25V4K
C868
0.1U_0402_25V4K
1
C869
2
Bypass CAP under B+ trace(+25V)
0.1U_0402_16V4ZGM@
PLTRST_VGA#<19>
2
PCEI_GTX_C_MRX_N[0..15]<8>
PCEI_GTX_C_MRX_P[0..15]<8>
1
C870
2
PCIE_MTX_C_GRX_N[0..15]<8>
PCIE_MTX_C_GRX_P[0..15]<8>
PCEI_GTX_C_MRX_N[0..15]
PCEI_GTX_C_MRX_P[0..15]
PCIE_MTX_C_GRX_N[0..15]
PCIE_MTX_C_GRX_P[0..15]
1
VGA BOARD Conn.
B+
DAC_BRIG
DISPOFF#
INVT_PWM
VGA_CRT_R<15>
VGA_CRT_G< 15>
VGA_CRT_B<15> VGA_CRT_HSYNC <15>
DVI_TXC+<22>
DVI_TXC-<22>
DVI_TXD0+<22>
DVI_TXD0-<22>
DVI_TXD1+<22>
DVI_TXD1-<22>
DVI_TXD2+<22>
DVI_TXD2-<22>
R510 0_0402_5%
GMCH_ENBKL<8,33>
VGA_CRT_R
VGA_CRT_G
VGA_CRT_B VGA_CRT_HSYNC
+3VALW
+2.5VS
1 2
GMCH_ENBKL
PCIE_MTX_C_GRX_P0
PCIE_MTX_C_GRX_N0
PCIE_MTX_C_GRX_P1
PCIE_MTX_C_GRX_N1
PCIE_MTX_C_GRX_P2
PCIE_MTX_C_GRX_N2
PCIE_MTX_C_GRX_P3
PCIE_MTX_C_GRX_N3
PCIE_MTX_C_GRX_P4
PCIE_MTX_C_GRX_N4
PCIE_MTX_C_GRX_P5
PCIE_MTX_C_GRX_N5
PCIE_MTX_C_GRX_P6
PCIE_MTX_C_GRX_N6
PCIE_MTX_C_GRX_P7
PCIE_MTX_C_GRX_N7
PCIE_MTX_C_GRX_P8
PCIE_MTX_C_GRX_N8
PCIE_MTX_C_GRX_P9
PCIE_MTX_C_GRX_N9
PCIE_MTX_C_GRX_P10
PCIE_MTX_C_GRX_N10
PCIE_MTX_C_GRX_P11
PCIE_MTX_C_GRX_N11
PCIE_MTX_C_GRX_P12
PCIE_MTX_C_GRX_N12
PCIE_MTX_C_GRX_P13
PCIE_MTX_C_GRX_N13
PCIE_MTX_C_GRX_P14
PCIE_MTX_C_GRX_N14
PCIE_MTX_C_GRX_P15
PCIE_MTX_C_GRX_N15
JP11
1 2
3 4
5 6
7 8
9 10
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
29 30
31 32
33 34
35 36
37 38
39 40
41 42
43 44
45 46
47 48
49 50
51 52
53 54
55 56
57 58
59 60
61 62
63 64
65 66
67 68
69 70
71 72
73 74
75 76
77 78
79 80
81 82
83 84
85 86
87 88
89 90
91 92
93 94
95 96
97 98
99 100
101 102
103 104
105 106
107 108
109 110
111 112
113 114
115 116
117 118
119 120
121 122
123 124
125 126
127 128
129 130
131 132
133 134
135 136
137 138
139 140
141 142
143 144
145 146
147 148
149 150
151 152
153 154
155 156
157 158
159 160
ACES_88081-1600
VGA_DDC_CLK
VGA_DDC_DATA
VGA_TV_LUMA
VGA_TV_CRMA
VGA_TV_COMPS
SUSP#
VGA_CRT_VSYNC
+3VS
+5VALW
SDVO_SCLK
SDVO_SDAT
PCEI_GTX_C_MRX_P0
PCEI_GTX_C_MRX_N0
PCEI_GTX_C_MRX_P1
PCEI_GTX_C_MRX_N1
PCEI_GTX_C_MRX_P2
PCEI_GTX_C_MRX_N2
PCEI_GTX_C_MRX_P3
PCEI_GTX_C_MRX_N3
PCEI_GTX_C_MRX_P4
PCEI_GTX_C_MRX_N4
PCEI_GTX_C_MRX_P5
PCEI_GTX_C_MRX_N5
PCEI_GTX_C_MRX_P6
PCEI_GTX_C_MRX_N6
PCEI_GTX_C_MRX_P7
PCEI_GTX_C_MRX_N7
PCEI_GTX_C_MRX_P8
PCEI_GTX_C_MRX_N8
PCEI_GTX_C_MRX_P9
PCEI_GTX_C_MRX_N9
PCEI_GTX_C_MRX_P10
PCEI_GTX_C_MRX_N10
PCEI_GTX_C_MRX_P11
PCEI_GTX_C_MRX_N11
PCEI_GTX_C_MRX_P12
PCEI_GTX_C_MRX_N12
PCEI_GTX_C_MRX_P13
PCEI_GTX_C_MRX_N13
PCEI_GTX_C_MRX_P14
PCEI_GTX_C_MRX_N14
PCEI_GTX_C_MRX_P15
PCEI_GTX_C_MRX_N15
B+
VGA_DDC_CLK <15>
VGA_DDC_DATA <15>
VGA_TV_LUMA <22>
VGA_TV_CRMA <22>
VGA_TV_COMPS <22>
SUSP# <33,35,40,47>
VGA_CRT_VSYNC <15>
+1.5VS
DVI_DET <22>
DVI_SCLK <22>
DVI_SDATA <22>
+5VS
SDVO_SCLK <8>
SDVO_SDAT <8>
CLK_PCIE_VGA <14>
CLK_PCIE_VGA# <14>
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SE CRET INFO RMATI ON. THIS SHEET MAY NO T BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
VGA / LCD CONN.
EDL00 LA-2601
Monday, November 15, 2004
1
of
16 51
0.1
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