COMPAL LA-2591 Schematics

A

1 1

B

C

D

E

2 2

Compal confidential

Schematics Document

Mobile Dothan uFCPGA with Intel
Alviso_GM+ICH6-M core logic

3 3

2004-10-08

LA-2591

REV:01

4 4

Title

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

D

Size Document Number Rev
Custom

Date: Sheet

Compal Electronics, Inc.

Cover Sheet

LA-2591

E

0.1

of

143Monday, October 11, 2004

A

B

C

D

E

Compal confidential

File Name : LA-2591

VRAM
128MByte

1 1

LVDS CONN

page 16

2 2

M/B-S/B CONN
LS-2594

TV-OUT / CRT

page 28

page 17

Gigabit LAN

RTL8110SBL/
8100CL

RJ45/11 CONN

page 24

page 24

conn

Mini PCI
socket

3 3

RTC CKT.

page 19

Power On/Off CKT.

page 34

4 4

DC/DC Int erface CKT.

page 35

Power Circuit DC/DC

36,37,38,39,40,41,42

A

(32MByte*4)

DDR300/300

M/B-NV44M VGA/B
CONN

LS-2591

page 16

PCI BUS

IEEE1394
TSB43AB21

page 27

M/B-S/B CONN
LS-2595

1394 conn

page 32

Fan Control

page 15

PCI-E

CardBus Controller

CB-714

page 25

Slot 0

page 26

B

4in1 Slot

page 25

M/B-S/B CONN
LS-2593

Touch Pad CONN.

Mobile Dothan/Yonah
uFCPGA-478 CPU

H_A#(3..31)

FSB

400/533MHz

Intel Alviso GMCH

PCBGA 1257

page 7,8,9,10,11

PCI-E(DMI)

Intel ICH6-M

mBGA-609

page 19,20,21,22

LPC BUS

EC KB910L

page 32

Clock Generator

ICS 954226

page 18

DDR BANK0 32M*16*4
DDR-SO-DIMM1

page 12,13,14

page 4,5,6

H_D#(0..63)

Thermal Sensor
ADM1031AR

page 15

DDR1 -333

One Channel

M/B-S/B CONN
LS-2594
Camera/BlueTooth

USB2.0

conn

page 17

M/B-S/B CONN
LS-2595

USB2.0

AC-LINK

IDEBUS

page 33

Int.KBD

page 33

Flash ROM

SST39VF080-70

page 34

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

USB conn x2

USB conn x2

Audio CKT
ALC250-VC

IDE HDD
Connector

page 23

LS-2592 SWDJ/B List:
SWDJ switch Button * 5
WL/BT on/foff Button *1
WL/BT LED *1

LS-2594 CRT/TV-OUT List:
CRT conn * 1
TV-OUT conn * 1
USB conn * 2
BlueTooth conn * 1
Num LED * 1
CAP LED * 1
Scroll LED * 1
Lid Switch * 1

LS-2595 USB&1394/B List:
USB conn* 2
1395 conn * 1

D

page 32

page 32

page 29

IDE ODD
Connector

page 23

MODEM
AGERE CPS1038

page 30

AMP & Audio Jack
APA2121

SubBoard CONN List:
LS-2591 VGA/B conn
LS-2592 SWDJ/B conn
LS-2593 TP/B conn
LS-2594 CRT/TV-OUT conn
LS-2595 USB&1394/B conn

Intel CPU debug conn
EC debug conn
SW debug conn

Switch Button list:
Power Botton(Sub/B)
Lid Switch

LED Function list:
AC Power LED
Charge LED
HDD LED

Title

Size Document Number Rev
Custom

Date: Sheet

page 31

Compal Electronics, Inc.

Block Diagram

LA-2591

E

Page 32
Page 32
Page 32
Page 17
Page 32
Page 4
Page 33
Page 33

Page 34
Page 34

Page 32
Page 32
Page 32

243Monday, October 11, 2004

of

0.1

5

I2C / SMBUS ADDRESSING

External PCI Devices

4

3

2

1

D D

LAN
CARD BUS
Cardreader
1394
Wireless LAN(MINI PCI)

Power Managment table

Signal

C C

State

S0

S1

S3

S5 S4/AC

S5 S4/AC don't exist

AD17
AD20

0
1

AD16 2
AD18

+12VALW +3V
+3VALW
+5VALW

ON

3

+2.5V

ON ON

ON ON ON

ON ON

ON OFF

OFF OFF OFF

F
A
B
E
G,H

+CPU_CORE
+VCCP(1.05V)
+5VS
+3VS
+2.5VS
+1.5VS
+1.25VS
+1.1VS(VGA/B)
+1.2VS(VGA/B)
+1.8VS(VGA/B)

OFF

OFF

IDSEL # PIRQREQ/GNT #DEVICE

B B

SMBUS Control Table

SOURCE

SMB_EC_CK1
SMB_EC_DA1

SMB_EC_CK2
SMB_EC_DA2

ICH_SMBCLK
ICH_SMBDATA
LCD_DDCCLK

LCD_DDCDATA
I2CC_SCL

I2CC_SDA

A A

KB910L

KB910L

ICH6-M

Alviso
GM-GP

NV44M

INVERTER BATT

5

SERIAL SENSOR
EEPROM

THERMAL
(CPU)

ADM1032

SODIMM CLK CHIP

4

MINI PCI

LCD

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

Title

Size Document Number Rev
Custom

Date: Sheet

Compal Electronics, Inc.

Design Note

LA-2591

1

of

343Monday, October 11, 2004

0.1

ZZZ1

5

4

3

2

1

LA-2591 REV 0.1

D D

C C

+VCCP

B B

H_DPRSLP will change to
H_DPRSTP in future
collateral version.

1 2

56_0402_5%

H_A#[3..31]<7>

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30

H_REQ#[0..4]<7>

H_ADSTB#0<7>
H_ADSTB#1<7>

CLK_ITP<18>
CLK_ITP#<18>

CLK_CPU_BCLK<18>
CLK_CPU_BCLK#<18>

H_ADS#<7>
H_BNR#<7>
H_BPRI#<7>
H_BR0#<7>
H_DEFER#<7>
H_DRDY#<7>

R37

H_RS#[0..2]<7>

H_HIT#<7>
H_HITM#<7>

H_LOCK#<7>
H_RESET#<7>

H_TRDY#<7>

H_DBSY#<7>
H_DPSLP#<20>

H_DPRSLP#<20>

H_DPWR#<7>

H_PWRGOOD<20>

H_CPUSLP#<7,20>

H_THERMDA<15>
H_THERMDC<15>

H_THERMTRIP#<7,20>

H_A#31
H_REQ#0

H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

H_ADSTB#0
H_ADSTB#1

CLK_ITP
CLK_ITP#

CLK_CPU_BCLK
CLK_CPU_BCLK#

H_ADS#
H_BNR#
H_BPRI#
H_BR0#
H_DEFER#
H_DRDY#
H_HIT#
H_HITM#
H_IERR#
H_LOCK#
H_RESET#

1" ~ 6.5"

H_RS#0
H_RS#1
H_RS#2
H_TRDY#

ITP_BPM#0
ITP_BPM#1
ITP_BPM#2
ITP_BPM#3

ITP_DBRESET#

H_DBSY#
H_DPSLP#
H_DPRSLP#

ITP_BPM#4
ITP_BPM#5

H_PROCHOT#

H_CPUSLP#
ITP_TCK
ITP_TDI
ITP_TDO
TEST1
TEST2
ITP_TMS
ITP_TRST#

H_THERMDA
H_THERMDC

U15A

P4

A3#

U4

A4#

V3

A5#

R3

A6#

V2

A7#

W1

A8#

T4

A9#

W2

A10#

Y4

A11#

Y1

A12#

U1

A13#

AA3

A14#

Y3

A15#

AA2

A16#

AF4

A17#

AC4

A18#

AC7

A19#

AC3

A20#

AD3

A21#

AE4

A22#

AD2

A23#

AB4

A24#

AC6

ADDR GROUP

A25#

AD5

A26#

AE2

A27#

AD6

A28#

AF3

A29#

AE1

A30#

AF1

A31#

R2

REQ0#

P3

REQ1#

T2

REQ2#

P1

REQ3#

T1

REQ4#

U3

ADSTB0#

AE5

ADSTB1#

A16

ITP_CLK0

A15

ITP_CLK1

B15

BCLK0

B14

BCLK1

N2

ADS#

L1

BNR#

J3

BPRI#

N4

BR0#

L4

DEFER#

H2

DRDY#

K3

HIT#

K4

HITM#

A4

IERR#

J2

LOCK#

B11

RESET#

H1

RS0#

K1

RS1#

L2

RS2#

M3

TRDY#

C8

BPM0#

B8

BPM1#

A9

BPM2#

C9

BPM3#

A7

DBR#

M2

DBSY#

B7

DPSLP#

G1

DPRSTP#

C19

DPWR#

A10

PRDY#

B10

PREQ#

B17

PROCHOT#

E4

PWRGOOD

A6

SLP#

A13

TCK

C12

TDI

A12

TDO

C5

TEST1

F23

TEST2

C11

TMS

B13

TRST#

B18

THERMDA

A18

THERMDC

C17

THERMTRIP#

TYCO_1612365-1_Dothan

Dothan

DATA GROUP

HOST CLK

CONTROL GROUP

MISC

THERMAL
DIODE

LEGACY CPU

D10#
D11#
D12#
D13#
D14#
D15#
D16#
D17#
D18#
D19#
D20#
D21#
D22#
D23#
D24#
D25#
D26#
D27#
D28#
D29#
D30#
D31#
D32#
D33#
D34#
D35#
D36#
D37#
D38#
D39#
D40#
D41#
D42#
D43#
D44#
D45#
D46#
D47#
D48#
D49#
D50#
D51#
D52#
D53#
D54#
D55#
D56#
D57#
D58#
D59#
D60#
D61#
D62#
D63#

DINV0#
DINV1#
DINV2#
DINV3#

DSTBN0#
DSTBN1#
DSTBN2#
DSTBN3#
DSTBP0#
DSTBP1#
DSTBP2#
DSTBP3#

A20M#
FERR#

IGNNE#

INIT#
LINT0
LINT1

STPCLK#

SMI#

D0#
D1#
D2#
D3#
D4#
D5#
D6#
D7#
D8#
D9#

A25
A22
B21
A24
B26
A21
B20
C20
B24
D24
E24
C26
B23
E23
C25
H23
G25
L23
M26
H24
F25
G24
J23
M23
J25
L26
N24
M25
H26
N25
K25
Y26
AA24
T25
U23
V23
R24
R26
R23
AA23
U26
V24
U25
V26
Y23
AA26
Y25
AB25
AC23
AB24
AC20
AC22
AC25
AD23
AE22
AF23
AD24
AF20
AE21
AD21
AF25
AF22
AF26

D25
J26
T24
AD20

C23
K24
W25
AE24
C22
L24
W24
AE25

C2
D3
A3
B5
D1
D4

C6
B4

H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63

H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3
H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3

H_A20M#
H_FERR#
H_IGNNE#
H_INIT#
H_INTR
H_NMI

H_STPCLK#
H_SMI#

H_DINV#0 <7>
H_DINV#1 <7>
H_DINV#2 <7>
H_DINV#3 <7>

H_A20M# <20>
H_FERR# <20>
H_IGNNE# <20>
H_INIT# <20>
H_INTR <20>
H_NMI <20>

H_STPCLK# <20>
H_SMI# <20>

H_D#0

A19

H_D#[0..63] <7>

ITP_DBRESET#<21>

ITP_BPM#[0:3] < 6" Spacing 1:2

Spacing 8 mil

Place near JITP 0.5"

H_DSTBN#[0..3] <7>

H_DSTBP#[0..3] <7>

+VCCP

Check ITP signal for Dothan

Place near JITP 0.5"

ITP_DBRESET#

R46

22.6_0402_1%@

H_RESET# RESETITP#

1 2

R47

22.6_0402_1%@

ITP_TDO ITP_TDO_R

1 2

R32
200_0402_5%

H_PWRGOOD

1 2

R38

200_0402_5%@

ITP_BPM#0
ITP_BPM#1
ITP_BPM#2
ITP_BPM#3
ITP_BPM#4
ITP_BPM#5

CLK_ITP
CLK_ITP#

ITP_TCK
ITP_TRST#
ITP_TMS
ITP_TDI

Add pullups for PWRGOOD and THERMTRIP per INTEL

12

R253
56_0402_5%

+VCCP

T1PAD
T6PAD
T5PAD
T8PAD
T2PAD
T9PAD
T3PAD

T15PAD

T18PAD
T19PAD
T16PAD

T17PAD
T14PAD
T4PAD
T13PAD

12

H_PROCHOT#

12

R266
56_0402_5%

2

B

+3VS

12

R258
1K_0402_5%

1

C

Q29
2SC2411K_SC59

E

3

+VCCP

1 2

R49 54.9_0402_1%

1 2

R48 54.9_0402_1%

1 2

R33 56_0402_5%

+VCCP

R42 39.2_0603_1%

1 2

R179150_0402_5%

1 2

R177680_0402_5%

1 2

R50 27.4_0402_1%

1 2

PROCHOT# <33>

Place near JITP 1"

ITP_TDO

Place near JITP 0.5"

H_RESET#
ITP_BPM#5

39.2

ITP_TMS

Within 2" of the CPU

ITP_TDI

Within 2" of the CPU

ITP_TRST#

Within 2" of the CPU

ITP_TCK

Within 2" of the CPU

A A

5

TEST2

TEST1

R251

1 2

1K_0402_5%@

R35

1 2

1K_0402_5%@

Title

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

4

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

Size Document Number Rev
Custom

Date: Sheet

Compal Electronics, Inc.

Dothan Processor(1/ 2)

LA-2591

1

0.1

of

443Monday, October 11, 2004

5

4

3

2

1

R181

+1.5VS

D D

1

1

C340

0.01U_0603_16V7K

C C

+VCCP

12

+V_CPU_GTLREF

B B

12

R248
1K_0402_1%

R247
2K_0402_1%

Layout close CPU

Layout Note:
500 mil max length

Spacing 25mil

20 mils

12

R249

27.4_0402_1%

5 mils (55 Ohm)

12

R250

54.9_0402_1%

20 mils(27.4Ohm)

12

R41

27.4_0402_1%

5 mils(55 Ohm)

12

R40

54.9_0402_1%

2

2

PSI#<42>

Spacing 1:2

Resistor placed within

0.5" of CPU pin.Trace
should be at least 25
miles away from any
other toggling signal.

54.9_0402_1%@

54.9_0402_1%@

C341
10U_1206_6.3V6M

+CPU_CORE

+V_CPU_GTLREF

CPU_BSEL0<18>
CPU_BSEL1<18>

1 2
1 2

R178

+VCCP

VID0<42>
VID1<42>
VID2<42>
VID3<42>
VID4<42>
VID5<42>

Spacing 25mil

CPU_BSEL0
CPU_BSEL1

T10 PAD
T7 PAD
T20 PAD
T12 PAD
T11 PAD

VCCSENSE
VSSSENSE

PSI#
VID0

VID1
VID2
VID3
VID4
VID5

COMP0
COMP1
COMP2
COMP3

U15B

AE7

VCCSENSE

AF6

VSSSENSE

F26

VCCA0

B1

VCCA1

N1

VCCA2

AC26

VCCA3

P23

VCCQ0

W4

VCCQ1

D10

VCCP

D12

VCCP

D14

VCCP

D16

VCCP

E11

VCCP

E13

VCCP

E15

VCCP

F10

VCCP

F12

VCCP

F14

VCCP

F16

VCCP

K6

VCCP

L5

VCCP

L21

VCCP

M6

VCCP

M22

VCCP

N5

VCCP

N21

VCCP

P6

VCCP

P22

VCCP

R5

VCCP

R21

VCCP

T6

VCCP

T22

VCCP

U21

VCCP

D6

VCC

D8

VCC

D18

VCC

D20

VCC

D22

VCC

E5

VCC

E7

VCC

E9

VCC

E17

VCC

E19

VCC

E21

VCC

F6

VCC

F8

VCC

F18

VCC

E1

PSI#

E2

VID0

F2

VID1

F3

VID2

G3

VID3

G4

VID4

H4

VID5

AD26

GTLREF

C16

BSEL0

C14

BSEL1

P25

COMP0

P26

COMP1

AB2

COMP2

AB1

COMP3

B2

RSVD

C3

RSVD

E26

RSVD

AF7

RSVD

AC1

RSVD

TYCO_1612365-1_Dothan

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

Dothan

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

POWER, GROUNG, RESERVED SIGNALS AND NC

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

A2
A5
A8
A11
A14
A17
A20
A23
A26
B3
B6
B9
B12
B16
B19
B22
B25
C1
C4
C7
C10
C13
C15
C18
C21
C24
D2
D5
D7
D9
D11
D13
D15
D17
D19
D21
D23
D26
E3
E6
E8
E10
E12
E14
E16
E18
E20
E22
E25
F1
F4
F5
F7
F9
F11
F13
F15
F17
F19
F21
F24
G2
G6
G22
G23
G26
H3
H5
H21
H25
J1
J4
J6
J22
J24
K2
K5
K21
K23
K26
L3
L6
L22
L25
M1

+CPU_CORE

U15C

F20

VCC

F22

VCC

G5

VCC

G21

VCC

H6

VCC

H22

VCC

J5

VCC

J21

VCC

K22

VCC

U5

VCC

V6

VCC

V22

VCC

W5

VCC

W21

VCC

Y6

VCC

Y22

VCC

AA5

VCC

AA7

VCC

AA9

VCC

AA11

VCC

AA13

VCC

AA15

VCC

AA17

VCC

AA19

VCC

AA21

VCC

AB6

VCC

AB8

VCC

AB10

VCC

AB12

VCC

AB14

VCC

AB16

VCC

AB18

VCC

AB20

VCC

AB22

VCC

AC9

VCC

AC11

VCC

AC13

VCC

AC15

VCC

AC17

VCC

AC19

VCC

AD8

VCC

AD10

VCC

AD12

VCC

AD14

VCC

AD16

VCC

AD18

VCC

AE9

VCC

AE11

VCC

AE13

VCC

AE15

VCC

AE17

VCC

AE19

VCC

AF8

VCC

AF10

VCC

AF12

VCC

AF14

VCC

AF16

VCC

AF18

VCC

M4

VSS

M5

VSS

M21

VSS

M24

VSS

N3

VSS

N6

VSS

N22

VSS

N23

VSS

N26

VSS

P2

VSS

P5

VSS

P21

VSS

P24

VSS

R1

VSS

R4

VSS

R6

VSS

R22

VSS

R25

VSS

T3

VSS

T5

VSS

T21

VSS

T23

VSS

TYCO_1612365-1_Dothan

Dothan

POWER, GROUND

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

T26
U2
U6
U22
U24
V1
V4
V5
V21
V25
W3
W6
W22
W23
W26
Y2
Y5
Y21
Y24
AA1
AA4
AA6
AA8
AA10
AA12
AA14
AA16
AA18
AA20
AA22
AA25
AB3
AB5
AB7
AB9
AB11
AB13
AB15
AB17
AB19
AB21
AB23
AB26
AC2
AC5
AC8
AC10
AC12
AC14
AC16
AC18
AC21
AC24
AD1
AD4
AD7
AD9
AD11
AD13
AD15
AD17
AD19
AD22
AD25
AE3
AE6
AE8
AE10
AE12
AE14
AE16
AE18
AE20
AE23
AE26
AF2
AF5
AF9
AF11
AF13
AF15
AF17
AF19
AF21
AF24

A A

Title

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

Size Document Number Rev
Custom

Date: Sheet

Compal Electronics, Inc.

Dothan Processor(2/ 2)

LA-2591

1

0.1

of

543Monday, October 11, 2004

5

4

3

2

1

+CPU_CORE

1

C84
10U_1206_6.3V6M

2

+CPU_CORE

1

2

+CPU_CORE

1

2

+CPU_CORE

1

2

C259
10U_1206_6.3V6M

C274
10U_1206_6.3V6M

C303
10U_1206_6.3V6M

D D

C C

1

C87
10U_1206_6.3V6M

2

1

C265
10U_1206_6.3V6M

2

1

C280
10U_1206_6.3V6M

2

1

C302
10U_1206_6.3V6M

2

1

C90
10U_1206_6.3V6M

2

1

C81
10U_1206_6.3V6M

2

1

C293
10U_1206_6.3V6M

2

1

C282
10U_1206_6.3V6M

2

1

C93
10U_1206_6.3V6M

2

1

C82
10U_1206_6.3V6M

2

1

C301
10U_1206_6.3V6M

2

1

C283
10U_1206_6.3V6M

2

1

C97
10U_1206_6.3V6M

2

1

C100
10U_1206_6.3V6M

2

1

C273
10U_1206_6.3V6M

2

1

C272
10U_1206_6.3V6M

2

+CPU_CORE

1

2

+CPU_CORE

1

2

+CPU_CORE

1

2

C99
10U_1206_6.3V6M

C101
10U_1206_6.3V6M

C279
10U_1206_6.3V6M

1

C83
10U_1206_6.3V6M

2

1

C102
10U_1206_6.3V6M

2

1

C292
10U_1206_6.3V6M

2

1

C86
10U_1206_6.3V6M

2

1

C98
10U_1206_6.3V6M

2

1

C300
10U_1206_6.3V6M

2

1

C89
10U_1206_6.3V6M

2

1

C260
10U_1206_6.3V6M

2

1

C257
10U_1206_6.3V6M

2

1

C92
10U_1206_6.3V6M

2

1

C267
10U_1206_6.3V6M

2

1

C256
10U_1206_6.3V6M

2

Near VCORE regulator.

+CPU_CORE

1

+

C94

B B

+VCCP

1

C70

+

150U_D_6.3VM

2

A A

1

C85

0.1U_0402_16V4Z

2

5

1

C88

0.1U_0402_16V4Z

2

1

C91

0.1U_0402_16V4Z

2

1

2

4

C96

0.1U_0402_16V4Z

1

C103

0.1U_0402_16V4Z

2

1

C104

0.1U_0402_16V4Z

2

330U_D2E_2.5VM

1

2

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2

330U_D2E_2.5VM

C78

0.1U_0402_16V4Z

3

C286

1

+

330U_D2E_2.5VM

2

1

2

1

+

C95

2

C80

0.1U_0402_16V4Z

C285

1

+

2

330U_D2E_2.5VM@

1

2

ESR <= 3m ohm
Capacitor > 880 uF

C105

0.1U_0402_16V4Z

1

C79

0.1U_0402_16V4Z

2

2

Title

Size Document Number Rev
Custom

Date: Sheet

Compal Electronics, Inc.

Dothan Bypass

LA-2591

1

of

643Monday, October 11, 2004

0.1

5

4

3

2

1

H_A#[3..31]<4>

D D

T29 PAD

H_REQ#[0..4]<4>

H_ADSTB#0<4>
H_ADSTB#1<4>

C C

B B

A A

CLK_MCH_BCLK#<18>
CLK_MCH_BCLK<18>

H_DSTBN#[0..3]<4>

H_DSTBP#[0..3]<4>

H_DINV#0<4>
H_DINV#1<4>
H_DINV#2<4>
H_DINV#3<4>

H_RESET#<4>
H_ADS#<4>

H_TRDY#<4>
H_DPWR#<4>
H_DRDY#<4>
H_DEFER#<4>

T30 PAD

H_HITM#<4>
H_HIT#<4>
H_LOCK#<4>

H_BR0#<4>
H_BNR#<4>
H_BPRI#<4>
H_DBSY#<4>

H_CPUSLP#<4,20>

H_RS#[0..2]<4>

5

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31

TP_H_PCREQ#

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
H_ADSTB#0
H_ADSTB#1

H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3
H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3

H_RESET#
H_ADS#

H_TRDY#
H_DRDY#

H_DEFER#
TP_H_EDRDY#
H_HITM#
H_HIT#
H_LOCK#
H_BR0#
H_BNR#
H_BPRI#
H_DBSY#

H_CPUSLP#

H_RS#0
H_RS#1
H_RS#2

U5A

G9

HA3#

C9

HA4#

E9

HA5#

B7

HA6#

A10

HA7#

F9

HA8#

D8

HA9#

B10

HA10#

E10

HA11#

G10

HA12#

D9

HA13#

E11

HA14#

F10

HA15#

G11

HA16#

G13

HA17#

C10

HA18#

C11

HA19#

D11

HA20#

C12

HA21#

B13

HA22#

A12

HA23#

F12

HA24#

G12

HA25#

E12

HA26#

C13

HA27#

B11

HA28#

D13

HA29#

A13

HA30#

F13

HA31#

A11

HPCREQ#

A7

HREQ#0

D7

HREQ#1

B8

HREQ#2

C7

HREQ#3

A8

HREQ#4

B9

HADSTB#0

E13

HADSTB#1

AB1

HCLKN

AB2

HCLKP

G4

HDSTBN#0

K1

HDSTBN#1

R3

HDSTBN#2

V3

HDSTBN#3

G5

HDSTBP#0

K2

HDSTBP#1

R2

HDSTBP#2

W4

HDSTBP#3

H8

HDINV#0

K3

HDINV#1

T7

HDINV#2

U5

HDINV#3

H10

HCPURST#

F8

HADS#

B5

HTRDY#

G6

HDPWR#

F7

HDRDY#

E6

HDEFER#

F6

HEDRDY#

D6

HHITM#

D4

HHIT#

B3

HLOCK#

E7

HBREQ0#

A5

HBNR#

D5

HBPRI#

C6

HDBSY#

G8

HCPUSLP#

A4

HRS0#

C5

HRS1#

B4

HRS2#

ALVISO_BGA1257

Alviso

HOST

H_SWNG0

C253

HXRCOMP
HXSCOMP
HYRCOMP
HYSCOMP

HXSWING
HYSWING

0.1U_0402_16V4Z

HD10#
HD11#
HD12#
HD13#
HD14#
HD15#
HD16#
HD17#
HD18#
HD19#
HD20#
HD21#
HD22#
HD23#
HD24#
HD25#
HD26#
HD27#
HD28#
HD29#
HD30#
HD31#
HD32#
HD33#
HD34#
HD35#
HD36#
HD37#
HD38#
HD39#
HD40#
HD41#
HD42#
HD43#
HD44#
HD45#
HD46#
HD47#
HD48#
HD49#
HD50#
HD51#
HD52#
HD53#
HD54#
HD55#
HD56#
HD57#
HD58#
HD59#
HD60#
HD61#
HD62#
HD63#

HVREF

1

2

HD0#
HD1#
HD2#
HD3#
HD4#
HD5#
HD6#
HD7#
HD8#
HD9#

E4
E1
F4
H7
E2
F1
E3
D3
K7
F2
J7
J8
H6
F3
K8
H5
H1
H2
K5
K6
J4
G3
H3
J1
L5
K4
J5
P7
L7
J3
P5
L3
U7
V6
R6
R5
P3
T8
R7
R8
U8
R4
T4
T5
R1
T3
V8
U6
W6
U3
V5
W8
W7
U2
U1
Y5
Y2
V4
Y7
W1
W3
Y3
Y6
W2

J11
C1
C2
T1
L1
D1
P1

12

R173

221_0603_1%

12

R169

100_0402_1%

4

H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63

H_VREF
H_XRCOMP
H_XSCOMP
H_YRCOMP
H_YSCOMP
H_SWNG0
H_SWNG1

H_SWNG1

C247

0.1U_0402_16V4Z

1

2

100mil

12

R165

R170

24.9_0402_1%

10/20 mils

+VCCP+VCCP

12

R168

221_0603_1%

12

R167

100_0402_1%

H_D#[0..63] <4>

+VCCP

12

R163

R164

54.9_0402_1%

12

24.9_0402_1%

12

54.9_0402_1%

1

C237

2

0.1U_0402_16V4Z

Layout Note:
Rote as short
as possible

12

R136

40.2_0402_1%

+VCCP

12

R156

100_0402_1%

12

R160

200_0402_1%

R147

40.2_0402_1%

12

DMI_TXN0<21>
DMI_TXN1<21>
DMI_TXN2<21>
DMI_TXN3<21>

DMI_TXP0<21>
DMI_TXP1<21>
DMI_TXP2<21>
DMI_TXP3<21>

DMI_RXN0<21>
DMI_RXN1<21>
DMI_RXN2<21>
DMI_RXN3<21>

DMI_RXP0<21>
DMI_RXP1<21>
DMI_RXP2<21>
DMI_RXP3<21>

DDR_CLK0<12>
DDR_CLK1<12>

DDR_CLK3<13>
DDR_CLK4<13>

DDR_CLK0#<12>
DDR_CLK1#<12>

DDR_CLK3#<13>
DDR_CLK4#<13>

DDR_CKE0<12>
DDR_CKE2<13>

DDR_CKE3<13>

DDR_SCS#0<12>
DDR_SCS#2<13>

DDR_SCS#3<13>

+2.5V

12

R174

SDREF

R172

12

+2.5V

12

R159 80.6_0402_1%

1 2

R157

80.6_0402_1%

10K_0402_1%

SDREF<12,13>

10K_0402_1%

CFG[2:0]

CFG5

CFG6

CFG7

CFG9

CFG[13:12]

M_OCDOCMP0
M_OCDOCMP1

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

CFG16
(FSB Dynamic
ODT)

CFG18
(VCC Select)

CFG19
(VTT Select)

DMI_TXN0
DMI_TXN1
DMI_TXN2
DMI_TXN3

DMI_TXP0
DMI_TXP1
DMI_TXP2
DMI_TXP3

DMI_RXN0
DMI_RXN1
DMI_RXN2
DMI_RXN3

DMI_RXP0
DMI_RXP1
DMI_RXP2
DMI_RXP3

DDR_CLK0
DDR_CLK1

DDR_CLK3
DDR_CLK4

DDR_CLK0#
DDR_CLK1#

DDR_CLK3#
DDR_CLK4#

DDR_CKE0
DDR_CKE2

DDR_CKE3
DDR_SCS#0
DDR_SCS#2

DDR_SCS#3

M_OCDOCMP0
M_OCDOCMP1

SMRCOMPN
SMRCOMPP

SDREF

1

C22

2

0.1U_0402_16V4Z

Refer to sheet 19 for FSB
frequency select

Low = DMI x 2
High = DMI x 4
Low = DDR-II
High = DDR-I
Low = DT/Transportable CPU
High = Mobile CPU
Low = Reverse Lane
High = Normal Operation

00 = Reserved
01 = XOR Mode Enabled
10 = All Z Mode Enabled
11 = Normal Operation (Default)

Low = Disabled
High = Enabled
Low = 1.05V (Default)
High = 1.5V
Low = 1.05V (Default)
High = 1.2V

AA31

DMIRXN0

AB35

DMIRXN1

AC31

DMIRXN2

AD35

DMIRXN3

Y31

DMIRXP0

AA35

DMIRXP1

AB31

DMIRXP2

AC35

DMIRXP3

AA33

DMITXN0

AB37

DMITXN1

AC33

DMITXN2

AD37

DMITXN3
DMITXP0

DMITXP1
DMITXP2
DMITXP3

SM_CK0
SM_CK1
SM_CK2
SM_CK3
SM_CK4
SM_CK5

SM_CK0#
SM_CK1#
SM_CK2#
SM_CK3#
SM_CK4#
SM_CK5#

SM_CKE0
SM_CKE1
SM_CKE2
SM_CKE3

SM_CS0#
SM_CS1#
SM_CS2#
SM_CS3#

SM_OCDCOMP0
SM_OCDCOMP1
SM_ODT0
SM_ODT1
SM_ODT2
SM_ODT3

SMRCOMPN
SMRCOMPP
SMVREF0
SMVREF1
SMXSLEWIN
SMXSLEWOUT
SMYSLEWIN
SMYSLEWOUT

ALVISO_BGA1257

DMIDDR MUXING

Y33
AA37
AB33
AC37

AM33

AL1
AE11

AJ34

AF6
AC10

AN33

AK1
AE10

AJ33

AF5
AD10

AP21
AM21
AH21
AK21

AN16
AM14
AH15
AG16

AF22
AF16
AP14

AL15
AM11
AN10

AK10
AK11
AF37

AD1
AE27
AE28

AF9

1

AF10

C252

2

0.1U_0402_16V4Z

*

*

*

*

*

*

*

*

2

CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8

CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG16
CFG17
CFG18
CFG19
CFG20

RSVD21
RSVD22

CFG/RSVD

RSVD23
RSVD24
RSVD25
RSVD26
RSVD27

BM_BUSY#

EXT_TS0#
EXT_TS1#

THRMTRIP#

PWROK

RSTIN#

PM

DREF_CLKN
DREF_CLKP

DREF_SSCLKP

CLK

DREF_SSCLKN

NC1
NC2
NC3
NC4
NC5
NC6
NC7
NC8
NC9

NC10

NC

NC11

U5B

G16
H13
G14
F16
F15
G15
E16
D17
J16
D15
E15
D14
E14
H12
C14
H15
J15
H14
G22
G23
D23
G25
G24
J17
A31
A30
D26
D25

J23
J21
H22
F5
AD30
AE29

A24
A23
D37
C37

AP37
AN37
AP36
AP2
AP1
AN1
B1
A2
B37
A36
A37

CFG0
MCH_CLKSEL1
MCH_CLKSEL0

T27PAD
T28PAD

CFG5

CFG6

CFG7

CFG9

CFG12

CFG13

CFG16

CFG18

CFG19

PM_EXTTS#0
PM_EXTTS#1

CFG0

R149 10K_0402_5%

CFG[17:3] hav e i n t e r n a l p u l l-up

CFG6

R151 2.2K_0402_5%@

CFG5

R154 2.2K_0402_5%@

CFG7

R146 2.2K_0402_5%@

CFG9

R153 2.2K_0402_5%@

CFG12

R152 2.2K_0402_5%@

CFG13

R158 2.2K_0402_5%@

CFG16

R148 2.2K_0402_5%@

CFG18

R138 2.2K_0402_5%@

CFG19

R134 2.2K_0402_5%@

MCH_CLKSEL1 <18>
MCH_CLKSEL0 <18>

PM_BMBUSY# <21>

H_THERMTRIP# <4,20>
+VCCP_PWRGD <33>
PLTRST_MCH# <19,21,25,27>

DREFCLK# <18>
DREFCLK <18>
SSC_DREFCLK <18>
SSC_DREFCLK# <18>

R141

1 2
1 2
1 2
1 2

1 2
1 2
1 2

1 2
1 2

10K_0402_5%

10K_0402_5%

12

R137

PM_EXTTS#0

PM_EXTTS#1

2.2K/3.5K reserve for choose

2.2K/3.5K reserve for choose

CFG[19:18] have internal pull-down

Title

Size Document Number Rev
Custom

Date: Sheet

Compal Electronics, Inc.

Alviso(1 of 5)

LA-2591

1

743Monday, October 11, 2004

+2.5VS

12

12

+VCCP

+2.5VS

0.1

of

5

D D

4

3

2

1

DDR_A_BS#0<12>
DDR_A_BS#1<12>

T23 PAD~D T24 PAD~D

DDR_A_DM[0..7]<12>

DDR_A_DQS[0..7]<12>

C C

DDR_A_MA[0..13]<12>

DDR_A_CAS#<12>
DDR_A_RAS#<12>

T21 PAD~D T25 PAD~D
T22 PAD~D T26 PAD~D

B B

DDR_A_WE#<12>

DDR_A_BS#0
DDR_A_BS#1
DDR_A_BS#2

DDR_A_DM0
DDR_A_DM1
DDR_A_DM2
DDR_A_DM3
DDR_A_DM4
DDR_A_DM5
DDR_A_DM6
DDR_A_DM7

DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7

DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13

DDR_A_CAS#
DDR_A_RAS#

TP_MA_RCVENIN#

TP_MA_RCVENOUT#

DDR_A_WE#

AK15
AK16

AL21
AJ37

AP35

AL29

AP24

AK36
AP33
AN29
AP23

AK35
AP34
AN30
AN23

AL17
AP17
AP18

AM17

AN18

AM18

AL19
AP20

AM19

AL20

AM16

AN20

AM20
AM15

AN15
AP16
AF29
AF28
AP15

AP9
AP4

AD3

AM8
AM4

AE5

AN8
AM5
AH1
AE4

AJ2

AJ1

U5C

SA_BS0#
SA_BS1#
SA_BS2#

SA_DM0
SA_DM1
SA_DM2
SA_DM3
SA_DM4
SA_DM5
SA_DM6
SA_DM7

SA_DQS0
SA_DQS1
SA_DQS2
SA_DQS3
SA_DQS4
SA_DQS5
SA_DQS6
SA_DQS7

SA_DQS0#
SA_DQS1#
SA_DQS2#
SA_DQS3#
SA_DQS4#
SA_DQS5#
SA_DQS6#
SA_DQS7#

SA_MA0
SA_MA1
SA_MA2
SA_MA3
SA_MA4
SA_MA5
SA_MA6
SA_MA7
SA_MA8
SA_MA9
SA_MA10
SA_MA11
SA_MA12
SA_MA13

SA_CAS#
SA_RAS#
SA_RCVENIN#
SA_RCVENOUT#
SA_WE#

SADQ0
SADQ1
SADQ2
SADQ3
SADQ4
SADQ5
SADQ6
SADQ7
SADQ8

SADQ9
SADQ10
SADQ11
SADQ12
SADQ13
SADQ14
SADQ15
SADQ16
SADQ17
SADQ18
SADQ19
SADQ20
SADQ21
SADQ22
SADQ23
SADQ24
SADQ25
SADQ26
SADQ27
SADQ28
SADQ29
SADQ30
SADQ31
SADQ32
SADQ33
SADQ34
SADQ35
SADQ36
SADQ37
SADQ38
SADQ39
SADQ40
SADQ41
SADQ42
SADQ43

DDR MEMORY SYSTEM A

SADQ44
SADQ45
SADQ46
SADQ47
SADQ48
SADQ49
SADQ50
SADQ51
SADQ52
SADQ53
SADQ54
SADQ55
SADQ56
SADQ57
SADQ58
SADQ59
SADQ60
SADQ61
SADQ62
SADQ63

ALVISO_BGA1257

AH35
AL35
AL37
AH36
AJ35
AK37
AL34
AM36
AN35
AP32
AM31
AM34
AM35
AL32
AM32
AN31
AP31
AN28
AP28
AL30
AM30
AM28
AL28
AP27
AM27
AM23
AM22
AL23
AM24
AN22
AP22
AM9
AL9
AL6
AP7
AP11
AP10
AL7
AM7
AN5
AN6
AN3
AP3
AP6
AM6
AL4
AM3
AK2
AK3
AG2
AG1
AL3
AM2
AH3
AG3
AF3
AE3
AD6
AC4
AF2
AF1
AD4
AD5

DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63

DDR_A_D0

AG35

DDR_A_D[0..63] <12>

This Symbol as same
as Intel CRB
schematic, So Layout
Guide will show these
signals routed
differentially.

DDR_B_BS#0<13>
DDR_B_BS#1<13>

DDR_B_MA[0..13]<13>

DDR_B_CAS#<13>
DDR_B_RAS#<13>

DDR_B_WE#<13>

DDR_B_BS#0
DDR_B_BS#1
DDR_B_BS#2

DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13

DDR_B_CAS#
DDR_B_RAS#

TP_MB_RCVENIN#

TP_MB_RCVENOUT#

DDR_B_WE#

AJ15
AG17
AG21

AF32
AK34
AK27
AK24

AJ10

AK5
AE7
AB7

AF34
AK32

AJ28
AK23
AM10

AH6
AF8
AB4

AF35
AK33
AK28

AJ23

AL10

AH7
AF7
AB5

AH17
AK17
AH18

AJ18
AK18

AJ19
AK19
AH19

AJ20
AH20

AJ16
AG18
AG20
AG15

AH14
AK14
AF15
AF14
AH16

U5D

SB_BS0#
SB_BS1#
SB_BS2#

SB_DM0
SB_DM1
SB_DM2
SB_DM3
SB_DM4
SB_DM5
SB_DM6
SB_DM7

SB_DQS0
SB_DQS1
SB_DQS2
SB_DQS3
SB_DQS4
SB_DQS5
SB_DQS6
SB_DQS7

SB_DQS0#
SB_DQS1#
SB_DQS2#
SB_DQS3#
SB_DQS4#
SB_DQS5#
SB_DQS6#
SB_DQS7#

SB_MA0
SB_MA1
SB_MA2
SB_MA3
SB_MA4
SB_MA5
SB_MA6
SB_MA7
SB_MA8
SB_MA9
SB_MA10
SB_MA11
SB_MA12
SB_MA13

SB_CAS#
SB_RAS#
SB_RCVENIN#
SB_RCVENOUT#
SB_WE#

AE31

SBDQ0

AE32

SBDQ1

AG32

SBDQ2

AG36

SBDQ3

AE34

SBDQ4

AE33

SBDQ5

AF31

SBDQ6

AF30

SBDQ7

AH33

SBDQ8

AH32

SBDQ9

AK31

SBDQ10

AG30

SBDQ11

AG34

SBDQ12

AG33

SBDQ13

AH31

SBDQ14

AJ31

SBDQ15

AK30

SBDQ16

AJ30

SBDQ17

AH29

SBDQ18

AH28

SBDQ19

AK29

SBDQ20

AH30

SBDQ21

AH27

SBDQ22

AG28

SBDQ23

AF24

SBDQ24

AG23

SBDQ25

AJ22

SBDQ26

AK22

SBDQ27

AH24

SBDQ28

AH23

SBDQ29

AG22

SBDQ30

AJ21

SBDQ31

AG10

SBDQ32

AG9

SBDQ33

AG8

SBDQ34

AH8

SBDQ35

AH11

SBDQ36

AH10

SBDQ37

AJ9

SBDQ38

AK9

SBDQ39

AJ7

SBDQ40

AK6

SBDQ41

AJ4

SBDQ42
SBDQ43
SBDQ44
SBDQ45
SBDQ46
SBDQ47
SBDQ48
SBDQ49
SBDQ50
SBDQ51
SBDQ52
SBDQ53
SBDQ54
SBDQ55
SBDQ56
SBDQ57
SBDQ58
SBDQ59
SBDQ60
SBDQ61
SBDQ62
SBDQ63

AH5
AK8
AJ8
AJ5
AK4
AG5
AG4
AD8
AD9
AH4
AG6
AE8
AD7
AC5
AB8
AB6
AA8
AC8
AC7
AA4
AA5

DDR SYSTEM MEMORY B

ALVISO_BGA1257

A A

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

Title

Size Document Number Rev
Custom

2

Date: Sheet

Compal Electronics, Inc.

Alviso(2 of 5)

LA-2591

1

0.1

of

843Monday, October 11, 2004

5

D D

+2.5VS

R132

CLK_MCH_3GPLL#<18>
CLK_MCH_3GPLL<18>

Y/G<17>

COMP/B<17>

C/R<17>

C C

CRT_BLU<17>
CRT_GRN<17>
CRT_RED<17>

+2.5VS

R133 2.2K_0402_5%
R140 2.2K_0402_5%

LCD_CLK
LCD_DAT

R128 1.5K_0402_1%

1 2
1 2

B B

A A

R131

R142

4.99K_0603_1%

CLK_DDC2<17>
DAT_DDC2<17>

VSYNC<17>
HSYNC<17>

BIA<16>
BK_EN<16>

LCD_CLK<16>
LCD_DAT<16>
EN_LCDVDD<16>

12

LVDS_AC-<16>
LVDS_AC+<16>

LVDS_A0-<16>
LVDS_A1-<16>
LVDS_A2-<16>

LVDS_A0+<16>
LVDS_A1+<16>
LVDS_A2+<16>

4

Striping: SDVOCTRL_DATA
0=No SDVO Device Present (default)
1=SDVO Device Present
SDVOCTRL_DATA/SDVOCTRL_CLK have internal pull down resistor

3.6K_0402_5% @

1 2
1 2

3.6K_0402_5%@

12

CLK_DDC2
DAT_DDC2

1 2

R143

NONVGA@

255_0402_1%

BIA
BK_EN

LCD_CLK
LCD_DAT
EN_LCDVDD

LVDS_AC­LVDS_AC+

LVDS_A0­LVDS_A1­LVDS_A2-

LVDS_A0+
LVDS_A1+
LVDS_A2+

AB29
AC29

H24
H25

A15
C16
A17

J18
B15
B16
B17

E24
E23
E21
D21
C20
B20
A19
B19
H21
G21

J20

E25
F25
C23
C22
F23
F22
F26
C33
C31
F28
F27

B30
B29
C25
C24

B34
B33
B32

A34
A33
B31

C29
D28
C27

C28
D27
C26

SDVOCTRL_DATA
SDVOCTRL_CLK
GCLKN
GCLKP

TVDAC_A
TVDAC_B
TVDAC_C
TV_REFSET
TV_IRTNA
TV_IRTNB
TV_IRTNC

DDCCLK
DDCDATA
BLUE
BLUE#
GREEN
GREEN#
RED
RED#
VSYNC
HSYNC
REFSET

LBKLT_CTL
LBKLT_EN
LCTLA_CLK
LCTLB_DATA
LDDC_CLK
LDDC_DATA
LVDD_EN
LIBG
LVBG
LVREFH
LVREFL

LACLKN
LACLKP
LBCLKN
LBCLKP

LADATAN0
LADATAN1
LADATAN2

LADATAP0
LADATAP1
LADATAP2

LBDATAN0
LBDATAN1
LBDATAN2

LBDATAP0
LBDATAP1
LBDATAP2

EXP_RXN0/SDVO_TVCLKIN#

EXP_RXN1/SDVO_INT#

MISCTVVGALVDS

EXP_RXN2/SDVO_FLDSTALL#

EXP_RXP0/SDVO_TVCLKIN

EXP_RXP1/SDVO_INT

EXP_RXP2/SDVO_FLDSTALL

EXP_TXN0/SDVOB_RED#

EXP_TXN1/SDVOB_GREEN#

EXP_TXN2/SDVOB_BLUE#

EXP_TXN3/SDVOB_CLKN
EXP_TXN4/SDVOC_RED#

EXP_TXN5/SDVOC_GREEN#

EXP_TXN6/SDVOC_BLUE#

EXP_TXN7/SDVOC_CLKN

PCI - EXPRESS GRAPHICS

EXP_TXP0/SDVOB_RED

EXP_TXP1/SDVOB_GREEN

EXP_TXP2/SDVOB_BLUE
EXP_TXP3/SDVOB_CLKP

EXP_TXP4/SDVOC_RED

EXP_TXP5/SDVOC_GREEN

EXP_TXP6/SDVOC_BLUE
EXP_TXP7/SDVOC_CLKP

EXP_COMPI

EXP_ICOMPO

EXP_RXN3
EXP_RXN4
EXP_RXN5
EXP_RXN6
EXP_RXN7
EXP_RXN8

EXP_RXN9
EXP_RXN10
EXP_RXN11
EXP_RXN12
EXP_RXN13
EXP_RXN14
EXP_RXN15

EXP_RXP3

EXP_RXP4

EXP_RXP5

EXP_RXP6

EXP_RXP7

EXP_RXP8

EXP_RXP9
EXP_RXP10
EXP_RXP11
EXP_RXP12
EXP_RXP13
EXP_RXP14
EXP_RXP15

EXP_TXN8

EXP_TXN9
EXP_TXN10
EXP_TXN11
EXP_TXN12
EXP_TXN13
EXP_TXN14
EXP_TXN15

EXP_TXP8

EXP_TXP9

EXP_TXP10
EXP_TXP11
EXP_TXP12
EXP_TXP13
EXP_TXP14
EXP_TXP15

ALVISO_BGA1257

U5G

D36
D34

E30
F34
G30
H34
J30
K34
L30
M34
N30
P34
R30
T34
U30
V34
W30
Y34

D30
E34
F30
G34
H30
J34
K30
L34
M30
N34
P30
R34
T30
U34
V30
W34

E32
F36
G32
H36
J32
K36
L32
M36
N32
P36
R32
T36
U32
V36
W32
Y36

D32
E36
F32
G36
H32
J36
K32
L36
M32
N36
P32
R36
T32
U36
V32
W36

3

+1.5VS_PCIE

PEG_RXN[0..15] <16>

PEG_RXP[0..15] <16>

This Symbol as same
as Intel CRB
schematic, So Layout
Guide will show these
signals routed
differentially.

PEG_TXN[0..15] <16>

PEG_TXP[0..15] <16>

PEGCOMP

PEG_RXN0
PEG_RXN1
PEG_RXN2
PEG_RXN3
PEG_RXN4
PEG_RXN5
PEG_RXN6
PEG_RXN7
PEG_RXN8
PEG_RXN9
PEG_RXN10
PEG_RXN11
PEG_RXN12
PEG_RXN13
PEG_RXN14
PEG_RXN15

PEG_RXP0
PEG_RXP1
PEG_RXP2
PEG_RXP3
PEG_RXP4
PEG_RXP5
PEG_RXP6
PEG_RXP7
PEG_RXP8
PEG_RXP9
PEG_RXP10
PEG_RXP11
PEG_RXP12
PEG_RXP13
PEG_RXP14
PEG_RXP15

PEG_TXN0
PEG_TXN1
PEG_TXN2
PEG_TXN3
PEG_TXN4
PEG_TXN5
PEG_TXN6
PEG_TXN7
PEG_TXN8
PEG_TXN9
PEG_TXN10
PEG_TXN11
PEG_TXN12
PEG_TXN13
PEG_TXN14
PEG_TXN15

PEG_TXP0
PEG_TXP1
PEG_TXP2
PEG_TXP3
PEG_TXP4
PEG_TXP5
PEG_TXP6
PEG_TXP7
PEG_TXP8
PEG_TXP9
PEG_TXP10
PEG_TXP11
PEG_TXP12
PEG_TXP13
PEG_TXP14
PEG_TXP15

R125

24.9_0402_1%

1 2

PEG_RXN[0..15]

PEG_RXP[0..15]

PEG_TXN[0..15]

PEG_TXP[0..15]

2

1

Title

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

Size Document Number Rev
Custom

Date: Sheet

Compal Electronics, Inc.

Alviso(3 of 5)

LA-2591

1

0.1

of

943Monday, October 11, 2004

5

K13

VTT0

J13

VTT1

K12

VTT2

W11

VTT3

V11

VTT4

U11

VTT5

T11

VTT6

R11

VTT7

P11

POWER

VTT8

N11

VTT9

M11

D D

+VCCP

1

C217

C232

2

4.7U_0805_10V4Z

2.2U_0603_6.3V4Z

1

C65

C C

0.47U_0603_16V7K

2

1

1

C245

2

2

0.47U_0603_16V7K

CHB1608U301_0603

+1.5VS

B B

L11
K11

W10

V10
U10
T10
R10
P10
N10

M10

K10

J10

1

Y9

W9

U9

2

R9

P9
N9
M9

L9

J9
N8
M8
N7
M7
N6
M6

A6
N5
M5
N4
M4
N3
M3
N2
M2

B2

V1
N1
M1
G1

1

C254

C244

2

0.22U_0603_16V4Z

L6

1 2

0.22U_0603_16V4Z

VTT10
VTT11
VTT12
VTT13
VTT14
VTT15
VTT16
VTT17
VTT18
VTT19
VTT20
VTT21
VTT22
VTT23
VTT24
VTT25
VTT26
VTT27
VTT28
VTT29
VTT30
VTT31
VTT32
VTT33
VTT34
VTT35
VTT36
VTT37
VTT38
VTT39
VTT40
VTT41
VTT42
VTT43
VTT44
VTT45
VTT46
VTT47
VTT48
VTT49
VTT50
VTT51

+1.5VS_DPLLA

1

C205

+

2

0.1U_0402_16V4Z

330U_D2E_2.5VM

C209

1

2

U5F

VCCSM0
VCCSM1
VCCSM2
VCCSM3
VCCSM4
VCCSM5
VCCSM6
VCCSM7
VCCSM8

VCCSM9
VCCSM10
VCCSM11
VCCSM12
VCCSM13
VCCSM14
VCCSM15
VCCSM16
VCCSM17
VCCSM18
VCCSM19
VCCSM20
VCCSM21
VCCSM22
VCCSM23
VCCSM24
VCCSM25
VCCSM26
VCCSM27
VCCSM28
VCCSM29
VCCSM30
VCCSM31
VCCSM32
VCCSM33
VCCSM34
VCCSM35
VCCSM36
VCCSM37
VCCSM38
VCCSM39
VCCSM40
VCCSM41
VCCSM42
VCCSM43
VCCSM44
VCCSM45
VCCSM46
VCCSM47
VCCSM48
VCCSM49
VCCSM50
VCCSM51
VCCSM52
VCCSM53
VCCSM54
VCCSM55
VCCSM56
VCCSM57
VCCSM58
VCCSM59
VCCSM60
VCCSM61
VCCSM62
VCCSM63
VCCSM64

ALVISO_BGA1257

AM37
AH37
AP29
AD28
AD27
AC27
AP26
AN26
AM26
AL26
AK26
AJ26
AH26
AG26
AF26
AE26
AP25
AN25
AM25
AL25
AK25
AJ25
AH25
AG25
AF25
AE25
AE24
AE23
AE22
AE21
AE20
AE19
AE18
AE17
AE16
AE15
AE14
AP13
AN13
AM13
AL13
AK13
AJ13
AH13
AG13
AF13
AE13
AP12
AN12
AM12
AL12
AK12
AJ12
AH12
AG12
AF12
AE12
AD11
AC11
AB11
AB10
AB9
AP8
AM1
AE1

V2.5_DDR_CAP1
V2.5_DDR_CAP2
V2.5_DDR_CAP5

V2.5_DDR_CAP6
V2.5_DDR_CAP4
V2.5_DDR_CAP3

C230

V2.5_DDR_CAP1
V2.5_DDR_CAP2
V2.5_DDR_CAP5

Note : All VCCSM pin
shorted internally.

V2.5_DDR_CAP6
V2.5_DDR_CAP4
V2.5_DDR_CAP3

Note: Place near chip.

10U_0805_6.3V6M

C201

C236

1

1

2

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

C211

2

2

C248

10U_0805_6.3V6M

C235

+2.5V

C35

4

+VCCP

1

0.1U_0402_16V4Z

0.1U_0402_16V4Z

C24

+2.5V

C198

0.1U_0402_16V4Z

1

2

1

C212

2

10U_0805_6.3V6M

+1.5VS

+1.5VS_DPLLA
+1.5VS_DPLLB

+1.5VS_HPLL
+1.5VS_MPLL

0.1U_0402_16V4Z

C202

2

0.1U_0402_16V4Z

1

1

2

0.1U_0402_16V4Z

1

2

1

+

2

0.1U_0402_16V4Z

1

2

1

C23

C192

2

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

C246

C239

1

1

2

2

@

330U_D2E_2.5VM

0.1U_0402_16V4Z

1

1

C199

C234

2

2

W=20 mils

T29

VCC0

R29

VCC1

N29

VCC2

M29

VCC3

K29

VCC4

J29

VCC5

V28

VCC6

U28

VCC7

T28

VCC8

R28

VCC9

P28

VCC10

N28

VCC11

M28

VCC12

L28

VCC13

K28

VCC14

J28

VCC15

H28

VCC16

G28

VCC17

V27

VCC18

U27

VCC19

T27

VCC20

R27

VCC21

P27

VCC22

N27

VCC23

M27

VCC24

L27

VCC25

K27

VCC26

J27

VCC27

H27

VCC28

K26

VCC29

H26

VCC30

K25

VCC31

J25

VCC32

K24

VCC33

K23

VCC34

K22

VCC35

K21

VCC36

W20

VCC37

U20

VCC38

T20

VCC39

K20

VCC40

V19

VCC41

U19

VCC42

K19

VCC43

W18

VCC44

V18

VCC45

T18

VCC46

K18

VCC47

K17

VCC48

AC1

VCCD_HMPLL1

AC2

VCCD_HMPLL2

B23

VCCA_DPLLA

C35

VCCA_DPLLB

AA1

VCCA_HPLL

AA2

VCCA_MPLL

3

POWER

VCCA_TVDACA0
VCCA_TVDACA1
VCCA_TVDACB0
VCCA_TVDACB1
VCCA_TVDACC0
VCCA_TVDACC1

VCCA_TVBG
VSSA_TVBG

VCCD_TVDAC

VCCDQ_TVDAC

VCCD_LVDS0
VCCD_LVDS1
VCCD_LVDS2

VCCA_LVDS

VCCHV0
VCCHV1
VCCHV2

VCCTX_LVDS0
VCCTX_LVDS1
VCCTX_LVDS2

VCCA_SM0
VCCA_SM1
VCCA_SM2
VCCA_SM3

VCC3G0
VCC3G1
VCC3G2
VCC3G3
VCC3G4
VCC3G5
VCC3G6

VCCA_3GPLL0
VCCA_3GPLL1
VCCA_3GPLL2

VCCA_3GBG
VSSA_3GBG

VCC_SYNC

VCCA_CRTDAC0
VCCA_CRTDAC1

VSSA_CRTDAC

ALVISO_BGA1257

U5E

F17
E17
D18
C18
F18
E18

H18
G18

D19
H17

B26
B25
A25

A35
B22

B21
A21

B28
A28
A27

AF20
AP19
AF19
AF18

AE37
W37
U37
R37
N37
L37
J37

Y29
Y28
Y27

F37
G37

H20
F19

E19
G19

1

C225

2

0.1U_0402_16V4Z

+1.5VS

+2.5VS
+2.5VS

+2.5VS

4.7U_0805_10V4Z

1

C222

C44

2

0.1U_0402_16V4Z

+2.5VS_CRT_DAC

C221

0.1U_0402_16V4Z

+3VS

1

2

C227

0.022U_0402_16V7K

1

1

C224

2

2

C226

C218

0.022U_0402_16V7K

0.1U_0402_16V4Z

C196

1

+

2

100U_D2_6.3VM

1 2

0_0603_5%

1

1

2

2

C220

0.022U_0402_16V7K

0.1U_0402_16V4Z

1

1

2

2

+1.5VS_PCIE

1

+

C16

2

C28

220U_D2_4VM

R19

Route VSSA3GBG gnd from GMCH to
decoupling cap ground lead and
then connect to the gnd plane.

CRTDAC: Route caps within
250mil of Alviso. Route FB
within 3" of Alviso.

Route VSSACRTDAC gnd from GMCH to
decouplin g cap ground lead and then
connect to the gnd plane.

2

Route VSSATVBG gnd from GMCH to
decoupling cap ground lead and
then connect to the gnd plane.

1

1

2

2

C228 0.022U_0402_16V7K

C195

0.1U_0402_16V4Z

1

C17

2

10U_0805_6.3V6M

10U_0805_6.3V6M

+2.5VS

1

+1.5VS

1

1

2

2

C200

+1.5VS

0.1U_0402_16V4Z
C203 0.022U_0402_16V7K

1

1

C216

2

2

C249

0.1U_0402_16V4Z
C204 0.022U_0402_16V7K

1

2

1

C193

2

0.1U_0402_16V4Z

1

2

C194

10U_0805_6.3V6M

0.1U_0402_16V4Z

1

C214

2

R13

0.5_0805_1%

1 2

1

2

0.1U_0402_16V4Z

C215

3GRLL_R

1

2

+2.5VS+2.5VS

10U_0805_6.3V6M

1

1

C182

2

2

0.01U_0402_16V7K

L7

BLM18PG600SN1_0603

L1

BLM18PG600SN1_0603

L3

BLM18PG600SN1_0603

L2

CHB1608U301_0603

C20

0.1U_0402_16V4Z

C185

12

0.1U_0402_16V4Z

12

12

12

1

2

+1.5VS+1.5VS_3GPLL

C21

1

2

0.1U_0402_16V4Z

+2.5VS+2.5VS_3GBG

+2.5VS

1

C38

2

10U_0805_6.3V6M

+1.5VS

C18

0.1U_0402_16V4Z

1

C19

0.1U_0402_16V4Z

2

1

C40

2

0.1U_0402_16V4Z

+1.5VS+1.5VS_DDRDLL

1

C243

2

1

2

0.1U_0402_16V4Z

CHB1608U301_0603

+1.5VS

A A

1 2

C188

0.1U_0402_16V4Z

330U_D2E_2.5VM

1

C186

1

+

2

2

5

+1.5VS

CHB1608U301_0603

1 2

+1.5VS_DPLLB

L5

+1.5VS_HPLL

L9

C73

0.1U_0402_16V4Z

330U_D2E_2.5VM

1

C250

1

+

2

2

+1.5VS

4

CHB1608U301_0603

1 2

+1.5VS_MPLL

L8

1

1

+

C242

C255

2

2

0.1U_0402_16V4Z

330U_D2E_2.5VM

Compal Electronics, Inc.

Alviso(4 of 5)

LA-2591

1

0.1

of

10 43Monday, October 11, 2004

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

Title

Size Document Number Rev
Custom

Date: Sheet

5

4

3

2

1

D D

C C

B B

A A

+VCCP

W12

W13

AA12
AA13

W14

AA14
AB14

W15

AA15
AB15

W16

AA16
AB16

AA17
AB17
AA18
AB18
AA19
AB19
AA20
AB20

AA21
AB21

AA22
AB22

AA23
AB23

AA24
AB24

AA25
AB25

AA26
AB26

W25

W26

L12
M12
N12

P12
R12

T12
U12

V12

L13
M13
N13

P13
R13

T13
U13

V13

Y12

Y13

L14
M14
N14

P14
R14

T14
U14

V14

Y14

L15
M15
N15

P15
R15

T15
U15

V15

Y15

L16
M16
N16

P16
R16

T16
U16

V16

Y16

R17

Y17

R21

Y21

Y22

Y23

Y24

Y25

Y26

V25

L26
M26
N26

P26
R26

T26
U26

V26

VTT_NCTF17
VTT_NCTF16
VTT_NCTF15
VTT_NCTF14
VTT_NCTF13
VTT_NCTF12
VTT_NCTF11
VTT_NCTF10
VTT_NCTF9
VTT_NCTF8
VTT_NCTF7
VTT_NCTF6
VTT_NCTF5
VTT_NCTF4
VTT_NCTF3
VTT_NCTF2
VTT_NCTF1
VTT_NCTF0

VSS_NCTF68
VSS_NCTF67
VSS_NCTF66
VSS_NCTF65
VSS_NCTF64
VSS_NCTF63
VSS_NCTF62
VSS_NCTF61
VSS_NCTF60
VSS_NCTF59
VSS_NCTF58
VSS_NCTF57
VSS_NCTF56
VSS_NCTF55
VSS_NCTF54
VSS_NCTF53
VSS_NCTF52
VSS_NCTF51
VSS_NCTF50
VSS_NCTF49
VSS_NCTF48
VSS_NCTF47
VSS_NCTF46
VSS_NCTF45
VSS_NCTF44
VSS_NCTF43
VSS_NCTF42
VSS_NCTF41
VSS_NCTF40
VSS_NCTF39
VSS_NCTF38
VSS_NCTF37
VSS_NCTF36
VSS_NCTF35
VSS_NCTF34
VSS_NCTF33
VSS_NCTF32
VSS_NCTF31
VSS_NCTF30
VSS_NCTF29
VSS_NCTF28
VSS_NCTF27
VSS_NCTF26
VSS_NCTF25
VSS_NCTF24
VSS_NCTF23
VSS_NCTF22
VSS_NCTF21
VSS_NCTF20
VSS_NCTF19
VSS_NCTF18
VSS_NCTF17
VSS_NCTF16
VSS_NCTF15
VSS_NCTF14
VSS_NCTF13
VSS_NCTF12
VSS_NCTF11
VSS_NCTF10
VSS_NCTF9
VSS_NCTF8
VSS_NCTF7
VSS_NCTF6
VSS_NCTF5
VSS_NCTF4
VSS_NCTF3
VSS_NCTF2
VSS_NCTF1
VSS_NCTF0

VCC_NCTF10
VCC_NCTF9
VCC_NCTF8
VCC_NCTF7
VCC_NCTF6
VCC_NCTF5
VCC_NCTF4
VCC_NCTF3
VCC_NCTF2
VCC_NCTF1
VCC_NCTF0

5

VCCSM_NCTF31
VCCSM_NCTF30
VCCSM_NCTF29
VCCSM_NCTF28
VCCSM_NCTF27
VCCSM_NCTF26
VCCSM_NCTF25
VCCSM_NCTF24
VCCSM_NCTF23
VCCSM_NCTF22
VCCSM_NCTF21
VCCSM_NCTF20
VCCSM_NCTF19
VCCSM_NCTF18
VCCSM_NCTF17
VCCSM_NCTF16
VCCSM_NCTF15
VCCSM_NCTF14
VCCSM_NCTF13
VCCSM_NCTF12
VCCSM_NCTF11
VCCSM_NCTF10

VCCSM_NCTF9
VCCSM_NCTF8
VCCSM_NCTF7
VCCSM_NCTF6
VCCSM_NCTF5
VCCSM_NCTF4
VCCSM_NCTF3
VCCSM_NCTF2
VCCSM_NCTF1
VCCSM_NCTF0

VCC_NCTF78
VCC_NCTF77
VCC_NCTF76
VCC_NCTF75
VCC_NCTF74
VCC_NCTF73
VCC_NCTF72
VCC_NCTF71
VCC_NCTF70

NCTF

VCC_NCTF69
VCC_NCTF68
VCC_NCTF67
VCC_NCTF66
VCC_NCTF65
VCC_NCTF64
VCC_NCTF63
VCC_NCTF62
VCC_NCTF61
VCC_NCTF60
VCC_NCTF59
VCC_NCTF58
VCC_NCTF57
VCC_NCTF56
VCC_NCTF55
VCC_NCTF54
VCC_NCTF53
VCC_NCTF52
VCC_NCTF51
VCC_NCTF50
VCC_NCTF49
VCC_NCTF48
VCC_NCTF47
VCC_NCTF46
VCC_NCTF45
VCC_NCTF44
VCC_NCTF43
VCC_NCTF42
VCC_NCTF41
VCC_NCTF40
VCC_NCTF39
VCC_NCTF38
VCC_NCTF37
VCC_NCTF36
VCC_NCTF35
VCC_NCTF34
VCC_NCTF33
VCC_NCTF32
VCC_NCTF31
VCC_NCTF30
VCC_NCTF29
VCC_NCTF28
VCC_NCTF27
VCC_NCTF26
VCC_NCTF25
VCC_NCTF24
VCC_NCTF23
VCC_NCTF22
VCC_NCTF21
VCC_NCTF20
VCC_NCTF19
VCC_NCTF18
VCC_NCTF17
VCC_NCTF16
VCC_NCTF15
VCC_NCTF14
VCC_NCTF13
VCC_NCTF12
VCC_NCTF11

ALVISO_BGA1257

U5H

+2.5V

AB12
AC12
AD12
AB13
AC13
AD13
AC14
AD14
AC15
AD15
AC16
AD16
AC17
AD17
AC18
AD18
AC19
AD19
AC20
AD20
AC21
AD21
AC22
AD22
AC23
AD23
AC24
AD24
AC25
AD25
AC26
AD26

L17

+VCCP
M17
N17

P17
T17
U17
V17
W17
L18
M18
N18
P18
R18
Y18
L19
M19
N19
P19
R19
Y19
L20
M20
N20
P20
R20
Y20
L21
M21
N21
P21
T21
U21
V21
W21
L22
M22
N22
P22
R22
T22
U22
V22
W22
L23
M23
N23
P23
R23
T23
U23
V23
W23
L24
M24
N24
P24
R24
T24
U24
V24
W24
L25
M25
N25
P25
R25
T25
U25

4

AA10

AD2
AE2
AH2
AL2
AN2

AA3
AB3
AC3

AF4
AN4

AL5
AP5

AA6
AC6
AE6

AA7
AG7
AK7
AN7

AL8

AA9
AC9
AE9
AH9
AN9
D10

Y10

H11
Y11

Y1
D2
G2

J2

L2
P2
T2
V2

A3
C3

AJ3

C4
H4

L4
P4
U4
Y4

E5

W5

B6

J6

L6
P6
T6

AJ6

G7
V7

C8
E8

L8
P8
Y8

A9
H9
K9
T9
V9

L10

F11

VSS271
VSS270
VSS269
VSS268
VSS260
VSS259
VSS258
VSS257
VSS256
VSS255
VSS254
VSS253
VSS252
VSS251
VSS250
VSS249
VSS248
VSS247
VSS246
VSS245
VSS244
VSS243
VSS242
VSS241
VSS240
VSS239
VSS238
VSS237
VSS236
VSS235
VSS234
VSS233
VSS232
VSS231
VSS230
VSS229
VSS228
VSS227
VSS226
VSS225
VSS224
VSS223
VSS222
VSS221
VSS220
VSS219
VSS218
VSS217
VSS216
VSS215
VSS214
VSS213
VSS212
VSS211
VSS210
VSS209
VSS208
VSS207
VSS206
VSS205
VSS204
VSS203
VSS202
VSS201
VSS200
VSS199
VSS198
VSS197
VSS196

ALVISO_BGA1257

VSS

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

VSSALVDS

VSS195
VSS194
VSS193
VSS192
VSS191
VSS190
VSS189
VSS188
VSS187
VSS186
VSS185
VSS184
VSS183
VSS182
VSS181
VSS180
VSS179
VSS178
VSS177
VSS176
VSS175
VSS174
VSS173
VSS172
VSS171
VSS170
VSS169
VSS168
VSS167
VSS166
VSS165
VSS164
VSS163
VSS162
VSS161
VSS160
VSS159
VSS158
VSS157
VSS156
VSS155
VSS154
VSS153
VSS152
VSS151
VSS150
VSS149
VSS148
VSS147
VSS146
VSS145
VSS144
VSS143
VSS142
VSS141
VSS140
VSS139
VSS138
VSS137
VSS136
VSS135
VSS134
VSS133
VSS132
VSS131
VSS130

U5I

B36
AA11

AF11
AG11
AJ11
AL11
AN11
B12
D12
J12
A14
B14
F14
J14
K14
AG14
AJ14
AL14
AN14
C15
K15
A16
D16
H16
K16
AL16
C17
G17
AF17
AJ17
AN17
A18
B18
U18
AL18
C19
H19
J19
T19
W19
AG19
AN19
A20
D20
E20
F20
G20
V20
AK20
C21
F21
AF21
AN21
A22
D22
E22
J22
AH22
AL22
H23
AF23
B24
D24
F24
J24
AG24
AJ24

AL24

VSS267

AN24

VSS266

A26

VSS265

E26

VSS264

G26

VSS263

J26

VSS262

B27

VSS261

E27

VSS129

G27

VSS128

W27

VSS127

AA27

VSS126

AB27

VSS125
VSS124
VSS123
VSS122
VSS121
VSS120
VSS119
VSS118
VSS117
VSS116
VSS115
VSS114
VSS113
VSS112
VSS111
VSS110
VSS109
VSS108
VSS107
VSS106
VSS105
VSS104
VSS103
VSS102
VSS101
VSS100
VSS99
VSS98
VSS97
VSS96
VSS95
VSS94
VSS93
VSS92
VSS91
VSS90
VSS89
VSS88
VSS87
VSS86
VSS85
VSS84
VSS83
VSS82
VSS81
VSS80
VSS79
VSS78
VSS77
VSS76
VSS75
VSS74
VSS73
VSS72
VSS71
VSS70
VSS69
VSS68

VSS

Title

Size Document Number Rev
Custom

Date: Sheet

AF27
AG27

AJ27
AL27

AN27

E28

W28
AA28
AB28
AC28

A29
D29
E29
F29
G29
H29

L29
P29
U29
V29

W29
AA29
AD29
AG29

AJ29

AM29

C30

Y30
AA30
AB30
AC30
AE30
AP30

D31

E31

F31

G31

H31

J31

K31

L31

M31

N31

P31

R31

T31

U31

V31

W31
AD31
AG31

AL31

A32
C32

Y32
AA32
AB32

2

U5J

AC32

VSS67

AD32

VSS66

AJ32

VSS65

AN32

VSS64

D33

VSS63

E33

VSS62

F33

VSS61

G33

VSS60

H33

VSS59

J33

VSS58

K33

VSS57

L33

VSS56

M33

VSS55

N33

VSS54

P33

VSS53

R33

VSS52

T33

VSS51

U33

VSS50

V33

VSS49

W33

VSS48

AD33

VSS47

AF33

VSS46

AL33

VSS45

C34

VSS44

AA34

VSS43

AB34

VSS42

AC34

VSS41

AD34

VSS40

AH34

VSS39

AN34

VSS38

B35

VSS37

D35

VSS36

E35

VSS35

F35

VSS34

G35

VSS33

H35

VSS32

J35

VSS31

K35

VSS30

L35

VSS29

M35

VSS28

N35

VSS27

P35

VSS26

R35

VSS25

T35

VSS24

U35

VSS23

V35

VSS22

W35

VSS21

Y35

VSS20

AE35

VSS19

C36

VSS18

AA36

VSS17

AB36

VSS16

AC36

VSS15

AD36

VSS14

AE36

VSS13

AF36

VSS12

AJ36

VSS11

AL36

VSS10

AN36

VSS9

E37

VSS8

H37

VSS7

K37

VSS6

M37

VSS5

P37

VSS4

T37

VSS3

V37

VSS2

Y37

VSS1

AG37

VSS0

ALVISO_BGA1257

Compal Electronics, Inc.

Alviso(5 of 5)

LA-2591

1

0.1

of

11 43Monday, October 11, 2004

A

DDR_A_D[0..63]<8>

DDR_A_DQS[0..7]<8>

1 1

2 2

3 3

4 4

DDR_A_D[0..63]
DDR_A_DM[0..7] DDR_A_MA[0..13]
DDR_A_DQS[0..7]

DDR_A_D0
DDR_A_D1
DDR_A_D4
DDR_A_D5

DDR_A_DM0
DDR_A_DQS0

DDR_A_D6
DDR_A_D2
DDR_A_D3
DDR_A_D7

DDR_A_D8
DDR_A_D13
DDR_A_D9
DDR_A_D12

DDR_A_DM1 DDR_DM1
DDR_A_DQS1 DDR_DQS1

DDR_A_D14
DDR_A_D15
DDR_A_D10
DDR_A_D11

DDR_A_D17
DDR_A_D16
DDR_A_D21
DDR_A_D20

DDR_A_DM2 DDR_DM2
DDR_A_DQS2 DDR_DQS2

DDR_A_D19
DDR_A_D18
DDR_A_D22
DDR_A_D23

DDR_A_D24
DDR_A_D25
DDR_A_D29
DDR_A_D26

DDR_A_DQS3 DDR_DQS3
DDR_A_DM3 DDR_DM3

DDR_A_D28
DDR_A_D30
DDR_A_D31
DDR_A_D27

DDR_A_D36
DDR_A_D37
DDR_A_D33
DDR_A_D32

DDR_A_DQS4 DDR_DQS4
DDR_A_DM4 DDR_DM4

DDR_A_D38
DDR_A_D39
DDR_A_D35
DDR_A_D34

DDR_A_D45
DDR_A_D44
DDR_A_D41
DDR_A_D40

DDR_A_DQS5 DDR_DQS5
DDR_A_DM5 DDR_DM5

DDR_A_D46
DDR_A_D47
DDR_A_D43
DDR_A_D42

DDR_A_D49
DDR_A_D52
DDR_A_D53
DDR_A_D48

DDR_A_DM6 DDR_DM6
DDR_A_DQS6

DDR_A_D54
DDR_A_D55
DDR_A_D50
DDR_A_D51

DDR_A_D61
DDR_A_D60
DDR_A_D56
DDR_A_D57

DDR_A_DM7 DDR_DM7
DDR_A_DQS7 DDR_DQS7

DDR_A_D62
DDR_A_D59
DDR_A_D63
DDR_A_D58

A

RP22

4 5
3 6
2 7
1 8

1 2

R118 10_0402_5%

1 2

RP23

R111 10_0402_5%

4 5
3 6
2 7
1 8

RP24

4 5
3 6
2 7
1 8

1 2

R121 10_0402_5%

1 2

R123 10_0402_5%

RP25

4 5
3 6
2 7
1 8

RP28

4 5
3 6
2 7
1 8

1 2

R127 10_0402_5%

1 2

R126 10_0402_5%

RP29

4 5
3 6
2 7
1 8

RP30

4 5
3 6
2 7
1 8

1 2

R129 10_0402_5%

1 2

RP33

R130 10_0402_5%

4 5
3 6
2 7
1 8

RP34

4 5
3 6
2 7
1 8

1 2

R144 10_0402_5%

1 2

R145 10_0402_5%

RP35

4 5
3 6
2 7
1 8

RP36

4 5
3 6
2 7
1 8

1 2

R155 10_0402_5%

1 2

R150 10_0402_5%

RP37

4 5
3 6
2 7
1 8

RP38

4 5
3 6
2 7
1 8

1 2

R161 10_0402_5%

1 2

R162 10_0402_5%

RP39

4 5
3 6
2 7
1 8

RP40

4 5
3 6
2 7
1 8

1 2

R171 10_0402_5%

1 2

R166 10_0402_5%

RP41

4 5
3 6
2 7
1 8

B

DDR_D[0..63]

DDR_DM[0..7]

DDR_DQS[0..7]

10_1206_8P4R_5%

10_1206_8P4R_5%

10_1206_8P4R_5%

10_1206_8P4R_5%

10_1206_8P4R_5%

10_1206_8P4R_5%

10_1206_8P4R_5%

10_1206_8P4R_5%

10_1206_8P4R_5%

10_1206_8P4R_5%

10_1206_8P4R_5%

10_1206_8P4R_5%

10_1206_8P4R_5%

10_1206_8P4R_5%

10_1206_8P4R_5%

10_1206_8P4R_5%

B

DDR_D0
DDR_D1
DDR_D4
DDR_D5

DDR_DM0
DDR_DQS0

DDR_D6
DDR_D2
DDR_D3
DDR_D7

DDR_D8
DDR_D13
DDR_D9
DDR_D12

DDR_D14
DDR_D15
DDR_D10
DDR_D11

DDR_D17
DDR_D16
DDR_D21
DDR_D20

DDR_D19
DDR_D18
DDR_D22
DDR_D23

DDR_D24
DDR_D25
DDR_D29
DDR_D26

DDR_D28
DDR_D30
DDR_D31
DDR_D27

DDR_D36
DDR_D37
DDR_D33
DDR_D32

DDR_D38
DDR_D39
DDR_D35
DDR_D34

DDR_D45
DDR_D44
DDR_D41
DDR_D40

DDR_D46
DDR_D47
DDR_D43
DDR_D42

DDR_D49
DDR_D52
DDR_D53
DDR_D48

DDR_DQS6
DDR_D54

DDR_D55
DDR_D50
DDR_D51

DDR_D61
DDR_D60
DDR_D56
DDR_D57

DDR_D62
DDR_D59
DDR_D63
DDR_D58

DDR_D[0..63] <13>

DDR_DM[0..7] <13>

DDR_DQS[0..7] <13>

DDR_CLK1<7>
DDR_CLK1#<7>

DDR_CLK0<7>
DDR_CLK0#<7>

DDR_CKE0<7>

DDR_A_BS#0<8>
DDR_A_BS#1<8>

DDR_SCS#0<7>

DDR_A_RAS#<8>
DDR_A_CAS#<8>
DDR_A_WE#<8>

+1.25VS

RP26

4 5
3 6
2 7
1 8

RP27

4 5
3 6
2 7
1 8

RP32

4 5
3 6
2 7
1 8

RP31

4 5
3 6
2 7
1 8

1 2

R124 56_0402_5%

1 2

R122 56_0402_5%

1 2

R139 56_0402_5%

1 2

R119 56_0402_5%

1 2

R135 56_0402_5%

C

DDR_A_MA[0..13]<8>DDR_A_DM[0..7]<8>

56_1206_8P4R_5%

56_1206_8P4R_5%

56_1206_8P4R_5%

56_1206_8P4R_5%

C

DDR_CLK1
DDR_CLK1#

DDR_CLK0
DDR_CLK0#

DDR_CKE0

DDR_A_BS#0
DDR_A_BS#1

DDR_SCS#0

DDR_A_RAS#
DDR_A_CAS#
DDR_A_WE#

DDR_A_BS#0

DDR_A_MA12

DDR_A_BS#1

DDR_A_MA10

DDR_A_MA1
DDR_A_MA2
DDR_A_MA5
DDR_A_MA3

DDR_A_MA4
DDR_A_MA6
DDR_A_MA0
DDR_A_MA7

DDR_A_MA8

DDR_A_MA9
DDR_A_MA11
DDR_A_MA13

DDR_CKE0

DDR_SCS#0

DDR_A_WE#
DDR_A_RAS#
DDR_A_CAS#

D

SDREF<7,13>

C25

0.1U_0402_16V4Z

Close
pin49

0.1U_0402_16V4Z

Close
pin49

D

E

F

+2.5V

U2

16

LDQS

20

LDM

2

DQ0

4

DQ1

5

DQ2

7

DQ3

8

DQ4

10

DQ5

11

DQ6

13

DQ7

51

UDQS

47

UDM

54

DQ8

56

DQ9

57

DQ10

59

DQ11

60

DQ12

62

DQ13

63

DQ14

65

DQ15

49

VREF

29

A0

30

A1

31

A2

32

A3

35

A4

36

A5

37

A6

38

A7

39

A8

40

A9

28

AP/A10

41

A11

42

A12

HY5DU121622A(L)T-J_TSOPII66

VDD0
VDD1

VDD2
VDDQ0
VDDQ1
VDDQ2
VDDQ3
VDDQ4

RAS#

CAS#

VSSQ0
VSSQ1
VSSQ2
VSSQ3
VSSQ4

VSS0
VSS1
VSS2

CKE

WE#

NC0
NC1
NC2
NC3
NC4
NC5
NC6

CK#

BA0
BA1

CS#

1

1 2

C4 0.1U_0402_16V4Z

18
33

1 2

C137 0.1U_0402_16V4Z

3
9

1 2

C27 0.1U_0402_16V4Z

15
55

1 2

C26 0.1U_0402_16V4Z

61
14

DDR_A_MA13

17
19
25
43
50
53

DDR_CLK0

45

CK

DDR_CLK0#

46

DDR_CKE0

44

DDR_A_BS#0

26

DDR_A_BS#1

27
24

23
22
21

6
12
52
58
64
34
48
66

DDR_SCS#0DDR_A_MA0
DDR_A_RAS#
DDR_A_CAS#
DDR_A_WE#

C56

0.1U_0402_16V4Z

Close
pin49

SDREF

1

2

DDR_DQS0
DDR_DM0
DDR_D0
DDR_D1
DDR_D4
DDR_D5
DDR_D6
DDR_D2
DDR_D3
DDR_D7

DDR_DQS1
DDR_DM1
DDR_D8
DDR_D13
DDR_D9
DDR_D12
DDR_D14
DDR_D15
DDR_D10
DDR_D11

DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12

+2.5V

DDR_DQS4
DDR_DM4
DDR_D36
DDR_D37
DDR_D33
DDR_D32
DDR_D38
DDR_D39
DDR_D35
DDR_D34

DDR_DQS5
DDR_DM5
DDR_D45
DDR_D44
DDR_D41
DDR_D40
DDR_D46
DDR_D47
DDR_D43
DDR_D42

SDREF

DDR_A_MA0

1

DDR_A_MA1
DDR_A_MA2

C41

DDR_A_MA3

2

DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

U4

16

LDQS

20

LDM

2

DQ0

4

DQ1

5

DQ2

7

DQ3

8

DQ4

10

DQ5

11

DQ6

13

DQ7

51

UDQS

47

UDM

54

DQ8

56

DQ9

57

DQ10

59

DQ11

60

DQ12

62

DQ13

63

DQ14

65

DQ15

49

VREF

29

A0

30

A1

31

A2

32

A3

35

A4

36

A5

37

A6

38

A7

39

A8

40

A9

28

AP/A10

41

A11

42

A12

HY5DU121622A(L)T-J_TSOPII66

VDD0

VDD1

VDD2
VDDQ0
VDDQ1
VDDQ2
VDDQ3
VDDQ4

RAS#

CAS#

VSSQ0
VSSQ1
VSSQ2
VSSQ3
VSSQ4

VSS0
VSS1
VSS2

E

NC0
NC1
NC2
NC3
NC4
NC5
NC6

CK#
CKE

BA0
BA1

CS#

WE#

1

1 2

C30 0.1U_0402_16V4Z

18
33

1 2

C29 0.1U_0402_16V4Z

3
9

1 2

C43 0.1U_0402_16V4Z

15
55

1 2

C42 0.1U_0402_16V4Z

61
14

DDR_A_MA13

17
19
25
43
50
53

DDR_CLK1

45

CK

DDR_CLK1#

46

DDR_CKE0

44

DDR_A_BS#0

26

DDR_A_BS#1

27
24

23
22
21

6
12
52
58
64
34
48
66

DDR_SCS#0
DDR_A_RAS#
DDR_A_CAS#
DDR_A_WE#

C74

0.1U_0402_16V4Z

Close
pin49

F

1

2

SDREF

1

2

SDREF

DDR_DQS2
DDR_DM2
DDR_D17
DDR_D16
DDR_D21
DDR_D20
DDR_D19
DDR_D18
DDR_D22
DDR_D23

DDR_DQS3
DDR_DM3
DDR_D24
DDR_D25
DDR_D29
DDR_D26
DDR_D28
DDR_D30
DDR_D31
DDR_D27

DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12

DDR_DQS6
DDR_DM6
DDR_D49
DDR_D52
DDR_D53
DDR_D48
DDR_D54
DDR_D55
DDR_D50
DDR_D51

DDR_DQS7
DDR_DM7
DDR_D61
DDR_D60
DDR_D56
DDR_D57
DDR_D62
DDR_D59
DDR_D63
DDR_D58

DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12

G

H

+2.5V

U3

16

LDQS

20

LDM

2

DQ0

4

DQ1

5

DQ2

7

DQ3

8

DQ4

10

DQ5

11

DQ6

13

DQ7

51

UDQS

47

UDM

54

DQ8

56

DQ9

57

DQ10

59

DQ11

60

DQ12

62

DQ13

63

DQ14

65

DQ15

49

VREF

29

A0

30

A1

31

A2

32

A3

35

A4

36

A5

37

A6

38

A7

39

A8

40

A9

28

AP/A10

41

A11

42

A12

HY5DU121622A(L)T-J_TSOPII66

VDD0
VDD1

VDD2
VDDQ0
VDDQ1
VDDQ2
VDDQ3
VDDQ4

NC0
NC1
NC2
NC3
NC4
NC5
NC6

CK#
CKE

BA0
BA1

CS#
RAS#
CAS#

WE#

VSSQ0
VSSQ1
VSSQ2
VSSQ3
VSSQ4

VSS0
VSS1
VSS2

1

1 2

C46 0.1U_0402_16V4Z

18
33

1 2

C47 0.1U_0402_16V4Z

3
9

1 2

C58 0.1U_0402_16V4Z

15
55

1 2

C57 0.1U_0402_16V4Z

61
14

DDR_A_MA13

17
19
25
43
50
53

DDR_CLK0

45

CK

DDR_CLK0#

46

DDR_CKE0

44

DDR_A_BS#0

26

DDR_A_BS#1

27

DDR_SCS#0

24

DDR_A_RAS#

23

DDR_A_CAS#

22

DDR_A_WE#

21
6

12
52
58
64
34
48
66

+2.5V

U7

16

LDQS

20

LDM

2

DQ0

4

DQ1

5

DQ2

7

DQ3

8

DQ4

10

DQ5

11

DQ6

13

DQ7

51

UDQS

47

UDM

54

DQ8

56

DQ9

57

DQ10

59

DQ11

60

DQ12

62

DQ13

63

DQ14

65

DQ15

49

VREF

29

A0

30

A1

31

A2

32

A3

35

A4

36

A5

37

A6

38

A7

39

A8

40

A9

28

AP/A10

41

A11

42

A12

HY5DU121622A(L)T-J_TSOPII66

Title

Size Document Number Rev

LA-2591

Date: Sheet

G

1
18
33
3
9
15
55
61

14
17
19
25
43
50
53

45
46
44

26
27

24
23
22
21

6
12
52
58
64
34
48
66

DDR_A_MA13

DDR_CLK1

DDR_CLK1#

DDR_CKE0
DDR_A_BS#0

DDR_A_BS#1

DDR_SCS#0
DDR_A_RAS#
DDR_A_CAS#
DDR_A_WE#

1 2

C62 0.1U_0402_16V4Z

1 2

C61 0.1U_0402_16V4Z

1 2

C76 0.1U_0402_16V4Z

1 2

C75 0.1U_0402_16V4Z

VDD0
VDD1

VDD2
VDDQ0
VDDQ1
VDDQ2
VDDQ3
VDDQ4

NC0
NC1
NC2
NC3
NC4
NC5
NC6

CK#
CKE

BA0
BA1

CS#
RAS#
CAS#

WE#

VSSQ0
VSSQ1
VSSQ2
VSSQ3
VSSQ4

VSS0
VSS1
VSS2

CK

Compal Electronics, Inc.

DDR-SODIMM SLOT0

of

12 43Monday, October 11, 2004

H

0.1

A

B

C

D

E

+2.5V

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200

D

DDR_D2
DDR_D6

DDR_DM0
DDR_D7

DDR_D3
DDR_D13

DDR_D8
DDR_DM1

DDR_D12
DDR_D9

DDR_D18
DDR_D19

DDR_DM2
DDR_D23

DDR_D22
DDR_D25

DDR_D24
DDR_DM3

DDR_D26
DDR_D29

DDR_B_MA11
DDR_B_MA8

DDR_B_MA6
DDR_B_MA4
DDR_B_MA2DDR_B_MA3
DDR_B_MA0

DDR_B_BS#1
DDR_B_RAS#
DDR_B_CAS#DDR_B_WE#
DDR_SCS#3

DDR_D39
DDR_D38

DDR_DM4
DDR_D34

DDR_D35
DDR_D44

DDR_D45
DDR_DM5

DDR_D40
DDR_D41

DDR_D55
DDR_D54

DDR_DM6
DDR_D51

DDR_D50
DDR_D60

DDR_D61
DDR_DM7

DDR_D57
DDR_D56

+3VS

SDREF

1

C135

0.1U_0402_16V4Z

2

SDREF <7,12>

DDR_CKE2 <7>

DDR_B_BS#1 <8>
DDR_B_RAS# <8>
DDR_B_CAS# <8>

DDR_SCS#3 <7>

DDR_CLK4# <7>

DDR_CLK4 <7>

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

DDR-SODIMM SLOT1

LA-2591

E

13 43Monday, October 11, 2004

0.1

of

DDR_D1
DDR_D0

DDR_DQS0
DDR_D5

DDR_D4
DDR_D15

DDR_D14
DDR_DQS1

DDR_D11
DDR_D10

DDR_D16
DDR_D17

DDR_DQS2
DDR_D20

DDR_D21
DDR_D30

DDR_D28
DDR_DQS3

DDR_D27
DDR_D31

DDR_D37
DDR_D36

DDR_DQS4
DDR_D32

DDR_D33
DDR_D47

DDR_D46
DDR_DQS5

DDR_D42
DDR_D43

DDR_D52
DDR_D49

DDR_DQS6
DDR_D48

DDR_D53
DDR_D59

DDR_D62
DDR_DQS7

DDR_D58
DDR_D63

CK_SDATA

CK_SCLK

+3VS

C

+2.5V

JP18

1

VREF

3

VSS

5

DQ0

7

DQ1

9

VDD

11

DQS0

13

DQ2

15

VSS

17

DQ3

19

DQ8

21

VDD

23

DQ9

25

DQS1

27

VSS

29

DQ10

31

DQ11

33

VDD

35

CK0

37

CK0#

39

VSS

41

DQ16

43

DQ17

45

VDD

47

DQS2

49

DQ18

51

VSS

53

DQ19

55

DQ24

57

VDD

59

DQ25

61

DQS3

63

VSS

65

DQ26

67

DQ27

69

VDD

71

CB0

73

CB1

75

VSS

77

DQS8

79

CB2

81

VDD

83

CB3

85

DU

87

VSS

89

CK2

91

CK2#

93

VDD

95

CKE1

97

DU/A13

99

A12

101

A9

103

VSS

105

A7

107

A5

109

A3

111

A1

113

VDD

115

A10/AP

117

BA0

119

WE#

121

S0#

123

DU

125

VSS

127

DQ32

129

DQ33

131

VDD

133

DQS4

135

DQ34

137

VSS

139

DQ35

141

DQ40

143

VDD

145

DQ41

147

DQS5

149

VSS

151

DQ42

153

DQ43

155

VDD

157

VDD

159

VSS

161

VSS

163

DQ48

165

DQ49

167

VDD

169

DQS6

171

DQ50

173

VSS

175

DQ51

177

DQ56

179

VDD

181

DQ57

183

DQS7

185

VSS

187

DQ58

189

DQ59

191

VDD

193

SDA

195

SCL

197

VDD_SPD

199

VDD_ID

VSS

AMP_1565917-1

201

VREF

DQ4
DQ5
VDD
DM0
DQ6

DQ7

DQ12

VDD

DQ13

DM1

DQ14
DQ15

VDD
VDD

DQ20
DQ21

VDD
DM2

DQ22
DQ23

DQ28

VDD

DQ29

DM3

DQ30
DQ31

VDD

DM8
VDD

DU/RESET#

VDD
VDD

CKE0

DU/BA2

VDD

RAS#
CAS#

DQ36
DQ37

VDD
DM4

DQ38
DQ39

DQ44

VDD

DQ45

DM5

DQ46
DQ47

VDD

CK1#

DQ52
DQ53

VDD
DM6

DQ54
DQ55

DQ60

VDD

DQ61

DM7

DQ62
DQ63

VDD

VSS

202

VSS

VSS

VSS

VSS
VSS

VSS

VSS

CB4
CB5
VSS

CB6
CB7
VSS

VSS

A11
VSS

BA1

S1#
VSS

VSS

VSS

CK1
VSS

VSS

VSS

SA0
SA1
SA2

A8
A6

A4
A2
A0

DU

DU

+1.25VS

DDR_D1
DDR_D0
DDR_D5
DDR_D4

DDR_DM0
DDR_DQS0

DDR_D2

1 1

DDR_D6
DDR_D7
DDR_D3

DDR_D13

DDR_D8

DDR_D12

DDR_D9

DDR_DM1

DDR_D15
DDR_D14
DDR_D11
DDR_D10

DDR_D16
DDR_D17
DDR_D20
DDR_D21

DDR_D18
DDR_D19
DDR_D23

2 2

DDR_D22

DDR_D25
DDR_D24
DDR_D26
DDR_D29

DDR_D30
DDR_D28
DDR_D27
DDR_D31

DDR_D37
DDR_D36
DDR_D32
DDR_D33

DDR_D39
DDR_D38
DDR_D34
DDR_D35

3 3

DDR_D44
DDR_D45
DDR_D40
DDR_D41

DDR_D47
DDR_D46
DDR_D42
DDR_D43

DDR_D52
DDR_D49
DDR_D48
DDR_D53

DDR_D55
DDR_D54
DDR_D51
DDR_D50

4 4

DDR_D60
DDR_D61
DDR_D57
DDR_D56

DDR_D59
DDR_D62
DDR_D58
DDR_D63

DDR_DQS1

DDR_DM2
DDR_DQS2

DDR_DM3
DDR_DQS3

DDR_DM4
DDR_DQS4

DDR_DM5
DDR_DQS5

DDR_DM6
DDR_DQS6

DDR_DM7
DDR_DQS7

RP1

1 8
2 7
3 6
4 5

10_1206_8P4R_5%

1 2

R5 10_0402_5%

1 2

RP2

R6 10_0402_5%

4 5
3 6
2 7
1 8

10_1206_8P4R_5%

RP4

4 5
3 6
2 7
1 8

10_1206_8P4R_5%

1 2

R7 10_0402_5%

1 2

RP3

R8 10_0402_5%

1 8
2 7
3 6
4 5

10_1206_8P4R_5%

RP5

1 8
2 7
3 6
4 5

10_1206_8P4R_5%

1 2

R16 10_0402_5%

1 2

RP6

R15 10_0402_5%

4 5
3 6
2 7
1 8

10_1206_8P4R_5%

RP8

4 5
3 6
2 7
1 8

10_1206_8P4R_5%

1 2

R17 10_0402_5%

1 2

RP7

R18 10_0402_5%

1 8
2 7
3 6
4 5

10_1206_8P4R_5%

RP14

1 8
2 7
3 6
4 5

10_1206_8P4R_5%

1 2

R23 10_0402_5%

1 2

R26 10_0402_5%

RP15

4 5
3 6
2 7
1 8

10_1206_8P4R_5%

RP17

4 5
3 6
2 7
1 8

10_1206_8P4R_5%

1 2

R28 10_0402_5%

1 2

R29 10_0402_5%

RP16

1 8
2 7
3 6
4 5

10_1206_8P4R_5%

RP18

1 8
2 7
3 6
4 5

10_1206_8P4R_5%

1 2

R30 10_0402_5%

1 2

R31 10_0402_5%

RP19

4 5
3 6
2 7
1 8

10_1206_8P4R_5%

RP21

4 5
3 6
2 7
1 8

10_1206_8P4R_5%

1 2

R36 10_0402_5%

1 2

RP20

R39 10_0402_5%

1 8
2 7
3 6
4 5

10_1206_8P4R_5%

A

DDR_D[0..63]

DDR_DM[0..7]

DDR_DQS[0..7]

DDR_B_MA[0..13]<8>

+1.25VS

RP9

56_1206_8P4R_5%

RP10

56_1206_8P4R_5%

RP11

56_1206_8P4R_5%

RP12

56_1206_8P4R_5%

RP13

56_1206_8P4R_5%

1 2

R21 56_0402_5%

1 2

R20 56_0402_5%

1 2

R22 56_0402_5%

18
27
36
45

45
36
27
18

18
27
36
45

45
36
27
18

18
27
36
45

B

DDR_D[0..63] <12>
DDR_DM[0..7] <12>
DDR_DQS[0..7] <12>

DDR_B_MA[0..13]

DDR_CKE2
DDR_CKE3
DDR_B_MA13
DDR_B_MA12

DDR_B_MA11
DDR_B_MA9
DDR_B_MA7
DDR_B_MA8

DDR_B_MA6
DDR_B_MA5
DDR_B_MA3
DDR_B_MA4

DDR_B_MA2
DDR_B_MA1
DDR_B_MA10
DDR_B_MA0

DDR_B_BS#1
DDR_B_BS#0
DDR_SCS#2
DDR_SCS#3

DDR_B_WE#
DDR_B_RAS#
DDR_B_CAS#

DDR_CLK3<7>
DDR_CLK3#<7>

DDR_CKE3<7>

DDR_CKE3 DDR_CKE2
DDR_B_MA13
DDR_B_MA12
DDR_B_MA9

DDR_B_MA7
DDR_B_MA5

DDR_B_MA1
DDR_B_MA10

DDR_B_BS#0<8>
DDR_B_WE#<8>
DDR_SCS#2<7>

CK_SDATA<18>

CK_SCLK<18>

DDR_B_BS#0
DDR_SCS#2

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.